diff --git a/Common/sim/altera/altera_lnsim_components.vhd b/Common/sim/altera/altera_lnsim_components.vhd new file mode 100644 index 0000000..b3a95e3 --- /dev/null +++ b/Common/sim/altera/altera_lnsim_components.vhd @@ -0,0 +1,1621 @@ +-- Copyright (C) 1991-2010 Altera Corporation +-- This simulation model contains highly confidential and +-- proprietary information of Altera and is being provided +-- in accordance with and subject to the protections of the +-- applicable Altera Program License Subscription Agreement +-- which governs its use and disclosure. Your use of Altera +-- Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, +-- and any output files any of the foregoing (including device +-- programming or simulation files), and any associated +-- documentation or information are expressly subject to the +-- terms and conditions of the Altera Program License Subscription +-- Agreement, Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of simulating designs for +-- use exclusively in logic devices manufactured by Altera and sold +-- by Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. Altera products and +-- services are protected under numerous U.S. and foreign patents, +-- maskwork rights, copyrights and other intellectual property laws. +-- Altera assumes no responsibility or liability arising out of the +-- application or use of this simulation model. + +library ieee; +use ieee.std_logic_1164.all; + +package altera_lnsim_components is + +component altera_pll + generic( + reference_clock_frequency: string := "0 ps"; + fractional_vco_multiplier : string := "false"; + pll_type : string := "General"; + pll_subtype : string := "General"; + number_of_clocks: integer := 1; + operation_mode : string := "internal feedback"; + deserialization_factor: integer := 4; + data_rate : integer := 0; + sim_additional_refclk_cycles_to_lock: integer := 0; + output_clock_frequency0: string := "0 ps"; + phase_shift0 : string := "0 ps"; + duty_cycle0 : integer := 50; + output_clock_frequency1: string := "0 ps"; + phase_shift1 : string := "0 ps"; + duty_cycle1 : integer := 50; + output_clock_frequency2: string := "0 ps"; + phase_shift2 : string := "0 ps"; + duty_cycle2 : integer := 50; + output_clock_frequency3: string := "0 ps"; + phase_shift3 : string := "0 ps"; + duty_cycle3 : integer := 50; + output_clock_frequency4: string := "0 ps"; + phase_shift4 : string := "0 ps"; + duty_cycle4 : integer := 50; + output_clock_frequency5: string := "0 ps"; + phase_shift5 : string := "0 ps"; + duty_cycle5 : integer := 50; + output_clock_frequency6: string := "0 ps"; + phase_shift6 : string := "0 ps"; + duty_cycle6 : integer := 50; + output_clock_frequency7: string := "0 ps"; + phase_shift7 : string := "0 ps"; + duty_cycle7 : integer := 50; + output_clock_frequency8: string := "0 ps"; + phase_shift8 : string := "0 ps"; + duty_cycle8 : integer := 50; + output_clock_frequency9: string := "0 ps"; + phase_shift9 : string := "0 ps"; + duty_cycle9 : integer := 50; + output_clock_frequency10: string := "0 ps"; + phase_shift10 : string := "0 ps"; + duty_cycle10 : integer := 50; + output_clock_frequency11: string := "0 ps"; + phase_shift11 : string := "0 ps"; + duty_cycle11 : integer := 50; + output_clock_frequency12: string := "0 ps"; + phase_shift12 : string := "0 ps"; + duty_cycle12 : integer := 50; + output_clock_frequency13: string := "0 ps"; + phase_shift13 : string := "0 ps"; + duty_cycle13 : integer := 50; + output_clock_frequency14: string := "0 ps"; + phase_shift14 : string := "0 ps"; + duty_cycle14 : integer := 50; + output_clock_frequency15: string := "0 ps"; + phase_shift15 : string := "0 ps"; + duty_cycle15 : integer := 50; + output_clock_frequency16: string := "0 ps"; + phase_shift16 : string := "0 ps"; + duty_cycle16 : integer := 50; + output_clock_frequency17: string := "0 ps"; + phase_shift17 : string := "0 ps"; + duty_cycle17 : integer := 50; + + m_cnt_hi_div :integer := 1; + m_cnt_lo_div :integer := 1; + m_cnt_bypass_en :string := "false"; + m_cnt_odd_div_duty_en :string := "false"; + n_cnt_hi_div :integer := 1; + n_cnt_lo_div :integer := 1; + n_cnt_bypass_en :string := "false"; + n_cnt_odd_div_duty_en :string := "false"; + c_cnt_hi_div0 :integer := 1; + c_cnt_lo_div0 :integer := 1; + c_cnt_bypass_en0 :string := "false"; + c_cnt_in_src0 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en0 :string := "false"; + c_cnt_prst0 :integer := 1; + c_cnt_ph_mux_prst0 :integer := 0; + c_cnt_hi_div1 :integer := 1; + c_cnt_lo_div1 :integer := 1; + c_cnt_bypass_en1 :string := "false"; + c_cnt_in_src1 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en1 :string := "false"; + c_cnt_prst1 :integer := 1; + c_cnt_ph_mux_prst1 :integer := 0; + c_cnt_hi_div2 :integer := 1; + c_cnt_lo_div2 :integer := 1; + c_cnt_bypass_en2 :string := "false"; + c_cnt_in_src2 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en2 :string := "false"; + c_cnt_prst2 :integer := 1; + c_cnt_ph_mux_prst2 :integer := 0; + c_cnt_hi_div3 :integer := 1; + c_cnt_lo_div3 :integer := 1; + c_cnt_bypass_en3 :string := "false"; + c_cnt_in_src3 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en3 :string := "false"; + c_cnt_prst3 :integer := 1; + c_cnt_ph_mux_prst3 :integer := 0; + c_cnt_hi_div4 :integer := 1; + c_cnt_lo_div4 :integer := 1; + c_cnt_bypass_en4 :string := "false"; + c_cnt_in_src4 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en4 :string := "false"; + c_cnt_prst4 :integer := 1; + c_cnt_ph_mux_prst4 :integer := 0; + c_cnt_hi_div5 :integer := 1; + c_cnt_lo_div5 :integer := 1; + c_cnt_bypass_en5 :string := "false"; + c_cnt_in_src5 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en5 :string := "false"; + c_cnt_prst5 :integer := 1; + c_cnt_ph_mux_prst5 :integer := 0; + c_cnt_hi_div6 :integer := 1; + c_cnt_lo_div6 :integer := 1; + c_cnt_bypass_en6 :string := "false"; + c_cnt_in_src6 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en6 :string := "false"; + c_cnt_prst6 :integer := 1; + c_cnt_ph_mux_prst6 :integer := 0; + c_cnt_hi_div7 :integer := 1; + c_cnt_lo_div7 :integer := 1; + c_cnt_bypass_en7 :string := "false"; + c_cnt_in_src7 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en7 :string := "false"; + c_cnt_prst7 :integer := 1; + c_cnt_ph_mux_prst7 :integer := 0; + c_cnt_hi_div8 :integer := 1; + c_cnt_lo_div8 :integer := 1; + c_cnt_bypass_en8 :string := "false"; + c_cnt_in_src8 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en8 :string := "false"; + c_cnt_prst8 :integer := 1; + c_cnt_ph_mux_prst8 :integer := 0; + c_cnt_hi_div9 :integer := 1; + c_cnt_lo_div9 :integer := 1; + c_cnt_bypass_en9 :string := "false"; + c_cnt_in_src9 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en9 :string := "false"; + c_cnt_prst9 :integer := 1; + c_cnt_ph_mux_prst9 :integer := 0; + c_cnt_hi_div10 :integer := 1; + c_cnt_lo_div10 :integer := 1; + c_cnt_bypass_en10 :string := "false"; + c_cnt_in_src10 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en10 :string := "false"; + c_cnt_prst10 :integer := 1; + c_cnt_ph_mux_prst10 :integer := 0; + c_cnt_hi_div11 :integer := 1; + c_cnt_lo_div11 :integer := 1; + c_cnt_bypass_en11 :string := "false"; + c_cnt_in_src11 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en11 :string := "false"; + c_cnt_prst11 :integer := 1; + c_cnt_ph_mux_prst11 :integer := 0; + c_cnt_hi_div12 :integer := 1; + c_cnt_lo_div12 :integer := 1; + c_cnt_bypass_en12 :string := "false"; + c_cnt_in_src12 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en12 :string := "false"; + c_cnt_prst12 :integer := 1; + c_cnt_ph_mux_prst12 :integer := 0; + c_cnt_hi_div13 :integer := 1; + c_cnt_lo_div13 :integer := 1; + c_cnt_bypass_en13 :string := "false"; + c_cnt_in_src13 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en13 :string := "false"; + c_cnt_prst13 :integer := 1; + c_cnt_ph_mux_prst13 :integer := 0; + c_cnt_hi_div14 :integer := 1; + c_cnt_lo_div14 :integer := 1; + c_cnt_bypass_en14 :string := "false"; + c_cnt_in_src14 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en14 :string := "false"; + c_cnt_prst14 :integer := 1; + c_cnt_ph_mux_prst14 :integer := 0; + c_cnt_hi_div15 :integer := 1; + c_cnt_lo_div15 :integer := 1; + c_cnt_bypass_en15 :string := "false"; + c_cnt_in_src15 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en15 :string := "false"; + c_cnt_prst15 :integer := 1; + c_cnt_ph_mux_prst15 :integer := 0; + c_cnt_hi_div16 :integer := 1; + c_cnt_lo_div16 :integer := 1; + c_cnt_bypass_en16 :string := "false"; + c_cnt_in_src16 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en16 :string := "false"; + c_cnt_prst16 :integer := 1; + c_cnt_ph_mux_prst16 :integer := 0; + c_cnt_hi_div17 :integer := 1; + c_cnt_lo_div17 :integer := 1; + c_cnt_bypass_en17 :string := "false"; + c_cnt_in_src17 :string := "ph_mux_clk"; + c_cnt_odd_div_duty_en17 :string := "false"; + c_cnt_prst17 :integer := 1; + c_cnt_ph_mux_prst17 :integer := 0; + pll_vco_div :integer := 0; + pll_bwctrl :integer := 0; + pll_cp_current :integer := 0; + pll_fractional_division :integer := 0; + pll_fractional_cout :integer := 24; + pll_dsm_out_sel :string := "1st_order"; + pll_output_clk_frequency :string := "0 MHz"; + refclk1_frequency :string := "0 MHz"; + pll_clkin_0_src :string := "clk_0"; + pll_clkin_1_src :string := "clk_0"; + pll_clk_loss_sw_en :string := "false"; + pll_auto_clk_sw_en :string := "false"; + pll_manu_clk_sw_en :string := "false"; + mimic_fbclk_type :string:= "gclk"; + pll_fbclk_mux_1 :string:= "glb"; + pll_fbclk_mux_2 :string:= "fb_1"; + pll_m_cnt_in_src :string:= "ph_mux_clk"; + pll_vcoph_div : integer := 1; + pll_clk_sw_dly :integer := 0; + pll_slf_rst :string := "false"; + pll_bw_sel :string := "low"; + pll_extclk_0_cnt_src :string := "pll_extclk_cnt_src_vss"; + pll_extclk_1_cnt_src :string := "pll_extclk_cnt_src_vss"; + + clock_name_0 : string := ""; + clock_name_1 : string := ""; + clock_name_2 : string := ""; + clock_name_3 : string := ""; + clock_name_4 : string := ""; + clock_name_5 : string := ""; + clock_name_6 : string := ""; + clock_name_7 : string := ""; + clock_name_8 : string := ""; + clock_name_global_0 : string := "false"; + clock_name_global_1 : string := "false"; + clock_name_global_2 : string := "false"; + clock_name_global_3 : string := "false"; + clock_name_global_4 : string := "false"; + clock_name_global_5 : string := "false"; + clock_name_global_6 : string := "false"; + clock_name_global_7 : string := "false"; + clock_name_global_8 : string := "false" + ); + port( + refclk : in std_logic := '0'; + refclk1 : in std_logic := '0'; + adjpllin : in std_logic := '0'; + cclk : in std_logic := '0'; + fbclk : in std_logic := '0'; + scanclk : in std_logic := '0'; + rst : in std_logic := '0'; + extswitch : in std_logic := '0'; + phase_en : in std_logic := '0'; + updn : in std_logic := '0'; + cntsel : in std_logic_vector(4 downto 0):= (others => '0'); + num_phase_shifts : in std_logic_vector(2 downto 0):= (others => '0'); + + reconfig_to_pll : in std_logic_vector(63 downto 0) := (others => '0'); + outclk : out std_logic_vector(number_of_clocks - 1 downto 0); + cascade_out : out std_logic_vector(number_of_clocks - 1 downto 0); + fboutclk : out std_logic; + locked : out std_logic; + phase_done : out std_logic; + activeclk : out std_logic; + clkbad : out std_logic_vector(1 downto 0); + phout : out std_logic_vector(7 downto 0); + lvds_clk : out std_logic_vector(1 downto 0); + loaden : out std_logic_vector(1 downto 0); + extclk_out : out std_logic_vector(1 downto 0); + reconfig_from_pll : out std_logic_vector(63 downto 0); + zdbfbclk : inout std_logic + ); +end component; + +component altera_pll_dps_lcell_comb + generic( + family : string := "Stratix V"; + lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1'); + dont_touch : string := "on" + ); + port( + dataa : in std_logic := '0'; + datab : in std_logic := '0'; + datac : in std_logic := '0'; + datad : in std_logic := '0'; + datae : in std_logic := '0'; + dataf : in std_logic := '0'; + combout : out std_logic + ); +end component; + +component generic_pll + generic( + lpm_type : string := "generic_pll"; + duty_cycle : integer := 50; + output_clock_frequency: string := "0 ps"; + phase_shift : string := "0 ps"; + reference_clock_frequency: string := "0 ps"; + sim_additional_refclk_cycles_to_lock: integer := 0; + fractional_vco_multiplier: string := "false"; + use_khz : integer := 1; + clock_name : string := ""; + clock_name_global : string := "false" + ); + port( + refclk : in std_logic := '0'; + rst : in std_logic := '0'; + fbclk : in std_logic := '0'; + writerefclkdata : in std_logic_vector(63 downto 0) := (others => '0'); + writeoutclkdata : in std_logic_vector(63 downto 0) := (others => '0'); + writephaseshiftdata : in std_logic_vector(63 downto 0) := (others => '0'); + writedutycycledata : in std_logic_vector(63 downto 0) := (others => '0'); + + outclk : out std_logic; + locked : out std_logic; + fboutclk : out std_logic; + readrefclkdata : out std_logic_vector(63 downto 0); + readoutclkdata : out std_logic_vector(63 downto 0); + readphaseshiftdata : out std_logic_vector(63 downto 0); + readdutycycledata : out std_logic_vector(63 downto 0) + ); +end component; + +component generic_cdr + generic( + reference_clock_frequency: string := "0 ps"; + output_clock_frequency: string := "0 ps" + ); + port( + extclk : in std_logic; + ltd : in std_logic; + ltr : in std_logic; + ppmlock : in std_logic; + refclk : in std_logic; + rst : in std_logic; + sd : in std_logic; + rxp : in std_logic; + clk90bdes : out std_logic; + clk270bdes : out std_logic; + clklow : out std_logic; + deven : out std_logic; + dodd : out std_logic; + fref : out std_logic; + pfdmodelock : out std_logic; + rxplllock : out std_logic + ); +end component; + +COMPONENT generic_m20k + GENERIC ( + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + ecc_pipeline_stage_enabled : STRING := "false"; + enable_ecc : STRING := "false"; + width_eccstatus : INTEGER := 2; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + bist_ena : STRING := "false"; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock : STRING := "clock1"; + port_b_read_enable_clock : STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + lpm_type : STRING := "stratixv_ram_block"; + lpm_hint : STRING := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : STRING := ""; + mem_init1 : STRING := ""; + mem_init2 : STRING := ""; + mem_init3 : STRING := ""; + mem_init4 : STRING := ""; + mem_init5 : STRING := ""; + mem_init6 : STRING := ""; + mem_init7 : STRING := ""; + mem_init8 : STRING := ""; + mem_init9 : STRING := ""; + connectivity_checking : string := "off" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + nerror : IN STD_LOGIC := '1'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0'); + dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000"; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT generic_m10k + GENERIC ( + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + ecc_pipeline_stage_enabled : STRING := "false"; + enable_ecc : STRING := "false"; + width_eccstatus : INTEGER := 2; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + bist_ena : STRING := "false"; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock : STRING := "clock1"; + port_b_read_enable_clock : STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + lpm_type : STRING := "arriav_ram_block"; + lpm_hint : STRING := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : STRING := ""; + mem_init1 : STRING := ""; + mem_init2 : STRING := ""; + mem_init3 : STRING := ""; + mem_init4 : STRING := ""; + connectivity_checking : STRING := "off" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + nerror : IN STD_LOGIC := '1'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0'); + dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000"; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT generic_mlab_cell + GENERIC ( + logical_ram_name : STRING := "lutram"; + logical_ram_depth : INTEGER := 0; + logical_ram_width : INTEGER := 0; + first_address : INTEGER := 0; + last_address : INTEGER := 0; + first_bit_number : INTEGER := 0; + init_file : STRING := "NONE"; + data_width : INTEGER := 20; + address_width : INTEGER := 6; + byte_enable_mask_width : INTEGER := 1; + byte_size : INTEGER := 1; + port_b_data_out_clock : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + lpm_type : STRING := "stratixv_lutram"; + lpm_hint : STRING := "true"; + mem_init0 : STRING := ""; + mixed_port_feed_through_mode : STRING := "new" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0'); + portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1'); + portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + clr : IN STD_LOGIC := '0'; + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT generic_28nm_hp_mlab_cell_impl + GENERIC ( + logical_ram_name : STRING := "lutram"; + logical_ram_depth : INTEGER := 0; + logical_ram_width : INTEGER := 0; + first_address : INTEGER := 0; + last_address : INTEGER := 0; + first_bit_number : INTEGER := 0; + init_file : STRING := "NONE"; + data_width : INTEGER := 20; + address_width : INTEGER := 6; + byte_enable_mask_width : INTEGER := 1; + byte_size : INTEGER := 1; + port_b_data_out_clock : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + lpm_type : STRING := "stratixv_lutram"; + lpm_hint : STRING := "true"; + mem_init0 : STRING := ""; + mixed_port_feed_through_mode : STRING := "new" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0'); + portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1'); + portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + clr : IN STD_LOGIC := '0'; + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT generic_28nm_lc_mlab_cell_impl + GENERIC ( + logical_ram_name : STRING := "lutram"; + logical_ram_depth : INTEGER := 0; + logical_ram_width : INTEGER := 0; + first_address : INTEGER := 0; + last_address : INTEGER := 0; + first_bit_number : INTEGER := 0; + init_file : STRING := "NONE"; + data_width : INTEGER := 20; + address_width : INTEGER := 5; + byte_enable_mask_width : INTEGER := 1; + byte_size : INTEGER := 1; + port_b_data_out_clock : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + lpm_type : STRING := "arriav_lutram"; + lpm_hint : STRING := "true"; + mem_init0 : STRING := ""; + mixed_port_feed_through_mode : STRING := "new" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0'); + portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1'); + portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + clr : IN STD_LOGIC := '0'; + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +component altera_functions +end component; + +component generic_mux + port( + din : in std_logic_vector(63 downto 0); + sel : in std_logic_vector(5 downto 0); + dout : out std_logic_vector + ); +end component; + +component generic_device_pll + generic( + reference_clock_frequency : string := "0 ps"; + output_clock_frequency : string := "0 ps"; + forcelock : string := "false"; + nreset_invert : string := "false"; + pll_enable : string := "true"; + pll_fbclk_mux_1 : string := "glb"; + pll_fbclk_mux_2 : string := "fb_1"; + pll_m_cnt_bypass_en : string := "false"; + pll_m_cnt_hi_div : integer := 1; + pll_m_cnt_in_src : string := "ph_mux_clk"; + pll_m_cnt_lo_div : integer := 1; + pll_n_cnt_bypass_en : string := "false"; + pll_n_cnt_hi_div : integer := 1; + pll_n_cnt_lo_div : integer := 1; + pll_vco_ph0_en : string := "false"; + pll_vco_ph1_en : string := "false"; + pll_vco_ph2_en : string := "false"; + pll_vco_ph3_en : string := "false"; + pll_vco_ph4_en : string := "false"; + pll_vco_ph5_en : string := "false"; + pll_vco_ph6_en : string := "false"; + pll_vco_ph7_en : string := "false" + ); + port( + coreclkfb : in std_logic; + fbclkfpll : in std_logic; + lvdsfbin : in std_logic; + nresync : in std_logic; + pfden : in std_logic; + refclkin : in std_logic; + zdb : in std_logic; + + fbclk : out std_logic; + fblvdsout : out std_logic; + lock : out std_logic; + vcoph : out std_logic_vector(7 downto 0) + ); +end component; + + + +component altera_mult_add + GENERIC ( + extra_latency : INTEGER := 0; + dedicated_multiplier_circuitry : STRING := "AUTO"; + dsp_block_balancing : STRING := "AUTO"; + selected_device_family : STRING := "Stratix V"; + lpm_type : STRING := "altera_mult_add"; + lpm_hint : STRING := "UNUSED"; + width_a : INTEGER := 1; + input_register_a0 : STRING := "UNREGISTERED"; + input_aclr_a0 : STRING := "NONE"; + input_source_a0 : STRING := "DATAA"; + input_register_a1 : STRING := "UNREGISTERED"; + input_aclr_a1 : STRING := "NONE"; + input_source_a1 : STRING := "DATAA"; + input_register_a2 : STRING := "UNREGISTERED"; + input_aclr_a2 : STRING := "NONE"; + input_source_a2 : STRING := "DATAA"; + input_register_a3 : STRING := "UNREGISTERED"; + input_aclr_a3 : STRING := "NONE"; + input_source_a3 : STRING := "DATAA"; + width_b : INTEGER := 1; + input_register_b0 : STRING := "UNREGISTERED"; + input_aclr_b0 : STRING := "NONE"; + input_source_b0 : STRING := "DATAB"; + input_register_b1 : STRING := "UNREGISTERED"; + input_aclr_b1 : STRING := "NONE"; + input_source_b1 : STRING := "DATAB"; + input_register_b2 : STRING := "UNREGISTERED"; + input_aclr_b2 : STRING := "NONE"; + input_source_b2 : STRING := "DATAB"; + input_register_b3 : STRING := "UNREGISTERED"; + input_aclr_b3 : STRING := "NONE"; + input_source_b3 : STRING := "DATAB"; + width_c : INTEGER := 1; + input_register_c0 : STRING := "UNREGISTERED"; + input_aclr_c0 : STRING := "NONE"; + input_register_c1 : STRING := "UNREGISTERED"; + input_aclr_c1 : STRING := "NONE"; + input_register_c2 : STRING := "UNREGISTERED"; + input_aclr_c2 : STRING := "NONE"; + input_register_c3 : STRING := "UNREGISTERED"; + input_aclr_c3 : STRING := "NONE"; + width_result : INTEGER := 34; + output_register : STRING := "UNREGISTERED"; + output_aclr : STRING := "NONE"; + port_signa : STRING := "PORT_UNUSED"; + representation_a : STRING := "UNSIGNED"; + signed_register_a : STRING := "UNREGISTERED"; + signed_aclr_a : STRING := "NONE"; + signed_pipeline_register_a : STRING := "UNREGISTERED"; + signed_pipeline_aclr_a : STRING := "NONE"; + port_signb : STRING := "PORT_UNUSED"; + representation_b : STRING := "UNSIGNED"; + signed_register_b : STRING := "UNREGISTERED"; + signed_aclr_b : STRING := "NONE"; + signed_pipeline_register_b : STRING := "UNREGISTERED"; + signed_pipeline_aclr_b : STRING := "NONE"; + number_of_multipliers : INTEGER := 1; + multiplier1_direction : STRING := "UNUSED"; + multiplier3_direction : STRING := "UNUSED"; + multiplier_register0 : STRING := "UNREGISTERED"; + multiplier_aclr0 : STRING := "NONE"; + multiplier_register1 : STRING := "UNREGISTERED"; + multiplier_aclr1 : STRING := "NONE"; + multiplier_register2 : STRING := "UNREGISTERED"; + multiplier_aclr2 : STRING := "NONE"; + multiplier_register3 : STRING := "UNREGISTERED"; + multiplier_aclr3 : STRING := "NONE"; + port_addnsub1 : STRING := "PORT_UNUSED"; + addnsub_multiplier_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr1 : STRING := "NONE"; + addnsub_multiplier_pipeline_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr1 : STRING := "NONE"; + port_addnsub3 : STRING := "PORT_UNUSED"; + addnsub_multiplier_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr3 : STRING := "NONE"; + addnsub_multiplier_pipeline_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr3 : STRING := "NONE"; + use_subnadd : STRING := "NO"; + adder1_rounding : STRING := "NO"; + addnsub1_round_register : STRING := "UNREGISTERED"; + addnsub1_round_aclr : STRING := "NONE"; + addnsub1_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub1_round_pipeline_aclr : STRING := "NONE"; + adder3_rounding : STRING := "NO"; + addnsub3_round_register : STRING := "UNREGISTERED"; + addnsub3_round_aclr : STRING := "NONE"; + addnsub3_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub3_round_pipeline_aclr : STRING := "NONE"; + multiplier01_rounding : STRING := "NO"; + mult01_round_register : STRING := "UNREGISTERED"; + mult01_round_aclr : STRING := "NONE"; + multiplier23_rounding : STRING := "NO"; + mult23_round_register : STRING := "UNREGISTERED"; + mult23_round_aclr : STRING := "NONE"; + width_msb : INTEGER := 17; + output_rounding : STRING := "NO"; + output_round_type : STRING := "NEAREST_INTEGER"; + output_round_register : STRING := "UNREGISTERED"; + output_round_aclr : STRING := "NONE"; + output_round_pipeline_register : STRING := "UNREGISTERED"; + output_round_pipeline_aclr : STRING := "NONE"; + chainout_rounding : STRING := "NO"; + chainout_round_register : STRING := "UNREGISTERED"; + chainout_round_aclr : STRING := "NONE"; + chainout_round_pipeline_register : STRING := "UNREGISTERED"; + chainout_round_pipeline_aclr : STRING := "NONE"; + chainout_round_output_register : STRING := "UNREGISTERED"; + chainout_round_output_aclr : STRING := "NONE"; + multiplier01_saturation : STRING := "NO"; + mult01_saturation_register : STRING := "UNREGISTERED"; + mult01_saturation_aclr : STRING := "NONE"; + multiplier23_saturation : STRING := "NO"; + mult23_saturation_register : STRING := "UNREGISTERED"; + mult23_saturation_aclr : STRING := "NONE"; + port_mult0_is_saturated : STRING := "UNUSED"; + port_mult1_is_saturated : STRING := "UNUSED"; + port_mult2_is_saturated : STRING := "UNUSED"; + port_mult3_is_saturated : STRING := "UNUSED"; + width_saturate_sign : INTEGER := 1; + output_saturation : STRING := "NO"; + port_output_is_overflow : STRING := "PORT_UNUSED"; + output_saturate_type : STRING := "ASYMMETRIC"; + output_saturate_register : STRING := "UNREGISTERED"; + output_saturate_aclr : STRING := "NONE"; + output_saturate_pipeline_register : STRING := "UNREGISTERED"; + output_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturation : STRING := "NO"; + port_chainout_sat_is_overflow : STRING := "PORT_UNUSED"; + chainout_saturate_register : STRING := "UNREGISTERED"; + chainout_saturate_aclr : STRING := "NONE"; + chainout_saturate_pipeline_register : STRING := "UNREGISTERED"; + chainout_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturate_output_register : STRING := "UNREGISTERED"; + chainout_saturate_output_aclr : STRING := "NONE"; + scanouta_register : STRING := "UNREGISTERED"; + scanouta_aclr : STRING := "NONE"; + width_chainin : INTEGER := 1; + chainout_adder : STRING := "NO"; + chainout_adder_direction : STRING := "ADD"; + chainout_register : STRING := "UNREGISTERED"; + chainout_aclr : STRING := "NONE"; + port_negate : STRING := "PORT_UNUSED"; + negate_register : STRING := "UNREGISTERED"; + negate_aclr : STRING := "NONE"; + negate_latency_clock : STRING := "UNREGISTERED"; + negate_latency_aclr : STRING := "NONE"; + zero_chainout_output_register : STRING := "UNREGISTERED"; + zero_chainout_output_aclr : STRING := "NONE"; + shift_mode : STRING := "NO"; + rotate_register : STRING := "UNREGISTERED"; + rotate_aclr : STRING := "NONE"; + rotate_pipeline_register : STRING := "UNREGISTERED"; + rotate_pipeline_aclr : STRING := "NONE"; + rotate_output_register : STRING := "UNREGISTERED"; + rotate_output_aclr : STRING := "NONE"; + shift_right_register : STRING := "UNREGISTERED"; + shift_right_aclr : STRING := "NONE"; + shift_right_pipeline_register : STRING := "UNREGISTERED"; + shift_right_pipeline_aclr : STRING := "NONE"; + shift_right_output_register : STRING := "UNREGISTERED"; + shift_right_output_aclr : STRING := "NONE"; + zero_loopback_register : STRING := "UNREGISTERED"; + zero_loopback_aclr : STRING := "NONE"; + zero_loopback_pipeline_register : STRING := "UNREGISTERED"; + zero_loopback_pipeline_aclr : STRING := "NONE"; + zero_loopback_output_register : STRING := "UNREGISTERED"; + zero_loopback_output_aclr : STRING := "NONE"; + accumulator : STRING := "NO"; + accum_direction : STRING := "ADD"; + double_accum : STRING := "NO"; + loadconst_value : INTEGER := 0; + use_sload_accum_port : STRING := "NO"; + accum_sload_register : STRING := "UNREGISTERED"; + accum_sload_aclr : STRING := "NONE"; + accum_sload_pipeline_register : STRING := "UNREGISTERED"; + accum_sload_pipeline_aclr : STRING := "NONE"; + loadconst_control_register : STRING := "UNREGISTERED"; + loadconst_control_aclr : STRING := "NONE"; + systolic_delay1 : STRING := "UNREGISTERED"; + systolic_delay3 : STRING := "UNREGISTERED"; + systolic_aclr1 : STRING := "NONE"; + systolic_aclr3 : STRING := "NONE"; + preadder_mode : STRING := "SIMPLE"; + preadder_direction_0 : STRING := "ADD"; + preadder_direction_1 : STRING := "ADD"; + preadder_direction_2 : STRING := "ADD"; + preadder_direction_3 : STRING := "ADD"; + width_coef : INTEGER := 1; + coefsel0_register : STRING := "UNREGISTERED"; + coefsel0_aclr : STRING := "NONE"; + coefsel1_register : STRING := "UNREGISTERED"; + coefsel1_aclr : STRING := "NONE"; + coefsel2_register : STRING := "UNREGISTERED"; + coefsel2_aclr : STRING := "NONE"; + coefsel3_register : STRING := "UNREGISTERED"; + coefsel3_aclr : STRING := "NONE"; + coef0_0 : INTEGER := 0; + coef0_1 : INTEGER := 0; + coef0_2 : INTEGER := 0; + coef0_3 : INTEGER := 0; + coef0_4 : INTEGER := 0; + coef0_5 : INTEGER := 0; + coef0_6 : INTEGER := 0; + coef0_7 : INTEGER := 0; + coef1_0 : INTEGER := 0; + coef1_1 : INTEGER := 0; + coef1_2 : INTEGER := 0; + coef1_3 : INTEGER := 0; + coef1_4 : INTEGER := 0; + coef1_5 : INTEGER := 0; + coef1_6 : INTEGER := 0; + coef1_7 : INTEGER := 0; + coef2_0 : INTEGER := 0; + coef2_1 : INTEGER := 0; + coef2_2 : INTEGER := 0; + coef2_3 : INTEGER := 0; + coef2_4 : INTEGER := 0; + coef2_5 : INTEGER := 0; + coef2_6 : INTEGER := 0; + coef2_7 : INTEGER := 0; + coef3_0 : INTEGER := 0; + coef3_1 : INTEGER := 0; + coef3_2 : INTEGER := 0; + coef3_3 : INTEGER := 0; + coef3_4 : INTEGER := 0; + coef3_5 : INTEGER := 0; + coef3_6 : INTEGER := 0; + coef3_7 : INTEGER := 0; + latency : INTEGER := 0; + input_a0_latency_clock : STRING := "UNREGISTERED"; + input_a0_latency_aclr : STRING := "NONE"; + input_a1_latency_clock : STRING := "UNREGISTERED"; + input_a1_latency_aclr : STRING := "NONE"; + input_a2_latency_clock : STRING := "UNREGISTERED"; + input_a2_latency_aclr : STRING := "NONE"; + input_a3_latency_clock : STRING := "UNREGISTERED"; + input_a3_latency_aclr : STRING := "NONE"; + input_b0_latency_clock : STRING := "UNREGISTERED"; + input_b0_latency_aclr : STRING := "NONE"; + input_b1_latency_clock : STRING := "UNREGISTERED"; + input_b1_latency_aclr : STRING := "NONE"; + input_b2_latency_clock : STRING := "UNREGISTERED"; + input_b2_latency_aclr : STRING := "NONE"; + input_b3_latency_clock : STRING := "UNREGISTERED"; + input_b3_latency_aclr : STRING := "NONE"; + input_c0_latency_clock : STRING := "UNREGISTERED"; + input_c0_latency_aclr : STRING := "NONE"; + input_c1_latency_clock : STRING := "UNREGISTERED"; + input_c1_latency_aclr : STRING := "NONE"; + input_c2_latency_clock : STRING := "UNREGISTERED"; + input_c2_latency_aclr : STRING := "NONE"; + input_c3_latency_clock : STRING := "UNREGISTERED"; + input_c3_latency_aclr : STRING := "NONE"; + coefsel0_latency_clock : STRING := "UNREGISTERED"; + coefsel0_latency_aclr : STRING := "NONE"; + coefsel1_latency_clock : STRING := "UNREGISTERED"; + coefsel1_latency_aclr : STRING := "NONE"; + coefsel2_latency_clock : STRING := "UNREGISTERED"; + coefsel2_latency_aclr : STRING := "NONE"; + coefsel3_latency_clock : STRING := "UNREGISTERED"; + coefsel3_latency_aclr : STRING := "NONE"; + signed_latency_clock_a : STRING := "UNREGISTERED"; + signed_latency_aclr_a : STRING := "NONE"; + signed_latency_clock_b : STRING := "UNREGISTERED"; + signed_latency_aclr_b : STRING := "NONE"; + addnsub_multiplier_latency_clock1 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr1 : STRING := "NONE"; + addnsub_multiplier_latency_clock3 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr3 : STRING := "NONE"; + accum_sload_latency_clock : STRING := "UNREGISTERED"; + accum_sload_latency_aclr : STRING := "NONE" + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR(width_a * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datab : IN STD_LOGIC_VECTOR(width_b * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datac : IN STD_LOGIC_VECTOR(width_c * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + scanina : IN STD_LOGIC_VECTOR(width_a - 1 downto 0) := (OTHERS => '0'); + scaninb : IN STD_LOGIC_VECTOR(width_b - 1 downto 0) := (OTHERS => '0'); + sourcea : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + sourceb : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + clock3 : IN STD_LOGIC := '0'; + clock2 : IN STD_LOGIC := '0'; + clock1 : IN STD_LOGIC := '0'; + clock0 : IN STD_LOGIC := '0'; + aclr3 : IN STD_LOGIC := '0'; + aclr2 : IN STD_LOGIC := '0'; + aclr1 : IN STD_LOGIC := '0'; + aclr0 : IN STD_LOGIC := '0'; + ena3 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena0 : IN STD_LOGIC := '1'; + signa : IN STD_LOGIC := '0'; + signb : IN STD_LOGIC := '0'; + addnsub1 : IN STD_LOGIC := '0'; + addnsub3 : IN STD_LOGIC := '0'; + result : OUT STD_LOGIC_VECTOR(width_result - 1 downto 0); + scanouta : OUT STD_LOGIC_VECTOR(width_a - 1 downto 0); + scanoutb : OUT STD_LOGIC_VECTOR(width_b - 1 downto 0); + mult01_round : IN STD_LOGIC := '0'; + mult23_round : IN STD_LOGIC := '0'; + mult01_saturation : IN STD_LOGIC := '0'; + mult23_saturation : IN STD_LOGIC := '0'; + addnsub1_round : IN STD_LOGIC := '0'; + addnsub3_round : IN STD_LOGIC := '0'; + mult0_is_saturated : OUT STD_LOGIC; + mult1_is_saturated : OUT STD_LOGIC; + mult2_is_saturated : OUT STD_LOGIC; + mult3_is_saturated : OUT STD_LOGIC; + output_round : IN STD_LOGIC := '0'; + chainout_round : IN STD_LOGIC := '0'; + output_saturate : IN STD_LOGIC := '0'; + chainout_saturate : IN STD_LOGIC := '0'; + overflow : OUT STD_LOGIC; + chainout_sat_overflow : OUT STD_LOGIC; + chainin : IN STD_LOGIC_VECTOR(width_chainin - 1 downto 0) := (OTHERS => '0'); + zero_chainout : IN STD_LOGIC := '0'; + rotate : IN STD_LOGIC := '0'; + shift_right : IN STD_LOGIC := '0'; + zero_loopback : IN STD_LOGIC := '0'; + accum_sload : IN STD_LOGIC := '0'; + sload_accum : IN STD_LOGIC := '0'; + negate : IN STD_LOGIC := '0'; + coefsel0 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel1 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel2 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel3 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0') + ); +end component; + +component altera_mult_add_rtl + GENERIC ( + extra_latency : INTEGER := 0; + dedicated_multiplier_circuitry : STRING := "AUTO"; + dsp_block_balancing : STRING := "AUTO"; + selected_device_family : STRING := "Stratix V"; + lpm_type : STRING := "altera_mult_add"; + lpm_hint : STRING := "UNUSED"; + width_a : INTEGER := 1; + input_register_a0 : STRING := "UNREGISTERED"; + input_aclr_a0 : STRING := "NONE"; + input_source_a0 : STRING := "DATAA"; + input_register_a1 : STRING := "UNREGISTERED"; + input_aclr_a1 : STRING := "NONE"; + input_source_a1 : STRING := "DATAA"; + input_register_a2 : STRING := "UNREGISTERED"; + input_aclr_a2 : STRING := "NONE"; + input_source_a2 : STRING := "DATAA"; + input_register_a3 : STRING := "UNREGISTERED"; + input_aclr_a3 : STRING := "NONE"; + input_source_a3 : STRING := "DATAA"; + width_b : INTEGER := 1; + input_register_b0 : STRING := "UNREGISTERED"; + input_aclr_b0 : STRING := "NONE"; + input_source_b0 : STRING := "DATAB"; + input_register_b1 : STRING := "UNREGISTERED"; + input_aclr_b1 : STRING := "NONE"; + input_source_b1 : STRING := "DATAB"; + input_register_b2 : STRING := "UNREGISTERED"; + input_aclr_b2 : STRING := "NONE"; + input_source_b2 : STRING := "DATAB"; + input_register_b3 : STRING := "UNREGISTERED"; + input_aclr_b3 : STRING := "NONE"; + input_source_b3 : STRING := "DATAB"; + width_c : INTEGER := 1; + input_register_c0 : STRING := "UNREGISTERED"; + input_aclr_c0 : STRING := "NONE"; + input_register_c1 : STRING := "UNREGISTERED"; + input_aclr_c1 : STRING := "NONE"; + input_register_c2 : STRING := "UNREGISTERED"; + input_aclr_c2 : STRING := "NONE"; + input_register_c3 : STRING := "UNREGISTERED"; + input_aclr_c3 : STRING := "NONE"; + width_result : INTEGER := 34; + output_register : STRING := "UNREGISTERED"; + output_aclr : STRING := "NONE"; + port_signa : STRING := "PORT_UNUSED"; + representation_a : STRING := "UNSIGNED"; + signed_register_a : STRING := "UNREGISTERED"; + signed_aclr_a : STRING := "NONE"; + signed_pipeline_register_a : STRING := "UNREGISTERED"; + signed_pipeline_aclr_a : STRING := "NONE"; + port_signb : STRING := "PORT_UNUSED"; + representation_b : STRING := "UNSIGNED"; + signed_register_b : STRING := "UNREGISTERED"; + signed_aclr_b : STRING := "NONE"; + signed_pipeline_register_b : STRING := "UNREGISTERED"; + signed_pipeline_aclr_b : STRING := "NONE"; + number_of_multipliers : INTEGER := 1; + multiplier1_direction : STRING := "UNUSED"; + multiplier3_direction : STRING := "UNUSED"; + multiplier_register0 : STRING := "UNREGISTERED"; + multiplier_aclr0 : STRING := "NONE"; + multiplier_register1 : STRING := "UNREGISTERED"; + multiplier_aclr1 : STRING := "NONE"; + multiplier_register2 : STRING := "UNREGISTERED"; + multiplier_aclr2 : STRING := "NONE"; + multiplier_register3 : STRING := "UNREGISTERED"; + multiplier_aclr3 : STRING := "NONE"; + port_addnsub1 : STRING := "PORT_UNUSED"; + addnsub_multiplier_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr1 : STRING := "NONE"; + addnsub_multiplier_pipeline_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr1 : STRING := "NONE"; + port_addnsub3 : STRING := "PORT_UNUSED"; + use_subnadd : STRING := "NO"; + addnsub_multiplier_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr3 : STRING := "NONE"; + addnsub_multiplier_pipeline_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr3 : STRING := "NONE"; + adder1_rounding : STRING := "NO"; + addnsub1_round_register : STRING := "UNREGISTERED"; + addnsub1_round_aclr : STRING := "NONE"; + addnsub1_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub1_round_pipeline_aclr : STRING := "NONE"; + adder3_rounding : STRING := "NO"; + addnsub3_round_register : STRING := "UNREGISTERED"; + addnsub3_round_aclr : STRING := "NONE"; + addnsub3_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub3_round_pipeline_aclr : STRING := "NONE"; + multiplier01_rounding : STRING := "NO"; + mult01_round_register : STRING := "UNREGISTERED"; + mult01_round_aclr : STRING := "NONE"; + multiplier23_rounding : STRING := "NO"; + mult23_round_register : STRING := "UNREGISTERED"; + mult23_round_aclr : STRING := "NONE"; + width_msb : INTEGER := 17; + output_rounding : STRING := "NO"; + output_round_type : STRING := "NEAREST_INTEGER"; + output_round_register : STRING := "UNREGISTERED"; + output_round_aclr : STRING := "NONE"; + output_round_pipeline_register : STRING := "UNREGISTERED"; + output_round_pipeline_aclr : STRING := "NONE"; + chainout_rounding : STRING := "NO"; + chainout_round_register : STRING := "UNREGISTERED"; + chainout_round_aclr : STRING := "NONE"; + chainout_round_pipeline_register : STRING := "UNREGISTERED"; + chainout_round_pipeline_aclr : STRING := "NONE"; + chainout_round_output_register : STRING := "UNREGISTERED"; + chainout_round_output_aclr : STRING := "NONE"; + multiplier01_saturation : STRING := "NO"; + mult01_saturation_register : STRING := "UNREGISTERED"; + mult01_saturation_aclr : STRING := "NONE"; + multiplier23_saturation : STRING := "NO"; + mult23_saturation_register : STRING := "UNREGISTERED"; + mult23_saturation_aclr : STRING := "NONE"; + port_mult0_is_saturated : STRING := "UNUSED"; + port_mult1_is_saturated : STRING := "UNUSED"; + port_mult2_is_saturated : STRING := "UNUSED"; + port_mult3_is_saturated : STRING := "UNUSED"; + width_saturate_sign : INTEGER := 1; + output_saturation : STRING := "NO"; + port_output_is_overflow : STRING := "PORT_UNUSED"; + output_saturate_type : STRING := "ASYMMETRIC"; + output_saturate_register : STRING := "UNREGISTERED"; + output_saturate_aclr : STRING := "NONE"; + output_saturate_pipeline_register : STRING := "UNREGISTERED"; + output_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturation : STRING := "NO"; + port_chainout_sat_is_overflow : STRING := "PORT_UNUSED"; + chainout_saturate_register : STRING := "UNREGISTERED"; + chainout_saturate_aclr : STRING := "NONE"; + chainout_saturate_pipeline_register : STRING := "UNREGISTERED"; + chainout_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturate_output_register : STRING := "UNREGISTERED"; + chainout_saturate_output_aclr : STRING := "NONE"; + scanouta_register : STRING := "UNREGISTERED"; + scanouta_aclr : STRING := "NONE"; + width_chainin : INTEGER := 1; + chainout_adder : STRING := "NO"; + chainout_adder_direction : STRING := "ADD"; + chainout_register : STRING := "UNREGISTERED"; + chainout_aclr : STRING := "NONE"; + port_negate : STRING := "PORT_UNUSED"; + negate_register : STRING := "UNREGISTERED"; + negate_aclr : STRING := "NONE"; + negate_latency_clock : STRING := "UNREGISTERED"; + negate_latency_aclr : STRING := "NONE"; + zero_chainout_output_register : STRING := "UNREGISTERED"; + zero_chainout_output_aclr : STRING := "NONE"; + shift_mode : STRING := "NO"; + rotate_register : STRING := "UNREGISTERED"; + rotate_aclr : STRING := "NONE"; + rotate_pipeline_register : STRING := "UNREGISTERED"; + rotate_pipeline_aclr : STRING := "NONE"; + rotate_output_register : STRING := "UNREGISTERED"; + rotate_output_aclr : STRING := "NONE"; + shift_right_register : STRING := "UNREGISTERED"; + shift_right_aclr : STRING := "NONE"; + shift_right_pipeline_register : STRING := "UNREGISTERED"; + shift_right_pipeline_aclr : STRING := "NONE"; + shift_right_output_register : STRING := "UNREGISTERED"; + shift_right_output_aclr : STRING := "NONE"; + zero_loopback_register : STRING := "UNREGISTERED"; + zero_loopback_aclr : STRING := "NONE"; + zero_loopback_pipeline_register : STRING := "UNREGISTERED"; + zero_loopback_pipeline_aclr : STRING := "NONE"; + zero_loopback_output_register : STRING := "UNREGISTERED"; + zero_loopback_output_aclr : STRING := "NONE"; + accumulator : STRING := "NO"; + accum_direction : STRING := "ADD"; + double_accum : STRING := "NO"; + loadconst_value : INTEGER := 0; + use_sload_accum_port : STRING := "NO"; + accum_sload_register : STRING := "UNREGISTERED"; + accum_sload_aclr : STRING := "NONE"; + accum_sload_pipeline_register : STRING := "UNREGISTERED"; + accum_sload_pipeline_aclr : STRING := "NONE"; + loadconst_control_register : STRING := "UNREGISTERED"; + loadconst_control_aclr : STRING := "NONE"; + systolic_delay1 : STRING := "UNREGISTERED"; + systolic_delay3 : STRING := "UNREGISTERED"; + systolic_aclr1 : STRING := "NONE"; + systolic_aclr3 : STRING := "NONE"; + preadder_mode : STRING := "SIMPLE"; + preadder_direction_0 : STRING := "ADD"; + preadder_direction_1 : STRING := "ADD"; + preadder_direction_2 : STRING := "ADD"; + preadder_direction_3 : STRING := "ADD"; + width_coef : INTEGER := 1; + coefsel0_register : STRING := "UNREGISTERED"; + coefsel0_aclr : STRING := "NONE"; + coefsel1_register : STRING := "UNREGISTERED"; + coefsel1_aclr : STRING := "NONE"; + coefsel2_register : STRING := "UNREGISTERED"; + coefsel2_aclr : STRING := "NONE"; + coefsel3_register : STRING := "UNREGISTERED"; + coefsel3_aclr : STRING := "NONE"; + coef0_0 : INTEGER := 0; + coef0_1 : INTEGER := 0; + coef0_2 : INTEGER := 0; + coef0_3 : INTEGER := 0; + coef0_4 : INTEGER := 0; + coef0_5 : INTEGER := 0; + coef0_6 : INTEGER := 0; + coef0_7 : INTEGER := 0; + coef1_0 : INTEGER := 0; + coef1_1 : INTEGER := 0; + coef1_2 : INTEGER := 0; + coef1_3 : INTEGER := 0; + coef1_4 : INTEGER := 0; + coef1_5 : INTEGER := 0; + coef1_6 : INTEGER := 0; + coef1_7 : INTEGER := 0; + coef2_0 : INTEGER := 0; + coef2_1 : INTEGER := 0; + coef2_2 : INTEGER := 0; + coef2_3 : INTEGER := 0; + coef2_4 : INTEGER := 0; + coef2_5 : INTEGER := 0; + coef2_6 : INTEGER := 0; + coef2_7 : INTEGER := 0; + coef3_0 : INTEGER := 0; + coef3_1 : INTEGER := 0; + coef3_2 : INTEGER := 0; + coef3_3 : INTEGER := 0; + coef3_4 : INTEGER := 0; + coef3_5 : INTEGER := 0; + coef3_6 : INTEGER := 0; + coef3_7 : INTEGER := 0; + latency : INTEGER := 0; + input_a0_latency_clock : STRING := "UNREGISTERED"; + input_a0_latency_aclr : STRING := "NONE"; + input_a1_latency_clock : STRING := "UNREGISTERED"; + input_a1_latency_aclr : STRING := "NONE"; + input_a2_latency_clock : STRING := "UNREGISTERED"; + input_a2_latency_aclr : STRING := "NONE"; + input_a3_latency_clock : STRING := "UNREGISTERED"; + input_a3_latency_aclr : STRING := "NONE"; + input_b0_latency_clock : STRING := "UNREGISTERED"; + input_b0_latency_aclr : STRING := "NONE"; + input_b1_latency_clock : STRING := "UNREGISTERED"; + input_b1_latency_aclr : STRING := "NONE"; + input_b2_latency_clock : STRING := "UNREGISTERED"; + input_b2_latency_aclr : STRING := "NONE"; + input_b3_latency_clock : STRING := "UNREGISTERED"; + input_b3_latency_aclr : STRING := "NONE"; + input_c0_latency_clock : STRING := "UNREGISTERED"; + input_c0_latency_aclr : STRING := "NONE"; + input_c1_latency_clock : STRING := "UNREGISTERED"; + input_c1_latency_aclr : STRING := "NONE"; + input_c2_latency_clock : STRING := "UNREGISTERED"; + input_c2_latency_aclr : STRING := "NONE"; + input_c3_latency_clock : STRING := "UNREGISTERED"; + input_c3_latency_aclr : STRING := "NONE"; + coefsel0_latency_clock : STRING := "UNREGISTERED"; + coefsel0_latency_aclr : STRING := "NONE"; + coefsel1_latency_clock : STRING := "UNREGISTERED"; + coefsel1_latency_aclr : STRING := "NONE"; + coefsel2_latency_clock : STRING := "UNREGISTERED"; + coefsel2_latency_aclr : STRING := "NONE"; + coefsel3_latency_clock : STRING := "UNREGISTERED"; + coefsel3_latency_aclr : STRING := "NONE"; + signed_latency_clock_a : STRING := "UNREGISTERED"; + signed_latency_aclr_a : STRING := "NONE"; + signed_latency_clock_b : STRING := "UNREGISTERED"; + signed_latency_aclr_b : STRING := "NONE"; + addnsub_multiplier_latency_clock1 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr1 : STRING := "NONE"; + addnsub_multiplier_latency_clock3 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr3 : STRING := "NONE"; + accum_sload_latency_clock : STRING := "UNREGISTERED"; + accum_sload_latency_aclr : STRING := "NONE" + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR(width_a * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datab : IN STD_LOGIC_VECTOR(width_b * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datac : IN STD_LOGIC_VECTOR(width_c * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + scanina : IN STD_LOGIC_VECTOR(width_a - 1 downto 0) := (OTHERS => '0'); + scaninb : IN STD_LOGIC_VECTOR(width_b - 1 downto 0) := (OTHERS => '0'); + sourcea : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + sourceb : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + clock3 : IN STD_LOGIC := '0'; + clock2 : IN STD_LOGIC := '0'; + clock1 : IN STD_LOGIC := '0'; + clock0 : IN STD_LOGIC := '0'; + aclr3 : IN STD_LOGIC := '0'; + aclr2 : IN STD_LOGIC := '0'; + aclr1 : IN STD_LOGIC := '0'; + aclr0 : IN STD_LOGIC := '0'; + ena3 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena0 : IN STD_LOGIC := '1'; + signa : IN STD_LOGIC := '0'; + signb : IN STD_LOGIC := '0'; + addnsub1 : IN STD_LOGIC := '0'; + addnsub3 : IN STD_LOGIC := '0'; + result : OUT STD_LOGIC_VECTOR(width_result - 1 downto 0); + scanouta : OUT STD_LOGIC_VECTOR(width_a - 1 downto 0); + scanoutb : OUT STD_LOGIC_VECTOR(width_b - 1 downto 0); + mult01_round : IN STD_LOGIC := '0'; + mult23_round : IN STD_LOGIC := '0'; + mult01_saturation : IN STD_LOGIC := '0'; + mult23_saturation : IN STD_LOGIC := '0'; + addnsub1_round : IN STD_LOGIC := '0'; + addnsub3_round : IN STD_LOGIC := '0'; + mult0_is_saturated : OUT STD_LOGIC; + mult1_is_saturated : OUT STD_LOGIC; + mult2_is_saturated : OUT STD_LOGIC; + mult3_is_saturated : OUT STD_LOGIC; + output_round : IN STD_LOGIC := '0'; + chainout_round : IN STD_LOGIC := '0'; + output_saturate : IN STD_LOGIC := '0'; + chainout_saturate : IN STD_LOGIC := '0'; + overflow : OUT STD_LOGIC; + chainout_sat_overflow : OUT STD_LOGIC; + chainin : IN STD_LOGIC_VECTOR(width_chainin - 1 downto 0) := (OTHERS => '0'); + zero_chainout : IN STD_LOGIC := '0'; + rotate : IN STD_LOGIC := '0'; + shift_right : IN STD_LOGIC := '0'; + zero_loopback : IN STD_LOGIC := '0'; + accum_sload : IN STD_LOGIC := '0'; + sload_accum : IN STD_LOGIC := '0'; + negate : IN STD_LOGIC := '0'; + coefsel0 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel1 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel2 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel3 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0') + ); +end component; + +component altera_pll_reconfig_tasks + generic( + number_of_fplls :integer := 1 + ); +end component; + +component altera_syncram + generic ( + operation_mode : string := "BIDIR_DUAL_PORT"; + -- port a parameters + width_a : integer := 1; + widthad_a : integer := 1; + numwords_a : integer := 0; + -- registering parameters + -- port a read parameters + outdata_reg_a : string := "UNREGISTERED"; + -- clearing parameters + address_aclr_a : string := "NONE"; + outdata_aclr_a : string := "NONE"; + -- clearing parameters + -- port a write parameters + -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9 + width_byteena_a : integer := 1; + -- port b parameters + width_b : integer := 1; + widthad_b : integer := 1; + numwords_b : integer := 0; + -- registering parameters + -- port b read parameters + rdcontrol_reg_b : string := "CLOCK1"; + address_reg_b : string := "CLOCK1"; + outdata_reg_b : string := "UNREGISTERED"; + -- clearing parameters + outdata_aclr_b : string := "NONE"; + -- registering parameters + -- port b write parameters + indata_reg_b : string := "CLOCK1"; + -- registering parameter for the byte enable reister for port b + byteena_reg_b : string := "CLOCK1"; + -- clearing parameters + address_aclr_b : string := "NONE"; + -- clear parameter for byte enable port register + clock_enable_input_a : string := "NORMAL"; + clock_enable_output_a : string := "NORMAL"; + clock_enable_input_b : string := "NORMAL"; + clock_enable_output_b : string := "NORMAL"; + -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9 + width_byteena_b : integer := 1; + -- clock enable setting for the core + clock_enable_core_a : string := "USE_INPUT_CLKEN"; + clock_enable_core_b : string := "USE_INPUT_CLKEN"; + -- read-during-write-same-port setting + read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ"; + read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ"; + -- ECC status ports setting + enable_ecc : string := "FALSE"; + ecc_pipeline_stage_enabled : string := "FALSE"; + + width_eccstatus : integer := 3; + -- global parameters + -- width of a byte for byte enables + byte_size : integer := 0; + read_during_write_mode_mixed_ports: string := "DONT_CARE"; + -- ram block type choices are "AUTO", "M20K", "M10K" and "MLAB" + ram_block_type : string := "AUTO"; + -- determine whether LE support is turned on or off for altsyncram + implement_in_les : string := "OFF"; + -- determine whether RAM would be power up to uninitialized or not + power_up_uninitialized : string := "FALSE"; + + sim_show_memory_data_in_port_b_layout : string := "OFF"; + + -- general operation parameters + init_file : string := "UNUSED"; + init_file_layout : string := "UNUSED"; + maximum_depth : integer := 0; + intended_device_family : string := "Arria 10"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altsyncram" ); + port ( + wren_a : in std_logic := '0'; + wren_b : in std_logic := '0'; + rden_a : in std_logic := '1'; + rden_b : in std_logic := '1'; + data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1'); + data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1'); + address_a : in std_logic_vector(widthad_a - 1 downto 0); + address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1'); + + clock0 : in std_logic := '1'; + clock1 : in std_logic := 'Z'; + clocken0 : in std_logic := '1'; + clocken1 : in std_logic := '1'; + clocken2 : in std_logic := '1'; + clocken3 : in std_logic := '1'; + aclr0 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1'); + byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z'); + + addressstall_a : in std_logic := '0'; + addressstall_b : in std_logic := '0'; + + q_a : out std_logic_vector(width_a - 1 downto 0); + q_b : out std_logic_vector(width_b - 1 downto 0); + + eccstatus : out std_logic_vector(width_eccstatus-1 downto 0) := (others => '0') ); +end component; + +component fourteennm_m20k + generic ( + -- -------- GLOBAL PARAMETERS --------- + + clk0_clock_enable : STRING := "none"; + clk1_clock_enable : STRING := "none"; + enable_ecc : STRING := "false"; + ecc_pipeline_stage_enabled : STRING := "false"; + enable_ecc_encoder_bypass : STRING := "false"; + enable_force_to_zero : STRING := "false"; + enable_coherent_read : STRING := "false"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + logical_ram_name : STRING := "ram_name"; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + mixed_port_feed_through_mode : STRING := "dont_care"; + operation_mode : STRING := "dual_port"; + + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_a_byte_size : INTEGER := 0; + port_a_data_out_clear : STRING := "none"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_first_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + + port_b_address_clock : STRING := "clock1"; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + port_b_byte_size : INTEGER := 0; + port_b_data_out_clear : STRING := "none"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_first_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + + width_eccencparity : INTEGER := 8; + ram_block_type : STRING := "auto"; + width_eccstatus : INTEGER := 2; + + power_up_uninitialized : STRING := "false"; + lpm_type : STRING := "nadder_ram_block"; + lpm_hint : STRING := "true"; + connectivity_checking : STRING := "off"; + mem_init0 : STRING := ""; + mem_init1 : STRING := ""; + mem_init2 : STRING := ""; + mem_init3 : STRING := ""; + mem_init4 : STRING := ""; + mem_init5 : STRING := ""; + mem_init6 : STRING := ""; + mem_init7 : STRING := ""; + mem_init8 : STRING := ""; + mem_init9 : STRING := ""; + + bist_ena : STRING := "false" + + + ); + -- -------- PORT DECLARATIONS --------- + port ( + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + aclr : IN STD_LOGIC := '0'; + sclr : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr2 : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddrstall : IN STD_LOGIC := '0'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portare : IN STD_LOGIC := '1'; + portawe : IN STD_LOGIC := '0'; + eccencbypass : IN STD_LOGIC := '0'; + eccencparity : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '1'); + + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr2 : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddrstall : IN STD_LOGIC := '0'; + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbre : IN STD_LOGIC := '1'; + portbwe : IN STD_LOGIC := '0'; + + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); + eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0'); + + + dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000"; + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1' + ); + +end component; + +end altera_lnsim_components; diff --git a/Common/sim/altera/altera_mf.vhd b/Common/sim/altera/altera_mf.vhd new file mode 100644 index 0000000..3c1fc81 --- /dev/null +++ b/Common/sim/altera/altera_mf.vhd @@ -0,0 +1,52596 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 +---START_PACKAGE_HEADER----------------------------------------------------- +-- +-- Package Name : ALTERA_COMMON_CONVERSION +-- +-- Description : Common conversion functions +-- +---END_PACKAGE_HEADER-------------------------------------------------------- + +-- BEGINING OF PRIMITIVE + +Library ieee; +use ieee.std_logic_1164.all; +entity LCELL is + port( + a_in : in std_logic; + a_out : out std_logic); +end LCELL; +architecture BEHAVIOR of LCELL is +begin + a_out <= a_in; +end BEHAVIOR; + +-- BEGINING OF PACKAGE +Library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +-- PACKAGE DECLARATION +package ALTERA_COMMON_CONVERSION is +-- FUNCTION DECLARATION + function INT_TO_STR_RAM (value : in integer) return string; + function INT_TO_STR_ARITH (value : in integer) return string; + function HEX_STR_TO_INT (str : in string) return integer; + function BIN_STR_TO_INT (str : in string) return integer; + function OCT_STR_TO_INT (str : in string) return integer; + function INT_STR_TO_INT (str : in string) return integer; + function ALPHA_TOLOWER (given_string : in string) return string; + procedure SHRINK_LINE (str_line : inout line; pos : in integer); +end ALTERA_COMMON_CONVERSION; + +package body ALTERA_COMMON_CONVERSION is +-- This function converts an integer to a string +function INT_TO_STR_RAM (value : in integer) return string is +variable ivalue : integer := 0; +variable index : integer := 0; +variable digit : integer := 0; +variable line_no: string(8 downto 1) := " "; +begin + ivalue := value; + index := 1; + + while (ivalue > 0) loop + digit := ivalue MOD 10; + ivalue := ivalue/10; + case digit is + when 0 => line_no(index) := '0'; + when 1 => line_no(index) := '1'; + when 2 => line_no(index) := '2'; + when 3 => line_no(index) := '3'; + when 4 => line_no(index) := '4'; + when 5 => line_no(index) := '5'; + when 6 => line_no(index) := '6'; + when 7 => line_no(index) := '7'; + when 8 => line_no(index) := '8'; + when 9 => line_no(index) := '9'; + when others => + ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + index := index + 1; + end loop; + + return line_no; +end INT_TO_STR_RAM; + +function INT_TO_STR_ARITH (value : in integer) return string is + variable ivalue : integer := 0; + variable index : integer := 0; + variable digit : integer := 0; + variable temp: string(10 downto 1) := "0000000000"; +begin + ivalue := value; + index := 1; + + while (ivalue > 0) loop + digit := ivalue mod 10; + ivalue := ivalue/10; + + case digit is + when 0 => temp(index) := '0'; + when 1 => temp(index) := '1'; + when 2 => temp(index) := '2'; + when 3 => temp(index) := '3'; + when 4 => temp(index) := '4'; + when 5 => temp(index) := '5'; + when 6 => temp(index) := '6'; + when 7 => temp(index) := '7'; + when 8 => temp(index) := '8'; + when 9 => temp(index) := '9'; + when others => + ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + index := index + 1; + end loop; + + if value < 0 then + return '-'& temp(index downto 1); + else + return temp(index downto 1); + end if; +end INT_TO_STR_ARITH; + +-- This function converts a hexadecimal number to an integer +function HEX_STR_TO_INT (str : in string) return integer is +variable len : integer := str'length; +variable ivalue : integer := 0; +variable digit : integer := 0; +begin + for i in len downto 1 loop + case str(i) is + when '0' => digit := 0; + when '1' => digit := 1; + when '2' => digit := 2; + when '3' => digit := 3; + when '4' => digit := 4; + when '5' => digit := 5; + when '6' => digit := 6; + when '7' => digit := 7; + when '8' => digit := 8; + when '9' => digit := 9; + when 'A' => digit := 10; + when 'a' => digit := 10; + when 'B' => digit := 11; + when 'b' => digit := 11; + when 'C' => digit := 12; + when 'c' => digit := 12; + when 'D' => digit := 13; + when 'd' => digit := 13; + when 'E' => digit := 14; + when 'e' => digit := 14; + when 'F' => digit := 15; + when 'f' => digit := 15; + when others => + ASSERT FALSE + REPORT "Illegal hex character "& str(i) & "! " + SEVERITY ERROR; + end case; + ivalue := ivalue * 16 + digit; + end loop; + return ivalue; +end HEX_STR_TO_INT; + +-- This function converts a binary number to an integer +function BIN_STR_TO_INT (str : in string) return integer is +variable len : integer := str'length; +variable ivalue : integer := 0; +variable digit : integer := 0; +begin + for i in len downto 1 loop + case str(i) is + when '0' => digit := 0; + when '1' => digit := 1; + when others => + ASSERT FALSE + REPORT "Illegal bin character "& str(i) & "! " + SEVERITY ERROR; + end case; + ivalue := ivalue * 2 + digit; + end loop; + return ivalue; +end BIN_STR_TO_INT; + +-- This function converts a octadecimal number to an integer +function OCT_STR_TO_INT (str : in string) return integer is +variable len : integer := str'length; +variable ivalue : integer := 0; +variable digit : integer := 0; +begin + for i in len downto 1 loop + case str(i) is + when '0' => digit := 0; + when '1' => digit := 1; + when '2' => digit := 2; + when '3' => digit := 3; + when '4' => digit := 4; + when '5' => digit := 5; + when '6' => digit := 6; + when '7' => digit := 7; + when others => + ASSERT FALSE + REPORT "Illegal octadecimal character "& str(i) & "! " + SEVERITY ERROR; + end case; + ivalue := ivalue * 8 + digit; + end loop; + return ivalue; +end OCT_STR_TO_INT; + +-- This function converts a integer string to an integer +function INT_STR_TO_INT (str : in string) return integer is +variable len : integer := str'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case str(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& str(i) & "i n string parameter! " + SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& str(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; + +-- converts uppercase parameter values (e.g. "AUTO") to lowercase ("auto") +function ALPHA_TOLOWER (given_string : in string) return string is + -- VARIABLE DECLARATION + variable result_string : string(given_string'low to given_string'high); + +begin + for i in given_string'low to given_string'high loop + case given_string(i) is + when 'A' => result_string(i) := 'a'; + when 'B' => result_string(i) := 'b'; + when 'C' => result_string(i) := 'c'; + when 'D' => result_string(i) := 'd'; + when 'E' => result_string(i) := 'e'; + when 'F' => result_string(i) := 'f'; + when 'G' => result_string(i) := 'g'; + when 'H' => result_string(i) := 'h'; + when 'I' => result_string(i) := 'i'; + when 'J' => result_string(i) := 'j'; + when 'K' => result_string(i) := 'k'; + when 'L' => result_string(i) := 'l'; + when 'M' => result_string(i) := 'm'; + when 'N' => result_string(i) := 'n'; + when 'O' => result_string(i) := 'o'; + when 'P' => result_string(i) := 'p'; + when 'Q' => result_string(i) := 'q'; + when 'R' => result_string(i) := 'r'; + when 'S' => result_string(i) := 's'; + when 'T' => result_string(i) := 't'; + when 'U' => result_string(i) := 'u'; + when 'V' => result_string(i) := 'v'; + when 'W' => result_string(i) := 'w'; + when 'X' => result_string(i) := 'x'; + when 'Y' => result_string(i) := 'y'; + when 'Z' => result_string(i) := 'z'; + when others => result_string(i) := given_string(i); + end case; + end loop; + + return (result_string(given_string'low to given_string'high)); +end; + +-- This procedure "cuts" the str_line into desired length +procedure SHRINK_LINE (str_line : inout line; pos : in integer) is +subtype nstring is string(1 to pos); +variable str : nstring; +begin + if (pos >= 1) then + read(str_line, str); + end if; +end; +end ALTERA_COMMON_CONVERSION; +-- END OF PACKAGE + +---START_PACKAGE_HEADER----------------------------------------------------- +-- +-- Package Name : ALTERA_MF_HINT_EVALUATION +-- +-- Description : Common function to grep the value of altera specific parameters +-- within the lpm_hint parameter. +-- +---END_PACKAGE_HEADER-------------------------------------------------------- + +-- BEGINING OF PACKAGE +Library ieee; +use ieee.std_logic_1164.all; + +-- PACKAGE DECLARATION +package ALTERA_MF_HINT_EVALUATION is +-- FUNCTION DECLARATION + function get_parameter_value( constant given_string : string; + compare_param_name : string) return string; +end ALTERA_MF_HINT_EVALUATION; + +package body ALTERA_MF_HINT_EVALUATION is + +-- This function will search through the string (given string) to look for a match for the +-- a given parameter(compare_param_name). It will return the value for the given parameter. +function get_parameter_value( constant given_string : string; + compare_param_name : string) return string is + variable param_name_left_index : integer := given_string'length; + variable param_name_right_index : integer := given_string'length; + variable param_value_left_index : integer := given_string'length; + variable param_value_right_index : integer := given_string'length; + variable set_right_index : boolean := true; + variable extract_param_value : boolean := true; + variable extract_param_name : boolean := false; + variable param_found : boolean := false; + +begin + + -- checking every character of the given_string from right to left. + for i in given_string'length downto 1 loop + if (given_string(i) /= ' ') then + if (given_string(i) = '=') then + extract_param_value := false; + extract_param_name := true; + set_right_index := true; + elsif (given_string(i) = ',') then + extract_param_value := true; + extract_param_name := false; + set_right_index := true; + + if (compare_param_name = given_string(param_name_left_index to param_name_right_index)) then + param_found := true; -- the compare_param_name have been found in the given_string + exit; + end if; + else + if (extract_param_value = true) then + if (set_right_index = true) then + param_value_right_index := i; + set_right_index := false; + end if; + param_value_left_index := i; + elsif (extract_param_name = true) then + if (set_right_index = true) then + param_name_right_index := i; + set_right_index := false; + end if; + param_name_left_index := i; + end if; + end if; + end if; + end loop; + + -- for the case whether parameter's name is the left most part of the given_string + if (extract_param_name = true) then + if(compare_param_name = given_string(param_name_left_index to param_name_right_index)) then + param_found := true; + end if; + end if; + + if(param_found = true) then + return given_string(param_value_left_index to param_value_right_index); + else + return ""; -- return empty string if parameter not found + end if; + +end get_parameter_value; +end ALTERA_MF_HINT_EVALUATION; +-- END OF PACKAGE + +---START_PACKAGE_HEADER----------------------------------------------------- +-- +-- Package Name : ALTERA_DEVICE_FAMILIES +-- +-- Description : Common Altera device families comparison +-- +---END_PACKAGE_HEADER-------------------------------------------------------- + +-- BEGINING OF PACKAGES +Library ieee; +use ieee.std_logic_1164.all; + +-- PACKAGE DECLARATION +package ALTERA_DEVICE_FAMILIES is +-- FUNCTION DECLARATION + function IS_FAMILY_ARRIA10 (device : in string) return boolean; + function IS_FAMILY_ARRIAGX (device : in string) return boolean; + function IS_FAMILY_ARRIAIIGX (device : in string) return boolean; + function IS_FAMILY_ARRIAIIGZ (device : in string) return boolean; + function IS_FAMILY_ARRIAVGZ (device : in string) return boolean; + function IS_FAMILY_ARRIAV (device : in string) return boolean; + function IS_FAMILY_CYCLONEII (device : in string) return boolean; + function IS_FAMILY_CYCLONEIIILS (device : in string) return boolean; + function IS_FAMILY_CYCLONEIII (device : in string) return boolean; + function IS_FAMILY_CYCLONEIVE (device : in string) return boolean; + function IS_FAMILY_CYCLONEIVGX (device : in string) return boolean; + function IS_FAMILY_CYCLONEV (device : in string) return boolean; + function IS_FAMILY_CYCLONE (device : in string) return boolean; + function IS_FAMILY_HARDCOPYII (device : in string) return boolean; + function IS_FAMILY_HARDCOPYIII (device : in string) return boolean; + function IS_FAMILY_HARDCOPYIV (device : in string) return boolean; + function IS_FAMILY_MAX10 (device : in string) return boolean; + function IS_FAMILY_MAXII (device : in string) return boolean; + function IS_FAMILY_MAXV (device : in string) return boolean; + function IS_FAMILY_STRATIX10 (device : in string) return boolean; + function IS_FAMILY_STRATIXGX (device : in string) return boolean; + function IS_FAMILY_STRATIXIIGX (device : in string) return boolean; + function IS_FAMILY_STRATIXII (device : in string) return boolean; + function IS_FAMILY_STRATIXIII (device : in string) return boolean; + function IS_FAMILY_STRATIXIV (device : in string) return boolean; + function IS_FAMILY_STRATIXV (device : in string) return boolean; + function IS_FAMILY_STRATIX (device : in string) return boolean; + function FEATURE_FAMILY_STRATIXGX (device : in string) return boolean; + function FEATURE_FAMILY_CYCLONE (device : in string) return boolean; + function FEATURE_FAMILY_STRATIXIIGX (device : in string) return boolean; + function FEATURE_FAMILY_STRATIXIII (device : in string) return boolean; + function FEATURE_FAMILY_ARRIAVGZ (device : in string) return boolean; + function FEATURE_FAMILY_STRATIXV (device : in string) return boolean; + function FEATURE_FAMILY_ARRIA10 (device : in string) return boolean; + function FEATURE_FAMILY_STRATIXII (device : in string) return boolean; + function FEATURE_FAMILY_CYCLONEIVGX (device : in string) return boolean; + function FEATURE_FAMILY_CYCLONEIVE (device : in string) return boolean; + function FEATURE_FAMILY_CYCLONEIII (device : in string) return boolean; + function FEATURE_FAMILY_STRATIX_HC (device : in string) return boolean; + function FEATURE_FAMILY_HARDCOPYII (device : in string) return boolean; + function FEATURE_FAMILY_STRATIX (device : in string) return boolean; + function FEATURE_FAMILY_MAXII (device : in string) return boolean; + function FEATURE_FAMILY_MAXV (device : in string) return boolean; + function FEATURE_FAMILY_CYCLONEII (device : in string) return boolean; + function FEATURE_FAMILY_STRATIXIV (device : in string) return boolean; + function FEATURE_FAMILY_ARRIAIIGZ (device : in string) return boolean; + function FEATURE_FAMILY_ARRIAIIGX (device : in string) return boolean; + function FEATURE_FAMILY_HARDCOPYIII (device : in string) return boolean; + function FEATURE_FAMILY_HARDCOPYIV (device : in string) return boolean; + function FEATURE_FAMILY_CYCLONEV (device : in string) return boolean; + function FEATURE_FAMILY_ARRIAV (device : in string) return boolean; + function FEATURE_FAMILY_MAX10 (device : in string) return boolean; + function FEATURE_FAMILY_STRATIX10 (device : in string) return boolean; + function FEATURE_FAMILY_BASE_STRATIXII (device : in string) return boolean; + function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean; + function FEATURE_FAMILY_BASE_CYCLONEII (device : in string) return boolean; + function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean; + function FEATURE_FAMILY_BASE_CYCLONEIII (device : in string) return boolean; + function FEATURE_FAMILY_BASE_STRATIXIII (device : in string) return boolean; + function FEATURE_FAMILY_STRATIX_NONGX (device : in string) return boolean; + function FEATURE_FAMILY_HAS_ALTERA_MULT_ADD_FLOW (device : in string) return boolean; + function FEATURE_FAMILY_IS_ALTMULT_ADD_EOL (device : in string) return boolean; + function FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM (device : in string) return boolean; + function FEATURE_FAMILY_HAS_MEGARAM (device : in string) return boolean; + function FEATURE_FAMILY_HAS_M512 (device : in string) return boolean; + function FEATURE_FAMILY_HAS_LUTRAM (device : in string) return boolean; + function FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM (device : in string) return boolean; + function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM (device : in string) return boolean; + function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM (device : in string) return boolean; + function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL (device : in string) return boolean; + function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL (device : in string) return boolean; + function FEATURE_FAMILY_USES_STRATIXIII_PLL (device : in string) return boolean; + function FEATURE_FAMILY_HAS_FLEXIBLE_LVDS (device : in string) return boolean; + function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO (device : in string) return boolean; + function IS_VALID_FAMILY (device: in string) return boolean; +end ALTERA_DEVICE_FAMILIES; + +package body ALTERA_DEVICE_FAMILIES is + + +function IS_FAMILY_ARRIA10 (device : in string) return boolean is +variable is_arria10 : boolean := false; +begin + if ((device = "Arria 10") or (device = "ARRIA 10") or (device = "arria 10") or (device = "Arria10") or (device = "ARRIA10") or (device = "arria10") or (device = "Arria VI") or (device = "ARRIA VI") or (device = "arria vi") or (device = "ArriaVI") or (device = "ARRIAVI") or (device = "arriavi") or (device = "Night Fury") or (device = "NIGHT FURY") or (device = "night fury") or (device = "nightfury") or (device = "NIGHTFURY") or (device = "Arria 10 (GX/SX/GT)") or (device = "ARRIA 10 (GX/SX/GT)") or (device = "arria 10 (gx/sx/gt)") or (device = "Arria10(GX/SX/GT)") or (device = "ARRIA10(GX/SX/GT)") or (device = "arria10(gx/sx/gt)") or (device = "Arria 10 (GX)") or (device = "ARRIA 10 (GX)") or (device = "arria 10 (gx)") or (device = "Arria10(GX)") or (device = "ARRIA10(GX)") or (device = "arria10(gx)") or (device = "Arria 10 (SX)") or (device = "ARRIA 10 (SX)") or (device = "arria 10 (sx)") or (device = "Arria10(SX)") or (device = "ARRIA10(SX)") or (device = "arria10(sx)") or (device = "Arria 10 (GT)") or (device = "ARRIA 10 (GT)") or (device = "arria 10 (gt)") or (device = "Arria10(GT)") or (device = "ARRIA10(GT)") or (device = "arria10(gt)")) + then + is_arria10 := true; + end if; + return is_arria10; +end IS_FAMILY_ARRIA10; + +function IS_FAMILY_ARRIAGX (device : in string) return boolean is +variable is_arriagx : boolean := false; +begin + if ((device = "Arria GX") or (device = "ARRIA GX") or (device = "arria gx") or (device = "ArriaGX") or (device = "ARRIAGX") or (device = "arriagx") or (device = "Stratix II GX Lite") or (device = "STRATIX II GX LITE") or (device = "stratix ii gx lite") or (device = "StratixIIGXLite") or (device = "STRATIXIIGXLITE") or (device = "stratixiigxlite")) + then + is_arriagx := true; + end if; + return is_arriagx; +end IS_FAMILY_ARRIAGX; + +function IS_FAMILY_ARRIAIIGX (device : in string) return boolean is +variable is_arriaiigx : boolean := false; +begin + if ((device = "Arria II GX") or (device = "ARRIA II GX") or (device = "arria ii gx") or (device = "ArriaIIGX") or (device = "ARRIAIIGX") or (device = "arriaiigx") or (device = "Arria IIGX") or (device = "ARRIA IIGX") or (device = "arria iigx") or (device = "ArriaII GX") or (device = "ARRIAII GX") or (device = "arriaii gx") or (device = "Arria II") or (device = "ARRIA II") or (device = "arria ii") or (device = "ArriaII") or (device = "ARRIAII") or (device = "arriaii") or (device = "Arria II (GX/E)") or (device = "ARRIA II (GX/E)") or (device = "arria ii (gx/e)") or (device = "ArriaII(GX/E)") or (device = "ARRIAII(GX/E)") or (device = "arriaii(gx/e)") or (device = "PIRANHA") or (device = "piranha")) + then + is_arriaiigx := true; + end if; + return is_arriaiigx; +end IS_FAMILY_ARRIAIIGX; + +function IS_FAMILY_ARRIAIIGZ (device : in string) return boolean is +variable is_arriaiigz : boolean := false; +begin + if ((device = "Arria II GZ") or (device = "ARRIA II GZ") or (device = "arria ii gz") or (device = "ArriaII GZ") or (device = "ARRIAII GZ") or (device = "arriaii gz") or (device = "Arria IIGZ") or (device = "ARRIA IIGZ") or (device = "arria iigz") or (device = "ArriaIIGZ") or (device = "ARRIAIIGZ") or (device = "arriaiigz")) + then + is_arriaiigz := true; + end if; + return is_arriaiigz; +end IS_FAMILY_ARRIAIIGZ; + +function IS_FAMILY_ARRIAVGZ (device : in string) return boolean is +variable is_arriavgz : boolean := false; +begin + if ((device = "Arria V GZ") or (device = "ARRIA V GZ") or (device = "arria v gz") or (device = "ArriaVGZ") or (device = "ARRIAVGZ") or (device = "arriavgz")) + then + is_arriavgz := true; + end if; + return is_arriavgz; +end IS_FAMILY_ARRIAVGZ; + +function IS_FAMILY_ARRIAV (device : in string) return boolean is +variable is_arriav : boolean := false; +begin + if ((device = "Arria V") or (device = "ARRIA V") or (device = "arria v") or (device = "Arria V (GT/GX)") or (device = "ARRIA V (GT/GX)") or (device = "arria v (gt/gx)") or (device = "ArriaV(GT/GX)") or (device = "ARRIAV(GT/GX)") or (device = "arriav(gt/gx)") or (device = "ArriaV") or (device = "ARRIAV") or (device = "arriav") or (device = "Arria V (GT/GX/ST/SX)") or (device = "ARRIA V (GT/GX/ST/SX)") or (device = "arria v (gt/gx/st/sx)") or (device = "ArriaV(GT/GX/ST/SX)") or (device = "ARRIAV(GT/GX/ST/SX)") or (device = "arriav(gt/gx/st/sx)") or (device = "Arria V (GT)") or (device = "ARRIA V (GT)") or (device = "arria v (gt)") or (device = "ArriaV(GT)") or (device = "ARRIAV(GT)") or (device = "arriav(gt)") or (device = "Arria V (GX)") or (device = "ARRIA V (GX)") or (device = "arria v (gx)") or (device = "ArriaV(GX)") or (device = "ARRIAV(GX)") or (device = "arriav(gx)") or (device = "Arria V (ST)") or (device = "ARRIA V (ST)") or (device = "arria v (st)") or (device = "ArriaV(ST)") or (device = "ARRIAV(ST)") or (device = "arriav(st)") or (device = "Arria V (SX)") or (device = "ARRIA V (SX)") or (device = "arria v (sx)") or (device = "ArriaV(SX)") or (device = "ARRIAV(SX)") or (device = "arriav(sx)")) + then + is_arriav := true; + end if; + return is_arriav; +end IS_FAMILY_ARRIAV; + +function IS_FAMILY_CYCLONEII (device : in string) return boolean is +variable is_cycloneii : boolean := false; +begin + if ((device = "Cyclone II") or (device = "CYCLONE II") or (device = "cyclone ii") or (device = "Cycloneii") or (device = "CYCLONEII") or (device = "cycloneii") or (device = "Magellan") or (device = "MAGELLAN") or (device = "magellan") or (device = "CycloneII") or (device = "CYCLONEII") or (device = "cycloneii")) + then + is_cycloneii := true; + end if; + return is_cycloneii; +end IS_FAMILY_CYCLONEII; + +function IS_FAMILY_CYCLONEIIILS (device : in string) return boolean is +variable is_cycloneiiils : boolean := false; +begin + if ((device = "Cyclone III LS") or (device = "CYCLONE III LS") or (device = "cyclone iii ls") or (device = "CycloneIIILS") or (device = "CYCLONEIIILS") or (device = "cycloneiiils") or (device = "Cyclone III LPS") or (device = "CYCLONE III LPS") or (device = "cyclone iii lps") or (device = "Cyclone LPS") or (device = "CYCLONE LPS") or (device = "cyclone lps") or (device = "CycloneLPS") or (device = "CYCLONELPS") or (device = "cyclonelps") or (device = "Tarpon") or (device = "TARPON") or (device = "tarpon") or (device = "Cyclone IIIE") or (device = "CYCLONE IIIE") or (device = "cyclone iiie")) + then + is_cycloneiiils := true; + end if; + return is_cycloneiiils; +end IS_FAMILY_CYCLONEIIILS; + +function IS_FAMILY_CYCLONEIII (device : in string) return boolean is +variable is_cycloneiii : boolean := false; +begin + if ((device = "Cyclone III") or (device = "CYCLONE III") or (device = "cyclone iii") or (device = "CycloneIII") or (device = "CYCLONEIII") or (device = "cycloneiii") or (device = "Barracuda") or (device = "BARRACUDA") or (device = "barracuda") or (device = "Cuda") or (device = "CUDA") or (device = "cuda") or (device = "CIII") or (device = "ciii")) + then + is_cycloneiii := true; + end if; + return is_cycloneiii; +end IS_FAMILY_CYCLONEIII; + +function IS_FAMILY_CYCLONEIVE (device : in string) return boolean is +variable is_cycloneive : boolean := false; +begin + if ((device = "Cyclone IV E") or (device = "CYCLONE IV E") or (device = "cyclone iv e") or (device = "CycloneIV E") or (device = "CYCLONEIV E") or (device = "cycloneiv e") or (device = "Cyclone IVE") or (device = "CYCLONE IVE") or (device = "cyclone ive") or (device = "CycloneIVE") or (device = "CYCLONEIVE") or (device = "cycloneive")) + then + is_cycloneive := true; + end if; + return is_cycloneive; +end IS_FAMILY_CYCLONEIVE; + +function IS_FAMILY_CYCLONEIVGX (device : in string) return boolean is +variable is_cycloneivgx : boolean := false; +begin + if ((device = "Cyclone IV GX") or (device = "CYCLONE IV GX") or (device = "cyclone iv gx") or (device = "Cyclone IVGX") or (device = "CYCLONE IVGX") or (device = "cyclone ivgx") or (device = "CycloneIV GX") or (device = "CYCLONEIV GX") or (device = "cycloneiv gx") or (device = "CycloneIVGX") or (device = "CYCLONEIVGX") or (device = "cycloneivgx") or (device = "Cyclone IV") or (device = "CYCLONE IV") or (device = "cyclone iv") or (device = "CycloneIV") or (device = "CYCLONEIV") or (device = "cycloneiv") or (device = "Cyclone IV (GX)") or (device = "CYCLONE IV (GX)") or (device = "cyclone iv (gx)") or (device = "CycloneIV(GX)") or (device = "CYCLONEIV(GX)") or (device = "cycloneiv(gx)") or (device = "Cyclone III GX") or (device = "CYCLONE III GX") or (device = "cyclone iii gx") or (device = "CycloneIII GX") or (device = "CYCLONEIII GX") or (device = "cycloneiii gx") or (device = "Cyclone IIIGX") or (device = "CYCLONE IIIGX") or (device = "cyclone iiigx") or (device = "CycloneIIIGX") or (device = "CYCLONEIIIGX") or (device = "cycloneiiigx") or (device = "Cyclone III GL") or (device = "CYCLONE III GL") or (device = "cyclone iii gl") or (device = "CycloneIII GL") or (device = "CYCLONEIII GL") or (device = "cycloneiii gl") or (device = "Cyclone IIIGL") or (device = "CYCLONE IIIGL") or (device = "cyclone iiigl") or (device = "CycloneIIIGL") or (device = "CYCLONEIIIGL") or (device = "cycloneiiigl") or (device = "Stingray") or (device = "STINGRAY") or (device = "stingray")) + then + is_cycloneivgx := true; + end if; + return is_cycloneivgx; +end IS_FAMILY_CYCLONEIVGX; + +function IS_FAMILY_CYCLONEV (device : in string) return boolean is +variable is_cyclonev : boolean := false; +begin + if ((device = "Cyclone V") or (device = "CYCLONE V") or (device = "cyclone v") or (device = "CycloneV") or (device = "CYCLONEV") or (device = "cyclonev") or (device = "Cyclone V (GT/GX/E/SX)") or (device = "CYCLONE V (GT/GX/E/SX)") or (device = "cyclone v (gt/gx/e/sx)") or (device = "CycloneV(GT/GX/E/SX)") or (device = "CYCLONEV(GT/GX/E/SX)") or (device = "cyclonev(gt/gx/e/sx)") or (device = "Cyclone V (E/GX/GT/SX/SE/ST)") or (device = "CYCLONE V (E/GX/GT/SX/SE/ST)") or (device = "cyclone v (e/gx/gt/sx/se/st)") or (device = "CycloneV(E/GX/GT/SX/SE/ST)") or (device = "CYCLONEV(E/GX/GT/SX/SE/ST)") or (device = "cyclonev(e/gx/gt/sx/se/st)") or (device = "Cyclone V (E)") or (device = "CYCLONE V (E)") or (device = "cyclone v (e)") or (device = "CycloneV(E)") or (device = "CYCLONEV(E)") or (device = "cyclonev(e)") or (device = "Cyclone V (GX)") or (device = "CYCLONE V (GX)") or (device = "cyclone v (gx)") or (device = "CycloneV(GX)") or (device = "CYCLONEV(GX)") or (device = "cyclonev(gx)") or (device = "Cyclone V (GT)") or (device = "CYCLONE V (GT)") or (device = "cyclone v (gt)") or (device = "CycloneV(GT)") or (device = "CYCLONEV(GT)") or (device = "cyclonev(gt)") or (device = "Cyclone V (SX)") or (device = "CYCLONE V (SX)") or (device = "cyclone v (sx)") or (device = "CycloneV(SX)") or (device = "CYCLONEV(SX)") or (device = "cyclonev(sx)") or (device = "Cyclone V (SE)") or (device = "CYCLONE V (SE)") or (device = "cyclone v (se)") or (device = "CycloneV(SE)") or (device = "CYCLONEV(SE)") or (device = "cyclonev(se)") or (device = "Cyclone V (ST)") or (device = "CYCLONE V (ST)") or (device = "cyclone v (st)") or (device = "CycloneV(ST)") or (device = "CYCLONEV(ST)") or (device = "cyclonev(st)")) + then + is_cyclonev := true; + end if; + return is_cyclonev; +end IS_FAMILY_CYCLONEV; + +function IS_FAMILY_CYCLONE (device : in string) return boolean is +variable is_cyclone : boolean := false; +begin + if ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado")) + then + is_cyclone := true; + end if; + return is_cyclone; +end IS_FAMILY_CYCLONE; + +function IS_FAMILY_HARDCOPYII (device : in string) return boolean is +variable is_hardcopyii : boolean := false; +begin + if ((device = "HardCopy II") or (device = "HARDCOPY II") or (device = "hardcopy ii") or (device = "HardCopyII") or (device = "HARDCOPYII") or (device = "hardcopyii") or (device = "Fusion") or (device = "FUSION") or (device = "fusion")) + then + is_hardcopyii := true; + end if; + return is_hardcopyii; +end IS_FAMILY_HARDCOPYII; + +function IS_FAMILY_HARDCOPYIII (device : in string) return boolean is +variable is_hardcopyiii : boolean := false; +begin + if ((device = "HardCopy III") or (device = "HARDCOPY III") or (device = "hardcopy iii") or (device = "HardCopyIII") or (device = "HARDCOPYIII") or (device = "hardcopyiii") or (device = "HCX") or (device = "hcx")) + then + is_hardcopyiii := true; + end if; + return is_hardcopyiii; +end IS_FAMILY_HARDCOPYIII; + +function IS_FAMILY_HARDCOPYIV (device : in string) return boolean is +variable is_hardcopyiv : boolean := false; +begin + if ((device = "HardCopy IV") or (device = "HARDCOPY IV") or (device = "hardcopy iv") or (device = "HardCopyIV") or (device = "HARDCOPYIV") or (device = "hardcopyiv") or (device = "HardCopy IV (GX)") or (device = "HARDCOPY IV (GX)") or (device = "hardcopy iv (gx)") or (device = "HardCopy IV (E)") or (device = "HARDCOPY IV (E)") or (device = "hardcopy iv (e)") or (device = "HardCopyIV(GX)") or (device = "HARDCOPYIV(GX)") or (device = "hardcopyiv(gx)") or (device = "HardCopyIV(E)") or (device = "HARDCOPYIV(E)") or (device = "hardcopyiv(e)") or (device = "HCXIV") or (device = "hcxiv") or (device = "HardCopy IV (GX/E)") or (device = "HARDCOPY IV (GX/E)") or (device = "hardcopy iv (gx/e)") or (device = "HardCopy IV (E/GX)") or (device = "HARDCOPY IV (E/GX)") or (device = "hardcopy iv (e/gx)") or (device = "HardCopyIV(GX/E)") or (device = "HARDCOPYIV(GX/E)") or (device = "hardcopyiv(gx/e)") or (device = "HardCopyIV(E/GX)") or (device = "HARDCOPYIV(E/GX)") or (device = "hardcopyiv(e/gx)")) + then + is_hardcopyiv := true; + end if; + return is_hardcopyiv; +end IS_FAMILY_HARDCOPYIV; + +function IS_FAMILY_MAX10 (device : in string) return boolean is +variable is_max10 : boolean := false; +begin + if ((device = "MAX 10") or (device = "max 10") or (device = "MAX 10 FPGA") or (device = "max 10 fpga") or (device = "Zippleback") or (device = "ZIPPLEBACK") or (device = "zippleback") or (device = "MAX10") or (device = "max10") or (device = "MAX 10 (DA/DF/DC/SA/SF/SC)") or (device = "max 10 (da/df/dc/sa/sf/sc)") or (device = "MAX10(DA/DF/DC/SA/SF/SC)") or (device = "max10(da/df/dc/sa/sf/sc)") or (device = "MAX 10 (DA)") or (device = "max 10 (da)") or (device = "MAX10(DA)") or (device = "max10(da)") or (device = "MAX 10 (DF)") or (device = "max 10 (df)") or (device = "MAX10(DF)") or (device = "max10(df)") or (device = "MAX 10 (DC)") or (device = "max 10 (dc)") or (device = "MAX10(DC)") or (device = "max10(dc)") or (device = "MAX 10 (SA)") or (device = "max 10 (sa)") or (device = "MAX10(SA)") or (device = "max10(sa)") or (device = "MAX 10 (SF)") or (device = "max 10 (sf)") or (device = "MAX10(SF)") or (device = "max10(sf)") or (device = "MAX 10 (SC)") or (device = "max 10 (sc)") or (device = "MAX10(SC)") or (device = "max10(sc)")) + then + is_max10 := true; + end if; + return is_max10; +end IS_FAMILY_MAX10; + +function IS_FAMILY_MAXII (device : in string) return boolean is +variable is_maxii : boolean := false; +begin + if ((device = "MAX II") or (device = "max ii") or (device = "MAXII") or (device = "maxii") or (device = "Tsunami") or (device = "TSUNAMI") or (device = "tsunami")) + then + is_maxii := true; + end if; + return is_maxii; +end IS_FAMILY_MAXII; + +function IS_FAMILY_MAXV (device : in string) return boolean is +variable is_maxv : boolean := false; +begin + if ((device = "MAX V") or (device = "max v") or (device = "MAXV") or (device = "maxv") or (device = "Jade") or (device = "JADE") or (device = "jade")) + then + is_maxv := true; + end if; + return is_maxv; +end IS_FAMILY_MAXV; + +function IS_FAMILY_STRATIX10 (device : in string) return boolean is +variable is_stratix10 : boolean := false; +begin + if ((device = "Stratix 10") or (device = "STRATIX 10") or (device = "stratix 10") or (device = "Stratix10") or (device = "STRATIX10") or (device = "stratix10") or (device = "nadder") or (device = "NADDER")) + then + is_stratix10 := true; + end if; + return is_stratix10; +end IS_FAMILY_STRATIX10; + +function IS_FAMILY_STRATIXGX (device : in string) return boolean is +variable is_stratixgx : boolean := false; +begin + if ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora")) + then + is_stratixgx := true; + end if; + return is_stratixgx; +end IS_FAMILY_STRATIXGX; + +function IS_FAMILY_STRATIXIIGX (device : in string) return boolean is +variable is_stratixiigx : boolean := false; +begin + if ((device = "Stratix II GX") or (device = "STRATIX II GX") or (device = "stratix ii gx") or (device = "StratixIIGX") or (device = "STRATIXIIGX") or (device = "stratixiigx")) + then + is_stratixiigx := true; + end if; + return is_stratixiigx; +end IS_FAMILY_STRATIXIIGX; + +function IS_FAMILY_STRATIXII (device : in string) return boolean is +variable is_stratixii : boolean := false; +begin + if ((device = "Stratix II") or (device = "STRATIX II") or (device = "stratix ii") or (device = "StratixII") or (device = "STRATIXII") or (device = "stratixii") or (device = "Armstrong") or (device = "ARMSTRONG") or (device = "armstrong")) + then + is_stratixii := true; + end if; + return is_stratixii; +end IS_FAMILY_STRATIXII; + +function IS_FAMILY_STRATIXIII (device : in string) return boolean is +variable is_stratixiii : boolean := false; +begin + if ((device = "Stratix III") or (device = "STRATIX III") or (device = "stratix iii") or (device = "StratixIII") or (device = "STRATIXIII") or (device = "stratixiii") or (device = "Titan") or (device = "TITAN") or (device = "titan") or (device = "SIII") or (device = "siii")) + then + is_stratixiii := true; + end if; + return is_stratixiii; +end IS_FAMILY_STRATIXIII; + +function IS_FAMILY_STRATIXIV (device : in string) return boolean is +variable is_stratixiv : boolean := false; +begin + if ((device = "Stratix IV") or (device = "STRATIX IV") or (device = "stratix iv") or (device = "TGX") or (device = "tgx") or (device = "StratixIV") or (device = "STRATIXIV") or (device = "stratixiv") or (device = "Stratix IV (GT)") or (device = "STRATIX IV (GT)") or (device = "stratix iv (gt)") or (device = "Stratix IV (GX)") or (device = "STRATIX IV (GX)") or (device = "stratix iv (gx)") or (device = "Stratix IV (E)") or (device = "STRATIX IV (E)") or (device = "stratix iv (e)") or (device = "StratixIV(GT)") or (device = "STRATIXIV(GT)") or (device = "stratixiv(gt)") or (device = "StratixIV(GX)") or (device = "STRATIXIV(GX)") or (device = "stratixiv(gx)") or (device = "StratixIV(E)") or (device = "STRATIXIV(E)") or (device = "stratixiv(e)") or (device = "StratixIIIGX") or (device = "STRATIXIIIGX") or (device = "stratixiiigx") or (device = "Stratix IV (GT/GX/E)") or (device = "STRATIX IV (GT/GX/E)") or (device = "stratix iv (gt/gx/e)") or (device = "Stratix IV (GT/E/GX)") or (device = "STRATIX IV (GT/E/GX)") or (device = "stratix iv (gt/e/gx)") or (device = "Stratix IV (E/GT/GX)") or (device = "STRATIX IV (E/GT/GX)") or (device = "stratix iv (e/gt/gx)") or (device = "Stratix IV (E/GX/GT)") or (device = "STRATIX IV (E/GX/GT)") or (device = "stratix iv (e/gx/gt)") or (device = "StratixIV(GT/GX/E)") or (device = "STRATIXIV(GT/GX/E)") or (device = "stratixiv(gt/gx/e)") or (device = "StratixIV(GT/E/GX)") or (device = "STRATIXIV(GT/E/GX)") or (device = "stratixiv(gt/e/gx)") or (device = "StratixIV(E/GX/GT)") or (device = "STRATIXIV(E/GX/GT)") or (device = "stratixiv(e/gx/gt)") or (device = "StratixIV(E/GT/GX)") or (device = "STRATIXIV(E/GT/GX)") or (device = "stratixiv(e/gt/gx)") or (device = "Stratix IV (GX/E)") or (device = "STRATIX IV (GX/E)") or (device = "stratix iv (gx/e)") or (device = "StratixIV(GX/E)") or (device = "STRATIXIV(GX/E)") or (device = "stratixiv(gx/e)")) + then + is_stratixiv := true; + end if; + return is_stratixiv; +end IS_FAMILY_STRATIXIV; + +function IS_FAMILY_STRATIXV (device : in string) return boolean is +variable is_stratixv : boolean := false; +begin + if ((device = "Stratix V") or (device = "STRATIX V") or (device = "stratix v") or (device = "StratixV") or (device = "STRATIXV") or (device = "stratixv") or (device = "Stratix V (GS)") or (device = "STRATIX V (GS)") or (device = "stratix v (gs)") or (device = "StratixV(GS)") or (device = "STRATIXV(GS)") or (device = "stratixv(gs)") or (device = "Stratix V (GT)") or (device = "STRATIX V (GT)") or (device = "stratix v (gt)") or (device = "StratixV(GT)") or (device = "STRATIXV(GT)") or (device = "stratixv(gt)") or (device = "Stratix V (GX)") or (device = "STRATIX V (GX)") or (device = "stratix v (gx)") or (device = "StratixV(GX)") or (device = "STRATIXV(GX)") or (device = "stratixv(gx)") or (device = "Stratix V (GS/GX)") or (device = "STRATIX V (GS/GX)") or (device = "stratix v (gs/gx)") or (device = "StratixV(GS/GX)") or (device = "STRATIXV(GS/GX)") or (device = "stratixv(gs/gx)") or (device = "Stratix V (GS/GT)") or (device = "STRATIX V (GS/GT)") or (device = "stratix v (gs/gt)") or (device = "StratixV(GS/GT)") or (device = "STRATIXV(GS/GT)") or (device = "stratixv(gs/gt)") or (device = "Stratix V (GT/GX)") or (device = "STRATIX V (GT/GX)") or (device = "stratix v (gt/gx)") or (device = "StratixV(GT/GX)") or (device = "STRATIXV(GT/GX)") or (device = "stratixv(gt/gx)") or (device = "Stratix V (GX/GS)") or (device = "STRATIX V (GX/GS)") or (device = "stratix v (gx/gs)") or (device = "StratixV(GX/GS)") or (device = "STRATIXV(GX/GS)") or (device = "stratixv(gx/gs)") or (device = "Stratix V (GT/GS)") or (device = "STRATIX V (GT/GS)") or (device = "stratix v (gt/gs)") or (device = "StratixV(GT/GS)") or (device = "STRATIXV(GT/GS)") or (device = "stratixv(gt/gs)") or (device = "Stratix V (GX/GT)") or (device = "STRATIX V (GX/GT)") or (device = "stratix v (gx/gt)") or (device = "StratixV(GX/GT)") or (device = "STRATIXV(GX/GT)") or (device = "stratixv(gx/gt)") or (device = "Stratix V (GS/GT/GX)") or (device = "STRATIX V (GS/GT/GX)") or (device = "stratix v (gs/gt/gx)") or (device = "Stratix V (GS/GX/GT)") or (device = "STRATIX V (GS/GX/GT)") or (device = "stratix v (gs/gx/gt)") or (device = "Stratix V (GT/GS/GX)") or (device = "STRATIX V (GT/GS/GX)") or (device = "stratix v (gt/gs/gx)") or (device = "Stratix V (GT/GX/GS)") or (device = "STRATIX V (GT/GX/GS)") or (device = "stratix v (gt/gx/gs)") or (device = "Stratix V (GX/GS/GT)") or (device = "STRATIX V (GX/GS/GT)") or (device = "stratix v (gx/gs/gt)") or (device = "Stratix V (GX/GT/GS)") or (device = "STRATIX V (GX/GT/GS)") or (device = "stratix v (gx/gt/gs)") or (device = "StratixV(GS/GT/GX)") or (device = "STRATIXV(GS/GT/GX)") or (device = "stratixv(gs/gt/gx)") or (device = "StratixV(GS/GX/GT)") or (device = "STRATIXV(GS/GX/GT)") or (device = "stratixv(gs/gx/gt)") or (device = "StratixV(GT/GS/GX)") or (device = "STRATIXV(GT/GS/GX)") or (device = "stratixv(gt/gs/gx)") or (device = "StratixV(GT/GX/GS)") or (device = "STRATIXV(GT/GX/GS)") or (device = "stratixv(gt/gx/gs)") or (device = "StratixV(GX/GS/GT)") or (device = "STRATIXV(GX/GS/GT)") or (device = "stratixv(gx/gs/gt)") or (device = "StratixV(GX/GT/GS)") or (device = "STRATIXV(GX/GT/GS)") or (device = "stratixv(gx/gt/gs)") or (device = "Stratix V (GS/GT/GX/E)") or (device = "STRATIX V (GS/GT/GX/E)") or (device = "stratix v (gs/gt/gx/e)") or (device = "StratixV(GS/GT/GX/E)") or (device = "STRATIXV(GS/GT/GX/E)") or (device = "stratixv(gs/gt/gx/e)") or (device = "Stratix V (E)") or (device = "STRATIX V (E)") or (device = "stratix v (e)") or (device = "StratixV(E)") or (device = "STRATIXV(E)") or (device = "stratixv(e)")) + then + is_stratixv := true; + end if; + return is_stratixv; +end IS_FAMILY_STRATIXV; + +function IS_FAMILY_STRATIX (device : in string) return boolean is +variable is_stratix : boolean := false; +begin + if ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager")) + then + is_stratix := true; + end if; + return is_stratix; +end IS_FAMILY_STRATIX; + +function FEATURE_FAMILY_STRATIXGX (device : in string) return boolean is +variable var_family_stratixgx : boolean := false; +begin + if (IS_FAMILY_STRATIXGX(device) ) + then + var_family_stratixgx := true; + end if; + return var_family_stratixgx; +end FEATURE_FAMILY_STRATIXGX; + + +function FEATURE_FAMILY_CYCLONE (device : in string) return boolean is +variable var_family_cyclone : boolean := false; +begin + if (IS_FAMILY_CYCLONE(device) ) + then + var_family_cyclone := true; + end if; + return var_family_cyclone; +end FEATURE_FAMILY_CYCLONE; + + +function FEATURE_FAMILY_STRATIXIIGX (device : in string) return boolean is +variable var_family_stratixiigx : boolean := false; +begin + if (IS_FAMILY_STRATIXIIGX(device) or IS_FAMILY_ARRIAGX(device) ) + then + var_family_stratixiigx := true; + end if; + return var_family_stratixiigx; +end FEATURE_FAMILY_STRATIXIIGX; + + +function FEATURE_FAMILY_STRATIXIII (device : in string) return boolean is +variable var_family_stratixiii : boolean := false; +begin + if (IS_FAMILY_STRATIXIII(device) or FEATURE_FAMILY_STRATIXIV(device) or FEATURE_FAMILY_HARDCOPYIII(device) ) + then + var_family_stratixiii := true; + end if; + return var_family_stratixiii; +end FEATURE_FAMILY_STRATIXIII; + + +function FEATURE_FAMILY_ARRIAVGZ (device : in string) return boolean is +variable var_family_arriavgz : boolean := false; +begin + if (IS_FAMILY_ARRIAVGZ(device) ) + then + var_family_arriavgz := true; + end if; + return var_family_arriavgz; +end FEATURE_FAMILY_ARRIAVGZ; + + +function FEATURE_FAMILY_STRATIXV (device : in string) return boolean is +variable var_family_stratixv : boolean := false; +begin + if (IS_FAMILY_STRATIXV(device) or FEATURE_FAMILY_ARRIAVGZ(device) ) + then + var_family_stratixv := true; + end if; + return var_family_stratixv; +end FEATURE_FAMILY_STRATIXV; + + +function FEATURE_FAMILY_ARRIA10 (device : in string) return boolean is +variable var_family_arria10 : boolean := false; +begin + if (IS_FAMILY_ARRIA10(device) or IS_FAMILY_ARRIA10(device) ) + then + var_family_arria10 := true; + end if; + return var_family_arria10; +end FEATURE_FAMILY_ARRIA10; + + +function FEATURE_FAMILY_STRATIXII (device : in string) return boolean is +variable var_family_stratixii : boolean := false; +begin + if (IS_FAMILY_STRATIXII(device) or IS_FAMILY_HARDCOPYII(device) or FEATURE_FAMILY_STRATIXIIGX(device) or FEATURE_FAMILY_STRATIXIII(device) ) + then + var_family_stratixii := true; + end if; + return var_family_stratixii; +end FEATURE_FAMILY_STRATIXII; + + +function FEATURE_FAMILY_CYCLONEIVGX (device : in string) return boolean is +variable var_family_cycloneivgx : boolean := false; +begin + if (IS_FAMILY_CYCLONEIVGX(device) or IS_FAMILY_CYCLONEIVGX(device) ) + then + var_family_cycloneivgx := true; + end if; + return var_family_cycloneivgx; +end FEATURE_FAMILY_CYCLONEIVGX; + + +function FEATURE_FAMILY_CYCLONEIVE (device : in string) return boolean is +variable var_family_cycloneive : boolean := false; +begin + if (IS_FAMILY_CYCLONEIVE(device) ) + then + var_family_cycloneive := true; + end if; + return var_family_cycloneive; +end FEATURE_FAMILY_CYCLONEIVE; + + +function FEATURE_FAMILY_CYCLONEIII (device : in string) return boolean is +variable var_family_cycloneiii : boolean := false; +begin + if (IS_FAMILY_CYCLONEIII(device) or IS_FAMILY_CYCLONEIIILS(device) or FEATURE_FAMILY_CYCLONEIVGX(device) or FEATURE_FAMILY_CYCLONEIVE(device) or FEATURE_FAMILY_MAX10(device) ) + then + var_family_cycloneiii := true; + end if; + return var_family_cycloneiii; +end FEATURE_FAMILY_CYCLONEIII; + + +function FEATURE_FAMILY_STRATIX_HC (device : in string) return boolean is +variable var_family_stratix_hc : boolean := false; +begin + if ((device = "StratixHC") ) + then + var_family_stratix_hc := true; + end if; + return var_family_stratix_hc; +end FEATURE_FAMILY_STRATIX_HC; + + +function FEATURE_FAMILY_HARDCOPYII (device : in string) return boolean is +variable var_family_hardcopyii : boolean := false; +begin + if (IS_FAMILY_HARDCOPYII(device) ) + then + var_family_hardcopyii := true; + end if; + return var_family_hardcopyii; +end FEATURE_FAMILY_HARDCOPYII; + + +function FEATURE_FAMILY_STRATIX (device : in string) return boolean is +variable var_family_stratix : boolean := false; +begin + if (IS_FAMILY_STRATIX(device) or FEATURE_FAMILY_STRATIX_HC(device) or FEATURE_FAMILY_STRATIXGX(device) or FEATURE_FAMILY_CYCLONE(device) or FEATURE_FAMILY_STRATIXII(device) or FEATURE_FAMILY_MAXII(device) or FEATURE_FAMILY_CYCLONEII(device) ) + then + var_family_stratix := true; + end if; + return var_family_stratix; +end FEATURE_FAMILY_STRATIX; + + +function FEATURE_FAMILY_MAXII (device : in string) return boolean is +variable var_family_maxii : boolean := false; +begin + if (IS_FAMILY_MAXII(device) or FEATURE_FAMILY_MAXV(device) ) + then + var_family_maxii := true; + end if; + return var_family_maxii; +end FEATURE_FAMILY_MAXII; + + +function FEATURE_FAMILY_MAXV (device : in string) return boolean is +variable var_family_maxv : boolean := false; +begin + if (IS_FAMILY_MAXV(device) ) + then + var_family_maxv := true; + end if; + return var_family_maxv; +end FEATURE_FAMILY_MAXV; + + +function FEATURE_FAMILY_CYCLONEII (device : in string) return boolean is +variable var_family_cycloneii : boolean := false; +begin + if (IS_FAMILY_CYCLONEII(device) or FEATURE_FAMILY_CYCLONEIII(device) ) + then + var_family_cycloneii := true; + end if; + return var_family_cycloneii; +end FEATURE_FAMILY_CYCLONEII; + + +function FEATURE_FAMILY_STRATIXIV (device : in string) return boolean is +variable var_family_stratixiv : boolean := false; +begin + if (IS_FAMILY_STRATIXIV(device) or IS_FAMILY_ARRIAIIGX(device) or FEATURE_FAMILY_HARDCOPYIV(device) or FEATURE_FAMILY_STRATIXV(device) or FEATURE_FAMILY_ARRIAV(device) or FEATURE_FAMILY_ARRIAIIGZ(device) or FEATURE_FAMILY_ARRIA10(device) ) + then + var_family_stratixiv := true; + end if; + return var_family_stratixiv; +end FEATURE_FAMILY_STRATIXIV; + + +function FEATURE_FAMILY_ARRIAIIGZ (device : in string) return boolean is +variable var_family_arriaiigz : boolean := false; +begin + if (IS_FAMILY_ARRIAIIGZ(device) ) + then + var_family_arriaiigz := true; + end if; + return var_family_arriaiigz; +end FEATURE_FAMILY_ARRIAIIGZ; + + +function FEATURE_FAMILY_ARRIAIIGX (device : in string) return boolean is +variable var_family_arriaiigx : boolean := false; +begin + if (IS_FAMILY_ARRIAIIGX(device) ) + then + var_family_arriaiigx := true; + end if; + return var_family_arriaiigx; +end FEATURE_FAMILY_ARRIAIIGX; + + +function FEATURE_FAMILY_HARDCOPYIII (device : in string) return boolean is +variable var_family_hardcopyiii : boolean := false; +begin + if (IS_FAMILY_HARDCOPYIII(device) or IS_FAMILY_HARDCOPYIII(device) ) + then + var_family_hardcopyiii := true; + end if; + return var_family_hardcopyiii; +end FEATURE_FAMILY_HARDCOPYIII; + + +function FEATURE_FAMILY_HARDCOPYIV (device : in string) return boolean is +variable var_family_hardcopyiv : boolean := false; +begin + if (IS_FAMILY_HARDCOPYIV(device) or IS_FAMILY_HARDCOPYIV(device) ) + then + var_family_hardcopyiv := true; + end if; + return var_family_hardcopyiv; +end FEATURE_FAMILY_HARDCOPYIV; + + +function FEATURE_FAMILY_CYCLONEV (device : in string) return boolean is +variable var_family_cyclonev : boolean := false; +begin + if (IS_FAMILY_CYCLONEV(device) ) + then + var_family_cyclonev := true; + end if; + return var_family_cyclonev; +end FEATURE_FAMILY_CYCLONEV; + + +function FEATURE_FAMILY_ARRIAV (device : in string) return boolean is +variable var_family_arriav : boolean := false; +begin + if (IS_FAMILY_ARRIAV(device) or FEATURE_FAMILY_CYCLONEV(device) ) + then + var_family_arriav := true; + end if; + return var_family_arriav; +end FEATURE_FAMILY_ARRIAV; + + +function FEATURE_FAMILY_MAX10 (device : in string) return boolean is +variable var_family_max10 : boolean := false; +begin + if (IS_FAMILY_MAX10(device) ) + then + var_family_max10 := true; + end if; + return var_family_max10; +end FEATURE_FAMILY_MAX10; + + +function FEATURE_FAMILY_STRATIX10 (device : in string) return boolean is +variable var_family_stratix10 : boolean := false; +begin + if (IS_FAMILY_STRATIX10(device) or IS_FAMILY_STRATIX10(device) ) + then + var_family_stratix10 := true; + end if; + return var_family_stratix10; +end FEATURE_FAMILY_STRATIX10; + + +function FEATURE_FAMILY_BASE_STRATIXII (device : in string) return boolean is +variable var_family_base_stratixii : boolean := false; +begin + if (IS_FAMILY_STRATIXII(device) or IS_FAMILY_HARDCOPYII(device) or FEATURE_FAMILY_STRATIXIIGX(device) ) + then + var_family_base_stratixii := true; + end if; + return var_family_base_stratixii; +end FEATURE_FAMILY_BASE_STRATIXII; + + +function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean is +variable var_family_base_stratix : boolean := false; +begin + if (IS_FAMILY_STRATIX(device) or IS_FAMILY_STRATIXGX(device) ) + then + var_family_base_stratix := true; + end if; + return var_family_base_stratix; +end FEATURE_FAMILY_BASE_STRATIX; + + +function FEATURE_FAMILY_BASE_CYCLONEII (device : in string) return boolean is +variable var_family_base_cycloneii : boolean := false; +begin + if (IS_FAMILY_CYCLONEII(device) ) + then + var_family_base_cycloneii := true; + end if; + return var_family_base_cycloneii; +end FEATURE_FAMILY_BASE_CYCLONEII; + + +function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean is +variable var_family_base_cyclone : boolean := false; +begin + if (IS_FAMILY_CYCLONE(device) ) + then + var_family_base_cyclone := true; + end if; + return var_family_base_cyclone; +end FEATURE_FAMILY_BASE_CYCLONE; + + +function FEATURE_FAMILY_BASE_CYCLONEIII (device : in string) return boolean is +variable var_family_base_cycloneiii : boolean := false; +begin + if (IS_FAMILY_CYCLONEIII(device) or IS_FAMILY_CYCLONEIIILS(device) or IS_FAMILY_CYCLONEIVGX(device) or FEATURE_FAMILY_CYCLONEIVE(device) or FEATURE_FAMILY_MAX10(device) ) + then + var_family_base_cycloneiii := true; + end if; + return var_family_base_cycloneiii; +end FEATURE_FAMILY_BASE_CYCLONEIII; + + +function FEATURE_FAMILY_BASE_STRATIXIII (device : in string) return boolean is +variable var_family_base_stratixiii : boolean := false; +begin + if (IS_FAMILY_STRATIXIII(device) or FEATURE_FAMILY_STRATIXIV(device) or IS_FAMILY_HARDCOPYIII(device) ) + then + var_family_base_stratixiii := true; + end if; + return var_family_base_stratixiii; +end FEATURE_FAMILY_BASE_STRATIXIII; + + +function FEATURE_FAMILY_STRATIX_NONGX (device : in string) return boolean is +variable var_family_stratix_nongx : boolean := false; +begin + if (IS_FAMILY_STRATIX(device) ) + then + var_family_stratix_nongx := true; + end if; + return var_family_stratix_nongx; +end FEATURE_FAMILY_STRATIX_NONGX; + + +function FEATURE_FAMILY_HAS_ALTERA_MULT_ADD_FLOW (device : in string) return boolean is +variable var_family_has_altera_mult_add_flow : boolean := false; +begin + if (FEATURE_FAMILY_STRATIXV(device) or FEATURE_FAMILY_ARRIAV(device) or FEATURE_FAMILY_CYCLONEV(device) or FEATURE_FAMILY_ARRIA10(device) or FEATURE_FAMILY_STRATIX10(device) ) + then + var_family_has_altera_mult_add_flow := true; + end if; + return var_family_has_altera_mult_add_flow; +end FEATURE_FAMILY_HAS_ALTERA_MULT_ADD_FLOW; + + +function FEATURE_FAMILY_IS_ALTMULT_ADD_EOL (device : in string) return boolean is +variable var_family_is_altmult_add_eol : boolean := false; +begin + if (FEATURE_FAMILY_ARRIA10(device) or FEATURE_FAMILY_STRATIX10(device) ) + then + var_family_is_altmult_add_eol := true; + end if; + return var_family_is_altmult_add_eol; +end FEATURE_FAMILY_IS_ALTMULT_ADD_EOL; + + +function FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM (device : in string) return boolean is +variable var_family_has_stratixv_style_ram : boolean := false; +begin + if (FEATURE_FAMILY_STRATIXV(device) or FEATURE_FAMILY_ARRIAV(device) or FEATURE_FAMILY_ARRIA10(device) ) + then + var_family_has_stratixv_style_ram := true; + end if; + return var_family_has_stratixv_style_ram; +end FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM; + + +function FEATURE_FAMILY_HAS_MEGARAM (device : in string) return boolean is +variable var_family_has_megaram : boolean := false; +begin + if (( ( IS_FAMILY_STRATIX(device) or FEATURE_FAMILY_STRATIX_HC(device) or IS_FAMILY_STRATIXGX(device) or FEATURE_FAMILY_STRATIXII(device) ) and NOT FEATURE_FAMILY_ARRIAIIGX(device) ) and NOT FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM(device) ) + then + var_family_has_megaram := true; + end if; + return var_family_has_megaram; +end FEATURE_FAMILY_HAS_MEGARAM; + + +function FEATURE_FAMILY_HAS_M512 (device : in string) return boolean is +variable var_family_has_m512 : boolean := false; +begin + if (IS_FAMILY_STRATIX(device) or FEATURE_FAMILY_STRATIX_HC(device) or IS_FAMILY_STRATIXGX(device) or IS_FAMILY_STRATIXII(device) or FEATURE_FAMILY_STRATIXIIGX(device) ) + then + var_family_has_m512 := true; + end if; + return var_family_has_m512; +end FEATURE_FAMILY_HAS_M512; + + +function FEATURE_FAMILY_HAS_LUTRAM (device : in string) return boolean is +variable var_family_has_lutram : boolean := false; +begin + if (FEATURE_FAMILY_STRATIXIII(device) or FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM(device) or FEATURE_FAMILY_STRATIX10(device) ) + then + var_family_has_lutram := true; + end if; + return var_family_has_lutram; +end FEATURE_FAMILY_HAS_LUTRAM; + + +function FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM (device : in string) return boolean is +variable var_family_has_stratixi_style_ram : boolean := false; +begin + if (IS_FAMILY_STRATIX(device) or FEATURE_FAMILY_STRATIX_HC(device) or FEATURE_FAMILY_STRATIXGX(device) or FEATURE_FAMILY_CYCLONE(device) ) + then + var_family_has_stratixi_style_ram := true; + end if; + return var_family_has_stratixi_style_ram; +end FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM; + + +function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM (device : in string) return boolean is +variable var_family_has_stratixii_style_ram : boolean := false; +begin + if (FEATURE_FAMILY_STRATIXII(device) or FEATURE_FAMILY_CYCLONEII(device) ) + then + var_family_has_stratixii_style_ram := true; + end if; + return var_family_has_stratixii_style_ram; +end FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM; + + +function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM (device : in string) return boolean is +variable var_family_has_stratixiii_style_ram : boolean := false; +begin + if (FEATURE_FAMILY_STRATIXIII(device) or FEATURE_FAMILY_CYCLONEIII(device) ) + then + var_family_has_stratixiii_style_ram := true; + end if; + return var_family_has_stratixiii_style_ram; +end FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM; + + +function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL (device : in string) return boolean is +variable var_family_has_stratix_style_pll : boolean := false; +begin + if (FEATURE_FAMILY_CYCLONE(device) or FEATURE_FAMILY_STRATIX_HC(device) or IS_FAMILY_STRATIX(device) or FEATURE_FAMILY_STRATIXGX(device) ) + then + var_family_has_stratix_style_pll := true; + end if; + return var_family_has_stratix_style_pll; +end FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL; + + +function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL (device : in string) return boolean is +variable var_family_has_stratixii_style_pll : boolean := false; +begin + if (( ( FEATURE_FAMILY_STRATIXII(device) and NOT FEATURE_FAMILY_STRATIXIII(device) ) or FEATURE_FAMILY_CYCLONEII(device) ) and NOT FEATURE_FAMILY_CYCLONEIII(device) ) + then + var_family_has_stratixii_style_pll := true; + end if; + return var_family_has_stratixii_style_pll; +end FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL; + + +function FEATURE_FAMILY_USES_STRATIXIII_PLL (device : in string) return boolean is +variable var_family_uses_stratixiii_pll : boolean := false; +begin + if (FEATURE_FAMILY_STRATIXIII(device) or FEATURE_FAMILY_CYCLONEIII(device) ) + then + var_family_uses_stratixiii_pll := true; + end if; + return var_family_uses_stratixiii_pll; +end FEATURE_FAMILY_USES_STRATIXIII_PLL; + + +function FEATURE_FAMILY_HAS_FLEXIBLE_LVDS (device : in string) return boolean is +variable var_family_has_flexible_lvds : boolean := false; +begin + if (FEATURE_FAMILY_CYCLONE(device) or FEATURE_FAMILY_CYCLONEII(device) or FEATURE_FAMILY_MAXV(device) ) + then + var_family_has_flexible_lvds := true; + end if; + return var_family_has_flexible_lvds; +end FEATURE_FAMILY_HAS_FLEXIBLE_LVDS; + + +function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO (device : in string) return boolean is +variable var_family_has_inverted_output_ddio : boolean := false; +begin + if (FEATURE_FAMILY_CYCLONEII(device) ) + then + var_family_has_inverted_output_ddio := true; + end if; + return var_family_has_inverted_output_ddio; +end FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO; + + +function IS_VALID_FAMILY (device : in string) return boolean is +variable is_valid : boolean := false; +begin + if (((device = "Arria 10") or (device = "ARRIA 10") or (device = "arria 10") or (device = "Arria10") or (device = "ARRIA10") or (device = "arria10") or (device = "Arria VI") or (device = "ARRIA VI") or (device = "arria vi") or (device = "ArriaVI") or (device = "ARRIAVI") or (device = "arriavi") or (device = "Night Fury") or (device = "NIGHT FURY") or (device = "night fury") or (device = "nightfury") or (device = "NIGHTFURY") or (device = "Arria 10 (GX/SX/GT)") or (device = "ARRIA 10 (GX/SX/GT)") or (device = "arria 10 (gx/sx/gt)") or (device = "Arria10(GX/SX/GT)") or (device = "ARRIA10(GX/SX/GT)") or (device = "arria10(gx/sx/gt)") or (device = "Arria 10 (GX)") or (device = "ARRIA 10 (GX)") or (device = "arria 10 (gx)") or (device = "Arria10(GX)") or (device = "ARRIA10(GX)") or (device = "arria10(gx)") or (device = "Arria 10 (SX)") or (device = "ARRIA 10 (SX)") or (device = "arria 10 (sx)") or (device = "Arria10(SX)") or (device = "ARRIA10(SX)") or (device = "arria10(sx)") or (device = "Arria 10 (GT)") or (device = "ARRIA 10 (GT)") or (device = "arria 10 (gt)") or (device = "Arria10(GT)") or (device = "ARRIA10(GT)") or (device = "arria10(gt)")) + or ((device = "Arria GX") or (device = "ARRIA GX") or (device = "arria gx") or (device = "ArriaGX") or (device = "ARRIAGX") or (device = "arriagx") or (device = "Stratix II GX Lite") or (device = "STRATIX II GX LITE") or (device = "stratix ii gx lite") or (device = "StratixIIGXLite") or (device = "STRATIXIIGXLITE") or (device = "stratixiigxlite")) + or ((device = "Arria II GX") or (device = "ARRIA II GX") or (device = "arria ii gx") or (device = "ArriaIIGX") or (device = "ARRIAIIGX") or (device = "arriaiigx") or (device = "Arria IIGX") or (device = "ARRIA IIGX") or (device = "arria iigx") or (device = "ArriaII GX") or (device = "ARRIAII GX") or (device = "arriaii gx") or (device = "Arria II") or (device = "ARRIA II") or (device = "arria ii") or (device = "ArriaII") or (device = "ARRIAII") or (device = "arriaii") or (device = "Arria II (GX/E)") or (device = "ARRIA II (GX/E)") or (device = "arria ii (gx/e)") or (device = "ArriaII(GX/E)") or (device = "ARRIAII(GX/E)") or (device = "arriaii(gx/e)") or (device = "PIRANHA") or (device = "piranha")) + or ((device = "Arria II GZ") or (device = "ARRIA II GZ") or (device = "arria ii gz") or (device = "ArriaII GZ") or (device = "ARRIAII GZ") or (device = "arriaii gz") or (device = "Arria IIGZ") or (device = "ARRIA IIGZ") or (device = "arria iigz") or (device = "ArriaIIGZ") or (device = "ARRIAIIGZ") or (device = "arriaiigz")) + or ((device = "Arria V GZ") or (device = "ARRIA V GZ") or (device = "arria v gz") or (device = "ArriaVGZ") or (device = "ARRIAVGZ") or (device = "arriavgz")) + or ((device = "Arria V") or (device = "ARRIA V") or (device = "arria v") or (device = "Arria V (GT/GX)") or (device = "ARRIA V (GT/GX)") or (device = "arria v (gt/gx)") or (device = "ArriaV(GT/GX)") or (device = "ARRIAV(GT/GX)") or (device = "arriav(gt/gx)") or (device = "ArriaV") or (device = "ARRIAV") or (device = "arriav") or (device = "Arria V (GT/GX/ST/SX)") or (device = "ARRIA V (GT/GX/ST/SX)") or (device = "arria v (gt/gx/st/sx)") or (device = "ArriaV(GT/GX/ST/SX)") or (device = "ARRIAV(GT/GX/ST/SX)") or (device = "arriav(gt/gx/st/sx)") or (device = "Arria V (GT)") or (device = "ARRIA V (GT)") or (device = "arria v (gt)") or (device = "ArriaV(GT)") or (device = "ARRIAV(GT)") or (device = "arriav(gt)") or (device = "Arria V (GX)") or (device = "ARRIA V (GX)") or (device = "arria v (gx)") or (device = "ArriaV(GX)") or (device = "ARRIAV(GX)") or (device = "arriav(gx)") or (device = "Arria V (ST)") or (device = "ARRIA V (ST)") or (device = "arria v (st)") or (device = "ArriaV(ST)") or (device = "ARRIAV(ST)") or (device = "arriav(st)") or (device = "Arria V (SX)") or (device = "ARRIA V (SX)") or (device = "arria v (sx)") or (device = "ArriaV(SX)") or (device = "ARRIAV(SX)") or (device = "arriav(sx)")) + or ((device = "BS") or (device = "bs")) + or ((device = "Cyclone II") or (device = "CYCLONE II") or (device = "cyclone ii") or (device = "Cycloneii") or (device = "CYCLONEII") or (device = "cycloneii") or (device = "Magellan") or (device = "MAGELLAN") or (device = "magellan") or (device = "CycloneII") or (device = "CYCLONEII") or (device = "cycloneii")) + or ((device = "Cyclone III LS") or (device = "CYCLONE III LS") or (device = "cyclone iii ls") or (device = "CycloneIIILS") or (device = "CYCLONEIIILS") or (device = "cycloneiiils") or (device = "Cyclone III LPS") or (device = "CYCLONE III LPS") or (device = "cyclone iii lps") or (device = "Cyclone LPS") or (device = "CYCLONE LPS") or (device = "cyclone lps") or (device = "CycloneLPS") or (device = "CYCLONELPS") or (device = "cyclonelps") or (device = "Tarpon") or (device = "TARPON") or (device = "tarpon") or (device = "Cyclone IIIE") or (device = "CYCLONE IIIE") or (device = "cyclone iiie")) + or ((device = "Cyclone III") or (device = "CYCLONE III") or (device = "cyclone iii") or (device = "CycloneIII") or (device = "CYCLONEIII") or (device = "cycloneiii") or (device = "Barracuda") or (device = "BARRACUDA") or (device = "barracuda") or (device = "Cuda") or (device = "CUDA") or (device = "cuda") or (device = "CIII") or (device = "ciii")) + or ((device = "Cyclone IV E") or (device = "CYCLONE IV E") or (device = "cyclone iv e") or (device = "CycloneIV E") or (device = "CYCLONEIV E") or (device = "cycloneiv e") or (device = "Cyclone IVE") or (device = "CYCLONE IVE") or (device = "cyclone ive") or (device = "CycloneIVE") or (device = "CYCLONEIVE") or (device = "cycloneive")) + or ((device = "Cyclone IV GX") or (device = "CYCLONE IV GX") or (device = "cyclone iv gx") or (device = "Cyclone IVGX") or (device = "CYCLONE IVGX") or (device = "cyclone ivgx") or (device = "CycloneIV GX") or (device = "CYCLONEIV GX") or (device = "cycloneiv gx") or (device = "CycloneIVGX") or (device = "CYCLONEIVGX") or (device = "cycloneivgx") or (device = "Cyclone IV") or (device = "CYCLONE IV") or (device = "cyclone iv") or (device = "CycloneIV") or (device = "CYCLONEIV") or (device = "cycloneiv") or (device = "Cyclone IV (GX)") or (device = "CYCLONE IV (GX)") or (device = "cyclone iv (gx)") or (device = "CycloneIV(GX)") or (device = "CYCLONEIV(GX)") or (device = "cycloneiv(gx)") or (device = "Cyclone III GX") or (device = "CYCLONE III GX") or (device = "cyclone iii gx") or (device = "CycloneIII GX") or (device = "CYCLONEIII GX") or (device = "cycloneiii gx") or (device = "Cyclone IIIGX") or (device = "CYCLONE IIIGX") or (device = "cyclone iiigx") or (device = "CycloneIIIGX") or (device = "CYCLONEIIIGX") or (device = "cycloneiiigx") or (device = "Cyclone III GL") or (device = "CYCLONE III GL") or (device = "cyclone iii gl") or (device = "CycloneIII GL") or (device = "CYCLONEIII GL") or (device = "cycloneiii gl") or (device = "Cyclone IIIGL") or (device = "CYCLONE IIIGL") or (device = "cyclone iiigl") or (device = "CycloneIIIGL") or (device = "CYCLONEIIIGL") or (device = "cycloneiiigl") or (device = "Stingray") or (device = "STINGRAY") or (device = "stingray")) + or ((device = "Cyclone V") or (device = "CYCLONE V") or (device = "cyclone v") or (device = "CycloneV") or (device = "CYCLONEV") or (device = "cyclonev") or (device = "Cyclone V (GT/GX/E/SX)") or (device = "CYCLONE V (GT/GX/E/SX)") or (device = "cyclone v (gt/gx/e/sx)") or (device = "CycloneV(GT/GX/E/SX)") or (device = "CYCLONEV(GT/GX/E/SX)") or (device = "cyclonev(gt/gx/e/sx)") or (device = "Cyclone V (E/GX/GT/SX/SE/ST)") or (device = "CYCLONE V (E/GX/GT/SX/SE/ST)") or (device = "cyclone v (e/gx/gt/sx/se/st)") or (device = "CycloneV(E/GX/GT/SX/SE/ST)") or (device = "CYCLONEV(E/GX/GT/SX/SE/ST)") or (device = "cyclonev(e/gx/gt/sx/se/st)") or (device = "Cyclone V (E)") or (device = "CYCLONE V (E)") or (device = "cyclone v (e)") or (device = "CycloneV(E)") or (device = "CYCLONEV(E)") or (device = "cyclonev(e)") or (device = "Cyclone V (GX)") or (device = "CYCLONE V (GX)") or (device = "cyclone v (gx)") or (device = "CycloneV(GX)") or (device = "CYCLONEV(GX)") or (device = "cyclonev(gx)") or (device = "Cyclone V (GT)") or (device = "CYCLONE V (GT)") or (device = "cyclone v (gt)") or (device = "CycloneV(GT)") or (device = "CYCLONEV(GT)") or (device = "cyclonev(gt)") or (device = "Cyclone V (SX)") or (device = "CYCLONE V (SX)") or (device = "cyclone v (sx)") or (device = "CycloneV(SX)") or (device = "CYCLONEV(SX)") or (device = "cyclonev(sx)") or (device = "Cyclone V (SE)") or (device = "CYCLONE V (SE)") or (device = "cyclone v (se)") or (device = "CycloneV(SE)") or (device = "CYCLONEV(SE)") or (device = "cyclonev(se)") or (device = "Cyclone V (ST)") or (device = "CYCLONE V (ST)") or (device = "cyclone v (st)") or (device = "CycloneV(ST)") or (device = "CYCLONEV(ST)") or (device = "cyclonev(st)")) + or ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado")) + or ((device = "HardCopy II") or (device = "HARDCOPY II") or (device = "hardcopy ii") or (device = "HardCopyII") or (device = "HARDCOPYII") or (device = "hardcopyii") or (device = "Fusion") or (device = "FUSION") or (device = "fusion")) + or ((device = "HardCopy III") or (device = "HARDCOPY III") or (device = "hardcopy iii") or (device = "HardCopyIII") or (device = "HARDCOPYIII") or (device = "hardcopyiii") or (device = "HCX") or (device = "hcx")) + or ((device = "HardCopy IV") or (device = "HARDCOPY IV") or (device = "hardcopy iv") or (device = "HardCopyIV") or (device = "HARDCOPYIV") or (device = "hardcopyiv") or (device = "HardCopy IV (GX)") or (device = "HARDCOPY IV (GX)") or (device = "hardcopy iv (gx)") or (device = "HardCopy IV (E)") or (device = "HARDCOPY IV (E)") or (device = "hardcopy iv (e)") or (device = "HardCopyIV(GX)") or (device = "HARDCOPYIV(GX)") or (device = "hardcopyiv(gx)") or (device = "HardCopyIV(E)") or (device = "HARDCOPYIV(E)") or (device = "hardcopyiv(e)") or (device = "HCXIV") or (device = "hcxiv") or (device = "HardCopy IV (GX/E)") or (device = "HARDCOPY IV (GX/E)") or (device = "hardcopy iv (gx/e)") or (device = "HardCopy IV (E/GX)") or (device = "HARDCOPY IV (E/GX)") or (device = "hardcopy iv (e/gx)") or (device = "HardCopyIV(GX/E)") or (device = "HARDCOPYIV(GX/E)") or (device = "hardcopyiv(gx/e)") or (device = "HardCopyIV(E/GX)") or (device = "HARDCOPYIV(E/GX)") or (device = "hardcopyiv(e/gx)")) + or ((device = "MAX 10") or (device = "max 10") or (device = "MAX 10 FPGA") or (device = "max 10 fpga") or (device = "Zippleback") or (device = "ZIPPLEBACK") or (device = "zippleback") or (device = "MAX10") or (device = "max10") or (device = "MAX 10 (DA/DF/DC/SA/SF/SC)") or (device = "max 10 (da/df/dc/sa/sf/sc)") or (device = "MAX10(DA/DF/DC/SA/SF/SC)") or (device = "max10(da/df/dc/sa/sf/sc)") or (device = "MAX 10 (DA)") or (device = "max 10 (da)") or (device = "MAX10(DA)") or (device = "max10(da)") or (device = "MAX 10 (DF)") or (device = "max 10 (df)") or (device = "MAX10(DF)") or (device = "max10(df)") or (device = "MAX 10 (DC)") or (device = "max 10 (dc)") or (device = "MAX10(DC)") or (device = "max10(dc)") or (device = "MAX 10 (SA)") or (device = "max 10 (sa)") or (device = "MAX10(SA)") or (device = "max10(sa)") or (device = "MAX 10 (SF)") or (device = "max 10 (sf)") or (device = "MAX10(SF)") or (device = "max10(sf)") or (device = "MAX 10 (SC)") or (device = "max 10 (sc)") or (device = "MAX10(SC)") or (device = "max10(sc)")) + or ((device = "MAX II") or (device = "max ii") or (device = "MAXII") or (device = "maxii") or (device = "Tsunami") or (device = "TSUNAMI") or (device = "tsunami")) + or ((device = "MAX V") or (device = "max v") or (device = "MAXV") or (device = "maxv") or (device = "Jade") or (device = "JADE") or (device = "jade")) + or ((device = "MAX3000A") or (device = "max3000a") or (device = "MAX 3000A") or (device = "max 3000a")) + or ((device = "MAX7000A") or (device = "max7000a") or (device = "MAX 7000A") or (device = "max 7000a")) + or ((device = "MAX7000AE") or (device = "max7000ae") or (device = "MAX 7000AE") or (device = "max 7000ae")) + or ((device = "MAX7000B") or (device = "max7000b") or (device = "MAX 7000B") or (device = "max 7000b")) + or ((device = "MAX7000S") or (device = "max7000s") or (device = "MAX 7000S") or (device = "max 7000s")) + or ((device = "Stratix 10") or (device = "STRATIX 10") or (device = "stratix 10") or (device = "Stratix10") or (device = "STRATIX10") or (device = "stratix10") or (device = "nadder") or (device = "NADDER")) + or ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora")) + or ((device = "Stratix II GX") or (device = "STRATIX II GX") or (device = "stratix ii gx") or (device = "StratixIIGX") or (device = "STRATIXIIGX") or (device = "stratixiigx")) + or ((device = "Stratix II") or (device = "STRATIX II") or (device = "stratix ii") or (device = "StratixII") or (device = "STRATIXII") or (device = "stratixii") or (device = "Armstrong") or (device = "ARMSTRONG") or (device = "armstrong")) + or ((device = "Stratix III") or (device = "STRATIX III") or (device = "stratix iii") or (device = "StratixIII") or (device = "STRATIXIII") or (device = "stratixiii") or (device = "Titan") or (device = "TITAN") or (device = "titan") or (device = "SIII") or (device = "siii")) + or ((device = "Stratix IV") or (device = "STRATIX IV") or (device = "stratix iv") or (device = "TGX") or (device = "tgx") or (device = "StratixIV") or (device = "STRATIXIV") or (device = "stratixiv") or (device = "Stratix IV (GT)") or (device = "STRATIX IV (GT)") or (device = "stratix iv (gt)") or (device = "Stratix IV (GX)") or (device = "STRATIX IV (GX)") or (device = "stratix iv (gx)") or (device = "Stratix IV (E)") or (device = "STRATIX IV (E)") or (device = "stratix iv (e)") or (device = "StratixIV(GT)") or (device = "STRATIXIV(GT)") or (device = "stratixiv(gt)") or (device = "StratixIV(GX)") or (device = "STRATIXIV(GX)") or (device = "stratixiv(gx)") or (device = "StratixIV(E)") or (device = "STRATIXIV(E)") or (device = "stratixiv(e)") or (device = "StratixIIIGX") or (device = "STRATIXIIIGX") or (device = "stratixiiigx") or (device = "Stratix IV (GT/GX/E)") or (device = "STRATIX IV (GT/GX/E)") or (device = "stratix iv (gt/gx/e)") or (device = "Stratix IV (GT/E/GX)") or (device = "STRATIX IV (GT/E/GX)") or (device = "stratix iv (gt/e/gx)") or (device = "Stratix IV (E/GT/GX)") or (device = "STRATIX IV (E/GT/GX)") or (device = "stratix iv (e/gt/gx)") or (device = "Stratix IV (E/GX/GT)") or (device = "STRATIX IV (E/GX/GT)") or (device = "stratix iv (e/gx/gt)") or (device = "StratixIV(GT/GX/E)") or (device = "STRATIXIV(GT/GX/E)") or (device = "stratixiv(gt/gx/e)") or (device = "StratixIV(GT/E/GX)") or (device = "STRATIXIV(GT/E/GX)") or (device = "stratixiv(gt/e/gx)") or (device = "StratixIV(E/GX/GT)") or (device = "STRATIXIV(E/GX/GT)") or (device = "stratixiv(e/gx/gt)") or (device = "StratixIV(E/GT/GX)") or (device = "STRATIXIV(E/GT/GX)") or (device = "stratixiv(e/gt/gx)") or (device = "Stratix IV (GX/E)") or (device = "STRATIX IV (GX/E)") or (device = "stratix iv (gx/e)") or (device = "StratixIV(GX/E)") or (device = "STRATIXIV(GX/E)") or (device = "stratixiv(gx/e)")) + or ((device = "Stratix V") or (device = "STRATIX V") or (device = "stratix v") or (device = "StratixV") or (device = "STRATIXV") or (device = "stratixv") or (device = "Stratix V (GS)") or (device = "STRATIX V (GS)") or (device = "stratix v (gs)") or (device = "StratixV(GS)") or (device = "STRATIXV(GS)") or (device = "stratixv(gs)") or (device = "Stratix V (GT)") or (device = "STRATIX V (GT)") or (device = "stratix v (gt)") or (device = "StratixV(GT)") or (device = "STRATIXV(GT)") or (device = "stratixv(gt)") or (device = "Stratix V (GX)") or (device = "STRATIX V (GX)") or (device = "stratix v (gx)") or (device = "StratixV(GX)") or (device = "STRATIXV(GX)") or (device = "stratixv(gx)") or (device = "Stratix V (GS/GX)") or (device = "STRATIX V (GS/GX)") or (device = "stratix v (gs/gx)") or (device = "StratixV(GS/GX)") or (device = "STRATIXV(GS/GX)") or (device = "stratixv(gs/gx)") or (device = "Stratix V (GS/GT)") or (device = "STRATIX V (GS/GT)") or (device = "stratix v (gs/gt)") or (device = "StratixV(GS/GT)") or (device = "STRATIXV(GS/GT)") or (device = "stratixv(gs/gt)") or (device = "Stratix V (GT/GX)") or (device = "STRATIX V (GT/GX)") or (device = "stratix v (gt/gx)") or (device = "StratixV(GT/GX)") or (device = "STRATIXV(GT/GX)") or (device = "stratixv(gt/gx)") or (device = "Stratix V (GX/GS)") or (device = "STRATIX V (GX/GS)") or (device = "stratix v (gx/gs)") or (device = "StratixV(GX/GS)") or (device = "STRATIXV(GX/GS)") or (device = "stratixv(gx/gs)") or (device = "Stratix V (GT/GS)") or (device = "STRATIX V (GT/GS)") or (device = "stratix v (gt/gs)") or (device = "StratixV(GT/GS)") or (device = "STRATIXV(GT/GS)") or (device = "stratixv(gt/gs)") or (device = "Stratix V (GX/GT)") or (device = "STRATIX V (GX/GT)") or (device = "stratix v (gx/gt)") or (device = "StratixV(GX/GT)") or (device = "STRATIXV(GX/GT)") or (device = "stratixv(gx/gt)") or (device = "Stratix V (GS/GT/GX)") or (device = "STRATIX V (GS/GT/GX)") or (device = "stratix v (gs/gt/gx)") or (device = "Stratix V (GS/GX/GT)") or (device = "STRATIX V (GS/GX/GT)") or (device = "stratix v (gs/gx/gt)") or (device = "Stratix V (GT/GS/GX)") or (device = "STRATIX V (GT/GS/GX)") or (device = "stratix v (gt/gs/gx)") or (device = "Stratix V (GT/GX/GS)") or (device = "STRATIX V (GT/GX/GS)") or (device = "stratix v (gt/gx/gs)") or (device = "Stratix V (GX/GS/GT)") or (device = "STRATIX V (GX/GS/GT)") or (device = "stratix v (gx/gs/gt)") or (device = "Stratix V (GX/GT/GS)") or (device = "STRATIX V (GX/GT/GS)") or (device = "stratix v (gx/gt/gs)") or (device = "StratixV(GS/GT/GX)") or (device = "STRATIXV(GS/GT/GX)") or (device = "stratixv(gs/gt/gx)") or (device = "StratixV(GS/GX/GT)") or (device = "STRATIXV(GS/GX/GT)") or (device = "stratixv(gs/gx/gt)") or (device = "StratixV(GT/GS/GX)") or (device = "STRATIXV(GT/GS/GX)") or (device = "stratixv(gt/gs/gx)") or (device = "StratixV(GT/GX/GS)") or (device = "STRATIXV(GT/GX/GS)") or (device = "stratixv(gt/gx/gs)") or (device = "StratixV(GX/GS/GT)") or (device = "STRATIXV(GX/GS/GT)") or (device = "stratixv(gx/gs/gt)") or (device = "StratixV(GX/GT/GS)") or (device = "STRATIXV(GX/GT/GS)") or (device = "stratixv(gx/gt/gs)") or (device = "Stratix V (GS/GT/GX/E)") or (device = "STRATIX V (GS/GT/GX/E)") or (device = "stratix v (gs/gt/gx/e)") or (device = "StratixV(GS/GT/GX/E)") or (device = "STRATIXV(GS/GT/GX/E)") or (device = "stratixv(gs/gt/gx/e)") or (device = "Stratix V (E)") or (device = "STRATIX V (E)") or (device = "stratix v (e)") or (device = "StratixV(E)") or (device = "STRATIXV(E)") or (device = "stratixv(e)")) + or ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager")) + or ((device = "eFPGA 28 HPM") or (device = "EFPGA 28 HPM") or (device = "efpga 28 hpm") or (device = "eFPGA28HPM") or (device = "EFPGA28HPM") or (device = "efpga28hpm") or (device = "Bedrock") or (device = "BEDROCK") or (device = "bedrock"))) + then + is_valid := true; + end if; + return is_valid; +end IS_VALID_FAMILY; + + +end ALTERA_DEVICE_FAMILIES; +-- END OF PACKAGE + +Library ieee; +use ieee.std_logic_1164.all; + +-- START PACKAGE HEADER -------------------------------------------------------- +-- +-- Package Name : MF_pllpack +-- +-- Description : Used by altpll model to calculate required advanced parameters +-- for PLL simulation. Also has functions to do string->integer, +-- integer->string conversions. +-- +-- END PACKAGE HEADER ---------------------------------------------------------- + +-- PACKAGE DECLARATION +package MF_pllpack is + +-- FUNCTION DECLARATION + function int2str (value : integer) + return string; +function alt_conv_integer(arg : in std_logic_vector) return integer; + + + procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer); + + procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ); + + function gcd (X: integer; Y: integer) return integer; + + function count_digit (X: integer) return integer; + + function scale_num (X: integer; Y: integer) return integer; + + function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) return integer; + + function output_counter_value (clk_divide: integer; clk_mult : integer ; + M: integer; N: integer ) return integer; + + function counter_mode (duty_cycle: integer; output_counter_value: integer) return string; + + function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer; + + function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer; + + function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function counter_time_delay ( clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer; + + function get_phase_degree (phase_shift: integer; clk_period: integer) return integer; + + function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer; + + function counter_ph (tap_phase: integer; m : integer; n: integer) return integer; + + function ph_adjust (tap_phase: integer; ph_base : integer) return integer; + + function translate_string (mode : string) return string; + + function str2int (s : string) return integer; +end MF_pllpack; + +-- BEGINNING OF PACKAGE +package body MF_pllpack is + +-- convert integer to string +function int2str( value : integer ) return string is +variable ivalue : integer := 0; +variable index : integer := 1; +variable digit : integer := 0; +variable temp: string(10 downto 1) := "0000000000"; + +begin + ivalue := value; + index := 1; + + while (ivalue > 0) loop + digit := ivalue mod 10; + ivalue := ivalue/10; + + case digit is + when 0 => temp(index) := '0'; + when 1 => temp(index) := '1'; + when 2 => temp(index) := '2'; + when 3 => temp(index) := '3'; + when 4 => temp(index) := '4'; + when 5 => temp(index) := '5'; + when 6 => temp(index) := '6'; + when 7 => temp(index) := '7'; + when 8 => temp(index) := '8'; + when 9 => temp(index) := '9'; + when others => ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + + index := index + 1; + end loop; + + if (value < 0) then + return ('-'& temp(index downto 1)); + else + return temp(index downto 1); + end if; + +end int2str; + +function alt_conv_integer(arg : in std_logic_vector) return integer is +variable result : integer; +begin + result := 0; + for i in arg'range loop + if arg(i) = '1' then + result := result + 2**i; + end if; + end loop; + return result; +end alt_conv_integer; + + +-- finds the closest integer fraction of a given pair of numerator and denominator. +procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer) is + constant MAX_ITER : integer := 20; + type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer; + + variable quotient_array : INT_ARRAY; + variable int_loop_iter : integer; + variable int_quot : integer; + variable m_value : integer; + variable d_value : integer; + variable old_m_value : integer; + variable swap : integer; + variable loop_iter : integer; + variable num : integer; + variable den : integer; + variable i_max_iter : integer; + +begin + loop_iter := 0; + + if (numerator = 0) then + num := 1; + else + num := numerator; + end if; + + if (denominator = 0) then + den := 1; + else + den := denominator; + end if; + + i_max_iter := max_iter; + + while (loop_iter < i_max_iter) loop + int_quot := num / den; + quotient_array(loop_iter) := int_quot; + num := num - (den*int_quot); + loop_iter := loop_iter+1; + + if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then + -- calculate the numerator and denominator if there is a restriction on the + -- max denom value or if the loop is ending + m_value := 0; + d_value := 1; + -- get the rounded value at this stage for the remaining fraction + if (den /= 0) then + m_value := (2*num/den); + end if; + -- calculate the fraction numerator and denominator at this stage + for int_loop_iter in (loop_iter-1) downto 0 loop + if (m_value = 0) then + m_value := quotient_array(int_loop_iter); + d_value := 1; + else + old_m_value := m_value; + m_value := (quotient_array(int_loop_iter)*m_value) + d_value; + d_value := old_m_value; + end if; + end loop; + -- if the denominator is less than the maximum denom_value or if there is no restriction save it + if ((d_value <= max_denom) or (max_denom = -1)) then + if ((m_value = 0) or (d_value = 0)) then + fraction_num := numerator; + fraction_div := denominator; + else + fraction_num := m_value; + fraction_div := d_value; + end if; + end if; + -- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round) + if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then + i_max_iter := loop_iter; + end if; + end if; + -- swap the numerator and denominator for the next round + swap := den; + den := num; + num := swap; + end loop; +end find_simple_integer_fraction; + +-- find the M and N values for Manual phase based on the following 5 criterias: +-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz +-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz +-- 3. M is less than 512 +-- 4. N is less than 512 +-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps +-- of the desired vco-phase-shift-step +procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ) is + constant MAX_M : integer := 511; + constant MAX_N : integer := 511; + constant MAX_PFD : integer := 720; + constant MIN_PFD : integer := 5; + constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz) + constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz) + constant MAX_OFFSET : real := 0.004; + + variable vco_period : integer; + variable pfd_freq : integer; + variable vco_freq : integer; + variable vco_ps_step_value : integer; + + variable i_m : integer; + variable i_n : integer; + + variable i_pre_m : integer; + variable i_pre_n : integer; + + variable closest_vco_step_value : integer; + + variable i_max_iter : integer; + variable loop_iter : integer; + + variable clk0_div_factor_real : real; + variable clk1_div_factor_real : real; + variable clk2_div_factor_real : real; + variable clk3_div_factor_real : real; + variable clk4_div_factor_real : real; + variable clk5_div_factor_real : real; + variable clk6_div_factor_real : real; + variable clk7_div_factor_real : real; + variable clk8_div_factor_real : real; + variable clk9_div_factor_real : real; + variable clk0_div_factor_int : integer; + variable clk1_div_factor_int : integer; + variable clk2_div_factor_int : integer; + variable clk3_div_factor_int : integer; + variable clk4_div_factor_int : integer; + variable clk5_div_factor_int : integer; + variable clk6_div_factor_int : integer; + variable clk7_div_factor_int : integer; + variable clk8_div_factor_int : integer; + variable clk9_div_factor_int : integer; +begin + vco_period := vco_phase_shift_step * 8; + i_pre_m := 0; + i_pre_n := 0; + closest_vco_step_value := 0; + + LOOP_1 : for i_n_out in 1 to MAX_N loop + for i_m_out in 1 to MAX_M loop + + clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out); + clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out); + clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out); + clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out); + clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out); + clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out); + clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out); + clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out); + clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out); + clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out); + + clk0_div_factor_int := integer(clk0_div_factor_real); + clk1_div_factor_int := integer(clk1_div_factor_real); + clk2_div_factor_int := integer(clk2_div_factor_real); + clk3_div_factor_int := integer(clk3_div_factor_real); + clk4_div_factor_int := integer(clk4_div_factor_real); + clk5_div_factor_int := integer(clk5_div_factor_real); + clk6_div_factor_int := integer(clk6_div_factor_real); + clk7_div_factor_int := integer(clk7_div_factor_real); + clk8_div_factor_int := integer(clk8_div_factor_real); + clk9_div_factor_int := integer(clk9_div_factor_real); + + if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and + ((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and + ((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and + ((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and + ((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and + ((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and + ((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and + ((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and + ((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and + ((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) ) + then + if ((i_m_out /= 0) and (i_n_out /= 0)) + then + pfd_freq := 1000000 / (inclock_period * i_n_out); + vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out); + vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out); + + if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and + (vco_freq >= min_vco) and (vco_freq <= max_vco) ) + then + if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + exit LOOP_1; + else + if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + closest_vco_step_value := vco_ps_step_value; + end if; + end if; + end if; + end if; + end if; + end loop; + end loop; + + if ((i_pre_m /= 0) and (i_pre_n /= 0)) + then + find_simple_integer_fraction(i_pre_m, i_pre_n, + MAX_N, m, n); + else + n := 1; + m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult, + clk4_mult, clk5_mult, clk6_mult, + clk7_mult, clk8_mult, clk9_mult, inclock_period); + end if; +end find_m_and_n_4_manual_phase; + +-- find the greatest common denominator of X and Y +function gcd (X: integer; Y: integer) return integer is +variable L, S, R, G : integer := 1; +begin + if (X < Y) then -- find which is smaller. + S := X; + L := Y; + else + S := Y; + L := X; + end if; + + R := S; + while ( R > 1) loop + S := L; + L := R; + R := S rem L; -- divide bigger number by smaller. + -- remainder becomes smaller number. + end loop; + if (R = 0) then -- if evenly divisible then L is gcd else it is 1. + G := L; + else + G := R; + end if; + + return G; +end gcd; + +-- count the number of digits in the given integer +function count_digit (X: integer) + return integer is +variable count, result: integer := 0; +begin + result := X; + while (result /= 0) loop + result := (result / 10); + count := count + 1; + end loop; + + return count; +end count_digit; + +-- reduce the given huge number to Y significant digits +function scale_num (X: integer; Y: integer) + return integer is +variable count : integer := 0; +variable lc, fac_ten, result: integer := 1; +begin + count := count_digit(X); + + for lc in 1 to (count-Y) loop + fac_ten := fac_ten * 10; + end loop; + + result := (X / fac_ten); + + return result; +end scale_num; + +-- find the least common multiple of A1 to A10 +function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) + return integer is +variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1; +begin + M1 := (A1 * A2)/gcd(A1, A2); + M2 := (M1 * A3)/gcd(M1, A3); + M3 := (M2 * A4)/gcd(M2, A4); + M4 := (M3 * A5)/gcd(M3, A5); + M5 := (M4 * A6)/gcd(M4, A6); + M6 := (M5 * A7)/gcd(M5, A7); + M7 := (M6 * A8)/gcd(M6, A8); + M8 := (M7 * A9)/gcd(M7, A9); + M9 := (M8 * A10)/gcd(M8, A10); + if (M9 < 3) then + R := 10; + elsif (M9 = 3) then + R := 9; + elsif ((M9 <= 10) and (M9 > 3)) then + R := 4 * M9; + elsif (M9 > 1000) then + R := scale_num(M9,3); + else + R := M9 ; + end if; + + return R; +end lcm; + +-- find the factor of division of the output clock frequency compared to the VCO +function output_counter_value (clk_divide: integer; clk_mult: integer ; + M: integer; N: integer ) return integer is +variable r_real : real := 1.0; +variable r: integer := 1; +begin + r_real := real(clk_divide * M)/ real(clk_mult * N); + r := integer(r_real); + + return R; +end output_counter_value; + +-- find the mode of each PLL counter - bypass, even or odd +function counter_mode (duty_cycle: integer; output_counter_value: integer) + return string is +variable R: string (1 to 6) := " "; +variable counter_value: integer := 1; +begin + counter_value := (2*duty_cycle*output_counter_value)/100; + if output_counter_value = 1 then + R := "bypass"; + elsif (counter_value REM 2) = 0 then + R := " even"; + else + R := " odd"; + end if; + + return R; +end counter_mode; + +-- find the number of VCO clock cycles to hold the output clock high +function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer is +variable R: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value *2)/100 ; + if (half_cycle_high REM 2 = 0) then + R := half_cycle_high/2 ; + else + R := (half_cycle_high/2) + 1; + end if; + + return R; +end; + +-- find the number of VCO clock cycles to hold the output clock low +function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer is +variable R, R1: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value*2)/100 ; + if (half_cycle_high REM 2 = 0) then + R1 := half_cycle_high/2 ; + else + R1 := (half_cycle_high/2) + 1; + end if; + + R := output_counter_value - R1; + + if (R = 0) then + R := 1; + end if; + + return R; +end; + +-- find the smallest time delay amongst t1 to t10 +function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 > 0) then return m9; else return 0; end if; +end; + +-- find the numerically largest negative number, and return its absolute value +function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 < 0) then return (0 - m9); else return 0; end if; +end; + +-- adjust the phase (tap_phase) with the largest negative number (ph_base) +function ph_adjust (tap_phase: integer; ph_base : integer) return integer is +begin + return (tap_phase + ph_base); +end; + +-- find the time delay for each PLL counter +function counter_time_delay (clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer is +variable R: integer := 0; +begin + R := clk_time_delay + m_time_delay - n_time_delay; + + return R; +end; + +-- calculate the given phase shift (in ps) in terms of degrees +function get_phase_degree (phase_shift: integer; clk_period: integer) + return integer is +variable result: integer := 0; +begin + result := ( phase_shift * 360 ) / clk_period; + -- to round up the calculation result + if (result > 0) then + result := result + 1; + elsif (result < 0) then + result := result - 1; + else + result := 0; + end if; + + return result; +end; + +-- find the number of VCO clock cycles to wait initially before the first rising +-- edge of the output clock +function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer is +variable R: integer; +variable R1: real; +begin + R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6; + -- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99. + -- This checking will ensure that the rounding up is done. + if (R1 >= 0.5) and (R1 <= 1.0) then + R1 := 1.0; + end if; + + R := integer(R1); + + return R; +end; + +-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to +function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is +variable R: integer := 0; +begin + -- 0.5 is added for proper rounding of the tap_phase. + R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8; + + return R; +end; + +-- convert given string to length 6 by padding with spaces +function translate_string (mode : string) return string is +variable new_mode : string (1 to 6) := " "; +begin + if (mode = "bypass") then + new_mode := "bypass"; + elsif (mode = "even") then + new_mode := " even"; + elsif (mode = "odd") then + new_mode := " odd"; + end if; + + return new_mode; +end; + +function str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "i n string parameter! " + SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; +end MF_pllpack; +-- END OF PACKAGE MF_pllpack + +library ieee; +use ieee.std_logic_1164.all; + +-- DFFP +entity DFFP is +port( + clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic := '0' +); +end DFFP; +architecture behave of DFFP is +begin +process (clk, prn, clrn) + begin + if (prn = '0') then + q <= '1'; + elsif (clrn = '0') then + q <= '0'; + else + if (ena = '1') then + q <= d; + end if; + end if; + end process; +end behave; + +Library ieee; +use ieee.std_logic_1164.all; +entity pll_iobuf is + port( + i : in std_logic; + oe : in std_logic; + io : inout std_logic; + o : out std_logic); +end pll_iobuf; +architecture BEHAVIOR of pll_iobuf is +begin + process(i, io, oe) + begin + if oe = '1' then + io <= i; + else + io <= 'Z'; + end if; + o <= io; + end process; +end BEHAVIOR; + + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_m_cntr +-- +-- Description : Simulation model for the M counter. This is a +-- model for the loop feedback counter of the Stratix PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY MF_m_cntr is + PORT ( clk : IN std_logic; + reset : IN std_logic; + cout : OUT std_logic; + initial_value : IN integer; + modulus : IN integer; + time_delay : IN integer; + ph : IN integer := 0); +END MF_m_cntr; + +ARCHITECTURE behave of MF_m_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_n_cntr +-- +-- Description : Simulation model for the N counter. This is a +-- model for the input counter of the Stratix PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY MF_n_cntr is + PORT ( clk : IN std_logic; + reset : IN std_logic; + cout : OUT std_logic; + modulus : IN integer; + time_delay : IN integer); +END MF_n_cntr; + +ARCHITECTURE behave of MF_n_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + variable clk_last_valid_value : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = 'X') then + ASSERT FALSE REPORT "Invalid transition to 'X' detected on Stratix PLL input clk. This edge will be ignored" severity warning; + elsif (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge and (clk_last_valid_value /= clk)) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + if (clk /= 'X') then + clk_last_valid_value := clk; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : stx_scale_cntr +-- +-- Description : Simulation model for the output scale-down counters. +-- This is a common model for the L0, L1, G0, G1, G2, G3, E0, +-- E1, E2 and E3 output counters of the Stratix PLL. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY stx_scale_cntr is + PORT ( clk : IN std_logic; + reset : IN std_logic; + initial : IN integer; + high : IN integer; + low : IN integer; + mode : IN string := "bypass"; + time_delay : IN integer; + ph_tap : IN natural; + cout : OUT std_logic); +END stx_scale_cntr; + +ARCHITECTURE behave of stx_scale_cntr is +begin + process (clk, reset) + variable tmp_cout : std_logic := '0'; + variable count : integer := 1; + variable output_shift_count : integer := 0; + variable first_rising_edge : boolean := false; + variable high_reg : integer := 0; + variable low_reg : integer := 0; + variable init : boolean := true; + variable high_cnt_xfer_done : boolean := false; + begin + if (reset = '1') then + count := 1; + output_shift_count := 0; + tmp_cout := '0'; + first_rising_edge := false; + elsif (clk'event) then + if (init) then + init := false; + high_reg := high; + low_reg := low; + end if; + if (mode = " off") then + tmp_cout := '0'; + elsif (mode = "bypass") then + tmp_cout := clk; + elsif (not first_rising_edge) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + if (output_shift_count = initial) then + tmp_cout := clk; + first_rising_edge := true; + end if; + end if; + elsif (output_shift_count < initial) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + end if; + else + count := count + 1; + if (mode = " even" and (count = (high_reg*2) + 1)) then + tmp_cout := '0'; + if (high_cnt_xfer_done) then + low_reg := low; + high_cnt_xfer_done := false; + end if; + elsif (mode = " odd" and (count = high_reg*2)) then + tmp_cout := '0'; + if (high_cnt_xfer_done) then + low_reg := low; + high_cnt_xfer_done := false; + end if; + elsif (count = (high_reg + low_reg)*2 + 1) then + tmp_cout := '1'; + count := 1; -- reset count + if (high_reg /= high) then + high_cnt_xfer_done := true; + high_reg := high; + end if; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; + +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_pll_reg +-- +-- Description : Simulation model for a simple DFF. +-- This is required for the generation of the bit slip-signals. +-- No timing, powers upto 0. +-- +--///////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY MF_pll_reg is + PORT ( clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic); +end MF_pll_reg; + +ARCHITECTURE behave of MF_pll_reg is +begin + process (clk, prn, clrn) + variable q_reg : std_logic := '0'; + begin + if (prn = '0') then + q_reg := '1'; + elsif (clrn = '0') then + q_reg := '0'; + elsif (clk'event and clk = '1' and (ena = '1')) then + q_reg := D; + end if; + + Q <= q_reg; + end process; +end behave; +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_stratix_pll +-- +-- Description : The behavioral model for Stratix PLL +-- +-- Limitations : Applies to the Stratix and Stratix GX device families +-- No support for spread spectrum feature in the model +-- +-- Outputs : Up to 10 output clocks, each defined by its own set of +-- parameters. Locked output (active high) indicates when the +-- PLL locks. clkbad, clkloss and activeclock are used for +-- clock switchover to indicate which input clock has gone +-- bad, when the clock switchover initiates and which input +-- clock is being used as the reference, respectively. +-- scandataout is the data output of the serial scan chain. +-- +--/////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE STD.TEXTIO.all; +USE work.MF_pllpack.all; +USE work.MF_m_cntr; +USE work.MF_n_cntr; +USE work.stx_scale_cntr; +USE work.dffp; +USE work.MF_pll_reg; + +ENTITY MF_stratix_pll is + GENERIC ( operation_mode : string := "normal"; + qualify_conf_done : string := "off"; + compensate_clock : string := "clk0"; + pll_type : string := "auto"; -- EGPP/FAST/AUTO + scan_chain : string := "long"; + + clk0_multiply_by : integer := 1; + clk0_divide_by : integer := 1; + clk0_phase_shift : string := "0"; + clk0_time_delay : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_multiply_by : integer := 1; + clk1_divide_by : integer := 1; + clk1_phase_shift : string := "0"; + clk1_time_delay : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_multiply_by : integer := 1; + clk2_divide_by : integer := 1; + clk2_phase_shift : string := "0"; + clk2_time_delay : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_multiply_by : integer := 1; + clk3_divide_by : integer := 1; + clk3_phase_shift : string := "0"; + clk3_time_delay : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_multiply_by : integer := 1; + clk4_divide_by : integer := 1; + clk4_phase_shift : string := "0"; + clk4_time_delay : string := "0"; + clk4_duty_cycle : integer := 50; + + clk5_multiply_by : integer := 1; + clk5_divide_by : integer := 1; + clk5_phase_shift : string := "0"; + clk5_time_delay : string := "0"; + clk5_duty_cycle : integer := 50; + + extclk0_multiply_by : integer := 1; + extclk0_divide_by : integer := 1; + extclk0_phase_shift : string := "0"; + extclk0_time_delay : string := "0"; + extclk0_duty_cycle : integer := 50; + + extclk1_multiply_by : integer := 1; + extclk1_divide_by : integer := 1; + extclk1_phase_shift : string := "0"; + extclk1_time_delay : string := "0"; + extclk1_duty_cycle : integer := 50; + + extclk2_multiply_by : integer := 1; + extclk2_divide_by : integer := 1; + extclk2_phase_shift : string := "0"; + extclk2_time_delay : string := "0"; + extclk2_duty_cycle : integer := 50; + + extclk3_multiply_by : integer := 1; + extclk3_divide_by : integer := 1; + extclk3_phase_shift : string := "0"; + extclk3_time_delay : string := "0"; + extclk3_duty_cycle : integer := 50; + + primary_clock : string := "inclk0"; + inclk0_input_frequency : integer := 10000; + inclk1_input_frequency : integer := 10000; + gate_lock_signal : string := "no"; + gate_lock_counter : integer := 1; + valid_lock_multiplier : integer := 5; + invalid_lock_multiplier : integer := 5; + + switch_over_on_lossclk : string := "off"; + switch_over_on_gated_lock : string := "off"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + feedback_source : string := "extclk0"; + bandwidth_type : string := "auto"; + bandwidth : integer := 0; + spread_frequency : integer := 0; + down_spread : string := "0.0"; + + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + + -- ADVANCED USER PARAMETERS + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + m2 : integer := 1; + n2 : integer := 1; + ss : integer := 0; + + l0_high : integer := 1; + l0_low : integer := 1; + l0_initial : integer := 1; + l0_mode : string := "bypass"; + l0_ph : integer := 0; + l0_time_delay : integer := 0; + + l1_high : integer := 1; + l1_low : integer := 1; + l1_initial : integer := 1; + l1_mode : string := "bypass"; + l1_ph : integer := 0; + l1_time_delay : integer := 0; + + g0_high : integer := 1; + g0_low : integer := 1; + g0_initial : integer := 1; + g0_mode : string := "bypass"; + g0_ph : integer := 0; + g0_time_delay : integer := 0; + + g1_high : integer := 1; + g1_low : integer := 1; + g1_initial : integer := 1; + g1_mode : string := "bypass"; + g1_ph : integer := 0; + g1_time_delay : integer := 0; + + g2_high : integer := 1; + g2_low : integer := 1; + g2_initial : integer := 1; + g2_mode : string := "bypass"; + g2_ph : integer := 0; + g2_time_delay : integer := 0; + + g3_high : integer := 1; + g3_low : integer := 1; + g3_initial : integer := 1; + g3_mode : string := "bypass"; + g3_ph : integer := 0; + g3_time_delay : integer := 0; + + e0_high : integer := 1; + e0_low : integer := 1; + e0_initial : integer := 1; + e0_mode : string := "bypass"; + e0_ph : integer := 0; + e0_time_delay : integer := 0; + + e1_high : integer := 1; + e1_low : integer := 1; + e1_initial : integer := 1; + e1_mode : string := "bypass"; + e1_ph : integer := 0; + e1_time_delay : integer := 0; + + e2_high : integer := 1; + e2_low : integer := 1; + e2_initial : integer := 1; + e2_mode : string := "bypass"; + e2_ph : integer := 0; + e2_time_delay : integer := 0; + + e3_high : integer := 1; + e3_low : integer := 1; + e3_initial : integer := 1; + e3_mode : string := "bypass"; + e3_ph : integer := 0; + e3_time_delay : integer := 0; + + m_ph : integer := 0; + m_time_delay : integer := 0; + n_time_delay : integer := 0; + + extclk0_counter : string := "e0"; + extclk1_counter : string := "e1"; + extclk2_counter : string := "e2"; + extclk3_counter : string := "e3"; + + clk0_counter : string := "g0"; + clk1_counter : string := "g1"; + clk2_counter : string := "g2"; + clk3_counter : string := "g3"; + clk4_counter : string := "l0"; + clk5_counter : string := "l1"; + + -- LVDS mode parameters + enable0_counter : string := "l0"; + enable1_counter : string := "l0"; + + charge_pump_current : integer := 0; + loop_filter_r : string := "1.0"; + loop_filter_c : integer := 1; + common_rx_tx : string := "off"; + rx_outclock_resource : string := "auto"; + use_vco_bypass : string := "false"; + use_dc_coupling : string := "false"; + + pll_compensation_delay : integer := 0; + simulation_type : string := "timing"; + + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + clk5_use_even_counter_mode : string := "off"; + extclk0_use_even_counter_mode : string := "off"; + extclk1_use_even_counter_mode : string := "off"; + extclk2_use_even_counter_mode : string := "off"; + extclk3_use_even_counter_mode : string := "off"; + + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + clk5_use_even_counter_value : string := "off"; + extclk0_use_even_counter_value : string := "off"; + extclk1_use_even_counter_value : string := "off"; + extclk2_use_even_counter_value : string := "off"; + extclk3_use_even_counter_value : string := "off"; + scan_chain_mif_file : string := ""; + + -- Simulation only generics + family_name : string := "Stratix"; + + skip_vco : string := "off" + + ); + + PORT ( inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + clkena : in std_logic_vector(5 downto 0) := "111111"; + extclkena : in std_logic_vector(3 downto 0) := "1111"; + scanaclr : in std_logic := '0'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + clk : out std_logic_vector(5 downto 0); + extclk : out std_logic_vector(3 downto 0); + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + clkloss : out std_logic; + scandataout : out std_logic; + -- lvds specific ports + comparator : in std_logic := '0'; + enable0 : out std_logic; + enable1 : out std_logic + ); +END MF_stratix_pll; + +ARCHITECTURE vital_pll of MF_stratix_pll is + +-- internal advanced parameter signals +signal i_vco_min : natural; +signal i_vco_max : natural; +signal i_vco_center : natural; +signal i_pfd_min : natural; +signal i_pfd_max : natural; +signal l0_ph_val : natural; +signal l1_ph_val : natural; +signal g0_ph_val : natural; +signal g1_ph_val : natural; +signal g2_ph_val : natural; +signal g3_ph_val : natural; +signal e0_ph_val : natural; +signal e1_ph_val : natural; +signal e2_ph_val : natural; +signal e3_ph_val : natural; +signal i_extclk3_counter : string(1 to 2) := "e3"; +signal i_extclk2_counter : string(1 to 2) := "e2"; +signal i_extclk1_counter : string(1 to 2) := "e1"; +signal i_extclk0_counter : string(1 to 2) := "e0"; +signal i_clk5_counter : string(1 to 2) := "l1"; +signal i_clk4_counter : string(1 to 2) := "l0"; +signal i_clk3_counter : string(1 to 2) := "g3"; +signal i_clk2_counter : string(1 to 2) := "g2"; +signal i_clk1_counter : string(1 to 2) := "g1"; +signal i_clk0_counter : string(1 to 2) := "g0"; +signal i_charge_pump_current : natural; +signal i_loop_filter_r : natural; + +-- end internal advanced parameter signals + +-- CONSTANTS +CONSTANT EGPP_SCAN_CHAIN : integer := 289; +CONSTANT GPP_SCAN_CHAIN : integer := 193; +CONSTANT TRST : time := 5000 ps; +CONSTANT TRSTCLK : time := 5000 ps; + +-- signals + +signal vcc : std_logic := '1'; + +signal fbclk : std_logic; +signal refclk : std_logic; + +signal l0_clk : std_logic; +signal l1_clk : std_logic; +signal g0_clk : std_logic; +signal g1_clk : std_logic; +signal g2_clk : std_logic; +signal g3_clk : std_logic; +signal e0_clk : std_logic; +signal e1_clk : std_logic; +signal e2_clk : std_logic; +signal e3_clk : std_logic; + +signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); + +-- signals to assign values to counter params +signal m_val : integer := 1; +signal m_val_tmp : integer := 1; +signal m2_val : integer := 1; +signal n_val : integer := 1; +signal n_val_tmp : integer := 1; +signal n2_val : integer := 1; +signal m_time_delay_val, n_time_delay_val : integer := 0; +signal m_ph_val : integer := 0; +signal m_initial_val : integer := m_initial; + +signal l0_initial_val : integer := l0_initial; +signal l1_initial_val : integer := l1_initial; +signal l0_high_val : integer := l0_high; +signal l1_high_val : integer := l1_high; +signal l0_low_val : integer := l0_low; +signal l1_low_val : integer := l1_low; +signal l0_mode_val : string(1 to 6) := "bypass"; +signal l1_mode_val : string(1 to 6) := "bypass"; +signal l0_time_delay_val : integer := l0_time_delay; +signal l1_time_delay_val : integer := l1_time_delay; + +signal g0_initial_val : integer := g0_initial; +signal g1_initial_val : integer := g1_initial; +signal g2_initial_val : integer := g2_initial; +signal g3_initial_val : integer := g3_initial; +signal g0_high_val : integer := g0_high; +signal g1_high_val : integer := g1_high; +signal g2_high_val : integer := g2_high; +signal g3_high_val : integer := g3_high; +signal g0_mode_val : string(1 to 6) := "bypass"; +signal g1_mode_val : string(1 to 6) := "bypass"; +signal g2_mode_val : string(1 to 6) := "bypass"; +signal g3_mode_val : string(1 to 6) := "bypass"; +signal g0_low_val : integer := g0_low; +signal g1_low_val : integer := g1_low; +signal g2_low_val : integer := g2_low; +signal g3_low_val : integer := g3_low; +signal g0_time_delay_val : integer := g0_time_delay; +signal g1_time_delay_val : integer := g1_time_delay; +signal g2_time_delay_val : integer := g2_time_delay; +signal g3_time_delay_val : integer := g3_time_delay; + +signal e0_initial_val : integer := e0_initial; +signal e1_initial_val : integer := e1_initial; +signal e2_initial_val : integer := e2_initial; +signal e3_initial_val : integer := e3_initial; +signal e0_high_val : integer := e0_high; +signal e1_high_val : integer := e1_high; +signal e2_high_val : integer := e2_high; +signal e3_high_val : integer := e3_high; +signal e0_low_val : integer := e0_low; +signal e1_low_val : integer := e1_low; +signal e2_low_val : integer := e2_low; +signal e3_low_val : integer := e3_low; +signal e0_time_delay_val : integer := e0_time_delay; +signal e1_time_delay_val : integer := e1_time_delay; +signal e2_time_delay_val : integer := e2_time_delay; +signal e3_time_delay_val : integer := e3_time_delay; +signal e0_mode_val : string(1 to 6) := "bypass"; +signal e1_mode_val : string(1 to 6) := "bypass"; +signal e2_mode_val : string(1 to 6) := "bypass"; +signal e3_mode_val : string(1 to 6) := "bypass"; + +signal m_mode_val : string(1 to 6) := " "; +signal m2_mode_val : string(1 to 6) := " "; +signal n_mode_val : string(1 to 6) := " "; +signal n2_mode_val : string(1 to 6) := " "; + +signal cntr_e0_initial : integer := 1; +signal cntr_e1_initial : integer := 1; +signal cntr_e2_initial : integer := 1; +signal cntr_e3_initial : integer := 1; +signal ext_fbk_delay : integer := 0; +signal cntr_e0_delay : integer := 0; +signal cntr_e1_delay : integer := 0; +signal cntr_e2_delay : integer := 0; +signal cntr_e3_delay : integer := 0; + +signal transfer : std_logic := '0'; + +signal scan_data : std_logic_vector(288 downto 0) := (OTHERS => '0'); +signal ena0 : std_logic; +signal ena1 : std_logic; +signal ena2 : std_logic; +signal ena3 : std_logic; +signal ena4 : std_logic; +signal ena5 : std_logic; +signal extena0 : std_logic; +signal extena1 : std_logic; +signal extena2 : std_logic; +signal extena3 : std_logic; + +signal clk0_tmp : std_logic; +signal clk1_tmp : std_logic; +signal clk2_tmp : std_logic; +signal clk3_tmp : std_logic; +signal clk4_tmp : std_logic; +signal clk5_tmp : std_logic; +signal extclk0_tmp : std_logic; +signal extclk1_tmp : std_logic; +signal extclk2_tmp : std_logic; +signal extclk3_tmp : std_logic; + +signal not_clk0_tmp : std_logic; +signal not_clk1_tmp : std_logic; +signal not_clk2_tmp : std_logic; +signal not_clk3_tmp : std_logic; +signal not_clk4_tmp : std_logic; +signal not_clk5_tmp : std_logic; + +signal not_extclk0_tmp : std_logic; +signal not_extclk1_tmp : std_logic; +signal not_extclk2_tmp : std_logic; +signal not_extclk3_tmp : std_logic; + +signal clkin : std_logic := '0'; +signal gate_locked : std_logic := '0'; +signal lock : std_logic := '0'; +signal about_to_lock : boolean := false; +signal quiet_period_violation : boolean := false; +signal reconfig_err : boolean := false; +signal scanclr_violation : boolean := false; +signal scanclr_clk_violation : boolean := false; + +signal inclk_l0 : std_logic; +signal inclk_l1 : std_logic; +signal inclk_g0 : std_logic; +signal inclk_g1 : std_logic; +signal inclk_g2 : std_logic; +signal inclk_g3 : std_logic; +signal inclk_e0 : std_logic; +signal inclk_e1 : std_logic; +signal inclk_e2 : std_logic; +signal inclk_e3 : std_logic; +signal inclk_m : std_logic; +signal devpor : std_logic; +signal devclrn : std_logic; + +signal inclk0_ipd : std_logic; +signal inclk1_ipd : std_logic; +signal ena_ipd : std_logic; +signal pfdena_ipd : std_logic; +signal comparator_ipd : std_logic; +signal areset_ipd : std_logic; +signal fbin_ipd : std_logic; +signal clkena0_ipd : std_logic; +signal clkena1_ipd : std_logic; +signal clkena2_ipd : std_logic; +signal clkena3_ipd : std_logic; +signal clkena4_ipd : std_logic; +signal clkena5_ipd : std_logic; +signal extclkena0_ipd : std_logic; +signal extclkena1_ipd : std_logic; +signal extclkena2_ipd : std_logic; +signal extclkena3_ipd : std_logic; +signal scanclk_ipd : std_logic; +signal scanaclr_ipd : std_logic; +signal scandata_ipd : std_logic; +signal clkswitch_ipd : std_logic; + +signal lvds_dffa_clk : std_logic; +signal lvds_dffb_clk : std_logic; +signal lvds_dffc_clk : std_logic; +signal lvds_dffd_clk : std_logic; +signal dffa_out : std_logic := '0'; +signal dffb_out : std_logic := '0'; +signal dffc_out : std_logic := '0'; +signal dffd_out : std_logic := '0'; +signal nce_temp : std_logic := '0'; +signal nce_l0 : std_logic := '0'; +signal nce_l1 : std_logic := '0'; + +signal inclk_l0_dly1 : std_logic := '0'; +signal inclk_l0_dly2 : std_logic := '0'; +signal inclk_l0_dly3 : std_logic := '0'; +signal inclk_l0_dly4 : std_logic := '0'; +signal inclk_l0_dly5 : std_logic := '0'; +signal inclk_l0_dly6 : std_logic := '0'; +signal inclk_l1_dly1 : std_logic := '0'; +signal inclk_l1_dly2 : std_logic := '0'; +signal inclk_l1_dly3 : std_logic := '0'; +signal inclk_l1_dly4 : std_logic := '0'; +signal inclk_l1_dly5 : std_logic := '0'; +signal inclk_l1_dly6 : std_logic := '0'; + + +signal sig_offset : time := 0 ps; +signal sig_refclk_time : time := 0 ps; +signal sig_fbclk_time : time := 0 ps; +signal sig_fbclk_period : time := 0 ps; +signal sig_vco_period_was_phase_adjusted : boolean := false; +signal sig_phase_adjust_was_scheduled : boolean := false; +signal sig_stop_vco : std_logic := '0'; +signal sig_m_times_vco_period : time := 0 ps; +signal sig_new_m_times_vco_period : time := 0 ps; +signal sig_got_refclk_posedge : boolean := false; +signal sig_got_fbclk_posedge : boolean := false; +signal sig_got_second_refclk : boolean := false; +signal sig_current_clock : string(1 to 6); + +signal m_delay : integer := 0; +signal n_delay : integer := 0; + +signal sig_curr_clock : string(1 to 6) := primary_clock; +signal scan_chain_length : integer := GPP_SCAN_CHAIN; + +signal ext_fbk_cntr_high : integer := 0; +signal ext_fbk_cntr_low : integer := 0; +signal ext_fbk_cntr_delay : integer := 0; +signal ext_fbk_cntr_ph : integer := 0; +signal ext_fbk_cntr_initial : integer := 1; +signal ext_fbk_cntr : string(1 to 2) := "e0"; +signal ext_fbk_cntr_mode : string(1 to 6) := "bypass"; + +signal enable0_tmp : std_logic := '0'; +signal enable1_tmp : std_logic := '0'; +signal reset_low : std_logic := '0'; + +signal scandataout_tmp : std_logic := '0'; +signal sdataout_trig : std_logic := '0'; +signal sdataout_rst_trig : std_logic := '0'; + +signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; + +signal schedule_vco : std_logic := '0'; + +signal areset_ena_sig : std_logic := '0'; +signal done_with_param_calc : boolean := false; + +COMPONENT MF_m_cntr + PORT ( clk : IN std_logic; + reset : IN std_logic; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer; + time_delay : IN integer; + ph : IN integer := 0 ); +END COMPONENT; + +COMPONENT MF_n_cntr + PORT ( clk : IN std_logic; + reset : IN std_logic; + cout : OUT std_logic; + modulus : IN integer; + time_delay : IN integer); +END COMPONENT; + +COMPONENT stx_scale_cntr + PORT ( clk : IN std_logic; + reset : IN std_logic; + cout : OUT std_logic; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + time_delay : IN integer := 0; + ph_tap : IN natural ); +END COMPONENT; + +COMPONENT dffp + + PORT ( Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +COMPONENT MF_pll_reg + PORT ( Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +begin + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + WireDelay : block + begin + inclk0_ipd <= inclk(0); + inclk1_ipd <= inclk(1); + areset_ipd <= areset; + ena_ipd <= ena; + fbin_ipd <= fbin; + pfdena_ipd <= pfdena; + clkena0_ipd <= clkena(0); + clkena1_ipd <= clkena(1); + clkena2_ipd <= clkena(2); + clkena3_ipd <= clkena(3); + clkena4_ipd <= clkena(4); + clkena5_ipd <= clkena(5); + extclkena0_ipd <= extclkena(0); + extclkena1_ipd <= extclkena(1); + extclkena2_ipd <= extclkena(2); + extclkena3_ipd <= extclkena(3); + scanclk_ipd <= scanclk; + scanaclr_ipd <= scanaclr; + scandata_ipd <= scandata; + comparator_ipd <= comparator; + clkswitch_ipd <= clkswitch; + end block; + + -- User to Advanced parameter conversion + + i_extclk3_counter <= "e3" when m=0 else extclk3_counter; + i_extclk2_counter <= "e2" when m=0 else extclk2_counter; + i_extclk1_counter <= "e1" when m=0 else extclk1_counter; + i_extclk0_counter <= "e0" when m=0 else extclk0_counter; + i_clk5_counter <= "l1" when m=0 else clk5_counter; + i_clk4_counter <= "l0" when m=0 else clk4_counter; + i_clk3_counter <= "g3" when m=0 else clk3_counter; + i_clk2_counter <= "g2" when m=0 else clk2_counter; + i_clk1_counter <= "g1" when m=0 else clk1_counter; + i_clk0_counter <= "l0" when m=0 and pll_type = "lvds" else + "g0" when m=0 else clk0_counter; + + -- end parameter conversion + + inclk_m <= extclk0_tmp when operation_mode = "external_feedback" and feedback_source = "extclk0" else + extclk1_tmp when operation_mode = "external_feedback" and feedback_source = "extclk1" else + extclk2_tmp when operation_mode = "external_feedback" and feedback_source = "extclk2" else + extclk3_tmp when operation_mode = "external_feedback" and feedback_source = "extclk3" else + vco_out(m_ph_val); + + ext_fbk_cntr <= "e0" when (feedback_source = "extclk0" and extclk0_counter = "e0") or (feedback_source = "extclk1" and extclk1_counter = "e0") or (feedback_source = "extclk2" and extclk2_counter = "e0") or (feedback_source = "extclk3" and extclk3_counter = "e0") else + "e1" when (feedback_source = "extclk0" and extclk0_counter = "e1") or (feedback_source = "extclk1" and extclk1_counter = "e1") or (feedback_source = "extclk2" and extclk2_counter = "e1") or (feedback_source = "extclk3" and extclk3_counter = "e1") else + "e2" when (feedback_source = "extclk0" and extclk0_counter = "e2") or (feedback_source = "extclk1" and extclk1_counter = "e2") or (feedback_source = "extclk2" and extclk2_counter = "e2") or (feedback_source = "extclk3" and extclk3_counter = "e2") else + "e3" when (feedback_source = "extclk0" and extclk0_counter = "e3") or (feedback_source = "extclk1" and extclk1_counter = "e3") or (feedback_source = "extclk2" and extclk2_counter = "e3") or (feedback_source = "extclk3" and extclk3_counter = "e3") else + "e0"; + + ext_fbk_cntr_high <= e0_high_val when ext_fbk_cntr = "e0" else + e1_high_val when ext_fbk_cntr = "e1" else + e2_high_val when ext_fbk_cntr = "e2" else + e3_high_val when ext_fbk_cntr = "e3" else + 1; + ext_fbk_cntr_low <= e0_low_val when ext_fbk_cntr = "e0" else + e1_low_val when ext_fbk_cntr = "e1" else + e2_low_val when ext_fbk_cntr = "e2" else + e3_low_val when ext_fbk_cntr = "e3" else + 1; + ext_fbk_cntr_delay <= e0_time_delay_val when ext_fbk_cntr = "e0" else + e1_time_delay_val when ext_fbk_cntr = "e1" else + e2_time_delay_val when ext_fbk_cntr = "e2" else + e3_time_delay_val when ext_fbk_cntr = "e3" else + 0; + + ext_fbk_cntr_ph <= e0_ph_val when ext_fbk_cntr = "e0" else + e1_ph_val when ext_fbk_cntr = "e1" else + e2_ph_val when ext_fbk_cntr = "e2" else + e3_ph_val when ext_fbk_cntr = "e3" else + 0; + + ext_fbk_cntr_initial <= e0_initial_val when ext_fbk_cntr = "e0" else + e1_initial_val when ext_fbk_cntr = "e1" else + e2_initial_val when ext_fbk_cntr = "e2" else + e3_initial_val when ext_fbk_cntr = "e3" else + 0; + ext_fbk_cntr_mode <= e0_mode_val when ext_fbk_cntr = "e0" else + e1_mode_val when ext_fbk_cntr = "e1" else + e2_mode_val when ext_fbk_cntr = "e2" else + e3_mode_val when ext_fbk_cntr = "e3" else + e0_mode_val; + + areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco; + + m1 : MF_m_cntr + port map ( clk => inclk_m, + reset => areset_ena_sig, + cout => fbclk, + initial_value => m_initial_val, + modulus => m_val, + time_delay => m_delay, + ph => m_ph_val ); + + -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed + -- in different simulation deltas. + + n1 : MF_n_cntr + port map ( clk => clkin, + reset => areset_ipd, + cout => refclk, + modulus => n_val, + time_delay => n_time_delay_val); + + inclk_l0 <= vco_out(l0_ph_val); + l0 : stx_scale_cntr + port map ( clk => inclk_l0, + reset => areset_ena_sig, + cout => l0_clk, + initial => l0_initial_val, + high => l0_high_val, + low => l0_low_val, + mode => l0_mode_val, + time_delay => l0_time_delay_val, + ph_tap => l0_ph_val); + + inclk_l1 <= vco_out(l1_ph_val); + l1 : stx_scale_cntr + port map ( clk => inclk_l1, + reset => areset_ena_sig, + cout => l1_clk, + initial => l1_initial_val, + high => l1_high_val, + low => l1_low_val, + mode => l1_mode_val, + time_delay => l1_time_delay_val, + ph_tap => l1_ph_val); + + inclk_g0 <= vco_out(g0_ph_val); + g0 : stx_scale_cntr + port map ( clk => inclk_g0, + reset => areset_ena_sig, + cout => g0_clk, + initial => g0_initial_val, + high => g0_high_val, + low => g0_low_val, + mode => g0_mode_val, + time_delay => g0_time_delay_val, + ph_tap => g0_ph_val); + + + process(g0_clk, l0_clk, l1_clk) + begin + if (g0_clk'event and g0_clk = '1') then + dffa_out <= comparator_ipd; + end if; + if (l0_clk'event and l0_clk = '1' and enable0_counter = "l0") then + dffb_out <= dffa_out; + dffc_out <= dffb_out; + dffd_out <= nce_temp; + end if; + if (l1_clk'event and l1_clk = '1' and enable0_counter = "l1") then + dffb_out <= dffa_out; + dffc_out <= dffb_out; + dffd_out <= nce_temp; + end if; + end process; + + nce_temp <= (not dffc_out) and dffb_out; + + nce_l0 <= dffd_out when enable0_counter = "l0" else '0'; + nce_l1 <= dffd_out when enable0_counter = "l1" else '0'; + + inclk_g1 <= vco_out(g1_ph_val); + g1 : stx_scale_cntr + port map ( clk => inclk_g1, + reset => areset_ena_sig, + cout => g1_clk, + initial => g1_initial_val, + high => g1_high_val, + low => g1_low_val, + mode => g1_mode_val, + time_delay => g1_time_delay_val, + ph_tap => g1_ph_val); + + inclk_g2 <= vco_out(g2_ph_val); + g2 : stx_scale_cntr + port map ( clk => inclk_g2, + reset => areset_ena_sig, + cout => g2_clk, + initial => g2_initial_val, + high => g2_high_val, + low => g2_low_val, + mode => g2_mode_val, + time_delay => g2_time_delay_val, + ph_tap => g2_ph_val); + + inclk_g3 <= vco_out(g3_ph_val); + g3 : stx_scale_cntr + port map ( clk => inclk_g3, + reset => areset_ena_sig, + cout => g3_clk, + initial => g3_initial_val, + high => g3_high_val, + low => g3_low_val, + mode => g3_mode_val, + time_delay => g3_time_delay_val, + ph_tap => g3_ph_val); + + inclk_e0 <= vco_out(e0_ph_val); + cntr_e0_initial <= 1 when operation_mode = "external_feedback" and + ext_fbk_cntr = "e0" else e0_initial_val; + cntr_e0_delay <= ext_fbk_delay when operation_mode = "external_feedback" and + ext_fbk_cntr = "e0" else + e0_time_delay_val; + e0 : stx_scale_cntr + port map ( clk => inclk_e0, + reset => areset_ena_sig, + cout => e0_clk, + initial => cntr_e0_initial, + high => e0_high_val, + low => e0_low_val, + mode => e0_mode_val, + time_delay => cntr_e0_delay, + ph_tap => e0_ph_val); + + inclk_e1 <= vco_out(e1_ph_val); + cntr_e1_initial <= 1 when operation_mode = "external_feedback" and + ext_fbk_cntr = "e1" else e1_initial_val; + cntr_e1_delay <= ext_fbk_delay when operation_mode = "external_feedback" and + ext_fbk_cntr = "e1" else + e1_time_delay_val; + e1 : stx_scale_cntr + port map ( clk => inclk_e1, + reset => areset_ena_sig, + cout => e1_clk, + initial => cntr_e1_initial, + high => e1_high_val, + low => e1_low_val, + mode => e1_mode_val, + time_delay => cntr_e1_delay, + ph_tap => e1_ph_val); + + inclk_e2 <= vco_out(e2_ph_val); + cntr_e2_initial <= 1 when operation_mode = "external_feedback" and + ext_fbk_cntr = "e2" else e2_initial_val; + cntr_e2_delay <= ext_fbk_delay when operation_mode = "external_feedback" and + ext_fbk_cntr = "e2" else + e2_time_delay_val; + e2 : stx_scale_cntr + port map ( clk => inclk_e2, + reset => areset_ena_sig, + cout => e2_clk, + initial => cntr_e2_initial, + high => e2_high_val, + low => e2_low_val, + mode => e2_mode_val, + time_delay => cntr_e2_delay, + ph_tap => e2_ph_val); + + inclk_e3 <= vco_out(e3_ph_val); + cntr_e3_initial <= 1 when operation_mode = "external_feedback" and + ext_fbk_cntr = "e3" else e3_initial_val; + cntr_e3_delay <= ext_fbk_delay when operation_mode = "external_feedback" and + ext_fbk_cntr = "e3" else + e3_time_delay_val; + e3 : stx_scale_cntr + port map ( clk => inclk_e3, + reset => areset_ena_sig, + cout => e3_clk, + initial => cntr_e3_initial, + high => e3_high_val, + low => e3_low_val, + mode => e3_mode_val, + time_delay => cntr_e3_delay, + ph_tap => e3_ph_val); + + inclk_l0_dly1 <= inclk_l0; + inclk_l0_dly2 <= inclk_l0_dly1; + inclk_l0_dly3 <= inclk_l0_dly2; + inclk_l0_dly4 <= inclk_l0_dly3; + inclk_l0_dly5 <= inclk_l0_dly4; + inclk_l0_dly6 <= inclk_l0_dly5; + + inclk_l1_dly1 <= inclk_l1; + inclk_l1_dly2 <= inclk_l1_dly1; + inclk_l1_dly3 <= inclk_l1_dly2; + inclk_l1_dly4 <= inclk_l1_dly3; + inclk_l1_dly5 <= inclk_l1_dly4; + inclk_l1_dly6 <= inclk_l1_dly5; + + process(inclk_l0_dly6, inclk_l1_dly6, areset_ipd, ena_ipd, sig_stop_vco) + variable l0_got_first_rising_edge : boolean := false; + variable l0_count : integer := 1; + variable l0_tmp, l1_tmp : std_logic := '0'; + variable l1_got_first_rising_edge : boolean := false; + variable l1_count : integer := 1; + begin + if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then + l0_count := 1; + l1_count := 1; + l0_got_first_rising_edge := false; + l1_got_first_rising_edge := false; + else + if (nce_l0 = '0') then + if (not l0_got_first_rising_edge) then + if (inclk_l0_dly6'event and inclk_l0_dly6 = '1') then + l0_got_first_rising_edge := true; + end if; + elsif (inclk_l0_dly6'event) then + l0_count := l0_count + 1; + if (l0_count = (l0_high_val + l0_low_val) * 2) then + l0_count := 1; + end if; + end if; + end if; + if (inclk_l0_dly6'event and inclk_l0_dly6 = '0') then + if (l0_count = 1) then + l0_tmp := '1'; + l0_got_first_rising_edge := false; + else + l0_tmp := '0'; + end if; + end if; + + if (nce_l1 = '0') then + if (not l1_got_first_rising_edge) then + if (inclk_l1_dly6'event and inclk_l1_dly6 = '1') then + l1_got_first_rising_edge := true; + end if; + elsif (inclk_l1_dly6'event) then + l1_count := l1_count + 1; + if (l1_count = (l1_high_val + l1_low_val) * 2) then + l1_count := 1; + end if; + end if; + end if; + if (inclk_l1_dly6'event and inclk_l1_dly6 = '0') then + if (l1_count = 1) then + l1_tmp := '1'; + l1_got_first_rising_edge := false; + else + l1_tmp := '0'; + end if; + end if; + end if; + + if (enable0_counter = "l0") then + enable0_tmp <= l0_tmp; + elsif (enable0_counter = "l1") then + enable0_tmp <= l1_tmp; + else + enable0_tmp <= '0'; + end if; + + if (enable1_counter = "l0") then + enable1_tmp <= l0_tmp; + elsif (enable1_counter = "l1") then + enable1_tmp <= l1_tmp; + else + enable1_tmp <= '0'; + end if; + + end process; + + glocked_cntr : process(clkin, ena_ipd, areset_ipd) + variable count : integer := 0; + variable output : std_logic := '0'; + begin + if (areset_ipd = '1') then + count := 0; + output := '0'; + elsif (clkin'event and clkin = '1') then + if (ena_ipd = '1') then + count := count + 1; + if (count = gate_lock_counter) then + output := '1'; + end if; + end if; + end if; + gate_locked <= output; + end process; + + locked <= gate_locked and lock when gate_lock_signal = "yes" else + lock; + + process (transfer) + variable init : boolean := true; + variable low, high : std_logic_vector(8 downto 0); + variable delay_chain : std_logic_vector(3 downto 0); + variable mn_delay_chain : std_logic_vector(0 to 3); + variable mode : string(1 to 6) := "bypass"; + variable delay_val : integer := 0; + variable is_error : boolean := false; + variable buf : line; + + -- user to advanced variables + + variable i_m_initial : natural; + variable i_m : integer := 1; + variable i_n : natural := 1; + variable i_m2 : natural; + variable i_n2 : natural; + variable i_ss : natural; + variable i_l0_high : natural; + variable i_l1_high : natural; + variable i_g0_high : natural; + variable i_g1_high : natural; + variable i_g2_high : natural; + variable i_g3_high : natural; + variable i_e0_high : natural; + variable i_e1_high : natural; + variable i_e2_high : natural; + variable i_e3_high : natural; + variable i_l0_low : natural; + variable i_l1_low : natural; + variable i_g0_low : natural; + variable i_g1_low : natural; + variable i_g2_low : natural; + variable i_g3_low : natural; + variable i_e0_low : natural; + variable i_e1_low : natural; + variable i_e2_low : natural; + variable i_e3_low : natural; + variable i_l0_initial : natural; + variable i_l1_initial : natural; + variable i_g0_initial : natural; + variable i_g1_initial : natural; + variable i_g2_initial : natural; + variable i_g3_initial : natural; + variable i_e0_initial : natural; + variable i_e1_initial : natural; + variable i_e2_initial : natural; + variable i_e3_initial : natural; + variable i_l0_mode : string(1 to 6); + variable i_l1_mode : string(1 to 6); + variable i_g0_mode : string(1 to 6); + variable i_g1_mode : string(1 to 6); + variable i_g2_mode : string(1 to 6); + variable i_g3_mode : string(1 to 6); + variable i_e0_mode : string(1 to 6); + variable i_e1_mode : string(1 to 6); + variable i_e2_mode : string(1 to 6); + variable i_e3_mode : string(1 to 6); + variable max_neg_abs : integer := 0; + variable i_l0_time_delay : natural; + variable i_l1_time_delay : natural; + variable i_g0_time_delay : natural; + variable i_g1_time_delay : natural; + variable i_g2_time_delay : natural; + variable i_g3_time_delay : natural; + variable i_e0_time_delay : natural; + variable i_e1_time_delay : natural; + variable i_e2_time_delay : natural; + variable i_e3_time_delay : natural; + variable i_m_time_delay : natural; + variable i_n_time_delay : natural; + variable i_l0_ph : natural; + variable i_l1_ph : natural; + variable i_g0_ph : natural; + variable i_g1_ph : natural; + variable i_g2_ph : natural; + variable i_g3_ph : natural; + variable i_e0_ph : natural; + variable i_e1_ph : natural; + variable i_e2_ph : natural; + variable i_e3_ph : natural; + variable i_m_ph : natural; + variable output_count : natural; + variable new_divisor : natural; + + -- variables for scaling of multiply_by and divide_by values + variable i_clk0_mult_by : integer := 1; + variable i_clk0_div_by : integer := 1; + variable i_clk1_mult_by : integer := 1; + variable i_clk1_div_by : integer := 1; + variable i_clk2_mult_by : integer := 1; + variable i_clk2_div_by : integer := 1; + variable i_clk3_mult_by : integer := 1; + variable i_clk3_div_by : integer := 1; + variable i_clk4_mult_by : integer := 1; + variable i_clk4_div_by : integer := 1; + variable i_clk5_mult_by : integer := 1; + variable i_clk5_div_by : integer := 1; + variable i_extclk0_mult_by : integer := 1; + variable i_extclk0_div_by : integer := 1; + variable i_extclk1_mult_by : integer := 1; + variable i_extclk1_div_by : integer := 1; + variable i_extclk2_mult_by : integer := 1; + variable i_extclk2_div_by : integer := 1; + variable i_extclk3_mult_by : integer := 1; + variable i_extclk3_div_by : integer := 1; + variable max_d_value : integer := 1; + variable new_multiplier : integer := 1; + + -- internal variables for storing the phase shift number.(used in lvds mode only) + variable i_clk0_phase_shift : integer := 1; + variable i_clk1_phase_shift : integer := 1; + variable i_clk2_phase_shift : integer := 1; + + begin + if (init) then + if (m = 0) then -- convert user parameters to advanced + -- set the limit of the divide_by value that can be returned by + -- the following function. + max_d_value := 500; + + -- scale down the multiply_by and divide_by values provided by the design + -- before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by, + max_d_value, i_clk5_mult_by, i_clk5_div_by); + find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by, + max_d_value, i_extclk0_mult_by, i_extclk0_div_by); + find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by, + max_d_value, i_extclk1_mult_by, i_extclk1_div_by); + find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by, + max_d_value, i_extclk2_mult_by, i_extclk2_div_by); + find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by, + max_d_value, i_extclk3_mult_by, i_extclk3_div_by); + + i_n := 1; + if (pll_type = "lvds") then + i_m := clk0_multiply_by; + else + i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, i_clk5_mult_by, + i_extclk0_mult_by, + i_extclk1_mult_by, i_extclk2_mult_by, + i_extclk3_mult_by, inclk0_input_frequency); + end if; + i_m_time_delay := maxnegabs ( str2int(clk0_time_delay), + str2int(clk1_time_delay), + str2int(clk2_time_delay), + str2int(clk3_time_delay), + str2int(clk4_time_delay), + str2int(clk5_time_delay), + str2int(extclk0_time_delay), + str2int(extclk1_time_delay), + str2int(extclk2_time_delay), + str2int(extclk3_time_delay)); + i_n_time_delay := mintimedelay(str2int(clk0_time_delay), + str2int(clk1_time_delay), + str2int(clk2_time_delay), + str2int(clk3_time_delay), + str2int(clk4_time_delay), + str2int(clk5_time_delay), + str2int(extclk0_time_delay), + str2int(extclk1_time_delay), + str2int(extclk2_time_delay), + str2int(extclk3_time_delay)); + if (pll_type = "lvds") then + i_g0_time_delay := counter_time_delay ( str2int(clk2_time_delay), + i_m_time_delay, i_n_time_delay); + else + i_g0_time_delay := counter_time_delay ( str2int(clk0_time_delay), + i_m_time_delay,i_n_time_delay); + end if; + i_g1_time_delay := counter_time_delay ( str2int(clk1_time_delay), + i_m_time_delay, i_n_time_delay); + i_g2_time_delay := counter_time_delay ( str2int(clk2_time_delay), + i_m_time_delay, i_n_time_delay); + i_g3_time_delay := counter_time_delay ( str2int(clk3_time_delay), + i_m_time_delay, i_n_time_delay); + if (pll_type = "lvds") then + i_l0_time_delay := i_g0_time_delay; + i_l1_time_delay := i_g0_time_delay; + else + i_l0_time_delay := counter_time_delay ( str2int(clk4_time_delay), + i_m_time_delay, i_n_time_delay); + i_l1_time_delay := counter_time_delay ( str2int(clk5_time_delay), + i_m_time_delay, i_n_time_delay); + end if; + i_e0_time_delay := counter_time_delay ( str2int(extclk0_time_delay), + i_m_time_delay, i_n_time_delay); + i_e1_time_delay := counter_time_delay ( str2int(extclk1_time_delay), + i_m_time_delay, i_n_time_delay); + i_e2_time_delay := counter_time_delay ( str2int(extclk2_time_delay), + i_m_time_delay, i_n_time_delay); + i_e3_time_delay := counter_time_delay ( str2int(extclk3_time_delay), + i_m_time_delay, i_n_time_delay); + + if (pll_type = "flvds") then + -- Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier := clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; + i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; + i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; + else + i_clk0_phase_shift := str2int(clk0_phase_shift); + i_clk1_phase_shift := str2int(clk1_phase_shift); + i_clk2_phase_shift := str2int(clk2_phase_shift); + end if; + + max_neg_abs := maxnegabs ( i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + str2int(clk5_phase_shift), + str2int(extclk0_phase_shift), + str2int(extclk1_phase_shift), + str2int(extclk2_phase_shift), + str2int(extclk3_phase_shift)); + i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); + if (pll_type = "lvds") then + i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n); + else + i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n); + end if; + + i_g1_ph := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_g2_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_g3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + + if (pll_type = "lvds") then + i_l0_ph := i_g0_ph; + i_l1_ph := i_g0_ph; + else + i_l0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_l1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + end if; + i_e0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_e1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_e2_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_e3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + if (pll_type = "lvds") then + i_g0_high := counter_high ( output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + else + i_g0_high := counter_high ( output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + end if; + i_g1_high := counter_high ( output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_g2_high := counter_high ( output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_g3_high := counter_high ( output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + if (pll_type = "lvds") then + i_l0_high := i_g0_high; + i_l1_high := i_g0_high; + else + i_l0_high := counter_high ( output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_l1_high := counter_high ( output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + end if; + i_e0_high := counter_high ( output_counter_value(i_extclk0_div_by, + i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle); + i_e1_high := counter_high ( output_counter_value(i_extclk1_div_by, + i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle); + i_e2_high := counter_high ( output_counter_value(i_extclk2_div_by, + i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle); + i_e3_high := counter_high ( output_counter_value(i_extclk3_div_by, + i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle); + if (pll_type = "lvds") then + i_g0_low := counter_low ( output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + else + i_g0_low := counter_low ( output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + end if; + i_g1_low := counter_low ( output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_g2_low := counter_low ( output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_g3_low := counter_low ( output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + if (pll_type = "lvds") then + i_l0_low := i_g0_low; + i_l1_low := i_g0_low; + else + i_l0_low := counter_low ( output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_l1_low := counter_low ( output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + end if; + i_e0_low := counter_low ( output_counter_value(i_extclk0_div_by, + i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle); + i_e1_low := counter_low ( output_counter_value(i_extclk1_div_by, + i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle); + i_e2_low := counter_low ( output_counter_value(i_extclk2_div_by, + i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle); + i_e3_low := counter_low ( output_counter_value(i_extclk3_div_by, + i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle); + i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); + if (pll_type = "lvds") then + i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + else + i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + end if; + + i_g1_initial := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_g2_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_g3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + if (pll_type = "lvds") then + i_l0_initial := i_g0_initial; + i_l1_initial := i_g0_initial; + else + i_l0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_l1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + end if; + i_e0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_e1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_e2_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_e3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + if (pll_type = "lvds") then + i_g0_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + else + i_g0_mode := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + end if; + i_g1_mode := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_g2_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_g3_mode := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + if (pll_type = "lvds") then + i_l0_mode := "bypass"; + i_l1_mode := "bypass"; + else + i_l0_mode := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + i_l1_mode := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n)); + end if; + i_e0_mode := counter_mode(extclk0_duty_cycle, output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n)); + i_e1_mode := counter_mode(extclk1_duty_cycle, output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n)); + i_e2_mode := counter_mode(extclk2_duty_cycle, output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n)); + i_e3_mode := counter_mode(extclk3_duty_cycle, output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n)); + + -- in external feedback mode, need to adjust M value to take + -- into consideration the external feedback counter value + if(operation_mode = "external_feedback") then + -- if there is a negative phase shift, m_initial can + -- only be 1 + if (max_neg_abs > 0) then + i_m_initial := 1; + end if; + + -- calculate the feedback counter multiplier + if (feedback_source = "extclk0") then + if (i_e0_mode = "bypass") then + output_count := 1; + else + output_count := i_e0_high + i_e0_low; + end if; + elsif (feedback_source = "extclk1") then + if (i_e1_mode = "bypass") then + output_count := 1; + else + output_count := i_e1_high + i_e1_low; + end if; + elsif (feedback_source = "extclk2") then + if (i_e2_mode = "bypass") then + output_count := 1; + else + output_count := i_e2_high + i_e2_low; + end if; + elsif (feedback_source = "extclk3") then + if (i_e3_mode = "bypass") then + output_count := 1; + else + output_count := i_e3_high + i_e3_low; + end if; + else -- default to e0 + if (i_e0_mode = "bypass") then + output_count := 1; + else + output_count := i_e0_high + i_e0_low; + end if; + end if; + + new_divisor := gcd(i_m, output_count); + i_m := i_m / new_divisor; + i_n := output_count / new_divisor; + end if; + + else -- m /= 0 + + i_n := n; + i_m := m; + i_m_initial := m_initial; + i_m_time_delay := m_time_delay; + i_n_time_delay := n_time_delay; + i_l0_time_delay := l0_time_delay; + i_l1_time_delay := l1_time_delay; + i_g0_time_delay := g0_time_delay; + i_g1_time_delay := g1_time_delay; + i_g2_time_delay := g2_time_delay; + i_g3_time_delay := g3_time_delay; + i_e0_time_delay := e0_time_delay; + i_e1_time_delay := e1_time_delay; + i_e2_time_delay := e2_time_delay; + i_e3_time_delay := e3_time_delay; + i_m_ph := m_ph; + i_l0_ph := l0_ph; + i_l1_ph := l1_ph; + i_g0_ph := g0_ph; + i_g1_ph := g1_ph; + i_g2_ph := g2_ph; + i_g3_ph := g3_ph; + i_e0_ph := e0_ph; + i_e1_ph := e1_ph; + i_e2_ph := e2_ph; + i_e3_ph := e3_ph; + i_l0_high := l0_high; + i_l1_high := l1_high; + i_g0_high := g0_high; + i_g1_high := g1_high; + i_g2_high := g2_high; + i_g3_high := g3_high; + i_e0_high := e0_high; + i_e1_high := e1_high; + i_e2_high := e2_high; + i_e3_high := e3_high; + i_l0_low := l0_low; + i_l1_low := l1_low; + i_g0_low := g0_low; + i_g1_low := g1_low; + i_g2_low := g2_low; + i_g3_low := g3_low; + i_e0_low := e0_low; + i_e1_low := e1_low; + i_e2_low := e2_low; + i_e3_low := e3_low; + i_l0_initial := l0_initial; + i_l1_initial := l1_initial; + i_g0_initial := g0_initial; + i_g1_initial := g1_initial; + i_g2_initial := g2_initial; + i_g3_initial := g3_initial; + i_e0_initial := e0_initial; + i_e1_initial := e1_initial; + i_e2_initial := e2_initial; + i_e3_initial := e3_initial; + i_l0_mode := translate_string(l0_mode); + i_l1_mode := translate_string(l1_mode); + i_g0_mode := translate_string(g0_mode); + i_g1_mode := translate_string(g1_mode); + i_g2_mode := translate_string(g2_mode); + i_g3_mode := translate_string(g3_mode); + i_e0_mode := translate_string(e0_mode); + i_e1_mode := translate_string(e1_mode); + i_e2_mode := translate_string(e2_mode); + i_e3_mode := translate_string(e3_mode); + + end if; -- user to advanced conversion. + + m_initial_val <= i_m_initial; + n_val_tmp <= i_n; + m_val_tmp <= i_m; + + if (i_m = 1) then + m_mode_val <= "bypass"; + end if; + if (i_n = 1) then + n_mode_val <= "bypass"; + end if; + + -- NOTE: m_time_delay (vco time delay) not supported for external + -- feedback mode + -- in feedback mode, m_time_delay = delay of feedback loop tap + + m_time_delay_val <= i_m_time_delay; + n_time_delay_val <= i_n_time_delay; + + m_ph_val <= i_m_ph; + + m2_val <= m2; + n2_val <= n2; + if (m2 = 1) then + m2_mode_val <= "bypass"; + end if; + if (n2 = 1) then + n2_mode_val <= "bypass"; + end if; + + if (skip_vco = "on") then + m_val_tmp <= 1; + m_initial_val <= 1; + m_time_delay_val <= 0; + m_ph_val <= 0; + end if; + + l0_ph_val <= i_l0_ph; + l1_ph_val <= i_l1_ph; + g0_ph_val <= i_g0_ph; + g1_ph_val <= i_g1_ph; + g2_ph_val <= i_g2_ph; + g3_ph_val <= i_g3_ph; + e0_ph_val <= i_e0_ph; + e1_ph_val <= i_e1_ph; + e2_ph_val <= i_e2_ph; + e3_ph_val <= i_e3_ph; + + l0_initial_val <= i_l0_initial; + l0_high_val <= i_l0_high; + l0_low_val <= i_l0_low; + l0_mode_val <= i_l0_mode; + l0_time_delay_val <= i_l0_time_delay; + + l1_initial_val <= i_l1_initial; + l1_high_val <= i_l1_high; + l1_low_val <= i_l1_low; + l1_mode_val <= i_l1_mode; + l1_time_delay_val <= i_l1_time_delay; + + g0_initial_val <= i_g0_initial; + g0_high_val <= i_g0_high; + g0_low_val <= i_g0_low; + g0_mode_val <= i_g0_mode; + g0_time_delay_val <= i_g0_time_delay; + + g1_initial_val <= i_g1_initial; + g1_high_val <= i_g1_high; + g1_low_val <= i_g1_low; + g1_mode_val <= i_g1_mode; + g1_time_delay_val <= i_g1_time_delay; + + g2_initial_val <= i_g2_initial; + g2_high_val <= i_g2_high; + g2_low_val <= i_g2_low; + g2_mode_val <= i_g2_mode; + g2_time_delay_val <= i_g2_time_delay; + + g3_initial_val <= i_g3_initial; + g3_high_val <= i_g3_high; + g3_low_val <= i_g3_low; + g3_mode_val <= i_g3_mode; + g3_time_delay_val <= i_g3_time_delay; + + if (scan_chain = "long") then + e0_initial_val <= i_e0_initial; + e0_high_val <= i_e0_high; + e0_low_val <= i_e0_low; + e0_mode_val <= i_e0_mode; + e0_time_delay_val <= i_e0_time_delay; + + e1_initial_val <= i_e1_initial; + e1_high_val <= i_e1_high; + e1_low_val <= i_e1_low; + e1_mode_val <= i_e1_mode; + e1_time_delay_val <= i_e1_time_delay; + + e2_initial_val <= i_e2_initial; + e2_high_val <= i_e2_high; + e2_low_val <= i_e2_low; + e2_mode_val <= i_e2_mode; + e2_time_delay_val <= i_e2_time_delay; + + e3_initial_val <= i_e3_initial; + e3_high_val <= i_e3_high; + e3_low_val <= i_e3_low; + e3_mode_val <= i_e3_mode; + e3_time_delay_val <= i_e3_time_delay; + + scan_chain_length <= EGPP_SCAN_CHAIN; + end if; + init := false; + done_with_param_calc <= true; + elsif (transfer'event and transfer = '1') then + reconfig_err <= false; + ASSERT false REPORT "Reconfiguring PLL" severity note; + if (scan_chain = "long") then + -- cntr e3 + delay_chain := scan_data(287 downto 284); + if (scan_data(273) = '1') then + e3_mode_val <= "bypass"; + if (scan_data(283) = '1') then + e3_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(283) = '1') then + e3_mode_val <= " odd"; + else + e3_mode_val <= " even"; + end if; + high := scan_data(272 downto 264); + low := scan_data(282 downto 274); + e3_low_val <= alt_conv_integer(low); + e3_high_val <= alt_conv_integer(high); + -- count value of 0 is actually 512 + if (alt_conv_integer(high) = 0) then + e3_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + e3_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + e3_time_delay_val <= delay_val; + + -- cntr e2 + delay_chain := scan_data(263 downto 260); + if (scan_data(249) = '1') then + e2_mode_val <= "bypass"; + if (scan_data(259) = '1') then + e2_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(259) = '1') then + e2_mode_val <= " odd"; + else + e2_mode_val <= " even"; + end if; + high := scan_data(248 downto 240); + low := scan_data(258 downto 250); + e2_low_val <= alt_conv_integer(low); + e2_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + e2_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + e2_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + e2_time_delay_val <= delay_val; + + -- cntr e1 + delay_chain := scan_data(239 downto 236); + if (scan_data(225) = '1') then + e1_mode_val <= "bypass"; + if (scan_data(235) = '1') then + e1_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(235) = '1') then + e1_mode_val <= " odd"; + else + e1_mode_val <= " even"; + end if; + high := scan_data(224 downto 216); + low := scan_data(234 downto 226); + e1_low_val <= alt_conv_integer(low); + e1_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + e1_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + e1_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + e1_time_delay_val <= delay_val; + + -- cntr e0 + delay_chain := scan_data(215 downto 212); + if (scan_data(201) = '1') then + e0_mode_val <= "bypass"; + if (scan_data(211) = '1') then + e0_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(211) = '1') then + e0_mode_val <= " odd"; + else + e0_mode_val <= " even"; + end if; + high := scan_data(200 downto 192); + low := scan_data(210 downto 202); + e0_low_val <= alt_conv_integer(low); + e0_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + e0_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + e0_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + e0_time_delay_val <= delay_val; + + end if; + -- cntr l1 + delay_chain := scan_data(191 downto 188); + if (scan_data(177) = '1') then + l1_mode_val <= "bypass"; + if (scan_data(187) = '1') then + l1_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(187) = '1') then + l1_mode_val <= " odd"; + else + l1_mode_val <= " even"; + end if; + high := scan_data(176 downto 168); + low := scan_data(186 downto 178); + l1_low_val <= alt_conv_integer(low); + l1_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + l1_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + l1_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + l1_time_delay_val <= delay_val; + + -- cntr l0 + delay_chain := scan_data(167 downto 164); + if (scan_data(153) = '1') then + l0_mode_val <= "bypass"; + if (scan_data(163) = '1') then + l0_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(163) = '1') then + l0_mode_val <= " odd"; + else + l0_mode_val <= " even"; + end if; + high := scan_data(152 downto 144); + low := scan_data(162 downto 154); + l0_low_val <= alt_conv_integer(low); + l0_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + l0_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + l0_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + l0_time_delay_val <= delay_val; + + -- cntr g3 + delay_chain := scan_data(143 downto 140); + if (scan_data(129) = '1') then + g3_mode_val <= "bypass"; + if (scan_data(139) = '1') then + g3_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(139) = '1') then + g3_mode_val <= " odd"; + else + g3_mode_val <= " even"; + end if; + high := scan_data(128 downto 120); + low := scan_data(138 downto 130); + g3_low_val <= alt_conv_integer(low); + g3_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + g3_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + g3_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + g3_time_delay_val <= delay_val; + + -- cntr g2 + delay_chain := scan_data(119 downto 116); + if (scan_data(105) = '1') then + g2_mode_val <= "bypass"; + if (scan_data(115) = '1') then + g2_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(115) = '1') then + g2_mode_val <= " odd"; + else + g2_mode_val <= " even"; + end if; + high := scan_data(104 downto 96); + low := scan_data(114 downto 106); + g2_low_val <= alt_conv_integer(low); + g2_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + g2_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + g2_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + g2_time_delay_val <= delay_val; + + -- cntr g1 + delay_chain := scan_data(95 downto 92); + if (scan_data(81) = '1') then + g1_mode_val <= "bypass"; + if (scan_data(91) = '1') then + g1_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(91) = '1') then + g1_mode_val <= " odd"; + else + g1_mode_val <= " even"; + end if; + high := scan_data(80 downto 72); + low := scan_data(90 downto 82); + g1_low_val <= alt_conv_integer(low); + g1_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + g1_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + g1_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + g1_time_delay_val <= delay_val; + + -- cntr g0 + delay_chain := scan_data(71 downto 68); + if (scan_data(57) = '1') then + g0_mode_val <= "bypass"; + if (scan_data(67) = '1') then + g0_mode_val <= " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (scan_data(67) = '1') then + g0_mode_val <= " odd"; + else + g0_mode_val <= " even"; + end if; + high := scan_data(56 downto 48); + low := scan_data(66 downto 58); + g0_low_val <= alt_conv_integer(low); + g0_high_val <= alt_conv_integer(high); + if (alt_conv_integer(high) = 0) then + g0_high_val <= 512; + end if; + if (alt_conv_integer(low) = 0) then + g0_low_val <= 512; + end if; + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + g0_time_delay_val <= delay_val; + + -- cntr M + is_error := false; + -- 'low' contains modulus for m_cntr(spread_spectrum disabled) + low := scan_data(32 downto 24); + m_val_tmp <= alt_conv_integer(low); + if (scan_data(33) /= '1') then + if (alt_conv_integer(low) = 1) then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal 1 value for M counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning; + elsif (alt_conv_integer(low) = 0) then + m_val_tmp <= 512; + end if; + if (not is_error) then + if (m_mode_val = "bypass") then + ASSERT false REPORT "M counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning; + else + write (buf, string'(" M modulus = ")); + write (buf, alt_conv_integer(low)); + writeline (output, buf); + end if; + m_mode_val <= " "; + end if; + elsif (scan_data(33) = '1') then + if (scan_data(24) /= '0') then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal value for M counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning; + else + if (m_mode_val /= "bypass") then + ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + write (buf, string'(" M modulus = ")); + write (buf, 1); + writeline (output, buf); + m_val_tmp <= 1; + m_mode_val <= "bypass"; + end if; + end if; + + if (skip_vco = "on") then + m_val_tmp <= 1; + ASSERT FALSE REPORT "VCO is bypassed, setting M modulus = 1, M time delay = 0" severity note; + end if; + + -- cntr M2 + if (ss > 0) then + is_error := false; + low := scan_data(42 downto 34); + m2_val <= alt_conv_integer(low); + if (scan_data(43) /= '1') then + if (alt_conv_integer(low) = 1) then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal 1 value for M2 counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning; + elsif (alt_conv_integer(low) = 0) then + m2_val <= 512; + end if; + if (not is_error) then + if (m2_mode_val = "bypass") then + ASSERT false REPORT "M2 counter switched from BYPASS mode to enabled (M2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning; + else + write (buf, string'(" M2 modulus = ")); + write (buf, alt_conv_integer(low)); + writeline (output, buf); + end if; + m2_mode_val <= " "; + end if; + elsif (scan_data(43) = '1') then + if (scan_data(34) /= '0') then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal value for M2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning; + else + if (m2_mode_val /= "bypass") then + ASSERT false REPORT "M2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + write (buf, string'(" M2 modulus = ")); + write (buf, 1); + writeline (output, buf); + m2_val <= 1; + m2_mode_val <= "bypass"; + end if; + end if; + if (m_mode_val /= m2_mode_val) then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Incompatible modes for M1/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning; + end if; + end if; + + delay_chain := scan_data(47 downto 44); + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + m_time_delay_val <= delay_val; + if (skip_vco = "on") then + m_time_delay_val <= 0; + delay_val := 0; + end if; + write (buf, string'(" M time delay = ")); + write (buf, delay_val); + writeline (output, buf); + + -- cntr N + is_error := false; + -- 'low' contains modulus for n_cntr(spread_spectrum disabled) + low := scan_data(8 downto 0); + n_val_tmp <= alt_conv_integer(low); + if (scan_data(9) /= '1') then + if (alt_conv_integer(low) = 1) then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal 1 value for N counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning; + elsif (alt_conv_integer(low) = 0) then + n_val_tmp <= 512; + write (buf, string'(" N modulus = ")); + write (buf, 512); + writeline (output, buf); + else + write (buf, string'(" N modulus = ")); + write (buf, alt_conv_integer(low)); + writeline (output, buf); + end if; + if (not is_error) then + if (n_mode_val = "bypass") then + ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning; + else + write (buf, string'(" N modulus = ")); + write (buf, alt_conv_integer(low)); + writeline (output, buf); + end if; + n_mode_val <= " "; + end if; + elsif (scan_data(9) = '1') then + if (scan_data(0) /= '0') then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning; + else + if (n_mode_val /= "bypass") then + ASSERT false REPORT "N counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + write (buf, string'(" N modulus = ")); + write (buf, 1); + writeline (output, buf); + n_val_tmp <= 1; + n_mode_val <= "bypass"; + end if; + end if; + + -- cntr N2 + if (ss > 0) then + is_error := false; + low := scan_data(18 downto 10); + n2_val <= alt_conv_integer(low); + if (scan_data(19) /= '1') then + if (alt_conv_integer(low) = 1) then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal 1 value for N2 counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning; + elsif (alt_conv_integer(low) = 0) then + n2_val <= 512; + end if; + if (not is_error) then + if (n2_mode_val = "bypass") then + ASSERT false REPORT "N2 counter switched from BYPASS mode to enabled (N2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning; + else + write (buf, string'(" N2 modulus = ")); + write (buf, alt_conv_integer(low)); + writeline (output, buf); + end if; + n2_mode_val <= " "; + end if; + elsif (scan_data(19) = '1') then + if (scan_data(10) /= '0') then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Illegal value for N2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning; + else + if (n2_mode_val /= "bypass") then + ASSERT false REPORT "N2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + write (buf, string'(" N2 modulus = ")); + write (buf, 1); + writeline (output, buf); + n2_val <= 1; + n2_mode_val <= "bypass"; + end if; + end if; + if (n_mode_val /= n2_mode_val) then + is_error := true; + reconfig_err <= true; + ASSERT false REPORT "Incompatible modes for N1/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning; + end if; + end if; + + delay_chain := scan_data(23 downto 20); + delay_val := alt_conv_integer(delay_chain); + delay_val := delay_val * 250; + if (delay_val > 3000) then + delay_val := 3000; + end if; + n_time_delay_val <= delay_val; + write (buf, string'(" N time delay = ")); + write (buf, delay_val); + writeline (output, buf); + + else + if (scan_chain = "long") then + write (buf, string'(" E3 high = ")); + write (buf, e3_high_val); + write (buf, string'(" , E3 low = ")); + write (buf, e3_low_val); + write (buf, string'(" , E3 mode = ")); + write (buf, e3_mode_val); + write (buf, string'(" , E3 time delay = ")); + write (buf, e3_time_delay_val); + writeline(output, buf); + + write (buf, string'(" E2 high = ")); + write (buf, e2_high_val); + write (buf, string'(" , E2 low = ")); + write (buf, e2_low_val); + write (buf, string'(" , E2 mode = ")); + write (buf, e2_mode_val); + write (buf, string'(" , E2 time delay = ")); + write (buf, e2_time_delay_val); + writeline(output, buf); + + write (buf, string'(" E1 high = ")); + write (buf, e1_high_val); + write (buf, string'(" , E1 low = ")); + write (buf, e1_low_val); + write (buf, string'(" , E1 mode = ")); + write (buf, e1_mode_val); + write (buf, string'(" , E1 time delay = ")); + write (buf, e1_time_delay_val); + writeline(output, buf); + + write (buf, string'(" E0 high = ")); + write (buf, e0_high_val); + write (buf, string'(" , E0 low = ")); + write (buf, e0_low_val); + write (buf, string'(" , E0 mode = ")); + write (buf, e0_mode_val); + write (buf, string'(" , E0 time delay = ")); + write (buf, e0_time_delay_val); + writeline(output, buf); + end if; + + write (buf, string'(" L1 high = ")); + write (buf, l1_high_val); + write (buf, string'(" , L1 low = ")); + write (buf, l1_low_val); + write (buf, string'(" , L1 mode = ")); + write (buf, l1_mode_val); + write (buf, string'(" , L1 time delay = ")); + write (buf, l1_time_delay_val); + writeline(output, buf); + + write (buf, string'(" L0 high = ")); + write (buf, l0_high_val); + write (buf, string'(" , L0 low = ")); + write (buf, l0_low_val); + write (buf, string'(" , L0 mode = ")); + write (buf, l0_mode_val); + write (buf, string'(" , L0 time delay = ")); + write (buf, l0_time_delay_val); + writeline(output, buf); + + write (buf, string'(" G3 high = ")); + write (buf, g3_high_val); + write (buf, string'(" , G3 low = ")); + write (buf, g3_low_val); + write (buf, string'(" , G3 mode = ")); + write (buf, g3_mode_val); + write (buf, string'(" , G3 time delay = ")); + write (buf, g3_time_delay_val); + writeline(output, buf); + + write (buf, string'(" G2 high = ")); + write (buf, g2_high_val); + write (buf, string'(" , G2 low = ")); + write (buf, g2_low_val); + write (buf, string'(" , G2 mode = ")); + write (buf, g2_mode_val); + write (buf, string'(" , G2 time delay = ")); + write (buf, g2_time_delay_val); + writeline(output, buf); + + write (buf, string'(" G1 high = ")); + write (buf, g1_high_val); + write (buf, string'(" , G1 low = ")); + write (buf, g1_low_val); + write (buf, string'(" , G1 mode = ")); + write (buf, g1_mode_val); + write (buf, string'(" , G1 time delay = ")); + write (buf, g1_time_delay_val); + writeline(output, buf); + + write (buf, string'(" G0 high = ")); + write (buf, g0_high_val); + write (buf, string'(" , G0 low = ")); + write (buf, g0_low_val); + write (buf, string'(" , G0 mode = ")); + write (buf, g0_mode_val); + write (buf, string'(" , G0 time delay = ")); + write (buf, g0_time_delay_val); + writeline(output, buf); + + end if; + end process; + + process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, inclk0_ipd, inclk1_ipd, clkswitch_ipd, done_with_param_calc) + variable sched_time : time := 0 ps; + + TYPE time_array is ARRAY (0 to 7) of time; + variable init : boolean := true; + variable refclk_period : time; + variable primary_clock_frequency : time; + variable m_times_vco_period : time; + variable new_m_times_vco_period : time; + + variable phase_shift : time_array := (OTHERS => 0 ps); + variable last_phase_shift : time_array := (OTHERS => 0 ps); + + variable l_index : integer := 1; + variable cycle_to_adjust : integer := 0; + + variable stop_vco : boolean := false; + + variable locked_tmp : std_logic := '0'; + variable pll_is_locked : boolean := false; + variable pll_about_to_lock : boolean := false; + variable cycles_to_lock : integer := 0; + variable cycles_to_unlock : integer := 0; + + variable got_first_refclk : boolean := false; + variable got_second_refclk : boolean := false; + variable got_first_fbclk : boolean := false; + + variable refclk_time : time := 0 ps; + variable fbclk_time : time := 0 ps; + variable first_fbclk_time : time := 0 ps; + + variable fbclk_period : time := 0 ps; + + variable first_schedule : boolean := true; + variable schedule_offset : boolean := true; + + variable vco_val : std_logic := '0'; + variable vco_period_was_phase_adjusted : boolean := false; + variable phase_adjust_was_scheduled : boolean := false; + + variable loop_xplier : integer; + variable loop_initial : integer := 0; + variable loop_ph : integer := 0; + variable loop_time_delay : integer := 0; + + variable initial_delay : time := 0 ps; + variable vco_per : time; + variable tmp_rem : integer; + variable my_rem : integer; + variable fbk_phase : integer := 0; + + variable pull_back_ext_fbk_cntr : integer := 0; + variable pull_back_M : integer := 0; + variable total_pull_back : integer := 0; + variable fbk_delay : integer := 0; + + variable offset : time := 0 ps; + + variable tmp_vco_per : integer := 0; + variable high_time : time; + variable low_time : time; + + variable got_refclk_posedge : boolean := false; + variable got_fbclk_posedge : boolean := false; + variable inclk_out_of_range : boolean := false; + variable no_warn : boolean := false; + variable init_clks : boolean := true; + variable ext_fbk_cntr_modulus : integer := 1; + variable pll_is_in_reset : boolean := false; + + -- clkswitch variables + variable other_clock_value : std_logic := '0'; + variable other_clock_last_value : std_logic; + variable current_clock : string(1 to 6) := primary_clock; + variable clk0_count, clk1_count : integer := 0; + variable clk0_is_bad, clk1_is_bad : std_logic := '0'; + variable primary_clk_is_bad : boolean := false; + variable current_clk_is_bad : boolean := false; + variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; + variable switch_over_count : integer := 0; + variable active_clock : std_logic := '0'; + variable external_switch : boolean := false; + + begin + if (init and done_with_param_calc) then + if (pll_type = "fast") then + locked_tmp := '1'; + end if; + m_val <= m_val_tmp; + n_val <= n_val_tmp; + -- jump-start the VCO + -- add 1 ps delay to ensure all signals are updated to initial + -- values + schedule_vco <= transport not schedule_vco after 1 ps; + + init := false; + end if; + + -- merged from separate process + if (now = 0 ps) then + if (current_clock = "inclk1") then + active_clock := '1'; + end if; + end if; + if (clkswitch_ipd'event and clkswitch_ipd = '1') then + external_switch := true; + end if; + -- save the current inclk event value + if (inclk0_ipd'event) then + if (current_clock /= "inclk0") then + other_clock_value := inclk0_ipd; + end if; + end if; + if (inclk1_ipd'event) then + if (current_clock /= "inclk1") then + other_clock_value := inclk1_ipd; + end if; + end if; + + -- check if either input clk is bad + if (inclk0_ipd'event and inclk0_ipd = '1') then + clk0_count := clk0_count + 1; + clk0_is_bad := '0'; + if (current_clock = "inclk0") then + current_clk_is_bad := false; + end if; + clk1_count := 0; + if (clk0_count > 2) then + -- no event on other clk for 2 cycles + clk1_is_bad := '1'; + if (current_clock = "inclk1") then + current_clk_is_bad := true; + end if; + end if; + end if; + if (inclk1_ipd'event and inclk1_ipd = '1') then + clk1_count := clk1_count + 1; + clk1_is_bad := '0'; + if (current_clock = "inclk1") then + current_clk_is_bad := false; + end if; + clk0_count := 0; + if (clk1_count > 2) then + -- no event on other clk for 2 cycles + clk0_is_bad := '1'; + if (current_clock = "inclk0") then + current_clk_is_bad := true; + end if; + end if; + end if; + + -- check if the bad clk is the primary clock + if ((primary_clock = "inclk0" and clk0_is_bad = '1') or (primary_clock = "inclk1" and clk1_is_bad = '1')) then + primary_clk_is_bad := true; + else + primary_clk_is_bad := false; + end if; + + -- actual switching + if (inclk0_ipd'event and current_clock = "inclk0") then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk0_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk0_ipd; + end if; + else + clkin <= transport inclk0_ipd; + end if; + end if; + if (inclk1_ipd'event and current_clock = "inclk1") then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk1_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk1_ipd; + end if; + else + clkin <= transport inclk1_ipd; + end if; + end if; + if (inclk0_ipd'event or inclk1_ipd'event) then + if ( (other_clock_value = '1') and + (other_clock_value /= other_clock_last_value) and + (switch_over_on_lossclk = "on") and + (enable_switch_over_counter = "on") and + (primary_clk_is_bad) ) then + switch_over_count := switch_over_count + 1; + end if; + if ((other_clock_value = '0') and (other_clock_value /= other_clock_last_value)) then + if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then + got_curr_clk_falling_edge_after_clkswitch := false; + if (current_clock = "inclk0") then + current_clock := "inclk1"; + else + current_clock := "inclk0"; + end if; + active_clock := not active_clock; + switch_over_count := 0; + external_switch := false; + current_clk_is_bad := false; + end if; + end if; + other_clock_last_value := other_clock_value; + end if; + + -- schedule outputs + clkbad(0) <= clk0_is_bad; + clkbad(1) <= clk1_is_bad; + if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then + if (primary_clk_is_bad) then + -- assert clkloss + clkloss <= '1'; + else + clkloss <= '0'; + end if; + else + clkloss <= clkswitch_ipd; + end if; + activeclock <= active_clock; + + -- end -- clkswitch + + if (schedule_vco'event) then + if (init_clks) then + if (primary_clock = "inclk0") then + refclk_period := inclk0_input_frequency * n_val * 1 ps; + primary_clock_frequency := inclk0_input_frequency * 1 ps; + elsif (primary_clock = "inclk1") then + refclk_period := inclk1_input_frequency * n_val * 1 ps; + primary_clock_frequency := inclk1_input_frequency * 1 ps; + end if; + + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + init_clks := false; + end if; + sched_time := 0 ps; + for i in 0 to 7 loop + last_phase_shift(i) := phase_shift(i); + end loop; + cycle_to_adjust := 0; + l_index := 1; + m_times_vco_period := new_m_times_vco_period; + end if; + + -- areset was asserted + if (areset_ipd'event and areset_ipd = '1') then + assert false report family_name & " PLL was reset" severity note; + end if; + + -- areset deasserted + if (areset_ipd'event and areset_ipd = '0') then + if (scandataout_tmp = '1') then + sdataout_rst_trig <= transport not sdataout_rst_trig; + end if; + end if; + + -- ena was deasserted + if (ena_ipd'event and ena_ipd = '0') then + assert false report family_name & " PLL was disabled" severity note; + end if; + + if (schedule_vco'event and (areset_ipd = '1' or ena_ipd = '0' or stop_vco)) then + if (areset_ipd = '1') then + pll_is_in_reset := true; + end if; + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after last_phase_shift(i); + phase_shift(i) := 0 ps; + last_phase_shift(i) := 0 ps; + end loop; + + -- reset lock parameters + locked_tmp := '0'; + if (pll_type = "fast") then + locked_tmp := '1'; + end if; + pll_is_locked := false; + pll_about_to_lock := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + + got_first_refclk := false; + got_second_refclk := false; + refclk_time := 0 ps; + got_first_fbclk := false; + fbclk_time := 0 ps; + first_fbclk_time := 0 ps; + fbclk_period := 0 ps; + + first_schedule := true; + schedule_offset := true; + vco_val := '0'; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + + elsif ((schedule_vco'event or ena_ipd'event or areset_ipd'event) and areset_ipd = '0' and ena_ipd = '1' and (not stop_vco) and (now > 0 ps)) then + + -- note areset deassert time + -- note it as refclk_time to prevent false triggering + -- of stop_vco after areset + if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then + refclk_time := now; + pll_is_in_reset := false; + end if; + + -- calculate loop_xplier : this will be different from m_val + -- in external_feedback_mode + loop_xplier := m_val; + loop_initial := m_initial_val - 1; + loop_ph := m_ph_val; + loop_time_delay := m_time_delay_val; + + if (operation_mode = "external_feedback") then + if (ext_fbk_cntr_mode = "bypass") then + ext_fbk_cntr_modulus := 1; + else + ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low; + end if; + + loop_xplier := m_val * (ext_fbk_cntr_modulus); + loop_ph := ext_fbk_cntr_ph; + loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * (ext_fbk_cntr_modulus)); + loop_time_delay := m_time_delay_val + ext_fbk_cntr_delay; + end if; + + -- convert initial value to delay + initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; + + -- convert loop ph_tap to delay + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier; + if (my_rem /= 0) then + tmp_vco_per := tmp_vco_per + 1; + end if; + fbk_phase := (loop_ph * tmp_vco_per)/8; + + if (operation_mode = "external_feedback") then + pull_back_ext_fbk_cntr := ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier)/1 ps + fbk_phase; + while (pull_back_ext_fbk_cntr > refclk_period/1 ps) loop + pull_back_ext_fbk_cntr := pull_back_ext_fbk_cntr - refclk_period/ 1 ps; + end loop; + pull_back_M := m_time_delay_val + (m_initial_val - 1) * (ext_fbk_cntr_modulus) * ((refclk_period/loop_xplier)/1 ps); + while (pull_back_M > refclk_period/1 ps) loop + pull_back_M := pull_back_M - refclk_period/ 1 ps; + end loop; + else + pull_back_ext_fbk_cntr := 0; + pull_back_M := initial_delay/1 ps + m_time_delay_val + fbk_phase; + end if; + + total_pull_back := pull_back_M + pull_back_ext_fbk_cntr; + + if (simulation_type = "timing") then + total_pull_back := total_pull_back + pll_compensation_delay; + end if; + while (total_pull_back > refclk_period/1 ps) loop + total_pull_back := total_pull_back - refclk_period/1 ps; + end loop; + + if (total_pull_back > 0) then + offset := refclk_period - (total_pull_back * 1 ps); + end if; + if (operation_mode = "external_feedback") then + fbk_delay := pull_back_M; + if (simulation_type = "timing") then + fbk_delay := fbk_delay + pll_compensation_delay; + end if; + ext_fbk_delay <= transport (pull_back_ext_fbk_cntr - fbk_phase) after 1 ps; + else + fbk_delay := total_pull_back - fbk_phase; + if (fbk_delay < 0) then + offset := offset - (fbk_phase * 1 ps); + fbk_delay := total_pull_back; + end if; + end if; + + -- assign m_delay + m_delay <= transport fbk_delay after 1 ps; + + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + for i in 1 to loop_xplier loop + -- adjust cycles + tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier; + if (my_rem /= 0 and l_index <= my_rem) then + tmp_rem := (loop_xplier * l_index) rem my_rem; + cycle_to_adjust := (loop_xplier * l_index) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + if (cycle_to_adjust = i) then + tmp_vco_per := tmp_vco_per + 1; + l_index := l_index + 1; + end if; + + -- calculate high and low periods + vco_per := tmp_vco_per * 1 ps; + high_time := (tmp_vco_per/2) * 1 ps; + if (tmp_vco_per rem 2 /= 0) then + high_time := high_time + 1 ps; + end if; + low_time := vco_per - high_time; + + -- schedule the rising and falling edges + for j in 1 to 2 loop + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + + -- add offset + if (schedule_offset) then + sched_time := sched_time + offset; + schedule_offset := false; + end if; + + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + if (first_schedule) then + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + else + vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k)); + end if; + end loop; + end loop; + end loop; + + -- schedule once more + if (first_schedule) then + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + end loop; + first_schedule := false; + end if; + + if (sched_time > 0 ps) then + schedule_vco <= transport not schedule_vco after sched_time; + end if; + + if (vco_period_was_phase_adjusted) then + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := true; + + vco_per := m_times_vco_period/loop_xplier; + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + end loop; + end if; + end if; + + if (refclk'event and refclk = '1' and areset_ipd = '0') then + n_val <= n_val_tmp; + got_refclk_posedge := true; + if (not got_first_refclk) then + got_first_refclk := true; + else + got_second_refclk := true; + refclk_period := now - refclk_time; + + -- check if incoming freq. will cause VCO range to be + -- exceeded + if ((vco_max /= 0 and vco_min /= 0 and skip_vco = "off" and pfdena_ipd = '1') and + (((refclk_period/1 ps)/loop_xplier > vco_max) or + ((refclk_period/1 ps)/loop_xplier < vco_min)) ) then + if (pll_is_locked) then + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning; + if (inclk_out_of_range) then + -- unlock + pll_is_locked := false; + locked_tmp := '0'; + if (pll_type = "fast") then + locked_tmp := '1'; + end if; + pll_about_to_lock := false; + cycles_to_lock := 0; + assert false report family_name & " PLL lost lock" severity note; + first_schedule := true; + schedule_offset := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + elsif (not no_warn) then + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock." severity warning; + no_warn := true; + end if; + inclk_out_of_range := true; + else + inclk_out_of_range := false; + end if; + end if; + + if (stop_vco) then + stop_vco := false; + schedule_vco <= not schedule_vco; + end if; + + refclk_time := now; + else + got_refclk_posedge := false; + end if; + + if (fbclk'event and fbclk = '1') then + m_val <= transport m_val_tmp after 1 ps; + got_fbclk_posedge := true; + if (not got_first_fbclk) then + got_first_fbclk := true; + else + fbclk_period := now - fbclk_time; + end if; + + -- need refclk_period here, so initialized to proper value above + if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ((now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then + stop_vco := true; + -- reset + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + if (pll_is_locked) then + pll_is_locked := false; + locked_tmp := '0'; + if (pll_type = "fast") then + locked_tmp := '1'; + end if; + assert false report family_name & " PLL lost lock due to loss of input clock" severity note; + end if; + pll_about_to_lock := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + first_schedule := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + fbclk_time := now; + else + got_fbclk_posedge := false; + end if; + + if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then + + -- now we know actual incoming period + if ( abs(fbclk_time - refclk_time) <= 5 ps or + (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + -- considered in phase + if (cycles_to_lock = valid_lock_multiplier - 1) then + pll_about_to_lock := true; + end if; + if (cycles_to_lock = valid_lock_multiplier) then + if (not pll_is_locked) then + assert (quiet_period_violation) report family_name & " PLL locked to incoming clock" severity note; + end if; + pll_is_locked := true; + locked_tmp := '1'; + if (pll_type = "fast") then + locked_tmp := '0'; + end if; + end if; + -- increment lock counter only if second part of above + -- time check is NOT true + if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + cycles_to_lock := cycles_to_lock + 1; + end if; + + -- adjust m_times_vco_period + new_m_times_vco_period := refclk_period; + else + -- if locked, begin unlock + if (pll_is_locked) then + cycles_to_unlock := cycles_to_unlock + 1; + if (cycles_to_unlock = invalid_lock_multiplier) then + pll_is_locked := false; + locked_tmp := '0'; + if (pll_type = "fast") then + locked_tmp := '1'; + end if; + pll_about_to_lock := false; + cycles_to_lock := 0; + assert (quiet_period_violation) report family_name & " PLL lost lock" severity note; + first_schedule := true; + schedule_offset := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + end if; + if ( abs(refclk_period - fbclk_period) <= 2 ps ) then + -- frequency is still good + if (now = fbclk_time and (not phase_adjust_was_scheduled)) then + if ( abs(fbclk_time - refclk_time) > refclk_period/2) then + if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then + -- input clock may have stopped; do nothing + else + new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted := true; + end if; + else + new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted := true; + end if; + + end if; + else + phase_adjust_was_scheduled := false; + new_m_times_vco_period := refclk_period; + end if; + end if; + end if; + + if (pfdena_ipd = '0') then + locked_tmp := 'X'; + pll_is_locked := false; + cycles_to_lock := 0; + end if; + + -- give message only at time of deassertion + if (pfdena_ipd'event and pfdena_ipd = '0') then + assert false report "PFDENA deasserted." severity note; + elsif (pfdena_ipd'event and pfdena_ipd = '1') then + got_first_refclk := false; + got_second_refclk := false; + refclk_time := now; + end if; + + if (quiet_period_violation or reconfig_err or scanclr_violation or scanclr_clk_violation) then + lock <= '0'; + if (pll_type = "fast") then + lock <= '1'; + end if; + else + lock <= locked_tmp; + end if; + about_to_lock <= pll_about_to_lock after 1 ps; + + -- signal to calculate quiet_time + sig_refclk_period <= refclk_period; + sig_current_clock <= current_clock; + + -- signals for debugging + sig_offset <= offset; + sig_refclk_time <= refclk_time; + sig_fbclk_time <= fbclk_time; + sig_fbclk_period <= fbclk_period; + sig_vco_period_was_phase_adjusted <= vco_period_was_phase_adjusted; + sig_phase_adjust_was_scheduled <= phase_adjust_was_scheduled; + if (stop_vco = true) then + sig_stop_vco <= '1'; + else + sig_stop_vco <= '0'; + end if; + sig_m_times_vco_period <= m_times_vco_period; + sig_new_m_times_vco_period <= new_m_times_vco_period; + sig_got_refclk_posedge <= got_refclk_posedge; + sig_got_fbclk_posedge <= got_fbclk_posedge; + sig_got_second_refclk <= got_second_refclk; + end process; + + process (scanclk_ipd, scanaclr_ipd, scan_data, transfer, sdataout_trig, sdataout_rst_trig) + variable j : integer := 0; + variable pll_in_quiet_period : boolean := false; + variable start_quiet_time : time := 0 ps; + variable quiet_time : time := 0 ps; + variable scanclr_rising_time : time := 0 ps; + variable scanclr_falling_time : time := 0 ps; + variable got_first_scanclk_after_scanclr_inactive_edge : boolean := false; + variable scan_chain_being_reset : boolean := false; + + function slowest_clk ( L0 : integer; L0_mode : string(1 to 6); + L1 : integer; L1_mode : string(1 to 6); + G0 : integer; G0_mode : string(1 to 6); + G1 : integer; G1_mode : string(1 to 6); + G2 : integer; G2_mode : string(1 to 6); + G3 : integer; G3_mode : string(1 to 6); + E0 : integer; E0_mode : string(1 to 6); + E1 : integer; E1_mode : string(1 to 6); + E2 : integer; E2_mode : string(1 to 6); + E3 : integer; E3_mode : string(1 to 6); + scan_chain : string; + refclk : time; m_mod : integer) return time is + variable max_modulus : integer := 1; + variable q_period : time := 0 ps; + variable refclk_int : integer := 0; + begin + if (L0_mode /= "bypass" and L0_mode /= " off") then + max_modulus := L0; + end if; + if (L1 > max_modulus and L1_mode /= "bypass" and L1_mode /= " off") then + max_modulus := L1; + end if; + if (G0 > max_modulus and G0_mode /= "bypass" and G0_mode /= " off") then + max_modulus := G0; + end if; + if (G1 > max_modulus and G1_mode /= "bypass" and G1_mode /= " off") then + max_modulus := G1; + end if; + if (G2 > max_modulus and G2_mode /= "bypass" and G2_mode /= " off") then + max_modulus := G2; + end if; + if (G3 > max_modulus and G3_mode /= "bypass" and G3_mode /= " off") then + max_modulus := G3; + end if; + if (scan_chain = "long") then + if (E0 > max_modulus and E0_mode /= "bypass" and E0_mode /= " off") then + max_modulus := E0; + end if; + if (E1 > max_modulus and E1_mode /= "bypass" and E1_mode /= " off") then + max_modulus := E1; + end if; + if (E2 > max_modulus and E2_mode /= "bypass" and E2_mode /= " off") then + max_modulus := E2; + end if; + if (E3 > max_modulus and E3_mode /= "bypass" and E3_mode /= " off") then + max_modulus := E3; + end if; + end if; + refclk_int := refclk / 1 ps; + if (m_mod /= 0) then + q_period := ((refclk_int/m_mod) * max_modulus) * 1 ps; + end if; + return (2*q_period); + end slowest_clk; + + begin + if (transfer'event) then + if (transfer = '0') then + -- clear the chain + for i in scan_data'range loop + scan_data(i) <= '0'; + end loop; + end if; + elsif (scanaclr_ipd'event and scanaclr_ipd = '1') then + -- scanaclr rising + scanclr_rising_time := now; + scan_chain_being_reset := true; + elsif (scanaclr_ipd'event and scanaclr_ipd = '0') then + -- scanaclr falling + scanclr_falling_time := now; + if (scan_chain_being_reset and (now - scanclr_rising_time < TRST)) then + scanclr_violation <= true; + ASSERT false REPORT "Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is "& int2str((now - scanclr_rising_time) / 1 ps) &". The PLL may not function correctly." severity warning; + else + scanclr_violation <= false; + for i in scan_data'range loop + scan_data(i) <= '0'; + end loop; + end if; + scan_chain_being_reset := false; + got_first_scanclk_after_scanclr_inactive_edge := false; + elsif (scanclk_ipd'event and scanclk_ipd = '1' and not got_first_scanclk_after_scanclr_inactive_edge and (now - scanclr_falling_time < TRSTCLK)) then + scanclr_clk_violation <= true; + got_first_scanclk_after_scanclr_inactive_edge := true; + + ASSERT false REPORT "Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is "& int2str((now - scanclr_falling_time) / 1 ps) &". Reconfiguration may not work." severity warning; + elsif (scanclk_ipd'event and scanclk_ipd = '1' and scanaclr_ipd = '0') then + if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then + ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning; + quiet_period_violation <= true; + else + pll_in_quiet_period := false; + for j in scan_chain_length-1 downto 1 loop + scan_data(j) <= scan_data(j-1); + end loop; + scan_data(0) <= scandata_ipd; + end if; + if (not got_first_scanclk_after_scanclr_inactive_edge) then + got_first_scanclk_after_scanclr_inactive_edge := true; + scanclr_clk_violation <= false; + end if; + elsif (scanclk_ipd'event and scanclk_ipd = '0' and scanaclr_ipd = '0') then + if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then + ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning; + quiet_period_violation <= true; + elsif (scan_data(scan_chain_length-1) = '1') then + -- reset violation flag only after another reconfig seq. + quiet_period_violation <= false; + + -- initiate transfer + transfer <= '1'; + transfer <= transport '0' after 1 ps; + scandataout_tmp <= '1'; + pll_in_quiet_period := true; + start_quiet_time := now; + quiet_time := slowest_clk ( l0_high_val+l0_low_val, l0_mode_val, + l1_high_val+l1_low_val, l1_mode_val, + g0_high_val+g0_low_val, g0_mode_val, + g1_high_val+g1_low_val, g1_mode_val, + g2_high_val+g2_low_val, g2_mode_val, + g3_high_val+g3_low_val, g3_mode_val, + e0_high_val+e0_low_val, e0_mode_val, + e1_high_val+e1_low_val, e1_mode_val, + e2_high_val+e2_low_val, e2_mode_val, + e3_high_val+e3_low_val, e3_mode_val, + scan_chain, sig_refclk_period, m_val); + sdataout_trig <= transport not sdataout_trig after quiet_time; + end if; + elsif (sdataout_trig'event) then + if (areset_ipd = '0') then + scandataout_tmp <= transport '0'; + end if; + elsif (sdataout_rst_trig'event) then + scandataout_tmp <= transport '0' after quiet_time; + end if; + end process; + + clk0_tmp <= l0_clk when i_clk0_counter = "l0" else + l1_clk when i_clk0_counter = "l1" else + g0_clk when i_clk0_counter = "g0" else + g1_clk when i_clk0_counter = "g1" else + g2_clk when i_clk0_counter = "g2" else + g3_clk when i_clk0_counter = "g3" else + '0'; + not_clk0_tmp <= not clk0_tmp; + ena0_reg : dffp + port map ( D => clkena(0), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_clk0_tmp, + Q => ena0 ); + + clk(0) <= ena0 and clk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + ena0 and 'X'; + + clk1_tmp <= l0_clk when i_clk1_counter = "l0" else + l1_clk when i_clk1_counter = "l1" else + g0_clk when i_clk1_counter = "g0" else + g1_clk when i_clk1_counter = "g1" else + g2_clk when i_clk1_counter = "g2" else + g3_clk when i_clk1_counter = "g3" else + '0'; + not_clk1_tmp <= not clk1_tmp; + ena1_reg : dffp + port map ( D => clkena(1), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_clk1_tmp, + Q => ena1 ); + + clk(1) <= ena1 and clk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + ena1 and 'X'; + + clk2_tmp <= l0_clk when i_clk2_counter = "l0" else + l1_clk when i_clk2_counter = "l1" else + g0_clk when i_clk2_counter = "g0" else + g1_clk when i_clk2_counter = "g1" else + g2_clk when i_clk2_counter = "g2" else + g3_clk when i_clk2_counter = "g3" else + '0'; + not_clk2_tmp <= not clk2_tmp; + ena2_reg : dffp + port map ( D => clkena(2), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_clk2_tmp, + Q => ena2 ); + + clk(2) <= ena2 and clk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + ena2 and 'X'; + + clk3_tmp <= l0_clk when i_clk3_counter = "l0" else + l1_clk when i_clk3_counter = "l1" else + g0_clk when i_clk3_counter = "g0" else + g1_clk when i_clk3_counter = "g1" else + g2_clk when i_clk3_counter = "g2" else + g3_clk when i_clk3_counter = "g3" else + '0'; + not_clk3_tmp <= not clk3_tmp; + ena3_reg : dffp + port map ( D => clkena(3), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_clk3_tmp, + Q => ena3 ); + + clk(3) <= ena3 and clk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + ena3 and 'X'; + + clk4_tmp <= l0_clk when i_clk4_counter = "l0" else + l1_clk when i_clk4_counter = "l1" else + g0_clk when i_clk4_counter = "g0" else + g1_clk when i_clk4_counter = "g1" else + g2_clk when i_clk4_counter = "g2" else + g3_clk when i_clk4_counter = "g3" else + '0'; + not_clk4_tmp <= not clk4_tmp; + ena4_reg : dffp + port map ( D => clkena(4), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_clk4_tmp, + Q => ena4 ); + + clk(4) <= ena4 and clk4_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + ena4 and 'X'; + + clk5_tmp <= l0_clk when i_clk5_counter = "l0" else + l1_clk when i_clk5_counter = "l1" else + g0_clk when i_clk5_counter = "g0" else + g1_clk when i_clk5_counter = "g1" else + g2_clk when i_clk5_counter = "g2" else + g3_clk when i_clk5_counter = "g3" else + '0'; + not_clk5_tmp <= not clk5_tmp; + ena5_reg : dffp + port map ( D => clkena(5), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_clk5_tmp, + Q => ena5 ); + + clk(5) <= ena5 and clk5_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + ena5 and 'X'; + + extclk0_tmp <= e0_clk when i_extclk0_counter = "e0" else + e1_clk when i_extclk0_counter = "e1" else + e2_clk when i_extclk0_counter = "e2" else + e3_clk when i_extclk0_counter = "e3" else + g0_clk when i_extclk0_counter = "g0" else + '0'; + not_extclk0_tmp <= not extclk0_tmp; + extena0_reg : dffp + port map ( D => extclkena(0), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_extclk0_tmp, + Q => extena0 ); + + extclk(0) <= extena0 and extclk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + extena0 and 'X'; + + extclk1_tmp <= e0_clk when i_extclk1_counter = "e0" else + e1_clk when i_extclk1_counter = "e1" else + e2_clk when i_extclk1_counter = "e2" else + e3_clk when i_extclk1_counter = "e3" else + g0_clk when i_extclk1_counter = "g0" else + '0'; + not_extclk1_tmp <= not extclk1_tmp; + extena1_reg : dffp + port map ( D => extclkena(1), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_extclk1_tmp, + Q => extena1 ); + + extclk(1) <= extena1 and extclk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + extena1 and 'X'; + + extclk2_tmp <= e0_clk when i_extclk2_counter = "e0" else + e1_clk when i_extclk2_counter = "e1" else + e2_clk when i_extclk2_counter = "e2" else + e3_clk when i_extclk2_counter = "e3" else + g0_clk when i_extclk2_counter = "g0" else + '0'; + not_extclk2_tmp <= not extclk2_tmp; + extena2_reg : dffp + port map ( D => extclkena(2), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_extclk2_tmp, + Q => extena2 ); + + extclk(2) <= extena2 and extclk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + extena2 and 'X'; + + extclk3_tmp <= e0_clk when i_extclk3_counter = "e0" else + e1_clk when i_extclk3_counter = "e1" else + e2_clk when i_extclk3_counter = "e2" else + e3_clk when i_extclk3_counter = "e3" else + g0_clk when i_extclk3_counter = "g0" else + '0'; + not_extclk3_tmp <= not extclk3_tmp; + extena3_reg : dffp + port map ( D => extclkena(3), + CLRN => vcc, + PRN => vcc, + ENA => vcc, + CLK => not_extclk3_tmp, + Q => extena3 ); + + extclk(3) <= extena3 and extclk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + extena3 and 'X'; + + enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + 'X'; + enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else + 'X'; + + scandataout <= scandataout_tmp; + +end vital_pll; +-- END ARCHITECTURE VITAL_PLL + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : arm_m_cntr +-- +-- Description : Simulation model for the M counter. M is the loop +-- feedback counter of the StratixII PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY arm_m_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END arm_m_cntr; + +ARCHITECTURE behave of arm_m_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : arm_n_cntr +-- +-- Description : Simulation model for the N counter. N is the +-- input counter of the StratixII PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY arm_n_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END arm_n_cntr; + +ARCHITECTURE behave of arm_n_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + variable clk_last_valid_value : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = 'X') then + ASSERT FALSE REPORT "Invalid transition to 'X' detected on PLL input clk. This edge will be ignored." severity warning; + elsif (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + if (clk /= 'X') then + clk_last_valid_value := clk; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : arm_scale_cntr +-- +-- Description : Simulation model for the output scale-down counters. +-- This is a common model for the C0, C1, C2, C3, C4 and C5 +-- output counters of the StratixII PLL. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY arm_scale_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0; + cout : OUT std_logic + ); +END arm_scale_cntr; + +ARCHITECTURE behave of arm_scale_cntr is +begin + process (clk, reset) + variable tmp_cout : std_logic := '0'; + variable count : integer := 1; + variable output_shift_count : integer := 1; + variable first_rising_edge : boolean := false; + begin + if (reset = '1') then + count := 1; + output_shift_count := 1; + tmp_cout := '0'; + first_rising_edge := false; + elsif (clk'event) then + if (mode = " off") then + tmp_cout := '0'; + elsif (mode = "bypass") then + tmp_cout := clk; + first_rising_edge := true; + elsif (not first_rising_edge) then + if (clk = '1') then + if (output_shift_count = initial) then + tmp_cout := clk; + first_rising_edge := true; + else + output_shift_count := output_shift_count + 1; + end if; + end if; + elsif (output_shift_count < initial) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + end if; + else + count := count + 1; + if (mode = " even" and (count = (high*2) + 1)) then + tmp_cout := '0'; + elsif (mode = " odd" and (count = high*2)) then + tmp_cout := '0'; + elsif (count = (high + low)*2 + 1) then + tmp_cout := '1'; + count := 1; -- reset count + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; + +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_stratixii_pll +-- +-- Description : Simulation model for the StratixII PLL. +-- In the functional mode, it is also the model for the altpll +-- megafunction. +-- +-- Limitations : Does not support Spread Spectrum and Bandwidth. +-- +-- Outputs : Up to 6 output clocks, each defined by its own set of +-- parameters. Locked output (active high) indicates when the +-- PLL locks. clkbad, clkloss and activeclock are used for +-- clock switchover to indicate which input clock has gone +-- bad, when the clock switchover initiates and which input +-- clock is being used as the reference, respectively. +-- scandataout is the data output of the serial scan chain. +-- +--/////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE STD.TEXTIO.all; +USE work.MF_pllpack.all; +USE work.arm_m_cntr; +USE work.arm_n_cntr; +USE work.arm_scale_cntr; +USE work.dffp; +USE work.MF_pll_reg; + +ENTITY MF_stratixii_pll is + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- EGPP/FAST/AUTO + compensate_clock : string := "clk0"; + feedback_source : string := "clk0"; + qualify_conf_done : string := "off"; + + test_input_comp_delay : integer := 0; + test_feedback_comp_delay : integer := 0; + + inclk0_input_frequency : integer := 10000; + inclk1_input_frequency : integer := 10000; + + gate_lock_signal : string := "no"; + gate_lock_counter : integer := 1; + self_reset_on_gated_loss_lock : string := "off"; + valid_lock_multiplier : integer := 1; + invalid_lock_multiplier : integer := 5; + sim_gate_lock_device_behavior : string := "off"; + + switch_over_type : string := "auto"; + switch_over_on_lossclk : string := "off"; + switch_over_on_gated_lock : string := "off"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "on"; + + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + down_spread : string := "0.0"; + spread_frequency : integer := 0; + + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 1; + clk0_divide_by : integer := 1; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 1; + clk1_divide_by : integer := 1; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 1; + clk2_divide_by : integer := 1; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 1; + clk3_divide_by : integer := 1; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 1; + clk4_divide_by : integer := 1; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + + clk5_output_frequency : integer := 0; + clk5_multiply_by : integer := 1; + clk5_divide_by : integer := 1; + clk5_phase_shift : string := "0"; + clk5_duty_cycle : integer := 50; + + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + + -- ADVANCED USER PARAMETERS + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + m2 : integer := 1; + n2 : integer := 1; + ss : integer := 0; + + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + c5_high : integer := 1; + c5_low : integer := 1; + c5_initial : integer := 1; + c5_mode : string := "bypass"; + c5_ph : integer := 0; + + m_ph : integer := 0; + + clk0_counter : string := "c0"; + clk1_counter : string := "c1"; + clk2_counter : string := "c2"; + clk3_counter : string := "c3"; + clk4_counter : string := "c4"; + clk5_counter : string := "c5"; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + c5_use_casc_in : string := "off"; + + m_test_source : integer := 5; + c0_test_source : integer := 5; + c1_test_source : integer := 5; + c2_test_source : integer := 5; + c3_test_source : integer := 5; + c4_test_source : integer := 5; + c5_test_source : integer := 5; + + -- LVDS mode parameters + enable0_counter : string := "c0"; + enable1_counter : string := "c1"; + sclkout0_phase_shift : string := "0"; + sclkout1_phase_shift : string := "0"; + + charge_pump_current : integer := 52; + loop_filter_r : string := " 1.000000"; + loop_filter_c : integer := 16; + common_rx_tx : string := "off"; + use_vco_bypass : string := "false"; + use_dc_coupling : string := "false"; + + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + + -- Simulation only generics + family_name : string := "StratixII"; + + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + clk5_use_even_counter_mode : string := "off"; + + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + clk5_use_even_counter_value : string := "off"; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + scan_chain_mif_file : string := ""; + vco_post_scale : integer := 1 + + ); + + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanread : in std_logic := '0'; + scanwrite : in std_logic := '0'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + testin : in std_logic_vector(3 downto 0) := "0000"; + clk : out std_logic_vector(5 downto 0); + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + clkloss : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + testupout : out std_logic; + testdownout : out std_logic; + -- lvds specific ports + enable0 : out std_logic; + enable1 : out std_logic; + sclkout : out std_logic_vector(1 downto 0) + ); +END MF_stratixii_pll; + +ARCHITECTURE vital_pll of MF_stratixii_pll is + +TYPE int_array is ARRAY(NATURAL RANGE <>) of integer; +TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6); +TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9); +TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic; + +-- internal advanced parameter signals +signal i_vco_min : integer; +signal i_vco_max : integer; +signal i_vco_center : integer; +signal i_pfd_min : integer; +signal i_pfd_max : integer; +signal c_ph_val : int_array(0 to 5) := (OTHERS => 0); +signal c_high_val : int_array(0 to 5) := (OTHERS => 1); +signal c_low_val : int_array(0 to 5) := (OTHERS => 1); +signal c_initial_val : int_array(0 to 5) := (OTHERS => 1); +signal c_mode_val : str_array(0 to 5); + +-- old values +signal c_high_val_old : int_array(0 to 5) := (OTHERS => 1); +signal c_low_val_old : int_array(0 to 5) := (OTHERS => 1); +signal c_ph_val_old : int_array(0 to 5) := (OTHERS => 0); +signal c_mode_val_old : str_array(0 to 5); + +-- hold registers +signal c_high_val_hold : int_array(0 to 5) := (OTHERS => 1); +signal c_low_val_hold : int_array(0 to 5) := (OTHERS => 1); +signal c_ph_val_hold : int_array(0 to 5) := (OTHERS => 0); +signal c_mode_val_hold : str_array(0 to 5); + +-- temp registers +signal sig_c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0); +signal sig_c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1); +signal sig_c_hi_val_tmp : int_array(0 to 5) := (OTHERS => 1); +signal c_ph_val_orig : int_array(0 to 5) := (OTHERS => 0); + +--signal i_clk5_counter : string(1 to 2) := "c5"; +--signal i_clk4_counter : string(1 to 2) := "c4"; +--signal i_clk3_counter : string(1 to 2) := "c3"; +--signal i_clk2_counter : string(1 to 2) := "c2"; +--signal i_clk1_counter : string(1 to 2) := "c1"; +--signal i_clk0_counter : string(1 to 2) := "c0"; + +signal i_clk5_counter : integer := 5; +signal i_clk4_counter : integer := 4; +signal i_clk3_counter : integer := 3; +signal i_clk2_counter : integer := 2; +signal i_clk1_counter : integer := 1; +signal i_clk0_counter : integer := 0; +signal i_charge_pump_current : integer; +signal i_loop_filter_r : integer; + +-- end internal advanced parameter signals + +-- CONSTANTS +CONSTANT GPP_SCAN_CHAIN : integer := 174; +CONSTANT FAST_SCAN_CHAIN : integer := 75; +CONSTANT GATE_LOCK_CYCLES : integer := 7; + +CONSTANT cntrs : str_array(5 downto 0) := (" C5", " C4", " C3", " C2", " C1", " C0"); +CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2"); + +CONSTANT loop_filter_c_arr : int_array(0 to 3) := (57, 16, 36, 5); +CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (18, 13, 8, 2); +CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (6, 12, 30, 36, 52, 57, 72, 77, 92, 96, 110, 114, 127, 131, 144, 148); +CONSTANT loop_filter_r_arr : str_array1(0 to 39) := (" 1.000000", " 1.500000", " 2.000000", " 2.500000", " 3.000000", " 3.500000", " 4.000000", " 4.500000", " 5.000000", " 5.500000", " 6.000000", " 6.500000", " 7.000000", " 7.500000", " 8.000000", " 8.500000", " 9.000000", " 9.500000", "10.000000", "10.500000", "11.000000", "11.500000", "12.000000", "12.500000", "13.000000", "13.500000", "14.000000", "14.500000", "15.000000", "15.500000", "16.000000", "16.500000", "17.000000", "17.500000", "18.000000", "18.500000", "19.000000", "19.500000", "20.000000", "20.500000"); + +-- signals + +signal vcc : std_logic := '1'; + +signal fbclk : std_logic; +signal refclk : std_logic; + +signal c_clk : std_logic_array(0 to 5); +signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); +signal vco_tap : std_logic_vector(7 downto 0) := (OTHERS => '0'); +signal vco_out_last_value : std_logic_vector(7 downto 0); +signal vco_tap_last_value : std_logic_vector(7 downto 0); + +-- signals to assign values to counter params +signal m_val : int_array(0 to 1) := (OTHERS => 1); +signal n_val : int_array(0 to 1) := (OTHERS => 1); +signal m_ph_val : integer := 0; +signal m_initial_val : integer := m_initial; + +signal m_mode_val : str_array(0 to 1) := (OTHERS => " "); +signal n_mode_val : str_array(0 to 1) := (OTHERS => " "); +signal lfc_val : integer := 0; +signal cp_curr_val : integer := 0; +signal lfr_val : string(1 to 9) := " "; + +-- old values +signal m_val_old : int_array(0 to 1) := (OTHERS => 1); +signal n_val_old : int_array(0 to 1) := (OTHERS => 1); +signal m_mode_val_old : str_array(0 to 1) := (OTHERS => " "); +signal n_mode_val_old : str_array(0 to 1) := (OTHERS => " "); +signal m_ph_val_old : integer := 0; +signal lfc_old : integer := 0; +signal cp_curr_old : integer := 0; +signal lfr_old : string(1 to 9) := " "; +signal num_output_cntrs : integer := 6; + +signal scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0'); + +signal clk0_tmp : std_logic; +signal clk1_tmp : std_logic; +signal clk2_tmp : std_logic; +signal clk3_tmp : std_logic; +signal clk4_tmp : std_logic; +signal clk5_tmp : std_logic; +signal sclkout0_tmp : std_logic; +signal sclkout1_tmp : std_logic; + +signal clkin : std_logic := '0'; +signal gate_locked : std_logic := '0'; +signal lock : std_logic := '0'; +signal about_to_lock : boolean := false; +signal reconfig_err : boolean := false; + +signal inclk_c0 : std_logic; +signal inclk_c1 : std_logic; +signal inclk_c2 : std_logic; +signal inclk_c3 : std_logic; +signal inclk_c4 : std_logic; +signal inclk_c5 : std_logic; +signal inclk_m : std_logic; +signal devpor : std_logic; +signal devclrn : std_logic; + +signal inclk0_ipd : std_logic; +signal inclk1_ipd : std_logic; +signal ena_ipd : std_logic; +signal pfdena_ipd : std_logic; +signal areset_ipd : std_logic; +signal fbin_ipd : std_logic; +signal scanclk_ipd : std_logic; +signal scanread_ipd : std_logic; +signal scanwrite_ipd : std_logic; +signal scandata_ipd : std_logic; +signal clkswitch_ipd : std_logic; +-- registered signals +signal scanread_reg : std_logic := '0'; +signal scanwrite_reg : std_logic := '0'; +signal scanwrite_enabled : std_logic := '0'; +signal gated_scanclk : std_logic := '1'; + +signal inclk_c0_dly1 : std_logic := '0'; +signal inclk_c0_dly2 : std_logic := '0'; +signal inclk_c0_dly3 : std_logic := '0'; +signal inclk_c0_dly4 : std_logic := '0'; +signal inclk_c0_dly5 : std_logic := '0'; +signal inclk_c0_dly6 : std_logic := '0'; +signal inclk_c1_dly1 : std_logic := '0'; +signal inclk_c1_dly2 : std_logic := '0'; +signal inclk_c1_dly3 : std_logic := '0'; +signal inclk_c1_dly4 : std_logic := '0'; +signal inclk_c1_dly5 : std_logic := '0'; +signal inclk_c1_dly6 : std_logic := '0'; + + +signal sig_offset : time := 0 ps; +signal sig_refclk_time : time := 0 ps; +signal sig_fbclk_period : time := 0 ps; +signal sig_vco_period_was_phase_adjusted : boolean := false; +signal sig_phase_adjust_was_scheduled : boolean := false; +signal sig_stop_vco : std_logic := '0'; +signal sig_m_times_vco_period : time := 0 ps; +signal sig_new_m_times_vco_period : time := 0 ps; +signal sig_got_refclk_posedge : boolean := false; +signal sig_got_fbclk_posedge : boolean := false; +signal sig_got_second_refclk : boolean := false; + +signal m_delay : integer := 0; +signal n_delay : integer := 0; + +signal inclk1_tmp : std_logic := '0'; + +signal ext_fbk_cntr_high : integer := 0; +signal ext_fbk_cntr_low : integer := 0; +signal ext_fbk_cntr_ph : integer := 0; +signal ext_fbk_cntr_initial : integer := 1; +signal ext_fbk_cntr : string(1 to 2) := "c0"; +signal ext_fbk_cntr_mode : string(1 to 6) := "bypass"; +signal ext_fbk_cntr_index : integer := 0; + +signal enable0_tmp : std_logic := '0'; +signal enable1_tmp : std_logic := '0'; +signal reset_low : std_logic := '0'; + +signal scandataout_tmp : std_logic := '0'; +signal scandone_tmp : std_logic := '0'; + +signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; + +signal schedule_vco : std_logic := '0'; + +signal areset_ena_sig : std_logic := '0'; +signal pll_in_test_mode : boolean := false; + +signal inclk_c_from_vco : std_logic_array(0 to 5); + +signal inclk_m_from_vco : std_logic; +signal inclk_sclkout0_from_vco : std_logic; +signal inclk_sclkout1_from_vco : std_logic; + +--signal tap0_is_active : boolean := true; + signal sig_quiet_time : time := 0 ps; + signal sig_slowest_clk_old : time := 0 ps; + signal sig_slowest_clk_new : time := 0 ps; + signal sig_m_val_tmp : int_array(0 to 1) := (OTHERS => 1); + +COMPONENT arm_m_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END COMPONENT; + +COMPONENT arm_n_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END COMPONENT; + +COMPONENT arm_scale_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0 + ); +END COMPONENT; + +COMPONENT dffp + + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +COMPONENT MF_pll_reg + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +begin + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + WireDelay : block + begin + inclk0_ipd <= inclk(0); + inclk1_ipd <= inclk(1); + areset_ipd <= areset; + ena_ipd <= ena; + fbin_ipd <= fbin; + pfdena_ipd <= pfdena; + scanclk_ipd <= scanclk; + scanread_ipd <= scanread; + scandata_ipd <= scandata; + scanwrite_ipd <= scanwrite; + clkswitch_ipd <= clkswitch; + end block; + + inclk_m <= clkin when m_test_source = 0 else + clk0_tmp when operation_mode = "external_feedback" and feedback_source = "clk0" else + clk1_tmp when operation_mode = "external_feedback" and feedback_source = "clk1" else + clk2_tmp when operation_mode = "external_feedback" and feedback_source = "clk2" else + clk3_tmp when operation_mode = "external_feedback" and feedback_source = "clk3" else + clk4_tmp when operation_mode = "external_feedback" and feedback_source = "clk4" else + clk5_tmp when operation_mode = "external_feedback" and feedback_source = "clk5" else + inclk_m_from_vco; + + + ext_fbk_cntr_high <= c_high_val(ext_fbk_cntr_index); + ext_fbk_cntr_low <= c_low_val(ext_fbk_cntr_index); + ext_fbk_cntr_ph <= c_ph_val(ext_fbk_cntr_index); + ext_fbk_cntr_initial <= c_initial_val(ext_fbk_cntr_index); + ext_fbk_cntr_mode <= c_mode_val(ext_fbk_cntr_index); + + areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco; + + pll_in_test_mode <= true when m_test_source /= 5 or c0_test_source /= 5 or + c1_test_source /= 5 or c2_test_source /= 5 or + c3_test_source /= 5 or c4_test_source /= 5 or + c5_test_source /= 5 else + false; + + + m1 : arm_m_cntr + port map ( clk => inclk_m, + reset => areset_ena_sig, + cout => fbclk, + initial_value => m_initial_val, + modulus => m_val(0), + time_delay => m_delay + ); + + -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed + -- in different simulation deltas. + inclk1_tmp <= inclk1_ipd; + + process (inclk0_ipd, inclk1_tmp, clkswitch_ipd) + variable input_value : std_logic := '0'; + variable current_clock : integer := 0; + variable clk0_count, clk1_count : integer := 0; + variable clk0_is_bad, clk1_is_bad : std_logic := '0'; + variable primary_clk_is_bad : boolean := false; + variable current_clk_is_bad : boolean := false; + variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; + variable switch_over_count : integer := 0; + variable active_clock : std_logic := '0'; + variable external_switch : boolean := false; + begin + if (now = 0 ps) then + if (switch_over_type = "manual" and clkswitch_ipd = '1') then + current_clock := 1; + active_clock := '1'; + end if; + end if; + if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then + external_switch := true; + elsif (switch_over_type = "manual") then + if (clkswitch_ipd'event and clkswitch_ipd = '1') then + current_clock := 1; + active_clock := '1'; + clkin <= transport inclk1_tmp; + elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then + current_clock := 0; + active_clock := '0'; + clkin <= transport inclk0_ipd; + end if; + end if; + -- save the current inclk event value + if (inclk0_ipd'event) then + input_value := inclk0_ipd; + elsif (inclk1_tmp'event) then + input_value := inclk1_tmp; + end if; + + -- check if either input clk is bad + if (inclk0_ipd'event and inclk0_ipd = '1') then + clk0_count := clk0_count + 1; + clk0_is_bad := '0'; + clk1_count := 0; + if (clk0_count > 2) then + -- no event on other clk for 2 cycles + clk1_is_bad := '1'; + if (current_clock = 1) then + current_clk_is_bad := true; + end if; + end if; + end if; + if (inclk1_tmp'event and inclk1_tmp = '1') then + clk1_count := clk1_count + 1; + clk1_is_bad := '0'; + clk0_count := 0; + if (clk1_count > 2) then + -- no event on other clk for 2 cycles + clk0_is_bad := '1'; + if (current_clock = 0) then + current_clk_is_bad := true; + end if; + end if; + end if; + + -- check if the bad clk is the primary clock + if (clk0_is_bad = '1') then + primary_clk_is_bad := true; + else + primary_clk_is_bad := false; + end if; + + -- actual switching + if (inclk0_ipd'event and current_clock = 0) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk0_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk0_ipd; + end if; + else + clkin <= transport inclk0_ipd; + end if; + elsif (inclk1_tmp'event and current_clock = 1) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk1_tmp = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk1_tmp; + end if; + else + clkin <= transport inclk1_tmp; + end if; + else + if (input_value = '1' and switch_over_on_lossclk = "on" and enable_switch_over_counter = "on" and primary_clk_is_bad) then + switch_over_count := switch_over_count + 1; + end if; + if (input_value = '0') then + if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then + got_curr_clk_falling_edge_after_clkswitch := false; + if (current_clock = 0) then + current_clock := 1; + else + current_clock := 0; + end if; + active_clock := not active_clock; + switch_over_count := 0; + external_switch := false; + current_clk_is_bad := false; + end if; + + end if; + end if; + + -- schedule outputs + clkbad(0) <= clk0_is_bad; + clkbad(1) <= clk1_is_bad; + if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then + if (primary_clk_is_bad) then + -- assert clkloss + clkloss <= '1'; + else + clkloss <= '0'; + end if; + else + clkloss <= clkswitch_ipd; + end if; + activeclock <= active_clock; + + end process; + + process (inclk_sclkout0_from_vco) + begin + sclkout0_tmp <= inclk_sclkout0_from_vco; + end process; + + process (inclk_sclkout1_from_vco) + begin + sclkout1_tmp <= inclk_sclkout1_from_vco; + end process; + + n1 : arm_n_cntr + port map ( + clk => clkin, + reset => areset_ipd, + cout => refclk, + initial_value => n_val(0), + modulus => n_val(0)); + + + inclk_c0 <= clkin when c0_test_source = 0 else + refclk when c0_test_source = 1 else + inclk_c_from_vco(0); + c0 : arm_scale_cntr + port map ( + clk => inclk_c0, + reset => areset_ena_sig, + cout => c_clk(0), + initial => c_initial_val(0), + high => c_high_val(0), + low => c_low_val(0), + mode => c_mode_val(0), + ph_tap => c_ph_val(0)); + + + inclk_c1 <= clkin when c1_test_source = 0 else + fbclk when c1_test_source = 2 else + c_clk(0) when c1_use_casc_in = "on" else + inclk_c_from_vco(1); + c1 : arm_scale_cntr + port map ( + clk => inclk_c1, + reset => areset_ena_sig, + cout => c_clk(1), + initial => c_initial_val(1), + high => c_high_val(1), + low => c_low_val(1), + mode => c_mode_val(1), + ph_tap => c_ph_val(1)); + + + inclk_c2 <= clkin when c2_test_source = 0 else + c_clk(1) when c2_use_casc_in = "on" else + inclk_c_from_vco(2); + c2 : arm_scale_cntr + port map ( + clk => inclk_c2, + reset => areset_ena_sig, + cout => c_clk(2), + initial => c_initial_val(2), + high => c_high_val(2), + low => c_low_val(2), + mode => c_mode_val(2), + ph_tap => c_ph_val(2)); + + + inclk_c3 <= clkin when c3_test_source = 0 else + c_clk(2) when c3_use_casc_in = "on" else + inclk_c_from_vco(3); + c3 : arm_scale_cntr + port map ( + clk => inclk_c3, + reset => areset_ena_sig, + cout => c_clk(3), + initial => c_initial_val(3), + high => c_high_val(3), + low => c_low_val(3), + mode => c_mode_val(3), + ph_tap => c_ph_val(3)); + + inclk_c4 <= '0' when (pll_type = "fast") else + clkin when (c4_test_source = 0) else + c_clk(3) when (c4_use_casc_in = "on") else + inclk_c_from_vco(4); + c4 : arm_scale_cntr + port map ( + clk => inclk_c4, + reset => areset_ena_sig, + cout => c_clk(4), + initial => c_initial_val(4), + high => c_high_val(4), + low => c_low_val(4), + mode => c_mode_val(4), + ph_tap => c_ph_val(4)); + + inclk_c5 <= '0' when (pll_type = "fast") else + clkin when c5_test_source = 0 else + c_clk(4) when c5_use_casc_in = "on" else + inclk_c_from_vco(5); + c5 : arm_scale_cntr + port map ( + clk => inclk_c5, + reset => areset_ena_sig, + cout => c_clk(5), + initial => c_initial_val(5), + high => c_high_val(5), + low => c_low_val(5), + mode => c_mode_val(5), + ph_tap => c_ph_val(5)); + + inclk_c0_dly1 <= inclk_c0 when (pll_type = "fast" or pll_type = "lvds") + else '0'; + inclk_c0_dly2 <= inclk_c0_dly1; + inclk_c0_dly3 <= inclk_c0_dly2; + inclk_c0_dly4 <= inclk_c0_dly3; + inclk_c0_dly5 <= inclk_c0_dly4; + inclk_c0_dly6 <= inclk_c0_dly5; + + inclk_c1_dly1 <= inclk_c1 when (pll_type = "fast" or pll_type = "lvds") + else '0'; + inclk_c1_dly2 <= inclk_c1_dly1; + inclk_c1_dly3 <= inclk_c1_dly2; + inclk_c1_dly4 <= inclk_c1_dly3; + inclk_c1_dly5 <= inclk_c1_dly4; + inclk_c1_dly6 <= inclk_c1_dly5; + + process(inclk_c0_dly6, inclk_c1_dly6, areset_ipd, ena_ipd, sig_stop_vco) + variable c0_got_first_rising_edge : boolean := false; + variable c0_count : integer := 2; + variable c0_initial_count : integer := 1; + variable c0_tmp, c1_tmp : std_logic := '0'; + variable c1_got_first_rising_edge : boolean := false; + variable c1_count : integer := 2; + variable c1_initial_count : integer := 1; + begin + if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then + c0_count := 2; + c1_count := 2; + c0_initial_count := 1; + c1_initial_count := 1; + c0_got_first_rising_edge := false; + c1_got_first_rising_edge := false; + else + if (not c0_got_first_rising_edge) then + if (inclk_c0_dly6'event and inclk_c0_dly6 = '1') then + if (c0_initial_count = c_initial_val(0)) then + c0_got_first_rising_edge := true; + else + c0_initial_count := c0_initial_count + 1; + end if; + end if; + elsif (inclk_c0_dly6'event) then + c0_count := c0_count + 1; + if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then + c0_count := 1; + end if; + end if; + if (inclk_c0_dly6'event and inclk_c0_dly6 = '0') then + if (c0_count = 1) then + c0_tmp := '1'; + c0_got_first_rising_edge := false; + else + c0_tmp := '0'; + end if; + end if; + + if (not c1_got_first_rising_edge) then + if (inclk_c1_dly6'event and inclk_c1_dly6 = '1') then + if (c1_initial_count = c_initial_val(1)) then + c1_got_first_rising_edge := true; + else + c1_initial_count := c1_initial_count + 1; + end if; + end if; + elsif (inclk_c1_dly6'event) then + c1_count := c1_count + 1; + if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then + c1_count := 1; + end if; + end if; + if (inclk_c1_dly6'event and inclk_c1_dly6 = '0') then + if (c1_count = 1) then + c1_tmp := '1'; + c1_got_first_rising_edge := false; + else + c1_tmp := '0'; + end if; + end if; + end if; + + if (enable0_counter = "c0") then + enable0_tmp <= c0_tmp; + elsif (enable0_counter = "c1") then + enable0_tmp <= c1_tmp; + else + enable0_tmp <= '0'; + end if; + + if (enable1_counter = "c0") then + enable1_tmp <= c0_tmp; + elsif (enable1_counter = "c1") then + enable1_tmp <= c1_tmp; + else + enable1_tmp <= '0'; + end if; + + end process; + + glocked_cntr : process(clkin, ena_ipd, areset_ipd) + variable count : integer := 0; + variable output : std_logic := '0'; + begin + if (areset_ipd = '1') then + count := 0; + output := '0'; + elsif (clkin'event and clkin = '1') then + if (ena_ipd = '1') then + count := count + 1; + if (sim_gate_lock_device_behavior = "on") then + if (count = gate_lock_counter) then + output := '1'; + end if; + elsif (count = GATE_LOCK_CYCLES) then + output := '1'; + end if; + end if; + end if; + gate_locked <= output; + end process; + + locked <= gate_locked and lock when gate_lock_signal = "yes" else + lock; + + + process (scandone_tmp) + variable buf : line; + begin + if (scandone_tmp'event and scandone_tmp = '1') then + if (reconfig_err = false) then + ASSERT false REPORT family_name & " PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note; + write (buf, string'(" N modulus = ")); + write (buf, n_val(0)); + write (buf, string'(" ( ")); + write (buf, n_val_old(0)); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M modulus = ")); + write (buf, m_val(0)); + write (buf, string'(" ( ")); + write (buf, m_val_old(0)); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M ph_tap = ")); + write (buf, m_ph_val); + write (buf, string'(" ( ")); + write (buf, m_ph_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + if (ss > 0) then + write (buf, string'(" M2 modulus = ")); + write (buf, m_val(1)); + write (buf, string'(" ( ")); + write (buf, m_val_old(1)); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" N2 modulus = ")); + write (buf, n_val(1)); + write (buf, string'(" ( ")); + write (buf, n_val_old(1)); + write (buf, string'(" )")); + writeline (output, buf); + end if; + + for i in 0 to (num_output_cntrs-1) loop + write (buf, cntrs(i)); + write (buf, string'(" : high = ")); + write (buf, c_high_val(i)); + write (buf, string'(" (")); + write (buf, c_high_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , low = ")); + write (buf, sig_c_low_val_tmp(i)); + write (buf, string'(" (")); + write (buf, c_low_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , mode = ")); + write (buf, c_mode_val(i)); + write (buf, string'(" (")); + write (buf, c_mode_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , phase tap = ")); + write (buf, c_ph_val(i)); + write (buf, string'(" (")); + write (buf, c_ph_val_old(i)); + write (buf, string'(") ")); + writeline(output, buf); + end loop; + + write (buf, string'(" Charge Pump Current (uA) = ")); + write (buf, cp_curr_val); + write (buf, string'(" ( ")); + write (buf, cp_curr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (pF) = ")); + write (buf, lfc_val); + write (buf, string'(" ( ")); + write (buf, lfc_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (Kohm) = ")); + write (buf, lfr_val); + write (buf, string'(" ( ")); + write (buf, lfr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning; + end if; + end if; + end process; + + process (scanwrite_enabled, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), vco_tap, fbclk, scanclk_ipd, gated_scanclk) + variable init : boolean := true; + variable low, high : std_logic_vector(7 downto 0); + variable low_fast, high_fast : std_logic_vector(3 downto 0); + variable mode : string(1 to 6) := "bypass"; + variable is_error : boolean := false; + variable m_tmp, n_tmp : std_logic_vector(8 downto 0); + variable n_fast : std_logic_vector(1 downto 0); + variable c_high_val_tmp : int_array(0 to 5) := (OTHERS => 1); + variable c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1); + variable c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0); + variable c_mode_val_tmp : str_array(0 to 5); + variable m_ph_val_tmp : integer := 0; + variable m_val_tmp : int_array(0 to 1) := (OTHERS => 1); + variable c0_rising_edge_transfer_done : boolean := false; + variable c1_rising_edge_transfer_done : boolean := false; + variable c2_rising_edge_transfer_done : boolean := false; + variable c3_rising_edge_transfer_done : boolean := false; + variable c4_rising_edge_transfer_done : boolean := false; + variable c5_rising_edge_transfer_done : boolean := false; + + -- variables for scaling of multiply_by and divide_by values + variable i_clk0_mult_by : integer := 1; + variable i_clk0_div_by : integer := 1; + variable i_clk1_mult_by : integer := 1; + variable i_clk1_div_by : integer := 1; + variable i_clk2_mult_by : integer := 1; + variable i_clk2_div_by : integer := 1; + variable i_clk3_mult_by : integer := 1; + variable i_clk3_div_by : integer := 1; + variable i_clk4_mult_by : integer := 1; + variable i_clk4_div_by : integer := 1; + variable i_clk5_mult_by : integer := 1; + variable i_clk5_div_by : integer := 1; + variable max_d_value : integer := 1; + variable new_multiplier : integer := 1; + + -- internal variables for storing the phase shift number.(used in lvds mode only) + variable i_clk0_phase_shift : integer := 1; + variable i_clk1_phase_shift : integer := 1; + variable i_clk2_phase_shift : integer := 1; + + -- user to advanced variables + + variable max_neg_abs : integer := 0; + variable i_m_initial : integer; + variable i_m : integer := 1; + variable i_n : integer := 1; + variable i_m2 : integer; + variable i_n2 : integer; + variable i_ss : integer; + variable i_c_high : int_array(0 to 5); + variable i_c_low : int_array(0 to 5); + variable i_c_initial : int_array(0 to 5); + variable i_c_ph : int_array(0 to 5); + variable i_c_mode : str_array(0 to 5); + variable i_m_ph : integer; + variable output_count : integer; + variable new_divisor : integer; + + variable clk0_cntr : string(1 to 2) := "c0"; + variable clk1_cntr : string(1 to 2) := "c1"; + variable clk2_cntr : string(1 to 2) := "c2"; + variable clk3_cntr : string(1 to 2) := "c3"; + variable clk4_cntr : string(1 to 2) := "c4"; + variable clk5_cntr : string(1 to 2) := "c5"; + + variable fbk_cntr : string(1 to 2); + variable fbk_cntr_index : integer; + variable start_bit : integer; + variable quiet_time : time := 0 ps; + variable slowest_clk_old : time := 0 ps; + variable slowest_clk_new : time := 0 ps; + variable tmp_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0'); + variable m_lo, m_hi : std_logic_vector(4 downto 0); + + variable j : integer := 0; + variable scanread_active_edge : time := 0 ps; + variable got_first_scanclk : boolean := false; + variable got_first_gated_scanclk : boolean := false; + variable scanclk_last_rising_edge : time := 0 ps; + variable scanclk_period : time := 0 ps; + variable current_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0'); + variable index : integer := 0; + variable scan_chain_length : integer := GPP_SCAN_CHAIN; + variable tmp_rem : integer := 0; + variable scanclk_cycles : integer := 0; + variable lfc_tmp : std_logic_vector(1 downto 0); + variable lfr_tmp : std_logic_vector(5 downto 0); + variable lfr_int : integer := 0; + + function slowest_clk ( + C0 : integer; C0_mode : string(1 to 6); + C1 : integer; C1_mode : string(1 to 6); + C2 : integer; C2_mode : string(1 to 6); + C3 : integer; C3_mode : string(1 to 6); + C4 : integer; C4_mode : string(1 to 6); + C5 : integer; C5_mode : string(1 to 6); + refclk : time; m_mod : integer) return time is + variable max_modulus : integer := 1; + variable q_period : time := 0 ps; + variable refclk_int : integer := 0; + begin + if (C0_mode /= "bypass" and C0_mode /= " off") then + max_modulus := C0; + end if; + if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then + max_modulus := C1; + end if; + if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then + max_modulus := C2; + end if; + if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then + max_modulus := C3; + end if; + if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then + max_modulus := C4; + end if; + if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then + max_modulus := C5; + end if; + + refclk_int := refclk / 1 ps; + if (m_mod /= 0) then + if (refclk_int > (refclk_int * max_modulus / m_mod)) then + q_period := refclk_int * 1 ps; + else + q_period := (refclk_int * max_modulus / m_mod) * 1 ps; + end if; + end if; + return (2*q_period); + end slowest_clk; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + + function extract_cntr_index (arg:string) return integer is + variable index : integer := 0; + begin + if (arg(2) = '0') then + index := 0; + elsif (arg(2) = '1') then + index := 1; + elsif (arg(2) = '2') then + index := 2; + elsif (arg(2) = '3') then + index := 3; + elsif (arg(2) = '4') then + index := 4; + else index := 5; + end if; + + return index; + end extract_cntr_index; + + begin + if (init) then + if (m = 0) then + clk5_cntr := "c5"; + clk4_cntr := "c4"; + clk3_cntr := "c3"; + clk2_cntr := "c2"; + clk1_cntr := "c1"; + clk0_cntr := "c0"; + else + clk5_cntr := clk5_counter; + clk4_cntr := clk4_counter; + clk3_cntr := clk3_counter; + clk2_cntr := clk2_counter; + clk1_cntr := clk1_counter; + clk0_cntr := clk0_counter; + end if; + + if (operation_mode = "external_feedback") then + if (feedback_source = "clk0") then + fbk_cntr := clk0_cntr; + elsif (feedback_source = "clk1") then + fbk_cntr := clk1_cntr; + elsif (feedback_source = "clk2") then + fbk_cntr := clk2_cntr; + elsif (feedback_source = "clk3") then + fbk_cntr := clk3_cntr; + elsif (feedback_source = "clk4") then + fbk_cntr := clk4_cntr; + elsif (feedback_source = "clk5") then + fbk_cntr := clk5_cntr; + else + fbk_cntr := "c0"; + end if; + + if (fbk_cntr = "c0") then + fbk_cntr_index := 0; + elsif (fbk_cntr = "c1") then + fbk_cntr_index := 1; + elsif (fbk_cntr = "c2") then + fbk_cntr_index := 2; + elsif (fbk_cntr = "c3") then + fbk_cntr_index := 3; + elsif (fbk_cntr = "c4") then + fbk_cntr_index := 4; + elsif (fbk_cntr = "c5") then + fbk_cntr_index := 5; + end if; + + ext_fbk_cntr <= fbk_cntr; + ext_fbk_cntr_index <= fbk_cntr_index; + end if; + i_clk0_counter <= extract_cntr_index(clk0_cntr); + i_clk1_counter <= extract_cntr_index(clk1_cntr); + i_clk2_counter <= extract_cntr_index(clk2_cntr); + i_clk3_counter <= extract_cntr_index(clk3_cntr); + i_clk4_counter <= extract_cntr_index(clk4_cntr); + i_clk5_counter <= extract_cntr_index(clk5_cntr); + + + if (m = 0) then -- convert user parameters to advanced + -- set the limit of the divide_by value that can be returned by + -- the following function. + max_d_value := 500; + + -- scale down the multiply_by and divide_by values provided by the design + -- before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by, + max_d_value, i_clk5_mult_by, i_clk5_div_by); + + if (((pll_type = "fast") or (pll_type = "lvds")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then + i_n := vco_divide_by; + i_m := vco_multiply_by; + else + i_n := 1; + i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, i_clk5_mult_by, + 1, 1, 1, 1, inclk0_input_frequency); + end if; + + if (pll_type = "flvds") then + -- Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier := clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; + i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; + i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; + else + i_clk0_phase_shift := str2int(clk0_phase_shift); + i_clk1_phase_shift := str2int(clk1_phase_shift); + i_clk2_phase_shift := str2int(clk2_phase_shift); + end if; + + max_neg_abs := maxnegabs(i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + str2int(clk5_phase_shift), + 0, 0, 0, 0); + i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); + + i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); + + i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n)); + + -- in external feedback mode, need to adjust M value to take + -- into consideration the external feedback counter value + if(operation_mode = "external_feedback") then + -- if there is a negative phase shift, m_initial can + -- only be 1 + if (max_neg_abs > 0) then + i_m_initial := 1; + end if; + + -- calculate the feedback counter multiplier + if (i_c_mode(fbk_cntr_index) = "bypass") then + output_count := 1; + else + output_count := i_c_high(fbk_cntr_index) + i_c_low(fbk_cntr_index); + end if; + + new_divisor := gcd(i_m, output_count); + i_m := i_m / new_divisor; + i_n := output_count / new_divisor; + end if; + + else -- m /= 0 + + i_n := n; + i_m := m; + i_m_initial := m_initial; + i_m_ph := m_ph; + i_c_ph(0) := c0_ph; + i_c_ph(1) := c1_ph; + i_c_ph(2) := c2_ph; + i_c_ph(3) := c3_ph; + i_c_ph(4) := c4_ph; + i_c_ph(5) := c5_ph; + i_c_high(0) := c0_high; + i_c_high(1) := c1_high; + i_c_high(2) := c2_high; + i_c_high(3) := c3_high; + i_c_high(4) := c4_high; + i_c_high(5) := c5_high; + i_c_low(0) := c0_low; + i_c_low(1) := c1_low; + i_c_low(2) := c2_low; + i_c_low(3) := c3_low; + i_c_low(4) := c4_low; + i_c_low(5) := c5_low; + i_c_initial(0) := c0_initial; + i_c_initial(1) := c1_initial; + i_c_initial(2) := c2_initial; + i_c_initial(3) := c3_initial; + i_c_initial(4) := c4_initial; + i_c_initial(5) := c5_initial; + i_c_mode(0) := translate_string(c0_mode); + i_c_mode(1) := translate_string(c1_mode); + i_c_mode(2) := translate_string(c2_mode); + i_c_mode(3) := translate_string(c3_mode); + i_c_mode(4) := translate_string(c4_mode); + i_c_mode(5) := translate_string(c5_mode); + + end if; -- user to advanced conversion. + + m_initial_val <= i_m_initial; + n_val(0) <= i_n; + m_val(0) <= i_m; + m_val(1) <= m2; + n_val(1) <= n2; + + if (i_m = 1) then + m_mode_val(0) <= "bypass"; + else + m_mode_val(0) <= " "; + end if; + if (m2 = 1) then + m_mode_val(1) <= "bypass"; + end if; + if (i_n = 1) then + n_mode_val(0) <= "bypass"; + end if; + if (n2 = 1) then + n_mode_val(1) <= "bypass"; + end if; + + m_ph_val <= i_m_ph; + m_ph_val_tmp := i_m_ph; + m_val_tmp := m_val; + + for i in 0 to 5 loop + if (i_c_mode(i) = "bypass") then + if (pll_type = "fast" or pll_type = "lvds") then + i_c_high(i) := 16; + i_c_low(i) := 16; + else + i_c_high(i) := 256; + i_c_low(i) := 256; + end if; + end if; + c_ph_val(i) <= i_c_ph(i); + c_initial_val(i) <= i_c_initial(i); + c_high_val(i) <= i_c_high(i); + c_low_val(i) <= i_c_low(i); + c_mode_val(i) <= i_c_mode(i); + c_high_val_tmp(i) := i_c_high(i); + c_low_val_tmp(i) := i_c_low(i); + c_mode_val_tmp(i) := i_c_mode(i); + c_ph_val_tmp(i) := i_c_ph(i); + c_ph_val_orig(i) <= i_c_ph(i); + c_high_val_hold(i) <= i_c_high(i); + c_low_val_hold(i) <= i_c_low(i); + c_mode_val_hold(i) <= i_c_mode(i); + end loop; + + lfc_val <= loop_filter_c; + lfr_val <= loop_filter_r; + cp_curr_val <= charge_pump_current; + + if (pll_type = "fast") then + scan_chain_length := FAST_SCAN_CHAIN; + end if; + -- initialize the scan_chain contents + -- CP/LF bits + scan_data(11 downto 0) <= "000000000000"; + for i in 0 to 3 loop + if (pll_type = "fast" or pll_type = "lvds") then + if (fpll_loop_filter_c_arr(i) = loop_filter_c) then + scan_data(11 downto 10) <= int2bin(i, 2); + end if; + else + if (loop_filter_c_arr(i) = loop_filter_c) then + scan_data(11 downto 10) <= int2bin(i, 2); + end if; + end if; + end loop; + for i in 0 to 15 loop + if (charge_pump_curr_arr(i) = charge_pump_current) then + scan_data(3 downto 0) <= int2bin(i, 4); + end if; + end loop; + for i in 0 to 39 loop + if (loop_filter_r_arr(i) = loop_filter_r) then + if (i >= 16 and i <= 23) then + scan_data(9 downto 4) <= int2bin((i+8), 6); + elsif (i >= 24 and i <= 31) then + scan_data(9 downto 4) <= int2bin((i+16), 6); + elsif (i >= 32) then + scan_data(9 downto 4) <= int2bin((i+24), 6); + else + scan_data(9 downto 4) <= int2bin(i, 6); + end if; + end if; + end loop; + + if (pll_type = "fast" or pll_type = "lvds") then + scan_data(21 downto 12) <= "0000000000"; -- M, C3-C0 ph + -- C0-C3 high + scan_data(25 downto 22) <= int2bin(i_c_high(0), 4); + scan_data(35 downto 32) <= int2bin(i_c_high(1), 4); + scan_data(45 downto 42) <= int2bin(i_c_high(2), 4); + scan_data(55 downto 52) <= int2bin(i_c_high(3), 4); + -- C0-C3 low + scan_data(30 downto 27) <= int2bin(i_c_low(0), 4); + scan_data(40 downto 37) <= int2bin(i_c_low(1), 4); + scan_data(50 downto 47) <= int2bin(i_c_low(2), 4); + scan_data(60 downto 57) <= int2bin(i_c_low(3), 4); + -- C0-C3 mode + for i in 0 to 3 loop + if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then + scan_data(26 + (10*i)) <= '1'; + if (i_c_mode(i) = " off") then + scan_data(31 + (10*i)) <= '1'; + else + scan_data(31 + (10*i)) <= '0'; + end if; + else + scan_data(26 + (10*i)) <= '0'; + if (i_c_mode(i) = " odd") then + scan_data(31 + (10*i)) <= '1'; + else + scan_data(31 + (10*i)) <= '0'; + end if; + end if; + end loop; + -- M + if (i_m = 1) then + scan_data(66) <= '1'; + scan_data(71) <= '0'; + scan_data(65 downto 62) <= "0000"; + scan_data(70 downto 67) <= "0000"; + else + scan_data(66) <= '0'; -- set BYPASS bit to 0 + scan_data(70 downto 67) <= int2bin(i_m/2, 4); -- set M low + if (i_m rem 2 = 0) then + -- M is an even no. : set M high = low, + -- set odd/even bit to 0 + scan_data(65 downto 62) <= int2bin(i_m/2, 4); + scan_data(71) <= '0'; + else -- M is odd : M high = low + 1 + scan_data(65 downto 62) <= int2bin((i_m/2) + 1, 4); + scan_data(71) <= '1'; + end if; + end if; + -- N + scan_data(73 downto 72) <= int2bin(i_n, 2); + if (i_n = 1) then + scan_data(74) <= '1'; + scan_data(73 downto 72) <= "00"; + end if; + else -- PLL type is auto or enhanced + scan_data(25 downto 12) <= "00000000000000"; -- M, C5-C0 ph + -- C0-C5 high + scan_data(123 downto 116) <= int2bin(i_c_high(0), 8); + scan_data(105 downto 98) <= int2bin(i_c_high(1), 8); + scan_data(87 downto 80) <= int2bin(i_c_high(2), 8); + scan_data(69 downto 62) <= int2bin(i_c_high(3), 8); + scan_data(51 downto 44) <= int2bin(i_c_high(4), 8); + scan_data(33 downto 26) <= int2bin(i_c_high(5), 8); + -- C0-C5 low + scan_data(132 downto 125) <= int2bin(i_c_low(0), 8); + scan_data(114 downto 107) <= int2bin(i_c_low(1), 8); + scan_data(96 downto 89) <= int2bin(i_c_low(2), 8); + scan_data(78 downto 71) <= int2bin(i_c_low(3), 8); + scan_data(60 downto 53) <= int2bin(i_c_low(4), 8); + scan_data(42 downto 35) <= int2bin(i_c_low(5), 8); + -- C0-C5 mode + for i in 0 to 5 loop + if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then + scan_data(124 - (18*i)) <= '1'; + if (i_c_mode(i) = " off") then + scan_data(133 - (18*i)) <= '1'; + else + scan_data(133 - (18*i)) <= '0'; + end if; + else + scan_data(124 - (18*i)) <= '0'; + if (i_c_mode(i) = " odd") then + scan_data(133 - (18*i)) <= '1'; + else + scan_data(133 - (18*i)) <= '0'; + end if; + end if; + end loop; + + -- M/M2 + scan_data(142 downto 134) <= int2bin(i_m, 9); + scan_data(143) <= '0'; + scan_data(152 downto 144) <= int2bin(m2, 9); + scan_data(153) <= '0'; + if (i_m = 1) then + scan_data(143) <= '1'; + scan_data(142 downto 134) <= "000000000"; + end if; + if (m2 = 1) then + scan_data(153) <= '1'; + scan_data(152 downto 144) <= "000000000"; + end if; + + -- N/N2 + scan_data(162 downto 154) <= int2bin(i_n, 9); + scan_data(172 downto 164) <= int2bin(n2, 9); + if (i_n = 1) then + scan_data(163) <= '1'; + scan_data(162 downto 154) <= "000000000"; + end if; + if (n2 = 1) then + scan_data(173) <= '1'; + scan_data(172 downto 164) <= "000000000"; + end if; + + end if; + if (pll_type = "fast" or pll_type = "lvds") then + num_output_cntrs <= 4; + else + num_output_cntrs <= 6; + end if; + + init := false; + elsif (scanwrite_enabled'event and scanwrite_enabled = '0') then + -- falling edge : deassert scandone + scandone_tmp <= transport '0' after (1.5 * scanclk_period); + c0_rising_edge_transfer_done := false; + c1_rising_edge_transfer_done := false; + c2_rising_edge_transfer_done := false; + c3_rising_edge_transfer_done := false; + c4_rising_edge_transfer_done := false; + c5_rising_edge_transfer_done := false; + elsif (scanwrite_enabled'event and scanwrite_enabled = '1') then + ASSERT false REPORT "PLL Reprogramming Initiated" severity note; + + reconfig_err <= false; + + -- make temporary copy of scan_data for processing + tmp_scan_data := scan_data; + + -- save old values + lfc_old <= lfc_val; + lfr_old <= lfr_val; + cp_curr_old <= cp_curr_val; + + -- CP + -- Bits 0-3 : all values are legal + cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(scan_data(3 downto 0))); + + -- LF Resistance : bits 4-9 + -- values from 010000 - 010111, 100000 - 100111, + -- 110000 - 110111 are illegal + lfr_tmp := tmp_scan_data(9 downto 4); + lfr_int := alt_conv_integer(lfr_tmp); + if (((lfr_int >= 16) and (lfr_int <= 23)) or + ((lfr_int >= 32) and (lfr_int <= 39)) or + ((lfr_int >= 48) and (lfr_int <= 55))) then + reconfig_err <= true; + ASSERT false REPORT "Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000-001111, 011000-011111, 101000-101111 and 111000-111111. Reconfiguration may not work." severity warning; + else + if (lfr_int >= 56) then + lfr_int := lfr_int - 24; + elsif ((lfr_int >= 40) and (lfr_int <= 47)) then + lfr_int := lfr_int - 16; + elsif ((lfr_int >= 24) and (lfr_int <= 31)) then + lfr_int := lfr_int - 8; + end if; + lfr_val <= loop_filter_r_arr(lfr_int); + end if; + + -- LF Capacitance : bits 10,11 : all values are legal + lfc_tmp := scan_data(11 downto 10); + if (pll_type = "fast" or pll_type = "lvds") then + lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(lfc_tmp)); + else + lfc_val <= loop_filter_c_arr(alt_conv_integer(lfc_tmp)); + end if; + + -- cntrs c0-c5 + -- save old values for display info. + m_val_old <= m_val; + n_val_old <= n_val; + m_mode_val_old <= m_mode_val; + n_mode_val_old <= n_mode_val; + m_ph_val_old <= m_ph_val; + c_high_val_old <= c_high_val; + c_low_val_old <= c_low_val; + c_ph_val_old <= c_ph_val; + c_mode_val_old <= c_mode_val; + + -- first the M counter phase : bit order same for fast and GPP + if (scan_data(12) = '0') then + -- do nothing + elsif (scan_data(12) = '1' and scan_data(13) = '1') then + m_ph_val_tmp := m_ph_val_tmp + 1; + if (m_ph_val_tmp > 7) then + m_ph_val_tmp := 0; + end if; + elsif (scan_data(12) = '1' and scan_data(13) = '0') then + m_ph_val_tmp := m_ph_val_tmp - 1; + if (m_ph_val_tmp < 0) then + m_ph_val_tmp := 7; + end if; + else + reconfig_err <= true; + ASSERT false REPORT "Illegal values for M counter phase tap. Reconfiguration may not work." severity warning; + end if; + + -- read the fast PLL bits + if (pll_type = "fast" or pll_type = "lvds") then + -- C3-C0 phase bits + for i in 3 downto 0 loop + start_bit := 14 + ((3-i)*2); + if (tmp_scan_data(start_bit) = '0') then + -- do nothing + elsif (tmp_scan_data(start_bit) = '1') then + if (tmp_scan_data(start_bit + 1) = '1') then + c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1; + if (c_ph_val_tmp(i) > 7) then + c_ph_val_tmp(i) := 0; + end if; + elsif (tmp_scan_data(start_bit + 1) = '0') then + c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1; + if (c_ph_val_tmp(i) < 0) then + c_ph_val_tmp(i) := 7; + end if; + end if; + end if; + end loop; + -- C0-C3 counter moduli + for i in 0 to 3 loop + start_bit := 22 + (i*10); + if (tmp_scan_data(start_bit + 4) = '1') then + c_mode_val_tmp(i) := "bypass"; + if (tmp_scan_data(start_bit + 9) = '1') then + c_mode_val_tmp(i) := " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (tmp_scan_data(start_bit + 9) = '1') then + c_mode_val_tmp(i) := " odd"; + else + c_mode_val_tmp(i) := " even"; + end if; + high_fast := tmp_scan_data(start_bit+3 downto start_bit); + low_fast := tmp_scan_data(start_bit+8 downto start_bit+5); + if (tmp_scan_data(start_bit+3 downto start_bit) = "0000") then + c_high_val_tmp(i) := 16; + else + c_high_val_tmp(i) := alt_conv_integer(high_fast); + end if; + if (tmp_scan_data(start_bit+8 downto start_bit+5) = "0000") then + c_low_val_tmp(i) := 16; + else + c_low_val_tmp(i) := alt_conv_integer(low_fast); + end if; + end loop; + sig_c_ph_val_tmp <= c_ph_val_tmp; + sig_c_low_val_tmp <= c_low_val_tmp; + sig_c_hi_val_tmp <= c_high_val_tmp; + -- M + -- some temporary storage + if (tmp_scan_data(65 downto 62) = "0000") then + m_hi := "10000"; + else + m_hi := "0" & tmp_scan_data(65 downto 62); + end if; + if (tmp_scan_data(70 downto 67) = "0000") then + m_lo := "10000"; + else + m_lo := "0" & tmp_scan_data(70 downto 67); + end if; + m_val_tmp(0) := alt_conv_integer(m_hi) + alt_conv_integer(m_lo); + if (tmp_scan_data(66) = '1') then + if (tmp_scan_data(71) = '1') then + -- this will turn off the M counter : error + reconfig_err <= true; + is_error := true; + ASSERT false REPORT "The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work." severity warning; + else -- M counter is being bypassed + if (m_mode_val(0) /= "bypass") then + -- mode is switched : give warning + ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + m_val_tmp(0) := 1; + m_mode_val(0) <= "bypass"; + end if; + else + if (m_mode_val(0) = "bypass") then + -- mode is switched : give warning + ASSERT false REPORT "M counter switched BYPASS mode to enabled. PLL may lose lock." severity warning; + end if; + m_mode_val(0) <= " "; + if (tmp_scan_data(71) = '1') then + -- odd : check for duty cycle, if not 50% -- error + if (alt_conv_integer(m_hi) - alt_conv_integer(m_lo) /= 1) then + reconfig_err <= true; + ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning; + end if; + else -- even + if (alt_conv_integer(m_hi) /= alt_conv_integer(m_lo)) then + reconfig_err <= true; + ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning; + end if; + end if; + end if; + + -- N + is_error := false; + n_fast := tmp_scan_data(73 downto 72); + n_val(0) <= alt_conv_integer(n_fast); + if (tmp_scan_data(74) /= '1') then + if (alt_conv_integer(n_fast) = 1) then + is_error := true; + reconfig_err <= true; + -- cntr value is illegal : give warning + ASSERT false REPORT "Illegal 1 value for N counter. Instead the counter should be BYPASSED. Reconfiguration may not work." severity warning; + elsif (alt_conv_integer(n_fast) = 0) then + n_val(0) <= 4; + ASSERT FALSE REPORT "N Modulus = " &int2str(4)& " " severity note; + end if; + if (not is_error) then + if (n_mode_val(0) = "bypass") then + ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_fast))& "). PLL may lose lock." severity warning; + else + ASSERT FALSE REPORT "N modulus = " &int2str(alt_conv_integer(n_fast))& " "severity note; + end if; + n_mode_val(0) <= " "; + end if; + elsif (tmp_scan_data(74) = '1') then + if (tmp_scan_data(72) /= '0') then + is_error := true; + reconfig_err <= true; + ASSERT false report "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning; + else + if (n_mode_val(0) /= "bypass") then + ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + n_val(0) <= 1; + n_mode_val(0) <= "bypass"; + end if; + end if; + else -- GENERAL PURPOSE PLL + for i in 0 to 5 loop + start_bit := 116 - (i*18); + if (tmp_scan_data(start_bit + 8) = '1') then + c_mode_val_tmp(i) := "bypass"; + if (tmp_scan_data(start_bit + 17) = '1') then + c_mode_val_tmp(i) := " off"; + ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning; + end if; + elsif (tmp_scan_data(start_bit + 17) = '1') then + c_mode_val_tmp(i) := " odd"; + else + c_mode_val_tmp(i) := " even"; + end if; + high := tmp_scan_data(start_bit + 7 downto start_bit); + low := tmp_scan_data(start_bit+16 downto start_bit+9); + if (tmp_scan_data(start_bit+7 downto start_bit) = "00000000") then + c_high_val_tmp(i) := 256; + else + c_high_val_tmp(i) := alt_conv_integer(high); + end if; + if (tmp_scan_data(start_bit+16 downto start_bit+9) = "00000000") then + c_low_val_tmp(i) := 256; + else + c_low_val_tmp(i) := alt_conv_integer(low); + end if; + end loop; + -- the phase taps + for i in 0 to 5 loop + start_bit := 14 + (i*2); + if (tmp_scan_data(start_bit) = '0') then + -- do nothing + elsif (tmp_scan_data(start_bit) = '1') then + if (tmp_scan_data(start_bit + 1) = '1') then + c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1; + if (c_ph_val_tmp(i) > 7) then + c_ph_val_tmp(i) := 0; + end if; + elsif (tmp_scan_data(start_bit + 1) = '0') then + c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1; + if (c_ph_val_tmp(i) < 0) then + c_ph_val_tmp(i) := 7; + end if; + end if; + end if; + end loop; + sig_c_ph_val_tmp <= c_ph_val_tmp; + sig_c_low_val_tmp <= c_low_val_tmp; + sig_c_hi_val_tmp <= c_high_val_tmp; + + -- cntrs M/M2 + for i in 0 to 1 loop + start_bit := 134 + (i*10); + if ( i = 0 or (i = 1 and ss > 0) ) then + is_error := false; + m_tmp := tmp_scan_data(start_bit+8 downto start_bit); + m_val_tmp(i) := alt_conv_integer(m_tmp); + if (tmp_scan_data(start_bit+9) /= '1') then + if (alt_conv_integer(m_tmp) = 1) then + is_error := true; + reconfig_err <= true; + -- cntr value is illegal : give warning + ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(i)& "counter. Instead " &ss_cntrs(i)& "should be BYPASSED. Reconfiguration may not work." severity warning; + elsif (tmp_scan_data(start_bit+8 downto start_bit) = "000000000") then + m_val_tmp(i) := 512; + end if; + if (not is_error) then + if (m_mode_val(i) = "bypass") then + -- Mode is switched : give warning + ASSERT false REPORT "M Counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(m_tmp))& "). PLL may lose lock." severity warning; + else + end if; + m_mode_val(i) <= " "; + end if; + elsif (tmp_scan_data(start_bit+9) = '1') then + if (tmp_scan_data(start_bit) /= '0') then + is_error := true; + reconfig_err <= true; + ASSERT false report "Illegal value for counter " &ss_cntrs(i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning; + else + if (m_mode_val(i) /= "bypass") then + -- Mode is switched : give warning + ASSERT false REPORT "M Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + m_val_tmp(i) := 1; + m_mode_val(i) <= "bypass"; + end if; + end if; + end if; + end loop; + if (ss > 0) then + if (m_mode_val(0) /= m_mode_val(1)) then + reconfig_err <= true; + is_error := true; + ASSERT false REPORT "Incompatible modes for M/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning; + end if; + end if; + sig_m_val_tmp <= m_val_tmp; + -- cntrs N/N2 + for i in 0 to 1 loop + start_bit := 154 + i*10; + if ( i = 0 or (i = 1 and ss > 0) ) then + is_error := false; + n_tmp := tmp_scan_data(start_bit+8 downto start_bit); + n_val(i) <= alt_conv_integer(n_tmp); + if (tmp_scan_data(start_bit+9) /= '1') then + if (alt_conv_integer(n_tmp) = 1) then + is_error := true; + reconfig_err <= true; + -- cntr value is illegal : give warning + ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(2+i)& "counter. Instead " &ss_cntrs(2+i)& "should be BYPASSED. Reconfiguration may not work." severity warning; + elsif (alt_conv_integer(n_tmp) = 0) then + n_val(i) <= 512; + end if; + if (not is_error) then + if (n_mode_val(i) = "bypass") then + ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_tmp))& "). PLL may lose lock." severity warning; + else + end if; + n_mode_val(i) <= " "; + end if; + elsif (tmp_scan_data(start_bit+9) = '1') then + if (tmp_scan_data(start_bit) /= '0') then + is_error := true; + reconfig_err <= true; + ASSERT false report "Illegal value for counter " &ss_cntrs(2+i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning; + else + if (n_mode_val(i) /= "bypass") then + ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning; + end if; + n_val(i) <= 1; + n_mode_val(i) <= "bypass"; + end if; + end if; + end if; + end loop; + if (ss > 0) then + if (n_mode_val(0) /= n_mode_val(1)) then + reconfig_err <= true; + is_error := true; + ASSERT false REPORT "Incompatible modes for N/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning; + end if; + end if; + end if; + + slowest_clk_old := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0), + c_high_val(1)+c_low_val(1), c_mode_val(1), + c_high_val(2)+c_low_val(2), c_mode_val(2), + c_high_val(3)+c_low_val(3), c_mode_val(3), + c_high_val(4)+c_low_val(4), c_mode_val(4), + c_high_val(5)+c_low_val(5), c_mode_val(5), + sig_refclk_period, m_val(0)); + + slowest_clk_new := slowest_clk(c_high_val_tmp(0)+c_low_val_tmp(0), c_mode_val_tmp(0), + c_high_val_tmp(1)+c_low_val_tmp(1), c_mode_val_tmp(1), + c_high_val_tmp(2)+c_low_val_tmp(2), c_mode_val_tmp(2), + c_high_val_tmp(3)+c_low_val_tmp(3), c_mode_val_tmp(3), + c_high_val_tmp(4)+c_low_val_tmp(4), c_mode_val_tmp(4), + c_high_val_tmp(5)+c_low_val_tmp(5), c_mode_val_tmp(5), + sig_refclk_period, m_val_tmp(0)); + + if (slowest_clk_new > slowest_clk_old) then + quiet_time := slowest_clk_new; + else + quiet_time := slowest_clk_old; + end if; + sig_quiet_time <= quiet_time; + sig_slowest_clk_old <= slowest_clk_old; + sig_slowest_clk_new <= slowest_clk_new; + tmp_rem := (quiet_time/1 ps) rem (scanclk_period/ 1 ps); + scanclk_cycles := (quiet_time/1 ps) / (scanclk_period/1 ps); + if (tmp_rem /= 0) then + scanclk_cycles := scanclk_cycles + 1; + end if; + scandone_tmp <= transport '1' after ((scanclk_cycles+1)*scanclk_period - (scanclk_period/2)); + end if; + + if (scanwrite_enabled = '1') then + if (fbclk'event and fbclk = '1') then + m_val <= m_val_tmp; + end if; + + if (c_clk(0)'event and c_clk(0) = '1') then + c_high_val(0) <= c_high_val_tmp(0); + c_mode_val(0) <= c_mode_val_tmp(0); + c0_rising_edge_transfer_done := true; + end if; + if (c_clk(1)'event and c_clk(1) = '1') then + c_high_val(1) <= c_high_val_tmp(1); + c_mode_val(1) <= c_mode_val_tmp(1); + c1_rising_edge_transfer_done := true; + end if; + if (c_clk(2)'event and c_clk(2) = '1') then + c_high_val(2) <= c_high_val_tmp(2); + c_mode_val(2) <= c_mode_val_tmp(2); + c2_rising_edge_transfer_done := true; + end if; + if (c_clk(3)'event and c_clk(3) = '1') then + c_high_val(3) <= c_high_val_tmp(3); + c_mode_val(3) <= c_mode_val_tmp(3); + c3_rising_edge_transfer_done := true; + end if; + if (c_clk(4)'event and c_clk(4) = '1') then + c_high_val(4) <= c_high_val_tmp(4); + c_mode_val(4) <= c_mode_val_tmp(4); + c4_rising_edge_transfer_done := true; + end if; + if (c_clk(5)'event and c_clk(5) = '1') then + c_high_val(5) <= c_high_val_tmp(5); + c_mode_val(5) <= c_mode_val_tmp(5); + c5_rising_edge_transfer_done := true; + end if; + end if; + + if (c_clk(0)'event and c_clk(0) = '0' and c0_rising_edge_transfer_done) then + c_low_val(0) <= c_low_val_tmp(0); + end if; + if (c_clk(1)'event and c_clk(1) = '0' and c1_rising_edge_transfer_done) then + c_low_val(1) <= c_low_val_tmp(1); + end if; + if (c_clk(2)'event and c_clk(2) = '0' and c2_rising_edge_transfer_done) then + c_low_val(2) <= c_low_val_tmp(2); + end if; + if (c_clk(3)'event and c_clk(3) = '0' and c3_rising_edge_transfer_done) then + c_low_val(3) <= c_low_val_tmp(3); + end if; + if (c_clk(4)'event and c_clk(4) = '0' and c4_rising_edge_transfer_done) then + c_low_val(4) <= c_low_val_tmp(4); + end if; + if (c_clk(5)'event and c_clk(5) = '0' and c5_rising_edge_transfer_done) then + c_low_val(5) <= c_low_val_tmp(5); + end if; + + if (scanwrite_enabled = '1') then + for x in 0 to 7 loop + if (vco_tap(x) /= vco_tap_last_value(x) and vco_tap(x) = '0') then + -- TAP X has event + for i in 0 to 5 loop + if (c_ph_val(i) = x) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = x) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + end loop; + end if; + + -- revert counter phase tap values to POF programmed values + -- if PLL is reset + + if (areset_ipd = '1') then + c_ph_val <= i_c_ph; + c_ph_val_tmp := i_c_ph; + m_ph_val <= i_m_ph; + m_ph_val_tmp := i_m_ph; + end if; + + for x in 0 to 7 loop + if (vco_tap(x) /= vco_tap_last_value(x)) then + -- TAP X has event + for i in 0 to 5 loop + if (c_ph_val(i) = x) then + inclk_c_from_vco(i) <= vco_tap(x); + if (i = 0 and enable0_counter = "c0") then + inclk_sclkout0_from_vco <= vco_tap(x); + end if; + if (i = 0 and enable1_counter = "c0") then + inclk_sclkout1_from_vco <= vco_tap(x); + end if; + if (i = 1 and enable0_counter = "c1") then + inclk_sclkout0_from_vco <= vco_tap(x); + end if; + if (i = 1 and enable1_counter = "c1") then + inclk_sclkout1_from_vco <= vco_tap(x); + end if; + end if; + end loop; + + if (m_ph_val = x) then + inclk_m_from_vco <= vco_tap(x); + end if; + + vco_tap_last_value(x) <= vco_tap(x); + end if; + end loop; + + + + if (scanclk_ipd'event and scanclk_ipd = '0') then + -- enable scanwrite on falling edge + scanwrite_enabled <= scanwrite_reg; + end if; + + if (scanread_reg = '1') then + gated_scanclk <= transport scanclk_ipd and scanread_reg; + else + gated_scanclk <= transport '1'; + end if; + + if (scanclk_ipd'event and scanclk_ipd = '1') then + -- register scanread and scanwrite + scanread_reg <= scanread_ipd; + scanwrite_reg <= scanwrite_ipd; + + if (got_first_scanclk) then + scanclk_period := now - scanclk_last_rising_edge; + else + got_first_scanclk := true; + end if; + -- reset got_first_scanclk on falling edge of scanread_reg + if (scanread_ipd = '0' and scanread_reg = '1') then + got_first_scanclk := false; + got_first_gated_scanclk := false; + end if; + + scanclk_last_rising_edge := now; + end if; + + if (gated_scanclk'event and gated_scanclk = '1' and now > 0 ps) then + if (not got_first_gated_scanclk) then + got_first_gated_scanclk := true; + end if; + for j in scan_chain_length - 1 downto 1 loop + scan_data(j) <= scan_data(j-1); + end loop; + scan_data(0) <= scandata_ipd; + end if; + end process; + + scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-1) when (pll_type = "fast" or pll_type = "lvds") else scan_data(GPP_SCAN_CHAIN-1); + + + SCHEDULE : process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, vco_out) + variable sched_time : time := 0 ps; + + TYPE time_array is ARRAY (0 to 7) of time; + variable init : boolean := true; + variable refclk_period : time; + variable m_times_vco_period : time; + variable new_m_times_vco_period : time; + + variable phase_shift : time_array := (OTHERS => 0 ps); + variable last_phase_shift : time_array := (OTHERS => 0 ps); + + variable l_index : integer := 1; + variable cycle_to_adjust : integer := 0; + + variable stop_vco : boolean := false; + + variable locked_tmp : std_logic := '0'; + variable pll_is_locked : boolean := false; + variable pll_about_to_lock : boolean := false; + variable cycles_to_lock : integer := 0; + variable cycles_to_unlock : integer := 0; + + variable got_first_refclk : boolean := false; + variable got_second_refclk : boolean := false; + variable got_first_fbclk : boolean := false; + + variable refclk_time : time := 0 ps; + variable fbclk_time : time := 0 ps; + variable first_fbclk_time : time := 0 ps; + + variable fbclk_period : time := 0 ps; + + variable first_schedule : boolean := true; + + variable vco_val : std_logic := '0'; + variable vco_period_was_phase_adjusted : boolean := false; + variable phase_adjust_was_scheduled : boolean := false; + + variable loop_xplier : integer; + variable loop_initial : integer := 0; + variable loop_ph : integer := 0; + variable loop_time_delay : integer := 0; + + variable initial_delay : time := 0 ps; + variable vco_per : time; + variable tmp_rem : integer; + variable my_rem : integer; + variable fbk_phase : integer := 0; + + variable pull_back_M : integer := 0; + variable total_pull_back : integer := 0; + variable fbk_delay : integer := 0; + + variable offset : time := 0 ps; + + variable tmp_vco_per : integer := 0; + variable high_time : time; + variable low_time : time; + + variable got_refclk_posedge : boolean := false; + variable got_fbclk_posedge : boolean := false; + variable inclk_out_of_range : boolean := false; + variable no_warn : boolean := false; + + variable ext_fbk_cntr_modulus : integer := 1; + variable init_clks : boolean := true; + variable pll_is_in_reset : boolean := false; + variable pll_is_disabled : boolean := false; + variable next_vco_sched_time : time := 0 ps; + variable tap0_is_active : boolean := true; + + begin + if (init) then + + -- jump-start the VCO + -- add 1 ps delay to ensure all signals are updated to initial + -- values + schedule_vco <= transport not schedule_vco after 1 ps; + + init := false; + end if; + + if (schedule_vco'event) then + if (init_clks) then + refclk_period := inclk0_input_frequency * n_val(0) * 1 ps; + + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + init_clks := false; + end if; + sched_time := 0 ps; + for i in 0 to 7 loop + last_phase_shift(i) := phase_shift(i); + end loop; + cycle_to_adjust := 0; + l_index := 1; + m_times_vco_period := new_m_times_vco_period; + end if; + + -- areset was asserted + if (areset_ipd'event and areset_ipd = '1') then + assert false report family_name & " PLL was reset" severity note; + -- reset lock parameters + locked_tmp := '0'; + pll_is_locked := false; + pll_about_to_lock := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + pll_is_in_reset := true; + tap0_is_active := false; + for x in 0 to 7 loop + vco_tap(x) <= '0'; + end loop; + end if; + + -- note areset deassert time + -- note it as refclk_time to prevent false triggering + -- of stop_vco after areset + if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then + refclk_time := now; + pll_is_in_reset := false; + if (ena_ipd = '1' and not stop_vco and next_vco_sched_time <= now) then + schedule_vco <= not schedule_vco; + end if; + end if; + + -- ena was deasserted + if (ena_ipd'event and ena_ipd = '0') then + assert false report family_name & " PLL was disabled" severity note; + pll_is_disabled := true; + tap0_is_active := false; + for x in 0 to 7 loop + vco_tap(x) <= '0'; + end loop; + end if; + + if (ena_ipd'event and ena_ipd = '1') then + assert false report family_name & " PLL is enabled" severity note; + pll_is_disabled := false; + if (areset_ipd /= '1' and not stop_vco and next_vco_sched_time < now) then + schedule_vco <= not schedule_vco; + end if; + end if; + + -- illegal value on areset_ipd + if (areset_ipd'event and areset_ipd = 'X') then + assert false report "Illegal value 'X' detected on ARESET input" severity warning; + end if; + + if (areset_ipd = '1' or ena_ipd = '0' or stop_vco) then + + -- reset lock parameters + locked_tmp := '0'; + pll_is_locked := false; + pll_about_to_lock := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + + got_first_refclk := false; + got_second_refclk := false; + refclk_time := 0 ps; + got_first_fbclk := false; + fbclk_time := 0 ps; + first_fbclk_time := 0 ps; + fbclk_period := 0 ps; + +-- first_schedule := true; +-- vco_val := '0'; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + + -- reset all counter phase taps to POF programmed values + end if; + + if (schedule_vco'event and areset_ipd /= '1' and ena_ipd /= '0' and (not stop_vco) and now > 0 ps) then + + + -- calculate loop_xplier : this will be different from m_val + -- in external_feedback_mode + loop_xplier := m_val(0); + loop_initial := m_initial_val - 1; + loop_ph := m_ph_val; + + if (operation_mode = "external_feedback") then + if (ext_fbk_cntr_mode = "bypass") then + ext_fbk_cntr_modulus := 1; + else + ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low; + end if; + loop_xplier := m_val(0) * (ext_fbk_cntr_modulus); + loop_ph := ext_fbk_cntr_ph; + loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * ext_fbk_cntr_modulus); + end if; + + -- convert initial value to delay + initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; + + -- convert loop ph_tap to delay + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier; + if (my_rem /= 0) then + tmp_vco_per := tmp_vco_per + 1; + end if; + fbk_phase := (loop_ph * tmp_vco_per)/8; + + if (operation_mode = "external_feedback") then + pull_back_M := (m_initial_val - 1) * ext_fbk_cntr_modulus * ((refclk_period/loop_xplier)/1 ps); + while (pull_back_M > refclk_period/1 ps) loop + pull_back_M := pull_back_M - refclk_period/ 1 ps; + end loop; + else + pull_back_M := initial_delay/1 ps + fbk_phase; + end if; + + total_pull_back := pull_back_M; + + if (simulation_type = "timing") then + total_pull_back := total_pull_back + pll_compensation_delay; + end if; + while (total_pull_back > refclk_period/1 ps) loop + total_pull_back := total_pull_back - refclk_period/1 ps; + end loop; + + if (total_pull_back > 0) then + offset := refclk_period - (total_pull_back * 1 ps); + end if; + if (operation_mode = "external_feedback") then + fbk_delay := pull_back_M; + if (simulation_type = "timing") then + fbk_delay := fbk_delay + pll_compensation_delay; + end if; + else + fbk_delay := total_pull_back - fbk_phase; + if (fbk_delay < 0) then + offset := offset - (fbk_phase * 1 ps); + fbk_delay := total_pull_back; + end if; + end if; + + -- assign m_delay + m_delay <= transport fbk_delay after 1 ps; + + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + for i in 1 to loop_xplier loop + -- adjust cycles + tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier; + if (my_rem /= 0 and l_index <= my_rem) then + tmp_rem := (loop_xplier * l_index) rem my_rem; + cycle_to_adjust := (loop_xplier * l_index) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + if (cycle_to_adjust = i) then + tmp_vco_per := tmp_vco_per + 1; + l_index := l_index + 1; + end if; + + -- calculate high and low periods + vco_per := tmp_vco_per * 1 ps; + high_time := (tmp_vco_per/2) * 1 ps; + if (tmp_vco_per rem 2 /= 0) then + high_time := high_time + 1 ps; + end if; + low_time := vco_per - high_time; + + -- schedule the rising and falling edges + for j in 1 to 2 loop + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + + -- schedule tap0 + vco_out(0) <= transport vco_val after sched_time; + end loop; + end loop; + + -- schedule once more + if (first_schedule) then + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + -- schedule tap 0 + vco_out(0) <= transport vco_val after sched_time; + + first_schedule := false; + end if; + + schedule_vco <= transport not schedule_vco after sched_time; + next_vco_sched_time := now + sched_time; + + if (vco_period_was_phase_adjusted) then + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := true; + + vco_per := m_times_vco_period/loop_xplier; + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + end loop; + end if; + end if; + + -- now schedule the other taps with the appropriate phase-shift + if (vco_out(0)'event) then + for k in 1 to 7 loop + phase_shift(k) := (k * vco_per)/8; + vco_out(k) <= transport vco_out(0) after phase_shift(k); + end loop; + end if; + + if (refclk'event and refclk = '1' and areset_ipd = '0') then + got_refclk_posedge := true; + if (not got_first_refclk) then + got_first_refclk := true; + else + got_second_refclk := true; + refclk_period := now - refclk_time; + + -- check if incoming freq. will cause VCO range to be + -- exceeded + if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and + (((refclk_period/1 ps)/loop_xplier > vco_max) or + ((refclk_period/1 ps)/loop_xplier < vco_min)) ) then + if (pll_is_locked) then + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning; + if (inclk_out_of_range) then + pll_is_locked := false; + locked_tmp := '0'; + pll_about_to_lock := false; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + end if; + elsif (not no_warn) then + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning; + no_warn := true; + end if; + inclk_out_of_range := true; + else + inclk_out_of_range := false; + end if; + end if; + + if (stop_vco) then + stop_vco := false; + schedule_vco <= not schedule_vco; + end if; + + refclk_time := now; + else + got_refclk_posedge := false; + end if; + + if (fbclk'event and fbclk = '1') then + got_fbclk_posedge := true; + if (not got_first_fbclk) then + got_first_fbclk := true; + else + fbclk_period := now - fbclk_time; + end if; + + -- need refclk_period here, so initialized to proper value above + if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then + stop_vco := true; + -- reset + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + if (pll_is_locked) then + pll_is_locked := false; + locked_tmp := '0'; + assert false report family_name & " PLL lost lock due to loss of input clock" severity note; + end if; + pll_about_to_lock := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + first_schedule := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + tap0_is_active := false; + for x in 0 to 7 loop + vco_tap(x) <= '0'; + end loop; + end if; + fbclk_time := now; + else + got_fbclk_posedge := false; + end if; + + if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then + + -- now we know actual incoming period + if ( abs(fbclk_time - refclk_time) <= 5 ps or + (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + -- considered in phase + if (cycles_to_lock = valid_lock_multiplier - 1) then + pll_about_to_lock := true; + end if; + if (cycles_to_lock = valid_lock_multiplier) then + if (not pll_is_locked) then + assert false report family_name & " PLL locked to incoming clock" severity note; + end if; + pll_is_locked := true; + locked_tmp := '1'; + cycles_to_unlock := 0; + end if; + -- increment lock counter only if second part of above + -- time check is NOT true + if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + cycles_to_lock := cycles_to_lock + 1; + end if; + + -- adjust m_times_vco_period + new_m_times_vco_period := refclk_period; + else + -- if locked, begin unlock + if (pll_is_locked) then + cycles_to_unlock := cycles_to_unlock + 1; + if (cycles_to_unlock = invalid_lock_multiplier) then + pll_is_locked := false; + locked_tmp := '0'; + pll_about_to_lock := false; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + end if; + end if; + if ( abs(refclk_period - fbclk_period) <= 2 ps ) then + -- frequency is still good + if (now = fbclk_time and (not phase_adjust_was_scheduled)) then + if ( abs(fbclk_time - refclk_time) > refclk_period/2) then + if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then + -- input clock may have stopped : do nothing + else + new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted := true; + end if; + else + new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted := true; + end if; + + end if; + else + phase_adjust_was_scheduled := false; + new_m_times_vco_period := refclk_period; + end if; + + end if; + end if; + + -- check which vco_tap has event + for x in 0 to 7 loop + if (vco_out(x) /= vco_out_last_value(x)) then + -- TAP X has event + if (x = 0 and areset_ipd = '0' and ena_ipd = '1' and sig_stop_vco = '0') then + if (vco_out(0) = '1') then + tap0_is_active := true; + end if; + if (tap0_is_active) then + vco_tap(0) <= vco_out(0); + end if; + elsif (tap0_is_active) then + vco_tap(x) <= vco_out(x); + end if; + if (sig_stop_vco = '1') then + vco_tap(x) <= '0'; + end if; + vco_out_last_value(x) <= vco_out(x); + end if; + end loop; + + if (pfdena_ipd = '0') then + if (pll_is_locked) then + locked_tmp := 'X'; + end if; + pll_is_locked := false; + cycles_to_lock := 0; + end if; + + -- give message only at time of deassertion + if (pfdena_ipd'event and pfdena_ipd = '0') then + assert false report "PFDENA deasserted." severity note; + elsif (pfdena_ipd'event and pfdena_ipd = '1') then + got_first_refclk := false; + got_second_refclk := false; + refclk_time := now; + end if; + + if (reconfig_err) then + lock <= '0'; + else + lock <= locked_tmp; + end if; + about_to_lock <= pll_about_to_lock after 1 ps; + + -- signal to calculate quiet_time + sig_refclk_period <= refclk_period; + + if (stop_vco = true) then + sig_stop_vco <= '1'; + else + sig_stop_vco <= '0'; + end if; + end process SCHEDULE; + + clk0_tmp <= c_clk(i_clk0_counter); + clk(0) <= clk0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + clk1_tmp <= c_clk(i_clk1_counter); + clk(1) <= clk1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + clk2_tmp <= c_clk(i_clk2_counter); + clk(2) <= clk2_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + clk3_tmp <= c_clk(i_clk3_counter); + clk(3) <= clk3_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + clk4_tmp <= c_clk(i_clk4_counter); + clk(4) <= clk4_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + clk5_tmp <= c_clk(i_clk5_counter); + clk(5) <= clk5_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + sclkout(0) <= sclkout0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + sclkout(1) <= sclkout1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else + 'X'; + + scandataout <= scandataout_tmp; + scandone <= scandone_tmp; + +end vital_pll; +-- END ARCHITECTURE VITAL_PLL + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_ttn_mn_cntr +-- +-- Description : Simulation model for the M and N counter. This is a +-- common model for the input counter and the loop feedback +-- counter of the StratixIII PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; + +ENTITY MF_ttn_mn_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END MF_ttn_mn_cntr; + +ARCHITECTURE behave of MF_ttn_mn_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_ttn_scale_cntr +-- +-- Description : Simulation model for the output scale-down counters. +-- This is a common model for the C0, C1, C2, C3, C4 and C5 +-- output counters of the StratixII PLL. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY MF_ttn_scale_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0; + cout : OUT std_logic + ); +END MF_ttn_scale_cntr; + +ARCHITECTURE behave of MF_ttn_scale_cntr is +begin + process (clk, reset) + variable tmp_cout : std_logic := '0'; + variable count : integer := 1; + variable output_shift_count : integer := 1; + variable first_rising_edge : boolean := false; + begin + if (reset = '1') then + count := 1; + output_shift_count := 1; + tmp_cout := '0'; + first_rising_edge := false; + elsif (clk'event) then + if (mode = " off") then + tmp_cout := '0'; + elsif (mode = "bypass") then + tmp_cout := clk; + first_rising_edge := true; + elsif (not first_rising_edge) then + if (clk = '1') then + if (output_shift_count = initial) then + tmp_cout := clk; + first_rising_edge := true; + else + output_shift_count := output_shift_count + 1; + end if; + end if; + elsif (output_shift_count < initial) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + end if; + else + count := count + 1; + if (mode = " even" and (count = (high*2) + 1)) then + tmp_cout := '0'; + elsif (mode = " odd" and (count = high*2)) then + tmp_cout := '0'; + elsif (count = (high + low)*2 + 1) then + tmp_cout := '1'; + count := 1; -- reset count + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; + +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_stratixiii_pll +-- +-- Description : Simulation model for the StratixII PLL. +-- In the functional mode, it is also the model for the altpll +-- megafunction. +-- +-- Limitations : Does not support Spread Spectrum and Bandwidth. +-- +-- Outputs : Up to 10 output clocks, each defined by its own set of +-- parameters. Locked output (active high) indicates when the +-- PLL locks. clkbad and activeclock are used for +-- clock switchover to indicate which input clock has gone +-- bad, when the clock switchover initiates and which input +-- clock is being used as the reference, respectively. +-- scandataout is the data output of the serial scan chain. +-- +--/////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE STD.TEXTIO.all; +USE work.MF_pllpack.all; +USE work.MF_ttn_mn_cntr; +USE work.MF_ttn_scale_cntr; +USE work.dffp; +USE work.MF_pll_reg; + +-- New Features : The list below outlines key new features in TITAN: +-- 1. Dynamic Phase Reconfiguration +-- 2. Dynamic PLL Reconfiguration (different protocol) +-- 3. More output counters + +ENTITY MF_stratixiii_pll is + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM + compensate_clock : string := "clock0"; + + inclk0_input_frequency : integer := 0; + inclk1_input_frequency : integer := 0; + + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 0; + + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + use_dc_coupling : string := "false"; + + + + lock_c : integer := 4; + sim_gate_lock_device_behavior : string := "off"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_window : time := 5 ps; + test_bypass_lock_detect : string := "off"; + + + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 0; + clk0_divide_by : integer := 0; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 0; + clk1_divide_by : integer := 0; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 0; + clk2_divide_by : integer := 0; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 0; + clk3_divide_by : integer := 0; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 0; + clk4_divide_by : integer := 0; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + + clk5_output_frequency : integer := 0; + clk5_multiply_by : integer := 0; + clk5_divide_by : integer := 0; + clk5_phase_shift : string := "0"; + clk5_duty_cycle : integer := 50; + + clk6_output_frequency : integer := 0; + clk6_multiply_by : integer := 0; + clk6_divide_by : integer := 0; + clk6_phase_shift : string := "0"; + clk6_duty_cycle : integer := 50; + + clk7_output_frequency : integer := 0; + clk7_multiply_by : integer := 0; + clk7_divide_by : integer := 0; + clk7_phase_shift : string := "0"; + clk7_duty_cycle : integer := 50; + + clk8_output_frequency : integer := 0; + clk8_multiply_by : integer := 0; + clk8_divide_by : integer := 0; + clk8_phase_shift : string := "0"; + clk8_duty_cycle : integer := 50; + + clk9_output_frequency : integer := 0; + clk9_multiply_by : integer := 0; + clk9_divide_by : integer := 0; + clk9_phase_shift : string := "0"; + clk9_duty_cycle : integer := 50; + + + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + + -- ADVANCED USER PARAMETERS + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + c5_high : integer := 1; + c5_low : integer := 1; + c5_initial : integer := 1; + c5_mode : string := "bypass"; + c5_ph : integer := 0; + + c6_high : integer := 1; + c6_low : integer := 1; + c6_initial : integer := 1; + c6_mode : string := "bypass"; + c6_ph : integer := 0; + + c7_high : integer := 1; + c7_low : integer := 1; + c7_initial : integer := 1; + c7_mode : string := "bypass"; + c7_ph : integer := 0; + + c8_high : integer := 1; + c8_low : integer := 1; + c8_initial : integer := 1; + c8_mode : string := "bypass"; + c8_ph : integer := 0; + + c9_high : integer := 1; + c9_low : integer := 1; + c9_initial : integer := 1; + c9_mode : string := "bypass"; + c9_ph : integer := 0; + + m_ph : integer := 0; + + clk0_counter : string := "unused"; + clk1_counter : string := "unused"; + clk2_counter : string := "unused"; + clk3_counter : string := "unused"; + clk4_counter : string := "unused"; + clk5_counter : string := "unused"; + clk6_counter : string := "unused"; + clk7_counter : string := "unused"; + clk8_counter : string := "unused"; + clk9_counter : string := "unused"; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + c5_use_casc_in : string := "off"; + c6_use_casc_in : string := "off"; + c7_use_casc_in : string := "off"; + c8_use_casc_in : string := "off"; + c9_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + c5_test_source : integer := -1; + c6_test_source : integer := -1; + c7_test_source : integer := -1; + c8_test_source : integer := -1; + c9_test_source : integer := -1; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + vco_post_scale : integer := 1; + vco_frequency_control : string := "auto"; + vco_phase_shift_step : integer := 0; + + charge_pump_current : integer := 10; + loop_filter_r : string := " 1.0"; + loop_filter_c : integer := 0; + + + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + clk5_use_even_counter_mode : string := "off"; + clk6_use_even_counter_mode : string := "off"; + clk7_use_even_counter_mode : string := "off"; + clk8_use_even_counter_mode : string := "off"; + clk9_use_even_counter_mode : string := "off"; + + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + clk5_use_even_counter_value : string := "off"; + clk6_use_even_counter_value : string := "off"; + clk7_use_even_counter_value : string := "off"; + clk8_use_even_counter_value : string := "off"; + clk9_use_even_counter_value : string := "off"; + +-- Test only + init_block_reset_a_count : integer := 1; + init_block_reset_b_count : integer := 1; + charge_pump_current_bits : integer := 0; + lock_window_ui_bits : integer := 0; + loop_filter_c_bits : integer := 0; + loop_filter_r_bits : integer := 0; + test_counter_c0_delay_chain_bits : integer := 0; + test_counter_c1_delay_chain_bits : integer := 0; + test_counter_c2_delay_chain_bits : integer := 0; + test_counter_c3_delay_chain_bits : integer := 0; + test_counter_c4_delay_chain_bits : integer := 0; + test_counter_c5_delay_chain_bits : integer := 0; + test_counter_c6_delay_chain_bits : integer := 0; + test_counter_c7_delay_chain_bits : integer := 0; + test_counter_c8_delay_chain_bits : integer := 0; + test_counter_c9_delay_chain_bits : integer := 0; + test_counter_m_delay_chain_bits : integer := 0; + test_counter_n_delay_chain_bits : integer := 0; + test_feedback_comp_delay_chain_bits : integer := 0; + test_input_comp_delay_chain_bits : integer := 0; + test_volt_reg_output_mode_bits : integer := 0; + test_volt_reg_output_voltage_bits : integer := 0; + test_volt_reg_test_mode : string := "false"; + vco_range_detector_high_bits : integer := -1; + vco_range_detector_low_bits : integer := -1; + scan_chain_mif_file : string := ""; + dpa_output_clock_phase_shift : integer := 0; + test_counter_c3_sclk_delay_chain_bits : integer := -1; + test_counter_c4_sclk_delay_chain_bits : integer := -1; + test_counter_c5_lden_delay_chain_bits : integer := -1; + test_counter_c6_lden_delay_chain_bits : integer := -1; + + auto_settings : string := "true"; +-- Simulation only generics + family_name : string := "StratixIII"; + + use_vco_bypass : string := "false" + ); + + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + fbout : out std_logic; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + clk : out std_logic_vector(9 downto 0); + phasecounterselect : in std_logic_vector(3 downto 0) := "0000"; + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic + + ); +END MF_stratixiii_pll; + +ARCHITECTURE vital_pll of MF_stratixiii_pll is + +function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is +begin + if (i_vco_post_scale = 1) then + return vco_min * 2; + else + return vco_min; + end if; +end; + +function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is +begin + if (i_vco_post_scale = 1) then + return vco_max * 2; + else + return vco_max; + end if; +end; + +TYPE int_array is ARRAY(NATURAL RANGE <>) of integer; +TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6); +TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9); +TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic; + +constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale); +constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale); + +-- internal advanced parameter signals +signal i_vco_min : integer := vco_min; +signal i_vco_max : integer := vco_max; +signal i_vco_center : integer; +signal i_pfd_min : integer; +signal i_pfd_max : integer; + signal c_ph_val : int_array(0 to 9) := (OTHERS => 0); + signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0); + signal c_high_val : int_array(0 to 9) := (OTHERS => 1); + signal c_low_val : int_array(0 to 9) := (OTHERS => 1); + signal c_initial_val : int_array(0 to 9) := (OTHERS => 1); + signal c_mode_val : str_array(0 to 9); + signal clk_num : str_array(0 to 9); + +-- old values + signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1); + signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1); + signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0); + signal c_mode_val_old : str_array(0 to 9); +-- hold registers + signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1); + signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1); + signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0); + signal c_mode_val_hold : str_array(0 to 9); + +-- temp registers + signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0); + signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0); + + signal i_clk9_counter : integer := 9; + signal i_clk8_counter : integer := 8; + signal i_clk7_counter : integer := 7; + signal i_clk6_counter : integer := 6; + signal i_clk5_counter : integer := 5; +signal real_lock_high : integer := 0; +signal i_clk4_counter : integer := 4; +signal i_clk3_counter : integer := 3; +signal i_clk2_counter : integer := 2; +signal i_clk1_counter : integer := 1; +signal i_clk0_counter : integer := 0; +signal i_charge_pump_current : integer; +signal i_loop_filter_r : integer; + +-- end internal advanced parameter signals + +-- CONSTANTS +CONSTANT SCAN_CHAIN : integer := 144; +CONSTANT GPP_SCAN_CHAIN : integer := 234; +CONSTANT FAST_SCAN_CHAIN : integer := 180; + CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0"); +CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2"); + +CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + +CONSTANT num_phase_taps : integer := 8; +-- signals + +signal vcc : std_logic := '1'; + +signal fbclk : std_logic; +signal refclk : std_logic; +signal vco_over : std_logic := '0'; +signal vco_under : std_logic := '1'; + +signal pll_locked : boolean := false; + + + signal c_clk : std_logic_array(0 to 9); +signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); + +-- signals to assign values to counter params +signal m_val : integer := 1; +signal n_val : integer := 1; +signal m_ph_val : integer := 0; +signal m_ph_initial : integer := 0; +signal m_ph_val_tmp : integer := 0; +signal m_initial_val : integer := m_initial; + +signal m_mode_val : string(1 to 6) := " "; +signal n_mode_val : string(1 to 6) := " "; +signal lfc_val : integer := 0; +signal vco_cur : integer := vco_post_scale; +signal cp_curr_val : integer := 0; +signal lfr_val : string(1 to 2) := " "; + +signal cp_curr_old_bit_setting : integer := charge_pump_current_bits; +signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0'); +signal lfr_old_bit_setting : integer := loop_filter_r_bits; +signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0'); +signal lfc_old_bit_setting : integer := loop_filter_c_bits; +signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0'); + +signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true +-- old values +signal m_val_old : integer := 1; +signal n_val_old : integer := 1; +signal m_mode_val_old : string(1 to 6) := " "; +signal n_mode_val_old : string(1 to 6) := " "; +signal m_ph_val_old : integer := 0; +signal lfc_old : integer := 0; +signal vco_old : integer := 0; +signal cp_curr_old : integer := 0; +signal lfr_old : string(1 to 2) := " "; + signal num_output_cntrs : integer := 10; +signal scanclk_period : time := 1 ps; + signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0'); + + + signal clk_pfd : std_logic_vector(0 to 9); +signal clk0_tmp : std_logic; +signal clk1_tmp : std_logic; +signal clk2_tmp : std_logic; +signal clk3_tmp : std_logic; +signal clk4_tmp : std_logic; + signal clk5_tmp : std_logic; + signal clk6_tmp : std_logic; + signal clk7_tmp : std_logic; + signal clk8_tmp : std_logic; + signal clk9_tmp : std_logic; + +signal update_conf_latches : std_logic := '0'; +signal update_conf_latches_reg : std_logic := '0'; + +signal clkin : std_logic := '0'; +signal gate_locked : std_logic := '0'; +signal pfd_locked : std_logic := '0'; +signal lock : std_logic := '0'; +signal about_to_lock : boolean := false; +signal reconfig_err : boolean := false; + +signal inclk_c0 : std_logic; +signal inclk_c1 : std_logic; +signal inclk_c2 : std_logic; +signal inclk_c3 : std_logic; +signal inclk_c4 : std_logic; + signal inclk_c5 : std_logic; + signal inclk_c6 : std_logic; + signal inclk_c7 : std_logic; + signal inclk_c8 : std_logic; + signal inclk_c9 : std_logic; +signal inclk_m : std_logic; +signal devpor : std_logic; +signal devclrn : std_logic; + +signal inclk0_ipd : std_logic; +signal inclk1_ipd : std_logic; +signal pfdena_ipd : std_logic; +signal areset_ipd : std_logic; +signal fbin_ipd : std_logic; +signal scanclk_ipd : std_logic; +signal scanclkena_ipd, scanclkena_reg : std_logic; +signal scandata_ipd : std_logic; +signal clkswitch_ipd : std_logic; + signal phasecounterselect_ipd : std_logic_vector(3 downto 0); +signal phaseupdown_ipd : std_logic; +signal phasestep_ipd : std_logic; +signal configupdate_ipd : std_logic; +-- registered signals + +signal sig_offset : time := 0 ps; +signal sig_refclk_time : time := 0 ps; +signal sig_fbclk_period : time := 0 ps; +signal sig_vco_period_was_phase_adjusted : boolean := false; +signal sig_phase_adjust_was_scheduled : boolean := false; +signal sig_stop_vco : std_logic := '0'; +signal sig_m_times_vco_period : time := 0 ps; +signal sig_new_m_times_vco_period : time := 0 ps; +signal sig_got_refclk_posedge : boolean := false; +signal sig_got_fbclk_posedge : boolean := false; +signal sig_got_second_refclk : boolean := false; + +signal m_delay : integer := 0; +signal n_delay : integer := 0; + +signal inclk1_tmp : std_logic := '0'; + + +signal reset_low : std_logic := '0'; + +-- Phase Reconfig + + SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0); + +SIGNAL phaseupdown_reg : std_logic := '0'; +SIGNAL phasestep_reg : std_logic := '0'; +SIGNAL phasestep_high_count : integer := 0; +SIGNAL update_phase : std_logic := '0'; + +signal scandataout_tmp : std_logic := '0'; +signal scandata_in : std_logic := '0'; +signal scandata_out : std_logic := '0'; +signal scandone_tmp : std_logic := '1'; +signal initiate_reconfig : std_logic := '0'; + +signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; + +signal schedule_vco : std_logic := '0'; + +signal areset_ena_sig : std_logic := '0'; +signal pll_in_test_mode : boolean := false; +signal pll_has_just_been_reconfigured : boolean := false; + + signal inclk_c_from_vco : std_logic_array(0 to 9); + +signal inclk_m_from_vco : std_logic; + +SIGNAL inclk0_period : time := 0 ps; +SIGNAL last_inclk0_period : time := 0 ps; +SIGNAL last_inclk0_edge : time := 0 ps; +SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0'; +SIGNAL inclk1_period : time := 0 ps; +SIGNAL last_inclk1_period : time := 0 ps; +SIGNAL last_inclk1_edge : time := 0 ps; +SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0'; + + + +COMPONENT MF_ttn_mn_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END COMPONENT; + +COMPONENT MF_ttn_scale_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0 + ); +END COMPONENT; + +COMPONENT dffp + + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +COMPONENT MF_pll_reg + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +begin + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + WireDelay : block + begin + inclk0_ipd <= inclk(0); + inclk1_ipd <= inclk(1); + areset_ipd <= areset; + fbin_ipd <= fbin; + pfdena_ipd <= pfdena; + scanclk_ipd <= scanclk; + scanclkena_ipd <= scanclkena; + scandata_ipd <= scandata; + configupdate_ipd <= configupdate; + clkswitch_ipd <= clkswitch; + phaseupdown_ipd <= phaseupdown; + phasestep_ipd <= phasestep; + phasecounterselect_ipd(0) <= phasecounterselect(0); + phasecounterselect_ipd(1) <= phasecounterselect(1); + phasecounterselect_ipd(2) <= phasecounterselect(2); + phasecounterselect_ipd(3) <= phasecounterselect(3); + + end block; + +inclk_m <= fbclk when m_test_source = 0 else + refclk when m_test_source = 1 else + inclk_m_from_vco; + + areset_ena_sig <= areset_ipd or sig_stop_vco; + + pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or + c1_test_source /= -1 or c2_test_source /= -1 or + c3_test_source /= -1 or c4_test_source /= -1 or + c5_test_source /= -1 or c6_test_source /= -1 or + c7_test_source /= -1 or c8_test_source /= -1 or + c9_test_source /= -1) + else + false; + + + real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0; + m1 : MF_ttn_mn_cntr + port map ( clk => inclk_m, + reset => areset_ena_sig, + cout => fbclk, + initial_value => m_initial_val, + modulus => m_val, + time_delay => m_delay + ); + + -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed + -- in different simulation deltas. + inclk1_tmp <= inclk1_ipd; + + -- Calculate the inclk0 period + PROCESS + VARIABLE inclk0_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1'); + IF (first_inclk0_edge_detect = '0') THEN + first_inclk0_edge_detect <= '1'; + ELSE + last_inclk0_period <= inclk0_period; + inclk0_period_tmp := NOW - last_inclk0_edge; + END IF; + last_inclk0_edge <= NOW; + inclk0_period <= inclk0_period_tmp; + END PROCESS; + + + -- Calculate the inclk1 period + PROCESS + VARIABLE inclk1_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1'); + IF (first_inclk1_edge_detect = '0') THEN + first_inclk1_edge_detect <= '1'; + ELSE + last_inclk1_period <= inclk1_period; + inclk1_period_tmp := NOW - last_inclk1_edge; + END IF; + last_inclk1_edge <= NOW; + inclk1_period <= inclk1_period_tmp; + END PROCESS; + + process (inclk0_ipd, inclk1_tmp, clkswitch_ipd) + variable input_value : std_logic := '0'; + variable current_clock : integer := 0; + variable clk0_count, clk1_count : integer := 0; + variable clk0_is_bad, clk1_is_bad : std_logic := '0'; + variable primary_clk_is_bad : boolean := false; + variable current_clk_is_bad : boolean := false; + variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; + variable switch_over_count : integer := 0; + variable active_clock : std_logic := '0'; + variable external_switch : boolean := false; + variable diff_percent_period : integer := 0; + variable buf : line; + variable switch_clock : boolean := false; + + begin + if (now = 0 ps) then + if (switch_over_type = "manual" and clkswitch_ipd = '1') then + current_clock := 1; + active_clock := '1'; + end if; + end if; + if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then + external_switch := true; + elsif (switch_over_type = "manual") then + if (clkswitch_ipd'event and clkswitch_ipd = '1') then + switch_clock := true; + elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then + switch_clock := false; + end if; + end if; + + if (switch_clock = true) then + if (inclk0_ipd'event or inclk1_tmp'event) then + if (current_clock = 0) then + current_clock := 1; + active_clock := '1'; + clkin <= transport inclk1_tmp; + elsif (current_clock = 1) then + current_clock := 0; + active_clock := '0'; + clkin <= transport inclk0_ipd; + end if; + switch_clock := false; + end if; + end if; + + -- save the current inclk event value + if (inclk0_ipd'event) then + input_value := inclk0_ipd; + elsif (inclk1_tmp'event) then + input_value := inclk1_tmp; + end if; + + -- check if either input clk is bad + if (inclk0_ipd'event and inclk0_ipd = '1') then + clk0_count := clk0_count + 1; + clk0_is_bad := '0'; + clk1_count := 0; + if (clk0_count > 2) then + -- no event on other clk for 2 cycles + clk1_is_bad := '1'; + if (current_clock = 1) then + current_clk_is_bad := true; + end if; + end if; + end if; + if (inclk1_tmp'event and inclk1_tmp = '1') then + clk1_count := clk1_count + 1; + clk1_is_bad := '0'; + clk0_count := 0; + if (clk1_count > 2) then + -- no event on other clk for 2 cycles + clk0_is_bad := '1'; + if (current_clock = 0) then + current_clk_is_bad := true; + end if; + end if; + end if; + + -- check if the bad clk is the primary clock + if (clk0_is_bad = '1') then + primary_clk_is_bad := true; + else + primary_clk_is_bad := false; + end if; + + -- actual switching + if (inclk0_ipd'event and current_clock = 0) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk0_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk0_ipd; + end if; + else + clkin <= transport inclk0_ipd; + end if; + elsif (inclk1_tmp'event and current_clock = 1) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk1_tmp = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk1_tmp; + end if; + else + clkin <= transport inclk1_tmp; + end if; + else + if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then + switch_over_count := switch_over_count + 1; + end if; + if ((input_value = '0')) then + if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then + got_curr_clk_falling_edge_after_clkswitch := false; + + if (areset_ipd = '0') then + if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then + diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period; + elsif (inclk0_period /= 0 ps) then + diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period; + end if; + + if((diff_percent_period > 20)and ( switch_over_type = "auto")) then + WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.")); + writeline(output, buf); + end if; + end if; + + if (current_clock = 0) then + current_clock := 1; + else + current_clock := 0; + end if; + active_clock := not active_clock; + switch_over_count := 0; + external_switch := false; + current_clk_is_bad := false; + else + if(switch_over_type = "auto") then + if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then + current_clock := 1; + active_clock := not active_clock; + end if; + + if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then + current_clock := 0; + active_clock := not active_clock; + end if; + end if; + end if; + + end if; + end if; + + -- schedule outputs + clkbad(0) <= clk0_is_bad; + clkbad(1) <= clk1_is_bad; + activeclock <= active_clock; + + end process; + + + n1 : MF_ttn_mn_cntr + port map ( + clk => clkin, + reset => areset_ipd, + cout => refclk, + initial_value => n_val, + modulus => n_val); + +inclk_c0 <= refclk when c0_test_source = 1 else + fbclk when c0_test_source = 0 else + inclk_c_from_vco(0); + + + c0 : MF_ttn_scale_cntr + port map ( + clk => inclk_c0, + reset => areset_ena_sig, + cout => c_clk(0), + initial => c_initial_val(0), + high => c_high_val(0), + low => c_low_val(0), + mode => c_mode_val(0), + ph_tap => c_ph_val(0)); + + inclk_c1 <= refclk when c1_test_source = 1 else + fbclk when c1_test_source = 0 else + c_clk(0) when c1_use_casc_in = "on" else + inclk_c_from_vco(1); + + + c1 : MF_ttn_scale_cntr + port map ( + clk => inclk_c1, + reset => areset_ena_sig, + cout => c_clk(1), + initial => c_initial_val(1), + high => c_high_val(1), + low => c_low_val(1), + mode => c_mode_val(1), + ph_tap => c_ph_val(1)); + +inclk_c2 <= refclk when c2_test_source = 1 else + fbclk when c2_test_source = 0 else + c_clk(1) when c2_use_casc_in = "on" else + inclk_c_from_vco(2); + + c2 : MF_ttn_scale_cntr + port map ( + clk => inclk_c2, + reset => areset_ena_sig, + cout => c_clk(2), + initial => c_initial_val(2), + high => c_high_val(2), + low => c_low_val(2), + mode => c_mode_val(2), + ph_tap => c_ph_val(2)); + + + inclk_c3 <= refclk when c3_test_source = 1 else + fbclk when c3_test_source = 0 else + c_clk(2) when c3_use_casc_in = "on" else + inclk_c_from_vco(3); + + c3 : MF_ttn_scale_cntr + port map ( + clk => inclk_c3, + reset => areset_ena_sig, + cout => c_clk(3), + initial => c_initial_val(3), + high => c_high_val(3), + low => c_low_val(3), + mode => c_mode_val(3), + ph_tap => c_ph_val(3)); + + inclk_c4 <= refclk when c4_test_source = 1 else + fbclk when c4_test_source = 0 else + c_clk(3) when (c4_use_casc_in = "on") else + inclk_c_from_vco(4); + + c4 : MF_ttn_scale_cntr + port map ( + clk => inclk_c4, + reset => areset_ena_sig, + cout => c_clk(4), + initial => c_initial_val(4), + high => c_high_val(4), + low => c_low_val(4), + mode => c_mode_val(4), + ph_tap => c_ph_val(4)); + + inclk_c5 <= refclk when c5_test_source = 1 else + fbclk when c5_test_source = 0 else + c_clk(4) when c5_use_casc_in = "on" else + inclk_c_from_vco(5); + + c5 : MF_ttn_scale_cntr + port map ( + clk => inclk_c5, + reset => areset_ena_sig, + cout => c_clk(5), + initial => c_initial_val(5), + high => c_high_val(5), + low => c_low_val(5), + mode => c_mode_val(5), + ph_tap => c_ph_val(5)); + + inclk_c6 <= refclk when c6_test_source = 1 else + fbclk when c6_test_source = 0 else + c_clk(5) when c6_use_casc_in = "on" else + inclk_c_from_vco(6); + + c6 : MF_ttn_scale_cntr + port map ( + clk => inclk_c6, + reset => areset_ena_sig, + cout => c_clk(6), + initial => c_initial_val(6), + high => c_high_val(6), + low => c_low_val(6), + mode => c_mode_val(6), + ph_tap => c_ph_val(6)); + + inclk_c7 <= refclk when c7_test_source = 1 else + fbclk when c7_test_source = 0 else + c_clk(6) when c7_use_casc_in = "on" else + inclk_c_from_vco(7); + + c7 : MF_ttn_scale_cntr + port map ( + clk => inclk_c7, + reset => areset_ena_sig, + cout => c_clk(7), + initial => c_initial_val(7), + high => c_high_val(7), + low => c_low_val(7), + mode => c_mode_val(7), + ph_tap => c_ph_val(7)); + + inclk_c8 <= refclk when c8_test_source = 1 else + fbclk when c8_test_source = 0 else + c_clk(7) when c8_use_casc_in = "on" else + inclk_c_from_vco(8); + + c8 : MF_ttn_scale_cntr + port map ( + clk => inclk_c8, + reset => areset_ena_sig, + cout => c_clk(8), + initial => c_initial_val(8), + high => c_high_val(8), + low => c_low_val(8), + mode => c_mode_val(8), + ph_tap => c_ph_val(8)); + + inclk_c9 <= refclk when c9_test_source = 1 else + fbclk when c9_test_source = 0 else + c_clk(8) when c9_use_casc_in = "on" else + inclk_c_from_vco(9); + + c9 : MF_ttn_scale_cntr + port map ( + clk => inclk_c9, + reset => areset_ena_sig, + cout => c_clk(9), + initial => c_initial_val(9), + high => c_high_val(9), + low => c_low_val(9), + mode => c_mode_val(9), + ph_tap => c_ph_val(9)); + + process(scandone_tmp, lock) + begin + if (scandone_tmp'event and (scandone_tmp = '1')) then + pll_has_just_been_reconfigured <= true; + elsif (lock'event and (lock = '1')) then + pll_has_just_been_reconfigured <= false; + end if; + end process; + + process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco) + variable c0_got_first_rising_edge : boolean := false; + variable c0_count : integer := 2; + variable c0_initial_count : integer := 1; + variable c0_tmp, c1_tmp : std_logic := '0'; + variable c1_got_first_rising_edge : boolean := false; + variable c1_count : integer := 2; + variable c1_initial_count : integer := 1; + begin + if (areset_ipd = '1' or sig_stop_vco = '1') then + c0_count := 2; + c1_count := 2; + c0_initial_count := 1; + c1_initial_count := 1; + c0_got_first_rising_edge := false; + c1_got_first_rising_edge := false; + else + if (not c0_got_first_rising_edge) then + if (inclk_c0'event and inclk_c0 = '1') then + if (c0_initial_count = c_initial_val(0)) then + c0_got_first_rising_edge := true; + else + c0_initial_count := c0_initial_count + 1; + end if; + end if; + elsif (inclk_c0'event) then + c0_count := c0_count + 1; + if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then + c0_count := 1; + end if; + end if; + if (inclk_c0'event and inclk_c0 = '0') then + if (c0_count = 1) then + c0_tmp := '1'; + c0_got_first_rising_edge := false; + else + c0_tmp := '0'; + end if; + end if; + + if (not c1_got_first_rising_edge) then + if (inclk_c1'event and inclk_c1 = '1') then + if (c1_initial_count = c_initial_val(1)) then + c1_got_first_rising_edge := true; + else + c1_initial_count := c1_initial_count + 1; + end if; + end if; + elsif (inclk_c1'event) then + c1_count := c1_count + 1; + if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then + c1_count := 1; + end if; + end if; + if (inclk_c1'event and inclk_c1 = '0') then + if (c1_count = 1) then + c1_tmp := '1'; + c1_got_first_rising_edge := false; + else + c1_tmp := '0'; + end if; + end if; + end if; + + end process; + + + locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE + lock; + + + process (scandone_tmp) + variable buf : line; + begin + if (scandone_tmp'event and scandone_tmp = '1') then + if (reconfig_err = false) then + ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note; + write (buf, string'(" N modulus = ")); + write (buf, n_val); + write (buf, string'(" ( ")); + write (buf, n_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M modulus = ")); + write (buf, m_val); + write (buf, string'(" ( ")); + write (buf, m_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M ph_tap = ")); + write (buf, m_ph_val); + write (buf, string'(" ( ")); + write (buf, m_ph_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + for i in 0 to (num_output_cntrs-1) loop + write (buf, clk_num(i)); + write (buf, string'(" : ")); + write (buf, cntrs(i)); + write (buf, string'(" : high = ")); + write (buf, c_high_val(i)); + write (buf, string'(" (")); + write (buf, c_high_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , low = ")); + write (buf, c_low_val(i)); + write (buf, string'(" (")); + write (buf, c_low_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , mode = ")); + write (buf, c_mode_val(i)); + write (buf, string'(" (")); + write (buf, c_mode_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , phase tap = ")); + write (buf, c_ph_val(i)); + write (buf, string'(" (")); + write (buf, c_ph_val_old(i)); + write (buf, string'(") ")); + writeline(output, buf); + end loop; + + IF (pll_reconfig_display_full_setting) THEN + write (buf, string'(" Charge Pump Current (uA) = ")); + write (buf, cp_curr_val); + write (buf, string'(" ( ")); + write (buf, cp_curr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (pF) = ")); + write (buf, lfc_val); + write (buf, string'(" ( ")); + write (buf, lfc_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (Kohm) = ")); + write (buf, lfr_val); + write (buf, string'(" ( ")); + write (buf, lfr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + + ELSE + write (buf, string'(" Charge Pump Current (bit setting) = ")); + write (buf, alt_conv_integer(cp_curr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, cp_curr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (bit setting) = ")); + write (buf, alt_conv_integer(lfc_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfc_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (bit setting) = ")); + write (buf, alt_conv_integer(lfr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + END IF; + cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting); + lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting); + lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting); + else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning; + end if; + end if; + + end process; + + update_conf_latches <= configupdate_ipd; + + + process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd) + variable init : boolean := true; + variable low, high : std_logic_vector(7 downto 0); + variable low_fast, high_fast : std_logic_vector(3 downto 0); + variable mode : string(1 to 6) := "bypass"; + variable is_error : boolean := false; + variable m_tmp, n_tmp : std_logic_vector(8 downto 0); + variable lfr_val_tmp : string(1 to 2) := " "; + + variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1); + variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1); + variable c_mode_val_tmp : str_array(0 to 9); + variable m_val_tmp : integer := 0; + variable c0_rising_edge_transfer_done : boolean := false; + variable c1_rising_edge_transfer_done : boolean := false; + variable c2_rising_edge_transfer_done : boolean := false; + variable c3_rising_edge_transfer_done : boolean := false; + variable c4_rising_edge_transfer_done : boolean := false; + variable c5_rising_edge_transfer_done : boolean := false; + variable c6_rising_edge_transfer_done : boolean := false; + variable c7_rising_edge_transfer_done : boolean := false; + variable c8_rising_edge_transfer_done : boolean := false; + variable c9_rising_edge_transfer_done : boolean := false; + + -- variables for scaling of multiply_by and divide_by values + variable i_clk0_mult_by : integer := 1; + variable i_clk0_div_by : integer := 1; + variable i_clk1_mult_by : integer := 1; + variable i_clk1_div_by : integer := 1; + variable i_clk2_mult_by : integer := 1; + variable i_clk2_div_by : integer := 1; + variable i_clk3_mult_by : integer := 1; + variable i_clk3_div_by : integer := 1; + variable i_clk4_mult_by : integer := 1; + variable i_clk4_div_by : integer := 1; + variable i_clk5_mult_by : integer := 1; + variable i_clk5_div_by : integer := 1; + variable i_clk6_mult_by : integer := 1; + variable i_clk6_div_by : integer := 1; + variable i_clk7_mult_by : integer := 1; + variable i_clk7_div_by : integer := 1; + variable i_clk8_mult_by : integer := 1; + variable i_clk8_div_by : integer := 1; + variable i_clk9_mult_by : integer := 1; + variable i_clk9_div_by : integer := 1; + variable max_d_value : integer := 1; + variable new_multiplier : integer := 1; + + -- internal variables for storing the phase shift number.(used in lvds mode only) + variable i_clk0_phase_shift : integer := 1; + variable i_clk1_phase_shift : integer := 1; + variable i_clk2_phase_shift : integer := 1; + + -- user to advanced variables + + variable max_neg_abs : integer := 0; + variable i_m_initial : integer; + variable i_m : integer := 1; + variable i_n : integer := 1; + variable i_c_high : int_array(0 to 9); + variable i_c_low : int_array(0 to 9); + variable i_c_initial : int_array(0 to 9); + variable i_c_ph : int_array(0 to 9); + variable i_c_mode : str_array(0 to 9); + variable i_m_ph : integer; + variable output_count : integer; + variable new_divisor : integer; + + variable clk0_cntr : string(1 to 6) := " c0"; + variable clk1_cntr : string(1 to 6) := " c1"; + variable clk2_cntr : string(1 to 6) := " c2"; + variable clk3_cntr : string(1 to 6) := " c3"; + variable clk4_cntr : string(1 to 6) := " c4"; + variable clk5_cntr : string(1 to 6) := " c5"; + variable clk6_cntr : string(1 to 6) := " c6"; + variable clk7_cntr : string(1 to 6) := " c7"; + variable clk8_cntr : string(1 to 6) := " c8"; + variable clk9_cntr : string(1 to 6) := " c9"; + + variable fbk_cntr : string(1 to 2); + variable fbk_cntr_index : integer; + variable start_bit : integer; + variable quiet_time : time := 0 ps; + variable slowest_clk_old : time := 0 ps; + variable slowest_clk_new : time := 0 ps; + + variable i : integer := 0; + variable j : integer := 0; + variable scanread_active_edge : time := 0 ps; + variable got_first_scanclk : boolean := false; + variable scanclk_last_rising_edge : time := 0 ps; + variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0'); + + variable index : integer := 0; + variable scan_chain_length : integer := GPP_SCAN_CHAIN; + variable tmp_rem : integer := 0; + variable scanclk_cycles : integer := 0; + variable lfc_tmp : std_logic_vector(1 downto 0); + variable lfr_tmp : std_logic_vector(5 downto 0); + variable lfr_int : integer := 0; + + variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0); + variable buf : line; + variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0'); + variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0'); + + function slowest_clk ( + C0 : integer; C0_mode : string(1 to 6); + C1 : integer; C1_mode : string(1 to 6); + C2 : integer; C2_mode : string(1 to 6); + C3 : integer; C3_mode : string(1 to 6); + C4 : integer; C4_mode : string(1 to 6); + C5 : integer; C5_mode : string(1 to 6); + C6 : integer; C6_mode : string(1 to 6); + C7 : integer; C7_mode : string(1 to 6); + C8 : integer; C8_mode : string(1 to 6); + C9 : integer; C9_mode : string(1 to 6); + refclk : time; m_mod : integer) return time is + variable max_modulus : integer := 1; + variable q_period : time := 0 ps; + variable refclk_int : integer := 0; + begin + if (C0_mode /= "bypass" and C0_mode /= " off") then + max_modulus := C0; + end if; + if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then + max_modulus := C1; + end if; + if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then + max_modulus := C2; + end if; + if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then + max_modulus := C3; + end if; + if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then + max_modulus := C4; + end if; + if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then + max_modulus := C5; + end if; + if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then + max_modulus := C6; + end if; + if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then + max_modulus := C7; + end if; + if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then + max_modulus := C8; + end if; + if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then + max_modulus := C9; + end if; + + refclk_int := refclk / 1 ps; + if (m_mod /= 0) then + q_period := (refclk_int * max_modulus / m_mod) * 1 ps; + end if; + return (2*q_period); + end slowest_clk; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + + function extract_cntr_string (arg:string) return string is + variable str : string(1 to 6) := " c0"; + begin + if (arg = "c0") then + str := " c0"; + elsif (arg = "c1") then + str := " c1"; + elsif (arg = "c2") then + str := " c2"; + elsif (arg = "c3") then + str := " c3"; + elsif (arg = "c4") then + str := " c4"; + elsif (arg = "c5") then + str := " c5"; + elsif (arg = "c6") then + str := " c6"; + elsif (arg = "c7") then + str := " c7"; + elsif (arg = "c8") then + str := " c8"; + elsif (arg = "c9") then + str := " c9"; + else str := " c0"; + + end if; + + return str; + + end extract_cntr_string; + + function extract_cntr_index (arg:string) return integer is + variable index : integer := 0; + begin + if (arg(6) = '0') then + index := 0; + elsif (arg(6) = '1') then + index := 1; + elsif (arg(6) = '2') then + index := 2; + elsif (arg(6) = '3') then + index := 3; + elsif (arg(6) = '4') then + index := 4; + elsif (arg(6) = '5') then + index := 5; + elsif (arg(6) = '6') then + index := 6; + elsif (arg(6) = '7') then + index := 7; + elsif (arg(6) = '8') then + index := 8; + else index := 9; + end if; + + return index; + end extract_cntr_index; + + function output_cntr_num (arg:string) return string is + variable str : string(1 to 6) := "unused"; + begin + if (arg = "c0") then + str := " clk0"; + elsif (arg = "c1") then + str := " clk1"; + elsif (arg = "c2") then + str := " clk2"; + elsif (arg = "c3") then + str := " clk3"; + elsif (arg = "c4") then + str := " clk4"; + elsif (arg = "c5") then + str := " clk5"; + elsif (arg = "c6") then + str := " clk6"; + elsif (arg = "c7") then + str := " clk7"; + elsif (arg = "c8") then + str := " clk8"; + elsif (arg = "c9") then + str := " clk9"; + else str := "unused"; + end if; + return str; + end output_cntr_num; + + begin + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val <= i_c_ph; + END IF; + + if (init) then + if (m = 0) then + clk9_cntr := " c9"; + clk8_cntr := " c8"; + clk7_cntr := " c7"; + clk6_cntr := " c6"; + clk5_cntr := " c5"; + clk4_cntr := " c4"; + clk3_cntr := " c3"; + clk2_cntr := " c2"; + clk1_cntr := " c1"; + clk0_cntr := " c0"; + else + clk9_cntr := extract_cntr_string(clk9_counter); + clk8_cntr := extract_cntr_string(clk8_counter); + clk7_cntr := extract_cntr_string(clk7_counter); + clk6_cntr := extract_cntr_string(clk6_counter); + clk5_cntr := extract_cntr_string(clk5_counter); + clk4_cntr := extract_cntr_string(clk4_counter); + clk3_cntr := extract_cntr_string(clk3_counter); + clk2_cntr := extract_cntr_string(clk2_counter); + clk1_cntr := extract_cntr_string(clk1_counter); + clk0_cntr := extract_cntr_string(clk0_counter); + end if; + + clk_num(9) <= output_cntr_num(clk9_counter); + clk_num(8) <= output_cntr_num(clk8_counter); + clk_num(7) <= output_cntr_num(clk7_counter); + clk_num(6) <= output_cntr_num(clk6_counter); + clk_num(5) <= output_cntr_num(clk5_counter); + clk_num(4) <= output_cntr_num(clk4_counter); + clk_num(3) <= output_cntr_num(clk3_counter); + clk_num(2) <= output_cntr_num(clk2_counter); + clk_num(1) <= output_cntr_num(clk1_counter); + clk_num(0) <= output_cntr_num(clk0_counter); + + i_clk0_counter <= extract_cntr_index(clk0_cntr); + i_clk1_counter <= extract_cntr_index(clk1_cntr); + i_clk2_counter <= extract_cntr_index(clk2_cntr); + i_clk3_counter <= extract_cntr_index(clk3_cntr); + i_clk4_counter <= extract_cntr_index(clk4_cntr); + i_clk5_counter <= extract_cntr_index(clk5_cntr); + i_clk6_counter <= extract_cntr_index(clk6_cntr); + i_clk7_counter <= extract_cntr_index(clk7_cntr); + i_clk8_counter <= extract_cntr_index(clk8_cntr); + i_clk9_counter <= extract_cntr_index(clk9_cntr); + + + if (m = 0) then -- convert user parameters to advanced + -- set the limit of the divide_by value that can be returned by + -- the following function. + max_d_value := 1500; + + -- scale down the multiply_by and divide_by values provided by the design + -- before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by, + max_d_value, i_clk5_mult_by, i_clk5_div_by); + find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by, + max_d_value, i_clk6_mult_by, i_clk6_div_by); + find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by, + max_d_value, i_clk7_mult_by, i_clk7_div_by); + find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by, + max_d_value, i_clk8_mult_by, i_clk8_div_by); + find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by, + max_d_value, i_clk9_mult_by, i_clk9_div_by); + + if (vco_frequency_control = "manual_phase") then + find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step, + i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + i_clk5_mult_by,i_clk6_mult_by, + i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by, + i_clk0_div_by, i_clk1_div_by, + i_clk2_div_by, i_clk3_div_by, + i_clk4_div_by, + i_clk5_div_by,i_clk6_div_by, + i_clk7_div_by,i_clk8_div_by,i_clk9_div_by, + clk0_counter, clk1_counter, + clk2_counter, clk3_counter, + clk4_counter, + clk5_counter,clk6_counter, + clk7_counter,clk8_counter,clk9_counter, + i_m, i_n); + elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then + i_n := vco_divide_by; + i_m := vco_multiply_by; + else + i_n := 1; + + if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then + i_m := i_clk0_mult_by; + else + i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + i_clk5_mult_by,i_clk6_mult_by, + i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by, + inclk0_input_frequency); + end if; + end if; + + if (pll_type = "flvds") then + -- Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier := clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; + i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; + i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; + else + i_clk0_phase_shift := str2int(clk0_phase_shift); + i_clk1_phase_shift := str2int(clk1_phase_shift); + i_clk2_phase_shift := str2int(clk2_phase_shift); + end if; + + max_neg_abs := maxnegabs(i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + str2int(clk5_phase_shift), + str2int(clk6_phase_shift), + str2int(clk7_phase_shift), + str2int(clk8_phase_shift), + str2int(clk9_phase_shift) + ); + i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); + + i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + + + i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by, + i_clk6_mult_by, i_m, i_n), clk6_duty_cycle); + + i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by, + i_clk7_mult_by, i_m, i_n), clk7_duty_cycle); + + i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by, + i_clk8_mult_by, i_m, i_n), clk8_duty_cycle); + + i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by, + i_clk9_mult_by, i_m, i_n), clk9_duty_cycle); + + i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by, + i_clk6_mult_by, i_m, i_n), clk6_duty_cycle); + i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by, + i_clk7_mult_by, i_m, i_n), clk7_duty_cycle); + i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by, + i_clk8_mult_by, i_m, i_n), clk8_duty_cycle); + i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by, + i_clk9_mult_by, i_m, i_n), clk9_duty_cycle); + + i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); + + i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n)); + i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n)); + i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n)); + i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n)); + i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n)); + + + + else -- m /= 0 + + i_n := n; + i_m := m; + i_m_initial := m_initial; + i_m_ph := m_ph; + i_c_ph(0) := c0_ph; + i_c_ph(1) := c1_ph; + i_c_ph(2) := c2_ph; + i_c_ph(3) := c3_ph; + i_c_ph(4) := c4_ph; + i_c_ph(5) := c5_ph; + i_c_ph(6) := c6_ph; + i_c_ph(7) := c7_ph; + i_c_ph(8) := c8_ph; + i_c_ph(9) := c9_ph; + i_c_high(0) := c0_high; + i_c_high(1) := c1_high; + i_c_high(2) := c2_high; + i_c_high(3) := c3_high; + i_c_high(4) := c4_high; + i_c_high(5) := c5_high; + i_c_high(6) := c6_high; + i_c_high(7) := c7_high; + i_c_high(8) := c8_high; + i_c_high(9) := c9_high; + i_c_low(0) := c0_low; + i_c_low(1) := c1_low; + i_c_low(2) := c2_low; + i_c_low(3) := c3_low; + i_c_low(4) := c4_low; + i_c_low(5) := c5_low; + i_c_low(6) := c6_low; + i_c_low(7) := c7_low; + i_c_low(8) := c8_low; + i_c_low(9) := c9_low; + i_c_initial(0) := c0_initial; + i_c_initial(1) := c1_initial; + i_c_initial(2) := c2_initial; + i_c_initial(3) := c3_initial; + i_c_initial(4) := c4_initial; + i_c_initial(5) := c5_initial; + i_c_initial(6) := c6_initial; + i_c_initial(7) := c7_initial; + i_c_initial(8) := c8_initial; + i_c_initial(9) := c9_initial; + i_c_mode(0) := translate_string(c0_mode); + i_c_mode(1) := translate_string(c1_mode); + i_c_mode(2) := translate_string(c2_mode); + i_c_mode(3) := translate_string(c3_mode); + i_c_mode(4) := translate_string(c4_mode); + i_c_mode(5) := translate_string(c5_mode); + i_c_mode(6) := translate_string(c6_mode); + i_c_mode(7) := translate_string(c7_mode); + i_c_mode(8) := translate_string(c8_mode); + i_c_mode(9) := translate_string(c9_mode); + + end if; -- user to advanced conversion. + + m_initial_val <= i_m_initial; + n_val <= i_n; + m_val <= i_m; + + if (i_m = 1) then + m_mode_val <= "bypass"; + else + m_mode_val <= " "; + end if; + if (i_n = 1) then + n_mode_val <= "bypass"; + else + n_mode_val <= " "; + end if; + + m_ph_val <= i_m_ph; + m_ph_initial <= i_m_ph; + m_val_tmp := i_m; + + for i in 0 to 9 loop + if (i_c_mode(i) = "bypass") then + if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then + i_c_high(i) := 16; + i_c_low(i) := 16; + else + i_c_high(i) := 256; + i_c_low(i) := 256; + end if; + end if; + c_ph_val(i) <= i_c_ph(i); + c_initial_val(i) <= i_c_initial(i); + c_high_val(i) <= i_c_high(i); + c_low_val(i) <= i_c_low(i); + c_mode_val(i) <= i_c_mode(i); + c_high_val_tmp(i) := i_c_high(i); + c_hval(i) := i_c_high(i); + c_low_val_tmp(i) := i_c_low(i); + c_lval(i) := i_c_low(i); + c_mode_val_tmp(i) := i_c_mode(i); + c_ph_val_orig(i) <= i_c_ph(i); + c_high_val_hold(i) <= i_c_high(i); + c_low_val_hold(i) <= i_c_low(i); + c_mode_val_hold(i) <= i_c_mode(i); + end loop; + + + + if (pll_type = "fast" OR (pll_type = "left_right")) then + scan_chain_length := FAST_SCAN_CHAIN; + else + scan_chain_length := GPP_SCAN_CHAIN; + end if; + + + if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then + num_output_cntrs <= 7; + else + num_output_cntrs <= 10; + end if; + + init := false; + elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then + c0_rising_edge_transfer_done := false; + c1_rising_edge_transfer_done := false; + c2_rising_edge_transfer_done := false; + c3_rising_edge_transfer_done := false; + c4_rising_edge_transfer_done := false; + c5_rising_edge_transfer_done := false; + c6_rising_edge_transfer_done := false; + c7_rising_edge_transfer_done := false; + c8_rising_edge_transfer_done := false; + c9_rising_edge_transfer_done := false; + update_conf_latches_reg <= '0'; + elsif (update_conf_latches'event and update_conf_latches = '1') then + initiate_reconfig <= '1'; + elsif (areset_ipd'event AND areset_ipd = '1') then + if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if; + elsif (scanclk_ipd'event and scanclk_ipd = '1') then + IF (initiate_reconfig = '1') THEN + initiate_reconfig <= '0'; + ASSERT false REPORT "PLL Reprogramming Initiated" severity note; + + update_conf_latches_reg <= update_conf_latches; + reconfig_err <= false; + scandone_tmp <= '0'; + cp_curr_old <= cp_curr_val; + lfc_old <= lfc_val; + lfr_old <= lfr_val; + vco_old <= vco_cur; + -- LF unused : bit 0,1 + -- LF Capacitance : bits 2,3 : all values are legal + buf_scan_data := scan_data(2 TO 3); + + IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN + lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + ELSE + lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + END IF; + -- LF Resistance : bits 4-8 + -- valid values - 00000,00100,10000,10100,11000,11011,11100,11110 + IF (scan_data(4 TO 8) = "00000") THEN + lfr_val <= "20"; + ELSIF (scan_data(4 TO 8) = "00100") THEN + lfr_val <= "16"; + ELSIF (scan_data(4 TO 8) = "10000") THEN + lfr_val <= "12"; + ELSIF (scan_data(4 TO 8) = "10100") THEN + lfr_val <= "08"; + ELSIF (scan_data(4 TO 8) = "11000") THEN + lfr_val <= "06"; + ELSIF (scan_data(4 TO 8) = "11011") THEN + lfr_val <= "04"; + ELSIF (scan_data(4 TO 8) = "11100") THEN + lfr_val <= "02"; + ELSE + lfr_val <= "01"; + END IF; + + + -- VCO post scale assignment + if (scan_data(9) = '1') then -- vco_post_scale = 1 + i_vco_max <= VCO_MAX_NO_DIVISION/2; + i_vco_min <= VCO_MIN_NO_DIVISION/2; + vco_cur <= 1; + else + i_vco_max <= vco_max; + i_vco_min <= vco_min; + vco_cur <= 2; + end if; + -- CP + -- Bit 9 : CRBYPASS + -- Bit 10-14 : unused + -- Bits 15-17 : all values are legal + + buf_scan_data_2 := scan_data(15 TO 17); + cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2)); + -- save old values for display info. + + cp_curr_val_bit_setting <= scan_data(15 TO 17); + lfc_val_bit_setting <= scan_data(2 TO 3); + lfr_val_bit_setting <= scan_data(4 TO 8); + + m_val_old <= m_val; + n_val_old <= n_val; + m_mode_val_old <= m_mode_val; + n_mode_val_old <= n_mode_val; + WHILE (i < num_output_cntrs) LOOP + c_high_val_old(i) <= c_high_val(i); + c_low_val_old(i) <= c_low_val(i); + c_mode_val_old(i) <= c_mode_val(i); + i := i + 1; + END LOOP; + -- M counter + -- 1. Mode - bypass (bit 18) + + IF (scan_data(18) = '1') THEN + m_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 27) + ELSIF (scan_data(27) = '1') THEN + m_mode_val <= " odd"; + ELSE + m_mode_val <= " even"; + END IF; + + -- 2. High (bit 19-26) + + m_hi := scan_data(19 TO 26); + + -- 4. Low (bit 28-35) + + m_lo := scan_data(28 TO 35); + -- N counter + -- 1. Mode - bypass (bit 36) + + IF (scan_data(36) = '1') THEN + n_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 45) + ELSIF (scan_data(45) = '1') THEN + n_mode_val <= " odd"; + ELSE + n_mode_val <= " even"; + END IF; + + -- 2. High (bit 37-44) + + n_hi := scan_data(37 TO 44); + + -- 4. Low (bit 46-53) + + n_lo := scan_data(46 TO 53); + -- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low + + i := 0; + WHILE (i < num_output_cntrs) LOOP + -- 1. Mode - bypass + + IF (scan_data(54 + i * 18 + 0) = '1') THEN + c_mode_val_tmp(i) := "bypass"; + -- 3. Mode - odd/even + ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN + c_mode_val_tmp(i) := " odd"; + ELSE + c_mode_val_tmp(i) := " even"; + END IF; + -- 2. Hi + + high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8); + c_hval(i) := alt_conv_integer(high); + IF (c_hval(i) /= 0) THEN + c_high_val_tmp(i) := c_hval(i); + ELSE + c_high_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + + -- 4. Low + + low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17); + c_lval(i) := alt_conv_integer(low); + IF (c_lval(i) /= 0) THEN + c_low_val_tmp(i) := c_lval(i); + ELSE + c_low_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + i := i + 1; + END LOOP; + -- Legality Checks + + -- M counter value + IF(scan_data(18) /= '1') THEN + IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (m_hi /= "00000000") THEN + m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo); + ELSE + m_val_tmp := alt_conv_integer("000000001"); + END IF; + ELSE + m_val_tmp := alt_conv_integer("10000000"); + END IF; + -- N counter value + IF(scan_data(36) /= '1') THEN + IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (n_hi /= "00000000") THEN + n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo); + ELSE + n_val <= alt_conv_integer("000000001"); + END IF; + ELSE + n_val <= alt_conv_integer("10000000"); + END IF; + -- TODO : Give warnings/errors in the following cases? + -- 1. Illegal counter values (error) + -- 2. Change of mode (warning) + -- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0) + + END IF; + end if; + + + if (fbclk'event and fbclk = '1') then + m_val <= m_val_tmp; + end if; + + if (update_conf_latches_reg = '1') then + if (scanclk_ipd'event and scanclk_ipd = '1') then + c0_rising_edge_transfer_done := true; + c_high_val(0) <= c_high_val_tmp(0); + c_mode_val(0) <= c_mode_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c1_rising_edge_transfer_done := true; + c_high_val(1) <= c_high_val_tmp(1); + c_mode_val(1) <= c_mode_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c2_rising_edge_transfer_done := true; + c_high_val(2) <= c_high_val_tmp(2); + c_mode_val(2) <= c_mode_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(3) <= c_high_val_tmp(3); + c_mode_val(3) <= c_mode_val_tmp(3); + c3_rising_edge_transfer_done := true; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(4) <= c_high_val_tmp(4); + c_mode_val(4) <= c_mode_val_tmp(4); + c4_rising_edge_transfer_done := true; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(5) <= c_high_val_tmp(5); + c_mode_val(5) <= c_mode_val_tmp(5); + c5_rising_edge_transfer_done := true; + end if; + + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(6) <= c_high_val_tmp(6); + c_mode_val(6) <= c_mode_val_tmp(6); + c6_rising_edge_transfer_done := true; + end if; + + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(7) <= c_high_val_tmp(7); + c_mode_val(7) <= c_mode_val_tmp(7); + c7_rising_edge_transfer_done := true; + end if; + + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(8) <= c_high_val_tmp(8); + c_mode_val(8) <= c_mode_val_tmp(8); + c8_rising_edge_transfer_done := true; + end if; + + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(9) <= c_high_val_tmp(9); + c_mode_val(9) <= c_mode_val_tmp(9); + c9_rising_edge_transfer_done := true; + end if; + + end if; + + if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then + c_low_val(0) <= c_low_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then + c_low_val(1) <= c_low_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then + c_low_val(2) <= c_low_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then + c_low_val(3) <= c_low_val_tmp(3); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then + c_low_val(4) <= c_low_val_tmp(4); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then + c_low_val(5) <= c_low_val_tmp(5); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then + c_low_val(6) <= c_low_val_tmp(6); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then + c_low_val(7) <= c_low_val_tmp(7); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then + c_low_val(8) <= c_low_val_tmp(8); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then + c_low_val(9) <= c_low_val_tmp(9); + end if; + + if (update_phase = '1') then + if (vco_out(0)'event and vco_out(0) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 0) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 0) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(1)'event and vco_out(1) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 1) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 1) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(2)'event and vco_out(2) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 2) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 2) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(3)'event and vco_out(3) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 3) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 3) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(4)'event and vco_out(4) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 4) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 4) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(5)'event and vco_out(5) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 5) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 5) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(6)'event and vco_out(6) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 6) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 6) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(7)'event and vco_out(7) = '0') then + for i in 0 to 9 loop + if (c_ph_val(i) = 7) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 7) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + end if; + + + + if (vco_out(0)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 0) then + inclk_c_from_vco(i) <= vco_out(0); + end if; + end loop; + if (m_ph_val = 0) then + inclk_m_from_vco <= vco_out(0); + end if; + end if; + if (vco_out(1)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 1) then + inclk_c_from_vco(i) <= vco_out(1); + end if; + end loop; + if (m_ph_val = 1) then + inclk_m_from_vco <= vco_out(1); + end if; + end if; + if (vco_out(2)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 2) then + inclk_c_from_vco(i) <= vco_out(2); + end if; + end loop; + if (m_ph_val = 2) then + inclk_m_from_vco <= vco_out(2); + end if; + end if; + if (vco_out(3)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 3) then + inclk_c_from_vco(i) <= vco_out(3); + end if; + end loop; + if (m_ph_val = 3) then + inclk_m_from_vco <= vco_out(3); + end if; + end if; + if (vco_out(4)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 4) then + inclk_c_from_vco(i) <= vco_out(4); + end if; + end loop; + if (m_ph_val = 4) then + inclk_m_from_vco <= vco_out(4); + end if; + end if; + if (vco_out(5)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 5) then + inclk_c_from_vco(i) <= vco_out(5); + end if; + end loop; + if (m_ph_val = 5) then + inclk_m_from_vco <= vco_out(5); + end if; + end if; + if (vco_out(6)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 6) then + inclk_c_from_vco(i) <= vco_out(6); + end if; + end loop; + if (m_ph_val = 6) then + inclk_m_from_vco <= vco_out(6); + end if; + end if; + if (vco_out(7)'event) then + for i in 0 to 9 loop + if (c_ph_val(i) = 7) then + inclk_c_from_vco(i) <= vco_out(7); + end if; + end loop; + if (m_ph_val = 7) then + inclk_m_from_vco <= vco_out(7); + end if; + end if; + + + + + if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then + scanclkena_reg <= scanclkena_ipd; + if (scanclkena_reg = '1') then + scandata_in <= scandata_ipd; + scandata_out <= scandataout_tmp; + end if; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then + if (got_first_scanclk) then + scanclk_period <= now - scanclk_last_rising_edge; + else + got_first_scanclk := true; + end if; + if (scanclkena_reg = '1') then + for j in scan_chain_length - 1 downto 1 loop + scan_data(j) <= scan_data(j-1); + end loop; + scan_data(0) <= scandata_in; + end if; + scanclk_last_rising_edge := now; + end if; + end process; + +-- PLL Phase Reconfiguration + +PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd) + VARIABLE i : INTEGER := 0; + VARIABLE c_ph : INTEGER := 0; + VARIABLE m_ph : INTEGER := 0; + VARIABLE select_counter : INTEGER := 0; +BEGIN + IF (NOW = 0 ps) THEN + m_ph_val_tmp <= m_ph_initial; + END IF; + + -- Latch phase enable (same as phasestep) on neg edge of scan clock + IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN + phasestep_reg <= phasestep_ipd; + END IF; + + IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN + IF (update_phase = '0') THEN + phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart + -- if not, next phasestep cycle is skipped + END IF; + END IF; + -- revert counter phase tap values to POF programmed values + -- if PLL is reset + + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val_tmp <= c_ph_val_orig; + m_ph_val_tmp <= m_ph_initial; + END IF; + + IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN + IF (phasestep_reg = '1') THEN + IF (phasestep_high_count = 1) THEN + phasecounterselect_reg <= phasecounterselect_ipd; + phaseupdown_reg <= phaseupdown_ipd; + -- start reconfiguration + IF (phasecounterselect_ipd < "1100") THEN -- no counters selected + IF (phasecounterselect_ipd = "0000") THEN + i := 0; + WHILE (i < num_output_cntrs) LOOP + c_ph := c_ph_val(i); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(i) <= c_ph; + i := i + 1; + END LOOP; + ELSIF (phasecounterselect_ipd = "0001") THEN + m_ph := m_ph_val; + IF (phaseupdown_ipd = '1') THEN + m_ph := (m_ph + 1) mod num_phase_taps; + ELSIF (m_ph = 0) THEN + m_ph := num_phase_taps - 1; + ELSE + m_ph := (m_ph - 1) mod num_phase_taps; + END IF; + m_ph_val_tmp <= m_ph; + ELSE + select_counter := alt_conv_integer(phasecounterselect_ipd) - 2; + c_ph := c_ph_val(select_counter); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(select_counter) <= c_ph; + END IF; + update_phase <= '1','0' AFTER (0.5 * scanclk_period); + END IF; + END IF; + phasestep_high_count <= phasestep_high_count + 1; + + END IF; + END IF; +END PROCESS; + + scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2); + + process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk) + variable sched_time : time := 0 ps; + + TYPE time_array is ARRAY (0 to 7) of time; + variable init : boolean := true; + variable refclk_period : time; + variable m_times_vco_period : time; + variable new_m_times_vco_period : time; + + variable phase_shift : time_array := (OTHERS => 0 ps); + variable last_phase_shift : time_array := (OTHERS => 0 ps); + + variable l_index : integer := 1; + variable cycle_to_adjust : integer := 0; + + variable stop_vco : boolean := false; + + variable locked_tmp : std_logic := '0'; + variable pll_is_locked : boolean := false; + variable cycles_pfd_low : integer := 0; + variable cycles_pfd_high : integer := 0; + variable cycles_to_lock : integer := 0; + variable cycles_to_unlock : integer := 0; + + variable got_first_refclk : boolean := false; + variable got_second_refclk : boolean := false; + variable got_first_fbclk : boolean := false; + + variable refclk_time : time := 0 ps; + variable fbclk_time : time := 0 ps; + variable first_fbclk_time : time := 0 ps; + + variable fbclk_period : time := 0 ps; + + variable first_schedule : boolean := true; + + variable vco_val : std_logic := '0'; + variable vco_period_was_phase_adjusted : boolean := false; + variable phase_adjust_was_scheduled : boolean := false; + + variable loop_xplier : integer; + variable loop_initial : integer := 0; + variable loop_ph : integer := 0; + variable loop_time_delay : integer := 0; + + variable initial_delay : time := 0 ps; + variable vco_per : time; + variable tmp_rem : integer; + variable my_rem : integer; + variable fbk_phase : integer := 0; + + variable pull_back_M : integer := 0; + variable total_pull_back : integer := 0; + variable fbk_delay : integer := 0; + + variable offset : time := 0 ps; + + variable tmp_vco_per : integer := 0; + variable high_time : time; + variable low_time : time; + + variable got_refclk_posedge : boolean := false; + variable got_fbclk_posedge : boolean := false; + variable inclk_out_of_range : boolean := false; + variable no_warn : boolean := false; + + variable ext_fbk_cntr_modulus : integer := 1; + variable init_clks : boolean := true; + variable pll_is_in_reset : boolean := false; + variable buf : line; + begin + if (init) then + + -- jump-start the VCO + -- add 1 ps delay to ensure all signals are updated to initial + -- values + schedule_vco <= transport not schedule_vco after 1 ps; + + init := false; + end if; + + if (schedule_vco'event) then + if (init_clks) then + refclk_period := inclk0_input_frequency * n_val * 1 ps; + + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + init_clks := false; + end if; + sched_time := 0 ps; + for i in 0 to 7 loop + last_phase_shift(i) := phase_shift(i); + end loop; + cycle_to_adjust := 0; + l_index := 1; + m_times_vco_period := new_m_times_vco_period; + end if; + + -- areset was asserted + if (areset_ipd'event and areset_ipd = '1') then + assert false report family_name & " PLL was reset" severity note; + -- reset lock parameters + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + end if; + + if (areset_ipd = '1') then + pll_is_in_reset := true; + got_first_refclk := false; + got_second_refclk := false; + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after 1 ps; + end loop; + end if; + + + if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after last_phase_shift(i); + phase_shift(i) := 0 ps; + last_phase_shift(i) := 0 ps; + end loop; + + -- reset lock parameters + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + + got_first_refclk := false; + got_second_refclk := false; + refclk_time := 0 ps; + got_first_fbclk := false; + fbclk_time := 0 ps; + first_fbclk_time := 0 ps; + fbclk_period := 0 ps; + + first_schedule := true; + vco_val := '0'; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + + elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then + + -- note areset deassert time + -- note it as refclk_time to prevent false triggering + -- of stop_vco after areset + if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then + refclk_time := now; + locked_tmp := '0'; + end if; + + pll_is_in_reset := false; + -- calculate loop_xplier : this will be different from m_val + -- in external_feedback_mode + loop_xplier := m_val; + loop_initial := m_initial_val - 1; + loop_ph := m_ph_val; + + + -- convert initial value to delay + initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; + + -- convert loop ph_tap to delay + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier; + if (my_rem /= 0) then + tmp_vco_per := tmp_vco_per + 1; + end if; + fbk_phase := (loop_ph * tmp_vco_per)/8; + + pull_back_M := initial_delay/1 ps + fbk_phase; + + total_pull_back := pull_back_M; + + if (simulation_type = "timing") then + total_pull_back := total_pull_back + pll_compensation_delay; + end if; + while (total_pull_back > refclk_period/1 ps) loop + total_pull_back := total_pull_back - refclk_period/1 ps; + end loop; + + if (total_pull_back > 0) then + offset := refclk_period - (total_pull_back * 1 ps); + end if; + + fbk_delay := total_pull_back - fbk_phase; + if (fbk_delay < 0) then + offset := offset - (fbk_phase * 1 ps); + fbk_delay := total_pull_back; + end if; + + -- assign m_delay + m_delay <= transport fbk_delay after 1 ps; + + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + for i in 1 to loop_xplier loop + -- adjust cycles + tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier; + if (my_rem /= 0 and l_index <= my_rem) then + tmp_rem := (loop_xplier * l_index) rem my_rem; + cycle_to_adjust := (loop_xplier * l_index) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + if (cycle_to_adjust = i) then + tmp_vco_per := tmp_vco_per + 1; + l_index := l_index + 1; + end if; + + -- calculate high and low periods + vco_per := tmp_vco_per * 1 ps; + high_time := (tmp_vco_per/2) * 1 ps; + if (tmp_vco_per rem 2 /= 0) then + high_time := high_time + 1 ps; + end if; + low_time := vco_per - high_time; + + -- schedule the rising and falling edges + for j in 1 to 2 loop + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + if (first_schedule) then + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + else + vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k)); + end if; + end loop; + end loop; + end loop; + + -- schedule once more + if (first_schedule) then + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + end loop; + first_schedule := false; + end if; + + schedule_vco <= transport not schedule_vco after sched_time; + + if (vco_period_was_phase_adjusted) then + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := true; + + vco_per := m_times_vco_period/loop_xplier; + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + end loop; + end if; + end if; +-- Bypass lock detect + +if (refclk'event and refclk = '1' and areset_ipd = '0') then + if (test_bypass_lock_detect = "on") then + if (pfdena_ipd = '1') then + cycles_pfd_low := 0; + if (pfd_locked = '0') then + if (cycles_pfd_high = lock_high) then + assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning; + pfd_locked <= '1'; + end if; + cycles_pfd_high := cycles_pfd_high + 1; + end if; + end if; + + if (pfdena_ipd = '0') then + cycles_pfd_high := 0; + if (pfd_locked = '1') then + if (cycles_pfd_low = lock_low) then + assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning; + pfd_locked <= '0'; + end if; + cycles_pfd_low := cycles_pfd_low + 1; + end if; + end if; + end if; + + + if (refclk'event and refclk = '1' and areset_ipd = '0') then + got_refclk_posedge := true; + if (not got_first_refclk) then + got_first_refclk := true; + else + got_second_refclk := true; + refclk_period := now - refclk_time; + + -- check if incoming freq. will cause VCO range to be + -- exceeded + if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and + (((refclk_period/1 ps)/loop_xplier > i_vco_max) or + ((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then + if (pll_is_locked) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + if (inclk_out_of_range) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + end if; + elsif (not no_warn) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning; + no_warn := true; + end if; + inclk_out_of_range := true; + else + vco_over <= '0'; + vco_under <= '0'; + inclk_out_of_range := false; + no_warn := false; + end if; + end if; + end if; + + if (stop_vco) then + stop_vco := false; + schedule_vco <= not schedule_vco; + end if; + + refclk_time := now; + else + got_refclk_posedge := false; + end if; + +-- Update M counter value on feedback clock edge + + if (fbclk'event and fbclk = '1') then + got_fbclk_posedge := true; + if (not got_first_fbclk) then + got_first_fbclk := true; + else + fbclk_period := now - fbclk_time; + end if; + + -- need refclk_period here, so initialized to proper value above + if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or + ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or + ( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then + stop_vco := true; + -- reset + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + if (pll_is_locked) then + pll_is_locked := false; + locked_tmp := '0'; + assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note; + if ((i_vco_max = 0) and (i_vco_min = 0)) then + assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note; + end if; + end if; + cycles_to_lock := 0; + cycles_to_unlock := 0; + first_schedule := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + fbclk_time := now; + else + got_fbclk_posedge := false; + end if; + + if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then + + -- now we know actual incoming period + if ( abs(fbclk_time - refclk_time) <= 5 ps or + (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + -- considered in phase + if (cycles_to_lock = real_lock_high) then + if (not pll_is_locked) then + assert false report family_name & " PLL locked to incoming clock" severity note; + end if; + pll_is_locked := true; + locked_tmp := '1'; + cycles_to_unlock := 0; + end if; + -- increment lock counter only if second part of above + -- time check is NOT true + if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then + cycles_to_lock := cycles_to_lock + 1; + end if; + + -- adjust m_times_vco_period + new_m_times_vco_period := refclk_period; + else + -- if locked, begin unlock + if (pll_is_locked) then + cycles_to_unlock := cycles_to_unlock + 1; + if (cycles_to_unlock = lock_low) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + end if; + end if; + if ( abs(refclk_period - fbclk_period) <= 2 ps ) then + -- frequency is still good + if (now = fbclk_time and (not phase_adjust_was_scheduled)) then + if ( abs(fbclk_time - refclk_time) > refclk_period/2) then + new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted := true; + else + new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted := true; + end if; + + end if; + else + phase_adjust_was_scheduled := false; + new_m_times_vco_period := refclk_period; + end if; + end if; + end if; + + if (pfdena_ipd = '0') then + if (pll_is_locked) then + locked_tmp := 'X'; + end if; + pll_is_locked := false; + cycles_to_lock := 0; + end if; + + -- give message only at time of deassertion + if (pfdena_ipd'event and pfdena_ipd = '0') then + assert false report "PFDENA deasserted." severity note; + elsif (pfdena_ipd'event and pfdena_ipd = '1') then + got_first_refclk := false; + got_second_refclk := false; + refclk_time := now; + end if; + + if (reconfig_err) then + lock <= '0'; + else + lock <= locked_tmp; + end if; + + -- signal to calculate quiet_time + sig_refclk_period <= refclk_period; + + if (stop_vco = true) then + sig_stop_vco <= '1'; + else + sig_stop_vco <= '0'; + end if; + + pll_locked <= pll_is_locked; + end process; + + clk0_tmp <= c_clk(i_clk0_counter); + clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE + clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else + 'X'; + + clk1_tmp <= c_clk(i_clk1_counter); + clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE + clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk2_tmp <= c_clk(i_clk2_counter); + clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE + clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk3_tmp <= c_clk(i_clk3_counter); + clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE + clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk4_tmp <= c_clk(i_clk4_counter); + clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE + clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk5_tmp <= c_clk(i_clk5_counter); + clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE + clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + + clk6_tmp <= c_clk(i_clk6_counter); + clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE + clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + + clk7_tmp <= c_clk(i_clk7_counter); + clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE + clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + + clk8_tmp <= c_clk(i_clk8_counter); + clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE + clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + + clk9_tmp <= c_clk(i_clk9_counter); + clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE + clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + + +scandataout <= scandata_out; +scandone <= NOT scandone_tmp; +phasedone <= NOT update_phase; +vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over; +vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under; +fbout <= fbclk; +end vital_pll; +-- END ARCHITECTURE VITAL_PLL + +-- cycloneiii_msg +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_cda_mn_cntr +-- +-- Description : Simulation model for the M and N counter. This is a +-- common model for the input counter and the loop feedback +-- counter of the CycloneIII PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; + +ENTITY MF_cda_mn_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END MF_cda_mn_cntr; + +ARCHITECTURE behave of MF_cda_mn_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_cda_scale_cntr +-- +-- Description : Simulation model for the output scale-down counters. +-- This is a common model for the C0, C1, C2, C3, C4 and C5 +-- output counters of the StratixII PLL. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY MF_cda_scale_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0; + cout : OUT std_logic + ); +END MF_cda_scale_cntr; + +ARCHITECTURE behave of MF_cda_scale_cntr is +begin + process (clk, reset) + variable tmp_cout : std_logic := '0'; + variable count : integer := 1; + variable output_shift_count : integer := 1; + variable first_rising_edge : boolean := false; + begin + if (reset = '1') then + count := 1; + output_shift_count := 1; + tmp_cout := '0'; + first_rising_edge := false; + elsif (clk'event) then + if (mode = " off") then + tmp_cout := '0'; + elsif (mode = "bypass") then + tmp_cout := clk; + first_rising_edge := true; + elsif (not first_rising_edge) then + if (clk = '1') then + if (output_shift_count = initial) then + tmp_cout := clk; + first_rising_edge := true; + else + output_shift_count := output_shift_count + 1; + end if; + end if; + elsif (output_shift_count < initial) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + end if; + else + count := count + 1; + if (mode = " even" and (count = (high*2) + 1)) then + tmp_cout := '0'; + elsif (mode = " odd" and (count = high*2)) then + tmp_cout := '0'; + elsif (count = (high + low)*2 + 1) then + tmp_cout := '1'; + count := 1; -- reset count + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; + +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_cycloneiii_pll +-- +-- Description : Simulation model for the StratixII PLL. +-- In the functional mode, it is also the model for the altpll +-- megafunction. +-- +-- Limitations : Does not support Spread Spectrum and Bandwidth. +-- +-- Outputs : Up to 10 output clocks, each defined by its own set of +-- parameters. Locked output (active high) indicates when the +-- PLL locks. clkbad and activeclock are used for +-- clock switchover to indicate which input clock has gone +-- bad, when the clock switchover initiates and which input +-- clock is being used as the reference, respectively. +-- scandataout is the data output of the serial scan chain. +-- +--/////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE STD.TEXTIO.all; +USE work.MF_pllpack.all; +USE work.MF_cda_mn_cntr; +USE work.MF_cda_scale_cntr; +USE work.dffp; +USE work.MF_pll_reg; + +-- New Features : The list below outlines key new features in TITAN: +-- 1. Dynamic Phase Reconfiguration +-- 2. Dynamic PLL Reconfiguration (different protocol) +-- 3. More output counters + +ENTITY MF_cycloneiii_pll is + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM + compensate_clock : string := "clock0"; + + inclk0_input_frequency : integer := 0; + inclk1_input_frequency : integer := 0; + + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + + + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + use_dc_coupling : string := "false"; + + + + lock_c : integer := 4; + sim_gate_lock_device_behavior : string := "off"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_window : time := 5 ps; + test_bypass_lock_detect : string := "off"; + + + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 0; + clk0_divide_by : integer := 0; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 0; + clk1_divide_by : integer := 0; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 0; + clk2_divide_by : integer := 0; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 0; + clk3_divide_by : integer := 0; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 0; + clk4_divide_by : integer := 0; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + + + + + + + + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + + -- ADVANCED USER PARAMETERS + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + + + + + + m_ph : integer := 0; + + clk0_counter : string := "unused"; + clk1_counter : string := "unused"; + clk2_counter : string := "unused"; + clk3_counter : string := "unused"; + clk4_counter : string := "unused"; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + vco_post_scale : integer := 1; + vco_frequency_control : string := "auto"; + vco_phase_shift_step : integer := 0; + + charge_pump_current : integer := 10; + loop_filter_r : string := " 1.0"; + loop_filter_c : integer := 0; + + + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + +-- Test only + init_block_reset_a_count : integer := 1; + init_block_reset_b_count : integer := 1; + charge_pump_current_bits : integer := 0; + lock_window_ui_bits : integer := 0; + loop_filter_c_bits : integer := 0; + loop_filter_r_bits : integer := 0; + test_counter_c0_delay_chain_bits : integer := 0; + test_counter_c1_delay_chain_bits : integer := 0; + test_counter_c2_delay_chain_bits : integer := 0; + test_counter_c3_delay_chain_bits : integer := 0; + test_counter_c4_delay_chain_bits : integer := 0; + test_counter_c5_delay_chain_bits : integer := 0; + test_counter_m_delay_chain_bits : integer := 0; + test_counter_n_delay_chain_bits : integer := 0; + test_feedback_comp_delay_chain_bits : integer := 0; + test_input_comp_delay_chain_bits : integer := 0; + test_volt_reg_output_mode_bits : integer := 0; + test_volt_reg_output_voltage_bits : integer := 0; + test_volt_reg_test_mode : string := "false"; + vco_range_detector_high_bits : integer := -1; + vco_range_detector_low_bits : integer := -1; + scan_chain_mif_file : string := ""; + + auto_settings : string := "true"; +-- Simulation only generics + family_name : string := "StratixIII"; + + use_vco_bypass : string := "false" + ); + + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + fbout : out std_logic; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + clk : out std_logic_vector(4 downto 0); + phasecounterselect : in std_logic_vector(2 downto 0) := "000"; + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic + + ); +END MF_cycloneiii_pll; + +ARCHITECTURE vital_pll of MF_cycloneiii_pll is + +function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is +begin + if (i_vco_post_scale = 1) then + return vco_min * 2; + else + return vco_min; + end if; +end; + +function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is +begin + if (i_vco_post_scale = 1) then + return vco_max * 2; + else + return vco_max; + end if; +end; + +TYPE int_array is ARRAY(NATURAL RANGE <>) of integer; +TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6); +TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9); +TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic; + +constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale); +constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale); + +-- internal advanced parameter signals +signal i_vco_min : integer := vco_min; +signal i_vco_max : integer := vco_max; +signal i_vco_center : integer; +signal i_pfd_min : integer; +signal i_pfd_max : integer; + signal c_ph_val : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_high_val : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val : int_array(0 to 4) := (OTHERS => 1); + signal c_initial_val : int_array(0 to 4) := (OTHERS => 1); + signal c_mode_val : str_array(0 to 4); + signal clk_num : str_array(0 to 4); + +-- old values + signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_old : str_array(0 to 4); +-- hold registers + signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_hold : str_array(0 to 4); + +-- temp registers + signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0); + +signal real_lock_high : integer := 0; +signal i_clk4_counter : integer := 4; +signal i_clk3_counter : integer := 3; +signal i_clk2_counter : integer := 2; +signal i_clk1_counter : integer := 1; +signal i_clk0_counter : integer := 0; +signal i_charge_pump_current : integer; +signal i_loop_filter_r : integer; + +-- end internal advanced parameter signals + +-- CONSTANTS +CONSTANT SCAN_CHAIN : integer := 144; +CONSTANT GPP_SCAN_CHAIN : integer := 234; +CONSTANT FAST_SCAN_CHAIN : integer := 180; + CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0"); +CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2"); + +CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + +CONSTANT num_phase_taps : integer := 8; +-- signals + +signal vcc : std_logic := '1'; + +signal fbclk : std_logic; +signal refclk : std_logic; +signal vco_over : std_logic := '0'; +signal vco_under : std_logic := '1'; + +signal pll_locked : boolean := false; + + + signal c_clk : std_logic_array(0 to 4); +signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); + +-- signals to assign values to counter params +signal m_val : integer := 1; +signal n_val : integer := 1; +signal m_ph_val : integer := 0; +signal m_ph_initial : integer := 0; +signal m_ph_val_tmp : integer := 0; +signal m_initial_val : integer := m_initial; + +signal m_mode_val : string(1 to 6) := " "; +signal n_mode_val : string(1 to 6) := " "; +signal lfc_val : integer := 0; +signal vco_cur : integer := vco_post_scale; +signal cp_curr_val : integer := 0; +signal lfr_val : string(1 to 2) := " "; + +signal cp_curr_old_bit_setting : integer := charge_pump_current_bits; +signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0'); +signal lfr_old_bit_setting : integer := loop_filter_r_bits; +signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0'); +signal lfc_old_bit_setting : integer := loop_filter_c_bits; +signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0'); + +signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true +-- old values +signal m_val_old : integer := 1; +signal n_val_old : integer := 1; +signal m_mode_val_old : string(1 to 6) := " "; +signal n_mode_val_old : string(1 to 6) := " "; +signal m_ph_val_old : integer := 0; +signal lfc_old : integer := 0; +signal vco_old : integer := 0; +signal cp_curr_old : integer := 0; +signal lfr_old : string(1 to 2) := " "; + signal num_output_cntrs : integer := 5; +signal scanclk_period : time := 1 ps; + signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + + signal clk_pfd : std_logic_vector(0 to 4); +signal clk0_tmp : std_logic; +signal clk1_tmp : std_logic; +signal clk2_tmp : std_logic; +signal clk3_tmp : std_logic; +signal clk4_tmp : std_logic; + +signal update_conf_latches : std_logic := '0'; +signal update_conf_latches_reg : std_logic := '0'; + +signal clkin : std_logic := '0'; +signal gate_locked : std_logic := '0'; +signal pfd_locked : std_logic := '0'; +signal lock : std_logic := '0'; +signal about_to_lock : boolean := false; +signal reconfig_err : boolean := false; + +signal inclk_c0 : std_logic; +signal inclk_c1 : std_logic; +signal inclk_c2 : std_logic; +signal inclk_c3 : std_logic; +signal inclk_c4 : std_logic; +signal inclk_m : std_logic; +signal devpor : std_logic; +signal devclrn : std_logic; + +signal inclk0_ipd : std_logic; +signal inclk1_ipd : std_logic; +signal pfdena_ipd : std_logic; +signal areset_ipd : std_logic; +signal fbin_ipd : std_logic; +signal scanclk_ipd : std_logic; +signal scanclkena_ipd, scanclkena_reg : std_logic; +signal scandata_ipd : std_logic; +signal clkswitch_ipd : std_logic; + signal phasecounterselect_ipd : std_logic_vector(2 downto 0); +signal phaseupdown_ipd : std_logic; +signal phasestep_ipd : std_logic; +signal configupdate_ipd : std_logic; +-- registered signals + +signal sig_offset : time := 0 ps; +signal sig_refclk_time : time := 0 ps; +signal sig_fbclk_period : time := 0 ps; +signal sig_vco_period_was_phase_adjusted : boolean := false; +signal sig_phase_adjust_was_scheduled : boolean := false; +signal sig_stop_vco : std_logic := '0'; +signal sig_m_times_vco_period : time := 0 ps; +signal sig_new_m_times_vco_period : time := 0 ps; +signal sig_got_refclk_posedge : boolean := false; +signal sig_got_fbclk_posedge : boolean := false; +signal sig_got_second_refclk : boolean := false; + +signal m_delay : integer := 0; +signal n_delay : integer := 0; + +signal inclk1_tmp : std_logic := '0'; + + +signal reset_low : std_logic := '0'; + +-- Phase Reconfig + + SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0); + +SIGNAL phaseupdown_reg : std_logic := '0'; +SIGNAL phasestep_reg : std_logic := '0'; +SIGNAL phasestep_high_count : integer := 0; +SIGNAL update_phase : std_logic := '0'; + +signal scandataout_tmp : std_logic := '0'; +signal scandata_in : std_logic := '0'; +signal scandata_out : std_logic := '0'; +signal scandone_tmp : std_logic := '1'; +signal initiate_reconfig : std_logic := '0'; + +signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; + +signal schedule_vco : std_logic := '0'; + +signal areset_ena_sig : std_logic := '0'; +signal pll_in_test_mode : boolean := false; +signal pll_has_just_been_reconfigured : boolean := false; + + signal inclk_c_from_vco : std_logic_array(0 to 4); + +signal inclk_m_from_vco : std_logic; + +SIGNAL inclk0_period : time := 0 ps; +SIGNAL last_inclk0_period : time := 0 ps; +SIGNAL last_inclk0_edge : time := 0 ps; +SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0'; +SIGNAL inclk1_period : time := 0 ps; +SIGNAL last_inclk1_period : time := 0 ps; +SIGNAL last_inclk1_edge : time := 0 ps; +SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0'; + + + +COMPONENT MF_cda_mn_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END COMPONENT; + +COMPONENT MF_cda_scale_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0 + ); +END COMPONENT; + +COMPONENT dffp + + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +COMPONENT MF_pll_reg + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +begin + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + WireDelay : block + begin + inclk0_ipd <= inclk(0); + inclk1_ipd <= inclk(1); + areset_ipd <= areset; + pfdena_ipd <= pfdena; + scanclk_ipd <= scanclk; + scanclkena_ipd <= scanclkena; + scandata_ipd <= scandata; + configupdate_ipd <= configupdate; + clkswitch_ipd <= clkswitch; + phaseupdown_ipd <= phaseupdown; + phasestep_ipd <= phasestep; + phasecounterselect_ipd(0) <= phasecounterselect(0); + phasecounterselect_ipd(1) <= phasecounterselect(1); + phasecounterselect_ipd(2) <= phasecounterselect(2); + + end block; + +inclk_m <= fbclk when m_test_source = 0 else + refclk when m_test_source = 1 else + inclk_m_from_vco; + + areset_ena_sig <= areset_ipd or sig_stop_vco; + + + pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or + c1_test_source /= -1 or c2_test_source /= -1 or + c3_test_source /= -1 or c4_test_source /= -1) + else false; + + real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0; + m1 : MF_cda_mn_cntr + port map ( clk => inclk_m, + reset => areset_ena_sig, + cout => fbclk, + initial_value => m_initial_val, + modulus => m_val, + time_delay => m_delay + ); + + -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed + -- in different simulation deltas. + inclk1_tmp <= inclk1_ipd; + + -- Calculate the inclk0 period + PROCESS + VARIABLE inclk0_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1'); + IF (first_inclk0_edge_detect = '0') THEN + first_inclk0_edge_detect <= '1'; + ELSE + last_inclk0_period <= inclk0_period; + inclk0_period_tmp := NOW - last_inclk0_edge; + END IF; + last_inclk0_edge <= NOW; + inclk0_period <= inclk0_period_tmp; + END PROCESS; + + + -- Calculate the inclk1 period + PROCESS + VARIABLE inclk1_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1'); + IF (first_inclk1_edge_detect = '0') THEN + first_inclk1_edge_detect <= '1'; + ELSE + last_inclk1_period <= inclk1_period; + inclk1_period_tmp := NOW - last_inclk1_edge; + END IF; + last_inclk1_edge <= NOW; + inclk1_period <= inclk1_period_tmp; + END PROCESS; + + process (inclk0_ipd, inclk1_tmp, clkswitch_ipd) + variable input_value : std_logic := '0'; + variable current_clock : integer := 0; + variable clk0_count, clk1_count : integer := 0; + variable clk0_is_bad, clk1_is_bad : std_logic := '0'; + variable primary_clk_is_bad : boolean := false; + variable current_clk_is_bad : boolean := false; + variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; + variable switch_over_count : integer := 0; + variable active_clock : std_logic := '0'; + variable external_switch : boolean := false; + variable diff_percent_period : integer := 0; + variable buf : line; + variable switch_clock : boolean := false; + + begin + if (now = 0 ps) then + if (switch_over_type = "manual" and clkswitch_ipd = '1') then + current_clock := 1; + active_clock := '1'; + end if; + end if; + if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then + external_switch := true; + elsif (switch_over_type = "manual") then + if (clkswitch_ipd'event and clkswitch_ipd = '1') then + switch_clock := true; + elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then + switch_clock := false; + end if; + end if; + + if (switch_clock = true) then + if (inclk0_ipd'event or inclk1_tmp'event) then + if (current_clock = 0) then + current_clock := 1; + active_clock := '1'; + clkin <= transport inclk1_tmp; + elsif (current_clock = 1) then + current_clock := 0; + active_clock := '0'; + clkin <= transport inclk0_ipd; + end if; + switch_clock := false; + end if; + end if; + + -- save the current inclk event value + if (inclk0_ipd'event) then + input_value := inclk0_ipd; + elsif (inclk1_tmp'event) then + input_value := inclk1_tmp; + end if; + + -- check if either input clk is bad + if (inclk0_ipd'event and inclk0_ipd = '1') then + clk0_count := clk0_count + 1; + clk0_is_bad := '0'; + clk1_count := 0; + if (clk0_count > 2) then + -- no event on other clk for 2 cycles + clk1_is_bad := '1'; + if (current_clock = 1) then + current_clk_is_bad := true; + end if; + end if; + end if; + if (inclk1_tmp'event and inclk1_tmp = '1') then + clk1_count := clk1_count + 1; + clk1_is_bad := '0'; + clk0_count := 0; + if (clk1_count > 2) then + -- no event on other clk for 2 cycles + clk0_is_bad := '1'; + if (current_clock = 0) then + current_clk_is_bad := true; + end if; + end if; + end if; + + -- check if the bad clk is the primary clock + if (clk0_is_bad = '1') then + primary_clk_is_bad := true; + else + primary_clk_is_bad := false; + end if; + + -- actual switching + if (inclk0_ipd'event and current_clock = 0) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk0_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk0_ipd; + end if; + else + clkin <= transport inclk0_ipd; + end if; + elsif (inclk1_tmp'event and current_clock = 1) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk1_tmp = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk1_tmp; + end if; + else + clkin <= transport inclk1_tmp; + end if; + else + if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then + switch_over_count := switch_over_count + 1; + end if; + if ((input_value = '0')) then + if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then + got_curr_clk_falling_edge_after_clkswitch := false; + + if (areset_ipd = '0') then + if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then + diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period; + elsif (inclk0_period /= 0 ps) then + diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period; + end if; + + if((diff_percent_period > 20)and ( switch_over_type = "auto")) then + WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.")); + writeline(output, buf); + end if; + end if; + + if (current_clock = 0) then + current_clock := 1; + else + current_clock := 0; + end if; + active_clock := not active_clock; + switch_over_count := 0; + external_switch := false; + current_clk_is_bad := false; + else + if(switch_over_type = "auto") then + if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then + current_clock := 1; + active_clock := not active_clock; + end if; + + if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then + current_clock := 0; + active_clock := not active_clock; + end if; + end if; + end if; + + end if; + end if; + + -- schedule outputs + clkbad(0) <= clk0_is_bad; + clkbad(1) <= clk1_is_bad; + activeclock <= active_clock; + + end process; + + + n1 : MF_cda_mn_cntr + port map ( + clk => clkin, + reset => areset_ipd, + cout => refclk, + initial_value => n_val, + modulus => n_val); + +inclk_c0 <= refclk when c0_test_source = 1 else + fbclk when c0_test_source = 0 else + inclk_c_from_vco(0); + + + c0 : MF_cda_scale_cntr + port map ( + clk => inclk_c0, + reset => areset_ena_sig, + cout => c_clk(0), + initial => c_initial_val(0), + high => c_high_val(0), + low => c_low_val(0), + mode => c_mode_val(0), + ph_tap => c_ph_val(0)); + + inclk_c1 <= refclk when c1_test_source = 1 else + fbclk when c1_test_source = 0 else + c_clk(0) when c1_use_casc_in = "on" else + inclk_c_from_vco(1); + + + c1 : MF_cda_scale_cntr + port map ( + clk => inclk_c1, + reset => areset_ena_sig, + cout => c_clk(1), + initial => c_initial_val(1), + high => c_high_val(1), + low => c_low_val(1), + mode => c_mode_val(1), + ph_tap => c_ph_val(1)); + +inclk_c2 <= refclk when c2_test_source = 1 else + fbclk when c2_test_source = 0 else + c_clk(1) when c2_use_casc_in = "on" else + inclk_c_from_vco(2); + + c2 : MF_cda_scale_cntr + port map ( + clk => inclk_c2, + reset => areset_ena_sig, + cout => c_clk(2), + initial => c_initial_val(2), + high => c_high_val(2), + low => c_low_val(2), + mode => c_mode_val(2), + ph_tap => c_ph_val(2)); + + + inclk_c3 <= refclk when c3_test_source = 1 else + fbclk when c3_test_source = 0 else + c_clk(2) when c3_use_casc_in = "on" else + inclk_c_from_vco(3); + + c3 : MF_cda_scale_cntr + port map ( + clk => inclk_c3, + reset => areset_ena_sig, + cout => c_clk(3), + initial => c_initial_val(3), + high => c_high_val(3), + low => c_low_val(3), + mode => c_mode_val(3), + ph_tap => c_ph_val(3)); + + inclk_c4 <= refclk when c4_test_source = 1 else + fbclk when c4_test_source = 0 else + c_clk(3) when (c4_use_casc_in = "on") else + inclk_c_from_vco(4); + + c4 : MF_cda_scale_cntr + port map ( + clk => inclk_c4, + reset => areset_ena_sig, + cout => c_clk(4), + initial => c_initial_val(4), + high => c_high_val(4), + low => c_low_val(4), + mode => c_mode_val(4), + ph_tap => c_ph_val(4)); + + + + + + + + + + + + process(scandone_tmp, lock) + begin + if (scandone_tmp'event and (scandone_tmp = '1')) then + pll_has_just_been_reconfigured <= true; + elsif (lock'event and (lock = '1')) then + pll_has_just_been_reconfigured <= false; + end if; + end process; + + process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco) + variable c0_got_first_rising_edge : boolean := false; + variable c0_count : integer := 2; + variable c0_initial_count : integer := 1; + variable c0_tmp, c1_tmp : std_logic := '0'; + variable c1_got_first_rising_edge : boolean := false; + variable c1_count : integer := 2; + variable c1_initial_count : integer := 1; + begin + if (areset_ipd = '1' or sig_stop_vco = '1') then + c0_count := 2; + c1_count := 2; + c0_initial_count := 1; + c1_initial_count := 1; + c0_got_first_rising_edge := false; + c1_got_first_rising_edge := false; + else + if (not c0_got_first_rising_edge) then + if (inclk_c0'event and inclk_c0 = '1') then + if (c0_initial_count = c_initial_val(0)) then + c0_got_first_rising_edge := true; + else + c0_initial_count := c0_initial_count + 1; + end if; + end if; + elsif (inclk_c0'event) then + c0_count := c0_count + 1; + if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then + c0_count := 1; + end if; + end if; + if (inclk_c0'event and inclk_c0 = '0') then + if (c0_count = 1) then + c0_tmp := '1'; + c0_got_first_rising_edge := false; + else + c0_tmp := '0'; + end if; + end if; + + if (not c1_got_first_rising_edge) then + if (inclk_c1'event and inclk_c1 = '1') then + if (c1_initial_count = c_initial_val(1)) then + c1_got_first_rising_edge := true; + else + c1_initial_count := c1_initial_count + 1; + end if; + end if; + elsif (inclk_c1'event) then + c1_count := c1_count + 1; + if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then + c1_count := 1; + end if; + end if; + if (inclk_c1'event and inclk_c1 = '0') then + if (c1_count = 1) then + c1_tmp := '1'; + c1_got_first_rising_edge := false; + else + c1_tmp := '0'; + end if; + end if; + end if; + + end process; + + + locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE + lock; + + + process (scandone_tmp) + variable buf : line; + begin + if (scandone_tmp'event and scandone_tmp = '1') then + if (reconfig_err = false) then + ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note; + write (buf, string'(" N modulus = ")); + write (buf, n_val); + write (buf, string'(" ( ")); + write (buf, n_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M modulus = ")); + write (buf, m_val); + write (buf, string'(" ( ")); + write (buf, m_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M ph_tap = ")); + write (buf, m_ph_val); + write (buf, string'(" ( ")); + write (buf, m_ph_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + for i in 0 to (num_output_cntrs-1) loop + write (buf, clk_num(i)); + write (buf, string'(" : ")); + write (buf, cntrs(i)); + write (buf, string'(" : high = ")); + write (buf, c_high_val(i)); + write (buf, string'(" (")); + write (buf, c_high_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , low = ")); + write (buf, c_low_val(i)); + write (buf, string'(" (")); + write (buf, c_low_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , mode = ")); + write (buf, c_mode_val(i)); + write (buf, string'(" (")); + write (buf, c_mode_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , phase tap = ")); + write (buf, c_ph_val(i)); + write (buf, string'(" (")); + write (buf, c_ph_val_old(i)); + write (buf, string'(") ")); + writeline(output, buf); + end loop; + + IF (pll_reconfig_display_full_setting) THEN + write (buf, string'(" Charge Pump Current (uA) = ")); + write (buf, cp_curr_val); + write (buf, string'(" ( ")); + write (buf, cp_curr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (pF) = ")); + write (buf, lfc_val); + write (buf, string'(" ( ")); + write (buf, lfc_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (Kohm) = ")); + write (buf, lfr_val); + write (buf, string'(" ( ")); + write (buf, lfr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + + ELSE + write (buf, string'(" Charge Pump Current (bit setting) = ")); + write (buf, alt_conv_integer(cp_curr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, cp_curr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (bit setting) = ")); + write (buf, alt_conv_integer(lfc_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfc_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (bit setting) = ")); + write (buf, alt_conv_integer(lfr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + END IF; + cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting); + lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting); + lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting); + else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning; + end if; + end if; + + end process; + + update_conf_latches <= configupdate_ipd; + + + process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd) + variable init : boolean := true; + variable low, high : std_logic_vector(7 downto 0); + variable low_fast, high_fast : std_logic_vector(3 downto 0); + variable mode : string(1 to 6) := "bypass"; + variable is_error : boolean := false; + variable m_tmp, n_tmp : std_logic_vector(8 downto 0); + variable lfr_val_tmp : string(1 to 2) := " "; + + variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1); + variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1); + variable c_mode_val_tmp : str_array(0 to 4); + variable m_val_tmp : integer := 0; + variable c0_rising_edge_transfer_done : boolean := false; + variable c1_rising_edge_transfer_done : boolean := false; + variable c2_rising_edge_transfer_done : boolean := false; + variable c3_rising_edge_transfer_done : boolean := false; + variable c4_rising_edge_transfer_done : boolean := false; + + -- variables for scaling of multiply_by and divide_by values + variable i_clk0_mult_by : integer := 1; + variable i_clk0_div_by : integer := 1; + variable i_clk1_mult_by : integer := 1; + variable i_clk1_div_by : integer := 1; + variable i_clk2_mult_by : integer := 1; + variable i_clk2_div_by : integer := 1; + variable i_clk3_mult_by : integer := 1; + variable i_clk3_div_by : integer := 1; + variable i_clk4_mult_by : integer := 1; + variable i_clk4_div_by : integer := 1; + variable max_d_value : integer := 1; + variable new_multiplier : integer := 1; + + -- internal variables for storing the phase shift number.(used in lvds mode only) + variable i_clk0_phase_shift : integer := 1; + variable i_clk1_phase_shift : integer := 1; + variable i_clk2_phase_shift : integer := 1; + + -- user to advanced variables + + variable max_neg_abs : integer := 0; + variable i_m_initial : integer; + variable i_m : integer := 1; + variable i_n : integer := 1; + variable i_c_high : int_array(0 to 4); + variable i_c_low : int_array(0 to 4); + variable i_c_initial : int_array(0 to 4); + variable i_c_ph : int_array(0 to 4); + variable i_c_mode : str_array(0 to 4); + variable i_m_ph : integer; + variable output_count : integer; + variable new_divisor : integer; + + variable clk0_cntr : string(1 to 6) := " c0"; + variable clk1_cntr : string(1 to 6) := " c1"; + variable clk2_cntr : string(1 to 6) := " c2"; + variable clk3_cntr : string(1 to 6) := " c3"; + variable clk4_cntr : string(1 to 6) := " c4"; + + variable fbk_cntr : string(1 to 2); + variable fbk_cntr_index : integer; + variable start_bit : integer; + variable quiet_time : time := 0 ps; + variable slowest_clk_old : time := 0 ps; + variable slowest_clk_new : time := 0 ps; + + variable i : integer := 0; + variable j : integer := 0; + variable scanread_active_edge : time := 0 ps; + variable got_first_scanclk : boolean := false; + variable scanclk_last_rising_edge : time := 0 ps; + variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + variable index : integer := 0; + variable scan_chain_length : integer := GPP_SCAN_CHAIN; + variable tmp_rem : integer := 0; + variable scanclk_cycles : integer := 0; + variable lfc_tmp : std_logic_vector(1 downto 0); + variable lfr_tmp : std_logic_vector(5 downto 0); + variable lfr_int : integer := 0; + + variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0); + variable buf : line; + variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0'); + variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0'); + + function slowest_clk ( + C0 : integer; C0_mode : string(1 to 6); + C1 : integer; C1_mode : string(1 to 6); + C2 : integer; C2_mode : string(1 to 6); + C3 : integer; C3_mode : string(1 to 6); + C4 : integer; C4_mode : string(1 to 6); + C5 : integer; C5_mode : string(1 to 6); + C6 : integer; C6_mode : string(1 to 6); + C7 : integer; C7_mode : string(1 to 6); + C8 : integer; C8_mode : string(1 to 6); + C9 : integer; C9_mode : string(1 to 6); + refclk : time; m_mod : integer) return time is + variable max_modulus : integer := 1; + variable q_period : time := 0 ps; + variable refclk_int : integer := 0; + begin + if (C0_mode /= "bypass" and C0_mode /= " off") then + max_modulus := C0; + end if; + if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then + max_modulus := C1; + end if; + if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then + max_modulus := C2; + end if; + if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then + max_modulus := C3; + end if; + if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then + max_modulus := C4; + end if; + if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then + max_modulus := C5; + end if; + if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then + max_modulus := C6; + end if; + if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then + max_modulus := C7; + end if; + if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then + max_modulus := C8; + end if; + if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then + max_modulus := C9; + end if; + + refclk_int := refclk / 1 ps; + if (m_mod /= 0) then + q_period := (refclk_int * max_modulus / m_mod) * 1 ps; + end if; + return (2*q_period); + end slowest_clk; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + + function extract_cntr_string (arg:string) return string is + variable str : string(1 to 6) := " c0"; + begin + if (arg = "c0") then + str := " c0"; + elsif (arg = "c1") then + str := " c1"; + elsif (arg = "c2") then + str := " c2"; + elsif (arg = "c3") then + str := " c3"; + elsif (arg = "c4") then + str := " c4"; + elsif (arg = "c5") then + str := " c5"; + elsif (arg = "c6") then + str := " c6"; + elsif (arg = "c7") then + str := " c7"; + elsif (arg = "c8") then + str := " c8"; + elsif (arg = "c9") then + str := " c9"; + else str := " c0"; + + end if; + + return str; + + end extract_cntr_string; + + function extract_cntr_index (arg:string) return integer is + variable index : integer := 0; + begin + if (arg(6) = '0') then + index := 0; + elsif (arg(6) = '1') then + index := 1; + elsif (arg(6) = '2') then + index := 2; + elsif (arg(6) = '3') then + index := 3; + elsif (arg(6) = '4') then + index := 4; + elsif (arg(6) = '5') then + index := 5; + elsif (arg(6) = '6') then + index := 6; + elsif (arg(6) = '7') then + index := 7; + elsif (arg(6) = '8') then + index := 8; + else index := 9; + end if; + + return index; + end extract_cntr_index; + + function output_cntr_num (arg:string) return string is + variable str : string(1 to 6) := "unused"; + begin + if (arg = "c0") then + str := " clk0"; + elsif (arg = "c1") then + str := " clk1"; + elsif (arg = "c2") then + str := " clk2"; + elsif (arg = "c3") then + str := " clk3"; + elsif (arg = "c4") then + str := " clk4"; + elsif (arg = "c5") then + str := " clk5"; + elsif (arg = "c6") then + str := " clk6"; + elsif (arg = "c7") then + str := " clk7"; + elsif (arg = "c8") then + str := " clk8"; + elsif (arg = "c9") then + str := " clk9"; + else str := "unused"; + end if; + return str; + end output_cntr_num; + + begin + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val <= i_c_ph; + END IF; + + if (init) then + if (m = 0) then + clk4_cntr := " c4"; + clk3_cntr := " c3"; + clk2_cntr := " c2"; + clk1_cntr := " c1"; + clk0_cntr := " c0"; + else + clk4_cntr := extract_cntr_string(clk4_counter); + clk3_cntr := extract_cntr_string(clk3_counter); + clk2_cntr := extract_cntr_string(clk2_counter); + clk1_cntr := extract_cntr_string(clk1_counter); + clk0_cntr := extract_cntr_string(clk0_counter); + end if; + + clk_num(4) <= output_cntr_num(clk4_counter); + clk_num(3) <= output_cntr_num(clk3_counter); + clk_num(2) <= output_cntr_num(clk2_counter); + clk_num(1) <= output_cntr_num(clk1_counter); + clk_num(0) <= output_cntr_num(clk0_counter); + + i_clk0_counter <= extract_cntr_index(clk0_cntr); + i_clk1_counter <= extract_cntr_index(clk1_cntr); + i_clk2_counter <= extract_cntr_index(clk2_cntr); + i_clk3_counter <= extract_cntr_index(clk3_cntr); + i_clk4_counter <= extract_cntr_index(clk4_cntr); + + + if (m = 0) then -- convert user parameters to advanced + -- set the limit of the divide_by value that can be returned by + -- the following function. + max_d_value := 1500; + + -- scale down the multiply_by and divide_by values provided by the design + -- before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + + if (vco_frequency_control = "manual_phase") then + find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step, + i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + i_clk0_div_by, i_clk1_div_by, + i_clk2_div_by, i_clk3_div_by, + i_clk4_div_by, + 1,1,1,1,1, + clk0_counter, clk1_counter, + clk2_counter, clk3_counter, + clk4_counter, + "unused","unused","unused","unused","unused", + i_m, i_n); + elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then + i_n := vco_divide_by; + i_m := vco_multiply_by; + else + i_n := 1; + + if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then + i_m := i_clk0_mult_by; + else + i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + inclk0_input_frequency); + end if; + end if; + + if (pll_type = "flvds") then + -- Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier := clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; + i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; + i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; + else + i_clk0_phase_shift := str2int(clk0_phase_shift); + i_clk1_phase_shift := str2int(clk1_phase_shift); + i_clk2_phase_shift := str2int(clk2_phase_shift); + end if; + + max_neg_abs := maxnegabs(i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + 0, + 0, + 0, + 0, + 0 + ); + i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); + + i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + + + i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + + + + i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); + + i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + + + + else -- m /= 0 + + i_n := n; + i_m := m; + i_m_initial := m_initial; + i_m_ph := m_ph; + i_c_ph(0) := c0_ph; + i_c_ph(1) := c1_ph; + i_c_ph(2) := c2_ph; + i_c_ph(3) := c3_ph; + i_c_ph(4) := c4_ph; + i_c_high(0) := c0_high; + i_c_high(1) := c1_high; + i_c_high(2) := c2_high; + i_c_high(3) := c3_high; + i_c_high(4) := c4_high; + i_c_low(0) := c0_low; + i_c_low(1) := c1_low; + i_c_low(2) := c2_low; + i_c_low(3) := c3_low; + i_c_low(4) := c4_low; + i_c_initial(0) := c0_initial; + i_c_initial(1) := c1_initial; + i_c_initial(2) := c2_initial; + i_c_initial(3) := c3_initial; + i_c_initial(4) := c4_initial; + i_c_mode(0) := translate_string(c0_mode); + i_c_mode(1) := translate_string(c1_mode); + i_c_mode(2) := translate_string(c2_mode); + i_c_mode(3) := translate_string(c3_mode); + i_c_mode(4) := translate_string(c4_mode); + + end if; -- user to advanced conversion. + + m_initial_val <= i_m_initial; + n_val <= i_n; + m_val <= i_m; + + if (i_m = 1) then + m_mode_val <= "bypass"; + else + m_mode_val <= " "; + end if; + if (i_n = 1) then + n_mode_val <= "bypass"; + else + n_mode_val <= " "; + end if; + + m_ph_val <= i_m_ph; + m_ph_initial <= i_m_ph; + m_val_tmp := i_m; + + for i in 0 to 4 loop + if (i_c_mode(i) = "bypass") then + if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then + i_c_high(i) := 16; + i_c_low(i) := 16; + else + i_c_high(i) := 256; + i_c_low(i) := 256; + end if; + end if; + c_ph_val(i) <= i_c_ph(i); + c_initial_val(i) <= i_c_initial(i); + c_high_val(i) <= i_c_high(i); + c_low_val(i) <= i_c_low(i); + c_mode_val(i) <= i_c_mode(i); + c_high_val_tmp(i) := i_c_high(i); + c_hval(i) := i_c_high(i); + c_low_val_tmp(i) := i_c_low(i); + c_lval(i) := i_c_low(i); + c_mode_val_tmp(i) := i_c_mode(i); + c_ph_val_orig(i) <= i_c_ph(i); + c_high_val_hold(i) <= i_c_high(i); + c_low_val_hold(i) <= i_c_low(i); + c_mode_val_hold(i) <= i_c_mode(i); + end loop; + + + + scan_chain_length := SCAN_CHAIN; + + + num_output_cntrs <= 5; + + init := false; + elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then + c0_rising_edge_transfer_done := false; + c1_rising_edge_transfer_done := false; + c2_rising_edge_transfer_done := false; + c3_rising_edge_transfer_done := false; + c4_rising_edge_transfer_done := false; + update_conf_latches_reg <= '0'; + elsif (update_conf_latches'event and update_conf_latches = '1') then + initiate_reconfig <= '1'; + elsif (areset_ipd'event AND areset_ipd = '1') then + if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if; + elsif (scanclk_ipd'event and scanclk_ipd = '1') then + IF (initiate_reconfig = '1') THEN + initiate_reconfig <= '0'; + ASSERT false REPORT "PLL Reprogramming Initiated" severity note; + + update_conf_latches_reg <= update_conf_latches; + reconfig_err <= false; + scandone_tmp <= '0'; + cp_curr_old <= cp_curr_val; + lfc_old <= lfc_val; + lfr_old <= lfr_val; + vco_old <= vco_cur; + -- LF unused : bit 0,1 + -- LF Capacitance : bits 2,3 : all values are legal + buf_scan_data := scan_data(2 TO 3); + + IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN + lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + ELSE + lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + END IF; + -- LF Resistance : bits 4-8 + -- valid values - 00000,00100,10000,10100,11000,11011,11100,11110 + IF (scan_data(4 TO 8) = "00000") THEN + lfr_val <= "20"; + ELSIF (scan_data(4 TO 8) = "00100") THEN + lfr_val <= "16"; + ELSIF (scan_data(4 TO 8) = "10000") THEN + lfr_val <= "12"; + ELSIF (scan_data(4 TO 8) = "10100") THEN + lfr_val <= "08"; + ELSIF (scan_data(4 TO 8) = "11000") THEN + lfr_val <= "06"; + ELSIF (scan_data(4 TO 8) = "11011") THEN + lfr_val <= "04"; + ELSIF (scan_data(4 TO 8) = "11100") THEN + lfr_val <= "02"; + ELSE + lfr_val <= "01"; + END IF; + + + -- VCO post scale assignment + if (scan_data(9) = '1') then -- vco_post_scale = 1 + i_vco_max <= VCO_MAX_NO_DIVISION/2; + i_vco_min <= VCO_MIN_NO_DIVISION/2; + vco_cur <= 1; + else + i_vco_max <= vco_max; + i_vco_min <= vco_min; + vco_cur <= 2; + end if; + -- CP + -- Bit 9 : CRBYPASS + -- Bit 10-14 : unused + -- Bits 15-17 : all values are legal + + buf_scan_data_2 := scan_data(15 TO 17); + cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2)); + -- save old values for display info. + + cp_curr_val_bit_setting <= scan_data(15 TO 17); + lfc_val_bit_setting <= scan_data(2 TO 3); + lfr_val_bit_setting <= scan_data(4 TO 8); + + m_val_old <= m_val; + n_val_old <= n_val; + m_mode_val_old <= m_mode_val; + n_mode_val_old <= n_mode_val; + WHILE (i < num_output_cntrs) LOOP + c_high_val_old(i) <= c_high_val(i); + c_low_val_old(i) <= c_low_val(i); + c_mode_val_old(i) <= c_mode_val(i); + i := i + 1; + END LOOP; + -- M counter + -- 1. Mode - bypass (bit 18) + + IF (scan_data(18) = '1') THEN + n_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 27) + ELSIF (scan_data(27) = '1') THEN + n_mode_val <= " odd"; + ELSE + n_mode_val <= " even"; + END IF; + + -- 2. High (bit 19-26) + + n_hi := scan_data(19 TO 26); + + -- 4. Low (bit 28-35) + + n_lo := scan_data(28 TO 35); + -- N counter + -- 1. Mode - bypass (bit 36) + + IF (scan_data(36) = '1') THEN + m_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 45) + ELSIF (scan_data(45) = '1') THEN + m_mode_val <= " odd"; + ELSE + m_mode_val <= " even"; + END IF; + + -- 2. High (bit 37-44) + + m_hi := scan_data(37 TO 44); + + -- 4. Low (bit 46-53) + + m_lo := scan_data(46 TO 53); + -- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low + + i := 0; + WHILE (i < num_output_cntrs) LOOP + -- 1. Mode - bypass + + IF (scan_data(54 + i * 18 + 0) = '1') THEN + c_mode_val_tmp(i) := "bypass"; + -- 3. Mode - odd/even + ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN + c_mode_val_tmp(i) := " odd"; + ELSE + c_mode_val_tmp(i) := " even"; + END IF; + -- 2. Hi + + high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8); + c_hval(i) := alt_conv_integer(high); + IF (c_hval(i) /= 0) THEN + c_high_val_tmp(i) := c_hval(i); + ELSE + c_high_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + + -- 4. Low + + low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17); + c_lval(i) := alt_conv_integer(low); + IF (c_lval(i) /= 0) THEN + c_low_val_tmp(i) := c_lval(i); + ELSE + c_low_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + i := i + 1; + END LOOP; + -- Legality Checks + + -- M counter value + IF(scan_data(36) /= '1') THEN + IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (m_hi /= "00000000") THEN + m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo); + ELSE + m_val_tmp := alt_conv_integer("000000001"); + END IF; + ELSE + m_val_tmp := alt_conv_integer("10000000"); + END IF; + -- N counter value + IF(scan_data(18) /= '1') THEN + IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (n_hi /= "00000000") THEN + n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo); + ELSE + n_val <= alt_conv_integer("000000001"); + END IF; + ELSE + n_val <= alt_conv_integer("10000000"); + END IF; + -- TODO : Give warnings/errors in the following cases? + -- 1. Illegal counter values (error) + -- 2. Change of mode (warning) + -- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0) + + END IF; + end if; + + + if (fbclk'event and fbclk = '1') then + m_val <= m_val_tmp; + end if; + + if (update_conf_latches_reg = '1') then + if (scanclk_ipd'event and scanclk_ipd = '1') then + c0_rising_edge_transfer_done := true; + c_high_val(0) <= c_high_val_tmp(0); + c_mode_val(0) <= c_mode_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c1_rising_edge_transfer_done := true; + c_high_val(1) <= c_high_val_tmp(1); + c_mode_val(1) <= c_mode_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c2_rising_edge_transfer_done := true; + c_high_val(2) <= c_high_val_tmp(2); + c_mode_val(2) <= c_mode_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(3) <= c_high_val_tmp(3); + c_mode_val(3) <= c_mode_val_tmp(3); + c3_rising_edge_transfer_done := true; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(4) <= c_high_val_tmp(4); + c_mode_val(4) <= c_mode_val_tmp(4); + c4_rising_edge_transfer_done := true; + end if; + + + + + + end if; + + if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then + c_low_val(0) <= c_low_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then + c_low_val(1) <= c_low_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then + c_low_val(2) <= c_low_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then + c_low_val(3) <= c_low_val_tmp(3); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then + c_low_val(4) <= c_low_val_tmp(4); + end if; + + if (update_phase = '1') then + if (vco_out(0)'event and vco_out(0) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 0) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(1)'event and vco_out(1) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 1) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(2)'event and vco_out(2) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 2) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(3)'event and vco_out(3) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 3) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(4)'event and vco_out(4) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 4) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(5)'event and vco_out(5) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 5) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(6)'event and vco_out(6) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 6) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(7)'event and vco_out(7) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 7) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + end if; + + + + if (vco_out(0)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + inclk_c_from_vco(i) <= vco_out(0); + end if; + end loop; + if (m_ph_val = 0) then + inclk_m_from_vco <= vco_out(0); + end if; + end if; + if (vco_out(1)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + inclk_c_from_vco(i) <= vco_out(1); + end if; + end loop; + if (m_ph_val = 1) then + inclk_m_from_vco <= vco_out(1); + end if; + end if; + if (vco_out(2)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + inclk_c_from_vco(i) <= vco_out(2); + end if; + end loop; + if (m_ph_val = 2) then + inclk_m_from_vco <= vco_out(2); + end if; + end if; + if (vco_out(3)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + inclk_c_from_vco(i) <= vco_out(3); + end if; + end loop; + if (m_ph_val = 3) then + inclk_m_from_vco <= vco_out(3); + end if; + end if; + if (vco_out(4)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + inclk_c_from_vco(i) <= vco_out(4); + end if; + end loop; + if (m_ph_val = 4) then + inclk_m_from_vco <= vco_out(4); + end if; + end if; + if (vco_out(5)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + inclk_c_from_vco(i) <= vco_out(5); + end if; + end loop; + if (m_ph_val = 5) then + inclk_m_from_vco <= vco_out(5); + end if; + end if; + if (vco_out(6)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + inclk_c_from_vco(i) <= vco_out(6); + end if; + end loop; + if (m_ph_val = 6) then + inclk_m_from_vco <= vco_out(6); + end if; + end if; + if (vco_out(7)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + inclk_c_from_vco(i) <= vco_out(7); + end if; + end loop; + if (m_ph_val = 7) then + inclk_m_from_vco <= vco_out(7); + end if; + end if; + + + + + if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then + scanclkena_reg <= scanclkena_ipd; + if (scanclkena_reg = '1') then + scandata_in <= scandata_ipd; + scandata_out <= scandataout_tmp; + end if; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then + if (got_first_scanclk) then + scanclk_period <= now - scanclk_last_rising_edge; + else + got_first_scanclk := true; + end if; + if (scanclkena_reg = '1') then + for j in scan_chain_length - 1 downto 1 loop + scan_data(j) <= scan_data(j-1); + end loop; + scan_data(0) <= scandata_in; + end if; + scanclk_last_rising_edge := now; + end if; + end process; + +-- PLL Phase Reconfiguration + +PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd) + VARIABLE i : INTEGER := 0; + VARIABLE c_ph : INTEGER := 0; + VARIABLE m_ph : INTEGER := 0; + VARIABLE select_counter : INTEGER := 0; +BEGIN + IF (NOW = 0 ps) THEN + m_ph_val_tmp <= m_ph_initial; + END IF; + + -- Latch phase enable (same as phasestep) on neg edge of scan clock + IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN + phasestep_reg <= phasestep_ipd; + END IF; + + IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN + IF (update_phase = '0') THEN + phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart + -- if not, next phasestep cycle is skipped + END IF; + END IF; + -- revert counter phase tap values to POF programmed values + -- if PLL is reset + + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val_tmp <= c_ph_val_orig; + m_ph_val_tmp <= m_ph_initial; + END IF; + + IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN + IF (phasestep_reg = '1') THEN + IF (phasestep_high_count = 1) THEN + phasecounterselect_reg <= phasecounterselect_ipd; + phaseupdown_reg <= phaseupdown_ipd; + -- start reconfiguration + IF (phasecounterselect_ipd < "111") THEN -- no counters selected + IF (phasecounterselect_ipd = "000") THEN + i := 0; + WHILE (i < num_output_cntrs) LOOP + c_ph := c_ph_val(i); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(i) <= c_ph; + i := i + 1; + END LOOP; + ELSIF (phasecounterselect_ipd = "001") THEN + m_ph := m_ph_val; + IF (phaseupdown_ipd = '1') THEN + m_ph := (m_ph + 1) mod num_phase_taps; + ELSIF (m_ph = 0) THEN + m_ph := num_phase_taps - 1; + ELSE + m_ph := (m_ph - 1) mod num_phase_taps; + END IF; + m_ph_val_tmp <= m_ph; + ELSE + select_counter := alt_conv_integer(phasecounterselect_ipd) - 2; + c_ph := c_ph_val(select_counter); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(select_counter) <= c_ph; + END IF; + update_phase <= '1','0' AFTER (0.5 * scanclk_period); + END IF; + END IF; + phasestep_high_count <= phasestep_high_count + 1; + + END IF; + END IF; +END PROCESS; + + scandataout_tmp <= scan_data(SCAN_CHAIN - 2); + + process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk) + variable sched_time : time := 0 ps; + + TYPE time_array is ARRAY (0 to 7) of time; + variable init : boolean := true; + variable refclk_period : time; + variable m_times_vco_period : time; + variable new_m_times_vco_period : time; + + variable phase_shift : time_array := (OTHERS => 0 ps); + variable last_phase_shift : time_array := (OTHERS => 0 ps); + + variable l_index : integer := 1; + variable cycle_to_adjust : integer := 0; + + variable stop_vco : boolean := false; + + variable locked_tmp : std_logic := '0'; + variable pll_is_locked : boolean := false; + variable cycles_pfd_low : integer := 0; + variable cycles_pfd_high : integer := 0; + variable cycles_to_lock : integer := 0; + variable cycles_to_unlock : integer := 0; + + variable got_first_refclk : boolean := false; + variable got_second_refclk : boolean := false; + variable got_first_fbclk : boolean := false; + + variable refclk_time : time := 0 ps; + variable fbclk_time : time := 0 ps; + variable first_fbclk_time : time := 0 ps; + + variable fbclk_period : time := 0 ps; + + variable first_schedule : boolean := true; + + variable vco_val : std_logic := '0'; + variable vco_period_was_phase_adjusted : boolean := false; + variable phase_adjust_was_scheduled : boolean := false; + + variable loop_xplier : integer; + variable loop_initial : integer := 0; + variable loop_ph : integer := 0; + variable loop_time_delay : integer := 0; + + variable initial_delay : time := 0 ps; + variable vco_per : time; + variable tmp_rem : integer; + variable my_rem : integer; + variable fbk_phase : integer := 0; + + variable pull_back_M : integer := 0; + variable total_pull_back : integer := 0; + variable fbk_delay : integer := 0; + + variable offset : time := 0 ps; + + variable tmp_vco_per : integer := 0; + variable high_time : time; + variable low_time : time; + + variable got_refclk_posedge : boolean := false; + variable got_fbclk_posedge : boolean := false; + variable inclk_out_of_range : boolean := false; + variable no_warn : boolean := false; + + variable ext_fbk_cntr_modulus : integer := 1; + variable init_clks : boolean := true; + variable pll_is_in_reset : boolean := false; + variable buf : line; + begin + if (init) then + + -- jump-start the VCO + -- add 1 ps delay to ensure all signals are updated to initial + -- values + schedule_vco <= transport not schedule_vco after 1 ps; + + init := false; + end if; + + if (schedule_vco'event) then + if (init_clks) then + refclk_period := inclk0_input_frequency * n_val * 1 ps; + + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + init_clks := false; + end if; + sched_time := 0 ps; + for i in 0 to 7 loop + last_phase_shift(i) := phase_shift(i); + end loop; + cycle_to_adjust := 0; + l_index := 1; + m_times_vco_period := new_m_times_vco_period; + end if; + + -- areset was asserted + if (areset_ipd'event and areset_ipd = '1') then + assert false report family_name & " PLL was reset" severity note; + -- reset lock parameters + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + end if; + + if (areset_ipd = '1') then + pll_is_in_reset := true; + got_first_refclk := false; + got_second_refclk := false; + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after 1 ps; + end loop; + end if; + + + if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after last_phase_shift(i); + phase_shift(i) := 0 ps; + last_phase_shift(i) := 0 ps; + end loop; + + -- reset lock parameters + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + + got_first_refclk := false; + got_second_refclk := false; + refclk_time := 0 ps; + got_first_fbclk := false; + fbclk_time := 0 ps; + first_fbclk_time := 0 ps; + fbclk_period := 0 ps; + + first_schedule := true; + vco_val := '0'; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + + elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then + + -- note areset deassert time + -- note it as refclk_time to prevent false triggering + -- of stop_vco after areset + if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then + refclk_time := now; + locked_tmp := '0'; + end if; + + pll_is_in_reset := false; + -- calculate loop_xplier : this will be different from m_val + -- in external_feedback_mode + loop_xplier := m_val; + loop_initial := m_initial_val - 1; + loop_ph := m_ph_val; + + + -- convert initial value to delay + initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; + + -- convert loop ph_tap to delay + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier; + if (my_rem /= 0) then + tmp_vco_per := tmp_vco_per + 1; + end if; + fbk_phase := (loop_ph * tmp_vco_per)/8; + + pull_back_M := initial_delay/1 ps + fbk_phase; + + total_pull_back := pull_back_M; + + if (simulation_type = "timing") then + total_pull_back := total_pull_back + pll_compensation_delay; + end if; + while (total_pull_back > refclk_period/1 ps) loop + total_pull_back := total_pull_back - refclk_period/1 ps; + end loop; + + if (total_pull_back > 0) then + offset := refclk_period - (total_pull_back * 1 ps); + end if; + + fbk_delay := total_pull_back - fbk_phase; + if (fbk_delay < 0) then + offset := offset - (fbk_phase * 1 ps); + fbk_delay := total_pull_back; + end if; + + -- assign m_delay + m_delay <= transport fbk_delay after 1 ps; + + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + for i in 1 to loop_xplier loop + -- adjust cycles + tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier; + if (my_rem /= 0 and l_index <= my_rem) then + tmp_rem := (loop_xplier * l_index) rem my_rem; + cycle_to_adjust := (loop_xplier * l_index) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + if (cycle_to_adjust = i) then + tmp_vco_per := tmp_vco_per + 1; + l_index := l_index + 1; + end if; + + -- calculate high and low periods + vco_per := tmp_vco_per * 1 ps; + high_time := (tmp_vco_per/2) * 1 ps; + if (tmp_vco_per rem 2 /= 0) then + high_time := high_time + 1 ps; + end if; + low_time := vco_per - high_time; + + -- schedule the rising and falling edges + for j in 1 to 2 loop + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + if (first_schedule) then + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + else + vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k)); + end if; + end loop; + end loop; + end loop; + + -- schedule once more + if (first_schedule) then + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + end loop; + first_schedule := false; + end if; + + schedule_vco <= transport not schedule_vco after sched_time; + + if (vco_period_was_phase_adjusted) then + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := true; + + vco_per := m_times_vco_period/loop_xplier; + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + end loop; + end if; + end if; +-- Bypass lock detect + +if (refclk'event and refclk = '1' and areset_ipd = '0') then + if (test_bypass_lock_detect = "on") then + if (pfdena_ipd = '1') then + cycles_pfd_low := 0; + if (pfd_locked = '0') then + if (cycles_pfd_high = lock_high) then + assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning; + pfd_locked <= '1'; + end if; + cycles_pfd_high := cycles_pfd_high + 1; + end if; + end if; + + if (pfdena_ipd = '0') then + cycles_pfd_high := 0; + if (pfd_locked = '1') then + if (cycles_pfd_low = lock_low) then + assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning; + pfd_locked <= '0'; + end if; + cycles_pfd_low := cycles_pfd_low + 1; + end if; + end if; + end if; + + + if (refclk'event and refclk = '1' and areset_ipd = '0') then + got_refclk_posedge := true; + if (not got_first_refclk) then + got_first_refclk := true; + else + got_second_refclk := true; + refclk_period := now - refclk_time; + + -- check if incoming freq. will cause VCO range to be + -- exceeded + if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and + (((refclk_period/1 ps)/loop_xplier > i_vco_max) or + ((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then + if (pll_is_locked) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + if (inclk_out_of_range) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + end if; + elsif (not no_warn) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning; + no_warn := true; + end if; + inclk_out_of_range := true; + else + vco_over <= '0'; + vco_under <= '0'; + inclk_out_of_range := false; + no_warn := false; + end if; + end if; + end if; + + if (stop_vco) then + stop_vco := false; + schedule_vco <= not schedule_vco; + end if; + + refclk_time := now; + else + got_refclk_posedge := false; + end if; + +-- Update M counter value on feedback clock edge + + if (fbclk'event and fbclk = '1') then + got_fbclk_posedge := true; + if (not got_first_fbclk) then + got_first_fbclk := true; + else + fbclk_period := now - fbclk_time; + end if; + + -- need refclk_period here, so initialized to proper value above + if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or + ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or + ( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then + stop_vco := true; + -- reset + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + if (pll_is_locked) then + pll_is_locked := false; + locked_tmp := '0'; + assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note; + if ((i_vco_max = 0) and (i_vco_min = 0)) then + assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note; + end if; + end if; + cycles_to_lock := 0; + cycles_to_unlock := 0; + first_schedule := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + fbclk_time := now; + else + got_fbclk_posedge := false; + end if; + + if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then + + -- now we know actual incoming period + if ( abs(fbclk_time - refclk_time) <= 5 ps or + (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + -- considered in phase + if (cycles_to_lock = real_lock_high) then + if (not pll_is_locked) then + assert false report family_name & " PLL locked to incoming clock" severity note; + end if; + pll_is_locked := true; + locked_tmp := '1'; + cycles_to_unlock := 0; + end if; + -- increment lock counter only if second part of above + -- time check is NOT true + if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then + cycles_to_lock := cycles_to_lock + 1; + end if; + + -- adjust m_times_vco_period + new_m_times_vco_period := refclk_period; + else + -- if locked, begin unlock + if (pll_is_locked) then + cycles_to_unlock := cycles_to_unlock + 1; + if (cycles_to_unlock = lock_low) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + end if; + end if; + if ( abs(refclk_period - fbclk_period) <= 2 ps ) then + -- frequency is still good + if (now = fbclk_time and (not phase_adjust_was_scheduled)) then + if ( abs(fbclk_time - refclk_time) > refclk_period/2) then + new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted := true; + else + new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted := true; + end if; + + end if; + else + phase_adjust_was_scheduled := false; + new_m_times_vco_period := refclk_period; + end if; + end if; + end if; + + if (pfdena_ipd = '0') then + if (pll_is_locked) then + locked_tmp := 'X'; + end if; + pll_is_locked := false; + cycles_to_lock := 0; + end if; + + -- give message only at time of deassertion + if (pfdena_ipd'event and pfdena_ipd = '0') then + assert false report "PFDENA deasserted." severity note; + elsif (pfdena_ipd'event and pfdena_ipd = '1') then + got_first_refclk := false; + got_second_refclk := false; + refclk_time := now; + end if; + + if (reconfig_err) then + lock <= '0'; + else + lock <= locked_tmp; + end if; + + -- signal to calculate quiet_time + sig_refclk_period <= refclk_period; + + if (stop_vco = true) then + sig_stop_vco <= '1'; + else + sig_stop_vco <= '0'; + end if; + + pll_locked <= pll_is_locked; + end process; + + clk0_tmp <= c_clk(i_clk0_counter); + clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE + clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else + 'X'; + + clk1_tmp <= c_clk(i_clk1_counter); + clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE + clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk2_tmp <= c_clk(i_clk2_counter); + clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE + clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk3_tmp <= c_clk(i_clk3_counter); + clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE + clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk4_tmp <= c_clk(i_clk4_counter); + clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE + clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + + + + + + + + + + + +scandataout <= scandata_out; +scandone <= NOT scandone_tmp; +phasedone <= NOT update_phase; +vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over; +vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under; +fbout <= fbclk; +end vital_pll; +-- END ARCHITECTURE VITAL_PLL +-- cycloneiii_msg + + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_stingray_mn_cntr +-- +-- Description : Simulation model for the M and N counter. This is a +-- common model for the input counter and the loop feedback +-- counter of the CycloneIIIGL PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; + +ENTITY MF_stingray_mn_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END MF_stingray_mn_cntr; + +ARCHITECTURE behave of MF_stingray_mn_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_stingray_post_divider +-- +-- Description : Simulation model that models the icdrclk output. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; + +ENTITY MF_stingray_post_divider is + GENERIC ( dpa_divider : integer := 1 + ); + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic + ); +END MF_stingray_post_divider; + +ARCHITECTURE behave of MF_stingray_post_divider is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + variable modules : integer := 0; + variable init : boolean := true; + begin + if (init = true) then + if (dpa_divider = 0) then + modules := 1; + else + modules := dpa_divider; + end if; + init := false; + end if; + + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modules) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_stingray_scale_cntr +-- +-- Description : Simulation model for the output scale-down counters. +-- This is a common model for the C0, C1, C2, C3, C4 and C5 +-- output counters of the Stingray PLL. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY MF_stingray_scale_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0; + cout : OUT std_logic + ); +END MF_stingray_scale_cntr; + +ARCHITECTURE behave of MF_stingray_scale_cntr is +begin + process (clk, reset) + variable tmp_cout : std_logic := '0'; + variable count : integer := 1; + variable output_shift_count : integer := 1; + variable first_rising_edge : boolean := false; + begin + if (reset = '1') then + count := 1; + output_shift_count := 1; + tmp_cout := '0'; + first_rising_edge := false; + elsif (clk'event) then + if (mode = " off") then + tmp_cout := '0'; + elsif (mode = "bypass") then + tmp_cout := clk; + first_rising_edge := true; + elsif (not first_rising_edge) then + if (clk = '1') then + if (output_shift_count = initial) then + tmp_cout := clk; + first_rising_edge := true; + else + output_shift_count := output_shift_count + 1; + end if; + end if; + elsif (output_shift_count < initial) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + end if; + else + count := count + 1; + if (mode = " even" and (count = (high*2) + 1)) then + tmp_cout := '0'; + elsif (mode = " odd" and (count = high*2)) then + tmp_cout := '0'; + elsif (count = (high + low)*2 + 1) then + tmp_cout := '1'; + count := 1; -- reset count + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; + +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : MF_cycloneiiigl_pll +-- +-- Description : Simulation model for the Stingray PLL. +-- In the functional mode, it is also the model for the altpll +-- megafunction. +-- +-- Limitations : Does not support Spread Spectrum and Bandwidth. +-- +-- Outputs : Up to 10 output clocks, each defined by its own set of +-- parameters. Locked output (active high) indicates when the +-- PLL locks. clkbad and activeclock are used for +-- clock switchover to indicate which input clock has gone +-- bad, when the clock switchover initiates and which input +-- clock is being used as the reference, respectively. +-- scandataout is the data output of the serial scan chain. +-- +--/////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE STD.TEXTIO.all; +USE work.MF_pllpack.all; +USE work.MF_stingray_mn_cntr; +USE work.MF_stingray_scale_cntr; +USE work.dffp; +USE work.MF_pll_reg; + + +ENTITY MF_cycloneiiigl_pll is + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM + compensate_clock : string := "clock0"; + + inclk0_input_frequency : integer := 0; + inclk1_input_frequency : integer := 0; + + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + use_dc_coupling : string := "false"; + + lock_c : integer := 4; + sim_gate_lock_device_behavior : string := "off"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_window : time := 5 ps; + test_bypass_lock_detect : string := "off"; + + + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 0; + clk0_divide_by : integer := 0; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 0; + clk1_divide_by : integer := 0; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 0; + clk2_divide_by : integer := 0; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 0; + clk3_divide_by : integer := 0; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 0; + clk4_divide_by : integer := 0; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + + feedback_source : integer := 0; + feedback_external_loop_divider : string := "false"; + + + -- ADVANCED USER PARAMETERS + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + m_ph : integer := 0; + + clk0_counter : string := "unused"; + clk1_counter : string := "unused"; + clk2_counter : string := "unused"; + clk3_counter : string := "unused"; + clk4_counter : string := "unused"; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + vco_post_scale : integer := 1; + vco_frequency_control : string := "auto"; + vco_phase_shift_step : integer := 0; + + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 1; + + charge_pump_current : integer := 10; + loop_filter_r : string := " 1.0"; + loop_filter_c : integer := 0; + + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + lpm_hint : string := "unused"; + + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + +-- Test only + init_block_reset_a_count : integer := 1; + init_block_reset_b_count : integer := 1; + charge_pump_current_bits : integer := 0; + lock_window_ui_bits : integer := 0; + loop_filter_c_bits : integer := 0; + loop_filter_r_bits : integer := 0; + test_counter_c0_delay_chain_bits : integer := 0; + test_counter_c1_delay_chain_bits : integer := 0; + test_counter_c2_delay_chain_bits : integer := 0; + test_counter_c3_delay_chain_bits : integer := 0; + test_counter_c4_delay_chain_bits : integer := 0; + test_counter_m_delay_chain_bits : integer := 0; + test_counter_n_delay_chain_bits : integer := 0; + test_feedback_comp_delay_chain_bits : integer := 0; + test_input_comp_delay_chain_bits : integer := 0; + test_volt_reg_output_mode_bits : integer := 0; + test_volt_reg_output_voltage_bits : integer := 0; + test_volt_reg_test_mode : string := "false"; + vco_range_detector_high_bits : integer := -1; + vco_range_detector_low_bits : integer := -1; + scan_chain_mif_file : string := ""; + + auto_settings : string := "true"; +-- Simulation only generics + family_name : string := "Stingray"; + + use_vco_bypass : string := "false" + ); + + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + fbout : out std_logic; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + clk : out std_logic_vector(4 downto 0); + phasecounterselect : in std_logic_vector(2 downto 0) := "000"; + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fref : out std_logic; + icdrclk : out std_logic + ); +END MF_cycloneiiigl_pll; + +ARCHITECTURE vital_pll of MF_cycloneiiigl_pll is + +TYPE int_array is ARRAY(NATURAL RANGE <>) of integer; +TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6); +TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9); +TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic; + +-- internal advanced parameter signals +signal i_vco_min : integer := vco_min * (vco_post_scale/2); +signal i_vco_max : integer := vco_max * (vco_post_scale/2); +signal i_vco_center : integer; +signal i_pfd_min : integer; +signal i_pfd_max : integer; + signal c_ph_val : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_high_val : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val : int_array(0 to 4) := (OTHERS => 1); + signal c_initial_val : int_array(0 to 4) := (OTHERS => 1); + signal c_mode_val : str_array(0 to 4); + signal clk_num : str_array(0 to 4); + +-- old values + signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_old : str_array(0 to 4); +-- hold registers + signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_hold : str_array(0 to 4); + +-- temp registers + signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0); + +signal real_lock_high : integer := 0; +signal i_clk4_counter : integer := 4; +signal i_clk3_counter : integer := 3; +signal i_clk2_counter : integer := 2; +signal i_clk1_counter : integer := 1; +signal i_clk0_counter : integer := 0; +signal i_charge_pump_current : integer; +signal i_loop_filter_r : integer; + +-- end internal advanced parameter signals + +-- CONSTANTS +CONSTANT SCAN_CHAIN : integer := 144; +CONSTANT GPP_SCAN_CHAIN : integer := 234; +CONSTANT FAST_SCAN_CHAIN : integer := 180; + CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0"); +CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2"); + +CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + +CONSTANT num_phase_taps : integer := 8; +-- signals + +signal vcc : std_logic := '1'; + +signal fbclk : std_logic; +signal refclk : std_logic; + +signal icdr_clk : std_logic; + +signal vco_over : std_logic := '0'; +signal vco_under : std_logic := '1'; + +signal pll_locked : boolean := false; + + + signal c_clk : std_logic_array(0 to 4); +signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); + +-- signals to assign values to counter params +signal m_val : integer := 1; +signal n_val : integer := 1; +signal m_ph_val : integer := 0; +signal m_ph_initial : integer := 0; +signal m_ph_val_tmp : integer := 0; +signal m_initial_val : integer := m_initial; + +signal m_mode_val : string(1 to 6) := " "; +signal n_mode_val : string(1 to 6) := " "; +signal lfc_val : integer := 0; +signal vco_cur : integer := vco_post_scale; +signal cp_curr_val : integer := 0; +signal lfr_val : string(1 to 2) := " "; + +signal cp_curr_old_bit_setting : integer := charge_pump_current_bits; +signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0'); +signal lfr_old_bit_setting : integer := loop_filter_r_bits; +signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0'); +signal lfc_old_bit_setting : integer := loop_filter_c_bits; +signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0'); + +signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true +-- old values +signal m_val_old : integer := 1; +signal n_val_old : integer := 1; +signal m_mode_val_old : string(1 to 6) := " "; +signal n_mode_val_old : string(1 to 6) := " "; +signal m_ph_val_old : integer := 0; +signal lfc_old : integer := 0; +signal vco_old : integer := 0; +signal cp_curr_old : integer := 0; +signal lfr_old : string(1 to 2) := " "; + signal num_output_cntrs : integer := 5; +signal scanclk_period : time := 1 ps; + signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + + signal clk_pfd : std_logic_vector(0 to 4); +signal clk0_tmp : std_logic; +signal clk1_tmp : std_logic; +signal clk2_tmp : std_logic; +signal clk3_tmp : std_logic; +signal clk4_tmp : std_logic; + +signal update_conf_latches : std_logic := '0'; +signal update_conf_latches_reg : std_logic := '0'; + +signal clkin : std_logic := '0'; +signal gate_locked : std_logic := '0'; +signal pfd_locked : std_logic := '0'; +signal lock : std_logic := '0'; +signal about_to_lock : boolean := false; +signal reconfig_err : boolean := false; + +signal inclk_c0 : std_logic; +signal inclk_c1 : std_logic; +signal inclk_c2 : std_logic; +signal inclk_c3 : std_logic; +signal inclk_c4 : std_logic; +signal inclk_m : std_logic; +signal devpor : std_logic; +signal devclrn : std_logic; + +signal inclk0_ipd : std_logic; +signal inclk1_ipd : std_logic; +signal pfdena_ipd : std_logic; +signal areset_ipd : std_logic; +signal fbin_ipd : std_logic; +signal scanclk_ipd : std_logic; +signal scanclkena_ipd, scanclkena_reg : std_logic; +signal scandata_ipd : std_logic; +signal clkswitch_ipd : std_logic; + signal phasecounterselect_ipd : std_logic_vector(2 downto 0); +signal phaseupdown_ipd : std_logic; +signal phasestep_ipd : std_logic; +signal configupdate_ipd : std_logic; +-- registered signals + +signal sig_offset : time := 0 ps; +signal sig_refclk_time : time := 0 ps; +signal sig_fbclk_period : time := 0 ps; +signal sig_vco_period_was_phase_adjusted : boolean := false; +signal sig_phase_adjust_was_scheduled : boolean := false; +signal sig_stop_vco : std_logic := '0'; +signal sig_m_times_vco_period : time := 0 ps; +signal sig_new_m_times_vco_period : time := 0 ps; +signal sig_got_refclk_posedge : boolean := false; +signal sig_got_fbclk_posedge : boolean := false; +signal sig_got_second_refclk : boolean := false; + +signal m_delay : integer := 0; +signal n_delay : integer := 0; + +signal inclk1_tmp : std_logic := '0'; + + +signal reset_low : std_logic := '0'; + +-- Phase Reconfig + + SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0); + +SIGNAL phaseupdown_reg : std_logic := '0'; +SIGNAL phasestep_reg : std_logic := '0'; +SIGNAL phasestep_high_count : integer := 0; +SIGNAL update_phase : std_logic := '0'; + +signal scandataout_tmp : std_logic := '0'; +signal scandata_in : std_logic := '0'; +signal scandata_out : std_logic := '0'; +signal scandone_tmp : std_logic := '1'; +signal initiate_reconfig : std_logic := '0'; + +signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; + +signal schedule_vco : std_logic := '0'; + +signal areset_ena_sig : std_logic := '0'; +signal pll_in_test_mode : boolean := false; +signal pll_has_just_been_reconfigured : boolean := false; + + signal inclk_c_from_vco : std_logic_array(0 to 4); + +signal inclk_m_from_vco : std_logic; + +SIGNAL inclk0_period : time := 0 ps; +SIGNAL last_inclk0_period : time := 0 ps; +SIGNAL last_inclk0_edge : time := 0 ps; +SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0'; +SIGNAL inclk1_period : time := 0 ps; +SIGNAL last_inclk1_period : time := 0 ps; +SIGNAL last_inclk1_edge : time := 0 ps; +SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0'; + + + +COMPONENT MF_stingray_mn_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END COMPONENT; + +COMPONENT MF_stingray_post_divider + GENERIC ( dpa_divider : integer := 0 + ); + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic + ); +END COMPONENT; + + +COMPONENT MF_stingray_scale_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0 + ); +END COMPONENT; + +COMPONENT dffp + + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +COMPONENT MF_pll_reg + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +begin + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + WireDelay : block + begin + inclk0_ipd <= inclk(0); + inclk1_ipd <= inclk(1); + areset_ipd <= areset; + pfdena_ipd <= pfdena; + scanclk_ipd <= scanclk; + scanclkena_ipd <= scanclkena; + scandata_ipd <= scandata; + configupdate_ipd <= configupdate; + clkswitch_ipd <= clkswitch; + phaseupdown_ipd <= phaseupdown; + phasestep_ipd <= phasestep; + phasecounterselect_ipd(0) <= phasecounterselect(0); + phasecounterselect_ipd(1) <= phasecounterselect(1); + phasecounterselect_ipd(2) <= phasecounterselect(2); + + end block; + +inclk_m <= fbclk when m_test_source = 0 else + refclk when m_test_source = 1 else + inclk_m_from_vco; + + areset_ena_sig <= areset_ipd or sig_stop_vco; + + + pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or + c1_test_source /= -1 or c2_test_source /= -1 or + c3_test_source /= -1 or c4_test_source /= -1) + else false; + + real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0; + m1 : MF_stingray_mn_cntr + port map ( clk => inclk_m, + reset => areset_ena_sig, + cout => fbclk, + initial_value => m_initial_val, + modulus => m_val, + time_delay => m_delay + ); + + -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed + -- in different simulation deltas. + inclk1_tmp <= inclk1_ipd; + + -- Calculate the inclk0 period + PROCESS + VARIABLE inclk0_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1'); + IF (first_inclk0_edge_detect = '0') THEN + first_inclk0_edge_detect <= '1'; + ELSE + last_inclk0_period <= inclk0_period; + inclk0_period_tmp := NOW - last_inclk0_edge; + END IF; + last_inclk0_edge <= NOW; + inclk0_period <= inclk0_period_tmp; + END PROCESS; + + + -- Calculate the inclk1 period + PROCESS + VARIABLE inclk1_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1'); + IF (first_inclk1_edge_detect = '0') THEN + first_inclk1_edge_detect <= '1'; + ELSE + last_inclk1_period <= inclk1_period; + inclk1_period_tmp := NOW - last_inclk1_edge; + END IF; + last_inclk1_edge <= NOW; + inclk1_period <= inclk1_period_tmp; + END PROCESS; + + process (inclk0_ipd, inclk1_tmp, clkswitch_ipd) + variable input_value : std_logic := '0'; + variable current_clock : integer := 0; + variable clk0_count, clk1_count : integer := 0; + variable clk0_is_bad, clk1_is_bad : std_logic := '0'; + variable primary_clk_is_bad : boolean := false; + variable current_clk_is_bad : boolean := false; + variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; + variable switch_over_count : integer := 0; + variable active_clock : std_logic := '0'; + variable external_switch : boolean := false; + variable diff_percent_period : integer := 0; + variable buf : line; + variable switch_clock : boolean := false; + + begin + if (now = 0 ps) then + if (switch_over_type = "manual" and clkswitch_ipd = '1') then + current_clock := 1; + active_clock := '1'; + end if; + end if; + if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then + external_switch := true; + elsif (switch_over_type = "manual") then + if (clkswitch_ipd'event and clkswitch_ipd = '1') then + switch_clock := true; + elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then + switch_clock := false; + end if; + end if; + + if (switch_clock = true) then + if (inclk0_ipd'event or inclk1_tmp'event) then + if (current_clock = 0) then + current_clock := 1; + active_clock := '1'; + clkin <= transport inclk1_tmp; + elsif (current_clock = 1) then + current_clock := 0; + active_clock := '0'; + clkin <= transport inclk0_ipd; + end if; + switch_clock := false; + end if; + end if; + + -- save the current inclk event value + if (inclk0_ipd'event) then + input_value := inclk0_ipd; + elsif (inclk1_tmp'event) then + input_value := inclk1_tmp; + end if; + + -- check if either input clk is bad + if (inclk0_ipd'event and inclk0_ipd = '1') then + clk0_count := clk0_count + 1; + clk0_is_bad := '0'; + clk1_count := 0; + if (clk0_count > 2) then + -- no event on other clk for 2 cycles + clk1_is_bad := '1'; + if (current_clock = 1) then + current_clk_is_bad := true; + end if; + end if; + end if; + if (inclk1_tmp'event and inclk1_tmp = '1') then + clk1_count := clk1_count + 1; + clk1_is_bad := '0'; + clk0_count := 0; + if (clk1_count > 2) then + -- no event on other clk for 2 cycles + clk0_is_bad := '1'; + if (current_clock = 0) then + current_clk_is_bad := true; + end if; + end if; + end if; + + -- check if the bad clk is the primary clock + if (clk0_is_bad = '1') then + primary_clk_is_bad := true; + else + primary_clk_is_bad := false; + end if; + + -- actual switching + if (inclk0_ipd'event and current_clock = 0) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk0_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk0_ipd; + end if; + else + clkin <= transport inclk0_ipd; + end if; + elsif (inclk1_tmp'event and current_clock = 1) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk1_tmp = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk1_tmp; + end if; + else + clkin <= transport inclk1_tmp; + end if; + else + if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then + switch_over_count := switch_over_count + 1; + end if; + if ((input_value = '0')) then + if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then + got_curr_clk_falling_edge_after_clkswitch := false; + + if (areset_ipd = '0') then + if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then + diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period; + elsif (inclk0_period /= 0 ps) then + diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period; + end if; + + if((diff_percent_period > 20)and ( switch_over_type = "auto")) then + WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.")); + writeline(output, buf); + end if; + end if; + + if (current_clock = 0) then + current_clock := 1; + else + current_clock := 0; + end if; + active_clock := not active_clock; + switch_over_count := 0; + external_switch := false; + current_clk_is_bad := false; + else + if(switch_over_type = "auto") then + if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then + current_clock := 1; + active_clock := not active_clock; + end if; + + if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then + current_clock := 0; + active_clock := not active_clock; + end if; + end if; + end if; + + end if; + end if; + + -- schedule outputs + clkbad(0) <= clk0_is_bad; + clkbad(1) <= clk1_is_bad; + activeclock <= active_clock; + + end process; + + + n1 : MF_stingray_mn_cntr + port map ( + clk => clkin, + reset => areset_ipd, + cout => refclk, + initial_value => n_val, + modulus => n_val); + + d1 : MF_stingray_post_divider + generic map ( dpa_divider => dpa_divider) + port map ( + clk => inclk_m_from_vco, + reset => areset_ipd, + cout => icdr_clk); + + +inclk_c0 <= refclk when c0_test_source = 1 else + fbclk when c0_test_source = 0 else + inclk_c_from_vco(0); + + + c0 : MF_stingray_scale_cntr + port map ( + clk => inclk_c0, + reset => areset_ena_sig, + cout => c_clk(0), + initial => c_initial_val(0), + high => c_high_val(0), + low => c_low_val(0), + mode => c_mode_val(0), + ph_tap => c_ph_val(0)); + + inclk_c1 <= refclk when c1_test_source = 1 else + fbclk when c1_test_source = 0 else + c_clk(0) when c1_use_casc_in = "on" else + inclk_c_from_vco(1); + + + c1 : MF_stingray_scale_cntr + port map ( + clk => inclk_c1, + reset => areset_ena_sig, + cout => c_clk(1), + initial => c_initial_val(1), + high => c_high_val(1), + low => c_low_val(1), + mode => c_mode_val(1), + ph_tap => c_ph_val(1)); + +inclk_c2 <= refclk when c2_test_source = 1 else + fbclk when c2_test_source = 0 else + c_clk(1) when c2_use_casc_in = "on" else + inclk_c_from_vco(2); + + c2 : MF_stingray_scale_cntr + port map ( + clk => inclk_c2, + reset => areset_ena_sig, + cout => c_clk(2), + initial => c_initial_val(2), + high => c_high_val(2), + low => c_low_val(2), + mode => c_mode_val(2), + ph_tap => c_ph_val(2)); + + + inclk_c3 <= refclk when c3_test_source = 1 else + fbclk when c3_test_source = 0 else + c_clk(2) when c3_use_casc_in = "on" else + inclk_c_from_vco(3); + + c3 : MF_stingray_scale_cntr + port map ( + clk => inclk_c3, + reset => areset_ena_sig, + cout => c_clk(3), + initial => c_initial_val(3), + high => c_high_val(3), + low => c_low_val(3), + mode => c_mode_val(3), + ph_tap => c_ph_val(3)); + + inclk_c4 <= refclk when c4_test_source = 1 else + fbclk when c4_test_source = 0 else + c_clk(3) when (c4_use_casc_in = "on") else + inclk_c_from_vco(4); + + c4 : MF_stingray_scale_cntr + port map ( + clk => inclk_c4, + reset => areset_ena_sig, + cout => c_clk(4), + initial => c_initial_val(4), + high => c_high_val(4), + low => c_low_val(4), + mode => c_mode_val(4), + ph_tap => c_ph_val(4)); + + + + + + + + + + + + process(scandone_tmp, lock) + begin + if (scandone_tmp'event and (scandone_tmp = '1')) then + pll_has_just_been_reconfigured <= true; + elsif (lock'event and (lock = '1')) then + pll_has_just_been_reconfigured <= false; + end if; + end process; + + process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco) + variable c0_got_first_rising_edge : boolean := false; + variable c0_count : integer := 2; + variable c0_initial_count : integer := 1; + variable c0_tmp, c1_tmp : std_logic := '0'; + variable c1_got_first_rising_edge : boolean := false; + variable c1_count : integer := 2; + variable c1_initial_count : integer := 1; + begin + if (areset_ipd = '1' or sig_stop_vco = '1') then + c0_count := 2; + c1_count := 2; + c0_initial_count := 1; + c1_initial_count := 1; + c0_got_first_rising_edge := false; + c1_got_first_rising_edge := false; + else + if (not c0_got_first_rising_edge) then + if (inclk_c0'event and inclk_c0 = '1') then + if (c0_initial_count = c_initial_val(0)) then + c0_got_first_rising_edge := true; + else + c0_initial_count := c0_initial_count + 1; + end if; + end if; + elsif (inclk_c0'event) then + c0_count := c0_count + 1; + if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then + c0_count := 1; + end if; + end if; + if (inclk_c0'event and inclk_c0 = '0') then + if (c0_count = 1) then + c0_tmp := '1'; + c0_got_first_rising_edge := false; + else + c0_tmp := '0'; + end if; + end if; + + if (not c1_got_first_rising_edge) then + if (inclk_c1'event and inclk_c1 = '1') then + if (c1_initial_count = c_initial_val(1)) then + c1_got_first_rising_edge := true; + else + c1_initial_count := c1_initial_count + 1; + end if; + end if; + elsif (inclk_c1'event) then + c1_count := c1_count + 1; + if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then + c1_count := 1; + end if; + end if; + if (inclk_c1'event and inclk_c1 = '0') then + if (c1_count = 1) then + c1_tmp := '1'; + c1_got_first_rising_edge := false; + else + c1_tmp := '0'; + end if; + end if; + end if; + + end process; + + + locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE + lock; + + + process (scandone_tmp) + variable buf : line; + begin + if (scandone_tmp'event and scandone_tmp = '1') then + if (reconfig_err = false) then + ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note; + write (buf, string'(" N modulus = ")); + write (buf, n_val); + write (buf, string'(" ( ")); + write (buf, n_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M modulus = ")); + write (buf, m_val); + write (buf, string'(" ( ")); + write (buf, m_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M ph_tap = ")); + write (buf, m_ph_val); + write (buf, string'(" ( ")); + write (buf, m_ph_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + for i in 0 to (num_output_cntrs-1) loop + write (buf, clk_num(i)); + write (buf, string'(" : ")); + write (buf, cntrs(i)); + write (buf, string'(" : high = ")); + write (buf, c_high_val(i)); + write (buf, string'(" (")); + write (buf, c_high_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , low = ")); + write (buf, c_low_val(i)); + write (buf, string'(" (")); + write (buf, c_low_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , mode = ")); + write (buf, c_mode_val(i)); + write (buf, string'(" (")); + write (buf, c_mode_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , phase tap = ")); + write (buf, c_ph_val(i)); + write (buf, string'(" (")); + write (buf, c_ph_val_old(i)); + write (buf, string'(") ")); + writeline(output, buf); + end loop; + + IF (pll_reconfig_display_full_setting) THEN + write (buf, string'(" Charge Pump Current (uA) = ")); + write (buf, cp_curr_val); + write (buf, string'(" ( ")); + write (buf, cp_curr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (pF) = ")); + write (buf, lfc_val); + write (buf, string'(" ( ")); + write (buf, lfc_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (Kohm) = ")); + write (buf, lfr_val); + write (buf, string'(" ( ")); + write (buf, lfr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + + ELSE + write (buf, string'(" Charge Pump Current (bit setting) = ")); + write (buf, alt_conv_integer(cp_curr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, cp_curr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (bit setting) = ")); + write (buf, alt_conv_integer(lfc_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfc_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (bit setting) = ")); + write (buf, alt_conv_integer(lfr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + END IF; + cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting); + lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting); + lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting); + else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning; + end if; + end if; + + end process; + + update_conf_latches <= configupdate_ipd; + + + process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd) + variable init : boolean := true; + variable low, high : std_logic_vector(7 downto 0); + variable low_fast, high_fast : std_logic_vector(3 downto 0); + variable mode : string(1 to 6) := "bypass"; + variable is_error : boolean := false; + variable m_tmp, n_tmp : std_logic_vector(8 downto 0); + variable lfr_val_tmp : string(1 to 2) := " "; + + variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1); + variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1); + variable c_mode_val_tmp : str_array(0 to 4); + variable m_val_tmp : integer := 0; + variable c0_rising_edge_transfer_done : boolean := false; + variable c1_rising_edge_transfer_done : boolean := false; + variable c2_rising_edge_transfer_done : boolean := false; + variable c3_rising_edge_transfer_done : boolean := false; + variable c4_rising_edge_transfer_done : boolean := false; + + -- variables for scaling of multiply_by and divide_by values + variable i_clk0_mult_by : integer := 1; + variable i_clk0_div_by : integer := 1; + variable i_clk1_mult_by : integer := 1; + variable i_clk1_div_by : integer := 1; + variable i_clk2_mult_by : integer := 1; + variable i_clk2_div_by : integer := 1; + variable i_clk3_mult_by : integer := 1; + variable i_clk3_div_by : integer := 1; + variable i_clk4_mult_by : integer := 1; + variable i_clk4_div_by : integer := 1; + variable max_d_value : integer := 1; + variable new_multiplier : integer := 1; + + -- internal variables for storing the phase shift number.(used in lvds mode only) + variable i_clk0_phase_shift : integer := 1; + variable i_clk1_phase_shift : integer := 1; + variable i_clk2_phase_shift : integer := 1; + + -- user to advanced variables + + variable max_neg_abs : integer := 0; + variable i_m_initial : integer; + variable i_m : integer := 1; + variable i_n : integer := 1; + variable i_c_high : int_array(0 to 4); + variable i_c_low : int_array(0 to 4); + variable i_c_initial : int_array(0 to 4); + variable i_c_ph : int_array(0 to 4); + variable i_c_mode : str_array(0 to 4); + variable i_m_ph : integer; + variable output_count : integer; + variable new_divisor : integer; + + variable clk0_cntr : string(1 to 6) := " c0"; + variable clk1_cntr : string(1 to 6) := " c1"; + variable clk2_cntr : string(1 to 6) := " c2"; + variable clk3_cntr : string(1 to 6) := " c3"; + variable clk4_cntr : string(1 to 6) := " c4"; + + variable i_clk4_cntr : integer := 4; + variable i_clk3_cntr : integer := 3; + variable i_clk2_cntr : integer := 2; + variable i_clk1_cntr : integer := 1; + variable i_clk0_cntr : integer := 0; + + variable fbk_cntr : string(1 to 2); + variable fbk_cntr_index : integer; + variable start_bit : integer; + variable quiet_time : time := 0 ps; + variable slowest_clk_old : time := 0 ps; + variable slowest_clk_new : time := 0 ps; + + variable i : integer := 0; + variable j : integer := 0; + variable scanread_active_edge : time := 0 ps; + variable got_first_scanclk : boolean := false; + variable scanclk_last_rising_edge : time := 0 ps; + variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + variable index : integer := 0; + variable scan_chain_length : integer := GPP_SCAN_CHAIN; + variable tmp_rem : integer := 0; + variable scanclk_cycles : integer := 0; + variable lfc_tmp : std_logic_vector(1 downto 0); + variable lfr_tmp : std_logic_vector(5 downto 0); + variable lfr_int : integer := 0; + + variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0); + variable buf : line; + variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0'); + variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0'); + + variable clk_index : integer := 0; + + function slowest_clk ( + C0 : integer; C0_mode : string(1 to 6); + C1 : integer; C1_mode : string(1 to 6); + C2 : integer; C2_mode : string(1 to 6); + C3 : integer; C3_mode : string(1 to 6); + C4 : integer; C4_mode : string(1 to 6); + C5 : integer; C5_mode : string(1 to 6); + C6 : integer; C6_mode : string(1 to 6); + C7 : integer; C7_mode : string(1 to 6); + C8 : integer; C8_mode : string(1 to 6); + C9 : integer; C9_mode : string(1 to 6); + refclk : time; m_mod : integer) return time is + variable max_modulus : integer := 1; + variable q_period : time := 0 ps; + variable refclk_int : integer := 0; + begin + if (C0_mode /= "bypass" and C0_mode /= " off") then + max_modulus := C0; + end if; + if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then + max_modulus := C1; + end if; + if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then + max_modulus := C2; + end if; + if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then + max_modulus := C3; + end if; + if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then + max_modulus := C4; + end if; + if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then + max_modulus := C5; + end if; + if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then + max_modulus := C6; + end if; + if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then + max_modulus := C7; + end if; + if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then + max_modulus := C8; + end if; + if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then + max_modulus := C9; + end if; + + refclk_int := refclk / 1 ps; + if (m_mod /= 0) then + q_period := (refclk_int * max_modulus / m_mod) * 1 ps; + end if; + return (2*q_period); + end slowest_clk; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + + function extract_cntr_string (arg:string) return string is + variable str : string(1 to 6) := " c0"; + begin + if (arg = "c0") then + str := " c0"; + elsif (arg = "c1") then + str := " c1"; + elsif (arg = "c2") then + str := " c2"; + elsif (arg = "c3") then + str := " c3"; + elsif (arg = "c4") then + str := " c4"; + elsif (arg = "c5") then + str := " c5"; + elsif (arg = "c6") then + str := " c6"; + elsif (arg = "c7") then + str := " c7"; + elsif (arg = "c8") then + str := " c8"; + elsif (arg = "c9") then + str := " c9"; + else str := " c0"; + + end if; + + return str; + + end extract_cntr_string; + + function extract_cntr_index (arg:string) return integer is + variable index : integer := 0; + begin + if (arg(6) = '0') then + index := 0; + elsif (arg(6) = '1') then + index := 1; + elsif (arg(6) = '2') then + index := 2; + elsif (arg(6) = '3') then + index := 3; + elsif (arg(6) = '4') then + index := 4; + elsif (arg(6) = '5') then + index := 5; + elsif (arg(6) = '6') then + index := 6; + elsif (arg(6) = '7') then + index := 7; + elsif (arg(6) = '8') then + index := 8; + else index := 9; + end if; + + return index; + end extract_cntr_index; + + function output_cntr_num (arg:string) return string is + variable str : string(1 to 6) := "unused"; + begin + if (arg = "c0") then + str := " clk0"; + elsif (arg = "c1") then + str := " clk1"; + elsif (arg = "c2") then + str := " clk2"; + elsif (arg = "c3") then + str := " clk3"; + elsif (arg = "c4") then + str := " clk4"; + elsif (arg = "c5") then + str := " clk5"; + elsif (arg = "c6") then + str := " clk6"; + elsif (arg = "c7") then + str := " clk7"; + elsif (arg = "c8") then + str := " clk8"; + elsif (arg = "c9") then + str := " clk9"; + else str := "unused"; + end if; + return str; + end output_cntr_num; + + begin + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val <= i_c_ph; + END IF; + + if (init) then + if (m = 0) then + clk4_cntr := " c4"; + clk3_cntr := " c3"; + clk2_cntr := " c2"; + clk1_cntr := " c1"; + clk0_cntr := " c0"; + else + clk4_cntr := extract_cntr_string(clk4_counter); + clk3_cntr := extract_cntr_string(clk3_counter); + clk2_cntr := extract_cntr_string(clk2_counter); + clk1_cntr := extract_cntr_string(clk1_counter); + clk0_cntr := extract_cntr_string(clk0_counter); + end if; + + clk_num(4) <= output_cntr_num(clk4_counter); + clk_num(3) <= output_cntr_num(clk3_counter); + clk_num(2) <= output_cntr_num(clk2_counter); + clk_num(1) <= output_cntr_num(clk1_counter); + clk_num(0) <= output_cntr_num(clk0_counter); + + i_clk0_counter <= extract_cntr_index(clk0_cntr); + i_clk1_counter <= extract_cntr_index(clk1_cntr); + i_clk2_counter <= extract_cntr_index(clk2_cntr); + i_clk3_counter <= extract_cntr_index(clk3_cntr); + i_clk4_counter <= extract_cntr_index(clk4_cntr); + + i_clk0_cntr := extract_cntr_index(clk0_cntr); + i_clk1_cntr := extract_cntr_index(clk1_cntr); + i_clk2_cntr := extract_cntr_index(clk2_cntr); + i_clk3_cntr := extract_cntr_index(clk3_cntr); + i_clk4_cntr := extract_cntr_index(clk4_cntr); + + if (m = 0) then -- convert user parameters to advanced + -- set the limit of the divide_by value that can be returned by + -- the following function. + max_d_value := 500; + + -- scale down the multiply_by and divide_by values provided by the design + -- before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + + if (vco_frequency_control = "manual_phase") then + find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step, + i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + i_clk0_div_by, i_clk1_div_by, + i_clk2_div_by, i_clk3_div_by, + i_clk4_div_by, + 1,1,1,1,1, + clk0_counter, clk1_counter, + clk2_counter, clk3_counter, + clk4_counter, + "unused","unused","unused","unused","unused", + i_m, i_n); + elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then + i_n := vco_divide_by; + i_m := vco_multiply_by; + elsif ((dpa_multiply_by /= 0) and (dpa_divide_by /= 0)) then + i_n := dpa_divide_by; + i_m := dpa_multiply_by; + else + i_n := 1; + + if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then + i_m := i_clk0_mult_by; + else + i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + inclk0_input_frequency); + end if; + end if; + + if (pll_type = "flvds") then + -- Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier := clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; + i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; + i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; + else + i_clk0_phase_shift := str2int(clk0_phase_shift); + i_clk1_phase_shift := str2int(clk1_phase_shift); + i_clk2_phase_shift := str2int(clk2_phase_shift); + end if; + + max_neg_abs := maxnegabs(i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + 0, + 0, + 0, + 0, + 0 + ); + i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); + + i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + + + i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + + + + i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); + + i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + + + + else -- m /= 0 + + i_n := n; + i_m := m; + i_m_initial := m_initial; + i_m_ph := m_ph; + i_c_ph(0) := c0_ph; + i_c_ph(1) := c1_ph; + i_c_ph(2) := c2_ph; + i_c_ph(3) := c3_ph; + i_c_ph(4) := c4_ph; + i_c_high(0) := c0_high; + i_c_high(1) := c1_high; + i_c_high(2) := c2_high; + i_c_high(3) := c3_high; + i_c_high(4) := c4_high; + i_c_low(0) := c0_low; + i_c_low(1) := c1_low; + i_c_low(2) := c2_low; + i_c_low(3) := c3_low; + i_c_low(4) := c4_low; + i_c_initial(0) := c0_initial; + i_c_initial(1) := c1_initial; + i_c_initial(2) := c2_initial; + i_c_initial(3) := c3_initial; + i_c_initial(4) := c4_initial; + i_c_mode(0) := translate_string(c0_mode); + i_c_mode(1) := translate_string(c1_mode); + i_c_mode(2) := translate_string(c2_mode); + i_c_mode(3) := translate_string(c3_mode); + i_c_mode(4) := translate_string(c4_mode); + + end if; -- user to advanced conversion. + + m_initial_val <= i_m_initial; + + if ((compensate_clock = "iqtxrxclk") and (m /= 0)) then + + case feedback_source is + when 0 => clk_index := i_clk0_cntr; + when 1 => clk_index := i_clk1_cntr; + when 2 => clk_index := i_clk2_cntr; + when 3 => clk_index := i_clk3_cntr; + when 4 => clk_index := i_clk4_cntr; + when others => + ASSERT FALSE + REPORT "Invalid feedback_source value (" & int2str(feedback_source) & ")!" + SEVERITY ERROR; + end case; + + if(feedback_external_loop_divider = "true") then + m_val <= i_m * (i_c_high(clk_index) + i_c_low(clk_index)) * 2; + m_val_tmp := i_m * (i_c_high(clk_index) + i_c_low(clk_index)) * 2; + else + m_val <= i_m * (i_c_high(clk_index) + i_c_low(clk_index)); + m_val_tmp := i_m * (i_c_high(clk_index) + i_c_low(clk_index)); + end if; + else + m_val <= i_m; + m_val_tmp := i_m; + end if; + + n_val <= i_n; + + + if (i_m = 1) then + m_mode_val <= "bypass"; + else + m_mode_val <= " "; + end if; + if (i_n = 1) then + n_mode_val <= "bypass"; + else + n_mode_val <= " "; + end if; + + m_ph_val <= i_m_ph; + m_ph_initial <= i_m_ph; + + + for i in 0 to 4 loop + if (i_c_mode(i) = "bypass") then + if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then + i_c_high(i) := 16; + i_c_low(i) := 16; + else + i_c_high(i) := 256; + i_c_low(i) := 256; + end if; + end if; + c_ph_val(i) <= i_c_ph(i); + c_initial_val(i) <= i_c_initial(i); + c_high_val(i) <= i_c_high(i); + c_low_val(i) <= i_c_low(i); + c_mode_val(i) <= i_c_mode(i); + c_high_val_tmp(i) := i_c_high(i); + c_hval(i) := i_c_high(i); + c_low_val_tmp(i) := i_c_low(i); + c_lval(i) := i_c_low(i); + c_mode_val_tmp(i) := i_c_mode(i); + c_ph_val_orig(i) <= i_c_ph(i); + c_high_val_hold(i) <= i_c_high(i); + c_low_val_hold(i) <= i_c_low(i); + c_mode_val_hold(i) <= i_c_mode(i); + end loop; + + + + scan_chain_length := SCAN_CHAIN; + + + num_output_cntrs <= 5; + + init := false; + elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then + c0_rising_edge_transfer_done := false; + c1_rising_edge_transfer_done := false; + c2_rising_edge_transfer_done := false; + c3_rising_edge_transfer_done := false; + c4_rising_edge_transfer_done := false; + update_conf_latches_reg <= '0'; + elsif (update_conf_latches'event and update_conf_latches = '1') then + initiate_reconfig <= '1'; + elsif (areset_ipd'event AND areset_ipd = '1') then + if (scandone_tmp = '0') then scandone_tmp <= '1' ; end if; + elsif (scanclk_ipd'event and scanclk_ipd = '1') then + IF (initiate_reconfig = '1') THEN + initiate_reconfig <= '0'; + ASSERT false REPORT "PLL Reprogramming Initiated" severity note; + + update_conf_latches_reg <= update_conf_latches; + reconfig_err <= false; + scandone_tmp <= '0' AFTER scanclk_period; + cp_curr_old <= cp_curr_val; + lfc_old <= lfc_val; + lfr_old <= lfr_val; + vco_old <= vco_cur; + -- LF unused : bit 0,1 + -- LF Capacitance : bits 2,3 : all values are legal + buf_scan_data := scan_data(2 TO 3); + + IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN + lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + ELSE + lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + END IF; + -- LF Resistance : bits 4-8 + -- valid values - 00000,00100,10000,10100,11000,11011,11100,11110 + IF (scan_data(4 TO 8) = "00000") THEN + lfr_val <= "20"; + ELSIF (scan_data(4 TO 8) = "00100") THEN + lfr_val <= "16"; + ELSIF (scan_data(4 TO 8) = "10000") THEN + lfr_val <= "12"; + ELSIF (scan_data(4 TO 8) = "10100") THEN + lfr_val <= "08"; + ELSIF (scan_data(4 TO 8) = "11000") THEN + lfr_val <= "06"; + ELSIF (scan_data(4 TO 8) = "11011") THEN + lfr_val <= "04"; + ELSIF (scan_data(4 TO 8) = "11100") THEN + lfr_val <= "02"; + ELSE + lfr_val <= "01"; + END IF; + + + -- VCO post scale assignment + if (scan_data(9) = '1') then -- vco_post_scale = 1 + i_vco_max <= vco_max/2; + i_vco_min <= vco_min/2; + vco_cur <= 1; + else + i_vco_max <= vco_max; + i_vco_min <= vco_min; + vco_cur <= 2; + end if; + -- CP + -- Bit 9 : CRBYPASS + -- Bit 10-14 : unused + -- Bits 15-17 : all values are legal + + buf_scan_data_2 := scan_data(15 TO 17); + cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2)); + -- save old values for display info. + + cp_curr_val_bit_setting <= scan_data(15 TO 17); + lfc_val_bit_setting <= scan_data(2 TO 3); + lfr_val_bit_setting <= scan_data(4 TO 8); + + m_val_old <= m_val; + n_val_old <= n_val; + m_mode_val_old <= m_mode_val; + n_mode_val_old <= n_mode_val; + WHILE (i < num_output_cntrs) LOOP + c_high_val_old(i) <= c_high_val(i); + c_low_val_old(i) <= c_low_val(i); + c_mode_val_old(i) <= c_mode_val(i); + i := i + 1; + END LOOP; + -- M counter + -- 1. Mode - bypass (bit 18) + + IF (scan_data(18) = '1') THEN + n_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 27) + ELSIF (scan_data(27) = '1') THEN + n_mode_val <= " odd"; + ELSE + n_mode_val <= " even"; + END IF; + + -- 2. High (bit 19-26) + + n_hi := scan_data(19 TO 26); + + -- 4. Low (bit 28-35) + + n_lo := scan_data(28 TO 35); + -- N counter + -- 1. Mode - bypass (bit 36) + + IF (scan_data(36) = '1') THEN + m_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 45) + ELSIF (scan_data(45) = '1') THEN + m_mode_val <= " odd"; + ELSE + m_mode_val <= " even"; + END IF; + + -- 2. High (bit 37-44) + + m_hi := scan_data(37 TO 44); + + -- 4. Low (bit 46-53) + + m_lo := scan_data(46 TO 53); + -- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low + + i := 0; + WHILE (i < num_output_cntrs) LOOP + -- 1. Mode - bypass + + IF (scan_data(54 + i * 18 + 0) = '1') THEN + c_mode_val_tmp(i) := "bypass"; + -- 3. Mode - odd/even + ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN + c_mode_val_tmp(i) := " odd"; + ELSE + c_mode_val_tmp(i) := " even"; + END IF; + -- 2. Hi + + high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8); + c_hval(i) := alt_conv_integer(high); + IF (c_hval(i) /= 0) THEN + c_high_val_tmp(i) := c_hval(i); + ELSE + c_high_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + + -- 4. Low + + low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17); + c_lval(i) := alt_conv_integer(low); + IF (c_lval(i) /= 0) THEN + c_low_val_tmp(i) := c_lval(i); + ELSE + c_low_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + i := i + 1; + END LOOP; + -- Legality Checks + + -- M counter value + IF(scan_data(36) /= '1') THEN + IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (m_hi /= "00000000") THEN + m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo); + ELSE + m_val_tmp := alt_conv_integer("000000001"); + END IF; + ELSE + m_val_tmp := alt_conv_integer("10000000"); + END IF; + -- N counter value + IF(scan_data(18) /= '1') THEN + IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (n_hi /= "00000000") THEN + n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo); + ELSE + n_val <= alt_conv_integer("000000001"); + END IF; + ELSE + n_val <= alt_conv_integer("10000000"); + END IF; + -- TODO : Give warnings/errors in the following cases? + -- 1. Illegal counter values (error) + -- 2. Change of mode (warning) + -- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0) + + END IF; + end if; + + + if (fbclk'event and fbclk = '1') then + m_val <= m_val_tmp; + end if; + + if (update_conf_latches_reg = '1') then + if (scanclk_ipd'event and scanclk_ipd = '1') then + c0_rising_edge_transfer_done := true; + c_high_val(0) <= c_high_val_tmp(0); + c_mode_val(0) <= c_mode_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c1_rising_edge_transfer_done := true; + c_high_val(1) <= c_high_val_tmp(1); + c_mode_val(1) <= c_mode_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c2_rising_edge_transfer_done := true; + c_high_val(2) <= c_high_val_tmp(2); + c_mode_val(2) <= c_mode_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(3) <= c_high_val_tmp(3); + c_mode_val(3) <= c_mode_val_tmp(3); + c3_rising_edge_transfer_done := true; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(4) <= c_high_val_tmp(4); + c_mode_val(4) <= c_mode_val_tmp(4); + c4_rising_edge_transfer_done := true; + end if; + + + + + + end if; + + if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then + c_low_val(0) <= c_low_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then + c_low_val(1) <= c_low_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then + c_low_val(2) <= c_low_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then + c_low_val(3) <= c_low_val_tmp(3); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then + c_low_val(4) <= c_low_val_tmp(4); + end if; + + if (update_phase = '1') then + if (vco_out(0)'event and vco_out(0) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 0) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(1)'event and vco_out(1) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 1) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(2)'event and vco_out(2) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 2) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(3)'event and vco_out(3) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 3) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(4)'event and vco_out(4) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 4) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(5)'event and vco_out(5) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 5) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(6)'event and vco_out(6) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 6) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(7)'event and vco_out(7) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 7) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + end if; + + + + if (vco_out(0)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + inclk_c_from_vco(i) <= vco_out(0); + end if; + end loop; + if (m_ph_val = 0) then + inclk_m_from_vco <= vco_out(0); + end if; + end if; + if (vco_out(1)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + inclk_c_from_vco(i) <= vco_out(1); + end if; + end loop; + if (m_ph_val = 1) then + inclk_m_from_vco <= vco_out(1); + end if; + end if; + if (vco_out(2)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + inclk_c_from_vco(i) <= vco_out(2); + end if; + end loop; + if (m_ph_val = 2) then + inclk_m_from_vco <= vco_out(2); + end if; + end if; + if (vco_out(3)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + inclk_c_from_vco(i) <= vco_out(3); + end if; + end loop; + if (m_ph_val = 3) then + inclk_m_from_vco <= vco_out(3); + end if; + end if; + if (vco_out(4)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + inclk_c_from_vco(i) <= vco_out(4); + end if; + end loop; + if (m_ph_val = 4) then + inclk_m_from_vco <= vco_out(4); + end if; + end if; + if (vco_out(5)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + inclk_c_from_vco(i) <= vco_out(5); + end if; + end loop; + if (m_ph_val = 5) then + inclk_m_from_vco <= vco_out(5); + end if; + end if; + if (vco_out(6)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + inclk_c_from_vco(i) <= vco_out(6); + end if; + end loop; + if (m_ph_val = 6) then + inclk_m_from_vco <= vco_out(6); + end if; + end if; + if (vco_out(7)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + inclk_c_from_vco(i) <= vco_out(7); + end if; + end loop; + if (m_ph_val = 7) then + inclk_m_from_vco <= vco_out(7); + end if; + end if; + + + + + if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then + scanclkena_reg <= scanclkena_ipd; + if (scanclkena_reg = '1') then + scandata_in <= scandata_ipd; + scandata_out <= scandataout_tmp; + end if; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then + if (got_first_scanclk) then + scanclk_period <= now - scanclk_last_rising_edge; + else + got_first_scanclk := true; + end if; + if (scanclkena_reg = '1') then + for j in scan_chain_length - 1 downto 1 loop + scan_data(j) <= scan_data(j-1); + end loop; + scan_data(0) <= scandata_in; + end if; + scanclk_last_rising_edge := now; + end if; + end process; + +-- PLL Phase Reconfiguration + +PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd) + VARIABLE i : INTEGER := 0; + VARIABLE c_ph : INTEGER := 0; + VARIABLE m_ph : INTEGER := 0; + VARIABLE select_counter : INTEGER := 0; +BEGIN + IF (NOW = 0 ps) THEN + m_ph_val_tmp <= m_ph_initial; + END IF; + + -- Latch phase enable (same as phasestep) on neg edge of scan clock + IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN + phasestep_reg <= phasestep_ipd; + END IF; + + IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN + IF (update_phase = '0') THEN + phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart + -- if not, next phasestep cycle is skipped + END IF; + END IF; + -- revert counter phase tap values to POF programmed values + -- if PLL is reset + + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val_tmp <= c_ph_val_orig; + m_ph_val_tmp <= m_ph_initial; + END IF; + + IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN + IF (phasestep_reg = '1') THEN + IF (phasestep_high_count = 1) THEN + phasecounterselect_reg <= phasecounterselect_ipd; + phaseupdown_reg <= phaseupdown_ipd; + -- start reconfiguration + IF (phasecounterselect_ipd < "111") THEN -- no counters selected + IF (phasecounterselect_ipd = "000") THEN + i := 0; + WHILE (i < num_output_cntrs) LOOP + c_ph := c_ph_val(i); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(i) <= c_ph; + i := i + 1; + END LOOP; + ELSIF (phasecounterselect_ipd = "001") THEN + m_ph := m_ph_val; + IF (phaseupdown_ipd = '1') THEN + m_ph := (m_ph + 1) mod num_phase_taps; + ELSIF (m_ph = 0) THEN + m_ph := num_phase_taps - 1; + ELSE + m_ph := (m_ph - 1) mod num_phase_taps; + END IF; + m_ph_val_tmp <= m_ph; + ELSE + select_counter := alt_conv_integer(phasecounterselect_ipd) - 2; + c_ph := c_ph_val(select_counter); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(select_counter) <= c_ph; + END IF; + update_phase <= '1','0' AFTER (0.5 * scanclk_period); + END IF; + END IF; + phasestep_high_count <= phasestep_high_count + 1; + + END IF; + END IF; +END PROCESS; + + scandataout_tmp <= scan_data(SCAN_CHAIN - 2); + + process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk) + variable sched_time : time := 0 ps; + + TYPE time_array is ARRAY (0 to 7) of time; + variable init : boolean := true; + variable refclk_period : time; + variable m_times_vco_period : time; + variable new_m_times_vco_period : time; + + variable phase_shift : time_array := (OTHERS => 0 ps); + variable last_phase_shift : time_array := (OTHERS => 0 ps); + + variable l_index : integer := 1; + variable cycle_to_adjust : integer := 0; + + variable stop_vco : boolean := false; + + variable locked_tmp : std_logic := '0'; + variable pll_is_locked : boolean := false; + variable cycles_pfd_low : integer := 0; + variable cycles_pfd_high : integer := 0; + variable cycles_to_lock : integer := 0; + variable cycles_to_unlock : integer := 0; + + variable got_first_refclk : boolean := false; + variable got_second_refclk : boolean := false; + variable got_first_fbclk : boolean := false; + + variable refclk_time : time := 0 ps; + variable fbclk_time : time := 0 ps; + variable first_fbclk_time : time := 0 ps; + + variable fbclk_period : time := 0 ps; + + variable first_schedule : boolean := true; + + variable vco_val : std_logic := '0'; + variable vco_period_was_phase_adjusted : boolean := false; + variable phase_adjust_was_scheduled : boolean := false; + + variable loop_xplier : integer; + variable loop_initial : integer := 0; + variable loop_ph : integer := 0; + variable loop_time_delay : integer := 0; + + variable initial_delay : time := 0 ps; + variable vco_per : time; + variable tmp_rem : integer; + variable my_rem : integer; + variable fbk_phase : integer := 0; + + variable pull_back_M : integer := 0; + variable total_pull_back : integer := 0; + variable fbk_delay : integer := 0; + + variable offset : time := 0 ps; + + variable tmp_vco_per : integer := 0; + variable high_time : time; + variable low_time : time; + variable time_resolution : time; + + variable got_refclk_posedge : boolean := false; + variable got_fbclk_posedge : boolean := false; + variable inclk_out_of_range : boolean := false; + variable no_warn : boolean := false; + + variable ext_fbk_cntr_modulus : integer := 1; + variable init_clks : boolean := true; + variable pll_is_in_reset : boolean := false; + variable buf : line; + begin + if (init) then + + if (lpm_hint = "time_resolution=100fs") then + time_resolution := 100 fs; + elsif (lpm_hint = "time_resolution=10fs") then + time_resolution := 10 fs; + elsif (lpm_hint = "time_resolution=fs") then + time_resolution := 1 fs; + else + time_resolution := 1 ps; + end if; + + -- jump-start the VCO + -- add 1 ps delay to ensure all signals are updated to initial + -- values + schedule_vco <= transport not schedule_vco after 1 ps; + + init := false; + end if; + + if (schedule_vco'event) then + if (init_clks) then + refclk_period := inclk0_input_frequency * n_val * 1 ps; + + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + init_clks := false; + end if; + sched_time := 0 ps; + for i in 0 to 7 loop + last_phase_shift(i) := phase_shift(i); + end loop; + cycle_to_adjust := 0; + l_index := 1; + m_times_vco_period := new_m_times_vco_period; + end if; + + -- areset was asserted + if (areset_ipd'event and areset_ipd = '1') then + assert false report family_name & " PLL was reset" severity note; + -- reset lock parameters + locked_tmp := '0'; + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + end if; + + + if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then + + if (areset_ipd = '1') then + pll_is_in_reset := true; + got_first_refclk := false; + got_second_refclk := false; + end if; + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after last_phase_shift(i); + phase_shift(i) := 0 ps; + last_phase_shift(i) := 0 ps; + end loop; + + -- reset lock parameters + locked_tmp := '0'; + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + + got_first_refclk := false; + got_second_refclk := false; + refclk_time := 0 ps; + got_first_fbclk := false; + fbclk_time := 0 ps; + first_fbclk_time := 0 ps; + fbclk_period := 0 ps; + + first_schedule := true; + vco_val := '0'; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + + elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then + + -- note areset deassert time + -- note it as refclk_time to prevent false triggering + -- of stop_vco after areset + if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then + refclk_time := now; + pll_is_in_reset := false; + locked_tmp := '0'; + end if; + + -- calculate loop_xplier : this will be different from m_val + -- in external_feedback_mode + loop_xplier := m_val; + loop_initial := m_initial_val - 1; + loop_ph := m_ph_val; + + + -- convert initial value to delay + initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; + + -- convert loop ph_tap to delay + my_rem := (m_times_vco_period/time_resolution) rem loop_xplier; + tmp_vco_per := (m_times_vco_period/time_resolution) / loop_xplier; + if (my_rem /= 0) then + tmp_vco_per := tmp_vco_per + 1; + end if; + fbk_phase := (loop_ph * tmp_vco_per)/8; + + pull_back_M := initial_delay/time_resolution + fbk_phase; + + total_pull_back := pull_back_M; + + if (simulation_type = "timing") then + total_pull_back := total_pull_back + pll_compensation_delay; + end if; + while (total_pull_back > refclk_period/time_resolution) loop + total_pull_back := total_pull_back - refclk_period/time_resolution; + end loop; + + if (total_pull_back > 0) then + offset := refclk_period - (total_pull_back * time_resolution); + end if; + + fbk_delay := total_pull_back - fbk_phase; + if (fbk_delay < 0) then + offset := offset - (fbk_phase * time_resolution); + fbk_delay := total_pull_back; + end if; + + -- assign m_delay + m_delay <= transport fbk_delay after time_resolution; + + my_rem := (m_times_vco_period/time_resolution) rem loop_xplier; + for i in 1 to loop_xplier loop + -- adjust cycles + tmp_vco_per := (m_times_vco_period/time_resolution)/loop_xplier; + if (my_rem /= 0 and l_index <= my_rem) then + tmp_rem := (loop_xplier * l_index) rem my_rem; + cycle_to_adjust := (loop_xplier * l_index) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + if (cycle_to_adjust = i) then + tmp_vco_per := tmp_vco_per + 1; + l_index := l_index + 1; + end if; + + -- calculate high and low periods + vco_per := tmp_vco_per * time_resolution; + high_time := (tmp_vco_per/2) * time_resolution; + if (tmp_vco_per rem 2 /= 0) then + high_time := high_time + time_resolution; + end if; + low_time := vco_per - high_time; + + -- schedule the rising and falling edges + for j in 1 to 2 loop + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + if (first_schedule) then + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + else + vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k)); + end if; + end loop; + end loop; + end loop; + + -- schedule once more + if (first_schedule) then + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + end loop; + first_schedule := false; + end if; + + schedule_vco <= transport not schedule_vco after sched_time; + + if (vco_period_was_phase_adjusted) then + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := true; + + vco_per := m_times_vco_period/loop_xplier; + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + end loop; + end if; + end if; +-- Bypass lock detect + +if (refclk'event and refclk = '1' and areset_ipd = '0') then + if (test_bypass_lock_detect = "on") then + if (pfdena_ipd = '1') then + cycles_pfd_low := 0; + if (pfd_locked = '0') then + if (cycles_pfd_high = lock_high) then + assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning; + pfd_locked <= '1'; + end if; + cycles_pfd_high := cycles_pfd_high + 1; + end if; + end if; + + if (pfdena_ipd = '0') then + cycles_pfd_high := 0; + if (pfd_locked = '1') then + if (cycles_pfd_low = lock_low) then + assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning; + pfd_locked <= '0'; + end if; + cycles_pfd_low := cycles_pfd_low + 1; + end if; + end if; + end if; + + + if (refclk'event and refclk = '1' and areset_ipd = '0') then + got_refclk_posedge := true; + if (not got_first_refclk) then + got_first_refclk := true; + else + got_second_refclk := true; + refclk_period := now - refclk_time; + + -- check if incoming freq. will cause VCO range to be + -- exceeded + if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and + (((refclk_period/1 ps)/loop_xplier > i_vco_max) or + ((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then + if (pll_is_locked) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + if (inclk_out_of_range) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + end if; + elsif (not no_warn) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning; + no_warn := true; + end if; + inclk_out_of_range := true; + else + vco_over <= '0'; + vco_under <= '0'; + inclk_out_of_range := false; + no_warn := false; + end if; + end if; + end if; + + if (stop_vco) then + stop_vco := false; + schedule_vco <= not schedule_vco; + end if; + + refclk_time := now; + else + got_refclk_posedge := false; + end if; + +-- Update M counter value on feedback clock edge + + if (fbclk'event and fbclk = '1') then + got_fbclk_posedge := true; + if (not got_first_fbclk) then + got_first_fbclk := true; + else + fbclk_period := now - fbclk_time; + end if; + + -- need refclk_period here, so initialized to proper value above + if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or + ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or + ( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then + stop_vco := true; + -- reset + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + if (pll_is_locked) then + pll_is_locked := false; + locked_tmp := '0'; + assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note; + if ((i_vco_max = 0) and (i_vco_min = 0)) then + assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note; + end if; + end if; + cycles_to_lock := 0; + cycles_to_unlock := 0; + first_schedule := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + fbclk_time := now; + else + got_fbclk_posedge := false; + end if; + + if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then + + -- now we know actual incoming period + if ( abs(fbclk_time - refclk_time) <= 5 ps or + (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + -- considered in phase + if (cycles_to_lock = real_lock_high) then + if (not pll_is_locked) then + assert false report family_name & " PLL locked to incoming clock" severity note; + end if; + pll_is_locked := true; + locked_tmp := '1'; + cycles_to_unlock := 0; + end if; + -- increment lock counter only if second part of above + -- time check is NOT true + if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then + cycles_to_lock := cycles_to_lock + 1; + end if; + + -- adjust m_times_vco_period + new_m_times_vco_period := refclk_period; + else + -- if locked, begin unlock + if (pll_is_locked) then + cycles_to_unlock := cycles_to_unlock + 1; + if (cycles_to_unlock = lock_low) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + end if; + end if; + if ( abs(refclk_period - fbclk_period) <= 2 ps ) then + -- frequency is still good + if (now = fbclk_time and (not phase_adjust_was_scheduled)) then + if ( abs(fbclk_time - refclk_time) > refclk_period/2) then + new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted := true; + else + new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted := true; + end if; + + end if; + else + phase_adjust_was_scheduled := false; + new_m_times_vco_period := refclk_period; + end if; + end if; + end if; + + if (pfdena_ipd = '0') then + if (pll_is_locked) then + locked_tmp := 'X'; + end if; + pll_is_locked := false; + cycles_to_lock := 0; + end if; + + -- give message only at time of deassertion + if (pfdena_ipd'event and pfdena_ipd = '0') then + assert false report "PFDENA deasserted." severity note; + elsif (pfdena_ipd'event and pfdena_ipd = '1') then + got_first_refclk := false; + got_second_refclk := false; + refclk_time := now; + end if; + + if (reconfig_err) then + lock <= '0'; + else + lock <= locked_tmp; + end if; + + -- signal to calculate quiet_time + sig_refclk_period <= refclk_period; + + if (stop_vco = true) then + sig_stop_vco <= '1'; + else + sig_stop_vco <= '0'; + end if; + + pll_locked <= pll_is_locked; + end process; + + clk0_tmp <= c_clk(i_clk0_counter); + clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE + clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else + 'X'; + + clk1_tmp <= c_clk(i_clk1_counter); + clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE + clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk2_tmp <= c_clk(i_clk2_counter); + clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE + clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk3_tmp <= c_clk(i_clk3_counter); + clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE + clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk4_tmp <= c_clk(i_clk4_counter); + clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE + clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + scandataout <= scandata_out; + scandone <= NOT scandone_tmp; + phasedone <= NOT update_phase; + vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over; + vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under; + fbout <= fbclk; + fref <= refclk; + icdrclk <= icdr_clk; +end vital_pll; +-- END ARCHITECTURE VITAL_PLL + +-- START ENTITY HEADER --------------------------------------------------------- +-- +-- Entity Name : ALTPLL +-- +-- Description : Phase-Locked Loop (PLL) behavioral model. Model supports +-- basic PLL features such as clock division and +-- multiplication, programmable duty cycle and phase shifts, +-- various feedback modes and clock delays. Also supports +-- real-time reconfiguration of PLL "parameters" and clock +-- switchover between the 2 input reference clocks. +-- Up to 10 clock outputs may be used. +-- +-- Limitations : Applicable to Stratix, Stratix-GX, Stratix II and Cyclone II +-- device families only. There is no support in the model for +-- spread-spectrum feature. +-- +-- Expected results : Up to 10 different output clocks, each defined by its own +-- parameters. Locked output (active high) indicates when +-- the PLL locks. clkbad, clkloss and activeclock highlights +-- which clock has gone bad, when clock switchover initiates, +-- and which input clock (0 or 1) is the reference clock, +-- respectively. scandataout is the data output of the serial +-- scan chain. +-- +-- END ENTITY HEADER ----------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.MF_stratix_pll; +use work.MF_stratixii_pll; +use work.MF_stratixiii_pll; +use work.MF_cycloneiii_pll; +use work.MF_cycloneiiigl_pll; +use work.pll_iobuf; + +-- ENTITY DECLARATION +entity altpll is +generic ( + intended_device_family : string := "Stratix" ; + operation_mode : string := "NORMAL" ; + pll_type : string := "AUTO" ; + qualify_conf_done : string := "OFF" ; + compensate_clock : string := "CLK0" ; + scan_chain : string := "LONG"; + primary_clock : string := "inclk0" ; + inclk0_input_frequency : natural; -- required parameter + inclk1_input_frequency : natural := 0; + gate_lock_signal : string := "NO"; + gate_lock_counter : integer := 0; + lock_high : natural := 1; + lock_low : natural := 0; + valid_lock_multiplier : natural := 1; + invalid_lock_multiplier : natural := 5; + switch_over_type : string := "AUTO" ; + switch_over_on_lossclk : string := "OFF" ; + switch_over_on_gated_lock : string := "OFF" ; + enable_switch_over_counter : string := "OFF"; + switch_over_counter : natural := 0; + feedback_source : string := "EXTCLK0" ; + bandwidth : natural := 0; + bandwidth_type : string := "UNUSED"; + lpm_hint : string := "UNUSED"; + spread_frequency : natural := 0; + down_spread : string := "0.0"; + self_reset_on_gated_loss_lock : string := "OFF"; + self_reset_on_loss_lock : string := "OFF"; + lock_window_ui : string := "0.05"; + width_clock : natural := 6; + width_phasecounterselect : natural := 4; + using_fbmimicbidir_port : string := "ON"; + charge_pump_current_bits : natural := 9999; + loop_filter_c_bits : natural := 9999; + loop_filter_r_bits : natural := 9999; + scan_chain_mif_file : string := "UNUSED"; + + -- simulation-only parameters + simulation_type : string := "functional"; + source_is_pll : string := "off"; + skip_vco : string := "off"; + -- internal clock (i.e. clock that feeds the core) specifications + clk9_multiply_by : natural := 1; + clk8_multiply_by : natural := 1; + clk7_multiply_by : natural := 1; + clk6_multiply_by : natural := 1; + clk5_multiply_by : natural := 1; + clk4_multiply_by : natural := 1; + clk3_multiply_by : natural := 1; + clk2_multiply_by : natural := 1; + clk1_multiply_by : natural := 1; + clk0_multiply_by : natural := 1; + clk9_divide_by : natural := 1; + clk8_divide_by : natural := 1; + clk7_divide_by : natural := 1; + clk6_divide_by : natural := 1; + clk5_divide_by : natural := 1; + clk4_divide_by : natural := 1; + clk3_divide_by : natural := 1; + clk2_divide_by : natural := 1; + clk1_divide_by : natural := 1; + clk0_divide_by : natural := 1; + clk9_phase_shift : string := "0"; + clk8_phase_shift : string := "0"; + clk7_phase_shift : string := "0"; + clk6_phase_shift : string := "0"; + clk5_phase_shift : string := "0"; + clk4_phase_shift : string := "0"; + clk3_phase_shift : string := "0"; + clk2_phase_shift : string := "0"; + clk1_phase_shift : string := "0"; + clk0_phase_shift : string := "0"; + clk5_time_delay : string := "0"; + clk4_time_delay : string := "0"; + clk3_time_delay : string := "0"; + clk2_time_delay : string := "0"; + clk1_time_delay : string := "0"; + clk0_time_delay : string := "0"; + clk9_duty_cycle : natural := 50; + clk8_duty_cycle : natural := 50; + clk7_duty_cycle : natural := 50; + clk6_duty_cycle : natural := 50; + clk5_duty_cycle : natural := 50; + clk4_duty_cycle : natural := 50; + clk3_duty_cycle : natural := 50; + clk2_duty_cycle : natural := 50; + clk1_duty_cycle : natural := 50; + clk0_duty_cycle : natural := 50; + clk9_use_even_counter_mode : string := "OFF"; + clk8_use_even_counter_mode : string := "OFF"; + clk7_use_even_counter_mode : string := "OFF"; + clk6_use_even_counter_mode : string := "OFF"; + clk5_use_even_counter_mode : string := "OFF"; + clk4_use_even_counter_mode : string := "OFF"; + clk3_use_even_counter_mode : string := "OFF"; + clk2_use_even_counter_mode : string := "OFF"; + clk1_use_even_counter_mode : string := "OFF"; + clk0_use_even_counter_mode : string := "OFF"; + clk9_use_even_counter_value : string := "OFF"; + clk8_use_even_counter_value : string := "OFF"; + clk7_use_even_counter_value : string := "OFF"; + clk6_use_even_counter_value : string := "OFF"; + clk5_use_even_counter_value : string := "OFF"; + clk4_use_even_counter_value : string := "OFF"; + clk3_use_even_counter_value : string := "OFF"; + clk2_use_even_counter_value : string := "OFF"; + clk1_use_even_counter_value : string := "OFF"; + clk0_use_even_counter_value : string := "OFF"; + + clk2_output_frequency : natural := 0; + clk1_output_frequency : natural := 0; + clk0_output_frequency : natural := 0; + + -- external clock (i.e. clock that feeds pins) specifications + extclk3_multiply_by : natural := 1; + extclk2_multiply_by : natural := 1; + extclk1_multiply_by : natural := 1; + extclk0_multiply_by : natural := 1; + extclk3_divide_by : natural := 1; + extclk2_divide_by : natural := 1; + extclk1_divide_by : natural := 1; + extclk0_divide_by : natural := 1; + extclk3_phase_shift : string := "0"; + extclk2_phase_shift : string := "0"; + extclk1_phase_shift : string := "0"; + extclk0_phase_shift : string := "0"; + extclk3_time_delay : string := "0"; + extclk2_time_delay : string := "0"; + extclk1_time_delay : string := "0"; + extclk0_time_delay : string := "0"; + extclk3_duty_cycle : natural := 50; + extclk2_duty_cycle : natural := 50; + extclk1_duty_cycle : natural := 50; + extclk0_duty_cycle : natural := 50; + + -- The following 4 parameters are for Stratix II pll in lvds mode only + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + sclkout0_phase_shift : string := "0"; + sclkout1_phase_shift : string := "0"; + + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 0; + + + -- advanced user parameters + vco_min : natural := 0; + vco_max : natural := 0; + vco_center : natural := 0; + pfd_min : natural := 0; + pfd_max : natural := 0; + m_initial : natural := 1; + m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself + n : natural := 1; + m2 : natural := 1; + n2 : natural := 1; + ss : natural := 0; + c0_high : natural := 1; + c1_high : natural := 1; + c2_high : natural := 1; + c3_high : natural := 1; + c4_high : natural := 1; + c5_high : natural := 1; + c6_high : natural := 1; + c7_high : natural := 1; + c8_high : natural := 1; + c9_high : natural := 1; + l0_high : natural := 1; + l1_high : natural := 1; + g0_high : natural := 1; + g1_high : natural := 1; + g2_high : natural := 1; + g3_high : natural := 1; + e0_high : natural := 1; + e1_high : natural := 1; + e2_high : natural := 1; + e3_high : natural := 1; + c0_low : natural := 1; + c1_low : natural := 1; + c2_low : natural := 1; + c3_low : natural := 1; + c4_low : natural := 1; + c5_low : natural := 1; + c6_low : natural := 1; + c7_low : natural := 1; + c8_low : natural := 1; + c9_low : natural := 1; + l0_low : natural := 1; + l1_low : natural := 1; + g0_low : natural := 1; + g1_low : natural := 1; + g2_low : natural := 1; + g3_low : natural := 1; + e0_low : natural := 1; + e1_low : natural := 1; + e2_low : natural := 1; + e3_low : natural := 1; + c0_initial : natural := 1; + c1_initial : natural := 1; + c2_initial : natural := 1; + c3_initial : natural := 1; + c4_initial : natural := 1; + c5_initial : natural := 1; + c6_initial : natural := 1; + c7_initial : natural := 1; + c8_initial : natural := 1; + c9_initial : natural := 1; + l0_initial : natural := 1; + l1_initial : natural := 1; + g0_initial : natural := 1; + g1_initial : natural := 1; + g2_initial : natural := 1; + g3_initial : natural := 1; + e0_initial : natural := 1; + e1_initial : natural := 1; + e2_initial : natural := 1; + e3_initial : natural := 1; + c0_mode : string := "bypass" ; + c1_mode : string := "bypass" ; + c2_mode : string := "bypass" ; + c3_mode : string := "bypass" ; + c4_mode : string := "bypass" ; + c5_mode : string := "bypass" ; + c6_mode : string := "bypass" ; + c7_mode : string := "bypass" ; + c8_mode : string := "bypass" ; + c9_mode : string := "bypass" ; + l0_mode : string := "bypass" ; + l1_mode : string := "bypass" ; + g0_mode : string := "bypass" ; + g1_mode : string := "bypass" ; + g2_mode : string := "bypass" ; + g3_mode : string := "bypass" ; + e0_mode : string := "bypass" ; + e1_mode : string := "bypass" ; + e2_mode : string := "bypass" ; + e3_mode : string := "bypass" ; + c0_ph : natural := 0; + c1_ph : natural := 0; + c2_ph : natural := 0; + c3_ph : natural := 0; + c4_ph : natural := 0; + c5_ph : natural := 0; + c6_ph : natural := 0; + c7_ph : natural := 0; + c8_ph : natural := 0; + c9_ph : natural := 0; + l0_ph : natural := 0; + l1_ph : natural := 0; + g0_ph : natural := 0; + g1_ph : natural := 0; + g2_ph : natural := 0; + g3_ph : natural := 0; + e0_ph : natural := 0; + e1_ph : natural := 0; + e2_ph : natural := 0; + e3_ph : natural := 0; + m_ph : natural := 0; + l0_time_delay : natural := 0; + l1_time_delay : natural := 0; + g0_time_delay : natural := 0; + g1_time_delay : natural := 0; + g2_time_delay : natural := 0; + g3_time_delay : natural := 0; + e0_time_delay : natural := 0; + e1_time_delay : natural := 0; + e2_time_delay : natural := 0; + e3_time_delay : natural := 0; + m_time_delay : natural := 0; + n_time_delay : natural := 0; + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + c5_use_casc_in : string := "off"; + c6_use_casc_in : string := "off"; + c7_use_casc_in : string := "off"; + c8_use_casc_in : string := "off"; + c9_use_casc_in : string := "off"; + extclk3_counter : string := "e3" ; + extclk2_counter : string := "e2" ; + extclk1_counter : string := "e1" ; + extclk0_counter : string := "e0" ; + clk9_counter : string := "c9" ; + clk8_counter : string := "c8" ; + clk7_counter : string := "c7" ; + clk6_counter : string := "c6" ; + clk5_counter : string := "l1" ; + clk4_counter : string := "l0" ; + clk3_counter : string := "g3" ; + clk2_counter : string := "g2" ; + clk1_counter : string := "g1" ; + clk0_counter : string := "g0" ; + enable0_counter : string := "l0"; + enable1_counter : string := "l0"; + charge_pump_current : natural := 2; + loop_filter_r : string := " 1.000000"; + loop_filter_c : natural := 5; + vco_post_scale : natural := 0; + vco_frequency_control : string := "AUTO"; + vco_phase_shift_step : natural := 0; + + m_test_source : integer := 5; + c0_test_source : integer := 5; + c1_test_source : integer := 5; + c2_test_source : integer := 5; + c3_test_source : integer := 5; + c4_test_source : integer := 5; + c5_test_source : integer := 5; + c6_test_source : integer := 5; + c7_test_source : integer := 5; + c8_test_source : integer := 5; + c9_test_source : integer := 5; + sim_gate_lock_device_behavior : string := "OFF"; + lpm_type : string := "altpll"; + + -- The following parameter are used to define the connectivity for some + -- of the input and output ports. + port_clkena0 : string := "PORT_CONNECTIVITY"; + port_clkena1 : string := "PORT_CONNECTIVITY"; + port_clkena2 : string := "PORT_CONNECTIVITY"; + port_clkena3 : string := "PORT_CONNECTIVITY"; + port_clkena4 : string := "PORT_CONNECTIVITY"; + port_clkena5 : string := "PORT_CONNECTIVITY"; + port_extclkena0 : string := "PORT_CONNECTIVITY"; + port_extclkena1 : string := "PORT_CONNECTIVITY"; + port_extclkena2 : string := "PORT_CONNECTIVITY"; + port_extclkena3 : string := "PORT_CONNECTIVITY"; + port_extclk0 : string := "PORT_CONNECTIVITY"; + port_extclk1 : string := "PORT_CONNECTIVITY"; + port_extclk2 : string := "PORT_CONNECTIVITY"; + port_extclk3 : string := "PORT_CONNECTIVITY"; + port_clk0 : string := "PORT_CONNECTIVITY"; + port_clk1 : string := "PORT_CONNECTIVITY"; + port_clk2 : string := "PORT_CONNECTIVITY"; + port_clk3 : string := "PORT_CONNECTIVITY"; + port_clk4 : string := "PORT_CONNECTIVITY"; + port_clk5 : string := "PORT_CONNECTIVITY"; + port_clk6 : string := "PORT_CONNECTIVITY"; + port_clk7 : string := "PORT_CONNECTIVITY"; + port_clk8 : string := "PORT_CONNECTIVITY"; + port_clk9 : string := "PORT_CONNECTIVITY"; + port_scandata : string := "PORT_CONNECTIVITY"; + port_scandataout : string := "PORT_CONNECTIVITY"; + port_scandone : string := "PORT_CONNECTIVITY"; + port_sclkout1 : string := "PORT_CONNECTIVITY"; + port_sclkout0 : string := "PORT_CONNECTIVITY"; + port_clkbad0 : string := "PORT_CONNECTIVITY"; + port_clkbad1 : string := "PORT_CONNECTIVITY"; + port_activeclock : string := "PORT_CONNECTIVITY"; + port_clkloss : string := "PORT_CONNECTIVITY"; + port_inclk1 : string := "PORT_CONNECTIVITY"; + port_inclk0 : string := "PORT_CONNECTIVITY"; + port_fbin : string := "PORT_CONNECTIVITY"; + port_fbout : string := "PORT_CONNECTIVITY"; + port_pllena : string := "PORT_CONNECTIVITY"; + port_clkswitch : string := "PORT_CONNECTIVITY"; + port_areset : string := "PORT_CONNECTIVITY"; + port_pfdena : string := "PORT_CONNECTIVITY"; + port_scanclk : string := "PORT_CONNECTIVITY"; + port_scanaclr : string := "PORT_CONNECTIVITY"; + port_scanread : string := "PORT_CONNECTIVITY"; + port_scanwrite : string := "PORT_CONNECTIVITY"; + port_enable0 : string := "PORT_CONNECTIVITY"; + port_enable1 : string := "PORT_CONNECTIVITY"; + port_locked : string := "PORT_CONNECTIVITY"; + port_configupdate : string := "PORT_CONNECTIVITY"; + port_phasecounterselect : string := "PORT_CONNECTIVITY"; + port_phasedone : string := "PORT_CONNECTIVITY"; + port_phasestep : string := "PORT_CONNECTIVITY"; + port_phaseupdown : string := "PORT_CONNECTIVITY"; + port_vcooverrange : string := "PORT_CONNECTIVITY"; + port_vcounderrange : string := "PORT_CONNECTIVITY"; + port_scanclkena : string := "PORT_CONNECTIVITY" +); +port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); -- input clocks, up to 2 can be used + fbin : in std_logic := '0'; -- external feedback port + pllena : in std_logic := '1'; -- PLL enable signal + clkswitch : in std_logic := '0'; -- switch between inclk0 and inclk1 + areset : in std_logic := '0'; -- asynchronous reset + pfdena : in std_logic := '1'; -- enable Phase Frequency Detector (PFD) + clkena : in std_logic_vector(5 downto 0) := (others => '1'); -- enable clk0-clk5 outputs + extclkena : in std_logic_vector(3 downto 0) := (others => '1'); -- enable extclk0-extclk3 outputs + scanclk : in std_logic := '0'; -- clock for scan chain + scanclkena : in std_logic := '1'; + scanaclr : in std_logic := '0'; -- asynchronous clear for the scan chain + scanread : in std_logic := '0'; -- determines when the scan chain can read in data from the scandata port + scanwrite : in std_logic := '0'; -- determines when the scan chain can write out data into pll + scandata : in std_logic := '0'; -- data for the scan chain + comparator : in std_logic := '0'; -- control the enable0 pulse generation to achieve data realignment in lvds. + phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '0'); + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + configupdate : in std_logic := '0'; + fbmimicbidir : inout std_logic := '1'; + + clk : out std_logic_vector(width_clock-1 downto 0); -- internal clock outputs (feeds the core) + extclk : out std_logic_vector(3 downto 0); -- external clock outputs (feeds pins) + clkbad : out std_logic_vector(1 downto 0); -- indicates if inclk0/inclk1 has gone bad + enable0 : out std_logic; -- load enable pulse 0 for lvds + enable1 : out std_logic; -- load enable pulse 1 for lvds + activeclock : out std_logic; -- indicates which input clock is being used + clkloss : out std_logic; -- indicates when clock switchover initiates + locked : out std_logic; -- indicates when the PLL locks + scandataout : out std_logic; -- data output from the scan chain + scandone : out std_logic; -- indicates when pll reconfiguration is complete + sclkout0 : out std_logic; -- serial clock output 0 for lvds + sclkout1 : out std_logic; -- serial clock output 1 for lvds + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fbout : out std_logic; + fref : out std_logic; + icdrclk : out std_logic + +); +end altpll; + +-- BEGINNING OF ARCHITECURE BEHAVIOR +architecture behavior of altpll is + +----------------------- +-- CONSTANT DECLARATION +----------------------- +constant IS_STRATIXII : boolean := FEATURE_FAMILY_STRATIXII(intended_device_family); +constant IS_STRATIXIII : boolean := FEATURE_FAMILY_STRATIXIII(intended_device_family); +constant IS_CYCLONEII : boolean := FEATURE_FAMILY_CYCLONEII(intended_device_family); +constant IS_CYCLONEIII : boolean := FEATURE_FAMILY_CYCLONEIII(intended_device_family) or FEATURE_FAMILY_MAX10(intended_device_family); +constant IS_PIRANHA : boolean := FEATURE_FAMILY_ARRIAIIGX(intended_device_family); +constant IS_STINGRAY : boolean := FEATURE_FAMILY_CYCLONEIVGX(intended_device_family); + +-- converts uppercase parameter values (e.g. "AUTO") to lowercase ("auto") +-- as expected by stratix_pll model +function alpha_tolower (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; + +begin + for i in 1 to string_length loop + case given_string(i) is + when 'A' => result_string(i) := 'a'; + when 'B' => result_string(i) := 'b'; + when 'C' => result_string(i) := 'c'; + when 'D' => result_string(i) := 'd'; + when 'E' => result_string(i) := 'e'; + when 'F' => result_string(i) := 'f'; + when 'G' => result_string(i) := 'g'; + when 'H' => result_string(i) := 'h'; + when 'I' => result_string(i) := 'i'; + when 'J' => result_string(i) := 'j'; + when 'K' => result_string(i) := 'k'; + when 'L' => result_string(i) := 'l'; + when 'M' => result_string(i) := 'm'; + when 'N' => result_string(i) := 'n'; + when 'O' => result_string(i) := 'o'; + when 'P' => result_string(i) := 'p'; + when 'Q' => result_string(i) := 'q'; + when 'R' => result_string(i) := 'r'; + when 'S' => result_string(i) := 's'; + when 'T' => result_string(i) := 't'; + when 'U' => result_string(i) := 'u'; + when 'V' => result_string(i) := 'v'; + when 'W' => result_string(i) := 'w'; + when 'X' => result_string(i) := 'x'; + when 'Y' => result_string(i) := 'y'; + when 'Z' => result_string(i) := 'z'; + when others => result_string(i) := given_string(i); + end case; + end loop; + + return (result_string(1 to string_length)); +end; + +-- The following functions are used to set the default parameters' values for +-- Stratix II if user do not specify these parameters' values. + +function get_clk0_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "g0") then + return "c0"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +-- get feedback source for stratixii +function get_clk1_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "g1") then + return "c1"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + + +function get_clk2_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "g2") then + return "c2"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +function get_clk3_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "g3") then + return "c3"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +function get_clk4_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "l0") then + return "c4"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +function get_clk5_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "l1") then + return "c5"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +function get_clk_counter (counter_value : string; port_usage : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := counter_value'length; + variable result_string : string(1 to 20) := " "; +begin + if (port_usage /= "PORT_USED") then + return "unused"; + else + result_string(1 to string_length) := alpha_tolower(counter_value); + return (result_string(1 to string_length)); + end if; +end; + +function get_enable0_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "l0") then + return "c0"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +function get_enable1_counter (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "l0") then + return "c1"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +-- get feedback source for stratixii +function get_feedback_source (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; +begin + if (given_string = "extclk0") then + return "clk0"; + else + result_string(1 to string_length) := alpha_tolower(given_string); + return (result_string(1 to string_length)); + end if; +end; + +-- get charge_pump_current for stratixii +function get_charge_pump_current (m_value : integer; charge_pump_current : integer) return integer is +begin + if (m_value = 0) then + return 52; + else + return charge_pump_current; + end if; +end; + +-- get loop_filter_c for stratixii +function get_loop_filter_c (m_value : integer; loop_filter_c : integer) return integer is +begin + if (m_value = 0) then + return 16; + else + return loop_filter_c; + end if; +end; + +function get_test_source (test_source : integer) return integer is +begin + if (test_source = 5) then + return -1; + else + return test_source; + end if; +end; + +function get_vco_min_s (vco_min : integer) return integer is +begin + if (vco_min = 0 AND m /= 0 ) then + return 1000; + else + return vco_min; + end if; +end; + +function get_vco_min_s2 (vco_min : integer) return integer is +begin + if (vco_min = 0 AND m /= 0) then + return 700; + else + return vco_min; + end if; +end; + +function get_vco_min_c2 (vco_min : integer) return integer is +begin + if (vco_min = 0 AND m /= 0) then + return 300; + else + return vco_min; + end if; +end; + +function get_vco_min_s3 (vco_min : integer) return integer is +begin + if (vco_min = 0 AND m /= 0) then + return 100; + else + return vco_min; + end if; +end; + +function get_vco_min_c3 (vco_min : integer) return integer is +begin + if (vco_min = 0 AND m /= 0) then + return 200; + else + return vco_min; + end if; +end; + +function get_vco_max (vco_max : integer) return integer is +begin + if (vco_max = 0 AND m /= 0) then + return 3600; + else + return vco_max; + end if; +end; + +-- COMPONENT DECLARATION +component MF_stratix_pll +generic ( + operation_mode : string := "normal"; + pll_type : string := "auto"; + qualify_conf_done : string := "off"; + compensate_clock : string := "clk0"; + scan_chain : string := "long"; + primary_clock : string := "inclk0"; + inclk0_input_frequency : integer := 1000; + inclk1_input_frequency : integer := 1000; + gate_lock_signal : string := "no"; + gate_lock_counter : integer := 0; + valid_lock_multiplier : integer := 1; + invalid_lock_multiplier : integer := 5; + switch_over_on_lossclk : string := "off"; + switch_over_on_gated_lock : string := "off"; + enable_switch_over_counter : string := "off"; + switch_over_counter : integer := 0; + feedback_source : string := "extclk0"; + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + spread_frequency : integer := 0; + down_spread : string := "0.0"; + simulation_type : string := "functional"; + skip_vco : string := "off"; + family_name : string := "Stratix"; + + clk0_multiply_by : integer := 1; + clk0_divide_by : integer := 1; + clk0_phase_shift : string := "0"; + clk0_time_delay : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_multiply_by : integer := 1; + clk1_divide_by : integer := 1; + clk1_phase_shift : string := "0"; + clk1_time_delay : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_multiply_by : integer := 1; + clk2_divide_by : integer := 1; + clk2_phase_shift : string := "0"; + clk2_time_delay : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_multiply_by : integer := 1; + clk3_divide_by : integer := 1; + clk3_phase_shift : string := "0"; + clk3_time_delay : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_multiply_by : integer := 1; + clk4_divide_by : integer := 1; + clk4_phase_shift : string := "0"; + clk4_time_delay : string := "0"; + clk4_duty_cycle : integer := 50; + + clk5_multiply_by : integer := 1; + clk5_divide_by : integer := 1; + clk5_phase_shift : string := "0"; + clk5_time_delay : string := "0"; + clk5_duty_cycle : integer := 50; + + extclk0_multiply_by : integer := 1; + extclk0_divide_by : integer := 1; + extclk0_phase_shift : string := "0"; + extclk0_time_delay : string := "0"; + extclk0_duty_cycle : integer := 50; + + extclk1_multiply_by : integer := 1; + extclk1_divide_by : integer := 1; + extclk1_phase_shift : string := "0"; + extclk1_time_delay : string := "0"; + extclk1_duty_cycle : integer := 50; + + extclk2_multiply_by : integer := 1; + extclk2_divide_by : integer := 1; + extclk2_phase_shift : string := "0"; + extclk2_time_delay : string := "0"; + extclk2_duty_cycle : integer := 50; + + extclk3_multiply_by : integer := 1; + extclk3_divide_by : integer := 1; + extclk3_phase_shift : string := "0"; + extclk3_time_delay : string := "0"; + extclk3_duty_cycle : integer := 50; + + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + pfd_min : integer := 0; + pfd_max : integer := 0; + +-- ADVANCED USER PARAMETERS + m_initial : integer := 1; -- 1-1024 + m : integer := 1; -- 1-1024 + n : integer := 1; -- 1-1024 + m2 : integer := 1; -- 1-1024 + n2 : integer := 1; -- 1-1024 + ss : integer := 0; + + l0_high : integer := 1; -- 1-512 + l0_low : integer := 1; -- 1-512 + l0_initial : integer := 1; -- 1-512 + l0_mode : string := "bypass"; -- bypass,odd,even + l0_ph : integer := 0; + l0_time_delay : integer := 0; + + l1_high : integer := 1; + l1_low : integer := 1; + l1_initial : integer := 1; + l1_mode : string := "bypass"; + l1_ph : integer := 0; + l1_time_delay : integer := 0; + + g0_high : integer := 1; + g0_low : integer := 1; + g0_initial : integer := 1; + g0_mode : string := "bypass"; + g0_ph : integer := 0; + g0_time_delay : integer := 0; + + g1_high : integer := 1; + g1_low : integer := 1; + g1_initial : integer := 1; + g1_mode : string := "bypass"; + g1_ph : integer := 0; + g1_time_delay : integer := 0; + + g2_high : integer := 1; + g2_low : integer := 1; + g2_initial : integer := 1; + g2_mode : string := "bypass"; + g2_ph : integer := 0; + g2_time_delay : integer := 0; + + g3_high : integer := 1; + g3_low : integer := 1; + g3_initial : integer := 1; + g3_mode : string := "bypass"; + g3_ph : integer := 0; + g3_time_delay : integer := 0; + + e0_high : integer := 1; + e0_low : integer := 1; + e0_initial : integer := 1; + e0_mode : string := "bypass"; + e0_ph : integer := 0; + e0_time_delay : integer := 0; + + e1_high : integer := 1; + e1_low : integer := 1; + e1_initial : integer := 1; + e1_mode : string := "bypass"; + e1_ph : integer := 0; + e1_time_delay : integer := 0; + + e2_high : integer := 1; + e2_low : integer := 1; + e2_initial : integer := 1; + e2_mode : string := "bypass"; + e2_ph : integer := 0; + e2_time_delay : integer := 0; + + e3_high : integer := 1; + e3_low : integer := 1; + e3_initial : integer := 1; + e3_mode : string := "bypass"; + e3_ph : integer := 0; + e3_time_delay : integer := 0; + + m_ph : integer := 0; + m_time_delay : integer := 0; + n_time_delay : integer := 0; + + extclk0_counter : string := "e0"; + extclk1_counter : string := "e1"; + extclk2_counter : string := "e2"; + extclk3_counter : string := "e3"; + + clk0_counter : string := "g0"; + clk1_counter : string := "g1"; + clk2_counter : string := "g2"; + clk3_counter : string := "g3"; + clk4_counter : string := "l0"; + clk5_counter : string := "l1"; + + enable0_counter : string := "l0"; + enable1_counter : string := "l0"; + + charge_pump_current : integer := 2; + + loop_filter_r : string := "1.0"; + loop_filter_c : natural := 5 +); +port ( + inclk : in std_logic_vector(1 downto 0) := (OTHERS=>'0'); + fbin : in std_logic := '0'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + clkena : in std_logic_vector(5 downto 0) := (OTHERS=>'1'); + extclkena : in std_logic_vector(3 downto 0) := (OTHERS=>'1'); + scanclk : in std_logic := '0'; + scanaclr : in std_logic := '0'; + scandata : in std_logic := '0'; + clk : out std_logic_vector(5 downto 0); + extclk : out std_logic_vector(3 downto 0); + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + clkloss : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + + -- lvds specific ports + comparator : in std_logic := '0'; + enable0 : out std_logic; + enable1 : out std_logic +); +end component; + + +component MF_stratixii_pll +generic ( + operation_mode : string := "normal"; + pll_type : string := "auto"; + qualify_conf_done : string := "off"; + compensate_clock : string := "clk0"; + inclk0_input_frequency : integer := 1000; + inclk1_input_frequency : integer := 1000; + gate_lock_signal : string := "no"; + gate_lock_counter : integer := 0; + valid_lock_multiplier : integer := 1; + invalid_lock_multiplier : integer := 5; + switch_over_type : string := "auto"; + switch_over_on_lossclk : string := "off"; + switch_over_on_gated_lock : string := "off"; + enable_switch_over_counter : string := "off"; + switch_over_counter : integer := 0; + feedback_source : string := "extclk0"; + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + spread_frequency : integer := 0; + down_spread : string := "0.0"; + self_reset_on_gated_loss_lock : string := "OFF"; + simulation_type : string := "functional"; + family_name : string := "StratixII"; + + clk0_output_frequency : natural := 0; + clk0_multiply_by : integer := 1; + clk0_divide_by : integer := 1; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_output_frequency : natural := 0; + clk1_multiply_by : integer := 1; + clk1_divide_by : integer := 1; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_output_frequency : natural := 0; + clk2_multiply_by : integer := 1; + clk2_divide_by : integer := 1; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_multiply_by : integer := 1; + clk3_divide_by : integer := 1; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_multiply_by : integer := 1; + clk4_divide_by : integer := 1; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + + clk5_multiply_by : integer := 1; + clk5_divide_by : integer := 1; + clk5_phase_shift : string := "0"; + clk5_duty_cycle : integer := 50; + + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + pfd_min : integer := 0; + pfd_max : integer := 0; + +-- ADVANCED USER PARAMETERS + m_initial : integer := 1; -- 1-1024 + m : integer := 1; -- 1-1024 + n : integer := 1; -- 1-1024 + m2 : integer := 1; -- 1-1024 + n2 : integer := 1; -- 1-1024 + ss : integer := 0; + + c0_high : integer := 1; -- 1-512 + c0_low : integer := 1; -- 1-512 + c0_initial : integer := 1; -- 1-512 + c0_mode : string := "bypass"; -- bypass,odd,even + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + c5_high : integer := 1; + c5_low : integer := 1; + c5_initial : integer := 1; + c5_mode : string := "bypass"; + c5_ph : integer := 0; + + m_ph : integer := 0; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + c5_use_casc_in : string := "off"; + + m_test_source : integer := 5; + c0_test_source : integer := 5; + c1_test_source : integer := 5; + c2_test_source : integer := 5; + c3_test_source : integer := 5; + c4_test_source : integer := 5; + c5_test_source : integer := 5; + + clk0_counter : string := "c0"; + clk1_counter : string := "c1"; + clk2_counter : string := "c2"; + clk3_counter : string := "c3"; + clk4_counter : string := "c4"; + clk5_counter : string := "c5"; + + enable0_counter : string := "c0"; + enable1_counter : string := "c0"; + sclkout0_phase_shift : string := "0"; + sclkout1_phase_shift : string := "0"; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + + charge_pump_current : integer := 2; + + loop_filter_r : string := "1.0"; + loop_filter_c : natural := 5; + sim_gate_lock_device_behavior : string := "OFF" +); +port ( + inclk : in std_logic_vector(1 downto 0) := (OTHERS=>'0'); + fbin : in std_logic := '0'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanclk : in std_logic := '1'; + scanread : in std_logic := '1'; + scanwrite : in std_logic := '1'; + scandata : in std_logic := '1'; + testin : in std_logic_vector(3 downto 0) := (OTHERS=>'0'); + clk : out std_logic_vector(5 downto 0); + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + clkloss : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + + -- lvds specific ports + enable0 : out std_logic; + enable1 : out std_logic; + sclkout : out std_logic_vector(1 downto 0) +); +end component; + +component MF_stratixiii_pll +generic ( + operation_mode : string := "normal"; + pll_type : string := "auto"; + compensate_clock : string := "clk0"; + inclk0_input_frequency : integer := 1000; + inclk1_input_frequency : integer := 1000; + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + enable_switch_over_counter : string := "off"; + switch_over_counter : integer := 0; + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := " 0.05"; + lock_c : integer := 4; + simulation_type : string := "functional"; + family_name : string := "StratixIII"; + + clk0_output_frequency : natural := 0; + clk0_multiply_by : integer := 1; + clk0_divide_by : integer := 1; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + clk0_use_even_counter_mode : string := "OFF"; + clk0_use_even_counter_value : string := "OFF"; + + clk1_output_frequency : natural := 0; + clk1_multiply_by : integer := 1; + clk1_divide_by : integer := 1; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + clk1_use_even_counter_mode : string := "OFF"; + clk1_use_even_counter_value : string := "OFF"; + + clk2_output_frequency : natural := 0; + clk2_multiply_by : integer := 1; + clk2_divide_by : integer := 1; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + clk2_use_even_counter_mode : string := "OFF"; + clk2_use_even_counter_value : string := "OFF"; + + clk3_multiply_by : integer := 1; + clk3_divide_by : integer := 1; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + clk3_use_even_counter_mode : string := "OFF"; + clk3_use_even_counter_value : string := "OFF"; + + clk4_multiply_by : integer := 1; + clk4_divide_by : integer := 1; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + clk4_use_even_counter_mode : string := "OFF"; + clk4_use_even_counter_value : string := "OFF"; + + clk5_multiply_by : integer := 1; + clk5_divide_by : integer := 1; + clk5_phase_shift : string := "0"; + clk5_duty_cycle : integer := 50; + clk5_use_even_counter_mode : string := "OFF"; + clk5_use_even_counter_value : string := "OFF"; + + clk6_multiply_by : integer := 1; + clk6_divide_by : integer := 1; + clk6_phase_shift : string := "0"; + clk6_duty_cycle : integer := 50; + clk6_use_even_counter_mode : string := "OFF"; + clk6_use_even_counter_value : string := "OFF"; + + clk7_multiply_by : integer := 1; + clk7_divide_by : integer := 1; + clk7_phase_shift : string := "0"; + clk7_duty_cycle : integer := 50; + clk7_use_even_counter_mode : string := "OFF"; + clk7_use_even_counter_value : string := "OFF"; + + clk8_multiply_by : integer := 1; + clk8_divide_by : integer := 1; + clk8_phase_shift : string := "0"; + clk8_duty_cycle : integer := 50; + clk8_use_even_counter_mode : string := "OFF"; + clk8_use_even_counter_value : string := "OFF"; + + clk9_multiply_by : integer := 1; + clk9_divide_by : integer := 1; + clk9_phase_shift : string := "0"; + clk9_duty_cycle : integer := 50; + clk9_use_even_counter_mode : string := "OFF"; + clk9_use_even_counter_value : string := "OFF"; + + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + pfd_min : integer := 0; + pfd_max : integer := 0; + +-- ADVANCED USER PARAMETERS + m_initial : integer := 1; -- 1-1024 + m : integer := 1; -- 1-1024 + n : integer := 1; -- 1-1024 + + c0_high : integer := 1; -- 1-512 + c0_low : integer := 1; -- 1-512 + c0_initial : integer := 1; -- 1-512 + c0_mode : string := "bypass"; -- bypass,odd,even + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + c5_high : integer := 1; + c5_low : integer := 1; + c5_initial : integer := 1; + c5_mode : string := "bypass"; + c5_ph : integer := 0; + + c6_high : integer := 1; + c6_low : integer := 1; + c6_initial : integer := 1; + c6_mode : string := "bypass"; + c6_ph : integer := 0; + + c7_high : integer := 1; + c7_low : integer := 1; + c7_initial : integer := 1; + c7_mode : string := "bypass"; + c7_ph : integer := 0; + + c8_high : integer := 1; + c8_low : integer := 1; + c8_initial : integer := 1; + c8_mode : string := "bypass"; + c8_ph : integer := 0; + + c9_high : integer := 1; + c9_low : integer := 1; + c9_initial : integer := 1; + c9_mode : string := "bypass"; + c9_ph : integer := 0; + + m_ph : integer := 0; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + c5_use_casc_in : string := "off"; + c6_use_casc_in : string := "off"; + c7_use_casc_in : string := "off"; + c8_use_casc_in : string := "off"; + c9_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + c5_test_source : integer := -1; + c6_test_source : integer := -1; + c7_test_source : integer := -1; + c8_test_source : integer := -1; + c9_test_source : integer := -1; + + clk0_counter : string := "c0"; + clk1_counter : string := "c1"; + clk2_counter : string := "c2"; + clk3_counter : string := "c3"; + clk4_counter : string := "c4"; + clk5_counter : string := "c5"; + clk6_counter : string := "c6"; + clk7_counter : string := "c7"; + clk8_counter : string := "c8"; + clk9_counter : string := "c9"; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 0; + + vco_frequency_control : string := "AUTO"; + vco_phase_shift_step : natural := 0; + charge_pump_current_bits : natural := 9999; + loop_filter_c_bits : natural := 9999; + loop_filter_r_bits : natural := 9999; + + charge_pump_current : integer := 2; + + loop_filter_r : string := "1.0"; + loop_filter_c : natural := 5 +); +port ( + inclk : in std_logic_vector(1 downto 0) := (OTHERS=>'0'); + fbin : in std_logic := '0'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanclk : in std_logic := '1'; + scandata : in std_logic := '1'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + phasecounterselect : in std_logic_vector(3 downto 0) := (OTHERS=>'0'); + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + + clk : out std_logic_vector(9 downto 0); + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fbout : out std_logic +); +end component; + +component MF_cycloneiii_pll +generic ( + operation_mode : string := "normal"; + pll_type : string := "auto"; + compensate_clock : string := "clk0"; + inclk0_input_frequency : integer := 1000; + inclk1_input_frequency : integer := 1000; + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + enable_switch_over_counter : string := "off"; + switch_over_counter : integer := 0; + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_c : integer := 4; + simulation_type : string := "functional"; + family_name : string := "CycloneIII"; + + clk0_output_frequency : natural := 0; + clk0_multiply_by : integer := 1; + clk0_divide_by : integer := 1; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + clk0_use_even_counter_mode : string := "OFF"; + clk0_use_even_counter_value : string := "OFF"; + + clk1_output_frequency : natural := 0; + clk1_multiply_by : integer := 1; + clk1_divide_by : integer := 1; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + clk1_use_even_counter_mode : string := "OFF"; + clk1_use_even_counter_value : string := "OFF"; + + clk2_output_frequency : natural := 0; + clk2_multiply_by : integer := 1; + clk2_divide_by : integer := 1; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + clk2_use_even_counter_mode : string := "OFF"; + clk2_use_even_counter_value : string := "OFF"; + + clk3_multiply_by : integer := 1; + clk3_divide_by : integer := 1; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + clk3_use_even_counter_mode : string := "OFF"; + clk3_use_even_counter_value : string := "OFF"; + + clk4_multiply_by : integer := 1; + clk4_divide_by : integer := 1; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + clk4_use_even_counter_mode : string := "OFF"; + clk4_use_even_counter_value : string := "OFF"; + + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + pfd_min : integer := 0; + pfd_max : integer := 0; + +-- ADVANCED USER PARAMETERS + m_initial : integer := 1; -- 1-1024 + m : integer := 1; -- 1-1024 + n : integer := 1; -- 1-1024 + + c0_high : integer := 1; -- 1-512 + c0_low : integer := 1; -- 1-512 + c0_initial : integer := 1; -- 1-512 + c0_mode : string := "bypass"; -- bypass,odd,even + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + m_ph : integer := 0; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + + clk0_counter : string := "c0"; + clk1_counter : string := "c1"; + clk2_counter : string := "c2"; + clk3_counter : string := "c3"; + clk4_counter : string := "c4"; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + + vco_frequency_control : string := "AUTO"; + vco_phase_shift_step : natural := 0; + charge_pump_current_bits : natural := 9999; + loop_filter_c_bits : natural := 9999; + loop_filter_r_bits : natural := 9999; + + charge_pump_current : integer := 2; + + loop_filter_r : string := "1.0"; + loop_filter_c : natural := 5 +); +port ( + inclk : in std_logic_vector(1 downto 0) := (OTHERS=>'0'); + fbin : in std_logic := '0'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanclk : in std_logic := '1'; + scandata : in std_logic := '1'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + phasecounterselect : in std_logic_vector(2 downto 0) := (OTHERS=>'0'); + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + + clk : out std_logic_vector(4 downto 0); + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fbout : out std_logic +); +end component; + +component MF_cycloneiiigl_pll +generic ( + operation_mode : string := "normal"; + pll_type : string := "auto"; + compensate_clock : string := "clk0"; + inclk0_input_frequency : integer := 1000; + inclk1_input_frequency : integer := 1000; + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + enable_switch_over_counter : string := "off"; + switch_over_counter : integer := 0; + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_c : integer := 4; + simulation_type : string := "functional"; + family_name : string := "CycloneIIIGL"; + lpm_hint : string := "unused"; + + clk0_output_frequency : natural := 0; + clk0_multiply_by : integer := 1; + clk0_divide_by : integer := 1; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + clk0_use_even_counter_mode : string := "OFF"; + clk0_use_even_counter_value : string := "OFF"; + + clk1_output_frequency : natural := 0; + clk1_multiply_by : integer := 1; + clk1_divide_by : integer := 1; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + clk1_use_even_counter_mode : string := "OFF"; + clk1_use_even_counter_value : string := "OFF"; + + clk2_output_frequency : natural := 0; + clk2_multiply_by : integer := 1; + clk2_divide_by : integer := 1; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + clk2_use_even_counter_mode : string := "OFF"; + clk2_use_even_counter_value : string := "OFF"; + + clk3_multiply_by : integer := 1; + clk3_divide_by : integer := 1; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + clk3_use_even_counter_mode : string := "OFF"; + clk3_use_even_counter_value : string := "OFF"; + + clk4_multiply_by : integer := 1; + clk4_divide_by : integer := 1; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + clk4_use_even_counter_mode : string := "OFF"; + clk4_use_even_counter_value : string := "OFF"; + + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 0; + pfd_min : integer := 0; + pfd_max : integer := 0; + +-- ADVANCED USER PARAMETERS + m_initial : integer := 1; -- 1-1024 + m : integer := 1; -- 1-1024 + n : integer := 1; -- 1-1024 + + c0_high : integer := 1; -- 1-512 + c0_low : integer := 1; -- 1-512 + c0_initial : integer := 1; -- 1-512 + c0_mode : string := "bypass"; -- bypass,odd,even + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + m_ph : integer := 0; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + + clk0_counter : string := "c0"; + clk1_counter : string := "c1"; + clk2_counter : string := "c2"; + clk3_counter : string := "c3"; + clk4_counter : string := "c4"; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + + vco_frequency_control : string := "AUTO"; + vco_phase_shift_step : natural := 0; + charge_pump_current_bits : natural := 9999; + loop_filter_c_bits : natural := 9999; + loop_filter_r_bits : natural := 9999; + + charge_pump_current : integer := 2; + + loop_filter_r : string := "1.0"; + loop_filter_c : natural := 5 +); +port ( + inclk : in std_logic_vector(1 downto 0) := (OTHERS=>'0'); + fbin : in std_logic := '0'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanclk : in std_logic := '1'; + scandata : in std_logic := '1'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + phasecounterselect : in std_logic_vector(2 downto 0) := (OTHERS=>'0'); + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + + clk : out std_logic_vector(4 downto 0); + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fbout : out std_logic; + fref : out std_logic; + icdrclk : out std_logic +); +end component; + +component pll_iobuf +port ( + i : in std_logic; + oe : in std_logic; + io : inout std_logic; + o : out std_logic +); +end component; + +signal locked_tmp : std_logic; +signal clk_tmp : std_logic_vector(6 downto 0); + +signal fbin_wire : std_logic; +signal pllena_wire : std_logic; +signal clkswitch_wire : std_logic; +signal areset_wire : std_logic; +signal pfdena_wire : std_logic; +signal scanclk_wire : std_logic; +signal scanaclr_wire : std_logic; +signal scanread_wire : std_logic; +signal scanwrite_wire : std_logic; +signal scandata_wire : std_logic; +signal clkena_wire : std_logic_vector(5 downto 0); +signal extclkena_wire : std_logic_vector(3 downto 0); +signal clk_wire : std_logic_vector(9 downto 0); +signal extclk_wire : std_logic_vector(3 downto 0); +signal clkbad_wire : std_logic_vector(1 downto 0); +signal activeclock_wire : std_logic; +signal clkloss_wire : std_logic; +signal scandataout_wire : std_logic; +signal scandone_wire : std_logic; +signal sclkout0_wire : std_logic; +signal sclkout1_wire : std_logic; +signal locked_wire : std_logic; +signal configupdate_wire : std_logic; +signal phasecounterselect_wire : std_logic_vector(3 downto 0); +signal phasestep_wire : std_logic; +signal phaseupdown_wire : std_logic; +signal scanclkena_wire : std_logic; +signal phasedone_wire : std_logic; +signal vcooverrange_wire : std_logic; +signal vcounderrange_wire : std_logic; +signal fbout_wire : std_logic; +signal iobuf_o : std_logic; +signal stratix3_fbin : std_logic; +signal oe_wire : std_logic; +signal pll_lock_sync : std_logic := '1'; +signal fref_wire : std_logic; +signal icdrclk_wire : std_logic; + +begin + +-- checking for invalid parameters +MSG: process +begin + + if (clk5_multiply_by <= 0) then + ASSERT FALSE + REPORT "The clk5_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk4_multiply_by <= 0) then + ASSERT FALSE + REPORT "The clk4_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk3_multiply_by <= 0) then + ASSERT FALSE + REPORT "The clk3_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk2_multiply_by <= 0) then + ASSERT FALSE + REPORT "The clk2_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk1_multiply_by <= 0) then + ASSERT FALSE + REPORT "The clk1_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk0_multiply_by <= 0) then + ASSERT FALSE + REPORT "The clk0_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk5_divide_by <= 0) then + ASSERT FALSE + REPORT "The clk5_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk4_divide_by <= 0) then + ASSERT FALSE + REPORT "The clk4_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk3_divide_by <= 0) then + ASSERT FALSE + REPORT "The clk3_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk2_divide_by <= 0) then + ASSERT FALSE + REPORT "The clk2_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk1_divide_by <= 0) then + ASSERT FALSE + REPORT "The clk1_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (clk0_divide_by <= 0) then + ASSERT FALSE + REPORT "The clk0_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + + if (extclk3_multiply_by <= 0) then + ASSERT FALSE + REPORT "The extclk3_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (extclk2_multiply_by <= 0) then + ASSERT FALSE + REPORT "The extclk2_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (extclk1_multiply_by <= 0) then + ASSERT FALSE + REPORT "The extclk1_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (extclk0_multiply_by <= 0) then + ASSERT FALSE + REPORT "The extclk0_multiply_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + + if (extclk3_divide_by <= 0) then + ASSERT FALSE + REPORT "The extclk3_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (extclk2_divide_by <= 0) then + ASSERT FALSE + REPORT "The extclk2_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (extclk1_divide_by <= 0) then + ASSERT FALSE + REPORT "The extclk1_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (extclk0_divide_by <= 0) then + ASSERT FALSE + REPORT "The extclk0_divide_by parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if not ((alpha_tolower(primary_clock) = "inclk0") or (alpha_tolower(primary_clock) = "inclk1")) then + ASSERT FALSE + REPORT "The primary clock is set to an illegal value" + SEVERITY ERROR; + end if; + + if ((IS_PIRANHA) and (alpha_tolower(operation_mode) = "external_feedback")) then + ASSERT FALSE + REPORT "The external feedback mode is not supported for the ARRIA II family." + SEVERITY ERROR; + end if; + + if((IS_PIRANHA) and (alpha_tolower(pll_type) = "top_bottom")) then + ASSERT FALSE + REPORT "A pll_type specification is not supported for the ARRIA II family. It will be ignored." + SEVERITY WARNING; + end if; + + if((IS_PIRANHA) and ((port_clk7 /= "PORT_UNUSED") or (port_clk8 /= "PORT_UNUSED") or (port_clk9 /= "PORT_UNUSED"))) then + ASSERT FALSE + REPORT "One or more clock outputs used in the design are not supported in ARRIA II family." + SEVERITY ERROR; + end if; + + wait; +end process MSG; + +-- For fast mode, the stratix pll atom model will give active low signal on locked output. +-- Therefore, need to invert the lock signal for fast mode as in user view, locked signal is +-- always active high. +locked_wire <= (not locked_tmp) when ((not IS_STRATIXII) and + (not IS_CYCLONEII) and + alpha_tolower(pll_type) = "fast") + else (locked_tmp and pll_lock_sync) when (IS_STRATIXIII) or + (IS_CYCLONEIII) + else locked_tmp; + +clkena_wire(0) <= clkena(0) when ((alpha_tolower(pll_type) /= "fast") or + (port_clkena0 = "PORT_USED")) and + (port_clkena0 /= "PORT_UNUSED") + else '1'; +clkena_wire(1) <= clkena(1) when ((alpha_tolower(pll_type) /= "fast") or + (port_clkena1 = "PORT_USED")) and + (port_clkena1 /= "PORT_UNUSED") + else '1'; +clkena_wire(2) <= clkena(2) when ((alpha_tolower(pll_type) /= "fast") or + (port_clkena2 = "PORT_USED")) and + (port_clkena2 /= "PORT_UNUSED") + else '1'; +clkena_wire(3) <= clkena(3) when ((alpha_tolower(pll_type) /= "fast") or + (port_clkena3 = "PORT_USED")) and + (port_clkena3 /= "PORT_UNUSED") + else '1'; +clkena_wire(4) <= clkena(4) when ((alpha_tolower(pll_type) /= "fast") or + (port_clkena4 = "PORT_USED")) and + (port_clkena4 /= "PORT_UNUSED") + else '1'; +clkena_wire(5) <= clkena(5) when ((alpha_tolower(pll_type) /= "fast") or + (port_clkena5 = "PORT_USED")) and + (port_clkena5 /= "PORT_UNUSED") + else '1'; + +extclkena_wire(0) <= extclkena(0) when ((alpha_tolower(pll_type) /= "fast") or + (port_extclkena0 = "PORT_USED")) and + (port_extclkena0 /= "PORT_UNUSED") + else '1'; +extclkena_wire(1) <= extclkena(1) when ((alpha_tolower(pll_type) /= "fast") or + (port_extclkena1 = "PORT_USED")) and + (port_extclkena1 /= "PORT_UNUSED") + else '1'; +extclkena_wire(2) <= extclkena(2) when ((alpha_tolower(pll_type) /= "fast") or + (port_extclkena2 = "PORT_USED")) and + (port_extclkena2 /= "PORT_UNUSED") + else '1'; +extclkena_wire(3) <= extclkena(3) when ((alpha_tolower(pll_type) /= "fast") or + (port_extclkena3 = "PORT_USED")) and + (port_extclkena3 /= "PORT_UNUSED") + else '1'; + +fbin_wire <= fbin when ((port_fbin = "PORT_CONNECTIVITY") or + (port_fbin = "PORT_USED")) + else '0'; + +pllena_wire <= pllena when ((port_pllena = "PORT_CONNECTIVITY") or + (port_pllena = "PORT_USED")) + else '1'; + +clkswitch_wire <= clkswitch when ((port_clkswitch = "PORT_CONNECTIVITY") or + (port_clkswitch = "PORT_USED")) + else '0'; + +areset_wire <= areset when ((port_areset = "PORT_CONNECTIVITY") or + (port_areset = "PORT_USED")) + else '0'; + +pfdena_wire <= pfdena when ((port_pfdena = "PORT_CONNECTIVITY") or + (port_pfdena = "PORT_USED")) + else '1'; + +scanclk_wire <= scanclk when (port_scanclk /= "PORT_UNUSED") + else '0'; + +scandata_wire <= scandata when (port_scandata /= "PORT_UNUSED") + else '0'; + +scanaclr_wire <= scanaclr when (port_scanaclr /= "PORT_UNUSED") + else '0'; + +scanread_wire <= scanread when (port_scanread /= "PORT_UNUSED") + else '0'; + +scanwrite_wire <= scanwrite when (port_scanwrite /= "PORT_UNUSED") + else '0'; + +configupdate_wire <= configupdate when (port_configupdate /= "PORT_UNUSED") + else '0'; + +phasecounterselect_wire(width_phasecounterselect-1 downto 0) <= phasecounterselect(width_phasecounterselect-1 downto 0) when (port_phasecounterselect /= "PORT_UNUSED") + else (others => '0'); + +phasecounterselect3 : if (width_phasecounterselect < 3) generate + phasecounterselect_wire(3) <= '0'; +end generate phasecounterselect3; + +phasestep_wire <= phasestep when (port_phasestep /= "PORT_UNUSED") + else '0'; + +phaseupdown_wire <= phaseupdown when (port_phaseupdown /= "PORT_UNUSED") + else '0'; + +scanclkena_wire <= scanclkena when (port_scanclkena /= "PORT_UNUSED") + else '1'; + +clk(0) <= clk_wire(0) when (port_clk0 /= "PORT_UNUSED") + else '0'; +clk(1) <= clk_wire(1) when (port_clk1 /= "PORT_UNUSED") + else '0'; +clk(2) <= clk_wire(2) when (port_clk2 /= "PORT_UNUSED") + else '0'; +clk(3) <= clk_wire(3) when (port_clk3 /= "PORT_UNUSED") + else '0'; +clk(4) <= clk_wire(4) when (port_clk4 /= "PORT_UNUSED") + else '0'; + +CLK5 : if (width_clock = 6) generate + clk(5) <= clk_wire(5) when (port_clk5 /= "PORT_UNUSED") + else '0'; +end generate CLK5; + +CLK5TO6: if (width_clock = 7) generate + clk(5) <= clk_wire(5) when (port_clk5 /= "PORT_UNUSED") + else '0'; + clk(6) <= clk_wire(6) when (port_clk6 /= "PORT_UNUSED") + else '0'; +end generate CLK5TO6; + +CLK5TO9: if (width_clock = 10) generate + clk(5) <= clk_wire(5) when (port_clk5 /= "PORT_UNUSED") + else '0'; + + clk(6) <= clk_wire(6) when (port_clk6 /= "PORT_UNUSED") + else '0'; + clk(7) <= clk_wire(7) when (port_clk7 /= "PORT_UNUSED") + else '0'; + clk(8) <= clk_wire(8) when (port_clk8 /= "PORT_UNUSED") + else '0'; + clk(9) <= clk_wire(9) when (port_clk9 /= "PORT_UNUSED") + else '0'; +end generate CLK5TO9; + +extclk(0) <= extclk_wire(0) when (port_extclk0 /= "PORT_UNUSED") + else '0'; +extclk(1) <= extclk_wire(1) when (port_extclk1 /= "PORT_UNUSED") + else '0'; +extclk(2) <= extclk_wire(2) when (port_extclk2 /= "PORT_UNUSED") + else '0'; +extclk(3) <= extclk_wire(3) when (port_extclk3 /= "PORT_UNUSED") + else '0'; + +clkbad(0) <= clkbad_wire(0) when (port_clkbad0 /= "PORT_UNUSED") + else '0'; +clkbad(1) <= clkbad_wire(1) when (port_clkbad1 /= "PORT_UNUSED") + else '0'; +activeclock <= activeclock_wire when (port_activeclock /= "PORT_UNUSED") + else '0'; +clkloss <= clkloss_wire when (port_clkloss /= "PORT_UNUSED") + else '0'; + +scandataout <= scandataout_wire when (port_scandataout /= "PORT_UNUSED") + else '0'; + +scandone <= scandone_wire when (port_scandone /= "PORT_UNUSED") + else '0'; + +sclkout0 <= sclkout0_wire when (port_sclkout0 /= "PORT_UNUSED") + else '0'; +sclkout1 <= sclkout1_wire when (port_sclkout1 /= "PORT_UNUSED") + else '0'; + +locked <= locked_wire when (port_locked /= "PORT_UNUSED") + else '0'; + +phasedone <= phasedone_wire when (port_phasedone /= "PORT_UNUSED") + else '0'; + +vcooverrange <= vcooverrange_wire when (port_vcooverrange /= "PORT_UNUSED") + else '0'; + +vcounderrange <= vcounderrange_wire when (port_vcounderrange /= "PORT_UNUSED") + else '0'; + +fbout <= fbout_wire when (port_fbout /= "PORT_UNUSED") + else '0'; + +stratix3_fbin <= iobuf_o when ((using_fbmimicbidir_port = "ON") and (alpha_tolower(operation_mode) = "zero_delay_buffer") and (IS_STRATIXIII) and (not IS_PIRANHA)) + else fbout_wire when ((alpha_tolower(operation_mode) = "zero_delay_buffer") and (IS_PIRANHA)) + else fbin; + +oe_wire <= '1'; + +fref <= fref_wire; + +icdrclk <= icdrclk_wire; + +-- Instantiate stratix_pll +STRATIX_ALTPLL: +if (FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL(intended_device_family) = true) generate + M0: MF_stratix_pll + generic map( + operation_mode => alpha_tolower(operation_mode), + pll_type => alpha_tolower(pll_type), + qualify_conf_done => alpha_tolower(qualify_conf_done), + compensate_clock => alpha_tolower(compensate_clock), + scan_chain => alpha_tolower(scan_chain), + primary_clock => alpha_tolower(primary_clock), + inclk0_input_frequency => inclk0_input_frequency, + inclk1_input_frequency => inclk1_input_frequency, + gate_lock_signal => alpha_tolower(gate_lock_signal), + gate_lock_counter => gate_lock_counter, + valid_lock_multiplier => valid_lock_multiplier, + invalid_lock_multiplier => invalid_lock_multiplier, + switch_over_on_lossclk => alpha_tolower(switch_over_on_lossclk), + switch_over_on_gated_lock => alpha_tolower(switch_over_on_gated_lock), + enable_switch_over_counter => alpha_tolower(enable_switch_over_counter), + switch_over_counter => switch_over_counter, + feedback_source => alpha_tolower(feedback_source), + bandwidth => bandwidth, + bandwidth_type => alpha_tolower(bandwidth_type), + spread_frequency => spread_frequency, + down_spread => down_spread, + simulation_type => alpha_tolower(simulation_type), + skip_vco => alpha_tolower(skip_vco), + family_name => intended_device_family, + + -- internal clock specifications + clk5_multiply_by => clk5_multiply_by, + clk4_multiply_by => clk4_multiply_by, + clk3_multiply_by => clk3_multiply_by, + clk2_multiply_by => clk2_multiply_by, + clk1_multiply_by => clk1_multiply_by, + clk0_multiply_by => clk0_multiply_by, + clk5_divide_by => clk5_divide_by, + clk4_divide_by => clk4_divide_by, + clk3_divide_by => clk3_divide_by, + clk2_divide_by => clk2_divide_by, + clk1_divide_by => clk1_divide_by, + clk0_divide_by => clk0_divide_by, + clk5_phase_shift => clk5_phase_shift, + clk4_phase_shift => clk4_phase_shift, + clk3_phase_shift => clk3_phase_shift, + clk2_phase_shift => clk2_phase_shift, + clk1_phase_shift => clk1_phase_shift, + clk0_phase_shift => clk0_phase_shift, + clk5_time_delay => clk5_time_delay, + clk4_time_delay => clk4_time_delay, + clk3_time_delay => clk3_time_delay, + clk2_time_delay => clk2_time_delay, + clk1_time_delay => clk1_time_delay, + clk0_time_delay => clk0_time_delay, + clk5_duty_cycle => clk5_duty_cycle, + clk4_duty_cycle => clk4_duty_cycle, + clk3_duty_cycle => clk3_duty_cycle, + clk2_duty_cycle => clk2_duty_cycle, + clk1_duty_cycle => clk1_duty_cycle, + clk0_duty_cycle => clk0_duty_cycle, + + -- external clock specifications + extclk3_multiply_by => extclk3_multiply_by, + extclk2_multiply_by => extclk2_multiply_by, + extclk1_multiply_by => extclk1_multiply_by, + extclk0_multiply_by => extclk0_multiply_by, + extclk3_divide_by => extclk3_divide_by, + extclk2_divide_by => extclk2_divide_by, + extclk1_divide_by => extclk1_divide_by, + extclk0_divide_by => extclk0_divide_by, + extclk3_phase_shift => extclk3_phase_shift, + extclk2_phase_shift => extclk2_phase_shift, + extclk1_phase_shift => extclk1_phase_shift, + extclk0_phase_shift => extclk0_phase_shift, + extclk3_time_delay => extclk3_time_delay, + extclk2_time_delay => extclk2_time_delay, + extclk1_time_delay => extclk1_time_delay, + extclk0_time_delay => extclk0_time_delay, + extclk3_duty_cycle => extclk3_duty_cycle, + extclk2_duty_cycle => extclk2_duty_cycle, + extclk1_duty_cycle => extclk1_duty_cycle, + extclk0_duty_cycle => extclk0_duty_cycle, + + -- advanced user parameters + vco_min => get_vco_min_s(vco_min), + vco_max => get_vco_max(vco_max), + vco_center => vco_center, + pfd_min => pfd_min, + pfd_max => pfd_max, + m_initial => m_initial, + m => m, + n => n, + m2 => m2, + n2 => n2, + ss => ss, + l0_high => l0_high, + l1_high => l1_high, + g0_high => g0_high, + g1_high => g1_high, + g2_high => g2_high, + g3_high => g3_high, + e0_high => e0_high, + e1_high => e1_high, + e2_high => e2_high, + e3_high => e3_high, + l0_low => l0_low, + l1_low => l1_low, + g0_low => g0_low, + g1_low => g1_low, + g2_low => g2_low, + g3_low => g3_low, + e0_low => e0_low, + e1_low => e1_low, + e2_low => e2_low, + e3_low => e3_low, + l0_initial => l0_initial, + l1_initial => l1_initial, + g0_initial => g0_initial, + g1_initial => g1_initial, + g2_initial => g2_initial, + g3_initial => g3_initial, + e0_initial => e0_initial, + e1_initial => e1_initial, + e2_initial => e2_initial, + e3_initial => e3_initial, + l0_mode => alpha_tolower(l0_mode), + l1_mode => alpha_tolower(l1_mode), + g0_mode => alpha_tolower(g0_mode), + g1_mode => alpha_tolower(g1_mode), + g2_mode => alpha_tolower(g2_mode), + g3_mode => alpha_tolower(g3_mode), + e0_mode => alpha_tolower(e0_mode), + e1_mode => alpha_tolower(e1_mode), + e2_mode => alpha_tolower(e2_mode), + e3_mode => alpha_tolower(e3_mode), + l0_ph => l0_ph, + l1_ph => l1_ph, + g0_ph => g0_ph, + g1_ph => g1_ph, + g2_ph => g2_ph, + g3_ph => g3_ph, + e0_ph => e0_ph, + e1_ph => e1_ph, + e2_ph => e2_ph, + e3_ph => e3_ph, + m_ph => m_ph, + l0_time_delay => l0_time_delay, + l1_time_delay => l1_time_delay, + g0_time_delay => g0_time_delay, + g1_time_delay => g1_time_delay, + g2_time_delay => g2_time_delay, + g3_time_delay => g3_time_delay, + e0_time_delay => e0_time_delay, + e1_time_delay => e1_time_delay, + e2_time_delay => e2_time_delay, + e3_time_delay => e3_time_delay, + m_time_delay => m_time_delay, + n_time_delay => n_time_delay, + + extclk3_counter => alpha_tolower(extclk3_counter), + extclk2_counter => alpha_tolower(extclk2_counter), + extclk1_counter => alpha_tolower(extclk1_counter), + extclk0_counter => alpha_tolower(extclk0_counter), + clk5_counter => alpha_tolower(clk5_counter), + clk4_counter => alpha_tolower(clk4_counter), + clk3_counter => alpha_tolower(clk3_counter), + clk2_counter => alpha_tolower(clk2_counter), + clk1_counter => alpha_tolower(clk1_counter), + clk0_counter => alpha_tolower(clk0_counter), + enable0_counter => alpha_tolower(enable0_counter), + enable1_counter => alpha_tolower(enable1_counter), + + charge_pump_current => charge_pump_current, + loop_filter_r => loop_filter_r, + loop_filter_c => loop_filter_c + ) + port map ( + inclk => inclk, + fbin => fbin_wire, + ena => pllena_wire, + clkswitch => clkswitch_wire, + areset => areset_wire, + pfdena => pfdena_wire, + clkena => clkena_wire, + extclkena => extclkena_wire, + scanclk => scanclk_wire, + scanaclr => scanaclr_wire, + scandata => scandata_wire, + comparator => comparator, + clk(0) => clk_wire(0), + clk(1) => clk_wire(1), + clk(2) => clk_wire(2), + clk(3) => clk_wire(3), + clk(4) => clk_wire(4), + clk(5) => clk_wire(5), + extclk => extclk_wire, + clkbad => clkbad_wire, + enable0 => enable0, + enable1 => enable1, + activeclock => activeclock_wire, + clkloss => clkloss_wire, + locked => locked_tmp, + scandataout => scandataout_wire + ); +end generate STRATIX_ALTPLL; + +-- Instantiate stratixii_pll +STRATIXII_ALTPLL: +if ((FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL(intended_device_family) = true) and + (FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) = false)) generate + M1 : MF_stratixii_pll + generic map( + operation_mode => alpha_tolower(operation_mode), + pll_type => alpha_tolower(pll_type), + qualify_conf_done => alpha_tolower(qualify_conf_done), + compensate_clock => alpha_tolower(compensate_clock), + inclk0_input_frequency => inclk0_input_frequency, + inclk1_input_frequency => inclk1_input_frequency, + gate_lock_signal => alpha_tolower(gate_lock_signal), + gate_lock_counter => gate_lock_counter, + valid_lock_multiplier => valid_lock_multiplier, + invalid_lock_multiplier => invalid_lock_multiplier, + switch_over_type => alpha_tolower(switch_over_type), + switch_over_on_lossclk => alpha_tolower(switch_over_on_lossclk), + switch_over_on_gated_lock => alpha_tolower(switch_over_on_gated_lock), + enable_switch_over_counter => alpha_tolower(enable_switch_over_counter), + switch_over_counter => switch_over_counter, + feedback_source => get_feedback_source(feedback_source), + bandwidth => bandwidth, + bandwidth_type => alpha_tolower(bandwidth_type), + spread_frequency => spread_frequency, + down_spread => down_spread, + self_reset_on_gated_loss_lock => self_reset_on_gated_loss_lock, + simulation_type => alpha_tolower(simulation_type), + family_name => intended_device_family, + + -- internal clock specifications + clk5_multiply_by => clk5_multiply_by, + clk4_multiply_by => clk4_multiply_by, + clk3_multiply_by => clk3_multiply_by, + clk2_multiply_by => clk2_multiply_by, + clk1_multiply_by => clk1_multiply_by, + clk0_multiply_by => clk0_multiply_by, + clk5_divide_by => clk5_divide_by, + clk4_divide_by => clk4_divide_by, + clk3_divide_by => clk3_divide_by, + clk2_divide_by => clk2_divide_by, + clk1_divide_by => clk1_divide_by, + clk0_divide_by => clk0_divide_by, + clk5_phase_shift => clk5_phase_shift, + clk4_phase_shift => clk4_phase_shift, + clk3_phase_shift => clk3_phase_shift, + clk2_phase_shift => clk2_phase_shift, + clk1_phase_shift => clk1_phase_shift, + clk0_phase_shift => clk0_phase_shift, + clk5_duty_cycle => clk5_duty_cycle, + clk4_duty_cycle => clk4_duty_cycle, + clk3_duty_cycle => clk3_duty_cycle, + clk2_duty_cycle => clk2_duty_cycle, + clk1_duty_cycle => clk1_duty_cycle, + clk0_duty_cycle => clk0_duty_cycle, + + -- advanced user parameters + vco_min => get_vco_min_s2(vco_min), + vco_max => get_vco_max(vco_max), + vco_center => vco_center, + pfd_min => pfd_min, + pfd_max => pfd_max, + m_initial => m_initial, + m => m, + n => n, + m2 => m2, + n2 => n2, + ss => ss, + c0_high => c0_high, + c1_high => c1_high, + c2_high => c2_high, + c3_high => c3_high, + c4_high => c4_high, + c5_high => c5_high, + c0_low => c0_low, + c1_low => c1_low, + c2_low => c2_low, + c3_low => c3_low, + c4_low => c4_low, + c5_low => c5_low, + c0_initial => c0_initial, + c1_initial => c1_initial, + c2_initial => c2_initial, + c3_initial => c3_initial, + c4_initial => c4_initial, + c5_initial => c5_initial, + c0_mode => alpha_tolower(c0_mode), + c1_mode => alpha_tolower(c1_mode), + c2_mode => alpha_tolower(c2_mode), + c3_mode => alpha_tolower(c3_mode), + c4_mode => alpha_tolower(c4_mode), + c5_mode => alpha_tolower(c5_mode), + c0_ph => c0_ph, + c1_ph => c1_ph, + c2_ph => c2_ph, + c3_ph => c3_ph, + c4_ph => c4_ph, + c5_ph => c5_ph, + m_ph => m_ph, + c1_use_casc_in => c1_use_casc_in, + c2_use_casc_in => c2_use_casc_in, + c3_use_casc_in => c3_use_casc_in, + c4_use_casc_in => c4_use_casc_in, + c5_use_casc_in => c5_use_casc_in, + m_test_source => m_test_source, + c0_test_source => c0_test_source, + c1_test_source => c1_test_source, + c2_test_source => c2_test_source, + c3_test_source => c3_test_source, + c4_test_source => c4_test_source, + c5_test_source => c5_test_source, + clk5_counter => get_clk5_counter(clk5_counter), + clk4_counter => get_clk4_counter(clk4_counter), + clk3_counter => get_clk3_counter(clk3_counter), + clk2_counter => get_clk2_counter(clk2_counter), + clk1_counter => get_clk1_counter(clk1_counter), + clk0_counter => get_clk0_counter(clk0_counter), + enable0_counter => get_enable0_counter(enable0_counter), + enable1_counter => get_enable1_counter(enable1_counter), + sclkout0_phase_shift => sclkout0_phase_shift, + sclkout1_phase_shift => sclkout1_phase_shift, + vco_multiply_by => vco_multiply_by, + vco_divide_by => vco_divide_by, + charge_pump_current => get_charge_pump_current(m, charge_pump_current), + loop_filter_r => loop_filter_r, + loop_filter_c => get_loop_filter_c(m, loop_filter_c), + sim_gate_lock_device_behavior => alpha_tolower(sim_gate_lock_device_behavior) + ) + port map ( + inclk => inclk, + fbin => fbin_wire, + ena => pllena_wire, + clkswitch => clkswitch_wire, + areset => areset_wire, + pfdena => pfdena_wire, + scanclk => scanclk_wire, + scanread => scanread_wire, + scanwrite => scanwrite_wire, + scandata => scandata_wire, + clk(0) => clk_wire(0), + clk(1) => clk_wire(1), + clk(2) => clk_wire(2), + clk(3) => clk_wire(3), + clk(4) => clk_wire(4), + clk(5) => clk_wire(5), + clkbad => clkbad_wire, + enable0 => enable0, + enable1 => enable1, + activeclock => activeclock_wire, + clkloss => clkloss_wire, + locked => locked_tmp, + scandataout => scandataout_wire, + scandone => scandone_wire, + sclkout(0) => sclkout0_wire, + sclkout(1) => sclkout1_wire + ); +end generate STRATIXII_ALTPLL; + +-- Instantiate cycloneii_pll +CYCLONEII_ALTPLL: +if (FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family) = true) generate + M3 : MF_stratixii_pll + generic map( + operation_mode => alpha_tolower(operation_mode), + pll_type => alpha_tolower(pll_type), + qualify_conf_done => alpha_tolower(qualify_conf_done), + compensate_clock => alpha_tolower(compensate_clock), + inclk0_input_frequency => inclk0_input_frequency, + inclk1_input_frequency => inclk1_input_frequency, + gate_lock_signal => alpha_tolower(gate_lock_signal), + gate_lock_counter => gate_lock_counter, + valid_lock_multiplier => valid_lock_multiplier, + invalid_lock_multiplier => invalid_lock_multiplier, + switch_over_type => "manual", + switch_over_on_lossclk => alpha_tolower(switch_over_on_lossclk), + switch_over_on_gated_lock => alpha_tolower(switch_over_on_gated_lock), + enable_switch_over_counter => alpha_tolower(enable_switch_over_counter), + switch_over_counter => switch_over_counter, + feedback_source => get_feedback_source(feedback_source), + bandwidth => bandwidth, + bandwidth_type => alpha_tolower(bandwidth_type), + spread_frequency => spread_frequency, + down_spread => down_spread, + simulation_type => alpha_tolower(simulation_type), + family_name => intended_device_family, + + -- internal clock specifications + clk5_multiply_by => clk5_multiply_by, + clk4_multiply_by => clk4_multiply_by, + clk3_multiply_by => clk3_multiply_by, + clk2_multiply_by => clk2_multiply_by, + clk1_multiply_by => clk1_multiply_by, + clk0_multiply_by => clk0_multiply_by, + clk5_divide_by => clk5_divide_by, + clk4_divide_by => clk4_divide_by, + clk3_divide_by => clk3_divide_by, + clk2_divide_by => clk2_divide_by, + clk1_divide_by => clk1_divide_by, + clk0_divide_by => clk0_divide_by, + clk5_phase_shift => clk5_phase_shift, + clk4_phase_shift => clk4_phase_shift, + clk3_phase_shift => clk3_phase_shift, + clk2_phase_shift => clk2_phase_shift, + clk1_phase_shift => clk1_phase_shift, + clk0_phase_shift => clk0_phase_shift, + clk5_duty_cycle => clk5_duty_cycle, + clk4_duty_cycle => clk4_duty_cycle, + clk3_duty_cycle => clk3_duty_cycle, + clk2_duty_cycle => clk2_duty_cycle, + clk1_duty_cycle => clk1_duty_cycle, + clk0_duty_cycle => clk0_duty_cycle, + clk2_output_frequency => clk2_output_frequency, + clk1_output_frequency => clk1_output_frequency, + clk0_output_frequency => clk0_output_frequency, + + -- advanced user parameters + vco_min => get_vco_min_c2(vco_min), + vco_max => get_vco_max(vco_max), + vco_center => vco_center, + pfd_min => pfd_min, + pfd_max => pfd_max, + m_initial => m_initial, + m => m, + n => n, + m2 => m2, + n2 => n2, + ss => ss, + c0_high => c0_high, + c1_high => c1_high, + c2_high => c2_high, + c3_high => c3_high, + c4_high => c4_high, + c5_high => c5_high, + c0_low => c0_low, + c1_low => c1_low, + c2_low => c2_low, + c3_low => c3_low, + c4_low => c4_low, + c5_low => c5_low, + c0_initial => c0_initial, + c1_initial => c1_initial, + c2_initial => c2_initial, + c3_initial => c3_initial, + c4_initial => c4_initial, + c5_initial => c5_initial, + c0_mode => alpha_tolower(c0_mode), + c1_mode => alpha_tolower(c1_mode), + c2_mode => alpha_tolower(c2_mode), + c3_mode => alpha_tolower(c3_mode), + c4_mode => alpha_tolower(c4_mode), + c5_mode => alpha_tolower(c5_mode), + c0_ph => c0_ph, + c1_ph => c1_ph, + c2_ph => c2_ph, + c3_ph => c3_ph, + c4_ph => c4_ph, + c5_ph => c5_ph, + m_ph => m_ph, + c1_use_casc_in => c1_use_casc_in, + c2_use_casc_in => c2_use_casc_in, + c3_use_casc_in => c3_use_casc_in, + c4_use_casc_in => c4_use_casc_in, + c5_use_casc_in => c5_use_casc_in, + clk5_counter => get_clk5_counter(clk5_counter), + clk4_counter => get_clk4_counter(clk4_counter), + clk3_counter => get_clk3_counter(clk3_counter), + clk2_counter => get_clk2_counter(clk2_counter), + clk1_counter => get_clk1_counter(clk1_counter), + clk0_counter => get_clk0_counter(clk0_counter), + enable0_counter => get_enable0_counter(enable0_counter), + enable1_counter => get_enable1_counter(enable1_counter), + sclkout0_phase_shift => sclkout0_phase_shift, + sclkout1_phase_shift => sclkout1_phase_shift, + vco_multiply_by => vco_multiply_by, + vco_divide_by => vco_divide_by, + charge_pump_current => get_charge_pump_current(m, charge_pump_current), + loop_filter_r => loop_filter_r, + loop_filter_c => get_loop_filter_c(m, loop_filter_c), + sim_gate_lock_device_behavior => alpha_tolower(sim_gate_lock_device_behavior) + ) + port map ( + inclk => inclk, + fbin => open, + ena => pllena_wire, + clkswitch => clkswitch_wire, + areset => areset_wire, + pfdena => pfdena_wire, + scanclk => open, + scanread => open, + scanwrite => open, + scandata => open, + clk(0) => clk_wire(0), + clk(1) => clk_wire(1), + clk(2) => clk_wire(2), + clk(3) => clk_tmp(0), + clk(4) => clk_tmp(1), + clk(5) => clk_tmp(2), + clkbad => open, + enable0 => open, + enable1 => open, + activeclock => open, + clkloss => open, + locked => locked_tmp, + scandataout => open, + scandone => open, + sclkout => open + ); +end generate CYCLONEII_ALTPLL; + +-- Instantiate stratixiii_pll +STRATIXIII_ALTPLL: +if (IS_STRATIXIII) generate + M4 : MF_stratixiii_pll + generic map( + operation_mode => alpha_tolower(operation_mode), + pll_type => alpha_tolower(pll_type), + compensate_clock => alpha_tolower(compensate_clock), + inclk0_input_frequency => inclk0_input_frequency, + inclk1_input_frequency => inclk1_input_frequency, + self_reset_on_loss_lock => alpha_tolower(self_reset_on_loss_lock), + switch_over_type => alpha_tolower(switch_over_type), + enable_switch_over_counter => alpha_tolower(enable_switch_over_counter), + switch_over_counter => switch_over_counter, + bandwidth => bandwidth, + bandwidth_type => alpha_tolower(bandwidth_type), + lock_high => lock_high, + lock_low => lock_low, + lock_window_ui => lock_window_ui, + simulation_type => alpha_tolower(simulation_type), + family_name => intended_device_family, + + -- internal clock specifications + clk9_multiply_by => clk9_multiply_by, + clk8_multiply_by => clk8_multiply_by, + clk7_multiply_by => clk7_multiply_by, + clk6_multiply_by => clk6_multiply_by, + clk5_multiply_by => clk5_multiply_by, + clk4_multiply_by => clk4_multiply_by, + clk3_multiply_by => clk3_multiply_by, + clk2_multiply_by => clk2_multiply_by, + clk1_multiply_by => clk1_multiply_by, + clk0_multiply_by => clk0_multiply_by, + clk9_divide_by => clk9_divide_by, + clk8_divide_by => clk8_divide_by, + clk7_divide_by => clk7_divide_by, + clk6_divide_by => clk6_divide_by, + clk5_divide_by => clk5_divide_by, + clk4_divide_by => clk4_divide_by, + clk3_divide_by => clk3_divide_by, + clk2_divide_by => clk2_divide_by, + clk1_divide_by => clk1_divide_by, + clk0_divide_by => clk0_divide_by, + clk9_phase_shift => clk9_phase_shift, + clk8_phase_shift => clk8_phase_shift, + clk7_phase_shift => clk7_phase_shift, + clk6_phase_shift => clk6_phase_shift, + clk5_phase_shift => clk5_phase_shift, + clk4_phase_shift => clk4_phase_shift, + clk3_phase_shift => clk3_phase_shift, + clk2_phase_shift => clk2_phase_shift, + clk1_phase_shift => clk1_phase_shift, + clk0_phase_shift => clk0_phase_shift, + clk9_duty_cycle => clk9_duty_cycle, + clk8_duty_cycle => clk8_duty_cycle, + clk7_duty_cycle => clk7_duty_cycle, + clk6_duty_cycle => clk6_duty_cycle, + clk5_duty_cycle => clk5_duty_cycle, + clk4_duty_cycle => clk4_duty_cycle, + clk3_duty_cycle => clk3_duty_cycle, + clk2_duty_cycle => clk2_duty_cycle, + clk1_duty_cycle => clk1_duty_cycle, + clk0_duty_cycle => clk0_duty_cycle, + + -- advanced user parameters + vco_min => get_vco_min_s3(vco_min), + vco_max => get_vco_max(vco_max), + vco_center => vco_center, + pfd_min => pfd_min, + pfd_max => pfd_max, + m_initial => m_initial, + m => m, + n => n, + c0_high => c0_high, + c1_high => c1_high, + c2_high => c2_high, + c3_high => c3_high, + c4_high => c4_high, + c5_high => c5_high, + c6_high => c6_high, + c7_high => c7_high, + c8_high => c8_high, + c9_high => c9_high, + c0_low => c0_low, + c1_low => c1_low, + c2_low => c2_low, + c3_low => c3_low, + c4_low => c4_low, + c5_low => c5_low, + c6_low => c6_low, + c7_low => c7_low, + c8_low => c8_low, + c9_low => c9_low, + c0_initial => c0_initial, + c1_initial => c1_initial, + c2_initial => c2_initial, + c3_initial => c3_initial, + c4_initial => c4_initial, + c5_initial => c5_initial, + c6_initial => c6_initial, + c7_initial => c7_initial, + c8_initial => c8_initial, + c9_initial => c9_initial, + c0_mode => alpha_tolower(c0_mode), + c1_mode => alpha_tolower(c1_mode), + c2_mode => alpha_tolower(c2_mode), + c3_mode => alpha_tolower(c3_mode), + c4_mode => alpha_tolower(c4_mode), + c5_mode => alpha_tolower(c5_mode), + c6_mode => alpha_tolower(c6_mode), + c7_mode => alpha_tolower(c7_mode), + c8_mode => alpha_tolower(c8_mode), + c9_mode => alpha_tolower(c9_mode), + c0_ph => c0_ph, + c1_ph => c1_ph, + c2_ph => c2_ph, + c3_ph => c3_ph, + c4_ph => c4_ph, + c5_ph => c5_ph, + c6_ph => c6_ph, + c7_ph => c7_ph, + c8_ph => c8_ph, + c9_ph => c9_ph, + m_ph => m_ph, + c1_use_casc_in => c1_use_casc_in, + c2_use_casc_in => c2_use_casc_in, + c3_use_casc_in => c3_use_casc_in, + c4_use_casc_in => c4_use_casc_in, + c5_use_casc_in => c5_use_casc_in, + c6_use_casc_in => c6_use_casc_in, + c7_use_casc_in => c7_use_casc_in, + c8_use_casc_in => c8_use_casc_in, + c9_use_casc_in => c9_use_casc_in, + m_test_source => get_test_source(m_test_source), + c0_test_source => get_test_source(c0_test_source), + c1_test_source => get_test_source(c1_test_source), + c2_test_source => get_test_source(c2_test_source), + c3_test_source => get_test_source(c3_test_source), + c4_test_source => get_test_source(c4_test_source), + c5_test_source => get_test_source(c5_test_source), + c6_test_source => get_test_source(c6_test_source), + c7_test_source => get_test_source(c7_test_source), + c8_test_source => get_test_source(c8_test_source), + c9_test_source => get_test_source(c9_test_source), + clk9_counter => get_clk_counter(clk9_counter, port_clk9), + clk8_counter => get_clk_counter(clk8_counter, port_clk8), + clk7_counter => get_clk_counter(clk7_counter, port_clk7), + clk6_counter => get_clk_counter(clk6_counter, port_clk6), + clk5_counter => get_clk_counter(get_clk5_counter(clk5_counter), port_clk5), + clk4_counter => get_clk_counter(get_clk4_counter(clk4_counter), port_clk4), + clk3_counter => get_clk_counter(get_clk3_counter(clk3_counter), port_clk3), + clk2_counter => get_clk_counter(get_clk2_counter(clk2_counter), port_clk2), + clk1_counter => get_clk_counter(get_clk1_counter(clk1_counter), port_clk1), + clk0_counter => get_clk_counter(get_clk0_counter(clk0_counter), port_clk0), + dpa_multiply_by => dpa_multiply_by, + dpa_divide_by => dpa_divide_by, + dpa_divider => dpa_divider, + vco_multiply_by => vco_multiply_by, + vco_divide_by => vco_divide_by, + vco_frequency_control => alpha_tolower(vco_frequency_control), + vco_phase_shift_step => vco_phase_shift_step, + charge_pump_current => charge_pump_current, + loop_filter_r => loop_filter_r, + loop_filter_c => loop_filter_c, + charge_pump_current_bits => charge_pump_current_bits, + loop_filter_c_bits => loop_filter_c_bits, + loop_filter_r_bits => loop_filter_r_bits, + clk9_use_even_counter_mode => alpha_tolower(clk0_use_even_counter_mode), + clk8_use_even_counter_mode => alpha_tolower(clk1_use_even_counter_mode), + clk7_use_even_counter_mode => alpha_tolower(clk2_use_even_counter_mode), + clk6_use_even_counter_mode => alpha_tolower(clk3_use_even_counter_mode), + clk5_use_even_counter_mode => alpha_tolower(clk4_use_even_counter_mode), + clk4_use_even_counter_mode => alpha_tolower(clk5_use_even_counter_mode), + clk3_use_even_counter_mode => alpha_tolower(clk6_use_even_counter_mode), + clk2_use_even_counter_mode => alpha_tolower(clk7_use_even_counter_mode), + clk1_use_even_counter_mode => alpha_tolower(clk8_use_even_counter_mode), + clk0_use_even_counter_mode => alpha_tolower(clk9_use_even_counter_mode), + clk9_use_even_counter_value => alpha_tolower(clk9_use_even_counter_value), + clk8_use_even_counter_value => alpha_tolower(clk8_use_even_counter_value), + clk7_use_even_counter_value => alpha_tolower(clk7_use_even_counter_value), + clk6_use_even_counter_value => alpha_tolower(clk6_use_even_counter_value), + clk5_use_even_counter_value => alpha_tolower(clk5_use_even_counter_value), + clk4_use_even_counter_value => alpha_tolower(clk4_use_even_counter_value), + clk3_use_even_counter_value => alpha_tolower(clk3_use_even_counter_value), + clk2_use_even_counter_value => alpha_tolower(clk2_use_even_counter_value), + clk1_use_even_counter_value => alpha_tolower(clk1_use_even_counter_value), + clk0_use_even_counter_value => alpha_tolower(clk0_use_even_counter_value) + ) + port map ( + inclk => inclk, + fbin => stratix3_fbin, + clkswitch => clkswitch_wire, + areset => areset_wire, + pfdena => pfdena_wire, + scanclk => scanclk_wire, + scandata => scandata_wire, + scanclkena => scanclkena_wire, + phasecounterselect => phasecounterselect_wire, + phaseupdown => phaseupdown_wire, + phasestep => phasestep_wire, + configupdate => configupdate_wire, + clk(0) => clk_wire(0), + clk(1) => clk_wire(1), + clk(2) => clk_wire(2), + clk(3) => clk_wire(3), + clk(4) => clk_wire(4), + clk(5) => clk_wire(5), + clk(6) => clk_wire(6), + clk(7) => clk_wire(7), + clk(8) => clk_wire(8), + clk(9) => clk_wire(9), + clkbad => clkbad_wire, + activeclock => activeclock_wire, + locked => locked_tmp, + scandataout => scandataout_wire, + scandone => scandone_wire, + phasedone => phasedone_wire, + vcooverrange => vcooverrange_wire, + vcounderrange => vcounderrange_wire, + fbout => fbout_wire + ); +end generate STRATIXIII_ALTPLL; + +-- Instantiate cycloneiii_pll +CYCLONEIII_ALTPLL: +if ((not IS_STINGRAY) and + (IS_CYCLONEIII)) generate + M5 : MF_cycloneiii_pll + generic map( + operation_mode => alpha_tolower(operation_mode), + pll_type => alpha_tolower(pll_type), + compensate_clock => alpha_tolower(compensate_clock), + inclk0_input_frequency => inclk0_input_frequency, + inclk1_input_frequency => inclk1_input_frequency, + self_reset_on_loss_lock => alpha_tolower(self_reset_on_loss_lock), + switch_over_type => alpha_tolower(switch_over_type), + enable_switch_over_counter => alpha_tolower(enable_switch_over_counter), + switch_over_counter => switch_over_counter, + bandwidth => bandwidth, + bandwidth_type => alpha_tolower(bandwidth_type), + lock_high => lock_high, + lock_low => lock_low, + lock_window_ui => lock_window_ui, + simulation_type => alpha_tolower(simulation_type), + family_name => intended_device_family, + + -- internal clock specifications + clk4_multiply_by => clk4_multiply_by, + clk3_multiply_by => clk3_multiply_by, + clk2_multiply_by => clk2_multiply_by, + clk1_multiply_by => clk1_multiply_by, + clk0_multiply_by => clk0_multiply_by, + clk4_divide_by => clk4_divide_by, + clk3_divide_by => clk3_divide_by, + clk2_divide_by => clk2_divide_by, + clk1_divide_by => clk1_divide_by, + clk0_divide_by => clk0_divide_by, + clk4_phase_shift => clk4_phase_shift, + clk3_phase_shift => clk3_phase_shift, + clk2_phase_shift => clk2_phase_shift, + clk1_phase_shift => clk1_phase_shift, + clk0_phase_shift => clk0_phase_shift, + clk4_duty_cycle => clk4_duty_cycle, + clk3_duty_cycle => clk3_duty_cycle, + clk2_duty_cycle => clk2_duty_cycle, + clk1_duty_cycle => clk1_duty_cycle, + clk0_duty_cycle => clk0_duty_cycle, + + -- advanced user parameters + vco_min => get_vco_min_c3(vco_min), + vco_max => get_vco_max(vco_max), + vco_center => vco_center, + pfd_min => pfd_min, + pfd_max => pfd_max, + m_initial => m_initial, + m => m, + n => n, + c0_high => c0_high, + c1_high => c1_high, + c2_high => c2_high, + c3_high => c3_high, + c4_high => c4_high, + c0_low => c0_low, + c1_low => c1_low, + c2_low => c2_low, + c3_low => c3_low, + c4_low => c4_low, + c0_initial => c0_initial, + c1_initial => c1_initial, + c2_initial => c2_initial, + c3_initial => c3_initial, + c4_initial => c4_initial, + c0_mode => alpha_tolower(c0_mode), + c1_mode => alpha_tolower(c1_mode), + c2_mode => alpha_tolower(c2_mode), + c3_mode => alpha_tolower(c3_mode), + c4_mode => alpha_tolower(c4_mode), + c0_ph => c0_ph, + c1_ph => c1_ph, + c2_ph => c2_ph, + c3_ph => c3_ph, + c4_ph => c4_ph, + m_ph => m_ph, + c1_use_casc_in => c1_use_casc_in, + c2_use_casc_in => c2_use_casc_in, + c3_use_casc_in => c3_use_casc_in, + c4_use_casc_in => c4_use_casc_in, + m_test_source => get_test_source(m_test_source), + c0_test_source => get_test_source(c0_test_source), + c1_test_source => get_test_source(c1_test_source), + c2_test_source => get_test_source(c2_test_source), + c3_test_source => get_test_source(c3_test_source), + c4_test_source => get_test_source(c4_test_source), + clk4_counter => get_clk_counter(get_clk4_counter(clk4_counter), port_clk4), + clk3_counter => get_clk_counter(get_clk3_counter(clk3_counter), port_clk3), + clk2_counter => get_clk_counter(get_clk2_counter(clk2_counter), port_clk2), + clk1_counter => get_clk_counter(get_clk1_counter(clk1_counter), port_clk1), + clk0_counter => get_clk_counter(get_clk0_counter(clk0_counter), port_clk0), + vco_multiply_by => vco_multiply_by, + vco_divide_by => vco_divide_by, + vco_frequency_control => alpha_tolower(vco_frequency_control), + vco_phase_shift_step => vco_phase_shift_step, + charge_pump_current => charge_pump_current, + loop_filter_r => loop_filter_r, + loop_filter_c => loop_filter_c, + charge_pump_current_bits => charge_pump_current_bits, + loop_filter_c_bits => loop_filter_c_bits, + loop_filter_r_bits => loop_filter_r_bits, + clk4_use_even_counter_mode => alpha_tolower(clk5_use_even_counter_mode), + clk3_use_even_counter_mode => alpha_tolower(clk6_use_even_counter_mode), + clk2_use_even_counter_mode => alpha_tolower(clk7_use_even_counter_mode), + clk1_use_even_counter_mode => alpha_tolower(clk8_use_even_counter_mode), + clk0_use_even_counter_mode => alpha_tolower(clk9_use_even_counter_mode), + clk4_use_even_counter_value => alpha_tolower(clk4_use_even_counter_value), + clk3_use_even_counter_value => alpha_tolower(clk3_use_even_counter_value), + clk2_use_even_counter_value => alpha_tolower(clk2_use_even_counter_value), + clk1_use_even_counter_value => alpha_tolower(clk1_use_even_counter_value), + clk0_use_even_counter_value => alpha_tolower(clk0_use_even_counter_value) + ) + port map ( + inclk => inclk, + fbin => fbin_wire, + clkswitch => clkswitch_wire, + areset => areset_wire, + pfdena => pfdena_wire, + scanclk => scanclk, + scandata => scandata, + scanclkena => scanclkena_wire, + configupdate => configupdate_wire, + phasecounterselect => phasecounterselect_wire(2 downto 0), + phaseupdown => phaseupdown_wire, + phasestep => phasestep_wire, + clk(0) => clk_wire(0), + clk(1) => clk_wire(1), + clk(2) => clk_wire(2), + clk(3) => clk_wire(3), + clk(4) => clk_wire(4), + clkbad => clkbad_wire, + activeclock => activeclock_wire, + locked => locked_tmp, + scandataout => scandataout_wire, + scandone => scandone_wire, + phasedone => phasedone_wire, + vcooverrange => vcooverrange_wire, + vcounderrange => vcounderrange_wire, + fbout => fbout_wire + ); +end generate CYCLONEIII_ALTPLL; + +-- Instantiate cycloneiiigx_pll +CYCLONEIIIGL_ALTPLL: +if (IS_STINGRAY) generate + M6 : MF_cycloneiiigl_pll + generic map( + operation_mode => alpha_tolower(operation_mode), + pll_type => alpha_tolower(pll_type), + compensate_clock => alpha_tolower(compensate_clock), + inclk0_input_frequency => inclk0_input_frequency, + inclk1_input_frequency => inclk1_input_frequency, + self_reset_on_loss_lock => alpha_tolower(self_reset_on_loss_lock), + switch_over_type => alpha_tolower(switch_over_type), + enable_switch_over_counter => alpha_tolower(enable_switch_over_counter), + switch_over_counter => switch_over_counter, + bandwidth => bandwidth, + bandwidth_type => alpha_tolower(bandwidth_type), + lock_high => lock_high, + lock_low => lock_low, + lock_window_ui => lock_window_ui, + simulation_type => alpha_tolower(simulation_type), + family_name => intended_device_family, + lpm_hint => lpm_hint, + + -- internal clock specifications + clk4_multiply_by => clk4_multiply_by, + clk3_multiply_by => clk3_multiply_by, + clk2_multiply_by => clk2_multiply_by, + clk1_multiply_by => clk1_multiply_by, + clk0_multiply_by => clk0_multiply_by, + clk4_divide_by => clk4_divide_by, + clk3_divide_by => clk3_divide_by, + clk2_divide_by => clk2_divide_by, + clk1_divide_by => clk1_divide_by, + clk0_divide_by => clk0_divide_by, + clk4_phase_shift => clk4_phase_shift, + clk3_phase_shift => clk3_phase_shift, + clk2_phase_shift => clk2_phase_shift, + clk1_phase_shift => clk1_phase_shift, + clk0_phase_shift => clk0_phase_shift, + clk4_duty_cycle => clk4_duty_cycle, + clk3_duty_cycle => clk3_duty_cycle, + clk2_duty_cycle => clk2_duty_cycle, + clk1_duty_cycle => clk1_duty_cycle, + clk0_duty_cycle => clk0_duty_cycle, + + -- advanced user parameters + vco_min => get_vco_min_c3(vco_min), + vco_max => get_vco_max(vco_max), + vco_center => vco_center, + dpa_multiply_by => dpa_multiply_by, + dpa_divide_by => dpa_divide_by, + dpa_divider => dpa_divider, + pfd_min => pfd_min, + pfd_max => pfd_max, + m_initial => m_initial, + m => m, + n => n, + c0_high => c0_high, + c1_high => c1_high, + c2_high => c2_high, + c3_high => c3_high, + c4_high => c4_high, + c0_low => c0_low, + c1_low => c1_low, + c2_low => c2_low, + c3_low => c3_low, + c4_low => c4_low, + c0_initial => c0_initial, + c1_initial => c1_initial, + c2_initial => c2_initial, + c3_initial => c3_initial, + c4_initial => c4_initial, + c0_mode => alpha_tolower(c0_mode), + c1_mode => alpha_tolower(c1_mode), + c2_mode => alpha_tolower(c2_mode), + c3_mode => alpha_tolower(c3_mode), + c4_mode => alpha_tolower(c4_mode), + c0_ph => c0_ph, + c1_ph => c1_ph, + c2_ph => c2_ph, + c3_ph => c3_ph, + c4_ph => c4_ph, + m_ph => m_ph, + c1_use_casc_in => c1_use_casc_in, + c2_use_casc_in => c2_use_casc_in, + c3_use_casc_in => c3_use_casc_in, + c4_use_casc_in => c4_use_casc_in, + m_test_source => get_test_source(m_test_source), + c0_test_source => get_test_source(c0_test_source), + c1_test_source => get_test_source(c1_test_source), + c2_test_source => get_test_source(c2_test_source), + c3_test_source => get_test_source(c3_test_source), + c4_test_source => get_test_source(c4_test_source), + clk4_counter => get_clk_counter(get_clk4_counter(clk4_counter), port_clk4), + clk3_counter => get_clk_counter(get_clk3_counter(clk3_counter), port_clk3), + clk2_counter => get_clk_counter(get_clk2_counter(clk2_counter), port_clk2), + clk1_counter => get_clk_counter(get_clk1_counter(clk1_counter), port_clk1), + clk0_counter => get_clk_counter(get_clk0_counter(clk0_counter), port_clk0), + vco_multiply_by => vco_multiply_by, + vco_divide_by => vco_divide_by, + vco_frequency_control => alpha_tolower(vco_frequency_control), + vco_phase_shift_step => vco_phase_shift_step, + charge_pump_current => charge_pump_current, + loop_filter_r => loop_filter_r, + loop_filter_c => loop_filter_c, + charge_pump_current_bits => charge_pump_current_bits, + loop_filter_c_bits => loop_filter_c_bits, + loop_filter_r_bits => loop_filter_r_bits, + clk4_use_even_counter_mode => alpha_tolower(clk5_use_even_counter_mode), + clk3_use_even_counter_mode => alpha_tolower(clk6_use_even_counter_mode), + clk2_use_even_counter_mode => alpha_tolower(clk7_use_even_counter_mode), + clk1_use_even_counter_mode => alpha_tolower(clk8_use_even_counter_mode), + clk0_use_even_counter_mode => alpha_tolower(clk9_use_even_counter_mode), + clk4_use_even_counter_value => alpha_tolower(clk4_use_even_counter_value), + clk3_use_even_counter_value => alpha_tolower(clk3_use_even_counter_value), + clk2_use_even_counter_value => alpha_tolower(clk2_use_even_counter_value), + clk1_use_even_counter_value => alpha_tolower(clk1_use_even_counter_value), + clk0_use_even_counter_value => alpha_tolower(clk0_use_even_counter_value) + ) + port map ( + inclk => inclk, + fbin => fbin_wire, + clkswitch => clkswitch_wire, + areset => areset_wire, + pfdena => pfdena_wire, + scanclk => scanclk, + scandata => scandata, + scanclkena => scanclkena_wire, + configupdate => configupdate_wire, + phasecounterselect => phasecounterselect_wire(2 downto 0), + phaseupdown => phaseupdown_wire, + phasestep => phasestep_wire, + clk(0) => clk_wire(0), + clk(1) => clk_wire(1), + clk(2) => clk_wire(2), + clk(3) => clk_wire(3), + clk(4) => clk_wire(4), + clkbad => clkbad_wire, + activeclock => activeclock_wire, + locked => locked_tmp, + scandataout => scandataout_wire, + scandone => scandone_wire, + phasedone => phasedone_wire, + vcooverrange => vcooverrange_wire, + vcounderrange => vcounderrange_wire, + fbout => fbout_wire, + fref => fref_wire, + icdrclk => icdrclk_wire + ); +end generate CYCLONEIIIGL_ALTPLL; + +-- Instantiate pll_iobuf +STRATIXIIIPLL_IOBUF: +if ((IS_STRATIXIII) and (not IS_PIRANHA) + and (alpha_tolower(operation_mode) = "zero_delay_buffer") + and (using_fbmimicbidir_port = "ON")) generate + iobuf1 : pll_iobuf + port map ( + i => fbout_wire, + oe => oe_wire, + o => iobuf_o, + io => fbmimicbidir + ); + + +end generate STRATIXIIIPLL_IOBUF; + +process (locked_tmp, areset) +begin + if (areset = '1') then + pll_lock_sync <= '0'; + elsif (locked_tmp = '1' and locked_tmp'event) then + pll_lock_sync <= '1'; + end if; +end process; + + +end behavior; +-- END ARCHITECTURE BEHAVIOR + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : altaccumulate +-- +-- Description : Parameterized accumulator megafunction. The accumulator +-- performs an add function or a subtract function based on the add_sub +-- parameter. The input data can be signed or unsigned. +-- +-- Limitation : n/a +-- +-- Results expected: result - The results of add or subtract operation. Output +-- port [width_out-1 .. 0] wide. +-- cout - The cout port has a physical interpretation as +-- the carry-out (borrow-in) of the MSB. The cout +-- port is most meaningful for detecting overflow +-- in unsigned operations. The cout port operates +-- in the same manner for signed and unsigned +-- operations. +-- overflow - Indicates the accumulator is overflow. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-- BEGINNING OF ENTITY +entity altaccumulate is + -- GENERIC DECLARATION + generic ( + width_in : natural := 4; -- Required + width_out : natural := 8; -- Required + lpm_representation : string := "UNSIGNED"; + extra_latency : integer := 0; + use_wys : string := "ON"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altaccumulate" + ); + + -- PORT DECLARATION + port ( + -- INPUT PORT DECLARATION + cin : in std_logic := 'Z'; + data : in std_logic_vector(width_in -1 downto 0); -- Required port + add_sub : in std_logic := '1'; + clock : in std_logic; -- Required port + sload : in std_logic := '0'; + clken : in std_logic := '1'; + sign_data : in std_logic := '0'; + aclr : in std_logic := '0'; + + -- OUTPUT PORT DECLARATION + result : out std_logic_vector(width_out -1 downto 0) := (others => '0'); -- Required port + cout : out std_logic := '0'; + overflow : out std_logic := '0' + ); +end altaccumulate; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +architecture behaviour of altaccumulate is + +-- TYPE DECLARATION +type pipeline is array (extra_latency-1 downto 0) of std_logic_vector (width_out+1 downto 0); + +-- SIGNAL DECLARATION +signal temp_sum : std_logic_vector (width_out downto 0) := (others => '0'); +signal cout_int : std_logic := '0'; +signal overflow_int : std_logic := '0'; +signal result_int : std_logic_vector (width_out+1 downto 0) := (others => '0'); + +signal result_pipe : pipeline := (others => (others => '0')); + + +begin + MSG: process + begin + if( width_in <= 0 ) then + ASSERT FALSE + REPORT "Error! Value of width_in parameter must be greater than 0." + SEVERITY ERROR; + end if; + + if( width_out <= 0 ) then + ASSERT FALSE + REPORT "Error! Value of width_out parameter must be greater than 0." + SEVERITY ERROR; + end if; + + if( extra_latency > width_out ) then + ASSERT FALSE + REPORT "Info: Value of extra_latency parameter should be lower than width_out parameter for better performance/utilization." + SEVERITY NOTE; + end if; + + if( width_in > width_out ) then + ASSERT FALSE + REPORT "Error! Value of width_in parameter should be lower than or equal to width_out." + SEVERITY ERROR; + end if; + wait; + end process MSG; + + -- PROCESS DECLARATION + ADDSUB : process (data, add_sub, sload, cin, sign_data, + result_int (width_out-1 downto 0)) + + -- VARIABLE DECLARATIOM + variable fb_int : std_logic_vector (width_out downto 0) := (others => '0'); + variable data_int : std_logic_vector (width_out-1 downto 0) := (others => '0'); + variable zeropad : std_logic_vector ((width_out - width_in)-1 downto 0) := (others => '0'); + variable temp_sum_int : std_logic_vector (width_out downto 0) := (others => '0'); + variable cout_temp, borrow : std_logic; + variable result_full : std_logic_vector (width_out downto 0); + variable temp_sum_zero : std_logic_vector (width_out downto 0) := (others => '0'); + variable cin_int : std_logic; + begin + + if ((LPM_REPRESENTATION = "SIGNED") or (sign_data = '1')) then + zeropad := (others => data (width_in-1)); + else + zeropad := (others => '0'); + end if; + + if (sload = '1') then + fb_int := (others => '0'); + else + fb_int := ('0' & result_int (width_out-1 downto 0)); + end if; + + if ((data (0) = '1') or (data (0) = '0')) then + data_int := (zeropad & data); + end if; + + -- If cin is omitted (i.e. cin = 'z'), cin default is 0 for add operation + -- and 1 for subtract operation. + if ((cin /= '0') and (cin /= '1')) then + cin_int := not add_sub; + else + cin_int := cin; + end if; + + if (sload = '1') then + temp_sum_int := unsigned(temp_sum_zero) + unsigned(data_int); + else + if (add_sub = '1') then + temp_sum_int := unsigned(temp_sum_zero) + unsigned(fb_int) + + unsigned(data_int) + cin_int; + cout_temp := temp_sum_int(width_out); + else + borrow := not cin_int; + if ((borrow /= '1') and (borrow /= '0')) then + borrow := '0'; + end if; + + temp_sum_int := unsigned(temp_sum_zero) + unsigned (fb_int) - + unsigned (data_int) - borrow; + result_full := unsigned(temp_sum_zero) + unsigned(data_int) + + borrow; + + if (fb_int >= result_full) then + cout_temp :='1'; + else + cout_temp :='0'; + end if; + end if; + end if; + + if (sload = '0') then + if ((LPM_REPRESENTATION = "SIGNED") or (sign_data = '1')) then + overflow_int <= ((not (data (width_in-1) xor result_int (width_out -1))) xor (not (add_sub))) and + (result_int (width_out -1) xor temp_sum_int (width_out -1)); + else + overflow_int <= not (add_sub xor cout_temp); + end if; + else + overflow_int <= '0'; + cout_temp := not add_sub; + end if; + + cout_int <= cout_temp; + temp_sum <= temp_sum_int; + + end process ADDSUB; + + ACC: process (clock, aclr, cout_int) + + -- VARIABLE DECLARATIOM + variable head_pipe : integer; + variable head : integer := 0; + variable full_res: std_logic_vector (width_out+1 downto 0); + begin + head_pipe := head; + + if ((aclr /= '1') and (extra_latency = 0)) then + cout <= cout_int; + end if; + + if (aclr = '1') then + result <= (others => '0'); + result_int <= (others => '0'); + if (extra_latency > 0) then + cout <= '0'; + else + cout <= cout_int; + end if; + overflow <= '0'; + result_pipe <= (others => (others => '0')); + + elsif rising_edge(clock) then + if (clken = '1') then + if (extra_latency > 0) then + result_pipe (head_pipe) <= (result_int (width_out+1) & + cout_int & + result_int (width_out-1 downto 0)); + + head_pipe := (head_pipe + 1) mod (extra_latency); + if (head_pipe = head) then + full_res := (result_int (width_out+1) & + cout_int & + result_int (width_out-1 downto 0)); + else + full_res := result_pipe (head_pipe); + end if; + cout <= full_res (width_out); + result <= full_res (width_out-1 downto 0); + overflow <= full_res (width_out+1); + else + overflow <= overflow_int; + result <= temp_sum (width_out-1 downto 0); + end if; + result_int <= (overflow_int & cout_int & + temp_sum (width_out-1 downto 0)); + end if; + end if; + + head := head_pipe; + end process ACC; + +end behaviour; -- End behaviour of altaccumulate +-- END OF ARCHITECTURE + +-- -------------------------------------------------------------------------- +-- Module Name : altmult_accum +-- +-- Description : a*b + x (MAC) +-- +-- Limitation : Stratix DSP block +-- +-- Results expected : signed & unsigned, maximum of 3 pipelines(latency) each. +-- +-- -------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.ALTERA_DEVICE_FAMILIES.all; + +entity altmult_accum is + generic ( + + -- --------------------- + -- PARAMETER DECLARATION + -- --------------------- + width_a : natural := 1; + width_b : natural := 1; + width_c : natural := 1; + width_result : natural := 2; + width_upper_data : natural := 1; + input_source_a : string := "DATAA"; + input_source_b : string := "DATAB"; + input_reg_a : string := "CLOCK0"; + input_aclr_a : string := "ACLR3"; + input_reg_b : string := "CLOCK0"; + input_aclr_b : string := "ACLR3"; + port_addnsub : string := "PORT_CONNECTIVITY"; + addnsub_reg : string := "CLOCK0"; + addnsub_aclr : string := "ACLR3"; + addnsub_pipeline_reg : string := "CLOCK0"; + addnsub_pipeline_aclr : string := "ACLR3"; + accum_direction : string := "ADD"; + accum_sload_reg : string := "CLOCK0"; + accum_sload_aclr : string := "ACLR3"; + accum_sload_pipeline_reg : string := "CLOCK0"; + accum_sload_pipeline_aclr : string := "ACLR3"; + representation_a : string := "UNSIGNED"; + port_signa : string := "PORT_CONNECTIVITY"; + sign_reg_a : string := "CLOCK0"; + sign_aclr_a : string := "ACLR3"; + sign_pipeline_reg_a : string := "CLOCK0"; + sign_pipeline_aclr_a : string := "ACLR3"; + representation_b : string := "UNSIGNED"; + port_signb : string := "PORT_CONNECTIVITY"; + sign_reg_b : string := "CLOCK0"; + sign_aclr_b : string := "ACLR3"; + sign_pipeline_reg_b : string := "CLOCK0"; + sign_pipeline_aclr_b : string := "ACLR3"; + multiplier_reg : string := "CLOCK0"; + multiplier_aclr : string := "ACLR3"; + output_reg : string := "CLOCK0"; + output_aclr : string := "ACLR3"; + extra_multiplier_latency : integer := 0; + extra_accumulator_latency : integer := 0; + dedicated_multiplier_circuitry : string := "AUTO"; + dsp_block_balancing : string := "AUTO"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altmult_accum"; + intended_device_family : string := "Stratix"; + multiplier_rounding : string := "NO"; + mult_round_aclr : string := "ACLR3"; + mult_round_reg : string := "CLOCK0"; + multiplier_saturation : string := "NO"; + mult_saturation_aclr : string := "ACLR3"; + mult_saturation_reg : string := "CLOCK0"; + accumulator_rounding : string := "NO"; + accum_round_aclr : string := "ACLR3"; + accum_round_reg : string := "CLOCK0"; + accum_round_pipeline_aclr : string := "ACLR3"; + accum_round_pipeline_reg : string := "CLOCK0"; + accumulator_saturation : string := "NO"; + accum_saturation_aclr : string := "ACLR3"; + accum_saturation_reg : string := "CLOCK0"; + accum_saturation_pipeline_aclr : string := "ACLR3"; + accum_saturation_pipeline_reg : string := "CLOCK0"; + accum_sload_upper_data_aclr : string := "ACLR3"; + accum_sload_upper_data_pipeline_aclr : string := "ACLR3"; + accum_sload_upper_data_pipeline_reg : string := "CLOCK0"; + accum_sload_upper_data_reg : string := "CLOCK0"; + port_mult_is_saturated : string := "UNUSED"; + port_accum_is_saturated : string := "UNUSED"; + -- StratixV parameters + preadder_mode : string := "SIMPLE"; + loadconst_value : integer := 0; + width_coef : integer := 0; + + loadconst_control_register : string := "CLOCK0"; + loadconst_control_aclr : string := "ACLR0"; + + coefsel0_register : string := "CLOCK0"; + coefsel1_register : string := "CLOCK0"; + coefsel2_register : string := "CLOCK0"; + coefsel3_register : string := "CLOCK0"; + coefsel0_aclr : string := "ACLR0"; + coefsel1_aclr : string := "ACLR0"; + coefsel2_aclr : string := "ACLR0"; + coefsel3_aclr : string := "ACLR0"; + + preadder_direction_0 : string := "ADD"; + preadder_direction_1 : string := "ADD"; + preadder_direction_2 : string := "ADD"; + preadder_direction_3 : string := "ADD"; + + systolic_delay1 : string := "UNREGISTERED"; + systolic_delay3 : string := "UNREGISTERED"; + systolic_aclr1 : string := "NONE"; + systolic_aclr3 : string := "NONE"; + -- coefficient storage + coef0_0 : integer := 0; + coef0_1 : integer := 0; + coef0_2 : integer := 0; + coef0_3 : integer := 0; + coef0_4 : integer := 0; + coef0_5 : integer := 0; + coef0_6 : integer := 0; + coef0_7 : integer := 0; + + coef1_0 : integer := 0; + coef1_1 : integer := 0; + coef1_2 : integer := 0; + coef1_3 : integer := 0; + coef1_4 : integer := 0; + coef1_5 : integer := 0; + coef1_6 : integer := 0; + coef1_7 : integer := 0; + + coef2_0 : integer := 0; + coef2_1 : integer := 0; + coef2_2 : integer := 0; + coef2_3 : integer := 0; + coef2_4 : integer := 0; + coef2_5 : integer := 0; + coef2_6 : integer := 0; + coef2_7 : integer := 0; + + coef3_0 : integer := 0; + coef3_1 : integer := 0; + coef3_2 : integer := 0; + coef3_3 : integer := 0; + coef3_4 : integer := 0; + coef3_5 : integer := 0; + coef3_6 : integer := 0; + coef3_7 : integer := 0 + ); + + port ( + + -- ---------------- + -- PORT DECLARATION + -- ---------------- + + -- input data ports + dataa : in std_logic_vector(width_a -1 downto 0) := (others => '0'); + datab : in std_logic_vector(width_b -1 downto 0) := (others => '0'); + datac : in std_logic_vector(width_c -1 downto 0) := (others => '0'); + scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z'); + scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z'); + accum_sload_upper_data : in std_logic_vector(width_upper_data - 1 downto 0) := (others => '0'); + sourcea : in std_logic := '0'; + sourceb : in std_logic := '0'; + -- control signals + addnsub : in std_logic := 'Z'; + accum_sload : in std_logic := '0'; + signa : in std_logic := 'Z'; + signb : in std_logic := 'Z'; + -- clock ports + clock0 : in std_logic := '1'; + clock1 : in std_logic := '1'; + clock2 : in std_logic := '1'; + clock3 : in std_logic := '1'; + -- clock enable ports + ena0 : in std_logic := '1'; + ena1 : in std_logic := '1'; + ena2 : in std_logic := '1'; + ena3 : in std_logic := '1'; + -- clear ports + aclr0 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + aclr2 : in std_logic := '0'; + aclr3 : in std_logic := '0'; + -- round and saturation ports + mult_round : in std_logic := '0'; + mult_saturation : in std_logic := '0'; + accum_round : in std_logic := '0'; + accum_saturation : in std_logic := '0'; + -- StratixV only input ports + coefsel0 : in std_logic_vector(2 downto 0) := (others => '0'); + coefsel1 : in std_logic_vector(2 downto 0) := (others => '0'); + coefsel2 : in std_logic_vector(2 downto 0) := (others => '0'); + coefsel3 : in std_logic_vector(2 downto 0) := (others => '0'); + -- output ports + result : out std_logic_vector(width_result -1 downto 0) := (others => '0'); + overflow : out std_logic :='0'; + scanouta : out std_logic_vector (width_a -1 downto 0) := (others => '0'); + scanoutb : out std_logic_vector (width_b -1 downto 0) := (others => '0'); + mult_is_saturated : out std_logic := '0'; + accum_is_saturated : out std_logic := '0' + ); +end altmult_accum; + + +architecture behaviour of altmult_accum is + -- ------------------------------------- + -- INTERNAL SIGNALS AND TYPE DECLARATION + -- ------------------------------------- + + -- CONSTANT DECLARATION + constant IS_STRATIXV : boolean := FEATURE_FAMILY_STRATIXV(intended_device_family); + constant IS_STRATIXIII : boolean := FEATURE_FAMILY_STRATIXIII(intended_device_family); + constant IS_STRATIXII : boolean := FEATURE_FAMILY_STRATIXII(intended_device_family); + constant IS_CYCLONEII : boolean := FEATURE_FAMILY_CYCLONEII(intended_device_family); + constant altera_mult_add_block : boolean := FEATURE_FAMILY_HAS_ALTERA_MULT_ADD_FLOW(intended_device_family); + constant altmult_add_eol_block : boolean := FEATURE_FAMILY_IS_ALTMULT_ADD_EOL(intended_device_family); + + function resolve_internal_width (ARG : integer;ARG2 : integer) return integer is + variable changed_width:integer := 0; + begin + if (multiplier_saturation = "NO" and multiplier_rounding = "NO" and + accumulator_saturation = "NO" and accumulator_rounding = "NO") then + if (ARG2 = 0) then + changed_width := width_a; + else + changed_width := width_b; + end if; + else + changed_width := 18; + end if; + return changed_width; + end resolve_internal_width; + + -- This constant int_width_a would be used internally in this model + -- to represent width_a + constant int_width_a : natural := resolve_internal_width(width_a, 0); + + -- This constant int_width_b woudl be used internally in this model + -- to represent width_b + constant int_width_b : natural := resolve_internal_width(width_b, 1); + + function resolve_internal_extra_width return integer is + variable changed_value :integer := 0; + begin + if (multiplier_saturation = "NO" and multiplier_rounding = "NO" and + accumulator_saturation = "NO" and accumulator_rounding = "NO") then + changed_value := 0; + else + changed_value := int_width_a + int_width_b - width_a - width_b; + end if; + return changed_value; + end resolve_internal_extra_width; + + constant int_extra_width : integer := resolve_internal_extra_width; + + function resolve_internal_width_result return integer is + variable changed_width_result:integer := 0; + begin + if (multiplier_saturation = "NO" and multiplier_rounding = "NO" and + accumulator_saturation = "NO" and accumulator_rounding = "NO") then + if ((int_width_a + int_width_b - 1) > width_result) then + changed_width_result := int_width_a + int_width_b - 1; + else + changed_width_result := width_result; + end if; + else + if ((int_width_a + int_width_b - 1) > 52) then + changed_width_result := int_width_a + int_width_b - 1; + else + changed_width_result := 52; + end if; + end if; + return changed_width_result; + end resolve_internal_width_result; + + constant int_width_result : natural := resolve_internal_width_result; + + -- ------------------------------------- + -- INTERNAL TEMPLATE DECLARATION + -- ------------------------------------- + type pipeline_accum is array (extra_accumulator_latency downto 0) of std_logic_vector (int_width_result downto 0); + type pipeline_multi is array (extra_multiplier_latency downto 0) of std_logic_vector (int_width_a + int_width_b + 4 downto 0); + type pipeline_sload is array (extra_multiplier_latency downto 0) of std_logic_vector (width_upper_data - 1 downto 0); + + signal mult_a : std_logic_vector (width_a - 1 downto 0):= (others => '0'); + signal mult_b : std_logic_vector (width_b - 1 downto 0):= (others => '0'); + signal mult_res : std_logic_vector (int_width_a + int_width_b - 1 downto 0):= (others => '0'); + signal acc_sload_reg : std_logic := '0'; + signal accum_sload_pipe : std_logic := '0'; + signal sign_a_reg : std_logic := '0'; + signal sign_a_pipe : std_logic := '0'; + signal sign_a_latent : std_logic := '0'; + signal sign_b_reg : std_logic := '0'; + signal sign_b_pipe : std_logic := '0'; + signal sign_b_latent : std_logic := '0'; + signal addsub_reg : std_logic := '0'; + signal addsub_pipe : std_logic := '0'; + signal addsub_latent : std_logic := '0'; + signal accum_sload_latent : std_logic := '0'; + + signal mult_pipe : pipeline_multi := (others => (others => '0')); + signal sload_upper_data_pipe : pipeline_sload := (others => (others => '0')); + + signal mult_out_latent : std_logic_vector (int_width_a + int_width_b - 1 downto 0):= (others => '0'); + signal result_int : std_logic_vector (int_width_result - 1 downto 0):= (others => '0'); + signal temp_mult_zero : std_logic_vector (int_width_a + int_width_b downto 0):= (others => '0'); + signal mult_full : std_logic_vector (int_width_a + int_width_b + 4 downto 0):= (others => '0'); + + signal mult_signed : std_logic := '0'; + signal do_add : std_logic := '0'; + signal temp_mult_signed : std_logic := '0'; + signal head_result : natural := 0; + signal head_mult : natural := 0; + + signal lower_bits : std_logic_vector (width_result + width_upper_data - 1 downto 0) := (others => '0'); + signal sload_upper_data_reg : std_logic_vector (width_upper_data - 1 downto 0) := (others => '0'); + signal sload_upper_data_latent : std_logic_vector (width_upper_data - 1 downto 0) := (others => '0'); + signal sload_upper_data_wire : std_logic_vector (width_upper_data - 1 downto 0) := (others => '0'); + signal sload_upper_data_full : std_logic_vector (width_upper_data - 1 downto 0) := (others => '0'); + + signal mult_is_saturated_wire : std_logic := '0'; + signal mult_is_saturated_reg : std_logic := '0'; + signal mult_is_saturated_out : std_logic := '0'; + signal accum_is_saturated_out : std_logic := '0'; + + signal mult_round_wire : std_logic := '0'; + signal mult_saturate_wire : std_logic := '0'; + signal mult_final_out : std_logic_vector (int_width_a + int_width_b - 1 downto 0) := (others => '0'); + + signal accum_round_pipe_wire : std_logic := '0'; + signal accum_round_wire : std_logic := '0'; + signal accum_saturation_pipe_wire : std_logic := '0'; + signal accum_saturate_wire : std_logic := '0'; + + begin + + scanouta <= mult_a; + scanoutb <= mult_b; + sign_a_latent <= mult_full (int_width_a + int_width_b + 4) when extra_multiplier_latency >0 else sign_a_reg; + sign_b_latent <= mult_full (int_width_a + int_width_b + 3) when extra_multiplier_latency >0 else sign_b_reg; + accum_sload_latent <= mult_full (int_width_a + int_width_b + 2) when extra_multiplier_latency >0 else acc_sload_reg; + addsub_latent <= mult_full (int_width_a + int_width_b + 1) when extra_multiplier_latency >0 else addsub_reg; + mult_signed <= mult_full (int_width_a + int_width_b + 0) when extra_multiplier_latency >0 else temp_mult_signed; + mult_out_latent <= mult_full (int_width_a + int_width_b - 1 downto 0) when extra_multiplier_latency >0 else mult_final_out; + sload_upper_data_latent <= sload_upper_data_full when extra_multiplier_latency >0 else sload_upper_data_reg; + + mult_is_saturated <= mult_is_saturated_out when (port_mult_is_saturated = "USED") else '0'; + accum_is_saturated <= accum_is_saturated_out when (port_accum_is_saturated = "USED") else '0'; + + + -- Parameter Checking + process + begin + + -- Legality check, family from Night Fury and moving forwards is officially EOL + if (altmult_add_eol_block) then + assert false + report "ALTMULT_ACCUM is EOL for "& intended_device_family &" device family" + severity failure; + end if; + + -- Legality check, block unsupported family from running pre_layout simulation using altera_mf (family with altera_mult_add flow) + if (altera_mult_add_block or altmult_add_eol_block) then + assert false + report "ALTMULT_ACCUM is not supported for "& intended_device_family &" device family" + severity failure; + end if; + + if ((dedicated_multiplier_circuitry /= "AUTO") and + (dedicated_multiplier_circuitry /= "YES") and + (dedicated_multiplier_circuitry /= "NO")) then + assert false + report "Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value." + severity error; + end if; + + if (width_a <= 0) then + assert false + report "Error: width_a must be greater than 0." + severity error; + end if; + + if (width_b <= 0) then + assert false + report "Error: width_b must be greater than 0." + severity error; + end if; + + if (width_result <= 0) then + assert false + report "Error: width_result must be greater than 0." + severity error; + end if; + + if ((not IS_STRATIXII) and + (not IS_CYCLONEII) and + (input_source_a /= "DATAA")) then + assert false + report "Error: The input source for port A are limited to input dataa." + severity error; + end if; + + if ((not IS_STRATIXII) and + (not IS_CYCLONEII) and + (input_source_b /= "DATAB")) then + assert false + report "Error: The input source for port B are limited to input datab." + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (multiplier_rounding /= "NO")) then + assert false + report "Error: There is no rounding feature for " & intended_device_family & " device." + severity error; + end if; + + if ((not IS_STRATIXII) and (accumulator_rounding /= "NO")) then + assert false + report "Error: There is no rounding feature for "& intended_device_family &" device." + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (multiplier_saturation /= "NO")) then + assert false + report "Error: There is no saturation feature for "& intended_device_family &" device." + severity error; + end if; + + if ((not IS_STRATIXII) and (accumulator_saturation /= "NO")) then + assert false + report "Error: There is no saturation feature for "& intended_device_family &" device." + severity error; + end if; + + if ((IS_STRATIXIII) and (port_addnsub /= "PORT_UNUSED")) then + assert false + report "Error: The addnsub port is not available for "& intended_device_family &" device." + severity error; + end if; + + if ((IS_STRATIXIII) and (accum_direction /= "ADD") and + (accum_direction /= "SUB")) then + assert false + report "Error: Invalid value for ACCUM_DIRECTION parameter for "& intended_device_family &" device." + severity error; + end if; + + if ((IS_STRATIXIII) and not(IS_STRATIXV) and (input_source_a = "VARIABLE")) then + assert false + report "Error: Invalid value for INPUT_SOURCE_A parameter for "& intended_device_family &" device." + severity error; + end if; + + wait; + + end process; + + G1:if (input_reg_a = "UNREGISTERED") generate + process (dataa, scanina, sourcea) + begin + if (input_source_a = "DATAA") then + mult_a <= dataa; + elsif (input_source_a = "SCANA") then + mult_a <= scanina; + elsif (input_source_a = "VARIABLE") then + if (sourcea = '1') then + mult_a <= dataa; + else + mult_a <= scanina; + end if; + end if; + end process; + end generate G1; + + G2:if (input_reg_b = "UNREGISTERED") generate + process (datab, scaninb, sourceb) + begin + if (input_source_b = "DATAB") then + mult_b <= datab; + elsif (input_source_b = "SCANB") then + mult_b <= scaninb; + elsif (input_source_b = "VARIABLE") then + if (sourceb = '1') then + mult_b <= datab; + else + mult_b <= scaninb; + end if; + end if; + end process; + end generate G2; + + G3: if (addnsub_reg = "UNREGISTERED") generate + addsub_reg <= addnsub; + end generate G3; + + G4: if (addnsub_pipeline_reg = "UNREGISTERED") generate + addsub_pipe <= addsub_latent; + end generate G4; + + G5: if (accum_sload_reg = "UNREGISTERED") generate + acc_sload_reg <= accum_sload; + end generate G5; + + G6: if (accum_sload_pipeline_reg = "UNREGISTERED") generate + accum_sload_pipe <= accum_sload_latent; + end generate G6; + + G7: if (sign_reg_a = "UNREGISTERED") generate + sign_a_reg <= signa; + end generate G7; + + G8: if sign_reg_b= "UNREGISTERED" generate + sign_b_reg <= signb; + end generate G8; + + G9: if (sign_pipeline_reg_a = "UNREGISTERED") generate + sign_a_pipe <= sign_a_latent; + end generate G9; + + G10: if (sign_pipeline_reg_b = "UNREGISTERED") generate + sign_b_pipe <= sign_b_latent; + end generate G10; + + G11: if (accum_round_reg = "UNREGISTERED") generate + process (accum_round, accum_sload) + begin + if (IS_STRATIXIII) then + accum_round_pipe_wire <= accum_sload; + else + accum_round_pipe_wire <= accum_round; + end if; + end process; + end generate G11; + + G12: if (accum_round_pipeline_reg = "UNREGISTERED") generate + accum_round_wire <= accum_round_pipe_wire; + end generate G12; + + G12b: if (accum_saturation_reg = "UNREGISTERED") generate + accum_saturation_pipe_wire <= accum_saturation; + end generate G12b; + + G14: if (accum_saturation_pipeline_reg = "UNREGISTERED") generate + accum_saturate_wire <= accum_saturation_pipe_wire; + end generate G14; + + G15: if (mult_round_reg = "UNREGISTERED") generate + mult_round_wire <= mult_round; + end generate G15; + + G16: if (mult_saturation_reg = "UNREGISTERED") generate + mult_saturate_wire <= mult_saturation; + end generate G16; + + G17: if (accum_sload_upper_data_reg = "UNREGISTERED") generate + sload_upper_data_reg <= accum_sload_upper_data; + end generate G17; + + G18: if (accum_sload_upper_data_pipeline_reg = "UNREGISTERED") generate + sload_upper_data_wire <= sload_upper_data_latent; + end generate G18; + + G19: if (multiplier_reg = "UNREGISTERED") generate + mult_res <= mult_out_latent; + mult_is_saturated_reg <= mult_is_saturated_wire; + end generate G19; + + -- ---------------------------------------------------------------------------- + -- This process contains 1 register and a combinatorial block (to set mult_a) + -- The signal registered is dataa + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if input_reg_a is unregistered and + -- dataa changes value + -- --------------------------------------------------------------------------- + + IFG1: if (input_reg_a = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, dataa, scanina, sourcea) + begin + if (((input_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a= "ACLR3") and (aclr3 = '1'))) then + mult_a <= (others => '0'); + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + if (input_source_a = "DATAA") then + mult_a <= dataa; + elsif (input_source_a = "SCANA") then + mult_a <= scanina; + elsif (input_source_a = "VARIABLE") then + if (sourcea = '1') then + mult_a <= dataa; + else + mult_a <= scanina; + end if; + end if; + end if; + end if; + end process; + end generate IFG1; + + IFG2: if (input_reg_a = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, dataa, scanina, sourcea) + begin + if (((input_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a= "ACLR3") and (aclr3 = '1'))) then + mult_a <= (others => '0'); + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + if (input_source_a = "DATAA") then + mult_a <= dataa; + elsif (input_source_a = "SCANA") then + mult_a <= scanina; + elsif (input_source_a = "VARIABLE") then + if (sourcea = '1') then + mult_a <= dataa; + else + mult_a <= scanina; + end if; + end if; + end if; + end if; + end process; + end generate IFG2; + + IFG3: if (input_reg_a = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, dataa, scanina, sourcea) + begin + if (((input_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a= "ACLR3") and (aclr3 = '1'))) then + mult_a <= (others => '0'); + elsif rising_edge(clock2) then + if ((ena2 ='1'))then + if (input_source_a = "DATAA") then + mult_a <= dataa; + elsif (input_source_a = "SCANA") then + mult_a <= scanina; + elsif (input_source_a = "VARIABLE") then + if (sourcea = '1') then + mult_a <= dataa; + else + mult_a <= scanina; + end if; + end if; + end if; + end if; + end process; + end generate IFG3; + + IFG4: if (input_reg_a = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, dataa, scanina, sourcea) + begin + if (((input_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a= "ACLR3") and (aclr3 = '1'))) then + mult_a <= (others => '0'); + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + if (input_source_a = "DATAA") then + mult_a <= dataa; + elsif (input_source_a = "SCANA") then + mult_a <= scanina; + elsif (input_source_a = "VARIABLE") then + if (sourcea = '1') then + mult_a <= dataa; + else + mult_a <= scanina; + end if; + end if; + end if; + end if; + end process; + end generate IFG4; + -- ---------------------------------------------------------------------------- + -- This process contains 1 register and a combinatorial block (to set mult_b) + -- The signal registered is datab + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if input_reg_b is unregistered and + -- datab changes value + -- --------------------------------------------------------------------------- + IFG5: if (input_reg_b = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, datab, scaninb, sourceb) + begin + if (((input_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b= "ACLR3") and (aclr3 = '1'))) then + mult_b <= (others => '0'); + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + if (input_source_b = "DATAB") then + mult_b <= datab; + elsif (input_source_b = "SCANB") then + mult_b <= scaninb; + elsif (input_source_b = "VARIABLE") then + if (sourceb = '1') then + mult_b <= datab; + else + mult_b <= scaninb; + end if; + end if; + end if; + end if; + end process; + end generate IFG5; + + IFG6: if (input_reg_b = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, datab, scaninb, sourceb) + begin + if (((input_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b= "ACLR3") and (aclr3 = '1'))) then + mult_b <= (others => '0'); + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + if (input_source_b = "DATAB") then + mult_b <= datab; + elsif (input_source_b = "SCANB") then + mult_b <= scaninb; + elsif (input_source_b = "VARIABLE") then + if (sourceb = '1') then + mult_b <= datab; + else + mult_b <= scaninb; + end if; + end if; + end if; + end if; + end process; + end generate IFG6; + + IFG7: if (input_reg_b = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, datab, scaninb, sourceb) + begin + if (((input_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b= "ACLR3") and (aclr3 = '1'))) then + mult_b <= (others => '0'); + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + if (input_source_b = "DATAB") then + mult_b <= datab; + elsif (input_source_b = "SCANB") then + mult_b <= scaninb; + elsif (input_source_b = "VARIABLE") then + if (sourceb = '1') then + mult_b <= datab; + else + mult_b <= scaninb; + end if; + end if; + end if; + end if; + end process; + end generate IFG7; + + IFG8: if (input_reg_b = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, datab, scaninb, sourceb) + begin + if (((input_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b= "ACLR3") and (aclr3 = '1'))) then + mult_b <= (others => '0'); + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + if (input_source_b = "DATAB") then + mult_b <= datab; + elsif (input_source_b = "SCANB") then + mult_b <= scaninb; + elsif (input_source_b = "VARIABLE") then + if (sourceb = '1') then + mult_b <= datab; + else + mult_b <= scaninb; + end if; + end if; + end if; + end if; + end process; + end generate IFG8; + + -- ------------------------------------------------------------------------------ + -- This process contains 1 register and a combinatorial block (to set addsub_reg) + -- The signal registered is addnsub + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub_reg is unregistered and + -- addnsub changes value + -- ------------------------------------------------------------------------------ + IFG9: if (addnsub_reg = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addnsub) + begin + if (((addnsub_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_reg <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addsub_reg <= addnsub; + end if; + end if; + end process; + end generate IFG9; + + IFG10: if (addnsub_reg = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addnsub) + begin + if (((addnsub_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_reg <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addsub_reg <= addnsub; + end if; + end if; + end process; + end generate IFG10; + + IFG11: if (addnsub_reg = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addnsub) + begin + if (((addnsub_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_reg <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addsub_reg <= addnsub; + end if; + end if; + end process; + end generate IFG11; + + IFG12: if (addnsub_reg = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addnsub) + begin + if (((addnsub_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_reg <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addsub_reg <= addnsub; + end if; + end if; + end process; + end generate IFG12; + + + -- ------------------------------------------------------------------------------------ + -- This process contains 1 register and a combinatorial block (to set addsub_pipe) + -- The signal registered is addnsub_latent + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub_pipeline_reg is unregistered and + -- addsub_latent changes value + -- ------------------------------------------------------------------------------------ + + IFG12b: if (addnsub_pipeline_reg = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addsub_latent) + begin + if (((addnsub_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addsub_pipe <= addsub_latent; + end if; + end if; + end process; + end generate IFG12b; + + IFG14: if (addnsub_pipeline_reg = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addsub_latent) + begin + if (((addnsub_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addsub_pipe <= addsub_latent; + end if; + end if; + end process; + end generate IFG14; + + IFG15: if (addnsub_pipeline_reg = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addsub_latent) + begin + if (((addnsub_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addsub_pipe <= addsub_latent; + end if; + end if; + end process; + end generate IFG15; + + IFG16: if (addnsub_pipeline_reg = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addsub_latent) + begin + if (((addnsub_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addsub_pipe <= addsub_latent; + end if; + end if; + end process; + end generate IFG16; + + + -- --------------------------------------------------------------------------------- + -- This process contains 1 register and a combinatorial block (to set acc_sload_reg) + -- The signal registered is accum_sload + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_sload_reg is unregistered and + -- accum_sload changes value + -- --------------------------------------------------------------------------------- + IFG17: if (accum_sload_reg = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr= "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr= "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr= "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr= "ACLR3") and (aclr3 = '1'))) then + acc_sload_reg <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + acc_sload_reg <= accum_sload; + end if; + end if; + end process; + end generate IFG17; + + IFG18: if (accum_sload_reg = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr= "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr= "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr= "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr= "ACLR3") and (aclr3 = '1'))) then + acc_sload_reg <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + acc_sload_reg <= accum_sload; + end if; + end if; + end process; + end generate IFG18; + + IFG19: if (accum_sload_reg = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr= "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr= "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr= "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr= "ACLR3") and (aclr3 = '1'))) then + acc_sload_reg <= '0'; + elsif rising_edge(clock2) then + if((ena2 ='1')) then + acc_sload_reg <= accum_sload; + end if; + end if; + end process; + end generate IFG19; + + IFG20: if (accum_sload_reg = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr= "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr= "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr= "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr= "ACLR3") and (aclr3 = '1'))) then + acc_sload_reg <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + acc_sload_reg <= accum_sload; + end if; + end if; + end process; + end generate IFG20; + + + + -- ------------------------------------------------------------------------------------ + -- This process contains 1 register and a combinatorial block (to set accum_sload_pipe) + -- The signal registered is accum_sload_latent + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_sload_pipeline_reg + -- is unregistered and accum_sload_latent changes value + -- ------------------------------------------------------------------------------------ + IFG21: if (accum_sload_pipeline_reg = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, accum_sload_latent) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_sload_pipe <= '0'; + elsif rising_edge(clock0) then + if ((ena0 = '1')) then + accum_sload_pipe <= accum_sload_latent; + end if; + end if; + end process; + end generate IFG21; + + IFG22: if (accum_sload_pipeline_reg = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, accum_sload_latent) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_sload_pipe <= '0'; + elsif rising_edge(clock1) then + if ((ena1 = '1')) then + accum_sload_pipe <= accum_sload_latent; + end if; + end if; + end process; + end generate IFG22; + + IFG23: if (accum_sload_pipeline_reg = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, accum_sload_latent) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_sload_pipe <= '0'; + elsif rising_edge(clock2) then + if ((ena2 = '1')) then + accum_sload_pipe <= accum_sload_latent; + end if; + end if; + end process; + end generate IFG23; + + IFG24: if (accum_sload_pipeline_reg = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, accum_sload_latent) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_sload_pipe <= '0'; + elsif rising_edge(clock3) then + if ((ena3 = '1')) then + accum_sload_pipe <= accum_sload_latent; + end if; + end if; + end process; + end generate IFG24; + + + -- ------------------------------------------------------------------------------ + -- This process contains 1 register and a combinatorial block (to set sign_a_reg) + -- The signal registered is signa + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if sign_reg_a is unregistered and + -- signa changes value + -- ------------------------------------------------------------------------------ + + IFG25: if (sign_reg_a = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((sign_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 ='1') then + sign_a_reg <= signa; + end if; + end if; + end process; + end generate IFG25; + + IFG26: if (sign_reg_a = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((sign_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif (rising_edge(clock1) and (ena1 ='1')) then + sign_a_reg <= signa; + end if; + end process; + end generate IFG26; + + IFG27: if (sign_reg_a = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((sign_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif (rising_edge(clock2) and (ena2 ='1')) then + sign_a_reg <= signa; + end if; + end process; + end generate IFG27; + + IFG28: if (sign_reg_a = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((sign_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif (rising_edge(clock3) and (ena3 ='1')) then + sign_a_reg <= signa; + end if; + end process; + end generate IFG28; + + + + + -- ------------------------------------------------------------------------------ + -- This process contains 1 register and a combinatorial block (to set sign_b_reg) + -- The signal registered is signb + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if sign_reg_b is unregistered and + -- signb changes value + -- ------------------------------------------------------------------------------ + + IFG29: if (sign_reg_b = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((sign_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 ='1') then + sign_b_reg <= signb; + end if; + end if; + end process; + end generate IFG29; + + IFG30: if (sign_reg_b = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((sign_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif (rising_edge(clock1) and (ena1 ='1')) then + sign_b_reg <= signb; + end if; + end process; + end generate IFG30; + + IFG31: if (sign_reg_b = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((sign_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif (rising_edge(clock2) and (ena2 ='1')) then + sign_b_reg <= signb; + end if; + end process; + end generate IFG31; + + IFG32: if (sign_reg_b = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((sign_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif (rising_edge(clock3) and (ena3 ='1'))then + sign_b_reg <= signb; + end if; + end process; + end generate IFG32; + + + -- ------------------------------------------------------------------------------- + -- This process contains 1 register and a combinatorial block (to set sign_a_pipe) + -- The signal registered is sign_a_latent + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if sign_pipeline_reg_a + -- is unregistered and sign_a_latent changes value + -- ------------------------------------------------------------------------------- + + IFG33: if (sign_pipeline_reg_a = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, sign_a_latent) + begin + if (((sign_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 ='1') then + sign_a_pipe <= sign_a_latent; + end if; + end if; + end process; + end generate IFG33; + + IFG34: if (sign_pipeline_reg_a = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, sign_a_latent) + begin + if (((sign_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif (rising_edge(clock1) and (ena1 ='1')) then + sign_a_pipe <= sign_a_latent; + end if; + end process; + end generate IFG34; + + IFG35: if (sign_pipeline_reg_a = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, sign_a_latent) + begin + if (((sign_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif (rising_edge(clock2) and (ena2 ='1')) then + sign_a_pipe <= sign_a_latent; + end if; + end process; + end generate IFG35; + + IFG36: if (sign_pipeline_reg_a = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, sign_a_latent) + begin + if (((sign_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif (rising_edge(clock3) and (ena3 ='1')) then + sign_a_pipe <= sign_a_latent; + end if; + end process; + end generate IFG36; + + + -- ------------------------------------------------------------------------------- + -- This process contains 1 register and a combinatorial block (to set sign_b_pipe) + -- The signal registered is sign_b_latent + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if sign_pipeline_reg_b + -- is unregistered and sign_b_latent changes value + -- ------------------------------------------------------------------------------- + + IFG37: if (sign_pipeline_reg_b = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, sign_b_latent) + begin + if (((sign_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 ='1') then + sign_b_pipe <= sign_b_latent; + end if; + end if; + end process; + end generate IFG37; + + IFG38: if (sign_pipeline_reg_b = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, sign_b_latent) + begin + if (((sign_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif (rising_edge(clock1) and (ena1 ='1')) then + sign_b_pipe <= sign_b_latent; + end if; + end process; + end generate IFG38; + + IFG39: if (sign_pipeline_reg_b = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, sign_b_latent) + begin + if (((sign_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif (rising_edge(clock2) and (ena2 ='1')) then + sign_b_pipe <= sign_b_latent; + end if; + end process; + end generate IFG39; + + IFG40: if (sign_pipeline_reg_b = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, sign_b_latent) + begin + if (((sign_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((sign_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((sign_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((sign_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif (rising_edge(clock3) and (ena3 ='1')) then + sign_b_pipe <= sign_b_latent; + end if; + end process; + end generate IFG40; + + + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set accum_round_pipe_wire) + -- The signal registered is accum_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_round_reg + -- is unregistered and accum_round changes value + ------------------------------------------------------------------------------------- + + IFG41: if (accum_round_reg = "CLOCK0") generate + process (clock0, accum_round, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_pipe_wire <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 = '1') then + if (IS_STRATIXIII) then + accum_round_pipe_wire <= accum_sload; + else + accum_round_pipe_wire <= accum_round; + end if; + end if; + end if; + end process; + end generate IFG41; + + IFG42: if (accum_round_reg = "CLOCK1") generate + process (clock1, accum_round, aclr0, aclr1, aclr2, aclr3) + begin + + if (((accum_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_pipe_wire <= '0'; + elsif (rising_edge(clock1) and (ena1 = '1')) then + if (IS_STRATIXIII) then + accum_round_pipe_wire <= accum_sload; + else + accum_round_pipe_wire <= accum_round; + end if; + end if; + end process; + end generate IFG42; + + IFG43: if (accum_round_reg = "CLOCK2") generate + process (clock2, accum_round, aclr0, aclr1, aclr2, aclr3) + begin + + if (((accum_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_pipe_wire <= '0'; + elsif (rising_edge(clock2) and (ena2 = '1')) then + if (IS_STRATIXIII) then + accum_round_pipe_wire <= accum_sload; + else + accum_round_pipe_wire <= accum_round; + end if; + end if; + end process; + end generate IFG43; + + IFG44: if (accum_round_reg = "CLOCK3") generate + process (clock3, accum_round, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_pipe_wire <= '0'; + elsif (rising_edge(clock3) and (ena3 = '1')) then + if (IS_STRATIXIII) then + accum_round_pipe_wire <= accum_sload; + else + accum_round_pipe_wire <= accum_round; + end if; + end if; + end process; + end generate IFG44; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set accum_round_wire) + -- The signal registered is accum_round_pipe_wire + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_round_pipeline_reg + -- is unregistered and accum_round_pipe_wire changes value + ------------------------------------------------------------------------------------- + + IFG45: if (accum_round_pipeline_reg = "CLOCK0") generate + process (clock0, accum_round_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_wire <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 = '1') then + accum_round_wire <= accum_round_pipe_wire; + end if; + end if; + end process; + end generate IFG45; + + IFG46: if (accum_round_pipeline_reg = "CLOCK1") generate + process (clock1, accum_round_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_wire <= '0'; + elsif (rising_edge(clock1) and (ena1 = '1')) then + accum_round_wire <= accum_round_pipe_wire; + end if; + end process; + end generate IFG46; + + IFG47: if (accum_round_pipeline_reg = "CLOCK2") generate + process (clock2, accum_round_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_wire <= '0'; + elsif (rising_edge(clock2) and (ena2 = '1')) then + accum_round_wire <= accum_round_pipe_wire; + end if; + end process; + end generate IFG47; + + IFG48: if (accum_round_pipeline_reg = "CLOCK3") generate + process (clock3, accum_round_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_round_wire <= '0'; + elsif (rising_edge(clock3) and (ena3 = '1')) then + accum_round_wire <= accum_round_pipe_wire; + end if; + end process; + end generate IFG48; + + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set accum_saturation_pipe_wire) + -- The signal registered is accum_saturation + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_saturation_reg + -- is unregistered and accum_saturation changes value + -- --------------------------------------------------------------------------------- + + IFG49: if (accum_saturation_reg = "CLOCK0") generate + process (clock0, accum_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturation_pipe_wire <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 = '1')then + accum_saturation_pipe_wire <= accum_saturation; + end if; + end if; + end process; + end generate IFG49; + + IFG50: if (accum_saturation_reg = "CLOCK1") generate + process (clock1, accum_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturation_pipe_wire <= '0'; + elsif (rising_edge(clock1) and (ena1 = '1')) then + accum_saturation_pipe_wire <= accum_saturation; + end if; + end process; + end generate IFG50; + + IFG51: if (accum_saturation_reg = "CLOCK2") generate + process (clock2, accum_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturation_pipe_wire <= '0'; + elsif (rising_edge(clock2) and (ena2 = '1')) then + accum_saturation_pipe_wire <= accum_saturation; + end if; + end process; + end generate IFG51; + + IFG52: if (accum_saturation_reg = "CLOCK3") generate + process (clock3, accum_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturation_pipe_wire <= '0'; + elsif (rising_edge(clock3) and (ena3 = '1')) then + accum_saturation_pipe_wire <= accum_saturation; + end if; + end process; + end generate IFG52; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set accum_saturate_wire) + -- The signal registered is accum_saturation_pipe_wire + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_saturation_pipeline_reg + -- is unregistered and accum_saturation_pipe_wire changes value + -- --------------------------------------------------------------------------------- + + IFG53: if (accum_saturation_pipeline_reg = "CLOCK0") generate + process (clock0, accum_saturation_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturate_wire <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 = '1') then + accum_saturate_wire <= accum_saturation_pipe_wire; + end if; + end if; + end process; + end generate IFG53; + + IFG54: if (accum_saturation_pipeline_reg = "CLOCK1") generate + process (clock1, accum_saturation_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturate_wire <= '0'; + elsif (rising_edge(clock1) and (ena1 = '1')) then + accum_saturate_wire <= accum_saturation_pipe_wire; + end if; + end process; + end generate IFG54; + + IFG55: if (accum_saturation_pipeline_reg = "CLOCK2") generate + process (clock2, accum_saturation_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturate_wire <= '0'; + elsif (rising_edge(clock2) and (ena2 = '1')) then + accum_saturate_wire <= accum_saturation_pipe_wire; + end if; + end process; + end generate IFG55; + + IFG56: if (accum_saturation_pipeline_reg = "CLOCK3") generate + process (clock3, accum_saturation_pipe_wire, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_saturation_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_saturation_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accum_saturate_wire <= '0'; + elsif (rising_edge(clock3) and (ena3 = '1')) then + accum_saturate_wire <= accum_saturation_pipe_wire; + end if; + end process; + end generate IFG56; + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set mult_round_wire) + -- The signal registered is mult_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if mult_round_reg + -- is unregistered and mult_round changes value + -- --------------------------------------------------------------------------------- + + IFG57: if (mult_round_reg = "CLOCK0") generate + process (clock0, mult_round, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_round_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_round_wire <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 = '1') then + mult_round_wire <= mult_round; + end if; + end if; + end process; + end generate IFG57; + + IFG58: if (mult_round_reg = "CLOCK1") generate + process (clock1, mult_round, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_round_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_round_wire <= '0'; + elsif (rising_edge(clock1) and (ena1 = '1')) then + mult_round_wire <= mult_round; + end if; + end process; + end generate IFG58; + + IFG59: if (mult_round_reg = "CLOCK2") generate + process (clock2, mult_round, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_round_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_round_wire <= '0'; + elsif (rising_edge(clock2) and (ena2 = '1')) then + mult_round_wire <= mult_round; + end if; + end process; + end generate IFG59; + + IFG60: if (mult_round_reg = "CLOCK3") generate + process (clock3, mult_round, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_round_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_round_wire <= '0'; + elsif (rising_edge(clock3) and (ena3 = '1')) then + mult_round_wire <= mult_round; + end if; + end process; + end generate IFG60; + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set mult_saturation_wire) + -- The signal registered is mult_saturation + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if mult_saturation_reg + -- is unregistered and mult_saturation changes value + -- --------------------------------------------------------------------------------- + IFG61: if (mult_saturation_reg = "CLOCK0") generate + process (clock0, mult_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_saturate_wire <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 = '1') then + mult_saturate_wire <= mult_saturation; + end if; + end if; + end process; + end generate IFG61; + + IFG62: if (mult_saturation_reg = "CLOCK1") generate + process (clock1, mult_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_saturate_wire <= '0'; + elsif (rising_edge(clock1) and (ena1 = '1')) then + mult_saturate_wire <= mult_saturation; + end if; + end process; + end generate IFG62; + + IFG63: if (mult_saturation_reg = "CLOCK2") generate + process (clock2, mult_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_saturate_wire <= '0'; + elsif (rising_edge(clock2) and (ena2 = '1')) then + mult_saturate_wire <= mult_saturation; + end if; + end process; + end generate IFG63; + + IFG64: if (mult_saturation_reg = "CLOCK3") generate + process (clock3, mult_saturation, aclr0, aclr1, aclr2, aclr3) + begin + if (((mult_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + mult_saturate_wire <= '0'; + elsif (rising_edge(clock3) and (ena3 = '1')) then + mult_saturate_wire <= mult_saturation; + end if; + end process; + end generate IFG64; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set sload_upper_data_reg) + -- The signal registered is accum_sload_upper_data + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_sload_upper_data_reg + -- is unregistered and accum_sload_upper_data changes value + -- --------------------------------------------------------------------------------- + + IFG65: if (accum_sload_upper_data_reg = "CLOCK0") generate + process (clock0, accum_sload_upper_data, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_reg <= (others => '0'); + elsif (rising_edge(clock0)) then + if (ena0 = '1') then + sload_upper_data_reg <= accum_sload_upper_data; + end if; + end if; + end process; + end generate IFG65; + + IFG66: if (accum_sload_upper_data_reg = "CLOCK1") generate + process (clock1, accum_sload_upper_data, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_reg <= (others => '0'); + elsif (rising_edge(clock1) and (ena1 = '1')) then + sload_upper_data_reg <= accum_sload_upper_data; + end if; + end process; + end generate IFG66; + + IFG67: if (accum_sload_upper_data_reg = "CLOCK2") generate + process (clock2, accum_sload_upper_data, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_reg <= (others => '0'); + elsif (rising_edge(clock2) and (ena2 = '1')) then + sload_upper_data_reg <= accum_sload_upper_data; + end if; + end process; + end generate IFG67; + + IFG68: if (accum_sload_upper_data_reg = "CLOCK3") generate + process (clock3, accum_sload_upper_data, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_reg <= (others => '0'); + elsif (rising_edge(clock3) and (ena3 = '1')) then + sload_upper_data_reg <= accum_sload_upper_data; + end if; + end process; + end generate IFG68; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set sload_upper_data_wire) + -- The signal registered is sload_upper_data_latent + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_sload_upper_data_pipeline_reg + -- is unregistered and sload_upper_data_latent changes value + -- --------------------------------------------------------------------------------- + IFG69: if (accum_sload_upper_data_pipeline_reg = "CLOCK0") generate + process (clock0, sload_upper_data_latent, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_wire <= (others => '0'); + elsif (rising_edge(clock0)) then + if (ena0 = '1') then + sload_upper_data_wire <= sload_upper_data_latent; + end if; + end if; + end process; + end generate IFG69; + + IFG70: if (accum_sload_upper_data_pipeline_reg = "CLOCK1") generate + process (clock1, sload_upper_data_latent, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_wire <= (others => '0'); + elsif (rising_edge(clock1) and (ena1 = '1')) then + sload_upper_data_wire <= sload_upper_data_latent; + end if; + end process; + end generate IFG70; + + IFG71: if (accum_sload_upper_data_pipeline_reg = "CLOCK2") generate + process (clock2, sload_upper_data_latent, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_wire <= (others => '0'); + elsif (rising_edge(clock2) and (ena2 = '1')) then + sload_upper_data_wire <= sload_upper_data_latent; + end if; + end process; + end generate IFG71; + + IFG72: if (accum_sload_upper_data_pipeline_reg = "CLOCK3") generate + process (clock3, sload_upper_data_latent, aclr0, aclr1, aclr2, aclr3) + begin + if (((accum_sload_upper_data_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_upper_data_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + sload_upper_data_wire <= (others => '0'); + elsif (rising_edge(clock3) and (ena3 = '1')) then + sload_upper_data_wire <= sload_upper_data_latent; + end if; + end process; + end generate IFG72; + + + -- ---------------------------------------------------------------------------- + -- This block multiplies the two input numbers and sets the result to mult_final_out + -- ---------------------------------------------------------------------------- + process (mult_a, mult_b, sign_a_reg, sign_b_reg, mult_round_wire, mult_saturate_wire, signa, signb, temp_mult_zero) + variable temp_mult_int : std_logic_vector (int_width_a + int_width_b downto 0); + variable temp_mult : std_logic_vector (int_width_a + int_width_b -1 downto 0):= (others => '0'); + variable neg_a, neg_b, is_signed : std_logic; + variable mult_round_out : std_logic_vector (int_width_a + int_width_b - 1 downto 0) := (others => '0'); + variable mult_saturate_overflow : std_logic := '0'; + variable mult_saturate_out : std_logic_vector (int_width_a + int_width_b - 1 downto 0) := (others => '0'); + variable mult_result : std_logic_vector (int_width_a + int_width_b - 1 downto 0) := (others => '0'); + + variable int_mult_a : std_logic_vector (int_width_a - 1 downto 0); + variable int_mult_b : std_logic_vector (int_width_b - 1 downto 0); + variable mult_a_zero_bits_pad : std_logic_vector (int_width_a - width_a - 1 downto 0) := (others => '0'); + variable mult_b_zero_bits_pad : std_logic_vector (int_width_b - width_b - 1 downto 0) := (others => '0'); + begin + is_signed := '0'; + + if (port_signa = "PORT_CONNECTIVITY") then + if (((representation_a = "SIGNED") and (signa = 'Z')) or (sign_a_reg = '1')) then + neg_a := mult_a (width_a-1); + is_signed :='1'; + end if; + else + if (((representation_a = "SIGNED") and (port_signa = "PORT_UNUSED")) or (sign_a_reg = '1')) then + neg_a := mult_a (width_a-1); + is_signed :='1'; + end if; + end if; + + if (port_signb = "PORT_CONNECTIVITY") then + if (((representation_b = "SIGNED") and (signb = 'Z')) or (sign_b_reg = '1')) then + neg_b := mult_b (width_b-1); + is_signed :='1'; + end if; + else + if (((representation_b = "SIGNED") and (port_signb = "PORT_UNUSED")) or (sign_b_reg = '1')) then + neg_b := mult_b (width_b-1); + is_signed :='1'; + end if; + end if; + + if(int_width_a > width_a) then + int_mult_a := mult_a & mult_a_zero_bits_pad; + else + int_mult_a := mult_a; + end if; + + if(int_width_b > width_b) then + int_mult_b := mult_b & mult_b_zero_bits_pad; + else + int_mult_b := mult_b; + end if; + + if (port_signa = "PORT_CONNECTIVITY" and port_signb ="PORT_CONNECTIVITY") then + if (((representation_a = "SIGNED") and (signa = 'Z')) or (sign_a_reg = '1')) then + if (((representation_b = "SIGNED") and( signb = 'Z')) or (sign_b_reg = '1')) then + temp_mult_int := signed (temp_mult_zero) + (signed (int_mult_a) * signed (int_mult_b)); + else + temp_mult_int := signed (temp_mult_zero) + (signed (int_mult_a) * unsigned (int_mult_b)); + end if; + else + if (((representation_b = "SIGNED") and (signb = 'Z')) or (sign_b_reg = '1')) then + temp_mult_int := signed (temp_mult_zero) + (unsigned (int_mult_a) * signed (int_mult_b)); + else + temp_mult_int := signed (temp_mult_zero) + (unsigned (int_mult_a) * unsigned (int_mult_b)); + end if; + end if; + else + if (((representation_a = "SIGNED") and (port_signa = "PORT_UNUSED")) or (sign_a_reg = '1')) then + if (((representation_b = "SIGNED") and(port_signb = "PORT_UNUSED")) or (sign_b_reg = '1')) then + temp_mult_int := signed (temp_mult_zero) + (signed (int_mult_a) * signed (int_mult_b)); + else + temp_mult_int := signed (temp_mult_zero) + (signed (int_mult_a) * unsigned (int_mult_b)); + end if; + else + if (((representation_b = "SIGNED") and (port_signb = "PORT_UNUSED")) or (sign_b_reg = '1')) then + temp_mult_int := signed (temp_mult_zero) + (unsigned (int_mult_a) * signed (int_mult_b)); + else + temp_mult_int := signed (temp_mult_zero) + (unsigned (int_mult_a) * unsigned (int_mult_b)); + end if; + end if; + end if; + + temp_mult := temp_mult_int (int_width_a + int_width_b -1 downto 0); + + if (FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) then + -- StratixII rounding support + + -- This is based on both input is in Q1.15 format with assumption + -- width_a = 16 and width_b = 16 + + if ((multiplier_rounding = "YES") or + ((multiplier_rounding = "VARIABLE") and (mult_round_wire = '1'))) then + mult_round_out := unsigned (temp_mult) + ( 2 ** (int_width_a + int_width_b - 18)); + else + mult_round_out := temp_mult; + end if; + + -- StratixII saturation support + + if ((multiplier_saturation = "YES") or + (( multiplier_saturation = "VARIABLE") and (mult_saturate_wire = '1'))) then + if((mult_round_out(int_width_a + int_width_b - 1) = '0') and (mult_round_out(int_width_a + int_width_b - 2) = '1')) then + mult_saturate_overflow := '1'; + else + mult_saturate_overflow := '0'; + end if; + + if (mult_saturate_overflow = '0') then + mult_saturate_out := mult_round_out; + else + for i in (int_width_a + int_width_b - 1) downto (int_width_a + int_width_b - 2) loop + mult_saturate_out(i) := mult_round_out(int_width_a + int_width_b - 1); + end loop; + + for i in (int_width_a + int_width_b - 3) downto 0 loop + mult_saturate_out(i) := not mult_round_out(int_width_a + int_width_b - 1); + end loop; + + for i in (int_width_a + int_width_b - 34) downto 0 loop + mult_saturate_out(i) := '0'; + end loop; + + end if; + else + mult_saturate_out := mult_round_out; + mult_saturate_overflow := '0'; + end if; + + if ((multiplier_rounding = "YES") or + ((multiplier_rounding = "VARIABLE") and (mult_round_wire = '1'))) then + + mult_result := mult_saturate_out; + + for i in (int_width_a + int_width_b - 18) downto 0 loop + mult_result(i) := '0'; + end loop; + else + mult_result := mult_saturate_out; + end if; + + mult_is_saturated_wire <= mult_saturate_overflow; + end if; + + if (not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) then + mult_final_out <= temp_mult; + else + mult_final_out <= mult_result; + end if; + + end process; + + + -- ---------------------------------------------------------------------------- + -- This process contains 1 register and a combinatorial block (to set mult_res) + -- The signal registered is mult_out_latent + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if multiplier_reg + -- is unregistered and mult_out_latent changes value + -- ---------------------------------------------------------------------------- + IFG73: if (multiplier_reg = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, mult_out_latent) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_res <= (others =>'0'); + elsif (rising_edge(clock0)) then + if (ena0 ='1') then + mult_res <= mult_out_latent; + end if; + end if; + end process; + end generate IFG73; + + IFG74: if (multiplier_reg = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, mult_out_latent) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_res <= (others =>'0'); + elsif (rising_edge(clock1) and (ena1 ='1')) then + mult_res <= mult_out_latent; + end if; + end process; + end generate IFG74; + + IFG75: if (multiplier_reg = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, mult_out_latent) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_res <= (others =>'0'); + elsif (rising_edge(clock2) and (ena2 ='1')) then + mult_res <= mult_out_latent; + end if; + end process; + end generate IFG75; + + IFG76: if (multiplier_reg = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, mult_out_latent) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_res <= (others =>'0'); + elsif (rising_edge(clock3) and (ena3 ='1')) then + mult_res <= mult_out_latent; + end if; + end process; + end generate IFG76; + + -- ---------------------------------------------------------------------------- + -- This process contains 1 register and a combinatorial block (to set mult_is_saturated_reg) + -- The signal registered is mult_is_saturated_wire + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if multiplier_reg + -- is unregistered and mult_is_saturated_wire changes value + -- ---------------------------------------------------------------------------- + IFG77: if (multiplier_reg = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, mult_is_saturated_wire) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_is_saturated_reg <= '0'; + elsif (rising_edge(clock0)) then + if (ena0 ='1') then + mult_is_saturated_reg <= mult_is_saturated_wire; + end if; + end if; + end process; + end generate IFG77; + + IFG78: if (multiplier_reg = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, mult_is_saturated_wire) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_is_saturated_reg <= '0'; + elsif (rising_edge(clock1) and (ena1 ='1')) then + mult_is_saturated_reg <= mult_is_saturated_wire; + end if; + end process; + end generate IFG78; + + IFG79: if (multiplier_reg = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, mult_is_saturated_wire) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_is_saturated_reg <= '0'; + elsif (rising_edge(clock2) and (ena2 ='1')) then + mult_is_saturated_reg <= mult_is_saturated_wire; + end if; + end process; + end generate IFG79; + + IFG80: if (multiplier_reg = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, mult_is_saturated_wire) + begin + if (((multiplier_aclr= "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1'))) then + mult_is_saturated_reg <= '0'; + elsif (rising_edge(clock3) and (ena3 ='1')) then + mult_is_saturated_reg <= mult_is_saturated_wire; + end if; + end process; + end generate IFG80; + + IFG81: if (extra_multiplier_latency >0) generate + process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3) + -- ------------------------------------------------------------------------ + -- This process is only valid if extra_multiplier_latency is greater then 0 + -- ------------------------------------------------------------------------ + variable head_mult_int: integer := 0; + + begin + -- ------------------------------------------------------------------------ + -- This process is only valid if extra_multiplier_latency is greater then 0 + -- ------------------------------------------------------------------------ + + if ( (((multiplier_aclr= "ACLR0") or (multiplier_reg = "UNREGISTERED")) and (aclr0 = '1')) or + ((multiplier_reg /= "UNREGISTERED") and + ( ((multiplier_aclr= "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr= "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr= "ACLR3") and (aclr3 = '1')) )) ) then + mult_pipe <= (others => (others => '0')); + mult_full <= (others => '0'); + sload_upper_data_full <= (others => '0'); + sload_upper_data_pipe <= (others => (others => '0')); + + + elsif ( (rising_edge(clock0) and ((multiplier_reg = "CLOCK0") or (multiplier_reg = "UNREGISTERED"))) or + (rising_edge(clock1) and (multiplier_reg = "CLOCK1")) or + (rising_edge(clock2) and (multiplier_reg = "CLOCK2")) or + (rising_edge(clock3) and (multiplier_reg = "CLOCK3")) ) then + + if ((((multiplier_reg = "CLOCK0") or (multiplier_reg = "UNREGISTERED")) and (ena0 ='1')) or + ((multiplier_reg = "CLOCK1") and (ena1 ='1')) or + ((multiplier_reg = "CLOCK2") and (ena2 ='1')) or + ((multiplier_reg = "CLOCK3") and (ena3 ='1')) ) then + + if (extra_multiplier_latency >0) then + head_mult_int := head_mult; + mult_pipe (head_mult_int) <= sign_a_reg & sign_b_reg & acc_sload_reg & addsub_reg & '0' & mult_final_out; + sload_upper_data_pipe (head_mult_int) <= sload_upper_data_reg; + head_mult_int := (head_mult_int +1) mod (extra_multiplier_latency); + + if (extra_multiplier_latency = 1) then + mult_full <= sign_a_reg & sign_b_reg & acc_sload_reg & addsub_reg & '0' & mult_final_out; + sload_upper_data_full <= sload_upper_data_reg; + else + mult_full <= (mult_pipe(head_mult_int)); + sload_upper_data_full <= (sload_upper_data_pipe(head_mult_int)); + end if; + + head_mult <= head_mult_int; + end if; + end if; + end if; + end process; + end generate IFG81; + + process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3) + -- ------------------------------------------------------------- + -- This is the main process block that performs the accumulation + -- ------------------------------------------------------------- + variable head_result_int : integer := 0; + variable temp_sum : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable result_full : std_logic_vector (int_width_result downto 0) := (others => '0'); + + variable cout_int, overflow_int :std_logic; + variable temp_sum_zero : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable accum_int, addsub_int, signed_int : std_logic; + variable result_temp : std_logic_vector (int_width_result -1 downto 0); + variable sign_extend : std_logic_vector (int_width_result - int_width_a - int_width_b - 1 downto 0) := (others => '0'); + variable mult_res_temp : std_logic_vector (int_width_result -1 downto 0) := (others => '0'); + variable accum_final_out : std_logic_vector (int_width_result - 1 downto 0) := (others => '0'); + variable accum_round_out : std_logic_vector (int_width_result - 1 downto 0) := (others => '0'); + variable accum_saturate_overflow : std_logic := '0'; + variable accum_saturate_out : std_logic_vector (int_width_result - 1 downto 0) := (others => '0'); + variable accum_result_sign_bits : std_logic_vector (int_width_result - int_width_a - int_width_b + 2 - 1 downto 0) := (others => '0'); + variable accum_result_sign_bits_ones : std_logic_vector (int_width_result - int_width_a - int_width_b + 2 - 1 downto 0) := (others => '1'); + variable accum_result_sign_bits_zeros : std_logic_vector (int_width_result - int_width_a - int_width_b + 2 - 1 downto 0) := (others => '0'); + variable accum_result : std_logic_vector (int_width_result - 1 downto 0) := (others => '0'); + variable upper_data_sign_extend : std_logic := '0'; + variable upper_data_sign_bit : std_logic := '0'; + variable result_pipe : pipeline_accum := (others => (others => '0')); + variable sat_for_ini : integer := int_width_a + int_width_b - 34; + variable bits_to_round : integer := int_width_a + int_width_b - 18; + variable accum_sat_for_limit : integer := int_width_a + int_width_b - 33; + + begin + + -- ------------------------------------------------------------- + -- This is the main process block that performs the accumulation + -- ------------------------------------------------------------- + + if (((output_aclr= "ACLR0") and (aclr0 = '1')) or + ((output_aclr= "ACLR1") and (aclr1 = '1')) or + ((output_aclr= "ACLR2") and (aclr2 = '1')) or + ((output_aclr= "ACLR3") and (aclr3 = '1'))) then + temp_sum := (others => '0'); + result_pipe := (others => (others => '0')); + result <= (others => '0'); + result_int <= (others => '0'); + overflow_int := '0'; + overflow <= '0'; + accum_is_saturated_out <= '0'; + mult_is_saturated_out <= '0'; + + elsif ( (rising_edge(clock0) and (output_reg = "CLOCK0")) or + (rising_edge(clock1) and (output_reg = "CLOCK1")) or + (rising_edge(clock2) and (output_reg = "CLOCK2")) or + (rising_edge(clock3) and (output_reg = "CLOCK3")) ) then + + if (((output_reg = "CLOCK0") and (ena0 ='1')) or + ((output_reg = "CLOCK1") and (ena1 ='1')) or + ((output_reg = "CLOCK2") and (ena2 ='1')) or + ((output_reg = "CLOCK3") and (ena3 ='1')) ) then + + if (accum_sload = 'Z') then + accum_int := '0'; + else + accum_int := accum_sload_pipe; + end if; + + -- check if addition flag is to be set + if (port_addnsub = "PORT_CONNECTIVITY") then + if (((addnsub = 'Z') and (accum_direction = "ADD")) or (addsub_pipe = '1')) then + addsub_int := '1'; + else + addsub_int := '0'; + end if; + else + if (((port_addnsub = "PORT_UNUSED") and (accum_direction = "ADD")) or (addsub_pipe = '1')) then + addsub_int := '1'; + else + addsub_int := '0'; + end if; + end if; + + -- check if signed flag is to be set + if (port_signa = "PORT_CONNECTIVITY" and port_signb = "PORT_CONNECTIVITY") then + if ((((representation_b = "SIGNED") and (signb = 'Z')) or (sign_b_pipe = '1')) or + (((representation_a = "SIGNED") and (signa = 'Z')) or (sign_a_pipe = '1'))) then + signed_int := '1'; + else + signed_int := '0'; + end if; + else + if ((((representation_b = "SIGNED") and (port_signb = "PORT_UNUSED")) or (sign_b_pipe = '1')) or + (((representation_a = "SIGNED") and (port_signa = "PORT_UNUSED")) or (sign_a_pipe = '1'))) then + signed_int := '1'; + else + signed_int := '0'; + end if; + end if; + + sign_extend := (others => (signed_int and mult_res (int_width_a + int_width_b -1))); + if (int_width_result >= (int_width_a + int_width_b)) then + mult_res_temp := sign_extend & mult_res; + else + mult_res_temp := sign_extend & mult_res(int_width_result -1 downto 0); + end if; + + if (int_width_result > width_result) then + upper_data_sign_extend := '1'; + else + upper_data_sign_extend := '0'; + end if; + + if (accum_int ='1') then + if ((not IS_STRATIXII) and + (not IS_CYCLONEII)) then + result_temp := (others => '0'); + else + upper_data_sign_bit := (signed_int and sload_upper_data_wire(width_upper_data - 1)); + result_temp := (others => '0'); + + if(upper_data_sign_extend = '1') then + for i in (int_width_result - 1) downto (int_extra_width + width_result) loop + result_temp(i) := upper_data_sign_bit; + end loop; + end if; + + if(width_upper_data > width_result) then + result_temp(int_extra_width + width_result - 1 downto int_extra_width) := sload_upper_data_wire(width_result - 1 downto 0); + else + result_temp(int_extra_width + width_result - 1 downto int_extra_width + width_result - width_upper_data) := sload_upper_data_wire; + end if; + end if; + else + result_temp := result_int; + end if; + + + if (addsub_int = '1') then -- add the numbers if the add flag is turned on + temp_sum := unsigned(temp_sum_zero)+ unsigned (result_temp) + unsigned (mult_res_temp); + + cout_int := temp_sum (int_width_result); + else -- subtract the numbers if the add flag is turned off + temp_sum := unsigned(temp_sum_zero)+ unsigned (result_temp) - unsigned (mult_res_temp); + + + if (unsigned (result_temp) >= unsigned (mult_res_temp)) then + cout_int := '1'; + else + cout_int := '0'; + end if; + end if; + + if (signed_int = '1' and (not (mult_res = temp_mult_zero))) then + overflow_int := (((not (mult_res (int_width_a + int_width_b-1) xor result_temp (int_width_result -1))) xor (not (addsub_int))) + and (result_temp (int_width_result -1) xor temp_sum (int_width_result -1))); + else + overflow_int := not (addsub_int xor cout_int); + end if; + + + if (IS_STRATIXII) then + -- StratixII rounding support + + -- This is based on both input is in Q1.15 format with assumption + -- width_a = 16 and width_b = 16 + -- result_width = widht_a + width_b + + if ((accumulator_rounding = "YES") or + ((accumulator_rounding = "VARIABLE") and (accum_round_wire = '1'))) then + accum_round_out := temp_sum(int_width_result -1 downto 0); + accum_round_out := signed (accum_round_out) + ( 2 ** bits_to_round); + else + accum_round_out := temp_sum(int_width_result -1 downto 0); + end if; + + -- StratixII saturation support + + if ((accumulator_saturation = "YES") or + ((accumulator_saturation = "VARIABLE") and (accum_saturate_wire = '1'))) then + accum_result_sign_bits := accum_round_out(int_width_result - 1 downto int_width_a + int_width_b - 2); + if ((accum_result_sign_bits = accum_result_sign_bits_ones) or + (accum_result_sign_bits = accum_result_sign_bits_zeros)) then + accum_saturate_overflow := '0'; + else + accum_saturate_overflow := '1'; + end if; + + if (accum_saturate_overflow = '0') then + accum_saturate_out := accum_round_out; + accum_saturate_out(sat_for_ini) := '0'; + else + + for i in (int_width_result - 1) downto (int_width_a + int_width_b - 2) loop + accum_saturate_out(i) := accum_round_out(int_width_result - 1); + end loop; + + for i in (int_width_a + int_width_b - 3) downto (accum_sat_for_limit) loop + accum_saturate_out(i) := not accum_round_out(int_width_result - 1); + end loop; + + for i in (sat_for_ini) downto 0 loop + accum_saturate_out(i) := '0'; + end loop; + + end if; + else + accum_saturate_out := accum_round_out; + accum_saturate_overflow := '0'; + end if; + + if ((accumulator_rounding = "YES") or + ((accumulator_rounding = "VARIABLE") and (accum_round_wire = '1'))) then + + accum_result := accum_saturate_out; + for i in (bits_to_round) downto 0 loop + accum_result(i) := '0'; + end loop; + else + accum_result := accum_saturate_out; + end if; + + accum_is_saturated_out <= accum_saturate_overflow; + mult_is_saturated_out <= mult_is_saturated_reg; + + end if; + + if (not IS_STRATIXII) then + accum_final_out := temp_sum(int_width_result -1 downto 0); + else + accum_final_out := accum_result; + end if; + + if (extra_accumulator_latency = 0) then + result <= accum_final_out(width_result - 1 + int_extra_width downto int_extra_width); + overflow <= overflow_int; + else + head_result_int := head_result; + result_pipe (head_result_int) := (overflow_int & accum_final_out); + head_result_int := (head_result_int +1) mod (extra_accumulator_latency + 1); + result_full := result_pipe(head_result_int); + result <= result_full (width_result - 1 + int_extra_width downto int_extra_width); + overflow <= result_full (int_width_result); + head_result <= head_result_int; + end if; + + result_int <= accum_final_out; + end if; + end if; + end process; + +end behaviour; -- end of ALT_MULT_ACCUM + +---------------------------------------------------------------------------- +-- Module Name : altmult_add +-- +-- Description : a*b + c*d +-- +-- Limitation : Stratix DSP block +-- +-- Results expected : signed & unsigned, maximum of 3 pipelines(latency) each. +-- possible of zero pipeline. +-- +---------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.ALTERA_DEVICE_FAMILIES.all; + +entity altmult_add is + generic ( + + -- --------------------- + -- PARAMETER DECLARATION + -- --------------------- + width_a : natural := 1; + width_b : natural := 1; + width_result : natural := 1; + number_of_multipliers : natural := 1; + + -- A inputs + input_register_a0 : string := "CLOCK0"; + input_aclr_a0 : string := "ACLR3"; + input_source_a0 : string := "DATAA"; + + input_register_a1 : string := "CLOCK0"; + input_aclr_a1 : string := "ACLR3"; + input_source_a1 : string := "DATAA"; + + input_register_a2 : string := "CLOCK0"; + input_aclr_a2 : string := "ACLR3"; + input_source_a2 : string := "DATAA"; + + input_register_a3 : string := "CLOCK0"; + input_aclr_a3 : string := "ACLR3"; + input_source_a3 : string := "DATAA"; + + port_signa : string := "PORT_CONNECTIVITY"; + representation_a : string := "UNSIGNED"; + signed_register_a : string := "CLOCK0"; + signed_aclr_a : string := "ACLR3"; + signed_pipeline_register_a : string := "CLOCK0"; + signed_pipeline_aclr_a : string := "ACLR3"; + + scanouta_register : string := "UNREGISTERED"; + scanouta_aclr : string := "NONE"; + + + -- B inputs + input_register_b0 : string := "CLOCK0"; + input_aclr_b0 : string := "ACLR3"; + input_source_b0 : string := "DATAB"; + + input_register_b1 : string := "CLOCK0"; + input_aclr_b1 : string := "ACLR3"; + input_source_b1 : string := "DATAB"; + + input_register_b2 : string := "CLOCK0"; + input_aclr_b2 : string := "ACLR3"; + input_source_b2 : string := "DATAB"; + + input_register_b3 : string := "CLOCK0"; + input_aclr_b3 : string := "ACLR3"; + input_source_b3 : string := "DATAB"; + + port_signb : string := "PORT_CONNECTIVITY"; + representation_b : string := "UNSIGNED"; + signed_register_b : string := "CLOCK0"; + signed_aclr_b : string := "ACLR3"; + signed_pipeline_register_b : string := "CLOCK0"; + signed_pipeline_aclr_b : string := "ACLR3"; + + -- Multiplier parameter + multiplier_register0 : string := "CLOCK0"; + multiplier_aclr0 : string := "ACLR3"; + multiplier_register1 : string := "CLOCK0"; + multiplier_aclr1 : string := "ACLR3"; + multiplier_register2 : string := "CLOCK0"; + multiplier_aclr2 : string := "ACLR3"; + multiplier_register3 : string := "CLOCK0"; + multiplier_aclr3 : string := "ACLR3"; + + port_addnsub1 : string := "PORT_CONNECTIVITY"; + addnsub_multiplier_register1 : string := "CLOCK0"; + addnsub_multiplier_aclr1 : string := "ACLR3"; + addnsub_multiplier_pipeline_register1 : string := "CLOCK0"; + addnsub_multiplier_pipeline_aclr1 : string := "ACLR3"; + + port_addnsub3 : string := "PORT_CONNECTIVITY"; + addnsub_multiplier_register3 : string := "CLOCK0"; + addnsub_multiplier_aclr3 : string := "ACLR3"; + addnsub_multiplier_pipeline_register3 : string := "CLOCK0"; + addnsub_multiplier_pipeline_aclr3 : string := "ACLR3"; + + multiplier1_direction : string := "ADD"; + multiplier3_direction : string := "ADD"; + + -- output parameters + output_register : string := "CLOCK0"; + output_aclr : string := "ACLR3"; + + -- StratixII parameters + multiplier01_rounding : string := "NO"; + multiplier01_saturation : string := "NO"; + mult01_round_aclr : string := "ACLR3"; + mult01_round_register : string := "CLOCK0"; + mult01_saturation_register : string := "CLOCK0"; + mult01_saturation_aclr : string := "ACLR3"; + multiplier23_rounding : string := "NO"; + multiplier23_saturation : string := "NO"; + mult23_round_aclr : string := "ACLR3"; + mult23_round_register : string := "CLOCK0"; + mult23_saturation_register : string := "CLOCK0"; + mult23_saturation_aclr : string := "ACLR3"; + adder1_rounding : string := "NO"; + adder3_rounding : string := "NO"; + addnsub1_round_aclr : string := "ACLR3"; + addnsub1_round_pipeline_aclr : string := "ACLR3"; + addnsub1_round_register : string := "CLOCK0"; + addnsub1_round_pipeline_register : string := "CLOCK0"; + addnsub3_round_aclr : string := "ACLR3"; + addnsub3_round_pipeline_aclr : string := "ACLR3"; + addnsub3_round_register : string := "CLOCK0"; + addnsub3_round_pipeline_register : string := "CLOCK0"; + port_mult0_is_saturated : string := "UNUSED"; + port_mult1_is_saturated : string := "UNUSED"; + port_mult2_is_saturated : string := "UNUSED"; + port_mult3_is_saturated : string := "UNUSED"; + + -- Stratix III parameters + -- Rounding parameters + output_rounding : string := "NO"; + output_round_type : string := "NEAREST_INTEGER"; + width_msb : integer := 17; + output_round_register : string := "UNREGISTERED"; + output_round_aclr : string := "NONE"; + output_round_pipeline_register : string := "UNREGISTERED"; + output_round_pipeline_aclr : string := "NONE"; + + chainout_rounding : string := "NO"; + chainout_round_register : string := "UNREGISTERED"; + chainout_round_aclr : string := "NONE"; + chainout_round_pipeline_register : string := "UNREGISTERED"; + chainout_round_pipeline_aclr : string := "NONE"; + chainout_round_output_register : string := "UNREGISTERED"; + chainout_round_output_aclr : string := "NONE"; + + -- saturation parameters + port_output_is_overflow : string := "PORT_UNUSED"; + port_chainout_sat_is_overflow : string := "PORT_UNUSED"; + output_saturation : string := "NO"; + output_saturate_type : string := "ASYMMETRIC"; + width_saturate_sign : integer := 1; + output_saturate_register : string := "UNREGISTERED"; + output_saturate_aclr : string := "NONE"; + output_saturate_pipeline_register : string := "UNREGISTERED"; + output_saturate_pipeline_aclr : string := "NONE"; + + chainout_saturation : string := "NO"; + chainout_saturate_register : string := "UNREGISTERED"; + chainout_saturate_aclr : string := "NONE"; + chainout_saturate_pipeline_register : string := "UNREGISTERED"; + chainout_saturate_pipeline_aclr : string := "NONE"; + chainout_saturate_output_register : string := "UNREGISTERED"; + chainout_saturate_output_aclr : string := "NONE"; + + -- chainout parameters + chainout_adder : string := "NO"; + chainout_register : string := "UNREGISTERED"; + chainout_aclr : string := "ACLR3"; + width_chainin : integer := 1; + zero_chainout_output_register : string := "UNREGISTERED"; + zero_chainout_output_aclr : string := "NONE"; + + -- rotate & shift parameters + shift_mode : string := "NO"; + rotate_aclr : string := "NONE"; + rotate_register : string := "UNREGISTERED"; + rotate_pipeline_register : string := "UNREGISTERED"; + rotate_pipeline_aclr : string := "NONE"; + rotate_output_register : string := "UNREGISTERED"; + rotate_output_aclr : string := "NONE"; + shift_right_register : string := "UNREGISTERED"; + shift_right_aclr : string := "NONE"; + shift_right_pipeline_register : string := "UNREGISTERED"; + shift_right_pipeline_aclr : string := "NONE"; + shift_right_output_register : string := "UNREGISTERED"; + shift_right_output_aclr : string := "NONE"; + + -- loopback parameters + zero_loopback_register : string := "UNREGISTERED"; + zero_loopback_aclr : string := "NONE"; + zero_loopback_pipeline_register : string := "UNREGISTERED"; + zero_loopback_pipeline_aclr : string := "NONE"; + zero_loopback_output_register : string := "UNREGISTERED"; + zero_loopback_output_aclr : string := "NONE"; + + -- accumulator parameters + accum_sload_register : string := "UNREGISTERED"; + accum_sload_aclr : string := "NONE"; + accum_sload_pipeline_register : string := "UNREGISTERED"; + accum_sload_pipeline_aclr : string := "NONE"; + accum_direction : string := "ADD"; + accumulator : string := "NO"; + + -- Stratix V parameters + width_c : integer := 22; + loadconst_value : integer := 64; + preadder_mode : string := "SIMPLE"; + preadder_direction_0 : string := "ADD"; + preadder_direction_1 : string := "ADD"; + preadder_direction_2 : string := "ADD"; + preadder_direction_3 : string := "ADD"; + input_register_c0 : string := "CLOCK0"; + input_aclr_c0 : string := "ACLR0"; + coefsel0_register : string := "CLOCK0"; + coefsel1_register : string := "CLOCK0"; + coefsel2_register : string := "CLOCK0"; + coefsel3_register : string := "CLOCK0"; + coefsel0_aclr : string := "ACLR0"; + coefsel1_aclr : string := "ACLR0"; + coefsel2_aclr : string := "ACLR0"; + coefsel3_aclr : string := "ACLR0"; + systolic_delay1 : string := "UNREGISTERED"; + systolic_delay3 : string := "UNREGISTERED"; + systolic_aclr1 : string := "NONE"; + systolic_aclr3 : string := "NONE"; + coef0_0 : integer := 0; + coef0_1 : integer := 0; + coef0_2 : integer := 0; + coef0_3 : integer := 0; + coef0_4 : integer := 0; + coef0_5 : integer := 0; + coef0_6 : integer := 0; + coef0_7 : integer := 0; + coef1_0 : integer := 0; + coef1_1 : integer := 0; + coef1_2 : integer := 0; + coef1_3 : integer := 0; + coef1_4 : integer := 0; + coef1_5 : integer := 0; + coef1_6 : integer := 0; + coef1_7 : integer := 0; + coef2_0 : integer := 0; + coef2_1 : integer := 0; + coef2_2 : integer := 0; + coef2_3 : integer := 0; + coef2_4 : integer := 0; + coef2_5 : integer := 0; + coef2_6 : integer := 0; + coef2_7 : integer := 0; + coef3_0 : integer := 0; + coef3_1 : integer := 0; + coef3_2 : integer := 0; + coef3_3 : integer := 0; + coef3_4 : integer := 0; + coef3_5 : integer := 0; + coef3_6 : integer := 0; + coef3_7 : integer := 0; + width_coef : integer := 18; + + -- General setting parameters + extra_latency : integer := 0; + dedicated_multiplier_circuitry : string := "AUTO"; + dsp_block_balancing : string := "AUTO"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altmult_add"; + intended_device_family : string := "Stratix" + ); + + port ( + + -- ---------------- + -- PORT DECLARATION + -- ---------------- + + -- data input ports + dataa : in std_logic_vector(number_of_multipliers * width_a -1 downto 0); + datab : in std_logic_vector(number_of_multipliers * width_b -1 downto 0); + + scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0'); + scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0'); + + sourcea : in std_logic_vector((number_of_multipliers -1) downto 0) := (others => '0'); + sourceb : in std_logic_vector((number_of_multipliers -1) downto 0) := (others => '0'); + + -- clock ports + clock3 : in std_logic := '1'; + clock2 : in std_logic := '1'; + clock1 : in std_logic := '1'; + clock0 : in std_logic := '1'; + + -- clear ports + aclr3 : in std_logic := '0'; + aclr2 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + aclr0 : in std_logic := '0'; + + -- clock enable signals + ena3 : in std_logic := '1'; + ena2 : in std_logic := '1'; + ena1 : in std_logic := '1'; + ena0 : in std_logic := '1'; + + -- control signals + signa : in std_logic := 'Z'; + signb : in std_logic := 'Z'; + addnsub1 : in std_logic := 'Z'; + addnsub3 : in std_logic := 'Z'; + + -- StratixII only input ports + mult01_round : in std_logic := '0'; + mult23_round : in std_logic := '0'; + mult01_saturation : in std_logic := '0'; + mult23_saturation : in std_logic := '0'; + addnsub1_round : in std_logic := '0'; + addnsub3_round : in std_logic := '0'; + + -- Stratix III only input ports + output_round : in std_logic := '0'; + chainout_round : in std_logic := '0'; + output_saturate : in std_logic := '0'; + chainout_saturate : in std_logic := '0'; + chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0'); + zero_chainout : in std_logic := '0'; + rotate : in std_logic := '0'; + shift_right : in std_logic := '0'; + zero_loopback : in std_logic := '0'; + accum_sload : in std_logic := '0'; + + -- Stratix V only input ports + coefsel0 : in std_logic_vector (2 downto 0) := (others => '0'); + coefsel1 : in std_logic_vector (2 downto 0) := (others => '0'); + coefsel2 : in std_logic_vector (2 downto 0) := (others => '0'); + coefsel3 : in std_logic_vector (2 downto 0) := (others => '0'); + datac : in std_logic_vector (number_of_multipliers * width_c -1 downto 0) := (others => '0'); + + + -- output ports + result : out std_logic_vector(width_result -1 downto 0) := (others => '0'); + scanouta : out std_logic_vector (width_a -1 downto 0) := (others => '0'); + scanoutb : out std_logic_vector (width_b -1 downto 0) := (others => '0'); + + -- StratixII only output ports + mult0_is_saturated : out std_logic := '0'; + mult1_is_saturated : out std_logic := '0'; + mult2_is_saturated : out std_logic := '0'; + mult3_is_saturated : out std_logic := '0'; + + -- Stratix III only output ports + overflow : out std_logic := '0'; + chainout_sat_overflow : out std_logic := '0' + + ); + +end altmult_add; + +architecture behaviour of altmult_add is + + -- --------------------------- + -- SIGNAL AND TYPE DECLARATION + -- --------------------------- + + function resolve_internal_width (ARG : integer;ARG2 : integer) return integer is + variable changed_width:integer := 0; + begin + if (multiplier01_saturation = "NO" and multiplier23_saturation = "NO" and multiplier01_rounding = "NO" and multiplier23_rounding = "NO" + and output_saturation = "NO" and output_rounding = "NO" and chainout_adder = "NO" and input_source_b0 /= "LOOPBACK" ) then + if (ARG2 = 0) then + changed_width := width_a; + else + changed_width := width_b; + end if; + else + if (ARG < 18) then + changed_width := 18; + else + if (ARG2 = 0) then + changed_width := width_a; + else + changed_width := width_b; + end if; + end if; + + end if; + return changed_width; + end resolve_internal_width; + -- This constant int_width_a would be used internally in this model + -- to represent width_a + constant int_width_a : natural := resolve_internal_width(width_a, 0); + -- This constant int_width_b woudl be used internally in this model + -- to represent width_b + constant int_width_b : natural := resolve_internal_width(width_b, 1); + + function resolve_internal_mult_diff return integer is + variable changed_value :integer := 0; + begin + if (multiplier01_saturation = "NO" and multiplier23_saturation = "NO" and multiplier01_rounding = "NO" and multiplier23_rounding = "NO" + and output_rounding = "NO" and output_saturation = "NO" and chainout_adder = "NO") then + changed_value := 0; + else + if (chainout_adder = "YES") then + if (width_result > width_a + width_b + 8) then + changed_value := 0; + else + changed_value := int_width_a - width_a + int_width_b - width_b; + end if; + else + changed_value := int_width_a - width_a + int_width_b - width_b; + end if; + end if; + return changed_value; + end resolve_internal_mult_diff; + + constant int_mult_diff_bit : integer := resolve_internal_mult_diff; + + function resolve_internal_width_result return integer is + variable changed_width_result:integer := 0; + begin + if (multiplier01_saturation = "NO" and multiplier23_saturation = "NO" and multiplier01_rounding = "NO" and multiplier23_rounding = "NO" + and output_rounding = "NO" and output_saturation = "NO" and chainout_rounding = "NO" and chainout_saturation = "NO" and chainout_adder = "NO" and shift_mode = "NO") then + changed_width_result := width_result; + else + if (shift_mode /= "NO") then + changed_width_result := 64; + elsif (chainout_adder = "YES") then + changed_width_result := 44; + elsif (width_result > (int_width_a + int_width_b)) then + changed_width_result := width_result + (width_result - int_width_a - int_width_b); + else + changed_width_result := int_width_a + int_width_b; + end if; + end if; + return changed_width_result; + end resolve_internal_width_result; + + constant int_width_result : natural := resolve_internal_width_result; + + function resolve_result_width return integer is + variable width_value :integer := 0; + begin + width_value := 44; + return width_value; + end resolve_result_width; + + constant result_width : integer := resolve_result_width; + + function resolve_saturation_position return integer is + variable saturation_value :integer := 0; + begin + if (output_saturation /= "NO" and chainout_saturation = "NO") then + if (((width_a + width_b )> width_result) and (width_result >= width_saturate_sign)) then + saturation_value := (int_width_a + int_width_b - width_saturate_sign - (width_a + width_b - width_result)); + elsif (((width_a + width_b) = width_result) and (width_result >= width_saturate_sign)) then + saturation_value:= (int_width_a + int_width_b - width_saturate_sign); + elsif (width_result >= width_saturate_sign) then + saturation_value := (int_width_a + int_width_b - width_saturate_sign + (width_result - width_saturate_sign) + (width_saturate_sign - width_a - width_b)); + end if; + elsif (chainout_saturation /= "NO") then + if ((width_result >= int_width_result) and (width_result > width_saturate_sign)) then + saturation_value := width_result - width_saturate_sign; + elsif (width_result > width_saturate_sign) then + saturation_value := width_result + int_mult_diff_bit - width_saturate_sign; + end if; + else + saturation_value:= 2; + end if; + return saturation_value; + end resolve_saturation_position; + + constant saturation_position : natural := resolve_saturation_position; + + function resolve_chainout_saturation_position return integer is + variable saturation_value :integer := 0; + begin + if (chainout_saturation /= "NO") then + if ((width_result >= int_width_result) and (width_result > width_saturate_sign)) then + saturation_value := width_result - width_saturate_sign; + elsif (width_result > width_saturate_sign) then + saturation_value := width_result + int_mult_diff_bit - width_saturate_sign; + end if; + else + saturation_value := 2; + end if; + + if (saturation_value < 0) then + saturation_value:= 2; + elsif (saturation_value > int_width_result) then + saturation_value:= (int_width_a + int_width_b - width_saturate_sign); + end if; + return saturation_value; + end resolve_chainout_saturation_position; + + constant chainout_saturation_position : natural := resolve_chainout_saturation_position; + + function resolve_round_position return integer is + variable round_value :integer := 2; + begin + if (output_rounding /= "NO" or output_saturate_type = "SYMMETRIC") then + if (input_source_b0 = "LOOPBACK") then + round_value := 18; + elsif (((width_a + width_b )> width_result) and (width_msb < width_result)) then + round_value := (int_width_a + int_width_b - width_msb - (width_a + width_b - width_result)); + elsif (((width_a + width_b) = width_result) and (width_msb < width_result)) then + round_value:= (int_width_a + int_width_b - width_msb); + elsif (width_msb < width_result) then + round_value := (int_width_a + int_width_b - width_msb + (width_result - width_a - width_b)); + end if; + else + round_value := 2; + end if; + + if (output_rounding /= "NO" or output_saturate_type = "SYMMETRIC") then + if (round_value < 0) then + round_value := 2; + elsif (round_value > int_width_result) then + round_value := int_width_result - width_msb; + end if; + end if; + return round_value; + end resolve_round_position; + + constant round_position : natural := resolve_round_position; + + function resolve_chainout_round_position return integer is + variable round_value :integer := 2; + begin + if (chainout_rounding /= "NO" or output_saturate_type = "SYMMETRIC") then + if ((width_result >= int_width_result) and (width_msb < width_result)) then + round_value := width_result - width_msb; + elsif (width_msb < width_result) then + round_value := width_result + int_mult_diff_bit - width_msb; + end if; + else + round_value := 2; + end if; + + if (chainout_rounding /= "NO" or output_saturate_type = "SYMMETRIC") then + if (round_value < 0) then + round_value := 2; + elsif (round_value > int_width_result) then + round_value := int_width_result - width_msb; + end if; + end if; + return round_value; + end resolve_chainout_round_position; + + constant chainout_round_position : natural := resolve_chainout_round_position; + + function resolve_chainout_input_a return integer is + variable input_a_value :integer := 0; + begin + if (chainout_adder = "YES") then + if (width_a < 18) then + input_a_value := 18 - width_a; + else + input_a_value := 1; + end if; + end if; + return input_a_value; + end resolve_chainout_input_a; + + constant chainout_input_a : natural := resolve_chainout_input_a; + + function resolve_chainout_input_b return integer is + variable input_b_value :integer := 0; + begin + if (chainout_adder = "YES") then + if (width_b < 18) then + input_b_value := 18 - width_b; + else + input_b_value := 1; + end if; + end if; + return input_b_value; + end resolve_chainout_input_b; + + constant chainout_input_b : natural := resolve_chainout_input_b; + + function resolve_accum_width return integer is + variable accum_value :integer := 0; + begin + if((int_width_a + int_width_b) < 44) then + accum_value := 44; + else + accum_value := int_width_a + int_width_b; + end if; + return accum_value; + end resolve_accum_width; + + constant accum_width : natural := resolve_accum_width; + + function resolve_loopback_width return integer is + variable loopback_value :integer := 0; + begin + loopback_value := 17; + return loopback_value; + end resolve_loopback_width; + + constant loopback_width : natural := resolve_loopback_width; + + function resolve_lsb_position return integer is + variable lsb_position_value :integer := 0; + begin + lsb_position_value := 36 - width_a - width_b; + + if(lsb_position_value < 0) then + lsb_position_value := 0; + end if; + return lsb_position_value; + end resolve_lsb_position; + + constant lsb_position : natural := resolve_lsb_position; + + function resolve_extra_sign_bit_width return integer is + variable extra_sign_bit_width_value :integer :=0; + begin + if(port_signa = "PORT_USED" or port_signb = "PORT_USED") then + extra_sign_bit_width_value := accum_width - width_result - lsb_position; + elsif(representation_a = "UNSIGNED" and representation_b = "UNSIGNED") then + extra_sign_bit_width_value := accum_width - width_result - lsb_position; + else + extra_sign_bit_width_value := accum_width - width_result + 1 - lsb_position; + end if; + + if(extra_sign_bit_width_value < 0) then + extra_sign_bit_width_value := 0; + end if; + + return extra_sign_bit_width_value; + + end resolve_extra_sign_bit_width; + + constant extra_sign_bit_width : natural := resolve_extra_sign_bit_width; + + function resolve_bit_position return integer is + variable bit_position_value :integer := 0; + begin + bit_position_value := accum_width - lsb_position - extra_sign_bit_width - 1; + + return bit_position_value; + end resolve_bit_position; + + constant bit_position : natural := resolve_bit_position; + type pipeline_accum is array (extra_latency downto 0) of std_logic_vector (width_result - 1 downto 0); + + signal mult_a : std_logic_vector ((4 * int_width_a) -1 downto 0) := (others => '0'); + signal mult_b : std_logic_vector ((4 * int_width_b) -1 downto 0) := (others => '0'); + signal mult_res : std_logic_vector ((number_of_multipliers * (int_width_a + int_width_b)) + number_of_multipliers downto 0) := (others => '0'); + signal tmp_mult_a : std_logic_vector ((4 * int_width_a) -1 downto 0) := (others => '0'); + signal tmp_mult_b : std_logic_vector ((4 * int_width_b) -1 downto 0) := (others => '0'); + + signal sign_a_reg : std_logic := '0'; + signal sign_a_pipe : std_logic := '0'; + signal sign_b_reg : std_logic := '0'; + signal sign_b_pipe : std_logic := '0'; + signal addsub_reg1 : std_logic := '0'; + signal addsub_pipe1 : std_logic := '0'; + signal addsub_reg3 : std_logic := '0'; + signal addsub_pipe3 : std_logic := '0'; + + signal mult_clock : std_logic_vector (3 downto 0) := (others => '0'); + signal mult_ena : std_logic_vector (3 downto 0) := (others => '0'); + signal mult_aclr : std_logic_vector (3 downto 0) := (others => '0'); + + signal clock_vector : std_logic_vector (3 downto 0) := (others => '0'); + signal ena_vector : std_logic_vector (3 downto 0) := (others => '0'); + signal aclr_vector : std_logic_vector (3 downto 0) := (others => '0'); + + signal dataa_int : std_logic_vector (4 * int_width_a -1 downto 0) := (others => '0'); + signal dataa_int1 : std_logic_vector (int_width_a -1 downto 0) := (others => '0'); + signal dataa_int2 : std_logic_vector (int_width_a -1 downto 0) := (others => '0'); + signal dataa_int3 : std_logic_vector (int_width_a -1 downto 0) := (others => '0'); + signal dataa_int4 : std_logic_vector (int_width_a -1 downto 0) := (others => '0'); + signal datab_int : std_logic_vector (4 * int_width_b -1 downto 0) := (others => '0'); + signal datab_int1 : std_logic_vector (int_width_b -1 downto 0) := (others => '0'); + signal datab_int2 : std_logic_vector (int_width_b -1 downto 0) := (others => '0'); + signal datab_int3 : std_logic_vector (int_width_b -1 downto 0) := (others => '0'); + signal datab_int4 : std_logic_vector (int_width_b -1 downto 0) := (others => '0'); + signal is_reg : std_logic_vector (3 downto 0) := (others => '0'); + signal temp_mult_zero : std_logic_vector ((int_width_a + int_width_b) -1 downto 0) := (others => '0'); + + signal head_result : natural := 0; + signal head_result_siii : natural := 0; + + signal head_overflow : natural := 0; + + signal mult01_round_wire : std_logic := '0'; + signal mult01_saturate_wire : std_logic := '0'; + signal mult23_round_wire : std_logic := '0'; + signal mult23_saturate_wire : std_logic := '0'; + signal mult_is_saturated : std_logic_vector ((number_of_multipliers - 1) downto 0) := (others => '0'); + signal mult_is_saturated_pipe : std_logic_vector ((number_of_multipliers - 1) downto 0) := (others => '0'); + + signal sourcea_wire : std_logic_vector (3 downto 0) := (others => '0'); + signal sourceb_wire : std_logic_vector (3 downto 0) := (others => '0'); + + + signal addnsub1_round_wire : std_logic := '0'; + signal addnsub1_round_pipe_wire : std_logic := '0'; + signal addnsub3_round_wire : std_logic := '0'; + signal addnsub3_round_pipe_wire : std_logic := '0'; + + signal outround_reg : std_logic := '0'; + signal outround_pipe : std_logic := '0'; + signal chainout_round_reg : std_logic := '0'; + signal chainout_round_pipe : std_logic := '0'; + signal chainout_round_out_reg : std_logic := '0'; + signal outsat_reg : std_logic := '0'; + signal outsat_pipe : std_logic := '0'; + signal chainout_sat_reg : std_logic := '0'; + signal chainout_sat_pipe : std_logic := '0'; + signal chainout_sat_out : std_logic := '0'; + signal scanouta_reg : std_logic_vector (width_a - 1 downto 0) := (others => '0'); + signal zerochainout_reg : std_logic := '0'; + signal rotate_reg : std_logic := '0'; + signal rotate_pipe : std_logic := '0'; + signal rotate_out : std_logic := '0'; + signal shiftr_reg : std_logic := '0'; + signal shiftr_pipe : std_logic := '0'; + signal shiftr_out : std_logic := '0'; + signal zeroloopback_reg : std_logic := '0'; + signal zeroloopback_pipe : std_logic := '0'; + signal zeroloopback_out : std_logic := '0'; + signal accumsload_reg : std_logic := '0'; + signal accumsload_pipe : std_logic := '0'; + signal acc_feedback : std_logic_vector (int_width_result + int_width_a + int_width_b downto 0) := (others => '0'); + signal loopback_wire : std_logic_vector (int_width_result downto 0) := (others => '0'); + signal shift_rot_result : std_logic_vector ((int_width_result/2) - 1 downto 0) := (others => '0'); + signal chainout_output : std_logic_vector (int_width_result downto 0) := (others => '0'); + signal output_result : std_logic_vector (int_width_result + int_width_a + int_width_b downto 0) := (others => '0'); + signal overflow_int : std_logic := '0'; + signal chainout_overflow_int : std_logic := '0'; + signal adder1_reg : std_logic_vector (int_width_result + int_width_a + int_width_b downto 0) := (others => '0'); + signal adder3_reg : std_logic_vector (int_width_result + int_width_a + int_width_b downto 0) := (others => '0'); + signal chainout_sat_block_res_wire : std_logic_vector (int_width_result downto 0) := (others => '0'); + signal acc_feedback_temp : std_logic_vector (accum_width downto 0) := (others => '0'); + signal accum_res : std_logic_vector (accum_width downto 0) := (others => '0'); + signal feedback : std_logic_vector (loopback_width downto 0) := (others => '0'); + signal unsigned_sub1_overflow_reg : std_logic := '0'; + signal unsigned_sub3_overflow_reg : std_logic := '0'; + signal unsigned_sub1_overflow_mult_reg : std_logic := '0'; + signal unsigned_sub3_overflow_mult_reg : std_logic := '0'; + + constant stratixii_block : boolean := FEATURE_FAMILY_BASE_STRATIXII(intended_device_family) or (FEATURE_FAMILY_STRATIXIII(intended_device_family) and (dedicated_multiplier_circuitry = "NO")); + constant stratixiii_block : boolean := FEATURE_FAMILY_STRATIXIII(intended_device_family) and (dedicated_multiplier_circuitry /= "NO"); + constant stratixv_block : boolean := FEATURE_FAMILY_STRATIXV(intended_device_family); + constant altera_mult_add_block : boolean := FEATURE_FAMILY_HAS_ALTERA_MULT_ADD_FLOW(intended_device_family); + constant altmult_add_eol_block : boolean := FEATURE_FAMILY_IS_ALTMULT_ADD_EOL(intended_device_family); + + -- ------------------------------------------------------------------- + -- This function takes in a string that describes the clock name + -- and returns the correct number that corresponds to that particular + -- clock signal + -- ------------------------------------------------------------------- + function resolve_clock (ARG : string) return integer is + variable clock_num:integer := 0; + begin + if (ARG = "CLOCK0") then + clock_num := 0; + elsif ARG = "CLOCK1" then + clock_num := 1; + elsif ARG = "CLOCK2" then + clock_num := 2; + elsif ARG = "CLOCK3" then + clock_num := 3; + end if; + + return clock_num; + end resolve_clock; + + + -- ------------------------------------------------------------------- + -- This function takes in a string that describes the clear name + -- and returns the correct number that corresponds to that particular + -- clear signal + -- ------------------------------------------------------------------- + function resolve_aclr (ARG : string) return integer is + variable aclr_num:integer := 0; + begin + if (ARG = "ACLR0") then + aclr_num := 0; + elsif ARG = "ACLR1" then + aclr_num := 1; + elsif ARG = "ACLR2" then + aclr_num := 2; + elsif ARG = "ACLR3" then + aclr_num := 3; + end if; + + return aclr_num; + end resolve_aclr; + + + -- ------------------------------------------------------------------- + -- This function takes in a integer that describes the particular + -- clock signal returns the correct string + -- ------------------------------------------------------------------- + function check_clock (arg: integer) return string is + variable ret_val:string (1 to 6); + begin + if (arg = 0) then + ret_val := multiplier_register0 (1 to 6); + elsif arg =1 then + ret_val := multiplier_register1 (1 to 6); + elsif arg=2 then + ret_val := multiplier_register2 (1 to 6); + elsif arg=3 then + ret_val := multiplier_register3 (1 to 6); + else + ret_val := "CLOCK0"; + end if; + + return ret_val; + end check_clock; + + + begin + + process(mult_b) + begin + if (altera_mult_add_block) then + scanoutb <= (others => 'Z'); + elsif (chainout_adder = "YES" and (width_result > width_a + width_b + 8)) then + scanoutb <= mult_b((number_of_multipliers * int_width_b) - 1 - (int_width_b - width_b) downto ((number_of_multipliers-1) * int_width_b)); + else + scanoutb <= mult_b ((number_of_multipliers * int_width_b) -1 downto ((number_of_multipliers -1 ) * int_width_b) + int_width_b - width_b); + end if; + end process; + + clock_vector (0) <= clock0; + clock_vector (1) <= clock1; + clock_vector (2) <= clock2; + clock_vector (3) <= clock3; + + ena_vector (0) <= ena0; + ena_vector (1) <= ena1; + ena_vector (2) <= ena2; + ena_vector (3) <= ena3; + + aclr_vector (0) <= aclr0; + aclr_vector (1) <= aclr1; + aclr_vector (2) <= aclr2; + aclr_vector (3) <= aclr3; + + sourcea_wire ( number_of_multipliers - 1 downto 0) <= sourcea (number_of_multipliers -1 downto 0); + sourceb_wire ( number_of_multipliers - 1 downto 0) <= sourceb (number_of_multipliers - 1 downto 0); + + tmp_mult_a <= mult_a; + tmp_mult_b <= mult_b; + + -- Parameter Checking + process + begin + + -- Legality check, family from Night Fury and moving forwards is officially EOL + if (altmult_add_eol_block) then + assert false + report "ALTMULT_ADD is EOL for "& intended_device_family &" device family" + severity failure; + end if; + + -- Legality check, block new family from running pre_layout simulation using altera_mf (family with altera_mult_add flow) + if (altera_mult_add_block) then + if(accumulator /= "NO") then + assert false + report "Accumulator mode is not supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (port_addnsub1 /= "PORT_UNUSED" or port_addnsub3 /= "PORT_UNUSED") then + assert false + report "Dynamic adder is not supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (chainout_adder /= "NO") then + assert false + report "Chain adder is not supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (systolic_delay1 /= "UNREGISTERED" or systolic_delay3 /= "UNREGISTERED") then + assert false + report "Systolic mode is not supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (input_source_a0 /= "DATAA" or input_source_a1 /= "DATAA" or input_source_a2 /= "DATAA" or input_source_a3 /= "DATAA") then + assert false + report "The INPUT_SOURCE_A parameter is set to an unsupported value. Only DATAA input is supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (input_source_b0 /= "DATAB" or input_source_b1 /= "DATAB" or input_source_b2 /= "DATAB" or input_source_b3 /= "DATAB") then + assert false + report "The INPUT_SOURCE_B parameter is set to an unsupported value. Only DATAB input is supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (preadder_mode /= "SIMPLE") then + assert false + report "The PREADDER_MODE parameter is set to an unsupported value. Only SIMPLE mode is supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (output_rounding /= "NO" or chainout_rounding /= "NO" or + adder1_rounding /= "NO" or adder3_rounding /= "NO" or + multiplier01_rounding /= "NO" or multiplier23_rounding /= "NO") then + assert false + report "Rounding is not supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (output_saturation /= "NO" or chainout_saturation /= "NO" or + port_mult0_is_saturated /= "UNUSED" or port_mult1_is_saturated /= "UNUSED" or port_mult2_is_saturated /= "UNUSED" or port_mult3_is_saturated /= "UNUSED" or + multiplier01_saturation /= "NO" or multiplier23_saturation /= "NO" or + port_output_is_overflow /= "PORT_UNUSED") then + assert false + report "Saturation is not supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (shift_mode /= "NO") then + assert false + report "Shift is not supported in altera_mf for "& intended_device_family &" device family" + severity failure; + end if; + if (signed_pipeline_register_a /= "UNREGISTERED" or signed_pipeline_register_b /= "UNREGISTERED" or + addnsub_multiplier_pipeline_register1 /= "UNREGISTERED" or addnsub_multiplier_pipeline_register3 /= "UNREGISTERED" or + accum_sload_pipeline_register /= "UNREGISTERED") then + assert false + report "Pipeline register is not supported in altera_mf for "& intended_device_family &" device family" + severity warning; + end if; + end if; + + -- Checking for invalid parameters, in case Wizard is bypassed (hand-modified). + if (number_of_multipliers > 4) then + assert false + report "Altmult_add does not currently support NUMBER_OF_MULTIPLIERS > 4" + severity error; + end if; + + if (number_of_multipliers <= 0) then + assert false + report "NUMBER_OF_MULTIPLIERS must be greater than 0." + severity error; + end if; + + if (width_a <= 0) then + assert false + report "Error: width_a must be greater than 0." + severity error; + end if; + + if (width_b <= 0) then + assert false + report "Error: width_b must be greater than 0." + severity error; + end if; + + if (width_result <= 0) then + assert false + report "Error: width_result must be greater than 0." + severity error; + end if; + + if ((dedicated_multiplier_circuitry /= "AUTO") and + (dedicated_multiplier_circuitry /= "YES") and + (dedicated_multiplier_circuitry /= "NO")) then + assert false + report "Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_a0 /= "DATAA") and + (input_source_a0 /= "SCANA") and + (input_source_a0 /= "VARIABLE")) then + assert false + report "Error: The INPUT_SOURCE_A0 parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_a1 /= "DATAA") and + (input_source_a1 /= "SCANA") and + (input_source_a1 /= "VARIABLE")) then + assert false + report "Error: The INPUT_SOURCE_A1 parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_a2 /= "DATAA") and + (input_source_a2 /= "SCANA") and + (input_source_a2 /= "VARIABLE")) then + assert false + report "Error: The INPUT_SOURCE_A2 parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_a3 /= "DATAA") and + (input_source_a3 /= "SCANA") and + (input_source_a3 /= "VARIABLE")) then + assert false + report "Error: The INPUT_SOURCE_A3 parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_b0 /= "DATAB") and + (input_source_b0 /= "SCANB") and + (input_source_b0 /= "VARIABLE") and + (input_source_b0 /= "LOOPBACK")) then + assert false + report "Error: The INPUT_SOURCE_B0 parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_b1 /= "DATAB") and + (input_source_b1 /= "SCANB") and + (input_source_b1 /= "VARIABLE")) then + assert false + report "Error: The INPUT_SOURCE_B1 parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_b2 /= "DATAB") and + (input_source_b2 /= "SCANB") and + (input_source_b2 /= "VARIABLE")) then + assert false + report "Error: The INPUT_SOURCE_B2 parameter is set to an illegal value." + severity error; + end if; + + if ((input_source_b3 /= "DATAB") and + (input_source_b3 /= "SCANB") and + (input_source_b3 /= "VARIABLE")) then + assert false + report "Error: The INPUT_SOURCE_B3 parameter is set to an illegal value." + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_a0 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_a1 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_a2 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_a3 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_b0 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_b1 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_b2 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and (not FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (input_source_b3 = "VARIABLE")) then + assert false + report "Error: Input source as VARIABLE is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and + ((multiplier01_rounding = "YES") or (multiplier01_rounding = "VARIABLE") or + (multiplier23_rounding = "YES") or (multiplier23_rounding = "VARIABLE"))) then + assert false + report "Error: Rounding for multiplier is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and + ((multiplier01_saturation = "YES") or (multiplier01_saturation = "VARIABLE") or + (multiplier23_saturation = "YES") or (multiplier23_saturation = "VARIABLE"))) then + assert false + report "Error: Saturation for multiplier is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_BASE_STRATIXII(intended_device_family)) and + ((adder1_rounding = "YES") or (adder1_rounding = "VARIABLE") or + (adder3_rounding = "YES") or (adder3_rounding = "VARIABLE"))) then + assert false + report "Error: Rounding for adder is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((multiplier01_saturation = "NO") and (multiplier23_saturation = "NO") + and (multiplier01_rounding = "NO") and (multiplier23_rounding = "NO") and + (output_rounding = "NO") and (output_saturation = "NO") and (shift_mode ="NO") and (chainout_adder = "NO")) then + if (int_width_result /= width_result) then + assert false + report "Error: Internal parameter setting of int_width_result is illegal" + severity error; + end if; + + if (int_mult_diff_bit /= 0) then + assert false + report "Error: Internal parameter setting of int_mult_diff_bit is illegal" + severity error; + end if; + else + if (((width_a < 18) and (int_width_a /= 18)) or + ((width_a >= 18) and (int_width_a /= width_a))) then + assert false + report "Error: Internal parameter setting of int_width_a is illegal" + severity error; + end if; + + if (((width_b < 18) and (int_width_b /= 18)) or + ((width_b >= 18) and (int_width_b /= width_b))) then + assert false + report "Error: Internal parameter setting of int_width_b is illegal" + severity error; + end if; + + if ((chainout_adder = "NO") and (shift_mode = "NO")) then + if ((int_width_result > (int_width_a + int_width_b))) then + if (int_width_result /= (width_result + width_result - int_width_a - int_width_b)) then + assert false + report "Error: Internal parameter setting of int_width_result is illegal" + severity error; + end if; + elsif ((int_width_result /= (int_width_a + int_width_b))) then + assert false + report "Error: Internal parameter setting of int_width_result is illegal" + severity error; + end if; + + if ((int_mult_diff_bit /= (int_width_a - width_a + int_width_b - width_b))) then + assert false + report "Error: Internal parameter setting of int_mult_diff_bit is illegal" + severity error; + end if; + end if; + end if; + + -- Stratix III parameter checking + if ((not FEATURE_FAMILY_STRATIXIII(intended_device_family)) and ((output_rounding = "YES") or + (output_rounding = "VARIABLE") or (chainout_rounding = "YES") or (chainout_rounding = "VARIABLE"))) then + assert false + report "Error: Output rounding and/or Chainout rounding are not supported for "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_STRATIXIII(intended_device_family)) and ((output_saturation = "YES") or + (output_saturation = "VARIABLE") or (chainout_saturation = "YES") or (chainout_saturation = "VARIABLE"))) then + assert false + report "Error: Output saturation and/or Chainout saturation are not supported for "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_STRATIXIII(intended_device_family)) and (input_source_b0 = "LOOPBACK")) then + assert false + report "Error: Loopback mode is not supported for "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_STRATIXIII(intended_device_family)) and (chainout_adder = "YES")) then + assert false + report "Error: Chainout mode is not supported for "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_STRATIXIII(intended_device_family)) and (shift_mode /= "NO")) then + assert false + report "Error: shift and rotate modes are not supported for "& intended_device_family &" device family" + severity error; + end if; + + if ((not FEATURE_FAMILY_STRATIXIII(intended_device_family)) and (accumulator = "YES")) then + assert false + report "Error: Accumulator mode is not supported for "& intended_device_family &" device family" + severity error; + end if; + + if ((output_rounding /= "YES") and (output_rounding /= "NO") and (output_rounding /= "VARIABLE")) then + assert false + report "Error: The OUTPUT_ROUNDING parameter is set to an invalid value" + severity error; + end if; + + if ((chainout_rounding /= "YES") and (chainout_rounding /= "NO") and (chainout_rounding /= "VARIABLE")) then + assert false + report "Error: The CHAINOUT_ROUNDING parameter is set to an invalid value" + severity error; + end if; + + if ((output_saturation /= "YES") and (output_saturation /= "NO") and (output_saturation /= "VARIABLE")) then + assert false + report "Error: The OUTPUT_SATURATION parameter is set to an invalid value" + severity error; + end if; + + if ((chainout_saturation /= "YES") and (chainout_saturation /= "NO") and (chainout_saturation /= "VARIABLE")) then + assert false + report "Error: The CHAINOUT_SATURATION parameter is set to an invalid value" + severity error; + end if; + + if ((output_rounding /= "NO") and ((output_round_type /= "NEAREST_INTEGER") and (output_round_type /= "NEAREST_EVEN"))) then + assert false + report "Error: The OUTPUT_ROUND_TYPE parameter is set to an invalid value" + severity error; + end if; + + if ((output_saturation /= "NO") and ((output_saturate_type /= "ASYMMETRIC") and (output_saturate_type /= "SYMMETRIC"))) then + assert false + report "Error: The OUTPUT_SATURATE_TYPE parameter is set to an invalid value" + severity error; + end if; + + if ((shift_mode /= "NO") and (shift_mode /= "LEFT") and (shift_mode /= "RIGHT") and (shift_mode /= "ROTATION") and + (shift_mode /= "VARIABLE")) then + assert false + report "Error: The SHIFT_MODE parameter is set to an inavlid value" + severity error; + end if; + + if ((accumulator = "YES") and (accum_direction /= "ADD") and (accum_direction /= "SUB")) then + assert false + report "Error: The ACCUM_DIRECTION parameter is set to an invalid value" + severity error; + end if; + + if (FEATURE_FAMILY_STRATIXIII(intended_device_family)) then + if ((output_rounding = "YES") and (accumulator = "YES")) then + assert false + report "Error: In accumulator mode, the OUTPUT_ROUNDING parameter has to be set to VARIABLE if used" + severity error; + end if; + + if ((chainout_adder = "YES") and (output_rounding /= "NO")) then + assert false + report "Error: In chainout mode, output rounding cannot be turned on" + severity error; + end if; + end if; + + + wait; + + end process; + + -- ---------------------------------------------------------------- + -- This process updates the dataa_int everytime dataa changes value + -- ---------------------------------------------------------------- + IFG01: if (number_of_multipliers >= 1) generate + process (dataa, signa, sign_a_reg, sign_a_pipe) + variable dataa1_cnt : integer := 0; + variable dataa_word_temp : std_logic_vector (int_width_a -1 downto 0) := (others=>'0'); + variable asign : boolean; + variable is_rep_a_sign : boolean; + variable is_rep_a_pipe_sign : boolean; + begin + is_rep_a_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_reg = '1'))) or ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_a_pipe_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_pipe = '1'))) or ((port_signa = "PORT_USED") and (sign_a_pipe = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + -- Use sign_a_reg instead of sign_a_pipe when signed_pipeline_register_a is unregistered + -- to set the asign flag + if (signed_pipeline_register_a = "UNREGISTERED") then + if (is_rep_a_sign) then + asign := true; + else + asign := false; + end if; + else + if (is_rep_a_pipe_sign) then + asign := true; + else + asign := false; + end if; + end if; + + dataa_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_a < 18)) then + if (asign = true) then -- signed number, extend MSB with sign bit + for dataa1_cnt in 1 to (chainout_input_a) loop + dataa_word_temp(int_width_a - dataa1_cnt) := dataa(width_a - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for dataa1_cnt in 1 to (chainout_input_a) loop + dataa_word_temp(int_width_a - dataa1_cnt) := '0'; + end loop; + end if; + + for dataa1_cnt in 0 to (width_a - 1) loop + dataa_word_temp(dataa1_cnt) := dataa(dataa1_cnt); + end loop; + + dataa_int1 <= dataa_word_temp(int_width_a -1 downto 0); + else + dataa_int1((int_width_a) - 1 downto ((int_width_a) - width_a)) <= dataa(width_a - 1 downto 0); + end if; + else + dataa_int1((int_width_a) - 1 downto ((int_width_a) - width_a)) <= dataa(width_a - 1 downto 0); + end if; + end process; + end generate IFG01; + + IFG02: if (number_of_multipliers >= 2) generate + process (dataa, signa, sign_a_reg, sign_a_pipe) + variable dataa2_cnt : integer := 0; + variable dataa2_word_temp : std_logic_vector (int_width_a -1 downto 0) := (others=>'0'); + variable asign : boolean; + variable is_rep_a_sign : boolean; + variable is_rep_a_pipe_sign : boolean; + begin + is_rep_a_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_reg = '1'))) or ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_a_pipe_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_pipe = '1'))) or ((port_signa = "PORT_USED") and (sign_a_pipe = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + -- Use sign_a_reg instead of sign_a_pipe when signed_pipeline_register_a is unregistered + -- to set the asign flag + if (signed_pipeline_register_a = "UNREGISTERED") then + if (is_rep_a_sign) then + asign := true; + else + asign := false; + end if; + else + if (is_rep_a_pipe_sign) then + asign := true; + else + asign := false; + end if; + end if; + + dataa2_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_a < 18)) then + if (asign = true) then -- signed number, extend MSB with sign bit + for dataa2_cnt in 1 to (chainout_input_a) loop + dataa2_word_temp(int_width_a - dataa2_cnt) := dataa((2*width_a) - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for dataa2_cnt in 1 to (chainout_input_a) loop + dataa2_word_temp(int_width_a - dataa2_cnt) := '0'; + end loop; + end if; + + for dataa2_cnt in 0 to (width_a - 1) loop + dataa2_word_temp(dataa2_cnt) := dataa(width_a + dataa2_cnt); + end loop; + + dataa_int2 <= dataa2_word_temp(int_width_a -1 downto 0); + + else + dataa_int2((int_width_a) - 1 downto ((int_width_a) - width_a)) <= dataa((2*width_a) - 1 downto width_a); + end if; + else + dataa_int2((int_width_a) - 1 downto ((int_width_a) - width_a)) <= dataa((2 * width_a) - 1 downto width_a); + end if; + end process; + end generate IFG02; + + IFG03: if (number_of_multipliers >= 3) generate + process (dataa, signa, sign_a_reg, sign_a_pipe) + variable dataa3_cnt : integer := 0; + variable dataa3_word_temp : std_logic_vector (int_width_a -1 downto 0) := (others=>'0'); + variable asign : boolean; + variable is_rep_a_sign : boolean; + variable is_rep_a_pipe_sign : boolean; + begin + is_rep_a_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_reg = '1'))) or ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_a_pipe_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_pipe = '1'))) or ((port_signa = "PORT_USED") and (sign_a_pipe = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + -- Use sign_a_reg instead of sign_a_pipe when signed_pipeline_register_a is unregistered + -- to set the asign flag + if (signed_pipeline_register_a = "UNREGISTERED") then + if (is_rep_a_sign) then + asign := true; + else + asign := false; + end if; + else + if (is_rep_a_pipe_sign) then + asign := true; + else + asign := false; + end if; + end if; + + dataa3_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_a < 18)) then + if (asign = true) then -- signed number, extend MSB with sign bit + for dataa3_cnt in 1 to (chainout_input_a) loop + dataa3_word_temp(int_width_a - dataa3_cnt) := dataa((3*width_a) - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for dataa3_cnt in 1 to (chainout_input_a) loop + dataa3_word_temp(int_width_a - dataa3_cnt) := '0'; + end loop; + end if; + + for dataa3_cnt in 0 to (width_a - 1) loop + dataa3_word_temp (dataa3_cnt) := dataa((2*width_a) + dataa3_cnt); + end loop; + + dataa_int3 <= dataa3_word_temp(int_width_a -1 downto 0); + + else + dataa_int3((int_width_a) - 1 downto ((int_width_a) - width_a)) <= dataa((3*width_a) - 1 downto (2*width_a)); + end if; + else + dataa_int3((int_width_a) - 1 downto (int_width_a) - width_a) <= dataa((3 * width_a) - 1 downto (2 * width_a)); + end if; + end process; + end generate IFG03; + + IFG04: if (number_of_multipliers >= 4) generate + process (dataa, signa, sign_a_reg, sign_a_pipe) + variable dataa4_cnt : integer := 0; + variable dataa4_word_temp : std_logic_vector (int_width_a -1 downto 0) := (others=>'0'); + variable asign : boolean; + variable is_rep_a_sign : boolean; + variable is_rep_a_pipe_sign : boolean; + begin + is_rep_a_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_reg = '1'))) or ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_a_pipe_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_pipe = '1'))) or ((port_signa = "PORT_USED") and (sign_a_pipe = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + -- Use sign_a_reg instead of sign_a_pipe when signed_pipeline_register_a is unregistered + -- to set the asign flag + if (signed_pipeline_register_a = "UNREGISTERED") then + if (is_rep_a_sign) then + asign := true; + else + asign := false; + end if; + else + if (is_rep_a_pipe_sign) then + asign := true; + else + asign := false; + end if; + end if; + + dataa4_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_a < 18)) then + if (asign = true) then -- signed number, extend MSB with sign bit + for dataa4_cnt in 1 to (chainout_input_a) loop + dataa4_word_temp(int_width_a - dataa4_cnt) := dataa((4*width_a) - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for dataa4_cnt in 1 to (chainout_input_a) loop + dataa4_word_temp(int_width_a - dataa4_cnt) := '0'; + end loop; + end if; + + for dataa4_cnt in 0 to (width_a - 1) loop + dataa4_word_temp(dataa4_cnt) := dataa((3*width_a) + dataa4_cnt); + end loop; + + dataa_int4 <= dataa4_word_temp(int_width_a -1 downto 0); + + else + dataa_int4((int_width_a) - 1 downto ((int_width_a) - width_a)) <= dataa((4*width_a) - 1 downto (3*width_a)); + end if; + else + dataa_int4((int_width_a) - 1 downto (int_width_a) - width_a) <= dataa((4 * width_a) - 1 downto (3 * width_a)); + end if; + end process; + end generate IFG04; + + -- ---------------------------------------------------------------- + -- This process updates the datab_int everytime datab changes value + -- ---------------------------------------------------------------- + + IFG05: if (number_of_multipliers >= 1) generate + process (datab, signb, sign_b_reg, sign_b_pipe) + variable datab1_cnt : integer := 0; + variable datab_word_temp : std_logic_vector(int_width_b -1 downto 0) := (others => '0'); + variable bsign : boolean; + variable is_rep_b_sign : boolean; + variable is_rep_b_pipe_sign : boolean; + begin + is_rep_b_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_reg = '1'))) or ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_rep_b_pipe_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_pipe = '1'))) or ((port_signb = "PORT_USED") and (sign_b_pipe = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + -- Use sign_b_reg instead of sign_b_pipe when + -- signed_pipeline_register_b is unregistered + -- to set the bsign flag + if (signed_pipeline_register_b = "UNREGISTERED") then + if (is_rep_b_sign) then + bsign := true; + else + bsign := false; + end if; + else + if (is_rep_b_pipe_sign) then + bsign := true; + else + bsign := false; + end if; + end if; + + datab_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_b < 18))then + if (bsign = true) then -- signed number, extend MSB with sign bit + for datab1_cnt in 1 to (chainout_input_b) loop + datab_word_temp(int_width_b - datab1_cnt) := datab(width_b - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for datab1_cnt in 1 to (chainout_input_b) loop + datab_word_temp(int_width_b - datab1_cnt) := '0'; + end loop; + end if; + + for datab1_cnt in 0 to (width_b - 1) loop + datab_word_temp(datab1_cnt) := datab(datab1_cnt); + end loop; + + datab_int1 <= datab_word_temp(int_width_b - 1 downto 0); + else + datab_int1((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab(width_b - 1 downto 0); + end if; + else + datab_int1((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab(width_b - 1 downto 0); + end if; + end process; + end generate IFG05; + + IFG06: if (number_of_multipliers >= 2) generate + process (datab, signb, sign_b_reg, sign_b_pipe) + variable datab2_cnt : integer := 0; + variable datab2_word_temp : std_logic_vector(int_width_b -1 downto 0) := (others => '0'); + variable bsign : boolean; + variable is_rep_b_sign : boolean; + variable is_rep_b_pipe_sign : boolean; + begin + is_rep_b_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_reg = '1'))) or ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_rep_b_pipe_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_pipe = '1'))) or ((port_signb = "PORT_USED") and (sign_b_pipe = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + -- Use sign_b_reg instead of sign_b_pipe when + -- signed_pipeline_register_b is unregistered + -- to set the bsign flag + if (signed_pipeline_register_b = "UNREGISTERED") then + if (is_rep_b_sign) then + bsign := true; + else + bsign := false; + end if; + else + if (is_rep_b_pipe_sign) then + bsign := true; + else + bsign := false; + end if; + end if; + + datab2_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_b < 18)) then + if (bsign = true) then -- signed number, extend MSB with sign bit + for datab2_cnt in 1 to (chainout_input_b) loop + datab2_word_temp(int_width_b - datab2_cnt) := datab((2*width_b) - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for datab2_cnt in 1 to (chainout_input_b) loop + datab2_word_temp(int_width_b - datab2_cnt) := '0'; + end loop; + end if; + + for datab2_cnt in 0 to (width_b - 1) loop + datab2_word_temp(datab2_cnt) := datab(width_b + datab2_cnt); + end loop; + + datab_int2 <= datab2_word_temp(int_width_b -1 downto 0); + else + datab_int2((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab((2*width_b) - 1 downto width_b); + end if; + else + datab_int2((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab((2 * width_b) - 1 downto width_b); + end if; + end process; + end generate IFG06; + + IFG07: if (number_of_multipliers >= 3) generate + process (datab, signb, sign_b_reg, sign_b_pipe) + variable datab3_cnt : integer := 0; + variable datab3_word_temp : std_logic_vector(int_width_b -1 downto 0) := (others => '0'); + variable bsign : boolean; + variable is_rep_b_sign : boolean; + variable is_rep_b_pipe_sign : boolean; + begin + is_rep_b_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_reg = '1'))) or ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_rep_b_pipe_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_pipe = '1'))) or ((port_signb = "PORT_USED") and (sign_b_pipe = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + -- Use sign_b_reg instead of sign_b_pipe when + -- signed_pipeline_register_b is unregistered + -- to set the bsign flag + if (signed_pipeline_register_b = "UNREGISTERED") then + if (is_rep_b_sign) then + bsign := true; + else + bsign := false; + end if; + else + if (is_rep_b_pipe_sign) then + bsign := true; + else + bsign := false; + end if; + end if; + + datab3_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_b < 18)) then + if (bsign = true) then -- signed number, extend MSB with sign bit + for datab3_cnt in 1 to (chainout_input_b) loop + datab3_word_temp(int_width_b - datab3_cnt) := datab((3*width_b) - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for datab3_cnt in 1 to (chainout_input_b) loop + datab3_word_temp(int_width_b - datab3_cnt) := '0'; + end loop; + end if; + + for datab3_cnt in 0 to (width_b - 1) loop + datab3_word_temp(datab3_cnt) := datab((2*width_b) + datab3_cnt); + end loop; + + datab_int3 <= datab3_word_temp(int_width_b - 1 downto 0); + else + datab_int3((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab((3*width_b) - 1 downto (2*width_b)); + end if; + else + datab_int3((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab((3 * width_b) - 1 downto (2 * width_b)); + end if; + end process; + end generate IFG07; + + IFG08: if (number_of_multipliers >= 4) generate + process (datab, signb, sign_b_reg, sign_b_pipe) + variable datab4_cnt : integer := 0; + variable datab4_word_temp : std_logic_vector(int_width_b -1 downto 0) := (others => '0'); + variable bsign : boolean; + variable is_rep_b_sign : boolean; + variable is_rep_b_pipe_sign : boolean; + begin + is_rep_b_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_reg = '1'))) or ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_rep_b_pipe_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_pipe = '1'))) or ((port_signb = "PORT_USED") and (sign_b_pipe = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + -- Use sign_b_reg instead of sign_b_pipe when + -- signed_pipeline_register_b is unregistered + -- to set the bsign flag + if (signed_pipeline_register_b = "UNREGISTERED") then + if (is_rep_b_sign) then + bsign := true; + else + bsign := false; + end if; + else + if (is_rep_b_pipe_sign) then + bsign := true; + else + bsign := false; + end if; + end if; + + datab4_word_temp := (others => '0'); + if ((chainout_adder = "YES") and (stratixiii_block)) then + if ((width_result > width_a + width_b + 8) and (width_b < 18)) then + if (bsign = true) then -- signed number, extend MSB with sign bit + for datab4_cnt in 1 to (chainout_input_b) loop + datab4_word_temp(int_width_b - datab4_cnt) := datab((4*width_b) - 1); + end loop; + else -- unsigned number, extend MSB with "0" + for datab4_cnt in 1 to (chainout_input_b) loop + datab4_word_temp(int_width_b - datab4_cnt) := '0'; + end loop; + end if; + + for datab4_cnt in 0 to (width_b - 1) loop + datab4_word_temp(datab4_cnt) := datab((3*width_b) + datab4_cnt); + end loop; + + datab_int4 <= datab4_word_temp(int_width_b - 1 downto 0); + + else + datab_int4((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab((4*width_b) - 1 downto (3*width_b)); + end if; + else + datab_int4((int_width_b) - 1 downto ((int_width_b) - width_b)) <= datab((4 * width_b) - 1 downto (3 * width_b)); + end if; + end process; + end generate IFG08; + + -- This process updates scanouta depending on which family is being used + process (mult_a, scanouta_reg) + begin + if (altera_mult_add_block) then + scanouta <= (others => 'Z'); + elsif (stratixiii_block) then + scanouta <= scanouta_reg (width_a - 1 downto 0); + else + scanouta <= mult_a ((number_of_multipliers * int_width_a) - 1 downto ((number_of_multipliers -1 ) * int_width_a) + int_width_a - width_a) ; + end if; + end process; + + -- This process updates dataa_int and datab_int + process (dataa_int1, dataa_int2, dataa_int3, dataa_int4, datab_int1, datab_int2, datab_int3, datab_int4) + begin + dataa_int <= dataa_int4 & dataa_int3 & dataa_int2 & dataa_int1; + datab_int <= datab_int4 & datab_int3 & datab_int2 & datab_int1; + end process; + + -- ------------------------------------------------------------------------------------ + -- This process sets up all the clock, clock enable and clear signals for all registers + -- ------------------------------------------------------------------------------------ + -- --------------------------------------- + -- SETTING UP THE CONTROL SIGNAL REGISTERS + -- --------------------------------------- + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addsub_reg1) + -- The signal registered is addnsub1 + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub_multiplier_register1 + -- is unregistered and addnsub1 changes value + -- --------------------------------------------------------------------------------- + + G1: if (addnsub_multiplier_register1 = "UNREGISTERED") generate + addsub_reg1 <= addnsub1; + end generate G1; + + IFG9: if (addnsub_multiplier_register1 = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addnsub1) + begin + if (((addnsub_multiplier_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_reg1 <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addsub_reg1 <= addnsub1; + end if; + end if; + end process; + end generate IFG9; + + IFG10: if (addnsub_multiplier_register1 = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addnsub1) + begin + if (((addnsub_multiplier_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_reg1 <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addsub_reg1 <= addnsub1; + end if; + end if; + end process; + end generate IFG10; + + IFG11: if (addnsub_multiplier_register1 = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addnsub1) + begin + if (((addnsub_multiplier_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_reg1 <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addsub_reg1 <= addnsub1; + end if; + end if; + end process; + end generate IFG11; + + IFG12: if (addnsub_multiplier_register1 = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addnsub1) + begin + if (((addnsub_multiplier_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_reg1 <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addsub_reg1 <= addnsub1; + end if; + end if; + end process; + end generate IFG12; + + -- ---------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addsub_pipe1) + -- The signal registered is addsub_reg1 + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub_multiplier_pipeline_register1 + -- is unregistered and addsub_reg1 changes value + -- ---------------------------------------------------------------------------------- + + G2: if (addnsub_multiplier_pipeline_register1 = "UNREGISTERED") generate + addsub_pipe1 <= addsub_reg1; + end generate G2; + + IFG14: if (addnsub_multiplier_pipeline_register1 = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addsub_reg1) + begin + if (((addnsub_multiplier_pipeline_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe1<= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addsub_pipe1 <= addsub_reg1; + end if; + end if; + end process; + end generate IFG14; + + IFG14a: if (addnsub_multiplier_pipeline_register1 = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addsub_reg1) + begin + if (((addnsub_multiplier_pipeline_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe1<= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addsub_pipe1 <= addsub_reg1; + end if; + end if; + end process; + end generate IFG14a; + + IFG15: if (addnsub_multiplier_pipeline_register1 = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addsub_reg1) + begin + if (((addnsub_multiplier_pipeline_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe1<= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addsub_pipe1 <= addsub_reg1; + end if; + end if; + end process; + end generate IFG15; + + IFG16: if (addnsub_multiplier_pipeline_register1 = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addsub_reg1) + begin + if (((addnsub_multiplier_pipeline_aclr1= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr1= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe1<= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addsub_pipe1 <= addsub_reg1; + end if; + end if; + end process; + end generate IFG16; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addsub_reg3) + -- The signal registered is addsub3 + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub_multiplier_register3 + -- is unregistered and addnsub3 changes value + -- --------------------------------------------------------------------------------- + + G3: if (addnsub_multiplier_register3 = "UNREGISTERED") generate + addsub_reg3 <= addnsub3; + end generate G3; + + IFG17: if (addnsub_multiplier_register3 = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addnsub3) + begin + if (((addnsub_multiplier_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_reg3 <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addsub_reg3 <= addnsub3; + end if; + end if; + end process; + end generate IFG17; + + IFG18: if (addnsub_multiplier_register3 = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addnsub3) + begin + if (((addnsub_multiplier_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_reg3 <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addsub_reg3 <= addnsub3; + end if; + end if; + end process; + end generate IFG18; + + IFG19: if (addnsub_multiplier_register3 = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addnsub3) + begin + if (((addnsub_multiplier_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_reg3 <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addsub_reg3 <= addnsub3; + end if; + end if; + end process; + end generate IFG19; + + IFG20: if (addnsub_multiplier_register3 = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addnsub3) + begin + if (((addnsub_multiplier_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_reg3 <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addsub_reg3 <= addnsub3; + end if; + end if; + end process; + end generate IFG20; + + -- ---------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addsub_pipe3) + -- The signal registered is addsub_reg3 + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub_multiplier_pipeline_register3 + -- is unregistered and addsub_reg3 changes value + -- ---------------------------------------------------------------------------------- + + G4: if (addnsub_multiplier_pipeline_register3 = "UNREGISTERED") generate + addsub_pipe3 <= addsub_reg3; + end generate G4; + + IFG21: if (addnsub_multiplier_pipeline_register3 = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addsub_reg3) + begin + if (((addnsub_multiplier_pipeline_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe3<= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addsub_pipe3 <= addsub_reg3; + end if; + end if; + end process; + end generate IFG21; + + IFG22: if (addnsub_multiplier_pipeline_register3 = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addsub_reg3) + begin + if (((addnsub_multiplier_pipeline_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe3<= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addsub_pipe3 <= addsub_reg3; + end if; + end if; + end process; + end generate IFG22; + + IFG23: if (addnsub_multiplier_pipeline_register3 = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addsub_reg3) + begin + if (((addnsub_multiplier_pipeline_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe3<= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addsub_pipe3 <= addsub_reg3; + end if; + end if; + end process; + end generate IFG23; + + IFG24: if (addnsub_multiplier_pipeline_register3 = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addsub_reg3) + begin + if (((addnsub_multiplier_pipeline_aclr3= "ACLR0") and (aclr0 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR1") and (aclr1 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR2") and (aclr2 = '1')) or + ((addnsub_multiplier_pipeline_aclr3= "ACLR3") and (aclr3 = '1'))) then + addsub_pipe3<= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addsub_pipe3 <= addsub_reg3; + end if; + end if; + end process; + end generate IFG24; + + -- -------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set sign_a_reg) + -- The signal registered is signa + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if signed_register_a + -- is unregistered and signa changes value + -- -------------------------------------------------------------------------------- + + G5: if (signed_register_a = "UNREGISTERED") generate + sign_a_reg <= signa; + end generate G5; + + IFG25: if (signed_register_a = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((signed_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + sign_a_reg <= signa; + end if; + end if; + end process; + end generate IFG25; + + IFG26: if (signed_register_a = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((signed_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + sign_a_reg <= signa; + end if; + end if; + end process; + end generate IFG26; + + IFG27: if (signed_register_a = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((signed_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + sign_a_reg <= signa; + end if; + end if; + end process; + end generate IFG27; + + IFG28: if (signed_register_a = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, signa) + begin + if (((signed_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_reg <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + sign_a_reg <= signa; + end if; + end if; + end process; + end generate IFG28; + + -- -------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set sign_b_reg) + -- The signal registered is signb + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if signed_register_b + -- is unregistered and signb changes value + -- -------------------------------------------------------------------------------- + + G6: if (signed_register_b = "UNREGISTERED") generate + sign_b_reg <= signb; + end generate G6; + + IFG29: if (signed_register_b = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((signed_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + sign_b_reg <= signb; + end if; + end if; + end process; + end generate IFG29; + + IFG30: if (signed_register_b = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((signed_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + sign_b_reg <= signb; + end if; + end if; + end process; + end generate IFG30; + + IFG31: if (signed_register_b = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((signed_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + sign_b_reg <= signb; + end if; + end if; + end process; + end generate IFG31; + + IFG32: if (signed_register_b = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, signb) + begin + if (((signed_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_reg <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + sign_b_reg <= signb; + end if; + end if; + end process; + end generate IFG32; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set sign_a_pipe) + -- The signal registered is sign_a_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if signed_pipeline_register_a + -- is unregistered and sign_a_reg changes value + -- --------------------------------------------------------------------------------- + + G7: if (signed_pipeline_register_a = "UNREGISTERED") generate + sign_a_pipe <= sign_a_reg; + end generate G7; + + IFG33: if (signed_pipeline_register_a = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, sign_a_reg) + begin + if (((signed_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + sign_a_pipe <= sign_a_reg; + end if; + end if; + end process; + end generate IFG33; + + IFG34: if (signed_pipeline_register_a = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, sign_a_reg) + begin + if (((signed_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + sign_a_pipe <= sign_a_reg; + end if; + end if; + end process; + end generate IFG34; + + IFG35: if (signed_pipeline_register_a = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, sign_a_reg) + begin + if (((signed_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + sign_a_pipe <= sign_a_reg; + end if; + end if; + end process; + end generate IFG35; + + IFG36: if (signed_pipeline_register_a = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, sign_a_reg) + begin + if (((signed_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then + sign_a_pipe <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + sign_a_pipe <= sign_a_reg; + end if; + end if; + end process; + end generate IFG36; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set sign_b_pipe) + -- The signal registered is sign_b_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if signed_pipeline_register_b + -- is unregistered and sign_b_reg changes value + -- --------------------------------------------------------------------------------- + + G8: if (signed_pipeline_register_b = "UNREGISTERED") generate + sign_b_pipe <= sign_b_reg; + end generate G8; + + IFG37: if (signed_pipeline_register_b = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, sign_b_reg) + begin + if (((signed_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + sign_b_pipe <= sign_b_reg; + end if; + end if; + end process; + end generate IFG37; + + IFG38: if (signed_pipeline_register_b = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, sign_b_reg) + begin + if (((signed_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + sign_b_pipe <= sign_b_reg; + end if; + end if; + end process; + end generate IFG38; + + IFG39: if (signed_pipeline_register_b = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, sign_b_reg) + begin + if (((signed_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + sign_b_pipe <= sign_b_reg; + end if; + end if; + end process; + end generate IFG39; + + IFG40: if (signed_pipeline_register_b = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, sign_b_reg) + begin + if (((signed_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or + ((signed_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or + ((signed_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or + ((signed_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then + sign_b_pipe <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + sign_b_pipe <= sign_b_reg; + end if; + end if; + end process; + end generate IFG40; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set outround_reg) + -- The signal registered is output_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if output_round_register + -- is unregistered and output_round changes value + -- --------------------------------------------------------------------------------- + + G17 : if (output_round_register = "UNREGISTERED") generate + outround_reg <= output_round; + end generate G17; + + IFG73: if (output_round_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, output_round) + begin + if (((output_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + outround_reg <= output_round; + end if; + end if; + end process; + end generate IFG73; + + IFG74: if (output_round_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, output_round) + begin + if (((output_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + outround_reg <= output_round; + end if; + end if; + end process; + end generate IFG74; + + IFG75: if (output_round_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, output_round) + begin + if (((output_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + outround_reg <= output_round; + end if; + end if; + end process; + end generate IFG75; + + IFG76: if (output_round_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, output_round) + begin + if (((output_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + outround_reg <= output_round; + end if; + end if; + end process; + end generate IFG76; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set outround_pipe) + -- The signal registered is outround_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if output_round_pipeline_register + -- is unregistered and outround_reg changes value + -- --------------------------------------------------------------------------------- + + G18 : if (output_round_pipeline_register = "UNREGISTERED") generate + outround_pipe <= outround_reg; + end generate G18; + + IFG77: if (output_round_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, outround_reg) + begin + if (((output_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + outround_pipe <= outround_reg; + end if; + end if; + end process; + end generate IFG77; + + IFG78: if (output_round_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, outround_reg) + begin + if (((output_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + outround_pipe <= outround_reg; + end if; + end if; + end process; + end generate IFG78; + + IFG79: if (output_round_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, outround_reg) + begin + if (((output_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + outround_pipe <= outround_reg; + end if; + end if; + end process; + end generate IFG79; + + IFG80: if (output_round_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, outround_reg) + begin + if (((output_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outround_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + outround_pipe <= outround_reg; + end if; + end if; + end process; + end generate IFG80; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set chainout_round_reg) + -- The signal registered is chainout_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if chainout_round_register + -- is unregistered and chainout_round changes value + -- --------------------------------------------------------------------------------- + + G19 : if (chainout_round_register = "UNREGISTERED") generate + chainout_round_reg <= chainout_round; + end generate G19; + + IFG81: if (chainout_round_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, chainout_round) + begin + if (((chainout_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + chainout_round_reg <= chainout_round; + end if; + end if; + end process; + end generate IFG81; + + IFG82: if (chainout_round_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, chainout_round) + begin + if (((chainout_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + chainout_round_reg <= chainout_round; + end if; + end if; + end process; + end generate IFG82; + + IFG83: if (chainout_round_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, chainout_round) + begin + if (((chainout_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + chainout_round_reg <= chainout_round; + end if; + end if; + end process; + end generate IFG83; + + IFG84: if (chainout_round_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, chainout_round) + begin + if (((chainout_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + chainout_round_reg <= chainout_round; + end if; + end if; + end process; + end generate IFG84; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set chainout_round_pipe) + -- The signal registered is chainout_round_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if chainout_round_pipeline_register + -- is unregistered and chainout_round_reg changes value + -- --------------------------------------------------------------------------------- + + G20 : if (chainout_round_pipeline_register = "UNREGISTERED") generate + chainout_round_pipe <= chainout_round_reg; + end generate G20; + + IFG85: if (chainout_round_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, chainout_round_reg) + begin + if (((chainout_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + chainout_round_pipe <= chainout_round_reg; + end if; + end if; + end process; + end generate IFG85; + + IFG86: if (chainout_round_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, chainout_round_reg) + begin + if (((chainout_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + chainout_round_pipe <= chainout_round_reg; + end if; + end if; + end process; + end generate IFG86; + + IFG87: if (chainout_round_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, chainout_round_reg) + begin + if (((chainout_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + chainout_round_pipe <= chainout_round_reg; + end if; + end if; + end process; + end generate IFG87; + + IFG88: if (chainout_round_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, chainout_round_reg) + begin + if (((chainout_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + chainout_round_pipe <= chainout_round_reg; + end if; + end if; + end process; + end generate IFG88; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set chainout_round_out_reg) + -- The signal registered is chainout_round_pipe + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if chainout_round_output_register + -- is unregistered and chainout_round_pipe changes value + -- --------------------------------------------------------------------------------- + + G21 : if (chainout_round_output_register = "UNREGISTERED") generate + chainout_round_out_reg <= chainout_round_pipe; + end generate G21; + + IFG89: if (chainout_round_output_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, chainout_round_pipe) + begin + if (((chainout_round_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_out_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + chainout_round_out_reg <= chainout_round_pipe; + end if; + end if; + end process; + end generate IFG89; + + IFG90: if (chainout_round_output_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, chainout_round_pipe) + begin + if (((chainout_round_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_out_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + chainout_round_out_reg <= chainout_round_pipe; + end if; + end if; + end process; + end generate IFG90; + + IFG91: if (chainout_round_output_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, chainout_round_pipe) + begin + if (((chainout_round_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_out_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + chainout_round_out_reg <= chainout_round_pipe; + end if; + end if; + end process; + end generate IFG91; + + IFG92: if (chainout_round_output_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, chainout_round_pipe) + begin + if (((chainout_round_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_round_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_round_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_round_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_round_out_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + chainout_round_out_reg <= chainout_round_pipe; + end if; + end if; + end process; + end generate IFG92; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set outsat_reg) + -- The signal registered is output_saturate + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if output_saturate_register + -- is unregistered and output_saturate changes value + -- --------------------------------------------------------------------------------- + + G22 : if (output_saturate_register = "UNREGISTERED") generate + outsat_reg <= output_saturate; + end generate G22; + + IFG93: if (output_saturate_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, output_saturate) + begin + if (((output_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + outsat_reg <= output_saturate; + end if; + end if; + end process; + end generate IFG93; + + IFG94: if (output_saturate_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, output_saturate) + begin + if (((output_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + outsat_reg <= output_saturate; + end if; + end if; + end process; + end generate IFG94; + + IFG95: if (output_saturate_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, output_saturate) + begin + if (((output_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + outsat_reg <= output_saturate; + end if; + end if; + end process; + end generate IFG95; + + IFG96: if (output_saturate_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, output_saturate) + begin + if (((output_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + outsat_reg <= output_saturate; + end if; + end if; + end process; + end generate IFG96; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set outsat_pipe) + -- The signal registered is outsat_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if output_saturate_pipeline_register + -- is unregistered and outsat_reg changes value + -- --------------------------------------------------------------------------------- + + G23 : if (output_saturate_pipeline_register = "UNREGISTERED") generate + outsat_pipe <= outsat_reg; + end generate G23; + + IFG97: if (output_saturate_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, outsat_reg) + begin + if (((output_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + outsat_pipe <= outsat_reg; + end if; + end if; + end process; + end generate IFG97; + + IFG98: if (output_saturate_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, outsat_reg) + begin + if (((output_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + outsat_pipe <= outsat_reg; + end if; + end if; + end process; + end generate IFG98; + + IFG99: if (output_saturate_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, outsat_reg) + begin + if (((output_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + outsat_pipe <= outsat_reg; + end if; + end if; + end process; + end generate IFG99; + + IFG100: if (output_saturate_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, outsat_reg) + begin + if (((output_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + outsat_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + outsat_pipe <= outsat_reg; + end if; + end if; + end process; + end generate IFG100; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set chainout_sat_reg) + -- The signal registered is chainout_saturate + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if chainout_saturate_register + -- is unregistered and chainout_saturate changes value + -- --------------------------------------------------------------------------------- + + G24 : if (chainout_saturate_register = "UNREGISTERED") generate + chainout_sat_reg <= chainout_saturate; + end generate G24; + + IFG101: if (chainout_saturate_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, chainout_saturate) + begin + if (((chainout_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + chainout_sat_reg <= chainout_saturate; + end if; + end if; + end process; + end generate IFG101; + + IFG102: if (chainout_saturate_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, chainout_saturate) + begin + if (((chainout_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + chainout_sat_reg <= chainout_saturate; + end if; + end if; + end process; + end generate IFG102; + + IFG103: if (chainout_saturate_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, chainout_saturate) + begin + if (((chainout_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + chainout_sat_reg <= chainout_saturate; + end if; + end if; + end process; + end generate IFG103; + + IFG104: if (chainout_saturate_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, chainout_saturate) + begin + if (((chainout_saturate_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + chainout_sat_reg <= chainout_saturate; + end if; + end if; + end process; + end generate IFG104; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set chainout_sat_pipe) + -- The signal registered is chainout_sat_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if chainout_saturate_pipeline_register + -- is unregistered and chainout_sat_reg changes value + -- --------------------------------------------------------------------------------- + + G25 : if (chainout_saturate_pipeline_register = "UNREGISTERED") generate + chainout_sat_pipe <= chainout_sat_reg; + end generate G25; + + IFG105: if (chainout_saturate_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, chainout_sat_reg) + begin + if (((chainout_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + chainout_sat_pipe <= chainout_sat_reg; + end if; + end if; + end process; + end generate IFG105; + + IFG106: if (chainout_saturate_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, chainout_sat_reg) + begin + if (((chainout_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + chainout_sat_pipe <= chainout_sat_reg; + end if; + end if; + end process; + end generate IFG106; + + IFG107: if (chainout_saturate_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, chainout_sat_reg) + begin + if (((chainout_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + chainout_sat_pipe <= chainout_sat_reg; + end if; + end if; + end process; + end generate IFG107; + + IFG108: if (chainout_saturate_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, chainout_sat_reg) + begin + if (((chainout_saturate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + chainout_sat_pipe <= chainout_sat_reg; + end if; + end if; + end process; + end generate IFG108; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set chainout_sat_out) + -- The signal registered is chainout_sat_pipe + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if chainout_saturate_output_register + -- is unregistered and chainout_sat_pipe changes value + -- --------------------------------------------------------------------------------- + + G26 : if (chainout_saturate_output_register = "UNREGISTERED") generate + chainout_sat_out <= chainout_sat_pipe; + end generate G26; + + IFG109: if (chainout_saturate_output_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, chainout_sat_pipe) + begin + if (((chainout_saturate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_out <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + chainout_sat_out <= chainout_sat_pipe; + end if; + end if; + end process; + end generate IFG109; + + IFG110: if (chainout_saturate_output_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, chainout_sat_pipe) + begin + if (((chainout_saturate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_out <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + chainout_sat_out <= chainout_sat_pipe; + end if; + end if; + end process; + end generate IFG110; + + IFG111: if (chainout_saturate_output_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, chainout_sat_pipe) + begin + if (((chainout_saturate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_out <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + chainout_sat_out <= chainout_sat_pipe; + end if; + end if; + end process; + end generate IFG111; + + IFG112: if (chainout_saturate_output_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, chainout_sat_pipe) + begin + if (((chainout_saturate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_saturate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_saturate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_saturate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + chainout_sat_out <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + chainout_sat_out <= chainout_sat_pipe; + end if; + end if; + end process; + end generate IFG112; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set scanouta_reg) + -- The signal registered is mult_a + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if scanouta_register + -- is unregistered and mult_a changes value + -- --------------------------------------------------------------------------------- + G27 : if ((scanouta_register = "UNREGISTERED" and chainout_adder = "YES") and (width_result > width_a + width_b + 8))generate + scanouta_reg <= mult_a((number_of_multipliers * int_width_a) - 1 - (int_width_a - width_a) downto ((number_of_multipliers-1) * int_width_a)); + end generate G27; + + G27_1: if (scanouta_register = "UNREGISTERED" and chainout_adder /= "YES") generate + scanouta_reg <= mult_a ((number_of_multipliers * int_width_a) - 1 downto ((number_of_multipliers -1 ) * int_width_a) + int_width_a - width_a) ; + end generate G27_1; + + G27_2: if ((scanouta_register = "UNREGISTERED" and chainout_adder = "YES") and (width_result <= width_a + width_b + 8))generate + scanouta_reg <= mult_a ((number_of_multipliers * int_width_a) - 1 downto ((number_of_multipliers -1 ) * int_width_a) + int_width_a - width_a) ; + end generate G27_2; + + IFG113: if (scanouta_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, mult_a) + begin + if (((scanouta_aclr = "ACLR0") and (aclr0 = '1')) or + ((scanouta_aclr = "ACLR1") and (aclr1 = '1')) or + ((scanouta_aclr = "ACLR2") and (aclr2 = '1')) or + ((scanouta_aclr = "ACLR3") and (aclr3 = '1'))) then + scanouta_reg <= (others => '0'); + elsif rising_edge(clock0) then + if (ena0 = '1') then + if (chainout_adder = "YES" and (width_result > width_a + width_b + 8)) then + scanouta_reg <= mult_a((number_of_multipliers * int_width_a) - 1 - (int_width_a - width_a) downto ((number_of_multipliers-1) * int_width_a)); + else + scanouta_reg <= mult_a ((number_of_multipliers * int_width_a) - 1 downto ((number_of_multipliers -1 ) * int_width_a) + int_width_a - width_a) ; + end if; + end if; + end if; + end process; + end generate IFG113; + + IFG114: if (scanouta_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, mult_a) + begin + if (((scanouta_aclr = "ACLR0") and (aclr0 = '1')) or + ((scanouta_aclr = "ACLR1") and (aclr1 = '1')) or + ((scanouta_aclr = "ACLR2") and (aclr2 = '1')) or + ((scanouta_aclr = "ACLR3") and (aclr3 = '1'))) then + scanouta_reg <= (others => '0'); + elsif rising_edge(clock1) then + if (ena1 = '1') then + if (chainout_adder = "YES" and (width_result > width_a + width_b + 8)) then + scanouta_reg <= mult_a((number_of_multipliers * int_width_a) - 1 - (int_width_a - width_a) downto ((number_of_multipliers-1) * int_width_a)); + else + scanouta_reg <= mult_a ((number_of_multipliers * int_width_a) - 1 downto ((number_of_multipliers -1 ) * int_width_a) + int_width_a - width_a) ; + end if; + end if; + end if; + end process; + end generate IFG114; + + IFG115: if (scanouta_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, mult_a) + begin + if (((scanouta_aclr = "ACLR0") and (aclr0 = '1')) or + ((scanouta_aclr = "ACLR1") and (aclr1 = '1')) or + ((scanouta_aclr = "ACLR2") and (aclr2 = '1')) or + ((scanouta_aclr = "ACLR3") and (aclr3 = '1'))) then + scanouta_reg <= (others => '0'); + elsif rising_edge(clock2) then + if (ena2 = '1') then + if (chainout_adder = "YES" and (width_result > width_a + width_b + 8)) then + scanouta_reg <= mult_a((number_of_multipliers * int_width_a) - 1 - (int_width_a - width_a) downto ((number_of_multipliers-1) * int_width_a)); + else + scanouta_reg <= mult_a ((number_of_multipliers * int_width_a) - 1 downto ((number_of_multipliers -1 ) * int_width_a) + int_width_a - width_a) ; + end if; + end if; + end if; + end process; + end generate IFG115; + + IFG116: if (scanouta_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, mult_a) + begin + if (((scanouta_aclr = "ACLR0") and (aclr0 = '1')) or + ((scanouta_aclr = "ACLR1") and (aclr1 = '1')) or + ((scanouta_aclr = "ACLR2") and (aclr2 = '1')) or + ((scanouta_aclr = "ACLR3") and (aclr3 = '1'))) then + scanouta_reg <= (others => '0'); + elsif rising_edge(clock3) then + if (ena3 = '1') then + if (chainout_adder = "YES" and (width_result > width_a + width_b + 8)) then + scanouta_reg <= mult_a((number_of_multipliers * int_width_a) - 1 - (int_width_a - width_a) downto ((number_of_multipliers-1) * int_width_a)); + else + scanouta_reg <= mult_a ((number_of_multipliers * int_width_a) - 1 downto ((number_of_multipliers -1 ) * int_width_a) + int_width_a - width_a) ; + end if; + end if; + end if; + end process; + end generate IFG116; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set zerochainout_reg) + -- The signal registered is zero_chainout + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if zero_chainout_output_register + -- is unregistered and zero_chainout changes value + -- --------------------------------------------------------------------------------- + + G28 : if (zero_chainout_output_register = "UNREGISTERED") generate + zerochainout_reg <= zero_chainout; + end generate G28; + + IFG117: if (zero_chainout_output_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, zero_chainout) + begin + if (((zero_chainout_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_chainout_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_chainout_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_chainout_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zerochainout_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + zerochainout_reg <= zero_chainout; + end if; + end if; + end process; + end generate IFG117; + + IFG118: if (zero_chainout_output_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, zero_chainout) + begin + if (((zero_chainout_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_chainout_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_chainout_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_chainout_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zerochainout_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + zerochainout_reg <= zero_chainout; + end if; + end if; + end process; + end generate IFG118; + + IFG119: if (zero_chainout_output_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, zero_chainout) + begin + if (((zero_chainout_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_chainout_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_chainout_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_chainout_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zerochainout_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + zerochainout_reg <= zero_chainout; + end if; + end if; + end process; + end generate IFG119; + + IFG120: if (zero_chainout_output_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, zero_chainout) + begin + if (((zero_chainout_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_chainout_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_chainout_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_chainout_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zerochainout_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + zerochainout_reg <= zero_chainout; + end if; + end if; + end process; + end generate IFG120; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set rotate_reg) + -- The signal registered is rotate + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if rotate_register + -- is unregistered and rotate changes value + -- --------------------------------------------------------------------------------- + + G29 : if (rotate_register = "UNREGISTERED") generate + rotate_reg <= rotate; + end generate G29; + + IFG121: if (rotate_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, rotate) + begin + if (((rotate_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + rotate_reg <= rotate; + end if; + end if; + end process; + end generate IFG121; + + IFG122: if (rotate_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, rotate) + begin + if (((rotate_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + rotate_reg <= rotate; + end if; + end if; + end process; + end generate IFG122; + + IFG123: if (rotate_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, rotate) + begin + if (((rotate_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + rotate_reg <= rotate; + end if; + end if; + end process; + end generate IFG123; + + IFG124: if (rotate_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, rotate) + begin + if (((rotate_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + rotate_reg <= rotate; + end if; + end if; + end process; + end generate IFG124; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set rotate_pipe) + -- The signal registered is rotate_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if rotate_pipeline_register + -- is unregistered and rotate_reg changes value + -- --------------------------------------------------------------------------------- + + G30 : if (rotate_pipeline_register = "UNREGISTERED") generate + rotate_pipe <= rotate_reg; + end generate G30; + + IFG125: if (rotate_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, rotate_reg) + begin + if (((rotate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + rotate_pipe <= rotate_reg; + end if; + end if; + end process; + end generate IFG125; + + IFG126: if (rotate_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, rotate_reg) + begin + if (((rotate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + rotate_pipe <= rotate_reg; + end if; + end if; + end process; + end generate IFG126; + + IFG127: if (rotate_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, rotate_reg) + begin + if (((rotate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + rotate_pipe <= rotate_reg; + end if; + end if; + end process; + end generate IFG127; + + IFG128: if (rotate_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, rotate_reg) + begin + if (((rotate_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + rotate_pipe <= rotate_reg; + end if; + end if; + end process; + end generate IFG128; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set rotate_out) + -- The signal registered is rotate_pipe + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if rotate_output_register + -- is unregistered and rotate_pipe changes value + -- --------------------------------------------------------------------------------- + + G31 : if (rotate_output_register = "UNREGISTERED") generate + rotate_out <= rotate_pipe; + end generate G31; + + IFG129: if (rotate_output_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, rotate_out) + begin + if (((rotate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_out <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + rotate_out <= rotate_pipe; + end if; + end if; + end process; + end generate IFG129; + + IFG130: if (rotate_output_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, rotate_out) + begin + if (((rotate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_out <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + rotate_out <= rotate_pipe; + end if; + end if; + end process; + end generate IFG130; + + IFG131: if (rotate_output_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, rotate_out) + begin + if (((rotate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_out <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + rotate_out <= rotate_pipe; + end if; + end if; + end process; + end generate IFG131; + + IFG132: if (rotate_output_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, rotate_out) + begin + if (((rotate_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((rotate_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((rotate_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((rotate_output_aclr = "ACLR3") and (aclr3 = '1'))) then + rotate_out <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + rotate_out <= rotate_pipe; + end if; + end if; + end process; + end generate IFG132; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set shiftr_reg) + -- The signal registered is shift_right + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if shift_right_register + -- is unregistered and shift_right changes value + -- --------------------------------------------------------------------------------- + + G32 : if (shift_right_register = "UNREGISTERED") generate + shiftr_reg <= shift_right; + end generate G32; + + IFG133: if (shift_right_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, shift_right) + begin + if (((shift_right_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + shiftr_reg <= shift_right; + end if; + end if; + end process; + end generate IFG133; + + IFG134: if (shift_right_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, shift_right) + begin + if (((shift_right_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + shiftr_reg <= shift_right; + end if; + end if; + end process; + end generate IFG134; + + IFG135: if (shift_right_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, shift_right) + begin + if (((shift_right_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + shiftr_reg <= shift_right; + end if; + end if; + end process; + end generate IFG135; + + IFG136: if (shift_right_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, shift_right) + begin + if (((shift_right_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + shiftr_reg <= shift_right; + end if; + end if; + end process; + end generate IFG136; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set shiftr_pipe) + -- The signal registered is shiftr_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if shift_right_pipeline_register + -- is unregistered and shiftr_reg changes value + -- --------------------------------------------------------------------------------- + + G33 : if (shift_right_pipeline_register = "UNREGISTERED") generate + shiftr_pipe <= shiftr_reg; + end generate G33; + + IFG137: if (shift_right_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, shiftr_reg) + begin + if (((shift_right_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + shiftr_pipe <= shiftr_reg; + end if; + end if; + end process; + end generate IFG137; + + IFG138: if (shift_right_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, shiftr_reg) + begin + if (((shift_right_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + shiftr_pipe <= shiftr_reg; + end if; + end if; + end process; + end generate IFG138; + + IFG139: if (shift_right_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, shiftr_reg) + begin + if (((shift_right_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + shiftr_pipe <= shiftr_reg; + end if; + end if; + end process; + end generate IFG139; + + IFG140: if (shift_right_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, shiftr_reg) + begin + if (((shift_right_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + shiftr_pipe <= shiftr_reg; + end if; + end if; + end process; + end generate IFG140; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set shiftr_out) + -- The signal registered is shiftr_pipe + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if shift_right_output_register + -- is unregistered and shiftr_pipe changes value + -- --------------------------------------------------------------------------------- + + G34 : if (shift_right_output_register = "UNREGISTERED") generate + shiftr_out <= shiftr_pipe; + end generate G34; + + IFG141: if (shift_right_output_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, shiftr_pipe) + begin + if (((shift_right_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_output_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_out <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + shiftr_out <= shiftr_pipe; + end if; + end if; + end process; + end generate IFG141; + + IFG142: if (shift_right_output_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, shiftr_pipe) + begin + if (((shift_right_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_output_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_out <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + shiftr_out <= shiftr_pipe; + end if; + end if; + end process; + end generate IFG142; + + IFG143: if (shift_right_output_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, shiftr_pipe) + begin + if (((shift_right_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_output_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_out <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + shiftr_out <= shiftr_pipe; + end if; + end if; + end process; + end generate IFG143; + + IFG144: if (shift_right_output_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, shiftr_pipe) + begin + if (((shift_right_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((shift_right_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((shift_right_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((shift_right_output_aclr = "ACLR3") and (aclr3 = '1'))) then + shiftr_out <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + shiftr_out <= shiftr_pipe; + end if; + end if; + end process; + end generate IFG144; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set zeroloopback_reg) + -- The signal registered is zero_loopback + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if zero_loopback_register + -- is unregistered and zero_loopback changes value + -- --------------------------------------------------------------------------------- + + G35 : if (zero_loopback_register = "UNREGISTERED") generate + zeroloopback_reg <= zero_loopback; + end generate G35; + + IFG145: if (zero_loopback_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, zero_loopback) + begin + if (((zero_loopback_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + zeroloopback_reg <= zero_loopback; + end if; + end if; + end process; + end generate IFG145; + + IFG146: if (zero_loopback_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, zero_loopback) + begin + if (((zero_loopback_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + zeroloopback_reg <= zero_loopback; + end if; + end if; + end process; + end generate IFG146; + + IFG147: if (zero_loopback_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, zero_loopback) + begin + if (((zero_loopback_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + zeroloopback_reg <= zero_loopback; + end if; + end if; + end process; + end generate IFG147; + + IFG148: if (zero_loopback_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, zero_loopback) + begin + if (((zero_loopback_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + zeroloopback_reg <= zero_loopback; + end if; + end if; + end process; + end generate IFG148; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set zeroloopback_pipe) + -- The signal registered is zeroloopback_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if zero_loopback_pipeline_register + -- is unregistered and zeroloopback_reg changes value + -- --------------------------------------------------------------------------------- + + G36 : if (zero_loopback_pipeline_register = "UNREGISTERED") generate + zeroloopback_pipe <= zeroloopback_reg; + end generate G36; + + IFG149: if (zero_loopback_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, zeroloopback_reg) + begin + if (((zero_loopback_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + zeroloopback_pipe <= zeroloopback_reg; + end if; + end if; + end process; + end generate IFG149; + + IFG150: if (zero_loopback_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, zeroloopback_reg) + begin + if (((zero_loopback_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + zeroloopback_pipe <= zeroloopback_reg; + end if; + end if; + end process; + end generate IFG150; + + IFG151: if (zero_loopback_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, zeroloopback_reg) + begin + if (((zero_loopback_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + zeroloopback_pipe <= zeroloopback_reg; + end if; + end if; + end process; + end generate IFG151; + + IFG152: if (zero_loopback_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, zeroloopback_reg) + begin + if (((zero_loopback_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + zeroloopback_pipe <= zeroloopback_reg; + end if; + end if; + end process; + end generate IFG152; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set zeroloopback_out) + -- The signal registered is zeroloopback_pipe + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if zero_loopback_output_register + -- is unregistered and zeroloopback_pipe changes value + -- --------------------------------------------------------------------------------- + + G37 : if (zero_loopback_output_register = "UNREGISTERED") generate + zeroloopback_out <= zeroloopback_pipe; + end generate G37; + + IFG153: if (zero_loopback_output_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, zeroloopback_pipe) + begin + if (((zero_loopback_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_out <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + zeroloopback_out <= zeroloopback_pipe; + end if; + end if; + end process; + end generate IFG153; + + IFG154: if (zero_loopback_output_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, zeroloopback_pipe) + begin + if (((zero_loopback_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_out <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + zeroloopback_out <= zeroloopback_pipe; + end if; + end if; + end process; + end generate IFG154; + + IFG155: if (zero_loopback_output_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, zeroloopback_pipe) + begin + if (((zero_loopback_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_out <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + zeroloopback_out <= zeroloopback_pipe; + end if; + end if; + end process; + end generate IFG155; + + IFG156: if (zero_loopback_output_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, zeroloopback_pipe) + begin + if (((zero_loopback_output_aclr = "ACLR0") and (aclr0 = '1')) or + ((zero_loopback_output_aclr = "ACLR1") and (aclr1 = '1')) or + ((zero_loopback_output_aclr = "ACLR2") and (aclr2 = '1')) or + ((zero_loopback_output_aclr = "ACLR3") and (aclr3 = '1'))) then + zeroloopback_out <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + zeroloopback_out <= zeroloopback_pipe; + end if; + end if; + end process; + end generate IFG156; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set accumsload_reg) + -- The signal registered is accum_sload + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_sload_register + -- is unregistered and accum_sload changes value + -- --------------------------------------------------------------------------------- + + G38 : if (accum_sload_register = "UNREGISTERED") generate + process (accum_sload, output_round) + begin + if ((accumulator = "YES") and (output_rounding = "VARIABLE") and (chainout_adder = "NO")) then + accumsload_reg <= output_round; + else + accumsload_reg <= accum_sload; + end if; + end process; + end generate G38; + + IFG157: if (accum_sload_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_reg <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + if ((accumulator = "YES") and (output_rounding = "VARIABLE") and (chainout_adder = "NO")) then + accumsload_reg <= output_round; + else + accumsload_reg <= accum_sload; + end if; + end if; + end if; + end process; + end generate IFG157; + + IFG158: if (accum_sload_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_reg <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + if ((accumulator = "YES") and (output_rounding = "VARIABLE") and (chainout_adder = "NO")) then + accumsload_reg <= output_round; + else + accumsload_reg <= accum_sload; + end if; + end if; + end if; + end process; + end generate IFG158; + + IFG159: if (accum_sload_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_reg <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + if ((accumulator = "YES") and (output_rounding = "VARIABLE") and (chainout_adder = "NO")) then + accumsload_reg <= output_round; + else + accumsload_reg <= accum_sload; + end if; + end if; + end if; + end process; + end generate IFG159; + + IFG160: if (accum_sload_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, accum_sload) + begin + if (((accum_sload_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_reg <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + if ((accumulator = "YES") and (output_rounding = "VARIABLE") and (chainout_adder = "NO")) then + accumsload_reg <= output_round; + else + accumsload_reg <= accum_sload; + end if; + end if; + end if; + end process; + end generate IFG160; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set accumsload_pipe) + -- The signal registered is accumsload_reg + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if accum_sload_pipeline_register + -- is unregistered and accumsload_reg changes value + -- --------------------------------------------------------------------------------- + + G39 : if (accum_sload_pipeline_register = "UNREGISTERED") generate + accumsload_pipe <= accumsload_reg; + end generate G39; + + IFG161: if (accum_sload_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, accumsload_reg) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_pipe <= '0'; + elsif rising_edge(clock0) then + if (ena0 = '1') then + accumsload_pipe <= accumsload_reg; + end if; + end if; + end process; + end generate IFG161; + + IFG162: if (accum_sload_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, accumsload_reg) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_pipe <= '0'; + elsif rising_edge(clock1) then + if (ena1 = '1') then + accumsload_pipe <= accumsload_reg; + end if; + end if; + end process; + end generate IFG162; + + IFG163: if (accum_sload_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, accumsload_reg) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_pipe <= '0'; + elsif rising_edge(clock2) then + if (ena2 = '1') then + accumsload_pipe <= accumsload_reg; + end if; + end if; + end process; + end generate IFG163; + + IFG164: if (accum_sload_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, accumsload_reg) + begin + if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + accumsload_pipe <= '0'; + elsif rising_edge(clock3) then + if (ena3 = '1') then + accumsload_pipe <= accumsload_reg; + end if; + end if; + end process; + end generate IFG164; + + --------------------------------------------------------------------------- + + process (clock0, clock1, clock2, clock3, aclr_vector, dataa_int, datab_int, scanina, scaninb, clock_vector, ena_vector, + aclr0, aclr1, aclr2, aclr3, sourcea_wire, sourceb_wire, tmp_mult_a, tmp_mult_b, feedback) + variable temp_clock : integer := 0; + variable temp_aclr : integer := 0; + variable x : integer := 0; + variable scanina_var : std_logic_vector (int_width_a -1 downto 0):= (others => '0'); + variable scaninb_var : std_logic_vector (int_width_b -1 downto 0):= (others => '0'); + variable mult_a_pre0 : std_logic_vector (4 * int_width_a -1 downto 0):= (others => '0'); + variable mult_a_pre1 : std_logic_vector (4 * int_width_a -1 downto 0):= (others => '0'); + variable mult_a_pre2 : std_logic_vector (4 * int_width_a -1 downto 0):= (others => '0'); + variable mult_a_pre3 : std_logic_vector (4 * int_width_a -1 downto 0):= (others => '0'); + variable mult_b_pre0 : std_logic_vector (4 * int_width_b -1 downto 0):= (others => '0'); + variable mult_b_pre1 : std_logic_vector (4 * int_width_b -1 downto 0):= (others => '0'); + variable mult_b_pre2 : std_logic_vector (4 * int_width_b -1 downto 0):= (others => '0'); + variable mult_b_pre3 : std_logic_vector (4 * int_width_b -1 downto 0):= (others => '0'); + variable mult1_source_scanin_en : std_logic := '0'; + variable mult2_source_scanin_en : std_logic := '0'; + variable mult3_source_scanin_en : std_logic := '0'; + begin + scanina_var(int_width_a - 1 downto (int_width_a - width_a)) := scanina (width_a - 1 downto 0); + scaninb_var(int_width_b - 1 downto (int_width_b - width_b)) := scaninb (width_b - 1 downto 0); + + --sets up all the clock, clock enable and clear signals for multiplier0 + if not (multiplier_register0 = "UNREGISTERED") then + temp_clock := resolve_clock (multiplier_register0); + mult_clock(0) <= clock_vector (temp_clock); + mult_ena(0) <= ena_vector (temp_clock); + temp_aclr := resolve_aclr (multiplier_aclr0); + mult_aclr(0) <= aclr_vector (temp_aclr); + is_reg(0) <= '1'; + end if; + + --sets up all the clock, clock enable and clear signals for multiplier1 + if not (multiplier_register1 = "UNREGISTERED") then + temp_clock := resolve_clock (multiplier_register1); + mult_clock(1) <= clock_vector (temp_clock); + mult_ena(1) <= ena_vector (temp_clock); + temp_aclr := resolve_aclr (multiplier_aclr1); + mult_aclr(1) <= aclr_vector (temp_aclr); + is_reg(1) <= '1'; + end if; + + --sets up all the clock, clock enable and clear signals for multiplier2 + if not (multiplier_register2 = "UNREGISTERED") then + temp_clock := resolve_clock (multiplier_register2); + mult_clock(2) <= clock_vector (temp_clock); + mult_ena(2) <= ena_vector (temp_clock); + temp_aclr := resolve_aclr (multiplier_aclr2); + mult_aclr(2) <= aclr_vector (temp_aclr); + is_reg(2) <= '1'; + end if; + + --sets up all the clock, clock enable and clear signals for multiplier3 + if not (multiplier_register3 = "UNREGISTERED") then + temp_clock := resolve_clock (multiplier_register3); + mult_clock(3) <= clock_vector (temp_clock); + mult_ena(3) <= ena_vector (temp_clock); + temp_aclr := resolve_aclr (multiplier_aclr3); + mult_aclr(3) <= aclr_vector (temp_aclr); + is_reg(3) <= '1'; + end if; + + + -- --------------------------------------------- + -- SETTING UP THE DATA INPUT REGISTERS OF PORT A + -- --------------------------------------------- + + -- ----------------- + -- INPUT_REGISTER_A0 + -- ----------------- + + -- set the initial value for mult_a_pre0 from dataa_int + if (input_source_a0 = "DATAA") then + mult_a_pre0 (int_width_a-1 downto 0) := dataa_int (int_width_a-1 downto 0); + elsif (input_source_a0 = "SCANA") then + if (stratixii_block) then + mult_a_pre0 (int_width_a-1 downto 0) := scanina_var; + else + mult_a_pre0 (int_width_a-1 downto 0) := dataa_int (int_width_a-1 downto 0); + end if; + else + if (sourcea_wire(0) = '1') then + mult_a_pre0 (int_width_a-1 downto 0) := scanina_var; + else + mult_a_pre0 (int_width_a-1 downto 0) := dataa_int (int_width_a-1 downto 0); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_a and mult_a_pre1 (this is the next variable to be used by register_a1) + -- whenever clear signal is triggered + -- + -- If clock is triggered or register is not used, assign mult_a to mult_a_pre0 + -- + -- Check make sure that register_a1 doesnt use the same clock as register_a0, + -- or if register_a0 is unregistered + -- If so, then update mult_a_pre1 with mult_a_pre0 to be used for register_a1 + -- + -- if nothing happens (ie. clock/clear is not triggered), + -- then update mult_a_pre1 with the current value of mult_a + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_a0 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a0 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a0 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a0 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_a0 = "UNREGISTERED"))) then + mult_a(int_width_a-1 downto 0) <= (others => '0'); + mult_a_pre1(int_width_a-1 downto 0) := (others => '0'); + elsif (((input_register_a0 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_a0 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_a0 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_a0 = "CLOCK3") and rising_edge(clock3)) or + (input_register_a0 = "UNREGISTERED")) then + if (((input_register_a0 = "CLOCK0") and (ena0 = '1')) or + ((input_register_a0 = "CLOCK1") and (ena1 = '1')) or + ((input_register_a0 = "CLOCK2") and (ena2 = '1')) or + ((input_register_a0 = "CLOCK3") and (ena3 = '1')) or + (input_register_a0 = "UNREGISTERED")) then + mult_a (int_width_a-1 downto 0) <= mult_a_pre0 (int_width_a-1 downto 0); + if ((not(input_register_a0 = input_register_a1)) or (input_register_a0 = "UNREGISTERED")) then + mult_a_pre1 (int_width_a-1 downto 0) := mult_a_pre0 (int_width_a-1 downto 0); + end if; + end if; + else + mult_a_pre1 (int_width_a-1 downto 0) := tmp_mult_a (int_width_a-1 downto 0); + end if; + + + -- ----------------- + -- INPUT_REGISTER_A1 + -- ----------------- + + -- set the initial value for mult_a_pre1 from dataa_int if input source is from dataa + -- otherwise, load it from the mult_a_pre1 that stored the previous value from register_a0 + if (input_source_a1 = "DATAA") then + if (mult1_source_scanin_en = '1') then + mult_a_pre1 ((2)*int_width_a-1 downto (int_width_a)) := mult_a_pre1(int_width_a-1 downto 0); + else + mult_a_pre1 ((2)*int_width_a-1 downto (int_width_a)) := dataa_int ((2)*int_width_a-1 downto (int_width_a)); + end if; + elsif (input_source_a1 = "SCANA") then + mult_a_pre1 ((2)*int_width_a-1 downto (int_width_a)) := mult_a_pre1(int_width_a-1 downto 0); + else + if (sourcea_wire(1) = '1') then + mult_a_pre1 ((2)*int_width_a-1 downto (int_width_a)) := mult_a_pre1(int_width_a-1 downto 0); + else + mult_a_pre1 ((2)*int_width_a-1 downto (int_width_a)) := dataa_int ((2)*int_width_a-1 downto (int_width_a)); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_a and mult_a_pre2 (this is the next variable to be used by register_a2) + -- whenever clear signal is triggered + -- + -- If clock is triggered or register is not used, assign mult_a to mult_a_pre1 + -- + -- Check make sure that register_a1 doesnt use the same clock as register_a2, + -- or if register_a1 is unregistered + -- If so, then update mult_a_pre2 with mult_a_pre1 to be used for register_a2 + -- + -- if nothing happens (ie. clock/clear is not triggered), + -- then update mult_a_pre2 with the current value of mult_a + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_a1 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a1 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a1 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a1 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_a1 = "UNREGISTERED"))) then + mult_a ((2)*int_width_a-1 downto (int_width_a)) <= (others => '0'); + mult_a_pre2 ((2)*int_width_a-1 downto (int_width_a)) := (others => '0'); + elsif (((input_register_a1 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_a1 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_a1 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_a1 = "CLOCK3") and rising_edge(clock3)) or + (input_register_a1 = "UNREGISTERED")) then + if (((input_register_a1 = "CLOCK0") and (ena0 = '1')) or + ((input_register_a1 = "CLOCK1") and (ena1 = '1')) or + ((input_register_a1 = "CLOCK2") and (ena2 = '1')) or + ((input_register_a1 = "CLOCK3") and (ena3 = '1')) or + (input_register_a1 = "UNREGISTERED")) then + mult_a ((2)*int_width_a-1 downto (int_width_a)) <= mult_a_pre1 ((2)*int_width_a-1 downto int_width_a); + if ((not(input_register_a1 = input_register_a2)) or (input_register_a1 = "UNREGISTERED")) then + mult_a_pre2 ((2)*int_width_a-1 downto (int_width_a)) := mult_a_pre1 ((2)*int_width_a-1 downto int_width_a); + end if; + end if; + else + mult_a_pre2 ((2)*int_width_a-1 downto (int_width_a)) := tmp_mult_a ((2)*int_width_a-1 downto (int_width_a)); + end if; + + + -- ----------------- + -- INPUT_REGISTER_A2 + -- ----------------- + + -- set the initial value for mult_a_pre2 from dataa_int if input source is from dataa + -- otherwise, load it from the mult_a_pre2 that stored the previous value from register_a1 + if (input_source_a2 = "DATAA") then + if (mult2_source_scanin_en = '1') then + mult_a_pre2 ((3)*int_width_a-1 downto (2*int_width_a)) := mult_a_pre2((2)*int_width_a-1 downto (int_width_a)); + else + mult_a_pre2 ((3)*int_width_a-1 downto (2*int_width_a)) := dataa_int ((3)*int_width_a-1 downto (2*int_width_a)); + end if; + elsif (input_source_a2 = "SCANA") then + mult_a_pre2 ((3)*int_width_a-1 downto (2*int_width_a)) := mult_a_pre2((2)*int_width_a-1 downto (int_width_a)); + else + if (sourcea_wire(2) = '1') then + mult_a_pre2 ((3)*int_width_a-1 downto (2*int_width_a)) := mult_a_pre2((2)*int_width_a-1 downto (int_width_a)); + else + mult_a_pre2 ((3)*int_width_a-1 downto (2*int_width_a)) := dataa_int ((3)*int_width_a-1 downto (2*int_width_a)); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_a and mult_a_pre3 (this is the next variable to be used by register_a3) + -- whenever clear signal is triggered + -- + -- If clock is triggered or register is not used, assign mult_a to mult_a_pre2 + -- + -- Check make sure that register_a2 doesnt use the same clock as register_a3, + -- or if register_a2 is unregistered + -- If so, then update mult_a_pre3 with mult_a_pre2 to be used for register_a3 + -- + -- if nothing happens (ie. clock/clear is not triggered), + -- then update mult_a_pre3 with the current value of mult_a + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_a2 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a2 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a2 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a2 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_a2 = "UNREGISTERED"))) then + + mult_a ((3)*int_width_a-1 downto (2*int_width_a)) <= (others => '0'); + mult_a_pre3 ((3)*int_width_a-1 downto (2*int_width_a)) := (others => '0'); + + elsif (((input_register_a2 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_a2 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_a2 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_a2 = "CLOCK3") and rising_edge(clock3)) or + (input_register_a2 = "UNREGISTERED")) then + if (((input_register_a2 = "CLOCK0") and (ena0 = '1')) or + ((input_register_a2 = "CLOCK1") and (ena1 = '1')) or + ((input_register_a2 = "CLOCK2") and (ena2 = '1')) or + ((input_register_a2 = "CLOCK3") and (ena3 = '1')) or + (input_register_a2 = "UNREGISTERED")) then + + mult_a ((3)*int_width_a-1 downto (2*int_width_a)) <= mult_a_pre2 ((3)*int_width_a-1 downto (2*int_width_a)); + + if ((not(input_register_a2 = input_register_a3)) or (input_register_a2 = "UNREGISTERED")) then + mult_a_pre3 ((3)*int_width_a-1 downto (2*int_width_a)) := mult_a_pre2 ((3)*int_width_a-1 downto (2*int_width_a)); + end if; + end if; + else + mult_a_pre3 ((3)*int_width_a-1 downto (2*int_width_a)) := tmp_mult_a ((3)*int_width_a-1 downto (2*int_width_a)); + end if; + + + -- ----------------- + -- INPUT_REGISTER_A3 + -- ----------------- + + -- set the initial value for mult_a_pre3 from dataa_int if input source is from dataa + -- otherwise, load it from the mult_a_pre3 that stored the previous value from register_a2 + if (input_source_a3 = "DATAA") then + if (mult3_source_scanin_en = '1') then + mult_a_pre3 ((4)*int_width_a-1 downto (3*int_width_a)) := mult_a_pre3 ((3)*int_width_a-1 downto (2*int_width_a)); + else + mult_a_pre3 ((4)*int_width_a-1 downto (3*int_width_a)) := dataa_int ((4)*int_width_a-1 downto (3*int_width_a)); + end if; + elsif (input_source_a3 = "SCANA") then + mult_a_pre3 ((4)*int_width_a-1 downto (3*int_width_a)) := mult_a_pre3 ((3)*int_width_a-1 downto (2*int_width_a)); + else + if (sourcea_wire(3) = '1') then + mult_a_pre3 ((4)*int_width_a-1 downto (3*int_width_a)) := mult_a_pre3 ((3)*int_width_a-1 downto (2*int_width_a)); + else + mult_a_pre3 ((4)*int_width_a-1 downto (3*int_width_a)) := dataa_int ((4)*int_width_a-1 downto (3*int_width_a)); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_a whenever clear signal is triggered + -- If clock is triggered or register is not used, assign mult_a to mult_a_pre3 + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_a3 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_a3 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_a3 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_a3 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_a3 = "UNREGISTERED"))) then + mult_a ((4)*int_width_a-1 downto (3*int_width_a)) <= (others => '0'); + elsif (((input_register_a3 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_a3 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_a3 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_a3 = "CLOCK3") and rising_edge(clock3)) or + (input_register_a3 = "UNREGISTERED")) then + if (((input_register_a3 = "CLOCK0") and (ena0 = '1')) or + ((input_register_a3 = "CLOCK1") and (ena1 = '1')) or + ((input_register_a3 = "CLOCK2") and (ena2 = '1')) or + ((input_register_a3 = "CLOCK3") and (ena3 = '1')) or + (input_register_a3 = "UNREGISTERED")) then + mult_a ((4)*int_width_a-1 downto (3*int_width_a)) <= mult_a_pre3 ((4)*int_width_a-1 downto (3*int_width_a)); + + end if; + end if; + + + -- --------------------------------------------- + -- SETTING UP THE DATA INPUT REGISTERS OF PORT B + -- --------------------------------------------- + + -- ----------------- + -- INPUT_REGISTER_B0 + -- ----------------- + + -- set the initial value for mult_b_pre0 from datab_int + if (input_source_b0 = "DATAB") then + mult_b_pre0 (int_width_b-1 downto 0) := datab_int (int_width_b-1 downto 0); + elsif (input_source_b0 = "SCANB") then + if (stratixii_block) then + mult_b_pre0 (int_width_b-1 downto 0) := scaninb_var; + else + mult_b_pre0 (int_width_b-1 downto 0) := datab_int (int_width_b-1 downto 0); + end if; + elsif (stratixiii_block and (input_source_b0 = "LOOPBACK")) then + mult_b_pre0 (int_width_b - 1 downto 0) := feedback; + else + if (sourceb_wire(0) = '1') then + mult_b_pre0 (int_width_b-1 downto 0) := scaninb_var; + else + mult_b_pre0 (int_width_b-1 downto 0) := datab_int (int_width_b-1 downto 0); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_b and mult_b_pre1 (this is the next variable to be used by register_b1) + -- whenever clear signal is triggered + -- + -- If clock is triggered or register is not used, assign mult_b to mult_b_pre0 + -- + -- Check make sure that register_b1 doesnt use the same clock as register_b0, + -- or if register_b0 is unregistered + -- If so, then update mult_b_pre1 with mult_b_pre0 to be used for register_b1 + -- + -- if nothing happens (ie. clock/clear is not triggered), + -- then update mult_b_pre1 with the current value of mult_b + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_b0 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b0 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b0 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b0 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_b0 = "UNREGISTERED"))) then + mult_b (int_width_b-1 downto 0) <= (others => '0'); + mult_b_pre1 (int_width_b-1 downto 0) := (others => '0'); + elsif (((input_register_b0 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_b0 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_b0 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_b0 = "CLOCK3") and rising_edge(clock3)) or + (input_register_b0 = "UNREGISTERED")) then + if (((input_register_b0 = "CLOCK0") and (ena0 = '1')) or + ((input_register_b0 = "CLOCK1") and (ena1 = '1')) or + ((input_register_b0 = "CLOCK2") and (ena2 = '1')) or + ((input_register_b0 = "CLOCK3") and (ena3 = '1')) or + (input_register_b0 = "UNREGISTERED")) then + mult_b (int_width_b-1 downto 0) <= mult_b_pre0 (int_width_b-1 downto 0); + if ((not(input_register_b0 = input_register_b1)) or (input_register_b0 = "UNREGISTERED")) then + mult_b_pre1 (int_width_b-1 downto 0) := mult_b_pre0 (int_width_b-1 downto 0); + end if; + end if; + else + mult_b_pre1 (int_width_b-1 downto 0) := tmp_mult_b (int_width_b-1 downto 0); + end if; + + + -- ----------------- + -- INPUT_REGISTER_B1 + -- ----------------- + + -- set the initial value for mult_b_pre1 from datab_int if input source is from datab + -- otherwise, load it from the mult_b_pre1 that stored the previous value from register_b0 + if (input_source_b1 = "DATAB") then + -- if loopback mode is used, the data input for b1 comes from datab[width_b-1 to 0] + if (input_source_b0 = "LOOPBACK") then + mult_b_pre1 ((2)*int_width_b-1 downto (int_width_b)) := datab_int (int_width_b-1 downto 0); + else + mult_b_pre1 ((2)*int_width_b-1 downto (int_width_b)) := datab_int ((2)*int_width_b-1 downto (int_width_b)); + end if; + elsif (input_source_b1 = "SCANB") then + if (mult1_source_scanin_en = '1') then + mult_b_pre1 ((2)*int_width_b-1 downto (int_width_b)) := datab_int ((2)*int_width_b-1 downto (int_width_b)); + else + mult_b_pre1 ((2)*int_width_b-1 downto (int_width_b)) := mult_b_pre1 (int_width_b-1 downto 0); + end if; + else + if (sourceb_wire(1) = '1') then + mult_b_pre1 ((2)*int_width_b-1 downto (int_width_b)) := mult_b_pre1 (int_width_b-1 downto 0); + else + mult_b_pre1 ((2)*int_width_b-1 downto (int_width_b)) := datab_int ((2)*int_width_b-1 downto (int_width_b)); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_b and mult_b_pre2 (this is the next variable to be used by register_b2) + -- whenever clear signal is triggered + -- + -- If clock is triggered or register is not used, assign mult_b to mult_b_pre1 + -- + -- Check make sure that register_a1 doesnt use the same clock as register_b2, + -- or if register_b1 is unregistered + -- If so, then update mult_b_pre2 with mult_b_pre1 to be used for register_b2 + -- + -- if nothing happens (ie. clock/clear is not triggered), + -- then update mult_b_pre2 with the current value of mult_b + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_b1 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b1 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b1 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b1 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_b1 = "UNREGISTERED"))) then + mult_b ((2)*int_width_b-1 downto (int_width_b)) <= (others => '0'); + mult_b_pre2 ((2)*int_width_b-1 downto (int_width_b)) := (others => '0'); + elsif (((input_register_b1 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_b1 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_b1 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_b1 = "CLOCK3") and rising_edge(clock3)) or + (input_register_b1 = "UNREGISTERED")) then + if (((input_register_b1 = "CLOCK0") and (ena0 = '1')) or + ((input_register_b1 = "CLOCK1") and (ena1 = '1')) or + ((input_register_b1 = "CLOCK2") and (ena2 = '1')) or + ((input_register_b1 = "CLOCK3") and (ena3 = '1')) or + (input_register_b1 = "UNREGISTERED")) then + mult_b ((2)*int_width_b-1 downto (int_width_b)) <= mult_b_pre1 ((2)*int_width_b-1 downto int_width_b); + if ((not(input_register_b1 = input_register_b2)) or (input_register_b1 = "UNREGISTERED")) then + mult_b_pre2 ((2)*int_width_b-1 downto (int_width_b)) := mult_b_pre1 ((2)*int_width_b-1 downto int_width_b); + end if; + end if; + else + mult_b_pre2 ((2)*int_width_b-1 downto (int_width_b)) := tmp_mult_b ((2)*int_width_b-1 downto (int_width_b)); + end if; + + + -- ----------------- + -- INPUT_REGISTER_B2 + -- ----------------- + + -- set the initial value for mult_b_pre2 from datab_int if input source is from datab + -- otherwise, load it from the mult_b_pre2 that stored the previous value from register_b1 + if (input_source_b2 = "DATAB") then + if (input_source_b0 = "LOOPBACK") then + mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)) := datab_int ((2*int_width_b) -1 downto int_width_b); + else + mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)) := datab_int ((3)*int_width_b-1 downto (2*int_width_b)); + end if; + elsif (input_source_b2 = "SCANB") then + if (mult2_source_scanin_en = '1') then + mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)) := datab_int ((3)*int_width_b-1 downto (2*int_width_b)); + else + mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)) := mult_b_pre2 ((2)*int_width_b-1 downto (int_width_b)); + end if; + else + if (sourceb_wire(2) = '1') then + mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)) := mult_b_pre2 ((2)*int_width_b-1 downto (int_width_b)); + else + mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)) := datab_int ((3)*int_width_b-1 downto (2*int_width_b)); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_b and mult_b_pre3 (this is the next variable to be used by register_b3) + -- whenever clear signal is triggered + -- + -- If clock is triggered or register is not used, assign mult_b to mult_b_pre2 + -- + -- Check make sure that register_b2 doesnt use the same clock as register_b3, + -- or if register_b2 is unregistered + -- If so, then update mult_b_pre3 with mult_b_pre2 to be used for register_b3 + -- + -- if nothing happens (ie. clock/clear is not triggered), + -- then update mult_b_pre3 with the current value of mult_b + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_b2 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b2 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b2 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b2 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_b2 = "UNREGISTERED"))) then + mult_b ((3)*int_width_b-1 downto (2*int_width_b)) <= (others => '0'); + mult_b_pre3 ((3)*int_width_b-1 downto (2*int_width_b)) := (others => '0'); + elsif (((input_register_b2 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_b2 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_b2 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_b2 = "CLOCK3") and rising_edge(clock3)) or + (input_register_b2 = "UNREGISTERED")) then + if (((input_register_b2 = "CLOCK0") and (ena0 = '1')) or + ((input_register_b2 = "CLOCK1") and (ena1 = '1')) or + ((input_register_b2 = "CLOCK2") and (ena2 = '1')) or + ((input_register_b2 = "CLOCK3") and (ena3 = '1')) or + (input_register_b2 = "UNREGISTERED")) then + mult_b ((3)*int_width_b-1 downto (2*int_width_b)) <= mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)); + if ((not(input_register_b2 = input_register_b3)) or (input_register_b2 = "UNREGISTERED")) then + mult_b_pre3 ((3)*int_width_b-1 downto (2*int_width_b)) := mult_b_pre2 ((3)*int_width_b-1 downto (2*int_width_b)); + end if; + end if; + else + mult_b_pre3 ((3)*int_width_b-1 downto (2*int_width_b)) := tmp_mult_b ((3)*int_width_b-1 downto (2*int_width_b)); + end if; + + + -- ----------------- + -- INPUT_REGISTER_B3 + -- ----------------- + + -- set the initial value for mult_b_pre3 from datab_int if input source is from datab + -- otherwise, load it from the mult_b_pre3 that stored the previous value from register_b2 + if (input_source_b3 = "DATAB") then + if (input_source_b0 = "LOOPBACK") then + mult_b_pre3 ((4)*int_width_b-1 downto (3*int_width_b)) := datab_int ((3)*int_width_b-1 downto (2*int_width_b)); + else + mult_b_pre3 ((4)*int_width_b-1 downto (3*int_width_b)) := datab_int ((4)*int_width_b-1 downto (3*int_width_b)); + end if; + elsif (input_source_b3 = "SCANB") then + if (mult3_source_scanin_en = '1') then + mult_b_pre3 ((4)*int_width_b-1 downto (3*int_width_b)) := datab_int ((4)*int_width_b-1 downto (3*int_width_b)); + else + mult_b_pre3 ((4)*int_width_b-1 downto (3*int_width_b)) := mult_b_pre3 ((3)*int_width_b-1 downto (2*int_width_b)); + end if; + else + if (sourceb_wire(3) = '1') then + mult_b_pre3 ((4)*int_width_b-1 downto (3*int_width_b)) := mult_b_pre3 ((3)*int_width_b-1 downto (2*int_width_b)); + else + mult_b_pre3 ((4)*int_width_b-1 downto (3*int_width_b)) := datab_int ((4)*int_width_b-1 downto (3*int_width_b)); + end if; + end if; + + -- ----------------------------------------------------------------------------------- + -- Clears mult_b whenever clear signal is triggered + -- If clock is triggered or register is not used, assign mult_b to mult_b_pre3 + -- ----------------------------------------------------------------------------------- + if ((((input_aclr_b3 = "ACLR0") and (aclr0 = '1')) or + ((input_aclr_b3 = "ACLR1") and (aclr1 = '1')) or + ((input_aclr_b3 = "ACLR2") and (aclr2 = '1')) or + ((input_aclr_b3 = "ACLR3") and (aclr3 = '1'))) and + (not (input_register_b3 = "UNREGISTERED"))) then + mult_b ((4)*int_width_b-1 downto (3*int_width_b)) <= (others => '0'); + elsif (((input_register_b3 = "CLOCK0") and rising_edge(clock0)) or + ((input_register_b3 = "CLOCK1") and rising_edge(clock1)) or + ((input_register_b3 = "CLOCK2") and rising_edge(clock2)) or + ((input_register_b3 = "CLOCK3") and rising_edge(clock3)) or + (input_register_b3 = "UNREGISTERED")) then + if (((input_register_b3 = "CLOCK0") and (ena0 = '1')) or + ((input_register_b3 = "CLOCK1") and (ena1 = '1')) or + ((input_register_b3 = "CLOCK2") and (ena2 = '1')) or + ((input_register_b3 = "CLOCK3") and (ena3 = '1')) or + (input_register_b3 = "UNREGISTERED")) then + mult_b ((4)*int_width_b-1 downto (3*int_width_b)) <= mult_b_pre3 ((4)*int_width_b-1 downto (3*int_width_b)); + end if; + end if; + + end process; + + -- ----------------------------------------------------------------------- + -- This process block performs the rounding and saturation control signal + -- setting + -- ----------------------------------------------------------------------- + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set mult01_round_wire) + -- The signal registered is mult01_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if mult01_round_register + -- is unregistered and mult01_round changes value + -- --------------------------------------------------------------------------------- + + G9: if (mult01_round_register = "UNREGISTERED") generate + mult01_round_wire <= mult01_round; + end generate G9; + + IFG41: if (mult01_round_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, mult01_round) + begin + if (((mult01_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult01_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult01_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult01_round_aclr= "ACLR3") and (aclr3 = '1'))) then + mult01_round_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + mult01_round_wire <= mult01_round; + end if; + end if; + end process; + end generate IFG41; + + IFG42: if (mult01_round_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, mult01_round) + begin + if (((mult01_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult01_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult01_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult01_round_aclr= "ACLR3") and (aclr3 = '1'))) then + mult01_round_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + mult01_round_wire <= mult01_round; + end if; + end if; + end process; + end generate IFG42; + + IFG43: if (mult01_round_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, mult01_round) + begin + if (((mult01_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult01_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult01_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult01_round_aclr= "ACLR3") and (aclr3 = '1'))) then + mult01_round_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + mult01_round_wire <= mult01_round; + end if; + end if; + end process; + end generate IFG43; + + IFG44: if (mult01_round_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, mult01_round) + begin + if (((mult01_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult01_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult01_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult01_round_aclr = "ACLR3") and (aclr3 = '1'))) then + mult01_round_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + mult01_round_wire <= mult01_round; + end if; + end if; + end process; + end generate IFG44; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set mult01_saturate_wire) + -- The signal registered is mult01_saturation + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if mult01_saturate_register + -- is unregistered and mult01_saturation changes value + -- --------------------------------------------------------------------------------- + + G10: if (mult01_saturation_register = "UNREGISTERED") generate + mult01_saturate_wire <= mult01_saturation; + end generate G10; + + IFG45: if (mult01_saturation_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, mult01_saturation) + begin + if (((mult01_saturation_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult01_saturation_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult01_saturation_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult01_saturation_aclr= "ACLR3") and (aclr3 = '1'))) then + mult01_saturate_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + mult01_saturate_wire <= mult01_saturation; + end if; + end if; + end process; + end generate IFG45; + + IFG46: if (mult01_saturation_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, mult01_saturation) + begin + if (((mult01_saturation_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult01_saturation_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult01_saturation_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult01_saturation_aclr= "ACLR3") and (aclr3 = '1'))) then + mult01_saturate_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + mult01_saturate_wire <= mult01_saturation; + end if; + end if; + end process; + end generate IFG46; + + IFG47: if (mult01_saturation_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, mult01_saturation) + begin + if (((mult01_saturation_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult01_saturation_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult01_saturation_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult01_saturation_aclr= "ACLR3") and (aclr3 = '1'))) then + mult01_saturate_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + mult01_saturate_wire <= mult01_saturation; + end if; + end if; + end process; + end generate IFG47; + + IFG48: if (mult01_saturation_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, mult01_saturation) + begin + if (((mult01_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult01_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult01_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult01_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + mult01_saturate_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + mult01_saturate_wire <= mult01_saturation; + end if; + end if; + end process; + end generate IFG48; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set mult23_round_wire) + -- The signal registered is mult23_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if mult23_round_register + -- is unregistered and mult23_round changes value + -- --------------------------------------------------------------------------------- + + G11: if (mult23_round_register = "UNREGISTERED") generate + mult23_round_wire <= mult23_round; + end generate G11; + + IFG49: if (mult23_round_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, mult23_round) + begin + if (((mult23_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult23_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult23_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult23_round_aclr= "ACLR3") and (aclr3 = '1'))) then + mult23_round_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + mult23_round_wire <= mult23_round; + end if; + end if; + end process; + end generate IFG49; + + IFG50: if (mult23_round_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, mult23_round) + begin + if (((mult23_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult23_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult23_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult23_round_aclr= "ACLR3") and (aclr3 = '1'))) then + mult23_round_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + mult23_round_wire <= mult23_round; + end if; + end if; + end process; + end generate IFG50; + + IFG51: if (mult23_round_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, mult23_round) + begin + if (((mult23_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult23_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult23_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult23_round_aclr= "ACLR3") and (aclr3 = '1'))) then + mult23_round_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + mult23_round_wire <= mult23_round; + end if; + end if; + end process; + end generate IFG51; + + IFG52: if (mult23_round_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, mult23_round) + begin + if (((mult23_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult23_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult23_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult23_round_aclr = "ACLR3") and (aclr3 = '1'))) then + mult23_round_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + mult23_round_wire <= mult23_round; + end if; + end if; + end process; + end generate IFG52; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set mult23_saturate_wire) + -- The signal registered is mult23_saturation + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if mult23_saturate_register + -- is unregistered and mult23_saturation changes value + -- --------------------------------------------------------------------------------- + + G12: if (mult23_saturation_register = "UNREGISTERED") generate + mult23_saturate_wire <= mult23_saturation; + end generate G12; + + IFG53: if (mult23_saturation_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, mult23_saturation) + begin + if (((mult23_saturation_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult23_saturation_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult23_saturation_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult23_saturation_aclr= "ACLR3") and (aclr3 = '1'))) then + mult23_saturate_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + mult23_saturate_wire <= mult23_saturation; + end if; + end if; + end process; + end generate IFG53; + + IFG54: if (mult23_saturation_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, mult23_saturation) + begin + if (((mult23_saturation_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult23_saturation_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult23_saturation_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult23_saturation_aclr= "ACLR3") and (aclr3 = '1'))) then + mult23_saturate_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + mult23_saturate_wire <= mult23_saturation; + end if; + end if; + end process; + end generate IFG54; + + IFG55: if (mult23_saturation_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, mult23_saturation) + begin + if (((mult23_saturation_aclr= "ACLR0") and (aclr0 = '1')) or + ((mult23_saturation_aclr= "ACLR1") and (aclr1 = '1')) or + ((mult23_saturation_aclr= "ACLR2") and (aclr2 = '1')) or + ((mult23_saturation_aclr= "ACLR3") and (aclr3 = '1'))) then + mult23_saturate_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + mult23_saturate_wire <= mult23_saturation; + end if; + end if; + end process; + end generate IFG55; + + IFG56: if (mult23_saturation_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, mult23_saturation) + begin + if (((mult23_saturation_aclr = "ACLR0") and (aclr0 = '1')) or + ((mult23_saturation_aclr = "ACLR1") and (aclr1 = '1')) or + ((mult23_saturation_aclr = "ACLR2") and (aclr2 = '1')) or + ((mult23_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then + mult23_saturate_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + mult23_saturate_wire <= mult23_saturation; + end if; + end if; + end process; + end generate IFG56; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addnsub1_round_wire) + -- The signal registered is addnsub1_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub1_round_register + -- is unregistered and addnsub1_round changes value + -- --------------------------------------------------------------------------------- + + G13: if (addnsub1_round_register = "UNREGISTERED") generate + addnsub1_round_wire <= addnsub1_round; + end generate G13; + + IFG57: if (addnsub1_round_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addnsub1_round) + begin + if (((addnsub1_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addnsub1_round_wire <= addnsub1_round; + end if; + end if; + end process; + end generate IFG57; + + IFG58: if (addnsub1_round_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addnsub1_round) + begin + if (((addnsub1_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addnsub1_round_wire <= addnsub1_round; + end if; + end if; + end process; + end generate IFG58; + + IFG59: if (addnsub1_round_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addnsub1_round) + begin + if (((addnsub1_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addnsub1_round_wire <= addnsub1_round; + end if; + end if; + end process; + end generate IFG59; + + IFG60: if (addnsub1_round_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addnsub1_round) + begin + if (((addnsub1_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_aclr = "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addnsub1_round_wire <= addnsub1_round; + end if; + end if; + end process; + end generate IFG60; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addnsub1_round_pipe_wire) + -- The signal registered is addnsub1_round_wire + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub1_round_pipe_register + -- is unregistered and addnsub1_round_wire changes value + -- --------------------------------------------------------------------------------- + + G14: if (addnsub1_round_pipeline_register = "UNREGISTERED") generate + addnsub1_round_pipe_wire <= addnsub1_round_wire; + end generate G14; + + IFG61: if (addnsub1_round_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addnsub1_round_wire) + begin + if (((addnsub1_round_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_pipe_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addnsub1_round_pipe_wire <= addnsub1_round_wire; + end if; + end if; + end process; + end generate IFG61; + + IFG62: if (addnsub1_round_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addnsub1_round_wire) + begin + if (((addnsub1_round_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_pipe_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addnsub1_round_pipe_wire <= addnsub1_round_wire; + end if; + end if; + end process; + end generate IFG62; + + IFG63: if (addnsub1_round_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addnsub1_round_wire) + begin + if (((addnsub1_round_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_pipe_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addnsub1_round_pipe_wire <= addnsub1_round_wire; + end if; + end if; + end process; + end generate IFG63; + + IFG64: if (addnsub1_round_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addnsub1_round_wire) + begin + if (((addnsub1_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((addnsub1_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((addnsub1_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((addnsub1_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + addnsub1_round_pipe_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addnsub1_round_pipe_wire <= addnsub1_round_wire; + end if; + end if; + end process; + end generate IFG64; + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addnsub3_round_wire) + -- The signal registered is addnsub3_round + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub3_round_register + -- is unregistered and addnsub3_round changes value + -- --------------------------------------------------------------------------------- + + G15: if (addnsub3_round_register = "UNREGISTERED") generate + addnsub3_round_wire <= addnsub3_round; + end generate G15; + + IFG65: if (addnsub3_round_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addnsub3_round) + begin + if (((addnsub3_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addnsub3_round_wire <= addnsub3_round; + end if; + end if; + end process; + end generate IFG65; + + IFG66: if (addnsub3_round_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addnsub3_round) + begin + if (((addnsub3_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addnsub3_round_wire <= addnsub3_round; + end if; + end if; + end process; + end generate IFG66; + + IFG67: if (addnsub3_round_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addnsub3_round) + begin + if (((addnsub3_round_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addnsub3_round_wire <= addnsub3_round; + end if; + end if; + end process; + end generate IFG67; + + IFG68: if (addnsub3_round_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addnsub3_round) + begin + if (((addnsub3_round_aclr = "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_aclr = "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_aclr = "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_aclr = "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addnsub3_round_wire <= addnsub3_round; + end if; + end if; + end process; + end generate IFG68; + + + -- --------------------------------------------------------------------------------- + -- This statement contains 1 register and a combinatorial block (to set addnsub3_round_pipe_wire) + -- The signal registered is addnsub3_round_wire + -- + -- The register has an asynchronous clear and a clock enable signal + -- NOTE: the combinatorial block is trigged if addnsub3_round_pipeline_register + -- is unregistered and addnsub3_round_wire changes value + -- --------------------------------------------------------------------------------- + G16: if (addnsub3_round_pipeline_register = "UNREGISTERED") generate + addnsub3_round_pipe_wire <= addnsub3_round_wire; + end generate G16; + + IFG69: if (addnsub3_round_pipeline_register = "CLOCK0") generate + process (clock0, aclr0, aclr1, aclr2, aclr3, addnsub3_round_wire) + begin + if (((addnsub3_round_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_pipe_wire <= '0'; + elsif rising_edge(clock0) then + if ((ena0 ='1')) then + addnsub3_round_pipe_wire <= addnsub3_round_wire; + end if; + end if; + end process; + end generate IFG69; + + IFG70: if (addnsub3_round_pipeline_register = "CLOCK1") generate + process (clock1, aclr0, aclr1, aclr2, aclr3, addnsub3_round_wire) + begin + if (((addnsub3_round_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_pipe_wire <= '0'; + elsif rising_edge(clock1) then + if ((ena1 ='1')) then + addnsub3_round_pipe_wire <= addnsub3_round_wire; + end if; + end if; + end process; + end generate IFG70; + + IFG71: if (addnsub3_round_pipeline_register = "CLOCK2") generate + process (clock2, aclr0, aclr1, aclr2, aclr3, addnsub3_round_wire) + begin + if (((addnsub3_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_pipe_wire <= '0'; + elsif rising_edge(clock2) then + if ((ena2 ='1')) then + addnsub3_round_pipe_wire <= addnsub3_round_wire; + end if; + end if; + end process; + end generate IFG71; + + IFG72: if (addnsub3_round_pipeline_register = "CLOCK3") generate + process (clock3, aclr0, aclr1, aclr2, aclr3, addnsub3_round_wire) + begin + if (((addnsub3_round_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or + ((addnsub3_round_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then + addnsub3_round_pipe_wire <= '0'; + elsif rising_edge(clock3) then + if ((ena3 ='1')) then + addnsub3_round_pipe_wire <= addnsub3_round_wire; + end if; + end if; + end process; + end generate IFG72; + + + -- ----------------------------------------------------------------------- + -- This process block performs the multiplication of the two input numbers + -- ----------------------------------------------------------------------- + process (clock0, clock1, clock2, clock3, mult_aclr, mult_a, mult_b, sign_a_reg, sign_b_reg, + mult01_round_wire, mult01_saturate_wire, mult23_round_wire, mult23_saturate_wire, mult_clock, is_reg, signa, signb) + variable mult_a_int : std_logic_vector (int_width_a -1 downto 0); + variable mult_b_int : std_logic_vector (int_width_b -1 downto 0); + variable mult_round_out : std_logic_vector (int_width_a + int_width_b - 1 downto 0) := (others => '0'); + variable mult_result : std_logic_vector (int_width_a + int_width_b - 1 downto 0) := (others => '0'); + variable mult_saturate_overflow : std_logic := '0'; + variable mult_saturate_out : std_logic_vector (int_width_a + int_width_b - 1 downto 0) := (others => '0'); + variable neg_a : std_logic := '0'; + variable neg_b : std_logic := '0'; + variable temp_mult_int : std_logic_vector ((int_width_a + int_width_b)-1 downto 0); + variable mux_clock : std_logic; + variable check_clock_out : string (1 to 6); + variable x : integer; + variable mult_round_bits : integer; + variable zero_pad : std_logic := '0'; + variable is_rep_a_sign : std_logic := '1'; + variable is_rep_b_sign : std_logic := '1'; + begin + + if (((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or (sign_a_reg = '1'))) or + ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED"))) then + is_rep_a_sign := '1'; + else + is_rep_a_sign := '0'; + end if; + + if (((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or (sign_b_reg = '1'))) or + ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED"))) then + is_rep_b_sign := '1'; + else + is_rep_b_sign := '0'; + end if; + + for i in 0 to (number_of_multipliers -1) loop + x := i; + + if (i > 3) then + x := 3; + end if; + + mux_clock := mult_clock (x); + check_clock_out := check_clock (x); + + if ((not stratixiii_block) and + ((is_reg (x) = '1') and (mult_aclr (x) = '1'))) then + mult_res ( ((i+1)*(int_width_a + int_width_b)) - 1 downto (i*(int_width_a + int_width_b))) <= (others => '0'); + mult_is_saturated(x) <= '0'; + elsif ((not stratixiii_block) and + (((check_clock_out = "CLOCK0") and rising_edge(clock0)) or + ((check_clock_out = "CLOCK1") and rising_edge(clock1)) or + ((check_clock_out = "CLOCK2") and rising_edge(clock2)) or + ((check_clock_out = "CLOCK3") and rising_edge(clock3)) or + (is_reg (x) = '0'))) or + (stratixiii_block) then + + if ((not stratixiii_block) and + (((check_clock_out = "CLOCK0") and (ena0 = '1')) or + ((check_clock_out = "CLOCK1") and (ena1 = '1')) or + ((check_clock_out = "CLOCK2") and (ena2 = '1')) or + ((check_clock_out = "CLOCK3") and (ena3 = '1')) or + is_reg (x) = '0')) or + (stratixiii_block) then + neg_a := '0'; + neg_b := '0'; + + -- check if mult_a is to be interpreted as negative + if (is_rep_a_sign = '1') then + neg_a := mult_a ( (i+1)*int_width_a-1); + end if; + + -- check if mult_b is to be interpreted as negative + if (is_rep_b_sign = '1') then + if (input_source_b0 = "LOOPBACK" and i=1) then + neg_b := mult_b ( (i+1)*int_width_b-1 );-- + (int_width_b - width_b)); + else + neg_b := mult_b ( (i+1)*int_width_b-1); + end if; + end if; + + -- perform 2's complement if mult_a is negative + if (neg_a ='1') then + mult_a_int := unsigned (not mult_a ( (i+1)*int_width_a-1 downto (i*int_width_a))) + 1; + else + mult_a_int := mult_a ( (i+1)*int_width_a-1 downto (i*int_width_a)); + end if; + + -- perform 2's complement if mult_b is negative + if (neg_b ='1') then + if(input_source_b0 = "LOOPBACK" and i=1) then + mult_b_int(width_b - 1 downto 0) := unsigned (not mult_b ( (i+1)*int_width_b-1 downto (i*int_width_b + (int_width_b - width_b)))) + 1; + else + mult_b_int := unsigned (not mult_b ( (i+1)*int_width_b-1 downto (i*int_width_b))) + 1; + end if; + else + if(input_source_b0 = "LOOPBACK" and i=1) then + mult_b_int := mult_b ( (i+1)*int_width_b-1 + (int_width_b - width_b) downto (i*int_width_b + (int_width_b - width_b))); + else + mult_b_int := mult_b ( (i+1)*int_width_b-1 downto (i*int_width_b)); + end if; + end if; + -- perform multiplication + temp_mult_int := unsigned (temp_mult_zero) + unsigned(mult_a_int) * unsigned(mult_b_int); + + -- determining if the result should be a negative number + -- based on the 2 input numbers + if ((neg_a xor neg_b) = '1') then + temp_mult_int := unsigned(temp_mult_zero) - unsigned(temp_mult_int); + end if; + + if (stratixii_block) then + -- ------------------------------------------------------- + -- Stratix II Rounding support + -- This block basically carries out the rounding for the + -- temp_mult_int. The equation to get the mult_round_out is + -- obtained from the Stratix II Mac FFD which is below: + -- round_adder_constant = (1 << (wfraction - wfraction_round - 1)) + -- roundout[] = datain[] + round_adder_constant + -- For Stratix II rounding, we round up the bits to 15 bits + -- or in another word wfraction_round = 15. The sign bits would be 2 bits + -- -------------------------------------------------------- + + if ((((x = 0) or (x = 1)) and ((multiplier01_rounding = "YES") or + ((multiplier01_rounding = "VARIABLE") and (mult01_round_wire = '1')))) or + (((x = 2) or (x = 3)) and ((multiplier23_rounding = "YES") or + ((multiplier23_rounding = "VARIABLE") and (mult23_round_wire = '1'))))) + then + -- Here the value 17 is from the 2 bits of sign and the rounding for 15 bits + mult_round_bits := (int_width_a + int_width_b) - 17; + mult_round_out := unsigned (temp_mult_int) + ( 2 ** (mult_round_bits - 1)); + else + mult_round_out := temp_mult_int; + end if; + + -- ------------------------------------------------------- + -- Stratix II Saturation support + -- This carries out the saturation for mult_round_out. + -- The equation to get the saturated result is obtained + -- from Stratix II MAC FFD which is below: + -- satoverflow = 1 if sign bit is different + -- satvalue[wtotal-1 : wfraction] = roundout[wtotal-1] + -- satvalue[wfraction-1 : 0] = !roundout[wtotal-1] + -- ------------------------------------------------------- + + if ((((x = 0) or (x = 1)) and ((multiplier01_saturation = "YES") or + (( multiplier01_saturation = "VARIABLE") and (mult01_saturate_wire = '1')))) or + (((x = 2) or (x = 3)) and ((multiplier23_saturation = "YES") or + (( multiplier23_saturation = "VARIABLE") and (mult23_saturate_wire = '1'))))) + then + mult_saturate_overflow := (not mult_round_out(int_width_a + int_width_b - 1)) and (mult_round_out(int_width_a + int_width_b - 2)); + + if (mult_saturate_overflow = '0') then + mult_saturate_out := mult_round_out; + mult_is_saturated(x) <= mult_round_out(0); + else + -- We are doing the Q2.31 saturation, thus there is a bit + -- insertion over here + for i in (int_width_a + int_width_b - 1) downto (int_width_a + int_width_b - 2) loop + mult_saturate_out(i) := mult_round_out(int_width_a + int_width_b - 1); + end loop; + + for i in (int_width_a + int_width_b - 3) downto 3 loop + mult_saturate_out(i) := not mult_round_out(int_width_a + int_width_b - 1); + end loop; + + mult_saturate_out(2 downto 0) := mult_round_out(2 downto 0); + mult_is_saturated(x) <= mult_saturate_overflow; + end if; + else + mult_is_saturated(x) <= mult_saturate_overflow; + mult_saturate_out := mult_round_out; + end if; + + if ((((x = 0) or (x = 1)) and ((multiplier01_rounding = "YES") or + (( multiplier01_rounding = "VARIABLE") and (mult01_round_wire = '1')))) or + (((x = 2) or (x = 3)) and ((multiplier23_rounding = "YES") or + (( multiplier23_rounding = "VARIABLE") and (mult23_round_wire = '1'))))) + then + mult_result := mult_saturate_out; + + for i in (mult_round_bits - 1) downto 0 loop + mult_result(i) := '0'; + end loop; + + else + mult_result := mult_saturate_out; + end if; + else + mult_result := temp_mult_int; + end if; + + mult_res ( ((i+1)*(int_width_a + int_width_b)) - 1 downto (i*(int_width_a + int_width_b)) ) <= mult_result; + end if; + + end if; + end loop; + end process; + + -- ----------------------------------------------------------------- + -- This is the main block that performs the addition and subtraction + -- ----------------------------------------------------------------- + IFGFAM0: if (not stratixiii_block) generate + process (clock0, clock1, clock2, clock3, + aclr0, aclr1, aclr2, aclr3, + mult_res, sign_a_reg, sign_b_reg, sign_a_pipe, sign_b_pipe, + addsub_pipe1, addsub_pipe3, addsub_reg1, addsub_reg3, addnsub1_round_pipe_wire, + addnsub3_round_pipe_wire, mult_is_saturated) + variable head_result_int : integer := 0; + variable do_add : boolean; + variable asign : boolean; + variable bsign : boolean; + variable temp_sum : std_logic_vector (int_width_a + int_width_b + int_width_result downto 0) := (others => '0'); + variable mult_res_temp : std_logic_vector ((int_width_a + int_width_b - 1) downto 0); + variable mult_res_ext : std_logic_vector (int_width_result-1 downto 0); + variable adder_round_bits: integer; + variable adder_result : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable adder1_result : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable adder3_result : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable adder_final_out : std_logic_vector (2*int_width_result - 1 downto 0) := (others => '0'); + variable adder_round_out : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable is_rep_a_sign : boolean; + variable is_rep_b_sign : boolean; + variable is_rep_a_pipe_sign : boolean; + variable is_rep_b_pipe_sign : boolean; + variable is_adder1_add : boolean; + variable is_adder3_add : boolean; + variable is_adder1_pipe_add : boolean; + variable is_adder3_pipe_add : boolean; + variable result_temp : std_logic_vector (width_result - 1 downto 0) := (others => '0'); + variable result_ext : std_logic_vector (width_result - 1 downto 0) := (others => '0'); + variable result_pipe : pipeline_accum := (others => (others => '0')); + + begin + + if ((((output_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_aclr = "ACLR3") and (aclr3 = '1'))) and + (not (output_register = "UNREGISTERED"))) then + temp_sum := (others => '0'); + result_pipe := (others => (others => '0')); + result <= (others => '0'); + mult_is_saturated_pipe <= (others => '0'); + + elsif (((output_register = "CLOCK0") and rising_edge(clock0) and (ena0 = '1')) or + ((output_register = "CLOCK1") and rising_edge(clock1) and (ena1 = '1')) or + ((output_register = "CLOCK2") and rising_edge(clock2) and (ena2 = '1')) or + ((output_register = "CLOCK3") and rising_edge(clock3) and (ena3 = '1')) or + (output_register = "UNREGISTERED")) then + if (((output_register = "CLOCK0") and (ena0 = '1')) or + ((output_register = "CLOCK1") and (ena1 = '1')) or + ((output_register = "CLOCK2") and (ena2 = '1')) or + ((output_register = "CLOCK3") and (ena3 = '1')) or + (output_register = "UNREGISTERED")) then + temp_sum := (others => '0'); + + is_rep_a_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_reg = '1'))) or ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_b_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_reg = '1'))) or ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_rep_a_pipe_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_pipe = '1'))) or ((port_signa = "PORT_USED") and (sign_a_pipe = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_b_pipe_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_pipe = '1'))) or ((port_signb = "PORT_USED") and (sign_b_pipe = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_adder1_add := ((port_addnsub1 = "PORT_CONNECTIVITY") and (((multiplier1_direction = "ADD") and (addnsub1 = 'Z')) or + (addsub_reg1 = '1'))) or ((port_addnsub1 = "PORT_USED") and (addsub_reg1 = '1')) or + ((port_addnsub1 = "PORT_UNUSED") and (multiplier1_direction = "ADD")); + + is_adder3_add := ((port_addnsub3 = "PORT_CONNECTIVITY") and (((multiplier3_direction = "ADD") and (addnsub3 = 'Z')) or + (addsub_reg3 = '1'))) or ((port_addnsub3 = "PORT_USED") and (addsub_reg3 = '1')) or + ((port_addnsub3 = "PORT_UNUSED") and (multiplier3_direction = "ADD")); + + + is_adder1_pipe_add := ((port_addnsub1 = "PORT_CONNECTIVITY") and (((multiplier1_direction = "ADD") and (addnsub1 = 'Z')) or + (addsub_pipe1 = '1'))) or ((port_addnsub1 = "PORT_USED") and (addsub_pipe1 = '1')) or + ((port_addnsub1 = "PORT_UNUSED") and (multiplier1_direction = "ADD")); + + is_adder3_pipe_add := ((port_addnsub3 = "PORT_CONNECTIVITY") and (((multiplier3_direction = "ADD") and (addnsub3 = 'Z')) or + (addsub_pipe3 = '1'))) or ((port_addnsub3 = "PORT_USED") and (addsub_pipe3 = '1')) or + ((port_addnsub3 = "PORT_UNUSED") and (multiplier3_direction = "ADD")); + + + for i in 0 to (number_of_multipliers -1) loop + + -- use addsub_reg instead of addsub_pipe if + -- addnsub_multiplier_pipeline_register is unregistered + -- to determine the do_add flag + if ((addnsub_multiplier_pipeline_register1 = "UNREGISTERED") and + (addnsub_multiplier_pipeline_register3 = "UNREGISTERED"))then + if (((i = 1) and (is_adder1_add)) or + ((i = 3) and (is_adder3_add)) or + (i = 0) or + (i = 2) or + (i > 3)) then + do_add := true; + else + do_add := false; + end if; + elsif ((addnsub_multiplier_pipeline_register1 = "UNREGISTERED") and + (not (addnsub_multiplier_pipeline_register3 = "UNREGISTERED")))then + if (((i = 1) and (is_adder1_add)) or + ((i = 3) and (is_adder3_pipe_add)) or + (i = 0) or + (i = 2) or + (i > 3)) then + do_add := true; + else + do_add := false; + end if; + elsif ((not (addnsub_multiplier_pipeline_register1 = "UNREGISTERED")) and + (addnsub_multiplier_pipeline_register3 = "UNREGISTERED")) then + if (((i = 1) and (is_adder1_pipe_add)) or + ((i = 3) and (is_adder3_add)) or + (i = 0) or + (i = 2) or + (i > 3)) then + do_add := true; + else + do_add := false; + end if; + else + if (((i = 1) and (is_adder1_pipe_add)) or + ((i = 3) and (is_adder3_pipe_add)) or + (i = 0) or + (i = 2) or + (i > 3)) then + do_add := true; + else + do_add := false; + end if; + end if; + + mult_res_temp := mult_res( ((i+1)*(int_width_a + int_width_b) - 1) downto (i*(int_width_a + int_width_b))); + + -- Use sign_a_reg instead of sign_a_pipe when + -- signed_pipeline_register_a is unregistered + -- to set the asign flag + if (signed_pipeline_register_a = "UNREGISTERED") then + if (is_rep_a_sign) then + asign := true; + else + asign := false; + end if; + else + if (is_rep_a_pipe_sign) then + asign := true; + else + asign := false; + end if; + end if; + + -- Use sign_b_reg instead of sign_b_pipe when + -- signed_pipeline_register_b is unregistered + -- to set the bsign flag + if (signed_pipeline_register_b = "UNREGISTERED") then + if (is_rep_b_sign) then + bsign := true; + else + bsign := false; + end if; + else + if (is_rep_b_pipe_sign) then + bsign := true; + else + bsign := false; + end if; + end if; + + -- perform addition/subrtaction based on the do_add flag + if (do_add = true) then + if ((asign = true) or (bsign = true)) then + temp_sum := signed (temp_sum) + signed(mult_res_temp); + else + temp_sum := unsigned (temp_sum) + unsigned(mult_res_temp); + end if; + else + if ((asign = true) or (bsign = true)) then + temp_sum := signed (temp_sum) - signed(mult_res_temp); + else + temp_sum := unsigned (temp_sum) - unsigned(mult_res_temp); + end if; + end if; + + if (stratixii_block) then + -- ------------------------------------------------------- + -- Stratix II Rounding support + -- This block basically carries out the rounding for the + -- temp_sum. The equation to get the adder_round_out is + -- obtained from the Stratix II Mac FFD which is below: + -- round_adder_constant = (1 << (wfraction - wfraction_round - 1)) + -- roundout[] = datain[] + round_adder_constant + -- For Stratix II rounding, we round up the bits to 15 bits + -- or in another word wfraction_round = 15. + -- -------------------------------------------------------- + + if (((i = 1) and ((adder1_rounding = "YES") or + ((adder1_rounding = "VARIABLE") and (addnsub1_round_pipe_wire = '1')))) or + ((i = 2) and (number_of_multipliers = 3) and ((adder3_rounding = "YES") or + ((adder3_rounding = "VARIABLE") and (addnsub3_round_pipe_wire = '1')))) or + ((i = 3) and ((adder3_rounding = "YES") or + ((adder3_rounding = "VARIABLE") and (addnsub3_round_pipe_wire = '1'))))) + then + + -- Here the value 17 is from the 2 bits of sign and the rounding for 15 bits + + adder_round_bits := (int_width_a + int_width_b) - 17; + adder_round_out := signed (temp_sum(int_width_result downto 0)) + ( 2 ** (adder_round_bits - 1)); + + for j in (adder_round_bits - 1) downto 0 loop + adder_round_out(j) := '0'; + end loop; + + --adder_result := adder_round_out; + + if ((i=2) or (i=3)) then + for j in (int_width_result - 1) downto 0 loop + temp_sum(j) := adder_round_out(j); + end loop; + end if; + + else + adder_round_out := temp_sum(int_width_result downto 0); + + end if; + + if (i = 0) then + adder_result := adder_round_out; + end if; + + if (i = 1) then + adder1_result := adder_round_out; + adder_result := adder1_result; + temp_sum := (others => '0'); + end if; + + if ((i=2) or (i=3))then + adder3_result := adder_round_out; + if ((asign = true) or (bsign = true)) then + adder_result := signed (adder3_result) + signed(adder1_result); + else + adder_result := unsigned (adder3_result) + unsigned(adder1_result); + end if; + end if; + end if; + + if (not stratixii_block) then + adder_final_out(int_width_result - 1 downto 0) := temp_sum(int_width_result - 1 downto 0); + adder_final_out(2*int_width_result - 1 downto int_width_result) := (others => temp_sum(int_width_result -1)); + + else + adder_final_out(int_width_result - 1 downto 0) := adder_result(int_width_result - 1 downto 0); + adder_final_out(2*int_width_result - 1 downto int_width_result) := (others => adder_result(int_width_result)); + end if; + + end loop; -- for i in 0 to (number_of_multipliers -1) loop + + mult_is_saturated_pipe <= mult_is_saturated; + + if (extra_latency = 0) then + result_temp := adder_final_out((width_result - 1 + int_mult_diff_bit) downto int_mult_diff_bit); + + -- need to extend the MSB for cases where width_result is larger than width_a + width_b + + if ((number_of_multipliers = 1) and (width_result > width_a + width_b)) then + if ((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) then + for res_cnt in 1 to (width_result - width_a - width_b) loop + result_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b) loop + result_ext(width_result - res_cnt) := result_temp(width_a + width_b - 1); + end loop; + end if; + result_ext(width_a + width_b - 1 downto 0) := result_temp(width_a + width_b - 1 downto 0); + elsif ((number_of_multipliers = 2) and (width_result > width_a + width_b + 1)) then + if ((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) then + for res_cnt in 1 to (width_result - width_a - width_b - 1) loop + result_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b - 1) loop + result_ext(width_result - res_cnt) := result_temp(width_a + width_b); + end loop; + end if; + result_ext(width_a + width_b downto 0) := result_temp(width_a + width_b downto 0); + elsif ((number_of_multipliers > 2) and (width_result > width_a + width_b + 2)) then + if ((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) then + for res_cnt in 1 to (width_result - width_a - width_b - 2) loop + result_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b - 2) loop + result_ext(width_result - res_cnt) := result_temp(width_a + width_b + 1); + end loop; + end if; + result_ext(width_a + width_b + 1 downto 0) := result_temp(width_a + width_b + 1 downto 0); + else + result_ext(width_result - 1 downto 0) := result_temp(width_result - 1 downto 0); + end if; + + result <= result_ext; + + else + result_temp := adder_final_out((width_result - 1 + int_mult_diff_bit) downto int_mult_diff_bit); + + if ((number_of_multipliers = 1) and (width_result > width_a + width_b)) then + if ((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) then + for res_cnt in 1 to (width_result - width_a - width_b) loop + result_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b) loop + result_ext(width_result - res_cnt) := result_temp(width_a + width_b - 1); + end loop; + end if; + result_ext(width_a + width_b - 1 downto 0) := result_temp(width_a + width_b - 1 downto 0); + elsif ((number_of_multipliers = 2) and (width_result > width_a + width_b + 1)) then + if ((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) then + for res_cnt in 1 to (width_result - width_a - width_b - 1) loop + result_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b - 1) loop + result_ext(width_result - res_cnt) := result_temp(width_a + width_b); + end loop; + end if; + result_ext(width_a + width_b downto 0) := result_temp(width_a + width_b downto 0); + elsif ((number_of_multipliers > 2) and (width_result > width_a + width_b + 2)) then + if ((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) then + for res_cnt in 1 to (width_result - width_a - width_b - 2) loop + result_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b - 2) loop + result_ext(width_result - res_cnt) := result_temp(width_a + width_b + 1); + end loop; + end if; + result_ext(width_a + width_b + 1 downto 0) := result_temp(width_a + width_b + 1 downto 0); + else + result_ext(width_result - 1 downto 0) := result_temp(width_result - 1 downto 0); + end if; + + head_result_int := head_result; + result_pipe (head_result_int) := adder_final_out(width_result - 1 downto 0); + head_result_int := (head_result_int +1) mod (extra_latency + 1); + result <= result_pipe(head_result_int); + head_result <= head_result_int; + + end if; + end if; + end if; + end process; + end generate IFGFAM0; + + process (mult_is_saturated_pipe) + begin + -- We also need to update the multpilier saturated port. The reason we update it here + -- is that the signal whether the multiplier is saturated or not can appear the same + -- time as the adder result + for num_mult in 0 to (number_of_multipliers -1) loop + + if (num_mult = 0) then + if (port_mult0_is_saturated = "USED") then + mult0_is_saturated <= mult_is_saturated_pipe(num_mult); + end if; + elsif (num_mult = 1) then + if (port_mult1_is_saturated = "USED") then + mult1_is_saturated <= mult_is_saturated_pipe(num_mult); + end if; + elsif (num_mult = 2) then + if (port_mult2_is_saturated = "USED") then + mult2_is_saturated <= mult_is_saturated_pipe(num_mult); + end if; + elsif (num_mult = 3) then + if (port_mult3_is_saturated = "USED") then + mult3_is_saturated <= mult_is_saturated_pipe(num_mult); + end if; + else + assert false + report "Error: Not supported number of multipliers in saturation"; + end if; + + end loop; -- for i in 0 to (number_of_multipliers -1) loop + end process; + + -- The addition, subtraction and other functionality for Stratix III + IFGFAM1: if (stratixiii_block) generate + process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, + adder1_reg, adder3_reg, acc_feedback, acc_feedback_temp, + outround_pipe, outsat_pipe, + mult_res) + + variable asign : boolean; + variable bsign : boolean; + variable is_rep_a_sign : boolean; + variable is_rep_b_sign : boolean; + variable is_rep_a_pipe_sign : boolean; + variable is_rep_b_pipe_sign : boolean; + variable round_happen : boolean; + + variable adder1_sum : std_logic_vector (int_width_a + int_width_b + int_width_result downto 0) := (others => '0'); + variable adder3_sum : std_logic_vector (int_width_a + int_width_b + int_width_result downto 0) := (others => '0'); + variable mult_res_temp : std_logic_vector ((int_width_a + int_width_b - 1) downto 0); + variable mult_res_temp_int : std_logic_vector ((int_width_a + int_width_b + int_width_result) downto 0) := (others => '0'); + + variable stckbit_cnt : integer := 0; + variable rndbit_cnt : integer := 0; + variable sat_bit_cnt : integer := 0; + variable leadsat_bit_cnt : integer := 0; + variable trailsat_bit_cnt : integer := 0; + variable allsat_bit_cnt : integer := 0; + variable satbit_or_cnt : integer := 0; + variable overflow_status_bit_pos : integer :=0; + variable i : integer := 0; + variable stick_bits_or : std_logic := '0'; + variable overflow_status : std_logic := '0'; + variable sat_bits_or : std_logic := '0'; + + variable round_sat_in_result : std_logic_vector (int_width_result + int_width_a + int_width_b downto 0) := (others => '0'); + variable round_block_result : std_logic_vector (int_width_result + int_width_a + int_width_b downto 0) := (others => '0'); + variable sat_block_result : std_logic_vector (int_width_result + int_width_a + int_width_b downto 0) := (others => '0'); + variable output_result_temp : std_logic_vector (int_width_result downto 0) := (others => '0'); + + variable adder1_reg_temp : std_logic_vector (accum_width downto 0) := (others => '0'); + variable adder3_reg_temp : std_logic_vector (accum_width downto 0) := (others => '0'); + variable accum_res_temp : std_logic_vector (accum_width downto 0) := (others => '0'); + variable accum_overflow : std_logic := '0'; + variable acc_feedback_int : std_logic_vector (accum_width downto 0) := (others => '0'); + variable accum_res_int : std_logic_vector (accum_width downto 0) := (others => '0'); + variable and_sign_wire : std_logic := '0'; + variable or_sign_wire : std_logic := '0'; + variable accum_overflow_int : std_logic := '0'; + variable msb : std_logic := '0'; + variable unsigned_sub1_overflow : std_logic := '0'; + variable unsigned_sub3_overflow : std_logic := '0'; + + begin + -- determine whether dataa and datab are signed or unsigned numbers + is_rep_a_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_reg = '1'))) or ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_b_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_reg = '1'))) or ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_rep_a_pipe_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_pipe = '1'))) or ((port_signa = "PORT_USED") and (sign_a_pipe = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_b_pipe_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_pipe = '1'))) or ((port_signb = "PORT_USED") and (sign_b_pipe = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + -- Use sign_a_reg instead of sign_a_pipe when + -- signed_pipeline_register_a is unregistered + -- to set the asign flag + if (signed_pipeline_register_a = "UNREGISTERED") then + if (is_rep_a_sign) then + asign := true; + else + asign := false; + end if; + else + if (is_rep_a_pipe_sign) then + asign := true; + else + asign := false; + end if; + end if; + + -- Use sign_b_reg instead of sign_b_pipe when + -- signed_pipeline_register_b is unregistered + -- to set the bsign flag + if (signed_pipeline_register_b = "UNREGISTERED") then + if (is_rep_b_sign) then + bsign := true; + else + bsign := false; + end if; + else + if (is_rep_b_pipe_sign) then + bsign := true; + else + bsign := false; + end if; + end if; + + acc_feedback_int(accum_width - 1 downto 0) := acc_feedback_temp(accum_width - 1 downto 0); + + if ((((output_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_aclr = "ACLR3") and (aclr3 = '1'))) and + (not (output_register = "UNREGISTERED"))) then + accum_res <= (others => '0'); + accum_res_temp := (others => '0'); + acc_feedback_int := (others => '0'); + elsif (((output_register = "CLOCK0") and rising_edge (clock0) and (ena0 = '1')) or + ((output_register = "CLOCK1") and rising_edge (clock1) and (ena1 = '1')) or + ((output_register = "CLOCK2") and rising_edge (clock2) and (ena2 = '1')) or + ((output_register = "CLOCK3") and rising_edge (clock3) and (ena3 = '1')) or + (output_register = "UNREGISTERED")) then + end if; + + + -- model the registering of the 1st-level adder/subtractor results + -- note: For Stratix III, multiplier_register0 should be the same setting as + -- multiplier_register1, multiplier_register2 and multiplier_register3, so just use 1 parameter will do + if ((((multiplier_aclr0 = "ACLR0") and (aclr0 = '1')) or + ((multiplier_aclr0 = "ACLR1") and (aclr1 = '1')) or + ((multiplier_aclr0 = "ACLR2") and (aclr2 = '1')) or + ((multiplier_aclr0 = "ACLR3") and (aclr3 = '1'))) and + (not (multiplier_register0 = "UNREGISTERED"))) then + + adder1_sum := (others => '0'); + adder3_sum := (others => '0'); + adder1_reg <= (others => '0'); + adder3_reg <= (others => '0'); + + elsif (((multiplier_register0 = "CLOCK0") and rising_edge (clock0)) or + ((multiplier_register0 = "CLOCK1") and rising_edge (clock1)) or + ((multiplier_register0 = "CLOCK2") and rising_edge (clock2)) or + ((multiplier_register0 = "CLOCK3") and rising_edge (clock3)) or + (multiplier_register0 = "UNREGISTERED")) then + + if (((multiplier_register0 = "CLOCK0") and (ena0 = '1')) or + ((multiplier_register0 = "CLOCK1") and (ena1 = '1')) or + ((multiplier_register0 = "CLOCK2") and (ena2 = '1')) or + ((multiplier_register0 = "CLOCK3") and (ena3 = '1')) or + (multiplier_register0 = "UNREGISTERED")) then + + adder1_sum := (others => '0'); + adder3_sum := (others => '0'); + -- model the first level adder/subtractor + for i in 0 to (number_of_multipliers - 1) loop + + mult_res_temp := mult_res( ((i+1)*(int_width_a + int_width_b) - 1) downto (i*(int_width_a + int_width_b))); + mult_res_temp_int(int_width_a + int_width_b - 1 downto 0) := mult_res_temp; + + if ((is_rep_a_sign) or (is_rep_b_sign))then + mult_res_temp_int(int_width_result + int_width_a + int_width_b downto int_width_a + int_width_b) := (others => mult_res_temp_int(int_width_a + int_width_b - 1)); + else + mult_res_temp_int(int_width_result + int_width_a + int_width_b downto int_width_a + int_width_b) := (others => '0'); + end if; + -- perform 1st level addition/subtraction + if ((i= 0) or (i = 1)) then + if ((multiplier1_direction = "ADD") or (i=0)) then + if ((asign = true) or (bsign = true)) then + adder1_sum := signed (adder1_sum) + signed(mult_res_temp_int); + else + adder1_sum := unsigned (adder1_sum) + unsigned(mult_res_temp_int); + end if; + else -- subtract + if ((asign = true) or (bsign = true)) then + adder1_sum := signed (adder1_sum) - signed(mult_res_temp_int); + else + adder1_sum := unsigned (adder1_sum) - unsigned(mult_res_temp_int); + if(adder1_sum(int_width_a + int_width_b + int_width_result) = '1') then + unsigned_sub1_overflow := '1'; + else + unsigned_sub1_overflow := '0'; + end if; + end if; + end if; + else -- 3rd and 4th multiplier + if ((multiplier3_direction = "ADD") or (i=2)) then + if ((asign = true) or (bsign = true)) then + adder3_sum := signed (adder3_sum) + signed(mult_res_temp_int); + else + adder3_sum := unsigned (adder3_sum) + unsigned(mult_res_temp_int); + end if; + else -- subtract + if ((asign = true) or (bsign = true)) then + adder3_sum := signed (adder3_sum) - signed(mult_res_temp_int); + else + adder3_sum := unsigned (adder3_sum) - unsigned(mult_res_temp_int); + if(adder3_sum(int_width_a + int_width_b + int_width_result) = '1') then + unsigned_sub3_overflow := '1'; + else + unsigned_sub3_overflow := '0'; + end if; + end if; + end if; + end if; + end loop; + + -- assign the results to signals + adder1_reg <= adder1_sum (int_width_result + int_width_a + int_width_b downto 0); + adder3_reg <= adder3_sum (int_width_result + int_width_a + int_width_b downto 0); + unsigned_sub1_overflow_mult_reg <= unsigned_sub1_overflow; + unsigned_sub3_overflow_mult_reg <= unsigned_sub3_overflow; + end if; + end if; -- end 1st adder register stage + + -- extend width for adder1_reg, adder2_reg and acc_feedback to set accumulator overflow bit + if(accum_width < int_width_result + int_width_a + int_width_b + 1) then + adder1_reg_temp(accum_width - 1 downto 0) := adder1_reg(accum_width - 1 downto 0); + adder3_reg_temp(accum_width - 1 downto 0) := adder3_reg(accum_width - 1 downto 0); + else + adder1_reg_temp(int_width_result + int_width_a + int_width_b downto 0) := adder1_reg(int_width_result + int_width_a + int_width_b downto 0); + adder3_reg_temp(int_width_result + int_width_a + int_width_b downto 0) := adder3_reg(int_width_result + int_width_a + int_width_b downto 0); + if ((asign = true) or (bsign = true)) then + adder1_reg_temp(accum_width - 1 downto int_width_result + int_width_a + int_width_b + 1) := (others => adder1_reg(int_width_result + int_width_a + int_width_b)); + adder3_reg_temp(accum_width - 1 downto int_width_result + int_width_a + int_width_b + 1) := (others => adder3_reg(int_width_result + int_width_a + int_width_b)); + else + adder1_reg_temp(accum_width - 1 downto int_width_result + int_width_a + int_width_b + 1) := (others => '0'); + adder3_reg_temp(accum_width - 1 downto int_width_result + int_width_a + int_width_b + 1) := (others => '0'); + end if; + end if; + + if ((asign = true) or (bsign = true)) then + if(acc_feedback_int(accum_width - 1) = '1') then + acc_feedback_int(accum_width) := '1'; + else + acc_feedback_int(accum_width) := '0'; + end if; + if((adder1_reg_temp(accum_width - 1) = '1') and (accum_direction = "SUB")) then + adder1_reg_temp(accum_width) := '1'; + else + adder1_reg_temp(accum_width) := '0'; + end if; + else + acc_feedback_int(accum_width) := '0'; + end if; + + adder1_reg_temp(accum_width) := '0'; + adder3_reg_temp(accum_width) := '0'; + -- model the output register + if ((((output_aclr = "ACLR0") and (aclr0 = '1')) or + ((output_aclr = "ACLR1") and (aclr1 = '1')) or + ((output_aclr = "ACLR2") and (aclr2 = '1')) or + ((output_aclr = "ACLR3") and (aclr3 = '1'))) and + (not (output_register = "UNREGISTERED"))) then + + output_result <= (others => '0'); + overflow_int <= '0'; + unsigned_sub1_overflow_reg <= '0'; + unsigned_sub3_overflow_reg <= '0'; + + elsif (((output_register = "CLOCK0") and rising_edge (clock0)) or + ((output_register = "CLOCK1") and rising_edge (clock1)) or + ((output_register = "CLOCK2") and rising_edge (clock2)) or + ((output_register = "CLOCK3") and rising_edge (clock3)) or + (output_register = "UNREGISTERED")) then + + if (((output_register = "CLOCK0") and (ena0 = '1')) or + ((output_register = "CLOCK1") and (ena1 = '1')) or + ((output_register = "CLOCK2") and (ena2 = '1')) or + ((output_register = "CLOCK3") and (ena3 = '1')) or + (output_register = "UNREGISTERED")) then + + unsigned_sub1_overflow_reg <= unsigned_sub1_overflow_mult_reg; + unsigned_sub3_overflow_reg <= unsigned_sub3_overflow_mult_reg; + + if ((asign = true) or (bsign = true)) then + if(accum_direction = "ADD") then + accum_res_temp := signed (adder3_reg_temp) + signed (adder1_reg_temp); + else + accum_res_temp := signed (acc_feedback_int) - signed (adder1_reg_temp); + end if; + else + if(accum_direction = "ADD") then + accum_res_temp := unsigned (adder3_reg_temp) + unsigned (adder1_reg_temp); + else + accum_res_temp := unsigned (acc_feedback_int) - unsigned (adder1_reg_temp); + end if; + end if; + + if ((asign = true) or (bsign = true)) then + if(accum_res_temp(accum_width - 1) = '1') then + accum_res_temp(accum_width) := '1'; + else + accum_res_temp(accum_width) := '0'; + end if; + + if(adder3_reg_temp(accum_width - 1) = '1') then + adder3_reg_temp(accum_width) := '1'; + else + adder3_reg_temp(accum_width) := '0'; + end if; + --else + -- accum_res_temp(accum_width) := '0'; + end if; + + if ((asign = true) or (bsign = true)) then + if(accum_direction = "ADD") then + accum_res_int := signed (acc_feedback_int) + signed (accum_res_temp); + else + accum_res_int := signed(accum_res_temp) - signed(adder3_reg_temp); + end if; + else + if(accum_direction = "ADD") then + accum_res_int := unsigned (acc_feedback_int) + unsigned (accum_res_temp); + else + accum_res_int := unsigned (accum_res_temp) - unsigned (adder3_reg_temp); + end if; + end if; + + or_sign_wire := '0'; + and_sign_wire := '0'; + + if(extra_sign_bit_width >= 1) then + and_sign_wire := '1'; + for i in (accum_width -lsb_position - extra_sign_bit_width) to (accum_width -lsb_position - 1) loop + if(accum_res_int(i) = '1') then + or_sign_wire := '1'; + end if; + + if(accum_res_int(i) = '0') then + and_sign_wire := '0'; + end if; + end loop; + end if; + + if(port_signa = "PORT_USED" or port_signb = "PORT_USED") then + if ((asign = true) or (bsign = true)) then + --signed data + if(accum_res_int(44) /= accum_res_int(43)) then + accum_overflow_int := '1'; + else + accum_overflow_int := '0'; + end if; + else + -- unsigned data + if(accum_direction = "ADD") then -- addition + if(accum_res_int(44) = '1') then + accum_overflow_int := '1'; + else + accum_overflow_int := '0'; + end if; + else -- subtraction + if(accum_res_int(44) = '0') then + accum_overflow_int := '0'; + else + accum_overflow_int := '0'; + end if; + end if; + end if; + + -- dynamic sign input + + if(accum_res_int(bit_position) = '1') then + msb := '1'; + else + msb := '0'; + end if; + + if(extra_sign_bit_width >= 1) then + if((and_sign_wire = '1') and ((not(asign = true or bsign = true)) or ((asign = true or bsign = true) and (msb = '1')))) then + and_sign_wire := '1'; + else + and_sign_wire := '0'; + end if; + + if ((asign = true or bsign = true) and (msb = '1')) then + or_sign_wire := '1'; + end if; + end if; + + --operation XOR + if ((or_sign_wire /= and_sign_wire) or accum_overflow_int = '1') then + accum_overflow := '1'; + else + accum_overflow := '0'; + end if; + elsif(representation_a = "SIGNED" or representation_b = "SIGNED") then + --signed data + if (accum_res_int(44) /= accum_res_int(43)) then + accum_overflow_int := '1'; + else + accum_overflow_int := '0'; + end if; + + --operation XOR + if ((or_sign_wire /= and_sign_wire) or accum_overflow_int = '1') then + accum_overflow := '1'; + else + accum_overflow := '0'; + end if; + else + -- unsigned data + if(accum_direction = "ADD") then + -- addition + if ((accum_res_int(44) = '1') or ((adder1_reg_temp(43) = '1') and (adder3_reg_temp(43) = '1')))then + accum_overflow_int := '1'; + else + accum_overflow_int := '0'; + end if; + else + -- subtraction + if (accum_res_int(44) = '0') then + accum_overflow_int := '1'; + else + accum_overflow_int := '0'; + end if; + end if; + + if(or_sign_wire = '1' or accum_overflow_int = '1') then + accum_overflow := '1'; + else + accum_overflow := '0'; + end if; + end if; + + accum_res <= accum_res_int; + + -- model the 2nd stage adder or accumulator + if (accumulator = "NO") then + if ((asign = true) or (bsign = true)) then + round_sat_in_result := signed (adder1_reg) + signed (adder3_reg); + else + round_sat_in_result := unsigned (adder1_reg) + unsigned (adder3_reg); + end if; + elsif (accum_direction = "ADD") then + if ((asign = true) or (bsign = true)) then + round_sat_in_result := signed (acc_feedback) + signed (adder1_reg) + signed (adder3_reg); + else + round_sat_in_result := unsigned (acc_feedback) + unsigned (adder1_reg) + unsigned (adder3_reg); + end if; + elsif (accum_direction = "SUB") then + if ((asign = true) or (bsign = true)) then + round_sat_in_result := signed (acc_feedback) - signed (adder1_reg) - signed (adder3_reg); + else + round_sat_in_result := unsigned (acc_feedback) - unsigned (adder1_reg) - unsigned (adder3_reg); + end if; + end if; + + round_happen := false; + -- 1st rounding block + if (output_rounding = "NO") then + round_block_result := round_sat_in_result; + else + if (((output_rounding = "VARIABLE") and (outround_pipe = '1')) or (output_rounding = "YES")) then + -- guard bit is '1' + if (round_sat_in_result(round_position - 1) = '1') then + if (output_round_type = "NEAREST_INTEGER") then -- round to nearest integer + round_block_result := unsigned(round_sat_in_result) + (2 ** (round_position)); + + else -- round to nearest even + stick_bits_or := '0'; + -- determine if any sticky bit is '1' + for stckbit_cnt in 0 to (round_position - 2) loop + stick_bits_or := stick_bits_or or round_sat_in_result(stckbit_cnt); + end loop; + + if (stick_bits_or = '1') then -- if sticky bits = 1, do rounding + round_block_result := unsigned(round_sat_in_result) + (2 ** (round_position)); + + else -- all sticky bits are 0, look at the LSB to determine to round or not + if (round_sat_in_result (round_position) = '1') then -- LSB is odd, so do rounding + round_block_result := unsigned(round_sat_in_result) + (2 ** (round_position)); + + else + round_block_result := round_sat_in_result; + end if; + end if; + end if; + else -- guard bit is 0, so no need to round + round_block_result := round_sat_in_result; + end if; + + -- if unsigned numbers enter into the rounding & saturation block, "X" the entire data + -- since unsigned numbers are illegal + if (((asign = false) and (bsign = false)) and (((port_signa = "PORT_USED") and (port_signb = "PORT_USED")) or + ((representation_a /= "UNUSED") and (representation_b /= "UNUSED")))) then + round_block_result := (others => 'X'); + end if; + + -- force the LSBs beyond the rounding position to "X" + if(input_source_b0 /= "LOOPBACK") then + for rndbit_cnt in 0 to (round_position - 1) loop + round_block_result(rndbit_cnt) := 'X'; + end loop; + end if; + + round_happen := true; + else + round_block_result := round_sat_in_result; + end if; + end if; + + -- prevent the previous overflow_status being taken into consideration when determining the overflow + if ((overflow_status = '0') and (port_output_is_overflow = "PORT_UNUSED") and (chainout_adder = "NO")) then + overflow_status_bit_pos := int_width_result + int_mult_diff_bit - 1; + else + overflow_status_bit_pos := int_width_result + 1; + end if; + + -- 1st saturation block + if (output_saturation = "NO") then + sat_block_result := round_block_result; + else + overflow_status := '0'; + if (((output_saturation = "VARIABLE") and (outsat_pipe = '1')) or (output_saturation = "YES")) then + if (round_block_result (int_width_result) = '0') then -- carry bit is 0, positive number + for sat_bit_cnt in (saturation_position) to (int_width_result) loop + if (sat_bit_cnt /= overflow_status_bit_pos) then + overflow_status := overflow_status or round_block_result (sat_bit_cnt); + end if; + end loop; + else -- carry bit is 1, negative number + for sat_bit_cnt in (saturation_position) to (int_width_result) loop + if (sat_bit_cnt /= overflow_status_bit_pos) then + overflow_status := overflow_status or (not round_block_result (sat_bit_cnt)); + end if; + end loop; + + if ((output_saturate_type = "SYMMETRIC") and (overflow_status = '0')) then + overflow_status := '1'; + if (round_happen) then + for sat_bit_cnt in (round_position) to (saturation_position - 1) loop + overflow_status := overflow_status and not(round_block_result (sat_bit_cnt)); + end loop; + else + for sat_bit_cnt in (0) to (saturation_position - 1) loop + overflow_status := overflow_status and not(round_block_result (sat_bit_cnt)); + end loop; + end if; + end if; + end if; + + if (overflow_status = '1') then + if (round_block_result (int_width_result) = '0') then -- positive number + if (port_output_is_overflow = "PORT_UNUSED") then + sat_block_result (int_width_a + int_width_b - 1) := overflow_status; + elsif (accumulator = "NO") then + sat_block_result (int_width_a + int_width_b - 1) := 'X'; + end if; + + for leadsat_bit_cnt in (saturation_position) to (int_width_a + int_width_b) loop + sat_block_result (leadsat_bit_cnt) := '0'; + end loop; + + if (round_happen) then + for trailsat_bit_cnt in (round_position) to (saturation_position - 1) loop + sat_block_result (trailsat_bit_cnt) := '1'; + end loop; + else + for trailsat_bit_cnt in 0 to (saturation_position - 1) loop + sat_block_result (trailsat_bit_cnt) := '1'; + end loop; + end if; + + sat_block_result(int_width_result + int_width_a + int_width_b - 1 downto int_width_a + int_width_b + 1) := (others => '0'); + + else -- negative number + if (port_output_is_overflow = "PORT_UNUSED") then + sat_block_result (int_width_a + int_width_b - 1) := overflow_status; + elsif (accumulator = "NO") then + sat_block_result (int_width_a + int_width_b - 1) := 'X'; + end if; + + for allsat_bit_cnt in (saturation_position) to (int_width_a + int_width_b) loop + sat_block_result (allsat_bit_cnt) := '1'; -- set all sign bits to '1' + end loop; + + if ((output_rounding /= "NO") and (output_saturate_type = "SYMMETRIC")) then + for allsat_bit_cnt in (round_position) to (saturation_position - 1) loop + sat_block_result (allsat_bit_cnt) := '0'; -- set all bits to "0" + end loop; + + if(accumulator = "NO") then + for allsat_bit_cnt in 0 to (round_position - 1) loop + sat_block_result (allsat_bit_cnt) := 'X'; -- set LSBs to "X" + end loop; + else + for allsat_bit_cnt in 0 to (round_position - 1) loop + sat_block_result (allsat_bit_cnt) := '0'; -- set LSBs to "X" + end loop; + end if; + else + for allsat_bit_cnt in 0 to (saturation_position - 1) loop + sat_block_result (allsat_bit_cnt) := '0'; -- set all bits to "0" + end loop; + end if; + + if ((output_rounding /= "NO") and (output_saturate_type = "SYMMETRIC")) then + sat_block_result (round_position) := '1'; + elsif (output_saturate_type = "SYMMETRIC") then + sat_block_result (int_mult_diff_bit) := '1'; + end if; + + sat_block_result(int_width_result + int_width_a + int_width_b - 1 downto int_width_a + int_width_b + 1) := (others => '1'); + end if; + else -- if not overflow + sat_block_result := round_block_result; + + if (port_output_is_overflow = "PORT_UNUSED" and chainout_adder = "NO" and ((output_saturation = "VARIABLE") and (outsat_pipe = '1'))) then + sat_block_result (int_width_result + int_mult_diff_bit - 1) := overflow_status; + end if; + -- if negative number & output_saturate_type is symmetric, need to check for special case + if (sat_block_result (int_width_a + int_width_b - 1) = '1') then + if (output_saturate_type = "SYMMETRIC") then + for satbit_or_cnt in (round_position) to (int_width_a + int_width_b - 2) loop + sat_bits_or := sat_bits_or or sat_block_result (satbit_or_cnt); + end loop; + + end if; + end if; + end if; + -- if unsigned numbers enter into the rounding & saturation block, "X" the entire data + -- since unsigned numbers are illegal + if (((asign = false) and (bsign = false)) and (((port_signa = "PORT_USED") and (port_signb = "PORT_USED")) or + ((representation_a /= "UNUSED") and (representation_b /= "UNUSED")))) then + sat_block_result := (others => 'X'); + end if; + elsif ((output_saturation = "VARIABLE") and (outsat_pipe = '0')) then + sat_block_result := round_block_result; + overflow_status := '0'; + else + sat_block_result := round_block_result; + end if; + end if; + + -- assign the saturation block output to a signal + output_result <= sat_block_result; + + -- assign the overflow status to the overflow port + if (port_output_is_overflow = "PORT_USED") then + if(output_saturation = "NO" and accumulator = "YES") then + overflow_int <= accum_overflow; + elsif(output_saturation /= "NO") then + overflow_int <= overflow_status; + end if; + end if; + + end if; + end if; -- end of output_register block + end process; + end generate IFGFAM1; + + IFGFAM10: if (stratixiii_block) generate + process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, + chainout_round_out_reg, chainout_sat_out, + zerochainout_reg, chainin, output_result) + + variable asign : boolean; + variable bsign : boolean; + variable is_rep_a_sign : boolean; + variable is_rep_b_sign : boolean; + variable is_rep_a_pipe_sign : boolean; + variable is_rep_b_pipe_sign : boolean; + variable cho_round_happen : boolean; + + variable cho_rndbit_cnt : integer := 0; + variable cho_stckbit_cnt : integer := 0; + variable cho_sat_bit_cnt : integer := 0; + variable cho_leadsat_bit_cnt : integer := 0; + variable cho_trailsat_bit_cnt : integer := 0; + variable cho_allsat_bit_cnt : integer := 0; + variable cho_satbit_or_cnt : integer := 0; + + variable cho_stick_bits_or : std_logic := '0'; + variable cho_sat_bits_or : std_logic := '0'; + variable chainout_overflow_status : std_logic := '0'; + + variable chainout_round_block_result : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable chainout_add_result : std_logic_vector (int_width_result downto 0) := (others => '0'); + variable chainout_sat_block_result : std_logic_vector (int_width_result downto 0) := (others => '0'); + + variable overflow_checking : std_logic; + variable round_checking : std_logic; + + begin + -- determine whether dataa and datab are signed or unsigned numbers + is_rep_a_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_reg = '1'))) or ((port_signa = "PORT_USED") and (sign_a_reg = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_b_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_reg = '1'))) or ((port_signb = "PORT_USED") and (sign_b_reg = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + is_rep_a_pipe_sign := ((port_signa = "PORT_CONNECTIVITY") and (((representation_a = "SIGNED") and (signa = 'Z')) or + (sign_a_pipe = '1'))) or ((port_signa = "PORT_USED") and (sign_a_pipe = '1')) or + ((port_signa = "PORT_UNUSED") and (representation_a = "SIGNED")); + + is_rep_b_pipe_sign := ((port_signb = "PORT_CONNECTIVITY") and (((representation_b = "SIGNED") and (signb = 'Z')) or + (sign_b_pipe = '1'))) or ((port_signb = "PORT_USED") and (sign_b_pipe = '1')) or + ((port_signb = "PORT_UNUSED") and (representation_b = "SIGNED")); + + -- Use sign_a_reg instead of sign_a_pipe when + -- signed_pipeline_register_a is unregistered + -- to set the asign flag + if (signed_pipeline_register_a = "UNREGISTERED") then + if (is_rep_a_sign) then + asign := true; + else + asign := false; + end if; + else + if (is_rep_a_pipe_sign) then + asign := true; + else + asign := false; + end if; + end if; + + -- Use sign_b_reg instead of sign_b_pipe when + -- signed_pipeline_register_b is unregistered + -- to set the bsign flag + if (signed_pipeline_register_b = "UNREGISTERED") then + if (is_rep_b_sign) then + bsign := true; + else + bsign := false; + end if; + else + if (is_rep_b_pipe_sign) then + bsign := true; + else + bsign := false; + end if; + end if; + + -- model the chainout stage + if ((((chainout_aclr = "ACLR0") and (aclr0 = '1')) or + ((chainout_aclr = "ACLR1") and (aclr1 = '1')) or + ((chainout_aclr = "ACLR2") and (aclr2 = '1')) or + ((chainout_aclr = "ACLR3") and (aclr3 = '1'))) and + (not (chainout_register = "UNREGISTERED"))) then + + chainout_sat_block_res_wire <= (others => '0'); + chainout_sat_overflow <= '0'; + chainout_overflow_int <= '0'; + + elsif (((chainout_register = "CLOCK0") and rising_edge (clock0)) or + ((chainout_register = "CLOCK1") and rising_edge (clock1)) or + ((chainout_register = "CLOCK2") and rising_edge (clock2)) or + ((chainout_register = "CLOCK3") and rising_edge (clock3)) or + (chainout_register = "UNREGISTERED")) then + + if (((chainout_register = "CLOCK0") and (ena0 = '1')) or + ((chainout_register = "CLOCK1") and (ena1 = '1')) or + ((chainout_register = "CLOCK2") and (ena2 = '1')) or + ((chainout_register = "CLOCK3") and (ena3 = '1')) or + (chainout_register = "UNREGISTERED")) then + + -- model the chainout adder + if (chainout_adder = "YES") then + if ((asign = true) or (bsign = true)) then + chainout_add_result := signed (output_result(int_width_result downto 0)) + signed (chainin); + else + chainout_add_result := unsigned (output_result(int_width_result downto 0)) + unsigned (chainin); + end if; + + cho_round_happen := false; + -- model the chainout stage rounding block + if (chainout_rounding = "NO") then + chainout_round_block_result := chainout_add_result; + else + if (((chainout_rounding = "VARIABLE") and (chainout_round_out_reg = '1')) or (chainout_rounding = "YES")) then + overflow_checking := chainout_add_result(int_width_result - 1); + -- guard bit is '1' + if (chainout_add_result(chainout_round_position - 1) = '1') then + if (output_round_type = "NEAREST_INTEGER") then -- round to nearest integer + round_checking := '1'; + chainout_round_block_result := unsigned(chainout_add_result) + (2 ** (chainout_round_position)); + + else -- round to nearest even + -- determine if any sticky bit is '1' + cho_stick_bits_or := '0'; + for cho_stckbit_cnt in 0 to (chainout_round_position - 2) loop + cho_stick_bits_or := cho_stick_bits_or or chainout_add_result(cho_stckbit_cnt); + end loop; + + if (cho_stick_bits_or = '1') then -- if sticky bits = 1, do rounding + chainout_round_block_result := unsigned(chainout_add_result) + (2 ** (chainout_round_position)); + + else -- all sticky bits are 0, look at the LSB to determine to round or not + if (chainout_add_result (chainout_round_position) = '1') then -- LSB is odd, so do rounding + chainout_round_block_result := unsigned(chainout_add_result) + (2 ** (chainout_round_position)); + else + chainout_round_block_result := chainout_add_result; + end if; + end if; + end if; + else -- guard bit is 0, so no need to round + chainout_round_block_result := chainout_add_result; + end if; + -- if unsigned numbers enter into the rounding & saturation block, "X" the entire data + -- since unsigned numbers are illegal + if (((asign = false) and (bsign = false)) and (((port_signa = "PORT_USED") and (port_signb = "PORT_USED")) or + ((representation_a /= "UNUSED") and (representation_b /= "UNUSED")))) then + chainout_round_block_result := (others => 'X'); + end if; + + cho_round_happen := true; + else + chainout_round_block_result := chainout_add_result; + end if; + end if; + + chainout_overflow_status := '0'; + if (chainout_saturation = "NO") then + chainout_sat_block_result := chainout_round_block_result; + else + if (((chainout_saturation = "VARIABLE") and (chainout_sat_out = '1')) or (chainout_saturation = "YES")) then + if ((((chainout_rounding = "VARIABLE") and (chainout_round_out_reg = '1')) or (chainout_rounding = "YES")) and round_checking = '1' and width_saturate_sign = 1 and width_result = result_width) then + if (chainout_round_block_result(int_width_result - 1) /= overflow_checking) then + chainout_overflow_status := '1'; + else + chainout_overflow_status := '0'; + end if; + elsif (chainout_round_block_result (int_width_result - 1) = '0') then -- carry bit is 0, positive number + for cho_sat_bit_cnt in (chainout_saturation_position) to (int_width_result - 1) loop + chainout_overflow_status := chainout_overflow_status or chainout_round_block_result (cho_sat_bit_cnt); + end loop; + else -- carry bit is 1, negative number + for cho_sat_bit_cnt in (chainout_saturation_position) to (int_width_result - 1) loop + chainout_overflow_status := chainout_overflow_status or (not chainout_round_block_result (cho_sat_bit_cnt)); + end loop; + + if ((output_saturate_type = "SYMMETRIC") and (chainout_overflow_status = '0')) then + chainout_overflow_status := '1'; + if (cho_round_happen) then + for cho_sat_bit_cnt in (chainout_round_position) to (chainout_saturation_position - 1) loop + chainout_overflow_status := chainout_overflow_status and not(chainout_round_block_result (cho_sat_bit_cnt)); + end loop; + else + for cho_sat_bit_cnt in (0) to (chainout_saturation_position - 1) loop + chainout_overflow_status := chainout_overflow_status and not(chainout_round_block_result (cho_sat_bit_cnt)); + end loop; + end if; + end if; + end if; + + if (chainout_overflow_status = '1') then + if ((((chainout_rounding = "VARIABLE") and (chainout_round_out_reg = '1')) or (chainout_rounding = "YES")) and round_checking = '1' and width_saturate_sign = 1 and width_result = result_width) then + if (chainout_round_block_result (int_width_result - 1) = '1') then -- positive number + if (port_chainout_sat_is_overflow = "PORT_UNUSED") then + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + else + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + end if; + + for cho_leadsat_bit_cnt in (chainout_saturation_position) to (int_width_result - 1) loop + chainout_sat_block_result (cho_leadsat_bit_cnt) := '0'; + end loop; + + if (cho_round_happen) then + for cho_trailsat_bit_cnt in (0) to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_trailsat_bit_cnt) := '1'; + end loop; + else + for cho_trailsat_bit_cnt in 0 to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_trailsat_bit_cnt) := '1'; + end loop; + end if; + + else -- negative number + if (port_chainout_sat_is_overflow = "PORT_UNUSED") then + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + else + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + end if; + + for cho_allsat_bit_cnt in (chainout_saturation_position) to (int_width_result - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '1'; -- set all sign bits to '1' + end loop; + + if ((chainout_rounding /= "NO") and (output_saturate_type = "SYMMETRIC")) then + for cho_allsat_bit_cnt in (chainout_round_position) to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '0'; -- set all bits to '0' + end loop; + + for cho_allsat_bit_cnt in 0 to (chainout_round_position - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '0'; -- set LSBs to '0' + end loop; + else + for cho_allsat_bit_cnt in 0 to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '0'; -- set all bits to '0' + end loop; + end if; + + if ((chainout_rounding /= "NO") and (output_saturate_type = "SYMMETRIC")) then + chainout_sat_block_result (chainout_round_position) := '1'; + elsif (output_saturate_type = "SYMMETRIC") then + chainout_sat_block_result (int_mult_diff_bit) := '1'; + end if; + end if; + else + if (chainout_round_block_result (int_width_result - 1) = '0') then -- positive number + if (port_chainout_sat_is_overflow = "PORT_UNUSED") then + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + else + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + end if; + + for cho_leadsat_bit_cnt in (chainout_saturation_position) to (int_width_result - 1) loop + chainout_sat_block_result (cho_leadsat_bit_cnt) := '0'; + end loop; + + if (cho_round_happen) then + for cho_trailsat_bit_cnt in (0) to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_trailsat_bit_cnt) := '1'; + end loop; + else + for cho_trailsat_bit_cnt in 0 to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_trailsat_bit_cnt) := '1'; + end loop; + end if; + + else -- negative number + if (port_chainout_sat_is_overflow = "PORT_UNUSED") then + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + else + chainout_sat_block_result (int_width_result - 1) := chainout_overflow_status; + end if; + + for cho_allsat_bit_cnt in (chainout_saturation_position) to (int_width_result - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '1'; -- set all sign bits to '1' + end loop; + + if ((chainout_rounding /= "NO") or (output_saturate_type = "SYMMETRIC")) then + for cho_allsat_bit_cnt in (chainout_round_position) to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '0'; -- set all bits to '0' + end loop; + + for cho_allsat_bit_cnt in 0 to (chainout_round_position - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '0'; -- set LSBs to 'X' + end loop; + else + for cho_allsat_bit_cnt in 0 to (chainout_saturation_position - 1) loop + chainout_sat_block_result (cho_allsat_bit_cnt) := '0'; -- set all bits to '0' + end loop; + end if; + + if ((chainout_rounding /= "NO") and (output_saturate_type = "SYMMETRIC")) then + chainout_sat_block_result (chainout_round_position) := '1'; + elsif (output_saturate_type = "SYMMETRIC") then + chainout_sat_block_result (int_mult_diff_bit) := '1'; + end if; + end if; + end if; + else -- if not overflow + chainout_sat_block_result := chainout_round_block_result; + + -- if negative number & output_saturate_type is symmetric, need to check for special case + if (chainout_sat_block_result (int_width_result) = '1') then + if (output_saturate_type = "SYMMETRIC") then + for cho_satbit_or_cnt in (chainout_round_position) to (int_width_result - 2) loop + cho_sat_bits_or := cho_sat_bits_or or chainout_sat_block_result (cho_satbit_or_cnt); + end loop; + + if ((cho_sat_bits_or = '0') and (chainout_sat_block_result (int_width_result - 1) = '1')) then + chainout_sat_block_result (chainout_round_position) := '1'; + end if; + end if; + end if; + end if; + -- if unsigned numbers enter into the rounding & saturation block, "X" the entire data + -- since unsigned numbers are illegal + if (((asign = false) and (bsign = false)) and (((port_signa = "PORT_USED") and (port_signb = "PORT_USED")) or + ((representation_a /= "UNUSED") and (representation_b /= "UNUSED")))) then + chainout_sat_block_result := (others => 'X'); + end if; + else + chainout_sat_block_result := chainout_round_block_result; + end if; + end if; + end if; + + -- assign the chainout overflow status to the chainout_sat_overflow port + if (port_chainout_sat_is_overflow = "PORT_USED") then + chainout_sat_overflow <= chainout_overflow_status; + chainout_overflow_int <= chainout_overflow_status; + end if; + + chainout_sat_block_res_wire <= chainout_sat_block_result; + + end if; + end if; -- end of chainout register stage + end process; + end generate IFGFAM10; + + IFGFAM11: if (stratixiii_block) generate + process (chainout_sat_block_res_wire, zerochainout_reg) + variable cho_cnt : integer := 0; + variable chainout_out_temp : std_logic_vector (int_width_result downto 0) := (others => '0'); + begin + chainout_out_temp := (others => '0'); + -- the chainout output after factoring in zero_chainout + for cho_cnt in 0 to int_width_result loop + chainout_out_temp(cho_cnt) := (not zerochainout_reg) and (chainout_sat_block_res_wire(cho_cnt)); + end loop; + + chainout_output(int_width_result downto 0) <= chainout_out_temp(int_width_result downto 0); + end process; + end generate IFGFAM11; + + -- model the shift & rotate blocks for Stratix III + IFGFAM2: if (stratixiii_block) generate + process (output_result, shiftr_out, rotate_out) + begin + if (not (shift_mode = "NO")) then + if ((shift_mode = "LEFT") or ((shift_mode = "VARIABLE") and (shiftr_out = '0') and (rotate_out = '0'))) then + shift_rot_result <= output_result((int_width_result / 2) - 1 downto 0); + elsif ((shift_mode = "RIGHT") or ((shift_mode = "VARIABLE") and (shiftr_out = '1') and (rotate_out = '0'))) then + shift_rot_result <= output_result(int_width_result - 1 downto (int_width_result / 2)); + elsif ((shift_mode = "ROTATION") or ((shift_mode = "VARIABLE") and (shiftr_out = '0') and (rotate_out = '1'))) then + shift_rot_result <= (output_result(int_width_result - 1 downto (int_width_result / 2))) or + (output_result((int_width_result / 2) - 1 downto 0)); + end if; + end if; + end process; + end generate IFGFAM2; + + IFGFAM3: if (stratixiii_block) generate + process (output_result, zeroloopback_out) + + variable lpbk_cnt : integer := 0; + + begin + if (input_source_b0 = "LOOPBACK") then + for lpbk_cnt in 0 to (int_width_result - 1) loop + loopback_wire(lpbk_cnt) <= output_result(lpbk_cnt + (int_width_b - width_b)) and (not zeroloopback_out); + end loop; + end if; + end process; + end generate IFGFAM3; + + IFLOOPBACK: if (stratixiii_block) generate + process (loopback_wire) + begin + if(input_source_b0 = "LOOPBACK") then + feedback <= loopback_wire(width_a + 18 - 1 downto width_a); + end if; + end process; + end generate IFLOOPBACK; + + IFGFAM4: if (stratixiii_block) generate + process (output_result, accumsload_pipe) + + variable acfdbk_cnt : integer := 0; + + begin + if (accumulator = "YES") then + for acfdbk_cnt in 0 to (int_width_result + int_width_a + int_width_b) loop + acc_feedback(acfdbk_cnt) <= output_result(acfdbk_cnt) and (not accumsload_pipe); + end loop; + end if; + end process; + end generate IFGFAM4; + + IFACCUM: if (stratixiii_block) generate + process (accum_res, accumsload_pipe) + + variable acfdbk_cnt : integer := 0; + + begin + if (accumulator = "YES") then + for acfdbk_cnt in 0 to (accum_width) loop + acc_feedback_temp(acfdbk_cnt) <= accum_res(acfdbk_cnt) and (not accumsload_pipe); + end loop; + end if; + end process; + end generate IFACCUM; + + + IFGFAM5: if (stratixiii_block) generate + process (output_result, overflow_int, chainout_overflow_int, shift_rot_result, chainout_output, clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, unsigned_sub1_overflow_reg, unsigned_sub3_overflow_reg) + + variable head_result_int : integer := 0; + variable res_cnt : integer := 0; + variable result_pipe : pipeline_accum := (others => (others => '0')); + variable result_stxiii : std_logic_vector (width_result - 1 downto 0) := (others => '0'); + variable result_stxiii_ext : std_logic_vector (width_result - 1 downto 0) := (others => '0'); + variable count : integer := 0; + variable overflow_stat_pipe_reg : std_logic_vector (extra_latency downto 0) := (others => '0'); + variable head_overflow_int : integer := 0; + + begin + if (extra_latency = 0) then + if (not (shift_mode = "NO")) then + result_stxiii := shift_rot_result((width_result - 1 + int_mult_diff_bit) downto int_mult_diff_bit); + elsif (chainout_adder = "YES") then + result_stxiii := chainout_output((width_result - 1 + int_mult_diff_bit) downto int_mult_diff_bit); + elsif (input_source_b0 = "LOOPBACK") then + result_stxiii := output_result((width_result - 1 + (int_width_b - width_b)) downto int_width_b - width_b); + else + result_stxiii := output_result((width_result - 1 + int_mult_diff_bit) downto int_mult_diff_bit); + end if; + + -- need to extend the MSB for cases where width_result is larger than width_a + width_b + if ((chainout_adder = "YES") or (accumulator = "YES")) then + result_stxiii_ext(width_result - 1 downto 0) := result_stxiii(width_result - 1 downto 0); + elsif ((number_of_multipliers = 1) and (width_result > width_a + width_b)) then + if (((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) and (unsigned_sub1_overflow_reg = '0' and unsigned_sub3_overflow_reg = '0')) then + for res_cnt in 1 to (width_result - width_a - width_b) loop + result_stxiii_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b) loop + result_stxiii_ext(width_result - res_cnt) := result_stxiii(width_a + width_b - 1); + end loop; + end if; + result_stxiii_ext(width_a + width_b - 1 downto 0) := result_stxiii(width_a + width_b - 1 downto 0); + elsif (((number_of_multipliers = 2) or (input_source_b0 = "LOOPBACK")) and (width_result > width_a + width_b + 1)) then + if (((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) and (unsigned_sub1_overflow_reg = '0' and unsigned_sub3_overflow_reg = '0')) then + for res_cnt in 1 to (width_result - width_a - width_b - 1) loop + result_stxiii_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b - 1) loop + result_stxiii_ext(width_result - res_cnt) := result_stxiii(width_a + width_b); + end loop; + end if; + result_stxiii_ext(width_a + width_b downto 0) := result_stxiii(width_a + width_b downto 0); + elsif ((number_of_multipliers > 2) and (width_result > width_a + width_b + 2)) then + if (((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) and (unsigned_sub1_overflow_reg = '0' and unsigned_sub3_overflow_reg = '0')) then + for res_cnt in 1 to (width_result - width_a - width_b - 2) loop + result_stxiii_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - width_a - width_b - 2) loop + result_stxiii_ext(width_result - res_cnt) := result_stxiii(width_a + width_b + 1); + end loop; + end if; + result_stxiii_ext(width_a + width_b + 1 downto 0) := result_stxiii(width_a + width_b + 1 downto 0); + else + result_stxiii_ext(width_result - 1 downto 0) := result_stxiii(width_result - 1 downto 0); + end if; + + result <= result_stxiii_ext; + if(chainout_saturation /= "NO") then + overflow <= chainout_overflow_int ; + else + overflow <= overflow_int; + end if; + + else + if (input_source_b0 = "LOOPBACK") then + result_stxiii := output_result((width_result - 1 + (int_width_b - width_b)) downto int_width_b - width_b); + else + result_stxiii := output_result((width_result - 1 + int_mult_diff_bit) downto int_mult_diff_bit); + end if; + + if ((chainout_adder = "YES") or (accumulator = "YES")) then + result_stxiii_ext(width_result - 1 downto 0) := result_stxiii(width_result - 1 downto 0); + elsif ((number_of_multipliers = 1) and (width_result > int_width_a + int_width_b)) then + if (((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) and (unsigned_sub1_overflow_reg = '0' and unsigned_sub3_overflow_reg = '0')) then + for res_cnt in 1 to (width_result - int_width_a - int_width_b) loop + result_stxiii_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - int_width_a - int_width_b) loop + result_stxiii_ext(width_result - res_cnt) := result_stxiii(int_width_a + int_width_b - 1); + end loop; + end if; + result_stxiii_ext(int_width_a + int_width_b - 1 downto 0) := result_stxiii(int_width_a + int_width_b - 1 downto 0); + elsif (((number_of_multipliers = 2) or (input_source_b0 = "LOOPBACK")) and (width_result > int_width_a + int_width_b + 1)) then + if (((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) and (unsigned_sub1_overflow_reg = '0' and unsigned_sub3_overflow_reg = '0')) then + for res_cnt in 1 to (width_result - int_width_a - int_width_b - 1) loop + result_stxiii_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - int_width_a - int_width_b - 1) loop + result_stxiii_ext(width_result - res_cnt) := result_stxiii(int_width_a + int_width_b); + end loop; + end if; + result_stxiii_ext(int_width_a + int_width_b downto 0) := result_stxiii(int_width_a + int_width_b downto 0); + elsif ((number_of_multipliers > 2) and (width_result > int_width_a + int_width_b + 2)) then + if (((representation_a = "UNSIGNED") and (representation_b = "UNSIGNED")) and (unsigned_sub1_overflow_reg = '0' and unsigned_sub3_overflow_reg = '0')) then + for res_cnt in 1 to (width_result - int_width_a - int_width_b - 2) loop + result_stxiii_ext(width_result - res_cnt) := '0'; + end loop; + else + for res_cnt in 1 to (width_result - int_width_a - int_width_b - 2) loop + result_stxiii_ext(width_result - res_cnt) := result_stxiii(int_width_a + int_width_b + 1); + end loop; + end if; + result_stxiii_ext(int_width_a + int_width_b + 1 downto 0) := result_stxiii(int_width_a + int_width_b + 1 downto 0); + else + result_stxiii_ext(width_result - 1 downto 0) := result_stxiii(width_result - 1 downto 0); + end if; + + if(output_aclr = "ACLR0" and aclr0 = '1') then + for count in 0 to extra_latency loop + result_pipe(count) := (others => '0'); + overflow_stat_pipe_reg (count) := '0'; + head_result_siii <= 0; + head_overflow <= 0; + result <= (others => '0'); + overflow <= '0'; + end loop; + elsif(output_aclr = "ACLR1" and aclr1 = '1') then + for count in 0 to extra_latency loop + result_pipe(count) := (others => '0'); + overflow_stat_pipe_reg (count) := '0'; + head_result_siii <= 0; + head_overflow <= 0; + result <= (others => '0'); + overflow <= '0'; + end loop; + elsif(output_aclr = "ACLR2" and aclr2 = '1') then + for count in 0 to extra_latency loop + result_pipe(count) := (others => '0'); + overflow_stat_pipe_reg (count) := '0'; + head_result_siii <= 0; + head_overflow <= 0; + result <= (others => '0'); + overflow <= '0'; + end loop; + elsif(output_aclr = "ACLR3" and aclr3 = '1') then + for count in 0 to extra_latency loop + result_pipe(count) := (others => '0'); + overflow_stat_pipe_reg (count) := '0'; + head_result_siii <= 0; + head_overflow <= 0; + result <= (others => '0'); + overflow <= '0'; + end loop; + end if; + + if ((output_register = "CLOCK0") and (rising_edge(clock0) and ena0 = '1')) then + head_result_int := head_result_siii; + head_overflow_int := head_overflow; + result_pipe(head_result_int) := result_stxiii_ext; + if(chainout_saturation /= "NO") then + overflow_stat_pipe_reg (head_overflow_int) := chainout_overflow_int; + else + overflow_stat_pipe_reg (head_overflow_int) := overflow_int; + end if; + head_result_int := (head_result_int +1) mod (extra_latency); + head_overflow_int := (head_overflow_int +1) mod (extra_latency); + overflow <= overflow_stat_pipe_reg(head_overflow_int); + result <= result_pipe(head_result_int); + head_result_siii <= head_result_int; + head_overflow <= head_overflow_int; + elsif ((output_register = "CLOCK1") and (rising_edge(clock1) and ena1 = '1')) then + head_result_int := head_result_siii; + head_overflow_int := head_overflow; + result_pipe(head_result_int) := result_stxiii_ext; + if(chainout_saturation /= "NO") then + overflow_stat_pipe_reg (head_overflow_int) := chainout_overflow_int; + else + overflow_stat_pipe_reg (head_overflow_int) := overflow_int; + end if; + head_result_int := (head_result_int +1) mod (extra_latency); + head_overflow_int := (head_overflow_int +1) mod (extra_latency); + overflow <= overflow_stat_pipe_reg(head_overflow_int); + result <= result_pipe(head_result_int); + head_result_siii <= head_result_int; + head_overflow <= head_overflow_int; + elsif ((output_register = "CLOCK2") and (rising_edge(clock2) and ena2 = '1')) then + head_result_int := head_result_siii; + head_overflow_int := head_overflow; + result_pipe(head_result_int) := result_stxiii_ext; + if(chainout_saturation /= "NO") then + overflow_stat_pipe_reg (head_overflow_int) := chainout_overflow_int; + else + overflow_stat_pipe_reg (head_overflow_int) := overflow_int; + end if; + head_result_int := (head_result_int +1) mod (extra_latency); + head_overflow_int := (head_overflow_int +1) mod (extra_latency); + overflow <= overflow_stat_pipe_reg(head_overflow_int); + result <= result_pipe(head_result_int); + head_result_siii <= head_result_int; + head_overflow <= head_overflow_int; + elsif ((output_register = "CLOCK3") and (rising_edge(clock3) and ena3 = '1')) then + head_result_int := head_result_siii; + head_overflow_int := head_overflow; + result_pipe(head_result_int) := result_stxiii_ext; + if(chainout_saturation /= "NO") then + overflow_stat_pipe_reg (head_overflow_int) := chainout_overflow_int; + else + overflow_stat_pipe_reg (head_overflow_int) := overflow_int; + end if; + head_result_int := (head_result_int +1) mod (extra_latency); + head_overflow_int := (head_overflow_int +1) mod (extra_latency); + overflow <= overflow_stat_pipe_reg(head_overflow_int); + result <= result_pipe(head_result_int); + head_result_siii <= head_result_int; + head_overflow <= head_overflow_int; + end if; + + if((width_a > 36) or (width_b > 36)) then + if (rising_edge(clock0) or rising_edge(clock1) or rising_edge(clock2) or rising_edge(clock3)) then + head_result_int := head_result_siii; + head_overflow_int := head_overflow; + result_pipe(head_result_int) := result_stxiii_ext; + overflow_stat_pipe_reg (head_overflow) := overflow_int; + head_result_int := (head_result_int +1) mod (extra_latency); + head_overflow_int := (head_overflow_int +1) mod (extra_latency); + overflow <= overflow_stat_pipe_reg(head_overflow_int); + result <= result_pipe(head_result_int); + head_result_siii <= head_result_int; + head_overflow <= head_overflow_int; + end if; + end if; + + if((width_a > 36) or (width_b > 36)) then + if (rising_edge(aclr0) or rising_edge(aclr1) or rising_edge(aclr2) or rising_edge(aclr3)) then + for count in 0 to extra_latency loop + result_pipe(count) := (others => '0'); + head_result_siii <= 0; + head_overflow <= 0; + result <= (others => '0'); + overflow <= '0'; + end loop; + end if; + end if; + + if((output_register = "UNREGISTERED") and (width_a < 36 and width_b < 36)) then + head_result_int := head_result_siii; + result_pipe(head_result_int) := result_stxiii_ext; + result <= result_pipe(head_result_int); + if(chainout_saturation /= "NO") then + overflow_stat_pipe_reg (head_overflow_int) := chainout_overflow_int; + else + overflow_stat_pipe_reg (head_overflow_int) := overflow_int; + end if; + overflow <= overflow_stat_pipe_reg(head_overflow_int); + head_result_siii <= head_result_int; + head_overflow <= head_overflow_int; + end if; + end if; + end process; + end generate IFGFAM5; + + + IFGFAM6: if (stratixv_block and not(preadder_mode = "SIMPLE")) generate + assert false + report "Error: Stratix V simulation model not support other mode beside simple mode in the current Quartus II Version"; + end generate IFGFAM6; + +end behaviour; -- end of ALTMULT_ADD + +-- START ENTITY HEADER --------------------------------------------------------- +-- +-- Entity Name : altfp_mult +-- +-- Description : Parameterized floating point multiplier megafunction. +-- This module implements IEEE-754 Compliant Floating Poing +-- Multiplier. The module supports Single Precision, Single +-- Extended Precision, and Double Precision floating point +-- multiplication. +-- +-- Limitations : Fixed clock latency with 4 clock cycle delay. +-- +--Results expected : result of multiplication and the result's status bits + +-- END ENTITY HEADER ----------------------------------------------------------- + + +-- LIBRARY USED----------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.ALTERA_COMMON_CONVERSION.all; + +-- ENTITY DECLARATION +entity altfp_mult is + +-- GENERIC DECLARATION + generic ( + -- exponent width, Minimum = 8, Maximum = 31 + width_exp : natural := 8; + -- mantissa width, Minimum = 23, Maximum = 52 + width_man : natural := 23; + -- Specifies whether to use dedicated multiplier circuitry. + dedicated_multiplier_circuitry : string := "AUTO"; + reduced_functionality : string := "NO"; + pipeline : natural := 5; + denormal_support : string := "YES"; + exception_handling : string := "YES"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altfp_mult" ); + +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + -- Clock input to the multiplier.(Required) + clock : in std_logic; + -- Clock enable for the multiplier. + clk_en : in std_logic := '1'; + -- Asynchronous clear for the multiplier. + aclr : in std_logic := '0'; + -- Data input to the multiplier.(Required) + dataa : in std_logic_vector(width_exp + width_man downto 0); + datab : in std_logic_vector(width_exp + width_man downto 0); + +-- OUTPUT PORT DECLARATION + -- Multiplier output port.(Required) + result : out std_logic_vector(width_exp + width_man downto 0); + overflow : out std_logic ; + underflow : out std_logic ; + zero : out std_logic; + denormal : out std_logic ; + indefinite : out std_logic; + nan : out std_logic ); + +end altfp_mult; +-- END OF ENTITY + + +-- BEGINNING OF ACHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of altfp_mult is + +-- CONSTANT DECLARATION +constant LATENCY : integer := pipeline -1; +constant WIDTH_MAN_EXP : integer := width_exp + width_man; + +-- TYPE DECLARATION +type PIPELINE_MULT is array (LATENCY downto 0) of std_logic_vector(WIDTH_MAN_EXP + 6 downto 0); + +-- FUNCTION DECLARATION + -- Bitwise left shift + procedure shift_left ( val : inout std_logic_vector) is + variable temp : std_logic_vector((val'length - 1) downto 0); + begin + temp := val; + if (val'length > 1) then + for i in temp'high downto 1 loop + temp(i) := temp(i-1); + end loop; + end if; + temp(0) :='0'; + val := temp; + end shift_left; + + -- Bitwise right shift + procedure shift_right ( cout: in std_logic; + val : inout std_logic_vector ) is + variable temp : std_logic_vector(val'length-1 downto 0); + begin + temp := val; + if (val'length > 1) then + for i in 0 to temp'high - 1 loop + temp(i) := temp(i+1); + end loop; + end if; + temp(temp'high) := cout; + val := temp; + end shift_right; + + -- Check whether all the bits is '0' or not + function bit_all_0 ( val : std_logic_vector ) return boolean is + variable all_0 : boolean := true; + begin + for i in val'range loop + if (val(i) = '1') then + all_0 := false; + exit; + end if; + end loop; + return all_0; + end bit_all_0; + + -- Check whether all the bits is '0' or not (with specific range) + function bit_all_0 (val : std_logic_vector; + index1 : integer; + index2 : integer ) return boolean is + variable all_0 : boolean := true; + begin + for i in index1 to index2 loop + if (val(i) = '1') then + all_0 := false; + exit; + end if; + end loop; + return all_0; + end bit_all_0; + + -- add val1 to temporary result + procedure add_bits( val1 : in std_logic_vector; + result : inout std_logic_vector; + cout : out std_logic) is + variable co : std_logic; + variable i : integer := 0; + begin + co := '0'; + for i in 0 to val1'high loop + if (co = '0') then + if (val1(i) /= result(i + width_man + 1)) then + result(i + width_man + 1) := '1'; + else + co := val1(i) and result(i + width_man + 1); + result(i + width_man + 1) := '0'; + end if; + else + co := val1(i) or result(i + width_man + 1); + if (val1(i) /= result(i + width_man + 1)) then + result(i + width_man + 1) := '0'; + else + result(i + width_man + 1) := '1'; + end if; + end if; + end loop; + cout := co; + end add_bits; + + +begin + +-- basic error checking for invalid deserialization factors + MSG: process + begin + -- Check for illegal mode setting + if ((width_exp + width_man) >= 64) then + ASSERT FALSE + REPORT "The sum of width_exp (" & INT_TO_STR_ARITH(width_exp) & + ") and width_man (" & INT_TO_STR_ARITH(width_man) & + ") must be less than 64" + SEVERITY ERROR; + end if; + if (width_exp < 8) then + ASSERT FALSE + REPORT "width_exp (" & INT_TO_STR_ARITH(width_exp) & ") must be at least 8" + SEVERITY ERROR; + end if; + if (width_man < 23) then + ASSERT FALSE + REPORT "width_man (" & INT_TO_STR_ARITH(width_man) & ") must be at least 23" + SEVERITY ERROR; + end if; + if not ((width_exp >= 11) or ((width_exp = 8) and (width_man = 23))) then + ASSERT FALSE + REPORT "Found width_exp (" & INT_TO_STR_ARITH(width_exp) & + ") inside the range of Single Precision. width_exp must be 8" & + " and width_man must be 23 for Single Precision" + SEVERITY ERROR; + end if; + if not ((width_man >= 31) or ((width_exp = 8) and (width_man = 23))) then + ASSERT FALSE + REPORT "Found width_man (" & INT_TO_STR_ARITH(width_man) & + ") inside the range of Single Precision. width_exp must be 8" & + " and width_man must be 23 for Single Precision" + SEVERITY ERROR; + end if; + if (width_exp >= width_man) then + ASSERT FALSE + REPORT "width_exp (" & INT_TO_STR_ARITH(width_exp) & + ") must be less than width_man (" & INT_TO_STR_ARITH(width_man) & ")" + SEVERITY ERROR; + end if; + if ((pipeline /= 5) and (pipeline /= 6) and (pipeline /= 10) and (pipeline /= 11)) then + ASSERT FALSE + REPORT "The legal value for pipeline is 5, 6, 10 or 11." + SEVERITY ERROR; + end if; + if ((reduced_functionality /= "NO") and (reduced_functionality /= "YES")) then + ASSERT FALSE + REPORT "reduced_functionality value must be ""YES"" or ""NO""." + SEVERITY ERROR; + end if; + + if ((denormal_support /= "NO") and (denormal_support /= "YES")) then + ASSERT FALSE + REPORT "denormal_support value must be ""YES"" or ""NO""." + SEVERITY ERROR; + end if; + + if (reduced_functionality /= "NO") then + ASSERT FALSE + REPORT "The Clearbox support is available for reduced functionality Floating Point Multiplier." + SEVERITY WARNING; + end if; + wait; + end process; -- MSG process + + MULTIPLY_FP: process(clock, aclr) + variable exp_dataa : integer := 0; + variable exp_datab : integer := 0; + variable exp_result : integer := 0; + variable mant_dataa : std_logic_vector (width_man downto 0) + := (others => '0'); + variable mant_datab : std_logic_vector (width_man downto 0) + := (others => '0'); + variable mant_result : std_logic_vector ((2 * (width_man + 1)) - 1 downto 0) + := (others => '0'); + variable cout : std_logic := '0'; + variable zero_mant_dataa : boolean := false; + variable zero_mant_datab : boolean := false; + variable zero_dataa : boolean := false; + variable zero_datab : boolean := false; + variable inf_dataa : boolean := false; + variable inf_datab : boolean := false; + variable nan_dataa : boolean := false; + variable nan_datab : boolean := false; + variable den_dataa : boolean := false; + variable den_datab : boolean := false; + variable no_multiply : boolean := false; + variable no_rounding : boolean := false; + variable mant_result_msb : std_logic := '0'; + variable sticky_bit : std_logic := '0'; + variable round_bit : std_logic := '0'; + variable guard_bit : std_logic := '0'; + variable carry : boolean := false; + variable temp_result : PIPELINE_MULT := (others => (others => '0')); + + begin + + if (aclr = '1') then --clear the output ports + temp_result := (others => (others => '0')); + for i in LATENCY downto 0 loop + temp_result(i)(WIDTH_MAN_EXP + 3) := '1'; -- set zero status + end loop; + result <= (others => '0'); + overflow <= '0'; + underflow <= '0'; + zero <= '1'; + denormal <= '0'; + indefinite <= '0'; + nan <= '0'; + elsif (clock = '1') and clock'event and (clock'last_value = '0') then + if (clk_en = '1') then + -- Create latency for the output result + for i in LATENCY downto 1 loop + temp_result(i) := temp_result(i - 1); + end loop; + + temp_result(0) := (others => '0'); + mant_result := (others => '0'); + + --convert exponent of dataa[] to integer + exp_dataa := 0; + for i in 0 to width_exp -1 loop + if (dataa(width_man + i) = '1') then + exp_dataa := (2**i) + exp_dataa; + end if; + end loop; + + --convert exponent of datab[] to integer + exp_datab := 0; + for i in 0 to width_exp -1 loop + if (datab(width_man + i) = '1') then + exp_datab := (2**i) + exp_datab; + end if; + end loop; + + --check whether all the bits in mantissa of dataa[] is '0' + zero_mant_dataa := true; + for i in 0 to width_man -1 loop + if (dataa(i) = '1') then + zero_mant_dataa := false; + exit; + end if; + end loop; + + --check whether all the bits in mantissa of datab[] is '0' + zero_mant_datab := true; + for i in 0 to width_man -1 loop + if (datab(i) = '1') then + zero_mant_datab := false; + exit; + end if; + end loop; + + --check whether dataa is special input + zero_dataa := false; + den_dataa := false; + inf_dataa := false; + nan_dataa := false; + if (exp_dataa = 0) then + if ((zero_mant_dataa = true) or + (reduced_functionality /= "NO")) then + zero_dataa := true; + else + if (denormal_support = "YES") then + den_dataa := true; + else + zero_dataa := true; + end if; + end if; + elsif (exp_dataa = (2**width_exp) -1) then + if (zero_mant_dataa = true) then + inf_dataa := true; + else + nan_dataa := true; + end if; + end if; + + --check whether datab is special input + zero_datab := false; + den_datab := false; + inf_datab := false; + nan_datab := false; + if (exp_datab = 0) then + if ((zero_mant_datab = true) or + (reduced_functionality /= "NO")) then + zero_datab := true; + else + if (denormal_support = "YES") then + den_datab := true; + else + zero_datab := true; + end if; + end if; + elsif (exp_datab = (2**width_exp) -1) then + if (zero_mant_datab = true) then + inf_datab := true; + else + nan_datab := true; + end if; + end if; + + --set status flag if special input exists + no_multiply := false; + if (nan_dataa or nan_datab or (inf_dataa and zero_datab) or + (inf_datab and zero_dataa)) then + temp_result(0)(WIDTH_MAN_EXP + 6) := '1'; --NaN + temp_result(0)(WIDTH_MAN_EXP - 1 downto width_man -1) := (others => '1'); + no_multiply := true; + elsif (zero_dataa) then + temp_result(0)(WIDTH_MAN_EXP + 3) := '1'; --zero result + temp_result(0)(WIDTH_MAN_EXP downto 0) := (others => '0'); + no_multiply := true; + elsif (zero_datab) then + temp_result(0)(WIDTH_MAN_EXP + 3) := '1'; --zero result + temp_result(0)(WIDTH_MAN_EXP downto 0) := (others => '0'); + no_multiply := true; + elsif (inf_dataa) then + temp_result(0)(WIDTH_MAN_EXP + 1) := '1'; --overflow + temp_result(0)(WIDTH_MAN_EXP downto 0) := dataa; --result + no_multiply := true; + elsif (inf_datab) then + temp_result(0)(WIDTH_MAN_EXP + 1) := '1'; --overflow + temp_result(0)(WIDTH_MAN_EXP downto 0) := datab; --result + no_multiply := true; + end if; + + -- do multiplication + if (no_multiply = false) then + + --perform exponent operation + exp_result := (exp_dataa + exp_datab) - ((2**(width_exp -1)) - 1); + + -- mantissa multiplication + --first operand for multiplication + mant_dataa(width_man downto 0) := "1" & dataa(width_man - 1 downto 0); + + --second operand for multiplication + mant_datab(width_man downto 0) := "1" & datab(width_man - 1 downto 0); + + --multiplication using add and shift algorithm + for i in 0 to width_man loop + cout := '0'; + if (mant_dataa(i) = '1') then + add_bits(mant_datab, mant_result, cout); + end if; + shift_right(cout, mant_result); + end loop; + sticky_bit := '0'; + mant_result_msb := mant_result(mant_result'high); + --Normalize the Result + if (mant_result_msb = '1') then + sticky_bit := mant_result(mant_result'low); + shift_right('0', mant_result); + exp_result := exp_result + 1; + end if; + round_bit := mant_result(width_man - 1); + guard_bit := mant_result(width_man); + no_rounding := false; + + -- check whether should perform rounding or not + if (round_bit = '0') then + no_rounding := true; + else + if (reduced_functionality = "NO") then + for i in 0 to width_man - 2 loop + sticky_bit := sticky_bit or mant_result(i); + end loop; + else + sticky_bit := (mant_result(width_man - 2) and + mant_result_msb); + end if; + + if ((sticky_bit = '0') and (guard_bit = '0')) then + no_rounding := true; + end if; + + end if; + if (no_rounding = false) then + --do rounding + carry := true; + for i in width_man to mant_result'high loop + if (carry = true) then + if (mant_result(i) = '0') then + mant_result(i) := '1'; + carry := false; + else + mant_result(i) := '0'; + end if; + end if; + end loop; + + -- If the mantissa of the result is 10.00.. after rounding, right shift the + -- mantissa of the result by 1 bit and increase the exponent of the result by 1. + if (mant_result(mant_result'high) = '1') then + shift_right('0', mant_result); + exp_result := exp_result + 1; + end if; + end if; + + --Normalize the Result + if ((not bit_all_0(mant_result)) and (mant_result(mant_result'high -1) = '0')) then + while ((mant_result(mant_result'high -1) = '0') and (exp_result /= 0)) loop + shift_left(mant_result); + exp_result := exp_result - 1; + end loop; + elsif ((exp_result < 0) and (exp_result >= - (2 * width_man))) then + while (exp_result /= 0) loop + shift_right('0', mant_result); + exp_result := exp_result + 1; + end loop; + end if; + + --set status flag "indefinite" if normal * denormal + --(ignore other status port since we dont care the output + if (den_dataa or den_datab) then + temp_result(0)(WIDTH_MAN_EXP + 5) := '1'; --indefinite + --set status flag if special output exists + elsif (exp_result >= ((2**width_exp) - 1)) then + temp_result(0)(WIDTH_MAN_EXP + 1) := '1'; --overflow + elsif (exp_result < 0) then + temp_result(0)(WIDTH_MAN_EXP + 2) := '1'; --underflow + temp_result(0)(WIDTH_MAN_EXP + 3) := '1'; --zero + elsif (exp_result = 0) then + temp_result(0)(WIDTH_MAN_EXP + 2) := '1'; --underflow + if (bit_all_0 (mant_result, width_man + 1, mant_result'high -1)) then + temp_result(0)(WIDTH_MAN_EXP + 3) := '1'; --zero + else + temp_result(0)(WIDTH_MAN_EXP + 4) := '1'; --denormal + end if; + end if; + + --get result mantissa + if (exp_result < 0) then --result underflow + temp_result(0)(width_man - 1 downto 0) := (others => '0'); + elsif (exp_result = 0) then --denormalized output + if ((reduced_functionality = "NO") and (denormal_support = "YES")) then + for i in (mant_result'high - 1) downto (mant_result'high - width_man) loop + temp_result(0)(i - width_man - 1) := mant_result(i); + end loop; + else + temp_result(0)(width_man - 1 downto 0) := (others => '0'); + temp_result(0)(WIDTH_MAN_EXP + 3) := '1'; + end if; + elsif exp_result >= ((2**width_exp) -1) then --result overflow + temp_result(0)(width_man - 1 downto 0) := (others => '0'); + elsif (exp_result > 0) then --normalized output + for i in (mant_result'high - 2) downto (mant_result'high - width_man - 1) loop + temp_result(0)(i - width_man) := mant_result(i); + end loop; + end if; + + --get result exponent + if (exp_result <= 0) then + temp_result(0)(WIDTH_MAN_EXP -1 downto width_man) := (others => '0'); + elsif (exp_result >= ((2**width_exp) -1)) then + for i in width_man to (WIDTH_MAN_EXP -1) loop + temp_result(0)(i) := '1'; + end loop; + else + --convert integer to binary bit + for i in width_man to (WIDTH_MAN_EXP -1) loop + if ((exp_result mod 2) = 1) then + temp_result(0)(i) := '1'; + else + temp_result(0)(i) := '0'; + end if; + exp_result := exp_result / 2; + end loop; + end if; + end if; + + --get result sign + temp_result(0)(WIDTH_MAN_EXP) := dataa(dataa'high) xor datab(datab'high); + end if; + end if; + + --output port + result <= temp_result(LATENCY)(WIDTH_MAN_EXP downto 0 ); + overflow <= temp_result(LATENCY)(WIDTH_MAN_EXP + 1 ); + + if ((reduced_functionality = "YES") or (denormal_support = "YES")) then + underflow <= temp_result(LATENCY)(WIDTH_MAN_EXP + 2 ); + else + underflow <= '0'; + end if; + + if (reduced_functionality = "NO") then + zero <= temp_result(LATENCY)(WIDTH_MAN_EXP + 3 ); + + if (denormal_support = "YES") then + denormal <= temp_result(LATENCY)(WIDTH_MAN_EXP + 4 ); + indefinite <= temp_result(LATENCY)(WIDTH_MAN_EXP + 5 ); + else + denormal <= '0'; + indefinite <= '0'; + end if; + else + zero <= '0'; + denormal <= '0'; + indefinite <= '0'; + end if; + nan <= temp_result(LATENCY)(WIDTH_MAN_EXP + 6 ); + + end process MULTIPLY_FP; + +end behavior; -- altfp_mult +-- END OF ARCHITECTURE + +-- START ENTITY HEADER --------------------------------------------------------- +-- +-- Entity Name : altsqrt +-- +-- Description : Parameterized integer square root megafunction. +-- This module computes q[] and remainder so that +-- q[]^2 + remainder[] == radical[] (remainder <= 2 * q[]) +-- It can support the sequential mode(pipeline > 0) or +-- combinational mode (pipeline = 0). +-- +-- Limitations : The radical is assumed to be unsigned integer. +-- +--Results expected : Square root of the radical and the remainder. + +-- END ENTITY HEADER ----------------------------------------------------------- + + +-- LIBRARY USED +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use work.ALTERA_COMMON_CONVERSION.all; + +-- ENTITY DECLARATION +entity altsqrt is + +-- GENERIC DECLARATION + generic ( + q_port_width : natural := 1; -- The width of the q port + r_port_width : natural := 1; -- The width of the remainder port + width : natural := 1; -- The width of the radical + pipeline : natural := 0; -- The latency for the output + -- (0 for comb. mode) + lpm_hint : string := "UNUSED"; + lpm_type : string := "altsqrt" ); + +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + + -- Input port for the radical + radical : in std_logic_vector(width - 1 downto 0); + + -- Clock port + clk : in std_logic := '1'; + + -- Clock enable port + ena : in std_logic := '1'; + + -- Asynchronous clear port + aclr : in std_logic := '0'; + +-- OUTPUT PORT DECLARATION + + -- Output port for returning the square root of the radical + q : out std_logic_vector( q_port_width - 1 downto 0) + := (others => '0'); + + -- Output port for returning the remainder of the square root. + remainder : out std_logic_vector( r_port_width - 1 downto 0) + := (others => '0') ); + +end altsqrt; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE +architecture behavior of altsqrt is + +-- TYPE DECLARATION +type PIPELINE_Q is array (pipeline downto 0) of std_logic_vector( q_port_width - 1 downto 0); +type PIPELINE_R is array (pipeline downto 0) of std_logic_vector( r_port_width - 1 downto 0); + +-- SIGNAL DECLARATION +signal q_pipe : std_logic_vector (q_port_width - 1 downto 0) + := (others => '0'); +signal q_value : std_logic_vector (q_port_width - 1 downto 0) + := (others => '0'); +signal remainder_pipe : std_logic_vector (r_port_width - 1 downto 0) + := (others => '0'); +signal remainder_value : std_logic_vector (r_port_width - 1 downto 0) + := (others => '0'); + +begin + +-- SIGNAL ASSIGNMENTS + q <= q_pipe when (pipeline > 0) else q_value; + remainder <= remainder_pipe when (pipeline > 0) else remainder_value; + +-- PROCESS DECLARATION + + -- Perform square root calculation. + -- In general, below are the steps to calculate the square root and the + -- remainder. + -- + -- Start of with q = 0 and remainder= 0 + -- For every iteration, do the same thing: + -- 1) Shift in the next 2 bits of the radical into the remainder + -- Eg. if the radical is b"101100". For the first iteration, + -- the remainder will be equal to b"10". + -- 2) Compare it to the 4* q + 1 + -- 3) if the remainder is greater than or equal to 4*q + 1 + -- remainder = remainder - (4*q + 1) + -- q = 2*q + 1 + -- otherwise + -- q = 2*q + SQUARE_ROOT: process(radical) + variable value1 : integer := 0; + variable value2 : integer := 0; + variable i : integer := 0; + variable index : integer := 0; + variable q_index : integer := 0; + variable q_temp : std_logic_vector (q_port_width - 1 downto 0) + := (others => '0'); + variable q_value_temp : std_logic_vector (q_port_width - 1 downto 0) + := (others => '0'); + variable q_value_comp : std_logic_vector (r_port_width downto 0) + := (others => '0'); + variable r_temp : std_logic_vector (r_port_width downto 0) + := (others => '0'); + variable radical_tmp : std_logic_vector(width - 1 downto 0) + := (others => '0'); + begin + + -- Check for illegal mode + if (width < 1) then + ASSERT FALSE + REPORT "width (" & INT_TO_STR_ARITH(width) & ") must be greater than 0." + SEVERITY ERROR; + end if; + + -- Reset variables + value1 := 0; + value2 := 0; + q_index := (width - 1) / 2; + index := width; + q_temp := (others => '0'); + q_value_temp := (others => '0'); + q_value_comp := (others => '0'); + r_temp := (others => '0'); + radical_tmp := radical; + + -- If the number of the bits of the radical is an odd number, + -- Then for the first iteration, only the 1st bit will be shifted + -- into the remainder. + -- Eg. if the radical is b"11111", then the remainder is b"01". + if ((width rem 2) = 1) then + value1 := 0; + + if (radical_tmp(width - 1) = '1') then + value2 := 1; + else + value2 := 0; + end if; + + index := index + 1; + elsif (width > 1) then + -- Otherwise, for the first iteration, the first two bits will be + -- shifted into the remainder. + -- Eg. if the radical is b"101111", then the remainder is b"10". + if (radical_tmp(width - 1) = '1') then + value1 := 1; + else + value1 := 0; + end if; + + if (radical_tmp(width - 2) = '1') then + value2 := 1; + else + value2 := 0; + end if; + + end if; + + -- For every iteration + while (index >= 2) loop + -- Get the remainder value by shifting in the next 2 bits + -- of the radical into the remainder + r_temp := r_temp(r_port_width-2 downto 0) & conv_std_logic_vector(value1, 1) & conv_std_logic_vector(value2, 1); + q_value_comp := q_value_temp(q_port_width-1 downto 0) & conv_std_logic_vector(1, 2); + + -- if remainder >= (4*q + 1) + if (r_temp >= q_value_comp) then + -- remainder = remainder - (4*q + 1) + r_temp := r_temp - q_value_comp; + -- q = 2*q + 1 + q_value_temp := q_value_temp(q_port_width-2 downto 0) & conv_std_logic_vector(1, 1); + -- set the q[q_index] = 1 + q_temp(q_index) := '1'; + else -- if remainder < (4*q + 1) + -- q = 2*q + q_value_temp := q_value_temp(q_port_width-2 downto 0) & '0'; + -- set the q[q_index] = 0 + q_temp(q_index) := '0'; + end if; + + index := index - 2; + + -- if not the last iteration, get the next 2 bits of the radical + if (index >= 2) then + if (radical(index - 1) = '1') then + value1 := 1; + else + value1 := 0; + end if; + + if (radical(index - 2) = '1') then + value2 := 1; + else + value2 := 0; + end if; + end if; + + -- Reduce the current index of q by 1 + q_index := q_index - 1; + + end loop; + + -- Store current result into the pipeline to create latency + q_value <= q_temp; + remainder_value <= r_temp(r_port_width-1 downto 0); + + end process SQUARE_ROOT; + + PIPELINE_REG : process(clk, aclr) + variable pipe_ptr : natural := 0; + variable q_pipeline : PIPELINE_Q := (others => (others => '0')); + variable remainder_pipeline : PIPELINE_R := (others => (others => '0')); + begin + -- if asynchronous clear signal has been asserted + if (aclr = '1') then + -- reset pipelines and clear the output ports + q_pipeline := (others => (others => '0')); + remainder_pipeline := (others => (others => '0')); + q_pipe <= (others => '0'); + remainder_pipe <= (others => '0'); + + elsif (rising_edge(clk)) then + if (ena = '1') then + q_pipeline(pipe_ptr) := q_value; + remainder_pipeline(pipe_ptr) := remainder_value; + + if (pipeline > 1) then + pipe_ptr := (pipe_ptr + 1) mod pipeline; + end if; + + q_pipe <= q_pipeline(pipe_ptr); + remainder_pipe <= remainder_pipeline(pipe_ptr); + end if; + end if; + end process PIPELINE_REG; + +end behavior; -- altsqrt +-- END OF ARCHITECTURE + +-- START ENTITY HEADER --------------------------------------------------------- +-- +-- Entity Name : ALTCLKLOCK +-- +-- Description : Phase-Locked Loop (PLL) behavioral model. Supports basic +-- PLL features such as multiplication and division of input +-- clock frequency and phase shift. +-- +-- Limitations : Model supports NORMAL operation mode only. External +-- feedback mode and zero-delay-buffer mode are not simulated. +-- +-- Expected results : Up to 4 clock outputs (clock0, clock1, clock2, clock_ext). +-- locked output indicates when PLL locks. +-- +-- END ENTITY HEADER ----------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.ALTERA_DEVICE_FAMILIES.all; + +-- ENTITY DECLARATION +entity altclklock is +generic( + inclock_period : natural := 10000; -- units in ps + inclock_settings : string := "UNUSED"; + valid_lock_cycles : natural := 5; + invalid_lock_cycles : natural := 5; + valid_lock_multiplier : natural := 5; + invalid_lock_multiplier : natural := 5; + operation_mode : string := "NORMAL"; + clock0_boost : natural := 1; + clock0_divide : natural := 1; + clock0_settings : string := "UNUSED"; + clock0_time_delay : string := "0"; + clock1_boost : natural := 1; + clock1_divide : natural := 1; + clock1_settings : string := "UNUSED"; + clock1_time_delay : string := "0"; + clock2_boost : natural := 1; + clock2_divide : natural := 1; + clock2_settings : string := "UNUSED"; + clock2_time_delay : string := "0"; + clock_ext_boost : natural := 1; + clock_ext_divide : natural := 1; + clock_ext_settings : string := "UNUSED"; + clock_ext_time_delay : string := "0"; + outclock_phase_shift : natural := 0; -- units in ps + intended_device_family : string := "Stratix" ; + lpm_type : string := "altclklock"; + lpm_hint : string := "UNUSED" +); +port( + inclock : in std_logic; -- required port, input reference clock + inclocken : in std_logic := '1'; -- PLL enable signal + fbin : in std_logic := '1'; -- feedback input for the PLL + + clock0 : out std_logic; -- clock0 output + clock1 : out std_logic; -- clock1 output + clock2 : out std_logic; -- clock2 output + clock_ext : out std_logic; -- external clock output + locked : out std_logic -- PLL lock signal +); + +-- +-- function time_delay - converts time_delay in string format to time, and +-- add result to outclock_phase_shift +-- +function time_delay (s : string) return time is + -- VARIABLE DECLARATION + variable outclock_phase_shift_adj : integer := 0; + variable len : integer := s'length; + variable sign : integer := 1; + variable digit : integer := 0; + +begin + for i in 1 to len loop + case s(i) is + when '-' => + if (i = 1) then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + + outclock_phase_shift_adj := (outclock_phase_shift_adj * 10) + digit; + end loop; + + -- add outclock phase shift to the time delay + outclock_phase_shift_adj := outclock_phase_shift + (sign * outclock_phase_shift_adj); + + -- adjust phase shift so that it is between 0 and 1 full inclock_period + while (outclock_phase_shift_adj < 0) loop + outclock_phase_shift_adj := outclock_phase_shift_adj + inclock_period; + end loop; + while (outclock_phase_shift_adj >= inclock_period) loop + outclock_phase_shift_adj := outclock_phase_shift_adj - inclock_period; + end loop; + + -- return the phase shift in ps + return (outclock_phase_shift_adj * 1 ps); +end; + +end altclklock; +-- END ENTITY DECLARATION + +-- BEGINNING OF ARCHITECTURE BEHAVIOR +architecture behavior of altclklock is + -- SIGNAL DECLARATION + +SIGNAL pll_lock : std_logic := '0'; +SIGNAL check_lock : std_logic := '0'; + +SIGNAL clk0_tmp : std_logic := 'X'; +SIGNAL clk1_tmp : std_logic := 'X'; +SIGNAL clk2_tmp : std_logic := 'X'; +SIGNAL extclk_tmp : std_logic := 'X'; +begin + +-- checking for invalid parameters +MSG: process +begin + if (inclock_period <= 0) then + ASSERT FALSE + REPORT "The period of the input clock (inclock_period) must be greater than 0" + SEVERITY ERROR; + end if; + + if ((clock0_boost <= 0) or (clock0_divide <= 0)) then + ASSERT FALSE + REPORT "The multiplication and division factors for clock0 must be greater than 0" + SEVERITY ERROR; + end if; + + if ((clock1_boost <= 0) or (clock1_divide <= 0)) then + ASSERT FALSE + REPORT "The multiplication and division factors for clock1 must be greater than 0" + SEVERITY ERROR; + end if; + + if ((clock2_boost <= 0) or (clock2_divide <= 0)) then + ASSERT FALSE + REPORT "The multiplication and division factors for clock2 must be greater than 0" + SEVERITY ERROR; + end if; + + if ((clock_ext_boost <= 0) or (clock_ext_divide <= 0)) then + ASSERT FALSE + REPORT "The multiplication and division factors for clock_ext must be greater than 0" + SEVERITY ERROR; + end if; + + if (FEATURE_FAMILY_STRATIX(intended_device_family) = false) then + ASSERT FALSE + REPORT "Device family specified by the intended_device_family parameter, "& intended_device_family &", may not be supported by altclklock" + SEVERITY WARNING; + end if; + wait; + +end process MSG; + +LOCK: process(inclock, inclocken, pll_lock, check_lock) + -- VARIABLE DECLARATION + variable inclk_ps : time := 0 ps; + variable violation : boolean := false; + variable pll_lock_tmp : std_logic := '0'; + variable start_lock_count, stop_lock_count : integer := 0; + variable pll_last_rising_edge, pll_last_falling_edge : time := 0 ps; + variable pll_rising_edge_count : integer := 0; + variable pll_cycle, pll_duty_cycle : time := 0 ps; + variable expected_next_clk_edge : time := 0 ps; + variable clk_per_tolerance : time := 0 ps; + + variable last_synchronizing_rising_edge_for_clk0 : time := 0 ps; + variable last_synchronizing_rising_edge_for_clk1 : time := 0 ps; + variable last_synchronizing_rising_edge_for_clk2 : time := 0 ps; + variable last_synchronizing_rising_edge_for_extclk : time := 0 ps; + variable input_cycles_per_clk0 : integer := clock0_divide; + variable input_cycles_per_clk1 : integer := clock1_divide; + variable input_cycles_per_clk2 : integer := clock2_divide; + variable input_cycles_per_extclk : integer := clock_ext_divide; + variable input_cycle_count_to_sync0 : integer := 0; + variable input_cycle_count_to_sync1 : integer := 0; + variable input_cycle_count_to_sync2 : integer := 0; + variable input_cycle_count_to_sync_extclk : integer := 0; + variable init : boolean := true; + variable output_value : std_logic := '0'; + variable vco_per : time := 0 ps; + variable high_time : time := 0 ps; + variable low_time : time := 0 ps; + variable sched_time : time := 0 ps; + variable tmp_per : integer := 0; + variable temp, tmp_rem, my_rem : integer := 0; + variable inc : integer := 1; + variable cycle_to_adjust : integer := 0; + variable clk0_synchronizing_period, clk1_synchronizing_period : time; + variable clk2_synchronizing_period, extclk_synchronizing_period : time; + variable clk0_cycles_per_sync_period : integer := clock0_boost; + variable clk1_cycles_per_sync_period : integer := clock1_boost; + variable clk2_cycles_per_sync_period : integer := clock2_boost; + variable extclk_cycles_per_sync_period : integer := clock_ext_boost; + variable schedule_clk0, schedule_clk1 : boolean := false; + variable schedule_clk2, schedule_extclk : boolean := false; + variable clk0_phase_delay : time := time_delay(clock0_time_delay); + variable clk1_phase_delay : time := time_delay(clock1_time_delay); + variable clk2_phase_delay : time := time_delay(clock2_time_delay); + variable extclk_phase_delay : time := time_delay(clock_ext_time_delay); + +begin + if (init) then + if ((clock0_boost rem clock0_divide) = 0) then + clk0_cycles_per_sync_period := clock0_boost / clock0_divide; + input_cycles_per_clk0 := 1; + end if; + if ((clock1_boost rem clock1_divide) = 0) then + clk1_cycles_per_sync_period := clock1_boost / clock1_divide; + input_cycles_per_clk1 := 1; + end if; + if ((clock2_boost rem clock2_divide) = 0) then + clk2_cycles_per_sync_period := clock2_boost / clock2_divide; + input_cycles_per_clk2 := 1; + end if; + if ((clock_ext_boost rem clock_ext_divide) = 0) then + extclk_cycles_per_sync_period := clock_ext_boost / clock_ext_divide; + input_cycles_per_extclk := 1; + end if; + + clk_per_tolerance := (0.1 * real(inclock_period)) * 1 ps; + + init := false; + end if; + + if (inclocken = '0') then + pll_lock_tmp := '0'; + pll_rising_edge_count := 0; + elsif (inclock'event and inclock = '1') then + if (pll_lock_tmp = '1') then + check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0; + end if; + if pll_rising_edge_count = 0 then -- at 1st rising edge + inclk_ps := (inclock_period / 1) * 1 ps; + pll_duty_cycle := inclk_ps/2; + elsif pll_rising_edge_count = 1 then -- at 2nd rising edge + pll_cycle := now - pll_last_rising_edge; -- calculate period + if ((NOW - pll_last_rising_edge) < (inclk_ps - clk_per_tolerance) or + (NOW - pll_last_rising_edge) > (inclk_ps + clk_per_tolerance)) then + ASSERT FALSE + REPORT "Inclock_Period Violation" + SEVERITY WARNING; + violation := true; + if (pll_lock = '1') then + stop_lock_count := stop_lock_count + 1; + if (stop_lock_count = invalid_lock_cycles) then + pll_lock_tmp := '0'; + ASSERT FALSE + REPORT "altclklock out of lock." + SEVERITY WARNING; + end if; + else + start_lock_count := 1; + end if; + else + violation := false; + end if; + if ((now - pll_last_falling_edge) < (pll_duty_cycle - clk_per_tolerance/2) or + (now - pll_last_falling_edge) > (pll_duty_cycle + clk_per_tolerance/2)) then + ASSERT FALSE + REPORT "Duty Cycle Violation" + SEVERITY WARNING; + violation := true; + else + violation := false; + end if; + else + pll_cycle := now - pll_last_rising_edge; -- calculate period + if ((now - pll_last_rising_edge) < (inclk_ps - clk_per_tolerance) or + (now - pll_last_rising_edge) > (inclk_ps + clk_per_tolerance)) then + ASSERT FALSE + REPORT "Cycle Violation" + SEVERITY WARNING; + violation := true; + if (pll_lock = '1') then + stop_lock_count := stop_lock_count + 1; + if (stop_lock_count = invalid_lock_cycles) then + pll_lock_tmp := '0'; + ASSERT FALSE + REPORT "altclklock out of lock." + SEVERITY WARNING; + end if; + else + start_lock_count := 1; + end if; + else + violation := false; + end if; + end if; + pll_last_rising_edge := now; + pll_rising_edge_count := pll_rising_edge_count +1; + if (not violation) then + if (pll_lock_tmp = '1') then + input_cycle_count_to_sync0 := input_cycle_count_to_sync0 + 1; + if (input_cycle_count_to_sync0 = input_cycles_per_clk0) then + clk0_synchronizing_period := now - last_synchronizing_rising_edge_for_clk0; + last_synchronizing_rising_edge_for_clk0 := now; + schedule_clk0 := true; + input_cycle_count_to_sync0 := 0; + end if; + input_cycle_count_to_sync1 := input_cycle_count_to_sync1 + 1; + if (input_cycle_count_to_sync1 = input_cycles_per_clk1) then + clk1_synchronizing_period := now - last_synchronizing_rising_edge_for_clk1; + last_synchronizing_rising_edge_for_clk1 := now; + schedule_clk1 := true; + input_cycle_count_to_sync1 := 0; + end if; + input_cycle_count_to_sync2 := input_cycle_count_to_sync2 + 1; + if (input_cycle_count_to_sync2 = input_cycles_per_clk2) then + clk2_synchronizing_period := now - last_synchronizing_rising_edge_for_clk2; + last_synchronizing_rising_edge_for_clk2 := now; + schedule_clk2 := true; + input_cycle_count_to_sync2 := 0; + end if; + input_cycle_count_to_sync_extclk := input_cycle_count_to_sync_extclk + 1; + if (input_cycle_count_to_sync_extclk = input_cycles_per_extclk) then + extclk_synchronizing_period := now - last_synchronizing_rising_edge_for_extclk; + last_synchronizing_rising_edge_for_extclk := now; + schedule_extclk := true; + input_cycle_count_to_sync_extclk := 0; + end if; + else + start_lock_count := start_lock_count + 1; + if (start_lock_count >= valid_lock_cycles) then + pll_lock_tmp := '1'; + input_cycle_count_to_sync0 := 0; + input_cycle_count_to_sync1 := 0; + input_cycle_count_to_sync2 := 0; + input_cycle_count_to_sync_extclk := 0; + clk0_synchronizing_period := ((pll_cycle/1 ps) * input_cycles_per_clk0) * 1 ps; + clk1_synchronizing_period := ((pll_cycle/1 ps) * input_cycles_per_clk1) * 1 ps; + clk2_synchronizing_period := ((pll_cycle/1 ps) * input_cycles_per_clk2) * 1 ps; + extclk_synchronizing_period := ((pll_cycle/1 ps) * input_cycles_per_extclk) * 1 ps; + last_synchronizing_rising_edge_for_clk0 := now; + last_synchronizing_rising_edge_for_clk1 := now; + last_synchronizing_rising_edge_for_clk2 := now; + last_synchronizing_rising_edge_for_extclk := now; + schedule_clk0 := true; + schedule_clk1 := true; + schedule_clk2 := true; + schedule_extclk := true; + end if; + end if; + else + start_lock_count := 1; + end if; + + elsif (inclock'event and inclock= '0') then + if (pll_lock_tmp = '1') then + check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0; + if (now > 0 ns and ((now - pll_last_rising_edge) < (pll_duty_cycle - clk_per_tolerance/2) or + (now - pll_last_rising_edge) > (pll_duty_cycle + clk_per_tolerance/2))) then + ASSERT FALSE + REPORT "Duty Cycle Violation" + SEVERITY WARNING; + violation := true; + if (pll_lock = '1') then + stop_lock_count := stop_lock_count + 1; + if (stop_lock_count = invalid_lock_cycles) then + pll_lock_tmp := '0'; + ASSERT FALSE + REPORT "altclklock out of lock." + SEVERITY WARNING; + end if; + end if; + else + violation := false; + end if; + else + start_lock_count := start_lock_count + 1; + end if; + pll_last_falling_edge := now; + else + if pll_lock_tmp = '1' then + if (inclock = '1') then + expected_next_clk_edge := pll_last_rising_edge + (inclk_ps+clk_per_tolerance)/2.0; + else + expected_next_clk_edge := pll_last_falling_edge + (inclk_ps+clk_per_tolerance)/2.0; + end if; + violation := false; + if (now < expected_next_clk_edge) then + check_lock <= not check_lock after (expected_next_clk_edge - now); + elsif (now = expected_next_clk_edge) then + check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0; + else + ASSERT FALSE + REPORT "Inclock_Period Violation" + SEVERITY WARNING; + violation := true; + if (pll_lock = '1') then + stop_lock_count := stop_lock_count + 1; + if (stop_lock_count = invalid_lock_cycles) then + pll_lock_tmp := '0'; + ASSERT FALSE + REPORT "altclklock out of lock." + SEVERITY WARNING; + else + check_lock <= not check_lock after (inclk_ps/2.0); + end if; + end if; + end if; + end if; + end if; + pll_lock <= pll_lock_tmp; + if (pll_lock'event and pll_lock = '0') then + start_lock_count := 1; + + stop_lock_count := 0; + clk0_tmp <= 'X'; + clk1_tmp <= 'X'; + clk2_tmp <= 'X'; + extclk_tmp <= 'X'; + end if; + + -- clock0 output + if (schedule_clk0 = true) then + -- initialize variables + sched_time := clk0_phase_delay; + cycle_to_adjust := 0; + inc := 1; + output_value := '1'; + temp := clk0_synchronizing_period / 1 ps; + my_rem := temp rem clk0_cycles_per_sync_period; + + -- schedule number of output clock + -- cycles in this loop in order to synchronize the output clock to the + -- input clock - to get rid of drifting for cases where the input clock + -- period is not always divisible + for i in 1 to clk0_cycles_per_sync_period loop + tmp_per := temp/clk0_cycles_per_sync_period; + if ((my_rem /= 0) and (inc <= my_rem)) then + tmp_rem := (clk0_cycles_per_sync_period * inc) rem my_rem; + cycle_to_adjust := (clk0_cycles_per_sync_period * inc) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + + -- if this cycle is the one to adjust the output period in, then + -- increment the period by 1 unit + if (cycle_to_adjust = i) then + tmp_per := tmp_per + 1; + inc := inc + 1; + end if; + + -- adjust the high and low cycle period + vco_per := tmp_per * 1 ps; + high_time := (tmp_per / 2) * 1 ps; + if ((tmp_per rem 2) /= 0) then + high_time := high_time + 1 ps; + end if; + + low_time := vco_per - high_time; + + -- schedule the high and low cycle of 1 output clock period + for j in 1 to 2 loop + clk0_tmp <= transport output_value after sched_time; + output_value := not output_value; + if (output_value = '0') then + sched_time := sched_time + high_time; + elsif (output_value = '1') then + sched_time := sched_time + low_time; + end if; + end loop; + end loop; + + -- reset schedule_clk0 + schedule_clk0 := false; + end if; -- schedule_clk0 + + if (schedule_clk1 = true) then + -- initialize variables + sched_time := clk1_phase_delay; + cycle_to_adjust := 0; + inc := 1; + output_value := '1'; + temp := clk1_synchronizing_period / 1 ps; + my_rem := temp rem clk1_cycles_per_sync_period; + + -- schedule number of output clock + -- cycles in this loop in order to synchronize the output clock to the + -- input clock - to get rid of drifting for cases where the input clock + -- period is not always divisible + for i in 1 to clk1_cycles_per_sync_period loop + tmp_per := temp/clk1_cycles_per_sync_period; + if ((my_rem /= 0) and (inc <= my_rem)) then + tmp_rem := (clk1_cycles_per_sync_period * inc) rem my_rem; + cycle_to_adjust := (clk1_cycles_per_sync_period * inc) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + + -- if this cycle is the one to adjust the output period in, then + -- increment the period by 1 unit + if (cycle_to_adjust = i) then + tmp_per := tmp_per + 1; + inc := inc + 1; + end if; + + -- adjust the high and low cycle period + vco_per := tmp_per * 1 ps; + high_time := (tmp_per/2) * 1 ps; + if ((tmp_per rem 2) /= 0) then + high_time := high_time + 1 ps; + end if; + + low_time := vco_per - high_time; + + -- schedule the high and low cycle of 1 output clock period + for j in 1 to 2 loop + clk1_tmp <= transport output_value after sched_time; + output_value := not output_value; + if (output_value = '0') then + sched_time := sched_time + high_time; + elsif (output_value = '1') then + sched_time := sched_time + low_time; + end if; + end loop; + end loop; + + -- reset schedule_clk1 + schedule_clk1 := false; + end if; -- schedule_clk1 + + if (FEATURE_FAMILY_STRATIX(intended_device_family)) then + -- clock2 output + if (schedule_clk2 = true) then + -- initialize variables + sched_time := clk2_phase_delay; + cycle_to_adjust := 0; + inc := 1; + output_value := '1'; + temp := clk2_synchronizing_period/1 ps; + my_rem := temp rem clk2_cycles_per_sync_period; + + -- schedule number of output clock + -- cycles in this loop in order to synchronize the output clock to the + -- input clock - to get rid of drifting for cases where the input clock + -- period is not always divisible + for i in 1 to clk2_cycles_per_sync_period loop + tmp_per := temp/clk2_cycles_per_sync_period; + if ((my_rem /= 0) and (inc <= my_rem)) then + tmp_rem := (clk2_cycles_per_sync_period * inc) rem my_rem; + cycle_to_adjust := (clk2_cycles_per_sync_period * inc) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + + -- if this cycle is the one to adjust the output period in, then + -- increment the period by 1 unit + if (cycle_to_adjust = i) then + tmp_per := tmp_per + 1; + inc := inc + 1; + end if; + + -- adjust the high and low cycle period + vco_per := tmp_per * 1 ps; + high_time := (tmp_per/2) * 1 ps; + if ((tmp_per rem 2) /= 0) then + high_time := high_time + 1 ps; + end if; + + low_time := vco_per - high_time; + + -- schedule the high and low cycle of 1 output clock period + for j in 1 to 2 loop + clk2_tmp <= transport output_value after sched_time; + output_value := not output_value; + if (output_value = '0') then + sched_time := sched_time + high_time; + elsif (output_value = '1') then + sched_time := sched_time + low_time; + end if; + end loop; + end loop; + + -- reset schedule_clk2 + schedule_clk2 := false; + end if; -- schedule_clk2 + + -- clock_ext output + if (schedule_extclk = true) then + -- initialize variables + sched_time := extclk_phase_delay; + cycle_to_adjust := 0; + inc := 1; + output_value := '1'; + temp := extclk_synchronizing_period/1 ps; + my_rem := temp rem extclk_cycles_per_sync_period; + + -- schedule number of output clock + -- cycles in this loop in order to synchronize the output clock to the + -- input clock - to get rid of drifting for cases where the input clock + -- period is not always divisible + for i in 1 to extclk_cycles_per_sync_period loop + tmp_per := temp/extclk_cycles_per_sync_period; + if ((my_rem /= 0) and (inc <= my_rem)) then + tmp_rem := (extclk_cycles_per_sync_period * inc) rem my_rem; + cycle_to_adjust := (extclk_cycles_per_sync_period * inc) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + + -- if this cycle is the one to adjust the output period in, then + -- increment the period by 1 unit + if (cycle_to_adjust = i) then + tmp_per := tmp_per + 1; + inc := inc + 1; + end if; + + -- adjust the high and low cycle period + vco_per := tmp_per * 1 ps; + high_time := (tmp_per/2) * 1 ps; + if ((tmp_per rem 2) /= 0) then + high_time := high_time + 1 ps; + end if; + + low_time := vco_per - high_time; + + -- schedule the high and low cycle of 1 output clock period + for j in 1 to 2 loop + extclk_tmp <= transport output_value after sched_time; + output_value := not output_value; + if (output_value = '0') then + sched_time := sched_time + high_time; + elsif (output_value = '1') then + sched_time := sched_time + low_time; + end if; + end loop; + end loop; + + -- reset schedule_extclk + schedule_extclk := false; + end if; -- schedule_extclk + end if; + +end process LOCK; + + clock0 <= clk0_tmp; + clock1 <= clk1_tmp; + clock2 <= clk2_tmp; + clock_ext <= extclk_tmp; + locked <= pll_lock; + +end behavior; +-- END ARCHITECTURE BEHAVIOR +-- START ENTITY NAME ----------------------------------------------------------- +-- +-- Entity Name : ALTDDIO_IN +-- +-- Description : Double Data Rate (DDR) input behavioural model. Receives +-- data on both edges of the reference clock. +-- +-- Limitations : Not available for MAX device families. +-- +-- Expected results : Data sampled from the datain port at the rising edge of +-- the reference clock (dataout_h) and at the falling edge of +-- the reference clock (dataout_l). +-- +-- END ENTITY NAME ------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.ALTERA_DEVICE_FAMILIES.all; + +-- ENTITY DECLARATION +entity altddio_in is +generic ( + width : positive; -- required parameter + invert_input_clocks : string := "OFF"; + intended_device_family : string := "Stratix"; + power_up_high : string := "OFF"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altddio_in" +); +port ( + datain : in std_logic_vector(width-1 downto 0); -- required port, DDR + -- input data + inclock : in std_logic := '0'; -- input reference clock + inclocken : in std_logic := '1'; -- input clock enable signal + aset : in std_logic := '0'; -- asynchronous set + aclr : in std_logic := '0'; -- asynchronous clear + sset : in std_logic := '0'; -- synchronous set + sclr : in std_logic := '0'; -- synchronous clear + dataout_h : out std_logic_vector(width-1 downto 0); --data sampled at + --rising edge of inclock + dataout_l : out std_logic_vector(width-1 downto 0) --data sampled at + --falling edge of inclock +); +end altddio_in; +-- END ENTITY DECLARATION + +-- BEGINNING OF ARCHITECTURE BEHAVE +architecture behave of altddio_in is + + -- CONSTANT DECLARATION + constant IS_STRATIXIII : boolean := FEATURE_FAMILY_STRATIXIII(intended_device_family); + constant IS_STRATIX : boolean := FEATURE_FAMILY_STRATIX(intended_device_family); + constant IS_MAXII : boolean := FEATURE_FAMILY_MAXII(intended_device_family); + +begin + +-- checking for invalid parameters +MSG: process +begin + if (width <= 0) then + ASSERT FALSE + REPORT "The width parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (IS_VALID_FAMILY(intended_device_family) = false) then + ASSERT FALSE + REPORT intended_device_family & " is not a valid device family!" + SEVERITY ERROR; + end if; + + if (not ((IS_STRATIX and + (not IS_MAXII)))) then + ASSERT FALSE + REPORT "Megafunction altddio_in is not supported in " & intended_device_family &"!" + SEVERITY ERROR; + end if; + wait; +end process MSG; + + + + +process (inclock, aset, aclr) + -- VARIABLE DECLARATION + variable dataout_h_tmp : std_logic_vector(width-1 downto 0) + := (OTHERS=>'0'); + variable dataout_l_tmp : std_logic_vector(width-1 downto 0) + := (OTHERS=>'0'); + variable datain_latched : std_logic_vector(width-1 downto 0) + := (OTHERS=>'0'); + variable need_init : boolean := true; + +begin + -- power up registers according the power_up_high parameter setting + if ((NOW = 0 ps) or (need_init = true)) then + if (power_up_high = "OFF") then + dataout_h_tmp := (others => '0'); + dataout_l_tmp := (others => '0'); + datain_latched := (others => '0'); + else + dataout_h_tmp := (others => '1'); + dataout_l_tmp := (others => '1'); + datain_latched := (others => '1'); + end if; + need_init := false; + end if; + + -- asynchronous clear is asserted + if (aclr = '1') then + dataout_h_tmp := (others => '0'); + dataout_l_tmp := (others => '0'); + datain_latched := (others => '0'); + -- else asynchronous set is asserted + elsif (aset = '1') then + dataout_h_tmp := (others => '1'); + dataout_l_tmp := (others => '1'); + datain_latched := (others => '1'); + -- not being cleared or preset + -- rising edge of inclock + elsif (inclock'event and (inclock = '1')) then + if (inclocken = '1') then + if (invert_input_clocks = "ON") then + if (sclr = '1') then + datain_latched := (others => '0'); + elsif (sset = '1') then + datain_latched := (others => '1'); + else + datain_latched := datain; + end if; + else + if (IS_STRATIXIII) then + if (sclr = '1') then + dataout_h_tmp := (others => '0'); + dataout_l_tmp := (others => '0'); + elsif (sset = '1') then + dataout_h_tmp := (others => '1'); + dataout_l_tmp := (others => '1'); + else + dataout_h_tmp := datain; + dataout_l_tmp := datain_latched; + end if; + else + if (sclr = '1') then + dataout_h_tmp := (others => '0'); + elsif (sset = '1') then + dataout_h_tmp := (others => '1'); + else + dataout_h_tmp := datain; + end if; + dataout_l_tmp := datain_latched; + end if; + end if; + end if; + -- falling edge of inclock + elsif (inclock'event and (inclock = '0')) then + if ((IS_STRATIX and + (not IS_MAXII))) then + + if (inclocken = '1') then + if (invert_input_clocks = "ON") then + if (IS_STRATIXIII) then + if (sclr = '1') then + dataout_h_tmp := (others => '0'); + dataout_l_tmp := (others => '0'); + elsif (sset = '1') then + dataout_h_tmp := (others => '1'); + dataout_l_tmp := (others => '1'); + else + dataout_h_tmp := datain; + dataout_l_tmp := datain_latched; + end if; + else + if (sclr = '1') then + dataout_h_tmp := (others => '0'); + elsif (sset = '1') then + dataout_h_tmp := (others => '1'); + else + dataout_h_tmp := datain; + end if; + dataout_l_tmp := datain_latched; + end if; + else + if (sclr = '1') then + datain_latched := (others => '0'); + elsif (sset = '1') then + datain_latched := (others => '1'); + else + datain_latched := datain; + end if; + end if; + end if; + else -- for future families + if (invert_input_clocks = "ON") then + dataout_h_tmp := datain; + dataout_l_tmp := datain_latched; + else + datain_latched := datain; + end if; + end if; + end if; + + -- assign variables to output ports + dataout_l <= dataout_l_tmp; + dataout_h <= dataout_h_tmp; +end process; + +end behave; +-- END ARCHITECTURE BEHAVE + +-- START ENTITY NAME ----------------------------------------------------------- +-- +-- Entity Name : ALTDDIO_OUT +-- +-- Description : Double Data Rate (DDR) output behavioural model. +-- Transmits data on both edges of the reference clock. +-- +-- Limitations : Not available for MAX device families. +-- +-- Expected results : Double data rate output on dataout. +-- +--END ENTITY NAME ------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.ALTERA_DEVICE_FAMILIES.all; + +-- ENTITY DECLARATION +entity altddio_out is +generic ( + width : positive; -- required parameter + power_up_high : string := "OFF"; + oe_reg : string := "UNUSED"; + extend_oe_disable : string := "UNUSED"; + invert_output : string := "OFF"; + intended_device_family : string := "Stratix"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altddio_out" + ); +port ( + datain_h : in std_logic_vector(width-1 downto 0); --required port, data + --input for the rising + --edge of outclock + datain_l : in std_logic_vector(width-1 downto 0); --required port, data + --input for the falling + --edge of outclock + outclock : in std_logic; -- required port, input reference clock to output + -- data by + outclocken : in std_logic := '1'; -- clock enable signal for outclock + aset : in std_logic := '0'; -- asynchronous set + aclr : in std_logic := '0'; -- asynchronous clear + sset : in std_logic := '0'; -- synchronous set + sclr : in std_logic := '0'; -- synchronous clear + oe : in std_logic := '1'; -- output enable for dataout + dataout : out std_logic_vector(width-1 downto 0); -- DDR data output + oe_out : out std_logic_vector(width-1 downto 0) -- DDR data output +); +end altddio_out; +-- END ENTITY DECLARATION + +-- BEGINNING OF ARCHITECTURE BEHAVE +architecture behave of altddio_out is + + -- CONSTANT DECLARATION + constant INVERT_DATAOUT : boolean := FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO(intended_device_family) and + (invert_output = "ON"); + constant IS_STRATIXIII : boolean := FEATURE_FAMILY_STRATIXIII(intended_device_family); + constant IS_STRATIX : boolean := FEATURE_FAMILY_STRATIX(intended_device_family); + constant IS_MAXII : boolean := FEATURE_FAMILY_MAXII(intended_device_family); + + -- SIGNAL DECLARATION + signal outclock_dly : std_logic; + signal dataout_h : std_logic_vector(width-1 downto 0) := (OTHERS=>'0'); + signal dataout_l : std_logic_vector(width-1 downto 0) := (OTHERS=>'0'); + signal oe_rgd : std_logic := '0'; + signal oe_reg_ext : std_logic := '0'; + signal stratix_oe : std_logic; + signal output_enable : std_logic; + +begin + +-- checking for invalid parameters +MSG: process +begin + if (width <= 0) then + ASSERT FALSE + REPORT "The width parameter must be greater than 0" + SEVERITY ERROR; + end if; + + if (IS_VALID_FAMILY(intended_device_family) = false) then + ASSERT FALSE + REPORT intended_device_family & " is not a valid device family!" + SEVERITY ERROR; + end if; + + if (not ((IS_STRATIX and + (not IS_MAXII)))) then + ASSERT FALSE + REPORT "Megafunction altddio_out is not supported in " & intended_device_family &"!" + SEVERITY ERROR; + end if; + + wait; +end process MSG; + +outclock_dly <= outclock; + +-- output enable signals +output_enable <= stratix_oe when ((IS_STRATIX and + (not IS_MAXII))) + else oe; + +stratix_oe <= (oe_reg_ext and oe_rgd) + when (extend_oe_disable = "ON") + else oe_rgd + when ((oe_reg = "REGISTERED") and (extend_oe_disable /= "ON")) + else oe; + +oe_out <= (others => output_enable); + +REGS: process (outclock, aset, aclr) + -- VARIABLE DECLARATION + variable need_init : boolean := true; + +begin + -- power up the registers according to the power_up_high parameter setting + if ((NOW = 0 ps) or (need_init = true)) then + if (power_up_high = "OFF") then + dataout_h <= (others => '0'); + dataout_l <= (others => '0'); + oe_rgd <= '0'; + oe_reg_ext <= '0'; + else + dataout_h <= (others => '1'); + dataout_l <= (others => '1'); + oe_rgd <= '1'; + oe_reg_ext <= '1'; + end if; + need_init := false; + end if; + + -- asynchronous clear is asserted + if (aclr = '1') then + dataout_h <= (others => '0'); + dataout_l <= (others => '0'); + oe_rgd <= '0'; + oe_reg_ext <= '0'; + -- else if asynchronous set is asserted + elsif (aset = '1') then + dataout_h <= (others => '1'); + dataout_l <= (others => '1'); + oe_rgd <= '1'; + oe_reg_ext <= '1'; + -- else outclock is triggered + elsif ((outclock = '1') and outclock'event) then + -- rising edge of outclock + if (outclocken = '1') then + -- synchronous clear is asserted + if (sclr = '1') then + dataout_h <= (others => '0'); + dataout_l <= (others => '0'); + oe_rgd <= '0'; + oe_reg_ext <= '0'; + -- else if synchronous set is asserted + elsif (sset = '1') then + dataout_h <= (others => '1'); + dataout_l <= (others => '1'); + oe_rgd <= '1'; + oe_reg_ext <= '1'; + else + if (INVERT_DATAOUT = true) then + dataout_h <= not datain_h; + dataout_l <= not datain_l; + else + dataout_h <= datain_h; + dataout_l <= datain_l; + end if; + oe_rgd <= oe; + end if; + end if; + elsif ((outclock = '0') and outclock'event) then + -- falling edge of outclock + if (outclocken = '1') then + oe_reg_ext <= oe_rgd; + end if; + end if; +end process REGS; + +DATA_OUTPUT: process(outclock_dly, dataout_h, dataout_l, output_enable) +begin + if (output_enable = '1') then + if (outclock_dly = '1') then + dataout <= dataout_h; + else + dataout <= dataout_l; + end if; + else -- output is not enabled + dataout <= (others => 'Z'); + end if; +end process DATA_OUTPUT; + +end behave; +-- END ARCHITECTURE BEHAVE + +-- START ENTITY NAME ----------------------------------------------------------- +-- +-- Entity Name : ALTDDIO_BIDIR +-- +-- Description : Double Data Rate (DDR) bi-directional behavioural model. +-- Transmits and receives data on both edges of the reference +-- clock. +-- +-- Limitations : Not available for MAX device families. +-- +-- Expected results : Data output sampled from padio port on rising edge of +-- inclock signal (dataout_h) and falling edge of inclock +-- signal (dataout_l). Combinatorial output fed by padio +-- directly (combout). +-- +--END ENTITY NAME -------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.altddio_in; +use work.altddio_out; + +-- ENTITY DECLARATION +entity altddio_bidir is +generic( + width : positive; -- required parameter + power_up_high : string := "OFF"; + oe_reg : string := "UNUSED"; + extend_oe_disable : string := "UNUSED"; + implement_input_in_lcell : string := "UNUSED"; + invert_output : string := "OFF"; + intended_device_family : string := "Stratix"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altddio_bidir" +); +port ( + datain_h : in std_logic_vector(width-1 downto 0); --input data to be + --output of padio port + --at the rising edge of + --outclock + datain_l : in std_logic_vector(width-1 downto 0); --input data to be + --output of padio port + --at the falling edge of + --outclock + inclock : in std_logic := '0'; -- input reference clock to sample DDR input. + inclocken : in std_logic := '1'; -- inclock enable + outclock : in std_logic; -- input reference clock to register data output + outclocken : in std_logic := '1'; -- outclock enable + aset : in std_logic := '0'; -- asynchronour set + aclr : in std_logic := '0'; -- asynchronous clear + sset : in std_logic := '0'; -- synchronour set + sclr : in std_logic := '0'; -- synchronous clear + oe : in std_logic := '1'; -- output enable for padio port + + dataout_h : out std_logic_vector(width-1 downto 0);--data sampled from the + --padio port at the + --rising edge of + --inclock + dataout_l : out std_logic_vector(width-1 downto 0);--data sampled from the + --padio port at the + --falling edge of + --inclock + combout : out std_logic_vector(width-1 downto 0);--combinatorial output + --directly fed by padio + + oe_out : out std_logic_vector(width-1 downto 0);--DDR OE output + + dqsundelayedout : out std_logic_vector(width-1 downto 0); -- undelayed DQS + -- signal to the + -- PLD core + + padio : inout std_logic_vector(width-1 downto 0) --bidirectional DDR + --port +); +end altddio_bidir; +-- END ENTITY DECLARATION + +-- BEGINNING ARCHITECTURE STRUCT +architecture struct of altddio_bidir is +-- COMPONENT DECLARATION +component altddio_in +generic ( + width : positive := 1; + intended_device_family : string := "Stratix"; + power_up_high : string := "OFF" +); +port ( + datain : in std_logic_vector(width-1 downto 0); + inclock : in std_logic; + inclocken : in std_logic := '1'; + aset : in std_logic := '0'; + aclr : in std_logic := '0'; + sset : in std_logic := '0'; + sclr : in std_logic := '0'; + dataout_h : out std_logic_vector(width-1 downto 0); + dataout_l : out std_logic_vector(width-1 downto 0) +); +end component; + +component altddio_out +generic ( + width : positive := 1; + power_up_high : string := "OFF"; + intended_device_family : string := "Stratix"; + oe_reg : string := "UNUSED"; + extend_oe_disable : string := "UNUSED"; + invert_output : string := "OFF" +); +port ( + datain_h : in std_logic_vector(width-1 downto 0); + datain_l : in std_logic_vector(width-1 downto 0); + outclock : in std_logic; + outclocken : in std_logic := '1'; + aset : in std_logic := '0'; + aclr : in std_logic := '0'; + sset : in std_logic := '0'; + sclr : in std_logic := '0'; + oe : in std_logic := '1'; + dataout : out std_logic_vector(width-1 downto 0); + oe_out : out std_logic_vector(width-1 downto 0) +); +end component; + +begin + +-- checking for invalid parameters +MSG: process +begin + if (width <= 0) then + ASSERT FALSE + REPORT "The width parameter must be greater than 0" + SEVERITY ERROR; + end if; + wait; +end process MSG; + + + +-- COMPONENT INSTANTIATION +U1: altddio_in +generic map ( + width => width, + intended_device_family => intended_device_family, + power_up_high => power_up_high +) +port map ( + datain => padio, + inclock => inclock, + inclocken => inclocken, + aset => aset, + aclr => aclr, + sset => sset, + sclr => sclr, + dataout_h => dataout_h, + dataout_l => dataout_l +); + +U2: altddio_out +generic map ( + width => width, + power_up_high => power_up_high, + intended_device_family => intended_device_family, + oe_reg => oe_reg, + extend_oe_disable => extend_oe_disable, + invert_output => invert_output +) +port map ( + datain_h => datain_h, + datain_l => datain_l, + outclock => outclock, + outclocken => outclocken, + aset => aset, + aclr => aclr, + sset => sset, + sclr => sclr, + oe => oe, + dataout => padio, + oe_out => oe_out +); + +-- assign padio to feed combout port +combout <= padio; +dqsundelayedout <= padio; +end struct; +-- END ARCHITECTURE STRUCT + + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : stratixii_lvds_rx +-- +-- Description : Stratix II lvds receiver. Support both the dpa and non-dpa +-- mode. +-- +-- Limitation : Only available to Stratix II. +-- +-- Results Expected: Deserialized output data, dpa lock signal and status bit +-- indicating whether maximum bitslip has been reached. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- ENTITY DECLARATION +entity stratixii_lvds_rx is + +-- GENERIC DECLARATION + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + enable_dpa_mode : string := "OFF"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + x_on_bitslip : string := "ON" ); + +-- PORT DECLARATION + port( +--INPUT PORT DECLARATION + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_fastclk : in std_logic; --Required port + rx_enable : in std_logic := '1'; + rx_locked : in std_logic; + rx_dpaclock : in std_logic := '0'; + rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1'); + rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + +-- OUTPUT PORT DECLARATION + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0); + rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0) := (others => '0') ); + +end stratixii_lvds_rx; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of stratixii_lvds_rx is + +-- CONSTANT DECLARATION + constant REGISTER_WIDTH : natural := deserialization_factor * number_of_channels; + constant MUX_WIDTH : natural := 12; + +-- TYPE DECLARATION + type CHANNEL_CNT is array (number_of_channels-1 downto 0) of integer; + type CHANNEL_BOOL is array (number_of_channels-1 downto 0) of boolean; + type DPA_FIFO_RAM is array (number_of_channels -1 downto 0) of std_logic_vector(5 downto 0); + type BITSLIP_REG_CHAIN is array (number_of_channels-1 downto 0) of std_logic_vector(MUX_WIDTH-1 downto 0); + + +-- SIGNAL DECLARATION + + -- constant signals + signal fifo_write_clk : std_logic := '0'; + signal fifo_read_clk : std_logic := '0'; + + signal temp_zero : std_logic := '0'; + + signal enable0_reg : std_logic := '0'; + signal enable_negedge_count : boolean := false; + + signal rx_shift_reg : std_logic_vector(REGISTER_WIDTH-1 downto 0) := (others => '0'); + signal rx_parallel_load_reg : std_logic_vector(REGISTER_WIDTH-1 downto 0) := (others => '0'); + + signal rx_in_reg : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal fifo_out_sync_reg : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal bitslip_mux_out : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal dpa_in : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal retime_data : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal dpll_lock : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal dpll_first_lock : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal rx_channel_data_align_pre : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal write_side_sync_reset : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal read_side_sync_reset : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + + signal ram_array : DPA_FIFO_RAM := (others => (others => '0')); + + signal dpa_fifo_in : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal dpa_fifo_out : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal rx_in_reg_clk : std_logic := '0'; + signal rx_bload : std_logic := '0'; + +begin + +-- SIGNAL ASSIGNMENTS + rx_out <= rx_parallel_load_reg; + dpa_fifo_in <= retime_data; + dpa_fifo_out <= fifo_out_sync_reg; + fifo_write_clk <= rx_fastclk; + fifo_read_clk <= rx_fastclk; + rx_in_reg_clk <= rx_fastclk; + rx_dpa_locked <= dpll_lock; + rx_bload <= enable0_reg; + +-- PROCESS DECLARATION + + -- the deserializer + STRATIXII_DESER : process(rx_fastclk) + begin + if (rx_fastclk'event and (rx_fastclk = '1')) then + if (rx_bload = '1') then + rx_parallel_load_reg <= rx_shift_reg; + end if; + + for i in 0 to number_of_channels -1 loop + for x in deserialization_factor-1 downto 1 loop + rx_shift_reg(x + (i * deserialization_factor)) <= rx_shift_reg(x-1 + (i * deserialization_factor)); + end loop; + rx_shift_reg(i * deserialization_factor) <= bitslip_mux_out(i); + end loop; + + -- Registering load enable signal + enable0_reg <= rx_enable; + end if; + end process STRATIXII_DESER; + + -- input synchronization register + IN_SYNC_REGISTER : process (rx_in_reg_clk) + begin + if (rx_in_reg_clk = '1' and rx_in_reg_clk'event) then + rx_in_reg <= rx_in; + end if; + end process IN_SYNC_REGISTER; + + -- STRATIXII bitslip logic + STRATIXII_BITSLIP : process (rx_fastclk, rx_cda_reset) + variable start_corrupt_bits : CHANNEL_BOOL := (others => false); + variable num_corrupt_bits : CHANNEL_CNT := (others => 0); + variable bitslip_count : CHANNEL_CNT := (others => 0); + variable shift_reg_chain : BITSLIP_REG_CHAIN := (others => (others => '0')); + begin + for i in 0 to number_of_channels-1 loop + if (rx_cda_reset(i) = '1') then + bitslip_count(i) := 0; + rx_cda_max(i) <= '0'; + end if; + if (rx_fastclk'event and (rx_fastclk = '1')) then + if ((((rx_channel_data_align(i) = '1') and + (rx_channel_data_align_pre(i) = '0')) or + ((start_corrupt_bits(i) = true) and + (num_corrupt_bits(i) < 4) and + (rx_channel_data_align(i) = '1'))) and + (x_on_bitslip = "ON")) then + bitslip_mux_out(i) <= 'X'; + else + bitslip_mux_out(i) <= shift_reg_chain(i)(bitslip_count(i)); + end if; + + for j in data_align_rollover -1 downto 0 loop + shift_reg_chain(i)(j + 1) := shift_reg_chain(i)(j); + end loop; + + if ((enable_dpa_mode = "ON") and (rx_dpll_enable(i) = '1')) then + shift_reg_chain(i)(0) := dpa_fifo_out(i); + else + shift_reg_chain(i)(0) := rx_in_reg(i); + end if; + + if ((rx_channel_data_align(i) = '1') and + (rx_channel_data_align_pre(i) = '0'))then + bitslip_count(i) := (bitslip_count(i) + 1) rem (data_align_rollover + 1); + if (bitslip_count(i) = data_align_rollover) then + rx_cda_max(i) <= '1'; + else + rx_cda_max(i) <= '0'; + end if; + + start_corrupt_bits(i) := true; + num_corrupt_bits(i) := 1; + elsif ((rx_channel_data_align(i) = '0') and + (rx_channel_data_align_pre(i) = '1'))then + start_corrupt_bits(i) := false; + num_corrupt_bits(i) := 0; + end if; + + if (start_corrupt_bits(i) = true) then + if (num_corrupt_bits(i) = 3) then + start_corrupt_bits(i) := false; + else + num_corrupt_bits(i) := num_corrupt_bits(i) + 1; + end if; + end if; + rx_channel_data_align_pre(i) <= rx_channel_data_align(i); + + end if; + end loop; + end process STRATIXII_BITSLIP; + + -- STRATIXII Phase Compensation FIFO + STRATIXII_DPA_FIFO : process (fifo_write_clk, fifo_read_clk, rx_reset) + variable wrPtr : CHANNEL_CNT := (others => 0); + variable rdPtr : CHANNEL_CNT := (others => 3); + variable fifo_in_sync_reg : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + + begin + for i in 0 to number_of_channels-1 loop + if (rx_reset(i) = '1') then + wrPtr(i) := 0; + rdPtr(i) := 3; + ram_array(i) <= (others => '0'); + fifo_in_sync_reg(i) := '0'; + fifo_out_sync_reg(i) <= '0'; + write_side_sync_reset(i) <= '1'; + read_side_sync_reset(i) <= '1'; + end if; + end loop; + + if (fifo_write_clk'event and (fifo_write_clk = '1')) then + for i in 0 to number_of_channels-1 loop + if ((rx_reset(i) = '1') or (rx_fifo_reset(i) = '1') or + ((reset_fifo_at_first_lock = "ON") and (dpll_first_lock(i) = '0'))) then + wrPtr(i) := 0; + ram_array(i) <= (others => '0'); + fifo_in_sync_reg(i) := '0'; + write_side_sync_reset(i) <= '1'; + else + write_side_sync_reset(i) <= '0'; + if (write_side_sync_reset(i) = '0') then + ram_array(i)(wrPtr(i)) <= fifo_in_sync_reg(i); + fifo_in_sync_reg(i) := dpa_fifo_in(i); + wrPtr(i) := (wrPtr(i) + 1) rem 6; + end if; + end if; + end loop; + end if; + + if (fifo_read_clk'event and (fifo_read_clk = '1')) then + for i in 0 to number_of_channels-1 loop + if ((rx_reset(i) = '1') or (rx_fifo_reset(i) = '1') or + ((reset_fifo_at_first_lock = "ON") and (dpll_first_lock(i) = '0'))) then + rdPtr(i) := 3; + ram_array(i) <= (others =>'0'); + fifo_out_sync_reg(i) <= '0'; + read_side_sync_reset(i) <= '1'; + else + read_side_sync_reset(i) <= '0'; + if (read_side_sync_reset(i) = '0') then + fifo_out_sync_reg(i) <= ram_array(i)(rdPtr(i)); + rdPtr(i) := (rdPtr(i) + 1) rem 6; + end if; + end if; + end loop; + end if; + end process STRATIXII_DPA_FIFO; + + -- STRATIXII DPA Block + STRATIXII_DPA_BLOCK : process (rx_fastclk, rx_reset) + variable dpll_clk_count : CHANNEL_CNT := (others => 0); + variable init : boolean := true; + begin + if (init = true) then + if (enable_dpa_mode = "ON") then + ASSERT false + REPORT "DPA Phase tracking is not modeled, and once locked, DPA will continue to lock until the next reset is asserted. Please refer to the device handbook for further details." + SEVERITY warning; + end if; + init := false; + end if; + + for i in 0 to number_of_channels-1 loop + if (rx_reset(i) = '1') then + dpll_clk_count(i) := 0; + dpll_lock(i) <= '0'; + end if; + + if (rx_fastclk'event and (rx_fastclk = '1')) then + dpa_in(i) <= rx_in(i); + retime_data(i) <= dpa_in(i); + + if (rx_reset(i) /= '1') then + dpll_clk_count(i) := dpll_clk_count(i) + 1; + + if (dpll_clk_count(i) > 2) then + dpll_lock(i) <= '1'; + dpll_first_lock(i) <= '1'; + end if; + end if; + end if; + end loop; + end process STRATIXII_DPA_BLOCK; + +end behavior; + +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : flexible_lvds_rx +-- +-- Description : flexible lvds receiver +-- +-- Limitation : Only available to Cyclone and Cyclone II families. +-- +-- Results Expected: Deserialized output data. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- ENTITY DECLARATION +entity flexible_lvds_rx is + +-- GENERIC DECLARATION + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; + use_extra_ddio_register : boolean := true; + use_extra_pll_clk : boolean := false; + buffer_implementation : string := "RAM"; + registered_data_align_input : string := "OFF"; + use_external_pll : string := "OFF"; + registered_output : string := "OFF"; + add_latency : boolean := true + ); + +-- PORT DECLARATION + port( +--INPUT PORT DECLARATION + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_fastclk : in std_logic; --Required port + rx_slowclk : in std_logic; --Required port + rx_syncclk : in std_logic; --Required port + pll_areset : in std_logic; --Required port + rx_data_reset : in std_logic; + rx_data_align : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_locked : in std_logic; + +-- OUTPUT PORT DECLARATION + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0)); + +end flexible_lvds_rx; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of flexible_lvds_rx is + +-- FUNCTION DECLARATION + function get_latency ( constant i_deserialization_factor : in natural) return natural is + begin + if ((deserialization_factor rem 2) = 1) then + return (deserialization_factor / 2) + 1; + else + return (deserialization_factor / 2); + end if; + end get_latency; + + function get_num_of_sync_stages ( constant i_latency : in natural) return natural is + variable num_of_sync_stages : natural := 0; + begin + + if ((deserialization_factor = 4) and (add_latency = true)) then + num_of_sync_stages := 1; + else + if (add_latency = false) then + num_of_sync_stages := i_latency-2; + else + num_of_sync_stages := i_latency-3; + end if; + end if; + + if (((deserialization_factor rem 2) = 1) and (not (((buffer_implementation = "RAM") or (buffer_implementation = "LES"))))) then + num_of_sync_stages := num_of_sync_stages + deserialization_factor/2; + end if; + + return num_of_sync_stages; + + end get_num_of_sync_stages; + +-- CONSTANT DECLARATION + constant REGISTER_WIDTH : natural := deserialization_factor * number_of_channels; + constant LATENCY : natural := get_latency(deserialization_factor); + constant NUM_OF_SYNC_STAGES : natural := get_num_of_sync_stages(LATENCY); + +-- TYPE DECLARATION + type CHANNEL_CNT is array (number_of_channels-1 downto 0) of integer; + type DFFPIPE is array (NUM_OF_SYNC_STAGES downto 0) of std_logic_vector(number_of_channels -1 downto 0); + + +-- SIGNAL DECLARATION + + -- constant signals + signal rx_shift_reg : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_shift_reg1 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_shift_reg2 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg1 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg2 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg1_buf1 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg1_buf1_pipe : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg2_buf1 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg1_buf2 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg1_buf2_pipe : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_sync_reg2_buf2 : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_out_odd : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_out_odd_mode : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_out_reg : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal rx_out_int : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal h_int_reg : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal l_int_reg : std_logic_vector (REGISTER_WIDTH -1 downto 0):= (others => '0'); + signal ddio_h_reg : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal ddio_l_reg : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal datain_h_reg : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal datain_l_reg : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal datain_l_latch : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal select_bit : std_logic := '0'; + signal sync_clock : std_logic := '0'; + signal rx_data_align_reg : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal rx_data_align_int : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal rx_data_align_clk : std_logic := '0'; + signal int_bitslip_reg : std_logic_vector (number_of_channels -1 downto 0):= (others => '0'); + signal bitslip_count : CHANNEL_CNT := (others => 0); + signal rx_reg_clk : std_logic := '0'; + +begin + +-- SIGNAL ASSIGNMENTS + rx_out_int <= rx_shift_reg when ((deserialization_factor rem 2) = 0) + else rx_out_odd when (buffer_implementation /= "MUX") + else rx_sync_reg1_buf1 when (select_bit = '1') + else rx_sync_reg2_buf1; + + rx_out <= rx_out_reg when ((registered_output = "ON") and (use_external_pll = "OFF")) + else rx_out_int; + + rx_reg_clk <= rx_slowclk when (registered_output = "ON") + else '0'; + + rx_data_align_clk <= rx_slowclk when ((deserialization_factor rem 2) = 0) + else sync_clock when (use_extra_pll_clk = false) + else rx_syncclk; + + rx_data_align_int <= rx_data_align_reg when (registered_data_align_input = "ON") and (use_external_pll = "OFF") + else rx_data_align; + + +-- PROCESS DECLARATION + + -- This always block implements the altddio_in that takes in the input serial + -- data of each channel and deserialized it into two parallel data stream + -- (ddio_h_reg and ddio_l_reg). Each parallel data stream will be registered + -- before send to shift registers. + DDIO_IN : process(rx_fastclk, pll_areset, rx_data_reset) + variable datain_h_reg_int : DFFPIPE := (others => (others => '0')); + variable datain_l_reg_int : DFFPIPE := (others => (others => '0')); + variable pipe_ptr : natural := 0; + begin + if (pll_areset = '1' or rx_data_reset = '1') then + ddio_h_reg <= (others => '0'); + datain_h_reg <= (others => '0'); + ddio_l_reg <= (others => '0'); + datain_l_reg <= (others => '0'); + datain_l_latch <= (others => '0'); + datain_h_reg_int := (others => (others => '0')); + datain_l_reg_int := (others => (others => '0')); + elsif ((rx_fastclk = '1') and rx_fastclk'event) then + if (NUM_OF_SYNC_STAGES > 0) then + + datain_h_reg <= datain_h_reg_int(pipe_ptr); + datain_l_reg <= datain_l_reg_int(pipe_ptr); + + if (use_extra_ddio_register = true) then + ddio_h_reg <= rx_in; + datain_h_reg_int(pipe_ptr) := ddio_h_reg; + else + datain_h_reg_int(pipe_ptr) := rx_in; + end if; + + datain_l_reg_int(pipe_ptr) := datain_l_latch; + + if (NUM_OF_SYNC_STAGES > 1) then + pipe_ptr := (pipe_ptr + 1) rem NUM_OF_SYNC_STAGES; + end if; + + else + if (use_extra_ddio_register = true) then + ddio_h_reg <= rx_in; + datain_h_reg <= ddio_h_reg; + else + datain_h_reg <= rx_in; + end if; + datain_l_reg <= datain_l_latch; + end if; + elsif (rx_fastclk'event and (rx_fastclk = '0')) then + if (use_extra_ddio_register = true) then + ddio_l_reg <= rx_in; + datain_l_latch <= ddio_l_reg; + else + datain_l_latch <= rx_in; + end if; + end if; + end process DDIO_IN; + + -- bitslip counter + BITSLIP_CNT : process(rx_fastclk, rx_cda_reset) + begin + for i in 0 to number_of_channels-1 loop + if (rx_cda_reset(i) = '1') then + bitslip_count(i) <= 0; + elsif ((rx_fastclk = '1') and rx_fastclk'event) then + if (((not int_bitslip_reg(i)) and rx_data_align_int(i)) = '1') then + bitslip_count(i) <= (bitslip_count(i) + 1) rem deserialization_factor; + end if; + end if; + end loop; + end process BITSLIP_CNT; + + DATA_ALIGN_REG : process(rx_data_align_clk) + begin + if ((rx_data_align_clk = '1') and rx_data_align_clk'event) then + rx_data_align_reg <= rx_data_align; + end if; + end process DATA_ALIGN_REG; + + BITSLIP_REG : process(rx_fastclk) + begin + if ((rx_fastclk = '1') and rx_fastclk'event) then + int_bitslip_reg <= rx_data_align_int; + end if; + end process BITSLIP_REG; + + -- Loading input data to shift register + SHIFTREG : process(rx_fastclk, pll_areset, rx_data_reset) + begin + if (pll_areset = '1' or rx_data_reset = '1') then + rx_shift_reg <= (others => '0'); + rx_shift_reg1 <= (others => '0'); + rx_shift_reg2 <= (others => '0'); + h_int_reg <= (others => '0'); + l_int_reg <= (others => '0'); + elsif ((rx_fastclk = '1') and rx_fastclk'event) then + -- Implementation for even deserialization factor. + if ((deserialization_factor rem 2) = 0) then + for i in 0 to number_of_channels-1 loop + for x in (deserialization_factor-1) downto 2 loop + rx_shift_reg(x + (i * deserialization_factor)) <= + rx_shift_reg(x-2 + (i * deserialization_factor)); + end loop; + + for x in (deserialization_factor-1) downto 1 loop + h_int_reg(x + (i * deserialization_factor)) <= + h_int_reg(x-1 + (i * deserialization_factor)); + + l_int_reg(x + (i * deserialization_factor)) <= + l_int_reg(x-1 + (i * deserialization_factor)); + end loop; + h_int_reg(i * deserialization_factor) <= datain_h_reg(i); + l_int_reg(i * deserialization_factor) <= datain_l_reg(i); + + if (bitslip_count(i) = 0) then + rx_shift_reg(i * deserialization_factor) <= datain_h_reg(i); + rx_shift_reg((i * deserialization_factor)+1) <= datain_l_reg(i); + elsif (bitslip_count(i) = 1) then + rx_shift_reg(i * deserialization_factor) <= datain_l_reg(i); + rx_shift_reg((i * deserialization_factor)+1) <= h_int_reg(i * deserialization_factor); + else + if (bitslip_count(i) rem 2 = 1) then + rx_shift_reg(i * deserialization_factor) <= l_int_reg((bitslip_count(i)/2) -1 + (i * deserialization_factor)); + rx_shift_reg((i * deserialization_factor)+1) <= h_int_reg((bitslip_count(i)/2) + (i * deserialization_factor)); + else + rx_shift_reg(i * deserialization_factor) <= h_int_reg((bitslip_count(i)/2) -1 + (i * deserialization_factor)); + rx_shift_reg((i * deserialization_factor)+1) <= l_int_reg((bitslip_count(i)/2) -1 + (i * deserialization_factor)); + end if; + end if; + end loop; + else -- Implementation for odd deserialization factor. + for i in 0 to number_of_channels-1 loop + for x in (deserialization_factor-1) downto 2 loop + rx_shift_reg1(x + (i * deserialization_factor)) <= + rx_shift_reg1(x-2 + (i * deserialization_factor)); + + rx_shift_reg2(x + (i * deserialization_factor)) <= + rx_shift_reg2(x-2 + (i * deserialization_factor)); + end loop; + for x in (deserialization_factor-1) downto 1 loop + h_int_reg(x + (i * deserialization_factor)) <= + h_int_reg(x-1 + (i * deserialization_factor)); + + l_int_reg(x + (i * deserialization_factor)) <= + l_int_reg(x-1 + (i * deserialization_factor)); + end loop; + h_int_reg(i * deserialization_factor) <= datain_h_reg(i); + l_int_reg(i * deserialization_factor) <= datain_l_reg(i); + + if (bitslip_count(i) = 0) then + rx_shift_reg1(i * deserialization_factor) <= datain_h_reg(i); + rx_shift_reg1((i * deserialization_factor)+1) <= datain_l_reg(i); + elsif (bitslip_count(i) = 1) then + rx_shift_reg1(i * deserialization_factor) <= datain_l_reg(i); + rx_shift_reg1((i * deserialization_factor)+1) <= h_int_reg(i*deserialization_factor); + elsif (bitslip_count(i) rem 2 = 0) then + rx_shift_reg1(i * deserialization_factor) <= h_int_reg(bitslip_count(i)/2 -1 + (i * deserialization_factor)); + rx_shift_reg1((i * deserialization_factor)+1) <= l_int_reg(bitslip_count(i)/2 -1 + (i * deserialization_factor)); + else + rx_shift_reg1(i * deserialization_factor) <= l_int_reg(bitslip_count(i)/2 -1 + (i * deserialization_factor)); + rx_shift_reg1((i * deserialization_factor)+1) <= h_int_reg(bitslip_count(i)/2 + (i * deserialization_factor)); + end if; + + rx_shift_reg2(i * deserialization_factor) <= rx_shift_reg1(((i+1)* deserialization_factor)-2); + rx_shift_reg2((i * deserialization_factor)+1) <= rx_shift_reg1(((i+1)* deserialization_factor)-1); + end loop; + end if; + end if; + end process SHIFTREG; + + -- Loading input data to shift register + BIT_SELECT : process(rx_slowclk, pll_areset, rx_data_reset) + begin + if (pll_areset = '1' or rx_data_reset = '1') then + rx_sync_reg1 <= (others => '0'); + rx_sync_reg2 <= (others => '0'); + rx_sync_reg1_buf2_pipe <= (others => '0'); + rx_out_odd <= (others => '0'); + rx_out_odd_mode <= (others => '0'); + elsif ((rx_slowclk = '1') and rx_slowclk'event) then + rx_sync_reg1 <= rx_shift_reg1; + rx_sync_reg2 <= rx_shift_reg2; + rx_sync_reg1_buf2_pipe <= rx_sync_reg1_buf2; + + if(use_extra_pll_clk = false) then + if (select_bit = '1') then + rx_out_odd_mode <= rx_sync_reg1_buf1_pipe; + else + rx_out_odd_mode <= rx_sync_reg2_buf1; + end if; + else + if (select_bit = '1') then + rx_out_odd_mode <= rx_sync_reg1_buf2_pipe; + else + rx_out_odd_mode <= rx_sync_reg2_buf2; + end if; + end if; + + rx_out_odd <= rx_out_odd_mode; + end if; + end process BIT_SELECT; + + process(rx_slowclk) + begin + if ((rx_slowclk = '1') and rx_slowclk'event) then + sync_clock <= not sync_clock; + select_bit <= not select_bit; + end if; + end process; + + SYNC_REG : process(sync_clock, pll_areset, rx_data_reset) + begin + if (pll_areset = '1' or rx_data_reset = '1') then + rx_sync_reg1_buf1 <= (others => '0'); + rx_sync_reg2_buf1 <= (others => '0'); + rx_sync_reg1_buf1_pipe <= (others => '0'); + elsif ((sync_clock = '1') and sync_clock'event) then + rx_sync_reg1_buf1 <= rx_sync_reg1; + rx_sync_reg2_buf1 <= rx_sync_reg2; + rx_sync_reg1_buf1_pipe <= rx_sync_reg1_buf1; + end if; + end process SYNC_REG; + + SYNC_REG2 : process(rx_syncclk, pll_areset, rx_data_reset) + begin + if (pll_areset = '1' or rx_data_reset = '1') then + rx_sync_reg1_buf2 <= (others => '0'); + rx_sync_reg2_buf2 <= (others => '0'); + elsif ((rx_syncclk = '1') and rx_syncclk'event) then + rx_sync_reg1_buf2 <= rx_sync_reg1; + rx_sync_reg2_buf2 <= rx_sync_reg2; + end if; + end process SYNC_REG2; + + OUTPUT_REG : process(rx_reg_clk, pll_areset, rx_data_reset) + begin + if (pll_areset = '1' or rx_data_reset = '1') then + rx_out_reg <= (others => '0'); + elsif ((rx_reg_clk = '1') and rx_reg_clk'event) then + rx_out_reg <= rx_out_int; + end if; + end process; + +end behavior; -- flexible_lvds_rx + +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : stratixiii_lvds_rx_dpa +-- +-- Description : Simulation model for Stratix III DPA block. +-- +-- Limitation : Only available to Stratix III. +-- +-- Results expected: Retimed data, dpa clock, enable and lock signal with the selected phase. +-- +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- ENTITY DECLARATION +entity stratixiii_lvds_rx_dpa is + +-- GENERIC DECLARATION + generic ( + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value : natural := 0 ); + +-- PORT DECLARATION + port ( +--INPUT PORT DECLARATION + rx_in : in std_logic; + rx_fastclk : in std_logic; + rx_enable : in std_logic; + rx_dpa_reset : in std_logic; + rx_dpa_hold : in std_logic; + +-- OUTPUT PORT DECLARATION + rx_out : out std_logic := '0'; + rx_dpa_clk : out std_logic := '0'; + rx_dpa_loaden : out std_logic := '0'; + rx_dpa_locked : out std_logic := '0' ); + +end stratixiii_lvds_rx_dpa; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of stratixiii_lvds_rx_dpa is + +-- FUNCTION DECLARATION + -- get phase_shift value for the clock that acts as enable signal (for StratixIII lvds) + function get_initial_phase_select ( constant i_initial_phase_select : in natural) return natural is + begin + + if ((enable_dpa_initial_phase_selection = "ON") and + (i_initial_phase_select > 0) and + (i_initial_phase_select <= 7)) then + return i_initial_phase_select; + else + return 0; + end if; + end get_initial_phase_select; + + +-- CONSTANT DECLARATION + constant INITIAL_PHASE_SELECT : natural := get_initial_phase_select(dpa_initial_phase_value); + constant PHASE_NUM : natural := 8; + +-- TYPE DECLARATION + type PHASE_TAP is array (PHASE_NUM -1 downto 0) of natural; + +-- SIGNAL DECLARATION + signal dpa_clk_tmp : std_logic_vector (PHASE_NUM -1 downto 0); + signal dpa_loaden : std_logic_vector (PHASE_NUM -1 downto 0) := (others => '0'); + signal dpa_dataout_tmp : std_logic_vector (PHASE_NUM -1 downto 0) := (others => '0'); + signal ppm_offset : integer := 0; + signal count : integer := 0; + signal rx_in_reg0 : std_logic := '0'; + signal rx_in_reg1 : std_logic := '0'; + signal dpa_locked_tmp : std_logic := '0'; + signal first_clkin_edge_detect : std_logic := '0'; + signal reg_clk : std_logic; + signal counter_reset_value : integer ; + signal count_value : integer ; + signal clk_period : time := 0 ps; + signal last_clk_period : time := 0 ps; + signal last_clkin_edge : time := 0 ps; + signal j : integer ; + +begin + + + -- SIGNAL ASSIGNMENTS + rx_dpa_loaden <= '0' when (enable_soft_cdr_mode = "ON") + else dpa_loaden(INITIAL_PHASE_SELECT); + + reg_clk <= dpa_clk_tmp(INITIAL_PHASE_SELECT); + +-- PROCESS DECLARATION + + -- Calculate the clock period + process (rx_fastclk) + variable clk_period_tmp : time := 0 ps; + begin + if (rx_fastclk'event and rx_fastclk = '1') then + if (first_clkin_edge_detect = '0') then + first_clkin_edge_detect <= '1'; + else + clk_period_tmp := now - last_clkin_edge; + end if; + + if (((clk_period_tmp = last_clk_period) or (clk_period_tmp = last_clk_period + 1 ps) or + (clk_period_tmp = last_clk_period - 1 ps)) and (clk_period_tmp /= 0 ps ) and (last_clk_period /= 0 ps)) then + dpa_locked_tmp <= '1'; + else + dpa_locked_tmp <= '0'; + end if; + + last_clkin_edge <= now; + last_clk_period <= clk_period_tmp; + end if; + end process; + + -- Generate the phase shifted dpa clock signals + process (rx_fastclk) + begin + dpa_clk_tmp(0) <= rx_fastclk; + dpa_clk_tmp(1) <= transport rx_fastclk after (clk_period * 0.125); + dpa_clk_tmp(2) <= transport rx_fastclk after (clk_period * 0.25); + dpa_clk_tmp(3) <= transport rx_fastclk after (clk_period * 0.375); + dpa_clk_tmp(4) <= transport rx_fastclk after (clk_period * 0.5); + dpa_clk_tmp(5) <= transport rx_fastclk after (clk_period * 0.625); + dpa_clk_tmp(6) <= transport rx_fastclk after (clk_period * 0.75); + dpa_clk_tmp(7) <= transport rx_fastclk after (clk_period * 0.875); + end process; + + -- Generate the phase shifted dpa enable signals + process (rx_enable) + begin + dpa_loaden(0) <= rx_enable; + dpa_loaden(1) <= transport rx_enable after (clk_period * 0.125); + dpa_loaden(2) <= transport rx_enable after (clk_period * 0.25); + dpa_loaden(3) <= transport rx_enable after (clk_period * 0.375); + dpa_loaden(4) <= transport rx_enable after (clk_period * 0.5); + dpa_loaden(5) <= transport rx_enable after (clk_period * 0.625); + dpa_loaden(6) <= transport rx_enable after (clk_period * 0.75); + dpa_loaden(7) <= transport rx_enable after (clk_period * 0.875); + end process; + + + -- Generate the phase shifted data signals + process (rx_in_reg1) + begin + dpa_dataout_tmp(0) <= rx_in_reg1; + dpa_dataout_tmp(1) <= transport rx_in_reg1 after (clk_period * 0.125) ; + dpa_dataout_tmp(2) <= transport rx_in_reg1 after (clk_period * 0.25) ; + dpa_dataout_tmp(3) <= transport rx_in_reg1 after (clk_period * 0.375) ; + dpa_dataout_tmp(4) <= transport rx_in_reg1 after (clk_period * 0.5) ; + dpa_dataout_tmp(5) <= transport rx_in_reg1 after (clk_period * 0.625) ; + dpa_dataout_tmp(6) <= transport rx_in_reg1 after (clk_period * 0.75) ; + dpa_dataout_tmp(7) <= transport rx_in_reg1 after (clk_period * 0.875) ; + end process; + + process (reg_clk) + begin + if (reg_clk'event and reg_clk = '1') then + rx_in_reg0 <= rx_in; + rx_in_reg1 <= rx_in_reg0; + end if; + end process; + + process (dpa_dataout_tmp, ppm_offset, rx_dpa_reset) + begin + if (enable_soft_cdr_mode = "OFF") then + rx_out <= dpa_dataout_tmp(0); + else + if (rx_dpa_reset = '1') then + rx_out <= '0'; + else + if (sim_dpa_is_negative_ppm_drift = "ON") then + rx_out <= dpa_dataout_tmp(ppm_offset rem PHASE_NUM); + elsif (ppm_offset = 0) then + rx_out <= dpa_dataout_tmp(0); + else + rx_out <= transport dpa_dataout_tmp(0) after (clk_period * 0.125 * ppm_offset); + end if; + end if; + end if; + end process; + + process (dpa_clk_tmp, ppm_offset, rx_dpa_reset) + begin + if (enable_soft_cdr_mode = "OFF") then + rx_dpa_clk <= dpa_clk_tmp(INITIAL_PHASE_SELECT); + else + if (rx_dpa_reset = '1') then + rx_dpa_clk <= '0'; + else + if (sim_dpa_is_negative_ppm_drift = "ON") then + rx_dpa_clk <= dpa_clk_tmp((INITIAL_PHASE_SELECT + ppm_offset) rem PHASE_NUM); + elsif ((INITIAL_PHASE_SELECT + ppm_offset) = 0) then + rx_dpa_clk <= dpa_clk_tmp(0); + else + rx_dpa_clk <= transport dpa_clk_tmp(0) after (clk_period * 0.125 * (INITIAL_PHASE_SELECT + ppm_offset)); + end if; + end if; + end if; + end process; + + process (dpa_locked_tmp, rx_dpa_reset) + begin + if (rx_dpa_reset = '1') then + rx_dpa_locked <= '0'; + else + rx_dpa_locked <= dpa_locked_tmp; + end if; + end process; + + + STRATIXIII_PPM_OFFSET : + + if (enable_soft_cdr_mode = "ON") generate + + process (rx_fastclk, rx_dpa_reset, rx_dpa_hold) + variable initial : boolean := true; + begin + if(initial) then + if(sim_dpa_net_ppm_variation = 0) then + counter_reset_value <= 1; + count_value <= 1; + else + counter_reset_value <= 1000000 / (sim_dpa_net_ppm_variation * 8); + count_value <= 1000000 / (sim_dpa_net_ppm_variation * 8); + end if; + initial := false; + end if; + + if (sim_dpa_net_ppm_variation = 0) then + ppm_offset <= 0; + else + if (rx_dpa_reset = '1') then + count <= 0; + ppm_offset <= 0; + else + if(rx_dpa_hold = '0') then + if (rx_fastclk'event and rx_fastclk = '1') then + if (count < count_value) then + count <= count + 1; + else + if (sim_dpa_is_negative_ppm_drift = "ON") then + ppm_offset <= (ppm_offset - 1 + PHASE_NUM) rem PHASE_NUM; + else + ppm_offset <= ppm_offset + 1; + end if; + count <= 0; + end if; + end if; + end if; + end if; + end if; + end process; + end generate STRATIXIII_PPM_OFFSET; + +end behavior; + +-- END OF ARCHITECTURE + + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : stratixv_local_clk_divider +-- +-- Description : Simulation model for Stratix V local clock divider. +-- +-- Limitation : Only available to Stratix V. +-- +-- Results expected: This module is used to generate the local loaden signal from fast clock for StratixV +-- family. To mimic local clock divider block. +-- +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- ENTITY DECLARATION +entity stratixv_local_clk_divider is + +-- GENERIC DECLARATION + generic ( + clk_divide_by : natural := 4 ); + +-- PORT DECLARATION + port ( +--INPUT PORT DECLARATION + clkin : in std_logic; +-- OUTPUT PORT DECLARATION + lloaden : out std_logic := '0' ); + +end stratixv_local_clk_divider; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of stratixv_local_clk_divider is + +-- FUNCTION DECLARATION + +-- CONSTANT DECLARATION + +-- TYPE DECLARATION + +-- SIGNAL DECLARATION + signal lloaden_tmp : std_logic := '0'; + signal cnt : integer := 0; + signal count : integer := 0; + +begin + + + -- SIGNAL ASSIGNMENTS + lloaden <= lloaden_tmp; + + -- PROCESS DECLARATION + + process (clkin) + begin + if (clkin'event and clkin = '1') then + count <= 1; + end if; + end process; + + + process (clkin) + begin + if (clkin'event and clkin = '0') then --falling edge on fastclock + if (count = 1) then + if (cnt < (clk_divide_by-1)) then + cnt <= cnt + 1; + else + cnt <= 0; + end if; + end if; + end if; + end process; + + + process (cnt) + begin + if (cnt = (clk_divide_by-1)) then + lloaden_tmp <= '1'; + else + lloaden_tmp <= '0'; + end if; + end process; + +end behavior; + +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : stratixiii_lvds_rx_channel +-- +-- Description : Simulation model for each channel of Stratix III lvds receiver. +-- Support both the dpa and non-dpa mode. +-- +-- Limitation : Only available to Stratix III. +-- +-- Results Expected: Deserialized output data, dpa lock signal, forwarded clock +-- and status bit indicating whether maximum bitslip has been +-- reached. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use work.stratixiii_lvds_rx_dpa; +use work.stratixv_local_clk_divider; + +-- ENTITY DECLARATION +entity stratixiii_lvds_rx_channel is + +-- GENERIC DECLARATION + generic ( + deserialization_factor : natural; -- Required parameter + enable_dpa_mode : string := "OFF"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + x_on_bitslip : string := "ON"; + rx_align_data_reg : string := "RISING_EDGE"; + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_output_clock_phase_shift : integer := 0; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value : natural := 0; + registered_output : string := "ON"; + use_external_pll : string := "OFF"; + use_dpa_calibration : boolean := false; + enable_clock_pin_mode : string := "UNUSED"; + ARRIAII_RX_STYLE : boolean := false; + STRATIXV_RX_STYLE : boolean := false ); + +-- PORT DECLARATION + port( +--INPUT PORT DECLARATION + rx_in : in std_logic; + rx_fastclk : in std_logic; + rx_slowclk : in std_logic; + rx_dpaclock : in std_logic := '0'; + rx_enable : in std_logic; + rx_reset : in std_logic; + rx_dpll_reset : in std_logic; + rx_dpll_hold : in std_logic; + rx_dpll_enable : in std_logic; + rx_fifo_reset : in std_logic; + rx_channel_data_align : in std_logic; + rx_cda_reset : in std_logic; + rx_dpa_lock_reset : in std_logic; + rx_locked : in std_logic; +-- OUTPUT PORT DECLARATION + rx_out : out std_logic_vector(deserialization_factor-1 downto 0); + rx_dpa_locked : out std_logic := '0'; + rx_cda_max : out std_logic := '0'; + rx_divfwdclk : out std_logic := '0' ); + +end stratixiii_lvds_rx_channel; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of stratixiii_lvds_rx_channel is + +-- CONSTANT DECLARATION + constant RAM_WIDTH : natural := 6; + constant MUX_WIDTH : natural := 12; + +-- TYPE DECLARATION + + +-- SIGNAL DECLARATION + + -- constant signals + signal fifo_write_clk : std_logic := '0'; + signal fifo_read_clk : std_logic := '0'; + + signal temp_zero : std_logic := '0'; + + signal enable0_reg : std_logic := '0'; + signal enable_negedge_count : boolean := false; + + signal rx_shift_reg : std_logic_vector(deserialization_factor-1 downto 0) := (others => '0'); + signal rx_parallel_load_reg : std_logic_vector(deserialization_factor-1 downto 0) := (others => '0'); + signal rx_out_reg : std_logic_vector(deserialization_factor-1 downto 0) := (others => '0'); + signal rx_dpa_sync_reg : std_logic_vector(deserialization_factor-1 downto 0) := (others => '0'); + + signal rx_in_reg_pos : std_logic := '0'; + signal rx_in_reg_neg : std_logic := '0'; + signal fifo_out_sync_reg : std_logic := '0'; + signal bitslip_mux_out : std_logic := '0'; + signal dpa_in : std_logic := '0'; + signal retime_data : std_logic := '0'; + signal dpll_lock : std_logic := '0'; + signal dpll_first_lock : std_logic := '0'; + signal rx_channel_data_align_pre : std_logic := '0'; + signal write_side_sync_reset : std_logic := '0'; + signal read_side_sync_reset : std_logic := '0'; + + signal ram_array : std_logic_vector(RAM_WIDTH-1 downto 0) := (others => '0'); + + signal dpa_fifo_in : std_logic := '0'; + signal dpa_fifo_out : std_logic := '0'; + signal rx_in_reg_clk : std_logic := '0'; + signal rx_bload : std_logic := '0'; + signal rx_enable_dly : std_logic := '0'; + signal load_enable_cdr : std_logic := '0'; + signal dpa_clock : std_logic := '0'; + signal dpa_locked : std_logic := '0'; + signal dpa_loaden : std_logic := '0'; + signal fast_clock : std_logic := '0'; + signal start_counter : std_logic := '0'; + signal rx_reg_clk : std_logic := '0'; + signal rx_dpa_sync_reg_clk : std_logic := '0'; + signal rx_divfwdclk_int : std_logic := '0'; + signal j : integer ; + signal lock_out_regr : std_logic := '0'; + signal pad_regr : std_logic_vector(deserialization_factor-1 downto 0) := (others => '0'); + signal extra_regr : std_logic := '0'; + signal in_bus_add : std_logic_vector(deserialization_factor-1 downto 0) := (others => '0'); + signal lock_out_reg_dly : std_logic := '0'; + signal fifo_reset_regr : std_logic := '0'; + signal int_pll_kick_reset : std_logic := '0'; + signal dpa_lock_fifo_reset : std_logic := '0'; + signal pll_locked : std_logic := '0'; + signal wire_lock_state_mc_d : std_logic_vector(1 DOWNTO 0); + signal lock_state_mc : std_logic_vector(1 DOWNTO 0) := (others => '0'); + signal wire_lock_state_mc_ena : std_logic_vector(1 DOWNTO 0); + signal dpaswitch : std_logic := '0'; + signal rx_in_wire : std_logic := '0'; + signal rx_dpaclock_wire : std_logic := '0'; + signal local_clk_div_lloaden : std_logic := '0'; + +-- COMPONENT DECLARATION + + -- stratixiii dpa block + component stratixiii_lvds_rx_dpa + generic ( + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value : natural := 0 ); + + port( + rx_in : in std_logic; + rx_fastclk : in std_logic; + rx_enable : in std_logic := '1'; + rx_dpa_reset : in std_logic; + rx_dpa_hold : in std_logic; + rx_out : out std_logic := '0'; + rx_dpa_clk : out std_logic := '0'; + rx_dpa_loaden : out std_logic := '0'; + rx_dpa_locked : out std_logic := '0' ); + end component; -- stratixiii_lvds_rx_dpa + + -- stratix V local clock divider block + component stratixv_local_clk_divider + generic ( + clk_divide_by : natural := 4 ); + + port( + clkin : in std_logic; + lloaden : out std_logic := '0' ); + end component; -- stratix V local clock divider block + +begin + +-- SIGNAL ASSIGNMENTS + rx_out <= rx_out_reg when (registered_output = "ON") + else rx_parallel_load_reg; + rx_divfwdclk <= not rx_divfwdclk_int; + dpa_fifo_in <= retime_data; + dpa_fifo_out <= fifo_out_sync_reg; + fifo_write_clk <= dpa_clock; + fifo_read_clk <= rx_fastclk; + rx_in_reg_clk <= rx_fastclk; + rx_dpa_locked <=((lock_state_mc(0) and lock_state_mc(1)) and lock_out_reg_dly) when (use_dpa_calibration = true) + else lock_out_reg_dly; + rx_bload <= enable0_reg; + rx_enable_dly <= local_clk_div_lloaden when ((STRATIXV_RX_STYLE = true) and (enable_clock_pin_mode = "ON")) + else rx_enable; + fast_clock <= dpa_clock when ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "ON")) + else rx_fastclk; + rx_reg_clk <= not rx_divfwdclk_int when ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "ON")) + else rx_slowclk; + rx_dpa_sync_reg_clk <= rx_divfwdclk_int when ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "ON")) + else '0'; + int_pll_kick_reset <= ((lock_state_mc(0) and (not lock_state_mc(1))) or ((lock_state_mc(0) and lock_state_mc(1)) and rx_dpa_lock_reset)) when (use_dpa_calibration = true) + else rx_dpa_lock_reset; + pll_locked <= rx_locked; + wire_lock_state_mc_ena(1 downto 0) <= (others => ((lock_state_mc(0) and lock_state_mc(1) and rx_dpa_lock_reset) or (not lock_state_mc(0) and not lock_state_mc(1) and lock_out_regr) or (lock_state_mc(0) and not lock_state_mc(1) and lock_out_reg_dly) or (not lock_state_mc(0) and lock_state_mc(1) and lock_out_regr))); + wire_lock_state_mc_d <= ((((lock_state_mc(0) and (not lock_state_mc(1))) and lock_out_reg_dly) or (((not lock_state_mc(0)) and lock_state_mc(1)) and lock_out_regr)) and (not (((lock_state_mc(0) and lock_state_mc(1)) and rx_dpa_lock_reset) or (((not lock_state_mc(0)) and (not lock_state_mc(1))) and lock_out_regr)))) & (((((not lock_state_mc(0)) and (not lock_state_mc(1))) and lock_out_regr) or (((not lock_state_mc(0)) and lock_state_mc(1)) and lock_out_regr)) and (not (((lock_state_mc(0) and lock_state_mc(1)) and rx_dpa_lock_reset) or ((lock_state_mc(0) and (not lock_state_mc(1))) and lock_out_reg_dly)))); + dpaswitch <= ((not lock_state_mc(0)) and (not lock_state_mc(1))) when (use_dpa_calibration = true) + else '1'; + fifo_reset_regr <= (((not lock_state_mc(0)) and lock_state_mc(1)) and (lock_out_regr xor lock_out_reg_dly)) when (use_dpa_calibration = true) + else ((lock_out_regr xor lock_out_reg_dly) or (not dpa_locked) or rx_fifo_reset); + rx_in_wire <= TRANSPORT rx_in after 120 ps when ((use_dpa_calibration = true) and (dpaswitch = '1')) + else rx_in; + rx_dpaclock_wire <= TRANSPORT rx_dpaclock when ((use_external_pll = "ON") and (STRATIXV_RX_STYLE = true) and (enable_dpa_mode = "ON")) + else rx_fastclk; + +-- COMPONENT ASSIGNMENTS + STRATIXIII_DPA: + if (enable_dpa_mode = "ON") generate + + dpa_block : stratixiii_lvds_rx_dpa -- Stratix III DPA block + generic map ( + enable_soft_cdr_mode => enable_soft_cdr_mode, + sim_dpa_is_negative_ppm_drift => sim_dpa_is_negative_ppm_drift, + sim_dpa_net_ppm_variation => sim_dpa_net_ppm_variation, + enable_dpa_align_to_rising_edge_only => enable_dpa_align_to_rising_edge_only, + enable_dpa_initial_phase_selection => enable_dpa_initial_phase_selection, + dpa_initial_phase_value => dpa_initial_phase_value ) + + port map ( + rx_in => rx_in_wire, + rx_fastclk => rx_dpaclock_wire, + rx_enable => rx_enable, + rx_dpa_reset => rx_reset, + rx_dpa_hold => rx_dpll_hold, + rx_out => retime_data, + rx_dpa_clk => dpa_clock, + rx_dpa_loaden => dpa_loaden, + rx_dpa_locked => dpa_locked ); + + end generate STRATIXIII_DPA; + + + STRATIXV_RX_LOCAL_CLK_DIVIDER: + if ((STRATIXV_RX_STYLE = true) and (enable_clock_pin_mode = "ON")) generate + + rx_local_clk_divider : stratixv_local_clk_divider -- Stratix V local clock divider block + generic map ( + clk_divide_by => deserialization_factor ) + + port map ( + clkin => fast_clock, + lloaden => local_clk_div_lloaden ); + + end generate STRATIXV_RX_LOCAL_CLK_DIVIDER; + + +-- PROCESS DECLARATION + + + + -- input synchronization register + IN_SYNC_REGISTER : process (fast_clock) + begin + if (fast_clock = '1' and fast_clock'event) then + rx_in_reg_pos <= rx_in_wire; + elsif (fast_clock = '0' and fast_clock'event) then + rx_in_reg_neg <= rx_in_wire; + end if; + end process IN_SYNC_REGISTER; + + -- the deserializer + STRATIXIII_DESER : process(fast_clock) + begin + if (fast_clock'event and (fast_clock = '1')) then + if (rx_bload = '1') then + rx_parallel_load_reg <= rx_shift_reg; + end if; + + rx_shift_reg <= rx_shift_reg(deserialization_factor-2 downto 0) & bitslip_mux_out; + + -- Registering load enable signal + if ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "ON")) then + enable0_reg <= load_enable_cdr; + else + enable0_reg <= rx_enable_dly; + end if; + end if; + end process STRATIXIII_DESER; + + STRATIXIII_FWDCLK : + + if ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "ON")) generate + -- STRATIXIII forwarded clock + process (fast_clock) + variable div_clk_count_pos : integer := 0; + variable div_clk_count_neg : integer := 0; + begin + if (fast_clock = '1' and fast_clock'event) then + if (div_clk_count_pos = deserialization_factor) then + div_clk_count_pos := 1; + else + div_clk_count_pos := div_clk_count_pos + 1; + end if; + elsif (fast_clock = '0' and fast_clock'event) then + div_clk_count_neg := div_clk_count_pos; + end if; + + -- even deser mode + if (deserialization_factor rem 2 = 0) then + if (div_clk_count_pos = 1) then + rx_divfwdclk_int <= '0'; + elsif (div_clk_count_pos = ((deserialization_factor/2) + 1)) then + rx_divfwdclk_int <= '1'; + end if; + else + -- odd deser mode + if (div_clk_count_pos = 1) then + rx_divfwdclk_int <= '0'; + elsif (div_clk_count_neg = ((deserialization_factor+1) / 2)) then + rx_divfwdclk_int <= '1'; + end if; + end if; + + if (div_clk_count_neg = (deserialization_factor-1)) then + load_enable_cdr <= '1'; + elsif (div_clk_count_neg = deserialization_factor) then + load_enable_cdr <= '0'; + end if; + + end process; + + end generate STRATIXIII_FWDCLK; + + -- STRATIXIII bitslip logic + STRATIXIII_BITSLIP : process (fast_clock, rx_cda_reset) + variable start_corrupt_bits : boolean := false; + variable num_corrupt_bits : integer := 0; + variable bitslip_count : integer := 0; + variable shift_reg_chain : std_logic_vector(MUX_WIDTH-1 downto 0) := (others => '0'); + begin + if (rx_cda_reset = '1') then + bitslip_count := 0; + rx_cda_max <= '0'; + end if; + if (fast_clock'event and (fast_clock = '1')) then + if ((((rx_channel_data_align = '1') and + (rx_channel_data_align_pre = '0')) or + ((start_corrupt_bits = true) and + (num_corrupt_bits < 4) and + (rx_channel_data_align = '1'))) and + (x_on_bitslip = "ON")) then + bitslip_mux_out <= 'X'; + else + bitslip_mux_out <= shift_reg_chain(bitslip_count); + end if; + + for j in data_align_rollover -1 downto 0 loop + shift_reg_chain(j + 1) := shift_reg_chain(j); + end loop; + + if ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "ON"))then + shift_reg_chain(0) := retime_data; + elsif ((enable_dpa_mode = "ON") and ((rx_dpll_enable = '1') or (dpaswitch = '1')))then + shift_reg_chain(0) := dpa_fifo_out; + elsif (rx_align_data_reg = "RISING_EDGE") then + shift_reg_chain(0) := rx_in_reg_pos; + else + shift_reg_chain(0) := rx_in_reg_neg; + end if; + + if ((rx_channel_data_align = '1') and + (rx_channel_data_align_pre = '0'))then + bitslip_count := (bitslip_count + 1) rem (data_align_rollover + 1); + if (bitslip_count = data_align_rollover) then + rx_cda_max <= '1'; + else + rx_cda_max <= '0'; + end if; + + start_corrupt_bits := true; + num_corrupt_bits := 1; + elsif ((rx_channel_data_align = '0') and + (rx_channel_data_align_pre = '1'))then + start_corrupt_bits := false; + num_corrupt_bits := 0; + end if; + + if (start_corrupt_bits = true) then + if (num_corrupt_bits = 3) then + start_corrupt_bits := false; + else + num_corrupt_bits := num_corrupt_bits + 1; + end if; + end if; + rx_channel_data_align_pre <= rx_channel_data_align; + + end if; + end process STRATIXIII_BITSLIP; + + + STRATIXIII_DPA_FIFO : + + if ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "OFF")) generate + + -- STRATIXIII Phase Compensation FIFO + DPA_FIFO : process (fifo_write_clk, fifo_read_clk, rx_reset, fifo_reset_regr) + variable wrPtr : integer := 0; + variable rdPtr : integer := 3; + variable fifo_in_sync_reg : std_logic := '0'; + begin + if (rx_reset = '1' or fifo_reset_regr = '1') then + wrPtr := 0; + rdPtr := 3; + ram_array <= (others => '0'); + fifo_in_sync_reg := '0'; + fifo_out_sync_reg <= '0'; + write_side_sync_reset <= '1'; + read_side_sync_reset <= '1'; + else + if (fifo_write_clk'event and (fifo_write_clk = '1')) then + write_side_sync_reset <= '0'; + if (write_side_sync_reset = '0') then + ram_array(wrPtr) <= fifo_in_sync_reg; + fifo_in_sync_reg := dpa_fifo_in; + wrPtr := (wrPtr + 1) rem 6; + end if; + end if; + + if (fifo_read_clk'event and (fifo_read_clk = '1')) then + read_side_sync_reset <= '0'; + if (read_side_sync_reset = '0') then + fifo_out_sync_reg <= ram_array(rdPtr); + rdPtr := (rdPtr + 1) rem 6; + end if; + end if; + end if; + end process DPA_FIFO; + + end generate STRATIXIII_DPA_FIFO; + + OUTPUT_REGISTER : process (rx_reg_clk) + begin + if (rx_reg_clk = '1' and rx_reg_clk'event) then + if ((enable_dpa_mode = "ON") and (enable_soft_cdr_mode = "ON")) then + rx_out_reg <= rx_dpa_sync_reg; + else + rx_out_reg <= rx_parallel_load_reg; + end if; + end if; + end process OUTPUT_REGISTER; + + DPA_SYNC_REGISTER : process (rx_dpa_sync_reg_clk) + begin + if ((rx_dpa_sync_reg_clk = '1') and rx_dpa_sync_reg_clk'event) then + rx_dpa_sync_reg <= rx_parallel_load_reg; + end if; + end process DPA_SYNC_REGISTER; + + + + + + + STRATIXIII_DPA_LOCKED : process (rx_slowclk, rx_reset, rx_fifo_reset, pll_locked ,int_pll_kick_reset) + variable accum_regr_temp : unsigned(8 downto 0) := (others => '0'); + variable int_accum_regr_temp : integer; + begin + if (rx_reset = '1' or pll_locked = '0' or int_pll_kick_reset = '1') then + extra_regr <= '0'; + lock_out_regr <= '0'; + for j in deserialization_factor-1 downto 0 loop + pad_regr(j) <= '0'; + end loop; + for j in 8 downto 0 loop + accum_regr_temp(j) := '0'; + end loop; + if (rx_reset = '1' or pll_locked = '0') then + lock_out_reg_dly <= '0'; + end if; + elsif rising_edge(rx_slowclk) then + for j in deserialization_factor-1 downto 0 loop + if (registered_output = "ON") then + pad_regr <= rx_out_reg; + else + pad_regr <= rx_parallel_load_reg; + end if; + end loop; + extra_regr <= pad_regr(deserialization_factor-1); + in_bus_add(0) <= extra_regr xor pad_regr(0); + lock_out_reg_dly <= lock_out_regr; + for j in deserialization_factor-1 downto 1 loop + in_bus_add(j) <= pad_regr(j) xor pad_regr(j-1); + end loop; + int_accum_regr_temp := conv_integer(accum_regr_temp); + for j in deserialization_factor-1 downto 0 loop + if (in_bus_add(j) = '1') then + int_accum_regr_temp := int_accum_regr_temp + 1; + end if; + end loop; + accum_regr_temp := conv_unsigned(int_accum_regr_temp, 9); + if (accum_regr_temp >= 256) then + lock_out_regr <= '1'; + end if; + end if; + + if (use_dpa_calibration = true) then + if (rx_reset = '1' or pll_locked = '0') then + lock_state_mc(1 downto 0) <= (others => '0'); + elsif rising_edge(rx_slowclk) then + if (wire_lock_state_mc_ena(1) = '1') then + lock_state_mc(1) <= wire_lock_state_mc_d(1); + end if; + if (wire_lock_state_mc_ena(0) = '1') then + lock_state_mc(0) <= wire_lock_state_mc_d(0); + end if; + end if; + end if; + end process STRATIXIII_DPA_LOCKED; + +end behavior; + +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : stratixiii_lvds_rx +-- +-- Description : Stratix III lvds receiver. Support both the dpa and non-dpa +-- mode. +-- +-- Limitation : Only available to Stratix III. +-- +-- Results Expected: Deserialized output data, dpa lock signal, forwarded clock +-- and status bit indicating whether maximum bitslip has been +-- reached. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use work.stratixiii_lvds_rx_channel; + +-- ENTITY DECLARATION +entity stratixiii_lvds_rx is + +-- GENERIC DECLARATION + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + enable_dpa_mode : string := "OFF"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + x_on_bitslip : string := "ON"; + rx_align_data_reg : string := "RISING_EDGE"; + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_output_clock_phase_shift : integer := 0; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value : natural := 0; + registered_output : string := "ON"; + enable_clock_pin_mode : string := "UNUSED"; + use_dpa_calibration : boolean := false; + ARRIAII_RX_STYLE : boolean := false; + STRATIXV_RX_STYLE : boolean := false ); + +-- PORT DECLARATION + port( +--INPUT PORT DECLARATION + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_fastclk : in std_logic; --Required port + rx_slowclk : in std_logic; --Required port + rx_enable : in std_logic := '1'; + rx_dpaclock : in std_logic; + rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1'); + rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_locked : in std_logic; + +-- OUTPUT PORT DECLARATION + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0) := (others => '0') ); + +end stratixiii_lvds_rx; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of stratixiii_lvds_rx is + + +-- COMPONENT DECLARATION + + -- stratixiii lvds_rx_channel + component stratixiii_lvds_rx_channel + generic ( + deserialization_factor : natural; -- Required parameter + enable_dpa_mode : string := "OFF"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + x_on_bitslip : string := "ON"; + rx_align_data_reg : string := "RISING_EDGE"; + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_output_clock_phase_shift : integer := 0; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value : natural := 0; + registered_output : string := "ON"; + enable_clock_pin_mode : string := "UNUSED"; + use_dpa_calibration : boolean := false; + ARRIAII_RX_STYLE : boolean := false; + STRATIXV_RX_STYLE : boolean := false ); + + port ( + rx_in : in std_logic; --Required port + rx_fastclk : in std_logic; --Required port + rx_slowclk : in std_logic; --Required port + rx_enable : in std_logic := '1'; + rx_dpaclock : in std_logic; + rx_reset : in std_logic; + rx_dpll_reset : in std_logic; + rx_dpll_hold : in std_logic; + rx_dpll_enable : in std_logic; + rx_fifo_reset : in std_logic; + rx_channel_data_align : in std_logic; + rx_cda_reset : in std_logic; + rx_dpa_lock_reset : in std_logic; + rx_locked : in std_logic; + rx_out : out std_logic_vector(deserialization_factor-1 downto 0); + rx_dpa_locked : out std_logic; + rx_cda_max : out std_logic; + rx_divfwdclk : out std_logic ); + end component; -- stratixiii_lvds_rx_channel + +begin + + +-- COMPONENT ASSIGNMENTS + + STRATIXIII_RX_CHANNEL : + for i in 0 to number_of_channels-1 generate + + LVDS_CHANNEL: stratixiii_lvds_rx_channel + generic map ( + deserialization_factor => deserialization_factor, + enable_dpa_mode => enable_dpa_mode, + data_align_rollover => data_align_rollover, + lose_lock_on_one_change => lose_lock_on_one_change, + reset_fifo_at_first_lock => reset_fifo_at_first_lock, + x_on_bitslip => x_on_bitslip, + rx_align_data_reg => rx_align_data_reg, + enable_soft_cdr_mode => enable_soft_cdr_mode, + sim_dpa_output_clock_phase_shift => sim_dpa_output_clock_phase_shift, + sim_dpa_is_negative_ppm_drift => sim_dpa_is_negative_ppm_drift, + sim_dpa_net_ppm_variation => sim_dpa_net_ppm_variation, + enable_dpa_align_to_rising_edge_only => enable_dpa_align_to_rising_edge_only, + enable_dpa_initial_phase_selection => enable_dpa_initial_phase_selection, + dpa_initial_phase_value => dpa_initial_phase_value, + registered_output => registered_output, + enable_clock_pin_mode => enable_clock_pin_mode, + use_dpa_calibration => use_dpa_calibration, + ARRIAII_RX_STYLE => ARRIAII_RX_STYLE, + STRATIXV_RX_STYLE => STRATIXV_RX_STYLE ) + + port map ( + rx_in => rx_in(i), + rx_fastclk => rx_fastclk, + rx_slowclk => rx_slowclk, + rx_enable => rx_enable, + rx_dpaclock => rx_dpaclock, + rx_reset => rx_reset(i), + rx_dpll_reset => rx_dpll_reset(i), + rx_dpll_hold => rx_dpll_hold(i), + rx_dpll_enable => rx_dpll_enable(i), + rx_fifo_reset => rx_fifo_reset(i), + rx_channel_data_align => rx_channel_data_align(i), + rx_cda_reset => rx_cda_reset(i), + rx_out => rx_out((i+1)*deserialization_factor-1 downto i*deserialization_factor), + rx_dpa_locked => rx_dpa_locked(i), + rx_cda_max => rx_cda_max(i), + rx_dpa_lock_reset => rx_dpa_lock_reset(i), + rx_locked => rx_locked, + rx_divfwdclk => rx_divfwdclk(i) ); + end generate STRATIXIII_RX_CHANNEL; + +end behavior; + +-- END OF ARCHITECTURE + + +-- START ENTITY HEADER --------------------------------------------------------- +-- +-- Entity Name : altlvds_rx +-- +-- Description : Low Voltage Differential Signaling (LVDS) receiver +-- megafunction. The altlvds_rx megafunction implements a +-- deserialization receiver. LVDS is a high speed IO interface +-- that uses inputs without a reference voltage. LVDS uses +-- two wires carrying differential values to create a single +-- channel. These wires are connected to two pins on +-- supported device to create a single LVDS channel +-- +-- Limitations : Only available for STRATIX, +-- STRATIX GX, Stratix II, Cyclone and Cyclone II families. +-- +--Results expected : output clock, deserialized output data and pll locked +-- signal. +-- +-- END ENTITY HEADER ----------------------------------------------------------- + + +-- LIBRARY USED----------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.MF_stratix_pll; +use work.MF_stratixii_pll; +use work.MF_stratixiii_pll; +use work.stratixii_lvds_rx; +use work.flexible_lvds_rx; +use work.stratixiii_lvds_rx; + +-- ENTITY DECLARATION +entity altlvds_rx is + +-- GENERIC DECLARATION + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + registered_output : string := "ON"; + inclock_period : natural := 10000; -- Required parameter + inclock_boost : natural := 0; + cds_mode : string := "UNUSED"; + intended_device_family : string := "Stratix"; + input_data_rate : natural := 0; + inclock_data_alignment : string := "UNUSED"; + registered_data_align_input : string := "ON"; + common_rx_tx_pll : string := "ON"; + enable_dpa_mode : string := "OFF"; + enable_dpa_pll_calibration : string := "OFF"; + enable_dpa_calibration : string := "ON"; + enable_dpa_fifo : string := "ON"; + use_dpll_rawperror : string := "OFF"; + use_coreclock_input : string := "OFF"; + dpll_lock_count : natural := 0; + dpll_lock_window : natural := 0; + outclock_resource : string := "AUTO"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + use_external_pll : string := "OFF"; + implement_in_les : string := "OFF"; + buffer_implementation : string := "RAM"; + port_rx_data_align : string := "PORT_CONNECTIVITY"; + port_rx_channel_data_align : string := "PORT_CONNECTIVITY"; + pll_operation_mode : string := "NORMAL"; + x_on_bitslip : string := "ON"; + use_no_phase_shift : string := "ON"; + rx_align_data_reg : string := "RISING_EDGE"; + inclock_phase_shift : integer := 0; + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_output_clock_phase_shift : integer := 0; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value :natural := 0; + pll_self_reset_on_loss_lock : string := "OFF"; + refclk_frequency : string := "UNUSED"; + enable_clock_pin_mode : string := "UNUSED"; + data_rate : string := "UNUSED"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altlvds_rx"; + -- Specifies whether the source of the input clock is from the PLL + clk_src_is_pll : string := "off" ); + +-- PORT DECLARATION + port ( +--INPUT PORT DECLARATION + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_inclock : in std_logic := '0'; + rx_syncclock : in std_logic := '0'; + rx_dpaclock : in std_logic := '0'; + rx_readclock : in std_logic := '0'; + rx_enable : in std_logic := '0'; + rx_deskew : in std_logic := '0'; + rx_pll_enable : in std_logic := '1'; + rx_data_align : in std_logic := 'Z'; + rx_data_align_reset : in std_logic := '0'; + rx_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0'); + rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0'); + rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1'); + rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => 'Z'); + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + pll_areset : in std_logic := '0'; + rx_data_reset : in std_logic := '0'; + dpa_pll_recal : in std_logic := '0'; + pll_phasedone : in std_logic := '1'; + rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + + +-- OUTPUT PORT DECLARATION + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + rx_outclock : out std_logic; + rx_locked : out std_logic; + rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0); + rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0); + rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0); + dpa_pll_cal_busy : out std_logic; + pll_phasestep : out std_logic; + pll_phaseupdown : out std_logic; + pll_phasecounterselect: out std_logic_Vector(3 downto 0); + pll_scanclk : out std_logic); + +end altlvds_rx; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of altlvds_rx is + +-- CONSTANT DECLARATION + constant STRATIX_RX_STYLE : boolean := (FEATURE_FAMILY_STRATIX_NONGX(intended_device_family) or + (FEATURE_FAMILY_STRATIXGX(intended_device_family) and + (enable_dpa_mode = "OFF"))); + constant STRATIXGX_DPA_RX_STYLE : boolean := (FEATURE_FAMILY_STRATIXGX(intended_device_family) and + (enable_dpa_mode = "ON")); + constant STRATIXII_RX_STYLE : boolean := FEATURE_FAMILY_BASE_STRATIXII(intended_device_family); + constant STRATIXIII_RX_STYLE : boolean := FEATURE_FAMILY_BASE_STRATIXIII(intended_device_family); + constant CYCLONE_RX_STYLE : boolean := FEATURE_FAMILY_BASE_CYCLONE(intended_device_family); + constant CYCLONEII_RX_STYLE : boolean := FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family); + constant CYCLONEIII_RX_STYLE : boolean := FEATURE_FAMILY_BASE_CYCLONEIII(intended_device_family); + constant ARRIAII_RX_STYLE : boolean := FEATURE_FAMILY_ARRIAIIGX(intended_device_family); + constant STRATIXV_RX_STYLE : boolean := FEATURE_FAMILY_STRATIXV(intended_device_family); + constant FAMILY_HAS_FLEXIBLE_LVDS : boolean := FEATURE_FAMILY_HAS_FLEXIBLE_LVDS(intended_device_family) or + (((STRATIX_RX_STYLE = true) or (STRATIXII_RX_STYLE = true) or + (STRATIXIII_RX_STYLE = true)) and + (implement_in_les = "ON")); + constant FAMILY_HAS_STRATIX_STYLE_PLL : boolean := FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL(intended_device_family); + constant FAMILY_HAS_STRATIXII_STYLE_PLL : boolean := FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL(intended_device_family); + constant FAMILY_HAS_STRATIXIII_STYLE_PLL : boolean := FEATURE_FAMILY_USES_STRATIXIII_PLL(intended_device_family); + constant VSERIES_FAMILY : boolean := (FEATURE_FAMILY_STRATIXV(intended_device_family) or FEATURE_FAMILY_ARRIAV(intended_device_family)); + +-- FUNCTION DECLARATION + + --- Convert integer to string --- + function int_to_str( constant value : integer ) return string is + variable ivalue : integer := 0; + variable index : integer := 0; + variable strlen : integer := 0; + variable digit : integer := 0; + variable temp : string(1 to 8) := "00000000"; + + begin + ivalue := abs(value); + strlen := 0; + + + while (ivalue > 0) loop + ivalue := ivalue/10; + strlen := strlen + 1; + end loop; + + if (strlen = 0) then + strlen := 1; + end if; + + ivalue := abs(value); + index := strlen; + + while (ivalue > 0) loop + digit := ivalue mod 10; + ivalue := ivalue/10; + + case digit is + when 0 => temp(index) := '0'; + when 1 => temp(index) := '1'; + when 2 => temp(index) := '2'; + when 3 => temp(index) := '3'; + when 4 => temp(index) := '4'; + when 5 => temp(index) := '5'; + when 6 => temp(index) := '6'; + when 7 => temp(index) := '7'; + when 8 => temp(index) := '8'; + when 9 => temp(index) := '9'; + when others => ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + + index := index - 1; + + end loop; + + if (value < 0) then + return ('-' & temp(1 to strlen)); + else + return temp(1 to strlen); + end if; + end int_to_str; + + -- M value for stratix/stratix II/Cyclone/Cyclone II PLL + function pll_m_value(constant i_input_data_rate, + i_inclock_period : in natural) return natural is + variable i_pll_m_value : natural; + begin + i_pll_m_value := (((i_input_data_rate * i_inclock_period) + + (5* 100000)) / 1000000); + + return i_pll_m_value; + + end pll_m_value; + + -- D value for Stratix/Stratix II/Cyclone/Cyclone II PLL + function pll_d_value(constant i_input_data_rate, + i_inclock_period : in natural) return natural is + variable i_pll_d_value : natural; + begin + if ((i_input_data_rate /= 0) and (i_inclock_period /= 0)) then + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + i_pll_d_value := 2; + else + i_pll_d_value := 1; + end if; + else + i_pll_d_value := 1; + end if; + + return i_pll_d_value; + end pll_d_value; + + --- calculate clock boost value need by the pll --- + function clock_boost_calc (constant i_input_data_rate, + i_inclock_period, + i_deserialization_factor, + i_inclock_boost : in natural) return natural is + variable i_input_clock_boost : natural; + + begin + if ((i_input_data_rate /= 0) and (i_inclock_period /= 0)) then + i_input_clock_boost := pll_m_value (i_input_data_rate, + i_inclock_period); + else + if (inclock_boost = 0) then + i_input_clock_boost := i_deserialization_factor; + else + i_input_clock_boost := i_inclock_boost; + end if; + end if; + + return i_input_clock_boost; + + end clock_boost_calc; + + + --- get phase delay in ps for stratix pll --- + function get_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + variable x, int_delay : integer := 0; + + begin + + -- get delay in ps ( * inclock period / 360 degress ) + if ((i_phase_delay = "UNUSED") or (VSERIES_FAMILY = true)) then + int_delay := inclock_phase_shift; + else + if (i_phase_delay = "EDGE_ALIGNED") then + my_phase := 0; + elsif (i_phase_delay = "CENTER_ALIGNED") then -- CENTER_ALIGNED means 180 degrees + my_phase := (180 * inclock_period) / 360; + elsif (i_phase_delay = "45_DEGREES") then + my_phase := (45 * inclock_period) / 360; + elsif (i_phase_delay = "90_DEGREES") then + my_phase := (90 * inclock_period) / 360; + elsif (i_phase_delay = "135_DEGREES") then + my_phase := (135 * inclock_period) / 360; + elsif (i_phase_delay = "180_DEGREES") then + my_phase := (180 * inclock_period) / 360; + elsif (i_phase_delay = "225_DEGREES") then + my_phase := (225 * inclock_period) / 360; + elsif (i_phase_delay = "270_DEGREES") then + my_phase := (270 * inclock_period) / 360; + elsif (i_phase_delay = "315_DEGREES") then + my_phase := (315 * inclock_period) / 360; + else + ASSERT FALSE + REPORT "Invalid clock data alignment. Using 'EDGE_ALIGNED' instead" + SEVERITY WARNING; + my_phase :=0; + end if; + + -- Add 1 to "round up" calculation result + my_phase := my_phase + 1; + + -- phase shift in ps = ( * inclock_period / 360 ) / fast clock multiply_by factor + -- in other words, the phase shift is a percentage of the fast clock period + int_delay := my_phase / clock_boost_calc(input_data_rate, inclock_period, deserialization_factor, inclock_boost); + + -- Add 1 to "round up" calculation result + int_delay := int_delay + 1; + end if; + + return int_delay; + + end get_phase_delay; + + + --- get phase delay in ps for stratix ii pll --- + function get_stxii_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + begin + + my_phase := get_phase_delay(i_phase_delay) - (inclock_period / (2 * clock_boost_calc(input_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + + return my_phase; + + end get_stxii_phase_delay; + + --- get clk1_multiply_by value for PLL (for flexible lvds) + function get_flvds_clk1_multiply_by ( constant i_deserialization_factor : in natural) return natural is + variable clk1_mult_by : natural := 0; + begin + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + if ((i_deserialization_factor rem 2) = 1) then + clk1_mult_by := clock_boost_calc(input_data_rate, + inclock_period, deserialization_factor, inclock_boost); + else + clk1_mult_by := 1; + end if; + end if; + + return clk1_mult_by; + + end get_flvds_clk1_multiply_by; + + --- get clk1_divide_by value for PLL (for flexible lvds) + function get_flvds_clk1_divide_by ( constant i_deserialization_factor : in natural) return natural is + variable clk1_div_by : natural := 0; + begin + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + if ((i_deserialization_factor rem 2) = 1) then + clk1_div_by := i_deserialization_factor; + clk1_div_by := clk1_div_by * pll_d_value(input_data_rate, + inclock_period); + else + clk1_div_by := 1; + end if; + end if; + + return clk1_div_by; + + end get_flvds_clk1_divide_by; + + --- get clk1_phase_shift value for PLL (for flexible lvds) + function get_flvds_clk1_phase_shift ( constant i_deserialization_factor : in natural; + constant i_phase_shift : in string) return string is + begin + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + if ((i_deserialization_factor rem 2) = 1) then + return i_phase_shift; + else + return "0"; + end if; + else + return "0"; + end if; + end get_flvds_clk1_phase_shift; + + --- get clk2_multiply_by value for PLL (for flexible lvds) + function get_flvds_clk2_multiply_by ( constant i_deserialization_factor : in natural) return natural is + variable clk2_mult_by : natural := 0; + begin + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + if ((i_deserialization_factor rem 2) = 1) then + clk2_mult_by := clock_boost_calc(input_data_rate, + inclock_period, deserialization_factor, inclock_boost) * 2; + else + clk2_mult_by := clock_boost_calc(input_data_rate, + inclock_period, deserialization_factor, inclock_boost); + end if; + end if; + + return clk2_mult_by; + + end get_flvds_clk2_multiply_by; + + --- get clk2_divide_by value for PLL (for flexible lvds) + function get_flvds_clk2_divide_by ( constant i_deserialization_factor : in natural) return natural is + variable clk2_div_by : natural := 0; + begin + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + if ((i_deserialization_factor rem 2) = 0) then + clk2_div_by := i_deserialization_factor / 2; + else + clk2_div_by := i_deserialization_factor; + end if; + end if; + + clk2_div_by := clk2_div_by * pll_d_value(input_data_rate, + inclock_period); + return clk2_div_by; + + end get_flvds_clk2_divide_by; + + --- get pll_type for PLL (for flexible lvds) + function get_flvds_pll_type ( constant i_inclock_alignment : in string) return string is + begin + if (i_inclock_alignment = "UNUSED") then + return "auto"; + else + return "flvds"; + end if; + + end get_flvds_pll_type; + + --- get phase delay in ps for cyclone ii and stratix II in LE mode --- + function get_stxii_le_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + begin + if ((use_no_phase_shift = "OFF") and (pll_operation_mode = "SOURCE_SYNCHRONOUS")) then + my_phase := get_phase_delay(i_phase_delay) - (inclock_period / (4 * clock_boost_calc(input_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + else + my_phase := get_phase_delay(i_phase_delay); + end if; + + return my_phase; + + end get_stxii_le_phase_delay; + + --- get clk1_phase_shift value for PLL (for flexible lvds) + function get_stxii_le_clk1_phase_shift ( constant i_deserialization_factor : in natural; + constant i_phase_shift : in string) return string is + begin + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + if ((i_deserialization_factor rem 2) = 1) then + return i_phase_shift; + else + return "0"; + end if; + else + return "0"; + end if; + end get_stxii_le_clk1_phase_shift; + + --- get phase delay in ps for stratix III in LE mode --- + function get_stxiii_le_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + begin + my_phase := get_phase_delay(i_phase_delay) - (inclock_period * pll_d_value(input_data_rate,inclock_period)/ + (4 * clock_boost_calc(input_data_rate,inclock_period, deserialization_factor, inclock_boost))); + return my_phase; + + end get_stxiii_le_phase_delay; + + --- get phase_shift value for the clock that acts as enable signal (for StratixIII lvds) + function get_clk_ena_phase_shift ( constant i_phase_shift : in string) return string is + variable fast_clk_ena_phase_shift : integer := 0; + begin + + fast_clk_ena_phase_shift := (deserialization_factor*2-3) * (inclock_period/(2*clock_boost_calc(input_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + + return int_to_str(get_stxii_phase_delay(i_phase_shift) + fast_clk_ena_phase_shift); + + end get_clk_ena_phase_shift; + +-- converts uppercase parameter values (e.g. "AUTO") to lowercase ("auto") +-- as expected by stratix_pll model +function alpha_tolower (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; + +begin + for i in 1 to string_length loop + case given_string(i) is + when 'A' => result_string(i) := 'a'; + when 'B' => result_string(i) := 'b'; + when 'C' => result_string(i) := 'c'; + when 'D' => result_string(i) := 'd'; + when 'E' => result_string(i) := 'e'; + when 'F' => result_string(i) := 'f'; + when 'G' => result_string(i) := 'g'; + when 'H' => result_string(i) := 'h'; + when 'I' => result_string(i) := 'i'; + when 'J' => result_string(i) := 'j'; + when 'K' => result_string(i) := 'k'; + when 'L' => result_string(i) := 'l'; + when 'M' => result_string(i) := 'm'; + when 'N' => result_string(i) := 'n'; + when 'O' => result_string(i) := 'o'; + when 'P' => result_string(i) := 'p'; + when 'Q' => result_string(i) := 'q'; + when 'R' => result_string(i) := 'r'; + when 'S' => result_string(i) := 's'; + when 'T' => result_string(i) := 't'; + when 'U' => result_string(i) := 'u'; + when 'V' => result_string(i) := 'v'; + when 'W' => result_string(i) := 'w'; + when 'X' => result_string(i) := 'x'; + when 'Y' => result_string(i) := 'y'; + when 'Z' => result_string(i) := 'z'; + when others => result_string(i) := given_string(i); + end case; + end loop; + + return (result_string(1 to string_length)); +end; + +-- CONSTANT DECLARATION + -- these constants are PLL parameters calculated from the altlvds_rx parameters given + constant PHASE_INCLOCK : string := int_to_str(get_phase_delay(inclock_data_alignment)); + constant STXII_PHASE_INCLOCK : string := int_to_str(get_stxii_phase_delay(inclock_data_alignment)); + constant INT_CLOCK_BOOST : natural := clock_boost_calc(input_data_rate, inclock_period, deserialization_factor, inclock_boost); + constant REGISTER_WIDTH : natural := deserialization_factor * number_of_channels; + constant FLVDS_CLK0_DIV : natural := pll_d_value(input_data_rate, inclock_period); + constant FLVDS_CLK1_MULT : natural := get_flvds_clk1_multiply_by(deserialization_factor); + constant FLVDS_CLK1_DIV : natural := get_flvds_clk1_divide_by(deserialization_factor); + constant FLVDS_CLK2_MULT : natural := get_flvds_clk2_multiply_by(deserialization_factor); + constant FLVDS_CLK2_DIV : natural := get_flvds_clk2_divide_by(deserialization_factor); + constant FLVDS_CLK1_PHASE_SHIFT : string := get_flvds_clk1_phase_shift(deserialization_factor, PHASE_INCLOCK); + constant FLVDS_PLL_TYPE : string := get_flvds_pll_type(inclock_data_alignment); + constant STXII_LE_PHASE_INCLOCK : string := int_to_str(get_stxii_le_phase_delay(inclock_data_alignment)); + constant STXII_LE_CLK1_PHASE_SHIFT : string := get_stxii_le_clk1_phase_shift(deserialization_factor, STXII_LE_PHASE_INCLOCK); + constant STXIII_LE_PHASE_INCLOCK : string := int_to_str(get_stxiii_le_phase_delay(inclock_data_alignment)); + constant STXIII_LE_CLK1_PHASE_SHIFT : string := get_stxii_le_clk1_phase_shift(deserialization_factor, STXIII_LE_PHASE_INCLOCK); + constant IS_USING_EXTRA_DDIO_REG : boolean := (CYCLONE_RX_STYLE = true) or (CYCLONEII_RX_STYLE = true) or (CYCLONEIII_RX_STYLE = true); + constant IS_USING_EXTRA_PLL_CLK : boolean := (CYCLONE_RX_STYLE = false) and (CYCLONEII_RX_STYLE = false); + constant IS_ADDING_EXTRA_LATENCY : boolean := (CYCLONE_RX_STYLE = true) or (CYCLONEII_RX_STYLE = true) or (CYCLONEIII_RX_STYLE = true); + constant CLK_ENA_PHASE_SHIFT : string := get_clk_ena_phase_shift(inclock_data_alignment); + constant use_dpa_calibration : boolean := ((ARRIAII_RX_STYLE = true) and (enable_dpa_calibration = "ON")); + +-- TYPE DECLARATION + type CHANNEL_CNT is array (number_of_channels-1 downto 0) of integer; + type DPA_FIFO_RAM is array (3 downto 0) of std_logic_vector(REGISTER_WIDTH -1 downto 0); + +-- SIGNAL DECLARATION + signal rxpdat1 : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rxpdat2 : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rxpdat3 : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rxpdatout : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rx_out_reg : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rx_out_rgd : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rx_out_rgd2 : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rx_out_extra_yeager_reg : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rx_out_int : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal data_out : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal serdes_data_out : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal write_data : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal read_data : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal rx_ddio_in : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal stratixii_dataout : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal stratixiii_dataout : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + signal flvds_dataout : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + + -- to store previous port values + signal rx_coreclk_pre : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal rx_channel_data_align_wire : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal rx_channel_data_align_pre : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + signal pclk_pre : std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + + -- constant signals + signal temp_high : std_logic_vector (5 downto 0):= (others => '1'); + signal temp_z : std_logic_vector (number_of_channels-1 downto 0):= (others => 'Z'); + + -- FIFO ram for Stratix GX + signal ram_array : DPA_FIFO_RAM := (others => (others => '0')); + + -- PLL ports + signal rx_clock0_int : std_logic := '0'; -- fast clock + signal rx_clock1_int : std_logic := '0'; -- slow clock + signal rx_pll_clk0 : std_logic := '0'; + signal rx_pll_clk1 : std_logic := '0'; + signal rx_reg_clk : std_logic := '0'; + signal yeager_locked_int : std_logic := '0'; + signal aurora_locked_int : std_logic := '0'; + signal stratixii_locked_int : std_logic := '0'; + signal stratixiii_locked_int : std_logic := '0'; + signal cyclone_locked_int : std_logic := '0'; + signal cycloneii_locked_int : std_logic := '0'; + signal rx_locked_int : std_logic := '0'; + signal temp_zero : std_logic := '0'; + + -- Stratix, Stratix II, Stratix GX, Cyclone and Cyclone II specific signals + signal rx_data_align_reg : std_logic := '0'; + signal rx_data_align_int : std_logic := '0'; + signal rx_data_align_wire : std_logic := '0'; + signal rx_data_align_clk : std_logic := '0'; + signal enable0_reg : std_logic; + signal enable0_pipe : std_logic; + signal enable0_neg : std_logic; + signal enable1_reg : std_logic; + signal sampling : std_logic := '0'; + signal yeager_clock : std_logic_vector (5 downto 0) := (others => '0'); + signal aurora_clock : std_logic_vector (5 downto 0) := (others => '0'); + signal stratixii_clock : std_logic_vector (5 downto 0) := (others => '0'); + signal stratixiii_clock : std_logic_vector (9 downto 0) := (others => '0'); + signal cyclone_clock : std_logic_vector (5 downto 0) := (others => '0'); + signal cycloneii_clock : std_logic_vector (5 downto 0) := (others => '0'); + signal pclk : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal clkout_tmp : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal sync_reset : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal stratixii_dpa_locked : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal stratixiii_dpa_locked : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal stratixii_cda_max : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal stratixiii_cda_max : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal stratixiii_divfwdclk : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal rx_pll_sclkout0 : std_logic := '0'; + signal rx_pll_sclkout1 : std_logic := '0'; + signal stratixii_sclkout0 : std_logic := '0'; + signal stratixii_fastclk : std_logic := '0'; + signal stratixii_enable : std_logic := '0'; + signal stratixiii_fastclk : std_logic := '0'; + signal stratixiii_slowclk : std_logic := '0'; + signal stratixiii_enable : std_logic := '0'; + signal rx_pll_enable0 : std_logic := '0'; + signal rx_pll_enable1 : std_logic := '0'; + signal rx_pll_sclkout0_dly : std_logic := '0'; + signal flvds_fastclk : std_logic := '0'; + signal flvds_slowclk : std_logic := '0'; + signal flvds_syncclk : std_logic := '0'; + signal flvds_rx_data_align : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal flvds_rx_cda_reset : std_logic_vector (number_of_channels-1 downto 0) := (others => '0'); + signal pll_lock_sync : std_logic := '1'; + + +-- COMPONENT DECLARATION + + -- pll definition + component MF_stratix_pll + generic ( + pll_type : string := "lvds"; + inclk0_input_frequency : positive ; + inclk1_input_frequency : positive ; + valid_lock_multiplier : integer := 1; + simulation_type : string := "functional"; + clk0_multiply_by : positive := 1; + clk0_divide_by : positive := 1; + clk0_phase_shift : string := "0"; + clk1_multiply_by : positive := 1; + clk1_divide_by : positive := 1; + clk1_phase_shift : string := "0"; + clk2_multiply_by : positive := 1; + clk2_divide_by : positive := 1; + clk2_phase_shift : string := "0"; + enable0_counter : string := "l0"; + enable1_counter : string := "l1"; + family_name : string := "Stratix"; + m : integer := 0 ); + + port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); + fbin : in std_logic := '1'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + clkena : in std_logic_vector(5 downto 0) := (others => '1'); + extclkena : in std_logic_vector(3 downto 0) := (OTHERS=>'1'); + scanaclr : in std_logic := '0'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + comparator : in std_logic := '0'; + clk : out std_logic_vector(5 downto 0); + locked : out std_logic; + enable0 : out std_logic; + enable1 : out std_logic ); + end component; -- MF_stratix_pll + + component MF_stratixii_pll + generic ( + operation_mode : string := "normal"; + pll_type : string := "lvds"; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + inclk0_input_frequency : positive ; + inclk1_input_frequency : positive ; + simulation_type : string := "functional"; + clk0_multiply_by : positive := 1; + clk0_divide_by : positive := 1; + clk0_phase_shift : string := "0"; + clk1_multiply_by : positive := 1; + clk1_divide_by : positive := 1; + clk1_phase_shift : string := "0"; + clk2_multiply_by : positive := 1; + clk2_divide_by : positive := 1; + clk2_phase_shift : string := "0"; + sclkout0_phase_shift : string := "0"; + enable0_counter : string := "c0"; + enable1_counter : string := "c1"; + family_name : string := "Stratix II"; + m : integer := 0 ); + + port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); + fbin : in std_logic := '1'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanread : in std_logic := '0'; + scanwrite : in std_logic := '0'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + testin : in std_logic_vector(3 downto 0) := (OTHERS=>'0'); + clk : out std_logic_vector(5 downto 0); + locked : out std_logic; + enable0 : out std_logic; + enable1 : out std_logic; + sclkout : out std_logic_vector(1 downto 0) ); + end component; -- MF_stratixii_pll + + component MF_stratixiii_pll + generic ( + operation_mode : string := "normal"; + pll_type : string := "lvds"; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + inclk0_input_frequency : positive ; + inclk1_input_frequency : positive ; + simulation_type : string := "functional"; + clk0_multiply_by : positive := 1; + clk0_divide_by : positive := 1; + clk0_phase_shift : string := "0"; + clk1_multiply_by : positive := 1; + clk1_divide_by : positive := 1; + clk1_duty_cycle : integer := 50; + clk1_phase_shift : string := "0"; + clk2_multiply_by : positive := 1; + clk2_divide_by : positive := 1; + clk2_phase_shift : string := "0"; + family_name : string := "Stratix III"; + self_reset_on_loss_lock : string := "OFF"; + m : integer := 0 ); + + port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); + fbin : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanclk : in std_logic := '1'; + scandata : in std_logic := '1'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + phasecounterselect : in std_logic_vector(3 downto 0) := (OTHERS=>'1'); + phaseupdown : in std_logic := '1'; + phasestep : in std_logic := '1'; + clk : out std_logic_vector(9 downto 0); + locked : out std_logic ); + end component; -- MF_stratixiii_pll + + component stratixii_lvds_rx + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + enable_dpa_mode : string := "OFF"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + x_on_bitslip : string := "ON" ); + + port ( + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_fastclk : in std_logic; --Required port + rx_enable : in std_logic := '1'; + rx_locked : in std_logic; + rx_dpaclock : in std_logic := '0'; + rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1'); + rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0); + rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0) ); + end component; -- stratixii_lvds_rx + + component stratixiii_lvds_rx + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + enable_dpa_mode : string := "OFF"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + x_on_bitslip : string := "ON"; + rx_align_data_reg : string := "RISING_EDGE"; + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_output_clock_phase_shift : integer := 0; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value :natural := 0; + registered_output : string := "ON"; + enable_clock_pin_mode : string := "UNUSED"; + use_dpa_calibration : boolean := false; + ARRIAII_RX_STYLE : boolean := false; + STRATIXV_RX_STYLE : boolean := false ); + + port ( + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_fastclk : in std_logic; --Required port + rx_slowclk : in std_logic; --Required port + rx_dpaclock : in std_logic; + rx_enable : in std_logic := '1'; + rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1'); + rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_locked : in std_logic := '1'; + rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0); + rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0); + rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0) := (others => '0') ); + end component; -- stratixiii_lvds_rx + + component flexible_lvds_rx + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; + use_extra_ddio_register : boolean := true; + use_extra_pll_clk : boolean := false; + buffer_implementation : string := "RAM"; + registered_data_align_input : string := "OFF"; + use_external_pll : string := "OFF"; + registered_output : string := "OFF"; + add_latency : boolean := true ); + + port ( + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_fastclk : in std_logic; --Required port + rx_slowclk : in std_logic; --Required port + rx_syncclk : in std_logic; --Required port + pll_areset : in std_logic; --Required port + rx_data_reset : in std_logic; + rx_locked : in std_logic; --Required port + rx_data_align : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0); --Required port + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0) ); + end component; -- flexible_lvds_rx + +begin + +-- SIGNAL ASSIGNMENTS + rx_out <= flvds_dataout when (FAMILY_HAS_FLEXIBLE_LVDS = true) and (deserialization_factor > 2) + else stratixiii_dataout when (STRATIXIII_RX_STYLE = true) and (deserialization_factor > 2) + else rx_out_reg when (registered_output = "ON") and (use_external_pll = "OFF") + else rx_out_int; + + rx_dpa_locked <= stratixii_dpa_locked when (STRATIXII_RX_STYLE = true) + else stratixiii_dpa_locked when (STRATIXIII_RX_STYLE = true) + else (others => '1'); + + rx_cda_max <= stratixii_cda_max when (STRATIXII_RX_STYLE = true) + else stratixiii_cda_max when (STRATIXIII_RX_STYLE = true) + else (others => '0'); + + rx_out_int <= rx_in when (deserialization_factor = 1) + else rx_ddio_in when (deserialization_factor = 2) + else stratixii_dataout when (STRATIXII_RX_STYLE = true) + else rxpdatout when (STRATIXGX_DPA_RX_STYLE = true) + else rx_out_extra_yeager_reg when (STRATIX_RX_STYLE = true) + else data_out; + + rx_out_reg <= rx_out_rgd2 when ((STRATIXGX_DPA_RX_STYLE = true) and + (use_coreclock_input = "ON")) + else rx_out_rgd; + rx_clock0_int <= rx_pll_clk0 when (deserialization_factor > 2) + else rx_inclock; + + rx_clock1_int <= rx_pll_clk1 when (deserialization_factor > 2) + else rx_inclock; + + rx_divfwdclk <= stratixiii_divfwdclk; + + rx_outclock <= rx_clock1_int; + + rx_reg_clk <= rx_inclock when ((use_external_pll = "ON") or (deserialization_factor <= 2)) + else rx_clock1_int; + + rx_locked <= rx_locked_int and pll_lock_sync when (((STRATIXIII_RX_STYLE = true) or + (CYCLONEIII_RX_STYLE = true)) and + (deserialization_factor > 2)) + else rx_locked_int when (deserialization_factor > 2) + else '1'; + + rx_pll_clk0 <= yeager_clock(0) when (STRATIX_RX_STYLE = true) + else aurora_clock(0) when (STRATIXGX_DPA_RX_STYLE = true) + else stratixii_clock(0) when (STRATIXII_RX_STYLE = true) + else '0'; + + rx_pll_clk1 <= cyclone_clock(2) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIX_STYLE_PLL = true)) + else cycloneii_clock(2) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXII_STYLE_PLL = true)) + else yeager_clock(2) when (STRATIX_RX_STYLE = true) + else aurora_clock(2) when (STRATIXGX_DPA_RX_STYLE = true) + else stratixii_clock(2) when (STRATIXII_RX_STYLE = true) + else stratixiii_clock(2) when (STRATIXIII_RX_STYLE = true) or (CYCLONEIII_RX_STYLE = true) + else '0'; + + rx_locked_int <= '1' when (use_external_pll = "ON") + else cyclone_locked_int when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIX_STYLE_PLL = true)) + else cycloneii_locked_int when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXII_STYLE_PLL = true)) + else yeager_locked_int when (STRATIX_RX_STYLE = true) + else aurora_locked_int when (STRATIXGX_DPA_RX_STYLE = true) + else stratixii_locked_int when (STRATIXII_RX_STYLE = true) + else stratixiii_locked_int when (STRATIXIII_RX_STYLE = true) or (CYCLONEIII_RX_STYLE = true) + else '1'; + + rxpdat1 <= read_data when ((STRATIXGX_DPA_RX_STYLE = true) and (enable_dpa_fifo = "ON")) + else serdes_data_out; + + write_data <= serdes_data_out; + + pclk <= clkout_tmp; + + stratixii_fastclk <= '0' when (STRATIXII_RX_STYLE = false) or (implement_in_les = "ON") + else rx_inclock when (use_external_pll = "ON") + else rx_pll_sclkout0_dly; + + stratixii_enable <= '0' when (STRATIXII_RX_STYLE = false) or (implement_in_les = "ON") + else rx_enable when (use_external_pll = "ON") + else rx_pll_enable0; + + stratixiii_fastclk <= '0' when (STRATIXIII_RX_STYLE = false) or (implement_in_les = "ON") + else rx_inclock when (use_external_pll = "ON") or (enable_clock_pin_mode = "ON") + else stratixiii_clock(0); + + stratixiii_slowclk <= '0' when (STRATIXIII_RX_STYLE = false) or (implement_in_les = "ON") or (enable_clock_pin_mode = "ON") + else rx_syncclock when (use_external_pll = "ON") + else stratixiii_clock(2); + + stratixiii_enable <= '0' when (STRATIXIII_RX_STYLE = false) or (implement_in_les = "ON") or (enable_clock_pin_mode = "ON") + else rx_enable when (use_external_pll = "ON") + else stratixiii_clock(1); + + rx_data_align_clk <= rx_clock1_int when ((STRATIX_RX_STYLE = true) or + (STRATIXII_RX_STYLE = true) or (STRATIXIII_RX_STYLE = true)) and + (implement_in_les = "OFF") + else '0'; + + rx_data_align_wire <= rx_data_align when (port_rx_data_align = "PORT_USED") + else '0' when (port_rx_data_align = "PORT_UNUSED") + else rx_data_align when (rx_data_align /= 'Z') + else '0'; + + rx_data_align_int <= rx_data_align_reg when (registered_data_align_input = "ON") + else rx_data_align_wire; + + rx_channel_data_align_wire <= rx_channel_data_align when (rx_channel_data_align /= temp_z) + else (others => rx_data_align_int ) when ((STRATIXII_RX_STYLE = true) or + (STRATIXIII_RX_STYLE = true)) + else (others => '0'); + + flvds_fastclk <= '0' when (FAMILY_HAS_FLEXIBLE_LVDS = false) + else rx_inclock when (use_external_pll = "ON") + else cyclone_clock(0) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIX_STYLE_PLL = true)) + else cycloneii_clock(0) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXII_STYLE_PLL = true)) + else stratixiii_clock(0) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXIII_STYLE_PLL = true)) + else '0'; + + flvds_slowclk <= '0' when (FAMILY_HAS_FLEXIBLE_LVDS = false) + else rx_readclock when (use_external_pll = "ON") + else cyclone_clock(2) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIX_STYLE_PLL = true)) + else cycloneii_clock(2) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXII_STYLE_PLL = true)) + else stratixiii_clock(2) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXIII_STYLE_PLL = true)) + else '0'; + + flvds_syncclk <= '0' when (FAMILY_HAS_FLEXIBLE_LVDS = false) + else rx_syncclock when (use_external_pll = "ON") + else cyclone_clock(1) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIX_STYLE_PLL = true)) + else cycloneii_clock(1) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXII_STYLE_PLL = true)) + else stratixiii_clock(1) when ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXIII_STYLE_PLL = true)) + else '0'; + + flvds_rx_data_align <= rx_channel_data_align when ((port_rx_channel_data_align = "PORT_USED") or + ((port_rx_channel_data_align = "PORT_CONNECTIVITY") and + (rx_channel_data_align /= temp_z))) + else (others => rx_data_align_wire ) when (port_rx_data_align /= "PORT_UNUSED") + else (others => '0'); + + flvds_rx_cda_reset <= rx_cda_reset when ((port_rx_channel_data_align = "PORT_USED") or + ((port_rx_channel_data_align = "PORT_CONNECTIVITY") and + (rx_channel_data_align /= temp_z))) + else (others => rx_data_align_reset ) when (port_rx_data_align /= "PORT_UNUSED") + else (others => '0'); + +-- COMPONENT ASSIGNMENTS + + -- instantiation of the PLLs used by LVDS_RX + -- MF_stratix_pll used for Stratix and Stratix GX + -- MF_stratixii_pll used for Stratix II + -- MF_stratixiii_pll used for Stratix III + STRATIX_PLL: + if ((STRATIX_RX_STYLE = true) and (implement_in_les = "OFF") and (deserialization_factor > 2)) generate + + U2: MF_stratix_pll -- STRATIX PLL + generic map ( + inclk0_input_frequency => inclock_period, + inclk1_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk2_multiply_by => INT_CLOCK_BOOST, + clk2_divide_by => deserialization_factor, + clk0_phase_shift => PHASE_INCLOCK, + clk2_phase_shift => PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => rx_inclock, + inclk(1) => rx_inclock, + ena => rx_pll_enable, + areset => pll_areset, + clkena(5 downto 0) => temp_high, + comparator => rx_data_align_int, + clk => yeager_clock, + enable0 => rx_pll_enable0, + enable1 => rx_pll_enable1, + locked => yeager_locked_int ); + + end generate STRATIX_PLL; + + + STRATIXGX_DPA_PLL: + if ((STRATIXGX_DPA_RX_STYLE = true) and (implement_in_les = "OFF") and (deserialization_factor > 2)) generate + + U2: MF_stratix_pll -- Stratix GX PLL + generic map ( + inclk0_input_frequency => inclock_period, + inclk1_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk2_multiply_by => INT_CLOCK_BOOST, + clk2_divide_by => deserialization_factor, + clk0_phase_shift => "0", + clk2_phase_shift => "0", + family_name => intended_device_family ) + port map ( + inclk(0) => rx_inclock, + inclk(1) => temp_zero, + ena => rx_pll_enable, + areset => pll_areset, + clkena(5 downto 0) => temp_high, + clk => aurora_clock, + locked => aurora_locked_int ); + + end generate STRATIXGX_DPA_PLL; + + STRATIXII_PLL: + if ((STRATIXII_RX_STYLE = true) and (implement_in_les = "OFF") and (use_external_pll /= "ON") and + (deserialization_factor > 2)) generate + + U3: MF_stratixii_pll -- Stratix II PLL + generic map ( + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + inclk1_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => deserialization_factor, + clk2_multiply_by => INT_CLOCK_BOOST, + clk2_divide_by => deserialization_factor, + clk0_phase_shift => STXII_PHASE_INCLOCK, + clk2_phase_shift => STXII_PHASE_INCLOCK, + sclkout0_phase_shift => STXII_PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => rx_inclock, + inclk(1) => temp_zero, + ena => rx_pll_enable, + areset => pll_areset, + clk => stratixii_clock, + locked => stratixii_locked_int, + enable0 => rx_pll_enable0, + sclkout(0) => rx_pll_sclkout0, + sclkout(1) => rx_pll_sclkout1 ); + + end generate STRATIXII_PLL; + + STRATIXIII_PLL: + if ((STRATIXIII_RX_STYLE = true) and (implement_in_les = "OFF") and (use_external_pll /= "ON") and + (deserialization_factor > 2)) generate + + U4: MF_stratixiii_pll -- Stratix III PLL + generic map ( + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + inclk1_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => 1, + clk1_multiply_by => INT_CLOCK_BOOST, + clk1_divide_by => deserialization_factor, + clk1_duty_cycle => integer(real(100/deserialization_factor) + real(0.5)), + clk2_multiply_by => INT_CLOCK_BOOST, + clk2_divide_by => deserialization_factor, + clk0_phase_shift => STXII_PHASE_INCLOCK, + clk1_phase_shift => CLK_ENA_PHASE_SHIFT, + clk2_phase_shift => STXII_PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => rx_inclock, + inclk(1) => temp_zero, + areset => pll_areset, + clk => stratixiii_clock, + locked => stratixiii_locked_int ); + + end generate STRATIXIII_PLL; + + FLVDS_STX_PLL: + if ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIX_STYLE_PLL = true) and (deserialization_factor > 2)) generate + + U4: MF_stratix_pll -- Cyclone PLL + generic map ( + pll_type => FLVDS_PLL_TYPE, + inclk0_input_frequency => inclock_period, + inclk1_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => FLVDS_CLK0_DIV, + clk1_multiply_by => FLVDS_CLK1_MULT, + clk1_divide_by => FLVDS_CLK1_DIV, + clk2_multiply_by => FLVDS_CLK2_MULT, + clk2_divide_by => FLVDS_CLK2_DIV, + clk0_phase_shift => PHASE_INCLOCK, + clk1_phase_shift => FLVDS_CLK1_PHASE_SHIFT, + clk2_phase_shift => PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => rx_inclock, + inclk(1) => temp_zero, + ena => rx_pll_enable, + areset => pll_areset, + clkena(5 downto 0) => temp_high, + clk => cyclone_clock, + locked => cyclone_locked_int ); + + end generate FLVDS_STX_PLL; + + FLVDS_STXII_PLL: + if ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXII_STYLE_PLL = true) and (use_external_pll /= "ON") and + (deserialization_factor > 2)) generate + + U5: MF_stratixii_pll -- Stratix II PLL + generic map ( + operation_mode => alpha_tolower(pll_operation_mode), + pll_type => FLVDS_PLL_TYPE, + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + inclk1_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => FLVDS_CLK0_DIV, + clk1_multiply_by => FLVDS_CLK1_MULT, + clk1_divide_by => FLVDS_CLK1_DIV, + clk2_multiply_by => FLVDS_CLK2_MULT, + clk2_divide_by => FLVDS_CLK2_DIV, + clk0_phase_shift => STXII_LE_PHASE_INCLOCK, + clk1_phase_shift => STXII_LE_CLK1_PHASE_SHIFT, + clk2_phase_shift => STXII_LE_PHASE_INCLOCK, + sclkout0_phase_shift => PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => rx_inclock, + inclk(1) => temp_zero, + ena => rx_pll_enable, + areset => pll_areset, + clk => cycloneii_clock, + locked => cycloneii_locked_int, + enable0 => rx_pll_enable0, + sclkout(0) => rx_pll_sclkout0, + sclkout(1) => rx_pll_sclkout1 ); + + end generate FLVDS_STXII_PLL; + + FLVDS_STXIII_PLL: + if ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXIII_STYLE_PLL = true) and (use_external_pll /= "ON") and + (deserialization_factor > 2)) generate + + U5: MF_stratixiii_pll -- Stratix III PLL + generic map ( + operation_mode => alpha_tolower(pll_operation_mode), + pll_type => FLVDS_PLL_TYPE, + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + inclk1_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => FLVDS_CLK0_DIV, + clk1_multiply_by => FLVDS_CLK1_MULT, + clk1_divide_by => FLVDS_CLK1_DIV, + clk2_multiply_by => FLVDS_CLK2_MULT, + clk2_divide_by => FLVDS_CLK2_DIV, + clk0_phase_shift => STXIII_LE_PHASE_INCLOCK, + clk1_phase_shift => STXIII_LE_CLK1_PHASE_SHIFT, + clk2_phase_shift => STXIII_LE_PHASE_INCLOCK, + family_name => intended_device_family, + self_reset_on_loss_lock => alpha_tolower(pll_self_reset_on_loss_lock) ) + port map ( + inclk(0) => rx_inclock, + inclk(1) => temp_zero, + areset => pll_areset, + clk => stratixiii_clock, + locked => stratixiii_locked_int ); + + end generate FLVDS_STXIII_PLL; + + STRATIXII_LVDS_RECEIVER: + if ((STRATIXII_RX_STYLE = true) and (implement_in_les = "OFF") and (deserialization_factor > 2)) generate + + U6: stratixii_lvds_rx + generic map ( + number_of_channels => number_of_channels, + deserialization_factor => deserialization_factor, + enable_dpa_mode => enable_dpa_mode, + data_align_rollover => data_align_rollover, + lose_lock_on_one_change => lose_lock_on_one_change, + reset_fifo_at_first_lock => reset_fifo_at_first_lock, + x_on_bitslip => x_on_bitslip ) + port map ( + rx_in => rx_in, + rx_fastclk => stratixii_fastclk, + rx_enable => stratixii_enable, + rx_locked => stratixii_locked_int, + rx_reset => rx_reset, + rx_dpll_reset => rx_dpll_reset, + rx_dpll_hold => rx_dpll_hold, + rx_dpll_enable => rx_dpll_enable, + rx_fifo_reset => rx_fifo_reset, + rx_channel_data_align => rx_channel_data_align_wire, + rx_cda_reset => rx_cda_reset, + rx_out => stratixii_dataout, + rx_dpa_locked => stratixii_dpa_locked, + rx_cda_max => stratixii_cda_max ); + end generate STRATIXII_LVDS_RECEIVER; + + FLEXIBLE_LVDS_RECEIVER: + if ((FAMILY_HAS_FLEXIBLE_LVDS = true) and (deserialization_factor > 2)) generate + + U7: flexible_lvds_rx + generic map ( + number_of_channels => number_of_channels, + deserialization_factor => deserialization_factor, + use_extra_ddio_register => IS_USING_EXTRA_DDIO_REG, + use_extra_pll_clk => IS_USING_EXTRA_PLL_CLK, + buffer_implementation => buffer_implementation, + registered_data_align_input => registered_data_align_input, + use_external_pll => use_external_pll, + registered_output => registered_output, + add_latency => IS_ADDING_EXTRA_LATENCY ) + port map ( + rx_in => rx_in, + rx_fastclk => flvds_fastclk, + rx_slowclk => flvds_slowclk, + rx_syncclk => flvds_syncclk, + pll_areset => pll_areset, + rx_data_reset => rx_data_reset, + rx_data_align => flvds_rx_data_align, + rx_cda_reset => flvds_rx_cda_reset, + rx_locked => rx_locked_int, + rx_out => flvds_dataout ); + end generate FLEXIBLE_LVDS_RECEIVER; + + STRATIXIII_LVDS_RECEIVER: + if ((STRATIXIII_RX_STYLE = true) and (implement_in_les = "OFF") and (deserialization_factor > 2)) generate + + U8: stratixiii_lvds_rx + generic map ( + number_of_channels => number_of_channels, + deserialization_factor => deserialization_factor, + enable_dpa_mode => enable_dpa_mode, + data_align_rollover => data_align_rollover, + lose_lock_on_one_change => lose_lock_on_one_change, + reset_fifo_at_first_lock => reset_fifo_at_first_lock, + x_on_bitslip => x_on_bitslip, + rx_align_data_reg => rx_align_data_reg, + enable_soft_cdr_mode => enable_soft_cdr_mode, + sim_dpa_output_clock_phase_shift => sim_dpa_output_clock_phase_shift, + sim_dpa_is_negative_ppm_drift => sim_dpa_is_negative_ppm_drift, + sim_dpa_net_ppm_variation => sim_dpa_net_ppm_variation, + enable_dpa_align_to_rising_edge_only => enable_dpa_align_to_rising_edge_only, + enable_dpa_initial_phase_selection => enable_dpa_initial_phase_selection, + dpa_initial_phase_value => dpa_initial_phase_value, + registered_output => registered_output, + enable_clock_pin_mode => enable_clock_pin_mode, + use_dpa_calibration => use_dpa_calibration, + ARRIAII_RX_STYLE => ARRIAII_RX_STYLE, + STRATIXV_RX_STYLE => STRATIXV_RX_STYLE ) + port map ( + rx_in => rx_in, + rx_fastclk => stratixiii_fastclk, + rx_slowclk => stratixiii_slowclk, + rx_enable => stratixiii_enable, + rx_dpaclock => rx_dpaclock, + rx_reset => rx_reset, + rx_dpll_reset => rx_dpll_reset, + rx_dpll_hold => rx_dpll_hold, + rx_dpll_enable => rx_dpll_enable, + rx_fifo_reset => rx_fifo_reset, + rx_channel_data_align => rx_channel_data_align_wire, + rx_cda_reset => rx_cda_reset, + rx_out => stratixiii_dataout, + rx_dpa_locked => stratixiii_dpa_locked, + rx_cda_max => stratixiii_cda_max, + rx_divfwdclk => stratixiii_divfwdclk ); + end generate STRATIXIII_LVDS_RECEIVER; + + +-- PROCESS DECLARATION + + STRATIXII_FCLK : process (rx_pll_sclkout0) + begin + rx_pll_sclkout0_dly <= rx_pll_sclkout0; + end process; -- STRATIXII_FCLK process + + -- basic error checking for invalid deserialization factors + MSG: process(rx_channel_data_align, rx_data_align) + variable all_z : std_logic_vector(number_of_channels-1 downto 0) + := (others =>'Z'); + variable init : boolean := true; + begin + if (init = true) then + if (IS_VALID_FAMILY(intended_device_family) = false) then + ASSERT FALSE + REPORT intended_device_family & " is not a valid device family!" + SEVERITY ERROR; + elsif ((STRATIX_RX_STYLE = true) and + (deserialization_factor /= 1) and + (deserialization_factor /= 2) and + ((deserialization_factor > 10) or + (deserialization_factor < 4))) then + ASSERT FALSE + REPORT "Stratix and Stratix GX (non DPA mode) does not support the specified deserialization factor!" + SEVERITY ERROR; + elsif ((STRATIXGX_DPA_RX_STYLE = true) and + (enable_dpa_mode = "ON") and + (deserialization_factor /= 8) and + (deserialization_factor /= 10)) then + ASSERT FALSE + REPORT "STRATIXGX in DPA mode does not support the specified deserialization factor!" + SEVERITY ERROR; + elsif ((STRATIXII_RX_STYLE = true) and + (deserialization_factor > 10)) then + ASSERT FALSE + REPORT "STRATIXII does not support the specified deserialization factor!" + SEVERITY ERROR; + elsif ((STRATIXII_RX_STYLE = true) and + (data_align_rollover > 11)) then + ASSERT FALSE + REPORT "Stratix II does not support data align rollover values > 11 !" + SEVERITY ERROR; + elsif (CYCLONE_RX_STYLE = true) then + if ((use_external_pll = "OFF") and ((deserialization_factor > 10) or (deserialization_factor = 3))) then + ASSERT FALSE + REPORT "Cyclone does not support the specified deserialization factor when use_external_pll is 'OFF'!" + SEVERITY ERROR; + end if; + elsif (CYCLONEII_RX_STYLE = true) then + if ((use_external_pll = "OFF") and ((deserialization_factor > 10) or (deserialization_factor = 3))) then + ASSERT FALSE + REPORT "Cyclone II does not support the specified deserialization factor when use_external_pll is 'OFF'!" + SEVERITY ERROR; + end if; + end if; + + if (((STRATIXII_RX_STYLE = true) or (STRATIXIII_RX_STYLE = true)) and + (rx_channel_data_align = all_z) and + (rx_data_align /= 'Z')) then + ASSERT FALSE + REPORT "Data alignment on Stratix II/III devices introduces one bit of latency for each assertion of the data alignment signal. In comparison, Stratix and Stratix GX devices remove one bit of latency for each assertion." + SEVERITY Warning; + end if; + init := false; + end if; + + end process; -- MSG process + + X2_MODE : + if (deserialization_factor = 2) generate + + -- For x2 mode, data input is sampled in both the rising edge and falling edge + -- of input clock. + DDIO_IN : process (rx_inclock) + variable datain_latched : std_logic_vector(number_of_channels-1 downto 0) + := (others =>'0'); + begin + if (rx_inclock'event and (rx_inclock = '1')) then + for i in 0 to number_of_channels -1 loop + if (CYCLONEIII_RX_STYLE = true) then + rx_ddio_in((i*2)+1) <= rx_in(i); + rx_ddio_in((i*2)) <= datain_latched(i); + else + rx_ddio_in((i*2)) <= rx_in(i); + rx_ddio_in((i*2)+1) <= datain_latched(i); + end if; + end loop; + -- falling edge of inclock + elsif (rx_inclock'event and (rx_inclock = '0')) then + for i in 0 to number_of_channels -1 loop + datain_latched(i) := rx_in(i); + end loop; + end if; + end process; -- DDIO_IN process + end generate X2_MODE; + + -- Register the load enable signal for Stratix + LOAD_ENABLE_PROC: process (rx_clock0_int) + begin + if (rx_clock0_int'event and (rx_clock0_int ='1') and (rx_clock0_int'last_value ='0')) then + enable0_pipe <= enable0_reg; + enable0_reg <= rx_pll_enable0; + enable1_reg <= rx_pll_enable1; + elsif (rx_clock0_int'event and (rx_clock0_int = '0') and (rx_clock0_int'last_value ='1')) then + enable0_neg <= enable0_pipe; + elsif (rx_clock0_int'event and (rx_clock0_int = 'X')) then + enable0_pipe <= 'X'; + enable0_reg <= 'X'; + enable1_reg <= 'X'; + enable0_neg <= 'X'; + end if; + + end process; -- LOAD_ENABLE_PROC process + + -- the deserializer + LOAD_DATA: process(rx_clock0_int, rx_clock1_int) + variable count : CHANNEL_CNT := (others => 0); + variable sample : integer; + variable start_data : integer := 0; + variable data_int : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + variable x : integer:=0; + begin + + if (rx_clock0_int'event and (rx_clock0_int = '0')) then + -- For Stratix and Stratix GX non-DPA mode, load data + -- when the registered load enable signal is high + if ((enable0_neg = '1') and + (STRATIX_RX_STYLE = true)) then + data_out <= data_int; + end if; + + -- Deserialize the incoming bits + for i in 0 to number_of_channels -1 loop + if (STRATIX_RX_STYLE = true) then + for x in deserialization_factor-1 downto 1 loop + -- Data gets shifted into MSB first. + data_int(x + (i * deserialization_factor)) := data_int (x-1 + (i * deserialization_factor)); + end loop; + data_int(i * deserialization_factor) := rx_in(i); + end if; + end loop; + end if; + end process; -- LOAD_DATA process + + -- the parallel and hold registers + PARALLEL_REG: process(rx_clock1_int, enable1_reg, stratixiii_divfwdclk) + begin + if (stratixiii_divfwdclk'event and (stratixiii_divfwdclk(0) = '1')) then + if (enable_soft_cdr_mode = "ON") then + rx_out_rgd <= rx_out_int; + end if; + end if; + + if(rx_clock1_int'event and (rx_clock1_int = '1')) then + if (enable_soft_cdr_mode = "OFF") then + rx_out_rgd <= rx_out_int; + end if; + end if; + + if (enable1_reg'event and (enable1_reg = '1')) then + rx_out_extra_yeager_reg <= data_out; + end if; + end process; -- PARALLEL_REG process + + DATA_ALIGN_REG: process(rx_data_align_clk) + begin + if (rx_data_align_clk'event and (rx_data_align_clk = '1')) then + rx_data_align_reg <= rx_data_align_wire; + end if; + end process; --DATA_ALIGN_REG + + + -- Stratix GX DPA internal model + + STRATIXGX_DPA_RX : + if (STRATIXGX_DPA_RX_STYLE = true) generate + + -- the synchronization register + SYNC_REGISTER: process(rx_coreclk) + begin + if (use_coreclock_input = "ON") then + for i in 0 to number_of_channels -1 loop + if ((rx_coreclk_pre(i) = '0') and (rx_coreclk(i) = '1')) then + rx_out_rgd2(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rx_out_int(deserialization_factor*(i+1) -1 downto deserialization_factor*i); + end if; + rx_coreclk_pre(i) <= rx_coreclk(i); + end loop; + end if; + end process; --SYNC_REGISTER process + + -- deserializer logic + DPA_SERDES: process(rx_clock0_int, rx_clock1_int, rx_coreclk, rx_reset, rx_dpll_reset) + variable negedge_count: CHANNEL_CNT := (others => 0); + variable posedge_count: CHANNEL_CNT := (others => 0); + variable fast_clk_count : CHANNEL_CNT := (others => deserialization_factor); + variable data_int : std_logic_vector(REGISTER_WIDTH -1 downto 0) := (others => '0'); + variable rx_in_pipe : std_logic_vector(number_of_channels -1 downto 0) := (others => '0'); + begin + + -- count the fast clock edge after the rising edge of the global slow + -- clock in order to generate the parallel unload enable signal + for i in 0 to number_of_channels -1 loop + if (((use_coreclock_input = "ON") and (rx_coreclk_pre(i) = '0') and (rx_coreclk(i) = '1')) or + ((use_coreclock_input = "OFF") and rx_clock1_int'event and (rx_clock1_int = '1'))) then + negedge_count(i) := 0; + posedge_count(i) := 0; + + if ((rx_reset(i) = '1') or (rx_dpll_reset(i) = '1')) then + sync_reset(i) <= '1'; + else + sync_reset(i) <= '0'; + end if; + end if; + rx_coreclk_pre(i) <= rx_coreclk(i); + end loop; + + if (rx_clock0_int'event and (rx_clock0_int = '1')) then + for i in 0 to number_of_channels -1 loop + posedge_count(i) := posedge_count(i) + 1; + + -- load the parallel data when parallel unload enable signal goes high + if (negedge_count(i) = 2) then + serdes_data_out <= data_int; + end if; + + if (sync_reset(i) = '1') then + fast_clk_count(i) := deserialization_factor; + clkout_tmp(i) <= '0'; + else + if (fast_clk_count(i) = deserialization_factor) then + fast_clk_count(i) := 0; + clkout_tmp(i) <= not clkout_tmp(i); + elsif (fast_clk_count(i) = (deserialization_factor+1)/2) then + clkout_tmp(i) <= not clkout_tmp(i); + end if; + fast_clk_count(i) := fast_clk_count(i) + 1; + end if; + end loop; + end if; + + + -- deserialize the incoming bits + if (rx_clock0_int'event and (rx_clock0_int = '0')) then + for i in 0 to number_of_channels -1 loop + for x in deserialization_factor-1 downto 1 loop + -- Data gets shifted into MSB first. + data_int(x + (i * deserialization_factor)) := data_int (x-1 + (i * deserialization_factor)); + end loop; + + data_int(i * deserialization_factor) := rx_in_pipe(i); + rx_in_pipe(i) := rx_in(i); + + if (((use_coreclock_input = "ON") and (posedge_count(i) > 0)) or (use_coreclock_input = "OFF")) then + negedge_count(i) := negedge_count(i) + 1; + end if; + end loop; + end if; + end process; -- DPA_SERDES process + + -- phase compensation FIFO + DPA_FIFO: process(pclk, rx_clock1_int, rx_coreclk) + variable rd_index : CHANNEL_CNT := (others => 2); + variable wr_index : CHANNEL_CNT := (others => 0); + variable enable_fifo : boolean := false; + variable clk0_posedge_count : integer := 0; + begin + -- enable the FIFO only when PLL locks + if (rx_locked_int = '1') then + enable_fifo := true; + end if; + + if (enable_fifo = true) then + -- Update write pointer and write data into the FIFO + for i in 0 to number_of_channels-1 loop + if ((pclk(i) = '1') and (pclk_pre(i) = '0')) then + if (sync_reset(i) = '1') then + wr_index(i) := 0; + else + ram_array(wr_index(i)) <= write_data; + wr_index(i) := (wr_index(i) + 1) rem 4; + end if; + end if; + pclk_pre(i) <= pclk(i); + end loop; + + -- Read data from the FIFO and update read pointer + for i in 0 to number_of_channels-1 loop + if (((use_coreclock_input = "ON") and (rx_coreclk_pre(i) = '0') and (rx_coreclk(i) = '1')) or + ((use_coreclock_input = "OFF") and (rx_clock1_int'event) and (rx_clock1_int = '1'))) then + + -- reset logic + if ((rx_reset(i) = '1') or (rx_dpll_reset(i) = '1') or (sync_reset(i) = '1')) then + read_data(deserialization_factor*(i+1) -1 downto deserialization_factor*i) <= (others => '0'); + wr_index(i) := 0; + rd_index(i) := 2; + for j in 0 to 3 loop + ram_array(j)(deserialization_factor*(i+1) -1 downto deserialization_factor*i) <= (others => '0'); + end loop; + else + -- read data and update read pointer + read_data(deserialization_factor*(i+1) -1 downto deserialization_factor*i) <= ram_array(rd_index(i))(deserialization_factor*(i+1) -1 downto deserialization_factor*i); + rd_index(i) := (rd_index(i) + 1) rem 4; + end if; + end if; + + rx_coreclk_pre(i) <= rx_coreclk(i); + + end loop; + end if; + + end process; -- DPA_FIFO process + + + -- bit-slipping logic + DPA_BIT_SLIP: process(rx_coreclk, rx_clock1_int, rx_channel_data_align) + variable count: CHANNEL_CNT := (others => 0); + variable count2: CHANNEL_CNT := (others => 0); + variable count3: CHANNEL_CNT := (others => 0); + begin + + for i in 0 to number_of_channels-1 loop + -- increment the number-of-bits-to-slip counter once for each rising edge of the bitslip control signal + if (((use_coreclock_input = "ON") and (rx_coreclk_pre(i) = '0') and (rx_coreclk(i) = '1')) or + ((use_coreclock_input = "OFF") and rx_clock1_int'event and (rx_clock1_int = '1'))) then + count3(i) := count2(i); + count2(i) := count(i); + if ((rx_channel_data_align_pre(i) = '0') and (rx_channel_data_align(i) = '1')) then + count(i) := (count(i) + 1) rem deserialization_factor; + end if; + + rx_channel_data_align_pre(i) <= rx_channel_data_align(i); + + -- reset logic + if ((rx_reset(i) = '1') or (rx_dpll_reset(i) = '1') or (sync_reset(i) = '1')) then + rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*i) <= (others => '0'); + rxpdat3(deserialization_factor*(i+1) -1 downto deserialization_factor*i) <= (others => '0'); + count(i) := 0; + count2(i) := 0; + count3(i) := 0; + rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) <= (others => '0'); + else + -- register the parallel data from either the FIFO or the SERDES + rxpdat2 <= rxpdat1; + rxpdat3 <= rxpdat2; + + -- select which bits to output to core from rxpdat2 and rxpdat3 registers + -- the bitslip counter determines how many bits to skip from rxpdat3, and + -- how many to take from rxpdat2 + -- MSB of the registers is the earliest bit to enter, hence the MSB will + -- be the first bit to be skipped + case count3(i) is + when 0 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -1 downto deserialization_factor*i); + --(RXPDAT3[8:0],RXPDAT2[9] + when 1 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -2 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1); + --(RXPDAT3[7:0],RXPDAT2[9:8] + when 2 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -3 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -2); + --(RXPDAT3[6:0],RXPDAT2[9:7] + when 3 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -4 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -3); + --(RXPDAT3[5:0],RXPDAT2[9:6] + when 4 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -5 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -4); + --(RXPDAT3[4:0],RXPDAT2[9:5] + when 5 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -6 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -5); + --(RXPDAT3[3:0],RXPDAT2[9:4] + when 6 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -7 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -6); + --(RXPDAT3[2:0],RXPDAT2[9:3] + when 7 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -8 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -7); + --(RXPDAT3[1:0],RXPDAT2[9:2] + when 8 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -9 downto deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -8); + --(RXPDAT3[0:0],RXPDAT2[9:1] + when 9 => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*i) + & rxpdat2(deserialization_factor*(i+1) -1 downto deserialization_factor*(i+1) -9); + + when others => rxpdatout(deserialization_factor*(i+1) -1 downto deserialization_factor*i) + <= rxpdat3(deserialization_factor*(i+1) -1 downto deserialization_factor*i); + end case; + end if; + end if; + + rx_coreclk_pre(i) <= rx_coreclk(i); + end loop; + + end process; -- DPA_BIT_SLIP process + end generate STRATIXGX_DPA_RX; + + process (rx_locked_int, pll_areset) + begin + if (pll_areset = '1') then + pll_lock_sync <= '0'; + elsif (rx_locked_int = '1' and rx_locked_int'event) then + pll_lock_sync <= '1'; + end if; + end process; + +end behavior; + +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : stratix_tx_outclk +-- +-- Description : This module is used to generate the tx_outclock for Stratix +-- and stratix GX family. +-- +-- Limitation : Only available to Stratix and Stratix GX family. +-- +-- Results Expected: Output clock. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- ENTITY DECLARATION +entity stratix_tx_outclk is + +-- GENERIC DECLARATION + generic ( + deserialization_factor : natural; -- Required parameter + bypass_serializer : boolean := FALSE; + invert_clock : boolean := FALSE; + use_falling_clock_edge : boolean := FALSE ); + +-- PORT DECLARATION + port ( +--INPUT PORT DECLARATION + tx_in : in std_logic_vector(deserialization_factor-1 downto 0); + tx_fastclk : in std_logic; + tx_enable : in std_logic := '1'; + +-- OUTPUT PORT DECLARATION + tx_out : out std_logic := '0' ); + +end stratix_tx_outclk; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of stratix_tx_outclk is + +-- SIGNAL DECLARATION + + -- constant signals + signal enable1_reg1 : std_logic; + signal enable1_reg2 : std_logic; + signal tx_out_neg : std_logic := '0'; + signal tx_shift_reg : std_logic_vector(deserialization_factor-1 downto 0) + := (others => '0'); + signal tx_parallel_load_reg : std_logic_vector(deserialization_factor-1 downto 0) + := (others => '0'); + +begin + +-- SIGNAL ASSIGNMENTS + tx_out <= tx_fastclk when (bypass_serializer = TRUE) and (invert_clock = FALSE) + else not tx_fastclk when (bypass_serializer = TRUE) and (invert_clock = TRUE) + else tx_out_neg when (use_falling_clock_edge = TRUE) + else tx_shift_reg(deserialization_factor-1); + +-- PROCESS DECLARATION + + -- Register the load enable signal + LOAD_ENABLE : process (tx_fastclk) + variable enable1_reg0 : std_logic; + begin + if (tx_fastclk'event and (tx_fastclk ='1') and (tx_fastclk'last_value ='0')) then + enable1_reg1 <= enable1_reg0; + enable1_reg0 := tx_enable; + elsif (tx_fastclk'event and (tx_fastclk = '0') and (tx_fastclk'last_value ='1')) then + enable1_reg2 <= enable1_reg1; + elsif (tx_fastclk'event and (tx_fastclk = 'X')) then + enable1_reg0 := 'X'; + enable1_reg1 <= 'X'; + enable1_reg2 <= 'X'; + end if; + + end process LOAD_ENABLE; -- LOAD_ENABLE process + + -- the deserializer + FAST_CLOCK : process(tx_fastclk) + begin + if (tx_fastclk'event and (tx_fastclk = '0')) then + -- Shift data from shift register to tx_out on negative edge of + -- fast clock + tx_out_neg <= tx_shift_reg(deserialization_factor-1); + elsif (tx_fastclk'event and (tx_fastclk = '1')) then + if (enable1_reg2 = '1') then + tx_shift_reg <= tx_parallel_load_reg; + else + -- Shift data from shift register to tx_out on positive edge + -- of fast clock + for x in deserialization_factor-1 downto 1 loop + tx_shift_reg(x) <= tx_shift_reg (x-1); + end loop; + end if; + tx_parallel_load_reg <= tx_in; + end if; + end process FAST_CLOCK; + + +end behavior; + +-- END OF ARCHITECTURE + + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : stratixii_tx_outclk +-- +-- Description : This module is used to generate the tx_outclock for StratixII +-- family. +-- +-- Limitation : Only available to Stratix II family. +-- +-- Results Expected: Output clock. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- ENTITY DECLARATION +entity stratixii_tx_outclk is + +-- GENERIC DECLARATION + generic ( + deserialization_factor : natural; -- Required parameter + bypass_serializer : boolean := FALSE; + invert_clock : boolean := FALSE; + use_falling_clock_edge : boolean := FALSE ); + +-- PORT DECLARATION + port ( +--INPUT PORT DECLARATION + tx_in : in std_logic_vector(deserialization_factor-1 downto 0); + tx_fastclk : in std_logic; + tx_enable : in std_logic := '1'; + +-- OUTPUT PORT DECLARATION + tx_out : out std_logic := '0' ); + +end stratixii_tx_outclk; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of stratixii_tx_outclk is + +-- SIGNAL DECLARATION + + -- constant signals + signal tx_out_neg : std_logic := '0'; + signal tx_shift_reg : std_logic_vector(deserialization_factor-1 downto 0) + := (others => '0'); + signal tx_parallel_load_reg : std_logic_vector(deserialization_factor-1 downto 0) + := (others => '0'); + +begin + +-- SIGNAL ASSIGNMENTS + tx_out <= tx_fastclk when (bypass_serializer = TRUE) and (invert_clock = FALSE) + else not tx_fastclk when (bypass_serializer = TRUE) and (invert_clock = TRUE) + else tx_out_neg when (use_falling_clock_edge = TRUE) + else tx_shift_reg(deserialization_factor-1); + +-- PROCESS DECLARATION + + -- the deserializer + FAST_CLOCK : process(tx_fastclk) + variable enable1_reg : std_logic := '0'; + begin + if (tx_fastclk'event and (tx_fastclk = '0')) then + tx_out_neg <= tx_shift_reg(deserialization_factor-1); + elsif (tx_fastclk'event and (tx_fastclk = '1')) then + if (enable1_reg = '1') then + tx_shift_reg <= tx_parallel_load_reg; + else -- Shift data from shift register to tx_out + for x in deserialization_factor-1 downto 1 loop + tx_shift_reg(x) <= tx_shift_reg (x-1); + end loop; + end if; + + -- registering enable1 signal + enable1_reg := tx_enable; + + tx_parallel_load_reg <= tx_in; + end if; + end process FAST_CLOCK; + + +end behavior; + +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : flexible_lvds_tx +-- +-- Description : flexible lvds transmitter +-- +-- Limitation : Only available to Cyclone and Cyclone II families. +-- +-- Results Expected: Serialized output data. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- LIBRARY USED---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- ENTITY DECLARATION +entity flexible_lvds_tx is + +-- GENERIC DECLARATION + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + registered_input : string := "ON"; + use_new_coreclk_ckt : boolean := false; + outclock_multiply_by : natural := 1; + outclock_divide_by : natural := 2; + outclock_duty_cycle : natural := 50; + use_self_generated_outclock : boolean := false ); + +-- PORT DECLARATION + port ( +--INPUT PORT DECLARATION + tx_in : in std_logic_vector(deserialization_factor* + number_of_channels -1 downto 0); + tx_fastclk : in std_logic; + tx_slowclk : in std_logic; + tx_regclk : in std_logic; + tx_data_reset : in std_logic; + pll_areset : in std_logic; + pll_outclock : in std_logic; + tx_locked : in std_logic; + +-- OUTPUT PORT DECLARATION + tx_out : out std_logic_vector(number_of_channels-1 downto 0); + tx_outclock : out std_logic ); + +end flexible_lvds_tx; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of flexible_lvds_tx is + +-- FUNCTION DECLARATION + function get_cntr_modulus(constant i_deserialization_factor : in natural) return natural is + begin + if (i_deserialization_factor rem 2 = 1) then + return i_deserialization_factor; + else + return i_deserialization_factor/2; + end if; + + end get_cntr_modulus; + +-- CONSTANT DECLARATION + constant REGISTER_WIDTH : natural := deserialization_factor * number_of_channels; + constant ZEROS : std_logic_vector(number_of_channels-1 downto 0) := (OTHERS => '0'); + constant LOAD_CNTR_MODULUS : natural := get_cntr_modulus(deserialization_factor); + +-- TYPE DECLARATION + type CHANNEL_CNT is array (number_of_channels-1 downto 0) of integer; + type REG_ARRAY is array (deserialization_factor-1 downto 0) of std_logic_vector(number_of_channels -1 downto 0); + +-- SIGNAL DECLARATION + signal tx_reg : std_logic_vector(REGISTER_WIDTH-1 downto 0) + := (others => '0'); + signal tx_reg2 : std_logic_vector((REGISTER_WIDTH*2)-1 downto 0) + := (others => '0'); + signal tx_shift_reg : std_logic_vector(REGISTER_WIDTH-1 downto 0) + := (others => '0'); + signal tx_shift_reg2 : std_logic_vector((REGISTER_WIDTH*2)-1 downto 0) + := (others => '0'); + signal h_sync_a : std_logic_vector(REGISTER_WIDTH-1 downto 0) + := (others => '0'); + signal sync_b_reg : std_logic_vector((REGISTER_WIDTH*2)-1 downto 0) + := (others => '0'); + signal dataout_h : std_logic_vector(number_of_channels-1 downto 0) + := (others => '0'); + signal dataout_l : std_logic_vector(number_of_channels-1 downto 0) + := (others => '0'); + signal dataout_tmp : std_logic_vector(number_of_channels-1 downto 0) + := (others => '0'); + signal tx_ddio_out : std_logic_vector(number_of_channels-1 downto 0) + := (others => '0'); + + signal tx_in_int : std_logic_vector(REGISTER_WIDTH -1 downto 0) + := (others => '0'); + signal tx_in_int2 : std_logic_vector((REGISTER_WIDTH*2) -1 downto 0) + := (others => '0'); + + signal stage1_a : std_logic_vector((number_of_channels*2)-1 downto 0) + := (others => '0'); + signal stage1_b : std_logic_vector((number_of_channels*2)-1 downto 0) + := (others => '0'); + signal stage2 : std_logic_vector((number_of_channels*2)-1 downto 0) + := (others => '0'); + signal tx_reg_2ary : REG_ARRAY := (others => (others => '0')); + signal tx_slowclk_dly : std_logic; + signal tx_outclock_tmp : std_logic := '0'; + signal start_sm_p2s : boolean := false; + + signal loadcnt : natural := 0; + signal sm_p2s : natural := 0; + + signal outclk_shift_l : std_logic_vector(deserialization_factor-1 downto 0) + := (others => '0'); + signal outclk_shift_h : std_logic_vector(deserialization_factor-1 downto 0) + := (others => '0'); + signal outclock_l : std_logic := '0'; + signal outclock_h : std_logic := '0'; + + signal outclk_load_cntr : natural := 0; + signal sync_dffe : std_logic := '0'; + signal load_enable : std_logic := '0'; + signal load_cntr : natural := 0; + signal h_ff : natural := 0; + signal h_us_ff : natural := 0; + signal l_s_ff : natural := 0; + signal l_ff : natural := 0; + signal l_us_ff : natural := 0; + signal h_s_ff : natural := 0; + +begin + + +-- SIGNAL ASSIGNMENTS + tx_in_int <= tx_in when (registered_input = "OFF") + else tx_reg; + tx_in_int2 <= sync_b_reg when (registered_input = "OFF") + else tx_reg2; + tx_out <= tx_ddio_out; + tx_outclock <= tx_outclock_tmp when (use_self_generated_outclock = true) + else pll_outclock; + + +-- PROCESS DECLARATION + + -- For each data channel, input data are separated into 2 data + -- stream which will be transmitted on different edge of input clock. + DDIO_OUT_RECEIVE : process(tx_fastclk, pll_areset, tx_data_reset) + begin + if (pll_areset = '1' or tx_data_reset = '1') then + dataout_h <= (others => '0'); + dataout_l <= (others => '0'); + dataout_tmp <= (others => '0'); + elsif ((tx_fastclk = '1') and tx_fastclk'event) then + if ((deserialization_factor rem 2) = 0) then + for i in 0 to number_of_channels -1 loop + dataout_h(i) <= tx_shift_reg((i+1)*deserialization_factor-1); + dataout_l(i) <= tx_shift_reg((i+1)*deserialization_factor-2); + dataout_tmp(i) <= tx_shift_reg((i+1)*deserialization_factor-1); + end loop; + else + if (use_new_coreclk_ckt = false) then + for i in 0 to number_of_channels -1 loop + dataout_h(i) <= tx_shift_reg2((i+1)*2*deserialization_factor-1); + dataout_l(i) <= tx_shift_reg2((i+1)*2*deserialization_factor-2); + dataout_tmp(i) <= tx_shift_reg2((i+1)*2*deserialization_factor-1); + end loop; + else + dataout_h <= stage2(number_of_channels*2-1 downto number_of_channels); + dataout_l <= stage2(number_of_channels-1 downto 0); + dataout_tmp <= stage2(number_of_channels*2-1 downto number_of_channels); + end if; + end if; + elsif ((tx_fastclk = '0') and tx_fastclk'event) then + dataout_tmp <= dataout_l; + end if; + end process DDIO_OUT_RECEIVE; + + -- Transmits data on both edges of the input clock. + DDIO_OUT_TRANSMIT : process (dataout_tmp) + begin + tx_ddio_out <= dataout_tmp; + end process DDIO_OUT_TRANSMIT; + + -- Loading input data to shift register + SHIFTREG : process (tx_fastclk, pll_areset, tx_data_reset) + begin + if (pll_areset = '1' or tx_data_reset = '1') then + tx_shift_reg <= (others => '0'); + tx_shift_reg2 <= (others => '0'); + sm_p2s <= 0; + stage1_a <= (others => '0'); + stage1_b <= (others => '0'); + stage2 <= (others => '0'); + tx_reg_2ary <= (others => (others => '0')); + elsif ((tx_fastclk = '1') and tx_fastclk'event) then + -- Implementation for even deserialization factor. + if ((deserialization_factor rem 2) = 0) then + + if(load_enable = '1') then + tx_shift_reg <= tx_in_int; + else + for i in 0 to number_of_channels-1 loop + for x in deserialization_factor-1 downto 2 loop + tx_shift_reg(x + (i * deserialization_factor)) <= + tx_shift_reg (x-2 + (i * deserialization_factor)); + end loop; + end loop; + end if; + else -- Implementation for odd deserialization factor. + if (use_new_coreclk_ckt = false) then + + if(load_enable = '1') then + tx_shift_reg2 <= tx_in_int2; + else + for i in 0 to number_of_channels-1 loop + for x in deserialization_factor*2-1 downto 2 loop + tx_shift_reg2(x + (i * 2 * deserialization_factor)) <= + tx_shift_reg2 (x-2 + (i * 2 * deserialization_factor)); + end loop; + end loop; + end if; + else + -- state machine counter + if (((sm_p2s = 0) and (start_sm_p2s = true)) or (sm_p2s /= 0)) then + sm_p2s <= (sm_p2s + 1) rem deserialization_factor; + end if; + + -- synchronization register + if (((sm_p2s = 0) and (start_sm_p2s = true)) or (sm_p2s = (deserialization_factor/2) + 1)) then + for i in 0 to number_of_channels -1 loop + for x in 0 to deserialization_factor-1 loop + tx_reg_2ary(x)(i) <= tx_in_int(i*deserialization_factor + x); + end loop; + end loop; + end if; + + -- stage 1a register + if ((sm_p2s > 0) and (sm_p2s < deserialization_factor/2 +1)) then + stage1_a <= tx_reg_2ary(deserialization_factor - (2*sm_p2s) + 1) & tx_reg_2ary(deserialization_factor - (2*sm_p2s)); + elsif (sm_p2s = deserialization_factor/2 + 1) then + stage1_a <= tx_reg_2ary(0) & ZEROS; + end if; + + -- stage 1b register + if ((sm_p2s = 0) and (start_sm_p2s = true)) then + stage1_b <= tx_reg_2ary(1) & tx_reg_2ary(0); + elsif ((sm_p2s > (deserialization_factor /2) + 1) and (sm_p2s < deserialization_factor)) then + stage1_b <= tx_reg_2ary((deserialization_factor - sm_p2s)*2 + 1) & tx_reg_2ary((deserialization_factor - sm_p2s)*2); + end if; + + -- stage 2 register + if ((sm_p2s > 1) and (sm_p2s < (deserialization_factor/2) +2)) then + stage2 <= stage1_a; + elsif (((sm_p2s = 0) and (start_sm_p2s = true)) or (sm_p2s = 1) or + ((sm_p2s > (deserialization_factor/2) + 2) and (sm_p2s < deserialization_factor))) then + stage2 <= stage1_b; + elsif (sm_p2s = (deserialization_factor/2) + 2) then + stage2 <= stage1_a((number_of_channels*2)-1 downto number_of_channels) & tx_reg_2ary(deserialization_factor - 1); + end if; + end if; + end if; + end if; + end process SHIFTREG; + + process (tx_fastclk) + begin + if ((tx_fastclk = '1') and tx_fastclk'event) then + tx_slowclk_dly <= tx_slowclk; + end if; + end process; + + process (tx_slowclk, tx_slowclk_dly) + begin + if ((tx_slowclk_dly = '0') and (tx_slowclk = '1')) then + start_sm_p2s <= true; + else + start_sm_p2s <= false; + end if; + end process; + + -- loading data to synchronization register + SYNC_REG : process (tx_slowclk, pll_areset, tx_data_reset) + begin + if (pll_areset = '1' or tx_data_reset = '1') then + h_sync_a <= (others => '0'); + sync_b_reg <= (others => '0'); + elsif ((tx_slowclk = '1') and tx_slowclk'event) then + h_sync_a <= tx_in; + elsif ((tx_slowclk = '0') and tx_slowclk'event) then + for i in 0 to number_of_channels-1 loop + for x in (deserialization_factor-1) downto 0 loop + sync_b_reg(x + (((i * 2) + 1) * deserialization_factor)) <= + h_sync_a(x + (i * deserialization_factor)); + sync_b_reg(x + (i * 2 * deserialization_factor)) <= + tx_in(x + (i * deserialization_factor)); + end loop; + end loop; + end if; + end process SYNC_REG; + + -- loading data to input register + IN_REG : process (tx_regclk, pll_areset, tx_data_reset) + begin + if (pll_areset = '1' or tx_data_reset = '1') then + tx_reg <= (others => '0'); + tx_reg2 <= (others => '0'); + elsif (tx_regclk'event and (tx_regclk = '1')) then + if (((deserialization_factor rem 2) = 0) or (use_new_coreclk_ckt = true)) then + tx_reg <= tx_in; + else + tx_reg2 <= sync_b_reg; + end if; + end if; + end process IN_REG; + + -- generate outclock + process (tx_fastclk, pll_areset, tx_data_reset) + begin + if (pll_areset = '1' or tx_data_reset = '1') then + outclk_load_cntr <= 0; + elsif (tx_fastclk'event and (tx_fastclk = '1')) then + outclk_load_cntr <= (outclk_load_cntr + 1) rem deserialization_factor; + end if; + + end process; + + process (pll_outclock, pll_areset, tx_data_reset) + variable outclk_data_l : std_logic_vector(9 downto 0) + := (others => '0'); + variable outclk_data_h : std_logic_vector(9 downto 0) + := (others => '0'); + variable init : boolean := true; + begin + if (init = true) then + + if ((deserialization_factor rem 2 = 1) or + (((deserialization_factor = 6) or + (deserialization_factor = 10)) and + (outclock_multiply_by = 2) and + (outclock_divide_by = deserialization_factor))) then + if (outclock_multiply_by = 2) then + if (use_new_coreclk_ckt = true) then + case deserialization_factor is + when 5 => outclk_data_l := conv_std_logic_vector(22, 10); + outclk_data_h := conv_std_logic_vector(21, 10); + when 7 => outclk_data_l := conv_std_logic_vector(102, 10); + outclk_data_h := conv_std_logic_vector(108, 10); + when 9 => outclk_data_l := conv_std_logic_vector(206, 10); + outclk_data_h := conv_std_logic_vector(460, 10); + when 6 => outclk_data_l := conv_std_logic_vector(9, 10); + outclk_data_h := conv_std_logic_vector(27, 10); + when 10 => outclk_data_l := conv_std_logic_vector(99, 10); + outclk_data_h := conv_std_logic_vector(231, 10); + when others => + outclk_data_l := (others => '0'); + outclk_data_h := (others => '0'); + end case; + else + case deserialization_factor is + when 5 => outclk_data_l := conv_std_logic_vector(13, 10); + outclk_data_h := conv_std_logic_vector(11, 10); + when 7 => outclk_data_l := conv_std_logic_vector(27, 10); + outclk_data_h := conv_std_logic_vector(51, 10); + when 9 => outclk_data_l := conv_std_logic_vector(115, 10); + outclk_data_h := conv_std_logic_vector(103, 10); + when 6 => outclk_data_l := conv_std_logic_vector(9, 10); + outclk_data_h := conv_std_logic_vector(27, 10); + when 10 => outclk_data_l := conv_std_logic_vector(99, 10); + outclk_data_h := conv_std_logic_vector(231, 10); + when others => + outclk_data_l := (others => '0'); + outclk_data_h := (others => '0'); + end case; + end if; + else + if (outclock_duty_cycle /= 50) then + if (use_new_coreclk_ckt = true) then + case deserialization_factor is + when 5 => outclk_data_l := conv_std_logic_vector(25, 10); + outclk_data_h := conv_std_logic_vector(25, 10); + when 7 => outclk_data_l := conv_std_logic_vector(113, 10); + outclk_data_h := conv_std_logic_vector(113, 10); + when 9 => outclk_data_l := conv_std_logic_vector(124, 10); + outclk_data_h := conv_std_logic_vector(124, 10); + when others => + outclk_data_l := (others => '0'); + outclk_data_h := (others => '0'); + end case; + else + case deserialization_factor is + when 5 => outclk_data_l := conv_std_logic_vector(28, 10); + outclk_data_h := conv_std_logic_vector(25, 10); + when 7 => outclk_data_l := conv_std_logic_vector(120, 10); + outclk_data_h := conv_std_logic_vector(113, 10); + when 9 => outclk_data_l := conv_std_logic_vector(31, 10); + outclk_data_h := conv_std_logic_vector(31, 10); + when others => + outclk_data_l := (others => '0'); + outclk_data_h := (others => '0'); + end case; + end if; + else + if (use_new_coreclk_ckt = true) then + case deserialization_factor is + when 5 => outclk_data_l := conv_std_logic_vector(24, 10); + outclk_data_h := conv_std_logic_vector(25, 10); + when 7 => outclk_data_l := conv_std_logic_vector(112, 10); + outclk_data_h := conv_std_logic_vector(113, 10); + when 9 => outclk_data_l := conv_std_logic_vector(60, 10); + outclk_data_h := conv_std_logic_vector(124, 10); + when 6 => outclk_data_l := conv_std_logic_vector(54, 10); + outclk_data_h := conv_std_logic_vector(36, 10); + when 10 => outclk_data_l := conv_std_logic_vector(924, 10); + outclk_data_h := conv_std_logic_vector(792, 10); + when others => + outclk_data_l := (others => '0'); + outclk_data_h := (others => '0'); + end case; + else + case deserialization_factor is + when 5 => outclk_data_l := conv_std_logic_vector(28, 10); + outclk_data_h := conv_std_logic_vector(24, 10); + when 7 => outclk_data_l := conv_std_logic_vector(120, 10); + outclk_data_h := conv_std_logic_vector(112, 10); + when 9 => outclk_data_l := conv_std_logic_vector(15, 10); + outclk_data_h := conv_std_logic_vector(31, 10); + when 6 => outclk_data_l := conv_std_logic_vector(54, 10); + outclk_data_h := conv_std_logic_vector(36, 10); + when 10 => outclk_data_l := conv_std_logic_vector(924, 10); + outclk_data_h := conv_std_logic_vector(792, 10); + when others => + outclk_data_l := (others => '0'); + outclk_data_h := (others => '0'); + end case; + end if; + end if; + end if; + else + if (deserialization_factor = 4) then + case outclock_divide_by is + when 2 => outclk_data_l := conv_std_logic_vector(5, 10); + when 4 => outclk_data_l := conv_std_logic_vector(12, 10); + when others => outclk_data_l := (others => '0'); + end case; + elsif (deserialization_factor = 6) then + case outclock_divide_by is + when 2 => outclk_data_l := conv_std_logic_vector(42, 10); + when 6 => outclk_data_l := conv_std_logic_vector(56, 10); + when others => outclk_data_l := (others => '0'); + end case; + elsif (deserialization_factor = 8) then + case outclock_divide_by is + when 2 => outclk_data_l := conv_std_logic_vector(170, 10); + when 4 => outclk_data_l := conv_std_logic_vector(51, 10); + when 8 => outclk_data_l := conv_std_logic_vector(240, 10); + when others => outclk_data_l := (others => '0'); + end case; + elsif (deserialization_factor = 10) then + case outclock_divide_by is + when 2 => outclk_data_l := conv_std_logic_vector(682, 10); + when 10 => outclk_data_l := conv_std_logic_vector(992, 10); + when others => outclk_data_l := (others => '0'); + end case; + elsif (deserialization_factor = 5) then + if (outclock_divide_by = 5) then + outclk_data_l := conv_std_logic_vector(19, 10); + else + outclk_data_l := (others => '0'); + end if; + elsif (deserialization_factor = 7) then + if (outclock_divide_by = 7) then + outclk_data_l := conv_std_logic_vector(120, 10); + else + outclk_data_l := (others => '0'); + end if; + elsif (deserialization_factor = 9) then + if (outclock_divide_by = 9) then + outclk_data_l := conv_std_logic_vector(391, 10); + else + outclk_data_l := (others => '0'); + end if; + end if; + + outclk_data_h := outclk_data_l; + end if; + init := false; + end if; + + if (pll_areset = '1' or tx_data_reset = '1') then + outclk_shift_l <= (others => '0'); + outclk_shift_h <= (others => '0'); + elsif (pll_outclock'event and (pll_outclock = '1')) then + if (outclk_load_cntr = 0) then + outclk_shift_l <= outclk_data_l(deserialization_factor-1 downto 0); + outclk_shift_h <= outclk_data_h(deserialization_factor-1 downto 0); + else + outclk_shift_l <= ('0' & outclk_shift_l(deserialization_factor-1 downto 1)); + outclk_shift_h <= ('0' & outclk_shift_h(deserialization_factor-1 downto 1)); + end if; + end if; + end process; + + process (pll_outclock, pll_areset, tx_data_reset) + begin + if (pll_areset = '1' or tx_data_reset = '1') then + outclock_h <= '0'; + outclock_l <= '0'; + tx_outclock_tmp <= '0'; + elsif (pll_outclock'event and (pll_outclock = '1')) then + if (outclock_divide_by = 1) then + outclock_h <= '1'; + outclock_l <= '0'; + tx_outclock_tmp <= '1'; + else + outclock_h <= outclk_shift_h(0); + outclock_l <= outclk_shift_l(0); + tx_outclock_tmp <= outclk_shift_h(0); + end if; + elsif (pll_outclock'event and (pll_outclock = '0')) then + tx_outclock_tmp <= outclock_l; + end if; + end process; + + -- new synchronization circuit to generate the load enable pulse + process (tx_slowclk) + begin + if (tx_slowclk'event and (tx_slowclk = '1')) then + sync_dffe <= not sync_dffe; + end if; + end process; + + process (tx_fastclk, pll_areset, tx_data_reset) + begin + if (pll_areset = '1' or tx_data_reset = '1') then + load_cntr <= 0; + elsif (tx_fastclk'event and (tx_fastclk = '1')) then + if (sync_dffe ='1') then + load_cntr <= (load_cntr +1) rem LOAD_CNTR_MODULUS; + else + load_cntr <= (LOAD_CNTR_MODULUS + load_cntr - 1) rem LOAD_CNTR_MODULUS; + end if; + end if; + end process; + + process (tx_fastclk) + begin + if (tx_fastclk'event and (tx_fastclk = '1')) then + if (sync_dffe = '1') then + h_ff <= load_cntr; + h_us_ff <= h_ff; + l_s_ff <= l_us_ff; + else + l_ff <= load_cntr; + l_us_ff <= l_ff; + h_s_ff <= h_us_ff; + end if; + + if (((h_ff = h_s_ff) and (sync_dffe = '1')) or ((l_ff = l_s_ff) and (sync_dffe /= '1'))) then + load_enable <= '1'; + else + load_enable <= '0'; + end if; + end if; + end process; + +end behavior; -- flexible_lvds_tx + +-- END OF ARCHITECTURE + + +-- START ENTITY HEADER --------------------------------------------------------- +-- +-- Entity Name : altlvds_tx +-- +-- Description : Low Voltage Differential Signaling (LVDS) transmitter +-- megafunction. The altlvds_tx megafunction implements a +-- serialization transmitter. LVDS is a high speed IO interface +-- that uses inputs without a reference voltage. LVDS uses two +-- wires carrying differential values to create a single +-- channel. These wires are connected to two pins on supported +-- device to create a single LVDS channel. +-- +-- Limitations : Only available for Stratix, +-- Stratix GX, Stratix II, Cyclone and Cyclone II families. +-- +--Results expected : output clock, serialized output data and pll locked signal. + +-- END ENTITY HEADER ----------------------------------------------------------- + + +-- LIBRARY USED----------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.MF_stratix_pll; +use work.MF_stratixii_pll; +use work.MF_stratixiii_pll; +use work.stratix_tx_outclk; +use work.stratixii_tx_outclk; +use work.flexible_lvds_tx; +use work.stratixv_local_clk_divider; + +-- ENTITY DECLARATION +entity altlvds_tx is + generic ( + -- Specifies the number of LVDS channels (required) + number_of_channels : natural; + + -- Specifies the number of bits per channel (required) + deserialization_factor : natural := 4; + + -- Indicates whether the tx_in[] and tx_outclock ports should be + -- registered. Choices for STRATIX are ON, OFF, TX_CLKIN or TX_CORECLK + registered_input : string := "ON"; + + -- "ON" means that sync_inclock is also used + -- (not used for Stratix and Stratix GX.) + multi_clock : string := "OFF"; + + -- Specifies the period of the input clock in ps (Required) + inclock_period : natural := 10000; + + -- Specifies the period of the tx_outclock port as + -- [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY] + outclock_divide_by : positive := 1; + + -- The effective clock period used to sample output data + inclock_boost : natural := 0; + + -- Aligns the Most Significant Bit(MSB) to the falling edge of the + -- clock instead of the rising edge + center_align_msb : string := "OFF"; + + -- Specifies the device family to be used + intended_device_family : string := "Stratix"; + + -- Specifies the data rate out of the PLL. + -- (required and only for Stratix and Stratix GX devices) + output_data_rate : natural := 0; + + -- Specifies the alignment of the input data with respect to the + -- tx_inclock port. (required and only available for Stratix and + -- Stratix GX devices) + inclock_data_alignment : string := "EDGE_ALIGNED"; + + -- Specifies the alignment of the output data with respect to the + -- tx_outclock port. (required and only available for Stratix and + -- Stratix GX devices) + outclock_alignment : string := "EDGE_ALIGNED"; + + -- Specifies whether the compiler uses the same PLL for both the LVDS + -- receiver and the LVDS transmitter + common_rx_tx_pll : string := "ON"; + + outclock_resource : string := "AUTO"; + + use_external_pll : string := "OFF"; + implement_in_les : STRING := "OFF"; + preemphasis_setting : natural := 0; + vod_setting : natural := 0; + differential_drive : natural := 0; + outclock_multiply_by : natural := 1; + coreclock_divide_by : natural := 2; + outclock_duty_cycle : natural := 50; + inclock_phase_shift : integer := 0; + outclock_phase_shift : integer := 0; + use_no_phase_shift : string := "ON"; + pll_self_reset_on_loss_lock : string := "OFF"; + refclk_frequency : string := "UNUSED"; + enable_clock_pin_mode : string := "UNUSED"; + data_rate : string := "UNUSED"; + lpm_type : string := "altlvds_tx"; + lpm_hint : string := "UNUSED"; + pll_compensation_mode : string := "AUTO"; + + -- Specifies whether the source of the input clock is from the PLL + clk_src_is_pll : string := "off" ); + +-- PORT DECLARATION + port ( + +-- INPUT PORT DECLARATION + -- Input data (required) + tx_in : in std_logic_vector(deserialization_factor* + number_of_channels -1 downto 0); + + -- Input clock (required) + tx_inclock : in std_logic := '0'; + + tx_syncclock : in std_logic := '0'; + + tx_enable : in std_logic := '1'; + + -- Optional clock for input registers (Required if "multi_clock" + -- parameters is turned on) + sync_inclock : in std_logic := '0'; + + -- Enable control for the LVDS PLL + tx_pll_enable : in std_logic := '1'; + + -- Asynchronously resets all counters to initial values (only for + --Stratix and Stratix GX devices) + pll_areset : in std_logic := '0'; + + tx_data_reset : in std_logic := '0'; + + +-- OUTPUT PORT DECLARATION + -- Serialized data signal(required) + tx_out : out std_logic_vector(number_of_channels-1 downto 0) + := (others => '0'); + + -- External reference clock + tx_outclock : out std_logic; + + -- Output clock used to feed non-peripheral logic. + -- Only available for Stratix, and Stratix GX devices only. + tx_coreclock : out std_logic; + + -- Gives the status of the LVDS PLL + -- (when the PLL is locked, this signal is VCC. GND otherwise) + tx_locked : out std_logic ); + +end altlvds_tx; +-- END OF ENTITY + + +-- BEGINNING OF ARCHITECTURE + +-- ARCHITECTURE DECLARATION +architecture behavior of altlvds_tx is + +-- CONSTANT DECLARATION + constant STRATIX_TX_STYLE : boolean := FEATURE_FAMILY_BASE_STRATIX(intended_device_family); + constant STRATIXII_TX_STYLE : boolean := FEATURE_FAMILY_BASE_STRATIXII(intended_device_family); + constant STRATIXIII_TX_STYLE : boolean := FEATURE_FAMILY_BASE_STRATIXIII(intended_device_family); + constant CYCLONE_TX_STYLE : boolean := FEATURE_FAMILY_BASE_CYCLONE(intended_device_family); + constant CYCLONEII_TX_STYLE : boolean := FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family); + constant CYCLONEIII_TX_STYLE : boolean := FEATURE_FAMILY_BASE_CYCLONEIII(intended_device_family); + constant MAXV_TX_STYLE : boolean := FEATURE_FAMILY_MAXV(intended_device_family); + constant FAMILY_HAS_FLEXIBLE_LVDS : boolean := FEATURE_FAMILY_HAS_FLEXIBLE_LVDS(intended_device_family) or + (((STRATIX_TX_STYLE = true) or (STRATIXII_TX_STYLE = true) or + (STRATIXIII_TX_STYLE = true)) and + (implement_in_les = "ON")); + constant FAMILY_HAS_STRATIX_STYLE_PLL : boolean := FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL(intended_device_family); + constant FAMILY_HAS_STRATIXII_STYLE_PLL : boolean := FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL(intended_device_family); + constant FAMILY_HAS_STRATIXIII_STYLE_PLL : boolean := FEATURE_FAMILY_USES_STRATIXIII_PLL(intended_device_family); + constant USE_NEW_CORECLK_CKT : boolean := ((deserialization_factor rem 2) = 1) and (coreclock_divide_by = 1); + constant USE_SELF_GENERATED_OUTCLOCK : boolean := not FEATURE_FAMILY_BASE_CYCLONE(intended_device_family); + +-- FUNCTION DECLARATION + + -- converts uppercase parameter values (e.g. "AUTO") to lowercase ("auto") + -- as expected by stratix_pll model + function alpha_tolower (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 20) := " "; + + begin + for i in 1 to string_length loop + case given_string(i) is + when 'A' => result_string(i) := 'a'; + when 'B' => result_string(i) := 'b'; + when 'C' => result_string(i) := 'c'; + when 'D' => result_string(i) := 'd'; + when 'E' => result_string(i) := 'e'; + when 'F' => result_string(i) := 'f'; + when 'G' => result_string(i) := 'g'; + when 'H' => result_string(i) := 'h'; + when 'I' => result_string(i) := 'i'; + when 'J' => result_string(i) := 'j'; + when 'K' => result_string(i) := 'k'; + when 'L' => result_string(i) := 'l'; + when 'M' => result_string(i) := 'm'; + when 'N' => result_string(i) := 'n'; + when 'O' => result_string(i) := 'o'; + when 'P' => result_string(i) := 'p'; + when 'Q' => result_string(i) := 'q'; + when 'R' => result_string(i) := 'r'; + when 'S' => result_string(i) := 's'; + when 'T' => result_string(i) := 't'; + when 'U' => result_string(i) := 'u'; + when 'V' => result_string(i) := 'v'; + when 'W' => result_string(i) := 'w'; + when 'X' => result_string(i) := 'x'; + when 'Y' => result_string(i) := 'y'; + when 'Z' => result_string(i) := 'z'; + when others => result_string(i) := given_string(i); + end case; + end loop; + + return (result_string(1 to string_length)); + end; + + -- M value for stratix/stratix II/Cyclone/Cyclone II PLL + function pll_m_value(constant i_output_data_rate, + i_inclock_period : in natural) return natural is + variable i_pll_m_value : natural; + begin + i_pll_m_value := (((i_output_data_rate * i_inclock_period) + + (5* 100000)) / 1000000); + + return i_pll_m_value; + + end pll_m_value; + + -- D value for Stratix/Stratix II/Cyclone/Cyclone II PLL + function pll_d_value(constant i_output_data_rate, + i_inclock_period : in natural) return natural is + variable i_pll_d_value : natural; + begin + if ((i_output_data_rate /= 0) and (i_inclock_period /= 0)) then + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + i_pll_d_value := 2; + else + i_pll_d_value := 1; + end if; + else + i_pll_d_value := 1; + end if; + + return i_pll_d_value; + end pll_d_value; + + -- clock_boost_calc calculates the multiply_by factor for the PLL clocks + -- used by LVDS_TX + function clock_boost_calc (constant i_output_data_rate, + i_inclock_period, + i_deserialization_factor, + i_inclock_boost : in natural) return natural is + variable i_input_clock_boost: natural := 1; + + begin + if ((i_output_data_rate /= 0) and (i_inclock_period /= 0)) then + i_input_clock_boost := pll_m_value (i_output_data_rate, + i_inclock_period); + else + if (inclock_boost = 0) then + i_input_clock_boost := i_deserialization_factor; + else + i_input_clock_boost := i_inclock_boost; + end if; + end if; + + return i_input_clock_boost; + + end clock_boost_calc; + + + -- int_to_str converts an integer to a string. This is mainly used for + -- converting the calculated phase shift to a string as required by altpll + function int_to_str(constant value : integer ) return string is + variable ivalue : integer := 0; + variable index : integer := 0; + variable strlen : integer := 0; + variable digit : integer := 0; + variable str : string(1 to 8) := "00000000"; + begin + + ivalue := abs(value); + strlen := 0; + + while (ivalue > 0) loop + ivalue := ivalue/10; + strlen := strlen + 1; + end loop; + + if (strlen = 0) then + strlen := 1; + end if; + + ivalue := abs(value); + index := strlen; + + while (ivalue > 0) loop + digit := ivalue mod 10; + ivalue := ivalue / 10; + + case digit is + when 0 => str(index) := '0'; + when 1 => str(index) := '1'; + when 2 => str(index) := '2'; + when 3 => str(index) := '3'; + when 4 => str(index) := '4'; + when 5 => str(index) := '5'; + when 6 => str(index) := '6'; + when 7 => str(index) := '7'; + when 8 => str(index) := '8'; + when 9 => str(index) := '9'; + when others => ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + + index := index - 1; + end loop; + + if (value < 0) then + return ('-'& str(1 to strlen)); + else + return str(1 to strlen); + end if; + end int_to_str; + + -- get_phase_delay calculates the phase shift for each PLL clock as + -- determined by the INCLOCK_DATA_ALIGNMENT parameter + function get_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + variable x : integer := 0; + variable int_delay : integer := 0; + begin + + if (i_phase_delay = "UNUSED") then + int_delay := inclock_phase_shift; + else + -- returns the delay in ps + -- ( * inclock period / 360 degress) + if (i_phase_delay = "EDGE_ALIGNED") then + my_phase := 0; + -- CENTER_ALIGNED means 180 degrees + elsif (i_phase_delay = "CENTER_ALIGNED") then + my_phase := (180 * inclock_period) / 360; + elsif (i_phase_delay = "45_DEGREES") then + my_phase := (45 * inclock_period) / 360; + elsif (i_phase_delay = "90_DEGREES") then + my_phase := (90 * inclock_period) / 360; + elsif (i_phase_delay = "135_DEGREES") then + my_phase := (135 * inclock_period) / 360; + elsif (i_phase_delay = "180_DEGREES") then + my_phase := (180 * inclock_period) / 360; + elsif (i_phase_delay = "225_DEGREES") then + my_phase := (225 * inclock_period) / 360; + elsif (i_phase_delay = "270_DEGREES") then + my_phase := (270 * inclock_period) / 360; + elsif (i_phase_delay = "315_DEGREES") then + my_phase := (315 * inclock_period) / 360; + else + ASSERT FALSE + REPORT "Invalid clock data alignment. Using 'EDGE_ALIGNED' instead" + SEVERITY WARNING; + my_phase := 0; + end if; + + -- add 1 to "round up" the calculation result + my_phase := my_phase + 1; + + -- phase shift = ( * inclock_period / 360 ) / (fast + -- clock multiply_by factor) + -- in other words, the data alignment phase shift is a percentage of the + -- fast clock period + int_delay := my_phase / clock_boost_calc(output_data_rate, inclock_period, + deserialization_factor, inclock_boost); + + -- add 1 to "round up" the calculation result + int_delay := int_delay + 1; + end if; + + return (int_delay); + + end get_phase_delay; + + -- get_stxii_inclock_phase_delay returns the adjusted input clock phase shift for Stratix II pll. + function get_stxii_inclock_phase_delay (constant i_phase_delay : in string) + return integer is + variable my_phase : integer := 0; + begin + + my_phase := get_phase_delay(i_phase_delay) - (inclock_period / (2 * clock_boost_calc (output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + + return (my_phase); + + end get_stxii_inclock_phase_delay; + + -- get_outclock_phase_delay calculates the phase shift for the outclock port + -- as determined by the OUTCLOCK_ALIGNMENT parameter + function get_outclock_phase_delay (constant i_phase_delay : in string) + return integer is + variable my_phase : integer := 0; + variable x : integer := 0; + variable int_delay : integer := 0; + begin + + if (i_phase_delay = "UNUSED") then + my_phase := outclock_phase_shift; + else + -- returns the delay in ps + -- ( * inclock period / 360 degress ) + if (i_phase_delay = "EDGE_ALIGNED") then + my_phase := 0; + -- CENTER_ALIGNED means 180 degrees + elsif (i_phase_delay = "CENTER_ALIGNED") then + my_phase := (180 * inclock_period) / 360; + elsif (i_phase_delay = "45_DEGREES") then + my_phase := (45 * inclock_period) / 360; + elsif (i_phase_delay = "90_DEGREES") then + my_phase := (90 * inclock_period) / 360; + elsif (i_phase_delay = "135_DEGREES") then + my_phase := (135 * inclock_period) / 360; + elsif (i_phase_delay = "180_DEGREES") then + my_phase := (180 * inclock_period) / 360; + elsif (i_phase_delay = "225_DEGREES") then + my_phase := (225 * inclock_period) / 360; + elsif (i_phase_delay = "270_DEGREES") then + my_phase := (270 * inclock_period) / 360; + elsif (i_phase_delay = "315_DEGREES") then + my_phase := (315 * inclock_period) / 360; + else + ASSERT FALSE + REPORT "Invalid outclock alignment. Using 'EDGE_ALIGNED' instead" + SEVERITY WARNING; + my_phase := 0; + end if; + + -- add 1 to "round up" calculation result + my_phase := my_phase + 1; + + my_phase := my_phase / clock_boost_calc (output_data_rate, inclock_period, + deserialization_factor, inclock_boost); + + -- add 1 to "round up" calculation result + my_phase := my_phase + 1; + + end if; + + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + int_delay := my_phase; + else + int_delay := my_phase + get_phase_delay(inclock_data_alignment); + end if; + + return int_delay; + + end get_outclock_phase_delay; + + + -- Calculates the phase shift of the fastclk that feeds the + -- stratix_tx_outclk or stratixii_tx_outclk. + function get_lvds_outclock_phase_delay (constant i_phase_delay : in string; + constant i_outclock_divide_by : in positive; + constant i_intended_device_family : in string) + return integer is + variable my_phase : integer := 0; + begin + if (FAMILY_HAS_FLEXIBLE_LVDS = true) then + my_phase := get_outclock_phase_delay(i_phase_delay); + elsif ((i_outclock_divide_by = 1) or + (i_phase_delay = "45_DEGREES") or + (i_phase_delay = "90_DEGREES") or + (i_phase_delay = "135_DEGREES")) then + my_phase := get_outclock_phase_delay(i_phase_delay); + elsif (outclock_alignment = "UNUSED") then + if (outclock_phase_shift >= get_phase_delay("180_DEGREES")) then + my_phase := get_outclock_phase_delay(i_phase_delay) - get_phase_delay("180_DEGREES"); + else + my_phase := get_outclock_phase_delay(i_phase_delay); + end if; + elsif ((i_phase_delay = "180_DEGREES") or + (i_phase_delay = "CENTER_ALIGNED")) then + my_phase := get_phase_delay(inclock_data_alignment); + elsif (i_phase_delay = "225_DEGREES") then + my_phase := get_outclock_phase_delay("45_DEGREES"); + elsif (i_phase_delay = "270_DEGREES") then + my_phase := get_outclock_phase_delay("90_DEGREES"); + elsif (i_phase_delay = "315_DEGREES") then + my_phase := get_outclock_phase_delay("135_DEGREES"); + else + my_phase := get_phase_delay(inclock_data_alignment); + end if; + + if (FEATURE_FAMILY_STRATIXII(i_intended_device_family) and (implement_in_les = "OFF")) then + my_phase := my_phase - (inclock_period / ( 2 * clock_boost_calc (output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + end if; + + return my_phase; + end get_lvds_outclock_phase_delay; + + -- get clk1_multiply_by value for PLL (for flexible lvds) + function get_flvds_clk1_multiply_by ( constant i_deserialization_factor : in natural; + constant i_outclock_multiply_by : in natural; + constant i_outclock_divide_by : in natural + ) return natural is + variable clk1_mult_by : natural := 0; + begin + if (CYCLONE_TX_STYLE = false) then + clk1_mult_by := clock_boost_calc (output_data_rate, inclock_period, + deserialization_factor, inclock_boost); + elsif ( ( ((i_deserialization_factor rem 2) = 1) or + (i_deserialization_factor = 6) or + (i_deserialization_factor = 10) ) and (outclock_multiply_by = 2) and + (outclock_divide_by = deserialization_factor)) then + clk1_mult_by := clock_boost_calc (output_data_rate, inclock_period, + deserialization_factor, inclock_boost) * 2; + else + clk1_mult_by := clock_boost_calc (output_data_rate, inclock_period, + deserialization_factor, inclock_boost); + end if; + + return clk1_mult_by; + + end get_flvds_clk1_multiply_by; + + -- get clk2_multiply_by value for PLL (for flexible lvds) + function get_flvds_clk2_multiply_by ( constant i_deserialization_factor : in natural) return natural is + variable clk2_mult_by : natural := 0; + begin + if (((i_deserialization_factor rem 2) = 0) or (USE_NEW_CORECLK_CKT = true)) then + clk2_mult_by := clock_boost_calc (output_data_rate, inclock_period, + deserialization_factor, inclock_boost) * 2; + else + clk2_mult_by := clock_boost_calc (output_data_rate, inclock_period, + deserialization_factor, inclock_boost); + end if; + + return clk2_mult_by; + + end get_flvds_clk2_multiply_by; + + -- get clk1_divide_by value for PLL (for flexible lvds) + function get_flvds_clk1_divide_by ( constant i_outclock_divide_by : in natural) return natural is + variable clk1_div_by : natural := 0; + begin + if (CYCLONE_TX_STYLE = false) then + clk1_div_by := pll_d_value (output_data_rate, inclock_period); + else + clk1_div_by := i_outclock_divide_by * pll_d_value (output_data_rate, inclock_period); + end if; + + return clk1_div_by; + + end get_flvds_clk1_divide_by; + + -- get clk2_divide_by value for PLL (for flexible lvds) + function get_flvds_clk2_divide_by ( constant i_deserialization_factor : in natural) return natural is + variable clk2_div_by : natural := 0; + begin + clk2_div_by := i_deserialization_factor * pll_d_value (output_data_rate, + inclock_period); + + return clk2_div_by; + + end get_flvds_clk2_divide_by; + + --- get pll_type for PLL (for flexible lvds) + function get_flvds_pll_type ( constant i_inclock_alignment : in string) return string is + begin + if (i_inclock_alignment = "UNUSED") then + return "auto"; + else + return "flvds"; + end if; + + end get_flvds_pll_type; + + --- get phase delay in ps for cyclone ii and stratix II in LE mode --- + function get_stxii_le_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + begin + if (use_no_phase_shift = "OFF") then + my_phase := get_phase_delay(i_phase_delay) - (inclock_period / (4 * clock_boost_calc(output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + else + my_phase := get_phase_delay(i_phase_delay); + end if; + + return my_phase; + + end get_stxii_le_phase_delay; + + --- get phase delay in ps for stratix III in LE mode --- + function get_stxiii_le_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + begin + if (FEATURE_FAMILY_STRATIXIII(intended_device_family)) then + my_phase := get_phase_delay(i_phase_delay); + else + my_phase := get_phase_delay(i_phase_delay) - (inclock_period / (4 * clock_boost_calc(output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + end if; + return my_phase; + + end get_stxiii_le_phase_delay; + + --- get outclock phase delay in ps for cyclone ii and stratix II in LE mode --- + function get_stxii_le_outclock_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + begin + if (use_no_phase_shift = "OFF") then + my_phase := get_outclock_phase_delay(i_phase_delay) - (inclock_period / (4 * clock_boost_calc(output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + else + my_phase := get_outclock_phase_delay(i_phase_delay); + end if; + + return my_phase; + + end get_stxii_le_outclock_phase_delay; + + --- get outclock phase delay in ps for stratix III in LE mode --- + function get_stxiii_le_outclock_phase_delay (constant i_phase_delay : in string) return integer is + variable my_phase : integer := 0; + begin + if (FEATURE_FAMILY_STRATIXIII(intended_device_family)) then + my_phase := get_outclock_phase_delay(i_phase_delay); + else + my_phase := get_outclock_phase_delay(i_phase_delay) - (inclock_period / (4 * clock_boost_calc(output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + end if; + return my_phase; + + end get_stxiii_le_outclock_phase_delay; + + --- get phase_shift value for the clock that acts as enable signal (for StratixIII lvds) + function get_clk_ena_phase_shift ( constant i_phase_shift : in string) return string is + variable fast_clk_ena_phase_shift : integer := 0; + begin + + fast_clk_ena_phase_shift := (deserialization_factor*2-3) * (inclock_period/(2*clock_boost_calc(output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + + return int_to_str(get_stxii_inclock_phase_delay(i_phase_shift) + fast_clk_ena_phase_shift); + + end get_clk_ena_phase_shift; + + --- get phase_shift value for the clock that acts as enable signal for outclock channel (for StratixIII lvds) + function get_outclk_ena_phase_shift ( constant i_phase_shift : in string) return string is + variable fast_clk_ena_phase_shift : integer := 0; + begin + + fast_clk_ena_phase_shift := (deserialization_factor*2-3) * (inclock_period/(2*clock_boost_calc(output_data_rate, + inclock_period, deserialization_factor, inclock_boost))); + + return int_to_str(get_lvds_outclock_phase_delay(i_phase_shift, outclock_divide_by, + intended_device_family) + fast_clk_ena_phase_shift); + + end get_outclk_ena_phase_shift; +-- CONSTANT DECLARATION + + -- these constants are PLL parameters calculated from the altlvds_tx + -- parameters given + constant PHASE_INCLOCK : string + := int_to_str(get_phase_delay(inclock_data_alignment)); + + constant STXII_PHASE_INCLOCK : string + := int_to_str(get_stxii_inclock_phase_delay(inclock_data_alignment)); + + constant PHASE_OUTCLOCK : string + := int_to_str(get_lvds_outclock_phase_delay(outclock_alignment, outclock_divide_by, + intended_device_family)); + + constant INT_CLOCK_BOOST : natural + := clock_boost_calc(output_data_rate, inclock_period, + deserialization_factor, inclock_boost); + + constant REGISTER_WIDTH : natural + := deserialization_factor * number_of_channels; + + constant FLVDS_CLK1_MUL : natural := get_flvds_clk1_multiply_by(deserialization_factor, + outclock_multiply_by, outclock_divide_by); + constant FLVDS_CLK2_MUL : natural := get_flvds_clk2_multiply_by(deserialization_factor); + + constant FLVDS_CLK0_DIV : natural := pll_d_value(output_data_rate, inclock_period); + constant FLVDS_CLK1_DIV : natural := get_flvds_clk1_divide_by(outclock_divide_by); + constant FLVDS_CLK2_DIV : natural := get_flvds_clk2_divide_by(deserialization_factor); + constant FLVDS_PLL_TYPE : string := get_flvds_pll_type(inclock_data_alignment); + + constant STXII_LE_PHASE_INCLOCK : string := int_to_str(get_stxii_le_phase_delay(inclock_data_alignment)); + constant STXII_LE_PHASE_OUTCLOCK : string := int_to_str(get_stxii_le_outclock_phase_delay(outclock_alignment)); + + constant STXIII_LE_PHASE_INCLOCK : string := int_to_str(get_stxiii_le_phase_delay(inclock_data_alignment)); + constant STXIII_LE_PHASE_OUTCLOCK : string := int_to_str(get_stxiii_le_outclock_phase_delay(outclock_alignment)); + + + constant CLK_ENA_PHASE_SHIFT : string := get_clk_ena_phase_shift(inclock_data_alignment); + constant OUTCLK_ENA_PHASE_SHIFT : string := get_outclk_ena_phase_shift(outclock_alignment); + + constant BYPASS_NEEDED : boolean := (outclock_divide_by = 1); + + constant INVERT_CLOCK_NEEDED : boolean := ((outclock_alignment = "180_DEGREES") or + (outclock_alignment = "CENTER_ALIGNED")) and (use_external_pll = "ON"); + + constant FALLING_CLOCK_EDGE_NEEDED : boolean := (outclock_phase_shift >= get_phase_delay("180_DEGREES")) or + (outclock_alignment = "180_DEGREES") or + (outclock_alignment = "CENTER_ALIGNED") or + (outclock_alignment = "225_DEGREES") or + (outclock_alignment = "270_DEGREES") or + (outclock_alignment = "315_DEGREES"); + +-- SIGNAL DECLARATION + + -- registers + signal tx_in_reg : std_logic_vector(REGISTER_WIDTH -1 downto 0) + := (others => '0'); + + signal tx_in_int : std_logic_vector(REGISTER_WIDTH -1 downto 0) + := (others => '0'); + + signal tx_parallel_load_reg : std_logic_vector(REGISTER_WIDTH -1 downto 0) + := (others => '0'); + + signal dataout_l : std_logic_vector(number_of_channels -1 downto 0) + := (others => '0'); + + signal dataout_h : std_logic_vector(number_of_channels -1 downto 0) + := (others => '0'); + + signal tx_ddio_out : std_logic_vector(number_of_channels -1 downto 0) + := (others => '0'); + + signal tx_out_stratix : std_logic_vector(number_of_channels -1 downto 0) + := (others => '0'); + + signal flvds_dataout : std_logic_vector(number_of_channels -1 downto 0) + := (others => '0'); + + signal stx_phase_shift_txdata : std_logic_vector(9 downto 0) + := (others => '0'); + + signal phase_shift_txdata : std_logic_vector(9 downto 0) + := (others => '0'); + + -- clock signals + signal tx_fastclk : std_logic; -- fast clock + signal tx_slowclk : std_logic; -- slow clock + signal tx_pll_clk0 : std_logic; -- PLL clk0 output + signal tx_pll_clk1 : std_logic; -- PLL clk1 output + signal tx_pll_clk2 : std_logic; -- PLL clk2 output + signal tx_pll_clk3 : std_logic; -- PLL clk3 output + signal tx_pll_clk4 : std_logic; -- PLL clk4 output + signal tx_reg_clk : std_logic; -- clock for sync register + signal tx_coreclk_int : std_logic; + signal tx_pll_sclkout : std_logic_vector (1 downto 0) + := (others => '0'); -- PLL serial clk output + + signal stratix_inclock : std_logic + := '0'; + + signal stratixii_inclock : std_logic + := '0'; + + signal stratix_outclock : std_logic + := '0'; + + signal stratixii_outclock : std_logic + := '0'; + + signal flvds_fastclk : std_logic + := '0'; + + signal flvds_slowclk : std_logic + := '0'; + + signal flvds_outclock : std_logic + := '0'; + + signal flvds_pll_outclock : std_logic + := '0'; + + + signal stratixiii_enable0 : std_logic + := '0'; + + signal stratixiii_enable1 : std_logic + := '0'; + + -- PLL locked signal + signal tx_locked_int : std_logic; + signal pll_lock_sync : std_logic := '1'; + + + -- constant signals + signal temp_zero : std_logic := '0'; + signal temp_high : std_logic_vector (5 downto 0) + := (others => '1'); + + signal temp_clk : std_logic_vector (6 downto 0) + := (others => '0'); + + -- load enable signals for Stratix, Stratix GX and Stratix II + signal tx_pll_enable0 : std_logic + := '0'; + + signal tx_pll_enable1 : std_logic + := '0'; + + signal enable0 : std_logic + := '0'; + + signal enable0_reg : std_logic + := '0'; + + signal enable0_pipe : std_logic + := '0'; + + signal enable0_neg : std_logic + := '0'; + + signal stratix_enable : std_logic + := '0'; + + signal stratixii_enable : std_logic + := '0'; + + signal local_clk_div_lloaden : std_logic + := '0'; + + +-- COMPONENT DECLARATION + -- PLL for Stratix and Stratix GX + component MF_stratix_pll + generic ( + pll_type : string := "lvds"; + inclk0_input_frequency : positive ; --Required + valid_lock_multiplier : integer := 1; + simulation_type : string := "functional"; + clk0_multiply_by : positive := 1; + clk0_divide_by : positive := 1; + clk0_phase_shift : string := "0"; + clk1_multiply_by : positive := 1; + clk1_divide_by : positive := 1; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : natural := 50; + clk2_multiply_by : positive := 1; + clk2_divide_by : positive := 1; + clk2_phase_shift : string := "0"; + family_name : string := "Stratix"; + m : integer := 0 ); + port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); + fbin : in std_logic := '1'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + clkena : in std_logic_vector(5 downto 0) := (others => '1'); + extclkena : in std_logic_vector(3 downto 0) := (OTHERS=>'1'); + scanaclr : in std_logic := '0'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + comparator : in std_logic := '0'; + clk : out std_logic_vector(5 downto 0); + locked : out std_logic; + enable0 : out std_logic; + enable1 : out std_logic ); + end component; -- MF_stratix_pll + + -- PLL for Stratix II + component MF_stratixii_pll + generic ( + pll_type : string := "lvds"; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + inclk0_input_frequency : positive ; --Required + simulation_type : string := "functional"; + clk0_multiply_by : positive := 1; + clk0_divide_by : positive := 1; + clk0_phase_shift : string := "0"; + clk1_multiply_by : positive := 1; + clk1_divide_by : positive := 1; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : natural := 50; + clk2_multiply_by : positive := 1; + clk2_divide_by : positive := 1; + clk2_phase_shift : string := "0"; + sclkout0_phase_shift : string := "0"; + sclkout1_phase_shift : string := "0"; + family_name : string := "Stratix II"; + m : integer := 0 ); + port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); + fbin : in std_logic := '1'; + ena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanread : in std_logic := '0'; + scanwrite : in std_logic := '0'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + testin : in std_logic_vector(3 downto 0) := (OTHERS=>'0'); + clk : out std_logic_vector(5 downto 0); + locked : out std_logic; + enable0 : out std_logic; + enable1 : out std_logic; + sclkout : out std_logic_vector(1 downto 0) ); + end component; -- MF_stratixii_pll + + -- PLL for Stratix III + component MF_stratixiii_pll + generic ( + operation_mode : string := "normal"; + pll_type : string := "lvds"; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + inclk0_input_frequency : positive ; + simulation_type : string := "functional"; + clk0_multiply_by : positive := 1; + clk0_divide_by : positive := 1; + clk0_phase_shift : string := "0"; + clk1_multiply_by : positive := 1; + clk1_divide_by : positive := 1; + clk1_duty_cycle : integer := 50; + clk1_phase_shift : string := "0"; + clk2_multiply_by : positive := 1; + clk2_divide_by : positive := 1; + clk2_phase_shift : string := "0"; + clk3_multiply_by : positive := 1; + clk3_divide_by : positive := 1; + clk3_phase_shift : string := "0"; + clk4_multiply_by : positive := 1; + clk4_divide_by : positive := 1; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + family_name : string := "Stratix III"; + self_reset_on_loss_lock : string := "OFF"; + m : integer := 0 ); + + port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); + fbin : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scanclk : in std_logic := '1'; + scandata : in std_logic := '1'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + phasecounterselect : in std_logic_vector(3 downto 0) := (OTHERS=>'1'); + phaseupdown : in std_logic := '1'; + phasestep : in std_logic := '1'; + clk : out std_logic_vector(9 downto 0); + locked : out std_logic ); + end component; -- MF_stratixiii_pll + + component stratix_tx_outclk + generic ( + deserialization_factor : natural; -- Required parameter + bypass_serializer : boolean := FALSE; + invert_clock : boolean := FALSE; + use_falling_clock_edge : boolean := FALSE ); + port ( + tx_in : in std_logic_vector(deserialization_factor-1 downto 0); + tx_fastclk : in std_logic; + tx_enable : in std_logic := '1'; + tx_out : out std_logic := '0' ); + end component; -- stratix_tx_outclk + + component stratixii_tx_outclk + generic ( + deserialization_factor : natural; -- Required parameter + bypass_serializer : boolean := FALSE; + invert_clock : boolean := FALSE; + use_falling_clock_edge : boolean := FALSE ); + port ( + tx_in : in std_logic_vector(deserialization_factor-1 downto 0); + tx_fastclk : in std_logic; + tx_enable : in std_logic := '1'; + tx_out : out std_logic := '0' ); + end component; -- stratixii_tx_outclk + + component flexible_lvds_tx + generic ( + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + registered_input : string := "ON"; + use_new_coreclk_ckt : boolean := false; + outclock_multiply_by : natural := 1; + outclock_divide_by : natural := 2; + outclock_duty_cycle : natural := 50; + use_self_generated_outclock : boolean := false ); + port ( + tx_in : in std_logic_vector(REGISTER_WIDTH -1 downto 0); + tx_fastclk : in std_logic; + tx_slowclk : in std_logic; + tx_regclk : in std_logic; + pll_areset : in std_logic; + tx_data_reset : in std_logic; + pll_outclock : in std_logic; + tx_locked : in std_logic; + tx_out : out std_logic_vector(number_of_channels-1 downto 0); + tx_outclock : out std_logic ); + end component; -- flexible_lvds_tx + + + component stratixv_local_clk_divider + generic ( + clk_divide_by : natural := 4 ); + port ( + clkin : in std_logic; + lloaden : out std_logic := '0' ); + end component; -- stratixv_local_clk_divider + + +begin + +-- SIGNAL ASSIGNMENTS + + tx_out <= tx_in_int when (deserialization_factor = 1) + else tx_ddio_out when (deserialization_factor = 2) + else flvds_dataout when (FAMILY_HAS_FLEXIBLE_LVDS = true) + else tx_out_stratix when ((STRATIX_TX_STYLE = true) or + (STRATIXII_TX_STYLE = true) or + (STRATIXIII_TX_STYLE = true)) + else tx_in_int; + + tx_in_int <= tx_in_reg when (registered_input /= "OFF") + else tx_in; + + tx_fastclk <= '0' when (deserialization_factor < 3) + else tx_inclock when ((use_external_pll = "ON") or (enable_clock_pin_mode = "ON")) + else tx_pll_sclkout(0) when (STRATIXII_TX_STYLE = true) + else tx_pll_clk0; + + tx_slowclk <= '0' when ((use_external_pll = "ON") or + (deserialization_factor < 3)) + else tx_pll_clk2 when ((STRATIX_TX_STYLE = true) or + (STRATIXII_TX_STYLE = true) or + (STRATIXIII_TX_STYLE = true) or + (CYCLONE_TX_STYLE = true) or + (CYCLONEIII_TX_STYLE = true) or + (CYCLONEII_TX_STYLE = true)) + else tx_pll_clk1; + + tx_outclock <= tx_inclock when (deserialization_factor < 3) + else flvds_outclock when (FAMILY_HAS_FLEXIBLE_LVDS = true) + else stratix_outclock when (STRATIX_TX_STYLE = true) + else stratixii_outclock when (STRATIXII_TX_STYLE = true) or + (STRATIXIII_TX_STYLE = true) + else tx_slowclk; + + flvds_pll_outclock <= tx_pll_clk1; + + tx_coreclk_int <= tx_slowclk; + + tx_coreclock <= tx_coreclk_int; + + tx_reg_clk <= tx_inclock when (use_external_pll = "ON") + else sync_inclock when (registered_input = "ON") and + (multi_clock = "ON") and + (STRATIX_TX_STYLE = false) and + (STRATIXII_TX_STYLE = false) and + (STRATIXIII_TX_STYLE = false) and + (CYCLONE_TX_STYLE = false) and + (CYCLONEIII_TX_STYLE = false) and + (CYCLONEII_TX_STYLE = false) + else tx_coreclk_int when (registered_input = "TX_CORECLK") and + ((STRATIX_TX_STYLE = true) or + (STRATIXII_TX_STYLE = true) or + (STRATIXIII_TX_STYLE = true) or + (CYCLONE_TX_STYLE = true) or + (CYCLONEIII_TX_STYLE = true) or + (CYCLONEII_TX_STYLE = true)) + else tx_inclock; + + tx_locked <= tx_locked_int and pll_lock_sync when (((STRATIXIII_TX_STYLE = true) or + (CYCLONEIII_TX_STYLE = true)) and + (deserialization_factor > 2)) + else tx_locked_int when (deserialization_factor > 2) + else '1'; + + enable0 <= tx_enable when (use_external_pll = "ON") + else stratixiii_enable0 when (STRATIXIII_TX_STYLE = true) and (implement_in_les = "OFF") + else tx_pll_enable0; + + stratixiii_enable0 <= local_clk_div_lloaden when (enable_clock_pin_mode = "ON") + else tx_pll_clk1; + + stratixiii_enable1 <= local_clk_div_lloaden when (enable_clock_pin_mode = "ON") + else tx_pll_clk4; + + stratix_inclock <= '0' when (STRATIX_TX_STYLE = false) or + (implement_in_les = "ON") + else tx_pll_clk1; + + stratix_enable <= '0' when (STRATIX_TX_STYLE = false) or + (implement_in_les = "ON") + else tx_pll_enable1; + + stratixii_inclock <= '0' when ((STRATIXII_TX_STYLE = false) and + (STRATIXIII_TX_STYLE = false)) or + (implement_in_les = "ON") + else tx_inclock when ((use_external_pll = "ON") or (enable_clock_pin_mode = "ON")) + else tx_pll_clk3 when (STRATIXIII_TX_STYLE = true) + else tx_pll_sclkout(1); + + stratixii_enable <= '0' when ((STRATIXII_TX_STYLE = false) and + (STRATIXIII_TX_STYLE = false)) or + (implement_in_les = "ON") + else tx_enable when (use_external_pll = "ON") + else stratixiii_enable1 when (STRATIXIII_TX_STYLE = true) + else tx_pll_enable1; + + flvds_fastclk <= '0' when (FAMILY_HAS_FLEXIBLE_LVDS = false) + else tx_inclock when (use_external_pll = "ON") + else tx_pll_clk0; + + flvds_slowclk <= '0' when (FAMILY_HAS_FLEXIBLE_LVDS = false) + else tx_syncclock when (use_external_pll = "ON") + else tx_pll_clk2; + + +-- COMPONENT ASSIGNMENTS + + -- PLL instantiations + -- MF_stratix_pll used for Stratix and Stratix GX + -- MF_stratixii_pll used for Stratix II + -- MF_stratixiii_pll used for Stratix III + STRATIX_PLL: + if ((STRATIX_TX_STYLE = true) and (implement_in_les = "OFF") and + (deserialization_factor > 2)) generate + + u2: MF_stratix_pll -- STRATIX PLL + generic map ( + inclk0_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => 1, + clk0_phase_shift => PHASE_INCLOCK, + clk1_multiply_by => INT_CLOCK_BOOST, + clk1_divide_by => 1, + clk1_phase_shift => PHASE_OUTCLOCK, + clk1_duty_cycle => 50, + clk2_multiply_by => INT_CLOCK_BOOST, + clk2_divide_by => deserialization_factor, + clk2_phase_shift => PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => tx_inclock, + inclk(1) => temp_zero, + ena => tx_pll_enable, + areset => pll_areset, + clkena(5 downto 0) => temp_high, + clk(0) => tx_pll_clk0, + clk(1) => tx_pll_clk1, + clk(2) => tx_pll_clk2, + clk (5 downto 3) => temp_clk(2 downto 0), + locked => tx_locked_int, + enable0 => tx_pll_enable0, + enable1 => tx_pll_enable1 ); + end generate STRATIX_PLL; + + STRATIXII_PLL: + if ((STRATIXII_TX_STYLE = true) and (implement_in_les = "OFF") and + (use_external_pll /= "ON") and (deserialization_factor > 2)) generate + + u2: MF_stratixii_pll -- STRATIX II PLL + generic map ( + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => deserialization_factor, + clk0_phase_shift => STXII_PHASE_INCLOCK, + clk1_multiply_by => INT_CLOCK_BOOST, + clk1_divide_by => deserialization_factor, + clk1_phase_shift => PHASE_OUTCLOCK, + clk1_duty_cycle => 50, + clk2_multiply_by => INT_CLOCK_BOOST, + clk2_divide_by => deserialization_factor, + clk2_phase_shift => STXII_PHASE_INCLOCK, + sclkout0_phase_shift => STXII_PHASE_INCLOCK, + sclkout1_phase_shift => PHASE_OUTCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => tx_inclock, + inclk(1) => temp_zero, + ena => tx_pll_enable, + areset => pll_areset, + clk(0) => tx_pll_clk0, + clk(1) => tx_pll_clk1, + clk(2) => tx_pll_clk2, + clk (5 downto 3) => temp_clk(2 downto 0), + locked => tx_locked_int, + enable0 => tx_pll_enable0, + enable1 => tx_pll_enable1, + sclkout(0) => tx_pll_sclkout(0), + sclkout(1) => tx_pll_sclkout(1) ); + end generate STRATIXII_PLL; + + STRATIXIII_PLL: + if ((STRATIXIII_TX_STYLE = true) and (implement_in_les = "OFF") and + (use_external_pll /= "ON") and (deserialization_factor > 2)) generate + + U4: MF_stratixiii_pll -- Stratix III PLL + generic map ( + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => 1, + clk1_multiply_by => INT_CLOCK_BOOST, + clk1_divide_by => deserialization_factor, + clk1_duty_cycle => integer(real(100/deserialization_factor) + real(0.5)), + clk2_multiply_by => INT_CLOCK_BOOST, + clk2_divide_by => deserialization_factor, + clk3_multiply_by => INT_CLOCK_BOOST, + clk3_divide_by => 1, + clk4_multiply_by => INT_CLOCK_BOOST, + clk4_divide_by => deserialization_factor, + clk4_duty_cycle => integer(real(100/deserialization_factor) + real(0.5)), + clk0_phase_shift => STXII_PHASE_INCLOCK, + clk1_phase_shift => CLK_ENA_PHASE_SHIFT, + clk2_phase_shift => STXII_PHASE_INCLOCK, + clk3_phase_shift => PHASE_OUTCLOCK, + clk4_phase_shift => OUTCLK_ENA_PHASE_SHIFT, + family_name => intended_device_family ) + port map ( + inclk(0) => tx_inclock, + inclk(1) => temp_zero, + areset => pll_areset, + clk(0) => tx_pll_clk0, + clk(1) => tx_pll_clk1, + clk(2) => tx_pll_clk2, + clk(3) => tx_pll_clk3, + clk(4) => tx_pll_clk4, + clk (9 downto 5) => temp_clk(4 downto 0), + locked => tx_locked_int ); + + end generate STRATIXIII_PLL; + + FLVDS_STX_PLL: + if ((FAMILY_HAS_FLEXIBLE_LVDS = true) and (FAMILY_HAS_STRATIX_STYLE_PLL = true) and + (CYCLONE_TX_STYLE = false) and (deserialization_factor > 2)) generate + + u2: MF_stratix_pll -- STRATIX PLL + generic map ( + pll_type => FLVDS_PLL_TYPE, + inclk0_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => FLVDS_CLK0_DIV, + clk0_phase_shift => PHASE_INCLOCK, + clk1_multiply_by => FLVDS_CLK1_MUL, + clk1_divide_by => FLVDS_CLK1_DIV, + clk1_phase_shift => PHASE_OUTCLOCK, + clk1_duty_cycle => 50, + clk2_multiply_by => FLVDS_CLK2_MUL, + clk2_divide_by => FLVDS_CLK2_DIV, + clk2_phase_shift => PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => tx_inclock, + inclk(1) => temp_zero, + ena => tx_pll_enable, + areset => pll_areset, + clkena(5 downto 0) => temp_high, + clk(0) => tx_pll_clk0, + clk(1) => tx_pll_clk1, + clk(2) => tx_pll_clk2, + clk (5 downto 3) => temp_clk(2 downto 0), + locked => tx_locked_int, + enable0 => tx_pll_enable0, + enable1 => tx_pll_enable1 ); + end generate FLVDS_STX_PLL; + + CYC_PLL: + if ((CYCLONE_TX_STYLE = true) and (deserialization_factor > 2)) generate + + u2: MF_stratix_pll -- Cyclone PLL + generic map ( + pll_type => FLVDS_PLL_TYPE, + inclk0_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => FLVDS_CLK0_DIV, + clk0_phase_shift => PHASE_INCLOCK, + clk1_multiply_by => FLVDS_CLK1_MUL, + clk1_divide_by => FLVDS_CLK1_DIV, + clk1_phase_shift => PHASE_OUTCLOCK, + clk1_duty_cycle => outclock_duty_cycle, + clk2_multiply_by => FLVDS_CLK2_MUL, + clk2_divide_by => FLVDS_CLK2_DIV, + clk2_phase_shift => PHASE_INCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => tx_inclock, + inclk(1) => temp_zero, + ena => tx_pll_enable, + areset => pll_areset, + clkena(5 downto 0) => temp_high, + clk(0) => tx_pll_clk0, + clk(1) => tx_pll_clk1, + clk(2) => tx_pll_clk2, + clk (5 downto 3) => temp_clk(2 downto 0), + locked => tx_locked_int, + enable0 => tx_pll_enable0, + enable1 => tx_pll_enable1 ); + end generate CYC_PLL; + + FLVDS_STXII_PLL: + if ((FAMILY_HAS_FLEXIBLE_LVDS = true) and (FAMILY_HAS_STRATIXII_STYLE_PLL = true) and + (use_external_pll /= "ON") and (deserialization_factor > 2)) generate + + u2: MF_stratixii_pll -- STRATIX II PLL + generic map ( + pll_type => FLVDS_PLL_TYPE, + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => FLVDS_CLK0_DIV, + clk0_phase_shift => STXII_LE_PHASE_INCLOCK, + clk1_multiply_by => FLVDS_CLK1_MUL, + clk1_divide_by => FLVDS_CLK1_DIV, + clk1_phase_shift => STXII_LE_PHASE_OUTCLOCK, + clk1_duty_cycle => 50, + clk2_multiply_by => FLVDS_CLK2_MUL, + clk2_divide_by => FLVDS_CLK2_DIV, + clk2_phase_shift => STXII_LE_PHASE_INCLOCK, + sclkout0_phase_shift => STXII_LE_PHASE_INCLOCK, + sclkout1_phase_shift => STXII_LE_PHASE_OUTCLOCK, + family_name => intended_device_family ) + port map ( + inclk(0) => tx_inclock, + inclk(1) => temp_zero, + ena => tx_pll_enable, + areset => pll_areset, + clk(0) => tx_pll_clk0, + clk(1) => tx_pll_clk1, + clk(2) => tx_pll_clk2, + clk (5 downto 3) => temp_clk(2 downto 0), + locked => tx_locked_int, + enable0 => tx_pll_enable0, + enable1 => tx_pll_enable1, + sclkout(0) => tx_pll_sclkout(0), + sclkout(1) => tx_pll_sclkout(1) ); + end generate FLVDS_STXII_PLL; + + FLVDS_STXIII_PLL: + if ((FAMILY_HAS_FLEXIBLE_LVDS = true) and + (FAMILY_HAS_STRATIXIII_STYLE_PLL = true) and (use_external_pll /= "ON") and + (deserialization_factor > 2)) generate + + U5: MF_stratixiii_pll -- Stratix III PLL + generic map ( + pll_type => FLVDS_PLL_TYPE, + vco_multiply_by => INT_CLOCK_BOOST, + vco_divide_by => 1, + inclk0_input_frequency => inclock_period, + clk0_multiply_by => INT_CLOCK_BOOST, + clk0_divide_by => FLVDS_CLK0_DIV, + clk0_phase_shift => STXIII_LE_PHASE_INCLOCK, + clk1_multiply_by => FLVDS_CLK1_MUL, + clk1_divide_by => FLVDS_CLK1_DIV, + clk1_phase_shift => STXIII_LE_PHASE_OUTCLOCK, + clk1_duty_cycle => 50, + clk2_multiply_by => FLVDS_CLK2_MUL, + clk2_divide_by => FLVDS_CLK2_DIV, + clk2_phase_shift => STXIII_LE_PHASE_INCLOCK, + family_name => intended_device_family, + self_reset_on_loss_lock => alpha_tolower(pll_self_reset_on_loss_lock) ) + port map ( + inclk(0) => tx_inclock, + inclk(1) => temp_zero, + areset => pll_areset, + clk(0) => tx_pll_clk0, + clk(1) => tx_pll_clk1, + clk(2) => tx_pll_clk2, + clk (9 downto 3) => temp_clk(6 downto 0), + locked => tx_locked_int ); + + end generate FLVDS_STXIII_PLL; + + STRATIX_OUTCLK : + if ((STRATIX_TX_STYLE = true) and (implement_in_les = "OFF") and + (deserialization_factor > 2)) generate + + u3: stratix_tx_outclk + generic map ( + deserialization_factor => deserialization_factor, + bypass_serializer => BYPASS_NEEDED, + invert_clock => INVERT_CLOCK_NEEDED, + use_falling_clock_edge => FALLING_CLOCK_EDGE_NEEDED ) + port map ( + tx_in => stx_phase_shift_txdata(deserialization_factor-1 downto 0), + tx_fastclk => stratix_inclock, + tx_enable => stratix_enable, + tx_out => stratix_outclock ); + end generate STRATIX_OUTCLK; + + STRATIXII_OUTCLK : + if (((STRATIXII_TX_STYLE = true) or (STRATIXIII_TX_STYLE = true)) and + (implement_in_les = "OFF") and (deserialization_factor > 2)) generate + + u3: stratixii_tx_outclk + generic map ( + deserialization_factor => deserialization_factor, + bypass_serializer => BYPASS_NEEDED, + invert_clock => INVERT_CLOCK_NEEDED, + use_falling_clock_edge => FALLING_CLOCK_EDGE_NEEDED ) + port map ( + tx_in => phase_shift_txdata(deserialization_factor-1 downto 0), + tx_fastclk => stratixii_inclock, + tx_enable => stratixii_enable, + tx_out => stratixii_outclock ); + end generate STRATIXII_OUTCLK; + + FLEXIBLE_LVDS_TRANSMITTER: + if (((FAMILY_HAS_FLEXIBLE_LVDS = true) and (deserialization_factor > 2)) or (MAXV_TX_STYLE = true)) generate + + U4: flexible_lvds_tx + generic map ( + number_of_channels => number_of_channels, + deserialization_factor => deserialization_factor, + registered_input => registered_input, + use_new_coreclk_ckt => USE_NEW_CORECLK_CKT, + outclock_multiply_by => outclock_multiply_by, + outclock_divide_by => outclock_divide_by, + outclock_duty_cycle => outclock_duty_cycle, + use_self_generated_outclock => USE_SELF_GENERATED_OUTCLOCK ) + port map ( + tx_in => tx_in, + tx_fastclk => flvds_fastclk, + tx_slowclk => flvds_slowclk, + tx_regclk => tx_reg_clk, + pll_areset => pll_areset, + tx_data_reset => tx_data_reset, + pll_outclock => flvds_pll_outclock, + tx_locked => tx_locked_int, + tx_out => flvds_dataout, + tx_outclock => flvds_outclock ); + end generate FLEXIBLE_LVDS_TRANSMITTER; + + STRATIXV_TX_LOCAL_CLK_DIVIDER: + if ((STRATIXIII_TX_STYLE = true) and (enable_clock_pin_mode = "ON")) generate + + U6: stratixv_local_clk_divider -- Stratix V local clock divider block + generic map ( + clk_divide_by => deserialization_factor ) + + port map ( + clkin => tx_fastclk, + lloaden => local_clk_div_lloaden ); + + end generate STRATIXV_TX_LOCAL_CLK_DIVIDER; + +-- PROCESS DECLARATION + + INITIAL : process + variable non_50_duty_cycle_is_valid : boolean := false; + begin + -- basic error checking for invalid deserialization factors + if (IS_VALID_FAMILY(intended_device_family) = false) then + ASSERT FALSE + REPORT intended_device_family & " is not a valid device family!" + SEVERITY ERROR; + elsif ((STRATIX_TX_STYLE = true) and + (deserialization_factor /= 1) and + (deserialization_factor /= 2) and + ((deserialization_factor > 10) or + (deserialization_factor < 4))) then + ASSERT FALSE + REPORT "Stratix and Stratix GX does not support the specified deserialization factor!" + SEVERITY ERROR; + elsif ((STRATIXII_TX_STYLE = true) and + (deserialization_factor > 10)) then + ASSERT FALSE + REPORT "Stratix II does not support the specified deserialization factor!" + SEVERITY ERROR; + elsif (FAMILY_HAS_FLEXIBLE_LVDS = true) then + if ((deserialization_factor rem 2) = 1) then + if ((outclock_multiply_by /= 1) and (outclock_multiply_by /= 2)) then + ASSERT FALSE + REPORT "Only values of 1 and 2 are allowed for outclock_multiply_by." + SEVERITY ERROR; + end if; + + if ((coreclock_divide_by /= 1) and (coreclock_divide_by /= 2)) then + ASSERT FALSE + REPORT "Only values of 1 and 2 are allowed for coreclock_divide_by." + SEVERITY ERROR; + end if; + + if ((coreclock_divide_by = 2) and ((deserialization_factor rem 2) = 1)) then + if (CYCLONE_TX_STYLE = true) then + if (outclock_multiply_by = 2) then + ASSERT FALSE + REPORT "The specified combination of coreclock_divide_by, outclock_multiply_by, outclock_divide_by and deserialization_factor is not supported for " & intended_device_family & + ". Use the megawizard to generate a valid configuration." + SEVERITY ERROR; + end if; + end if; + end if; + + if (outclock_multiply_by = 2) then + if (outclock_divide_by /= deserialization_factor) then + ASSERT FALSE + REPORT "The specified combination of coreclock_divide_by, outclock_multiply_by, outclock_divide_by and deserialization_factor is not supported for " & intended_device_family & + ". Use the megawizard to generate a valid configuration." + SEVERITY ERROR; + end if; + end if; + + if (CYCLONE_TX_STYLE = true) then + if ((outclock_divide_by = deserialization_factor) and (outclock_multiply_by = 1)) then + non_50_duty_cycle_is_valid := true; + end if; + else + if ((outclock_divide_by = deserialization_factor) and ((outclock_multiply_by = 1) or (coreclock_divide_by = 2))) then + non_50_duty_cycle_is_valid := true; + end if; + end if; + end if; + + if (outclock_duty_cycle /= 50) then + if (non_50_duty_cycle_is_valid = true) then + if ((outclock_multiply_by = 2) and ((deserialization_factor rem 2) = 1)) then + if (deserialization_factor = 7) then + if (outclock_duty_cycle /= 57) then + ASSERT FALSE + REPORT "Illegal value of " & int_to_str(outclock_duty_cycle) & " specified for outclock_duty_cycle parameter. The legal value(s) for the specified parameter are 57." + SEVERITY ERROR; + end if; + elsif (deserialization_factor = 9) then + if (outclock_duty_cycle /= 56) then + ASSERT FALSE + REPORT "Illegal value of " & int_to_str(outclock_duty_cycle) & " specified for outclock_duty_cycle parameter. The legal value(s) for the specified parameter are 56." + SEVERITY ERROR; + end if; + elsif (deserialization_factor = 5) then + if (outclock_duty_cycle /= 60) then + ASSERT FALSE + REPORT "Illegal value of " & int_to_str(outclock_duty_cycle) & " specified for outclock_duty_cycle parameter. The legal value(s) for the specified parameter are 60." + SEVERITY ERROR; + end if; + end if; + else + if (deserialization_factor = 7) then + if (outclock_duty_cycle /= 57) then + ASSERT FALSE + REPORT "Illegal value of " & int_to_str(outclock_duty_cycle) & " specified for outclock_duty_cycle parameter. The legal value(s) for the specified parameter are 50 and 57." + SEVERITY ERROR; + end if; + elsif (deserialization_factor = 9) then + if (outclock_duty_cycle /= 56) then + ASSERT FALSE + REPORT "Illegal value of " & int_to_str(outclock_duty_cycle) & " specified for outclock_duty_cycle parameter. The legal value(s) for the specified parameter are 50 and 56." + SEVERITY ERROR; + end if; + elsif (deserialization_factor = 5) then + if (outclock_duty_cycle /= 60) then + ASSERT FALSE + REPORT "Illegal value of " & int_to_str(outclock_duty_cycle) & " specified for outclock_duty_cycle parameter. The legal value(s) for the specified parameter are 50 and 60." + SEVERITY ERROR; + end if; + end if; + end if; + else + ASSERT FALSE + REPORT "Illegal value of " & int_to_str(outclock_duty_cycle) & " specified for outclock_duty_cycle parameter. The legal value(s) for the specified parameter are 50." + SEVERITY ERROR; + end if; + end if; + end if; + + -- Input data needed by stratix_tx_outclk in order to generate the tx_outclock. + if (outclock_divide_by > 1) then + if (deserialization_factor = 4) then + if ( outclock_divide_by = 2) then + stx_phase_shift_txdata(3 downto 0) <= "1010"; + elsif (outclock_divide_by = 4) then + stx_phase_shift_txdata(3 downto 0) <= "0011"; + end if; + elsif (deserialization_factor = 8) then + if (outclock_divide_by = 2) then + stx_phase_shift_txdata(7 downto 0) <= "10101010"; + elsif (outclock_divide_by = 4) then + stx_phase_shift_txdata(7 downto 0) <= "00110011"; + elsif (outclock_divide_by = 8) then + stx_phase_shift_txdata(7 downto 0) <= "11000011"; + end if; + elsif (deserialization_factor = 10) then + if (outclock_divide_by = 2) then + stx_phase_shift_txdata(9 downto 0) <= "1010101010"; + elsif (outclock_divide_by = 10) then + stx_phase_shift_txdata(9 downto 0) <= "1110000011"; + end if; + elsif (deserialization_factor = 7) then + if (outclock_divide_by = 7) then + stx_phase_shift_txdata(6 downto 0) <= "1100011"; + end if; + elsif (deserialization_factor = 9) then + if (outclock_divide_by = 9) then + stx_phase_shift_txdata(8 downto 0) <= "110000111"; + end if; + elsif (deserialization_factor = 5) then + if (outclock_divide_by = 5) then + stx_phase_shift_txdata(4 downto 0) <= "10011"; + end if; + end if; + end if; + + -- Input data needed by stratixii_tx_outclk in order to generate the tx_outclock. + if (outclock_divide_by > 1) then + if (deserialization_factor = 4) then + if ( outclock_divide_by = 2) then + phase_shift_txdata(3 downto 0) <= "1010"; + elsif (outclock_divide_by = 4) then + phase_shift_txdata(3 downto 0) <= "1100"; + end if; + elsif (deserialization_factor = 6) then + if ( outclock_divide_by = 2) then + phase_shift_txdata(5 downto 0) <= "101010"; + elsif (outclock_divide_by = 6) then + phase_shift_txdata(5 downto 0) <= "111000"; + end if; + elsif (deserialization_factor = 8) then + if (outclock_divide_by = 2) then + phase_shift_txdata(7 downto 0) <= "10101010"; + elsif (outclock_divide_by = 4) then + phase_shift_txdata(7 downto 0) <= "11001100"; + elsif (outclock_divide_by = 8) then + phase_shift_txdata(7 downto 0) <= "11110000"; + end if; + elsif (deserialization_factor = 10) then + if (outclock_divide_by = 2) then + phase_shift_txdata(9 downto 0) <= "1010101010"; + elsif (outclock_divide_by = 10) then + phase_shift_txdata(9 downto 0) <= "1111100000"; + end if; + elsif (deserialization_factor = 7) then + if (outclock_divide_by = 7) then + phase_shift_txdata(6 downto 0) <= "1111000"; + end if; + elsif (deserialization_factor = 9) then + if (outclock_divide_by = 9) then + phase_shift_txdata(8 downto 0) <= "110000111"; + end if; + elsif (deserialization_factor = 5) then + if (outclock_divide_by = 5) then + phase_shift_txdata(4 downto 0) <= "10011"; + end if; + -- SPR 338253 - add support for SIII deserialization 3, outclock divide 3 mode. + elsif ((deserialization_factor = 3) and (STRATIXIII_TX_STYLE = true)) then + if (outclock_divide_by = 3) then + phase_shift_txdata(2 downto 0) <= "101"; + end if; + end if; + end if; + wait; + end process; -- INITIAL process + + + DDIO_OUT_RECEIVE : process (tx_inclock, tx_in_int) + begin + if (deserialization_factor = 2) then + if (tx_inclock'event and (tx_inclock = '1')) then + for i in 0 to (number_of_channels-1) loop + dataout_l(i) <= tx_in_int(i*2); + dataout_h(i) <= tx_in_int((i*2)+1); + end loop; + end if; + end if; + end process; -- DDIO_OUT_RECEIVE process + + + DDIO_OUT_TRANSMIT : process(tx_inclock, dataout_h, dataout_l) + begin + if (deserialization_factor = 2) then + if (tx_inclock = '1') then + for i in 0 to (number_of_channels-1) loop + tx_ddio_out(i) <= dataout_h(i); + end loop; + else + for i in 0 to (number_of_channels-1) loop + tx_ddio_out(i) <= dataout_l(i); + end loop; + end if; + end if; + end process; -- DDIO_OUT_TRANSMIT process + + + -- Registering of the load enable signal for Stratix's registers + TXLOADEN: process (tx_fastclk) + begin + if (tx_fastclk'event and (tx_fastclk ='1')) then + enable0_pipe <= enable0_reg; + enable0_reg <= enable0; + elsif (tx_fastclk'event and (tx_fastclk = '0')) then + enable0_neg <= enable0_pipe; + end if; + + end process; -- TXLOADEN process + + STRATIX_SERIALIZE : + if ((implement_in_les = "OFF") and (deserialization_factor > 2)) generate + + -- Load and serialize the data + SERIALIZE2: process(tx_fastclk, enable0_reg) + variable count : integer := 0; + variable sample : integer; + variable shift_data : std_logic := '0'; + variable tx_shift_reg : std_logic_vector(REGISTER_WIDTH -1 downto 0) + := (others => '0'); + begin + + -- Load data when registered load enable signal goes high + if (((STRATIX_TX_STYLE = true) and (enable0_reg = '1') and enable0_reg'event) or + (((STRATIXII_TX_STYLE = true) or (STRATIXIII_TX_STYLE = true)) and tx_fastclk'event and (tx_fastclk = '1'))) then + if (registered_input /= "OFF") then + tx_parallel_load_reg <= tx_in_reg; + else + tx_parallel_load_reg <= tx_in; + end if; + end if; + + -- Serialize the data, MSB is the first bit to be shifted out + if (tx_fastclk'event and (tx_fastclk = '1')) then + if (((STRATIX_TX_STYLE = true) and (enable0_neg = '1')) or + (((STRATIXII_TX_STYLE = true) or (STRATIXIII_TX_STYLE = true)) and (enable0_reg = '1'))) then + tx_shift_reg := tx_parallel_load_reg; + count := 0; + shift_data := '1'; + end if; + + if (shift_data = '1') then + count := (count rem deserialization_factor) + 1; + for i in 0 to number_of_channels-1 loop + tx_out_stratix(i) <= tx_shift_reg((i+1)*deserialization_factor - count); + end loop; + end if; + end if; + end process; -- SERIALIZE2 process + end generate STRATIX_SERIALIZE; + + -- synchronization register + -- registers the data_in before passing on to the parallel load register or + -- holding register + SYNC_REG: process(tx_reg_clk) + begin + if ((tx_reg_clk = '1') and tx_reg_clk'event) then + tx_in_reg <= tx_in after 5 ps; + end if; + end process; -- SYNC_REG process + + process (tx_locked_int, pll_areset) + begin + if (pll_areset = '1') then + pll_lock_sync <= '0'; + elsif (tx_locked_int = '1' and tx_locked_int'event) then + pll_lock_sync <= '1'; + end if; + end process; + +end behavior; +--END OF ARCHITECTURE + +---------------------------------------------------------------------------- +-- Module Name : altdpram +-- +-- Description : Parameterized Dual Port RAM megafunction +-- +-- Limitation : This megafunction is provided only for backward +-- compatibility in Cyclone, Stratix, and Stratix GX +-- designs. +-- +-- Results expected : RAM having dual ports behaviour +-- +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use std.textio.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.ALTERA_COMMON_CONVERSION.all; + +-- ENTITY DECLARATION +entity altdpram is + generic + ( width : natural; + widthad : natural; + numwords : natural := 0; + lpm_file : string := "UNUSED"; + lpm_hint : string := "USE_EAB=ON"; + use_eab : string := "ON"; + indata_reg : string := "INCLOCK"; + indata_aclr : string := "ON"; + wraddress_reg : string := "INCLOCK"; + wraddress_aclr : string := "ON"; + wrcontrol_reg : string := "INCLOCK"; + wrcontrol_aclr : string := "ON"; + rdaddress_reg : string := "OUTCLOCK"; + rdaddress_aclr : string := "ON"; + rdcontrol_reg : string := "OUTCLOCK"; + rdcontrol_aclr : string := "ON"; + outdata_reg : string := "UNREGISTERED"; + outdata_aclr : string := "ON"; + ram_block_type : string := "AUTO"; + width_byteena : natural := 1; + byte_size : natural := 0; + read_during_write_mode_mixed_ports : string := "DONT_CARE"; + maximum_depth : natural := 2048; + intended_device_family : string := "Stratix"; + lpm_type : string := "altdpram"); + port + ( wren : in std_logic := '0'; + data : in std_logic_vector(width-1 downto 0); + wraddress : in std_logic_vector(widthad-1 downto 0); + wraddressstall : in std_logic := '0'; + inclock : in std_logic := '1'; + inclocken : in std_logic := '1'; + rden : in std_logic := '1'; + rdaddress : in std_logic_vector(widthad-1 downto 0); + rdaddressstall : in std_logic := '0'; + byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1'); + outclock : in std_logic := '1'; + outclocken : in std_logic := '1'; + aclr : in std_logic := '0'; + q : out std_logic_vector(width-1 downto 0) ); + +end altdpram; + +-- ARCHITECTURE DECLARATION +architecture behavior of altdpram is + +-- FUNCTION DEFINITION + +function get_read_during_write_mode(read_during_write : string; wrcontrol_reg : string; rdaddress_reg : string; outdata_reg : string) return string is +begin + if ((wrcontrol_reg = "INCLOCK") and (rdaddress_reg = "INCLOCK") and (outdata_reg = "INCLOCK")) then + return read_during_write; + else + return "NEW_DATA"; + end if; +end get_read_during_write_mode; + + +-- CONSTANT DEFINITION + +constant i_read_during_write : string := get_read_during_write_mode(read_during_write_mode_mixed_ports, wrcontrol_reg, rdaddress_reg, outdata_reg); + + +-- TYPE DECLARATION +type alt_memory is array((2**WIDTHAD)-1 downto 0) of std_logic_vector(WIDTH-1 downto 0); + +-- SIGNAL DECLARATION +signal idata_tmp: std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal idata_reg: std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal idata_hi : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal idata_lo : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal ibyteena_tmp : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '1'); +signal ibyteena_reg : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '1'); +signal iq_tmp : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal iq_reg : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal irdaddress_tmp : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal irdaddress_reg : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal irdaddress_reg_low : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal iwraddress_tmp : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal iwraddress_reg : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal iwraddress_hi : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal iwraddress_lo : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal iwren_tmp : std_logic := '0'; +signal iwren_reg : std_logic := '0'; +signal iwren_hi : std_logic := '0'; +signal iwren_lo : std_logic := '0'; +signal irden_tmp : std_logic := '0'; +signal irden_reg : std_logic := '0'; +signal write_at_low_clock : boolean := false; +signal rden_low_output_0 : boolean := false; +signal i_byte_size : integer := 0; +signal i_byteena_mask_reg_hi : std_logic_vector(width - 1 downto 0) := (others => '1'); +signal i_byteena_mask_reg_out_hi : std_logic_vector(width - 1 downto 0) := (others => '1'); +signal i_byteena_mask_reg_x_hi : std_logic_vector(width - 1 downto 0) := (others => '0'); +signal i_byteena_mask_reg_lo : std_logic_vector(width - 1 downto 0) := (others => '1'); +signal i_byteena_mask_reg_out_lo : std_logic_vector(width - 1 downto 0) := (others => '1'); +signal i_byteena_mask_reg_x_lo : std_logic_vector(width - 1 downto 0) := (others => '0'); +signal first_clk_rising_edge : boolean := true; + +begin + +-- PROCESS BLOCKS + CHECKING: process + begin + if ((indata_aclr = "ON") and ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))) then + assert false + report intended_device_family & " device family does not support aclr on input data. Aclr on this port will be ignored." + severity warning; + end if; + + if ((wraddress_aclr = "ON") and ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))) then + assert false + report intended_device_family & " device family does not support aclr on write address. Aclr on this port will be ignored." + severity warning; + end if; + + if ((wrcontrol_aclr = "ON") and ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))) then + assert false + report intended_device_family & " device family does not support aclr on write control. Aclr on this port will be ignored." + severity warning; + end if; + + if ((rdcontrol_aclr = "ON") and ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))) then + assert false + report intended_device_family & "device family does not have read control (rden). Parameter rdcontrol_aclr will be ignored." + severity warning; + end if; + + if (((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))) and (wrcontrol_reg /= "INCLOCK")) then + assert false + report "wrcontrol_reg can only be INCLOCK for " & intended_device_family + severity warning; + end if; + + if (((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))) and (read_during_write_mode_mixed_ports = "OLD_DATA") and (rdaddress_aclr = "ON")) then + assert false + report "rdaddress_aclr cannot be turned on when it is " & intended_device_family & " with read_during_write_mode_mixed_ports = OLD_DATA" + severity warning; + end if; + + if ((((width / width_byteena) = 5) or (width / width_byteena = 10) or (width / width_byteena = 8) or (width / width_byteena = 9)) and (byte_size = 0)) and + ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))) then + assert false + report "byte_size (width / width_byteena) should be in 5, 8, 9 or 10. It will default to 5." + severity warning; + end if; + + wait; + end process; + + INITIAL: process (inclock, outclock) + variable init : boolean := false; + begin + if (not init) then + if ((((lpm_hint = "USE_EAB=ON") and (use_eab /= "OFF")) or (use_eab = "ON")) ) then + if (wrcontrol_reg = "INCLOCK") then + if (not (FEATURE_FAMILY_STRATIXV(intended_device_family) or FEATURE_FAMILY_ARRIAV(intended_device_family) or FEATURE_FAMILY_ARRIA10(intended_device_family))) then + write_at_low_clock <= true; + end if; + end if; + end if; + + if ((byte_size = 0) and (width_byteena > 0)) then + if (((width / width_byteena) = 5) or (width / width_byteena = 10) or (width / width_byteena = 8) or (width / width_byteena = 9)) then + i_byte_size <= 5; + else + i_byte_size <= width / width_byteena; + end if; + else + i_byte_size <= byte_size; + end if; + + init := true; + end if; + end process; -- initial + + SYNC: process( data, idata_reg, rden, irden_reg, rdaddress, irdaddress_reg, + wren, iwren_reg, wraddress, iwraddress_reg, iq_tmp, iq_reg, + aclr, ibyteena_reg, irdaddress_reg_low) + begin + ibyteena_tmp <= ibyteena_reg; + + if (((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))) and (rdaddress_reg = "INCLOCK") and (i_read_during_write = "OLD_DATA")) then + irdaddress_tmp <= irdaddress_reg_low; + elsif ((rdaddress_reg = "INCLOCK") or (rdaddress_reg = "OUTCLOCK")) then + irdaddress_tmp <= irdaddress_reg; + else + irdaddress_tmp <= rdaddress; + end if; + + if (((rdcontrol_reg = "INCLOCK") or (rdcontrol_reg = "OUTCLOCK")) and not ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))) then + irden_tmp <= irden_reg; + else + irden_tmp <= rden; + end if; + + if (wraddress_reg = "INCLOCK") then + iwraddress_tmp <= iwraddress_reg; + else + iwraddress_tmp <= wraddress; + end if; + + if (wrcontrol_reg = "INCLOCK") then + iwren_tmp <= iwren_reg; + else + iwren_tmp <= wren; + end if; + + if (indata_reg = "INCLOCK") then + idata_tmp <= idata_reg; + else + idata_tmp <= data; + end if; + + if (outdata_reg /= "UNREGISTERED") then + q <= iq_reg; + else + q <= iq_tmp; + end if; + + if (aclr = '1') then + if( (indata_aclr = "ON") and ( indata_reg /= "UNREGISTERED") and not ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))) then + idata_tmp <= (OTHERS => '0'); + end if; + + if( (wraddress_aclr = "ON") and ( wraddress_reg /= "UNREGISTERED") and not ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))))then + iwraddress_tmp <= (OTHERS => '0'); + end if; + + if( (wrcontrol_aclr = "ON") and ( wrcontrol_reg /= "UNREGISTERED") and not ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))))then + iwren_tmp <= '0'; + end if; + + if( (rdaddress_aclr = "ON") and ( rdaddress_reg /= "UNREGISTERED") and not + ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))and (read_during_write_mode_mixed_ports = "OLD_DATA"))then + irdaddress_tmp <= (OTHERS => '0'); + end if; + + if( (rdcontrol_aclr = "ON") and ( rdcontrol_reg /= "UNREGISTERED") and not ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))))then + irden_tmp <= '0'; + end if; + + if( (outdata_aclr = "ON") and (outdata_reg /= "UNREGISTERED") ) then + q <= (OTHERS => '0'); + end if; + end if; + end process; -- sync + + SYNC2: process( idata_hi, idata_lo, iwraddress_hi, iwraddress_lo, + iwren_hi, iwren_lo, write_at_low_clock, + i_byteena_mask_reg_hi, i_byteena_mask_reg_lo) + begin + if (write_at_low_clock) then + idata_reg <= idata_lo; + iwren_reg <= iwren_lo; + iwraddress_reg <= iwraddress_lo; + ibyteena_reg <= i_byteena_mask_reg_lo; + else + idata_reg <= idata_hi; + iwren_reg <= iwren_hi; + iwraddress_reg <= iwraddress_hi; + ibyteena_reg <= i_byteena_mask_reg_hi; + end if; + end process; -- sync2 + + + IFG1: if (rdaddress_reg = "INCLOCK") generate + process (inclock, aclr) + begin + if ((aclr = '1') and (rdaddress_aclr = "ON") and + not ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))and (read_during_write_mode_mixed_ports = "OLD_DATA")) then + irdaddress_reg <= (OTHERS => '0'); + elsif rising_edge(inclock) then + if ((inclocken = '1') and (rdaddressstall /= '1')) then + irdaddress_reg <= rdaddress; + end if; + end if; + + if falling_edge(inclock) then + if (inclocken = '1') then + irdaddress_reg_low <= irdaddress_reg; + end if; + end if; + end process; + end generate IFG1; + + IFG2: if (rdcontrol_reg = "INCLOCK") generate + process (inclock, aclr) + begin + if ((aclr = '1') and (rdcontrol_aclr = "ON")) then + irden_reg <= '0'; + elsif rising_edge(inclock) then + if (inclocken = '1') then + irden_reg <= rden; + end if; + end if; + end process; + end generate IFG2; + + IFG3: if (rdaddress_reg = "OUTCLOCK") generate + process (outclock, aclr) + begin + if ((aclr = '1') and (rdaddress_aclr = "ON") and + not ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))and (read_during_write_mode_mixed_ports = "OLD_DATA")) then + irdaddress_reg <= (OTHERS => '0'); + elsif rising_edge(outclock) then + if ((outclocken = '1') and (rdaddressstall /= '1')) then + irdaddress_reg <= rdaddress; + end if; + end if; + end process; + end generate IFG3; + + IFG4: if (rdcontrol_reg = "OUTCLOCK") generate + process (outclock, aclr) + begin + if ((aclr = '1') and (rdcontrol_aclr = "ON")) then + irden_reg <= '0'; + elsif rising_edge(outclock) then + if (outclocken = '1') then + irden_reg <= rden; + end if; + end if; + end process; + end generate IFG4; + + + + REGISTERS: process (inclock, outclock, aclr) + variable m_byteena_mask_reg : std_logic_vector(width - 1 downto 0); + variable m_byteena_mask_reg_out : std_logic_vector(width - 1 downto 0); + variable m_byteena_mask_reg_x : std_logic_vector(width - 1 downto 0):= (others => '0'); + begin + + -- WRITE REGS -- + if ((aclr = '1') and (indata_aclr = "ON") and (indata_reg /= "UNREGISTERED") ) then + idata_hi <= (OTHERS => '0'); + idata_lo <= (OTHERS => '0'); + elsif rising_edge(inclock) then + if (inclocken = '1') then + idata_hi <= data; + end if; + elsif falling_edge(inclock) then + idata_lo <= idata_hi; + end if; + + if ((aclr = '1') and (wraddress_aclr = "ON") and (wraddress_reg /= "UNREGISTERED") ) then + iwraddress_hi <= (OTHERS => '0'); + iwraddress_lo <= (OTHERS => '0'); + elsif rising_edge(inclock) then + if ((inclocken = '1') and (wraddressstall /= '1')) then + iwraddress_hi <= wraddress; + end if; + elsif falling_edge(inclock) then + iwraddress_lo <= iwraddress_hi; + end if; + + if ((aclr = '1') and (wrcontrol_aclr = "ON") and (wrcontrol_reg /= "UNREGISTERED") ) then + iwren_hi <= '0'; + iwren_lo <= '0'; + elsif rising_edge(inclock) then + if (inclocken = '1') then + iwren_hi <= wren; + end if; + elsif falling_edge(inclock) then + iwren_lo <= iwren_hi; + end if; + + if rising_edge(inclock) then + if (width_byteena = 1) then + m_byteena_mask_reg := (others => byteena(0)); + if (byteena(0) = '1') then + m_byteena_mask_reg_out := (others => '0'); + m_byteena_mask_reg_x := (others => '0'); + elsif (byteena(0) = '0') then + m_byteena_mask_reg_x := (others => '0'); + m_byteena_mask_reg_out := (others => 'X'); + else + m_byteena_mask_reg_x := (others => 'X'); + m_byteena_mask_reg_out := (others => 'X'); + end if; + + else + for k in 0 to (width - 1) loop + m_byteena_mask_reg(k) := byteena(k / i_byte_size); + if (m_byteena_mask_reg(k) = '1') then + m_byteena_mask_reg_out(k) := '0'; + m_byteena_mask_reg_x(k) := '0'; + elsif (m_byteena_mask_reg(k) = '0') then + m_byteena_mask_reg_x(k) := '0'; + m_byteena_mask_reg_out(k) := 'X'; + else + m_byteena_mask_reg_out(k) := 'X'; + m_byteena_mask_reg_x(k) := 'X'; + end if; + end loop; + end if; + + i_byteena_mask_reg_out_hi <= m_byteena_mask_reg_out; + i_byteena_mask_reg_hi <= m_byteena_mask_reg; + i_byteena_mask_reg_x_hi <= m_byteena_mask_reg_x; + + if (inclocken = '1') then + first_clk_rising_edge <= false; + end if; + elsif falling_edge(inclock) then + + i_byteena_mask_reg_out_lo <= i_byteena_mask_reg_out_hi; + i_byteena_mask_reg_lo <= i_byteena_mask_reg_hi; + i_byteena_mask_reg_x_lo <= i_byteena_mask_reg_x_hi; + + end if; + + -- READ REGS -- + if ((aclr = '1') and (outdata_aclr = "ON") and ( outdata_reg /= "UNREGISTERED") ) then + iq_reg <= (OTHERS => '0'); + elsif (rising_edge(outclock) and (outdata_reg = "OUTCLOCK")) then + if (outclocken = '1') then + iq_reg <= iq_tmp; + end if; + elsif (rising_edge(inclock) and (outdata_reg = "INCLOCK")) then + if (inclocken = '1') then + iq_reg <= iq_tmp; + end if; + end if; + + end process; -- registers + + MEMORY: process(idata_tmp, iwren_tmp, irden_tmp, irdaddress_tmp, iwraddress_tmp, ibyteena_tmp, rden_low_output_0, inclocken, first_clk_rising_edge) + variable mem_data : alt_memory; + variable mem_data_word : std_logic_vector(width-1 downto 0); + variable mem_init : boolean := false; + variable i : integer := 0; + variable j : integer := 0; + variable k : integer := 0; + variable n : integer := 0; + variable m : integer := 0; + variable lineno : integer := 0; + variable buf : line; + variable booval : boolean; + FILE mem_data_file : TEXT; + variable char : string(1 downto 1) := " "; + variable base : string(2 downto 1); + variable byte : string(2 downto 1); + variable rec_type : string(2 downto 1); + variable datain : string(2 downto 1); + variable addr : string(2 downto 1); + variable checksum : string(2 downto 1); + variable startadd: string(4 downto 1); + variable ibase : integer := 0; + variable ibyte : integer := 0; + variable istartadd : integer := 0; + variable check_sum_vec : std_logic_vector(7 downto 0); + variable check_sum_vec_tmp : std_logic_vector(7 downto 0); + variable m_write_event : std_logic := '0'; + variable m_old_data : std_logic_vector(width-1 downto 0); + variable m_string : string(1 to 15); + variable m_data_radix : string(1 to 3); + variable m_address_radix : string(1 to 3); + variable m_width : integer; + variable m_depth : integer; + variable m_start_address_int : integer := 0; + variable m_end_address_int : integer := 0; + variable m_address_int : integer := 0; + variable m_data_int : std_logic_vector(width+4 downto 0) := (OTHERS => '0'); + variable found_keyword_content : boolean := false; + variable get_memory_content : boolean := false; + variable get_start_Address : boolean := false; + variable get_end_Address : boolean := false; + begin + -- INITIALIZE -- + if NOT(mem_init) then + -- INITIALIZE TO 0 -- + for i in mem_data'LOW to mem_data'HIGH loop + mem_data(i) := (OTHERS => '0'); + end loop; + + if (lpm_file /= "UNUSED") then + FILE_OPEN(mem_data_file, LPM_FILE, READ_MODE); + if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3 to lpm_file'length)) = ".hex") then + WHILE NOT ENDFILE(mem_data_file) loop + booval := true; + READLINE(mem_data_file, buf); + lineno := lineno + 1; + check_sum_vec := (OTHERS => '0'); + + if (buf(buf'LOW) = ':') then + i := 1; + SHRINK_LINE(buf, i); + READ(L=>buf, VALUE=>byte, good=>booval); + if (not booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal Intel Hex Format!" + SEVERITY ERROR; + end if; + ibyte := HEX_STR_TO_INT(byte); + check_sum_vec := unsigned(check_sum_vec) + + unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8)); + READ(L=>buf, VALUE=>startadd, good=>booval); + if (not booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + istartadd := HEX_STR_TO_INT(startadd); + addr(2) := startadd(4); + addr(1) := startadd(3); + check_sum_vec := unsigned(check_sum_vec) + + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8)); + addr(2) := startadd(2); + addr(1) := startadd(1); + check_sum_vec := unsigned(check_sum_vec) + + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8)); + READ(L=>buf, VALUE=>rec_type, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8)); + else + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + + case rec_type is + when "00"=> -- Data record + i := 0; + k := (WIDTH + 7) / 8; -- # of bytes per entry + while (i < ibyte) loop + mem_data_word := (others => '0'); + j := 1; + while ( (j <= k) and (i < ibyte) ) loop + READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time. + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8)); + + if (WIDTH > 8) then + mem_data_word := mem_data_word(WIDTH - 9 downto 0) & CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8); + else + mem_data_word := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), WIDTH); + end if; + j := j + 1; + i := i + 1; + end loop; + + if ((ibase + istartadd) <= (2 ** widthad - 1)) then + mem_data(ibase + istartadd) := mem_data_word; + else + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]: Unable to initialized memory with this data record since the specified address is out of valid address range!" + SEVERITY WARNING; + end if; + istartadd := istartadd + 1; + end loop; + when "01"=> + exit; + when "02"=> + ibase := 0; + if (ibyte /= 2) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal Intel Hex Format for record type 02! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + ibase := (ibase * 256) + HEX_STR_TO_INT(base); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + ibase := ibase * 16; + when "03"=> + if (ibyte /= 4) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format for record type 03! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + when "04"=> + ibase := 0; + if (ibyte /= 2) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format for record type 04! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + ibase := (ibase * 256) + HEX_STR_TO_INT(base); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + ibase := ibase * 65536; + when "05"=> + if (ibyte /= 4) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format for record type 05! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + when OTHERS => + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Illegal record type in Intel Hex File! " + SEVERITY ERROR; + end case; + + READ(L=>buf, VALUE=>checksum,good=>booval); + if (not booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Checksum is missing! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(not (check_sum_vec)) + 1 ; + check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8); + + if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Incorrect checksum!" + SEVERITY ERROR; + end if; + end loop; + elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3 to lpm_file'length)) = ".mif") then + -- ************************************************ + -- Read in RAM initialization file (mif) + -- ************************************************ + while not endfile(mem_data_file) loop + booval := true; + readline(mem_data_file, buf); + lineno := lineno + 1; + LOOP2 : while (buf'length > 0) loop + if (buf(buf'low) = '-') then + if (buf(buf'low) = '-') then + -- ignore comment started with --. + exit LOOP2; + end if; + elsif (buf(buf'low) = '%') then + i := 1; + + -- ignore comment which begin with % and end with another %. + while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop + i := i+1; + end loop; + + if (i >= buf'high) then + exit LOOP2; + else + SHRINK_LINE(buf, i+1); + end if; + elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then + i := 1; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i >= buf'high) then + exit LOOP2; + else + SHRINK_LINE(buf, i); + end if; + elsif (get_memory_content = true) then + + if ((buf(buf'low to buf'low +2) = "end") or + (buf(buf'low to buf'low +2) = "END") or + (buf(buf'low to buf'low +2) = "End")) then + get_memory_content := false; + exit LOOP2; + else + get_start_address := false; + get_end_address := false; + m_start_address_int := 0; + m_end_address_int := 0; + m_address_int := 0; + m_data_int := (others => '0'); + if (buf(buf'low) = '[') then + get_start_Address := true; + SHRINK_LINE(buf, 1); + end if; + + case m_address_radix is + when "hex" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *16 + HEX_STR_TO_INT(char); + end loop; + when "bin" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *2 + BIN_STR_TO_INT(char); + end loop; + when "dec" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "uns" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "oct" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *8 + OCT_STR_TO_INT(char); + end loop; + when others => + assert false + report "Unsupported address_radix!" + severity error; + end case; + + if (get_start_Address = true) then + + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then + get_start_Address := false; + get_end_Address := true; + m_start_address_int := m_address_int; + SHRINK_LINE(buf, 2); + end if; + end if; + + if (get_end_address = true) then + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + m_address_int := 0; + case m_address_radix is + when "hex" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *16 + HEX_STR_TO_INT(char); + end loop; + when "bin" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *2 + BIN_STR_TO_INT(char); + end loop; + when "dec" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "uns" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "oct" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *8 + OCT_STR_TO_INT(char); + end loop; + when others => + assert false + report "Unsupported address_radix!" + severity error; + end case; + + if (buf(buf'low) = ']') then + get_end_address := false; + m_end_address_int := m_address_int; + SHRINK_LINE(buf, 1); + end if; + end if; + + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + if (buf(buf'low) = ':') then + SHRINK_LINE(buf, 1); + end if; + + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + case m_data_radix is + when "hex" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+4 downto 0) := m_data_int(width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4); + end loop; + when "bin" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+1 downto 0) := m_data_int(width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4); + end loop; + when "dec" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+3 downto 0) := m_data_int(width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4); + end loop; + when "uns" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+3 downto 0) := m_data_int(width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4); + end loop; + when "oct" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+3 downto 0) := m_data_int(width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4); + end loop; + when others => + assert false + report "Unsupported data_radix!" + severity error; + end case; + + if (m_start_address_int /= m_end_address_int) then + for i in m_start_address_int to m_end_address_int loop + mem_data(i) := m_data_int(width-1 downto 0); + end loop; + else + mem_data(m_address_int) := m_data_int(width-1 downto 0); + end if; + exit LOOP2; + end if; + elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then + read(l=>buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to i)); + + m_width := INT_STR_TO_INT(m_string(1 to i)); + end if; + exit LOOP2; + elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and + ((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then + read(l=>buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to i)); + + m_depth := INT_STR_TO_INT(m_string(1 to i)); + end if; + exit LOOP2; + elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then + read(l=>buf, value=>m_string(1 to 10)); + + if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to 3)); + + m_data_radix := ALPHA_TOLOWER(m_string(1 to 3)); + end if; + exit LOOP2; + elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then + read(l=>buf, value=>m_string(1 to 13)); + + if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to 3)); + + m_address_radix := ALPHA_TOLOWER(m_string(1 to 3)); + end if; + exit LOOP2; + elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then + read(l=>buf, value=>m_string(1 to 7)); + + if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then + found_keyword_content := true; + end if; + elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then + read(l=>buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then + if (found_keyword_content = true) then + get_memory_content := true; + end if; + end if; + end if; + end loop; + end loop; + + else + assert false + report "Unsupported memory initialization file type (" & lpm_file(lpm_file'length -3 to lpm_file'length) & ")!" + severity error; + end if; + -- VHDL93 FILE_CLOSE(mem_data_file); + end if; + mem_init := TRUE; + + else -- already initialized + + if (iwren_tmp'event or iwraddress_tmp'event or idata_tmp'event or ibyteena_tmp'event) then + m_write_event := '1'; + end if; + + -- MEMORY FUNCTION -- + -- Write and read data to and from the memory. + -- If write and read are at the same address, whatever wrote into + -- the memory will immediately reflected at the read results. + if ((iwren_tmp = '1') and (m_write_event = '1')) then + if ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family))) then + if (inclocken = '1') then + m_old_data := mem_data (ieee.std_logic_unsigned.conv_integer(iwraddress_tmp)); + mem_data (ieee.std_logic_unsigned.conv_integer(iwraddress_tmp)) := ((idata_tmp and ibyteena_tmp) or + (mem_data(ieee.std_logic_unsigned.conv_integer(iwraddress_tmp)) and not ibyteena_tmp)); + end if; + else + mem_data (ieee.std_logic_unsigned.conv_integer(iwraddress_tmp)) := idata_tmp; + end if; + end if; + + m_write_event := '0'; + + if (irden_tmp = '1') then + if ((irdaddress_tmp = iwraddress_tmp) and (iwren_tmp = '1') and ((FEATURE_FAMILY_STRATIXV(intended_device_family)) or (FEATURE_FAMILY_STRATIXIII(intended_device_family)))) then + if ((i_read_during_write = "DONT_CARE") or (i_read_during_write = "CONSTRAINED_DONT_CARE")) then + iq_tmp <= (others => 'X'); + elsif (i_read_during_write = "OLD_DATA") then + iq_tmp <= m_old_data; + else + iq_tmp <= mem_data(ieee.std_logic_unsigned.conv_integer(irdaddress_tmp)); + end if; + elsif ((not first_clk_rising_edge) or (i_read_during_write /= "OLD_DATA")) then + iq_tmp <= mem_data(ieee.std_logic_unsigned.conv_integer(irdaddress_tmp)); + end if; + elsif (rden_low_output_0) then + iq_tmp <= (OTHERS => '0'); + end if; + + end if; -- if NOT(mem_init) + + end process; -- memory + +end behavior; -- altdpram + +---START_ENTITY_HEADER---------------------------------------------------------- +-- +-- Entity Name : ALTSYNCRAM +-- +-- Description : Synchronous ram model for Stratix series family +-- +-- Limitation : +-- +---END_ENTITY_HEADER------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use std.textio.all; +use work.ALTERA_COMMON_CONVERSION.all; +use work.ALTERA_DEVICE_FAMILIES.all; + +-- BEGINNING OF ENTITY + +-- ENTITY DECLARATION + +entity altsyncram is +-- GENERIC DECLARATION + generic ( + -- PORT A PARAMETERS + width_a : integer := 1; + widthad_a : integer := 1; + numwords_a : integer := 0; + outdata_reg_a : string := "UNREGISTERED"; + address_aclr_a : string := "NONE"; + outdata_aclr_a : string := "NONE"; + indata_aclr_a : string := "NONE"; + wrcontrol_aclr_a : string := "NONE"; + byteena_aclr_a : string := "NONE"; + width_byteena_a : integer := 1; + clock_enable_input_a : string := "NORMAL"; + clock_enable_output_a : string := "NORMAL"; + clock_enable_core_a : string := "USE_INPUT_CLKEN"; + read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ"; + + -- PORT B PARAMETERS + width_b : integer := 1; + widthad_b : integer := 1; + numwords_b : integer := 0; + rdcontrol_reg_b : string := "CLOCK1"; + address_reg_b : string := "CLOCK1"; + outdata_reg_b : string := "UNREGISTERED"; + outdata_aclr_b : string := "NONE"; + rdcontrol_aclr_b : string := "NONE"; + indata_reg_b : string := "CLOCK1"; + wrcontrol_wraddress_reg_b : string := "CLOCK1"; + byteena_reg_b : string := "CLOCK1"; + indata_aclr_b : string := "NONE"; + wrcontrol_aclr_b : string := "NONE"; + address_aclr_b : string := "NONE"; + byteena_aclr_b : string := "NONE"; + width_byteena_b : integer := 1; + clock_enable_input_b : string := "NORMAL"; + clock_enable_output_b : string := "NORMAL"; + clock_enable_core_b : string := "USE_INPUT_CLKEN"; + read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ"; + + -- ECC STATUS PARAMETERS + enable_ecc : string := "FALSE"; + width_eccstatus : integer := 3; + ecc_pipeline_stage_enabled : string := "FALSE"; + + -- GLOBAL PARAMETERS + operation_mode : string := "BIDIR_DUAL_PORT"; + byte_size : integer := 0; + read_during_write_mode_mixed_ports : string := "DONT_CARE"; + ram_block_type : string := "AUTO"; + init_file : string := "UNUSED"; + init_file_layout : string := "UNUSED"; + maximum_depth : integer := 0; + intended_device_family : string := "Stratix"; + power_up_uninitialized : string := "FALSE"; + implement_in_les : string := "OFF"; + sim_show_memory_data_in_port_b_layout : string := "OFF"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altsyncram" + ); + +-- PORT DECLARATION + port ( + -- INPUT PORT DECLARATION + wren_a : in std_logic := '0'; -- Port A write/read enable input + wren_b : in std_logic := '0'; -- Port B write enable input + rden_a : in std_logic := '1'; -- Port A read enable input + rden_b : in std_logic := '1'; -- Port B read enable input + data_a : in std_logic_vector(width_a - 1 downto 0) := (others => '1'); + -- Port A data input + data_b : in std_logic_vector(width_b - 1 downto 0) := (others => '1'); + -- Port B data input + address_a : in std_logic_vector(widthad_a - 1 downto 0); + -- Port A address input + address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1'); + -- Port B address input + + -- clock inputs on both ports and here are their usages: + -- Port A + -- 1. all input registers must be clocked by clock0. + -- 2. output register can be clocked by either by clock0, clock1 or none. + -- Port B + -- 1. all input registers must be clocked by either clock0 or clock1. + -- 2. output register can be clocked by either clock0, clock1 or none. + clock0 : in std_logic := '1'; + clock1 : in std_logic := 'Z'; + + -- clock enable inputs and here are their usages: + -- clocken0 -- can only be used for enabling clock0. + -- clocken1 -- can only be used for enabling clock1. + -- clocken2 -- as an alternative for enabling clock0. + -- clocken3 -- as an alternative for enabling clock1. + clocken0 : in std_logic := '1'; + clocken1 : in std_logic := '1'; + clocken2 : in std_logic := '1'; + clocken3 : in std_logic := '1'; + + -- clear inputs on both ports and here are their usages: + -- Port A + -- 1. all input registers can only be cleared by clear0 or none. + -- 2. output register can be cleared by either clear0, clear1 or none. + -- Port B + -- 1. all input registers can be cleared by either clear0, clear1 or none. + -- 2. output register can be cleared by either clear0, clear1 or none. + aclr0 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + + addressstall_a : in std_logic := '0'; + addressstall_b : in std_logic := '0'; + + byteena_a : in std_logic_vector( (width_byteena_a) - 1 downto 0) := (others => '1'); + -- Port A byte enable input + byteena_b : in std_logic_vector( (width_byteena_b) - 1 downto 0) := (others => 'Z'); + -- Port B byte enable input + + -- OUTPUT PORT DECLARATION + q_a : out std_logic_vector(width_a - 1 downto 0); -- Port A output + q_b : out std_logic_vector(width_b - 1 downto 0); -- Port B output + + -- ECC status flag + eccstatus : out std_logic_vector(width_eccstatus-1 downto 0) := (others => '0') + ); + +-- TYPE DECLARATION + + type width_a_array is array (2 ** widthad_a - 1 downto 0) of std_logic_vector(width_a - 1 downto 0); + type width_b_array is array (2 ** widthad_b - 1 downto 0) of std_logic_vector(width_b - 1 downto 0); + + +-- FUNCTION DEFINITION + + -- This procedure read the hex file into the memory content + procedure read_my_memory ( + constant use_a : in boolean; + variable mem_data_a : out width_a_array; + variable mem_data_b : out width_b_array + ) is + + variable m_mem_data_word_a : std_logic_vector(width_a-1 downto 0); + variable m_mem_data_word_b : std_logic_vector(width_b-1 downto 0); + variable i : integer := 0; + variable j : integer := 0; + variable m_num_of_bytes : integer := 0; + variable m_line_no : integer := 0; + variable m_line_buf : line ; + variable m_err_check : boolean := true; + variable m_base : string(2 downto 1); + variable m_ibase : integer := 0; + variable m_byte_str : string(2 downto 1); + variable m_rec_type : string(2 downto 1); + variable m_datain : string(2 downto 1); + variable m_character : string(1 downto 1); + variable m_addr : string(2 downto 1); + variable m_checksum : string(2 downto 1); + variable m_startadd : string(4 downto 1); + variable m_istartadd : integer := 0; + variable m_istartadd_pre : integer := 0; + variable m_byte_int : integer := 0; + variable m_check_sum_vec : std_logic_vector(7 downto 0); + variable m_check_sum_vec_tmp : std_logic_vector(7 downto 0); + variable m_string : string(1 to 15); + variable m_data_radix : string(1 to 3); + variable m_address_radix : string(1 to 3); + variable m_width : integer; + variable m_depth : integer; + variable m_start_address_int : integer := 0; + variable m_end_address_int : integer := 0; + variable m_address_int : integer := 0; + variable m_data_int : std_logic_vector(width_a+width_b+4 downto 0) := (OTHERS => '0'); + variable found_keyword_content : boolean := false; + variable get_memory_content : boolean := false; + variable get_start_Address : boolean := false; + variable get_end_Address : boolean := false; + variable m_divide_factor : integer := 1; + variable first_normal_record : boolean := true; + variable is_word_address_format : boolean := false; + file m_mem_data_file : text; + + begin + + -- Initialize memory content + if (use_a) then + for i in mem_data_a'low to mem_data_a'high loop + mem_data_a(i) := (others => '0'); + end loop; + else + for i in mem_data_b'low to mem_data_b'high loop + mem_data_b(i) := (others => '0'); + end loop; + end if; + + file_open(m_mem_data_file, init_file, read_mode); + + if (ALPHA_TOLOWER(init_file(init_file'right -3 to init_file'right)) = ".hex") then + while not endfile(m_mem_data_file) loop + m_err_check := true; + readline(m_mem_data_file, m_line_buf); + m_line_no := m_line_no + 1; + m_check_sum_vec := (others=> '0'); + + if (m_line_buf(m_line_buf'low) = ':') then + i := 1; + SHRINK_LINE(m_line_buf, i); + read(l=>m_line_buf, value=>m_byte_str, good=>m_err_check); + + if not (m_err_check) then + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal Intel Hex Format!" + severity error; + end if; + + m_byte_int := HEX_STR_TO_INT(m_byte_str); + m_check_sum_vec := unsigned(m_check_sum_vec) + + unsigned(conv_std_logic_vector(m_byte_int, 8)); + read(l=>m_line_buf, value=>m_startadd, good=>m_err_check); + + if not (m_err_check) then + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal Intel Hex Format! " + severity error; + end if; + m_istartadd_pre := m_istartadd; + m_istartadd := HEX_STR_TO_INT(m_startadd); + m_addr(2) := m_startadd(4); + m_addr(1) := m_startadd(3); + m_check_sum_vec := unsigned(m_check_sum_vec) + + unsigned(conv_std_logic_vector(HEX_STR_TO_INT(m_addr), 8)); + m_addr(2) := m_startadd(2); + m_addr(1) := m_startadd(1); + m_check_sum_vec := unsigned(m_check_sum_vec) + + unsigned(conv_std_logic_vector(HEX_STR_TO_INT(m_addr), 8)); + read(l=>m_line_buf, value=>m_rec_type, good=>m_err_check); + + if not (m_err_check) then + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal Intel Hex Format! " + severity error; + end if; + + m_check_sum_vec := unsigned(m_check_sum_vec) + + unsigned(conv_std_logic_vector(HEX_STR_TO_INT(m_rec_type), 8)); + + else + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal Intel Hex Format! " + severity error; + end if; + + case m_rec_type is + when "00"=> -- Data record + i := 0; + if (use_a) then + m_num_of_bytes := (width_a + 7) / 8; + else + m_num_of_bytes := (width_b + 7) / 8; + end if; + + if ((first_normal_record = false) and (m_istartadd /= m_num_of_bytes)) then + is_word_address_format := true; + end if; + + first_normal_record := false; + + if ((m_istartadd = m_num_of_bytes) and (is_word_address_format = false)) then + m_divide_factor := m_num_of_bytes; + end if; + + while (i < m_byte_int) loop + + if (use_a) then + m_mem_data_word_a := (others => '0'); + else + m_mem_data_word_b := (others => '0'); + end if; + + j := 1; + while ( j <= m_num_of_bytes and i < m_byte_int ) loop + read(l => m_line_buf, value => m_datain, good => m_err_check); + if not (m_err_check) then + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal Intel Hex Format! " + severity error; + end if; + + m_check_sum_vec := unsigned(m_check_sum_vec) + + unsigned(conv_std_logic_vector(HEX_STR_TO_INT(m_datain), 8)); + + if (use_a) then + if (width_a > 8) then + m_mem_data_word_a := m_mem_data_word_a(width_a - 9 downto 0) & conv_std_logic_vector(HEX_STR_TO_INT(m_datain), 8); + else + m_mem_data_word_a := conv_std_logic_vector(HEX_STR_TO_INT(m_datain), width_a); + end if; + else + if (width_b > 8) then + m_mem_data_word_b := m_mem_data_word_b(width_b - 9 downto 0) & conv_std_logic_vector(HEX_STR_TO_INT(m_datain), 8); + else + m_mem_data_word_b := conv_std_logic_vector(HEX_STR_TO_INT(m_datain), width_b); + end if; + end if; + + + j := j + 1; + i := i + 1; + end loop; + + if ((use_a) and ((m_ibase + m_istartadd) / m_divide_factor <= (2 ** widthad_a - 1)))then + mem_data_a((m_ibase + m_istartadd) / m_divide_factor) := m_mem_data_word_a; + elsif ((m_ibase + m_istartadd) / m_divide_factor <= (2 ** widthad_b - 1)) then + mem_data_b((m_ibase + m_istartadd) / m_divide_factor) := m_mem_data_word_b; + else + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]: Unable to initialized memory with this data record since the specified address is out of valid address range!" + severity warning; + end if; + m_istartadd := m_istartadd + 1; + end loop; + + when "01"=> + exit; + + when "02"=> + m_ibase := 0; + if (m_byte_int /= 2) then + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal Intel Hex Format for record type 02! " + severity error; + end if; + + for i in 0 to (m_byte_int-1) loop + read(l=>m_line_buf, value=>m_base,good=>m_err_check); + m_ibase := m_ibase * 256 + HEX_STR_TO_INT(m_base); + + if not (m_err_check) then + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal Intel Hex Format! " + severity error; + end if; + + m_check_sum_vec := unsigned(m_check_sum_vec) + + unsigned(conv_std_logic_vector(HEX_STR_TO_INT(m_base), 8)); + end loop; + + m_ibase := m_ibase * 16; + + when "03"=> + if (m_byte_int /= 4) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(m_line_no) & + "]:Illegal Intel Hex Format for record type 03! " + SEVERITY ERROR; + end if; + for i in 0 to (m_byte_int-1) loop + READ(L=>m_line_buf, VALUE=>m_base,good=>m_err_check); + if not (m_err_check) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(m_line_no) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + m_check_sum_vec := unsigned(m_check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(m_base), 8)); + end loop; + when "04"=> + m_ibase := 0; + if (m_byte_int /= 2) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(m_line_no) & + "]:Illegal Intel Hex Format for record type 04! " + SEVERITY ERROR; + end if; + for i in 0 to (m_byte_int-1) loop + READ(L=>m_line_buf, VALUE=>m_base,good=>m_err_check); + m_ibase := (m_ibase * 256) + HEX_STR_TO_INT(m_base); + if not (m_err_check) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(m_line_no) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + m_check_sum_vec := unsigned(m_check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(m_base), 8)); + end loop; + m_ibase := m_ibase * 65536; + when "05"=> + if (m_byte_int /= 4) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(m_line_no) & + "]:Illegal Intel Hex Format for record type 05! " + SEVERITY ERROR; + end if; + for i in 0 to (m_byte_int-1) loop + READ(L=>m_line_buf, VALUE=>m_base,good=>m_err_check); + if not (m_err_check) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(m_line_no) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + m_check_sum_vec := unsigned(m_check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(m_base), 8)); + end loop; + + when others=> + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Illegal record type in Intel Hex File! " + severity error; + + end case; + + read(l=>m_line_buf, value=>m_checksum, good=>m_err_check); + + if not (m_err_check) then + assert false + report"[Line "& INT_TO_STR_RAM(m_line_no) & "]:Checksum is missing! " + severity error; + end if; + + m_check_sum_vec := unsigned(not (m_check_sum_vec)) + 1; + m_check_sum_vec_tmp := conv_std_logic_vector(HEX_STR_TO_INT(m_checksum),8); + + if (unsigned(m_check_sum_vec) /= unsigned(m_check_sum_vec_tmp)) then + assert false + report "[Line "& INT_TO_STR_RAM(m_line_no) & "]:Incorrect checksum!" + severity error; + end if; + end loop; + elsif (ALPHA_TOLOWER(init_file(init_file'length -3 to init_file'length)) = ".mif") then + while not endfile(m_mem_data_file) loop + m_err_check := true; + readline(m_mem_data_file, m_line_buf); + m_line_no := m_line_no + 1; + m_check_sum_vec := (others=> '0'); + LOOP2 : while (m_line_buf'length > 0) loop + if (m_line_buf(m_line_buf'low) = CR) then + -- strip out CR (carriage return) character. + exit LOOP2; + elsif (m_line_buf(m_line_buf'low) = LF) then + -- strip out LF (line feed) character. + exit LOOP2; + elsif (m_line_buf(m_line_buf'low) = '-') then + if (m_line_buf(m_line_buf'low) = '-') then + -- ignore comment started with --. + exit LOOP2; + end if; + elsif (m_line_buf(m_line_buf'low) = '%') then + i := 1; + + -- ignore comment which begin with % and end with another %. + while ((i < m_line_buf'high) and (m_line_buf(m_line_buf'low + i) /= '%')) loop + i := i+1; + end loop; + + if (i >= m_line_buf'high) then + exit LOOP2; + else + SHRINK_LINE(m_line_buf, i+1); + end if; + elsif ((m_line_buf(m_line_buf'low) = ' ') or (m_line_buf(m_line_buf'low) = HT)) then + i := 1; + -- ignore space or tab character. + while ((i < m_line_buf'high-1) and ((m_line_buf(m_line_buf'low +i) = ' ') or + (m_line_buf(m_line_buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i >= m_line_buf'high) then + exit LOOP2; + else + SHRINK_LINE(m_line_buf, i); + end if; + elsif (get_memory_content = true) then + + if ((m_line_buf(m_line_buf'low to m_line_buf'low +2) = "end") or + (m_line_buf(m_line_buf'low to m_line_buf'low +2) = "END") or + (m_line_buf(m_line_buf'low to m_line_buf'low +2) = "End")) then + get_memory_content := false; + exit LOOP2; + else + get_start_address := false; + get_end_address := false; + m_start_address_int := 0; + m_end_address_int := 0; + m_address_int := 0; + m_data_int := (others => '0'); + if (m_line_buf(m_line_buf'low) = '[') then + get_start_Address := true; + SHRINK_LINE(m_line_buf, 1); + end if; + + case m_address_radix is + when "hex" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ':') and (m_line_buf(m_line_buf'low) /= '.')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *16 + HEX_STR_TO_INT(m_character); + end loop; + when "bin" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ':') and (m_line_buf(m_line_buf'low) /= '.')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *2 + BIN_STR_TO_INT(m_character); + end loop; + when "dec" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ':') and (m_line_buf(m_line_buf'low) /= '.')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *10 + INT_STR_TO_INT(m_character); + end loop; + when "uns" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ':') and (m_line_buf(m_line_buf'low) /= '.')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *10 + INT_STR_TO_INT(m_character); + end loop; + when "oct" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ':') and (m_line_buf(m_line_buf'low) /= '.')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *8 + OCT_STR_TO_INT(m_character); + end loop; + when others => + assert false + report "Unsupported address_radix!" + severity error; + end case; + + if (get_start_Address = true) then + + i := 0; + -- ignore space or tab character. + while ((i < m_line_buf'high-1) and ((m_line_buf(m_line_buf'low +i) = ' ') or + (m_line_buf(m_line_buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(m_line_buf, i); + end if; + + if ((m_line_buf(m_line_buf'low) = '.') and (m_line_buf(m_line_buf'low+1) = '.')) then + get_start_Address := false; + get_end_Address := true; + m_start_address_int := m_address_int; + SHRINK_LINE(m_line_buf, 2); + end if; + end if; + + if (get_end_address = true) then + i := 0; + -- ignore space or tab character. + while ((i < m_line_buf'high-1) and ((m_line_buf(m_line_buf'low +i) = ' ') or + (m_line_buf(m_line_buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(m_line_buf, i); + end if; + + m_address_int := 0; + case m_address_radix is + when "hex" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ']')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *16 + HEX_STR_TO_INT(m_character); + end loop; + when "bin" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ']')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *2 + BIN_STR_TO_INT(m_character); + end loop; + when "dec" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ']')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *10 + INT_STR_TO_INT(m_character); + end loop; + when "uns" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ']')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *10 + INT_STR_TO_INT(m_character); + end loop; + when "oct" => + while ((m_line_buf(m_line_buf'low) /= ' ') and (m_line_buf(m_line_buf'low) /= HT) and + (m_line_buf(m_line_buf'low) /= ']')) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_address_int := m_address_int *8 + OCT_STR_TO_INT(m_character); + end loop; + when others => + assert false + report "Unsupported address_radix!" + severity error; + end case; + + if (m_line_buf(m_line_buf'low) = ']') then + get_end_address := false; + m_end_address_int := m_address_int; + SHRINK_LINE(m_line_buf, 1); + end if; + end if; + + i := 0; + -- ignore space or tab character. + while ((i < m_line_buf'high-1) and ((m_line_buf(m_line_buf'low +i) = ' ') or + (m_line_buf(m_line_buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(m_line_buf, i); + end if; + + if (m_line_buf(m_line_buf'low) = ':') then + SHRINK_LINE(m_line_buf, 1); + end if; + + i := 0; + -- ignore space or tab character. + while ((i < m_line_buf'high-1) and ((m_line_buf(m_line_buf'low +i) = ' ') or + (m_line_buf(m_line_buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(m_line_buf, i); + end if; + + case m_data_radix is + when "hex" => + while ((m_line_buf(m_line_buf'low) /= ';') and (m_line_buf(m_line_buf'low) /= ' ') and + (m_line_buf(m_line_buf'low) /= HT)) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_data_int(width_a+width_b+4 downto 0) := m_data_int(width_a+width_b-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(m_character), 4); + end loop; + when "bin" => + while ((m_line_buf(m_line_buf'low) /= ';') and (m_line_buf(m_line_buf'low) /= ' ') and + (m_line_buf(m_line_buf'low) /= HT)) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_data_int(width_a+width_b+1 downto 0) := m_data_int(width_a+width_b-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(m_character), 4); + end loop; + when "dec" => + while ((m_line_buf(m_line_buf'low) /= ';') and (m_line_buf(m_line_buf'low) /= ' ') and + (m_line_buf(m_line_buf'low) /= HT)) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_data_int(width_a+width_b+3 downto 0) := m_data_int(width_a+width_b-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(m_character), 4); + end loop; + when "uns" => + while ((m_line_buf(m_line_buf'low) /= ';') and (m_line_buf(m_line_buf'low) /= ' ') and + (m_line_buf(m_line_buf'low) /= HT)) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_data_int(width_a+width_b+3 downto 0) := m_data_int(width_a+width_b-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(m_character), 4); + end loop; + when "oct" => + while ((m_line_buf(m_line_buf'low) /= ';') and (m_line_buf(m_line_buf'low) /= ' ') and + (m_line_buf(m_line_buf'low) /= HT)) loop + read(l => m_line_buf, value => m_character, good => m_err_check); + m_data_int(width_a+width_b+3 downto 0) := m_data_int(width_a+width_b-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(m_character), 4); + end loop; + when others => + assert false + report "Unsupported data_radix!" + severity error; + end case; + + if (use_a) then + if (m_start_address_int /= m_end_address_int) then + for i in m_start_address_int to m_end_address_int loop + mem_data_a(i) := m_data_int(width_a-1 downto 0); + end loop; + else + mem_data_a(m_address_int) := m_data_int(width_a-1 downto 0); + end if; + else + if (m_start_address_int /= m_end_address_int) then + for i in m_start_address_int to m_end_address_int loop + mem_data_b(i) := m_data_int(width_b-1 downto 0); + end loop; + else + mem_data_b(m_address_int) := m_data_int(width_b-1 downto 0); + end if; + end if; + exit LOOP2; + end if; + elsif ((m_line_buf(m_line_buf'low) = 'W') or (m_line_buf(m_line_buf'low) = 'w')) then + read(l=>m_line_buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then + i := 0; + + while ((m_line_buf(m_line_buf'low+i) = ' ') or (m_line_buf(m_line_buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (m_line_buf(m_line_buf'low + i) = '=') then + i := i+1; + end if; + + while ((m_line_buf(m_line_buf'low +i) = ' ') or (m_line_buf(m_line_buf'low +i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(m_line_buf, i); + + i := 0; + while (m_line_buf(m_line_buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>m_line_buf, value=>m_string(1 to i)); + + m_width := INT_STR_TO_INT(m_string(1 to i)); + end if; + exit LOOP2; + elsif (((m_line_buf(m_line_buf'low) = 'D') or (m_line_buf(m_line_buf'low) = 'd')) and + ((m_line_buf(m_line_buf'low+1) = 'E') or (m_line_buf(m_line_buf'low+1) = 'e'))) then + read(l=>m_line_buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then + i := 0; + + while ((m_line_buf(m_line_buf'low+i) = ' ') or (m_line_buf(m_line_buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (m_line_buf(m_line_buf'low + i) = '=') then + i := i+1; + end if; + + while ((m_line_buf(m_line_buf'low +i) = ' ') or (m_line_buf(m_line_buf'low +i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(m_line_buf, i); + + i := 0; + while (m_line_buf(m_line_buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>m_line_buf, value=>m_string(1 to i)); + + m_depth := INT_STR_TO_INT(m_string(1 to i)); + end if; + exit LOOP2; + elsif ((m_line_buf(m_line_buf'low) = 'D') or (m_line_buf(m_line_buf'low) = 'd')) then + read(l=>m_line_buf, value=>m_string(1 to 10)); + + if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then + i := 0; + + while ((m_line_buf(m_line_buf'low+i) = ' ') or (m_line_buf(m_line_buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (m_line_buf(m_line_buf'low + i) = '=') then + i := i+1; + end if; + + while ((m_line_buf(m_line_buf'low+i) = ' ') or (m_line_buf(m_line_buf'low+i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(m_line_buf, i); + + i := 0; + while (m_line_buf(m_line_buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>m_line_buf, value=>m_string(1 to 3)); + + m_data_radix := ALPHA_TOLOWER(m_string(1 to 3)); + end if; + exit LOOP2; + elsif ((m_line_buf(m_line_buf'low) = 'A') or (m_line_buf(m_line_buf'low) = 'a')) then + read(l=>m_line_buf, value=>m_string(1 to 13)); + + if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then + i := 0; + + while ((m_line_buf(m_line_buf'low+i) = ' ') or (m_line_buf(m_line_buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (m_line_buf(m_line_buf'low + i) = '=') then + i := i+1; + end if; + + while ((m_line_buf(m_line_buf'low+i) = ' ') or (m_line_buf(m_line_buf'low+i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(m_line_buf, i); + + i := 0; + while (m_line_buf(m_line_buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>m_line_buf, value=>m_string(1 to 3)); + + m_address_radix := ALPHA_TOLOWER(m_string(1 to 3)); + end if; + exit LOOP2; + elsif ((m_line_buf(m_line_buf'low) = 'C') or (m_line_buf(m_line_buf'low) = 'c')) then + read(l=>m_line_buf, value=>m_string(1 to 7)); + + if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then + found_keyword_content := true; + end if; + elsif ((m_line_buf(m_line_buf'low) = 'B') or (m_line_buf(m_line_buf'low) = 'b')) then + read(l=>m_line_buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then + if (found_keyword_content = true) then + get_memory_content := true; + end if; + end if; + else + assert false + report "MIF contains illegal character" & m_line_buf(m_line_buf'low) + severity error; + end if; + end loop; + end loop; + + else + assert false + report "Unsupported memory initialization file type (" & init_file(init_file'length -3 to init_file'length) & ")!" + severity error; + end if; + file_close(m_mem_data_file); + end read_my_memory; + +end altsyncram; + +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE + +architecture translated of altsyncram is + + function is_lutram (ram_block_type : string) return boolean is + begin + if ((ram_block_type = "LUTRAM") or (ram_block_type = "MLAB")) then + return true; + else + return false; + end if; + end is_lutram; + + function get_write_mode(read_during_write_mode_mixed_ports : string; device : string) return string is + begin + if (FEATURE_FAMILY_CYCLONE(device) or FEATURE_FAMILY_CYCLONEII(device)) then + return "OLD_DATA"; + elsif (read_during_write_mode_mixed_ports = "UNUSED") or + (read_during_write_mode_mixed_ports = "DONT_CARE") then + return "DONT_CARE"; + end if; + return read_during_write_mode_mixed_ports; + end get_write_mode; + + function get_read_operation(operation_mode : string; port_name : string) return boolean is + begin + if (port_name = "A") then + if ((operation_mode = "BIDIR_DUAL_PORT") or + (operation_mode = "SINGLE_PORT") or (operation_mode= "ROM")) then + return true; + else + return false; + end if; + else + if ((operation_mode = "BIDIR_DUAL_PORT") or + (operation_mode = "DUAL_PORT")) then + return true; + else + return false; + end if; + end if; + end get_read_operation; + + function get_write_operation(operation_mode : string; port_name : string) return boolean is + begin + if (port_name = "A") then + if ((operation_mode = "BIDIR_DUAL_PORT") or + (operation_mode = "SINGLE_PORT") or (operation_mode= "DUAL_PORT")) then + return true; + else + return false; + end if; + else + if (operation_mode = "BIDIR_DUAL_PORT") then + return true; + else + return false; + end if; + end if; + end get_write_operation; + + function check_simultaneous(operation_mode : string; ram_type : string; cread : string) return boolean is + begin + if (operation_mode = "BIDIR_DUAL_PORT") then + if ((ram_type = "MEGARAM") or (ram_type = "M-RAM") or + ((cread = "DONT_CARE") and (ram_type = "AUTO")) or + ((cread = "NEW_DATA") and (is_lutram(ram_type)))) then + return true; + else + return false; + end if; + else + return false; + end if; + end check_simultaneous; + + function get_ram_block_type (intended_device_family : string; ram_block_type : string) return string is + begin + if (FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM(intended_device_family)) then + if ((((ram_block_type = "M10K") or (is_lutram(ram_block_type))) and FEATURE_FAMILY_ARRIAV(intended_device_family)) or + (((ram_block_type = "M20K") or (is_lutram(ram_block_type))) and (FEATURE_FAMILY_STRATIXV(intended_device_family) or FEATURE_FAMILY_ARRIA10(intended_device_family))) ) then + return ram_block_type; + else + return "AUTO"; + end if; + elsif (FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family)) then + if (((ram_block_type = "M-RAM") or (ram_block_type = "MEGARAM")) and FEATURE_FAMILY_STRATIXIII(intended_device_family)) then + return "M144K"; + elsif ((((ram_block_type = "M144K") or (is_lutram(ram_block_type))) and FEATURE_FAMILY_STRATIXIII(intended_device_family)) or + (ram_block_type = "M9K")) then + return ram_block_type; + else + return "AUTO"; + end if; + else + if ((ram_block_type /= "AUTO") and (ram_block_type /= "M-RAM") and (ram_block_type /= "MEGARAM") and + (ram_block_type /= "M512") and (ram_block_type /= "M4K")) then + return "AUTO"; + else + return ram_block_type; + end if; + end if; + end get_ram_block_type; + + function get_byte_size (byte_size : integer; width_byteena_a : integer; width_a : integer; device_family : string) return integer is + variable temp : integer; + begin + if ((byte_size = 0) and (width_byteena_a > 1)) then + temp := width_a / width_byteena_a; + if (((FEATURE_FAMILY_STRATIX(device_family) or FEATURE_FAMILY_STRATIXV(device_family)) and (temp /= 8) and (temp /= 9)) or + ((FEATURE_FAMILY_BASE_STRATIXII(device_family) or FEATURE_FAMILY_BASE_CYCLONEII(device_family)) and (temp /= 1) and (temp /= 2) and (temp /= 4)) or + ((FEATURE_FAMILY_STRATIXIII(device_family) or FEATURE_FAMILY_STRATIXV(device_family)) and (temp /= 5) and (temp /= 10))) then + return 8; + else + return temp; + end if; + elsif (byte_size = 0) then + return 8; + else + return byte_size; + end if; + end get_byte_size; + + function get_write_edge (ram_block_type : string; device_family : string) return boolean is + begin + if ((ram_block_type = "M-RAM") or (ram_block_type = "MEGARAM") or + (ram_block_type = "M9K") or (ram_block_type = "M144K") or + ((FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(device_family) and (ram_block_type = "AUTO")))) then + return true; + elsif ((ram_block_type = "M20K") or (ram_block_type = "M10K") or + (FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM(device_family) and (is_lutram(ram_block_type) or (ram_block_type = "AUTO")))) then + return true; + else + return false; + end if; + end get_write_edge; + + function get_numwords(numwords : integer; widthad : integer) return integer is + begin + if (numwords /= 0) then + return numwords; + else + return (2 ** widthad); + end if; + end get_numwords; + + function is_lutram_single_port_fast_read(ram_block_type : string; read_during_write : string; operation_mode : string) return boolean is + begin + if ((is_lutram(ram_block_type)) and + ((read_during_write = "DONT_CARE") or ((outdata_reg_a = "UNREGISTERED") AND + (operation_mode = "SINGLE_PORT")))) then + return true; + else + return false; + end if; + end is_lutram_single_port_fast_read; + + function is_lutram_dual_port_fast_read (ram_block_type : string; read_during_write_mixed_ports : string; address_reg_b : string; operation_mode : string) return boolean is + begin + if ((is_lutram(ram_block_type)) and + (operation_mode = "DUAL_PORT") and + ((read_during_write_mixed_ports = "NEW_DATA") or + (read_during_write_mixed_ports = "DONT_CARE") or + (read_during_write_mixed_ports = "CONSTRAINED_DONT_CARE") or + ((read_during_write_mixed_ports = "OLD_DATA") and (outdata_reg_b = "UNREGISTERED")))) then + return true; + else + return false; + end if; + end is_lutram_dual_port_fast_read; + + function get_rden_reg_initial_value(device : string) return std_logic is + begin + if (FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family)) then + return '0'; + else + return '1'; + end if; + end get_rden_reg_initial_value; + + function get_byteena_reg_initial_value(device : string) return std_logic is + begin + if (FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM(intended_device_family)) then + return '0'; + else + return '1'; + end if; + end get_byteena_reg_initial_value; + +-- CONSTANT DECLARATION + + constant IS_STRATIXV : boolean := FEATURE_FAMILY_STRATIXV(intended_device_family); + constant IS_STRATIXIII : boolean := FEATURE_FAMILY_STRATIXIII(intended_device_family); + constant IS_HARDCOPYII : boolean := FEATURE_FAMILY_HARDCOPYII(intended_device_family); + constant IS_HARDCOPYIII : boolean := FEATURE_FAMILY_HARDCOPYIII(intended_device_family); + constant IS_HARDCOPYIV : boolean := FEATURE_FAMILY_HARDCOPYIV(intended_device_family); + constant IS_CYCLONEIII : boolean := FEATURE_FAMILY_CYCLONEIII(intended_device_family); + constant IS_BASE_STRATIXIII : boolean := FEATURE_FAMILY_BASE_STRATIXIII(intended_device_family); + constant IS_BASE_STRATIXII : boolean := FEATURE_FAMILY_BASE_STRATIXII(intended_device_family); + constant IS_BASE_CYCLONEII : boolean := FEATURE_FAMILY_BASE_CYCLONEII(intended_device_family); + constant HAS_STRATIXI_STYLE_RAM : boolean := FEATURE_FAMILY_HAS_STRATIXI_STYLE_RAM(intended_device_family); + constant HAS_STRATIXII_STYLE_RAM : boolean := FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family); + constant HAS_STRATIXIII_STYLE_RAM : boolean := FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family); + constant HAS_STRATIXV_STYLE_RAM : boolean := FEATURE_FAMILY_HAS_STRATIXV_STYLE_RAM(intended_device_family); + constant HAS_LUTRAM : boolean := FEATURE_FAMILY_HAS_LUTRAM(intended_device_family); + constant HAS_M512 : boolean := FEATURE_FAMILY_HAS_M512(intended_device_family); + constant HAS_MEGARAM : boolean := FEATURE_FAMILY_HAS_MEGARAM(intended_device_family); + + constant i_is_lutram : boolean := is_lutram(ram_block_type); + + constant i_ram_block_type : string := get_ram_block_type(intended_device_family, ram_block_type); + + constant cread_during_write_mode_mixed_ports : string := get_write_mode(read_during_write_mode_mixed_ports, intended_device_family); + + constant read_operation_a : boolean := get_read_operation(operation_mode, "A"); + + constant write_operation_a : boolean := get_write_operation(operation_mode, "A"); + + constant read_operation_b : boolean := get_read_operation(operation_mode, "B"); + + constant write_operation_b : boolean := get_write_operation(operation_mode, "B"); + + constant check_simultaneous_read_write : boolean := check_simultaneous(operation_mode, ram_block_type, cread_during_write_mode_mixed_ports); + + constant i_byte_size : integer := get_byte_size(byte_size, width_byteena_a, width_a, intended_device_family); + + constant is_write_positive_edge : boolean := get_write_edge(i_ram_block_type, intended_device_family); + + constant i_numwords_a : integer := get_numwords(numwords_a, widthad_a); + + constant i_numwords_b : integer := get_numwords(numwords_b, widthad_b); + + constant i_lutram_single_port_fast_read : boolean := is_lutram_single_port_fast_read(ram_block_type, read_during_write_mode_port_a, operation_mode); + + constant i_lutram_dual_port_fast_read : boolean := is_lutram_dual_port_fast_read(ram_block_type, read_during_write_mode_mixed_ports, address_reg_b, operation_mode); + + constant rden_reg_initial_value : std_logic := get_rden_reg_initial_value(intended_device_family); + + constant byteena_reg_initial_value : std_logic := get_byteena_reg_initial_value(intended_device_family); + + constant enable_mem_data_b_reading : boolean := (sim_show_memory_data_in_port_b_layout = "ON") and ((operation_mode = "BIDIR_DUAL_PORT") or (operation_mode = "DUAL_PORT")); + + + constant all_z : std_logic_vector(width_byteena_b-1 downto 0) := (others => 'Z'); + + +-- SIGNAL DECLARATION + + signal i_data_reg_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_data_reg_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + + signal i_q_reg_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_q_tmp_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_q_tmp2_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_q_tmp_wren_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_q_tmp2_wren_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_q_tmp_wren_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + signal i_q_reg_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + signal i_q_tmp_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + signal i_q_tmp2_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + signal i_q_output_latch : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + + signal i_q_ecc_reg_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + signal i_q_ecc_tmp_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + + signal i_current_written_data_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_original_data_a : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_original_data_b : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + + signal i_byteena_mask_reg_a_x : std_logic_vector(width_a - 1 downto 0) := (others => '0'); + signal i_byteena_mask_reg_b_x : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + signal i_byteena_mask_reg_a : std_logic_vector(width_a - 1 downto 0) := (others => byteena_reg_initial_value); + signal i_byteena_mask_reg_b : std_logic_vector(width_b - 1 downto 0) := (others => byteena_reg_initial_value); + signal i_byteena_mask_reg_a_out : std_logic_vector(width_a - 1 downto 0) := (others => byteena_reg_initial_value); + signal i_byteena_mask_reg_b_out : std_logic_vector(width_b - 1 downto 0) := (others => byteena_reg_initial_value); + signal i_byteena_mask_reg_a_out_b : std_logic_vector(width_a - 1 downto 0) := (others => byteena_reg_initial_value); + signal i_byteena_mask_reg_b_out_a : std_logic_vector(width_b - 1 downto 0) := (others => byteena_reg_initial_value); + + signal i_address_reg_a : std_logic_vector(widthad_a - 1 downto 0) := (others => '0'); + signal i_address_reg_b : std_logic_vector(widthad_b - 1 downto 0) := (others => '0'); + + signal i_wren_reg_a : std_logic := '0'; + signal i_wren_reg_b : std_logic := '0'; + signal i_rden_reg_a : std_logic := rden_reg_initial_value; + signal i_rden_reg_b : std_logic := rden_reg_initial_value; + signal i_read_flag_a : std_logic := '0'; + signal i_read_flag_b : std_logic := '0'; + signal i_reread_flag_a : std_logic := '0'; + signal i_reread_flag_b : std_logic := '0'; + signal i_reread_flag2_a : std_logic := '0'; + signal i_reread_flag2_b : std_logic := '0'; + signal i_write_flag_a : std_logic := '0'; + signal i_write_flag_b : std_logic := '0'; + signal i_nmram_write_a : std_logic := '0'; + signal i_nmram_write_b : std_logic := '0'; + + signal i_indata_aclr_a : std_logic := '0'; + signal i_address_aclr_a : std_logic := '0'; + signal i_wrcontrol_aclr_a : std_logic := '0'; + signal i_indata_aclr_b : std_logic := '0'; + signal i_address_aclr_b : std_logic := '0'; + signal i_wrcontrol_aclr_b : std_logic := '0'; + signal i_outdata_aclr_a : std_logic := '0'; + signal i_outdata_aclr_b : std_logic := '0'; + signal i_rdcontrol_aclr_b : std_logic := '0'; + signal i_byteena_aclr_a : std_logic := '0'; + signal i_byteena_aclr_b : std_logic := '0'; + + signal good_to_go_a : std_logic := '0'; + signal good_to_go_b : std_logic := '0'; + + signal i_core_clocken_a : std_logic := '1'; + signal i_core_clocken_b : std_logic := '1'; + signal i_core_clocken_b0 : std_logic := '1'; + signal i_core_clocken_b1 : std_logic := '1'; + signal i_inclocken0 : std_logic := '0'; + signal i_input_clocken_b : std_logic := '0'; + signal i_outdata_clken_b : std_logic := '0'; + signal i_outdata_clken_a : std_logic := '0'; + signal i_outlatch_clken_a : std_logic := '1'; + signal i_outlatch_clken_b : std_logic := '1'; + signal i_core_clocken_a_reg : std_logic := '0'; + signal i_core_clocken_b_reg : std_logic := '0'; + + signal default_val : std_logic := '0'; + + signal i_data_zero_a : std_logic_vector (width_a - 1 downto 0) := (others => '0'); + signal i_data_zero_b : std_logic_vector (width_b - 1 downto 0) := (others => '0'); + signal i_data_ones_a : std_logic_vector (width_a - 1 downto 0) := (others => '1'); + signal i_data_ones_b : std_logic_vector (width_b - 1 downto 0) := (others => '1'); + + signal same_clock_pulse0 : std_logic := '0'; + signal same_clock_pulse1 : std_logic := '0'; + signal i_force_reread_a : std_logic := '0'; + signal i_force_reread_a1 : std_logic := '0'; + signal i_force_reread_b : std_logic := '0'; + signal i_force_reread_b1 : std_logic := '0'; + signal i_force_reread_signal_a : std_logic := '0'; + signal i_force_reread_signal_b : std_logic := '0'; + + signal i_good_to_write_a : std_logic := '1'; + signal i_good_to_write_b : std_logic := '1'; + + +begin + + + -- Parameter Checking + process + begin + if ((operation_mode /= "BIDIR_DUAL_PORT") and (operation_mode /= "SINGLE_PORT") and + (operation_mode /= "DUAL_PORT") and (operation_mode /= "ROM")) then + assert false + report "Error: Not a valid operation mode." + severity error; + end if; + + if ((ram_block_type /= "M4K") and (ram_block_type /= "M512") and + (ram_block_type /= "LARGE") and (ram_block_type /= "MEGARAM") and + (ram_block_type /= "M-RAM") and (ram_block_type /= "AUTO") and + (ram_block_type /= "M9K") and (ram_block_type /= "M144K") and + (ram_block_type /= "M20K") and + (ram_block_type /= "M10K") and + (not i_is_lutram)) then + assert false + report "Error: RAM_BLOCK_TYPE has an invalid value." + severity error; + end if; + + if (ram_block_type /= i_ram_block_type) then + assert false + report "Warning: RAM block type is assumed as " & i_ram_block_type + severity warning; + end if; + + if ((cread_during_write_mode_mixed_ports /= "DONT_CARE") and + (cread_during_write_mode_mixed_ports /= "CONSTRAINED_DONT_CARE") and + (cread_during_write_mode_mixed_ports /= "OLD_DATA") and + (cread_during_write_mode_mixed_ports /= "NEW_DATA")) then + assert false + report "Error: Invalid value for READ_DURING_WRITE_MODE_MIXED_PORTS parameter. It has to be OLD_DATA or DONT_CARE or CONSTRAINED_DONT_CARE or NEW_DATA" + severity error; + end if; + + if ((read_during_write_mode_mixed_ports /= cread_during_write_mode_mixed_ports) and ((operation_mode /= "SINGLE_PORT") and (operation_mode /= "ROM"))) then + assert false + report "Warning: READ_DURING_WRITE_MODE_MIXED_PORTS is assumed as " & cread_during_write_mode_mixed_ports + severity warning; + end if; + + if (((i_ram_block_type = "M-RAM") or (i_ram_block_type = "MEGARAM")) and + (init_file /= "UNUSED")) then + assert false + report "Error: M-RAM block type doesn't support the use of an initialization file" + severity error; + end if; + + if ((i_byte_size /= 8) and (i_byte_size /= 9) and + (HAS_STRATIXI_STYLE_RAM)) then + assert false + report "Error: BYTE_SIZE has to be either 8 or 9" + severity error; + end if; + + if ((i_byte_size /= 8) and (i_byte_size /= 9) and + (i_byte_size /= 1) and (i_byte_size /= 2) and (i_byte_size /= 4) and + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)) then + assert false + report "Error: BYTE_SIZE has to be either 1, 2, 4, 8 or 9" + severity error; + end if; + + if ((i_byte_size /= 8) and (i_byte_size /= 9) and + (i_byte_size /= 5) and (i_byte_size /= 10) and + ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) then + assert false + report "Error: BYTE_SIZE has to be either 5, 8, 9 or 10" + severity error; + end if; + + if (width_a <= 0) then + assert false + report "Error: Invalid value for WIDTH_A parameter" + severity error; + end if; + + if ((width_b <= 0) and + ((operation_mode /= "SINGLE_PORT") and (operation_mode /= "ROM"))) then + assert false + report "Error: Invalid value for WIDTH_B parameter" + severity error; + end if; + + if (widthad_a <= 0) then + assert false + report "Error: Invalid value for WIDTHAD_A parameter" + severity error; + end if; + + if ((widthad_b <= 0) and + ((operation_mode /= "SINGLE_PORT") and (operation_mode /= "ROM"))) then + assert false + report "Error: Invalid value for WIDTHAD_B parameter" + severity error; + end if; + + if ((operation_mode = "ROM") and + ((i_ram_block_type = "M-RAM") or (i_ram_block_type = "MEGARAM"))) then + assert false + report "Error: ROM mode does not support ram_block_type = M-RAM" + severity error; + end if; + + if ((IS_BASE_STRATIXII or IS_BASE_CYCLONEII) and + (((indata_aclr_a /= "UNUSED") and (indata_aclr_a /= "NONE")) or + ((wrcontrol_aclr_a /= "UNUSED") and (wrcontrol_aclr_a /= "NONE")) or + ((byteena_aclr_a /= "UNUSED") and (byteena_aclr_a /= "NONE")) or + ((address_aclr_a /= "UNUSED") and (address_aclr_a /= "NONE")) or + ((indata_aclr_b /= "UNUSED") and (indata_aclr_b /= "NONE")) or + ((rdcontrol_aclr_b /= "UNUSED") and (rdcontrol_aclr_b /= "NONE")) or + ((wrcontrol_aclr_b /= "UNUSED") and (wrcontrol_aclr_b /= "NONE")) or + ((byteena_aclr_b /= "UNUSED") and (byteena_aclr_b /= "NONE")) or + ((address_aclr_b /= "UNUSED") and (address_aclr_b /= "NONE")))) then + assert false + report "Warning: " & intended_device_family & " device family does not support aclr signal on input ports. The aclr to input ports will be ignored." + severity warning; + end if; + + if ((not HAS_STRATIXV_STYLE_RAM) + and (not HAS_STRATIXIII_STYLE_RAM) + and (read_during_write_mode_port_a /= "NEW_DATA_NO_NBE_READ")) then + assert false + report "Warning: " & read_during_write_mode_port_a & " value for read_during_write_mode_port_a is not supported in " & intended_device_family & " device family, it might cause incorrect behavioural simulation result" + severity warning; + end if; + + if ((not HAS_STRATIXV_STYLE_RAM) + and (not HAS_STRATIXIII_STYLE_RAM) + and (read_during_write_mode_port_b /= "NEW_DATA_NO_NBE_READ")) then + assert false + report "Warning: " & read_during_write_mode_port_b & " value for read_during_write_mode_port_b is not supported in " & intended_device_family & " device family, it might cause incorrect behavioural simulation result" + severity warning; + end if; +-- SPR 249576: Enable don't care as RDW setting in MegaFunctions - eliminates checking for ram_block_type = "AUTO" + if (not (i_is_lutram or ((i_ram_block_type = "AUTO") and (HAS_LUTRAM)) or + ((i_ram_block_type /= "AUTO") and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)))) and + (operation_mode /= "SINGLE_PORT") and (read_during_write_mode_port_a = "DONT_CARE")) then + assert false + report "Error: " & read_during_write_mode_port_a & " value for read_during_write_mode_port_a is not supported in " & + intended_device_family & " device family for " & ram_block_type & " ram block type in " & operation_mode & " operation mode" + severity error; + end if; + + if ((not i_is_lutram) and (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE")) then + assert false + report "Warning : read_during_write_mode_mixed_ports cannot be set to CONSTRAINED_DONT_CARE for non-LUTRAM ram block type. This will cause incorrect simulation result." + severity warning; + end if; + + if ((not i_is_lutram) and (cread_during_write_mode_mixed_ports = "NEW_DATA")) then + assert false + report "Warning : read_during_write_mode_mixed_ports cannot be set to NEW_DATA for non-LUTRAM ram block type. This will cause incorrect simulation result." + severity warning; + end if; + + if ((operation_mode = "DUAL_PORT") and (outdata_reg_b /= "CLOCK0") and (i_is_lutram) and + (cread_during_write_mode_mixed_ports = "OLD_DATA")) then + assert false + report "Warning: Value for read_during_write_mode_mixed_ports is not honoured in " & operation_mode & " operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM" + severity warning; + end if; + + if ((i_is_lutram) and (operation_mode = "BIDIR_DUAL_PORT")) then + assert false + report "Error: LUTRAM RAM block type does not support BIDIR_DUAL_PORT operation mode" + severity error; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (indata_aclr_a /= "NONE") and (indata_aclr_a /= "UNUSED")) then + assert false + report "Warning : " & indata_aclr_a & "value for indata_aclr_a is not supported in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (wrcontrol_aclr_a /= "NONE") and (wrcontrol_aclr_a /= "UNUSED")) then + assert false + report "Warning : " & wrcontrol_aclr_a & " value for wrcontrol_aclr_a is not supported in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (byteena_aclr_a /= "NONE") and (byteena_aclr_a /= "UNUSED")) then + assert false + report "Warning : " & byteena_aclr_a & " value for byteena_aclr_a is not supported in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (address_aclr_a /= "NONE") and (address_aclr_a /= "UNUSED") and (operation_mode /= "ROM")) then + assert false + report "Warning : " & address_aclr_a & " value for address_aclr_a is not supported for write port in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (indata_aclr_b /= "NONE") and (indata_aclr_b /= "UNUSED")) then + assert false + report "Warning : " & indata_aclr_b & " value for indata_aclr_b is not supported in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (rdcontrol_aclr_b /= "NONE") and (rdcontrol_aclr_b /= "UNUSED")) then + assert false + report "Warning : " & rdcontrol_aclr_b & " value for rdcontrol_aclr_b is not supported in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (wrcontrol_aclr_b /= "NONE") and (wrcontrol_aclr_b /= "UNUSED")) then + assert false + report "Warning : " & wrcontrol_aclr_b & " value for wrcontrol_aclr_b is not supported in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (byteena_aclr_b /= "NONE") and (byteena_aclr_b /= "UNUSED")) then + assert false + report "Warning : " & byteena_aclr_b & " value for byteena_aclr_b is not supported in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (address_aclr_b /= "NONE") and (address_aclr_b /= "UNUSED") and (operation_mode = "BIDIR_DUAL_PORT")) then + assert false + report "Warning : " & address_aclr_b & " value for address_aclr_b is not supported for write port in " & intended_device_family & " device family. The aclr to data_a registers will be ignored." + severity warning; + end if; + + if ((i_is_lutram) and (address_aclr_b /= "NONE") and (address_aclr_b /= "UNUSED") and (operation_mode = "DUAL_PORT") and (cread_during_write_mode_mixed_ports = "OLD_DATA")) then + assert false + report "Warning : aclr signal for address_b is ignored for RAM block type " & ram_block_type & " when read_during_write_mode_mixed_ports is set to OLD_DATA" + severity warning; + end if; + + if (((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)) and + ((clock_enable_core_a /= "USE_INPUT_CLKEN") and + (clock_enable_core_a /= clock_enable_input_a))) then + assert false + report "Warning: clock_enable_core_a value must be 'USE_INPUT_CLKEN' or same as clock_enable_input_a in " & intended_device_family & " device family. It will be set to follow clock_enable_input_a value." + severity warning; + end if; + + if (((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)) and + ((clock_enable_core_b /= "USE_INPUT_CLKEN") and (clock_enable_core_b /= clock_enable_input_b))) then + assert false + report "Warning: clock_enable_core_b value must be 'USE_INPUT_CLKEN' or same as clock_enable_input_b in " & intended_device_family & " device family. It will be set to follow clock_enable_input_b value." + severity warning; + end if; + + if ((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM) and + (clock_enable_input_a = "ALTERNATE")) then + assert false + report "Error: ALTERNATE value for clock_enable_input_a is not supported in " & intended_device_family + severity error; + end if; + + if ((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM) and + (clock_enable_input_b = "ALTERNATE")) then + assert false + report "Error: ALTERNATE value for clock_enable_input_b is not supported in " & intended_device_family + severity error; + end if; + + if ((enable_ecc = "TRUE") and (((i_ram_block_type /= "M20K") and (i_ram_block_type /= "M144K")) or (operation_mode /= "DUAL_PORT"))) then + assert false + report "Error: " & enable_ecc & " value for enable_ecc is not supported in " & ram_block_type & " ram block type for " & intended_device_family & " device family in " & operation_mode & " operation mode." + severity error; + end if; + + if ((i_ram_block_type /= "M20K") and (ecc_pipeline_stage_enabled = "TRUE")) then + assert false + report "Error: " & ecc_pipeline_stage_enabled & " value for ecc_pipeline_stage_enabled is not supported in " & ram_block_type & " ram block type." + severity error; + end if; + + if ((outdata_reg_b = "UNREGISTERED") and (ecc_pipeline_stage_enabled = "TRUE")) then + assert false + report "Error: " & ecc_pipeline_stage_enabled & " is not supported when output_reg_b is set to " & outdata_reg_b & " ." + severity error; + end if; + + --Setting this to only warning because in synthesis it will ignore the ecc_pipeline_stage_enabled parameter when enable_ecc is set to false + if ((ecc_pipeline_stage_enabled = "TRUE") and (enable_ecc /= "TRUE")) then + assert false + report "Warning: " & ecc_pipeline_stage_enabled & " value for ecc_pipeline_stage_enabled is not supported when enable_ecc is set to " & enable_ecc & " ." + severity warning; + end if; + + if ((cread_during_write_mode_mixed_ports = "OLD_DATA") and (enable_ecc = "TRUE") and ((i_ram_block_type = "M20K") or (i_ram_block_type = "M144K"))) then + assert false + report "Error : ECC is not supported for read-before-write mode." + severity error; + end if; + + if (((wrcontrol_aclr_a /= "NONE") and (wrcontrol_aclr_a /= "UNUSED")) and (i_ram_block_type = "M512") and (operation_mode = "SINGLE_PORT")) then + assert false + report "Error: Wren_a cannot have clear in single port mode for M512 block" + severity error; + end if; + + if ((operation_mode = "DUAL_PORT") and (numwords_a * width_a /= numwords_b * width_b)) then + assert false + report "Error: Total number of bits of port A and port B should be the same for dual port mode" + severity error; + end if; + + if (((rdcontrol_aclr_b /= "NONE") and (rdcontrol_aclr_b /= "UNUSED")) and (i_ram_block_type = "M512") and (operation_mode = "DUAL_PORT")) then + assert false + report "Error: rden_b cannot have clear in simple dual port mode for M512 block" + severity error; + end if; + + if ((operation_mode = "BIDIR_DUAL_PORT") and (numwords_a * width_a /= numwords_b * width_b)) then + assert false + report "Error: Total number of bits of port A and port B should be the same for bidir dual port mode" + severity error; + end if; + + if ((operation_mode = "BIDIR_DUAL_PORT") and (i_ram_block_type = "M512")) then + assert false + report "Error: M512 block type doesn't support bidir dual mode" + severity error; + end if; + + if (((i_ram_block_type = "M-RAM") or (i_ram_block_type = "MEGARAM")) and + (cread_during_write_mode_mixed_ports = "OLD_DATA")) then + assert false + report "Error: M-RAM doesn't support OLD_DATA value for READ_DURING_WRITE_MODE_MIXED_PORTS parameter" + severity error; + end if; + + if ((not HAS_STRATIXII_STYLE_RAM) and + (clock_enable_input_a = "BYPASS")) then + assert false + report "Error: BYPASS value for CLOCK_ENABLE_INPUT_A is not supported in "& intended_device_family &" device family" + severity error; + end if; + if ((not HAS_STRATIXII_STYLE_RAM) and + (clock_enable_output_a = "BYPASS")) then + assert false + report "Error: BYPASS value for CLOCK_ENABLE_OUTPUT_A is not supported in "& intended_device_family &" device family" + severity error; + end if; + if ((not HAS_STRATIXII_STYLE_RAM) and + (clock_enable_input_b = "BYPASS") and + ((operation_mode = "BIDIR_DUAL_PORT") or (operation_mode = "DUAL_PORT"))) then + assert false + report "Error: BYPASS value for CLOCK_ENABLE_INPUT_B is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not HAS_STRATIXII_STYLE_RAM) and + (clock_enable_output_b = "BYPASS") and + ((operation_mode = "BIDIR_DUAL_PORT") or (operation_mode = "DUAL_PORT"))) then + assert false + report "Error: BYPASS value for CLOCK_ENABLE_OUTPUT_B is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((implement_in_les /= "OFF") and (implement_in_les /= "ON")) then + assert false + report "Error: Illegal parameter value for implement_in_les" + severity error; + end if; + + if ((not HAS_M512) and (i_ram_block_type = "M512")) then + assert false + report "Error: M512 as ram_block_type is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if ((not HAS_MEGARAM) and (i_ram_block_type = "MEGARAM")) then + assert false + report "Error: MEGARAM as ram_block_type is not supported in "& intended_device_family &" device family" + severity error; + end if; + + if (operation_mode /= "DUAL_PORT") then + if ((outdata_reg_a /= "CLOCK0") and (outdata_reg_a /= "CLOCK1") and (outdata_reg_a /= "UNUSED") and (outdata_reg_a /= "UNREGISTERED")) then + assert false + report "Error: " & outdata_reg_a & " value for outdata_reg_a is not supported." + severity error; + end if; + end if; + + if ((operation_mode = "BIDIR_DUAL_PORT") or (operation_mode = "DUAL_PORT")) then + if ((address_reg_b /= "CLOCK0") and (address_reg_b /= "CLOCK1") and (address_reg_b /= "UNUSED")) then + assert false + report "Error: " & address_reg_b & " value for address_reg_b is not supported." + severity error; + end if; + + if ((outdata_reg_b /= "CLOCK0") and (outdata_reg_b /= "CLOCK1") and (outdata_reg_b /= "UNUSED") and (outdata_reg_b /= "UNREGISTERED")) then + assert false + report "Error: " & outdata_reg_b & " value for outdata_reg_b is not supported." + severity error; + end if; + + if ((rdcontrol_reg_b /= "CLOCK0") and (rdcontrol_reg_b /= "CLOCK1") and (rdcontrol_reg_b /= "UNUSED") and (operation_mode = "DUAL_PORT")) then + assert false + report "Error: " & rdcontrol_reg_b & " value for rdcontrol_reg_b is not supported." + severity error; + end if; + + if ((indata_reg_b /= "CLOCK0") and (indata_reg_b /= "CLOCK1") and (indata_reg_b /= "UNUSED") and (operation_mode = "BIDIR_DUAL_PORT")) then + assert false + report "Error: " & indata_reg_b & " value for indata_reg_b is not supported." + severity error; + end if; + + if ((wrcontrol_wraddress_reg_b /= "CLOCK0") and (wrcontrol_wraddress_reg_b /= "CLOCK1") and (wrcontrol_wraddress_reg_b /= "UNUSED") and (operation_mode = "BIDIR_DUAL_PORT")) then + assert false + report "Error: " & wrcontrol_wraddress_reg_b & " value for wrcontrol_wraddress_reg_b is not supported." + severity error; + end if; + + if ((byteena_reg_b /= "CLOCK0") and (byteena_reg_b /= "CLOCK1") and (byteena_reg_b /= "UNUSED") and (operation_mode = "BIDIR_DUAL_PORT")) then + assert false + report "Error: " & byteena_reg_b & " value for byteena_reg_b is not supported." + severity error; + end if; + end if; + wait; + end process; + +-- SIGNAL ASSIGNMENTS + + -- Checking for same clock phase + process (clock0, clock1) + begin + if (rising_edge(clock0)) then + if (clock1 = '1') then + same_clock_pulse0 <= '1'; + else + same_clock_pulse0 <= '0'; + end if; + end if; + if (rising_edge(clock1)) then + if (clock0 = '1') then + same_clock_pulse1 <= '1'; + else + same_clock_pulse1 <= '0'; + end if; + end if; + if (falling_edge(clock0) and (clock1 = '1')) then + same_clock_pulse0 <= '0'; + end if; + if (falling_edge(clock1) and (clock0 = '1')) then + same_clock_pulse1 <= '0'; + end if; + end process; + + + -- Checking ram_block_type and setting default_val + IFG01: if ((((i_ram_block_type = "AUTO") and + ((cread_during_write_mode_mixed_ports = "DONT_CARE") or (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE"))) or + (i_ram_block_type = "MEGARAM") or + (i_ram_block_type = "M-RAM")) and + (operation_mode /= "ROM") and + not (HAS_STRATIXV_STYLE_RAM) and + not (HAS_STRATIXIII_STYLE_RAM)) generate + default_val <= 'X'; + end generate IFG01; + + IFG02: if (not ((((i_ram_block_type = "AUTO") and + ((cread_during_write_mode_mixed_ports = "DONT_CARE") or (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE"))) or + (i_ram_block_type = "MEGARAM") or + (i_ram_block_type = "M-RAM")) and + (operation_mode /= "ROM") and + not (HAS_STRATIXV_STYLE_RAM) and + not (HAS_STRATIXIII_STYLE_RAM))) generate + default_val <= '0'; + end generate IFG02; + + + -- Assigning the correct clock enable signals based on the input clock + + -- for input ports in a + IFG03: if (clock_enable_input_a = "NORMAL") generate + i_inclocken0 <= clocken0; + end generate IFG03; + IFG03a: if (clock_enable_input_a = "BYPASS") generate + i_inclocken0 <= '1'; + end generate IFG03a; + IFG03b: if (clock_enable_input_a = "ALTERNATE") generate + i_inclocken0 <= clocken2; + end generate IFG03b; + + -- for input ports in b + IFG14: if ((address_reg_b = "CLOCK0") and (clock_enable_input_b = "NORMAL")) generate + i_input_clocken_b <= clocken0; + end generate IFG14; + IFG14b: if ((address_reg_b = "CLOCK0") and (clock_enable_input_b = "ALTERNATE")) generate + i_input_clocken_b <= clocken2; + end generate IFG14b; + IFG14a: if (clock_enable_input_b = "BYPASS") generate + i_input_clocken_b <= '1'; + end generate IFG14a; + IFG15: if ((address_reg_b = "CLOCK1") and (clock_enable_input_b = "NORMAL")) generate + i_input_clocken_b <= clocken1; + end generate IFG15; + IFG14c: if ((address_reg_b = "CLOCK1") and (clock_enable_input_b = "ALTERNATE")) generate + i_input_clocken_b <= clocken3; + end generate IFG14c; + + -- for data out a + IFG171: if ((outdata_reg_a = "CLOCK0") and (clock_enable_output_a = "NORMAL")) generate + i_outdata_clken_a <= clocken0; + end generate IFG171; + IFG172b: if ((outdata_reg_a = "CLOCK0") and (clock_enable_output_a = "ALTERNATE")) generate + i_outdata_clken_a <= clocken2; + end generate IFG172b; + IFG172a: if (clock_enable_output_a = "BYPASS") generate + i_outdata_clken_a <= '1'; + end generate IFG172a; + IFG173 : if ((outdata_reg_a = "CLOCK1") and (clock_enable_output_a = "NORMAL")) generate + i_outdata_clken_a <= clocken1; + end generate IFG173; + IFG173a : if ((outdata_reg_a = "CLOCK1") and (clock_enable_output_a = "ALTERNATE")) generate + i_outdata_clken_a <= clocken3; + end generate IFG173a; + + -- case:32394, on SV onwards clear deassertion depends on output clock instead of core clock + IFG171a: if ((clock_enable_output_b = "NORMAL") and (outdata_reg_a = "UNREGISTERED") and (outdata_reg_b = "CLOCK0") and (HAS_STRATIXV_STYLE_RAM) and (operation_mode = "BIDIR_DUAL_PORT")) generate + i_outlatch_clken_a <= clocken0; + end generate IFG171a; + + -- for data out b + IFG17: if ((outdata_reg_b = "CLOCK0") and (clock_enable_output_b = "NORMAL")) generate + i_outdata_clken_b <= clocken0; + end generate IFG17; + IFG17b: if ((outdata_reg_b = "CLOCK0") and (clock_enable_output_b = "ALTERNATE")) generate + i_outdata_clken_b <= clocken2; + end generate IFG17b; + IFG17a: if (clock_enable_output_b = "BYPASS") generate + i_outdata_clken_b <= '1'; + end generate IFG17a; + IFG18 : if ((outdata_reg_b = "CLOCK1") and (clock_enable_output_b = "NORMAL")) generate + i_outdata_clken_b <= clocken1; + end generate IFG18; + IFG18a : if ((outdata_reg_b = "CLOCK1") and (clock_enable_output_b = "ALTERNATE")) generate + i_outdata_clken_b <= clocken3; + end generate IFG18a; + + -- case:32394, on SV onwards clear deassertion depends on output clock instead of core clock + IFG171b: if ((clock_enable_output_a = "NORMAL") and (outdata_reg_b = "UNREGISTERED") and (outdata_reg_a = "CLOCK0") and (address_reg_b = "CLOCK0") and (HAS_STRATIXV_STYLE_RAM) and (operation_mode = "BIDIR_DUAL_PORT")) generate + i_outlatch_clken_b <= clocken0; + end generate IFG171b; + + -- case:32394, on SV onwards clear deassertion depends on output clock instead of core clock + IFG171c: if ((clock_enable_output_a = "NORMAL") and (outdata_reg_b = "UNREGISTERED") and (outdata_reg_a = "CLOCK1") and (address_reg_b = "CLOCK1") and (HAS_STRATIXV_STYLE_RAM) and (operation_mode = "BIDIR_DUAL_PORT")) generate + i_outlatch_clken_b <= clocken1; + end generate IFG171c; + + -- for core clock a + IFG50a: if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_a = "USE_INPUT_CLKEN")) generate + i_core_clocken_a <= i_inclocken0; + end generate IFG50a; + IFG50b: if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_a = "ALTERNATE")) generate + i_core_clocken_a <= clocken2; + end generate IFG50b; + IFG50d: if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_a = "BYPASS")) generate + i_core_clocken_a <= '1'; + end generate IFG50d; + IFG50c: if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_a = "NORMAL")) generate + i_core_clocken_a <= clocken0; + end generate IFG50c; + IFG50e: if ((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)) generate + i_core_clocken_a <= i_inclocken0; + end generate IFG50e; + + -- for core clock b + IFG51a: if ((((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_b = "USE_INPUT_CLKEN")) or + ((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM))) generate + i_core_clocken_b0 <= i_input_clocken_b; + i_core_clocken_b1 <= i_input_clocken_b; + end generate IFG51a; + IFG51e: if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_b = "NORMAL")) generate + i_core_clocken_b0 <= clocken0; + i_core_clocken_b1 <= clocken1; + end generate IFG51e; + IFG51b: if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_b = "ALTERNATE")) generate + i_core_clocken_b0 <= clocken2; + i_core_clocken_b1 <= clocken3; + end generate IFG51b; + IFG51c: if (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (clock_enable_core_b = "BYPASS")) generate + i_core_clocken_b0 <= '1'; + i_core_clocken_b1 <= '1'; + end generate IFG51c; + IFG52a: if (address_reg_b = "CLOCK0") generate + i_core_clocken_b <= i_core_clocken_b0; + end generate IFG52a; + IFG52b: if (address_reg_b = "CLOCK1") generate + i_core_clocken_b <= i_core_clocken_b1; + end generate IFG52b; + + + + -- Assigning the correct clear signals + + -- for data in a + IFG20: if ((indata_aclr_a = "CLEAR0") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_indata_aclr_a <= aclr0; + end generate IFG20; + + -- for address a + IFG22: if ((address_aclr_a = "CLEAR0") and + (not ((((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (operation_mode /= "ROM")) or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_address_aclr_a <= aclr0; + end generate IFG22; + + -- for wren a + IFG24: if ((wrcontrol_aclr_a = "CLEAR0") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_wrcontrol_aclr_a <= aclr0; + end generate IFG24; + + -- for byteena a + IFG26: if ((byteena_aclr_a = "CLEAR0") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_byteena_aclr_a <= aclr0; + end generate IFG26; + IFG27: if ((byteena_aclr_a = "CLEAR1") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_byteena_aclr_a <= aclr1; + end generate IFG27; + + -- for data out a + IFG29: if (outdata_aclr_a = "CLEAR0") generate + i_outdata_aclr_a <= aclr0; + end generate IFG29; + IFG30: if (outdata_aclr_a = "CLEAR1") generate + i_outdata_aclr_a <= aclr1; + end generate IFG30; + + -- for data out b + IFG31a: if (outdata_aclr_b = "CLEAR0") generate + i_outdata_aclr_b <= aclr0; + end generate IFG31a; + IFG31b: if (outdata_aclr_b = "CLEAR1") generate + i_outdata_aclr_b <= aclr1; + end generate IFG31b; + + -- for data in b + IFG32: if ((indata_aclr_b = "CLEAR0") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_indata_aclr_b <= aclr0; + end generate IFG32; + IFG33: if ((indata_aclr_b = "CLEAR1") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_indata_aclr_b <= aclr1; + end generate IFG33; + + -- for address b + IFG35: if ((address_aclr_b = "CLEAR0") and + not (IS_BASE_STRATIXII) and + not (IS_BASE_CYCLONEII) and + not (HAS_STRATIXV_STYLE_RAM) and + not (HAS_STRATIXIII_STYLE_RAM)) generate + i_address_aclr_b <= aclr0; + end generate IFG35; + IFG35a: if ((address_aclr_b = "CLEAR0") and (operation_mode = "DUAL_PORT") and + ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) generate + i_address_aclr_b <= aclr0; + end generate IFG35a; + IFG36: if ((address_aclr_b = "CLEAR1") and + not (IS_BASE_STRATIXII) and + not (IS_BASE_CYCLONEII) and + not ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) generate + i_address_aclr_b <= aclr1; + end generate IFG36; + IFG36a: if ((address_aclr_b = "CLEAR1") and (operation_mode = "DUAL_PORT") and + ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) generate + i_address_aclr_b <= aclr1; + end generate IFG36a; + + -- for wren b + IFG38:if ((wrcontrol_aclr_b = "CLEAR0") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_wrcontrol_aclr_b <= aclr0; + end generate IFG38; + IFG39: if ((wrcontrol_aclr_b = "CLEAR1") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_wrcontrol_aclr_b <= aclr1; + end generate IFG39; + + -- for rden b + IFG41: if ((rdcontrol_aclr_b = "CLEAR0") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_rdcontrol_aclr_b <= aclr0; + end generate IFG41; + IFG42: if ((rdcontrol_aclr_b = "CLEAR1") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_rdcontrol_aclr_b <= aclr1; + end generate IFG42; + + -- for byteena b + IFG44: if ((byteena_aclr_b = "CLEAR0") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_byteena_aclr_b <= aclr0; + end generate IFG44; + IFG45: if ((byteena_aclr_b = "CLEAR1") and (not (HAS_STRATIXV_STYLE_RAM or HAS_STRATIXIII_STYLE_RAM or + (IS_BASE_STRATIXII or IS_BASE_CYCLONEII)))) generate + i_byteena_aclr_b <= aclr1; + end generate IFG45; + + + + -- This process initializes and updates the memory content in the RAM accordingly + MEMORY: process (i_read_flag_a, i_write_flag_a, i_read_flag_b, i_write_flag_b, default_val, i_reread_flag_a, i_reread_flag_b, i_reread_flag2_a, i_reread_flag2_b) + + variable j : integer := 0; + variable port_a_bit_count_low : integer := 0; + variable port_a_bit_count_high : integer := 0; + variable port_b_bit_count_low : integer := 0; + variable port_b_bit_count_high : integer := 0; + variable i_byteena_count : integer := 0; + variable m_mem_data_a : width_a_array; + variable m_mem_data_b : width_b_array; + variable m_temp_wa : std_logic_vector(width_a - 1 downto 0); + variable m_temp_wa2 : std_logic_vector(width_a - 1 downto 0) := (others => 'U'); + variable m_temp_wa3 : std_logic_vector(width_a - 1 downto 0); + variable m_temp_wb : std_logic_vector(width_b - 1 downto 0); + variable m_temp_wb2 : std_logic; + variable m_init_file_b_port : boolean := false; + variable m_temp_wb3 : std_logic_vector(width_a - 1 downto 0); + variable m_current_written_data_b : std_logic_vector(width_b - 1 downto 0); + + variable m_address_a : integer := 0; + variable m_address_b : integer := 0; + variable m_original_address_a : integer := 0; + variable m_data_write_time_a : time := 0 ps; + variable m_q_tmp2_a : std_logic_vector(width_a - 1 downto 0); + variable write_by_a : integer := 0; + variable prev_write_by_a : integer := 0; + + variable write_by_b : integer := 0; + variable prev_write_by_b : integer := 0; + + variable ctime : time := 0 ps; + variable reread_a : boolean := false; + variable reread_b : boolean := false; + variable last_read_a_event : boolean := false; + variable last_read_b_event : boolean := false; + variable need_init_var : boolean := true; + variable m_current_written_data_a : std_logic_vector(width_a - 1 downto 0); + variable m_original_data_a : std_logic_vector(width_a - 1 downto 0); + variable m_original_data_b : std_logic_vector(width_b - 1 downto 0); + variable m_data_a_x : std_logic_vector(width_a - 1 downto 0) := (others => 'X'); + variable m_data_b_x : std_logic_vector(width_b - 1 downto 0) := (others => 'X'); + + begin + if (need_init_var) then + -- Begin of initializations + m_original_data_a := (others => default_val); + m_original_data_b := (others => default_val); + + if (init_file = "UNUSED" or init_file = "NONE" or init_file = "") then + -- No memory file used + if (operation_mode /= "ROM") then + if (( ( (i_ram_block_type = "AUTO") and + ( (cread_during_write_mode_mixed_ports = "DONT_CARE") or + (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE"))) or + IS_HARDCOPYII or + IS_HARDCOPYIII or + IS_HARDCOPYIV or + (i_ram_block_type = "MEGARAM") or (i_ram_block_type = "M-RAM") or + (power_up_uninitialized = "TRUE")) and + (implement_in_les = "OFF") and + not ((((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and (not IS_HARDCOPYIII) and (not IS_HARDCOPYIV) ) + and (power_up_uninitialized /= "TRUE"))) then + + for i in 0 to (2**widthad_a - 1) loop + m_mem_data_a(i) := (others => 'X'); + end loop; + + if (enable_mem_data_b_reading = true) then + for i in 0 to (2**widthad_b - 1) loop + m_mem_data_b(i) := (others => 'X'); + end loop; + end if; + else + + for i in 0 to (2**widthad_a - 1) loop + m_mem_data_a(i) := (others => '0'); + end loop; + + if (enable_mem_data_b_reading = true) then + for i in 0 to (2**widthad_b - 1) loop + m_mem_data_b(i) := (others => '0'); + end loop; + end if; + end if; + + end if; + else + -- Using memory file to initialize memory content + if (( ((i_ram_block_type = "AUTO") and + ( (cread_during_write_mode_mixed_ports = "DONT_CARE") or + (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE"))) or + IS_HARDCOPYII or + (power_up_uninitialized = "TRUE") or + (i_ram_block_type = "MEGARAM") or + (i_ram_block_type = "M-RAM")) and + not (HAS_STRATIXV_STYLE_RAM) and + not (HAS_STRATIXIII_STYLE_RAM) and + (operation_mode /= "ROM") ) then + for i in 0 to (2 ** widthad_a - 1) loop + m_mem_data_a(i) := (others => 'X'); + end loop; + + if (enable_mem_data_b_reading = true) then + for i in 0 to (2**widthad_b - 1) loop + m_mem_data_b(i) := (others => 'X'); + end loop; + end if; + else + for i in 0 to (2 ** widthad_a - 1) loop + m_mem_data_a(i) := (others => '0'); + end loop; + + if (enable_mem_data_b_reading = true) then + for i in 0 to (2**widthad_b - 1) loop + m_mem_data_b(i) := (others => '0'); + end loop; + end if; + end if; + + if (init_file_layout = "UNUSED") then + if (operation_mode = "DUAL_PORT") then + m_init_file_b_port := true; + else + m_init_file_b_port := false; + end if; + else + if (init_file_layout = "PORT_A") then + m_init_file_b_port := false; + elsif (init_file_layout = "PORT_B") then + m_init_file_b_port := true; + end if; + end if; + + if (m_init_file_b_port) then + read_my_memory (false, m_mem_data_a, m_mem_data_b); + + for i in 0 to (i_numwords_b * width_b - 1) loop + m_temp_wb := m_mem_data_b(i / width_b); + m_temp_wb2 := m_temp_wb((i)mod width_b); + m_temp_wa := m_mem_data_a(i / width_a); + m_temp_wa(i mod width_a) := m_temp_wb2; + m_mem_data_a(i / width_a) := m_temp_wa; + end loop; + else + read_my_memory (true, m_mem_data_a, m_mem_data_b); + + if (enable_mem_data_b_reading = true) then + for i in 0 to (i_numwords_a * width_a - 1) loop + m_temp_wa := m_mem_data_a(i / width_a); + m_temp_wb2 := m_temp_wa((i)mod width_a); + m_temp_wb := m_mem_data_b(i / width_b); + m_temp_wb(i mod width_b) := m_temp_wb2; + m_mem_data_b(i / width_b) := m_temp_wb; + end loop; + end if; + end if; + end if; + + if (i_is_lutram) then + if (operation_mode = "DUAL_PORT") then + for i in 0 to (width_b - 1) loop + m_temp_wa2 := m_mem_data_a(i / width_a); + m_temp_wb(i) := m_temp_wa2(i mod width_a); + end loop; + i_q_tmp2_b <= m_temp_wb; + end if; + + if ((operation_mode = "SINGLE_PORT") or (operation_mode = "ROM")) then + i_q_tmp2_a <= m_mem_data_a(0); + end if; + + end if; + + need_init_var := false; + + -- End of initializations + + end if; + + -- Port A writing + if ((rising_edge(i_write_flag_a) or falling_edge(i_write_flag_a)) and (need_init_var = false)) then + if ((write_operation_a) and (i_good_to_write_a = '1')) then + m_original_data_a := m_mem_data_a(conv_integer(unsigned(i_address_reg_a))); + i_original_data_a <= m_mem_data_a(conv_integer(unsigned(i_address_reg_a))); + + if (i_wren_reg_a = '1') then + if ((i_address_aclr_a = '1') and (conv_integer(unsigned(i_address_reg_a)) /= 0)) then + for i in 0 to (i_numwords_a - 1) loop + m_mem_data_a(i) := (others => 'X'); + end loop; + + if (enable_mem_data_b_reading = true) then + for i in 0 to (i_numwords_b - 1) loop + m_mem_data_b(i) := (others => 'X'); + end loop; + end if; + elsif (((i_indata_aclr_a = '1') and (i_data_reg_a /= i_data_zero_a)) or + ((i_byteena_aclr_a = '1') and (i_byteena_mask_reg_a /= i_data_ones_a)) or + ((i_wrcontrol_aclr_a = '1') and (i_wren_reg_a /= '0'))) then + m_mem_data_a (conv_integer(unsigned(i_address_reg_a))) := (others => 'X'); + + j := conv_integer(unsigned(i_address_reg_a)) * width_a; + + if (enable_mem_data_b_reading = true) then + for i in 0 to (width_a - 1) loop + m_temp_wb := m_mem_data_b((j + i) / width_b); + m_temp_wb((j + i) mod width_b) := 'X'; + m_mem_data_b((j + i) / width_b) := m_temp_wb; + end loop; + end if; + else + port_a_bit_count_low := (conv_integer(unsigned(i_address_reg_a)) * width_a); + port_b_bit_count_low := (conv_integer(unsigned(i_address_reg_b)) * width_b); + port_b_bit_count_high := ((conv_integer(unsigned(i_address_reg_b)) * width_b) + width_b); + m_temp_wa := m_mem_data_a(conv_integer(unsigned(i_address_reg_a))); + + for i in 0 to (width_a - 1) loop + port_a_bit_count_high := port_a_bit_count_low + i; + i_byteena_count := port_a_bit_count_high mod width_b; + + if ((port_a_bit_count_high >= port_b_bit_count_low) and (port_a_bit_count_high < port_b_bit_count_high)) then + if ((i_core_clocken_b_reg = '1') and (i_wren_reg_b = '1') and ((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and + (i_byteena_mask_reg_b(i_byteena_count) = '1') and (i_byteena_mask_reg_a(i) = '1') and i_write_flag_b'event) then + m_temp_wa(i) := 'X'; + elsif (i_byteena_mask_reg_a(i) = '1') then + m_temp_wa(i) := i_data_reg_a(i); + end if; + elsif (i_byteena_mask_reg_a(i) = '1') then + m_temp_wa(i) := i_data_reg_a(i); + end if; + + if (enable_mem_data_b_reading = true) then + m_temp_wb := m_mem_data_b(port_a_bit_count_high / width_b); + m_temp_wb(port_a_bit_count_high mod width_b) := m_temp_wa(i); + m_mem_data_b(port_a_bit_count_high / width_b) := m_temp_wb; + end if; + end loop; + + m_mem_data_a (conv_integer(unsigned(i_address_reg_a))) := m_temp_wa; + m_original_address_a := conv_integer(unsigned(i_address_reg_a)); + m_data_write_time_a := now; + write_by_a := write_by_a + 1; + end if; + end if; + + m_current_written_data_a := m_mem_data_a(conv_integer(unsigned(i_address_reg_a))); + i_current_written_data_a <= m_mem_data_a(conv_integer(unsigned(i_address_reg_a))); + end if; + end if; + + -- Port B writing + if ((rising_edge(i_write_flag_b) or falling_edge(i_write_flag_b)) and (need_init_var = false)) then + if ((write_operation_b) and (i_good_to_write_b = '1')) then + + j := conv_integer(unsigned(i_address_reg_b)) * width_b; + for i in 0 to (width_b - 1) loop + m_temp_wb3 := m_mem_data_a((j + i) / width_a); + m_original_data_b(i) := m_temp_wb3((j + i) mod width_a); + i_original_data_b(i) <= m_temp_wb3((j + i) mod width_a); + end loop; + + if (i_wren_reg_b = '1') then + if ((i_wrcontrol_aclr_b = '1') and (conv_integer(unsigned(i_address_reg_b)) /= 0)) then + for i in 0 to (i_numwords_a - 1) loop + m_mem_data_a(i) := (others => 'X'); + end loop; + + if (enable_mem_data_b_reading = true) then + for i in 0 to (i_numwords_b - 1) loop + m_mem_data_b(i) := (others => 'X'); + end loop; + end if; + elsif (((i_byteena_aclr_b = '1') and (i_byteena_mask_reg_b /= i_data_ones_b)) or + ((i_indata_aclr_b = '1') and (i_data_reg_b /= i_data_zero_b)) or + ((i_wrcontrol_aclr_b = '1') and (i_wren_reg_b /= '0'))) then + + if (width_a = width_b) then + j := conv_integer(unsigned(i_address_reg_b)); + m_mem_data_a(j) := (others => 'X'); + else + j := conv_integer(unsigned(i_address_reg_b)) * width_b; + for i in 0 to (width_b - 1) loop + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wa2((j + i) mod width_a) := 'X'; + m_mem_data_a((j + i) / width_a) := m_temp_wa2; + end loop; + end if; + + if (enable_mem_data_b_reading = true) then + m_mem_data_b(conv_integer(unsigned(i_address_reg_b))) := (others => 'X'); + end if; + else + + port_b_bit_count_low := (conv_integer(unsigned(i_address_reg_b)) * width_b); + port_a_bit_count_low := (conv_integer(unsigned(i_address_reg_a)) * width_a); + port_a_bit_count_high := (conv_integer(unsigned(i_address_reg_a)) * width_a) + width_a; + + for i in 0 to (width_b - 1) loop + port_b_bit_count_high := port_b_bit_count_low + i; + m_temp_wa2 := m_mem_data_a((port_b_bit_count_high) / width_a); + if ((port_b_bit_count_high >= port_a_bit_count_low) and (port_b_bit_count_high < port_a_bit_count_high) and + (i_core_clocken_a_reg = '1') and (i_wren_reg_a = '1') and ((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and + (i_byteena_mask_reg_a((port_b_bit_count_high) mod width_a) = '1') and (i_byteena_mask_reg_b(i) = '1') and i_write_flag_a'event) then + m_temp_wa2((port_b_bit_count_high) mod width_a) := 'X'; + elsif (i_byteena_mask_reg_b(i) = '1') then + m_temp_wa2((port_b_bit_count_high) mod width_a) := i_data_reg_b(i); + end if; + + m_mem_data_a((port_b_bit_count_high) / width_a) := m_temp_wa2; + + m_current_written_data_b(i) := m_temp_wa2((port_b_bit_count_high) mod width_a); + m_temp_wb(i) := m_temp_wa2((port_b_bit_count_high) mod width_a); + end loop; + + if (enable_mem_data_b_reading = true) then + m_mem_data_b (conv_integer(unsigned(i_address_reg_b))) := m_temp_wb; + end if; + write_by_b := write_by_b + 1; + end if; -- end of choice selection + end if; -- i_wren_reg_b = '1' + + end if;-- write_operation_b + end if; -- i_write_flag_b'event + + -- To ensure that the model will reread port if two event (read & write) event triggered + -- at the different time quantum + reread_a := false; + reread_b := false; + if (ctime /= 0 ps) and (ctime = now) and + ((i_write_flag_a'event) or + (i_write_flag_b'event)) then + if last_read_a_event then + reread_a := true; + end if; + if last_read_b_event then + reread_b := true; + end if; + end if; + + if (i_write_flag_a'event and i_lutram_dual_port_fast_read) then + reread_b := true; + end if; + + last_read_a_event := i_read_flag_a'event; + last_read_b_event := i_read_flag_b'event; + ctime := now; + + + -- Port A reading + if ((rising_edge(i_read_flag_a) or falling_edge(i_read_flag_a)) or (reread_a) or + rising_edge(i_reread_flag_a) or falling_edge(i_reread_flag_a) or rising_edge(i_reread_flag2_a) or falling_edge(i_reread_flag2_a)) then + if (write_by_a /= prev_write_by_a) then + prev_write_by_a := write_by_a; + end if; + + if (read_operation_a) then + if (i_rden_reg_a = '1') then + m_address_a := conv_integer(unsigned(i_address_reg_a)); + + if (i_wren_reg_a = '1') then + if (i_core_clocken_a = '1') then + if (read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ") then + if (i_is_lutram and (clock0 = '1')) then + m_q_tmp2_a := m_mem_data_a(m_address_a); + else + m_q_tmp2_a := ((i_data_reg_a and i_byteena_mask_reg_a) or (m_data_a_x and not i_byteena_mask_reg_a)); + end if; + elsif (read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ") then + if (i_is_lutram and (clock0 = '1')) then + m_q_tmp2_a := m_mem_data_a(m_address_a); + else + m_q_tmp2_a := ((i_data_reg_a and i_byteena_mask_reg_a) or (m_mem_data_a(m_address_a) and not i_byteena_mask_reg_a)) xor i_byteena_mask_reg_a_x; + end if; + elsif (read_during_write_mode_port_a = "OLD_DATA") then + m_q_tmp2_a := m_original_data_a; + else + m_q_tmp2_a := i_data_reg_a xor i_byteena_mask_reg_a_out; + if ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) then + m_q_tmp2_a := (others => 'X'); + end if; + end if; + end if; + + if (i_lutram_single_port_fast_read) then + m_q_tmp2_a := m_mem_data_a(m_address_a); + end if; + else + + m_address_a := conv_integer(unsigned(i_address_reg_a)); + m_q_tmp2_a := m_mem_data_a(m_address_a); + + -- This is to output an "X" when the other port is writing into the same location + -- when read_during_write_mode_mixed_ports = "DONT_CARE" + + if (((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and (is_write_positive_edge)) then + if ((i_wren_reg_b = '1') and + (((i_core_clocken_b = '1') and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) or + ((i_input_clocken_b = '1') and (not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)))) then + + m_address_b := conv_integer(unsigned(i_address_reg_b)); + + if (width_a = width_b) then + if (m_address_b = m_address_a) then + if (cread_during_write_mode_mixed_ports = "OLD_DATA") then + m_q_tmp2_a := m_original_data_b; + else + m_q_tmp2_a := m_q_tmp2_a xor i_byteena_mask_reg_b_out_a; + end if; + end if; + else + + for i in (m_address_a * width_a) to ((m_address_a * width_a) + width_a - 1) loop + if ((i >= (m_address_b * width_b)) and (i <= ((m_address_b * width_b) + width_b - 1))) then + j := i - (m_address_a * width_a); + i_byteena_count := i - (m_address_b * width_b); + + if (cread_during_write_mode_mixed_ports = "OLD_DATA") then + m_q_tmp2_a(j) := m_original_data_b(i_byteena_count); + else + m_q_tmp2_a(j) := m_q_tmp2_a(j) xor i_byteena_mask_reg_b_out_a(i_byteena_count); + end if; + end if; + end loop; + end if; + end if; + end if; + end if; + + if (conv_integer(unsigned(i_address_reg_a)) >= i_numwords_a) then + if ((i_wren_reg_a = '0') or (i_core_clocken_a = '0')) then + i_q_tmp2_a <= (others => 'X'); + else + i_q_tmp2_a <= m_q_tmp2_a; + end if; + assert false + report "Address pointed at port A is out of bound! " + severity warning; + else + + if (((HAS_STRATIXV_STYLE_RAM) or (IS_CYCLONEIII)) and + (((outdata_aclr_a = "CLEAR0") and (aclr0 = '1')) or + ((outdata_aclr_a = "CLEAR1") and (aclr1 = '1'))) and + (outdata_reg_a = "UNREGISTERED")) then + i_q_tmp2_a <= (others => '0'); + else + i_q_tmp2_a <= m_q_tmp2_a; + end if; + + if (i_is_lutram and (i_address_aclr_a = '1') and (operation_mode = "ROM")) then + i_q_tmp2_a <= m_mem_data_a(0); + end if; + end if; + + else + if (((HAS_STRATIXV_STYLE_RAM) or (IS_CYCLONEIII)) and + (not i_is_lutram) and + (((outdata_aclr_a = "CLEAR0") and (aclr0 = '1')) or + ((outdata_aclr_a = "CLEAR1") and (aclr1 = '1'))) and + (outdata_reg_a /= "CLOCK0") and (outdata_reg_a /= "CLOCK1")) then + i_q_tmp2_a <= (others => '0'); + end if; + + end if; + end if; -- end read_operation_a + + end if; + + -- Port B reading + if ((rising_edge(i_read_flag_b) or falling_edge(i_read_flag_b)) or (reread_b) or + rising_edge(i_reread_flag_b) or falling_edge(i_reread_flag_b) or rising_edge(i_reread_flag2_b) or falling_edge(i_reread_flag2_b)) then + + if (write_by_b /= prev_write_by_b) then + prev_write_by_b := write_by_b; + end if; + + if (read_operation_b) then + if (i_rden_reg_b = '1') then + m_address_a := conv_integer(unsigned(i_address_reg_a)); + m_address_b := conv_integer(unsigned(i_address_reg_b)); + + -- No address conversion calculation if width_a is equals to width_b + if (width_a = width_b) then + + if (i_wren_reg_b = '1') then + if (i_core_clocken_b = '1') then + if (read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ") then + i_q_tmp2_b <= ((i_data_reg_b and i_byteena_mask_reg_b) or + (m_data_b_x and not i_byteena_mask_reg_b)); + elsif (read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ") then + i_q_tmp2_b <= ((i_data_reg_b and i_byteena_mask_reg_b) or (m_mem_data_a(m_address_b) and + not i_byteena_mask_reg_b)) xor i_byteena_mask_reg_b_x; + elsif (read_during_write_mode_port_b = "OLD_DATA") then + i_q_tmp2_b <= m_original_data_b; + else + i_q_tmp2_b <= (others => 'X'); + end if; + end if; + elsif (((m_data_write_time_a = now) and (operation_mode = "DUAL_PORT") and + (not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM))) then + if ((m_address_a = m_address_b) and (m_address_a = m_original_address_a)) then + if (address_reg_b /= "CLOCK0") then + i_q_tmp2_b <= m_mem_data_a(m_address_b) xor i_byteena_mask_reg_a_out_b; + elsif (cread_during_write_mode_mixed_ports = "OLD_DATA") then + i_q_tmp2_b <= m_original_data_a; + elsif ((cread_during_write_mode_mixed_ports = "DONT_CARE") or (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE")) then + + i_q_tmp2_b <= m_mem_data_a(m_address_b) xor i_byteena_mask_reg_a_out_b; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + else + if (m_address_a = m_address_b) then + if (i_is_lutram) then + if (((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and (is_write_positive_edge)) then + if ((i_wren_reg_a = '1') and + (((i_core_clocken_a = '1') and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) or + ((i_inclocken0 = '1') and (not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)))) then + if ((cread_during_write_mode_mixed_ports = "OLD_DATA") and (outdata_reg_b = "CLOCK0")) then + i_q_tmp2_b <= m_mem_data_a(m_address_b); + else + i_q_tmp2_b <= m_current_written_data_a; + end if; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + elsif ((i_ram_block_type = "MEGARAM") or + (i_ram_block_type = "M-RAM") or + (((cread_during_write_mode_mixed_ports = "DONT_CARE") or (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE")) and (i_ram_block_type = "AUTO"))) then + if (((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and (is_write_positive_edge)) then + if ((i_wren_reg_a = '1') and + (((i_core_clocken_a = '1') and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) or + ((i_inclocken0 = '1') and (not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)))) then + i_q_tmp2_b <= m_mem_data_a(m_address_b) xor i_byteena_mask_reg_a_out_b; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + else + if (((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and (is_write_positive_edge)) then + if ((i_wren_reg_a = '1') and + (((i_core_clocken_a = '1') and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) or + ((i_inclocken0 = '1') and (not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM))) and + (is_write_positive_edge)) then + if (cread_during_write_mode_mixed_ports = "OLD_DATA") then + i_q_tmp2_b <= m_original_data_a; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b) xor i_byteena_mask_reg_a_out_b; + end if; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + end if; + else + i_q_tmp2_b <= m_mem_data_a(m_address_b); + end if; + end if; + + else + + j := m_address_b * width_b; + + for i in 0 to (width_b - 1) loop + + if (i_wren_reg_b = '1') then + if (read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ") then + m_temp_wb(i) := ((i_data_reg_b(i) and i_byteena_mask_reg_b(i)) or + (m_data_b_x(i) and not i_byteena_mask_reg_b(i))); + elsif (read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ") then + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := ((i_data_reg_b(i) and i_byteena_mask_reg_b(i)) or (m_temp_wa2((j + i) mod width_a) and not i_byteena_mask_reg_b(i))) xor i_byteena_mask_reg_b_x(i); + elsif (read_during_write_mode_port_b = "OLD_DATA") then + m_temp_wb(i) := m_original_data_b(i); + else + m_temp_wb(i) := 'X'; + end if; + elsif ((m_data_write_time_a = now) and (operation_mode = "DUAL_PORT") and + (not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)) then + if ((m_address_a = ((j + i) / width_a)) and (m_address_a = m_original_address_a)) then + if (address_reg_b /= "CLOCK0") then + m_temp_wa2 := (m_mem_data_a((j + i) / width_a)) xor i_byteena_mask_reg_a_out_b; + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + elsif (cread_during_write_mode_mixed_ports = "OLD_DATA") then + m_temp_wb(i) := m_original_data_a((j + i) mod width_a); + elsif ((cread_during_write_mode_mixed_ports = "DONT_CARE") or (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE"))then + m_temp_wa2 := (m_mem_data_a((j + i) / width_a)) xor i_byteena_mask_reg_a_out_b; + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + else + if (((j + i) / width_a) = m_address_a) then + if (i_is_lutram) then + if (((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and (is_write_positive_edge)) then + if ((i_wren_reg_a = '1') and + (((i_core_clocken_a = '1') and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) or + ((i_inclocken0 = '1') and (not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)))) then + if ((cread_during_write_mode_mixed_ports = "OLD_DATA") and (outdata_reg_b = "CLOCK0")) then + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + else + m_temp_wb(i) := m_current_written_data_a((j + i) mod width_a); + end if; + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + elsif ((i_ram_block_type = "MEGARAM") or (i_ram_block_type = "M-RAM") or + (((cread_during_write_mode_mixed_ports = "DONT_CARE") or (cread_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE")) and + (i_ram_block_type = "AUTO"))) then + if (((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and (is_write_positive_edge)) then + if ((i_wren_reg_a = '1') and + (((i_core_clocken_a = '1') or (i_inclocken0 = '1')) and + ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)))) then + m_temp_wa2 := (m_mem_data_a((j + i) / width_a)) xor i_byteena_mask_reg_a_out_b; + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + else + if (((address_reg_b = "CLOCK0") or (same_clock_pulse0 = '1' and same_clock_pulse1 = '1')) and (is_write_positive_edge)) then + if ((i_wren_reg_a = '1') and + (((i_core_clocken_a = '1') or (i_inclocken0 = '1')) and + ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) and + (is_write_positive_edge)) then + if (cread_during_write_mode_mixed_ports = "OLD_DATA") then + m_temp_wb(i) := m_original_data_a((j + i) mod width_a); + else + m_temp_wa2 := (m_mem_data_a((j + i) / width_a)) xor i_byteena_mask_reg_a_out_b; + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + end if; + else + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end if; + end if; + end loop; + + i_q_tmp2_b <= m_temp_wb; + end if; + end if; + + if (i_is_lutram and (i_address_aclr_b = '1') and operation_mode = "DUAL_PORT") then + for i in 0 to (width_b - 1) loop + m_temp_wa2 := m_mem_data_a(i / width_a); + m_temp_wb(i) := m_temp_wa2(i mod width_a); + end loop; + i_q_tmp2_b <= m_temp_wb; + elsif (i_is_lutram and operation_mode = "DUAL_PORT") then + j := m_address_b * width_b; + + for i in 0 to (width_b - 1) loop + m_temp_wa2 := m_mem_data_a((j + i) / width_a); + m_temp_wb(i) := m_temp_wa2((j + i) mod width_a); + end loop; + i_q_tmp2_b <= m_temp_wb; + end if; + + if ((((outdata_aclr_b = "CLEAR0") and (aclr0 = '1')) or ((outdata_aclr_b = "CLEAR1") and (aclr1 = '1'))) and + (outdata_reg_b /= "CLOCK0") and (outdata_reg_b /= "CLOCK1") and + (((HAS_STRATIXV_STYLE_RAM) or (IS_CYCLONEIII)) and + (not i_is_lutram))) then + i_q_tmp2_b <= (others => '0'); + end if; + end if; + end if; + + end process memory; + + + -- Port A inputs registered : indata, address, byeteena, wren + process (clock0) + variable m_byteena_mask_reg_a : std_logic_vector(width_a - 1 downto 0); + variable m_byteena_mask_reg_a_out : std_logic_vector(width_a - 1 downto 0); + variable m_byteena_mask_reg_a_x : std_logic_vector(width_a - 1 downto 0):= (others => '0'); + variable m_indata_reg_aclr_a : std_logic := '0'; + variable m_wren_reg_aclr_a : std_logic := '0'; + variable m_byteena_reg_aclr_a : std_logic := '0'; + variable m_address_reg_aclr_a : std_logic := '0'; + variable m_byteena_mask_reg_a_out_b : std_logic_vector(width_a - 1 downto 0); + variable need_init_var : boolean := true; + begin + + if (need_init_var = true) then + if ((IS_HARDCOPYII) and + (ram_block_type = "M4K") and (operation_mode /= "SINGLE_PORT") and (clock0 = '1')) then + i_good_to_write_b <= '0'; + end if; + + need_init_var := false; + end if; + + if (rising_edge(clock0)) then + + if (i_address_aclr_a = '1') then + i_address_reg_a <= (others => '0'); + end if; + + if (i_force_reread_a = '1' and (i_outlatch_clken_a = '1')) then + i_force_reread_signal_a <= not i_force_reread_signal_a; + end if; + + i_core_clocken_a_reg <= i_core_clocken_a; + + if (i_core_clocken_a = '1') then + if (i_force_reread_a1 = '1') then + i_force_reread_signal_a <= not i_force_reread_signal_a; + end if; + + if ((HAS_STRATIXV_STYLE_RAM or IS_STRATIXIII) and (not i_is_lutram)) then + + good_to_go_a <= '1'; + + if (i_wrcontrol_aclr_a = '1') then + i_wren_reg_a <= '0'; + else + i_wren_reg_a <= wren_a; + end if; + + i_rden_reg_a <= rden_a; + + end if; + + if ((not i_is_lutram) and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) then + i_read_flag_a <= not i_read_flag_a; + end if; + + if ((is_write_positive_edge) and ((wren_a = '1') or (i_wren_reg_a = '1'))) then + i_write_flag_a <= not i_write_flag_a; + end if; + + if (operation_mode /= "ROM") then + i_nmram_write_a <= '1'; + end if; + else + if (operation_mode /= "ROM") then + i_nmram_write_a <= '0'; + end if; + end if; + + if (i_is_lutram) then + if (i_wrcontrol_aclr_a = '1') then + i_wren_reg_a <= '0'; + elsif (i_core_clocken_a = '1') then + i_wren_reg_a <= wren_a; + end if; + end if; + + if (((clock_enable_input_a = "NORMAL") and (clocken0 = '1')) or + ((clock_enable_input_a = "ALTERNATE") and (clocken2 = '1')) or + (clock_enable_input_a = "BYPASS")) then + + if (((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)) or i_is_lutram) then + i_read_flag_a <= not i_read_flag_a; + end if; + + if (i_indata_aclr_a = '1') then + i_data_reg_a <= (others => '0'); + else + i_data_reg_a <= data_a; + end if; + + if (((not HAS_STRATIXV_STYLE_RAM) and (not IS_STRATIXIII)) or (i_is_lutram)) then + + good_to_go_a <= '1'; + + if (i_wrcontrol_aclr_a = '1') then + i_wren_reg_a <= '0'; + else + i_wren_reg_a <= wren_a; + end if; + + i_rden_reg_a <= rden_a; + + end if; + + if (i_byteena_aclr_a = '1') then + m_byteena_mask_reg_a := (others => '1'); + m_byteena_mask_reg_a_out := (others => '0'); + m_byteena_mask_reg_a_out_b := (others => 'X'); + else + if (width_byteena_a = 1) then + m_byteena_mask_reg_a := (others => byteena_a(0)); + if (byteena_a(0) = '1') then + m_byteena_mask_reg_a_out := (others => '0'); + m_byteena_mask_reg_a_x := (others => '0'); + m_byteena_mask_reg_a_out_b := (others => 'X'); + elsif (byteena_a(0) = '0') then + m_byteena_mask_reg_a_x := (others => '0'); + m_byteena_mask_reg_a_out := (others => 'X'); + m_byteena_mask_reg_a_out_b := (others => '0'); + else + m_byteena_mask_reg_a_x := (others => 'X'); + m_byteena_mask_reg_a_out := (others => 'X'); + m_byteena_mask_reg_a_out_b := (others => 'X'); + end if; + + else + for k in 0 to (width_a - 1) loop + m_byteena_mask_reg_a(k) := byteena_a(k / i_byte_size); + if (m_byteena_mask_reg_a(k) = '1') then + m_byteena_mask_reg_a_out(k) := '0'; + m_byteena_mask_reg_a_x(k) := '0'; + m_byteena_mask_reg_a_out_b(k) := 'X'; + elsif (m_byteena_mask_reg_a(k) = '0') then + m_byteena_mask_reg_a_x(k) := '0'; + m_byteena_mask_reg_a_out(k) := 'X'; + m_byteena_mask_reg_a_out_b(k) := '0'; + else + m_byteena_mask_reg_a_out(k) := 'X'; + m_byteena_mask_reg_a_x(k) := 'X'; + m_byteena_mask_reg_a_out_b(k) := 'X'; + end if; + end loop; + end if; + end if; + + i_byteena_mask_reg_a_out <= m_byteena_mask_reg_a_out; + i_byteena_mask_reg_a <= m_byteena_mask_reg_a; + i_byteena_mask_reg_a_x <= m_byteena_mask_reg_a_x; + i_byteena_mask_reg_a_out_b <= m_byteena_mask_reg_a_out_b; + + if (i_address_aclr_a = '1') then + i_address_reg_a <= (others => '0'); + elsif (addressstall_a /= '1') then + i_address_reg_a <= address_a; + end if; + end if; + + end if; + + if (falling_edge(clock0)) then + + if (i_core_clocken_a = '1') then + i_good_to_write_b <= '1'; + end if; + + if (not is_write_positive_edge) then + if (i_nmram_write_a = '1') then + i_write_flag_a <= not i_write_flag_a; + if (i_is_lutram) then + i_read_flag_a <= not i_read_flag_a; + end if; + end if; + end if; + end if; + + end process; + + IFCLR01 : if ((HAS_STRATIXV_STYLE_RAM) or (IS_CYCLONEIII)) generate + process (i_outdata_aclr_a) + begin + if ((outdata_reg_a /= "CLOCK0") and (outdata_reg_a /= "CLOCK1")) then + if (rising_edge(i_outdata_aclr_a)) then + i_reread_flag_a <= not i_reread_flag_a; + end if; + end if; + end process; + + process (i_outdata_aclr_b) + begin + if ((outdata_reg_b /= "CLOCK0") and (outdata_reg_b /= "CLOCK1")) then + if (rising_edge(i_outdata_aclr_b)) then + i_reread_flag_b <= not i_reread_flag_b; + end if; + end if; + end process; + end generate IFCLR01; + + IFCLR02 : if (i_is_lutram and (operation_mode = "DUAL_PORT")) generate + process (i_address_aclr_b) + begin + if (rising_edge(i_address_aclr_b)) then + i_reread_flag2_b <= not i_reread_flag2_b; + end if; + end process; + end generate IFCLR02; + + IFCLR03 : if (i_is_lutram and (operation_mode = "ROM")) generate + process (i_address_aclr_a) + begin + if (rising_edge(i_address_aclr_a)) then + i_reread_flag2_a <= not i_reread_flag2_a; + end if; + end process; + end generate IFCLR03; + + + -- Port B address input registered (for dual_port mode) + IFG48: if (((address_reg_b = "CLOCK0") or (address_reg_b = "CLOCK1")) and + (operation_mode = "DUAL_PORT")) generate + process (clock0, clock1, i_address_aclr_b) + variable need_init_var : boolean := true; + begin + + if (need_init_var = true) then + if ((IS_HARDCOPYII) and + (ram_block_type = "M4K") and (operation_mode /= "SINGLE_PORT") and + (((address_reg_b = "CLOCK0") and (clock0 = '1')) or ((address_reg_b = "CLOCK1") and (clock1 = '1')))) then + i_good_to_write_a <= '0'; + end if; + + need_init_var := false; + end if; + + if (rising_edge(i_address_aclr_b)) then + if (i_address_aclr_b = '1') then + if (i_is_lutram) then + i_address_reg_b <= (others => '0'); + i_read_flag_b <= not i_read_flag_b; + end if; + end if; + end if; + + if ((rising_edge(clock0) and (address_reg_b = "CLOCK0")) or + (rising_edge(clock1) and (address_reg_b = "CLOCK1"))) then + + i_core_clocken_b_reg <= i_core_clocken_b; + + if (i_force_reread_b = '1' and (i_outlatch_clken_b = '1')) then + i_force_reread_signal_b <= not i_force_reread_signal_b; + end if; + + if (i_address_aclr_b = '1') then + i_address_reg_b <= (others => '0'); + end if; + + if (i_core_clocken_b = '1') then + if (i_force_reread_b1 = '1') then + i_force_reread_signal_b <= not i_force_reread_signal_b; + end if; + if ((HAS_STRATIXV_STYLE_RAM or IS_STRATIXIII) and not i_is_lutram) then + good_to_go_b <= '1'; + + if (i_rdcontrol_aclr_b = '1') then + i_rden_reg_b <= '1'; + else + i_rden_reg_b <= rden_b; + end if; + end if; + end if; + + if (i_input_clocken_b = '1') then + + if (((not HAS_STRATIXV_STYLE_RAM) and (not IS_STRATIXIII)) or i_is_lutram) then + good_to_go_b <= '1'; + + if (i_rdcontrol_aclr_b = '1') then + i_rden_reg_b <= '1'; + else + i_rden_reg_b <= rden_b; + end if; + end if; + + if (i_indata_aclr_b = '1') then + i_data_reg_b <= (others => '0'); + else + i_data_reg_b <= data_b; + end if; + + if (i_address_aclr_b = '1') then + i_address_reg_b <= (others => '0'); + elsif (addressstall_b /= '1') then + i_address_reg_b <= address_b; + end if; + + end if; + + if (not i_lutram_dual_port_fast_read and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) then + if (i_core_clocken_b = '1') then + i_read_flag_b <= not i_read_flag_b; + end if; + elsif (((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)) or (i_is_lutram)) then + if (i_input_clocken_b = '1') then + i_read_flag_b <= not i_read_flag_b; + end if; + end if; + + end if; + + if (((i_is_lutram) and + (i_lutram_dual_port_fast_read)) and + falling_edge(clock0)) then + if (i_core_clocken_b = '1') then + i_read_flag_b <= not i_read_flag_b; + end if; + end if; + + if ((falling_edge(clock0) and (address_reg_b = "CLOCK0")) or + (falling_edge(clock1) and (address_reg_b = "CLOCK1"))) then + if (i_core_clocken_b = '1') then + i_good_to_write_a <= '1'; + end if; + end if; + + end process; + end generate IFG48; + + + -- Port B inputs registered : wren, address, byteena (for bidir_dual_port mode) + IFG49: if (((address_reg_b = "CLOCK0") or + (address_reg_b = "CLOCK1")) and + (operation_mode = "BIDIR_DUAL_PORT")) generate + process (clock0, clock1) + variable m_byteena_mask_reg_b : std_logic_vector(width_b - 1 downto 0); + variable m_byteena_mask_reg_b_out : std_logic_vector(width_b - 1 downto 0); + variable m_byteena_mask_reg_b_x : std_logic_vector(width_b - 1 downto 0) := (others => '0'); + variable m_byteena_mask_reg_b_out_a : std_logic_vector(width_b - 1 downto 0); + variable need_init_var : boolean := true; + begin + + if (need_init_var = true) then + if ((IS_HARDCOPYII) and + (ram_block_type = "M4K") and (operation_mode /= "SINGLE_PORT") and + (((address_reg_b = "CLOCK0") and (clock0 = '1')) or ((address_reg_b = "CLOCK1") and (clock1 = '1')))) then + i_good_to_write_a <= '0'; + end if; + + need_init_var := false; + end if; + + if (((address_reg_b = "CLOCK0") and + (rising_edge(clock0))) or + ((address_reg_b = "CLOCK1") and + (rising_edge(clock1)))) then + + if (i_force_reread_b = '1' and (i_outlatch_clken_b = '1')) then + i_force_reread_signal_b <= not i_force_reread_signal_b; + end if; + + if (i_core_clocken_b = '1') then + if (HAS_STRATIXV_STYLE_RAM or IS_STRATIXIII) then + good_to_go_b <= '1'; + + if (i_rdcontrol_aclr_b = '1') then + i_rden_reg_b <= '1'; + else + i_rden_reg_b <= rden_b; + end if; + + if (i_wrcontrol_aclr_b = '1') then + i_wren_reg_b <= '0'; + else + i_wren_reg_b <= wren_b; + + i_read_flag_b <= not i_read_flag_b; + end if; + end if; + else + i_nmram_write_b <= '0'; + end if; + + if (i_input_clocken_b = '1') then + + if ((not HAS_STRATIXV_STYLE_RAM) and (not HAS_STRATIXIII_STYLE_RAM)) then + i_read_flag_b <= not i_read_flag_b; + end if; + + if (i_indata_aclr_b = '1') then + i_data_reg_b <= (others => '0'); + else + i_data_reg_b <= data_b; + end if; + + if ((not HAS_STRATIXV_STYLE_RAM) and (not IS_STRATIXIII)) then + good_to_go_b <= '1'; + + if (i_rdcontrol_aclr_b = '1') then + i_rden_reg_b <= '1'; + else + i_rden_reg_b <= rden_b; + end if; + + if (i_wrcontrol_aclr_b = '1') then + i_wren_reg_b <= '0'; + else + i_wren_reg_b <= wren_b; + + end if; + end if; + + if (i_wrcontrol_aclr_b = '1') then + i_address_reg_b <= (others => '0'); + elsif (addressstall_b /= '1') then + i_address_reg_b <= address_b; + end if; + + if (i_byteena_aclr_b = '1') then + m_byteena_mask_reg_b := (others => '1'); + m_byteena_mask_reg_b_out := (others => '0'); + m_byteena_mask_reg_b_x := (others => '0'); + m_byteena_mask_reg_b_out_a := (others => 'X'); + else + if (width_byteena_b = 1) then + if (byteena_b(0) = 'Z') then + m_byteena_mask_reg_b := (others => '1'); + else + m_byteena_mask_reg_b := (others => byteena_b(0)); + end if; + if ((byteena_b(0) = '1') or (byteena_b(0) = 'Z')) then + m_byteena_mask_reg_b_out := (others => '0'); + m_byteena_mask_reg_b_x := (others => '0'); + m_byteena_mask_reg_b_out_a := (others => 'X'); + elsif (byteena_b(0) = '0') then + m_byteena_mask_reg_b_x := (others => '0'); + m_byteena_mask_reg_b_out := (others => 'X'); + m_byteena_mask_reg_b_out_a := (others => '0'); + else + m_byteena_mask_reg_b_x := (others => 'X'); + m_byteena_mask_reg_b_out := (others => 'X'); + m_byteena_mask_reg_b_out_a := (others => 'X'); + end if; + else + for k in 0 to (width_b - 1) loop + if (byteena_b(k / i_byte_size) = 'Z') then + m_byteena_mask_reg_b(k) := '1'; + else + m_byteena_mask_reg_b(k) := byteena_b(k / i_byte_size); + end if; + + if (m_byteena_mask_reg_b(k) = '1') then + m_byteena_mask_reg_b_out(k) := '0'; + m_byteena_mask_reg_b_x(k) := '0'; + m_byteena_mask_reg_b_out_a(k) := 'X'; + elsif (m_byteena_mask_reg_b(k) = '0') then + m_byteena_mask_reg_b_out(k) := 'X'; + m_byteena_mask_reg_b_x(k) := '0'; + m_byteena_mask_reg_b_out_a(k) := '0'; + else + m_byteena_mask_reg_b_out(k) := 'X'; + m_byteena_mask_reg_b_x(k) := 'X'; + m_byteena_mask_reg_b_out_a(k) := 'X'; + end if; + end loop; + end if; + end if; + + i_byteena_mask_reg_b_out <= m_byteena_mask_reg_b_out; + i_byteena_mask_reg_b <= m_byteena_mask_reg_b; + i_byteena_mask_reg_b_x <= m_byteena_mask_reg_b_x; + i_byteena_mask_reg_b_out_a <= m_byteena_mask_reg_b_out_a; + end if; + + if ((i_core_clocken_b = '1') and ((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM))) then + i_read_flag_b <= not i_read_flag_b; + end if; + + if ((i_core_clocken_b = '1') and ((wren_b = '1') or (i_wren_reg_b = '1'))) then + if (is_write_positive_edge) then + i_write_flag_b <= not i_write_flag_b; + end if; + + i_nmram_write_b <= '1'; + end if; + + end if; + + if (((address_reg_b = "CLOCK0") and + (falling_edge(clock0))) or + ((address_reg_b = "CLOCK1") and + (falling_edge(clock1)))) then + + if (i_core_clocken_b = '1') then + i_good_to_write_a <= '1'; + end if; + + if (not is_write_positive_edge) then + if ((i_nmram_write_b = '1') and (i_wren_reg_b = '1')) then + i_write_flag_b <= not i_write_flag_b; + end if; + end if; + end if; + + end process; + end generate IFG49; + + -- Port A : assigning the correct output values for i_q_tmp_a (non-registered output) + + process (i_q_tmp2_a, i_force_reread_signal_a, i_outdata_aclr_a, good_to_go_a, default_val, i_address_aclr_a) + variable i_force_reread_a1_flag : std_logic := '0'; + begin + if (not good_to_go_a = '1') then + if (i_is_lutram) then + i_q_tmp_a <= i_q_tmp2_a; + else + i_q_tmp_a <= (others => default_val); + end if; + else + if ((i_outdata_aclr_a = '1')and + (outdata_reg_a /= "CLOCK0") and + (outdata_reg_a /= "CLOCK1") and + (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and + (not i_is_lutram))) then + i_q_tmp_a <= (others => '0'); + elsif (falling_edge(i_outdata_aclr_a)and + (outdata_reg_a /= "CLOCK0") and + (outdata_reg_a /= "CLOCK1") and + (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and + (not i_is_lutram))) then + i_force_reread_a <= '1'; + elsif (rising_edge(i_address_aclr_a) and + (outdata_reg_a /= "CLOCK0") and + (outdata_reg_a /= "CLOCK1") and + (((HAS_STRATIXV_STYLE_RAM) or (IS_BASE_STRATIXIII)) and + (not i_is_lutram))) then + i_q_tmp_a <= (others => 'X'); + i_force_reread_a1 <= '1'; + i_force_reread_a1_flag := '1'; + elsif ((i_force_reread_signal_a'event) or (i_force_reread_a1_flag = '0' and i_force_reread_a = '0')) then + if(i_force_reread_a = '0' or (not HAS_STRATIXV_STYLE_RAM)) then + i_q_tmp_a <= i_q_tmp2_a; + end if; + i_force_reread_a1 <= '0'; + i_force_reread_a <= '0'; + i_force_reread_a1_flag := '0'; + elsif (i_force_reread_a = '1')then + i_q_tmp_a <= (others => '0'); + end if; + end if; + end process; + + -- Port A outdata output registered + process (clock0, clock1, i_outdata_aclr_a, i_address_aclr_a, i_rden_reg_a) + variable i_address_aclr_a_flag : std_logic := '0'; + begin + if ((i_address_aclr_a'event) and (i_address_aclr_a = '1') and + (i_rden_reg_a = '1')) then + i_address_aclr_a_flag := '1'; + end if; + if (i_outdata_aclr_a = '1') then + i_q_reg_a <= (others => '0'); + i_address_aclr_a_flag := '0'; + elsif (((outdata_reg_a = "CLOCK0") and (rising_edge(clock0))) or + ((outdata_reg_a = "CLOCK1") and (rising_edge(clock1)))) then + if i_outdata_clken_a = '1' then + -- clear for 1 clock cycle + if ((i_address_aclr_a_flag = '1') and + ((HAS_STRATIXV_STYLE_RAM) or (IS_BASE_STRATIXIII)) and + (outdata_reg_a = "CLOCK0") and (not i_is_lutram)) then + i_q_reg_a <= (others => 'X'); + else + i_q_reg_a <= i_q_tmp_a; + end if; + if (i_core_clocken_a = '1') then + i_address_aclr_a_flag := '0'; + end if; + elsif (i_core_clocken_a = '1') then + i_address_aclr_a_flag := '0'; + end if; + end if; + end process; + + + -- Port A : assigning the correct output values for q_a + + IFG52: if (((outdata_reg_a = "CLOCK0") or (outdata_reg_a = "CLOCK1")) and + (operation_mode /= "DUAL_PORT")) generate + q_a <= i_q_reg_a; + end generate IFG52; + + IFG53: if (((outdata_reg_a /= "CLOCK0") and (outdata_reg_a /= "CLOCK1")) and + (operation_mode /= "DUAL_PORT")) generate + q_a <= i_q_tmp_a; + end generate IFG53; + + IFG54: if (operation_mode = "DUAL_PORT") generate + q_a <= (others => '0'); + end generate IFG54; + + + -- Port B : assigning the correct output values for i_q_tmp_b (non-registered output) + process (i_q_tmp2_b, good_to_go_b, i_rden_reg_b, i_wren_reg_b, i_data_reg_b, i_address_aclr_b, + i_byteena_mask_reg_b_out, default_val, i_address_reg_b, i_core_clocken_b, + i_original_data_b, i_outdata_aclr_b, i_force_reread_signal_b) + variable i_force_reread_b1_flag : std_logic := '0'; + variable m_address_a : integer := 0; + variable m_address_b : integer := 0; + begin + if ((operation_mode = "DUAL_PORT") or (operation_mode = "BIDIR_DUAL_PORT")) then + if (not good_to_go_b = '1') then + if (i_is_lutram) then + i_q_tmp_b <= i_q_tmp2_b; + else + i_q_tmp_b <= (others => default_val); + end if; + else + + if (i_q_tmp2_b'event or good_to_go_b'event or i_rden_reg_b'event or i_wren_reg_b'event or + i_data_reg_b'event or i_byteena_mask_reg_b_out'event or i_address_reg_b'event or + i_original_data_b'event or i_force_reread_signal_b'event) then + if (((i_rden_reg_b = '1') and (i_force_reread_b1_flag = '0')) or (i_is_lutram)) then + if ((conv_integer(unsigned(i_address_reg_b)) >= i_numwords_b)) then + if ((i_wren_reg_b = '1') and (i_core_clocken_b = '1')) then + i_q_tmp_b <= i_q_tmp2_b; + else + i_q_tmp_b <= (others => 'X'); + end if; + assert false + report "Address pointed at port B is out of bound! " + severity warning; + else + i_q_tmp_b <= i_q_tmp2_b; + end if; + end if; + + end if; + + if ((i_outdata_aclr_b = '1') and + (outdata_reg_b /= "CLOCK0") and + (outdata_reg_b /= "CLOCK1") and + (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and + (not i_is_lutram))) then + i_q_tmp_b <= (others => '0'); + elsif (falling_edge(i_outdata_aclr_b)and + (outdata_reg_b /= "CLOCK0") and + (outdata_reg_b /= "CLOCK1") and + (((HAS_STRATIXV_STYLE_RAM) or (HAS_STRATIXIII_STYLE_RAM)) and + (not i_is_lutram))) then + i_force_reread_b <= '1'; + elsif (rising_edge(i_address_aclr_b) and + (outdata_reg_b /= "CLOCK0") and + (outdata_reg_b /= "CLOCK1") and + ((HAS_STRATIXV_STYLE_RAM) or (IS_BASE_STRATIXIII)) and + (not i_is_lutram)) then + if (i_rden_reg_b = '1') then + i_q_tmp_b <= (others => 'X'); + end if; + i_force_reread_b1 <= '1'; + i_force_reread_b1_flag := '1'; + elsif (i_force_reread_signal_b'event) then + if(i_force_reread_b = '0' or (not HAS_STRATIXV_STYLE_RAM)) then + i_q_tmp_b <= i_q_tmp2_b; + end if; + i_force_reread_b <= '0'; + i_force_reread_b1 <= '0'; + i_force_reread_b1_flag := '0'; + elsif(i_force_reread_b = '1') then + i_q_tmp_b <= (others => '0'); + end if; + + + + if ((i_is_lutram) and (is_write_positive_edge) and (cread_during_write_mode_mixed_ports = "OLD_DATA")) then + m_address_a := conv_integer(unsigned(i_address_reg_a)); + m_address_b := conv_integer(unsigned(i_address_reg_b)); + if((width_a = width_b) and (m_address_a = m_address_b) and (i_wren_reg_a = '1') and (i_rden_reg_b = '1')) then + i_q_tmp_b <= i_original_data_a; + else + i_q_tmp_b <= i_q_tmp2_b; + end if; + end if; + end if; + end if; + + end process; + + -- Port B outdata output registered + process (clock0, clock1, i_outdata_aclr_b, i_address_aclr_b, i_rden_reg_b) + variable i_address_aclr_b_flag : std_logic := '0'; + variable m_address_a : integer := 0; + variable m_address_b : integer := 0; + begin + if ((i_address_aclr_b'event) and (i_address_aclr_b = '1') and + (i_rden_reg_b = '1')) then + i_address_aclr_b_flag := '1'; + end if; + if (i_outdata_aclr_b = '1') then + i_q_reg_b <= (others => '0'); + i_address_aclr_b_flag := '0'; + elsif (((outdata_reg_b = "CLOCK0") and (rising_edge(clock0))) or + ((outdata_reg_b = "CLOCK1") and (rising_edge(clock1)))) then + if (i_outdata_clken_b = '1') then + if ((i_is_lutram) and (cread_during_write_mode_mixed_ports = "OLD_DATA") and + (outdata_reg_b = "CLOCK0")) then + i_q_reg_b <= i_q_output_latch; + else + if ((i_address_aclr_b_flag = '1') and + ((HAS_STRATIXV_STYLE_RAM) or (IS_BASE_STRATIXIII)) and + (outdata_reg_b = "CLOCK0") and (not i_is_lutram)) then + i_q_reg_b <= (others => 'X'); + else + i_q_reg_b <= i_q_tmp_b; + end if; + if (i_core_clocken_b = '1') then + i_address_aclr_b_flag := '0'; + end if; + end if; + elsif (i_core_clocken_b = '1') then + i_address_aclr_b_flag := '0'; + end if; + end if; + + if (((outdata_reg_b = "CLOCK0") and (falling_edge(clock0))) or + ((outdata_reg_b = "CLOCK1") and (falling_edge(clock1)))) then + if (i_core_clocken_a = '1') then + m_address_a := conv_integer(unsigned(i_address_reg_a)); + m_address_b := conv_integer(unsigned(i_address_reg_b)); + if((width_a = width_b) and (m_address_a = m_address_b) and (i_wren_reg_a = '1') and (i_rden_reg_b = '1')) then + i_q_output_latch <= i_original_data_a; + else + i_q_output_latch <= i_q_tmp_b; + end if; + end if; + end if; + end process; + + -- ECC Pipeline Register + process (clock0, clock1, i_outdata_aclr_b) + begin + if (i_outdata_aclr_b = '1') then + i_q_ecc_reg_b <= (others => '0'); + elsif (((outdata_reg_b = "CLOCK0") and (rising_edge(clock0))) or + ((outdata_reg_b = "CLOCK1") and (rising_edge(clock1)))) then + if (i_outdata_clken_b = '1') then + i_q_ecc_reg_b <= i_q_reg_b; + end if; + end if; + end process; + + -- Port B : assigning the correct output values for q_b + + IFG55: if ((ecc_pipeline_stage_enabled = "FALSE") and + ((outdata_reg_b = "CLOCK0") or (outdata_reg_b = "CLOCK1")) and + (operation_mode /= "SINGLE_PORT") and (operation_mode /= "ROM")) generate + q_b <= i_q_reg_b; + end generate IFG55; + + IFG56: if ((ecc_pipeline_stage_enabled = "FALSE") and + ((outdata_reg_b /= "CLOCK0") and (outdata_reg_b /= "CLOCK1")) and + (operation_mode /= "SINGLE_PORT") and (operation_mode /= "ROM")) generate + q_b <= i_q_tmp_b; + end generate IFG56; + + IFG57: if ((operation_mode = "SINGLE_PORT") or (operation_mode = "ROM")) generate + q_b <= (others => '0'); + end generate IFG57; + + IFG58: if ((ecc_pipeline_stage_enabled = "TRUE") and + ((outdata_reg_b = "CLOCK0") or (outdata_reg_b = "CLOCK1")) and + (operation_mode /= "SINGLE_PORT") and (operation_mode /= "ROM")) generate + q_b <= i_q_ecc_reg_b; + end generate IFG58; + + IFG59: if ((ecc_pipeline_stage_enabled = "TRUE") and + ((outdata_reg_b /= "CLOCK0") and (outdata_reg_b /= "CLOCK1")) and + (operation_mode /= "SINGLE_PORT") and (operation_mode /= "ROM")) generate + q_b <= i_q_ecc_tmp_b; --i_q_ecc_tmp_b has 'x' output + end generate IFG59; + -- ECC status + + eccstatus <= (others => '0'); + +end translated; + +-- END OF ARCHITECTURE ALTSYNCRAM + +-------------------------------------------------------------------------------+ +-- Module Name : alt3pram +-- +-- Description : Triple-Port RAM megafunction. This megafunction implements +-- RAM with 1 write port and 2 read ports. +-- +-- Limitation : This megafunction is provided only for backward +-- compatibility in Stratix™ designs; instead, Altera® +-- recommends using the altsyncram megafunction +-- +-- In MAX 3000, and MAX 7000 devices, +-- or if the USE_EAB paramter is set to "OFF", uses one +-- logic cell (LCs) per memory bit. +-- +-- +-- Results expected : The alt3pram function represents asynchronous memory +-- or memory with synchronous inputs and/or outputs. +-- (note: ^ below indicates posedge) +-- +-- [ Synchronous Write to Memory (all inputs registered) ] +-- inclock inclocken wren Function +-- X L L No change. +-- not ^ H H No change. +-- ^ L X No change. +-- ^ H H The memory location +-- pointed to by wraddress[] +-- is loaded with data[]. +-- +-- [ Synchronous Read from Memory ] +-- inclock inclocken rden_a/rden_b Function +-- X L L No change. +-- not ^ H H No change. +-- ^ L X No change. +-- ^ H H The q_a[]/q_b[]port +-- outputs the contents of +-- the memory location. +-- +-- [ Asynchronous Memory Operations ] +-- wren Function +-- L No change. +-- H The memory location pointed to by wraddress[] is +-- loaded with data[] and controlled by wren. +-- The output q_a[] is asynchronous and reflects +-- the memory location pointed to by rdaddress_a[]. +-- +-------------------------------------------------------------------------------+ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use std.textio.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.ALTERA_COMMON_CONVERSION.all; +use work.altsyncram; +use work.ALTERA_MF_HINT_EVALUATION.all; + + +--------------------- +-- ENTITY DECLARATION +--------------------- + +entity alt3pram is + generic + ( width : natural; -- data[], qa[] and qb[] + widthad : natural; -- rdaddress_a,rdaddress_b,wraddress + numwords : natural := 0; -- words stored in memory + lpm_file : string := "UNUSED"; -- name of hex file + lpm_hint : string := "USE_EAB=ON"; -- non-LPM parameters (Altera) + indata_reg : string := "UNREGISTERED";-- clock used by data[] port + indata_aclr : string := "ON"; -- aclr affects data[]? + write_reg : string := "UNREGISTERED";-- clock used by wraddress & wren + write_aclr : string := "ON"; -- aclr affects wraddress? + rdaddress_reg_a : string := "UNREGISTERED";-- clock used by readdress_a + rdaddress_aclr_a : string := "ON"; -- aclr affects rdaddress_a? + rdaddress_reg_b : string := "UNREGISTERED";-- clock used by readdress_b + rdaddress_aclr_b : string := "ON"; -- aclr affects rdaddress_b? + rdcontrol_reg_a : string := "UNREGISTERED";-- clock used by rden_a + rdcontrol_aclr_a : string := "ON"; -- aclr affects rden_a? + rdcontrol_reg_b : string := "UNREGISTERED";-- clock used by rden_b + rdcontrol_aclr_b : string := "ON"; -- aclr affects rden_b? + outdata_reg_a : string := "UNREGISTERED";-- clock used by qa[] + outdata_aclr_a : string := "ON"; -- aclr affects qa[]? + outdata_reg_b : string := "UNREGISTERED";-- clock used by qb[] + outdata_aclr_b : string := "ON"; -- aclr affects qb[]? + intended_device_family : string := "Stratix"; + ram_block_type : string := "AUTO"; -- ram block type to be used + maximum_depth : integer := 0; -- maximum segmented value of the RAM + lpm_type : string := "alt3pram" + ); + + port + ( wren : in std_logic := '0'; + data : in std_logic_vector(width-1 downto 0); + wraddress : in std_logic_vector(widthad-1 downto 0); + inclock : in std_logic := '0'; + inclocken : in std_logic := '1'; + rden_a : in std_logic := '1'; + rden_b : in std_logic := '1'; + rdaddress_a : in std_logic_vector(widthad-1 downto 0); + rdaddress_b : in std_logic_vector(widthad-1 downto 0); + outclock : in std_logic := '0'; + outclocken : in std_logic := '1'; + aclr : in std_logic := '0'; + qa : out std_logic_vector(width-1 downto 0); + qb : out std_logic_vector(width-1 downto 0) + ); + +end alt3pram; -- Entity: alt3pram + +--------------------------- +-- ARCHITECTURE DECLARATION +--------------------------- +architecture behavior of alt3pram is + +------------------------ +-- FUNCTION DECLARATION +------------------------ +-- The following functions take in parameters values used in alt3pram and convert +-- to a corresponding(or suitable) parameters value that used in altsyncram. +function get_num_words (i_numwords : natural; + i_widthad : natural) return integer is +begin + if (i_numwords = 0) then + return 2**i_widthad; + else + return i_numwords; + end if; +end; + +function get_read_during_write_mode_mixed_ports(i_ram_block_type : string) return string is +begin + if (i_ram_block_type = "AUTO") then + return "OLD_DATA"; + else + return "DONT_CARE"; + end if; +end; + +function get_write_aclr_a_clk(i_write_aclr : string) return string is +begin + if ((not FEATURE_FAMILY_STRATIXII(intended_device_family)) and i_write_aclr = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +function get_indata_aclr_a_clk(i_indata_aclr : string) return string is +begin + if ((not FEATURE_FAMILY_STRATIXII(intended_device_family)) and i_indata_aclr = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +function get_rdcontrol_reg_a_clk(i_rdcontrol_reg_a : string) return string is +begin + if (i_rdcontrol_reg_a = "INCLOCK") then + return "CLOCK0"; + elsif (i_rdcontrol_reg_a = "OUTCLOCK") then + return "CLOCK1"; + else + return "UNUSED"; + end if; +end; + +function get_rdaddress_reg_a_clk(i_rdaddress_reg_a : string) return string is +begin + if (i_rdaddress_reg_a = "INCLOCK") then + return "CLOCK0"; + elsif (i_rdaddress_reg_a = "OUTCLOCK") then + return "CLOCK1"; + else + return "UNUSED"; + end if; +end; + +function get_outdata_reg_a_clk(i_outdata_reg_a : string) return string is +begin + if (i_outdata_reg_a = "INCLOCK") then + return "CLOCK0"; + elsif (i_outdata_reg_a = "OUTCLOCK") then + return "CLOCK1"; + else + return "UNREGISTERED"; + end if; +end; + +function get_outdata_aclr_a_clk(i_outdata_aclr_a : string) return string is +begin + if (i_outdata_aclr_a = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +function get_rdcontrol_aclr_a_clk(i_rdcontrol_aclr_a : string) return string is +begin + if ((not FEATURE_FAMILY_STRATIXII(intended_device_family)) and i_rdcontrol_aclr_a = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +function get_rdaddress_aclr_a_clk(i_rdaddress_aclr_a : string) return string is +begin + if ((not FEATURE_FAMILY_STRATIXII(intended_device_family)) and i_rdaddress_aclr_a = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +function get_rdcontrol_reg_b_clk(i_rdcontrol_reg_b : string) return string is +begin + if (i_rdcontrol_reg_b = "INCLOCK") then + return "CLOCK0"; + elsif (i_rdcontrol_reg_b = "OUTCLOCK") then + return "CLOCK1"; + else + return "UNUSED"; + end if; +end; + +function get_rdaddress_reg_b_clk(i_rdaddress_reg_b : string) return string is +begin + if (i_rdaddress_reg_b = "INCLOCK") then + return "CLOCK0"; + elsif (i_rdaddress_reg_b = "OUTCLOCK") then + return "CLOCK1"; + else + return "UNUSED"; + end if; +end; + +function get_outdata_reg_b_clk(i_outdata_reg_b : string) return string is +begin + if (i_outdata_reg_b = "INCLOCK") then + return "CLOCK0"; + elsif (i_outdata_reg_b = "OUTCLOCK") then + return "CLOCK1"; + else + return "UNREGISTERED"; + end if; +end; + +function get_outdata_aclr_b_clk(i_outdata_aclr_b : string) return string is +begin + if (i_outdata_aclr_b = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +function get_rdcontrol_aclr_b_clk(i_rdcontrol_aclr_b : string) return string is +begin + if ((not FEATURE_FAMILY_STRATIXII(intended_device_family)) and i_rdcontrol_aclr_b = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +function get_rdaddress_aclr_b_clk(i_rdaddress_aclr_b : string) return string is +begin + if ((not FEATURE_FAMILY_STRATIXII(intended_device_family)) and i_rdaddress_aclr_b = "ON") then + return "CLEAR0"; + else + return "NONE"; + end if; +end; + +------------------- +-- TYPE DECLARATION +------------------- +type alt_memory is array((2**WIDTHAD)-1 downto 0) of std_logic_vector(WIDTH-1 downto 0); + +----------------------- +-- CONSTANT DECLARATION +----------------------- +constant IS_STRATIX : boolean := FEATURE_FAMILY_STRATIX(intended_device_family); +constant NUM_WORDS : integer := get_num_words(numwords, widthad); +constant READ_DURING_WRITE_MODE : string := get_read_during_write_mode_mixed_ports(ram_block_type); +constant WRITE_ACLR_A_CLK : string := get_write_aclr_a_clk(write_aclr); +constant INDATA_ACLR_A_CLK : string := get_indata_aclr_a_clk(indata_aclr); +constant RDCONTROL_REG_A_CLK : string := get_rdcontrol_reg_a_clk(rdcontrol_reg_a); +constant RDADDRESS_REG_A_CLK : string := get_rdaddress_reg_a_clk(rdaddress_reg_a); +constant OUTDATA_REG_A_CLK : string := get_outdata_reg_a_clk(outdata_reg_a); +constant OUTDATA_ACLR_A_CLK : string := get_outdata_aclr_a_clk(outdata_aclr_a); +constant RDCONTROL_ACLR_A_CLK : string := get_rdcontrol_aclr_a_clk(rdcontrol_aclr_a); +constant RDADDRESS_ACLR_A_CLK : string := get_rdaddress_aclr_a_clk(rdaddress_aclr_a); +constant RDCONTROL_REG_B_CLK : string := get_rdcontrol_reg_b_clk(rdcontrol_reg_b); +constant RDADDRESS_REG_B_CLK : string := get_rdaddress_reg_b_clk(rdaddress_reg_b); +constant OUTDATA_REG_B_CLK : string := get_outdata_reg_b_clk(outdata_reg_b); +constant OUTDATA_ACLR_B_CLK : string := get_outdata_aclr_b_clk(outdata_aclr_b); +constant RDCONTROL_ACLR_B_CLK : string := get_rdcontrol_aclr_b_clk(rdcontrol_aclr_b); +constant RDADDRESS_ACLR_B_CLK : string := get_rdaddress_aclr_b_clk(rdaddress_aclr_b); +constant LPM_HINT_USE_EAB : string := GET_PARAMETER_VALUE(lpm_hint, "USE_EAB"); + + +--------------------- +-- SIGNAL DECLARATION +--------------------- +signal idata_tmp : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal idata_reg : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); + +signal idata_hi : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal idata_lo : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); + +signal iqa_tmp : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal iqa_reg : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); + +signal iqb_tmp : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); +signal iqb_reg : std_logic_vector(WIDTH-1 downto 0) := (OTHERS => '0'); + +signal iwren_tmp : std_logic := '0'; +signal iwren_reg : std_logic := '0'; + +signal iwren_hi : std_logic := '0'; +signal iwren_lo : std_logic := '0'; + +signal irdaddress_tmp_a : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal irdaddress_reg_a : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); + +signal irdaddress_tmp_b : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal irdaddress_reg_b : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); + +signal iwraddress_tmp : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal iwraddress_reg : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); + +signal iwraddress_hi : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); +signal iwraddress_lo : std_logic_vector(WIDTHAD-1 downto 0) := (OTHERS => '0'); + +signal irden_tmp_a : std_logic := '0'; +signal irden_reg_a : std_logic := '0'; + +signal irden_tmp_b : std_logic := '0'; +signal irden_reg_b : std_logic := '0'; + +signal unused_port0 : std_logic_vector(width-1 downto 0); +signal unused_port1 : std_logic_vector(width-1 downto 0); + +signal iqa_non_stratix : std_logic_vector(width-1 downto 0); +signal iqb_non_stratix : std_logic_vector(width-1 downto 0); + +signal iqa_stratix : std_logic_vector(width-1 downto 0); +signal iqb_stratix : std_logic_vector(width-1 downto 0); + +signal iinclock_non_stratix : std_logic; -- inclock signal for non-Stratix families +signal ioutclock_non_stratix : std_logic; -- outclock signal for non-Stratix families + +signal write_at_low_clock : boolean := false; +signal rden_low_output_0 : boolean := false; + +-------------------------- +-- COMPONENTS DECLARATION +-------------------------- +component altsyncram + GENERIC ( + operation_mode : string := "SINGLE_PORT"; + width_a : natural := 8; + widthad_a : natural := 2; + numwords_a : natural := 4; + address_aclr_a : string := "NONE"; + indata_aclr_a : string := "CLEAR0"; + wrcontrol_aclr_a : string := "NONE"; + width_b : natural := 8; + widthad_b : natural := 4; + numwords_b : natural := 4; + rdcontrol_reg_b : string := "CLOCK1"; + address_reg_b : string := "CLOCK1"; + outdata_reg_b : string := "UNREGISTERED"; + outdata_aclr_b : string := "NONE"; + rdcontrol_aclr_b : string := "NONE"; + address_aclr_b : string := "NONE"; + read_during_write_mode_mixed_ports: string := READ_DURING_WRITE_MODE; + ram_block_type : string := "AUTO"; + init_file : string := "UNUSED"; + init_file_layout : string := "UNUSED"; + maximum_depth : integer := 0; + intended_device_family : string := "Stratix" ); + PORT ( + wren_a : IN std_logic := '0'; + rden_b : IN std_logic := '1'; + data_a : IN std_logic_vector(width_a - 1 DOWNTO 0):= (others => '0'); + address_a : IN std_logic_vector(widthad_a - 1 DOWNTO 0) := (others => '0'); + address_b : IN std_logic_vector(widthad_b - 1 DOWNTO 0) := (others => '0'); + clock0 : IN std_logic := '1'; + clock1 : IN std_logic := '1'; + clocken0 : IN std_logic := '1'; + clocken1 : IN std_logic := '1'; + aclr0 : IN std_logic := '0'; + q_a : OUT std_logic_vector(width_a - 1 DOWNTO 0); + q_b : OUT std_logic_vector(width_b - 1 DOWNTO 0)); +END component; + + +begin + +-------------------------- +-- COMPONENTS ASSIGNMENTS +-------------------------- + -- The alt3pram for Stratix/Stratix II/ Stratix GX and Cyclone device families + -- are basically consists of 2 instances of altsyncram with write port of each + -- instance been tied together. + STRATIX_DUALPORT_RAM0: + if (IS_STRATIX = true) generate + U0: altsyncram + generic map + ( operation_mode => "DUAL_PORT", + width_a => width, + widthad_a => widthad, + numwords_a => NUM_WORDS, + address_aclr_a => WRITE_ACLR_A_CLK, + indata_aclr_a => INDATA_ACLR_A_CLK, + wrcontrol_aclr_a => WRITE_ACLR_A_CLK, + width_b => width, + widthad_b => widthad, + numwords_b => NUM_WORDS, + rdcontrol_reg_b => RDCONTROL_REG_A_CLK, + address_reg_b => RDADDRESS_REG_A_CLK, + outdata_reg_b => OUTDATA_REG_A_CLK, + outdata_aclr_b => OUTDATA_ACLR_A_CLK, + rdcontrol_aclr_b => RDCONTROL_ACLR_A_CLK, + address_aclr_b => RDADDRESS_ACLR_A_CLK, + read_during_write_mode_mixed_ports => READ_DURING_WRITE_MODE, + ram_block_type => ram_block_type, + init_file => lpm_file, + init_file_layout => "PORT_B", + maximum_depth => maximum_depth, + intended_device_family => intended_device_family) + port map + ( wren_a => wren, + rden_b => rden_a, + data_a => data, + address_a => wraddress, + address_b => rdaddress_a, + clock0 => inclock, + clock1 => outclock, + clocken0 => inclocken, + clocken1 => outclocken, + aclr0 => aclr, + q_a => unused_port0, + q_b => iqa_stratix); + end generate STRATIX_DUALPORT_RAM0; + + STRATIX_DUALPORT_RAM1: + if (IS_STRATIX = true) generate + U1: altsyncram + generic map + ( operation_mode => "DUAL_PORT", + width_a => width, + widthad_a => widthad, + numwords_a => NUM_WORDS, + address_aclr_a => WRITE_ACLR_A_CLK, + indata_aclr_a => INDATA_ACLR_A_CLK, + wrcontrol_aclr_a => WRITE_ACLR_A_CLK, + width_b => width, + widthad_b => widthad, + numwords_b => NUM_WORDS, + rdcontrol_reg_b => RDCONTROL_REG_B_CLK, + address_reg_b => RDADDRESS_REG_B_CLK, + outdata_reg_b => OUTDATA_REG_B_CLK, + outdata_aclr_b => OUTDATA_ACLR_B_CLK, + rdcontrol_aclr_b => RDCONTROL_ACLR_B_CLK, + address_aclr_b => RDADDRESS_ACLR_B_CLK, + read_during_write_mode_mixed_ports => READ_DURING_WRITE_MODE, + ram_block_type => ram_block_type, + init_file => lpm_file, + init_file_layout => "PORT_B", + maximum_depth => maximum_depth, + intended_device_family => intended_device_family) + port map + ( wren_a => wren, + rden_b => rden_b, + data_a => data, + address_a => wraddress, + address_b => rdaddress_b, + clock0 => inclock, + clock1 => outclock, + clocken0 => inclocken, + clocken1 => outclocken, + aclr0 => aclr, + q_a => unused_port1, + q_b => iqb_stratix); + end generate STRATIX_DUALPORT_RAM1; + +-- ****************** +-- SIGNAL ASSIGNMENTS +-- ****************** + qa <= iqa_stratix when (IS_STRATIX = true) + else iqa_non_stratix; + + qb <= iqb_stratix when (IS_STRATIX = true) + else iqb_non_stratix; + + iinclock_non_stratix <= inclock when (IS_STRATIX = false) + else '0'; + + ioutclock_non_stratix <= outclock when (IS_STRATIX = false) + else '0'; + +-- ************* +-- PROCESS BLOCK +-- ************* + +-- The following process blocks are used to implement the alt3pram behavior for +-- device families other than Stratix/Stratix II/Stratix GX and Cyclone. + + -- Initial Block + ---------------- + INITIAL: process (iinclock_non_stratix, ioutclock_non_stratix) + variable init : boolean := false; + begin + if (not init) then + if (LPM_HINT_USE_EAB = "ON") then + + -- ------------------------------------------------------------------------- + -- the following behaviour come in effect when RAM is implemented in EAB/ESB + + -- This is the flag to indicate if the memory is constructed using EAB/ESB: + -- A write request requires both rising and falling edge of the clock + -- to complete. First the data will be clocked in (registered) at the + -- rising edge and will not be written into the ESB/EAB memory until + -- the falling edge appears on the the write clock. + -- No such restriction if the memory is constructed using LCs. + if (write_reg = "INCLOCK") then + write_at_low_clock <= true; + end if; + end if; + init := true; + end if; + end process INITIAL; + + ------------------------- + -- Syncronization Process + ------------------------- + SYNC: process (data, idata_reg, rden_a, rden_b, irden_reg_a, irden_reg_b, + rdaddress_a, rdaddress_b, irdaddress_reg_a, irdaddress_reg_b, + wren, iwren_reg, wraddress, iwraddress_reg, + iqa_tmp, iqb_tmp, iqa_reg, iqb_reg, aclr) + begin + if ((rdaddress_reg_a = "INCLOCK") or (rdaddress_reg_a = "OUTCLOCK")) then + irdaddress_tmp_a <= irdaddress_reg_a; + else + irdaddress_tmp_a <= rdaddress_a; + end if; + + if ((rdcontrol_reg_a = "INCLOCK") or (rdcontrol_reg_a = "OUTCLOCK")) then + irden_tmp_a <= irden_reg_a; + else + irden_tmp_a <= rden_a; + end if; + + if ((rdaddress_reg_b = "INCLOCK") or (rdaddress_reg_b = "OUTCLOCK")) then + irdaddress_tmp_b <= irdaddress_reg_b; + else + irdaddress_tmp_b <= rdaddress_b; + end if; + + if ((rdcontrol_reg_b = "INCLOCK") or (rdcontrol_reg_b = "OUTCLOCK")) then + irden_tmp_b <= irden_reg_b; + else + irden_tmp_b <= rden_b; + end if; + + if (write_reg = "INCLOCK") then + iwraddress_tmp <= iwraddress_reg; + iwren_tmp <= iwren_reg; + else + iwraddress_tmp <= wraddress; + iwren_tmp <= wren; + end if; + + if (indata_reg = "INCLOCK") then + idata_tmp <= idata_reg; + else + idata_tmp <= data; + end if; + + if (outdata_reg_a = "OUTCLOCK") then + iqa_non_stratix <= iqa_reg; + else + iqa_non_stratix <= iqa_tmp; + end if; + + if (outdata_reg_b = "OUTCLOCK") then + iqb_non_stratix <= iqb_reg; + else + iqb_non_stratix <= iqb_tmp; + end if; + + if (aclr = '1') then + if(indata_aclr = "ON") then + idata_tmp <= (OTHERS => '0'); + end if; + if(write_aclr = "ON") then + iwraddress_tmp <= (OTHERS => '0'); + iwren_tmp <= '0'; + end if; + if(rdaddress_aclr_a = "ON") then + irdaddress_tmp_a <= (OTHERS => '0'); + end if; + if(rdcontrol_aclr_a = "ON") then + irden_tmp_a <= '0'; + end if; + if(rdaddress_aclr_b = "ON") then + irdaddress_tmp_b <= (OTHERS => '0'); + end if; + if(rdcontrol_aclr_b = "ON") then + irden_tmp_b <= '0'; + end if; + if(outdata_aclr_a = "ON") then + iqa_non_stratix <= (OTHERS => '0'); + end if; + if(outdata_aclr_b = "ON") then + iqb_non_stratix <= (OTHERS => '0'); + end if; + end if; + end process SYNC; + + ------------------------- + -- Syncronization Process + ------------------------- + SYNC2: process (idata_hi, idata_lo, iwraddress_hi, iwraddress_lo, + iwren_hi, iwren_lo, write_at_low_clock) + begin + if (write_at_low_clock) then + idata_reg <= idata_lo; + iwren_reg <= iwren_lo; + iwraddress_reg <= iwraddress_lo; + else + idata_reg <= idata_hi; + iwren_reg <= iwren_hi; + iwraddress_reg <= iwraddress_hi; + end if; + end process SYNC2; + + ------------------------------------------------- + -- Synchronous READ Operation (SHARED CLOCK MODE) + ------------------------------------------------- + + -- READ REGS PORT A + ------------------- + IFG1: if (rdaddress_reg_a = "INCLOCK") generate + process (iinclock_non_stratix, aclr) + begin + if ((aclr = '1') and (rdaddress_aclr_a = "ON")) then + irdaddress_reg_a <= (OTHERS => '0'); + elsif rising_edge(iinclock_non_stratix) then + if (inclocken = '1') then + irdaddress_reg_a <= rdaddress_a; + end if; + end if; + end process; + end generate IFG1; + + IFG2: if (rdcontrol_reg_a = "INCLOCK") generate + process (iinclock_non_stratix, aclr) + begin + if ((aclr = '1') and (rdcontrol_aclr_a = "ON")) then + irden_reg_a <= '0'; + elsif rising_edge(iinclock_non_stratix) then + if (inclocken = '1') then + irden_reg_a <= rden_a; + end if; + end if; + end process; + end generate IFG2; + + IFG3: if (rdaddress_reg_a = "OUTCLOCK") generate + process (ioutclock_non_stratix, aclr) + begin + if ((aclr = '1') and (rdaddress_aclr_a = "ON")) then + irdaddress_reg_a <= (OTHERS => '0'); + elsif rising_edge(ioutclock_non_stratix) then + if (outclocken = '1') then + irdaddress_reg_a <= rdaddress_a; + end if; + end if; + end process; + end generate IFG3; + + IFG4: if (rdcontrol_reg_a = "OUTCLOCK") generate + process (ioutclock_non_stratix, aclr) + begin + if ((aclr = '1') and (rdcontrol_aclr_a = "ON")) then + irden_reg_a <= '0'; + elsif rising_edge(ioutclock_non_stratix) then + if (outclocken = '1') then + irden_reg_a <= rden_a; + end if; + end if; + end process; + end generate IFG4; + + IFG5: if (rdaddress_reg_b = "INCLOCK") generate + process (iinclock_non_stratix, aclr) + begin + if (aclr = '1' and rdaddress_aclr_b = "ON") then + irdaddress_reg_b <= (OTHERS => '0'); + elsif rising_edge(iinclock_non_stratix) then + if (inclocken = '1') then + irdaddress_reg_b <= rdaddress_b; + end if; + end if; + end process; + end generate IFG5; + + IFG6: if (rdcontrol_reg_b = "INCLOCK") generate + process (iinclock_non_stratix, aclr) + begin + if (aclr = '1' and rdcontrol_aclr_b = "ON") then + irden_reg_b <= '0'; + elsif rising_edge(iinclock_non_stratix) then + if (inclocken = '1') then + irden_reg_b <= rden_b; + end if; + end if; + end process; + end generate IFG6; + + IFG7 : if (rdaddress_reg_b = "OUTCLOCK") generate + process (ioutclock_non_stratix, aclr) + begin + if ((aclr = '1') and (rdaddress_aclr_b = "ON")) then + irdaddress_reg_b <= (OTHERS => '0'); + elsif rising_edge(ioutclock_non_stratix) then + if (outclocken = '1') then + irdaddress_reg_b <= rdaddress_b; + end if; + end if; + end process; + end generate IFG7; + + IFG8: if (rdcontrol_reg_b = "OUTCLOCK") generate + process (ioutclock_non_stratix, aclr) + begin + if ((aclr = '1') and (rdcontrol_aclr_b = "ON")) then + irden_reg_b <= '0'; + elsif rising_edge(ioutclock_non_stratix) then + if (outclocken = '1') then + irden_reg_b <= rden_b; + end if; + end if; + end process; + end generate IFG8; + + -- At posedge of the write clock: + -- All input ports values (data, address and control) are + -- clocked in from physical ports to internal variables + -- Write Cycle: i*_hi + -- Read Cycle: i*_reg (Shared Clock Mode) + -- + -- At negedge of the write clock: + -- Write Cycle: since internally data only completed written on memory + -- at the falling edge of write clock, the "write" related + -- data, address and controls need to be shift to another + -- varibles (i*_hi -> i*_lo) during falling edge. + PROC_INCLOCK_OUTCLOCK: process (iinclock_non_stratix, ioutclock_non_stratix, aclr) + begin + -- WRITE REGS -- + if ((aclr = '1') and (indata_aclr = "ON")) then + idata_hi <= (OTHERS => '0'); + idata_lo <= (OTHERS => '0'); + elsif rising_edge(iinclock_non_stratix) then + if (inclocken = '1') then + idata_hi <= data; + end if; + elsif falling_edge(iinclock_non_stratix) then + idata_lo <= idata_hi; + end if; + + if ((aclr = '1') and (write_aclr = "ON")) then + iwraddress_hi <= (OTHERS => '0'); + iwraddress_lo <= (OTHERS => '0'); + iwren_hi <= '0'; + iwren_lo <= '0'; + elsif rising_edge(iinclock_non_stratix) then + if (inclocken = '1') then + iwraddress_hi <= wraddress; + iwren_hi <= wren; + end if; + elsif falling_edge(iinclock_non_stratix) then + iwraddress_lo <= iwraddress_hi; + iwren_lo <= iwren_hi; + end if; + + -- READ REGS PORT A-- + if (aclr = '1' and outdata_aclr_a = "ON") then + iqa_reg <= (OTHERS => '0'); + elsif rising_edge(ioutclock_non_stratix) then + if (outclocken = '1') then + iqa_reg <= iqa_tmp; + end if; + end if; + + + ---------------------------------------------------- + -- Synchronouse READ Operation (SEPERATE CLOCK MODE) + -- At posedge of read clock: + -- Read Cycle: This block is valid only if the operating mode is + -- in "Seperate Clock Mode". All read data, address + -- and control are clocked out from internal vars + -- (i*_reg) to output port. + ---------------------------------------------------- + + -- READ REGS PORT B + ------------------- + if ((aclr = '1') and (outdata_aclr_b = "ON")) then + iqb_reg <= (OTHERS => '0'); + elsif rising_edge(ioutclock_non_stratix) then + if (outclocken = '1') then + iqb_reg <= iqb_tmp; + end if; + end if; + + end process PROC_INCLOCK_OUTCLOCK; + + ----------------------- + -- MEMORY Process Block + ----------------------- + MEMORY: process(idata_tmp, iwren_tmp, irden_tmp_a, irden_tmp_b, irdaddress_tmp_a, + irdaddress_tmp_b, iwraddress_tmp, rden_low_output_0) + variable mem_data : alt_memory; + variable mem_data_word : std_logic_vector(width-1 downto 0) := (OTHERS => '0'); + variable mem_init : boolean := false; + variable i : integer := 0; + variable j : integer := 0; + variable k : integer := 0; + variable n : integer := 0; + variable m : integer := 0; + variable lineno : integer := 0; + variable buf : line; + variable booval : boolean := false; + FILE mem_data_file : TEXT; + variable char : string(1 downto 1) := " "; + variable base : string(2 downto 1) := " "; + variable byte : string(2 downto 1) := " "; + variable rec_type : string(2 downto 1) := " "; + variable datain : string(2 downto 1) := " "; + variable addr : string(2 downto 1) := " "; + variable checksum : string(2 downto 1) := " "; + variable startadd : string(4 downto 1) := " "; + variable ibase : integer := 0; + variable ibyte : integer := 0; + variable istartadd : integer := 0; + variable check_sum_vec : std_logic_vector(7 downto 0) := (OTHERS => '0'); + variable check_sum_vec_tmp : std_logic_vector(7 downto 0) := (OTHERS => '0'); + variable m_string : string(1 to 15); + variable m_data_radix : string(1 to 3); + variable m_address_radix : string(1 to 3); + variable m_width : integer; + variable m_depth : integer; + variable m_start_address_int : integer := 0; + variable m_end_address_int : integer := 0; + variable m_address_int : integer := 0; + variable m_data_int : std_logic_vector(width+4 downto 0) := (OTHERS => '0'); + variable found_keyword_content : boolean := false; + variable get_memory_content : boolean := false; + variable get_start_Address : boolean := false; + variable get_end_Address : boolean := false; + + begin + -- INITIALIZE -- + if NOT(mem_init) then + + --INITIALIZE TO X, IF WRITE_REG IS "UNREGISTERED" + if (write_reg = "UNREGISTERED") then + + for i in mem_data'LOW to mem_data'HIGH loop + mem_data(i) := (OTHERS => 'X'); + + end loop; + + + else + + -- INITIALIZE TO 0 -- + for i in mem_data'LOW to mem_data'HIGH loop + mem_data(i) := (OTHERS => '0'); + + end loop; + end if; + + + if (lpm_file /= "UNUSED") then + FILE_OPEN(mem_data_file, lpm_file, READ_MODE); + if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3 to lpm_file'length)) = ".hex") then + -- ************************************************ + -- Read in RAM intialization file (hex) + -- ************************************************ + WHILE NOT ENDFILE(mem_data_file) loop + booval := true; + READLINE(mem_data_file, buf); + lineno := lineno + 1; + check_sum_vec := (OTHERS => '0'); + if (buf(buf'LOW) = ':') then + i := 1; + shrink_line(buf, i); + READ(L=>buf, VALUE=>byte, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format!" + SEVERITY ERROR; + end if; + ibyte := HEX_STR_TO_INT(byte); + check_sum_vec := unsigned(check_sum_vec) + + unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8)); + READ(L=>buf, VALUE=>startadd, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + istartadd := HEX_STR_TO_INT(startadd); + addr(2) := startadd(4); + addr(1) := startadd(3); + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8)); + addr(2) := startadd(2); + addr(1) := startadd(1); + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8)); + READ(L=>buf, VALUE=>rec_type, good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8)); + else + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + + case rec_type is + when "00"=> -- Data record + i := 0; + k := (WIDTH + 7) / 8; -- # of bytes per entry + while (i < ibyte) loop + mem_data_word := (others => '0'); + + j := 1; + while ( (j <= k) and (i < ibyte) ) loop + -- read in data a byte (2 hex chars) at a time. + READ(L=>buf, VALUE=>datain,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8)); + if (WIDTH > 8) then + mem_data_word := mem_data_word(WIDTH - 9 downto 0) & CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8); + else + mem_data_word := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), WIDTH); + end if; + j := j + 1; + i := i + 1; + end loop; + + if ((ibase + istartadd) <= (2 ** widthad - 1)) then + mem_data(ibase + istartadd) := mem_data_word; + else + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]: Unable to initialized memory with this data record since the specified address is out of valid address range!" + SEVERITY WARNING; + end if; + istartadd := istartadd + 1; + end loop; + when "01"=> + exit; + when "02"=> + ibase := 0; + if (ibyte /= 2) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format for record type 02! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + ibase := (ibase * 256) + HEX_STR_TO_INT(base); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + ibase := ibase * 16; + when "03"=> + if (ibyte /= 4) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format for record type 03! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + when "04"=> + ibase := 0; + if (ibyte /= 2) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format for record type 04! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + ibase := (ibase * 256) + HEX_STR_TO_INT(base); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + ibase := ibase * 65536; + when "05"=> + if (ibyte /= 4) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format for record type 05! " + SEVERITY ERROR; + end if; + for i in 0 to (ibyte-1) loop + READ(L=>buf, VALUE=>base,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal Intel Hex Format! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8)); + end loop; + when OTHERS => + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & + "]:Illegal record type in Intel Hex File! " + SEVERITY ERROR; + end case; + READ(L=>buf, VALUE=>checksum,good=>booval); + if not (booval) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Checksum is missing! " + SEVERITY ERROR; + end if; + check_sum_vec := unsigned(not (check_sum_vec)) + 1 ; + check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8); + + if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then + ASSERT FALSE + REPORT "[Line "& INT_TO_STR_RAM(lineno) & "]:Incorrect checksum!" + SEVERITY ERROR; + end if; + end loop; + elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3 to lpm_file'length)) = ".mif") then + -- ************************************************ + -- Read in RAM initialization file (mif) + -- ************************************************ + while not endfile(mem_data_file) loop + booval := true; + readline(mem_data_file, buf); + lineno := lineno + 1; + LOOP2 : while (buf'length > 0) loop + if (buf(buf'low) = '-') then + if (buf(buf'low) = '-') then + -- ignore comment started with --. + exit LOOP2; + end if; + elsif (buf(buf'low) = '%') then + i := 1; + + -- ignore comment which begin with % and end with another %. + while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop + i := i+1; + end loop; + + if (i >= buf'high) then + exit LOOP2; + else + SHRINK_LINE(buf, i+1); + end if; + elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then + i := 1; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i >= buf'high) then + exit LOOP2; + else + SHRINK_LINE(buf, i); + end if; + elsif (get_memory_content = true) then + + if ((buf(buf'low to buf'low +2) = "end") or + (buf(buf'low to buf'low +2) = "END") or + (buf(buf'low to buf'low +2) = "End")) then + get_memory_content := false; + exit LOOP2; + else + get_start_address := false; + get_end_address := false; + m_start_address_int := 0; + m_end_address_int := 0; + m_address_int := 0; + m_data_int := (others => '0'); + if (buf(buf'low) = '[') then + get_start_Address := true; + SHRINK_LINE(buf, 1); + end if; + + case m_address_radix is + when "hex" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *16 + HEX_STR_TO_INT(char); + end loop; + when "bin" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *2 + BIN_STR_TO_INT(char); + end loop; + when "dec" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "uns" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "oct" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *8 + OCT_STR_TO_INT(char); + end loop; + when others => + assert false + report "Unsupported address_radix!" + severity error; + end case; + + if (get_start_Address = true) then + + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then + get_start_Address := false; + get_end_Address := true; + m_start_address_int := m_address_int; + SHRINK_LINE(buf, 2); + end if; + end if; + + if (get_end_address = true) then + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + m_address_int := 0; + case m_address_radix is + when "hex" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *16 + HEX_STR_TO_INT(char); + end loop; + when "bin" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *2 + BIN_STR_TO_INT(char); + end loop; + when "dec" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "uns" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *10 + INT_STR_TO_INT(char); + end loop; + when "oct" => + while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and + (buf(buf'low) /= ']')) loop + read(l => buf, value => char, good => booval); + m_address_int := m_address_int *8 + OCT_STR_TO_INT(char); + end loop; + when others => + assert false + report "Unsupported address_radix!" + severity error; + end case; + + if (buf(buf'low) = ']') then + get_end_address := false; + m_end_address_int := m_address_int; + SHRINK_LINE(buf, 1); + end if; + end if; + + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + if (buf(buf'low) = ':') then + SHRINK_LINE(buf, 1); + end if; + + i := 0; + -- ignore space or tab character. + while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or + (buf(buf'low+i) = HT))) loop + i := i+1; + end loop; + + if (i > 0) then + SHRINK_LINE(buf, i); + end if; + + case m_data_radix is + when "hex" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+4 downto 0) := m_data_int(width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4); + end loop; + when "bin" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+1 downto 0) := m_data_int(width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4); + end loop; + when "dec" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+3 downto 0) := m_data_int(width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4); + end loop; + when "uns" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+3 downto 0) := m_data_int(width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4); + end loop; + when "oct" => + while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and + (buf(buf'low) /= HT)) loop + read(l => buf, value => char, good => booval); + m_data_int(width+3 downto 0) := m_data_int(width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4); + end loop; + when others => + assert false + report "Unsupported data_radix!" + severity error; + end case; + + if (m_start_address_int /= m_end_address_int) then + for i in m_start_address_int to m_end_address_int loop + mem_data(i) := m_data_int(width-1 downto 0); + end loop; + else + mem_data(m_address_int) := m_data_int(width-1 downto 0); + end if; + exit LOOP2; + end if; + elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then + read(l=>buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to i)); + + m_width := INT_STR_TO_INT(m_string(1 to i)); + end if; + exit LOOP2; + elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and + ((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then + read(l=>buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to i)); + + m_depth := INT_STR_TO_INT(m_string(1 to i)); + end if; + exit LOOP2; + elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then + read(l=>buf, value=>m_string(1 to 10)); + + if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to 3)); + + m_data_radix := ALPHA_TOLOWER(m_string(1 to 3)); + end if; + exit LOOP2; + elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then + read(l=>buf, value=>m_string(1 to 13)); + + if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then + i := 0; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + if (buf(buf'low + i) = '=') then + i := i+1; + end if; + + while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop + i := i+1; + end loop; + + SHRINK_LINE(buf, i); + + i := 0; + while (buf(buf'low + i) /= ';') loop + i := i+1; + end loop; + + read(l=>buf, value=>m_string(1 to 3)); + + m_address_radix := ALPHA_TOLOWER(m_string(1 to 3)); + end if; + exit LOOP2; + elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then + read(l=>buf, value=>m_string(1 to 7)); + + if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then + found_keyword_content := true; + end if; + elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then + read(l=>buf, value=>m_string(1 to 5)); + + if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then + if (found_keyword_content = true) then + get_memory_content := true; + end if; + end if; + end if; + end loop; + end loop; + + else + assert false + report "Unsupported memory initialization file type (" & lpm_file(lpm_file'length -3 to lpm_file'length) & ")!" + severity error; + end if; + + + FILE_CLOSE(mem_data_file); + end if; + mem_init := TRUE; + -- + --******************************************* + else -- already initialized + + -- MEMORY FUNCTION -- + -- This is where data is being write to the internal memory: mem_data[] + -- + if (iwren_tmp = '1') then + mem_data (ieee.std_logic_unsigned.conv_integer(iwraddress_tmp)) := idata_tmp; + end if; + + -- Triple-Port Ram (alt3pram) has one write port and two read ports (a and b) + -- Below is the operation to read data from internal memory (mem_data[]) + -- to the output port (iqa_tmp or iqb_tmp) + -- Note: iq*_tmp will serve as the var directly link to the physical + -- output port q* if alt3pram is operate in "Shared Clock Mode", + -- else data read from iq*_tmp will need to be latched to i_q*_reg + -- through outclock before it is fed to the output port q* (qa or qb). + if (irden_tmp_a = '1') then + iqa_tmp <= mem_data(ieee.std_logic_unsigned.conv_integer(irdaddress_tmp_a)); + elsif (rden_low_output_0) then + iqa_tmp <= (OTHERS => '0'); + end if; + + if (irden_tmp_b = '1') then + iqb_tmp <= mem_data(ieee.std_logic_unsigned.conv_integer(irdaddress_tmp_b)); + elsif (rden_low_output_0) then + iqb_tmp <= (OTHERS => '0'); + end if; + + end if; + + end process MEMORY; + +end behavior; -- architecture of alt3pram + +--end of alt3pram + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- entity Name : parallel_add +-- +-- Description : Parameterized parallel adder megafunction. The data input +-- is a concatenated group of input words. The size +-- parameter indicates the number of 'width'-bit words. +-- +-- Each word is added together to generate the result output. +-- Each word is left shifted according to the shift +-- parameter. The shift amount is multiplied by the word +-- index, with the least significant word being word 0. +-- The shift for word I is (shift * I). +-- +-- The most significant word can be subtracted from the total +-- by setting the msw_subtract parameter to 1. +-- if the result width is less than is required to show the +-- full result, the result output can be aligned to the MSB +-- or the LSB of the internal result. when aligning to the +-- MSB, the internally calculated BEST_RESULT_WIDTH is used +-- to find the true MSB. +-- The input data can be signed or unsigned, and the output +-- can be pipelined. +-- +-- Limitations : Minimum data width is 1, and at least 2 words are required. +-- +-- Results expected: result - The sum of all inputs. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; +use work.altera_mf_components.all; + +-- BEGINNING OF ENTITY + +-- ENTITY DECLARATION + +entity parallel_add is +-- GENERIC DECLARATION + generic ( + width : natural := 4; + size : natural := 2; + widthr : natural := 4; + shift : natural := 0; + msw_subtract : string := "NO"; + representation : string := "UNSIGNED"; + pipeline : natural := 0; + result_alignment : string := "LSB"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "parallel_add" ); + +-- PORT DECLARATION + port ( + -- INPUT PORT DECLARATION + data : in altera_mf_logic_2D(size - 1 downto 0, width- 1 downto 0); + clock : in std_logic := '1'; + aclr : in std_logic := '0'; + clken : in std_logic := '1'; + + -- OUTPUT PORT DECLARATION + result : out std_logic_vector(widthr - 1 downto 0) ); +end parallel_add; + +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE + +architecture behaviour OF parallel_add IS + +-- TYPE DECLARATION + TYPE pipeline_type is ARRAY (pipeline downto 0) OF std_logic_vector(widthr - 1 downto 0); + +-- Maximum precision required for internal calculations. +-- This is a pessimistic estimate, but it is guaranteed to be sufficient. +-- The +30 is there only to simplify the test generator, which occasionally asks +-- for output widths far in excess of what is needed. The excess is always less than 30. + constant MAX_PRECISION : natural := (width + size + shift * (size - 1) + 30); + + -- Bitwise Left shift -- Bitwise Left shift + procedure shift_left ( val : inout std_logic_vector; num : in natural) is + variable temp : std_logic_vector((val'length - 1) downto 0); + begin + if num /= 0 then + temp := val; + if (val'length > 1) then + for i in temp'high downto num loop + temp(i) := temp(i- num); + end loop; + for i in num-1 downto 0 loop + temp(i) := '0'; + end loop; + end if; + temp(0) :='0'; + val := temp; + end if; + end shift_left; + + -- Bitwise right shift + procedure shift_right ( val : inout std_logic_vector; num : in natural ) is + variable temp : std_logic_vector(val'length-1 downto 0); + begin + if num /= 0 then + temp := val; + if (val'length > 1) then + for i in 0 to temp'high - 1 loop + if (i + num) <= (temp'high - 1) then + temp(i) := temp(i+num); + else + temp(i) := '0'; + end if; + end loop; + end if; + temp(temp'high) := '0'; + val := temp; + end if; + end shift_right; + + + function ceil_log2 (input_num : in std_logic_vector(MAX_PRECISION - 1 downto 0)) + return natural IS + variable i : natural; + variable try_result : std_logic_vector(MAX_PRECISION - 1 downto 0); + variable ceil_log2 : natural; + begin + i := 0; + try_result := conv_std_logic_vector(1,MAX_PRECISION); + while (i < MAX_PRECISION) loop + shift_left(try_result,1); + if (unsigned(try_result) < unsigned(input_num)) then + i := i + 1; + else + exit; + end if; + end loop; + ceil_log2 := i; + return (ceil_log2); + end ceil_log2; + +-- best_result_width calculation +-- DEFINE CALC_PADD_WIDTHR(w, z, s) = (s == 0) ? CEIL(LOG2(z*((2^w)-1))) : +-- CEIL(LOG2(((2^w)-1) * (2^(z*s)-1) / ((2^s)-1))); + +-- Note: The recommended value for WIDTHR parameter, +-- the width of addition result, for full +-- precision is: +-- if shift = 0 then +-- WIDTHR = CEIL(LOG2( ((2^WIDTH)-1) * SIZE)) +-- +-- +-- if shift /= 0 then +-- ((2^WIDTH)-1) * (2^(SIZE*SHIFT)-1) +-- WIDTHR = CEIL(LOG2(-----------------------------------)) +-- (2^SHIFT)-1 + + function get_best_result_width (shift, width, size : in natural) return natural is + variable best_result_width : natural; + variable input_num : std_logic_vector(MAX_PRECISION - 1 downto 0) := (others => '0'); + variable size_vec : std_logic_vector(size downto 0) := (others => '0'); + variable width_power : std_logic_vector(width downto 0) := (others => '0'); + variable size_shift_power : std_logic_vector((size * shift) downto 0) := (others => '0'); + + variable i_denom : std_logic_vector(width + (size * shift) + 1 downto 0) := (others => '0'); + variable mult_power : std_logic_vector(width + (size * shift) + 1 downto 0) := (others => '0'); + variable max_width : natural; + variable trailing_zero_count : natural; + variable i_remain : std_logic_vector(width + (size * shift) + 1 downto 0) := (others => '0'); + variable i_quotient : std_logic_vector(MAX_PRECISION - 1 downto 0) := (others => '0'); + begin + + -- Convert size natural into std logic vector + size_vec := conv_std_logic_vector(size,size+1); + + -- width_power = (2^WIDTH)-1) + width_power := conv_std_logic_vector(1,width+1); + shift_left(width_power,width+1); + width_power := width_power - '1'; + + if (shift = 0) then + input_num(size + width + 1 downto 0) := (width_power * size_vec); + else + -- size_shift_power = (2^(SIZE*SHIFT)-1) + size_shift_power := conv_std_logic_vector(1, size * shift+1); + shift_left(size_shift_power,size * shift + 1); + size_shift_power := size_shift_power - '1'; + -- i_denom = (2^SHIFT)-1 + i_denom := conv_std_logic_vector(1, width + (size * shift) + 2); + shift_left(i_denom,shift+1); + i_denom := i_denom - '1'; + + -- mult_power := ((2^WIDTH)-1) * (2^(SIZE*SHIFT)-1) + mult_power := (width_power * size_shift_power); + max_width := width + (size * shift) + 1; + + -- perform division using long division algorithm using LPM_DIVIDE method + + trailing_zero_count := 0; + for i in 0 to max_width loop + if i_denom(i) /= '0' then + trailing_zero_count := i; + exit; + end if; + end loop; + + for i in 0 to max_width loop + if i_denom(max_width - i) /= '0' then + shift_left(i_denom,i); + exit; + end if; + end loop; + i_remain := mult_power; + if (unsigned(i_remain) >= unsigned(i_denom)) then + i_remain := i_remain - i_denom; + i_quotient(0) := '1'; + else + i_quotient(0) := '0'; + end if; + + while (i_denom(trailing_zero_count) = '0') loop + shift_right(i_denom,1); + shift_left(i_quotient, 1); + if (unsigned(i_remain) >= unsigned(i_denom)) then + i_remain := i_remain - i_denom; + i_quotient(0) := '1'; + else + i_quotient(0) := '0'; + end if; + end loop; + input_num := i_quotient; + end if; + + best_result_width := ceil_log2(input_num); + return (best_result_width); + end get_best_result_width; + + + + constant BEST_RESULT_WIDTH : natural := get_best_result_width(shift, width, size); +-- constant BEST_RESULT_WIDTH : natural := 33; + + -- INTERNAL SIGNAL DECLARATION + signal isigned : std_logic; + signal imsw_subtract : std_logic; + signal imsb_align : std_logic; + signal aligned_result : std_logic_vector(widthr - 1 downto 0); + signal result_tmp : std_logic_vector(widthr - 1 downto 0); + +begin + + -- checking for invalid parameters + MSG: process + begin + if (width <= 0) then + ASSERT FALSE + REPORT "The width parameter must be greater than 0" + SEVERITY ERROR; + end if; + if (widthr > MAX_PRECISION) then + ASSERT FALSE + REPORT "Error! WIDTHR must not exceed WIDTH+SIZE+SHIFT*(SIZE-1)." + SEVERITY ERROR; + end if; + + if (size < 2) then + ASSERT FALSE + REPORT "Error! SIZE must be greater than 1." + SEVERITY ERROR; + end if; + wait; + end process MSG; + + isigned <= '0' when (representation = "UNSIGNED") else '1'; + imsw_subtract <= '1' when (msw_subtract = "YES") else '0'; + imsb_align <= '1' when (result_alignment = "MSB" and widthr < BEST_RESULT_WIDTH) else '0'; + + + process (data, isigned, imsw_subtract, imsb_align) + variable zero_padding : std_logic_vector(MAX_PRECISION - width - 1 downto 0) + := (others => '0'); + variable one_padding : std_logic_vector(MAX_PRECISION - width - 1 downto 0) + := (others => '1'); + variable tmp_result : std_logic_vector(MAX_PRECISION - 1 downto 0); + variable idata_word : std_logic_vector(width - 1 downto 0); + variable idata : std_logic_vector(MAX_PRECISION - 1 downto 0); + variable idata_extended : std_logic_vector(MAX_PRECISION - 1 downto 0); + variable ni : natural; + variable nj : natural; + begin + tmp_result := (others => '0'); + idata_extended := (others => '0'); + idata_word := (others => '0'); + for ni in 0 to (size - 1) loop + for nj in 0 to (width - 1) loop + idata_word(nj) := '0'; + -- To ensure there is only '1' or '0' in idata_word to avoid any + -- warning arithmetic message . + if (data(ni, nj) = '1') then + idata_word(nj) := '1'; + end if; + end loop; + + if ((isigned = '1') and (idata_word(width - 1) = '1')) then + idata_extended := one_padding & idata_word; + shift_left(idata_extended, (shift * ni)); + else + idata_extended := zero_padding & idata_word; + shift_left(idata_extended,(shift * ni)); + end if; + + if ((imsw_subtract = '1') and (ni = (size - 1))) then + tmp_result := tmp_result - idata_extended; + else + tmp_result := tmp_result + idata_extended; + end if; + + end loop; + + if (imsb_align = '1') then + shift_right(tmp_result, (BEST_RESULT_WIDTH - widthr)); + end if; + aligned_result <= tmp_result(widthr - 1 downto 0); + + end process; + + process (clock, aclr, clken, aligned_result) + variable ni : natural; + variable pipe_ptr : natural := 0; + variable resultpipe : pipeline_type := (others => (others => '0')); + + begin + if (aclr = '1') then + for ni in 0 to (pipeline - 1) loop + resultpipe(ni) := (others => '0'); + end loop; + result_tmp <= (others => '0'); + elsif ((clock = '1') and (clock'last_value = '0') and clock'event and + (clken = '1')) then + resultpipe(pipe_ptr) := aligned_result; + if (pipeline > 1) then + pipe_ptr := (pipe_ptr + 1) mod pipeline; + end if; + result_tmp <= resultpipe(pipe_ptr); + end if; + end process; + + result <= result_tmp when (pipeline > 0) else aligned_result; + +end behaviour; +-- END OF ARCHITECTURE PARALLEL_ADD + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : scfifo +-- +-- Description : Single Clock FIFO +-- +-- Limitation : USE_EAB=OFF is not supported +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use work.ALTERA_DEVICE_FAMILIES.all; + +-- ENTITY DECLARATION +entity SCFIFO is +-- GENERIC DECLARATION + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + lpm_showahead : string := "OFF"; + lpm_type : string := "scfifo"; + lpm_hint : string := "USE_EAB=ON"; + intended_device_family : string := "Stratix"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + allow_rwcycle_when_full : string := "OFF"; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"; + almost_full_value : natural := 0; + almost_empty_value : natural := 0; + maximum_depth : natural := 0 + ); + +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + data : in std_logic_vector(lpm_width-1 downto 0); + clock : in std_logic; + wrreq : in std_logic; + rdreq : in std_logic; + aclr : in std_logic := '0'; + sclr : in std_logic := '0'; +-- OUTPUT PORT DECLARATION + q : out std_logic_vector(lpm_width-1 downto 0); + usedw : out std_logic_vector(lpm_widthu-1 downto 0); + full : out std_logic; + empty : out std_logic; + almost_full : out std_logic; + almost_empty : out std_logic); +end SCFIFO; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of SCFIFO is +-- TYPE DECLARATION +type lpm_memory is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); + +-- CONSTANT DECLARATION +constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +constant NIL : std_logic_vector(2**lpm_widthu-1 downto 0) := (OTHERS => '0'); +constant UNKNOWNS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => 'X'); +constant USEDW_UNKNOWNS : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => 'X'); + +-- SIGNAL DECLARATION +signal i_count_id : integer := 0; +signal i_read_id : integer := 0; +signal i_full_flag : std_logic := '0'; +signal i_empty_flag : std_logic := '1'; +signal i_almost_full_flag : std_logic := '0'; +signal i_almost_empty_flag : std_logic := '1'; +signal i_set_q_to_x : std_logic := '0'; +signal i_set_q_to_x_by_empty : std_logic := '0'; +signal i_tmp_q : std_logic_vector(lpm_width-1 downto 0) := ZEROS; + +signal i_write_id : integer := 0; +signal i_write_latency1 : integer := 0; +signal i_write_latency2 : integer := 0; +signal i_write_latency3 : integer := 0; +signal i_wrt_count : integer := 0; +signal i_empty_latency1 : std_logic := '1'; +signal i_empty_latency2 : std_logic := '1'; +signal i_data_ready : std_logic_vector(2**lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_data_shown : std_logic_vector(2**lpm_widthu-1 downto 0) := (OTHERS => '0'); + +begin +-- PROCESS DECLARATION + process (clock, aclr) + -- VARIABLE DECLARATION + variable mem_data : lpm_memory := (OTHERS => ZEROS); + variable tmp_data : std_logic_vector(lpm_width-1 downto 0) := ZEROS; + variable write_flag : boolean := false; + variable full_flag : boolean := false; + variable valid_rreq : boolean := false; + variable valid_wreq : boolean := false; + variable max_widthu : integer := 0; + variable numwords_minus_one : integer := 0; + variable almost_full_minus_one : integer := 0; + variable almost_empty_minus_one : integer := 0; + variable need_init : boolean := true; + variable stratix_family : boolean := ( FEATURE_FAMILY_STRATIX(intended_device_family) ) ; + variable showahead_area : boolean := (lpm_showahead = "ON" and add_ram_output_register = "OFF"); + variable showahead_speed : boolean := (lpm_showahead = "ON" and add_ram_output_register = "ON"); + variable legacy_speed : boolean := (lpm_showahead = "OFF" and add_ram_output_register = "ON"); + begin + if (need_init) then + if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF")) then + ASSERT FALSE + REPORT "Illegal LPM_SHOWAHEAD property value for SCFIFO!" + SEVERITY ERROR; + end if; + if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) then + ASSERT FALSE + REPORT "Illegal UNDERFLOW_CHECKING property value for SCFIFO!" + SEVERITY ERROR; + end if; + if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) then + ASSERT FALSE + REPORT "Illegal OVERFLOW_CHECKING property value for SCFIFO!" + SEVERITY ERROR; + end if; + if ((allow_rwcycle_when_full /= "ON") and (allow_rwcycle_when_full /= "OFF")) then + ASSERT FALSE + REPORT "Illegal ALLOW_RWCYCLE_WHEN_FULL property value for SCFIFO!" + SEVERITY ERROR; + end if; + if (IS_VALID_FAMILY(intended_device_family) = false) then + ASSERT FALSE + REPORT "Illegal INTENDED_DEVICE_FAMILY for SCFIFO!" + SEVERITY ERROR; + end if; + if ((add_ram_output_register /= "ON") and (add_ram_output_register /= "OFF")) + then + ASSERT FALSE + REPORT "Error! ADD_RAM_OUTPUT_REGISTER must be ON or OFF." + SEVERITY ERROR; + end if; + for i in 0 to (lpm_widthu - 1) loop + if (stratix_family) + then + if ((add_ram_output_register = "ON") or (use_eab = "OFF") or + (FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family))) + then + mem_data(i) := ZEROS; + else + mem_data(i) := UNKNOWNS; + end if; + else + mem_data(i) := ZEROS; + end if; + end loop; + + if (stratix_family) + then + if ((add_ram_output_register = "ON") or (use_eab = "OFF") or + (FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family))) + then + i_tmp_q <= ZEROS; + else + i_tmp_q <= UNKNOWNS; + end if; + else + i_tmp_q <= ZEROS; + end if; + + if (almost_full_value = 0) + then + i_almost_full_flag <= '1'; + else + i_almost_full_flag <= '0'; + end if; + + if (almost_empty_value = 0) + then + i_almost_empty_flag <= '0'; + else + i_almost_empty_flag <= '1'; + end if; + + max_widthu := (2 ** lpm_widthu) - 1; + numwords_minus_one := lpm_numwords - 1; + + almost_full_minus_one := almost_full_value - 1; + almost_empty_minus_one := almost_empty_value - 1; + + i_write_latency1 <= max_widthu+1; + i_write_latency2 <= max_widthu+1; + i_write_latency3 <= max_widthu+1; + + need_init := false; + end if; + + if (aclr = '1') then + full_flag := false; + i_read_id <= 0; + i_count_id <= 0; + i_full_flag <= '0'; + i_empty_flag <= '1'; + i_empty_latency1 <= '1'; + i_empty_latency2 <= '1'; + i_set_q_to_x <= '0'; + i_set_q_to_x_by_empty <= '0'; + i_wrt_count <= 0; + + if (add_ram_output_register = "ON") then + i_tmp_q <= ZEROS; + elsif ((lpm_showahead = "ON") and (use_eab = "ON")) then + i_tmp_q <= UNKNOWNS; + else + if (not stratix_family) then + i_tmp_q <= ZEROS; + else + i_tmp_q <= UNKNOWNS; + end if; + end if; + end if; + + if (clock'event and (clock = '1') and + ((aclr = '0') or (stratix_family))) + then + valid_rreq := rdreq = '1' and ((i_empty_flag = '0') or + (underflow_checking = "OFF")); + valid_wreq := wrreq = '1' and ((i_full_flag = '0') or + (overflow_checking = "OFF") or ((rdreq = '1') and + (allow_rwcycle_when_full = "ON"))); + + + if ((sclr = '1') or (aclr = '1')) + then + if (add_ram_output_register = "ON") then + i_tmp_q <= ZEROS; + else + i_tmp_q <= UNKNOWNS; + end if; + + i_read_id <= 0; + i_count_id <= 0; + i_full_flag <= '0'; + i_empty_flag <= '1'; + i_empty_latency1 <= '1'; + i_empty_latency2 <= '1'; + i_set_q_to_x <= '0'; + i_set_q_to_x_by_empty <= '0'; + i_wrt_count <= 0; + + if (almost_full_value > 0) + then + i_almost_full_flag <= '0'; + end if; + if (almost_empty_value > 0) + then + i_almost_empty_flag <= '1'; + end if; + + full_flag := false; + + if (not(stratix_family)) + then + if (valid_wreq) + then + tmp_data := data; + write_flag := true; + else + i_write_id <= 0; + end if; + else + i_write_id <= 0; + end if; + else + + -- READ operation only + if (valid_rreq) + then + if (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) + then + if (not valid_wreq) + then + i_wrt_count <= i_wrt_count - 1; + end if; + + if (not valid_wreq) + then + i_full_flag <= '0'; + full_flag := false; + + if (i_count_id <= 0) + then + i_count_id <= max_widthu; + else + i_count_id <= i_count_id - 1; + end if; + end if; + + if ((use_eab = "ON") and stratix_family and (showahead_speed or showahead_area or legacy_speed)) + then + if ((i_wrt_count = 1) or ((i_wrt_count = 1) and valid_wreq and valid_rreq)) + then + i_empty_flag <= '1'; + else + if (showahead_speed) + then + if (i_write_latency2 <= max_widthu) + then + if (i_data_shown(i_write_latency2) = '0') + then + i_empty_flag <= '1'; + end if; + end if; + else if (showahead_area or legacy_speed) + then + if (i_write_latency1 <= max_widthu) + then + if (i_data_shown(i_write_latency1) = '0') + then + i_empty_flag <= '1'; + end if; + end if; + end if; + end if; + end if; + else + if (not(valid_wreq)) + then + if (i_count_id = 1 and i_full_flag = '0') + then + i_empty_flag <= '1'; + end if; + end if; + end if; + + if (i_empty_flag = '1') + then + + if (underflow_checking = "ON") then + if ((use_eab = "OFF") or stratix_family) then + i_tmp_q <= ZEROS; + end if; + else + i_set_q_to_x_by_empty <= '1'; + ASSERT FALSE + REPORT "Warning : Underflow occurred! Fifo output is unknown until the next reset is asserted" + SEVERITY WARNING; + end if; + + else + if (i_read_id >= max_widthu) + then + if (lpm_showahead = "ON") + then + if ((use_eab = "ON") and stratix_family and (showahead_speed or showahead_area)) + then + if (showahead_speed) + then + if ((i_write_latency2 = ZEROS) or (i_data_ready(0) = '1')) + then + if (i_data_shown(0) = '1') + then + i_tmp_q <= mem_data(0); + i_data_shown(0) <= '0'; + i_data_ready(0) <= '0'; + end if; + end if; + else + if (i_count_id = 1 and i_full_flag = '0') + then + if (underflow_checking = "ON") then + if ((use_eab = "OFF") or stratix_family) then + i_tmp_q <= ZEROS; + end if; + else + i_tmp_q <= UNKNOWNS; + end if; + else + if ((i_write_latency1 = ZEROS) or (i_data_ready(0) = '1')) + then + if (i_data_shown(0) = '1') + then + i_tmp_q <= mem_data(0); + i_data_shown(0) <= '0'; + i_data_ready(0) <= '0'; + end if; + end if; + end if; + end if; + else + if (i_count_id = 1 and i_full_flag = '0') + then + if (valid_wreq) + then + i_tmp_q <= data; + else + if (underflow_checking = "ON") then + if ((use_eab = "OFF") or stratix_family) then + i_tmp_q <= ZEROS; + end if; + else + i_tmp_q <= UNKNOWNS; + end if; + end if; + else + i_tmp_q <= mem_data(0); + end if; + end if; + else + if ((use_eab = "ON") and (stratix_family and legacy_speed)) + then + if ((i_write_latency1 = i_read_id) or (i_data_ready(i_read_id) = '1')) + then + if (i_data_shown(i_read_id) = '1') + then + i_tmp_q <= mem_data(i_read_id); + i_data_shown(i_read_id) <= '0'; + i_data_ready(i_read_id) <= '0'; + end if; + else + i_tmp_q <= UNKNOWNS; + end if; + else + i_tmp_q <= mem_data(i_read_id); + end if; + end if; + + i_read_id <= 0; + else + if (lpm_showahead = "ON") + then + if ((use_eab = "ON") and (stratix_family and (showahead_speed or showahead_area))) + then + if (showahead_speed) + then + if ((i_write_latency2 = i_read_id+1) or (i_data_ready(i_read_id+1) = '1')) + then + if (i_data_shown(i_read_id+1) = '1') + then + i_tmp_q <= mem_data(i_read_id + 1); + i_data_shown(i_read_id+1) <= '0'; + i_data_ready(i_read_id+1) <= '0'; + end if; + end if; + else + if (i_count_id = 1 and i_full_flag = '0') + then + if (underflow_checking = "ON") then + if ((use_eab = "OFF") or stratix_family) then + i_tmp_q <= ZEROS; + end if; + else + i_tmp_q <= UNKNOWNS; + end if; + else + if ((i_write_latency1 = i_read_id+1) or (i_data_ready(i_read_id+1) = '1')) + then + if (i_data_shown(i_read_id+1) = '1') + then + i_tmp_q <= mem_data(i_read_id + 1); + i_data_shown(i_read_id+1) <= '0'; + i_data_ready(i_read_id+1) <= '0'; + end if; + end if; + end if; + end if; + else + if (i_count_id = 1 and i_full_flag = '0') + then + if ((use_eab = "OFF") and stratix_family) + then + if (valid_wreq) then + i_tmp_q <= data; + else + if (underflow_checking = "ON") then + i_tmp_q <= ZEROS; + else + i_tmp_q <= UNKNOWNS; + end if; + end if; + else + i_tmp_q <= UNKNOWNS; + end if; + else + i_tmp_q <= mem_data(i_read_id + 1); + end if; + end if; + else + if ((use_eab = "ON") and stratix_family and legacy_speed) + then + if ((i_write_latency1 = i_read_id) or (i_data_ready(i_read_id) = '1')) + then + if (i_data_shown(i_read_id) = '1') + then + i_tmp_q <= mem_data(i_read_id); + i_data_shown(i_read_id) <= '0'; + i_data_ready(i_read_id) <= '0'; + end if; + else + i_tmp_q <= UNKNOWNS; + end if; + else + i_tmp_q <= mem_data(i_read_id); + end if; + end if; + + i_read_id <= i_read_id + 1; + end if; + end if; + end if; + end if; + + -- WRITE operation only + if (valid_wreq) + then + if (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) + then + if ((overflow_checking = "OFF") and full_flag) + then + i_set_q_to_x <= '1'; + ASSERT FALSE + REPORT "Warning : Overflow occurred! Fifo output is unknown until the next reset is asserted" + SEVERITY WARNING; + else + tmp_data := data; + write_flag := true; + + if (not((use_eab = "ON") and (stratix_family) and (showahead_speed or showahead_area or legacy_speed))) + then + i_empty_flag <= '0'; + else + i_empty_latency1 <= '0'; + end if; + + if (not valid_rreq) + then + i_wrt_count <= i_wrt_count + 1; + end if; + + if (not valid_rreq) + then + if (i_count_id >= max_widthu) + then + i_count_id <= 0; + else + i_count_id <= i_count_id + 1; + end if; + else + if (allow_rwcycle_when_full = "OFF") + then + i_full_flag <= '0'; + end if; + end if; + + if (not(stratix_family) or(stratix_family and not(showahead_speed or showahead_area or legacy_speed))) + then + if (not valid_rreq) + then + if ((i_count_id = numwords_minus_one) and (i_empty_flag = '0')) + then + i_full_flag <= '1'; + full_flag := true; + end if; + end if; + else + if (not valid_rreq) + then + if (i_count_id = numwords_minus_one) + then + i_full_flag <= '1'; + full_flag := true; + end if; + end if; + end if; + + if (lpm_showahead = "ON") + then + if ((use_eab = "ON") and (stratix_family) and (showahead_speed or showahead_area)) + then + i_write_latency1 <= i_write_id; + + if (i_write_id <= max_widthu) + then + i_data_shown(i_write_id) <= '1'; + i_data_ready(i_write_id) <= 'X'; + end if; + else + if ((use_eab = "OFF") and stratix_family and (i_count_id = 0) and (not full_flag)) + then + i_tmp_q <= data; + else + if ((not i_empty_flag = '0') and (not valid_rreq)) + then + i_tmp_q <= mem_data(i_read_id); + end if; + end if; + end if; + else + if ((use_eab = "ON") and stratix_family and legacy_speed) + then + i_write_latency1 <= i_write_id; + + if (i_write_id <= max_widthu) + then + i_data_shown(i_write_id) <= '1'; + i_data_ready(i_write_id) <= 'X'; + end if; + end if; + end if; + end if; + end if; + end if; + + if (almost_full_value = 0) + then + i_almost_full_flag <= '1'; + elsif (lpm_numwords = almost_full_value) + then + if (full_flag) + then + i_almost_full_flag <= '1'; + else + i_almost_full_flag <= '0'; + end if; + else + if (i_almost_full_flag = '1') + then + if ((i_count_id = almost_full_value) and (wrreq = '0') and + (rdreq = '1')) + then + i_almost_full_flag <= '0'; + end if; + else + if ((almost_full_value = 1) and (i_count_id = 0) and (wrreq = '1')) + then + i_almost_full_flag <= '1'; + elsif ((almost_full_value > 1) and (i_count_id = almost_full_minus_one) + and (wrreq = '1') and (rdreq = '0')) + then + i_almost_full_flag <= '1'; + end if; + end if; + end if; + + if (almost_empty_value = 0) + then + i_almost_empty_flag <= '0'; + elsif (lpm_numwords = almost_empty_value) + then + if (full_flag) + then + i_almost_empty_flag <= '0'; + else + i_almost_empty_flag <= '1'; + end if; + else + if (i_almost_empty_flag = '1') + then + if ((almost_empty_value = 1) and (i_count_id = 0) and (wrreq = '1')) + then + i_almost_empty_flag <= '0'; + elsif ((almost_empty_value > 1) and (i_count_id = almost_empty_minus_one) + and (wrreq = '1') and (rdreq = '0')) + then + i_almost_empty_flag <= '0'; + end if; + else + if ((i_count_id = almost_empty_value) and (wrreq = '0') and + (rdreq = '1')) + then + i_almost_empty_flag <= '1'; + end if; + end if; + end if; + end if; + + if ((clock'event and (clock = '1')) and ((use_eab = "ON") and stratix_family)) + then + if (showahead_speed) + then + i_write_latency2 <= i_write_latency1; + i_write_latency3 <= i_write_latency2; + + if (i_write_latency3 /= i_write_latency2) + then + if (i_write_latency2 <= max_widthu) + then + i_data_ready(i_write_latency2) <= '1'; + end if; + end if; + + i_empty_latency2 <= i_empty_latency1; + + if ((aclr = '1') or (sclr = '1')) + then + i_write_latency1 <= max_widthu+1; + i_write_latency2 <= max_widthu+1; + i_data_shown <= NIL; + if (add_ram_output_register = "ON") then + i_tmp_q <= ZEROS; + else + i_tmp_q <= UNKNOWNS; + end if; + end if; + + if (i_write_latency2 <= max_widthu) + then + if (i_data_shown(i_write_latency2) = '1') + then + if ((i_read_id = i_write_latency2) or (aclr = '1') or (sclr = '1')) + then + if (not (aclr = '1') and (not(sclr = '1'))) + then + i_tmp_q <= mem_data(i_write_latency2); + i_data_shown(i_write_latency2) <= '0'; + i_data_ready(i_write_latency2) <= '0'; + + if (not valid_rreq) + then + i_empty_flag <= i_empty_latency2; + end if; + end if; + end if; + end if; + end if; + elsif (showahead_area) + then + i_write_latency2 <= i_write_latency1; + + if (i_write_latency2 /= i_write_latency1) + then + if (i_write_latency1 <= max_widthu) + then + i_data_ready(i_write_latency1) <= '1'; + end if; + end if; + + if ((aclr = '1') or (sclr = '1')) + then + i_write_latency1 <= max_widthu+1; + i_write_latency2 <= max_widthu+1; + i_data_shown <= NIL; + if (add_ram_output_register = "ON") then + i_tmp_q <= ZEROS; + else + i_tmp_q <= UNKNOWNS; + end if; + end if; + + if (i_write_latency1 <= max_widthu) + then + if (i_data_shown(i_write_latency1) = '1') + then + if ((i_read_id = i_write_latency1) or (aclr = '1') or (sclr = '1')) + then + if (not (aclr = '1') and (not(sclr = '1'))) + then + i_tmp_q <= mem_data(i_write_latency1); + i_data_shown(i_write_latency1) <= '0'; + i_data_ready(i_write_latency1) <= '0'; + + if (not valid_rreq) + then + i_empty_flag <= i_empty_latency1; + end if; + end if; + end if; + end if; + end if; + else + if (legacy_speed) + then + i_write_latency2 <= i_write_latency1; + + if (i_write_latency2 /= i_write_latency1) + then + if (i_write_latency1 <= max_widthu) + then + i_data_ready(i_write_latency1) <= '1'; + end if; + end if; + + if ((aclr = '1') or (sclr = '1')) + then + i_write_latency1 <= max_widthu+1; + i_write_latency2 <= max_widthu+1; + i_data_shown <= NIL; + if (add_ram_output_register = "ON") then + i_tmp_q <= ZEROS; + else + i_tmp_q <= UNKNOWNS; + end if; + end if; + + if ((i_wrt_count = 0 and (not valid_wreq)) or (aclr = '1') or (sclr = '1') or (i_wrt_count = 1 and valid_rreq and (not valid_wreq))) + then + i_empty_flag <= '1'; + i_empty_latency1 <= '1'; + else + if (i_wrt_count = 1 and valid_wreq and valid_rreq) + then + i_empty_flag <= '1'; + else + i_empty_flag <= i_empty_latency1; + end if; + end if; + end if; + end if; + end if; + elsif (clock'event and (clock = '0')) + then + if (write_flag) + then + write_flag := false; + mem_data(i_write_id) := tmp_data; + + if ((aclr = '1') or (sclr = '1') or (i_write_id >= max_widthu)) + then + i_write_id <= 0; + else + i_write_id <= i_write_id + 1; + end if; + end if; + + if (not(stratix_family)) + then + if (not i_empty_flag = '1') + then + if (lpm_showahead = "ON") + then + i_tmp_q <= mem_data(i_read_id); + end if; + end if; + end if; + end if; + + if (aclr = '1') then + i_full_flag <= '0'; + i_empty_flag <= '1'; + if (almost_full_value > 0) + then + i_almost_full_flag <= '0'; + end if; + if (almost_empty_value > 0) + then + i_almost_empty_flag <= '1'; + end if; + + i_read_id <= 0; + i_write_id <= 0; + i_count_id <= 0; + i_set_q_to_x <= '0'; + i_wrt_count <= 0; + end if; + + end process; + + q <= i_tmp_q when (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) else UNKNOWNS; + full <= i_full_flag when (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) else 'X'; + empty <= i_empty_flag when (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) else 'X'; + almost_full <= i_almost_full_flag when (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) else 'X'; + almost_empty <= i_almost_empty_flag when (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) else 'X'; + usedw <= conv_std_logic_vector(i_count_id, lpm_widthu) when (not ((i_set_q_to_x = '1') or (i_set_q_to_x_by_empty = '1'))) else USEDW_UNKNOWNS ; + +end behavior; -- scfifo +-- END OF ARCHITECTURE + + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : dcfifo_dffpipe +-- +-- Description : Dual Clocks FIFO +-- +-- Limitation : +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +-- ENTITY DECLARATION +entity DCFIFO_DFFPIPE is +-- GENERIC DECLARATION + generic ( + lpm_delay : natural; + lpm_width : natural); +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + d : in std_logic_vector (lpm_width-1 downto 0); + clock : in std_logic; + aclr : in std_logic := '0'; +-- OUTPUT PORT DECLARATION + q : out std_logic_vector (lpm_width-1 downto 0)); +end DCFIFO_DFFPIPE; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of DCFIFO_DFFPIPE is +-- TYPE DECLARATION +type DELAYPIPE is array (lpm_delay downto 0) of std_logic_vector (lpm_width-1 downto 0); + +-- CONSTANT DECLARATION +constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +begin + +-- PROCESS DECLARATION + process (clock, aclr, d) +------ VARIABLE DECLARATION + variable intpipe : DELAYPIPE := (OTHERS => ZEROS); + variable delay : integer := lpm_delay - 1; + variable need_init : boolean := true; + begin + if (lpm_delay = 0) + then + if ((aclr = '1') or need_init) + then + q <= ZEROS; + need_init := false; + else + q <= d; + end if; + else + if ((aclr = '1') or need_init) + then + for i in lpm_delay downto 0 loop + intpipe(i) := ZEROS; + end loop; + need_init := false; + q <= ZEROS; + end if; + + if (clock'event and (clock = '1') and (NOW > 0 ns)) + then + if (delay > 0) then + for i in delay downto 1 loop + intpipe(i) := intpipe(i-1); + end loop; + end if; + intpipe(0) := d; + q <= intpipe(delay); + end if; + end if; -- (lpm_delay = 0) + end process; -- clock, aclr, d events +end behavior; -- dcfifo_dffpipe +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : dcfifo_fefifo +-- +-- Description : Dual Clocks FIFO +-- +-- Limitation : +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +-- ENTITY DECLARATION +entity DCFIFO_FEFIFO is +-- GENERIC DECLARATION + generic ( + lpm_widthad : natural; + lpm_numwords : natural; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + lpm_mode : string); +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + usedw_in : in std_logic_vector(lpm_widthad-1 downto 0); + wreq : in std_logic := 'Z'; + rreq : in std_logic := 'Z'; + clock : in std_logic; + aclr : in std_logic := '0'; +-- OUTPUT PORT DECLARATION + empty : out std_logic; + full : out std_logic); +end DCFIFO_FEFIFO; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of DCFIFO_FEFIFO is + +-- SIGNAL DECLARATION +signal i_empty : std_logic := '1'; +signal i_full : std_logic := '0'; + +begin + +-- PROCESS DECLARATION + process (clock, aclr) +------ VARIABLE DECLARATION + variable sm_empty : std_logic_vector(1 downto 0) := "00"; + variable lrreq : std_logic := '0'; + variable almost_full : integer := 0; + variable usedw_is_1 : boolean := false; + variable need_init : boolean := true; + begin + if (need_init) + then + if ((lpm_mode /= "READ") and (lpm_mode /= "WRITE")) + then + ASSERT FALSE + REPORT "Error! LPM_MODE must be READ or WRITE." + SEVERITY ERROR; + end if; + if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! OVERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + + if (lpm_numwords >= 3) + then + almost_full := lpm_numwords - 3; + else + almost_full := 0; + end if; + + need_init := false; + end if; -- need_init + + if (aclr'event and (aclr = '1')) + then + sm_empty := "00"; + lrreq := '0'; + + i_empty <= '1'; + i_full <= '0'; + end if; -- aclr event + + if (clock'event and (clock = '1') and (aclr = '0') and (NOW > 0 ns)) + then + if (lpm_mode = "READ") + then + case sm_empty is + -- state_empty + when "00" => + if (usedw_in /= 0) + then + sm_empty := "01"; + end if; + -- state_non_empty + when "01" => + if (lpm_widthad > 1) + then + usedw_is_1 := ((usedw_in = 1) and (lrreq = '0')) or ((usedw_in = 2) and (lrreq = '1')); + else + usedw_is_1 := (usedw_in = 1) and (lrreq = '0'); + end if; + + if ((rreq = '1') and usedw_is_1) + then + sm_empty := "10"; + end if; + -- state_emptywait + when "10" => + if (usedw_in > 1) + then + sm_empty := "01"; + else + sm_empty := "00"; + end if; + when others => + ASSERT FALSE + REPORT "Error! Invalid sm_empty state in read mode." + SEVERITY ERROR; + end case; + elsif (lpm_mode = "WRITE") + then + case sm_empty is + -- state_empty + when "00" => + if (wreq = '1') + then + sm_empty := "01"; + end if; + -- state_one + when "01" => + if (wreq = '0') + then + sm_empty := "11"; + end if; + -- state_non_empty + when "11" => + if (wreq = '1') + then + sm_empty := "01"; + elsif (usedw_in = 0) + then + sm_empty := "00"; + end if; + when others => + ASSERT FALSE + REPORT "Error! Invalid sm_empty state in write mode." + SEVERITY ERROR; + end case; + end if; + + i_empty <= not sm_empty(0); + if ((aclr = '0') and (usedw_in >= almost_full) and (NOW > 0 ns)) + then + i_full <= '1'; + else + i_full <= '0'; + end if; + + if (underflow_checking = "OFF") + then + lrreq := rreq; + else + lrreq := rreq and not i_empty; + end if; + end if; -- clock event + end process; -- clock, aclr events + + empty <= i_empty; + full <= i_full; + +end behavior; -- dcfifo_fefifo +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : dcfifo_async +-- +-- Description : Asynchoronous Dual Clocks FIFO +-- +-- Limitation : +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.DCFIFO_FEFIFO; +use work.DCFIFO_DFFPIPE; + +-- ENTITY DECLARATION +entity DCFIFO_ASYNC is +-- GENERIC DECLARATION + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + delay_rdusedw : natural := 1; + delay_wrusedw : natural := 1; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"; + clocks_are_synchronized : string := "FALSE"; + lpm_hint : string := "USE_EAB=ON"); +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + rdreq : in std_logic; + wrreq : in std_logic; + aclr : in std_logic := '0'; +-- OUTPUT PORT DECLARATION + rdempty : out std_logic; + wrempty : out std_logic; + rdfull : out std_logic; + wrfull : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width-1 downto 0)); +end DCFIFO_ASYNC; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of DCFIFO_ASYNC is +-- TYPE DECLARATION +type LPM_MEMORY is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); +type LPM_BOOLEAN is array (2**lpm_widthu-1 downto 0) of boolean; +type LPM_NATURAL is array (2**lpm_widthu-1 downto 0) of natural; + +-- CONSTANT DECLARATION +constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +constant UNKNOWN : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => 'X'); +constant ZEROU : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +constant GRAY_DELAYPIPE : integer := 1; +constant WRUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full +constant RDUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full + +-- SIGNAL DECLARATION +signal i_data_tmp : std_logic_vector(lpm_width-1 downto 0); +signal i_rdptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wrptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wrptr_tmp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rdptrrg : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wrdelaycycle : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rden : std_logic := '0'; +signal i_wren : std_logic := '0'; +signal i_rdenclock : std_logic := '0'; +signal i_wren_tmp : std_logic := '0'; +signal i_rdempty : std_logic := '1'; +signal i_wrempty : std_logic := '1'; +signal i_rdfull : std_logic := '0'; +signal i_wrfull : std_logic := '0'; +signal i_rdusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wrusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_ws_nbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rs_nbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_ws_dbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rs_dbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wr_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rd_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wr_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rd_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_q_tmp : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +signal i_showahead_flag : std_logic := '0'; +signal i_showahead_flag1 : std_logic := '0'; +signal i_showahead_flag2 : std_logic := '0'; +signal i_showahead_flag3 : std_logic := '0'; +signal i_data_ready : LPM_BOOLEAN := (OTHERS => false); +signal i_data_delay_count : LPM_NATURAL := (OTHERS => 0); +signal i_zero : std_logic := '0'; + + +-- COMPONENT DECLARATION +component DCFIFO_FEFIFO + generic ( + lpm_widthad : natural; + lpm_numwords : natural; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + lpm_mode : string); + port ( + usedw_in : in std_logic_vector(lpm_widthad-1 downto 0); + wreq : in std_logic := 'Z'; + rreq : in std_logic := 'Z'; + clock : in std_logic; + aclr : in std_logic := '0'; + empty : out std_logic; + full : out std_logic); +end component; + +component DCFIFO_DFFPIPE + generic ( + lpm_delay : natural; + lpm_width : natural); + port ( + d : in std_logic_vector(lpm_width-1 downto 0); + clock : in std_logic; + aclr : in std_logic := '0'; + q : out std_logic_vector(lpm_width-1 downto 0)); +end component; + +begin +-- COMPONENT ASSIGNMENTS + -- Delays & DFF Pipes + DP_RDPTR_D: DCFIFO_DFFPIPE + generic map ( + lpm_delay => 0, + lpm_width => lpm_widthu) + port map ( + d => i_rdptr, + clock => i_rdenclock, + aclr => aclr, + q => i_rdptrrg); + + DP_WRPTR_D: DCFIFO_DFFPIPE + generic map ( + lpm_delay => 1, + lpm_width => lpm_widthu) + port map ( + d => i_wrptr, + clock => wrclk, + aclr => aclr, + q => i_wrdelaycycle); + + DP_WS_NBRP: DCFIFO_DFFPIPE + generic map ( + lpm_delay => WRSYNC_DELAYPIPE, + lpm_width => lpm_widthu) + port map ( + d => i_rdptrrg, + clock => wrclk, + aclr => aclr, + q => i_ws_nbrp); + + DP_RS_NBWP: DCFIFO_DFFPIPE + generic map ( + lpm_delay => RDSYNC_DELAYPIPE, + lpm_width => lpm_widthu) + port map ( + d => i_wrdelaycycle, + clock => rdclk, + aclr => aclr, + q => i_rs_nbwp); + + DP_WS_DBRP: DCFIFO_DFFPIPE + generic map ( + lpm_delay => GRAY_DELAYPIPE, + lpm_width => lpm_widthu) + port map ( + d => i_ws_nbrp, + clock => wrclk, + aclr => aclr, + q => i_ws_dbrp); + + DP_RS_DBWP: DCFIFO_DFFPIPE + generic map ( + lpm_delay => GRAY_DELAYPIPE, + lpm_width => lpm_widthu) + port map ( + d => i_rs_nbwp, + clock => rdclk, + aclr => aclr, + q => i_rs_dbwp); + + DP_WR_USEDW: DCFIFO_DFFPIPE + generic map ( + lpm_delay => DELAY_WRUSEDW, + lpm_width => lpm_widthu) + port map ( + d => i_wr_udwn, + clock => wrclk, + aclr => aclr, + q => i_wrusedw); + + DP_RD_USEDW: DCFIFO_DFFPIPE + generic map ( + lpm_delay => DELAY_RDUSEDW, + lpm_width => lpm_widthu) + port map ( + d => i_rd_udwn, + clock => rdclk, + aclr => aclr, + q => i_rdusedw); + + DP_WR_DBUW: DCFIFO_DFFPIPE + generic map ( + lpm_delay => WRUSEDW_DELAYPIPE, + lpm_width => lpm_widthu) + port map ( + d => i_wr_udwn, + clock => wrclk, + aclr => aclr, + q => i_wr_dbuw); + + DP_RD_DBUW: DCFIFO_DFFPIPE + generic map ( + lpm_delay => RDUSEDW_DELAYPIPE, + lpm_width => lpm_widthu) + port map ( + d => i_rd_udwn, + clock => rdclk, + aclr => aclr, + q => i_rd_dbuw); + + -- Empty/Full + WR_FE: DCFIFO_FEFIFO + generic map ( + lpm_widthad => lpm_widthu, + lpm_numwords => lpm_numwords, + underflow_checking => UNDERFLOW_CHECKING, + overflow_checking => OVERFLOW_CHECKING, + lpm_mode => "WRITE") + port map ( + usedw_in => i_wr_dbuw, + wreq => wrreq, + rreq => i_zero, + clock => wrclk, + aclr => aclr, + empty => i_wrempty, + full => i_wrfull); + + RD_FE: DCFIFO_FEFIFO + generic map ( + lpm_widthad => lpm_widthu, + lpm_numwords => lpm_numwords, + underflow_checking => underflow_checking, + overflow_checking => overflow_checking, + lpm_mode => "READ") + port map ( + usedw_in => i_rd_dbuw, + wreq => i_zero, + rreq => rdreq, + clock => rdclk, + aclr => aclr, + empty => i_rdempty, + full => i_rdfull); + +-- PROCESS DECLARATION + -- FIFOram + process (wrclk, rdclk, aclr, i_showahead_flag) +------ VARIABLE DECLARATION + variable max_widthu : integer := 0; + variable max_widthu_minus_one : integer := 0; + variable mem_data : LPM_MEMORY := (OTHERS => ZEROS); + variable mem_data2 : LPM_MEMORY := (OTHERS => ZEROS); + variable wrptr_tmp : integer := 0; + variable rdptr_tmp : integer := 0; + variable need_init : boolean := true; + begin + if (need_init) then + if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF")) + then + ASSERT FALSE + REPORT "Error! LPM_SHOWAHEAD must be ON or OFF." + SEVERITY ERROR; + end if; + if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! OVERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + if ((use_eab /= "ON") and (use_eab /= "OFF")) + then + ASSERT FALSE + REPORT "Error! USE_EAB must be ON or OFF." + SEVERITY ERROR; + end if; + if ((add_ram_output_register /= "ON") and (add_ram_output_register /= "OFF")) + then + ASSERT FALSE + REPORT "Error! ADD_RAM_OUTPUT_REGISTER must be ON or OFF." + SEVERITY ERROR; + end if; + if (IS_VALID_FAMILY(intended_device_family) = false) then + ASSERT FALSE + REPORT "Error! Illegal INTENDED_DEVICE_FAMILY." + SEVERITY ERROR; + end if; + + max_widthu := 2 ** lpm_widthu; + max_widthu_minus_one := (2 ** lpm_widthu) - 1; + + for i in lpm_numwords - 1 downto 0 loop + mem_data(i) := ZEROS; + end loop; + + if ((add_ram_output_register = "OFF") and + (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + then + for i in 0 to max_widthu_minus_one loop + mem_data2(i) := UNKNOWN; + end loop; + else + for i in 0 to max_widthu_minus_one loop + mem_data2(i) := ZEROS; + end loop; + end if; + + need_init := false; + end if; -- need_init + + if (aclr'event and (aclr = '1')) + then + i_rdptr <= ZEROU; + i_wrptr <= ZEROU; + if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or + (use_eab = "OFF")) + then + if (lpm_showahead = "ON") + then + i_q_tmp <= mem_data(0); + else + i_q_tmp <= ZEROS; + end if; + elsif ((add_ram_output_register = "ON") and + (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + then + if (lpm_showahead = "OFF") + then + i_q_tmp <= ZEROS; + else + i_q_tmp <= UNKNOWN; + + for i in 0 to max_widthu_minus_one loop + i_data_ready(i) <= false; + i_data_delay_count(i) <= 0; + end loop; + end if; + end if; + end if; -- aclr event + + if (wrclk'event and (wrclk = '1')) + then + if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or + (add_ram_output_register = "ON") or (use_eab = "OFF"))) + then + i_data_tmp <= ZEROS; + i_wrptr_tmp <= ZEROU; + i_wren_tmp <= '0'; + elsif (NOW > 0 ns) + then + i_data_tmp <= data; + i_wrptr_tmp <= i_wrptr; + i_wren_tmp <= i_wren; + + if (i_wren = '1') + then + if ((aclr = '0') and (i_wrptr < max_widthu_minus_one)) + then + i_wrptr <= i_wrptr + 1; + else + i_wrptr <= ZEROU; + end if; + + if (use_eab = "OFF") + then + mem_data(CONV_INTEGER(i_wrptr) mod max_widthu) := data; + + if (lpm_showahead = "ON") + then + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu); + end if; + end if; + end if; + end if; + end if; + + if (wrclk'event and (wrclk = '0')) + then + if ((use_eab = "ON") and (NOW > 0 ns)) + then + if (i_wren_tmp = '1') + then + wrptr_tmp := CONV_INTEGER(i_wrptr_tmp) mod max_widthu; + mem_data(wrptr_tmp) := i_data_tmp; + i_data_ready(wrptr_tmp) <= false; + end if; + + if ((lpm_showahead = "ON") and + (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))) + then + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu); + end if; + end if; + end if; -- wrclk'event and (wrclk = '0') + + if ((rdclk'event) and (rdclk = '1') and (NOW > 0 ns)) + then + if ((lpm_showahead = "ON") and (add_ram_output_register = "ON") and + (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + then + for i in 0 to max_widthu_minus_one loop + if (i_data_ready(i) = false) + then + i_data_delay_count(i) <= i_data_delay_count(i) + 1; + end if; + + if (i_data_delay_count(i) = (rdsync_delaypipe+2)) + then + i_data_ready(i) <= true; + i_data_delay_count(i) <= 0; + end if; + end loop; + + if (aclr = '0') + then + i_showahead_flag3 <= '1'; + end if; + end if; + + if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or (use_eab = "OFF"))) + then + if (lpm_showahead = "ON") + then + i_q_tmp <= mem_data(0); + else + i_q_tmp <= ZEROS; + end if; + elsif ((aclr = '1') and (add_ram_output_register = "ON") and + (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + then + if (lpm_showahead = "ON") + then + i_q_tmp <= UNKNOWN; + else + i_q_tmp <= ZEROS; + end if; + elsif ((i_rden = '1') and (NOW > 0 ns)) + then + if ((aclr = '0') and (i_rdptr < max_widthu_minus_one)) + then + i_rdptr <= i_rdptr + 1; + else + i_rdptr <= ZEROU; + end if; + + if (lpm_showahead = "ON") + then + if ((add_ram_output_register = "ON") and + (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + then + i_showahead_flag3 <= '1'; + else + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr + 1) mod max_widthu); + end if; + else + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu); + end if; + end if; + end if; -- (rdclk'event) and (rdclk = '1') + + if (i_showahead_flag'event and (i_showahead_flag = '1')) + then + if ((lpm_showahead = "ON") and (add_ram_output_register = "ON") and + (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) + then + if (i_rdempty = '0') + then + rdptr_tmp := CONV_INTEGER(i_rdptr) mod max_widthu; + if (i_data_ready(rdptr_tmp) = true) + then + i_q_tmp <= mem_data(rdptr_tmp); + mem_data2(rdptr_tmp) := mem_data(rdptr_tmp); + else + i_q_tmp <= mem_data2(rdptr_tmp); + end if; + end if; + end if; + i_showahead_flag3 <= '0'; + end if; + + end process; -- aclr, wrclk, rdclk events + + process (i_showahead_flag3) + begin + i_showahead_flag2 <= i_showahead_flag3; + end process; + + process (i_showahead_flag2) + begin + i_showahead_flag1 <= i_showahead_flag2; + end process; + + process (i_showahead_flag1) + begin + i_showahead_flag <= i_showahead_flag1; + end process; + + i_rden <= rdreq when underflow_checking = "OFF" else + rdreq and not i_rdempty; + i_wren <= wrreq when overflow_checking = "OFF" else + wrreq and not i_wrfull; + + -- Delays & DFF Pipes + process (rdclk) + begin + if (rdclk'event and (rdclk = '0')) + then + i_rdenclock <= '0'; + elsif (rdclk'event and (rdclk = '1')) + then + if (i_rden = '1') + then + i_rdenclock <= '1'; + end if; + end if; + end process; -- rdclk event + + process (i_wrptr, i_ws_dbrp) + begin + if (NOW > 0 ns) + then + i_wr_udwn <= i_wrptr - i_ws_dbrp; + end if; + end process; -- i_wrptr, i_ws_dbrp events + + process (i_rdptr, i_rs_dbwp) + begin + if (NOW > 0 ns) + then + i_rd_udwn <= i_rs_dbwp - i_rdptr; + end if; + end process; -- i_rdptr, i_rs_dbwp events + + -- Outputs + rdempty <= i_rdempty; + rdfull <= i_rdfull; + wrempty <= i_wrempty; + wrfull <= i_wrfull; + rdusedw <= i_rdusedw; + wrusedw <= i_wrusedw; + q <= i_q_tmp; + +end behavior; -- dcfifo_async +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : dcfifo_sync +-- +-- Description : Synchronous Dual Clocks FIFO +-- +-- Limitation : +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.DCFIFO_DFFPIPE; + +-- ENTITY DECLARATION +entity DCFIFO_SYNC is +-- GENERIC DECLARATION + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"); + +-- PORT DECLARATION + port + ( +-- INPUT PORT DECLARATION + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; +-- OUTPUT PORT DECLARATION + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width-1 downto 0)); +end DCFIFO_SYNC; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of DCFIFO_SYNC is +-- TYPE DECLARATION +type LPM_MEMORY is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0); + +-- CONSTANT DECLARATION +constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +constant ZEROU : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); + +-- SIGNAL DECLARATION +signal i_data_tmp : std_logic_vector(lpm_width-1 downto 0); +signal i_rdptr : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_wrptr : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_wrptr_tmp : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_rdptr_s : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_wrptr_r : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_wrptr_s : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_rdempty : std_logic := '1'; +signal i_wrempty : std_logic := '1'; +signal i_rdfull : std_logic := '0'; +signal i_wrfull : std_logic := '0'; +signal i_rden : std_logic := '0'; +signal i_wren : std_logic := '0'; +signal i_wren_tmp : std_logic := '0'; +signal i_rdusedw : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_wrusedw : std_logic_vector(lpm_widthu downto 0) := (OTHERS => '0'); +signal i_q_tmp : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +signal i_cnt_mod : natural := 0; +signal i_max_widthu : natural := 0; + +-- COMPONENT DECLARATION +component DCFIFO_DFFPIPE + generic ( + lpm_delay : natural; + lpm_width : natural); + port ( + d : in std_logic_vector(LPM_WIDTH-1 downto 0); + clock : in std_logic; + aclr : in std_logic := '0'; + q : out std_logic_vector(LPM_WIDTH-1 downto 0)); +end component; + +begin + -- Delays + RDPTR_D: DCFIFO_DFFPIPE + generic map ( + lpm_delay => 1, + lpm_width => lpm_widthu + 1) + port map ( + d => i_rdptr, + clock => wrclk, + aclr => aclr, + q => i_rdptr_s); + + WRPTR_D: DCFIFO_DFFPIPE + generic map ( + lpm_delay => 1, + lpm_width => lpm_widthu + 1) + port map ( + d => i_wrptr, + clock => wrclk, + aclr => aclr, + q => i_wrptr_r); + + WRPTR_E: DCFIFO_DFFPIPE + generic map ( + lpm_delay => 1, + lpm_width => lpm_widthu + 1) + port map ( + d => i_wrptr_r, + clock => rdclk, + aclr => aclr, + q => i_wrptr_s); + +-- PROCESS DECLARATION + -- FIFOram + process (aclr, wrclk, rdclk) + variable need_init : boolean := true; + variable mem_data : LPM_MEMORY := (OTHERS => ZEROS); + begin + if (need_init) then + if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF")) + then + ASSERT FALSE + REPORT "Error! LPM_SHOWAHEAD must be ON or OFF." + SEVERITY ERROR; + end if; + if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! OVERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + if ((use_eab /= "ON") and (use_eab /= "OFF")) + then + ASSERT FALSE + REPORT "Error! USE_EAB must be ON or OFF." + SEVERITY ERROR; + end if; + if (lpm_numwords > 2 ** lpm_widthu) + then + ASSERT FALSE + REPORT "Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU." + SEVERITY ERROR; + end if; + if ((add_ram_output_register /= "ON") and (add_ram_output_register /= "OFF")) + then + ASSERT FALSE + REPORT "Error! ADD_RAM_OUTPUT_REGISTER must be ON or OFF." + SEVERITY ERROR; + end if; + if (IS_VALID_FAMILY(intended_device_family) = false) then + ASSERT FALSE + REPORT "Error! Illegal INTENDED_DEVICE_FAMILY." + SEVERITY ERROR; + end if; + + for i in lpm_numwords-1 downto 0 loop + mem_data(i) := ZEROS; + end loop; + + if (lpm_numwords = 2 ** lpm_widthu) + then + i_cnt_mod <= 2 ** (lpm_widthu + 1); + else + i_cnt_mod <= 2 ** lpm_widthu; + end if; + + i_max_widthu <= 2 ** lpm_widthu; + + need_init := false; + end if; -- need_init + + if (aclr'event and (aclr = '1')) + then + i_rdptr <= ZEROU; + i_wrptr <= ZEROU; + if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or + ((add_ram_output_register = "ON") and (use_eab = "OFF"))) + then + if (lpm_showahead = "ON") + then + if ((FEATURE_FAMILY_STRATIXII(intended_device_family)) or + (FEATURE_FAMILY_CYCLONEII(intended_device_family))) + then + i_q_tmp <= (OTHERS => 'X'); + else + i_q_tmp <= mem_data(0); + end if; + else + i_q_tmp <= ZEROS; + end if; + end if; + end if; -- aclr event + + if (wrclk'event and (wrclk = '1')) + then + if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or + ((add_ram_output_register = "ON") and (use_eab = "OFF")))) + then + i_data_tmp <= ZEROS; + i_wrptr_tmp <= ZEROU; + i_wren_tmp <= '0'; + elsif (NOW > 0 ns) + then + i_data_tmp <= data; + i_wrptr_tmp <= i_wrptr; + i_wren_tmp <= i_wren; + + if (i_wren = '1') + then + if ((aclr = '0') and (i_wrptr < i_cnt_mod - 1)) + then + i_wrptr <= i_wrptr + 1; + else + i_wrptr <= ZEROU; + end if; + + if (use_eab = "OFF") + then + mem_data(CONV_INTEGER(i_wrptr) mod i_max_widthu) := data; + + if (lpm_showahead = "ON") + then + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod i_max_widthu); + end if; + end if; + end if; + end if; + end if; -- wrclk'event and (wrclk = '1') + + if (wrclk'event and (wrclk = '0')) + then + if((use_eab = "ON") and (NOW > 0 ns)) + then + if (i_wren_tmp = '1') + then + mem_data(CONV_INTEGER(i_wrptr_tmp) mod i_max_widthu) := i_data_tmp; + end if; + + if ((lpm_showahead = "ON") and + (not(FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))) + then + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod i_max_widthu); + end if; + end if; + end if; -- wrclk'event and (wrclk = '0') + + if (rdclk'event and (rdclk = '1')) + then + if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or + ((add_ram_output_register = "ON") and (use_eab = "OFF")))) + then + if (lpm_showahead = "ON") + then + if ((FEATURE_FAMILY_STRATIXII(intended_device_family)) or + (FEATURE_FAMILY_CYCLONEII(intended_device_family))) + then + i_q_tmp <= (OTHERS => 'X'); + else + i_q_tmp <= mem_data(0); + end if; + else + i_q_tmp <= ZEROS; + end if; + elsif ((i_rden = '1') and (NOW > 0 ns)) + then + if ((aclr = '0') and (i_rdptr < i_cnt_mod - 1)) + then + i_rdptr <= i_rdptr + 1; + else + i_rdptr <= ZEROU; + end if; + + if ((lpm_showahead = "ON") and (not ((use_eab = "ON") and + (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or + FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))))) + then + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr + 1) mod i_max_widthu); + else + i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod i_max_widthu); + end if; + end if; + end if; -- rdclk'event and (rdclk = '1') + end process; -- aclr, wrclk, rdclk events + + i_rden <= rdreq when (underflow_checking = "OFF") + else + rdreq and not i_rdempty; + + i_wren <= wrreq when (overflow_checking = "OFF") + else + wrreq and not i_wrfull; + + -- Usedw/Empty/Full + process (i_rdptr, i_wrptr_s, i_cnt_mod) + begin + if (NOW > 0 ns) + then + if (CONV_INTEGER (i_wrptr_s) >= CONV_INTEGER (i_rdptr)) + then + i_rdusedw <= i_wrptr_s - i_rdptr; + else + i_rdusedw <= i_wrptr_s + i_cnt_mod - i_rdptr; + end if; + end if; + end process; -- i_rdusedw event + + process (i_wrptr, i_rdptr_s, i_cnt_mod) + begin + if (NOW > 0 ns) + then + if (CONV_INTEGER (i_wrptr) >= CONV_INTEGER (i_rdptr_s)) + then + i_wrusedw <= i_wrptr - i_rdptr_s; + else + i_wrusedw <= i_wrptr + i_cnt_mod - i_rdptr_s; + end if; + end if; + end process; -- i_wrusedw event + + process (i_rdusedw, i_max_widthu) + begin + if (i_rdusedw = 0) + then + i_rdempty <= '1'; + else + i_rdempty <= '0'; + end if; + + if ((lpm_numwords = i_max_widthu) and (i_rdusedw >= i_max_widthu)) or + ((lpm_numwords < i_max_widthu) and (i_rdusedw = lpm_numwords)) + then + i_rdfull <= '1'; + else + i_rdfull <= '0'; + end if; + end process; -- i_rdempty and i_rdfull event + + process (i_wrusedw, i_max_widthu) + begin + if (i_wrusedw = 0) + then + i_wrempty <= '1'; + else + i_wrempty <= '0'; + end if; + + if ((lpm_numwords = i_max_widthu) and (i_wrusedw >= i_max_widthu)) or + ((lpm_numwords < i_max_widthu) and (i_wrusedw = lpm_numwords)) + then + i_wrfull <= '1'; + else + i_wrfull <= '0'; + end if; + end process; -- i_wrempty and i_wrfull event + + -- Outputs + rdfull <= i_rdfull; + wrfull <= i_wrfull; + rdempty <= i_rdempty; + wrempty <= i_wrempty; + rdusedw <= i_rdusedw (lpm_widthu-1 downto 0); + wrusedw <= i_wrusedw (lpm_widthu-1 downto 0); + q <= i_q_tmp; + +end behavior; -- dcfifo_sync +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : dcfifo_low_latency +-- +-- Description : Dual Clocks FIFO with lowest latency. This fifo implements +-- the fifo behavior for Stratix II, Cyclone II, Stratix III, +-- Cyclone III and Stratix showahead area mode (LPM_SHOWAHEAD= +-- ON, ADD_RAM_OUTPUT_REGISTER=OFF) +-- +-- Limitation : +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.DCFIFO_DFFPIPE; +use work.ALTERA_MF_HINT_EVALUATION.all; + +-- ENTITY DECLARATION +entity DCFIFO_LOW_LATENCY is +-- GENERIC DECLARATION + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_width_r : natural; + lpm_widthu_r : natural; + lpm_numwords : natural; + delay_rdusedw : natural := 2; + delay_wrusedw : natural := 2; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + add_usedw_msb_bit : string := "OFF"; + read_aclr_synch : string := "OFF"; + write_aclr_synch : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"); + +-- PORT DECLARATION + port + ( +-- INPUT PORT DECLARATION + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; +-- OUTPUT PORT DECLARATION + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width_r-1 downto 0)); +end DCFIFO_LOW_LATENCY; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of DCFIFO_LOW_LATENCY is + +-- FUNCTION DECLARATION +function get_delay_rdusedw (constant i_input_delay_rdusedw : in natural) + return natural is +variable i_delay_rdusedw : natural; +begin + if (i_input_delay_rdusedw > 2) + then + i_delay_rdusedw := 2; + else + i_delay_rdusedw := i_input_delay_rdusedw; + end if; + + return i_delay_rdusedw; + +end get_delay_rdusedw; + +function get_delay_wrusedw (constant i_input_delay_wrusedw : in natural) + return natural is +variable i_delay_wrusedw : natural; +begin + if (i_input_delay_wrusedw > 2) + then + i_delay_wrusedw := 2; + else + i_delay_wrusedw := i_input_delay_wrusedw; + end if; + + return i_delay_wrusedw; + +end get_delay_wrusedw; + +function STR_TO_INT ( str : string ) return integer is +variable ivalue : integer := 0; +variable digit : integer := 0; +begin + for i in str'left to str'right loop + case str(i) is + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& str(i) & "in string parameter! " + SEVERITY ERROR; + end case; + ivalue := ivalue * 10 + digit; + end loop; + return ivalue; +end STR_TO_INT; + +function is_wrempty_speed (constant i_maximize_speed : in string) + return boolean is +begin + if (FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family)) + then + return true; + elsif (FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family)) + then + if ((STR_TO_INT(i_maximize_speed) > 5) or + (wrsync_delaypipe >= 2)) + then + return true; + else + return false; + end if; + else + return false; + end if; +end is_wrempty_speed; + +function is_rdfull_speed (constant i_maximize_speed : in string) + return boolean is +begin + if (FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family)) + then + return true; + elsif (FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family)) + then + if ((STR_TO_INT(i_maximize_speed) > 5) or + (rdsync_delaypipe >= 2)) + then + return true; + else + return false; + end if; + else + return false; + end if; +end is_rdfull_speed; + +function get_cnt_mod (constant i_intended_device_family : in string) + return natural is +begin + if (FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(i_intended_device_family)) + then + if (add_usedw_msb_bit = "OFF") + then + if (lpm_width_r > lpm_width) + then + return (2 ** lpm_widthu) + lpm_width_r/lpm_width; + else + return (2 ** lpm_widthu) + 1; + end if; + else + if (lpm_width_r > lpm_width) + then + return (2 ** (lpm_widthu-1)) + lpm_width_r/lpm_width; + else + return (2 ** (lpm_widthu-1)) + 1; + end if; + end if; + else + return 2 ** lpm_widthu; + end if; +end get_cnt_mod; + +function get_cnt_mod_r (constant i_intended_device_family : in string) + return natural is +begin + if (FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(i_intended_device_family)) + then + if (add_usedw_msb_bit = "OFF") + then + if (lpm_width_r > lpm_width) + then + return (2 ** lpm_widthu_r) + 1; + else + return (2 ** lpm_widthu_r) + lpm_width/lpm_width_r; + end if; + else + if (lpm_width_r > lpm_width) + then + return (2 ** (lpm_widthu_r-1)) + 1; + else + return (2 ** (lpm_widthu_r-1)) + lpm_width/lpm_width_r; + end if; + end if; + else + return 2 ** lpm_widthu_r; + end if; +end get_cnt_mod_r; + +function get_width_ratio (constant L, R : natural) return natural is +begin + if L > R then + return L/R; + else + return R/L; + end if; +end get_width_ratio; + +function get_fifo_depth (constant widthu_r : natural) return natural is +begin + if (add_usedw_msb_bit = "OFF") + then + return widthu_r; + else + return widthu_r -1; + end if; +end get_fifo_depth; + +-- CONSTANT DECLARATION +constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +constant ZEROU : std_logic_vector(lpm_widthu+1 downto 0) := (OTHERS => '0'); +constant ZEROS_R : std_logic_vector(lpm_width_r-1 downto 0) := (OTHERS => '0'); +constant ZEROU_R : std_logic_vector(lpm_widthu_r+1 downto 0) := (OTHERS => '0'); +constant MAXIMIZE_SPEED : string := GET_PARAMETER_VALUE(lpm_hint, "MAXIMIZE_SPEED"); +constant USE_WREMPTY_SPEED : boolean := is_wrempty_speed(MAXIMIZE_SPEED); +constant USE_RDFULL_SPEED : boolean := is_rdfull_speed(MAXIMIZE_SPEED); +constant CNT_MOD : natural := get_cnt_mod(intended_device_family); +constant CNT_MOD_R : natural := get_cnt_mod_r(intended_device_family); +constant WIDTH_RATIO : natural := get_width_ratio(lpm_width, lpm_width_r); +constant FIFO_DEPTH : natural := get_fifo_depth(lpm_widthu_r); +constant USE_SYNC_READ_ACLR : boolean := (FEATURE_FAMILY_STRATIXIII(intended_device_family) or + FEATURE_FAMILY_CYCLONEIII(intended_device_family)) and + (read_aclr_synch = "ON"); +constant USE_SYNC_WRITE_ACLR : boolean := (FEATURE_FAMILY_STRATIXII(intended_device_family) or + FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (write_aclr_synch = "ON"); + +-- TYPE DECLARATION +type LPM_MEMORY is array (2**(FIFO_DEPTH)+ WIDTH_RATIO downto 0) of std_logic_vector(lpm_width_r-1 downto 0); + +-- SIGNAL DECLARATION +signal mem_data : LPM_MEMORY := (OTHERS => ZEROS_R); +signal i_rdptr_g : std_logic_vector(lpm_widthu_r+1 downto 0) := (OTHERS => '0'); +signal i_rdptr_g1p : std_logic_vector(lpm_widthu_r+1 downto 0) := CONV_STD_LOGIC_VECTOR(1, lpm_widthu_r+2); +signal i_wrptr_g : std_logic_vector(lpm_widthu+1 downto 0) := (OTHERS => '0'); +signal i_wrptr_g1 : std_logic_vector(lpm_widthu+1 downto 0) := CONV_STD_LOGIC_VECTOR(1, lpm_widthu+2); +signal i_delayed_wrptr_g : std_logic_vector(lpm_widthu+1 downto 0) := (OTHERS => '0'); +signal i_rden : std_logic := '0'; +signal i_wren : std_logic := '0'; +signal i_showahead_flag : std_logic := '0'; +signal i_rdempty : std_logic := '1'; +signal i_wrempty_area : std_logic := '1'; +signal i_wrempty_speed : std_logic := '1'; +signal i_rdempty_rreg : std_logic := '1'; +signal i_rdfull_area : std_logic := '0'; +signal i_rdfull_speed : std_logic := '0'; +signal i_wrfull : std_logic := '0'; +signal i_wrfull_wreg : std_logic := '0'; +signal i_rdusedw : std_logic_vector(lpm_widthu_r+1 downto 0) := (OTHERS => '0'); +signal i_wrusedw : std_logic_vector(lpm_widthu+1 downto 0) := (OTHERS => '0'); +signal i_rdusedw_tmp : std_logic_vector(lpm_widthu_r+1 downto 0) := (OTHERS => '0'); +signal i_wrusedw_tmp : std_logic_vector(lpm_widthu+1 downto 0) := (OTHERS => '0'); +signal i_rs_dgwp : std_logic_vector(lpm_widthu+1 downto 0) := (OTHERS => '0'); +signal i_ws_dgrp : std_logic_vector(lpm_widthu_r+1 downto 0) := (OTHERS => '0'); +signal i_q : std_logic_vector(lpm_width_r-1 downto 0) := (OTHERS => '0'); +signal sync_rdaclr : std_logic := '1'; +signal sync_rdaclr_pre : std_logic := '1'; +signal read_aclr : std_logic := '0'; +signal sync_wraclr : std_logic := '1'; +signal sync_wraclr_pre : std_logic := '1'; +signal write_aclr : std_logic := '0'; +signal is_overflow : boolean := false; +signal is_underflow : boolean := false; + + +-- COMPONENT DECLARATION +component DCFIFO_DFFPIPE + generic ( + lpm_delay : natural; + lpm_width : natural); + port ( + d : in std_logic_vector(lpm_width-1 downto 0); + clock : in std_logic; + aclr : in std_logic := '0'; + q : out std_logic_vector(lpm_width-1 downto 0)); +end component; + +begin + +-- COMPONENT INSTANTIATIONS + DP_WS_DGRP : dcfifo_dffpipe + generic map ( + lpm_delay => wrsync_delaypipe, + lpm_width => lpm_widthu_r + 2) + port map ( + d => i_rdptr_g, + clock => wrclk, + aclr => aclr, + q => i_ws_dgrp); + + DP_RS_DGWP : dcfifo_dffpipe + generic map ( + lpm_delay => rdsync_delaypipe, + lpm_width => lpm_widthu + 2) + port map ( + d => i_delayed_wrptr_g, + clock => rdclk, + aclr => aclr, + q => i_rs_dgwp); + + DP_RDUSEDW : dcfifo_dffpipe + generic map ( + lpm_delay => get_delay_rdusedw(delay_rdusedw), + lpm_width => lpm_widthu_r + 2) + port map ( + d => i_rdusedw_tmp, + clock => rdclk, + aclr => aclr, + q => i_rdusedw); + + DP_WRUSEDW : dcfifo_dffpipe + generic map ( + lpm_delay => get_delay_wrusedw(delay_wrusedw), + lpm_width => lpm_widthu + 2) + port map ( + d => i_wrusedw_tmp, + clock => wrclk, + aclr => aclr, + q => i_wrusedw); + +-- PROCESS DECLARATION + -- FIFOram + process (aclr, wrclk, rdclk, write_aclr, read_aclr) + variable need_init : boolean := true; + variable mem_data : LPM_MEMORY := (OTHERS => ZEROS_R); + variable i_q_is_registered : boolean := false; + variable max_widthu_r : integer := 0; + variable no_warn : boolean := false; + variable start_address : integer := 0; + begin + if (need_init) then + if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF")) + then + ASSERT FALSE + REPORT "Error! LPM_SHOWAHEAD must be ON or OFF." + SEVERITY ERROR; + end if; + if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) + then + ASSERT FALSE + REPORT "Error! OVERFLOW_CHECKING must be ON or OFF." + SEVERITY ERROR; + end if; + if (lpm_numwords > 2 ** lpm_widthu) + then + ASSERT FALSE + REPORT "Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU." + SEVERITY ERROR; + end if; + if (IS_VALID_FAMILY(intended_device_family) = false) + then + ASSERT FALSE + REPORT "Error! Illegal INTENDED_DEVICE_FAMILY." + SEVERITY ERROR; + end if; + + max_widthu_r := CNT_MOD_R; + + if ((lpm_showahead = "OFF") and + ((FEATURE_FAMILY_STRATIXII(intended_device_family)) or + (FEATURE_FAMILY_CYCLONEII(intended_device_family)))) + then + i_q_is_registered := true; + else + i_q_is_registered := false; + end if; + + need_init := false; + end if; -- need_init + + if (aclr'event and (aclr = '1')) + then + i_rdptr_g <= ZEROU_R; + i_rdptr_g1p <= CONV_STD_LOGIC_VECTOR(1, lpm_widthu_r+2); + i_wrptr_g <= ZEROU; + i_wrptr_g1 <= CONV_STD_LOGIC_VECTOR(1, lpm_widthu+2); + i_delayed_wrptr_g <= ZEROU; + i_wrempty_area <= '1'; + i_rdempty_rreg <= '1'; + i_rdfull_area <= '0'; + i_wrfull_wreg <= '0'; + is_overflow <= false; + is_underflow <= false; + no_warn := false; + + if(i_q_is_registered) + then + i_q <= (OTHERS => '0'); + elsif ((FEATURE_FAMILY_STRATIXII(intended_device_family)) or + (FEATURE_FAMILY_CYCLONEII(intended_device_family))) + then + i_q <= (OTHERS => 'X'); + end if; + end if; + + if ((wrclk'event) and (wrclk = '1') and (NOW > 0 ns)) + then + if (write_aclr = '0') + then + if (i_wren = '1') + then + if ((i_wrfull = '1') and (overflow_checking = "OFF")) then + if (no_warn = false) then + ASSERT FALSE + REPORT "Overflow occurred! Fifo output is unknown until the next reset is asserted" + SEVERITY WARNING; + no_warn := true; + end if; + is_overflow <= true; + else + if (i_wrptr_g1 < (cnt_mod - 1)) + then + i_wrptr_g1 <= i_wrptr_g1 + 1; + else + i_wrptr_g1 <= ZEROU; + end if; + + i_wrptr_g <= i_wrptr_g1; + + if (lpm_width > lpm_width_r) + then + for i in 0 to (lpm_width/lpm_width_r-1) + loop + mem_data((CONV_INTEGER(i_wrptr_g)*lpm_width/lpm_width_r+i) mod max_widthu_r) := data(lpm_width_r*(i + 1) -1 downto lpm_width_r*i); + end loop; + elsif (lpm_width < lpm_width_r) + then + start_address := CONV_INTEGER(i_wrptr_g) mod (lpm_width_r/lpm_width); + mem_data((CONV_INTEGER(i_wrptr_g)*lpm_width/lpm_width_r) mod max_widthu_r)((start_address +1 )*lpm_width -1 downto (start_address * lpm_width)) := data; + else + mem_data(CONV_INTEGER(i_wrptr_g) mod max_widthu_r) := data; + end if; + end if; + end if; + + i_delayed_wrptr_g <= i_wrptr_g; + end if; + + i_wrempty_area <= i_rdempty_rreg; + + if ((aclr = '0') and (write_aclr_synch = "ON") and (FEATURE_FAMILY_STRATIXII(intended_device_family) or + FEATURE_FAMILY_CYCLONEII(intended_device_family))) + then + i_wrfull_wreg <= (i_wrfull or write_aclr); + else + i_wrfull_wreg <= i_wrfull; + end if; + end if; + + if (rdclk'event and (rdclk = '1')) + then + if (read_aclr = '0') + then + if ((i_rden = '1') and (NOW > 0 ns)) + then + if ((i_rdempty = '1') and (underflow_checking = "OFF")) then + if (no_warn = false) then + ASSERT FALSE + REPORT "Underflow occurred! Fifo output is unknown until the next reset is asserted" + SEVERITY WARNING; + no_warn := true; + end if; + is_underflow <= true; + else + if (i_rdptr_g1p < (cnt_mod_r - 1)) then + i_rdptr_g1p <= i_rdptr_g1p + 1; + else + i_rdptr_g1p <= ZEROU_R; + end if; + i_rdptr_g <= i_rdptr_g1p; + end if; + end if; + end if; + + if ((is_overflow = true) or (is_underflow = true)) then + i_q <= (OTHERS => 'X'); + else + if ((i_q_is_registered = false) and (NOW > 0 ns)) + then + if ((read_aclr = '1') and ((FEATURE_FAMILY_STRATIXII(intended_device_family)) or + (FEATURE_FAMILY_CYCLONEII(intended_device_family)))) + then + i_q <= (OTHERS => 'X'); + else + if (i_rdempty = '1') + then + i_q <= mem_data(CONV_INTEGER(i_rdptr_g) mod max_widthu_r); + elsif (i_rden = '1') + then + i_q <= mem_data(CONV_INTEGER(i_rdptr_g1p) mod max_widthu_r); + end if; + end if; + elsif ((read_aclr = '0') and (i_rden = '1') and (NOW > 0 ns)) + then + i_q <= mem_data(CONV_INTEGER(i_rdptr_g) mod max_widthu_r); + end if; + end if; + + if ((rdclk = '1') and (NOW > 0 ns)) + then + i_rdfull_area <= i_wrfull_wreg; + i_rdempty_rreg <= i_rdempty; + end if; + end if; -- rdclk event + end process; + + process (wrclk, aclr) + begin + if (aclr = '1') + then + sync_wraclr <= '1'; + sync_wraclr_pre <= '1'; + elsif (wrclk'event and (wrclk = '1') and (NOW > 0 ns)) + then + sync_wraclr <= sync_wraclr_pre; + sync_wraclr_pre <= '0'; + end if; + end process; + + process (rdclk, aclr) + begin + if (aclr = '1') + then + sync_rdaclr <= '1'; + sync_rdaclr_pre <= '1'; + elsif (rdclk'event and (rdclk = '1') and (NOW > 0 ns)) + then + sync_rdaclr <= sync_rdaclr_pre; + sync_rdaclr_pre <= '0'; + end if; + end process; + + process (i_rdptr_g, i_rs_dgwp) + begin + if (lpm_width > lpm_width_r) + then + if (CONV_INTEGER(i_rdptr_g(lpm_widthu_r downto 0))*lpm_width_r/lpm_width = CONV_INTEGER((i_rs_dgwp(lpm_widthu downto 0)))) + then + i_rdempty <= '1'; + else + i_rdempty <= '0'; + end if; + else + if (CONV_INTEGER(i_rdptr_g(lpm_widthu_r downto 0)) = CONV_INTEGER((i_rs_dgwp(lpm_widthu downto 0)))*lpm_width/lpm_width_r) + then + i_rdempty <= '1'; + else + i_rdempty <= '0'; + end if; + end if; + end process; + + process (i_wrptr_g1, i_ws_dgrp) + begin + if (lpm_width < lpm_width_r) + then + if (((CONV_INTEGER(i_wrptr_g1(lpm_widthu downto 0)) + WIDTH_RATIO -1) mod CNT_MOD) = CONV_INTEGER(i_ws_dgrp(lpm_widthu_r downto 0))*lpm_width_r/lpm_width) + then + i_wrfull <= '1'; + else + i_wrfull <= '0'; + end if; + else + if (CONV_INTEGER(i_wrptr_g1(lpm_widthu downto 0)) = CONV_INTEGER(i_ws_dgrp(lpm_widthu_r downto 0))*lpm_width_r/lpm_width) + then + i_wrfull <= '1'; + else + i_wrfull <= '0'; + end if; + end if; + end process; + + process (i_wrptr_g, i_ws_dgrp) + begin + if ((NOW > 0 ns) and (CONV_INTEGER(i_wrptr_g) < CONV_INTEGER(i_ws_dgrp)*lpm_width_r/lpm_width)) + then + i_wrusedw_tmp <= CONV_STD_LOGIC_VECTOR(CNT_MOD + CONV_INTEGER(i_wrptr_g) - CONV_INTEGER(i_ws_dgrp)*lpm_width_r/lpm_width, lpm_widthu + 2); + else + i_wrusedw_tmp <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(i_wrptr_g) - CONV_INTEGER(i_ws_dgrp)*lpm_width_r/lpm_width, lpm_widthu + 2); + end if; + + if (lpm_width > lpm_width_r) + then + if (CONV_INTEGER(i_wrptr_g) = CONV_INTEGER(i_ws_dgrp)*lpm_width_r/lpm_width) + then + i_wrempty_speed <= '1'; + else + i_wrempty_speed <= '0'; + end if; + else + if (CONV_INTEGER(i_wrptr_g)*lpm_width/lpm_width_r = CONV_INTEGER(i_ws_dgrp)) + then + i_wrempty_speed <= '1'; + else + i_wrempty_speed <= '0'; + end if; + + end if; + end process; + + process (i_rdptr_g, i_rs_dgwp) + begin + if ((NOW > 0 ns) and (CONV_INTEGER(i_rs_dgwp)*lpm_width/lpm_width_r < CONV_INTEGER(i_rdptr_g))) + then + i_rdusedw_tmp <= CONV_STD_LOGIC_VECTOR((CNT_MOD + CONV_INTEGER(i_rs_dgwp))*lpm_width/lpm_width_r - CONV_INTEGER(i_rdptr_g), lpm_widthu_r + 2); + else + i_rdusedw_tmp <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(i_rs_dgwp)*lpm_width/lpm_width_r - CONV_INTEGER(i_rdptr_g), lpm_widthu_r + 2); + end if; + + if (lpm_width < lpm_width_r) + then + if (CONV_INTEGER(i_rdptr_g)*lpm_width_r/lpm_width = ((CONV_INTEGER(i_rs_dgwp) + WIDTH_RATIO) mod CNT_MOD)) + then + i_rdfull_speed <= '1'; + else + i_rdfull_speed <= '0'; + end if; + else + if (CONV_INTEGER(i_rdptr_g) = ((CONV_INTEGER(i_rs_dgwp) +1) mod CNT_MOD)*lpm_width/lpm_width_r) + then + i_rdfull_speed <= '1'; + else + i_rdfull_speed <= '0'; + end if; + end if; + end process; + +-- SIGNAL ASSIGNMENTS + i_rden <= rdreq and not sync_rdaclr when ((underflow_checking = "OFF") and (USE_SYNC_READ_ACLR = true)) else + rdreq and not (i_rdempty or sync_rdaclr) when (USE_SYNC_READ_ACLR = true) else + rdreq when (underflow_checking = "OFF") else + rdreq and not i_rdempty; + i_wren <= wrreq and not sync_wraclr when ((overflow_checking = "OFF") and (USE_SYNC_WRITE_ACLR = true)) else + wrreq and not (i_wrfull or sync_wraclr) when (USE_SYNC_WRITE_ACLR = true) else + wrreq when (overflow_checking = "OFF") else + wrreq and not i_wrfull; + read_aclr <= sync_rdaclr when ((FEATURE_FAMILY_STRATIXIII(intended_device_family) or + FEATURE_FAMILY_CYCLONEIII(intended_device_family)) and + (read_aclr_synch = "ON")) else + aclr; + write_aclr <= sync_wraclr when ((FEATURE_FAMILY_STRATIXII(intended_device_family) or + FEATURE_FAMILY_CYCLONEII(intended_device_family)) and + (write_aclr_synch = "ON")) else + aclr; + + -- Outputs + rdempty <= 'X' when ((is_overflow = true) or (is_underflow = true)) else + (i_rdempty or sync_rdaclr) when (USE_SYNC_READ_ACLR = true) else + i_rdempty; + wrempty <= 'X' when ((is_overflow = true) or (is_underflow = true)) else + i_wrempty_speed when (USE_WREMPTY_SPEED) else + i_wrempty_area; + rdfull <= 'X' when ((is_overflow = true) or (is_underflow = true)) else + i_rdfull_speed when (USE_RDFULL_SPEED) else + i_rdfull_area; + wrfull <= 'X' when ((is_overflow = true) or (is_underflow = true)) else + (i_wrfull or sync_wraclr) when (USE_SYNC_WRITE_ACLR = true) else + i_wrfull; + wrusedw <= (OTHERS => 'X') when ((is_overflow = true) or (is_underflow = true)) else + i_wrusedw(lpm_widthu-1 downto 0); + rdusedw <= (OTHERS => 'X') when ((is_overflow = true) or (is_underflow = true)) else + i_rdusedw(lpm_widthu_r-1 downto 0); + q <= (OTHERS => 'X') when ((is_overflow = true) or (is_underflow = true)) else + i_q; + +end behavior; -- dcfifo_low_latency +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : dcfifo_mixed_widths +-- +-- Description : Mixed Widths Dual clocks FIFO +-- +-- Limitation : +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use work.ALTERA_DEVICE_FAMILIES.all; +use work.DCFIFO_ASYNC; +use work.DCFIFO_SYNC; +use work.DCFIFO_LOW_LATENCY; + +-- ENTITY DECLARATION +entity DCFIFO_MIXED_WIDTHS is +-- GENERIC DECLARATION + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_width_r : natural := 0; + lpm_widthu_r : natural := 0; + lpm_numwords : natural; + delay_rdusedw : natural := 1; + delay_wrusedw : natural := 1; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + clocks_are_synchronized : string := "FALSE"; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"; + add_width : natural := 1; + ram_block_type : string := "AUTO"; + add_usedw_msb_bit : string := "OFF"; + read_aclr_synch : string := "OFF"; + write_aclr_synch : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"; + lpm_type : string := "dcfifo_mixed_widths"); +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; + +-- OUTPUT PORT DECLARATION + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width_r-1 downto 0)); +end DCFIFO_MIXED_WIDTHS; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of DCFIFO_MIXED_WIDTHS is + +-- FUNCTION DECLARATION + + function dcfifo_max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function get_rdsync_delaypipe(i_rdsync_delaypipe : natural) return natural is + begin + if (i_rdsync_delaypipe = 0) then + + if ((FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM (intended_device_family) or FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM (intended_device_family)) + and (clocks_are_synchronized = "FALSE")) then + return 4; + else + return 3; + end if; + else + return i_rdsync_delaypipe; + end if; + end; + + function get_wrsync_delaypipe(i_wrsync_delaypipe : natural) return natural is + begin + if (i_wrsync_delaypipe = 0) then + + if ((FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM (intended_device_family) or FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM (intended_device_family)) + and (clocks_are_synchronized = "FALSE")) then + return 4; + else + return 3; + end if; + else + return i_wrsync_delaypipe; + end if; + end; + + +-- CONSTANT DECLARATION +constant USE_LOW_LATENCY_FIFO : boolean := (FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM (intended_device_family) and + ((use_eab = "ON") or ((use_eab = "OFF") and (lpm_width /= lpm_width_r) and (lpm_width_r /= 0)) or + ((lpm_numwords < 16) and (clocks_are_synchronized = "FALSE")))) or + (FEATURE_FAMILY_STRATIX(intended_device_family) and (use_eab = "ON") and + (((lpm_showahead = "ON") and (add_ram_output_register = "OFF")) or + (clocks_are_synchronized = "FALSE_LOW_LATENCY"))); +-- CONSTANT DECLARATION +constant READ_SIDE_SYNCHRONIZERS : natural := get_rdsync_delaypipe(rdsync_delaypipe); +constant WRITE_SIDE_SYNCHRONIZERS : natural := get_wrsync_delaypipe(wrsync_delaypipe); +-- For low-latency FIFO, reduce the default number of synchronization stages by 2, but need at least 1 stage +constant LOW_RDSYNC_DELAYPIPE : natural := dcfifo_max((READ_SIDE_SYNCHRONIZERS - 2), 1); +constant LOW_WRSYNC_DELAYPIPE : natural := dcfifo_max((WRITE_SIDE_SYNCHRONIZERS - 2), 1); +constant WIDTH_R : natural := lpm_width_r; +constant WIDTHU_R : natural := lpm_widthu_r; + +-- SIGNAL DECLARATION +signal i_rdfull_a : std_logic := '0'; +signal i_wrfull_a : std_logic := '0'; +signal i_rdempty_a : std_logic := '1'; +signal i_wrempty_a : std_logic := '1'; +signal i_rdfull_s : std_logic := '0'; +signal i_wrfull_s : std_logic := '0'; +signal i_rdempty_s : std_logic := '1'; +signal i_wrempty_s : std_logic := '1'; +signal i_rdfull_l : std_logic := '0'; +signal i_wrfull_l : std_logic := '0'; +signal i_rdempty_l : std_logic := '1'; +signal i_wrempty_l : std_logic := '1'; +signal i_rdusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wrusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rdusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wrusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_rdusedw_l : std_logic_vector(WIDTHU_R-1 downto 0) := (OTHERS => '0'); +signal i_wrusedw_l : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_q_a : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +signal i_q_s : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); +signal i_q_l : std_logic_vector(WIDTH_R-1 downto 0) := (OTHERS => '0'); + + +-- COMPONENT DECLARATION +component DCFIFO_ASYNC + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + delay_rdusedw : natural := 1; + delay_wrusedw : natural := 1; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width-1 downto 0)); +end component; + +component DCFIFO_SYNC + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width-1 downto 0)); +end component; + +component DCFIFO_LOW_LATENCY + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_width_r : natural; + lpm_widthu_r : natural; + lpm_numwords : natural; + delay_rdusedw : natural := 2; + delay_wrusedw : natural := 2; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + add_usedw_msb_bit : string := "OFF"; + read_aclr_synch : string := "OFF"; + write_aclr_synch : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(WIDTHU_R-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(WIDTH_R-1 downto 0)); +end component; + +begin +-- COMPONENT ASSIGNMENTS + ASYNC: DCFIFO_ASYNC + generic map ( + lpm_width => lpm_width, + lpm_widthu => lpm_widthu, + lpm_numwords => lpm_numwords, + delay_rdusedw => delay_rdusedw, + delay_wrusedw => delay_wrusedw, + rdsync_delaypipe => READ_SIDE_SYNCHRONIZERS, + wrsync_delaypipe => WRITE_SIDE_SYNCHRONIZERS, + intended_device_family => intended_device_family, + lpm_showahead => lpm_showahead, + underflow_checking => underflow_checking, + overflow_checking => overflow_checking, + use_eab => use_eab, + add_ram_output_register => add_ram_output_register) + port map ( + data => data, + rdclk => rdclk, + wrclk => wrclk, + aclr => aclr, + rdreq => rdreq, + wrreq => wrreq, + rdfull => i_rdfull_a, + wrfull => i_wrfull_a, + rdempty => i_rdempty_a, + wrempty => i_wrempty_a, + rdusedw => i_rdusedw_a, + wrusedw => i_wrusedw_a, + q => i_q_a); + + SYNC: DCFIFO_SYNC + generic map ( + lpm_width => lpm_width, + lpm_widthu => lpm_widthu, + lpm_numwords => lpm_numwords, + intended_device_family => intended_device_family, + lpm_showahead => lpm_showahead, + underflow_checking => underflow_checking, + overflow_checking => overflow_checking, + use_eab => use_eab, + add_ram_output_register => add_ram_output_register) + port map ( + data => data, + rdclk => rdclk, + wrclk => wrclk, + aclr => aclr, + rdreq => rdreq, + wrreq => wrreq, + rdfull => i_rdfull_s, + wrfull => i_wrfull_s, + rdempty => i_rdempty_s, + wrempty => i_wrempty_s, + rdusedw => i_rdusedw_s, + wrusedw => i_wrusedw_s, + q => i_q_s); + + LOWLATENCY_FIFO: + if (USE_LOW_LATENCY_FIFO = true) generate + + LOWLATENCY : DCFIFO_LOW_LATENCY + generic map ( + lpm_width => lpm_width, + lpm_widthu => lpm_widthu, + lpm_width_r => WIDTH_R, + lpm_widthu_r => WIDTHU_R, + lpm_numwords => lpm_numwords, + delay_rdusedw => delay_rdusedw, + delay_wrusedw => delay_wrusedw, + rdsync_delaypipe => LOW_RDSYNC_DELAYPIPE, + wrsync_delaypipe => LOW_WRSYNC_DELAYPIPE, + intended_device_family => intended_device_family, + lpm_showahead => lpm_showahead, + underflow_checking => underflow_checking, + overflow_checking => overflow_checking, + add_usedw_msb_bit => add_usedw_msb_bit, + read_aclr_synch => read_aclr_synch, + write_aclr_synch => write_aclr_synch, + lpm_hint => lpm_hint) + port map ( + data => data, + rdclk => rdclk, + wrclk => wrclk, + aclr => aclr, + rdreq => rdreq, + wrreq => wrreq, + rdfull => i_rdfull_l, + wrfull => i_wrfull_l, + rdempty => i_rdempty_l, + wrempty => i_wrempty_l, + rdusedw => i_rdusedw_l, + wrusedw => i_wrusedw_l, + q => i_q_l); + + end generate LOWLATENCY_FIFO; + + rdfull <= i_rdfull_l when USE_LOW_LATENCY_FIFO = true + else i_rdfull_s when clocks_are_synchronized = "TRUE" + else i_rdfull_a; + wrfull <= i_wrfull_l when USE_LOW_LATENCY_FIFO = true + else i_wrfull_s when clocks_are_synchronized = "TRUE" + else i_wrfull_a; + rdempty <= i_rdempty_l when USE_LOW_LATENCY_FIFO = true + else i_rdempty_s when clocks_are_synchronized = "TRUE" + else i_rdempty_a; + wrempty <= i_wrempty_l when USE_LOW_LATENCY_FIFO = true + else i_wrempty_s when clocks_are_synchronized = "TRUE" + else i_wrempty_a; + rdusedw <= i_rdusedw_l when USE_LOW_LATENCY_FIFO = true + else i_rdusedw_s when clocks_are_synchronized = "TRUE" + else i_rdusedw_a; + wrusedw <= i_wrusedw_l when USE_LOW_LATENCY_FIFO = true + else i_wrusedw_s when clocks_are_synchronized = "TRUE" + else i_wrusedw_a; + q <= i_q_l when USE_LOW_LATENCY_FIFO = true + else i_q_s when clocks_are_synchronized = "TRUE" + else i_q_a; + + +-- PROCESS DECLARATION + + INITIAL : process + begin + if (((wrsync_delaypipe = 0) or (rdsync_delaypipe = 0)) and (clocks_are_synchronized = "FALSE")) then + if (FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM (intended_device_family) or FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM (intended_device_family)) then + ASSERT FALSE + REPORT "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2." + SEVERITY WARNING; + end if; + end if; + wait; + end process; -- INITIAL process + +end behavior; -- DCFIFO_MIXED_WIDTHS +-- END OF ARCHITECTURE + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : dcfifo +-- +-- Description : Dual clocks FIFO +-- +-- Limitation : +-- +-- Results Expected: +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.DCFIFO_MIXED_WIDTHS; + +-- ENTITY DECLARATION +entity DCFIFO is +-- GENERIC DECLARATION + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + delay_rdusedw : natural := 1; + delay_wrusedw : natural := 1; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + intended_device_family : string := "Stratix"; + lpm_showahead : string := "OFF"; + underflow_checking : string := "ON"; + overflow_checking : string := "ON"; + clocks_are_synchronized : string := "FALSE"; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"; + add_width : natural := 1; + ram_block_type : string := "AUTO"; + add_usedw_msb_bit : string := "OFF"; + read_aclr_synch : string := "OFF"; + write_aclr_synch : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"; + lpm_type : string := "dcfifo"); +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; + +-- OUTPUT PORT DECLARATION + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width-1 downto 0)); +end DCFIFO; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of DCFIFO is + +-- SIGNAL DECLARATION +signal i_rdfull : std_logic := '0'; +signal i_wrfull : std_logic := '0'; +signal i_rdempty : std_logic := '1'; +signal i_wrempty : std_logic := '1'; +signal i_rdusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_wrusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0'); +signal i_q : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0'); + +-- COMPONENT DECLARATION + +component DCFIFO_MIXED_WIDTHS + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_width_r : natural; + lpm_widthu_r : natural; + lpm_numwords : natural; + delay_rdusedw : natural; + delay_wrusedw : natural; + rdsync_delaypipe : natural; + wrsync_delaypipe : natural; + intended_device_family : string; + lpm_showahead : string; + underflow_checking : string; + overflow_checking : string; + clocks_are_synchronized : string; + use_eab : string; + add_ram_output_register : string; + add_width : natural; + ram_block_type : string; + add_usedw_msb_bit : string; + read_aclr_synch : string; + write_aclr_synch : string; + lpm_hint : string ); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + aclr : in std_logic := '0'; + rdreq : in std_logic; + wrreq : in std_logic; + rdfull : out std_logic; + wrfull : out std_logic; + rdempty : out std_logic; + wrempty : out std_logic; + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0); + q : out std_logic_vector(lpm_width-1 downto 0)); +end component; + +begin +-- COMPONENT ASSIGNMENTS + DCFIFO_MW : DCFIFO_MIXED_WIDTHS + generic map ( + lpm_width => lpm_width, + lpm_widthu => lpm_widthu, + lpm_width_r => lpm_width, + lpm_widthu_r => lpm_widthu, + lpm_numwords => lpm_numwords, + delay_rdusedw => delay_rdusedw, + delay_wrusedw => delay_wrusedw, + rdsync_delaypipe => rdsync_delaypipe, + wrsync_delaypipe => wrsync_delaypipe, + intended_device_family => intended_device_family, + lpm_showahead => lpm_showahead, + underflow_checking => underflow_checking, + overflow_checking => overflow_checking, + clocks_are_synchronized => clocks_are_synchronized, + use_eab => use_eab, + add_ram_output_register => add_ram_output_register, + add_width => add_width, + ram_block_type => ram_block_type, + add_usedw_msb_bit => add_usedw_msb_bit, + read_aclr_synch => read_aclr_synch, + write_aclr_synch => write_aclr_synch, + lpm_hint => lpm_hint) + port map ( + data => data, + rdclk => rdclk, + wrclk => wrclk, + aclr => aclr, + rdreq => rdreq, + wrreq => wrreq, + rdfull => i_rdfull, + wrfull => i_wrfull, + rdempty => i_rdempty, + wrempty => i_wrempty, + rdusedw => i_rdusedw, + wrusedw => i_wrusedw, + q => i_q); + + rdfull <= i_rdfull; + wrfull <= i_wrfull; + rdempty <= i_rdempty; + wrempty <= i_wrempty; + rdusedw <= i_rdusedw; + wrusedw <= i_wrusedw; + q <= i_q; + +end behavior; -- dcfifo +-- END OF ARCHITECTURE + +-------------------------------------------------------------------------------- +-- Module Name : altshift_taps +-- +-- Description : Parameterized shift register with taps megafunction. +-- Implements a RAM-based shift register for efficient +-- creation of very large shift registers +-- +-- Limitation : This megafunction is provided only for backward +-- compatibility in Cyclone, Stratix, and Stratix GX +-- designs. +-- +-- Results expected : Produce output from the end of the shift register +-- and from the regularly spaced taps along the +-- shift register. +-- +-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; + +-- ENTITY DECLARATION +entity altshift_taps is +generic ( + number_of_taps : natural := 4; -- Specifies the number of regularly spaced + -- taps along the shift register + tap_distance : natural := 3; -- Specifies the distance between the + -- regularly spaced taps in clock cycles + -- This number translates to the number of + -- RAM words that will be used + width : natural := 8; + power_up_state : string := "CLEARED"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altshift_taps"; + intended_device_family : string := "Stratix" + ); + +port (-- data input to the shifter + shiftin : in std_logic_vector (width-1 downto 0); + -- Positive-edge triggered clock + clock : in std_logic; + -- Clock enable for the clock port + clken : in std_logic := '1'; + -- Asynchronous clear port + aclr : in std_logic := '0'; + -- Output from the end of the shift register + shiftout : out std_logic_vector (width-1 downto 0); + -- Output from the regularly spaced taps along the shift register + taps : out std_logic_vector ((width*number_of_taps)-1 downto 0) + ); + +end altshift_taps; + + +-- ARCHITECTURE DECLARATION +architecture behavioural of altshift_taps is + +-- CONSTANT DECLARATION +constant TOTAL_TAP_DISTANCE : natural := number_of_taps * tap_distance; + +-- TYPE DECLARATION +type mxn_array is array (TOTAL_TAP_DISTANCE-1 downto 0) of + std_logic_vector (width downto 0); + +-- SIGNAL DECLARATION +signal contents : mxn_array; +signal head_pipe : natural := 0; +signal i : natural := 0; + +begin + +-- PROCESS BLOCKS + SHIFT: process (clock, aclr) + variable head: natural := 0; + variable init : boolean := true; + begin + if init and (power_up_state = "CLEARED") then + shiftout <= (others => '0'); + taps <= (others => '0'); + contents <= (others => (others => '0')); + init := false; + end if; + + if (aclr = '1') then + shiftout <= (others => '0'); + taps <= (others => '0'); + contents <= (others => (others => '0')); + head := 0; + head_pipe <= 0; + elsif (rising_edge(clock)) then + if (clken = '1') then + head := head_pipe; + + contents (head)(width-1 downto 0) <= shiftin; + shiftout <= contents ((head+1) mod + TOTAL_TAP_DISTANCE)(width-1 downto 0); + head := (head+1) mod TOTAL_TAP_DISTANCE; + + for i in 0 to (number_of_taps-1) + loop + taps (((i+1)*width)-1 downto (i*width) ) <= + contents ((((number_of_taps - i - 1)*tap_distance) + head) + mod TOTAL_TAP_DISTANCE)(width-1 downto 0); + end loop; + + head_pipe <= head; + end if; + end if; + end process shift; + + +end behavioural; -- altshift_taps + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- Entity Name : a_graycounter +-- +-- Description : Gray counter with Count-enable, Up/Down, aclr and sclr +-- +-- Limitation : Sync sigal priority: clk_en (higher),sclr,cnt_en (lower) +-- +-- Results Expected: q is graycounter output and qbin is normal counter +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +-- BEGINNING OF ENTITY +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; + +-- ENTITY DECLARATION +entity A_GRAYCOUNTER is +-- GENERIC DECLARATION + generic ( + width : natural; + pvalue : natural; + lpm_hint : string := "UNUSED"; + lpm_type : string := "a_graycounter"); + +-- PORT DECLARATION + port ( +-- INPUT PORT DECLARATION + clock : in std_logic; + clk_en : in std_logic := '1'; + cnt_en : in std_logic := '1'; + updown : in std_logic := '1'; + aclr : in std_logic := '0'; + sclr : in std_logic := '0'; +-- OUTPUT PORT DECLARATION + qbin : out std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0)); +end A_GRAYCOUNTER; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +-- ARCHITECTURE DECLARATION +architecture behavior of A_GRAYCOUNTER is + +-- SIGNAL DECLARATION +signal cnt : std_logic_vector(width-1 downto 0); +signal qbin_tmp : std_logic_vector(width-1 downto 0); + +begin +-- PROCESS DECLARATION + -- basic error checking for invalid parameters + MSG: process + begin + if (width <= 0) then + ASSERT FALSE + REPORT "Value of WIDTH parameter of a_graycounter must be greater than 0!" + SEVERITY ERROR; + end if; + + wait; + end process MSG; + + process(aclr, clock) + variable init : boolean := true; + begin + if (init) then + -- Initialize to pvalue + cnt <= conv_std_logic_vector(pvalue, width); + init := false; + elsif (aclr'event and (aclr = '1')) then + cnt <= conv_std_logic_vector(pvalue, width); + elsif (clock'event and (clock = '1')) then + if ((aclr = '0') and (clk_en = '1')) then + if (sclr = '1') then + cnt <= conv_std_logic_vector(pvalue, width); + elsif (cnt_en = '1') then + if (updown = '1') then + cnt <= cnt + 1; + else + cnt <= cnt - 1; + end if; + end if; + end if; + end if; + end process; + + qbin_tmp <= cnt; + process(qbin_tmp) + variable qbin_rshift : std_logic_vector(width-1 downto 0); + begin + if (width > 1) then + qbin_rshift(width-2 downto 0) := qbin_tmp(width-1 downto 1); + end if; + qbin_rshift(width-1) := '0'; + q <= qbin_tmp xor qbin_rshift; + end process; + + qbin <= cnt; + +end behavior; -- a_graycounter +-- END OF ARCHITECTURE + + + + +---START_ENTITY_HEADER--------------------------------------------------------- +-- +-- entity Name : altsquare +-- +-- Description : Parameterized integer square megafunction. +-- The input data can be signed or unsigned, and the output +-- can be pipelined. +-- +-- Limitations : Minimum data width is 1. +-- +-- Results expected: result - The square of input data. +-- +---END_ENTITY_HEADER----------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-- BEGINNING OF ENTITY + +-- ENTITY DECLARATION +entity altsquare is +-- GENERIC DECLARATION + generic + ( + data_width : natural; + result_width : natural; + pipeline : natural := 0; + representation : string := "UNSIGNED"; + result_alignment : string := "LSB"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altsquare" + ); +-- PORT DECLARATION + port + ( + data : in std_logic_vector (data_width - 1 downto 0); + clock : in std_logic := '0'; + ena : in std_logic := '1'; + aclr : in std_logic := '0'; + result : out std_logic_vector (result_width - 1 downto 0) + ); +end altsquare; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +architecture altsquare_syn of altsquare is + +-- TYPE DECLARATION + -- for storing the pipeline values + type T_PIPE_ARRAY is array (0 to pipeline) of std_logic_vector(2 * data_width - 1 downto 0); + +-- SIGNAL DECLARATION + signal stage_value : T_PIPE_ARRAY; + signal next_value : std_logic_vector(2 * data_width - 1 downto 0); +begin + -- error checking + assert data_width > 0 + report "Value of data_width parameter must be greater than 0" severity error; + assert result_width > 0 + report "Value of result_width parameter must be greater than 0" severity error; + assert representation = "UNSIGNED" or representation = "SIGNED" + report "Value of representation parameter must be signed or unsigned" severity error; + +-- PROCESS DECLARATION + process(clock, aclr, data) + variable stage_value : T_PIPE_ARRAY; + begin + if aclr = '1' and pipeline > 0 then + stage_value := (others => (others => '0')); + elsif (clock = '1' and clock'event) or pipeline = 0 then + if (ena = '1') or (pipeline = 0) then + if representation = "SIGNED" then + stage_value(0) := signed(data) * signed(data); + else + stage_value(0) := unsigned(data) * unsigned(data); + end if; + if pipeline > 0 then + for i in pipeline downto 1 loop + stage_value(i) := stage_value(i - 1); + end loop; + end if; + end if; + end if; + next_value <= stage_value(pipeline); + end process; + + -- now set the result + data_shrink_LSB : if (result_width <= 2 * data_width) and (result_alignment = "LSB") generate + result(result_width - 1 downto 0) <= next_value(result_width - 1 downto 0); + end generate; + data_shrink_MSB : if (result_width <= 2 * data_width) and (result_alignment = "MSB") generate + result(result_width - 1 downto 0) <= next_value((2*data_width)-1 downto (2*data_width)-result_width); + end generate; + data_expand : if result_width > 2 * data_width generate + result(result_width - 1 downto 2* data_width) <= (others => '0'); + result((2 * data_width) - 1 downto 0) <= next_value; + end generate; +end altsquare_syn; -- altsquare +-- END OF ARCHITECTURE +-- START_FILE_HEADER ---------------------------------------------------------- +-- +-- Filename : altera_std_synchronizer.vhd +-- +-- Description : Contains the simulation model for the altera_std_synchronizer +-- +-- Owner : Paul Scheidt +-- +-- Copyright (C) Altera Corporation 2008, All Rights Reserved +-- +-- END_FILE_HEADER ------------------------------------------------------------ +-- +-- START_ENTITY_HEADER -------------------------------------------------------- +-- +-- Entity Name : altera_std_synchronizer +-- +-- Description : Single bit clock domain crossing synchronizer. +-- Composed of two flip flops connected in series. +-- +-- Limitations : +-- +-- END_FILE_HEADER ------------------------------------------------------------ +-- +library ieee ; +use ieee.std_logic_1164.all; +use work.all; + +-- BEGINNING OF ENTITY +entity altera_std_synchronizer is + -- GENERIC DECLARATION + generic (depth : integer := 3); -- must be >= 2 + + -- PORT DECLARATION + port ( + clk : in std_logic; + reset_n : in std_logic; + din : in std_logic; + dout : out std_logic + ); +end altera_std_synchronizer; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +architecture behavioral of altera_std_synchronizer is +-- SIGNAL DECLARATION + signal din_s1 : std_logic; + signal dreg : std_logic_vector(depth-2 downto 0); +begin + process (din, clk) begin + if (clk'event and clk='1') then + if reset_n='0' then + din_s1 <= '0'; + else + din_s1 <= din; + end if; + end if; + end process; + + g1: if depth = 1 generate + -- normally this is an illegal condition + dout <= din_s1; + end generate g1; + + g2: if depth = 2 generate + process (din, clk) begin + if (clk'event and clk='1') then + if reset_n='0' then + dout <= '0'; + else + dout <= din_s1; + end if; + end if; + end process; + end generate g2; + + g3: if depth >= 3 generate + process (din, clk) begin + if (clk'event and clk='1') then + if reset_n='0' then + dreg <= (others => '0'); + else + dreg <= dreg(depth-3 downto 0) & din_s1; + end if; + end if; + end process; + dout <= dreg(depth-2); + end generate g3; + +end behavioral; +-- END OF ARCHITECTURE + +-- START_FILE_HEADER ---------------------------------------------------------- +-- +-- Filename : altera_std_synchronizer_bundle.vhd +-- +-- Description : Contains the simulation model for the altera_std_synchronizer_bundle +-- +-- Owner : Paul Scheidt +-- +-- Copyright (C) Altera Corporation 2008, All Rights Reserved +-- +-- END_FILE_HEADER ------------------------------------------------------------ +-- +-- START_ENTITY_HEADER -------------------------------------------------------- +-- +-- Entity Name : altera_std_synchronizer_bundle +-- +-- Description : Bundle of bit synchronizers. +-- WARNING: only use this to synchronize a bundle of +-- *independent* single bit signals or a Gray encoded +-- bus of signals. Also remember that pulses entering +-- the synchronizer will be swallowed upon a metastable +-- condition if the pulse width is shorter than twice +-- the synchronizing clock period. +-- +-- Limitations : +-- +-- END_FILE_HEADER ------------------------------------------------------------- +-- + +library ieee ; +use ieee.std_logic_1164.all; +use work.all; + +-- BEGINNNG OF ENTITY +entity altera_std_synchronizer_bundle is + -- GENERIC DECLARATION + generic ( depth : integer := 3; -- must be >= 2 + width : integer := 1); + + -- PORT DECLARATION + port ( + clk : in std_logic; + reset_n : in std_logic; + din : in std_logic_vector(width-1 downto 0); + dout : out std_logic_vector(width-1 downto 0) + ); +end altera_std_synchronizer_bundle; +-- END OF ENTITY + +-- BEGINNING OF ARCHITECTURE +architecture behavioral of altera_std_synchronizer_bundle is +-- COMPONENT DECLARATION + component altera_std_synchronizer + generic (depth : integer := 3); + port ( + clk : in std_logic; + reset_n : in std_logic; + din : in std_logic; + dout : out std_logic + ); + end component; +begin + g1: for i in 0 to width-1 generate + s: altera_std_synchronizer + generic map (depth => depth) + port map ( clk => clk, + reset_n => reset_n, + din => din(i), + dout => dout(i) + ); + end generate g1; +end behavioral; +-- END OF ARCHITECTURE + +LIBRARY ieee; +USE ieee.std_logic_unsigned.all; + +--synthesis_resources = lut 4 reg 5 +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY alt_cal IS + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal" + ); + PORT + ( + busy : OUT STD_LOGIC; + cal_error : OUT STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0); + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + retain_addr : OUT STD_LOGIC; + start : IN STD_LOGIC := '0'; + transceiver_init : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0') + ); +END alt_cal; + +ARCHITECTURE RTL OF alt_cal IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + ATTRIBUTE ALTERA_ATTRIBUTE : string; + ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "PRESERVE_REGISTER=ON"; + + SIGNAL p0addr_sim : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF p0addr_sim : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"; + + SIGNAL wire_p0addr_sim_w_lg_w_lg_q4w5w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_q4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF sim_counter_reg : SIGNAL IS "POWER_UP_LEVEL=LOW"; + SIGNAL first_run : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '1') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF first_run : SIGNAL IS "POWER_UP_LEVEL=HIGH"; + + SIGNAL wire_next_scount_num_dataa : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_next_scount_num_datab : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_next_scount_num_result : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_reset7w8w9w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_reset7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_sim_counter_and2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and1w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_reset7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL busy_sim : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_activator : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_and : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_next : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sim_counter_or : STD_LOGIC_VECTOR (0 DOWNTO 0); +BEGIN + + loop0 : FOR i IN 0 TO 3 GENERATE + wire_w_lg_w_lg_w_lg_reset7w8w9w(i) <= (wire_w_lg_w_lg_reset7w8w(0) AND wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) AND NOT(reset AND first_run(0))) OR (reset AND NOT first_run(0)); + END GENERATE loop0; +-- wire_w_lg_w_lg_reset7w8w(0) <= wire_w_lg_reset7w(0) AND sim_activator(0); + wire_w_lg_w_lg_reset7w8w(0) <= (NOT transceiver_init AND NOT start) AND sim_activator(0); + wire_w_lg_w_lg_sim_counter_and2w3w(0) <= wire_w_lg_sim_counter_and2w(0) AND sim_counter_or(0); + loop1 : FOR i IN 0 TO 3 GENERATE + wire_w_lg_sim_counter_and1w(i) <= sim_counter_and(0) AND sim_counter_reg(i); + END GENERATE loop1; + wire_w_lg_reset7w(0) <= NOT reset; + wire_w_lg_sim_counter_and2w(0) <= NOT sim_counter_and(0); + busy <= busy_sim(0); + busy_sim(0) <= (wire_w_lg_reset7w(0) AND p0addr_sim(0) AND wire_w_lg_sim_counter_and2w(0)); + cal_error <= (OTHERS => '0'); + dprio_addr <= (OTHERS => '0'); + dprio_dataout <= (OTHERS => '0'); + dprio_rden <= '0'; + dprio_wren <= '0'; + quad_addr <= (OTHERS => '0'); + retain_addr <= '0'; + sim_activator <= p0addr_sim; + sim_counter_and(0) <= (((sim_counter_reg(0) AND sim_counter_reg(1)) AND sim_counter_reg(2)) AND sim_counter_reg(3)); + sim_counter_next <= wire_next_scount_num_result; + sim_counter_or(0) <= (((sim_counter_reg(0) OR sim_counter_reg(1)) OR sim_counter_reg(2)) OR sim_counter_reg(3)); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN p0addr_sim <= "1"; + END IF; + END PROCESS; + loop2 : FOR i IN 0 TO 3 GENERATE + wire_p0addr_sim_w_lg_w_lg_q4w5w(i) <= wire_p0addr_sim_w_lg_q4w(0) AND sim_counter_next(i); + END GENERATE loop2; + loop3 : FOR i IN 0 TO 3 GENERATE + wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) <= wire_p0addr_sim_w_lg_w_lg_q4w5w(i) OR wire_w_lg_sim_counter_and1w(i); + END GENERATE loop3; + wire_p0addr_sim_w_lg_q4w(0) <= p0addr_sim(0) OR wire_w_lg_w_lg_sim_counter_and2w3w(0); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN sim_counter_reg <= wire_w_lg_w_lg_w_lg_reset7w8w9w; + END IF; + END PROCESS; + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN + IF (first_run(0) = '1') THEN + first_run(0) <= (NOT sim_counter_and(0)); + ELSE + first_run(0) <= '0'; + END IF; + END IF; + END PROCESS; + wire_next_scount_num_result <= wire_next_scount_num_dataa + wire_next_scount_num_datab; + wire_next_scount_num_dataa <= sim_counter_reg; + wire_next_scount_num_datab <= "0001"; + +END RTL; --alt_cal +--VALID FILE + +LIBRARY ieee; +USE ieee.std_logic_unsigned.all; + +--synthesis_resources = lut 4 reg 5 +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY alt_cal_mm IS + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + CAL_PD_WR : string := "00101"; + CAL_RX_RD : string := "00110"; + CAL_RX_WR : string := "00111"; + CH_ADV : string := "01100"; + CH_WAIT : string := "00001"; + DPRIO_READ : string := "01110"; + DPRIO_WAIT : string := "01000"; + DPRIO_WRITE : string := "01111"; + IDLE : string := "00000"; + KICK_DELAY_OC : integer := 10010; + KICK_PAUSE : integer := 10001; + KICK_START_RD : string := "01101"; + KICK_START_WR : integer := 10000; + OFFSETS_PDEN_RD : string := "00011"; + OFFSETS_PDEN_WR : string := "00100"; + sample_length : string := "01100100"; + SAMPLE_TB : string := "01001"; + TEST_INPUT : string := "01010"; + TESTBUS_SET : string := "00010"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal_mm" + ); + PORT + ( + busy : OUT STD_LOGIC; + cal_error : OUT STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0); + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + retain_addr : OUT STD_LOGIC; + start : IN STD_LOGIC := '0'; + transceiver_init : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0') + ); +END alt_cal_mm; + +ARCHITECTURE RTL OF alt_cal_mm IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + ATTRIBUTE ALTERA_ATTRIBUTE : string; + ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "PRESERVE_REGISTER=ON"; + + SIGNAL p0addr_sim : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF p0addr_sim : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"; + + SIGNAL wire_p0addr_sim_w_lg_w_lg_q4w5w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_q4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF sim_counter_reg : SIGNAL IS "POWER_UP_LEVEL=LOW"; + SIGNAL first_run : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '1') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF first_run : SIGNAL IS "POWER_UP_LEVEL=HIGH"; + + SIGNAL wire_next_scount_num_dataa : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_next_scount_num_datab : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_next_scount_num_result : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_reset7w8w9w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_reset7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_sim_counter_and2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and1w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_reset7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL busy_sim : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_activator : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_and : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_next : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sim_counter_or : STD_LOGIC_VECTOR (0 DOWNTO 0); +BEGIN + + loop0 : FOR i IN 0 TO 3 GENERATE + wire_w_lg_w_lg_w_lg_reset7w8w9w(i) <= ((NOT start AND NOT transceiver_init) AND wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) AND NOT (reset AND first_run(0))) OR (reset AND NOT first_run(0)); + END GENERATE loop0; + wire_w_lg_w_lg_reset7w8w(0) <= wire_w_lg_reset7w(0) AND sim_activator(0); + wire_w_lg_w_lg_sim_counter_and2w3w(0) <= wire_w_lg_sim_counter_and2w(0) AND sim_counter_or(0); + loop1 : FOR i IN 0 TO 3 GENERATE + wire_w_lg_sim_counter_and1w(i) <= sim_counter_and(0) AND sim_counter_reg(i); + END GENERATE loop1; + wire_w_lg_reset7w(0) <= NOT reset; + wire_w_lg_sim_counter_and2w(0) <= NOT sim_counter_and(0); + busy <= busy_sim(0); + busy_sim(0) <= wire_w_lg_reset7w(0) AND (p0addr_sim(0) AND wire_w_lg_sim_counter_and2w(0)); + cal_error <= (OTHERS => '0'); + dprio_addr <= (OTHERS => '0'); + dprio_dataout <= (OTHERS => '0'); + dprio_rden <= '0'; + dprio_wren <= '0'; + quad_addr <= (OTHERS => '0'); + retain_addr <= '0'; + sim_activator <= p0addr_sim; + sim_counter_and(0) <= (((sim_counter_reg(0) AND sim_counter_reg(1)) AND sim_counter_reg(2)) AND sim_counter_reg(3)); + sim_counter_next <= wire_next_scount_num_result; + sim_counter_or(0) <= (((sim_counter_reg(0) OR sim_counter_reg(1)) OR sim_counter_reg(2)) OR sim_counter_reg(3)); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN p0addr_sim <= "1"; + END IF; + END PROCESS; + loop2 : FOR i IN 0 TO 3 GENERATE + wire_p0addr_sim_w_lg_w_lg_q4w5w(i) <= wire_p0addr_sim_w_lg_q4w(0) AND sim_counter_next(i); + END GENERATE loop2; + loop3 : FOR i IN 0 TO 3 GENERATE + wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) <= wire_p0addr_sim_w_lg_w_lg_q4w5w(i) OR wire_w_lg_sim_counter_and1w(i); + END GENERATE loop3; + wire_p0addr_sim_w_lg_q4w(0) <= p0addr_sim(0) OR wire_w_lg_w_lg_sim_counter_and2w3w(0); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN sim_counter_reg <= wire_w_lg_w_lg_w_lg_reset7w8w9w; + END IF; + END PROCESS; + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN + IF (first_run(0) = '1') THEN + first_run(0) <= (NOT sim_counter_and(0)); + ELSE + first_run(0) <= '0'; + END IF; + END IF; + END PROCESS; + wire_next_scount_num_result <= wire_next_scount_num_dataa + wire_next_scount_num_datab; + wire_next_scount_num_dataa <= sim_counter_reg; + wire_next_scount_num_datab <= "0001"; + +END RTL; --alt_cal_mm +--VALID FILE + +LIBRARY ieee; +USE ieee.std_logic_unsigned.all; + +--synthesis_resources = lut 4 reg 5 +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY alt_cal_c3gxb IS + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal_c3gxb" + ); + PORT + ( + busy : OUT STD_LOGIC; + cal_error : OUT STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0); + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + retain_addr : OUT STD_LOGIC; + start : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0) := (OTHERS => '0') + ); +END alt_cal_c3gxb; + +ARCHITECTURE RTL OF alt_cal_c3gxb IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + ATTRIBUTE ALTERA_ATTRIBUTE : string; + ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "PRESERVE_REGISTER=ON"; + + SIGNAL p0addr_sim : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF p0addr_sim : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"; + + SIGNAL wire_p0addr_sim_w_lg_w_lg_q4w5w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_q4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF sim_counter_reg : SIGNAL IS "POWER_UP_LEVEL=LOW"; + SIGNAL first_run : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '1') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF first_run : SIGNAL IS "POWER_UP_LEVEL=HIGH"; + + SIGNAL wire_next_scount_num_dataa : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_next_scount_num_datab : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_next_scount_num_result : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_reset7w8w9w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_reset7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_sim_counter_and2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and1w : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_reset7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL busy_sim : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_activator : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_and : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_next : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sim_counter_or : STD_LOGIC_VECTOR (0 DOWNTO 0); +BEGIN + + loop0 : FOR i IN 0 TO 3 GENERATE + wire_w_lg_w_lg_w_lg_reset7w8w9w(i) <= (wire_w_lg_w_lg_reset7w8w(0) AND wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) AND NOT (reset AND first_run(0))) OR (reset AND NOT first_run(0)); + END GENERATE loop0; + wire_w_lg_w_lg_reset7w8w(0) <= (NOT start) AND sim_activator(0); + wire_w_lg_w_lg_sim_counter_and2w3w(0) <= wire_w_lg_sim_counter_and2w(0) AND sim_counter_or(0); + loop1 : FOR i IN 0 TO 3 GENERATE + wire_w_lg_sim_counter_and1w(i) <= sim_counter_and(0) AND sim_counter_reg(i); + END GENERATE loop1; + wire_w_lg_reset7w(0) <= NOT reset; + wire_w_lg_sim_counter_and2w(0) <= NOT sim_counter_and(0); + busy <= busy_sim(0); + busy_sim(0) <= (wire_w_lg_reset7w(0) AND p0addr_sim(0) AND wire_w_lg_sim_counter_and2w(0)); + cal_error <= (OTHERS => '0'); + dprio_addr <= (OTHERS => '0'); + dprio_dataout <= (OTHERS => '0'); + dprio_rden <= '0'; + dprio_wren <= '0'; + quad_addr <= (OTHERS => '0'); + retain_addr <= '0'; + sim_activator <= p0addr_sim; + sim_counter_and(0) <= (((sim_counter_reg(0) AND sim_counter_reg(1)) AND sim_counter_reg(2)) AND sim_counter_reg(3)); + sim_counter_next <= wire_next_scount_num_result; + sim_counter_or(0) <= (((sim_counter_reg(0) OR sim_counter_reg(1)) OR sim_counter_reg(2)) OR sim_counter_reg(3)); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN p0addr_sim <= "1"; + END IF; + END PROCESS; + loop2 : FOR i IN 0 TO 3 GENERATE + wire_p0addr_sim_w_lg_w_lg_q4w5w(i) <= wire_p0addr_sim_w_lg_q4w(0) AND sim_counter_next(i); + END GENERATE loop2; + loop3 : FOR i IN 0 TO 3 GENERATE + wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) <= wire_p0addr_sim_w_lg_w_lg_q4w5w(i) OR wire_w_lg_sim_counter_and1w(i); + END GENERATE loop3; + wire_p0addr_sim_w_lg_q4w(0) <= p0addr_sim(0) OR wire_w_lg_w_lg_sim_counter_and2w3w(0); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN sim_counter_reg <= wire_w_lg_w_lg_w_lg_reset7w8w9w; + END IF; + END PROCESS; + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN + IF (first_run(0) = '1') THEN + first_run(0) <= (NOT sim_counter_and(0)); + ELSE + first_run(0) <= '0'; + END IF; + END IF; + END PROCESS; + wire_next_scount_num_result <= wire_next_scount_num_dataa + wire_next_scount_num_datab; + wire_next_scount_num_dataa <= sim_counter_reg; + wire_next_scount_num_datab <= "0001"; + +END RTL; +--VALID FILE + +LIBRARY ieee; +USE ieee.std_logic_unsigned.all; + +--synthesis_resources = lut 4 reg 5 +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY alt_cal_sv IS + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal_sv"; + sample_length : integer := 100; + pma_base_address : integer := 0 + ); + PORT + ( + busy : OUT STD_LOGIC; + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + start : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0') + ); +END alt_cal_sv; + +ARCHITECTURE RTL OF alt_cal_sv IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + ATTRIBUTE ALTERA_ATTRIBUTE : string; + ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "PRESERVE_REGISTER=ON"; + + SIGNAL p0addr_sim : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF p0addr_sim : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"; + + SIGNAL wire_p0addr_sim_w_lg_w_lg_q4w5w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_q4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_reg : STD_LOGIC_VECTOR(8 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF sim_counter_reg : SIGNAL IS "POWER_UP_LEVEL=LOW"; + SIGNAL first_run : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '1') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF first_run : SIGNAL IS "POWER_UP_LEVEL=HIGH"; + + SIGNAL wire_next_scount_num_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_next_scount_num_datab : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_next_scount_num_result : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_reset7w8w9w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_reset7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_sim_counter_and2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and1w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_w_lg_reset7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL busy_sim : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_activator : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_and : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_next : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL sim_counter_or : STD_LOGIC_VECTOR (0 DOWNTO 0); +BEGIN + + loop0 : FOR i IN 0 TO 8 GENERATE + wire_w_lg_w_lg_w_lg_reset7w8w9w(i) <= (wire_w_lg_w_lg_reset7w8w(0) AND wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) AND NOT (reset AND first_run(0))) OR (reset AND NOT first_run(0)); + END GENERATE loop0; + wire_w_lg_w_lg_reset7w8w(0) <= (NOT start) AND sim_activator(0); + wire_w_lg_w_lg_sim_counter_and2w3w(0) <= wire_w_lg_sim_counter_and2w(0) AND sim_counter_or(0); + loop1 : FOR i IN 0 TO 8 GENERATE + wire_w_lg_sim_counter_and1w(i) <= sim_counter_and(0) AND sim_counter_reg(i); + END GENERATE loop1; + wire_w_lg_reset7w(0) <= NOT reset; + wire_w_lg_sim_counter_and2w(0) <= NOT sim_counter_and(0); + busy <= busy_sim(0); + busy_sim(0) <= (wire_w_lg_reset7w(0) AND p0addr_sim(0) AND wire_w_lg_sim_counter_and2w(0)); + dprio_addr <= (OTHERS => '0'); + dprio_dataout <= (OTHERS => '0'); + dprio_rden <= '0'; + dprio_wren <= '0'; + quad_addr <= (OTHERS => '0'); + sim_activator <= p0addr_sim; + sim_counter_and(0) <= (sim_counter_reg(0) AND sim_counter_reg(1) AND sim_counter_reg(2) AND sim_counter_reg(3) AND sim_counter_reg(4) AND sim_counter_reg(5) AND sim_counter_reg(6) AND sim_counter_reg(7) AND sim_counter_reg(8)); + sim_counter_next <= wire_next_scount_num_result; + sim_counter_or(0) <= (sim_counter_reg(0) OR sim_counter_reg(1) OR sim_counter_reg(2) OR sim_counter_reg(3) OR sim_counter_reg(4) OR sim_counter_reg(5) OR sim_counter_reg(6) OR sim_counter_reg(7) OR sim_counter_reg(8)); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN p0addr_sim <= "1"; + END IF; + END PROCESS; + loop2 : FOR i IN 0 TO 8 GENERATE + wire_p0addr_sim_w_lg_w_lg_q4w5w(i) <= wire_p0addr_sim_w_lg_q4w(0) AND sim_counter_next(i); + END GENERATE loop2; + loop3 : FOR i IN 0 TO 8 GENERATE + wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) <= wire_p0addr_sim_w_lg_w_lg_q4w5w(i) OR wire_w_lg_sim_counter_and1w(i); + END GENERATE loop3; + wire_p0addr_sim_w_lg_q4w(0) <= p0addr_sim(0) OR wire_w_lg_w_lg_sim_counter_and2w3w(0); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN sim_counter_reg <= wire_w_lg_w_lg_w_lg_reset7w8w9w; + END IF; + END PROCESS; + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN + IF (first_run(0) = '1') THEN + first_run(0) <= (NOT sim_counter_and(0)); + ELSE + first_run(0) <= '0'; + END IF; + END IF; + END PROCESS; + wire_next_scount_num_result <= wire_next_scount_num_dataa + wire_next_scount_num_datab; + wire_next_scount_num_dataa <= sim_counter_reg; + wire_next_scount_num_datab <= "000000001"; + +END RTL; +--VALID FILE + +LIBRARY ieee; +USE ieee.std_logic_unsigned.all; + +--synthesis_resources = lut 4 reg 5 +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY alt_cal_av IS + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal_av"; + sample_length : integer := 100; + pma_base_address : integer := 0 + ); + PORT + ( + busy : OUT STD_LOGIC; + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + start : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0') + ); +END alt_cal_av; + +ARCHITECTURE RTL OF alt_cal_av IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + ATTRIBUTE ALTERA_ATTRIBUTE : string; + ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "PRESERVE_REGISTER=ON"; + + SIGNAL p0addr_sim : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF p0addr_sim : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"; + + SIGNAL wire_p0addr_sim_w_lg_w_lg_q4w5w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_p0addr_sim_w_lg_q4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_reg : STD_LOGIC_VECTOR(8 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF sim_counter_reg : SIGNAL IS "POWER_UP_LEVEL=LOW"; + SIGNAL first_run : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '1') + -- synopsys translate_on + ; + ATTRIBUTE ALTERA_ATTRIBUTE OF first_run : SIGNAL IS "POWER_UP_LEVEL=HIGH"; + + SIGNAL wire_next_scount_num_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_next_scount_num_datab : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_next_scount_num_result : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_reset7w8w9w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_reset7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_sim_counter_and2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and1w : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_w_lg_reset7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sim_counter_and2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL busy_sim : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_activator : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_and : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sim_counter_next : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL sim_counter_or : STD_LOGIC_VECTOR (0 DOWNTO 0); +BEGIN + + loop0 : FOR i IN 0 TO 8 GENERATE + wire_w_lg_w_lg_w_lg_reset7w8w9w(i) <= (wire_w_lg_w_lg_reset7w8w(0) AND wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) AND NOT (reset AND first_run(0))) OR (reset AND NOT first_run(0)); + END GENERATE loop0; + wire_w_lg_w_lg_reset7w8w(0) <= (NOT start) AND sim_activator(0); + wire_w_lg_w_lg_sim_counter_and2w3w(0) <= wire_w_lg_sim_counter_and2w(0) AND sim_counter_or(0); + loop1 : FOR i IN 0 TO 8 GENERATE + wire_w_lg_sim_counter_and1w(i) <= sim_counter_and(0) AND sim_counter_reg(i); + END GENERATE loop1; + wire_w_lg_reset7w(0) <= NOT reset; + wire_w_lg_sim_counter_and2w(0) <= NOT sim_counter_and(0); + busy <= busy_sim(0); + busy_sim(0) <= (wire_w_lg_reset7w(0) AND p0addr_sim(0) AND wire_w_lg_sim_counter_and2w(0)); + dprio_addr <= (OTHERS => '0'); + dprio_dataout <= (OTHERS => '0'); + dprio_rden <= '0'; + dprio_wren <= '0'; + quad_addr <= (OTHERS => '0'); + sim_activator <= p0addr_sim; + sim_counter_and(0) <= (sim_counter_reg(0) AND sim_counter_reg(1) AND sim_counter_reg(2) AND sim_counter_reg(3) AND sim_counter_reg(4) AND sim_counter_reg(5) AND sim_counter_reg(6) AND sim_counter_reg(7) AND sim_counter_reg(8)); + sim_counter_next <= wire_next_scount_num_result; + sim_counter_or(0) <= (sim_counter_reg(0) OR sim_counter_reg(1) OR sim_counter_reg(2) OR sim_counter_reg(3) OR sim_counter_reg(4) OR sim_counter_reg(5) OR sim_counter_reg(6) OR sim_counter_reg(7) OR sim_counter_reg(8)); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN p0addr_sim <= "1"; + END IF; + END PROCESS; + loop2 : FOR i IN 0 TO 8 GENERATE + wire_p0addr_sim_w_lg_w_lg_q4w5w(i) <= wire_p0addr_sim_w_lg_q4w(0) AND sim_counter_next(i); + END GENERATE loop2; + loop3 : FOR i IN 0 TO 8 GENERATE + wire_p0addr_sim_w_lg_w_lg_w_lg_q4w5w6w(i) <= wire_p0addr_sim_w_lg_w_lg_q4w5w(i) OR wire_w_lg_sim_counter_and1w(i); + END GENERATE loop3; + wire_p0addr_sim_w_lg_q4w(0) <= p0addr_sim(0) OR wire_w_lg_w_lg_sim_counter_and2w3w(0); + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN sim_counter_reg <= wire_w_lg_w_lg_w_lg_reset7w8w9w; + END IF; + END PROCESS; + PROCESS (clock) + BEGIN + IF (clock = '1' AND clock'event) THEN + IF (first_run(0) = '1') THEN + first_run(0) <= (NOT sim_counter_and(0)); + ELSE + first_run(0) <= '0'; + END IF; + END IF; + END PROCESS; + wire_next_scount_num_result <= wire_next_scount_num_dataa + wire_next_scount_num_datab; + wire_next_scount_num_dataa <= sim_counter_reg; + wire_next_scount_num_datab <= "000000001"; + +END RTL; +--VALID FILE + +------------------------------------------------------------------- +-- Filename : alt_aeq_s4.vhd +-- +-- Description : Simulation model for ADCE +-- +-- Limitation : Currently, only applies for Stratix IV +-- +-- Copyright (c) Altera Corporation 1997-2008 +-- All rights reserved +-- +--------------------------------------------------------------------- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_unsigned.all; + +LIBRARY std; +USE std.textio.all; + +PACKAGE alt_aeq_s4_func IS + FUNCTION to_integer ( + val : std_logic) RETURN integer; + + FUNCTION to_integer ( + val : std_logic_vector) RETURN integer; + + FUNCTION or_br ( + val : std_logic_vector) RETURN std_logic; + +END; + +PACKAGE BODY alt_aeq_s4_func IS + + FUNCTION to_integer ( + val : std_logic) RETURN integer IS + + VARIABLE rtn : integer := 0; + BEGIN + IF (val = '1') THEN + rtn := 1; + ELSE + rtn := 0; + END IF; + RETURN(rtn); + END to_integer; + + -- + + FUNCTION to_integer ( + val : std_logic_vector) RETURN integer IS + + CONSTANT vec : std_logic_vector(val'high-val'low DOWNTO 0) := val; + VARIABLE rtn : integer := 0; + BEGIN + FOR index IN vec'RANGE LOOP + IF (vec(index) = '1') THEN + rtn := rtn + (2**index); + END IF; + END LOOP; + RETURN(rtn); + END to_integer; + + FUNCTION or_br ( + val : std_logic_vector) RETURN std_logic IS + + VARIABLE rtn : std_logic := '0'; + BEGIN + FOR index IN val'RANGE LOOP + rtn := rtn OR val(index); + END LOOP; + RETURN(rtn); + END or_br; + + + +END; + + +-- + + +USE work.alt_aeq_s4_func.all; +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_unsigned.all; + +ENTITY alt_aeq_s4 IS + GENERIC ( + + show_errors : STRING := "NO"; + radce_hflck : INTEGER := 0; + radce_lflck : INTEGER := 0; + use_hw_conv_det : INTEGER := 0; + + number_of_channels : INTEGER := 5; + channel_address_width : INTEGER := 3; + lpm_type : STRING := "alt_aeq_s4"; + lpm_hint : STRING := "UNUSED" + ); + PORT ( + + reconfig_clk : IN STD_LOGIC; + aclr : IN STD_LOGIC; + calibrate : IN STD_LOGIC; + shutdown : IN STD_LOGIC; + all_channels : IN STD_LOGIC; + logical_channel_address : IN STD_LOGIC_VECTOR(channel_address_width - 1 DOWNTO 0); + remap_address : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + quad_address : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + adce_done : IN STD_LOGIC_VECTOR(number_of_channels - 1 DOWNTO 0); + busy : OUT STD_LOGIC; + adce_standby : OUT STD_LOGIC_VECTOR(number_of_channels - 1 DOWNTO 0); + adce_continuous : IN STD_LOGIC; + adce_cal_busy : OUT STD_LOGIC; + + dprio_busy : IN STD_LOGIC; + dprio_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dprio_wren : OUT STD_LOGIC; + dprio_rden : OUT STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + dprio_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + + eqout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + timeout : OUT STD_LOGIC; + testbuses : IN STD_LOGIC_VECTOR(7 * number_of_channels - 1 DOWNTO 0); + testbus_sels : OUT STD_LOGIC_VECTOR(4 * number_of_channels - 1 DOWNTO 0); + + conv_error : OUT STD_LOGIC_VECTOR(number_of_channels - 1 DOWNTO 0); + error : OUT STD_LOGIC_VECTOR(number_of_channels - 1 DOWNTO 0) + ); +END alt_aeq_s4; + +ARCHITECTURE trans OF alt_aeq_s4 IS + + SIGNAL busy_counter : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL busy_xhdl0 : STD_LOGIC; + SIGNAL adce_cal_busy_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + busy <= busy_xhdl0; + adce_cal_busy <= adce_cal_busy_xhdl0; + + dprio_addr <= (OTHERS => '0'); + dprio_data <= (OTHERS => '0'); + dprio_rden <= '0'; + dprio_wren <= '0'; + quad_address <= (OTHERS => '0'); + busy_xhdl0 <= (or_br(busy_counter)); + adce_cal_busy_xhdl0 <= (or_br(busy_counter(7 downto 4))); + timeout <= '0'; + + error <= (OTHERS => '0'); + conv_error <= (OTHERS => '0'); + eqout <= (OTHERS => '0'); + testbus_sels <= (OTHERS => '0'); + + + PROCESS (reconfig_clk) + BEGIN + IF (reconfig_clk'EVENT AND reconfig_clk = '1') THEN + IF (aclr = '1') THEN + busy_counter <= "00000000"; + adce_standby(to_integer(logical_channel_address)) <= '0'; + ELSIF (calibrate = '1') THEN + busy_counter <= "11111111"; + adce_standby <= (OTHERS => '0'); + ELSIF (shutdown = '1') THEN + busy_counter <= "00001111"; + adce_standby(to_integer(logical_channel_address)) <= '1'; + ELSIF (busy_xhdl0 = '1') THEN + busy_counter <= busy_counter - "00000001"; + END IF; + END IF; + END PROCESS; + + +END trans; + + + +------------------------------------------------------------------- +-- Filename : alt_eyemon.vhd +-- +-- Description : Simulation model for Eye Monitor (EyeQ) +-- +-- Limitation : Currently, only supported for Stratix IV +-- +-- Copyright (c) Altera Corporation 1997-2008 +-- All rights reserved +-- +--------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + +library std; +use std.textio.all; + +package alt_eyemon_func is + + function or_br ( + val : std_logic_vector) return std_logic; + + FUNCTION to_integer ( + val : bit_vector) RETURN integer; + + FUNCTION to_integer ( + val : std_logic_vector) RETURN integer; + + function to_integer ( + val : std_logic) return integer; + + function to_stdlogic ( + val : in boolean) return std_logic; + + function to_stdlogicvector ( + val : in integer; + len : in integer) return std_logic_vector; + + function to_stdlogicvector ( + val : in boolean; + len : in integer) return std_logic_vector; + +end; + +package body alt_eyemon_func is + + function to_integer ( + val : bit_vector) return integer is + + constant vec : bit_vector(val'high-val'low downto 0) := val; + variable rtn : integer := 0; + begin + for index in vec'range loop + if (vec(index) = '1') then + rtn := rtn + (2**index); + end if; + end loop; + return(rtn); + end to_integer; + + -- + + function to_integer ( + val : std_logic_vector) return integer is + + constant vec : std_logic_vector(val'high-val'low downto 0) := val; + variable rtn : integer := 0; + begin + for index in vec'range loop + if (vec(index) = '1') then + rtn := rtn + (2**index); + end if; + end loop; + return(rtn); + end to_integer; + + -- + + function or_br ( + val : std_logic_vector) return std_logic is + + variable rtn : std_logic := '0'; + begin + for index in val'range loop + rtn := rtn or val(index); + end loop; + return(rtn); + end or_br; + + -- + + function to_integer ( + val : std_logic) return integer is + + variable rtn : integer := 0; + begin + if (val = '1') then + rtn := 1; + else + rtn := 0; + end if; + return(rtn); + end to_integer; + + -- + + function to_stdlogic ( + val : in boolean) return std_logic is + begin + if (val) then + return('1'); + else + return('0'); + end if; + end to_stdlogic; + + -- + + function to_stdlogicvector ( + val : in integer; + len : in integer) return std_logic_vector is + + variable rtn : std_logic_vector(len-1 downto 0) := (others => '0'); + variable num : integer := val; + variable r : integer; + begin + for index in 0 to len-1 loop + r := num rem 2; + num := num/2; + if (r = 1) then + rtn(index) := '1'; + else + rtn(index) := '0'; + end if; + end loop; + return(rtn); + end to_stdlogicvector; + + -- + + function to_stdlogicvector ( + val : in boolean; + len : in integer) return std_logic_vector is + + variable rtn : std_logic_vector(len-1 downto 0) := (others => '0'); + begin + rtn(0) := to_stdlogic(val); + return(rtn); + end to_stdlogicvector; + + + +end; + + +-- + +use work.alt_eyemon_func.all; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + + +entity alt_eyemon is + generic ( + channel_address_width : integer := 3; + lpm_type : string := "alt_eyemon"; + lpm_hint : string := "UNUSED"; + + avmm_slave_addr_width : integer := 16; + avmm_slave_rdata_width : integer := 16; + avmm_slave_wdata_width : integer := 16; + + avmm_master_addr_width : integer := 16; + avmm_master_rdata_width : integer := 16; + avmm_master_wdata_width : integer := 16; + + dprio_addr_width : integer := 16; + dprio_data_width : integer := 16; + ireg_wdaddr_width : integer := 2; + ireg_chaddr_width : integer := 2; + ireg_data_width : integer := 16 + + ); + port ( + i_resetn : in std_logic; + i_avmm_clk : in std_logic; + + i_avmm_saddress : in std_logic_vector(avmm_slave_addr_width - 1 downto 0); + i_avmm_sread : in std_logic; + i_avmm_swrite : in std_logic; + i_avmm_swritedata : in std_logic_vector(avmm_slave_wdata_width - 1 downto 0); + o_avmm_sreaddata : out std_logic_vector(avmm_slave_rdata_width - 1 downto 0); + o_avmm_swaitrequest : out std_logic; + + i_remap_phase : in std_logic; + i_remap_address : in std_logic_vector(11 downto 0); + o_quad_address : out std_logic_vector(8 downto 0); + o_reconfig_busy : out std_logic; + + i_dprio_busy : in std_logic; + i_dprio_in : in std_logic_vector(dprio_data_width - 1 downto 0); + o_dprio_wren : out std_logic; + o_dprio_rden : out std_logic; + o_dprio_addr : out std_logic_vector(dprio_addr_width - 1 downto 0); + o_dprio_data : out std_logic_vector(dprio_data_width - 1 downto 0) + ); +end alt_eyemon; + +architecture trans of alt_eyemon is + type type_xhdl0 is array (((2 ** channel_address_width) - 1) downto 0) of std_logic_vector(6 downto 0); + type state_type is (ST_IDLE, ST_WRITE, ST_READ); + + signal state : state_type := ST_IDLE; + signal state0q : state_type := ST_IDLE; + signal reg_read : std_logic; + signal reg_write : std_logic; + signal busy_counter : std_logic_vector(5 downto 0) := "000000"; + + signal reg_chaddress : std_logic_vector(channel_address_width - 1 downto 0) := to_stdlogicvector(0, channel_address_width); + signal reg_chaddress0q : std_logic_vector(channel_address_width - 1 downto 0) := to_stdlogicvector(0, channel_address_width); + signal reg_data : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_data0q : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_ctrlstatus : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_ctrlstatus0q : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_wdaddress : std_logic_vector(ireg_wdaddr_width - 1 downto 0) := to_stdlogicvector(0, ireg_wdaddr_width); + signal reg_wdaddress0q : std_logic_vector(ireg_wdaddr_width - 1 downto 0) := to_stdlogicvector(0, ireg_wdaddr_width); + + signal dprio_reg : type_xhdl0; + signal dprio_reg0q : type_xhdl0; + + signal invalid_channel_address : std_logic; + signal invalid_word_address : std_logic; + signal i : integer; + -- X-HDL generated signals + + signal xhdl1 : std_logic; + signal xhdl2 : std_logic; +begin + + o_dprio_wren <= '0'; + o_dprio_rden <= '0'; + o_dprio_addr <= (others => '0'); + o_dprio_data <=(others => '0'); + o_quad_address <= (others => '0'); + o_reconfig_busy <= reg_ctrlstatus0q(15); + + process (i_avmm_clk) + begin + if (i_avmm_clk'event and i_avmm_clk = '1') then + if ((not(i_resetn)) = '1') then + state0q <= ST_IDLE; + else + state0q <= state; + end if; + end if; + end process; + + + process (i_avmm_clk) + begin + if (i_avmm_clk'event and i_avmm_clk = '1') then + if ((not(i_resetn)) = '1') then + busy_counter <= "000000"; + elsif (((reg_ctrlstatus(0) = '1') and (reg_ctrlstatus0q(0) = '0')) and ((not(reg_ctrlstatus(1))) = '1')) then + busy_counter <= "111111"; + elsif (((reg_ctrlstatus(0) = '1') and (reg_ctrlstatus0q(0) = '0')) and ((reg_ctrlstatus(1)) = '1')) then + busy_counter <= "011111"; + elsif ((or_BR(busy_counter)) = '1') then + busy_counter <= busy_counter - "000001"; + end if; + end if; + end process; + + + process (state0q, i_avmm_sread, i_avmm_swrite, reg_ctrlstatus0q) + begin + o_avmm_swaitrequest <= '0'; + reg_write <= '0'; + + reg_read <= '0'; + case state0q is + when ST_WRITE => + o_avmm_swaitrequest <= '0'; + state <= ST_IDLE; + when ST_READ => + o_avmm_swaitrequest <= '0'; + reg_read <= '1'; + state <= ST_IDLE; + when others => + if (i_avmm_sread = '1') then + o_avmm_swaitrequest <= '1'; + reg_read <= '1'; + state <= ST_READ; + elsif (i_avmm_swrite = '1') then + o_avmm_swaitrequest <= '1'; + if ((reg_ctrlstatus0q(15)) = '1') then + reg_write <= '0'; + else + reg_write <= '1'; + end if; + state <= ST_WRITE; + else + o_avmm_swaitrequest <= '0'; + state <= ST_IDLE; + end if; + end case; + end process; + + + process (i_avmm_clk) + begin + if (i_avmm_clk'event and i_avmm_clk = '1') then + if ((not(i_resetn)) = '1') then + reg_chaddress0q <= (others => '0'); + reg_data0q <= (others => '0'); + reg_ctrlstatus0q <= (others => '0'); + reg_wdaddress0q <= (others => '0'); + for i in 0 to ((2 ** channel_address_width)) - 1 loop + dprio_reg0q(i) <= (others => '0'); + end loop; + else + reg_chaddress0q <= reg_chaddress; + reg_data0q <= reg_data; + reg_ctrlstatus0q <= reg_ctrlstatus; + reg_wdaddress0q <= reg_wdaddress; + for i in 0 to ((2 ** channel_address_width)) - 1 loop + dprio_reg0q(i) <= dprio_reg(i); + end loop; + end if; + end if; + end process; + + process (reg_read, i_avmm_saddress, reg_ctrlstatus0q, reg_chaddress0q, reg_wdaddress0q, reg_data0q) + begin + if (reg_read = '1') then + if (i_avmm_saddress (15 downto 0) = "0000000000000000") then + o_avmm_sreaddata(ireg_data_width - 1 downto 0) <= reg_ctrlstatus0q; + elsif (i_avmm_saddress (15 downto 0)= "0000000000000001") then + o_avmm_sreaddata(channel_address_width - 1 downto 0) <= reg_chaddress0q; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000010") then + o_avmm_sreaddata(ireg_wdaddr_width - 1 downto 0) <= reg_wdaddress0q; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000011") then + o_avmm_sreaddata <= reg_data0q; + else + o_avmm_sreaddata <= (others => '0'); + end if; + else + o_avmm_sreaddata <= (others => '0'); + end if; + end process; + invalid_channel_address <= to_stdlogic((i_remap_address = "111111111111")); + invalid_word_address <= to_stdlogic((reg_wdaddress0q > "01")); + + + xhdl1 <= '0' when ((i_avmm_swritedata(14)) = '1') else + reg_ctrlstatus0q(14); + xhdl2 <= '0' when ((i_avmm_swritedata(13)) = '1') else + reg_ctrlstatus0q(13); + process (reg_chaddress0q, reg_data0q, reg_ctrlstatus0q, reg_wdaddress0q, i, dprio_reg, busy_counter, dprio_reg0q, reg_write, i_avmm_saddress, i_avmm_swritedata, invalid_channel_address, invalid_word_address) + begin + reg_chaddress <= reg_chaddress0q; + reg_data <= reg_data0q; + reg_ctrlstatus <= reg_ctrlstatus0q; + reg_wdaddress <= reg_wdaddress0q; + for i in 0 to ((2 ** channel_address_width)) - 1 loop + dprio_reg0q(i) <= dprio_reg(i); + end loop; + if (busy_counter = "000001") then + reg_ctrlstatus(15) <= '0'; + reg_ctrlstatus(0) <= '0'; + if ((reg_ctrlstatus0q(1)) = '1') then + if (reg_wdaddress0q = "00") then + reg_data(0) <= dprio_reg0q(to_integer(reg_chaddress0q))(0); + reg_data(15 downto 1) <= "000000000000000"; + elsif (reg_wdaddress0q = "01") then + reg_data(5 downto 0) <= dprio_reg0q(to_integer(reg_chaddress0q))(6 downto 1); + reg_data(15 downto 6) <= "0000000000"; + end if; + end if; + end if; + if (reg_write = '1') then + if (i_avmm_saddress = "0000000000000000") then + reg_ctrlstatus(1) <= i_avmm_swritedata(1); + if ((i_avmm_swritedata(0)) = '1') then + if ((invalid_channel_address = '1') or (invalid_word_address = '1')) then + reg_ctrlstatus(15) <= '0'; + reg_ctrlstatus(14) <= invalid_word_address; + reg_ctrlstatus(13) <= invalid_channel_address; + else + if ((not(i_avmm_swritedata(1))) = '1') then + if (reg_wdaddress0q = "00") then + dprio_reg(to_integer(reg_chaddress0q))(0) <= (reg_data0q(0)); + elsif (reg_wdaddress0q = "01") then + dprio_reg(to_integer(reg_chaddress0q))(6 downto 1) <= (reg_data0q(5 downto 0)); + end if; + end if; + reg_ctrlstatus(0) <= '1'; + reg_ctrlstatus(15) <= '1'; + reg_ctrlstatus(14) <= '0'; + reg_ctrlstatus(13) <= '0'; + end if; + else + reg_ctrlstatus(15) <= '0'; + reg_ctrlstatus(14) <= xhdl1; + reg_ctrlstatus(13) <= xhdl2; + end if; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000001") then + if (channel_address_width < 2) then + reg_chaddress <= i_avmm_swritedata(0 downto 0); + else + reg_chaddress <= i_avmm_swritedata(channel_address_width - 1 downto 0); + end if; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000010") then + reg_wdaddress <= i_avmm_swritedata(ireg_wdaddr_width - 1 downto 0); + elsif (i_avmm_saddress(15 downto 0) = "0000000000000011") then + reg_data <= i_avmm_swritedata(ireg_data_width - 1 downto 0); + end if; + end if; + end process; + + +end trans; +------------------------------------------------------------------- +-- Filename : alt_dfe.vhd +-- +-- Description : Simulation model for DFE +-- +-- Limitation : Currently, only supported for Stratix IV +-- +-- Copyright (c) Altera Corporation 1997-2008 +-- All rights reserved +-- +--------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + +library std; +use std.textio.all; + +package alt_dfe_func is + + function or_br ( + val : std_logic_vector) return std_logic; + + FUNCTION to_integer ( + val : bit_vector) RETURN integer; + + FUNCTION to_integer ( + val : std_logic_vector) RETURN integer; + + function to_integer ( + val : std_logic) return integer; + + function to_stdlogic ( + val : in boolean) return std_logic; + + function to_stdlogicvector ( + val : in integer; + len : in integer) return std_logic_vector; + + function to_stdlogicvector ( + val : in boolean; + len : in integer) return std_logic_vector; + +end; + +package body alt_dfe_func is + + function to_integer ( + val : bit_vector) return integer is + + constant vec : bit_vector(val'high-val'low downto 0) := val; + variable rtn : integer := 0; + begin + for index in vec'range loop + if (vec(index) = '1') then + rtn := rtn + (2**index); + end if; + end loop; + return(rtn); + end to_integer; + + -- + + function to_integer ( + val : std_logic_vector) return integer is + + constant vec : std_logic_vector(val'high-val'low downto 0) := val; + variable rtn : integer := 0; + begin + for index in vec'range loop + if (vec(index) = '1') then + rtn := rtn + (2**index); + end if; + end loop; + return(rtn); + end to_integer; + + -- + + function or_br ( + val : std_logic_vector) return std_logic is + + variable rtn : std_logic := '0'; + begin + for index in val'range loop + rtn := rtn or val(index); + end loop; + return(rtn); + end or_br; + + -- + + function to_integer ( + val : std_logic) return integer is + + variable rtn : integer := 0; + begin + if (val = '1') then + rtn := 1; + else + rtn := 0; + end if; + return(rtn); + end to_integer; + + -- + + function to_stdlogic ( + val : in boolean) return std_logic is + begin + if (val) then + return('1'); + else + return('0'); + end if; + end to_stdlogic; + + -- + + function to_stdlogicvector ( + val : in integer; + len : in integer) return std_logic_vector is + + variable rtn : std_logic_vector(len-1 downto 0) := (others => '0'); + variable num : integer := val; + variable r : integer; + begin + for index in 0 to len-1 loop + r := num rem 2; + num := num/2; + if (r = 1) then + rtn(index) := '1'; + else + rtn(index) := '0'; + end if; + end loop; + return(rtn); + end to_stdlogicvector; + + -- + + function to_stdlogicvector ( + val : in boolean; + len : in integer) return std_logic_vector is + + variable rtn : std_logic_vector(len-1 downto 0) := (others => '0'); + begin + rtn(0) := to_stdlogic(val); + return(rtn); + end to_stdlogicvector; + + + +end; + + +-- + +use work.alt_dfe_func.all; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + + +entity alt_dfe is + generic ( + channel_address_width : integer := 3; + lpm_type : string := "alt_dfe"; + lpm_hint : string := "UNUSED"; + + avmm_slave_addr_width : integer := 16; + avmm_slave_rdata_width : integer := 16; + avmm_slave_wdata_width : integer := 16; + + avmm_master_addr_width : integer := 16; + avmm_master_rdata_width : integer := 16; + avmm_master_wdata_width : integer := 16; + + dprio_addr_width : integer := 16; + dprio_data_width : integer := 16; + ireg_chaddr_width : integer := 2; + ireg_wdaddr_width : integer := 2; + ireg_data_width : integer := 16 + + ); + port ( + i_resetn : in std_logic; + i_avmm_clk : in std_logic; + + i_avmm_saddress : in std_logic_vector(avmm_slave_addr_width - 1 downto 0); + i_avmm_sread : in std_logic; + i_avmm_swrite : in std_logic; + i_avmm_swritedata : in std_logic_vector(avmm_slave_wdata_width - 1 downto 0); + o_avmm_sreaddata : out std_logic_vector(avmm_slave_rdata_width - 1 downto 0); + o_avmm_swaitrequest : out std_logic; + + i_remap_address : in std_logic_vector(11 downto 0); + o_quad_address : out std_logic_vector(8 downto 0); + o_reconfig_busy : out std_logic; + + i_dprio_busy : in std_logic; + i_dprio_in : in std_logic_vector(dprio_data_width - 1 downto 0); + o_dprio_wren : out std_logic; + o_dprio_rden : out std_logic; + o_dprio_addr : out std_logic_vector(dprio_addr_width - 1 downto 0); + o_dprio_data : out std_logic_vector(dprio_data_width - 1 downto 0) + ); +end alt_dfe; + +architecture trans of alt_dfe is + type type_xhdl0 is array (((2 ** channel_address_width) - 1) downto 0) of std_logic_vector(12 downto 0); + type state_type is (ST_IDLE, ST_WRITE, ST_READ); + + signal state : state_type := ST_IDLE; + signal state0q : state_type := ST_IDLE; + signal reg_read : std_logic; + signal reg_write : std_logic; + signal busy_counter : std_logic_vector(5 downto 0) := "000000"; + + signal reg_chaddress : std_logic_vector(channel_address_width - 1 downto 0) := to_stdlogicvector(0, channel_address_width); + signal reg_chaddress0q : std_logic_vector(channel_address_width - 1 downto 0) := to_stdlogicvector(0, channel_address_width); + signal reg_data : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_data0q : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_ctrlstatus : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_ctrlstatus0q : std_logic_vector(ireg_data_width - 1 downto 0) := to_stdlogicvector(0, ireg_data_width); + signal reg_wdaddress : std_logic_vector(ireg_wdaddr_width - 1 downto 0) := to_stdlogicvector(0, ireg_wdaddr_width); + signal reg_wdaddress0q : std_logic_vector(ireg_wdaddr_width - 1 downto 0) := to_stdlogicvector(0, ireg_wdaddr_width); + + signal dprio_reg : type_xhdl0; + signal dprio_reg0q : type_xhdl0; + + signal invalid_channel_address : std_logic; + signal invalid_word_address : std_logic; + signal i : integer; + -- X-HDL generated signals + + signal xhdl1 : std_logic; + signal xhdl2 : std_logic; +begin + + o_dprio_wren <= '0'; + o_dprio_rden <= '0'; + o_dprio_addr <= (others => '0'); + o_dprio_data <= (others => '0'); + o_quad_address <= (others => '0'); + o_reconfig_busy <= reg_ctrlstatus0q(15); + + process (i_avmm_clk) + begin + if (i_avmm_clk'event and i_avmm_clk = '1') then + if ((not(i_resetn)) = '1') then + state0q <= ST_IDLE; + else + state0q <= state; + end if; + end if; + end process; + + + process (i_avmm_clk) + begin + if (i_avmm_clk'event and i_avmm_clk = '1') then + if ((not(i_resetn)) = '1') then + busy_counter <= (others => '0'); + elsif (((reg_ctrlstatus(0) = '1') and (reg_ctrlstatus0q(0) = '0')) and ((not(reg_ctrlstatus(1))) = '1')) then + busy_counter <= "111111"; + elsif (((reg_ctrlstatus(0) = '1') and (reg_ctrlstatus0q(0) = '0')) and ((reg_ctrlstatus(1)) = '1')) then + busy_counter <= "011111"; + elsif ((or_BR(busy_counter)) = '1') then + busy_counter <= busy_counter - "000001"; + end if; + end if; + end process; + + + process (state0q, i_avmm_sread, i_avmm_swrite, reg_ctrlstatus0q) + begin + o_avmm_swaitrequest <= '0'; + reg_write <= '0'; + + reg_read <= '0'; + case state0q is + when ST_WRITE => + o_avmm_swaitrequest <= '0'; + state <= ST_IDLE; + when ST_READ => + o_avmm_swaitrequest <= '0'; + reg_read <= '1'; + state <= ST_IDLE; + when others => + if (i_avmm_sread = '1') then + o_avmm_swaitrequest <= '1'; + reg_read <= '1'; + state <= ST_READ; + elsif (i_avmm_swrite = '1') then + o_avmm_swaitrequest <= '1'; + if ((reg_ctrlstatus0q(15)) = '1') then + reg_write <= '0'; + else + reg_write <= '1'; + end if; + state <= ST_WRITE; + else + o_avmm_swaitrequest <= '0'; + state <= ST_IDLE; + end if; + end case; + end process; + + + process (i_avmm_clk) + begin + if (i_avmm_clk'event and i_avmm_clk = '1') then + if ((not(i_resetn)) = '1') then + reg_chaddress0q <= (others => '0'); + reg_data0q <= (others => '0'); + reg_ctrlstatus0q <= (others => '0'); + reg_wdaddress0q <= (others => '0'); + for i in 0 to ((2 ** channel_address_width)) - 1 loop + dprio_reg0q(i) <= (others => '0'); + end loop; + else + reg_chaddress0q <= reg_chaddress; + reg_data0q <= reg_data; + reg_ctrlstatus0q <= reg_ctrlstatus; + reg_wdaddress0q <= reg_wdaddress; + for i in 0 to ((2 ** channel_address_width)) - 1 loop + dprio_reg0q(i) <= dprio_reg(i); + end loop; + end if; + end if; + end process; + + process (reg_read, i_avmm_saddress, reg_ctrlstatus0q, reg_chaddress0q, reg_wdaddress0q, reg_data0q) + begin + if (reg_read = '1') then + if (i_avmm_saddress(15 downto 0) = "0000000000000000") then + o_avmm_sreaddata(ireg_data_width - 1 downto 0) <= reg_ctrlstatus0q; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000001") then + o_avmm_sreaddata(channel_address_width - 1 downto 0) <= reg_chaddress0q; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000010") then + o_avmm_sreaddata(ireg_wdaddr_width - 1 downto 0) <= reg_wdaddress0q; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000011") then + o_avmm_sreaddata <= reg_data0q; + else + o_avmm_sreaddata <= (others => '0'); + end if; + else + o_avmm_sreaddata <= (others => '0'); + end if; + end process; + invalid_channel_address <= to_stdlogic((i_remap_address = "111111111111")); + invalid_word_address <= to_stdlogic((reg_wdaddress0q > "10")); + + + xhdl1 <= '0' when ((i_avmm_swritedata(14)) = '1') else + reg_ctrlstatus0q(14); + xhdl2 <= '0' when ((i_avmm_swritedata(13)) = '1') else + reg_ctrlstatus0q(13); + process (reg_chaddress0q, reg_data0q, reg_ctrlstatus0q, reg_wdaddress0q, i, dprio_reg, busy_counter, dprio_reg0q, reg_write, i_avmm_saddress, i_avmm_swritedata, invalid_channel_address, invalid_word_address) + begin + reg_chaddress <= reg_chaddress0q; + reg_data <= reg_data0q; + reg_ctrlstatus <= reg_ctrlstatus0q; + reg_wdaddress <= reg_wdaddress0q; + for i in 0 to ((2 ** channel_address_width)) - 1 loop + dprio_reg0q(i) <= dprio_reg(i); + end loop; + if (busy_counter = "000001") then + reg_ctrlstatus(15) <= '0'; + reg_ctrlstatus(0) <= '0'; + if ((reg_ctrlstatus0q(1)) = '1') then + if (reg_wdaddress0q = "00") then + reg_data(2 downto 0) <= dprio_reg0q(to_integer(reg_chaddress0q))(2 downto 0); + reg_data(15 downto 3) <= "0000000000000"; + elsif (reg_wdaddress0q = "01") then + reg_data(3 downto 0) <= dprio_reg0q(to_integer(reg_chaddress0q))(6 downto 3); + reg_data(15 downto 4) <= "000000000000"; + elsif (reg_wdaddress0q = "10") then + reg_data(5 downto 0) <= dprio_reg0q(to_integer(reg_chaddress0q))(12 downto 7); + reg_data(15 downto 6) <= "0000000000"; + end if; + end if; + end if; + if (reg_write = '1') then + if (i_avmm_saddress(15 downto 0) = "0000000000000000") then + reg_ctrlstatus(1) <= i_avmm_swritedata(1); + if ((i_avmm_swritedata(0)) = '1') then + if ((invalid_channel_address = '1') or (invalid_word_address = '1')) then + reg_ctrlstatus(15) <= '0'; + reg_ctrlstatus(14) <= invalid_word_address; + reg_ctrlstatus(13) <= invalid_channel_address; + else + if ((not(i_avmm_swritedata(1))) = '1') then + if (reg_wdaddress0q = "00") then + dprio_reg(to_integer(reg_chaddress0q))(2 downto 0) <= (reg_data0q(2 downto 0)); + elsif (reg_wdaddress0q = "01") then + dprio_reg(to_integer(reg_chaddress0q))(6 downto 3) <= (reg_data0q(3 downto 0)); + elsif (reg_wdaddress0q = "10") then + dprio_reg(to_integer(reg_chaddress0q))(12 downto 7) <= (reg_data0q(5 downto 0)); + end if; + end if; + reg_ctrlstatus(0) <= '1'; + reg_ctrlstatus(15) <= '1'; + reg_ctrlstatus(14) <= '0'; + reg_ctrlstatus(13) <= '0'; + end if; + else + reg_ctrlstatus(15) <= '0'; + reg_ctrlstatus(14) <= xhdl1; + reg_ctrlstatus(13) <= xhdl2; + end if; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000001") then + if (channel_address_width < 2) then + reg_chaddress <= i_avmm_swritedata(0 downto 0); + else + reg_chaddress <= i_avmm_swritedata(channel_address_width - 1 downto 0); + end if; + elsif (i_avmm_saddress(15 downto 0) = "0000000000000010") then + reg_wdaddress <= i_avmm_swritedata(ireg_wdaddr_width - 1 downto 0); + elsif (i_avmm_saddress(15 downto 0) = "0000000000000011") then + reg_data <= i_avmm_swritedata(ireg_data_width - 1 downto 0); + end if; + end if; + end process; + + +end trans; + + + +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +package SLD_NODE is + + constant CLK_PERIOD : time := 100 NS; -- the clock period of the system (10Mhz) + + constant NUM_SELECTION_BITS : natural := 4; + -- the number of selection bits + 3 to be added to the IR register + -- in the dummy hub. 3 is the width of + -- hub instructions + constant PARAM_ERROR : string := "Invalid parameter specification : SLD_NODE_SIM_ACTION"; + -- error message for invalid parameters + + constant HEXCON_ERROR : string := "Invalid hexadecimal character : SLD_NODE_SIM_ACTION"; + -- error message for invalid + -- hexadecimal parameters + + constant TYPE_ERROR : string := "Invalid Scan type specified : SLD_NODE_SIM_ACTION"; + -- error message for an invalid scan type + + constant FIRST_TYPE_ERROR : string := "First scan should always be an IR scan. : SLD_NODE_SIM_ACTION"; + -- error message for an invalid first scan type + + constant LENGTH_ERROR : string := "IR length specified is less than SLD_NODE_IR_WIDTH : SLD_NODE_SIM_ACTION"; + -- error message for an invalid ir length + + constant ZERO_LENGTH_ERROR : string := "Zero is not a valid length parameter : SLD_NODE_SIM_ACTION"; + -- error message when zero length is given + + constant V_IR_SCAN_TYPE : std_logic_vector(3 downto 0) := "0001"; + -- ir type signal + constant V_DR_SCAN_TYPE : std_logic_vector(3 downto 0) := "0010"; + -- dr type signal + constant JTAG_USR1_INSTR : std_logic_vector(9 downto 0) := "0000001110"; + -- the usr1 instruction for jtag controller + + -- purpose: handles errors based on the severity level. Can stop simulation and will also display message + procedure message ( + mess : string; -- string to be displayed + sev : severity_level); -- severity level of message + + procedure hexmessage ( + mess : string; -- string to be displayed + value : character; -- string to be displayed + sev : severity_level); + + -- purpose: converts a character to a 4 bit value. All characters beyond F generate a warning and convert to + -- zero + function hexToBits ( + constant hexValue : character) -- the charcater to be decoded + return unsigned; + + -- purpose: converts a character to an exact number of bits value. All characters beyond 7 generate a warning and convert + -- to zero + function hexToExactBits ( + constant hexValue : character; -- the character to be converted + constant num_bits : natural) -- the number of bits to return + return unsigned; + + -- purpose: move JTAG tap into a dr shift state + procedure goto_dr_shift_state ( + signal tck : out std_logic; -- tck signal + signal tms : out std_logic); -- tms signal + + -- purpose: shifts usr0 into the jtag tap controller. Assumes tap is in update or rti state. + procedure jtag_ir_usr0 ( + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic); -- tdi signal + + -- purpose: shifts the usr1 instruction into the jtag tap controller. Works if jtag is in an update state or rti state + procedure jtag_ir_usr1 ( + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic); -- tdi signal + + + -- purpose: sends a HUB_FORCE_IR_CAPTURE instruction to the hub + procedure send_force_ir_capture ( + constant ir_width : in integer; -- ir_width - 4 + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic); -- tdi signal + + -- purpose: a dr scan with the passed in value. Assumes we are in udr/uir state + procedure dr_scan ( + constant length : in natural; -- length of the value + constant idx_lsb : in natural; -- the index to start reading values from + constant idx_msb : in natural; -- the index to stop reading at + constant value : in std_logic_vector; -- the value to be shifted + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic); -- tdi signal + + -- purpose: virtual dr scan + procedure v_dr_scan ( + constant length : in natural; -- length of the value + constant idx_lsb : in natural; -- the index to start reading values from + constant idx_msb : in natural; -- the index to stop reading at + constant value : in std_logic_vector; -- the value to be shifted + signal jtag_usr1 : in std_logic; -- high if jtag is in usr1 state + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic); -- tdi signal + + -- purpose: virtual ir scan + procedure v_ir_scan ( + constant length : in natural; -- length of bit stream + constant idx_lsb : in natural; -- the index to start reading values from + constant idx_msb : in natural; -- the index to stop reading at + constant value : in std_logic_vector; -- the value to be shifted out + constant ir_width : in integer; -- sld_node_ir_width - 4 + signal jtag_usr1 : in std_logic; -- high if jtag is in usr1 state + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic); -- tdi signal + + +end SLD_NODE; + +package body SLD_NODE is + + -- purpose: handles errors based on the severity level. Can stop simulation and will also display message + procedure message ( + mess : string; -- string to be displayed + sev : severity_level) is -- severity level of message + begin -- message + assert (FALSE) report mess severity sev; + end message; + + -- purpose: handles errors based on the severity level. Can stop simulation and will also display message + procedure hexmessage ( + mess : string; -- string to be displayed + value : character; -- string to be displayed + sev : severity_level) is -- severity level of message + begin -- message + assert (FALSE) report mess & " Character is : " & value severity sev; + end hexmessage; + + + -- purpose: converts a character to a 4 bit value. All characters beyond F generate a warning and convert to + -- zero + function hexToBits ( + constant hexValue : character) -- the character to be converted + return unsigned is + variable result : unsigned(3 downto 0) := (others => '0'); + -- variable to hold decoded bits + begin -- hexToBits + case hexValue is + when '0' => result := "0000"; + when '1' => result := "0001"; + when '2' => result := "0010"; + when '3' => result := "0011"; + when '4' => result := "0100"; + when '5' => result := "0101"; + when '6' => result := "0110"; + when '7' => result := "0111"; + when '8' => result := "1000"; + when '9' => result := "1001"; + when 'A' => result := "1010"; + when 'a' => result := "1010"; + when 'B' => result := "1011"; + when 'b' => result := "1011"; + when 'C' => result := "1100"; + when 'c' => result := "1100"; + when 'D' => result := "1101"; + when 'd' => result := "1101"; + when 'E' => result := "1110"; + when 'e' => result := "1110"; + when 'F' => result := "1111"; + when 'f' => result := "1111"; + when others => + hexmessage(hexcon_error, hexValue, WARNING); + result := "0000"; + end case; + return result; + end hexToBits; + + -- purpose: converts a character to an exact number of bits value. All characters beyond 7 generate a warning and convert + -- to zero + function hexToExactBits ( + constant hexValue : character; -- the character to be converted + constant num_bits : natural) -- the number of bits to return + return unsigned is + variable result : unsigned(3 downto 0) := (others => '0'); + -- variable to hold bits + begin -- hexToExactBits + result := hexToBits(hexValue); + return result(num_bits - 1 downto 0); + end hexToExactBits; + + -- purpose: move JTAG tap into a dr shift state + procedure goto_dr_shift_state ( + signal tck : out std_logic; -- tck signal + signal tms : out std_logic) is -- tms signal + begin -- goto_dr_shift_state + -- get into drs state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into cdr state + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into sdr state + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end goto_dr_shift_state; + + -- purpose: move jtag from dr/ir shift state to ir/dr update state + procedure goto_update_state ( + signal tck : out std_logic; -- tck signal + signal tms : out std_logic) is -- tms signal + begin -- goto_update_state + -- get into e1(i/d)r state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into u(i/d)r state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end goto_update_state; + + -- purpose: shifts the usr1 instruction into the jtag tap controller. Works if jtag is in an update state or rti state + procedure jtag_ir_usr1 ( + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic) is -- tdi signal + begin -- jtag_to_usr1 + -- get into drs state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into irs state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into cir state + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into sir state + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- shift in data i.e usr1 instruction + -- usr1 = 0x0E = 0b00 0000 1110 + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '1'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '1'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '1'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- done with 1110 + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- done with 0000 + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- done with 00 + -- now in e1ir state + -- get into uir state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end jtag_ir_usr1; + + -- purpose: shifts usr0 into the jtag tap controller. Assumes tap is in update or rti state. + procedure jtag_ir_usr0 ( + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic) is -- tdi signal + begin -- jtag_ir_usr0 + -- get into drs state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into irs state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into cir state + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into sir state + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- shift in data i.e usr0 instruction + -- usr1 = 0x0E = 0b00 0000 1100 + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '1'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '1'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- done with 1100 + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- done with 0000 + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- done with 00 + -- get into e1ir state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- get into uir state + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end jtag_ir_usr0; + + -- purpose: sends a HUB_FORCE_IR_CAPTURE instruction to the hub + procedure send_force_ir_capture ( + constant ir_width : in integer; -- ir_width - 4 + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic) is -- tdi signal + begin -- send_force_ir_capture + goto_dr_shift_state(tck, tms); + -- shift in the instruction + tdi <= '1'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '1'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- done with 011 + -- fill up for ir width + for j in 0 to ir_width - 1 loop + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end loop; -- j + -- one select bit + tdi <= '0'; + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + goto_update_state(tck, tms); + end send_force_ir_capture; + + -- purpose: a dr scan with the passed in value. Assumes we are in udr/uir state + procedure dr_scan ( + constant length : in natural; -- length of the value + constant idx_lsb : in natural; -- the index to start reading values from + constant idx_msb : in natural; -- the index to stop reading at + constant value : in std_logic_vector; -- the value to be shifted + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic) is -- tdi signal + begin -- dr_scan + goto_dr_shift_state(tck, tms); + for i in idx_lsb to idx_msb - 1 loop + tms <= '0'; + tdi <= value(i); + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end loop; -- i + -- check if we need to pad with zeros + if ((idx_msb - idx_lsb + 1) < length ) then + -- clock last value bit + tdi <= value(idx_msb); + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + -- pad with zeros + for j in idx_msb - idx_lsb + 1 to length - 2 loop + tms <= '0'; + tdi <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end loop; -- j + tdi <= '0'; + else + tdi <= value(idx_msb); + end if; + -- last bit is clocked together with state transition + goto_update_state(tck, tms); + end dr_scan; + + -- purpose: virtual dr scan + procedure v_dr_scan ( + constant length : in natural; -- length of the value + constant idx_lsb : in natural; -- the index to start reading values from + constant idx_msb : in natural; -- the index to stop reading at + constant value : in std_logic_vector; -- the value to be shifted + signal jtag_usr1 : in std_logic; -- high if jtag is in usr1 state + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic) is -- tdi signal + begin -- v_dr_scan + if (jtag_usr1 = '1') then + -- shift in usr0 instruction + jtag_ir_usr0(tck, tms, tdi); + end if; + -- shift in the dr value + dr_scan(length, idx_lsb, idx_msb, value, tck, tms, tdi); + end v_dr_scan; + + -- purpose: virtual ir scan + procedure v_ir_scan ( + constant length : in natural; -- length of bit stream this is ignored + constant idx_lsb : in natural; -- the index to start reading values from + constant idx_msb : in natural; -- the index to stop reading at + constant value : in std_logic_vector; -- the value to be shifted out + constant ir_width : in integer; -- sld_node_ir_width - 4 + signal jtag_usr1 : in std_logic; -- high if jtag is in usr1 state + signal tck : out std_logic; -- tck signal + signal tms : out std_logic; -- tms signal + signal tdi : out std_logic) is -- tdi signal + begin -- v_ir_scan + if (jtag_usr1 = '0' ) then + -- shift in usr1 instruction + jtag_ir_usr1(tck, tms, tdi); + end if; + -- send capture_ir instructions + send_force_ir_capture(ir_width, tck, tms, tdi); + -- shift in the ir value + goto_dr_shift_state(tck, tms); + for i in idx_lsb to idx_msb loop + tms <= '0'; + tdi <= value(i); + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end loop; -- i + -- pad with zeros if necessary + for j in idx_msb - idx_lsb + 1 to ir_width + 3 loop + tms <= '0'; + tdi <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end loop; -- j + -- last bit is clocked together with state transition + -- last bit is selection bit. For IR scans this is always 1 implying + -- node as opposed to hub + tdi <= '1'; + goto_update_state(tck, tms); + end v_ir_scan; + +end SLD_NODE; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +use work.sld_node.all; + +------------------------------------------------------------------------------- +-- Entity Name : signal_gen +-- +-- Description : Simulates customizable actions on a JTAG input +-- +-- Limitation : See file limitations above +-- +-- Results Expected : +-- +-- +------------------------------------------------------------------------------- + +entity signal_gen is + + generic ( + sld_node_ir_width : integer; -- ir width for this instance + sld_node_n_scan : natural; -- the number of scans to be executed + sld_node_total_length : natural; -- the total length of all scan values + sld_node_sim_action : string); -- the actions to be simulated. + port ( + tck : out std_logic; -- jtag clock + tms : out std_logic; -- tms signal for jtag + tdi : out std_logic; -- tdi signal to the jtag + jtag_usr1 : in std_logic; -- high when jtag is in usr1 state + tdo : in std_logic); -- tdo signal from jtag +end signal_gen; + +architecture simModel of signal_gen is + +------------------------------------------------------------------------------- + + type instr is record -- represents a single instruction + scan_time : time; + -- the time to wait before executing this instruction + scan_type : std_logic_vector(3 downto 0); + -- the type of scan this is + length : unsigned(31 downto 0); + -- the bit length of the value to be shifted + idx_lsb : natural; -- the starting index of value + idx_msb : natural; -- the starting index of value + end record; + +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- array for instructions + type scansArray is array (sld_node_n_scan - 1 downto 0) of instr; + -- the scansArray +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Parsed string data structure + type decodedScans is record + -- decodedScans for this instance of the model + scans : scansArray; -- the array of instructions + values : std_logic_vector(sld_node_total_length - 1 downto 0); + -- the values for all scans + end record; +------------------------------------------------------------------------------- + -- purpose: takes in a string and returns the decoded scans for use by the model + function decode ( + constant actions : string) -- the string to be decoded + return decodedScans is + + type mStates is (STARTSTATE, TIMESTATE, TYPESTATE, LENGTHSTATE, VALUESTATE); + -- the states of the parsing machine + + variable decScans : decodedScans; + -- the variable to store the decoded scans + variable decValues : std_logic_vector(sld_node_total_length - 1 downto 0); + -- variable to store decoded values + variable decScanArray : scansArray; -- variable to store decoded scans + + variable cState : mStates := STARTSTATE; -- the current state variable + + variable cTime : unsigned(31 downto 0) := (others => '0'); + -- the current Time being decoded + + variable cIdx_lsb : natural := 0; -- the current lsb idx for the value array + variable cIdx_msb : natural := 0; -- the current msb idx for the value array + + variable cType : std_logic_vector(3 downto 0) := (others => '0'); + -- the current type + variable scanArrIdx : natural range 0 to sld_node_n_scan := 0; -- the index to the scan array + -- scanArrIdx is one more than needed to allow for the loop not to crash, since we + -- increment index at the end of the loop + variable cLength : unsigned(31 downto 0) := (others => '0'); + -- the current length value + begin -- decode + decValues := (others =>'0'); -- initialize all bits to zero + for i in 2 to actions'length - 1 loop + case cState is + when STARTSTATE => + if (actions(i) = '(') then + cState := TIMESTATE; + end if; + when TIMESTATE => + if (actions(i) = ',') then + cState := TYPESTATE; + else + cTime(31 downto 4) := cTime(27 downto 0); + cTime(3 downto 0) := hexToBits(actions(i)); + end if; + when TYPESTATE => + if (actions(i) = ',') then + cState := VALUESTATE; + else + cType := std_logic_vector(hexToBits(actions(i))); + end if; + when VALUESTATE => + if (actions(i) = ',') then + cState := LENGTHSTATE; + elsif ((sld_node_total_length - cIdx_lsb) < 4) then + decValues(sld_node_total_length - 1 downto cIdx_lsb) := std_logic_vector(hexToExactBits(actions(i),sld_node_total_length - cIdx_lsb)); + cIdx_msb := cIdx_msb + sld_node_total_length - cIdx_lsb; + else + -- the line below shifts the previous character + decValues(sld_node_total_length - 1 downto cIdx_lsb + 4) := decValues(sld_node_total_length - 5 downto cIdx_lsb); + decValues(cIdx_lsb + 3 downto cIdx_lsb) := std_logic_vector(hexToBits(actions(i))); + cIdx_msb := cIdx_msb + 4; + end if; + when LENGTHSTATE => + if (actions(i) = ')') then + -- zero is not a valid length + if (conv_integer(cLength) = 0) then + message(ZERO_LENGTH_ERROR,FAILURE); + end if; + decScanArray(scanArrIdx).scan_time := CLK_PERIOD * 10000 * conv_integer(cTime); + decScanArray(scanArrIdx).scan_type := cType; + decScanArray(scanArrIdx).length := cLength; + decScanArray(scanArrIdx).idx_lsb := cIdx_lsb; + -- error checking for cases when actual bit length > + -- specified length i.e need for truncation + if (cIdx_lsb + conv_integer(cLength) < cIdx_msb) then + cIdx_msb := cIdx_lsb + conv_integer(cLength); + end if; + decScanArray(scanArrIdx).idx_msb := cIdx_msb - 1; + cTime := (others => '0'); + cType := (others => '0'); + cLength := (others => '0'); + cIdx_lsb := cIdx_msb; + scanArrIdx := scanArrIdx + 1 ; + cState := STARTSTATE; + else + cLength(31 downto 4) := cLength(27 downto 0); + cLength(3 downto 0) := hexToBits(actions(i)); + end if; + when others => null; + end case; + end loop; -- i + decScans.scans := decScanArray; + decScans.values := decValues; + return decScans; + end decode; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + -- Resets the JTAP controller. + procedure reset_jtag ( + constant length : in unsigned(31 downto 0); -- the ir-calue to be shifted + constant idx : in natural; + -- the index to start reading value from + constant values : in std_logic_vector(sld_node_total_length - 1 downto 0); + -- the values to be shifted out + signal tck : out std_logic; -- the tck signal + signal tms : out std_logic; -- the tms signal + signal tdi : out std_logic) is -- the tdi signal + begin -- ir_scan + -- get into tlr state + for i in 0 to 5 loop + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end loop; -- i + -- get into rti state + tms <= '0'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + jtag_ir_usr1(tck,tms,tdi); + end reset_jtag; + +------------------------------------------------------------------------------- + + signal myScans : decodedScans; -- the decoded scan + + +begin -- simModel + -- purpose: Resets jtag and then iterates through instructions and performs + -- actions. + -- type : combinational + -- inputs : + -- outputs: tck,tdi,tms + simulate : process + begin -- process simulate + tck <= '1'; + tdi <= '0'; + tms <= '0'; + myScans <= decode(sld_node_sim_action); + wait for CLK_PERIOD; + reset_jtag(myScans.scans(0).length, myScans.scans(0).idx_lsb,myScans.values,tck,tms,tdi); + -- first instruction needs to be an IR intsruction. + if (myScans.scans(0).scan_type /= V_IR_SCAN_TYPE) then + message(FIRST_TYPE_ERROR,FAILURE); + end if; + for l in 0 to sld_node_n_scan - 1 loop + wait for myScans.scans(l).scan_time; + if (myScans.scans(l).scan_type = V_IR_SCAN_TYPE) then + v_ir_scan(conv_integer(myScans.scans(l).length), + myScans.scans(l).idx_lsb, myScans.scans(l).idx_msb, myScans.values, + sld_node_ir_width - 4, + jtag_usr1, tck, tms, tdi); + -- do error checking for when length is not equal to SLD_NODE_IR_WIDTH + if (conv_integer(myScans.scans(l).length) /= sld_node_ir_width) then + message(LENGTH_ERROR,WARNING); + end if; + elsif (myScans.scans(l).scan_type = V_DR_SCAN_TYPE) then + v_dr_scan(conv_integer(myScans.scans(l).length), + myScans.scans(l).idx_lsb, myScans.scans(l).idx_msb, myScans.values, + jtag_usr1, tck, tms, tdi); + else + message(TYPE_ERROR,ERROR); + end if; + end loop; -- l + -- get into tlr state + for i in 0 to 5 loop + tms <= '1'; + tck <= '0', '1' after clk_period/2; + wait for clk_period; + end loop; -- i + wait; + end process simulate; + + +end simModel; + +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.sld_node.all; + +------------------------------------------------------------------------------- +-- Entity Name : jtag_tap_controller +-- +-- Description : Behavioral model of JTAg tap controller with state signals +-- +-- Limitation : Can only decode USER1 and USER0 instructions +-- +-- Results Expected : +-- +-- +------------------------------------------------------------------------------- + +entity jtag_tap_controller is + generic ( + ir_register_width : integer); -- the width of the shift register + + port ( + tck : in std_logic; -- tck signal from signal_gen + tms : in std_logic; -- tms signal from signal_gen + tdi : in std_logic; -- tdi signal from signal_gen + jtag_tdo : in std_logic; -- tdo signal from hub + tdo : out std_logic; -- tdo signal to signal_gen + jtag_tck : out std_logic; -- tck signal from jtag + jtag_tms : out std_logic; -- tms signal from jtag + jtag_tdi : out std_logic; -- tdi signal from jtag + jtag_state_tlr : out std_logic; -- tlr state + jtag_state_rti : out std_logic; -- rti state + jtag_state_drs : out std_logic; -- select dr scan state + jtag_state_cdr : out std_logic; -- capture dr state + jtag_state_sdr : out std_logic; -- shift dr state + jtag_state_e1dr : out std_logic; -- exit1 dr state + jtag_state_pdr : out std_logic; -- pause dr sart + jtag_state_e2dr : out std_logic; -- exit2 dr state + jtag_state_udr : out std_logic; -- update dr state + jtag_state_irs : out std_logic; -- select ir scan state + jtag_state_cir : out std_logic; -- capture ir state + jtag_state_sir : out std_logic; -- shift ir state + jtag_state_e1ir : out std_logic; -- exit1 ir state + jtag_state_pir : out std_logic; -- pause ir state + jtag_state_e2ir : out std_logic; -- exit2 ir state + jtag_state_uir : out std_logic; -- update ir state + jtag_usr1 : out std_logic); -- jtag has usr1 instruction + +end jtag_tap_controller; + + +architecture FSM of jtag_tap_controller is + + type tap_states is (TLR_ST, RTI_ST, DRS_ST, CDR_ST, SDR_ST, E1DR_ST, + PDR_ST, E2DR_ST, UDR_ST, IRS_ST, CIR_ST, SIR_ST, + E1IR_ST, PIR_ST, E2IR_ST, UIR_ST); + -- the tap states + + signal nState : tap_states; -- the next state signal + signal cState : tap_states; -- the current state signal + signal ir_srl : std_logic_vector(ir_register_width -1 downto 0); + -- the shift register for the controller + signal ir_srl_hold : std_logic_vector(ir_register_width -1 downto 0); + -- the hold register for the controller + signal jtag_usr1_c : std_logic; -- combinational usr1 signal + signal jtag_usr1_r : std_logic; -- registered usr1 signal + signal jtag_e1ir_i : std_logic; + -- internal signal to tell enable hold part of ir shift register + signal tdo_i : std_logic; -- internal signal for tdo + signal tdo_i_c : std_logic; + -- internal combinational signal for tdo + signal jtag_reset_i : std_logic; + -- internal reset signal that goes high when in TLR state +begin -- FSM + + -- purpose: state transitions for the FSM + -- type : combinational + -- inputs : cState, tms + -- outputs: nState + stateTrans: process (cState, tms, jtag_usr1_r, ir_srl_hold) + begin -- process stateTrans + nState <= cState; + jtag_e1ir_i <= '0'; + jtag_state_tlr <= '0'; + jtag_state_rti <= '0'; + jtag_state_drs <= '0'; + jtag_state_cdr <= '0'; + jtag_state_sdr <= '0'; + jtag_state_e1dr <= '0'; + jtag_state_pdr <= '0'; + jtag_state_e2dr <= '0'; + jtag_state_udr <= '0'; + jtag_state_irs <= '0'; + jtag_state_cir <= '0'; + jtag_state_sir <= '0'; + jtag_state_e1ir <= '0'; + jtag_state_pir <= '0'; + jtag_state_e2ir <= '0'; + jtag_state_uir <= '0'; + jtag_reset_i <= '0'; + jtag_usr1_c <= jtag_usr1_r; + case cState is + when TLR_ST => + if (tms = '0') then + nState <= RTI_ST; + jtag_reset_i <= '0'; + else + jtag_reset_i <= '1'; + end if; + jtag_state_tlr <= '1'; + jtag_usr1_c <= '0'; + when RTI_ST => + if (tms = '1') then + nState <= DRS_ST; + end if; + jtag_state_rti <= '1'; + when DRS_ST => + if (tms = '1') then + nState <= IRS_ST; + else + nState <= CDR_ST; + end if; + jtag_state_drs <= '1'; + when CDR_ST => + if (tms = '1') then + nState <= E1DR_ST; + else + nState <= SDR_ST; + end if; + jtag_state_cdr <= '1'; + when SDR_ST => + if (tms = '1') then + nState <= E1DR_ST; + end if; + jtag_state_sdr <= '1'; + when E1DR_ST => + if (tms = '1') then + nState <= UDR_ST; + else + nState <= PDR_ST; + end if; + jtag_state_e1dr <= '1'; + when PDR_ST => + if (tms = '1') then + nState <= E2DR_ST; + end if; + jtag_state_pdr <= '1'; + when E2DR_ST => + if (tms = '1') then + nState <= UDR_ST; + else + nState <= SDR_ST; + end if; + jtag_state_e2dr <= '1'; + when UDR_ST => + if (tms = '1') then + nState <= DRS_ST; + else + nState <= RTI_ST; + end if; + jtag_state_udr <= '1'; + when IRS_ST => + if (tms = '1') then + nState <= TLR_ST; + else + nState <= CIR_ST; + end if; + jtag_state_irs <= '1'; + when CIR_ST => + if (tms = '1') then + nState <= E1IR_ST; + else + nState <= SIR_ST; + end if; + jtag_state_cir <= '1'; + when SIR_ST => + if (tms = '1') then + nState <= E1IR_ST; + end if; + jtag_state_sir <= '1'; + when E1IR_ST => + if (tms = '1') then + nState <= UIR_ST; + else + nState <= PIR_ST; + end if; + jtag_state_e1ir <= '1'; + jtag_e1ir_i <= '1'; + when PIR_ST => + if (tms = '1') then + nState <= E2IR_ST; + end if; + jtag_state_pir <= '1'; + when E2IR_ST => + if (tms = '1') then + nState <= UIR_ST; + else + nState <= SIR_ST; + end if; + jtag_state_e2ir <= '1'; + when UIR_ST => + if (tms = '1') then + nState <= DRS_ST; + else + nState <= RTI_ST; + end if; + if (ir_srl_hold = JTAG_USR1_INSTR) then + jtag_usr1_c <= '1'; + else + jtag_usr1_c <= '0'; + end if; + jtag_state_uir <= '1'; + when others => null; + end case; + end process stateTrans; + + -- purpose: Regsiter for state machine and shift register + -- type : sequential + -- inputs : tck, jtag_reset_i + -- outputs: cState, sr + stateReg: process (tck, jtag_reset_i) + begin -- process stateReg + if jtag_reset_i = '1' then -- asynchronous reset (active high) + cState <= TLR_ST; + ir_srl <= (others =>'0'); + jtag_usr1_r <= '0'; + tdo_i <= '0'; + tdo_i_c <= '0'; + elsif tck'event and tck = '1' then -- rising clock edge + cState <= nState; + jtag_usr1_r <= jtag_usr1_c; + if (cState = CIR_ST) then + tdo_i_c <= '0'; -- so that we can generate 010101... + -- during SIR + elsif (cState = SIR_ST) then + ir_srl(ir_register_width - 2 downto 0) <= ir_srl(ir_register_width - 1 downto 1); + ir_srl(ir_register_width - 1) <= tdi; + tdo_i_c <= not(tdo_i_c); + tdo_i <= tdo_i_c; + else + tdo_i <= jtag_tdo; + end if; + end if; + end process stateReg; + jtag_usr1 <= jtag_usr1_r; + tdo <= tdo_i; + +-- pipe through signals + jtag_tck <= tck; + jtag_tdi <= tdi; + jtag_tms <= tms; + +-- purpose: hold register of shift register +-- type : sequential +-- inputs : tck, jtag_reset_i +-- outputs: ir_srl_hold + holdReg: process (tck, jtag_reset_i) + begin -- process holdReg + if jtag_reset_i = '1' then -- asynchronous reset (active high) + ir_srl_hold <= (others => '0'); + elsif tck'event and tck = '0' then -- falling clock edge + if (jtag_e1ir_i = '1') then + ir_srl_hold <= ir_srl; + end if; + end if; + end process holdReg; +end FSM; +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.sld_node.all; + +------------------------------------------------------------------------------- +-- Entity Name : dummy_hub +-- +-- Description : Acts as node and mux between the tap controller and +-- user design. Generates hub signals +-- +-- Limitation : Assumes only one node. Ignores user input on tdo and ir_out. +-- +-- Results Expected : +-- +-- +------------------------------------------------------------------------------ + +entity dummy_hub is + + generic ( + sld_node_ir_width : integer); -- the width of the ir registers + + port ( + jtag_tck : in std_logic; -- tck signal from tap controller + jtag_tdi : in std_logic; -- tdi signal from tap controller + jtag_tms : in std_logic; -- tms signal from tap controller + jtag_usr1 : in std_logic; -- usr1 signal from tap controller + jtag_state_tlr : in std_logic; -- tlr state signal from tap controller + jtag_state_rti : in std_logic; -- rti state signal from tap controller + jtag_state_drs : in std_logic; -- drs state signal from tap controller + jtag_state_cdr : in std_logic; -- cdr state signal from tap controller + jtag_state_sdr : in std_logic; -- sdr state signal from tap controller + jtag_state_e1dr : in std_logic; -- e1dr state signal from tap controller + jtag_state_pdr : in std_logic; -- pdr state signal from tap controller + jtag_state_e2dr : in std_logic; -- esdr state signal from tap controller + jtag_state_udr : in std_logic; -- udr state signal from tap controller + jtag_state_irs : in std_logic; -- irs state signal from tap controller + jtag_state_cir : in std_logic; -- cir state signals from tap controller + jtag_state_sir : in std_logic; -- sir state signal from tap controller + jtag_state_e1ir : in std_logic; -- e1ir state signal from tap controller + jtag_state_pir : in std_logic; -- pir state signals from tap controller + jtag_state_e2ir : in std_logic; -- e2ir state signal from tap controller + jtag_state_uir : in std_logic; -- uir state signal from tap controller + dummy_tdo : in std_logic; -- tdo signal from world + virtual_ir_out : in std_logic_vector(sld_node_ir_width - 1 downto 0); + -- captures parallel input from + -- user design + jtag_tdo : out std_logic; -- tdo signal to tap controller + dummy_tck : out std_logic; -- tck signal to world + dummy_tdi : out std_logic; -- tdi signal to world + dummy_tms : out std_logic; -- tms signal to world + dummy_state_tlr : out std_logic; -- tlr state signal to world + dummy_state_rti : out std_logic; -- rti state signal to world + dummy_state_drs : out std_logic; -- drs state signal to world + dummy_state_cdr : out std_logic; -- cdr state signal to world + dummy_state_sdr : out std_logic; -- sdr state signal to world + dummy_state_e1dr : out std_logic; -- e1dr state signal to the world + dummy_state_pdr : out std_logic; -- pdr state signal to world + dummy_state_e2dr : out std_logic; -- e2dr state signal to world + dummy_state_udr : out std_logic; -- udr state signal to world + dummy_state_irs : out std_logic; -- irs state signal to world + dummy_state_cir : out std_logic; -- cir state signal to world + dummy_state_sir : out std_logic; -- sir state signal to world + dummy_state_e1ir : out std_logic; -- e1ir state signal to world + dummy_state_pir : out std_logic; -- pir state signal to world + dummy_state_e2ir : out std_logic; -- e2ir state signal to world + dummy_state_uir : out std_logic; -- uir state signal to world + virtual_state_cdr : out std_logic; -- virtual cdr state signal + virtual_state_sdr : out std_logic; -- virtual sdr state signal + virtual_state_e1dr : out std_logic; -- virtual e1dr state signal + virtual_state_pdr : out std_logic; -- virtula pdr state signal + virtual_state_e2dr : out std_logic; -- virtual e2dr state signal + virtual_state_udr : out std_logic; -- virtual udr state signal + virtual_state_cir : out std_logic; -- virtual cir state signal + virtual_state_uir : out std_logic; -- virtual uir state signal + virtual_ir_in : out std_logic_vector(sld_node_ir_width - 1 downto 0)); + -- parallel output to user design +end dummy_hub; + +architecture behavior of dummy_hub is + + constant SLD_NODE_IR_WIDTH_i : integer := sld_node_ir_width + NUM_SELECTION_BITS; + -- the internal ir_width representation + signal ir_srl : std_logic_vector(SLD_NODE_IR_WIDTH_i - 1 downto 0); + -- ir shift register + signal virtual_ir_in_i : std_logic_vector(SLD_NODE_IR_WIDTH_i - 1 downto 0); + -- internal hold portion of ir shift register + signal capture_ir : std_logic; -- signals a force_ir_capture +begin -- behavior + + -- purpose: the register for the fsm and other registered data + -- type : sequential + -- inputs : tck, trst + -- outputs: + stateReg : process (jtag_tck,jtag_state_tlr) + begin -- process stateReg + if jtag_state_tlr = '1' then -- asynchronous reset (active high) + ir_srl <= (others => '0'); + jtag_tdo <= '0'; + dummy_tdi <= '0'; + capture_ir <= '0'; + virtual_ir_in <= (others => '0'); + elsif jtag_tck'event and jtag_tck = '1' then -- rising clock edge + virtual_ir_in <= virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 2 downto NUM_SELECTION_BITS - 1); + -- should check for 011 instruction + -- but we know that it is the only instruction ever sent to the + -- hub. So all we have to do is check the selection bit, udr and + -- usr1 state + if (jtag_state_udr = '1' and ir_srl(SLD_NODE_IR_WIDTH_i - 1) = '0') then + capture_ir <= jtag_usr1; + elsif (jtag_state_e1dr = '1') then + capture_ir <= '0'; + end if; + + if (jtag_usr1 = '1' and jtag_state_sdr = '1') then + + ir_srl(SLD_NODE_IR_WIDTH_i - 2 downto 0) <= ir_srl(SLD_NODE_IR_WIDTH_i - 1 downto 1); + ir_srl(SLD_NODE_IR_WIDTH_i - 1) <= jtag_tdi; + jtag_tdo <= ir_srl(0); + + elsif (capture_ir = '1' and jtag_state_cdr = '1') then + + ir_srl(SLD_NODE_IR_WIDTH_i - 2 downto NUM_SELECTION_BITS - 1) <= virtual_ir_out; + + elsif (capture_ir = '1' and jtag_state_sdr = '1') then + + ir_srl(SLD_NODE_IR_WIDTH_i - 2 downto 0) <= ir_srl(SLD_NODE_IR_WIDTH_i - 1 downto 1); + ir_srl(SLD_NODE_IR_WIDTH_i - 1) <= jtag_tdi; + jtag_tdo <= ir_srl(0); + + elsif (jtag_state_sdr = '1') then + + dummy_tdi <= jtag_tdi; + jtag_tdo <= dummy_tdo; + + end if; + + end if; + end process stateReg; + + -- pipe through signals + dummy_state_tlr <= jtag_state_tlr; + dummy_state_rti <= jtag_state_rti; + dummy_state_drs <= jtag_state_drs; + dummy_state_cdr <= jtag_state_cdr; + dummy_state_sdr <= jtag_state_sdr; + dummy_state_e1dr <= jtag_state_e1dr; + dummy_state_pdr <= jtag_state_pdr; + dummy_state_e2dr <= jtag_state_e2dr; + dummy_state_udr <= jtag_state_udr; + dummy_state_irs <= jtag_state_irs; + dummy_state_cir <= jtag_state_cir; + dummy_state_sir <= jtag_state_sir; + dummy_state_e1ir <= jtag_state_e1ir; + dummy_state_pir <= jtag_state_pir; + dummy_state_e2ir <= jtag_state_e2ir; + dummy_state_uir <= jtag_state_uir; + dummy_tms <= jtag_tms; + dummy_tck <= jtag_tck; + -- virtual signals + virtual_state_uir <= jtag_usr1 and jtag_state_udr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + virtual_state_cir <= jtag_usr1 and jtag_state_cdr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + virtual_state_udr <= not jtag_usr1 and jtag_state_udr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + virtual_state_e2dr <= not jtag_usr1 and jtag_state_e2dr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + virtual_state_pdr <= not jtag_usr1 and jtag_state_pdr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + virtual_state_e1dr <= not jtag_usr1 and jtag_state_e1dr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + virtual_state_sdr <= not jtag_usr1 and jtag_state_sdr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + virtual_state_cdr <= not jtag_usr1 and jtag_state_cdr and virtual_ir_in_i(SLD_NODE_IR_WIDTH_i - 1); + + + -- purpose: captures the shift register during jtag_state_e1dr + -- type : sequential + -- inputs : jtag_tck, jtag_state_tlr + -- outputs: virtual_ir_in + SHIFT_REG_HOLD : process (jtag_tck, jtag_state_tlr) + begin -- process SHIFT_REG_HOLD + if jtag_state_tlr = '1' then -- asynchronous reset (active high) + virtual_ir_in_i <= (others => '0'); + elsif jtag_tck'event and jtag_tck = '0' then -- falling clock edge + if (ir_srl(SLD_NODE_IR_WIDTH_i - 1) = '1' and jtag_state_e1dr = '1') then + virtual_ir_in_i <= ir_srl; + end if; + end if; + end process SHIFT_REG_HOLD; + + +end behavior; + + +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.signal_gen; +use work.jtag_tap_controller; +use work.dummy_hub; + +------------------------------------------------------------------------------- +-- Entity Name : sld_virtual_jtag +-- +-- Description : Simulatiom model for SLD_VIRTUAL_JTAG megafunction +-- +-- Limitation : +-- +-- Results Expected : +-- +-- +------------------------------------------------------------------------------- + + +entity sld_virtual_jtag is + + generic ( + lpm_type : string := "SLD_VIRTUAL_JTAG"; + -- required by coding standard + lpm_hint : string := "SLD_VIRTUAL_JTAG"; -- required by coding standard + sld_auto_instance_index : string := "NO"; + -- Yes of auto index is desired and no otherwise + sld_instance_index : integer := 0; + -- Index to be used if SLD_AUTO_INSTANCE_INDEX is no + sld_ir_width : integer := 1; + -- the width of the IR register + sld_sim_n_scan : integer := 0; + -- the number of scans in the simulation model + sld_sim_total_length : integer := 0; + -- the total bit width of all DR scan values + sld_sim_action : string := ""); + -- the actions to be simulated in a format specified by the documentation + port ( + tdo : in std_logic := '0'; -- tdo signal into megafunction + ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0'); + -- parallel ir data into megafunction + tck : out std_logic; -- tck signal from megafunction + tdi : out std_logic; -- tdi signal from megafunction + ir_in : out std_logic_vector(sld_ir_width - 1 downto 0); + -- paraller ir data from megafunction + virtual_state_cdr : out std_logic; -- cdr state signal of megafunction + virtual_state_sdr : out std_logic; -- sdr state signal of megafunction + virtual_state_e1dr : out std_logic; + -- e1dr state signal of megafunction + virtual_state_pdr : out std_logic; -- pdr state signal of megafunction + virtual_state_e2dr : out std_logic; + -- e2dr state signal of megafunction + virtual_state_udr : out std_logic; -- udr state signal of megafunction + virtual_state_cir : out std_logic; -- cir state signal of megafunction + virtual_state_uir : out std_logic; -- uir state signal of megafunction + jtag_state_tlr : out std_logic; -- Test, Logic, Reset state + jtag_state_rti : out std_logic; -- Run, Test, Idle state + jtag_state_sdrs : out std_logic; -- Select DR scan state + jtag_state_cdr : out std_logic; -- capture DR state + jtag_state_sdr : out std_logic; -- Shift DR state + jtag_state_e1dr : out std_logic; -- exit 1 dr state + jtag_state_pdr : out std_logic; -- pause dr state + jtag_state_e2dr : out std_logic; -- exit 2 dr state + jtag_state_udr : out std_logic; -- update dr state + jtag_state_sirs : out std_logic; -- Select IR scan state + jtag_state_cir : out std_logic; -- capture IR state + jtag_state_sir : out std_logic; -- shift IR state + jtag_state_e1ir : out std_logic; -- exit 1 IR state + jtag_state_pir : out std_logic; -- pause IR state + jtag_state_e2ir : out std_logic; -- exit 2 IR state + jtag_state_uir : out std_logic; -- update IR state + tms : out std_logic); -- tms signal +end sld_virtual_jtag; + +architecture structural of sld_virtual_jtag is + + component signal_gen + generic ( + sld_node_ir_width : integer; + sld_node_n_scan : natural; + sld_node_total_length : natural; + sld_node_sim_action : string); + port ( + tck : out std_logic; + tms : out std_logic; + tdi : out std_logic; + jtag_usr1 : in std_logic; + tdo : in std_logic); + end component; + + component jtag_tap_controller + generic ( + ir_register_width : integer); + port ( + tck : in std_logic; + tms : in std_logic; + tdi : in std_logic; + jtag_tdo : in std_logic; + tdo : out std_logic; + jtag_tck : out std_logic; + jtag_tms : out std_logic; + jtag_tdi : out std_logic; + jtag_state_tlr : out std_logic; + jtag_state_rti : out std_logic; + jtag_state_drs : out std_logic; + jtag_state_cdr : out std_logic; + jtag_state_sdr : out std_logic; + jtag_state_e1dr : out std_logic; + jtag_state_pdr : out std_logic; + jtag_state_e2dr : out std_logic; + jtag_state_udr : out std_logic; + jtag_state_irs : out std_logic; + jtag_state_cir : out std_logic; + jtag_state_sir : out std_logic; + jtag_state_e1ir : out std_logic; + jtag_state_pir : out std_logic; + jtag_state_e2ir : out std_logic; + jtag_state_uir : out std_logic; + jtag_usr1 : out std_logic); + end component; + + component dummy_hub + generic ( + sld_node_ir_width : integer); + port ( + jtag_tck : in std_logic; + jtag_tdi : in std_logic; + jtag_tms : in std_logic; + jtag_usr1 : in std_logic; + jtag_state_tlr : in std_logic; + jtag_state_rti : in std_logic; + jtag_state_drs : in std_logic; + jtag_state_cdr : in std_logic; + jtag_state_sdr : in std_logic; + jtag_state_e1dr : in std_logic; + jtag_state_pdr : in std_logic; + jtag_state_e2dr : in std_logic; + jtag_state_udr : in std_logic; + jtag_state_irs : in std_logic; + jtag_state_cir : in std_logic; + jtag_state_sir : in std_logic; + jtag_state_e1ir : in std_logic; + jtag_state_pir : in std_logic; + jtag_state_e2ir : in std_logic; + jtag_state_uir : in std_logic; + dummy_tdo : in std_logic; + virtual_ir_out : in std_logic_vector(sld_node_ir_width - 1 downto 0); + jtag_tdo : out std_logic; + dummy_tck : out std_logic; + dummy_tdi : out std_logic; + dummy_tms : out std_logic; + dummy_state_tlr : out std_logic; + dummy_state_rti : out std_logic; + dummy_state_drs : out std_logic; + dummy_state_cdr : out std_logic; + dummy_state_sdr : out std_logic; + dummy_state_e1dr : out std_logic; + dummy_state_pdr : out std_logic; + dummy_state_e2dr : out std_logic; + dummy_state_udr : out std_logic; + dummy_state_irs : out std_logic; + dummy_state_cir : out std_logic; + dummy_state_sir : out std_logic; + dummy_state_e1ir : out std_logic; + dummy_state_pir : out std_logic; + dummy_state_e2ir : out std_logic; + dummy_state_uir : out std_logic; + virtual_state_cdr : out std_logic; + virtual_state_sdr : out std_logic; + virtual_state_e1dr : out std_logic; + virtual_state_pdr : out std_logic; + virtual_state_e2dr : out std_logic; + virtual_state_udr : out std_logic; + virtual_state_cir : out std_logic; + virtual_state_uir : out std_logic; + virtual_ir_in : out std_logic_vector(sld_node_ir_width - 1 downto 0)); + end component; + +--------------------------------------------------------------------------- +-- internal signals + signal tck_i : std_logic; + signal tms_i : std_logic; + signal tdi_i : std_logic; + signal tdo_i : std_logic; + signal jtag_tdo_i : std_logic; + signal jtag_tck_i : std_logic; + signal jtag_tms_i : std_logic; + signal jtag_tdi_i : std_logic; + signal jtag_state_tlr_i : std_logic; + signal jtag_state_rti_i : std_logic; + signal jtag_state_drs_i : std_logic; + signal jtag_state_cdr_i : std_logic; + signal jtag_state_sdr_i : std_logic; + signal jtag_state_e1dr_i : std_logic; + signal jtag_state_pdr_i : std_logic; + signal jtag_state_e2dr_i : std_logic; + signal jtag_state_udr_i : std_logic; + signal jtag_state_irs_i : std_logic; + signal jtag_state_cir_i : std_logic; + signal jtag_state_sir_i : std_logic; + signal jtag_state_e1ir_i : std_logic; + signal jtag_state_pir_i : std_logic; + signal jtag_state_e2ir_i : std_logic; + signal jtag_state_uir_i : std_logic; + signal jtag_usr1_i : std_logic; + + constant ir_register_width : integer := 10; -- the width of the ir shift register + + + +begin -- structural + user_input: signal_gen + generic map ( + sld_node_ir_width => sld_ir_width, + sld_node_n_scan => sld_sim_n_scan, + sld_node_total_length => sld_sim_total_length, + sld_node_sim_action => sld_sim_action) + port map ( + tck => tck_i, + tms => tms_i, + tdi => tdi_i, + jtag_usr1 => jtag_usr1_i, + tdo => tdo_i); + + jtag : jtag_tap_controller + generic map ( + ir_register_width => ir_register_width) + port map ( + tck => tck_i, + tms => tms_i, + tdi => tdi_i, + jtag_tdo => jtag_tdo_i, + tdo => tdo_i, + jtag_tck => jtag_tck_i, + jtag_tms => jtag_tms_i, + jtag_tdi => jtag_tdi_i, + jtag_state_tlr => jtag_state_tlr_i, + jtag_state_rti => jtag_state_rti_i, + jtag_state_drs => jtag_state_drs_i, + jtag_state_cdr => jtag_state_cdr_i, + jtag_state_sdr => jtag_state_sdr_i, + jtag_state_e1dr => jtag_state_e1dr_i, + jtag_state_pdr => jtag_state_pdr_i, + jtag_state_e2dr => jtag_state_e2dr_i, + jtag_state_udr => jtag_state_udr_i, + jtag_state_irs => jtag_state_irs_i, + jtag_state_cir => jtag_state_cir_i, + jtag_state_sir => jtag_state_sir_i, + jtag_state_e1ir => jtag_state_e1ir_i, + jtag_state_pir => jtag_state_pir_i, + jtag_state_e2ir => jtag_state_e2ir_i, + jtag_state_uir => jtag_state_uir_i, + jtag_usr1 => jtag_usr1_i); + + hub: dummy_hub + generic map ( + sld_node_ir_width => sld_ir_width) + port map ( + jtag_tck => jtag_tck_i, + jtag_tdi => jtag_tdi_i, + jtag_tms => jtag_tms_i, + jtag_usr1 => jtag_usr1_i, + jtag_state_tlr => jtag_state_tlr_i, + jtag_state_rti => jtag_state_rti_i, + jtag_state_drs => jtag_state_drs_i, + jtag_state_cdr => jtag_state_cdr_i, + jtag_state_sdr => jtag_state_sdr_i, + jtag_state_e1dr => jtag_state_e1dr_i, + jtag_state_pdr => jtag_state_pdr_i, + jtag_state_e2dr => jtag_state_e2dr_i, + jtag_state_udr => jtag_state_udr_i, + jtag_state_irs => jtag_state_irs_i, + jtag_state_cir => jtag_state_cir_i, + jtag_state_sir => jtag_state_sir_i, + jtag_state_e1ir => jtag_state_e1ir_i, + jtag_state_pir => jtag_state_pir_i, + jtag_state_e2ir => jtag_state_e2ir_i, + jtag_state_uir => jtag_state_uir_i, + dummy_tdo => tdo, + virtual_ir_out => ir_out, + jtag_tdo => jtag_tdo_i, + dummy_tck => tck, + dummy_tdi => tdi, + dummy_tms => tms, + dummy_state_tlr => jtag_state_tlr, + dummy_state_rti => jtag_state_rti, + dummy_state_drs => jtag_state_sdrs, + dummy_state_cdr => jtag_state_cdr, + dummy_state_sdr => jtag_state_sdr, + dummy_state_e1dr => jtag_state_e1dr, + dummy_state_pdr => jtag_state_pdr, + dummy_state_e2dr => jtag_state_e2dr, + dummy_state_udr => jtag_state_udr, + dummy_state_irs => jtag_state_sirs, + dummy_state_cir => jtag_state_cir, + dummy_state_sir => jtag_state_sir, + dummy_state_e1ir => jtag_state_e1ir, + dummy_state_pir => jtag_state_pir, + dummy_state_e2ir => jtag_state_e2ir, + dummy_state_uir => jtag_state_uir, + virtual_state_cdr => virtual_state_cdr, + virtual_state_sdr => virtual_state_sdr, + virtual_state_e1dr => virtual_state_e1dr, + virtual_state_pdr => virtual_state_pdr, + virtual_state_e2dr => virtual_state_e2dr, + virtual_state_udr => virtual_state_udr, + virtual_state_cir => virtual_state_cir, + virtual_state_uir => virtual_state_uir, + virtual_ir_in => ir_in); + +end structural; +library ieee; +use ieee.std_logic_1164.all; +use work.altera_mf_components.all; + +entity sld_signaltap is + generic ( + SLD_USE_JTAG_SIGNAL_ADAPTER : natural := 1; + SLD_CURRENT_RESOURCE_WIDTH : natural := 0; + SLD_INVERSION_MASK : std_logic_vector := "0"; + SLD_POWER_UP_TRIGGER : natural := 0; + SLD_ADVANCED_TRIGGER_6 : string := "NONE"; + SLD_ADVANCED_TRIGGER_9 : string := "NONE"; + SLD_ADVANCED_TRIGGER_7 : string := "NONE"; + SLD_HPS_EVENT_ENABLED : natural := 0; + SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : string := "basic"; + SLD_STORAGE_QUALIFIER_GAP_RECORD : natural := 0; + SLD_SECTION_ID : string := "hdl_signaltap_0"; + SLD_INCREMENTAL_ROUTING : natural := 0; + SLD_STORAGE_QUALIFIER_PIPELINE : natural := 0; + SLD_TRIGGER_IN_ENABLED : natural := 0; + SLD_STATE_BITS : natural := 11; + SLD_HPS_EVENT_ID : natural := 0; + SLD_CREATE_MONITOR_INTERFACE : natural := 0; + SLD_STATE_FLOW_USE_GENERATED : natural := 0; + SLD_INVERSION_MASK_LENGTH : integer := 1; + SLD_DATA_BITS : natural := 1; + SLD_BUFFER_FULL_STOP : natural := 1; + SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : natural := 0; + SLD_ATTRIBUTE_MEM_MODE : string := "OFF"; + SLD_STORAGE_QUALIFIER_MODE : string := "OFF"; + SLD_STATE_FLOW_MGR_ENTITY : string := "state_flow_mgr_entity.vhd"; + SLD_HPS_TRIGGER_IN_ENABLED : natural := 0; + SLD_NODE_CRC_LOWORD : natural := 50132; + SLD_ADVANCED_TRIGGER_5 : string := "NONE"; + SLD_TRIGGER_BITS : natural := 1; + SLD_STORAGE_QUALIFIER_BITS : natural := 1; + SLD_HPS_TRIGGER_OUT_ENABLED : natural := 0; + SLD_ADVANCED_TRIGGER_10 : string := "NONE"; + SLD_MEM_ADDRESS_BITS : natural := 7; + SLD_ADVANCED_TRIGGER_ENTITY : string := "basic"; + SLD_ADVANCED_TRIGGER_4 : string := "NONE"; + SLD_ADVANCED_TRIGGER_8 : string := "NONE"; + SLD_TRIGGER_LEVEL : natural := 10; + SLD_RAM_BLOCK_TYPE : string := "AUTO"; + SLD_ADVANCED_TRIGGER_2 : string := "NONE"; + SLD_ADVANCED_TRIGGER_1 : string := "NONE"; + SLD_DATA_BIT_CNTR_BITS : natural := 4; + SLD_SAMPLE_DEPTH : natural := 16; + lpm_type : string := "sld_signaltap"; + SLD_NODE_CRC_BITS : natural := 32; + SLD_ENABLE_ADVANCED_TRIGGER : natural := 0; + SLD_SEGMENT_SIZE : natural := 0; + SLD_NODE_INFO : natural := 0; + SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : natural := 0; + SLD_NODE_CRC_HIWORD : natural := 41394; + SLD_TRIGGER_LEVEL_PIPELINE : natural := 1; + SLD_ADVANCED_TRIGGER_3 : string := "NONE" + ); + port ( + jtag_state_sdr : in std_logic := '0'; + ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0'); + acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0); + gnd : out std_logic; + jtag_state_cir : in std_logic := '0'; + jtag_state_e2ir : in std_logic := '0'; + jtag_state_pir : in std_logic := '0'; + jtag_state_udr : in std_logic := '0'; + vcc : out std_logic; + jtag_state_e1dr : in std_logic := '0'; + jtag_state_rti : in std_logic := '0'; + jtag_state_e1ir : in std_logic := '0'; + jtag_state_pdr : in std_logic := '0'; + acq_clk : in std_logic; + clr : in std_logic := '0'; + trigger_in : in std_logic := '0'; + ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0); + jtag_state_sirs : in std_logic := '0'; + jtag_state_cdr : in std_logic := '0'; + jtag_state_sir : in std_logic := '0'; + jtag_state_e2dr : in std_logic := '0'; + tms : in std_logic := '0'; + jtag_state_tlr : in std_logic := '0'; + jtag_state_sdrs : in std_logic := '0'; + tdi : in std_logic := '0'; + jtag_state_uir : in std_logic := '0'; + acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0'); + trigger_out : out std_logic; + storage_enable : in std_logic := '0'; + acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0); + acq_storage_qualifier_in : in std_logic_vector(SLD_STORAGE_QUALIFIER_BITS-1 downto 0) := (others => '0'); + acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0'); + tdo : out std_logic; + crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0'); + clrn : in std_logic := '0'; + raw_tck : in std_logic := '0'; + irq : out std_logic; + usr1 : in std_logic := '0'; + ena : in std_logic := '0' + ); +end sld_signaltap; + +architecture sim_sld_signaltap of sld_signaltap is +begin + +end sim_sld_signaltap; + +library ieee; +use ieee.std_logic_1164.all; +use work.altera_mf_components.all; + +entity altstratixii_oct is + generic ( + lpm_type : string := "altstratixii_oct" + ); + port ( + terminationenable : in std_logic; + terminationclock : in std_logic; + rdn : in std_logic; + rup : in std_logic + ); +end altstratixii_oct; + +architecture sim_altstratixii_oct of altstratixii_oct is +begin + +end sim_altstratixii_oct; + +library ieee; +use ieee.std_logic_1164.all; +use work.altera_mf_components.all; + +entity altparallel_flash_loader is + generic ( + flash_data_width : NATURAL := 16; + dclk_create_delay : NATURAL := 0; + flash_burst_extra_cycle : NATURAL := 0; + safe_mode_retry : NATURAL := 1; + us_unit_counter : NATURAL := 1; + burst_mode_numonyx : NATURAL := 0; + burst_mode : NATURAL := 0; + clk_divisor : NATURAL := 1; + addr_width : NATURAL := 20; + tristate_checkbox : NATURAL := 0; + nflash_mfc : STRING := "NUMONYX"; + safe_mode_revert_addr : NATURAL := 0; + flash_static_wait_width : NATURAL := 15; + page_mode : NATURAL := 0; + flash_ecc_checkbox : NATURAL := 0; + features_pgm : NATURAL := 1; + BURST_MODE_LATENCY_COUNT : NATURAL := 4; + auto_restart : STRING := "OFF"; + page_clk_divisor : NATURAL := 1; + safe_mode_halt : NATURAL := 0; + flash_nreset_counter : NATURAL := 1; + normal_mode : NATURAL := 1; + safe_mode_revert : NATURAL := 0; + fifo_size : NATURAL := 16; + nrb_addr : NATURAL := 65667072; + nand_size : NATURAL := 67108864; + dclk_divisor : NATURAL := 1; + rsu_watchdog_counter : NATURAL := 100000000; + flash_nreset_checkbox : NATURAL := 0; + flash_type : STRING := "CFI_FLASH"; + features_cfg : NATURAL := 1; + burst_mode_intel : NATURAL := 0; + extra_addr_byte : NATURAL := 0; + qspi_data_delay : NATURAL := 0; + option_bits_start_address : NATURAL := 0; + pfl_rsu_watchdog_enabled : NATURAL := 0; + qflash_fast_speed : NATURAL := 0; + enhanced_flash_programming : NATURAL := 0; + qspi_data_delay_count : NATURAL := 1; + conf_wait_timer_width : NATURAL := 16; + lpm_type : STRING := "ALTPARALLEL_FLASH_LOADER"; + n_flash : NATURAL := 1; + disable_crc_checkbox : NATURAL := 0; + burst_mode_spansion : NATURAL := 0; + qflash_mfc : STRING := "ALTERA"; + decompressor_mode : STRING := "NONE"; + conf_data_width : NATURAL := 1 + ); + port ( + flash_nce : out std_logic_vector(n_flash-1 downto 0); + fpga_data : out std_logic_vector(conf_data_width-1 downto 0); + fpga_dclk : out std_logic; + fpga_nstatus : in std_logic := '0'; + flash_ale : out std_logic; + pfl_clk : in std_logic := '0'; + fpga_nconfig : out std_logic; + flash_io2 : inout std_logic_vector(n_flash-1 downto 0); + flash_sck : out std_logic_vector(n_flash-1 downto 0); + flash_noe : out std_logic; + flash_nwe : out std_logic; + pfl_watchdog_error : out std_logic; + pfl_reset_watchdog : in std_logic := '0'; + fpga_conf_done : in std_logic := '0'; + flash_rdy : in std_logic := '1'; + pfl_flash_access_granted : in std_logic := '0'; + pfl_nreconfigure : in std_logic := '1'; + flash_cle : out std_logic; + flash_nreset : out std_logic; + flash_io0 : inout std_logic_vector(n_flash-1 downto 0); + pfl_nreset : in std_logic := '0'; + flash_data : inout std_logic_vector(flash_data_width-1 downto 0); + flash_io1 : inout std_logic_vector(n_flash-1 downto 0); + flash_nadv : out std_logic; + flash_clk : out std_logic; + flash_io3 : inout std_logic_vector(n_flash-1 downto 0); + flash_io : inout std_logic_vector(7 downto 0); + flash_addr : out std_logic_vector(addr_width-1 downto 0); + pfl_flash_access_request : out std_logic; + flash_ncs : out std_logic_vector(n_flash-1 downto 0); + fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0') + ); +end altparallel_flash_loader; + +architecture sim_altparallel_flash_loader of altparallel_flash_loader is +begin + +end sim_altparallel_flash_loader; + +library ieee; +use ieee.std_logic_1164.all; +use work.altera_mf_components.all; + +entity altserial_flash_loader is + generic ( + enhanced_mode : natural := 0; + intended_device_family : STRING := "Cyclone"; + enable_shared_access : STRING := "OFF"; + enable_quad_spi_support : natural := 0; + ncso_width : natural := 1; + lpm_type : STRING := "ALTSERIAL_FLASH_LOADER" + ); + port ( + data_in : in std_logic_vector(3 downto 0) := (others => '0'); + noe : in std_logic := '0'; + asmi_access_granted : in std_logic := '1'; + data_out : out std_logic_vector(3 downto 0); + data_oe : in std_logic_vector(3 downto 0) := (others => '0'); + sdoin : in std_logic := '0'; + asmi_access_request : out std_logic; + data0out : out std_logic; + scein : in std_logic_vector(ncso_width-1 downto 0) := (others => '0'); + dclkin : in std_logic := '0' + ); +end altserial_flash_loader; + +architecture sim_altserial_flash_loader of altserial_flash_loader is +begin + +end sim_altserial_flash_loader; + +library ieee; +use ieee.std_logic_1164.all; +use work.altera_mf_components.all; + +entity sld_virtual_jtag_basic is + generic ( + lpm_hint : string := "UNUSED"; + sld_sim_action : string := "UNUSED"; + sld_instance_index : natural := 0; + sld_ir_width : natural := 1; + sld_sim_n_scan : natural := 0; + sld_mfg_id : natural := 0; + sld_version : natural := 0; + sld_type_id : natural := 0; + lpm_type : string := "sld_virtual_jtag_basic"; + sld_auto_instance_index : string := "NO"; + sld_sim_total_length : natural := 0 + ); + port ( + jtag_state_sdr : out std_logic; + jtag_state_sirs : out std_logic; + ir_out : in std_logic_vector(sld_ir_width-1 downto 0); + jtag_state_sir : out std_logic; + jtag_state_cdr : out std_logic; + jtag_state_e2dr : out std_logic; + tms : out std_logic; + jtag_state_sdrs : out std_logic; + jtag_state_tlr : out std_logic; + ir_in : out std_logic_vector(sld_ir_width-1 downto 0); + virtual_state_sdr : out std_logic; + tdi : out std_logic; + jtag_state_uir : out std_logic; + jtag_state_cir : out std_logic; + virtual_state_cdr : out std_logic; + virtual_state_uir : out std_logic; + virtual_state_e2dr : out std_logic; + jtag_state_e2ir : out std_logic; + virtual_state_cir : out std_logic; + jtag_state_pir : out std_logic; + jtag_state_udr : out std_logic; + virtual_state_udr : out std_logic; + tdo : in std_logic; + jtag_state_e1dr : out std_logic; + jtag_state_rti : out std_logic; + virtual_state_pdr : out std_logic; + virtual_state_e1dr : out std_logic; + jtag_state_e1ir : out std_logic; + jtag_state_pdr : out std_logic; + tck : out std_logic + ); +end sld_virtual_jtag_basic; + +architecture sim_sld_virtual_jtag_basic of sld_virtual_jtag_basic is +begin + +end sim_sld_virtual_jtag_basic; + +library ieee; +use ieee.std_logic_1164.all; +use work.altera_mf_components.all; + +entity altsource_probe is + generic ( + lpm_hint : string := "UNUSED"; + sld_instance_index : natural := 0; + source_initial_value : string := "0"; + sld_ir_width : natural := 4; + probe_width : natural := 1; + source_width : natural := 1; + instance_id : string := "UNUSED"; + lpm_type : string := "altsource_probe"; + sld_auto_instance_index : string := "YES"; + SLD_NODE_INFO : natural := 4746752; + enable_metastability : string := "NO" + ); + port ( + source_clk : in std_logic; + probe : in std_logic_vector(probe_width-1 downto 0); + source : out std_logic_vector(source_width-1 downto 0); + source_ena : in std_logic + ); +end altsource_probe; + +architecture sim_altsource_probe of altsource_probe is +begin + +end sim_altsource_probe; + diff --git a/Common/sim/altera/altera_mf_components.vhd b/Common/sim/altera/altera_mf_components.vhd new file mode 100644 index 0000000..6438c3c --- /dev/null +++ b/Common/sim/altera/altera_mf_components.vhd @@ -0,0 +1,2166 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 +---------------------------------------------------------------------------- +-- ALtera Megafunction Component Declaration File +---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package altera_mf_components is +type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + +component lcell + port ( + a_in : in std_logic; + a_out : out std_logic); +end component; + + +component altclklock + generic ( + inclock_period : natural := 10000; -- units in ps + inclock_settings : string := "UNUSED"; + valid_lock_cycles : natural := 5; + invalid_lock_cycles : natural := 5; + valid_lock_multiplier : natural := 5; + invalid_lock_multiplier : natural := 5; + operation_mode : string := "NORMAL"; + clock0_boost : natural := 1; + clock0_divide : natural := 1; + clock0_settings : string := "UNUSED"; + clock0_time_delay : string := "0"; + clock1_boost : natural := 1; + clock1_divide : natural := 1; + clock1_settings : string := "UNUSED"; + clock1_time_delay : string := "0"; + clock2_boost : natural := 1; + clock2_divide : natural := 1; + clock2_settings : string := "UNUSED"; + clock2_time_delay : string := "0"; + clock_ext_boost : natural := 1; + clock_ext_divide : natural := 1; + clock_ext_settings : string := "UNUSED"; + clock_ext_time_delay : string := "0"; + outclock_phase_shift : natural := 0; -- units in ps + intended_device_family : string := "Stratix" ; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altclklock" ); + port( + inclock : in std_logic; -- required port, input reference clock + inclocken : in std_logic := '1'; -- PLL enable signal + fbin : in std_logic := '1'; -- feedback input for the PLL + clock0 : out std_logic; -- clock0 output + clock1 : out std_logic; -- clock1 output + clock2 : out std_logic; -- clock2 output + clock_ext : out std_logic; -- external clock output + locked : out std_logic ); -- PLL lock signal +end component; + +component altlvds_rx + generic ( + number_of_channels : natural; + deserialization_factor : natural; + inclock_boost : natural:= 0; + registered_output : string := "ON"; + inclock_period : natural; + cds_mode : string := "UNUSED"; + intended_device_family : string := "Stratix"; + input_data_rate : natural:= 0; + inclock_data_alignment : string := "UNUSED"; + registered_data_align_input : string :="ON"; + common_rx_tx_pll : string :="ON"; + enable_dpa_mode : string := "OFF"; + enable_dpa_pll_calibration : string := "OFF"; + enable_dpa_calibration : string := "ON"; + enable_dpa_fifo : string := "ON"; + use_dpll_rawperror : string := "OFF"; + use_coreclock_input : string := "OFF"; + dpll_lock_count : natural:= 0; + dpll_lock_window : natural:= 0; + outclock_resource : string := "AUTO"; + data_align_rollover : natural := 10; + lose_lock_on_one_change : string := "OFF"; + reset_fifo_at_first_lock : string := "ON"; + use_external_pll : string := "OFF"; + implement_in_les : string := "OFF"; + buffer_implementation : string := "RAM"; + port_rx_data_align : string := "PORT_CONNECTIVITY"; + port_rx_channel_data_align : string := "PORT_CONNECTIVITY"; + pll_operation_mode : string := "NORMAL"; + x_on_bitslip : string := "ON"; + use_no_phase_shift : string := "ON"; + rx_align_data_reg : string := "RISING_EDGE"; + inclock_phase_shift : integer := 0; + enable_soft_cdr_mode : string := "OFF"; + sim_dpa_output_clock_phase_shift : integer := 0; + sim_dpa_is_negative_ppm_drift : string := "OFF"; + sim_dpa_net_ppm_variation : natural := 0; + enable_dpa_align_to_rising_edge_only : string := "OFF"; + enable_dpa_initial_phase_selection : string := "OFF"; + dpa_initial_phase_value :natural := 0; + pll_self_reset_on_loss_lock : string := "OFF"; + refclk_frequency : string := "UNUSED"; + enable_clock_pin_mode : string := "UNUSED"; + data_rate : string := "UNUSED"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altlvds_rx"; + clk_src_is_pll : string := "off" ); + port ( + rx_in : in std_logic_vector(number_of_channels-1 downto 0); + rx_inclock : in std_logic := '0'; + rx_syncclock : in std_logic := '0'; + rx_dpaclock : in std_logic := '0'; + rx_readclock : in std_logic := '0'; + rx_enable : in std_logic := '1'; + rx_deskew : in std_logic := '0'; + rx_pll_enable : in std_logic := '1'; + rx_data_align : in std_logic := '0'; + rx_data_align_reset : in std_logic := '0'; + rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1'); + rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + pll_areset : in std_logic := '0'; + rx_data_reset : in std_logic := '0'; + dpa_pll_recal : in std_logic := '0'; + pll_phasedone : in std_logic := '1'; + rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + rx_outclock : out std_logic; + rx_locked : out std_logic; + rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0); + rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0); + rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0); + dpa_pll_cal_busy : out std_logic; + pll_phasestep : out std_logic; + pll_phaseupdown : out std_logic; + pll_phasecounterselect: out std_logic_Vector(3 downto 0); + pll_scanclk : out std_logic); +end component; + +component altlvds_tx + generic ( + number_of_channels : natural; + deserialization_factor : natural:= 4; + inclock_boost : natural := 0; + outclock_divide_by : positive:= 1; + registered_input : string := "ON"; + multi_clock : string := "OFF"; + inclock_period : natural; + center_align_msb : string := "UNUSED"; + intended_device_family : string := "Stratix"; + output_data_rate : natural:= 0; + outclock_resource : string := "AUTO"; + common_rx_tx_pll : string := "ON"; + inclock_data_alignment : string := "EDGE_ALIGNED"; + outclock_alignment : string := "EDGE_ALIGNED"; + use_external_pll : string := "OFF"; + implement_in_les : STRING := "OFF"; + preemphasis_setting : natural := 0; + vod_setting : natural := 0; + differential_drive : natural := 0; + outclock_multiply_by : natural := 1; + coreclock_divide_by : natural := 2; + outclock_duty_cycle : natural := 50; + inclock_phase_shift : integer := 0; + outclock_phase_shift : integer := 0; + use_no_phase_shift : string := "ON"; + pll_self_reset_on_loss_lock : string := "OFF"; + refclk_frequency : string := "UNUSED"; + enable_clock_pin_mode : string := "UNUSED"; + data_rate : string := "UNUSED"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altlvds_tx"; + clk_src_is_pll : string := "off" ); + port ( + tx_in : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + tx_inclock : in std_logic := '0'; + tx_syncclock : in std_logic := '0'; + tx_enable : in std_logic := '1'; + sync_inclock : in std_logic := '0'; + tx_pll_enable : in std_logic := '1'; + pll_areset : in std_logic := '0'; + tx_data_reset : in std_logic := '0'; + tx_out : out std_logic_vector(number_of_channels-1 downto 0); + tx_outclock : out std_logic; + tx_coreclock : out std_logic; + tx_locked : out std_logic ); +end component; + +component altdpram + generic ( + width : natural; + widthad : natural; + numwords : natural := 0; + lpm_file : string := "UNUSED"; + lpm_hint : string := "USE_EAB=ON"; + use_eab : string := "ON"; + indata_reg : string := "INCLOCK"; + indata_aclr : string := "ON"; + wraddress_reg : string := "INCLOCK"; + wraddress_aclr : string := "ON"; + wrcontrol_reg : string := "INCLOCK"; + wrcontrol_aclr : string := "ON"; + rdaddress_reg : string := "OUTCLOCK"; + rdaddress_aclr : string := "ON"; + rdcontrol_reg : string := "OUTCLOCK"; + rdcontrol_aclr : string := "ON"; + outdata_reg : string := "UNREGISTERED"; + outdata_aclr : string := "ON"; + ram_block_type : string := "AUTO"; + width_byteena : natural := 1; + byte_size : natural := 5; + read_during_write_mode_mixed_ports : string := "DONT_CARE"; + maximum_depth : natural:= 2048; + intended_device_family : string := "Stratix"; + lpm_type : string := "altdpram" ); + port( + wren : in std_logic := '0'; + data : in std_logic_vector(width-1 downto 0); + wraddress : in std_logic_vector(widthad-1 downto 0); + wraddressstall : in std_logic := '0'; + inclock : in std_logic := '1'; + inclocken : in std_logic := '1'; + rden : in std_logic := '1'; + rdaddress : in std_logic_vector(widthad-1 downto 0); + rdaddressstall : in std_logic := '0'; + byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1'); + outclock : in std_logic := '1'; + outclocken : in std_logic := '1'; + aclr : in std_logic := '0'; + q : out std_logic_vector(width-1 downto 0) ); +end component; + + +component alt3pram + generic ( + width : natural; + widthad : natural; + numwords : natural := 0; + lpm_file : string := "UNUSED"; + lpm_hint : string := "USE_EAB=ON"; + indata_reg : string := "UNREGISTERED"; + indata_aclr : string := "OFF"; + write_reg : string := "UNREGISTERED"; + write_aclr : string := "OFF"; + rdaddress_reg_a : string := "UNREGISTERED"; + rdaddress_aclr_a : string := "OFF"; + rdaddress_reg_b : string := "UNREGISTERED"; + rdaddress_aclr_b : string := "OFF"; + rdcontrol_reg_a : string := "UNREGISTERED"; + rdcontrol_aclr_a : string := "OFF"; + rdcontrol_reg_b : string := "UNREGISTERED"; + rdcontrol_aclr_b : string := "OFF"; + outdata_reg_a : string := "UNREGISTERED"; + outdata_aclr_a : string := "OFF"; + outdata_reg_b : string := "UNREGISTERED"; + outdata_aclr_b : string := "OFF"; + intended_device_family : string := "Stratix"; + ram_block_type : string := "AUTO"; + maximum_depth : integer := 0; + lpm_type : string := "alt3pram" ); + port ( + wren : in std_logic := '0'; + data : in std_logic_vector(width-1 downto 0); + wraddress : in std_logic_vector(widthad-1 downto 0); + inclock : in std_logic := '0'; + inclocken : in std_logic := '1'; + rden_a : in std_logic := '1'; + rden_b : in std_logic := '1'; + rdaddress_a : in std_logic_vector(widthad-1 downto 0); + rdaddress_b : in std_logic_vector(widthad-1 downto 0); + outclock : in std_logic := '0'; + outclocken : in std_logic := '1'; + aclr : in std_logic := '0'; + qa : out std_logic_vector(width-1 downto 0); + qb : out std_logic_vector(width-1 downto 0) ); +end component; + + +component scfifo + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + lpm_showahead : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"; + intended_device_family : string := "NON_STRATIX"; + almost_full_value : natural := 0; + almost_empty_value : natural := 0; + overflow_checking : string := "ON"; + underflow_checking : string := "ON"; + allow_rwcycle_when_full : string := "OFF"; + add_ram_output_register : string := "OFF"; + use_eab : string := "ON"; + lpm_type : string := "scfifo"; + maximum_depth : natural := 0 ); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + clock : in std_logic; + wrreq : in std_logic; + rdreq : in std_logic; + aclr : in std_logic := '0'; + sclr : in std_logic := '0'; + full : out std_logic; + almost_full : out std_logic; + empty : out std_logic; + almost_empty : out std_logic; + q : out std_logic_vector(lpm_width-1 downto 0); + usedw : out std_logic_vector(lpm_widthu-1 downto 0) ); +end component; + +component dcfifo_mixed_widths + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_width_r : natural := 0; + lpm_widthu_r : natural := 0; + lpm_numwords : natural; + lpm_showahead : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"; + overflow_checking : string := "ON"; + underflow_checking : string := "ON"; + delay_rdusedw : natural := 1; + delay_wrusedw : natural := 1; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"; + add_width : natural := 1; + clocks_are_synchronized : string := "FALSE"; + ram_block_type : string := "AUTO"; + add_usedw_msb_bit : string := "OFF"; + read_aclr_synch : string := "OFF"; + write_aclr_synch : string := "OFF"; + lpm_type : string := "dcfifo_mixed_widths"; + intended_device_family : string := "NON_STRATIX" ); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + wrreq : in std_logic; + rdreq : in std_logic; + aclr : in std_logic := '0'; + rdfull : out std_logic; + wrfull : out std_logic; + wrempty : out std_logic; + rdempty : out std_logic; + q : out std_logic_vector(lpm_width_r-1 downto 0); + rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) ); +end component; + +component dcfifo + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + lpm_showahead : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"; + overflow_checking : string := "ON"; + underflow_checking : string := "ON"; + delay_rdusedw : natural := 1; + delay_wrusedw : natural := 1; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"; + add_width : natural := 1; + clocks_are_synchronized : string := "FALSE"; + ram_block_type : string := "AUTO"; + add_usedw_msb_bit : string := "OFF"; + read_aclr_synch : string := "OFF"; + write_aclr_synch : string := "OFF"; + lpm_type : string := "dcfifo"; + intended_device_family : string := "NON_STRATIX" ); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + wrreq : in std_logic; + rdreq : in std_logic; + aclr : in std_logic := '0'; + rdfull : out std_logic; + wrfull : out std_logic; + wrempty : out std_logic; + rdempty : out std_logic; + q : out std_logic_vector(lpm_width-1 downto 0); + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) ); +end component; + +component altddio_in + generic ( + width : positive; -- required parameter + invert_input_clocks : string := "OFF"; + intended_device_family : string := "Stratix"; + power_up_high : string := "OFF"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altddio_in" ); + port ( + datain : in std_logic_vector(width-1 downto 0); + inclock : in std_logic; + inclocken : in std_logic := '1'; + aset : in std_logic := '0'; + aclr : in std_logic := '0'; + sset : in std_logic := '0'; + sclr : in std_logic := '0'; + dataout_h : out std_logic_vector(width-1 downto 0); + dataout_l : out std_logic_vector(width-1 downto 0) ); +end component; + +component altddio_out + generic ( + width : positive; -- required parameter + power_up_high : string := "OFF"; + oe_reg : string := "UNUSED"; + extend_oe_disable : string := "UNUSED"; + invert_output : string := "OFF"; + intended_device_family : string := "Stratix"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altddio_out" ); + port ( + datain_h : in std_logic_vector(width-1 downto 0); + datain_l : in std_logic_vector(width-1 downto 0); + outclock : in std_logic; + outclocken : in std_logic := '1'; + aset : in std_logic := '0'; + aclr : in std_logic := '0'; + sset : in std_logic := '0'; + sclr : in std_logic := '0'; + oe : in std_logic := '1'; + dataout : out std_logic_vector(width-1 downto 0); + oe_out : out std_logic_vector(width-1 downto 0) ); +end component; + +component altddio_bidir + generic( + width : positive; -- required parameter + power_up_high : string := "OFF"; + oe_reg : string := "UNUSED"; + extend_oe_disable : string := "UNUSED"; + implement_input_in_lcell : string := "UNUSED"; + invert_output : string := "OFF"; + intended_device_family : string := "Stratix"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altddio_bidir" ); + port ( + datain_h : in std_logic_vector(width-1 downto 0); + datain_l : in std_logic_vector(width-1 downto 0); + inclock : in std_logic := '0'; + inclocken : in std_logic := '1'; + outclock : in std_logic; + outclocken : in std_logic := '1'; + aset : in std_logic := '0'; + aclr : in std_logic := '0'; + sset : in std_logic := '0'; + sclr : in std_logic := '0'; + oe : in std_logic := '1'; + dataout_h : out std_logic_vector(width-1 downto 0); + dataout_l : out std_logic_vector(width-1 downto 0); + combout : out std_logic_vector(width-1 downto 0); + oe_out : out std_logic_vector(width-1 downto 0); + dqsundelayedout : out std_logic_vector(width-1 downto 0); + padio : inout std_logic_vector(width-1 downto 0) ); +end component; + +component altshift_taps + generic ( + number_of_taps : integer := 4; + tap_distance : integer := 3; + width : integer := 8; + power_up_state : string := "CLEARED"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altshift_taps"; + intended_device_family : string := "Stratix" ); + port ( + shiftin : in std_logic_vector (width-1 downto 0); + clock : in std_logic; + clken : in std_logic := '1'; + aclr : in std_logic := '0'; + shiftout : out std_logic_vector (width-1 downto 0); + taps : out std_logic_vector ((width*number_of_taps)-1 downto 0)); +end component; + +component altmult_add + generic ( + WIDTH_A : integer := 1; + WIDTH_B : integer := 1; + WIDTH_RESULT : integer := 1; + NUMBER_OF_MULTIPLIERS : integer := 1; + + -- A inputs + INPUT_REGISTER_A0 : string := "CLOCK0"; + INPUT_ACLR_A0 : string := "ACLR3"; + INPUT_SOURCE_A0 : string := "DATAA"; + + INPUT_REGISTER_A1 : string := "CLOCK0"; + INPUT_ACLR_A1 : string := "ACLR3"; + INPUT_SOURCE_A1 : string := "DATAA"; + + INPUT_REGISTER_A2 : string := "CLOCK0"; + INPUT_ACLR_A2 : string := "ACLR3"; + INPUT_SOURCE_A2 : string := "DATAA"; + + INPUT_REGISTER_A3 : string := "CLOCK0"; + INPUT_ACLR_A3 : string := "ACLR3"; + INPUT_SOURCE_A3 : string := "DATAA"; + + PORT_SIGNA : string := "PORT_CONNECTIVITY"; + REPRESENTATION_A : string := "UNSIGNED"; + SIGNED_REGISTER_A : string := "CLOCK0"; + SIGNED_ACLR_A : string := "ACLR3"; + SIGNED_PIPELINE_REGISTER_A : string := "CLOCK0"; + SIGNED_PIPELINE_ACLR_A : string := "ACLR3"; + + -- B inputs + INPUT_REGISTER_B0 : string := "CLOCK0"; + INPUT_ACLR_B0 : string := "ACLR3"; + INPUT_SOURCE_B0 : string := "DATAB"; + + INPUT_REGISTER_B1 : string := "CLOCK0"; + INPUT_ACLR_B1 : string := "ACLR3"; + INPUT_SOURCE_B1 : string := "DATAB"; + + INPUT_REGISTER_B2 : string := "CLOCK0"; + INPUT_ACLR_B2 : string := "ACLR3"; + INPUT_SOURCE_B2 : string := "DATAB"; + + INPUT_REGISTER_B3 : string := "CLOCK0"; + INPUT_ACLR_B3 : string := "ACLR3"; + INPUT_SOURCE_B3 : string := "DATAB"; + + PORT_SIGNB : string := "PORT_CONNECTIVITY"; + REPRESENTATION_B : string := "UNSIGNED"; + SIGNED_REGISTER_B : string := "CLOCK0"; + SIGNED_ACLR_B : string := "ACLR3"; + SIGNED_PIPELINE_REGISTER_B : string := "CLOCK0"; + SIGNED_PIPELINE_ACLR_B : string := "ACLR3"; + + MULTIPLIER_REGISTER0 : string := "CLOCK0"; + MULTIPLIER_ACLR0 : string := "ACLR3"; + MULTIPLIER_REGISTER1 : string := "CLOCK0"; + MULTIPLIER_ACLR1 : string := "ACLR3"; + MULTIPLIER_REGISTER2 : string := "CLOCK0"; + MULTIPLIER_ACLR2 : string := "ACLR3"; + MULTIPLIER_REGISTER3 : string := "CLOCK0"; + MULTIPLIER_ACLR3 : string := "ACLR3"; + + PORT_ADDNSUB1 : string := "PORT_CONNECTIVITY"; + ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0"; + ADDNSUB_MULTIPLIER_ACLR1 : string := "ACLR3"; + ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0"; + ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3"; + + PORT_ADDNSUB3 : string := "PORT_CONNECTIVITY"; + ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0"; + ADDNSUB_MULTIPLIER_ACLR3 : string := "ACLR3"; + ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0"; + ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3"; + + ADDNSUB1_ROUND_ACLR : string := "ACLR3"; + ADDNSUB1_ROUND_PIPELINE_ACLR : string := "ACLR3"; + ADDNSUB1_ROUND_REGISTER : string := "CLOCK0"; + ADDNSUB1_ROUND_PIPELINE_REGISTER : string := "CLOCK0"; + ADDNSUB3_ROUND_ACLR : string := "ACLR3"; + ADDNSUB3_ROUND_PIPELINE_ACLR : string := "ACLR3"; + ADDNSUB3_ROUND_REGISTER : string := "CLOCK0"; + ADDNSUB3_ROUND_PIPELINE_REGISTER : string := "CLOCK0"; + + MULT01_ROUND_ACLR : string := "ACLR3"; + MULT01_ROUND_REGISTER : string := "CLOCK0"; + MULT01_SATURATION_REGISTER : string := "CLOCK0"; + MULT01_SATURATION_ACLR : string := "ACLR3"; + MULT23_ROUND_REGISTER : string := "CLOCK0"; + MULT23_ROUND_ACLR : string := "ACLR3"; + MULT23_SATURATION_REGISTER : string := "CLOCK0"; + MULT23_SATURATION_ACLR : string := "ACLR3"; + + multiplier1_direction : string := "ADD"; + multiplier3_direction : string := "ADD"; + + OUTPUT_REGISTER : string := "CLOCK0"; + OUTPUT_ACLR : string := "ACLR0"; + + -- StratixII parameters + multiplier01_rounding : string := "NO"; + multiplier01_saturation : string := "NO"; + multiplier23_rounding : string := "NO"; + multiplier23_saturation : string := "NO"; + adder1_rounding : string := "NO"; + adder3_rounding : string := "NO"; + port_mult0_is_saturated : string := "UNUSED"; + port_mult1_is_saturated : string := "UNUSED"; + port_mult2_is_saturated : string := "UNUSED"; + port_mult3_is_saturated : string := "UNUSED"; + + -- Stratix III parameters + scanouta_register : string := "UNREGISTERED"; + scanouta_aclr : string := "NONE"; + + -- Rounding parameters + output_rounding : string := "NO"; + output_round_type : string := "NEAREST_INTEGER"; + width_msb : integer := 17; + output_round_register : string := "UNREGISTERED"; + output_round_aclr : string := "NONE"; + output_round_pipeline_register : string := "UNREGISTERED"; + output_round_pipeline_aclr : string := "NONE"; + + chainout_rounding : string := "NO"; + chainout_round_register : string := "UNREGISTERED"; + chainout_round_aclr : string := "NONE"; + chainout_round_pipeline_register : string := "UNREGISTERED"; + chainout_round_pipeline_aclr : string := "NONE"; + chainout_round_output_register : string := "UNREGISTERED"; + chainout_round_output_aclr : string := "NONE"; + + -- saturation parameters + port_output_is_overflow : string := "PORT_UNUSED"; + port_chainout_sat_is_overflow : string := "PORT_UNUSED"; + output_saturation : string := "NO"; + output_saturate_type : string := "ASYMMETRIC"; + width_saturate_sign : integer := 1; + output_saturate_register : string := "UNREGISTERED"; + output_saturate_aclr : string := "NONE"; + output_saturate_pipeline_register : string := "UNREGISTERED"; + output_saturate_pipeline_aclr : string := "NONE"; + + chainout_saturation : string := "NO"; + chainout_saturate_register : string := "UNREGISTERED"; + chainout_saturate_aclr : string := "NONE"; + chainout_saturate_pipeline_register : string := "UNREGISTERED"; + chainout_saturate_pipeline_aclr : string := "NONE"; + chainout_saturate_output_register : string := "UNREGISTERED"; + chainout_saturate_output_aclr : string := "NONE"; + + -- chainout parameters + chainout_adder : string := "NO"; + chainout_register : string := "UNREGISTERED"; + chainout_aclr : string := "NONE"; + width_chainin : integer := 1; + zero_chainout_output_register : string := "UNREGISTERED"; + zero_chainout_output_aclr : string := "NONE"; + + -- rotate & shift parameters + shift_mode : string := "NO"; + rotate_aclr : string := "NONE"; + rotate_register : string := "UNREGISTERED"; + rotate_pipeline_register : string := "UNREGISTERED"; + rotate_pipeline_aclr : string := "NONE"; + rotate_output_register : string := "UNREGISTERED"; + rotate_output_aclr : string := "NONE"; + shift_right_register : string := "UNREGISTERED"; + shift_right_aclr : string := "NONE"; + shift_right_pipeline_register : string := "UNREGISTERED"; + shift_right_pipeline_aclr : string := "NONE"; + shift_right_output_register : string := "UNREGISTERED"; + shift_right_output_aclr : string := "NONE"; + + -- loopback parameters + zero_loopback_register : string := "UNREGISTERED"; + zero_loopback_aclr : string := "NONE"; + zero_loopback_pipeline_register : string := "UNREGISTERED"; + zero_loopback_pipeline_aclr : string := "NONE"; + zero_loopback_output_register : string := "UNREGISTERED"; + zero_loopback_output_aclr : string := "NONE"; + + -- accumulator parameters + accum_sload_register : string := "UNREGISTERED"; + accum_sload_aclr : string := "NONE"; + accum_sload_pipeline_register : string := "UNREGISTERED"; + accum_sload_pipeline_aclr : string := "NONE"; + accum_direction : string := "ADD"; + accumulator : string := "NO"; + + -- Stratix V parameters + width_c : integer := 22; + loadconst_value : integer := 64; + preadder_mode : string := "SIMPLE"; + preadder_direction_0 : string := "ADD"; + preadder_direction_1 : string := "ADD"; + preadder_direction_2 : string := "ADD"; + preadder_direction_3 : string := "ADD"; + input_register_c0 : string := "CLOCK0"; + input_aclr_c0 : string := "ACLR0"; + coefsel0_register : string := "CLOCK0"; + coefsel1_register : string := "CLOCK0"; + coefsel2_register : string := "CLOCK0"; + coefsel3_register : string := "CLOCK0"; + coefsel0_aclr : string := "ACLR0"; + coefsel1_aclr : string := "ACLR0"; + coefsel2_aclr : string := "ACLR0"; + coefsel3_aclr : string := "ACLR0"; + systolic_delay1 : string := "UNREGISTERED"; + systolic_delay3 : string := "UNREGISTERED"; + systolic_aclr1 : string := "NONE"; + systolic_aclr3 : string := "NONE"; + coef0_0 : integer := 0; + coef0_1 : integer := 0; + coef0_2 : integer := 0; + coef0_3 : integer := 0; + coef0_4 : integer := 0; + coef0_5 : integer := 0; + coef0_6 : integer := 0; + coef0_7 : integer := 0; + coef1_0 : integer := 0; + coef1_1 : integer := 0; + coef1_2 : integer := 0; + coef1_3 : integer := 0; + coef1_4 : integer := 0; + coef1_5 : integer := 0; + coef1_6 : integer := 0; + coef1_7 : integer := 0; + coef2_0 : integer := 0; + coef2_1 : integer := 0; + coef2_2 : integer := 0; + coef2_3 : integer := 0; + coef2_4 : integer := 0; + coef2_5 : integer := 0; + coef2_6 : integer := 0; + coef2_7 : integer := 0; + coef3_0 : integer := 0; + coef3_1 : integer := 0; + coef3_2 : integer := 0; + coef3_3 : integer := 0; + coef3_4 : integer := 0; + coef3_5 : integer := 0; + coef3_6 : integer := 0; + coef3_7 : integer := 0; + width_coef : integer := 18; + + EXTRA_LATENCY : integer :=0; + DEDICATED_MULTIPLIER_CIRCUITRY:string := "AUTO"; + DSP_BLOCK_BALANCING : string := "AUTO"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altmult_add"; + intended_device_family : string := "Stratix" ); + port ( + dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0); + datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0); + + scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0'); + scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0'); + + sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0'); + sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0'); + + + -- clock ports + clock3 : in std_logic := '1'; + clock2 : in std_logic := '1'; + clock1 : in std_logic := '1'; + clock0 : in std_logic := '1'; + aclr3 : in std_logic := '0'; + aclr2 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + aclr0 : in std_logic := '0'; + ena3 : in std_logic := '1'; + ena2 : in std_logic := '1'; + ena1 : in std_logic := '1'; + ena0 : in std_logic := '1'; + + -- control signals + signa : in std_logic := 'Z'; + signb : in std_logic := 'Z'; + addnsub1 : in std_logic := 'Z'; + addnsub3 : in std_logic := 'Z'; + + -- StratixII only input ports + mult01_round : in std_logic := '0'; + mult23_round : in std_logic := '0'; + mult01_saturation : in std_logic := '0'; + mult23_saturation : in std_logic := '0'; + addnsub1_round : in std_logic := '0'; + addnsub3_round : in std_logic := '0'; + + -- Stratix III only input ports + output_round : in std_logic := '0'; + chainout_round : in std_logic := '0'; + output_saturate : in std_logic := '0'; + chainout_saturate : in std_logic := '0'; + chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0'); + zero_chainout : in std_logic := '0'; + rotate : in std_logic := '0'; + shift_right : in std_logic := '0'; + zero_loopback : in std_logic := '0'; + accum_sload : in std_logic := '0'; + + -- Stratix V only input ports + coefsel0 : in std_logic_vector (2 downto 0) := (others => '0'); + coefsel1 : in std_logic_vector (2 downto 0) := (others => '0'); + coefsel2 : in std_logic_vector (2 downto 0) := (others => '0'); + coefsel3 : in std_logic_vector (2 downto 0) := (others => '0'); + datac : in std_logic_vector (NUMBER_OF_MULTIPLIERS * width_c -1 downto 0) := (others => '0'); + + -- output ports + result : out std_logic_vector(WIDTH_RESULT -1 downto 0); + scanouta : out std_logic_vector (WIDTH_A -1 downto 0); + scanoutb : out std_logic_vector (WIDTH_B -1 downto 0); + + -- StratixII only output ports + mult0_is_saturated : out std_logic := '0'; + mult1_is_saturated : out std_logic := '0'; + mult2_is_saturated : out std_logic := '0'; + mult3_is_saturated : out std_logic := '0'; + + -- Stratix III only output ports + overflow : out std_logic := '0'; + chainout_sat_overflow : out std_logic := '0'); +end component; + +component altmult_accum + generic ( + width_a : integer := 1; + width_b : integer := 1; + width_c : natural := 1; + width_result : integer := 2; + width_upper_data : integer := 1; + input_source_a : string := "DATAA"; + input_source_b : string := "DATAB"; + input_reg_a : string := "CLOCK0"; + input_aclr_a : string := "ACLR3"; + input_reg_b : string := "CLOCK0"; + input_aclr_b : string := "ACLR3"; + port_addnsub : string := "PORT_CONNECTIVITY"; + addnsub_reg : string := "CLOCK0"; + addnsub_aclr : string := "ACLR3"; + addnsub_pipeline_reg : string := "CLOCK0"; + addnsub_pipeline_aclr : string := "ACLR3"; + accum_direction : string := "ADD"; + accum_sload_reg : string := "CLOCK0"; + accum_sload_aclr : string := "ACLR3"; + accum_sload_pipeline_reg : string := "CLOCK0"; + accum_sload_pipeline_aclr : string := "ACLR3"; + representation_a : string := "UNSIGNED"; + port_signa : string := "PORT_CONNECTIVITY"; + sign_reg_a : string := "CLOCK0"; + sign_aclr_a : string := "ACLR3"; + sign_pipeline_reg_a : string := "CLOCK0"; + sign_pipeline_aclr_a : string := "ACLR3"; + representation_b : string := "UNSIGNED"; + port_signb : string := "PORT_CONNECTIVITY"; + sign_reg_b : string := "CLOCK0"; + sign_aclr_b : string := "ACLR3"; + sign_pipeline_reg_b : string := "CLOCK0"; + sign_pipeline_aclr_b : string := "ACLR3"; + multiplier_reg : string := "CLOCK0"; + multiplier_aclr : string := "ACLR3"; + output_reg : string := "CLOCK0"; + output_aclr : string := "ACLR0"; + extra_multiplier_latency : integer := 0; + extra_accumulator_latency : integer := 0; + dedicated_multiplier_circuitry : string := "AUTO"; + dsp_block_balancing : string := "AUTO"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altmult_accum"; + intended_device_family : string := "Stratix"; + multiplier_rounding : string := "NO"; + multiplier_saturation : string := "NO"; + accumulator_rounding : string := "NO"; + accumulator_saturation : string := "NO"; + port_mult_is_saturated : string := "UNUSED"; + port_accum_is_saturated : string := "UNUSED"; + mult_round_aclr : string := "ACLR3"; + mult_round_reg : string := "CLOCK0"; + mult_saturation_aclr : string := "ACLR3"; + mult_saturation_reg : string := "CLOCK0"; + accum_round_aclr : string := "ACLR3"; + accum_round_reg : string := "CLOCK3"; + accum_round_pipeline_aclr : string := "ACLR3"; + accum_round_pipeline_reg : string := "CLOCK0"; + accum_saturation_aclr : string := "ACLR3"; + accum_saturation_reg : string := "CLOCK0"; + accum_saturation_pipeline_aclr : string := "ACLR3"; + accum_saturation_pipeline_reg : string := "CLOCK0"; + accum_sload_upper_data_aclr : string := "ACLR3"; + accum_sload_upper_data_pipeline_aclr : string := "ACLR3"; + accum_sload_upper_data_pipeline_reg : string := "CLOCK0"; + accum_sload_upper_data_reg : string := "CLOCK0"; + -- StratixV parameters + preadder_mode : string := "SIMPLE"; + loadconst_value : integer := 0; + width_coef : integer := 0; + + loadconst_control_register : string := "CLOCK0"; + loadconst_control_aclr : string := "ACLR0"; + + coefsel0_register : string := "CLOCK0"; + coefsel1_register : string := "CLOCK0"; + coefsel2_register : string := "CLOCK0"; + coefsel3_register : string := "CLOCK0"; + coefsel0_aclr : string := "ACLR0"; + coefsel1_aclr : string := "ACLR0"; + coefsel2_aclr : string := "ACLR0"; + coefsel3_aclr : string := "ACLR0"; + + preadder_direction_0 : string := "ADD"; + preadder_direction_1 : string := "ADD"; + preadder_direction_2 : string := "ADD"; + preadder_direction_3 : string := "ADD"; + + systolic_delay1 : string := "UNREGISTERED"; + systolic_delay3 : string := "UNREGISTERED"; + systolic_aclr1 : string := "NONE"; + systolic_aclr3 : string := "NONE"; + -- coefficient storage + coef0_0 : integer := 0; + coef0_1 : integer := 0; + coef0_2 : integer := 0; + coef0_3 : integer := 0; + coef0_4 : integer := 0; + coef0_5 : integer := 0; + coef0_6 : integer := 0; + coef0_7 : integer := 0; + + coef1_0 : integer := 0; + coef1_1 : integer := 0; + coef1_2 : integer := 0; + coef1_3 : integer := 0; + coef1_4 : integer := 0; + coef1_5 : integer := 0; + coef1_6 : integer := 0; + coef1_7 : integer := 0; + + coef2_0 : integer := 0; + coef2_1 : integer := 0; + coef2_2 : integer := 0; + coef2_3 : integer := 0; + coef2_4 : integer := 0; + coef2_5 : integer := 0; + coef2_6 : integer := 0; + coef2_7 : integer := 0; + + coef3_0 : integer := 0; + coef3_1 : integer := 0; + coef3_2 : integer := 0; + coef3_3 : integer := 0; + coef3_4 : integer := 0; + coef3_5 : integer := 0; + coef3_6 : integer := 0; + coef3_7 : integer := 0 ); + + port ( + dataa : in std_logic_vector(width_a -1 downto 0) := (others => '0'); + datab : in std_logic_vector(width_b -1 downto 0) := (others => '0'); + scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z'); + scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z'); + accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0'); + sourcea : in std_logic := '1'; + sourceb : in std_logic := '1'; + -- control signals + addnsub : in std_logic := 'Z'; + accum_sload : in std_logic := '0'; + signa : in std_logic := 'Z'; + signb : in std_logic := 'Z'; + -- clock ports + clock0 : in std_logic := '1'; + clock1 : in std_logic := '1'; + clock2 : in std_logic := '1'; + clock3 : in std_logic := '1'; + ena0 : in std_logic := '1'; + ena1 : in std_logic := '1'; + ena2 : in std_logic := '1'; + ena3 : in std_logic := '1'; + aclr0 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + aclr2 : in std_logic := '0'; + aclr3 : in std_logic := '0'; + -- round and saturation ports + mult_round : in std_logic := '0'; + mult_saturation : in std_logic := '0'; + accum_round : in std_logic := '0'; + accum_saturation : in std_logic := '0'; + -- StratixV only input ports + coefsel0 : in std_logic_vector(2 downto 0) := (others => '0'); + coefsel1 : in std_logic_vector(2 downto 0) := (others => '0'); + coefsel2 : in std_logic_vector(2 downto 0) := (others => '0'); + coefsel3 : in std_logic_vector(2 downto 0) := (others => '0'); + -- output ports + result : out std_logic_vector(width_result -1 downto 0); + overflow : out std_logic; + scanouta : out std_logic_vector (width_a -1 downto 0); + scanoutb : out std_logic_vector (width_b -1 downto 0); + mult_is_saturated : out std_logic := '0'; + accum_is_saturated : out std_logic := '0' ); +end component; + +component altaccumulate + generic ( + width_in : integer:= 4; + width_out : integer:= 8; + lpm_representation : string := "UNSIGNED"; + extra_latency : integer:= 0; + use_wys : string := "ON"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altaccumulate" ); + + port ( + -- Input ports + cin : in std_logic := 'Z'; + data : in std_logic_vector(width_in -1 downto 0); -- Required port + add_sub : in std_logic := '1'; + clock : in std_logic; -- Required port + sload : in std_logic := '0'; + clken : in std_logic := '1'; + sign_data : in std_logic := '0'; + aclr : in std_logic := '0'; + + -- Output ports + result : out std_logic_vector(width_out -1 downto 0) := (others => '0'); + cout : out std_logic := '0'; + overflow : out std_logic := '0' ); +end component; + +component altsyncram + generic ( + operation_mode : string := "BIDIR_DUAL_PORT"; + -- port a parameters + width_a : integer := 1; + widthad_a : integer := 1; + numwords_a : integer := 0; + -- registering parameters + -- port a read parameters + outdata_reg_a : string := "UNREGISTERED"; + -- clearing parameters + address_aclr_a : string := "NONE"; + outdata_aclr_a : string := "NONE"; + -- clearing parameters + -- port a write parameters + indata_aclr_a : string := "NONE"; + wrcontrol_aclr_a : string := "NONE"; + -- clear for the byte enable port reigsters which are clocked by clk0 + byteena_aclr_a : string := "NONE"; + -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9 + width_byteena_a : integer := 1; + -- port b parameters + width_b : integer := 1; + widthad_b : integer := 1; + numwords_b : integer := 0; + -- registering parameters + -- port b read parameters + rdcontrol_reg_b : string := "CLOCK1"; + address_reg_b : string := "CLOCK1"; + outdata_reg_b : string := "UNREGISTERED"; + -- clearing parameters + outdata_aclr_b : string := "NONE"; + rdcontrol_aclr_b : string := "NONE"; + -- registering parameters + -- port b write parameters + indata_reg_b : string := "CLOCK1"; + wrcontrol_wraddress_reg_b : string := "CLOCK1"; + -- registering parameter for the byte enable reister for port b + byteena_reg_b : string := "CLOCK1"; + -- clearing parameters + indata_aclr_b : string := "NONE"; + wrcontrol_aclr_b : string := "NONE"; + address_aclr_b : string := "NONE"; + -- clear parameter for byte enable port register + byteena_aclr_b : string := "NONE"; + -- StratixII only : to bypass clock enable or using clock enable + clock_enable_input_a : string := "NORMAL"; + clock_enable_output_a : string := "NORMAL"; + clock_enable_input_b : string := "NORMAL"; + clock_enable_output_b : string := "NORMAL"; + -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9 + width_byteena_b : integer := 1; + -- clock enable setting for the core + clock_enable_core_a : string := "USE_INPUT_CLKEN"; + clock_enable_core_b : string := "USE_INPUT_CLKEN"; + -- read-during-write-same-port setting + read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ"; + read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ"; + -- ECC status ports setting + enable_ecc : string := "FALSE"; + ecc_pipeline_stage_enabled : string := "FALSE"; + + width_eccstatus : integer := 3; + -- global parameters + -- width of a byte for byte enables + byte_size : integer := 0; + read_during_write_mode_mixed_ports: string := "DONT_CARE"; + -- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM" + ram_block_type : string := "AUTO"; + -- determine whether LE support is turned on or off for altsyncram + implement_in_les : string := "OFF"; + -- determine whether RAM would be power up to uninitialized or not + power_up_uninitialized : string := "FALSE"; + + sim_show_memory_data_in_port_b_layout : string := "OFF"; + + -- general operation parameters + init_file : string := "UNUSED"; + init_file_layout : string := "UNUSED"; + maximum_depth : integer := 0; + intended_device_family : string := "Stratix"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altsyncram" ); + port ( + wren_a : in std_logic := '0'; + wren_b : in std_logic := '0'; + rden_a : in std_logic := '1'; + rden_b : in std_logic := '1'; + data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1'); + data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1'); + address_a : in std_logic_vector(widthad_a - 1 downto 0); + address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1'); + + clock0 : in std_logic := '1'; + clock1 : in std_logic := 'Z'; + clocken0 : in std_logic := '1'; + clocken1 : in std_logic := '1'; + clocken2 : in std_logic := '1'; + clocken3 : in std_logic := '1'; + aclr0 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1'); + byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z'); + + addressstall_a : in std_logic := '0'; + addressstall_b : in std_logic := '0'; + + q_a : out std_logic_vector(width_a - 1 downto 0); + q_b : out std_logic_vector(width_b - 1 downto 0); + + eccstatus : out std_logic_vector(width_eccstatus-1 downto 0) := (others => '0') ); +end component; + +component altpll + generic ( + intended_device_family : string := "Stratix" ; + operation_mode : string := "NORMAL" ; + pll_type : string := "AUTO" ; + qualify_conf_done : string := "OFF" ; + compensate_clock : string := "CLK0" ; + scan_chain : string := "LONG"; + primary_clock : string := "inclk0" ; + inclk0_input_frequency : natural; -- required parameter + inclk1_input_frequency : natural := 0; + gate_lock_signal : string := "NO"; + gate_lock_counter : integer := 0; + lock_high : natural := 1; + lock_low : natural := 0; + valid_lock_multiplier : natural := 1; + invalid_lock_multiplier : natural := 5; + switch_over_type : string := "AUTO"; + switch_over_on_lossclk : string := "OFF" ; + switch_over_on_gated_lock : string := "OFF" ; + enable_switch_over_counter : string := "OFF"; + switch_over_counter : natural := 0; + feedback_source : string := "EXTCLK0" ; + bandwidth : natural := 0; + bandwidth_type : string := "UNUSED"; + spread_frequency : natural := 0; + down_spread : string := "0.0"; + self_reset_on_gated_loss_lock : string := "OFF"; + self_reset_on_loss_lock : string := "OFF"; + lock_window_ui : string := "0.05"; + width_clock : natural := 6; + width_phasecounterselect : natural := 4; + charge_pump_current_bits : natural := 9999; + loop_filter_c_bits : natural := 9999; + loop_filter_r_bits : natural := 9999; + scan_chain_mif_file : string := "UNUSED"; + + -- simulation-only parameters + simulation_type : string := "functional"; + source_is_pll : string := "off"; + skip_vco : string := "off"; + + -- internal clock specifications + clk9_multiply_by : natural := 1; + clk8_multiply_by : natural := 1; + clk7_multiply_by : natural := 1; + clk6_multiply_by : natural := 1; + clk5_multiply_by : natural := 1; + clk4_multiply_by : natural := 1; + clk3_multiply_by : natural := 1; + clk2_multiply_by : natural := 1; + clk1_multiply_by : natural := 1; + clk0_multiply_by : natural := 1; + clk9_divide_by : natural := 1; + clk8_divide_by : natural := 1; + clk7_divide_by : natural := 1; + clk6_divide_by : natural := 1; + clk5_divide_by : natural := 1; + clk4_divide_by : natural := 1; + clk3_divide_by : natural := 1; + clk2_divide_by : natural := 1; + clk1_divide_by : natural := 1; + clk0_divide_by : natural := 1; + clk9_phase_shift : string := "0"; + clk8_phase_shift : string := "0"; + clk7_phase_shift : string := "0"; + clk6_phase_shift : string := "0"; + clk5_phase_shift : string := "0"; + clk4_phase_shift : string := "0"; + clk3_phase_shift : string := "0"; + clk2_phase_shift : string := "0"; + clk1_phase_shift : string := "0"; + clk0_phase_shift : string := "0"; + clk5_time_delay : string := "0"; + clk4_time_delay : string := "0"; + clk3_time_delay : string := "0"; + clk2_time_delay : string := "0"; + clk1_time_delay : string := "0"; + clk0_time_delay : string := "0"; + clk9_duty_cycle : natural := 50; + clk8_duty_cycle : natural := 50; + clk7_duty_cycle : natural := 50; + clk6_duty_cycle : natural := 50; + clk5_duty_cycle : natural := 50; + clk4_duty_cycle : natural := 50; + clk3_duty_cycle : natural := 50; + clk2_duty_cycle : natural := 50; + clk1_duty_cycle : natural := 50; + clk0_duty_cycle : natural := 50; + clk2_output_frequency : natural := 0; + clk1_output_frequency : natural := 0; + clk0_output_frequency : natural := 0; + clk9_use_even_counter_mode : string := "OFF"; + clk8_use_even_counter_mode : string := "OFF"; + clk7_use_even_counter_mode : string := "OFF"; + clk6_use_even_counter_mode : string := "OFF"; + clk5_use_even_counter_mode : string := "OFF"; + clk4_use_even_counter_mode : string := "OFF"; + clk3_use_even_counter_mode : string := "OFF"; + clk2_use_even_counter_mode : string := "OFF"; + clk1_use_even_counter_mode : string := "OFF"; + clk0_use_even_counter_mode : string := "OFF"; + clk9_use_even_counter_value : string := "OFF"; + clk8_use_even_counter_value : string := "OFF"; + clk7_use_even_counter_value : string := "OFF"; + clk6_use_even_counter_value : string := "OFF"; + clk5_use_even_counter_value : string := "OFF"; + clk4_use_even_counter_value : string := "OFF"; + clk3_use_even_counter_value : string := "OFF"; + clk2_use_even_counter_value : string := "OFF"; + clk1_use_even_counter_value : string := "OFF"; + clk0_use_even_counter_value : string := "OFF"; + + -- external clock specifications + extclk3_multiply_by : natural := 1; + extclk2_multiply_by : natural := 1; + extclk1_multiply_by : natural := 1; + extclk0_multiply_by : natural := 1; + extclk3_divide_by : natural := 1; + extclk2_divide_by : natural := 1; + extclk1_divide_by : natural := 1; + extclk0_divide_by : natural := 1; + extclk3_phase_shift : string := "0"; + extclk2_phase_shift : string := "0"; + extclk1_phase_shift : string := "0"; + extclk0_phase_shift : string := "0"; + extclk3_time_delay : string := "0"; + extclk2_time_delay : string := "0"; + extclk1_time_delay : string := "0"; + extclk0_time_delay : string := "0"; + extclk3_duty_cycle : natural := 50; + extclk2_duty_cycle : natural := 50; + extclk1_duty_cycle : natural := 50; + extclk0_duty_cycle : natural := 50; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + sclkout0_phase_shift : string := "0"; + sclkout1_phase_shift : string := "0"; + + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 0; + + -- advanced user parameters + vco_min : natural := 0; + vco_max : natural := 0; + vco_center : natural := 0; + pfd_min : natural := 0; + pfd_max : natural := 0; + m_initial : natural := 1; + m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself + n : natural := 1; + m2 : natural := 1; + n2 : natural := 1; + ss : natural := 0; + c0_high : natural := 1; + c1_high : natural := 1; + c2_high : natural := 1; + c3_high : natural := 1; + c4_high : natural := 1; + c5_high : natural := 1; + c6_high : natural := 1; + c7_high : natural := 1; + c8_high : natural := 1; + c9_high : natural := 1; + l0_high : natural := 1; + l1_high : natural := 1; + g0_high : natural := 1; + g1_high : natural := 1; + g2_high : natural := 1; + g3_high : natural := 1; + e0_high : natural := 1; + e1_high : natural := 1; + e2_high : natural := 1; + e3_high : natural := 1; + c0_low : natural := 1; + c1_low : natural := 1; + c2_low : natural := 1; + c3_low : natural := 1; + c4_low : natural := 1; + c5_low : natural := 1; + c6_low : natural := 1; + c7_low : natural := 1; + c8_low : natural := 1; + c9_low : natural := 1; + l0_low : natural := 1; + l1_low : natural := 1; + g0_low : natural := 1; + g1_low : natural := 1; + g2_low : natural := 1; + g3_low : natural := 1; + e0_low : natural := 1; + e1_low : natural := 1; + e2_low : natural := 1; + e3_low : natural := 1; + c0_initial : natural := 1; + c1_initial : natural := 1; + c2_initial : natural := 1; + c3_initial : natural := 1; + c4_initial : natural := 1; + c5_initial : natural := 1; + c6_initial : natural := 1; + c7_initial : natural := 1; + c8_initial : natural := 1; + c9_initial : natural := 1; + l0_initial : natural := 1; + l1_initial : natural := 1; + g0_initial : natural := 1; + g1_initial : natural := 1; + g2_initial : natural := 1; + g3_initial : natural := 1; + e0_initial : natural := 1; + e1_initial : natural := 1; + e2_initial : natural := 1; + e3_initial : natural := 1; + c0_mode : string := "bypass" ; + c1_mode : string := "bypass" ; + c2_mode : string := "bypass" ; + c3_mode : string := "bypass" ; + c4_mode : string := "bypass" ; + c5_mode : string := "bypass" ; + c6_mode : string := "bypass" ; + c7_mode : string := "bypass" ; + c8_mode : string := "bypass" ; + c9_mode : string := "bypass" ; + l0_mode : string := "bypass" ; + l1_mode : string := "bypass" ; + g0_mode : string := "bypass" ; + g1_mode : string := "bypass" ; + g2_mode : string := "bypass" ; + g3_mode : string := "bypass" ; + e0_mode : string := "bypass" ; + e1_mode : string := "bypass" ; + e2_mode : string := "bypass" ; + e3_mode : string := "bypass" ; + c0_ph : natural := 0; + c1_ph : natural := 0; + c2_ph : natural := 0; + c3_ph : natural := 0; + c4_ph : natural := 0; + c5_ph : natural := 0; + c6_ph : natural := 0; + c7_ph : natural := 0; + c8_ph : natural := 0; + c9_ph : natural := 0; + l0_ph : natural := 0; + l1_ph : natural := 0; + g0_ph : natural := 0; + g1_ph : natural := 0; + g2_ph : natural := 0; + g3_ph : natural := 0; + e0_ph : natural := 0; + e1_ph : natural := 0; + e2_ph : natural := 0; + e3_ph : natural := 0; + m_ph : natural := 0; + l0_time_delay : natural := 0; + l1_time_delay : natural := 0; + g0_time_delay : natural := 0; + g1_time_delay : natural := 0; + g2_time_delay : natural := 0; + g3_time_delay : natural := 0; + e0_time_delay : natural := 0; + e1_time_delay : natural := 0; + e2_time_delay : natural := 0; + e3_time_delay : natural := 0; + m_time_delay : natural := 0; + n_time_delay : natural := 0; + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + c5_use_casc_in : string := "off"; + c6_use_casc_in : string := "off"; + c7_use_casc_in : string := "off"; + c8_use_casc_in : string := "off"; + c9_use_casc_in : string := "off"; + m_test_source : integer := 5; + c0_test_source : integer := 5; + c1_test_source : integer := 5; + c2_test_source : integer := 5; + c3_test_source : integer := 5; + c4_test_source : integer := 5; + c5_test_source : integer := 5; + c6_test_source : integer := 5; + c7_test_source : integer := 5; + c8_test_source : integer := 5; + c9_test_source : integer := 5; + extclk3_counter : string := "e3" ; + extclk2_counter : string := "e2" ; + extclk1_counter : string := "e1" ; + extclk0_counter : string := "e0" ; + clk9_counter : string := "c9" ; + clk8_counter : string := "c8" ; + clk7_counter : string := "c7" ; + clk6_counter : string := "c6" ; + clk5_counter : string := "l1" ; + clk4_counter : string := "l0" ; + clk3_counter : string := "g3" ; + clk2_counter : string := "g2" ; + clk1_counter : string := "g1" ; + clk0_counter : string := "g0" ; + enable0_counter : string := "l0"; + enable1_counter : string := "l0"; + charge_pump_current : natural := 2; + loop_filter_r : string := " 1.000000"; + loop_filter_c : natural := 5; + vco_post_scale : natural := 0; + vco_frequency_control : string := "AUTO"; + vco_phase_shift_step : natural := 0; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altpll"; + port_clkena0 : string := "PORT_CONNECTIVITY"; + port_clkena1 : string := "PORT_CONNECTIVITY"; + port_clkena2 : string := "PORT_CONNECTIVITY"; + port_clkena3 : string := "PORT_CONNECTIVITY"; + port_clkena4 : string := "PORT_CONNECTIVITY"; + port_clkena5 : string := "PORT_CONNECTIVITY"; + port_extclkena0 : string := "PORT_CONNECTIVITY"; + port_extclkena1 : string := "PORT_CONNECTIVITY"; + port_extclkena2 : string := "PORT_CONNECTIVITY"; + port_extclkena3 : string := "PORT_CONNECTIVITY"; + port_extclk0 : string := "PORT_CONNECTIVITY"; + port_extclk1 : string := "PORT_CONNECTIVITY"; + port_extclk2 : string := "PORT_CONNECTIVITY"; + port_extclk3 : string := "PORT_CONNECTIVITY"; + port_clkbad0 : string := "PORT_CONNECTIVITY"; + port_clkbad1 : string := "PORT_CONNECTIVITY"; + port_clk0 : string := "PORT_CONNECTIVITY"; + port_clk1 : string := "PORT_CONNECTIVITY"; + port_clk2 : string := "PORT_CONNECTIVITY"; + port_clk3 : string := "PORT_CONNECTIVITY"; + port_clk4 : string := "PORT_CONNECTIVITY"; + port_clk5 : string := "PORT_CONNECTIVITY"; + port_clk6 : string := "PORT_CONNECTIVITY"; + port_clk7 : string := "PORT_CONNECTIVITY"; + port_clk8 : string := "PORT_CONNECTIVITY"; + port_clk9 : string := "PORT_CONNECTIVITY"; + port_scandata : string := "PORT_CONNECTIVITY"; + port_scandataout : string := "PORT_CONNECTIVITY"; + port_scandone : string := "PORT_CONNECTIVITY"; + port_sclkout1 : string := "PORT_CONNECTIVITY"; + port_sclkout0 : string := "PORT_CONNECTIVITY"; + port_activeclock : string := "PORT_CONNECTIVITY"; + port_clkloss : string := "PORT_CONNECTIVITY"; + port_inclk1 : string := "PORT_CONNECTIVITY"; + port_inclk0 : string := "PORT_CONNECTIVITY"; + port_fbin : string := "PORT_CONNECTIVITY"; + port_fbout : string := "PORT_CONNECTIVITY"; + port_pllena : string := "PORT_CONNECTIVITY"; + port_clkswitch : string := "PORT_CONNECTIVITY"; + port_areset : string := "PORT_CONNECTIVITY"; + port_pfdena : string := "PORT_CONNECTIVITY"; + port_scanclk : string := "PORT_CONNECTIVITY"; + port_scanaclr : string := "PORT_CONNECTIVITY"; + port_scanread : string := "PORT_CONNECTIVITY"; + port_scanwrite : string := "PORT_CONNECTIVITY"; + port_enable0 : string := "PORT_CONNECTIVITY"; + port_enable1 : string := "PORT_CONNECTIVITY"; + port_locked : string := "PORT_CONNECTIVITY"; + port_configupdate : string := "PORT_CONNECTIVITY"; + port_phasecounterselect : string := "PORT_CONNECTIVITY"; + port_phasedone : string := "PORT_CONNECTIVITY"; + port_phasestep : string := "PORT_CONNECTIVITY"; + port_phaseupdown : string := "PORT_CONNECTIVITY"; + port_vcooverrange : string := "PORT_CONNECTIVITY"; + port_vcounderrange : string := "PORT_CONNECTIVITY"; + port_scanclkena : string := "PORT_CONNECTIVITY"; + using_fbmimicbidir_port : string := "ON"; + sim_gate_lock_device_behavior : string := "OFF" ); + port ( + inclk : in std_logic_vector(1 downto 0) := (others => '0'); + fbin : in std_logic := '0'; + pllena : in std_logic := '1'; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + clkena : in std_logic_vector(5 downto 0) := (others => '1'); + extclkena : in std_logic_vector(3 downto 0) := (others => '1'); + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + scanaclr : in std_logic := '0'; + scanread : in std_logic := '0'; + scanwrite : in std_logic := '0'; + scandata : in std_logic := '0'; + phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '0'); + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + configupdate : in std_logic := '0'; + fbmimicbidir : inout std_logic := '1'; + clk : out std_logic_vector(width_clock-1 downto 0); + extclk : out std_logic_vector(3 downto 0); + clkbad : out std_logic_vector(1 downto 0); + enable0 : out std_logic; + enable1 : out std_logic; + activeclock : out std_logic; + clkloss : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + sclkout0 : out std_logic; + sclkout1 : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fbout : out std_logic; + fref : out std_logic; + icdrclk : out std_logic ); +end component; + +component altfp_mult + generic ( + width_exp : integer := 11; + width_man : integer := 31; + dedicated_multiplier_circuitry : string := "AUTO"; + reduced_functionality : string := "NO"; + pipeline : natural := 5; + denormal_support : string := "YES"; + exception_handling : string := "YES"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altfp_mult" ); + port ( + clock : in std_logic; + clk_en : in std_logic := '1'; + aclr : in std_logic := '0'; + dataa : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ; + datab : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ; + result : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ; + overflow : out std_logic ; + underflow : out std_logic ; + zero : out std_logic ; + denormal : out std_logic ; + indefinite : out std_logic ; + nan : out std_logic ); +end component; + +component altsqrt + generic ( + q_port_width : integer := 1; + r_port_width : integer := 1; + width : integer := 1; + pipeline : integer := 0; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altsqrt" ); + port ( + radical : in std_logic_vector(width - 1 downto 0) ; + clk : in std_logic := '1'; + ena : in std_logic := '1'; + aclr : in std_logic := '0'; + q : out std_logic_vector( q_port_width - 1 downto 0) ; + remainder : out std_logic_vector( r_port_width - 1 downto 0) ); +end component; + +component parallel_add + generic ( + width : natural := 4; + size : natural := 2; + widthr : natural := 4; + shift : natural := 0; + msw_subtract : string := "NO"; + representation : string := "UNSIGNED"; + pipeline : natural := 0; + result_alignment : string := "LSB"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "parallel_add" ); + port ( + data : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0); + clock : in std_logic := '1'; + aclr : in std_logic := '0'; + clken : in std_logic := '1'; + result : out std_logic_vector(widthr - 1 downto 0) ); +end component; + +component a_graycounter + generic ( + width : natural; + pvalue : natural; + lpm_hint : string := "UNUSED"; + lpm_type : string := "a_graycounter" ); + port ( + clock : in std_logic; + clk_en : in std_logic := '1'; + cnt_en : in std_logic := '1'; + updown : in std_logic := '1'; + aclr : in std_logic := '0'; + sclr : in std_logic := '0'; + qbin : out std_logic_vector(width-1 downto 0); + q : out std_logic_vector(width-1 downto 0) ); +end component; + +component altsquare + generic ( + data_width : natural; + pipeline : natural; + representation : string := "UNSIGNED"; + result_alignment : string := "LSB"; + result_width : natural; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altsquare" + ); + port( + aclr : in std_logic := '0'; + clock : in std_logic := '1'; + data : in std_logic_vector(data_width-1 downto 0); + ena : in std_logic := '1'; + result : out std_logic_vector(result_width-1 downto 0) + ); +end component; + +component sld_virtual_jtag + generic ( + lpm_type : string; + lpm_hint : string; + sld_auto_instance_index : string; + sld_instance_index : integer; + sld_ir_width : integer; + sld_sim_n_scan : integer; + sld_sim_total_length : integer; + sld_sim_action : string); + port ( + tdo : in std_logic := '0'; + ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0'); + tck : out std_logic; + tdi : out std_logic; + ir_in : out std_logic_vector(sld_ir_width - 1 downto 0); + virtual_state_cdr : out std_logic; + virtual_state_sdr : out std_logic; + virtual_state_e1dr : out std_logic; + virtual_state_pdr : out std_logic; + virtual_state_e2dr : out std_logic; + virtual_state_udr : out std_logic; + virtual_state_cir : out std_logic; + virtual_state_uir : out std_logic; + jtag_state_tlr : out std_logic; + jtag_state_rti : out std_logic; + jtag_state_sdrs : out std_logic; + jtag_state_cdr : out std_logic; + jtag_state_sdr : out std_logic; + jtag_state_e1dr : out std_logic; + jtag_state_pdr : out std_logic; + jtag_state_e2dr : out std_logic; + jtag_state_udr : out std_logic; + jtag_state_sirs : out std_logic; + jtag_state_cir : out std_logic; + jtag_state_sir : out std_logic; + jtag_state_e1ir : out std_logic; + jtag_state_pir : out std_logic; + jtag_state_e2ir : out std_logic; + jtag_state_uir : out std_logic; + tms : out std_logic); +end component; + + +component altera_std_synchronizer + generic + ( + depth : integer := 3 + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + din : in std_logic; + dout : out std_logic + ); +end component; + +component altera_std_synchronizer_bundle + generic + ( + depth : integer := 3; + width : integer := 1 + ); + + port + ( + clk : in std_logic; + reset_n : in std_logic; + din : in std_logic_vector(width-1 downto 0); + dout : out std_logic_vector(width-1 downto 0) + ); +end component; + +component alt_cal + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal" + ); + PORT + ( + busy : OUT STD_LOGIC; + cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + start : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0') + ); +end component; + +component alt_cal_av + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal"; + sample_length : integer := 100; + pma_base_address : integer := 0 + ); + PORT + ( + busy : OUT STD_LOGIC; + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + start : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0') + ); +end component; + +component alt_cal_c3gxb + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal_c3gxb" + ); + PORT + ( + busy : OUT STD_LOGIC; + cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + start : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0) := (OTHERS => '0') + ); +end component; + +component alt_cal_mm + generic ( + number_of_channels : integer := 1; + channel_address_width : integer := 1; + sim_model_mode : string := "TRUE"; + CAL_PD_WR : string := "00101"; + CAL_RX_RD : string := "00110"; + CAL_RX_WR : string := "00111"; + CH_ADV : string := "01100"; + CH_WAIT : string := "00001"; + DPRIO_READ : string := "01110"; + DPRIO_WAIT : string := "01000"; + DPRIO_WRITE : string := "01111"; + IDLE : string := "00000"; + KICK_DELAY_OC : integer := 10010; + KICK_PAUSE : integer := 10001; + KICK_START_RD : string := "01101"; + KICK_START_WR : integer := 10000; + OFFSETS_PDEN_RD : string := "00011"; + OFFSETS_PDEN_WR : string := "00100"; + sample_length : string := "01100100"; + SAMPLE_TB : string := "01001"; + TEST_INPUT : string := "01010"; + TESTBUS_SET : string := "00010"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "alt_cal_mm" + ); + PORT + ( + busy : OUT STD_LOGIC; + cal_error : OUT STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0); + clock : IN STD_LOGIC; + dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_busy : IN STD_LOGIC; + dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dprio_rden : OUT STD_LOGIC; + dprio_wren : OUT STD_LOGIC; + quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0'); + reset : IN STD_LOGIC := '0'; + retain_addr : OUT STD_LOGIC; + start : IN STD_LOGIC := '0'; + transceiver_init : IN STD_LOGIC := '0'; + testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0') + ); +END component; + + + + + + + + constant SLD_IR_BITS : natural := 10; + +component sld_signaltap + generic ( + SLD_USE_JTAG_SIGNAL_ADAPTER : natural := 1; + SLD_CURRENT_RESOURCE_WIDTH : natural := 0; + SLD_INVERSION_MASK : std_logic_vector := "0"; + SLD_POWER_UP_TRIGGER : natural := 0; + SLD_ADVANCED_TRIGGER_6 : string := "NONE"; + SLD_ADVANCED_TRIGGER_9 : string := "NONE"; + SLD_ADVANCED_TRIGGER_7 : string := "NONE"; + SLD_HPS_EVENT_ENABLED : natural := 0; + SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : string := "basic"; + SLD_STORAGE_QUALIFIER_GAP_RECORD : natural := 0; + SLD_SECTION_ID : string := "hdl_signaltap_0"; + SLD_INCREMENTAL_ROUTING : natural := 0; + SLD_STORAGE_QUALIFIER_PIPELINE : natural := 0; + SLD_TRIGGER_IN_ENABLED : natural := 0; + SLD_STATE_BITS : natural := 11; + SLD_HPS_EVENT_ID : natural := 0; + SLD_CREATE_MONITOR_INTERFACE : natural := 0; + SLD_STATE_FLOW_USE_GENERATED : natural := 0; + SLD_INVERSION_MASK_LENGTH : integer := 1; + SLD_DATA_BITS : natural := 1; + SLD_BUFFER_FULL_STOP : natural := 1; + SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : natural := 0; + SLD_ATTRIBUTE_MEM_MODE : string := "OFF"; + SLD_STORAGE_QUALIFIER_MODE : string := "OFF"; + SLD_STATE_FLOW_MGR_ENTITY : string := "state_flow_mgr_entity.vhd"; + SLD_HPS_TRIGGER_IN_ENABLED : natural := 0; + SLD_NODE_CRC_LOWORD : natural := 50132; + SLD_ADVANCED_TRIGGER_5 : string := "NONE"; + SLD_TRIGGER_BITS : natural := 1; + SLD_STORAGE_QUALIFIER_BITS : natural := 1; + SLD_HPS_TRIGGER_OUT_ENABLED : natural := 0; + SLD_ADVANCED_TRIGGER_10 : string := "NONE"; + SLD_MEM_ADDRESS_BITS : natural := 7; + SLD_ADVANCED_TRIGGER_ENTITY : string := "basic"; + SLD_ADVANCED_TRIGGER_4 : string := "NONE"; + SLD_ADVANCED_TRIGGER_8 : string := "NONE"; + SLD_TRIGGER_LEVEL : natural := 10; + SLD_RAM_BLOCK_TYPE : string := "AUTO"; + SLD_ADVANCED_TRIGGER_2 : string := "NONE"; + SLD_ADVANCED_TRIGGER_1 : string := "NONE"; + SLD_DATA_BIT_CNTR_BITS : natural := 4; + SLD_SAMPLE_DEPTH : natural := 16; + lpm_type : string := "sld_signaltap"; + SLD_NODE_CRC_BITS : natural := 32; + SLD_ENABLE_ADVANCED_TRIGGER : natural := 0; + SLD_SEGMENT_SIZE : natural := 0; + SLD_NODE_INFO : natural := 0; + SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : natural := 0; + SLD_NODE_CRC_HIWORD : natural := 41394; + SLD_TRIGGER_LEVEL_PIPELINE : natural := 1; + SLD_ADVANCED_TRIGGER_3 : string := "NONE" + ); + port ( + jtag_state_sdr : in std_logic := '0'; + ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0'); + acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0); + gnd : out std_logic; + jtag_state_cir : in std_logic := '0'; + jtag_state_e2ir : in std_logic := '0'; + jtag_state_pir : in std_logic := '0'; + jtag_state_udr : in std_logic := '0'; + vcc : out std_logic; + jtag_state_e1dr : in std_logic := '0'; + jtag_state_rti : in std_logic := '0'; + jtag_state_e1ir : in std_logic := '0'; + jtag_state_pdr : in std_logic := '0'; + acq_clk : in std_logic; + clr : in std_logic := '0'; + trigger_in : in std_logic := '0'; + ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0); + jtag_state_sirs : in std_logic := '0'; + jtag_state_cdr : in std_logic := '0'; + jtag_state_sir : in std_logic := '0'; + jtag_state_e2dr : in std_logic := '0'; + tms : in std_logic := '0'; + jtag_state_tlr : in std_logic := '0'; + jtag_state_sdrs : in std_logic := '0'; + tdi : in std_logic := '0'; + jtag_state_uir : in std_logic := '0'; + acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0'); + trigger_out : out std_logic; + storage_enable : in std_logic := '0'; + acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0); + acq_storage_qualifier_in : in std_logic_vector(SLD_STORAGE_QUALIFIER_BITS-1 downto 0) := (others => '0'); + acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0'); + tdo : out std_logic; + crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0'); + clrn : in std_logic := '0'; + raw_tck : in std_logic := '0'; + irq : out std_logic; + usr1 : in std_logic := '0'; + ena : in std_logic := '0' + ); +end component; --sld_signaltap + + +component altstratixii_oct + generic ( + lpm_type : string := "altstratixii_oct" + ); + port ( + terminationenable : in std_logic; + terminationclock : in std_logic; + rdn : in std_logic; + rup : in std_logic + ); +end component; --altstratixii_oct + + constant PFL_QUAD_IO_FLASH_IR_BITS : NATURAL := 8; + constant PFL_CFI_FLASH_IR_BITS : NATURAL := 5; + constant PFL_NAND_FLASH_IR_BITS : NATURAL := 4; + constant N_FLASH_BITS : NATURAL := 4; + +component altparallel_flash_loader + generic ( + flash_data_width : NATURAL := 16; + dclk_create_delay : NATURAL := 0; + flash_burst_extra_cycle : NATURAL := 0; + safe_mode_retry : NATURAL := 1; + us_unit_counter : NATURAL := 1; + burst_mode_numonyx : NATURAL := 0; + burst_mode : NATURAL := 0; + clk_divisor : NATURAL := 1; + addr_width : NATURAL := 20; + tristate_checkbox : NATURAL := 0; + nflash_mfc : STRING := "NUMONYX"; + safe_mode_revert_addr : NATURAL := 0; + flash_static_wait_width : NATURAL := 15; + page_mode : NATURAL := 0; + flash_ecc_checkbox : NATURAL := 0; + features_pgm : NATURAL := 1; + BURST_MODE_LATENCY_COUNT : NATURAL := 4; + auto_restart : STRING := "OFF"; + page_clk_divisor : NATURAL := 1; + safe_mode_halt : NATURAL := 0; + flash_nreset_counter : NATURAL := 1; + normal_mode : NATURAL := 1; + safe_mode_revert : NATURAL := 0; + fifo_size : NATURAL := 16; + nrb_addr : NATURAL := 65667072; + nand_size : NATURAL := 67108864; + dclk_divisor : NATURAL := 1; + rsu_watchdog_counter : NATURAL := 100000000; + flash_nreset_checkbox : NATURAL := 0; + flash_type : STRING := "CFI_FLASH"; + features_cfg : NATURAL := 1; + burst_mode_intel : NATURAL := 0; + extra_addr_byte : NATURAL := 0; + qspi_data_delay : NATURAL := 0; + option_bits_start_address : NATURAL := 0; + pfl_rsu_watchdog_enabled : NATURAL := 0; + qflash_fast_speed : NATURAL := 0; + enhanced_flash_programming : NATURAL := 0; + qspi_data_delay_count : NATURAL := 1; + conf_wait_timer_width : NATURAL := 16; + lpm_type : STRING := "ALTPARALLEL_FLASH_LOADER"; + n_flash : NATURAL := 1; + disable_crc_checkbox : NATURAL := 0; + burst_mode_spansion : NATURAL := 0; + qflash_mfc : STRING := "ALTERA"; + decompressor_mode : STRING := "NONE"; + conf_data_width : NATURAL := 1 + ); + port ( + flash_nce : out std_logic_vector(n_flash-1 downto 0); + fpga_data : out std_logic_vector(conf_data_width-1 downto 0); + fpga_dclk : out std_logic; + fpga_nstatus : in std_logic := '0'; + flash_ale : out std_logic; + pfl_clk : in std_logic := '0'; + fpga_nconfig : out std_logic; + flash_io2 : inout std_logic_vector(n_flash-1 downto 0); + flash_sck : out std_logic_vector(n_flash-1 downto 0); + flash_noe : out std_logic; + flash_nwe : out std_logic; + pfl_watchdog_error : out std_logic; + pfl_reset_watchdog : in std_logic := '0'; + fpga_conf_done : in std_logic := '0'; + flash_rdy : in std_logic := '1'; + pfl_flash_access_granted : in std_logic := '0'; + pfl_nreconfigure : in std_logic := '1'; + flash_cle : out std_logic; + flash_nreset : out std_logic; + flash_io0 : inout std_logic_vector(n_flash-1 downto 0); + pfl_nreset : in std_logic := '0'; + flash_data : inout std_logic_vector(flash_data_width-1 downto 0); + flash_io1 : inout std_logic_vector(n_flash-1 downto 0); + flash_nadv : out std_logic; + flash_clk : out std_logic; + flash_io3 : inout std_logic_vector(n_flash-1 downto 0); + flash_io : inout std_logic_vector(7 downto 0); + flash_addr : out std_logic_vector(addr_width-1 downto 0); + pfl_flash_access_request : out std_logic; + flash_ncs : out std_logic_vector(n_flash-1 downto 0); + fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0') + ); +end component; --altparallel_flash_loader + + +component altserial_flash_loader + generic ( + enhanced_mode : natural := 0; + intended_device_family : STRING := "Cyclone"; + enable_shared_access : STRING := "OFF"; + enable_quad_spi_support : natural := 0; + ncso_width : natural := 1; + lpm_type : STRING := "ALTSERIAL_FLASH_LOADER" + ); + port ( + data_in : in std_logic_vector(3 downto 0) := (others => '0'); + noe : in std_logic := '0'; + asmi_access_granted : in std_logic := '1'; + data_out : out std_logic_vector(3 downto 0); + data_oe : in std_logic_vector(3 downto 0) := (others => '0'); + sdoin : in std_logic := '0'; + asmi_access_request : out std_logic; + data0out : out std_logic; + scein : in std_logic_vector(ncso_width-1 downto 0) := (others => '0'); + dclkin : in std_logic := '0' + ); +end component; --altserial_flash_loader + + +component sld_virtual_jtag_basic + generic ( + lpm_hint : string := "UNUSED"; + sld_sim_action : string := "UNUSED"; + sld_instance_index : natural := 0; + sld_ir_width : natural := 1; + sld_sim_n_scan : natural := 0; + sld_mfg_id : natural := 0; + sld_version : natural := 0; + sld_type_id : natural := 0; + lpm_type : string := "sld_virtual_jtag_basic"; + sld_auto_instance_index : string := "NO"; + sld_sim_total_length : natural := 0 + ); + port ( + jtag_state_sdr : out std_logic; + jtag_state_sirs : out std_logic; + ir_out : in std_logic_vector(sld_ir_width-1 downto 0); + jtag_state_sir : out std_logic; + jtag_state_cdr : out std_logic; + jtag_state_e2dr : out std_logic; + tms : out std_logic; + jtag_state_sdrs : out std_logic; + jtag_state_tlr : out std_logic; + ir_in : out std_logic_vector(sld_ir_width-1 downto 0); + virtual_state_sdr : out std_logic; + tdi : out std_logic; + jtag_state_uir : out std_logic; + jtag_state_cir : out std_logic; + virtual_state_cdr : out std_logic; + virtual_state_uir : out std_logic; + virtual_state_e2dr : out std_logic; + jtag_state_e2ir : out std_logic; + virtual_state_cir : out std_logic; + jtag_state_pir : out std_logic; + jtag_state_udr : out std_logic; + virtual_state_udr : out std_logic; + tdo : in std_logic; + jtag_state_e1dr : out std_logic; + jtag_state_rti : out std_logic; + virtual_state_pdr : out std_logic; + virtual_state_e1dr : out std_logic; + jtag_state_e1ir : out std_logic; + jtag_state_pdr : out std_logic; + tck : out std_logic + ); +end component; --sld_virtual_jtag_basic + + +component altsource_probe + generic ( + lpm_hint : string := "UNUSED"; + sld_instance_index : natural := 0; + source_initial_value : string := "0"; + sld_ir_width : natural := 4; + probe_width : natural := 1; + source_width : natural := 1; + instance_id : string := "UNUSED"; + lpm_type : string := "altsource_probe"; + sld_auto_instance_index : string := "YES"; + SLD_NODE_INFO : natural := 4746752; + enable_metastability : string := "NO" + ); + port ( + source_clk : in std_logic; + probe : in std_logic_vector(probe_width-1 downto 0); + source : out std_logic_vector(source_width-1 downto 0); + source_ena : in std_logic + ); +end component; --altsource_probe + +end altera_mf_components; diff --git a/Common/sim/altera/altera_primitives_components.vhd b/Common/sim/altera/altera_primitives_components.vhd new file mode 100644 index 0000000..5ca7a08 --- /dev/null +++ b/Common/sim/altera/altera_primitives_components.vhd @@ -0,0 +1,436 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 + +---------------------------------------------------------------------------- +-- ALtera Primitives Component Declaration File +---------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +package dffeas_pack is + +-- default generic values + CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns); + CONSTANT DefSetupHoldCnst : TIME := 0 ns; + CONSTANT DefPulseWdthCnst : TIME := 0 ns; + CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport; + CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE; + CONSTANT DefGlitchXOn : BOOLEAN := FALSE; + CONSTANT DefMsgOnChecks : BOOLEAN := TRUE; + CONSTANT DefXOnChecks : BOOLEAN := TRUE; + +end dffeas_pack; + +library ieee; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use work.dffeas_pack.all; + +package altera_primitives_components is + +component carry + port ( + a_in : in std_logic; + a_out : out std_logic ); +end component; + +component cascade + port ( + a_in : in std_logic; + a_out : out std_logic ); +end component; + +component global + port ( + a_in : in std_logic; + a_out : out std_logic); +end component; + +component tri + port( + a_in : in std_logic; + oe : in std_logic; + a_out : out std_logic); +end component; + +component carry_sum + port ( + sin : in std_logic; + cin : in std_logic; + sout : out std_logic; + cout : out std_logic ); +end component; + +component exp + port ( + a_in : in std_logic; + a_out : out std_logic); +end component; + +component soft + port ( + a_in : in std_logic; + a_out : out std_logic ); +end component; + +component opndrn + port ( + a_in : in std_logic; + a_out : out std_logic ); +end component; + +component row_global + port ( + a_in : in std_logic; + a_out : out std_logic ); +end component; + +component lut_input + port( + a_in : in std_logic; + a_out : out std_logic); +end component; + +component lut_output + port( + a_in : in std_logic; + a_out : out std_logic); +end component; + +component dlatch + port( + d : in std_logic; + ena : in std_logic; + clrn : in std_logic; + prn : in std_logic; + q : out std_logic); +end component; + +component latch + port( + d : in std_logic; + ena : in std_logic; + q : out std_logic); +end component; + +component dff + port( + d, clk, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component dffe + port( + d, clk, ena, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component dffea + port( + d, clk, ena, clrn, prn, aload, adata : in std_logic; + q : out std_logic); +end component; + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + dont_touch : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic ); +end component; + +component tff + port( + t, clk, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component tffe + port( + t, clk, ena, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component jkff + port( + j, k, clk, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component jkffe + port( + j, k, clk, ena, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component srff + port( + s, r, clk, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component srffe + port( + s, r, clk, ena, clrn, prn : in std_logic; + q : out std_logic); +end component; + +component clklock + generic( + input_frequency : natural := 10000; + clockboost : natural := 1); + + port( + inclk : in std_logic; + outclk : out std_logic); +end component; + +component alt_inbuf + generic( + io_standard : string := "NONE"; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + lpm_type : string := "alt_inbuf" ); + + port( + i : in std_logic; + o : out std_logic); +end component; + +component alt_outbuf + generic( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + slow_slew_rate : string := "NONE"; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + lpm_type : string := "alt_outbuf" ); + + port( + i : in std_logic; + o : out std_logic); +end component; + +component alt_outbuf_tri + generic( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + slow_slew_rate : string := "NONE"; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + lpm_type : string := "alt_outbuf_tri" ); + + port( + i : in std_logic; + oe : in std_logic; + o : out std_logic); +end component; + +component alt_iobuf + generic( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + slow_slew_rate : string := "NONE"; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + input_termination : string := "NONE"; + output_termination : string := "NONE"; + lpm_type : string := "alt_iobuf" ); + + port( + i : in std_logic; + oe : in std_logic; + io : inout std_logic; + o : out std_logic); +end component; + +component alt_inbuf_diff + generic( + io_standard : string := "NONE"; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + lpm_type : string := "alt_inbuf_diff" ); + + port( + i : in std_logic; + ibar : in std_logic; + o : out std_logic); +end component; + +component alt_outbuf_diff + generic ( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + lpm_type : string := "alt_outbuf_diff" ); + + port( + i : in std_logic; + o : out std_logic; + obar : out std_logic ); +end component; + +component alt_outbuf_tri_diff + generic ( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + lpm_type : string := "alt_outbuf_tri_diff" ); + port( + i : in std_logic; + oe : in std_logic; + o : out std_logic; + obar : out std_logic ); +end component; + +component alt_iobuf_diff + generic ( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + input_termination : string := "NONE"; + output_termination : string := "NONE"; + lpm_type : string := "alt_iobuf_diff" ); + port( + i : in std_logic; + oe : in std_logic; + io : inout std_logic; + iobar : inout std_logic; + o : out std_logic ); +end component; + +component alt_bidir_diff + generic ( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + input_termination : string := "NONE"; + output_termination : string := "NONE"; + lpm_type : string := "alt_bidir_diff" ); + port( + oe : in std_logic; + bidirin : inout std_logic; + io : inout std_logic; + iobar : inout std_logic ); +end component; + +component alt_bidir_buf + generic ( + io_standard : string := "NONE"; + current_strength : string := "NONE"; + current_strength_new : string := "NONE"; + slew_rate : integer := -1; + location : string := "NONE"; + enable_bus_hold : string := "NONE"; + weak_pull_up_resistor : string := "NONE"; + termination : string := "NONE"; + input_termination : string := "NONE"; + output_termination : string := "NONE"; + lpm_type : string := "alt_bidir_buf" ); + port( + oe : in std_logic; + bidirin : inout std_logic; + io : inout std_logic ); +end component; + +end altera_primitives_components; + diff --git a/Common/sim/altera/altera_standard_functions.vhd b/Common/sim/altera/altera_standard_functions.vhd new file mode 100644 index 0000000..a0e9bb4 --- /dev/null +++ b/Common/sim/altera/altera_standard_functions.vhd @@ -0,0 +1,46 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 +library std; +use std.standard.all; + +package altera_standard_functions is + + function maximum (L, R: integer) return integer; + function minimum (L, R: integer) return integer; + +end altera_standard_functions; + +package body altera_standard_functions is + + function maximum (L, R: integer) return integer is + begin + if L > R then + return L; + else + return R; + end if; + end maximum; + + function minimum (L, R: integer) return integer is + begin + if L > R then + return R; + else + return L; + end if; + end minimum; + +end altera_standard_functions; diff --git a/Common/sim/altera/altera_syn_attributes.vhd b/Common/sim/altera/altera_syn_attributes.vhd new file mode 100644 index 0000000..a991796 --- /dev/null +++ b/Common/sim/altera/altera_syn_attributes.vhd @@ -0,0 +1,95 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 +----------------------------------------------------------------------------- +-- -- +-- Copyright (c) 2006 by Altera Corp. All rights reserved. -- +-- -- +-- -- +-- Description: Package containing Attribute Declarations for all -- +-- attributes that control Quartus II Integrated Synthesis. -- +-- Please refer to the Quartus II Help for documentation -- +-- on using these attributes. -- +-- -- +-- -- +----------------------------------------------------------------------------- + +library std; +use std.standard.all; + + +PACKAGE altera_syn_attributes is + + -- Directs Quartus II to implement input, output, and output + -- enable registers in I/O cells that have fast, direct connections to + -- an I/O pin, when possible + ATTRIBUTE useioff : BOOLEAN; + + -- Prevents Quartus II from minimizing or removing a register + ATTRIBUTE preserve : BOOLEAN; + + -- Prevents Quartus II from removing a dangling register + ATTRIBUTE noprune : BOOLEAN; + + -- Prevents Quartus II from merging a register with a duplicate + ATTRIBUTE dont_merge : BOOLEAN; + + -- Prevents Quartus II from replicating a register to improve timing + ATTRIBUTE dont_replicate : BOOLEAN; + + -- Prevents Quartus II from retiming a register + ATTRIBUTE dont_retime : BOOLEAN; + + -- Identifies the critical clock enable signal for a register. The + -- Quartus II software will attempt to connect this signal to the + -- dedicated clock enable port. + ATTRIBUTE direct_enable : BOOLEAN; + + -- Prevents Quartus II from minimizing or removing a particular + -- signal net during combinational logic optimization + ATTRIBUTE keep : BOOLEAN; + + -- Sets a fan-out limit on a register or net. + ATTRIBUTE maxfan : NATURAL; + + -- Controls the implementation of a multiplication (*) operations in VHDL + ATTRIBUTE multstyle : STRING; + + -- Controls the implementation of inferred memories + ATTRIBUTE ramstyle : STRING; + + -- Controls the implementation of inferred ROMs + ATTRIBUTE romstyle : STRING; + + -- Specifies a Memory Initialization File (.mif) for an inferred RAM + ATTRIBUTE ram_init_file : STRING; + + -- Assigns a logic encoding to an enumerated type. Prevents state + -- machine extraction for all objects with the enumerated type. + ATTRIBUTE enum_encoding : STRING; + + -- Assigns a state encoding to an enumerated type that models the states + -- of an extracted state machine. + ATTRIBUTE syn_encoding : STRING; + + -- Specifies device pin assignments for a VHDL entity port + ATTRIBUTE chip_pin : STRING; + + -- Applies an arbitrary number of Quartus Settings File (QSF) assignments + -- to a signal, entity, architecture, instance, or inferred register + ATTRIBUTE altera_attribute : STRING; + +END altera_syn_attributes; + diff --git a/Common/sim/altera/cycloneiv_atoms.vhd b/Common/sim/altera/cycloneiv_atoms.vhd new file mode 100644 index 0000000..6c84e4d --- /dev/null +++ b/Common/sim/altera/cycloneiv_atoms.vhd @@ -0,0 +1,8906 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +package cycloneiv_atom_pack is + +function str_to_bin (lut_mask : string ) return std_logic_vector; + +function product(list : std_logic_vector) return std_logic ; + +function alt_conv_integer(arg : in std_logic_vector) return integer; + + +-- default generic values + CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns); + CONSTANT DefSetupHoldCnst : TIME := 0 ns; + CONSTANT DefPulseWdthCnst : TIME := 0 ns; +-- default control options +-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent; +-- change default delay type to Transport : for spr 68748 + CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport; + CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE; + CONSTANT DefGlitchXOn : BOOLEAN := FALSE; + CONSTANT DefMsgOnChecks : BOOLEAN := TRUE; + CONSTANT DefXOnChecks : BOOLEAN := TRUE; +-- output strength mapping + -- UX01ZWHL- + CONSTANT PullUp : VitalOutputMapType := "UX01HX01X"; + CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X"; + CONSTANT PullDown : VitalOutputMapType := "UX01LX01X"; +-- primitive result strength mapping + CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' ); + CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' ); + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) + +-- Declare array types for CAM_SLICE + TYPE cycloneiv_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0); + +function int2str( value : integer ) return string; + +function map_x_to_0 (value : std_logic) return std_logic; + +function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME; + +function int2bit (arg : boolean) return std_logic; +function int2bit (arg : integer) return std_logic; +function bin2int (s : bit_vector) return integer; +function bin2int (s : bit) return integer; +function bin2int (s : std_logic_vector) return integer; +function bin2int (s : std_logic) return integer; +function int2bin (arg : integer; size : integer) return std_logic_vector; +function int2bin (arg : boolean; size : integer) return std_logic_vector; +function calc_sum_len( widtha : integer; widthb : integer) return integer; + +end cycloneiv_atom_pack; + +library IEEE; +use IEEE.std_logic_1164.all; + +package body cycloneiv_atom_pack is + +type masklength is array (4 downto 1) of std_logic_vector(3 downto 0); +function str_to_bin (lut_mask : string) return std_logic_vector is +variable slice : masklength := (OTHERS => "0000"); +variable mask : std_logic_vector(15 downto 0); + + +begin + + for i in 1 to lut_mask'length loop + case lut_mask(i) is + when '0' => slice(i) := "0000"; + when '1' => slice(i) := "0001"; + when '2' => slice(i) := "0010"; + when '3' => slice(i) := "0011"; + when '4' => slice(i) := "0100"; + when '5' => slice(i) := "0101"; + when '6' => slice(i) := "0110"; + when '7' => slice(i) := "0111"; + when '8' => slice(i) := "1000"; + when '9' => slice(i) := "1001"; + when 'a' => slice(i) := "1010"; + when 'A' => slice(i) := "1010"; + when 'b' => slice(i) := "1011"; + when 'B' => slice(i) := "1011"; + when 'c' => slice(i) := "1100"; + when 'C' => slice(i) := "1100"; + when 'd' => slice(i) := "1101"; + when 'D' => slice(i) := "1101"; + when 'e' => slice(i) := "1110"; + when 'E' => slice(i) := "1110"; + when others => slice(i) := "1111"; + end case; + end loop; + + + mask := (slice(1) & slice(2) & slice(3) & slice(4)); + return (mask); + +end str_to_bin; + +function product (list: std_logic_vector) return std_logic is +begin + + for i in 0 to 31 loop + if list(i) = '0' then + return ('0'); + end if; + end loop; + return ('1'); + +end product; + +function alt_conv_integer(arg : in std_logic_vector) return integer is +variable result : integer; +begin + result := 0; + for i in arg'range loop + if arg(i) = '1' then + result := result + 2**i; + end if; + end loop; + return result; +end alt_conv_integer; + +function int2str( value : integer ) return string is +variable ivalue,index : integer; +variable digit : integer; +variable line_no: string(8 downto 1) := " "; +begin + ivalue := value; + index := 1; + if (ivalue = 0) then + line_no := " 0"; + end if; + while (ivalue > 0) loop + digit := ivalue MOD 10; + ivalue := ivalue/10; + case digit is + when 0 => + line_no(index) := '0'; + when 1 => + line_no(index) := '1'; + when 2 => + line_no(index) := '2'; + when 3 => + line_no(index) := '3'; + when 4 => + line_no(index) := '4'; + when 5 => + line_no(index) := '5'; + when 6 => + line_no(index) := '6'; + when 7 => + line_no(index) := '7'; + when 8 => + line_no(index) := '8'; + when 9 => + line_no(index) := '9'; + when others => + ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + index := index + 1; + end loop; + return line_no; +end; + +function map_x_to_0 (value : std_logic) return std_logic is +begin + if (Is_X (value) = TRUE) then + return '0'; + else + return value; + end if; +end; + +function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS + +variable Temp : TIME; +variable TransitionTime : TIME := TIME'HIGH; +variable PathDelay : TIME := TIME'HIGH; + +begin + + for i IN Paths'RANGE loop + next when not Paths(i).PathCondition; + + next when Paths(i).InputChangeTime > TransitionTime; + + Temp := Paths(i).PathDelay(tr01); + + if Paths(i).InputChangeTime < TransitionTime then + PathDelay := Temp; + else + if Temp < PathDelay then + PathDelay := Temp; + end if; + end if; + TransitionTime := Paths(i).InputChangeTime; + end loop; + + return PathDelay; + +end; + +function int2bit (arg : integer) return std_logic is + variable int_val : integer := arg; + variable result : std_logic; + begin + + if (int_val = 0) then + result := '0'; + else + result := '1'; + end if; + + return result; +end int2bit; + +function int2bit (arg : boolean) return std_logic is + variable int_val : boolean := arg; + variable result : std_logic; + begin + + if (int_val ) then + result := '1'; + else + result := '0'; + end if; + + return result; +end int2bit; + +function bin2int (s : bit_vector) return integer is + + constant temp : bit_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : bit) return integer is + constant temp : bit := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + +function bin2int (s : std_logic_vector) return integer is + + constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : std_logic) return integer is + constant temp : std_logic := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + +function int2bin (arg : boolean; size : integer) return std_logic_vector is + variable result : std_logic_vector(size-1 downto 0); + begin + if(arg)then + result := (OTHERS => '1'); + else + result := (OTHERS => '0'); + end if; + return result; + end int2bin; + +function calc_sum_len( widtha : integer; widthb : integer) return integer is +variable result: integer; +begin + if(widtha >= widthb) then + result := widtha + 1; + else + result := widthb + 1; + end if; + return result; +end calc_sum_len; + +end cycloneiv_atom_pack; + +Library ieee; +use ieee.std_logic_1164.all; + +Package cycloneiv_pllpack is + + + procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer); + + procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ); + + function gcd (X: integer; Y: integer) return integer; + + function count_digit (X: integer) return integer; + + function scale_num (X: integer; Y: integer) return integer; + + function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) return integer; + + function output_counter_value (clk_divide: integer; clk_mult : integer ; + M: integer; N: integer ) return integer; + + function counter_mode (duty_cycle: integer; output_counter_value: integer) return string; + + function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer; + + function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer; + + function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function counter_time_delay ( clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer; + + function get_phase_degree (phase_shift: integer; clk_period: integer) return integer; + + function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer; + + function counter_ph (tap_phase: integer; m : integer; n: integer) return integer; + + function ph_adjust (tap_phase: integer; ph_base : integer) return integer; + + function translate_string (mode : string) return string; + + function str2int (s : string) return integer; + + function dqs_str2int (s : string) return integer; + +end cycloneiv_pllpack; + +package body cycloneiv_pllpack is + + +-- finds the closest integer fraction of a given pair of numerator and denominator. +procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer) is + constant MAX_ITER : integer := 20; + type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer; + + variable quotient_array : INT_ARRAY; + variable int_loop_iter : integer; + variable int_quot : integer; + variable m_value : integer; + variable d_value : integer; + variable old_m_value : integer; + variable swap : integer; + variable loop_iter : integer; + variable num : integer; + variable den : integer; + variable i_max_iter : integer; + +begin + loop_iter := 0; + + if (numerator = 0) then + num := 1; + else + num := numerator; + end if; + + if (denominator = 0) then + den := 1; + else + den := denominator; + end if; + + i_max_iter := max_iter; + + while (loop_iter < i_max_iter) loop + int_quot := num / den; + quotient_array(loop_iter) := int_quot; + num := num - (den*int_quot); + loop_iter := loop_iter+1; + + if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then + -- calculate the numerator and denominator if there is a restriction on the + -- max denom value or if the loop is ending + m_value := 0; + d_value := 1; + -- get the rounded value at this stage for the remaining fraction + if (den /= 0) then + m_value := (2*num/den); + end if; + -- calculate the fraction numerator and denominator at this stage + for int_loop_iter in (loop_iter-1) downto 0 loop + if (m_value = 0) then + m_value := quotient_array(int_loop_iter); + d_value := 1; + else + old_m_value := m_value; + m_value := (quotient_array(int_loop_iter)*m_value) + d_value; + d_value := old_m_value; + end if; + end loop; + -- if the denominator is less than the maximum denom_value or if there is no restriction save it + if ((d_value <= max_denom) or (max_denom = -1)) then + if ((m_value = 0) or (d_value = 0)) then + fraction_num := numerator; + fraction_div := denominator; + else + fraction_num := m_value; + fraction_div := d_value; + end if; + end if; + -- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round) + if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then + i_max_iter := loop_iter; + end if; + end if; + -- swap the numerator and denominator for the next round + swap := den; + den := num; + num := swap; + end loop; +end find_simple_integer_fraction; + +-- find the M and N values for Manual phase based on the following 5 criterias: +-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz +-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz +-- 3. M is less than 512 +-- 4. N is less than 512 +-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps +-- of the desired vco-phase-shift-step +procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ) is + constant MAX_M : integer := 511; + constant MAX_N : integer := 511; + constant MAX_PFD : integer := 720; + constant MIN_PFD : integer := 5; + constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz) + constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz) + constant MAX_OFFSET : real := 0.004; + + variable vco_period : integer; + variable pfd_freq : integer; + variable vco_freq : integer; + variable vco_ps_step_value : integer; + + variable i_m : integer; + variable i_n : integer; + + variable i_pre_m : integer; + variable i_pre_n : integer; + + variable closest_vco_step_value : integer; + + variable i_max_iter : integer; + variable loop_iter : integer; + + variable clk0_div_factor_real : real; + variable clk1_div_factor_real : real; + variable clk2_div_factor_real : real; + variable clk3_div_factor_real : real; + variable clk4_div_factor_real : real; + variable clk5_div_factor_real : real; + variable clk6_div_factor_real : real; + variable clk7_div_factor_real : real; + variable clk8_div_factor_real : real; + variable clk9_div_factor_real : real; + variable clk0_div_factor_int : integer; + variable clk1_div_factor_int : integer; + variable clk2_div_factor_int : integer; + variable clk3_div_factor_int : integer; + variable clk4_div_factor_int : integer; + variable clk5_div_factor_int : integer; + variable clk6_div_factor_int : integer; + variable clk7_div_factor_int : integer; + variable clk8_div_factor_int : integer; + variable clk9_div_factor_int : integer; +begin + vco_period := vco_phase_shift_step * 8; + i_pre_m := 0; + i_pre_n := 0; + closest_vco_step_value := 0; + + LOOP_1 : for i_n_out in 1 to MAX_N loop + for i_m_out in 1 to MAX_M loop + + clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out); + clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out); + clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out); + clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out); + clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out); + clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out); + clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out); + clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out); + clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out); + clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out); + + clk0_div_factor_int := integer(clk0_div_factor_real); + clk1_div_factor_int := integer(clk1_div_factor_real); + clk2_div_factor_int := integer(clk2_div_factor_real); + clk3_div_factor_int := integer(clk3_div_factor_real); + clk4_div_factor_int := integer(clk4_div_factor_real); + clk5_div_factor_int := integer(clk5_div_factor_real); + clk6_div_factor_int := integer(clk6_div_factor_real); + clk7_div_factor_int := integer(clk7_div_factor_real); + clk8_div_factor_int := integer(clk8_div_factor_real); + clk9_div_factor_int := integer(clk9_div_factor_real); + + if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and + ((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and + ((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and + ((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and + ((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and + ((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and + ((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and + ((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and + ((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and + ((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) ) + then + if ((i_m_out /= 0) and (i_n_out /= 0)) + then + pfd_freq := 1000000 / (inclock_period * i_n_out); + vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out); + vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out); + + if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and + (vco_freq >= min_vco) and (vco_freq <= max_vco) ) + then + if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + exit LOOP_1; + else + if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + closest_vco_step_value := vco_ps_step_value; + end if; + end if; + end if; + end if; + end if; + end loop; + end loop; + + if ((i_pre_m /= 0) and (i_pre_n /= 0)) + then + find_simple_integer_fraction(i_pre_m, i_pre_n, + MAX_N, m, n); + else + n := 1; + m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult, + clk4_mult, clk5_mult, clk6_mult, + clk7_mult, clk8_mult, clk9_mult, inclock_period); + end if; +end find_m_and_n_4_manual_phase; + +-- find the greatest common denominator of X and Y +function gcd (X: integer; Y: integer) return integer is +variable L, S, R, G : integer := 1; +begin + if (X < Y) then -- find which is smaller. + S := X; + L := Y; + else + S := Y; + L := X; + end if; + + R := S; + while ( R > 1) loop + S := L; + L := R; + R := S rem L; -- divide bigger number by smaller. + -- remainder becomes smaller number. + end loop; + if (R = 0) then -- if evenly divisible then L is gcd else it is 1. + G := L; + else + G := R; + end if; + + return G; +end gcd; + +-- count the number of digits in the given integer +function count_digit (X: integer) + return integer is +variable count, result: integer := 0; +begin + result := X; + while (result /= 0) loop + result := (result / 10); + count := count + 1; + end loop; + + return count; +end count_digit; + +-- reduce the given huge number to Y significant digits +function scale_num (X: integer; Y: integer) + return integer is +variable count : integer := 0; +variable lc, fac_ten, result: integer := 1; +begin + count := count_digit(X); + + for lc in 1 to (count-Y) loop + fac_ten := fac_ten * 10; + end loop; + + result := (X / fac_ten); + + return result; +end scale_num; + +-- find the least common multiple of A1 to A10 +function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) + return integer is +variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1; +begin + M1 := (A1 * A2)/gcd(A1, A2); + M2 := (M1 * A3)/gcd(M1, A3); + M3 := (M2 * A4)/gcd(M2, A4); + M4 := (M3 * A5)/gcd(M3, A5); + M5 := (M4 * A6)/gcd(M4, A6); + M6 := (M5 * A7)/gcd(M5, A7); + M7 := (M6 * A8)/gcd(M6, A8); + M8 := (M7 * A9)/gcd(M7, A9); + M9 := (M8 * A10)/gcd(M8, A10); + if (M9 < 3) then + R := 10; + elsif (M9 = 3) then + R := 9; + elsif ((M9 <= 10) and (M9 > 3)) then + R := 4 * M9; + elsif (M9 > 1000) then + R := scale_num(M9,3); + else + R := M9 ; + end if; + + return R; +end lcm; + +-- find the factor of division of the output clock frequency compared to the VCO +function output_counter_value (clk_divide: integer; clk_mult: integer ; + M: integer; N: integer ) return integer is +variable r_real : real := 1.0; +variable r: integer := 1; +begin + r_real := real(clk_divide * M)/ real(clk_mult * N); + r := integer(r_real); + + return R; +end output_counter_value; + +-- find the mode of each PLL counter - bypass, even or odd +function counter_mode (duty_cycle: integer; output_counter_value: integer) + return string is +variable R: string (1 to 6) := " "; +variable counter_value: integer := 1; +begin + counter_value := (2*duty_cycle*output_counter_value)/100; + if output_counter_value = 1 then + R := "bypass"; + elsif (counter_value REM 2) = 0 then + R := " even"; + else + R := " odd"; + end if; + + return R; +end counter_mode; + +-- find the number of VCO clock cycles to hold the output clock high +function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer is +variable R: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value *2)/100 ; + if (half_cycle_high REM 2 = 0) then + R := half_cycle_high/2 ; + else + R := (half_cycle_high/2) + 1; + end if; + + return R; +end; + +-- find the number of VCO clock cycles to hold the output clock low +function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer is +variable R, R1: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value*2)/100 ; + if (half_cycle_high REM 2 = 0) then + R1 := half_cycle_high/2 ; + else + R1 := (half_cycle_high/2) + 1; + end if; + + R := output_counter_value - R1; + + if (R = 0) then + R := 1; + end if; + + return R; +end; + +-- find the smallest time delay amongst t1 to t10 +function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 > 0) then return m9; else return 0; end if; +end; + +-- find the numerically largest negative number, and return its absolute value +function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 < 0) then return (0 - m9); else return 0; end if; +end; + +-- adjust the phase (tap_phase) with the largest negative number (ph_base) +function ph_adjust (tap_phase: integer; ph_base : integer) return integer is +begin + return (tap_phase + ph_base); +end; + +-- find the time delay for each PLL counter +function counter_time_delay (clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer is +variable R: integer := 0; +begin + R := clk_time_delay + m_time_delay - n_time_delay; + + return R; +end; + +-- calculate the given phase shift (in ps) in terms of degrees +function get_phase_degree (phase_shift: integer; clk_period: integer) + return integer is +variable result: integer := 0; +begin + result := ( phase_shift * 360 ) / clk_period; + -- to round up the calculation result + if (result > 0) then + result := result + 1; + elsif (result < 0) then + result := result - 1; + else + result := 0; + end if; + + return result; +end; + +-- find the number of VCO clock cycles to wait initially before the first rising +-- edge of the output clock +function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer is +variable R: integer; +variable R1: real; +begin + R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6; + -- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99. + -- This checking will ensure that the rounding up is done. + if (R1 >= 0.5) and (R1 <= 1.0) then + R1 := 1.0; + end if; + + R := integer(R1); + + return R; +end; + +-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to +function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is +variable R: integer := 0; +begin + -- 0.5 is added for proper rounding of the tap_phase. + R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8; + + return R; +end; + +-- convert given string to length 6 by padding with spaces +function translate_string (mode : string) return string is +variable new_mode : string (1 to 6) := " "; +begin + if (mode = "bypass") then + new_mode := "bypass"; + elsif (mode = "even") then + new_mode := " even"; + elsif (mode = "odd") then + new_mode := " odd"; + end if; + + return new_mode; +end; + +function str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "i n string parameter! " + SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; + +function dqs_str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +variable err : boolean := false; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & " in string parameter! " + SEVERITY ERROR; + err := true; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + -- set error flag + err := true; + end case; + if (err) then + err := false; + else + newdigit := newdigit * 10 + digit; + end if; + end loop; + + return (sign*newdigit); +end; + +end cycloneiv_pllpack; + +-- +-- +-- DFFE Model +-- +-- + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_dffe is + generic( + TimingChecksOn: Boolean := True; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tipd_D : VitalDelayType01 := DefPropDelay01; + tipd_CLRN : VitalDelayType01 := DefPropDelay01; + tipd_PRN : VitalDelayType01 := DefPropDelay01; + tipd_CLK : VitalDelayType01 := DefPropDelay01; + tipd_ENA : VitalDelayType01 := DefPropDelay01); + + port( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC; + CLRN : in STD_LOGIC; + PRN : in STD_LOGIC; + CLK : in STD_LOGIC; + ENA : in STD_LOGIC); + attribute VITAL_LEVEL0 of cycloneiv_dffe : entity is TRUE; +end cycloneiv_dffe; + +-- architecture body -- + +architecture behave of cycloneiv_dffe is + attribute VITAL_LEVEL0 of behave : architecture is TRUE; + + signal D_ipd : STD_ULOGIC := 'U'; + signal CLRN_ipd : STD_ULOGIC := 'U'; + signal PRN_ipd : STD_ULOGIC := 'U'; + signal CLK_ipd : STD_ULOGIC := 'U'; + signal ENA_ipd : STD_ULOGIC := 'U'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN); + VitalWireDelay (PRN_ipd, PRN, tipd_PRN); + VitalWireDelay (CLK_ipd, CLK, tipd_CLK); + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd) + + -- timing check results + VARIABLE Tviol_D_CLK : STD_ULOGIC := '0'; + VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0'; + VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit; + VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7); + VARIABLE D_delayed : STD_ULOGIC := 'U'; + VARIABLE CLK_delayed : STD_ULOGIC := 'U'; + VARIABLE ENA_delayed : STD_ULOGIC := 'U'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0'); + + -- output glitch detection variables + VARIABLE Q_VitalGlitchData : VitalGlitchDataType; + + + CONSTANT dffe_Q_tab : VitalStateTableType := ( + ( L, L, x, x, x, x, x, x, x, L ), + ( L, H, L, H, H, x, x, H, x, H ), + ( L, H, L, H, x, L, x, H, x, H ), + ( L, H, L, x, H, H, x, H, x, H ), + ( L, H, H, x, x, x, H, x, x, S ), + ( L, H, x, x, x, x, L, x, x, H ), + ( L, H, x, x, x, x, H, L, x, S ), + ( L, x, L, L, L, x, H, H, x, L ), + ( L, x, L, L, x, L, H, H, x, L ), + ( L, x, L, x, L, H, H, H, x, L ), + ( L, x, x, x, x, x, x, x, x, S )); + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_CLK, + TimingData => TimingData_D_CLK, + TestSignal => D_ipd, + TestSignalName => "D", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_D_CLK_noedge_posedge, + SetupLow => tsetup_D_CLK_noedge_posedge, + HoldHigh => thold_D_CLK_noedge_posedge, + HoldLow => thold_D_CLK_noedge_posedge, + CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/DFFE", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLK, + TimingData => TimingData_ENA_CLK, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ENA_CLK_noedge_posedge, + SetupLow => tsetup_ENA_CLK_noedge_posedge, + HoldHigh => thold_ENA_CLK_noedge_posedge, + HoldLow => thold_ENA_CLK_noedge_posedge, + CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/DFFE", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_CLK or Tviol_ENA_CLK; + VitalStateTable( + StateTable => dffe_Q_tab, + DataIn => ( + Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd), + Result => Results, + NumStates => 1, + PreviousDataIn => PrevData_Q); + D_delayed := D_ipd; + CLK_delayed := CLK_ipd; + ENA_delayed := ENA_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + OutSignalName => "Q", + OutTemp => Results(1), + Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE), + 1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE), + 2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)), + GlitchData => Q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; + +-- +-- +-- cycloneiv_mux21 Model +-- +-- + +LIBRARY IEEE; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_mux21 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic); + attribute VITAL_LEVEL0 of cycloneiv_mux21 : entity is TRUE; +end cycloneiv_mux21; + +architecture AltVITAL of cycloneiv_mux21 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + signal A_ipd, B_ipd, S_ipd : std_logic; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (A_ipd, A, tipd_A); + VitalWireDelay (B_ipd, B, tipd_B); + VitalWireDelay (S_ipd, S, tipd_S); + end block; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (A_ipd, B_ipd, S_ipd) + + -- output glitch detection variables + VARIABLE MO_GlitchData : VitalGlitchDataType; + + variable tmp_MO : std_logic; + begin + ------------------------- + -- Functionality Section + ------------------------- + if (S_ipd = '1') then + tmp_MO := B_ipd; + else + tmp_MO := A_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => MO, + OutSignalName => "MO", + OutTemp => tmp_MO, + Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE), + 1 => (B_ipd'last_event, tpd_B_MO, TRUE), + 2 => (S_ipd'last_event, tpd_S_MO, TRUE)), + GlitchData => MO_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; + +-- +-- +-- cycloneiv_mux41 Model +-- +-- + +LIBRARY IEEE; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_mux41 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_IN0_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN1_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN2_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN3_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_IN0 : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01; + tipd_IN2 : VitalDelayType01 := DefPropDelay01; + tipd_IN3 : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01) + ); + port ( + IN0 : in std_logic := '0'; + IN1 : in std_logic := '0'; + IN2 : in std_logic := '0'; + IN3 : in std_logic := '0'; + S : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + MO : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneiv_mux41 : entity is TRUE; +end cycloneiv_mux41; + +architecture AltVITAL of cycloneiv_mux41 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic; + signal S_ipd : std_logic_vector(1 downto 0); + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (IN0_ipd, IN0, tipd_IN0); + VitalWireDelay (IN1_ipd, IN1, tipd_IN1); + VitalWireDelay (IN2_ipd, IN2, tipd_IN2); + VitalWireDelay (IN3_ipd, IN3, tipd_IN3); + VitalWireDelay (S_ipd(0), S(0), tipd_S(0)); + VitalWireDelay (S_ipd(1), S(1), tipd_S(1)); + end block; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1)) + + -- output glitch detection variables + VARIABLE MO_GlitchData : VitalGlitchDataType; + + variable tmp_MO : std_logic; + begin + ------------------------- + -- Functionality Section + ------------------------- + if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then + tmp_MO := IN3_ipd; + elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then + tmp_MO := IN2_ipd; + elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then + tmp_MO := IN1_ipd; + else + tmp_MO := IN0_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => MO, + OutSignalName => "MO", + OutTemp => tmp_MO, + Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE), + 1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE), + 2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE), + 3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE), + 4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE), + 5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)), + GlitchData => MO_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; + +-- +-- +-- cycloneiv_and1 Model +-- +-- +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneiv_atom_pack.all; + +-- entity declaration -- +entity cycloneiv_and1 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01); + + port( + Y : out STD_LOGIC; + IN1 : in STD_LOGIC); + attribute VITAL_LEVEL0 of cycloneiv_and1 : entity is TRUE; +end cycloneiv_and1; + +-- architecture body -- + +architecture AltVITAL of cycloneiv_and1 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + SIGNAL IN1_ipd : STD_ULOGIC := 'U'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (IN1_ipd, IN1, tipd_IN1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (IN1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS Y_zd : STD_ULOGIC is Results(1); + + -- output glitch detection variables + VARIABLE Y_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + Y_zd := TO_X01(IN1_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Y, + OutSignalName => "Y", + OutTemp => Y_zd, + Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)), + GlitchData => Y_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_lcell_comb +-- +-- Description : Cyclone II LCELL_COMB VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_lcell_comb is + generic ( + lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1'); + sum_lutc_input : string := "datac"; + dont_touch : string := "off"; + lpm_type : string := "cycloneiv_lcell_comb"; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; + tpd_datab_combout : VitalDelayType01 := DefPropDelay01; + tpd_datac_combout : VitalDelayType01 := DefPropDelay01; + tpd_datad_combout : VitalDelayType01 := DefPropDelay01; + tpd_cin_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; + tpd_datab_cout : VitalDelayType01 := DefPropDelay01; + tpd_datac_cout : VitalDelayType01 := DefPropDelay01; + tpd_datad_cout : VitalDelayType01 := DefPropDelay01; + tpd_cin_cout : VitalDelayType01 := DefPropDelay01; + tipd_dataa : VitalDelayType01 := DefPropDelay01; + tipd_datab : VitalDelayType01 := DefPropDelay01; + tipd_datac : VitalDelayType01 := DefPropDelay01; + tipd_datad : VitalDelayType01 := DefPropDelay01; + tipd_cin : VitalDelayType01 := DefPropDelay01 + ); + + port ( + dataa : in std_logic := '1'; + datab : in std_logic := '1'; + datac : in std_logic := '1'; + datad : in std_logic := '1'; + cin : in std_logic := '0'; + combout : out std_logic; + cout : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneiv_lcell_comb : entity is TRUE; +end cycloneiv_lcell_comb; + +architecture vital_lcell_comb of cycloneiv_lcell_comb is + attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE; + signal dataa_ipd : std_logic; + signal datab_ipd : std_logic; + signal datac_ipd : std_logic; + signal datad_ipd : std_logic; + signal cin_ipd : std_logic; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (dataa_ipd, dataa, tipd_dataa); + VitalWireDelay (datab_ipd, datab, tipd_datab); + VitalWireDelay (datac_ipd, datac, tipd_datac); + VitalWireDelay (datad_ipd, datad, tipd_datad); + VitalWireDelay (cin_ipd, cin, tipd_cin); + end block; + +VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, + cin_ipd) + +variable combout_VitalGlitchData : VitalGlitchDataType; +variable cout_VitalGlitchData : VitalGlitchDataType; +-- output variables +variable combout_tmp : std_logic; +variable cout_tmp : std_logic; + +begin + + -- lut_mask_var := lut_mask; + + ------------------------ + -- Timing Check Section + ------------------------ + + if (sum_lutc_input = "datac") then + -- combout + combout_tmp := VitalMUX(data => lut_mask, + dselect => (datad_ipd, + datac_ipd, + datab_ipd, + dataa_ipd)); + elsif (sum_lutc_input = "cin") then + -- combout + combout_tmp := VitalMUX(data => lut_mask, + dselect => (datad_ipd, + cin_ipd, + datab_ipd, + dataa_ipd)); + end if; + + -- cout + cout_tmp := VitalMUX(data => lut_mask, + dselect => ('0', + cin_ipd, + datab_ipd, + dataa_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + + VitalPathDelay01 ( + OutSignal => combout, + OutSignalName => "COMBOUT", + OutTemp => combout_tmp, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_combout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_combout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_combout, TRUE), + 4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)), + GlitchData => combout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => cout, + OutSignalName => "COUT", + OutTemp => cout_tmp, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_cout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_cout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_cout, TRUE), + 4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)), + GlitchData => cout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + +end process; + +end vital_lcell_comb; + + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_routing_wire +-- +-- Description : Cyclone IV GX Routing Wire VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_routing_wire is + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneiv_routing_wire : entity is TRUE; +end cycloneiv_routing_wire; + +ARCHITECTURE behave of cycloneiv_routing_wire is +attribute VITAL_LEVEL0 of behave : architecture is TRUE; +signal datain_ipd : std_logic; +signal datainglitch_inert : std_logic; +begin + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (datain_ipd, datain, tipd_datain); + end block; + + VITAL: process(datain_ipd, datainglitch_inert) + variable datain_inert_VitalGlitchData : VitalGlitchDataType; + variable dataout_VitalGlitchData : VitalGlitchDataType; + + begin + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => datainglitch_inert, + OutSignalName => "datainglitch_inert", + OutTemp => datain_ipd, + Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)), + GlitchData => datain_inert_VitalGlitchData, + Mode => VitalInertial, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => dataout, + OutSignalName => "dataout", + OutTemp => datainglitch_inert, + Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_ff +-- +-- Description : Cyclone IV GX FF VHDL simulation model +-- +-- +--------------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; +use work.cycloneiv_and1; + +entity cycloneiv_ff is + generic ( + power_up : string := "low"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneiv_ff"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + clrn : in std_logic := '1'; + aload : in std_logic := '0'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + ena : in std_logic := '1'; + asdata : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneiv_ff : entity is TRUE; +end cycloneiv_ff; + +architecture vital_lcell_ff of cycloneiv_ff is + attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE; + signal clk_ipd : std_logic; + signal d_ipd : std_logic; + signal d_dly : std_logic; + signal asdata_ipd : std_logic; + signal asdata_dly : std_logic; + signal asdata_dly1 : std_logic; + signal sclr_ipd : std_logic; + signal sload_ipd : std_logic; + signal clrn_ipd : std_logic; + signal aload_ipd : std_logic; + signal ena_ipd : std_logic; + +component cycloneiv_and1 + generic (XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01 + ); + + port (Y : out STD_LOGIC; + IN1 : in STD_LOGIC + ); +end component; + +begin + +ddelaybuffer: cycloneiv_and1 + port map(IN1 => d_ipd, + Y => d_dly); + +asdatadelaybuffer: cycloneiv_and1 + port map(IN1 => asdata_ipd, + Y => asdata_dly); + +asdatadelaybuffer1: cycloneiv_and1 + port map(IN1 => asdata_dly, + Y => asdata_dly1); + + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (asdata_ipd, asdata, tipd_asdata); + VitalWireDelay (sclr_ipd, sclr, tipd_sclr); + VitalWireDelay (sload_ipd, sload, tipd_sload); + VitalWireDelay (clrn_ipd, clrn, tipd_clrn); + VitalWireDelay (aload_ipd, aload, tipd_aload); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + VITALtiming : process (clk_ipd, d_dly, asdata_dly1, + sclr_ipd, sload_ipd, clrn_ipd, aload_ipd, + ena_ipd, devclrn, devpor) + + variable Tviol_d_clk : std_ulogic := '0'; + variable Tviol_asdata_clk : std_ulogic := '0'; + variable Tviol_sclr_clk : std_ulogic := '0'; + variable Tviol_sload_clk : std_ulogic := '0'; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + + variable iq : std_logic := '0'; + variable idata: std_logic := '0'; + + -- variables for 'X' generation + variable violation : std_logic := '0'; + + begin + + if (now = 0 ns) then + if (power_up = "low") then + iq := '0'; + elsif (power_up = "high") then + iq := '1'; + end if; + end if; + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_clk, + TimingData => TimingData_d_clk, + TestSignal => d, + TestSignalName => "DATAIN", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (sload_ipd) OR + (sclr_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_asdata_clk, + TimingData => TimingData_asdata_clk, + TestSignal => asdata_ipd, + TestSignalName => "ASDATA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_asdata_clk_noedge_posedge, + SetupLow => tsetup_asdata_clk_noedge_posedge, + HoldHigh => thold_asdata_clk_noedge_posedge, + HoldLow => thold_asdata_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT sload_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_sclr_clk, + TimingData => TimingData_sclr_clk, + TestSignal => sclr_ipd, + TestSignalName => "SCLR", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_sclr_clk_noedge_posedge, + SetupLow => tsetup_sclr_clk_noedge_posedge, + HoldHigh => thold_sclr_clk_noedge_posedge, + HoldLow => thold_sclr_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_sload_clk, + TimingData => TimingData_sload_clk, + TestSignal => sload_ipd, + TestSignalName => "SLOAD", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_sload_clk_noedge_posedge, + SetupLow => tsetup_sload_clk_noedge_posedge, + HoldHigh => thold_sload_clk_noedge_posedge, + HoldLow => thold_sload_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena_ipd, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) ) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + violation := Tviol_d_clk or Tviol_asdata_clk or + Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk; + + + if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then + iq := '0'; + elsif (aload_ipd = '1') then + iq := asdata_dly1; + elsif (violation = 'X' and x_on_violation = "on") then + iq := 'X'; + elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then + if (ena_ipd = '1') then + if (sclr_ipd = '1') then + iq := '0'; + elsif (sload_ipd = '1') then + iq := asdata_dly1; + else + iq := d_dly; + end if; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => iq, + Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE), + 1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE), + 2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE), + 3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end vital_lcell_ff; + +---------------------------------------------------------------------------- +-- Module Name : cycloneiv_ram_register +-- Description : Register module for RAM inputs/outputs +---------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_ram_register IS + +GENERIC ( + width : INTEGER := 1; + preset : STD_LOGIC := '0'; + tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_stall : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst + ); + +PORT ( + d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + clk : IN STD_LOGIC; + ena : IN STD_LOGIC; + stall : IN STD_LOGIC; + aclr : IN STD_LOGIC; + devclrn : IN STD_LOGIC; + devpor : IN STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + aclrout : OUT STD_LOGIC + ); + +END cycloneiv_ram_register; + +ARCHITECTURE reg_arch OF cycloneiv_ram_register IS + +SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0); +SIGNAL clk_ipd : STD_LOGIC; +SIGNAL ena_ipd : STD_LOGIC; +SIGNAL aclr_ipd : STD_LOGIC; + SIGNAL stall_ipd : STD_LOGIC; + +BEGIN + +WireDelay : BLOCK +BEGIN + loopbits : FOR i in d'RANGE GENERATE + VitalWireDelay (d_ipd(i), d(i), tipd_d(i)); + END GENERATE; + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (stall_ipd, stall, tipd_stall); +END BLOCK; + + PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor) +VARIABLE Tviol_clk_ena : STD_ULOGIC := '0'; +VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0'; +VARIABLE Tviol_data_clk : STD_ULOGIC := '0'; +VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit; + VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit; +VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit; +VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit; +VARIABLE Tviol_ena : STD_ULOGIC := '0'; +VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit; +VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0); +VARIABLE CQDelay : TIME := 0 ns; +VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset); +BEGIN + + IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN + q_reg := (OTHERS => preset); + ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN + q_reg := d_ipd; + END IF; + + -- Timing checks + VitalSetupHoldCheck ( + Violation => Tviol_clk_ena, + TimingData => TimingData_clk_ena, + TestSignal => ena_ipd, + TestSignalName => "ena", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_clk_ena, + TimingData => TimingData_clk_stall, + TestSignal => stall_ipd, + TestSignalName => "stall", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_stall_clk_noedge_posedge, + SetupLow => tsetup_stall_clk_noedge_posedge, + HoldHigh => thold_stall_clk_noedge_posedge, + HoldLow => thold_stall_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_clk_aclr, + TimingData => TimingData_clk_aclr, + TestSignal => aclr_ipd, + TestSignalName => "aclr", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_aclr_clk_noedge_posedge, + SetupLow => tsetup_aclr_clk_noedge_posedge, + HoldHigh => thold_aclr_clk_noedge_posedge, + HoldLow => thold_aclr_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_data_clk, + TimingData => TimingData_data_clk, + TestSignal => d_ipd, + TestSignalName => "data", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalPeriodPulseCheck ( + Violation => Tviol_ena, + PeriodData => PeriodData_ena, + TestSignal => ena_ipd, + TestSignalName => "ena", + PulseWidthHigh => tpw_ena_posedge, + HeaderMsg => "/RAM Register VitalPeriodPulseCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + -- Path Delay Selection + CQDelay := SelectDelay ( + Paths => ( + (0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE), + 1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE)) + ) + ); + q <= TRANSPORT q_reg AFTER CQDelay; + +END PROCESS; + +aclrout <= aclr_ipd; + +END reg_arch; + +---------------------------------------------------------------------------- +-- Module Name : cycloneiv_ram_pulse_generator +-- Description : Generate pulse to initiate memory read/write operations +---------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_ram_pulse_generator IS +GENERIC ( + tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns); + tipd_ena : VitalDelayType01 := DefPropDelay01; + tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01 + ); +PORT ( + clk,ena : IN STD_LOGIC; +delaywrite : IN STD_LOGIC := '0'; + pulse,cycle : OUT STD_LOGIC + ); +ATTRIBUTE VITAL_Level0 OF cycloneiv_ram_pulse_generator:ENTITY IS TRUE; +END cycloneiv_ram_pulse_generator; + +ARCHITECTURE pgen_arch OF cycloneiv_ram_pulse_generator IS +SIGNAL clk_ipd,ena_ipd : STD_LOGIC; +SIGNAL state : STD_LOGIC; +ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE; +BEGIN + +WireDelay : BLOCK +BEGIN + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (ena_ipd, ena, tipd_ena); +END BLOCK; + +PROCESS (clk_ipd,state) +BEGIN + IF (state = '1' AND state'EVENT) THEN + state <= '0'; + ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN + IF (delaywrite = '1') THEN + state <= '1' AFTER 1 NS; -- delayed write + ELSE + state <= '1'; + END IF; + END IF; +END PROCESS; + +PathDelay : PROCESS +VARIABLE pulse_VitalGlitchData : VitalGlitchDataType; +BEGIN + WAIT UNTIL state'EVENT; + VitalPathDelay01 ( + OutSignal => pulse, + OutSignalName => "pulse", + OutTemp => state, + Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)), + GlitchData => pulse_VitalGlitchData, + Mode => DefGlitchMode, + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks + ); +END PROCESS; + +cycle <= clk_ipd; + +END pgen_arch; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneiv_atom_pack.all; +USE work.cycloneiv_ram_register; +USE work.cycloneiv_ram_pulse_generator; + +ENTITY cycloneiv_ram_block IS + GENERIC ( + -- -------- GLOBAL PARAMETERS --------- + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock: STRING := "clock1"; + port_b_read_enable_clock: STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + safe_write : STRING := "err_on_2clk"; + init_file_restructured : STRING := "unused"; + lpm_type : string := "cycloneiv_ram_block"; + lpm_hint : string := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : BIT_VECTOR := X"0"; + mem_init1 : BIT_VECTOR := X"0"; + mem_init2 : BIT_VECTOR := X"0"; + mem_init3 : BIT_VECTOR := X"0"; + mem_init4 : BIT_VECTOR := X"0"; + connectivity_checking : string := "off" + ); + -- -------- PORT DECLARATIONS --------- + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); + +END cycloneiv_ram_block; + +ARCHITECTURE block_arch OF cycloneiv_ram_block IS + +COMPONENT cycloneiv_ram_pulse_generator + PORT ( + clk : IN STD_LOGIC; + ena : IN STD_LOGIC; + delaywrite : IN STD_LOGIC := '0'; + pulse : OUT STD_LOGIC; + cycle : OUT STD_LOGIC + ); +END COMPONENT; + +COMPONENT cycloneiv_ram_register + GENERIC ( + preset : STD_LOGIC := '0'; + width : integer := 1 + ); + PORT ( + d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + clk : IN STD_LOGIC; + aclr : IN STD_LOGIC; + devclrn : IN STD_LOGIC; + devpor : IN STD_LOGIC; + ena : IN STD_LOGIC; + stall : IN STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + aclrout : OUT STD_LOGIC + ); +END COMPONENT; + +FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS +VARIABLE c: INTEGER; +BEGIN + IF (condition) THEN c := a; ELSE c := b; END IF; + RETURN c; +END; + +SUBTYPE port_type IS BOOLEAN; + +CONSTANT primary : port_type := TRUE; +CONSTANT secondary : port_type := FALSE; + +CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width); +CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a; + +CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom"); +CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port"); +CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port"); +CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port"); + +CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1) + AND (port_a_data_width /= port_b_data_width); +CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1, + cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width)))); +CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width); +CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width); + +CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width); +CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width); + +CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width; +CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width; + +CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED"); +CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED"); + +CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0'); +CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0'); + + CONSTANT ram_type : BOOLEAN := FALSE; + +TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC; +CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0'); + +-- Hardware write modes + +CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR + operation_mode = "bidir_dual_port") AND + (port_b_address_clock = "clock1"); +CONSTANT both_new_data_same_port : BOOLEAN := ( + ((port_a_read_during_write_mode = "new_data_no_nbe_read") OR + (port_a_read_during_write_mode = "dont_care")) AND + ((port_b_read_during_write_mode = "new_data_no_nbe_read") OR + (port_b_read_during_write_mode = "dont_care")) + ); +SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1); +SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1); + +SIGNAL delay_write_pulse_a : STD_LOGIC ; +SIGNAL delay_write_pulse_b : STD_LOGIC ; + +CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read"); +CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read"); + +CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data"); +CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data"); + +SIGNAL read_before_write_a : BOOLEAN; +SIGNAL read_before_write_b : BOOLEAN; + +-- -------- internal signals --------- +SIGNAL portadatain_int : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL portaaddr_int : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0); +SIGNAL portabyteenamasks_int : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0); +SIGNAL portbdatain_int : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL portbaddr_int : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0); +SIGNAL portbbyteenamasks_int : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0); + SIGNAL portaaddrstall_int : STD_LOGIC; + SIGNAL portbaddrstall_int : STD_LOGIC; +-- clock / clock enable +SIGNAL clk_a_in,clk_b_in : STD_LOGIC; +SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC; +SIGNAL clk_a_out,clk_b_out : STD_LOGIC; +SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC; +SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC; +SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC; + +SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC; +SIGNAL clk_a_core : STD_LOGIC; + +SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC; +SIGNAL clk_b_core : STD_LOGIC; + +SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0); + +-- asynch clear +TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; +TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC; +SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC; +SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC; +SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC; +SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type; +SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type; + SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC; + SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type; + SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type; + + +SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC; +SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC; +SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC; +SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC; +SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC; +SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC; +SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC; +SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type; +SIGNAL clear_asserted_during_write : clear_vec_type; + + +-- port A registers +SIGNAL we_a_reg : STD_LOGIC; +SIGNAL re_a_reg : STD_LOGIC; +SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type; +SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type; +SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0); +SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0); +-- port B registers +SIGNAL we_b_reg, re_b_reg : STD_LOGIC; +SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type; +SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0); +SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0); +-- pulses +TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC; +SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec; +SIGNAL rw_pulse : pulse_vec; +SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC; +SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC; +SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC; +SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC; +-- registered address +SIGNAL addr_prime_reg,addr_sec_reg : INTEGER; +-- input/output +SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); +SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0); +-- overlapping location write +SIGNAL dual_write : BOOLEAN; +-- byte enable mask write +TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; +SIGNAL be_mask_write : be_mask_write_vec; +-- memory core +SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0); +SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0); +TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type; +TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type; +SIGNAL mem : mem_type; +SIGNAL init_mem : BOOLEAN := FALSE; +CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X'))); +CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X')); +CONSTANT col_x : mem_col_type := (OTHERS => 'X'); +SIGNAL mem_data : mem_row_type; +SIGNAL old_mem_data : mem_row_type; +SIGNAL mem_unit_data : mem_col_type; + +-- latches +TYPE read_latch_rec IS RECORD + prime : mem_row_type; + sec : mem_col_type; +END RECORD; +SIGNAL read_latch : read_latch_rec; +-- (row,column) coordinates +SIGNAL row_sec,col_sec : INTEGER; +-- byte enable +TYPE mask_type IS (normal,inverse); +TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type; +TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type; +TYPE mask_rec IS RECORD + prime : mask_prime_type; + sec : mask_sec_type; +END RECORD; +SIGNAL mask_vector : mask_rec; +SIGNAL mask_vector_common : mem_col_type; + +FUNCTION get_mask( + b_ena : IN STD_LOGIC_VECTOR; + mode : port_type; + CONSTANT b_ena_width ,byte_size: INTEGER +) RETURN mask_rec IS + +VARIABLE l : INTEGER; +VARIABLE mask : mask_rec := ( + (normal => (OTHERS => '0'),inverse => (OTHERS => 'X')), + (normal => (OTHERS => '0'),inverse => (OTHERS => 'X')) + ); +BEGIN + FOR l in 0 TO b_ena_width - 1 LOOP + IF (b_ena(l) = '0') THEN + IF (mode = primary) THEN + mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0'); + ELSE + mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0'); + END IF; + ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN + IF (mode = primary) THEN + mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + ELSE + mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + END IF; + END IF; + END LOOP; + RETURN mask; +END get_mask; +-- port active for read/write +SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type; +SIGNAL active_a_in,active_b_in : STD_LOGIC; +SIGNAL active_write_a : BOOLEAN; +SIGNAL active_write_b : BOOLEAN; +SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC; +SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC; +SIGNAL active_a_core, active_b_core : BOOLEAN; +SIGNAL wire_vcc : STD_LOGIC := '1'; +SIGNAL wire_gnd : STD_LOGIC := '0'; + + + + + + +BEGIN + -- memory initialization + init_mem <= TRUE; + -- hardware write modes + hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR + (port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE + " FW" WHEN (dual_clock OR ( + mixed_port_feed_through_mode = "dont_care" AND + both_new_data_same_port + )) ELSE + " DW"; + + hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR + (port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE + " FW" WHEN (dual_clock OR ( + mixed_port_feed_through_mode = "dont_care" AND + both_new_data_same_port + )) ELSE + " DW"; + delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0'; + delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ; + read_before_write_a <= (hw_write_mode_a = "R+W"); + read_before_write_b <= (hw_write_mode_b = "R+W"); + + -- -------- core logic --------------- + portadatain_int <= portadatain; + portaaddr_int <= portaaddr; + portabyteenamasks_int <= portabyteenamasks; + portbdatain_int <= portbdatain; + portbaddr_int <= portbaddr; + portbbyteenamasks_int <= portbbyteenamasks; + portaaddrstall_int <= portaaddrstall; + portbaddrstall_int <= portbaddrstall; + clk_a_in <= clk0; + clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk0; + clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk0; + + clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk0; + clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE + clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1; + + clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1; + clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE + clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1; + clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE + clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE + clk1; + clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE + clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE + clk1; + clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE + clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1; + + addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0; + addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE + clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1; + + datain_a_clr_in <= '0'; + datain_b_clr_in <= '0'; + + dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE + clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1; + dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE + '0'; + + dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE + clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1; + dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE + '0'; + + byteena_a_clr_in <= '0'; + byteena_b_clr_in <= '0'; + we_a_clr_in <= '0'; + re_a_clr_in <= '0'; + we_b_clr_in <= '0'; + re_b_clr_in <= '0'; + + active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE + ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE + ena2; + active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE + ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE + ena2; + + be_mask_write(primary_port_is_a) <= be_mask_write_a; + be_mask_write(primary_port_is_b) <= be_mask_write_b; + + active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE + ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE + ena2; + active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE + ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE + ena3; + active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1; + active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE + ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE + ena2; + active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE + ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE + ena3; + active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1; + + active_write_a <= (byteena_a_reg /= bytes_a_disabled); + + active_write_b <= (byteena_b_reg /= bytes_b_disabled); + + -- Store core clock enable value for delayed write + -- port A core active + active_a_core_in_vec(0) <= active_a_core_in; + active_core_port_a : cycloneiv_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => active_a_core_in_vec, + clk => clk_a_in, + aclr => wire_gnd, + devclrn => wire_vcc,devpor => wire_vcc, + ena => wire_vcc, + stall => wire_gnd, + q => active_a_core_out + ); + active_a_core <= (active_a_core_out(0) = '1'); + + -- port B core active + active_b_core_in_vec(0) <= active_b_core_in; + active_core_port_b : cycloneiv_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => active_b_core_in_vec, + clk => clk_b_in, + aclr => wire_gnd, + devclrn => wire_vcc,devpor => wire_vcc, + ena => wire_vcc, + stall => wire_gnd, + q => active_b_core_out + ); + active_b_core <= (active_b_core_out(0) = '1'); + + + + -- ------ A input registers + -- write enable + we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe; + we_a_register : cycloneiv_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => we_a_reg_in, + clk => clk_a_wena, + aclr => we_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => we_a_reg_out, + aclrout => we_a_clr + ); + we_a_reg <= we_a_reg_out(0); + -- read enable + re_a_reg_in(0) <= portare; + re_a_register : cycloneiv_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => re_a_reg_in, + clk => clk_a_rena, + aclr => re_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => re_a_reg_out, + aclrout => re_a_clr + ); + re_a_reg <= re_a_reg_out(0); + + -- address + addr_a_register : cycloneiv_ram_register + GENERIC MAP ( width => port_a_address_width ) + PORT MAP ( + d => portaaddr_int, + clk => clk_a_in, + aclr => addr_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => portaaddrstall_int, + ena => active_a_in, + q => addr_a_reg, + aclrout => addr_a_clr + ); + -- data + datain_a_register : cycloneiv_ram_register + GENERIC MAP ( width => port_a_data_width ) + PORT MAP ( + d => portadatain_int, + clk => clk_a_in, + aclr => datain_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => datain_a_reg, + aclrout => datain_a_clr + ); + -- byte enable + byteena_a_register : cycloneiv_ram_register + GENERIC MAP ( + width => port_a_byte_enable_mask_width, + preset => '1' + ) + PORT MAP ( + d => portabyteenamasks_int, + clk => clk_a_byteena, + aclr => byteena_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => byteena_a_reg, + aclrout => byteena_a_clr + ); + -- ------ B input registers + + -- read enable + re_b_reg_in(0) <= portbre; + re_b_register : cycloneiv_ram_register + GENERIC MAP ( + width => 1 + ) + PORT MAP ( + d => re_b_reg_in, + clk => clk_b_rena, + aclr => re_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => re_b_reg_out, + aclrout => re_b_clr + ); + re_b_reg <= re_b_reg_out(0); + + -- write enable + we_b_reg_in(0) <= portbwe; + we_b_register : cycloneiv_ram_register + GENERIC MAP ( + width => 1 + ) + PORT MAP ( + d => we_b_reg_in, + clk => clk_b_wena, + aclr => we_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => we_b_reg_out, + aclrout => we_b_clr + ); + we_b_reg <= we_b_reg_out(0); + + -- address + addr_b_register : cycloneiv_ram_register + GENERIC MAP ( width => port_b_address_width ) + PORT MAP ( + d => portbaddr_int, + clk => clk_b_in, + aclr => addr_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => portbaddrstall_int, + ena => active_b_in, + q => addr_b_reg, + aclrout => addr_b_clr + ); + -- data + datain_b_register : cycloneiv_ram_register + GENERIC MAP ( width => port_b_data_width ) + PORT MAP ( + d => portbdatain_int, + clk => clk_b_in, + aclr => datain_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => datain_b_reg, + aclrout => datain_b_clr + ); + -- byte enable + byteena_b_register : cycloneiv_ram_register + GENERIC MAP ( + width => port_b_byte_enable_mask_width, + preset => '1' + ) + PORT MAP ( + d => portbbyteenamasks_int, + clk => clk_b_byteena, + aclr => byteena_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => byteena_b_reg, + aclrout => byteena_b_clr + ); + + datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg; + addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg); + + datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE + datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg; + addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg); + + -- Write pulse generation + wpgen_a_clk <= clk_a_in; + wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0'; + + wpgen_a : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => wpgen_a_clk, + ena => wpgen_a_clkena, + delaywrite => delay_write_pulse_a, + pulse => write_pulse(primary_port_is_a), + cycle => write_cycle_a + ); + + wpgen_b_clk <= clk_b_in; + wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0'; + + + wpgen_b : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => wpgen_b_clk, + ena => wpgen_b_clkena, + delaywrite => delay_write_pulse_b, + pulse => write_pulse(primary_port_is_b), + cycle => write_cycle_b + ); + + -- Read pulse generation + rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0'; + + rpgen_a : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => clk_a_in, + ena => rpgen_a_clkena, + cycle => clk_a_core, + pulse => read_pulse(primary_port_is_a) + ); + rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0'; + rpgen_b : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => clk_b_in, + ena => rpgen_b_clkena, + cycle => clk_b_core, + pulse => read_pulse(primary_port_is_b) + ); + + -- Read-during-Write pulse generation + rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0'; + rwpgen_a : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => clk_a_in, + ena => rwpgen_a_clkena, + pulse => rw_pulse(primary_port_is_a) + ); + + rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0'; + rwpgen_b : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => clk_b_in, + ena => rwpgen_b_clkena, + pulse => rw_pulse(primary_port_is_b) + ); + + -- Create internal masks for byte enable processing + mask_create : PROCESS (byteena_a_reg,byteena_b_reg) + VARIABLE mask : mask_rec; + BEGIN + IF (byteena_a_reg'EVENT) THEN + mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a); + IF (primary_port_is_a) THEN + mask_vector.prime <= mask.prime; + ELSE + mask_vector.sec <= mask.sec; + END IF; + END IF; + IF (byteena_b_reg'EVENT) THEN + mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b); + IF (primary_port_is_b) THEN + mask_vector.prime <= mask.prime; + ELSE + mask_vector.sec <= mask.sec; + END IF; + END IF; + END PROCESS mask_create; + + -- (row,col) coordinates + row_sec <= addr_sec_reg / num_cols; + col_sec <= addr_sec_reg mod num_cols; + + + + + mem_rw : PROCESS (init_mem, + write_pulse,read_pulse,read_pulse_feedthru, + rw_pulse, + dataout_a_clr, dataout_b_clr, + mem_invalidate,mem_invalidate_loc,read_latch_invalidate) + -- mem init + TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; + VARIABLE addr_range_init,row,col,index : INTEGER; + VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0); + VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0); + + VARIABLE mem_val : mem_type; + -- read/write + VARIABLE mem_data_p : mem_row_type; + VARIABLE old_mem_data_p : mem_row_type; + VARIABLE row_prime,col_prime : INTEGER; + VARIABLE access_same_location : BOOLEAN; + VARIABLE read_during_write : rw_type; + BEGIN + -- Latch Clear + IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN + IF (primary_port_is_a) THEN + read_latch.prime <= (OTHERS => (OTHERS => '0')); + dataout_prime <= (OTHERS => '0'); + ELSE + read_latch.sec <= (OTHERS => '0'); + dataout_sec <= (OTHERS => '0'); + END IF; + END IF; + + IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN + IF (primary_port_is_b) THEN + read_latch.prime <= (OTHERS => (OTHERS => '0')); + dataout_prime <= (OTHERS => '0'); + ELSE + read_latch.sec <= (OTHERS => '0'); + dataout_sec <= (OTHERS => '0'); + END IF; + END IF; + read_during_write := (FALSE,FALSE); + -- Memory initialization + IF (init_mem'EVENT) THEN + -- Initialize output latches to 0 + IF (primary_port_is_a) THEN + dataout_prime <= (OTHERS => '0'); + IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF; + ELSE + dataout_sec <= (OTHERS => '0'); + IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF; + END IF; + IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN + mem_val := (OTHERS => (OTHERS => (OTHERS => '0'))); + END IF; + IF (primary_port_is_a) THEN + addr_range_init := port_a_last_address - port_a_first_address + 1; + ELSE + addr_range_init := port_b_last_address - port_b_first_address + 1; + END IF; + IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN + mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0; + mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0); + FOR row IN 0 TO addr_range_init - 1 LOOP + FOR col IN 0 to num_cols - 1 LOOP + index := row * data_width; + mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO + index + col*data_unit_width); + END LOOP; + END LOOP; + END IF; + mem <= mem_val; + END IF; + access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec); + -- Read before Write stage 1 : read data from memory + -- Read before Write stage 2 : send data to output + IF (rw_pulse(primary)'EVENT) THEN + IF (rw_pulse(primary) = '1') THEN + read_latch.prime <= mem(addr_prime_reg); + ELSE + IF (be_mask_write(primary)) THEN + FOR i IN 0 TO data_width - 1 LOOP + IF (mask_vector.prime(normal)(i) = 'X') THEN + row_prime := i / data_unit_width; col_prime := i mod data_unit_width; + dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); + END IF; + END LOOP; + ELSE + FOR i IN 0 TO data_width - 1 LOOP + row_prime := i / data_unit_width; col_prime := i mod data_unit_width; + dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); + END LOOP; + END IF; + END IF; + END IF; + IF (rw_pulse(secondary)'EVENT) THEN + IF (rw_pulse(secondary) = '1') THEN + read_latch.sec <= mem(row_sec)(col_sec); + ELSE + IF (be_mask_write(secondary)) THEN + FOR i IN 0 TO data_unit_width - 1 LOOP + IF (mask_vector.sec(normal)(i) = 'X') THEN + dataout_sec(i) <= read_latch.sec(i); + END IF; + END LOOP; + ELSE + dataout_sec <= read_latch.sec; + END IF; + END IF; + END IF; + + -- Write stage 1 : X to buffer + -- Write stage 2 : actual data to memory + IF (write_pulse(primary)'EVENT) THEN + IF (write_pulse(primary) = '1') THEN + old_mem_data_p := mem(addr_prime_reg); + mem_data_p := mem(addr_prime_reg); + FOR i IN 0 TO num_cols - 1 LOOP + mem_data_p(i) := mem_data_p(i) XOR + mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width); + END LOOP; + read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1'); + IF (read_during_write(secondary)) THEN + read_latch.sec <= old_mem_data_p(col_sec); + ELSE + mem_data <= mem_data_p; + END IF; + ELSIF (clear_asserted_during_write(primary) /= '1') THEN + FOR i IN 0 TO data_width - 1 LOOP + IF (mask_vector.prime(normal)(i) = '0') THEN + mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i); + ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN + mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X'; + END IF; + END LOOP; + END IF; + END IF; + + IF (write_pulse(secondary)'EVENT) THEN + IF (write_pulse(secondary) = '1') THEN + read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1'); + IF (read_during_write(primary)) THEN + read_latch.prime <= mem(addr_prime_reg); + read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse); + ELSE + mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse); + END IF; + + IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN + mask_vector_common <= + mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND + mask_vector.sec(inverse); + dual_write <= TRUE; + END IF; + ELSIF (clear_asserted_during_write(secondary) /= '1') THEN + FOR i IN 0 TO data_unit_width - 1 LOOP + IF (mask_vector.sec(normal)(i) = '0') THEN + mem(row_sec)(col_sec)(i) <= datain_sec_reg(i); + ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN + mem(row_sec)(col_sec)(i) <= 'X'; + END IF; + END LOOP; + END IF; + END IF; + -- Simultaneous write + IF (dual_write AND write_pulse = "00") THEN + mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common; + dual_write <= FALSE; + END IF; + -- Read stage 1 : read data + -- Read stage 2 : send data to output + IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN + IF (read_pulse(primary) = '1') THEN + read_latch.prime <= mem(addr_prime_reg); + IF (access_same_location AND write_pulse(secondary) = '1') THEN + read_latch.prime(col_sec) <= mem_unit_data; + END IF; + ELSE + FOR i IN 0 TO data_width - 1 LOOP + row_prime := i / data_unit_width; col_prime := i mod data_unit_width; + dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); + END LOOP; + END IF; + END IF; + + IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN + IF (read_pulse(secondary) = '1') THEN + IF (access_same_location AND write_pulse(primary) = '1') THEN + read_latch.sec <= mem_data(col_sec); + ELSE + read_latch.sec <= mem(row_sec)(col_sec); + END IF; + ELSE + dataout_sec <= read_latch.sec; + END IF; + END IF; + -- Same port feed thru + IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN + IF (be_mask_write(primary)) THEN + FOR i IN 0 TO data_width - 1 LOOP + IF (mask_vector.prime(normal)(i) = '0') THEN + dataout_prime(i) <= datain_prime_reg(i); + END IF; + END LOOP; + ELSE + dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal); + END IF; + END IF; + + IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN + IF (be_mask_write(secondary)) THEN + FOR i IN 0 TO data_unit_width - 1 LOOP + IF (mask_vector.sec(normal)(i) = '0') THEN + dataout_sec(i) <= datain_sec_reg(i); + END IF; + END LOOP; + ELSE + dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal); + END IF; + END IF; + -- Async clear + IF (mem_invalidate'EVENT) THEN + IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN + mem <= mem_x; + END IF; + END IF; + IF (mem_invalidate_loc'EVENT) THEN + IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF; + IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF; + END IF; + IF (read_latch_invalidate'EVENT) THEN + IF (read_latch_invalidate(primary)) THEN + read_latch.prime <= row_x; + END IF; + IF (read_latch_invalidate(secondary)) THEN + read_latch.sec <= col_x; + END IF; + END IF; + + END PROCESS mem_rw; + + -- Same port feed through + ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0'; + ftpgen_a : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => clk_a_in, + ena => ftpgen_a_clkena, + pulse => read_pulse_feedthru(primary_port_is_a) + ); + ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0'; + + ftpgen_b : cycloneiv_ram_pulse_generator + PORT MAP ( + clk => clk_b_in, + ena => ftpgen_b_clkena, + pulse => read_pulse_feedthru(primary_port_is_b) + ); + + + + + + -- Asynch clear events + clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr) + BEGIN + IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN + clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a); + IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN + mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN + read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN + clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a); + IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN + mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + END PROCESS clear_a; + + clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr) + BEGIN + IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN + clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b); + IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN + mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN + read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN + clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b); + IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN + mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + END PROCESS clear_b; + + + -- Clear mux registers (Latch Clear) + -- Port A output register clear + dataout_a_clr_reg_latch_in(0) <= dataout_a_clr; + aclr_a_mux_register : cycloneiv_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => dataout_a_clr_reg_latch_in, + clk => clk_a_core, + aclr => wire_gnd, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => wire_vcc, + q => dataout_a_clr_reg_latch_out + ); + dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0); + + -- Port B output register clear + dataout_b_clr_reg_latch_in(0) <= dataout_b_clr; + aclr_b_mux_register : cycloneiv_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => dataout_b_clr_reg_latch_in, + clk => clk_b_core, + aclr => wire_gnd, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => wire_vcc, + q => dataout_b_clr_reg_latch_out + ); + dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0); + + -- ------ Output registers + + + clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0; + clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1; + clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1; + clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1; + + dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec; + dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE + dataout_prime WHEN primary_port_is_b ELSE dataout_sec; + + dataout_a_register : cycloneiv_ram_register + GENERIC MAP ( width => port_a_data_width ) + PORT MAP ( + d => dataout_a, + clk => clk_a_out, + aclr => dataout_a_clr_reg, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => clkena_a_out, + q => dataout_a_reg + ); + + dataout_b_register : cycloneiv_ram_register + GENERIC MAP ( width => port_b_data_width ) + PORT MAP ( + d => dataout_b, + clk => clk_b_out, + aclr => dataout_b_clr_reg, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => clkena_b_out, + q => dataout_b_reg + ); + + portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a; + portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b; + + +END block_arch; + + +----------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_mac_data_reg +-- +-- Description : Simulation model for the data input register of +-- Cyclone II MAC_MULT +-- +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_mac_data_reg IS + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + data_width : integer := 18 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + data : IN std_logic_vector(17 DOWNTO 0); + ena : IN std_logic; + aclr : IN std_logic; + -- OUTPUT PORTS + dataout : OUT std_logic_vector(17 DOWNTO 0) + ); +END cycloneiv_mac_data_reg; + +ARCHITECTURE vital_cycloneiv_mac_data_reg OF cycloneiv_mac_data_reg IS + + SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL aclr_ipd : std_logic; + SIGNAL clk_ipd : std_logic; + SIGNAL ena_ipd : std_logic; + SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + +BEGIN + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + g1 : for i in data'range generate + VitalWireDelay (data_ipd(i), data(i), tipd_data(i)); + end generate; + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + + process (clk_ipd, aclr_ipd, data_ipd) + begin + if (aclr_ipd = '1') then + dataout_tmp <= (OTHERS => '0'); + elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then + dataout_tmp <= data_ipd; + end if; + + end process; + + sh: block + begin + g0 : for i in data'range generate + process (data_ipd(i),clk_ipd,ena_ipd) + variable Tviol_data_clk : std_ulogic := '0'; + variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_data_clk, + TimingData => TimingData_data_clk, + TestSignal => data_ipd(i), + TestSignalName => "DATA(i)", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_data_clk_noedge_posedge(i), + SetupLow => tsetup_data_clk_noedge_posedge(i), + HoldHigh => thold_data_clk_noedge_posedge(i), + HoldLow => thold_data_clk_noedge_posedge(i), + CheckEnabled => TO_X01((aclr) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena_ipd, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01(aclr) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + END PROCESS; + end generate g0; + end block; + + ---------------------- + -- Path Delay Section + ---------------------- + PathDelay : block + begin + g1 : for i in dataout_tmp'range generate + VITALtiming : process (dataout_tmp(i)) + variable dataout_VitalGlitchData : VitalGlitchDataType; + begin + VitalPathDelay01 (OutSignal => dataout(i), + OutSignalName => "DATAOUT", + OutTemp => dataout_tmp(i), + Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE), + 1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn); + end process; + end generate; + end block; + +END vital_cycloneiv_mac_data_reg; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_mac_sign_reg +-- +-- Description : Simulation model for the sign input register of +-- Cyclone II MAC_MULT +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_mac_sign_reg IS + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + d : IN std_logic; + ena : IN std_logic; + aclr : IN std_logic; + + -- OUTPUT PORTS + q : OUT std_logic + ); +END cycloneiv_mac_sign_reg; + +ARCHITECTURE cycloneiv_mac_sign_reg OF cycloneiv_mac_sign_reg IS + + signal d_ipd : std_logic; + signal clk_ipd : std_logic; + signal aclr_ipd : std_logic; + signal ena_ipd : std_logic; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + VITALtiming : process (clk_ipd, aclr_ipd) + variable Tviol_d_clk : std_ulogic := '0'; + variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + variable q_reg : std_logic := '0'; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_clk, + TimingData => TimingData_d_clk, + TestSignal => d, + TestSignalName => "D", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => TO_X01((aclr) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/SIGN_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01(aclr) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/SIGN_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + if (aclr_ipd = '1') then + q_reg := '0'; + elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then + q_reg := d_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => q_reg, + Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE), + 1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + end process; +END cycloneiv_mac_sign_reg; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_mac_mult_internal +-- +-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; +USE work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_mac_mult_internal IS + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_datab : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_signa : VitalDelayType01 := DefPropDelay01; + tipd_signb : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + dataa_width : integer := 18; + datab_width : integer := 18 + ); + PORT ( + dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) + ); +END cycloneiv_mac_mult_internal; + +ARCHITECTURE vital_cycloneiv_mac_mult_internal OF cycloneiv_mac_mult_internal IS + + -- Internal variables + SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL signa_ipd : std_logic; + SIGNAL signb_ipd : std_logic; + + -- padding with 1's for input negation + SIGNAL reg_aclr : std_logic; + SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0'); + +BEGIN + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + g1 : for i in dataa'range generate + VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); + end generate; + g2 : for i in datab'range generate + VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i)); + end generate; + + VitalWireDelay (signa_ipd, signa, tipd_signa); + VitalWireDelay (signb_ipd, signb, tipd_signb); + end block; + + + VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd) + begin + if((signa_ipd = '0') and (signb_ipd = '1')) then + dataout_tmp <= + unsigned(dataa_ipd(dataa_width-1 downto 0)) * + signed(datab_ipd(datab_width-1 downto 0)); + elsif((signa_ipd = '1') and (signb_ipd = '0')) then + dataout_tmp <= + signed(dataa_ipd(dataa_width-1 downto 0)) * + unsigned(datab_ipd(datab_width-1 downto 0)); + elsif((signa_ipd = '1') and (signb_ipd = '1')) then + dataout_tmp(dataout'range) <= + signed(dataa_ipd(dataa_width-1 downto 0)) * + signed(datab_ipd(datab_width-1 downto 0)); + else --((signa_ipd = '0') and (signb_ipd = '0')) then + dataout_tmp(dataout'range) <= + unsigned(dataa_ipd(dataa_width-1 downto 0)) * + unsigned(datab_ipd(datab_width-1 downto 0)); + end if; + end process; + + ---------------------- + -- Path Delay Section + ---------------------- + PathDelay : block + begin + g1 : for i in dataout'range generate + VITALtiming : process (dataout_tmp(i)) + variable dataout_VitalGlitchData : VitalGlitchDataType; + begin + VitalPathDelay01 (OutSignal => dataout(i), + OutSignalName => "dataout", + OutTemp => dataout_tmp(i), + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE), + 1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE), + 2 => (signa'last_event, tpd_signa_dataout(i), TRUE), + 3 => (signb'last_event, tpd_signb_dataout(i), TRUE)), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + MsgOn => FALSE, + XOn => TRUE ); + end process; + end generate; + end block; + +END vital_cycloneiv_mac_mult_internal; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_mac_mult +-- +-- Description : Cyclone II MAC_MULT VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; +USE work.cycloneiv_atom_pack.all; +USE work.cycloneiv_mac_data_reg; +USE work.cycloneiv_mac_sign_reg; +USE work.cycloneiv_mac_mult_internal; + +ENTITY cycloneiv_mac_mult IS + GENERIC ( + dataa_width : integer := 18; + datab_width : integer := 18; + dataa_clock : string := "none"; + datab_clock : string := "none"; + signa_clock : string := "none"; + signb_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + lpm_hint : string := "true"; + lpm_type : string := "cycloneiv_mac_mult" + ); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '0'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneiv_mac_mult; + +ARCHITECTURE vital_cycloneiv_mac_mult OF cycloneiv_mac_mult IS + + COMPONENT cycloneiv_mac_data_reg + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + data_width : integer := 18 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + data : IN std_logic_vector(17 DOWNTO 0); + ena : IN std_logic; + aclr : IN std_logic; + -- OUTPUT PORTS + dataout : OUT std_logic_vector(17 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_mac_sign_reg + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + d : IN std_logic; + ena : IN std_logic; + aclr : IN std_logic; + + -- OUTPUT PORTS + q : OUT std_logic + ); + END COMPONENT; + + COMPONENT cycloneiv_mac_mult_internal + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_datab : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_signa : VitalDelayType01 := DefPropDelay01; + tipd_signb : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + dataa_width : integer := 18; + datab_width : integer := 18 + ); + PORT ( + dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) + ); + END COMPONENT; + + -- Internal variables + SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input + SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input + SIGNAL isigna_reg : std_logic; -- optional register for signa input + SIGNAL isignb_reg : std_logic; -- optional register for signb input + SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input + SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input + SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input + SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input + -- padding with 1's for input negation + SIGNAL reg_aclr : std_logic; + SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0'); + +BEGIN + + --------------------- + -- INPUT PATH DELAYs + --------------------- + + reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ; + + -- padding input data to full bus width + dataa_ipd(dataa_width-1 downto 0) <= dataa; + datab_ipd(datab_width-1 downto 0) <= datab; + + -- Optional input registers for dataa,b and signa,b + dataa_reg : cycloneiv_mac_data_reg + GENERIC MAP ( + data_width => dataa_width) + PORT MAP ( + clk => clk, + data => dataa_ipd, + ena => ena, + aclr => reg_aclr, + dataout => idataa_reg); + + datab_reg : cycloneiv_mac_data_reg + GENERIC MAP ( + data_width => datab_width) + PORT MAP ( + clk => clk, + data => datab_ipd, + ena => ena, + aclr => reg_aclr, + dataout => idatab_reg); + + signa_reg : cycloneiv_mac_sign_reg + PORT MAP ( + clk => clk, + d => signa, + ena => ena, + aclr => reg_aclr, + q => isigna_reg); + + signb_reg : cycloneiv_mac_sign_reg + PORT MAP ( + clk => clk, + d => signb, + ena => ena, + aclr => reg_aclr, + q => isignb_reg); + + idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg; + idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg; + isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg; + isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg; + + mac_multiply : cycloneiv_mac_mult_internal + GENERIC MAP ( + dataa_width => dataa_width, + datab_width => datab_width + ) + PORT MAP ( + dataa => idataa_int, + datab => idatab_int, + signa => isigna_int, + signb => isignb_int, + dataout => dataout + ); +END vital_cycloneiv_mac_mult; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_mac_out +-- +-- Description : Cyclone II MAC_OUT VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_mac_out IS + GENERIC ( + dataa_width : integer := 1; + output_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(35 downto 0) + := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + lpm_hint : string := "true"; + lpm_type : string := "cycloneiv_mac_out"); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '1'; + dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneiv_mac_out; + +ARCHITECTURE vital_cycloneiv_mac_out OF cycloneiv_mac_out IS + + -- internal variables + SIGNAL dataa_ipd : std_logic_vector(dataa'range); + SIGNAL clk_ipd : std_logic; + SIGNAL aclr_ipd : std_logic; + SIGNAL ena_ipd : std_logic; + + -- optional register + SIGNAL use_reg : std_logic; + + SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0'); + +BEGIN + + --------------------- + -- PATH DELAYs + --------------------- + WireDelay : block + begin + g1 : for i in dataa'range generate + VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); + VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i)) + variable dataout_VitalGlitchData : VitalGlitchDataType; + begin + VitalPathDelay01 ( + OutSignal => dataout(i), + OutSignalName => "DATAOUT", + OutTemp => dataout_tmp(i), + Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'), + 1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'), + 2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + end process; + end generate; + + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + + end block; + + use_reg <= '1' WHEN (output_clock /= "none") ELSE '0'; + + sh: block + begin + g0 : for i in dataa'range generate + VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i)) + variable Tviol_dataa_clk : std_ulogic := '0'; + variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_dataa_clk, + TimingData => TimingData_dataa_clk, + TestSignal => dataa(i), + TestSignalName => "D", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_dataa_clk_noedge_posedge(i), + SetupLow => tsetup_dataa_clk_noedge_posedge(i), + HoldHigh => thold_dataa_clk_noedge_posedge(i), + HoldLow => thold_dataa_clk_noedge_posedge(i), + CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01((aclr) OR + (NOT use_reg)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + END PROCESS; + end generate g0; + end block; + + process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd) + begin + if (use_reg = '0') then + dataout_tmp <= dataa_ipd; + else + if (aclr_ipd = '1') then + dataout_tmp <= (OTHERS => '0'); + elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then + dataout_tmp <= dataa_ipd; + end if; + end if; + + end process; + +END vital_cycloneiv_mac_out; + + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_io_ibuf +-- +-- Description : Cyclone IV GX IO Ibuf VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_io_ibuf IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_ibar : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_ibar_o : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + differential_mode : string := "false"; + bus_hold : string := "false"; + simulate_z_as : string := "Z"; + lpm_type : string := "cycloneiv_io_ibuf" + ); + PORT ( + i : IN std_logic := '0'; + ibar : IN std_logic := '0'; + o : OUT std_logic + ); +END cycloneiv_io_ibuf; + +ARCHITECTURE arch OF cycloneiv_io_ibuf IS + SIGNAL i_ipd : std_logic := '0'; + SIGNAL ibar_ipd : std_logic := '0'; + SIGNAL o_tmp : std_logic; + SIGNAL out_tmp : std_logic; + SIGNAL prev_value : std_logic := '0'; +BEGIN + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (ibar_ipd, ibar, tipd_ibar); + end block; + + PROCESS(i_ipd, ibar_ipd) + BEGIN + IF (differential_mode = "false") THEN + IF (i_ipd = '1') THEN + o_tmp <= '1'; + prev_value <= '1'; + ELSIF (i_ipd = '0') THEN + o_tmp <= '0'; + prev_value <= '0'; + ELSE + o_tmp <= i_ipd; + END IF; + ELSE + IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then + o_tmp <= '0'; + ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then + o_tmp <= '1'; + ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then + o_tmp <= 'X'; + ELSE + o_tmp <= 'X'; + END IF; + END IF; + END PROCESS; + + out_tmp <= prev_value when (bus_hold = "true") else + 'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else + 'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else + '1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else + '0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else + o_tmp; + ---------------------- + -- Path Delay Section + ---------------------- + PROCESS( out_tmp) + variable output_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => out_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), + 1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)), + GlitchData => output_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; + END arch; + + + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_io_obuf +-- +-- Description : Cyclone IV GX IO Obuf VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_io_obuf IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_oe_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tpd_oe_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + open_drain_output : string := "false"; + bus_hold : string := "false"; + lpm_type : string := "cycloneiv_io_obuf" + ); + PORT ( + i : IN std_logic := '0'; + oe : IN std_logic := '1'; + seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + devoe : IN std_logic := '1'; + o : OUT std_logic; + obar : OUT std_logic + ); +END cycloneiv_io_obuf; + +ARCHITECTURE arch OF cycloneiv_io_obuf IS + --INTERNAL Signals + SIGNAL i_ipd : std_logic := '0'; + SIGNAL oe_ipd : std_logic := '0'; + SIGNAL out_tmp : std_logic := 'Z'; + SIGNAL out_tmp_bar : std_logic; + SIGNAL prev_value : std_logic := '0'; + SIGNAL o_tmp : std_logic; + SIGNAL obar_tmp : std_logic; + SIGNAL o_tmp1 : std_logic; + SIGNAL obar_tmp1 : std_logic; + SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0'); + +BEGIN + +WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (oe_ipd, oe, tipd_oe); + g1 :for i in seriesterminationcontrol'range generate + VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i)); + end generate; + + + end block; + PROCESS( i_ipd, oe_ipd) + BEGIN + IF (oe_ipd = '1') THEN + IF (open_drain_output = "true") THEN + IF (i_ipd = '0') THEN + out_tmp <= '0'; + out_tmp_bar <= '1'; + prev_value <= '0'; + ELSE + out_tmp <= 'Z'; + out_tmp_bar <= 'Z'; + END IF; + ELSE + IF (i_ipd = '0') THEN + out_tmp <= '0'; + out_tmp_bar <= '1'; + prev_value <= '0'; + ELSE + IF (i_ipd = '1') THEN + out_tmp <= '1'; + out_tmp_bar <= '0'; + prev_value <= '1'; + ELSE + out_tmp <= i_ipd; + out_tmp_bar <= i_ipd; + END IF; + END IF; + END IF; + ELSE + IF (oe_ipd = '0') THEN + out_tmp <= 'Z'; + out_tmp_bar <= 'Z'; + ELSE + out_tmp <= 'X'; + out_tmp_bar <= 'X'; + END IF; + END IF; + END PROCESS; + o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp; + obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar; + o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z'; + obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z'; + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( o_tmp,obar_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable obar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => o_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), + 1 => (oe_ipd'last_event, tpd_oe_o, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => obar, + OutSignalName => "obar", + OutTemp => obar_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE), + 1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)), + GlitchData => obar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; +END arch; + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_ddio_oe +-- +-- Description : Cyclone IV GX DDIO_OE VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +LIBRARY altera; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use altera.all; +use work.cycloneiv_atom_pack.all; + + + +ENTITY cycloneiv_ddio_oe IS + generic( + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + lpm_type : string := "cycloneiv_ddio_oe" + ); + + PORT ( + oe : IN std_logic := '1'; + clk : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneiv_ddio_oe; + +ARCHITECTURE arch OF cycloneiv_ddio_oe IS + +component cycloneiv_mux21 + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01 + ); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic + ); +end component; + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +end component; + + --Internal Signals + SIGNAL oe_ipd : std_logic := '0'; + SIGNAL clk_ipd : std_logic := '0'; + SIGNAL ena_ipd : std_logic := '0'; + SIGNAL areset_ipd : std_logic := '0'; + SIGNAL sreset_ipd : std_logic := '0'; + SIGNAL ddioreg_aclr : std_logic; + SIGNAL ddioreg_prn : std_logic; + SIGNAL ddioreg_adatasdata : std_logic; + SIGNAL ddioreg_sclr : std_logic; + SIGNAL ddioreg_sload : std_logic; + SIGNAL dfflo_tmp : std_logic; + SIGNAL dffhi_tmp : std_logic; + signal nclk : std_logic; + signal dataout_tmp : std_logic; + + +BEGIN + + WireDelay : block + begin + VitalWireDelay (oe_ipd, oe, tipd_oe); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (sreset_ipd, sreset, tipd_sreset); + end block; + + nclk <= NOT clk_ipd; + PROCESS + BEGIN + WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; + IF (async_mode = "clear") THEN + ddioreg_aclr <= NOT areset_ipd; + ddioreg_prn <= '1'; + ELSIF (async_mode = "preset") THEN + ddioreg_aclr <= '1'; + ddioreg_prn <= NOT areset_ipd; + ELSE + ddioreg_aclr <= '1'; + ddioreg_prn <= '1'; + END IF; + + IF (sync_mode = "clear") THEN + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= sreset_ipd; + ddioreg_sload <= '0'; + ELSIF (sync_mode = "preset") THEN + ddioreg_adatasdata <= '1'; + ddioreg_sclr <= '0'; + ddioreg_sload <= sreset_ipd; + ELSE + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= '0'; + ddioreg_sload <= '0'; + END IF; + END PROCESS; + + ddioreg_hi : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => oe_ipd, --REM_AV + clk => clk_ipd, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dffhi_tmp, + devpor => devpor, + devclrn => devclrn + ); + + + --DDIO Low Register + ddioreg_lo : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => dffhi_tmp, --REM_AV + clk => nclk, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dfflo_tmp, + devpor => devpor, + devclrn => devclrn + ); + + --registered output + or_gate : cycloneiv_mux21 + port map ( + A => dffhi_tmp, + B => dfflo_tmp, + S => dfflo_tmp, + MO => dataout + ); + + dfflo <= dfflo_tmp ; + dffhi <= dffhi_tmp ; + + +END arch; +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_latch +-- +-- Description : Cyclone IV GX latch VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +Library ieee; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; +entity cycloneiv_latch is + generic( + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneiv_latch"; + tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tpd_d_q : VitalDelayType01 := DefPropDelay01; + tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clr : VitalDelayType01 := DefPropDelay01; + tipd_pre : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port( + d : in std_logic := '0'; + ena : in std_logic := '1'; + clr : in std_logic := '1'; + pre : in std_logic := '1'; + q : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneiv_latch : entity is TRUE; +end cycloneiv_latch; + + +architecture vital_latch of cycloneiv_latch is + attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE; + signal d_ipd : std_logic; + signal d_dly : std_logic; + signal clr_ipd : std_logic; + signal pre_ipd : std_logic; + signal ena_ipd : std_logic; + +begin + + d_dly <= d_ipd; + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (clr_ipd, clr, tipd_clr); + VitalWireDelay (pre_ipd, pre, tipd_pre); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd) + + variable Tviol_d_ena : std_ulogic := '0'; + variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + + variable iq : std_logic := '0'; + variable idata: std_logic := '0'; + + -- variables for 'X' generation + variable violation : std_logic := '0'; + + begin + + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_ena, + TimingData => TimingData_d_ena, + TestSignal => d_ipd, + TestSignalName => "DATAIN", + RefSignal => ena_ipd, + RefSignalName => "ENA", + SetupHigh => tsetup_d_ena_noedge_negedge, + SetupLow => tsetup_d_ena_noedge_negedge, + HoldHigh => thold_d_ena_noedge_negedge, + HoldLow => thold_d_ena_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + HeaderMsg => InstancePath & "/cycloneiv_latch", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + + + violation := Tviol_d_ena; + + + if ( (clr_ipd = '0')) then + iq := '0'; + elsif (pre_ipd = '0') then + iq := '1'; + elsif (violation = 'X' and x_on_violation = "on") then + iq := 'X'; + elsif (ena_ipd = '1') then + iq := d_dly; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => iq, + Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE), + 1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE), + 2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end vital_latch; +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_ddio_out +-- +-- Description : Cyclone IV GX DDIO_OUT VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +LIBRARY altera; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use altera.all; +use work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_ddio_out IS + generic( + tipd_datainlo : VitalDelayType01 := DefPropDelay01; + tipd_datainhi : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkhi : VitalDelayType01 := DefPropDelay01; + tipd_clklo : VitalDelayType01 := DefPropDelay01; + tipd_muxsel : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + use_new_clocking_model : string := "false"; + lpm_type : string := "cycloneiv_ddio_out" + ); + PORT ( + datainlo : IN std_logic := '0'; + datainhi : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkhi : IN std_logic := '0'; + clklo : IN std_logic := '0'; + muxsel : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic ; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneiv_ddio_out; + +ARCHITECTURE arch OF cycloneiv_ddio_out IS + +component cycloneiv_mux21 + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01 + ); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic + ); +end component; + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +end component; + +component cycloneiv_latch + generic( + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneiv_latch"; + tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tpd_d_q : VitalDelayType01 := DefPropDelay01; + tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clr : VitalDelayType01 := DefPropDelay01; + tipd_pre : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port( + d : in std_logic := '0'; + ena : in std_logic := '1'; + clr : in std_logic := '1'; + pre : in std_logic := '1'; + q : out std_logic + ); +end component; + +component cycloneiv_routing_wire is + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); + +end component; + --Internal Signals + SIGNAL datainlo_ipd : std_logic := '0'; + SIGNAL datainhi_ipd : std_logic := '0'; + SIGNAL clk_ipd : std_logic := '0'; + SIGNAL clkhi_ipd : std_logic := '0'; + SIGNAL clklo_ipd : std_logic := '0'; + SIGNAL muxsel_ipd : std_logic := '0'; + SIGNAL ena_ipd : std_logic := '0'; + SIGNAL areset_ipd : std_logic := '0'; + SIGNAL sreset_ipd : std_logic := '0'; + SIGNAL ddioreg_aclr : std_logic; + SIGNAL ddioreg_prn : std_logic; + SIGNAL ddioreg_adatasdata : std_logic; + SIGNAL ddioreg_sclr : std_logic; + SIGNAL ddioreg_sload : std_logic; + SIGNAL dfflo_tmp : std_logic; + SIGNAL dffhi_tmp : std_logic; + SIGNAL dataout_tmp : std_logic; + Signal mux_sel : std_logic; + Signal mux_hi : std_logic; + Signal sel_mux_hi_in : std_logic; + signal clk1 : std_logic; + signal clk_hi : std_logic; + signal clk_lo : std_logic; + + signal muxsel1 : std_logic; + signal muxsel2: std_logic; + signal clk2 : std_logic; + signal muxsel_tmp: std_logic; + signal sel_mux_lo_in : std_logic; + signal datainlo_tmp : std_logic; + signal datainhi_tmp : std_logic; + signal dffhi_tmp1 : std_logic; + signal bdataout : std_logic; + signal hrb_sel: std_logic; + +BEGIN + +WireDelay : block + begin + VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo); + VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi); + VitalWireDelay (clklo_ipd, clklo, tipd_clklo); + VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (sreset_ipd, sreset, tipd_sreset); + end block; + PROCESS + BEGIN + WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; + IF (async_mode = "clear") THEN + ddioreg_aclr <= NOT areset_ipd; + ddioreg_prn <= '1'; + ELSIF (async_mode = "preset") THEN + ddioreg_aclr <= '1'; + ddioreg_prn <= NOT areset_ipd; + ELSE + ddioreg_aclr <= '1'; + ddioreg_prn <= '1'; + END IF; + + IF (sync_mode = "clear") THEN + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= sreset_ipd; + ddioreg_sload <= '0'; + ELSIF (sync_mode = "preset") THEN + ddioreg_adatasdata <= '1'; + ddioreg_sclr <= '0'; + ddioreg_sload <= sreset_ipd; + ELSE + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= '0'; + ddioreg_sload <= '0'; + END IF; + END PROCESS; + + process(clk_ipd) + begin + clk1 <= clk_ipd; + end process; + + process(muxsel_ipd) + begin + muxsel1 <= muxsel_ipd; + end process; + + + process(dffhi_tmp) + begin + dffhi_tmp1 <= dffhi_tmp; + end process; + + + --DDIO HIGH Register + clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd); + datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi; + + ddioreg_hi : cycloneiv_latch + PORT MAP ( + d=> datainhi_tmp, + ena => clk_hi, + pre => ddioreg_prn, + clr => ddioreg_aclr, + q => dffhi_tmp + ); + + --DDIO Low Register + clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd; + datainlo_tmp <= datainlo; + ddioreg_lo : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => datainlo_tmp, + clk => clk_lo, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dfflo_tmp, + devpor => devpor, + devclrn => devclrn + ); + + + muxsel2 <= muxsel1; + clk2 <= clk1; + mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2; + muxsel_tmp <= NOT mux_sel; + sel_mux_lo_in <= dfflo_tmp; + sel_mux_hi_in <= dffhi_tmp1; + + + +wire_delay : cycloneiv_routing_wire + port map ( + datain => bdataout, + dataout => dataout + ); + + sel_mux : cycloneiv_mux21 + port map ( + A => sel_mux_hi_in, + B => sel_mux_lo_in, + S => muxsel_tmp, + MO => bdataout --REM_AV + ); + + dfflo <= dfflo_tmp; + dffhi <= dffhi_tmp; + +END arch; +---------------------------------------------------------------------------- +-- Module Name : cycloneiv_io_pad +-- Description : Simulation model for cycloneiv IO pad +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +ENTITY cycloneiv_io_pad IS + GENERIC ( + lpm_type : string := "cycloneiv_io_pad"); + PORT ( + --INPUT PORTS + + padin : IN std_logic := '0'; -- Input Pad + --OUTPUT PORTS + + padout : OUT std_logic); -- Output Pad +END cycloneiv_io_pad; + +ARCHITECTURE arch OF cycloneiv_io_pad IS + +BEGIN + padout <= padin; +END arch; +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneiv_ena_reg +-- +-- Description : Simulation model for a simple DFF. +-- This is used for the gated clock generation +-- Powers upto 1. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_ena_reg is + generic ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneiv_ena_reg : entity is TRUE; +end cycloneiv_ena_reg; + +ARCHITECTURE behave of cycloneiv_ena_reg is + attribute VITAL_LEVEL0 of behave : architecture is TRUE; + signal d_ipd : std_logic; + signal clk_ipd : std_logic; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (clk_ipd, clk, tipd_clk); + end block; + + VITALtiming : process (clk_ipd, prn, clrn) + variable Tviol_d_clk : std_ulogic := '0'; + variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + variable q_reg : std_logic := '1'; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_clk, + TimingData => TimingData_d_clk, + TestSignal => d, + TestSignalName => "D", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => TO_X01((clrn) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_ena_reg", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + if (prn = '0') then + q_reg := '1'; + elsif (clrn = '0') then + q_reg := '0'; + elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then + q_reg := d_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => q_reg, + Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; + + +--///////////////////////////////////////////////////////////////////////////// +-- +-- VHDL Simulation Model for Cyclone III CLKCTRL Atom +-- +--///////////////////////////////////////////////////////////////////////////// + +-- +-- +-- CYCLONEIV_CLKCTRL Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; +use work.cycloneiv_ena_reg; + +entity cycloneiv_clkctrl is + generic ( + clock_type : STRING := "Auto"; + lpm_type : STRING := "cycloneiv_clkctrl"; + ena_register_mode : STRING := "Falling Edge"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01 + ); + port ( + inclk : in std_logic_vector(3 downto 0) := "0000"; + clkselect : in std_logic_vector(1 downto 0) := "00"; + ena : in std_logic := '1'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + outclk : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneiv_clkctrl : entity is TRUE; +end cycloneiv_clkctrl; + +architecture vital_clkctrl of cycloneiv_clkctrl is + attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE; + + component cycloneiv_ena_reg + generic ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic + ); + end component; + + signal inclk_ipd : std_logic_vector(3 downto 0); + signal clkselect_ipd : std_logic_vector(1 downto 0); + signal ena_ipd : std_logic; + signal clkmux_out : std_logic; + signal clkmux_out_inv : std_logic; + signal cereg_clr : std_logic; + signal cereg1_out : std_logic; + signal cereg2_out : std_logic; + signal ena_out : std_logic; + signal outclk_tmp : std_logic; + signal vcc : std_logic := '1'; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0)); + VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1)); + VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2)); + VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3)); + VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0)); + VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1)); + end block; + + process(inclk_ipd, clkselect_ipd) + variable tmp : std_logic; + begin + if (clkselect_ipd = "11") then + tmp := inclk_ipd(3); + elsif (clkselect_ipd = "10") then + tmp := inclk_ipd(2); + elsif (clkselect_ipd = "01") then + tmp := inclk_ipd(1); + else + tmp := inclk_ipd(0); + end if; + clkmux_out <= tmp; + clkmux_out_inv <= NOT tmp; + end process; + + extena0_reg : cycloneiv_ena_reg + port map ( + clk => clkmux_out_inv, + ena => vcc, + d => ena_ipd, + clrn => vcc, + prn => devpor, + q => cereg1_out + ); + + extena1_reg : cycloneiv_ena_reg + port map ( + clk => clkmux_out_inv, + ena => vcc, + d => cereg1_out, + clrn => vcc, + prn => devpor, + q => cereg2_out + ); + + ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE + ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out; + + outclk_tmp <= ena_out AND clkmux_out; + + -- output path + process (inclk_ipd,outclk_tmp) + variable outclk_VitalGlitchData : VitalGlitchDataType; + begin + ---------------------- + -- Path Delay Section + ---------------------- + + VitalPathDelay01 + ( + OutSignal => outclk, + OutSignalName => "OUTCLK", + OutTemp => outclk_tmp, + Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE), + 1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE), + 2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE), + 3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)), + GlitchData => outclk_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + end process; + + +end vital_clkctrl; + +---------------------------------------------------------------------------------- +--Module Name: cycloneiv_pseudo_diff_out -- +--Description: Simulation model for Cyclone IV GX Pseudo Differential -- +-- Output Buffer -- +---------------------------------------------------------------------------------- + + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +ENTITY cycloneiv_pseudo_diff_out IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + lpm_type : string := "cycloneiv_pseudo_diff_out" + ); + PORT ( + i : IN std_logic := '0'; + o : OUT std_logic; + obar : OUT std_logic + ); +END cycloneiv_pseudo_diff_out; + +ARCHITECTURE arch OF cycloneiv_pseudo_diff_out IS + SIGNAL i_ipd : std_logic ; + SIGNAL o_tmp : std_logic ; + SIGNAL obar_tmp : std_logic; + +BEGIN + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + + PROCESS( i_ipd) + BEGIN + IF (i_ipd = '0') THEN + o_tmp <= '0'; + obar_tmp <= '1'; + ELSE + IF (i_ipd = '1') THEN + o_tmp <= '1'; + obar_tmp <= '0'; + ELSE + o_tmp <= i_ipd; + obar_tmp <= i_ipd; + END IF; + END IF; + END PROCESS; + + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( o_tmp,obar_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable obar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => o_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => obar, + OutSignalName => "obar", + OutTemp => obar_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)), + GlitchData => obar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; +END arch; +-- +-- +-- CYCLONEIV_RUBLOCK Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_rublock is + generic + ( + sim_init_config : string := "factory"; + sim_init_watchdog_value : integer := 0; + sim_init_status : integer := 0; + sim_init_config_is_application : string := "false"; + sim_init_watchdog_enabled : string := "false"; + operation_mode : string := "active_serial_remote"; + lpm_type : string := "cycloneiv_rublock" + ); + port + ( + clk : in std_logic; + shiftnld : in std_logic; + captnupdt : in std_logic; + regin : in std_logic; + rsttimer : in std_logic; + rconfig : in std_logic; + regout : out std_logic + ); + +end cycloneiv_rublock; + +architecture architecture_rublock of cycloneiv_rublock is + +begin + +end architecture_rublock; + + + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_termination +-- +-- Description : Cyclone IV GX Termination Atom VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY cycloneiv_termination IS + GENERIC ( + pullup_control_to_core: string := "false"; + power_down : string := "true"; + test_mode : string := "false"; + left_shift_termination_code : string := "false"; + pullup_adder : integer := 0; + pulldown_adder : integer := 0; + clock_divide_by : integer := 32; -- 1, 4, 32 + runtime_control : string := "false"; + shift_vref_rup : string := "true"; + shift_vref_rdn : string := "true"; + shifted_vref_control : string := "true"; + lpm_type : string := "cycloneiv_termination"); + PORT ( + rup : IN std_logic := '0'; + rdn : IN std_logic := '0'; + terminationclock : IN std_logic := '0'; + terminationclear : IN std_logic := '0'; + devpor : IN std_logic := '1'; + devclrn : IN std_logic := '1'; + comparatorprobe : OUT std_logic; + terminationcontrolprobe : OUT std_logic; + calibrationdone : OUT std_logic; + terminationcontrol : OUT std_logic_vector(15 DOWNTO 0)); +END cycloneiv_termination; + +ARCHITECTURE cycloneiv_termination_arch OF cycloneiv_termination IS + SIGNAL rup_compout : std_logic := '0'; + SIGNAL rdn_compout : std_logic := '1'; + +BEGIN + calibrationdone <= '1'; -- power-up calibration status + + comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout; + rup_compout <= rup; + rdn_compout <= not rdn; + +END cycloneiv_termination_arch; +------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_jtag +-- +-- Description : Cyclone IV GX JTAG VHDL Simulation model +-- +------------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_jtag is + generic ( + lpm_type : string := "cycloneiv_jtag" + ); + port ( + tms : in std_logic := '0'; + tck : in std_logic := '0'; + tdi : in std_logic := '0'; + tdoutap : in std_logic := '0'; + tdouser : in std_logic := '0'; + tdo: out std_logic; + tmsutap: out std_logic; + tckutap: out std_logic; + tdiutap: out std_logic; + shiftuser: out std_logic; + clkdruser: out std_logic; + updateuser: out std_logic; + runidleuser: out std_logic; + usr1user: out std_logic + ); +end cycloneiv_jtag; + +architecture architecture_jtag of cycloneiv_jtag is +begin + +end architecture_jtag; + +------------------------------------------------------------------- +-- +-- Entity Name : cycloneiv_crcblock +-- +-- Description : Cyclone IV GX CRCBLOCK VHDL Simulation model +-- +------------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_crcblock is + generic ( + oscillator_divider : integer := 1; + lpm_type : string := "cycloneiv_crcblock" + ); + port ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + ldsrc : in std_logic := '0'; + crcerror : out std_logic; + regout : out std_logic + ); +end cycloneiv_crcblock; + +architecture architecture_crcblock of cycloneiv_crcblock is +begin + crcerror <= '0'; + regout <= '0'; + +end architecture_crcblock; + +-- +-- +-- CYCLONEIV_OSCILLATOR Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_oscillator is + generic + ( + lpm_type: string := "cycloneiv_oscillator"; + TimingChecksOn: Boolean := True; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01; + tipd_oscena : VitalDelayType01 := DefPropDelay01 + ); + port + ( + oscena : in std_logic; + observableoutputport: out std_logic; + clkout : out std_logic + ); + +end cycloneiv_oscillator; + +architecture architecture_oscillator of cycloneiv_oscillator is + signal oscena_ipd : std_logic; + signal int_osc : std_logic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (oscena_ipd, oscena, tipd_oscena); + end block; + + VITAL_osc : process(oscena_ipd, int_osc) + variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock + variable osc_VitalGlitchData : VitalGlitchDataType; + begin + if (oscena_ipd = '1') then + if ((int_osc = '0') or (int_osc = '1')) then + int_osc <= not int_osc after OSC_PW; + else + int_osc <= '0' after OSC_PW; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => clkout, + OutSignalName => "osc", + OutTemp => int_osc, + Paths => (0 => (InputChangeTime => oscena_ipd'last_event, + PathDelay => tpd_oscena_clkout_posedge, + PathCondition => (oscena_ipd = '1'))), + GlitchData => osc_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + end process; + +end architecture_oscillator; + + +-- +-- +-- CYCLONEIV_CONTROLLER Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.cycloneiv_atom_pack.all; + +entity cycloneiv_controller is + generic + ( + lpm_type: string := "cycloneiv_controller" + ); + port + ( + usermode : out std_logic; + nceout : out std_logic + ); + +end cycloneiv_controller; + +architecture architecture_apfcontroller of cycloneiv_controller is + + +begin + +end architecture_apfcontroller; + + +library IEEE; +use IEEE.std_logic_1164.all; + +entity cycloneiv_asmiblock is + generic ( + lpm_type : string := "cycloneiv_asmiblock"; + enable_sim : string := "false" + ); + port ( + dclkin : in std_logic; + scein : in std_logic; + oe : in std_logic; + sdoin : in std_logic; + data0out: out std_logic + ); +end entity cycloneiv_asmiblock; + +architecture behavior of cycloneiv_asmiblock is + +-- component asmi_sim_model is port(dclk: in std_logic; ncso: in std_logic; asdo: in std_logic; data0: out std_logic); end component; + +signal dclk_wire, ncs, data0 : std_logic; + +begin + +process(dclkin, scein, oe, data0) +begin + if (oe = '0') then + dclk_wire <= dclkin; + ncs <= scein; + data0 <= sdoin; + elsif (oe = '1' ) then + dclk_wire <= 'Z'; + ncs <= 'Z'; + data0 <= 'Z'; + else + dclk_wire <= 'X'; + ncs <= 'X'; + data0 <= 'X'; + end if; +end process; + +----------------------------------------------------- +-- Instantiate module to represent Active Serial pins +----------------------------------------------------- +-- sim_model_inst : asmi_sim_model port map(dclk => dclk_wire, ncso => ncs, asdo => data0, data0 => data0out); + +end architecture; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneiv_mn_cntr +-- +-- Description : Timing simulation model for the M and N counter. This is a +-- common model for the input counter and the loop feedback +-- counter of the Cyclone IV GX PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; + +ENTITY cycloneiv_mn_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END cycloneiv_mn_cntr; + +ARCHITECTURE behave of cycloneiv_mn_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneiv_post_divider +-- +-- Description : Timing simulation model that models the icdrclk output. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; + +ENTITY cycloneiv_post_divider is + GENERIC ( dpa_divider : integer := 1 + ); + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic + ); +END cycloneiv_post_divider; + +ARCHITECTURE behave of cycloneiv_post_divider is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + variable modules : integer := 0; + variable init : boolean := true; + begin + if (init = true) then + if (dpa_divider = 0) then + modules := 1; + else + modules := dpa_divider; + end if; + init := false; + end if; + + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modules) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneiv_scale_cntr +-- +-- Description : Timing simulation model for the output scale-down counters. +-- This is a common model for the C0, C1, C2, C3, C4 and C5 +-- output counters of the Cyclone IV GX PLL. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; + +ENTITY cycloneiv_scale_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0; + cout : OUT std_logic + ); +END cycloneiv_scale_cntr; + +ARCHITECTURE behave of cycloneiv_scale_cntr is +begin + process (clk, reset) + variable tmp_cout : std_logic := '0'; + variable count : integer := 1; + variable output_shift_count : integer := 1; + variable first_rising_edge : boolean := false; + begin + if (reset = '1') then + count := 1; + output_shift_count := 1; + tmp_cout := '0'; + first_rising_edge := false; + elsif (clk'event) then + if (mode = " off") then + tmp_cout := '0'; + elsif (mode = "bypass") then + tmp_cout := clk; + first_rising_edge := true; + elsif (not first_rising_edge) then + if (clk = '1') then + if (output_shift_count = initial) then + tmp_cout := clk; + first_rising_edge := true; + else + output_shift_count := output_shift_count + 1; + end if; + end if; + elsif (output_shift_count < initial) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + end if; + else + count := count + 1; + if (mode = " even" and (count = (high*2) + 1)) then + tmp_cout := '0'; + elsif (mode = " odd" and (count = high*2)) then + tmp_cout := '0'; + elsif (count = (high + low)*2 + 1) then + tmp_cout := '1'; + count := 1; -- reset count + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; + +end behave; + +--BEGIN MF PORTING DELETE +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneiv_pll_reg +-- +-- Description : Simulation model for a simple DFF. +-- This is required for the generation of the bit slip-signals. +-- No timing, powers upto 0. +-- +--///////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY cycloneiv_pll_reg is + PORT( clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic + ); +end cycloneiv_pll_reg; + +ARCHITECTURE behave of cycloneiv_pll_reg is +begin + process (clk, prn, clrn) + variable q_reg : std_logic := '0'; + begin + if (prn = '0') then + q_reg := '1'; + elsif (clrn = '0') then + q_reg := '0'; + elsif (clk'event and clk = '1' and (ena = '1')) then + q_reg := D; + end if; + + Q <= q_reg; + end process; +end behave; +--END MF PORTING DELETE +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneiv_pll +-- +-- Description : Timing simulation model for the Cyclone IV GX PLL. +-- In the functional mode, it is also the model for the altpll +-- megafunction. +-- +-- Limitations : Does not support Spread Spectrum and Bandwidth. +-- +-- Outputs : Up to 10 output clocks, each defined by its own set of +-- parameters. Locked output (active high) indicates when the +-- PLL locks. clkbad and activeclock are used for +-- clock switchover to indicate which input clock has gone +-- bad, when the clock switchover initiates and which input +-- clock is being used as the reference, respectively. +-- scandataout is the data output of the serial scan chain. +-- +--/////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE STD.TEXTIO.all; +USE work.cycloneiv_atom_pack.all; +USE work.cycloneiv_pllpack.all; +USE work.cycloneiv_mn_cntr; +USE work.cycloneiv_scale_cntr; +USE work.cycloneiv_dffe; +USE work.cycloneiv_pll_reg; + + +ENTITY cycloneiv_pll is + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM + compensate_clock : string := "clock0"; + + inclk0_input_frequency : integer := 0; + inclk1_input_frequency : integer := 0; + + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + use_dc_coupling : string := "false"; + + lock_c : integer := 4; + sim_gate_lock_device_behavior : string := "off"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_window : time := 5 ps; + test_bypass_lock_detect : string := "off"; + + + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 0; + clk0_divide_by : integer := 0; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 0; + clk1_divide_by : integer := 0; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 0; + clk2_divide_by : integer := 0; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 0; + clk3_divide_by : integer := 0; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 0; + clk4_divide_by : integer := 0; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + + feedback_source : integer := 0; + feedback_external_loop_divider : string := "false"; + + + -- ADVANCED USER PARAMETERS + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + m_ph : integer := 0; + + clk0_counter : string := "unused"; + clk1_counter : string := "unused"; + clk2_counter : string := "unused"; + clk3_counter : string := "unused"; + clk4_counter : string := "unused"; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + vco_post_scale : integer := 1; + vco_frequency_control : string := "auto"; + vco_phase_shift_step : integer := 0; + + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 1; + + charge_pump_current : integer := 10; + loop_filter_r : string := " 1.0"; + loop_filter_c : integer := 0; + + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + lpm_type : string := "cycloneiv_pll"; + lpm_hint : string := "unused"; + + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + +-- Test only + init_block_reset_a_count : integer := 1; + init_block_reset_b_count : integer := 1; + charge_pump_current_bits : integer := 0; + lock_window_ui_bits : integer := 0; + loop_filter_c_bits : integer := 0; + loop_filter_r_bits : integer := 0; + test_counter_c0_delay_chain_bits : integer := 0; + test_counter_c1_delay_chain_bits : integer := 0; + test_counter_c2_delay_chain_bits : integer := 0; + test_counter_c3_delay_chain_bits : integer := 0; + test_counter_c4_delay_chain_bits : integer := 0; + test_counter_m_delay_chain_bits : integer := 0; + test_counter_n_delay_chain_bits : integer := 0; + test_feedback_comp_delay_chain_bits : integer := 0; + test_input_comp_delay_chain_bits : integer := 0; + test_volt_reg_output_mode_bits : integer := 0; + test_volt_reg_output_voltage_bits : integer := 0; + test_volt_reg_test_mode : string := "false"; + vco_range_detector_high_bits : integer := -1; + vco_range_detector_low_bits : integer := -1; + scan_chain_mif_file : string := ""; + + auto_settings : string := "true"; +-- Simulation only generics + family_name : string := "Cyclone IV GX"; + + -- VITAL generics + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + TimingChecksOn : Boolean := true; + InstancePath : STRING := "*"; + tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_pfdena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_fbin : VitalDelayType01 := DefPropDelay01; + tipd_scanclk : VitalDelayType01 := DefPropDelay01; + tipd_scanclkena : VitalDelayType01 := DefPropDelay01; + tipd_scandata : VitalDelayType01 := DefPropDelay01; + tipd_configupdate : VitalDelayType01 := DefPropDelay01; + tipd_clkswitch : VitalDelayType01 := DefPropDelay01; + tipd_phaseupdown : VitalDelayType01 := DefPropDelay01; + tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phasestep : VitalDelayType01 := DefPropDelay01; + tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + use_vco_bypass : string := "false" + ); + + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + fbout : out std_logic; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + clk : out std_logic_vector(4 downto 0); + phasecounterselect : in std_logic_vector(2 downto 0) := "000"; + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fref : out std_logic; + icdrclk : out std_logic + ); +END cycloneiv_pll; + +ARCHITECTURE vital_pll of cycloneiv_pll is + +TYPE int_array is ARRAY(NATURAL RANGE <>) of integer; +TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6); +TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9); +TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic; + +-- internal advanced parameter signals +signal i_vco_min : integer := vco_min * (vco_post_scale/2); +signal i_vco_max : integer := vco_max * (vco_post_scale/2); +signal i_vco_center : integer; +signal i_pfd_min : integer; +signal i_pfd_max : integer; + signal c_ph_val : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_high_val : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val : int_array(0 to 4) := (OTHERS => 1); + signal c_initial_val : int_array(0 to 4) := (OTHERS => 1); + signal c_mode_val : str_array(0 to 4); + signal clk_num : str_array(0 to 4); + +-- old values + signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_old : str_array(0 to 4); +-- hold registers + signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_hold : str_array(0 to 4); + +-- temp registers + signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0); + +signal real_lock_high : integer := 0; +signal i_clk4_counter : integer := 4; +signal i_clk3_counter : integer := 3; +signal i_clk2_counter : integer := 2; +signal i_clk1_counter : integer := 1; +signal i_clk0_counter : integer := 0; +signal i_charge_pump_current : integer; +signal i_loop_filter_r : integer; + +-- end internal advanced parameter signals + +-- CONSTANTS +CONSTANT SCAN_CHAIN : integer := 144; +CONSTANT GPP_SCAN_CHAIN : integer := 234; +CONSTANT FAST_SCAN_CHAIN : integer := 180; + CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0"); +CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2"); + +CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + +CONSTANT num_phase_taps : integer := 8; +-- signals + +signal vcc : std_logic := '1'; + +signal fbclk : std_logic; +signal refclk : std_logic; + +signal icdr_clk : std_logic; + +signal vco_over : std_logic := '0'; +signal vco_under : std_logic := '1'; + +signal pll_locked : boolean := false; + + + signal c_clk : std_logic_array(0 to 4); +signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); + +-- signals to assign values to counter params +signal m_val : integer := 1; +signal n_val : integer := 1; +signal m_ph_val : integer := 0; +signal m_ph_initial : integer := 0; +signal m_ph_val_tmp : integer := 0; +signal m_initial_val : integer := m_initial; + +signal m_mode_val : string(1 to 6) := " "; +signal n_mode_val : string(1 to 6) := " "; +signal lfc_val : integer := 0; +signal vco_cur : integer := vco_post_scale; +signal cp_curr_val : integer := 0; +signal lfr_val : string(1 to 2) := " "; + +signal cp_curr_old_bit_setting : integer := charge_pump_current_bits; +signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0'); +signal lfr_old_bit_setting : integer := loop_filter_r_bits; +signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0'); +signal lfc_old_bit_setting : integer := loop_filter_c_bits; +signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0'); + +signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true +-- old values +signal m_val_old : integer := 1; +signal n_val_old : integer := 1; +signal m_mode_val_old : string(1 to 6) := " "; +signal n_mode_val_old : string(1 to 6) := " "; +signal m_ph_val_old : integer := 0; +signal lfc_old : integer := 0; +signal vco_old : integer := 0; +signal cp_curr_old : integer := 0; +signal lfr_old : string(1 to 2) := " "; + signal num_output_cntrs : integer := 5; +signal scanclk_period : time := 1 ps; + signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + + signal clk_pfd : std_logic_vector(0 to 4); +signal clk0_tmp : std_logic; +signal clk1_tmp : std_logic; +signal clk2_tmp : std_logic; +signal clk3_tmp : std_logic; +signal clk4_tmp : std_logic; + +signal update_conf_latches : std_logic := '0'; +signal update_conf_latches_reg : std_logic := '0'; + +signal clkin : std_logic := '0'; +signal gate_locked : std_logic := '0'; +signal pfd_locked : std_logic := '0'; +signal lock : std_logic := '0'; +signal about_to_lock : boolean := false; +signal reconfig_err : boolean := false; + +signal inclk_c0 : std_logic; +signal inclk_c1 : std_logic; +signal inclk_c2 : std_logic; +signal inclk_c3 : std_logic; +signal inclk_c4 : std_logic; +signal inclk_m : std_logic; +signal devpor : std_logic; +signal devclrn : std_logic; + +signal inclk0_ipd : std_logic; +signal inclk1_ipd : std_logic; +signal pfdena_ipd : std_logic; +signal areset_ipd : std_logic; +signal fbin_ipd : std_logic; +signal scanclk_ipd : std_logic; +signal scanclkena_ipd, scanclkena_reg : std_logic; +signal scandata_ipd : std_logic; +signal clkswitch_ipd : std_logic; + signal phasecounterselect_ipd : std_logic_vector(2 downto 0); +signal phaseupdown_ipd : std_logic; +signal phasestep_ipd : std_logic; +signal configupdate_ipd : std_logic; +-- registered signals + +signal sig_offset : time := 0 ps; +signal sig_refclk_time : time := 0 ps; +signal sig_fbclk_period : time := 0 ps; +signal sig_vco_period_was_phase_adjusted : boolean := false; +signal sig_phase_adjust_was_scheduled : boolean := false; +signal sig_stop_vco : std_logic := '0'; +signal sig_m_times_vco_period : time := 0 ps; +signal sig_new_m_times_vco_period : time := 0 ps; +signal sig_got_refclk_posedge : boolean := false; +signal sig_got_fbclk_posedge : boolean := false; +signal sig_got_second_refclk : boolean := false; + +signal m_delay : integer := 0; +signal n_delay : integer := 0; + +signal inclk1_tmp : std_logic := '0'; + + +signal reset_low : std_logic := '0'; + +-- Phase Reconfig + + SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0); + +SIGNAL phaseupdown_reg : std_logic := '0'; +SIGNAL phasestep_reg : std_logic := '0'; +SIGNAL phasestep_high_count : integer := 0; +SIGNAL update_phase : std_logic := '0'; + +signal scandataout_tmp : std_logic := '0'; +signal scandata_in : std_logic := '0'; +signal scandata_out : std_logic := '0'; +signal scandone_tmp : std_logic := '1'; +signal initiate_reconfig : std_logic := '0'; + +signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; + +signal schedule_vco : std_logic := '0'; + +signal areset_ena_sig : std_logic := '0'; +signal pll_in_test_mode : boolean := false; +signal pll_has_just_been_reconfigured : boolean := false; + + signal inclk_c_from_vco : std_logic_array(0 to 4); + +signal inclk_m_from_vco : std_logic; + +SIGNAL inclk0_period : time := 0 ps; +SIGNAL last_inclk0_period : time := 0 ps; +SIGNAL last_inclk0_edge : time := 0 ps; +SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0'; +SIGNAL inclk1_period : time := 0 ps; +SIGNAL last_inclk1_period : time := 0 ps; +SIGNAL last_inclk1_edge : time := 0 ps; +SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0'; + + + +COMPONENT cycloneiv_mn_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END COMPONENT; + +COMPONENT cycloneiv_post_divider + GENERIC ( dpa_divider : integer := 0 + ); + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic + ); +END COMPONENT; + + +COMPONENT cycloneiv_scale_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0 + ); +END COMPONENT; + +COMPONENT cycloneiv_dffe + GENERIC( + TimingChecksOn: Boolean := true; + InstancePath: STRING := "*"; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tipd_D : VitalDelayType01 := DefPropDelay01; + tipd_CLRN : VitalDelayType01 := DefPropDelay01; + tipd_PRN : VitalDelayType01 := DefPropDelay01; + tipd_CLK : VitalDelayType01 := DefPropDelay01; + tipd_ENA : VitalDelayType01 := DefPropDelay01); + + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +COMPONENT cycloneiv_pll_reg + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +begin + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + WireDelay : block + begin + VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0)); + VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1)); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena); + VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk); + VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena); + VitalWireDelay (scandata_ipd, scandata, tipd_scandata); + VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate); + VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch); + VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown); + VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep); + VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0)); + VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1)); + VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2)); + + end block; + +inclk_m <= fbclk when m_test_source = 0 else + refclk when m_test_source = 1 else + inclk_m_from_vco; + + areset_ena_sig <= areset_ipd or sig_stop_vco; + + + pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or + c1_test_source /= -1 or c2_test_source /= -1 or + c3_test_source /= -1 or c4_test_source /= -1) + else false; + + real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0; + m1 : cycloneiv_mn_cntr + port map ( clk => inclk_m, + reset => areset_ena_sig, + cout => fbclk, + initial_value => m_initial_val, + modulus => m_val, + time_delay => m_delay + ); + + -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed + -- in different simulation deltas. + inclk1_tmp <= inclk1_ipd; + + -- Calculate the inclk0 period + PROCESS + VARIABLE inclk0_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1'); + IF (first_inclk0_edge_detect = '0') THEN + first_inclk0_edge_detect <= '1'; + ELSE + last_inclk0_period <= inclk0_period; + inclk0_period_tmp := NOW - last_inclk0_edge; + END IF; + last_inclk0_edge <= NOW; + inclk0_period <= inclk0_period_tmp; + END PROCESS; + + + -- Calculate the inclk1 period + PROCESS + VARIABLE inclk1_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1'); + IF (first_inclk1_edge_detect = '0') THEN + first_inclk1_edge_detect <= '1'; + ELSE + last_inclk1_period <= inclk1_period; + inclk1_period_tmp := NOW - last_inclk1_edge; + END IF; + last_inclk1_edge <= NOW; + inclk1_period <= inclk1_period_tmp; + END PROCESS; + + process (inclk0_ipd, inclk1_tmp, clkswitch_ipd) + variable input_value : std_logic := '0'; + variable current_clock : integer := 0; + variable clk0_count, clk1_count : integer := 0; + variable clk0_is_bad, clk1_is_bad : std_logic := '0'; + variable primary_clk_is_bad : boolean := false; + variable current_clk_is_bad : boolean := false; + variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; + variable switch_over_count : integer := 0; + variable active_clock : std_logic := '0'; + variable external_switch : boolean := false; + variable diff_percent_period : integer := 0; + variable buf : line; + variable switch_clock : boolean := false; + + begin + if (now = 0 ps) then + if (switch_over_type = "manual" and clkswitch_ipd = '1') then + current_clock := 1; + active_clock := '1'; + end if; + end if; + if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then + external_switch := true; + elsif (switch_over_type = "manual") then + if (clkswitch_ipd'event and clkswitch_ipd = '1') then + switch_clock := true; + elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then + switch_clock := false; + end if; + end if; + + if (switch_clock = true) then + if (inclk0_ipd'event or inclk1_tmp'event) then + if (current_clock = 0) then + current_clock := 1; + active_clock := '1'; + clkin <= transport inclk1_tmp; + elsif (current_clock = 1) then + current_clock := 0; + active_clock := '0'; + clkin <= transport inclk0_ipd; + end if; + switch_clock := false; + end if; + end if; + + -- save the current inclk event value + if (inclk0_ipd'event) then + input_value := inclk0_ipd; + elsif (inclk1_tmp'event) then + input_value := inclk1_tmp; + end if; + + -- check if either input clk is bad + if (inclk0_ipd'event and inclk0_ipd = '1') then + clk0_count := clk0_count + 1; + clk0_is_bad := '0'; + clk1_count := 0; + if (clk0_count > 2) then + -- no event on other clk for 2 cycles + clk1_is_bad := '1'; + if (current_clock = 1) then + current_clk_is_bad := true; + end if; + end if; + end if; + if (inclk1_tmp'event and inclk1_tmp = '1') then + clk1_count := clk1_count + 1; + clk1_is_bad := '0'; + clk0_count := 0; + if (clk1_count > 2) then + -- no event on other clk for 2 cycles + clk0_is_bad := '1'; + if (current_clock = 0) then + current_clk_is_bad := true; + end if; + end if; + end if; + + -- check if the bad clk is the primary clock + if (clk0_is_bad = '1') then + primary_clk_is_bad := true; + else + primary_clk_is_bad := false; + end if; + + -- actual switching + if (inclk0_ipd'event and current_clock = 0) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk0_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk0_ipd; + end if; + else + clkin <= transport inclk0_ipd; + end if; + elsif (inclk1_tmp'event and current_clock = 1) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk1_tmp = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk1_tmp; + end if; + else + clkin <= transport inclk1_tmp; + end if; + else + if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then + switch_over_count := switch_over_count + 1; + end if; + if ((input_value = '0')) then + if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then + got_curr_clk_falling_edge_after_clkswitch := false; + + if (areset_ipd = '0') then + if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then + diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period; + elsif (inclk0_period /= 0 ps) then + diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period; + end if; + + if((diff_percent_period > 20)and ( switch_over_type = "auto")) then + WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.")); + writeline(output, buf); + end if; + end if; + + if (current_clock = 0) then + current_clock := 1; + else + current_clock := 0; + end if; + active_clock := not active_clock; + switch_over_count := 0; + external_switch := false; + current_clk_is_bad := false; + else + if(switch_over_type = "auto") then + if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then + current_clock := 1; + active_clock := not active_clock; + end if; + + if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then + current_clock := 0; + active_clock := not active_clock; + end if; + end if; + end if; + + end if; + end if; + + -- schedule outputs + clkbad(0) <= clk0_is_bad; + clkbad(1) <= clk1_is_bad; + activeclock <= active_clock; + + end process; + + + n1 : cycloneiv_mn_cntr + port map ( + clk => clkin, + reset => areset_ipd, + cout => refclk, + initial_value => n_val, + modulus => n_val); + + d1 : cycloneiv_post_divider + generic map ( dpa_divider => dpa_divider) + port map ( + clk => inclk_m_from_vco, + reset => areset_ipd, + cout => icdr_clk); + + +inclk_c0 <= refclk when c0_test_source = 1 else + fbclk when c0_test_source = 0 else + inclk_c_from_vco(0); + + + c0 : cycloneiv_scale_cntr + port map ( + clk => inclk_c0, + reset => areset_ena_sig, + cout => c_clk(0), + initial => c_initial_val(0), + high => c_high_val(0), + low => c_low_val(0), + mode => c_mode_val(0), + ph_tap => c_ph_val(0)); + + inclk_c1 <= refclk when c1_test_source = 1 else + fbclk when c1_test_source = 0 else + c_clk(0) when c1_use_casc_in = "on" else + inclk_c_from_vco(1); + + + c1 : cycloneiv_scale_cntr + port map ( + clk => inclk_c1, + reset => areset_ena_sig, + cout => c_clk(1), + initial => c_initial_val(1), + high => c_high_val(1), + low => c_low_val(1), + mode => c_mode_val(1), + ph_tap => c_ph_val(1)); + +inclk_c2 <= refclk when c2_test_source = 1 else + fbclk when c2_test_source = 0 else + c_clk(1) when c2_use_casc_in = "on" else + inclk_c_from_vco(2); + + c2 : cycloneiv_scale_cntr + port map ( + clk => inclk_c2, + reset => areset_ena_sig, + cout => c_clk(2), + initial => c_initial_val(2), + high => c_high_val(2), + low => c_low_val(2), + mode => c_mode_val(2), + ph_tap => c_ph_val(2)); + + + inclk_c3 <= refclk when c3_test_source = 1 else + fbclk when c3_test_source = 0 else + c_clk(2) when c3_use_casc_in = "on" else + inclk_c_from_vco(3); + + c3 : cycloneiv_scale_cntr + port map ( + clk => inclk_c3, + reset => areset_ena_sig, + cout => c_clk(3), + initial => c_initial_val(3), + high => c_high_val(3), + low => c_low_val(3), + mode => c_mode_val(3), + ph_tap => c_ph_val(3)); + + inclk_c4 <= refclk when c4_test_source = 1 else + fbclk when c4_test_source = 0 else + c_clk(3) when (c4_use_casc_in = "on") else + inclk_c_from_vco(4); + + c4 : cycloneiv_scale_cntr + port map ( + clk => inclk_c4, + reset => areset_ena_sig, + cout => c_clk(4), + initial => c_initial_val(4), + high => c_high_val(4), + low => c_low_val(4), + mode => c_mode_val(4), + ph_tap => c_ph_val(4)); + + + + + + + + + + + + process(scandone_tmp, lock) + begin + if (scandone_tmp'event and (scandone_tmp = '1')) then + pll_has_just_been_reconfigured <= true; + elsif (lock'event and (lock = '1')) then + pll_has_just_been_reconfigured <= false; + end if; + end process; + + process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco) + variable c0_got_first_rising_edge : boolean := false; + variable c0_count : integer := 2; + variable c0_initial_count : integer := 1; + variable c0_tmp, c1_tmp : std_logic := '0'; + variable c1_got_first_rising_edge : boolean := false; + variable c1_count : integer := 2; + variable c1_initial_count : integer := 1; + begin + if (areset_ipd = '1' or sig_stop_vco = '1') then + c0_count := 2; + c1_count := 2; + c0_initial_count := 1; + c1_initial_count := 1; + c0_got_first_rising_edge := false; + c1_got_first_rising_edge := false; + else + if (not c0_got_first_rising_edge) then + if (inclk_c0'event and inclk_c0 = '1') then + if (c0_initial_count = c_initial_val(0)) then + c0_got_first_rising_edge := true; + else + c0_initial_count := c0_initial_count + 1; + end if; + end if; + elsif (inclk_c0'event) then + c0_count := c0_count + 1; + if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then + c0_count := 1; + end if; + end if; + if (inclk_c0'event and inclk_c0 = '0') then + if (c0_count = 1) then + c0_tmp := '1'; + c0_got_first_rising_edge := false; + else + c0_tmp := '0'; + end if; + end if; + + if (not c1_got_first_rising_edge) then + if (inclk_c1'event and inclk_c1 = '1') then + if (c1_initial_count = c_initial_val(1)) then + c1_got_first_rising_edge := true; + else + c1_initial_count := c1_initial_count + 1; + end if; + end if; + elsif (inclk_c1'event) then + c1_count := c1_count + 1; + if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then + c1_count := 1; + end if; + end if; + if (inclk_c1'event and inclk_c1 = '0') then + if (c1_count = 1) then + c1_tmp := '1'; + c1_got_first_rising_edge := false; + else + c1_tmp := '0'; + end if; + end if; + end if; + + end process; + + + locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE + lock; + + + process (scandone_tmp) + variable buf : line; + begin + if (scandone_tmp'event and scandone_tmp = '1') then + if (reconfig_err = false) then + ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note; + write (buf, string'(" N modulus = ")); + write (buf, n_val); + write (buf, string'(" ( ")); + write (buf, n_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M modulus = ")); + write (buf, m_val); + write (buf, string'(" ( ")); + write (buf, m_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M ph_tap = ")); + write (buf, m_ph_val); + write (buf, string'(" ( ")); + write (buf, m_ph_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + for i in 0 to (num_output_cntrs-1) loop + write (buf, clk_num(i)); + write (buf, string'(" : ")); + write (buf, cntrs(i)); + write (buf, string'(" : high = ")); + write (buf, c_high_val(i)); + write (buf, string'(" (")); + write (buf, c_high_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , low = ")); + write (buf, c_low_val(i)); + write (buf, string'(" (")); + write (buf, c_low_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , mode = ")); + write (buf, c_mode_val(i)); + write (buf, string'(" (")); + write (buf, c_mode_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , phase tap = ")); + write (buf, c_ph_val(i)); + write (buf, string'(" (")); + write (buf, c_ph_val_old(i)); + write (buf, string'(") ")); + writeline(output, buf); + end loop; + + IF (pll_reconfig_display_full_setting) THEN + write (buf, string'(" Charge Pump Current (uA) = ")); + write (buf, cp_curr_val); + write (buf, string'(" ( ")); + write (buf, cp_curr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (pF) = ")); + write (buf, lfc_val); + write (buf, string'(" ( ")); + write (buf, lfc_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (Kohm) = ")); + write (buf, lfr_val); + write (buf, string'(" ( ")); + write (buf, lfr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + + ELSE + write (buf, string'(" Charge Pump Current (bit setting) = ")); + write (buf, alt_conv_integer(cp_curr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, cp_curr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (bit setting) = ")); + write (buf, alt_conv_integer(lfc_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfc_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (bit setting) = ")); + write (buf, alt_conv_integer(lfr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + END IF; + cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting); + lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting); + lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting); + else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning; + end if; + end if; + + end process; + + update_conf_latches <= configupdate_ipd; + + + process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd) + variable init : boolean := true; + variable low, high : std_logic_vector(7 downto 0); + variable low_fast, high_fast : std_logic_vector(3 downto 0); + variable mode : string(1 to 6) := "bypass"; + variable is_error : boolean := false; + variable m_tmp, n_tmp : std_logic_vector(8 downto 0); + variable lfr_val_tmp : string(1 to 2) := " "; + + variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1); + variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1); + variable c_mode_val_tmp : str_array(0 to 4); + variable m_val_tmp : integer := 0; + variable c0_rising_edge_transfer_done : boolean := false; + variable c1_rising_edge_transfer_done : boolean := false; + variable c2_rising_edge_transfer_done : boolean := false; + variable c3_rising_edge_transfer_done : boolean := false; + variable c4_rising_edge_transfer_done : boolean := false; + + -- variables for scaling of multiply_by and divide_by values + variable i_clk0_mult_by : integer := 1; + variable i_clk0_div_by : integer := 1; + variable i_clk1_mult_by : integer := 1; + variable i_clk1_div_by : integer := 1; + variable i_clk2_mult_by : integer := 1; + variable i_clk2_div_by : integer := 1; + variable i_clk3_mult_by : integer := 1; + variable i_clk3_div_by : integer := 1; + variable i_clk4_mult_by : integer := 1; + variable i_clk4_div_by : integer := 1; + variable max_d_value : integer := 1; + variable new_multiplier : integer := 1; + + -- internal variables for storing the phase shift number.(used in lvds mode only) + variable i_clk0_phase_shift : integer := 1; + variable i_clk1_phase_shift : integer := 1; + variable i_clk2_phase_shift : integer := 1; + + -- user to advanced variables + + variable max_neg_abs : integer := 0; + variable i_m_initial : integer; + variable i_m : integer := 1; + variable i_n : integer := 1; + variable i_c_high : int_array(0 to 4); + variable i_c_low : int_array(0 to 4); + variable i_c_initial : int_array(0 to 4); + variable i_c_ph : int_array(0 to 4); + variable i_c_mode : str_array(0 to 4); + variable i_m_ph : integer; + variable output_count : integer; + variable new_divisor : integer; + + variable clk0_cntr : string(1 to 6) := " c0"; + variable clk1_cntr : string(1 to 6) := " c1"; + variable clk2_cntr : string(1 to 6) := " c2"; + variable clk3_cntr : string(1 to 6) := " c3"; + variable clk4_cntr : string(1 to 6) := " c4"; + + variable i_clk4_cntr : integer := 4; + variable i_clk3_cntr : integer := 3; + variable i_clk2_cntr : integer := 2; + variable i_clk1_cntr : integer := 1; + variable i_clk0_cntr : integer := 0; + + variable fbk_cntr : string(1 to 2); + variable fbk_cntr_index : integer; + variable start_bit : integer; + variable quiet_time : time := 0 ps; + variable slowest_clk_old : time := 0 ps; + variable slowest_clk_new : time := 0 ps; + + variable i : integer := 0; + variable j : integer := 0; + variable scanread_active_edge : time := 0 ps; + variable got_first_scanclk : boolean := false; + variable scanclk_last_rising_edge : time := 0 ps; + variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + variable index : integer := 0; + variable Tviol_scandata_scanclk : std_ulogic := '0'; + variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_scanclkena_scanclk : std_ulogic := '0'; + variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit; + variable scan_chain_length : integer := GPP_SCAN_CHAIN; + variable tmp_rem : integer := 0; + variable scanclk_cycles : integer := 0; + variable lfc_tmp : std_logic_vector(1 downto 0); + variable lfr_tmp : std_logic_vector(5 downto 0); + variable lfr_int : integer := 0; + + variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0); + variable buf : line; + variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0'); + variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0'); + + variable clk_index : integer := 0; + + function slowest_clk ( + C0 : integer; C0_mode : string(1 to 6); + C1 : integer; C1_mode : string(1 to 6); + C2 : integer; C2_mode : string(1 to 6); + C3 : integer; C3_mode : string(1 to 6); + C4 : integer; C4_mode : string(1 to 6); + C5 : integer; C5_mode : string(1 to 6); + C6 : integer; C6_mode : string(1 to 6); + C7 : integer; C7_mode : string(1 to 6); + C8 : integer; C8_mode : string(1 to 6); + C9 : integer; C9_mode : string(1 to 6); + refclk : time; m_mod : integer) return time is + variable max_modulus : integer := 1; + variable q_period : time := 0 ps; + variable refclk_int : integer := 0; + begin + if (C0_mode /= "bypass" and C0_mode /= " off") then + max_modulus := C0; + end if; + if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then + max_modulus := C1; + end if; + if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then + max_modulus := C2; + end if; + if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then + max_modulus := C3; + end if; + if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then + max_modulus := C4; + end if; + if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then + max_modulus := C5; + end if; + if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then + max_modulus := C6; + end if; + if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then + max_modulus := C7; + end if; + if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then + max_modulus := C8; + end if; + if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then + max_modulus := C9; + end if; + + refclk_int := refclk / 1 ps; + if (m_mod /= 0) then + q_period := (refclk_int * max_modulus / m_mod) * 1 ps; + end if; + return (2*q_period); + end slowest_clk; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + + function extract_cntr_string (arg:string) return string is + variable str : string(1 to 6) := " c0"; + begin + if (arg = "c0") then + str := " c0"; + elsif (arg = "c1") then + str := " c1"; + elsif (arg = "c2") then + str := " c2"; + elsif (arg = "c3") then + str := " c3"; + elsif (arg = "c4") then + str := " c4"; + elsif (arg = "c5") then + str := " c5"; + elsif (arg = "c6") then + str := " c6"; + elsif (arg = "c7") then + str := " c7"; + elsif (arg = "c8") then + str := " c8"; + elsif (arg = "c9") then + str := " c9"; + else str := " c0"; + + end if; + + return str; + + end extract_cntr_string; + + function extract_cntr_index (arg:string) return integer is + variable index : integer := 0; + begin + if (arg(6) = '0') then + index := 0; + elsif (arg(6) = '1') then + index := 1; + elsif (arg(6) = '2') then + index := 2; + elsif (arg(6) = '3') then + index := 3; + elsif (arg(6) = '4') then + index := 4; + elsif (arg(6) = '5') then + index := 5; + elsif (arg(6) = '6') then + index := 6; + elsif (arg(6) = '7') then + index := 7; + elsif (arg(6) = '8') then + index := 8; + else index := 9; + end if; + + return index; + end extract_cntr_index; + + function output_cntr_num (arg:string) return string is + variable str : string(1 to 6) := "unused"; + begin + if (arg = "c0") then + str := " clk0"; + elsif (arg = "c1") then + str := " clk1"; + elsif (arg = "c2") then + str := " clk2"; + elsif (arg = "c3") then + str := " clk3"; + elsif (arg = "c4") then + str := " clk4"; + elsif (arg = "c5") then + str := " clk5"; + elsif (arg = "c6") then + str := " clk6"; + elsif (arg = "c7") then + str := " clk7"; + elsif (arg = "c8") then + str := " clk8"; + elsif (arg = "c9") then + str := " clk9"; + else str := "unused"; + end if; + return str; + end output_cntr_num; + + begin + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val <= i_c_ph; + END IF; + + if (init) then + if (m = 0) then + clk4_cntr := " c4"; + clk3_cntr := " c3"; + clk2_cntr := " c2"; + clk1_cntr := " c1"; + clk0_cntr := " c0"; + else + clk4_cntr := extract_cntr_string(clk4_counter); + clk3_cntr := extract_cntr_string(clk3_counter); + clk2_cntr := extract_cntr_string(clk2_counter); + clk1_cntr := extract_cntr_string(clk1_counter); + clk0_cntr := extract_cntr_string(clk0_counter); + end if; + + clk_num(4) <= output_cntr_num(clk4_counter); + clk_num(3) <= output_cntr_num(clk3_counter); + clk_num(2) <= output_cntr_num(clk2_counter); + clk_num(1) <= output_cntr_num(clk1_counter); + clk_num(0) <= output_cntr_num(clk0_counter); + + i_clk0_counter <= extract_cntr_index(clk0_cntr); + i_clk1_counter <= extract_cntr_index(clk1_cntr); + i_clk2_counter <= extract_cntr_index(clk2_cntr); + i_clk3_counter <= extract_cntr_index(clk3_cntr); + i_clk4_counter <= extract_cntr_index(clk4_cntr); + + i_clk0_cntr := extract_cntr_index(clk0_cntr); + i_clk1_cntr := extract_cntr_index(clk1_cntr); + i_clk2_cntr := extract_cntr_index(clk2_cntr); + i_clk3_cntr := extract_cntr_index(clk3_cntr); + i_clk4_cntr := extract_cntr_index(clk4_cntr); + + if (m = 0) then -- convert user parameters to advanced + -- set the limit of the divide_by value that can be returned by + -- the following function. + max_d_value := 500; + + -- scale down the multiply_by and divide_by values provided by the design + -- before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + + if (vco_frequency_control = "manual_phase") then + find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step, + i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + i_clk0_div_by, i_clk1_div_by, + i_clk2_div_by, i_clk3_div_by, + i_clk4_div_by, + 1,1,1,1,1, + clk0_counter, clk1_counter, + clk2_counter, clk3_counter, + clk4_counter, + "unused","unused","unused","unused","unused", + i_m, i_n); + elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then + i_n := vco_divide_by; + i_m := vco_multiply_by; + elsif ((dpa_multiply_by /= 0) and (dpa_divide_by /= 0)) then + i_n := dpa_divide_by; + i_m := dpa_multiply_by; + else + i_n := 1; + + if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then + i_m := i_clk0_mult_by; + else + i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + inclk0_input_frequency); + end if; + end if; + + if (pll_type = "flvds") then + -- Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier := clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; + i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; + i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; + else + i_clk0_phase_shift := str2int(clk0_phase_shift); + i_clk1_phase_shift := str2int(clk1_phase_shift); + i_clk2_phase_shift := str2int(clk2_phase_shift); + end if; + + max_neg_abs := maxnegabs(i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + 0, + 0, + 0, + 0, + 0 + ); + i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); + + i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + + + i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + + + + i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); + + i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + + + + else -- m /= 0 + + i_n := n; + i_m := m; + i_m_initial := m_initial; + i_m_ph := m_ph; + i_c_ph(0) := c0_ph; + i_c_ph(1) := c1_ph; + i_c_ph(2) := c2_ph; + i_c_ph(3) := c3_ph; + i_c_ph(4) := c4_ph; + i_c_high(0) := c0_high; + i_c_high(1) := c1_high; + i_c_high(2) := c2_high; + i_c_high(3) := c3_high; + i_c_high(4) := c4_high; + i_c_low(0) := c0_low; + i_c_low(1) := c1_low; + i_c_low(2) := c2_low; + i_c_low(3) := c3_low; + i_c_low(4) := c4_low; + i_c_initial(0) := c0_initial; + i_c_initial(1) := c1_initial; + i_c_initial(2) := c2_initial; + i_c_initial(3) := c3_initial; + i_c_initial(4) := c4_initial; + i_c_mode(0) := translate_string(c0_mode); + i_c_mode(1) := translate_string(c1_mode); + i_c_mode(2) := translate_string(c2_mode); + i_c_mode(3) := translate_string(c3_mode); + i_c_mode(4) := translate_string(c4_mode); + + end if; -- user to advanced conversion. + + m_initial_val <= i_m_initial; + + if ((compensate_clock = "iqtxrxclk") and (m /= 0)) then + + case feedback_source is + when 0 => clk_index := i_clk0_cntr; + when 1 => clk_index := i_clk1_cntr; + when 2 => clk_index := i_clk2_cntr; + when 3 => clk_index := i_clk3_cntr; + when 4 => clk_index := i_clk4_cntr; + when others => + ASSERT FALSE + REPORT "Invalid feedback_source value (" & int2str(feedback_source) & ")!" + SEVERITY ERROR; + end case; + + if(feedback_external_loop_divider = "true") then + m_val <= i_m * (i_c_high(clk_index) + i_c_low(clk_index)) * 2; + m_val_tmp := i_m * (i_c_high(clk_index) + i_c_low(clk_index)) * 2; + else + m_val <= i_m * (i_c_high(clk_index) + i_c_low(clk_index)); + m_val_tmp := i_m * (i_c_high(clk_index) + i_c_low(clk_index)); + end if; + else + m_val <= i_m; + m_val_tmp := i_m; + end if; + + n_val <= i_n; + + + if (i_m = 1) then + m_mode_val <= "bypass"; + else + m_mode_val <= " "; + end if; + if (i_n = 1) then + n_mode_val <= "bypass"; + else + n_mode_val <= " "; + end if; + + m_ph_val <= i_m_ph; + m_ph_initial <= i_m_ph; + + + for i in 0 to 4 loop + if (i_c_mode(i) = "bypass") then + if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then + i_c_high(i) := 16; + i_c_low(i) := 16; + else + i_c_high(i) := 256; + i_c_low(i) := 256; + end if; + end if; + c_ph_val(i) <= i_c_ph(i); + c_initial_val(i) <= i_c_initial(i); + c_high_val(i) <= i_c_high(i); + c_low_val(i) <= i_c_low(i); + c_mode_val(i) <= i_c_mode(i); + c_high_val_tmp(i) := i_c_high(i); + c_hval(i) := i_c_high(i); + c_low_val_tmp(i) := i_c_low(i); + c_lval(i) := i_c_low(i); + c_mode_val_tmp(i) := i_c_mode(i); + c_ph_val_orig(i) <= i_c_ph(i); + c_high_val_hold(i) <= i_c_high(i); + c_low_val_hold(i) <= i_c_low(i); + c_mode_val_hold(i) <= i_c_mode(i); + end loop; + + + + scan_chain_length := SCAN_CHAIN; + + + num_output_cntrs <= 5; + + init := false; + elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then + c0_rising_edge_transfer_done := false; + c1_rising_edge_transfer_done := false; + c2_rising_edge_transfer_done := false; + c3_rising_edge_transfer_done := false; + c4_rising_edge_transfer_done := false; + update_conf_latches_reg <= '0'; + elsif (update_conf_latches'event and update_conf_latches = '1') then + initiate_reconfig <= '1'; + elsif (areset_ipd'event AND areset_ipd = '1') then + if (scandone_tmp = '0') then scandone_tmp <= '1' ; end if; + elsif (scanclk_ipd'event and scanclk_ipd = '1') then + IF (initiate_reconfig = '1') THEN + initiate_reconfig <= '0'; + ASSERT false REPORT "PLL Reprogramming Initiated" severity note; + + update_conf_latches_reg <= update_conf_latches; + reconfig_err <= false; + scandone_tmp <= '0' AFTER scanclk_period; + cp_curr_old <= cp_curr_val; + lfc_old <= lfc_val; + lfr_old <= lfr_val; + vco_old <= vco_cur; + -- LF unused : bit 0,1 + -- LF Capacitance : bits 2,3 : all values are legal + buf_scan_data := scan_data(2 TO 3); + + IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN + lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + ELSE + lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + END IF; + -- LF Resistance : bits 4-8 + -- valid values - 00000,00100,10000,10100,11000,11011,11100,11110 + IF (scan_data(4 TO 8) = "00000") THEN + lfr_val <= "20"; + ELSIF (scan_data(4 TO 8) = "00100") THEN + lfr_val <= "16"; + ELSIF (scan_data(4 TO 8) = "10000") THEN + lfr_val <= "12"; + ELSIF (scan_data(4 TO 8) = "10100") THEN + lfr_val <= "08"; + ELSIF (scan_data(4 TO 8) = "11000") THEN + lfr_val <= "06"; + ELSIF (scan_data(4 TO 8) = "11011") THEN + lfr_val <= "04"; + ELSIF (scan_data(4 TO 8) = "11100") THEN + lfr_val <= "02"; + ELSE + lfr_val <= "01"; + END IF; + + + -- VCO post scale assignment + if (scan_data(9) = '1') then -- vco_post_scale = 1 + i_vco_max <= vco_max/2; + i_vco_min <= vco_min/2; + vco_cur <= 1; + else + i_vco_max <= vco_max; + i_vco_min <= vco_min; + vco_cur <= 2; + end if; + -- CP + -- Bit 9 : CRBYPASS + -- Bit 10-14 : unused + -- Bits 15-17 : all values are legal + + buf_scan_data_2 := scan_data(15 TO 17); + cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2)); + -- save old values for display info. + + cp_curr_val_bit_setting <= scan_data(15 TO 17); + lfc_val_bit_setting <= scan_data(2 TO 3); + lfr_val_bit_setting <= scan_data(4 TO 8); + + m_val_old <= m_val; + n_val_old <= n_val; + m_mode_val_old <= m_mode_val; + n_mode_val_old <= n_mode_val; + WHILE (i < num_output_cntrs) LOOP + c_high_val_old(i) <= c_high_val(i); + c_low_val_old(i) <= c_low_val(i); + c_mode_val_old(i) <= c_mode_val(i); + i := i + 1; + END LOOP; + -- M counter + -- 1. Mode - bypass (bit 18) + + IF (scan_data(18) = '1') THEN + n_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 27) + ELSIF (scan_data(27) = '1') THEN + n_mode_val <= " odd"; + ELSE + n_mode_val <= " even"; + END IF; + + -- 2. High (bit 19-26) + + n_hi := scan_data(19 TO 26); + + -- 4. Low (bit 28-35) + + n_lo := scan_data(28 TO 35); + -- N counter + -- 1. Mode - bypass (bit 36) + + IF (scan_data(36) = '1') THEN + m_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 45) + ELSIF (scan_data(45) = '1') THEN + m_mode_val <= " odd"; + ELSE + m_mode_val <= " even"; + END IF; + + -- 2. High (bit 37-44) + + m_hi := scan_data(37 TO 44); + + -- 4. Low (bit 46-53) + + m_lo := scan_data(46 TO 53); + -- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low + + i := 0; + WHILE (i < num_output_cntrs) LOOP + -- 1. Mode - bypass + + IF (scan_data(54 + i * 18 + 0) = '1') THEN + c_mode_val_tmp(i) := "bypass"; + -- 3. Mode - odd/even + ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN + c_mode_val_tmp(i) := " odd"; + ELSE + c_mode_val_tmp(i) := " even"; + END IF; + -- 2. Hi + + high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8); + c_hval(i) := alt_conv_integer(high); + IF (c_hval(i) /= 0) THEN + c_high_val_tmp(i) := c_hval(i); + ELSE + c_high_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + + -- 4. Low + + low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17); + c_lval(i) := alt_conv_integer(low); + IF (c_lval(i) /= 0) THEN + c_low_val_tmp(i) := c_lval(i); + ELSE + c_low_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + i := i + 1; + END LOOP; + -- Legality Checks + + -- M counter value + IF(scan_data(36) /= '1') THEN + IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (m_hi /= "00000000") THEN + m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo); + ELSE + m_val_tmp := alt_conv_integer("000000001"); + END IF; + ELSE + m_val_tmp := alt_conv_integer("10000000"); + END IF; + -- N counter value + IF(scan_data(18) /= '1') THEN + IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (n_hi /= "00000000") THEN + n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo); + ELSE + n_val <= alt_conv_integer("000000001"); + END IF; + ELSE + n_val <= alt_conv_integer("10000000"); + END IF; + -- TODO : Give warnings/errors in the following cases? + -- 1. Illegal counter values (error) + -- 2. Change of mode (warning) + -- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0) + + END IF; + end if; + + + if (fbclk'event and fbclk = '1') then + m_val <= m_val_tmp; + end if; + + if (update_conf_latches_reg = '1') then + if (scanclk_ipd'event and scanclk_ipd = '1') then + c0_rising_edge_transfer_done := true; + c_high_val(0) <= c_high_val_tmp(0); + c_mode_val(0) <= c_mode_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c1_rising_edge_transfer_done := true; + c_high_val(1) <= c_high_val_tmp(1); + c_mode_val(1) <= c_mode_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c2_rising_edge_transfer_done := true; + c_high_val(2) <= c_high_val_tmp(2); + c_mode_val(2) <= c_mode_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(3) <= c_high_val_tmp(3); + c_mode_val(3) <= c_mode_val_tmp(3); + c3_rising_edge_transfer_done := true; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(4) <= c_high_val_tmp(4); + c_mode_val(4) <= c_mode_val_tmp(4); + c4_rising_edge_transfer_done := true; + end if; + + + + + + end if; + + if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then + c_low_val(0) <= c_low_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then + c_low_val(1) <= c_low_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then + c_low_val(2) <= c_low_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then + c_low_val(3) <= c_low_val_tmp(3); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then + c_low_val(4) <= c_low_val_tmp(4); + end if; + + if (update_phase = '1') then + if (vco_out(0)'event and vco_out(0) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 0) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(1)'event and vco_out(1) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 1) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(2)'event and vco_out(2) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 2) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(3)'event and vco_out(3) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 3) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(4)'event and vco_out(4) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 4) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(5)'event and vco_out(5) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 5) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(6)'event and vco_out(6) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 6) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(7)'event and vco_out(7) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 7) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + end if; + + + + if (vco_out(0)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + inclk_c_from_vco(i) <= vco_out(0); + end if; + end loop; + if (m_ph_val = 0) then + inclk_m_from_vco <= vco_out(0); + end if; + end if; + if (vco_out(1)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + inclk_c_from_vco(i) <= vco_out(1); + end if; + end loop; + if (m_ph_val = 1) then + inclk_m_from_vco <= vco_out(1); + end if; + end if; + if (vco_out(2)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + inclk_c_from_vco(i) <= vco_out(2); + end if; + end loop; + if (m_ph_val = 2) then + inclk_m_from_vco <= vco_out(2); + end if; + end if; + if (vco_out(3)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + inclk_c_from_vco(i) <= vco_out(3); + end if; + end loop; + if (m_ph_val = 3) then + inclk_m_from_vco <= vco_out(3); + end if; + end if; + if (vco_out(4)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + inclk_c_from_vco(i) <= vco_out(4); + end if; + end loop; + if (m_ph_val = 4) then + inclk_m_from_vco <= vco_out(4); + end if; + end if; + if (vco_out(5)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + inclk_c_from_vco(i) <= vco_out(5); + end if; + end loop; + if (m_ph_val = 5) then + inclk_m_from_vco <= vco_out(5); + end if; + end if; + if (vco_out(6)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + inclk_c_from_vco(i) <= vco_out(6); + end if; + end loop; + if (m_ph_val = 6) then + inclk_m_from_vco <= vco_out(6); + end if; + end if; + if (vco_out(7)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + inclk_c_from_vco(i) <= vco_out(7); + end if; + end loop; + if (m_ph_val = 7) then + inclk_m_from_vco <= vco_out(7); + end if; + end if; + + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_scandata_scanclk, + TimingData => TimingData_scandata_scanclk, + TestSignal => scandata_ipd, + TestSignalName => "scandata", + RefSignal => scanclk_ipd, + RefSignalName => "scanclk", + SetupHigh => tsetup_scandata_scanclk_noedge_negedge, + SetupLow => tsetup_scandata_scanclk_noedge_negedge, + HoldHigh => thold_scandata_scanclk_noedge_negedge, + HoldLow => thold_scandata_scanclk_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + HeaderMsg => InstancePath & "/cycloneiv_pll", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + + + VitalSetupHoldCheck ( + Violation => Tviol_scanclkena_scanclk, + TimingData => TimingData_scanclkena_scanclk, + TestSignal => scanclkena_ipd, + TestSignalName => "scanclkena", + RefSignal => scanclk_ipd, + RefSignalName => "scanclk", + SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge, + SetupLow => tsetup_scanclkena_scanclk_noedge_negedge, + HoldHigh => thold_scanclkena_scanclk_noedge_negedge, + HoldLow => thold_scanclkena_scanclk_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + HeaderMsg => InstancePath & "/cycloneiv_pll", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then + scanclkena_reg <= scanclkena_ipd; + if (scanclkena_reg = '1') then + scandata_in <= scandata_ipd; + scandata_out <= scandataout_tmp; + end if; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then + if (got_first_scanclk) then + scanclk_period <= now - scanclk_last_rising_edge; + else + got_first_scanclk := true; + end if; + if (scanclkena_reg = '1') then + for j in scan_chain_length - 1 downto 1 loop + scan_data(j) <= scan_data(j-1); + end loop; + scan_data(0) <= scandata_in; + end if; + scanclk_last_rising_edge := now; + end if; + end process; + +-- PLL Phase Reconfiguration + +PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd) + VARIABLE i : INTEGER := 0; + VARIABLE c_ph : INTEGER := 0; + VARIABLE m_ph : INTEGER := 0; + VARIABLE select_counter : INTEGER := 0; +BEGIN + IF (NOW = 0 ps) THEN + m_ph_val_tmp <= m_ph_initial; + END IF; + + -- Latch phase enable (same as phasestep) on neg edge of scan clock + IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN + phasestep_reg <= phasestep_ipd; + END IF; + + IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN + IF (update_phase = '0') THEN + phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart + -- if not, next phasestep cycle is skipped + END IF; + END IF; + -- revert counter phase tap values to POF programmed values + -- if PLL is reset + + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val_tmp <= c_ph_val_orig; + m_ph_val_tmp <= m_ph_initial; + END IF; + + IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN + IF (phasestep_reg = '1') THEN + IF (phasestep_high_count = 1) THEN + phasecounterselect_reg <= phasecounterselect_ipd; + phaseupdown_reg <= phaseupdown_ipd; + -- start reconfiguration + IF (phasecounterselect_ipd < "111") THEN -- no counters selected + IF (phasecounterselect_ipd = "000") THEN + i := 0; + WHILE (i < num_output_cntrs) LOOP + c_ph := c_ph_val(i); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(i) <= c_ph; + i := i + 1; + END LOOP; + ELSIF (phasecounterselect_ipd = "001") THEN + m_ph := m_ph_val; + IF (phaseupdown_ipd = '1') THEN + m_ph := (m_ph + 1) mod num_phase_taps; + ELSIF (m_ph = 0) THEN + m_ph := num_phase_taps - 1; + ELSE + m_ph := (m_ph - 1) mod num_phase_taps; + END IF; + m_ph_val_tmp <= m_ph; + ELSE + select_counter := alt_conv_integer(phasecounterselect_ipd) - 2; + c_ph := c_ph_val(select_counter); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(select_counter) <= c_ph; + END IF; + update_phase <= '1','0' AFTER (0.5 * scanclk_period); + END IF; + END IF; + phasestep_high_count <= phasestep_high_count + 1; + + END IF; + END IF; +END PROCESS; + + scandataout_tmp <= scan_data(SCAN_CHAIN - 2); + + process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk) + variable sched_time : time := 0 ps; + + TYPE time_array is ARRAY (0 to 7) of time; + variable init : boolean := true; + variable refclk_period : time; + variable m_times_vco_period : time; + variable new_m_times_vco_period : time; + + variable phase_shift : time_array := (OTHERS => 0 ps); + variable last_phase_shift : time_array := (OTHERS => 0 ps); + + variable l_index : integer := 1; + variable cycle_to_adjust : integer := 0; + + variable stop_vco : boolean := false; + + variable locked_tmp : std_logic := '0'; + variable pll_is_locked : boolean := false; + variable cycles_pfd_low : integer := 0; + variable cycles_pfd_high : integer := 0; + variable cycles_to_lock : integer := 0; + variable cycles_to_unlock : integer := 0; + + variable got_first_refclk : boolean := false; + variable got_second_refclk : boolean := false; + variable got_first_fbclk : boolean := false; + + variable refclk_time : time := 0 ps; + variable fbclk_time : time := 0 ps; + variable first_fbclk_time : time := 0 ps; + + variable fbclk_period : time := 0 ps; + + variable first_schedule : boolean := true; + + variable vco_val : std_logic := '0'; + variable vco_period_was_phase_adjusted : boolean := false; + variable phase_adjust_was_scheduled : boolean := false; + + variable loop_xplier : integer; + variable loop_initial : integer := 0; + variable loop_ph : integer := 0; + variable loop_time_delay : integer := 0; + + variable initial_delay : time := 0 ps; + variable vco_per : time; + variable tmp_rem : integer; + variable my_rem : integer; + variable fbk_phase : integer := 0; + + variable pull_back_M : integer := 0; + variable total_pull_back : integer := 0; + variable fbk_delay : integer := 0; + + variable offset : time := 0 ps; + + variable tmp_vco_per : integer := 0; + variable high_time : time; + variable low_time : time; + variable time_resolution : time; + + variable got_refclk_posedge : boolean := false; + variable got_fbclk_posedge : boolean := false; + variable inclk_out_of_range : boolean := false; + variable no_warn : boolean := false; + + variable ext_fbk_cntr_modulus : integer := 1; + variable init_clks : boolean := true; + variable pll_is_in_reset : boolean := false; + variable buf : line; + begin + if (init) then + + if (lpm_hint = "time_resolution=100fs") then + time_resolution := 100 fs; + elsif (lpm_hint = "time_resolution=10fs") then + time_resolution := 10 fs; + elsif (lpm_hint = "time_resolution=fs") then + time_resolution := 1 fs; + else + time_resolution := 1 ps; + end if; + + -- jump-start the VCO + -- add 1 ps delay to ensure all signals are updated to initial + -- values + schedule_vco <= transport not schedule_vco after 1 ps; + + init := false; + end if; + + if (schedule_vco'event) then + if (init_clks) then + refclk_period := inclk0_input_frequency * n_val * 1 ps; + + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + init_clks := false; + end if; + sched_time := 0 ps; + for i in 0 to 7 loop + last_phase_shift(i) := phase_shift(i); + end loop; + cycle_to_adjust := 0; + l_index := 1; + m_times_vco_period := new_m_times_vco_period; + end if; + + -- areset was asserted + if (areset_ipd'event and areset_ipd = '1') then + assert false report family_name & " PLL was reset" severity note; + -- reset lock parameters + locked_tmp := '0'; + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + end if; + + + if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then + + if (areset_ipd = '1') then + pll_is_in_reset := true; + got_first_refclk := false; + got_second_refclk := false; + end if; + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after last_phase_shift(i); + phase_shift(i) := 0 ps; + last_phase_shift(i) := 0 ps; + end loop; + + -- reset lock parameters + locked_tmp := '0'; + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + + got_first_refclk := false; + got_second_refclk := false; + refclk_time := 0 ps; + got_first_fbclk := false; + fbclk_time := 0 ps; + first_fbclk_time := 0 ps; + fbclk_period := 0 ps; + + first_schedule := true; + vco_val := '0'; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + + elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then + + -- note areset deassert time + -- note it as refclk_time to prevent false triggering + -- of stop_vco after areset + if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then + refclk_time := now; + pll_is_in_reset := false; + locked_tmp := '0'; + end if; + + -- calculate loop_xplier : this will be different from m_val + -- in external_feedback_mode + loop_xplier := m_val; + loop_initial := m_initial_val - 1; + loop_ph := m_ph_val; + + + -- convert initial value to delay + initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; + + -- convert loop ph_tap to delay + my_rem := (m_times_vco_period/time_resolution) rem loop_xplier; + tmp_vco_per := (m_times_vco_period/time_resolution) / loop_xplier; + if (my_rem /= 0) then + tmp_vco_per := tmp_vco_per + 1; + end if; + fbk_phase := (loop_ph * tmp_vco_per)/8; + + pull_back_M := initial_delay/time_resolution + fbk_phase; + + total_pull_back := pull_back_M; + + if (simulation_type = "timing") then + total_pull_back := total_pull_back + pll_compensation_delay; + end if; + while (total_pull_back > refclk_period/time_resolution) loop + total_pull_back := total_pull_back - refclk_period/time_resolution; + end loop; + + if (total_pull_back > 0) then + offset := refclk_period - (total_pull_back * time_resolution); + end if; + + fbk_delay := total_pull_back - fbk_phase; + if (fbk_delay < 0) then + offset := offset - (fbk_phase * time_resolution); + fbk_delay := total_pull_back; + end if; + + -- assign m_delay + m_delay <= transport fbk_delay after time_resolution; + + my_rem := (m_times_vco_period/time_resolution) rem loop_xplier; + for i in 1 to loop_xplier loop + -- adjust cycles + tmp_vco_per := (m_times_vco_period/time_resolution)/loop_xplier; + if (my_rem /= 0 and l_index <= my_rem) then + tmp_rem := (loop_xplier * l_index) rem my_rem; + cycle_to_adjust := (loop_xplier * l_index) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + if (cycle_to_adjust = i) then + tmp_vco_per := tmp_vco_per + 1; + l_index := l_index + 1; + end if; + + -- calculate high and low periods + vco_per := tmp_vco_per * time_resolution; + high_time := (tmp_vco_per/2) * time_resolution; + if (tmp_vco_per rem 2 /= 0) then + high_time := high_time + time_resolution; + end if; + low_time := vco_per - high_time; + + -- schedule the rising and falling edges + for j in 1 to 2 loop + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + if (first_schedule) then + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + else + vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k)); + end if; + end loop; + end loop; + end loop; + + -- schedule once more + if (first_schedule) then + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + end loop; + first_schedule := false; + end if; + + schedule_vco <= transport not schedule_vco after sched_time; + + if (vco_period_was_phase_adjusted) then + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := true; + + vco_per := m_times_vco_period/loop_xplier; + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + end loop; + end if; + end if; +-- Bypass lock detect + +if (refclk'event and refclk = '1' and areset_ipd = '0') then + if (test_bypass_lock_detect = "on") then + if (pfdena_ipd = '1') then + cycles_pfd_low := 0; + if (pfd_locked = '0') then + if (cycles_pfd_high = lock_high) then + assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning; + pfd_locked <= '1'; + end if; + cycles_pfd_high := cycles_pfd_high + 1; + end if; + end if; + + if (pfdena_ipd = '0') then + cycles_pfd_high := 0; + if (pfd_locked = '1') then + if (cycles_pfd_low = lock_low) then + assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning; + pfd_locked <= '0'; + end if; + cycles_pfd_low := cycles_pfd_low + 1; + end if; + end if; + end if; + + + if (refclk'event and refclk = '1' and areset_ipd = '0') then + got_refclk_posedge := true; + if (not got_first_refclk) then + got_first_refclk := true; + else + got_second_refclk := true; + refclk_period := now - refclk_time; + + -- check if incoming freq. will cause VCO range to be + -- exceeded + if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and + (((refclk_period/1 ps)/loop_xplier > i_vco_max) or + ((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then + if (pll_is_locked) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + if (inclk_out_of_range) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + end if; + elsif (not no_warn) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning; + no_warn := true; + end if; + inclk_out_of_range := true; + else + vco_over <= '0'; + vco_under <= '0'; + inclk_out_of_range := false; + no_warn := false; + end if; + end if; + end if; + + if (stop_vco) then + stop_vco := false; + schedule_vco <= not schedule_vco; + end if; + + refclk_time := now; + else + got_refclk_posedge := false; + end if; + +-- Update M counter value on feedback clock edge + + if (fbclk'event and fbclk = '1') then + got_fbclk_posedge := true; + if (not got_first_fbclk) then + got_first_fbclk := true; + else + fbclk_period := now - fbclk_time; + end if; + + -- need refclk_period here, so initialized to proper value above + if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or + ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or + ( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then + stop_vco := true; + -- reset + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + if (pll_is_locked) then + pll_is_locked := false; + locked_tmp := '0'; + assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note; + if ((i_vco_max = 0) and (i_vco_min = 0)) then + assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note; + end if; + end if; + cycles_to_lock := 0; + cycles_to_unlock := 0; + first_schedule := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + fbclk_time := now; + else + got_fbclk_posedge := false; + end if; + + if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then + + -- now we know actual incoming period + if ( abs(fbclk_time - refclk_time) <= 5 ps or + (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + -- considered in phase + if (cycles_to_lock = real_lock_high) then + if (not pll_is_locked) then + assert false report family_name & " PLL locked to incoming clock" severity note; + end if; + pll_is_locked := true; + locked_tmp := '1'; + cycles_to_unlock := 0; + end if; + -- increment lock counter only if second part of above + -- time check is NOT true + if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then + cycles_to_lock := cycles_to_lock + 1; + end if; + + -- adjust m_times_vco_period + new_m_times_vco_period := refclk_period; + else + -- if locked, begin unlock + if (pll_is_locked) then + cycles_to_unlock := cycles_to_unlock + 1; + if (cycles_to_unlock = lock_low) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + end if; + end if; + if ( abs(refclk_period - fbclk_period) <= 2 ps ) then + -- frequency is still good + if (now = fbclk_time and (not phase_adjust_was_scheduled)) then + if ( abs(fbclk_time - refclk_time) > refclk_period/2) then + new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted := true; + else + new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted := true; + end if; + + end if; + else + phase_adjust_was_scheduled := false; + new_m_times_vco_period := refclk_period; + end if; + end if; + end if; + + if (pfdena_ipd = '0') then + if (pll_is_locked) then + locked_tmp := 'X'; + end if; + pll_is_locked := false; + cycles_to_lock := 0; + end if; + + -- give message only at time of deassertion + if (pfdena_ipd'event and pfdena_ipd = '0') then + assert false report "PFDENA deasserted." severity note; + elsif (pfdena_ipd'event and pfdena_ipd = '1') then + got_first_refclk := false; + got_second_refclk := false; + refclk_time := now; + end if; + + if (reconfig_err) then + lock <= '0'; + else + lock <= locked_tmp; + end if; + + -- signal to calculate quiet_time + sig_refclk_period <= refclk_period; + + if (stop_vco = true) then + sig_stop_vco <= '1'; + else + sig_stop_vco <= '0'; + end if; + + pll_locked <= pll_is_locked; + end process; + + clk0_tmp <= c_clk(i_clk0_counter); + clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE + clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else + 'X'; + + clk1_tmp <= c_clk(i_clk1_counter); + clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE + clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk2_tmp <= c_clk(i_clk2_counter); + clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE + clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk3_tmp <= c_clk(i_clk3_counter); + clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE + clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk4_tmp <= c_clk(i_clk4_counter); + clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE + clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + scandataout <= scandata_out; + scandone <= NOT scandone_tmp; + phasedone <= NOT update_phase; + vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over; + vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under; + fbout <= fbclk; + fref <= refclk; + icdrclk <= icdr_clk; +end vital_pll; +-- END ARCHITECTURE VITAL_PLL diff --git a/Common/sim/altera/cycloneiv_components.vhd b/Common/sim/altera/cycloneiv_components.vhd new file mode 100644 index 0000000..8965982 --- /dev/null +++ b/Common/sim/altera/cycloneiv_components.vhd @@ -0,0 +1,858 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneiv_atom_pack.all; + +package cycloneiv_components is + + +-- +-- cycloneiv_lcell_comb +-- + +COMPONENT cycloneiv_lcell_comb + generic ( + lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1'); + sum_lutc_input : string := "datac"; + dont_touch : string := "off"; + lpm_type : string := "cycloneiv_lcell_comb"; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; + tpd_datab_combout : VitalDelayType01 := DefPropDelay01; + tpd_datac_combout : VitalDelayType01 := DefPropDelay01; + tpd_datad_combout : VitalDelayType01 := DefPropDelay01; + tpd_cin_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; + tpd_datab_cout : VitalDelayType01 := DefPropDelay01; + tpd_datac_cout : VitalDelayType01 := DefPropDelay01; + tpd_datad_cout : VitalDelayType01 := DefPropDelay01; + tpd_cin_cout : VitalDelayType01 := DefPropDelay01; + tipd_dataa : VitalDelayType01 := DefPropDelay01; + tipd_datab : VitalDelayType01 := DefPropDelay01; + tipd_datac : VitalDelayType01 := DefPropDelay01; + tipd_datad : VitalDelayType01 := DefPropDelay01; + tipd_cin : VitalDelayType01 := DefPropDelay01 + ); + port ( + dataa : in std_logic := '1'; + datab : in std_logic := '1'; + datac : in std_logic := '1'; + datad : in std_logic := '1'; + cin : in std_logic := '0'; + combout : out std_logic; + cout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_routing_wire +-- + +COMPONENT cycloneiv_routing_wire + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_ff +-- + +COMPONENT cycloneiv_ff + generic ( + power_up : string := "low"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneiv_ff"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + clrn : in std_logic := '1'; + aload : in std_logic := '0'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + ena : in std_logic := '1'; + asdata : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_ram_block +-- + +COMPONENT cycloneiv_ram_block + GENERIC ( + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock: STRING := "clock1"; + port_b_read_enable_clock: STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + safe_write : STRING := "err_on_2clk"; + init_file_restructured : STRING := "unused"; + lpm_type : string := "cycloneiv_ram_block"; + lpm_hint : string := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : BIT_VECTOR := X"0"; + mem_init1 : BIT_VECTOR := X"0"; + mem_init2 : BIT_VECTOR := X"0"; + mem_init3 : BIT_VECTOR := X"0"; + mem_init4 : BIT_VECTOR := X"0"; + connectivity_checking : string := "off" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +-- +-- cycloneiv_mac_mult +-- + +COMPONENT cycloneiv_mac_mult + GENERIC ( + dataa_width : integer := 18; + datab_width : integer := 18; + dataa_clock : string := "none"; + datab_clock : string := "none"; + signa_clock : string := "none"; + signb_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + lpm_hint : string := "true"; + lpm_type : string := "cycloneiv_mac_mult" + ); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '0'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneiv_mac_out +-- + +COMPONENT cycloneiv_mac_out + GENERIC ( + dataa_width : integer := 1; + output_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(35 downto 0) + := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + lpm_hint : string := "true"; + lpm_type : string := "cycloneiv_mac_out"); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '1'; + dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneiv_io_ibuf +-- + +COMPONENT cycloneiv_io_ibuf + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_ibar : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_ibar_o : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + differential_mode : string := "false"; + bus_hold : string := "false"; + simulate_z_as : string := "Z"; + lpm_type : string := "cycloneiv_io_ibuf" + ); + PORT ( + i : IN std_logic := '0'; + ibar : IN std_logic := '0'; + o : OUT std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_io_obuf +-- + +COMPONENT cycloneiv_io_obuf + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_oe_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tpd_oe_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + open_drain_output : string := "false"; + bus_hold : string := "false"; + lpm_type : string := "cycloneiv_io_obuf" + ); + PORT ( + i : IN std_logic := '0'; + oe : IN std_logic := '1'; + seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + devoe : IN std_logic := '1'; + o : OUT std_logic; + obar : OUT std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_ddio_oe +-- + +COMPONENT cycloneiv_ddio_oe + generic( + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + lpm_type : string := "cycloneiv_ddio_oe" + ); + PORT ( + oe : IN std_logic := '1'; + clk : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneiv_ddio_out +-- + +COMPONENT cycloneiv_ddio_out + generic( + tipd_datainlo : VitalDelayType01 := DefPropDelay01; + tipd_datainhi : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkhi : VitalDelayType01 := DefPropDelay01; + tipd_clklo : VitalDelayType01 := DefPropDelay01; + tipd_muxsel : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + use_new_clocking_model : string := "false"; + lpm_type : string := "cycloneiv_ddio_out" + ); + PORT ( + datainlo : IN std_logic := '0'; + datainhi : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkhi : IN std_logic := '0'; + clklo : IN std_logic := '0'; + muxsel : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic ; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneiv_io_pad +-- + +COMPONENT cycloneiv_io_pad + GENERIC ( + lpm_type : string := "cycloneiv_io_pad"); + PORT ( + padin : IN std_logic := '0'; -- Input Pad + padout : OUT std_logic); -- Output Pad +END COMPONENT; + +-- +-- cycloneiv_clkctrl +-- + +COMPONENT cycloneiv_clkctrl + generic ( + clock_type : STRING := "Auto"; + lpm_type : STRING := "cycloneiv_clkctrl"; + ena_register_mode : STRING := "Falling Edge"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01 + ); + port ( + inclk : in std_logic_vector(3 downto 0) := "0000"; + clkselect : in std_logic_vector(1 downto 0) := "00"; + ena : in std_logic := '1'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + outclk : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_pseudo_diff_out +-- + +COMPONENT cycloneiv_pseudo_diff_out + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + lpm_type : string := "cycloneiv_pseudo_diff_out" + ); + PORT ( + i : IN std_logic := '0'; + o : OUT std_logic; + obar : OUT std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_rublock +-- + +COMPONENT cycloneiv_rublock + generic + ( + sim_init_config : string := "factory"; + sim_init_watchdog_value : integer := 0; + sim_init_status : integer := 0; + sim_init_config_is_application : string := "false"; + sim_init_watchdog_enabled : string := "false"; + operation_mode : string := "active_serial_remote"; + lpm_type : string := "cycloneiv_rublock" + ); + port + ( + clk : in std_logic; + shiftnld : in std_logic; + captnupdt : in std_logic; + regin : in std_logic; + rsttimer : in std_logic; + rconfig : in std_logic; + regout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_termination +-- + +COMPONENT cycloneiv_termination + GENERIC ( + pullup_control_to_core: string := "false"; + power_down : string := "true"; + test_mode : string := "false"; + left_shift_termination_code : string := "false"; + pullup_adder : integer := 0; + pulldown_adder : integer := 0; + clock_divide_by : integer := 32; -- 1, 4, 32 + runtime_control : string := "false"; + shift_vref_rup : string := "true"; + shift_vref_rdn : string := "true"; + shifted_vref_control : string := "true"; + lpm_type : string := "cycloneiv_termination"); + PORT ( + rup : IN std_logic := '0'; + rdn : IN std_logic := '0'; + terminationclock : IN std_logic := '0'; + terminationclear : IN std_logic := '0'; + devpor : IN std_logic := '1'; + devclrn : IN std_logic := '1'; + comparatorprobe : OUT std_logic; + terminationcontrolprobe : OUT std_logic; + calibrationdone : OUT std_logic; + terminationcontrol : OUT std_logic_vector(15 DOWNTO 0)); +END COMPONENT; + +-- +-- cycloneiv_jtag +-- + +COMPONENT cycloneiv_jtag + generic ( + lpm_type : string := "cycloneiv_jtag" + ); + port ( + tms : in std_logic := '0'; + tck : in std_logic := '0'; + tdi : in std_logic := '0'; + tdoutap : in std_logic := '0'; + tdouser : in std_logic := '0'; + tdo: out std_logic; + tmsutap: out std_logic; + tckutap: out std_logic; + tdiutap: out std_logic; + shiftuser: out std_logic; + clkdruser: out std_logic; + updateuser: out std_logic; + runidleuser: out std_logic; + usr1user: out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_crcblock +-- + +COMPONENT cycloneiv_crcblock + generic ( + oscillator_divider : integer := 1; + lpm_type : string := "cycloneiv_crcblock" + ); + port ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + ldsrc : in std_logic := '0'; + crcerror : out std_logic; + regout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_oscillator +-- + +COMPONENT cycloneiv_oscillator + generic + ( + lpm_type: string := "cycloneiv_oscillator"; + TimingChecksOn: Boolean := True; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01; + tipd_oscena : VitalDelayType01 := DefPropDelay01 + ); + port + ( + oscena : in std_logic; + observableoutputport: out std_logic; + clkout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_controller +-- + +COMPONENT cycloneiv_controller + generic + ( + lpm_type: string := "cycloneiv_controller" + ); + port + ( + usermode : out std_logic; + nceout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_asmiblock +-- + +COMPONENT cycloneiv_asmiblock + generic ( + lpm_type : string := "cycloneiv_asmiblock"; + enable_sim : string := "false" + ); + port ( + dclkin : in std_logic; + scein : in std_logic; + oe : in std_logic; + sdoin : in std_logic; + data0out: out std_logic + ); +END COMPONENT; + +-- +-- cycloneiv_pll +-- + +COMPONENT cycloneiv_pll + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM + compensate_clock : string := "clock0"; + inclk0_input_frequency : integer := 0; + inclk1_input_frequency : integer := 0; + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + use_dc_coupling : string := "false"; + lock_c : integer := 4; + sim_gate_lock_device_behavior : string := "off"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_window : time := 5 ps; + test_bypass_lock_detect : string := "off"; + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 0; + clk0_divide_by : integer := 0; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 0; + clk1_divide_by : integer := 0; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 0; + clk2_divide_by : integer := 0; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 0; + clk3_divide_by : integer := 0; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 0; + clk4_divide_by : integer := 0; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + feedback_source : integer := 0; + feedback_external_loop_divider : string := "false"; + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + m_ph : integer := 0; + clk0_counter : string := "unused"; + clk1_counter : string := "unused"; + clk2_counter : string := "unused"; + clk3_counter : string := "unused"; + clk4_counter : string := "unused"; + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + vco_post_scale : integer := 1; + vco_frequency_control : string := "auto"; + vco_phase_shift_step : integer := 0; + dpa_multiply_by : integer := 0; + dpa_divide_by : integer := 0; + dpa_divider : integer := 1; + charge_pump_current : integer := 10; + loop_filter_r : string := " 1.0"; + loop_filter_c : integer := 0; + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + lpm_type : string := "cycloneiv_pll"; + lpm_hint : string := "unused"; + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + init_block_reset_a_count : integer := 1; + init_block_reset_b_count : integer := 1; + charge_pump_current_bits : integer := 0; + lock_window_ui_bits : integer := 0; + loop_filter_c_bits : integer := 0; + loop_filter_r_bits : integer := 0; + test_counter_c0_delay_chain_bits : integer := 0; + test_counter_c1_delay_chain_bits : integer := 0; + test_counter_c2_delay_chain_bits : integer := 0; + test_counter_c3_delay_chain_bits : integer := 0; + test_counter_c4_delay_chain_bits : integer := 0; + test_counter_m_delay_chain_bits : integer := 0; + test_counter_n_delay_chain_bits : integer := 0; + test_feedback_comp_delay_chain_bits : integer := 0; + test_input_comp_delay_chain_bits : integer := 0; + test_volt_reg_output_mode_bits : integer := 0; + test_volt_reg_output_voltage_bits : integer := 0; + test_volt_reg_test_mode : string := "false"; + vco_range_detector_high_bits : integer := -1; + vco_range_detector_low_bits : integer := -1; + scan_chain_mif_file : string := ""; + auto_settings : string := "true"; + family_name : string := "Cyclone IV GX"; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + TimingChecksOn : Boolean := true; + InstancePath : STRING := "*"; + tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_pfdena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_fbin : VitalDelayType01 := DefPropDelay01; + tipd_scanclk : VitalDelayType01 := DefPropDelay01; + tipd_scanclkena : VitalDelayType01 := DefPropDelay01; + tipd_scandata : VitalDelayType01 := DefPropDelay01; + tipd_configupdate : VitalDelayType01 := DefPropDelay01; + tipd_clkswitch : VitalDelayType01 := DefPropDelay01; + tipd_phaseupdown : VitalDelayType01 := DefPropDelay01; + tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phasestep : VitalDelayType01 := DefPropDelay01; + tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + use_vco_bypass : string := "false" + ); + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + fbout : out std_logic; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + clk : out std_logic_vector(4 downto 0); + phasecounterselect : in std_logic_vector(2 downto 0) := "000"; + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic; + fref : out std_logic; + icdrclk : out std_logic + ); +END COMPONENT; + +end cycloneiv_components; diff --git a/Common/sim/altera/cycloneiv_hssi_atoms.vhd b/Common/sim/altera/cycloneiv_hssi_atoms.vhd new file mode 100644 index 0000000..539d1d3 --- /dev/null +++ b/Common/sim/altera/cycloneiv_hssi_atoms.vhd @@ -0,0 +1,103838 @@ +-- Copyright (C) 2009 - Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +------------------------------------------------------------------------------- +-- -- +-- Containing VHDL Model for the Atoms: -- +-- cycloneiv_hssi_rx_pma -- +-- cycloneiv_hssi_tx_pma -- +-- cycloneiv_hssi_tx_pcs -- +-- cycloneiv_hssi_rx_pcs -- +-- cycloneiv_hssi_cmu -- +-- cycloneiv_hssi_calibration_block -- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_reg +-- +-- Description : Simulation model for a simple DFF. +-- This is used for registering the enable inputs. +-- No timing, powers upto 0. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, std; +USE ieee.std_logic_1164.all; +--USE ieee.std_logic_unsigned.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +use work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_tx_pma_sub_reg is +PORT ( q : OUT std_logic; + clk : IN std_logic; + ena : IN std_logic; + d : IN std_logic; + clrn : IN std_logic; + prn : IN std_logic +); +ATTRIBUTE VITAL_LEVEL0 of cycloneiv_hssi_tx_pma_sub_reg : ENTITY is TRUE; +END cycloneiv_hssi_tx_pma_sub_reg; + +ARCHITECTURE vital_cycloneiv_hssi_tx_pma_sub_reg of cycloneiv_hssi_tx_pma_sub_reg is +ATTRIBUTE VITAL_LEVEL0 of vital_cycloneiv_hssi_tx_pma_sub_reg : architecture is TRUE; +BEGIN + PROCESS (clk, clrn, prn) + BEGIN + if (prn = '0') then + q <= '1'; + elsif (clrn = '0') then + q <= '0'; + elsif (clk'event and clk = '1') then + if (ena = '1') then + q <= d; + end if; + end if; + END PROCESS; + +END vital_cycloneiv_hssi_tx_pma_sub_reg; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_out_block +-- +-- Description : Negative edge triggered register on the Tx output. +-- Also, optionally generates an identical/inverted output clock +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneiv_hssi_components.all; +USE std.textio.all; + +ENTITY cycloneiv_hssi_tx_pma_sub_out_block is +GENERIC ( bypass_serializer : String := "false"; + invert_clock : String := "false"; + use_falling_clock_edge : String := "false" +); + +PORT ( clk : IN std_logic; + datain : IN std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1'; + dataout : OUT std_logic +); + +END cycloneiv_hssi_tx_pma_sub_out_block; + +ARCHITECTURE vital_tx_out_block of cycloneiv_hssi_tx_pma_sub_out_block is +BEGIN + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- +VITAL: PROCESS (clk, datain, devpor, devclrn) +BEGIN + if (now = 0 ns) then + dataout <= '0'; + else + if (bypass_serializer = "false") then + if (use_falling_clock_edge = "false") then + dataout <= datain; + end if; + + if (clk'event and clk = '0') then + if (use_falling_clock_edge = "true") then + dataout <= datain; + end if; + end if; + else + if (invert_clock = "false") then + dataout <= clk; + else + dataout <= NOT (clk); + end if; + + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- +END PROCESS; +END vital_tx_out_block; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_parallel_register +-- +-- Description : Register for the 10 data input channels of the cycloneiv +-- LVDS Tx +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneiv_hssi_components.all; +USE std.textio.all; + +ENTITY cycloneiv_hssi_tx_pma_sub_parallel_register is +GENERIC ( channel_width : integer := 4 +); + +PORT ( clk : IN std_logic; + enable : IN std_logic; + datain : IN std_logic_vector(channel_width - 1 downto 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1'; + dataout : OUT std_logic_vector(channel_width - 1 downto 0) +); + +END cycloneiv_hssi_tx_pma_sub_parallel_register; + +ARCHITECTURE vital_tx_reg of cycloneiv_hssi_tx_pma_sub_parallel_register is +BEGIN + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + +VITAL: PROCESS (clk, enable, datain, devpor, devclrn) +VARIABLE Tviol_datain_clk : std_ulogic := '0'; +VARIABLE i : integer := 0; +VARIABLE dataout_tmp : std_logic_vector(channel_width - 1 downto 0); +BEGIN + + if (now = 0 ns) then + dataout_tmp := (OTHERS => '0'); + end if; + + ------------------------ + -- Timing Check Section + ------------------------ + + if ((devpor = '0') or (devclrn = '0')) then + dataout_tmp := (OTHERS => '0'); + else + if (clk'event and clk = '1') then + if (enable = '1') then + dataout_tmp := datain; + end if; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + dataout <= dataout_tmp; + +END PROCESS; + +END vital_tx_reg; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_ser +-- +-- Description : Timing simulation model for the cycloneiv LVDS Tx WYSIWYG. +-- It instantiates the following sub-modules : +-- 1) primitive DFFE +-- 2) cycloneiv_hssi_tx_pma_sub_parallel_register and +-- 3) cycloneiv_hssi_tx_pma_sub_out_block +-- +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; +USE work.cycloneiv_hssi_tx_pma_sub_reg; +USE work.cycloneiv_hssi_tx_pma_sub_out_block; +USE work.cycloneiv_hssi_tx_pma_sub_parallel_register; + +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; + +ENTITY cycloneiv_hssi_tx_pma_sub_ser is +GENERIC ( channel_width : integer := 8; + bypass_serializer : String := "false"; + invert_clock : String := "false"; + use_falling_clock_edge : String := "false"; + use_serial_data_input : String := "false"; + use_post_dpa_serial_data_input : String := "false"; + is_used_as_outclk : String := "false"; + tx_output_path_delay_engineering_bits : Integer := -1; + enable_dpaclk_to_lvdsout : string := "off"; + preemphasis_setting : integer := 0; + vod_setting : integer := 0; + differential_drive : integer := 0; + lpm_type : string := "cycloneiv_hssi_tx_pma_sub_ser" +); + +PORT ( clk0 : IN std_logic; + cgb_pdb : IN std_logic; + enable0 : IN std_logic := '0'; + datain : IN std_logic_vector(9 downto 0); + serialdatain : IN std_logic := '0'; + postdpaserialdatain : IN std_logic := '0'; + dpaclkin : IN std_logic := '0'; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1'; + dataout : OUT std_logic; + serialfdbkout : OUT std_logic +); + +END cycloneiv_hssi_tx_pma_sub_ser; + +ARCHITECTURE vital_transmitter_atom of cycloneiv_hssi_tx_pma_sub_ser is + +SIGNAL txload0 : std_logic; + +SIGNAL dataout_buf : std_logic; +SIGNAL dataout_wire : std_logic; +SIGNAL dataout_tmp : std_logic; +SIGNAL deven : std_logic; +SIGNAL dodd : std_logic; + +SIGNAL shift_out_even : std_logic; +SIGNAL shift_out_odd : std_logic; + +SIGNAL shift_data_even : std_logic_vector(channel_width/2 - 1 downto 0); +SIGNAL shift_data_odd : std_logic_vector(channel_width/2 - 1 downto 0); + +SIGNAL input_data_even : std_logic_vector(channel_width/2 - 1 downto 0); +SIGNAL input_data_odd : std_logic_vector(channel_width/2 - 1 downto 0); + +SIGNAL datain_odd : std_logic_vector(channel_width/2 - 1 downto 0); +SIGNAL datain_even : std_logic_vector(channel_width/2 - 1 downto 0); + +SIGNAL datain_odd_x10 : std_logic_vector(4 downto 0); +SIGNAL datain_odd_x8 : std_logic_vector(3 downto 0); + +SIGNAL datain_even_x10 : std_logic_vector(4 downto 0); +SIGNAL datain_even_x8 : std_logic_vector(3 downto 0); + +SIGNAL vcc : std_logic := '1'; +SIGNAL tmp_dataout : std_logic; + +COMPONENT cycloneiv_hssi_tx_pma_sub_parallel_register +GENERIC ( channel_width : integer := 8 +); + +PORT ( clk : IN std_logic; + enable : IN std_logic; + datain : IN std_logic_vector(channel_width - 1 downto 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1'; + dataout : OUT std_logic_vector(channel_width - 1 downto 0) +); + +END COMPONENT; + +COMPONENT cycloneiv_hssi_tx_pma_sub_out_block +GENERIC ( bypass_serializer : String := "false"; + invert_clock : String := "false"; + use_falling_clock_edge : String := "false" +); + +PORT ( clk : IN std_logic; + datain : IN std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1'; + dataout : OUT std_logic +); +END COMPONENT; + +COMPONENT cycloneiv_hssi_tx_pma_sub_reg +PORT ( q : OUT STD_LOGIC := '0'; + d : IN STD_LOGIC := '1'; + clrn : IN STD_LOGIC := '1'; + prn : IN STD_LOGIC := '1'; + clk : IN STD_LOGIC := '0'; + ena : IN STD_LOGIC := '1' +); +END COMPONENT; + +BEGIN + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + + txload0_reg: cycloneiv_hssi_tx_pma_sub_reg + PORT MAP ( d => enable0, + clrn => vcc, + prn => vcc, + ena => vcc, + clk => clk0, + q => txload0 + ); + + input_data_odd <= (OTHERS => '0') WHEN ((devpor = '0') OR (devclrn = '0')) ELSE datain_odd; + input_data_even <= (OTHERS => '0') WHEN ((devpor = '0') OR (devclrn = '0')) ELSE datain_even; + + + output_module_even: cycloneiv_hssi_tx_pma_sub_out_block + GENERIC MAP ( bypass_serializer => bypass_serializer, + use_falling_clock_edge => use_falling_clock_edge, + invert_clock => invert_clock) + PORT MAP ( clk => clk0, + datain => shift_out_even, + dataout => deven, + devclrn => devclrn, + devpor => devpor + ); + + output_module_odd: cycloneiv_hssi_tx_pma_sub_out_block + GENERIC MAP ( bypass_serializer => bypass_serializer, + use_falling_clock_edge => use_falling_clock_edge, + invert_clock => invert_clock) + PORT MAP ( clk => clk0, + datain => shift_out_odd, + dataout => dodd, + devclrn => devclrn, + devpor => devpor + ); + + VITAL: PROCESS (clk0, devclrn, devpor) + VARIABLE i : integer := 0; + BEGIN + if (now = 0 ns) then + shift_data_even <= (OTHERS => '0'); + shift_data_odd <= (OTHERS => '0'); + end if; + + if ((devpor = '0') or (devclrn = '0')) then + shift_data_even <= (OTHERS => '0'); + shift_data_odd <= (OTHERS => '0'); + else + if (bypass_serializer = "false") then + if (clk0'event and clk0 = '1') then + if (txload0 = '1') then + shift_data_even <= input_data_even; + shift_data_odd <= input_data_odd; + else + for i in (channel_width/2 - 1) downto 1 loop + shift_data_even(i) <= shift_data_even(i - 1); -- here! + shift_data_odd(i) <= shift_data_odd(i - 1); + end loop; + end if; + end if; + end if; + end if; + + END PROCESS; + + shift_out_even <= shift_data_even(channel_width/2 - 1); + shift_out_odd <= shift_data_odd(channel_width/2 - 1); + + datain_even <= datain_even_x10 when (channel_width = 10) else datain_even_x8; + datain_odd <= datain_odd_x10 when (channel_width = 10) else datain_odd_x8; + + datain_even_x10 <= datain(0) & datain(2) & datain(4) & datain(6) & datain(8); + datain_even_x8 <= datain(0) & datain(2) & datain(4) & datain(6); + datain_odd_x10 <= datain(1) & datain(3) & datain(5) & datain(7) & datain(9); + datain_odd_x8 <= datain(1) & datain(3) & datain(5) & datain(7); + + dataout_tmp <= deven when (clk0 = '1') else dodd; + + PROCESS (serialdatain, postdpaserialdatain, dpaclkin, dataout_tmp) + BEGIN + if (serialdatain'event and use_serial_data_input = "true") then + dataout_wire <= serialdatain; + elsif (postdpaserialdatain'event and use_post_dpa_serial_data_input = "true") then + dataout_wire <= postdpaserialdatain; + elsif (dpaclkin'event and enable_dpaclk_to_lvdsout = "on") then + dataout_wire <= dpaclkin; + else + dataout_wire <= dataout_tmp; + end if; + + END PROCESS; + + dataout_buf <= '0' when (cgb_pdb = '0') else dataout_wire; + + dataout <= dataout_buf; + serialfdbkout <= dataout_buf; + +end vital_transmitter_atom; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 +-- +-- Description : Module to halve the frequency or double the period of the +-- input clock by 2. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 IS + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + clkout : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2; + +ARCHITECTURE div_by_2_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 IS + + + SIGNAL next_val : std_logic := '0'; + SIGNAL clkout_xhdl1 : std_logic := '0'; + +BEGIN + clkout <= clkout_xhdl1; + + -- state definition + + PROCESS + BEGIN + WAIT UNTIL (clk'EVENT AND clk = '1') OR (reset_n'EVENT AND reset_n = '0'); + IF (NOT reset_n = '1') THEN + clkout_xhdl1 <= '0'; + ELSE + clkout_xhdl1 <= next_val; + END IF; + END PROCESS; + next_val <= NOT clkout_xhdl1 ; + +END div_by_2_arch; +-- div_by_2 + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 IS + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + clkout : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2; + +ARCHITECTURE div_by_2_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 IS + + + SIGNAL next_val : std_logic := '0'; + SIGNAL clkout_xhdl1 : std_logic := '0'; + +BEGIN + clkout <= clkout_xhdl1; + + -- state definition + + PROCESS + BEGIN + WAIT UNTIL (clk'EVENT AND clk = '1') OR (reset_n'EVENT AND reset_n = '0'); + IF (NOT reset_n = '1') THEN + clkout_xhdl1 <= '0'; + ELSE + clkout_xhdl1 <= next_val; + END IF; + END PROCESS; + next_val <= NOT clkout_xhdl1 ; + +END div_by_2_arch; +-- div_by_2 + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen +-- +-- Description : Network of byn clock generators; where n = 2, 4, 8 +-- Instantiates tx_rx_det_div_by_2 +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +USE WORK.cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2; + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen IS + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + clkout : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen; + +ARCHITECTURE clk_gen_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen IS + + COMPONENT cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + clkout : OUT std_logic); + END COMPONENT; + + + SIGNAL clk8m : std_logic; + SIGNAL clk4m : std_logic; + SIGNAL clk2m : std_logic; + SIGNAL clkout_xhdl1 : std_logic; + +BEGIN + clkout <= clkout_xhdl1; + div_1 : cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 + PORT MAP ( + clk => clk, + reset_n => reset_n, + clkout => clk8m); + + div_2 : cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 + PORT MAP ( + clk => clk8m, + reset_n => reset_n, + clkout => clk4m); + + div_3 : cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 + PORT MAP ( + clk => clk4m, + reset_n => reset_n, + clkout => clk2m); + + div_4 : cycloneiv_hssi_tx_pma_sub_tx_rx_det_div_by_2 + PORT MAP ( + clk => clk2m, + reset_n => reset_n, + clkout => clkout_xhdl1); + + +END clk_gen_arch; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync +-- +-- Description : Delays input data by 1 clock cycle +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync IS + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + rcv_det : IN std_logic; + rcv_det_out : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync; + +ARCHITECTURE rcv_det_sync_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync IS + + + SIGNAL rcv_det_mid : std_logic; + SIGNAL rcv_det_out_xhdl1 : std_logic; + +BEGIN + rcv_det_out <= rcv_det_out_xhdl1; + + PROCESS + BEGIN + WAIT UNTIL (clk'EVENT AND clk = '1') OR (reset_n'EVENT AND reset_n = '0'); + IF (NOT reset_n = '1') THEN + rcv_det_out_xhdl1 <= '0'; + rcv_det_mid <= '0'; + ELSE + rcv_det_out_xhdl1 <= rcv_det_mid; + rcv_det_mid <= rcv_det; + END IF; + END PROCESS; + +END rcv_det_sync_arch; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm +-- +-- Description : State machine to generate SIGNALs/ indications for +-- rcv_found, next_rcv_found and detect_valid +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm IS + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + com_pass : IN std_logic; + probe_pass : IN std_logic; + det_on : OUT std_logic; + detect_valid : OUT std_logic; + rcv_found : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm; + +ARCHITECTURE rcv_det_fsm_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm IS + + + SIGNAL state : std_logic_vector(2 DOWNTO 0); + SIGNAL nextstate : std_logic_vector(2 DOWNTO 0) := "001"; + SIGNAL next_rcv_found : std_logic; + SIGNAL fake_rcv_present : std_logic; + -- state definition + CONSTANT reset : std_logic_vector(2 DOWNTO 0) := "000"; + CONSTANT wake : std_logic_vector(2 DOWNTO 0) := "001"; + CONSTANT state_1 : std_logic_vector(2 DOWNTO 0) := "011"; + CONSTANT state_2 : std_logic_vector(2 DOWNTO 0) := "101"; + CONSTANT hold : std_logic_vector(2 DOWNTO 0) := "100"; + SIGNAL rcv_found_xhdl1 : std_logic; + SIGNAL det_on_xhdl2 : std_logic; + SIGNAL detect_valid_xhdl3 : std_logic; + +BEGIN + rcv_found <= rcv_found_xhdl1; + det_on <= det_on_xhdl2; + detect_valid <= detect_valid_xhdl3; + + PROCESS + VARIABLE xhdl_initial : BOOLEAN := TRUE; + BEGIN + IF (xhdl_initial) THEN + fake_rcv_present <= '1'; + xhdl_initial := FALSE; + ELSE + WAIT; + END IF; + END PROCESS; + + -- State logic and fsm + + PROCESS + BEGIN + WAIT UNTIL (clk'EVENT AND clk = '1') OR (reset_n'EVENT AND reset_n = '0'); + IF (NOT reset_n = '1') THEN + state <= reset; + ELSE + state <= nextstate; + END IF; + END PROCESS; + + PROCESS + BEGIN + WAIT UNTIL state'EVENT OR com_pass'EVENT; + CASE state IS + WHen reset => + nextstate <= wake; + WHen wake => + IF (com_pass = '1') THEN + nextstate <= state_1; + ELSE + nextstate <= wake; + END IF; + WHen state_1 => + nextstate <= state_2; + WHen state_2 => + nextstate <= hold; + WHen hold => + nextstate <= hold; + WHen OTHERS => + nextstate <= reset; + + END CASE; + -- case(state) + + + END PROCESS; + + -- always @ (state or com_pass) + -- Output logic + + PROCESS + BEGIN + WAIT UNTIL (clk'EVENT AND clk = '1') OR (reset_n'EVENT AND reset_n = '0'); + IF (NOT reset_n = '1') THEN + rcv_found_xhdl1 <= '0'; + ELSE + rcv_found_xhdl1 <= next_rcv_found; + END IF; + END PROCESS; + + PROCESS + BEGIN + WAIT UNTIL nextstate'EVENT OR probe_pass'EVENT OR fake_rcv_present'EVENT; + IF ( (nextstate = state_2) AND (probe_pass = '0') AND (fake_rcv_present = '1') ) THEN + -- probe pass goes up slow -> there is rx + + next_rcv_found <= '1'; + ELSE + IF ((nextstate = hold) AND (fake_rcv_present = '1')) THEN + next_rcv_found <= rcv_found_xhdl1; + ELSE + -- probe pass goes up fast -> no rx + + next_rcv_found <= '0'; + END IF; + END IF; + END PROCESS; + + -- there is no rcv_det_syn + + PROCESS + BEGIN + WAIT UNTIL state'EVENT; + IF (state = reset) THEN + det_on_xhdl2 <= '0'; + ELSE + det_on_xhdl2 <= '1'; + END IF; + END PROCESS; + + PROCESS + BEGIN + WAIT UNTIL state'EVENT; + IF (state = hold) THEN + detect_valid_xhdl3 <= '1'; + ELSE + detect_valid_xhdl3 <= '0'; + END IF; + END PROCESS; + +END rcv_det_fsm_arch; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control +-- +-- Description : Module to hook up the fsm and detect sync block +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +USE WORK.cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm; +USE WORK.cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync; + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control IS + PORT ( + clk : IN std_logic; + rcv_det_en : IN std_logic; + rcv_det_pdb : IN std_logic; + com_pass : IN std_logic; + probe_pass : IN std_logic; + det_on : OUT std_logic; + detect_valid : OUT std_logic; + rcv_found : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control; + +ARCHITECTURE rcv_det_control_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control IS + + COMPONENT cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + com_pass : IN std_logic; + probe_pass : IN std_logic; + det_on : OUT std_logic; + detect_valid : OUT std_logic; + rcv_found : OUT std_logic); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + rcv_det : IN std_logic; + rcv_det_out : OUT std_logic); + END COMPONENT; + + + SIGNAL rcv_det_syn : std_logic; + SIGNAL det_on_xhdl1 : std_logic; + SIGNAL detect_valid_xhdl2 : std_logic; + SIGNAL rcv_found_xhdl3 : std_logic; + +BEGIN + det_on <= det_on_xhdl1; + detect_valid <= detect_valid_xhdl2; + rcv_found <= rcv_found_xhdl3; + Xrcv_det_sync : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_sync + PORT MAP ( + clk => clk, + reset_n => rcv_det_pdb, + rcv_det => rcv_det_en, + rcv_det_out => rcv_det_syn); + + Xrcv_det_fsm : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_fsm + PORT MAP ( + clk => clk, + reset_n => rcv_det_syn, + com_pass => com_pass, + probe_pass => probe_pass, + det_on => det_on_xhdl1, + detect_valid => detect_valid_xhdl2, + rcv_found => rcv_found_xhdl3); + + +END rcv_det_control_arch; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital +-- +-- Description : Digital part of the receiver detection +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +USE WORK.cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen; +USE WORK.cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control; + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital IS + PORT ( + oscclk : IN std_logic; + rcv_det_pdb : IN std_logic; + rcv_det_en : IN std_logic; + com_pass : IN std_logic; + probe_pass : IN std_logic; + det_on : OUT std_logic; + detect_valid : OUT std_logic; + rcv_found : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital; + +ARCHITECTURE rcv_det_digital_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital IS + + COMPONENT cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen + PORT ( + clk : IN std_logic; + reset_n : IN std_logic; + clkout : OUT std_logic); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control + PORT ( + clk : IN std_logic; + rcv_det_en : IN std_logic; + rcv_det_pdb : IN std_logic; + com_pass : IN std_logic; + probe_pass : IN std_logic; + det_on : OUT std_logic; + detect_valid : OUT std_logic; + rcv_found : OUT std_logic); + END COMPONENT; + + + SIGNAL clk : std_logic; + SIGNAL det_on_xhdl1 : std_logic; + SIGNAL rcv_found_xhdl2 : std_logic; + SIGNAL detect_valid_xhdl3 : std_logic; + +BEGIN + det_on <= det_on_xhdl1; + rcv_found <= rcv_found_xhdl2; + detect_valid <= detect_valid_xhdl3; + Xclk_Gen : cycloneiv_hssi_tx_pma_sub_tx_rx_det_clk_gen + PORT MAP ( + clk => oscclk, + reset_n => rcv_det_pdb, + clkout => clk); + + Xrcv_det_CTRL : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_control + PORT MAP ( + clk => clk, + rcv_det_en => rcv_det_en, + rcv_det_pdb => rcv_det_pdb, + com_pass => com_pass, + probe_pass => probe_pass, + det_on => det_on_xhdl1, + detect_valid => detect_valid_xhdl3, + rcv_found => rcv_found_xhdl2); + + +END rcv_det_digital_arch; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma_sub_tx_rx_det +-- +-- Description : Receiver detect +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +USE WORK.cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital; + +ENTITY cycloneiv_hssi_tx_pma_sub_tx_rx_det IS + PORT ( + rx_det_pdb : IN std_logic; + clk15m : IN std_logic; + tx_det_rx : IN std_logic; + rx_found : OUT std_logic; + rx_det_valid : OUT std_logic); +END cycloneiv_hssi_tx_pma_sub_tx_rx_det; + +ARCHITECTURE tx_rx_det_arch OF cycloneiv_hssi_tx_pma_sub_tx_rx_det IS + + CONSTANT xhdl_timescale : time := 1 ps; + + COMPONENT cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital + PORT ( + oscclk : IN std_logic; + rcv_det_pdb : IN std_logic; + rcv_det_en : IN std_logic; + com_pass : IN std_logic; + probe_pass : IN std_logic; + det_on : OUT std_logic; + detect_valid : OUT std_logic; + rcv_found : OUT std_logic); + END COMPONENT; + + + SIGNAL com_pass : std_logic; + SIGNAL probe_pass : std_logic; + SIGNAL det_on : std_logic; + CONSTANT rx_exist : std_logic := '1'; + SIGNAL rx_found_xhdl1 : std_logic; + SIGNAL rx_det_valid_xhdl2 : std_logic; + +BEGIN + rx_found <= rx_found_xhdl1; + rx_det_valid <= rx_det_valid_xhdl2; + com_pass <= det_on AFTER 100000 * xhdl_timescale; + probe_pass <= NOT rx_exist AFTER 100000 * xhdl_timescale; + Xrcv_det_digital : cycloneiv_hssi_tx_pma_sub_tx_rx_det_rcv_det_digital + PORT MAP ( + oscclk => clk15m, + rcv_det_pdb => rx_det_pdb, + rcv_det_en => tx_det_rx, + com_pass => com_pass, + probe_pass => probe_pass, + det_on => det_on, + detect_valid => rx_det_valid_xhdl2, + rcv_found => rx_found_xhdl1); + +END tx_rx_det_arch; +-- *********************************************************** +-- This WYSIWYG atom header was automatically generated by the +-- Atmgen build tool. To change it, alter data stored in the +-- corresponding WYS file(s) in the tools-atmgen subdirectory. +-- *********************************************************** + +-- *** Section 1 -- Header *** + +-- ----------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_tx_pma +-- +-- Description : DEV_FAMILY_cycloneiv cycloneiv_hssi_tx_pma VHDL simulation model +-- +-- ----------------------------------------------------------- + +-- *** End of Section 1 *** + +-- *** Section 3 -- Module declaration *** + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +ENTITY cycloneiv_hssi_tx_pma IS +GENERIC ( + -- generic control parameters -- + enable_diagnostic_loopback : STRING := "false"; + enable_reverse_serial_loopback : STRING := "false"; + enable_txclkout_loopback : STRING := "false"; + lpm_type : STRING := "cycloneiv_hssi_tx_pma"; + channel_number : INTEGER := 0; + common_mode : STRING := "0.65V"; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + logical_channel_address : INTEGER := 0; + preemp_tap_1 : INTEGER := 0; + protocol_hint : STRING := "basic"; + effective_data_rate : STRING := "unused"; + rx_detect : INTEGER := 0; + serialization_factor : INTEGER := 8; + slew_rate : STRING := "low"; + termination : STRING := "OCT 100 Ohms"; + use_external_termination : STRING := "false"; + use_rx_detect : STRING := "false"; + vod_selection : INTEGER := 0 +); +PORT ( + cgbpowerdn : IN STD_LOGIC := '0'; + datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); + detectrxpowerdown : IN STD_LOGIC := '0'; + diagnosticlpbkin : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0'); + fastrefclk0in : IN STD_LOGIC := '0'; + forceelecidle : IN STD_LOGIC := '0'; + powerdn : IN STD_LOGIC := '0'; + refclk0in : IN STD_LOGIC := '0'; + refclk0inpulse : IN STD_LOGIC := '0'; + reverselpbkin : IN STD_LOGIC := '0'; + rxdetectclk : IN STD_LOGIC := '0'; + rxdetecten : IN STD_LOGIC := '0'; + txpmareset : IN STD_LOGIC := '0'; + clockout : OUT STD_LOGIC; + dataout : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0); + rxdetectvalidout : OUT STD_LOGIC; + rxfoundout : OUT STD_LOGIC; + seriallpbkout : OUT STD_LOGIC +); +END cycloneiv_hssi_tx_pma; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_pma IS +COMPONENT cycloneiv_hssi_tx_pma_sub_ser +GENERIC ( + channel_width : INTEGER := 8; + bypass_serializer : STRING := "false"; + invert_clock : STRING := "false"; + use_falling_clock_edge : STRING := "false"; + use_serial_data_input : STRING := "false"; + use_post_dpa_serial_data_input : STRING := "false"; + is_used_as_outclk : STRING := "false"; + tx_output_path_delay_engineering_bits : INTEGER := -1; + enable_dpaclk_to_lvdsout : STRING := "off"; + preemphasis_setting : INTEGER := 0; + vod_setting : INTEGER := 0; + differential_drive : INTEGER := 0; + lpm_type : STRING := "cycloneiv_hssi_tx_pma_sub_ser" +); +PORT ( + datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + clk0 : IN STD_LOGIC; + cgb_pdb : IN STD_LOGIC; -- not in wys yet + enable0 : IN STD_LOGIC; + serialdatain : IN STD_LOGIC; + postdpaserialdatain : IN STD_LOGIC; + devclrn : IN STD_LOGIC; + devpor : IN STD_LOGIC; + dpaclkin : IN STD_LOGIC; + dataout : OUT STD_LOGIC; + serialfdbkout : OUT STD_LOGIC +); +END COMPONENT; + +COMPONENT cycloneiv_hssi_tx_pma_sub_tx_rx_det +PORT ( + rx_det_pdb : IN std_logic; + clk15m : IN std_logic; + tx_det_rx : IN std_logic; + rx_found : OUT std_logic; + rx_det_valid : OUT std_logic +); +END COMPONENT; + +-- Declare intermediate signals for referenced outputs +-- Buffers +SIGNAL dataout_buf : STD_LOGIC; + +-- Resets +SIGNAL txpma_rstb : STD_LOGIC; +SIGNAL cgb_pdb : STD_LOGIC; +SIGNAL tx_pdb : STD_LOGIC; + +-- Serializer +SIGNAL ser_dataout : STD_LOGIC; + +-- RX Detect +SIGNAL rxdet_in_rx_det_pdb : STD_LOGIC; +SIGNAL rxdet_in_tx_det_rx : STD_LOGIC; +SIGNAL rxdet_in_clk15m : STD_LOGIC; +SIGNAL rxdet_fixclk_reg : STD_LOGIC; +SIGNAL rxdet_out_rx_found : STD_LOGIC; +SIGNAL rxdet_out_rx_det_valid : STD_LOGIC; + +-- --------------------------------------------------------------------------- +-- New DPRIO Begin +-- --------------------------------------------------------------------------- + + -- Table28: PMA Per Channel TX Control Register 1 for Channel 0 + constant rpowdnt_TXPMA_IDX_0 : integer := 0; + constant reserved_0_TB28_TXPMA_IDX_1 : integer := 1; + constant reserved_0_TB28_TXPMA_IDX_2 : integer := 2; + constant reserved_0_TB28_TXPMA_IDX_3 : integer := 3; + constant reserved_0_TB28_TXPMA_IDX_4 : integer := 4; + constant reserved_0_TB28_TXPMA_IDX_5 : integer := 5; + constant reserved_0_TB28_TXPMA_IDX_6 : integer := 6; + constant reserved_0_TB28_TXPMA_IDX_7 : integer := 7; + constant reserved_0_TB28_TXPMA_IDX_8 : integer := 8; + constant reserved_0_TB28_TXPMA_IDX_9 : integer := 9; + constant reserved_0_TB28_TXPMA_IDX_10 : integer := 10; + constant reserved_0_TB28_TXPMA_IDX_11 : integer := 11; + constant reserved_0_TB28_TXPMA_IDX_12 : integer := 12; + constant rvod_sel_non_pcie_TXPMA_IDX_0 : integer := 13; + constant rvod_sel_non_pcie_TXPMA_IDX_1 : integer := 14; + constant rvod_sel_non_pcie_TXPMA_IDX_2 : integer := 15; + + -- Table29: PMA Per Channel TX Control Register 2 for Channel 0 + constant reserved_0_TB29_TXPMA_IDX_0 : integer := 16; + constant reserved_0_TB29_TXPMA_IDX_1 : integer := 17; + constant reserved_0_TB29_TXPMA_IDX_2 : integer := 18; + constant reserved_0_TB29_TXPMA_IDX_3 : integer := 19; + constant reserved_0_TB29_TXPMA_IDX_4 : integer := 20; + constant reserved_0_TB29_TXPMA_IDX_5 : integer := 21; + constant reserved_0_TB29_TXPMA_IDX_6 : integer := 22; + constant reserved_0_TB29_TXPMA_IDX_7 : integer := 23; + constant reserved_0_TB29_TXPMA_IDX_8 : integer := 24; + constant reserved_0_TB29_TXPMA_IDX_9 : integer := 25; + constant reserved_0_TB29_TXPMA_IDX_10 : integer := 26; + constant rpre_em_1t_no_pcie_TXPMA_IDX_0 : integer := 27; + constant rpre_em_1t_no_pcie_TXPMA_IDX_1 : integer := 28; + constant rpre_em_1t_no_pcie_TXPMA_IDX_2 : integer := 29; + constant rpre_em_1t_no_pcie_TXPMA_IDX_3 : integer := 30; + constant rpre_em_1t_no_pcie_TXPMA_IDX_4 : integer := 31; + + -- Table30: PMA Per Channel TX Control Register 3 for Channel 0 + constant reserved_0_TB30_TXPMA_IDX_0 : integer := 32; + constant reserved_0_TB30_TXPMA_IDX_1 : integer := 33; + constant reserved_0_TB30_TXPMA_IDX_2 : integer := 34; + constant reserved_0_TB30_TXPMA_IDX_3 : integer := 35; + constant reserved_0_TB30_TXPMA_IDX_4 : integer := 36; + constant reserved_0_TB30_TXPMA_IDX_5 : integer := 37; + constant reserved_0_TB30_TXPMA_IDX_6 : integer := 38; + constant reserved_0_TB30_TXPMA_IDX_7 : integer := 39; + constant reserved_0_TB30_TXPMA_IDX_8 : integer := 40; + constant reserved_0_TB30_TXPMA_IDX_9 : integer := 41; + constant reserved_0_TB30_TXPMA_IDX_10 : integer := 42; + constant reserved_0_TB30_TXPMA_IDX_11 : integer := 43; + constant reserved_0_TB30_TXPMA_IDX_12 : integer := 44; + constant reserved_0_TB30_TXPMA_IDX_13 : integer := 45; + constant reserved_0_TB30_TXPMA_IDX_14 : integer := 46; + constant reserved_0_TB30_TXPMA_IDX_15 : integer := 47; + + -- Table31: PMA Per Channel TX Control Register 4 for Channel 0 + constant rlowv_TXPMA_IDX_0 : integer := 48; + constant rrx_det_TXPMA_IDX_0 : integer := 49; + constant rrx_det_TXPMA_IDX_1 : integer := 50; + constant reserved_0_TB31_TXPMA_IDX_3 : integer := 51; + constant reserved_0_TB31_TXPMA_IDX_4 : integer := 52; + constant rslew_TXPMA_IDX_0 : integer := 53; + constant rslew_TXPMA_IDX_1 : integer := 54; + constant rtx_lst_TXPMA_IDX_0 : integer := 55; + constant rtx_lst_TXPMA_IDX_1 : integer := 56; + constant rtx_lst_TXPMA_IDX_2 : integer := 57; + constant rtx_lst_TXPMA_IDX_3 : integer := 58; + constant rtx_vtt_TXPMA_IDX_0 : integer := 59; + constant rtx_vtt_TXPMA_IDX_1 : integer := 60; + constant rtx_term_sel_TXPMA_IDX_0 : integer := 61; + constant rtx_term_sel_TXPMA_IDX_1 : integer := 62; + constant rtx_term_sel_TXPMA_IDX_2 : integer := 63; + + -- Table32: PMA Per Channel TX Control Register 5 for Channel 0 + constant reserved_1_TB32_TXPMA_IDX_0 : integer := 64; + constant reserved_1_TB32_TXPMA_IDX_1 : integer := 65; + constant reserved_1_TB32_TXPMA_IDX_2 : integer := 66; + constant reserved_1_TB32_TXPMA_IDX_3 : integer := 67; + constant reserved_1_TB32_TXPMA_IDX_4 : integer := 68; + constant reserved_1_TB32_TXPMA_IDX_5 : integer := 69; + constant reserved_1_TB32_TXPMA_IDX_6 : integer := 70; + constant reserved_1_TB32_TXPMA_IDX_7 : integer := 71; + constant reserved_1_TB32_TXPMA_IDX_8 : integer := 72; + constant reserved_1_TB32_TXPMA_IDX_9 : integer := 73; + constant reserved_1_TB32_TXPMA_IDX_10 : integer := 74; + constant rtx_ob_pdb_TXPMA_IDX_0 : integer := 75; + constant reserved_0_TB32_TXPMA_IDX_0 : integer := 76; + constant r_dft_sel_TXPMA_IDX_0 : integer := 77; + constant r_dft_sel_TXPMA_IDX_1 : integer := 78; + constant r_dft_sel_TXPMA_IDX_2 : integer := 79; + + -- Table33: PMA Per Channel TX Control Register 6 for Channel 0 + constant reserved_0_TB33_TXPMA_IDX_0 : integer := 80; + constant reserved_0_TB33_TXPMA_IDX_1 : integer := 81; + constant reserved_0_TB33_TXPMA_IDX_2 : integer := 82; + constant reserved_0_TB33_TXPMA_IDX_3 : integer := 83; + constant rtx_cgb_pdb_TXPMA_IDX_0 : integer := 84; + constant reserved_0_TB33_TXPMA_IDX_5 : integer := 85; + constant reserved_0_TB33_TXPMA_IDX_6 : integer := 86; + constant reserved_0_TB33_TXPMA_IDX_7 : integer := 87; + constant reserved_0_TB33_TXPMA_IDX_8 : integer := 88; + constant rpmadwidth_tx_TXPMA_IDX_0 : integer := 89; + constant reserved_0_TB33_TXPMA_IDX_10 : integer := 90; + constant reserved_0_TB33_TXPMA_IDX_11 : integer := 91; + constant reserved_0_TB33_TXPMA_IDX_12 : integer := 92; + constant reserved_0_TB33_TXPMA_IDX_13 : integer := 93; + constant reserved_0_TB33_TXPMA_IDX_14 : integer := 94; + constant reserved_0_TB33_TXPMA_IDX_15 : integer := 95; + + -- Table34: PMA Per Channel TX Control Register 7 for Channel 0 + constant ricdr_reserved_0_TB34_TXPMA_IDX_8 : integer := 96; + constant ricdr_reserved_0_TB34_TXPMA_IDX_9 : integer := 97; + constant ricdr_reserved_0_TB34_TXPMA_IDX_10 : integer := 98; + constant ricdr_reserved_0_TB34_TXPMA_IDX_11 : integer := 99; + constant ricdr_reserved_0_TB34_TXPMA_IDX_12 : integer := 100; + constant ricdr_reserved_0_TB34_TXPMA_IDX_13 : integer := 101; + constant ricdr_reserved_0_TB34_TXPMA_IDX_14 : integer := 102; + constant ricdr_reserved_0_TB34_TXPMA_IDX_15 : integer := 103; + constant ricdr_reserved_0_TB34_TXPMA_IDX_16 : integer := 104; + constant ricdr_reserved_0_TB34_TXPMA_IDX_17 : integer := 105; + constant ricdr_reserved_0_TB34_TXPMA_IDX_18 : integer := 106; + constant ricdr_reserved_0_TB34_TXPMA_IDX_19 : integer := 107; + constant ricdr_reserved_0_TB34_TXPMA_IDX_20 : integer := 108; + constant ricdr_reserved_0_TB34_TXPMA_IDX_21 : integer := 109; + constant ricdr_reserved_0_TB34_TXPMA_IDX_22 : integer := 110; + constant ricdr_reserved_0_TB34_TXPMA_IDX_23 : integer := 111; + + -- Table35: PMA Per Channel TX Control Register 8 for Channel 0 + constant rpma_reserved_0_TB35_TXPMA_IDX_0 : integer := 112; + constant rpma_reserved_0_TB35_TXPMA_IDX_1 : integer := 113; + constant rpma_reserved_0_TB35_TXPMA_IDX_2 : integer := 114; + constant rpma_reserved_0_TB35_TXPMA_IDX_3 : integer := 115; + constant rpma_reserved_0_TB35_TXPMA_IDX_4 : integer := 116; + constant rpma_reserved_0_TB35_TXPMA_IDX_5 : integer := 117; + constant rpma_reserved_0_TB35_TXPMA_IDX_6 : integer := 118; + constant rpma_reserved_0_TB35_TXPMA_IDX_7 : integer := 119; + constant rpma_reserved_0_TB35_TXPMA_IDX_8 : integer := 120; + constant rpma_reserved_0_TB35_TXPMA_IDX_9 : integer := 121; + constant rpma_reserved_0_TB35_TXPMA_IDX_10 : integer := 122; + constant rpma_reserved_0_TB35_TXPMA_IDX_11 : integer := 123; + constant rpma_reserved_0_TB35_TXPMA_IDX_12 : integer := 124; + constant rpma_reserved_0_TB35_TXPMA_IDX_13 : integer := 125; + constant rpma_reserved_0_TB35_TXPMA_IDX_14 : integer := 126; + constant rpma_reserved_0_TB35_TXPMA_IDX_15 : integer := 127; + + -- Manually added cram bit that shared with RX PMA + constant rpma_loopback1 : integer := 203; + constant rpma_loopback3 : integer := 204; + -- --------------------------------------------------------------------------- + -- DPRIO input CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel TX Control Register 6 for Channel 0 + SIGNAL dprioin_rpmadwidth_tx : STD_LOGIC; + + -- PMA Per Channel TX Control that shared with RX PMA + SIGNAL dprioin_rpma_loopback1 : STD_LOGIC; + SIGNAL dprioin_rpma_loopback3 : STD_LOGIC; + -- --------------------------------------------------------------------------- + -- CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel TX Control Register 6 for Channel 0 + SIGNAL cram_rpmadwidth_tx : STD_LOGIC; + -- PMA Per Channel TX Control that shared with RX PMA + SIGNAL cram_rpma_rloopback1 : STD_LOGIC; + SIGNAL cram_rpma_rloopback3 : STD_LOGIC; + + -- ----------------------------------- + -- Initial CRAM ---------------------- + -- ----------------------------------- + + -- PMA Per Channel TX Control Register 1 for Channel 0 + SIGNAL init_rpowdnt : STD_LOGIC; + SIGNAL init_rvod_sel_non_pcie : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- PMA Per Channel TX Control Register 2 for Channel 0 + SIGNAL init_rpre_em_1t_no_pcie : STD_LOGIC_VECTOR(4 DOWNTO 0); + + -- PMA Per Channel TX Control Register 4 for Channel 0 + SIGNAL init_rlowv : STD_LOGIC; + SIGNAL init_rrx_det : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rslew : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rtx_term_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rtx_vtt : STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- PMA Per Channel TX Control Register 6 for Channel 0 + SIGNAL init_rtx_cgb_pdb : STD_LOGIC; + SIGNAL init_rpmadwidth_tx : STD_LOGIC; + SIGNAL init_rs_lpbk : STD_LOGIC; + +BEGIN + + -- Resets + txpma_rstb <= mux_select((txpmareset = '1'), '0', '1'); + cgb_pdb <= mux_select((cgbpowerdn = '1'), '0', '1'); -- not in wys yet + tx_pdb <= mux_select((powerdn = '1'), '0', '1'); + + -- Drive referenced outputs + dataout <= mux_select((tx_pdb = '0'), '0', + mux_select((forceelecidle = '1'), 'Z', dataout_buf)); + + dataout_buf <= (mux_select((enable_reverse_serial_loopback = ("true") OR (cram_rpma_rloopback3 = '1' AND cram_rpma_rloopback1 = '0')), reverselpbkin, + mux_select((enable_diagnostic_loopback = ("true") OR cram_rpma_rloopback1 = '1'), diagnosticlpbkin, + mux_select((enable_txclkout_loopback = ("true")), refclk0in, ser_dataout)))); + -- Serializer + clockout <= refclk0in; + seriallpbkout <= ser_dataout; + + -- RX Detect + rxfoundout <= rxdet_out_rx_found; + rxdetectvalidout <= rxdet_out_rx_det_valid; + rxdet_in_clk15m <= rxdet_fixclk_reg; + rxdet_in_rx_det_pdb <= mux_select((detectrxpowerdown = '1'), '0', '1'); + rxdet_in_tx_det_rx <= mux_select((rxdetecten = '1'), '1', '0'); + + -- --------------------------------------------------------------------------- + -- Set DPRIO CRAM input from dprioin + -- --------------------------------------------------------------------------- + + -- PMA Per Channel TX Control Register 6 for Channel 0 + dprioin_rpmadwidth_tx <= dprioin(rpmadwidth_tx_TXPMA_IDX_0); + + -- PMA Per Channel TX Control that shared with RX PMA + dprioin_rpma_loopback1 <= dprioin(rpma_loopback1); + dprioin_rpma_loopback3 <= dprioin(rpma_loopback3); + -- --------------------------------------------------------------------------- + -- Set DPRIO output from initial CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel TX Control Register 1 for Channel 0 + dprioout(rpowdnt_TXPMA_IDX_0) <= init_rpowdnt; + dprioout(rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rvod_sel_non_pcie_TXPMA_IDX_0) <= init_rvod_sel_non_pcie; + + -- PMA Per Channel TX Control Register 2 for Channel 0 + dprioout(rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO rpre_em_1t_no_pcie_TXPMA_IDX_0) <= init_rpre_em_1t_no_pcie; + + -- PMA Per Channel TX Control Register 4 for Channel 0 + dprioout(rlowv_TXPMA_IDX_0) <= init_rlowv; + dprioout(rrx_det_TXPMA_IDX_1 DOWNTO rrx_det_TXPMA_IDX_0) <= init_rrx_det; + dprioout(rslew_TXPMA_IDX_1 DOWNTO rslew_TXPMA_IDX_0) <= init_rslew; + dprioout(rtx_vtt_TXPMA_IDX_1 DOWNTO rtx_vtt_TXPMA_IDX_0) <= init_rtx_vtt; + dprioout(rtx_term_sel_TXPMA_IDX_2 DOWNTO rtx_term_sel_TXPMA_IDX_0) <= init_rtx_term_sel; + + -- PMA Per Channel TX Control Register 6 for Channel 0 + dprioout(rtx_cgb_pdb_TXPMA_IDX_0) <= init_rtx_cgb_pdb; + dprioout(rpmadwidth_tx_TXPMA_IDX_0) <= init_rpmadwidth_tx; + + -- PMA Per Channel TX Control that shared with RX PMA + dprioout(rpma_loopback1) <= init_rs_lpbk; + dprioout(rpma_loopback3) <= init_rs_lpbk; + -- --------------------------------------------------------------------------- + -- Set DPRIO CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel TX Control Register 6 for Channel 0 + cram_rpmadwidth_tx <= init_rpmadwidth_tx WHEN (dpriodisable /= '0') ELSE dprioin_rpmadwidth_tx; + -- PMA Per Channel TX Control that shared with RX PMA + cram_rpma_rloopback1 <= init_rs_lpbk WHEN (dpriodisable /= '0') ELSE dprioin_rpma_loopback1; + cram_rpma_rloopback3 <= init_rs_lpbk WHEN (dpriodisable /= '0') ELSE dprioin_rpma_loopback3; + + -- -------------------------------------------- + -- CRAM bits ---------------------------------- + -- -------------------------------------------- + + PROCESS + BEGIN + -- TX PMA control register 1 + init_rpowdnt <= '0'; + init_rvod_sel_non_pcie <= mux_select((vod_selection = 0), "000", mux_select((vod_selection = 1), "001", mux_select((vod_selection = 2), "010", mux_select((vod_selection = 3), "011", mux_select((vod_selection = 4), "111", mux_select((vod_selection = 5), "100", mux_select((vod_selection = 6), "101", "000"))))))); + + -- TX PMA control register 2 + init_rpre_em_1t_no_pcie <= mux_select((preemp_tap_1 = 1), "00001", + mux_select((preemp_tap_1 = 5), "00101", + mux_select((preemp_tap_1 = 9), "01001", + mux_select((preemp_tap_1 = 13), "01101", + mux_select((preemp_tap_1 = 16), "10000", + mux_select((preemp_tap_1 = 17), "10001", + mux_select((preemp_tap_1 = 18), "10010", + mux_select((preemp_tap_1 = 19), "10011", + mux_select((preemp_tap_1 = 20), "10100", + mux_select((preemp_tap_1 = 21), "10101", "XXXXX")))))))))); + + -- TX PMA control register 4 + init_rlowv <= '0'; + init_rrx_det <= mux_select((rx_detect = 1), "01", + mux_select((rx_detect = 2), "10", + mux_select((rx_detect = 3), "11", "00"))); + + init_rslew <= mux_select((alpha_tolower(slew_rate) = ("low")), "01", + mux_select((alpha_tolower(slew_rate) = ("medium")), "10", + mux_select((alpha_tolower(slew_rate) = ("high")), "11", "00"))); + + init_rtx_term_sel(1 DOWNTO 0) <= (mux_select((alpha_tolower(termination) = ("oct 150 ohms")), "00", mux_select((alpha_tolower(termination) = ("oct 100 ohms")), "10", "XX"))); + init_rtx_term_sel(2) <= mux_select((use_external_termination = ("true")), '1', '0'); + + init_rtx_vtt <= mux_select((alpha_tolower(common_mode) = ("tristate")), "00", + mux_select((alpha_tolower(common_mode) = ("0.65v")), "11", "XX")); + + -- TX PMA Control Register 6 + init_rtx_cgb_pdb <= '0'; + init_rpmadwidth_tx <= mux_select((serialization_factor = 10), '1', '0'); + init_rs_lpbk <= mux_select((enable_reverse_serial_loopback = ("true")), '1', '0'); + WAIT; + END PROCESS; + + -- -------------------------------------------- + -- Behavior model starting here --------------- + -- -------------------------------------------- + + -- RX Detect + PROCESS + BEGIN + rxdet_fixclk_reg <= '0'; + WHILE (TRUE) LOOP + WAIT FOR 4000 ps; + rxdet_fixclk_reg <= NOT(rxdet_fixclk_reg); + END LOOP; + WAIT; + END PROCESS; + +tx_pma_ser : cycloneiv_hssi_tx_pma_sub_ser +GENERIC MAP ( + channel_width => serialization_factor +) +PORT MAP ( + clk0 => fastrefclk0in, + cgb_pdb => cgb_pdb, -- not in wys yet + enable0 => refclk0inpulse, + datain => datain, + serialdatain => '0', + postdpaserialdatain => '0', + dataout => ser_dataout, + --serialfdbkout => , + dpaclkin => '0', + devclrn => txpma_rstb, + devpor => '1' +); + +m_rxdet : cycloneiv_hssi_tx_pma_sub_tx_rx_det +PORT MAP ( + rx_det_pdb => rxdet_in_rx_det_pdb, + clk15m => rxdet_in_clk15m, + tx_det_rx => rxdet_in_tx_det_rx, + rx_found => rxdet_out_rx_found, + rx_det_valid => rxdet_out_rx_det_valid +); + +END trans; +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_rx_pma_sub_deser +-- +-- Description : Timing simulation model for the cycloneiv RX PMA +-- Deserializer. This module receives serial data and outputs +-- parallel data word of width = channel_width +-- +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY cycloneiv_hssi_rx_pma_sub_deser IS + GENERIC ( + channel_width : INTEGER := 8 + ); + PORT ( + fclk : IN STD_LOGIC := '0'; + deven : IN STD_LOGIC := '0'; + dodd : IN STD_LOGIC := '0'; + loaden : IN STD_LOGIC := '0'; + clr : IN STD_LOGIC := '0'; + rxdat : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) + ); +END cycloneiv_hssi_rx_pma_sub_deser; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_pma_sub_deser IS + -- INTERNAL VARIABLES AND NETS + SIGNAL rxdat_tmp : STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000" ; + SIGNAL rxdat_output : STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000" ; + + SIGNAL i : INTEGER := 0 ; + SIGNAL clr_edge : STD_LOGIC := '0' ; +BEGIN + PROCESS (loaden, clr) + BEGIN + IF (clr = '1') THEN + rxdat_output <= "0000000000"; + rxdat <= "0000000000"; + ELSE + IF (loaden = '1') THEN + rxdat_output <= rxdat_tmp; + ELSIF (loaden = '0') THEN + rxdat <= rxdat_output; + END IF; + END IF; + END PROCESS; + + PROCESS (fclk, clr) + BEGIN + IF (clr = '1') THEN + rxdat_tmp <= "0000000000"; + i <= 0; + clr_edge <= '1'; + ELSE + IF (clr_edge = '1') THEN + clr_edge <= '0'; + ELSIF (rising_edge(fclk)) THEN + rxdat_tmp(7 DOWNTO 0) <= rxdat_tmp(9 DOWNTO 2); + rxdat_tmp(8) <= deven; + rxdat_tmp(9) <= dodd; + END IF; + END IF; + END PROCESS; +END trans; + +------------------------------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_rx_pma_sub_clkdiv +-- +-- Description : Cyclone IV GX RX PMA Clock divider +-- +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY cycloneiv_hssi_rx_pma_sub_clkdiv IS + PORT ( + rxfclk : IN STD_LOGIC := '0'; + clr : IN STD_LOGIC := '0'; + deser_fact : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + loaden : OUT STD_LOGIC; + clkdivrx : OUT STD_LOGIC + ); +END cycloneiv_hssi_rx_pma_sub_clkdiv; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_pma_sub_clkdiv IS + SIGNAL clk_count_prev : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000" ; + SIGNAL clk_count : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000" ; + + SIGNAL first_clkcount : STD_LOGIC := '0' ; + SIGNAL clkdivrx_prev : STD_LOGIC := '0' ; + SIGNAL rxloaden : STD_LOGIC := '0' ; + SIGNAL clkdivrx_tmp : STD_LOGIC := '1' ; + SIGNAL loaden_tmp : STD_LOGIC := '0' ; + +BEGIN + -- Drive referenced outputs + loaden <= loaden_tmp; + clkdivrx <= clkdivrx_tmp; + + PROCESS (clk_count_prev) + BEGIN + clk_count <= clk_count_prev + "0001"; + END PROCESS; + + -- rxloaden + PROCESS (rxfclk) + BEGIN + IF (clkdivrx_tmp = '0' OR first_clkcount = '0') THEN + rxloaden <= '0'; + ELSIF (falling_edge(rxfclk) AND (clkdivrx_tmp = '1' OR rising_edge(clkdivrx_tmp))) THEN + rxloaden <= NOT rxloaden; + END IF; + END PROCESS; + + PROCESS (rxfclk, clr) + BEGIN + IF (clr = '1') THEN + clkdivrx_tmp <= '1'; + loaden_tmp <= '0'; + clkdivrx_prev <= '1'; + clk_count_prev <= "0000"; + first_clkcount <= '0'; + ELSIF (clr = '0') THEN + -- clockout + IF (first_clkcount = '0' AND rising_edge(rxfclk)) THEN + first_clkcount <= '1'; + clk_count_prev <= "0000"; + clkdivrx_tmp <= '0'; + ELSIF (clk_count = deser_fact) THEN + clk_count_prev <= "0000"; + clkdivrx_tmp <= NOT (clkdivrx_prev); + ELSE + clk_count_prev <= clk_count; + END IF; + clkdivrx_prev <= clkdivrx_tmp; + + -- loaden + IF (rising_edge(rxfclk)) THEN + IF (rxloaden = '1') THEN + loaden_tmp <= '1'; + ELSIF (rxloaden = '0') THEN + loaden_tmp <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + +END trans;-- *********************************************************** +-- This WYSIWYG atom header was automatically generated by the +-- Atmgen build tool. To change it, alter data stored in the +-- corresponding WYS file(s) in the tools-atmgen subdirectory. +-- *********************************************************** + +-- *** Section 1 -- Header *** + +-- ----------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_rx_pma +-- +-- Description : DEV_FAMILY_cycloneiv cycloneiv_hssi_rx_pma Verilog simulation model +-- +-- ----------------------------------------------------------- + +-- *** End of Section 1 *** + +-- *** Section 3 -- Module declaration *** + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_pma IS + GENERIC ( + lpm_type : STRING := "cycloneiv_hssi_rx_pma"; + allow_serial_loopback : STRING := "false"; + channel_number : INTEGER := 0; + common_mode : STRING := "0.82V"; + deserialization_factor : INTEGER := 8; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + enable_local_divider : STRING := "false"; + enable_dpa_shift : STRING := "false"; + enable_initial_phase_selection : STRING := "false"; + enable_pd_counter_accumulate_mode : STRING := "false"; + enable_ltd : STRING := "false"; + enable_ltr : STRING := "false"; + eq_dc_gain : INTEGER := 0; + eq_setting : INTEGER := 1; + force_signal_detect : STRING := "true"; + initial_phase_value : INTEGER := 0; + logical_channel_address : INTEGER := 0; + offset_cancellation : INTEGER := 0; + pi_frequency_selector : INTEGER := 0; + ppm_gen1_2_xcnt_en : INTEGER := 1; + ppm_post_eidle : INTEGER := 0; + pd1_counter_setting : INTEGER := 5; + pd2_counter_setting : INTEGER := 5; + pd_rising_edge_only : STRING := "false"; + phase_step_add_setting : INTEGER := 2; + phase_step_sub_setting : INTEGER := 1; + ppmselect : INTEGER := 0; + protocol_hint : STRING := "basic"; + effective_data_rate : STRING := "unused"; + send_reverse_serial_loopback_data : STRING := "false"; + send_reverse_serial_loopback_recovered_clk : STRING := "false"; + signal_detect_hysteresis : INTEGER := 4; + signal_detect_hysteresis_valid_threshold : INTEGER := 1; + signal_detect_loss_threshold : INTEGER := 1; + termination : STRING := "OCT 100 Ohms"; + use_external_termination : STRING := "false"; + loop_1_digital_filter : INTEGER := 8; + enable_second_order_loop : STRING := "false" + ); + PORT ( + crupowerdn : IN STD_LOGIC := '0'; + datain : IN STD_LOGIC := '0'; + deserclock : IN STD_LOGIC := '0'; + dpashift : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0'); + locktodata : IN STD_LOGIC := '0'; + locktoref : IN STD_LOGIC := '0'; + powerdn : IN STD_LOGIC := '0'; + ppmdetectrefclk : IN STD_LOGIC := '0'; + rxpmareset : IN STD_LOGIC := '0'; + seriallpbkin : IN STD_LOGIC := '0'; + testbussel : IN STD_LOGIC_VECTOR(3 DOWNTO 0):= (others => '0'); + analogtestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + clockout : OUT STD_LOGIC; + datastrobeout : OUT STD_LOGIC; + diagnosticlpbkout : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0); + freqlocked : OUT STD_LOGIC; + locktorefout : OUT STD_LOGIC; + recoverdataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + reverselpbkout : OUT STD_LOGIC; + signaldetect : OUT STD_LOGIC + ); +END cycloneiv_hssi_rx_pma; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_pma IS + COMPONENT cycloneiv_hssi_rx_pma_sub_deser + GENERIC ( + channel_width : INTEGER := 8 + ); + PORT ( + fclk : IN STD_LOGIC; + deven : IN STD_LOGIC; + dodd : IN STD_LOGIC; + loaden : IN STD_LOGIC; + clr : IN STD_LOGIC; + rxdat : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_pma_sub_clkdiv + PORT ( + rxfclk : IN STD_LOGIC; + clr : IN STD_LOGIC; + deser_fact : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + loaden : OUT STD_LOGIC; + clkdivrx : OUT STD_LOGIC + ); + END COMPONENT; + + ---------------------------------------------------------------------------- + -- Behavior model starting here -------------------------------------------- + ---------------------------------------------------------------------------- + ---------------------------------------------------------------------------- + -- Model / Submodule Instantiations - + ---------------------------------------------------------------------------- + SIGNAL deven : STD_LOGIC := '0' ; + SIGNAL dodd : STD_LOGIC := '0' ; + SIGNAL deven_prev : STD_LOGIC := '0' ; + SIGNAL dodd_prev : STD_LOGIC := '0' ; + SIGNAL rxdata : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL loaden : STD_LOGIC; + SIGNAL first_edge : STD_LOGIC := '1' ; + SIGNAL clkdivrx : STD_LOGIC; + SIGNAL signaldetect_reg : STD_LOGIC := '0' ; + SIGNAL rxdatain : STD_LOGIC; + SIGNAL datain_in : STD_LOGIC; + SIGNAL sd_rx : STD_LOGIC; + SIGNAL sd_reset : STD_LOGIC; + SIGNAL mfreqlocked_reg : STD_LOGIC := '0' ; + SIGNAL mfreqlocked_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000" ; + SIGNAL signal_detect_reg_n : STD_LOGIC; + SIGNAL sd_cdr : STD_LOGIC; + SIGNAL clockout_xhdl0 : STD_LOGIC; + SIGNAL locktorefout_xhdl1 : STD_LOGIC; + SIGNAL recoverdataout_xhdl2 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL signaldetect_xhdl3 : STD_LOGIC; + SIGNAL locktorefout_freqlock : STD_LOGIC := '0'; + SIGNAL deserclock_div_2 : STD_LOGIC := '0'; + SIGNAL deserclock_local_div : STD_LOGIC := '0'; + -- lpbk signals + SIGNAL rlpbk_data : STD_LOGIC; + SIGNAL rlpbk_clk : STD_LOGIC; + SIGNAL clr : STD_LOGIC; + -- for dpashift + SIGNAL dpashift_on : STD_LOGIC := '0'; + SIGNAL deserclock_dly : STD_LOGIC := '0'; + SIGNAL prev_posedge : TIME := 0.0 ps; + SIGNAL deserclock_period : TIME := 0.0 ps; + SIGNAL deserclock_delay : TIME := 0.0 ps; + + -- --------------------------------------------------------------------------- + -- New DPRIO Begin + -- --------------------------------------------------------------------------- +-- Table34: PMA Per Channel TX Control Register 7 for Channel 0 (RX PMA) +constant ricdr_reserved_0_TB34_TXPMA_IDX_0 : integer := 0; +constant ricdr_reserved_0_TB34_TXPMA_IDX_1 : integer := 1; +constant ricdr_reserved_1_TB34_TXPMA_IDX_0 : integer := 2; +constant ricdr_reserved_1_TB34_TXPMA_IDX_1 : integer := 3; +constant ricdr_reserved_2_TB34_TXPMA_IDX_0 : integer := 4; +constant ricdr_reserved_2_TB34_TXPMA_IDX_1 : integer := 5; +constant ricdr_ssc_enable : integer := 6; +constant ricdr_en_local_clkdiv : integer := 7; +constant ricdr_rlocdiv_TXPMA_IDX_0 : integer := 8; +constant ricdr_rlocdiv_TXPMA_IDX_1 : integer := 9; +constant ricdr_rlocdiv_TXPMA_IDX_2 : integer := 10; +constant ricdr_rlocdiv_TXPMA_IDX_3 : integer := 11; +constant ricdr_rlocdiv_TXPMA_IDX_4 : integer := 12; +constant ricdr_rlocdiv_TXPMA_IDX_5 : integer := 13; +constant ricdr_rlocdiv_TXPMA_IDX_6 : integer := 14; +constant ricdr_rlocdiv_TXPMA_IDX_7 : integer := 15; + + + -- Table36: PMA Per Channel RX Control Register 1 for Channel 0 +constant rrx_term_sel_RXPMA_IDX_0 : integer := 16; +constant rrx_term_sel_RXPMA_IDX_1 : integer := 17; +constant rrx_term_sel_RXPMA_IDX_2 : integer := 18; +constant rrx_vtt_RXPMA_IDX_0 : integer := 19; +constant rrx_vtt_RXPMA_IDX_1 : integer := 20; +constant rrx_vtt_RXPMA_IDX_2 : integer := 21; +constant rrx_s_rdlpbk_RXPMA_IDX_0 : integer := 22; +constant rrx_bit_dc_RXPMA_IDX_0 : integer := 23; +constant rrx_bit_dc_RXPMA_IDX_1 : integer := 24; +constant rrx_bit_dc_RXPMA_IDX_2 : integer := 25; +constant rrx_bit_dc_RXPMA_IDX_3 : integer := 26; +constant rrx_lst_RXPMA_IDX_0 : integer := 27; +constant rrx_lst_RXPMA_IDX_1 : integer := 28; +constant rrx_lst_RXPMA_IDX_2 : integer := 29; +constant rrx_lst_RXPMA_IDX_3 : integer := 30; +constant rrx_lst_RXPMA_IDX_4 : integer := 31; + + -- Table37: PMA Per Channel RX Control Register 2 for Channel 0 +constant rrxurstpma_RXPMA_IDX_0 : integer := 32; +constant rrx_test_RXPMA_IDX_0 : integer := 33; +constant rrx_sd_force_RXPMA_IDX_0 : integer := 34; +constant rrx_oc_RXPMA_IDX_0 : integer := 35; +constant rrx_oc_RXPMA_IDX_1 : integer := 36; +constant rrx_oc_RXPMA_IDX_2 : integer := 37; +constant rrx_oc_RXPMA_IDX_3 : integer := 38; +constant rrx_oc_RXPMA_IDX_4 : integer := 39; +constant rrx_oc_RXPMA_IDX_5 : integer := 40; +constant rrx_oc_RXPMA_IDX_6 : integer := 41; +constant rrx_oc_RXPMA_IDX_7 : integer := 42; +constant rrx_oc_en_RXPMA_IDX_0 : integer := 43; +constant rrx_sdlv_RXPMA_IDX_0 : integer := 44; +constant rrx_sdlv_RXPMA_IDX_1 : integer := 45; +constant rrx_sdlv_RXPMA_IDX_2 : integer := 46; +constant rrx_sdlv_RXPMA_IDX_3 : integer := 47; + + -- Table38: PMA Per Channel RX Control Register 3 for Channel 0 +constant reserved_0_TB38_RXPMA_IDX_0 : integer := 48; +constant reserved_0_TB38_RXPMA_IDX_1 : integer := 49; +constant reserved_0_TB38_RXPMA_IDX_2 : integer := 50; +constant rpowdnr_RXPMA_IDX_0 : integer := 51; +constant rrx_ib_pdb_RXPMA_IDX_0 : integer := 52; +constant rurx_pdb_RXPMA_IDX_0 : integer := 53; +constant rrx_oc_calpd_RXPMA_IDX_0 : integer := 54; +constant rrx_sd_off_RXPMA_IDX_0 : integer := 55; +constant rrx_sd_off_RXPMA_IDX_1 : integer := 56; +constant rrx_sd_off_RXPMA_IDX_2 : integer := 57; +constant rrx_sd_off_RXPMA_IDX_3 : integer := 58; +constant rrx_sd_off_RXPMA_IDX_4 : integer := 59; +constant rrx_sd_on_RXPMA_IDX_0 : integer := 60; +constant rrx_sd_on_RXPMA_IDX_1 : integer := 61; +constant rrx_sd_on_RXPMA_IDX_2 : integer := 62; +constant rrx_sd_on_RXPMA_IDX_3 : integer := 63; + + -- Table39: PMA Per Channel RX Control Register 4 for Channel 0 +constant ricdr_freq_sel_pi_IDX_0 : integer := 64; +constant ricdr_freq_sel_pi_IDX_1 : integer := 65; +constant rdefact_RXPMA_IDX_0 : integer := 66; +constant rdefact_RXPMA_IDX_1 : integer := 67; +constant rdefact_RXPMA_IDX_2 : integer := 68; +constant rdefact_RXPMA_IDX_3 : integer := 69; +constant ricdr_rcl_prst_IDX_0 : integer := 70; +constant ricdr_rcl_prst_IDX_1 : integer := 71; +constant ricdr_rcl_prst_IDX_2 : integer := 72; +constant ricdr_rcl_prst_IDX_3 : integer := 73; +constant ricdr_rcl_prst_IDX_4 : integer := 74; +constant ricdr_rcl_prst_IDX_5 : integer := 75; +constant ricdr_rcl_prst_IDX_6 : integer := 76; +constant ricdr_rcl_prst_IDX_7 : integer := 77; +constant ricdr_rcl_hi_DP : integer := 78; +constant ricdr_rcl_lo_DP : integer := 79; + + -- Table40: PMA Per Channel RX Control Register 5 for Channel 0 +constant ricdr_rcl_hi_tb40_IDX_0 : integer := 80; +constant ricdr_rcl_hi_tb40_IDX_1 : integer := 81; +constant ricdr_rcl_hi_tb40_IDX_2 : integer := 82; +constant ricdr_rcl_hi_tb40_IDX_3 : integer := 83; +constant ricdr_rcl_hi_tb40_IDX_4 : integer := 84; +constant ricdr_rcl_hi_tb40_IDX_5 : integer := 85; +constant ricdr_rcl_hi_tb40_IDX_6 : integer := 86; +constant ricdr_rcl_hi_tb40_IDX_7 : integer := 87; +constant ricdr_rcl_lo_tb40_IDX_0 : integer := 88; +constant ricdr_rcl_lo_tb40_IDX_1 : integer := 89; +constant ricdr_rcl_lo_tb40_IDX_2 : integer := 90; +constant ricdr_rcl_lo_tb40_IDX_3 : integer := 91; +constant ricdr_rcl_lo_tb40_IDX_4 : integer := 92; +constant ricdr_rcl_lo_tb40_IDX_5 : integer := 93; +constant ricdr_rcl_lo_tb40_IDX_6 : integer := 94; +constant ricdr_rcl_lo_tb40_IDX_7 : integer := 95; + + -- Table41: PMA Per Channel RX Control Register 6 for Channel 0 +constant reserved_0_tb41_IDX_0 : integer := 96; +constant reserved_1_tb41_IDX_0 : integer := 97; +constant reserved_2_tb41_IDX_0 : integer := 98; +constant reserved_2_tb41_IDX_1 : integer := 99; +constant reserved_2_tb41_IDX_2 : integer := 100; +constant reserved_2_tb41_IDX_3 : integer := 101; +constant reserved_3_tb41_IDX_0 : integer := 102; +constant reserved_3_tb41_IDX_1 : integer := 103; +constant rclocktree_reserved_tb41_IDX_0 : integer := 104; +constant rclocktree_reserved_tb41_IDX_1 : integer := 105; +constant reserved_4_tb41_IDX_0 : integer := 106; +constant reserved_5_tb41_IDX_0 : integer := 107; +constant rrx_cru_pdb_IDX_0 : integer := 108; +constant rltr_RXPMA_IDX_0 : integer := 109; +constant rltd_RXPMA_IDX_0 : integer := 110; +constant reserved_6_tb41_IDX_0 : integer := 111; + +-- Table42: PMA Per Channel RX Control Register 7 for Channel 0 +constant rphsel_clkdivrx_RXPMA_IDX_0 : integer := 112; +constant rrisedge_RXPMA_IDX_0 : integer := 113; +constant rpdof_en_RXPMA_IDX_0 : integer := 114; +constant rcntfact_RXPMA_IDX_0 : integer := 115; +constant rcntfact_RXPMA_IDX_1 : integer := 116; +constant rcntfact_RXPMA_IDX_2 : integer := 117; +constant rcntfact2_RXPMA_IDX_0 : integer := 118; +constant rcntfact2_RXPMA_IDX_1 : integer := 119; +constant rcntfact2_RXPMA_IDX_2 : integer := 120; +constant ropt1_RXPMA_IDX_0 : integer := 121; +constant rrtest_RXPMA_IDX_0 : integer := 122; +constant rrtest2_RXPMA_IDX_0 : integer := 123; +constant ricdrclkout_RXPMA_IDX_0 : integer := 124; +constant rtxfclkout_RXPMA_IDX_0 : integer := 125; +constant rjtaglp_RXPMA_IDX_2 : integer := 126; +constant reserved_0_tb42_IDX_0 : integer := 127; + + -- Table43: PMA Per Channel RX Control Register 8 for Channel 0 +constant rloopback1_RXPMA_IDX_0 : integer := 128; +constant rloopback2_RXPMA_IDX_0 : integer := 129; +constant rloopback3_RXPMA_IDX_0 : integer := 130; +constant rendpa_RXPMA_IDX_0 : integer := 131; +constant rup_RXPMA_IDX_0 : integer := 132; +constant rdn_RXPMA_IDX_0 : integer := 133; +constant rtxclk_en_b_RXPMA_IDX_0 : integer := 134; +constant rtxclk_en_t_RXPMA_IDX_0 : integer := 135; +constant rfrefmx_RXPMA_IDX_0 : integer := 136; +constant rtxclk_divmx_RXPMA_IDX_0 : integer := 137; +constant rtxloadmx_RXPMA_IDX_0 : integer := 138; +constant rtxfclkmx_RXPMA_IDX_0 : integer := 139; +constant rntri_icdrtree_RXPMA_IDX_0 : integer := 140; +constant rntri_lvdstree_RXPMA_IDX_0 : integer := 141; +constant rsel_lvdstree_RXPMA_IDX_0 : integer := 142; +constant reserved_0_TB43_RXPMA_IDX_0 : integer := 143; + + -- Table44: PMA Per Channel RX Control Register 9 for Channel 0 +constant rclk_sd_RXPMA_IDX_0 : integer := 144; +constant rclk_sd_RXPMA_IDX_1 : integer := 145; +constant rtestenp_sd_RXPMA_IDX_0 : integer := 146; +constant rtestenn_sd_RXPMA_IDX_0 : integer := 147; +constant rshiften_RXPMA_IDX_0 : integer := 148; +constant radd_RXPMA_IDX_0 : integer := 149; +constant radd_RXPMA_IDX_1 : integer := 150; +constant rsub_RXPMA_IDX_0 : integer := 151; +constant rsub_RXPMA_IDX_1 : integer := 152; +constant rphenable_RXPMA_IDX_0 : integer := 153; +constant rprst_RXPMA_IDX_0 : integer := 154; +constant rprst_RXPMA_IDX_1 : integer := 155; +constant rprst_RXPMA_IDX_2 : integer := 156; +constant rprst_RXPMA_IDX_3 : integer := 157; +constant rprst_RXPMA_IDX_4 : integer := 158; +constant rprst_RXPMA_IDX_5 : integer := 159; + +-- Table45: PMA Per Channel RX Control Register 10 for Channel 0 +constant rppm_cnt_reset_RXPMA_IDX_0 : integer := 160; +constant rforce1_freqdet_RXPMA_IDX_1 : integer := 161; +constant rforce0_freqdet_RXPMA_IDX_0 : integer := 162; +constant rppmsel_RXPMA_IDX_0 : integer := 163; +constant rppmsel_RXPMA_IDX_1 : integer := 164; +constant rppmsel_RXPMA_IDX_2 : integer := 165; +constant rppmsel_RXPMA_IDX_3 : integer := 166; +constant rppmsel_RXPMA_IDX_4 : integer := 167; +constant rppmsel_RXPMA_IDX_5 : integer := 168; +constant reserved_0_TB45_RXPMA_IDX_0 : integer := 169; +constant reserved_0_TB45_RXPMA_IDX_1 : integer := 170; +constant reserved_0_TB45_RXPMA_IDX_2 : integer := 171; +constant reserved_0_TB45_RXPMA_IDX_3 : integer := 172; +constant reserved_1_TB45_RXPMA_IDX_4 : integer := 173; +constant rpmadwidth_rx_RXPMA_IDX_0 : integer := 174; +constant reserved_2_TB45_RXPMA_IDX_0 : integer := 175; + + -- Table46: PMA Per Channel RX Control Register 11 for Channel 0 +constant reserved_0_TB46_RXPMA_IDX_0 : integer := 176; +constant reserved_0_TB46_RXPMA_IDX_1 : integer := 177; +constant reserved_0_TB46_RXPMA_IDX_2 : integer := 178; +constant reserved_0_TB46_RXPMA_IDX_3 : integer := 179; +constant reserved_0_TB46_RXPMA_IDX_4 : integer := 180; +constant reserved_0_TB46_RXPMA_IDX_5 : integer := 181; +constant reserved_0_TB46_RXPMA_IDX_6 : integer := 182; +constant reserved_0_TB46_RXPMA_IDX_7 : integer := 183; +constant rppm_gen1_2xcnt_en_RXPMA_IDX_0 : integer := 184; +constant rppm_post_eidle_del_RXPMA_IDX_0 : integer := 185; +constant r_dfe_2t_RXPMA_IDX_0 : integer := 186; +constant r_dfe_2t_RXPMA_IDX_1 : integer := 187; +constant r_dfe_2t_RXPMA_IDX_2 : integer := 188; +constant r_dfe_1t_RXPMA_IDX_0 : integer := 189; +constant r_dfe_1t_RXPMA_IDX_1 : integer := 190; +constant r_dfe_1t_RXPMA_IDX_2 : integer := 191; + + -- Table47: PMA Per Channel RX Control Register 12 for Channel 0 +constant reqv_set_RXPMA_IDX_0 : integer := 192; +constant reqv_set_RXPMA_IDX_1 : integer := 193; +constant reqv_set_RXPMA_IDX_2 : integer := 194; +constant reqd_set_RXPMA_IDX_0 : integer := 195; +constant reqd_set_RXPMA_IDX_1 : integer := 196; +constant reqd_set_RXPMA_IDX_2 : integer := 197; +constant reqc_set_RXPMA_IDX_0 : integer := 198; +constant reqc_set_RXPMA_IDX_1 : integer := 199; +constant reqc_set_RXPMA_IDX_2 : integer := 200; +constant reqb_set_RXPMA_IDX_0 : integer := 201; +constant reqb_set_RXPMA_IDX_1 : integer := 202; +constant reqb_set_RXPMA_IDX_2 : integer := 203; +constant reqa_set_RXPMA_IDX_0 : integer := 204; +constant reqa_set_RXPMA_IDX_1 : integer := 205; +constant reqa_set_RXPMA_IDX_2 : integer := 206; +constant reserved_0_TB47_RXPMA_IDX_0 : integer := 207; + + -- --------------------------------------------------------------------------- + -- DPRIO input CRAM + -- --------------------------------------------------------------------------- + -- PMA Per Channel RX Control Register 2 for Channel 0 + SIGNAL dprioin_rrx_sd_force : STD_LOGIC; + + -- PMA Per Channel RX Control Register 4 for Channel 0 + SIGNAL dprioin_rdefact : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- PMA Per Channel RX Control Register 7 for Channel 0 + SIGNAL dprioin_ricdrclkout : STD_LOGIC; + + -- PMA Per Channel RX Control Register 8 for Channel 0 + SIGNAL dprioin_rloopback2 : STD_LOGIC; + SIGNAL dprioin_rloopback3 : STD_LOGIC; + + -- PMA Per Channel RX Control Register 9 for Channel 0 + SIGNAL dprioin_rshiften : STD_LOGIC; + + -- PMA Per Channel RX Control Register 7 for Channel 0 (Table 34) + SIGNAL dprioin_bypass_local_div : STD_LOGIC; + + + + + + -- --------------------------------------------------------------------------- + -- Initial CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel RX Control Register 1 for Channel 0 + SIGNAL init_rrx_term_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rrx_vtt : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rrx_bit_dc : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- PMA Per Channel RX Control Register 2 for Channel 0 + SIGNAL init_rrx_sd_force : STD_LOGIC; + SIGNAL init_rrx_sdlv : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- PMA Per Channel RX Control Register 3 for Channel 0 + SIGNAL init_rrx_sd_off : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_rrx_sd_on : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- PMA Per Channel RX Control Register 4 for Channel 0 + SIGNAL init_rdefact : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- PMA Per Channel RX Control Register 7 for Channel 0 + SIGNAL init_rrisedge : STD_LOGIC; + SIGNAL init_rcntfact : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rcntfact2 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_ropt1 : STD_LOGIC; + SIGNAL init_ricdrclkout : STD_LOGIC; + SIGNAL init_bypass_local_div : STD_LOGIC; + + + -- PMA Per Channel RX Control Register 8 for Channel 0 + SIGNAL init_rloopback2 : STD_LOGIC; + SIGNAL init_rloopback3 : STD_LOGIC; + + -- PMA Per Channel RX Control Register 9 for Channel 0 + SIGNAL init_rshiften : STD_LOGIC; + SIGNAL init_radd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rsub : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rphenable : STD_LOGIC; + SIGNAL init_rprst : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PMA Per Channel RX Control Register 10 for Channel 0 + SIGNAL init_rppmsel : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL init_rpmadwidth_rx : STD_LOGIC; + + + -- PMA Per Channel RX Control Register 12 for Channel 0 + SIGNAL init_reqv_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_reqb_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_reqa_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- --------------------------------------------------------------------------- + -- CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel RX Control Register 2 for Channel 0 + SIGNAL cram_rrx_sd_force : STD_LOGIC; + + -- PMA Per Channel RX Control Register 4 for Channel 0 + SIGNAL cram_rdefact : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- PMA Per Channel RX Control Register 7 for Channel 0 + SIGNAL cram_ricdrclkout : STD_LOGIC; + SIGNAL cram_bypass_local_div : STD_LOGIC; + + -- PMA Per Channel RX Control Register 8 for Channel 0 + SIGNAL cram_rloopback2 : STD_LOGIC; + SIGNAL cram_rloopback3 : STD_LOGIC; + + -- PMA Per Channel RX Control Register 9 for Channel 0 + SIGNAL cram_rshiften : STD_LOGIC; + +BEGIN + + -- --------------------------------------------------------------------------- + -- Set DPRIO CRAM input from dprioin + -- --------------------------------------------------------------------------- + + -- PMA Per Channel RX Control Register 2 for Channel 0 + dprioin_rrx_sd_force <= dprioin(rrx_sd_force_RXPMA_IDX_0); + + -- PMA Per Channel RX Control Register 4 for Channel 0 + dprioin_rdefact <= dprioin(rdefact_RXPMA_IDX_3 DOWNTO rdefact_RXPMA_IDX_0); + + + -- PMA Per Channel RX Control Register 7 for Channel 0 + dprioin_ricdrclkout <= dprioin(ricdrclkout_RXPMA_IDX_0); + dprioin_bypass_local_div <= dprioin(ricdr_en_local_clkdiv); + + -- PMA Per Channel RX Control Register 8 for Channel 0 + dprioin_rloopback2 <= dprioin(rloopback2_RXPMA_IDX_0); + dprioin_rloopback3 <= dprioin(rloopback3_RXPMA_IDX_0); + + -- PMA Per Channel RX Control Register 9 for Channel 0 + dprioin_rshiften <= dprioin(rshiften_RXPMA_IDX_0); + + -- --------------------------------------------------------------------------- + -- Set DPRIO CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel RX Control Register 2 for Channel 0 + cram_rrx_sd_force <= init_rrx_sd_force WHEN (dpriodisable /= '0') ELSE dprioin_rrx_sd_force; + + -- PMA Per Channel RX Control Register 4 for Channel 0 + cram_rdefact <= init_rdefact WHEN (dpriodisable /= '0') ELSE dprioin_rdefact; + + -- PMA Per Channel RX Control Register 7 for Channel 0 + cram_ricdrclkout <= init_ricdrclkout WHEN (dpriodisable /= '0') ELSE dprioin_ricdrclkout; + cram_bypass_local_div <= init_bypass_local_div WHEN (dpriodisable /= '0') ELSE dprioin_bypass_local_div; + + -- PMA Per Channel RX Control Register 8 for Channel 0 + cram_rloopback2 <= init_rloopback2 WHEN (dpriodisable /= '0') ELSE dprioin_rloopback2; + cram_rloopback3 <= init_rloopback3 WHEN (dpriodisable /= '0') ELSE dprioin_rloopback3; + + -- PMA Per Channel RX Control Register 9 for Channel 0 + cram_rshiften <= init_rshiften WHEN (dpriodisable /= '0') ELSE dprioin_rshiften; + + -- --------------------------------------------------------------------------- + -- Set DPRIO output from initial CRAM + -- --------------------------------------------------------------------------- + + -- PMA Per Channel RX Control Register 1 for Channel 0 + dprioout(rrx_term_sel_RXPMA_IDX_2 DOWNTO rrx_term_sel_RXPMA_IDX_0) <= init_rrx_term_sel; + dprioout(rrx_vtt_RXPMA_IDX_2 DOWNTO rrx_vtt_RXPMA_IDX_0) <= init_rrx_vtt; + dprioout(rrx_bit_dc_RXPMA_IDX_3 DOWNTO rrx_bit_dc_RXPMA_IDX_0) <= init_rrx_bit_dc; + + -- PMA Per Channel RX Control Register 2 for Channel 0 + dprioout(rrx_sd_force_RXPMA_IDX_0) <= init_rrx_sd_force; + dprioout(rrx_sdlv_RXPMA_IDX_3 DOWNTO rrx_sdlv_RXPMA_IDX_0) <= init_rrx_sdlv; + + -- PMA Per Channel RX Control Register 3 for Channel 0 + dprioout(rrx_sd_off_RXPMA_IDX_4 DOWNTO rrx_sd_off_RXPMA_IDX_0) <= init_rrx_sd_off; + dprioout(rrx_sd_on_RXPMA_IDX_3 DOWNTO rrx_sd_on_RXPMA_IDX_0) <= init_rrx_sd_on; + + -- PMA Per Channel RX Control Register 4 for Channel 0 + dprioout(rdefact_RXPMA_IDX_3 DOWNTO rdefact_RXPMA_IDX_0) <= init_rdefact; + + -- PMA Per Channel RX Control Register 7 for Channel 0 + dprioout(rrisedge_RXPMA_IDX_0) <= init_rrisedge; + dprioout(rcntfact_RXPMA_IDX_2 DOWNTO rcntfact_RXPMA_IDX_0) <= init_rcntfact; + dprioout(rcntfact2_RXPMA_IDX_2 DOWNTO rcntfact2_RXPMA_IDX_0) <= init_rcntfact2; + dprioout(ropt1_RXPMA_IDX_0) <= init_ropt1; + dprioout(ricdrclkout_RXPMA_IDX_0) <= init_ricdrclkout; + dprioout(ricdr_en_local_clkdiv) <= init_bypass_local_div; + + -- PMA Per Channel RX Control Register 8 for Channel 0 + dprioout(rloopback2_RXPMA_IDX_0) <= init_rloopback2; + dprioout(rloopback3_RXPMA_IDX_0) <= init_rloopback3; + + -- PMA Per Channel RX Control Register 9 for Channel 0 + dprioout(rshiften_RXPMA_IDX_0) <= init_rshiften; + dprioout(radd_RXPMA_IDX_1 DOWNTO radd_RXPMA_IDX_0) <= init_radd; + dprioout(rsub_RXPMA_IDX_1 DOWNTO rsub_RXPMA_IDX_0) <= init_rsub; + dprioout(rphenable_RXPMA_IDX_0) <= init_rphenable; + dprioout(rprst_RXPMA_IDX_5 DOWNTO rprst_RXPMA_IDX_0) <= init_rprst; + + -- PMA Per Channel RX Control Register 10 for Channel 0 + dprioout(rppmsel_RXPMA_IDX_5 DOWNTO rppmsel_RXPMA_IDX_0) <= init_rppmsel; + dprioout(rpmadwidth_rx_RXPMA_IDX_0) <= init_rpmadwidth_rx; + + -- PMA Per Channel RX Control Register 12 for Channel 0 + dprioout(reqv_set_RXPMA_IDX_2 DOWNTO reqv_set_RXPMA_IDX_0) <= init_reqv_set; + dprioout(reqb_set_RXPMA_IDX_2 DOWNTO reqb_set_RXPMA_IDX_0) <= init_reqb_set; + dprioout(reqa_set_RXPMA_IDX_2 DOWNTO reqa_set_RXPMA_IDX_0) <= init_reqa_set; + + -- -------------------------------------------------------------------------- + -- Initial CRAM bits --------------------------------------------- + -- -------------------------------------------------------------------------- + + PROCESS + BEGIN + -- RX PMA control register 1 + init_rrx_term_sel(1 DOWNTO 0) <= (mux_select((alpha_tolower(termination) = ("oct 150 ohms")), "00", mux_select((alpha_tolower(termination) = ("oct 100 ohms")), "10", mux_select((alpha_tolower(termination) = ("oct 85 ohms")), "10", "XX")))); + init_rrx_term_sel(2) <= mux_select((use_external_termination = ("true")), '1', '0'); + init_rrx_vtt <= (mux_select((alpha_tolower(common_mode) = ("0.82v")), "010", mux_select((alpha_tolower(common_mode) = ("tristate")), "100", "000"))); + init_rrx_bit_dc <= (mux_select((eq_dc_gain = 3), "0001", mux_select((eq_dc_gain = 6), "0011", mux_select((eq_dc_gain = 9), "0111", mux_select((eq_dc_gain = 12), "1111", "0000"))))); + + -- RX PMA control register 2 + init_rrx_sd_force <= (mux_select((force_signal_detect = ("true")), '1', '0')); + init_rrx_sdlv <= int2bin(signal_detect_hysteresis, 4); + + -- RX PMA control register 3 + init_rrx_sd_off <= int2bin(signal_detect_loss_threshold, 5); + init_rrx_sd_on <= int2bin(signal_detect_hysteresis_valid_threshold, 4); + + -- RX PMA Control Register 4 + init_rdefact <= (mux_select((deserialization_factor = 8), "0100", "0101")); + + -- RX PMA Control Register 7 + init_rrisedge <= (mux_select((pd_rising_edge_only = ("true")), '1', '0')); + init_rcntfact <= int2bin(pd1_counter_setting, 3); + init_rcntfact2 <= int2bin(pd2_counter_setting, 3); + init_ropt1 <= (mux_select((enable_pd_counter_accumulate_mode = ("true")), '1', '0')); + init_ricdrclkout <= (mux_select((send_reverse_serial_loopback_recovered_clk = ("true")), '1', mux_select((send_reverse_serial_loopback_data = ("true")), '0', 'X'))); + init_bypass_local_div <= (mux_select((enable_local_divider = ("true")), '0', '1')); + + -- RX PMA Control Register 8 + init_rloopback2 <= (mux_select((allow_serial_loopback = ("true")), '1', '0')); + init_rloopback3 <= (mux_select((send_reverse_serial_loopback_data = ("true") OR send_reverse_serial_loopback_recovered_clk = ("true")), '1', '0')); + + -- RX PMA Control Register 9 + init_rshiften <= (mux_select((enable_dpa_shift = ("true")), '1', '0')); + init_radd <= int2bin(phase_step_add_setting, 2); + init_rsub <= int2bin(phase_step_sub_setting, 2); + init_rphenable <= mux_select((enable_initial_phase_selection = ("true")), '1', '0'); + init_rprst <= int2bin(initial_phase_value, 6); + + -- RX PMA Control Register 10 + init_rppmsel <= int2bin(ppmselect, 6); + + init_rpmadwidth_rx <= (mux_select((deserialization_factor = 8), '0', '1')); + + -- RX PMA control register 12 + init_reqv_set <= (mux_select((eq_setting = 1), "001", mux_select((eq_setting = 5), "001", mux_select((eq_setting = 4), "000", mux_select((eq_setting = 7), "001", "000"))))); + init_reqb_set <= (mux_select((eq_setting = 1), "000", mux_select((eq_setting = 5), "000", mux_select((eq_setting = 4), "000", mux_select((eq_setting = 7), "001", "000"))))); + init_reqa_set <= (mux_select((eq_setting = 1), "000", mux_select((eq_setting = 5), "001", mux_select((eq_setting = 4), "001", mux_select((eq_setting = 7), "001", "000"))))); + WAIT; + END PROCESS; + + -- enable_dpa_shift is turned on + -- for shifting 0.25 UI of deserclock if enable_dpa_shift==true + PROCESS (dpashift) + BEGIN + IF (cram_rshiften = '1') THEN + IF (dpashift'EVENT AND dpashift = '1') THEN + dpashift_on <= NOT dpashift_on; + END IF; + END IF; + END PROCESS; + + --prevent x/z propagate to gate netlist + datain_in <= datain WHEN (datain = '1' OR datain = '0') ELSE '0'; + + clr <= '1' WHEN ((rxpmareset = '1') OR (crupowerdn = '1')) ELSE + '0'; + rxdatain <= '0' WHEN (clr = '1') ELSE + seriallpbkin WHEN (cram_rloopback2 = '1') ELSE + datain_in; + + -- Divide the deserializer fast clock if local divider is turned on + PROCESS (deserclock) + BEGIN + IF (deserclock'EVENT AND deserclock= '1') THEN + deserclock_div_2 <= NOT (deserclock_div_2); + END IF; + + END PROCESS; + + deserclock_local_div <= deserclock_div_2 WHEN (cram_bypass_local_div = '0') ELSE deserclock; + + -- Deserializer & dpashift operation + PROCESS (deserclock_local_div) + BEGIN + -- dpashift operation + -- calculating period + deserclock_period <= NOW - prev_posedge; + deserclock_delay <= deserclock_period / 4; + prev_posedge <= NOW; + + IF (dpashift_on = '1' AND dpashift = '0') THEN + deserclock_dly <= TRANSPORT deserclock_local_div AFTER deserclock_delay; + ELSE + deserclock_dly <= deserclock_local_div; + END IF; + END PROCESS; + + -- Deserializer + PROCESS (deserclock_dly) + BEGIN + -- sample deven & dodd + IF (deserclock_dly'EVENT AND deserclock_dly = '1') THEN + deven_prev <= rxdatain; + IF (first_edge = '1') THEN + deven <= '0'; + dodd <= '0'; + first_edge <= '0'; + ELSE + deven <= deven_prev; + dodd <= dodd_prev; + END IF; + + ELSIF (deserclock_dly'EVENT AND deserclock_dly = '0') THEN + dodd_prev <= rxdatain; + END IF; + END PROCESS; + + rx_pma_deser : cycloneiv_hssi_rx_pma_sub_deser + GENERIC MAP ( + channel_width => deserialization_factor + ) + PORT MAP ( + fclk => deserclock_dly, + deven => deven, + dodd => dodd, + loaden => loaden, + clr => clr, + rxdat => rxdata + ); + + recoverdataout <= rxdata; + + -- CLKDIVRX + rx_pma_clkdiv : cycloneiv_hssi_rx_pma_sub_clkdiv + PORT MAP ( + rxfclk => deserclock_dly, + loaden => loaden, + deser_fact => cram_rdefact, + clr => clr, + clkdivrx => clkdivrx + ); + + clockout <= clkdivrx; + + -- Signal Detect + sd_rx <= seriallpbkin WHEN (cram_rloopback2 = '1') ELSE datain; + sd_reset <= '1' WHEN (powerdn = '1' OR rxpmareset = '1') ELSE + '0'; + PROCESS (sd_reset, sd_rx) + BEGIN + IF (sd_reset = '1') THEN + signaldetect_reg <= '0'; + ELSIF (sd_rx = '0' OR sd_rx = '1') THEN + signaldetect_reg <= '1'; + ELSE + signaldetect_reg <= '0'; + END IF; + END PROCESS; + + signaldetect <= signaldetect_reg; + + -- Lock to Ref Out + -- simplified freqlock behavior: + -- (1). Responding to rising edge of rxpll_lock with small counter; + -- (2). Responding to analogreset + -- (3). Not responding to loss of rxpll_lock + + signal_detect_reg_n <= NOT(signaldetect_reg); + + PROCESS (ppmdetectrefclk, rxpmareset) + BEGIN + IF (rxpmareset = '1') THEN + mfreqlocked_reg <= '0'; + ELSIF (ppmdetectrefclk'EVENT AND ppmdetectrefclk = '1') THEN + IF (mfreqlocked_cnt = "1111") THEN + mfreqlocked_reg <= '1'; + ELSE + mfreqlocked_reg <= '0'; + END IF; + END IF; + END PROCESS; + + PROCESS (ppmdetectrefclk, signal_detect_reg_n) + BEGIN + IF (signal_detect_reg_n = '1') THEN + mfreqlocked_cnt <= "0000"; + ELSIF (ppmdetectrefclk'EVENT AND ppmdetectrefclk = '1') THEN + IF (mfreqlocked_cnt /= "1111") THEN + mfreqlocked_cnt <= mfreqlocked_cnt + "0001"; + END IF; + END IF; + END PROCESS; + + sd_cdr <= cram_rrx_sd_force OR cram_rloopback2 OR signaldetect_reg; + + locktorefout <= '0' WHEN (clr = '1') ELSE + '1' WHEN (locktodata = '1') ELSE + '0' WHEN (locktoref = '1') ELSE + '0' WHEN (sd_cdr = '0') ELSE + '1' WHEN (sd_cdr = '1' AND mfreqlocked_reg = '1' AND locktoref = '0') ELSE + '0'; + + -- Loopback + rlpbk_data <= '1' WHEN (cram_rloopback3 = '1' AND cram_ricdrclkout = '0') ELSE '0'; + rlpbk_clk <= '1' WHEN (cram_rloopback3 = '1' AND cram_ricdrclkout = '1') ELSE '0'; + + diagnosticlpbkout <= datain_in; + reverselpbkout <= deserclock_dly WHEN (rlpbk_clk = '1') ELSE + rxdatain WHEN (rlpbk_data = '1') ELSE + '0'; + + -- drive 0 on analogtestbus + analogtestbus <= "00000000"; + + -- freqlocked + locktorefout_freqlock <= '0' WHEN (clr = '1') ELSE + '0' WHEN (sd_cdr = '0') ELSE + '1' WHEN (sd_cdr = '1' AND mfreqlocked_reg = '1') ELSE + '0'; + + freqlocked <= '1' WHEN (locktorefout_freqlock = '1') ELSE + '0'; + + -- datastrobeout + datastrobeout <= '0'; + +END trans; + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_pcs_reset IS + PORT ( + + hard_reset : IN STD_LOGIC; + clk_2_b : IN STD_LOGIC; + refclk_b_in : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rxpcs_rst : IN STD_LOGIC; + txpcs_rst : IN STD_LOGIC; + + rxrst_int : OUT STD_LOGIC; + txrst_int : OUT STD_LOGIC + ); +END cycloneiv_hssi_pcs_reset; + +ARCHITECTURE trans OF cycloneiv_hssi_pcs_reset IS + + SIGNAL txrst_sync1 : STD_LOGIC := '0'; + SIGNAL txrst_sync2 : STD_LOGIC := '0'; + SIGNAL rxrst_sync1 : STD_LOGIC := '0'; + SIGNAL rxrst_sync2 : STD_LOGIC := '0'; +BEGIN + + PROCESS (hard_reset, clk_2_b) +VARIABLE txt : LINE; + BEGIN + IF (hard_reset = '1') THEN + rxrst_sync2 <= '1'; + rxrst_sync1 <= '1'; + ELSIF (clk_2_b'EVENT AND clk_2_b = '1') THEN + rxrst_sync2 <= TRANSPORT rxrst_sync1 AFTER 1* 1 ps; + rxrst_sync1 <= rxpcs_rst; + END IF; + END PROCESS; + + PROCESS (hard_reset, refclk_b_in) +VARIABLE txt : LINE; + BEGIN + IF (hard_reset = '1') THEN + txrst_sync2 <= '1'; + txrst_sync1 <= '1'; + ELSIF (refclk_b_in'EVENT AND refclk_b_in = '1') THEN + txrst_sync2 <= TRANSPORT txrst_sync1 AFTER 1* 1 ps; + txrst_sync1 <= txpcs_rst; + END IF; + END PROCESS; + + -- 06-14-02 BT Changed SCAN_SHIFT signal to SCAN_MODE + --assign rxrst_int = !SCAN_SHIFT & rxrst_sync2; + --assign txrst_int = !SCAN_SHIFT & txrst_sync2; + rxrst_int <= NOT(scan_mode) AND rxrst_sync2; + txrst_int <= NOT(scan_mode) AND txrst_sync2; + +END trans; + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_digi_chnl_hip_spt IS + PORT ( + + rhip_ena : IN STD_LOGIC; + + pcs_rxd_ch : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + pcs_rxvalid : IN STD_LOGIC; + pcs_rxelecidle : IN STD_LOGIC; + pcs_rxstatus_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_phystatus : IN STD_LOGIC; + txpma_local_clk : IN STD_LOGIC; + txd_ch : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + hip_txd_ch : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + txdetectrxloopback : IN STD_LOGIC; + hip_txdetectrxloopback : IN STD_LOGIC; + rxpolarity : IN STD_LOGIC; + hip_rxpolarity : IN STD_LOGIC; + powerdown_ch : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + hip_powerdown_ch : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txdeemph : IN STD_LOGIC; + hip_txdeemph : IN STD_LOGIC; + txmargin_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_txmargin_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidleinfersel_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_eidleinfersel_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rate : IN STD_LOGIC; + hip_rate : IN STD_LOGIC; + hip_txelecidle : IN STD_LOGIC; + + rxd_ch : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + hip_rxd_ch : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + rxvalid : OUT STD_LOGIC; + hip_rxvalid : OUT STD_LOGIC; + rxelecidle : OUT STD_LOGIC; + hip_rxelecidle : OUT STD_LOGIC; + rxstatus_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_rxstatus_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + phystatus : OUT STD_LOGIC; + hip_phystatus : OUT STD_LOGIC; + hip_tx_clk : OUT STD_LOGIC; + pcs_txd_ch : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); + pcs_txdetectrxloopback : OUT STD_LOGIC; + pcs_rxpolarity : OUT STD_LOGIC; + pcs_powerdown_ch : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pcs_txdeemph : OUT STD_LOGIC; + pcs_txmargin_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_eidleinfersel_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_rate : OUT STD_LOGIC + ); +END cycloneiv_hssi_digi_chnl_hip_spt; + +ARCHITECTURE trans OF cycloneiv_hssi_digi_chnl_hip_spt IS +BEGIN + + --// SECTION for SPLIT signals + --// =============================== + --// + -- MUX/SPLIT #5,6,7,8 in Excel spreadsheet + rxd_ch <= pcs_rxd_ch; + hip_rxd_ch <= pcs_rxd_ch WHEN (rhip_ena = '1') ELSE + "000000000"; + + -- MUX/SPLIT #16 in Excel spreadsheet + rxvalid <= pcs_rxvalid; + hip_rxvalid <= pcs_rxvalid WHEN (rhip_ena = '1') ELSE + '0'; + + -- MUX/SPLIT #17 in Excel spreadsheet + rxelecidle <= pcs_rxelecidle; + hip_rxelecidle <= pcs_rxelecidle WHEN (rhip_ena = '1') ELSE + '1'; + + -- MUX/SPLIT #18,19,20,21 in Excel spreadsheet + rxstatus_ch <= pcs_rxstatus_ch; + hip_rxstatus_ch <= pcs_rxstatus_ch WHEN (rhip_ena = '1') ELSE + "000"; + + -- MUX/SPLIT #22 in Excel spreadsheet + phystatus <= pcs_phystatus; + hip_phystatus <= pcs_phystatus WHEN (rhip_ena = '1') ELSE + '0'; + + hip_tx_clk <= txpma_local_clk; + + --// SECTION for MUX signals + --// =============================== + --// + -- MUX/SPLIT #1,2,3,4 in Excel spreadsheet + pcs_txd_ch <= (hip_txelecidle & hip_txd_ch) WHEN (rhip_ena = '1') ELSE + txd_ch; + + -- MUX/SPLIT #10 in Excel spreadsheet + pcs_txdetectrxloopback <= hip_txdetectrxloopback WHEN (rhip_ena = '1') ELSE + txdetectrxloopback; + + -- MUX/SPLIT #11 in Excel spreadsheet + pcs_rxpolarity <= hip_rxpolarity WHEN (rhip_ena = '1') ELSE + rxpolarity; + + -- MUX/SPLIT #12,13,14,15 in Excel spreadsheet + pcs_powerdown_ch <= hip_powerdown_ch WHEN (rhip_ena = '1') ELSE + powerdown_ch; + + -- MUX/SPLIT #23 in Excel spreadsheet + pcs_txdeemph <= hip_txdeemph WHEN (rhip_ena = '1') ELSE + txdeemph; + + -- MUX/SPLIT #24,25,26,27 in Excel spreadsheet + pcs_txmargin_ch <= hip_txmargin_ch WHEN (rhip_ena = '1') ELSE + txmargin_ch; + + -- MUX/SPLIT #28,29,30,31 in Excel spreadsheet + pcs_eidleinfersel_ch <= hip_eidleinfersel_ch WHEN (rhip_ena = '1') ELSE + eidleinfersel_ch; + + -- MUX/SPLIT #32 in Excel spreadsheet + pcs_rate <= hip_rate WHEN (rhip_ena = '1') ELSE + rate; + +END trans; + + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_phystatus_generator_fsm IS + PORT ( + + -- General signals + + --CRAM + -- OR of rtx_pipe_enable and rrx_pipe_enable + -- no toggle (gen 2) = 0, toggle (option for gen 1) = 1 + + -- PLD Interface + -- power state control + -- communicate completion of power state transitions, receiver + -- detection, rate change + + -- Auto Negotiation Module + -- asserted when signaling rate change between Gen 1 and Gen 2 + + -- RX PIPE Interface + -- p1_sync, + + -- PMA interface + -- TX PMA + -- rx_detect_bypass = 0 : Validation of rx_found: + -- synchronized at pipe_interface_top level + -- rx_detect_bypass = 1 : delayed version of txdetectrx + + -- RX PMA + -- asserted when successful power state transition occurs + -- validates power_state_transition_done, currently tied to 0 + + -- Latched Power State Signals + -- P1 power state from TX PIPE interface + + -- Internal Power State Done Generator + -- faked successful power state transition generated by internal + -- power state transition done module + + --******************************************************************************** + -- INCLUDE STATEMENTS + --******************************************************************************** + + --******************************************************************************** + -- I/O SIGNALS + --******************************************************************************** + -- General signals + clk : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + + -- CRAM + phystat_ena : IN STD_LOGIC; + rphystatus_rst_toggle : IN STD_LOGIC; + + -- PLD Interface + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + phystatus : OUT STD_LOGIC; + + rindv_rx : IN STD_LOGIC; -- Select between XAUI mode or indiv channel mode + rmaster_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rmaster_up_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + + -- Auto Negotiation Module + speed_change : IN STD_LOGIC; + speed_change_centrl : IN STD_LOGIC; + speed_change_quad_up : IN STD_LOGIC; + speed_change_quad_down : IN STD_LOGIC; + + -- RX PIPE Interface + --output p1_sync; + + -- PMA interface + -- TX PMA + rx_detect_valid : IN STD_LOGIC; + + -- RX PMA + power_state_transition_done : IN STD_LOGIC; + power_state_transition_done_ena : IN STD_LOGIC; + + -- Latched Power state signals + p1 : IN STD_LOGIC; -- longer recovery time (64 us max) latency + + -- Internal Power State Done Generator + internal_done : IN STD_LOGIC + ); +END cycloneiv_hssi_phystatus_generator_fsm; + +ARCHITECTURE trans OF cycloneiv_hssi_phystatus_generator_fsm IS + + --******************************************************************************** + -- PARAMETERS + --******************************************************************************** + + --******************************************************************************** + -- DECLARATIONS + --******************************************************************************** + --reg phystatus; + + -- select between PMA done and internally generated done + SIGNAL done : STD_LOGIC; + SIGNAL pre_power_state_transition_done_sync : STD_LOGIC; + SIGNAL power_state_transition_done_sync : STD_LOGIC; + SIGNAL power_state_transition_done_sync_reg : STD_LOGIC; + + -- Reset condition + SIGNAL reset_phystatus : STD_LOGIC; + + -- State transition + SIGNAL state_transition_phystatus : STD_LOGIC; + + -- Speed Negotiation + SIGNAL speed_change_reg : STD_LOGIC; + SIGNAL speed_change_sync : STD_LOGIC; + SIGNAL speed_change_sync_reg : STD_LOGIC; + SIGNAL speed_change_phystatus : STD_LOGIC; + + -- Receiver Detection + --reg p1_reg; // synchronize from tx clk domain to rx clk domain + --reg p1_sync; + + SIGNAL rx_detect_valid_reg : STD_LOGIC; -- Edge detection of receiver detection status signal + SIGNAL rx_detect_valid_phystatus : STD_LOGIC; + + -- P2 exit detection + SIGNAL decode_p2 : STD_LOGIC; + SIGNAL decode_p2_reg : STD_LOGIC; + SIGNAL decode_p2_reg1 : STD_LOGIC; + SIGNAL phystatus_high_sel : STD_LOGIC; + SIGNAL phystatus_high_sel_reg : STD_LOGIC; + + -- Reset + SIGNAL phystatus_toggle_sel : STD_LOGIC; + SIGNAL phystatus_toggle_sel_reg : STD_LOGIC; + + SIGNAL pre_phystatus : STD_LOGIC; + + SIGNAL speed_change_local : STD_LOGIC; + + SIGNAL speed_change_centrl_del1 : STD_LOGIC; + SIGNAL speed_change_centrl_del2 : STD_LOGIC; +BEGIN + + --******************************************************************************** + -- ASSIGN STATEMENTS + --******************************************************************************** + -- Move to PLD interface + phystatus <= '1' WHEN ((NOT(decode_p2) AND decode_p2_reg1) = '1') ELSE + pre_phystatus; + --assign phystatus= pre_phystatus; + + done <= (power_state_transition_done_sync AND NOT(power_state_transition_done_sync_reg)) WHEN (power_state_transition_done_ena = '1') ELSE + internal_done; + + decode_p2 <= phystat_ena WHEN (powerdown = "11") ELSE + '0'; + + --******************************************************************************** + -- SUBMODULE INSTANTIATIONS + --******************************************************************************** + + --******************************************************************************** + -- MAIN CODE + --******************************************************************************** + -- Reset phystatus generation + + -- Phystatus is asserted during reset and then the successful 'transition' into P1 is signal by the assertion + -- phystatus for 1 cycle. Unlike regular operation, the first entry into P1 is not indicated by a 'done' signal + -- The assertion of phystatus occurs 4 cycles after reset is released + PROCESS (reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + reset_phystatus <= '1'; + ELSE + reset_phystatus <= '0'; + END IF; + END PROCESS; + + PROCESS (reset_n, rphystatus_rst_toggle, done, phystatus_toggle_sel_reg) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + phystatus_toggle_sel <= '1'; + ELSIF ((rphystatus_rst_toggle OR done) = '1') THEN + phystatus_toggle_sel <= '0'; + ELSE + phystatus_toggle_sel <= phystatus_toggle_sel_reg; + END IF; + END PROCESS; + + PROCESS (clk, reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + phystatus_toggle_sel_reg <= TRANSPORT '1' AFTER 1* 1 ps; + phystatus_high_sel_reg <= TRANSPORT '1' AFTER 1* 1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + phystatus_toggle_sel_reg <= TRANSPORT phystatus_toggle_sel AFTER 1* 1 ps; + phystatus_high_sel_reg <= TRANSPORT phystatus_high_sel AFTER 1* 1 ps; + END IF; + END PROCESS; + -- State transition: sync PMA signal to local clk. Currently not being used + -- State transition: Internal done generator indicates that there was a successful state transition. + -- Illegal transitions have been taken into account by the previous module. + PROCESS (clk, reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + pre_power_state_transition_done_sync <= TRANSPORT '0' AFTER 1* 1 ps; + power_state_transition_done_sync <= TRANSPORT '0' AFTER 1* 1 ps; + + power_state_transition_done_sync_reg <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + pre_power_state_transition_done_sync <= TRANSPORT power_state_transition_done AFTER 1* 1 ps; + power_state_transition_done_sync <= TRANSPORT pre_power_state_transition_done_sync AFTER 1* 1 ps; + + power_state_transition_done_sync_reg <= TRANSPORT power_state_transition_done_sync AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (reset_n, done) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + state_transition_phystatus <= '0'; + ELSIF (done = '1') THEN + state_transition_phystatus <= '1'; + ELSE + state_transition_phystatus <= '0'; + END IF; + END PROCESS; + + PROCESS (clk, reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + speed_change_centrl_del1 <= TRANSPORT '0' AFTER 1* 1 ps; + + speed_change_centrl_del2 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + speed_change_centrl_del1 <= TRANSPORT speed_change_centrl AFTER 1* 1 ps; + speed_change_centrl_del2 <= TRANSPORT speed_change_centrl_del1 AFTER 1* 1 ps; + END IF; + END PROCESS; + -- always @ (posedge clk or negedge reset_n) + + speed_change_local <= speed_change WHEN (rindv_rx = '1') ELSE + speed_change_centrl_del2 WHEN (rmaster_rx = '1') ELSE + speed_change_quad_up WHEN (rmaster_up_rx = '1') ELSE + speed_change_quad_down; + + -- Speed Negotiation + PROCESS (clk, reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + speed_change_reg <= TRANSPORT '0' AFTER 1* 1 ps; + speed_change_sync <= TRANSPORT '0' AFTER 1* 1 ps; + + speed_change_sync_reg <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + speed_change_reg <= TRANSPORT speed_change_local AFTER 1* 1 ps; + speed_change_sync <= TRANSPORT speed_change_reg AFTER 1* 1 ps; + speed_change_sync_reg <= TRANSPORT speed_change_sync AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (reset_n, speed_change_sync, speed_change_sync_reg) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + speed_change_phystatus <= '0'; + ELSIF ((NOT(speed_change_sync) AND speed_change_sync_reg) = '1') THEN + speed_change_phystatus <= '1'; + ELSE + speed_change_phystatus <= '0'; + END IF; + END PROCESS; + + -- Receiver Detection + PROCESS (clk, reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + -- p1_reg <= 1'b0; + -- p1_sync <= 1'b0; + + -- rx_detect_valid_phystatus <= 1'b0; + rx_detect_valid_reg <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + -- p1_reg <= p1; + -- p1_sync <= p1_reg; + + -- rx_detect_valid_phystatus <= p1_sync && rx_detect_valid && !rx_detect_valid_reg; + rx_detect_valid_reg <= TRANSPORT rx_detect_valid AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (reset_n, p1, rx_detect_valid, rx_detect_valid_reg) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + -- else if (p1_sync && rx_detect_valid && !rx_detect_valid_reg) + rx_detect_valid_phystatus <= '0'; + ELSIF ((p1 AND rx_detect_valid AND NOT(rx_detect_valid_reg)) = '1') THEN + rx_detect_valid_phystatus <= '1'; + ELSE + + rx_detect_valid_phystatus <= '0'; + END IF; + END PROCESS; + + -- P2 state exit Detection + PROCESS (clk, reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + decode_p2_reg <= TRANSPORT '0' AFTER 1* 1 ps; + decode_p2_reg1 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + decode_p2_reg <= TRANSPORT decode_p2 AFTER 1* 1 ps; + decode_p2_reg1 <= TRANSPORT decode_p2_reg AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (reset_n, decode_p2, decode_p2_reg, phystatus_high_sel_reg, done) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + phystatus_high_sel <= '0'; + ELSIF ((NOT(decode_p2) AND decode_p2_reg) = '1') THEN + phystatus_high_sel <= '1'; + ELSIF (done = '1') THEN + phystatus_high_sel <= '0'; + ELSE + phystatus_high_sel <= phystatus_high_sel_reg; + END IF; + END PROCESS; + + PROCESS (reset_n, phystatus_high_sel, reset_phystatus, state_transition_phystatus, rx_detect_valid_phystatus, phystatus_toggle_sel, speed_change_phystatus) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(reset_n)) = '1') THEN + pre_phystatus <= '1'; + ELSE + IF ((phystatus_high_sel OR reset_phystatus OR state_transition_phystatus OR rx_detect_valid_phystatus OR phystatus_toggle_sel OR speed_change_phystatus) = '1') THEN + pre_phystatus <= '1'; + ELSE + pre_phystatus <= '0'; + END IF; + END IF; + END PROCESS; + +END trans; + + +-- always @ (reset_n or phystatus_high_sel or reset_phystatus or state_transition_phystatus or rx_detect_valid_phystatus... + +-- phystatus_generator_fsm--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 53 oper_mux 1 cycloneiv_hssi_phystatus_generator_fsm 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_phystatus_generator IS + PORT + ( + clk : IN STD_LOGIC; + latched_p0 : IN STD_LOGIC; + latched_p0s : IN STD_LOGIC; + latched_p1 : IN STD_LOGIC; + latched_p2 : IN STD_LOGIC; + phystat_ena : IN STD_LOGIC; + phystatus : OUT STD_LOGIC; + power_state_transition_done : IN STD_LOGIC; + power_state_transition_done_ena : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + reset_n : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rphystatus_delay : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rphystatus_rst_toggle : IN STD_LOGIC; + rx_detect_valid : IN STD_LOGIC; + speed_change : IN STD_LOGIC; + speed_change_centrl : IN STD_LOGIC; + speed_change_quad_down : IN STD_LOGIC; + speed_change_quad_up : IN STD_LOGIC + ); + END cycloneiv_hssi_phystatus_generator; + + ARCHITECTURE RTL OF cycloneiv_hssi_phystatus_generator IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nllOi21 : STD_LOGIC := '0'; + SIGNAL nllOi22 : STD_LOGIC := '0'; + SIGNAL wire_nllOi22_w_lg_w_lg_q82w83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllOi22_w_lg_q82w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nllOl19 : STD_LOGIC := '0'; + SIGNAL nllOl20 : STD_LOGIC := '0'; + SIGNAL wire_nllOl20_w_lg_w_lg_q79w80w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllOl20_w_lg_q79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nllOO17 : STD_LOGIC := '0'; + SIGNAL nllOO18 : STD_LOGIC := '0'; + SIGNAL wire_nllOO18_w_lg_w_lg_q72w73w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllOO18_w_lg_q72w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO0l11 : STD_LOGIC := '0'; + SIGNAL nlO0l12 : STD_LOGIC := '0'; + SIGNAL nlO1i15 : STD_LOGIC := '0'; + SIGNAL nlO1i16 : STD_LOGIC := '0'; + SIGNAL nlO1O13 : STD_LOGIC := '0'; + SIGNAL nlO1O14 : STD_LOGIC := '0'; + SIGNAL nlOii10 : STD_LOGIC := '0'; + SIGNAL nlOii9 : STD_LOGIC := '0'; + SIGNAL nlOil7 : STD_LOGIC := '0'; + SIGNAL nlOil8 : STD_LOGIC := '0'; + SIGNAL nlOli5 : STD_LOGIC := '0'; + SIGNAL nlOli6 : STD_LOGIC := '0'; + SIGNAL nlOlO3 : STD_LOGIC := '0'; + SIGNAL nlOlO4 : STD_LOGIC := '0'; + SIGNAL nlOOl1 : STD_LOGIC := '0'; + SIGNAL nlOOl2 : STD_LOGIC := '0'; + SIGNAL ni0i : STD_LOGIC := '0'; + SIGNAL ni0l : STD_LOGIC := '0'; + SIGNAL ni1O : STD_LOGIC := '0'; + SIGNAL niii : STD_LOGIC := '0'; + SIGNAL wire_ni0O_CLRN : STD_LOGIC; + SIGNAL n00i : STD_LOGIC := '0'; + SIGNAL n00l : STD_LOGIC := '0'; + SIGNAL n00O : STD_LOGIC := '0'; + SIGNAL n01i : STD_LOGIC := '0'; + SIGNAL n01l : STD_LOGIC := '0'; + SIGNAL n01O : STD_LOGIC := '0'; + SIGNAL n0ii : STD_LOGIC := '0'; + SIGNAL n0il : STD_LOGIC := '0'; + SIGNAL n0iO : STD_LOGIC := '0'; + SIGNAL n0li : STD_LOGIC := '0'; + SIGNAL n0ll : STD_LOGIC := '0'; + SIGNAL n0lO : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL n1lO : STD_LOGIC := '0'; + SIGNAL n1Ol : STD_LOGIC := '0'; + SIGNAL n1OO : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1l : STD_LOGIC := '0'; + SIGNAL niil : STD_LOGIC := '0'; + SIGNAL niiO : STD_LOGIC := '0'; + SIGNAL nili : STD_LOGIC := '0'; + SIGNAL nill : STD_LOGIC := '0'; + SIGNAL nilO : STD_LOGIC := '0'; + SIGNAL niOi : STD_LOGIC := '0'; + SIGNAL niOl : STD_LOGIC := '0'; + SIGNAL nl1i : STD_LOGIC := '0'; + SIGNAL wire_niOO_CLRN : STD_LOGIC; + SIGNAL wire_niOO_PRN : STD_LOGIC; + SIGNAL wire_niOO_w_lg_w_lg_w_lg_w_lg_nill7w9w11w12w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_w_lg_w_lg_nill7w9w11w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_w_lg_w_lg_nill7w9w16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_w_lg_nill7w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_w_lg_nill7w24w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_nill32w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_niil17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_niiO10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_nili8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_w_lg_nill7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oi_o : STD_LOGIC; + SIGNAL wire_n1Oi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0O_phystatus : STD_LOGIC; + SIGNAL wire_nl0O_powerdown : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_w_lg_power_state_transition_done_ena60w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO0O : STD_LOGIC; + SIGNAL nlOiO : STD_LOGIC; + COMPONENT cycloneiv_hssi_phystatus_generator_fsm + PORT + ( + clk : IN STD_LOGIC; + internal_done : IN STD_LOGIC; + p1 : IN STD_LOGIC; + phystat_ena : IN STD_LOGIC; + phystatus : OUT STD_LOGIC; + power_state_transition_done : IN STD_LOGIC; + power_state_transition_done_ena : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + reset_n : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rphystatus_rst_toggle : IN STD_LOGIC; + rx_detect_valid : IN STD_LOGIC; + speed_change : IN STD_LOGIC; + speed_change_centrl : IN STD_LOGIC; + speed_change_quad_down : IN STD_LOGIC; + speed_change_quad_up : IN STD_LOGIC + ); + END COMPONENT; + BEGIN + + wire_w_lg_power_state_transition_done_ena60w(0) <= NOT power_state_transition_done_ena; + nlO0O <= '1'; + nlOiO <= ((((((wire_niOO_w_lg_w_lg_w_lg_w_lg_nill7w9w11w12w(0) AND (nlOOl2 XOR nlOOl1)) OR (wire_niOO_w_lg_w_lg_w_lg_nill7w9w16w(0) AND wire_niOO_w_lg_niil17w(0))) OR (NOT (nlOlO4 XOR nlOlO3))) OR ((wire_niOO_w_lg_w_lg_nill7w24w(0) AND wire_niOO_w_lg_niiO10w(0)) AND wire_niOO_w_lg_niil17w(0))) OR (NOT (nlOli6 XOR nlOli5))) OR ((wire_niOO_w_lg_nill32w(0) AND wire_niOO_w_lg_niiO10w(0)) AND wire_niOO_w_lg_niil17w(0))); + phystatus <= wire_nl0O_phystatus; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nllOi21 <= nllOi22; + END IF; + if (now = 0 ns) then + nllOi21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nllOi22 <= nllOi21; + END IF; + END PROCESS; + wire_nllOi22_w_lg_w_lg_q82w83w(0) <= wire_nllOi22_w_lg_q82w(0) AND n1OO; + wire_nllOi22_w_lg_q82w(0) <= nllOi22 XOR nllOi21; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nllOl19 <= nllOl20; + END IF; + if (now = 0 ns) then + nllOl19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nllOl20 <= nllOl19; + END IF; + END PROCESS; + wire_nllOl20_w_lg_w_lg_q79w80w(0) <= wire_nllOl20_w_lg_q79w(0) AND n01i; + wire_nllOl20_w_lg_q79w(0) <= nllOl20 XOR nllOl19; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nllOO17 <= nllOO18; + END IF; + if (now = 0 ns) then + nllOO17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nllOO18 <= nllOO17; + END IF; + END PROCESS; + wire_nllOO18_w_lg_w_lg_q72w73w(0) <= wire_nllOO18_w_lg_q72w(0) AND n00l; + wire_nllOO18_w_lg_q72w(0) <= nllOO18 XOR nllOO17; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0l11 <= nlO0l12; + END IF; + if (now = 0 ns) then + nlO0l11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0l12 <= nlO0l11; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO1i15 <= nlO1i16; + END IF; + if (now = 0 ns) then + nlO1i15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO1i16 <= nlO1i15; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO1O13 <= nlO1O14; + END IF; + if (now = 0 ns) then + nlO1O13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO1O14 <= nlO1O13; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOii10 <= nlOii9; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOii9 <= nlOii10; + END IF; + if (now = 0 ns) then + nlOii9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOil7 <= nlOil8; + END IF; + if (now = 0 ns) then + nlOil7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOil8 <= nlOil7; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOli5 <= nlOli6; + END IF; + if (now = 0 ns) then + nlOli5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOli6 <= nlOli5; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlO3 <= nlOlO4; + END IF; + if (now = 0 ns) then + nlOlO3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlO4 <= nlOlO3; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOOl1 <= nlOOl2; + END IF; + if (now = 0 ns) then + nlOOl1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOOl2 <= nlOOl1; + END IF; + END PROCESS; + PROCESS (clk, wire_ni0O_CLRN) + BEGIN + IF (wire_ni0O_CLRN = '0') THEN + ni0i <= '0'; + ni0l <= '0'; + ni1O <= '0'; + niii <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + IF (nlOiO = '1') THEN + ni0i <= niiO; + ni0l <= nili; + ni1O <= niil; + niii <= nill; + END IF; + END IF; + END PROCESS; + wire_ni0O_CLRN <= ((nlO0l12 XOR nlO0l11) AND reset_n); + PROCESS (clk, wire_niOO_PRN, wire_niOO_CLRN) + BEGIN + IF (wire_niOO_PRN = '0') THEN + n00i <= '1'; + n00l <= '1'; + n00O <= '1'; + n01i <= '1'; + n01l <= '1'; + n01O <= '1'; + n0ii <= '1'; + n0il <= '1'; + n0iO <= '1'; + n0li <= '1'; + n0ll <= '1'; + n0lO <= '1'; + n0Ol <= '1'; + n0OO <= '1'; + n1lO <= '1'; + n1Ol <= '1'; + n1OO <= '1'; + ni1i <= '1'; + ni1l <= '1'; + niil <= '1'; + niiO <= '1'; + nili <= '1'; + nill <= '1'; + nilO <= '1'; + niOi <= '1'; + niOl <= '1'; + nl1i <= '1'; + ELSIF (wire_niOO_CLRN = '0') THEN + n00i <= '0'; + n00l <= '0'; + n00O <= '0'; + n01i <= '0'; + n01l <= '0'; + n01O <= '0'; + n0ii <= '0'; + n0il <= '0'; + n0iO <= '0'; + n0li <= '0'; + n0ll <= '0'; + n0lO <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + n1lO <= '0'; + n1Ol <= '0'; + n1OO <= '0'; + ni1i <= '0'; + ni1l <= '0'; + niil <= '0'; + niiO <= '0'; + nili <= '0'; + nill <= '0'; + nilO <= '0'; + niOi <= '0'; + niOl <= '0'; + nl1i <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + n00i <= n00l; + n00l <= n0ii; + n00O <= wire_n1Oi_o; + n01i <= n01l; + n01l <= n01O; + n01O <= n00i; + n0ii <= n0il; + n0il <= n0iO; + n0iO <= n0li; + n0li <= n0ll; + n0ll <= ((phystat_ena AND wire_w_lg_power_state_transition_done_ena60w(0)) AND n0lO); + n0lO <= (NOT (((((NOT ((ni1O XOR n0Ol) XOR (NOT (nlO1O14 XOR nlO1O13)))) AND (NOT (ni0i XOR n0OO))) AND (NOT (ni0l XOR ni1i))) AND (NOT (niii XOR ni1l))) AND (nlO1i16 XOR nlO1i15))); + n0Ol <= ni1O; + n0OO <= ni0i; + n1lO <= n1Ol; + n1Ol <= n1OO; + n1OO <= n01i; + ni1i <= ni0l; + ni1l <= niii; + niil <= nilO; + niiO <= niOi; + nili <= niOl; + nill <= nl1i; + nilO <= latched_p0; + niOi <= latched_p0s; + niOl <= latched_p1; + nl1i <= latched_p2; + END IF; + END PROCESS; + wire_niOO_CLRN <= ((nlOil8 XOR nlOil7) AND reset_n); + wire_niOO_PRN <= (nlOii10 XOR nlOii9); + wire_niOO_w_lg_w_lg_w_lg_w_lg_nill7w9w11w12w(0) <= wire_niOO_w_lg_w_lg_w_lg_nill7w9w11w(0) AND niil; + wire_niOO_w_lg_w_lg_w_lg_nill7w9w11w(0) <= wire_niOO_w_lg_w_lg_nill7w9w(0) AND wire_niOO_w_lg_niiO10w(0); + wire_niOO_w_lg_w_lg_w_lg_nill7w9w16w(0) <= wire_niOO_w_lg_w_lg_nill7w9w(0) AND niiO; + wire_niOO_w_lg_w_lg_nill7w9w(0) <= wire_niOO_w_lg_nill7w(0) AND wire_niOO_w_lg_nili8w(0); + wire_niOO_w_lg_w_lg_nill7w24w(0) <= wire_niOO_w_lg_nill7w(0) AND nili; + wire_niOO_w_lg_nill32w(0) <= nill AND wire_niOO_w_lg_nili8w(0); + wire_niOO_w_lg_niil17w(0) <= NOT niil; + wire_niOO_w_lg_niiO10w(0) <= NOT niiO; + wire_niOO_w_lg_nili8w(0) <= NOT nili; + wire_niOO_w_lg_nill7w(0) <= NOT nill; + wire_n1Oi_data <= ( n1lO & n1Ol & wire_nllOi22_w_lg_w_lg_q82w83w & wire_nllOl20_w_lg_w_lg_q79w80w & n01l & n01O & n00i & wire_nllOO18_w_lg_w_lg_q72w73w); + wire_n1Oi_sel <= ( rphystatus_delay(2 DOWNTO 0)); + n1Oi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1Oi_data, + o => wire_n1Oi_o, + sel => wire_n1Oi_sel + ); + wire_nl0O_powerdown <= ( powerdown(1 DOWNTO 0)); + nl0O : cycloneiv_hssi_phystatus_generator_fsm + PORT MAP ( + clk => clk, + internal_done => n00O, + p1 => latched_p1, + phystat_ena => phystat_ena, + phystatus => wire_nl0O_phystatus, + power_state_transition_done => power_state_transition_done, + power_state_transition_done_ena => power_state_transition_done_ena, + powerdown => wire_nl0O_powerdown, + reset_n => reset_n, + rindv_rx => rindv_rx, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + rphystatus_rst_toggle => rphystatus_rst_toggle, + rx_detect_valid => rx_detect_valid, + speed_change => speed_change, + speed_change_centrl => speed_change_centrl, + speed_change_quad_down => speed_change_quad_down, + speed_change_quad_up => speed_change_quad_up + ); + + END RTL; --cycloneiv_hssi_phystatus_generator +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + +--synthesis_resources = lut 50 mux21 146 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_pipe_interface IS + PORT + ( + clk : IN STD_LOGIC; + latched_p1 : IN STD_LOGIC; + polinv_rx : IN STD_LOGIC; + polinv_rx_int : OUT STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + rind_error_reporting : IN STD_LOGIC; + rrdwidth_rx : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rx_detect_valid : IN STD_LOGIC; + rx_detect_valid_sync : IN STD_LOGIC; + rx_found : IN STD_LOGIC; + rx_found_sync : IN STD_LOGIC; + rxd : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + rxd_ch : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rxelecidle : OUT STD_LOGIC; + rxelectricalidle : IN STD_LOGIC; + rxpolarity : IN STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + rxvalid : OUT STD_LOGIC; + sigdetni : IN STD_LOGIC; + txdetectrx : IN STD_LOGIC + ); + END cycloneiv_hssi_rx_pipe_interface; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_pipe_interface IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n110l7 : STD_LOGIC := '0'; + SIGNAL n110l8 : STD_LOGIC := '0'; + SIGNAL wire_n110l8_w_lg_q84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n111i11 : STD_LOGIC := '0'; + SIGNAL n111i12 : STD_LOGIC := '0'; + SIGNAL wire_n111i12_w_lg_q92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n111O10 : STD_LOGIC := '0'; + SIGNAL wire_n111O10_w_lg_q88w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n111O9 : STD_LOGIC := '0'; + SIGNAL n11ii5 : STD_LOGIC := '0'; + SIGNAL n11ii6 : STD_LOGIC := '0'; + SIGNAL wire_n11ii6_w_lg_q77w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n11iO3 : STD_LOGIC := '0'; + SIGNAL n11iO4 : STD_LOGIC := '0'; + SIGNAL n11Ol1 : STD_LOGIC := '0'; + SIGNAL n11Ol2 : STD_LOGIC := '0'; + SIGNAL nlO0ll41 : STD_LOGIC := '0'; + SIGNAL nlO0ll42 : STD_LOGIC := '0'; + SIGNAL nlO0Oi39 : STD_LOGIC := '0'; + SIGNAL nlO0Oi40 : STD_LOGIC := '0'; + SIGNAL nlO0OO37 : STD_LOGIC := '0'; + SIGNAL nlO0OO38 : STD_LOGIC := '0'; + SIGNAL nlOi0l35 : STD_LOGIC := '0'; + SIGNAL nlOi0l36 : STD_LOGIC := '0'; + SIGNAL nlOiil33 : STD_LOGIC := '0'; + SIGNAL nlOiil34 : STD_LOGIC := '0'; + SIGNAL nlOilO31 : STD_LOGIC := '0'; + SIGNAL nlOilO32 : STD_LOGIC := '0'; + SIGNAL nlOiOl29 : STD_LOGIC := '0'; + SIGNAL nlOiOl30 : STD_LOGIC := '0'; + SIGNAL nlOl1l27 : STD_LOGIC := '0'; + SIGNAL nlOl1l28 : STD_LOGIC := '0'; + SIGNAL nlOlii25 : STD_LOGIC := '0'; + SIGNAL nlOlii26 : STD_LOGIC := '0'; + SIGNAL nlOlli23 : STD_LOGIC := '0'; + SIGNAL nlOlli24 : STD_LOGIC := '0'; + SIGNAL nlOlOi21 : STD_LOGIC := '0'; + SIGNAL nlOlOi22 : STD_LOGIC := '0'; + SIGNAL nlOO0i17 : STD_LOGIC := '0'; + SIGNAL nlOO0i18 : STD_LOGIC := '0'; + SIGNAL nlOO1i19 : STD_LOGIC := '0'; + SIGNAL nlOO1i20 : STD_LOGIC := '0'; + SIGNAL nlOOiO15 : STD_LOGIC := '0'; + SIGNAL nlOOiO16 : STD_LOGIC := '0'; + SIGNAL nlOOOl13 : STD_LOGIC := '0'; + SIGNAL nlOOOl14 : STD_LOGIC := '0'; + SIGNAL n00ii : STD_LOGIC := '0'; + SIGNAL n0ill : STD_LOGIC := '0'; + SIGNAL n0iOi : STD_LOGIC := '0'; + SIGNAL n1l1l : STD_LOGIC := '0'; + SIGNAL n1O0i : STD_LOGIC := '0'; + SIGNAL n1O1O : STD_LOGIC := '0'; + SIGNAL wire_n0ilO_w_lg_w_lg_w_lg_n0iOi81w94w95w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ilO_w_lg_w_lg_w_lg_n1O0i73w79w80w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ilO_w_lg_w_lg_n0iOi81w94w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ilO_w_lg_w_lg_n1O0i73w79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ilO_w_lg_n0iOi81w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ilO_w_lg_n1O0i73w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOOO : STD_LOGIC := '0'; + SIGNAL nO : STD_LOGIC := '0'; + SIGNAL wire_nl_CLRN : STD_LOGIC; + SIGNAL wire_n000i_dataout : STD_LOGIC; + SIGNAL wire_n001i_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001O_dataout : STD_LOGIC; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n010i_dataout : STD_LOGIC; + SIGNAL wire_n010l_dataout : STD_LOGIC; + SIGNAL wire_n010O_dataout : STD_LOGIC; + SIGNAL wire_n011i_dataout : STD_LOGIC; + SIGNAL wire_n011l_dataout : STD_LOGIC; + SIGNAL wire_n011O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01lO_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n100O_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10ii_dataout : STD_LOGIC; + SIGNAL wire_n10il_dataout : STD_LOGIC; + SIGNAL wire_n10iO_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10li_dataout : STD_LOGIC; + SIGNAL wire_n10ll_dataout : STD_LOGIC; + SIGNAL wire_n10lO_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n10Oi_dataout : STD_LOGIC; + SIGNAL wire_n10Ol_dataout : STD_LOGIC; + SIGNAL wire_n10OO_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iii_dataout : STD_LOGIC; + SIGNAL wire_n1iil_dataout : STD_LOGIC; + SIGNAL wire_n1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1ili_dataout : STD_LOGIC; + SIGNAL wire_n1ill_dataout : STD_LOGIC; + SIGNAL wire_n1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1liO_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_w_lg_w_lg_rrdwidth_rx82w85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rx_detect_valid_sync90w93w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rx_detect_valid_sync75w78w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rx_found_sync86w89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlO0iO267w268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOl0l211w212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_latched_p174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOl0i226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOl0i220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOii110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rclkcmpinsertpad227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rclkcmpinsertpad221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rrdwidth_rx82w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_detect_valid_sync90w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_detect_valid_sync75w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_detect_valid_sync193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_detect_valid_sync259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_found_sync86w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxd_range52w279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxd_range20w235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlO00l272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlO0iO267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlO0li263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOili225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOl0l211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOliO197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rclkcmpinsertpad205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reset_n72w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rind_error_reporting109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rrdwidth_rx199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sigdetni66w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxd_range51w277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxd_range19w233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n11lO : STD_LOGIC; + SIGNAL nlO00i : STD_LOGIC; + SIGNAL nlO00l : STD_LOGIC; + SIGNAL nlO00O : STD_LOGIC; + SIGNAL nlO01i : STD_LOGIC; + SIGNAL nlO01l : STD_LOGIC; + SIGNAL nlO01O : STD_LOGIC; + SIGNAL nlO0ii : STD_LOGIC; + SIGNAL nlO0il : STD_LOGIC; + SIGNAL nlO0iO : STD_LOGIC; + SIGNAL nlO0li : STD_LOGIC; + SIGNAL nlOi0i : STD_LOGIC; + SIGNAL nlOi1l : STD_LOGIC; + SIGNAL nlOi1O : STD_LOGIC; + SIGNAL nlOiii : STD_LOGIC; + SIGNAL nlOili : STD_LOGIC; + SIGNAL nlOill : STD_LOGIC; + SIGNAL nlOl0i : STD_LOGIC; + SIGNAL nlOl0l : STD_LOGIC; + SIGNAL nlOl0O : STD_LOGIC; + SIGNAL nlOl1i : STD_LOGIC; + SIGNAL nlOliO : STD_LOGIC; + SIGNAL nlOllO : STD_LOGIC; + SIGNAL nlOlOO : STD_LOGIC; + SIGNAL nlOO0O : STD_LOGIC; + SIGNAL nlOO1O : STD_LOGIC; + SIGNAL nlOOii : STD_LOGIC; + SIGNAL nlOOil : STD_LOGIC; + SIGNAL nlOOll : STD_LOGIC; + SIGNAL nlOOlO : STD_LOGIC; + SIGNAL nlOOOi : STD_LOGIC; + SIGNAL wire_w_rxd_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rxd_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rxd_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rxd_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_w_lg_rrdwidth_rx82w85w(0) <= wire_w_lg_rrdwidth_rx82w(0) AND wire_n110l8_w_lg_q84w(0); + wire_w_lg_w_lg_rx_detect_valid_sync90w93w(0) <= wire_w_lg_rx_detect_valid_sync90w(0) AND wire_n111i12_w_lg_q92w(0); + wire_w_lg_w_lg_rx_detect_valid_sync75w78w(0) <= wire_w_lg_rx_detect_valid_sync75w(0) AND wire_n11ii6_w_lg_q77w(0); + wire_w_lg_w_lg_rx_found_sync86w89w(0) <= wire_w_lg_rx_found_sync86w(0) AND wire_n111O10_w_lg_q88w(0); + wire_w_lg_w_lg_nlO0iO267w268w(0) <= wire_w_lg_nlO0iO267w(0) AND nlO0il; + wire_w_lg_w_lg_nlOl0l211w212w(0) <= wire_w_lg_nlOl0l211w(0) AND nlOl0i; + wire_w_lg_latched_p174w(0) <= latched_p1 AND rx_found_sync; + wire_w_lg_nlOl0i226w(0) <= nlOl0i AND wire_w_lg_nlOili225w(0); + wire_w_lg_nlOl0i220w(0) <= nlOl0i AND nlOili; + wire_w_lg_nlOOii110w(0) <= nlOOii AND wire_w_lg_rind_error_reporting109w(0); + wire_w_lg_rclkcmpinsertpad227w(0) <= rclkcmpinsertpad AND wire_w_lg_nlOl0i226w(0); + wire_w_lg_rclkcmpinsertpad221w(0) <= rclkcmpinsertpad AND wire_w_lg_nlOl0i220w(0); + wire_w_lg_rrdwidth_rx82w(0) <= rrdwidth_rx AND latched_p1; + wire_w_lg_rx_detect_valid_sync90w(0) <= rx_detect_valid_sync AND wire_w_lg_w_lg_rx_found_sync86w89w(0); + wire_w_lg_rx_detect_valid_sync75w(0) <= rx_detect_valid_sync AND wire_w_lg_latched_p174w(0); + wire_w_lg_rx_detect_valid_sync193w(0) <= rx_detect_valid_sync AND wire_n0ilO_w_lg_n0iOi81w(0); + wire_w_lg_rx_detect_valid_sync259w(0) <= rx_detect_valid_sync AND wire_n0ilO_w_lg_n1O0i73w(0); + wire_w_lg_rx_found_sync86w(0) <= rx_found_sync AND wire_w_lg_w_lg_rrdwidth_rx82w85w(0); + wire_w_lg_w_rxd_range52w279w(0) <= wire_w_rxd_range52w(0) AND wire_w_lg_w_rxd_range51w277w(0); + wire_w_lg_w_rxd_range20w235w(0) <= wire_w_rxd_range20w(0) AND wire_w_lg_w_rxd_range19w233w(0); + wire_w_lg_nlO00l272w(0) <= NOT nlO00l; + wire_w_lg_nlO0iO267w(0) <= NOT nlO0iO; + wire_w_lg_nlO0li263w(0) <= NOT nlO0li; + wire_w_lg_nlOili225w(0) <= NOT nlOili; + wire_w_lg_nlOl0l211w(0) <= NOT nlOl0l; + wire_w_lg_nlOliO197w(0) <= NOT nlOliO; + wire_w_lg_rclkcmpinsertpad205w(0) <= NOT rclkcmpinsertpad; + wire_w_lg_reset_n72w(0) <= NOT reset_n; + wire_w_lg_rind_error_reporting109w(0) <= NOT rind_error_reporting; + wire_w_lg_rrdwidth_rx199w(0) <= NOT rrdwidth_rx; + wire_w_lg_sigdetni66w(0) <= NOT sigdetni; + wire_w_lg_w_rxd_range51w277w(0) <= NOT wire_w_rxd_range51w(0); + wire_w_lg_w_rxd_range19w233w(0) <= NOT wire_w_rxd_range19w(0); + n11lO <= '1'; + nlO00i <= (rclkcmpinsertpad AND (nlO0il AND nlO00l)); + nlO00l <= (((((((rxd(0) AND rxd(1)) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + nlO00O <= (wire_w_lg_rclkcmpinsertpad205w(0) AND wire_w_lg_w_lg_nlO0iO267w268w(0)); + nlO01i <= ((NOT rxd(13)) AND wire_w_lg_w_rxd_range51w277w(0)); + nlO01l <= wire_w_lg_w_rxd_range52w279w(0); + nlO01O <= (rclkcmpinsertpad AND (nlO0il AND wire_w_lg_nlO00l272w(0))); + nlO0ii <= (wire_w_lg_rclkcmpinsertpad205w(0) AND (nlO0iO AND nlO0il)); + nlO0il <= ((NOT rxd(13)) AND rxd(14)); + nlO0iO <= ((((((((NOT rxd(0)) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + nlO0li <= (wire_w_lg_rx_detect_valid_sync259w(0) AND (nlO0ll42 XOR nlO0ll41)); + nlOi0i <= (wire_w_lg_rclkcmpinsertpad227w(0) AND (nlOi0l36 XOR nlOi0l35)); + nlOi1l <= ((NOT rxd(45)) AND wire_w_lg_w_rxd_range19w233w(0)); + nlOi1O <= (wire_w_lg_w_rxd_range20w235w(0) AND (nlO0OO38 XOR nlO0OO37)); + nlOiii <= (wire_w_lg_rclkcmpinsertpad221w(0) AND (nlOiil34 XOR nlOiil33)); + nlOili <= ((((((((rxd(32) AND rxd(33)) AND rxd(34)) AND (NOT rxd(35))) AND rxd(36)) AND rxd(37)) AND rxd(38)) AND rxd(39)) AND (nlO0Oi40 XOR nlO0Oi39)); + nlOill <= ((wire_w_lg_rclkcmpinsertpad205w(0) AND (wire_w_lg_w_lg_nlOl0l211w212w(0) AND (nlOiOl30 XOR nlOiOl29))) AND (nlOilO32 XOR nlOilO31)); + nlOl0i <= ((NOT rxd(45)) AND rxd(46)); + nlOl0l <= ((((((((NOT rxd(32)) AND rxd(33)) AND rxd(34)) AND rxd(35)) AND rxd(36)) AND rxd(37)) AND rxd(38)) AND rxd(39)); + nlOl0O <= ((wire_w_lg_reset_n72w(0) OR wire_w_lg_rrdwidth_rx199w(0)) OR (NOT (nlOlii26 XOR nlOlii25))); + nlOl1i <= ((wire_w_lg_rclkcmpinsertpad205w(0) AND (nlOl0l AND nlOl0i)) AND (nlOl1l28 XOR nlOl1l27)); + nlOliO <= (wire_w_lg_rx_detect_valid_sync193w(0) AND (nlOlli24 XOR nlOlli23)); + nlOllO <= ((reset_n AND rrdwidth_rx) AND (nlOlOi22 XOR nlOlOi21)); + nlOlOO <= ((wire_n10ii_dataout OR wire_n1OlO_dataout) OR (NOT (nlOO1i20 XOR nlOO1i19))); + nlOO0O <= (nlOOii AND rind_error_reporting); + nlOO1O <= (wire_w_lg_nlOOii110w(0) AND (nlOO0i18 XOR nlOO0i17)); + nlOOii <= (wire_n1liO_dataout OR wire_n00OO_dataout); + nlOOil <= ((wire_n10il_dataout OR wire_n1OOi_dataout) OR (NOT (nlOOiO16 XOR nlOOiO15))); + nlOOll <= (wire_n10iO_dataout OR wire_n1OOl_dataout); + nlOOlO <= (wire_n1lll_dataout OR wire_n0i1l_dataout); + nlOOOi <= (wire_n0ilO_w_lg_w_lg_w_lg_n1O0i73w79w80w(0) OR (wire_n0ilO_w_lg_w_lg_w_lg_n0iOi81w94w95w(0) AND (nlOOOl14 XOR nlOOOl13))); + polinv_rx_int <= wire_n1iO_dataout; + rxd_ch <= ( wire_ni_dataout & wire_nlO_dataout & wire_nll_dataout & wire_nli_dataout & wire_niO_dataout & wire_nil_dataout & wire_nii_dataout & wire_n0O_dataout & wire_n0l_dataout & wire_n0i_dataout & wire_n1O_dataout & wire_n1l_dataout & wire_n1i_dataout & wire_nlOO_dataout & wire_nlOl_dataout & wire_nlOi_dataout & wire_nllO_dataout & wire_nlll_dataout & wire_nlli_dataout & wire_nliO_dataout & wire_nlil_dataout & wire_nlii_dataout & wire_nl0O_dataout & wire_nl0l_dataout & wire_nl0i_dataout & wire_nl1O_dataout & wire_nl1l_dataout & wire_nl1i_dataout & wire_niOO_dataout & wire_niOl_dataout & wire_niOi_dataout & wire_nilO_dataout & wire_nill_dataout & wire_nili_dataout & wire_niiO_dataout & wire_niil_dataout & wire_niii_dataout & wire_ni0O_dataout & wire_ni0l_dataout & wire_ni0i_dataout & wire_ni1O_dataout & wire_ni1l_dataout & wire_ni1i_dataout & wire_n0OO_dataout & wire_n0Ol_dataout & wire_n0Oi_dataout & wire_n0lO_dataout & wire_n0ll_dataout & wire_n0li_dataout & wire_n0iO_dataout & wire_n0il_dataout & wire_n0ii_dataout & wire_n00O_dataout & wire_n00l_dataout & wire_n00i_dataout & wire_n01O_dataout & wire_n01l_dataout & wire_n01i_dataout & wire_n1OO_dataout & wire_n1Ol_dataout & wire_n1Oi_dataout & wire_n1lO_dataout & wire_n1ll_dataout & wire_n1li_dataout); + rxelecidle <= wire_n1ii_dataout; + rxstatus <= ( wire_n10O_dataout & wire_n10l_dataout & wire_n10i_dataout); + rxvalid <= wire_n1il_dataout; + wire_w_rxd_range52w(0) <= rxd(13); + wire_w_rxd_range51w(0) <= rxd(14); + wire_w_rxd_range20w(0) <= rxd(45); + wire_w_rxd_range19w(0) <= rxd(46); + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n110l7 <= n110l8; + END IF; + if (now = 0 ns) then + n110l7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n110l8 <= n110l7; + END IF; + END PROCESS; + wire_n110l8_w_lg_q84w(0) <= n110l8 XOR n110l7; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n111i11 <= n111i12; + END IF; + if (now = 0 ns) then + n111i11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n111i12 <= n111i11; + END IF; + END PROCESS; + wire_n111i12_w_lg_q92w(0) <= n111i12 XOR n111i11; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n111O10 <= n111O9; + END IF; + END PROCESS; + wire_n111O10_w_lg_q88w(0) <= n111O10 XOR n111O9; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n111O9 <= n111O10; + END IF; + if (now = 0 ns) then + n111O9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n11ii5 <= n11ii6; + END IF; + if (now = 0 ns) then + n11ii5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n11ii6 <= n11ii5; + END IF; + END PROCESS; + wire_n11ii6_w_lg_q77w(0) <= n11ii6 XOR n11ii5; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n11iO3 <= n11iO4; + END IF; + if (now = 0 ns) then + n11iO3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n11iO4 <= n11iO3; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n11Ol1 <= n11Ol2; + END IF; + if (now = 0 ns) then + n11Ol1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n11Ol2 <= n11Ol1; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0ll41 <= nlO0ll42; + END IF; + if (now = 0 ns) then + nlO0ll41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0ll42 <= nlO0ll41; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0Oi39 <= nlO0Oi40; + END IF; + if (now = 0 ns) then + nlO0Oi39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0Oi40 <= nlO0Oi39; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0OO37 <= nlO0OO38; + END IF; + if (now = 0 ns) then + nlO0OO37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlO0OO38 <= nlO0OO37; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOi0l35 <= nlOi0l36; + END IF; + if (now = 0 ns) then + nlOi0l35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOi0l36 <= nlOi0l35; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOiil33 <= nlOiil34; + END IF; + if (now = 0 ns) then + nlOiil33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOiil34 <= nlOiil33; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOilO31 <= nlOilO32; + END IF; + if (now = 0 ns) then + nlOilO31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOilO32 <= nlOilO31; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOiOl29 <= nlOiOl30; + END IF; + if (now = 0 ns) then + nlOiOl29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOiOl30 <= nlOiOl29; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOl1l27 <= nlOl1l28; + END IF; + if (now = 0 ns) then + nlOl1l27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOl1l28 <= nlOl1l27; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlii25 <= nlOlii26; + END IF; + if (now = 0 ns) then + nlOlii25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlii26 <= nlOlii25; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlli23 <= nlOlli24; + END IF; + if (now = 0 ns) then + nlOlli23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlli24 <= nlOlli23; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlOi21 <= nlOlOi22; + END IF; + if (now = 0 ns) then + nlOlOi21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOlOi22 <= nlOlOi21; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOO0i17 <= nlOO0i18; + END IF; + if (now = 0 ns) then + nlOO0i17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOO0i18 <= nlOO0i17; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOO1i19 <= nlOO1i20; + END IF; + if (now = 0 ns) then + nlOO1i19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOO1i20 <= nlOO1i19; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOOiO15 <= nlOOiO16; + END IF; + if (now = 0 ns) then + nlOOiO15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOOiO16 <= nlOOiO15; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOOOl13 <= nlOOOl14; + END IF; + if (now = 0 ns) then + nlOOOl13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nlOOOl14 <= nlOOOl13; + END IF; + END PROCESS; + PROCESS (clk, reset_n) + BEGIN + IF (reset_n = '0') THEN + n00ii <= '0'; + n0ill <= '0'; + n0iOi <= '0'; + n1l1l <= '0'; + n1O0i <= '0'; + n1O1O <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + n00ii <= n0ill; + n0ill <= txdetectrx; + n0iOi <= rx_detect_valid_sync; + n1l1l <= n1O1O; + n1O0i <= rx_detect_valid_sync; + n1O1O <= txdetectrx; + END IF; + END PROCESS; + wire_n0ilO_w_lg_w_lg_w_lg_n0iOi81w94w95w(0) <= wire_n0ilO_w_lg_w_lg_n0iOi81w94w(0) AND n00ii; + wire_n0ilO_w_lg_w_lg_w_lg_n1O0i73w79w80w(0) <= wire_n0ilO_w_lg_w_lg_n1O0i73w79w(0) AND n1l1l; + wire_n0ilO_w_lg_w_lg_n0iOi81w94w(0) <= wire_n0ilO_w_lg_n0iOi81w(0) AND wire_w_lg_w_lg_rx_detect_valid_sync90w93w(0); + wire_n0ilO_w_lg_w_lg_n1O0i73w79w(0) <= wire_n0ilO_w_lg_n1O0i73w(0) AND wire_w_lg_w_lg_rx_detect_valid_sync75w78w(0); + wire_n0ilO_w_lg_n0iOi81w(0) <= NOT n0iOi; + wire_n0ilO_w_lg_n1O0i73w(0) <= NOT n1O0i; + PROCESS (clk, reset_n, wire_nl_CLRN) + BEGIN + IF (reset_n = '0') THEN + nlOOO <= '1'; + nO <= '1'; + ELSIF (wire_nl_CLRN = '0') THEN + nlOOO <= '0'; + nO <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + nlOOO <= rxelectricalidle; + nO <= nlOOO; + END IF; + if (now = 0 ns) then + nlOOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nO <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl_CLRN <= (n11Ol2 XOR n11Ol1); + wire_n000i_dataout <= (rxd(45) AND rxd(46)) AND NOT(nlOi0i); + wire_n001i_dataout <= wire_n001O_dataout AND NOT(nlOill); + wire_n001l_dataout <= nlOi0i AND NOT(nlOiii); + wire_n001O_dataout <= wire_n000i_dataout AND NOT(nlOiii); + wire_n00i_dataout <= rxd(9) AND rrx_pipe_enable; + wire_n00l_dataout <= rxd(10) AND rrx_pipe_enable; + wire_n00O_dataout <= rxd(11) AND rrx_pipe_enable; + wire_n00OO_dataout <= rxd(43) AND (nlOllO AND wire_w_lg_nlOliO197w(0)); + wire_n010i_dataout <= wire_n01il_dataout AND NOT(nlOi1l); + wire_n010l_dataout <= nlOi1O AND NOT(nlOi1l); + wire_n010O_dataout <= wire_n01iO_dataout AND NOT(nlOi1l); + wire_n011i_dataout <= wire_n010l_dataout AND NOT(nlOliO); + wire_n011l_dataout <= wire_n010O_dataout AND NOT(nlOliO); + wire_n011O_dataout <= wire_n01ii_dataout AND NOT(nlOliO); + wire_n01i_dataout <= rxd(6) AND rrx_pipe_enable; + wire_n01ii_dataout <= wire_n01li_dataout AND NOT(nlOi1l); + wire_n01il_dataout <= wire_n01ll_dataout AND NOT(nlOi1O); + wire_n01iO_dataout <= wire_n01lO_dataout AND NOT(nlOi1O); + wire_n01l_dataout <= rxd(7) AND rrx_pipe_enable; + wire_n01li_dataout <= wire_n01Oi_dataout AND NOT(nlOi1O); + wire_n01ll_dataout <= wire_n01Ol_dataout AND NOT(nlOl1i); + wire_n01lO_dataout <= wire_n01OO_dataout OR nlOl1i; + wire_n01O_dataout <= rxd(8) AND rrx_pipe_enable; + wire_n01Oi_dataout <= wire_n001i_dataout AND NOT(nlOl1i); + wire_n01Ol_dataout <= wire_n001l_dataout OR nlOill; + wire_n01OO_dataout <= nlOiii AND NOT(nlOill); + wire_n0i_dataout <= rxd(54) AND rrx_pipe_enable; + wire_n0i1l_dataout <= rxd(41) AND (nlOllO AND wire_w_lg_nlOliO197w(0)); + wire_n0ii_dataout <= rxd(12) AND rrx_pipe_enable; + wire_n0il_dataout <= rxd(13) AND rrx_pipe_enable; + wire_n0iO_dataout <= rxd(14) AND rrx_pipe_enable; + wire_n0l_dataout <= rxd(55) AND rrx_pipe_enable; + wire_n0li_dataout <= rxd(15) AND rrx_pipe_enable; + wire_n0ll_dataout <= rxd(16) AND rrx_pipe_enable; + wire_n0lO_dataout <= rxd(17) AND rrx_pipe_enable; + wire_n0O_dataout <= rxd(56) AND rrx_pipe_enable; + wire_n0Oi_dataout <= rxd(18) AND rrx_pipe_enable; + wire_n0Ol_dataout <= rxd(19) AND rrx_pipe_enable; + wire_n0OO_dataout <= rxd(20) AND rrx_pipe_enable; + wire_n100O_dataout <= wire_n10li_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_n10i_dataout <= wire_nliOl_dataout WHEN rrx_pipe_enable = '1' ELSE rx_found; + wire_n10ii_dataout <= wire_n10ll_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_n10il_dataout <= wire_n10lO_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_n10iO_dataout <= wire_n10Oi_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_n10l_dataout <= wire_nliOO_dataout WHEN rrx_pipe_enable = '1' ELSE rx_detect_valid; + wire_n10li_dataout <= wire_n10Ol_dataout AND NOT(nlO0li); + wire_n10ll_dataout <= wire_n10OO_dataout AND NOT(nlO0li); + wire_n10lO_dataout <= wire_n1i1i_dataout AND NOT(nlO0li); + wire_n10O_dataout <= wire_nll1i_dataout AND rrx_pipe_enable; + wire_n10Oi_dataout <= wire_n1i1l_dataout AND NOT(nlO0li); + wire_n10Ol_dataout <= wire_n1i1O_dataout AND NOT(nlO01i); + wire_n10OO_dataout <= nlO01l AND NOT(nlO01i); + wire_n11i_dataout <= wire_n11l_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_n11l_dataout <= ((rxd(10) OR rxd(42)) OR (NOT (n11iO4 XOR n11iO3))) WHEN rrdwidth_rx = '1' ELSE rxd(10); + wire_n1i_dataout <= rxd(51) AND rrx_pipe_enable; + wire_n1i0i_dataout <= wire_n1iii_dataout AND NOT(nlO01l); + wire_n1i0l_dataout <= wire_n1iil_dataout AND NOT(nlO01l); + wire_n1i0O_dataout <= wire_n1iiO_dataout AND NOT(nlO0ii); + wire_n1i1i_dataout <= wire_n1i0i_dataout AND NOT(nlO01i); + wire_n1i1l_dataout <= wire_n1i0l_dataout AND NOT(nlO01i); + wire_n1i1O_dataout <= wire_n1i0O_dataout AND NOT(nlO01l); + wire_n1ii_dataout <= wire_nlOOl_dataout WHEN rrx_pipe_enable = '1' ELSE wire_w_lg_sigdetni66w(0); + wire_n1iii_dataout <= wire_n1ili_dataout OR nlO0ii; + wire_n1iil_dataout <= wire_n1ill_dataout AND NOT(nlO0ii); + wire_n1iiO_dataout <= wire_n1ilO_dataout OR nlO00O; + wire_n1il_dataout <= wire_n11i_dataout AND rrx_pipe_enable; + wire_n1ili_dataout <= nlO00i AND NOT(nlO00O); + wire_n1ill_dataout <= wire_n1iOi_dataout AND NOT(nlO00O); + wire_n1ilO_dataout <= nlO01O AND NOT(nlO00i); + wire_n1iO_dataout <= rxpolarity WHEN rrx_pipe_enable = '1' ELSE polinv_rx; + wire_n1iOi_dataout <= wire_n1iOl_dataout AND NOT(nlO00i); + wire_n1iOl_dataout <= (rxd(13) AND rxd(14)) AND NOT(nlO01O); + wire_n1l_dataout <= rxd(52) AND rrx_pipe_enable; + wire_n1li_dataout <= rxd(0) AND rrx_pipe_enable; + wire_n1liO_dataout <= rxd(11) AND (reset_n AND wire_w_lg_nlO0li263w(0)); + wire_n1ll_dataout <= rxd(1) AND rrx_pipe_enable; + wire_n1lll_dataout <= rxd(9) AND (reset_n AND wire_w_lg_nlO0li263w(0)); + wire_n1lO_dataout <= rxd(2) AND rrx_pipe_enable; + wire_n1O_dataout <= rxd(53) AND rrx_pipe_enable; + wire_n1Oi_dataout <= rxd(3) AND rrx_pipe_enable; + wire_n1Ol_dataout <= rxd(4) AND rrx_pipe_enable; + wire_n1Oll_dataout <= wire_n1OOO_dataout AND NOT(nlOl0O); + wire_n1OlO_dataout <= wire_n011i_dataout AND NOT(nlOl0O); + wire_n1OO_dataout <= rxd(5) AND rrx_pipe_enable; + wire_n1OOi_dataout <= wire_n011l_dataout AND NOT(nlOl0O); + wire_n1OOl_dataout <= wire_n011O_dataout AND NOT(nlOl0O); + wire_n1OOO_dataout <= wire_n010i_dataout AND NOT(nlOliO); + wire_ni_dataout <= rxd(63) AND rrx_pipe_enable; + wire_ni0i_dataout <= rxd(24) AND rrx_pipe_enable; + wire_ni0l_dataout <= rxd(25) AND rrx_pipe_enable; + wire_ni0O_dataout <= rxd(26) AND rrx_pipe_enable; + wire_ni1i_dataout <= rxd(21) AND rrx_pipe_enable; + wire_ni1l_dataout <= rxd(22) AND rrx_pipe_enable; + wire_ni1O_dataout <= rxd(23) AND rrx_pipe_enable; + wire_nii_dataout <= rxd(57) AND rrx_pipe_enable; + wire_niii_dataout <= rxd(27) AND rrx_pipe_enable; + wire_niil_dataout <= rxd(28) AND rrx_pipe_enable; + wire_niiO_dataout <= rxd(29) AND rrx_pipe_enable; + wire_nil_dataout <= rxd(58) AND rrx_pipe_enable; + wire_nili_dataout <= rxd(30) AND rrx_pipe_enable; + wire_nill_dataout <= rxd(31) AND rrx_pipe_enable; + wire_nilO_dataout <= rxd(32) AND rrx_pipe_enable; + wire_niO_dataout <= rxd(59) AND rrx_pipe_enable; + wire_niOi_dataout <= rxd(33) AND rrx_pipe_enable; + wire_niOl_dataout <= rxd(34) AND rrx_pipe_enable; + wire_niOO_dataout <= rxd(35) AND rrx_pipe_enable; + wire_nl0i_dataout <= rxd(39) AND rrx_pipe_enable; + wire_nl0l_dataout <= rxd(40) AND rrx_pipe_enable; + wire_nl0O_dataout <= rxd(41) AND rrx_pipe_enable; + wire_nl1i_dataout <= rxd(36) AND rrx_pipe_enable; + wire_nl1l_dataout <= rxd(37) AND rrx_pipe_enable; + wire_nl1O_dataout <= rxd(38) AND rrx_pipe_enable; + wire_nli_dataout <= rxd(60) AND rrx_pipe_enable; + wire_nlii_dataout <= rxd(42) AND rrx_pipe_enable; + wire_nlil_dataout <= rxd(43) AND rrx_pipe_enable; + wire_nliO_dataout <= rxd(44) AND rrx_pipe_enable; + wire_nliOl_dataout <= wire_nll1l_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_nliOO_dataout <= wire_nll1O_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_nll_dataout <= rxd(61) AND rrx_pipe_enable; + wire_nll0i_dataout <= wire_nllii_dataout AND NOT(nlOOOi); + wire_nll0l_dataout <= wire_nllil_dataout AND NOT(nlOOlO); + wire_nll0O_dataout <= wire_nlliO_dataout AND NOT(nlOOlO); + wire_nll1i_dataout <= wire_nll0i_dataout AND NOT(wire_w_lg_reset_n72w(0)); + wire_nll1l_dataout <= wire_nll0l_dataout OR nlOOOi; + wire_nll1O_dataout <= wire_nll0O_dataout OR nlOOOi; + wire_nlli_dataout <= rxd(45) AND rrx_pipe_enable; + wire_nllii_dataout <= wire_nllli_dataout OR nlOOlO; + wire_nllil_dataout <= wire_nllll_dataout OR nlOOll; + wire_nlliO_dataout <= wire_nlllO_dataout AND NOT(nlOOll); + wire_nlll_dataout <= rxd(46) AND rrx_pipe_enable; + wire_nllli_dataout <= wire_nllOi_dataout OR nlOOll; + wire_nllll_dataout <= wire_nllOl_dataout AND NOT(nlOOil); + wire_nlllO_dataout <= wire_nllOO_dataout OR nlOOil; + wire_nllO_dataout <= rxd(47) AND rrx_pipe_enable; + wire_nllOi_dataout <= wire_nlO1i_dataout OR nlOOil; + wire_nllOl_dataout <= wire_nlO1l_dataout OR nlOO0O; + wire_nllOO_dataout <= wire_nlO1O_dataout OR nlOO0O; + wire_nlO_dataout <= rxd(62) AND rrx_pipe_enable; + wire_nlO0i_dataout <= (wire_n100O_dataout OR wire_n1Oll_dataout) AND NOT(nlOlOO); + wire_nlO1i_dataout <= nlOO1O OR nlOO0O; + wire_nlO1l_dataout <= wire_nlO0i_dataout AND NOT(nlOO1O); + wire_nlO1O_dataout <= nlOlOO AND NOT(nlOO1O); + wire_nlOi_dataout <= rxd(48) AND rrx_pipe_enable; + wire_nlOl_dataout <= rxd(49) AND rrx_pipe_enable; + wire_nlOO_dataout <= rxd(50) AND rrx_pipe_enable; + wire_nlOOl_dataout <= nO OR wire_w_lg_reset_n72w(0); + + END RTL; --cycloneiv_hssi_rx_pipe_interface +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 36 mux21 13 oper_mux 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_tx_pipe_interface IS + PORT + ( + clk : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + powerstate : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + refclk_b : IN STD_LOGIC; + refclk_b_reset_n : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + rev_loopbk : OUT STD_LOGIC; + revloopback : IN STD_LOGIC; + rtx_elec_idle_delay : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rtx_pipe_enable : IN STD_LOGIC; + rtxswing_sel_ena : IN STD_LOGIC; + tx_elec_idle : OUT STD_LOGIC; + tx_elec_idle_comp : IN STD_LOGIC; + txd : OUT STD_LOGIC_VECTOR (43 DOWNTO 0); + txd_ch : IN STD_LOGIC_VECTOR (43 DOWNTO 0); + txdeemph : IN STD_LOGIC; + txdeemph_int : OUT STD_LOGIC; + txdetectrx : OUT STD_LOGIC; + txdetectrxloopback : IN STD_LOGIC; + txelecidle : IN STD_LOGIC; + txmargin : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + txmargin_int : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + txswing : IN STD_LOGIC; + txswing_int : OUT STD_LOGIC + ); + END cycloneiv_hssi_tx_pipe_interface; + + ARCHITECTURE RTL OF cycloneiv_hssi_tx_pipe_interface IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL niiOl23 : STD_LOGIC := '0'; + SIGNAL niiOl24 : STD_LOGIC := '0'; + SIGNAL nil0i19 : STD_LOGIC := '0'; + SIGNAL nil0i20 : STD_LOGIC := '0'; + SIGNAL wire_nil0i20_w_lg_w_lg_q190w191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil0i20_w_lg_q190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nil0l17 : STD_LOGIC := '0'; + SIGNAL nil0l18 : STD_LOGIC := '0'; + SIGNAL wire_nil0l18_w_lg_w_lg_q184w185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil0l18_w_lg_q184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nil0O15 : STD_LOGIC := '0'; + SIGNAL nil0O16 : STD_LOGIC := '0'; + SIGNAL wire_nil0O16_w_lg_w_lg_q171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil0O16_w_lg_q171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nil1i21 : STD_LOGIC := '0'; + SIGNAL nil1i22 : STD_LOGIC := '0'; + SIGNAL nilii13 : STD_LOGIC := '0'; + SIGNAL nilii14 : STD_LOGIC := '0'; + SIGNAL niliO11 : STD_LOGIC := '0'; + SIGNAL niliO12 : STD_LOGIC := '0'; + SIGNAL nilli10 : STD_LOGIC := '0'; + SIGNAL nilli9 : STD_LOGIC := '0'; + SIGNAL nilOi7 : STD_LOGIC := '0'; + SIGNAL nilOi8 : STD_LOGIC := '0'; + SIGNAL nilOl5 : STD_LOGIC := '0'; + SIGNAL nilOl6 : STD_LOGIC := '0'; + SIGNAL niO1i3 : STD_LOGIC := '0'; + SIGNAL niO1i4 : STD_LOGIC := '0'; + SIGNAL niO1O1 : STD_LOGIC := '0'; + SIGNAL niO1O2 : STD_LOGIC := '0'; + SIGNAL nl00i : STD_LOGIC := '0'; + SIGNAL nl10i : STD_LOGIC := '0'; + SIGNAL nl10l : STD_LOGIC := '0'; + SIGNAL nl10O : STD_LOGIC := '0'; + SIGNAL nl11O : STD_LOGIC := '0'; + SIGNAL nl1ii : STD_LOGIC := '0'; + SIGNAL nl1il : STD_LOGIC := '0'; + SIGNAL nl1iO : STD_LOGIC := '0'; + SIGNAL nl1li : STD_LOGIC := '0'; + SIGNAL wire_nl01O_CLRN : STD_LOGIC; + SIGNAL wire_nl01O_PRN : STD_LOGIC; + SIGNAL nl1lO : STD_LOGIC := '0'; + SIGNAL wire_nl1ll_CLRN : STD_LOGIC; + SIGNAL wire_nl1ll_PRN : STD_LOGIC; + SIGNAL wire_nl1ll_ENA : STD_LOGIC; + SIGNAL nl1Oi : STD_LOGIC := '0'; + SIGNAL nl1OO : STD_LOGIC := '0'; + SIGNAL wire_nl1Ol_w_lg_nl1Oi168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00O_dataout : STD_LOGIC; + SIGNAL wire_nl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl11l_o : STD_LOGIC; + SIGNAL wire_nl11l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_w_powerdown_range196w204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOO193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reset_n194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rtx_pipe_enable151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_powerdown_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nil1O : STD_LOGIC; + SIGNAL nilll : STD_LOGIC; + SIGNAL nillO : STD_LOGIC; + SIGNAL nilOO : STD_LOGIC; + SIGNAL wire_w_powerdown_range196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_powerdown_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rtx_elec_idle_delay_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_w_powerdown_range196w204w(0) <= wire_w_powerdown_range196w(0) AND wire_w_lg_w_powerdown_range198w199w(0); + wire_w_lg_nilOO193w(0) <= NOT nilOO; + wire_w_lg_reset_n194w(0) <= NOT reset_n; + wire_w_lg_rtx_pipe_enable151w(0) <= NOT rtx_pipe_enable; + wire_w_lg_w_powerdown_range198w199w(0) <= NOT wire_w_powerdown_range198w(0); + nil1O <= (wire_w_lg_reset_n194w(0) OR wire_w_lg_rtx_pipe_enable151w(0)); + nilll <= '0'; + nillO <= '1'; + nilOO <= ((tx_elec_idle_comp OR nl1lO) OR (NOT (niO1i4 XOR niO1i3))); + powerstate <= ( wire_nl0OO_dataout & wire_nl0Ol_dataout & wire_nl0Oi_dataout & wire_nl0lO_dataout); + rev_loopbk <= wire_nl0iO_dataout; + tx_elec_idle <= wire_nl0il_dataout; + txd <= ( txd_ch(43 DOWNTO 0)); + txdeemph_int <= txdeemph; + txdetectrx <= wire_nl00O_dataout; + txmargin_int <= ( txmargin(2 DOWNTO 0)); + txswing_int <= wire_nl0ll_dataout; + wire_w_powerdown_range196w(0) <= powerdown(0); + wire_w_powerdown_range198w(0) <= powerdown(1); + wire_w_rtx_elec_idle_delay_range170w(0) <= rtx_elec_idle_delay(0); + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niiOl23 <= niiOl24; + END IF; + if (now = 0 ns) then + niiOl23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niiOl24 <= niiOl23; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil0i19 <= nil0i20; + END IF; + if (now = 0 ns) then + nil0i19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil0i20 <= nil0i19; + END IF; + END PROCESS; + wire_nil0i20_w_lg_w_lg_q190w191w(0) <= wire_nil0i20_w_lg_q190w(0) AND nl00i; + wire_nil0i20_w_lg_q190w(0) <= nil0i20 XOR nil0i19; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil0l17 <= nil0l18; + END IF; + if (now = 0 ns) then + nil0l17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil0l18 <= nil0l17; + END IF; + END PROCESS; + wire_nil0l18_w_lg_w_lg_q184w185w(0) <= wire_nil0l18_w_lg_q184w(0) AND nl10O; + wire_nil0l18_w_lg_q184w(0) <= nil0l18 XOR nil0l17; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil0O15 <= nil0O16; + END IF; + if (now = 0 ns) then + nil0O15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil0O16 <= nil0O15; + END IF; + END PROCESS; + wire_nil0O16_w_lg_w_lg_q171w172w(0) <= wire_nil0O16_w_lg_q171w(0) AND wire_w_rtx_elec_idle_delay_range170w(0); + wire_nil0O16_w_lg_q171w(0) <= nil0O16 XOR nil0O15; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil1i21 <= nil1i22; + END IF; + if (now = 0 ns) then + nil1i21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nil1i22 <= nil1i21; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilii13 <= nilii14; + END IF; + if (now = 0 ns) then + nilii13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilii14 <= nilii13; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niliO11 <= niliO12; + END IF; + if (now = 0 ns) then + niliO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niliO12 <= niliO11; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilli10 <= nilli9; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilli9 <= nilli10; + END IF; + if (now = 0 ns) then + nilli9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilOi7 <= nilOi8; + END IF; + if (now = 0 ns) then + nilOi7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilOi8 <= nilOi7; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilOl5 <= nilOl6; + END IF; + if (now = 0 ns) then + nilOl5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN nilOl6 <= nilOl5; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niO1i3 <= niO1i4; + END IF; + if (now = 0 ns) then + niO1i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niO1i4 <= niO1i3; + END IF; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niO1O1 <= niO1O2; + END IF; + if (now = 0 ns) then + niO1O1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b) + BEGIN + IF (refclk_b = '1' AND refclk_b'event) THEN niO1O2 <= niO1O1; + END IF; + END PROCESS; + PROCESS (refclk_b, wire_nl01O_PRN, wire_nl01O_CLRN) + BEGIN + IF (wire_nl01O_PRN = '0') THEN + nl00i <= '1'; + nl10i <= '1'; + nl10l <= '1'; + nl10O <= '1'; + nl11O <= '1'; + nl1ii <= '1'; + nl1il <= '1'; + nl1iO <= '1'; + nl1li <= '1'; + ELSIF (wire_nl01O_CLRN = '0') THEN + nl00i <= '0'; + nl10i <= '0'; + nl10l <= '0'; + nl10O <= '0'; + nl11O <= '0'; + nl1ii <= '0'; + nl1il <= '0'; + nl1iO <= '0'; + nl1li <= '0'; + ELSIF (refclk_b = '1' AND refclk_b'event) THEN + nl00i <= nl11O; + nl10i <= nl10l; + nl10l <= nl10O; + nl10O <= nl1ii; + nl11O <= nl10i; + nl1ii <= nl1il; + nl1il <= nl1iO; + nl1iO <= nl1li; + nl1li <= nilOO; + END IF; + if (now = 0 ns) then + nl00i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl10i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl10l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl10O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl11O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1li <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl01O_CLRN <= (nilOl6 XOR nilOl5); + wire_nl01O_PRN <= ((nilOi8 XOR nilOi7) AND refclk_b_reset_n); + PROCESS (refclk_b, wire_nl1ll_PRN, wire_nl1ll_CLRN) + BEGIN + IF (wire_nl1ll_PRN = '0') THEN + nl1lO <= '1'; + ELSIF (wire_nl1ll_CLRN = '0') THEN + nl1lO <= '0'; + ELSIF (refclk_b = '1' AND refclk_b'event) THEN + IF (wire_nl1ll_ENA = '1') THEN + nl1lO <= nilll; + END IF; + END IF; + if (now = 0 ns) then + nl1lO <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl1ll_CLRN <= (nilli10 XOR nilli9); + wire_nl1ll_ENA <= (((nl1OO AND nl1lO) AND (nilii14 XOR nilii13)) AND wire_nl1Ol_w_lg_nl1Oi168w(0)); + wire_nl1ll_PRN <= ((niliO12 XOR niliO11) AND refclk_b_reset_n); + PROCESS (refclk_b, refclk_b_reset_n) + BEGIN + IF (refclk_b_reset_n = '0') THEN + nl1Oi <= '0'; + nl1OO <= '0'; + ELSIF (refclk_b = '1' AND refclk_b'event) THEN + nl1Oi <= nl1OO; + nl1OO <= tx_elec_idle_comp; + END IF; + END PROCESS; + wire_nl1Ol_w_lg_nl1Oi168w(0) <= NOT nl1Oi; + wire_niOll_dataout <= (powerdown(0) AND powerdown(1)) AND NOT(nil1O); + wire_niOlO_dataout <= ((NOT powerdown(0)) AND powerdown(1)) AND NOT(nil1O); + wire_niOOi_dataout <= (wire_w_lg_w_powerdown_range196w204w(0) AND (niiOl24 XOR niiOl23)) AND NOT(nil1O); + wire_niOOl_dataout <= (((NOT powerdown(0)) AND wire_w_lg_w_powerdown_range198w199w(0)) AND (nil1i22 XOR nil1i21)) AND NOT(nil1O); + wire_nl00O_dataout <= txdetectrxloopback WHEN wire_w_lg_rtx_pipe_enable151w(0) = '1' ELSE (txdetectrxloopback AND wire_niOlO_dataout); + wire_nl0il_dataout <= txelecidle WHEN wire_w_lg_rtx_pipe_enable151w(0) = '1' ELSE wire_nl11i_dataout; + wire_nl0iO_dataout <= revloopback WHEN wire_w_lg_rtx_pipe_enable151w(0) = '1' ELSE ((txdetectrxloopback AND wire_niOOl_dataout) AND (niO1O2 XOR niO1O1)); + wire_nl0ll_dataout <= txswing AND rtxswing_sel_ena; + wire_nl0lO_dataout <= wire_niOOl_dataout AND rtx_pipe_enable; + wire_nl0Oi_dataout <= wire_niOOi_dataout AND rtx_pipe_enable; + wire_nl0Ol_dataout <= wire_niOlO_dataout AND rtx_pipe_enable; + wire_nl0OO_dataout <= wire_niOll_dataout AND rtx_pipe_enable; + wire_nl11i_dataout <= nl1li WHEN wire_w_lg_nilOO193w(0) = '1' ELSE wire_nl11l_o; + wire_nl11l_data <= ( wire_nil0i20_w_lg_w_lg_q190w191w & nl11O & nl10i & nl10l & wire_nil0l18_w_lg_w_lg_q184w185w & nl1ii & nl1il & nl1iO); + wire_nl11l_sel <= ( rtx_elec_idle_delay(2 DOWNTO 1) & wire_nil0O16_w_lg_w_lg_q171w172w); + nl11l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl11l_data, + o => wire_nl11l_o, + sel => wire_nl11l_sel + ); + + END RTL; --cycloneiv_hssi_tx_pipe_interface +--synopsys translate_on +--VALID FILE + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_q_pipe_interface_top IS + PORT ( + + -- General signals + -- TX PIPE interface clock == TX Phase Comp write clock + -- RX PIPE interface clock == RX Phase Comp read clock + -- TX Phase Comp FIFO read clock + -- synchronized reset i.e TX Phase Comp write clock + -- synchronized reset i.e.RX Phase Comp read clock + -- synchronized reset i.e.TX Phase Comp read clock + + -- CRAM + -- enable tx pipe interface + -- enable rx pipe interface + -- Single width = 0, double width = 1 + -- programmable delay for controlling output buffer + -- Enables control of voltage swing level. Implementation + -- is optional under PIPE 1.87. When this CRAM is not set, full swing is the default mode + -- normal = 0, bypass = 1 + -- recognize EDB = 0, PAD = 1 insertion for 8b/10b decode errors + -- Combined reporting = 0 i.e. 8b/10b error|disparity error=> rxstatus=3'b100 + -- individual reporting = 1 i.e. 8b/10b error => rxstatus = 3'b111; + -- disparity error => rxstatus = 3'b100 + -- no toggle (gen 2) = 0, toggle (option for gen 1) = 1 + + -- programmable delay for the emulation circuitry of successfull power state + -- transition. Default delay between the change of power state and the assertion + -- of ~ 13 parallel cycles. Setting of this CRAM to 3'b000 will result in a delay + -- of ~ 13 parallel cycles. + + -- PLD - PIPE Interface + -- TX PIPE Interface: Command + -- P0 ==> loopback, P1 ==> RX detection + -- output buffer control + -- txcompliance, // compliance pattern command + -- power state control + + -- Selects transmitter de-emphasis under Gen 2 speeds + -- Selects transmitter voltage levels + -- Selects transmitter voltage swing levels + + -- TX PIPE Interface: Data + -- TX data path + + -- RX PIPE Interface: Command/Status + -- polarity inversion command + + -- indicates symbol lock and valid data + -- indicates receiver detection of electrical idle. + -- encodes receiver status and error codes when receiving data + -- encodes compliance pattern speed when doing receiver detection + + -- RX PIPE Interface: Data + -- RX data path + + -- PHYStatus Generator + -- communicate completion of power state transitions, receiver + -- detection, rate change + + -- Commands + -- enables reverse parallel loopback when in PIPE bypass mode + -- enables polarity inversion when in PIPE bypass mode + + -- PIPE - PCS Inteface + -- TX PIPE Interface + -- TX data path to TX Phase Comp FIFO + -- reverse parallel loopback control to MUX after the encoder + -- compensated txelecidle from the TX Phase Comp FIFO + -- synchronous to refclk_b + + -- Auto Speed Negotiation + + -- Auto Negotiation Module + -- asserted when signaling rate change between Gen 1 and Gen 2 is in process. Sychronization occurs within PIPE module + + -- RX PIPE Interface + -- RX data path from the RX Phase comp FIFO + -- polarity inversion control; sychronization occurs at 8b/10b decoder + + -- PIPE - PMA Interface + -- TX PIPE Interface + -- command to the output buffer + -- command to the PMA module for receiver detection + -- decoded power state: used internally to the PIPE interface + + -- RX PIPE Interface + -- PMA indication of receiver being detected + -- Validation of rx_found + -- electrical idle detection from Rx Electrical Idle inference module + + --shawn + --shawn + --shawn + + -- PHYStatus Generator + -- asserted when successful power state transition occurs + -- validates power_state_transition_done, currently tied to 0 + + -- PIPE-DPRIO interface + -- Selects transmitter de-emphasis under Gen 2 speeds + -- Selects transmitter voltage levels + -- Selects transmitter voltage swing levels + + --******************************************************************************** + -- INCLUDE STATEMENTS + --******************************************************************************** + + --******************************************************************************** + -- I/O SIGNALS + --******************************************************************************** + -- General signals + --shawn + --shawn + --shawn + + pipe_tx_clk : IN STD_LOGIC; + pipe_rx_clk : IN STD_LOGIC; + refclk_b : IN STD_LOGIC; + tx_pipe_reset : IN STD_LOGIC; + rx_pipe_reset : IN STD_LOGIC; + refclk_b_reset : IN STD_LOGIC; + + -- CRAM + rtx_pipe_enable : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rrdwidth_rx : IN STD_LOGIC; + rtx_elec_idle_delay : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rtxswing_sel_ena : IN STD_LOGIC; + rrx_detect_bypass : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rind_error_reporting : IN STD_LOGIC; + rphystatus_rst_toggle : IN STD_LOGIC; + rphystatus_delay : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- PLD - PIPE Interface + -- TX PIPE Interface: Command + txdetectrxloopback : IN STD_LOGIC; + txelecidle : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + + txdeemph : IN STD_LOGIC; + txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txswing : IN STD_LOGIC; + + -- TX PIPE Interface: Data + txd_ch : IN STD_LOGIC_VECTOR(43 DOWNTO 0); + + -- RX PIPE Interface: Command/Status + rxpolarity : IN STD_LOGIC; + + rxvalid : OUT STD_LOGIC; + rxelecidle : OUT STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX PIPE Interface: Data + rxd_ch : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + + -- PHYStatus Generator + phystatus : OUT STD_LOGIC; + + -- Commands + revloopback : IN STD_LOGIC; + polinv_rx : IN STD_LOGIC; + + -- PIPE - PCS Inteface + -- TX PIPE Interface + txd : OUT STD_LOGIC_VECTOR(43 DOWNTO 0); + rev_loopbk : OUT STD_LOGIC; + tx_elec_idle_comp : IN STD_LOGIC; + + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rmaster_up_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + + -- Auto Negotiation Module + speed_change : IN STD_LOGIC; + speed_change_centrl : IN STD_LOGIC; + speed_change_quad_up : IN STD_LOGIC; + speed_change_quad_down : IN STD_LOGIC; + + -- RX PIPE Interface + rxd : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + polinv_rx_int : OUT STD_LOGIC; + + -- PIPE - PMA Interface + -- TX PIPE Interface + tx_elec_idle : OUT STD_LOGIC; + txdetectrx : OUT STD_LOGIC; + powerstate : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + sigdetni : IN STD_LOGIC; -- ww25_2008 + + -- RX PIPE Interface + rx_found : IN STD_LOGIC; + rx_detect_valid : IN STD_LOGIC; + rxelectricalidle : IN STD_LOGIC; + txdetectrxin : IN STD_LOGIC; + powerstatein : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + use_powerstatein : IN STD_LOGIC; + + -- PHYStatus Generator + power_state_transition_done : IN STD_LOGIC; + power_state_transition_done_ena : IN STD_LOGIC; + + -- PIPE-DPRIO interface + txdeemph_int : OUT STD_LOGIC; + txmargin_int : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txswing_int : OUT STD_LOGIC + ); +END cycloneiv_hssi_q_pipe_interface_top; + +ARCHITECTURE trans OF cycloneiv_hssi_q_pipe_interface_top IS + COMPONENT cycloneiv_hssi_tx_pipe_interface + PORT ( + clk : IN STD_LOGIC; + refclk_b : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + refclk_b_reset_n : IN STD_LOGIC; + rtx_pipe_enable : IN STD_LOGIC; + rtx_elec_idle_delay : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rtxswing_sel_ena : IN STD_LOGIC; + txdetectrxloopback : IN STD_LOGIC; + txelecidle : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txdeemph : IN STD_LOGIC; + txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txswing : IN STD_LOGIC; + txd_ch : IN STD_LOGIC_VECTOR(43 DOWNTO 0); + revloopback : IN STD_LOGIC; + txd : OUT STD_LOGIC_VECTOR(43 DOWNTO 0); + rev_loopbk : OUT STD_LOGIC; + tx_elec_idle_comp : IN STD_LOGIC; + tx_elec_idle : OUT STD_LOGIC; + txdetectrx : OUT STD_LOGIC; + powerstate : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txdeemph_int : OUT STD_LOGIC; + txmargin_int : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txswing_int : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_phystatus_generator + PORT ( + clk : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + phystat_ena : IN STD_LOGIC; + rphystatus_rst_toggle : IN STD_LOGIC; + rphystatus_delay : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + phystatus : OUT STD_LOGIC; + latched_p0 : IN STD_LOGIC; + latched_p0s : IN STD_LOGIC; + latched_p1 : IN STD_LOGIC; + latched_p2 : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + speed_change : IN STD_LOGIC; + speed_change_centrl : IN STD_LOGIC; + speed_change_quad_up : IN STD_LOGIC; + speed_change_quad_down : IN STD_LOGIC; + rx_detect_valid : IN STD_LOGIC; + power_state_transition_done : IN STD_LOGIC; + power_state_transition_done_ena : IN STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_pipe_interface + PORT ( + clk : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rrdwidth_rx : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rind_error_reporting : IN STD_LOGIC; + rxpolarity : IN STD_LOGIC; + rxvalid : OUT STD_LOGIC; + rxelecidle : OUT STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rxd_ch : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + polinv_rx : IN STD_LOGIC; + rxd : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + polinv_rx_int : OUT STD_LOGIC; + latched_p1 : IN STD_LOGIC; + txdetectrx : IN STD_LOGIC; + rx_found : IN STD_LOGIC; + rx_found_sync : IN STD_LOGIC; + rx_detect_valid : IN STD_LOGIC; + rx_detect_valid_sync : IN STD_LOGIC; + sigdetni : IN STD_LOGIC; -- ww25_2008 + rxelectricalidle : IN STD_LOGIC + ); + END COMPONENT; + + + --******************************************************************************** + -- PARAMETERS + --******************************************************************************** + + --******************************************************************************** + -- DECLARATIONS + --******************************************************************************** + + SIGNAL phystat_ena : STD_LOGIC; + + SIGNAL rx_found_reg_0 : STD_LOGIC; + SIGNAL rx_found_reg_1 : STD_LOGIC; + + SIGNAL rx_detect_valid_reg_0 : STD_LOGIC; + SIGNAL rx_detect_valid_reg_1 : STD_LOGIC; + + SIGNAL tx_pipe_reset_n : STD_LOGIC; + SIGNAL rx_pipe_reset_n : STD_LOGIC; + SIGNAL refclk_b_reset_n : STD_LOGIC; -- reset for txelecidle_d_generator + + SIGNAL txdetectrx_reg_0 : STD_LOGIC; + SIGNAL txdetectrx_reg_1 : STD_LOGIC; + SIGNAL txdetectrx_reg_2 : STD_LOGIC; + SIGNAL txdetectrx_reg_3 : STD_LOGIC; + SIGNAL txdetectrx_reg_4 : STD_LOGIC; + SIGNAL txdetectrx_reg_5 : STD_LOGIC; + SIGNAL txdetectrx_reg_6 : STD_LOGIC; + + SIGNAL bypass_rx_found : STD_LOGIC; + SIGNAL bypass_rx_detect_valid : STD_LOGIC; + + SIGNAL rx_found_int : STD_LOGIC; + SIGNAL rx_detect_valid_int : STD_LOGIC; + + SIGNAL latched_p0 : STD_LOGIC; + SIGNAL latched_p0s : STD_LOGIC; + SIGNAL latched_p1 : STD_LOGIC; + SIGNAL latched_p2 : STD_LOGIC; + + SIGNAL p1_sync : STD_LOGIC; + + SIGNAL tmp_txdetectrxin : STD_LOGIC; --shawn + + -- Declare intermediate signals for referenced outputs + SIGNAL rxvalid_xhdl7 : STD_LOGIC; + SIGNAL rxelecidle_xhdl5 : STD_LOGIC; + SIGNAL rxstatus_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxd_ch_xhdl4 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL phystatus_xhdl0 : STD_LOGIC; + SIGNAL txd_xhdl9 : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL rev_loopbk_xhdl3 : STD_LOGIC; + SIGNAL polinv_rx_int_xhdl1 : STD_LOGIC; + SIGNAL tx_elec_idle_xhdl8 : STD_LOGIC; + SIGNAL txdetectrx_xhdl11 : STD_LOGIC; + SIGNAL powerstate_xhdl2 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txdeemph_int_xhdl10 : STD_LOGIC; + SIGNAL txmargin_int_xhdl12 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL txswing_int_xhdl13 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + rxvalid <= rxvalid_xhdl7; + rxelecidle <= rxelecidle_xhdl5; + rxstatus <= rxstatus_xhdl6; + rxd_ch <= rxd_ch_xhdl4; + phystatus <= phystatus_xhdl0; + txd <= txd_xhdl9; + rev_loopbk <= rev_loopbk_xhdl3; + polinv_rx_int <= polinv_rx_int_xhdl1; + tx_elec_idle <= tx_elec_idle_xhdl8; + txdetectrx <= txdetectrx_xhdl11; + powerstate <= powerstate_xhdl2; + txdeemph_int <= txdeemph_int_xhdl10; + txmargin_int <= txmargin_int_xhdl12; + txswing_int <= txswing_int_xhdl13; + + --******************************************************************************** + -- ASSIGN STATEMENTS + --******************************************************************************** + phystat_ena <= rtx_pipe_enable OR rrx_pipe_enable; + + tx_pipe_reset_n <= NOT(tx_pipe_reset); + rx_pipe_reset_n <= NOT(rx_pipe_reset); + refclk_b_reset_n <= NOT(refclk_b_reset); + + rx_found_int <= bypass_rx_found WHEN (rrx_detect_bypass = '1') ELSE + rx_found_reg_1; + rx_detect_valid_int <= bypass_rx_detect_valid WHEN (rrx_detect_bypass = '1') ELSE + rx_detect_valid_reg_1; + + tmp_txdetectrxin <= txdetectrxin WHEN (use_powerstatein = '1') ELSE --shawn + txdetectrx_xhdl11; + + latched_p0 <= powerstatein(0) WHEN (use_powerstatein = '1') ELSE --shawn + powerstate_xhdl2(0); + latched_p0s <= powerstatein(1) WHEN (use_powerstatein = '1') ELSE --shawn; + powerstate_xhdl2(1); + latched_p1 <= powerstatein(2) WHEN (use_powerstatein = '1') ELSE --shawn; + powerstate_xhdl2(2); + latched_p2 <= powerstatein(3) WHEN (use_powerstatein = '1') ELSE --shawn; + powerstate_xhdl2(3); + + --******************************************************************************** + -- SUBMODULE INSTANTIATIONS + --******************************************************************************** + + + + tx_pipe_interface_inst : cycloneiv_hssi_tx_pipe_interface + PORT MAP ( + + -- General signals + clk => pipe_tx_clk, + refclk_b => refclk_b, + reset_n => tx_pipe_reset_n, + refclk_b_reset_n => refclk_b_reset_n, + + -- CRAM + rtx_pipe_enable => rtx_pipe_enable, + rtx_elec_idle_delay => rtx_elec_idle_delay, + + rtxswing_sel_ena => rtxswing_sel_ena, + + -- PLD - PIPE Interface + -- TX PIPE Interface: Command + txdetectrxloopback => txdetectrxloopback, + txelecidle => txelecidle, + -- .txcompliance (txcompliance), + powerdown => powerdown, + + txdeemph => txdeemph, + txmargin => txmargin, + txswing => txswing, + + -- TX PIPE Interface: Data + txd_ch => txd_ch, + + -- Commands + revloopback => revloopback, + + -- PIPE - PCS Inteface + -- TX PIPE Interface + txd => txd_xhdl9, + rev_loopbk => rev_loopbk_xhdl3, + tx_elec_idle_comp => tx_elec_idle_comp, + + -- PIPE - PMA Interface + tx_elec_idle => tx_elec_idle_xhdl8, + txdetectrx => txdetectrx_xhdl11, + + -- Central PCS + powerstate => powerstate_xhdl2, + + -- PIPE - DPRIO + txdeemph_int => txdeemph_int_xhdl10, + txmargin_int => txmargin_int_xhdl12, + txswing_int => txswing_int_xhdl13 + ); + + + + rx_pipe_interface_inst : cycloneiv_hssi_rx_pipe_interface + PORT MAP ( + + -- General signals + clk => pipe_rx_clk, + reset_n => rx_pipe_reset_n, + + -- CRAM + rrx_pipe_enable => rrx_pipe_enable, + rrdwidth_rx => rrdwidth_rx, + rclkcmpinsertpad => rclkcmpinsertpad, + rind_error_reporting => rind_error_reporting, + + -- PLD - PIPE Interface + -- RX PIPE Interface: Command/Status + rxpolarity => rxpolarity, + + rxvalid => rxvalid_xhdl7, + rxelecidle => rxelecidle_xhdl5, + rxstatus => rxstatus_xhdl6, + + -- RX PIPE Interface: Data + rxd_ch => rxd_ch_xhdl4, + + -- Commands + polinv_rx => polinv_rx, + + -- PIPE - PCS Inteface + -- RX PIPE Interface + rxd => rxd, + polinv_rx_int => polinv_rx_int_xhdl1, + + -- TX PIPE Interface + -- Latched Power State Signals + latched_p1 => latched_p1, + + txdetectrx => tmp_txdetectrxin, --shawn (txdetectrx), + + -- PIPE - PMA Interface + -- TX PIPE Interface + rx_found => rx_found, + rx_found_sync => rx_found_int, + rx_detect_valid => rx_detect_valid, + rx_detect_valid_sync => rx_detect_valid_int, + + sigdetni => sigdetni, -- ww25_2008 + + -- RX PIPE Interface + rxelectricalidle => rxelectricalidle + ); + + + + phystatus_generator_inst : cycloneiv_hssi_phystatus_generator + PORT MAP ( + + -- General signals + clk => pipe_rx_clk, + reset_n => rx_pipe_reset_n, + + --CRAM + phystat_ena => phystat_ena, + rphystatus_rst_toggle => rphystatus_rst_toggle, + rphystatus_delay => rphystatus_delay, + + -- PLD Interface + powerdown => powerdown, + phystatus => phystatus_xhdl0, + + -- Latched Power State Signals + latched_p0 => latched_p0, + latched_p0s => latched_p0s, + latched_p1 => latched_p1, + latched_p2 => latched_p2, + + rindv_rx => rindv_rx, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + + -- Auto Negotiation Module + speed_change => speed_change, + speed_change_centrl => speed_change_centrl, + speed_change_quad_up => speed_change_quad_up, + speed_change_quad_down => speed_change_quad_down, + + -- TX PMA Interface + rx_detect_valid => rx_detect_valid_int, + + -- RX PMA Interface + power_state_transition_done => power_state_transition_done, + power_state_transition_done_ena => power_state_transition_done_ena + ); + + --******************************************************************************** + -- MAIN CODE + --******************************************************************************** + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + rx_detect_valid_reg_0 <= TRANSPORT '0' AFTER 1* 1 ps; + rx_found_reg_0 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + rx_detect_valid_reg_0 <= TRANSPORT rx_detect_valid AFTER 1* 1 ps; + rx_found_reg_0 <= TRANSPORT rx_found AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + rx_detect_valid_reg_1 <= TRANSPORT '0' AFTER 1* 1 ps; + rx_found_reg_1 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + rx_detect_valid_reg_1 <= TRANSPORT rx_detect_valid_reg_0 AFTER 1* 1 ps; + rx_found_reg_1 <= TRANSPORT rx_found_reg_0 AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + txdetectrx_reg_0 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + txdetectrx_reg_0 <= TRANSPORT tmp_txdetectrxin AFTER 1* 1 ps; -- txdetectrx; shawn + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + txdetectrx_reg_1 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + txdetectrx_reg_1 <= TRANSPORT txdetectrx_reg_0 AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + txdetectrx_reg_2 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + txdetectrx_reg_2 <= TRANSPORT txdetectrx_reg_1 AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + txdetectrx_reg_3 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + txdetectrx_reg_3 <= TRANSPORT txdetectrx_reg_2 AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + txdetectrx_reg_4 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + txdetectrx_reg_4 <= TRANSPORT txdetectrx_reg_3 AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + txdetectrx_reg_5 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + txdetectrx_reg_5 <= TRANSPORT txdetectrx_reg_4 AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + txdetectrx_reg_6 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + txdetectrx_reg_6 <= TRANSPORT txdetectrx_reg_5 AFTER 1* 1 ps; + END IF; + END PROCESS; + + PROCESS (pipe_rx_clk, rx_pipe_reset_n) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_pipe_reset_n)) = '1') THEN + bypass_rx_found <= TRANSPORT '0' AFTER 1* 1 ps; + bypass_rx_detect_valid <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (pipe_rx_clk'EVENT AND pipe_rx_clk = '1') THEN + bypass_rx_found <= TRANSPORT txdetectrx_reg_6 AFTER 1* 1 ps; + bypass_rx_detect_valid <= TRANSPORT txdetectrx_reg_6 AFTER 1* 1 ps; + END IF; + END PROCESS; + +END trans; + + + +-- pipe_interface_top + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_tx_digis_txclk_gating IS + PORT ( + + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); +END cycloneiv_hssi_tx_digis_txclk_gating; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_digis_txclk_gating IS +BEGIN + + clk1out_n <= NOT((select_n OR clk1)); + clk2out_n <= NOT((NOT(select_n) OR clk2)); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_tx_digi_txclk_ctl IS + PORT ( + + -- Clock Inputs + pld_tx_clk : IN STD_LOGIC; -- PLD clock from PLD clock trees, the transmit clock from XGMII. + refclk_pma : IN STD_LOGIC; -- Quad based clk from TXPLL + txpma_local_clk : IN STD_LOGIC; -- Local channel TX PMA clock. + + -- Control Inputs + txrst : IN STD_LOGIC; -- reset for the tx_pcs + scan_mode : IN STD_LOGIC; -- Scan mode enable signal for selecting scan_clk from refclk_pma + + -- New Control Inputs + gen2ngen1 : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling + gen2ngen1_bundle : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 + tx_div2_sync_centrl : IN STD_LOGIC; -- divided clock from the central channel (x2, x4 mode) + tx_div2_sync_quad_up : IN STD_LOGIC; -- divided clock from quad above (> x4 mode) + tx_div2_sync_quad_down : IN STD_LOGIC; -- divided clock from quad below (> x4 mode) + + -- MDIO Inputs + rindv_tx : IN STD_LOGIC; -- Selects between indiv chan. mode and bundled mode + rtxwrclksel : IN STD_LOGIC; -- Selects which clock writes into FIFO + rtxrdclksel : IN STD_LOGIC; -- Selects which clock reads from FIFO and also clocks reest of TX logic + rdwidth_tx : IN STD_LOGIC; -- divide by 1 or 2 before feeding to FIFO read clock + rfreerun_tx : IN STD_LOGIC; -- Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by TX PCS reset + + -- New MDIO Inputs + rauto_speed_ena : IN STD_LOGIC; -- auto speed negotiation enable + rfreq_sel : IN STD_LOGIC; -- freq scaling or data width scaling + rtxpcsclkpwdn : IN STD_LOGIC; -- TX clocking power down enable + rmaster_tx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rmaster_up_tx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rself_sw_en_tx : IN STD_LOGIC; -- enables self-switch to have correct /2 clock in all quads in bundle mode + + -- Removed Inputs + -- input tx_div2_sync_in_ch0; // from the channel zero tx_div2_sync_out + -- input tx_div2_sync_in_q0_ch0; // From channel0 of Master Quad + -- input rphfifo_master_sel_tx; // TX Phase comp. FIFO tx_div2_sync selection CRAM + + -- Clock Outputs wtih CTS + refclk_b : OUT STD_LOGIC; -- Drives the tx channel clock + wr_clk_pos : OUT STD_LOGIC; -- Drives tx phase comp fifo write side + fifo_rd_clk : OUT STD_LOGIC; -- Drives tx phase comp fifo read side + + -- Clock Outputs to PLD, w/o CTS + tx_clk_out : OUT STD_LOGIC; -- Drives to the PLD clock tree -- unconnected + + -- New Clock Outputs with CTS + refclk_b_raw : OUT STD_LOGIC; -- same as refclk_b, but with no clock gating + wr_clk_pos_raw : OUT STD_LOGIC; -- same as wr_clk_pos, but with no clock gating + fifo_rd_clk_raw : OUT STD_LOGIC; -- same as fifo_rd_clk, but with no clock gating + + -- Control Outputs + tx_div2_sync_out : OUT STD_LOGIC -- Synchronizes the divided by two clock + ); +END cycloneiv_hssi_tx_digi_txclk_ctl; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_digi_txclk_ctl IS + COMPONENT cycloneiv_hssi_tx_digis_txclk_gating + PORT ( + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL fifo_rd_clk_by2 : STD_LOGIC := '0'; + SIGNAL gen2ngen1_local_sync : STD_LOGIC; + SIGNAL counter : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL tx_rst_n : STD_LOGIC; + SIGNAL tx_div2_sync : STD_LOGIC; + SIGNAL dynamic_div2ndiv1 : STD_LOGIC; + SIGNAL gen2ngen1_local : STD_LOGIC; + SIGNAL tx_div2_this_quad : STD_LOGIC; + SIGNAL tx_div2_this_channel : STD_LOGIC; + SIGNAL tx_div2_other_quad : STD_LOGIC; + SIGNAL force_master : STD_LOGIC; + SIGNAL rtxpcsclkpwdn_nscan : STD_LOGIC; + + SIGNAL select_div1_n : STD_LOGIC; + SIGNAL clk1out_n : STD_LOGIC; + SIGNAL clk2out_n : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL fifo_rd_clk_xhdl0 : STD_LOGIC; + SIGNAL refclk_b_raw_xhdl2 : STD_LOGIC; + SIGNAL wr_clk_pos_raw_xhdl4 : STD_LOGIC; + SIGNAL fifo_rd_clk_raw_xhdl1 : STD_LOGIC; + SIGNAL tx_div2_sync_out_xhdl3 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + fifo_rd_clk <= fifo_rd_clk_xhdl0; + refclk_b_raw <= refclk_b_raw_xhdl2; + wr_clk_pos_raw <= wr_clk_pos_raw_xhdl4; + fifo_rd_clk_raw <= fifo_rd_clk_raw_xhdl1; + tx_div2_sync_out <= tx_div2_sync_out_xhdl3; + + + -- Old bundle logic: + -- Select between the local synchronization signal or the global synchronization signal (either from Channel0 or + -- Channel0 of Master Quad + --assign tx_div2_sync = rindv_tx ? tx_div2_sync_out : tx_div2_sync_in; + -- assign tx_div2_sync = (rphfifo_master_sel_tx == 1'b0) ? tx_div2_sync_in_q0_ch0 : + -- (rindv_tx == 1'b0) ? tx_div2_sync_in_ch0 : + -- (rauto_speed_ena & ~rfreq_sel) ? (tx_div2_sync_out | ~gen2ngen1_local_sync) : tx_div2_sync_out; + + PROCESS (txrst, refclk_b_raw_xhdl2) +VARIABLE txt : LINE; + BEGIN + IF (txrst = '1') THEN + counter <= TRANSPORT "00" AFTER 1* 1 ps; + ELSIF (refclk_b_raw_xhdl2'EVENT AND refclk_b_raw_xhdl2 = '1') THEN + IF (((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_tx) AND NOT(force_master)) = '1') THEN + counter <= TRANSPORT counter + "01" AFTER 1* 1 ps; + END IF; + END IF; + END PROCESS; + + force_master <= '1' WHEN ((counter = "11") AND ((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_tx) = '1')) ELSE + '0'; + + tx_div2_sync <= tx_div2_this_quad WHEN ((rmaster_tx OR force_master) = '1') ELSE + tx_div2_other_quad; + tx_div2_this_quad <= tx_div2_this_channel WHEN ((rindv_tx OR force_master) = '1') ELSE + tx_div2_sync_centrl; + tx_div2_this_channel <= (tx_div2_sync_out_xhdl3 OR NOT(gen2ngen1_local_sync)) WHEN ((rauto_speed_ena AND NOT(rfreq_sel)) = '1') ELSE + tx_div2_sync_out_xhdl3; + tx_div2_other_quad <= tx_div2_sync_quad_up WHEN (rmaster_up_tx = '1') ELSE + tx_div2_sync_quad_down; + + gen2ngen1_local <= gen2ngen1_bundle WHEN (rindv_tx = '0') ELSE + gen2ngen1; + + PROCESS (txrst, refclk_b_raw_xhdl2) +VARIABLE txt : LINE; + BEGIN + IF (txrst = '1') THEN + gen2ngen1_local_sync <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk_b_raw_xhdl2'EVENT AND refclk_b_raw_xhdl2 = '1') THEN + gen2ngen1_local_sync <= TRANSPORT gen2ngen1_local AFTER 1* 1 ps; + END IF; + END PROCESS; + + dynamic_div2ndiv1 <= rdwidth_tx OR (gen2ngen1_local_sync AND rauto_speed_ena AND NOT(rfreq_sel)); + + -- Reset for Divide-by-2 FF + tx_rst_n <= '1' WHEN (rfreerun_tx = '1') ELSE + NOT(txrst); + + rtxpcsclkpwdn_nscan <= rtxpcsclkpwdn AND NOT(scan_mode); + + -- Full speed clock for TX PCS + refclk_b_raw_xhdl2 <= refclk_pma WHEN ((scan_mode OR rtxrdclksel) = '1') ELSE + txpma_local_clk; + + refclk_b <= '1' WHEN (rtxpcsclkpwdn_nscan = '1') ELSE + refclk_b_raw_xhdl2; + + -- Divide-by-2 FF + PROCESS (tx_rst_n, refclk_b_raw_xhdl2) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(tx_rst_n)) = '1') THEN + fifo_rd_clk_by2 <= '1'; + ELSIF (refclk_b_raw_xhdl2'EVENT AND refclk_b_raw_xhdl2 = '1') THEN + fifo_rd_clk_by2 <= tx_div2_sync; -- local divided clock + END IF; + END PROCESS; + + tx_div2_sync_out_xhdl3 <= NOT(fifo_rd_clk_by2); + + -- TX FIFO read clock: could be fast or divided by 2 + -- old code: + -- assign fifo_rd_clk = ((rdwidth_tx == 1'b0) || scan_mode) ? refclk_b_raw : fifo_rd_clk_by2; + + select_div1_n <= NOT((scan_mode OR NOT(dynamic_div2ndiv1))); + + cycloneiv_hssi_tx_digis_txclk_gating_inst : cycloneiv_hssi_tx_digis_txclk_gating + PORT MAP ( + select_n => select_div1_n, + clk1 => refclk_b_raw_xhdl2, + clk2 => fifo_rd_clk_by2, + clk1out_n => clk1out_n, + clk2out_n => clk2out_n + ); + + fifo_rd_clk_raw_xhdl1 <= NOT (clk1out_n OR clk2out_n); + + fifo_rd_clk_xhdl0 <= '1' WHEN (rtxpcsclkpwdn_nscan = '1') ELSE + fifo_rd_clk_raw_xhdl1; + + -- TX FIFO write clock: used internal clock when in BIST or scan or HIP + wr_clk_pos_raw_xhdl4 <= fifo_rd_clk_raw_xhdl1 WHEN ((scan_mode OR rtxwrclksel) = '1') ELSE + pld_tx_clk; + wr_clk_pos <= '1' WHEN (rtxpcsclkpwdn_nscan = '1') ELSE + wr_clk_pos_raw_xhdl4; + + -- TX Clock Out + tx_clk_out <= fifo_rd_clk_xhdl0; -- drives PLD clock tree + +END trans; + + + + +-- txclk_ctl + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_tx_digis_ram8x49_syn IS + GENERIC ( + + read_access_time : INTEGER := 0; + write_access_time : INTEGER := 0; + ram_width : INTEGER := 54 + ); + PORT ( + data_in : IN STD_LOGIC_VECTOR(53 DOWNTO 0); + clk : IN STD_LOGIC; + fifo_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rst_l : IN STD_LOGIC; + fifo_re : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR(53 DOWNTO 0) + ); +END cycloneiv_hssi_tx_digis_ram8x49_syn; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_digis_ram8x49_syn IS + + SIGNAL data_out_i : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + + SIGNAL data_reg_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + + SIGNAL we : STD_LOGIC; + SIGNAL re_l : STD_LOGIC; +BEGIN + + we <= '1'; + re_l <= '0'; + + data_reg_0 <= data_in WHEN (fifo_wr(0) = '1') ELSE + ram_array_q_0; + data_reg_1 <= data_in WHEN (fifo_wr(1) = '1') ELSE + ram_array_q_1; + data_reg_2 <= data_in WHEN (fifo_wr(2) = '1') ELSE + ram_array_q_2; + data_reg_3 <= data_in WHEN (fifo_wr(3) = '1') ELSE + ram_array_q_3; + data_reg_4 <= data_in WHEN (fifo_wr(4) = '1') ELSE + ram_array_q_4; + data_reg_5 <= data_in WHEN (fifo_wr(5) = '1') ELSE + ram_array_q_5; + data_reg_6 <= data_in WHEN (fifo_wr(6) = '1') ELSE + ram_array_q_6; + data_reg_7 <= data_in WHEN (fifo_wr(7) = '1') ELSE + ram_array_q_7; + + data_out <= "100001000000000000000000000000000000000000000000000000" WHEN (re_l = '1') ELSE + data_out_i; + + PROCESS (ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, fifo_re) +VARIABLE txt : LINE; + BEGIN + CASE fifo_re IS -- synopsys parallel_case full_case + WHEN "00000001" => + data_out_i <= ram_array_q_0; + WHEN "00000010" => + data_out_i <= ram_array_q_1; + WHEN "00000100" => + data_out_i <= ram_array_q_2; + WHEN "00001000" => + data_out_i <= ram_array_q_3; + WHEN "00010000" => + data_out_i <= ram_array_q_4; + WHEN "00100000" => + data_out_i <= ram_array_q_5; + WHEN "01000000" => + data_out_i <= ram_array_q_6; + WHEN "10000000" => + data_out_i <= ram_array_q_7; + WHEN OTHERS => + data_out_i <= ram_array_q_0; + END CASE; + END PROCESS; + + + PROCESS (clk, rst_l) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rst_l)) = '1') THEN + ram_array_q_0 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_1 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_2 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_3 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_4 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_5 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_6 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_7 <= TRANSPORT "100001000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + ram_array_q_0 <= TRANSPORT ram_array_d_0 AFTER (write_access_time)*1 ps; + ram_array_q_1 <= TRANSPORT ram_array_d_1 AFTER (write_access_time)*1 ps; + ram_array_q_2 <= TRANSPORT ram_array_d_2 AFTER (write_access_time)*1 ps; + ram_array_q_3 <= TRANSPORT ram_array_d_3 AFTER (write_access_time)*1 ps; + ram_array_q_4 <= TRANSPORT ram_array_d_4 AFTER (write_access_time)*1 ps; + ram_array_q_5 <= TRANSPORT ram_array_d_5 AFTER (write_access_time)*1 ps; + ram_array_q_6 <= TRANSPORT ram_array_d_6 AFTER (write_access_time)*1 ps; + ram_array_q_7 <= TRANSPORT ram_array_d_7 AFTER (write_access_time)*1 ps; + END IF; + END PROCESS; + + + PROCESS (we, data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7) +VARIABLE txt : LINE; + BEGIN + IF (we = '1') THEN + ram_array_d_0 <= data_reg_0; + ram_array_d_1 <= data_reg_1; + ram_array_d_2 <= data_reg_2; + ram_array_d_3 <= data_reg_3; + ram_array_d_4 <= data_reg_4; + ram_array_d_5 <= data_reg_5; + ram_array_d_6 <= data_reg_6; + ram_array_d_7 <= data_reg_7; + ELSE + ram_array_d_0 <= ram_array_q_0; + ram_array_d_1 <= ram_array_q_1; + ram_array_d_2 <= ram_array_q_2; + ram_array_d_3 <= ram_array_q_3; + ram_array_d_4 <= ram_array_q_4; + ram_array_d_5 <= ram_array_q_5; + ram_array_d_6 <= ram_array_q_6; + ram_array_d_7 <= ram_array_q_7; + END IF; + END PROCESS; + + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_tx_digis_ph_fifo IS + PORT ( + -- inputs + --en, + -- outputs + + -- ======= + -- inputs + -- ======= + rst_wclk : IN STD_LOGIC; -- wr clk rst + rst_rclk : IN STD_LOGIC; -- rd clk rst + wr_clk : IN STD_LOGIC; -- Write Clock + rd_clk : IN STD_LOGIC; -- Read Clock + bypass_en : IN STD_LOGIC; -- FIFO bypass enable - only for Altera internal debug + --input en; // Disable FIFO, reset wptr and rptr + -- only for Altera internal debug + lowlatency_en : IN STD_LOGIC; -- Enable low latency option + we : IN STD_LOGIC; -- PLD dynamic write pointer enable + re : IN STD_LOGIC; -- PLD dynamic read pointer enable + din : IN STD_LOGIC_VECTOR(53 DOWNTO 0); -- 10-bit code-group bus from deskew module. + + rphfifo_regmode_tx : IN STD_LOGIC; + rindv_tx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + + -- ======= + -- outputs + -- ======= + -- Indicates overflow (rd_clk) + -- FIFO empty (rd_clk) + data_out : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- output data (rd_clk synchronous if not FIFO bypass) + ph_fifo_full : OUT STD_LOGIC; + ph_fifo_empty : OUT STD_LOGIC; + wptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- wptr test bus + rptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) -- rptr test bus + ); +END cycloneiv_hssi_tx_digis_ph_fifo; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_digis_ph_fifo IS + COMPONENT cycloneiv_hssi_tx_digis_ram8x49_syn + GENERIC ( + read_access_time : INTEGER := 0; + write_access_time : INTEGER := 0; + ram_width : INTEGER := 54 + ); + PORT ( + data_in : IN STD_LOGIC_VECTOR(53 DOWNTO 0); + clk : IN STD_LOGIC; + fifo_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rst_l : IN STD_LOGIC; + fifo_re : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR(53 DOWNTO 0) + ); + END COMPONENT; + + + -- =================== + -- signal declaration + -- =================== + SIGNAL wptr : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000" ; + SIGNAL rptr : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000" ; + SIGNAL wptr0_pre : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000" ; + SIGNAL wptr0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000" ; + SIGNAL wptr1 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000" ; + SIGNAL rptr_gray : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ; + SIGNAL rptr_gray0 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rptr0 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ; + SIGNAL rptr1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ; + SIGNAL rptr1_onehot : STD_LOGIC_VECTOR(7 DOWNTO 0); + -- wptr test bus + -- rptr test bus + SIGNAL first_rd : STD_LOGIC; -- first read after reset + SIGNAL ram_data_out : STD_LOGIC_VECTOR(53 DOWNTO 0); + SIGNAL ram_data_out_pre : STD_LOGIC_VECTOR(53 DOWNTO 0); + + SIGNAL ph_fifo_full_pre : STD_LOGIC; + + -- Invert rst for new FIFO + SIGNAL rst_n : STD_LOGIC; + + SIGNAL fifo_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL fifo_cnt_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wptr1_bin : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rptr1_bin_wclk : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL reset_ptrs_local : STD_LOGIC; + + SIGNAL reset_ptrs_local_sync1 : STD_LOGIC; + SIGNAL reset_ptrs_local_sync2 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL ph_fifo_empty_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + ph_fifo_empty <= ph_fifo_empty_xhdl0; + + -- ============= + -- functionality + -- ============= + rst_n <= NOT(rst_wclk); + + data_out(53 DOWNTO 0) <= din WHEN (bypass_en = '1') ELSE + ram_data_out; + + reset_ptrs_local <= rauto_speed_ena AND reset_pc_ptrs WHEN (rindv_tx = '1') ELSE + reset_pc_ptrs_centrl WHEN (rmaster_tx = '1') ELSE + reset_pc_ptrs_quad_up WHEN (rmaster_up_tx = '1') ELSE + reset_pc_ptrs_quad_down; + + --newly added fifo_cnt and fifo_cnt_pre logic for full/empty flag use + -- manually translated + PROCESS(fifo_cnt_pre, rst_wclk, rptr1_bin_wclk, wptr1_bin) + BEGIN + IF (rptr1_bin_wclk = wptr1_bin) THEN + IF (rst_wclk /= '1') THEN + IF (fifo_cnt_pre = "0111" OR fifo_cnt_pre = "0110" OR fifo_cnt_pre = "1000") THEN + fifo_cnt <= "1000"; + ELSE + fifo_cnt <= "0000"; + END IF; + ELSE + fifo_cnt <= "0000"; + END IF; + ELSE + IF (wptr1_bin > rptr1_bin_wclk) THEN + fifo_cnt <= ('0' & (wptr1_bin - rptr1_bin_wclk)); + ELSE + fifo_cnt <= ("1000" - ('0' & (rptr1_bin_wclk - wptr1_bin))); + END IF; + END IF; + END PROCESS; + + --newly added fifo_cnt and fifo_cnt_pre logic for full/empty flag use + -- incorrect translation - replaced above section + --fifo_cnt <= "1000" WHEN (fifo_cnt_pre = "0111" OR fifo_cnt_pre = "0110" OR fifo_cnt_pre = "1000") ELSE + -- "0000" WHEN (rst_wclk /= '1') ELSE + -- "0000" WHEN (wptr1_bin = rptr1_bin_wclk) ELSE + -- ('0' & (wptr1_bin - rptr1_bin_wclk)) WHEN (wptr1_bin > rptr1_bin_wclk) ELSE + -- ("1000" - ('0' & (rptr1_bin_wclk - wptr1_bin))); + + PROCESS (rst_wclk, wr_clk) +VARIABLE txt : LINE; + BEGIN + IF (rst_wclk = '1') THEN + reset_ptrs_local_sync1 <= TRANSPORT '0' AFTER 1 ps; + reset_ptrs_local_sync2 <= TRANSPORT '0' AFTER 1 ps; + ELSIF (wr_clk'EVENT AND wr_clk = '1') THEN + IF (rphfifo_regmode_tx = '1') THEN + reset_ptrs_local_sync1 <= TRANSPORT '0' AFTER 1 ps; + reset_ptrs_local_sync2 <= TRANSPORT '0' AFTER 1 ps; + ELSE + reset_ptrs_local_sync1 <= TRANSPORT reset_ptrs_local AFTER 1 ps; + reset_ptrs_local_sync2 <= TRANSPORT reset_ptrs_local_sync1 AFTER 1 ps; + END IF; + END IF; + END PROCESS; -- always @ (posedge rst_wclk or posedge wr_clk) + + --ECO for S4GX to fix metastability issue + -- replace the 1st FF with new flop w/o reset + -- replace the 2nd FF with an enhanced flop + PROCESS (wr_clk) + BEGIN + IF (wr_clk'EVENT AND wr_clk = '1') THEN + IF (reset_ptrs_local_sync2 = '1' OR rphfifo_regmode_tx = '1') THEN + rptr0 <= TRANSPORT "000" AFTER 1 ps; + ELSE + rptr0 <= TRANSPORT rptr_gray(2 DOWNTO 0) AFTER 1 ps; + END IF; + END IF; + END PROCESS; -- always @ (posedge rst_wclk or posedge wr_clk) + + PROCESS(rst_wclk, wr_clk) + BEGIN + IF (rst_wclk = '1') THEN + rptr1 <= TRANSPORT "000" AFTER 1 ps; + ELSIF (wr_clk'EVENT AND wr_clk = '1') THEN + IF ((reset_ptrs_local_sync2 OR rphfifo_regmode_tx) = '1') THEN + rptr1 <= TRANSPORT "000" AFTER 1 ps; + ELSE + rptr1 <= TRANSPORT rptr0 AFTER 1 ps; + END IF; + END IF; + END PROCESS; -- always @ (posedge rst_wclk or posedge wr_clk) + + PROCESS (rst_wclk, wr_clk) +VARIABLE txt : LINE; + BEGIN + IF (rst_wclk = '1') THEN + wptr <= TRANSPORT "00000001" AFTER 1 ps; + wptr0_pre <= TRANSPORT "00000001" AFTER 1 ps; + wptr0 <= TRANSPORT "00000001" AFTER 1 ps; + wptr1 <= TRANSPORT "00000001" AFTER 1 ps; + --rptr0 <= TRANSPORT "000" AFTER 1 ps; + --rptr1 <= TRANSPORT "000" AFTER 1 ps; + ph_fifo_full_pre <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_full <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_empty_xhdl0 <= TRANSPORT '0' AFTER 1 ps; -- fifo_cnt previous value + fifo_cnt_pre <= TRANSPORT "0000" AFTER 1 ps; -- if (rst_wclk == 1'b1) + ELSIF (wr_clk'EVENT AND wr_clk = '1') THEN + IF ((reset_ptrs_local_sync2 OR rphfifo_regmode_tx) = '1') THEN + wptr <= TRANSPORT "00000001" AFTER 1 ps; + wptr0_pre <= TRANSPORT "00000001" AFTER 1 ps; + wptr0 <= TRANSPORT "00000001" AFTER 1 ps; + wptr1 <= TRANSPORT "00000001" AFTER 1 ps; + --rptr0 <= TRANSPORT "000" AFTER 1 ps; + --rptr1 <= TRANSPORT "000" AFTER 1 ps; + ph_fifo_full_pre <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_full <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_empty_xhdl0 <= TRANSPORT '0' AFTER 1 ps; -- fifo_cnt previous value + fifo_cnt_pre <= TRANSPORT "0000" AFTER 1 ps; -- if (reset_ptrs_local_sync2) + ELSE + + fifo_cnt_pre <= TRANSPORT fifo_cnt AFTER 1 ps; + ph_fifo_full <= TRANSPORT ph_fifo_full_pre AFTER 1 ps; + wptr0_pre <= TRANSPORT wptr AFTER 1 ps; + wptr0 <= TRANSPORT wptr0_pre AFTER 1 ps; + wptr1 <= TRANSPORT wptr0 AFTER 1 ps; + + --rptr0 <= TRANSPORT rptr_gray(2 DOWNTO 0) AFTER 1 ps; + --rptr1 <= TRANSPORT rptr0 AFTER 1 ps; + + -- wptr operation + IF (we = '1') THEN + + -- full condition + --$if ({wptr1[6:0],wptr1[7]} == rptr1_onehot) + --new full flag requirement + wptr <= TRANSPORT (wptr(6 DOWNTO 0) & wptr(7)) AFTER 1 ps; + END IF; + IF ((fifo_cnt = "1000") AND ((NOT(ph_fifo_empty_xhdl0))) = '1') THEN + --else if (ph_fifo_full_pre == 1'b1 & (wptr1 != rptr1_onehot)) //now become sticky flag until reset + --ph_fifo_full_pre <= #1 1'b0; + + -- empty condition + --$if ({rptr1_onehot[6:0],rptr1_onehot[7]} == wptr1) + --new empty flag requirement + ph_fifo_full_pre <= TRANSPORT '1' AFTER 1 ps; --==1 to cover if wptr not moving + END IF; + IF ((((wptr1(6 DOWNTO 0)) & (wptr1(7))) = rptr1_onehot) AND (fifo_cnt_pre = "0001" OR fifo_cnt_pre = "0000") AND ((NOT(ph_fifo_full_pre))) = '1') THEN + --else if (ph_fifo_empty == 1'b1 & ({wptr1[6:0],wptr1[7]} != rptr1_onehot)) //now become sticky flag until reset + --ph_fifo_empty <= #1 1'b0; + ph_fifo_empty_xhdl0 <= TRANSPORT '1' AFTER 1 ps; + END IF; + END IF; + END IF; + END PROCESS; -- always @ (posedge rst_wclk or posedge wr_clk) + -- end of eco + + PROCESS (rst_rclk, rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (rst_rclk = '1') THEN + first_rd <= TRANSPORT '1' AFTER 1 ps; + rptr <= TRANSPORT "00100000" AFTER 1 ps; + ELSIF (rd_clk'EVENT AND rd_clk = '1') THEN + IF ((reset_ptrs_local OR rphfifo_regmode_tx) = '1') THEN + first_rd <= TRANSPORT '1' AFTER 1 ps; + rptr <= TRANSPORT "00100000" AFTER 1 ps; + ELSE + + IF (first_rd = '1' AND re = '1') THEN + + -- read pointer operation + first_rd <= TRANSPORT '0' AFTER 1 ps; + END IF; + IF (re = '1') THEN + -- low latency option, advance 2 on the first read + IF (first_rd = '1' AND lowlatency_en = '1') THEN + rptr <= TRANSPORT (rptr(5 DOWNTO 0) & rptr(7 DOWNTO 6)) AFTER 1 ps; + ELSE + rptr <= TRANSPORT (rptr(6 DOWNTO 0) & rptr(7)) AFTER 1 ps; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge rst_rclk or posedge rd_clk) + + -- Instantiate FIFO CORE Module. Fifo 8 words deep, 44 bits wide + + + + ram8x49_syn_1 : cycloneiv_hssi_tx_digis_ram8x49_syn + PORT MAP ( + rst_l => rst_n, + clk => wr_clk, + fifo_wr => wptr, + data_in => din, + fifo_re => rptr, + data_out => ram_data_out_pre + ); + + PROCESS (rst_rclk, rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (rst_rclk = '1') THEN + ram_data_out <= TRANSPORT "100000000000000000000000000000000000000000000000000000" AFTER 1 ps; + ELSIF (rd_clk'EVENT AND rd_clk = '1') THEN + IF (rphfifo_regmode_tx = '1') THEN + ram_data_out <= TRANSPORT din AFTER 1 ps; + ELSE + ram_data_out <= TRANSPORT ram_data_out_pre AFTER 1 ps; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge rst_rclk or posedge rd_clk) + + PROCESS (wptr) +VARIABLE txt : LINE; + BEGIN + CASE wptr IS + WHEN "00000001" => + wptr_bin <= "000"; + WHEN "00000010" => + wptr_bin <= "001"; + WHEN "00000100" => + wptr_bin <= "010"; + WHEN "00001000" => + wptr_bin <= "011"; + WHEN "00010000" => + wptr_bin <= "100"; + WHEN "00100000" => + wptr_bin <= "101"; + WHEN "01000000" => + wptr_bin <= "110"; + WHEN "10000000" => + wptr_bin <= "111"; + WHEN OTHERS => -- case(wptr) + wptr_bin <= "111"; + END CASE; + END PROCESS; + + -- always@ (wptr) + + PROCESS (wptr1) +VARIABLE txt : LINE; + BEGIN + CASE wptr1 IS + WHEN "00000001" => + wptr1_bin <= "000"; + WHEN "00000010" => + wptr1_bin <= "001"; + WHEN "00000100" => + wptr1_bin <= "010"; + WHEN "00001000" => + wptr1_bin <= "011"; + WHEN "00010000" => + wptr1_bin <= "100"; + WHEN "00100000" => + wptr1_bin <= "101"; + WHEN "01000000" => + wptr1_bin <= "110"; + WHEN "10000000" => + wptr1_bin <= "111"; + WHEN OTHERS => -- case(wptr1) + wptr1_bin <= "111"; + END CASE; + END PROCESS; + + -- always@ (wptr1) + + PROCESS (rptr) +VARIABLE txt : LINE; + BEGIN + CASE rptr IS + WHEN "00000001" => + rptr_bin <= "000"; + WHEN "00000010" => + rptr_bin <= "001"; + WHEN "00000100" => + rptr_bin <= "010"; + WHEN "00001000" => + rptr_bin <= "011"; + WHEN "00010000" => + rptr_bin <= "100"; + WHEN "00100000" => + rptr_bin <= "101"; + WHEN "01000000" => + rptr_bin <= "110"; + WHEN "10000000" => + rptr_bin <= "111"; + WHEN OTHERS => -- case(rptr) + rptr_bin <= "111"; + END CASE; + END PROCESS; + + -- always@ (rptr) + + PROCESS (rst_rclk, rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (rst_rclk = '1') THEN + rptr_gray <= TRANSPORT "000" AFTER 1 ps; + ELSIF (rd_clk'EVENT AND rd_clk = '1') THEN + rptr_gray <= TRANSPORT rptr_gray0 AFTER 1 ps; + END IF; + END PROCESS; + + + PROCESS (rptr) +VARIABLE txt : LINE; + BEGIN + CASE rptr IS + WHEN "00000001" => + rptr_gray0 <= "000"; + WHEN "00000010" => + rptr_gray0 <= "001"; + WHEN "00000100" => + rptr_gray0 <= "011"; + WHEN "00001000" => + rptr_gray0 <= "010"; + WHEN "00010000" => + rptr_gray0 <= "110"; + WHEN "00100000" => + rptr_gray0 <= "111"; + WHEN "01000000" => + rptr_gray0 <= "101"; + WHEN "10000000" => + rptr_gray0 <= "100"; + WHEN OTHERS => -- case(rptr) + rptr_gray0 <= "000"; + END CASE; + END PROCESS; + + -- always@ (rptr) + + PROCESS (rptr1) +VARIABLE txt : LINE; + BEGIN + CASE rptr1 IS + WHEN "000" => + rptr1_onehot <= "00000001"; + WHEN "001" => + rptr1_onehot <= "00000010"; + WHEN "011" => + rptr1_onehot <= "00000100"; + WHEN "010" => + rptr1_onehot <= "00001000"; + WHEN "110" => + rptr1_onehot <= "00010000"; + WHEN "111" => + rptr1_onehot <= "00100000"; + WHEN "101" => + rptr1_onehot <= "01000000"; + WHEN "100" => + rptr1_onehot <= "10000000"; + WHEN OTHERS => -- case(rptr1) + rptr1_onehot <= "00000001"; + END CASE; + END PROCESS; + + -- always@ (rptr1) + + PROCESS (rptr1) +VARIABLE txt : LINE; + BEGIN + CASE rptr1 IS + WHEN "000" => + rptr1_bin_wclk <= "000"; + WHEN "001" => + rptr1_bin_wclk <= "001"; + WHEN "011" => + rptr1_bin_wclk <= "010"; + WHEN "010" => + rptr1_bin_wclk <= "011"; + WHEN "110" => + rptr1_bin_wclk <= "100"; + WHEN "111" => + rptr1_bin_wclk <= "101"; + WHEN "101" => + rptr1_bin_wclk <= "110"; + WHEN "100" => + rptr1_bin_wclk <= "111"; + WHEN OTHERS => -- case(rptr1) + rptr1_bin_wclk <= "000"; + END CASE; + END PROCESS; + + +END trans; + + +-- always@ (rptr1) + + +-- ph_fifo_tx + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_tx_digi_tx_ctrl IS + PORT ( + -- inputs + --is_lane0, + -- PCS bypass + + -- TX PIPE signals + + -- RX PIPE signals + + -- New inputs for new bundling scheme and new PCIE features like autospeed + + -- New MDIO for new bundling scheme and new PCIE features like autospeed + + -- outputs + + -- TX PIPE signals + + -- RX PIPE signals + + -- test bus + -- fifo_select_out // test_bus[8], bit re-used in test bus + -- test_bus[7] + -- test_bus[6:4] + -- test_bus[3] + -- test_bus[2:0] + -- *_xgmii = from XGMII interface + -- *_sg = from selftest_gen + -- *_rc = from rx_ctrl + + -- ====== + -- inputs + -- ====== + soft_reset : IN STD_LOGIC; -- Reset + fifo_wr_clk : IN STD_LOGIC; -- Used to be wr_clk_pos + fifo_rd_clk : IN STD_LOGIC; -- Coming from txclk_xg_ctl + refclk_b_in : IN STD_LOGIC; -- The local reference clock used by the internal + -- transmit logic. Used to be tx_clk. + scan_mode : IN STD_LOGIC; -- scan enable + -- Control bit/pin to enable parallel loop back at XGMII + -- To select XGMII signals from selftest_gen (*_sg) + -- Control bit to support double-width data bus on xgmii. + -- When set, fifo_wr_clk is running at half frequency + -- as refclk_b_in and 2-byte/code-group of data should be sampled + -- at the rising edge of fifo_wr_clk. When DWIDTH=1'b0, the + -- fifo_wr_clk is running at the same frequency as refclk_b_in. + rindv_tx : IN STD_LOGIC; + p_rlpbk : IN STD_LOGIC; + selftest_en : IN STD_LOGIC; + rdwidth_tx : IN STD_LOGIC; + --input is_lane0; // lane 0 of the quad + -- rx data from rx_ctrl. + txfifo_dis : IN STD_LOGIC; + + -- Tx data + -- These extension bits may be used to force disparity or other uses. + -- Extend txd by 2 bits. Used to force disparity. + -- The xgmii data from selftest_gen.. + -- The xgmii control from selftest_gen. + -- redundant Tx data , unused + -- redundant Tx data select, unused + -- Acting with {txd_extend, TXD[9] forces current disparity to 1 or 0 + + rtxfifo_urst_en : IN STD_LOGIC; -- user reset CRAM enable + txfifo_urst : IN STD_LOGIC; -- user reset + rtxfifo_lowlatency_en : IN STD_LOGIC; -- low latency enable + rtxphfifopldctl_en : IN STD_LOGIC; -- CRAM to enable PLD controlled write/read enable + rtx_pipe_enable : IN STD_LOGIC; -- enable pipe + pld_we : IN STD_LOGIC; -- PLD phase comp. fifo we, level active + pld_rd_dis : IN STD_LOGIC; -- PLD phase comp. fifo rd dis, edge active + txd : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + txd_extend : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rforce_disp : IN STD_LOGIC; + tx_data_sg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + tx_control_sg : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rxd_lpbk : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + redund_ctl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + txd_redun : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + rforce_kchar : IN STD_LOGIC; + rforce_echar : IN STD_LOGIC; + -- PCS Bypass mode + rtxpcsbypass_en : IN STD_LOGIC; + + -- TX PIPE interface signals + txdetectrxloopback : IN STD_LOGIC; + --input txelecidle; txd[9] + --input txcompliance; txd[10] and txd[32] + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + + revloopback : IN STD_LOGIC; + + txswing : IN STD_LOGIC; + txdeemph : IN STD_LOGIC; + txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX PIPE interface signals + rxpolarity : IN STD_LOGIC; + polinv_rx : IN STD_LOGIC; + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- New Inputs for new bundling scheme and new PCIE features like autospeed + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + dis_pc_byte : IN STD_LOGIC; + wr_enable_centrl : IN STD_LOGIC; + wr_enable_quad_up : IN STD_LOGIC; + wr_enable_quad_down : IN STD_LOGIC; + rd_enable_centrl : IN STD_LOGIC; + rd_enable_quad_up : IN STD_LOGIC; + rd_enable_quad_down : IN STD_LOGIC; + fifo_select_in_centrl : IN STD_LOGIC; + fifo_select_in_quad_up : IN STD_LOGIC; + fifo_select_in_quad_down : IN STD_LOGIC; + + -- New MDIO for new bundling scheme and new PCIE features like autospeed + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rphfifo_regmode_tx : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + + -- ======= + -- outputs + -- ======= + txd_extend_tc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- This will go to the encoder. This is serialized (muxed) txd_extend_int. But + -- txd_extend_int has to go through the FIFOs first to be serialized. + -- ch0 wr_enable1 output for X4/X8 mode + -- ch0 rd_enable1 output for X4/X8 mode + tx_data_tc : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- 8-bit data passed onto the internal transmit logic. + tx_ctl_tc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- Control passed onto the internal transmit logic. + -- Can be bit 8 of the 10-bit code group. + tx_data_9_tc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- Bit 9 of the 10-bit code group passed onto the internal transmit logic. + rd_enable_sync : OUT STD_LOGIC; + k_det : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + d21_5_eq_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + d2_2_eq_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + wr_enable_out : OUT STD_LOGIC; + rd_enable_out : OUT STD_LOGIC; + fifo_select_out : OUT STD_LOGIC; -- New output for Rev.B + ph_fifo_full : OUT STD_LOGIC; -- fifo full flag + ph_fifo_empty : OUT STD_LOGIC; -- fifo empty flag + soft_reset_wclk1 : OUT STD_LOGIC; -- synchronized reset for BIST; + soft_reset_rclk1 : OUT STD_LOGIC; -- syncrhonized reset for PIPE + pipe_electric_idle : OUT STD_LOGIC; -- PIPE electric idle bit + + -- TX PIPE interface signals + txdetectrxloopback_int : OUT STD_LOGIC; + --output txelecidle; txd[9] + --output txcompliance; txd[10] and txd[32] + powerdown_int : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + revloopback_int : OUT STD_LOGIC; + + phfifo_txswing : OUT STD_LOGIC; + phfifo_txdeemph : OUT STD_LOGIC; + phfifo_txmargin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX PIPE interface signals + rxpolarity_int : OUT STD_LOGIC; + polinv_rx_int : OUT STD_LOGIC; + gray_eidleinfersel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- test bus + -- testbus[8] = fifo_select_out + -- testbus[7] = wr_enable2 + -- testbus[6:4] = wptr_bin + -- testbus[3] = rd_enable2 + -- testbus[2:0] = rptr_bin + wr_enable2 : OUT STD_LOGIC; + wptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rd_enable2 : OUT STD_LOGIC; + rptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END cycloneiv_hssi_tx_digi_tx_ctrl; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_digi_tx_ctrl IS + COMPONENT cycloneiv_hssi_tx_digis_ph_fifo + PORT ( + rst_wclk : IN STD_LOGIC; + rst_rclk : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + bypass_en : IN STD_LOGIC; + lowlatency_en : IN STD_LOGIC; + we : IN STD_LOGIC; + re : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(53 DOWNTO 0); + rphfifo_regmode_tx : IN STD_LOGIC; + rindv_tx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); + ph_fifo_full : OUT STD_LOGIC; + ph_fifo_empty : OUT STD_LOGIC; + wptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT; + + + -- ================ + -- internal signals + -- ================ + + -- Begin: 22 Bits output of this module (44 to 22 / 22 to 22) + SIGNAL tx_data_tc_mux : STD_LOGIC_VECTOR(15 DOWNTO 0); --temp holder for non PCS bypass data branch before mux + SIGNAL tx_ctl_tc_mux : STD_LOGIC_VECTOR(1 DOWNTO 0); --temp holder for non PCS bypass branch before mux + SIGNAL tx_data_9_tc_mux : STD_LOGIC_VECTOR(1 DOWNTO 0); --temp holder for non PCS bypass branch before mux + SIGNAL txd_extend_tc_mux : STD_LOGIC_VECTOR(1 DOWNTO 0); --temp holder for non PCS bypass branch before mux + -- End: 22 bits output of this module + + SIGNAL tx_data_lt : STD_LOGIC_VECTOR(19 DOWNTO 0); + + SIGNAL tx_data : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL din0 : STD_LOGIC_VECTOR(53 DOWNTO 0); + SIGNAL fifo_data_out : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL tx_data_9_tc_d : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL tx_data_9_tc_d_others : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL tx_ctl_tc_d : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL tx_ctl_tc_d_others : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL tx_data_tc_d : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL tx_data_tc_d_others : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL d21_5_eq_n_d : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL d2_2_eq_n_d : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL k_det_sync1 : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL txfifo_en_refclk0 : STD_LOGIC; + SIGNAL txfifo_en_refclk1 : STD_LOGIC; + + SIGNAL wr_enable0 : STD_LOGIC; + SIGNAL wr_enable0p5 : STD_LOGIC; + SIGNAL wr_enable1 : STD_LOGIC; + SIGNAL rd_enable0 : STD_LOGIC; + SIGNAL rd_enable0p5 : STD_LOGIC; + SIGNAL rd_enable1 : STD_LOGIC; + + SIGNAL txd_extend_int : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txd_extend_tc_d : STD_LOGIC_VECTOR(1 DOWNTO 0); -- This is registered and sent out to the encoder as txd_extend_tc. + -- This is serialized (muxed) txd_extend_int. But + -- txd_extend_int has to go through the FIFOs first to be serialized. + SIGNAL txd_extend_low : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txd_extend_high : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txd_data_extend_tmp : STD_LOGIC_VECTOR(17 DOWNTO 0); + + SIGNAL txfifo_en_rclk0 : STD_LOGIC; + SIGNAL txfifo_en_rclk1 : STD_LOGIC; + SIGNAL txfifo_en : STD_LOGIC; + + SIGNAL soft_reset_local : STD_LOGIC; + SIGNAL soft_reset_wclk0 : STD_LOGIC; + SIGNAL soft_reset_wclk1_b4scan : STD_LOGIC; + SIGNAL soft_reset_wclk1_wire : STD_LOGIC; + SIGNAL soft_reset_rclk0 : STD_LOGIC; + SIGNAL soft_reset_rclk1_b4scan : STD_LOGIC; + SIGNAL soft_reset_rclk1_wire : STD_LOGIC; + SIGNAL data_out_temp : STD_LOGIC_VECTOR(53 DOWNTO 0); + + SIGNAL pld_rd_dis0 : STD_LOGIC; + SIGNAL pld_rd_dis1 : STD_LOGIC; + SIGNAL pld_rd_dis2 : STD_LOGIC; + SIGNAL pld_rd_dis_edge : STD_LOGIC; + + -- PIPE electric idle bit + + -- register rd_enable_sync to fast clock domain. Necessary to send out low + -- byte first after soft_reset. + SIGNAL rd_enable_sync_refclk_b_in : STD_LOGIC; + + -- PIPE command signals + SIGNAL pipe_cmd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL pipe_cmd_out : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL rdwidth_or_auto : STD_LOGIC; + SIGNAL gen2ngen1_int : STD_LOGIC; + SIGNAL gen2ngen1_reg : STD_LOGIC; + SIGNAL gen2ngen1_sync : STD_LOGIC; + + SIGNAL pipe_tx_trans : STD_LOGIC_VECTOR(4 DOWNTO 0); -- PIPE transmitter settings + -- {txswing, txdeemph, txmargin} + SIGNAL pipe_tx_trans_out : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- X-HDL generated signals + + SIGNAL xhdl8 : STD_LOGIC; + SIGNAL xhdl9 : STD_LOGIC; + SIGNAL xhdl10 : STD_LOGIC; + SIGNAL xhdl11 : STD_LOGIC; + SIGNAL xhdl12 : STD_LOGIC; + SIGNAL xhdl13 : STD_LOGIC; + SIGNAL xhdl14 : STD_LOGIC; + SIGNAL xhdl15 : STD_LOGIC; + SIGNAL xhdl16 : STD_LOGIC; + SIGNAL xhdl17 : STD_LOGIC; + SIGNAL xhdl18 : STD_LOGIC; + SIGNAL xhdl19 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl20 : STD_LOGIC; + SIGNAL xhdl21 : STD_LOGIC; + SIGNAL xhdl22 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL rd_enable_sync_xhdl4 : STD_LOGIC; + SIGNAL fifo_select_out_xhdl0 : STD_LOGIC; + SIGNAL ph_fifo_full_xhdl2 : STD_LOGIC; + SIGNAL ph_fifo_empty_xhdl1 : STD_LOGIC; + SIGNAL wr_enable2_xhdl7 : STD_LOGIC; + SIGNAL wptr_bin_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rd_enable2_xhdl3 : STD_LOGIC; + SIGNAL rptr_bin_xhdl5 : STD_LOGIC_VECTOR(2 DOWNTO 0); +BEGIN + -- Drive referenced outputs + rd_enable_sync <= rd_enable_sync_xhdl4; + fifo_select_out <= fifo_select_out_xhdl0; + ph_fifo_full <= ph_fifo_full_xhdl2; + ph_fifo_empty <= ph_fifo_empty_xhdl1; + wr_enable2 <= wr_enable2_xhdl7; + wptr_bin <= wptr_bin_xhdl6; + rd_enable2 <= rd_enable2_xhdl3; + rptr_bin <= rptr_bin_xhdl5; + + -- ============= + -- functionality + -- ============= + soft_reset_wclk1 <= soft_reset_wclk1_wire; + soft_reset_rclk1 <= soft_reset_rclk1_wire; + txd_extend_int <= txd_extend WHEN (rforce_disp = '1') ELSE + "0000"; + + -- GiGE Idle Detection, replaced in 8b10b encoder + d21_5_eq_n_d(0) <= int2bit(((tx_ctl_tc_d(0) & tx_data_tc_d(7 DOWNTO 0)) /= "010110101")); + d21_5_eq_n_d(1) <= int2bit(((tx_ctl_tc_d(1) & tx_data_tc_d(15 DOWNTO 8)) /= "010110101")); + d2_2_eq_n_d(0) <= int2bit(((tx_ctl_tc_d(0) & tx_data_tc_d(7 DOWNTO 0)) /= "001000010")); + d2_2_eq_n_d(1) <= int2bit(((tx_ctl_tc_d(1) & tx_data_tc_d(15 DOWNTO 8)) /= "001000010")); + + wr_enable_out <= wr_enable1; + rd_enable_out <= rd_enable1; + + -- 2-17-04 BT: Tied the tx_data[9] to 1'b0 in selftest mode since it effects the + -- disparity input in the 8B/10B encoder + tx_data(19 DOWNTO 0) <= rxd_lpbk(19 DOWNTO 0) WHEN (p_rlpbk = '1') ELSE + ('0' & tx_control_sg(1) & tx_data_sg(15 DOWNTO 8) & '0' & tx_control_sg(0) & tx_data_sg(7 DOWNTO 0)) WHEN (selftest_en = '1') ELSE + txd_redun(19 DOWNTO 0) WHEN (redund_ctl /= "0000") ELSE + txd(19 DOWNTO 0); + + -- enable 3G double-width BIST by mapping tx_data_sg[15:8] & tx_control_sg[1] to the 3rd symbol location + tx_data(39 DOWNTO 20) <= rxd_lpbk(39 DOWNTO 20) WHEN (p_rlpbk = '1') ELSE + ('0' & tx_control_sg(3) & tx_data_sg(31 DOWNTO 24) & '0' & tx_control_sg(1) & tx_data_sg(15 DOWNTO 8)) WHEN (selftest_en = '1') ELSE + txd_redun(39 DOWNTO 20) WHEN (redund_ctl /= "0000") ELSE + txd(39 DOWNTO 20); + + txfifo_en <= NOT(txfifo_urst) WHEN (rtxfifo_urst_en = '1') ELSE + '1'; + + -- PIPE electric idle is on txd[10] + --assign pipe_electric_idle = txd_extend_tc_d[0]; + + soft_reset_local <= soft_reset OR (rtxfifo_urst_en AND txfifo_urst); + + -- PIPE cmd + pipe_cmd <= (powerdown & txdetectrxloopback & revloopback & '0'); + + revloopback_int <= pipe_cmd(1) WHEN (txfifo_dis = '1') ELSE + pipe_cmd_out(1); + txdetectrxloopback_int <= pipe_cmd(2) WHEN (txfifo_dis = '1') ELSE + pipe_cmd_out(2); + powerdown_int <= pipe_cmd(4 DOWNTO 3) WHEN (txfifo_dis = '1') ELSE + pipe_cmd_out(4 DOWNTO 3); + + rxpolarity_int <= rxpolarity; + polinv_rx_int <= polinv_rx; + + gen2ngen1_int <= gen2ngen1 WHEN (rindv_tx = '1') ELSE + gen2ngen1_bundle; + --//************************************ + --// Synchronization of gen2ngen1 + --//************************************ + PROCESS (soft_reset, refclk_b_in) + BEGIN + IF (soft_reset = '1') THEN + gen2ngen1_reg <= '0'; + gen2ngen1_sync <= '0'; + ELSIF (refclk_b_in'EVENT AND refclk_b_in = '1') THEN + gen2ngen1_reg <= gen2ngen1_int; + gen2ngen1_sync <= gen2ngen1_reg; + END IF; + END PROCESS; -- always @ (posedge soft_reset or posedge refclk_b_in) + + rdwidth_or_auto <= (rdwidth_tx OR (rauto_speed_ena AND NOT(rfreq_sel) AND gen2ngen1_sync)); + + pipe_tx_trans <= (txswing & txdeemph & txmargin); + + phfifo_txswing <= pipe_tx_trans(4) WHEN (txfifo_dis = '1') ELSE + pipe_tx_trans_out(4); + phfifo_txdeemph <= pipe_tx_trans(3) WHEN (txfifo_dis = '1') ELSE + pipe_tx_trans_out(3); + phfifo_txmargin <= pipe_tx_trans(2 DOWNTO 0) WHEN (txfifo_dis = '1') ELSE + pipe_tx_trans_out(2 DOWNTO 0); + + -- synchronize reset input (in refclk_b domain) + PROCESS (soft_reset_local, fifo_wr_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_local = '1') THEN + soft_reset_wclk0 <= TRANSPORT '1' AFTER 1 ps; + soft_reset_wclk1_b4scan <= TRANSPORT '1' AFTER 1 ps; + ELSIF (fifo_wr_clk'EVENT AND fifo_wr_clk = '1') THEN + soft_reset_wclk0 <= TRANSPORT '0' AFTER 1 ps; + soft_reset_wclk1_b4scan <= TRANSPORT soft_reset_wclk0 AFTER 1 ps; + END IF; + END PROCESS; + + -- always @ (posedge soft_reset_local or posedge fifo_wr_clk) + + soft_reset_wclk1_wire <= '0' WHEN (scan_mode = '1') ELSE + soft_reset_wclk1_b4scan; + + -- synchronize reset input (in refclk_b domain) and balance it with fifo_wr_clk reset + PROCESS (soft_reset_local, fifo_rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_local = '1') THEN + soft_reset_rclk0 <= TRANSPORT '1' AFTER 1 ps; + soft_reset_rclk1_b4scan <= TRANSPORT '1' AFTER 1 ps; + ELSIF (fifo_rd_clk'EVENT AND fifo_rd_clk = '1') THEN + soft_reset_rclk0 <= TRANSPORT '0' AFTER 1 ps; + soft_reset_rclk1_b4scan <= TRANSPORT soft_reset_rclk0 AFTER 1 ps; + END IF; + END PROCESS; + + -- always @ (posedge soft_reset_local or posedge fifo_rd_clk) + + soft_reset_rclk1_wire <= '0' WHEN (scan_mode = '1') ELSE + soft_reset_rclk1_b4scan; + + -- write enable + --wr_enable0 <= txfifo_en; + --wr_enable0 <= 1'b1; + xhdl8 <= (wr_enable0p5 AND pld_we) WHEN (rtxphfifopldctl_en = '1') ELSE + wr_enable0p5; + xhdl9 <= wr_enable1 WHEN (rindv_tx = '1') ELSE + wr_enable_centrl; + xhdl10 <= wr_enable_quad_up WHEN (rmaster_up_tx = '1') ELSE + wr_enable_quad_down; + xhdl11 <= (xhdl9) WHEN (rmaster_tx = '1') ELSE + (xhdl10); + PROCESS (soft_reset_wclk1_wire, fifo_wr_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_wclk1_wire = '1') THEN + wr_enable0 <= TRANSPORT '0' AFTER 1 ps; + wr_enable0p5 <= TRANSPORT '0' AFTER 1 ps; + wr_enable1 <= TRANSPORT '0' AFTER 1 ps; + wr_enable2_xhdl7 <= TRANSPORT '0' AFTER 1 ps; + ELSIF (fifo_wr_clk'EVENT AND fifo_wr_clk = '1') THEN + wr_enable0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1 ps; + wr_enable0p5 <= TRANSPORT wr_enable0 AFTER 1 ps; + wr_enable1 <= TRANSPORT xhdl8 AFTER 1 ps; + wr_enable2_xhdl7 <= TRANSPORT xhdl11 AFTER 1 ps; + END IF; + END PROCESS; + + -- always @ (posedge soft_reset_wclk1 or posedge fifo_wr_clk) + + din0 <= (pipe_tx_trans & pipe_cmd & txd_extend_int(3 DOWNTO 2) & tx_data(39 DOWNTO 20) & txd_extend_int(1 DOWNTO 0) & tx_data(19 DOWNTO 0)); + + -- Instantiate new FIFO + + + ph_fifo_tx_1 : cycloneiv_hssi_tx_digis_ph_fifo + PORT MAP ( + rst_wclk => soft_reset_wclk1_wire, + rst_rclk => soft_reset_rclk1_wire, + wr_clk => fifo_wr_clk, + rd_clk => fifo_rd_clk, + bypass_en => txfifo_dis, + --.en(1'b1), + lowlatency_en => rtxfifo_lowlatency_en, + we => wr_enable2_xhdl7, + re => rd_enable2_xhdl3, + din => din0, + data_out => data_out_temp, + ph_fifo_full => ph_fifo_full_xhdl2, + ph_fifo_empty => ph_fifo_empty_xhdl1, + wptr_bin => wptr_bin_xhdl6, + rptr_bin => rptr_bin_xhdl5, + rphfifo_regmode_tx => rphfifo_regmode_tx, + rindv_tx => rindv_tx, + rmaster_tx => rmaster_tx, + rmaster_up_tx => rmaster_up_tx, + rauto_speed_ena => rauto_speed_ena, + reset_pc_ptrs => reset_pc_ptrs, + reset_pc_ptrs_centrl => reset_pc_ptrs_centrl, + reset_pc_ptrs_quad_up => reset_pc_ptrs_quad_up, + reset_pc_ptrs_quad_down => reset_pc_ptrs_quad_down + ); + pipe_tx_trans_out <= data_out_temp(53 DOWNTO 49); + pipe_cmd_out <= data_out_temp(48 DOWNTO 44); + txd_extend_high <= data_out_temp(43 DOWNTO 42); + fifo_data_out(39 DOWNTO 20) <= data_out_temp(41 DOWNTO 22); + txd_extend_low <= data_out_temp(21 DOWNTO 20); + fifo_data_out(19 DOWNTO 0) <= data_out_temp(19 DOWNTO 0); + + -- Modified Byte Serializer logic to use fifo_select_out to ping-pong between + -- low and high banks of FIFO during normal mode + -- Toggle between {19,9} and {39,29} when DWIDTH is set, else fixed to {19,9} + tx_data_9_tc_d <= (fifo_data_out(19) & fifo_data_out(9)) WHEN ((NOT(txfifo_dis) AND rd_enable_sync_xhdl4 AND (NOT(rdwidth_or_auto) OR fifo_select_out_xhdl0) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + (fifo_data_out(39) & fifo_data_out(29)) WHEN ((NOT(txfifo_dis) AND rd_enable_sync_xhdl4 AND (rdwidth_or_auto AND NOT(fifo_select_out_xhdl0)) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + (tx_data(19) & tx_data(9)) WHEN ((txfifo_dis AND (NOT(rdwidth_or_auto) OR NOT(fifo_select_out_xhdl0)) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + tx_data_9_tc_d_others; + + tx_data_9_tc_d_others <= "00" WHEN ((NOT(rforce_kchar) AND rforce_echar) = '1') ELSE + (tx_data_lt(19) & tx_data_lt(9)) WHEN ((txfifo_dis AND rdwidth_or_auto AND fifo_select_out_xhdl0 AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + "00"; + + -- 8th bit in each word. Toggle between {18,8} and {38,28} when DWIDTH is set, else fixed to {18,8} + tx_ctl_tc_d <= (fifo_data_out(18) & fifo_data_out(8)) WHEN ((NOT(txfifo_dis) AND rd_enable_sync_xhdl4 AND (NOT(rdwidth_or_auto) OR fifo_select_out_xhdl0) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + (fifo_data_out(38) & fifo_data_out(28)) WHEN ((NOT(txfifo_dis) AND rd_enable_sync_xhdl4 AND (rdwidth_or_auto AND NOT(fifo_select_out_xhdl0)) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + (tx_data(18) & tx_data(8)) WHEN ((txfifo_dis AND (NOT(rdwidth_or_auto) OR NOT(fifo_select_out_xhdl0)) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + tx_ctl_tc_d_others; + + -- When transmitting Error(FE) or bypassing FIFO, transmit 11 in the former case and transmit bypassed data/ctl in the latter + tx_ctl_tc_d_others <= "11" WHEN ((NOT(rforce_kchar) AND rforce_echar) = '1') ELSE + (tx_data_lt(18) & tx_data_lt(8)) WHEN ((txfifo_dis AND rdwidth_or_auto AND fifo_select_out_xhdl0 AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + "11"; + + -- After rd_enable_sync goes high, start transmitting. Initially, fifo_select_out is zero, so MSByte transmitted first. + -- Transmit data if not forced Error or K-char. + txd_extend_tc_d <= txd_data_extend_tmp(17 DOWNTO 16); + tx_data_tc_d <= txd_data_extend_tmp(15 DOWNTO 0); + txd_data_extend_tmp <= (txd_extend_low & fifo_data_out(17 DOWNTO 10) & fifo_data_out(7 DOWNTO 0)) WHEN ((NOT(txfifo_dis) AND rd_enable_sync_xhdl4 AND (NOT(rdwidth_or_auto) OR fifo_select_out_xhdl0) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + (txd_extend_high & fifo_data_out(37 DOWNTO 30) & fifo_data_out(27 DOWNTO 20)) WHEN ((NOT(txfifo_dis) AND rd_enable_sync_xhdl4 AND (rdwidth_or_auto AND NOT(fifo_select_out_xhdl0)) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + (txd_extend_int(1 DOWNTO 0) & tx_data(17 DOWNTO 10) & tx_data(7 DOWNTO 0)) WHEN ((txfifo_dis AND (NOT(rdwidth_or_auto) OR NOT(fifo_select_out_xhdl0)) AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + tx_data_tc_d_others; + + -- When transmitting Error(FE) or bypassing FIFO, transmit FE in the former case and transmit bypassed data/ctl in the latter + tx_data_tc_d_others <= ("00" & "11111110" & "11111110") WHEN ((NOT(rforce_kchar) AND rforce_echar) = '1') ELSE + (txd_extend_int(3 DOWNTO 2) & tx_data_lt(17 DOWNTO 10) & tx_data_lt(7 DOWNTO 0)) WHEN ((txfifo_dis AND rdwidth_or_auto AND fifo_select_out_xhdl0 AND NOT(rforce_kchar) AND NOT(rforce_echar)) = '1') ELSE + ("00" & "00000111" & "00000111") WHEN ((NOT(rindv_tx)) = '1') ELSE + ("00" & "10111100" & "10111100"); + + -- read enable & + -- read enable sync (for byte serializer output enable) + + --rd_enable0 <= txfifo_en; + -- rd_enable0 <= 1'b1; + xhdl12 <= (rd_enable0p5 AND NOT(pld_rd_dis_edge)) WHEN (rtxphfifopldctl_en = '1') ELSE + rd_enable0p5; + xhdl13 <= rd_enable1 WHEN (rindv_tx = '1') ELSE + rd_enable_centrl; + xhdl14 <= rd_enable_quad_up WHEN (rmaster_up_tx = '1') ELSE + rd_enable_quad_down; + xhdl15 <= (xhdl13) WHEN (rmaster_tx = '1') ELSE + (xhdl14); + + --txfifo_en_rclk0 <= txfifo_en; + + -- start with valid data, so rd_enable_sync serves as dout valid + -- ideally should be "rptr_bin == 3'd7", + -- but fifo_data_out is registered (1 clk delay). rd_enable_sync is + -- used in high/low byte selection enable + xhdl16 <= rd_enable1 WHEN (rindv_tx = '1') ELSE + rd_enable_centrl; + xhdl17 <= rd_enable_quad_up WHEN (rmaster_up_tx = '1') ELSE + rd_enable_quad_down; + xhdl18 <= (xhdl16) WHEN (rmaster_tx = '1') ELSE + (xhdl17); + PROCESS (soft_reset_rclk1_wire, fifo_rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_rclk1_wire = '1') THEN + pld_rd_dis0 <= TRANSPORT '0' AFTER 1 ps; + pld_rd_dis1 <= TRANSPORT '0' AFTER 1 ps; + pld_rd_dis2 <= TRANSPORT '0' AFTER 1 ps; + pld_rd_dis_edge <= TRANSPORT '0' AFTER 1 ps; + rd_enable0 <= TRANSPORT '0' AFTER 1 ps; + rd_enable0p5 <= TRANSPORT '0' AFTER 1 ps; + rd_enable1 <= TRANSPORT '0' AFTER 1 ps; + rd_enable2_xhdl3 <= TRANSPORT '0' AFTER 1 ps; + txfifo_en_rclk0 <= TRANSPORT '0' AFTER 1 ps; + txfifo_en_rclk1 <= TRANSPORT '0' AFTER 1 ps; + rd_enable_sync_xhdl4 <= TRANSPORT '0' AFTER 1 ps; + ELSIF (fifo_rd_clk'EVENT AND fifo_rd_clk = '1') THEN + pld_rd_dis0 <= TRANSPORT pld_rd_dis AFTER 1 ps; + pld_rd_dis1 <= TRANSPORT pld_rd_dis0 AFTER 1 ps; + pld_rd_dis2 <= TRANSPORT pld_rd_dis1 AFTER 1 ps; + pld_rd_dis_edge <= TRANSPORT int2bit((pld_rd_dis2 /= pld_rd_dis1)) AFTER 1 ps; + rd_enable0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1 ps; + rd_enable0p5 <= TRANSPORT rd_enable0 AFTER 1 ps; + rd_enable1 <= TRANSPORT xhdl12 AFTER 1 ps; + rd_enable2_xhdl3 <= TRANSPORT xhdl15 AFTER 1 ps; + txfifo_en_rclk0 <= TRANSPORT '1' AFTER 1 ps; + txfifo_en_rclk1 <= TRANSPORT txfifo_en_rclk0 AFTER 1 ps; + IF (rphfifo_regmode_tx = '1') THEN + rd_enable_sync_xhdl4 <= TRANSPORT '1' AFTER 1 ps; + ELSIF (rd_enable_sync_xhdl4 = '0' AND rptr_bin_xhdl5 = "000") THEN + rd_enable_sync_xhdl4 <= TRANSPORT xhdl18 AFTER 1 ps; + ELSIF (txfifo_en_rclk1 = '0') THEN + rd_enable_sync_xhdl4 <= TRANSPORT '0' AFTER 1 ps; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge soft_reset_rclk1 or posedge fifo_rd_clk) + + + -- PIPE enabled, txd[21] & txd[10] are used as PIPE electric idle + -- hence in PIPE mode, txd[21] & txd[10](crd_enforce_value) are forced to txd[20] & txd[9] + -- (crd_enforce_enable) to have crd negative enable. + -- crd positive enable is not provided in PIPE mode + xhdl19 <= (txd_extend_tc_d(1) & tx_data_9_tc_d(0)) WHEN (rtx_pipe_enable = '1') ELSE + txd_extend_tc_d; + PROCESS (soft_reset, refclk_b_in) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset = '1') THEN + tx_data_9_tc_mux <= TRANSPORT "00" AFTER 1 ps; + tx_ctl_tc_mux <= TRANSPORT "00" AFTER 1 ps; + tx_data_tc_mux <= TRANSPORT "0000000000000000" AFTER 1 ps; + txd_extend_tc_mux <= TRANSPORT "00" AFTER 1 ps; + tx_data_lt <= TRANSPORT "00000000000000000000" AFTER 1 ps; + d21_5_eq_n <= TRANSPORT "11" AFTER 1 ps; + d2_2_eq_n <= TRANSPORT "11" AFTER 1 ps; + k_det_sync1 <= TRANSPORT "00" AFTER 1 ps; + k_det <= TRANSPORT "00" AFTER 1 ps; + pipe_electric_idle <= TRANSPORT '0' AFTER 1 ps; + ELSIF (refclk_b_in'EVENT AND refclk_b_in = '1') THEN + tx_data_9_tc_mux <= TRANSPORT tx_data_9_tc_d AFTER 1 ps; + tx_ctl_tc_mux <= TRANSPORT tx_ctl_tc_d AFTER 1 ps; + tx_data_tc_mux <= TRANSPORT tx_data_tc_d AFTER 1 ps; + txd_extend_tc_mux <= TRANSPORT xhdl19 AFTER 1 ps; + + pipe_electric_idle <= TRANSPORT txd_extend_tc_d(0) AFTER 1 ps; + d21_5_eq_n <= TRANSPORT d21_5_eq_n_d AFTER 1 ps; + d2_2_eq_n <= TRANSPORT d2_2_eq_n_d AFTER 1 ps; + + k_det <= TRANSPORT k_det_sync1 AFTER 1 ps; + IF ((rdwidth_or_auto AND NOT(fifo_select_out_xhdl0)) = '1') THEN + + tx_data_lt <= TRANSPORT tx_data(39 DOWNTO 20) AFTER 1 ps; + END IF; + IF (((tx_ctl_tc_d(0)) & (tx_data_tc_d(7 DOWNTO 0))) = "110111100") THEN + k_det_sync1(0) <= TRANSPORT '1' AFTER 1 ps; + ELSE + + k_det_sync1(0) <= TRANSPORT '0' AFTER 1 ps; + END IF; + IF (((tx_ctl_tc_d(1)) & (tx_data_tc_d(15 DOWNTO 8))) = "110111100") THEN + k_det_sync1(1) <= TRANSPORT '1' AFTER 1 ps; + ELSE + k_det_sync1(1) <= TRANSPORT '0' AFTER 1 ps; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge soft_reset or posedge refclk_b_in) + + -- byte serializer high/low select + --txfifo_en_refclk0 <= txfifo_en; + -- txfifo_en_refclk0 <= 1'b1; + + -- was ~fifo_select_in, it allows 1 cycle to send the signal across x4, x8 channels + xhdl20 <= NOT(fifo_select_out_xhdl0) WHEN (rindv_tx = '1') ELSE + NOT(fifo_select_in_centrl); + xhdl21 <= NOT(fifo_select_in_quad_up) WHEN (rmaster_up_tx = '1') ELSE + NOT(fifo_select_in_quad_down); + xhdl22 <= (xhdl20) WHEN (rmaster_tx = '1') ELSE + (xhdl21); + PROCESS (soft_reset, refclk_b_in) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset = '1') THEN + rd_enable_sync_refclk_b_in <= TRANSPORT '0' AFTER 1 ps; + txfifo_en_refclk0 <= TRANSPORT '0' AFTER 1 ps; + txfifo_en_refclk1 <= TRANSPORT '0' AFTER 1 ps; + fifo_select_out_xhdl0 <= TRANSPORT '0' AFTER 1 ps; + ELSIF (refclk_b_in'EVENT AND refclk_b_in = '1') THEN + txfifo_en_refclk0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1 ps; + txfifo_en_refclk1 <= TRANSPORT txfifo_en_refclk0 AFTER 1 ps; + IF (txfifo_en_refclk1 = '0') THEN + rd_enable_sync_refclk_b_in <= TRANSPORT '0' AFTER 1 ps; + ELSIF (rd_enable_sync_refclk_b_in = '0') THEN + rd_enable_sync_refclk_b_in <= TRANSPORT rd_enable2_xhdl3 AFTER 1 ps; + END IF; + IF (rd_enable_sync_refclk_b_in = '1') THEN + fifo_select_out_xhdl0 <= TRANSPORT xhdl22 AFTER 1 ps; + ELSE + fifo_select_out_xhdl0 <= TRANSPORT '0' AFTER 1 ps; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge soft_reset or posedge refclk_b_in) + + tx_data_9_tc <= tx_data_9_tc_d WHEN ((rtxpcsbypass_en AND (NOT(rdwidth_or_auto))) = '1') ELSE + tx_data_9_tc_mux; + tx_ctl_tc <= tx_ctl_tc_d WHEN ((rtxpcsbypass_en AND (NOT(rdwidth_or_auto))) = '1') ELSE + tx_ctl_tc_mux; + tx_data_tc <= tx_data_tc_d WHEN ((rtxpcsbypass_en AND (NOT(rdwidth_or_auto))) = '1') ELSE + tx_data_tc_mux; + txd_extend_tc <= txd_extend_tc_d WHEN ((rtxpcsbypass_en AND (NOT(rdwidth_or_auto))) = '1') ELSE + txd_extend_tc_mux; + + -- LMC bin to gray for eidlinfersel + + PROCESS (fifo_wr_clk, soft_reset_wclk1_wire) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_wclk1_wire = '1') THEN + gray_eidleinfersel <= "000"; + ELSIF (fifo_wr_clk'EVENT AND fifo_wr_clk = '1') THEN + CASE eidleinfersel IS + WHEN "000" => + gray_eidleinfersel <= "000"; + WHEN "001" => + gray_eidleinfersel <= "001"; + WHEN "010" => + gray_eidleinfersel <= "011"; + WHEN "011" => + gray_eidleinfersel <= "010"; + WHEN "100" => + gray_eidleinfersel <= "110"; + WHEN "101" => + gray_eidleinfersel <= "111"; + WHEN "110" => + gray_eidleinfersel <= "101"; + WHEN "111" => + gray_eidleinfersel <= "100"; + WHEN OTHERS => + gray_eidleinfersel <= "000"; + END CASE; + END IF; + END PROCESS; + + +END trans; + + + +-- tx_ctrl--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 211 mux21 446 oper_add 10 oper_selector 88 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_tx_digi_bist_gen IS + PORT + ( + bist_ctl_sg : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + bist_data_sg : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + rbist_sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rbisten_tx : IN STD_LOGIC; + rcxpat_chnl_sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rdwidth_tx : IN STD_LOGIC; + rpma_doublewidth_tx : IN STD_LOGIC; + rpmadwidth_tx : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + tx_clk : IN STD_LOGIC + ); + END cycloneiv_hssi_tx_digi_bist_gen; + + ARCHITECTURE RTL OF cycloneiv_hssi_tx_digi_bist_gen IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL ni001l45 : STD_LOGIC := '0'; + SIGNAL ni001l46 : STD_LOGIC := '0'; + SIGNAL nii00O39 : STD_LOGIC := '0'; + SIGNAL nii00O40 : STD_LOGIC := '0'; + SIGNAL wire_nii00O40_w_lg_w_lg_q228w230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii00O40_w_lg_q228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii01O41 : STD_LOGIC := '0'; + SIGNAL nii01O42 : STD_LOGIC := '0'; + SIGNAL nii0il37 : STD_LOGIC := '0'; + SIGNAL nii0il38 : STD_LOGIC := '0'; + SIGNAL nii0li35 : STD_LOGIC := '0'; + SIGNAL nii0li36 : STD_LOGIC := '0'; + SIGNAL wire_nii0li36_w_lg_w_lg_q207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii0li36_w_lg_q207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii0lO33 : STD_LOGIC := '0'; + SIGNAL nii0lO34 : STD_LOGIC := '0'; + SIGNAL nii0OO31 : STD_LOGIC := '0'; + SIGNAL nii0OO32 : STD_LOGIC := '0'; + SIGNAL wire_nii0OO32_w_lg_w_lg_q155w156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii0OO32_w_lg_q155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii1OO43 : STD_LOGIC := '0'; + SIGNAL nii1OO44 : STD_LOGIC := '0'; + SIGNAL wire_nii1OO44_w_lg_w_lg_q295w296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii1OO44_w_lg_q295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niii0i23 : STD_LOGIC := '0'; + SIGNAL niii0i24 : STD_LOGIC := '0'; + SIGNAL wire_niii0i24_w_lg_w_lg_q129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niii0i24_w_lg_q129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niii0O21 : STD_LOGIC := '0'; + SIGNAL niii0O22 : STD_LOGIC := '0'; + SIGNAL niii1i29 : STD_LOGIC := '0'; + SIGNAL niii1i30 : STD_LOGIC := '0'; + SIGNAL wire_niii1i30_w_lg_w_lg_q152w153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niii1i30_w_lg_q152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niii1l27 : STD_LOGIC := '0'; + SIGNAL niii1l28 : STD_LOGIC := '0'; + SIGNAL wire_niii1l28_w_lg_w_lg_q141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niii1l28_w_lg_q141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niii1O25 : STD_LOGIC := '0'; + SIGNAL niii1O26 : STD_LOGIC := '0'; + SIGNAL wire_niii1O26_w_lg_w_lg_q132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niii1O26_w_lg_q132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niillO19 : STD_LOGIC := '0'; + SIGNAL niillO20 : STD_LOGIC := '0'; + SIGNAL niilOi17 : STD_LOGIC := '0'; + SIGNAL niilOi18 : STD_LOGIC := '0'; + SIGNAL niilOO15 : STD_LOGIC := '0'; + SIGNAL niilOO16 : STD_LOGIC := '0'; + SIGNAL wire_niilOO16_w_lg_w_lg_q78w79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niilOO16_w_lg_q78w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niiO0i10 : STD_LOGIC := '0'; + SIGNAL niiO0i9 : STD_LOGIC := '0'; + SIGNAL niiO0O7 : STD_LOGIC := '0'; + SIGNAL niiO0O8 : STD_LOGIC := '0'; + SIGNAL niiO1i13 : STD_LOGIC := '0'; + SIGNAL niiO1i14 : STD_LOGIC := '0'; + SIGNAL wire_niiO1i14_w_lg_w_lg_q53w54w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO1i14_w_lg_q53w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niiO1l11 : STD_LOGIC := '0'; + SIGNAL niiO1l12 : STD_LOGIC := '0'; + SIGNAL niiOll5 : STD_LOGIC := '0'; + SIGNAL niiOll6 : STD_LOGIC := '0'; + SIGNAL niiOOl3 : STD_LOGIC := '0'; + SIGNAL niiOOl4 : STD_LOGIC := '0'; + SIGNAL nil11i1 : STD_LOGIC := '0'; + SIGNAL nil11i2 : STD_LOGIC := '0'; + SIGNAL wire_nil11i2_w_lg_q4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n100i : STD_LOGIC := '0'; + SIGNAL n100l : STD_LOGIC := '0'; + SIGNAL n100O : STD_LOGIC := '0'; + SIGNAL n101i : STD_LOGIC := '0'; + SIGNAL n101l : STD_LOGIC := '0'; + SIGNAL n101O : STD_LOGIC := '0'; + SIGNAL n10ii : STD_LOGIC := '0'; + SIGNAL n10il : STD_LOGIC := '0'; + SIGNAL n10iO : STD_LOGIC := '0'; + SIGNAL n10li : STD_LOGIC := '0'; + SIGNAL n10ll : STD_LOGIC := '0'; + SIGNAL n10lO : STD_LOGIC := '0'; + SIGNAL n10Oi : STD_LOGIC := '0'; + SIGNAL n10Ol : STD_LOGIC := '0'; + SIGNAL n10OO : STD_LOGIC := '0'; + SIGNAL n110i : STD_LOGIC := '0'; + SIGNAL n110l : STD_LOGIC := '0'; + SIGNAL n110O : STD_LOGIC := '0'; + SIGNAL n111i : STD_LOGIC := '0'; + SIGNAL n111l : STD_LOGIC := '0'; + SIGNAL n111O : STD_LOGIC := '0'; + SIGNAL n11ii : STD_LOGIC := '0'; + SIGNAL n11il : STD_LOGIC := '0'; + SIGNAL n11iO : STD_LOGIC := '0'; + SIGNAL n11li : STD_LOGIC := '0'; + SIGNAL n11ll : STD_LOGIC := '0'; + SIGNAL n11lO : STD_LOGIC := '0'; + SIGNAL n11Oi : STD_LOGIC := '0'; + SIGNAL n11Ol : STD_LOGIC := '0'; + SIGNAL n11OO : STD_LOGIC := '0'; + SIGNAL n1i0i : STD_LOGIC := '0'; + SIGNAL n1i0l : STD_LOGIC := '0'; + SIGNAL n1i0O : STD_LOGIC := '0'; + SIGNAL n1i1i : STD_LOGIC := '0'; + SIGNAL n1i1l : STD_LOGIC := '0'; + SIGNAL n1i1O : STD_LOGIC := '0'; + SIGNAL n1iii : STD_LOGIC := '0'; + SIGNAL n1iil : STD_LOGIC := '0'; + SIGNAL n1iiO : STD_LOGIC := '0'; + SIGNAL n1ili : STD_LOGIC := '0'; + SIGNAL n1ill : STD_LOGIC := '0'; + SIGNAL n1ilO : STD_LOGIC := '0'; + SIGNAL n1iOi : STD_LOGIC := '0'; + SIGNAL n1iOl : STD_LOGIC := '0'; + SIGNAL n1iOO : STD_LOGIC := '0'; + SIGNAL n1l0i : STD_LOGIC := '0'; + SIGNAL n1l0l : STD_LOGIC := '0'; + SIGNAL n1l1i : STD_LOGIC := '0'; + SIGNAL n1l1l : STD_LOGIC := '0'; + SIGNAL n1l1O : STD_LOGIC := '0'; + SIGNAL n1lii : STD_LOGIC := '0'; + SIGNAL nliliO : STD_LOGIC := '0'; + SIGNAL nlOOil : STD_LOGIC := '0'; + SIGNAL nlOOiO : STD_LOGIC := '0'; + SIGNAL nlOOli : STD_LOGIC := '0'; + SIGNAL nlOOll : STD_LOGIC := '0'; + SIGNAL nlOOlO : STD_LOGIC := '0'; + SIGNAL nlOOOi : STD_LOGIC := '0'; + SIGNAL nlOOOl : STD_LOGIC := '0'; + SIGNAL nlOOOO : STD_LOGIC := '0'; + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_w1501w1502w1503w1504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w1510w1511w1512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w1501w1502w1503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w1510w1511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w1501w1502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w1510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w1501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n101i1506w1507w1508w1509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n101i1480w1497w1499w1500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n11ii897w899w900w901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_n101i1506w1507w1508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_n11ii902w903w904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_n101i1480w1482w1483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_n101i1480w1497w1499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_n11ii897w899w900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_n101i1506w1507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_n11ii902w903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_n101i1480w1482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_n101i1480w1497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_n11ii897w899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_nlOOiO1476w1543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_nlOOOO1529w1530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n101i1506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11ii902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nlOOOO1538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n101i1480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n110i1516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n110O898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n111O1524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11ii897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11il1494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11iO1492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11li1490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11ll1488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11lO1486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11Oi1484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11Ol1498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n11OO1481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nliliO1544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nlOOil1477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nlOOiO1476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nlOOlO1533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nlOOOi1531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nlOOOl1537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_nlOOOO1529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_w_lg_n1ill1401w1402w1403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_w_lg_n1ill1401w1402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n1ill1401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l0O_w_lg_n1l0i1211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1liO : STD_LOGIC := '0'; + SIGNAL wire_n1lil_w_lg_w_lg_w_lg_n1liO1051w1092w1093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lil_w_lg_w_lg_n1liO1051w1092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lil_w_lg_n1liO1051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl00il : STD_LOGIC := '0'; + SIGNAL nl00iO : STD_LOGIC := '0'; + SIGNAL nl00li : STD_LOGIC := '0'; + SIGNAL nl00ll : STD_LOGIC := '0'; + SIGNAL nl00lO : STD_LOGIC := '0'; + SIGNAL nl00Oi : STD_LOGIC := '0'; + SIGNAL nl00Ol : STD_LOGIC := '0'; + SIGNAL nl00OO : STD_LOGIC := '0'; + SIGNAL nl0i0i : STD_LOGIC := '0'; + SIGNAL nl0i0l : STD_LOGIC := '0'; + SIGNAL nl0i0O : STD_LOGIC := '0'; + SIGNAL nl0i1i : STD_LOGIC := '0'; + SIGNAL nl0i1l : STD_LOGIC := '0'; + SIGNAL nl0i1O : STD_LOGIC := '0'; + SIGNAL nl0iii : STD_LOGIC := '0'; + SIGNAL nl0iil : STD_LOGIC := '0'; + SIGNAL nl0iiO : STD_LOGIC := '0'; + SIGNAL nl0ili : STD_LOGIC := '0'; + SIGNAL nl0ill : STD_LOGIC := '0'; + SIGNAL nl0ilO : STD_LOGIC := '0'; + SIGNAL nl0iOi : STD_LOGIC := '0'; + SIGNAL nl0iOl : STD_LOGIC := '0'; + SIGNAL nl0iOO : STD_LOGIC := '0'; + SIGNAL nl0l0i : STD_LOGIC := '0'; + SIGNAL nl0l0l : STD_LOGIC := '0'; + SIGNAL nl0l0O : STD_LOGIC := '0'; + SIGNAL nl0l1i : STD_LOGIC := '0'; + SIGNAL nl0l1l : STD_LOGIC := '0'; + SIGNAL nl0l1O : STD_LOGIC := '0'; + SIGNAL nl0lii : STD_LOGIC := '0'; + SIGNAL nl0lil : STD_LOGIC := '0'; + SIGNAL nl0liO : STD_LOGIC := '0'; + SIGNAL nl0lli : STD_LOGIC := '0'; + SIGNAL nl0lll : STD_LOGIC := '0'; + SIGNAL nl0llO : STD_LOGIC := '0'; + SIGNAL nl0lOi : STD_LOGIC := '0'; + SIGNAL nl0lOl : STD_LOGIC := '0'; + SIGNAL nl0lOO : STD_LOGIC := '0'; + SIGNAL nl0O0i : STD_LOGIC := '0'; + SIGNAL nl0O0l : STD_LOGIC := '0'; + SIGNAL nl0O0O : STD_LOGIC := '0'; + SIGNAL nl0O1i : STD_LOGIC := '0'; + SIGNAL nl0O1l : STD_LOGIC := '0'; + SIGNAL nl0O1O : STD_LOGIC := '0'; + SIGNAL nl0Oii : STD_LOGIC := '0'; + SIGNAL nl0Oil : STD_LOGIC := '0'; + SIGNAL nl0OiO : STD_LOGIC := '0'; + SIGNAL nl0Oli : STD_LOGIC := '0'; + SIGNAL nl0Oll : STD_LOGIC := '0'; + SIGNAL nl0OlO : STD_LOGIC := '0'; + SIGNAL nl0OOi : STD_LOGIC := '0'; + SIGNAL nl0OOl : STD_LOGIC := '0'; + SIGNAL nli11i : STD_LOGIC := '0'; + SIGNAL wire_nl0OOO_PRN : STD_LOGIC; + SIGNAL wire_nl0OOO_w_lg_w_lg_w_lg_w_lg_nl0iOl2241w2243w2245w2253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_w_lg_w_lg_nl0iOl2241w2243w2245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_w_lg_nl0iOl2241w2243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0iii2259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0iil2257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0iiO2255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0ili2248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0ill2246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0ilO2244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0iOi2242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0iOl2241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0O0l2201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OOO_w_lg_nl0O0l2215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli11O : STD_LOGIC := '0'; + SIGNAL wire_nli11l_w_lg_nli11O2169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0lOi : STD_LOGIC := '0'; + SIGNAL niO0l : STD_LOGIC := '0'; + SIGNAL niO0O : STD_LOGIC := '0'; + SIGNAL niOii : STD_LOGIC := '0'; + SIGNAL niOil : STD_LOGIC := '0'; + SIGNAL niOiO : STD_LOGIC := '0'; + SIGNAL niOli : STD_LOGIC := '0'; + SIGNAL niOll : STD_LOGIC := '0'; + SIGNAL niOlO : STD_LOGIC := '0'; + SIGNAL niOOi : STD_LOGIC := '0'; + SIGNAL niOOl : STD_LOGIC := '0'; + SIGNAL niOOO : STD_LOGIC := '0'; + SIGNAL nl00i : STD_LOGIC := '0'; + SIGNAL nl00l : STD_LOGIC := '0'; + SIGNAL nl00O : STD_LOGIC := '0'; + SIGNAL nl01i : STD_LOGIC := '0'; + SIGNAL nl01l : STD_LOGIC := '0'; + SIGNAL nl01O : STD_LOGIC := '0'; + SIGNAL nl0ii : STD_LOGIC := '0'; + SIGNAL nl0il : STD_LOGIC := '0'; + SIGNAL nl0iO : STD_LOGIC := '0'; + SIGNAL nl0li : STD_LOGIC := '0'; + SIGNAL nl0ll : STD_LOGIC := '0'; + SIGNAL nl0lO : STD_LOGIC := '0'; + SIGNAL nl0Oi : STD_LOGIC := '0'; + SIGNAL nl0Ol : STD_LOGIC := '0'; + SIGNAL nl0OO : STD_LOGIC := '0'; + SIGNAL nl10i : STD_LOGIC := '0'; + SIGNAL nl10l : STD_LOGIC := '0'; + SIGNAL nl10O : STD_LOGIC := '0'; + SIGNAL nl11i : STD_LOGIC := '0'; + SIGNAL nl11l : STD_LOGIC := '0'; + SIGNAL nl11O : STD_LOGIC := '0'; + SIGNAL nl1ii : STD_LOGIC := '0'; + SIGNAL nl1il : STD_LOGIC := '0'; + SIGNAL nl1iO : STD_LOGIC := '0'; + SIGNAL nl1li : STD_LOGIC := '0'; + SIGNAL nl1ll : STD_LOGIC := '0'; + SIGNAL nl1lO : STD_LOGIC := '0'; + SIGNAL nl1Oi : STD_LOGIC := '0'; + SIGNAL nl1Ol : STD_LOGIC := '0'; + SIGNAL nl1OO : STD_LOGIC := '0'; + SIGNAL nli0i : STD_LOGIC := '0'; + SIGNAL nli0l : STD_LOGIC := '0'; + SIGNAL nli0O : STD_LOGIC := '0'; + SIGNAL nli1i : STD_LOGIC := '0'; + SIGNAL nli1l : STD_LOGIC := '0'; + SIGNAL nli1O : STD_LOGIC := '0'; + SIGNAL nliil : STD_LOGIC := '0'; + SIGNAL wire_nliii_w_lg_w_lg_w_lg_niOll766w767w768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_niOll766w767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_niO0O762w771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOll766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0lOi772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niO0l763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niO0O762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOii769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nl00O654w655w656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nl00O654w655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl00O654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlili : STD_LOGIC := '0'; + SIGNAL wire_nliiO_CLRN : STD_LOGIC; + SIGNAL wire_nliiO_PRN : STD_LOGIC; + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w194w195w196w197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w120w121w122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w194w195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w194w195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w256w257w258w259w260w261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w217w218w219w220w221w222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w114w115w116w117w118w119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w256w257w258w259w260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w217w218w219w220w221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w114w115w116w117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w256w257w258w259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w217w218w219w220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w114w115w116w117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w188w189w190w191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w256w257w258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w217w218w219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w114w115w116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w188w189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w256w257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w217w218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w188w189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili160w161w162w254w255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili160w161w214w215w216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili109w110w111w112w113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili109w184w185w186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili160w161w162w254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili160w161w214w215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili109w110w111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili109w184w185w186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_nlili160w161w162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_nlili160w161w214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_nlili109w110w111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_w_lg_nlili109w184w185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_nlili160w161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_nlili109w110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_w_lg_nlili109w184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_nlili160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO_w_lg_nlili109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n000i_dataout : STD_LOGIC; + SIGNAL wire_n000l_dataout : STD_LOGIC; + SIGNAL wire_n000O_dataout : STD_LOGIC; + SIGNAL wire_n001i_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001O_dataout : STD_LOGIC; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00ii_dataout : STD_LOGIC; + SIGNAL wire_n00il_dataout : STD_LOGIC; + SIGNAL wire_n00iO_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00li_dataout : STD_LOGIC; + SIGNAL wire_n00ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n010i_dataout : STD_LOGIC; + SIGNAL wire_n010l_dataout : STD_LOGIC; + SIGNAL wire_n010O_dataout : STD_LOGIC; + SIGNAL wire_n011i_dataout : STD_LOGIC; + SIGNAL wire_n011l_dataout : STD_LOGIC; + SIGNAL wire_n011O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01lO_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0llO_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1lli_dataout : STD_LOGIC; + SIGNAL wire_n1lll_dataout : STD_LOGIC; + SIGNAL wire_n1llO_dataout : STD_LOGIC; + SIGNAL wire_n1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOl_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni0OO_dataout : STD_LOGIC; + SIGNAL wire_ni11i_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0O_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO00i_dataout : STD_LOGIC; + SIGNAL wire_niO00l_dataout : STD_LOGIC; + SIGNAL wire_niO00O_dataout : STD_LOGIC; + SIGNAL wire_niO01i_dataout : STD_LOGIC; + SIGNAL wire_niO01l_dataout : STD_LOGIC; + SIGNAL wire_niO01O_dataout : STD_LOGIC; + SIGNAL wire_niO0ii_dataout : STD_LOGIC; + SIGNAL wire_niO0il_dataout : STD_LOGIC; + SIGNAL wire_niO0iO_dataout : STD_LOGIC; + SIGNAL wire_niO0li_dataout : STD_LOGIC; + SIGNAL wire_niO0ll_dataout : STD_LOGIC; + SIGNAL wire_niO0lO_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0OO_dataout : STD_LOGIC; + SIGNAL wire_niO10i_dataout : STD_LOGIC; + SIGNAL wire_niO10l_dataout : STD_LOGIC; + SIGNAL wire_niO10O_dataout : STD_LOGIC; + SIGNAL wire_niO11l_dataout : STD_LOGIC; + SIGNAL wire_niO11O_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1ii_dataout : STD_LOGIC; + SIGNAL wire_niO1il_dataout : STD_LOGIC; + SIGNAL wire_niO1iO_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1li_dataout : STD_LOGIC; + SIGNAL wire_niO1ll_dataout : STD_LOGIC; + SIGNAL wire_niO1lO_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOiii_dataout : STD_LOGIC; + SIGNAL wire_niOiil_dataout : STD_LOGIC; + SIGNAL wire_niOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOili_dataout : STD_LOGIC; + SIGNAL wire_niOill_dataout : STD_LOGIC; + SIGNAL wire_niOilO_dataout : STD_LOGIC; + SIGNAL wire_niOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOlii_dataout : STD_LOGIC; + SIGNAL wire_niOlil_dataout : STD_LOGIC; + SIGNAL wire_niOliO_dataout : STD_LOGIC; + SIGNAL wire_niOlli_dataout : STD_LOGIC; + SIGNAL wire_niOlll_dataout : STD_LOGIC; + SIGNAL wire_niOllO_dataout : STD_LOGIC; + SIGNAL wire_niOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOl_dataout : STD_LOGIC; + SIGNAL wire_niOlOO_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOO0i_dataout : STD_LOGIC; + SIGNAL wire_niOO0l_dataout : STD_LOGIC; + SIGNAL wire_niOO0O_dataout : STD_LOGIC; + SIGNAL wire_niOO1i_dataout : STD_LOGIC; + SIGNAL wire_niOO1l_dataout : STD_LOGIC; + SIGNAL wire_niOO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOii_dataout : STD_LOGIC; + SIGNAL wire_niOOil_dataout : STD_LOGIC; + SIGNAL wire_niOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOli_dataout : STD_LOGIC; + SIGNAL wire_niOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl000i_dataout : STD_LOGIC; + SIGNAL wire_nl000l_dataout : STD_LOGIC; + SIGNAL wire_nl000O_dataout : STD_LOGIC; + SIGNAL wire_nl001i_dataout : STD_LOGIC; + SIGNAL wire_nl001l_dataout : STD_LOGIC; + SIGNAL wire_nl001O_dataout : STD_LOGIC; + SIGNAL wire_nl00ii_dataout : STD_LOGIC; + SIGNAL wire_nl010i_dataout : STD_LOGIC; + SIGNAL wire_nl010l_dataout : STD_LOGIC; + SIGNAL wire_nl010O_dataout : STD_LOGIC; + SIGNAL wire_nl011i_dataout : STD_LOGIC; + SIGNAL wire_nl011l_dataout : STD_LOGIC; + SIGNAL wire_nl011O_dataout : STD_LOGIC; + SIGNAL wire_nl01ii_dataout : STD_LOGIC; + SIGNAL wire_nl01il_dataout : STD_LOGIC; + SIGNAL wire_nl01iO_dataout : STD_LOGIC; + SIGNAL wire_nl01li_dataout : STD_LOGIC; + SIGNAL wire_nl01ll_dataout : STD_LOGIC; + SIGNAL wire_nl01lO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl100i_dataout : STD_LOGIC; + SIGNAL wire_nl100l_dataout : STD_LOGIC; + SIGNAL wire_nl100O_dataout : STD_LOGIC; + SIGNAL wire_nl101i_dataout : STD_LOGIC; + SIGNAL wire_nl101l_dataout : STD_LOGIC; + SIGNAL wire_nl101O_dataout : STD_LOGIC; + SIGNAL wire_nl10ii_dataout : STD_LOGIC; + SIGNAL wire_nl10il_dataout : STD_LOGIC; + SIGNAL wire_nl10iO_dataout : STD_LOGIC; + SIGNAL wire_nl10li_dataout : STD_LOGIC; + SIGNAL wire_nl10ll_dataout : STD_LOGIC; + SIGNAL wire_nl10lO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10OO_dataout : STD_LOGIC; + SIGNAL wire_nl110i_dataout : STD_LOGIC; + SIGNAL wire_nl110l_dataout : STD_LOGIC; + SIGNAL wire_nl110O_dataout : STD_LOGIC; + SIGNAL wire_nl111i_dataout : STD_LOGIC; + SIGNAL wire_nl111l_dataout : STD_LOGIC; + SIGNAL wire_nl111O_dataout : STD_LOGIC; + SIGNAL wire_nl11ii_dataout : STD_LOGIC; + SIGNAL wire_nl11il_dataout : STD_LOGIC; + SIGNAL wire_nl11iO_dataout : STD_LOGIC; + SIGNAL wire_nl11li_dataout : STD_LOGIC; + SIGNAL wire_nl11ll_dataout : STD_LOGIC; + SIGNAL wire_nl11lO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli00i_dataout : STD_LOGIC; + SIGNAL wire_nli00l_dataout : STD_LOGIC; + SIGNAL wire_nli00O_dataout : STD_LOGIC; + SIGNAL wire_nli01i_dataout : STD_LOGIC; + SIGNAL wire_nli01l_dataout : STD_LOGIC; + SIGNAL wire_nli01O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0il_dataout : STD_LOGIC; + SIGNAL wire_nli0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0li_dataout : STD_LOGIC; + SIGNAL wire_nli10i_dataout : STD_LOGIC; + SIGNAL wire_nli10l_dataout : STD_LOGIC; + SIGNAL wire_nli10O_dataout : STD_LOGIC; + SIGNAL wire_nli1ii_dataout : STD_LOGIC; + SIGNAL wire_nli1il_dataout : STD_LOGIC; + SIGNAL wire_nli1iO_dataout : STD_LOGIC; + SIGNAL wire_nli1li_dataout : STD_LOGIC; + SIGNAL wire_nli1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlil0O_dataout : STD_LOGIC; + SIGNAL wire_nlilii_dataout : STD_LOGIC; + SIGNAL wire_nlilil_dataout : STD_LOGIC; + SIGNAL wire_nlill_dataout : STD_LOGIC; + SIGNAL wire_nlilli_dataout : STD_LOGIC; + SIGNAL wire_nlilll_dataout : STD_LOGIC; + SIGNAL wire_nlillO_dataout : STD_LOGIC; + SIGNAL wire_nlilO_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOll_dataout : STD_LOGIC; + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll11i_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nlllil_dataout : STD_LOGIC; + SIGNAL wire_nllliO_dataout : STD_LOGIC; + SIGNAL wire_nlllli_dataout : STD_LOGIC; + SIGNAL wire_nlllll_dataout : STD_LOGIC; + SIGNAL wire_nllllO_dataout : STD_LOGIC; + SIGNAL wire_nlllOi_dataout : STD_LOGIC; + SIGNAL wire_nlllOl_dataout : STD_LOGIC; + SIGNAL wire_nlllOO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllO0i_dataout : STD_LOGIC; + SIGNAL wire_nllO0l_dataout : STD_LOGIC; + SIGNAL wire_nllO0O_dataout : STD_LOGIC; + SIGNAL wire_nllO1i_dataout : STD_LOGIC; + SIGNAL wire_nllO1l_dataout : STD_LOGIC; + SIGNAL wire_nllO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOii_dataout : STD_LOGIC; + SIGNAL wire_nllOil_dataout : STD_LOGIC; + SIGNAL wire_nllOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOli_dataout : STD_LOGIC; + SIGNAL wire_nllOll_dataout : STD_LOGIC; + SIGNAL wire_nllOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlO_w_lg_dataout1647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO00i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO11l_dataout : STD_LOGIC; + SIGNAL wire_nlO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOili_dataout : STD_LOGIC; + SIGNAL wire_nlOill_dataout : STD_LOGIC; + SIGNAL wire_nlOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n00Oi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n00Oi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n01iO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n01iO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n01iO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOi_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1lOi_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1lOi_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1Oll_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1Oll_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1Oll_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OOO_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1OOO_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1OOO_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli0ll_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli0ll_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli0ll_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli0lO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli0lO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli0lO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli0Oi_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli0Oi_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli0Oi_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nliOl_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOl_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOl_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllli_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllli_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllli_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0iii_o : STD_LOGIC; + SIGNAL wire_n0iii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0iil_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0iil_o : STD_LOGIC; + SIGNAL wire_n0iil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0iiO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iiO_o : STD_LOGIC; + SIGNAL wire_n0iiO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ilO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0ilO_o : STD_LOGIC; + SIGNAL wire_n0ilO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0iOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0iOl_o : STD_LOGIC; + SIGNAL wire_n0iOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0l1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0l1i_o : STD_LOGIC; + SIGNAL wire_n0l1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0l1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l1O_o : STD_LOGIC; + SIGNAL wire_n0l1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lii_o : STD_LOGIC; + SIGNAL wire_n0lii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lil_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lil_o : STD_LOGIC; + SIGNAL wire_n0lil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0liO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0liO_o : STD_LOGIC; + SIGNAL wire_n0liO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lli_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lli_o : STD_LOGIC; + SIGNAL wire_n0lli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lOl_o : STD_LOGIC; + SIGNAL wire_n0lOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0O0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0O0l_o : STD_LOGIC; + SIGNAL wire_n0O0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0O1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0O1l_o : STD_LOGIC; + SIGNAL wire_n0O1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Oil_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Oil_o : STD_LOGIC; + SIGNAL wire_n0Oil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Oll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Oll_o : STD_LOGIC; + SIGNAL wire_n0Oll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0OOl_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0OOl_o : STD_LOGIC; + SIGNAL wire_n0OOl_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni00l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni00l_o : STD_LOGIC; + SIGNAL wire_ni00l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni01i_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni01i_o : STD_LOGIC; + SIGNAL wire_ni01i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni01O_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni01O_o : STD_LOGIC; + SIGNAL wire_ni01O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0ii_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0ii_o : STD_LOGIC; + SIGNAL wire_ni0ii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0iO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0iO_o : STD_LOGIC; + SIGNAL wire_ni0iO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0ll_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0ll_o : STD_LOGIC; + SIGNAL wire_ni0ll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0Oi_data : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_ni0Oi_o : STD_LOGIC; + SIGNAL wire_ni0Oi_sel : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_ni10i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni10i_o : STD_LOGIC; + SIGNAL wire_ni10i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni11l_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni11l_o : STD_LOGIC; + SIGNAL wire_ni11l_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1Ol_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni1Ol_o : STD_LOGIC; + SIGNAL wire_ni1Ol_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nil00l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil00l_o : STD_LOGIC; + SIGNAL wire_nil00l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil01O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil01O_o : STD_LOGIC; + SIGNAL wire_nil01O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil0il_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0il_o : STD_LOGIC; + SIGNAL wire_nil0il_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0li_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0li_o : STD_LOGIC; + SIGNAL wire_nil0li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0Oi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil0Oi_o : STD_LOGIC; + SIGNAL wire_nil0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil1li_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nil1li_o : STD_LOGIC; + SIGNAL wire_nil1li_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nil1lO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil1lO_o : STD_LOGIC; + SIGNAL wire_nil1lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil1OO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil1OO_o : STD_LOGIC; + SIGNAL wire_nil1OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nili0i_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nili0i_o : STD_LOGIC; + SIGNAL wire_nili0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nili0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nili0O_o : STD_LOGIC; + SIGNAL wire_nili0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nili1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nili1i_o : STD_LOGIC; + SIGNAL wire_nili1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niliil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niliil_o : STD_LOGIC; + SIGNAL wire_niliil_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nilili_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nilili_o : STD_LOGIC; + SIGNAL wire_nilili_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nililO_data : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nililO_o : STD_LOGIC; + SIGNAL wire_nililO_sel : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niliOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niliOl_o : STD_LOGIC; + SIGNAL wire_niliOl_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nill0O_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nill0O_o : STD_LOGIC; + SIGNAL wire_nill0O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nill1i_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nill1i_o : STD_LOGIC; + SIGNAL wire_nill1i_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nill1O_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nill1O_o : STD_LOGIC; + SIGNAL wire_nill1O_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nillil_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nillil_o : STD_LOGIC; + SIGNAL wire_nillil_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nillli_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nillli_o : STD_LOGIC; + SIGNAL wire_nillli_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilllO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nilllO_o : STD_LOGIC; + SIGNAL wire_nilllO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nillOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nillOl_o : STD_LOGIC; + SIGNAL wire_nillOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilO0l_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nilO0l_o : STD_LOGIC; + SIGNAL wire_nilO0l_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nilO1i_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nilO1i_o : STD_LOGIC; + SIGNAL wire_nilO1i_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nilO1O_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilO1O_o : STD_LOGIC; + SIGNAL wire_nilO1O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilOii_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilOii_o : STD_LOGIC; + SIGNAL wire_nilOii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilOiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOiO_o : STD_LOGIC; + SIGNAL wire_nilOiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOli_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilOli_o : STD_LOGIC; + SIGNAL wire_nilOli_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilOlO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOlO_o : STD_LOGIC; + SIGNAL wire_nilOlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOOl_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nilOOl_o : STD_LOGIC; + SIGNAL wire_nilOOl_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_niO11i_data : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_niO11i_o : STD_LOGIC; + SIGNAL wire_niO11i_sel : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nlilOi_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilOi_o : STD_LOGIC; + SIGNAL wire_nlilOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliO0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliO0l_o : STD_LOGIC; + SIGNAL wire_nliO0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliO1i_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliO1i_o : STD_LOGIC; + SIGNAL wire_nliO1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliO1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliO1O_o : STD_LOGIC; + SIGNAL wire_nliO1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliOii_o : STD_LOGIC; + SIGNAL wire_nliOii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliOli_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOli_o : STD_LOGIC; + SIGNAL wire_nliOli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOlO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOlO_o : STD_LOGIC; + SIGNAL wire_nliOlO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOOi_o : STD_LOGIC; + SIGNAL wire_nliOOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliOOl_o : STD_LOGIC; + SIGNAL wire_nliOOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll00O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll00O_o : STD_LOGIC; + SIGNAL wire_nll00O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll01i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll01i_o : STD_LOGIC; + SIGNAL wire_nll01i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll01O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll01O_o : STD_LOGIC; + SIGNAL wire_nll01O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0iO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0iO_o : STD_LOGIC; + SIGNAL wire_nll0iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0lO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0lO_o : STD_LOGIC; + SIGNAL wire_nll0lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0OO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0OO_o : STD_LOGIC; + SIGNAL wire_nll0OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll10i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll10i_o : STD_LOGIC; + SIGNAL wire_nll10i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll10O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll10O_o : STD_LOGIC; + SIGNAL wire_nll10O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll11l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll11l_o : STD_LOGIC; + SIGNAL wire_nll11l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1il_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nll1il_o : STD_LOGIC; + SIGNAL wire_nll1il_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nll1ll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1ll_o : STD_LOGIC; + SIGNAL wire_nll1ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1Ol_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nll1Ol_o : STD_LOGIC; + SIGNAL wire_nll1Ol_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlli0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlli0i_o : STD_LOGIC; + SIGNAL wire_nlli0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlliil_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlliil_o : STD_LOGIC; + SIGNAL wire_nlliil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllili_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllili_o : STD_LOGIC; + SIGNAL wire_nllili_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllilO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllilO_o : STD_LOGIC; + SIGNAL wire_nllilO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlliOi_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlliOi_o : STD_LOGIC; + SIGNAL wire_nlliOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlliOO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlliOO_o : STD_LOGIC; + SIGNAL wire_nlliOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlll0i_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlll0i_o : STD_LOGIC; + SIGNAL wire_nlll0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlll0O_data : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlll0O_o : STD_LOGIC; + SIGNAL wire_nlll0O_sel : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlll1l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlll1l_o : STD_LOGIC; + SIGNAL wire_nlll1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rpmadwidth_tx2w5w6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rpmadwidth_tx2w5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpmadwidth_tx2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rbist_sel_range12w20w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rcxpat_chnl_sel_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni000l1442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0iOi1037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0iOl1019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0iOO996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l0l913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l0O912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l1i983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l1l970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l1O957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0lii914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0lil911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0liO910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0lll909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0llO908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0lOl907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0O0i894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0O0O893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0O1i896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0O1l895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0Oii1237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0Oil891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0OiO892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0Oli906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0OOi889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0OOl888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni1lll2233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni1Oil2081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii00l246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii01i291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii01l267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii0ii229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii0ll204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii0Ol176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii11i695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nii1Ol312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiiil107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiiiO106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiili108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiill105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiilO447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiiOi102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiiOl103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiiOO104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niil0l99w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niil0O98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niil1O100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilii97w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilil96w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiliO95w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiOOi445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpma_doublewidth_tx1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset93w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rbist_sel_range14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rcxpat_chnl_sel_range757w758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni000i : STD_LOGIC; + SIGNAL ni000l : STD_LOGIC; + SIGNAL ni000O : STD_LOGIC; + SIGNAL ni001i : STD_LOGIC; + SIGNAL ni001O : STD_LOGIC; + SIGNAL ni00ii : STD_LOGIC; + SIGNAL ni00il : STD_LOGIC; + SIGNAL ni00iO : STD_LOGIC; + SIGNAL ni00li : STD_LOGIC; + SIGNAL ni00ll : STD_LOGIC; + SIGNAL ni00lO : STD_LOGIC; + SIGNAL ni00Oi : STD_LOGIC; + SIGNAL ni00Ol : STD_LOGIC; + SIGNAL ni00OO : STD_LOGIC; + SIGNAL ni010i : STD_LOGIC; + SIGNAL ni010l : STD_LOGIC; + SIGNAL ni010O : STD_LOGIC; + SIGNAL ni011i : STD_LOGIC; + SIGNAL ni011l : STD_LOGIC; + SIGNAL ni011O : STD_LOGIC; + SIGNAL ni01ii : STD_LOGIC; + SIGNAL ni01il : STD_LOGIC; + SIGNAL ni01iO : STD_LOGIC; + SIGNAL ni01li : STD_LOGIC; + SIGNAL ni01ll : STD_LOGIC; + SIGNAL ni01lO : STD_LOGIC; + SIGNAL ni01Oi : STD_LOGIC; + SIGNAL ni01Ol : STD_LOGIC; + SIGNAL ni01OO : STD_LOGIC; + SIGNAL ni0i0i : STD_LOGIC; + SIGNAL ni0i0l : STD_LOGIC; + SIGNAL ni0i0O : STD_LOGIC; + SIGNAL ni0i1i : STD_LOGIC; + SIGNAL ni0i1l : STD_LOGIC; + SIGNAL ni0i1O : STD_LOGIC; + SIGNAL ni0iii : STD_LOGIC; + SIGNAL ni0iil : STD_LOGIC; + SIGNAL ni0iiO : STD_LOGIC; + SIGNAL ni0ili : STD_LOGIC; + SIGNAL ni0ill : STD_LOGIC; + SIGNAL ni0ilO : STD_LOGIC; + SIGNAL ni0iOi : STD_LOGIC; + SIGNAL ni0iOl : STD_LOGIC; + SIGNAL ni0iOO : STD_LOGIC; + SIGNAL ni0l0i : STD_LOGIC; + SIGNAL ni0l0l : STD_LOGIC; + SIGNAL ni0l0O : STD_LOGIC; + SIGNAL ni0l1i : STD_LOGIC; + SIGNAL ni0l1l : STD_LOGIC; + SIGNAL ni0l1O : STD_LOGIC; + SIGNAL ni0lii : STD_LOGIC; + SIGNAL ni0lil : STD_LOGIC; + SIGNAL ni0liO : STD_LOGIC; + SIGNAL ni0lli : STD_LOGIC; + SIGNAL ni0lll : STD_LOGIC; + SIGNAL ni0llO : STD_LOGIC; + SIGNAL ni0lOi : STD_LOGIC; + SIGNAL ni0lOl : STD_LOGIC; + SIGNAL ni0lOO : STD_LOGIC; + SIGNAL ni0O0i : STD_LOGIC; + SIGNAL ni0O0l : STD_LOGIC; + SIGNAL ni0O0O : STD_LOGIC; + SIGNAL ni0O1i : STD_LOGIC; + SIGNAL ni0O1l : STD_LOGIC; + SIGNAL ni0O1O : STD_LOGIC; + SIGNAL ni0Oii : STD_LOGIC; + SIGNAL ni0Oil : STD_LOGIC; + SIGNAL ni0OiO : STD_LOGIC; + SIGNAL ni0Oli : STD_LOGIC; + SIGNAL ni0Oll : STD_LOGIC; + SIGNAL ni0OlO : STD_LOGIC; + SIGNAL ni0OOi : STD_LOGIC; + SIGNAL ni0OOl : STD_LOGIC; + SIGNAL ni0OOO : STD_LOGIC; + SIGNAL ni1lll : STD_LOGIC; + SIGNAL ni1llO : STD_LOGIC; + SIGNAL ni1lOi : STD_LOGIC; + SIGNAL ni1lOl : STD_LOGIC; + SIGNAL ni1lOO : STD_LOGIC; + SIGNAL ni1O0i : STD_LOGIC; + SIGNAL ni1O0l : STD_LOGIC; + SIGNAL ni1O0O : STD_LOGIC; + SIGNAL ni1O1i : STD_LOGIC; + SIGNAL ni1O1l : STD_LOGIC; + SIGNAL ni1O1O : STD_LOGIC; + SIGNAL ni1Oii : STD_LOGIC; + SIGNAL ni1Oil : STD_LOGIC; + SIGNAL ni1OiO : STD_LOGIC; + SIGNAL ni1Oli : STD_LOGIC; + SIGNAL ni1Oll : STD_LOGIC; + SIGNAL ni1OlO : STD_LOGIC; + SIGNAL ni1OOi : STD_LOGIC; + SIGNAL ni1OOl : STD_LOGIC; + SIGNAL ni1OOO : STD_LOGIC; + SIGNAL nii00l : STD_LOGIC; + SIGNAL nii01i : STD_LOGIC; + SIGNAL nii01l : STD_LOGIC; + SIGNAL nii0ii : STD_LOGIC; + SIGNAL nii0ll : STD_LOGIC; + SIGNAL nii0Ol : STD_LOGIC; + SIGNAL nii10i : STD_LOGIC; + SIGNAL nii10l : STD_LOGIC; + SIGNAL nii10O : STD_LOGIC; + SIGNAL nii11i : STD_LOGIC; + SIGNAL nii11l : STD_LOGIC; + SIGNAL nii11O : STD_LOGIC; + SIGNAL nii1ii : STD_LOGIC; + SIGNAL nii1il : STD_LOGIC; + SIGNAL nii1iO : STD_LOGIC; + SIGNAL nii1li : STD_LOGIC; + SIGNAL nii1ll : STD_LOGIC; + SIGNAL nii1lO : STD_LOGIC; + SIGNAL nii1Oi : STD_LOGIC; + SIGNAL nii1Ol : STD_LOGIC; + SIGNAL niii0l : STD_LOGIC; + SIGNAL niiiil : STD_LOGIC; + SIGNAL niiiiO : STD_LOGIC; + SIGNAL niiili : STD_LOGIC; + SIGNAL niiill : STD_LOGIC; + SIGNAL niiilO : STD_LOGIC; + SIGNAL niiiOi : STD_LOGIC; + SIGNAL niiiOl : STD_LOGIC; + SIGNAL niiiOO : STD_LOGIC; + SIGNAL niil0i : STD_LOGIC; + SIGNAL niil0l : STD_LOGIC; + SIGNAL niil0O : STD_LOGIC; + SIGNAL niil1i : STD_LOGIC; + SIGNAL niil1l : STD_LOGIC; + SIGNAL niil1O : STD_LOGIC; + SIGNAL niilii : STD_LOGIC; + SIGNAL niilil : STD_LOGIC; + SIGNAL niiliO : STD_LOGIC; + SIGNAL niilli : STD_LOGIC; + SIGNAL niilll : STD_LOGIC; + SIGNAL niilOl : STD_LOGIC; + SIGNAL niiOil : STD_LOGIC; + SIGNAL niiOiO : STD_LOGIC; + SIGNAL niiOli : STD_LOGIC; + SIGNAL niiOOi : STD_LOGIC; + SIGNAL wire_w_rbist_sel_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rbist_sel_range14w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rcxpat_chnl_sel_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rcxpat_chnl_sel_range757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_w_lg_w_lg_w_lg_rpmadwidth_tx2w5w6w(0) <= wire_w_lg_w_lg_rpmadwidth_tx2w5w(0) AND rdwidth_tx; + wire_w_lg_w_lg_rpmadwidth_tx2w5w(0) <= wire_w_lg_rpmadwidth_tx2w(0) AND wire_nil11i2_w_lg_q4w(0); + wire_w_lg_rpmadwidth_tx2w(0) <= rpmadwidth_tx AND wire_w_lg_rpma_doublewidth_tx1w(0); + wire_w_lg_w_rbist_sel_range12w20w(0) <= wire_w_rbist_sel_range12w(0) AND wire_w_lg_w_rbist_sel_range14w15w(0); + wire_w_lg_w_rcxpat_chnl_sel_range755w760w(0) <= wire_w_rcxpat_chnl_sel_range755w(0) AND wire_w_lg_w_rcxpat_chnl_sel_range757w758w(0); + wire_w_lg_ni000l1442w(0) <= NOT ni000l; + wire_w_lg_ni0iOi1037w(0) <= NOT ni0iOi; + wire_w_lg_ni0iOl1019w(0) <= NOT ni0iOl; + wire_w_lg_ni0iOO996w(0) <= NOT ni0iOO; + wire_w_lg_ni0l0l913w(0) <= NOT ni0l0l; + wire_w_lg_ni0l0O912w(0) <= NOT ni0l0O; + wire_w_lg_ni0l1i983w(0) <= NOT ni0l1i; + wire_w_lg_ni0l1l970w(0) <= NOT ni0l1l; + wire_w_lg_ni0l1O957w(0) <= NOT ni0l1O; + wire_w_lg_ni0lii914w(0) <= NOT ni0lii; + wire_w_lg_ni0lil911w(0) <= NOT ni0lil; + wire_w_lg_ni0liO910w(0) <= NOT ni0liO; + wire_w_lg_ni0lll909w(0) <= NOT ni0lll; + wire_w_lg_ni0llO908w(0) <= NOT ni0llO; + wire_w_lg_ni0lOl907w(0) <= NOT ni0lOl; + wire_w_lg_ni0O0i894w(0) <= NOT ni0O0i; + wire_w_lg_ni0O0O893w(0) <= NOT ni0O0O; + wire_w_lg_ni0O1i896w(0) <= NOT ni0O1i; + wire_w_lg_ni0O1l895w(0) <= NOT ni0O1l; + wire_w_lg_ni0Oii1237w(0) <= NOT ni0Oii; + wire_w_lg_ni0Oil891w(0) <= NOT ni0Oil; + wire_w_lg_ni0OiO892w(0) <= NOT ni0OiO; + wire_w_lg_ni0Oli906w(0) <= NOT ni0Oli; + wire_w_lg_ni0OOi889w(0) <= NOT ni0OOi; + wire_w_lg_ni0OOl888w(0) <= NOT ni0OOl; + wire_w_lg_ni1lll2233w(0) <= NOT ni1lll; + wire_w_lg_ni1Oil2081w(0) <= NOT ni1Oil; + wire_w_lg_nii00l246w(0) <= NOT nii00l; + wire_w_lg_nii01i291w(0) <= NOT nii01i; + wire_w_lg_nii01l267w(0) <= NOT nii01l; + wire_w_lg_nii0ii229w(0) <= NOT nii0ii; + wire_w_lg_nii0ll204w(0) <= NOT nii0ll; + wire_w_lg_nii0Ol176w(0) <= NOT nii0Ol; + wire_w_lg_nii11i695w(0) <= NOT nii11i; + wire_w_lg_nii1Ol312w(0) <= NOT nii1Ol; + wire_w_lg_niiiil107w(0) <= NOT niiiil; + wire_w_lg_niiiiO106w(0) <= NOT niiiiO; + wire_w_lg_niiili108w(0) <= NOT niiili; + wire_w_lg_niiill105w(0) <= NOT niiill; + wire_w_lg_niiilO447w(0) <= NOT niiilO; + wire_w_lg_niiiOi102w(0) <= NOT niiiOi; + wire_w_lg_niiiOl103w(0) <= NOT niiiOl; + wire_w_lg_niiiOO104w(0) <= NOT niiiOO; + wire_w_lg_niil0l99w(0) <= NOT niil0l; + wire_w_lg_niil0O98w(0) <= NOT niil0O; + wire_w_lg_niil1O100w(0) <= NOT niil1O; + wire_w_lg_niilii97w(0) <= NOT niilii; + wire_w_lg_niilil96w(0) <= NOT niilil; + wire_w_lg_niiliO95w(0) <= NOT niiliO; + wire_w_lg_niiOOi445w(0) <= NOT niiOOi; + wire_w_lg_rpma_doublewidth_tx1w(0) <= NOT rpma_doublewidth_tx; + wire_w_lg_soft_reset93w(0) <= NOT soft_reset; + wire_w_lg_w_rbist_sel_range14w15w(0) <= NOT wire_w_rbist_sel_range14w(0); + wire_w_lg_w_rcxpat_chnl_sel_range757w758w(0) <= NOT wire_w_rcxpat_chnl_sel_range757w(0); + bist_ctl_sg <= ( wire_ni1O_dataout & wire_ni1l_dataout); + bist_data_sg <= ( wire_ni1i_dataout & wire_n0OO_dataout & wire_n0Ol_dataout & wire_n0Oi_dataout & wire_n0lO_dataout & wire_n0ll_dataout & wire_n0li_dataout & wire_n0iO_dataout & wire_n0il_dataout & wire_n0ii_dataout & wire_n00O_dataout & wire_n00l_dataout & wire_n00i_dataout & wire_n01O_dataout & wire_n01l_dataout & wire_n01i_dataout); + ni000i <= (((((((((((((n1liO OR n1lii) OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil); + ni000l <= ((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1iiO) OR n1i0O) OR n1i0l); + ni000O <= (((((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii); + ni001i <= (((((wire_nl0OOO_w_lg_w_lg_w_lg_nl0iOl2241w2243w2245w(0) AND wire_nl0OOO_w_lg_nl0ill2246w(0)) AND wire_nl0OOO_w_lg_nl0ili2248w(0)) AND nl0iiO) AND nl0iil) AND nl0iii); + ni001O <= (nli11i OR nl0OOi); + ni00ii <= (((((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1i0l); + ni00il <= (((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1i0O) OR n1i0l); + ni00iO <= (((((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni00li <= (((((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni00ll <= ((((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni00lO <= ((((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1l1O) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni00Oi <= (((((((((((n1liO OR n1lii) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni00Ol <= (((((((((((((((n1liO OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni00OO <= (((((((((((wire_n1l0O_w_lg_n1l0i1211w(0) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1i0O); + ni010i <= ((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni010l <= (((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni010O <= ((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni011i <= (((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O1O); + ni011l <= ((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0i) OR nl0O1O); + ni011O <= (((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni01ii <= (((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni01il <= ((((((((nl0OOl OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni01iO <= (((((((((nl0OOl OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni01li <= (((((((((nl0OlO OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni01ll <= ((((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni01lO <= ((((((((nl0OOl OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l); + ni01Oi <= (((((((nl0iOl AND nl0iOi) AND nl0ilO) AND nl0ill) AND nl0ili) AND nl0iiO) AND nl0iil) AND nl0iii); + ni01Ol <= ((((((nl00Ol AND nl00Oi) AND nl00lO) AND nl00ll) AND nl00li) AND nl00iO) AND nl00il); + ni01OO <= ((((wire_nl0OOO_w_lg_w_lg_w_lg_w_lg_nl0iOl2241w2243w2245w2253w(0) AND wire_nl0OOO_w_lg_nl0ili2248w(0)) AND wire_nl0OOO_w_lg_nl0iiO2255w(0)) AND wire_nl0OOO_w_lg_nl0iil2257w(0)) AND wire_nl0OOO_w_lg_nl0iii2259w(0)); + ni0i0i <= ((((((n1lii OR n1l1O) OR n1l1l) OR n1iOO) OR n1ill) OR n1ili) OR n1iil); + ni0i0l <= (((((((((n1liO OR n1l0l) OR n1l0i) OR n1l1i) OR n1iOl) OR n1ilO) OR n1iiO) OR n1iii) OR n1i0O) OR n1i0l); + ni0i0O <= (((((((((((n1l0l OR n1l0i) OR n1l1l) OR n1l1i) OR n1iOl) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iii) OR n1i0O) OR n1i0l); + ni0i1i <= ((((((((((((((n1lii OR n1l0l) OR n1l0i) OR n1l1O) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iOl) OR n1iOi) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1i0O); + ni0i1l <= (((((((((n1lii OR n1l0l) OR n1l0i) OR n1l1O) OR n1iOO) OR n1iOl) OR n1ilO) OR n1ill) OR n1iiO) OR n1iil); + ni0i1O <= ((((((n1liO OR n1l1l) OR n1l1i) OR n1ili) OR n1iii) OR n1i0O) OR n1i0l); + ni0iii <= ((((n1liO OR n1lii) OR n1l1O) OR n1iOO) OR n1iil); + ni0iil <= (((((((((((n1lii OR n1l1O) OR n1l1l) OR n1iOO) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni0iiO <= ((((n1liO OR n1l0l) OR n1l0i) OR n1l1i) OR n1iOl); + ni0ili <= ((((((((((((n1lii OR n1l0l) OR n1l0i) OR n1l1l) OR n1l1i) OR n1iOl) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iii) OR n1i0O) OR n1i0l); + ni0ill <= (((((((n1lii OR n1l0l) OR n1l0i) OR n1l1l) OR n1l1i) OR n1iOO) OR n1iiO) OR n1i0O); + ni0ilO <= (((((((wire_n1lil_w_lg_n1liO1051w(0) OR n1iOl) OR n1ilO) OR n1ill) OR n1ili) OR n1iil) OR n1iii) OR n1i0l); + ni0iOi <= (((((((((((n1liO OR n1l0i) OR n1l1O) OR n1l1l) OR n1iOO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni0iOl <= (((((((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1iOO) OR n1iOl) OR n1ilO) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni0iOO <= ((((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1iOO) OR n1iOl) OR n1iiO) OR n1i0O) OR n1i0l); + ni0l0i <= (((((((n1liO OR n1lii) OR n1l0i) OR n1l1O) OR n1l1l) OR n1iiO) OR n1i0O) OR n1i0l); + ni0l0l <= ((nlOOiO AND wire_n1l0O_w_lg_nlOOil1477w(0)) AND nliliO); + ni0l0O <= ((nlOOiO AND nlOOil) AND wire_n1l0O_w_lg_nliliO1544w(0)); + ni0l1i <= ((((((n1liO OR n1l0i) OR n1l1i) OR n1iOi) OR n1iiO) OR n1i0O) OR n1i0l); + ni0l1l <= ((((((n1liO OR n1lii) OR n1l0l) OR n1l0i) OR n1iiO) OR n1i0O) OR n1i0l); + ni0l1O <= ((((((((((n1liO OR n1l0i) OR n1iOl) OR n1iOi) OR n1ill) OR n1ili) OR n1iiO) OR n1iil) OR n1iii) OR n1i0O) OR n1i0l); + ni0lii <= (wire_n1l0O_w_lg_w_lg_nlOOiO1476w1543w(0) AND wire_n1l0O_w_lg_nliliO1544w(0)); + ni0lil <= ((((wire_n1l0O_w_lg_w_lg_nlOOOO1529w1530w(0) AND wire_n1l0O_w_lg_nlOOOi1531w(0)) AND wire_n1l0O_w_lg_nlOOlO1533w(0)) AND nlOOll) AND nlOOli); + ni0liO <= ((((wire_n1l0O_w_lg_nlOOOO1538w(0) AND wire_n1l0O_w_lg_nlOOOi1531w(0)) AND nlOOlO) AND nlOOll) AND nlOOli); + ni0lli <= ((wire_n1l0O_w_lg_n111O1524w(0) AND n111l) AND n111i); + ni0lll <= ((n111O AND n111l) AND n111i); + ni0llO <= (wire_n1l0O_w_lg_w_lg_w_lg_n11ii897w899w900w(0) AND wire_n1l0O_w_lg_n110i1516w(0)); + ni0lOi <= (((wire_n1l0O_w_lg_n11ii897w(0) AND n110O) AND n110l) AND n110i); + ni0lOl <= (((n11ii AND n110O) AND n110l) AND n110i); + ni0lOO <= (wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n11ii897w899w900w901w(0) OR wire_n1l0O_w_lg_w_lg_w_lg_n11ii902w903w904w(0)); + ni0O0i <= (wire_n1l0O_w_lg_w_lg_w_lg_w1501w1502w1503w1504w(0) AND n11il); + ni0O0l <= ((((((wire_n1l0O_w_lg_w_lg_w_lg_n101i1480w1482w1483w(0) AND wire_n1l0O_w_lg_n11Oi1484w(0)) AND wire_n1l0O_w_lg_n11lO1486w(0)) AND wire_n1l0O_w_lg_n11ll1488w(0)) AND wire_n1l0O_w_lg_n11li1490w(0)) AND wire_n1l0O_w_lg_n11iO1492w(0)) AND wire_n1l0O_w_lg_n11il1494w(0)); + ni0O0O <= (wire_n1l0O_w_lg_w_lg_w_lg_w1501w1502w1503w1504w(0) AND wire_n1l0O_w_lg_n11il1494w(0)); + ni0O1i <= (wire_n1l0O_w_lg_w_lg_w1510w1511w1512w(0) AND n11il); + ni0O1l <= (wire_n1l0O_w_lg_w_lg_w1510w1511w1512w(0) AND wire_n1l0O_w_lg_n11il1494w(0)); + ni0O1O <= ((((((wire_n1l0O_w_lg_w_lg_w_lg_n101i1480w1482w1483w(0) AND wire_n1l0O_w_lg_n11Oi1484w(0)) AND wire_n1l0O_w_lg_n11lO1486w(0)) AND wire_n1l0O_w_lg_n11ll1488w(0)) AND wire_n1l0O_w_lg_n11li1490w(0)) AND wire_n1l0O_w_lg_n11iO1492w(0)) AND n11il); + ni0Oii <= ((NOT rcxpat_chnl_sel(0)) AND wire_w_lg_w_rcxpat_chnl_sel_range757w758w(0)); + ni0Oil <= ((wire_n1l0O_w_lg_nlOOiO1476w(0) AND wire_n1l0O_w_lg_nlOOil1477w(0)) AND nliliO); + ni0OiO <= (ni0Oll OR ni0Oli); + ni0Oli <= ((NOT rcxpat_chnl_sel(0)) AND rcxpat_chnl_sel(1)); + ni0Oll <= wire_w_lg_w_rcxpat_chnl_sel_range755w760w(0); + ni0OlO <= ((((n1lii OR n1iiO) OR n1iii) OR n1i0O) OR n1i0l); + ni0OOi <= ((((((n1liO OR n1l0l) OR n1l0i) OR n1l1O) OR n1ill) OR n1ili) OR n1i0l); + ni0OOl <= ((((((n1liO OR n1l0l) OR n1l1O) OR n1l1l) OR n1ili) OR n1i0O) OR n1i0l); + ni0OOO <= (((((((((((((((((wire_nliiO_w_lg_w_lg_nlili109w110w(0) OR nli0i) OR nli1O) OR nli1l) OR nli1i) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O); + ni1lll <= ((((((nli11O OR nl0OOi) OR nl0Oll) OR nl0OiO) OR nl0Oii) OR nl0O0l) OR nl0O1O); + ni1llO <= (((((((((nli11O OR nli11i) OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0i); + ni1lOi <= (((((((((nli11O OR nli11i) OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O1O); + ni1lOl <= ((((((((((nli11i OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni1lOO <= ((((((((((nli11i OR nl0OOl) OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0i) OR nl0O1O); + ni1O0i <= ((((((nl0Oli OR nl0OiO) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni1O0l <= ((((nli11O OR nli11i) OR nl0OlO) OR nl0Oll) OR nl0Oil); + ni1O0O <= (((((((nli11i OR nl0OOl) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni1O1i <= (((((((((((nli11i OR nl0OOl) OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni1O1l <= (((((((nli11i OR nl0OOl) OR nl0Oll) OR nl0OiO) OR nl0O0O) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni1O1O <= ((((nli11O OR nl0OlO) OR nl0Oli) OR nl0Oil) OR nl0Oii); + ni1Oii <= ((((nli11O OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO); + ni1Oil <= (((((((((nli11O OR nli11i) OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0l) OR nl0O1O); + ni1OiO <= ((((((((((nli11O OR nli11i) OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0l) OR nl0O0i) OR nl0O1O); + ni1Oli <= ((((((nli11O OR nl0OOl) OR nl0Oll) OR nl0OiO) OR nl0Oii) OR nl0O0l) OR nl0O1O); + ni1Oll <= ((((((nli11O OR nl0Oll) OR nl0OiO) OR nl0Oii) OR nl0O0O) OR nl0O0l) OR nl0O1O); + ni1OlO <= (((((nli11O OR nl0Oll) OR nl0OiO) OR nl0Oii) OR nl0O0l) OR nl0O1O); + ni1OOi <= ((((((nli11O OR nl0Oll) OR nl0OiO) OR nl0Oil) OR nl0Oii) OR nl0O0l) OR nl0O1O); + ni1OOl <= (((((((nli11O OR nli11i) OR nl0OlO) OR nl0Oll) OR nl0OiO) OR nl0Oii) OR nl0O0l) OR nl0O1O); + ni1OOO <= (((((((nli11O OR nl0OlO) OR nl0Oll) OR nl0Oli) OR nl0OiO) OR nl0Oii) OR nl0O0l) OR nl0O1O); + nii00l <= ((((((((wire_nliiO_w_lg_w188w189w(0) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0li) OR nl0il) OR nl01O) OR nl01i) OR nl1OO); + nii01i <= ((((((((((((((((wire_nliiO_w_lg_w_lg_w_lg_nlili109w184w185w(0) OR nli1O) OR nli1i) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii01l <= (wire_nliiO_w262w(0) OR (NOT (nii01O42 XOR nii01O41))); + nii0ii <= (wire_nliiO_w223w(0) OR (NOT (nii0il38 XOR nii0il37))); + nii0ll <= (wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w199w(0) OR (NOT (nii0lO34 XOR nii0lO33))); + nii0Ol <= (((((((((((((wire_nliiO_w_lg_w_lg_w_lg_nlili160w161w162w(0) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0li) OR nl0il) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii10i <= ((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl01i) OR nl1OO); + nii10l <= ((((((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) OR nl0ll) OR nl0li) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii10O <= ((((((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii11i <= (((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl01O) OR nl01i) OR nl1OO); + nii11l <= ((((((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l); + nii11O <= ((((((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl1OO); + nii1ii <= ((((((((((((wire_nliiO_w_lg_w_lg_w_lg_w188w189w190w191w(0) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii1il <= ((((((((((((((wire_nliiO_w_lg_w188w189w(0) OR nl0Oi) OR nl0lO) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii1iO <= ((((((((((((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili109w184w185w186w187w(0) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii1li <= ((((((((((((((((((wire_nliiO_w_lg_w_lg_w_lg_nlili109w184w185w(0) OR nli1l) OR nli1i) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii1ll <= ((((((((((((((((((nlili OR nli0i) OR nli1O) OR nli1l) OR nli1i) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0ll) OR nl0li) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + nii1lO <= ((((((((((((((((((nli0l OR nli0i) OR nli1O) OR nli1l) OR nli1i) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01i); + nii1Oi <= ((((((((((((((((((((nliil OR nli0O) OR nli0l) OR nli0i) OR nli1O) OR nli1l) OR nli1i) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0ll) OR nl0li) OR nl0iO) OR nl0il) OR nl0ii) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01i); + nii1Ol <= (((((((((((wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili160w161w162w254w(0) OR nl0Oi) OR nl0lO) OR nl0li) OR nl0il) OR nl00O) OR nl00l) OR nl00i) OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + niii0l <= (wire_nliiO_w_lg_w_lg_w120w121w122w(0) OR (NOT (niii0O22 XOR niii0O21))); + niiiil <= ((niO0O AND wire_nliii_w_lg_niO0l763w(0)) AND n0lOi); + niiiiO <= ((niO0O AND niO0l) AND wire_nliii_w_lg_n0lOi772w(0)); + niiili <= (wire_nliii_w_lg_w_lg_niO0O762w771w(0) AND wire_nliii_w_lg_n0lOi772w(0)); + niiill <= (wire_nliii_w_lg_w_lg_w_lg_niOll766w767w768w(0) AND wire_nliii_w_lg_niOii769w(0)); + niiilO <= ((NOT rcxpat_chnl_sel(0)) AND wire_w_lg_w_rcxpat_chnl_sel_range757w758w(0)); + niiiOi <= ((wire_nliii_w_lg_niO0O762w(0) AND wire_nliii_w_lg_niO0l763w(0)) AND n0lOi); + niiiOl <= (niil1i OR niiiOO); + niiiOO <= ((NOT rcxpat_chnl_sel(0)) AND rcxpat_chnl_sel(1)); + niil0i <= (((((((((nliil OR nli0i) OR nli1O) OR nli1l) OR nli1i) OR nl0OO) OR nl0Ol) OR nl0Oi) OR nl0ll) OR nl0li); + niil0l <= ((((((((wire_nliiO_w_lg_nlili109w(0) OR nli1l) OR nl0OO) OR nl0Oi) OR nl0li) OR nl0il) OR nl0ii) OR nl00O) OR nl00i); + niil0O <= (((((((((nlili OR nli0O) OR nli0l) OR nli1O) OR nli1l) OR nli1i) OR nl0Oi) OR nl0lO) OR nl0iO) OR nl00l); + niil1i <= wire_w_lg_w_rcxpat_chnl_sel_range755w760w(0); + niil1l <= ((((nliil OR nl01O) OR nl01l) OR nl01i) OR nl1OO); + niil1O <= (((((((nlili OR nli0i) OR nl0lO) OR nl0ll) OR nl0ii) OR nl01l) OR nl01i) OR nl1OO); + niilii <= (((((nlili OR nli1l) OR nli1i) OR nl0OO) OR nl0Ol) OR nl00l); + niilil <= (((((((((((nlili OR nli0O) OR nli0l) OR nli1O) OR nli1i) OR nl0Ol) OR nl0lO) OR nl0ll) OR nl0il) OR nl00l) OR nl00i) OR nl1OO); + niiliO <= (((((((((nlili OR nli0i) OR nli1l) OR nl0Ol) OR nl0Oi) OR nl0lO) OR nl0iO) OR nl00l) OR nl01l) OR nl1OO); + niilli <= (((((((((nliil OR nli0l) OR nli0i) OR nli1O) OR nl0Ol) OR nl0Oi) OR nl0li) OR nl0ii) OR nl01O) OR nl01l); + niilll <= '1'; + niilOl <= '0'; + niiOil <= (((NOT rbist_sel(0)) AND wire_w_lg_w_rbist_sel_range14w15w(0)) AND (niiO0O8 XOR niiO0O7)); + niiOiO <= (wire_w_lg_w_rbist_sel_range12w20w(0) AND (niiO0i10 XOR niiO0i9)); + niiOli <= (((NOT rbist_sel(0)) AND rbist_sel(1)) AND (niiO1l12 XOR niiO1l11)); + niiOOi <= (wire_w_lg_w_lg_w_lg_rpmadwidth_tx2w5w6w(0) OR ((rpmadwidth_tx AND rpma_doublewidth_tx) AND (niiOOl4 XOR niiOOl3))); + wire_w_rbist_sel_range12w(0) <= rbist_sel(0); + wire_w_rbist_sel_range14w(0) <= rbist_sel(1); + wire_w_rcxpat_chnl_sel_range755w(0) <= rcxpat_chnl_sel(0); + wire_w_rcxpat_chnl_sel_range757w(0) <= rcxpat_chnl_sel(1); + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN ni001l45 <= ni001l46; + END IF; + if (now = 0 ns) then + ni001l45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN ni001l46 <= ni001l45; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii00O39 <= nii00O40; + END IF; + if (now = 0 ns) then + nii00O39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii00O40 <= nii00O39; + END IF; + END PROCESS; + wire_nii00O40_w_lg_w_lg_q228w230w(0) <= wire_nii00O40_w_lg_q228w(0) AND wire_w_lg_nii0ii229w(0); + wire_nii00O40_w_lg_q228w(0) <= nii00O40 XOR nii00O39; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii01O41 <= nii01O42; + END IF; + if (now = 0 ns) then + nii01O41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii01O42 <= nii01O41; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0il37 <= nii0il38; + END IF; + if (now = 0 ns) then + nii0il37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0il38 <= nii0il37; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0li35 <= nii0li36; + END IF; + if (now = 0 ns) then + nii0li35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0li36 <= nii0li35; + END IF; + END PROCESS; + wire_nii0li36_w_lg_w_lg_q207w208w(0) <= wire_nii0li36_w_lg_q207w(0) AND nii0ll; + wire_nii0li36_w_lg_q207w(0) <= nii0li36 XOR nii0li35; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0lO33 <= nii0lO34; + END IF; + if (now = 0 ns) then + nii0lO33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0lO34 <= nii0lO33; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0OO31 <= nii0OO32; + END IF; + if (now = 0 ns) then + nii0OO31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii0OO32 <= nii0OO31; + END IF; + END PROCESS; + wire_nii0OO32_w_lg_w_lg_q155w156w(0) <= wire_nii0OO32_w_lg_q155w(0) AND wire_nilli_dataout; + wire_nii0OO32_w_lg_q155w(0) <= nii0OO32 XOR nii0OO31; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii1OO43 <= nii1OO44; + END IF; + if (now = 0 ns) then + nii1OO43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nii1OO44 <= nii1OO43; + END IF; + END PROCESS; + wire_nii1OO44_w_lg_w_lg_q295w296w(0) <= wire_nii1OO44_w_lg_q295w(0) AND niiOOi; + wire_nii1OO44_w_lg_q295w(0) <= nii1OO44 XOR nii1OO43; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii0i23 <= niii0i24; + END IF; + if (now = 0 ns) then + niii0i23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii0i24 <= niii0i23; + END IF; + END PROCESS; + wire_niii0i24_w_lg_w_lg_q129w130w(0) <= wire_niii0i24_w_lg_q129w(0) AND nl00i; + wire_niii0i24_w_lg_q129w(0) <= niii0i24 XOR niii0i23; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii0O21 <= niii0O22; + END IF; + if (now = 0 ns) then + niii0O21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii0O22 <= niii0O21; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii1i29 <= niii1i30; + END IF; + if (now = 0 ns) then + niii1i29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii1i30 <= niii1i29; + END IF; + END PROCESS; + wire_niii1i30_w_lg_w_lg_q152w153w(0) <= wire_niii1i30_w_lg_q152w(0) AND niiOOi; + wire_niii1i30_w_lg_q152w(0) <= niii1i30 XOR niii1i29; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii1l27 <= niii1l28; + END IF; + if (now = 0 ns) then + niii1l27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii1l28 <= niii1l27; + END IF; + END PROCESS; + wire_niii1l28_w_lg_w_lg_q141w142w(0) <= wire_niii1l28_w_lg_q141w(0) AND niii0l; + wire_niii1l28_w_lg_q141w(0) <= niii1l28 XOR niii1l27; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii1O25 <= niii1O26; + END IF; + if (now = 0 ns) then + niii1O25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niii1O26 <= niii1O25; + END IF; + END PROCESS; + wire_niii1O26_w_lg_w_lg_q132w133w(0) <= wire_niii1O26_w_lg_q132w(0) AND nl00l; + wire_niii1O26_w_lg_q132w(0) <= niii1O26 XOR niii1O25; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niillO19 <= niillO20; + END IF; + if (now = 0 ns) then + niillO19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niillO20 <= niillO19; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niilOi17 <= niilOi18; + END IF; + if (now = 0 ns) then + niilOi17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niilOi18 <= niilOi17; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niilOO15 <= niilOO16; + END IF; + if (now = 0 ns) then + niilOO15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niilOO16 <= niilOO15; + END IF; + END PROCESS; + wire_niilOO16_w_lg_w_lg_q78w79w(0) <= wire_niilOO16_w_lg_q78w(0) AND niO0O; + wire_niilOO16_w_lg_q78w(0) <= niilOO16 XOR niilOO15; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO0i10 <= niiO0i9; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO0i9 <= niiO0i10; + END IF; + if (now = 0 ns) then + niiO0i9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO0O7 <= niiO0O8; + END IF; + if (now = 0 ns) then + niiO0O7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO0O8 <= niiO0O7; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO1i13 <= niiO1i14; + END IF; + if (now = 0 ns) then + niiO1i13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO1i14 <= niiO1i13; + END IF; + END PROCESS; + wire_niiO1i14_w_lg_w_lg_q53w54w(0) <= wire_niiO1i14_w_lg_q53w(0) AND niOil; + wire_niiO1i14_w_lg_q53w(0) <= niiO1i14 XOR niiO1i13; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO1l11 <= niiO1l12; + END IF; + if (now = 0 ns) then + niiO1l11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiO1l12 <= niiO1l11; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiOll5 <= niiOll6; + END IF; + if (now = 0 ns) then + niiOll5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiOll6 <= niiOll5; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiOOl3 <= niiOOl4; + END IF; + if (now = 0 ns) then + niiOOl3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niiOOl4 <= niiOOl3; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nil11i1 <= nil11i2; + END IF; + if (now = 0 ns) then + nil11i1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nil11i2 <= nil11i1; + END IF; + END PROCESS; + wire_nil11i2_w_lg_q4w(0) <= nil11i2 XOR nil11i1; + PROCESS (tx_clk, soft_reset) + BEGIN + IF (soft_reset = '1') THEN + n100i <= '0'; + n100l <= '0'; + n100O <= '0'; + n101i <= '0'; + n101l <= '0'; + n101O <= '0'; + n10ii <= '0'; + n10il <= '0'; + n10iO <= '0'; + n10li <= '0'; + n10ll <= '0'; + n10lO <= '0'; + n10Oi <= '0'; + n10Ol <= '0'; + n10OO <= '0'; + n110i <= '0'; + n110l <= '0'; + n110O <= '0'; + n111i <= '0'; + n111l <= '0'; + n111O <= '0'; + n11ii <= '0'; + n11il <= '0'; + n11iO <= '0'; + n11li <= '0'; + n11ll <= '0'; + n11lO <= '0'; + n11Oi <= '0'; + n11Ol <= '0'; + n11OO <= '0'; + n1i0i <= '0'; + n1i0l <= '0'; + n1i0O <= '0'; + n1i1i <= '0'; + n1i1l <= '0'; + n1i1O <= '0'; + n1iii <= '0'; + n1iil <= '0'; + n1iiO <= '0'; + n1ili <= '0'; + n1ill <= '0'; + n1ilO <= '0'; + n1iOi <= '0'; + n1iOl <= '0'; + n1iOO <= '0'; + n1l0i <= '0'; + n1l0l <= '0'; + n1l1i <= '0'; + n1l1l <= '0'; + n1l1O <= '0'; + n1lii <= '0'; + nliliO <= '0'; + nlOOil <= '0'; + nlOOiO <= '0'; + nlOOli <= '0'; + nlOOll <= '0'; + nlOOlO <= '0'; + nlOOOi <= '0'; + nlOOOl <= '0'; + nlOOOO <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (wire_nll_dataout = '1') THEN + n100i <= wire_nll01O_o; + n100l <= wire_nll00O_o; + n100O <= wire_nll0iO_o; + n101i <= wire_n001O_dataout; + n101l <= ni0OlO; + n101O <= wire_nliO1i_o; + n10ii <= wire_nll0lO_o; + n10il <= wire_nll0OO_o; + n10iO <= wire_w_lg_ni0OOi889w(0); + n10li <= wire_nlli0i_o; + n10ll <= wire_w_lg_ni0OOl888w(0); + n10lO <= wire_nlliil_o; + n10Oi <= wire_nllili_o; + n10Ol <= wire_nllilO_o; + n10OO <= wire_nlliOi_o; + n110i <= wire_n011i_dataout; + n110l <= wire_n011l_dataout; + n110O <= wire_n011O_dataout; + n111i <= wire_n1OlO_dataout; + n111l <= wire_n1OOi_dataout; + n111O <= wire_n1OOl_dataout; + n11ii <= wire_n010i_dataout; + n11il <= wire_n01li_dataout; + n11iO <= wire_n01ll_dataout; + n11li <= wire_n01lO_dataout; + n11ll <= wire_n01Oi_dataout; + n11lO <= wire_n01Ol_dataout; + n11Oi <= wire_n01OO_dataout; + n11Ol <= wire_n001i_dataout; + n11OO <= wire_n001l_dataout; + n1i0i <= wire_nlll0O_o; + n1i0l <= wire_nliO1O_o; + n1i0O <= wire_nliO0l_o; + n1i1i <= wire_nlliOO_o; + n1i1l <= wire_nlll1l_o; + n1i1O <= wire_nlll0i_o; + n1iii <= wire_nliOii_o; + n1iil <= wire_nliOli_o; + n1iiO <= wire_nliOll_dataout; + n1ili <= wire_nliOlO_o; + n1ill <= wire_nliOOi_o; + n1ilO <= wire_nliOOl_o; + n1iOi <= wire_nll11i_dataout; + n1iOl <= wire_nll11l_o; + n1iOO <= wire_nll10i_o; + n1l0i <= wire_nll1Oi_dataout; + n1l0l <= wire_nll1Ol_o; + n1l1i <= wire_nll10O_o; + n1l1l <= wire_nll1il_o; + n1l1O <= wire_nll1ll_o; + n1lii <= wire_nll01i_o; + nliliO <= wire_n1lli_dataout; + nlOOil <= wire_n1lll_dataout; + nlOOiO <= wire_n1llO_dataout; + nlOOli <= wire_n1lOl_dataout; + nlOOll <= wire_n1lOO_dataout; + nlOOlO <= wire_n1O1i_dataout; + nlOOOi <= wire_n1O1l_dataout; + nlOOOl <= wire_n1O1O_dataout; + nlOOOO <= wire_n1O0i_dataout; + END IF; + END IF; + END PROCESS; + wire_n1l0O_w_lg_w_lg_w_lg_w1501w1502w1503w1504w(0) <= wire_n1l0O_w_lg_w_lg_w1501w1502w1503w(0) AND n11iO; + wire_n1l0O_w_lg_w_lg_w1510w1511w1512w(0) <= wire_n1l0O_w_lg_w1510w1511w(0) AND n11iO; + wire_n1l0O_w_lg_w_lg_w1501w1502w1503w(0) <= wire_n1l0O_w_lg_w1501w1502w(0) AND wire_n1l0O_w_lg_n11li1490w(0); + wire_n1l0O_w_lg_w1510w1511w(0) <= wire_n1l0O_w1510w(0) AND n11li; + wire_n1l0O_w_lg_w1501w1502w(0) <= wire_n1l0O_w1501w(0) AND wire_n1l0O_w_lg_n11ll1488w(0); + wire_n1l0O_w1510w(0) <= wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n101i1506w1507w1508w1509w(0) AND wire_n1l0O_w_lg_n11ll1488w(0); + wire_n1l0O_w1501w(0) <= wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n101i1480w1497w1499w1500w(0) AND wire_n1l0O_w_lg_n11lO1486w(0); + wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n101i1506w1507w1508w1509w(0) <= wire_n1l0O_w_lg_w_lg_w_lg_n101i1506w1507w1508w(0) AND wire_n1l0O_w_lg_n11lO1486w(0); + wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n101i1480w1497w1499w1500w(0) <= wire_n1l0O_w_lg_w_lg_w_lg_n101i1480w1497w1499w(0) AND wire_n1l0O_w_lg_n11Oi1484w(0); + wire_n1l0O_w_lg_w_lg_w_lg_w_lg_n11ii897w899w900w901w(0) <= wire_n1l0O_w_lg_w_lg_w_lg_n11ii897w899w900w(0) AND n110i; + wire_n1l0O_w_lg_w_lg_w_lg_n101i1506w1507w1508w(0) <= wire_n1l0O_w_lg_w_lg_n101i1506w1507w(0) AND wire_n1l0O_w_lg_n11Oi1484w(0); + wire_n1l0O_w_lg_w_lg_w_lg_n11ii902w903w904w(0) <= wire_n1l0O_w_lg_w_lg_n11ii902w903w(0) AND n110i; + wire_n1l0O_w_lg_w_lg_w_lg_n101i1480w1482w1483w(0) <= wire_n1l0O_w_lg_w_lg_n101i1480w1482w(0) AND n11Ol; + wire_n1l0O_w_lg_w_lg_w_lg_n101i1480w1497w1499w(0) <= wire_n1l0O_w_lg_w_lg_n101i1480w1497w(0) AND wire_n1l0O_w_lg_n11Ol1498w(0); + wire_n1l0O_w_lg_w_lg_w_lg_n11ii897w899w900w(0) <= wire_n1l0O_w_lg_w_lg_n11ii897w899w(0) AND n110l; + wire_n1l0O_w_lg_w_lg_n101i1506w1507w(0) <= wire_n1l0O_w_lg_n101i1506w(0) AND wire_n1l0O_w_lg_n11Ol1498w(0); + wire_n1l0O_w_lg_w_lg_n11ii902w903w(0) <= wire_n1l0O_w_lg_n11ii902w(0) AND n110l; + wire_n1l0O_w_lg_w_lg_n101i1480w1482w(0) <= wire_n1l0O_w_lg_n101i1480w(0) AND wire_n1l0O_w_lg_n11OO1481w(0); + wire_n1l0O_w_lg_w_lg_n101i1480w1497w(0) <= wire_n1l0O_w_lg_n101i1480w(0) AND n11OO; + wire_n1l0O_w_lg_w_lg_n11ii897w899w(0) <= wire_n1l0O_w_lg_n11ii897w(0) AND wire_n1l0O_w_lg_n110O898w(0); + wire_n1l0O_w_lg_w_lg_nlOOiO1476w1543w(0) <= wire_n1l0O_w_lg_nlOOiO1476w(0) AND nlOOil; + wire_n1l0O_w_lg_w_lg_nlOOOO1529w1530w(0) <= wire_n1l0O_w_lg_nlOOOO1529w(0) AND nlOOOl; + wire_n1l0O_w_lg_n101i1506w(0) <= n101i AND wire_n1l0O_w_lg_n11OO1481w(0); + wire_n1l0O_w_lg_n11ii902w(0) <= n11ii AND wire_n1l0O_w_lg_n110O898w(0); + wire_n1l0O_w_lg_nlOOOO1538w(0) <= nlOOOO AND wire_n1l0O_w_lg_nlOOOl1537w(0); + wire_n1l0O_w_lg_n101i1480w(0) <= NOT n101i; + wire_n1l0O_w_lg_n110i1516w(0) <= NOT n110i; + wire_n1l0O_w_lg_n110O898w(0) <= NOT n110O; + wire_n1l0O_w_lg_n111O1524w(0) <= NOT n111O; + wire_n1l0O_w_lg_n11ii897w(0) <= NOT n11ii; + wire_n1l0O_w_lg_n11il1494w(0) <= NOT n11il; + wire_n1l0O_w_lg_n11iO1492w(0) <= NOT n11iO; + wire_n1l0O_w_lg_n11li1490w(0) <= NOT n11li; + wire_n1l0O_w_lg_n11ll1488w(0) <= NOT n11ll; + wire_n1l0O_w_lg_n11lO1486w(0) <= NOT n11lO; + wire_n1l0O_w_lg_n11Oi1484w(0) <= NOT n11Oi; + wire_n1l0O_w_lg_n11Ol1498w(0) <= NOT n11Ol; + wire_n1l0O_w_lg_n11OO1481w(0) <= NOT n11OO; + wire_n1l0O_w_lg_nliliO1544w(0) <= NOT nliliO; + wire_n1l0O_w_lg_nlOOil1477w(0) <= NOT nlOOil; + wire_n1l0O_w_lg_nlOOiO1476w(0) <= NOT nlOOiO; + wire_n1l0O_w_lg_nlOOlO1533w(0) <= NOT nlOOlO; + wire_n1l0O_w_lg_nlOOOi1531w(0) <= NOT nlOOOi; + wire_n1l0O_w_lg_nlOOOl1537w(0) <= NOT nlOOOl; + wire_n1l0O_w_lg_nlOOOO1529w(0) <= NOT nlOOOO; + wire_n1l0O_w_lg_w_lg_w_lg_n1ill1401w1402w1403w(0) <= wire_n1l0O_w_lg_w_lg_n1ill1401w1402w(0) OR n1iil; + wire_n1l0O_w_lg_w_lg_n1ill1401w1402w(0) <= wire_n1l0O_w_lg_n1ill1401w(0) OR n1iiO; + wire_n1l0O_w_lg_n1ill1401w(0) <= n1ill OR n1ili; + wire_n1l0O_w_lg_n1l0i1211w(0) <= n1l0i OR n1l1O; + PROCESS (tx_clk, soft_reset) + BEGIN + IF (soft_reset = '1') THEN + n1liO <= '1'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (wire_nll_dataout = '1') THEN + n1liO <= niilOl; + END IF; + END IF; + if (now = 0 ns) then + n1liO <= '1' after 1 ps; + end if; + END PROCESS; + wire_n1lil_w_lg_w_lg_w_lg_n1liO1051w1092w1093w(0) <= wire_n1lil_w_lg_w_lg_n1liO1051w1092w(0) OR n1iil; + wire_n1lil_w_lg_w_lg_n1liO1051w1092w(0) <= wire_n1lil_w_lg_n1liO1051w(0) OR n1iOO; + wire_n1lil_w_lg_n1liO1051w(0) <= n1liO OR n1l1O; + PROCESS (tx_clk, wire_nl0OOO_PRN, soft_reset) + BEGIN + IF (wire_nl0OOO_PRN = '0') THEN + nl00il <= '1'; + nl00iO <= '1'; + nl00li <= '1'; + nl00ll <= '1'; + nl00lO <= '1'; + nl00Oi <= '1'; + nl00Ol <= '1'; + nl00OO <= '1'; + nl0i0i <= '1'; + nl0i0l <= '1'; + nl0i0O <= '1'; + nl0i1i <= '1'; + nl0i1l <= '1'; + nl0i1O <= '1'; + nl0iii <= '1'; + nl0iil <= '1'; + nl0iiO <= '1'; + nl0ili <= '1'; + nl0ill <= '1'; + nl0ilO <= '1'; + nl0iOi <= '1'; + nl0iOl <= '1'; + nl0iOO <= '1'; + nl0l0i <= '1'; + nl0l0l <= '1'; + nl0l0O <= '1'; + nl0l1i <= '1'; + nl0l1l <= '1'; + nl0l1O <= '1'; + nl0lii <= '1'; + nl0lil <= '1'; + nl0liO <= '1'; + nl0lli <= '1'; + nl0lll <= '1'; + nl0llO <= '1'; + nl0lOi <= '1'; + nl0lOl <= '1'; + nl0lOO <= '1'; + nl0O0i <= '1'; + nl0O0l <= '1'; + nl0O0O <= '1'; + nl0O1i <= '1'; + nl0O1l <= '1'; + nl0O1O <= '1'; + nl0Oii <= '1'; + nl0Oil <= '1'; + nl0OiO <= '1'; + nl0Oli <= '1'; + nl0Oll <= '1'; + nl0OlO <= '1'; + nl0OOi <= '1'; + nl0OOl <= '1'; + nli11i <= '1'; + ELSIF (soft_reset = '1') THEN + nl00il <= '0'; + nl00iO <= '0'; + nl00li <= '0'; + nl00ll <= '0'; + nl00lO <= '0'; + nl00Oi <= '0'; + nl00Ol <= '0'; + nl00OO <= '0'; + nl0i0i <= '0'; + nl0i0l <= '0'; + nl0i0O <= '0'; + nl0i1i <= '0'; + nl0i1l <= '0'; + nl0i1O <= '0'; + nl0iii <= '0'; + nl0iil <= '0'; + nl0iiO <= '0'; + nl0ili <= '0'; + nl0ill <= '0'; + nl0ilO <= '0'; + nl0iOi <= '0'; + nl0iOl <= '0'; + nl0iOO <= '0'; + nl0l0i <= '0'; + nl0l0l <= '0'; + nl0l0O <= '0'; + nl0l1i <= '0'; + nl0l1l <= '0'; + nl0l1O <= '0'; + nl0lii <= '0'; + nl0lil <= '0'; + nl0liO <= '0'; + nl0lli <= '0'; + nl0lll <= '0'; + nl0llO <= '0'; + nl0lOi <= '0'; + nl0lOl <= '0'; + nl0lOO <= '0'; + nl0O0i <= '0'; + nl0O0l <= '0'; + nl0O0O <= '0'; + nl0O1i <= '0'; + nl0O1l <= '0'; + nl0O1O <= '0'; + nl0Oii <= '0'; + nl0Oil <= '0'; + nl0OiO <= '0'; + nl0Oli <= '0'; + nl0Oll <= '0'; + nl0OlO <= '0'; + nl0OOi <= '0'; + nl0OOl <= '0'; + nli11i <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + nl00il <= wire_nli10i_dataout; + nl00iO <= wire_nli10l_dataout; + nl00li <= wire_nli10O_dataout; + nl00ll <= wire_nli1ii_dataout; + nl00lO <= wire_nli1il_dataout; + nl00Oi <= wire_nli1iO_dataout; + nl00Ol <= wire_nli1li_dataout; + nl00OO <= wire_nli1ll_dataout; + nl0i0i <= wire_nli1OO_dataout; + nl0i0l <= wire_nli01i_dataout; + nl0i0O <= wire_nli01l_dataout; + nl0i1i <= wire_nli1lO_dataout; + nl0i1l <= wire_nli1Oi_dataout; + nl0i1O <= wire_nli1Ol_dataout; + nl0iii <= wire_nli01O_dataout; + nl0iil <= wire_nli00i_dataout; + nl0iiO <= wire_nli00l_dataout; + nl0ili <= wire_nli00O_dataout; + nl0ill <= wire_nli0ii_dataout; + nl0ilO <= wire_nli0il_dataout; + nl0iOi <= wire_nli0iO_dataout; + nl0iOl <= wire_nli0li_dataout; + nl0iOO <= (NOT (nli11O OR nl0OOi)); + nl0l0i <= wire_nil01O_o; + nl0l0l <= wire_nil00l_o; + nl0l0O <= wire_nil0il_o; + nl0l1i <= wire_nil1li_o; + nl0l1l <= wire_nil1lO_o; + nl0l1O <= wire_nil1OO_o; + nl0lii <= wire_nil0li_o; + nl0lil <= wire_nil0Oi_o; + nl0liO <= wire_nili1i_o; + nl0lli <= wire_nili0i_o; + nl0lll <= wire_nili0O_o; + nl0llO <= wire_niliil_o; + nl0lOi <= wire_nilili_o; + nl0lOl <= wire_nililO_o; + nl0lOO <= wire_niliOl_o; + nl0O0i <= wire_nillil_o; + nl0O0l <= wire_nillli_o; + nl0O0O <= wire_nilllO_o; + nl0O1i <= wire_nill1i_o; + nl0O1l <= wire_nill1O_o; + nl0O1O <= wire_nill0O_o; + nl0Oii <= wire_nillOl_o; + nl0Oil <= wire_nilO1i_o; + nl0OiO <= wire_nilO1O_o; + nl0Oli <= wire_nilO0l_o; + nl0Oll <= wire_nilOii_o; + nl0OlO <= wire_nilOiO_o; + nl0OOi <= wire_nilOli_o; + nl0OOl <= wire_nilOlO_o; + nli11i <= wire_nilOOl_o; + END IF; + END PROCESS; + wire_nl0OOO_PRN <= (ni001l46 XOR ni001l45); + wire_nl0OOO_w_lg_w_lg_w_lg_w_lg_nl0iOl2241w2243w2245w2253w(0) <= wire_nl0OOO_w_lg_w_lg_w_lg_nl0iOl2241w2243w2245w(0) AND nl0ill; + wire_nl0OOO_w_lg_w_lg_w_lg_nl0iOl2241w2243w2245w(0) <= wire_nl0OOO_w_lg_w_lg_nl0iOl2241w2243w(0) AND wire_nl0OOO_w_lg_nl0ilO2244w(0); + wire_nl0OOO_w_lg_w_lg_nl0iOl2241w2243w(0) <= wire_nl0OOO_w_lg_nl0iOl2241w(0) AND wire_nl0OOO_w_lg_nl0iOi2242w(0); + wire_nl0OOO_w_lg_nl0iii2259w(0) <= NOT nl0iii; + wire_nl0OOO_w_lg_nl0iil2257w(0) <= NOT nl0iil; + wire_nl0OOO_w_lg_nl0iiO2255w(0) <= NOT nl0iiO; + wire_nl0OOO_w_lg_nl0ili2248w(0) <= NOT nl0ili; + wire_nl0OOO_w_lg_nl0ill2246w(0) <= NOT nl0ill; + wire_nl0OOO_w_lg_nl0ilO2244w(0) <= NOT nl0ilO; + wire_nl0OOO_w_lg_nl0iOi2242w(0) <= NOT nl0iOi; + wire_nl0OOO_w_lg_nl0iOl2241w(0) <= NOT nl0iOl; + wire_nl0OOO_w_lg_nl0O0l2201w(0) <= nl0O0l OR nl0O0i; + wire_nl0OOO_w_lg_nl0O0l2215w(0) <= nl0O0l OR nl0O1O; + PROCESS (tx_clk, soft_reset) + BEGIN + IF (soft_reset = '1') THEN + nli11O <= '1'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + nli11O <= wire_niO11i_o; + END IF; + if (now = 0 ns) then + nli11O <= '1' after 1 ps; + end if; + END PROCESS; + wire_nli11l_w_lg_nli11O2169w(0) <= nli11O OR nl0O0l; + PROCESS (tx_clk, soft_reset) + BEGIN + IF (soft_reset = '1') THEN + n0lOi <= '0'; + niO0l <= '0'; + niO0O <= '0'; + niOii <= '0'; + niOil <= '0'; + niOiO <= '0'; + niOli <= '0'; + niOll <= '0'; + niOlO <= '0'; + niOOi <= '0'; + niOOl <= '0'; + niOOO <= '0'; + nl00i <= '0'; + nl00l <= '0'; + nl00O <= '0'; + nl01i <= '0'; + nl01l <= '0'; + nl01O <= '0'; + nl0ii <= '0'; + nl0il <= '0'; + nl0iO <= '0'; + nl0li <= '0'; + nl0ll <= '0'; + nl0lO <= '0'; + nl0Oi <= '0'; + nl0Ol <= '0'; + nl0OO <= '0'; + nl10i <= '0'; + nl10l <= '0'; + nl10O <= '0'; + nl11i <= '0'; + nl11l <= '0'; + nl11O <= '0'; + nl1ii <= '0'; + nl1il <= '0'; + nl1iO <= '0'; + nl1li <= '0'; + nl1ll <= '0'; + nl1lO <= '0'; + nl1Oi <= '0'; + nl1Ol <= '0'; + nl1OO <= '0'; + nli0i <= '0'; + nli0l <= '0'; + nli0O <= '0'; + nli1i <= '0'; + nli1l <= '0'; + nli1O <= '0'; + nliil <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (wire_nli_dataout = '1') THEN + n0lOi <= wire_nlill_dataout; + niO0l <= wire_nlilO_dataout; + niO0O <= wire_nliOi_dataout; + niOii <= wire_nliOO_dataout; + niOil <= wire_nll1i_dataout; + niOiO <= wire_nll1l_dataout; + niOli <= wire_nll1O_dataout; + niOll <= wire_nll0i_dataout; + niOlO <= niil1l; + niOOi <= wire_n0ilO_o; + niOOl <= wire_w_lg_niil1O100w(0); + niOOO <= niil0i; + nl00i <= wire_n0lii_o; + nl00l <= wire_n0lil_o; + nl00O <= wire_n0liO_o; + nl01i <= wire_n0l1i_o; + nl01l <= wire_n0l1O_o; + nl01O <= wire_n0l0O_dataout; + nl0ii <= wire_n0lli_o; + nl0il <= wire_n0llO_dataout; + nl0iO <= wire_n0lOl_o; + nl0li <= wire_n0O1i_dataout; + nl0ll <= wire_n0O1l_o; + nl0lO <= wire_n0O0i_dataout; + nl0Oi <= wire_n0O0l_o; + nl0Ol <= wire_n0Oii_dataout; + nl0OO <= wire_n0Oil_o; + nl10i <= wire_w_lg_niilil96w(0); + nl10l <= wire_w_lg_niiliO95w(0); + nl10O <= niilli; + nl11i <= wire_w_lg_niil0l99w(0); + nl11l <= wire_w_lg_niil0O98w(0); + nl11O <= wire_w_lg_niilii97w(0); + nl1ii <= wire_ni1Ol_o; + nl1il <= wire_ni01i_o; + nl1iO <= wire_ni01O_o; + nl1li <= wire_ni00l_o; + nl1ll <= wire_ni0ii_o; + nl1lO <= wire_ni0iO_o; + nl1Oi <= wire_ni0ll_o; + nl1Ol <= wire_ni0Oi_o; + nl1OO <= wire_n0iOl_o; + nli0i <= wire_n0OOl_o; + nli0l <= wire_ni11i_dataout; + nli0O <= wire_ni11l_o; + nli1i <= wire_n0Oli_dataout; + nli1l <= wire_n0Oll_o; + nli1O <= wire_n0OOi_dataout; + nliil <= wire_ni10i_o; + END IF; + END IF; + END PROCESS; + wire_nliii_w_lg_w_lg_w_lg_niOll766w767w768w(0) <= wire_nliii_w_lg_w_lg_niOll766w767w(0) AND niOil; + wire_nliii_w_lg_w_lg_niOll766w767w(0) <= wire_nliii_w_lg_niOll766w(0) AND niOiO; + wire_nliii_w_lg_w_lg_niO0O762w771w(0) <= wire_nliii_w_lg_niO0O762w(0) AND niO0l; + wire_nliii_w_lg_niOll766w(0) <= niOll AND niOli; + wire_nliii_w_lg_n0lOi772w(0) <= NOT n0lOi; + wire_nliii_w_lg_niO0l763w(0) <= NOT niO0l; + wire_nliii_w_lg_niO0O762w(0) <= NOT niO0O; + wire_nliii_w_lg_niOii769w(0) <= NOT niOii; + wire_nliii_w_lg_w_lg_w_lg_nl00O654w655w656w(0) <= wire_nliii_w_lg_w_lg_nl00O654w655w(0) OR nl01O; + wire_nliii_w_lg_w_lg_nl00O654w655w(0) <= wire_nliii_w_lg_nl00O654w(0) OR nl00i; + wire_nliii_w_lg_nl00O654w(0) <= nl00O OR nl00l; + PROCESS (tx_clk, wire_nliiO_PRN, wire_nliiO_CLRN) + BEGIN + IF (wire_nliiO_PRN = '0') THEN + nlili <= '1'; + ELSIF (wire_nliiO_CLRN = '0') THEN + nlili <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (wire_nli_dataout = '1') THEN + nlili <= niilOl; + END IF; + END IF; + if (now = 0 ns) then + nlili <= '1' after 1 ps; + end if; + END PROCESS; + wire_nliiO_CLRN <= (niilOi18 XOR niilOi17); + wire_nliiO_PRN <= ((niillO20 XOR niillO19) AND wire_w_lg_soft_reset93w(0)); + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w199w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w(0) OR nl1OO; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w194w195w196w197w198w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w194w195w196w197w(0) OR nl01i; + wire_nliiO_w_lg_w_lg_w_lg_w194w195w196w197w(0) <= wire_nliiO_w_lg_w_lg_w194w195w196w(0) OR nl01O; + wire_nliiO_w_lg_w_lg_w120w121w122w(0) <= wire_nliiO_w_lg_w120w121w(0) OR nl1OO; + wire_nliiO_w_lg_w_lg_w194w195w196w(0) <= wire_nliiO_w_lg_w194w195w(0) OR nl0il; + wire_nliiO_w_lg_w120w121w(0) <= wire_nliiO_w120w(0) OR nl01i; + wire_nliiO_w_lg_w194w195w(0) <= wire_nliiO_w194w(0) OR nl0iO; + wire_nliiO_w262w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w256w257w258w259w260w261w(0) OR nl1OO; + wire_nliiO_w223w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w217w218w219w220w221w222w(0) OR nl1OO; + wire_nliiO_w120w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w114w115w116w117w118w119w(0) OR nl01O; + wire_nliiO_w194w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) OR nl0li; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w256w257w258w259w260w261w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w256w257w258w259w260w(0) OR nl01i; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w217w218w219w220w221w222w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w217w218w219w220w221w(0) OR nl01i; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w114w115w116w117w118w119w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w114w115w116w117w118w(0) OR nl0il; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w193w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w(0) OR nl0lO; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w256w257w258w259w260w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w256w257w258w259w(0) OR nl01O; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w217w218w219w220w221w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w217w218w219w220w(0) OR nl01O; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w114w115w116w117w118w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w114w115w116w117w(0) OR nl0iO; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w188w189w190w191w192w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w188w189w190w191w(0) OR nl0Oi; + wire_nliiO_w_lg_w_lg_w_lg_w256w257w258w259w(0) <= wire_nliiO_w_lg_w_lg_w256w257w258w(0) OR nl0il; + wire_nliiO_w_lg_w_lg_w_lg_w217w218w219w220w(0) <= wire_nliiO_w_lg_w_lg_w217w218w219w(0) OR nl0il; + wire_nliiO_w_lg_w_lg_w_lg_w114w115w116w117w(0) <= wire_nliiO_w_lg_w_lg_w114w115w116w(0) OR nl0li; + wire_nliiO_w_lg_w_lg_w_lg_w188w189w190w191w(0) <= wire_nliiO_w_lg_w_lg_w188w189w190w(0) OR nl0Ol; + wire_nliiO_w_lg_w_lg_w256w257w258w(0) <= wire_nliiO_w_lg_w256w257w(0) OR nl0iO; + wire_nliiO_w_lg_w_lg_w217w218w219w(0) <= wire_nliiO_w_lg_w217w218w(0) OR nl0li; + wire_nliiO_w_lg_w_lg_w114w115w116w(0) <= wire_nliiO_w_lg_w114w115w(0) OR nl0lO; + wire_nliiO_w_lg_w_lg_w188w189w190w(0) <= wire_nliiO_w_lg_w188w189w(0) OR nl0OO; + wire_nliiO_w_lg_w256w257w(0) <= wire_nliiO_w256w(0) OR nl0li; + wire_nliiO_w_lg_w217w218w(0) <= wire_nliiO_w217w(0) OR nl0lO; + wire_nliiO_w_lg_w114w115w(0) <= wire_nliiO_w114w(0) OR nl0Oi; + wire_nliiO_w_lg_w188w189w(0) <= wire_nliiO_w188w(0) OR nli1i; + wire_nliiO_w256w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili160w161w162w254w255w(0) OR nl0ll; + wire_nliiO_w217w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili160w161w214w215w216w(0) OR nl0Ol; + wire_nliiO_w114w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili109w110w111w112w113w(0) OR nl0Ol; + wire_nliiO_w188w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili109w184w185w186w187w(0) OR nli1l; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili160w161w162w254w255w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili160w161w162w254w(0) OR nl0lO; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili160w161w214w215w216w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili160w161w214w215w(0) OR nl0OO; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili109w110w111w112w113w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili109w110w111w112w(0) OR nli1i; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_w_lg_nlili109w184w185w186w187w(0) <= wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili109w184w185w186w(0) OR nli1O; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili160w161w162w254w(0) <= wire_nliiO_w_lg_w_lg_w_lg_nlili160w161w162w(0) OR nl0Ol; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili160w161w214w215w(0) <= wire_nliiO_w_lg_w_lg_w_lg_nlili160w161w214w(0) OR nli1i; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili109w110w111w112w(0) <= wire_nliiO_w_lg_w_lg_w_lg_nlili109w110w111w(0) OR nli1l; + wire_nliiO_w_lg_w_lg_w_lg_w_lg_nlili109w184w185w186w(0) <= wire_nliiO_w_lg_w_lg_w_lg_nlili109w184w185w(0) OR nli0i; + wire_nliiO_w_lg_w_lg_w_lg_nlili160w161w162w(0) <= wire_nliiO_w_lg_w_lg_nlili160w161w(0) OR nli1i; + wire_nliiO_w_lg_w_lg_w_lg_nlili160w161w214w(0) <= wire_nliiO_w_lg_w_lg_nlili160w161w(0) OR nli1l; + wire_nliiO_w_lg_w_lg_w_lg_nlili109w110w111w(0) <= wire_nliiO_w_lg_w_lg_nlili109w110w(0) OR nli1O; + wire_nliiO_w_lg_w_lg_w_lg_nlili109w184w185w(0) <= wire_nliiO_w_lg_w_lg_nlili109w184w(0) OR nli0l; + wire_nliiO_w_lg_w_lg_nlili160w161w(0) <= wire_nliiO_w_lg_nlili160w(0) OR nli1O; + wire_nliiO_w_lg_w_lg_nlili109w110w(0) <= wire_nliiO_w_lg_nlili109w(0) OR nli0l; + wire_nliiO_w_lg_w_lg_nlili109w184w(0) <= wire_nliiO_w_lg_nlili109w(0) OR nli0O; + wire_nliiO_w_lg_nlili160w(0) <= nlili OR nli0l; + wire_nliiO_w_lg_nlili109w(0) <= nlili OR nliil; + wire_n000i_dataout <= wire_n00Oi_o(0) WHEN n1l1l = '1' ELSE n11il; + wire_n000l_dataout <= wire_n00Oi_o(1) WHEN n1l1l = '1' ELSE n11iO; + wire_n000O_dataout <= wire_n00Oi_o(2) WHEN n1l1l = '1' ELSE n11li; + wire_n001i_dataout <= wire_n00li_dataout AND NOT(wire_nlillO_dataout); + wire_n001l_dataout <= wire_n00ll_dataout AND NOT(wire_nlillO_dataout); + wire_n001O_dataout <= wire_n00lO_dataout AND NOT(wire_nlillO_dataout); + wire_n00i_dataout <= nl0l0l WHEN niiOil = '1' ELSE wire_niii_dataout; + wire_n00ii_dataout <= wire_n00Oi_o(3) WHEN n1l1l = '1' ELSE n11ll; + wire_n00il_dataout <= wire_n00Oi_o(4) WHEN n1l1l = '1' ELSE n11lO; + wire_n00iO_dataout <= wire_n00Oi_o(5) WHEN n1l1l = '1' ELSE n11Oi; + wire_n00l_dataout <= nl0l0O WHEN niiOil = '1' ELSE wire_niil_dataout; + wire_n00li_dataout <= wire_n00Oi_o(6) WHEN n1l1l = '1' ELSE n11Ol; + wire_n00ll_dataout <= wire_n00Oi_o(7) WHEN n1l1l = '1' ELSE n11OO; + wire_n00lO_dataout <= wire_n00Oi_o(8) WHEN n1l1l = '1' ELSE n101i; + wire_n00O_dataout <= nl0lii WHEN niiOil = '1' ELSE wire_niiO_dataout; + wire_n010i_dataout <= wire_n01il_dataout AND NOT(wire_nlilll_dataout); + wire_n010l_dataout <= wire_n01iO_o(0) WHEN wire_nlilli_dataout = '1' ELSE n110i; + wire_n010O_dataout <= wire_n01iO_o(1) WHEN wire_nlilli_dataout = '1' ELSE n110l; + wire_n011i_dataout <= wire_n010l_dataout AND NOT(wire_nlilll_dataout); + wire_n011l_dataout <= wire_n010O_dataout AND NOT(wire_nlilll_dataout); + wire_n011O_dataout <= wire_n01ii_dataout AND NOT(wire_nlilll_dataout); + wire_n01i_dataout <= nl0l1l WHEN niiOil = '1' ELSE wire_ni0i_dataout; + wire_n01ii_dataout <= wire_n01iO_o(2) WHEN wire_nlilli_dataout = '1' ELSE n110O; + wire_n01il_dataout <= wire_n01iO_o(3) WHEN wire_nlilli_dataout = '1' ELSE n11ii; + wire_n01l_dataout <= nl0l1O WHEN niiOil = '1' ELSE wire_ni0l_dataout; + wire_n01li_dataout <= wire_n000i_dataout AND NOT(wire_nlillO_dataout); + wire_n01ll_dataout <= wire_n000l_dataout AND NOT(wire_nlillO_dataout); + wire_n01lO_dataout <= wire_n000O_dataout AND NOT(wire_nlillO_dataout); + wire_n01O_dataout <= nl0l0i WHEN niiOil = '1' ELSE wire_ni0O_dataout; + wire_n01Oi_dataout <= wire_n00ii_dataout AND NOT(wire_nlillO_dataout); + wire_n01Ol_dataout <= wire_n00il_dataout AND NOT(wire_nlillO_dataout); + wire_n01OO_dataout <= wire_n00iO_dataout AND NOT(wire_nlillO_dataout); + wire_n0i_dataout <= nl1ll AND niiOli; + wire_n0ii_dataout <= nl0lil WHEN niiOil = '1' ELSE wire_nili_dataout; + wire_n0il_dataout <= nl0liO WHEN niiOil = '1' ELSE wire_nill_dataout; + wire_n0iO_dataout <= nl0lli WHEN niiOil = '1' ELSE wire_nilO_dataout; + wire_n0l_dataout <= nl1lO AND niiOli; + wire_n0l0O_dataout <= wire_w_lg_niiOOi445w(0) AND nl0ii; + wire_n0li_dataout <= nl0lll WHEN niiOil = '1' ELSE wire_niOi_dataout; + wire_n0ll_dataout <= nl0llO WHEN niiOil = '1' ELSE wire_niOl_dataout; + wire_n0llO_dataout <= wire_w_lg_niiOOi445w(0) AND nl0iO; + wire_n0lO_dataout <= nl0lOi WHEN niiOil = '1' ELSE wire_niOO_dataout; + wire_n0O_dataout <= nl1Oi AND niiOli; + wire_n0O0i_dataout <= wire_w_lg_niiOOi445w(0) AND nl0Oi; + wire_n0O1i_dataout <= wire_w_lg_niiOOi445w(0) AND nl0ll; + wire_n0Oi_dataout <= nl0lOl WHEN niiOil = '1' ELSE wire_nl1i_dataout; + wire_n0Oii_dataout <= wire_w_lg_niiOOi445w(0) AND nl0OO; + wire_n0Ol_dataout <= nl0lOO WHEN niiOil = '1' ELSE wire_nl1l_dataout; + wire_n0Oli_dataout <= wire_w_lg_niiOOi445w(0) AND nli1l; + wire_n0OO_dataout <= nl0O1i WHEN niiOil = '1' ELSE wire_nl1O_dataout; + wire_n0OOi_dataout <= wire_w_lg_niiOOi445w(0) AND nli0i; + wire_n1i_dataout <= nl1il AND niiOli; + wire_n1l_dataout <= nl1iO AND niiOli; + wire_n1lli_dataout <= wire_n1lOi_o(0) AND wire_nlilOi_o; + wire_n1lll_dataout <= wire_n1lOi_o(1) AND wire_nlilOi_o; + wire_n1llO_dataout <= wire_n1lOi_o(2) AND wire_nlilOi_o; + wire_n1lOl_dataout <= wire_n1Oll_o(0) WHEN wire_nlil0O_dataout = '1' ELSE wire_n1O0l_dataout; + wire_n1lOO_dataout <= wire_n1Oll_o(1) WHEN wire_nlil0O_dataout = '1' ELSE wire_n1O0O_dataout; + wire_n1O_dataout <= nl1li AND niiOli; + wire_n1O0i_dataout <= wire_n1Oll_o(5) WHEN wire_nlil0O_dataout = '1' ELSE wire_n1Oli_dataout; + wire_n1O0l_dataout <= nlOOli AND NOT(wire_nlilii_dataout); + wire_n1O0O_dataout <= nlOOll AND NOT(wire_nlilii_dataout); + wire_n1O1i_dataout <= wire_n1Oll_o(2) WHEN wire_nlil0O_dataout = '1' ELSE wire_n1Oii_dataout; + wire_n1O1l_dataout <= wire_n1Oll_o(3) WHEN wire_nlil0O_dataout = '1' ELSE wire_n1Oil_dataout; + wire_n1O1O_dataout <= wire_n1Oll_o(4) WHEN wire_nlil0O_dataout = '1' ELSE wire_n1OiO_dataout; + wire_n1Oii_dataout <= nlOOlO AND NOT(wire_nlilii_dataout); + wire_n1Oil_dataout <= nlOOOi AND NOT(wire_nlilii_dataout); + wire_n1OiO_dataout <= nlOOOl AND NOT(wire_nlilii_dataout); + wire_n1Oli_dataout <= nlOOOO AND NOT(wire_nlilii_dataout); + wire_n1OlO_dataout <= wire_n1OOO_o(0) WHEN wire_nlilil_dataout = '1' ELSE n111i; + wire_n1OOi_dataout <= wire_n1OOO_o(1) WHEN wire_nlilil_dataout = '1' ELSE n111l; + wire_n1OOl_dataout <= wire_n1OOO_o(2) WHEN wire_nlilil_dataout = '1' ELSE n111O; + wire_ni0i_dataout <= n100i WHEN niiOiO = '1' ELSE wire_nlii_dataout; + wire_ni0l_dataout <= n100l WHEN niiOiO = '1' ELSE wire_nlil_dataout; + wire_ni0O_dataout <= n100O WHEN niiOiO = '1' ELSE wire_nliO_dataout; + wire_ni0OO_dataout <= niiiil AND NOT(niiilO); + wire_ni11i_dataout <= wire_nillO_dataout AND nli0O; + wire_ni1i_dataout <= nl0O1l WHEN niiOil = '1' ELSE wire_nl0i_dataout; + wire_ni1l_dataout <= nl0iOO WHEN niiOil = '1' ELSE wire_nl0l_dataout; + wire_ni1O_dataout <= nl0l1i WHEN niiOil = '1' ELSE wire_nl0O_dataout; + wire_nii_dataout <= nl1Ol AND niiOli; + wire_nii0i_dataout <= wire_niiil_dataout AND niiOOi; + wire_nii0l_dataout <= wire_niiiO_dataout AND niiOOi; + wire_nii0O_dataout <= niiiil WHEN niiilO = '1' ELSE niiiiO; + wire_nii1i_dataout <= niiiil AND niiilO; + wire_nii1l_dataout <= wire_nii0O_dataout AND NOT(niiOOi); + wire_nii1O_dataout <= wire_w_lg_niiili108w(0) WHEN niiOOi = '1' ELSE wire_niiii_dataout; + wire_niii_dataout <= n10ii WHEN niiOiO = '1' ELSE wire_nlli_dataout; + wire_niiii_dataout <= wire_w_lg_niiiil107w(0) WHEN niiilO = '1' ELSE wire_w_lg_niiiiO106w(0); + wire_niiil_dataout <= niiili AND NOT(niiilO); + wire_niiiO_dataout <= niiili AND niiilO; + wire_niil_dataout <= n10il WHEN niiOiO = '1' ELSE wire_nlll_dataout; + wire_niili_dataout <= wire_nil1i_dataout AND niiOOi; + wire_niill_dataout <= wire_nil1l_dataout AND niiOOi; + wire_niilO_dataout <= wire_nil1O_dataout AND niiOOi; + wire_niiO_dataout <= n10iO WHEN niiOiO = '1' ELSE wire_nllO_dataout; + wire_niiOi_dataout <= wire_nil0i_dataout AND niiOOi; + wire_niiOl_dataout <= wire_w_lg_niiill105w(0) AND niiOOi; + wire_niiOO_dataout <= niiill AND niiOOi; + wire_nil_dataout <= niOlO AND niiOli; + wire_nil0i_dataout <= niiilO AND niiill; + wire_nil0l_dataout <= wire_nilil_dataout AND NOT(niiilO); + wire_nil0O_dataout <= wire_niliO_dataout AND NOT(niiilO); + wire_nil1i_dataout <= wire_nil0l_dataout AND niiill; + wire_nil1l_dataout <= wire_nil0O_dataout AND niiill; + wire_nil1O_dataout <= wire_nilii_dataout AND niiill; + wire_nili_dataout <= n10li WHEN niiOiO = '1' ELSE wire_nlOi_dataout; + wire_nilii_dataout <= niil1i AND NOT(niiilO); + wire_nilil_dataout <= wire_w_lg_niiiOO104w(0) AND NOT(niil1i); + wire_niliO_dataout <= niiiOO AND NOT(niil1i); + wire_nill_dataout <= n10ll WHEN niiOiO = '1' ELSE wire_nlOl_dataout; + wire_nilli_dataout <= wire_w_lg_niiiOl103w(0) AND niiOOi; + wire_nilll_dataout <= wire_nilOl_dataout OR niiOOi; + wire_nillO_dataout <= wire_nilOO_dataout AND NOT(niiOOi); + wire_nilO_dataout <= n10lO WHEN niiOiO = '1' ELSE wire_nlOO_dataout; + wire_nilOi_dataout <= wire_niO1i_dataout AND NOT(niiOOi); + wire_nilOl_dataout <= wire_niO1l_dataout OR niiilO; + wire_nilOO_dataout <= wire_w_lg_niiiOl103w(0) AND NOT(niiilO); + wire_niO_dataout <= niOOi AND niiOli; + wire_niO00i_dataout <= nl00OO WHEN niiOOi = '1' ELSE nl0iil; + wire_niO00l_dataout <= nl0i1i WHEN niiOOi = '1' ELSE nl0iiO; + wire_niO00O_dataout <= nl0i1l WHEN niiOOi = '1' ELSE nl0ili; + wire_niO01i_dataout <= wire_niOOOi_dataout WHEN niiOOi = '1' ELSE wire_niOiOO_dataout; + wire_niO01l_dataout <= wire_niOOOl_dataout WHEN niiOOi = '1' ELSE wire_niOl1i_dataout; + wire_niO01O_dataout <= nl0iii AND NOT(niiOOi); + wire_niO0ii_dataout <= nl0i1O WHEN niiOOi = '1' ELSE nl0ill; + wire_niO0il_dataout <= nl0i0i WHEN niiOOi = '1' ELSE nl0ilO; + wire_niO0iO_dataout <= nl0i0l WHEN niiOOi = '1' ELSE nl0iOi; + wire_niO0li_dataout <= nl0i0O WHEN niiOOi = '1' ELSE nl0iOl; + wire_niO0ll_dataout <= nl00il AND niiOOi; + wire_niO0lO_dataout <= nl00iO AND niiOOi; + wire_niO0Oi_dataout <= nl00li AND niiOOi; + wire_niO0Ol_dataout <= nl00ll AND niiOOi; + wire_niO0OO_dataout <= nl00lO AND niiOOi; + wire_niO10i_dataout <= wire_niOO1i_dataout WHEN niiOOi = '1' ELSE wire_niOi1O_dataout; + wire_niO10l_dataout <= wire_niOO1l_dataout WHEN niiOOi = '1' ELSE wire_niOi0i_dataout; + wire_niO10O_dataout <= wire_niOO1O_dataout WHEN niiOOi = '1' ELSE wire_niOi0l_dataout; + wire_niO11l_dataout <= wire_nlO_dataout AND niiOOi; + wire_niO11O_dataout <= wire_nlO_dataout AND NOT(niiOOi); + wire_niO1i_dataout <= wire_niO1O_dataout AND NOT(niiilO); + wire_niO1ii_dataout <= wire_niOO0i_dataout WHEN niiOOi = '1' ELSE wire_niOi0O_dataout; + wire_niO1il_dataout <= wire_niOO0l_dataout WHEN niiOOi = '1' ELSE wire_niOiii_dataout; + wire_niO1iO_dataout <= wire_niOO0O_dataout WHEN niiOOi = '1' ELSE wire_niOiil_dataout; + wire_niO1l_dataout <= niiiOi AND niiiOl; + wire_niO1li_dataout <= wire_niOOii_dataout WHEN niiOOi = '1' ELSE wire_niOiiO_dataout; + wire_niO1ll_dataout <= wire_niOOil_dataout WHEN niiOOi = '1' ELSE wire_niOili_dataout; + wire_niO1lO_dataout <= wire_niOOiO_dataout WHEN niiOOi = '1' ELSE wire_niOill_dataout; + wire_niO1O_dataout <= wire_w_lg_niiiOi102w(0) AND niiiOl; + wire_niO1Oi_dataout <= wire_niOOli_dataout WHEN niiOOi = '1' ELSE wire_niOilO_dataout; + wire_niO1Ol_dataout <= wire_niOOll_dataout WHEN niiOOi = '1' ELSE wire_niOiOi_dataout; + wire_niO1OO_dataout <= wire_niOOlO_dataout WHEN niiOOi = '1' ELSE wire_niOiOl_dataout; + wire_niOi_dataout <= n10Oi WHEN niiOiO = '1' ELSE wire_n1i_dataout; + wire_niOi0i_dataout <= wire_niOl1O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOi0l_dataout <= wire_niOl0i_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOi0O_dataout <= wire_niOl0l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOi1i_dataout <= nl00Oi AND niiOOi; + wire_niOi1l_dataout <= nl00Ol AND niiOOi; + wire_niOi1O_dataout <= wire_niOl1l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOiii_dataout <= wire_niOl0O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOiil_dataout <= wire_niOlii_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOiiO_dataout <= wire_niOlil_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOili_dataout <= wire_niOliO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOill_dataout <= wire_niOlli_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOilO_dataout <= wire_niOlll_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOiOi_dataout <= wire_niOllO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOiOl_dataout <= wire_niOlOi_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOiOO_dataout <= wire_niOlOl_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOl_dataout <= n10Ol WHEN niiOiO = '1' ELSE wire_n1l_dataout; + wire_niOl0i_dataout <= nl0O0l AND NOT(ni01Oi); + wire_niOl0l_dataout <= nl0O0O AND NOT(ni01Oi); + wire_niOl0O_dataout <= nl0Oii AND NOT(ni01Oi); + wire_niOl1i_dataout <= wire_niOlOO_dataout OR wire_nlO_w_lg_dataout1647w(0); + wire_niOl1l_dataout <= nl0O1O AND NOT(ni01Oi); + wire_niOl1O_dataout <= nl0O0i AND NOT(ni01Oi); + wire_niOlii_dataout <= nl0Oil AND NOT(ni01Oi); + wire_niOlil_dataout <= nl0OiO AND NOT(ni01Oi); + wire_niOliO_dataout <= nl0Oli AND NOT(ni01Oi); + wire_niOlli_dataout <= nl0Oll AND NOT(ni01Oi); + wire_niOlll_dataout <= nl0OlO OR ni01Oi; + wire_niOllO_dataout <= nl0OOi AND NOT(ni01Oi); + wire_niOlOi_dataout <= nl0OOl AND NOT(ni01Oi); + wire_niOlOl_dataout <= nli11i AND NOT(ni01Oi); + wire_niOlOO_dataout <= nli11O AND NOT(ni01Oi); + wire_niOO_dataout <= n10OO WHEN niiOiO = '1' ELSE wire_n1O_dataout; + wire_niOO0i_dataout <= wire_nl111O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOO0l_dataout <= wire_nl110i_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOO0O_dataout <= wire_nl110l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOO1i_dataout <= wire_niOOOO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOO1l_dataout <= wire_nl111i_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOO1O_dataout <= wire_nl111l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOii_dataout <= wire_nl110O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOil_dataout <= wire_nl11ii_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOiO_dataout <= wire_nl11il_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOli_dataout <= wire_nl11iO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOll_dataout <= wire_nl11li_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOlO_dataout <= wire_nl11ll_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOOi_dataout <= wire_nl11lO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_niOOOl_dataout <= wire_nl11Oi_dataout OR wire_nlO_w_lg_dataout1647w(0); + wire_niOOOO_dataout <= nl0O1O AND NOT(ni01Ol); + wire_nl000i_dataout <= nl0OOi AND NOT(wire_nlO_dataout); + wire_nl000l_dataout <= nl0OOl AND NOT(wire_nlO_dataout); + wire_nl000O_dataout <= nli11i OR wire_nlO_dataout; + wire_nl001i_dataout <= nl0Oli AND NOT(wire_nlO_dataout); + wire_nl001l_dataout <= nl0Oll AND NOT(wire_nlO_dataout); + wire_nl001O_dataout <= nl0OlO AND NOT(wire_nlO_dataout); + wire_nl00ii_dataout <= nli11O AND NOT(wire_nlO_dataout); + wire_nl010i_dataout <= nl0OlO AND NOT(ni001i); + wire_nl010l_dataout <= nl0OOi AND NOT(ni001i); + wire_nl010O_dataout <= nl0OOl OR ni001i; + wire_nl011i_dataout <= nl0OiO AND NOT(ni001i); + wire_nl011l_dataout <= nl0Oli AND NOT(ni001i); + wire_nl011O_dataout <= nl0Oll AND NOT(ni001i); + wire_nl01ii_dataout <= nli11i AND NOT(ni001i); + wire_nl01il_dataout <= nli11O AND NOT(ni001i); + wire_nl01iO_dataout <= nl0O1O AND NOT(wire_nlO_dataout); + wire_nl01li_dataout <= nl0O0i AND NOT(wire_nlO_dataout); + wire_nl01ll_dataout <= nl0O0l AND NOT(wire_nlO_dataout); + wire_nl01lO_dataout <= nl0O0O AND NOT(wire_nlO_dataout); + wire_nl01Oi_dataout <= nl0Oii AND NOT(wire_nlO_dataout); + wire_nl01Ol_dataout <= nl0Oil AND NOT(wire_nlO_dataout); + wire_nl01OO_dataout <= nl0OiO AND NOT(wire_nlO_dataout); + wire_nl0i_dataout <= n1i0i WHEN niiOiO = '1' ELSE wire_nii_dataout; + wire_nl0l_dataout <= n101l WHEN niiOiO = '1' ELSE wire_nil_dataout; + wire_nl0O_dataout <= n101O WHEN niiOiO = '1' ELSE wire_niO_dataout; + wire_nl100i_dataout <= wire_nl1O1i_dataout WHEN niiOOi = '1' ELSE wire_nl1i1O_dataout; + wire_nl100l_dataout <= wire_nl1O1l_dataout WHEN niiOOi = '1' ELSE wire_nl1i0i_dataout; + wire_nl100O_dataout <= wire_nl1O1O_dataout WHEN niiOOi = '1' ELSE wire_nl1i0l_dataout; + wire_nl101i_dataout <= wire_nl1lOi_dataout WHEN niiOOi = '1' ELSE wire_nl10OO_dataout; + wire_nl101l_dataout <= wire_nl1lOl_dataout WHEN niiOOi = '1' ELSE wire_nl1i1i_dataout; + wire_nl101O_dataout <= wire_nl1lOO_dataout WHEN niiOOi = '1' ELSE wire_nl1i1l_dataout; + wire_nl10ii_dataout <= wire_nl1O0i_dataout WHEN niiOOi = '1' ELSE wire_nl1i0O_dataout; + wire_nl10il_dataout <= wire_nl1O0l_dataout WHEN niiOOi = '1' ELSE wire_nl1iii_dataout; + wire_nl10iO_dataout <= wire_nl1O0O_dataout WHEN niiOOi = '1' ELSE wire_nl1iil_dataout; + wire_nl10li_dataout <= wire_nl1Oii_dataout WHEN niiOOi = '1' ELSE wire_nl1iiO_dataout; + wire_nl10ll_dataout <= wire_nl1Oil_dataout WHEN niiOOi = '1' ELSE wire_nl1ili_dataout; + wire_nl10lO_dataout <= wire_nl1OiO_dataout WHEN niiOOi = '1' ELSE wire_nl1ill_dataout; + wire_nl10Oi_dataout <= wire_nl1ilO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl10Ol_dataout <= wire_nl1iOi_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl10OO_dataout <= wire_nl1iOl_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl110i_dataout <= nl0Oii AND NOT(ni01Ol); + wire_nl110l_dataout <= nl0Oil AND NOT(ni01Ol); + wire_nl110O_dataout <= nl0OiO AND NOT(ni01Ol); + wire_nl111i_dataout <= nl0O0i AND NOT(ni01Ol); + wire_nl111l_dataout <= nl0O0l AND NOT(ni01Ol); + wire_nl111O_dataout <= nl0O0O AND NOT(ni01Ol); + wire_nl11ii_dataout <= nl0Oli AND NOT(ni01Ol); + wire_nl11il_dataout <= nl0Oll AND NOT(ni01Ol); + wire_nl11iO_dataout <= nl0OlO OR ni01Ol; + wire_nl11li_dataout <= nl0OOi AND NOT(ni01Ol); + wire_nl11ll_dataout <= nl0OOl AND NOT(ni01Ol); + wire_nl11lO_dataout <= nli11i AND NOT(ni01Ol); + wire_nl11Oi_dataout <= nli11O AND NOT(ni01Ol); + wire_nl11Ol_dataout <= wire_nl1lll_dataout WHEN niiOOi = '1' ELSE wire_nl10Oi_dataout; + wire_nl11OO_dataout <= wire_nl1llO_dataout WHEN niiOOi = '1' ELSE wire_nl10Ol_dataout; + wire_nl1i_dataout <= n1i1i WHEN niiOiO = '1' ELSE wire_n0i_dataout; + wire_nl1i0i_dataout <= wire_nl1l1O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1i0l_dataout <= wire_nl1l0i_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1i0O_dataout <= wire_nl1l0l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1i1i_dataout <= wire_nl1iOO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1i1l_dataout <= wire_nl1l1i_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1i1O_dataout <= wire_nl1l1l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1iii_dataout <= wire_nl1l0O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1iil_dataout <= wire_nl1lii_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1iiO_dataout <= wire_nl1lil_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1ili_dataout <= wire_nl1liO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1ill_dataout <= wire_nl1lli_dataout OR wire_nlO_w_lg_dataout1647w(0); + wire_nl1ilO_dataout <= nl0O1O AND NOT(ni01OO); + wire_nl1iOi_dataout <= nl0O0i AND NOT(ni01OO); + wire_nl1iOl_dataout <= nl0O0l AND NOT(ni01OO); + wire_nl1iOO_dataout <= nl0O0O AND NOT(ni01OO); + wire_nl1l_dataout <= n1i1l WHEN niiOiO = '1' ELSE wire_n0l_dataout; + wire_nl1l0i_dataout <= nl0Oli AND NOT(ni01OO); + wire_nl1l0l_dataout <= nl0Oll AND NOT(ni01OO); + wire_nl1l0O_dataout <= nl0OlO AND NOT(ni01OO); + wire_nl1l1i_dataout <= nl0Oii AND NOT(ni01OO); + wire_nl1l1l_dataout <= nl0Oil AND NOT(ni01OO); + wire_nl1l1O_dataout <= nl0OiO AND NOT(ni01OO); + wire_nl1lii_dataout <= nl0OOi AND NOT(ni01OO); + wire_nl1lil_dataout <= nl0OOl OR ni01OO; + wire_nl1liO_dataout <= nli11i AND NOT(ni01OO); + wire_nl1lli_dataout <= nli11O AND NOT(ni01OO); + wire_nl1lll_dataout <= wire_nl1Oli_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1llO_dataout <= wire_nl1Oll_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1lOi_dataout <= wire_nl1OlO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1lOl_dataout <= wire_nl1OOi_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1lOO_dataout <= wire_nl1OOl_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1O_dataout <= n1i1O WHEN niiOiO = '1' ELSE wire_n0O_dataout; + wire_nl1O0i_dataout <= wire_nl011O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1O0l_dataout <= wire_nl010i_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1O0O_dataout <= wire_nl010l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1O1i_dataout <= wire_nl1OOO_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1O1l_dataout <= wire_nl011i_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1O1O_dataout <= wire_nl011l_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1Oii_dataout <= wire_nl010O_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1Oil_dataout <= wire_nl01ii_dataout AND NOT(wire_nlO_w_lg_dataout1647w(0)); + wire_nl1OiO_dataout <= wire_nl01il_dataout OR wire_nlO_w_lg_dataout1647w(0); + wire_nl1Oli_dataout <= nl0O1O AND NOT(ni001i); + wire_nl1Oll_dataout <= nl0O0i AND NOT(ni001i); + wire_nl1OlO_dataout <= nl0O0l AND NOT(ni001i); + wire_nl1OOi_dataout <= nl0O0O AND NOT(ni001i); + wire_nl1OOl_dataout <= nl0Oii AND NOT(ni001i); + wire_nl1OOO_dataout <= nl0Oil AND NOT(ni001i); + wire_nli_dataout <= rbisten_tx AND ((NOT rbist_sel(0)) AND rbist_sel(1)); + wire_nli00i_dataout <= wire_nli0Oi_o(1) AND ni001O; + wire_nli00l_dataout <= wire_nli0Oi_o(2) AND ni001O; + wire_nli00O_dataout <= wire_nli0Oi_o(3) AND ni001O; + wire_nli01i_dataout <= wire_nli0lO_o(5) AND ni001O; + wire_nli01l_dataout <= wire_nli0lO_o(6) AND ni001O; + wire_nli01O_dataout <= wire_nli0Oi_o(0) AND ni001O; + wire_nli0ii_dataout <= wire_nli0Oi_o(4) AND ni001O; + wire_nli0il_dataout <= wire_nli0Oi_o(5) AND ni001O; + wire_nli0iO_dataout <= wire_nli0Oi_o(6) AND ni001O; + wire_nli0li_dataout <= wire_nli0Oi_o(7) AND ni001O; + wire_nli10i_dataout <= wire_nli0ll_o(0) AND ni001O; + wire_nli10l_dataout <= wire_nli0ll_o(1) AND ni001O; + wire_nli10O_dataout <= wire_nli0ll_o(2) AND ni001O; + wire_nli1ii_dataout <= wire_nli0ll_o(3) AND ni001O; + wire_nli1il_dataout <= wire_nli0ll_o(4) AND ni001O; + wire_nli1iO_dataout <= wire_nli0ll_o(5) AND ni001O; + wire_nli1li_dataout <= wire_nli0ll_o(6) AND ni001O; + wire_nli1ll_dataout <= wire_nli0lO_o(0) AND ni001O; + wire_nli1lO_dataout <= wire_nli0lO_o(1) AND ni001O; + wire_nli1Oi_dataout <= wire_nli0lO_o(2) AND ni001O; + wire_nli1Ol_dataout <= wire_nli0lO_o(3) AND ni001O; + wire_nli1OO_dataout <= wire_nli0lO_o(4) AND ni001O; + wire_nlii_dataout <= niOOl AND niiOli; + wire_nlil_dataout <= niOOO AND niiOli; + wire_nlil0O_dataout <= wire_nllO1O_dataout AND n1iOl; + wire_nlilii_dataout <= wire_nllO0i_dataout AND n1iOl; + wire_nlilil_dataout <= niiOOi AND n1iOO; + wire_nlill_dataout <= wire_nliOl_o(0) AND wire_n0iiO_o; + wire_nlilli_dataout <= wire_nlO10l_dataout AND n1l1i; + wire_nlilll_dataout <= wire_nlO10O_dataout AND n1l1i; + wire_nlillO_dataout <= wire_nlOi0O_dataout AND n1l1l; + wire_nlilO_dataout <= wire_nliOl_o(1) AND wire_n0iiO_o; + wire_nliO_dataout <= nl11i AND niiOli; + wire_nliOi_dataout <= wire_nliOl_o(2) AND wire_n0iiO_o; + wire_nliOll_dataout <= wire_w_lg_niiOOi445w(0) AND n1ilO; + wire_nliOO_dataout <= wire_nllli_o(0) WHEN wire_n0iii_o = '1' ELSE wire_nll0l_dataout; + wire_nll_dataout <= rbisten_tx AND wire_w_lg_w_rbist_sel_range12w20w(0); + wire_nll0i_dataout <= wire_nllli_o(4) WHEN wire_n0iii_o = '1' ELSE wire_nlliO_dataout; + wire_nll0l_dataout <= niOii AND NOT(wire_n0iil_o); + wire_nll0O_dataout <= niOil AND NOT(wire_n0iil_o); + wire_nll11i_dataout <= wire_nlO1ll_dataout AND n1l1i; + wire_nll1i_dataout <= wire_nllli_o(1) WHEN wire_n0iii_o = '1' ELSE wire_nll0O_dataout; + wire_nll1l_dataout <= wire_nllli_o(2) WHEN wire_n0iii_o = '1' ELSE wire_nllii_dataout; + wire_nll1O_dataout <= wire_nllli_o(3) WHEN wire_n0iii_o = '1' ELSE wire_nllil_dataout; + wire_nll1Oi_dataout <= wire_nlOlOO_dataout AND n1l0l; + wire_nlli_dataout <= nl11l AND niiOli; + wire_nllii_dataout <= niOiO AND NOT(wire_n0iil_o); + wire_nllil_dataout <= niOli AND NOT(wire_n0iil_o); + wire_nlliO_dataout <= niOll AND NOT(wire_n0iil_o); + wire_nlll_dataout <= nl11O AND niiOli; + wire_nlllil_dataout <= ni0l0l AND NOT(ni0Oii); + wire_nllliO_dataout <= ni0l0l AND ni0Oii; + wire_nlllli_dataout <= wire_nlllOl_dataout AND NOT(niiOOi); + wire_nlllll_dataout <= wire_w_lg_ni0lii914w(0) WHEN niiOOi = '1' ELSE wire_nlllOO_dataout; + wire_nllllO_dataout <= wire_nllO1i_dataout AND niiOOi; + wire_nlllOi_dataout <= wire_nllO1l_dataout AND niiOOi; + wire_nlllOl_dataout <= ni0l0l WHEN ni0Oii = '1' ELSE ni0l0O; + wire_nlllOO_dataout <= wire_w_lg_ni0l0l913w(0) WHEN ni0Oii = '1' ELSE wire_w_lg_ni0l0O912w(0); + wire_nllO_dataout <= nl10i AND niiOli; + wire_nllO0i_dataout <= ni0lil WHEN niiOOi = '1' ELSE ni0liO; + wire_nllO0l_dataout <= wire_nllOll_dataout AND niiOOi; + wire_nllO0O_dataout <= wire_nllOlO_dataout AND niiOOi; + wire_nllO1i_dataout <= ni0lii AND NOT(ni0Oii); + wire_nllO1l_dataout <= ni0lii AND ni0Oii; + wire_nllO1O_dataout <= wire_w_lg_ni0lil911w(0) WHEN niiOOi = '1' ELSE wire_w_lg_ni0liO910w(0); + wire_nllOii_dataout <= wire_nllOOi_dataout AND niiOOi; + wire_nllOil_dataout <= wire_nllOOl_dataout AND niiOOi; + wire_nllOiO_dataout <= wire_nllOOO_dataout AND niiOOi; + wire_nllOli_dataout <= ni0lli AND niiOOi; + wire_nllOll_dataout <= wire_nlO11i_dataout AND NOT(ni0lli); + wire_nllOlO_dataout <= wire_nlO11l_dataout AND NOT(ni0lli); + wire_nllOOi_dataout <= wire_nlO11O_dataout AND NOT(ni0lli); + wire_nllOOl_dataout <= wire_nlO10i_dataout AND NOT(ni0lli); + wire_nllOOO_dataout <= wire_w_lg_ni0lll909w(0) AND NOT(ni0lli); + wire_nlO_dataout <= rbisten_tx AND (((NOT rbist_sel(0)) AND wire_w_lg_w_rbist_sel_range14w15w(0)) AND (niiOll6 XOR niiOll5)); + wire_nlO_w_lg_dataout1647w(0) <= NOT wire_nlO_dataout; + wire_nlO00i_dataout <= wire_nlO0li_dataout AND NOT(ni0lOO); + wire_nlO00l_dataout <= ni0lOi AND NOT(ni0lOO); + wire_nlO00O_dataout <= wire_nlO0ll_dataout AND NOT(ni0lOi); + wire_nlO01i_dataout <= wire_nlO0ii_dataout AND NOT(ni0lOO); + wire_nlO01l_dataout <= wire_nlO0il_dataout AND NOT(ni0lOO); + wire_nlO01O_dataout <= wire_nlO0iO_dataout AND NOT(ni0lOO); + wire_nlO0ii_dataout <= wire_nlO0lO_dataout AND NOT(ni0lOi); + wire_nlO0il_dataout <= wire_nlO0Oi_dataout AND NOT(ni0lOi); + wire_nlO0iO_dataout <= wire_nlO0Ol_dataout AND NOT(ni0lOi); + wire_nlO0li_dataout <= wire_w_lg_ni0lOl907w(0) AND NOT(ni0lOi); + wire_nlO0ll_dataout <= wire_nlO0OO_dataout AND ni0lOl; + wire_nlO0lO_dataout <= wire_nlOi1i_dataout AND ni0lOl; + wire_nlO0Oi_dataout <= wire_nlOi1l_dataout AND ni0lOl; + wire_nlO0Ol_dataout <= ni0Oii AND ni0lOl; + wire_nlO0OO_dataout <= wire_nlOi1O_dataout AND NOT(ni0Oii); + wire_nlO10i_dataout <= ni0Oii AND ni0lll; + wire_nlO10l_dataout <= wire_w_lg_ni0llO908w(0) OR NOT(niiOOi); + wire_nlO10O_dataout <= ni0llO AND niiOOi; + wire_nlO11i_dataout <= wire_nlO0OO_dataout AND ni0lll; + wire_nlO11l_dataout <= wire_nlOi1i_dataout AND ni0lll; + wire_nlO11O_dataout <= wire_nlOi1l_dataout AND ni0lll; + wire_nlO1ii_dataout <= wire_nlO1OO_dataout AND NOT(niiOOi); + wire_nlO1il_dataout <= wire_nlO01i_dataout AND NOT(niiOOi); + wire_nlO1iO_dataout <= wire_nlO01l_dataout AND NOT(niiOOi); + wire_nlO1li_dataout <= wire_nlO01O_dataout AND NOT(niiOOi); + wire_nlO1ll_dataout <= ni0llO WHEN niiOOi = '1' ELSE ni0lOO; + wire_nlO1lO_dataout <= wire_nlO00i_dataout AND NOT(niiOOi); + wire_nlO1Oi_dataout <= wire_w_lg_ni0llO908w(0) AND niiOOi; + wire_nlO1Ol_dataout <= wire_nlO00l_dataout AND NOT(niiOOi); + wire_nlO1OO_dataout <= wire_nlO00O_dataout AND NOT(ni0lOO); + wire_nlOi_dataout <= nl10l AND niiOli; + wire_nlOi0i_dataout <= ni0Oli AND NOT(ni0Oll); + wire_nlOi0O_dataout <= wire_nlOl1O_dataout WHEN niiOOi = '1' ELSE wire_nlOiiO_dataout; + wire_nlOi1i_dataout <= wire_nlOi0i_dataout AND NOT(ni0Oii); + wire_nlOi1l_dataout <= ni0Oll AND NOT(ni0Oii); + wire_nlOi1O_dataout <= wire_w_lg_ni0Oli906w(0) AND NOT(ni0Oll); + wire_nlOiii_dataout <= wire_nlOl0i_dataout WHEN niiOOi = '1' ELSE wire_nlOili_dataout; + wire_nlOiil_dataout <= wire_nlOl0l_dataout WHEN niiOOi = '1' ELSE wire_nlOill_dataout; + wire_nlOiiO_dataout <= wire_nlOiOO_dataout WHEN ni0Oii = '1' ELSE wire_nlOilO_dataout; + wire_nlOili_dataout <= wire_nlOl1i_dataout WHEN ni0Oii = '1' ELSE wire_nlOiOi_dataout; + wire_nlOill_dataout <= wire_nlOl1l_dataout WHEN ni0Oii = '1' ELSE wire_nlOiOl_dataout; + wire_nlOilO_dataout <= ni0O1i AND NOT(ni0O0i); + wire_nlOiOi_dataout <= ni0O1i OR ni0O0i; + wire_nlOiOl_dataout <= wire_w_lg_ni0O1i896w(0) AND NOT(ni0O0i); + wire_nlOiOO_dataout <= ni0O1l AND NOT(ni0O0O); + wire_nlOl_dataout <= nl10O AND niiOli; + wire_nlOl0i_dataout <= wire_nlOlli_dataout WHEN ni0Oii = '1' ELSE wire_nlOlii_dataout; + wire_nlOl0l_dataout <= wire_nlOlll_dataout WHEN ni0Oii = '1' ELSE wire_nlOlil_dataout; + wire_nlOl0O_dataout <= ni0O0i AND NOT(ni0O1O); + wire_nlOl1i_dataout <= ni0O1l OR ni0O0O; + wire_nlOl1l_dataout <= wire_w_lg_ni0O1l895w(0) AND NOT(ni0O0O); + wire_nlOl1O_dataout <= wire_nlOliO_dataout WHEN ni0Oii = '1' ELSE wire_nlOl0O_dataout; + wire_nlOlii_dataout <= ni0O0i OR ni0O1O; + wire_nlOlil_dataout <= wire_w_lg_ni0O0i894w(0) AND NOT(ni0O1O); + wire_nlOliO_dataout <= ni0O0O AND NOT(ni0O0l); + wire_nlOlli_dataout <= ni0O0O OR ni0O0l; + wire_nlOlll_dataout <= wire_w_lg_ni0O0O893w(0) AND NOT(ni0O0l); + wire_nlOllO_dataout <= wire_w_lg_ni0OiO892w(0) AND niiOOi; + wire_nlOlOi_dataout <= wire_nlOO1l_dataout OR niiOOi; + wire_nlOlOl_dataout <= ni0Oii AND NOT(niiOOi); + wire_nlOlOO_dataout <= wire_nlOO1O_dataout AND NOT(niiOOi); + wire_nlOO_dataout <= nl1ii AND niiOli; + wire_nlOO0i_dataout <= wire_nlOO0O_dataout AND NOT(ni0Oii); + wire_nlOO0l_dataout <= ni0Oil AND ni0OiO; + wire_nlOO0O_dataout <= wire_w_lg_ni0Oil891w(0) AND ni0OiO; + wire_nlOO1i_dataout <= wire_nlOO0i_dataout AND NOT(niiOOi); + wire_nlOO1l_dataout <= wire_nlOO0l_dataout AND NOT(ni0Oii); + wire_nlOO1O_dataout <= wire_w_lg_ni0OiO892w(0) AND NOT(ni0Oii); + wire_n00Oi_a <= ( n101i & n11OO & n11Ol & n11Oi & n11lO & n11ll & n11li & n11iO & n11il); + wire_n00Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n00Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_n00Oi_a, + b => wire_n00Oi_b, + cin => wire_gnd, + o => wire_n00Oi_o + ); + wire_n01iO_a <= ( n11ii & n110O & n110l & n110i); + wire_n01iO_b <= ( "0" & "0" & "0" & "1"); + n01iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n01iO_a, + b => wire_n01iO_b, + cin => wire_gnd, + o => wire_n01iO_o + ); + wire_n1lOi_a <= ( nlOOiO & nlOOil & nliliO); + wire_n1lOi_b <= ( "0" & "0" & "1"); + n1lOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_n1lOi_a, + b => wire_n1lOi_b, + cin => wire_gnd, + o => wire_n1lOi_o + ); + wire_n1Oll_a <= ( nlOOOO & nlOOOl & nlOOOi & nlOOlO & nlOOll & nlOOli); + wire_n1Oll_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n1Oll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n1Oll_a, + b => wire_n1Oll_b, + cin => wire_gnd, + o => wire_n1Oll_o + ); + wire_n1OOO_a <= ( n111O & n111l & n111i); + wire_n1OOO_b <= ( "0" & "0" & "1"); + n1OOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_n1OOO_a, + b => wire_n1OOO_b, + cin => wire_gnd, + o => wire_n1OOO_o + ); + wire_nli0ll_a <= ( nl00Ol & nl00Oi & nl00lO & nl00ll & nl00li & nl00iO & nl00il); + wire_nli0ll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nli0ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nli0ll_a, + b => wire_nli0ll_b, + cin => wire_gnd, + o => wire_nli0ll_o + ); + wire_nli0lO_a <= ( nl0i0O & nl0i0l & nl0i0i & nl0i1O & nl0i1l & nl0i1i & nl00OO); + wire_nli0lO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nli0lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nli0lO_a, + b => wire_nli0lO_b, + cin => wire_gnd, + o => wire_nli0lO_o + ); + wire_nli0Oi_a <= ( nl0iOl & nl0iOi & nl0ilO & nl0ill & nl0ili & nl0iiO & nl0iil & nl0iii); + wire_nli0Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nli0Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nli0Oi_a, + b => wire_nli0Oi_b, + cin => wire_gnd, + o => wire_nli0Oi_o + ); + wire_nliOl_a <= ( wire_niilOO16_w_lg_w_lg_q78w79w & niO0l & n0lOi); + wire_nliOl_b <= ( "0" & "0" & "1"); + nliOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_nliOl_a, + b => wire_nliOl_b, + cin => wire_gnd, + o => wire_nliOl_o + ); + wire_nllli_a <= ( niOll & niOli & niOiO & wire_niiO1i14_w_lg_w_lg_q53w54w & niOii); + wire_nllli_b <= ( "0" & "0" & "0" & "0" & "1"); + nllli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nllli_a, + b => wire_nllli_b, + cin => wire_gnd, + o => wire_nllli_o + ); + wire_n0iii_data <= ( "0" & wire_niiOl_dataout & wire_w_lg_niiill105w); + wire_n0iii_sel <= ( nii10l & nl0iO & nl0il); + n0iii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0iii_data, + o => wire_n0iii_o, + sel => wire_n0iii_sel + ); + wire_n0iil_data <= ( "0" & wire_niiOO_dataout & niiill); + wire_n0iil_sel <= ( nii10l & nl0iO & nl0il); + n0iil : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0iil_data, + o => wire_n0iil_o, + sel => wire_n0iil_sel + ); + wire_n0iiO_data <= ( "0" & wire_nilOi_dataout & wire_nii1O_dataout & wire_w_lg_niiiil107w & wire_w_lg_niiiil107w); + wire_n0iiO_sel <= ( ni0OOO & nli0O & nl01l & nl01i & nl1OO); + n0iiO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0iiO_data, + o => wire_n0iiO_o, + sel => wire_n0iiO_sel + ); + wire_n0ilO_data <= ( "0" & niiOOi); + wire_n0ilO_sel <= ( nii11i & wire_w_lg_nii11i695w); + n0ilO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n0ilO_data, + o => wire_n0ilO_o, + sel => wire_n0ilO_sel + ); + wire_n0iOl_data <= ( "0" & niiiil & wire_w_lg_niiiil107w); + wire_n0iOl_sel <= ( nii11l & nl01i & nl1OO); + n0iOl : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0iOl_data, + o => wire_n0iOl_o, + sel => wire_n0iOl_sel + ); + wire_n0l1i_data <= ( "0" & wire_nii1l_dataout & wire_w_lg_niiiil107w); + wire_n0l1i_sel <= ( nii11O & nl01l & nl01i); + n0l1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0l1i_data, + o => wire_n0l1i_o, + sel => wire_n0l1i_sel + ); + wire_n0l1O_data <= ( "0" & niiOOi & "1" & wire_nii1O_dataout); + wire_n0l1O_sel <= ( nii10i & nl0ii & wire_nliii_w_lg_w_lg_w_lg_nl00O654w655w656w & nl01l); + n0l1O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0l1O_data, + o => wire_n0l1O_o, + sel => wire_n0l1O_sel + ); + wire_n0lii_data <= ( "0" & wire_niili_dataout & wire_nil1i_dataout); + wire_n0lii_sel <= ( nii10l & nl0iO & nl0il); + n0lii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0lii_data, + o => wire_n0lii_o, + sel => wire_n0lii_sel + ); + wire_n0lil_data <= ( "0" & wire_niill_dataout & wire_nil1l_dataout); + wire_n0lil_sel <= ( nii10l & nl0iO & nl0il); + n0lil : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0lil_data, + o => wire_n0lil_o, + sel => wire_n0lil_sel + ); + wire_n0liO_data <= ( "0" & wire_niilO_dataout & wire_nil1O_dataout); + wire_n0liO_sel <= ( nii10l & nl0iO & nl0il); + n0liO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0liO_data, + o => wire_n0liO_o, + sel => wire_n0liO_sel + ); + wire_n0lli_data <= ( "0" & wire_niiOi_dataout & wire_nil0i_dataout); + wire_n0lli_sel <= ( nii10l & nl0iO & nl0il); + n0lli : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0lli_data, + o => wire_n0lli_o, + sel => wire_n0lli_sel + ); + wire_n0lOl_data <= ( "0" & niiOOi & "1"); + wire_n0lOl_sel <= ( nii10O & nl0ll & nl0li); + n0lOl : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0lOl_data, + o => wire_n0lOl_o, + sel => wire_n0lOl_sel + ); + wire_n0O0l_data <= ( "0" & niiOOi & "1"); + wire_n0O0l_sel <= ( nii1il & nl0OO & nl0Ol); + n0O0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0O0l_data, + o => wire_n0O0l_o, + sel => wire_n0O0l_sel + ); + wire_n0O1l_data <= ( "0" & niiOOi & "1"); + wire_n0O1l_sel <= ( nii1ii & nl0Oi & nl0lO); + n0O1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0O1l_data, + o => wire_n0O1l_o, + sel => wire_n0O1l_sel + ); + wire_n0Oil_data <= ( "0" & niiOOi & "1"); + wire_n0Oil_sel <= ( nii1iO & nli1l & nli1i); + n0Oil : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0Oil_data, + o => wire_n0Oil_o, + sel => wire_n0Oil_sel + ); + wire_n0Oll_data <= ( "0" & niiOOi & "1"); + wire_n0Oll_sel <= ( nii1li & nli0i & nli1O); + n0Oll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0Oll_data, + o => wire_n0Oll_o, + sel => wire_n0Oll_sel + ); + wire_n0OOl_data <= ( "0" & niiOOi & wire_nilll_dataout & "1" & wire_niiOl_dataout & wire_w_lg_niiill105w); + wire_n0OOl_sel <= ( nii1ll & nliil & nli0O & nli0l & nl0iO & nl0il); + n0OOl : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n0OOl_data, + o => wire_n0OOl_o, + sel => wire_n0OOl_sel + ); + wire_ni00l_data <= ( "0" & niiOOi); + wire_ni00l_sel <= ( nii00l & wire_w_lg_nii00l246w); + ni00l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni00l_data, + o => wire_ni00l_o, + sel => wire_ni00l_sel + ); + wire_ni01i_data <= ( "0" & wire_nii1OO44_w_lg_w_lg_q295w296w); + wire_ni01i_sel <= ( nii01i & wire_w_lg_nii01i291w); + ni01i : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni01i_data, + o => wire_ni01i_o, + sel => wire_ni01i_sel + ); + wire_ni01O_data <= ( "0" & niiOOi); + wire_ni01O_sel <= ( nii01l & wire_w_lg_nii01l267w); + ni01O : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni01O_data, + o => wire_ni01O_o, + sel => wire_ni01O_sel + ); + wire_ni0ii_data <= ( "0" & niiOOi); + wire_ni0ii_sel <= ( nii0ii & wire_nii00O40_w_lg_w_lg_q228w230w); + ni0ii : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni0ii_data, + o => wire_ni0ii_o, + sel => wire_ni0ii_sel + ); + wire_ni0iO_data <= ( "0" & niiOOi); + wire_ni0iO_sel <= ( wire_nii0li36_w_lg_w_lg_q207w208w & wire_w_lg_nii0ll204w); + ni0iO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni0iO_data, + o => wire_ni0iO_o, + sel => wire_ni0iO_sel + ); + wire_ni0ll_data <= ( "0" & niiOOi); + wire_ni0ll_sel <= ( nii0Ol & wire_w_lg_nii0Ol176w); + ni0ll : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni0ll_data, + o => wire_ni0ll_o, + sel => wire_ni0ll_sel + ); + wire_ni0Oi_data <= ( "0" & wire_nii0OO32_w_lg_w_lg_q155w156w & wire_niii1i30_w_lg_w_lg_q152w153w & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi); + wire_ni0Oi_sel <= ( wire_niii1l28_w_lg_w_lg_q141w142w & nli0O & nli0i & nl0OO & nl0ll & nl0ii & nl00O & wire_niii1O26_w_lg_w_lg_q132w133w & wire_niii0i24_w_lg_w_lg_q129w130w & nl01l); + ni0Oi : oper_selector + GENERIC MAP ( + width_data => 10, + width_sel => 10 + ) + PORT MAP ( + data => wire_ni0Oi_data, + o => wire_ni0Oi_o, + sel => wire_ni0Oi_sel + ); + wire_ni10i_data <= ( niiilO & "0" & wire_nii0l_dataout & wire_nii1i_dataout); + wire_ni10i_sel <= ( nlili & nii1Oi & nl01l & nl1OO); + ni10i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni10i_data, + o => wire_ni10i_o, + sel => wire_ni10i_sel + ); + wire_ni11l_data <= ( wire_w_lg_niiilO447w & wire_w_lg_niiOOi445w & wire_nilOi_dataout & "0" & wire_nii0i_dataout & wire_ni0OO_dataout); + wire_ni11l_sel <= ( nlili & nliil & nli0O & nii1lO & nl01l & nl1OO); + ni11l : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_ni11l_data, + o => wire_ni11l_o, + sel => wire_ni11l_sel + ); + wire_ni1Ol_data <= ( "0" & niiOOi); + wire_ni1Ol_sel <= ( nii1Ol & wire_w_lg_nii1Ol312w); + ni1Ol : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni1Ol_data, + o => wire_ni1Ol_o, + sel => wire_ni1Ol_sel + ); + wire_nil00l_data <= ( "0" & "1" & wire_niO00O_dataout); + wire_nil00l_sel <= ( wire_nli11l_w_lg_nli11O2169w & ni1lOO & nl0OOi); + nil00l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nil00l_data, + o => wire_nil00l_o, + sel => wire_nil00l_sel + ); + wire_nil01O_data <= ( "0" & "1" & niiOOi & wire_niO00l_dataout); + wire_nil01O_sel <= ( nli11O & ni1lOl & nl0OOl & nl0OOi); + nil01O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nil01O_data, + o => wire_nil01O_o, + sel => wire_nil01O_sel + ); + wire_nil0il_data <= ( "0" & "1" & wire_niO0ii_dataout); + wire_nil0il_sel <= ( nli11O & ni1O1i & nl0OOi); + nil0il : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nil0il_data, + o => wire_nil0il_o, + sel => wire_nil0il_sel + ); + wire_nil0li_data <= ( "0" & "1" & wire_niO0il_dataout); + wire_nil0li_sel <= ( ni1O1O & ni1O1l & nl0OOi); + nil0li : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nil0li_data, + o => wire_nil0li_o, + sel => wire_nil0li_sel + ); + wire_nil0Oi_data <= ( "0" & wire_w_lg_niiOOi445w & wire_niO0iO_dataout & "1"); + wire_nil0Oi_sel <= ( ni1O0l & nl0OOl & nl0OOi & ni1O0i); + nil0Oi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nil0Oi_data, + o => wire_nil0Oi_o, + sel => wire_nil0Oi_sel + ); + wire_nil1li_data <= ( "0" & niiOOi); + wire_nil1li_sel <= ( ni1lll & wire_w_lg_ni1lll2233w); + nil1li : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nil1li_data, + o => wire_nil1li_o, + sel => wire_nil1li_sel + ); + wire_nil1lO_data <= ( "0" & wire_w_lg_niiOOi445w & wire_niO01O_dataout & "1"); + wire_nil1lO_sel <= ( ni1llO & nl0OOl & nl0OOi & wire_nl0OOO_w_lg_nl0O0l2215w); + nil1lO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nil1lO_data, + o => wire_nil1lO_o, + sel => wire_nil1lO_sel + ); + wire_nil1OO_data <= ( "0" & wire_w_lg_niiOOi445w & wire_niO00i_dataout & "1"); + wire_nil1OO_sel <= ( ni1lOi & nl0OOl & nl0OOi & wire_nl0OOO_w_lg_nl0O0l2201w); + nil1OO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nil1OO_data, + o => wire_nil1OO_o, + sel => wire_nil1OO_sel + ); + wire_nili0i_data <= ( "0" & niiOOi); + wire_nili0i_sel <= ( ni1Oil & wire_w_lg_ni1Oil2081w); + nili0i : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nili0i_data, + o => wire_nili0i_o, + sel => wire_nili0i_sel + ); + wire_nili0O_data <= ( "0" & niiOOi & wire_niO0ll_dataout & niiOOi); + wire_nili0O_sel <= ( ni1OiO & nl0OOl & nl0OOi & nl0O0O); + nili0O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nili0O_data, + o => wire_nili0O_o, + sel => wire_nili0O_sel + ); + wire_nili1i_data <= ( "0" & "1" & wire_niO0li_dataout); + wire_nili1i_sel <= ( ni1Oii & ni1O0O & nl0OOi); + nili1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nili1i_data, + o => wire_nili1i_o, + sel => wire_nili1i_sel + ); + wire_niliil_data <= ( "0" & niiOOi & wire_niO0lO_dataout & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi); + wire_niliil_sel <= ( ni1Oli & nli11i & nl0OOi & nl0OlO & nl0Oli & nl0Oil & nl0O0O & nl0O0i); + niliil : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_niliil_data, + o => wire_niliil_o, + sel => wire_niliil_sel + ); + wire_nilili_data <= ( "0" & niiOOi & niiOOi & wire_niO0Oi_dataout & niiOOi & niiOOi & niiOOi & niiOOi); + wire_nilili_sel <= ( ni1Oll & nli11i & nl0OOl & nl0OOi & nl0OlO & nl0Oli & nl0Oil & nl0O0i); + nilili : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nilili_data, + o => wire_nilili_o, + sel => wire_nilili_sel + ); + wire_nililO_data <= ( "0" & niiOOi & niiOOi & wire_niO0Ol_dataout & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi); + wire_nililO_sel <= ( ni1OlO & nli11i & nl0OOl & nl0OOi & nl0OlO & nl0Oli & nl0Oil & nl0O0O & nl0O0i); + nililO : oper_selector + GENERIC MAP ( + width_data => 9, + width_sel => 9 + ) + PORT MAP ( + data => wire_nililO_data, + o => wire_nililO_o, + sel => wire_nililO_sel + ); + wire_niliOl_data <= ( "0" & niiOOi & niiOOi & wire_niO0OO_dataout & niiOOi & niiOOi & niiOOi & niiOOi); + wire_niliOl_sel <= ( ni1OOi & nli11i & nl0OOl & nl0OOi & nl0OlO & nl0Oli & nl0O0O & nl0O0i); + niliOl : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_niliOl_data, + o => wire_niliOl_o, + sel => wire_niliOl_sel + ); + wire_nill0O_data <= ( wire_nl01iO_dataout & wire_nl11Ol_dataout & "0" & wire_niO10i_dataout & wire_niO11O_dataout); + wire_nill0O_sel <= ( nli11O & nli11i & ni011i & nl0OOi & nl0O0i); + nill0O : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nill0O_data, + o => wire_nill0O_o, + sel => wire_nill0O_sel + ); + wire_nill1i_data <= ( "0" & niiOOi & wire_niOi1i_dataout & niiOOi & niiOOi & niiOOi & niiOOi); + wire_nill1i_sel <= ( ni1OOl & nl0OOl & nl0OOi & nl0Oli & nl0Oil & nl0O0O & nl0O0i); + nill1i : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nill1i_data, + o => wire_nill1i_o, + sel => wire_nill1i_sel + ); + wire_nill1O_data <= ( "0" & niiOOi & niiOOi & wire_niOi1l_dataout & niiOOi & niiOOi & niiOOi); + wire_nill1O_sel <= ( ni1OOO & nli11i & nl0OOl & nl0OOi & nl0Oil & nl0O0O & nl0O0i); + nill1O : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nill1O_data, + o => wire_nill1O_o, + sel => wire_nill1O_sel + ); + wire_nillil_data <= ( wire_nl01li_dataout & wire_nl11OO_dataout & "0" & wire_niO10l_dataout & wire_niO11l_dataout & wire_nlO_dataout); + wire_nillil_sel <= ( nli11O & nli11i & ni011l & nl0OOi & nl0O0O & nl0O0l); + nillil : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nillil_data, + o => wire_nillil_o, + sel => wire_nillil_sel + ); + wire_nillli_data <= ( wire_nl01ll_dataout & wire_nl101i_dataout & "0" & wire_niO10O_dataout & wire_niO11O_dataout); + wire_nillli_sel <= ( nli11O & nli11i & ni011O & nl0OOi & nl0O0O); + nillli : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nillli_data, + o => wire_nillli_o, + sel => wire_nillli_sel + ); + wire_nilllO_data <= ( wire_nl01lO_dataout & wire_nl101l_dataout & "0" & wire_niO1ii_dataout & wire_niO11l_dataout & wire_nlO_dataout); + wire_nilllO_sel <= ( nli11O & nli11i & ni010i & nl0OOi & nl0Oil & nl0Oii); + nilllO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nilllO_data, + o => wire_nilllO_o, + sel => wire_nilllO_sel + ); + wire_nillOl_data <= ( wire_nl01Oi_dataout & wire_nl101O_dataout & "0" & wire_niO1il_dataout & wire_niO11O_dataout); + wire_nillOl_sel <= ( nli11O & nli11i & ni010l & nl0OOi & nl0Oil); + nillOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nillOl_data, + o => wire_nillOl_o, + sel => wire_nillOl_sel + ); + wire_nilO0l_data <= ( wire_nl001i_dataout & wire_nl100O_dataout & "0" & wire_niO1ll_dataout & wire_niO11l_dataout & wire_nlO_dataout); + wire_nilO0l_sel <= ( nli11O & nli11i & ni01il & nl0OOi & nl0OlO & nl0Oll); + nilO0l : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nilO0l_data, + o => wire_nilO0l_o, + sel => wire_nilO0l_sel + ); + wire_nilO1i_data <= ( wire_nl01Ol_dataout & wire_nl100i_dataout & "0" & wire_niO1iO_dataout & wire_niO11l_dataout & wire_nlO_dataout); + wire_nilO1i_sel <= ( nli11O & nli11i & ni010O & nl0OOi & nl0Oli & nl0OiO); + nilO1i : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nilO1i_data, + o => wire_nilO1i_o, + sel => wire_nilO1i_sel + ); + wire_nilO1O_data <= ( wire_nl01OO_dataout & wire_nl100l_dataout & "0" & wire_niO1li_dataout & wire_niO11O_dataout); + wire_nilO1O_sel <= ( nli11O & nli11i & ni01ii & nl0OOi & nl0Oli); + nilO1O : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nilO1O_data, + o => wire_nilO1O_o, + sel => wire_nilO1O_sel + ); + wire_nilOii_data <= ( wire_nl001l_dataout & wire_nl10ii_dataout & "0" & wire_niO1lO_dataout & wire_niO11O_dataout); + wire_nilOii_sel <= ( nli11O & nli11i & ni01iO & nl0OOi & nl0OlO); + nilOii : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nilOii_data, + o => wire_nilOii_o, + sel => wire_nilOii_sel + ); + wire_nilOiO_data <= ( wire_nl001O_dataout & wire_nl10il_dataout & "0" & wire_niO1Oi_dataout); + wire_nilOiO_sel <= ( nli11O & nli11i & ni01ll & nl0OOi); + nilOiO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilOiO_data, + o => wire_nilOiO_o, + sel => wire_nilOiO_sel + ); + wire_nilOli_data <= ( wire_nl000i_dataout & wire_nl10iO_dataout & wire_nlO_dataout & wire_niO1Ol_dataout & "0"); + wire_nilOli_sel <= ( nli11O & nli11i & nl0OOl & nl0OOi & ni01li); + nilOli : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nilOli_data, + o => wire_nilOli_o, + sel => wire_nilOli_sel + ); + wire_nilOlO_data <= ( wire_nl000l_dataout & wire_nl10li_dataout & "0" & wire_niO1OO_dataout); + wire_nilOlO_sel <= ( nli11O & nli11i & ni01ll & nl0OOi); + nilOlO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilOlO_data, + o => wire_nilOlO_o, + sel => wire_nilOlO_sel + ); + wire_nilOOl_data <= ( wire_nl000O_dataout & wire_nl10ll_dataout & "0" & wire_niO01i_dataout & wire_niO11l_dataout & wire_nlO_dataout); + wire_nilOOl_sel <= ( nli11O & nli11i & ni01lO & nl0OOi & nl0O0i & nl0O1O); + nilOOl : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nilOOl_data, + o => wire_nilOOl_o, + sel => wire_nilOOl_sel + ); + wire_niO11i_data <= ( wire_nl00ii_dataout & wire_nl10lO_dataout & wire_nlO_w_lg_dataout1647w & wire_niO01l_dataout & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w & wire_nlO_w_lg_dataout1647w); + wire_niO11i_sel <= ( nli11O & nli11i & nl0OOl & nl0OOi & nl0OlO & nl0Oll & nl0Oli & nl0OiO & nl0Oil & nl0Oii & nl0O0O & nl0O0l & nl0O0i & nl0O1O); + niO11i : oper_selector + GENERIC MAP ( + width_data => 14, + width_sel => 14 + ) + PORT MAP ( + data => wire_niO11i_data, + o => wire_niO11i_o, + sel => wire_niO11i_sel + ); + wire_nlilOi_data <= ( "0" & wire_nlOO1i_dataout & wire_nlllll_dataout & wire_w_lg_ni0l0l913w & wire_w_lg_ni0l0l913w); + wire_nlilOi_sel <= ( ni000i & n1l0l & n1iii & n1i0O & n1i0l); + nlilOi : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilOi_data, + o => wire_nlilOi_o, + sel => wire_nlilOi_sel + ); + wire_nliO0l_data <= ( "0" & wire_nlllli_dataout & wire_w_lg_ni0l0l913w); + wire_nliO0l_sel <= ( ni00ii & n1iii & n1i0O); + nliO0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliO0l_data, + o => wire_nliO0l_o, + sel => wire_nliO0l_sel + ); + wire_nliO1i_data <= ( "0" & niiOOi); + wire_nliO1i_sel <= ( ni000l & wire_w_lg_ni000l1442w); + nliO1i : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nliO1i_data, + o => wire_nliO1i_o, + sel => wire_nliO1i_sel + ); + wire_nliO1O_data <= ( "0" & ni0l0l & wire_w_lg_ni0l0l913w); + wire_nliO1O_sel <= ( ni000O & n1i0O & n1i0l); + nliO1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliO1O_data, + o => wire_nliO1O_o, + sel => wire_nliO1O_sel + ); + wire_nliOii_data <= ( "0" & niiOOi & "1" & wire_nlllll_dataout); + wire_nliOii_sel <= ( ni00il & n1ilO & wire_n1l0O_w_lg_w_lg_w_lg_n1ill1401w1402w1403w & n1iii); + nliOii : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nliOii_data, + o => wire_nliOii_o, + sel => wire_nliOii_sel + ); + wire_nliOli_data <= ( "0" & wire_nlO1ii_dataout & wire_nllO0l_dataout); + wire_nliOli_sel <= ( ni00iO & n1l1i & n1iOO); + nliOli : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliOli_data, + o => wire_nliOli_o, + sel => wire_nliOli_sel + ); + wire_nliOlO_data <= ( "0" & wire_nlO1il_dataout & wire_nllO0O_dataout); + wire_nliOlO_sel <= ( ni00iO & n1l1i & n1iOO); + nliOlO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliOlO_data, + o => wire_nliOlO_o, + sel => wire_nliOlO_sel + ); + wire_nliOOi_data <= ( "0" & wire_nlO1iO_dataout & wire_nllOii_dataout); + wire_nliOOi_sel <= ( ni00iO & n1l1i & n1iOO); + nliOOi : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliOOi_data, + o => wire_nliOOi_o, + sel => wire_nliOOi_sel + ); + wire_nliOOl_data <= ( "0" & wire_nlO1li_dataout & wire_nllOil_dataout); + wire_nliOOl_sel <= ( ni00iO & n1l1i & n1iOO); + nliOOl : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliOOl_data, + o => wire_nliOOl_o, + sel => wire_nliOOl_sel + ); + wire_nll00O_data <= ( "0" & "1" & wire_w_lg_niiOOi445w); + wire_nll00O_sel <= ( ni0i0l & ni0i0i & n1iOi); + nll00O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll00O_data, + o => wire_nll00O_o, + sel => wire_nll00O_sel + ); + wire_nll01i_data <= ( ni0Oii & "0" & wire_nlllOi_dataout & wire_nllliO_dataout); + wire_nll01i_sel <= ( n1liO & ni0i1i & n1iii & n1i0l); + nll01i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll01i_data, + o => wire_nll01i_o, + sel => wire_nll01i_sel + ); + wire_nll01O_data <= ( "0" & "1" & wire_w_lg_niiOOi445w); + wire_nll01O_sel <= ( ni0i1O & ni0i1l & n1iOi); + nll01O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll01O_data, + o => wire_nll01O_o, + sel => wire_nll01O_sel + ); + wire_nll0iO_data <= ( "0" & "1" & niiOOi); + wire_nll0iO_sel <= ( ni0iii & ni0i0O & n1iOi); + nll0iO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll0iO_data, + o => wire_nll0iO_o, + sel => wire_nll0iO_sel + ); + wire_nll0lO_data <= ( "0" & "1" & wire_w_lg_niiOOi445w); + wire_nll0lO_sel <= ( ni0iiO & ni0iil & n1iOi); + nll0lO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll0lO_data, + o => wire_nll0lO_o, + sel => wire_nll0lO_sel + ); + wire_nll0OO_data <= ( "0" & "1" & niiOOi); + wire_nll0OO_sel <= ( wire_n1lil_w_lg_w_lg_w_lg_n1liO1051w1092w1093w & ni0ili & n1iOi); + nll0OO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll0OO_data, + o => wire_nll0OO_o, + sel => wire_nll0OO_sel + ); + wire_nll10i_data <= ( "0" & wire_nlO1lO_dataout & wire_nllOiO_dataout & wire_nllO0i_dataout); + wire_nll10i_sel <= ( ni00ll & n1l1i & n1iOO & n1iOl); + nll10i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll10i_data, + o => wire_nll10i_o, + sel => wire_nll10i_sel + ); + wire_nll10O_data <= ( "0" & wire_nlOiii_dataout & wire_nlO1Oi_dataout & wire_w_lg_niiOOi445w); + wire_nll10O_sel <= ( ni00lO & n1l1l & n1l1i & n1iOO); + nll10O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll10O_data, + o => wire_nll10O_o, + sel => wire_nll10O_sel + ); + wire_nll11l_data <= ( "0" & "1" & wire_nllO1O_dataout); + wire_nll11l_sel <= ( ni00li & n1iOi & n1iOl); + nll11l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll11l_data, + o => wire_nll11l_o, + sel => wire_nll11l_sel + ); + wire_nll1il_data <= ( "0" & wire_nlOlOi_dataout & "1" & wire_nlOiil_dataout & wire_nlO1Ol_dataout & wire_nllOli_dataout); + wire_nll1il_sel <= ( ni00Oi & n1l0l & wire_n1l0O_w_lg_n1l0i1211w & n1l1l & n1l1i & n1iOO); + nll1il : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nll1il_data, + o => wire_nll1il_o, + sel => wire_nll1il_sel + ); + wire_nll1ll_data <= ( "0" & niiOOi & wire_nlOlOl_dataout); + wire_nll1ll_sel <= ( ni00Ol & n1lii & n1l0l); + nll1ll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll1ll_data, + o => wire_nll1ll_o, + sel => wire_nll1ll_sel + ); + wire_nll1Ol_data <= ( wire_w_lg_ni0Oii1237w & wire_w_lg_niiOOi445w & wire_nlOO1i_dataout & "0" & wire_nllllO_dataout & wire_nlllil_dataout); + wire_nll1Ol_sel <= ( n1liO & n1lii & n1l0l & ni00OO & n1iii & n1i0l); + nll1Ol : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nll1Ol_data, + o => wire_nll1Ol_o, + sel => wire_nll1Ol_sel + ); + wire_nlli0i_data <= ( "0" & "1" & niiOOi); + wire_nlli0i_sel <= ( ni0ilO & ni0ill & n1iOi); + nlli0i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlli0i_data, + o => wire_nlli0i_o, + sel => wire_nlli0i_sel + ); + wire_nlliil_data <= ( "0" & niiOOi); + wire_nlliil_sel <= ( ni0iOi & wire_w_lg_ni0iOi1037w); + nlliil : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlliil_data, + o => wire_nlliil_o, + sel => wire_nlliil_sel + ); + wire_nllili_data <= ( "0" & niiOOi); + wire_nllili_sel <= ( ni0iOl & wire_w_lg_ni0iOl1019w); + nllili : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllili_data, + o => wire_nllili_o, + sel => wire_nllili_sel + ); + wire_nllilO_data <= ( "0" & niiOOi); + wire_nllilO_sel <= ( ni0l1i & wire_w_lg_ni0l1i983w); + nllilO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllilO_data, + o => wire_nllilO_o, + sel => wire_nllilO_sel + ); + wire_nlliOi_data <= ( "0" & niiOOi); + wire_nlliOi_sel <= ( ni0iOO & wire_w_lg_ni0iOO996w); + nlliOi : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlliOi_data, + o => wire_nlliOi_o, + sel => wire_nlliOi_sel + ); + wire_nlliOO_data <= ( "0" & niiOOi); + wire_nlliOO_sel <= ( ni0l1i & wire_w_lg_ni0l1i983w); + nlliOO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlliOO_data, + o => wire_nlliOO_o, + sel => wire_nlliOO_sel + ); + wire_nlll0i_data <= ( "0" & niiOOi); + wire_nlll0i_sel <= ( ni0l1O & wire_w_lg_ni0l1O957w); + nlll0i : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlll0i_data, + o => wire_nlll0i_o, + sel => wire_nlll0i_sel + ); + wire_nlll0O_data <= ( "0" & wire_nlOllO_dataout & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi & niiOOi); + wire_nlll0O_sel <= ( ni0l0i & n1l0l & n1l1i & n1iOO & n1iOi & n1iOl & n1ilO & n1ill & n1ili & n1iil & n1iii); + nlll0O : oper_selector + GENERIC MAP ( + width_data => 11, + width_sel => 11 + ) + PORT MAP ( + data => wire_nlll0O_data, + o => wire_nlll0O_o, + sel => wire_nlll0O_sel + ); + wire_nlll1l_data <= ( "0" & niiOOi); + wire_nlll1l_sel <= ( ni0l1l & wire_w_lg_ni0l1l970w); + nlll1l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlll1l_data, + o => wire_nlll1l_o, + sel => wire_nlll1l_sel + ); + + END RTL; --cycloneiv_hssi_tx_digi_bist_gen +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 106 mux21 189 oper_add 1 oper_decoder 1 oper_mux 23 oper_selector 23 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_tx_digi_prbs_gen IS + PORT + ( + cid_en : IN STD_LOGIC; + prbs_out : OUT STD_LOGIC_VECTOR (19 DOWNTO 0); + rcid_len : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rcid_pattern : IN STD_LOGIC; + rpma_doublewidth_tx : IN STD_LOGIC; + rpmadwidth_tx : IN STD_LOGIC; + rprbs_en_tx : IN STD_LOGIC; + rprbs_sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + soft_reset : IN STD_LOGIC; + tx_clk : IN STD_LOGIC + ); + END cycloneiv_hssi_tx_digi_prbs_gen; + + ARCHITECTURE RTL OF cycloneiv_hssi_tx_digi_prbs_gen IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nll00l33 : STD_LOGIC := '0'; + SIGNAL nll00l34 : STD_LOGIC := '0'; + SIGNAL wire_nll00l34_w_lg_w_lg_q141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll00l34_w_lg_q141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nll01i37 : STD_LOGIC := '0'; + SIGNAL nll01i38 : STD_LOGIC := '0'; + SIGNAL wire_nll01i38_w_lg_w_lg_q152w153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll01i38_w_lg_q152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nll01O35 : STD_LOGIC := '0'; + SIGNAL nll01O36 : STD_LOGIC := '0'; + SIGNAL nll0ii31 : STD_LOGIC := '0'; + SIGNAL nll0ii32 : STD_LOGIC := '0'; + SIGNAL nll0iO29 : STD_LOGIC := '0'; + SIGNAL nll0iO30 : STD_LOGIC := '0'; + SIGNAL nll0Ol27 : STD_LOGIC := '0'; + SIGNAL nll0Ol28 : STD_LOGIC := '0'; + SIGNAL nll1ii45 : STD_LOGIC := '0'; + SIGNAL nll1ii46 : STD_LOGIC := '0'; + SIGNAL nll1li43 : STD_LOGIC := '0'; + SIGNAL nll1li44 : STD_LOGIC := '0'; + SIGNAL nll1lO41 : STD_LOGIC := '0'; + SIGNAL nll1lO42 : STD_LOGIC := '0'; + SIGNAL nll1Ol39 : STD_LOGIC := '0'; + SIGNAL nll1Ol40 : STD_LOGIC := '0'; + SIGNAL wire_nll1Ol40_w_lg_w_lg_q157w158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1Ol40_w_lg_q157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlli0l23 : STD_LOGIC := '0'; + SIGNAL nlli0l24 : STD_LOGIC := '0'; + SIGNAL nlli1O25 : STD_LOGIC := '0'; + SIGNAL nlli1O26 : STD_LOGIC := '0'; + SIGNAL nlliil21 : STD_LOGIC := '0'; + SIGNAL nlliil22 : STD_LOGIC := '0'; + SIGNAL wire_nlliil22_w_lg_w_lg_q93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlliil22_w_lg_q93w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlliiO19 : STD_LOGIC := '0'; + SIGNAL nlliiO20 : STD_LOGIC := '0'; + SIGNAL wire_nlliiO20_w_lg_w_lg_q88w89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlliiO20_w_lg_q88w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nllill17 : STD_LOGIC := '0'; + SIGNAL nllill18 : STD_LOGIC := '0'; + SIGNAL wire_nllill18_w_lg_w_lg_q79w80w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllill18_w_lg_q79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlliOi15 : STD_LOGIC := '0'; + SIGNAL nlliOi16 : STD_LOGIC := '0'; + SIGNAL wire_nlliOi16_w_lg_w_lg_q69w70w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlliOi16_w_lg_q69w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlll0O11 : STD_LOGIC := '0'; + SIGNAL nlll0O12 : STD_LOGIC := '0'; + SIGNAL nlll1i13 : STD_LOGIC := '0'; + SIGNAL nlll1i14 : STD_LOGIC := '0'; + SIGNAL nlllil10 : STD_LOGIC := '0'; + SIGNAL wire_nlllil10_w_lg_w_lg_q20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlllil10_w_lg_q20w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlllil9 : STD_LOGIC := '0'; + SIGNAL nllliO7 : STD_LOGIC := '0'; + SIGNAL nllliO8 : STD_LOGIC := '0'; + SIGNAL wire_nllliO8_w_lg_w_lg_q17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllliO8_w_lg_q17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlllli5 : STD_LOGIC := '0'; + SIGNAL nlllli6 : STD_LOGIC := '0'; + SIGNAL wire_nlllli6_w_lg_w_lg_q12w13w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlllli6_w_lg_q12w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlllll3 : STD_LOGIC := '0'; + SIGNAL nlllll4 : STD_LOGIC := '0'; + SIGNAL wire_nlllll4_w_lg_w_lg_q7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlllll4_w_lg_q7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlllOl1 : STD_LOGIC := '0'; + SIGNAL nlllOl2 : STD_LOGIC := '0'; + SIGNAL ni0O : STD_LOGIC := '0'; + SIGNAL nlO0Ol : STD_LOGIC := '0'; + SIGNAL nlO0OO : STD_LOGIC := '0'; + SIGNAL nlOi0i : STD_LOGIC := '0'; + SIGNAL nlOi0l : STD_LOGIC := '0'; + SIGNAL nlOi0O : STD_LOGIC := '0'; + SIGNAL nlOi1i : STD_LOGIC := '0'; + SIGNAL nlOi1l : STD_LOGIC := '0'; + SIGNAL nlOi1O : STD_LOGIC := '0'; + SIGNAL nlOiii : STD_LOGIC := '0'; + SIGNAL nlOiil : STD_LOGIC := '0'; + SIGNAL nlOiiO : STD_LOGIC := '0'; + SIGNAL nlOili : STD_LOGIC := '0'; + SIGNAL nlOill : STD_LOGIC := '0'; + SIGNAL nlOilO : STD_LOGIC := '0'; + SIGNAL nlOiOi : STD_LOGIC := '0'; + SIGNAL nlOiOl : STD_LOGIC := '0'; + SIGNAL nlOiOO : STD_LOGIC := '0'; + SIGNAL nlOl1i : STD_LOGIC := '0'; + SIGNAL nlOl1l : STD_LOGIC := '0'; + SIGNAL nlOl1O : STD_LOGIC := '0'; + SIGNAL wire_ni0l_PRN : STD_LOGIC; + SIGNAL wire_ni0l_w_lg_ni0O182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0i : STD_LOGIC := '0'; + SIGNAL n1i : STD_LOGIC := '0'; + SIGNAL n1l : STD_LOGIC := '0'; + SIGNAL n1O : STD_LOGIC := '0'; + SIGNAL nili : STD_LOGIC := '0'; + SIGNAL nill : STD_LOGIC := '0'; + SIGNAL nlll : STD_LOGIC := '0'; + SIGNAL nllO : STD_LOGIC := '0'; + SIGNAL nlOi : STD_LOGIC := '0'; + SIGNAL nlOl : STD_LOGIC := '0'; + SIGNAL nlOl0i : STD_LOGIC := '0'; + SIGNAL nlOl0l : STD_LOGIC := '0'; + SIGNAL nlOl0O : STD_LOGIC := '0'; + SIGNAL nlOlii : STD_LOGIC := '0'; + SIGNAL nlOlil : STD_LOGIC := '0'; + SIGNAL nlOliO : STD_LOGIC := '0'; + SIGNAL nlOlli : STD_LOGIC := '0'; + SIGNAL nlOlll : STD_LOGIC := '0'; + SIGNAL nlOllO : STD_LOGIC := '0'; + SIGNAL nlOlOi : STD_LOGIC := '0'; + SIGNAL nlOlOl : STD_LOGIC := '0'; + SIGNAL nlOlOO : STD_LOGIC := '0'; + SIGNAL nlOO : STD_LOGIC := '0'; + SIGNAL nlOO0i : STD_LOGIC := '0'; + SIGNAL nlOO0l : STD_LOGIC := '0'; + SIGNAL nlOO0O : STD_LOGIC := '0'; + SIGNAL nlOO1i : STD_LOGIC := '0'; + SIGNAL nlOO1l : STD_LOGIC := '0'; + SIGNAL nlOO1O : STD_LOGIC := '0'; + SIGNAL nlOOii : STD_LOGIC := '0'; + SIGNAL nlOOil : STD_LOGIC := '0'; + SIGNAL nlOOiO : STD_LOGIC := '0'; + SIGNAL nlOOli : STD_LOGIC := '0'; + SIGNAL nlOOll : STD_LOGIC := '0'; + SIGNAL nlOOlO : STD_LOGIC := '0'; + SIGNAL nO : STD_LOGIC := '0'; + SIGNAL wire_nl_CLRN : STD_LOGIC; + SIGNAL wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll2157w2180w2181w2182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll2189w2190w2191w2192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlOlll2157w2180w2181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlOlll2189w2190w2191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_n0i61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOlll2157w2180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOlll2189w2190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n0i61w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlll2157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n1i2167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n1l2165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n1O2164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlll2177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nllO2175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOi2173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOl0i2187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOl0l2185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOl0O2183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOl2171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlii2193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOliO2179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlll2189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO2169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOOlO103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll137w138w139w143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlOlll137w138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOlll1321w1322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOlll137w138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOO0i869w870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOO0l1760w1761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOO0O1692w1693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOO1O939w940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOOii955w956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOOil885w886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOl0O1719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlii1254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlii1651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOliO1625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlli1560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlli1530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlll1321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlll1465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlll137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOllO1400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlOi1333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlOl1744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlOO1280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOlOO1676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO0i869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO0l1760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO0l1227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO0O1692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO0O1159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO1i1212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO1l1144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO1O939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOO1O1076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOOii1091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOOii955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOOil885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOOil1023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nilO : STD_LOGIC := '0'; + SIGNAL nlil : STD_LOGIC := '0'; + SIGNAL nlli : STD_LOGIC := '0'; + SIGNAL wire_nliO_PRN : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n100i_dataout : STD_LOGIC; + SIGNAL wire_n100l_dataout : STD_LOGIC; + SIGNAL wire_n100O_dataout : STD_LOGIC; + SIGNAL wire_n101i_dataout : STD_LOGIC; + SIGNAL wire_n101l_dataout : STD_LOGIC; + SIGNAL wire_n101O_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10ii_dataout : STD_LOGIC; + SIGNAL wire_n10il_dataout : STD_LOGIC; + SIGNAL wire_n10iO_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10li_dataout : STD_LOGIC; + SIGNAL wire_n10ll_dataout : STD_LOGIC; + SIGNAL wire_n10lO_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n10Oi_dataout : STD_LOGIC; + SIGNAL wire_n10Ol_dataout : STD_LOGIC; + SIGNAL wire_n10OO_dataout : STD_LOGIC; + SIGNAL wire_n110i_dataout : STD_LOGIC; + SIGNAL wire_n110l_dataout : STD_LOGIC; + SIGNAL wire_n110O_dataout : STD_LOGIC; + SIGNAL wire_n111i_dataout : STD_LOGIC; + SIGNAL wire_n111l_dataout : STD_LOGIC; + SIGNAL wire_n111O_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11ii_dataout : STD_LOGIC; + SIGNAL wire_n11il_dataout : STD_LOGIC; + SIGNAL wire_n11iO_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11li_dataout : STD_LOGIC; + SIGNAL wire_n11ll_dataout : STD_LOGIC; + SIGNAL wire_n11lO_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n11Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Ol_dataout : STD_LOGIC; + SIGNAL wire_n11OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iii_dataout : STD_LOGIC; + SIGNAL wire_n1iil_dataout : STD_LOGIC; + SIGNAL wire_n1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1ili_dataout : STD_LOGIC; + SIGNAL wire_n1ill_dataout : STD_LOGIC; + SIGNAL wire_n1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1lii_dataout : STD_LOGIC; + SIGNAL wire_n1lil_dataout : STD_LOGIC; + SIGNAL wire_n1liO_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lli_dataout : STD_LOGIC; + SIGNAL wire_n1lll_dataout : STD_LOGIC; + SIGNAL wire_n1llO_dataout : STD_LOGIC; + SIGNAL wire_n1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl10l_dataout : STD_LOGIC; + SIGNAL wire_nl10O_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nliii_dataout : STD_LOGIC; + SIGNAL wire_nliil_dataout : STD_LOGIC; + SIGNAL wire_nliiO_dataout : STD_LOGIC; + SIGNAL wire_nlili_dataout : STD_LOGIC; + SIGNAL wire_nlill_dataout : STD_LOGIC; + SIGNAL wire_nlilO_dataout : STD_LOGIC; + SIGNAL wire_nliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO_dataout : STD_LOGIC; + SIGNAL wire_ni_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_ni_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_ni_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n00ii_w_lg_w_lg_w_o_range106w1878w1941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00ii_w_lg_w_lg_w_o_range106w1961w1962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00ii_w_lg_w_o_range106w1878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00ii_w_lg_w_o_range106w1961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00ii_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00ii_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00ii_w_o_range106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00ii_w_o_range1798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00ii_w_o_range1824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00ii_w_o_range1839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00il_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00il_o : STD_LOGIC; + SIGNAL wire_n00il_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00iO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00iO_o : STD_LOGIC; + SIGNAL wire_n00iO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00li_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00li_o : STD_LOGIC; + SIGNAL wire_n00li_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00ll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00ll_o : STD_LOGIC; + SIGNAL wire_n00ll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00lO_o : STD_LOGIC; + SIGNAL wire_n00lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00Oi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00Oi_o : STD_LOGIC; + SIGNAL wire_n00Oi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00Ol_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00Ol_o : STD_LOGIC; + SIGNAL wire_n00Ol_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00OO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n00OO_o : STD_LOGIC; + SIGNAL wire_n00OO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i0i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0i0i_o : STD_LOGIC; + SIGNAL wire_n0i0i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i0l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0i0l_o : STD_LOGIC; + SIGNAL wire_n0i0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i0O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0i0O_o : STD_LOGIC; + SIGNAL wire_n0i0O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i1i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0i1i_o : STD_LOGIC; + SIGNAL wire_n0i1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i1l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0i1l_o : STD_LOGIC; + SIGNAL wire_n0i1l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i1O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0i1O_o : STD_LOGIC; + SIGNAL wire_n0i1O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0iii_o : STD_LOGIC; + SIGNAL wire_n0iii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iil_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0iil_o : STD_LOGIC; + SIGNAL wire_n0iil_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iiO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0iiO_o : STD_LOGIC; + SIGNAL wire_n0iiO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ili_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0ili_o : STD_LOGIC; + SIGNAL wire_n0ili_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ill_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0ill_o : STD_LOGIC; + SIGNAL wire_n0ill_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ilO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0ilO_o : STD_LOGIC; + SIGNAL wire_n0ilO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iOi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0iOi_o : STD_LOGIC; + SIGNAL wire_n0iOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iOl_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0iOl_o : STD_LOGIC; + SIGNAL wire_n0iOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iOO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0iOO_o : STD_LOGIC; + SIGNAL wire_n0iOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n000i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n000i_o : STD_LOGIC; + SIGNAL wire_n000i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n001O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n001O_o : STD_LOGIC; + SIGNAL wire_n001O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n010i_o : STD_LOGIC; + SIGNAL wire_n010i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n010O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010O_o : STD_LOGIC; + SIGNAL wire_n010O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n011i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011i_o : STD_LOGIC; + SIGNAL wire_n011i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011l_o : STD_LOGIC; + SIGNAL wire_n011l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011O_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n011O_o : STD_LOGIC; + SIGNAL wire_n011O_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n01iO_o : STD_LOGIC; + SIGNAL wire_n01iO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n01ll_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01ll_o : STD_LOGIC; + SIGNAL wire_n01ll_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01lO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01lO_o : STD_LOGIC; + SIGNAL wire_n01lO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01Oi_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01Oi_o : STD_LOGIC; + SIGNAL wire_n01Oi_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01Ol_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01Ol_o : STD_LOGIC; + SIGNAL wire_n01Ol_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1O0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O0O_o : STD_LOGIC; + SIGNAL wire_n1O0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oii_o : STD_LOGIC; + SIGNAL wire_n1Oii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oil_o : STD_LOGIC; + SIGNAL wire_n1Oil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OiO_o : STD_LOGIC; + SIGNAL wire_n1OiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oli_o : STD_LOGIC; + SIGNAL wire_n1Oli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oll_o : STD_LOGIC; + SIGNAL wire_n1Oll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OlO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OlO_o : STD_LOGIC; + SIGNAL wire_n1OlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OOi_o : STD_LOGIC; + SIGNAL wire_n1OOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOO_o : STD_LOGIC; + SIGNAL wire_niOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1i_o : STD_LOGIC; + SIGNAL wire_nl1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1l_o : STD_LOGIC; + SIGNAL wire_nl1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_nlli0i2123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlliii115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nllili85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nllilO77w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlliOl66w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlll0i60w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpma_doublewidth_tx2149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpmadwidth_tx2148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w160w161w162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w160w161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_nlli1i150w154w155w159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nlli1i150w154w155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliOli815w816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliOll745w746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliOlO675w676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliOOi538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliOOl469w470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nll10i729w730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nll11O799w800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlli1i150w154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliO0O1363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliO1l1348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliOli815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliOll745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliOlO675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliOOi607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliOOi538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliOOl469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nll10i729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nll10l1129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nll10O1197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nll11O799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nll1iO1265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlli1i150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliiOO : STD_LOGIC; + SIGNAL nlil0i : STD_LOGIC; + SIGNAL nlil0l : STD_LOGIC; + SIGNAL nlil0O : STD_LOGIC; + SIGNAL nlil1i : STD_LOGIC; + SIGNAL nlil1l : STD_LOGIC; + SIGNAL nlil1O : STD_LOGIC; + SIGNAL nlilii : STD_LOGIC; + SIGNAL nlilil : STD_LOGIC; + SIGNAL nliliO : STD_LOGIC; + SIGNAL nlilli : STD_LOGIC; + SIGNAL nlilll : STD_LOGIC; + SIGNAL nlillO : STD_LOGIC; + SIGNAL nlilOi : STD_LOGIC; + SIGNAL nlilOl : STD_LOGIC; + SIGNAL nlilOO : STD_LOGIC; + SIGNAL nliO0i : STD_LOGIC; + SIGNAL nliO0l : STD_LOGIC; + SIGNAL nliO0O : STD_LOGIC; + SIGNAL nliO1i : STD_LOGIC; + SIGNAL nliO1l : STD_LOGIC; + SIGNAL nliO1O : STD_LOGIC; + SIGNAL nliOii : STD_LOGIC; + SIGNAL nliOil : STD_LOGIC; + SIGNAL nliOiO : STD_LOGIC; + SIGNAL nliOli : STD_LOGIC; + SIGNAL nliOll : STD_LOGIC; + SIGNAL nliOlO : STD_LOGIC; + SIGNAL nliOOi : STD_LOGIC; + SIGNAL nliOOl : STD_LOGIC; + SIGNAL nliOOO : STD_LOGIC; + SIGNAL nll0ll : STD_LOGIC; + SIGNAL nll0lO : STD_LOGIC; + SIGNAL nll0Oi : STD_LOGIC; + SIGNAL nll10i : STD_LOGIC; + SIGNAL nll10l : STD_LOGIC; + SIGNAL nll10O : STD_LOGIC; + SIGNAL nll11i : STD_LOGIC; + SIGNAL nll11l : STD_LOGIC; + SIGNAL nll11O : STD_LOGIC; + SIGNAL nll1iO : STD_LOGIC; + SIGNAL nlli0i : STD_LOGIC; + SIGNAL nlli1i : STD_LOGIC; + SIGNAL nlli1l : STD_LOGIC; + SIGNAL nlliii : STD_LOGIC; + SIGNAL nllili : STD_LOGIC; + SIGNAL nllilO : STD_LOGIC; + SIGNAL nlliOl : STD_LOGIC; + SIGNAL nlliOO : STD_LOGIC; + SIGNAL nlll0i : STD_LOGIC; + SIGNAL nlll0l : STD_LOGIC; + SIGNAL nlll1O : STD_LOGIC; + SIGNAL nllllO : STD_LOGIC; + BEGIN + + wire_gnd <= '0'; + wire_w_lg_nlli0i2123w(0) <= NOT nlli0i; + wire_w_lg_nlliii115w(0) <= NOT nlliii; + wire_w_lg_nllili85w(0) <= NOT nllili; + wire_w_lg_nllilO77w(0) <= NOT nllilO; + wire_w_lg_nlliOl66w(0) <= NOT nlliOl; + wire_w_lg_nlll0i60w(0) <= NOT nlll0i; + wire_w_lg_rpma_doublewidth_tx2149w(0) <= NOT rpma_doublewidth_tx; + wire_w_lg_rpmadwidth_tx2148w(0) <= NOT rpmadwidth_tx; + wire_w_lg_soft_reset2w(0) <= NOT soft_reset; + wire_w_lg_w_lg_w160w161w162w(0) <= wire_w_lg_w160w161w(0) XOR nlOl0i; + wire_w_lg_w160w161w(0) <= wire_w160w(0) XOR nlOl0l; + wire_w160w(0) <= wire_w_lg_w_lg_w_lg_w_lg_nlli1i150w154w155w159w(0) XOR nlOl0O; + wire_w_lg_w_lg_w_lg_w_lg_nlli1i150w154w155w159w(0) <= wire_w_lg_w_lg_w_lg_nlli1i150w154w155w(0) XOR wire_nll1Ol40_w_lg_w_lg_q157w158w(0); + wire_w_lg_w_lg_w_lg_nlli1i150w154w155w(0) <= wire_w_lg_w_lg_nlli1i150w154w(0) XOR nlOlii; + wire_w_lg_w_lg_nliOli815w816w(0) <= wire_w_lg_nliOli815w(0) XOR nlOO1l; + wire_w_lg_w_lg_nliOll745w746w(0) <= wire_w_lg_nliOll745w(0) XOR nlOO1O; + wire_w_lg_w_lg_nliOlO675w676w(0) <= wire_w_lg_nliOlO675w(0) XOR nlOO0i; + wire_w_lg_w_lg_nliOOi538w539w(0) <= wire_w_lg_nliOOi538w(0) XOR nlOO1l; + wire_w_lg_w_lg_nliOOl469w470w(0) <= wire_w_lg_nliOOl469w(0) XOR nlOO1l; + wire_w_lg_w_lg_nll10i729w730w(0) <= wire_w_lg_nll10i729w(0) XOR nlOlOl; + wire_w_lg_w_lg_nll11O799w800w(0) <= wire_w_lg_nll11O799w(0) XOR nlOlOi; + wire_w_lg_w_lg_nlli1i150w154w(0) <= wire_w_lg_nlli1i150w(0) XOR wire_nll01i38_w_lg_w_lg_q152w153w(0); + wire_w_lg_nliO0O1363w(0) <= nliO0O XOR nlOO1l; + wire_w_lg_nliO1l1348w(0) <= nliO1l XOR nlOlOi; + wire_w_lg_nliOli815w(0) <= nliOli XOR nlOO1O; + wire_w_lg_nliOll745w(0) <= nliOll XOR nlOO0i; + wire_w_lg_nliOlO675w(0) <= nliOlO XOR nlOO0l; + wire_w_lg_nliOOi607w(0) <= nliOOi XOR nlOO0l; + wire_w_lg_nliOOi538w(0) <= nliOOi XOR nlOO1O; + wire_w_lg_nliOOl469w(0) <= nliOOl XOR nlOO0i; + wire_w_lg_nll10i729w(0) <= nll10i XOR nlOlOO; + wire_w_lg_nll10l1129w(0) <= nll10l XOR nlOlOi; + wire_w_lg_nll10O1197w(0) <= nll10O XOR nlOllO; + wire_w_lg_nll11O799w(0) <= nll11O XOR nlOlOl; + wire_w_lg_nll1iO1265w(0) <= nll1iO XOR nlOlll; + wire_w_lg_nlli1i150w(0) <= nlli1i XOR nlOliO; + nliiOO <= ((wire_n00ii_o(25) OR wire_n00ii_o(17)) OR wire_n00ii_o(4)); + nlil0i <= wire_n00ii_w_lg_w_o_range106w1878w(0); + nlil0l <= (((((((((wire_n00ii_o(24) OR wire_n00ii_o(2)) OR wire_n00ii_o(28)) OR wire_n00ii_o(27)) OR wire_n00ii_o(26)) OR wire_n00ii_o(11)) OR wire_n00ii_o(10)) OR wire_n00ii_o(9)) OR wire_n00ii_o(8)) OR wire_n00ii_o(1)); + nlil0O <= ((((((((((((((((wire_n00ii_o(31) OR wire_n00ii_o(30)) OR wire_n00ii_o(29)) OR wire_n00ii_o(23)) OR wire_n00ii_o(22)) OR wire_n00ii_o(21)) OR wire_n00ii_o(20)) OR wire_n00ii_o(19)) OR wire_n00ii_o(15)) OR wire_n00ii_o(14)) OR wire_n00ii_o(13)) OR wire_n00ii_o(12)) OR wire_n00ii_o(7)) OR wire_n00ii_o(6)) OR wire_n00ii_o(5)) OR wire_n00ii_o(4)) OR wire_n00ii_o(3)); + nlil1i <= (((((((((((((((wire_n00ii_o(31) OR wire_n00ii_o(30)) OR wire_n00ii_o(29)) OR wire_n00ii_o(23)) OR wire_n00ii_o(22)) OR wire_n00ii_o(21)) OR wire_n00ii_o(20)) OR wire_n00ii_o(19)) OR wire_n00ii_o(15)) OR wire_n00ii_o(14)) OR wire_n00ii_o(13)) OR wire_n00ii_o(12)) OR wire_n00ii_o(7)) OR wire_n00ii_o(6)) OR wire_n00ii_o(5)) OR wire_n00ii_o(3)); + nlil1l <= ((((((((((wire_n00ii_o(24) OR wire_n00ii_o(2)) OR wire_n00ii_o(28)) OR wire_n00ii_o(27)) OR wire_n00ii_o(26)) OR wire_n00ii_o(25)) OR wire_n00ii_o(11)) OR wire_n00ii_o(10)) OR wire_n00ii_o(9)) OR wire_n00ii_o(8)) OR wire_n00ii_o(1)); + nlil1O <= ((((((((((wire_n00ii_o(24) OR wire_n00ii_o(2)) OR wire_n00ii_o(28)) OR wire_n00ii_o(27)) OR wire_n00ii_o(26)) OR wire_n00ii_o(17)) OR wire_n00ii_o(11)) OR wire_n00ii_o(10)) OR wire_n00ii_o(9)) OR wire_n00ii_o(8)) OR wire_n00ii_o(1)); + nlilii <= (((((((((((wire_n00ii_o(24) OR wire_n00ii_o(16)) OR wire_n00ii_o(2)) OR wire_n00ii_o(28)) OR wire_n00ii_o(27)) OR wire_n00ii_o(26)) OR wire_n00ii_o(18)) OR wire_n00ii_o(11)) OR wire_n00ii_o(10)) OR wire_n00ii_o(9)) OR wire_n00ii_o(8)) OR wire_n00ii_o(1)); + nlilil <= (((((((((((((((((wire_n00ii_o(31) OR wire_n00ii_o(30)) OR wire_n00ii_o(29)) OR wire_n00ii_o(23)) OR wire_n00ii_o(22)) OR wire_n00ii_o(21)) OR wire_n00ii_o(20)) OR wire_n00ii_o(19)) OR wire_n00ii_o(17)) OR wire_n00ii_o(15)) OR wire_n00ii_o(14)) OR wire_n00ii_o(13)) OR wire_n00ii_o(12)) OR wire_n00ii_o(7)) OR wire_n00ii_o(6)) OR wire_n00ii_o(5)) OR wire_n00ii_o(4)) OR wire_n00ii_o(3)); + nliliO <= (nlOlll XOR nlOl0O); + nlilli <= (nlOllO XOR nlOlii); + nlilll <= (nlOlOi XOR nlOlil); + nlillO <= (nlOlOl XOR nlOliO); + nlilOi <= (nlOlOO XOR nlOlli); + nlilOl <= (nlOO1i XOR nlOlll); + nlilOO <= (nlOO1l XOR nlOllO); + nliO0i <= (nlOO0O XOR nlOO1i); + nliO0l <= (nlOOii XOR nlOO1l); + nliO0O <= (nlOOil XOR nlOO1O); + nliO1i <= (nlOO1O XOR nlOlOi); + nliO1l <= (nlOO0i XOR nlOlOl); + nliO1O <= (nlOO0l XOR nlOlOO); + nliOii <= (nlOOiO XOR nlOO0i); + nliOil <= (nlOOli XOR nlOO0l); + nliOiO <= (nlOOll XOR nlOO0O); + nliOli <= (nlOO0l XOR nlOO0i); + nliOll <= (nlOO0O XOR nlOO0l); + nliOlO <= (nlOOii XOR nlOO0O); + nliOOi <= (nliOOl XOR nlOO0O); + nliOOl <= (nlOOil XOR nlOOii); + nliOOO <= (nlOO1O XOR nlOO1l); + nll0ll <= (nlOlil XOR nlOlii); + nll0lO <= (nlOliO XOR nlOlil); + nll0Oi <= ((nlOlli XOR nlOliO) XOR (NOT (nll0Ol28 XOR nll0Ol27))); + nll10i <= (nlOO1l XOR nlOO1i); + nll10l <= (nlOliO XOR nlOl0O); + nll10O <= ((nlOlil XOR nlOl0l) XOR (NOT (nll1ii46 XOR nll1ii45))); + nll11i <= (nlOO0i XOR nlOO1O); + nll11l <= (nlOO0i XOR nlOO1l); + nll11O <= (nlOO1i XOR nlOlOO); + nll1iO <= ((nlOlii XOR nlOl0i) XOR (NOT (nll1li44 XOR nll1li43))); + nlli0i <= (((wire_n00ii_o(24) OR wire_n00ii_o(16)) OR wire_n00ii_o(2)) OR (NOT (nlli0l24 XOR nlli0l23))); + nlli1i <= (nlOlll XOR nlOlli); + nlli1l <= (wire_niOl_dataout OR wire_niOi_dataout); + nlliii <= (nili AND wire_nl_w_lg_nlOOlO103w(0)); + nllili <= (((((((wire_nl_w_lg_n1O2164w(0) AND wire_nl_w_lg_n1l2165w(0)) AND wire_nl_w_lg_n1i2167w(0)) AND wire_nl_w_lg_nlOO2169w(0)) AND wire_nl_w_lg_nlOl2171w(0)) AND wire_nl_w_lg_nlOi2173w(0)) AND wire_nl_w_lg_nllO2175w(0)) AND nlll); + nllilO <= ((((((wire_nl_w_lg_nlOlll2157w(0) AND nlOliO) AND nlOlil) AND nlOlii) AND nlOl0O) AND nlOl0l) AND nlOl0i); + nlliOl <= ((((wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll2189w2190w2191w2192w(0) AND wire_nl_w_lg_nlOlii2193w(0)) AND wire_nl_w_lg_nlOl0O2183w(0)) AND wire_nl_w_lg_nlOl0l2185w(0)) AND wire_nl_w_lg_nlOl0i2187w(0)); + nlliOO <= (wire_nl_w_lg_w_lg_n0i61w62w(0) AND (nlll1i14 XOR nlll1i13)); + nlll0i <= (((((((wire_nl_w_lg_n1O2164w(0) AND wire_nl_w_lg_n1l2165w(0)) AND wire_nl_w_lg_n1i2167w(0)) AND wire_nl_w_lg_nlOO2169w(0)) AND wire_nl_w_lg_nlOl2171w(0)) AND wire_nl_w_lg_nlOi2173w(0)) AND wire_nl_w_lg_nllO2175w(0)) AND wire_nl_w_lg_nlll2177w(0)); + nlll0l <= ((((wire_w_lg_rpmadwidth_tx2148w(0) AND wire_w_lg_rpma_doublewidth_tx2149w(0)) AND (NOT rprbs_sel(0))) AND (NOT rprbs_sel(1))) AND (NOT rprbs_sel(2))); + nlll1O <= (((wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll2157w2180w2181w2182w(0) AND wire_nl_w_lg_nlOl0O2183w(0)) AND wire_nl_w_lg_nlOl0l2185w(0)) AND wire_nl_w_lg_nlOl0i2187w(0)); + nllllO <= '1'; + prbs_out <= ( nlOl1O & nlOl1l & nlOl1i & nlOiOO & nlOiOl & nlOiOi & nlOilO & nlOill & nlOili & nlOiiO & nlOiil & nlOiii & nlOi0O & nlOi0l & nlOi0i & nlOi1O & nlOi1l & nlOi1i & nlO0OO & nlO0Ol); + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll00l33 <= nll00l34; + END IF; + if (now = 0 ns) then + nll00l33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll00l34 <= nll00l33; + END IF; + END PROCESS; + wire_nll00l34_w_lg_w_lg_q141w142w(0) <= NOT wire_nll00l34_w_lg_q141w(0); + wire_nll00l34_w_lg_q141w(0) <= nll00l34 XOR nll00l33; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll01i37 <= nll01i38; + END IF; + if (now = 0 ns) then + nll01i37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll01i38 <= nll01i37; + END IF; + END PROCESS; + wire_nll01i38_w_lg_w_lg_q152w153w(0) <= NOT wire_nll01i38_w_lg_q152w(0); + wire_nll01i38_w_lg_q152w(0) <= nll01i38 XOR nll01i37; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll01O35 <= nll01O36; + END IF; + if (now = 0 ns) then + nll01O35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll01O36 <= nll01O35; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll0ii31 <= nll0ii32; + END IF; + if (now = 0 ns) then + nll0ii31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll0ii32 <= nll0ii31; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll0iO29 <= nll0iO30; + END IF; + if (now = 0 ns) then + nll0iO29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll0iO30 <= nll0iO29; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll0Ol27 <= nll0Ol28; + END IF; + if (now = 0 ns) then + nll0Ol27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll0Ol28 <= nll0Ol27; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1ii45 <= nll1ii46; + END IF; + if (now = 0 ns) then + nll1ii45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1ii46 <= nll1ii45; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1li43 <= nll1li44; + END IF; + if (now = 0 ns) then + nll1li43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1li44 <= nll1li43; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1lO41 <= nll1lO42; + END IF; + if (now = 0 ns) then + nll1lO41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1lO42 <= nll1lO41; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1Ol39 <= nll1Ol40; + END IF; + if (now = 0 ns) then + nll1Ol39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nll1Ol40 <= nll1Ol39; + END IF; + END PROCESS; + wire_nll1Ol40_w_lg_w_lg_q157w158w(0) <= NOT wire_nll1Ol40_w_lg_q157w(0); + wire_nll1Ol40_w_lg_q157w(0) <= nll1Ol40 XOR nll1Ol39; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlli0l23 <= nlli0l24; + END IF; + if (now = 0 ns) then + nlli0l23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlli0l24 <= nlli0l23; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlli1O25 <= nlli1O26; + END IF; + if (now = 0 ns) then + nlli1O25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlli1O26 <= nlli1O25; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlliil21 <= nlliil22; + END IF; + if (now = 0 ns) then + nlliil21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlliil22 <= nlliil21; + END IF; + END PROCESS; + wire_nlliil22_w_lg_w_lg_q93w94w(0) <= wire_nlliil22_w_lg_q93w(0) AND nlil; + wire_nlliil22_w_lg_q93w(0) <= nlliil22 XOR nlliil21; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlliiO19 <= nlliiO20; + END IF; + if (now = 0 ns) then + nlliiO19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlliiO20 <= nlliiO19; + END IF; + END PROCESS; + wire_nlliiO20_w_lg_w_lg_q88w89w(0) <= wire_nlliiO20_w_lg_q88w(0) AND nlliOO; + wire_nlliiO20_w_lg_q88w(0) <= nlliiO20 XOR nlliiO19; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nllill17 <= nllill18; + END IF; + if (now = 0 ns) then + nllill17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nllill18 <= nllill17; + END IF; + END PROCESS; + wire_nllill18_w_lg_w_lg_q79w80w(0) <= wire_nllill18_w_lg_q79w(0) AND nlil; + wire_nllill18_w_lg_q79w(0) <= nllill18 XOR nllill17; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlliOi15 <= nlliOi16; + END IF; + if (now = 0 ns) then + nlliOi15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlliOi16 <= nlliOi15; + END IF; + END PROCESS; + wire_nlliOi16_w_lg_w_lg_q69w70w(0) <= wire_nlliOi16_w_lg_q69w(0) AND nilO; + wire_nlliOi16_w_lg_q69w(0) <= nlliOi16 XOR nlliOi15; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlll0O11 <= nlll0O12; + END IF; + if (now = 0 ns) then + nlll0O11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlll0O12 <= nlll0O11; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlll1i13 <= nlll1i14; + END IF; + if (now = 0 ns) then + nlll1i13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlll1i14 <= nlll1i13; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllil10 <= nlllil9; + END IF; + END PROCESS; + wire_nlllil10_w_lg_w_lg_q20w21w(0) <= wire_nlllil10_w_lg_q20w(0) AND n1O; + wire_nlllil10_w_lg_q20w(0) <= nlllil10 XOR nlllil9; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllil9 <= nlllil10; + END IF; + if (now = 0 ns) then + nlllil9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nllliO7 <= nllliO8; + END IF; + if (now = 0 ns) then + nllliO7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nllliO8 <= nllliO7; + END IF; + END PROCESS; + wire_nllliO8_w_lg_w_lg_q17w18w(0) <= wire_nllliO8_w_lg_q17w(0) AND n1l; + wire_nllliO8_w_lg_q17w(0) <= nllliO8 XOR nllliO7; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllli5 <= nlllli6; + END IF; + if (now = 0 ns) then + nlllli5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllli6 <= nlllli5; + END IF; + END PROCESS; + wire_nlllli6_w_lg_w_lg_q12w13w(0) <= wire_nlllli6_w_lg_q12w(0) AND nlOl; + wire_nlllli6_w_lg_q12w(0) <= nlllli6 XOR nlllli5; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllll3 <= nlllll4; + END IF; + if (now = 0 ns) then + nlllll3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllll4 <= nlllll3; + END IF; + END PROCESS; + wire_nlllll4_w_lg_w_lg_q7w8w(0) <= wire_nlllll4_w_lg_q7w(0) AND nlll; + wire_nlllll4_w_lg_q7w(0) <= nlllll4 XOR nlllll3; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllOl1 <= nlllOl2; + END IF; + if (now = 0 ns) then + nlllOl1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nlllOl2 <= nlllOl1; + END IF; + END PROCESS; + PROCESS (tx_clk, wire_ni0l_PRN, soft_reset) + BEGIN + IF (wire_ni0l_PRN = '0') THEN + ni0O <= '1'; + nlO0Ol <= '1'; + nlO0OO <= '1'; + nlOi0i <= '1'; + nlOi0l <= '1'; + nlOi0O <= '1'; + nlOi1i <= '1'; + nlOi1l <= '1'; + nlOi1O <= '1'; + nlOiii <= '1'; + nlOiil <= '1'; + nlOiiO <= '1'; + nlOili <= '1'; + nlOill <= '1'; + nlOilO <= '1'; + nlOiOi <= '1'; + nlOiOl <= '1'; + nlOiOO <= '1'; + nlOl1i <= '1'; + nlOl1l <= '1'; + nlOl1O <= '1'; + ELSIF (soft_reset = '1') THEN + ni0O <= '0'; + nlO0Ol <= '0'; + nlO0OO <= '0'; + nlOi0i <= '0'; + nlOi0l <= '0'; + nlOi0O <= '0'; + nlOi1i <= '0'; + nlOi1l <= '0'; + nlOi1O <= '0'; + nlOiii <= '0'; + nlOiil <= '0'; + nlOiiO <= '0'; + nlOili <= '0'; + nlOill <= '0'; + nlOilO <= '0'; + nlOiOi <= '0'; + nlOiOl <= '0'; + nlOiOO <= '0'; + nlOl1i <= '0'; + nlOl1l <= '0'; + nlOl1O <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (nlliii = '0') THEN + ni0O <= wire_n100O_dataout; + nlO0Ol <= wire_n10ii_dataout; + nlO0OO <= wire_n10il_dataout; + nlOi0i <= wire_n10lO_dataout; + nlOi0l <= wire_n10Oi_dataout; + nlOi0O <= wire_n10Ol_dataout; + nlOi1i <= wire_n10iO_dataout; + nlOi1l <= wire_n10li_dataout; + nlOi1O <= wire_n10ll_dataout; + nlOiii <= wire_n10OO_dataout; + nlOiil <= wire_n1i1i_dataout; + nlOiiO <= wire_n1i1l_dataout; + nlOili <= wire_n1i1O_dataout; + nlOill <= wire_n1i0i_dataout; + nlOilO <= wire_n1i0l_dataout; + nlOiOi <= wire_n1i0O_dataout; + nlOiOl <= wire_n1iii_dataout; + nlOiOO <= wire_n1iil_dataout; + nlOl1i <= wire_n1iiO_dataout; + nlOl1l <= wire_n1ili_dataout; + nlOl1O <= wire_n1ill_dataout; + END IF; + END IF; + END PROCESS; + wire_ni0l_PRN <= (nlli1O26 XOR nlli1O25); + wire_ni0l_w_lg_ni0O182w(0) <= NOT ni0O; + PROCESS (tx_clk, wire_nl_CLRN) + BEGIN + IF (wire_nl_CLRN = '0') THEN + n0i <= '0'; + n1i <= '0'; + n1l <= '0'; + n1O <= '0'; + nili <= '0'; + nill <= '0'; + nlll <= '0'; + nllO <= '0'; + nlOi <= '0'; + nlOl <= '0'; + nlOl0i <= '0'; + nlOl0l <= '0'; + nlOl0O <= '0'; + nlOlii <= '0'; + nlOlil <= '0'; + nlOliO <= '0'; + nlOlli <= '0'; + nlOlll <= '0'; + nlOllO <= '0'; + nlOlOi <= '0'; + nlOlOl <= '0'; + nlOlOO <= '0'; + nlOO <= '0'; + nlOO0i <= '0'; + nlOO0l <= '0'; + nlOO0O <= '0'; + nlOO1i <= '0'; + nlOO1l <= '0'; + nlOO1O <= '0'; + nlOOii <= '0'; + nlOOil <= '0'; + nlOOiO <= '0'; + nlOOli <= '0'; + nlOOll <= '0'; + nlOOlO <= '0'; + nO <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + n0i <= nO; + n1i <= wire_nli_dataout; + n1l <= wire_nll_dataout; + n1O <= wire_nlO_dataout; + nili <= nill; + nill <= rprbs_en_tx; + nlll <= wire_n0l_dataout; + nllO <= wire_n0O_dataout; + nlOi <= wire_nii_dataout; + nlOl <= wire_nil_dataout; + nlOl0i <= wire_nlOOOi_dataout; + nlOl0l <= wire_nlOOOl_dataout; + nlOl0O <= wire_nlOOOO_dataout; + nlOlii <= wire_n111i_dataout; + nlOlil <= wire_n111l_dataout; + nlOliO <= wire_n111O_dataout; + nlOlli <= wire_n110i_dataout; + nlOlll <= wire_n110l_dataout; + nlOllO <= wire_n110O_dataout; + nlOlOi <= wire_n11ii_dataout; + nlOlOl <= wire_n11il_dataout; + nlOlOO <= wire_n11iO_dataout; + nlOO <= wire_niO_dataout; + nlOO0i <= wire_n11Oi_dataout; + nlOO0l <= wire_n11Ol_dataout; + nlOO0O <= wire_n11OO_dataout; + nlOO1i <= wire_n11li_dataout; + nlOO1l <= wire_n11ll_dataout; + nlOO1O <= wire_n11lO_dataout; + nlOOii <= wire_n101i_dataout; + nlOOil <= wire_n101l_dataout; + nlOOiO <= wire_n101O_dataout; + nlOOli <= wire_n100i_dataout; + nlOOll <= wire_n100l_dataout; + nlOOlO <= nili; + nO <= cid_en; + END IF; + END PROCESS; + wire_nl_CLRN <= ((nlllOl2 XOR nlllOl1) AND wire_w_lg_soft_reset2w(0)); + wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll2157w2180w2181w2182w(0) <= wire_nl_w_lg_w_lg_w_lg_nlOlll2157w2180w2181w(0) AND nlOlii; + wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll2189w2190w2191w2192w(0) <= wire_nl_w_lg_w_lg_w_lg_nlOlll2189w2190w2191w(0) AND nlOlil; + wire_nl_w_lg_w_lg_w_lg_nlOlll2157w2180w2181w(0) <= wire_nl_w_lg_w_lg_nlOlll2157w2180w(0) AND nlOlil; + wire_nl_w_lg_w_lg_w_lg_nlOlll2189w2190w2191w(0) <= wire_nl_w_lg_w_lg_nlOlll2189w2190w(0) AND wire_nl_w_lg_nlOliO2179w(0); + wire_nl_w_lg_w_lg_n0i61w62w(0) <= wire_nl_w_lg_n0i61w(0) AND nlll1O; + wire_nl_w_lg_w_lg_nlOlll2157w2180w(0) <= wire_nl_w_lg_nlOlll2157w(0) AND wire_nl_w_lg_nlOliO2179w(0); + wire_nl_w_lg_w_lg_nlOlll2189w2190w(0) <= wire_nl_w_lg_nlOlll2189w(0) AND nlOlli; + wire_nl_w_lg_n0i61w(0) <= n0i AND wire_w_lg_nlll0i60w(0); + wire_nl_w_lg_nlOlll2157w(0) <= nlOlll AND nlOlli; + wire_nl_w_lg_n1i2167w(0) <= NOT n1i; + wire_nl_w_lg_n1l2165w(0) <= NOT n1l; + wire_nl_w_lg_n1O2164w(0) <= NOT n1O; + wire_nl_w_lg_nlll2177w(0) <= NOT nlll; + wire_nl_w_lg_nllO2175w(0) <= NOT nllO; + wire_nl_w_lg_nlOi2173w(0) <= NOT nlOi; + wire_nl_w_lg_nlOl0i2187w(0) <= NOT nlOl0i; + wire_nl_w_lg_nlOl0l2185w(0) <= NOT nlOl0l; + wire_nl_w_lg_nlOl0O2183w(0) <= NOT nlOl0O; + wire_nl_w_lg_nlOl2171w(0) <= NOT nlOl; + wire_nl_w_lg_nlOlii2193w(0) <= NOT nlOlii; + wire_nl_w_lg_nlOliO2179w(0) <= NOT nlOliO; + wire_nl_w_lg_nlOlll2189w(0) <= NOT nlOlll; + wire_nl_w_lg_nlOO2169w(0) <= NOT nlOO; + wire_nl_w_lg_nlOOlO103w(0) <= NOT nlOOlO; + wire_nl_w_lg_w144w145w(0) <= wire_nl_w144w(0) XOR nlOl0i; + wire_nl_w144w(0) <= wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll137w138w139w143w(0) XOR nlOl0O; + wire_nl_w_lg_w_lg_w_lg_w_lg_nlOlll137w138w139w143w(0) <= wire_nl_w_lg_w_lg_w_lg_nlOlll137w138w139w(0) XOR wire_nll00l34_w_lg_w_lg_q141w142w(0); + wire_nl_w_lg_w_lg_w_lg_nlOlll137w138w139w(0) <= wire_nl_w_lg_w_lg_nlOlll137w138w(0) XOR nlOlii; + wire_nl_w_lg_w_lg_nlOlll1321w1322w(0) <= wire_nl_w_lg_nlOlll1321w(0) XOR nlOl0O; + wire_nl_w_lg_w_lg_nlOlll137w138w(0) <= wire_nl_w_lg_nlOlll137w(0) XOR nlOlil; + wire_nl_w_lg_w_lg_nlOO0i869w870w(0) <= wire_nl_w_lg_nlOO0i869w(0) XOR nlOlOl; + wire_nl_w_lg_w_lg_nlOO0l1760w1761w(0) <= wire_nl_w_lg_nlOO0l1760w(0) XOR nlOOli; + wire_nl_w_lg_w_lg_nlOO0O1692w1693w(0) <= wire_nl_w_lg_nlOO0O1692w(0) XOR nlOOll; + wire_nl_w_lg_w_lg_nlOO1O939w940w(0) <= wire_nl_w_lg_nlOO1O939w(0) XOR nlOlOi; + wire_nl_w_lg_w_lg_nlOOii955w956w(0) <= wire_nl_w_lg_nlOOii955w(0) XOR nlOO1l; + wire_nl_w_lg_w_lg_nlOOil885w886w(0) <= wire_nl_w_lg_nlOOil885w(0) XOR nlOO1O; + wire_nl_w_lg_nlOl0O1719w(0) <= nlOl0O XOR nlOl0l; + wire_nl_w_lg_nlOlii1254w(0) <= nlOlii XOR nlOl0l; + wire_nl_w_lg_nlOlii1651w(0) <= nlOlii XOR nlOl0O; + wire_nl_w_lg_nlOliO1625w(0) <= nlOliO XOR nlOl0i; + wire_nl_w_lg_nlOlli1560w(0) <= nlOlli XOR nlOl0l; + wire_nl_w_lg_nlOlli1530w(0) <= nlOlli XOR nlOlii; + wire_nl_w_lg_nlOlll1321w(0) <= nlOlll XOR nlOl0l; + wire_nl_w_lg_nlOlll1465w(0) <= nlOlll XOR nlOlil; + wire_nl_w_lg_nlOlll137w(0) <= nlOlll XOR nlOliO; + wire_nl_w_lg_nlOllO1400w(0) <= nlOllO XOR nlOliO; + wire_nl_w_lg_nlOlOi1333w(0) <= nlOlOi XOR nlOlli; + wire_nl_w_lg_nlOlOl1744w(0) <= nlOlOl XOR nlOlOi; + wire_nl_w_lg_nlOlOO1280w(0) <= nlOlOO XOR nlOlOi; + wire_nl_w_lg_nlOlOO1676w(0) <= nlOlOO XOR nlOlOl; + wire_nl_w_lg_nlOO0i869w(0) <= nlOO0i XOR nlOlOO; + wire_nl_w_lg_nlOO0l1760w(0) <= nlOO0l XOR nlOlii; + wire_nl_w_lg_nlOO0l1227w(0) <= nlOO0l XOR nlOO1O; + wire_nl_w_lg_nlOO0O1692w(0) <= nlOO0O XOR nlOlil; + wire_nl_w_lg_nlOO0O1159w(0) <= nlOO0O XOR nlOO0i; + wire_nl_w_lg_nlOO1i1212w(0) <= nlOO1i XOR nlOlOl; + wire_nl_w_lg_nlOO1l1144w(0) <= nlOO1l XOR nlOlOO; + wire_nl_w_lg_nlOO1O939w(0) <= nlOO1O XOR nlOlOl; + wire_nl_w_lg_nlOO1O1076w(0) <= nlOO1O XOR nlOO1i; + wire_nl_w_lg_nlOOii1091w(0) <= nlOOii XOR nlOO0l; + wire_nl_w_lg_nlOOii955w(0) <= nlOOii XOR nlOO1O; + wire_nl_w_lg_nlOOil885w(0) <= nlOOil XOR nlOO0i; + wire_nl_w_lg_nlOOil1023w(0) <= nlOOil XOR nlOO0O; + PROCESS (tx_clk, soft_reset) + BEGIN + IF (soft_reset = '1') THEN + nilO <= '0'; + nlil <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (nlll0l = '1') THEN + nilO <= wire_niOO_o; + nlil <= wire_nl1i_o; + END IF; + END IF; + END PROCESS; + PROCESS (tx_clk, wire_nliO_PRN) + BEGIN + IF (wire_nliO_PRN = '0') THEN + nlli <= '1'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (nlll0l = '1') THEN + nlli <= wire_nl1l_o; + END IF; + END IF; + if (now = 0 ns) then + nlli <= '1' after 1 ps; + end if; + END PROCESS; + wire_nliO_PRN <= ((nlll0O12 XOR nlll0O11) AND wire_w_lg_soft_reset2w(0)); + wire_n0l_dataout <= wire_ni_o(1) WHEN wire_niOi_dataout = '1' ELSE rcid_len(0); + wire_n0O_dataout <= wire_ni_o(2) WHEN wire_niOi_dataout = '1' ELSE rcid_len(1); + wire_n100i_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1O1O_dataout; + wire_n100l_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1O0i_dataout; + wire_n100O_dataout <= wire_n1O0l_dataout WHEN nlOOlO = '1' ELSE ni0O; + wire_n101i_dataout <= (NOT (wire_n00ii_o(16) OR wire_n00ii_o(2))) WHEN nlliii = '1' ELSE wire_n1lOO_dataout; + wire_n101l_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1O1i_dataout; + wire_n101O_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1O1l_dataout; + wire_n10i_dataout <= nlOO0i AND nlli1l; + wire_n10ii_dataout <= wire_n1O0O_o WHEN nlOOlO = '1' ELSE nlO0Ol; + wire_n10il_dataout <= wire_n1Oii_o WHEN nlOOlO = '1' ELSE nlO0OO; + wire_n10iO_dataout <= wire_n1Oil_o WHEN nlOOlO = '1' ELSE nlOi1i; + wire_n10l_dataout <= nlOO0l AND nlli1l; + wire_n10li_dataout <= wire_n1OiO_o WHEN nlOOlO = '1' ELSE nlOi1l; + wire_n10ll_dataout <= wire_n1Oli_o WHEN nlOOlO = '1' ELSE nlOi1O; + wire_n10lO_dataout <= wire_n1Oll_o WHEN nlOOlO = '1' ELSE nlOi0i; + wire_n10O_dataout <= nlOO0O AND nlli1l; + wire_n10Oi_dataout <= wire_n1OlO_o WHEN nlOOlO = '1' ELSE nlOi0l; + wire_n10Ol_dataout <= wire_n1OOi_o WHEN nlOOlO = '1' ELSE nlOi0O; + wire_n10OO_dataout <= wire_n011i_o WHEN nlOOlO = '1' ELSE nlOiii; + wire_n110i_dataout <= wire_n1l1O_dataout OR nlliii; + wire_n110l_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1l0i_dataout; + wire_n110O_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1l0l_dataout; + wire_n111i_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1iOO_dataout; + wire_n111l_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1l1i_dataout; + wire_n111O_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1l1l_dataout; + wire_n11i_dataout <= nlOO1i AND nlli1l; + wire_n11ii_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1l0O_dataout; + wire_n11il_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1lii_dataout; + wire_n11iO_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1lil_dataout; + wire_n11l_dataout <= nlOO1l AND nlli1l; + wire_n11li_dataout <= (NOT wire_n00ii_o(2)) WHEN nlliii = '1' ELSE wire_n1liO_dataout; + wire_n11ll_dataout <= (NOT wire_n00ii_o(2)) WHEN nlliii = '1' ELSE wire_n1lli_dataout; + wire_n11lO_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1lll_dataout; + wire_n11O_dataout <= nlOO1O AND nlli1l; + wire_n11Oi_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1llO_dataout; + wire_n11Ol_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1lOi_dataout; + wire_n11OO_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1lOl_dataout; + wire_n1i0i_dataout <= wire_n010O_o WHEN nlOOlO = '1' ELSE nlOill; + wire_n1i0l_dataout <= wire_n01iO_o WHEN nlOOlO = '1' ELSE nlOilO; + wire_n1i0O_dataout <= wire_n01ll_o WHEN nlOOlO = '1' ELSE nlOiOi; + wire_n1i1i_dataout <= wire_n011l_o WHEN nlOOlO = '1' ELSE nlOiil; + wire_n1i1l_dataout <= wire_n011O_o WHEN nlOOlO = '1' ELSE nlOiiO; + wire_n1i1O_dataout <= wire_n010i_o WHEN nlOOlO = '1' ELSE nlOili; + wire_n1ii_dataout <= nlOOii AND nlli1l; + wire_n1iii_dataout <= wire_n01lO_o WHEN nlOOlO = '1' ELSE nlOiOl; + wire_n1iil_dataout <= wire_n01Oi_o WHEN nlOOlO = '1' ELSE nlOiOO; + wire_n1iiO_dataout <= wire_n01Ol_o WHEN nlOOlO = '1' ELSE nlOl1i; + wire_n1il_dataout <= nlOOil AND nlli1l; + wire_n1ili_dataout <= wire_n001O_o WHEN nlOOlO = '1' ELSE nlOl1l; + wire_n1ill_dataout <= wire_n000i_o WHEN nlOOlO = '1' ELSE nlOl1O; + wire_n1ilO_dataout <= wire_n00il_o WHEN nlOOlO = '1' ELSE nlOl0i; + wire_n1iO_dataout <= nlOOiO AND nlli1l; + wire_n1iOi_dataout <= wire_n00iO_o WHEN nlOOlO = '1' ELSE nlOl0l; + wire_n1iOl_dataout <= wire_n00li_o WHEN nlOOlO = '1' ELSE nlOl0O; + wire_n1iOO_dataout <= wire_n00ll_o WHEN nlOOlO = '1' ELSE nlOlii; + wire_n1l0i_dataout <= wire_n00OO_o WHEN nlOOlO = '1' ELSE nlOlll; + wire_n1l0l_dataout <= wire_n0i1i_o WHEN nlOOlO = '1' ELSE nlOllO; + wire_n1l0O_dataout <= wire_n0i1l_o WHEN nlOOlO = '1' ELSE nlOlOi; + wire_n1l1i_dataout <= wire_n00lO_o WHEN nlOOlO = '1' ELSE nlOlil; + wire_n1l1l_dataout <= wire_n00Oi_o WHEN nlOOlO = '1' ELSE nlOliO; + wire_n1l1O_dataout <= wire_n00Ol_o WHEN nlOOlO = '1' ELSE nlOlli; + wire_n1li_dataout <= nlOOli AND nlli1l; + wire_n1lii_dataout <= wire_n0i1O_o WHEN nlOOlO = '1' ELSE nlOlOl; + wire_n1lil_dataout <= wire_n0i0i_o WHEN nlOOlO = '1' ELSE nlOlOO; + wire_n1liO_dataout <= wire_n0i0l_o WHEN nlOOlO = '1' ELSE nlOO1i; + wire_n1ll_dataout <= nlOOll AND nlli1l; + wire_n1lli_dataout <= wire_n0i0O_o WHEN nlOOlO = '1' ELSE nlOO1l; + wire_n1lll_dataout <= wire_n0iii_o WHEN nlOOlO = '1' ELSE nlOO1O; + wire_n1llO_dataout <= wire_n0iil_o WHEN nlOOlO = '1' ELSE nlOO0i; + wire_n1lOi_dataout <= wire_n0iiO_o WHEN nlOOlO = '1' ELSE nlOO0l; + wire_n1lOl_dataout <= wire_n0ili_o WHEN nlOOlO = '1' ELSE nlOO0O; + wire_n1lOO_dataout <= wire_n0ill_o WHEN nlOOlO = '1' ELSE nlOOii; + wire_n1O0i_dataout <= wire_n0iOO_o WHEN nlOOlO = '1' ELSE nlOOll; + wire_n1O0l_dataout <= wire_ni0l_w_lg_ni0O182w(0) WHEN wire_n00ii_o(11) = '1' ELSE ni0O; + wire_n1O1i_dataout <= wire_n0ilO_o WHEN nlOOlO = '1' ELSE nlOOil; + wire_n1O1l_dataout <= wire_n0iOi_o WHEN nlOOlO = '1' ELSE nlOOiO; + wire_n1O1O_dataout <= wire_n0iOl_o WHEN nlOOlO = '1' ELSE nlOOli; + wire_nii_dataout <= wire_ni_o(3) WHEN wire_niOi_dataout = '1' ELSE rcid_len(2); + wire_niiil_dataout <= wire_niO1i_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_niiiO_dataout <= wire_niO1l_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_niili_dataout <= wire_niO1O_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_niill_dataout <= wire_niO0i_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_niilO_dataout <= wire_niO0l_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_niiOi_dataout <= wire_niO0O_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_niiOl_dataout <= wire_niOii_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_niiOO_dataout <= wire_niOil_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nil_dataout <= wire_ni_o(4) WHEN wire_niOi_dataout = '1' ELSE rcid_len(3); + wire_nil0i_dataout <= wire_niOlO_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nil0l_dataout <= wire_niOOi_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nil0O_dataout <= wire_niOOl_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nil1i_dataout <= wire_niOiO_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_nil1l_dataout <= wire_niOli_dataout OR wire_ni0l_w_lg_ni0O182w(0); + wire_nil1O_dataout <= wire_niOll_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nilii_dataout <= wire_niOOO_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nilil_dataout <= wire_nl11i_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_niliO_dataout <= wire_nl11l_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nilli_dataout <= wire_nl11O_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nilll_dataout <= wire_nl10i_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nillO_dataout <= wire_nl10l_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nilOi_dataout <= wire_nl10O_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nilOl_dataout <= wire_nl1ii_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_nilOO_dataout <= wire_nl1il_dataout AND NOT(wire_ni0l_w_lg_ni0O182w(0)); + wire_niO_dataout <= wire_ni_o(5) WHEN wire_niOi_dataout = '1' ELSE rcid_len(4); + wire_niO0i_dataout <= nlOlii AND NOT(ni0O); + wire_niO0l_dataout <= nlOlil AND NOT(ni0O); + wire_niO0O_dataout <= nlOliO OR ni0O; + wire_niO1i_dataout <= nlOl0i AND NOT(ni0O); + wire_niO1l_dataout <= nlOl0l AND NOT(ni0O); + wire_niO1O_dataout <= nlOl0O AND NOT(ni0O); + wire_niOi_dataout <= nlil AND nlll0l; + wire_niOii_dataout <= nlOlli AND NOT(ni0O); + wire_niOil_dataout <= nlOlll OR ni0O; + wire_niOiO_dataout <= nlOllO AND NOT(ni0O); + wire_niOl_dataout <= nlli AND nlll0l; + wire_niOli_dataout <= nlOlOi AND NOT(ni0O); + wire_niOll_dataout <= nlOlOl AND NOT(ni0O); + wire_niOlO_dataout <= nlOlOO AND NOT(ni0O); + wire_niOOi_dataout <= nlOO1i AND NOT(ni0O); + wire_niOOl_dataout <= nlOO1l AND NOT(ni0O); + wire_niOOO_dataout <= nlOO1O AND NOT(ni0O); + wire_nl0i_dataout <= nlliOl AND NOT(nlliOO); + wire_nl0iO_dataout <= wire_nliOl_dataout AND NOT(wire_niOl_dataout); + wire_nl0li_dataout <= wire_nliOO_dataout OR wire_niOl_dataout; + wire_nl0ll_dataout <= wire_nll1i_dataout AND NOT(wire_niOl_dataout); + wire_nl0lO_dataout <= wire_nll1l_dataout OR wire_niOl_dataout; + wire_nl0Oi_dataout <= wire_nll1O_dataout OR wire_niOl_dataout; + wire_nl0Ol_dataout <= wire_nll0i_dataout AND NOT(wire_niOl_dataout); + wire_nl0OO_dataout <= wire_nll0l_dataout OR wire_niOl_dataout; + wire_nl10i_dataout <= nlOOii AND NOT(ni0O); + wire_nl10l_dataout <= nlOOil AND NOT(ni0O); + wire_nl10O_dataout <= nlOOiO AND NOT(ni0O); + wire_nl11i_dataout <= nlOO0i AND NOT(ni0O); + wire_nl11l_dataout <= nlOO0l AND NOT(ni0O); + wire_nl11O_dataout <= nlOO0O AND NOT(ni0O); + wire_nl1ii_dataout <= nlOOli AND NOT(ni0O); + wire_nl1il_dataout <= nlOOll AND NOT(ni0O); + wire_nl1O_dataout <= wire_w_lg_nlliOl66w(0) AND NOT(nlliOO); + wire_nli_dataout <= wire_ni_o(6) WHEN wire_niOi_dataout = '1' ELSE rcid_len(5); + wire_nli0i_dataout <= wire_nlliO_dataout AND NOT(wire_niOl_dataout); + wire_nli0l_dataout <= wire_nllli_dataout AND NOT(wire_niOl_dataout); + wire_nli0O_dataout <= wire_nllll_dataout AND NOT(wire_niOl_dataout); + wire_nli1i_dataout <= wire_nll0O_dataout AND NOT(wire_niOl_dataout); + wire_nli1l_dataout <= wire_nllii_dataout AND NOT(wire_niOl_dataout); + wire_nli1O_dataout <= wire_nllil_dataout AND NOT(wire_niOl_dataout); + wire_nliii_dataout <= wire_nlllO_dataout AND NOT(wire_niOl_dataout); + wire_nliil_dataout <= wire_nllOi_dataout AND NOT(wire_niOl_dataout); + wire_nliiO_dataout <= wire_nllOl_dataout AND NOT(wire_niOl_dataout); + wire_nlili_dataout <= wire_nllOO_dataout AND NOT(wire_niOl_dataout); + wire_nlill_dataout <= wire_nlO1i_dataout AND NOT(wire_niOl_dataout); + wire_nlilO_dataout <= wire_nlO1l_dataout AND NOT(wire_niOl_dataout); + wire_nliOi_dataout <= wire_nlO1O_dataout AND NOT(wire_niOl_dataout); + wire_nliOl_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOl0i; + wire_nliOO_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOl0l; + wire_nll_dataout <= wire_ni_o(7) WHEN wire_niOi_dataout = '1' ELSE rcid_len(6); + wire_nll0i_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOliO; + wire_nll0l_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOlli; + wire_nll0O_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOlll; + wire_nll1i_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOl0O; + wire_nll1l_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOlii; + wire_nll1O_dataout <= rcid_pattern WHEN wire_niOi_dataout = '1' ELSE nlOlil; + wire_nllii_dataout <= nlOllO AND NOT(wire_niOi_dataout); + wire_nllil_dataout <= nlOlOi AND NOT(wire_niOi_dataout); + wire_nlliO_dataout <= nlOlOl AND NOT(wire_niOi_dataout); + wire_nllli_dataout <= nlOlOO AND NOT(wire_niOi_dataout); + wire_nllll_dataout <= nlOO1i AND NOT(wire_niOi_dataout); + wire_nlllO_dataout <= nlOO1l AND NOT(wire_niOi_dataout); + wire_nllOi_dataout <= nlOO1O AND NOT(wire_niOi_dataout); + wire_nllOl_dataout <= nlOO0i AND NOT(wire_niOi_dataout); + wire_nllOO_dataout <= nlOO0l AND NOT(wire_niOi_dataout); + wire_nlO_dataout <= wire_ni_o(8) WHEN wire_niOi_dataout = '1' ELSE rcid_len(7); + wire_nlO0i_dataout <= nlOl0i WHEN nlli1l = '1' ELSE ((nll0Oi XOR nlOl0l) XOR nlOl0i); + wire_nlO0l_dataout <= nlOl0l WHEN nlli1l = '1' ELSE ((nlli1i XOR nlOl0O) XOR nlOl0l); + wire_nlO0O_dataout <= nlOl0O WHEN nlli1l = '1' ELSE (wire_w_lg_w_lg_w160w161w162w(0) XOR (NOT (nll1lO42 XOR nll1lO41))); + wire_nlO1i_dataout <= nlOO0O AND NOT(wire_niOi_dataout); + wire_nlO1l_dataout <= nlOOii AND NOT(wire_niOi_dataout); + wire_nlO1O_dataout <= nlOOil AND NOT(wire_niOi_dataout); + wire_nlOii_dataout <= nlOlii WHEN nlli1l = '1' ELSE (wire_nl_w_lg_w144w145w(0) XOR (NOT (nll01O36 XOR nll01O35))); + wire_nlOil_dataout <= nlOlil WHEN nlli1l = '1' ELSE (nll0ll XOR nlOl0i); + wire_nlOiO_dataout <= nlOliO WHEN nlli1l = '1' ELSE (nll0lO XOR nlOl0l); + wire_nlOli_dataout <= nlOlli WHEN nlli1l = '1' ELSE ((nll0Oi XOR nlOl0O) XOR (NOT (nll0ii32 XOR nll0ii31))); + wire_nlOll_dataout <= nlOlll WHEN nlli1l = '1' ELSE ((nlli1i XOR nlOlii) XOR (NOT (nll0iO30 XOR nll0iO29))); + wire_nlOlO_dataout <= nlOllO AND nlli1l; + wire_nlOOi_dataout <= nlOlOi AND nlli1l; + wire_nlOOl_dataout <= nlOlOl AND nlli1l; + wire_nlOOO_dataout <= nlOlOO AND nlli1l; + wire_nlOOOi_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1ilO_dataout; + wire_nlOOOl_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1iOi_dataout; + wire_nlOOOO_dataout <= wire_w_lg_nlli0i2123w(0) WHEN nlliii = '1' ELSE wire_n1iOl_dataout; + wire_ni_a <= ( wire_nlllil10_w_lg_w_lg_q20w21w & wire_nllliO8_w_lg_w_lg_q17w18w & n1i & nlOO & wire_nlllli6_w_lg_w_lg_q12w13w & nlOi & nllO & wire_nlllll4_w_lg_w_lg_q7w8w & "1"); + wire_ni_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + ni : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_ni_a, + b => wire_ni_b, + cin => wire_gnd, + o => wire_ni_o + ); + wire_n00ii_w_lg_w_lg_w_o_range106w1878w1941w(0) <= wire_n00ii_w_lg_w_o_range106w1878w(0) OR wire_n00ii_w_o_range1798w(0); + wire_n00ii_w_lg_w_lg_w_o_range106w1961w1962w(0) <= wire_n00ii_w_lg_w_o_range106w1961w(0) OR wire_n00ii_w_o_range1824w(0); + wire_n00ii_w_lg_w_o_range106w1878w(0) <= wire_n00ii_w_o_range106w(0) OR wire_n00ii_w_o_range1824w(0); + wire_n00ii_w_lg_w_o_range106w1961w(0) <= wire_n00ii_w_o_range106w(0) OR wire_n00ii_w_o_range1839w(0); + wire_n00ii_i <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + wire_n00ii_w_o_range106w(0) <= wire_n00ii_o(16); + wire_n00ii_w_o_range1798w(0) <= wire_n00ii_o(17); + wire_n00ii_w_o_range1824w(0) <= wire_n00ii_o(18); + wire_n00ii_w_o_range1839w(0) <= wire_n00ii_o(25); + n00ii : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_n00ii_i, + o => wire_n00ii_o + ); + wire_n00il_data <= ( "0" & "0" & "0" & "1" & "1" & "1" & wire_nl_w_lg_w_lg_nlOO0l1760w1761w & nliOOO & "0" & "0" & "0" & "0" & "0" & "1" & nliliO & wire_nl_w_lg_nlOlOl1744w & "0" & "0" & "0" & "0" & wire_niiil_dataout & "1" & "1" & nll1iO & "0" & "0" & "0" & nliO1l & "0" & wire_nl_w_lg_nlOl0O1719w & "1" & wire_nlO0i_dataout); + wire_n00il_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00il : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00il_data, + o => wire_n00il_o, + sel => wire_n00il_sel + ); + wire_n00iO_data <= ( "0" & "0" & "0" & "1" & "1" & "0" & wire_nl_w_lg_w_lg_nlOO0O1692w1693w & nll11i & "0" & "0" & "0" & "0" & "0" & "0" & nlilli & wire_nl_w_lg_nlOlOO1676w & "0" & "0" & "0" & "0" & wire_niiiO_dataout & "1" & "0" & nll10O & "0" & "0" & "0" & nliO1O & "0" & wire_nl_w_lg_nlOlii1651w & "0" & wire_nlO0l_dataout); + wire_n00iO_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00iO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00iO_data, + o => wire_n00iO_o, + sel => wire_n00iO_sel + ); + wire_n00li_data <= ( "0" & "0" & "0" & "1" & "1" & "1" & wire_nl_w_lg_nlOliO1625w & nliOli & "0" & "0" & "0" & "0" & "0" & "1" & nlilll & nll11O & "0" & "0" & "0" & "0" & wire_niili_dataout & "1" & "1" & nll10l & "0" & "0" & "0" & nliO0i & "0" & nll0ll & "1" & wire_nlO0O_dataout); + wire_n00li_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00li : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00li_data, + o => wire_n00li_o, + sel => wire_n00li_sel + ); + wire_n00ll_data <= ( "0" & "0" & "0" & "1" & "1" & "0" & wire_nl_w_lg_nlOlli1560w & nliOll & "0" & "0" & "0" & "0" & "0" & "0" & nlillO & nll10i & "0" & "0" & "0" & "0" & wire_niill_dataout & "1" & "0" & wire_nl_w_lg_nlOlli1530w & "0" & "0" & "0" & nliO0l & "0" & nll0lO & "0" & wire_nlOii_dataout); + wire_n00ll_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00ll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00ll_data, + o => wire_n00ll_o, + sel => wire_n00ll_sel + ); + wire_n00lO_data <= ( "0" & "0" & "0" & "1" & "1" & "1" & nliliO & nliOlO & "0" & "0" & "0" & "0" & "0" & "1" & nlilOi & nliOOO & "0" & "0" & "0" & "0" & wire_niilO_dataout & "1" & "1" & wire_nl_w_lg_nlOlll1465w & "0" & "0" & "0" & nliO0O & "0" & nll0Oi & "1" & wire_nlOil_dataout); + wire_n00lO_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00lO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00lO_data, + o => wire_n00lO_o, + sel => wire_n00lO_sel + ); + wire_n00Oi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nlilli & nliOOl & "0" & "0" & "0" & "0" & "0" & "0" & nlilOl & nll11i & "0" & "0" & "0" & "0" & wire_niiOi_dataout & "0" & "0" & wire_nl_w_lg_nlOllO1400w & "0" & "0" & "0" & nliOii & "0" & nlli1i & "0" & wire_nlOiO_dataout); + wire_n00Oi_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00Oi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00Oi_data, + o => wire_n00Oi_o, + sel => wire_n00Oi_sel + ); + wire_n00Ol_data <= ( "0" & "0" & "0" & "1" & "0" & "1" & nlilll & wire_w_lg_nliO0O1363w & "0" & "0" & "0" & "0" & "0" & "1" & nlilOO & wire_w_lg_nliO1l1348w & "0" & "0" & "0" & "0" & wire_niiOl_dataout & "0" & "1" & wire_nl_w_lg_nlOlOi1333w & "0" & "0" & "0" & nliOil & "0" & wire_nl_w_lg_w_lg_nlOlll1321w1322w & "1" & wire_nlOli_dataout); + wire_n00Ol_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00Ol : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00Ol_data, + o => wire_n00Ol_o, + sel => wire_n00Ol_sel + ); + wire_n00OO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nlillO & nll11l & "0" & "0" & "0" & "0" & "0" & "0" & nliO1i & wire_nl_w_lg_nlOlOO1280w & "0" & "0" & "0" & "0" & wire_niiOO_dataout & "0" & "0" & wire_w_lg_nll1iO1265w & "0" & "0" & "0" & nliOiO & "0" & wire_nl_w_lg_nlOlii1254w & "0" & wire_nlOll_dataout); + wire_n00OO_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n00OO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n00OO_data, + o => wire_n00OO_o, + sel => wire_n00OO_sel + ); + wire_n0i0i_data <= ( "0" & "0" & "0" & "0" & "1" & "0" & nliO1i & wire_nl_w_lg_nlOOil1023w & "0" & "0" & "0" & "0" & "0" & "0" & nliO0l & nll11l & "0" & "0" & "0" & "0" & wire_nil0i_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOlii & "0" & "0" & "0" & wire_nlOOO_dataout); + wire_n0i0i_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0i0i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0i0i_data, + o => wire_n0i0i_o, + sel => wire_n0i0i_sel + ); + wire_n0i0l_data <= ( "0" & "0" & "0" & "0" & "1" & "1" & nliO1l & wire_nl_w_lg_w_lg_nlOOii955w956w & "0" & "0" & "0" & "0" & "0" & "1" & nliO0O & wire_nl_w_lg_w_lg_nlOO1O939w940w & "0" & "0" & "0" & "0" & wire_nil0l_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOlil & "0" & "0" & "0" & wire_n11i_dataout); + wire_n0i0l_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0i0l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0i0l_data, + o => wire_n0i0l_o, + sel => wire_n0i0l_sel + ); + wire_n0i0O_data <= ( "0" & "0" & "0" & "0" & "1" & "0" & nliO1O & wire_nl_w_lg_w_lg_nlOOil885w886w & "0" & "0" & "0" & "0" & "0" & "0" & nliOii & wire_nl_w_lg_w_lg_nlOO0i869w870w & "0" & "0" & "0" & "0" & wire_nil0O_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOliO & "0" & "0" & "0" & wire_n11l_dataout); + wire_n0i0O_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0i0O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0i0O_data, + o => wire_n0i0O_o, + sel => wire_n0i0O_sel + ); + wire_n0i1i_data <= ( "0" & "0" & "0" & "1" & "0" & "1" & nlilOi & wire_nl_w_lg_nlOO0l1227w & "0" & "0" & "0" & "0" & "0" & "1" & nliO1l & wire_nl_w_lg_nlOO1i1212w & "0" & "0" & "0" & "0" & wire_nil1i_dataout & "0" & "1" & wire_w_lg_nll10O1197w & "0" & "0" & "0" & nlOl0i & "0" & "0" & "0" & wire_nlOlO_dataout); + wire_n0i1i_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0i1i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0i1i_data, + o => wire_n0i1i_o, + sel => wire_n0i1i_sel + ); + wire_n0i1l_data <= ( "0" & "0" & "0" & "1" & "0" & "0" & nlilOl & wire_nl_w_lg_nlOO0O1159w & "0" & "0" & "0" & "0" & "0" & "0" & nliO1O & wire_nl_w_lg_nlOO1l1144w & "0" & "0" & "0" & "0" & wire_nil1l_dataout & "0" & "0" & wire_w_lg_nll10l1129w & "0" & "0" & "0" & nlOl0l & "0" & "0" & "0" & wire_nlOOi_dataout); + wire_n0i1l_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0i1l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0i1l_data, + o => wire_n0i1l_o, + sel => wire_n0i1l_sel + ); + wire_n0i1O_data <= ( "0" & "0" & "0" & "0" & "1" & "1" & nlilOO & wire_nl_w_lg_nlOOii1091w & "0" & "0" & "0" & "0" & "0" & "1" & nliO0i & wire_nl_w_lg_nlOO1O1076w & "0" & "0" & "0" & "0" & wire_nil1O_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOl0O & "0" & "0" & "0" & wire_nlOOl_dataout); + wire_n0i1O_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0i1O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0i1O_data, + o => wire_n0i1O_o, + sel => wire_n0i1O_sel + ); + wire_n0iii_data <= ( "0" & "0" & "0" & "0" & "1" & "1" & nliO0i & wire_w_lg_w_lg_nliOli815w816w & "0" & "0" & "0" & "0" & "0" & "1" & nliOil & wire_w_lg_w_lg_nll11O799w800w & "0" & "0" & "0" & "0" & wire_nilii_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOlli & "0" & "0" & "0" & wire_n11O_dataout); + wire_n0iii_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0iii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0iii_data, + o => wire_n0iii_o, + sel => wire_n0iii_sel + ); + wire_n0iil_data <= ( "0" & "0" & "0" & "1" & "0" & "0" & nliO0l & wire_w_lg_w_lg_nliOll745w746w & "0" & "0" & "0" & "0" & "0" & "0" & nliOiO & wire_w_lg_w_lg_nll10i729w730w & "0" & "0" & "0" & "0" & wire_nilil_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOlll & "0" & "0" & "0" & wire_n10i_dataout); + wire_n0iil_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0iil : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0iil_data, + o => wire_n0iil_o, + sel => wire_n0iil_sel + ); + wire_n0iiO_data <= ( "0" & "0" & "0" & "0" & "0" & "1" & nliO0O & wire_w_lg_w_lg_nliOlO675w676w & "0" & "0" & "0" & "0" & "0" & "0" & nlOl0i & "0" & "0" & "0" & "0" & "0" & wire_niliO_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOllO & "0" & "0" & "0" & wire_n10l_dataout); + wire_n0iiO_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0iiO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0iiO_data, + o => wire_n0iiO_o, + sel => wire_n0iiO_sel + ); + wire_n0ili_data <= ( "0" & "0" & "0" & "1" & "0" & "0" & nliOii & wire_w_lg_nliOOi607w & "0" & "0" & "0" & "0" & "0" & "0" & nlOl0l & "0" & "0" & "0" & "0" & "0" & wire_nilli_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOlOi & "0" & "0" & "0" & wire_n10O_dataout); + wire_n0ili_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0ili : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0ili_data, + o => wire_n0ili_o, + sel => wire_n0ili_sel + ); + wire_n0ill_data <= ( "0" & "0" & "0" & "0" & "0" & "1" & nliOil & wire_w_lg_w_lg_nliOOi538w539w & "0" & "0" & "0" & "0" & "0" & "0" & nlOl0O & "0" & "0" & "0" & "0" & "0" & wire_nilll_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOlOl & "0" & "0" & "0" & wire_n1ii_dataout); + wire_n0ill_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0ill : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0ill_data, + o => wire_n0ill_o, + sel => wire_n0ill_sel + ); + wire_n0ilO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nliOiO & wire_w_lg_w_lg_nliOOl469w470w & "0" & "0" & "0" & "0" & "0" & "0" & nlOlii & "0" & "0" & "0" & "0" & "0" & wire_nillO_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOlOO & "0" & "0" & "0" & wire_n1il_dataout); + wire_n0ilO_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0ilO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0ilO_data, + o => wire_n0ilO_o, + sel => wire_n0ilO_sel + ); + wire_n0iOi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nlOl0i & "0" & "0" & "0" & "0" & "0" & "0" & "0" & nlOlil & "0" & "0" & "0" & "0" & "0" & wire_nilOi_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOO1i & "0" & "0" & "0" & wire_n1iO_dataout); + wire_n0iOi_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0iOi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0iOi_data, + o => wire_n0iOi_o, + sel => wire_n0iOi_sel + ); + wire_n0iOl_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nlOl0l & "0" & "0" & "0" & "0" & "0" & "0" & "0" & nlOliO & "0" & "0" & "0" & "0" & "0" & wire_nilOl_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOO1l & "0" & "0" & "0" & wire_n1li_dataout); + wire_n0iOl_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0iOl : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0iOl_data, + o => wire_n0iOl_o, + sel => wire_n0iOl_sel + ); + wire_n0iOO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nlOl0O & "0" & "0" & "0" & "0" & "0" & "0" & "0" & nlOlli & "0" & "0" & "0" & "0" & "0" & wire_nilOO_dataout & "0" & "0" & "0" & "0" & "0" & "0" & nlOO1O & "0" & "0" & "0" & wire_n1ll_dataout); + wire_n0iOO_sel <= ( rpma_doublewidth_tx & rpmadwidth_tx & rprbs_sel(2 DOWNTO 0)); + n0iOO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n0iOO_data, + o => wire_n0iOO_o, + sel => wire_n0iOO_sel + ); + wire_n000i_data <= ( "0" & nlOOil & nlOlii & wire_nliOi_dataout); + wire_n000i_sel <= ( nlilil & nlilii & wire_n00ii_o(25) & wire_n00ii_o(0)); + n000i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n000i_data, + o => wire_n000i_o, + sel => wire_n000i_sel + ); + wire_n001O_data <= ( "0" & nlOOii & nlOlil & wire_nlilO_dataout); + wire_n001O_sel <= ( nlilil & nlilii & wire_n00ii_o(25) & wire_n00ii_o(0)); + n001O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n001O_data, + o => wire_n001O_o, + sel => wire_n001O_sel + ); + wire_n010i_data <= ( "0" & nlOlOO & nlOlOi & nlOO1l & wire_nli0l_dataout); + wire_n010i_sel <= ( nlil0O & nlil1l & nlil0i & wire_n00ii_o(17) & wire_n00ii_o(0)); + n010i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n010i_data, + o => wire_n010i_o, + sel => wire_n010i_sel + ); + wire_n010O_data <= ( "0" & nlOO1i & nlOlOl & wire_nli0O_dataout); + wire_n010O_sel <= ( nlil0O & nlil1O & wire_n00ii_w_lg_w_lg_w_o_range106w1961w1962w & wire_n00ii_o(0)); + n010O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n010O_data, + o => wire_n010O_o, + sel => wire_n010O_sel + ); + wire_n011i_data <= ( "0" & nlOllO & nlOO1O & nlOO0l & wire_nli1l_dataout); + wire_n011i_sel <= ( nlilil & nlil0l & wire_n00ii_o(25) & nlil0i & wire_n00ii_o(0)); + n011i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n011i_data, + o => wire_n011i_o, + sel => wire_n011i_sel + ); + wire_n011l_data <= ( "0" & nlOlOi & nlOO1l & nlOO0O & wire_nli1O_dataout); + wire_n011l_sel <= ( nlilil & nlil0l & wire_n00ii_o(25) & nlil0i & wire_n00ii_o(0)); + n011l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n011l_data, + o => wire_n011l_o, + sel => wire_n011l_sel + ); + wire_n011O_data <= ( "0" & nlOlOl & nlOO1i & nlOllO & nlOO1O & wire_nli0i_dataout); + wire_n011O_sel <= ( nlil0O & nlil0l & wire_n00ii_o(25) & nlil0i & wire_n00ii_o(17) & wire_n00ii_o(0)); + n011O : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n011O_data, + o => wire_n011O_o, + sel => wire_n011O_sel + ); + wire_n01iO_data <= ( "0" & nlOO1l & nlOlOi & nlOlOO & wire_nliii_dataout); + wire_n01iO_sel <= ( nlil0O & nlil0l & wire_n00ii_o(25) & wire_n00ii_w_lg_w_lg_w_o_range106w1878w1941w & wire_n00ii_o(0)); + n01iO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n01iO_data, + o => wire_n01iO_o, + sel => wire_n01iO_sel + ); + wire_n01ll_data <= ( "0" & nlOO1O & nlOllO & nlOO1i & nlOlOl & wire_nliil_dataout); + wire_n01ll_sel <= ( nlil0O & nlil0l & wire_n00ii_o(25) & nlil0i & wire_n00ii_o(17) & wire_n00ii_o(0)); + n01ll : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n01ll_data, + o => wire_n01ll_o, + sel => wire_n01ll_sel + ); + wire_n01lO_data <= ( "0" & nlOO0i & nlOlll & nlOO1l & nlOlOi & wire_nliiO_dataout); + wire_n01lO_sel <= ( nlil0O & nlil0l & wire_n00ii_o(25) & nlil0i & wire_n00ii_o(17) & wire_n00ii_o(0)); + n01lO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n01lO_data, + o => wire_n01lO_o, + sel => wire_n01lO_sel + ); + wire_n01Oi_data <= ( "0" & nlOO0l & nlOlli & nlOO1O & nlOllO & wire_nlili_dataout); + wire_n01Oi_sel <= ( nlil0O & nlil0l & wire_n00ii_o(25) & nlil0i & wire_n00ii_o(17) & wire_n00ii_o(0)); + n01Oi : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n01Oi_data, + o => wire_n01Oi_o, + sel => wire_n01Oi_sel + ); + wire_n01Ol_data <= ( "0" & nlOO0O & nlOliO & nlOO0i & nlOlll & wire_nlill_dataout); + wire_n01Ol_sel <= ( nlil0O & nlil0l & wire_n00ii_o(25) & nlil0i & wire_n00ii_o(17) & wire_n00ii_o(0)); + n01Ol : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n01Ol_data, + o => wire_n01Ol_o, + sel => wire_n01Ol_sel + ); + wire_n1O0O_data <= ( "0" & nlOl0i & nlOOll & wire_nl0iO_dataout); + wire_n1O0O_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1O0O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1O0O_data, + o => wire_n1O0O_o, + sel => wire_n1O0O_sel + ); + wire_n1Oii_data <= ( "0" & nlOl0l & nlOOli & wire_nl0li_dataout); + wire_n1Oii_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1Oii : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oii_data, + o => wire_n1Oii_o, + sel => wire_n1Oii_sel + ); + wire_n1Oil_data <= ( "0" & nlOl0O & nlOOiO & wire_nl0ll_dataout); + wire_n1Oil_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1Oil : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oil_data, + o => wire_n1Oil_o, + sel => wire_n1Oil_sel + ); + wire_n1OiO_data <= ( "0" & nlOlii & nlOOil & wire_nl0lO_dataout); + wire_n1OiO_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1OiO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OiO_data, + o => wire_n1OiO_o, + sel => wire_n1OiO_sel + ); + wire_n1Oli_data <= ( "0" & nlOlil & nlOOii & wire_nl0Oi_dataout); + wire_n1Oli_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1Oli : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oli_data, + o => wire_n1Oli_o, + sel => wire_n1Oli_sel + ); + wire_n1Oll_data <= ( "0" & nlOliO & nlOO0O & wire_nl0Ol_dataout); + wire_n1Oll_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1Oll : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oll_data, + o => wire_n1Oll_o, + sel => wire_n1Oll_sel + ); + wire_n1OlO_data <= ( "0" & nlOlli & nlOO0l & wire_nl0OO_dataout); + wire_n1OlO_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1OlO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OlO_data, + o => wire_n1OlO_o, + sel => wire_n1OlO_sel + ); + wire_n1OOi_data <= ( "0" & nlOlll & nlOO0i & wire_nli1i_dataout); + wire_n1OOi_sel <= ( nlil1i & nlilii & nliiOO & wire_n00ii_o(0)); + n1OOi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OOi_data, + o => wire_n1OOi_o, + sel => wire_n1OOi_sel + ); + wire_niOO_data <= ( nllilO & wire_nl1O_dataout & nllili); + wire_niOO_sel <= ( nlli & nilO & wire_nlliil22_w_lg_w_lg_q93w94w); + niOO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOO_data, + o => wire_niOO_o, + sel => wire_niOO_sel + ); + wire_nl1i_data <= ( "0" & wire_nlliiO20_w_lg_w_lg_q88w89w & wire_w_lg_nllili85w); + wire_nl1i_sel <= ( nlli & nilO & wire_nllill18_w_lg_w_lg_q79w80w); + nl1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1i_data, + o => wire_nl1i_o, + sel => wire_nl1i_sel + ); + wire_nl1l_data <= ( wire_w_lg_nllilO77w & wire_nl0i_dataout & "0"); + wire_nl1l_sel <= ( nlli & wire_nlliOi16_w_lg_w_lg_q69w70w & nlil); + nl1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1l_data, + o => wire_nl1l_o, + sel => wire_nl1l_sel + ); + + END RTL; --cycloneiv_hssi_tx_digi_prbs_gen +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 139 mux21 168 oper_decoder 2 oper_mux 184 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_tx_digi_enc_chnl_top IS + PORT + ( + cascaded_8b10b_en : IN STD_LOGIC; + clk : IN STD_LOGIC; + d21_5_eq_n : IN STD_LOGIC; + d2_2_eq_n : IN STD_LOGIC; + disp_out_3b : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + doublewidth : IN STD_LOGIC; + dwidth : IN STD_LOGIC; + endec : IN STD_LOGIC; + enpolinv_tx : IN STD_LOGIC; + ge_xaui_sel : IN STD_LOGIC; + ib_force_disparity : IN STD_LOGIC; + k_det : IN STD_LOGIC; + prbs_en : IN STD_LOGIC; + pudr : OUT STD_LOGIC_VECTOR (19 DOWNTO 0); + r8b10b_enc_ibm_en : IN STD_LOGIC; + renbitrev_tx : IN STD_LOGIC; + rendec_data_sel_tx : IN STD_LOGIC; + renpolinv_tx : IN STD_LOGIC; + rensymswap_tx : IN STD_LOGIC; + rev_loop_data : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + rev_loopbk : IN STD_LOGIC; + rforce_disp : IN STD_LOGIC; + rrev_loopbk : IN STD_LOGIC; + rst : IN STD_LOGIC; + rtxbitslip_en : IN STD_LOGIC; + tx_boundary_sel : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tx_ctl_pre_en : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + tx_ctl_tc : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + tx_ctl_ts : IN STD_LOGIC; + tx_data_9_pre_en : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + tx_data_9_tc : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + tx_data_pg : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + tx_data_pre_en : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + tx_data_tc : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + tx_data_ts : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + txd_extend_tc : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + txlp20b : OUT STD_LOGIC_VECTOR (19 DOWNTO 0) + ); + END cycloneiv_hssi_tx_digi_enc_chnl_top; + + ARCHITECTURE RTL OF cycloneiv_hssi_tx_digi_enc_chnl_top IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL ni0O0l49 : STD_LOGIC := '0'; + SIGNAL ni0O0l50 : STD_LOGIC := '0'; + SIGNAL ni0O0O47 : STD_LOGIC := '0'; + SIGNAL ni0O0O48 : STD_LOGIC := '0'; + SIGNAL ni0Oii45 : STD_LOGIC := '0'; + SIGNAL ni0Oii46 : STD_LOGIC := '0'; + SIGNAL ni0OiO43 : STD_LOGIC := '0'; + SIGNAL ni0OiO44 : STD_LOGIC := '0'; + SIGNAL ni0Oli41 : STD_LOGIC := '0'; + SIGNAL ni0Oli42 : STD_LOGIC := '0'; + SIGNAL ni0Oll39 : STD_LOGIC := '0'; + SIGNAL ni0Oll40 : STD_LOGIC := '0'; + SIGNAL wire_ni0Oll40_w_lg_w_lg_q202w203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0Oll40_w_lg_q202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni0OlO37 : STD_LOGIC := '0'; + SIGNAL ni0OlO38 : STD_LOGIC := '0'; + SIGNAL wire_ni0OlO38_w_lg_w_lg_q195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OlO38_w_lg_q195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni0OOi35 : STD_LOGIC := '0'; + SIGNAL ni0OOi36 : STD_LOGIC := '0'; + SIGNAL wire_ni0OOi36_w_lg_w_lg_q187w189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OOi36_w_lg_q187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni0OOl33 : STD_LOGIC := '0'; + SIGNAL ni0OOl34 : STD_LOGIC := '0'; + SIGNAL wire_ni0OOl34_w_lg_w_lg_q160w161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OOl34_w_lg_q160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni0OOO31 : STD_LOGIC := '0'; + SIGNAL ni0OOO32 : STD_LOGIC := '0'; + SIGNAL wire_ni0OOO32_w_lg_w_lg_q139w140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OOO32_w_lg_q139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii00i5 : STD_LOGIC := '0'; + SIGNAL nii00i6 : STD_LOGIC := '0'; + SIGNAL wire_nii00i6_w_lg_q15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii01l7 : STD_LOGIC := '0'; + SIGNAL nii01l8 : STD_LOGIC := '0'; + SIGNAL wire_nii01l8_w_lg_q21w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii0ii3 : STD_LOGIC := '0'; + SIGNAL nii0ii4 : STD_LOGIC := '0'; + SIGNAL nii0iO1 : STD_LOGIC := '0'; + SIGNAL nii0iO2 : STD_LOGIC := '0'; + SIGNAL wire_nii0iO2_w_lg_q3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii10i23 : STD_LOGIC := '0'; + SIGNAL nii10i24 : STD_LOGIC := '0'; + SIGNAL wire_nii10i24_w_lg_w_lg_q100w101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii10i24_w_lg_q100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii10l21 : STD_LOGIC := '0'; + SIGNAL nii10l22 : STD_LOGIC := '0'; + SIGNAL wire_nii10l22_w_lg_w_lg_q86w87w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii10l22_w_lg_q86w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii10O19 : STD_LOGIC := '0'; + SIGNAL nii10O20 : STD_LOGIC := '0'; + SIGNAL wire_nii10O20_w_lg_w_lg_q83w84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii10O20_w_lg_q83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii11i29 : STD_LOGIC := '0'; + SIGNAL nii11i30 : STD_LOGIC := '0'; + SIGNAL wire_nii11i30_w_lg_w_lg_q132w134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii11i30_w_lg_q132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii11l27 : STD_LOGIC := '0'; + SIGNAL nii11l28 : STD_LOGIC := '0'; + SIGNAL wire_nii11l28_w_lg_w_lg_q118w120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii11l28_w_lg_q118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii11O25 : STD_LOGIC := '0'; + SIGNAL nii11O26 : STD_LOGIC := '0'; + SIGNAL wire_nii11O26_w_lg_w_lg_q115w116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii11O26_w_lg_q115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii1ii17 : STD_LOGIC := '0'; + SIGNAL nii1ii18 : STD_LOGIC := '0'; + SIGNAL wire_nii1ii18_w_lg_w_lg_q75w76w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii1ii18_w_lg_q75w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii1il15 : STD_LOGIC := '0'; + SIGNAL nii1il16 : STD_LOGIC := '0'; + SIGNAL wire_nii1il16_w_lg_w_lg_q67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii1il16_w_lg_q67w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii1li13 : STD_LOGIC := '0'; + SIGNAL nii1li14 : STD_LOGIC := '0'; + SIGNAL wire_nii1li14_w_lg_q33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii1lO11 : STD_LOGIC := '0'; + SIGNAL nii1lO12 : STD_LOGIC := '0'; + SIGNAL wire_nii1lO12_w_lg_q28w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nii1OO10 : STD_LOGIC := '0'; + SIGNAL nii1OO9 : STD_LOGIC := '0'; + SIGNAL n01li : STD_LOGIC := '0'; + SIGNAL wire_n01iO_PRN : STD_LOGIC; + SIGNAL wire_n01iO_ENA : STD_LOGIC; + SIGNAL wire_n01iO_w_lg_n01li1049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n000i : STD_LOGIC := '0'; + SIGNAL n000l : STD_LOGIC := '0'; + SIGNAL n000O : STD_LOGIC := '0'; + SIGNAL n001i : STD_LOGIC := '0'; + SIGNAL n001l : STD_LOGIC := '0'; + SIGNAL n001O : STD_LOGIC := '0'; + SIGNAL n00ii : STD_LOGIC := '0'; + SIGNAL n00il : STD_LOGIC := '0'; + SIGNAL n00iO : STD_LOGIC := '0'; + SIGNAL n00li : STD_LOGIC := '0'; + SIGNAL n00ll : STD_LOGIC := '0'; + SIGNAL n00lO : STD_LOGIC := '0'; + SIGNAL n00Oi : STD_LOGIC := '0'; + SIGNAL n00Ol : STD_LOGIC := '0'; + SIGNAL n00OO : STD_LOGIC := '0'; + SIGNAL n01ii : STD_LOGIC := '0'; + SIGNAL n01il : STD_LOGIC := '0'; + SIGNAL n01lO : STD_LOGIC := '0'; + SIGNAL n01Oi : STD_LOGIC := '0'; + SIGNAL n01Ol : STD_LOGIC := '0'; + SIGNAL n01OO : STD_LOGIC := '0'; + SIGNAL n0i1i : STD_LOGIC := '0'; + SIGNAL n0i1l : STD_LOGIC := '0'; + SIGNAL n0i1O : STD_LOGIC := '0'; + SIGNAL n0iiO : STD_LOGIC := '0'; + SIGNAL n0ill : STD_LOGIC := '0'; + SIGNAL n0iOl : STD_LOGIC := '0'; + SIGNAL n0iOO : STD_LOGIC := '0'; + SIGNAL n0l0l : STD_LOGIC := '0'; + SIGNAL n0l1i : STD_LOGIC := '0'; + SIGNAL n0l1l : STD_LOGIC := '0'; + SIGNAL n0l1O : STD_LOGIC := '0'; + SIGNAL n0lii : STD_LOGIC := '0'; + SIGNAL n0lil : STD_LOGIC := '0'; + SIGNAL n0liO : STD_LOGIC := '0'; + SIGNAL n0lli : STD_LOGIC := '0'; + SIGNAL n0lll : STD_LOGIC := '0'; + SIGNAL n0llO : STD_LOGIC := '0'; + SIGNAL n0lOi : STD_LOGIC := '0'; + SIGNAL ni00i : STD_LOGIC := '0'; + SIGNAL ni01l : STD_LOGIC := '0'; + SIGNAL ni0ii : STD_LOGIC := '0'; + SIGNAL ni0il : STD_LOGIC := '0'; + SIGNAL ni0iO : STD_LOGIC := '0'; + SIGNAL ni0li : STD_LOGIC := '0'; + SIGNAL ni0ll : STD_LOGIC := '0'; + SIGNAL ni0Ol : STD_LOGIC := '0'; + SIGNAL ni1li : STD_LOGIC := '0'; + SIGNAL ni1ll : STD_LOGIC := '0'; + SIGNAL nii0Oi : STD_LOGIC := '0'; + SIGNAL nii0Ol : STD_LOGIC := '0'; + SIGNAL nii0OO : STD_LOGIC := '0'; + SIGNAL niii0i : STD_LOGIC := '0'; + SIGNAL niii0l : STD_LOGIC := '0'; + SIGNAL niii0O : STD_LOGIC := '0'; + SIGNAL niii1i : STD_LOGIC := '0'; + SIGNAL niii1l : STD_LOGIC := '0'; + SIGNAL niii1O : STD_LOGIC := '0'; + SIGNAL niiiii : STD_LOGIC := '0'; + SIGNAL niiiil : STD_LOGIC := '0'; + SIGNAL niiiiO : STD_LOGIC := '0'; + SIGNAL niiili : STD_LOGIC := '0'; + SIGNAL niiill : STD_LOGIC := '0'; + SIGNAL niiilO : STD_LOGIC := '0'; + SIGNAL niiiOi : STD_LOGIC := '0'; + SIGNAL niiiOl : STD_LOGIC := '0'; + SIGNAL niiiOO : STD_LOGIC := '0'; + SIGNAL niil1i : STD_LOGIC := '0'; + SIGNAL wire_ni0Oi_CLRN : STD_LOGIC; + SIGNAL wire_ni0Oi_PRN : STD_LOGIC; + SIGNAL wire_ni0Oi_w_lg_n01il36w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0i0i : STD_LOGIC := '0'; + SIGNAL n0i0l : STD_LOGIC := '0'; + SIGNAL n0i0O : STD_LOGIC := '0'; + SIGNAL n0iii : STD_LOGIC := '0'; + SIGNAL n0iil : STD_LOGIC := '0'; + SIGNAL n0ili : STD_LOGIC := '0'; + SIGNAL n0ilO : STD_LOGIC := '0'; + SIGNAL n0iOi : STD_LOGIC := '0'; + SIGNAL n0l0i : STD_LOGIC := '0'; + SIGNAL n0l0O : STD_LOGIC := '0'; + SIGNAL ni00l : STD_LOGIC := '0'; + SIGNAL ni00O : STD_LOGIC := '0'; + SIGNAL ni01i : STD_LOGIC := '0'; + SIGNAL ni01O : STD_LOGIC := '0'; + SIGNAL ni0lO : STD_LOGIC := '0'; + SIGNAL ni1lO : STD_LOGIC := '0'; + SIGNAL ni1Oi : STD_LOGIC := '0'; + SIGNAL ni1Ol : STD_LOGIC := '0'; + SIGNAL ni1OO : STD_LOGIC := '0'; + SIGNAL nii1i : STD_LOGIC := '0'; + SIGNAL wire_ni0OO_CLRN : STD_LOGIC; + SIGNAL wire_ni0OO_PRN : STD_LOGIC; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00i_w_lg_w_lg_dataout1617w1689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w_lg_dataout1617w1640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w_lg_dataout1617w1698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_dataout1617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w_lg_w_lg_dataout1617w1689w1691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w_lg_w_lg_dataout1617w1640w1643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w_lg_w_lg_dataout1617w1698w1699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w_lg_w_lg_w_lg_dataout1617w1689w1691w1693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w_lg_w_lg_w_lg_dataout1617w1640w1643w1646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w1695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w1649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_w_lg_w1695w1696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00l_w_lg_w_lg_w_lg_dataout1637w1638w1650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_w_lg_dataout1719w1720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_w_lg_dataout1637w1700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_w_lg_dataout1637w1638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_w_lg_w_lg_dataout1637w1679w1680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_dataout1685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_dataout1618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_dataout1719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_dataout1694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_dataout1692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_dataout1690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_dataout1637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00l_w_lg_w_lg_dataout1637w1679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n00O_w_lg_dataout1663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01i_w_lg_dataout1624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01l_w_lg_w_lg_dataout1620w1666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01l_w_lg_w_lg_dataout1620w1621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01l_w_lg_dataout1625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01l_w_lg_dataout1667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01l_w_lg_dataout1620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01l_w_lg_dataout1676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n01O_w_lg_w_lg_dataout1619w1750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_w_lg_dataout1619w1745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_w_lg_dataout1619w1736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_w_lg_dataout1619w1733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_w_lg_dataout1619w1641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_w_lg_dataout1619w1632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_dataout1739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_dataout1644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_dataout1647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_dataout1688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_dataout1639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_dataout1619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01O_w_lg_dataout1677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0ii_w_lg_dataout1654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ii_w_lg_dataout1616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0il_w_lg_dataout1655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0il_w_lg_dataout1612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_w_lg_dataout1848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_w_lg_dataout1697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1il_w_lg_dataout1775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iO_w_lg_w_lg_dataout1771w1817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iO_w_lg_w_lg_dataout1771w1772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iO_w_lg_dataout1776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iO_w_lg_dataout1818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iO_w_lg_dataout1771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iO_w_lg_dataout1827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1li_w_lg_w_lg_dataout1770w1792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_w_lg_dataout1770w1783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_w_lg_dataout1770w1901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_w_lg_dataout1770w1896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_w_lg_dataout1770w1887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_w_lg_dataout1770w1884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_dataout1890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_dataout1795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_dataout1798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_dataout1839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_dataout1790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_dataout1770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_w_lg_dataout1828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1ll_w_lg_w_lg_dataout1768w1840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w_lg_dataout1768w1791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w_lg_dataout1768w1849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1793w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_dataout1768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1840w1842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1791w1794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1849w1850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w_lg_w_lg_w_lg_dataout1768w1840w1842w1844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w_lg_w_lg_w_lg_dataout1768w1791w1794w1797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w1846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w1800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_w_lg_w1846w1847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1lO_w_lg_w_lg_w_lg_dataout1788w1789w1801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_w_lg_dataout1870w1871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_w_lg_dataout1788w1851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_w_lg_dataout1788w1789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_w_lg_w_lg_dataout1788w1830w1831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_dataout1836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_dataout1769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_dataout1870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_dataout1845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_dataout1843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_dataout1841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_dataout1788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO_w_lg_w_lg_dataout1788w1830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_w_lg_dataout1814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_w_lg_dataout1805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Ol_w_lg_dataout1767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO_w_lg_dataout1806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OO_w_lg_dataout1763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni10i_dataout : STD_LOGIC; + SIGNAL wire_ni10l_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0O_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil_w_lg_dataout1804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil00l_dataout : STD_LOGIC; + SIGNAL wire_nil00O_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil0OO_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nili1i_dataout : STD_LOGIC; + SIGNAL wire_niliOl_dataout : STD_LOGIC; + SIGNAL wire_niliOO_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nill0i_dataout : STD_LOGIC; + SIGNAL wire_nill0l_dataout : STD_LOGIC; + SIGNAL wire_nill0O_dataout : STD_LOGIC; + SIGNAL wire_nill1i_dataout : STD_LOGIC; + SIGNAL wire_nill1l_dataout : STD_LOGIC; + SIGNAL wire_nill1O_dataout : STD_LOGIC; + SIGNAL wire_nillii_dataout : STD_LOGIC; + SIGNAL wire_nillil_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_nilO0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O_dataout : STD_LOGIC; + SIGNAL wire_nilOii_dataout : STD_LOGIC; + SIGNAL wire_nilOil_dataout : STD_LOGIC; + SIGNAL wire_nilOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOli_dataout : STD_LOGIC; + SIGNAL wire_nilOll_dataout : STD_LOGIC; + SIGNAL wire_nilOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO_w_lg_dataout1653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOi_w_lg_w_lg_dataout1755w1758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOlOi_w_lg_w_lg_dataout1755w1760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOlOi_w_lg_dataout1802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOlOi_w_lg_dataout1755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOlOi_w_lg_w_lg_w_lg_dataout1755w1758w1759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl000i_dataout : STD_LOGIC; + SIGNAL wire_nl000l_dataout : STD_LOGIC; + SIGNAL wire_nl001i_dataout : STD_LOGIC; + SIGNAL wire_nl001i_w_lg_dataout1765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl001l_dataout : STD_LOGIC; + SIGNAL wire_nl001O_dataout : STD_LOGIC; + SIGNAL wire_nl00ll_dataout : STD_LOGIC; + SIGNAL wire_nl00ll_w_lg_dataout1757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010O_dataout : STD_LOGIC; + SIGNAL wire_nl01iO_dataout : STD_LOGIC; + SIGNAL wire_nl01iO_w_lg_dataout1762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01li_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol_w_lg_dataout1764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol_w_lg_dataout1859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10OO_dataout : STD_LOGIC; + SIGNAL wire_nl10OO_w_lg_dataout1860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl111i_dataout : STD_LOGIC; + SIGNAL wire_nl111l_dataout : STD_LOGIC; + SIGNAL wire_nl111O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O_w_lg_dataout1861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli0il_dataout : STD_LOGIC; + SIGNAL wire_nli0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1il_dataout : STD_LOGIC; + SIGNAL wire_nli1il_w_lg_w_lg_dataout1604w1607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1il_w_lg_w_lg_dataout1604w1609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1il_w_lg_dataout1651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1il_w_lg_dataout1604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1il_w_lg_w_lg_w_lg_dataout1604w1607w1608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nliliO_dataout : STD_LOGIC; + SIGNAL wire_nliliO_w_lg_dataout1708w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlilli_dataout : STD_LOGIC; + SIGNAL wire_nlilli_w_lg_dataout1709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliO1i_dataout : STD_LOGIC; + SIGNAL wire_nliO1i_w_lg_dataout1710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO1l_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlli0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0i_w_lg_dataout1611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli0l_dataout : STD_LOGIC; + SIGNAL wire_nlli1i_dataout : STD_LOGIC; + SIGNAL wire_nlliiO_dataout : STD_LOGIC; + SIGNAL wire_nlliiO_w_lg_dataout1613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllill_dataout : STD_LOGIC; + SIGNAL wire_nllill_w_lg_dataout1614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllilO_dataout : STD_LOGIC; + SIGNAL wire_nlliOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0O_dataout : STD_LOGIC; + SIGNAL wire_nlll0O_w_lg_dataout1606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_nili1O_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nili1O_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nillli_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nillli_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n010i_w_lg_o200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n010i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n010i_o : STD_LOGIC; + SIGNAL wire_n010i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010l_w_lg_o188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n010l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n010l_o : STD_LOGIC; + SIGNAL wire_n010l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010O_w_lg_o178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n010O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n010O_o : STD_LOGIC; + SIGNAL wire_n010O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n011i_w_lg_o229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n011i_o : STD_LOGIC; + SIGNAL wire_n011i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n011l_w_lg_o220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n011l_o : STD_LOGIC; + SIGNAL wire_n011l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n011O_w_lg_o211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n011O_o : STD_LOGIC; + SIGNAL wire_n011O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O0i_w_lg_o122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1O0i_o : STD_LOGIC; + SIGNAL wire_n1O0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O0l_w_lg_o133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1O0l_o : STD_LOGIC; + SIGNAL wire_n1O0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O0O_w_lg_o130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1O0O_o : STD_LOGIC; + SIGNAL wire_n1O0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O1l_w_lg_o96w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1O1l_o : STD_LOGIC; + SIGNAL wire_n1O1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O1O_w_lg_o108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1O1O_o : STD_LOGIC; + SIGNAL wire_n1O1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oii_w_lg_o119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1Oii_o : STD_LOGIC; + SIGNAL wire_n1Oii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oil_w_lg_o106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1Oil_o : STD_LOGIC; + SIGNAL wire_n1Oil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OiO_w_lg_o94w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1OiO_o : STD_LOGIC; + SIGNAL wire_n1OiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oli_w_lg_o81w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oli_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1Oli_o : STD_LOGIC; + SIGNAL wire_n1Oli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oll_w_lg_o70w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1Oll_o : STD_LOGIC; + SIGNAL wire_n1Oll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OlO_w_lg_o265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OlO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1OlO_o : STD_LOGIC; + SIGNAL wire_n1OlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OOi_w_lg_o256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1OOi_o : STD_LOGIC; + SIGNAL wire_n1OOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OOl_w_lg_o247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1OOl_o : STD_LOGIC; + SIGNAL wire_n1OOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OOO_w_lg_o238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1OOO_o : STD_LOGIC; + SIGNAL wire_n1OOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niil0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niil0i_o : STD_LOGIC; + SIGNAL wire_niil0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niil0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niil0l_o : STD_LOGIC; + SIGNAL wire_niil0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niil0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niil0O_o : STD_LOGIC; + SIGNAL wire_niil0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niil1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niil1l_o : STD_LOGIC; + SIGNAL wire_niil1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niil1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niil1O_o : STD_LOGIC; + SIGNAL wire_niil1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niilii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niilii_o : STD_LOGIC; + SIGNAL wire_niilii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niilil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niilil_o : STD_LOGIC; + SIGNAL wire_niilil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiliO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiliO_o : STD_LOGIC; + SIGNAL wire_niiliO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niilli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niilli_o : STD_LOGIC; + SIGNAL wire_niilli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niilll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niilll_o : STD_LOGIC; + SIGNAL wire_niilll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niillO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niillO_o : STD_LOGIC; + SIGNAL wire_niillO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niilOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niilOi_o : STD_LOGIC; + SIGNAL wire_niilOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niilOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niilOl_o : STD_LOGIC; + SIGNAL wire_niilOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niilOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niilOO_o : STD_LOGIC; + SIGNAL wire_niilOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiO0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiO0i_o : STD_LOGIC; + SIGNAL wire_niiO0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiO0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiO0l_o : STD_LOGIC; + SIGNAL wire_niiO0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiO0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiO0O_o : STD_LOGIC; + SIGNAL wire_niiO0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiO1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiO1i_o : STD_LOGIC; + SIGNAL wire_niiO1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiO1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiO1l_o : STD_LOGIC; + SIGNAL wire_niiO1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiO1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiO1O_o : STD_LOGIC; + SIGNAL wire_niiO1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niiOii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOii_o : STD_LOGIC; + SIGNAL wire_niiOii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOil_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOil_o : STD_LOGIC; + SIGNAL wire_niiOil_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOiO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOiO_o : STD_LOGIC; + SIGNAL wire_niiOiO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOli_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOli_o : STD_LOGIC; + SIGNAL wire_niiOli_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOll_o : STD_LOGIC; + SIGNAL wire_niiOll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOlO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOlO_o : STD_LOGIC; + SIGNAL wire_niiOlO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOOi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOOi_o : STD_LOGIC; + SIGNAL wire_niiOOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOOl_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOOl_o : STD_LOGIC; + SIGNAL wire_niiOOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOOO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiOOO_o : STD_LOGIC; + SIGNAL wire_niiOOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil00i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil00i_o : STD_LOGIC; + SIGNAL wire_nil00i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil01i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil01i_o : STD_LOGIC; + SIGNAL wire_nil01i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil01l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil01l_o : STD_LOGIC; + SIGNAL wire_nil01l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil01O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil01O_o : STD_LOGIC; + SIGNAL wire_nil01O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0ii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0ii_o : STD_LOGIC; + SIGNAL wire_nil0ii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0il_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0il_o : STD_LOGIC; + SIGNAL wire_nil0il_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0iO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0iO_o : STD_LOGIC; + SIGNAL wire_nil0iO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0li_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0li_o : STD_LOGIC; + SIGNAL wire_nil0li_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0ll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0ll_o : STD_LOGIC; + SIGNAL wire_nil0ll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0lO_o : STD_LOGIC; + SIGNAL wire_nil0lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0Oi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0Oi_o : STD_LOGIC; + SIGNAL wire_nil0Oi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0Ol_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil0Ol_o : STD_LOGIC; + SIGNAL wire_nil0Ol_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil10i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil10i_o : STD_LOGIC; + SIGNAL wire_nil10i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil10l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil10l_o : STD_LOGIC; + SIGNAL wire_nil10l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil10O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil10O_o : STD_LOGIC; + SIGNAL wire_nil10O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil11i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil11i_o : STD_LOGIC; + SIGNAL wire_nil11i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil11l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil11l_o : STD_LOGIC; + SIGNAL wire_nil11l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil11O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil11O_o : STD_LOGIC; + SIGNAL wire_nil11O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1ii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1ii_o : STD_LOGIC; + SIGNAL wire_nil1ii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1il_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1il_o : STD_LOGIC; + SIGNAL wire_nil1il_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1iO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1iO_o : STD_LOGIC; + SIGNAL wire_nil1iO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1li_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1li_o : STD_LOGIC; + SIGNAL wire_nil1li_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1ll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1ll_o : STD_LOGIC; + SIGNAL wire_nil1ll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1lO_o : STD_LOGIC; + SIGNAL wire_nil1lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1Oi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1Oi_o : STD_LOGIC; + SIGNAL wire_nil1Oi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1Ol_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1Ol_o : STD_LOGIC; + SIGNAL wire_nil1Ol_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil1OO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nil1OO_o : STD_LOGIC; + SIGNAL wire_nil1OO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nili0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nili0i_o : STD_LOGIC; + SIGNAL wire_nili0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nili0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nili0l_o : STD_LOGIC; + SIGNAL wire_nili0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nili0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nili0O_o : STD_LOGIC; + SIGNAL wire_nili0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilii_o : STD_LOGIC; + SIGNAL wire_nilii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niliii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niliii_o : STD_LOGIC; + SIGNAL wire_niliii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niliil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niliil_o : STD_LOGIC; + SIGNAL wire_niliil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niliiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niliiO_o : STD_LOGIC; + SIGNAL wire_niliiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilil_o : STD_LOGIC; + SIGNAL wire_nilil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nilili_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nilili_o : STD_LOGIC; + SIGNAL wire_nilili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilill_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nilill_o : STD_LOGIC; + SIGNAL wire_nilill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nililO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nililO_o : STD_LOGIC; + SIGNAL wire_nililO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niliO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niliO_o : STD_LOGIC; + SIGNAL wire_niliO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niliOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niliOi_o : STD_LOGIC; + SIGNAL wire_niliOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilli_o : STD_LOGIC; + SIGNAL wire_nilli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nilll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilll_o : STD_LOGIC; + SIGNAL wire_nilll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nillll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nillll_o : STD_LOGIC; + SIGNAL wire_nillll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilllO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nilllO_o : STD_LOGIC; + SIGNAL wire_nilllO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nillO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nillO_o : STD_LOGIC; + SIGNAL wire_nillO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nillOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nillOi_o : STD_LOGIC; + SIGNAL wire_nillOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nillOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nillOl_o : STD_LOGIC; + SIGNAL wire_nillOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nillOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nillOO_o : STD_LOGIC; + SIGNAL wire_nillOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilO1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nilO1i_o : STD_LOGIC; + SIGNAL wire_nilO1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilO1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nilO1l_o : STD_LOGIC; + SIGNAL wire_nilO1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilO1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nilO1O_o : STD_LOGIC; + SIGNAL wire_nilO1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOi_o : STD_LOGIC; + SIGNAL wire_nilOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nilOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOl_o : STD_LOGIC; + SIGNAL wire_nilOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nilOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nilOO_o : STD_LOGIC; + SIGNAL wire_nilOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niO0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niO0i_o : STD_LOGIC; + SIGNAL wire_niO0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niO0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niO0l_o : STD_LOGIC; + SIGNAL wire_niO0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niO0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niO0O_o : STD_LOGIC; + SIGNAL wire_niO0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niO1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niO1i_o : STD_LOGIC; + SIGNAL wire_niO1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niO1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niO1l_o : STD_LOGIC; + SIGNAL wire_niO1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niO1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niO1O_o : STD_LOGIC; + SIGNAL wire_niO1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niOii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOii_o : STD_LOGIC; + SIGNAL wire_niOii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niOil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOil_o : STD_LOGIC; + SIGNAL wire_niOil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niOiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOiO_o : STD_LOGIC; + SIGNAL wire_niOiO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niOli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOli_o : STD_LOGIC; + SIGNAL wire_niOli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niOll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOll_o : STD_LOGIC; + SIGNAL wire_niOll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_niOlO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niOlO_o : STD_LOGIC; + SIGNAL wire_niOlO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niOOi_o : STD_LOGIC; + SIGNAL wire_niOOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niOOl_o : STD_LOGIC; + SIGNAL wire_niOOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niOOO_o : STD_LOGIC; + SIGNAL wire_niOOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl00i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl00i_o : STD_LOGIC; + SIGNAL wire_nl00i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl00l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl00l_o : STD_LOGIC; + SIGNAL wire_nl00l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl00O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl00O_o : STD_LOGIC; + SIGNAL wire_nl00O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl01i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01i_o : STD_LOGIC; + SIGNAL wire_nl01i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl01l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01l_o : STD_LOGIC; + SIGNAL wire_nl01l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl01O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01O_o : STD_LOGIC; + SIGNAL wire_nl01O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0ii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0ii_o : STD_LOGIC; + SIGNAL wire_nl0ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0il_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0il_o : STD_LOGIC; + SIGNAL wire_nl0il_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0iO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0iO_o : STD_LOGIC; + SIGNAL wire_nl0iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0li_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0li_o : STD_LOGIC; + SIGNAL wire_nl0li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0ll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0ll_o : STD_LOGIC; + SIGNAL wire_nl0ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0lO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0lO_o : STD_LOGIC; + SIGNAL wire_nl0lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Oi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Oi_o : STD_LOGIC; + SIGNAL wire_nl0Oi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Ol_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol_o : STD_LOGIC; + SIGNAL wire_nl0Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OO_o : STD_LOGIC; + SIGNAL wire_nl0OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl10i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10i_o : STD_LOGIC; + SIGNAL wire_nl10i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl10l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10l_o : STD_LOGIC; + SIGNAL wire_nl10l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl10O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10O_o : STD_LOGIC; + SIGNAL wire_nl10O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl11i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl11i_o : STD_LOGIC; + SIGNAL wire_nl11i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl11l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl11l_o : STD_LOGIC; + SIGNAL wire_nl11l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl11O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl11O_o : STD_LOGIC; + SIGNAL wire_nl11O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1ii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1ii_o : STD_LOGIC; + SIGNAL wire_nl1ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1il_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il_o : STD_LOGIC; + SIGNAL wire_nl1il_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1iO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1iO_o : STD_LOGIC; + SIGNAL wire_nl1iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1li_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1li_o : STD_LOGIC; + SIGNAL wire_nl1li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1ll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1ll_o : STD_LOGIC; + SIGNAL wire_nl1ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1lO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1lO_o : STD_LOGIC; + SIGNAL wire_nl1lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1Oi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1Oi_o : STD_LOGIC; + SIGNAL wire_nl1Oi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1Ol_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1Ol_o : STD_LOGIC; + SIGNAL wire_nl1Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1OO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1OO_o : STD_LOGIC; + SIGNAL wire_nl1OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli0i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli0i_o : STD_LOGIC; + SIGNAL wire_nli0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli0l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli0l_o : STD_LOGIC; + SIGNAL wire_nli0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli0O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli0O_o : STD_LOGIC; + SIGNAL wire_nli0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli1i_o : STD_LOGIC; + SIGNAL wire_nli1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli1l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli1l_o : STD_LOGIC; + SIGNAL wire_nli1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli1O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli1O_o : STD_LOGIC; + SIGNAL wire_nli1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliii_o : STD_LOGIC; + SIGNAL wire_nliii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliil_o : STD_LOGIC; + SIGNAL wire_nliil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliiO_o : STD_LOGIC; + SIGNAL wire_nliiO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlili_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlili_o : STD_LOGIC; + SIGNAL wire_nlili_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlill_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill_o : STD_LOGIC; + SIGNAL wire_nlill_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlilO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlilO_o : STD_LOGIC; + SIGNAL wire_nlilO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliOi_o : STD_LOGIC; + SIGNAL wire_nliOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliOl_o : STD_LOGIC; + SIGNAL wire_nliOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliOO_o : STD_LOGIC; + SIGNAL wire_nliOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll0i_o : STD_LOGIC; + SIGNAL wire_nll0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll0l_o : STD_LOGIC; + SIGNAL wire_nll0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll0O_o : STD_LOGIC; + SIGNAL wire_nll0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1i_o : STD_LOGIC; + SIGNAL wire_nll1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1l_o : STD_LOGIC; + SIGNAL wire_nll1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1O_o : STD_LOGIC; + SIGNAL wire_nll1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllii_o : STD_LOGIC; + SIGNAL wire_nllii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllil_o : STD_LOGIC; + SIGNAL wire_nllil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlliO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlliO_o : STD_LOGIC; + SIGNAL wire_nlliO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllli_o : STD_LOGIC; + SIGNAL wire_nllli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll_o : STD_LOGIC; + SIGNAL wire_nllll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlllO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO_o : STD_LOGIC; + SIGNAL wire_nlllO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOi_o : STD_LOGIC; + SIGNAL wire_nllOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOl_o : STD_LOGIC; + SIGNAL wire_nllOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOO_o : STD_LOGIC; + SIGNAL wire_nllOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0i_o : STD_LOGIC; + SIGNAL wire_nlO0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0l_o : STD_LOGIC; + SIGNAL wire_nlO0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0O_o : STD_LOGIC; + SIGNAL wire_nlO0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO1i_o : STD_LOGIC; + SIGNAL wire_nlO1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO1l_o : STD_LOGIC; + SIGNAL wire_nlO1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO1O_o : STD_LOGIC; + SIGNAL wire_nlO1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_w_lg_w22w23w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w22w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w35w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w31w34w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_d21_5_eq_n1w4w5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_ni000i1832w1834w1835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_ni0l1i1681w1683w1684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_d21_5_eq_n1w16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_d21_5_eq_n1w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_d21_5_eq_n1w29w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_ni000i1832w1834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_ni0l1i1681w1683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_d21_5_eq_n1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ib_force_disparity1054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rforce_disp1040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rforce_disp1047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rforce_disp1036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rforce_disp1043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni000i1832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni000l1833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni000O1858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni001O1857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0i0O1756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0iOO1706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l1i1681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l1l1682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l1O1707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0O1O1605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rst1030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_tc_range6w7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_txd_extend_tc_range1035w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_txd_extend_tc_range1042w1046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_ni00lO1852w1853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_ni0liO1701w1702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni001l1854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni00lO1852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0iOl1703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0liO1701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni000i : STD_LOGIC; + SIGNAL ni000l : STD_LOGIC; + SIGNAL ni000O : STD_LOGIC; + SIGNAL ni001i : STD_LOGIC; + SIGNAL ni001l : STD_LOGIC; + SIGNAL ni001O : STD_LOGIC; + SIGNAL ni00ii : STD_LOGIC; + SIGNAL ni00il : STD_LOGIC; + SIGNAL ni00iO : STD_LOGIC; + SIGNAL ni00li : STD_LOGIC; + SIGNAL ni00ll : STD_LOGIC; + SIGNAL ni00lO : STD_LOGIC; + SIGNAL ni00Oi : STD_LOGIC; + SIGNAL ni00Ol : STD_LOGIC; + SIGNAL ni00OO : STD_LOGIC; + SIGNAL ni01il : STD_LOGIC; + SIGNAL ni01iO : STD_LOGIC; + SIGNAL ni01li : STD_LOGIC; + SIGNAL ni01ll : STD_LOGIC; + SIGNAL ni01lO : STD_LOGIC; + SIGNAL ni01Oi : STD_LOGIC; + SIGNAL ni01Ol : STD_LOGIC; + SIGNAL ni01OO : STD_LOGIC; + SIGNAL ni0i0i : STD_LOGIC; + SIGNAL ni0i0l : STD_LOGIC; + SIGNAL ni0i0O : STD_LOGIC; + SIGNAL ni0i1i : STD_LOGIC; + SIGNAL ni0i1l : STD_LOGIC; + SIGNAL ni0i1O : STD_LOGIC; + SIGNAL ni0iii : STD_LOGIC; + SIGNAL ni0iil : STD_LOGIC; + SIGNAL ni0iiO : STD_LOGIC; + SIGNAL ni0ili : STD_LOGIC; + SIGNAL ni0ill : STD_LOGIC; + SIGNAL ni0ilO : STD_LOGIC; + SIGNAL ni0iOi : STD_LOGIC; + SIGNAL ni0iOl : STD_LOGIC; + SIGNAL ni0iOO : STD_LOGIC; + SIGNAL ni0l0i : STD_LOGIC; + SIGNAL ni0l0l : STD_LOGIC; + SIGNAL ni0l0O : STD_LOGIC; + SIGNAL ni0l1i : STD_LOGIC; + SIGNAL ni0l1l : STD_LOGIC; + SIGNAL ni0l1O : STD_LOGIC; + SIGNAL ni0lii : STD_LOGIC; + SIGNAL ni0lil : STD_LOGIC; + SIGNAL ni0liO : STD_LOGIC; + SIGNAL ni0lli : STD_LOGIC; + SIGNAL ni0lll : STD_LOGIC; + SIGNAL ni0llO : STD_LOGIC; + SIGNAL ni0lOi : STD_LOGIC; + SIGNAL ni0lOl : STD_LOGIC; + SIGNAL ni0lOO : STD_LOGIC; + SIGNAL ni0O0i : STD_LOGIC; + SIGNAL ni0O1i : STD_LOGIC; + SIGNAL ni0O1l : STD_LOGIC; + SIGNAL ni0O1O : STD_LOGIC; + SIGNAL ni0Oil : STD_LOGIC; + SIGNAL nii00O : STD_LOGIC; + SIGNAL nii1iO : STD_LOGIC; + SIGNAL nii1Ol : STD_LOGIC; + SIGNAL wire_w_tx_ctl_tc_range6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_9_tc_range1037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_txd_extend_tc_range1035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_txd_extend_tc_range1042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_w22w23w(0) <= wire_w22w(0) AND n01il; + wire_w22w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w18w19w(0) AND wire_nii01l8_w_lg_q21w(0); + wire_w35w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w31w34w(0) AND k_det; + wire_w_lg_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w18w19w(0) <= wire_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w18w(0) AND k_det; + wire_w_lg_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w31w34w(0) <= wire_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w31w(0) AND wire_nii1li14_w_lg_q33w(0); + wire_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w18w(0) <= wire_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w(0) AND wire_w_lg_w_tx_ctl_tc_range6w7w(0); + wire_w_lg_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w31w(0) <= wire_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w(0) AND wire_w_lg_w_tx_ctl_tc_range6w7w(0); + wire_w_lg_w_lg_w_lg_d21_5_eq_n1w16w17w(0) <= wire_w_lg_w_lg_d21_5_eq_n1w16w(0) AND ge_xaui_sel; + wire_w_lg_w_lg_w_lg_d21_5_eq_n1w4w5w(0) <= wire_w_lg_w_lg_d21_5_eq_n1w4w(0) AND ge_xaui_sel; + wire_w_lg_w_lg_w_lg_d21_5_eq_n1w29w30w(0) <= wire_w_lg_w_lg_d21_5_eq_n1w29w(0) AND ge_xaui_sel; + wire_w_lg_w_lg_w_lg_ni000i1832w1834w1835w(0) <= wire_w_lg_w_lg_ni000i1832w1834w(0) AND ni00ii; + wire_w_lg_w_lg_w_lg_ni0l1i1681w1683w1684w(0) <= wire_w_lg_w_lg_ni0l1i1681w1683w(0) AND ni0l0i; + wire_w_lg_w_lg_d21_5_eq_n1w16w(0) <= wire_w_lg_d21_5_eq_n1w(0) AND wire_nii00i6_w_lg_q15w(0); + wire_w_lg_w_lg_d21_5_eq_n1w4w(0) <= wire_w_lg_d21_5_eq_n1w(0) AND wire_nii0iO2_w_lg_q3w(0); + wire_w_lg_w_lg_d21_5_eq_n1w29w(0) <= wire_w_lg_d21_5_eq_n1w(0) AND wire_nii1lO12_w_lg_q28w(0); + wire_w_lg_w_lg_ni000i1832w1834w(0) <= wire_w_lg_ni000i1832w(0) AND wire_w_lg_ni000l1833w(0); + wire_w_lg_w_lg_ni0l1i1681w1683w(0) <= wire_w_lg_ni0l1i1681w(0) AND wire_w_lg_ni0l1l1682w(0); + wire_w_lg_d21_5_eq_n1w(0) <= d21_5_eq_n AND d2_2_eq_n; + wire_w_lg_ib_force_disparity1054w(0) <= ib_force_disparity AND wire_w_tx_data_9_tc_range1037w(0); + wire_w_lg_rforce_disp1040w(0) <= rforce_disp AND wire_w_lg_w_txd_extend_tc_range1035w1039w(0); + wire_w_lg_rforce_disp1047w(0) <= rforce_disp AND wire_w_lg_w_txd_extend_tc_range1042w1046w(0); + wire_w_lg_rforce_disp1036w(0) <= rforce_disp AND wire_w_txd_extend_tc_range1035w(0); + wire_w_lg_rforce_disp1043w(0) <= rforce_disp AND wire_w_txd_extend_tc_range1042w(0); + wire_w_lg_ni000i1832w(0) <= NOT ni000i; + wire_w_lg_ni000l1833w(0) <= NOT ni000l; + wire_w_lg_ni000O1858w(0) <= NOT ni000O; + wire_w_lg_ni001O1857w(0) <= NOT ni001O; + wire_w_lg_ni0i0O1756w(0) <= NOT ni0i0O; + wire_w_lg_ni0iOO1706w(0) <= NOT ni0iOO; + wire_w_lg_ni0l1i1681w(0) <= NOT ni0l1i; + wire_w_lg_ni0l1l1682w(0) <= NOT ni0l1l; + wire_w_lg_ni0l1O1707w(0) <= NOT ni0l1O; + wire_w_lg_ni0O1O1605w(0) <= NOT ni0O1O; + wire_w_lg_rst1030w(0) <= NOT rst; + wire_w_lg_w_tx_ctl_tc_range6w7w(0) <= NOT wire_w_tx_ctl_tc_range6w(0); + wire_w_lg_w_txd_extend_tc_range1035w1039w(0) <= NOT wire_w_txd_extend_tc_range1035w(0); + wire_w_lg_w_txd_extend_tc_range1042w1046w(0) <= NOT wire_w_txd_extend_tc_range1042w(0); + wire_w_lg_w_lg_ni00lO1852w1853w(0) <= wire_w_lg_ni00lO1852w(0) OR ni001i; + wire_w_lg_w_lg_ni0liO1701w1702w(0) <= wire_w_lg_ni0liO1701w(0) OR ni0iOi; + wire_w_lg_ni001l1854w(0) <= ni001l OR wire_w_lg_w_lg_ni00lO1852w1853w(0); + wire_w_lg_ni00lO1852w(0) <= ni00lO OR wire_n1lO_w_lg_w_lg_dataout1788w1851w(0); + wire_w_lg_ni0iOl1703w(0) <= ni0iOl OR wire_w_lg_w_lg_ni0liO1701w1702w(0); + wire_w_lg_ni0liO1701w(0) <= ni0liO OR wire_n00l_w_lg_w_lg_dataout1637w1700w(0); + disp_out_3b <= ( wire_nlli1i_dataout & wire_nl010O_dataout); + ni000i <= ((((wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_dataout AND ni01ll)) OR wire_n1ll_w_lg_dataout1902w(0)) OR wire_n1ll_w_lg_dataout1796w(0)) OR wire_n1ll_w_lg_dataout1799w(0)); + ni000l <= ((((((wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_w_lg_dataout1770w(0) AND wire_n1iO_w_lg_dataout1818w(0))) OR (wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_dataout AND ni01Ol))) OR (wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_dataout AND ni01Oi))) OR wire_n1ll_w_lg_dataout1885w(0)) OR wire_n1ll_w_lg_dataout1888w(0)) OR wire_n1ll_w_lg_dataout1891w(0)); + ni000O <= (ni00il OR (wire_n1lO_dataout AND ni00ii)); + ni001i <= (wire_n1lO_dataout AND ((wire_n1ll_dataout AND ni00iO) OR ni000i)); + ni001l <= (wire_nl1iii_dataout AND ni000l); + ni001O <= (wire_n1lO_w_lg_w_lg_w_lg_dataout1788w1830w1831w(0) OR wire_n1lO_w_lg_dataout1836w(0)); + ni00ii <= (wire_n1ll_w_lg_dataout1768w(0) OR wire_n1li_w_lg_dataout1828w(0)); + ni00il <= (wire_n1lO_w_lg_dataout1788w(0) AND ni00iO); + ni00iO <= ((((wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_w_lg_dataout1770w(0) AND wire_n1iO_w_lg_w_lg_dataout1771w1772w(0))) OR (wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_w_lg_dataout1770w(0) AND wire_n1iO_w_lg_dataout1776w(0)))) OR (wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_dataout AND ni01lO))) OR wire_n1ll_w_lg_dataout1897w(0)); + ni00li <= (wire_n1ll_dataout AND wire_n1li_w_lg_dataout1839w(0)); + ni00ll <= (wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_w_lg_dataout1770w(0) AND wire_n1iO_w_lg_w_lg_dataout1771w1817w(0))); + ni00lO <= (ni00li OR ni00ll); + ni00Oi <= ((wire_n1lO_w_lg_w_lg_dataout1870w1871w(0) AND wire_n1iO_w_lg_dataout1771w(0)) AND wire_n1il_w_lg_dataout1775w(0)); + ni00Ol <= wire_n1iO_w_lg_dataout1818w(0); + ni00OO <= wire_n1iO_w_lg_w_lg_dataout1771w1817w(0); + ni01il <= ((((((((((((((wire_nili1O_o(15) OR wire_nili1O_o(14)) OR wire_nili1O_o(13)) OR wire_nili1O_o(12)) OR wire_nili1O_o(11)) OR wire_nili1O_o(10)) OR wire_nili1O_o(9)) OR wire_nili1O_o(8)) OR wire_nili1O_o(7)) OR wire_nili1O_o(6)) OR wire_nili1O_o(5)) OR wire_nili1O_o(4)) OR wire_nili1O_o(3)) OR wire_nili1O_o(2)) OR wire_nili1O_o(1)); + ni01iO <= ((((((wire_nillli_o(15) OR wire_nillli_o(14)) OR wire_nillli_o(13)) OR wire_nillli_o(12)) OR wire_nillli_o(11)) OR wire_nillli_o(10)) OR wire_nillli_o(0)); + ni01li <= ((((((wire_nillli_o(7) OR wire_nillli_o(6)) OR wire_nillli_o(5)) OR wire_nillli_o(4)) OR wire_nillli_o(3)) OR wire_nillli_o(2)) OR wire_nillli_o(1)); + ni01ll <= wire_n1iO_w_lg_dataout1818w(0); + ni01lO <= wire_n1iO_w_lg_w_lg_dataout1771w1817w(0); + ni01Oi <= wire_n1iO_w_lg_dataout1776w(0); + ni01Ol <= wire_n1iO_w_lg_w_lg_dataout1771w1772w(0); + ni01OO <= (wire_n1ll_w_lg_w1846w1847w(0) XOR (wire_n0O1l_w_lg_dataout1848w(0) AND wire_w_lg_ni001l1854w(0))); + ni0i0i <= (wire_niOlOi_w_lg_w_lg_w_lg_dataout1755w1758w1759w(0) XOR wire_niOlOi_w_lg_w_lg_dataout1755w1760w(0)); + ni0i0l <= (wire_n1Ol_dataout AND wire_n1Oi_dataout); + ni0i0O <= (ni0i0l OR ni0i1l); + ni0i1i <= (wire_n1OO_w_lg_dataout1763w(0) AND ni0i1l); + ni0i1l <= (wire_n1Ol_w_lg_dataout1767w(0) AND wire_n1Oi_w_lg_dataout1814w(0)); + ni0i1O <= (wire_n1OO_dataout AND (wire_n1Ol_dataout AND (wire_n1Oi_dataout AND (((wire_niOlOi_w_lg_dataout1755w(0) AND (wire_n1lO_w_lg_dataout1769w(0) AND ((((wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_w_lg_dataout1770w(0) AND wire_n1iO_w_lg_w_lg_dataout1771w1772w(0))) OR (wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_w_lg_dataout1770w(0) AND wire_n1iO_w_lg_dataout1776w(0)))) OR (wire_n1ll_w_lg_dataout1768w(0) AND (wire_n1li_dataout AND ni00OO))) OR wire_n1ll_w_lg_dataout1784w(0)))) OR wire_niOlOi_w_lg_dataout1802w(0)) OR wire_n1OO_w_lg_dataout1806w(0))))); + ni0iii <= (wire_nil_dataout AND ni00Oi); + ni0iil <= wire_n01l_w_lg_dataout1667w(0); + ni0iiO <= wire_n01l_w_lg_w_lg_dataout1620w1666w(0); + ni0ili <= wire_n01l_w_lg_dataout1625w(0); + ni0ill <= wire_n01l_w_lg_w_lg_dataout1620w1621w(0); + ni0ilO <= (wire_n00i_w_lg_w1695w1696w(0) XOR (wire_n0O1O_w_lg_dataout1697w(0) AND wire_w_lg_ni0iOl1703w(0))); + ni0iOi <= (wire_n00l_dataout AND ((wire_n00i_dataout AND ni0l0O) OR ni0l1i)); + ni0iOl <= (wire_nliO1l_dataout AND ni0l1l); + ni0iOO <= (wire_n00l_w_lg_w_lg_w_lg_dataout1637w1679w1680w(0) OR wire_n00l_w_lg_dataout1685w(0)); + ni0l0i <= (wire_n00i_w_lg_dataout1617w(0) OR wire_n01O_w_lg_dataout1677w(0)); + ni0l0l <= (wire_n00l_w_lg_dataout1637w(0) AND ni0l0O); + ni0l0O <= ((((wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_w_lg_dataout1619w(0) AND wire_n01l_w_lg_w_lg_dataout1620w1621w(0))) OR (wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_w_lg_dataout1619w(0) AND wire_n01l_w_lg_dataout1625w(0)))) OR (wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_dataout AND ni0iiO))) OR wire_n00i_w_lg_dataout1746w(0)); + ni0l1i <= ((((wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_dataout AND ni0iil)) OR wire_n00i_w_lg_dataout1751w(0)) OR wire_n00i_w_lg_dataout1645w(0)) OR wire_n00i_w_lg_dataout1648w(0)); + ni0l1l <= ((((((wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_w_lg_dataout1619w(0) AND wire_n01l_w_lg_dataout1667w(0))) OR (wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_dataout AND ni0ill))) OR (wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_dataout AND ni0ili))) OR wire_n00i_w_lg_dataout1734w(0)) OR wire_n00i_w_lg_dataout1737w(0)) OR wire_n00i_w_lg_dataout1740w(0)); + ni0l1O <= (ni0l0l OR (wire_n00l_dataout AND ni0l0i)); + ni0lii <= (wire_n00i_dataout AND wire_n01O_w_lg_dataout1688w(0)); + ni0lil <= (wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_w_lg_dataout1619w(0) AND wire_n01l_w_lg_w_lg_dataout1620w1666w(0))); + ni0liO <= (ni0lii OR ni0lil); + ni0lli <= ((wire_n00l_w_lg_w_lg_dataout1719w1720w(0) AND wire_n01l_w_lg_dataout1620w(0)) AND wire_n01i_w_lg_dataout1624w(0)); + ni0lll <= wire_n01l_w_lg_dataout1667w(0); + ni0llO <= wire_n01l_w_lg_w_lg_dataout1620w1666w(0); + ni0lOi <= (wire_n0il_w_lg_dataout1612w(0) AND ni0lOl); + ni0lOl <= (wire_n0ii_w_lg_dataout1616w(0) AND wire_n00O_w_lg_dataout1663w(0)); + ni0lOO <= (wire_n0il_dataout AND (wire_n0ii_dataout AND (wire_n00O_dataout AND (((wire_nli1il_w_lg_dataout1604w(0) AND (wire_n00l_w_lg_dataout1618w(0) AND ((((wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_w_lg_dataout1619w(0) AND wire_n01l_w_lg_w_lg_dataout1620w1621w(0))) OR (wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_w_lg_dataout1619w(0) AND wire_n01l_w_lg_dataout1625w(0)))) OR (wire_n00i_w_lg_dataout1617w(0) AND (wire_n01O_dataout AND ni0llO))) OR wire_n00i_w_lg_dataout1633w(0)))) OR wire_nli1il_w_lg_dataout1651w(0)) OR wire_n0il_w_lg_dataout1655w(0))))); + ni0O0i <= (wire_niO_dataout AND ni0lli); + ni0O1i <= (wire_nli1il_w_lg_w_lg_w_lg_dataout1604w1607w1608w(0) XOR wire_nli1il_w_lg_w_lg_dataout1604w1609w(0)); + ni0O1l <= (wire_n0ii_dataout AND wire_n00O_dataout); + ni0O1O <= (ni0O1l OR ni0lOl); + ni0Oil <= '1'; + nii00O <= (((wire_w_lg_w_lg_w_lg_d21_5_eq_n1w4w5w(0) AND wire_w_lg_w_tx_ctl_tc_range6w7w(0)) AND (nii0ii4 XOR nii0ii3)) AND k_det); + nii1iO <= (wire_w35w(0) AND wire_ni0Oi_w_lg_n01il36w(0)); + nii1Ol <= (wire_w_lg_w22w23w(0) AND (nii1OO10 XOR nii1OO9)); + pudr <= ( nii1i & ni0Ol & ni0lO & ni0ll & ni0li & ni0iO & ni0il & ni0ii & ni00O & ni00l & ni00i & ni01O & ni01l & ni01i & ni1OO & ni1Ol & ni1Oi & ni1lO & ni1ll & n0lOi); + tx_ctl_pre_en <= ( n01OO & n01Ol); + tx_data_9_pre_en <= ( n01Oi & n01lO); + tx_data_pre_en <= ( n0i1i & n00OO & n00Ol & n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n000O & n000l & n000i & n001O & n001l & n001i); + txlp20b <= ( n0l0O & n0l0l & n0l0i & n0l1O & n0l1l & n0l1i & n0iOO & n0iOl & n0iOi & n0ilO & n0ill & n0ili & n0iiO & n0iil & n0iii & n0i0O & n0i0l & n0i0i & n0i1O & n0i1l); + wire_w_tx_ctl_tc_range6w(0) <= tx_ctl_tc(0); + wire_w_tx_data_9_tc_range1037w(0) <= tx_data_9_tc(0); + wire_w_txd_extend_tc_range1035w(0) <= txd_extend_tc(0); + wire_w_txd_extend_tc_range1042w(0) <= txd_extend_tc(1); + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0O0l49 <= ni0O0l50; + END IF; + if (now = 0 ns) then + ni0O0l49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0O0l50 <= ni0O0l49; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0O0O47 <= ni0O0O48; + END IF; + if (now = 0 ns) then + ni0O0O47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0O0O48 <= ni0O0O47; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0Oii45 <= ni0Oii46; + END IF; + if (now = 0 ns) then + ni0Oii45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0Oii46 <= ni0Oii45; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OiO43 <= ni0OiO44; + END IF; + if (now = 0 ns) then + ni0OiO43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OiO44 <= ni0OiO43; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0Oli41 <= ni0Oli42; + END IF; + if (now = 0 ns) then + ni0Oli41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0Oli42 <= ni0Oli41; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0Oll39 <= ni0Oll40; + END IF; + if (now = 0 ns) then + ni0Oll39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0Oll40 <= ni0Oll39; + END IF; + END PROCESS; + wire_ni0Oll40_w_lg_w_lg_q202w203w(0) <= wire_ni0Oll40_w_lg_q202w(0) AND wire_n010i_w_lg_o200w(0); + wire_ni0Oll40_w_lg_q202w(0) <= ni0Oll40 XOR ni0Oll39; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OlO37 <= ni0OlO38; + END IF; + if (now = 0 ns) then + ni0OlO37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OlO38 <= ni0OlO37; + END IF; + END PROCESS; + wire_ni0OlO38_w_lg_w_lg_q195w196w(0) <= wire_ni0OlO38_w_lg_q195w(0) AND wire_n010i_o; + wire_ni0OlO38_w_lg_q195w(0) <= ni0OlO38 XOR ni0OlO37; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OOi35 <= ni0OOi36; + END IF; + if (now = 0 ns) then + ni0OOi35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OOi36 <= ni0OOi35; + END IF; + END PROCESS; + wire_ni0OOi36_w_lg_w_lg_q187w189w(0) <= wire_ni0OOi36_w_lg_q187w(0) AND wire_n010l_w_lg_o188w(0); + wire_ni0OOi36_w_lg_q187w(0) <= ni0OOi36 XOR ni0OOi35; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OOl33 <= ni0OOl34; + END IF; + if (now = 0 ns) then + ni0OOl33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OOl34 <= ni0OOl33; + END IF; + END PROCESS; + wire_ni0OOl34_w_lg_w_lg_q160w161w(0) <= wire_ni0OOl34_w_lg_q160w(0) AND wire_n1O1O_w_lg_o108w(0); + wire_ni0OOl34_w_lg_q160w(0) <= ni0OOl34 XOR ni0OOl33; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OOO31 <= ni0OOO32; + END IF; + if (now = 0 ns) then + ni0OOO31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN ni0OOO32 <= ni0OOO31; + END IF; + END PROCESS; + wire_ni0OOO32_w_lg_w_lg_q139w140w(0) <= wire_ni0OOO32_w_lg_q139w(0) AND wire_n1O0l_o; + wire_ni0OOO32_w_lg_q139w(0) <= ni0OOO32 XOR ni0OOO31; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii00i5 <= nii00i6; + END IF; + if (now = 0 ns) then + nii00i5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii00i6 <= nii00i5; + END IF; + END PROCESS; + wire_nii00i6_w_lg_q15w(0) <= nii00i6 XOR nii00i5; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii01l7 <= nii01l8; + END IF; + if (now = 0 ns) then + nii01l7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii01l8 <= nii01l7; + END IF; + END PROCESS; + wire_nii01l8_w_lg_q21w(0) <= nii01l8 XOR nii01l7; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii0ii3 <= nii0ii4; + END IF; + if (now = 0 ns) then + nii0ii3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii0ii4 <= nii0ii3; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii0iO1 <= nii0iO2; + END IF; + if (now = 0 ns) then + nii0iO1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii0iO2 <= nii0iO1; + END IF; + END PROCESS; + wire_nii0iO2_w_lg_q3w(0) <= nii0iO2 XOR nii0iO1; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii10i23 <= nii10i24; + END IF; + if (now = 0 ns) then + nii10i23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii10i24 <= nii10i23; + END IF; + END PROCESS; + wire_nii10i24_w_lg_w_lg_q100w101w(0) <= wire_nii10i24_w_lg_q100w(0) AND n0lll; + wire_nii10i24_w_lg_q100w(0) <= nii10i24 XOR nii10i23; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii10l21 <= nii10l22; + END IF; + if (now = 0 ns) then + nii10l21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii10l22 <= nii10l21; + END IF; + END PROCESS; + wire_nii10l22_w_lg_w_lg_q86w87w(0) <= wire_nii10l22_w_lg_q86w(0) AND n0liO; + wire_nii10l22_w_lg_q86w(0) <= nii10l22 XOR nii10l21; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii10O19 <= nii10O20; + END IF; + if (now = 0 ns) then + nii10O19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii10O20 <= nii10O19; + END IF; + END PROCESS; + wire_nii10O20_w_lg_w_lg_q83w84w(0) <= wire_nii10O20_w_lg_q83w(0) AND wire_n1Oli_w_lg_o81w(0); + wire_nii10O20_w_lg_q83w(0) <= nii10O20 XOR nii10O19; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii11i29 <= nii11i30; + END IF; + if (now = 0 ns) then + nii11i29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii11i30 <= nii11i29; + END IF; + END PROCESS; + wire_nii11i30_w_lg_w_lg_q132w134w(0) <= wire_nii11i30_w_lg_q132w(0) AND wire_n1O0l_w_lg_o133w(0); + wire_nii11i30_w_lg_q132w(0) <= nii11i30 XOR nii11i29; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii11l27 <= nii11l28; + END IF; + if (now = 0 ns) then + nii11l27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii11l28 <= nii11l27; + END IF; + END PROCESS; + wire_nii11l28_w_lg_w_lg_q118w120w(0) <= wire_nii11l28_w_lg_q118w(0) AND wire_n1Oii_w_lg_o119w(0); + wire_nii11l28_w_lg_q118w(0) <= nii11l28 XOR nii11l27; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii11O25 <= nii11O26; + END IF; + if (now = 0 ns) then + nii11O25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii11O26 <= nii11O25; + END IF; + END PROCESS; + wire_nii11O26_w_lg_w_lg_q115w116w(0) <= wire_nii11O26_w_lg_q115w(0) AND wire_n1O0i_o; + wire_nii11O26_w_lg_q115w(0) <= nii11O26 XOR nii11O25; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1ii17 <= nii1ii18; + END IF; + if (now = 0 ns) then + nii1ii17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1ii18 <= nii1ii17; + END IF; + END PROCESS; + wire_nii1ii18_w_lg_w_lg_q75w76w(0) <= wire_nii1ii18_w_lg_q75w(0) AND n0lll; + wire_nii1ii18_w_lg_q75w(0) <= nii1ii18 XOR nii1ii17; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1il15 <= nii1il16; + END IF; + if (now = 0 ns) then + nii1il15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1il16 <= nii1il15; + END IF; + END PROCESS; + wire_nii1il16_w_lg_w_lg_q67w68w(0) <= wire_nii1il16_w_lg_q67w(0) AND wire_n1Oll_o; + wire_nii1il16_w_lg_q67w(0) <= nii1il16 XOR nii1il15; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1li13 <= nii1li14; + END IF; + if (now = 0 ns) then + nii1li13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1li14 <= nii1li13; + END IF; + END PROCESS; + wire_nii1li14_w_lg_q33w(0) <= nii1li14 XOR nii1li13; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1lO11 <= nii1lO12; + END IF; + if (now = 0 ns) then + nii1lO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1lO12 <= nii1lO11; + END IF; + END PROCESS; + wire_nii1lO12_w_lg_q28w(0) <= nii1lO12 XOR nii1lO11; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1OO10 <= nii1OO9; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN nii1OO9 <= nii1OO10; + END IF; + if (now = 0 ns) then + nii1OO9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk, wire_n01iO_PRN, rst) + BEGIN + IF (wire_n01iO_PRN = '0') THEN + n01li <= '1'; + ELSIF (rst = '1') THEN + n01li <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + IF (wire_n01iO_ENA = '1') THEN + n01li <= ni0Oil; + END IF; + END IF; + END PROCESS; + wire_n01iO_ENA <= (wire_w_lg_ib_force_disparity1054w(0) AND wire_n01iO_w_lg_n01li1049w(0)); + wire_n01iO_PRN <= (ni0O0l50 XOR ni0O0l49); + wire_n01iO_w_lg_n01li1049w(0) <= NOT n01li; + PROCESS (clk, wire_ni0Oi_PRN, wire_ni0Oi_CLRN) + BEGIN + IF (wire_ni0Oi_PRN = '0') THEN + n000i <= '1'; + n000l <= '1'; + n000O <= '1'; + n001i <= '1'; + n001l <= '1'; + n001O <= '1'; + n00ii <= '1'; + n00il <= '1'; + n00iO <= '1'; + n00li <= '1'; + n00ll <= '1'; + n00lO <= '1'; + n00Oi <= '1'; + n00Ol <= '1'; + n00OO <= '1'; + n01ii <= '1'; + n01il <= '1'; + n01lO <= '1'; + n01Oi <= '1'; + n01Ol <= '1'; + n01OO <= '1'; + n0i1i <= '1'; + n0i1l <= '1'; + n0i1O <= '1'; + n0iiO <= '1'; + n0ill <= '1'; + n0iOl <= '1'; + n0iOO <= '1'; + n0l0l <= '1'; + n0l1i <= '1'; + n0l1l <= '1'; + n0l1O <= '1'; + n0lii <= '1'; + n0lil <= '1'; + n0liO <= '1'; + n0lli <= '1'; + n0lll <= '1'; + n0llO <= '1'; + n0lOi <= '1'; + ni00i <= '1'; + ni01l <= '1'; + ni0ii <= '1'; + ni0il <= '1'; + ni0iO <= '1'; + ni0li <= '1'; + ni0ll <= '1'; + ni0Ol <= '1'; + ni1li <= '1'; + ni1ll <= '1'; + nii0Oi <= '1'; + nii0Ol <= '1'; + nii0OO <= '1'; + niii0i <= '1'; + niii0l <= '1'; + niii0O <= '1'; + niii1i <= '1'; + niii1l <= '1'; + niii1O <= '1'; + niiiii <= '1'; + niiiil <= '1'; + niiiiO <= '1'; + niiili <= '1'; + niiill <= '1'; + niiilO <= '1'; + niiiOi <= '1'; + niiiOl <= '1'; + niiiOO <= '1'; + niil1i <= '1'; + ELSIF (wire_ni0Oi_CLRN = '0') THEN + n000i <= '0'; + n000l <= '0'; + n000O <= '0'; + n001i <= '0'; + n001l <= '0'; + n001O <= '0'; + n00ii <= '0'; + n00il <= '0'; + n00iO <= '0'; + n00li <= '0'; + n00ll <= '0'; + n00lO <= '0'; + n00Oi <= '0'; + n00Ol <= '0'; + n00OO <= '0'; + n01ii <= '0'; + n01il <= '0'; + n01lO <= '0'; + n01Oi <= '0'; + n01Ol <= '0'; + n01OO <= '0'; + n0i1i <= '0'; + n0i1l <= '0'; + n0i1O <= '0'; + n0iiO <= '0'; + n0ill <= '0'; + n0iOl <= '0'; + n0iOO <= '0'; + n0l0l <= '0'; + n0l1i <= '0'; + n0l1l <= '0'; + n0l1O <= '0'; + n0lii <= '0'; + n0lil <= '0'; + n0liO <= '0'; + n0lli <= '0'; + n0lll <= '0'; + n0llO <= '0'; + n0lOi <= '0'; + ni00i <= '0'; + ni01l <= '0'; + ni0ii <= '0'; + ni0il <= '0'; + ni0iO <= '0'; + ni0li <= '0'; + ni0ll <= '0'; + ni0Ol <= '0'; + ni1li <= '0'; + ni1ll <= '0'; + nii0Oi <= '0'; + nii0Ol <= '0'; + nii0OO <= '0'; + niii0i <= '0'; + niii0l <= '0'; + niii0O <= '0'; + niii1i <= '0'; + niii1l <= '0'; + niii1O <= '0'; + niiiii <= '0'; + niiiil <= '0'; + niiiiO <= '0'; + niiili <= '0'; + niiill <= '0'; + niiilO <= '0'; + niiiOi <= '0'; + niiiOl <= '0'; + niiiOO <= '0'; + niil1i <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + n000i <= tx_data_tc(3); + n000l <= tx_data_tc(4); + n000O <= tx_data_tc(5); + n001i <= tx_data_tc(0); + n001l <= tx_data_tc(1); + n001O <= tx_data_tc(2); + n00ii <= tx_data_tc(6); + n00il <= tx_data_tc(7); + n00iO <= tx_data_tc(8); + n00li <= tx_data_tc(9); + n00ll <= tx_data_tc(10); + n00lO <= tx_data_tc(11); + n00Oi <= tx_data_tc(12); + n00Ol <= tx_data_tc(13); + n00OO <= tx_data_tc(14); + n01ii <= rev_loopbk; + n01il <= wire_n01ll_dataout; + n01lO <= tx_data_9_tc(0); + n01Oi <= tx_data_9_tc(1); + n01Ol <= tx_ctl_tc(0); + n01OO <= tx_ctl_tc(1); + n0i1i <= tx_data_tc(15); + n0i1l <= n0lOi; + n0i1O <= ni1ll; + n0iiO <= ni01l; + n0ill <= ni00i; + n0iOl <= ni0ii; + n0iOO <= ni0il; + n0l0l <= ni0Ol; + n0l1i <= ni0iO; + n0l1l <= ni0li; + n0l1O <= ni0ll; + n0lii <= n0lil; + n0lil <= rensymswap_tx; + n0liO <= n0lli; + n0lli <= renbitrev_tx; + n0lll <= n0llO; + n0llO <= (renpolinv_tx AND enpolinv_tx); + n0lOi <= wire_nii1l_dataout; + ni00i <= wire_niill_dataout; + ni01l <= wire_niiiO_dataout; + ni0ii <= wire_niiOl_dataout; + ni0il <= wire_niiOO_dataout; + ni0iO <= wire_nil1i_dataout; + ni0li <= wire_nil1l_dataout; + ni0ll <= wire_nil1O_dataout; + ni0Ol <= wire_nil0l_dataout; + ni1li <= n01ii; + ni1ll <= wire_nii1O_dataout; + nii0Oi <= wire_niliO_o; + nii0Ol <= wire_nilli_o; + nii0OO <= wire_nilll_o; + niii0i <= wire_nilOO_o; + niii0l <= wire_niO1i_o; + niii0O <= wire_niO1l_o; + niii1i <= wire_nillO_o; + niii1l <= wire_nilOi_o; + niii1O <= wire_nilOl_o; + niiiii <= wire_niO1O_o; + niiiil <= wire_niO0i_o; + niiiiO <= wire_niO0l_o; + niiili <= wire_niO0O_o; + niiill <= wire_niOii_o; + niiilO <= wire_niOil_o; + niiiOi <= wire_niOiO_o; + niiiOl <= wire_niOli_o; + niiiOO <= wire_niOll_o; + niil1i <= wire_nilil_o; + END IF; + END PROCESS; + wire_ni0Oi_CLRN <= ((ni0Oii46 XOR ni0Oii45) AND wire_w_lg_rst1030w(0)); + wire_ni0Oi_PRN <= (ni0O0O48 XOR ni0O0O47); + wire_ni0Oi_w_lg_n01il36w(0) <= NOT n01il; + PROCESS (clk, wire_ni0OO_PRN, wire_ni0OO_CLRN) + BEGIN + IF (wire_ni0OO_PRN = '0') THEN + n0i0i <= '1'; + n0i0l <= '1'; + n0i0O <= '1'; + n0iii <= '1'; + n0iil <= '1'; + n0ili <= '1'; + n0ilO <= '1'; + n0iOi <= '1'; + n0l0i <= '1'; + n0l0O <= '1'; + ni00l <= '1'; + ni00O <= '1'; + ni01i <= '1'; + ni01O <= '1'; + ni0lO <= '1'; + ni1lO <= '1'; + ni1Oi <= '1'; + ni1Ol <= '1'; + ni1OO <= '1'; + nii1i <= '1'; + ELSIF (wire_ni0OO_CLRN = '0') THEN + n0i0i <= '0'; + n0i0l <= '0'; + n0i0O <= '0'; + n0iii <= '0'; + n0iil <= '0'; + n0ili <= '0'; + n0ilO <= '0'; + n0iOi <= '0'; + n0l0i <= '0'; + n0l0O <= '0'; + ni00l <= '0'; + ni00O <= '0'; + ni01i <= '0'; + ni01O <= '0'; + ni0lO <= '0'; + ni1lO <= '0'; + ni1Oi <= '0'; + ni1Ol <= '0'; + ni1OO <= '0'; + nii1i <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + n0i0i <= ni1lO; + n0i0l <= ni1Oi; + n0i0O <= ni1Ol; + n0iii <= ni1OO; + n0iil <= ni01i; + n0ili <= ni01O; + n0ilO <= ni00l; + n0iOi <= ni00O; + n0l0i <= ni0lO; + n0l0O <= nii1i; + ni00l <= wire_niilO_dataout; + ni00O <= wire_niiOi_dataout; + ni01i <= wire_niiil_dataout; + ni01O <= wire_niili_dataout; + ni0lO <= wire_nil0i_dataout; + ni1lO <= wire_nii0i_dataout; + ni1Oi <= wire_nii0l_dataout; + ni1Ol <= wire_nii0O_dataout; + ni1OO <= wire_niiii_dataout; + nii1i <= wire_nil0O_dataout; + END IF; + if (now = 0 ns) then + n0i0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0ili <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0ilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0l0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0l0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni00l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni01i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni01O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni0lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii1i <= '1' after 1 ps; + end if; + END PROCESS; + wire_ni0OO_CLRN <= (ni0Oli42 XOR ni0Oli41); + wire_ni0OO_PRN <= ((ni0OiO44 XOR ni0OiO43) AND wire_w_lg_rst1030w(0)); + wire_n00i_dataout <= tx_data_tc(11) WHEN cascaded_8b10b_en = '1' ELSE wire_ni0l_dataout; + wire_n00i_w_lg_w_lg_dataout1617w1689w(0) <= wire_n00i_w_lg_dataout1617w(0) AND wire_n01O_w_lg_dataout1688w(0); + wire_n00i_w_lg_w_lg_dataout1617w1640w(0) <= wire_n00i_w_lg_dataout1617w(0) AND wire_n01O_w_lg_dataout1639w(0); + wire_n00i_w_lg_w_lg_dataout1617w1698w(0) <= wire_n00i_w_lg_dataout1617w(0) AND ni0l1i; + wire_n00i_w_lg_dataout1751w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_w_lg_dataout1619w1750w(0); + wire_n00i_w_lg_dataout1746w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_w_lg_dataout1619w1745w(0); + wire_n00i_w_lg_dataout1737w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_w_lg_dataout1619w1736w(0); + wire_n00i_w_lg_dataout1734w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_w_lg_dataout1619w1733w(0); + wire_n00i_w_lg_dataout1642w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_w_lg_dataout1619w1641w(0); + wire_n00i_w_lg_dataout1633w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_w_lg_dataout1619w1632w(0); + wire_n00i_w_lg_dataout1740w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_dataout1739w(0); + wire_n00i_w_lg_dataout1645w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_dataout1644w(0); + wire_n00i_w_lg_dataout1648w(0) <= wire_n00i_dataout AND wire_n01O_w_lg_dataout1647w(0); + wire_n00i_w_lg_dataout1617w(0) <= NOT wire_n00i_dataout; + wire_n00i_w_lg_w_lg_w_lg_dataout1617w1689w1691w(0) <= wire_n00i_w_lg_w_lg_dataout1617w1689w(0) OR wire_n00l_w_lg_dataout1690w(0); + wire_n00i_w_lg_w_lg_w_lg_dataout1617w1640w1643w(0) <= wire_n00i_w_lg_w_lg_dataout1617w1640w(0) OR wire_n00i_w_lg_dataout1642w(0); + wire_n00i_w_lg_w_lg_w_lg_dataout1617w1698w1699w(0) <= wire_n00i_w_lg_w_lg_dataout1617w1698w(0) OR ni0l0O; + wire_n00i_w_lg_w_lg_w_lg_w_lg_dataout1617w1689w1691w1693w(0) <= wire_n00i_w_lg_w_lg_w_lg_dataout1617w1689w1691w(0) OR wire_n00l_w_lg_dataout1692w(0); + wire_n00i_w_lg_w_lg_w_lg_w_lg_dataout1617w1640w1643w1646w(0) <= wire_n00i_w_lg_w_lg_w_lg_dataout1617w1640w1643w(0) OR wire_n00i_w_lg_dataout1645w(0); + wire_n00i_w1695w(0) <= wire_n00i_w_lg_w_lg_w_lg_w_lg_dataout1617w1689w1691w1693w(0) OR wire_n00l_w_lg_dataout1694w(0); + wire_n00i_w1649w(0) <= wire_n00i_w_lg_w_lg_w_lg_w_lg_dataout1617w1640w1643w1646w(0) OR wire_n00i_w_lg_dataout1648w(0); + wire_n00i_w_lg_w1695w1696w(0) <= wire_n00i_w1695w(0) OR ni0iOl; + wire_n00l_dataout <= tx_data_tc(12) WHEN cascaded_8b10b_en = '1' ELSE wire_ni0O_dataout; + wire_n00l_w_lg_w_lg_w_lg_dataout1637w1638w1650w(0) <= wire_n00l_w_lg_w_lg_dataout1637w1638w(0) AND wire_n00i_w1649w(0); + wire_n00l_w_lg_w_lg_dataout1719w1720w(0) <= wire_n00l_w_lg_dataout1719w(0) AND wire_n01O_dataout; + wire_n00l_w_lg_w_lg_dataout1637w1700w(0) <= wire_n00l_w_lg_dataout1637w(0) AND wire_n00i_w_lg_w_lg_w_lg_dataout1617w1698w1699w(0); + wire_n00l_w_lg_w_lg_dataout1637w1638w(0) <= wire_n00l_w_lg_dataout1637w(0) AND wire_n00i_dataout; + wire_n00l_w_lg_w_lg_w_lg_dataout1637w1679w1680w(0) <= wire_n00l_w_lg_w_lg_dataout1637w1679w(0) AND ni0l1l; + wire_n00l_w_lg_dataout1685w(0) <= wire_n00l_dataout AND wire_w_lg_w_lg_w_lg_ni0l1i1681w1683w1684w(0); + wire_n00l_w_lg_dataout1618w(0) <= wire_n00l_dataout AND wire_n00i_w_lg_dataout1617w(0); + wire_n00l_w_lg_dataout1719w(0) <= wire_n00l_dataout AND wire_n00i_dataout; + wire_n00l_w_lg_dataout1694w(0) <= wire_n00l_dataout AND ni0l1i; + wire_n00l_w_lg_dataout1692w(0) <= wire_n00l_dataout AND ni0lii; + wire_n00l_w_lg_dataout1690w(0) <= wire_n00l_dataout AND ni0lil; + wire_n00l_w_lg_dataout1637w(0) <= NOT wire_n00l_dataout; + wire_n00l_w_lg_w_lg_dataout1637w1679w(0) <= wire_n00l_w_lg_dataout1637w(0) OR wire_nliO1l_dataout; + wire_n00O_dataout <= tx_data_tc(13) WHEN cascaded_8b10b_en = '1' ELSE wire_niii_dataout; + wire_n00O_w_lg_dataout1663w(0) <= NOT wire_n00O_dataout; + wire_n01i_dataout <= tx_data_tc(8) WHEN cascaded_8b10b_en = '1' ELSE wire_ni1l_dataout; + wire_n01i_w_lg_dataout1624w(0) <= NOT wire_n01i_dataout; + wire_n01l_dataout <= tx_data_tc(9) WHEN cascaded_8b10b_en = '1' ELSE wire_ni1O_dataout; + wire_n01l_w_lg_w_lg_dataout1620w1666w(0) <= wire_n01l_w_lg_dataout1620w(0) AND wire_n01i_w_lg_dataout1624w(0); + wire_n01l_w_lg_w_lg_dataout1620w1621w(0) <= wire_n01l_w_lg_dataout1620w(0) AND wire_n01i_dataout; + wire_n01l_w_lg_dataout1625w(0) <= wire_n01l_dataout AND wire_n01i_w_lg_dataout1624w(0); + wire_n01l_w_lg_dataout1667w(0) <= wire_n01l_dataout AND wire_n01i_dataout; + wire_n01l_w_lg_dataout1620w(0) <= NOT wire_n01l_dataout; + wire_n01l_w_lg_dataout1676w(0) <= wire_n01l_dataout OR wire_n01i_dataout; + wire_n01ll_dataout <= wire_nlli1i_dataout WHEN cascaded_8b10b_en = '1' ELSE wire_nl010O_dataout; + wire_n01O_dataout <= tx_data_tc(10) WHEN cascaded_8b10b_en = '1' ELSE wire_ni0i_dataout; + wire_n01O_w_lg_w_lg_dataout1619w1750w(0) <= wire_n01O_w_lg_dataout1619w(0) AND ni0iil; + wire_n01O_w_lg_w_lg_dataout1619w1745w(0) <= wire_n01O_w_lg_dataout1619w(0) AND ni0iiO; + wire_n01O_w_lg_w_lg_dataout1619w1736w(0) <= wire_n01O_w_lg_dataout1619w(0) AND ni0ili; + wire_n01O_w_lg_w_lg_dataout1619w1733w(0) <= wire_n01O_w_lg_dataout1619w(0) AND ni0ill; + wire_n01O_w_lg_w_lg_dataout1619w1641w(0) <= wire_n01O_w_lg_dataout1619w(0) AND ni0lll; + wire_n01O_w_lg_w_lg_dataout1619w1632w(0) <= wire_n01O_w_lg_dataout1619w(0) AND ni0llO; + wire_n01O_w_lg_dataout1739w(0) <= wire_n01O_dataout AND wire_n01l_w_lg_w_lg_dataout1620w1666w(0); + wire_n01O_w_lg_dataout1644w(0) <= wire_n01O_dataout AND wire_n01l_w_lg_w_lg_dataout1620w1621w(0); + wire_n01O_w_lg_dataout1647w(0) <= wire_n01O_dataout AND wire_n01l_w_lg_dataout1625w(0); + wire_n01O_w_lg_dataout1688w(0) <= wire_n01O_dataout AND wire_n01l_w_lg_dataout1667w(0); + wire_n01O_w_lg_dataout1639w(0) <= wire_n01O_dataout AND ni0lll; + wire_n01O_w_lg_dataout1619w(0) <= NOT wire_n01O_dataout; + wire_n01O_w_lg_dataout1677w(0) <= wire_n01O_dataout OR wire_n01l_w_lg_dataout1676w(0); + wire_n0ii_dataout <= tx_data_tc(14) WHEN cascaded_8b10b_en = '1' ELSE wire_niil_dataout; + wire_n0ii_w_lg_dataout1654w(0) <= wire_n0ii_dataout AND wire_niO_w_lg_dataout1653w(0); + wire_n0ii_w_lg_dataout1616w(0) <= NOT wire_n0ii_dataout; + wire_n0il_dataout <= tx_data_tc(15) WHEN cascaded_8b10b_en = '1' ELSE wire_niiO_dataout; + wire_n0il_w_lg_dataout1655w(0) <= wire_n0il_dataout AND wire_n0ii_w_lg_dataout1654w(0); + wire_n0il_w_lg_dataout1612w(0) <= NOT wire_n0il_dataout; + wire_n0iO_dataout <= wire_nili_dataout AND NOT(nii1Ol); + wire_n0li_dataout <= wire_nill_dataout AND NOT(nii1Ol); + wire_n0ll_dataout <= wire_nilO_dataout AND NOT(nii1Ol); + wire_n0lO_dataout <= wire_niOi_dataout AND NOT(nii1Ol); + wire_n0O_dataout <= tx_ctl_tc(0) WHEN rendec_data_sel_tx = '1' ELSE tx_ctl_ts; + wire_n0O0i_dataout <= ((wire_n01iO_w_lg_n01li1049w(0) AND tx_data_9_tc(0)) OR n01il) WHEN ib_force_disparity = '1' ELSE wire_n0O0l_dataout; + wire_n0O0l_dataout <= wire_n0O0O_dataout OR (wire_w_lg_rforce_disp1040w(0) AND tx_data_9_tc(0)); + wire_n0O0O_dataout <= n01il AND NOT((wire_w_lg_rforce_disp1036w(0) AND tx_data_9_tc(0))); + wire_n0O1l_dataout <= wire_ni10i_dataout WHEN cascaded_8b10b_en = '1' ELSE wire_n0O0i_dataout; + wire_n0O1l_w_lg_dataout1848w(0) <= NOT wire_n0O1l_dataout; + wire_n0O1O_dataout <= wire_n0OOi_dataout WHEN cascaded_8b10b_en = '1' ELSE wire_nl010O_dataout; + wire_n0O1O_w_lg_dataout1697w(0) <= NOT wire_n0O1O_dataout; + wire_n0Oi_dataout <= wire_niOl_dataout OR nii1Ol; + wire_n0Ol_dataout <= wire_niOO_dataout AND NOT(nii1Ol); + wire_n0OO_dataout <= wire_nl1i_dataout OR nii1Ol; + wire_n0OOi_dataout <= wire_n0OOl_dataout OR (wire_w_lg_rforce_disp1047w(0) AND tx_data_9_tc(1)); + wire_n0OOl_dataout <= wire_nl010O_dataout AND NOT((wire_w_lg_rforce_disp1043w(0) AND tx_data_9_tc(1))); + wire_n10i_dataout <= tx_data_tc(12) AND rendec_data_sel_tx; + wire_n10l_dataout <= tx_data_tc(13) AND rendec_data_sel_tx; + wire_n10O_dataout <= tx_data_tc(14) AND rendec_data_sel_tx; + wire_n11i_dataout <= tx_data_tc(9) AND rendec_data_sel_tx; + wire_n11l_dataout <= tx_data_tc(10) AND rendec_data_sel_tx; + wire_n11O_dataout <= tx_data_tc(11) AND rendec_data_sel_tx; + wire_n1ii_dataout <= tx_data_tc(15) AND rendec_data_sel_tx; + wire_n1il_dataout <= tx_data_tc(0) WHEN cascaded_8b10b_en = '1' ELSE wire_n0iO_dataout; + wire_n1il_w_lg_dataout1775w(0) <= NOT wire_n1il_dataout; + wire_n1iO_dataout <= tx_data_tc(1) WHEN cascaded_8b10b_en = '1' ELSE wire_n0li_dataout; + wire_n1iO_w_lg_w_lg_dataout1771w1817w(0) <= wire_n1iO_w_lg_dataout1771w(0) AND wire_n1il_w_lg_dataout1775w(0); + wire_n1iO_w_lg_w_lg_dataout1771w1772w(0) <= wire_n1iO_w_lg_dataout1771w(0) AND wire_n1il_dataout; + wire_n1iO_w_lg_dataout1776w(0) <= wire_n1iO_dataout AND wire_n1il_w_lg_dataout1775w(0); + wire_n1iO_w_lg_dataout1818w(0) <= wire_n1iO_dataout AND wire_n1il_dataout; + wire_n1iO_w_lg_dataout1771w(0) <= NOT wire_n1iO_dataout; + wire_n1iO_w_lg_dataout1827w(0) <= wire_n1iO_dataout OR wire_n1il_dataout; + wire_n1li_dataout <= tx_data_tc(2) WHEN cascaded_8b10b_en = '1' ELSE wire_n0ll_dataout; + wire_n1li_w_lg_w_lg_dataout1770w1792w(0) <= wire_n1li_w_lg_dataout1770w(0) AND ni00Ol; + wire_n1li_w_lg_w_lg_dataout1770w1783w(0) <= wire_n1li_w_lg_dataout1770w(0) AND ni00OO; + wire_n1li_w_lg_w_lg_dataout1770w1901w(0) <= wire_n1li_w_lg_dataout1770w(0) AND ni01ll; + wire_n1li_w_lg_w_lg_dataout1770w1896w(0) <= wire_n1li_w_lg_dataout1770w(0) AND ni01lO; + wire_n1li_w_lg_w_lg_dataout1770w1887w(0) <= wire_n1li_w_lg_dataout1770w(0) AND ni01Oi; + wire_n1li_w_lg_w_lg_dataout1770w1884w(0) <= wire_n1li_w_lg_dataout1770w(0) AND ni01Ol; + wire_n1li_w_lg_dataout1890w(0) <= wire_n1li_dataout AND wire_n1iO_w_lg_w_lg_dataout1771w1817w(0); + wire_n1li_w_lg_dataout1795w(0) <= wire_n1li_dataout AND wire_n1iO_w_lg_w_lg_dataout1771w1772w(0); + wire_n1li_w_lg_dataout1798w(0) <= wire_n1li_dataout AND wire_n1iO_w_lg_dataout1776w(0); + wire_n1li_w_lg_dataout1839w(0) <= wire_n1li_dataout AND wire_n1iO_w_lg_dataout1818w(0); + wire_n1li_w_lg_dataout1790w(0) <= wire_n1li_dataout AND ni00Ol; + wire_n1li_w_lg_dataout1770w(0) <= NOT wire_n1li_dataout; + wire_n1li_w_lg_dataout1828w(0) <= wire_n1li_dataout OR wire_n1iO_w_lg_dataout1827w(0); + wire_n1ll_dataout <= tx_data_tc(3) WHEN cascaded_8b10b_en = '1' ELSE wire_n0lO_dataout; + wire_n1ll_w_lg_w_lg_dataout1768w1840w(0) <= wire_n1ll_w_lg_dataout1768w(0) AND wire_n1li_w_lg_dataout1839w(0); + wire_n1ll_w_lg_w_lg_dataout1768w1791w(0) <= wire_n1ll_w_lg_dataout1768w(0) AND wire_n1li_w_lg_dataout1790w(0); + wire_n1ll_w_lg_w_lg_dataout1768w1849w(0) <= wire_n1ll_w_lg_dataout1768w(0) AND ni000i; + wire_n1ll_w_lg_dataout1793w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_w_lg_dataout1770w1792w(0); + wire_n1ll_w_lg_dataout1784w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_w_lg_dataout1770w1783w(0); + wire_n1ll_w_lg_dataout1902w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_w_lg_dataout1770w1901w(0); + wire_n1ll_w_lg_dataout1897w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_w_lg_dataout1770w1896w(0); + wire_n1ll_w_lg_dataout1888w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_w_lg_dataout1770w1887w(0); + wire_n1ll_w_lg_dataout1885w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_w_lg_dataout1770w1884w(0); + wire_n1ll_w_lg_dataout1891w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_dataout1890w(0); + wire_n1ll_w_lg_dataout1796w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_dataout1795w(0); + wire_n1ll_w_lg_dataout1799w(0) <= wire_n1ll_dataout AND wire_n1li_w_lg_dataout1798w(0); + wire_n1ll_w_lg_dataout1768w(0) <= NOT wire_n1ll_dataout; + wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1840w1842w(0) <= wire_n1ll_w_lg_w_lg_dataout1768w1840w(0) OR wire_n1lO_w_lg_dataout1841w(0); + wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1791w1794w(0) <= wire_n1ll_w_lg_w_lg_dataout1768w1791w(0) OR wire_n1ll_w_lg_dataout1793w(0); + wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1849w1850w(0) <= wire_n1ll_w_lg_w_lg_dataout1768w1849w(0) OR ni00iO; + wire_n1ll_w_lg_w_lg_w_lg_w_lg_dataout1768w1840w1842w1844w(0) <= wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1840w1842w(0) OR wire_n1lO_w_lg_dataout1843w(0); + wire_n1ll_w_lg_w_lg_w_lg_w_lg_dataout1768w1791w1794w1797w(0) <= wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1791w1794w(0) OR wire_n1ll_w_lg_dataout1796w(0); + wire_n1ll_w1846w(0) <= wire_n1ll_w_lg_w_lg_w_lg_w_lg_dataout1768w1840w1842w1844w(0) OR wire_n1lO_w_lg_dataout1845w(0); + wire_n1ll_w1800w(0) <= wire_n1ll_w_lg_w_lg_w_lg_w_lg_dataout1768w1791w1794w1797w(0) OR wire_n1ll_w_lg_dataout1799w(0); + wire_n1ll_w_lg_w1846w1847w(0) <= wire_n1ll_w1846w(0) OR ni001l; + wire_n1lO_dataout <= tx_data_tc(4) WHEN cascaded_8b10b_en = '1' ELSE wire_n0Oi_dataout; + wire_n1lO_w_lg_w_lg_w_lg_dataout1788w1789w1801w(0) <= wire_n1lO_w_lg_w_lg_dataout1788w1789w(0) AND wire_n1ll_w1800w(0); + wire_n1lO_w_lg_w_lg_dataout1870w1871w(0) <= wire_n1lO_w_lg_dataout1870w(0) AND wire_n1li_dataout; + wire_n1lO_w_lg_w_lg_dataout1788w1851w(0) <= wire_n1lO_w_lg_dataout1788w(0) AND wire_n1ll_w_lg_w_lg_w_lg_dataout1768w1849w1850w(0); + wire_n1lO_w_lg_w_lg_dataout1788w1789w(0) <= wire_n1lO_w_lg_dataout1788w(0) AND wire_n1ll_dataout; + wire_n1lO_w_lg_w_lg_w_lg_dataout1788w1830w1831w(0) <= wire_n1lO_w_lg_w_lg_dataout1788w1830w(0) AND ni000l; + wire_n1lO_w_lg_dataout1836w(0) <= wire_n1lO_dataout AND wire_w_lg_w_lg_w_lg_ni000i1832w1834w1835w(0); + wire_n1lO_w_lg_dataout1769w(0) <= wire_n1lO_dataout AND wire_n1ll_w_lg_dataout1768w(0); + wire_n1lO_w_lg_dataout1870w(0) <= wire_n1lO_dataout AND wire_n1ll_dataout; + wire_n1lO_w_lg_dataout1845w(0) <= wire_n1lO_dataout AND ni000i; + wire_n1lO_w_lg_dataout1843w(0) <= wire_n1lO_dataout AND ni00li; + wire_n1lO_w_lg_dataout1841w(0) <= wire_n1lO_dataout AND ni00ll; + wire_n1lO_w_lg_dataout1788w(0) <= NOT wire_n1lO_dataout; + wire_n1lO_w_lg_w_lg_dataout1788w1830w(0) <= wire_n1lO_w_lg_dataout1788w(0) OR wire_nl1iii_dataout; + wire_n1Oi_dataout <= tx_data_tc(5) WHEN cascaded_8b10b_en = '1' ELSE wire_n0Ol_dataout; + wire_n1Oi_w_lg_dataout1814w(0) <= NOT wire_n1Oi_dataout; + wire_n1Ol_dataout <= tx_data_tc(6) WHEN cascaded_8b10b_en = '1' ELSE wire_n0OO_dataout; + wire_n1Ol_w_lg_dataout1805w(0) <= wire_n1Ol_dataout AND wire_nil_w_lg_dataout1804w(0); + wire_n1Ol_w_lg_dataout1767w(0) <= NOT wire_n1Ol_dataout; + wire_n1OO_dataout <= tx_data_tc(7) WHEN cascaded_8b10b_en = '1' ELSE wire_ni1i_dataout; + wire_n1OO_w_lg_dataout1806w(0) <= wire_n1OO_dataout AND wire_n1Ol_w_lg_dataout1805w(0); + wire_n1OO_w_lg_dataout1763w(0) <= NOT wire_n1OO_dataout; + wire_ni0i_dataout <= wire_nl0l_dataout AND NOT(nii1Ol); + wire_ni0l_dataout <= wire_nl0O_dataout AND NOT(nii1Ol); + wire_ni0O_dataout <= wire_nlii_dataout AND NOT(nii1Ol); + wire_ni10i_dataout <= wire_ni10l_dataout OR (wire_w_lg_rforce_disp1040w(0) AND tx_data_9_tc(0)); + wire_ni10l_dataout <= n01il AND NOT((wire_w_lg_rforce_disp1036w(0) AND tx_data_9_tc(0))); + wire_ni1i_dataout <= wire_nl1l_dataout AND NOT(nii1Ol); + wire_ni1l_dataout <= wire_nl1O_dataout AND NOT(nii1Ol); + wire_ni1O_dataout <= wire_nl0i_dataout AND NOT(nii1Ol); + wire_nii_dataout <= tx_ctl_tc(1) AND rendec_data_sel_tx; + wire_nii0i_dataout <= wire_niil0i_o WHEN rtxbitslip_en = '1' ELSE wire_niliO_o; + wire_nii0l_dataout <= wire_niil0l_o WHEN rtxbitslip_en = '1' ELSE wire_nilli_o; + wire_nii0O_dataout <= wire_niil0O_o WHEN rtxbitslip_en = '1' ELSE wire_nilll_o; + wire_nii1l_dataout <= wire_niil1l_o WHEN rtxbitslip_en = '1' ELSE wire_nilii_o; + wire_nii1O_dataout <= wire_niil1O_o WHEN rtxbitslip_en = '1' ELSE wire_nilil_o; + wire_niii_dataout <= wire_nlil_dataout AND NOT(nii1Ol); + wire_niiii_dataout <= wire_niilii_o WHEN rtxbitslip_en = '1' ELSE wire_nillO_o; + wire_niiil_dataout <= wire_niilil_o WHEN rtxbitslip_en = '1' ELSE wire_nilOi_o; + wire_niiiO_dataout <= wire_niiliO_o WHEN rtxbitslip_en = '1' ELSE wire_nilOl_o; + wire_niil_dataout <= wire_nliO_dataout AND NOT(nii1Ol); + wire_niili_dataout <= wire_niilli_o WHEN rtxbitslip_en = '1' ELSE wire_nilOO_o; + wire_niill_dataout <= wire_niilll_o WHEN rtxbitslip_en = '1' ELSE wire_niO1i_o; + wire_niilO_dataout <= wire_niillO_o WHEN rtxbitslip_en = '1' ELSE wire_niO1l_o; + wire_niiO_dataout <= wire_nlli_dataout AND NOT(nii1Ol); + wire_niiOi_dataout <= wire_niilOi_o WHEN rtxbitslip_en = '1' ELSE wire_niO1O_o; + wire_niiOl_dataout <= wire_niilOl_o WHEN rtxbitslip_en = '1' ELSE wire_niO0i_o; + wire_niiOO_dataout <= wire_niilOO_o WHEN rtxbitslip_en = '1' ELSE wire_niO0l_o; + wire_nil_dataout <= tx_ctl_tc(0) WHEN cascaded_8b10b_en = '1' ELSE wire_nli_dataout; + wire_nil_w_lg_dataout1804w(0) <= wire_nil_dataout AND wire_n1Oi_dataout; + wire_nil00l_dataout <= wire_nilOO_o AND NOT(ni01il); + wire_nil00O_dataout <= wire_niO1i_o AND NOT(ni01il); + wire_nil0i_dataout <= wire_niiO0i_o WHEN rtxbitslip_en = '1' ELSE wire_niOiO_o; + wire_nil0l_dataout <= wire_niiO0l_o WHEN rtxbitslip_en = '1' ELSE wire_niOli_o; + wire_nil0O_dataout <= wire_niiO0O_o WHEN rtxbitslip_en = '1' ELSE wire_niOll_o; + wire_nil0OO_dataout <= wire_niOli_o AND NOT(ni01il); + wire_nil1i_dataout <= wire_niiO1i_o WHEN rtxbitslip_en = '1' ELSE wire_niO0O_o; + wire_nil1l_dataout <= wire_niiO1l_o WHEN rtxbitslip_en = '1' ELSE wire_niOii_o; + wire_nil1O_dataout <= wire_niiO1O_o WHEN rtxbitslip_en = '1' ELSE wire_niOil_o; + wire_nili_dataout <= wire_nlOii_dataout OR nii1iO; + wire_nili1i_dataout <= wire_niOll_o AND NOT(ni01il); + wire_niliOl_dataout <= wire_niO1l_o AND ni01iO; + wire_niliOO_dataout <= wire_niO1O_o AND ni01iO; + wire_nill_dataout <= wire_nlOil_dataout AND NOT(nii1iO); + wire_nill0i_dataout <= wire_niOii_o AND ni01iO; + wire_nill0l_dataout <= wire_niOil_o AND ni01iO; + wire_nill0O_dataout <= wire_niOiO_o AND ni01iO; + wire_nill1i_dataout <= wire_niO0i_o AND ni01iO; + wire_nill1l_dataout <= wire_niO0l_o AND ni01iO; + wire_nill1O_dataout <= wire_niO0O_o AND ni01iO; + wire_nillii_dataout <= wire_niOli_o AND ni01iO; + wire_nillil_dataout <= wire_niOll_o AND ni01iO; + wire_nilO_dataout <= wire_nlOiO_dataout OR nii1iO; + wire_nilO0i_dataout <= wire_nilOO_o AND NOT(ni01li); + wire_nilO0l_dataout <= wire_niO1i_o AND NOT(ni01li); + wire_nilO0O_dataout <= wire_niO1l_o AND NOT(ni01li); + wire_nilOii_dataout <= wire_niO1O_o AND NOT(ni01li); + wire_nilOil_dataout <= wire_niO0i_o AND NOT(ni01li); + wire_nilOiO_dataout <= wire_niO0l_o AND NOT(ni01li); + wire_nilOli_dataout <= wire_niO0O_o AND NOT(ni01li); + wire_nilOll_dataout <= wire_niOii_o AND NOT(ni01li); + wire_nilOlO_dataout <= wire_niOil_o AND NOT(ni01li); + wire_nilOOi_dataout <= wire_niOiO_o AND NOT(ni01li); + wire_nilOOl_dataout <= wire_niOli_o AND NOT(ni01li); + wire_nilOOO_dataout <= wire_niOll_o AND NOT(ni01li); + wire_niO_dataout <= tx_ctl_tc(1) WHEN cascaded_8b10b_en = '1' ELSE wire_nll_dataout; + wire_niO_w_lg_dataout1653w(0) <= wire_niO_dataout AND wire_n00O_dataout; + wire_niOi_dataout <= wire_nlOli_dataout AND NOT(nii1iO); + wire_niOl_dataout <= wire_nlOll_dataout AND NOT(nii1iO); + wire_niOlOi_dataout <= wire_n0O1l_w_lg_dataout1848w(0) WHEN ((ni00il OR ((wire_nl1iii_dataout OR ni00ll) OR ni00li)) OR ni001i) = '1' ELSE wire_n0O1l_dataout; + wire_niOlOi_w_lg_w_lg_dataout1755w1758w(0) <= wire_niOlOi_w_lg_dataout1755w(0) AND wire_nl00ll_w_lg_dataout1757w(0); + wire_niOlOi_w_lg_w_lg_dataout1755w1760w(0) <= wire_niOlOi_w_lg_dataout1755w(0) AND ni0i0O; + wire_niOlOi_w_lg_dataout1802w(0) <= wire_niOlOi_dataout AND wire_n1lO_w_lg_w_lg_w_lg_dataout1788w1789w1801w(0); + wire_niOlOi_w_lg_dataout1755w(0) <= NOT wire_niOlOi_dataout; + wire_niOlOi_w_lg_w_lg_w_lg_dataout1755w1758w1759w(0) <= wire_niOlOi_w_lg_w_lg_dataout1755w1758w(0) OR ni0i0l; + wire_niOO_dataout <= wire_nlOlO_dataout AND NOT(nii1iO); + wire_niOOOi_dataout <= wire_n1il_w_lg_dataout1775w(0) WHEN ni01OO = '1' ELSE wire_n1il_dataout; + wire_niOOOl_dataout <= wire_nl1i0O_w_lg_dataout1861w(0) WHEN ni01OO = '1' ELSE wire_nl1i0O_dataout; + wire_niOOOO_dataout <= wire_nl10OO_w_lg_dataout1860w(0) WHEN ni01OO = '1' ELSE wire_nl10OO_dataout; + wire_nl000i_dataout <= wire_n1OO_w_lg_dataout1763w(0) WHEN ni0i0i = '1' ELSE wire_n1OO_dataout; + wire_nl000l_dataout <= wire_nl01iO_w_lg_dataout1762w(0) WHEN ni0i0i = '1' ELSE wire_nl01iO_dataout; + wire_nl001i_dataout <= wire_n1Oi_dataout AND NOT(ni0i1O); + wire_nl001i_w_lg_dataout1765w(0) <= NOT wire_nl001i_dataout; + wire_nl001l_dataout <= wire_nl001i_w_lg_dataout1765w(0) WHEN ni0i0i = '1' ELSE wire_nl001i_dataout; + wire_nl001O_dataout <= wire_nl01Ol_w_lg_dataout1764w(0) WHEN ni0i0i = '1' ELSE wire_nl01Ol_dataout; + wire_nl00ll_dataout <= ni0iii WHEN r8b10b_enc_ibm_en = '1' ELSE wire_nil_dataout; + wire_nl00ll_w_lg_dataout1757w(0) <= wire_nl00ll_dataout AND wire_w_lg_ni0i0O1756w(0); + wire_nl010O_dataout <= wire_niOlOi_w_lg_dataout1755w(0) WHEN (ni0i1i OR (wire_n1OO_dataout AND ni0i0O)) = '1' ELSE wire_niOlOi_dataout; + wire_nl01iO_dataout <= wire_nl01li_dataout OR ni0i1O; + wire_nl01iO_w_lg_dataout1762w(0) <= NOT wire_nl01iO_dataout; + wire_nl01li_dataout <= wire_w_lg_ni0i0O1756w(0) AND NOT(wire_n1OO_dataout); + wire_nl01Ol_dataout <= wire_n1Ol_w_lg_dataout1767w(0) WHEN ni0i1i = '1' ELSE wire_n1Ol_dataout; + wire_nl01Ol_w_lg_dataout1764w(0) <= NOT wire_nl01Ol_dataout; + wire_nl0i_dataout <= wire_n11i_dataout AND NOT(nii1iO); + wire_nl0l_dataout <= wire_n11l_dataout AND NOT(nii1iO); + wire_nl0O_dataout <= wire_n11O_dataout AND NOT(nii1iO); + wire_nl10Ol_dataout <= wire_n1ll_w_lg_dataout1768w(0) WHEN ni00li = '1' ELSE wire_n1ll_dataout; + wire_nl10Ol_w_lg_dataout1859w(0) <= NOT wire_nl10Ol_dataout; + wire_nl10OO_dataout <= wire_n1li_w_lg_dataout1770w(0) WHEN ((wire_n1lO_dataout AND (wire_n1ll_dataout AND (wire_n1li_w_lg_dataout1770w(0) AND wire_n1iO_w_lg_w_lg_dataout1771w1817w(0)))) OR ni00ll) = '1' ELSE wire_n1li_dataout; + wire_nl10OO_w_lg_dataout1860w(0) <= NOT wire_nl10OO_dataout; + wire_nl111i_dataout <= wire_nl10Ol_w_lg_dataout1859w(0) WHEN ni01OO = '1' ELSE wire_nl10Ol_dataout; + wire_nl111l_dataout <= wire_w_lg_ni000O1858w(0) WHEN ni01OO = '1' ELSE ni000O; + wire_nl111O_dataout <= wire_w_lg_ni001O1857w(0) WHEN ni01OO = '1' ELSE ni001O; + wire_nl1i_dataout <= wire_nlOOi_dataout OR nii1iO; + wire_nl1i0O_dataout <= wire_n1iO_w_lg_dataout1771w(0) WHEN ni00lO = '1' ELSE wire_n1iO_dataout; + wire_nl1i0O_w_lg_dataout1861w(0) <= NOT wire_nl1i0O_dataout; + wire_nl1iii_dataout <= ni0iii WHEN r8b10b_enc_ibm_en = '1' ELSE wire_nil_dataout; + wire_nl1l_dataout <= wire_nlOOl_dataout OR nii1iO; + wire_nl1O_dataout <= wire_nlOOO_dataout AND NOT(nii1iO); + wire_nli_dataout <= wire_n0O_dataout AND NOT(nii00O); + wire_nli0il_dataout <= wire_n01i_w_lg_dataout1624w(0) WHEN ni0ilO = '1' ELSE wire_n01i_dataout; + wire_nli0iO_dataout <= wire_nliO1i_w_lg_dataout1710w(0) WHEN ni0ilO = '1' ELSE wire_nliO1i_dataout; + wire_nli0li_dataout <= wire_nlilli_w_lg_dataout1709w(0) WHEN ni0ilO = '1' ELSE wire_nlilli_dataout; + wire_nli0ll_dataout <= wire_nliliO_w_lg_dataout1708w(0) WHEN ni0ilO = '1' ELSE wire_nliliO_dataout; + wire_nli0lO_dataout <= wire_w_lg_ni0l1O1707w(0) WHEN ni0ilO = '1' ELSE ni0l1O; + wire_nli0Oi_dataout <= wire_w_lg_ni0iOO1706w(0) WHEN ni0ilO = '1' ELSE ni0iOO; + wire_nli1il_dataout <= wire_n0O1O_w_lg_dataout1697w(0) WHEN ((ni0l0l OR ((wire_nliO1l_dataout OR ni0lil) OR ni0lii)) OR ni0iOi) = '1' ELSE wire_n0O1O_dataout; + wire_nli1il_w_lg_w_lg_dataout1604w1607w(0) <= wire_nli1il_w_lg_dataout1604w(0) AND wire_nlll0O_w_lg_dataout1606w(0); + wire_nli1il_w_lg_w_lg_dataout1604w1609w(0) <= wire_nli1il_w_lg_dataout1604w(0) AND ni0O1O; + wire_nli1il_w_lg_dataout1651w(0) <= wire_nli1il_dataout AND wire_n00l_w_lg_w_lg_w_lg_dataout1637w1638w1650w(0); + wire_nli1il_w_lg_dataout1604w(0) <= NOT wire_nli1il_dataout; + wire_nli1il_w_lg_w_lg_w_lg_dataout1604w1607w1608w(0) <= wire_nli1il_w_lg_w_lg_dataout1604w1607w(0) OR ni0O1l; + wire_nlii_dataout <= wire_n10i_dataout AND NOT(nii1iO); + wire_nlil_dataout <= wire_n10l_dataout AND NOT(nii1iO); + wire_nliliO_dataout <= wire_n00i_w_lg_dataout1617w(0) WHEN ni0lii = '1' ELSE wire_n00i_dataout; + wire_nliliO_w_lg_dataout1708w(0) <= NOT wire_nliliO_dataout; + wire_nlilli_dataout <= wire_n01O_w_lg_dataout1619w(0) WHEN ((wire_n00l_dataout AND (wire_n00i_dataout AND (wire_n01O_w_lg_dataout1619w(0) AND wire_n01l_w_lg_w_lg_dataout1620w1666w(0)))) OR ni0lil) = '1' ELSE wire_n01O_dataout; + wire_nlilli_w_lg_dataout1709w(0) <= NOT wire_nlilli_dataout; + wire_nliO_dataout <= wire_n10O_dataout AND NOT(nii1iO); + wire_nliO1i_dataout <= wire_n01l_w_lg_dataout1620w(0) WHEN ni0liO = '1' ELSE wire_n01l_dataout; + wire_nliO1i_w_lg_dataout1710w(0) <= NOT wire_nliO1i_dataout; + wire_nliO1l_dataout <= ni0O0i WHEN r8b10b_enc_ibm_en = '1' ELSE wire_niO_dataout; + wire_nll_dataout <= wire_nii_dataout AND NOT(nii00O); + wire_nlli_dataout <= wire_n1ii_dataout AND NOT(nii1iO); + wire_nlli0i_dataout <= wire_nlli0l_dataout OR ni0lOO; + wire_nlli0i_w_lg_dataout1611w(0) <= NOT wire_nlli0i_dataout; + wire_nlli0l_dataout <= wire_w_lg_ni0O1O1605w(0) AND NOT(wire_n0il_dataout); + wire_nlli1i_dataout <= wire_nli1il_w_lg_dataout1604w(0) WHEN (ni0lOi OR (wire_n0il_dataout AND ni0O1O)) = '1' ELSE wire_nli1il_dataout; + wire_nlliiO_dataout <= wire_n0ii_w_lg_dataout1616w(0) WHEN ni0lOi = '1' ELSE wire_n0ii_dataout; + wire_nlliiO_w_lg_dataout1613w(0) <= NOT wire_nlliiO_dataout; + wire_nllill_dataout <= wire_n00O_dataout AND NOT(ni0lOO); + wire_nllill_w_lg_dataout1614w(0) <= NOT wire_nllill_dataout; + wire_nllilO_dataout <= wire_nllill_w_lg_dataout1614w(0) WHEN ni0O1i = '1' ELSE wire_nllill_dataout; + wire_nlliOi_dataout <= wire_nlliiO_w_lg_dataout1613w(0) WHEN ni0O1i = '1' ELSE wire_nlliiO_dataout; + wire_nlliOl_dataout <= wire_n0il_w_lg_dataout1612w(0) WHEN ni0O1i = '1' ELSE wire_n0il_dataout; + wire_nlliOO_dataout <= wire_nlli0i_w_lg_dataout1611w(0) WHEN ni0O1i = '1' ELSE wire_nlli0i_dataout; + wire_nlll0O_dataout <= ni0O0i WHEN r8b10b_enc_ibm_en = '1' ELSE wire_niO_dataout; + wire_nlll0O_w_lg_dataout1606w(0) <= wire_nlll0O_dataout AND wire_w_lg_ni0O1O1605w(0); + wire_nlOii_dataout <= tx_data_tc(0) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(0); + wire_nlOil_dataout <= tx_data_tc(1) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(1); + wire_nlOiO_dataout <= tx_data_tc(2) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(2); + wire_nlOli_dataout <= tx_data_tc(3) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(3); + wire_nlOll_dataout <= tx_data_tc(4) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(4); + wire_nlOlO_dataout <= tx_data_tc(5) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(5); + wire_nlOOi_dataout <= tx_data_tc(6) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(6); + wire_nlOOl_dataout <= tx_data_tc(7) WHEN rendec_data_sel_tx = '1' ELSE tx_data_ts(7); + wire_nlOOO_dataout <= tx_data_tc(8) AND rendec_data_sel_tx; + wire_nili1O_i <= ( tx_boundary_sel(4 DOWNTO 0)); + nili1O : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_nili1O_i, + o => wire_nili1O_o + ); + wire_nillli_i <= ( tx_boundary_sel(3 DOWNTO 0)); + nillli : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nillli_i, + o => wire_nillli_o + ); + wire_n010i_w_lg_o200w(0) <= NOT wire_n010i_o; + wire_n010i_data <= ( tx_data_pg(17) & tx_data_pg(17) & tx_data_pg(17) & tx_data_pg(17) & rev_loop_data(17) & wire_nlliOi_dataout & tx_data_pg(17) & wire_nlliOi_dataout & tx_data_pg(17) & tx_data_pg(17) & tx_data_pg(17) & tx_data_pg(17) & rev_loop_data(17) & tx_data_tc(15) & tx_data_pg(17) & tx_data_tc(15)); + wire_n010i_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n010i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n010i_data, + o => wire_n010i_o, + sel => wire_n010i_sel + ); + wire_n010l_w_lg_o188w(0) <= NOT wire_n010l_o; + wire_n010l_data <= ( tx_data_pg(18) & tx_data_pg(18) & tx_data_pg(18) & tx_data_pg(18) & rev_loop_data(18) & wire_nlliOl_dataout & tx_data_pg(18) & wire_nlliOl_dataout & tx_data_pg(18) & tx_data_pg(18) & tx_data_pg(18) & tx_data_pg(18) & rev_loop_data(18) & tx_ctl_tc(1) & tx_data_pg(18) & tx_ctl_tc(1)); + wire_n010l_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n010l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n010l_data, + o => wire_n010l_o, + sel => wire_n010l_sel + ); + wire_n010O_w_lg_o178w(0) <= NOT wire_n010O_o; + wire_n010O_data <= ( tx_data_pg(19) & tx_data_pg(19) & tx_data_pg(19) & tx_data_pg(19) & rev_loop_data(19) & wire_nlliOO_dataout & tx_data_pg(19) & wire_nlliOO_dataout & tx_data_pg(19) & tx_data_pg(19) & tx_data_pg(19) & tx_data_pg(19) & rev_loop_data(19) & tx_data_9_tc(1) & tx_data_pg(19) & tx_data_9_tc(1)); + wire_n010O_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n010O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n010O_data, + o => wire_n010O_o, + sel => wire_n010O_sel + ); + wire_n011i_w_lg_o229w(0) <= NOT wire_n011i_o; + wire_n011i_data <= ( tx_data_pg(14) & tx_data_pg(14) & tx_data_pg(14) & tx_data_pg(14) & rev_loop_data(14) & wire_nli0lO_dataout & tx_data_pg(14) & wire_nli0lO_dataout & tx_data_pg(14) & tx_data_pg(14) & tx_data_pg(14) & tx_data_pg(14) & rev_loop_data(14) & tx_data_tc(12) & tx_data_pg(14) & tx_data_tc(12)); + wire_n011i_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n011i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n011i_data, + o => wire_n011i_o, + sel => wire_n011i_sel + ); + wire_n011l_w_lg_o220w(0) <= NOT wire_n011l_o; + wire_n011l_data <= ( tx_data_pg(15) & tx_data_pg(15) & tx_data_pg(15) & tx_data_pg(15) & rev_loop_data(15) & wire_nli0Oi_dataout & tx_data_pg(15) & wire_nli0Oi_dataout & tx_data_pg(15) & tx_data_pg(15) & tx_data_pg(15) & tx_data_pg(15) & rev_loop_data(15) & tx_data_tc(13) & tx_data_pg(15) & tx_data_tc(13)); + wire_n011l_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n011l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n011l_data, + o => wire_n011l_o, + sel => wire_n011l_sel + ); + wire_n011O_w_lg_o211w(0) <= NOT wire_n011O_o; + wire_n011O_data <= ( tx_data_pg(16) & tx_data_pg(16) & tx_data_pg(16) & tx_data_pg(16) & rev_loop_data(16) & wire_nllilO_dataout & tx_data_pg(16) & wire_nllilO_dataout & tx_data_pg(16) & tx_data_pg(16) & tx_data_pg(16) & tx_data_pg(16) & rev_loop_data(16) & tx_data_tc(14) & tx_data_pg(16) & tx_data_tc(14)); + wire_n011O_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n011O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n011O_data, + o => wire_n011O_o, + sel => wire_n011O_sel + ); + wire_n1O0i_w_lg_o122w(0) <= NOT wire_n1O0i_o; + wire_n1O0i_data <= ( tx_data_pg(2) & tx_data_pg(2) & tx_data_pg(2) & tx_data_pg(2) & rev_loop_data(2) & wire_niOOOO_dataout & tx_data_pg(2) & wire_niOOOO_dataout & tx_data_pg(2) & tx_data_pg(2) & tx_data_pg(2) & tx_data_pg(2) & rev_loop_data(2) & tx_data_tc(2) & tx_data_pg(2) & tx_data_tc(2)); + wire_n1O0i_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1O0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1O0i_data, + o => wire_n1O0i_o, + sel => wire_n1O0i_sel + ); + wire_n1O0l_w_lg_o133w(0) <= NOT wire_n1O0l_o; + wire_n1O0l_data <= ( tx_data_pg(3) & tx_data_pg(3) & tx_data_pg(3) & tx_data_pg(3) & rev_loop_data(3) & wire_nl111i_dataout & tx_data_pg(3) & wire_nl111i_dataout & tx_data_pg(3) & tx_data_pg(3) & tx_data_pg(3) & tx_data_pg(3) & rev_loop_data(3) & tx_data_tc(3) & tx_data_pg(3) & tx_data_tc(3)); + wire_n1O0l_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1O0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1O0l_data, + o => wire_n1O0l_o, + sel => wire_n1O0l_sel + ); + wire_n1O0O_w_lg_o130w(0) <= NOT wire_n1O0O_o; + wire_n1O0O_data <= ( tx_data_pg(4) & tx_data_pg(4) & tx_data_pg(4) & tx_data_pg(4) & rev_loop_data(4) & wire_nl111l_dataout & tx_data_pg(4) & wire_nl111l_dataout & tx_data_pg(4) & tx_data_pg(4) & tx_data_pg(4) & tx_data_pg(4) & rev_loop_data(4) & tx_data_tc(4) & tx_data_pg(4) & tx_data_tc(4)); + wire_n1O0O_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1O0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1O0O_data, + o => wire_n1O0O_o, + sel => wire_n1O0O_sel + ); + wire_n1O1l_w_lg_o96w(0) <= NOT wire_n1O1l_o; + wire_n1O1l_data <= ( tx_data_pg(0) & tx_data_pg(0) & tx_data_pg(0) & tx_data_pg(0) & rev_loop_data(0) & wire_niOOOi_dataout & tx_data_pg(0) & wire_niOOOi_dataout & tx_data_pg(0) & tx_data_pg(0) & tx_data_pg(0) & tx_data_pg(0) & rev_loop_data(0) & tx_data_tc(0) & tx_data_pg(0) & tx_data_tc(0)); + wire_n1O1l_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1O1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1O1l_data, + o => wire_n1O1l_o, + sel => wire_n1O1l_sel + ); + wire_n1O1O_w_lg_o108w(0) <= NOT wire_n1O1O_o; + wire_n1O1O_data <= ( tx_data_pg(1) & tx_data_pg(1) & tx_data_pg(1) & tx_data_pg(1) & rev_loop_data(1) & wire_niOOOl_dataout & tx_data_pg(1) & wire_niOOOl_dataout & tx_data_pg(1) & tx_data_pg(1) & tx_data_pg(1) & tx_data_pg(1) & rev_loop_data(1) & tx_data_tc(1) & tx_data_pg(1) & tx_data_tc(1)); + wire_n1O1O_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1O1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1O1O_data, + o => wire_n1O1O_o, + sel => wire_n1O1O_sel + ); + wire_n1Oii_w_lg_o119w(0) <= NOT wire_n1Oii_o; + wire_n1Oii_data <= ( tx_data_pg(5) & tx_data_pg(5) & tx_data_pg(5) & tx_data_pg(5) & rev_loop_data(5) & wire_nl111O_dataout & tx_data_pg(5) & wire_nl111O_dataout & tx_data_pg(5) & tx_data_pg(5) & tx_data_pg(5) & tx_data_pg(5) & rev_loop_data(5) & tx_data_tc(5) & tx_data_pg(5) & tx_data_tc(5)); + wire_n1Oii_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1Oii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oii_data, + o => wire_n1Oii_o, + sel => wire_n1Oii_sel + ); + wire_n1Oil_w_lg_o106w(0) <= NOT wire_n1Oil_o; + wire_n1Oil_data <= ( tx_data_pg(6) & tx_data_pg(6) & tx_data_pg(6) & tx_data_pg(6) & rev_loop_data(6) & wire_nl001l_dataout & tx_data_pg(6) & wire_nl001l_dataout & tx_data_pg(6) & tx_data_pg(6) & tx_data_pg(6) & tx_data_pg(6) & rev_loop_data(6) & tx_data_tc(6) & tx_data_pg(6) & tx_data_tc(6)); + wire_n1Oil_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1Oil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oil_data, + o => wire_n1Oil_o, + sel => wire_n1Oil_sel + ); + wire_n1OiO_w_lg_o94w(0) <= NOT wire_n1OiO_o; + wire_n1OiO_data <= ( tx_data_pg(7) & tx_data_pg(7) & tx_data_pg(7) & tx_data_pg(7) & rev_loop_data(7) & wire_nl001O_dataout & tx_data_pg(7) & wire_nl001O_dataout & tx_data_pg(7) & tx_data_pg(7) & tx_data_pg(7) & tx_data_pg(7) & rev_loop_data(7) & tx_data_tc(7) & tx_data_pg(7) & tx_data_tc(7)); + wire_n1OiO_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1OiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OiO_data, + o => wire_n1OiO_o, + sel => wire_n1OiO_sel + ); + wire_n1Oli_w_lg_o81w(0) <= NOT wire_n1Oli_o; + wire_n1Oli_data <= ( tx_data_pg(8) & tx_data_pg(8) & tx_data_pg(8) & tx_data_pg(8) & rev_loop_data(8) & wire_nl000i_dataout & tx_data_pg(8) & wire_nl000i_dataout & tx_data_pg(8) & tx_data_pg(8) & tx_data_pg(8) & tx_data_pg(8) & rev_loop_data(8) & tx_ctl_tc(1) & tx_data_pg(8) & tx_ctl_tc(0)); + wire_n1Oli_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1Oli : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oli_data, + o => wire_n1Oli_o, + sel => wire_n1Oli_sel + ); + wire_n1Oll_w_lg_o70w(0) <= NOT wire_n1Oll_o; + wire_n1Oll_data <= ( tx_data_pg(9) & tx_data_pg(9) & tx_data_pg(9) & tx_data_pg(9) & rev_loop_data(9) & wire_nl000l_dataout & tx_data_pg(9) & wire_nl000l_dataout & tx_data_pg(9) & tx_data_pg(9) & tx_data_pg(9) & tx_data_pg(9) & rev_loop_data(9) & tx_data_9_tc(0) & tx_data_pg(9) & tx_data_9_tc(0)); + wire_n1Oll_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1Oll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oll_data, + o => wire_n1Oll_o, + sel => wire_n1Oll_sel + ); + wire_n1OlO_w_lg_o265w(0) <= NOT wire_n1OlO_o; + wire_n1OlO_data <= ( tx_data_pg(10) & tx_data_pg(10) & tx_data_pg(10) & tx_data_pg(10) & rev_loop_data(10) & wire_nli0il_dataout & tx_data_pg(10) & wire_nli0il_dataout & tx_data_pg(10) & tx_data_pg(10) & tx_data_pg(10) & tx_data_pg(10) & rev_loop_data(10) & tx_data_tc(8) & tx_data_pg(10) & tx_data_tc(8)); + wire_n1OlO_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1OlO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OlO_data, + o => wire_n1OlO_o, + sel => wire_n1OlO_sel + ); + wire_n1OOi_w_lg_o256w(0) <= NOT wire_n1OOi_o; + wire_n1OOi_data <= ( tx_data_pg(11) & tx_data_pg(11) & tx_data_pg(11) & tx_data_pg(11) & rev_loop_data(11) & wire_nli0iO_dataout & tx_data_pg(11) & wire_nli0iO_dataout & tx_data_pg(11) & tx_data_pg(11) & tx_data_pg(11) & tx_data_pg(11) & rev_loop_data(11) & tx_data_tc(9) & tx_data_pg(11) & tx_data_tc(9)); + wire_n1OOi_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1OOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OOi_data, + o => wire_n1OOi_o, + sel => wire_n1OOi_sel + ); + wire_n1OOl_w_lg_o247w(0) <= NOT wire_n1OOl_o; + wire_n1OOl_data <= ( tx_data_pg(12) & tx_data_pg(12) & tx_data_pg(12) & tx_data_pg(12) & rev_loop_data(12) & wire_nli0li_dataout & tx_data_pg(12) & wire_nli0li_dataout & tx_data_pg(12) & tx_data_pg(12) & tx_data_pg(12) & tx_data_pg(12) & rev_loop_data(12) & tx_data_tc(10) & tx_data_pg(12) & tx_data_tc(10)); + wire_n1OOl_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1OOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OOl_data, + o => wire_n1OOl_o, + sel => wire_n1OOl_sel + ); + wire_n1OOO_w_lg_o238w(0) <= NOT wire_n1OOO_o; + wire_n1OOO_data <= ( tx_data_pg(13) & tx_data_pg(13) & tx_data_pg(13) & tx_data_pg(13) & rev_loop_data(13) & wire_nli0ll_dataout & tx_data_pg(13) & wire_nli0ll_dataout & tx_data_pg(13) & tx_data_pg(13) & tx_data_pg(13) & tx_data_pg(13) & rev_loop_data(13) & tx_data_tc(11) & tx_data_pg(13) & tx_data_tc(11)); + wire_n1OOO_sel <= ( endec & prbs_en & rrev_loopbk & ni1li); + n1OOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OOO_data, + o => wire_n1OOO_o, + sel => wire_n1OOO_sel + ); + wire_niil0i_data <= ( wire_niiOiO_o & wire_nil1Ol_o & wire_nili0O_o & wire_nillOi_o); + wire_niil0i_sel <= ( doublewidth & dwidth); + niil0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niil0i_data, + o => wire_niil0i_o, + sel => wire_niil0i_sel + ); + wire_niil0l_data <= ( wire_niiOli_o & wire_nil1OO_o & wire_niliii_o & wire_nillOl_o); + wire_niil0l_sel <= ( doublewidth & dwidth); + niil0l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niil0l_data, + o => wire_niil0l_o, + sel => wire_niil0l_sel + ); + wire_niil0O_data <= ( wire_niiOll_o & wire_nil01i_o & wire_niliil_o & wire_nillOO_o); + wire_niil0O_sel <= ( doublewidth & dwidth); + niil0O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niil0O_data, + o => wire_niil0O_o, + sel => wire_niil0O_sel + ); + wire_niil1l_data <= ( wire_niiOii_o & wire_nil1lO_o & wire_nili0i_o & wire_nillll_o); + wire_niil1l_sel <= ( doublewidth & dwidth); + niil1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niil1l_data, + o => wire_niil1l_o, + sel => wire_niil1l_sel + ); + wire_niil1O_data <= ( wire_niiOil_o & wire_nil1Oi_o & wire_nili0l_o & wire_nilllO_o); + wire_niil1O_sel <= ( doublewidth & dwidth); + niil1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niil1O_data, + o => wire_niil1O_o, + sel => wire_niil1O_sel + ); + wire_niilii_data <= ( wire_niiOlO_o & wire_nil01l_o & wire_niliiO_o & wire_nilO1i_o); + wire_niilii_sel <= ( doublewidth & dwidth); + niilii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niilii_data, + o => wire_niilii_o, + sel => wire_niilii_sel + ); + wire_niilil_data <= ( wire_niiOOi_o & wire_nil01O_o & wire_nilili_o & wire_nilO1l_o); + wire_niilil_sel <= ( doublewidth & dwidth); + niilil : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niilil_data, + o => wire_niilil_o, + sel => wire_niilil_sel + ); + wire_niiliO_data <= ( wire_niiOOl_o & wire_nil00i_o & wire_nilill_o & wire_nilO1O_o); + wire_niiliO_sel <= ( doublewidth & dwidth); + niiliO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niiliO_data, + o => wire_niiliO_o, + sel => wire_niiliO_sel + ); + wire_niilli_data <= ( wire_niiOOO_o & wire_nil00l_dataout & wire_nililO_o & wire_nilO0i_dataout); + wire_niilli_sel <= ( doublewidth & dwidth); + niilli : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niilli_data, + o => wire_niilli_o, + sel => wire_niilli_sel + ); + wire_niilll_data <= ( wire_nil11i_o & wire_nil00O_dataout & wire_niliOi_o & wire_nilO0l_dataout); + wire_niilll_sel <= ( doublewidth & dwidth); + niilll : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niilll_data, + o => wire_niilll_o, + sel => wire_niilll_sel + ); + wire_niillO_data <= ( wire_nil11l_o & wire_nil0ii_o & wire_niliOl_dataout & wire_nilO0O_dataout); + wire_niillO_sel <= ( doublewidth & dwidth); + niillO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niillO_data, + o => wire_niillO_o, + sel => wire_niillO_sel + ); + wire_niilOi_data <= ( wire_nil11O_o & wire_nil0il_o & wire_niliOO_dataout & wire_nilOii_dataout); + wire_niilOi_sel <= ( doublewidth & dwidth); + niilOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niilOi_data, + o => wire_niilOi_o, + sel => wire_niilOi_sel + ); + wire_niilOl_data <= ( wire_nil10i_o & wire_nil0iO_o & wire_nill1i_dataout & wire_nilOil_dataout); + wire_niilOl_sel <= ( doublewidth & dwidth); + niilOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niilOl_data, + o => wire_niilOl_o, + sel => wire_niilOl_sel + ); + wire_niilOO_data <= ( wire_nil10l_o & wire_nil0li_o & wire_nill1l_dataout & wire_nilOiO_dataout); + wire_niilOO_sel <= ( doublewidth & dwidth); + niilOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niilOO_data, + o => wire_niilOO_o, + sel => wire_niilOO_sel + ); + wire_niiO0i_data <= ( wire_nil1iO_o & wire_nil0Ol_o & wire_nill0O_dataout & wire_nilOOi_dataout); + wire_niiO0i_sel <= ( doublewidth & dwidth); + niiO0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niiO0i_data, + o => wire_niiO0i_o, + sel => wire_niiO0i_sel + ); + wire_niiO0l_data <= ( wire_nil1li_o & wire_nil0OO_dataout & wire_nillii_dataout & wire_nilOOl_dataout); + wire_niiO0l_sel <= ( doublewidth & dwidth); + niiO0l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niiO0l_data, + o => wire_niiO0l_o, + sel => wire_niiO0l_sel + ); + wire_niiO0O_data <= ( wire_nil1ll_o & wire_nili1i_dataout & wire_nillil_dataout & wire_nilOOO_dataout); + wire_niiO0O_sel <= ( doublewidth & dwidth); + niiO0O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niiO0O_data, + o => wire_niiO0O_o, + sel => wire_niiO0O_sel + ); + wire_niiO1i_data <= ( wire_nil10O_o & wire_nil0ll_o & wire_nill1O_dataout & wire_nilOli_dataout); + wire_niiO1i_sel <= ( doublewidth & dwidth); + niiO1i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niiO1i_data, + o => wire_niiO1i_o, + sel => wire_niiO1i_sel + ); + wire_niiO1l_data <= ( wire_nil1ii_o & wire_nil0lO_o & wire_nill0i_dataout & wire_nilOll_dataout); + wire_niiO1l_sel <= ( doublewidth & dwidth); + niiO1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niiO1l_data, + o => wire_niiO1l_o, + sel => wire_niiO1l_sel + ); + wire_niiO1O_data <= ( wire_nil1il_o & wire_nil0Oi_o & wire_nill0l_dataout & wire_nilOlO_dataout); + wire_niiO1O_sel <= ( doublewidth & dwidth); + niiO1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niiO1O_data, + o => wire_niiO1O_o, + sel => wire_niiO1O_sel + ); + wire_niiOii_data <= ( wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & niil1i & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o); + wire_niiOii_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOii_data, + o => wire_niiOii_o, + sel => wire_niiOii_sel + ); + wire_niiOil_data <= ( wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o); + wire_niiOil_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOil : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOil_data, + o => wire_niiOil_o, + sel => wire_niiOil_sel + ); + wire_niiOiO_data <= ( wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o); + wire_niiOiO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOiO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOiO_data, + o => wire_niiOiO_o, + sel => wire_niiOiO_sel + ); + wire_niiOli_data <= ( wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o); + wire_niiOli_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOli : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOli_data, + o => wire_niiOli_o, + sel => wire_niiOli_sel + ); + wire_niiOll_data <= ( wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & niii1i & niii1l & niii1O & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o); + wire_niiOll_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOll_data, + o => wire_niiOll_o, + sel => wire_niiOll_sel + ); + wire_niiOlO_data <= ( wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & niii1l & niii1O & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o); + wire_niiOlO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOlO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOlO_data, + o => wire_niiOlO_o, + sel => wire_niiOlO_sel + ); + wire_niiOOi_data <= ( wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & niii1O & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o); + wire_niiOOi_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOOi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOOi_data, + o => wire_niiOOi_o, + sel => wire_niiOOi_sel + ); + wire_niiOOl_data <= ( wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & niii0i & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o); + wire_niiOOl_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOOl : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOOl_data, + o => wire_niiOOl_o, + sel => wire_niiOOl_sel + ); + wire_niiOOO_data <= ( wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & niii0l & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o); + wire_niiOOO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + niiOOO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiOOO_data, + o => wire_niiOOO_o, + sel => wire_niiOOO_sel + ); + wire_nil00i_data <= ( wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o); + wire_nil00i_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil00i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil00i_data, + o => wire_nil00i_o, + sel => wire_nil00i_sel + ); + wire_nil01i_data <= ( wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & niii1i & niii1l & niii1O & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o); + wire_nil01i_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil01i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil01i_data, + o => wire_nil01i_o, + sel => wire_nil01i_sel + ); + wire_nil01l_data <= ( wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & niii1l & niii1O & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o); + wire_nil01l_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil01l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil01l_data, + o => wire_nil01l_o, + sel => wire_nil01l_sel + ); + wire_nil01O_data <= ( wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & niii1O & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o); + wire_nil01O_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil01O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil01O_data, + o => wire_nil01O_o, + sel => wire_nil01O_sel + ); + wire_nil0ii_data <= ( wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o); + wire_nil0ii_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0ii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0ii_data, + o => wire_nil0ii_o, + sel => wire_nil0ii_sel + ); + wire_nil0il_data <= ( wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o & wire_niO1O_o); + wire_nil0il_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0il : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0il_data, + o => wire_nil0il_o, + sel => wire_nil0il_sel + ); + wire_nil0iO_data <= ( wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o); + wire_nil0iO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0iO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0iO_data, + o => wire_nil0iO_o, + sel => wire_nil0iO_sel + ); + wire_nil0li_data <= ( wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o); + wire_nil0li_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0li : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0li_data, + o => wire_nil0li_o, + sel => wire_nil0li_sel + ); + wire_nil0ll_data <= ( wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o); + wire_nil0ll_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0ll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0ll_data, + o => wire_nil0ll_o, + sel => wire_nil0ll_sel + ); + wire_nil0lO_data <= ( wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o); + wire_nil0lO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0lO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0lO_data, + o => wire_nil0lO_o, + sel => wire_nil0lO_sel + ); + wire_nil0Oi_data <= ( wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o & wire_niOil_o); + wire_nil0Oi_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0Oi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0Oi_data, + o => wire_nil0Oi_o, + sel => wire_nil0Oi_sel + ); + wire_nil0Ol_data <= ( wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o & wire_niOil_o & wire_niOiO_o); + wire_nil0Ol_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil0Ol : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil0Ol_data, + o => wire_nil0Ol_o, + sel => wire_nil0Ol_sel + ); + wire_nil10i_data <= ( wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & wire_niO0i_o & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o); + wire_nil10i_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil10i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil10i_data, + o => wire_nil10i_o, + sel => wire_nil10i_sel + ); + wire_nil10l_data <= ( wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & wire_niO0l_o & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o); + wire_nil10l_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil10l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil10l_data, + o => wire_nil10l_o, + sel => wire_nil10l_sel + ); + wire_nil10O_data <= ( wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & wire_niO0O_o & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o); + wire_nil10O_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil10O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil10O_data, + o => wire_nil10O_o, + sel => wire_nil10O_sel + ); + wire_nil11i_data <= ( wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o); + wire_nil11i_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil11i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil11i_data, + o => wire_nil11i_o, + sel => wire_nil11i_sel + ); + wire_nil11l_data <= ( wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & wire_niO1l_o & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o); + wire_nil11l_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil11l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil11l_data, + o => wire_nil11l_o, + sel => wire_nil11l_sel + ); + wire_nil11O_data <= ( wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & wire_niO1O_o & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o); + wire_nil11O_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil11O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil11O_data, + o => wire_nil11O_o, + sel => wire_nil11O_sel + ); + wire_nil1ii_data <= ( wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & wire_niOii_o & niiilO & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o); + wire_nil1ii_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1ii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1ii_data, + o => wire_nil1ii_o, + sel => wire_nil1ii_sel + ); + wire_nil1il_data <= ( wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & wire_niOil_o & niiiOi & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o & wire_niOil_o); + wire_nil1il_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1il : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1il_data, + o => wire_nil1il_o, + sel => wire_nil1il_sel + ); + wire_nil1iO_data <= ( wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & wire_niOiO_o & niiiOl & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o & wire_niOil_o & wire_niOiO_o); + wire_nil1iO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1iO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1iO_data, + o => wire_nil1iO_o, + sel => wire_nil1iO_sel + ); + wire_nil1li_data <= ( wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & wire_niOli_o & niiiOO & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o & wire_niOil_o & wire_niOiO_o & wire_niOli_o); + wire_nil1li_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1li : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1li_data, + o => wire_nil1li_o, + sel => wire_nil1li_sel + ); + wire_nil1ll_data <= ( wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_niOll_o & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o & wire_niO1l_o & wire_niO1O_o & wire_niO0i_o & wire_niO0l_o & wire_niO0O_o & wire_niOii_o & wire_niOil_o & wire_niOiO_o & wire_niOli_o & wire_niOll_o); + wire_nil1ll_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1ll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1ll_data, + o => wire_nil1ll_o, + sel => wire_nil1ll_sel + ); + wire_nil1lO_data <= ( wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & niil1i & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o); + wire_nil1lO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1lO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1lO_data, + o => wire_nil1lO_o, + sel => wire_nil1lO_sel + ); + wire_nil1Oi_data <= ( wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o); + wire_nil1Oi_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1Oi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1Oi_data, + o => wire_nil1Oi_o, + sel => wire_nil1Oi_sel + ); + wire_nil1Ol_data <= ( wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o); + wire_nil1Ol_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1Ol : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1Ol_data, + o => wire_nil1Ol_o, + sel => wire_nil1Ol_sel + ); + wire_nil1OO_data <= ( wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & nii0OO & niii1i & niii1l & niii1O & niii0O & niiiii & niiiil & niiiiO & niiili & niiill & niiilO & niiiOi & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o); + wire_nil1OO_sel <= ( tx_boundary_sel(4 DOWNTO 0)); + nil1OO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nil1OO_data, + o => wire_nil1OO_o, + sel => wire_nil1OO_sel + ); + wire_nili0i_data <= ( wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & niil1i & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & wire_nilii_o); + wire_nili0i_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nili0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nili0i_data, + o => wire_nili0i_o, + sel => wire_nili0i_sel + ); + wire_nili0l_data <= ( wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & wire_nilii_o & wire_nilil_o); + wire_nili0l_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nili0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nili0l_data, + o => wire_nili0l_o, + sel => wire_nili0l_sel + ); + wire_nili0O_data <= ( wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & nii0Ol & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & wire_nilii_o & wire_nilil_o & wire_niliO_o); + wire_nili0O_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nili0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nili0O_data, + o => wire_nili0O_o, + sel => wire_nili0O_sel + ); + wire_nilii_data <= ( wire_niOlO_o & wire_nl01l_o & wire_nliii_o & wire_nlllO_o); + wire_nilii_sel <= ( doublewidth & dwidth); + nilii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nilii_data, + o => wire_nilii_o, + sel => wire_nilii_sel + ); + wire_niliii_data <= ( wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & nii0OO & niii1i & niii1l & niii1O & niii0i & niii0l & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o); + wire_niliii_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + niliii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niliii_data, + o => wire_niliii_o, + sel => wire_niliii_sel + ); + wire_niliil_data <= ( wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & niii1i & niii1l & niii1O & niii0i & niii0l & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o); + wire_niliil_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + niliil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niliil_data, + o => wire_niliil_o, + sel => wire_niliil_sel + ); + wire_niliiO_data <= ( wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & niii1l & niii1O & niii0i & niii0l & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o); + wire_niliiO_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + niliiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niliiO_data, + o => wire_niliiO_o, + sel => wire_niliiO_sel + ); + wire_nilil_data <= ( wire_niOOi_o & wire_nl01O_o & wire_nliil_o & wire_nllOi_o); + wire_nilil_sel <= ( doublewidth & dwidth); + nilil : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nilil_data, + o => wire_nilil_o, + sel => wire_nilil_sel + ); + wire_nilili_data <= ( wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & niii1O & niii0i & niii0l & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o); + wire_nilili_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nilili : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilili_data, + o => wire_nilili_o, + sel => wire_nilili_sel + ); + wire_nilill_data <= ( wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & niii0i & niii0l & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o); + wire_nilill_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nilill : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilill_data, + o => wire_nilill_o, + sel => wire_nilill_sel + ); + wire_nililO_data <= ( wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & wire_nilOO_o & niii0l & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o); + wire_nililO_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nililO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nililO_data, + o => wire_nililO_o, + sel => wire_nililO_sel + ); + wire_niliO_data <= ( wire_niOOl_o & wire_nl00i_o & wire_nliiO_o & wire_nllOl_o); + wire_niliO_sel <= ( doublewidth & dwidth); + niliO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niliO_data, + o => wire_niliO_o, + sel => wire_niliO_sel + ); + wire_niliOi_data <= ( wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_niO1i_o & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o & wire_nilOO_o & wire_niO1i_o); + wire_niliOi_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + niliOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niliOi_data, + o => wire_niliOi_o, + sel => wire_niliOi_sel + ); + wire_nilli_data <= ( wire_niOOO_o & wire_nl00l_o & wire_nlili_o & wire_nllOO_o); + wire_nilli_sel <= ( doublewidth & dwidth); + nilli : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nilli_data, + o => wire_nilli_o, + sel => wire_nilli_sel + ); + wire_nilll_data <= ( wire_nl11i_o & wire_nl00O_o & wire_nlill_o & wire_nlO1i_o); + wire_nilll_sel <= ( doublewidth & dwidth); + nilll : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nilll_data, + o => wire_nilll_o, + sel => wire_nilll_sel + ); + wire_nillll_data <= ( wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & wire_nilii_o & niil1i & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & wire_nilii_o); + wire_nillll_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nillll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nillll_data, + o => wire_nillll_o, + sel => wire_nillll_sel + ); + wire_nilllO_data <= ( wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & wire_nilil_o & nii0Oi & nii0Ol & nii0OO & niii1i & niii1l & niii1O & wire_nilii_o & wire_nilil_o); + wire_nilllO_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nilllO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilllO_data, + o => wire_nilllO_o, + sel => wire_nilllO_sel + ); + wire_nillO_data <= ( wire_nl11l_o & wire_nl0ii_o & wire_nlilO_o & wire_nlO1l_o); + wire_nillO_sel <= ( doublewidth & dwidth); + nillO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nillO_data, + o => wire_nillO_o, + sel => wire_nillO_sel + ); + wire_nillOi_data <= ( wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & wire_niliO_o & nii0Ol & nii0OO & niii1i & niii1l & niii1O & wire_nilii_o & wire_nilil_o & wire_niliO_o); + wire_nillOi_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nillOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nillOi_data, + o => wire_nillOi_o, + sel => wire_nillOi_sel + ); + wire_nillOl_data <= ( wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & wire_nilli_o & nii0OO & niii1i & niii1l & niii1O & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o); + wire_nillOl_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nillOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nillOl_data, + o => wire_nillOl_o, + sel => wire_nillOl_sel + ); + wire_nillOO_data <= ( wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & wire_nilll_o & niii1i & niii1l & niii1O & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o); + wire_nillOO_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nillOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nillOO_data, + o => wire_nillOO_o, + sel => wire_nillOO_sel + ); + wire_nilO1i_data <= ( wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & wire_nillO_o & niii1l & niii1O & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o); + wire_nilO1i_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nilO1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilO1i_data, + o => wire_nilO1i_o, + sel => wire_nilO1i_sel + ); + wire_nilO1l_data <= ( wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & wire_nilOi_o & niii1O & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o); + wire_nilO1l_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nilO1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilO1l_data, + o => wire_nilO1l_o, + sel => wire_nilO1l_sel + ); + wire_nilO1O_data <= ( wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilOl_o & wire_nilii_o & wire_nilil_o & wire_niliO_o & wire_nilli_o & wire_nilll_o & wire_nillO_o & wire_nilOi_o & wire_nilOl_o); + wire_nilO1O_sel <= ( tx_boundary_sel(3 DOWNTO 0)); + nilO1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nilO1O_data, + o => wire_nilO1O_o, + sel => wire_nilO1O_sel + ); + wire_nilOi_data <= ( wire_nl11O_o & wire_nl0il_o & wire_nliOi_o & wire_nlO1O_o); + wire_nilOi_sel <= ( doublewidth & dwidth); + nilOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nilOi_data, + o => wire_nilOi_o, + sel => wire_nilOi_sel + ); + wire_nilOl_data <= ( wire_nl10i_o & wire_nl0iO_o & wire_nliOl_o & wire_nlO0i_o); + wire_nilOl_sel <= ( doublewidth & dwidth); + nilOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nilOl_data, + o => wire_nilOl_o, + sel => wire_nilOl_sel + ); + wire_nilOO_data <= ( wire_nl10l_o & wire_nl0li_o & wire_nliOO_o & wire_nlO0l_o); + wire_nilOO_sel <= ( doublewidth & dwidth); + nilOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nilOO_data, + o => wire_nilOO_o, + sel => wire_nilOO_sel + ); + wire_niO0i_data <= ( wire_nl1iO_o & wire_nl0Ol_o & wire_nll0i_o & wire_nll0i_o); + wire_niO0i_sel <= ( doublewidth & dwidth); + niO0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niO0i_data, + o => wire_niO0i_o, + sel => wire_niO0i_sel + ); + wire_niO0l_data <= ( wire_nl1li_o & wire_nl0OO_o & wire_nll0l_o & wire_nll0l_o); + wire_niO0l_sel <= ( doublewidth & dwidth); + niO0l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niO0l_data, + o => wire_niO0l_o, + sel => wire_niO0l_sel + ); + wire_niO0O_data <= ( wire_nl1ll_o & wire_nli1i_o & wire_nll0O_o & wire_nll0O_o); + wire_niO0O_sel <= ( doublewidth & dwidth); + niO0O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niO0O_data, + o => wire_niO0O_o, + sel => wire_niO0O_sel + ); + wire_niO1i_data <= ( wire_nl10O_o & wire_nl0ll_o & wire_nll1i_o & wire_nlO0O_o); + wire_niO1i_sel <= ( doublewidth & dwidth); + niO1i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niO1i_data, + o => wire_niO1i_o, + sel => wire_niO1i_sel + ); + wire_niO1l_data <= ( wire_nl1ii_o & wire_nl0lO_o & wire_nll1l_o & wire_nll1l_o); + wire_niO1l_sel <= ( doublewidth & dwidth); + niO1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niO1l_data, + o => wire_niO1l_o, + sel => wire_niO1l_sel + ); + wire_niO1O_data <= ( wire_nl1il_o & wire_nl0Oi_o & wire_nll1O_o & wire_nll1O_o); + wire_niO1O_sel <= ( doublewidth & dwidth); + niO1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niO1O_data, + o => wire_niO1O_o, + sel => wire_niO1O_sel + ); + wire_niOii_data <= ( wire_nl1lO_o & wire_nli1l_o & wire_nllii_o & wire_nllii_o); + wire_niOii_sel <= ( doublewidth & dwidth); + niOii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niOii_data, + o => wire_niOii_o, + sel => wire_niOii_sel + ); + wire_niOil_data <= ( wire_nl1Oi_o & wire_nli1O_o & wire_nllil_o & wire_nllil_o); + wire_niOil_sel <= ( doublewidth & dwidth); + niOil : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niOil_data, + o => wire_niOil_o, + sel => wire_niOil_sel + ); + wire_niOiO_data <= ( wire_nl1Ol_o & wire_nli0i_o & wire_nlliO_o & wire_nlliO_o); + wire_niOiO_sel <= ( doublewidth & dwidth); + niOiO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niOiO_data, + o => wire_niOiO_o, + sel => wire_niOiO_sel + ); + wire_niOli_data <= ( wire_nl1OO_o & wire_nli0l_o & wire_nllli_o & wire_nllli_o); + wire_niOli_sel <= ( doublewidth & dwidth); + niOli : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niOli_data, + o => wire_niOli_o, + sel => wire_niOli_sel + ); + wire_niOll_data <= ( wire_nl01i_o & wire_nli0O_o & wire_nllll_o & wire_nllll_o); + wire_niOll_sel <= ( doublewidth & dwidth); + niOll : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_niOll_data, + o => wire_niOll_o, + sel => wire_niOll_sel + ); + wire_niOlO_data <= ( wire_n1Oll_w_lg_o70w & wire_n010O_w_lg_o178w & wire_n1OlO_w_lg_o265w & wire_n1O1l_w_lg_o96w & wire_n1Oll_o & wire_n010O_o & wire_n1OlO_o & wire_n1O1l_o); + wire_niOlO_sel <= ( n0lll & n0liO & n0lii); + niOlO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOlO_data, + o => wire_niOlO_o, + sel => wire_niOlO_sel + ); + wire_niOOi_data <= ( wire_n1Oli_w_lg_o81w & wire_n010l_w_lg_o188w & wire_n1OOi_w_lg_o256w & wire_n1O1O_w_lg_o108w & wire_n1Oli_o & wire_n010l_o & wire_n1OOi_o & wire_n1O1O_o); + wire_niOOi_sel <= ( n0lll & n0liO & n0lii); + niOOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOOi_data, + o => wire_niOOi_o, + sel => wire_niOOi_sel + ); + wire_niOOl_data <= ( wire_n1OiO_w_lg_o94w & wire_n010i_w_lg_o200w & wire_n1OOl_w_lg_o247w & wire_n1O0i_w_lg_o122w & wire_n1OiO_o & wire_n010i_o & wire_n1OOl_o & wire_n1O0i_o); + wire_niOOl_sel <= ( n0lll & n0liO & n0lii); + niOOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOOl_data, + o => wire_niOOl_o, + sel => wire_niOOl_sel + ); + wire_niOOO_data <= ( wire_n1Oil_w_lg_o106w & wire_n011O_w_lg_o211w & wire_n1OOO_w_lg_o238w & wire_n1O0l_w_lg_o133w & wire_n1Oil_o & wire_n011O_o & wire_n1OOO_o & wire_n1O0l_o); + wire_niOOO_sel <= ( n0lll & n0liO & n0lii); + niOOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOOO_data, + o => wire_niOOO_o, + sel => wire_niOOO_sel + ); + wire_nl00i_data <= ( wire_n1Oii_w_lg_o119w & wire_n011l_w_lg_o220w & wire_n1OOl_w_lg_o247w & wire_n1O0i_w_lg_o122w & wire_n1Oii_o & wire_n011l_o & wire_n1OOl_o & wire_n1O0i_o); + wire_nl00i_sel <= ( n0lll & n0liO & n0lii); + nl00i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl00i_data, + o => wire_nl00i_o, + sel => wire_nl00i_sel + ); + wire_nl00l_data <= ( wire_n1O0O_w_lg_o130w & wire_n011i_w_lg_o229w & wire_n1OOO_w_lg_o238w & wire_n1O0l_w_lg_o133w & wire_n1O0O_o & wire_n011i_o & wire_n1OOO_o & wire_n1O0l_o); + wire_nl00l_sel <= ( n0lll & n0liO & n0lii); + nl00l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl00l_data, + o => wire_nl00l_o, + sel => wire_nl00l_sel + ); + wire_nl00O_data <= ( wire_n1O0l_w_lg_o133w & wire_n1OOO_w_lg_o238w & wire_n011i_w_lg_o229w & wire_n1O0O_w_lg_o130w & wire_n1O0l_o & wire_n1OOO_o & wire_n011i_o & wire_n1O0O_o); + wire_nl00O_sel <= ( n0lll & n0liO & n0lii); + nl00O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl00O_data, + o => wire_nl00O_o, + sel => wire_nl00O_sel + ); + wire_nl01i_data <= ( wire_n1OlO_w_lg_o265w & wire_n1O1l_w_lg_o96w & wire_n1Oll_w_lg_o70w & wire_n010O_w_lg_o178w & wire_n1OlO_o & wire_n1O1l_o & wire_n1Oll_o & wire_n010O_o); + wire_nl01i_sel <= ( n0lll & n0liO & n0lii); + nl01i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl01i_data, + o => wire_nl01i_o, + sel => wire_nl01i_sel + ); + wire_nl01l_data <= ( wire_n1OiO_w_lg_o94w & wire_n010i_w_lg_o200w & wire_n1OlO_w_lg_o265w & wire_n1O1l_w_lg_o96w & wire_n1OiO_o & wire_n010i_o & wire_n1OlO_o & wire_n1O1l_o); + wire_nl01l_sel <= ( n0lll & n0liO & n0lii); + nl01l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl01l_data, + o => wire_nl01l_o, + sel => wire_nl01l_sel + ); + wire_nl01O_data <= ( wire_n1Oil_w_lg_o106w & wire_n011O_w_lg_o211w & wire_n1OOi_w_lg_o256w & wire_n1O1O_w_lg_o108w & wire_n1Oil_o & wire_n011O_o & wire_n1OOi_o & wire_n1O1O_o); + wire_nl01O_sel <= ( n0lll & n0liO & n0lii); + nl01O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl01O_data, + o => wire_nl01O_o, + sel => wire_nl01O_sel + ); + wire_nl0ii_data <= ( wire_n1O0i_w_lg_o122w & wire_n1OOl_w_lg_o247w & wire_n011l_w_lg_o220w & wire_n1Oii_w_lg_o119w & wire_n1O0i_o & wire_n1OOl_o & wire_n011l_o & wire_n1Oii_o); + wire_nl0ii_sel <= ( n0lll & n0liO & n0lii); + nl0ii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0ii_data, + o => wire_nl0ii_o, + sel => wire_nl0ii_sel + ); + wire_nl0il_data <= ( wire_n1O1O_w_lg_o108w & wire_n1OOi_w_lg_o256w & wire_n011O_w_lg_o211w & wire_n1Oil_w_lg_o106w & wire_n1O1O_o & wire_n1OOi_o & wire_n011O_o & wire_n1Oil_o); + wire_nl0il_sel <= ( n0lll & n0liO & n0lii); + nl0il : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0il_data, + o => wire_nl0il_o, + sel => wire_nl0il_sel + ); + wire_nl0iO_data <= ( wire_n1O1l_w_lg_o96w & wire_n1OlO_w_lg_o265w & wire_n010i_w_lg_o200w & wire_n1OiO_w_lg_o94w & wire_n1O1l_o & wire_n1OlO_o & wire_n010i_o & wire_n1OiO_o); + wire_nl0iO_sel <= ( n0lll & n0liO & n0lii); + nl0iO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0iO_data, + o => wire_nl0iO_o, + sel => wire_nl0iO_sel + ); + wire_nl0li_data <= ( wire_n1Oli_w_lg_o81w & wire_n1Oli_w_lg_o81w & wire_n1Oli_w_lg_o81w & wire_n1Oli_w_lg_o81w & wire_n1Oli_o & wire_n1Oli_o & wire_n1Oli_o & wire_n1Oli_o); + wire_nl0li_sel <= ( n0lll & n0liO & n0lii); + nl0li : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0li_data, + o => wire_nl0li_o, + sel => wire_nl0li_sel + ); + wire_nl0ll_data <= ( wire_n1Oll_w_lg_o70w & wire_n1Oll_w_lg_o70w & wire_n1Oll_w_lg_o70w & wire_n1Oll_w_lg_o70w & wire_n1Oll_o & wire_n1Oll_o & wire_n1Oll_o & wire_n1Oll_o); + wire_nl0ll_sel <= ( n0lll & n0liO & n0lii); + nl0ll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0ll_data, + o => wire_nl0ll_o, + sel => wire_nl0ll_sel + ); + wire_nl0lO_data <= ( wire_n010i_w_lg_o200w & wire_n1OiO_w_lg_o94w & wire_n1O1l_w_lg_o96w & wire_n1OlO_w_lg_o265w & wire_n010i_o & wire_n1OiO_o & wire_n1O1l_o & wire_n1OlO_o); + wire_nl0lO_sel <= ( n0lll & n0liO & n0lii); + nl0lO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0lO_data, + o => wire_nl0lO_o, + sel => wire_nl0lO_sel + ); + wire_nl0Oi_data <= ( wire_n011O_w_lg_o211w & wire_n1Oil_w_lg_o106w & wire_n1O1O_w_lg_o108w & wire_n1OOi_w_lg_o256w & wire_n011O_o & wire_n1Oil_o & wire_n1O1O_o & wire_n1OOi_o); + wire_nl0Oi_sel <= ( n0lll & n0liO & n0lii); + nl0Oi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Oi_data, + o => wire_nl0Oi_o, + sel => wire_nl0Oi_sel + ); + wire_nl0Ol_data <= ( wire_n011l_w_lg_o220w & wire_n1Oii_w_lg_o119w & wire_n1O0i_w_lg_o122w & wire_n1OOl_w_lg_o247w & wire_n011l_o & wire_n1Oii_o & wire_n1O0i_o & wire_n1OOl_o); + wire_nl0Ol_sel <= ( n0lll & n0liO & n0lii); + nl0Ol : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Ol_data, + o => wire_nl0Ol_o, + sel => wire_nl0Ol_sel + ); + wire_nl0OO_data <= ( wire_n011i_w_lg_o229w & wire_n1O0O_w_lg_o130w & wire_n1O0l_w_lg_o133w & wire_n1OOO_w_lg_o238w & wire_n011i_o & wire_n1O0O_o & wire_n1O0l_o & wire_n1OOO_o); + wire_nl0OO_sel <= ( n0lll & n0liO & n0lii); + nl0OO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OO_data, + o => wire_nl0OO_o, + sel => wire_nl0OO_sel + ); + wire_nl10i_data <= ( wire_n1O0i_w_lg_o122w & wire_n1OOl_w_lg_o247w & wire_n010i_w_lg_o200w & wire_n1OiO_w_lg_o94w & wire_n1O0i_o & wire_n1OOl_o & wire_n010i_o & wire_n1OiO_o); + wire_nl10i_sel <= ( n0lll & n0liO & n0lii); + nl10i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl10i_data, + o => wire_nl10i_o, + sel => wire_nl10i_sel + ); + wire_nl10l_data <= ( wire_n1O1O_w_lg_o108w & wire_n1OOi_w_lg_o256w & wire_n010l_w_lg_o188w & wire_n1Oli_w_lg_o81w & wire_n1O1O_o & wire_n1OOi_o & wire_n010l_o & wire_n1Oli_o); + wire_nl10l_sel <= ( n0lll & n0liO & n0lii); + nl10l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl10l_data, + o => wire_nl10l_o, + sel => wire_nl10l_sel + ); + wire_nl10O_data <= ( wire_n1O1l_w_lg_o96w & wire_n1OlO_w_lg_o265w & wire_n010O_w_lg_o178w & wire_n1Oll_w_lg_o70w & wire_n1O1l_o & wire_n1OlO_o & wire_n010O_o & wire_n1Oll_o); + wire_nl10O_sel <= ( n0lll & n0liO & n0lii); + nl10O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl10O_data, + o => wire_nl10O_o, + sel => wire_nl10O_sel + ); + wire_nl11i_data <= ( wire_n1Oii_w_lg_o119w & wire_n011l_w_lg_o220w & wire_n011i_w_lg_o229w & wire_n1O0O_w_lg_o130w & wire_n1Oii_o & wire_n011l_o & wire_n011i_o & wire_n1O0O_o); + wire_nl11i_sel <= ( n0lll & n0liO & n0lii); + nl11i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl11i_data, + o => wire_nl11i_o, + sel => wire_nl11i_sel + ); + wire_nl11l_data <= ( wire_n1O0O_w_lg_o130w & wire_n011i_w_lg_o229w & wire_n011l_w_lg_o220w & wire_n1Oii_w_lg_o119w & wire_n1O0O_o & wire_n011i_o & wire_n011l_o & wire_n1Oii_o); + wire_nl11l_sel <= ( n0lll & n0liO & n0lii); + nl11l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl11l_data, + o => wire_nl11l_o, + sel => wire_nl11l_sel + ); + wire_nl11O_data <= ( wire_n1O0l_w_lg_o133w & wire_n1OOO_w_lg_o238w & wire_n011O_w_lg_o211w & wire_n1Oil_w_lg_o106w & wire_n1O0l_o & wire_n1OOO_o & wire_n011O_o & wire_n1Oil_o); + wire_nl11O_sel <= ( n0lll & n0liO & n0lii); + nl11O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl11O_data, + o => wire_nl11O_o, + sel => wire_nl11O_sel + ); + wire_nl1ii_data <= ( wire_n010O_w_lg_o178w & wire_n1Oll_w_lg_o70w & wire_n1O1l_w_lg_o96w & wire_n1OlO_w_lg_o265w & wire_n010O_o & wire_n1Oll_o & wire_n1O1l_o & wire_n1OlO_o); + wire_nl1ii_sel <= ( n0lll & n0liO & n0lii); + nl1ii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1ii_data, + o => wire_nl1ii_o, + sel => wire_nl1ii_sel + ); + wire_nl1il_data <= ( wire_n010l_w_lg_o188w & wire_n1Oli_w_lg_o81w & wire_n1O1O_w_lg_o108w & wire_n1OOi_w_lg_o256w & wire_n010l_o & wire_n1Oli_o & wire_n1O1O_o & wire_n1OOi_o); + wire_nl1il_sel <= ( n0lll & n0liO & n0lii); + nl1il : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1il_data, + o => wire_nl1il_o, + sel => wire_nl1il_sel + ); + wire_nl1iO_data <= ( wire_n010i_w_lg_o200w & wire_n1OiO_w_lg_o94w & wire_n1O0i_w_lg_o122w & wire_n1OOl_w_lg_o247w & wire_n010i_o & wire_n1OiO_o & wire_n1O0i_o & wire_n1OOl_o); + wire_nl1iO_sel <= ( n0lll & n0liO & n0lii); + nl1iO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1iO_data, + o => wire_nl1iO_o, + sel => wire_nl1iO_sel + ); + wire_nl1li_data <= ( wire_n011O_w_lg_o211w & wire_n1Oil_w_lg_o106w & wire_n1O0l_w_lg_o133w & wire_n1OOO_w_lg_o238w & wire_n011O_o & wire_n1Oil_o & wire_n1O0l_o & wire_n1OOO_o); + wire_nl1li_sel <= ( n0lll & n0liO & n0lii); + nl1li : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1li_data, + o => wire_nl1li_o, + sel => wire_nl1li_sel + ); + wire_nl1ll_data <= ( wire_n011l_w_lg_o220w & wire_n1Oii_w_lg_o119w & wire_n1O0O_w_lg_o130w & wire_n011i_w_lg_o229w & wire_n011l_o & wire_n1Oii_o & wire_n1O0O_o & wire_n011i_o); + wire_nl1ll_sel <= ( n0lll & n0liO & n0lii); + nl1ll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1ll_data, + o => wire_nl1ll_o, + sel => wire_nl1ll_sel + ); + wire_nl1lO_data <= ( wire_n011i_w_lg_o229w & wire_n1O0O_w_lg_o130w & wire_n1Oii_w_lg_o119w & wire_n011l_w_lg_o220w & wire_n011i_o & wire_n1O0O_o & wire_n1Oii_o & wire_n011l_o); + wire_nl1lO_sel <= ( n0lll & n0liO & n0lii); + nl1lO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1lO_data, + o => wire_nl1lO_o, + sel => wire_nl1lO_sel + ); + wire_nl1Oi_data <= ( wire_n1OOO_w_lg_o238w & wire_n1O0l_w_lg_o133w & wire_n1Oil_w_lg_o106w & wire_n011O_w_lg_o211w & wire_n1OOO_o & wire_n1O0l_o & wire_n1Oil_o & wire_n011O_o); + wire_nl1Oi_sel <= ( n0lll & n0liO & n0lii); + nl1Oi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1Oi_data, + o => wire_nl1Oi_o, + sel => wire_nl1Oi_sel + ); + wire_nl1Ol_data <= ( wire_n1OOl_w_lg_o247w & wire_n1O0i_w_lg_o122w & wire_n1OiO_w_lg_o94w & wire_n010i_w_lg_o200w & wire_n1OOl_o & wire_n1O0i_o & wire_n1OiO_o & wire_n010i_o); + wire_nl1Ol_sel <= ( n0lll & n0liO & n0lii); + nl1Ol : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1Ol_data, + o => wire_nl1Ol_o, + sel => wire_nl1Ol_sel + ); + wire_nl1OO_data <= ( wire_n1OOi_w_lg_o256w & wire_n1O1O_w_lg_o108w & wire_n1Oli_w_lg_o81w & wire_n010l_w_lg_o188w & wire_n1OOi_o & wire_n1O1O_o & wire_n1Oli_o & wire_n010l_o); + wire_nl1OO_sel <= ( n0lll & n0liO & n0lii); + nl1OO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1OO_data, + o => wire_nl1OO_o, + sel => wire_nl1OO_sel + ); + wire_nli0i_data <= ( wire_n1OlO_w_lg_o265w & wire_n1O1l_w_lg_o96w & wire_n1OiO_w_lg_o94w & wire_n010i_w_lg_o200w & wire_n1OlO_o & wire_n1O1l_o & wire_n1OiO_o & wire_n010i_o); + wire_nli0i_sel <= ( n0lll & n0liO & n0lii); + nli0i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli0i_data, + o => wire_nli0i_o, + sel => wire_nli0i_sel + ); + wire_nli0l_data <= ( wire_n010l_w_lg_o188w & wire_n010l_w_lg_o188w & wire_n010l_w_lg_o188w & wire_n010l_w_lg_o188w & wire_n010l_o & wire_n010l_o & wire_n010l_o & wire_n010l_o); + wire_nli0l_sel <= ( n0lll & n0liO & n0lii); + nli0l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli0l_data, + o => wire_nli0l_o, + sel => wire_nli0l_sel + ); + wire_nli0O_data <= ( wire_n010O_w_lg_o178w & wire_n010O_w_lg_o178w & wire_n010O_w_lg_o178w & wire_n010O_w_lg_o178w & wire_n010O_o & wire_n010O_o & wire_n010O_o & wire_n010O_o); + wire_nli0O_sel <= ( n0lll & n0liO & n0lii); + nli0O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli0O_data, + o => wire_nli0O_o, + sel => wire_nli0O_sel + ); + wire_nli1i_data <= ( wire_n1OOO_w_lg_o238w & wire_n1O0l_w_lg_o133w & wire_n1O0O_w_lg_o130w & wire_n011i_w_lg_o229w & wire_n1OOO_o & wire_n1O0l_o & wire_n1O0O_o & wire_n011i_o); + wire_nli1i_sel <= ( n0lll & n0liO & n0lii); + nli1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli1i_data, + o => wire_nli1i_o, + sel => wire_nli1i_sel + ); + wire_nli1l_data <= ( wire_n1OOl_w_lg_o247w & wire_n1O0i_w_lg_o122w & wire_n1Oii_w_lg_o119w & wire_n011l_w_lg_o220w & wire_n1OOl_o & wire_n1O0i_o & wire_n1Oii_o & wire_n011l_o); + wire_nli1l_sel <= ( n0lll & n0liO & n0lii); + nli1l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli1l_data, + o => wire_nli1l_o, + sel => wire_nli1l_sel + ); + wire_nli1O_data <= ( wire_n1OOi_w_lg_o256w & wire_n1O1O_w_lg_o108w & wire_n1Oil_w_lg_o106w & wire_n011O_w_lg_o211w & wire_n1OOi_o & wire_n1O1O_o & wire_n1Oil_o & wire_n011O_o); + wire_nli1O_sel <= ( n0lll & n0liO & n0lii); + nli1O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli1O_data, + o => wire_nli1O_o, + sel => wire_nli1O_sel + ); + wire_nliii_data <= ( wire_n1Oll_w_lg_o70w & wire_n1O1l_w_lg_o96w & wire_n1Oll_o & wire_n1O1l_o); + wire_nliii_sel <= ( n0lll & n0liO); + nliii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nliii_data, + o => wire_nliii_o, + sel => wire_nliii_sel + ); + wire_nliil_data <= ( wire_n1Oli_w_lg_o81w & wire_n1O1O_w_lg_o108w & wire_n1Oli_o & wire_n1O1O_o); + wire_nliil_sel <= ( n0lll & n0liO); + nliil : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nliil_data, + o => wire_nliil_o, + sel => wire_nliil_sel + ); + wire_nliiO_data <= ( wire_n1OiO_w_lg_o94w & wire_n1O0i_w_lg_o122w & wire_n1OiO_o & wire_n1O0i_o); + wire_nliiO_sel <= ( n0lll & n0liO); + nliiO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nliiO_data, + o => wire_nliiO_o, + sel => wire_nliiO_sel + ); + wire_nlili_data <= ( wire_n1Oil_w_lg_o106w & wire_n1O0l_w_lg_o133w & wire_n1Oil_o & wire_n1O0l_o); + wire_nlili_sel <= ( n0lll & n0liO); + nlili : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlili_data, + o => wire_nlili_o, + sel => wire_nlili_sel + ); + wire_nlill_data <= ( wire_n1Oii_w_lg_o119w & wire_n1O0O_w_lg_o130w & wire_n1Oii_o & wire_n1O0O_o); + wire_nlill_sel <= ( n0lll & n0liO); + nlill : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlill_data, + o => wire_nlill_o, + sel => wire_nlill_sel + ); + wire_nlilO_data <= ( wire_n1O0O_w_lg_o130w & wire_n1Oii_w_lg_o119w & wire_n1O0O_o & wire_n1Oii_o); + wire_nlilO_sel <= ( n0lll & n0liO); + nlilO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlilO_data, + o => wire_nlilO_o, + sel => wire_nlilO_sel + ); + wire_nliOi_data <= ( wire_n1O0l_w_lg_o133w & wire_n1Oil_w_lg_o106w & wire_n1O0l_o & wire_n1Oil_o); + wire_nliOi_sel <= ( n0lll & n0liO); + nliOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nliOi_data, + o => wire_nliOi_o, + sel => wire_nliOi_sel + ); + wire_nliOl_data <= ( wire_n1O0i_w_lg_o122w & wire_n1OiO_w_lg_o94w & wire_n1O0i_o & wire_n1OiO_o); + wire_nliOl_sel <= ( n0lll & n0liO); + nliOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nliOl_data, + o => wire_nliOl_o, + sel => wire_nliOl_sel + ); + wire_nliOO_data <= ( wire_n1O1O_w_lg_o108w & wire_n1Oli_w_lg_o81w & wire_n1O1O_o & wire_n1Oli_o); + wire_nliOO_sel <= ( n0lll & n0liO); + nliOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nliOO_data, + o => wire_nliOO_o, + sel => wire_nliOO_sel + ); + wire_nll0i_data <= ( wire_n1OOl_w_lg_o247w & wire_n1OOl_w_lg_o247w & wire_n1OOl_o & wire_n1OOl_o); + wire_nll0i_sel <= ( n0lll & n0liO); + nll0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nll0i_data, + o => wire_nll0i_o, + sel => wire_nll0i_sel + ); + wire_nll0l_data <= ( wire_n1OOO_w_lg_o238w & wire_n1OOO_w_lg_o238w & wire_n1OOO_o & wire_n1OOO_o); + wire_nll0l_sel <= ( n0lll & n0liO); + nll0l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nll0l_data, + o => wire_nll0l_o, + sel => wire_nll0l_sel + ); + wire_nll0O_data <= ( wire_n011i_w_lg_o229w & wire_n011i_w_lg_o229w & wire_n011i_o & wire_n011i_o); + wire_nll0O_sel <= ( n0lll & n0liO); + nll0O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nll0O_data, + o => wire_nll0O_o, + sel => wire_nll0O_sel + ); + wire_nll1i_data <= ( wire_n1O1l_w_lg_o96w & wire_n1Oll_w_lg_o70w & wire_n1O1l_o & wire_n1Oll_o); + wire_nll1i_sel <= ( n0lll & n0liO); + nll1i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nll1i_data, + o => wire_nll1i_o, + sel => wire_nll1i_sel + ); + wire_nll1l_data <= ( wire_n1OlO_w_lg_o265w & wire_n1OlO_w_lg_o265w & wire_n1OlO_o & wire_n1OlO_o); + wire_nll1l_sel <= ( n0lll & n0liO); + nll1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nll1l_data, + o => wire_nll1l_o, + sel => wire_nll1l_sel + ); + wire_nll1O_data <= ( wire_n1OOi_w_lg_o256w & wire_n1OOi_w_lg_o256w & wire_n1OOi_o & wire_n1OOi_o); + wire_nll1O_sel <= ( n0lll & n0liO); + nll1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nll1O_data, + o => wire_nll1O_o, + sel => wire_nll1O_sel + ); + wire_nllii_data <= ( wire_n011l_w_lg_o220w & wire_n011l_w_lg_o220w & wire_n011l_o & wire_n011l_o); + wire_nllii_sel <= ( n0lll & n0liO); + nllii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllii_data, + o => wire_nllii_o, + sel => wire_nllii_sel + ); + wire_nllil_data <= ( wire_n011O_w_lg_o211w & wire_n011O_w_lg_o211w & wire_n011O_o & wire_n011O_o); + wire_nllil_sel <= ( n0lll & n0liO); + nllil : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllil_data, + o => wire_nllil_o, + sel => wire_nllil_sel + ); + wire_nlliO_data <= ( wire_ni0Oll40_w_lg_w_lg_q202w203w & wire_n010i_w_lg_o200w & wire_n010i_o & wire_ni0OlO38_w_lg_w_lg_q195w196w); + wire_nlliO_sel <= ( n0lll & n0liO); + nlliO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlliO_data, + o => wire_nlliO_o, + sel => wire_nlliO_sel + ); + wire_nllli_data <= ( wire_n010l_w_lg_o188w & wire_ni0OOi36_w_lg_w_lg_q187w189w & wire_n010l_o & wire_n010l_o); + wire_nllli_sel <= ( n0lll & n0liO); + nllli : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllli_data, + o => wire_nllli_o, + sel => wire_nllli_sel + ); + wire_nllll_data <= ( wire_n010O_w_lg_o178w & wire_n010O_w_lg_o178w & wire_n010O_o & wire_n010O_o); + wire_nllll_sel <= ( n0lll & n0liO); + nllll : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllll_data, + o => wire_nllll_o, + sel => wire_nllll_sel + ); + wire_nlllO_data <= ( wire_n1OiO_w_lg_o94w & wire_n1O1l_w_lg_o96w & wire_n1OiO_o & wire_n1O1l_o); + wire_nlllO_sel <= ( n0lll & n0liO); + nlllO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlllO_data, + o => wire_nlllO_o, + sel => wire_nlllO_sel + ); + wire_nllOi_data <= ( wire_n1Oil_w_lg_o106w & wire_ni0OOl34_w_lg_w_lg_q160w161w & wire_n1Oil_o & wire_n1O1O_o); + wire_nllOi_sel <= ( n0lll & n0liO); + nllOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOi_data, + o => wire_nllOi_o, + sel => wire_nllOi_sel + ); + wire_nllOl_data <= ( wire_n1Oii_w_lg_o119w & wire_n1O0i_w_lg_o122w & wire_n1Oii_o & wire_n1O0i_o); + wire_nllOl_sel <= ( n0lll & n0liO); + nllOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOl_data, + o => wire_nllOl_o, + sel => wire_nllOl_sel + ); + wire_nllOO_data <= ( wire_n1O0O_w_lg_o130w & wire_n1O0l_w_lg_o133w & wire_n1O0O_o & wire_ni0OOO32_w_lg_w_lg_q139w140w); + wire_nllOO_sel <= ( n0lll & n0liO); + nllOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOO_data, + o => wire_nllOO_o, + sel => wire_nllOO_sel + ); + wire_nlO0i_data <= ( wire_n1O1l_w_lg_o96w & wire_n1OiO_w_lg_o94w & wire_n1O1l_o & wire_n1OiO_o); + wire_nlO0i_sel <= ( n0lll & wire_nii10l22_w_lg_w_lg_q86w87w); + nlO0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO0i_data, + o => wire_nlO0i_o, + sel => wire_nlO0i_sel + ); + wire_nlO0l_data <= ( wire_nii10O20_w_lg_w_lg_q83w84w & wire_n1Oli_w_lg_o81w & wire_n1Oli_o & wire_n1Oli_o); + wire_nlO0l_sel <= ( wire_nii1ii18_w_lg_w_lg_q75w76w & n0liO); + nlO0l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO0l_data, + o => wire_nlO0l_o, + sel => wire_nlO0l_sel + ); + wire_nlO0O_data <= ( wire_n1Oll_w_lg_o70w & wire_n1Oll_w_lg_o70w & wire_nii1il16_w_lg_w_lg_q67w68w & wire_n1Oll_o); + wire_nlO0O_sel <= ( n0lll & n0liO); + nlO0O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO0O_data, + o => wire_nlO0O_o, + sel => wire_nlO0O_sel + ); + wire_nlO1i_data <= ( wire_nii11i30_w_lg_w_lg_q132w134w & wire_n1O0O_w_lg_o130w & wire_n1O0l_o & wire_n1O0O_o); + wire_nlO1i_sel <= ( n0lll & n0liO); + nlO1i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO1i_data, + o => wire_nlO1i_o, + sel => wire_nlO1i_sel + ); + wire_nlO1l_data <= ( wire_n1O0i_w_lg_o122w & wire_nii11l28_w_lg_w_lg_q118w120w & wire_nii11O26_w_lg_w_lg_q115w116w & wire_n1Oii_o); + wire_nlO1l_sel <= ( n0lll & n0liO); + nlO1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO1l_data, + o => wire_nlO1l_o, + sel => wire_nlO1l_sel + ); + wire_nlO1O_data <= ( wire_n1O1O_w_lg_o108w & wire_n1Oil_w_lg_o106w & wire_n1O1O_o & wire_n1Oil_o); + wire_nlO1O_sel <= ( wire_nii10i24_w_lg_w_lg_q100w101w & n0liO); + nlO1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO1O_data, + o => wire_nlO1O_o, + sel => wire_nlO1O_sel + ); + + END RTL; --cycloneiv_hssi_tx_digi_enc_chnl_top +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + +--synthesis_resources = lut 12 mux21 13 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_tx_digi_iq_pipe_tx IS + PORT + ( + fifo_rd_clk_raw : IN STD_LOGIC; + fifo_select_in_centrl : IN STD_LOGIC; + fifo_select_in_pipe_quad_down : IN STD_LOGIC; + fifo_select_in_pipe_quad_up : IN STD_LOGIC; + fifo_select_out_pipe : OUT STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_out_pipe : OUT STD_LOGIC; + refclk_b_raw : IN STD_LOGIC; + rfreerun_tx : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + rpipeline_bypass_tx : IN STD_LOGIC; + soft_reset_rclk1 : IN STD_LOGIC; + soft_reset_wclk1 : IN STD_LOGIC; + tx_div2_sync_in_centrl : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + tx_div2_sync_out_pipe : OUT STD_LOGIC; + txrst : IN STD_LOGIC; + wr_clk_pos_raw : IN STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_out_pipe : OUT STD_LOGIC + ); + END cycloneiv_hssi_tx_digi_iq_pipe_tx; + + ARCHITECTURE RTL OF cycloneiv_hssi_tx_digi_iq_pipe_tx IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n0ii7 : STD_LOGIC := '0'; + SIGNAL n0ii8 : STD_LOGIC := '0'; + SIGNAL n0il5 : STD_LOGIC := '0'; + SIGNAL n0il6 : STD_LOGIC := '0'; + SIGNAL n0li3 : STD_LOGIC := '0'; + SIGNAL n0li4 : STD_LOGIC := '0'; + SIGNAL n0Oi1 : STD_LOGIC := '0'; + SIGNAL n0Oi2 : STD_LOGIC := '0'; + SIGNAL n1l : STD_LOGIC := '0'; + SIGNAL wire_n1i_CLRN : STD_LOGIC; + SIGNAL nO : STD_LOGIC := '0'; + SIGNAL wire_nl_CLRN : STD_LOGIC; + SIGNAL ni : STD_LOGIC := '0'; + SIGNAL wire_nlO_CLRN : STD_LOGIC; + SIGNAL nlOO : STD_LOGIC := '0'; + SIGNAL wire_nlOl_PRN : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O_w_lg_dataout8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_w_lg_rmaster_tx6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset_rclk12w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset_wclk19w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_txrst5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0ll : STD_LOGIC; + BEGIN + + wire_w_lg_rmaster_tx6w(0) <= NOT rmaster_tx; + wire_w_lg_soft_reset_rclk12w(0) <= NOT soft_reset_rclk1; + wire_w_lg_soft_reset_wclk19w(0) <= NOT soft_reset_wclk1; + wire_w_lg_txrst5w(0) <= NOT txrst; + fifo_select_out_pipe <= wire_nllO_dataout; + n0ll <= '1'; + rd_enable_out_pipe <= wire_nlli_dataout; + tx_div2_sync_out_pipe <= wire_nlOi_dataout; + wr_enable_out_pipe <= wire_nlll_dataout; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0ii7 <= n0ii8; + END IF; + if (now = 0 ns) then + n0ii7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0ii8 <= n0ii7; + END IF; + END PROCESS; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0il5 <= n0il6; + END IF; + if (now = 0 ns) then + n0il5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0il6 <= n0il5; + END IF; + END PROCESS; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0li3 <= n0li4; + END IF; + if (now = 0 ns) then + n0li3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0li4 <= n0li3; + END IF; + END PROCESS; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0Oi1 <= n0Oi2; + END IF; + if (now = 0 ns) then + n0Oi1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk_b_raw) + BEGIN + IF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN n0Oi2 <= n0Oi1; + END IF; + END PROCESS; + PROCESS (refclk_b_raw, wire_n1O_dataout, wire_n1i_CLRN) + BEGIN + IF (wire_n1O_dataout = '1') THEN + n1l <= '1'; + ELSIF (wire_n1i_CLRN = '0') THEN + n1l <= '0'; + ELSIF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN + n1l <= wire_nli_dataout; + END IF; + if (now = 0 ns) then + n1l <= '1' after 1 ps; + end if; + END PROCESS; + wire_n1i_CLRN <= (n0il6 XOR n0il5); + PROCESS (fifo_rd_clk_raw, wire_nl_CLRN) + BEGIN + IF (wire_nl_CLRN = '0') THEN + nO <= '0'; + ELSIF (fifo_rd_clk_raw = '1' AND fifo_rd_clk_raw'event) THEN + nO <= wire_n0i_dataout; + END IF; + END PROCESS; + wire_nl_CLRN <= ((n0Oi2 XOR n0Oi1) AND wire_w_lg_soft_reset_rclk12w(0)); + PROCESS (refclk_b_raw, txrst, wire_nlO_CLRN) + BEGIN + IF (txrst = '1') THEN + ni <= '1'; + ELSIF (wire_nlO_CLRN = '0') THEN + ni <= '0'; + ELSIF (refclk_b_raw = '1' AND refclk_b_raw'event) THEN + ni <= wire_nil_dataout; + END IF; + if (now = 0 ns) then + ni <= '1' after 1 ps; + end if; + END PROCESS; + wire_nlO_CLRN <= (n0li4 XOR n0li3); + PROCESS (wr_clk_pos_raw, wire_nlOl_PRN, soft_reset_wclk1) + BEGIN + IF (wire_nlOl_PRN = '0') THEN + nlOO <= '1'; + ELSIF (soft_reset_wclk1 = '1') THEN + nlOO <= '0'; + ELSIF (wr_clk_pos_raw = '1' AND wr_clk_pos_raw'event) THEN + nlOO <= wire_n0O_dataout; + END IF; + END PROCESS; + wire_nlOl_PRN <= (n0ii8 XOR n0ii7); + wire_n0i_dataout <= wire_n0l_dataout WHEN wire_w_lg_rmaster_tx6w(0) = '1' ELSE rd_enable_in_centrl; + wire_n0l_dataout <= rd_enable_in_pipe_quad_up WHEN rmaster_up_tx = '1' ELSE rd_enable_in_pipe_quad_down; + wire_n0O_dataout <= wire_nii_dataout WHEN wire_w_lg_rmaster_tx6w(0) = '1' ELSE wr_enable_in_centrl; + wire_n1O_dataout <= txrst AND NOT(rfreerun_tx); + wire_n1O_w_lg_dataout8w(0) <= NOT wire_n1O_dataout; + wire_nii_dataout <= wr_enable_in_pipe_quad_up WHEN rmaster_up_tx = '1' ELSE wr_enable_in_pipe_quad_down; + wire_nil_dataout <= wire_niO_dataout WHEN wire_w_lg_rmaster_tx6w(0) = '1' ELSE fifo_select_in_centrl; + wire_niO_dataout <= fifo_select_in_pipe_quad_up WHEN rmaster_up_tx = '1' ELSE fifo_select_in_pipe_quad_down; + wire_nli_dataout <= wire_nll_dataout WHEN wire_w_lg_rmaster_tx6w(0) = '1' ELSE tx_div2_sync_in_centrl; + wire_nll_dataout <= tx_div2_sync_in_pipe_quad_up WHEN rmaster_up_tx = '1' ELSE tx_div2_sync_in_pipe_quad_down; + wire_nlli_dataout <= wire_n0i_dataout WHEN rpipeline_bypass_tx = '1' ELSE nO; + wire_nlll_dataout <= wire_n0O_dataout WHEN rpipeline_bypass_tx = '1' ELSE nlOO; + wire_nllO_dataout <= wire_nil_dataout WHEN rpipeline_bypass_tx = '1' ELSE ni; + wire_nlOi_dataout <= wire_nli_dataout WHEN rpipeline_bypass_tx = '1' ELSE n1l; + + END RTL; --cycloneiv_hssi_tx_digi_iq_pipe_tx +--synopsys translate_on +--VALID FILE + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_tx_digi IS + PORT ( + + -- Reset inputs + txpcs_rst : IN STD_LOGIC; -- TX PCS resets + + -- Scan inputs + scan_mode : IN STD_LOGIC; -- 1'b1 = scan mode active; + -- 1'b0 = normal mode + -- TX PCS channel inputs/outputs + txd : IN STD_LOGIC_VECTOR(43 DOWNTO 0); -- TXD data bus from PLD + pld_tx_clk : IN STD_LOGIC; -- XGMII tx clock for this lane from PLD + polinv_tx : IN STD_LOGIC; -- TX polarity inversion dynamic control signal + -- 8-bit tx data from 10G ethernet + -- tx state machine (tx_sm) + -- 1-bit tx control from 10G ethernet tx state machine (tx_sm) + -- Global parallel clock from TX PLL + -- Individual TX PMA clock from TX PMA Extension + -- Dynamic signal causes reverse loopback + rev_loop_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- 10 bit data from RX rate matching FIFO, reverse loopback + wrenable_tx : IN STD_LOGIC; -- TX phase comp. FIFO write enable control signal + rddisable_tx : IN STD_LOGIC; -- TX phase comp. FIFO read disable control signal + phfifourst_tx : IN STD_LOGIC; -- TX phase comp. FIFO user reset + + -- TX PIPE interface signals + txdetectrxloopback : IN STD_LOGIC; + --input txelecidle; txd[9] + --input txcompliance; txd[10] and txd[32] + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + + revloopback : IN STD_LOGIC; + + -- push through TX Phase Comp FIFO + txswing : IN STD_LOGIC; + pcs_txdeemph : IN STD_LOGIC; + pcs_txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX PIPE interface signals + rxpolarity : IN STD_LOGIC; + polinv_rx : IN STD_LOGIC; + + --PRBS-CID dynamic signal + + full_tx : OUT STD_LOGIC; -- TX Phase comp. FIFO full flag + empty_tx : OUT STD_LOGIC; -- TX Phase comp. FIFO empty flag + tx_data_ts : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + tx_ctl_ts : IN STD_LOGIC; + refclk_pma : IN STD_LOGIC; + txpma_local_clk : IN STD_LOGIC; + tx_clk_out : OUT STD_LOGIC; + tx_data_tc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8-bit tx data from tx_ctrl to XAUI TX SM + tx_ctl_tc : OUT STD_LOGIC; -- TX control/TX data bit 8 from tx_ctrl to XAUI TX SM + pudr : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); -- TX PCS 20-bit code group bus to TX PMA + rd_enable_sync : OUT STD_LOGIC; + refclk_b : OUT STD_LOGIC; + txlp20b : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); -- tx 20-bit code group bus to RX PCS for loopback + tx_pipe_clk : OUT STD_LOGIC; -- TX PIPE interface clock + encoder_testbus : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- Test bus from 8B10B encoder + tx_ctrl_testbus : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- Test bus from TX FIFO + tx_pipe_soft_reset : OUT STD_LOGIC; -- TX PIPE soft reset from TX FIFO + tx_pipe_electidle : OUT STD_LOGIC; -- TxElecIdle output from TX FIFO + + -- TX PIPE interface signals + txdetectrxloopback_int : OUT STD_LOGIC; + --output txelecidle; txd[9] + --output txcompliance; txd[10] and txd[32] + powerdown_int : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + revloopback_int : OUT STD_LOGIC; + + -- push through TX Phase Comp FIFO + phfifo_txswing : OUT STD_LOGIC; + phfifo_txdeemph : OUT STD_LOGIC; + phfifo_txmargin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX PIPE interface signals + rxpolarity_int : OUT STD_LOGIC; + polinv_rx_int : OUT STD_LOGIC; + + -- TX PCS CRAMs + rrev_loopbk : IN STD_LOGIC; -- CRAM - Enable dynamic Reverse, PIPE mode + rev_loopbk : IN STD_LOGIC; + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + gray_eidleinfersel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rbisten_tx : IN STD_LOGIC; -- ENBIST CRAM + rforce_disp : IN STD_LOGIC; -- Acting with TXD[9, 19] forces current disparity to 1 or 0 + rib_force_disp : IN STD_LOGIC; -- Disparity force CRAM in IB mode + rforce_echar : IN STD_LOGIC; -- Force /E/ char CRAM + rforce_kchar : IN STD_LOGIC; -- Force /K/ char CRAM + rendec_tx : IN STD_LOGIC; -- Enable 8B/10B encoder CRAM + rge_xaui_tx : IN STD_LOGIC; -- GIGE Idle test enable CRAM + rdwidth_tx : IN STD_LOGIC; -- TX parallel interface data width CRAM + rtxfifo_dis : IN STD_LOGIC; -- TX FIFO disable CRAM + rcascaded_8b10b_en_tx : IN STD_LOGIC; -- Caascaded 8b/10b encoder enable CRAM + rprbsen_tx : IN STD_LOGIC; -- PRBS generator enable CRAM + rprbs_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- PRBS selection CRAM + rbist_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- BIST selection CRAM + rcxpat_chnl_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- CRPAT or CJPAT selection CRAM + renpolinv_tx : IN STD_LOGIC; -- TX Polarity inversion enable CRAM + rphfifopldentx : IN STD_LOGIC; -- TX phase comp. FIFO PLD read/write enable CRAM + rphfifoursttx : IN STD_LOGIC; -- TX phase comp. FIFO user reset enable CRAM + rfreerun_tx : IN STD_LOGIC; -- TX_CLK out free running during TX PCS reset enable CRAM + rtxwrclksel : IN STD_LOGIC; -- TX FIFO write clock selection CRAM + rtxrdclksel : IN STD_LOGIC; -- TX FIFO read clock selection CRAM + renbitrev_tx : IN STD_LOGIC; -- TX bit reversal enable CRAM + rensymswap_tx : IN STD_LOGIC; -- TX symbol swap enable CRAM + r8b10b_enc_ibm_en : IN STD_LOGIC; -- 8B10B Encoder fix enable CRAM + rtxfifo_lowlatency_en : IN STD_LOGIC; -- TX FIFO low latency enable CRAM + rpmadwidth_tx : IN STD_LOGIC; -- TX PCS to TX PMA data width selection CRAM + rpma_doublewidth_tx : IN STD_LOGIC; -- PCS/PMA double width (16/20) selection CRAM + rtx_pipe_enable : IN STD_LOGIC; -- TX PIPE enable CRAM + -- CID pattern to be 0 or 1 + -- Length of CID pattern in cycles + + -- Common PCS CRAMs + rindv_tx : IN STD_LOGIC; -- TX SM bypassing CRAM + rendec_data_sel_tx : IN STD_LOGIC; -- TX 8B10B encoder data in selection CRAM + rtxpcsbypass_en : IN STD_LOGIC; -- CRAM for enable low-latency PCS bypass mode + rtxpcsclkpwdn : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + rcid_pattern_tx : IN STD_LOGIC; + rcid_len_tx : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- new signal inputs for bundling + tx_div2_sync_in_centrl : IN STD_LOGIC; + tx_div2_sync_in_quad_up : IN STD_LOGIC; + tx_div2_sync_in_quad_down : IN STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_quad_up : IN STD_LOGIC; + wr_enable_in_quad_down : IN STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_quad_up : IN STD_LOGIC; + rd_enable_in_quad_down : IN STD_LOGIC; + fifo_select_in_centrl : IN STD_LOGIC; + fifo_select_in_quad_up : IN STD_LOGIC; + fifo_select_in_quad_down : IN STD_LOGIC; + + dis_pc_byte : IN STD_LOGIC; + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_in_centrl : IN STD_LOGIC; + reset_pc_ptrs_in_quad_up : IN STD_LOGIC; + reset_pc_ptrs_in_quad_down : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + fifo_select_in_pipe_quad_up : IN STD_LOGIC; + fifo_select_in_pipe_quad_down : IN STD_LOGIC; + + -- new MDIO inputs for bundling and auto speed + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + rself_sw_en_tx : IN STD_LOGIC; + rpipeline_bypass_tx : IN STD_LOGIC; + rphfifo_regmode_tx : IN STD_LOGIC; + + -- new outputs for bundling and auto speed + + -- new signals in this module for bundling and auto speed + + --CRAM for TX bitslip + rtxbitslip_en : IN STD_LOGIC; + tx_div2_sync_out_pipe_up : OUT STD_LOGIC; + fifo_select_out_pipe_up : OUT STD_LOGIC; + wr_enable_out_pipe_up : OUT STD_LOGIC; + rd_enable_out_pipe_up : OUT STD_LOGIC; + tx_div2_sync_out_pipe_down : OUT STD_LOGIC; + fifo_select_out_pipe_down : OUT STD_LOGIC; + wr_enable_out_pipe_down : OUT STD_LOGIC; + rd_enable_out_pipe_down : OUT STD_LOGIC; + prbs_cid_en : IN STD_LOGIC; + tx_boundary_sel : IN STD_LOGIC_VECTOR(4 DOWNTO 0) + ); +END cycloneiv_hssi_tx_digi; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_digi IS + COMPONENT cycloneiv_hssi_tx_digi_prbs_gen + PORT ( + tx_clk : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + rprbs_en_tx : IN STD_LOGIC; + rpmadwidth_tx : IN STD_LOGIC; + rpma_doublewidth_tx : IN STD_LOGIC; + rprbs_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + cid_en : IN STD_LOGIC; + rcid_len : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rcid_pattern : IN STD_LOGIC; + prbs_out : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_digi_txclk_ctl + PORT ( + pld_tx_clk : IN STD_LOGIC; + refclk_pma : IN STD_LOGIC; + txpma_local_clk : IN STD_LOGIC; + txrst : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + tx_div2_sync_centrl : IN STD_LOGIC; + tx_div2_sync_quad_up : IN STD_LOGIC; + tx_div2_sync_quad_down : IN STD_LOGIC; + rindv_tx : IN STD_LOGIC; + rtxwrclksel : IN STD_LOGIC; + rtxrdclksel : IN STD_LOGIC; + rdwidth_tx : IN STD_LOGIC; + rfreerun_tx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rtxpcsclkpwdn : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + rself_sw_en_tx : IN STD_LOGIC; + refclk_b : OUT STD_LOGIC; + wr_clk_pos : OUT STD_LOGIC; + fifo_rd_clk : OUT STD_LOGIC; + tx_clk_out : OUT STD_LOGIC; + refclk_b_raw : OUT STD_LOGIC; + wr_clk_pos_raw : OUT STD_LOGIC; + fifo_rd_clk_raw : OUT STD_LOGIC; + tx_div2_sync_out : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_digi_enc_chnl_top + PORT ( + rst : IN STD_LOGIC; + clk : IN STD_LOGIC; + cascaded_8b10b_en : IN STD_LOGIC; + rendec_data_sel_tx : IN STD_LOGIC; + rrev_loopbk : IN STD_LOGIC; + rev_loopbk : IN STD_LOGIC; + dwidth : IN STD_LOGIC; + doublewidth : IN STD_LOGIC; + endec : IN STD_LOGIC; + ge_xaui_sel : IN STD_LOGIC; + rforce_disp : IN STD_LOGIC; + ib_force_disparity : IN STD_LOGIC; + prbs_en : IN STD_LOGIC; + r8b10b_enc_ibm_en : IN STD_LOGIC; + rev_loop_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + tx_ctl_ts : IN STD_LOGIC; + tx_ctl_tc : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + tx_data_ts : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + txd_extend_tc : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + tx_data_tc : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + tx_data_9_tc : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + tx_data_pg : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + k_det : IN STD_LOGIC; + d21_5_eq_n : IN STD_LOGIC; + d2_2_eq_n : IN STD_LOGIC; + renpolinv_tx : IN STD_LOGIC; + enpolinv_tx : IN STD_LOGIC; + renbitrev_tx : IN STD_LOGIC; + rensymswap_tx : IN STD_LOGIC; + rtxbitslip_en : IN STD_LOGIC; + tx_boundary_sel : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + pudr : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + txlp20b : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + tx_data_pre_en : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + tx_data_9_pre_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + tx_ctl_pre_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + disp_out_3b : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_digi_iq_pipe_tx + PORT ( + refclk_b_raw : IN STD_LOGIC; + wr_clk_pos_raw : IN STD_LOGIC; + fifo_rd_clk_raw : IN STD_LOGIC; + txrst : IN STD_LOGIC; + soft_reset_rclk1 : IN STD_LOGIC; + soft_reset_wclk1 : IN STD_LOGIC; + tx_div2_sync_in_centrl : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + fifo_select_in_centrl : IN STD_LOGIC; + fifo_select_in_pipe_quad_up : IN STD_LOGIC; + fifo_select_in_pipe_quad_down : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + rpipeline_bypass_tx : IN STD_LOGIC; + rfreerun_tx : IN STD_LOGIC; + tx_div2_sync_out_pipe : OUT STD_LOGIC; + fifo_select_out_pipe : OUT STD_LOGIC; + wr_enable_out_pipe : OUT STD_LOGIC; + rd_enable_out_pipe : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_digi_bist_gen + PORT ( + tx_clk : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + rbisten_tx : IN STD_LOGIC; + rpmadwidth_tx : IN STD_LOGIC; + rpma_doublewidth_tx : IN STD_LOGIC; + rdwidth_tx : IN STD_LOGIC; + rbist_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcxpat_chnl_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + bist_data_sg : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + bist_ctl_sg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_digi_tx_ctrl + PORT ( + soft_reset : IN STD_LOGIC; + fifo_wr_clk : IN STD_LOGIC; + fifo_rd_clk : IN STD_LOGIC; + refclk_b_in : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rindv_tx : IN STD_LOGIC; + p_rlpbk : IN STD_LOGIC; + selftest_en : IN STD_LOGIC; + rdwidth_tx : IN STD_LOGIC; + txfifo_dis : IN STD_LOGIC; + rtxfifo_urst_en : IN STD_LOGIC; + txfifo_urst : IN STD_LOGIC; + rtxfifo_lowlatency_en : IN STD_LOGIC; + rtxphfifopldctl_en : IN STD_LOGIC; + rtx_pipe_enable : IN STD_LOGIC; + pld_we : IN STD_LOGIC; + pld_rd_dis : IN STD_LOGIC; + txd : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + txd_extend : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rforce_disp : IN STD_LOGIC; + tx_data_sg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + tx_control_sg : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rxd_lpbk : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + redund_ctl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + txd_redun : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + rforce_kchar : IN STD_LOGIC; + rforce_echar : IN STD_LOGIC; + rtxpcsbypass_en : IN STD_LOGIC; + txdetectrxloopback : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + revloopback : IN STD_LOGIC; + txswing : IN STD_LOGIC; + txdeemph : IN STD_LOGIC; + txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rxpolarity : IN STD_LOGIC; + polinv_rx : IN STD_LOGIC; + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + dis_pc_byte : IN STD_LOGIC; + wr_enable_centrl : IN STD_LOGIC; + wr_enable_quad_up : IN STD_LOGIC; + wr_enable_quad_down : IN STD_LOGIC; + rd_enable_centrl : IN STD_LOGIC; + rd_enable_quad_up : IN STD_LOGIC; + rd_enable_quad_down : IN STD_LOGIC; + fifo_select_in_centrl : IN STD_LOGIC; + fifo_select_in_quad_up : IN STD_LOGIC; + fifo_select_in_quad_down : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rphfifo_regmode_tx : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + txd_extend_tc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + tx_data_tc : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + tx_ctl_tc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + tx_data_9_tc : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rd_enable_sync : OUT STD_LOGIC; + k_det : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + d21_5_eq_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + d2_2_eq_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + wr_enable_out : OUT STD_LOGIC; + rd_enable_out : OUT STD_LOGIC; + fifo_select_out : OUT STD_LOGIC; + ph_fifo_full : OUT STD_LOGIC; + ph_fifo_empty : OUT STD_LOGIC; + soft_reset_wclk1 : OUT STD_LOGIC; + soft_reset_rclk1 : OUT STD_LOGIC; + pipe_electric_idle : OUT STD_LOGIC; + txdetectrxloopback_int : OUT STD_LOGIC; + powerdown_int : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + revloopback_int : OUT STD_LOGIC; + phfifo_txswing : OUT STD_LOGIC; + phfifo_txdeemph : OUT STD_LOGIC; + phfifo_txmargin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rxpolarity_int : OUT STD_LOGIC; + polinv_rx_int : OUT STD_LOGIC; + gray_eidleinfersel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + wr_enable2 : OUT STD_LOGIC; + wptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rd_enable2 : OUT STD_LOGIC; + rptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT; + + SIGNAL refclk_b_raw : STD_LOGIC; + SIGNAL wr_clk_pos_raw : STD_LOGIC; + SIGNAL fifo_rd_clk_raw : STD_LOGIC; + SIGNAL nc_new_bundle1 : STD_LOGIC; + SIGNAL nc_new_bundle2 : STD_LOGIC; + SIGNAL nc_new_bundle3 : STD_LOGIC; + SIGNAL fifo_select_out_testbus : STD_LOGIC; + -- removed + -- txfifo_shared_sig_in_ch0 + -- txfifo_shared_sig_in_q0_ch0 + -- rphfifo_master_sel_tx + -- txfifo_shared_sig_out + + -- Wiring section + SIGNAL wr_clk_pos : STD_LOGIC; + SIGNAL fifo_rd_clk : STD_LOGIC; + SIGNAL soft_reset_wclk1 : STD_LOGIC; + SIGNAL tx_data_tc_high : STD_LOGIC_VECTOR(7 DOWNTO 0); -- high 8-bit tx data from tx_ctrl + -- low 8-bit tx data from tx_ctrl + SIGNAL tx_ctl_tc_high : STD_LOGIC; -- high tx control/tx data bit 8 from tx_ctrl + -- low tx control/tx data bit 8 from tx_ctrl + SIGNAL tx_ctl_pre_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL tx_data_pre_en : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL tx_data_9_pre_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL tx_data_sg : STD_LOGIC_VECTOR(15 DOWNTO 0); -- 16-bit data sequence generated by bist_gen. + SIGNAL tx_control_sg : STD_LOGIC_VECTOR(1 DOWNTO 0); -- 2-bit control sequence generated by selftest_gen. + SIGNAL tx_data_9_tc : STD_LOGIC_VECTOR(1 DOWNTO 0); -- tx data bit 9 from tx_ctrl + SIGNAL tx_data_pg : STD_LOGIC_VECTOR(19 DOWNTO 0); -- 20-bit tx code group generated by prbs_gen + SIGNAL soft_reset_int : STD_LOGIC; + SIGNAL k_det : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL d21_5_eq_n : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL d2_2_eq_n : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txd_extend_tc : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Extend txd by 2 bits. Used to force disparity. This will go to the encoder. + -- THis is input from the PLD Fabric + SIGNAL disp_out_3b : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Disparity output from encoder for testbus + SIGNAL wr_enable2 : STD_LOGIC; + SIGNAL wptr_bin : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rd_enable2 : STD_LOGIC; + SIGNAL rptr_bin : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL tx_data_tc_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL tx_ctl_tc_temp : STD_LOGIC_VECTOR(1 DOWNTO 0); + -- X-HDL generated signals + + SIGNAL xhdl28 : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL xhdl29 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL xhdl30 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL xhdl31 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL xhdl32 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL full_tx_xhdl3 : STD_LOGIC; + SIGNAL empty_tx_xhdl0 : STD_LOGIC; + SIGNAL tx_clk_out_xhdl17 : STD_LOGIC; + SIGNAL tx_data_tc_xhdl19 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL tx_ctl_tc_xhdl18 : STD_LOGIC; + SIGNAL pudr_xhdl10 : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL rd_enable_sync_xhdl13 : STD_LOGIC; + SIGNAL refclk_b_xhdl14 : STD_LOGIC; + SIGNAL txlp20b_xhdl25 : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL tx_pipe_soft_reset_xhdl23 : STD_LOGIC; + SIGNAL tx_pipe_electidle_xhdl22 : STD_LOGIC; + SIGNAL txdetectrxloopback_int_xhdl24 : STD_LOGIC; + SIGNAL powerdown_int_xhdl9 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL revloopback_int_xhdl15 : STD_LOGIC; + SIGNAL phfifo_txswing_xhdl7 : STD_LOGIC; + SIGNAL phfifo_txdeemph_xhdl5 : STD_LOGIC; + SIGNAL phfifo_txmargin_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxpolarity_int_xhdl16 : STD_LOGIC; + SIGNAL polinv_rx_int_xhdl8 : STD_LOGIC; + SIGNAL gray_eidleinfersel_xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL tx_div2_sync_out_pipe_up_xhdl21 : STD_LOGIC; + SIGNAL fifo_select_out_pipe_up_xhdl2 : STD_LOGIC; + SIGNAL wr_enable_out_pipe_up_xhdl27 : STD_LOGIC; + SIGNAL rd_enable_out_pipe_up_xhdl12 : STD_LOGIC; + SIGNAL tx_div2_sync_out_pipe_down_xhdl20 : STD_LOGIC; + SIGNAL fifo_select_out_pipe_down_xhdl1 : STD_LOGIC; + SIGNAL wr_enable_out_pipe_down_xhdl26 : STD_LOGIC; + SIGNAL rd_enable_out_pipe_down_xhdl11 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + full_tx <= full_tx_xhdl3; + empty_tx <= empty_tx_xhdl0; + tx_clk_out <= tx_clk_out_xhdl17; + tx_data_tc <= tx_data_tc_xhdl19; + tx_ctl_tc <= tx_ctl_tc_xhdl18; + pudr <= pudr_xhdl10; + rd_enable_sync <= rd_enable_sync_xhdl13; + refclk_b <= refclk_b_xhdl14; + txlp20b <= txlp20b_xhdl25; + tx_pipe_soft_reset <= tx_pipe_soft_reset_xhdl23; + tx_pipe_electidle <= tx_pipe_electidle_xhdl22; + txdetectrxloopback_int <= txdetectrxloopback_int_xhdl24; + powerdown_int <= powerdown_int_xhdl9; + revloopback_int <= revloopback_int_xhdl15; + phfifo_txswing <= phfifo_txswing_xhdl7; + phfifo_txdeemph <= phfifo_txdeemph_xhdl5; + phfifo_txmargin <= phfifo_txmargin_xhdl6; + rxpolarity_int <= rxpolarity_int_xhdl16; + polinv_rx_int <= polinv_rx_int_xhdl8; + gray_eidleinfersel <= gray_eidleinfersel_xhdl4; + tx_div2_sync_out_pipe_up <= tx_div2_sync_out_pipe_up_xhdl21; + fifo_select_out_pipe_up <= fifo_select_out_pipe_up_xhdl2; + wr_enable_out_pipe_up <= wr_enable_out_pipe_up_xhdl27; + rd_enable_out_pipe_up <= rd_enable_out_pipe_up_xhdl12; + tx_div2_sync_out_pipe_down <= tx_div2_sync_out_pipe_down_xhdl20; + fifo_select_out_pipe_down <= fifo_select_out_pipe_down_xhdl1; + wr_enable_out_pipe_down <= wr_enable_out_pipe_down_xhdl26; + rd_enable_out_pipe_down <= rd_enable_out_pipe_down_xhdl11; + + -- Gated soft reset by scan_mode signal + --assign soft_reset_int = (scan_mode) ? 1'b0 : txpcs_rst; + soft_reset_int <= txpcs_rst; + + -- TX PIPE interface clock + --assign tx_pipe_clk = wr_clk_pos; + tx_pipe_clk <= fifo_rd_clk; + + -- Encoder testbus + encoder_testbus <= (disp_out_3b & pudr_xhdl10(7 DOWNTO 0)); + + -- TX FIFO testbus + tx_ctrl_testbus <= ('0' & fifo_select_out_testbus & wr_enable2 & wptr_bin & rd_enable2 & rptr_bin); + + -- Clock selection module + + + txclk_ctl_1 : cycloneiv_hssi_tx_digi_txclk_ctl + PORT MAP ( + pld_tx_clk => pld_tx_clk, + refclk_pma => refclk_pma, + txpma_local_clk => txpma_local_clk, + txrst => txpcs_rst, + scan_mode => scan_mode, + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + tx_div2_sync_centrl => tx_div2_sync_in_centrl, + tx_div2_sync_quad_up => tx_div2_sync_in_quad_up, + tx_div2_sync_quad_down => tx_div2_sync_in_quad_down, + rindv_tx => rindv_tx, + rtxwrclksel => rtxwrclksel, + rtxrdclksel => rtxrdclksel, + rdwidth_tx => rdwidth_tx, + rfreerun_tx => rfreerun_tx, + rauto_speed_ena => rauto_speed_ena, + rfreq_sel => rfreq_sel, + rtxpcsclkpwdn => rtxpcsclkpwdn, + rmaster_tx => rmaster_tx, + rmaster_up_tx => rmaster_up_tx, + rself_sw_en_tx => rself_sw_en_tx, + refclk_b => refclk_b_xhdl14, + wr_clk_pos => wr_clk_pos, + fifo_rd_clk => fifo_rd_clk, + tx_clk_out => tx_clk_out_xhdl17, + refclk_b_raw => refclk_b_raw, + wr_clk_pos_raw => wr_clk_pos_raw, + fifo_rd_clk_raw => fifo_rd_clk_raw, + tx_div2_sync_out => nc_new_bundle1 + ); + + -- TX Phase compensation FIFO module + + + -- S. Park 11/29/07 - Phase FIFO bypass feature removed + -- .txfifo_dis (rtxfifo_dis), + xhdl28 <= (txd(42 DOWNTO 33) & txd(31 DOWNTO 22) & txd(20 DOWNTO 11) & txd(9 DOWNTO 0)); + xhdl29 <= (txd(43) & txd(32) & txd(21) & txd(10)); + xhdl30 <= ("0000000000000000" & tx_data_sg); + xhdl31 <= ("00" & tx_control_sg); + tx_ctrl_1 : cycloneiv_hssi_tx_digi_tx_ctrl + PORT MAP ( + soft_reset => soft_reset_int, + fifo_wr_clk => wr_clk_pos, + fifo_rd_clk => fifo_rd_clk, + refclk_b_in => refclk_b_xhdl14, + scan_mode => scan_mode, + rindv_tx => rindv_tx, + p_rlpbk => '0', + selftest_en => rbisten_tx, + rdwidth_tx => rdwidth_tx, + txfifo_dis => '0', + rtxfifo_urst_en => rphfifoursttx, + txfifo_urst => phfifourst_tx, + rtxfifo_lowlatency_en => rtxfifo_lowlatency_en, + rtxphfifopldctl_en => rphfifopldentx, + rtx_pipe_enable => rtx_pipe_enable, + pld_we => wrenable_tx, + pld_rd_dis => rddisable_tx, + txd => xhdl28, + txd_extend => xhdl29, + rforce_disp => rforce_disp, + tx_data_sg => xhdl30, + tx_control_sg => xhdl31, + rxd_lpbk => "0000000000000000000000000000000000000000", + redund_ctl => "0000", + txd_redun => "0000000000000000000000000000000000000000", + rforce_kchar => rforce_kchar, + rforce_echar => rforce_echar, + rtxpcsbypass_en => rtxpcsbypass_en, + -- TX PIPE signals + txdetectrxloopback => txdetectrxloopback, + powerdown => powerdown, + revloopback => revloopback, + txswing => txswing, + txdeemph => pcs_txdeemph, + txmargin => pcs_txmargin, + -- RX PIPE signals + rxpolarity => rxpolarity, + polinv_rx => polinv_rx, + eidleinfersel => eidleinfersel, + reset_pc_ptrs => reset_pc_ptrs, + reset_pc_ptrs_centrl => reset_pc_ptrs_in_centrl, + reset_pc_ptrs_quad_up => reset_pc_ptrs_in_quad_up, + reset_pc_ptrs_quad_down => reset_pc_ptrs_in_quad_down, + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + dis_pc_byte => dis_pc_byte, + wr_enable_centrl => wr_enable_in_centrl, + wr_enable_quad_up => wr_enable_in_quad_up, + wr_enable_quad_down => wr_enable_in_quad_down, + rd_enable_centrl => rd_enable_in_centrl, + rd_enable_quad_up => rd_enable_in_quad_up, + rd_enable_quad_down => rd_enable_in_quad_down, + fifo_select_in_centrl => fifo_select_in_centrl, + fifo_select_in_quad_up => fifo_select_in_quad_up, + fifo_select_in_quad_down => fifo_select_in_quad_down, + rauto_speed_ena => rauto_speed_ena, + rfreq_sel => rfreq_sel, + rphfifo_regmode_tx => rphfifo_regmode_tx, + rmaster_tx => rmaster_tx, + rmaster_up_tx => rmaster_up_tx, + txd_extend_tc => txd_extend_tc, + tx_data_tc => tx_data_tc_temp, + tx_ctl_tc => tx_ctl_tc_temp, + tx_data_9_tc => tx_data_9_tc, + rd_enable_sync => rd_enable_sync_xhdl13, + k_det => k_det, + d21_5_eq_n => d21_5_eq_n, + d2_2_eq_n => d2_2_eq_n, + wr_enable_out => nc_new_bundle2, + rd_enable_out => nc_new_bundle3, + fifo_select_out => fifo_select_out_testbus, + ph_fifo_full => full_tx_xhdl3, + ph_fifo_empty => empty_tx_xhdl0, + soft_reset_wclk1 => soft_reset_wclk1, + soft_reset_rclk1 => tx_pipe_soft_reset_xhdl23, + pipe_electric_idle => tx_pipe_electidle_xhdl22, + -- TX PIPE signals + txdetectrxloopback_int => txdetectrxloopback_int_xhdl24, + powerdown_int => powerdown_int_xhdl9, + revloopback_int => revloopback_int_xhdl15, + gray_eidleinfersel => gray_eidleinfersel_xhdl4, + + phfifo_txswing => phfifo_txswing_xhdl7, + phfifo_txdeemph => phfifo_txdeemph_xhdl5, + phfifo_txmargin => phfifo_txmargin_xhdl6, + + -- RX PIPE signals + rxpolarity_int => rxpolarity_int_xhdl16, + polinv_rx_int => polinv_rx_int_xhdl8, + wr_enable2 => wr_enable2, + wptr_bin => wptr_bin, + rd_enable2 => rd_enable2, + rptr_bin => rptr_bin + ); + tx_data_tc_high <= tx_data_tc_temp(15 DOWNTO 8); + tx_data_tc_xhdl19 <= tx_data_tc_temp(7 DOWNTO 0); + tx_ctl_tc_high <= tx_ctl_tc_temp(1); + tx_ctl_tc_xhdl18 <= tx_ctl_tc_temp(0); + -- BIST generator module + + + selftest_gen_1 : cycloneiv_hssi_tx_digi_bist_gen + PORT MAP ( + tx_clk => wr_clk_pos, + soft_reset => soft_reset_wclk1, + rbisten_tx => rbisten_tx, + rpmadwidth_tx => rpmadwidth_tx, + rpma_doublewidth_tx => rpma_doublewidth_tx, + rdwidth_tx => rdwidth_tx, + rbist_sel => rbist_sel, + rcxpat_chnl_sel => rcxpat_chnl_en, + bist_data_sg => tx_data_sg, + bist_ctl_sg => tx_control_sg + ); + + -- PRBS generator module + + + prbs_gen_1 : cycloneiv_hssi_tx_digi_prbs_gen + PORT MAP ( + tx_clk => refclk_b_xhdl14, + soft_reset => soft_reset_int, + rprbs_en_tx => rprbsen_tx, + rpmadwidth_tx => rpmadwidth_tx, + rpma_doublewidth_tx => rpma_doublewidth_tx, + cid_en => prbs_cid_en, + rcid_len => rcid_len_tx, + rcid_pattern => rcid_pattern_tx, + rprbs_sel => rprbs_sel, + prbs_out => tx_data_pg + ); + + -- 8B-10B Encoder module + + + xhdl32 <= (tx_ctl_tc_high & tx_ctl_tc_xhdl18); + xhdl33 <= (tx_data_tc_high & tx_data_tc_xhdl19); + enc_chnl_top_1 : cycloneiv_hssi_tx_digi_enc_chnl_top + PORT MAP ( + rst => soft_reset_int, + clk => refclk_b_xhdl14, + cascaded_8b10b_en => rcascaded_8b10b_en_tx, + rendec_data_sel_tx => rendec_data_sel_tx, + rrev_loopbk => rrev_loopbk, + rev_loopbk => rev_loopbk, + dwidth => rpmadwidth_tx, + doublewidth => rpma_doublewidth_tx, + endec => rendec_tx, + ge_xaui_sel => rge_xaui_tx, + rforce_disp => rforce_disp, + ib_force_disparity => rib_force_disp, + prbs_en => rprbsen_tx, + r8b10b_enc_ibm_en => r8b10b_enc_ibm_en, + rev_loop_data => rev_loop_data, + tx_ctl_ts => tx_ctl_ts, + tx_ctl_tc => xhdl32, + tx_data_ts => tx_data_ts, + txd_extend_tc => txd_extend_tc, + tx_data_tc => xhdl33, + tx_data_9_tc => tx_data_9_tc, + tx_data_pg => tx_data_pg, + k_det => k_det(0), + d21_5_eq_n => d21_5_eq_n(0), + d2_2_eq_n => d2_2_eq_n(0), + renpolinv_tx => renpolinv_tx, + enpolinv_tx => polinv_tx, + renbitrev_tx => renbitrev_tx, + rensymswap_tx => rensymswap_tx, + rtxbitslip_en => rtxbitslip_en, + tx_boundary_sel => tx_boundary_sel, + pudr => pudr_xhdl10, + txlp20b => txlp20b_xhdl25, + tx_data_pre_en => tx_data_pre_en, + tx_data_9_pre_en => tx_data_9_pre_en, + tx_ctl_pre_en => tx_ctl_pre_en, + disp_out_3b => disp_out_3b + ); + + + + iqp_out_up : cycloneiv_hssi_tx_digi_iq_pipe_tx + PORT MAP ( + refclk_b_raw => refclk_b_raw, + wr_clk_pos_raw => wr_clk_pos_raw, + fifo_rd_clk_raw => fifo_rd_clk_raw, + txrst => txpcs_rst, + soft_reset_rclk1 => tx_pipe_soft_reset_xhdl23, + soft_reset_wclk1 => soft_reset_wclk1, + tx_div2_sync_in_centrl => tx_div2_sync_in_centrl, + tx_div2_sync_in_pipe_quad_up => '0', + tx_div2_sync_in_pipe_quad_down => tx_div2_sync_in_pipe_quad_down, + wr_enable_in_centrl => wr_enable_in_centrl, + wr_enable_in_pipe_quad_up => '0', + wr_enable_in_pipe_quad_down => wr_enable_in_pipe_quad_down, + rd_enable_in_centrl => rd_enable_in_centrl, + rd_enable_in_pipe_quad_up => '0', + rd_enable_in_pipe_quad_down => rd_enable_in_pipe_quad_down, + fifo_select_in_centrl => fifo_select_in_centrl, + fifo_select_in_pipe_quad_up => '0', + fifo_select_in_pipe_quad_down => fifo_select_in_pipe_quad_down, + rmaster_tx => rmaster_tx, + rmaster_up_tx => rmaster_up_tx, + rpipeline_bypass_tx => rpipeline_bypass_tx, + rfreerun_tx => rfreerun_tx, + tx_div2_sync_out_pipe => tx_div2_sync_out_pipe_up_xhdl21, + fifo_select_out_pipe => fifo_select_out_pipe_up_xhdl2, + wr_enable_out_pipe => wr_enable_out_pipe_up_xhdl27, + rd_enable_out_pipe => rd_enable_out_pipe_up_xhdl12 + ); + + + + iqp_out_down : cycloneiv_hssi_tx_digi_iq_pipe_tx + PORT MAP ( + refclk_b_raw => refclk_b_raw, + wr_clk_pos_raw => wr_clk_pos_raw, + fifo_rd_clk_raw => fifo_rd_clk_raw, + txrst => txpcs_rst, + soft_reset_rclk1 => tx_pipe_soft_reset_xhdl23, + soft_reset_wclk1 => soft_reset_wclk1, + tx_div2_sync_in_centrl => tx_div2_sync_in_centrl, + tx_div2_sync_in_pipe_quad_up => tx_div2_sync_in_pipe_quad_up, + tx_div2_sync_in_pipe_quad_down => '0', + wr_enable_in_centrl => wr_enable_in_centrl, + wr_enable_in_pipe_quad_up => wr_enable_in_pipe_quad_up, + wr_enable_in_pipe_quad_down => '0', + rd_enable_in_centrl => rd_enable_in_centrl, + rd_enable_in_pipe_quad_up => rd_enable_in_pipe_quad_up, + rd_enable_in_pipe_quad_down => '0', + fifo_select_in_centrl => fifo_select_in_centrl, + fifo_select_in_pipe_quad_up => fifo_select_in_pipe_quad_up, + fifo_select_in_pipe_quad_down => '0', + rmaster_tx => rmaster_tx, + rmaster_up_tx => rmaster_up_tx, + rpipeline_bypass_tx => rpipeline_bypass_tx, + rfreerun_tx => rfreerun_tx, + tx_div2_sync_out_pipe => tx_div2_sync_out_pipe_down_xhdl20, + fifo_select_out_pipe => fifo_select_out_pipe_down_xhdl1, + wr_enable_out_pipe => wr_enable_out_pipe_down_xhdl26, + rd_enable_out_pipe => rd_enable_out_pipe_down_xhdl11 + ); + +END trans; + + + + +-- digi_tx--/////////////////////////////////////////////////////////////////////////////// +-- hssi_module: transmitter ***************************************************// +--/////////////////////////////////////////////////////////////////////////////// + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +ENTITY cycloneiv_hssi_tx_pcs IS + GENERIC ( + + -- generic control parameters -- + -- VITAL + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + + -- tipd :interconnect path delays -- + tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_coreclk : VitalDelayType01 := DefpropDelay01; + tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_detectrxloop : VitalDelayType01 := DefpropDelay01; + tipd_digitalreset : VitalDelayType01 := DefpropDelay01; + tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01; + tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01; + tipd_forceelecidle : VitalDelayType01 := DefpropDelay01; + tipd_freezptr : VitalDelayType01 := DefpropDelay01; + tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01; + tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01; + tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01; + tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_invpol : VitalDelayType01 := DefpropDelay01; + tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_localrefclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01; + tipd_phfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01; + tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01; + tipd_pipetxswing : VitalDelayType01 := DefpropDelay01; + tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_prbscidenable : VitalDelayType01 := DefpropDelay01; + tipd_quadreset : VitalDelayType01 := DefpropDelay01; + tipd_rateswitch : VitalDelayType01 := DefpropDelay01; + tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01; + tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01; + tipd_refclk : VitalDelayType01 := DefpropDelay01; + tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_xgmctrl : VitalDelayType01 := DefpropDelay01; + tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); + + -- TSU-TH section + tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + --tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + --tsetup_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + --tsetup_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + --thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + --thold_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + --thold_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + + -- TCO section + tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01; + + lpm_type : STRING := "cycloneiv_hssi_tx_pcs"; + allow_polarity_inversion : STRING := "false"; + --auto_spd_self_switch_enable : STRING := "false"; + bitslip_enable : STRING := "false"; + channel_bonding : STRING := "none"; -- none, x8, x4 + channel_number : INTEGER := 0; + channel_width : INTEGER := 8; + core_clock_0ppm : STRING := "false"; + datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL= + datapath_protocol : STRING := "basic"; --replaced by protocol_hint + disable_ph_low_latency_mode : STRING := "false"; + disparity_mode : STRING := "none"; -- legacy, new, none + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6> + enable_bit_reversal : STRING := "false"; + enable_idle_selection : STRING := "false"; + enable_phfifo_bypass : STRING := "false"; + enable_reverse_parallel_loopback : STRING := "false"; + enable_self_test_mode : STRING := "false"; + --enable_symbol_swap : STRING := "false"; + enc_8b_10b_compatibility_mode : STRING := "true"; + enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none + force_echar : STRING := "false"; + force_kchar : STRING := "false"; + hip_enable : STRING := "false"; + --iqp_bypass : STRING := "false"; + --iqp_ph_fifo_xn_select : INTEGER := 9999; + logical_channel_address : INTEGER := 0; + migrated_from_prev_family : STRING := "false"; + ph_fifo_reg_mode : STRING := "false"; + ph_fifo_reset_enable : STRING := "false"; + ph_fifo_user_ctrl_enable : STRING := "false"; + --ph_fifo_xn_mapping0 : STRING := "none"; + --ph_fifo_xn_mapping1 : STRING := "none"; + --ph_fifo_xn_mapping2 : STRING := "none"; + --ph_fifo_xn_select : INTEGER := 9999; + --pipe_auto_speed_nego_enable : STRING := "false"; + --pipe_freq_scale_mode : STRING := "Data width"; + pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL= + --prbs_all_one_detect : STRING := "false"; + prbs_cid_pattern : STRING := "false"; + prbs_cid_pattern_length : INTEGER := 0; + protocol_hint : STRING := "basic"; + refclk_select : STRING := "local"; -- cmu_clk_divider + reset_clock_output_during_digital_reset : STRING := "false"; + self_test_mode : STRING := "incremental"; + use_double_data_mode : STRING := "false"; + --use_serializer_double_data_mode : STRING := "false"; + wr_clk_mux_select : STRING := "core_clk" -- INT_CLK // int_clk + ); + PORT ( + bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0'); + coreclk : IN STD_LOGIC := '0'; + ctrlenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); + datainfull : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE + detectrxloop : IN STD_LOGIC := '0'; + digitalreset : IN STD_LOGIC := '0'; + dispval : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0'); + elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + enrevparallellpbk : IN STD_LOGIC := '0'; + forcedisp : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); --fix_width + --forcedispcompliance : IN STD_LOGIC := '0'; + forceelecidle : IN STD_LOGIC := '0'; + --freezptr : IN STD_LOGIC := '0'; + hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); + hipdetectrxloop : IN STD_LOGIC := '0'; + hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + hipforceelecidle : IN STD_LOGIC := '0'; + hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + --hiptxdeemph : IN STD_LOGIC := '0'; + --hiptxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + invpol : IN STD_LOGIC := '0'; + --iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + --iqpphfifoxnrdclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + --iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + --iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + localrefclk : IN STD_LOGIC := '0'; + --phfifobyteserdisable : IN STD_LOGIC := '0'; + --phfifoptrsreset : IN STD_LOGIC := '0'; + phfiforddisable : IN STD_LOGIC := '0'; + phfiforeset : IN STD_LOGIC := '0'; + phfifowrenable : IN STD_LOGIC := '1'; + phfifox4bytesel : IN STD_LOGIC := '0'; + phfifox4rdclk : IN STD_LOGIC := '0'; + phfifox4rdenable : IN STD_LOGIC := '0'; + phfifox4wrenable : IN STD_LOGIC := '0'; + --phfifoxnbottombytesel : IN STD_LOGIC := '0'; + --phfifoxnbottomrdclk : IN STD_LOGIC := '0'; + --phfifoxnbottomrdenable : IN STD_LOGIC := '0'; + --phfifoxnbottomwrenable : IN STD_LOGIC := '0'; + --phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + --phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + --phfifoxnrdclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + --phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + --phfifoxntopbytesel : IN STD_LOGIC := '0'; + --phfifoxntoprdclk : IN STD_LOGIC := '0'; + --phfifoxntoprdenable : IN STD_LOGIC := '0'; + --phfifoxntopwrenable : IN STD_LOGIC := '0'; + --phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + pipestatetransdone : IN STD_LOGIC := '0'; + --pipetxdeemph : IN STD_LOGIC := '0'; --NEW; RTL=txdeemph; + --pipetxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); --NEW; RTL=txmargin[2:0] + pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing + powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + prbscidenable : IN STD_LOGIC := '0'; + quadreset : IN STD_LOGIC := '0'; + --rateswitch : IN STD_LOGIC := '0'; --NEW, RTL=rate + --rateswitchisdone : IN STD_LOGIC := '0'; + --rateswitchxndone : IN STD_LOGIC := '0'; + refclk : IN STD_LOGIC := '0'; + revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); + xgmctrl : IN STD_LOGIC := '0'; + xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + + clkout : OUT STD_LOGIC; + coreclkout : OUT STD_LOGIC; + dataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0); + forceelecidleout : OUT STD_LOGIC; + grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + hiptxclkout : OUT STD_LOGIC; + --iqpphfifobyteselout : OUT STD_LOGIC; + --iqpphfifordclkout : OUT STD_LOGIC; + --iqpphfifordenableout : OUT STD_LOGIC; + --iqpphfifowrenableout : OUT STD_LOGIC; + parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + --phfifobyteselout : OUT STD_LOGIC; + phfifooverflow : OUT STD_LOGIC; + --phfifordclkout : OUT STD_LOGIC; + phfiforddisableout : OUT STD_LOGIC; + --phfifordenableout : OUT STD_LOGIC; + phfiforesetout : OUT STD_LOGIC; + phfifounderflow : OUT STD_LOGIC; + phfifowrenableout : OUT STD_LOGIC; + pipeenrevparallellpbkout : OUT STD_LOGIC; + pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + --rateswitchout : OUT STD_LOGIC; + rdenablesync : OUT STD_LOGIC; + txdetectrx : OUT STD_LOGIC; + xgmctrlenable : OUT STD_LOGIC; + xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END cycloneiv_hssi_tx_pcs; + +ARCHITECTURE trans OF cycloneiv_hssi_tx_pcs IS + +-- -------------------------------------------------------------------------- +-- parameters in TgX but not in cycloneiv ------------------------------------ +-- --- make them local with fixed value so maximally reuse TgX code - +-- to not modifying internal codes - +-- --- total = 57 5/7/09 - +-- -------------------------------------------------------------------------- + CONSTANT auto_spd_self_switch_enable : STRING := "false"; + CONSTANT enable_symbol_swap : STRING := "false"; + CONSTANT iqp_bypass : STRING := "false"; + CONSTANT iqp_ph_fifo_xn_select : INTEGER := 9999; + CONSTANT ph_fifo_xn_mapping0 : STRING := "none"; + CONSTANT ph_fifo_xn_mapping1 : STRING := "none"; + CONSTANT ph_fifo_xn_mapping2 : STRING := "none"; + CONSTANT ph_fifo_xn_select : INTEGER := 9999; + CONSTANT pipe_auto_speed_nego_enable : STRING := "false"; + CONSTANT pipe_freq_scale_mode : STRING := "Data width"; + CONSTANT prbs_all_one_detect : STRING := "false"; + CONSTANT use_serializer_double_data_mode : STRING := "false"; + +-- -------------------------------------------------------------------------- +-- Input ports in TgX but not in cycloneiv ----------------------------------- +-- --- make them wire with fixed value so maximally reuse TgX code - +-- to not modifying internal codes - +-- --- total = 60 5/7/09 - +-- -------------------------------------------------------------------------- + SIGNAL forcedispcompliance : STD_LOGIC := '0'; + SIGNAL freezptr : STD_LOGIC := '0'; + SIGNAL hiptxdeemph : STD_LOGIC := '0'; + SIGNAL hiptxmargin : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + SIGNAL iqpphfifoxnbytesel : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + SIGNAL iqpphfifoxnrdclk : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + SIGNAL iqpphfifoxnrdenable : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + SIGNAL iqpphfifoxnwrenable : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + SIGNAL phfifobyteserdisable : STD_LOGIC := '0'; + SIGNAL phfifoptrsreset : STD_LOGIC := '0'; + SIGNAL phfifoxnbottombytesel : STD_LOGIC := '0'; + SIGNAL phfifoxnbottomrdclk : STD_LOGIC := '0'; + SIGNAL phfifoxnbottomrdenable : STD_LOGIC := '0'; + SIGNAL phfifoxnbottomwrenable : STD_LOGIC := '0'; + SIGNAL phfifoxnbytesel : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + SIGNAL phfifoxnptrsreset : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + SIGNAL phfifoxnrdclk : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + SIGNAL phfifoxnrdenable : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + SIGNAL phfifoxntopbytesel : STD_LOGIC := '0'; + SIGNAL phfifoxntoprdclk : STD_LOGIC := '0'; + SIGNAL phfifoxntoprdenable : STD_LOGIC := '0'; + SIGNAL phfifoxntopwrenable : STD_LOGIC := '0'; + SIGNAL phfifoxnwrenable : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + SIGNAL pipetxdeemph : STD_LOGIC := '0'; --NEW; RTL=txdeemph; + SIGNAL pipetxmargin : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); --NEW; RTL=txmargin[2:0] + SIGNAL rateswitch : STD_LOGIC := '0'; --NEW, RTL=rate + SIGNAL rateswitchisdone : STD_LOGIC := '0'; + SIGNAL rateswitchxndone : STD_LOGIC := '0'; + +-- -------------------------------------------------------------------------- +-- Output ports in TgX but not in cycloneiv ---------------------------------- +-- SIGNAL - make them wire to maximally reuse TgX code - +-- to not modifying internal codes - +-- -------------------------------------------------------------------------- + SIGNAL iqpphfifobyteselout : STD_LOGIC; + SIGNAL iqpphfifordclkout : STD_LOGIC; + SIGNAL iqpphfifordenableout : STD_LOGIC; + SIGNAL iqpphfifowrenableout : STD_LOGIC; + SIGNAL phfifobyteselout : STD_LOGIC; + SIGNAL phfifordclkout : STD_LOGIC; + SIGNAL phfifordenableout : STD_LOGIC; + SIGNAL rateswitchout : STD_LOGIC; + +-- -------------------------------------------------------------------------- +-- Behavior code start ---------------------------------- +-- -------------------------------------------------------------------------- + + SIGNAL bitslipboundaryselect_ipd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL coreclk_ipd : STD_LOGIC; + SIGNAL ctrlenable_ipd : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL datain_ipd : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL datainfull_ipd : STD_LOGIC_VECTOR(21 DOWNTO 0); + SIGNAL datainfull_siv : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL detectrxloop_ipd : STD_LOGIC; + SIGNAL digitalreset_ipd : STD_LOGIC; + SIGNAL dispval_ipd : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dpriodisable_ipd : STD_LOGIC; + SIGNAL dprioin_ipd : STD_LOGIC_VECTOR(149 DOWNTO 0); + SIGNAL enrevparallellpbk_ipd : STD_LOGIC; + SIGNAL forcedisp_ipd : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL forcedispcompliance_ipd : STD_LOGIC; + SIGNAL forceelecidle_ipd : STD_LOGIC; + SIGNAL freezptr_ipd : STD_LOGIC; + SIGNAL hipdatain_ipd : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL hipdetectrxloop_ipd : STD_LOGIC; + SIGNAL hipforceelecidle_ipd : STD_LOGIC; + SIGNAL hippowerdn_ipd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hiptxdeemph_ipd : STD_LOGIC; + SIGNAL hiptxmargin_ipd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL invpol_ipd : STD_LOGIC; + SIGNAL iqpphfifoxnbytesel_ipd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL iqpphfifoxnrdclk_ipd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL iqpphfifoxnrdenable_ipd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL iqpphfifoxnwrenable_ipd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL localrefclk_ipd : STD_LOGIC; + SIGNAL phfifobyteserdisable_ipd: STD_LOGIC; + SIGNAL phfifoptrsreset_ipd : STD_LOGIC; + SIGNAL phfiforddisable_ipd : STD_LOGIC; + SIGNAL phfiforeset_ipd : STD_LOGIC; + SIGNAL phfifowrenable_ipd : STD_LOGIC; + SIGNAL phfifox4bytesel_ipd : STD_LOGIC; + SIGNAL phfifox4rdclk_ipd : STD_LOGIC; + SIGNAL phfifox4rdenable_ipd : STD_LOGIC; + SIGNAL phfifox4wrenable_ipd : STD_LOGIC; + SIGNAL phfifoxnbottombytesel_ipd : STD_LOGIC; + SIGNAL phfifoxnbottomrdclk_ipd : STD_LOGIC; + SIGNAL phfifoxnbottomrdenable_ipd : STD_LOGIC; + SIGNAL phfifoxnbottomwrenable_ipd : STD_LOGIC; + SIGNAL phfifoxnbytesel_ipd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxnptrsreset_ipd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxnrdclk_ipd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxnrdenable_ipd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxntopbytesel_ipd : STD_LOGIC; + SIGNAL phfifoxntoprdclk_ipd : STD_LOGIC; + SIGNAL phfifoxntoprdenable_ipd : STD_LOGIC; + SIGNAL phfifoxntopwrenable_ipd : STD_LOGIC; + SIGNAL phfifoxnwrenable_ipd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL pipestatetransdone_ipd : STD_LOGIC; + SIGNAL pipetxdeemph_ipd : STD_LOGIC; + SIGNAL pipetxmargin_ipd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL pipetxswing_ipd : STD_LOGIC; + SIGNAL powerdn_ipd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL prbscidenable_ipd : STD_LOGIC; + SIGNAL quadreset_ipd : STD_LOGIC; + SIGNAL rateswitch_ipd : STD_LOGIC; + SIGNAL rateswitchisdone_ipd : STD_LOGIC; + SIGNAL rateswitchxndone_ipd : STD_LOGIC; + SIGNAL refclk_ipd : STD_LOGIC; + SIGNAL revparallelfdbk_ipd : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL xgmctrl_ipd : STD_LOGIC; + SIGNAL xgmdatain_ipd : STD_LOGIC_VECTOR(7 DOWNTO 0); + + COMPONENT cycloneiv_hssi_tx_pipe_interface + PORT ( + clk : IN STD_LOGIC; + refclk_b : IN STD_LOGIC; + reset_n : IN STD_LOGIC; + refclk_b_reset_n : IN STD_LOGIC; + rtx_pipe_enable : IN STD_LOGIC; + rtx_elec_idle_delay : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rtxswing_sel_ena : IN STD_LOGIC; + txdetectrxloopback : IN STD_LOGIC; + txelecidle : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txswing : IN STD_LOGIC; + txdeemph : IN STD_LOGIC; + txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txd_ch : IN STD_LOGIC_VECTOR(43 DOWNTO 0); + revloopback : IN STD_LOGIC; + txd : OUT STD_LOGIC_VECTOR(43 DOWNTO 0); + rev_loopbk : OUT STD_LOGIC; + tx_elec_idle_comp : IN STD_LOGIC; + tx_elec_idle : OUT STD_LOGIC; + txdetectrx : OUT STD_LOGIC; + powerstate : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txswing_int : OUT STD_LOGIC; + txdeemph_int : OUT STD_LOGIC; + txmargin_int : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_digi + PORT ( + txpcs_rst : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + txd : IN STD_LOGIC_VECTOR(43 DOWNTO 0); + pld_tx_clk : IN STD_LOGIC; + polinv_tx : IN STD_LOGIC; + rev_loop_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + wrenable_tx : IN STD_LOGIC; + rddisable_tx : IN STD_LOGIC; + phfifourst_tx : IN STD_LOGIC; + txdetectrxloopback : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + revloopback : IN STD_LOGIC; + txswing : IN STD_LOGIC; + pcs_txdeemph : IN STD_LOGIC; + pcs_txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rxpolarity : IN STD_LOGIC; + polinv_rx : IN STD_LOGIC; + full_tx : OUT STD_LOGIC; + empty_tx : OUT STD_LOGIC; + tx_data_ts : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + tx_ctl_ts : IN STD_LOGIC; + refclk_pma : IN STD_LOGIC; + txpma_local_clk : IN STD_LOGIC; + tx_clk_out : OUT STD_LOGIC; + tx_data_tc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + tx_ctl_tc : OUT STD_LOGIC; + pudr : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + rd_enable_sync : OUT STD_LOGIC; + refclk_b : OUT STD_LOGIC; + txlp20b : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + tx_pipe_clk : OUT STD_LOGIC; + encoder_testbus : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + tx_ctrl_testbus : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + tx_pipe_soft_reset : OUT STD_LOGIC; + tx_pipe_electidle : OUT STD_LOGIC; + txdetectrxloopback_int : OUT STD_LOGIC; + powerdown_int : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + revloopback_int : OUT STD_LOGIC; + phfifo_txswing : OUT STD_LOGIC; + phfifo_txdeemph : OUT STD_LOGIC; + phfifo_txmargin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rxpolarity_int : OUT STD_LOGIC; + polinv_rx_int : OUT STD_LOGIC; + rrev_loopbk : IN STD_LOGIC; + rev_loopbk : IN STD_LOGIC; + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + gray_eidleinfersel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rbisten_tx : IN STD_LOGIC; + rforce_disp : IN STD_LOGIC; + rib_force_disp : IN STD_LOGIC; + rforce_echar : IN STD_LOGIC; + rforce_kchar : IN STD_LOGIC; + rendec_tx : IN STD_LOGIC; + rge_xaui_tx : IN STD_LOGIC; + rdwidth_tx : IN STD_LOGIC; + rtxfifo_dis : IN STD_LOGIC; + rcascaded_8b10b_en_tx : IN STD_LOGIC; + rprbsen_tx : IN STD_LOGIC; + rprbs_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rbist_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcxpat_chnl_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + renpolinv_tx : IN STD_LOGIC; + rphfifopldentx : IN STD_LOGIC; + rphfifoursttx : IN STD_LOGIC; + rfreerun_tx : IN STD_LOGIC; + rtxwrclksel : IN STD_LOGIC; + rtxrdclksel : IN STD_LOGIC; + renbitrev_tx : IN STD_LOGIC; + rensymswap_tx : IN STD_LOGIC; + r8b10b_enc_ibm_en : IN STD_LOGIC; + rtxfifo_lowlatency_en : IN STD_LOGIC; + rpmadwidth_tx : IN STD_LOGIC; + rpma_doublewidth_tx : IN STD_LOGIC; + rtx_pipe_enable : IN STD_LOGIC; + rindv_tx : IN STD_LOGIC; + rendec_data_sel_tx : IN STD_LOGIC; + rtxpcsbypass_en : IN STD_LOGIC; + rtxpcsclkpwdn : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + rcid_pattern_tx : IN STD_LOGIC; + rcid_len_tx : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + tx_div2_sync_in_centrl : IN STD_LOGIC; + tx_div2_sync_in_quad_up : IN STD_LOGIC; + tx_div2_sync_in_quad_down : IN STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_quad_up : IN STD_LOGIC; + wr_enable_in_quad_down : IN STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_quad_up : IN STD_LOGIC; + rd_enable_in_quad_down : IN STD_LOGIC; + fifo_select_in_centrl : IN STD_LOGIC; + fifo_select_in_quad_up : IN STD_LOGIC; + fifo_select_in_quad_down : IN STD_LOGIC; + dis_pc_byte : IN STD_LOGIC; + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_in_centrl : IN STD_LOGIC; + reset_pc_ptrs_in_quad_up : IN STD_LOGIC; + reset_pc_ptrs_in_quad_down : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + tx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + fifo_select_in_pipe_quad_up : IN STD_LOGIC; + fifo_select_in_pipe_quad_down : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + rself_sw_en_tx : IN STD_LOGIC; + rpipeline_bypass_tx : IN STD_LOGIC; + rphfifo_regmode_tx : IN STD_LOGIC; + rtxbitslip_en : IN STD_LOGIC; + tx_div2_sync_out_pipe_up : OUT STD_LOGIC; + fifo_select_out_pipe_up : OUT STD_LOGIC; + wr_enable_out_pipe_up : OUT STD_LOGIC; + rd_enable_out_pipe_up : OUT STD_LOGIC; + tx_div2_sync_out_pipe_down : OUT STD_LOGIC; + fifo_select_out_pipe_down : OUT STD_LOGIC; + wr_enable_out_pipe_down : OUT STD_LOGIC; + rd_enable_out_pipe_down : OUT STD_LOGIC; + prbs_cid_en : IN STD_LOGIC; + tx_boundary_sel : IN STD_LOGIC_VECTOR(4 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_digi_chnl_hip_spt + PORT ( + rhip_ena : IN STD_LOGIC; + pcs_rxd_ch : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + pcs_rxvalid : IN STD_LOGIC; + pcs_rxelecidle : IN STD_LOGIC; + pcs_rxstatus_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_phystatus : IN STD_LOGIC; + txpma_local_clk : IN STD_LOGIC; + txd_ch : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + hip_txd_ch : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + txdetectrxloopback : IN STD_LOGIC; + hip_txdetectrxloopback : IN STD_LOGIC; + rxpolarity : IN STD_LOGIC; + hip_rxpolarity : IN STD_LOGIC; + powerdown_ch : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + hip_powerdown_ch : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txdeemph : IN STD_LOGIC; + hip_txdeemph : IN STD_LOGIC; + txmargin_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_txmargin_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidleinfersel_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_eidleinfersel_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rate : IN STD_LOGIC; + hip_rate : IN STD_LOGIC; + hip_txelecidle : IN STD_LOGIC; + rxd_ch : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + hip_rxd_ch : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + rxvalid : OUT STD_LOGIC; + hip_rxvalid : OUT STD_LOGIC; + rxelecidle : OUT STD_LOGIC; + hip_rxelecidle : OUT STD_LOGIC; + rxstatus_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_rxstatus_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + phystatus : OUT STD_LOGIC; + hip_phystatus : OUT STD_LOGIC; + hip_tx_clk : OUT STD_LOGIC; + pcs_txd_ch : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); + pcs_txdetectrxloopback : OUT STD_LOGIC; + pcs_rxpolarity : OUT STD_LOGIC; + pcs_powerdown_ch : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pcs_txdeemph : OUT STD_LOGIC; + pcs_txmargin_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_eidleinfersel_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_rate : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_pcs_reset + PORT ( + hard_reset : IN STD_LOGIC; + clk_2_b : IN STD_LOGIC; + refclk_b_in : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rxpcs_rst : IN STD_LOGIC; + txpcs_rst : IN STD_LOGIC; + rxrst_int : OUT STD_LOGIC; + txrst_int : OUT STD_LOGIC + ); + END COMPONENT; + + SIGNAL tmp_ctrlenable : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tmp_datain : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL tmp_dispval : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tmp_forcedisp : STD_LOGIC_VECTOR(3 DOWNTO 0); + + constant DPRIO_CHANNEL_INTERFACE_BIT : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000100"; + + -- new dprio model -- + -- Table1: PCS Per Channel TX Control Register 1 for Channel 0 + constant rforce_disp_TXPCS_IDX_0 : integer := 0; + constant rrev_loopbk_TXPCS_IDX_0 : integer := 1; + constant rtxrdclksel_TXPCS_IDX_0 : integer := 2; + constant rtxwrclksel_TXPCS_IDX_0 : integer := 3; + constant rfreerun_tx_TXPCS_IDX_0 : integer := 4; + constant rtxurstpcs_TXPCS_IDX_0 : integer := 5; + constant reserved_0_TB1_TXPCS_IDX_0 : integer := 6; + constant rphfifoursttx_TXPCS_IDX_0 : integer := 7; + constant rphfifopldentx_TXPCS_IDX_0 : integer := 8; + constant rge_xaui_tx_TXPCS_IDX_0 : integer := 9; + constant rdwidth_tx_TXPCS_IDX_0 : integer := 10; + constant rtxfifo_lowlatency_en_TXPCS_IDX_0 : integer := 11; + constant rib_force_disp_TXPCS_IDX_0 : integer := 12; + constant rtxfifo_dis_TXPCS_IDX_0 : integer := 13; + constant rforce_echar_TXPCS_IDX_0 : integer := 14; + constant rforce_kchar_TXPCS_IDX_0 : integer := 15; + + -- Table2: PCS Per Channel TX Control Register 2 for Channel 0 + constant rtxpcsbypass_en_TXPCS_IDX_0 : integer := 16; + constant rcxpat_chnl_en_TXPCS_IDX_0 : integer := 17; + constant rcxpat_chnl_en_TXPCS_IDX_1 : integer := 18; + constant rbist_sel_TXPCS_IDX_0 : integer := 19; + constant rbist_sel_TXPCS_IDX_1 : integer := 20; + constant rbisten_tx_TXPCS_IDX_0 : integer := 21; + constant rprbs_sel_TXPCS_IDX_0 : integer := 22; + constant rprbs_sel_TXPCS_IDX_1 : integer := 23; + constant rprbs_sel_TXPCS_IDX_2 : integer := 24; + constant rprbsen_tx_TXPCS_IDX_0 : integer := 25; + constant renbitrev_tx_TXPCS_IDX_0 : integer := 26; + constant renpolinv_tx_TXPCS_IDX_0 : integer := 27; + constant rensymswap_tx_TXPCS_IDX_0 : integer := 28; + constant rcascaded_8b10b_en_tx_TXPCS_IDX_0 : integer := 29; + constant r8b10b_enc_ibm_en_TXPCS_IDX_0 : integer := 30; + constant rendec_tx_TXPCS_IDX_0 : integer := 31; + + -- Table3: PCS Per Channel TX Control Register 3 for Channel 0 + constant reserved_0_TB3_TXPCS_IDX_0 : integer := 32; + constant rcid_len_tx_TXPCS_IDX_0 : integer := 33; + constant rcid_len_tx_TXPCS_IDX_1 : integer := 34; + constant rcid_len_tx_TXPCS_IDX_2 : integer := 35; + constant rcid_len_tx_TXPCS_IDX_3 : integer := 36; + constant rcid_len_tx_TXPCS_IDX_4 : integer := 37; + constant rcid_len_tx_TXPCS_IDX_5 : integer := 38; + constant rcid_len_tx_TXPCS_IDX_6 : integer := 39; + constant rcid_len_tx_TXPCS_IDX_7 : integer := 40; + constant rcid_pattern_tx_TXPCS_IDX_0 : integer := 41; + constant rtxpcsclkpwdn_TXPCS_IDX_0 : integer := 42; + constant rtxswing_sel_ena_TXPCS_IDX_0 : integer := 43; + constant rtx_elec_idle_delay_TXPCS_IDX_0 : integer := 44; + constant rtx_elec_idle_delay_TXPCS_IDX_1 : integer := 45; + constant rtx_elec_idle_delay_TXPCS_IDX_2 : integer := 46; + constant rtx_pipe_enable_TXPCS_IDX_0 : integer := 47; + + -- Table4: PCS Per Channel TX Control Register 4 for Channel 0 + constant reserved_0_TB4_TXPCS_IDX_0 : integer := 48; + constant reserved_0_TB4_TXPCS_IDX_1 : integer := 49; + constant reserved_0_TB4_TXPCS_IDX_2 : integer := 50; + constant reserved_0_TB4_TXPCS_IDX_3 : integer := 51; + constant reserved_0_TB4_TXPCS_IDX_4 : integer := 52; + constant reserved_0_TB4_TXPCS_IDX_5 : integer := 53; + constant reserved_0_TB4_TXPCS_IDX_6 : integer := 54; + constant reserved_0_TB4_TXPCS_IDX_7 : integer := 55; + constant reserved_0_TB4_TXPCS_IDX_8 : integer := 56; + constant reserved_0_TB4_TXPCS_IDX_9 : integer := 57; + constant reserved_0_TB4_TXPCS_IDX_10 : integer := 58; + constant reserved_0_TB4_TXPCS_IDX_11 : integer := 59; + constant rtxbitslip_en_TXPCS_IDX_0 : integer := 60; + constant rphfifo_regmode_tx_TXPCS_IDX_0 : integer := 61; + constant rpipeline_bypass_tx_TXPCS_IDX_0 : integer := 62; + constant rself_sw_en_tx_TXPCS_IDX_0 : integer := 63; + + -- Existing + constant rauto_speed_ena_TX_IDX : integer := 64; + constant rendec_data_sel_tx_TX_IDX : integer := 65; + constant rfreq_sel_TX_IDX : integer := 66; + constant rhip_ena_TX_IDX : integer := 67; + constant rindv_tx_TX_IDX : integer := 68; + constant rphfifo_master_sel_tx_TX_IDX : integer := 69; + constant rpma_doublewidth_tx_TX_IDX : integer := 70; + constant rpmadwidth_tx_TX_IDX : integer := 71; + constant rtx_cmu_sel_TX_IDX : integer := 72; + + -- ------------------------------------------------------------------------- + -- DPRIO input CRAM + -- ------------------------------------------------------------------------- + -- Existing + SIGNAL dprioin_is_lane0: STD_LOGIC; + SIGNAL dprioin_rauto_speed_ena: STD_LOGIC; + SIGNAL dprioin_rclkcmpinsertpad: STD_LOGIC; -- rx only ========= pipe =========== + SIGNAL dprioin_rendec_data_sel_tx: STD_LOGIC; + SIGNAL dprioin_rfreq_sel: STD_LOGIC; + SIGNAL dprioin_rhip_ena: STD_LOGIC; + SIGNAL dprioin_rindv_tx: STD_LOGIC; + SIGNAL dprioin_rmaster_tx: STD_LOGIC; + SIGNAL dprioin_rmaster_up_tx: STD_LOGIC; + SIGNAL dprioin_rphfifo_master_sel_tx: STD_LOGIC; + SIGNAL dprioin_rpma_doublewidth_tx: STD_LOGIC; + SIGNAL dprioin_rpmadwidth_tx: STD_LOGIC; + SIGNAL dprioin_rrdwidth_rx: STD_LOGIC; -- rx only + SIGNAL dprioin_rrx_detect_bypass: STD_LOGIC; -- rx only + SIGNAL dprioin_rrx_pipe_enable: STD_LOGIC; -- rx only + SIGNAL dprioin_rtx_cmu_sel: STD_LOGIC; -- added in 6.1 + SIGNAL dprioin_scan_mode: STD_LOGIC; + + -- PCS Per Channel TX Control Register 1 for Channel 0 + SIGNAL dprioin_rforce_disp : STD_LOGIC; + SIGNAL dprioin_rrev_loopbk : STD_LOGIC; + SIGNAL dprioin_rtxrdclksel : STD_LOGIC; + SIGNAL dprioin_rtxwrclksel : STD_LOGIC; + SIGNAL dprioin_rfreerun_tx : STD_LOGIC; + SIGNAL dprioin_rtxurstpcs : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB1 : STD_LOGIC; + SIGNAL dprioin_rphfifoursttx : STD_LOGIC; + SIGNAL dprioin_rphfifopldentx : STD_LOGIC; + SIGNAL dprioin_rge_xaui_tx : STD_LOGIC; + SIGNAL dprioin_rdwidth_tx : STD_LOGIC; + SIGNAL dprioin_rtxfifo_lowlatency_en : STD_LOGIC; + SIGNAL dprioin_rib_force_disp : STD_LOGIC; + SIGNAL dprioin_rtxfifo_dis : STD_LOGIC; + SIGNAL dprioin_rforce_echar : STD_LOGIC; + SIGNAL dprioin_rforce_kchar : STD_LOGIC; + + -- PCS Per Channel TX Control Register 2 for Channel 0 + SIGNAL dprioin_rtxpcsbypass_en : STD_LOGIC; + SIGNAL dprioin_rcxpat_chnl_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rbist_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rbisten_tx : STD_LOGIC; + SIGNAL dprioin_rprbs_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dprioin_rprbsen_tx : STD_LOGIC; + SIGNAL dprioin_renbitrev_tx : STD_LOGIC; + SIGNAL dprioin_renpolinv_tx : STD_LOGIC; + SIGNAL dprioin_rensymswap_tx : STD_LOGIC; + SIGNAL dprioin_rcascaded_8b10b_en_tx : STD_LOGIC; + SIGNAL dprioin_r8b10b_enc_ibm_en : STD_LOGIC; + SIGNAL dprioin_rendec_tx : STD_LOGIC; + + -- PCS Per Channel TX Control Register 3 for Channel 0 + SIGNAL dprioin_reserved_0_TB3 : STD_LOGIC; + SIGNAL dprioin_rcid_len_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dprioin_rcid_pattern_tx : STD_LOGIC; + SIGNAL dprioin_rtxpcsclkpwdn : STD_LOGIC; + SIGNAL dprioin_rtxswing_sel_ena : STD_LOGIC; + SIGNAL dprioin_rtx_elec_idle_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dprioin_rtx_pipe_enable : STD_LOGIC; + + -- PCS Per Channel TX Control Register 4 for Channel 0 + SIGNAL dprioin_reserved_0_TB4 : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL dprioin_rtxbitslip_en : STD_LOGIC; + SIGNAL dprioin_rphfifo_regmode_tx : STD_LOGIC; + SIGNAL dprioin_rpipeline_bypass_tx : STD_LOGIC; + SIGNAL dprioin_rself_sw_en_tx : STD_LOGIC; + + -- ------------------------------------------------------------------------- + -- Initial CRAM + -- ------------------------------------------------------------------------- + -- Existing + SIGNAL init_is_lane0: STD_LOGIC; + SIGNAL init_rauto_speed_ena: STD_LOGIC; + SIGNAL init_rclkcmpinsertpad: STD_LOGIC; -- rx only ========= pipe =========== + SIGNAL init_rendec_data_sel_tx: STD_LOGIC; + SIGNAL init_rfreq_sel: STD_LOGIC; + SIGNAL init_rhip_ena: STD_LOGIC; + SIGNAL init_rindv_tx: STD_LOGIC; + SIGNAL init_rmaster_tx: STD_LOGIC; + SIGNAL init_rmaster_up_tx: STD_LOGIC; + SIGNAL init_rphfifo_master_sel_tx: STD_LOGIC; + SIGNAL init_rpma_doublewidth_tx: STD_LOGIC; + SIGNAL init_rpmadwidth_tx: STD_LOGIC; + SIGNAL init_rrdwidth_rx: STD_LOGIC; -- rx only + SIGNAL init_rrx_detect_bypass: STD_LOGIC; -- rx only + SIGNAL init_rrx_pipe_enable: STD_LOGIC; -- rx only + SIGNAL init_rtx_cmu_sel: STD_LOGIC; -- added in 6.1 + SIGNAL init_scan_mode: STD_LOGIC; + + -- PCS Per Channel TX Control Register 1 for Channel 0 + SIGNAL init_rforce_disp : STD_LOGIC; + SIGNAL init_rrev_loopbk : STD_LOGIC; + SIGNAL init_rtxrdclksel : STD_LOGIC; + SIGNAL init_rtxwrclksel : STD_LOGIC; + SIGNAL init_rfreerun_tx : STD_LOGIC; + SIGNAL init_rtxurstpcs : STD_LOGIC; + SIGNAL init_reserved_0_TB1 : STD_LOGIC; + SIGNAL init_rphfifoursttx : STD_LOGIC; + SIGNAL init_rphfifopldentx : STD_LOGIC; + SIGNAL init_rge_xaui_tx : STD_LOGIC; + SIGNAL init_rdwidth_tx : STD_LOGIC; + SIGNAL init_rtxfifo_lowlatency_en : STD_LOGIC; + SIGNAL init_rib_force_disp : STD_LOGIC; + SIGNAL init_rtxfifo_dis : STD_LOGIC; + SIGNAL init_rforce_echar : STD_LOGIC; + SIGNAL init_rforce_kchar : STD_LOGIC; + + -- PCS Per Channel TX Control Register 2 for Channel 0 + SIGNAL init_rtxpcsbypass_en : STD_LOGIC; + SIGNAL init_rcxpat_chnl_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rbist_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rbisten_tx : STD_LOGIC; + SIGNAL init_rprbs_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rprbsen_tx : STD_LOGIC; + SIGNAL init_renbitrev_tx : STD_LOGIC; + SIGNAL init_renpolinv_tx : STD_LOGIC; + SIGNAL init_rensymswap_tx : STD_LOGIC; + SIGNAL init_rcascaded_8b10b_en_tx : STD_LOGIC; + SIGNAL init_r8b10b_enc_ibm_en : STD_LOGIC; + SIGNAL init_rendec_tx : STD_LOGIC; + + -- PCS Per Channel TX Control Register 3 for Channel 0 + SIGNAL init_reserved_0_TB3 : STD_LOGIC; + SIGNAL init_rcid_len_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL init_rcid_pattern_tx : STD_LOGIC; + SIGNAL init_rtxpcsclkpwdn : STD_LOGIC; + SIGNAL init_rtxswing_sel_ena : STD_LOGIC; + SIGNAL init_rtx_elec_idle_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rtx_pipe_enable : STD_LOGIC; + + -- PCS Per Channel TX Control Register 4 for Channel 0 + SIGNAL init_reserved_0_TB4 : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL init_rtxbitslip_en : STD_LOGIC; + SIGNAL init_rphfifo_regmode_tx : STD_LOGIC; + SIGNAL init_rpipeline_bypass_tx : STD_LOGIC; + SIGNAL init_rself_sw_en_tx : STD_LOGIC; + + -- ------------------------------------------------------------------------- + -- CRAM + -- ------------------------------------------------------------------------- + -- Existing + SIGNAL cram_is_lane0: STD_LOGIC; + SIGNAL cram_rauto_speed_ena: STD_LOGIC; + SIGNAL cram_rclkcmpinsertpad: STD_LOGIC; -- rx only ========= pipe =========== + SIGNAL cram_rendec_data_sel_tx: STD_LOGIC; + SIGNAL cram_rfreq_sel: STD_LOGIC; + SIGNAL cram_rhip_ena: STD_LOGIC; + SIGNAL cram_rindv_tx: STD_LOGIC; + SIGNAL cram_rmaster_tx: STD_LOGIC; + SIGNAL cram_rmaster_up_tx: STD_LOGIC; + SIGNAL cram_rphfifo_master_sel_tx: STD_LOGIC; + SIGNAL cram_rpma_doublewidth_tx: STD_LOGIC; + SIGNAL cram_rpmadwidth_tx: STD_LOGIC; + SIGNAL cram_rrdwidth_rx: STD_LOGIC; -- rx only + SIGNAL cram_rrx_detect_bypass: STD_LOGIC; -- rx only + SIGNAL cram_rrx_pipe_enable: STD_LOGIC; -- rx only + SIGNAL cram_rtx_cmu_sel: STD_LOGIC; -- added in 6.1 + SIGNAL cram_scan_mode: STD_LOGIC; + + -- PCS Per Channel TX Control Register 1 for Channel 0 + SIGNAL cram_rforce_disp : STD_LOGIC; + SIGNAL cram_rrev_loopbk : STD_LOGIC; + SIGNAL cram_rtxrdclksel : STD_LOGIC; + SIGNAL cram_rtxwrclksel : STD_LOGIC; + SIGNAL cram_rfreerun_tx : STD_LOGIC; + SIGNAL cram_rtxurstpcs : STD_LOGIC; + SIGNAL cram_reserved_0_TB1 : STD_LOGIC; + SIGNAL cram_rphfifoursttx : STD_LOGIC; + SIGNAL cram_rphfifopldentx : STD_LOGIC; + SIGNAL cram_rge_xaui_tx : STD_LOGIC; + SIGNAL cram_rdwidth_tx : STD_LOGIC; + SIGNAL cram_rtxfifo_lowlatency_en : STD_LOGIC; + SIGNAL cram_rib_force_disp : STD_LOGIC; + SIGNAL cram_rtxfifo_dis : STD_LOGIC; + SIGNAL cram_rforce_echar : STD_LOGIC; + SIGNAL cram_rforce_kchar : STD_LOGIC; + + -- PCS Per Channel TX Control Register 2 for Channel 0 + SIGNAL cram_rtxpcsbypass_en : STD_LOGIC; + SIGNAL cram_rcxpat_chnl_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rbist_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rbisten_tx : STD_LOGIC; + SIGNAL cram_rprbs_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL cram_rprbsen_tx : STD_LOGIC; + SIGNAL cram_renbitrev_tx : STD_LOGIC; + SIGNAL cram_renpolinv_tx : STD_LOGIC; + SIGNAL cram_rensymswap_tx : STD_LOGIC; + SIGNAL cram_rcascaded_8b10b_en_tx : STD_LOGIC; + SIGNAL cram_r8b10b_enc_ibm_en : STD_LOGIC; + SIGNAL cram_rendec_tx : STD_LOGIC; + + -- PCS Per Channel TX Control Register 3 for Channel 0 + SIGNAL cram_reserved_0_TB3 : STD_LOGIC; + SIGNAL cram_rcid_len_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL cram_rcid_pattern_tx : STD_LOGIC; + SIGNAL cram_rtxpcsclkpwdn : STD_LOGIC; + SIGNAL cram_rtxswing_sel_ena : STD_LOGIC; + SIGNAL cram_rtx_elec_idle_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL cram_rtx_pipe_enable : STD_LOGIC; + + -- PCS Per Channel TX Control Register 4 for Channel 0 + SIGNAL cram_reserved_0_TB4 : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL cram_rtxbitslip_en : STD_LOGIC; + SIGNAL cram_rphfifo_regmode_tx : STD_LOGIC; + SIGNAL cram_rpipeline_bypass_tx : STD_LOGIC; + SIGNAL cram_rself_sw_en_tx : STD_LOGIC; + + SIGNAL dpriodisable_in : STD_LOGIC; + + ----- new dprio end + + --/////////////////////////////////////////////////////////////////////////////// + -- sub-block interface: pcs_reset -----------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + SIGNAL pr_in_hard_reset : STD_LOGIC; + SIGNAL pr_in_clk_2_b : STD_LOGIC; + SIGNAL pr_in_refclk_b_in : STD_LOGIC; + SIGNAL pr_in_scan_mode : STD_LOGIC; + SIGNAL pr_in_rxpcs_rst : STD_LOGIC; + SIGNAL pr_in_txpcs_rst : STD_LOGIC; + SIGNAL pr_out_txrst_int : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////////// + -- sub-block interface: chnl_hip_spt -----------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + SIGNAL hs_in_eidleinfersel_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_hip_eidleinfersel_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_hip_powerdown_ch : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hs_in_hip_rate : STD_LOGIC; + SIGNAL hs_in_hip_rxpolarity : STD_LOGIC; + SIGNAL hs_in_hip_txd_ch : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL hs_in_hip_txdeemph : STD_LOGIC; + SIGNAL hs_in_hip_txdetectrxloopback : STD_LOGIC; + SIGNAL hs_in_hip_txelecidle : STD_LOGIC; + SIGNAL hs_in_hip_txmargin_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_pcs_phystatus : STD_LOGIC; + SIGNAL hs_in_pcs_rxd_ch : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL hs_in_pcs_rxelecidle : STD_LOGIC; + SIGNAL hs_in_pcs_rxstatus_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_pcs_rxvalid : STD_LOGIC; + SIGNAL hs_in_powerdown_ch : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hs_in_rate : STD_LOGIC; + SIGNAL hs_in_rhip_ena : STD_LOGIC; + SIGNAL hs_in_rxpolarity : STD_LOGIC; + SIGNAL hs_in_txd_ch : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL hs_in_txdeemph : STD_LOGIC; + SIGNAL hs_in_txdetectrxloopback : STD_LOGIC; + SIGNAL hs_in_txmargin_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_txpma_local_clk : STD_LOGIC; + + SIGNAL hs_out_hip_phystatus : STD_LOGIC; + SIGNAL hs_out_hip_rxd_ch : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL hs_out_hip_rxelecidle : STD_LOGIC; + SIGNAL hs_out_hip_rxstatus_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_hip_rxvalid : STD_LOGIC; + SIGNAL hs_out_hip_tx_clk : STD_LOGIC; + SIGNAL hs_out_pcs_eidleinfersel_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_pcs_powerdown_ch : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hs_out_pcs_rate : STD_LOGIC; + SIGNAL hs_out_pcs_rxpolarity : STD_LOGIC; + SIGNAL hs_out_pcs_txd_ch : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL hs_out_pcs_txdeemph : STD_LOGIC; + SIGNAL hs_out_pcs_txdetectrxloopback : STD_LOGIC; + SIGNAL hs_out_pcs_txmargin_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_phystatus : STD_LOGIC; + SIGNAL hs_out_rxd_ch : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL hs_out_rxelecidle : STD_LOGIC; + SIGNAL hs_out_rxstatus_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_rxvalid : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////////// + -- sub-block interface: pipe_interface ---------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + -- inputs + SIGNAL pi_in_pipe_tx_clk : STD_LOGIC; + SIGNAL pi_in_powerdown : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL pi_in_refclk_b : STD_LOGIC; + SIGNAL pi_in_refclk_b_reset_n : STD_LOGIC; + SIGNAL pi_in_revloopback : STD_LOGIC; + SIGNAL pi_in_state_transition_done : STD_LOGIC; + SIGNAL pi_in_tx_elec_idle_comp : STD_LOGIC; + SIGNAL pi_in_tx_pipe_reset_n : STD_LOGIC; + SIGNAL pi_in_txd_ch : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL pi_in_txd_ch_dprio : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL pi_in_txdetectrxloopback : STD_LOGIC; + SIGNAL pi_in_txelecidle : STD_LOGIC; + SIGNAL pi_in_txd_ch_tmp : STD_LOGIC_VECTOR(43 DOWNTO 0); -- before interleaving in dwidth_single PMA + + -- outputs + SIGNAL pi_out_powerstate : STD_LOGIC_VECTOR(3 DOWNTO 0); -- to top - both cmu and rx + SIGNAL pi_out_rev_loopbk : STD_LOGIC; -- to TD + SIGNAL pi_out_tx_elec_idle : STD_LOGIC; -- to tx PMA - TX sending electrical idle + SIGNAL pi_out_txd : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL pi_out_txdetectrx : STD_LOGIC; -- to tx PMA - RX_DET + + -- new input in CYCLONEIV - ww26.5 ===================================== + -- from PLD + SIGNAL pi_in_txdeemph : STD_LOGIC; + SIGNAL pi_in_txmargin : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL pi_in_txswing : STD_LOGIC; + + -- new output in CYCLONEIV - ww26.5 ==================================== + -- exposured to digi_top + SIGNAL pi_out_txdeemph_int : STD_LOGIC; + SIGNAL pi_out_txmargin_int : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL pi_out_txswing_int : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////////// + -- sub-block interface: tx digital -------------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + -- inputs + SIGNAL td_in_phfifourst_tx : STD_LOGIC; + SIGNAL td_in_pld_tx_clk : STD_LOGIC; + SIGNAL td_in_polinv_tx : STD_LOGIC; + SIGNAL td_in_rddisable_tx : STD_LOGIC; + SIGNAL td_in_refclk_pma : STD_LOGIC; + SIGNAL td_in_rev_loop_data : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL td_in_rev_loopbk : STD_LOGIC; + SIGNAL td_in_tx_ctl_ts : STD_LOGIC; + SIGNAL td_in_tx_data_ts : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL td_in_txd : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL td_in_txfifo_shared_sig_in_ch0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL td_in_txfifo_shared_sig_in_q0_ch0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL td_in_txpcs_rst : STD_LOGIC; + SIGNAL td_in_txpma_local_clk : STD_LOGIC; + SIGNAL td_in_wrenable_tx : STD_LOGIC; + + -- new input in CYCLONEIV - ww26.5 ====================================== + + -- freeze pointer for TX/RX phase comp FIFO during freq negotiation + -- to tx_ctrl from rx_digi (auto_speed_neg sub-block) + SIGNAL td_in_freeze_ptr : STD_LOGIC; + -- to tx_ctrl from TX PMA local clock divider + SIGNAL td_in_gen2ngen1 : STD_LOGIC; + -- to tx_ctrl from central clock divider + SIGNAL td_in_gen2ngen1_bundle : STD_LOGIC; + -- to tx_ctrl from PLD (RX polarity inversion dynamic control) + -- paired with polinv_tx + -- path: polinv_rx (pld) -> tx_digi (tx_ctrl after encoder) -> + -- (just a simple wire in tx_ctrl so leaving it out of tx) + -- rx_pipe (mux with rxpolarity) -> rx_digi (wordalign and decoder) + SIGNAL td_in_polinv_rx : STD_LOGIC; + -- to tx_ctrl from PLD + -- generating powerdown_int output feeding both rx_pipe and tx_pipe + SIGNAL td_in_powerdown : STD_LOGIC_VECTOR(1 DOWNTO 0); + -- to tx_ctrl from quad pcs top + -- generating rate_int output feeding rx_digi (auto_speed_neg) + SIGNAL td_in_rate : STD_LOGIC; + -- to tx_ctrl from quad pcs top + -- generating revloopback_int output feeding tx_pipe + SIGNAL td_in_revloopback : STD_LOGIC; + -- to tx_ctrl from quad pcs top (no functionality change) + -- path: rxpolarity (pld) -> tx_digi (tx_ctrl)-> + -- rx_pipe (muxing with polinv_rx) --> rx_digi + SIGNAL td_in_rxpolarity : STD_LOGIC; + -- to tx_ctrl from quad pcs top + -- (just a simple wire in tx_ctrl so leaving it out of tx) + -- generating txdetectrxloopback_int output feeding tx_pipe + SIGNAL td_in_txdetectrxloopback : STD_LOGIC; + + -- new output in CYCLONEIV - ww26.5 =================================== + -- to rx_digi muxed with rxpolarity_int + SIGNAL td_out_polinv_rx_int : STD_LOGIC; + -- to rx_pipe and tx_pipe + SIGNAL td_out_powerdown_int : STD_LOGIC_VECTOR(1 DOWNTO 0); + -- to tx_pipe + SIGNAL td_out_revloopback_int : STD_LOGIC; + -- to rx_digi (mux with polinv_rx_int) + SIGNAL td_out_rxpolarity_int : STD_LOGIC; + -- to tx_pipe + SIGNAL td_out_txdetectrxloopback_int : STD_LOGIC; + + -- outputs + SIGNAL td_out_empty_tx : STD_LOGIC; + SIGNAL td_out_encoder_testbus : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL td_out_full_tx : STD_LOGIC; + SIGNAL td_out_pudr : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL td_out_rd_enable_sync : STD_LOGIC; + SIGNAL td_out_refclk_b : STD_LOGIC; + SIGNAL td_out_tx_clk_out : STD_LOGIC; + SIGNAL td_out_tx_ctl_tc : STD_LOGIC; + SIGNAL td_out_tx_ctrl_testbus : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL td_out_tx_data_tc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL td_out_tx_pipe_clk : STD_LOGIC; + SIGNAL td_out_tx_pipe_electidle : STD_LOGIC; + SIGNAL td_out_tx_pipe_soft_reset : STD_LOGIC; + SIGNAL td_out_txfifo_shared_sig_out : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL td_out_txlp20b : STD_LOGIC_VECTOR(19 DOWNTO 0); + + -- new ports in ww47 -------------------------------------------------- + SIGNAL td_in_prbs_cid_en : STD_LOGIC; --PRBS-CID dynamic signal + SIGNAL td_in_tx_boundary_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); + + -- new signal inputs for bundling + SIGNAL td_in_tx_div2_sync_in_centrl : STD_LOGIC; + SIGNAL td_in_tx_div2_sync_in_quad_up : STD_LOGIC; + SIGNAL td_in_tx_div2_sync_in_quad_down : STD_LOGIC; + SIGNAL td_in_wr_enable_in_centrl : STD_LOGIC; + SIGNAL td_in_wr_enable_in_quad_up : STD_LOGIC; + SIGNAL td_in_wr_enable_in_quad_down : STD_LOGIC; + SIGNAL td_in_rd_enable_in_centrl : STD_LOGIC; + SIGNAL td_in_rd_enable_in_quad_up : STD_LOGIC; + SIGNAL td_in_rd_enable_in_quad_down : STD_LOGIC; + SIGNAL td_in_fifo_select_in_centrl : STD_LOGIC; + SIGNAL td_in_fifo_select_in_quad_up : STD_LOGIC; + SIGNAL td_in_fifo_select_in_quad_down : STD_LOGIC; + SIGNAL td_in_reset_pc_ptrs : STD_LOGIC; + SIGNAL td_in_reset_pc_ptrs_in_centrl : STD_LOGIC; + SIGNAL td_in_reset_pc_ptrs_in_quad_up : STD_LOGIC; + SIGNAL td_in_reset_pc_ptrs_in_quad_down : STD_LOGIC; + + SIGNAL td_in_tx_div2_sync_in_pipe_quad_up : STD_LOGIC; + SIGNAL td_in_tx_div2_sync_in_pipe_quad_down : STD_LOGIC; + SIGNAL td_in_wr_enable_in_pipe_quad_up : STD_LOGIC; + SIGNAL td_in_wr_enable_in_pipe_quad_down : STD_LOGIC; + SIGNAL td_in_rd_enable_in_pipe_quad_up : STD_LOGIC; + SIGNAL td_in_rd_enable_in_pipe_quad_down : STD_LOGIC; + SIGNAL td_in_fifo_select_in_pipe_quad_up : STD_LOGIC; + SIGNAL td_in_fifo_select_in_pipe_quad_down : STD_LOGIC; + + SIGNAL td_in_dis_pc_byte : STD_LOGIC; + + -- new outputs for bundling and auto speed + SIGNAL td_out_tx_div2_sync_out_pipe : STD_LOGIC; + SIGNAL td_out_fifo_select_out_pipe : STD_LOGIC; + SIGNAL td_out_wr_enable_out_pipe : STD_LOGIC; + SIGNAL td_out_rd_enable_out_pipe : STD_LOGIC; + -- ww47 new ports end --------------------------------------------------------- + + -- new ports in ww12 ---------------------------------------------------------- + -- push through TX Phase Comp FIFO + SIGNAL td_in_txswing : STD_LOGIC; + SIGNAL td_in_pcs_txdeemph : STD_LOGIC; + SIGNAL td_in_pcs_txmargin : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX PIPE interface signals + SIGNAL td_in_eidleinfersel : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- push through TX Phase Comp FIFO + SIGNAL td_out_phfifo_txswing : STD_LOGIC; + SIGNAL td_out_phfifo_txdeemph : STD_LOGIC; + SIGNAL td_out_phfifo_txmargin : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX PIPE interface signals + SIGNAL td_out_gray_eidleinfersel : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- new outputs for bundling and auto speed + -- splitting _out_pipe into _up and _down + SIGNAL td_out_tx_div2_sync_out_pipe_up : STD_LOGIC; + SIGNAL td_out_fifo_select_out_pipe_up : STD_LOGIC; + SIGNAL td_out_wr_enable_out_pipe_up : STD_LOGIC; + SIGNAL td_out_rd_enable_out_pipe_up : STD_LOGIC; + SIGNAL td_out_tx_div2_sync_out_pipe_down : STD_LOGIC; + SIGNAL td_out_fifo_select_out_pipe_down : STD_LOGIC; + SIGNAL td_out_wr_enable_out_pipe_down : STD_LOGIC; + SIGNAL td_out_rd_enable_out_pipe_down : STD_LOGIC; + -- ww12 new ports end --------------------------------------------------------- + + --/////////////////////////////////////////////////////////////////////////////// + -- Internal Variables --------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + SIGNAL i : INTEGER; + SIGNAL j : INTEGER; + SIGNAL rxdet_fixclk_reg : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////////// + -- Timing - INPUT BUFFERS ----------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + SIGNAL rxrst_int_wire : STD_LOGIC; + + --ww47 new inputs + SIGNAL hipdatain_in : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL hipdetectrxloop_in : STD_LOGIC; + SIGNAL hipforceelecidle_in : STD_LOGIC; + SIGNAL hippowerdn_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hiptxdeemph_in : STD_LOGIC; + SIGNAL hiptxmargin_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL iqpphfifoxnbytesel_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL iqpphfifoxnrdclk_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL iqpphfifoxnrdenable_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL iqpphfifoxnwrenable_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL phfifobyteserdisable_in : STD_LOGIC; + SIGNAL phfifoptrsreset_in : STD_LOGIC; + SIGNAL phfifoxnbytesel_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxnptrsreset_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxnrdclk_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxnrdenable_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL phfifoxnwrenable_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL prbscidenable_in : STD_LOGIC; + + -- cycloneiv only + SIGNAL phfifox4rdclk_in : STD_LOGIC; + SIGNAL phfifox4wrenable_in : STD_LOGIC; + SIGNAL phfifox4rdenable_in : STD_LOGIC; + SIGNAL phfifox4bytesel_in : STD_LOGIC; + + -- ww12.08 inputs + SIGNAL elecidleinfersel_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hipelecidleinfersel_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + + --/////////////////////////////////////////////////////////////////////////////// + -- TIMING -- TCO/TSU/HOLD // + --/////////////////////////////////////////////////////////////////////////////// + + --/////////////////////////////////////////////////////////////////////////////// + -- dprio outputs + --/////////////////////////////////////////////////////////////////////////////// + + SIGNAL dprioin_in : STD_LOGIC_VECTOR(149 DOWNTO 0); + + -- PCS - disabled with mpcs_dpriodisable - enable case by case + SIGNAL mpcs_dpriodisable : STD_LOGIC; + -- X-HDL generated signals + + SIGNAL xhdl0 : STD_LOGIC_VECTOR(1 DOWNTO 0); +BEGIN + + ------------------------ + -- Wire Delay Block -- + ------------------------ + WireDelay : BLOCK + BEGIN + bits_phfifoxnbytesel : FOR i in phfifoxnbytesel'RANGE GENERATE + VitalWireDelay (phfifoxnbytesel_ipd(i),phfifoxnbytesel(i), tipd_phfifoxnbytesel(i)); + END GENERATE; + bits_dispval : FOR i in dispval'RANGE GENERATE + VitalWireDelay (dispval_ipd(i),dispval(i), tipd_dispval(i)); + END GENERATE; + VitalWireDelay (phfifoxnbottomwrenable_ipd,phfifoxnbottomwrenable, tipd_phfifoxnbottomwrenable); + VitalWireDelay (phfifoxntopwrenable_ipd,phfifoxntopwrenable, tipd_phfifoxntopwrenable); + VitalWireDelay (phfifoptrsreset_ipd,phfifoptrsreset, tipd_phfifoptrsreset); + bits_phfifoxnptrsreset : FOR i in phfifoxnptrsreset'RANGE GENERATE + VitalWireDelay (phfifoxnptrsreset_ipd(i),phfifoxnptrsreset(i), tipd_phfifoxnptrsreset(i)); + END GENERATE; + bits_forcedisp : FOR i in forcedisp'RANGE GENERATE + VitalWireDelay (forcedisp_ipd(i),forcedisp(i), tipd_forcedisp(i)); + END GENERATE; + bits_hiptxmargin : FOR i in hiptxmargin'RANGE GENERATE + VitalWireDelay (hiptxmargin_ipd(i),hiptxmargin(i), tipd_hiptxmargin(i)); + END GENERATE; + bits_iqpphfifoxnwrenable : FOR i in iqpphfifoxnwrenable'RANGE GENERATE + VitalWireDelay (iqpphfifoxnwrenable_ipd(i),iqpphfifoxnwrenable(i), tipd_iqpphfifoxnwrenable(i)); + END GENERATE; + VitalWireDelay (phfiforddisable_ipd,phfiforddisable, tipd_phfiforddisable); + bits_phfifoxnrdenable : FOR i in phfifoxnrdenable'RANGE GENERATE + VitalWireDelay (phfifoxnrdenable_ipd(i),phfifoxnrdenable(i), tipd_phfifoxnrdenable(i)); + END GENERATE; + bits_powerdn : FOR i in powerdn'RANGE GENERATE + VitalWireDelay (powerdn_ipd(i),powerdn(i), tipd_powerdn(i)); + END GENERATE; + VitalWireDelay (rateswitchisdone_ipd,rateswitchisdone, tipd_rateswitchisdone); + VitalWireDelay (phfifoxntopbytesel_ipd,phfifoxntopbytesel, tipd_phfifoxntopbytesel); + bits_ctrlenable : FOR i in ctrlenable'RANGE GENERATE + VitalWireDelay (ctrlenable_ipd(i),ctrlenable(i), tipd_ctrlenable(i)); + END GENERATE; + VitalWireDelay (phfifoxntoprdclk_ipd,phfifoxntoprdclk, tipd_phfifoxntoprdclk); + VitalWireDelay (hiptxdeemph_ipd,hiptxdeemph, tipd_hiptxdeemph); + VitalWireDelay (freezptr_ipd,freezptr, tipd_freezptr); + VitalWireDelay (refclk_ipd,refclk, tipd_refclk); + VitalWireDelay (phfifox4bytesel_ipd,phfifox4bytesel, tipd_phfifox4bytesel); + VitalWireDelay (rateswitchxndone_ipd,rateswitchxndone, tipd_rateswitchxndone); + VitalWireDelay (forcedispcompliance_ipd,forcedispcompliance, tipd_forcedispcompliance); + bits_datainfull : FOR i in datainfull'RANGE GENERATE + VitalWireDelay (datainfull_ipd(i),datainfull(i), tipd_datainfull(i)); + END GENERATE; + VitalWireDelay (phfifox4rdclk_ipd,phfifox4rdclk, tipd_phfifox4rdclk); + VitalWireDelay (phfiforeset_ipd,phfiforeset, tipd_phfiforeset); + bits_dprioin : FOR i in dprioin'RANGE GENERATE + VitalWireDelay (dprioin_ipd(i),dprioin(i), tipd_dprioin(i)); + END GENERATE; + VitalWireDelay (coreclk_ipd,coreclk, tipd_coreclk); + VitalWireDelay (pipestatetransdone_ipd,pipestatetransdone, tipd_pipestatetransdone); + VitalWireDelay (rateswitch_ipd,rateswitch, tipd_rateswitch); + VitalWireDelay (hipforceelecidle_ipd,hipforceelecidle, tipd_hipforceelecidle); + VitalWireDelay (phfifox4rdenable_ipd,phfifox4rdenable, tipd_phfifox4rdenable); + VitalWireDelay (phfifowrenable_ipd,phfifowrenable, tipd_phfifowrenable); + bits_datain : FOR i in datain'RANGE GENERATE + VitalWireDelay (datain_ipd(i),datain(i), tipd_datain(i)); + END GENERATE; + VitalWireDelay (enrevparallellpbk_ipd,enrevparallellpbk, tipd_enrevparallellpbk); + VitalWireDelay (forceelecidle_ipd,forceelecidle, tipd_forceelecidle); + bits_phfifoxnrdclk : FOR i in phfifoxnrdclk'RANGE GENERATE + VitalWireDelay (phfifoxnrdclk_ipd(i),phfifoxnrdclk(i), tipd_phfifoxnrdclk(i)); + END GENERATE; + VitalWireDelay (pipetxswing_ipd,pipetxswing, tipd_pipetxswing); + bits_pipetxmargin : FOR i in pipetxmargin'RANGE GENERATE + VitalWireDelay (pipetxmargin_ipd(i),pipetxmargin(i), tipd_pipetxmargin(i)); + END GENERATE; + VitalWireDelay (phfifox4wrenable_ipd,phfifox4wrenable, tipd_phfifox4wrenable); + VitalWireDelay (pipetxdeemph_ipd,pipetxdeemph, tipd_pipetxdeemph); + bits_bitslipboundaryselect : FOR i in bitslipboundaryselect'RANGE GENERATE + VitalWireDelay (bitslipboundaryselect_ipd(i),bitslipboundaryselect(i), tipd_bitslipboundaryselect(i)); + END GENERATE; + VitalWireDelay (phfifobyteserdisable_ipd,phfifobyteserdisable, tipd_phfifobyteserdisable); + VitalWireDelay (dpriodisable_ipd,dpriodisable, tipd_dpriodisable); + VitalWireDelay (phfifoxnbottomrdclk_ipd,phfifoxnbottomrdclk, tipd_phfifoxnbottomrdclk); + VitalWireDelay (phfifoxnbottomrdenable_ipd,phfifoxnbottomrdenable, tipd_phfifoxnbottomrdenable); + bits_hippowerdn : FOR i in hippowerdn'RANGE GENERATE + VitalWireDelay (hippowerdn_ipd(i),hippowerdn(i), tipd_hippowerdn(i)); + END GENERATE; + VitalWireDelay (xgmctrl_ipd,xgmctrl, tipd_xgmctrl); + VitalWireDelay (invpol_ipd,invpol, tipd_invpol); + VitalWireDelay (hipdetectrxloop_ipd,hipdetectrxloop, tipd_hipdetectrxloop); + VitalWireDelay (localrefclk_ipd,localrefclk, tipd_localrefclk); + bits_revparallelfdbk : FOR i in revparallelfdbk'RANGE GENERATE + VitalWireDelay (revparallelfdbk_ipd(i),revparallelfdbk(i), tipd_revparallelfdbk(i)); + END GENERATE; + bits_iqpphfifoxnrdenable : FOR i in iqpphfifoxnrdenable'RANGE GENERATE + VitalWireDelay (iqpphfifoxnrdenable_ipd(i),iqpphfifoxnrdenable(i), tipd_iqpphfifoxnrdenable(i)); + END GENERATE; + VitalWireDelay (prbscidenable_ipd,prbscidenable, tipd_prbscidenable); + VitalWireDelay (digitalreset_ipd,digitalreset, tipd_digitalreset); + bits_iqpphfifoxnbytesel : FOR i in iqpphfifoxnbytesel'RANGE GENERATE + VitalWireDelay (iqpphfifoxnbytesel_ipd(i),iqpphfifoxnbytesel(i), tipd_iqpphfifoxnbytesel(i)); + END GENERATE; + bits_iqpphfifoxnrdclk : FOR i in iqpphfifoxnrdclk'RANGE GENERATE + VitalWireDelay (iqpphfifoxnrdclk_ipd(i),iqpphfifoxnrdclk(i), tipd_iqpphfifoxnrdclk(i)); + END GENERATE; + bits_phfifoxnwrenable : FOR i in phfifoxnwrenable'RANGE GENERATE + VitalWireDelay (phfifoxnwrenable_ipd(i),phfifoxnwrenable(i), tipd_phfifoxnwrenable(i)); + END GENERATE; + VitalWireDelay (quadreset_ipd,quadreset, tipd_quadreset); + bits_xgmdatain : FOR i in xgmdatain'RANGE GENERATE + VitalWireDelay (xgmdatain_ipd(i),xgmdatain(i), tipd_xgmdatain(i)); + END GENERATE; + VitalWireDelay (phfifoxnbottombytesel_ipd,phfifoxnbottombytesel, tipd_phfifoxnbottombytesel); + bits_hipdatain : FOR i in hipdatain'RANGE GENERATE + VitalWireDelay (hipdatain_ipd(i),hipdatain(i), tipd_hipdatain(i)); + END GENERATE; + VitalWireDelay (phfifoxntoprdenable_ipd,phfifoxntoprdenable, tipd_phfifoxntoprdenable); + VitalWireDelay (detectrxloop_ipd,detectrxloop, tipd_detectrxloop); + END BLOCK; + + + VITAL: PROCESS (coreclk_ipd, datain_ipd, ctrlenable_ipd, detectrxloop_ipd, dispval_ipd, forcedisp_ipd, forcedispcompliance_ipd, forceelecidle_ipd, phfifowrenable_ipd, powerdn_ipd, pipetxdeemph_ipd, pipetxswing_ipd, pipetxmargin_ipd) + + variable Tviol_coreclk_ctrlenable : std_ulogic := '0'; + variable TimingData_coreclk_ctrlenable : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_datain : std_ulogic := '0'; + variable TimingData_coreclk_datain : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_detectrxloop : std_ulogic := '0'; + variable TimingData_coreclk_detectrxloop : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_dispval : std_ulogic := '0'; + variable TimingData_coreclk_dispval : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_forcedisp : std_ulogic := '0'; + variable TimingData_coreclk_forcedisp : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_forcedispcompliance : std_ulogic := '0'; + variable TimingData_coreclk_forcedispcompliance : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_forceelecidle : std_ulogic := '0'; + variable TimingData_coreclk_forceelecidle : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_phfifowrenable : std_ulogic := '0'; + variable TimingData_coreclk_phfifowrenable : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_powerdn : std_ulogic := '0'; + variable TimingData_coreclk_powerdn : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_pipetxdeemph : std_ulogic := '0'; + variable TimingData_coreclk_pipetxdeemph : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_pipetxmargin : std_ulogic := '0'; + variable TimingData_coreclk_pipetxmargin : VitalTimingDataType := VitalTimingDataInit; + + variable Tviol_coreclk_pipetxswing : std_ulogic := '0'; + variable TimingData_coreclk_pipetxswing : VitalTimingDataType := VitalTimingDataInit; + + variable phfifooverflow_VitalGlitchData : VitalGlitchDataType; + variable phfifounderflow_VitalGlitchData : VitalGlitchDataType; + + BEGIN + + ------------------------ + -- Timing Check Section + ------------------------ + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_ctrlenable, + TimingData => TimingData_coreclk_ctrlenable, + TestSignal => ctrlenable_ipd, + TestSignalName => "CTRLENABLE", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_ctrlenable_coreclk_noedge_posedge, + SetupLow => tsetup_ctrlenable_coreclk_noedge_posedge, + HoldHigh => thold_ctrlenable_coreclk_noedge_posedge, + HoldLow => thold_ctrlenable_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_datain, + TimingData => TimingData_coreclk_datain, + TestSignal => datain_ipd, + TestSignalName => "DATAIN", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_datain_coreclk_noedge_posedge, + SetupLow => tsetup_datain_coreclk_noedge_posedge, + HoldHigh => thold_datain_coreclk_noedge_posedge, + HoldLow => thold_datain_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_detectrxloop, + TimingData => TimingData_coreclk_detectrxloop, + TestSignal => detectrxloop_ipd, + TestSignalName => "DETECTRXLOOP", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_detectrxloop_coreclk_noedge_posedge, + SetupLow => tsetup_detectrxloop_coreclk_noedge_posedge, + HoldHigh => thold_detectrxloop_coreclk_noedge_posedge, + HoldLow => thold_detectrxloop_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_dispval, + TimingData => TimingData_coreclk_dispval, + TestSignal => dispval_ipd, + TestSignalName => "DISPVAL", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_dispval_coreclk_noedge_posedge, + SetupLow => tsetup_dispval_coreclk_noedge_posedge, + HoldHigh => thold_dispval_coreclk_noedge_posedge, + HoldLow => thold_dispval_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_forcedisp, + TimingData => TimingData_coreclk_forcedisp, + TestSignal => forcedisp_ipd, + TestSignalName => "FORCEDISP", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_forcedisp_coreclk_noedge_posedge, + SetupLow => tsetup_forcedisp_coreclk_noedge_posedge, + HoldHigh => thold_forcedisp_coreclk_noedge_posedge, + HoldLow => thold_forcedisp_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_forceelecidle, + TimingData => TimingData_coreclk_forceelecidle, + TestSignal => forceelecidle_ipd, + TestSignalName => "FORCEELECIDLE", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_forceelecidle_coreclk_noedge_posedge, + SetupLow => tsetup_forceelecidle_coreclk_noedge_posedge, + HoldHigh => thold_forceelecidle_coreclk_noedge_posedge, + HoldLow => thold_forceelecidle_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_phfifowrenable, + TimingData => TimingData_coreclk_phfifowrenable, + TestSignal => phfifowrenable_ipd, + TestSignalName => "PHFIFOWRENABLE", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_phfifowrenable_coreclk_noedge_posedge, + SetupLow => tsetup_phfifowrenable_coreclk_noedge_posedge, + HoldHigh => thold_phfifowrenable_coreclk_noedge_posedge, + HoldLow => thold_phfifowrenable_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_powerdn, + TimingData => TimingData_coreclk_powerdn, + TestSignal => powerdn_ipd, + TestSignalName => "POWERDN", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_powerdn_coreclk_noedge_posedge, + SetupLow => tsetup_powerdn_coreclk_noedge_posedge, + HoldHigh => thold_powerdn_coreclk_noedge_posedge, + HoldLow => thold_powerdn_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + + + VitalSetupHoldCheck ( + Violation => Tviol_coreclk_pipetxswing, + TimingData => TimingData_coreclk_pipetxswing, + TestSignal => pipetxswing_ipd, + TestSignalName => "PIPETXSWING", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_pipetxswing_coreclk_noedge_posedge, + SetupLow => tsetup_pipetxswing_coreclk_noedge_posedge, + HoldHigh => thold_pipetxswing_coreclk_noedge_posedge, + HoldLow => thold_pipetxswing_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_TX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + + END IF; + + ---------------------- + -- Path Delay Section + ---------------------- + + VitalPathDelay01 ( + OutSignal => phfifooverflow, + OutSignalName => "PHFIFOOVERFLOW", + OutTemp => td_out_full_tx, + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_phfifooverflow_posedge, TRUE)), + GlitchData => phfifooverflow_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => phfifounderflow, + OutSignalName => "PHFIFOUNDERFLOW", + OutTemp => td_out_empty_tx, + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_phfifounderflow_posedge, TRUE)), + GlitchData => phfifounderflow_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + END PROCESS; + + ---------------------------------------- + -- Cyclone IV GX_modify due to width change + ---------------------------------------- + ctrlenable_ipd (3 DOWNTO 2) <= "00"; + datainfull_siv(43 DOWNTO 33) <= (others => '0'); + datainfull_siv(10 DOWNTO 0) <= datainfull_ipd(10 DOWNTO 0); + datainfull_siv(32 DOWNTO 22) <= datainfull_ipd(21 DOWNTO 11); + datainfull_siv(21 DOWNTO 11) <= (others => '0'); + dispval_ipd (3 DOWNTO 2) <= "00"; + forcedisp_ipd (3 DOWNTO 2) <= "00"; + + ------------------------ + -- Functionality Section -- + ------------------------ + -- cycloneiv only + phfifox4rdclk_in <= '1' WHEN (phfifox4rdclk = '1') ELSE '0'; + phfifox4wrenable_in <= '1' WHEN (phfifox4wrenable = '1') ELSE '0'; + phfifox4rdenable_in <= '1' WHEN (phfifox4rdenable = '1') ELSE '0'; + phfifox4bytesel_in <= '1' WHEN (phfifox4bytesel = '1') ELSE '0'; + + hipdatain_in <= hipdatain; + hipdetectrxloop_in <= hipdetectrxloop; + hipforceelecidle_in <= hipforceelecidle; + hippowerdn_in <= hippowerdn; + hiptxdeemph_in <= hiptxdeemph; + hiptxmargin_in <= hiptxmargin; + iqpphfifoxnbytesel_in <= iqpphfifoxnbytesel; + iqpphfifoxnrdclk_in <= iqpphfifoxnrdclk; + iqpphfifoxnrdenable_in <= iqpphfifoxnrdenable; + iqpphfifoxnwrenable_in <= iqpphfifoxnwrenable; + phfifobyteserdisable_in <= phfifobyteserdisable; + phfifoptrsreset_in <= phfifoptrsreset; + phfifoxnbytesel_in <= phfifoxnbytesel; + phfifoxnptrsreset_in <= phfifoxnptrsreset; + phfifoxnrdclk_in <= phfifoxnrdclk; + phfifoxnrdenable_in <= phfifoxnrdenable; + phfifoxnwrenable_in <= phfifoxnwrenable; + prbscidenable_in <= prbscidenable; + dprioin_in <= dprioin; + + PROCESS + VARIABLE i : INTEGER := 0; + VARIABLE txt : LINE; + + PROCEDURE compute_rprbs_sel ( + pma_doublewidth : IN std_logic; + pma_width : IN std_logic; + test_mode : IN string; result : OUT std_logic_vector) IS + + VARIABLE res : std_logic_vector(2 DOWNTO 0); + VARIABLE temp_xhdl20 : STD_LOGIC_VECTOR(1 DOWNTO 0); + BEGIN + temp_xhdl20 := pma_doublewidth & pma_width; + CASE temp_xhdl20 IS + WHEN "00" => + IF ((test_mode = "prbs_8") OR (test_mode = "prbs8")) THEN + res := "000"; + ELSIF (test_mode = "prbs7") THEN + res := "010"; + ELSIF (test_mode = "prbs23") THEN + res := "100"; + ELSIF (test_mode = "high frequency") THEN + res := "001"; + ELSE + res := "000"; -- default + END IF; + WHEN "01" => + IF ((test_mode = "prbs_10") OR (test_mode = "prbs10")) THEN + res := "000"; + ELSIF (test_mode = "high frequency") THEN + res := "001"; + ELSIF (test_mode = "low frequency") THEN + res := "010"; + ELSIF (test_mode = "mixed frequency") THEN + res := "011"; + ELSE + res := "000"; -- default + END IF; + WHEN "10" => + IF ((test_mode = "prbs_7") OR (test_mode = "prbs7")) THEN + res := "000"; + ELSIF (test_mode = "PRBS_23" OR test_mode = "prbs_23" OR test_mode = "prbs23") THEN + res := "001"; + ELSIF (test_mode = "high frequency") THEN + res := "010"; + ELSE + res := "000"; -- default + END IF; + WHEN "11" => + IF ((test_mode = "prbs_7") OR (test_mode = "prbs7")) THEN + res := "000"; + ELSIF ((test_mode = "PRBS_23") OR (test_mode = "prbs_23") OR (test_mode = "prbs23")) THEN + res := "001"; + ELSIF (test_mode = "high frequency") THEN + res := "010"; + ELSIF (test_mode = "low frequency") THEN + res := "011"; + ELSIF (test_mode = "mixed frequency") THEN + res := "100"; + ELSE + res := "000"; -- default + END IF; + WHEN OTHERS => + --WRITE(txt,string'("Invalid pma_doublewidth and pma_width selection")); + --WRITELINE (OUTPUT,txt); + + END CASE; + result := res; + END compute_rprbs_sel; + + VARIABLE init_rprbs_sel_val : std_logic_vector(2 DOWNTO 0); + VARIABLE init_rpma_doublewidth_tx_var,init_rpmadwidth_tx_var : STD_LOGIC; + + BEGIN + init_r8b10b_enc_ibm_en <= mux_select((enc_8b_10b_compatibility_mode = ("true")), '1', '0'); + init_rbist_sel <= mux_select((self_test_mode = ("incremental")), "00", mux_select((self_test_mode = ("cjpat")), "01", mux_select((self_test_mode = ("crpat")), "10", "00"))); + init_rbisten_tx <= mux_select(((enable_self_test_mode = ("true")) AND (self_test_mode = ("incremental") OR self_test_mode = ("cjpat") OR self_test_mode = ("cjpat"))), '1', '0'); + init_rcascaded_8b10b_en_tx <= mux_select((enc_8b_10b_mode = ("cascaded")), '1', '0'); + init_rcxpat_chnl_en <= mux_select((channel_number = 1), "01", mux_select((channel_number = 2), "10", mux_select((channel_number = 3), "11", "00"))); + init_rdwidth_tx <= mux_select((use_double_data_mode = ("true")), '1', '0'); + init_renbitrev_tx <= mux_select((enable_bit_reversal = ("true")), '1', '0'); + init_rendec_data_sel_tx <= mux_select((protocol_hint = ("xaui")), '0', '1'); + init_rendec_tx <= mux_select((enc_8b_10b_mode /= ("none")), '1', '0'); + init_renpolinv_tx <= mux_select((allow_polarity_inversion = ("true")), '1', '0'); + init_rensymswap_tx <= mux_select((alpha_tolower(enable_symbol_swap) = ("true")), '1', '0'); + init_rforce_disp <= mux_select((disparity_mode = ("new")), '1', '0'); + init_rforce_echar <= mux_select((force_echar = ("true")), '1', '0'); + init_rforce_kchar <= mux_select((force_kchar = ("true")), '1', '0'); + init_rfreerun_tx <= mux_select((reset_clock_output_during_digital_reset = ("false")), '1', '0'); + init_rge_xaui_tx <= mux_select((protocol_hint = ("gige") OR enable_idle_selection = ("true")), '1', '0'); + init_rib_force_disp <= mux_select((disparity_mode = ("legacy")), '1', '0'); + init_rindv_tx <= mux_select((channel_bonding = ("x4") OR channel_bonding = ("x8") OR protocol_hint = ("xaui")), '0', '1'); + init_rphfifo_master_sel_tx <= mux_select((channel_bonding = ("x8")), '0', '1'); + init_rphfifopldentx <= '1'; + init_rphfifoursttx <= '1'; + + IF (alpha_tolower(use_serializer_double_data_mode) = "true") THEN + init_rpma_doublewidth_tx <= '1'; + init_rpma_doublewidth_tx_var := '1'; + ELSE + init_rpma_doublewidth_tx <= '0'; + init_rpma_doublewidth_tx_var := '0'; + END IF; + + IF ((enc_8b_10b_mode = "none") AND ((channel_width = 8) OR (channel_width = 16) OR (channel_width = 32))) THEN + init_rpmadwidth_tx <= '0'; + init_rpmadwidth_tx_var := '0'; + ELSE + init_rpmadwidth_tx <= '1'; + init_rpmadwidth_tx_var := '1'; + END IF; + + compute_rprbs_sel(init_rpma_doublewidth_tx_var,init_rpmadwidth_tx_var,self_test_mode,init_rprbs_sel_val); + init_rprbs_sel <= init_rprbs_sel_val; + + init_rprbsen_tx <= mux_select(((enable_self_test_mode = ("true")) AND (self_test_mode /= ("incremental")) AND (self_test_mode /= ("cjpat")) AND (self_test_mode /= ("crpat"))), '1', '0'); + init_rrev_loopbk <= mux_select((enable_reverse_parallel_loopback = ("true")), '1', '0'); + init_rtx_pipe_enable <= mux_select((protocol_hint = ("pcie") OR protocol_hint = ("pcie2")), '1', '0'); + init_rtxfifo_dis <= mux_select((enable_phfifo_bypass = ("true")), '1', '0'); + init_rtxfifo_lowlatency_en <= mux_select((disable_ph_low_latency_mode = ("false")), '1', '0'); + init_rtxpcsbypass_en <= mux_select((datapath_low_latency_mode = ("true")), '1', '0'); + init_rtxrdclksel <= mux_select((refclk_select = ("central")), '1', '0'); + init_rtxswing_sel_ena <= mux_select((pipe_voltage_swing_control = ("true")), '1', '0'); + init_rtxwrclksel <= mux_select((wr_clk_mux_select = ("int_clk") OR wr_clk_mux_select = ("int clk") OR wr_clk_mux_select = ("internal clock")), '1', '0'); + init_rclkcmpinsertpad <= '1'; + init_rrdwidth_rx <= '1'; + init_rrx_detect_bypass <= '1'; + init_rrx_pipe_enable <= '1'; + init_rtx_elec_idle_delay <= "011"; + init_is_lane0 <= mux_select((channel_number = 0), '1', '0'); + init_scan_mode <= '0'; + init_rauto_speed_ena <= mux_select((alpha_tolower(pipe_auto_speed_nego_enable) = ("true")), '1', '0'); + init_rfreq_sel <= mux_select((pipe_freq_scale_mode = ("data width")), '0', '1'); + init_rtxpcsclkpwdn <= '0'; + init_rcid_pattern_tx <= mux_select((prbs_cid_pattern = ("true")), '1', '0'); + init_rcid_len_tx <= int2bin(prbs_cid_pattern_length, 8); + IF ((channel_bonding /= "x8") OR (cycloneiv_tx_pcs_mph_fifo_xn_mapping(ph_fifo_xn_select,ph_fifo_xn_mapping0,ph_fifo_xn_mapping1,ph_fifo_xn_mapping2) = "central")) THEN + init_rmaster_tx <= '1'; + ELSE + init_rmaster_tx <= '0'; + END IF; + -- flip + IF (cycloneiv_tx_pcs_mph_fifo_xn_mapping(ph_fifo_xn_select,ph_fifo_xn_mapping0,ph_fifo_xn_mapping1,ph_fifo_xn_mapping2) = "down") THEN + init_rmaster_up_tx <= '1'; + ELSE + init_rmaster_up_tx <= '0'; + END IF; + init_rself_sw_en_tx <= mux_select((alpha_tolower(auto_spd_self_switch_enable) = ("true")), '1', '0'); + init_rpipeline_bypass_tx <= mux_select((alpha_tolower(iqp_bypass) = ("true")), '1', '0'); + init_rphfifo_regmode_tx <= mux_select((ph_fifo_reg_mode = ("true")), '1', '0'); + init_rtxbitslip_en <= mux_select((bitslip_enable = ("true")), '1', '0'); + init_rhip_ena <= mux_select((hip_enable = ("true")), '1', '0'); + WAIT; + END PROCESS; + +-- new DPRIO model begin -- +-- --------------------------------------------------------------------------- +-- Set DPRIO CRAM input from dprioin +-- --------------------------------------------------------------------------- +-- Existing +dprioin_is_lane0 <= init_is_lane0; +dprioin_rauto_speed_ena <= dprioin_in(rauto_speed_ena_TX_IDX); +dprioin_rclkcmpinsertpad <= init_rclkcmpinsertpad; -- rx only <=<=<=<=<=<=<=<=<= pipe <=<=<=<=<=<=<=<=<=<=<= +dprioin_rendec_data_sel_tx <= init_rendec_data_sel_tx; -- disable reconfiguration for quad-level crams +dprioin_rfreq_sel <= dprioin_in(rfreq_sel_TX_IDX); +dprioin_rhip_ena <= dprioin_in(rhip_ena_TX_IDX); +dprioin_rmaster_tx <= init_rmaster_tx; +dprioin_rmaster_up_tx <= init_rmaster_up_tx; +dprioin_rindv_tx <= init_rindv_tx; -- disable reconfiguration for quad-level crams +dprioin_rphfifo_master_sel_tx <= init_rphfifo_master_sel_tx; -- disable reconfiguration for quad-level crams +dprioin_rpma_doublewidth_tx <= dprioin_in(rpma_doublewidth_tx_TX_IDX); --dprioen +dprioin_rpmadwidth_tx <= dprioin_in(rpmadwidth_tx_TX_IDX); --dprioen +dprioin_rrdwidth_rx <= init_rrdwidth_rx; -- rx only +dprioin_rrx_detect_bypass <= init_rrx_detect_bypass; -- rx only +dprioin_rrx_pipe_enable <= init_rrx_pipe_enable; -- rx only +dprioin_rtx_cmu_sel <= dprioin_in(rtx_cmu_sel_TX_IDX); +dprioin_scan_mode <= init_scan_mode; + +-- PCS Per Channel TX Control Register 1 for Channel 0 +dprioin_rforce_disp <= dprioin(rforce_disp_TXPCS_IDX_0); +dprioin_rrev_loopbk <= dprioin(rrev_loopbk_TXPCS_IDX_0); +dprioin_rtxrdclksel <= dprioin(rtxrdclksel_TXPCS_IDX_0); +dprioin_rtxwrclksel <= dprioin(rtxwrclksel_TXPCS_IDX_0); +dprioin_rfreerun_tx <= dprioin(rfreerun_tx_TXPCS_IDX_0); +dprioin_rtxurstpcs <= dprioin(rtxurstpcs_TXPCS_IDX_0); +dprioin_reserved_0_TB1 <= dprioin(reserved_0_TB1_TXPCS_IDX_0); +dprioin_rphfifoursttx <= dprioin(rphfifoursttx_TXPCS_IDX_0); +dprioin_rphfifopldentx <= dprioin(rphfifopldentx_TXPCS_IDX_0); +dprioin_rge_xaui_tx <= dprioin(rge_xaui_tx_TXPCS_IDX_0); +dprioin_rdwidth_tx <= dprioin(rdwidth_tx_TXPCS_IDX_0); +dprioin_rtxfifo_lowlatency_en <= dprioin(rtxfifo_lowlatency_en_TXPCS_IDX_0); +dprioin_rib_force_disp <= dprioin(rib_force_disp_TXPCS_IDX_0); +dprioin_rtxfifo_dis <= dprioin(rtxfifo_dis_TXPCS_IDX_0); +dprioin_rforce_echar <= dprioin(rforce_echar_TXPCS_IDX_0); +dprioin_rforce_kchar <= dprioin(rforce_kchar_TXPCS_IDX_0); + +-- PCS Per Channel TX Control Register 2 for Channel 0 +dprioin_rtxpcsbypass_en <= dprioin(rtxpcsbypass_en_TXPCS_IDX_0); +dprioin_rcxpat_chnl_en <= dprioin(rcxpat_chnl_en_TXPCS_IDX_1 DOWNTO rcxpat_chnl_en_TXPCS_IDX_0); +dprioin_rbist_sel <= dprioin(rbist_sel_TXPCS_IDX_1 DOWNTO rbist_sel_TXPCS_IDX_0); +dprioin_rbisten_tx <= dprioin(rbisten_tx_TXPCS_IDX_0); +dprioin_rprbs_sel <= dprioin(rprbs_sel_TXPCS_IDX_2 DOWNTO rprbs_sel_TXPCS_IDX_0); +dprioin_rprbsen_tx <= dprioin(rprbsen_tx_TXPCS_IDX_0); +dprioin_renbitrev_tx <= dprioin(renbitrev_tx_TXPCS_IDX_0); +dprioin_renpolinv_tx <= dprioin(renpolinv_tx_TXPCS_IDX_0); +dprioin_rensymswap_tx <= dprioin(rensymswap_tx_TXPCS_IDX_0); +dprioin_rcascaded_8b10b_en_tx <= dprioin(rcascaded_8b10b_en_tx_TXPCS_IDX_0); +dprioin_r8b10b_enc_ibm_en <= dprioin(r8b10b_enc_ibm_en_TXPCS_IDX_0); +dprioin_rendec_tx <= dprioin(rendec_tx_TXPCS_IDX_0); + +-- PCS Per Channel TX Control Register 3 for Channel 0 +dprioin_reserved_0_TB3 <= dprioin(reserved_0_TB3_TXPCS_IDX_0); +dprioin_rcid_len_tx <= dprioin(rcid_len_tx_TXPCS_IDX_7 DOWNTO rcid_len_tx_TXPCS_IDX_0); +dprioin_rcid_pattern_tx <= dprioin(rcid_pattern_tx_TXPCS_IDX_0); +dprioin_rtxpcsclkpwdn <= dprioin(rtxpcsclkpwdn_TXPCS_IDX_0); +dprioin_rtxswing_sel_ena <= dprioin(rtxswing_sel_ena_TXPCS_IDX_0); +dprioin_rtx_elec_idle_delay <= dprioin(rtx_elec_idle_delay_TXPCS_IDX_2 DOWNTO rtx_elec_idle_delay_TXPCS_IDX_0); +dprioin_rtx_pipe_enable <= dprioin(rtx_pipe_enable_TXPCS_IDX_0); + +-- PCS Per Channel TX Control Register 4 for Channel 0 +dprioin_reserved_0_TB4 <= dprioin(reserved_0_TB4_TXPCS_IDX_11 DOWNTO reserved_0_TB4_TXPCS_IDX_0); +dprioin_rtxbitslip_en <= dprioin(rtxbitslip_en_TXPCS_IDX_0); +dprioin_rphfifo_regmode_tx <= dprioin(rphfifo_regmode_tx_TXPCS_IDX_0); +dprioin_rpipeline_bypass_tx <= dprioin(rpipeline_bypass_tx_TXPCS_IDX_0); +dprioin_rself_sw_en_tx <= dprioin(rself_sw_en_tx_TXPCS_IDX_0); + +-- --------------------------------------------------------------------------- +-- Set DPRIO output from initial CRAM +-- --------------------------------------------------------------------------- +-- Existing +dprioout(rauto_speed_ena_TX_IDX) <= init_rauto_speed_ena; +dprioout(rfreq_sel_TX_IDX) <= init_rfreq_sel; +dprioout(rhip_ena_TX_IDX) <= init_rhip_ena; +dprioout(rpma_doublewidth_tx_TX_IDX) <= init_rpma_doublewidth_tx; +dprioout(rpmadwidth_tx_TX_IDX) <= init_rpmadwidth_tx; +dprioout(rtx_cmu_sel_TX_IDX) <= init_rtx_cmu_sel; + +-- PCS Per Channel TX Control Register 1 for Channel 0 +dprioout(rforce_disp_TXPCS_IDX_0) <= init_rforce_disp; +dprioout(rrev_loopbk_TXPCS_IDX_0) <= init_rrev_loopbk; +dprioout(rtxrdclksel_TXPCS_IDX_0) <= init_rtxrdclksel; +dprioout(rtxwrclksel_TXPCS_IDX_0) <= init_rtxwrclksel; +dprioout(rfreerun_tx_TXPCS_IDX_0) <= init_rfreerun_tx; +dprioout(rtxurstpcs_TXPCS_IDX_0) <= init_rtxurstpcs; +dprioout(reserved_0_TB1_TXPCS_IDX_0) <= init_reserved_0_TB1; +dprioout(rphfifoursttx_TXPCS_IDX_0) <= init_rphfifoursttx; +dprioout(rphfifopldentx_TXPCS_IDX_0) <= init_rphfifopldentx; +dprioout(rge_xaui_tx_TXPCS_IDX_0) <= init_rge_xaui_tx; +dprioout(rdwidth_tx_TXPCS_IDX_0) <= init_rdwidth_tx; +dprioout(rtxfifo_lowlatency_en_TXPCS_IDX_0) <= init_rtxfifo_lowlatency_en; +dprioout(rib_force_disp_TXPCS_IDX_0) <= init_rib_force_disp; +dprioout(rtxfifo_dis_TXPCS_IDX_0) <= init_rtxfifo_dis; +dprioout(rforce_echar_TXPCS_IDX_0) <= init_rforce_echar; +dprioout(rforce_kchar_TXPCS_IDX_0) <= init_rforce_kchar; + +-- PCS Per Channel TX Control Register 2 for Channel 0 +dprioout(rtxpcsbypass_en_TXPCS_IDX_0) <= init_rtxpcsbypass_en; +dprioout(rcxpat_chnl_en_TXPCS_IDX_1 DOWNTO rcxpat_chnl_en_TXPCS_IDX_0) <= init_rcxpat_chnl_en; +dprioout(rbist_sel_TXPCS_IDX_1 DOWNTO rbist_sel_TXPCS_IDX_0) <= init_rbist_sel; +dprioout(rbisten_tx_TXPCS_IDX_0) <= init_rbisten_tx; +dprioout(rprbs_sel_TXPCS_IDX_2 DOWNTO rprbs_sel_TXPCS_IDX_0) <= init_rprbs_sel; +dprioout(rprbsen_tx_TXPCS_IDX_0) <= init_rprbsen_tx; +dprioout(renbitrev_tx_TXPCS_IDX_0) <= init_renbitrev_tx; +dprioout(renpolinv_tx_TXPCS_IDX_0) <= init_renpolinv_tx; +dprioout(rensymswap_tx_TXPCS_IDX_0) <= init_rensymswap_tx; +dprioout(rcascaded_8b10b_en_tx_TXPCS_IDX_0) <= init_rcascaded_8b10b_en_tx; +dprioout(r8b10b_enc_ibm_en_TXPCS_IDX_0) <= init_r8b10b_enc_ibm_en; +dprioout(rendec_tx_TXPCS_IDX_0) <= init_rendec_tx; + +-- PCS Per Channel TX Control Register 3 for Channel 0 +dprioout(reserved_0_TB3_TXPCS_IDX_0) <= init_reserved_0_TB3; +dprioout(rcid_len_tx_TXPCS_IDX_7 DOWNTO rcid_len_tx_TXPCS_IDX_0) <= init_rcid_len_tx; +dprioout(rcid_pattern_tx_TXPCS_IDX_0) <= init_rcid_pattern_tx; +dprioout(rtxpcsclkpwdn_TXPCS_IDX_0) <= init_rtxpcsclkpwdn; +dprioout(rtxswing_sel_ena_TXPCS_IDX_0) <= init_rtxswing_sel_ena; +dprioout(rtx_elec_idle_delay_TXPCS_IDX_2 DOWNTO rtx_elec_idle_delay_TXPCS_IDX_0) <= init_rtx_elec_idle_delay; +dprioout(rtx_pipe_enable_TXPCS_IDX_0) <= init_rtx_pipe_enable; + +-- PCS Per Channel TX Control Register 4 for Channel 0 +dprioout(reserved_0_TB4_TXPCS_IDX_11 DOWNTO reserved_0_TB4_TXPCS_IDX_0) <= init_reserved_0_TB4; +dprioout(rtxbitslip_en_TXPCS_IDX_0) <= init_rtxbitslip_en; +dprioout(rphfifo_regmode_tx_TXPCS_IDX_0) <= init_rphfifo_regmode_tx; +dprioout(rpipeline_bypass_tx_TXPCS_IDX_0) <= init_rpipeline_bypass_tx; +dprioout(rself_sw_en_tx_TXPCS_IDX_0) <= init_rself_sw_en_tx; + +-- --------------------------------------------------------------------------- +-- Set DPRIO CRAM +-- --------------------------------------------------------------------------- +dpriodisable_in <= '0' WHEN (dpriodisable = '0') ELSE '1'; + +-- Existing +cram_is_lane0 <= init_is_lane0 WHEN (dpriodisable_in /= '0') ELSE dprioin_is_lane0; +cram_rauto_speed_ena <= init_rauto_speed_ena WHEN (dpriodisable_in /= '0') ELSE dprioin_rauto_speed_ena; +cram_rclkcmpinsertpad <= init_rclkcmpinsertpad WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpinsertpad; -- rx only +cram_rendec_data_sel_tx <= init_rendec_data_sel_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rendec_data_sel_tx; +cram_rfreq_sel <= init_rfreq_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rfreq_sel; +cram_rhip_ena <= init_rhip_ena WHEN (dpriodisable_in /= '0') ELSE dprioin_rhip_ena; +cram_rindv_tx <= init_rindv_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rindv_tx; +cram_rmaster_tx <= init_rmaster_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rmaster_tx; +cram_rmaster_up_tx <= init_rmaster_up_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rmaster_up_tx; +cram_rphfifo_master_sel_tx <= init_rphfifo_master_sel_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifo_master_sel_tx; +cram_rpma_doublewidth_tx <= init_rpma_doublewidth_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rpma_doublewidth_tx; +cram_rpmadwidth_tx <= init_rpmadwidth_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rpmadwidth_tx; +cram_rrdwidth_rx <= init_rrdwidth_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rrdwidth_rx; -- rx only +cram_rrx_detect_bypass <= init_rrx_detect_bypass WHEN (dpriodisable_in /= '0') ELSE dprioin_rrx_detect_bypass; -- rx only +cram_rrx_pipe_enable <= init_rrx_pipe_enable WHEN (dpriodisable_in /= '0') ELSE dprioin_rrx_pipe_enable; -- rx only +cram_rtx_cmu_sel <= init_rtx_cmu_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rtx_cmu_sel; +cram_scan_mode <= init_scan_mode WHEN (dpriodisable_in /= '0') ELSE dprioin_scan_mode; + +-- PCS Per Channel TX Control Register 1 for Channel 0 +cram_rforce_disp <= init_rforce_disp WHEN (dpriodisable_in /= '0') ELSE dprioin_rforce_disp; +cram_rrev_loopbk <= init_rrev_loopbk WHEN (dpriodisable_in /= '0') ELSE dprioin_rrev_loopbk; +cram_rtxrdclksel <= init_rtxrdclksel WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxrdclksel; +cram_rtxwrclksel <= init_rtxwrclksel WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxwrclksel; +cram_rfreerun_tx <= init_rfreerun_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rfreerun_tx; +cram_rtxurstpcs <= init_rtxurstpcs WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxurstpcs; +cram_reserved_0_TB1 <= init_reserved_0_TB1 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB1; +cram_rphfifoursttx <= init_rphfifoursttx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifoursttx; +cram_rphfifopldentx <= init_rphfifopldentx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifopldentx; +cram_rge_xaui_tx <= init_rge_xaui_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rge_xaui_tx; +cram_rdwidth_tx <= init_rdwidth_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rdwidth_tx; +cram_rtxfifo_lowlatency_en <= init_rtxfifo_lowlatency_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxfifo_lowlatency_en; +cram_rib_force_disp <= init_rib_force_disp WHEN (dpriodisable_in /= '0') ELSE dprioin_rib_force_disp; +cram_rtxfifo_dis <= init_rtxfifo_dis WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxfifo_dis; +cram_rforce_echar <= init_rforce_echar WHEN (dpriodisable_in /= '0') ELSE dprioin_rforce_echar; +cram_rforce_kchar <= init_rforce_kchar WHEN (dpriodisable_in /= '0') ELSE dprioin_rforce_kchar; + +-- PCS Per Channel TX Control Register 2 for Channel 0 +cram_rtxpcsbypass_en <= init_rtxpcsbypass_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxpcsbypass_en; +cram_rcxpat_chnl_en <= init_rcxpat_chnl_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rcxpat_chnl_en; +cram_rbist_sel <= init_rbist_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rbist_sel; +cram_rbisten_tx <= init_rbisten_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rbisten_tx; +cram_rprbs_sel <= init_rprbs_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rprbs_sel; +cram_rprbsen_tx <= init_rprbsen_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rprbsen_tx; +cram_renbitrev_tx <= init_renbitrev_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_renbitrev_tx; +cram_renpolinv_tx <= init_renpolinv_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_renpolinv_tx; +cram_rensymswap_tx <= init_rensymswap_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rensymswap_tx; +cram_rcascaded_8b10b_en_tx <= init_rcascaded_8b10b_en_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rcascaded_8b10b_en_tx; +cram_r8b10b_enc_ibm_en <= init_r8b10b_enc_ibm_en WHEN (dpriodisable_in /= '0') ELSE dprioin_r8b10b_enc_ibm_en; +cram_rendec_tx <= init_rendec_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rendec_tx; + +-- PCS Per Channel TX Control Register 3 for Channel 0 +cram_reserved_0_TB3 <= init_reserved_0_TB3 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB3; +cram_rcid_len_tx <= init_rcid_len_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rcid_len_tx; +cram_rcid_pattern_tx <= init_rcid_pattern_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rcid_pattern_tx; +cram_rtxpcsclkpwdn <= init_rtxpcsclkpwdn WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxpcsclkpwdn; +cram_rtxswing_sel_ena <= init_rtxswing_sel_ena WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxswing_sel_ena; +cram_rtx_elec_idle_delay <= init_rtx_elec_idle_delay WHEN (dpriodisable_in /= '0') ELSE dprioin_rtx_elec_idle_delay; +cram_rtx_pipe_enable <= init_rtx_pipe_enable WHEN (dpriodisable_in /= '0') ELSE dprioin_rtx_pipe_enable; + +-- PCS Per Channel TX Control Register 4 for Channel 0 +cram_reserved_0_TB4 <= init_reserved_0_TB4 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB4; +cram_rtxbitslip_en <= init_rtxbitslip_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rtxbitslip_en; +cram_rphfifo_regmode_tx <= init_rphfifo_regmode_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifo_regmode_tx; +cram_rpipeline_bypass_tx <= init_rpipeline_bypass_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rpipeline_bypass_tx; +cram_rself_sw_en_tx <= init_rself_sw_en_tx WHEN (dpriodisable_in /= '0') ELSE dprioin_rself_sw_en_tx; +-- new DPRIO model end -- + + --////////////////////////////////////////////////////////////////////////////////////////////////// + -- datain TXD mapping - datain[32/40], ctrlenable[4], forcedispacompliance, forcedisp[4], dispval[4] + --////////////////////////////////////////////////////////////////////////////////////////////////// + + tmp_ctrlenable(0) <= '1' WHEN (ctrlenable_ipd(0) = '1') ELSE + '0'; + tmp_ctrlenable(1) <= '1' WHEN (ctrlenable_ipd(1) = '1') ELSE + '0'; + tmp_ctrlenable(2) <= '1' WHEN (ctrlenable_ipd(2) = '1') ELSE + '0'; + tmp_ctrlenable(3) <= '1' WHEN (ctrlenable_ipd(3) = '1') ELSE + '0'; + + tmp_dispval(0) <= '1' WHEN (dispval_ipd(0) = '1') ELSE + '0'; + tmp_dispval(1) <= '1' WHEN (dispval_ipd(1) = '1') ELSE + '0'; + tmp_dispval(2) <= '1' WHEN (dispval_ipd(2) = '1') ELSE + '0'; + tmp_dispval(3) <= '1' WHEN (dispval_ipd(3) = '1') ELSE + '0'; + + tmp_forcedisp(0) <= '1' WHEN (forcedisp_ipd(0) = '1') ELSE + '0'; + tmp_forcedisp(1) <= '1' WHEN (forcedisp_ipd(1) = '1') ELSE + '0'; + tmp_forcedisp(2) <= '1' WHEN (forcedisp_ipd(2) = '1') ELSE + '0'; + tmp_forcedisp(3) <= '1' WHEN (forcedisp_ipd(3) = '1') ELSE + '0'; + + tmp_datain(0) <= '1' WHEN (datain_ipd(0) = '1') ELSE + '0'; + tmp_datain(1) <= '1' WHEN (datain_ipd(1) = '1') ELSE + '0'; + tmp_datain(2) <= '1' WHEN (datain_ipd(2) = '1') ELSE + '0'; + tmp_datain(3) <= '1' WHEN (datain_ipd(3) = '1') ELSE + '0'; + tmp_datain(4) <= '1' WHEN (datain_ipd(4) = '1') ELSE + '0'; + tmp_datain(5) <= '1' WHEN (datain_ipd(5) = '1') ELSE + '0'; + tmp_datain(6) <= '1' WHEN (datain_ipd(6) = '1') ELSE + '0'; + tmp_datain(7) <= '1' WHEN (datain_ipd(7) = '1') ELSE + '0'; + tmp_datain(8) <= '1' WHEN (datain_ipd(8) = '1') ELSE + '0'; + tmp_datain(9) <= '1' WHEN (datain_ipd(9) = '1') ELSE + '0'; + tmp_datain(10) <= '1' WHEN (datain_ipd(10) = '1') ELSE + '0'; + tmp_datain(11) <= '1' WHEN (datain_ipd(11) = '1') ELSE + '0'; + tmp_datain(12) <= '1' WHEN (datain_ipd(12) = '1') ELSE + '0'; + tmp_datain(13) <= '1' WHEN (datain_ipd(13) = '1') ELSE + '0'; + tmp_datain(14) <= '1' WHEN (datain_ipd(14) = '1') ELSE + '0'; + tmp_datain(15) <= '1' WHEN (datain_ipd(15) = '1') ELSE + '0'; + tmp_datain(16) <= '1' WHEN (datain_ipd(16) = '1') ELSE + '0'; + tmp_datain(17) <= '1' WHEN (datain_ipd(17) = '1') ELSE + '0'; + tmp_datain(18) <= '1' WHEN (datain_ipd(18) = '1') ELSE + '0'; + tmp_datain(19) <= '1' WHEN (datain_ipd(19) = '1') ELSE + '0'; + tmp_datain(20) <= '1' WHEN (datain_ipd(20) = '1') ELSE + '0'; + tmp_datain(21) <= '1' WHEN (datain_ipd(21) = '1') ELSE + '0'; + tmp_datain(22) <= '1' WHEN (datain_ipd(22) = '1') ELSE + '0'; + tmp_datain(23) <= '1' WHEN (datain_ipd(23) = '1') ELSE + '0'; + tmp_datain(24) <= '1' WHEN (datain_ipd(24) = '1') ELSE + '0'; + tmp_datain(25) <= '1' WHEN (datain_ipd(25) = '1') ELSE + '0'; + tmp_datain(26) <= '1' WHEN (datain_ipd(26) = '1') ELSE + '0'; + tmp_datain(27) <= '1' WHEN (datain_ipd(27) = '1') ELSE + '0'; + tmp_datain(28) <= '1' WHEN (datain_ipd(28) = '1') ELSE + '0'; + tmp_datain(29) <= '1' WHEN (datain_ipd(29) = '1') ELSE + '0'; + tmp_datain(30) <= '1' WHEN (datain_ipd(30) = '1') ELSE + '0'; + tmp_datain(31) <= '1' WHEN (datain_ipd(31) = '1') ELSE + '0'; + tmp_datain(32) <= '1' WHEN (datain_ipd(32) = '1') ELSE + '0'; + tmp_datain(33) <= '1' WHEN (datain_ipd(33) = '1') ELSE + '0'; + tmp_datain(34) <= '1' WHEN (datain_ipd(34) = '1') ELSE + '0'; + tmp_datain(35) <= '1' WHEN (datain_ipd(35) = '1') ELSE + '0'; + tmp_datain(36) <= '1' WHEN (datain_ipd(36) = '1') ELSE + '0'; + tmp_datain(37) <= '1' WHEN (datain_ipd(37) = '1') ELSE + '0'; + tmp_datain(38) <= '1' WHEN (datain_ipd(38) = '1') ELSE + '0'; + tmp_datain(39) <= '1' WHEN (datain_ipd(39) = '1') ELSE + '0'; + + pi_in_txd_ch_tmp(7 DOWNTO 0) <= tmp_datain(7 DOWNTO 0); + pi_in_txd_ch_tmp(8) <= tmp_ctrlenable(0) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(8) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(9) <= tmp_forcedisp(0) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(9) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(10) <= tmp_dispval(0) WHEN (cram_rendec_tx = '1') ELSE + 'X'; + + pi_in_txd_ch_tmp(18 DOWNTO 11) <= tmp_datain(15 DOWNTO 8) WHEN (cram_rendec_tx = '1' OR cram_rpmadwidth_tx = '0') ELSE + tmp_datain(17 DOWNTO 10); + pi_in_txd_ch_tmp(19) <= tmp_ctrlenable(1) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(18) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(20) <= tmp_forcedisp(1) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(19) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(21) <= tmp_dispval(1) WHEN (cram_rendec_tx = '1') ELSE + 'X'; + + pi_in_txd_ch_tmp(29 DOWNTO 22) <= tmp_datain(23 DOWNTO 16) WHEN (cram_rendec_tx = '1' OR cram_rpmadwidth_tx = '0') ELSE + tmp_datain(27 DOWNTO 20); + pi_in_txd_ch_tmp(30) <= tmp_ctrlenable(2) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(28) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(31) <= tmp_forcedisp(2) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(29) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(32) <= tmp_dispval(2) WHEN (cram_rendec_tx = '1') ELSE + 'X'; + + pi_in_txd_ch_tmp(40 DOWNTO 33) <= tmp_datain(31 DOWNTO 24) WHEN (cram_rendec_tx = '1' OR cram_rpmadwidth_tx = '0') ELSE + tmp_datain(37 DOWNTO 30); + pi_in_txd_ch_tmp(41) <= tmp_ctrlenable(3) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(38) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(42) <= tmp_forcedisp(3) WHEN (cram_rendec_tx = '1') ELSE + tmp_datain(39) WHEN (cram_rpmadwidth_tx = '1') ELSE + 'X'; + pi_in_txd_ch_tmp(43) <= tmp_dispval(3) WHEN (cram_rendec_tx = '1') ELSE + 'X'; + + --interleaving + pi_in_txd_ch(10 DOWNTO 0) <= pi_in_txd_ch_tmp(10 DOWNTO 0); + pi_in_txd_ch(32 DOWNTO 22) <= pi_in_txd_ch_tmp(21 DOWNTO 11) WHEN (cram_rdwidth_tx = '1' AND cram_rpma_doublewidth_tx = '0') ELSE + pi_in_txd_ch_tmp(32 DOWNTO 22); + pi_in_txd_ch(21 DOWNTO 11) <= pi_in_txd_ch_tmp(32 DOWNTO 22) WHEN (cram_rdwidth_tx = '1' AND cram_rpma_doublewidth_tx = '0') ELSE + pi_in_txd_ch_tmp(21 DOWNTO 11); + pi_in_txd_ch(43 DOWNTO 33) <= pi_in_txd_ch_tmp(43 DOWNTO 33); + + pi_in_txd_ch_dprio <= datainfull_siv WHEN ((dprio_config_mode AND DPRIO_CHANNEL_INTERFACE_BIT) = "000100") ELSE pi_in_txd_ch; + + --/////////////////////////////////////////////////////////////////////////////// + -- Connect Atom level output to appropriate RTL - PORT_OUT_Table ------------ // + --/////////////////////////////////////////////////////////////////////////////// + + clkout <= td_out_tx_clk_out; + dataout <= td_out_pudr(9 DOWNTO 0); -- cycloneiv_width modify + parallelfdbkout <= td_out_txlp20b; + phfifooverflow <= td_out_full_tx; + phfifounderflow <= td_out_empty_tx; + + pipepowerdownout <= td_out_powerdown_int; -- powerdn_ipd; + pipepowerstateout <= pi_out_powerstate(3 DOWNTO 0); + rdenablesync <= td_out_rd_enable_sync; + txdetectrx <= pi_out_txdetectrx; -- NEW + xgmctrlenable <= td_out_tx_ctl_tc; + xgmdataout <= td_out_tx_data_tc; + + coreclkout <= coreclk_ipd; + hiptxclkout <= hs_out_hip_tx_clk; + iqpphfifobyteselout <= td_out_fifo_select_out_pipe; + iqpphfifordclkout <= td_out_tx_div2_sync_out_pipe; + iqpphfifordenableout <= td_out_rd_enable_out_pipe; + iqpphfifowrenableout <= td_out_wr_enable_out_pipe; + phfiforddisableout <= phfiforddisable; + phfiforesetout <= phfiforeset; + phfifowrenableout <= phfifowrenable; + + grayelecidleinferselout <= td_out_gray_eidleinfersel; + pipeenrevparallellpbkout <= pi_out_rev_loopbk; + + -- q90 ww47 fix --------------------------------------------------------------- + forceelecidleout <= pi_out_tx_elec_idle; + + --/////////////////////////////////////////////////////////////////////////////// + -- tx sub-block instantiation: pcs_reset --------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + pr_in_hard_reset <= '1' WHEN (quadreset = '1') ELSE -- from top + '0'; + pr_in_clk_2_b <= '0'; -- for rx side + pr_in_refclk_b_in <= td_out_refclk_b; + pr_in_scan_mode <= '0'; + pr_in_rxpcs_rst <= '0'; -- for rx side + pr_in_txpcs_rst <= '1' WHEN (digitalreset = '1') ELSE -- from top + '0'; + + tx_pcs_reset_1 : cycloneiv_hssi_pcs_reset + PORT MAP ( + hard_reset => pr_in_hard_reset, + clk_2_b => pr_in_clk_2_b, + refclk_b_in => pr_in_refclk_b_in, + scan_mode => pr_in_scan_mode, + rxpcs_rst => pr_in_rxpcs_rst, + txpcs_rst => pr_in_txpcs_rst, + rxrst_int => rxrst_int_wire, + txrst_int => pr_out_txrst_int + ); + + --/////////////////////////////////////////////////////////////////////////////// + -- tx sub-block instantiation: chnl_hip_support -------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + hs_in_eidleinfersel_ch <= elecidleinfersel_in; + hs_in_hip_eidleinfersel_ch <= hipelecidleinfersel_in; + hs_in_hip_powerdown_ch <= hippowerdn_in; + hs_in_hip_rate <= 'X'; + hs_in_hip_rxpolarity <= 'X'; + hs_in_hip_txd_ch <= hipdatain_in; + hs_in_hip_txdeemph <= hiptxdeemph_in; + hs_in_hip_txdetectrxloopback <= hipdetectrxloop_in; + hs_in_hip_txelecidle <= hipforceelecidle_in; + hs_in_hip_txmargin_ch <= hiptxmargin_in; + hs_in_pcs_phystatus <= 'X'; + hs_in_pcs_rxd_ch <= "XXXXXXXXX"; + hs_in_pcs_rxelecidle <= 'X'; + hs_in_pcs_rxstatus_ch <= "00X"; + hs_in_pcs_rxvalid <= 'X'; + hs_in_powerdown_ch <= powerdn_ipd; + hs_in_rate <= 'X'; + hs_in_rhip_ena <= cram_rhip_ena; + hs_in_rxpolarity <= 'X'; + hs_in_txd_ch <= pi_in_txd_ch_dprio(10 DOWNTO 0); + hs_in_txdeemph <= pipetxdeemph_ipd; + hs_in_txdetectrxloopback <= detectrxloop_ipd; + hs_in_txmargin_ch <= pipetxmargin_ipd; + hs_in_txpma_local_clk <= localrefclk; + + mtx_hs : cycloneiv_hssi_digi_chnl_hip_spt + PORT MAP ( + + eidleinfersel_ch => hs_in_eidleinfersel_ch, + hip_eidleinfersel_ch => hs_in_hip_eidleinfersel_ch, + hip_powerdown_ch => hs_in_hip_powerdown_ch, + hip_rate => hs_in_hip_rate, + hip_rxpolarity => hs_in_hip_rxpolarity, + hip_txd_ch => hs_in_hip_txd_ch, + hip_txdeemph => hs_in_hip_txdeemph, + hip_txdetectrxloopback => hs_in_hip_txdetectrxloopback, + hip_txelecidle => hs_in_hip_txelecidle, + hip_txmargin_ch => hs_in_hip_txmargin_ch, + pcs_phystatus => hs_in_pcs_phystatus, + pcs_rxd_ch => hs_in_pcs_rxd_ch, + pcs_rxelecidle => hs_in_pcs_rxelecidle, + pcs_rxstatus_ch => hs_in_pcs_rxstatus_ch, + pcs_rxvalid => hs_in_pcs_rxvalid, + powerdown_ch => hs_in_powerdown_ch, + rate => hs_in_rate, + rhip_ena => hs_in_rhip_ena, + rxpolarity => hs_in_rxpolarity, + txd_ch => hs_in_txd_ch, + txdeemph => hs_in_txdeemph, + txdetectrxloopback => hs_in_txdetectrxloopback, + txmargin_ch => hs_in_txmargin_ch, + txpma_local_clk => hs_in_txpma_local_clk, + + hip_phystatus => hs_out_hip_phystatus, + hip_rxd_ch => hs_out_hip_rxd_ch, + hip_rxelecidle => hs_out_hip_rxelecidle, + hip_rxstatus_ch => hs_out_hip_rxstatus_ch, + hip_rxvalid => hs_out_hip_rxvalid, + hip_tx_clk => hs_out_hip_tx_clk, + pcs_eidleinfersel_ch => hs_out_pcs_eidleinfersel_ch, + pcs_powerdown_ch => hs_out_pcs_powerdown_ch, + pcs_rate => hs_out_pcs_rate, + pcs_rxpolarity => hs_out_pcs_rxpolarity, + pcs_txd_ch => hs_out_pcs_txd_ch, + pcs_txdeemph => hs_out_pcs_txdeemph, + pcs_txdetectrxloopback => hs_out_pcs_txdetectrxloopback, + pcs_txmargin_ch => hs_out_pcs_txmargin_ch, + phystatus => hs_out_phystatus, + rxd_ch => hs_out_rxd_ch, + rxelecidle => hs_out_rxelecidle, + rxstatus_ch => hs_out_rxstatus_ch, + rxvalid => hs_out_rxvalid + ); + + --/////////////////////////////////////////////////////////////////////////////// + -- tx sub-block instantiation: pipe_interface ---------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + pi_in_pipe_tx_clk <= '0' WHEN (cram_rtx_pipe_enable = '0') ELSE + td_out_tx_pipe_clk; + pi_in_powerdown <= td_out_powerdown_int; -- powerdn_ipd; + pi_in_refclk_b <= '0' WHEN (cram_rtx_pipe_enable = '0') ELSE + td_out_refclk_b; + pi_in_refclk_b_reset_n <= NOT(pr_out_txrst_int); + pi_in_revloopback <= td_out_revloopback_int; -- (enrevparallellpbk_ipd === 1'b1) ? 1'b1 : 1'b0; + pi_in_tx_elec_idle_comp <= td_out_tx_pipe_electidle; + pi_in_tx_pipe_reset_n <= NOT(td_out_tx_pipe_soft_reset); + pi_in_txdetectrxloopback <= td_out_txdetectrxloopback_int; -- (detectrxloop_ipd === 1'b1) ? 1'b1 : 1'b0; + pi_in_txelecidle <= forceelecidle_ipd; + pi_in_state_transition_done <= pipestatetransdone; + + -- new interfaces in CYCLONEIV + pi_in_txdeemph <= td_out_phfifo_txdeemph; + pi_in_txmargin <= td_out_phfifo_txmargin; + pi_in_txswing <= td_out_phfifo_txswing; + + tx_pipe_interface_inst : cycloneiv_hssi_tx_pipe_interface + PORT MAP ( + clk => pi_in_pipe_tx_clk, + refclk_b => pi_in_refclk_b, + refclk_b_reset_n => pi_in_refclk_b_reset_n, + reset_n => pi_in_tx_pipe_reset_n, + rtx_pipe_enable => cram_rtx_pipe_enable, + rtx_elec_idle_delay => cram_rtx_elec_idle_delay, + txdetectrxloopback => pi_in_txdetectrxloopback, + txelecidle => pi_in_txelecidle, + powerdown => pi_in_powerdown, + txd_ch => pi_in_txd_ch_dprio, + revloopback => pi_in_revloopback, + txd => pi_out_txd, + rev_loopbk => pi_out_rev_loopbk, + tx_elec_idle_comp => pi_in_tx_elec_idle_comp, + tx_elec_idle => pi_out_tx_elec_idle, + txdetectrx => pi_out_txdetectrx, + powerstate => pi_out_powerstate, + + -- new interfaces in CYCLONEIV - ww26.5 + rtxswing_sel_ena => cram_rtxswing_sel_ena, + txdeemph => pi_in_txdeemph, + txmargin => pi_in_txmargin, + txswing => pi_in_txswing, + txdeemph_int => pi_out_txdeemph_int, + txmargin_int => pi_out_txmargin_int, + txswing_int => pi_out_txswing_int + ); + + --/////////////////////////////////////////////////////////////////////////////// + -- tx sub-block instantiation: tx_digi ----------------------------------------// + --/////////////////////////////////////////////////////////////////////////////// + + td_in_phfifourst_tx <= '1' WHEN (phfiforeset = '1') ELSE + '0'; + td_in_pld_tx_clk <= coreclk; -- coreclk_ipd; + td_in_polinv_tx <= '1' WHEN (invpol_ipd = '1') ELSE + '0'; + td_in_rddisable_tx <= '1' WHEN (phfiforddisable = '1') ELSE -- enable by default + '0'; + td_in_refclk_pma <= refclk_ipd; + td_in_rev_loop_data <= revparallelfdbk; + td_in_rev_loopbk <= pi_out_rev_loopbk; + td_in_tx_data_ts <= xgmdatain; + td_in_tx_ctl_ts <= xgmctrl; + td_in_txd <= (pi_in_txd_ch_dprio(43 DOWNTO 11) & hs_out_pcs_txd_ch); --pi_in_txd_ch_dprio; // pi_out_txd - 44 bit + td_in_txpcs_rst <= pr_out_txrst_int; + td_in_txpma_local_clk <= localrefclk; + td_in_wrenable_tx <= '0' WHEN (phfifowrenable_ipd = '0') ELSE -- enable by default + '1'; + + td_in_gen2ngen1 <= '1' WHEN (rateswitchisdone = '1') ELSE --from tx_pma local clk divider + '0'; + td_in_gen2ngen1_bundle <= '1' WHEN (rateswitchxndone = '1') ELSE --from central clk divider + '0'; + td_in_polinv_rx <= '0'; -- leaving it out of tx as it is a simple wire in tx_ctrl + td_in_powerdown <= hs_out_pcs_powerdown_ch; -- powerdn_ipd; + td_in_revloopback <= '1' WHEN (enrevparallellpbk_ipd = '1') ELSE + '0'; + td_in_rxpolarity <= '0'; --// leaving it out of tx as it is a simple wire in tx_ctrl + td_in_txdetectrxloopback <= hs_out_pcs_txdetectrxloopback; -- (detectrxloop_ipd === 1'b1) ? 1'b1 : 1'b0; + + td_in_prbs_cid_en <= prbscidenable_in; + td_in_tx_boundary_sel <= bitslipboundaryselect_ipd; + + -- new signal inputs for bundling + -- temporary disabled by forcing rindv_tx = 1'b0 todo + -- SPR 311609 + td_in_tx_div2_sync_in_centrl <= phfifox4rdclk_in; + td_in_tx_div2_sync_in_quad_up <= phfifox4rdclk_in; + td_in_tx_div2_sync_in_quad_down <= phfifox4rdclk_in; + td_in_wr_enable_in_centrl <= phfifox4wrenable_in; + td_in_wr_enable_in_quad_up <= phfifox4wrenable_in; + td_in_wr_enable_in_quad_down <= phfifox4wrenable_in; + td_in_rd_enable_in_centrl <= phfifox4rdenable_in; + td_in_rd_enable_in_quad_up <= phfifox4rdenable_in; + td_in_rd_enable_in_quad_down <= phfifox4rdenable_in; + td_in_fifo_select_in_centrl <= phfifox4bytesel_in; + td_in_fifo_select_in_quad_up <= phfifox4bytesel_in; + td_in_fifo_select_in_quad_down <= phfifox4bytesel_in; + td_in_reset_pc_ptrs <= phfifoptrsreset_in; -- from rx + td_in_reset_pc_ptrs_in_centrl <= phfifoxnptrsreset_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + td_in_reset_pc_ptrs_in_quad_up <= phfifoxnptrsreset_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + td_in_reset_pc_ptrs_in_quad_down <= phfifoxnptrsreset_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + + td_in_tx_div2_sync_in_pipe_quad_up <= iqpphfifoxnrdclk_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + td_in_tx_div2_sync_in_pipe_quad_down <= iqpphfifoxnrdclk_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + td_in_wr_enable_in_pipe_quad_up <= iqpphfifoxnwrenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + td_in_wr_enable_in_pipe_quad_down <= iqpphfifoxnwrenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + td_in_rd_enable_in_pipe_quad_up <= iqpphfifoxnrdenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + td_in_rd_enable_in_pipe_quad_down <= iqpphfifoxnrdenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + td_in_fifo_select_in_pipe_quad_up <= iqpphfifoxnbytesel_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + td_in_fifo_select_in_pipe_quad_down <= iqpphfifoxnbytesel_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + + td_in_dis_pc_byte <= phfifobyteserdisable_in; -- from rx + + -- push through TX Phase Comp FIFO + td_in_txswing <= pipetxswing_ipd; --ww12_new conne + td_in_pcs_txdeemph <= hs_out_pcs_txdeemph; --ww12_new conne + td_in_pcs_txmargin <= hs_out_pcs_txmargin_ch; --ww12_new conne + + -- RX PIPE interface signals + td_in_eidleinfersel <= hs_out_pcs_eidleinfersel_ch; + + td_out_tx_div2_sync_out_pipe <= td_out_tx_div2_sync_out_pipe_up WHEN (cram_rmaster_up_tx = '0') ELSE + td_out_tx_div2_sync_out_pipe_down; + td_out_fifo_select_out_pipe <= td_out_fifo_select_out_pipe_up WHEN (cram_rmaster_up_tx = '0') ELSE + td_out_fifo_select_out_pipe_down; + td_out_wr_enable_out_pipe <= td_out_wr_enable_out_pipe_up WHEN (cram_rmaster_up_tx = '0') ELSE + td_out_wr_enable_out_pipe_down; + td_out_rd_enable_out_pipe <= td_out_rd_enable_out_pipe_up WHEN (cram_rmaster_up_tx = '0') ELSE + td_out_rd_enable_out_pipe_down; + + digi_tx_1 : cycloneiv_hssi_tx_digi + PORT MAP ( + empty_tx => td_out_empty_tx, + encoder_testbus => td_out_encoder_testbus, + full_tx => td_out_full_tx, + phfifourst_tx => td_in_phfifourst_tx, + pld_tx_clk => td_in_pld_tx_clk, + polinv_tx => td_in_polinv_tx, + pudr => td_out_pudr, + r8b10b_enc_ibm_en => cram_r8b10b_enc_ibm_en, + rbist_sel => cram_rbist_sel, + rbisten_tx => cram_rbisten_tx, + rcascaded_8b10b_en_tx => cram_rcascaded_8b10b_en_tx, + rcxpat_chnl_en => cram_rcxpat_chnl_en, + rd_enable_sync => td_out_rd_enable_sync, + rddisable_tx => td_in_rddisable_tx, + rdwidth_tx => cram_rdwidth_tx, + refclk_b => td_out_refclk_b, + refclk_pma => td_in_refclk_pma, + renbitrev_tx => cram_renbitrev_tx, + rendec_data_sel_tx => cram_rendec_data_sel_tx, + rendec_tx => cram_rendec_tx, + renpolinv_tx => cram_renpolinv_tx, + rensymswap_tx => cram_rensymswap_tx, + rev_loop_data => td_in_rev_loop_data, + rev_loopbk => td_in_rev_loopbk, + rforce_disp => cram_rforce_disp, + rforce_echar => cram_rforce_echar, + rforce_kchar => cram_rforce_kchar, + rfreerun_tx => cram_rfreerun_tx, + rge_xaui_tx => cram_rge_xaui_tx, + rib_force_disp => cram_rib_force_disp, + rindv_tx => cram_rindv_tx, + rphfifopldentx => cram_rphfifopldentx, + rphfifoursttx => cram_rphfifoursttx, + rpma_doublewidth_tx => cram_rpma_doublewidth_tx, + rpmadwidth_tx => cram_rpmadwidth_tx, + rprbs_sel => cram_rprbs_sel, + rprbsen_tx => cram_rprbsen_tx, + rrev_loopbk => cram_rrev_loopbk, + rtx_pipe_enable => cram_rtx_pipe_enable, + rtxfifo_dis => cram_rtxfifo_dis, + rtxfifo_lowlatency_en => cram_rtxfifo_lowlatency_en, + rtxrdclksel => cram_rtxrdclksel, + rtxwrclksel => cram_rtxwrclksel, + scan_mode => cram_scan_mode, + tx_clk_out => td_out_tx_clk_out, + tx_ctl_tc => td_out_tx_ctl_tc, + tx_ctl_ts => td_in_tx_ctl_ts, + tx_ctrl_testbus => td_out_tx_ctrl_testbus, + tx_data_tc => td_out_tx_data_tc, + tx_data_ts => td_in_tx_data_ts, + tx_pipe_clk => td_out_tx_pipe_clk, + tx_pipe_electidle => td_out_tx_pipe_electidle, + tx_pipe_soft_reset => td_out_tx_pipe_soft_reset, + txd => td_in_txd, + txlp20b => td_out_txlp20b, + txpcs_rst => td_in_txpcs_rst, + txpma_local_clk => td_in_txpma_local_clk, + wrenable_tx => td_in_wrenable_tx, + + gen2ngen1 => td_in_gen2ngen1, + gen2ngen1_bundle => td_in_gen2ngen1_bundle, + polinv_rx => td_in_polinv_rx, + powerdown => td_in_powerdown, + revloopback => td_in_revloopback, + rxpolarity => td_in_rxpolarity, + txdetectrxloopback => td_in_txdetectrxloopback, + + rauto_speed_ena => cram_rauto_speed_ena, + rfreq_sel => cram_rfreq_sel, + rtxpcsbypass_en => cram_rtxpcsbypass_en, + rtxpcsclkpwdn => cram_rtxpcsclkpwdn, + + polinv_rx_int => td_out_polinv_rx_int, + powerdown_int => td_out_powerdown_int, + revloopback_int => td_out_revloopback_int, + rxpolarity_int => td_out_rxpolarity_int, + txdetectrxloopback_int => td_out_txdetectrxloopback_int, + + prbs_cid_en => td_in_prbs_cid_en, + tx_boundary_sel => td_in_tx_boundary_sel, + rcid_pattern_tx => cram_rcid_pattern_tx, + rcid_len_tx => cram_rcid_len_tx, + + tx_div2_sync_in_centrl => td_in_tx_div2_sync_in_centrl, + tx_div2_sync_in_quad_up => td_in_tx_div2_sync_in_quad_up, + tx_div2_sync_in_quad_down => td_in_tx_div2_sync_in_quad_down, + wr_enable_in_centrl => td_in_wr_enable_in_centrl, + wr_enable_in_quad_up => td_in_wr_enable_in_quad_up, + wr_enable_in_quad_down => td_in_wr_enable_in_quad_down, + rd_enable_in_centrl => td_in_rd_enable_in_centrl, + rd_enable_in_quad_up => td_in_rd_enable_in_quad_up, + rd_enable_in_quad_down => td_in_rd_enable_in_quad_down, + fifo_select_in_centrl => td_in_fifo_select_in_centrl, + fifo_select_in_quad_up => td_in_fifo_select_in_quad_up, + fifo_select_in_quad_down => td_in_fifo_select_in_quad_down, + reset_pc_ptrs => td_in_reset_pc_ptrs, + reset_pc_ptrs_in_centrl => td_in_reset_pc_ptrs_in_centrl, + reset_pc_ptrs_in_quad_up => td_in_reset_pc_ptrs_in_quad_up, + reset_pc_ptrs_in_quad_down => td_in_reset_pc_ptrs_in_quad_down, + tx_div2_sync_in_pipe_quad_up => td_in_tx_div2_sync_in_pipe_quad_up, + tx_div2_sync_in_pipe_quad_down => td_in_tx_div2_sync_in_pipe_quad_down, + wr_enable_in_pipe_quad_up => td_in_wr_enable_in_pipe_quad_up, + wr_enable_in_pipe_quad_down => td_in_wr_enable_in_pipe_quad_down, + rd_enable_in_pipe_quad_up => td_in_rd_enable_in_pipe_quad_up, + rd_enable_in_pipe_quad_down => td_in_rd_enable_in_pipe_quad_down, + fifo_select_in_pipe_quad_up => td_in_fifo_select_in_pipe_quad_up, + fifo_select_in_pipe_quad_down => td_in_fifo_select_in_pipe_quad_down, + + dis_pc_byte => td_in_dis_pc_byte, + + rmaster_tx => cram_rmaster_tx, + rmaster_up_tx => cram_rmaster_up_tx, + rself_sw_en_tx => cram_rself_sw_en_tx, + rpipeline_bypass_tx => cram_rpipeline_bypass_tx, + rphfifo_regmode_tx => cram_rphfifo_regmode_tx, + + tx_div2_sync_out_pipe_up => td_out_tx_div2_sync_out_pipe_up, + fifo_select_out_pipe_up => td_out_fifo_select_out_pipe_up, + wr_enable_out_pipe_up => td_out_wr_enable_out_pipe_up, + rd_enable_out_pipe_up => td_out_rd_enable_out_pipe_up, + tx_div2_sync_out_pipe_down => td_out_tx_div2_sync_out_pipe_down, + fifo_select_out_pipe_down => td_out_fifo_select_out_pipe_down, + wr_enable_out_pipe_down => td_out_wr_enable_out_pipe_down, + rd_enable_out_pipe_down => td_out_rd_enable_out_pipe_down, + + txswing => td_in_txswing, + pcs_txdeemph => td_in_pcs_txdeemph, + pcs_txmargin => td_in_pcs_txmargin, + eidleinfersel => td_in_eidleinfersel, + + phfifo_txswing => td_out_phfifo_txswing, + phfifo_txdeemph => td_out_phfifo_txdeemph, + phfifo_txmargin => td_out_phfifo_txmargin, + gray_eidleinfersel => td_out_gray_eidleinfersel, + + rtxbitslip_en => cram_rtxbitslip_en + ); + +END trans; + +-- stratixiigx_hssi_transmitter + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_digis_ram8x70_syn IS + GENERIC ( + + read_access_time : INTEGER := 0; + write_access_time : INTEGER := 0; + ram_width : INTEGER := 70 + ); + PORT ( + rst_l : IN STD_LOGIC; + clk : IN STD_LOGIC; + fifo_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR(69 DOWNTO 0); + fifo_re : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR(69 DOWNTO 0) + ); +END cycloneiv_hssi_rx_digis_ram8x70_syn; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_digis_ram8x70_syn IS + + SIGNAL data_out_i : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + + SIGNAL data_reg_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + + SIGNAL we : STD_LOGIC; + SIGNAL re_l : STD_LOGIC; +BEGIN + + we <= '1'; + re_l <= '0'; + + --assignment + data_reg_0 <= data_in WHEN (fifo_wr(0) = '1') ELSE + ram_array_q_0; + data_reg_1 <= data_in WHEN (fifo_wr(1) = '1') ELSE + ram_array_q_1; + data_reg_2 <= data_in WHEN (fifo_wr(2) = '1') ELSE + ram_array_q_2; + data_reg_3 <= data_in WHEN (fifo_wr(3) = '1') ELSE + ram_array_q_3; + data_reg_4 <= data_in WHEN (fifo_wr(4) = '1') ELSE + ram_array_q_4; + data_reg_5 <= data_in WHEN (fifo_wr(5) = '1') ELSE + ram_array_q_5; + data_reg_6 <= data_in WHEN (fifo_wr(6) = '1') ELSE + ram_array_q_6; + data_reg_7 <= data_in WHEN (fifo_wr(7) = '1') ELSE + ram_array_q_7; + + data_out <= "0000000000000000000000000000000000000000000000000000000000000000000000" WHEN (re_l = '1') ELSE + data_out_i; + + PROCESS (ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, fifo_re) +VARIABLE txt : LINE; + BEGIN + CASE fifo_re IS -- synopsys parallel_case full_case + WHEN "00000001" => + data_out_i <= ram_array_q_0; + WHEN "00000010" => + data_out_i <= ram_array_q_1; + WHEN "00000100" => + data_out_i <= ram_array_q_2; + WHEN "00001000" => + data_out_i <= ram_array_q_3; + WHEN "00010000" => + data_out_i <= ram_array_q_4; + WHEN "00100000" => + data_out_i <= ram_array_q_5; + WHEN "01000000" => + data_out_i <= ram_array_q_6; + WHEN "10000000" => + data_out_i <= ram_array_q_7; + WHEN OTHERS => + data_out_i <= ram_array_q_0; + END CASE; + END PROCESS; + + PROCESS (clk, rst_l) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rst_l)) = '1') THEN + ram_array_q_0 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_1 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_2 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_3 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_4 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_5 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_6 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_7 <= TRANSPORT "0000100000000000000000000000000000000000000000000000000000000000000000" AFTER (write_access_time)*1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + ram_array_q_0 <= TRANSPORT ram_array_d_0 AFTER (write_access_time)*1 ps; + ram_array_q_1 <= TRANSPORT ram_array_d_1 AFTER (write_access_time)*1 ps; + ram_array_q_2 <= TRANSPORT ram_array_d_2 AFTER (write_access_time)*1 ps; + ram_array_q_3 <= TRANSPORT ram_array_d_3 AFTER (write_access_time)*1 ps; + ram_array_q_4 <= TRANSPORT ram_array_d_4 AFTER (write_access_time)*1 ps; + ram_array_q_5 <= TRANSPORT ram_array_d_5 AFTER (write_access_time)*1 ps; + ram_array_q_6 <= TRANSPORT ram_array_d_6 AFTER (write_access_time)*1 ps; + ram_array_q_7 <= TRANSPORT ram_array_d_7 AFTER (write_access_time)*1 ps; + END IF; + END PROCESS; + + PROCESS (we, data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7) +VARIABLE txt : LINE; + BEGIN + IF (we = '1') THEN + ram_array_d_0 <= data_reg_0; + ram_array_d_1 <= data_reg_1; + ram_array_d_2 <= data_reg_2; + ram_array_d_3 <= data_reg_3; + ram_array_d_4 <= data_reg_4; + ram_array_d_5 <= data_reg_5; + ram_array_d_6 <= data_reg_6; + ram_array_d_7 <= data_reg_7; + ELSE + ram_array_d_0 <= ram_array_q_0; + ram_array_d_1 <= ram_array_q_1; + ram_array_d_2 <= ram_array_q_2; + ram_array_d_3 <= ram_array_q_3; + ram_array_d_4 <= ram_array_q_4; + ram_array_d_5 <= ram_array_q_5; + ram_array_d_6 <= ram_array_q_6; + ram_array_d_7 <= ram_array_q_7; + END IF; + END PROCESS; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_digis_ph_fifo IS + PORT ( + -- inputs + -- outputs + + -- ======= + -- inputs + -- ======= + rst_wclk : IN STD_LOGIC; + rst_rclk : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; -- Write Clock + rd_clk : IN STD_LOGIC; -- Read Clock + en : IN STD_LOGIC; -- Disable FIFO or bypass - only for Altera internal debug + lowlatency_en : IN STD_LOGIC; -- low latency enable + we : IN STD_LOGIC; -- PLD dynamic write pointer enable + re : IN STD_LOGIC; -- PLD dynamic read pointer enable + din : IN STD_LOGIC_VECTOR(69 DOWNTO 0); -- 10-bit code-group bus from deskew module. + + rphfifo_regmode_rx : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + + -- ======= + -- outputs + -- ======= + -- Indicates overflow (rd_clk) + -- FIFO empty (rd_clk) + data_out : OUT STD_LOGIC_VECTOR(69 DOWNTO 0); -- output data (rd_clk synchronous if not FIFO bypass) + ph_fifo_full : OUT STD_LOGIC; + ph_fifo_empty : OUT STD_LOGIC; + wptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- test bus + rptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_wrapback_in : IN STD_LOGIC_VECTOR(69 DOWNTO 0); + rpcs_wrapback_en : IN STD_LOGIC; + scan_mode : IN STD_LOGIC + ); +END cycloneiv_hssi_rx_digis_ph_fifo; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_digis_ph_fifo IS + COMPONENT cycloneiv_hssi_rx_digis_ram8x70_syn IS + GENERIC ( + read_access_time : INTEGER := 0; + write_access_time : INTEGER := 0; + ram_width : INTEGER := 70 + ); + PORT ( + rst_l : IN STD_LOGIC; + clk : IN STD_LOGIC; + fifo_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR(69 DOWNTO 0); + fifo_re : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR(69 DOWNTO 0) + ); + END COMPONENT; + + + -- =================== + -- signal declaration + -- =================== + SIGNAL wptr : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rptr : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL wptr_gray : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL wptr_gray0 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL wptr0 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL wptr1 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL wptr1_onehot : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rptr0_pre : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rptr0 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rptr1 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL first_rd : STD_LOGIC; + SIGNAL ram_data_out : STD_LOGIC_VECTOR(69 DOWNTO 0); + SIGNAL ram_data_out_pre : STD_LOGIC_VECTOR(69 DOWNTO 0); + -- test bus + -- test bus + + SIGNAL ph_fifo_empty_pre : STD_LOGIC; + + SIGNAL rst_n : STD_LOGIC; -- Invert rst for new FIFO + + SIGNAL fifo_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL fifo_cnt_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rptr1_bin : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL wptr1_bin_rclk : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL reset_ptrs_local : STD_LOGIC; + + SIGNAL reset_ptrs_local_sync1 : STD_LOGIC; + SIGNAL reset_ptrs_local_sync2 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL ph_fifo_full_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + ph_fifo_full <= ph_fifo_full_xhdl0; + + -- ============= + -- functionality + -- ============= + rst_n <= NOT(rst_wclk); + + -- bypass + data_out(69 DOWNTO 0) <= ram_data_out WHEN (en = '1') ELSE + din; + + reset_ptrs_local <= rauto_speed_ena AND reset_pc_ptrs WHEN (rindv_rx = '1') ELSE + reset_pc_ptrs_centrl WHEN (rmaster_rx = '1') ELSE + reset_pc_ptrs_quad_up WHEN (rmaster_up_rx = '1') ELSE + reset_pc_ptrs_quad_down; + + -- write pointer + PROCESS (rst_wclk, wr_clk) + BEGIN + IF (rst_wclk = '1') THEN + wptr <= TRANSPORT "00000001" AFTER 1 ps; + ELSIF (wr_clk'EVENT AND wr_clk = '1') THEN + IF (rphfifo_regmode_rx = '1') THEN + wptr <= TRANSPORT "00000001" AFTER 1 ps; + ELSIF (reset_ptrs_local = '1') THEN + wptr <= TRANSPORT "00000001" AFTER 1 ps; + ELSE + IF (we = '1') THEN + wptr <= TRANSPORT (wptr(6 DOWNTO 0) & wptr(7)) AFTER 1 ps; + END IF; + END IF; + END IF; + END PROCESS; + + --newly added fifo_cnt and fifo_cnt_pre logic for full/empty flag use + -- manually translated + PROCESS(fifo_cnt_pre, rst_rclk, rptr1_bin, wptr1_bin_rclk) + BEGIN + IF (rptr1_bin = wptr1_bin_rclk) THEN + IF (rst_rclk /= '1') THEN + IF (fifo_cnt_pre = "0111" OR fifo_cnt_pre = "0110" OR fifo_cnt_pre = "1000") THEN + fifo_cnt <= "1000"; + ELSE + fifo_cnt <= "0000"; + END IF; + ELSE + fifo_cnt <= "0000"; + END IF; + ELSE + IF (wptr1_bin_rclk > rptr1_bin) THEN + fifo_cnt <= ('0' & (wptr1_bin_rclk - rptr1_bin)); + ELSE + fifo_cnt <= ("1000" - ('0' & (rptr1_bin - wptr1_bin_rclk))); + END IF; + END IF; + END PROCESS; + + -- incorrect translation + --fifo_cnt <= "1000" WHEN (fifo_cnt_pre = "0111" OR fifo_cnt_pre = "0110" OR fifo_cnt_pre = "1000") ELSE + -- "0000" WHEN (rst_rclk /= '1') ELSE + -- "0000" WHEN (rptr1_bin = wptr1_bin_rclk) ELSE + -- ('0' & (wptr1_bin_rclk - rptr1_bin)) WHEN (wptr1_bin_rclk > rptr1_bin) ELSE + -- ("1000" - ('0' & (rptr1_bin - wptr1_bin_rclk))); + + PROCESS (rst_rclk, rd_clk) + BEGIN + IF (rst_rclk = '1') THEN + reset_ptrs_local_sync1 <= TRANSPORT '0' AFTER 1 ps; + reset_ptrs_local_sync2 <= TRANSPORT '0' AFTER 1 ps; -- if (rst_rclk == 1'b1) + ELSIF (rd_clk'EVENT AND rd_clk = '1') THEN + IF (rphfifo_regmode_rx = '1') THEN + reset_ptrs_local_sync1 <= TRANSPORT '0' AFTER 1 ps; + reset_ptrs_local_sync2 <= TRANSPORT '0' AFTER 1 ps; + ELSE + reset_ptrs_local_sync1 <= TRANSPORT reset_ptrs_local AFTER 1 ps; + reset_ptrs_local_sync2 <= TRANSPORT reset_ptrs_local_sync1 AFTER 1 ps; + END IF; + END IF; + END PROCESS; + -- always @ (posedge rst_rclk or posedge rd_clk) + + --ECO for S4GX to fix metastability issue + -- replace the 1st FF with new flop w/o reset + -- replace the 2nd FF with an enhanced flop + PROCESS (rd_clk) + BEGIN + IF (rd_clk'EVENT AND rd_clk = '1') THEN + IF (reset_ptrs_local_sync2 = '1' OR rphfifo_regmode_rx = '1') THEN + wptr0 <= TRANSPORT "001" AFTER 1 ps; + ELSE + wptr0 <= TRANSPORT wptr_gray AFTER 1 ps; + END IF; + END IF; + END PROCESS; -- always @ (posedge rst_rclk or posedge rd_clk) + + PROCESS(rst_rclk, rd_clk) + BEGIN + IF (rst_rclk = '1') THEN + wptr1 <= TRANSPORT "001" AFTER 1 ps; + ELSIF (rd_clk'EVENT AND rd_clk = '1') THEN + IF ((reset_ptrs_local_sync2 OR rphfifo_regmode_rx) = '1') THEN + wptr1 <= TRANSPORT "001" AFTER 1 ps; + ELSE + wptr1 <= TRANSPORT wptr0 AFTER 1 ps; + END IF; + END IF; + END PROCESS; -- always @ (posedge rst_rclk or posedge rd_clk) + + -- read pointer + -- full & empty + PROCESS (rst_rclk, rd_clk) + BEGIN + IF (rst_rclk = '1') THEN + --wptr0 <= TRANSPORT "001" AFTER 1 ps; + --wptr1 <= TRANSPORT "001" AFTER 1 ps; + rptr <= TRANSPORT "00100000" AFTER 1 ps; + rptr0_pre <= TRANSPORT "00010000" AFTER 1 ps; + rptr0 <= TRANSPORT "00010000" AFTER 1 ps; + rptr1 <= TRANSPORT "00010000" AFTER 1 ps; + ph_fifo_full_xhdl0 <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_empty <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_empty_pre <= TRANSPORT '0' AFTER 1 ps; + first_rd <= TRANSPORT '1' AFTER 1 ps; -- fifo_cnt previous value + fifo_cnt_pre <= TRANSPORT "0000" AFTER 1 ps; -- if (rst_rclk == 1'b1) + ELSIF (rd_clk'EVENT AND rd_clk = '1') THEN + IF ((reset_ptrs_local_sync2 OR rphfifo_regmode_rx) = '1') THEN + --wptr0 <= TRANSPORT "001" AFTER 1 ps; + --wptr1 <= TRANSPORT "001" AFTER 1 ps; + rptr <= TRANSPORT "00100000" AFTER 1 ps; + rptr0_pre <= TRANSPORT "00010000" AFTER 1 ps; + rptr0 <= TRANSPORT "00010000" AFTER 1 ps; + rptr1 <= TRANSPORT "00010000" AFTER 1 ps; + ph_fifo_full_xhdl0 <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_empty <= TRANSPORT '0' AFTER 1 ps; + ph_fifo_empty_pre <= TRANSPORT '0' AFTER 1 ps; + first_rd <= TRANSPORT '1' AFTER 1 ps; -- fifo_cnt previous value + fifo_cnt_pre <= TRANSPORT "0000" AFTER 1 ps; -- if (reset_ptrs_local_sync2) + ELSE + ph_fifo_empty <= TRANSPORT ph_fifo_empty_pre AFTER 1 ps; + + fifo_cnt_pre <= TRANSPORT fifo_cnt AFTER 1 ps; + + --wptr0 <= TRANSPORT wptr_gray AFTER 1 ps; + --wptr1 <= TRANSPORT wptr0 AFTER 1 ps; + + rptr0_pre <= TRANSPORT rptr AFTER 1 ps; + rptr0 <= TRANSPORT rptr0_pre AFTER 1 ps; + + rptr1 <= TRANSPORT rptr0 AFTER 1 ps; + IF (first_rd = '1' AND re = '1') THEN + + -- advance by 2 on first read in low-latency mode + first_rd <= TRANSPORT '0' AFTER 1 ps; + END IF; + IF (re = '1') THEN + IF (first_rd = '1' AND lowlatency_en = '1') THEN + rptr <= TRANSPORT (rptr(5 DOWNTO 0) & rptr(7 DOWNTO 6)) AFTER 1 ps; + ELSE + + -- full condition + --$if ({wptr1_onehot[6:0],wptr1_onehot[7]} == rptr1) + --new full flag requirement + rptr <= TRANSPORT (rptr(6 DOWNTO 0) & rptr(7)) AFTER 1 ps; + END IF; + END IF; + IF ( ((rptr1(6 DOWNTO 0) & rptr1(7)) = wptr1_onehot) AND (fifo_cnt_pre = "0111" OR fifo_cnt_pre = "1000") AND ((NOT ph_fifo_empty_pre) = '1') ) THEN + --else if (ph_fifo_full == 1'b1 && ({rptr1[6:0],rptr1[7]} != wptr1_onehot)) //become sticky until reset + --ph_fifo_full <= #1 1'b0; + + -- empty condition + --$if ({rptr1[6:0],rptr1[7]} == wptr1_onehot) + --new empty flag requirement + ph_fifo_full_xhdl0 <= TRANSPORT '1' AFTER 1 ps; + END IF; + IF (fifo_cnt = "0000" AND ((NOT(ph_fifo_full_xhdl0))) = '1') THEN + --else if (ph_fifo_empty_pre == 1'b1 && (rptr1 != wptr1_onehot)) // become sticky until reset + --ph_fifo_empty_pre <= #1 1'b0; + ph_fifo_empty_pre <= TRANSPORT '1' AFTER 1 ps; -- else: !if(rst_rclk == 1'b1) + END IF; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge rst_rclk or posedge rd_clk) + + + + ram8x70_syn_1 : cycloneiv_hssi_rx_digis_ram8x70_syn + PORT MAP ( + rst_l => rst_n, + clk => wr_clk, + fifo_wr => wptr, + data_in => din, + fifo_re => rptr, + data_out => ram_data_out_pre + ); + + PROCESS (rst_rclk, rd_clk) + BEGIN + IF (rst_rclk = '1') THEN + ram_data_out <= TRANSPORT "0000000000000000000000000000000000000000000000000000000000000000000000" AFTER 1 ps; + ELSIF (rd_clk'EVENT AND rd_clk = '1') THEN + IF (rphfifo_regmode_rx = '1') THEN + ram_data_out <= TRANSPORT din AFTER 1 ps; + ELSE + ram_data_out <= TRANSPORT ram_data_out_pre AFTER 1 ps; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge rst_rclk or posedge rd_clk) + + PROCESS (wptr) + BEGIN + CASE wptr IS + WHEN "00000001" => + wptr_bin <= "000"; + WHEN "00000010" => + wptr_bin <= "001"; + WHEN "00000100" => + wptr_bin <= "010"; + WHEN "00001000" => + wptr_bin <= "011"; + WHEN "00010000" => + wptr_bin <= "100"; + WHEN "00100000" => + wptr_bin <= "101"; + WHEN "01000000" => + wptr_bin <= "110"; + WHEN "10000000" => + wptr_bin <= "111"; + WHEN OTHERS => -- case(wptr) + wptr_bin <= "111"; + END CASE; + END PROCESS; + + -- always@ (wptr) + + PROCESS (rptr) + BEGIN + CASE rptr IS + WHEN "00000001" => + rptr_bin <= "000"; + WHEN "00000010" => + rptr_bin <= "001"; + WHEN "00000100" => + rptr_bin <= "010"; + WHEN "00001000" => + rptr_bin <= "011"; + WHEN "00010000" => + rptr_bin <= "100"; + WHEN "00100000" => + rptr_bin <= "101"; + WHEN "01000000" => + rptr_bin <= "110"; + WHEN "10000000" => + rptr_bin <= "111"; + WHEN OTHERS => -- case(rptr) + rptr_bin <= "111"; + END CASE; + END PROCESS; + + -- always@ (rptr) + + PROCESS (rptr1) + BEGIN + CASE rptr1 IS + WHEN "00000001" => + rptr1_bin <= "000"; + WHEN "00000010" => + rptr1_bin <= "001"; + WHEN "00000100" => + rptr1_bin <= "010"; + WHEN "00001000" => + rptr1_bin <= "011"; + WHEN "00010000" => + rptr1_bin <= "100"; + WHEN "00100000" => + rptr1_bin <= "101"; + WHEN "01000000" => + rptr1_bin <= "110"; + WHEN "10000000" => + rptr1_bin <= "111"; + WHEN OTHERS => -- case(rptr1) + rptr1_bin <= "111"; + END CASE; + END PROCESS; + + -- always@ (rptr1) + + PROCESS (rst_wclk, wr_clk) + BEGIN + IF (rst_wclk = '1') THEN + wptr_gray <= TRANSPORT "000" AFTER 1 ps; + ELSIF (wr_clk'EVENT AND wr_clk = '1') THEN + wptr_gray <= TRANSPORT wptr_gray0 AFTER 1 ps; + END IF; + END PROCESS; + + + PROCESS (wptr) + BEGIN + CASE wptr IS + WHEN "00000001" => + wptr_gray0 <= "000"; + WHEN "00000010" => + wptr_gray0 <= "001"; + WHEN "00000100" => + wptr_gray0 <= "011"; + WHEN "00001000" => + wptr_gray0 <= "010"; + WHEN "00010000" => + wptr_gray0 <= "110"; + WHEN "00100000" => + wptr_gray0 <= "111"; + WHEN "01000000" => + wptr_gray0 <= "101"; + WHEN "10000000" => + wptr_gray0 <= "100"; + WHEN OTHERS => -- case(wptr) + wptr_gray0 <= "000"; + END CASE; + END PROCESS; + + -- always@ (wptr) + + PROCESS (wptr1) + BEGIN + CASE wptr1 IS + WHEN "000" => + wptr1_onehot <= "00000001"; + WHEN "001" => + wptr1_onehot <= "00000010"; + WHEN "011" => + wptr1_onehot <= "00000100"; + WHEN "010" => + wptr1_onehot <= "00001000"; + WHEN "110" => + wptr1_onehot <= "00010000"; + WHEN "111" => + wptr1_onehot <= "00100000"; + WHEN "101" => + wptr1_onehot <= "01000000"; + WHEN "100" => + wptr1_onehot <= "10000000"; + WHEN OTHERS => -- case(wptr1) + wptr1_onehot <= "10000000"; + END CASE; + END PROCESS; + + -- always@ (wptr1) + + PROCESS (wptr1) + BEGIN + CASE wptr1 IS + WHEN "000" => + wptr1_bin_rclk <= "000"; + WHEN "001" => + wptr1_bin_rclk <= "001"; + WHEN "011" => + wptr1_bin_rclk <= "010"; + WHEN "010" => + wptr1_bin_rclk <= "011"; + WHEN "110" => + wptr1_bin_rclk <= "100"; + WHEN "111" => + wptr1_bin_rclk <= "101"; + WHEN "101" => + wptr1_bin_rclk <= "110"; + WHEN "100" => + wptr1_bin_rclk <= "111"; + WHEN OTHERS => -- case(wptr1) + wptr1_bin_rclk <= "000"; + END CASE; + END PROCESS; + + +END trans; + + +-- always@ (wptr1) + +-- ph_fifo_rx + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_digis_ram16x14_syn IS + GENERIC ( + + read_access_time : INTEGER := 0; + write_access_time : INTEGER := 0; + ram_width : INTEGER := 14 + ); + PORT ( + clk : IN STD_LOGIC; + rst_l : IN STD_LOGIC; + addr_wr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + addr_rd1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + addr_rd2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + we : IN STD_LOGIC; + re_l : IN STD_LOGIC; + data_out1 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + data_out2 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) + ); +END cycloneiv_hssi_rx_digis_ram16x14_syn; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_digis_ram16x14_syn IS + + SIGNAL data_out1_i : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_out2_i : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_8 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_9 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_10 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_11 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_12 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_13 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_14 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_15 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_8 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_9 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_10 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_11 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_12 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_13 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_14 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_15 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_8 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_9 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_10 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_11 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_12 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_13 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_14 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_15 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); +BEGIN + + --assignment + data_reg_0 <= data_in WHEN (addr_wr(0) = '1') ELSE + ram_array_q_0; + data_reg_1 <= data_in WHEN (addr_wr(1) = '1') ELSE + ram_array_q_1; + data_reg_2 <= data_in WHEN (addr_wr(2) = '1') ELSE + ram_array_q_2; + data_reg_3 <= data_in WHEN (addr_wr(3) = '1') ELSE + ram_array_q_3; + data_reg_4 <= data_in WHEN (addr_wr(4) = '1') ELSE + ram_array_q_4; + data_reg_5 <= data_in WHEN (addr_wr(5) = '1') ELSE + ram_array_q_5; + data_reg_6 <= data_in WHEN (addr_wr(6) = '1') ELSE + ram_array_q_6; + data_reg_7 <= data_in WHEN (addr_wr(7) = '1') ELSE + ram_array_q_7; + data_reg_8 <= data_in WHEN (addr_wr(8) = '1') ELSE + ram_array_q_8; + data_reg_9 <= data_in WHEN (addr_wr(9) = '1') ELSE + ram_array_q_9; + data_reg_10 <= data_in WHEN (addr_wr(10) = '1') ELSE + ram_array_q_10; + data_reg_11 <= data_in WHEN (addr_wr(11) = '1') ELSE + ram_array_q_11; + data_reg_12 <= data_in WHEN (addr_wr(12) = '1') ELSE + ram_array_q_12; + data_reg_13 <= data_in WHEN (addr_wr(13) = '1') ELSE + ram_array_q_13; + data_reg_14 <= data_in WHEN (addr_wr(14) = '1') ELSE + ram_array_q_14; + data_reg_15 <= data_in WHEN (addr_wr(15) = '1') ELSE + ram_array_q_15; + + data_out1 <= "00000000000000" WHEN (re_l = '1') ELSE + data_out1_i; + data_out2 <= "00000000000000" WHEN (re_l = '1') ELSE + data_out2_i; + + PROCESS (ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15, addr_rd1, addr_rd2) +VARIABLE txt : LINE; + BEGIN + CASE addr_rd1 IS -- synopsys parallel_case full_case + WHEN "0000000000000001" => + data_out1_i <= ram_array_q_0; + WHEN "0000000000000010" => + data_out1_i <= ram_array_q_1; + WHEN "0000000000000100" => + data_out1_i <= ram_array_q_2; + WHEN "0000000000001000" => + data_out1_i <= ram_array_q_3; + WHEN "0000000000010000" => + data_out1_i <= ram_array_q_4; + WHEN "0000000000100000" => + data_out1_i <= ram_array_q_5; + WHEN "0000000001000000" => + data_out1_i <= ram_array_q_6; + WHEN "0000000010000000" => + data_out1_i <= ram_array_q_7; + WHEN "0000000100000000" => + data_out1_i <= ram_array_q_8; + WHEN "0000001000000000" => + data_out1_i <= ram_array_q_9; + WHEN "0000010000000000" => + data_out1_i <= ram_array_q_10; + WHEN "0000100000000000" => + data_out1_i <= ram_array_q_11; + WHEN "0001000000000000" => + data_out1_i <= ram_array_q_12; + WHEN "0010000000000000" => + data_out1_i <= ram_array_q_13; + WHEN "0100000000000000" => + data_out1_i <= ram_array_q_14; + WHEN "1000000000000000" => + data_out1_i <= ram_array_q_15; + WHEN OTHERS => + NULL; + END CASE; + + CASE addr_rd2 IS -- synopsys parallel_case full_case + WHEN "0000000000000001" => + data_out2_i <= ram_array_q_0; + WHEN "0000000000000010" => + data_out2_i <= ram_array_q_1; + WHEN "0000000000000100" => + data_out2_i <= ram_array_q_2; + WHEN "0000000000001000" => + data_out2_i <= ram_array_q_3; + WHEN "0000000000010000" => + data_out2_i <= ram_array_q_4; + WHEN "0000000000100000" => + data_out2_i <= ram_array_q_5; + WHEN "0000000001000000" => + data_out2_i <= ram_array_q_6; + WHEN "0000000010000000" => + data_out2_i <= ram_array_q_7; + WHEN "0000000100000000" => + data_out2_i <= ram_array_q_8; + WHEN "0000001000000000" => + data_out2_i <= ram_array_q_9; + WHEN "0000010000000000" => + data_out2_i <= ram_array_q_10; + WHEN "0000100000000000" => + data_out2_i <= ram_array_q_11; + WHEN "0001000000000000" => + data_out2_i <= ram_array_q_12; + WHEN "0010000000000000" => + data_out2_i <= ram_array_q_13; + WHEN "0100000000000000" => + data_out2_i <= ram_array_q_14; + WHEN "1000000000000000" => + data_out2_i <= ram_array_q_15; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS; + + PROCESS (clk, rst_l) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rst_l)) = '1') THEN + ram_array_q_0 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_1 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_2 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_3 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_4 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_5 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_6 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_7 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_8 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_9 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_10 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_11 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_12 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_13 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_14 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ram_array_q_15 <= TRANSPORT "00000000000000" AFTER (write_access_time)*1* 1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + ram_array_q_0 <= TRANSPORT ram_array_d_0 AFTER (write_access_time)*1* 1 ps; + ram_array_q_1 <= TRANSPORT ram_array_d_1 AFTER (write_access_time)*1* 1 ps; + ram_array_q_2 <= TRANSPORT ram_array_d_2 AFTER (write_access_time)*1* 1 ps; + ram_array_q_3 <= TRANSPORT ram_array_d_3 AFTER (write_access_time)*1* 1 ps; + ram_array_q_4 <= TRANSPORT ram_array_d_4 AFTER (write_access_time)*1* 1 ps; + ram_array_q_5 <= TRANSPORT ram_array_d_5 AFTER (write_access_time)*1* 1 ps; + ram_array_q_6 <= TRANSPORT ram_array_d_6 AFTER (write_access_time)*1* 1 ps; + ram_array_q_7 <= TRANSPORT ram_array_d_7 AFTER (write_access_time)*1* 1 ps; + ram_array_q_8 <= TRANSPORT ram_array_d_8 AFTER (write_access_time)*1* 1 ps; + ram_array_q_9 <= TRANSPORT ram_array_d_9 AFTER (write_access_time)*1* 1 ps; + ram_array_q_10 <= TRANSPORT ram_array_d_10 AFTER (write_access_time)*1* 1 ps; + ram_array_q_11 <= TRANSPORT ram_array_d_11 AFTER (write_access_time)*1* 1 ps; + ram_array_q_12 <= TRANSPORT ram_array_d_12 AFTER (write_access_time)*1* 1 ps; + ram_array_q_13 <= TRANSPORT ram_array_d_13 AFTER (write_access_time)*1* 1 ps; + ram_array_q_14 <= TRANSPORT ram_array_d_14 AFTER (write_access_time)*1* 1 ps; + ram_array_q_15 <= TRANSPORT ram_array_d_15 AFTER (write_access_time)*1* 1 ps; + END IF; + END PROCESS; + + PROCESS (we, data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7, data_reg_8, data_reg_9, data_reg_10, data_reg_11, data_reg_12, data_reg_13, data_reg_14, data_reg_15, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15) +VARIABLE txt : LINE; + BEGIN + IF (we = '1') THEN + ram_array_d_0 <= TRANSPORT data_reg_0 AFTER (write_access_time)*1* 1 ps; + ram_array_d_1 <= TRANSPORT data_reg_1 AFTER (write_access_time)*1* 1 ps; + ram_array_d_2 <= TRANSPORT data_reg_2 AFTER (write_access_time)*1* 1 ps; + ram_array_d_3 <= TRANSPORT data_reg_3 AFTER (write_access_time)*1* 1 ps; + ram_array_d_4 <= TRANSPORT data_reg_4 AFTER (write_access_time)*1* 1 ps; + ram_array_d_5 <= TRANSPORT data_reg_5 AFTER (write_access_time)*1* 1 ps; + ram_array_d_6 <= TRANSPORT data_reg_6 AFTER (write_access_time)*1* 1 ps; + ram_array_d_7 <= TRANSPORT data_reg_7 AFTER (write_access_time)*1* 1 ps; + ram_array_d_8 <= TRANSPORT data_reg_8 AFTER (write_access_time)*1* 1 ps; + ram_array_d_9 <= TRANSPORT data_reg_9 AFTER (write_access_time)*1* 1 ps; + ram_array_d_10 <= TRANSPORT data_reg_10 AFTER (write_access_time)*1* 1 ps; + ram_array_d_11 <= TRANSPORT data_reg_11 AFTER (write_access_time)*1* 1 ps; + ram_array_d_12 <= TRANSPORT data_reg_12 AFTER (write_access_time)*1* 1 ps; + ram_array_d_13 <= TRANSPORT data_reg_13 AFTER (write_access_time)*1* 1 ps; + ram_array_d_14 <= TRANSPORT data_reg_14 AFTER (write_access_time)*1* 1 ps; + ram_array_d_15 <= TRANSPORT data_reg_15 AFTER (write_access_time)*1* 1 ps; + ELSE + ram_array_d_0 <= TRANSPORT ram_array_q_0 AFTER (write_access_time)*1* 1 ps; + ram_array_d_1 <= TRANSPORT ram_array_q_1 AFTER (write_access_time)*1* 1 ps; + ram_array_d_2 <= TRANSPORT ram_array_q_2 AFTER (write_access_time)*1* 1 ps; + ram_array_d_3 <= TRANSPORT ram_array_q_3 AFTER (write_access_time)*1* 1 ps; + ram_array_d_4 <= TRANSPORT ram_array_q_4 AFTER (write_access_time)*1* 1 ps; + ram_array_d_5 <= TRANSPORT ram_array_q_5 AFTER (write_access_time)*1* 1 ps; + ram_array_d_6 <= TRANSPORT ram_array_q_6 AFTER (write_access_time)*1* 1 ps; + ram_array_d_7 <= TRANSPORT ram_array_q_7 AFTER (write_access_time)*1* 1 ps; + ram_array_d_8 <= TRANSPORT ram_array_q_8 AFTER (write_access_time)*1* 1 ps; + ram_array_d_9 <= TRANSPORT ram_array_q_9 AFTER (write_access_time)*1* 1 ps; + ram_array_d_10 <= TRANSPORT ram_array_q_10 AFTER (write_access_time)*1* 1 ps; + ram_array_d_11 <= TRANSPORT ram_array_q_11 AFTER (write_access_time)*1* 1 ps; + ram_array_d_12 <= TRANSPORT ram_array_q_12 AFTER (write_access_time)*1* 1 ps; + ram_array_d_13 <= TRANSPORT ram_array_q_13 AFTER (write_access_time)*1* 1 ps; + ram_array_d_14 <= TRANSPORT ram_array_q_14 AFTER (write_access_time)*1* 1 ps; + + ram_array_d_15 <= TRANSPORT ram_array_q_15 AFTER (write_access_time)*1* 1 ps; + END IF; + END PROCESS; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_digis_ram20x16_syn IS + GENERIC ( + + read_access_time : INTEGER := 0; + write_access_time : INTEGER := 0; + ram_width : INTEGER := 16 + ); + PORT ( + data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; + fifo_wr : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + rst_l : IN STD_LOGIC; + fifo_re1 : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + fifo_re2 : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + data_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + data_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END cycloneiv_hssi_rx_digis_ram20x16_syn; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_digis_ram20x16_syn IS + + SIGNAL data_out1_i : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_out2_i : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_8 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_9 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_10 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_11 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_12 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_13 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_14 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_15 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_16 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_17 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_18 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_d_19 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_8 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_9 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_10 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_11 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_12 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_13 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_14 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_15 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_16 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_17 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_18 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL ram_array_q_19 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_0 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_1 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_2 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_3 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_4 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_5 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_6 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_7 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_8 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_9 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_10 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_11 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_12 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_13 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_14 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_15 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_16 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_17 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_18 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + SIGNAL data_reg_19 : STD_LOGIC_VECTOR(ram_width - 1 DOWNTO 0); + + SIGNAL we : STD_LOGIC; + SIGNAL re_l : STD_LOGIC; +BEGIN + + we <= '1'; + re_l <= '0'; + + --assignment + data_reg_0 <= data_in WHEN (fifo_wr(0) = '1') ELSE + ram_array_q_0; + data_reg_1 <= data_in WHEN (fifo_wr(1) = '1') ELSE + ram_array_q_1; + data_reg_2 <= data_in WHEN (fifo_wr(2) = '1') ELSE + ram_array_q_2; + data_reg_3 <= data_in WHEN (fifo_wr(3) = '1') ELSE + ram_array_q_3; + data_reg_4 <= data_in WHEN (fifo_wr(4) = '1') ELSE + ram_array_q_4; + data_reg_5 <= data_in WHEN (fifo_wr(5) = '1') ELSE + ram_array_q_5; + data_reg_6 <= data_in WHEN (fifo_wr(6) = '1') ELSE + ram_array_q_6; + data_reg_7 <= data_in WHEN (fifo_wr(7) = '1') ELSE + ram_array_q_7; + data_reg_8 <= data_in WHEN (fifo_wr(8) = '1') ELSE + ram_array_q_8; + data_reg_9 <= data_in WHEN (fifo_wr(9) = '1') ELSE + ram_array_q_9; + data_reg_10 <= data_in WHEN (fifo_wr(10) = '1') ELSE + ram_array_q_10; + data_reg_11 <= data_in WHEN (fifo_wr(11) = '1') ELSE + ram_array_q_11; + data_reg_12 <= data_in WHEN (fifo_wr(12) = '1') ELSE + ram_array_q_12; + data_reg_13 <= data_in WHEN (fifo_wr(13) = '1') ELSE + ram_array_q_13; + data_reg_14 <= data_in WHEN (fifo_wr(14) = '1') ELSE + ram_array_q_14; + data_reg_15 <= data_in WHEN (fifo_wr(15) = '1') ELSE + ram_array_q_15; + data_reg_16 <= data_in WHEN (fifo_wr(16) = '1') ELSE + ram_array_q_16; + data_reg_17 <= data_in WHEN (fifo_wr(17) = '1') ELSE + ram_array_q_17; + data_reg_18 <= data_in WHEN (fifo_wr(18) = '1') ELSE + ram_array_q_18; + data_reg_19 <= data_in WHEN (fifo_wr(19) = '1') ELSE + ram_array_q_19; + + -- 03/22/05 VC: LEDA fix: Remove delay on combinatorial statement + -- and changed 15'b0 to 16'd0 + --assign #read_access_time data_out1 = re_l ? 15'b0 : data_out1_i; + --assign #read_access_time data_out2 = re_l ? 15'b0 : data_out2_i; + data_out1 <= "0000000000000000" WHEN (re_l = '1') ELSE + data_out1_i; + data_out2 <= "0000000000000000" WHEN (re_l = '1') ELSE + data_out2_i; + + PROCESS (ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15, ram_array_q_16, ram_array_q_17, ram_array_q_18, ram_array_q_19, fifo_re1, fifo_re2) +VARIABLE txt : LINE; + BEGIN + -- 03/22/05 VC: Removed full case statement because + -- not all cases are listed + -- case ( fifo_re1 ) // synopsys parallel_case full_case + CASE fifo_re1 IS -- synopsys parallel_case + WHEN "00000000000000000001" => + data_out1_i <= ram_array_q_0; + WHEN "00000000000000000010" => + data_out1_i <= ram_array_q_1; + WHEN "00000000000000000100" => + data_out1_i <= ram_array_q_2; + WHEN "00000000000000001000" => + data_out1_i <= ram_array_q_3; + WHEN "00000000000000010000" => + data_out1_i <= ram_array_q_4; + WHEN "00000000000000100000" => + data_out1_i <= ram_array_q_5; + WHEN "00000000000001000000" => + data_out1_i <= ram_array_q_6; + WHEN "00000000000010000000" => + data_out1_i <= ram_array_q_7; + WHEN "00000000000100000000" => + data_out1_i <= ram_array_q_8; + WHEN "00000000001000000000" => + data_out1_i <= ram_array_q_9; + WHEN "00000000010000000000" => + data_out1_i <= ram_array_q_10; + WHEN "00000000100000000000" => + data_out1_i <= ram_array_q_11; + WHEN "00000001000000000000" => + data_out1_i <= ram_array_q_12; + WHEN "00000010000000000000" => + data_out1_i <= ram_array_q_13; + WHEN "00000100000000000000" => + data_out1_i <= ram_array_q_14; + WHEN "00001000000000000000" => + data_out1_i <= ram_array_q_15; + WHEN "00010000000000000000" => + data_out1_i <= ram_array_q_16; + WHEN "00100000000000000000" => + data_out1_i <= ram_array_q_17; + WHEN "01000000000000000000" => + data_out1_i <= ram_array_q_18; + -- 03/22/05 VC: LEDA fix: Added default clause to case statement + WHEN "10000000000000000000" => + data_out1_i <= ram_array_q_19; + WHEN OTHERS => + data_out1_i <= ram_array_q_0; + END CASE; + + -- 03/22/05 VC: Removed full case statement because + -- not all cases are listed + -- case ( fifo_re2 ) // synopsys parallel_case full_case + CASE fifo_re2 IS -- synopsys parallel_case + WHEN "00000000000000000001" => + data_out2_i <= ram_array_q_0; + WHEN "00000000000000000010" => + data_out2_i <= ram_array_q_1; + WHEN "00000000000000000100" => + data_out2_i <= ram_array_q_2; + WHEN "00000000000000001000" => + data_out2_i <= ram_array_q_3; + WHEN "00000000000000010000" => + data_out2_i <= ram_array_q_4; + WHEN "00000000000000100000" => + data_out2_i <= ram_array_q_5; + WHEN "00000000000001000000" => + data_out2_i <= ram_array_q_6; + WHEN "00000000000010000000" => + data_out2_i <= ram_array_q_7; + WHEN "00000000000100000000" => + data_out2_i <= ram_array_q_8; + WHEN "00000000001000000000" => + data_out2_i <= ram_array_q_9; + WHEN "00000000010000000000" => + data_out2_i <= ram_array_q_10; + WHEN "00000000100000000000" => + data_out2_i <= ram_array_q_11; + WHEN "00000001000000000000" => + data_out2_i <= ram_array_q_12; + WHEN "00000010000000000000" => + data_out2_i <= ram_array_q_13; + WHEN "00000100000000000000" => + data_out2_i <= ram_array_q_14; + WHEN "00001000000000000000" => + data_out2_i <= ram_array_q_15; + WHEN "00010000000000000000" => + data_out2_i <= ram_array_q_16; + WHEN "00100000000000000000" => + data_out2_i <= ram_array_q_17; + WHEN "01000000000000000000" => + data_out2_i <= ram_array_q_18; + -- 03/22/05 VC: LEDA fix: Added default clause to case statement + WHEN "10000000000000000000" => + data_out2_i <= ram_array_q_19; + WHEN OTHERS => + data_out2_i <= ram_array_q_0; + END CASE; + END PROCESS; + + -- 03/22/05 VC: LEDA fix: Change 0 to 16'd0 + PROCESS (clk, rst_l) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rst_l)) = '1') THEN + ram_array_q_0 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_1 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_2 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_3 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_4 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_5 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_6 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_7 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_8 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_9 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_10 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_11 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_12 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_13 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_14 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_15 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_16 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_17 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_18 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ram_array_q_19 <= TRANSPORT "0000000000000000" AFTER (write_access_time)*1 ps; + ELSIF (clk'EVENT AND clk = '1') THEN + ram_array_q_0 <= TRANSPORT ram_array_d_0 AFTER (write_access_time)*1 ps; + ram_array_q_1 <= TRANSPORT ram_array_d_1 AFTER (write_access_time)*1 ps; + ram_array_q_2 <= TRANSPORT ram_array_d_2 AFTER (write_access_time)*1 ps; + ram_array_q_3 <= TRANSPORT ram_array_d_3 AFTER (write_access_time)*1 ps; + ram_array_q_4 <= TRANSPORT ram_array_d_4 AFTER (write_access_time)*1 ps; + ram_array_q_5 <= TRANSPORT ram_array_d_5 AFTER (write_access_time)*1 ps; + ram_array_q_6 <= TRANSPORT ram_array_d_6 AFTER (write_access_time)*1 ps; + ram_array_q_7 <= TRANSPORT ram_array_d_7 AFTER (write_access_time)*1 ps; + ram_array_q_8 <= TRANSPORT ram_array_d_8 AFTER (write_access_time)*1 ps; + ram_array_q_9 <= TRANSPORT ram_array_d_9 AFTER (write_access_time)*1 ps; + ram_array_q_10 <= TRANSPORT ram_array_d_10 AFTER (write_access_time)*1 ps; + ram_array_q_11 <= TRANSPORT ram_array_d_11 AFTER (write_access_time)*1 ps; + ram_array_q_12 <= TRANSPORT ram_array_d_12 AFTER (write_access_time)*1 ps; + ram_array_q_13 <= TRANSPORT ram_array_d_13 AFTER (write_access_time)*1 ps; + ram_array_q_14 <= TRANSPORT ram_array_d_14 AFTER (write_access_time)*1 ps; + ram_array_q_15 <= TRANSPORT ram_array_d_15 AFTER (write_access_time)*1 ps; + ram_array_q_16 <= TRANSPORT ram_array_d_16 AFTER (write_access_time)*1 ps; + ram_array_q_17 <= TRANSPORT ram_array_d_17 AFTER (write_access_time)*1 ps; + ram_array_q_18 <= TRANSPORT ram_array_d_18 AFTER (write_access_time)*1 ps; + ram_array_q_19 <= TRANSPORT ram_array_d_19 AFTER (write_access_time)*1 ps; + END IF; + END PROCESS; + + PROCESS (we, data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7, data_reg_8, data_reg_9, data_reg_10, data_reg_11, data_reg_12, data_reg_13, data_reg_14, data_reg_15, data_reg_16, data_reg_17, data_reg_18, data_reg_19, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15, ram_array_q_16, ram_array_q_17, ram_array_q_18, ram_array_q_19) +VARIABLE txt : LINE; + BEGIN + IF (we = '1') THEN + ram_array_d_0 <= data_reg_0; + ram_array_d_1 <= data_reg_1; + ram_array_d_2 <= data_reg_2; + ram_array_d_3 <= data_reg_3; + ram_array_d_4 <= data_reg_4; + ram_array_d_5 <= data_reg_5; + ram_array_d_6 <= data_reg_6; + ram_array_d_7 <= data_reg_7; + ram_array_d_8 <= data_reg_8; + ram_array_d_9 <= data_reg_9; + ram_array_d_10 <= data_reg_10; + ram_array_d_11 <= data_reg_11; + ram_array_d_12 <= data_reg_12; + ram_array_d_13 <= data_reg_13; + ram_array_d_14 <= data_reg_14; + ram_array_d_15 <= data_reg_15; + ram_array_d_16 <= data_reg_16; + ram_array_d_17 <= data_reg_17; + ram_array_d_18 <= data_reg_18; + ram_array_d_19 <= data_reg_19; + ELSE + ram_array_d_0 <= ram_array_q_0; + ram_array_d_1 <= ram_array_q_1; + ram_array_d_2 <= ram_array_q_2; + ram_array_d_3 <= ram_array_q_3; + ram_array_d_4 <= ram_array_q_4; + ram_array_d_5 <= ram_array_q_5; + ram_array_d_6 <= ram_array_q_6; + ram_array_d_7 <= ram_array_q_7; + ram_array_d_8 <= ram_array_q_8; + ram_array_d_9 <= ram_array_q_9; + ram_array_d_10 <= ram_array_q_10; + ram_array_d_11 <= ram_array_q_11; + ram_array_d_12 <= ram_array_q_12; + ram_array_d_13 <= ram_array_q_13; + ram_array_d_14 <= ram_array_q_14; + ram_array_d_15 <= ram_array_q_15; + ram_array_d_16 <= ram_array_q_16; + ram_array_d_17 <= ram_array_q_17; + ram_array_d_18 <= ram_array_q_18; + ram_array_d_19 <= ram_array_q_19; + END IF; + END PROCESS; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_digis_rxclk_gating IS + PORT ( + + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); +END cycloneiv_hssi_rx_digis_rxclk_gating; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_digis_rxclk_gating IS +BEGIN + + clk1out_n <= NOT((select_n OR clk1)); + clk2out_n <= NOT((NOT(select_n) OR clk2)); + +END ARCHITECTURE trans; + + + +-- rxclk_gating + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_digi_rxclk_ctl IS + PORT ( + + -- Clock Inputs + pld_rx_clk : IN STD_LOGIC; -- PLD clock from PLD clock trees + rcvd_clk_pma : IN STD_LOGIC; -- local recovered clock + rcvd_clk0_pma : IN STD_LOGIC; -- channel zero recovered clock + tx_pma_clk : IN STD_LOGIC; -- local TX PMA clock + refclk_pma : IN STD_LOGIC; -- Quad based clk from TXPLL + fref : IN STD_LOGIC; + clklow : IN STD_LOGIC; + + -- Control Inputs + scan_mode : IN STD_LOGIC; -- Scan mode enable signal + -- This is the soft_reset for the RX_PCS + + -- New Control Inputs + gen2ngen1 : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling + gen2ngen1_bundle : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 + rx_div2_sync_centrl : IN STD_LOGIC; -- divided clock from the central channel (x2, x4 mode) + rx_div2_sync_quad_up : IN STD_LOGIC; -- divided clock from quad above (> x4 mode) + rx_div2_sync_quad_down : IN STD_LOGIC; -- divided clock from quad below (> x4 mode) + + -- MDIO Inputs + rrcvd_clk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_1_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_2_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrx_rd_clk_sel : IN STD_LOGIC; -- Select clock for rx ph comp fifo read side + rxrst : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; -- Select between XAUI mode or indiv channel mode + rdwidth_rx : IN STD_LOGIC; -- divide by 1 or 2 before feeding to FIFO write clock + rfreerun_rx : IN STD_LOGIC; -- Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by RX PCS reset + + -- New MDIO Inputs + rauto_speed_ena : IN STD_LOGIC; -- auto speed negotiation enable + rfreq_sel : IN STD_LOGIC; -- freq scaling or data width scaling + rrxpcsclkpwdn : IN STD_LOGIC; -- RX clocking power down enable + rmaster_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rmaster_up_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rself_sw_en_rx : IN STD_LOGIC; -- enables self-switch to have correct /2 clock in all quads in bundle mode + + -- Removed Inputs + -- input rphfifo_master_sel_rx; // RX Phase comp. FIFO rx_div2_sync selection CRAM + -- input rx_div2_sync_in_ch0; // Connect from channel zero rx_div2_sync_out + -- input rx_div2_sync_in_q0_ch0; // Connect from channel zero rx_div2_sync_out of Master Quad + + -- Clock Outputs with CTS + fref_muxed : OUT STD_LOGIC; + clklow_muxed : OUT STD_LOGIC; + rcvd_clk : OUT STD_LOGIC; + clk_1_b : OUT STD_LOGIC; + clk_2_b : OUT STD_LOGIC; + rx_wr_clk : OUT STD_LOGIC; -- drives the rx ph comp fifo write clock tree + rx_rd_clk : OUT STD_LOGIC; -- drives the rx ph comp fifo read clock tree + + -- Clock Outputs to PLD, no CTS + rx_clk : OUT STD_LOGIC; -- drives the PLD clock tree in x1 mode, logically same as rx_wr_clk + rcvd_clk_pma_b : OUT STD_LOGIC; -- debug output clock to PLD + + -- New Clock Outputs with CTS + clk_2_b_raw : OUT STD_LOGIC; -- same as clk_2_b, but with no clock gating + rx_wr_clk_raw : OUT STD_LOGIC; -- same as rx_wr_clk, but with no clock gating + rx_rd_clk_raw : OUT STD_LOGIC; -- same as rx_rd_clk, but with no clock gating + + -- Control Outputs + rx_div2_sync_out : OUT STD_LOGIC -- inverted /2 clock. not used w/new bundling scheme. (left for safety) + ); +END cycloneiv_hssi_rx_digi_rxclk_ctl; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_digi_rxclk_ctl IS + COMPONENT cycloneiv_hssi_rx_digis_rxclk_gating + PORT ( + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); + END COMPONENT; + + SIGNAL rx_clk_2_by2 : STD_LOGIC := '1'; + SIGNAL gen2ngen1_local_sync : STD_LOGIC; + SIGNAL counter : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL rx_div2_sync : STD_LOGIC; + SIGNAL rx_rst_n : STD_LOGIC; + SIGNAL rrcvd_clk_sel_int : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rclk_1_sel_int : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rclk_2_sel_int : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dynamic_div2ndiv1 : STD_LOGIC; + SIGNAL gen2ngen1_local : STD_LOGIC; + SIGNAL rrxpcsclkpwdn_nscan : STD_LOGIC; + SIGNAL rx_div2_this_quad : STD_LOGIC; + SIGNAL rx_div2_this_channel : STD_LOGIC; + SIGNAL rx_div2_other_quad : STD_LOGIC; + SIGNAL force_master : STD_LOGIC; + + SIGNAL select_div1_n : STD_LOGIC; + SIGNAL clk1out_n : STD_LOGIC; + SIGNAL clk2out_n : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL rx_wr_clk_xhdl3 : STD_LOGIC; + SIGNAL clk_2_b_raw_xhdl0 : STD_LOGIC; + SIGNAL rx_wr_clk_raw_xhdl4 : STD_LOGIC; + SIGNAL rx_rd_clk_raw_xhdl2 : STD_LOGIC; + SIGNAL rx_div2_sync_out_xhdl1 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + rx_wr_clk <= rx_wr_clk_xhdl3; + clk_2_b_raw <= clk_2_b_raw_xhdl0; + rx_wr_clk_raw <= rx_wr_clk_raw_xhdl4; + rx_rd_clk_raw <= rx_rd_clk_raw_xhdl2; + rx_div2_sync_out <= rx_div2_sync_out_xhdl1; + + + -- Old bundle logic: + -- Select between the local synchronization signal or the global synchronization signal + --assign rx_div2_sync = rindv_rx ? rx_div2_sync_out : rx_div2_sync_in; + -- assign rx_div2_sync = (rphfifo_master_sel_rx == 1'b0) ? rx_div2_sync_in_q0_ch0 : + -- (rindv_rx == 1'b0) ? rx_div2_sync_in_ch0 : + -- (rauto_speed_ena & ~rfreq_sel) ? (rx_div2_sync_out | ~gen2ngen1_local_sync) : rx_div2_sync_out; + + PROCESS (rxrst, clk_2_b_raw_xhdl0) +VARIABLE txt : LINE; + BEGIN + IF (rxrst = '1') THEN + counter <= TRANSPORT "00" AFTER 1* 1 ps; + ELSIF (clk_2_b_raw_xhdl0'EVENT AND clk_2_b_raw_xhdl0 = '1') THEN + IF (((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_rx) AND NOT(force_master)) = '1') THEN + counter <= TRANSPORT counter + "01" AFTER 1* 1 ps; + END IF; + END IF; + END PROCESS; + + force_master <= '1' WHEN ((counter = "11") AND ((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_rx) = '1')) ELSE + '0'; + + rx_div2_sync <= rx_div2_this_quad WHEN ((rmaster_rx OR force_master) = '1') ELSE + rx_div2_other_quad; + rx_div2_this_quad <= rx_div2_this_channel WHEN ((rindv_rx OR force_master) = '1') ELSE + rx_div2_sync_centrl; + rx_div2_this_channel <= (rx_div2_sync_out_xhdl1 OR NOT(gen2ngen1_local_sync)) WHEN ((rauto_speed_ena AND NOT(rfreq_sel)) = '1') ELSE + rx_div2_sync_out_xhdl1; + rx_div2_other_quad <= rx_div2_sync_quad_up WHEN (rmaster_up_rx = '1') ELSE + rx_div2_sync_quad_down; + + gen2ngen1_local <= gen2ngen1_bundle WHEN (rindv_rx = '0') ELSE + gen2ngen1; + + PROCESS (rxrst, clk_2_b_raw_xhdl0) +VARIABLE txt : LINE; + BEGIN + IF (rxrst = '1') THEN + gen2ngen1_local_sync <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk_2_b_raw_xhdl0'EVENT AND clk_2_b_raw_xhdl0 = '1') THEN + gen2ngen1_local_sync <= TRANSPORT gen2ngen1_local AFTER 1* 1 ps; + END IF; + END PROCESS; + + dynamic_div2ndiv1 <= rdwidth_rx OR (gen2ngen1_local_sync AND rauto_speed_ena AND NOT(rfreq_sel)); + + -- Reset for Divide-by-2 FF and synchronization FF's for clock gating + rx_rst_n <= '1' WHEN (rfreerun_rx = '1') ELSE + NOT(rxrst); + + rrxpcsclkpwdn_nscan <= rrxpcsclkpwdn AND NOT(scan_mode); + + -- clocks are assigned below in the order in which they appear in the out flowing data path + -- RCVD_CLK selection + rrcvd_clk_sel_int <= "01" WHEN (scan_mode = '1') ELSE + rrcvd_clk_sel; + rcvd_clk <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rcvd_clk_pma WHEN (rrcvd_clk_sel_int = "00") ELSE + refclk_pma WHEN (rrcvd_clk_sel_int = "01") ELSE + tx_pma_clk WHEN (rrcvd_clk_sel_int = "10") ELSE + rcvd_clk_pma WHEN (rrcvd_clk_sel_int = "11") ELSE + rcvd_clk_pma; + + -- CLK_1 seleciton + rclk_1_sel_int <= "01" WHEN (scan_mode = '1') ELSE + rclk_1_sel; + clk_1_b <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rcvd_clk_pma WHEN (rclk_1_sel_int = "00") ELSE + refclk_pma WHEN (rclk_1_sel_int = "01") ELSE + tx_pma_clk WHEN (rclk_1_sel_int = "10") ELSE + rcvd_clk0_pma WHEN (rclk_1_sel_int = "11") ELSE + rcvd_clk_pma; + + -- CLK_2 selection + rclk_2_sel_int <= "10" WHEN (scan_mode = '1') ELSE + rclk_2_sel; + clk_2_b_raw_xhdl0 <= rcvd_clk_pma WHEN (rclk_2_sel_int = "00") ELSE + tx_pma_clk WHEN (rclk_2_sel_int = "01") ELSE + refclk_pma WHEN (rclk_2_sel_int = "10") ELSE + rcvd_clk_pma; + --change made for S3GX to remove pld_rx_clk from mux input + --(rclk_2_sel_int == 2'b10) ? refclk_pma : + --(rclk_2_sel_int == 2'b11) ? pld_rx_clk : rcvd_clk_pma; + + clk_2_b <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + clk_2_b_raw_xhdl0; + + -- This register is used to generate divided by two clock. Div by 2 clock starts off high after reset + -- No #1 on this FF as it generates a clock + PROCESS (rx_rst_n, clk_2_b_raw_xhdl0) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_rst_n)) = '1') THEN + rx_clk_2_by2 <= '1'; + ELSIF (clk_2_b_raw_xhdl0'EVENT AND clk_2_b_raw_xhdl0 = '1') THEN + rx_clk_2_by2 <= rx_div2_sync; + END IF; + END PROCESS; + + rx_div2_sync_out_xhdl1 <= NOT(rx_clk_2_by2); + + -- RX FIFO write clock: could be fast or divided by 2 + -- old code: + -- assign rx_wr_clk = ((rdwidth_rx == 1'b0) || scan_mode) ? clk_2_b_raw : rx_clk_2_by2; + + select_div1_n <= NOT((scan_mode OR NOT(dynamic_div2ndiv1))); + + rxclk_gating : cycloneiv_hssi_rx_digis_rxclk_gating + PORT MAP ( + select_n => select_div1_n, + clk1 => clk_2_b_raw_xhdl0, + clk2 => rx_clk_2_by2, + clk1out_n => clk1out_n, + clk2out_n => clk2out_n + ); + + rx_wr_clk_raw_xhdl4 <= NOT((clk1out_n OR clk2out_n)); + + + rx_wr_clk_xhdl3 <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rx_wr_clk_raw_xhdl4; + + -- RX FIFO read clock + rx_rd_clk_raw_xhdl2 <= rx_wr_clk_raw_xhdl4 WHEN ((scan_mode OR int2bit((rrx_rd_clk_sel = '0'))) = '1') ELSE + pld_rx_clk; + rx_rd_clk <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rx_rd_clk_raw_xhdl2; + + -- RX clock out + rx_clk <= rx_wr_clk_xhdl3; -- drives PLD clock tree + + -- Recovered clock for debugging + rcvd_clk_pma_b <= rcvd_clk_pma; -- Goes out to PLD as debug clock. This clock may or may not be routed out to PLD fabric. TBD + + fref_muxed <= refclk_pma WHEN (scan_mode = '1') ELSE + '1' WHEN (rrxpcsclkpwdn = '1') ELSE + fref; + clklow_muxed <= refclk_pma WHEN (scan_mode = '1') ELSE + '1' WHEN (rrxpcsclkpwdn = '1') ELSE + clklow; + +END trans; + + + + +-- rxclk_ctl +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 74 mux21 44 oper_add 1 oper_decoder 1 oper_mux 4 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_auto_speed_neg IS + PORT + ( + config_sel : OUT STD_LOGIC; + config_sel_centrl : IN STD_LOGIC; + config_sel_quad_down : IN STD_LOGIC; + config_sel_quad_up : IN STD_LOGIC; + cs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + dis_pc_byte : OUT STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + pcie_switch : OUT STD_LOGIC; + rate : IN STD_LOGIC; + rauto_deassert_pc_rst_cnt : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + rauto_pc_en_cnt : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + rauto_speed_ena : IN STD_LOGIC; + refclk : IN STD_LOGIC; + reset_pc_ptrs : OUT STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rpma_done_count : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + rwait_for_phfifo_cnt : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + rxpcs_rst_int : IN STD_LOGIC; + singleorbundle : IN STD_LOGIC; + speed_change : OUT STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_auto_speed_neg; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_auto_speed_neg IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n000l43 : STD_LOGIC := '0'; + SIGNAL n000l44 : STD_LOGIC := '0'; + SIGNAL n00ii41 : STD_LOGIC := '0'; + SIGNAL n00ii42 : STD_LOGIC := '0'; + SIGNAL n00il39 : STD_LOGIC := '0'; + SIGNAL n00il40 : STD_LOGIC := '0'; + SIGNAL n00ll37 : STD_LOGIC := '0'; + SIGNAL n00ll38 : STD_LOGIC := '0'; + SIGNAL n00Ol35 : STD_LOGIC := '0'; + SIGNAL n00Ol36 : STD_LOGIC := '0'; + SIGNAL n0i0i31 : STD_LOGIC := '0'; + SIGNAL n0i0i32 : STD_LOGIC := '0'; + SIGNAL n0i0O29 : STD_LOGIC := '0'; + SIGNAL n0i0O30 : STD_LOGIC := '0'; + SIGNAL n0i1i33 : STD_LOGIC := '0'; + SIGNAL n0i1i34 : STD_LOGIC := '0'; + SIGNAL wire_n0i1i34_w_lg_q150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0iil27 : STD_LOGIC := '0'; + SIGNAL n0iil28 : STD_LOGIC := '0'; + SIGNAL n0ili25 : STD_LOGIC := '0'; + SIGNAL n0ili26 : STD_LOGIC := '0'; + SIGNAL wire_n0ili26_w_lg_q120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0ilO23 : STD_LOGIC := '0'; + SIGNAL n0ilO24 : STD_LOGIC := '0'; + SIGNAL wire_n0ilO24_w_lg_w_lg_q114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ilO24_w_lg_q114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0iOl21 : STD_LOGIC := '0'; + SIGNAL n0iOl22 : STD_LOGIC := '0'; + SIGNAL wire_n0iOl22_w_lg_w_lg_q106w107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iOl22_w_lg_q106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0l0i17 : STD_LOGIC := '0'; + SIGNAL n0l0i18 : STD_LOGIC := '0'; + SIGNAL n0l0O15 : STD_LOGIC := '0'; + SIGNAL n0l0O16 : STD_LOGIC := '0'; + SIGNAL wire_n0l0O16_w_lg_q83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0l1i19 : STD_LOGIC := '0'; + SIGNAL n0l1i20 : STD_LOGIC := '0'; + SIGNAL wire_n0l1i20_w_lg_w_lg_q95w96w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l1i20_w_lg_q95w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0lli13 : STD_LOGIC := '0'; + SIGNAL n0lli14 : STD_LOGIC := '0'; + SIGNAL wire_n0lli14_w_lg_q74w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0lOO11 : STD_LOGIC := '0'; + SIGNAL n0lOO12 : STD_LOGIC := '0'; + SIGNAL wire_n0lOO12_w_lg_w_lg_q29w30w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOO12_w_lg_q29w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O0i3 : STD_LOGIC := '0'; + SIGNAL n0O0i4 : STD_LOGIC := '0'; + SIGNAL wire_n0O0i4_w_lg_w_lg_q9w10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O0i4_w_lg_q9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O0l1 : STD_LOGIC := '0'; + SIGNAL n0O0l2 : STD_LOGIC := '0'; + SIGNAL wire_n0O0l2_w_lg_w_lg_q1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O0l2_w_lg_q1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O1i10 : STD_LOGIC := '0'; + SIGNAL wire_n0O1i10_w_lg_w_lg_q21w22w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O1i10_w_lg_q21w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O1i9 : STD_LOGIC := '0'; + SIGNAL n0O1l7 : STD_LOGIC := '0'; + SIGNAL n0O1l8 : STD_LOGIC := '0'; + SIGNAL wire_n0O1l8_w_lg_w_lg_q17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O1l8_w_lg_q17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O1O5 : STD_LOGIC := '0'; + SIGNAL n0O1O6 : STD_LOGIC := '0'; + SIGNAL wire_n0O1O6_w_lg_w_lg_q14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O1O6_w_lg_q14w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n11l : STD_LOGIC := '0'; + SIGNAL wire_n11i_PRN : STD_LOGIC; + SIGNAL wire_n11i_ENA : STD_LOGIC; + SIGNAL n00i : STD_LOGIC := '0'; + SIGNAL n00l : STD_LOGIC := '0'; + SIGNAL n00O : STD_LOGIC := '0'; + SIGNAL n01i : STD_LOGIC := '0'; + SIGNAL n01l : STD_LOGIC := '0'; + SIGNAL n01O : STD_LOGIC := '0'; + SIGNAL n0ii : STD_LOGIC := '0'; + SIGNAL n0il : STD_LOGIC := '0'; + SIGNAL n0iO : STD_LOGIC := '0'; + SIGNAL n0li : STD_LOGIC := '0'; + SIGNAL n0ll : STD_LOGIC := '0'; + SIGNAL n0lO : STD_LOGIC := '0'; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL n10i : STD_LOGIC := '0'; + SIGNAL n10l : STD_LOGIC := '0'; + SIGNAL n11O : STD_LOGIC := '0'; + SIGNAL n1il : STD_LOGIC := '0'; + SIGNAL n1iO : STD_LOGIC := '0'; + SIGNAL n1li : STD_LOGIC := '0'; + SIGNAL n1Ol : STD_LOGIC := '0'; + SIGNAL n1OO : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1O : STD_LOGIC := '0'; + SIGNAL nll0i : STD_LOGIC := '0'; + SIGNAL nlOOi : STD_LOGIC := '0'; + SIGNAL nlOOl : STD_LOGIC := '0'; + SIGNAL nlOOO : STD_LOGIC := '0'; + SIGNAL wire_ni1l_CLRN : STD_LOGIC; + SIGNAL wire_ni1l_w_lg_w118w121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_w_lg_w_lg_w_lg_n1OO93w97w98w102w110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_w_lg_w_lg_n1OO93w97w98w102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_w_lg_n01l104w108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_w_lg_n01O112w116w117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_w_lg_n1OO93w97w98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_n01i100w101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_n01l104w108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_n01O112w116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_w_lg_n1OO93w97w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_n01i100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_n01l104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_n01O112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_n1OO93w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_n1OO129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nO_a : STD_LOGIC_VECTOR (18 DOWNTO 0); + SIGNAL wire_nO_b : STD_LOGIC_VECTOR (18 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_nO_o : STD_LOGIC_VECTOR (18 DOWNTO 0); + SIGNAL wire_nllii_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllii_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nliOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nliOO_o : STD_LOGIC; + SIGNAL wire_nliOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll1i_o : STD_LOGIC; + SIGNAL wire_nll1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll1l_o : STD_LOGIC; + SIGNAL wire_nll1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll1O_o : STD_LOGIC; + SIGNAL wire_nll1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_gen2ngen1148w151w152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_gen2ngen181w84w85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_gen2ngen172w75w76w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_gen2ngen1122w123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_gen2ngen1148w151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_gen2ngen181w84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_gen2ngen172w75w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_gen2ngen177w156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_gen2ngen177w89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_gen2ngen177w78w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_gen2ngen1122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_gen2ngen1148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_gen2ngen181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_gen2ngen172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_gen2ngen177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n001l355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n00lO160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rphfifo_regmode_rx196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rxpcs_rst_int180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n000i : STD_LOGIC; + SIGNAL n001l : STD_LOGIC; + SIGNAL n001O : STD_LOGIC; + SIGNAL n00li : STD_LOGIC; + SIGNAL n00lO : STD_LOGIC; + SIGNAL n00Oi : STD_LOGIC; + SIGNAL n0i1O : STD_LOGIC; + SIGNAL n0l1O : STD_LOGIC; + SIGNAL n0lil : STD_LOGIC; + SIGNAL n0liO : STD_LOGIC; + SIGNAL n0llO : STD_LOGIC; + SIGNAL wire_w_rauto_deassert_pc_rst_cnt_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rauto_deassert_pc_rst_cnt_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rauto_deassert_pc_rst_cnt_range103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rauto_deassert_pc_rst_cnt_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_w_lg_w_lg_w_lg_gen2ngen1148w151w152w(0) <= wire_w_lg_w_lg_gen2ngen1148w151w(0) AND n1Ol; + wire_w_lg_w_lg_w_lg_gen2ngen181w84w85w(0) <= wire_w_lg_w_lg_gen2ngen181w84w(0) AND n1Ol; + wire_w_lg_w_lg_w_lg_gen2ngen172w75w76w(0) <= wire_w_lg_w_lg_gen2ngen172w75w(0) AND n1Ol; + wire_w_lg_w_lg_gen2ngen1122w123w(0) <= wire_w_lg_gen2ngen1122w(0) AND n1Ol; + wire_w_lg_w_lg_gen2ngen1148w151w(0) <= wire_w_lg_gen2ngen1148w(0) AND wire_n0i1i34_w_lg_q150w(0); + wire_w_lg_w_lg_gen2ngen181w84w(0) <= wire_w_lg_gen2ngen181w(0) AND wire_n0l0O16_w_lg_q83w(0); + wire_w_lg_w_lg_gen2ngen172w75w(0) <= wire_w_lg_gen2ngen172w(0) AND wire_n0lli14_w_lg_q74w(0); + wire_w_lg_w_lg_gen2ngen177w156w(0) <= wire_w_lg_gen2ngen177w(0) AND n00Oi; + wire_w_lg_w_lg_gen2ngen177w89w(0) <= wire_w_lg_gen2ngen177w(0) AND n0l1O; + wire_w_lg_w_lg_gen2ngen177w78w(0) <= wire_w_lg_gen2ngen177w(0) AND n0liO; + wire_w_lg_gen2ngen1122w(0) <= gen2ngen1 AND wire_ni1l_w_lg_w118w121w(0); + wire_w_lg_gen2ngen1148w(0) <= gen2ngen1 AND n0i1O; + wire_w_lg_gen2ngen181w(0) <= gen2ngen1 AND n0lil; + wire_w_lg_gen2ngen172w(0) <= gen2ngen1 AND n0llO; + wire_w_lg_gen2ngen177w(0) <= NOT gen2ngen1; + wire_w_lg_n001l355w(0) <= NOT n001l; + wire_w_lg_n00lO160w(0) <= NOT n00lO; + wire_w_lg_rphfifo_regmode_rx196w(0) <= NOT rphfifo_regmode_rx; + wire_w_lg_rxpcs_rst_int180w(0) <= NOT rxpcs_rst_int; + config_sel <= n11l; + cs <= ( nlOOO & nlOOl & nlOOi & nll0i); + dis_pc_byte <= n001O; + n000i <= ((((n1il XOR n10l) XOR (NOT (n000l44 XOR n000l43))) AND rauto_speed_ena) AND singleorbundle); + n001l <= (((((((wire_nllii_o(15) OR wire_nllii_o(14)) OR wire_nllii_o(13)) OR wire_nllii_o(12)) OR wire_nllii_o(11)) OR wire_nllii_o(10)) OR wire_nllii_o(1)) OR wire_nllii_o(0)); + n001O <= (((((wire_nllii_o(7) OR wire_nllii_o(6)) OR wire_nllii_o(5)) OR wire_nllii_o(4)) OR wire_nllii_o(2)) OR wire_nllii_o(3)); + n00li <= '1'; + n00lO <= (((wire_nllii_o(7) OR wire_nllii_o(5)) OR wire_nllii_o(1)) OR wire_nllii_o(9)); + n00Oi <= ((((((((((((((((((NOT (n1Ol XOR rpma_done_count(0))) AND (NOT (n1OO XOR rpma_done_count(1)))) AND (NOT (n01i XOR rpma_done_count(2)))) AND (NOT (n01l XOR rpma_done_count(3)))) AND (NOT (n01O XOR rpma_done_count(4)))) AND (NOT (n00i XOR rpma_done_count(5)))) AND (NOT (n00l XOR rpma_done_count(6)))) AND (NOT (n00O XOR rpma_done_count(7)))) AND (NOT (n0ii XOR rpma_done_count(8)))) AND (NOT (n0il XOR rpma_done_count(9)))) AND (NOT (n0iO XOR rpma_done_count(10)))) AND (NOT (n0li XOR rpma_done_count(11)))) AND (NOT (n0ll XOR rpma_done_count(12)))) AND (NOT (n0lO XOR rpma_done_count(13)))) AND (NOT (n0Oi XOR rpma_done_count(14)))) AND (NOT (n0Ol XOR rpma_done_count(15)))) AND (NOT (n0OO XOR rpma_done_count(16)))) AND (NOT (ni1i XOR rpma_done_count(17)))); + n0i1O <= ((((((((((((((((((NOT (n1OO XOR rpma_done_count(0))) AND (NOT (n01i XOR rpma_done_count(1)))) AND (NOT (n01l XOR rpma_done_count(2)))) AND (NOT (n01O XOR rpma_done_count(3)))) AND (NOT (n00i XOR rpma_done_count(4)))) AND (NOT (n00l XOR rpma_done_count(5)))) AND (NOT (n00O XOR rpma_done_count(6)))) AND (NOT (n0ii XOR rpma_done_count(7)))) AND (NOT (n0il XOR rpma_done_count(8)))) AND (NOT (n0iO XOR rpma_done_count(9)))) AND (NOT (n0li XOR rpma_done_count(10)))) AND (NOT (n0ll XOR rpma_done_count(11)))) AND (NOT (n0lO XOR rpma_done_count(12)))) AND (NOT (n0Oi XOR rpma_done_count(13)))) AND (NOT (n0Ol XOR rpma_done_count(14)))) AND (NOT (n0OO XOR rpma_done_count(15)))) AND (NOT (ni1i XOR rpma_done_count(16)))) AND (NOT (ni1O XOR rpma_done_count(17)))); + n0l1O <= (((((NOT (n1Ol XOR rauto_pc_en_cnt(0))) AND (NOT (n1OO XOR rauto_pc_en_cnt(1)))) AND (NOT (n01i XOR rauto_pc_en_cnt(2)))) AND (NOT (n01l XOR rauto_pc_en_cnt(3)))) AND (NOT (n01O XOR rauto_pc_en_cnt(4)))); + n0lil <= (((((NOT (n1OO XOR rauto_pc_en_cnt(0))) AND (NOT (n01i XOR rauto_pc_en_cnt(1)))) AND (NOT (n01l XOR rauto_pc_en_cnt(2)))) AND (NOT (n01O XOR rauto_pc_en_cnt(3)))) AND (NOT (n00i XOR rauto_pc_en_cnt(4)))); + n0liO <= ((((((NOT (n1Ol XOR rwait_for_phfifo_cnt(0))) AND (NOT (n1OO XOR rwait_for_phfifo_cnt(1)))) AND (NOT (n01i XOR rwait_for_phfifo_cnt(2)))) AND (NOT (n01l XOR rwait_for_phfifo_cnt(3)))) AND (NOT (n01O XOR rwait_for_phfifo_cnt(4)))) AND (NOT (n00i XOR rwait_for_phfifo_cnt(5)))); + n0llO <= ((((((NOT (n1OO XOR rwait_for_phfifo_cnt(0))) AND (NOT (n01i XOR rwait_for_phfifo_cnt(1)))) AND (NOT (n01l XOR rwait_for_phfifo_cnt(2)))) AND (NOT (n01O XOR rwait_for_phfifo_cnt(3)))) AND (NOT (n00i XOR rwait_for_phfifo_cnt(4)))) AND (NOT (n00l XOR rwait_for_phfifo_cnt(5)))); + pcie_switch <= wire_n1ll_dataout; + reset_pc_ptrs <= (((wire_nllii_o(5) OR wire_nllii_o(4)) OR wire_nllii_o(2)) OR wire_nllii_o(3)); + speed_change <= wire_w_lg_n001l355w(0); + wire_w_rauto_deassert_pc_rst_cnt_range92w(0) <= rauto_deassert_pc_rst_cnt(0); + wire_w_rauto_deassert_pc_rst_cnt_range99w(0) <= rauto_deassert_pc_rst_cnt(1); + wire_w_rauto_deassert_pc_rst_cnt_range103w(0) <= rauto_deassert_pc_rst_cnt(2); + wire_w_rauto_deassert_pc_rst_cnt_range111w(0) <= rauto_deassert_pc_rst_cnt(3); + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n000l43 <= n000l44; + END IF; + if (now = 0 ns) then + n000l43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n000l44 <= n000l43; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00ii41 <= n00ii42; + END IF; + if (now = 0 ns) then + n00ii41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00ii42 <= n00ii41; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00il39 <= n00il40; + END IF; + if (now = 0 ns) then + n00il39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00il40 <= n00il39; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00ll37 <= n00ll38; + END IF; + if (now = 0 ns) then + n00ll37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00ll38 <= n00ll37; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00Ol35 <= n00Ol36; + END IF; + if (now = 0 ns) then + n00Ol35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n00Ol36 <= n00Ol35; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0i0i31 <= n0i0i32; + END IF; + if (now = 0 ns) then + n0i0i31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0i0i32 <= n0i0i31; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0i0O29 <= n0i0O30; + END IF; + if (now = 0 ns) then + n0i0O29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0i0O30 <= n0i0O29; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0i1i33 <= n0i1i34; + END IF; + if (now = 0 ns) then + n0i1i33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0i1i34 <= n0i1i33; + END IF; + END PROCESS; + wire_n0i1i34_w_lg_q150w(0) <= n0i1i34 XOR n0i1i33; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0iil27 <= n0iil28; + END IF; + if (now = 0 ns) then + n0iil27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0iil28 <= n0iil27; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0ili25 <= n0ili26; + END IF; + if (now = 0 ns) then + n0ili25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0ili26 <= n0ili25; + END IF; + END PROCESS; + wire_n0ili26_w_lg_q120w(0) <= n0ili26 XOR n0ili25; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0ilO23 <= n0ilO24; + END IF; + if (now = 0 ns) then + n0ilO23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0ilO24 <= n0ilO23; + END IF; + END PROCESS; + wire_n0ilO24_w_lg_w_lg_q114w115w(0) <= NOT wire_n0ilO24_w_lg_q114w(0); + wire_n0ilO24_w_lg_q114w(0) <= n0ilO24 XOR n0ilO23; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0iOl21 <= n0iOl22; + END IF; + if (now = 0 ns) then + n0iOl21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0iOl22 <= n0iOl21; + END IF; + END PROCESS; + wire_n0iOl22_w_lg_w_lg_q106w107w(0) <= NOT wire_n0iOl22_w_lg_q106w(0); + wire_n0iOl22_w_lg_q106w(0) <= n0iOl22 XOR n0iOl21; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0l0i17 <= n0l0i18; + END IF; + if (now = 0 ns) then + n0l0i17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0l0i18 <= n0l0i17; + END IF; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0l0O15 <= n0l0O16; + END IF; + if (now = 0 ns) then + n0l0O15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0l0O16 <= n0l0O15; + END IF; + END PROCESS; + wire_n0l0O16_w_lg_q83w(0) <= n0l0O16 XOR n0l0O15; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0l1i19 <= n0l1i20; + END IF; + if (now = 0 ns) then + n0l1i19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0l1i20 <= n0l1i19; + END IF; + END PROCESS; + wire_n0l1i20_w_lg_w_lg_q95w96w(0) <= NOT wire_n0l1i20_w_lg_q95w(0); + wire_n0l1i20_w_lg_q95w(0) <= n0l1i20 XOR n0l1i19; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0lli13 <= n0lli14; + END IF; + if (now = 0 ns) then + n0lli13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0lli14 <= n0lli13; + END IF; + END PROCESS; + wire_n0lli14_w_lg_q74w(0) <= n0lli14 XOR n0lli13; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0lOO11 <= n0lOO12; + END IF; + if (now = 0 ns) then + n0lOO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0lOO12 <= n0lOO11; + END IF; + END PROCESS; + wire_n0lOO12_w_lg_w_lg_q29w30w(0) <= wire_n0lOO12_w_lg_q29w(0) AND ni1i; + wire_n0lOO12_w_lg_q29w(0) <= n0lOO12 XOR n0lOO11; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O0i3 <= n0O0i4; + END IF; + if (now = 0 ns) then + n0O0i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O0i4 <= n0O0i3; + END IF; + END PROCESS; + wire_n0O0i4_w_lg_w_lg_q9w10w(0) <= wire_n0O0i4_w_lg_q9w(0) AND n00i; + wire_n0O0i4_w_lg_q9w(0) <= n0O0i4 XOR n0O0i3; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O0l1 <= n0O0l2; + END IF; + if (now = 0 ns) then + n0O0l1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O0l2 <= n0O0l1; + END IF; + END PROCESS; + wire_n0O0l2_w_lg_w_lg_q1w2w(0) <= wire_n0O0l2_w_lg_q1w(0) AND n1Ol; + wire_n0O0l2_w_lg_q1w(0) <= n0O0l2 XOR n0O0l1; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O1i10 <= n0O1i9; + END IF; + END PROCESS; + wire_n0O1i10_w_lg_w_lg_q21w22w(0) <= wire_n0O1i10_w_lg_q21w(0) AND n0li; + wire_n0O1i10_w_lg_q21w(0) <= n0O1i10 XOR n0O1i9; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O1i9 <= n0O1i10; + END IF; + if (now = 0 ns) then + n0O1i9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O1l7 <= n0O1l8; + END IF; + if (now = 0 ns) then + n0O1l7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O1l8 <= n0O1l7; + END IF; + END PROCESS; + wire_n0O1l8_w_lg_w_lg_q17w18w(0) <= wire_n0O1l8_w_lg_q17w(0) AND n0il; + wire_n0O1l8_w_lg_q17w(0) <= n0O1l8 XOR n0O1l7; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O1O5 <= n0O1O6; + END IF; + if (now = 0 ns) then + n0O1O5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (refclk) + BEGIN + IF (refclk = '1' AND refclk'event) THEN n0O1O6 <= n0O1O5; + END IF; + END PROCESS; + wire_n0O1O6_w_lg_w_lg_q14w15w(0) <= wire_n0O1O6_w_lg_q14w(0) AND n0ii; + wire_n0O1O6_w_lg_q14w(0) <= n0O1O6 XOR n0O1O5; + PROCESS (refclk, wire_n11i_PRN, rxpcs_rst_int) + BEGIN + IF (wire_n11i_PRN = '0') THEN + n11l <= '1'; + ELSIF (rxpcs_rst_int = '1') THEN + n11l <= '0'; + ELSIF (refclk = '1' AND refclk'event) THEN + IF (wire_nllii_o(3) = '1') THEN + n11l <= n1il; + END IF; + END IF; + END PROCESS; + wire_n11i_ENA <= wire_nllii_o(3); + wire_n11i_PRN <= (n00ii42 XOR n00ii41); + PROCESS (refclk, wire_ni1l_CLRN) + BEGIN + IF (wire_ni1l_CLRN = '0') THEN + n00i <= '0'; + n00l <= '0'; + n00O <= '0'; + n01i <= '0'; + n01l <= '0'; + n01O <= '0'; + n0ii <= '0'; + n0il <= '0'; + n0iO <= '0'; + n0li <= '0'; + n0ll <= '0'; + n0lO <= '0'; + n0Oi <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + n10i <= '0'; + n10l <= '0'; + n11O <= '0'; + n1il <= '0'; + n1iO <= '0'; + n1li <= '0'; + n1Ol <= '0'; + n1OO <= '0'; + ni1i <= '0'; + ni1O <= '0'; + nll0i <= '0'; + nlOOi <= '0'; + nlOOl <= '0'; + nlOOO <= '0'; + ELSIF (refclk = '1' AND refclk'event) THEN + n00i <= wire_nili_dataout; + n00l <= wire_nill_dataout; + n00O <= wire_nilO_dataout; + n01i <= wire_niii_dataout; + n01l <= wire_niil_dataout; + n01O <= wire_niiO_dataout; + n0ii <= wire_niOi_dataout; + n0il <= wire_niOl_dataout; + n0iO <= wire_niOO_dataout; + n0li <= wire_nl1i_dataout; + n0ll <= wire_nl1l_dataout; + n0lO <= wire_nl1O_dataout; + n0Oi <= wire_nl0i_dataout; + n0Ol <= wire_nl0l_dataout; + n0OO <= wire_nl0O_dataout; + n10i <= gen2ngen1; + n10l <= n1il; + n11O <= ((n10i XOR gen2ngen1) XOR (NOT (n00il40 XOR n00il39))); + n1il <= n1iO; + n1iO <= rate; + n1li <= wire_ni0i_dataout; + n1Ol <= wire_ni0l_dataout; + n1OO <= wire_ni0O_dataout; + ni1i <= wire_nlii_dataout; + ni1O <= wire_nlil_dataout; + nll0i <= wire_nliOO_o; + nlOOi <= wire_nll1i_o; + nlOOl <= wire_nll1l_o; + nlOOO <= wire_nll1O_o; + END IF; + END PROCESS; + wire_ni1l_CLRN <= ((n00ll38 XOR n00ll37) AND wire_w_lg_rxpcs_rst_int180w(0)); + wire_ni1l_w_lg_w118w121w(0) <= wire_ni1l_w118w(0) AND wire_n0ili26_w_lg_q120w(0); + wire_ni1l_w118w(0) <= wire_ni1l_w_lg_w_lg_w_lg_w_lg_w_lg_n1OO93w97w98w102w110w(0) AND wire_ni1l_w_lg_w_lg_w_lg_n01O112w116w117w(0); + wire_ni1l_w_lg_w_lg_w_lg_w_lg_w_lg_n1OO93w97w98w102w110w(0) <= wire_ni1l_w_lg_w_lg_w_lg_w_lg_n1OO93w97w98w102w(0) AND wire_ni1l_w_lg_w_lg_w_lg_n01l104w108w109w(0); + wire_ni1l_w_lg_w_lg_w_lg_w_lg_n1OO93w97w98w102w(0) <= wire_ni1l_w_lg_w_lg_w_lg_n1OO93w97w98w(0) AND wire_ni1l_w_lg_w_lg_n01i100w101w(0); + wire_ni1l_w_lg_w_lg_w_lg_n01l104w108w109w(0) <= NOT wire_ni1l_w_lg_w_lg_n01l104w108w(0); + wire_ni1l_w_lg_w_lg_w_lg_n01O112w116w117w(0) <= NOT wire_ni1l_w_lg_w_lg_n01O112w116w(0); + wire_ni1l_w_lg_w_lg_w_lg_n1OO93w97w98w(0) <= NOT wire_ni1l_w_lg_w_lg_n1OO93w97w(0); + wire_ni1l_w_lg_w_lg_n01i100w101w(0) <= NOT wire_ni1l_w_lg_n01i100w(0); + wire_ni1l_w_lg_w_lg_n01l104w108w(0) <= wire_ni1l_w_lg_n01l104w(0) XOR wire_n0iOl22_w_lg_w_lg_q106w107w(0); + wire_ni1l_w_lg_w_lg_n01O112w116w(0) <= wire_ni1l_w_lg_n01O112w(0) XOR wire_n0ilO24_w_lg_w_lg_q114w115w(0); + wire_ni1l_w_lg_w_lg_n1OO93w97w(0) <= wire_ni1l_w_lg_n1OO93w(0) XOR wire_n0l1i20_w_lg_w_lg_q95w96w(0); + wire_ni1l_w_lg_n01i100w(0) <= n01i XOR wire_w_rauto_deassert_pc_rst_cnt_range99w(0); + wire_ni1l_w_lg_n01l104w(0) <= n01l XOR wire_w_rauto_deassert_pc_rst_cnt_range103w(0); + wire_ni1l_w_lg_n01O112w(0) <= n01O XOR wire_w_rauto_deassert_pc_rst_cnt_range111w(0); + wire_ni1l_w_lg_n1OO93w(0) <= n1OO XOR wire_w_rauto_deassert_pc_rst_cnt_range92w(0); + wire_ni1l_w_lg_n1OO129w(0) <= n1OO XOR wire_w_rauto_deassert_pc_rst_cnt_range99w(0); + wire_n1ll_dataout <= wire_n1Oi_dataout WHEN rmaster_rx = '1' ELSE wire_n1lO_dataout; + wire_n1lO_dataout <= config_sel_quad_up WHEN rmaster_up_rx = '1' ELSE config_sel_quad_down; + wire_n1Oi_dataout <= n11l WHEN rindv_rx = '1' ELSE config_sel_centrl; + wire_ni0i_dataout <= wire_nliO_dataout AND NOT(wire_w_lg_n00lO160w(0)); + wire_ni0l_dataout <= wire_nO_o(0) AND NOT(wire_w_lg_n00lO160w(0)); + wire_ni0O_dataout <= wire_nO_o(1) AND NOT(wire_w_lg_n00lO160w(0)); + wire_niii_dataout <= wire_nO_o(2) AND NOT(wire_w_lg_n00lO160w(0)); + wire_niil_dataout <= wire_nO_o(3) AND NOT(wire_w_lg_n00lO160w(0)); + wire_niiO_dataout <= wire_nO_o(4) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nili_dataout <= wire_nO_o(5) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nill_dataout <= wire_nO_o(6) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nilO_dataout <= wire_nO_o(7) AND NOT(wire_w_lg_n00lO160w(0)); + wire_niOi_dataout <= wire_nO_o(8) AND NOT(wire_w_lg_n00lO160w(0)); + wire_niOl_dataout <= wire_nO_o(9) AND NOT(wire_w_lg_n00lO160w(0)); + wire_niOO_dataout <= wire_nO_o(10) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nl0i_dataout <= wire_nO_o(14) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nl0l_dataout <= wire_nO_o(15) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nl0O_dataout <= wire_nO_o(16) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nl1i_dataout <= wire_nO_o(11) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nl1l_dataout <= wire_nO_o(12) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nl1O_dataout <= wire_nO_o(13) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nlii_dataout <= wire_nO_o(17) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nlil_dataout <= wire_nO_o(18) AND NOT(wire_w_lg_n00lO160w(0)); + wire_nliO_dataout <= wire_nlli_dataout OR n1li; + wire_nlli_dataout <= ((wire_w_lg_w_lg_w_lg_gen2ngen1148w151w152w(0) AND (n00Ol36 XOR n00Ol35)) OR wire_w_lg_w_lg_gen2ngen177w156w(0)) WHEN wire_nllii_o(5) = '1' ELSE wire_nlll_dataout; + wire_nlll_dataout <= ((wire_w_lg_w_lg_gen2ngen1122w123w(0) AND (n0iil28 XOR n0iil27)) OR (wire_w_lg_gen2ngen177w(0) AND (((((NOT (n1Ol XOR rauto_deassert_pc_rst_cnt(0))) AND (NOT (wire_ni1l_w_lg_n1OO129w(0) XOR (NOT (n0i0O30 XOR n0i0O29))))) AND (NOT (n01i XOR rauto_deassert_pc_rst_cnt(2)))) AND (NOT (n01l XOR rauto_deassert_pc_rst_cnt(3)))) AND (n0i0i32 XOR n0i0i31)))) WHEN wire_nllii_o(7) = '1' ELSE wire_nllO_dataout; + wire_nllli_dataout <= nll0i AND NOT(n1li); + wire_nllll_dataout <= nlOOi OR n1li; + wire_nlllO_dataout <= nlOOl AND NOT(n1li); + wire_nllO_dataout <= ((wire_w_lg_w_lg_w_lg_gen2ngen181w84w85w(0) AND (n0l0i18 XOR n0l0i17)) OR wire_w_lg_w_lg_gen2ngen177w89w(0)) WHEN wire_nllii_o(9) = '1' ELSE wire_nlOi_dataout; + wire_nllOi_dataout <= nlOOO OR n1li; + wire_nllOl_dataout <= nlOOi AND NOT(n1li); + wire_nllOO_dataout <= wire_w_lg_rphfifo_regmode_rx196w(0) WHEN n1li = '1' ELSE nlOOl; + wire_nlO0i_dataout <= nlOOl OR n11O; + wire_nlO0l_dataout <= nlOOO AND NOT(n11O); + wire_nlO0O_dataout <= nlOOO AND NOT(n1li); + wire_nlO1i_dataout <= rphfifo_regmode_rx WHEN n1li = '1' ELSE nlOOO; + wire_nlO1l_dataout <= nll0i OR n11O; + wire_nlO1O_dataout <= nlOOi AND NOT(n11O); + wire_nlOi_dataout <= (wire_w_lg_w_lg_w_lg_gen2ngen172w75w76w(0) OR wire_w_lg_w_lg_gen2ngen177w78w(0)) WHEN wire_nllii_o(1) = '1' ELSE n1li; + wire_nlOii_dataout <= nll0i OR n000i; + wire_nlOil_dataout <= rphfifo_regmode_rx WHEN n000i = '1' ELSE nlOOi; + wire_nlOiO_dataout <= nlOOl AND NOT(n000i); + wire_nlOli_dataout <= nlOOO AND NOT(n000i); + wire_nO_a <= ( ni1O & wire_n0lOO12_w_lg_w_lg_q29w30w & n0OO & n0Ol & n0Oi & n0lO & n0ll & wire_n0O1i10_w_lg_w_lg_q21w22w & n0iO & wire_n0O1l8_w_lg_w_lg_q17w18w & wire_n0O1O6_w_lg_w_lg_q14w15w & n00O & n00l & wire_n0O0i4_w_lg_w_lg_q9w10w & n01O & n01l & n01i & n1OO & wire_n0O0l2_w_lg_w_lg_q1w2w); + wire_nO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 19, + width_b => 19, + width_o => 19 + ) + PORT MAP ( + a => wire_nO_a, + b => wire_nO_b, + cin => wire_gnd, + o => wire_nO_o + ); + wire_nllii_i <= ( nlOOO & nlOOl & nlOOi & nll0i); + nllii : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nllii_i, + o => wire_nllii_o + ); + wire_nliOO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nllli_dataout & "1" & wire_nllli_dataout & "1" & wire_nllli_dataout & wire_nlO1l_dataout & "0" & "1" & wire_nllli_dataout & wire_nlOii_dataout); + wire_nliOO_sel <= ( nlOOO & nlOOl & nlOOi & nll0i); + nliOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nliOO_data, + o => wire_nliOO_o, + sel => wire_nliOO_sel + ); + wire_nll1i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nllll_dataout & "0" & wire_nllOl_dataout & "1" & wire_nllll_dataout & wire_nlO1O_dataout & "0" & "1" & wire_nllll_dataout & wire_nlOil_dataout); + wire_nll1i_sel <= ( nlOOO & nlOOl & nlOOi & nll0i); + nll1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll1i_data, + o => wire_nll1i_o, + sel => wire_nll1i_sel + ); + wire_nll1l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nlllO_dataout & "0" & wire_nlllO_dataout & "1" & wire_nllOO_dataout & wire_nlO0i_dataout & "1" & "0" & wire_nlllO_dataout & wire_nlOiO_dataout); + wire_nll1l_sel <= ( nlOOO & nlOOl & nlOOi & nll0i); + nll1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll1l_data, + o => wire_nll1l_o, + sel => wire_nll1l_sel + ); + wire_nll1O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nllOi_dataout & "1" & wire_nllOi_dataout & "0" & wire_nlO1i_dataout & wire_nlO0l_dataout & "0" & "0" & wire_nlO0O_dataout & wire_nlOli_dataout); + wire_nll1O_sel <= ( nlOOO & nlOOl & nlOOi & nll0i); + nll1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll1O_data, + o => wire_nll1O_o, + sel => wire_nll1O_sel + ); + + END RTL; --cycloneiv_hssi_rx_digi_auto_speed_neg +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 149 mux21 612 oper_add 8 oper_decoder 4 oper_mux 37 oper_selector 4 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_bist_ver IS + PORT + ( + bistdone : OUT STD_LOGIC; + bisterr : OUT STD_LOGIC; + clk_2 : IN STD_LOGIC; + cur_state : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + err_ctl : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + err_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + prbs_done : IN STD_LOGIC; + prbs_err : IN STD_LOGIC; + rbist_clr_rx : IN STD_LOGIC; + rbist_sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rbisten_rx : IN STD_LOGIC; + rcxpat_chnl_sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rdwidth_rx : IN STD_LOGIC; + rpma_doublewidth_rx : IN STD_LOGIC; + rpmadwidth_rx : IN STD_LOGIC; + rxc : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + rxd : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + selftest_done : OUT STD_LOGIC; + selftest_err : OUT STD_LOGIC; + soft_reset : IN STD_LOGIC; + sync_status : IN STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_bist_ver; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_bist_ver IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n0li1O47 : STD_LOGIC := '0'; + SIGNAL n0li1O48 : STD_LOGIC := '0'; + SIGNAL n0lOOi45 : STD_LOGIC := '0'; + SIGNAL n0lOOi46 : STD_LOGIC := '0'; + SIGNAL wire_n0lOOi46_w_lg_w_lg_q339w340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOOi46_w_lg_q339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0lOOl43 : STD_LOGIC := '0'; + SIGNAL n0lOOl44 : STD_LOGIC := '0'; + SIGNAL wire_n0lOOl44_w_lg_w_lg_q314w315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOOl44_w_lg_q314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0lOOO41 : STD_LOGIC := '0'; + SIGNAL n0lOOO42 : STD_LOGIC := '0'; + SIGNAL wire_n0lOOO42_w_lg_w_lg_q309w310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOOO42_w_lg_q309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O10i33 : STD_LOGIC := '0'; + SIGNAL n0O10i34 : STD_LOGIC := '0'; + SIGNAL wire_n0O10i34_w_lg_w_lg_q186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O10i34_w_lg_q186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O10l31 : STD_LOGIC := '0'; + SIGNAL n0O10l32 : STD_LOGIC := '0'; + SIGNAL wire_n0O10l32_w_lg_w_lg_q177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O10l32_w_lg_q177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O10O29 : STD_LOGIC := '0'; + SIGNAL n0O10O30 : STD_LOGIC := '0'; + SIGNAL wire_n0O10O30_w_lg_w_lg_q174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O10O30_w_lg_q174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O11i39 : STD_LOGIC := '0'; + SIGNAL n0O11i40 : STD_LOGIC := '0'; + SIGNAL wire_n0O11i40_w_lg_w_lg_q303w304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O11i40_w_lg_q303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O11l37 : STD_LOGIC := '0'; + SIGNAL n0O11l38 : STD_LOGIC := '0'; + SIGNAL wire_n0O11l38_w_lg_w_lg_q237w238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O11l38_w_lg_q237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O11O35 : STD_LOGIC := '0'; + SIGNAL n0O11O36 : STD_LOGIC := '0'; + SIGNAL wire_n0O11O36_w_lg_w_lg_q191w192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O11O36_w_lg_q191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O1ii27 : STD_LOGIC := '0'; + SIGNAL n0O1ii28 : STD_LOGIC := '0'; + SIGNAL wire_n0O1ii28_w_lg_w_lg_q159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O1ii28_w_lg_q159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O1Ol25 : STD_LOGIC := '0'; + SIGNAL n0O1Ol26 : STD_LOGIC := '0'; + SIGNAL n0Oi0O21 : STD_LOGIC := '0'; + SIGNAL n0Oi0O22 : STD_LOGIC := '0'; + SIGNAL wire_n0Oi0O22_w_lg_w_lg_q116w117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0Oi0O22_w_lg_q116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0Oi1O23 : STD_LOGIC := '0'; + SIGNAL n0Oi1O24 : STD_LOGIC := '0'; + SIGNAL n0OiOi19 : STD_LOGIC := '0'; + SIGNAL n0OiOi20 : STD_LOGIC := '0'; + SIGNAL n0OiOO17 : STD_LOGIC := '0'; + SIGNAL n0OiOO18 : STD_LOGIC := '0'; + SIGNAL n0Ol0i11 : STD_LOGIC := '0'; + SIGNAL n0Ol0i12 : STD_LOGIC := '0'; + SIGNAL n0Ol0O10 : STD_LOGIC := '0'; + SIGNAL n0Ol0O9 : STD_LOGIC := '0'; + SIGNAL n0Ol1i15 : STD_LOGIC := '0'; + SIGNAL n0Ol1i16 : STD_LOGIC := '0'; + SIGNAL n0Ol1l13 : STD_LOGIC := '0'; + SIGNAL n0Ol1l14 : STD_LOGIC := '0'; + SIGNAL n0Olil7 : STD_LOGIC := '0'; + SIGNAL n0Olil8 : STD_LOGIC := '0'; + SIGNAL n0OlOO5 : STD_LOGIC := '0'; + SIGNAL n0OlOO6 : STD_LOGIC := '0'; + SIGNAL n0OO0i1 : STD_LOGIC := '0'; + SIGNAL n0OO0i2 : STD_LOGIC := '0'; + SIGNAL n0OO1l3 : STD_LOGIC := '0'; + SIGNAL n0OO1l4 : STD_LOGIC := '0'; + SIGNAL ni00i : STD_LOGIC := '0'; + SIGNAL ni01l : STD_LOGIC := '0'; + SIGNAL ni1lOl : STD_LOGIC := '0'; + SIGNAL niiilO : STD_LOGIC := '0'; + SIGNAL niiiOi : STD_LOGIC := '0'; + SIGNAL niiiOl : STD_LOGIC := '0'; + SIGNAL niiiOO : STD_LOGIC := '0'; + SIGNAL niil0i : STD_LOGIC := '0'; + SIGNAL niil0l : STD_LOGIC := '0'; + SIGNAL niil0O : STD_LOGIC := '0'; + SIGNAL niil1i : STD_LOGIC := '0'; + SIGNAL niil1l : STD_LOGIC := '0'; + SIGNAL niil1O : STD_LOGIC := '0'; + SIGNAL niilii : STD_LOGIC := '0'; + SIGNAL niilil : STD_LOGIC := '0'; + SIGNAL niiliO : STD_LOGIC := '0'; + SIGNAL niilli : STD_LOGIC := '0'; + SIGNAL niilll : STD_LOGIC := '0'; + SIGNAL niillO : STD_LOGIC := '0'; + SIGNAL niilOi : STD_LOGIC := '0'; + SIGNAL niilOl : STD_LOGIC := '0'; + SIGNAL niiO1i : STD_LOGIC := '0'; + SIGNAL niiO1l : STD_LOGIC := '0'; + SIGNAL nll00O : STD_LOGIC := '0'; + SIGNAL nll0ii : STD_LOGIC := '0'; + SIGNAL wire_ni01O_CLRN : STD_LOGIC; + SIGNAL n11Oi : STD_LOGIC := '0'; + SIGNAL ni00l : STD_LOGIC := '0'; + SIGNAL ni00O : STD_LOGIC := '0'; + SIGNAL ni01i : STD_LOGIC := '0'; + SIGNAL ni0ii : STD_LOGIC := '0'; + SIGNAL ni0il : STD_LOGIC := '0'; + SIGNAL ni0iO : STD_LOGIC := '0'; + SIGNAL ni0li : STD_LOGIC := '0'; + SIGNAL ni0ll : STD_LOGIC := '0'; + SIGNAL ni0lO : STD_LOGIC := '0'; + SIGNAL ni0Oi : STD_LOGIC := '0'; + SIGNAL ni0Ol : STD_LOGIC := '0'; + SIGNAL nii1i : STD_LOGIC := '0'; + SIGNAL niilOO : STD_LOGIC := '0'; + SIGNAL niiO0l : STD_LOGIC := '0'; + SIGNAL niiO0O : STD_LOGIC := '0'; + SIGNAL niiOii : STD_LOGIC := '0'; + SIGNAL niiOil : STD_LOGIC := '0'; + SIGNAL niiOiO : STD_LOGIC := '0'; + SIGNAL niiOli : STD_LOGIC := '0'; + SIGNAL niiOll : STD_LOGIC := '0'; + SIGNAL niiOlO : STD_LOGIC := '0'; + SIGNAL niiOOi : STD_LOGIC := '0'; + SIGNAL niiOOl : STD_LOGIC := '0'; + SIGNAL niiOOO : STD_LOGIC := '0'; + SIGNAL nil00i : STD_LOGIC := '0'; + SIGNAL nil00l : STD_LOGIC := '0'; + SIGNAL nil00O : STD_LOGIC := '0'; + SIGNAL nil01i : STD_LOGIC := '0'; + SIGNAL nil01l : STD_LOGIC := '0'; + SIGNAL nil01O : STD_LOGIC := '0'; + SIGNAL nil10i : STD_LOGIC := '0'; + SIGNAL nil10l : STD_LOGIC := '0'; + SIGNAL nil10O : STD_LOGIC := '0'; + SIGNAL nil11i : STD_LOGIC := '0'; + SIGNAL nil11l : STD_LOGIC := '0'; + SIGNAL nil11O : STD_LOGIC := '0'; + SIGNAL nil1ii : STD_LOGIC := '0'; + SIGNAL nil1il : STD_LOGIC := '0'; + SIGNAL nil1iO : STD_LOGIC := '0'; + SIGNAL nil1li : STD_LOGIC := '0'; + SIGNAL nil1ll : STD_LOGIC := '0'; + SIGNAL nil1lO : STD_LOGIC := '0'; + SIGNAL nil1Oi : STD_LOGIC := '0'; + SIGNAL nil1Ol : STD_LOGIC := '0'; + SIGNAL nil1OO : STD_LOGIC := '0'; + SIGNAL nl1Oll : STD_LOGIC := '0'; + SIGNAL nll00l : STD_LOGIC := '0'; + SIGNAL nll0il : STD_LOGIC := '0'; + SIGNAL nll0iO : STD_LOGIC := '0'; + SIGNAL nll0li : STD_LOGIC := '0'; + SIGNAL nll0ll : STD_LOGIC := '0'; + SIGNAL nll0lO : STD_LOGIC := '0'; + SIGNAL nll0Oi : STD_LOGIC := '0'; + SIGNAL nll0Ol : STD_LOGIC := '0'; + SIGNAL nll0OO : STD_LOGIC := '0'; + SIGNAL nlli0i : STD_LOGIC := '0'; + SIGNAL nlli0l : STD_LOGIC := '0'; + SIGNAL nlli0O : STD_LOGIC := '0'; + SIGNAL nlli1i : STD_LOGIC := '0'; + SIGNAL nlli1l : STD_LOGIC := '0'; + SIGNAL nlli1O : STD_LOGIC := '0'; + SIGNAL nlliii : STD_LOGIC := '0'; + SIGNAL nlliil : STD_LOGIC := '0'; + SIGNAL nlliiO : STD_LOGIC := '0'; + SIGNAL nllili : STD_LOGIC := '0'; + SIGNAL nllill : STD_LOGIC := '0'; + SIGNAL nllilO : STD_LOGIC := '0'; + SIGNAL nlliOi : STD_LOGIC := '0'; + SIGNAL nlliOl : STD_LOGIC := '0'; + SIGNAL nlliOO : STD_LOGIC := '0'; + SIGNAL nlll0i : STD_LOGIC := '0'; + SIGNAL nlll1i : STD_LOGIC := '0'; + SIGNAL nlll1l : STD_LOGIC := '0'; + SIGNAL nlll1O : STD_LOGIC := '0'; + SIGNAL wire_ni0OO_CLRN : STD_LOGIC; + SIGNAL wire_ni0OO_PRN : STD_LOGIC; + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_w1242w1243w1244w1245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w1251w1252w1253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w1242w1243w1244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w1251w1252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w1242w1243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w1251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w1242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlliOO1247w1248w1249w1250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlli0O990w992w993w994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlliOO1222w1238w1240w1241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_ni0li837w838w839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_nil1Oi2312w2314w2315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_nlli0O995w996w997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1247w1248w1249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_nlli0O990w992w993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1222w1224w1225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1222w1238w1240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_ni0li837w838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_nil1Oi2312w2314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_nlli0O995w996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_nlliOO1247w1248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_nll0Ol1343w1344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_nlli0O990w992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_nlliOO1222w1224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_w_lg_nlliOO1222w1238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_ni0li837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil1Oi2312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nll0Ol1352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlli0O995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlliOO1247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_ni00O840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil10l2331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil10O2322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil1ii2320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil1il2318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil1iO2316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil1li2325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil1ll2313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nil1lO2311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nll0ll1347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nll0lO1345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nll0Oi1351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nll0Ol1343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlli0l991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlli0O990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlli1l1296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlli1O1273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlliii1236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlliil1234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlliiO1232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nllili1230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nllill1228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nllilO1226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlliOi1239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlliOl1223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0OO_w_lg_nlliOO1222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niiO0i : STD_LOGIC := '0'; + SIGNAL wire_niiO1O_CLRN : STD_LOGIC; + SIGNAL wire_n000i_dataout : STD_LOGIC; + SIGNAL wire_n000l_dataout : STD_LOGIC; + SIGNAL wire_n000O_dataout : STD_LOGIC; + SIGNAL wire_n001i_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001O_dataout : STD_LOGIC; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00ii_dataout : STD_LOGIC; + SIGNAL wire_n00il_dataout : STD_LOGIC; + SIGNAL wire_n00iO_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00li_dataout : STD_LOGIC; + SIGNAL wire_n00ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n010i_dataout : STD_LOGIC; + SIGNAL wire_n010l_dataout : STD_LOGIC; + SIGNAL wire_n010O_dataout : STD_LOGIC; + SIGNAL wire_n011i_dataout : STD_LOGIC; + SIGNAL wire_n011l_dataout : STD_LOGIC; + SIGNAL wire_n011O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01lO_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0iii_dataout : STD_LOGIC; + SIGNAL wire_n0iil_dataout : STD_LOGIC; + SIGNAL wire_n0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0lii_dataout : STD_LOGIC; + SIGNAL wire_n0lil_dataout : STD_LOGIC; + SIGNAL wire_n0liO_dataout : STD_LOGIC; + SIGNAL wire_n0lli_dataout : STD_LOGIC; + SIGNAL wire_n0lll_dataout : STD_LOGIC; + SIGNAL wire_n0llO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOO_dataout : STD_LOGIC; + SIGNAL wire_n100O_dataout : STD_LOGIC; + SIGNAL wire_n10ii_dataout : STD_LOGIC; + SIGNAL wire_n10il_dataout : STD_LOGIC; + SIGNAL wire_n10iO_dataout : STD_LOGIC; + SIGNAL wire_n10li_dataout : STD_LOGIC; + SIGNAL wire_n10ll_dataout : STD_LOGIC; + SIGNAL wire_n10lO_dataout : STD_LOGIC; + SIGNAL wire_n10Oi_dataout : STD_LOGIC; + SIGNAL wire_n10Ol_dataout : STD_LOGIC; + SIGNAL wire_n10OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1iii_dataout : STD_LOGIC; + SIGNAL wire_n1iil_dataout : STD_LOGIC; + SIGNAL wire_n1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1ili_dataout : STD_LOGIC; + SIGNAL wire_n1ill_dataout : STD_LOGIC; + SIGNAL wire_n1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1lii_dataout : STD_LOGIC; + SIGNAL wire_n1lil_dataout : STD_LOGIC; + SIGNAL wire_n1liO_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lli_dataout : STD_LOGIC; + SIGNAL wire_n1lll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni_dataout : STD_LOGIC; + SIGNAL wire_ni_w_lg_dataout403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_dataout153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni000i_dataout : STD_LOGIC; + SIGNAL wire_ni000l_dataout : STD_LOGIC; + SIGNAL wire_ni000O_dataout : STD_LOGIC; + SIGNAL wire_ni001i_dataout : STD_LOGIC; + SIGNAL wire_ni001l_dataout : STD_LOGIC; + SIGNAL wire_ni001O_dataout : STD_LOGIC; + SIGNAL wire_ni00il_dataout : STD_LOGIC; + SIGNAL wire_ni00iO_dataout : STD_LOGIC; + SIGNAL wire_ni00ll_dataout : STD_LOGIC; + SIGNAL wire_ni00lO_dataout : STD_LOGIC; + SIGNAL wire_ni00Ol_dataout : STD_LOGIC; + SIGNAL wire_ni00OO_dataout : STD_LOGIC; + SIGNAL wire_ni010i_dataout : STD_LOGIC; + SIGNAL wire_ni010l_dataout : STD_LOGIC; + SIGNAL wire_ni010O_dataout : STD_LOGIC; + SIGNAL wire_ni011l_dataout : STD_LOGIC; + SIGNAL wire_ni011O_dataout : STD_LOGIC; + SIGNAL wire_ni01ii_dataout : STD_LOGIC; + SIGNAL wire_ni01il_dataout : STD_LOGIC; + SIGNAL wire_ni01li_dataout : STD_LOGIC; + SIGNAL wire_ni01ll_dataout : STD_LOGIC; + SIGNAL wire_ni01Oi_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0i0i_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l_dataout : STD_LOGIC; + SIGNAL wire_ni0i1i_dataout : STD_LOGIC; + SIGNAL wire_ni0i1l_dataout : STD_LOGIC; + SIGNAL wire_ni0i1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iii_dataout : STD_LOGIC; + SIGNAL wire_ni0iil_dataout : STD_LOGIC; + SIGNAL wire_ni0ili_dataout : STD_LOGIC; + SIGNAL wire_ni0ill_dataout : STD_LOGIC; + SIGNAL wire_ni0iOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i_dataout : STD_LOGIC; + SIGNAL wire_ni0l1l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O_dataout : STD_LOGIC; + SIGNAL wire_ni0lil_dataout : STD_LOGIC; + SIGNAL wire_ni0liO_dataout : STD_LOGIC; + SIGNAL wire_ni0lli_dataout : STD_LOGIC; + SIGNAL wire_ni0lll_dataout : STD_LOGIC; + SIGNAL wire_ni0llO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O0i_dataout : STD_LOGIC; + SIGNAL wire_ni0O0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O1i_dataout : STD_LOGIC; + SIGNAL wire_ni0O1l_dataout : STD_LOGIC; + SIGNAL wire_ni0O1O_dataout : STD_LOGIC; + SIGNAL wire_ni0OiO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli_dataout : STD_LOGIC; + SIGNAL wire_ni0Oll_dataout : STD_LOGIC; + SIGNAL wire_ni0OlO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OOO_dataout : STD_LOGIC; + SIGNAL wire_ni10i_dataout : STD_LOGIC; + SIGNAL wire_ni10l_dataout : STD_LOGIC; + SIGNAL wire_ni10O_dataout : STD_LOGIC; + SIGNAL wire_ni11i_dataout : STD_LOGIC; + SIGNAL wire_ni11l_dataout : STD_LOGIC; + SIGNAL wire_ni11O_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1il_dataout : STD_LOGIC; + SIGNAL wire_ni1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l1O_dataout : STD_LOGIC; + SIGNAL wire_ni1lii_dataout : STD_LOGIC; + SIGNAL wire_ni1lil_dataout : STD_LOGIC; + SIGNAL wire_ni1liO_dataout : STD_LOGIC; + SIGNAL wire_ni1lli_dataout : STD_LOGIC; + SIGNAL wire_ni1lll_dataout : STD_LOGIC; + SIGNAL wire_ni1llO_dataout : STD_LOGIC; + SIGNAL wire_ni1lOO_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O0i_dataout : STD_LOGIC; + SIGNAL wire_ni1O0l_dataout : STD_LOGIC; + SIGNAL wire_ni1O0O_dataout : STD_LOGIC; + SIGNAL wire_ni1O1i_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O1O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli_dataout : STD_LOGIC; + SIGNAL wire_ni1Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO_dataout : STD_LOGIC; + SIGNAL wire_ni1OOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nii00i_dataout : STD_LOGIC; + SIGNAL wire_nii00l_dataout : STD_LOGIC; + SIGNAL wire_nii00O_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0ii_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0ll_dataout : STD_LOGIC; + SIGNAL wire_nii0O_dataout : STD_LOGIC; + SIGNAL wire_nii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nii10i_dataout : STD_LOGIC; + SIGNAL wire_nii10l_dataout : STD_LOGIC; + SIGNAL wire_nii10O_dataout : STD_LOGIC; + SIGNAL wire_nii11i_dataout : STD_LOGIC; + SIGNAL wire_nii11l_dataout : STD_LOGIC; + SIGNAL wire_nii11O_dataout : STD_LOGIC; + SIGNAL wire_nii1ii_dataout : STD_LOGIC; + SIGNAL wire_nii1il_dataout : STD_LOGIC; + SIGNAL wire_nii1iO_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil0ii_dataout : STD_LOGIC; + SIGNAL wire_nil0il_dataout : STD_LOGIC; + SIGNAL wire_nil0iO_dataout : STD_LOGIC; + SIGNAL wire_nil0li_dataout : STD_LOGIC; + SIGNAL wire_nil0ll_dataout : STD_LOGIC; + SIGNAL wire_nil0lO_dataout : STD_LOGIC; + SIGNAL wire_nil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0OO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nili0i_dataout : STD_LOGIC; + SIGNAL wire_nili0l_dataout : STD_LOGIC; + SIGNAL wire_nili0O_dataout : STD_LOGIC; + SIGNAL wire_nili1i_dataout : STD_LOGIC; + SIGNAL wire_nili1l_dataout : STD_LOGIC; + SIGNAL wire_nili1O_dataout : STD_LOGIC; + SIGNAL wire_niliii_dataout : STD_LOGIC; + SIGNAL wire_niliil_dataout : STD_LOGIC; + SIGNAL wire_niliiO_dataout : STD_LOGIC; + SIGNAL wire_nilili_dataout : STD_LOGIC; + SIGNAL wire_nilill_dataout : STD_LOGIC; + SIGNAL wire_nililO_dataout : STD_LOGIC; + SIGNAL wire_niliOi_dataout : STD_LOGIC; + SIGNAL wire_niliOl_dataout : STD_LOGIC; + SIGNAL wire_niliOO_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nill0i_dataout : STD_LOGIC; + SIGNAL wire_nill0l_dataout : STD_LOGIC; + SIGNAL wire_nill0O_dataout : STD_LOGIC; + SIGNAL wire_nill1i_dataout : STD_LOGIC; + SIGNAL wire_nill1l_dataout : STD_LOGIC; + SIGNAL wire_nill1O_dataout : STD_LOGIC; + SIGNAL wire_nillii_dataout : STD_LOGIC; + SIGNAL wire_nillil_dataout : STD_LOGIC; + SIGNAL wire_nilliO_dataout : STD_LOGIC; + SIGNAL wire_nillli_dataout : STD_LOGIC; + SIGNAL wire_nillll_dataout : STD_LOGIC; + SIGNAL wire_nilllO_dataout : STD_LOGIC; + SIGNAL wire_nillOi_dataout : STD_LOGIC; + SIGNAL wire_nillOl_dataout : STD_LOGIC; + SIGNAL wire_nillOO_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_nilO0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOii_dataout : STD_LOGIC; + SIGNAL wire_nilOil_dataout : STD_LOGIC; + SIGNAL wire_nilOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOli_dataout : STD_LOGIC; + SIGNAL wire_nilOll_dataout : STD_LOGIC; + SIGNAL wire_nilOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO00i_dataout : STD_LOGIC; + SIGNAL wire_niO00l_dataout : STD_LOGIC; + SIGNAL wire_niO00O_dataout : STD_LOGIC; + SIGNAL wire_niO01i_dataout : STD_LOGIC; + SIGNAL wire_niO01l_dataout : STD_LOGIC; + SIGNAL wire_niO01O_dataout : STD_LOGIC; + SIGNAL wire_niO0ii_dataout : STD_LOGIC; + SIGNAL wire_niO0il_dataout : STD_LOGIC; + SIGNAL wire_niO0iO_dataout : STD_LOGIC; + SIGNAL wire_niO0li_dataout : STD_LOGIC; + SIGNAL wire_niO0ll_dataout : STD_LOGIC; + SIGNAL wire_niO0lO_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niO10i_dataout : STD_LOGIC; + SIGNAL wire_niO10l_dataout : STD_LOGIC; + SIGNAL wire_niO10O_dataout : STD_LOGIC; + SIGNAL wire_niO11i_dataout : STD_LOGIC; + SIGNAL wire_niO11l_dataout : STD_LOGIC; + SIGNAL wire_niO11O_dataout : STD_LOGIC; + SIGNAL wire_niO1ii_dataout : STD_LOGIC; + SIGNAL wire_niO1il_dataout : STD_LOGIC; + SIGNAL wire_niO1iO_dataout : STD_LOGIC; + SIGNAL wire_niO1li_dataout : STD_LOGIC; + SIGNAL wire_niO1ll_dataout : STD_LOGIC; + SIGNAL wire_niO1lO_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOiii_dataout : STD_LOGIC; + SIGNAL wire_niOiil_dataout : STD_LOGIC; + SIGNAL wire_niOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOili_dataout : STD_LOGIC; + SIGNAL wire_niOill_dataout : STD_LOGIC; + SIGNAL wire_niOilO_dataout : STD_LOGIC; + SIGNAL wire_niOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl_dataout : STD_LOGIC; + SIGNAL wire_nl_w_lg_dataout1094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_dataout1013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl000l_dataout : STD_LOGIC; + SIGNAL wire_nl000O_dataout : STD_LOGIC; + SIGNAL wire_nl001i_dataout : STD_LOGIC; + SIGNAL wire_nl001l_dataout : STD_LOGIC; + SIGNAL wire_nl001O_dataout : STD_LOGIC; + SIGNAL wire_nl00ii_dataout : STD_LOGIC; + SIGNAL wire_nl00il_dataout : STD_LOGIC; + SIGNAL wire_nl00iO_dataout : STD_LOGIC; + SIGNAL wire_nl00li_dataout : STD_LOGIC; + SIGNAL wire_nl00ll_dataout : STD_LOGIC; + SIGNAL wire_nl00lO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00OO_dataout : STD_LOGIC; + SIGNAL wire_nl01il_dataout : STD_LOGIC; + SIGNAL wire_nl01iO_dataout : STD_LOGIC; + SIGNAL wire_nl01li_dataout : STD_LOGIC; + SIGNAL wire_nl01ll_dataout : STD_LOGIC; + SIGNAL wire_nl01lO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli00i_dataout : STD_LOGIC; + SIGNAL wire_nli00l_dataout : STD_LOGIC; + SIGNAL wire_nli00O_dataout : STD_LOGIC; + SIGNAL wire_nli01i_dataout : STD_LOGIC; + SIGNAL wire_nli01l_dataout : STD_LOGIC; + SIGNAL wire_nli01O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0il_dataout : STD_LOGIC; + SIGNAL wire_nli0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0OO_dataout : STD_LOGIC; + SIGNAL wire_nli10i_dataout : STD_LOGIC; + SIGNAL wire_nli10l_dataout : STD_LOGIC; + SIGNAL wire_nli10O_dataout : STD_LOGIC; + SIGNAL wire_nli11i_dataout : STD_LOGIC; + SIGNAL wire_nli11l_dataout : STD_LOGIC; + SIGNAL wire_nli11O_dataout : STD_LOGIC; + SIGNAL wire_nli1ii_dataout : STD_LOGIC; + SIGNAL wire_nli1il_dataout : STD_LOGIC; + SIGNAL wire_nli1iO_dataout : STD_LOGIC; + SIGNAL wire_nli1li_dataout : STD_LOGIC; + SIGNAL wire_nli1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlii_w_lg_dataout2015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlii0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1O_dataout : STD_LOGIC; + SIGNAL wire_nliiii_dataout : STD_LOGIC; + SIGNAL wire_nliiil_dataout : STD_LOGIC; + SIGNAL wire_nliiiO_dataout : STD_LOGIC; + SIGNAL wire_nliill_dataout : STD_LOGIC; + SIGNAL wire_nliilO_dataout : STD_LOGIC; + SIGNAL wire_nliiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlil_w_lg_dataout720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlil0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O_dataout : STD_LOGIC; + SIGNAL wire_nlilii_dataout : STD_LOGIC; + SIGNAL wire_nlilil_dataout : STD_LOGIC; + SIGNAL wire_nliliO_dataout : STD_LOGIC; + SIGNAL wire_nlilli_dataout : STD_LOGIC; + SIGNAL wire_nlilll_dataout : STD_LOGIC; + SIGNAL wire_nlillO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOO_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliO_w_lg_dataout718w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0i_dataout : STD_LOGIC; + SIGNAL wire_nliO0l_dataout : STD_LOGIC; + SIGNAL wire_nliO0O_dataout : STD_LOGIC; + SIGNAL wire_nliO1i_dataout : STD_LOGIC; + SIGNAL wire_nliO1l_dataout : STD_LOGIC; + SIGNAL wire_nliO1O_dataout : STD_LOGIC; + SIGNAL wire_nliOii_dataout : STD_LOGIC; + SIGNAL wire_nliOil_dataout : STD_LOGIC; + SIGNAL wire_nliOiO_dataout : STD_LOGIC; + SIGNAL wire_nliOli_dataout : STD_LOGIC; + SIGNAL wire_nliOll_dataout : STD_LOGIC; + SIGNAL wire_nliOlO_dataout : STD_LOGIC; + SIGNAL wire_nliOOi_dataout : STD_LOGIC; + SIGNAL wire_nliOOl_dataout : STD_LOGIC; + SIGNAL wire_nliOOO_dataout : STD_LOGIC; + SIGNAL wire_nll10i_dataout : STD_LOGIC; + SIGNAL wire_nll10l_dataout : STD_LOGIC; + SIGNAL wire_nll10O_dataout : STD_LOGIC; + SIGNAL wire_nll11i_dataout : STD_LOGIC; + SIGNAL wire_nll11O_dataout : STD_LOGIC; + SIGNAL wire_nll1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1il_dataout : STD_LOGIC; + SIGNAL wire_nll1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1li_dataout : STD_LOGIC; + SIGNAL wire_nll1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlli_w_lg_dataout716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nlll_w_lg_dataout679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0O_dataout : STD_LOGIC; + SIGNAL wire_nlllii_dataout : STD_LOGIC; + SIGNAL wire_nlllil_dataout : STD_LOGIC; + SIGNAL wire_nllliO_dataout : STD_LOGIC; + SIGNAL wire_nlllli_dataout : STD_LOGIC; + SIGNAL wire_nlllll_dataout : STD_LOGIC; + SIGNAL wire_nllllO_dataout : STD_LOGIC; + SIGNAL wire_nlllOi_dataout : STD_LOGIC; + SIGNAL wire_nlllOl_dataout : STD_LOGIC; + SIGNAL wire_nlllOO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_w_lg_dataout713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO0l_dataout : STD_LOGIC; + SIGNAL wire_nllO0O_dataout : STD_LOGIC; + SIGNAL wire_nllO1i_dataout : STD_LOGIC; + SIGNAL wire_nllO1l_dataout : STD_LOGIC; + SIGNAL wire_nllO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOii_dataout : STD_LOGIC; + SIGNAL wire_nllOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOli_dataout : STD_LOGIC; + SIGNAL wire_nllOll_dataout : STD_LOGIC; + SIGNAL wire_nllOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l_dataout : STD_LOGIC; + SIGNAL wire_nlO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O_dataout : STD_LOGIC; + SIGNAL wire_nlO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi_w_lg_dataout678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl_w_lg_dataout710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_w_lg_w_lg_w2466w2467w2468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w2481w2482w2483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w2466w2467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w2481w2482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w2410w2411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w2433w2434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w2452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w2466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w2481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w2410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w2433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2449w2450w2451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2334w2335w2465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2334w2335w2336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout709w711w2408w2409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout709w2430w2431w2432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_dataout2333w2449w2450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_dataout2333w2334w2335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_dataout709w711w2408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_w_lg_dataout709w2430w2431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout2333w2449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout2333w2334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout709w711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout709w2430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout2333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_nO_w_lg_dataout1517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiOl_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOl_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_niiOl_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niO0Ol_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niO0Ol_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niO0Ol_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niO0OO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niO0OO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niO0OO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niOi1i_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niOi1i_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niOi1i_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nllO0i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nllO0i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nllO0i_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nllOil_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOil_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOil_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00O_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlO00O_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlO00O_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlO11l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO11l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO11l_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n11li_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11li_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_ni1iii_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1iii_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nii0Ol_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii0Ol_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1OiO_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1OiO_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n100i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n100i_o : STD_LOGIC; + SIGNAL wire_n100i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n100l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n100l_o : STD_LOGIC; + SIGNAL wire_n100l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n101i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n101i_o : STD_LOGIC; + SIGNAL wire_n101i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n101l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n101l_o : STD_LOGIC; + SIGNAL wire_n101l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n101O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n101O_o : STD_LOGIC; + SIGNAL wire_n101O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11Ol_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11Ol_o : STD_LOGIC; + SIGNAL wire_n11Ol_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11OO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11OO_o : STD_LOGIC; + SIGNAL wire_n11OO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1iil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1iil_o : STD_LOGIC; + SIGNAL wire_ni1iil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1iiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1iiO_o : STD_LOGIC; + SIGNAL wire_ni1iiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1ili_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1ili_o : STD_LOGIC; + SIGNAL wire_ni1ili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1ill_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1ill_o : STD_LOGIC; + SIGNAL wire_ni1ill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1ilO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1ilO_o : STD_LOGIC; + SIGNAL wire_ni1ilO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1iOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1iOi_o : STD_LOGIC; + SIGNAL wire_ni1iOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1iOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1iOl_o : STD_LOGIC; + SIGNAL wire_ni1iOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1iOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1iOO_o : STD_LOGIC; + SIGNAL wire_ni1iOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii0iO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nii0iO_o : STD_LOGIC; + SIGNAL wire_nii0iO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii0li_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nii0li_o : STD_LOGIC; + SIGNAL wire_nii0li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii0lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nii0lO_o : STD_LOGIC; + SIGNAL wire_nii0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii0OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nii0OO_o : STD_LOGIC; + SIGNAL wire_nii0OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niii0i_o : STD_LOGIC; + SIGNAL wire_niii0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niii0l_o : STD_LOGIC; + SIGNAL wire_niii0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niii0O_o : STD_LOGIC; + SIGNAL wire_niii0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niii1i_o : STD_LOGIC; + SIGNAL wire_niii1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niii1l_o : STD_LOGIC; + SIGNAL wire_niii1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niii1O_o : STD_LOGIC; + SIGNAL wire_niii1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiiii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niiiii_o : STD_LOGIC; + SIGNAL wire_niiiii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiiil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niiiil_o : STD_LOGIC; + SIGNAL wire_niiiil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiiiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niiiiO_o : STD_LOGIC; + SIGNAL wire_niiiiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiili_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niiili_o : STD_LOGIC; + SIGNAL wire_niiili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiill_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niiill_o : STD_LOGIC; + SIGNAL wire_niiill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl010i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl010i_o : STD_LOGIC; + SIGNAL wire_nl010i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl010l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl010l_o : STD_LOGIC; + SIGNAL wire_nl010l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl010O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl010O_o : STD_LOGIC; + SIGNAL wire_nl010O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl011i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl011i_o : STD_LOGIC; + SIGNAL wire_nl011i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl011l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl011l_o : STD_LOGIC; + SIGNAL wire_nl011l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl011O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl011O_o : STD_LOGIC; + SIGNAL wire_nl011O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl01ii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl01ii_o : STD_LOGIC; + SIGNAL wire_nl01ii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n11ii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11ii_o : STD_LOGIC; + SIGNAL wire_n11ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11il_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11il_o : STD_LOGIC; + SIGNAL wire_n11il_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11ll_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n11ll_o : STD_LOGIC; + SIGNAL wire_n11ll_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1i0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1i0l_o : STD_LOGIC; + SIGNAL wire_ni1i0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rpmadwidth_rx15w16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0OlOi124w2004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_n0OiiO114w118w119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lOli979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0OilO112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpmadwidth_rx15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rbist_sel_range1w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rcxpat_chnl_sel_range842w847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxc_range111w980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxc_range111w113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxc_range111w2011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxc_range111w2008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxd_range651w668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iO0l2052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iO1O2054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOii2050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOil2133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOiO2048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOli2046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOll2044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOlO2047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOOi2042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOOO2040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l01l2021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l01O2020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l0il2014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l0iO2013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l10i2036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l10l2126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l10O2034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l11l2038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1ii2032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1il2030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1iO2033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1li2028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1lO2026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1Ol2024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1OO2023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0li0l1011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0li0O1010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0liii1009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0liil1008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lili1006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lill1005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lilO1004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0liOi1003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0liOl1002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0liOO1001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ll0i999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ll1O1000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0llil989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lliO988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0llll987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lllO986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0llOl985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0llOO984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O00i136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O00l135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O00O134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O01i139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O01l138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O01O137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0ii133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0il132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0iO131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0li130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0ll129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0lO128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0Oi127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O0Ol126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1iO151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1li150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1ll149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1lO148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0Oi1i125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0OlOi124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rbist_clr_rx108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpma_doublewidth_rx14w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rbist_sel_range3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rcxpat_chnl_sel_range844w845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rxd_range652w667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0OiiO114w118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0OiiO114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0iO0i : STD_LOGIC; + SIGNAL n0iO0l : STD_LOGIC; + SIGNAL n0iO0O : STD_LOGIC; + SIGNAL n0iO1i : STD_LOGIC; + SIGNAL n0iO1l : STD_LOGIC; + SIGNAL n0iO1O : STD_LOGIC; + SIGNAL n0iOii : STD_LOGIC; + SIGNAL n0iOil : STD_LOGIC; + SIGNAL n0iOiO : STD_LOGIC; + SIGNAL n0iOli : STD_LOGIC; + SIGNAL n0iOll : STD_LOGIC; + SIGNAL n0iOlO : STD_LOGIC; + SIGNAL n0iOOi : STD_LOGIC; + SIGNAL n0iOOl : STD_LOGIC; + SIGNAL n0iOOO : STD_LOGIC; + SIGNAL n0l00i : STD_LOGIC; + SIGNAL n0l00l : STD_LOGIC; + SIGNAL n0l00O : STD_LOGIC; + SIGNAL n0l01i : STD_LOGIC; + SIGNAL n0l01l : STD_LOGIC; + SIGNAL n0l01O : STD_LOGIC; + SIGNAL n0l0ii : STD_LOGIC; + SIGNAL n0l0il : STD_LOGIC; + SIGNAL n0l0iO : STD_LOGIC; + SIGNAL n0l0li : STD_LOGIC; + SIGNAL n0l0ll : STD_LOGIC; + SIGNAL n0l0lO : STD_LOGIC; + SIGNAL n0l0Oi : STD_LOGIC; + SIGNAL n0l0Ol : STD_LOGIC; + SIGNAL n0l0OO : STD_LOGIC; + SIGNAL n0l10i : STD_LOGIC; + SIGNAL n0l10l : STD_LOGIC; + SIGNAL n0l10O : STD_LOGIC; + SIGNAL n0l11i : STD_LOGIC; + SIGNAL n0l11l : STD_LOGIC; + SIGNAL n0l11O : STD_LOGIC; + SIGNAL n0l1ii : STD_LOGIC; + SIGNAL n0l1il : STD_LOGIC; + SIGNAL n0l1iO : STD_LOGIC; + SIGNAL n0l1li : STD_LOGIC; + SIGNAL n0l1ll : STD_LOGIC; + SIGNAL n0l1lO : STD_LOGIC; + SIGNAL n0l1Oi : STD_LOGIC; + SIGNAL n0l1Ol : STD_LOGIC; + SIGNAL n0l1OO : STD_LOGIC; + SIGNAL n0li0i : STD_LOGIC; + SIGNAL n0li0l : STD_LOGIC; + SIGNAL n0li0O : STD_LOGIC; + SIGNAL n0li1i : STD_LOGIC; + SIGNAL n0li1l : STD_LOGIC; + SIGNAL n0liii : STD_LOGIC; + SIGNAL n0liil : STD_LOGIC; + SIGNAL n0liiO : STD_LOGIC; + SIGNAL n0lili : STD_LOGIC; + SIGNAL n0lill : STD_LOGIC; + SIGNAL n0lilO : STD_LOGIC; + SIGNAL n0liOi : STD_LOGIC; + SIGNAL n0liOl : STD_LOGIC; + SIGNAL n0liOO : STD_LOGIC; + SIGNAL n0ll0i : STD_LOGIC; + SIGNAL n0ll0l : STD_LOGIC; + SIGNAL n0ll0O : STD_LOGIC; + SIGNAL n0ll1i : STD_LOGIC; + SIGNAL n0ll1l : STD_LOGIC; + SIGNAL n0ll1O : STD_LOGIC; + SIGNAL n0llii : STD_LOGIC; + SIGNAL n0llil : STD_LOGIC; + SIGNAL n0lliO : STD_LOGIC; + SIGNAL n0llli : STD_LOGIC; + SIGNAL n0llll : STD_LOGIC; + SIGNAL n0lllO : STD_LOGIC; + SIGNAL n0llOi : STD_LOGIC; + SIGNAL n0llOl : STD_LOGIC; + SIGNAL n0llOO : STD_LOGIC; + SIGNAL n0lO0i : STD_LOGIC; + SIGNAL n0lO0l : STD_LOGIC; + SIGNAL n0lO0O : STD_LOGIC; + SIGNAL n0lO1i : STD_LOGIC; + SIGNAL n0lO1l : STD_LOGIC; + SIGNAL n0lO1O : STD_LOGIC; + SIGNAL n0lOii : STD_LOGIC; + SIGNAL n0lOil : STD_LOGIC; + SIGNAL n0lOiO : STD_LOGIC; + SIGNAL n0lOli : STD_LOGIC; + SIGNAL n0lOll : STD_LOGIC; + SIGNAL n0lOlO : STD_LOGIC; + SIGNAL n0O00i : STD_LOGIC; + SIGNAL n0O00l : STD_LOGIC; + SIGNAL n0O00O : STD_LOGIC; + SIGNAL n0O01i : STD_LOGIC; + SIGNAL n0O01l : STD_LOGIC; + SIGNAL n0O01O : STD_LOGIC; + SIGNAL n0O0ii : STD_LOGIC; + SIGNAL n0O0il : STD_LOGIC; + SIGNAL n0O0iO : STD_LOGIC; + SIGNAL n0O0li : STD_LOGIC; + SIGNAL n0O0ll : STD_LOGIC; + SIGNAL n0O0lO : STD_LOGIC; + SIGNAL n0O0Oi : STD_LOGIC; + SIGNAL n0O0Ol : STD_LOGIC; + SIGNAL n0O0OO : STD_LOGIC; + SIGNAL n0O1il : STD_LOGIC; + SIGNAL n0O1iO : STD_LOGIC; + SIGNAL n0O1li : STD_LOGIC; + SIGNAL n0O1ll : STD_LOGIC; + SIGNAL n0O1lO : STD_LOGIC; + SIGNAL n0O1Oi : STD_LOGIC; + SIGNAL n0Oi0l : STD_LOGIC; + SIGNAL n0Oi1i : STD_LOGIC; + SIGNAL n0Oi1l : STD_LOGIC; + SIGNAL n0Oiil : STD_LOGIC; + SIGNAL n0OiiO : STD_LOGIC; + SIGNAL n0Oili : STD_LOGIC; + SIGNAL n0Oill : STD_LOGIC; + SIGNAL n0OilO : STD_LOGIC; + SIGNAL n0OiOl : STD_LOGIC; + SIGNAL n0Olli : STD_LOGIC; + SIGNAL n0Olll : STD_LOGIC; + SIGNAL n0OllO : STD_LOGIC; + SIGNAL n0OlOi : STD_LOGIC; + SIGNAL n0OlOl : STD_LOGIC; + SIGNAL wire_w_rbist_sel_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rbist_sel_range3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rcxpat_chnl_sel_range842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rcxpat_chnl_sel_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rxc_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rxd_range651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rxd_range652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_w_lg_w_lg_rpmadwidth_rx15w16w(0) <= wire_w_lg_rpmadwidth_rx15w(0) AND rdwidth_rx; + wire_w_lg_w_lg_n0OlOi124w2004w(0) <= wire_w_lg_n0OlOi124w(0) AND n0li1i; + wire_w_lg_w_lg_w_lg_n0OiiO114w118w119w(0) <= wire_w_lg_w_lg_n0OiiO114w118w(0) AND n0Oi0l; + wire_w_lg_n0lOli979w(0) <= n0lOli AND n0lOiO; + wire_w_lg_n0OilO112w(0) <= n0OilO AND n0Oill; + wire_w_lg_rpmadwidth_rx15w(0) <= rpmadwidth_rx AND wire_w_lg_rpma_doublewidth_rx14w(0); + wire_w_lg_w_rbist_sel_range1w9w(0) <= wire_w_rbist_sel_range1w(0) AND wire_w_lg_w_rbist_sel_range3w4w(0); + wire_w_lg_w_rcxpat_chnl_sel_range842w847w(0) <= wire_w_rcxpat_chnl_sel_range842w(0) AND wire_w_lg_w_rcxpat_chnl_sel_range844w845w(0); + wire_w_lg_w_rxc_range111w980w(0) <= wire_w_rxc_range111w(0) AND wire_w_lg_n0lOli979w(0); + wire_w_lg_w_rxc_range111w113w(0) <= wire_w_rxc_range111w(0) AND wire_w_lg_n0OilO112w(0); + wire_w_lg_w_rxc_range111w2011w(0) <= wire_w_rxc_range111w(0) AND n0l0li; + wire_w_lg_w_rxc_range111w2008w(0) <= wire_w_rxc_range111w(0) AND n0l0lO; + wire_w_lg_w_rxd_range651w668w(0) <= wire_w_rxd_range651w(0) AND wire_w_lg_w_rxd_range652w667w(0); + wire_w_lg_n0iO0l2052w(0) <= NOT n0iO0l; + wire_w_lg_n0iO1O2054w(0) <= NOT n0iO1O; + wire_w_lg_n0iOii2050w(0) <= NOT n0iOii; + wire_w_lg_n0iOil2133w(0) <= NOT n0iOil; + wire_w_lg_n0iOiO2048w(0) <= NOT n0iOiO; + wire_w_lg_n0iOli2046w(0) <= NOT n0iOli; + wire_w_lg_n0iOll2044w(0) <= NOT n0iOll; + wire_w_lg_n0iOlO2047w(0) <= NOT n0iOlO; + wire_w_lg_n0iOOi2042w(0) <= NOT n0iOOi; + wire_w_lg_n0iOOO2040w(0) <= NOT n0iOOO; + wire_w_lg_n0l01l2021w(0) <= NOT n0l01l; + wire_w_lg_n0l01O2020w(0) <= NOT n0l01O; + wire_w_lg_n0l0il2014w(0) <= NOT n0l0il; + wire_w_lg_n0l0iO2013w(0) <= NOT n0l0iO; + wire_w_lg_n0l10i2036w(0) <= NOT n0l10i; + wire_w_lg_n0l10l2126w(0) <= NOT n0l10l; + wire_w_lg_n0l10O2034w(0) <= NOT n0l10O; + wire_w_lg_n0l11l2038w(0) <= NOT n0l11l; + wire_w_lg_n0l1ii2032w(0) <= NOT n0l1ii; + wire_w_lg_n0l1il2030w(0) <= NOT n0l1il; + wire_w_lg_n0l1iO2033w(0) <= NOT n0l1iO; + wire_w_lg_n0l1li2028w(0) <= NOT n0l1li; + wire_w_lg_n0l1lO2026w(0) <= NOT n0l1lO; + wire_w_lg_n0l1Ol2024w(0) <= NOT n0l1Ol; + wire_w_lg_n0l1OO2023w(0) <= NOT n0l1OO; + wire_w_lg_n0li0l1011w(0) <= NOT n0li0l; + wire_w_lg_n0li0O1010w(0) <= NOT n0li0O; + wire_w_lg_n0liii1009w(0) <= NOT n0liii; + wire_w_lg_n0liil1008w(0) <= NOT n0liil; + wire_w_lg_n0lili1006w(0) <= NOT n0lili; + wire_w_lg_n0lill1005w(0) <= NOT n0lill; + wire_w_lg_n0lilO1004w(0) <= NOT n0lilO; + wire_w_lg_n0liOi1003w(0) <= NOT n0liOi; + wire_w_lg_n0liOl1002w(0) <= NOT n0liOl; + wire_w_lg_n0liOO1001w(0) <= NOT n0liOO; + wire_w_lg_n0ll0i999w(0) <= NOT n0ll0i; + wire_w_lg_n0ll1O1000w(0) <= NOT n0ll1O; + wire_w_lg_n0llil989w(0) <= NOT n0llil; + wire_w_lg_n0lliO988w(0) <= NOT n0lliO; + wire_w_lg_n0llll987w(0) <= NOT n0llll; + wire_w_lg_n0lllO986w(0) <= NOT n0lllO; + wire_w_lg_n0llOl985w(0) <= NOT n0llOl; + wire_w_lg_n0llOO984w(0) <= NOT n0llOO; + wire_w_lg_n0O00i136w(0) <= NOT n0O00i; + wire_w_lg_n0O00l135w(0) <= NOT n0O00l; + wire_w_lg_n0O00O134w(0) <= NOT n0O00O; + wire_w_lg_n0O01i139w(0) <= NOT n0O01i; + wire_w_lg_n0O01l138w(0) <= NOT n0O01l; + wire_w_lg_n0O01O137w(0) <= NOT n0O01O; + wire_w_lg_n0O0ii133w(0) <= NOT n0O0ii; + wire_w_lg_n0O0il132w(0) <= NOT n0O0il; + wire_w_lg_n0O0iO131w(0) <= NOT n0O0iO; + wire_w_lg_n0O0li130w(0) <= NOT n0O0li; + wire_w_lg_n0O0ll129w(0) <= NOT n0O0ll; + wire_w_lg_n0O0lO128w(0) <= NOT n0O0lO; + wire_w_lg_n0O0Oi127w(0) <= NOT n0O0Oi; + wire_w_lg_n0O0Ol126w(0) <= NOT n0O0Ol; + wire_w_lg_n0O1iO151w(0) <= NOT n0O1iO; + wire_w_lg_n0O1li150w(0) <= NOT n0O1li; + wire_w_lg_n0O1ll149w(0) <= NOT n0O1ll; + wire_w_lg_n0O1lO148w(0) <= NOT n0O1lO; + wire_w_lg_n0Oi1i125w(0) <= NOT n0Oi1i; + wire_w_lg_n0OlOi124w(0) <= NOT n0OlOi; + wire_w_lg_rbist_clr_rx108w(0) <= NOT rbist_clr_rx; + wire_w_lg_rpma_doublewidth_rx14w(0) <= NOT rpma_doublewidth_rx; + wire_w_lg_soft_reset105w(0) <= NOT soft_reset; + wire_w_lg_w_rbist_sel_range3w4w(0) <= NOT wire_w_rbist_sel_range3w(0); + wire_w_lg_w_rcxpat_chnl_sel_range844w845w(0) <= NOT wire_w_rcxpat_chnl_sel_range844w(0); + wire_w_lg_w_rxd_range652w667w(0) <= NOT wire_w_rxd_range652w(0); + wire_w_lg_w_lg_n0OiiO114w118w(0) <= wire_w_lg_n0OiiO114w(0) OR wire_n0Oi0O22_w_lg_w_lg_q116w117w(0); + wire_w_lg_n0OiiO114w(0) <= n0OiiO OR n0Oiil; + bistdone <= ((wire_nl1l_dataout OR prbs_done) OR (NOT (n0Ol0O10 XOR n0Ol0O9))); + bisterr <= ((wire_nl1i_dataout OR prbs_err) OR (NOT (n0Olil8 XOR n0Olil7))); + cur_state <= ( wire_n1OO_dataout & wire_n1Ol_dataout & wire_n1Oi_dataout & wire_n1lO_dataout & wire_n1ll_dataout); + err_ctl <= ( wire_niOO_dataout & wire_niOl_dataout); + err_data <= ( wire_niOi_dataout & wire_nilO_dataout & wire_nill_dataout & wire_nili_dataout & wire_niiO_dataout & wire_niil_dataout & wire_niii_dataout & wire_ni0O_dataout & wire_ni0l_dataout & wire_ni0i_dataout & wire_ni1O_dataout & wire_ni1l_dataout & wire_ni1i_dataout & wire_n0OO_dataout & wire_n0Ol_dataout & wire_n0Oi_dataout); + n0iO0i <= (wire_w_lg_n0iO0l2052w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0iO0l <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0iO0O <= (wire_w_lg_n0iOii2050w(0) OR wire_w_lg_n0l01l2021w(0)); + n0iO1i <= (((((((((((((wire_ni1iii_o(15) OR wire_ni1iii_o(14)) OR wire_ni1iii_o(13)) OR wire_ni1iii_o(12)) OR wire_ni1iii_o(11)) OR wire_ni1iii_o(10)) OR wire_ni1iii_o(9)) OR wire_ni1iii_o(8)) OR wire_ni1iii_o(7)) OR wire_ni1iii_o(6)) OR wire_ni1iii_o(5)) OR wire_ni1iii_o(4)) OR wire_ni1iii_o(3)) OR wire_ni1iii_o(0)); + n0iO1l <= (wire_w_lg_n0iO1O2054w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0iO1O <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0iOii <= ((((((((wire_nlOO_w_lg_w_lg_w2481w2482w2483w(0) AND (NOT rxd(0))) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0iOil <= (wire_w_lg_n0iOiO2048w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0iOiO <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0iOli <= (wire_w_lg_n0iOll2044w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0iOll <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0iOlO <= (wire_w_lg_n0iOOi2042w(0) OR wire_w_lg_n0l01l2021w(0)); + n0iOOi <= ((((((((wire_nlOO_w_lg_w_lg_w2466w2467w2468w(0) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0iOOl <= (wire_w_lg_n0iOOO2040w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0iOOO <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND rxd(7)); + n0l00i <= (((((((nil1lO AND nil1ll) AND nil1li) AND nil1iO) AND nil1il) AND nil1ii) AND nil10O) AND nil10l); + n0l00l <= (n0OlOi AND n0l00O); + n0l00O <= (((((((niiOll AND niiOli) AND niiOiO) AND niiOil) AND niiOii) AND niiO0O) AND niiO0l) AND niiO0i); + n0l01i <= (wire_w_lg_n0l01O2020w(0) OR wire_w_lg_n0l01l2021w(0)); + n0l01l <= (wire_nlii_dataout AND rxc(0)); + n0l01O <= ((((((((((wire_nlOO_w_lg_w2410w2411w(0) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND (NOT rxd(6))) AND (NOT rxd(7))); + n0l0ii <= (wire_w_lg_n0l0il2014w(0) OR (NOT (wire_nlii_w_lg_dataout2015w(0) AND (NOT rxc(0))))); + n0l0il <= ((((((((((((((((NOT (rxd(0) XOR wire_niOi1l_dataout)) AND (NOT (rxd(1) XOR wire_niOi1O_dataout))) AND (NOT (rxd(2) XOR wire_niOi0i_dataout))) AND (NOT (rxd(3) XOR wire_niOi0l_dataout))) AND (NOT (rxd(4) XOR wire_niOi0O_dataout))) AND (NOT (rxd(5) XOR wire_niOiii_dataout))) AND (NOT (rxd(6) XOR wire_niOiil_dataout))) AND (NOT (rxd(7) XOR wire_niOiiO_dataout))) AND (NOT (wire_nlil_dataout XOR wire_niOili_dataout))) AND (NOT (wire_nliO_dataout XOR wire_niOill_dataout))) AND (NOT (wire_nlli_dataout XOR wire_niOilO_dataout))) AND (NOT (wire_nlll_dataout XOR wire_niOiOi_dataout))) AND (NOT (wire_nllO_dataout XOR wire_niOiOl_dataout))) AND (NOT (wire_nlOi_dataout XOR wire_niOiOO_dataout))) AND (NOT (wire_nlOl_dataout XOR wire_niOl1i_dataout))) AND (NOT (wire_nlOO_dataout XOR wire_niOl1l_dataout))); + n0l0iO <= (wire_w_lg_n0OlOi124w(0) AND wire_w_lg_w_rxc_range111w2011w(0)); + n0l0li <= (((((((rxd(0) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0l0ll <= (n0OlOi AND ((wire_nlii_dataout AND n0l0Oi) AND wire_w_lg_w_rxc_range111w2008w(0))); + n0l0lO <= ((((((((NOT rxd(0)) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND (NOT rxd(6))) AND rxd(7)); + n0l0Oi <= (((wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2334w2335w2336w(0) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_dataout) AND wire_nlil_dataout); + n0l0Ol <= (wire_w_lg_w_lg_n0OlOi124w2004w(0) OR (n0OlOi AND n0l0OO)); + n0l0OO <= ((((((wire_ni0OO_w_lg_w_lg_nil1Oi2312w2314w(0) AND wire_ni0OO_w_lg_nil1li2325w(0)) AND wire_ni0OO_w_lg_nil1iO2316w(0)) AND wire_ni0OO_w_lg_nil1il2318w(0)) AND wire_ni0OO_w_lg_nil1ii2320w(0)) AND wire_ni0OO_w_lg_nil10O2322w(0)) AND wire_ni0OO_w_lg_nil10l2331w(0)); + n0l10i <= ((((((((((wire_nlOO_w2452w(0) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND (NOT rxd(6))) AND rxd(7)); + n0l10l <= (wire_w_lg_n0l10O2034w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0l10O <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND (NOT rxd(7))); + n0l11i <= (wire_w_lg_n0l11l2038w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0l11l <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND (NOT rxd(6))) AND rxd(7)); + n0l11O <= (wire_w_lg_n0l10i2036w(0) OR wire_w_lg_n0l01l2021w(0)); + n0l1ii <= (wire_w_lg_n0l1il2030w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0l1il <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))); + n0l1iO <= (wire_w_lg_n0l1li2028w(0) OR wire_w_lg_n0l01l2021w(0)); + n0l1li <= ((((((((((wire_nlOO_w_lg_w2433w2434w(0) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))); + n0l1ll <= (wire_w_lg_n0l1lO2026w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0l1lO <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND (NOT rxd(6))) AND (NOT rxd(7))); + n0l1Oi <= (wire_w_lg_n0l1OO2023w(0) OR wire_w_lg_n0l1Ol2024w(0)); + n0l1Ol <= (wire_nlii_w_lg_dataout2015w(0) AND rxc(0)); + n0l1OO <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND (NOT rxd(6))) AND (NOT rxd(7))); + n0li0i <= ((NOT rxc(0)) OR wire_w_lg_n0li0l1011w(0)); + n0li0l <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0li0O <= (((((((((((((((wire_nlOl_w_lg_dataout710w(0) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND (NOT rxd(4))) AND rxd(5)) AND (NOT rxd(6))) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0li1i <= (((((wire_ni0OO_w_lg_w_lg_w_lg_nil1Oi2312w2314w2315w(0) AND wire_ni0OO_w_lg_nil1iO2316w(0)) AND wire_ni0OO_w_lg_nil1il2318w(0)) AND wire_ni0OO_w_lg_nil1ii2320w(0)) AND wire_ni0OO_w_lg_nil10O2322w(0)) AND nil10l); + n0li1l <= (wire_nO_dataout AND rxd(10)); + n0liii <= (((((((((((((((wire_nlOl_w_lg_dataout710w(0) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND (NOT rxd(6))) AND (NOT rxd(7))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0liil <= (((((((((((((((wire_nlOl_w_lg_dataout710w(0) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND (NOT rxd(6))) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0liiO <= (wire_w_lg_n0lili1006w(0) OR (NOT (wire_nlii_dataout AND (NOT rxc(0))))); + n0lili <= (((((((((((((((wire_nliO_w_lg_dataout718w(0) AND rxd(0)) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND (NOT rxd(6))) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0lill <= (((((((((((((((wire_nlOl_w_lg_dataout710w(0) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND rxd(0)) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND rxd(5)) AND (NOT rxd(6))) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0lilO <= ((((wire_ni0OO_w_lg_w_lg_nll0Ol1343w1344w(0) AND wire_ni0OO_w_lg_nll0lO1345w(0)) AND wire_ni0OO_w_lg_nll0ll1347w(0)) AND nll0li) AND nll0iO); + n0liOi <= ((((wire_ni0OO_w_lg_nll0Ol1352w(0) AND wire_ni0OO_w_lg_nll0lO1345w(0)) AND nll0ll) AND nll0li) AND nll0iO); + n0liOl <= (((((((((((((((wire_nlOl_w_lg_dataout710w(0) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND rxd(5)) AND rxd(7)) AND (NOT (wire_w_lg_n0OlOi124w(0) XOR rxd(0)))) AND (NOT (wire_w_lg_n0OlOi124w(0) XOR rxd(1)))) AND (NOT (n0OlOi XOR rxd(2)))) AND (NOT (wire_w_lg_n0OlOi124w(0) XOR rxd(3)))) AND (NOT (n0OlOi XOR rxd(4)))) AND (NOT (n0OlOi XOR rxd(6)))) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0liOO <= (((((((((((((((wire_nlll_w_lg_dataout679w(0) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND (NOT rxd(4))) AND rxd(5)) AND rxd(6)) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0ll0i <= (wire_ni0OO_w_lg_w_lg_w_lg_nlli0O990w992w993w(0) AND wire_ni0OO_w_lg_nlli1O1273w(0)); + n0ll0l <= (((wire_ni0OO_w_lg_nlli0O990w(0) AND nlli0l) AND nlli0i) AND nlli1O); + n0ll0O <= (((nlli0O AND nlli0l) AND nlli0i) AND nlli1O); + n0ll1i <= ((wire_ni0OO_w_lg_nlli1l1296w(0) AND nlli1i) AND nll0OO); + n0ll1l <= ((nlli1l AND nlli1i) AND nll0OO); + n0ll1O <= (((((((((((((((wire_nllO_w_lg_dataout713w(0) AND wire_nlli_w_lg_dataout716w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0llii <= (wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlli0O990w992w993w994w(0) OR wire_ni0OO_w_lg_w_lg_w_lg_nlli0O995w996w997w(0)); + n0llil <= (((((((((((((((wire_nlOO_w_lg_dataout709w(0) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND (NOT rxd(7))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))); + n0lliO <= (wire_ni0OO_w_lg_w_lg_w1251w1252w1253w(0) AND nlliii); + n0llli <= ((((((wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1222w1224w1225w(0) AND wire_ni0OO_w_lg_nllilO1226w(0)) AND wire_ni0OO_w_lg_nllill1228w(0)) AND wire_ni0OO_w_lg_nllili1230w(0)) AND wire_ni0OO_w_lg_nlliiO1232w(0)) AND wire_ni0OO_w_lg_nlliil1234w(0)) AND nlliii); + n0llll <= (wire_ni0OO_w_lg_w_lg_w_lg_w1242w1243w1244w1245w(0) AND nlliii); + n0lllO <= (wire_ni0OO_w_lg_w_lg_w1251w1252w1253w(0) AND wire_ni0OO_w_lg_nlliii1236w(0)); + n0llOi <= ((((((wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1222w1224w1225w(0) AND wire_ni0OO_w_lg_nllilO1226w(0)) AND wire_ni0OO_w_lg_nllill1228w(0)) AND wire_ni0OO_w_lg_nllili1230w(0)) AND wire_ni0OO_w_lg_nlliiO1232w(0)) AND wire_ni0OO_w_lg_nlliil1234w(0)) AND wire_ni0OO_w_lg_nlliii1236w(0)); + n0llOl <= (wire_ni0OO_w_lg_w_lg_w_lg_w1242w1243w1244w1245w(0) AND wire_ni0OO_w_lg_nlliii1236w(0)); + n0llOO <= (((((((((((((((wire_nlOO_w_lg_dataout709w(0) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND (NOT rxd(4))) AND (NOT rxd(5))) AND (NOT rxd(6))) AND (NOT rxd(7))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))); + n0lO0i <= (rcxpat_chnl_sel(0) AND rcxpat_chnl_sel(1)); + n0lO0l <= (n0lOii AND n0lO0O); + n0lO0O <= ((((((wire_w_lg_w_rxd_range651w668w(0) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))); + n0lO1i <= ((NOT rcxpat_chnl_sel(0)) AND rcxpat_chnl_sel(1)); + n0lO1l <= wire_w_lg_w_rcxpat_chnl_sel_range842w847w(0); + n0lO1O <= (n0lO0O AND n0lO0i); + n0lOii <= (n0lO1l OR n0lO1i); + n0lOil <= wire_w_lg_w_rxc_range111w980w(0); + n0lOiO <= ((NOT rcxpat_chnl_sel(0)) AND wire_w_lg_w_rcxpat_chnl_sel_range844w845w(0)); + n0lOli <= (((((((rxd(0) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0lOll <= (((((((((((((((((((((((((((((wire_n11li_o(31) OR wire_n11li_o(30)) OR wire_n11li_o(29)) OR wire_n11li_o(28)) OR wire_n11li_o(27)) OR wire_n11li_o(26)) OR wire_n11li_o(25)) OR wire_n11li_o(24)) OR wire_n11li_o(23)) OR wire_n11li_o(22)) OR wire_n11li_o(21)) OR wire_n11li_o(20)) OR wire_n11li_o(19)) OR wire_n11li_o(18)) OR wire_n11li_o(17)) OR wire_n11li_o(16)) OR wire_n11li_o(13)) OR wire_n11li_o(12)) OR wire_n11li_o(11)) OR wire_n11li_o(10)) OR wire_n11li_o(9)) OR wire_n11li_o(8)) OR wire_n11li_o(7)) OR wire_n11li_o(6)) OR wire_n11li_o(5)) OR wire_n11li_o(4)) OR wire_n11li_o(3)) OR wire_n11li_o(2)) OR wire_n11li_o(1)) OR wire_n11li_o(0)); + n0lOlO <= ((((((((((((((((((((((((((wire_n11li_o(31) OR wire_n11li_o(30)) OR wire_n11li_o(29)) OR wire_n11li_o(28)) OR wire_n11li_o(27)) OR wire_n11li_o(26)) OR wire_n11li_o(25)) OR wire_n11li_o(24)) OR wire_n11li_o(23)) OR wire_n11li_o(22)) OR wire_n11li_o(21)) OR wire_n11li_o(15)) OR wire_n11li_o(14)) OR wire_n11li_o(13)) OR wire_n11li_o(12)) OR wire_n11li_o(11)) OR wire_n11li_o(10)) OR wire_n11li_o(9)) OR wire_n11li_o(8)) OR wire_n11li_o(7)) OR wire_n11li_o(6)) OR wire_n11li_o(5)) OR wire_n11li_o(4)) OR wire_n11li_o(3)) OR wire_n11li_o(2)) OR wire_n11li_o(1)) OR wire_n11li_o(0)); + n0O00i <= (wire_ni0OO_w_lg_w_lg_w_lg_ni0li837w838w839w(0) AND wire_ni0OO_w_lg_ni00O840w(0)); + n0O00l <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0O00O <= (((((((((((((((wire_nlli_w_lg_dataout716w(0) AND (NOT rxd(0))) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0O01i <= (((((((((((((((wire_nliO_w_lg_dataout718w(0) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOi_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0O01l <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND wire_w_lg_w_rxd_range652w667w(0)) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))); + n0O01O <= (((((((((((((((wire_nlOO_w_lg_dataout709w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND rxd(0)) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND rxd(5)) AND (NOT rxd(6))) AND (NOT rxd(7))) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))); + n0O0ii <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND (NOT rxd(0))) AND wire_w_lg_w_rxd_range652w667w(0)) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND (NOT rxd(5))) AND (NOT rxd(6))) AND (NOT rxd(7))); + n0O0il <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND (NOT rxd(2))) AND (NOT rxd(3))) AND rxd(4)) AND rxd(5)) AND (NOT rxd(6))) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))); + n0O0iO <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND (NOT rxd(4))) AND (NOT rxd(5))) AND (NOT rxd(6))) AND rxd(7)); + n0O0li <= (((((((((((((((wire_nlOl_w_lg_dataout710w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND rxd(0)) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND (NOT rxd(4))) AND rxd(5)) AND rxd(6)) AND (NOT rxd(7))) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlll_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0O0ll <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND rxd(2)) AND (NOT rxd(3))) AND (NOT rxd(4))) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))); + n0O0lO <= (((((((((((((((wire_nlOO_w_lg_dataout709w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND rxd(0)) AND rxd(1)) AND (NOT rxd(2))) AND (NOT rxd(3))) AND (NOT rxd(4))) AND rxd(5)) AND (NOT rxd(6))) AND (NOT rxd(7))) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))); + n0O0Oi <= ((((((((((((((wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_w_lg_dataout678w(0)) AND wire_nllO_w_lg_dataout713w(0)) AND wire_nlll_w_lg_dataout679w(0)) AND wire_nlli_w_lg_dataout716w(0)) AND wire_nliO_w_lg_dataout718w(0)) AND wire_nlil_w_lg_dataout720w(0)) AND rxd(0)) AND rxd(1)) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND rxd(7)); + n0O0Ol <= (((((((((((((((wire_nlOi_w_lg_dataout678w(0) AND wire_nlll_w_lg_dataout679w(0)) AND (NOT rxd(0))) AND rxd(1)) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND (NOT rxd(6))) AND rxd(7)) AND (NOT (n0OlOi XOR wire_nlil_dataout))) AND (NOT (n0OlOi XOR wire_nliO_dataout))) AND (NOT (n0OlOi XOR wire_nlli_dataout))) AND (NOT (n0OlOi XOR wire_nllO_dataout))) AND (NOT (n0OlOi XOR wire_nlOl_dataout))) AND (NOT (n0OlOi XOR wire_nlOO_dataout))); + n0O0OO <= (n0Oi0l AND n0Oi1i); + n0O1il <= ((NOT rxc(0)) OR wire_w_lg_n0O1iO151w(0)); + n0O1iO <= ((((((wire_w_lg_w_rxd_range651w668w(0) AND rxd(2)) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0O1li <= ((((((wire_w_lg_w_rxd_range651w668w(0) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))); + n0O1ll <= ((((((wire_w_lg_w_rxd_range651w668w(0) AND rxd(2)) AND (NOT rxd(3))) AND (NOT rxd(4))) AND (NOT rxd(5))) AND (NOT rxd(6))) AND (NOT rxd(7))); + n0O1lO <= ((((((wire_w_lg_w_rxd_range651w668w(0) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND (NOT rxd(7))); + n0O1Oi <= ((wire_w_lg_n0O01i139w(0) OR (NOT (wire_nlii_dataout AND (NOT rxc(0))))) OR (NOT (n0O1Ol26 XOR n0O1Ol25))); + n0Oi0l <= ((((((wire_w_lg_w_rxd_range651w668w(0) AND rxd(2)) AND (NOT rxd(3))) AND rxd(4)) AND (NOT rxd(5))) AND rxd(6)) AND (NOT rxd(7))); + n0Oi1i <= (rcxpat_chnl_sel(0) AND rcxpat_chnl_sel(1)); + n0Oi1l <= (wire_w_lg_w_lg_w_lg_n0OiiO114w118w119w(0) AND (n0Oi1O24 XOR n0Oi1O23)); + n0Oiil <= ((NOT rcxpat_chnl_sel(0)) AND rcxpat_chnl_sel(1)); + n0OiiO <= wire_w_lg_w_rcxpat_chnl_sel_range842w847w(0); + n0Oili <= wire_w_lg_w_rxc_range111w113w(0); + n0Oill <= ((NOT rcxpat_chnl_sel(0)) AND wire_w_lg_w_rcxpat_chnl_sel_range844w845w(0)); + n0OilO <= (((((((rxd(0) AND rxd(1)) AND (NOT rxd(2))) AND rxd(3)) AND rxd(4)) AND rxd(5)) AND rxd(6)) AND rxd(7)); + n0OiOl <= '1'; + n0Olli <= (((NOT rbist_sel(0)) AND wire_w_lg_w_rbist_sel_range3w4w(0)) AND (n0Ol0i12 XOR n0Ol0i11)); + n0Olll <= wire_w_lg_w_rbist_sel_range1w9w(0); + n0OllO <= (((NOT rbist_sel(0)) AND rbist_sel(1)) AND (n0Ol1l14 XOR n0Ol1l13)); + n0OlOi <= (n0OlOl OR (rpmadwidth_rx AND rpma_doublewidth_rx)); + n0OlOl <= (wire_w_lg_w_lg_rpmadwidth_rx15w16w(0) AND (n0OlOO6 XOR n0OlOO5)); + selftest_done <= wire_nl1l_dataout; + selftest_err <= wire_nl1i_dataout; + wire_w_rbist_sel_range1w(0) <= rbist_sel(0); + wire_w_rbist_sel_range3w(0) <= rbist_sel(1); + wire_w_rcxpat_chnl_sel_range842w(0) <= rcxpat_chnl_sel(0); + wire_w_rcxpat_chnl_sel_range844w(0) <= rcxpat_chnl_sel(1); + wire_w_rxc_range111w(0) <= rxc(0); + wire_w_rxd_range651w(0) <= rxd(0); + wire_w_rxd_range652w(0) <= rxd(1); + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0li1O47 <= n0li1O48; + END IF; + if (now = 0 ns) then + n0li1O47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0li1O48 <= n0li1O47; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOi45 <= n0lOOi46; + END IF; + if (now = 0 ns) then + n0lOOi45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOi46 <= n0lOOi45; + END IF; + END PROCESS; + wire_n0lOOi46_w_lg_w_lg_q339w340w(0) <= wire_n0lOOi46_w_lg_q339w(0) AND ni0lO; + wire_n0lOOi46_w_lg_q339w(0) <= n0lOOi46 XOR n0lOOi45; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOl43 <= n0lOOl44; + END IF; + if (now = 0 ns) then + n0lOOl43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOl44 <= n0lOOl43; + END IF; + END PROCESS; + wire_n0lOOl44_w_lg_w_lg_q314w315w(0) <= wire_n0lOOl44_w_lg_q314w(0) AND wire_n10li_dataout; + wire_n0lOOl44_w_lg_q314w(0) <= n0lOOl44 XOR n0lOOl43; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOO41 <= n0lOOO42; + END IF; + if (now = 0 ns) then + n0lOOO41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOO42 <= n0lOOO41; + END IF; + END PROCESS; + wire_n0lOOO42_w_lg_w_lg_q309w310w(0) <= wire_n0lOOO42_w_lg_q309w(0) AND wire_n1ill_dataout; + wire_n0lOOO42_w_lg_q309w(0) <= n0lOOO42 XOR n0lOOO41; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10i33 <= n0O10i34; + END IF; + if (now = 0 ns) then + n0O10i33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10i34 <= n0O10i33; + END IF; + END PROCESS; + wire_n0O10i34_w_lg_w_lg_q186w187w(0) <= wire_n0O10i34_w_lg_q186w(0) AND wire_n1iOO_dataout; + wire_n0O10i34_w_lg_q186w(0) <= n0O10i34 XOR n0O10i33; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10l31 <= n0O10l32; + END IF; + if (now = 0 ns) then + n0O10l31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10l32 <= n0O10l31; + END IF; + END PROCESS; + wire_n0O10l32_w_lg_w_lg_q177w178w(0) <= wire_n0O10l32_w_lg_q177w(0) AND wire_w_lg_n0O0il132w(0); + wire_n0O10l32_w_lg_q177w(0) <= n0O10l32 XOR n0O10l31; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10O29 <= n0O10O30; + END IF; + if (now = 0 ns) then + n0O10O29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10O30 <= n0O10O29; + END IF; + END PROCESS; + wire_n0O10O30_w_lg_w_lg_q174w175w(0) <= wire_n0O10O30_w_lg_q174w(0) AND wire_w_lg_n0O0iO131w(0); + wire_n0O10O30_w_lg_q174w(0) <= n0O10O30 XOR n0O10O29; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O11i39 <= n0O11i40; + END IF; + if (now = 0 ns) then + n0O11i39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O11i40 <= n0O11i39; + END IF; + END PROCESS; + wire_n0O11i40_w_lg_w_lg_q303w304w(0) <= wire_n0O11i40_w_lg_q303w(0) AND wire_n00il_dataout; + wire_n0O11i40_w_lg_q303w(0) <= n0O11i40 XOR n0O11i39; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O11l37 <= n0O11l38; + END IF; + if (now = 0 ns) then + n0O11l37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O11l38 <= n0O11l37; + END IF; + END PROCESS; + wire_n0O11l38_w_lg_w_lg_q237w238w(0) <= wire_n0O11l38_w_lg_q237w(0) AND n0O0ii; + wire_n0O11l38_w_lg_q237w(0) <= n0O11l38 XOR n0O11l37; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O11O35 <= n0O11O36; + END IF; + if (now = 0 ns) then + n0O11O35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O11O36 <= n0O11O35; + END IF; + END PROCESS; + wire_n0O11O36_w_lg_w_lg_q191w192w(0) <= wire_n0O11O36_w_lg_q191w(0) AND wire_n1i1i_dataout; + wire_n0O11O36_w_lg_q191w(0) <= n0O11O36 XOR n0O11O35; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1ii27 <= n0O1ii28; + END IF; + if (now = 0 ns) then + n0O1ii27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1ii28 <= n0O1ii27; + END IF; + END PROCESS; + wire_n0O1ii28_w_lg_w_lg_q159w160w(0) <= wire_n0O1ii28_w_lg_q159w(0) AND nii1i; + wire_n0O1ii28_w_lg_q159w(0) <= n0O1ii28 XOR n0O1ii27; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1Ol25 <= n0O1Ol26; + END IF; + if (now = 0 ns) then + n0O1Ol25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1Ol26 <= n0O1Ol25; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Oi0O21 <= n0Oi0O22; + END IF; + if (now = 0 ns) then + n0Oi0O21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Oi0O22 <= n0Oi0O21; + END IF; + END PROCESS; + wire_n0Oi0O22_w_lg_w_lg_q116w117w(0) <= NOT wire_n0Oi0O22_w_lg_q116w(0); + wire_n0Oi0O22_w_lg_q116w(0) <= n0Oi0O22 XOR n0Oi0O21; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Oi1O23 <= n0Oi1O24; + END IF; + if (now = 0 ns) then + n0Oi1O23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Oi1O24 <= n0Oi1O23; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OiOi19 <= n0OiOi20; + END IF; + if (now = 0 ns) then + n0OiOi19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OiOi20 <= n0OiOi19; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OiOO17 <= n0OiOO18; + END IF; + if (now = 0 ns) then + n0OiOO17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OiOO18 <= n0OiOO17; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol0i11 <= n0Ol0i12; + END IF; + if (now = 0 ns) then + n0Ol0i11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol0i12 <= n0Ol0i11; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol0O10 <= n0Ol0O9; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol0O9 <= n0Ol0O10; + END IF; + if (now = 0 ns) then + n0Ol0O9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol1i15 <= n0Ol1i16; + END IF; + if (now = 0 ns) then + n0Ol1i15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol1i16 <= n0Ol1i15; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol1l13 <= n0Ol1l14; + END IF; + if (now = 0 ns) then + n0Ol1l13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Ol1l14 <= n0Ol1l13; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Olil7 <= n0Olil8; + END IF; + if (now = 0 ns) then + n0Olil7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Olil8 <= n0Olil7; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OlOO5 <= n0OlOO6; + END IF; + if (now = 0 ns) then + n0OlOO5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OlOO6 <= n0OlOO5; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO0i1 <= n0OO0i2; + END IF; + if (now = 0 ns) then + n0OO0i1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO0i2 <= n0OO0i1; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO1l3 <= n0OO1l4; + END IF; + if (now = 0 ns) then + n0OO1l3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO1l4 <= n0OO1l3; + END IF; + END PROCESS; + PROCESS (clk_2, wire_ni01O_CLRN) + BEGIN + IF (wire_ni01O_CLRN = '0') THEN + ni00i <= '0'; + ni01l <= '0'; + ni1lOl <= '0'; + niiilO <= '0'; + niiiOi <= '0'; + niiiOl <= '0'; + niiiOO <= '0'; + niil0i <= '0'; + niil0l <= '0'; + niil0O <= '0'; + niil1i <= '0'; + niil1l <= '0'; + niil1O <= '0'; + niilii <= '0'; + niilil <= '0'; + niiliO <= '0'; + niilli <= '0'; + niilll <= '0'; + niillO <= '0'; + niilOi <= '0'; + niilOl <= '0'; + niiO1i <= '0'; + niiO1l <= '0'; + nll00O <= '0'; + nll0ii <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + ni00i <= wire_nii1O_dataout; + ni01l <= wire_nii1l_dataout; + ni1lOl <= wire_nil0ii_dataout; + niiilO <= wire_nil0il_dataout; + niiiOi <= wire_nil0iO_dataout; + niiiOl <= wire_nil0li_dataout; + niiiOO <= wire_nil0ll_dataout; + niil0i <= wire_nil0OO_dataout; + niil0l <= wire_nili1i_dataout; + niil0O <= wire_nili1l_dataout; + niil1i <= wire_nil0lO_dataout; + niil1l <= wire_nil0Oi_dataout; + niil1O <= wire_nil0Ol_dataout; + niilii <= wire_nili1O_dataout; + niilil <= wire_nili0i_dataout; + niiliO <= wire_nili0l_dataout; + niilli <= wire_nili0O_dataout; + niilll <= wire_niliii_dataout; + niillO <= wire_niliil_dataout; + niilOi <= wire_niliiO_dataout; + niilOl <= wire_nilili_dataout; + niiO1i <= wire_nilill_dataout; + niiO1l <= wire_nililO_dataout; + nll00O <= wire_nlll0l_dataout; + nll0ii <= wire_nlll0O_dataout; + END IF; + END PROCESS; + wire_ni01O_CLRN <= ((n0OiOi20 XOR n0OiOi19) AND wire_w_lg_soft_reset105w(0)); + PROCESS (clk_2, wire_ni0OO_PRN, wire_ni0OO_CLRN) + BEGIN + IF (wire_ni0OO_PRN = '0') THEN + n11Oi <= '1'; + ni00l <= '1'; + ni00O <= '1'; + ni01i <= '1'; + ni0ii <= '1'; + ni0il <= '1'; + ni0iO <= '1'; + ni0li <= '1'; + ni0ll <= '1'; + ni0lO <= '1'; + ni0Oi <= '1'; + ni0Ol <= '1'; + nii1i <= '1'; + niilOO <= '1'; + niiO0l <= '1'; + niiO0O <= '1'; + niiOii <= '1'; + niiOil <= '1'; + niiOiO <= '1'; + niiOli <= '1'; + niiOll <= '1'; + niiOlO <= '1'; + niiOOi <= '1'; + niiOOl <= '1'; + niiOOO <= '1'; + nil00i <= '1'; + nil00l <= '1'; + nil00O <= '1'; + nil01i <= '1'; + nil01l <= '1'; + nil01O <= '1'; + nil10i <= '1'; + nil10l <= '1'; + nil10O <= '1'; + nil11i <= '1'; + nil11l <= '1'; + nil11O <= '1'; + nil1ii <= '1'; + nil1il <= '1'; + nil1iO <= '1'; + nil1li <= '1'; + nil1ll <= '1'; + nil1lO <= '1'; + nil1Oi <= '1'; + nil1Ol <= '1'; + nil1OO <= '1'; + nl1Oll <= '1'; + nll00l <= '1'; + nll0il <= '1'; + nll0iO <= '1'; + nll0li <= '1'; + nll0ll <= '1'; + nll0lO <= '1'; + nll0Oi <= '1'; + nll0Ol <= '1'; + nll0OO <= '1'; + nlli0i <= '1'; + nlli0l <= '1'; + nlli0O <= '1'; + nlli1i <= '1'; + nlli1l <= '1'; + nlli1O <= '1'; + nlliii <= '1'; + nlliil <= '1'; + nlliiO <= '1'; + nllili <= '1'; + nllill <= '1'; + nllilO <= '1'; + nlliOi <= '1'; + nlliOl <= '1'; + nlliOO <= '1'; + nlll0i <= '1'; + nlll1i <= '1'; + nlll1l <= '1'; + nlll1O <= '1'; + ELSIF (wire_ni0OO_CLRN = '0') THEN + n11Oi <= '0'; + ni00l <= '0'; + ni00O <= '0'; + ni01i <= '0'; + ni0ii <= '0'; + ni0il <= '0'; + ni0iO <= '0'; + ni0li <= '0'; + ni0ll <= '0'; + ni0lO <= '0'; + ni0Oi <= '0'; + ni0Ol <= '0'; + nii1i <= '0'; + niilOO <= '0'; + niiO0l <= '0'; + niiO0O <= '0'; + niiOii <= '0'; + niiOil <= '0'; + niiOiO <= '0'; + niiOli <= '0'; + niiOll <= '0'; + niiOlO <= '0'; + niiOOi <= '0'; + niiOOl <= '0'; + niiOOO <= '0'; + nil00i <= '0'; + nil00l <= '0'; + nil00O <= '0'; + nil01i <= '0'; + nil01l <= '0'; + nil01O <= '0'; + nil10i <= '0'; + nil10l <= '0'; + nil10O <= '0'; + nil11i <= '0'; + nil11l <= '0'; + nil11O <= '0'; + nil1ii <= '0'; + nil1il <= '0'; + nil1iO <= '0'; + nil1li <= '0'; + nil1ll <= '0'; + nil1lO <= '0'; + nil1Oi <= '0'; + nil1Ol <= '0'; + nil1OO <= '0'; + nl1Oll <= '0'; + nll00l <= '0'; + nll0il <= '0'; + nll0iO <= '0'; + nll0li <= '0'; + nll0ll <= '0'; + nll0lO <= '0'; + nll0Oi <= '0'; + nll0Ol <= '0'; + nll0OO <= '0'; + nlli0i <= '0'; + nlli0l <= '0'; + nlli0O <= '0'; + nlli1i <= '0'; + nlli1l <= '0'; + nlli1O <= '0'; + nlliii <= '0'; + nlliil <= '0'; + nlliiO <= '0'; + nllili <= '0'; + nllill <= '0'; + nllilO <= '0'; + nlliOi <= '0'; + nlliOl <= '0'; + nlliOO <= '0'; + nlll0i <= '0'; + nlll1i <= '0'; + nlll1l <= '0'; + nlll1O <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + IF (rbist_clr_rx = '0') THEN + n11Oi <= ni01i; + ni00l <= wire_n11ll_o; + ni00O <= wire_nii0i_dataout; + ni01i <= sync_status; + ni0ii <= wire_nii0l_dataout; + ni0il <= wire_nii0O_dataout; + ni0iO <= wire_niiii_dataout; + ni0li <= wire_niiil_dataout; + ni0ll <= wire_n101i_o; + ni0lO <= wire_n101l_o; + ni0Oi <= wire_n101O_o; + ni0Ol <= wire_n100i_o; + nii1i <= wire_n100l_o; + niilOO <= wire_ni1iiO_o; + niiO0l <= wire_niO1Oi_dataout; + niiO0O <= wire_niO1Ol_dataout; + niiOii <= wire_niO1OO_dataout; + niiOil <= wire_niO01i_dataout; + niiOiO <= wire_niO01l_dataout; + niiOli <= wire_niO01O_dataout; + niiOll <= wire_niO00i_dataout; + niiOlO <= wire_niO10i_dataout; + niiOOi <= wire_niO10l_dataout; + niiOOl <= wire_niO10O_dataout; + niiOOO <= wire_niO1ii_dataout; + nil00i <= wire_ni1iOi_o; + nil00l <= wire_ni1iOl_o; + nil00O <= wire_ni1iOO_o; + nil01i <= nil00l; + nil01l <= nil00O; + nil01O <= wire_ni1ilO_o; + nil10i <= wire_niO1ll_dataout; + nil10l <= wire_niO00l_dataout; + nil10O <= wire_niO00O_dataout; + nil11i <= wire_niO1il_dataout; + nil11l <= wire_niO1iO_dataout; + nil11O <= wire_niO1li_dataout; + nil1ii <= wire_niO0ii_dataout; + nil1il <= wire_niO0il_dataout; + nil1iO <= wire_niO0iO_dataout; + nil1li <= wire_niO0li_dataout; + nil1ll <= wire_niO0ll_dataout; + nil1lO <= wire_niO0lO_dataout; + nil1Oi <= wire_niO0Oi_dataout; + nil1Ol <= nil01O; + nil1OO <= nil00i; + nl1Oll <= nll00l; + nll00l <= sync_status; + nll0il <= wire_nl011i_o; + nll0iO <= wire_nlllii_dataout; + nll0li <= wire_nlllil_dataout; + nll0ll <= wire_nllliO_dataout; + nll0lO <= wire_nlllli_dataout; + nll0Oi <= wire_nlllll_dataout; + nll0Ol <= wire_nllllO_dataout; + nll0OO <= wire_nllO0l_dataout; + nlli0i <= wire_nllOli_dataout; + nlli0l <= wire_nllOll_dataout; + nlli0O <= wire_nllOlO_dataout; + nlli1i <= wire_nllO0O_dataout; + nlli1l <= wire_nllOii_dataout; + nlli1O <= wire_nllOiO_dataout; + nlliii <= wire_nlO11O_dataout; + nlliil <= wire_nlO10i_dataout; + nlliiO <= wire_nlO10l_dataout; + nllili <= wire_nlO10O_dataout; + nllill <= wire_nlO1ii_dataout; + nllilO <= wire_nlO1il_dataout; + nlliOi <= wire_nlO1iO_dataout; + nlliOl <= wire_nlO1li_dataout; + nlliOO <= wire_nlO1ll_dataout; + nlll0i <= wire_nl01ii_o; + nlll1i <= wire_nl010i_o; + nlll1l <= wire_nl010l_o; + nlll1O <= wire_nl010O_o; + END IF; + END IF; + END PROCESS; + wire_ni0OO_CLRN <= ((n0Ol1i16 XOR n0Ol1i15) AND wire_w_lg_soft_reset105w(0)); + wire_ni0OO_PRN <= (n0OiOO18 XOR n0OiOO17); + wire_ni0OO_w_lg_w_lg_w_lg_w1242w1243w1244w1245w(0) <= wire_ni0OO_w_lg_w_lg_w1242w1243w1244w(0) AND nlliil; + wire_ni0OO_w_lg_w_lg_w1251w1252w1253w(0) <= wire_ni0OO_w_lg_w1251w1252w(0) AND nlliil; + wire_ni0OO_w_lg_w_lg_w1242w1243w1244w(0) <= wire_ni0OO_w_lg_w1242w1243w(0) AND wire_ni0OO_w_lg_nlliiO1232w(0); + wire_ni0OO_w_lg_w1251w1252w(0) <= wire_ni0OO_w1251w(0) AND nlliiO; + wire_ni0OO_w_lg_w1242w1243w(0) <= wire_ni0OO_w1242w(0) AND wire_ni0OO_w_lg_nllili1230w(0); + wire_ni0OO_w1251w(0) <= wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlliOO1247w1248w1249w1250w(0) AND wire_ni0OO_w_lg_nllili1230w(0); + wire_ni0OO_w1242w(0) <= wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlliOO1222w1238w1240w1241w(0) AND wire_ni0OO_w_lg_nllill1228w(0); + wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlliOO1247w1248w1249w1250w(0) <= wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1247w1248w1249w(0) AND wire_ni0OO_w_lg_nllill1228w(0); + wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlli0O990w992w993w994w(0) <= wire_ni0OO_w_lg_w_lg_w_lg_nlli0O990w992w993w(0) AND nlli1O; + wire_ni0OO_w_lg_w_lg_w_lg_w_lg_nlliOO1222w1238w1240w1241w(0) <= wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1222w1238w1240w(0) AND wire_ni0OO_w_lg_nllilO1226w(0); + wire_ni0OO_w_lg_w_lg_w_lg_ni0li837w838w839w(0) <= wire_ni0OO_w_lg_w_lg_ni0li837w838w(0) AND ni0ii; + wire_ni0OO_w_lg_w_lg_w_lg_nil1Oi2312w2314w2315w(0) <= wire_ni0OO_w_lg_w_lg_nil1Oi2312w2314w(0) AND nil1li; + wire_ni0OO_w_lg_w_lg_w_lg_nlli0O995w996w997w(0) <= wire_ni0OO_w_lg_w_lg_nlli0O995w996w(0) AND nlli1O; + wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1247w1248w1249w(0) <= wire_ni0OO_w_lg_w_lg_nlliOO1247w1248w(0) AND wire_ni0OO_w_lg_nllilO1226w(0); + wire_ni0OO_w_lg_w_lg_w_lg_nlli0O990w992w993w(0) <= wire_ni0OO_w_lg_w_lg_nlli0O990w992w(0) AND nlli0i; + wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1222w1224w1225w(0) <= wire_ni0OO_w_lg_w_lg_nlliOO1222w1224w(0) AND nlliOi; + wire_ni0OO_w_lg_w_lg_w_lg_nlliOO1222w1238w1240w(0) <= wire_ni0OO_w_lg_w_lg_nlliOO1222w1238w(0) AND wire_ni0OO_w_lg_nlliOi1239w(0); + wire_ni0OO_w_lg_w_lg_ni0li837w838w(0) <= wire_ni0OO_w_lg_ni0li837w(0) AND ni0il; + wire_ni0OO_w_lg_w_lg_nil1Oi2312w2314w(0) <= wire_ni0OO_w_lg_nil1Oi2312w(0) AND wire_ni0OO_w_lg_nil1ll2313w(0); + wire_ni0OO_w_lg_w_lg_nlli0O995w996w(0) <= wire_ni0OO_w_lg_nlli0O995w(0) AND nlli0i; + wire_ni0OO_w_lg_w_lg_nlliOO1247w1248w(0) <= wire_ni0OO_w_lg_nlliOO1247w(0) AND wire_ni0OO_w_lg_nlliOi1239w(0); + wire_ni0OO_w_lg_w_lg_nll0Ol1343w1344w(0) <= wire_ni0OO_w_lg_nll0Ol1343w(0) AND nll0Oi; + wire_ni0OO_w_lg_w_lg_nlli0O990w992w(0) <= wire_ni0OO_w_lg_nlli0O990w(0) AND wire_ni0OO_w_lg_nlli0l991w(0); + wire_ni0OO_w_lg_w_lg_nlliOO1222w1224w(0) <= wire_ni0OO_w_lg_nlliOO1222w(0) AND wire_ni0OO_w_lg_nlliOl1223w(0); + wire_ni0OO_w_lg_w_lg_nlliOO1222w1238w(0) <= wire_ni0OO_w_lg_nlliOO1222w(0) AND nlliOl; + wire_ni0OO_w_lg_ni0li837w(0) <= ni0li AND ni0iO; + wire_ni0OO_w_lg_nil1Oi2312w(0) <= nil1Oi AND wire_ni0OO_w_lg_nil1lO2311w(0); + wire_ni0OO_w_lg_nll0Ol1352w(0) <= nll0Ol AND wire_ni0OO_w_lg_nll0Oi1351w(0); + wire_ni0OO_w_lg_nlli0O995w(0) <= nlli0O AND wire_ni0OO_w_lg_nlli0l991w(0); + wire_ni0OO_w_lg_nlliOO1247w(0) <= nlliOO AND wire_ni0OO_w_lg_nlliOl1223w(0); + wire_ni0OO_w_lg_ni00O840w(0) <= NOT ni00O; + wire_ni0OO_w_lg_nil10l2331w(0) <= NOT nil10l; + wire_ni0OO_w_lg_nil10O2322w(0) <= NOT nil10O; + wire_ni0OO_w_lg_nil1ii2320w(0) <= NOT nil1ii; + wire_ni0OO_w_lg_nil1il2318w(0) <= NOT nil1il; + wire_ni0OO_w_lg_nil1iO2316w(0) <= NOT nil1iO; + wire_ni0OO_w_lg_nil1li2325w(0) <= NOT nil1li; + wire_ni0OO_w_lg_nil1ll2313w(0) <= NOT nil1ll; + wire_ni0OO_w_lg_nil1lO2311w(0) <= NOT nil1lO; + wire_ni0OO_w_lg_nll0ll1347w(0) <= NOT nll0ll; + wire_ni0OO_w_lg_nll0lO1345w(0) <= NOT nll0lO; + wire_ni0OO_w_lg_nll0Oi1351w(0) <= NOT nll0Oi; + wire_ni0OO_w_lg_nll0Ol1343w(0) <= NOT nll0Ol; + wire_ni0OO_w_lg_nlli0l991w(0) <= NOT nlli0l; + wire_ni0OO_w_lg_nlli0O990w(0) <= NOT nlli0O; + wire_ni0OO_w_lg_nlli1l1296w(0) <= NOT nlli1l; + wire_ni0OO_w_lg_nlli1O1273w(0) <= NOT nlli1O; + wire_ni0OO_w_lg_nlliii1236w(0) <= NOT nlliii; + wire_ni0OO_w_lg_nlliil1234w(0) <= NOT nlliil; + wire_ni0OO_w_lg_nlliiO1232w(0) <= NOT nlliiO; + wire_ni0OO_w_lg_nllili1230w(0) <= NOT nllili; + wire_ni0OO_w_lg_nllill1228w(0) <= NOT nllill; + wire_ni0OO_w_lg_nllilO1226w(0) <= NOT nllilO; + wire_ni0OO_w_lg_nlliOi1239w(0) <= NOT nlliOi; + wire_ni0OO_w_lg_nlliOl1223w(0) <= NOT nlliOl; + wire_ni0OO_w_lg_nlliOO1222w(0) <= NOT nlliOO; + PROCESS (clk_2, soft_reset, wire_niiO1O_CLRN) + BEGIN + IF (soft_reset = '1') THEN + niiO0i <= '1'; + ELSIF (wire_niiO1O_CLRN = '0') THEN + niiO0i <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + IF (rbist_clr_rx = '0') THEN + niiO0i <= wire_niO1lO_dataout; + END IF; + END IF; + if (now = 0 ns) then + niiO0i <= '1' after 1 ps; + end if; + END PROCESS; + wire_niiO1O_CLRN <= (n0li1O48 XOR n0li1O47); + wire_n000i_dataout <= ni01l OR wire_w_lg_n0O01O137w(0); + wire_n000l_dataout <= ni00i OR wire_w_lg_n0O01O137w(0); + wire_n000O_dataout <= wire_n00lO_dataout OR wire_w_lg_n0O01O137w(0); + wire_n001i_dataout <= nii1i OR n0Oi1i; + wire_n001l_dataout <= wire_n00ll_dataout AND NOT(wire_w_lg_n0O01O137w(0)); + wire_n001O_dataout <= wire_n0i1l_dataout AND NOT(wire_w_lg_n0O01O137w(0)); + wire_n00i_dataout <= nlll0i WHEN n0Olll = '1' ELSE wire_n0iO_dataout; + wire_n00ii_dataout <= wire_n00Oi_dataout AND NOT(wire_w_lg_n0O01O137w(0)); + wire_n00il_dataout <= wire_n00Ol_dataout OR wire_w_lg_n0O01O137w(0); + wire_n00iO_dataout <= wire_n00OO_dataout AND NOT(wire_w_lg_n0O01O137w(0)); + wire_n00l_dataout <= wire_n0li_dataout AND NOT(n0Olll); + wire_n00li_dataout <= wire_n0i1i_dataout OR wire_w_lg_n0O01O137w(0); + wire_n00ll_dataout <= wire_w_lg_n0O00i136w(0) AND n0OlOi; + wire_n00lO_dataout <= wire_n1Oii_dataout OR NOT(n0OlOi); + wire_n00O_dataout <= ni0ll AND n0OllO; + wire_n00Oi_dataout <= wire_n1Oil_dataout OR NOT(n0OlOi); + wire_n00Ol_dataout <= wire_n1OiO_dataout OR NOT(n0OlOi); + wire_n00OO_dataout <= wire_n1Oli_dataout OR NOT(n0OlOi); + wire_n010i_dataout <= wire_n01iO_dataout AND NOT(n0OiiO); + wire_n010l_dataout <= wire_n01li_dataout AND NOT(n0OiiO); + wire_n010O_dataout <= wire_n01ll_dataout OR n0OiiO; + wire_n011i_dataout <= wire_n010O_dataout OR n0Oill; + wire_n011l_dataout <= wire_n01ii_dataout OR n0OiiO; + wire_n011O_dataout <= wire_n01il_dataout AND NOT(n0OiiO); + wire_n01i_dataout <= nlll1i WHEN n0Olll = '1' ELSE wire_n00O_dataout; + wire_n01ii_dataout <= wire_n01lO_dataout AND NOT(n0Oiil); + wire_n01il_dataout <= wire_n01Oi_dataout OR n0Oiil; + wire_n01iO_dataout <= wire_n01Ol_dataout AND NOT(n0Oiil); + wire_n01l_dataout <= nlll1l WHEN n0Olll = '1' ELSE wire_n0ii_dataout; + wire_n01li_dataout <= wire_n01OO_dataout AND NOT(n0Oiil); + wire_n01ll_dataout <= wire_n001i_dataout OR n0Oiil; + wire_n01lO_dataout <= ni0ll OR n0Oi1i; + wire_n01O_dataout <= nlll1O WHEN n0Olll = '1' ELSE wire_n0il_dataout; + wire_n01Oi_dataout <= ni0lO OR n0Oi1i; + wire_n01Ol_dataout <= ni0Oi AND NOT(n0Oi1i); + wire_n01OO_dataout <= ni0Ol AND NOT(n0Oi1i); + wire_n0i_dataout <= rxd(33) WHEN n0OlOl = '1' ELSE rxd(17); + wire_n0i0i_dataout <= ni00i OR wire_w_lg_n0O00l135w(0); + wire_n0i0l_dataout <= ni01l OR wire_w_lg_n0O00O134w(0); + wire_n0i0O_dataout <= ni00i OR wire_w_lg_n0O00O134w(0); + wire_n0i1i_dataout <= wire_n1Oll_dataout AND n0OlOi; + wire_n0i1l_dataout <= n0O00i AND n0OlOi; + wire_n0i1O_dataout <= ni01l OR wire_w_lg_n0O00l135w(0); + wire_n0ii_dataout <= ni0lO AND n0OllO; + wire_n0iii_dataout <= wire_w_lg_n0OlOi124w(0) OR wire_w_lg_n0O00O134w(0); + wire_n0iil_dataout <= n0OlOi AND NOT(wire_w_lg_n0O00O134w(0)); + wire_n0iiO_dataout <= ni01l OR wire_w_lg_n0O0ii133w(0); + wire_n0il_dataout <= ni0Oi AND n0OllO; + wire_n0ili_dataout <= ni00i OR wire_w_lg_n0O0ii133w(0); + wire_n0ill_dataout <= ni01l OR wire_w_lg_n0O0il132w(0); + wire_n0ilO_dataout <= ni00i OR wire_w_lg_n0O0il132w(0); + wire_n0iO_dataout <= ni0Ol AND n0OllO; + wire_n0iOi_dataout <= wire_w_lg_n0OlOi124w(0) OR wire_w_lg_n0O0il132w(0); + wire_n0iOl_dataout <= wire_w_lg_n0OlOi124w(0) AND NOT(wire_w_lg_n0O0il132w(0)); + wire_n0iOO_dataout <= n0OlOi OR wire_w_lg_n0O0il132w(0); + wire_n0l_dataout <= rxd(34) WHEN n0OlOl = '1' ELSE rxd(18); + wire_n0l0i_dataout <= ni00i OR wire_w_lg_n0O0li130w(0); + wire_n0l0l_dataout <= wire_w_lg_n0OlOi124w(0) OR wire_w_lg_n0O0li130w(0); + wire_n0l0O_dataout <= n0OlOi AND NOT(wire_w_lg_n0O0li130w(0)); + wire_n0l1i_dataout <= ni01l OR wire_w_lg_n0O0iO131w(0); + wire_n0l1l_dataout <= ni00i OR wire_w_lg_n0O0iO131w(0); + wire_n0l1O_dataout <= ni01l OR wire_w_lg_n0O0li130w(0); + wire_n0li_dataout <= nii1i AND n0OllO; + wire_n0lii_dataout <= ni01l OR wire_w_lg_n0O0ll129w(0); + wire_n0lil_dataout <= ni00i OR wire_w_lg_n0O0ll129w(0); + wire_n0liO_dataout <= ni01l OR wire_w_lg_n0O0lO128w(0); + wire_n0lli_dataout <= ni00i OR wire_w_lg_n0O0lO128w(0); + wire_n0lll_dataout <= wire_w_lg_n0OlOi124w(0) AND NOT(wire_w_lg_n0O0lO128w(0)); + wire_n0llO_dataout <= wire_w_lg_n0OlOi124w(0) OR wire_w_lg_n0O0lO128w(0); + wire_n0lOi_dataout <= n0OlOi AND NOT(wire_w_lg_n0O0lO128w(0)); + wire_n0lOl_dataout <= ni01l OR wire_w_lg_n0O0Oi127w(0); + wire_n0lOO_dataout <= ni00i OR wire_w_lg_n0O0Oi127w(0); + wire_n0O_dataout <= rxd(35) WHEN n0OlOl = '1' ELSE rxd(19); + wire_n0O0i_dataout <= n0OlOi AND NOT(wire_w_lg_n0O0Ol126w(0)); + wire_n0O0l_dataout <= ni0ll AND NOT(wire_w_lg_n0Oi1i125w(0)); + wire_n0O0O_dataout <= ni0lO AND NOT(wire_w_lg_n0Oi1i125w(0)); + wire_n0O1i_dataout <= ni01l OR wire_w_lg_n0O0Ol126w(0); + wire_n0O1l_dataout <= ni00i OR wire_w_lg_n0O0Ol126w(0); + wire_n0O1O_dataout <= wire_w_lg_n0OlOi124w(0) OR wire_w_lg_n0O0Ol126w(0); + wire_n0Oi_dataout <= ni1lOl AND n0Olli; + wire_n0Oii_dataout <= ni0Oi OR wire_w_lg_n0Oi1i125w(0); + wire_n0Oil_dataout <= ni0Ol AND NOT(wire_w_lg_n0Oi1i125w(0)); + wire_n0OiO_dataout <= nii1i AND NOT(wire_w_lg_n0Oi1i125w(0)); + wire_n0Ol_dataout <= niiilO AND n0Olli; + wire_n0Oli_dataout <= wire_n0OOO_dataout AND NOT(n0Oili); + wire_n0Oll_dataout <= wire_w_lg_n0OlOi124w(0) WHEN n0Oili = '1' ELSE wire_ni11i_dataout; + wire_n0OlO_dataout <= n0OlOi WHEN n0Oili = '1' ELSE wire_ni11l_dataout; + wire_n0OO_dataout <= niiiOi AND n0Olli; + wire_n0OOi_dataout <= wire_ni11O_dataout AND NOT(n0Oili); + wire_n0OOl_dataout <= wire_ni10i_dataout AND NOT(n0Oili); + wire_n0OOO_dataout <= wire_ni10l_dataout AND NOT(n0Oi1l); + wire_n100O_dataout <= ni00i AND NOT(wire_ni_w_lg_dataout153w(0)); + wire_n10ii_dataout <= ni01l AND NOT(wire_ni_w_lg_dataout153w(0)); + wire_n10il_dataout <= ni0ll AND NOT(wire_ni_w_lg_dataout153w(0)); + wire_n10iO_dataout <= ni0lO AND NOT(wire_ni_w_lg_dataout153w(0)); + wire_n10li_dataout <= ni0Oi AND NOT(wire_ni_w_lg_dataout153w(0)); + wire_n10ll_dataout <= ni0Ol AND NOT(wire_ni_w_lg_dataout153w(0)); + wire_n10lO_dataout <= nii1i AND NOT(wire_ni_w_lg_dataout153w(0)); + wire_n10Oi_dataout <= ni00l OR NOT(n0O1il); + wire_n10Ol_dataout <= wire_n1i1l_dataout OR n0O1il; + wire_n10OO_dataout <= ni00i OR n0O1il; + wire_n1i0i_dataout <= ni00l OR NOT(wire_w_lg_n0O1li150w(0)); + wire_n1i0l_dataout <= wire_n1i1l_dataout OR wire_w_lg_n0O1li150w(0); + wire_n1i0O_dataout <= ni00i OR wire_w_lg_n0O1li150w(0); + wire_n1i1i_dataout <= ni00l OR n0O1il; + wire_n1i1l_dataout <= ni01l OR ni00l; + wire_n1iii_dataout <= ni00l OR wire_w_lg_n0O1li150w(0); + wire_n1iil_dataout <= ni00l OR NOT(wire_w_lg_n0O1ll149w(0)); + wire_n1iiO_dataout <= wire_n1i1l_dataout OR wire_w_lg_n0O1ll149w(0); + wire_n1ili_dataout <= ni00i OR wire_w_lg_n0O1ll149w(0); + wire_n1ill_dataout <= ni00l OR wire_w_lg_n0O1ll149w(0); + wire_n1ilO_dataout <= ni00l OR NOT(wire_w_lg_n0O1lO148w(0)); + wire_n1iOi_dataout <= wire_n1i1l_dataout OR wire_w_lg_n0O1lO148w(0); + wire_n1iOl_dataout <= ni00i OR wire_w_lg_n0O1lO148w(0); + wire_n1iOO_dataout <= ni00l OR wire_w_lg_n0O1lO148w(0); + wire_n1l_dataout <= rxc(2) WHEN n0OlOl = '1' ELSE rxc(1); + wire_n1l0i_dataout <= wire_w_lg_n0O01i139w(0) OR n0OlOi; + wire_n1l0l_dataout <= wire_n1lll_dataout OR NOT(n0OlOi); + wire_n1l0O_dataout <= ni01l OR wire_w_lg_n0O01i139w(0); + wire_n1l1i_dataout <= wire_n1lil_dataout WHEN n0OlOi = '1' ELSE ni00l; + wire_n1l1l_dataout <= wire_n1liO_dataout WHEN n0OlOi = '1' ELSE wire_n1l0O_dataout; + wire_n1l1O_dataout <= wire_n1lli_dataout WHEN n0OlOi = '1' ELSE wire_n1lii_dataout; + wire_n1lii_dataout <= ni00i OR wire_w_lg_n0O01i139w(0); + wire_n1lil_dataout <= ni00l OR NOT(n0O1Oi); + wire_n1liO_dataout <= wire_n1i1l_dataout OR n0O1Oi; + wire_n1ll_dataout <= nil01O WHEN n0Olli = '1' ELSE wire_n01i_dataout; + wire_n1lli_dataout <= ni00i OR n0O1Oi; + wire_n1lll_dataout <= ni00l OR n0O1Oi; + wire_n1lO_dataout <= nil00i WHEN n0Olli = '1' ELSE wire_n01l_dataout; + wire_n1lOi_dataout <= wire_w_lg_n0O00i136w(0) AND NOT(wire_w_lg_n0O01l138w(0)); + wire_n1lOl_dataout <= n0O00i AND NOT(wire_w_lg_n0O01l138w(0)); + wire_n1lOO_dataout <= ni01l OR wire_w_lg_n0O01l138w(0); + wire_n1O_dataout <= rxd(32) WHEN n0OlOl = '1' ELSE rxd(16); + wire_n1O0i_dataout <= wire_n1OiO_dataout OR wire_w_lg_n0O01l138w(0); + wire_n1O0l_dataout <= wire_n1Oli_dataout AND NOT(wire_w_lg_n0O01l138w(0)); + wire_n1O0O_dataout <= wire_n1Oll_dataout OR wire_w_lg_n0O01l138w(0); + wire_n1O1i_dataout <= ni00i OR wire_w_lg_n0O01l138w(0); + wire_n1O1l_dataout <= wire_n1Oii_dataout OR wire_w_lg_n0O01l138w(0); + wire_n1O1O_dataout <= wire_n1Oil_dataout AND NOT(wire_w_lg_n0O01l138w(0)); + wire_n1Oi_dataout <= nil00l WHEN n0Olli = '1' ELSE wire_n01O_dataout; + wire_n1Oii_dataout <= wire_n1OlO_dataout AND n0O00i; + wire_n1Oil_dataout <= wire_n1OOi_dataout AND n0O00i; + wire_n1OiO_dataout <= wire_n1OOl_dataout OR NOT(n0O00i); + wire_n1Ol_dataout <= nil00O WHEN n0Olli = '1' ELSE wire_n00i_dataout; + wire_n1Oli_dataout <= wire_n1OOO_dataout AND n0O00i; + wire_n1Oll_dataout <= wire_n011i_dataout AND n0O00i; + wire_n1OlO_dataout <= wire_n011l_dataout AND NOT(n0Oill); + wire_n1OO_dataout <= wire_n00l_dataout AND NOT(n0Olli); + wire_n1OOi_dataout <= wire_n011O_dataout AND NOT(n0Oill); + wire_n1OOl_dataout <= wire_n010i_dataout AND NOT(n0Oill); + wire_n1OOO_dataout <= wire_n010l_dataout AND NOT(n0Oill); + wire_ni_dataout <= rbisten_rx AND (((NOT rbist_sel(0)) AND rbist_sel(1)) AND (n0OO1l4 XOR n0OO1l3)); + wire_ni_w_lg_dataout403w(0) <= wire_ni_dataout AND n11Oi; + wire_ni_w_lg_dataout153w(0) <= NOT wire_ni_dataout; + wire_ni000i_dataout <= n0l11O WHEN n0OlOi = '1' ELSE n0l11i; + wire_ni000l_dataout <= niiO1i OR n0l11i; + wire_ni000O_dataout <= niiO1l OR n0l11i; + wire_ni001i_dataout <= wire_ni00il_dataout WHEN n0OlOi = '1' ELSE wire_ni000l_dataout; + wire_ni001l_dataout <= wire_ni00iO_dataout WHEN n0OlOi = '1' ELSE wire_ni000O_dataout; + wire_ni001O_dataout <= n0l11i OR n0OlOi; + wire_ni00il_dataout <= niiO1i OR n0l11O; + wire_ni00iO_dataout <= niiO1l OR n0l11O; + wire_ni00ll_dataout <= niiO1i OR n0l10l; + wire_ni00lO_dataout <= niiO1l OR n0l10l; + wire_ni00Ol_dataout <= wire_ni0iii_dataout WHEN n0OlOi = '1' ELSE wire_ni0i0i_dataout; + wire_ni00OO_dataout <= wire_ni0iil_dataout WHEN n0OlOi = '1' ELSE wire_ni0i0l_dataout; + wire_ni010i_dataout <= n0iOli OR n0OlOi; + wire_ni010l_dataout <= wire_w_lg_n0iOlO2047w(0) WHEN n0OlOi = '1' ELSE wire_w_lg_n0iOli2046w(0); + wire_ni010O_dataout <= n0iOlO WHEN n0OlOi = '1' ELSE n0iOli; + wire_ni011l_dataout <= wire_ni01li_dataout WHEN n0OlOi = '1' ELSE wire_ni01ii_dataout; + wire_ni011O_dataout <= wire_ni01ll_dataout WHEN n0OlOi = '1' ELSE wire_ni01il_dataout; + wire_ni01ii_dataout <= niiO1i OR n0iOli; + wire_ni01il_dataout <= niiO1l OR n0iOli; + wire_ni01li_dataout <= niiO1i OR n0iOlO; + wire_ni01ll_dataout <= niiO1l OR n0iOlO; + wire_ni01Oi_dataout <= niiO1i OR n0iOOl; + wire_ni01Ol_dataout <= niiO1l OR n0iOOl; + wire_ni0i_dataout <= niil1l AND n0Olli; + wire_ni0i0i_dataout <= niiO1i OR n0l1ii; + wire_ni0i0l_dataout <= niiO1l OR n0l1ii; + wire_ni0i1i_dataout <= n0l1ii OR n0OlOi; + wire_ni0i1l_dataout <= wire_w_lg_n0l1iO2033w(0) WHEN n0OlOi = '1' ELSE wire_w_lg_n0l1ii2032w(0); + wire_ni0i1O_dataout <= n0l1iO WHEN n0OlOi = '1' ELSE n0l1ii; + wire_ni0iii_dataout <= niiO1i OR n0l1iO; + wire_ni0iil_dataout <= niiO1l OR n0l1iO; + wire_ni0ili_dataout <= niiO1i OR n0l1ll; + wire_ni0ill_dataout <= niiO1l OR n0l1ll; + wire_ni0iOi_dataout <= wire_ni0l0l_dataout WHEN n0OlOi = '1' ELSE wire_ni0l1l_dataout; + wire_ni0iOl_dataout <= wire_ni0l0O_dataout WHEN n0OlOi = '1' ELSE wire_ni0l1O_dataout; + wire_ni0iOO_dataout <= n0l1Oi OR n0OlOi; + wire_ni0l_dataout <= niil1O AND n0Olli; + wire_ni0l0l_dataout <= niiO1i OR n0l01i; + wire_ni0l0O_dataout <= niiO1l OR n0l01i; + wire_ni0l1i_dataout <= n0l01i WHEN n0OlOi = '1' ELSE n0l1Oi; + wire_ni0l1l_dataout <= niiO1i OR n0l1Oi; + wire_ni0l1O_dataout <= niiO1l OR n0l1Oi; + wire_ni0lil_dataout <= niiO1i OR n0l0ii; + wire_ni0liO_dataout <= niiO1l OR n0l0ii; + wire_ni0lli_dataout <= wire_ni0lOl_dataout OR n0l0ii; + wire_ni0lll_dataout <= wire_ni0lOO_dataout AND NOT(n0l0ii); + wire_ni0llO_dataout <= wire_ni0O1i_dataout OR n0l0ii; + wire_ni0lOi_dataout <= wire_ni0O1l_dataout OR n0l0ii; + wire_ni0lOl_dataout <= wire_ni0O1O_dataout OR n0l00l; + wire_ni0lOO_dataout <= wire_ni0O0i_dataout OR n0l00l; + wire_ni0O_dataout <= niil0i AND n0Olli; + wire_ni0O0i_dataout <= nil00i OR n0l00i; + wire_ni0O0l_dataout <= nil00l AND NOT(n0l00i); + wire_ni0O0O_dataout <= nil00O AND NOT(n0l00i); + wire_ni0O1i_dataout <= wire_ni0O0l_dataout AND NOT(n0l00l); + wire_ni0O1l_dataout <= wire_ni0O0O_dataout AND NOT(n0l00l); + wire_ni0O1O_dataout <= nil01O OR n0l00i; + wire_ni0OiO_dataout <= wire_nii11i_dataout OR n0l0Ol; + wire_ni0Oli_dataout <= niiO1i OR n0l0Ol; + wire_ni0Oll_dataout <= niiO1l OR n0l0Ol; + wire_ni0OlO_dataout <= wire_nii11l_dataout OR n0l0Ol; + wire_ni0OOi_dataout <= wire_nii11O_dataout AND NOT(n0l0Ol); + wire_ni0OOl_dataout <= wire_nii10i_dataout OR n0l0Ol; + wire_ni0OOO_dataout <= wire_nii10l_dataout OR n0l0Ol; + wire_ni10i_dataout <= wire_ni1iO_dataout AND NOT(n0Oi1l); + wire_ni10l_dataout <= wire_w_lg_n0OlOi124w(0) WHEN n0O0OO = '1' ELSE ni0ll; + wire_ni10O_dataout <= wire_w_lg_n0OlOi124w(0) WHEN n0O0OO = '1' ELSE ni0lO; + wire_ni11i_dataout <= wire_w_lg_n0OlOi124w(0) WHEN n0Oi1l = '1' ELSE wire_ni10O_dataout; + wire_ni11l_dataout <= n0OlOi WHEN n0Oi1l = '1' ELSE wire_ni1ii_dataout; + wire_ni11O_dataout <= wire_ni1il_dataout AND NOT(n0Oi1l); + wire_ni1i_dataout <= niiiOl AND n0Olli; + wire_ni1ii_dataout <= n0OlOi WHEN n0O0OO = '1' ELSE ni0Oi; + wire_ni1il_dataout <= ni0Ol AND NOT(n0O0OO); + wire_ni1iO_dataout <= nii1i AND NOT(n0O0OO); + wire_ni1l_dataout <= niiiOO AND n0Olli; + wire_ni1l0i_dataout <= nil01O AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_ni1l0l_dataout <= nil00i AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_ni1l0O_dataout <= nil00l AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_ni1l1i_dataout <= niilOO AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_ni1l1l_dataout <= niiO1i AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_ni1l1O_dataout <= niiO1l AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_ni1lii_dataout <= nil00O AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_ni1lil_dataout <= niilOO OR NOT(n0iO1l); + wire_ni1liO_dataout <= niiO1i OR n0iO1l; + wire_ni1lli_dataout <= wire_ni1llO_dataout OR n0iO1l; + wire_ni1lll_dataout <= niilOO OR n0iO1l; + wire_ni1llO_dataout <= niiO1l OR niilOO; + wire_ni1lOO_dataout <= wire_ni1OiO_dataout WHEN n0OlOi = '1' ELSE niilOO; + wire_ni1O_dataout <= niil1i AND n0Olli; + wire_ni1O0i_dataout <= n0iO0i OR n0OlOi; + wire_ni1O0l_dataout <= wire_ni1OlO_dataout OR NOT(n0OlOi); + wire_ni1O0O_dataout <= niiO1i OR n0iO0i; + wire_ni1O1i_dataout <= n0iO0O WHEN n0OlOi = '1' ELSE n0iO0i; + wire_ni1O1l_dataout <= wire_ni1Oli_dataout WHEN n0OlOi = '1' ELSE wire_ni1O0O_dataout; + wire_ni1O1O_dataout <= wire_ni1Oll_dataout WHEN n0OlOi = '1' ELSE wire_ni1Oii_dataout; + wire_ni1Oii_dataout <= niiO1l OR n0iO0i; + wire_ni1OiO_dataout <= niilOO OR NOT(n0iO0O); + wire_ni1Oli_dataout <= niiO1i OR n0iO0O; + wire_ni1Oll_dataout <= wire_ni1llO_dataout OR n0iO0O; + wire_ni1OlO_dataout <= niilOO OR n0iO0O; + wire_ni1OOl_dataout <= niiO1i OR n0iOil; + wire_ni1OOO_dataout <= niiO1l OR n0iOil; + wire_nii_dataout <= rxd(36) WHEN n0OlOl = '1' ELSE rxd(20); + wire_nii00i_dataout <= nil01O OR n0li1l; + wire_nii00l_dataout <= nil00i AND NOT(n0li1l); + wire_nii00O_dataout <= nil00l AND NOT(n0li1l); + wire_nii0i_dataout <= wire_niiOl_o(0) WHEN wire_n11ii_o = '1' ELSE wire_niiiO_dataout; + wire_nii0ii_dataout <= nil00O AND NOT(n0li1l); + wire_nii0l_dataout <= wire_niiOl_o(1) WHEN wire_n11ii_o = '1' ELSE wire_niili_dataout; + wire_nii0ll_dataout <= wire_niOi0i_dataout OR NOT(wire_nii0Ol_o(2)); + wire_nii0O_dataout <= wire_niiOl_o(2) WHEN wire_n11ii_o = '1' ELSE wire_niill_dataout; + wire_nii0Oi_dataout <= wire_niOi0O_dataout OR NOT(wire_nii0Ol_o(2)); + wire_nii10i_dataout <= wire_nii1il_dataout AND NOT(n0l0ll); + wire_nii10l_dataout <= wire_nii1iO_dataout AND NOT(n0l0ll); + wire_nii10O_dataout <= nil01O AND NOT(n0l0iO); + wire_nii11i_dataout <= wire_w_lg_n0l0iO2013w(0) AND NOT(n0l0ll); + wire_nii11l_dataout <= wire_nii10O_dataout AND NOT(n0l0ll); + wire_nii11O_dataout <= wire_nii1ii_dataout OR n0l0ll; + wire_nii1ii_dataout <= nil00i OR n0l0iO; + wire_nii1il_dataout <= nil00l AND NOT(n0l0iO); + wire_nii1iO_dataout <= nil00O AND NOT(n0l0iO); + wire_nii1l_dataout <= wire_n11OO_o AND NOT(rbist_clr_rx); + wire_nii1O_dataout <= wire_n11Ol_o AND NOT(rbist_clr_rx); + wire_niii_dataout <= niil0l AND n0Olli; + wire_niiii_dataout <= wire_niiOl_o(3) WHEN wire_n11ii_o = '1' ELSE wire_niilO_dataout; + wire_niiil_dataout <= wire_niiOl_o(4) WHEN wire_n11ii_o = '1' ELSE wire_niiOi_dataout; + wire_niiiO_dataout <= ni00O AND NOT(wire_n11il_o); + wire_niil_dataout <= niil0O AND n0Olli; + wire_niili_dataout <= ni0ii AND NOT(wire_n11il_o); + wire_niill_dataout <= ni0il AND NOT(wire_n11il_o); + wire_niilO_dataout <= ni0iO AND NOT(wire_n11il_o); + wire_niiO_dataout <= niilii AND n0Olli; + wire_niiOi_dataout <= ni0li AND NOT(wire_n11il_o); + wire_nil_dataout <= rxd(37) WHEN n0OlOl = '1' ELSE rxd(21); + wire_nil0ii_dataout <= wire_niliOi_dataout AND NOT(rbist_clr_rx); + wire_nil0il_dataout <= wire_niliOl_dataout AND NOT(rbist_clr_rx); + wire_nil0iO_dataout <= wire_niliOO_dataout AND NOT(rbist_clr_rx); + wire_nil0li_dataout <= wire_nill1i_dataout AND NOT(rbist_clr_rx); + wire_nil0ll_dataout <= wire_nill1l_dataout AND NOT(rbist_clr_rx); + wire_nil0lO_dataout <= wire_nill1O_dataout AND NOT(rbist_clr_rx); + wire_nil0Oi_dataout <= wire_nill0i_dataout AND NOT(rbist_clr_rx); + wire_nil0Ol_dataout <= wire_nill0l_dataout AND NOT(rbist_clr_rx); + wire_nil0OO_dataout <= wire_nill0O_dataout AND NOT(rbist_clr_rx); + wire_nili_dataout <= niilil AND n0Olli; + wire_nili0i_dataout <= wire_nillli_dataout AND NOT(rbist_clr_rx); + wire_nili0l_dataout <= wire_nillll_dataout AND NOT(rbist_clr_rx); + wire_nili0O_dataout <= wire_nilllO_dataout AND NOT(rbist_clr_rx); + wire_nili1i_dataout <= wire_nillii_dataout AND NOT(rbist_clr_rx); + wire_nili1l_dataout <= wire_nillil_dataout AND NOT(rbist_clr_rx); + wire_nili1O_dataout <= wire_nilliO_dataout AND NOT(rbist_clr_rx); + wire_niliii_dataout <= wire_nillOi_dataout AND NOT(rbist_clr_rx); + wire_niliil_dataout <= wire_nillOl_dataout AND NOT(rbist_clr_rx); + wire_niliiO_dataout <= wire_nillOO_dataout AND NOT(rbist_clr_rx); + wire_nilili_dataout <= wire_ni1iil_o AND NOT(rbist_clr_rx); + wire_nilill_dataout <= wire_ni1ili_o AND NOT(rbist_clr_rx); + wire_nililO_dataout <= wire_ni1ill_o AND NOT(rbist_clr_rx); + wire_niliOi_dataout <= wire_nilO1i_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_niliOl_dataout <= wire_nilO1l_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_niliOO_dataout <= wire_nilO1O_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nill_dataout <= niiliO AND n0Olli; + wire_nill0i_dataout <= wire_nilOii_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nill0l_dataout <= wire_nilOil_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nill0O_dataout <= wire_nilOiO_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nill1i_dataout <= wire_nilO0i_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nill1l_dataout <= wire_nilO0l_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nill1O_dataout <= wire_nilO0O_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nillii_dataout <= wire_nilOli_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nillil_dataout <= wire_nilOll_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nilliO_dataout <= wire_nilOlO_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nillli_dataout <= wire_nilOOi_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nillll_dataout <= wire_nilOOl_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nilllO_dataout <= wire_nilOOO_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nillOi_dataout <= wire_niO11i_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nillOl_dataout <= wire_niO11l_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nillOO_dataout <= wire_niO11O_dataout AND NOT(wire_nO_w_lg_dataout1517w(0)); + wire_nilO_dataout <= niilli AND n0Olli; + wire_nilO0i_dataout <= wire_nii0lO_o WHEN niilOl = '1' ELSE niiiOl; + wire_nilO0l_dataout <= wire_nii0Oi_dataout WHEN niilOl = '1' ELSE niiiOO; + wire_nilO0O_dataout <= wire_nii0OO_o WHEN niilOl = '1' ELSE niil1i; + wire_nilO1i_dataout <= wire_nii0iO_o WHEN niilOl = '1' ELSE ni1lOl; + wire_nilO1l_dataout <= wire_nii0li_o WHEN niilOl = '1' ELSE niiilO; + wire_nilO1O_dataout <= wire_nii0ll_dataout WHEN niilOl = '1' ELSE niiiOi; + wire_nilOii_dataout <= wire_niii1i_o WHEN niilOl = '1' ELSE niil1l; + wire_nilOil_dataout <= wire_niii1l_o WHEN niilOl = '1' ELSE niil1O; + wire_nilOiO_dataout <= wire_niii1O_o WHEN niilOl = '1' ELSE niil0i; + wire_nilOli_dataout <= wire_niii0i_o WHEN niilOl = '1' ELSE niil0l; + wire_nilOll_dataout <= wire_niii0l_o WHEN niilOl = '1' ELSE niil0O; + wire_nilOlO_dataout <= wire_niii0O_o WHEN niilOl = '1' ELSE niilii; + wire_nilOOi_dataout <= wire_niiiii_o WHEN niilOl = '1' ELSE niilil; + wire_nilOOl_dataout <= wire_niiiil_o WHEN niilOl = '1' ELSE niiliO; + wire_nilOOO_dataout <= wire_niiiiO_o WHEN niilOl = '1' ELSE niilli; + wire_niO_dataout <= rxd(38) WHEN n0OlOl = '1' ELSE rxd(22); + wire_niO00i_dataout <= wire_niO0OO_o(6) AND wire_ni1i0l_o; + wire_niO00l_dataout <= wire_niOi1i_o(0) AND wire_ni1i0l_o; + wire_niO00O_dataout <= wire_niOi1i_o(1) AND wire_ni1i0l_o; + wire_niO01i_dataout <= wire_niO0OO_o(3) AND wire_ni1i0l_o; + wire_niO01l_dataout <= wire_niO0OO_o(4) AND wire_ni1i0l_o; + wire_niO01O_dataout <= wire_niO0OO_o(5) AND wire_ni1i0l_o; + wire_niO0ii_dataout <= wire_niOi1i_o(2) AND wire_ni1i0l_o; + wire_niO0il_dataout <= wire_niOi1i_o(3) AND wire_ni1i0l_o; + wire_niO0iO_dataout <= wire_niOi1i_o(4) AND wire_ni1i0l_o; + wire_niO0li_dataout <= wire_niOi1i_o(5) AND wire_ni1i0l_o; + wire_niO0ll_dataout <= wire_niOi1i_o(6) AND wire_ni1i0l_o; + wire_niO0lO_dataout <= wire_niOi1i_o(7) AND wire_ni1i0l_o; + wire_niO0Oi_dataout <= wire_niOi1i_o(8) AND wire_ni1i0l_o; + wire_niO10i_dataout <= niiOlO AND wire_ni1i0l_o; + wire_niO10l_dataout <= wire_niO0Ol_o(0) AND wire_ni1i0l_o; + wire_niO10O_dataout <= wire_niO0Ol_o(1) AND wire_ni1i0l_o; + wire_niO11i_dataout <= wire_niiili_o WHEN niilOl = '1' ELSE niilll; + wire_niO11l_dataout <= (NOT wire_nii0Ol_o(2)) WHEN niilOl = '1' ELSE niillO; + wire_niO11O_dataout <= wire_niiill_o WHEN niilOl = '1' ELSE niilOi; + wire_niO1ii_dataout <= wire_niO0Ol_o(2) AND wire_ni1i0l_o; + wire_niO1il_dataout <= wire_niO0Ol_o(3) AND wire_ni1i0l_o; + wire_niO1iO_dataout <= wire_niO0Ol_o(4) AND wire_ni1i0l_o; + wire_niO1li_dataout <= wire_niO0Ol_o(5) AND wire_ni1i0l_o; + wire_niO1ll_dataout <= wire_niO0Ol_o(6) AND wire_ni1i0l_o; + wire_niO1lO_dataout <= niiO0i OR NOT(wire_ni1i0l_o); + wire_niO1Oi_dataout <= wire_niO0OO_o(0) AND wire_ni1i0l_o; + wire_niO1Ol_dataout <= wire_niO0OO_o(1) AND wire_ni1i0l_o; + wire_niO1OO_dataout <= wire_niO0OO_o(2) AND wire_ni1i0l_o; + wire_niOi_dataout <= niilll AND n0Olli; + wire_niOi0i_dataout <= niiOOl WHEN n0OlOi = '1' ELSE nil1ii; + wire_niOi0l_dataout <= niiOOO WHEN n0OlOi = '1' ELSE nil1il; + wire_niOi0O_dataout <= nil11i WHEN n0OlOi = '1' ELSE nil1iO; + wire_niOi1l_dataout <= niiOlO WHEN n0OlOi = '1' ELSE nil10l; + wire_niOi1O_dataout <= niiOOi WHEN n0OlOi = '1' ELSE nil10O; + wire_niOiii_dataout <= nil11l WHEN n0OlOi = '1' ELSE nil1li; + wire_niOiil_dataout <= nil11O WHEN n0OlOi = '1' ELSE nil1ll; + wire_niOiiO_dataout <= nil10i WHEN n0OlOi = '1' ELSE nil1lO; + wire_niOili_dataout <= niiO0i AND n0OlOi; + wire_niOill_dataout <= niiO0l AND n0OlOi; + wire_niOilO_dataout <= niiO0O AND n0OlOi; + wire_niOiOi_dataout <= niiOii AND n0OlOi; + wire_niOiOl_dataout <= niiOil AND n0OlOi; + wire_niOiOO_dataout <= niiOiO AND n0OlOi; + wire_niOl_dataout <= niillO AND n0Olli; + wire_niOl1i_dataout <= niiOli AND n0OlOi; + wire_niOl1l_dataout <= niiOll AND n0OlOi; + wire_niOO_dataout <= niilOi AND n0Olli; + wire_nl_dataout <= rbisten_rx AND wire_w_lg_w_rbist_sel_range1w9w(0); + wire_nl_w_lg_dataout1094w(0) <= wire_nl_dataout AND nl1Oll; + wire_nl_w_lg_dataout1013w(0) <= NOT wire_nl_dataout; + wire_nl000l_dataout <= nll0il OR NOT(wire_w_lg_n0li0O1010w(0)); + wire_nl000O_dataout <= wire_nl001O_dataout OR wire_w_lg_n0li0O1010w(0); + wire_nl001i_dataout <= nll0ii OR n0li0i; + wire_nl001l_dataout <= nll0il OR n0li0i; + wire_nl001O_dataout <= nll00O OR nll0il; + wire_nl00ii_dataout <= nll0ii OR wire_w_lg_n0li0O1010w(0); + wire_nl00il_dataout <= nll0il OR wire_w_lg_n0li0O1010w(0); + wire_nl00iO_dataout <= nll0il OR NOT(wire_w_lg_n0liii1009w(0)); + wire_nl00li_dataout <= wire_nl001O_dataout OR wire_w_lg_n0liii1009w(0); + wire_nl00ll_dataout <= nll0ii OR wire_w_lg_n0liii1009w(0); + wire_nl00lO_dataout <= nll0il OR wire_w_lg_n0liii1009w(0); + wire_nl00Oi_dataout <= nll0il OR NOT(wire_w_lg_n0liil1008w(0)); + wire_nl00Ol_dataout <= wire_nl001O_dataout OR wire_w_lg_n0liil1008w(0); + wire_nl00OO_dataout <= nll0ii OR wire_w_lg_n0liil1008w(0); + wire_nl01il_dataout <= nll0ii AND NOT(wire_nl_w_lg_dataout1013w(0)); + wire_nl01iO_dataout <= nll00O AND NOT(wire_nl_w_lg_dataout1013w(0)); + wire_nl01li_dataout <= nlll1i AND NOT(wire_nl_w_lg_dataout1013w(0)); + wire_nl01ll_dataout <= nlll1l AND NOT(wire_nl_w_lg_dataout1013w(0)); + wire_nl01lO_dataout <= nlll1O AND NOT(wire_nl_w_lg_dataout1013w(0)); + wire_nl01Oi_dataout <= nlll0i AND NOT(wire_nl_w_lg_dataout1013w(0)); + wire_nl01Ol_dataout <= nll0il OR NOT(n0li0i); + wire_nl01OO_dataout <= wire_nl001O_dataout OR n0li0i; + wire_nl0i_dataout <= nll00O WHEN n0Olll = '1' ELSE wire_nl0O_dataout; + wire_nl0i0i_dataout <= wire_nl0ill_dataout WHEN n0OlOi = '1' ELSE wire_nl0iil_dataout; + wire_nl0i0l_dataout <= wire_w_lg_n0lili1006w(0) OR n0OlOi; + wire_nl0i0O_dataout <= wire_nl0ilO_dataout OR NOT(n0OlOi); + wire_nl0i1i_dataout <= nll0il OR wire_w_lg_n0liil1008w(0); + wire_nl0i1l_dataout <= wire_nl0iiO_dataout WHEN n0OlOi = '1' ELSE nll0il; + wire_nl0i1O_dataout <= wire_nl0ili_dataout WHEN n0OlOi = '1' ELSE wire_nl0iii_dataout; + wire_nl0iii_dataout <= nll00O OR wire_w_lg_n0lili1006w(0); + wire_nl0iil_dataout <= nll0ii OR wire_w_lg_n0lili1006w(0); + wire_nl0iiO_dataout <= nll0il OR NOT(n0liiO); + wire_nl0ili_dataout <= wire_nl001O_dataout OR n0liiO; + wire_nl0ill_dataout <= nll0ii OR n0liiO; + wire_nl0ilO_dataout <= nll0il OR n0liiO; + wire_nl0iOl_dataout <= wire_nl0l0O_dataout AND NOT(wire_w_lg_n0lill1005w(0)); + wire_nl0iOO_dataout <= wire_nl0l0l_dataout AND NOT(wire_w_lg_n0lill1005w(0)); + wire_nl0l_dataout <= ni00i AND n0OllO; + wire_nl0l0i_dataout <= wire_nl0l0O_dataout OR wire_w_lg_n0lill1005w(0); + wire_nl0l0l_dataout <= n0lilO WHEN n0OlOi = '1' ELSE n0liOi; + wire_nl0l0O_dataout <= wire_w_lg_n0lilO1004w(0) WHEN n0OlOi = '1' ELSE wire_w_lg_n0liOi1003w(0); + wire_nl0l1i_dataout <= nll00O OR wire_w_lg_n0lill1005w(0); + wire_nl0l1l_dataout <= nll0ii OR wire_w_lg_n0lill1005w(0); + wire_nl0l1O_dataout <= wire_nl0l0l_dataout OR wire_w_lg_n0lill1005w(0); + wire_nl0lii_dataout <= nll00O OR wire_w_lg_n0liOl1002w(0); + wire_nl0lil_dataout <= nll0ii OR wire_w_lg_n0liOl1002w(0); + wire_nl0liO_dataout <= n0OlOi AND NOT(wire_w_lg_n0liOO1001w(0)); + wire_nl0lli_dataout <= nll00O OR wire_w_lg_n0liOO1001w(0); + wire_nl0lll_dataout <= nll0ii OR wire_w_lg_n0liOO1001w(0); + wire_nl0llO_dataout <= wire_nl0O1i_dataout OR wire_w_lg_n0liOO1001w(0); + wire_nl0lOi_dataout <= wire_nl0O1l_dataout OR wire_w_lg_n0liOO1001w(0); + wire_nl0lOl_dataout <= wire_nl0O1O_dataout OR wire_w_lg_n0liOO1001w(0); + wire_nl0lOO_dataout <= wire_nl0O0i_dataout OR wire_w_lg_n0liOO1001w(0); + wire_nl0O_dataout <= ni01l AND n0OllO; + wire_nl0O0i_dataout <= wire_nl0Oil_dataout AND n0OlOi; + wire_nl0O0l_dataout <= wire_nl0OiO_dataout OR n0ll1i; + wire_nl0O0O_dataout <= wire_nl0Oli_dataout AND NOT(n0ll1i); + wire_nl0O1i_dataout <= wire_nl0O0l_dataout AND n0OlOi; + wire_nl0O1l_dataout <= wire_nl0O0O_dataout OR NOT(n0OlOi); + wire_nl0O1O_dataout <= wire_nl0Oii_dataout OR NOT(n0OlOi); + wire_nl0Oii_dataout <= wire_nl0Oll_dataout OR n0ll1i; + wire_nl0Oil_dataout <= wire_nl0OlO_dataout AND NOT(n0ll1i); + wire_nl0OiO_dataout <= wire_nl0OOi_dataout OR NOT(n0ll1l); + wire_nl0Oli_dataout <= wire_nl0OOl_dataout OR NOT(n0ll1l); + wire_nl0Oll_dataout <= wire_nl0OOO_dataout OR NOT(n0ll1l); + wire_nl0OlO_dataout <= wire_nli11i_dataout AND n0ll1l; + wire_nl0OOi_dataout <= wire_nli11l_dataout AND NOT(n0lOiO); + wire_nl0OOl_dataout <= wire_nli11O_dataout OR n0lOiO; + wire_nl0OOO_dataout <= wire_nli10i_dataout AND NOT(n0lOiO); + wire_nl1i_dataout <= niiO1i WHEN n0Olli = '1' ELSE wire_nl1O_dataout; + wire_nl1l_dataout <= niiO1l WHEN n0Olli = '1' ELSE wire_nl0i_dataout; + wire_nl1O_dataout <= nll0ii WHEN n0Olll = '1' ELSE wire_nl0l_dataout; + wire_nl1Oii_dataout <= wire_nliill_dataout AND wire_nl1OiO_o(5); + wire_nl1Oil_dataout <= n0llil AND wire_nl1OiO_o(5); + wire_nl1Oli_dataout <= wire_nli1Ol_dataout AND wire_nl1OiO_o(6); + wire_nl1OlO_dataout <= wire_nli1OO_dataout AND wire_nl1OiO_o(6); + wire_nl1OOi_dataout <= wire_nl0liO_dataout AND wire_nl1OiO_o(7); + wire_nl1OOl_dataout <= wire_nl0iOl_dataout AND wire_nl1OiO_o(8); + wire_nl1OOO_dataout <= wire_nl0iOO_dataout AND wire_nl1OiO_o(8); + wire_nli_dataout <= rxd(39) WHEN n0OlOl = '1' ELSE rxd(23); + wire_nli00i_dataout <= wire_nli0li_dataout OR wire_w_lg_n0ll1O1000w(0); + wire_nli00l_dataout <= wire_nli0ll_dataout OR wire_w_lg_n0ll1O1000w(0); + wire_nli00O_dataout <= wire_nli0lO_dataout OR wire_w_lg_n0ll1O1000w(0); + wire_nli01i_dataout <= nll00O OR wire_w_lg_n0ll1O1000w(0); + wire_nli01l_dataout <= nll0ii OR wire_w_lg_n0ll1O1000w(0); + wire_nli01O_dataout <= wire_nli0iO_dataout OR wire_w_lg_n0ll1O1000w(0); + wire_nli0ii_dataout <= wire_w_lg_n0ll0i999w(0) OR NOT(n0OlOi); + wire_nli0il_dataout <= n0ll0i AND n0OlOi; + wire_nli0iO_dataout <= n0ll0i WHEN n0OlOi = '1' ELSE wire_nli0Oi_dataout; + wire_nli0li_dataout <= wire_w_lg_n0ll0i999w(0) WHEN n0OlOi = '1' ELSE wire_nli0Ol_dataout; + wire_nli0ll_dataout <= wire_w_lg_n0ll0i999w(0) WHEN n0OlOi = '1' ELSE wire_nli0OO_dataout; + wire_nli0lO_dataout <= n0ll0i WHEN n0OlOi = '1' ELSE wire_nlii1i_dataout; + wire_nli0Oi_dataout <= wire_nlii1l_dataout OR n0llii; + wire_nli0Ol_dataout <= wire_nlii1O_dataout AND NOT(n0llii); + wire_nli0OO_dataout <= wire_nlii0i_dataout AND NOT(n0llii); + wire_nli10i_dataout <= wire_nli1il_dataout AND NOT(n0lO1l); + wire_nli10l_dataout <= wire_nli1iO_dataout OR n0lO1l; + wire_nli10O_dataout <= wire_nli1li_dataout AND NOT(n0lO1i); + wire_nli11i_dataout <= wire_nli10l_dataout OR n0lOiO; + wire_nli11l_dataout <= wire_nli10O_dataout OR n0lO1l; + wire_nli11O_dataout <= wire_nli1ii_dataout OR n0lO1l; + wire_nli1ii_dataout <= wire_nli1ll_dataout AND NOT(n0lO1i); + wire_nli1il_dataout <= wire_nli1lO_dataout OR n0lO1i; + wire_nli1iO_dataout <= wire_nli1Oi_dataout OR n0lO1i; + wire_nli1li_dataout <= nlll1i OR n0lO0i; + wire_nli1ll_dataout <= nlll1l AND NOT(n0lO0i); + wire_nli1lO_dataout <= nlll1O OR n0lO0i; + wire_nli1Oi_dataout <= nlll0i OR n0lO0i; + wire_nli1Ol_dataout <= wire_nli0ii_dataout AND NOT(wire_w_lg_n0ll1O1000w(0)); + wire_nli1OO_dataout <= wire_nli0il_dataout AND NOT(wire_w_lg_n0ll1O1000w(0)); + wire_nlii_dataout <= wire_n1l_dataout AND n0OlOi; + wire_nlii_w_lg_dataout2015w(0) <= NOT wire_nlii_dataout; + wire_nlii0i_dataout <= wire_nliiil_dataout OR n0ll0l; + wire_nlii0l_dataout <= wire_nliiiO_dataout AND NOT(n0ll0l); + wire_nlii0O_dataout <= wire_nl0OOi_dataout OR NOT(n0ll0O); + wire_nlii1i_dataout <= wire_nlii0l_dataout OR n0llii; + wire_nlii1l_dataout <= wire_nlii0O_dataout OR n0ll0l; + wire_nlii1O_dataout <= wire_nliiii_dataout AND NOT(n0ll0l); + wire_nliiii_dataout <= wire_nl0OOl_dataout OR NOT(n0ll0O); + wire_nliiil_dataout <= wire_nl0OOO_dataout OR NOT(n0ll0O); + wire_nliiiO_dataout <= wire_nli11i_dataout AND n0ll0O; + wire_nliill_dataout <= wire_nlil1i_dataout AND NOT(wire_w_lg_n0llil989w(0)); + wire_nliilO_dataout <= nll00O OR wire_w_lg_n0llil989w(0); + wire_nliiOi_dataout <= nll0ii OR wire_w_lg_n0llil989w(0); + wire_nliiOl_dataout <= wire_nlil1l_dataout OR wire_w_lg_n0llil989w(0); + wire_nliiOO_dataout <= wire_nlil1O_dataout OR wire_w_lg_n0llil989w(0); + wire_nlil_dataout <= wire_n1O_dataout AND n0OlOi; + wire_nlil_w_lg_dataout720w(0) <= NOT wire_nlil_dataout; + wire_nlil0i_dataout <= wire_nlilli_dataout WHEN n0OlOi = '1' ELSE wire_nlilii_dataout; + wire_nlil0l_dataout <= wire_nlilll_dataout WHEN n0OlOi = '1' ELSE wire_nlilil_dataout; + wire_nlil0O_dataout <= wire_nlillO_dataout WHEN n0OlOi = '1' ELSE wire_nliliO_dataout; + wire_nlil1i_dataout <= wire_nlilOi_dataout WHEN n0lOiO = '1' ELSE wire_nlil0i_dataout; + wire_nlil1l_dataout <= wire_nlilOl_dataout WHEN n0lOiO = '1' ELSE wire_nlil0l_dataout; + wire_nlil1O_dataout <= wire_nlilOO_dataout WHEN n0lOiO = '1' ELSE wire_nlil0O_dataout; + wire_nlilii_dataout <= n0lliO AND NOT(n0llll); + wire_nlilil_dataout <= wire_w_lg_n0lliO988w(0) AND NOT(n0llll); + wire_nliliO_dataout <= n0lliO OR n0llll; + wire_nlilli_dataout <= n0llll AND NOT(n0llli); + wire_nlilll_dataout <= wire_w_lg_n0llll987w(0) AND NOT(n0llli); + wire_nlillO_dataout <= n0llll OR n0llli; + wire_nlilOi_dataout <= wire_nliO0i_dataout WHEN n0OlOi = '1' ELSE wire_nliO1i_dataout; + wire_nlilOl_dataout <= wire_nliO0l_dataout WHEN n0OlOi = '1' ELSE wire_nliO1l_dataout; + wire_nlilOO_dataout <= wire_nliO0O_dataout WHEN n0OlOi = '1' ELSE wire_nliO1O_dataout; + wire_nliO_dataout <= wire_n0i_dataout AND n0OlOi; + wire_nliO_w_lg_dataout718w(0) <= NOT wire_nliO_dataout; + wire_nliO0i_dataout <= n0llOl AND NOT(n0llOi); + wire_nliO0l_dataout <= wire_w_lg_n0llOl985w(0) AND NOT(n0llOi); + wire_nliO0O_dataout <= n0llOl OR n0llOi; + wire_nliO1i_dataout <= n0lllO AND NOT(n0llOl); + wire_nliO1l_dataout <= wire_w_lg_n0lllO986w(0) AND NOT(n0llOl); + wire_nliO1O_dataout <= n0lllO OR n0llOl; + wire_nliOii_dataout <= nll00O OR wire_w_lg_n0llOO984w(0); + wire_nliOil_dataout <= nll0ii OR wire_w_lg_n0llOO984w(0); + wire_nliOiO_dataout <= wire_nliOOi_dataout AND NOT(n0lOiO); + wire_nliOli_dataout <= wire_nliOOl_dataout AND NOT(n0lOiO); + wire_nliOll_dataout <= wire_nliOOO_dataout OR n0lOiO; + wire_nliOlO_dataout <= wire_nll11i_dataout AND NOT(n0lOiO); + wire_nliOOi_dataout <= nlll1i OR n0lOii; + wire_nliOOl_dataout <= nlll1l AND NOT(n0lOii); + wire_nliOOO_dataout <= nlll1O OR n0lOii; + wire_nll10i_dataout <= wire_w_lg_n0OlOi124w(0) WHEN n0lOil = '1' ELSE wire_nll1il_dataout; + wire_nll10l_dataout <= n0OlOi WHEN n0lOil = '1' ELSE wire_nll1iO_dataout; + wire_nll10O_dataout <= wire_nll1li_dataout AND NOT(n0lOil); + wire_nll11i_dataout <= nlll0i AND NOT(n0lOii); + wire_nll11O_dataout <= wire_nll1ii_dataout AND NOT(n0lOil); + wire_nll1ii_dataout <= n0OlOi WHEN n0lO0l = '1' ELSE wire_nll1ll_dataout; + wire_nll1il_dataout <= wire_w_lg_n0OlOi124w(0) WHEN n0lO0l = '1' ELSE wire_nll1lO_dataout; + wire_nll1iO_dataout <= n0OlOi WHEN n0lO0l = '1' ELSE wire_nll1Oi_dataout; + wire_nll1li_dataout <= wire_nll1Ol_dataout AND NOT(n0lO0l); + wire_nll1ll_dataout <= nlll1i OR n0lO1O; + wire_nll1lO_dataout <= wire_w_lg_n0OlOi124w(0) WHEN n0lO1O = '1' ELSE nlll1l; + wire_nll1Oi_dataout <= n0OlOi WHEN n0lO1O = '1' ELSE nlll1O; + wire_nll1Ol_dataout <= nlll0i AND NOT(n0lO1O); + wire_nlli_dataout <= wire_n0l_dataout AND n0OlOi; + wire_nlli_w_lg_dataout716w(0) <= NOT wire_nlli_dataout; + wire_nlll_dataout <= wire_n0O_dataout AND n0OlOi; + wire_nlll_w_lg_dataout679w(0) <= NOT wire_nlll_dataout; + wire_nlll0l_dataout <= wire_nl011O_o AND NOT(rbist_clr_rx); + wire_nlll0O_dataout <= wire_nl011l_o AND NOT(rbist_clr_rx); + wire_nlllii_dataout <= wire_nllO0i_o(0) WHEN wire_nl1OOl_dataout = '1' ELSE wire_nlllOi_dataout; + wire_nlllil_dataout <= wire_nllO0i_o(1) WHEN wire_nl1OOl_dataout = '1' ELSE wire_nlllOl_dataout; + wire_nllliO_dataout <= wire_nllO0i_o(2) WHEN wire_nl1OOl_dataout = '1' ELSE wire_nlllOO_dataout; + wire_nlllli_dataout <= wire_nllO0i_o(3) WHEN wire_nl1OOl_dataout = '1' ELSE wire_nllO1i_dataout; + wire_nlllll_dataout <= wire_nllO0i_o(4) WHEN wire_nl1OOl_dataout = '1' ELSE wire_nllO1l_dataout; + wire_nllllO_dataout <= wire_nllO0i_o(5) WHEN wire_nl1OOl_dataout = '1' ELSE wire_nllO1O_dataout; + wire_nlllOi_dataout <= nll0iO AND NOT(wire_nl1OOO_dataout); + wire_nlllOl_dataout <= nll0li AND NOT(wire_nl1OOO_dataout); + wire_nlllOO_dataout <= nll0ll AND NOT(wire_nl1OOO_dataout); + wire_nllO_dataout <= wire_nii_dataout AND n0OlOi; + wire_nllO_w_lg_dataout713w(0) <= NOT wire_nllO_dataout; + wire_nllO0l_dataout <= wire_nllOil_o(0) WHEN wire_nl1OOi_dataout = '1' ELSE nll0OO; + wire_nllO0O_dataout <= wire_nllOil_o(1) WHEN wire_nl1OOi_dataout = '1' ELSE nlli1i; + wire_nllO1i_dataout <= nll0lO AND NOT(wire_nl1OOO_dataout); + wire_nllO1l_dataout <= nll0Oi AND NOT(wire_nl1OOO_dataout); + wire_nllO1O_dataout <= nll0Ol AND NOT(wire_nl1OOO_dataout); + wire_nllOii_dataout <= wire_nllOil_o(2) WHEN wire_nl1OOi_dataout = '1' ELSE nlli1l; + wire_nllOiO_dataout <= wire_nllOOi_dataout AND NOT(wire_nl1OlO_dataout); + wire_nllOli_dataout <= wire_nllOOl_dataout AND NOT(wire_nl1OlO_dataout); + wire_nllOll_dataout <= wire_nllOOO_dataout AND NOT(wire_nl1OlO_dataout); + wire_nllOlO_dataout <= wire_nlO11i_dataout AND NOT(wire_nl1OlO_dataout); + wire_nllOOi_dataout <= wire_nlO11l_o(0) WHEN wire_nl1Oli_dataout = '1' ELSE nlli1O; + wire_nllOOl_dataout <= wire_nlO11l_o(1) WHEN wire_nl1Oli_dataout = '1' ELSE nlli0i; + wire_nllOOO_dataout <= wire_nlO11l_o(2) WHEN wire_nl1Oli_dataout = '1' ELSE nlli0l; + wire_nlO00i_dataout <= wire_nlO00O_o(7) WHEN wire_nl1Oil_dataout = '1' ELSE nlliOl; + wire_nlO00l_dataout <= wire_nlO00O_o(8) WHEN wire_nl1Oil_dataout = '1' ELSE nlliOO; + wire_nlO01i_dataout <= wire_nlO00O_o(4) WHEN wire_nl1Oil_dataout = '1' ELSE nllill; + wire_nlO01l_dataout <= wire_nlO00O_o(5) WHEN wire_nl1Oil_dataout = '1' ELSE nllilO; + wire_nlO01O_dataout <= wire_nlO00O_o(6) WHEN wire_nl1Oil_dataout = '1' ELSE nlliOi; + wire_nlO10i_dataout <= wire_nlO1Oi_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO10l_dataout <= wire_nlO1Ol_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO10O_dataout <= wire_nlO1OO_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO11i_dataout <= wire_nlO11l_o(3) WHEN wire_nl1Oli_dataout = '1' ELSE nlli0O; + wire_nlO11O_dataout <= wire_nlO1lO_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO1ii_dataout <= wire_nlO01i_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO1il_dataout <= wire_nlO01l_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO1iO_dataout <= wire_nlO01O_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO1li_dataout <= wire_nlO00i_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO1ll_dataout <= wire_nlO00l_dataout AND NOT(wire_nl1Oii_dataout); + wire_nlO1lO_dataout <= wire_nlO00O_o(0) WHEN wire_nl1Oil_dataout = '1' ELSE nlliii; + wire_nlO1Oi_dataout <= wire_nlO00O_o(1) WHEN wire_nl1Oil_dataout = '1' ELSE nlliil; + wire_nlO1Ol_dataout <= wire_nlO00O_o(2) WHEN wire_nl1Oil_dataout = '1' ELSE nlliiO; + wire_nlO1OO_dataout <= wire_nlO00O_o(3) WHEN wire_nl1Oil_dataout = '1' ELSE nllili; + wire_nlOi_dataout <= wire_nil_dataout AND n0OlOi; + wire_nlOi_w_lg_dataout678w(0) <= NOT wire_nlOi_dataout; + wire_nlOl_dataout <= wire_niO_dataout AND n0OlOi; + wire_nlOl_w_lg_dataout710w(0) <= NOT wire_nlOl_dataout; + wire_nlOO_dataout <= wire_nli_dataout AND n0OlOi; + wire_nlOO_w_lg_w_lg_w2466w2467w2468w(0) <= wire_nlOO_w_lg_w2466w2467w(0) AND wire_nlil_dataout; + wire_nlOO_w_lg_w_lg_w2481w2482w2483w(0) <= wire_nlOO_w_lg_w2481w2482w(0) AND wire_nlil_dataout; + wire_nlOO_w_lg_w2466w2467w(0) <= wire_nlOO_w2466w(0) AND wire_nliO_dataout; + wire_nlOO_w_lg_w2481w2482w(0) <= wire_nlOO_w2481w(0) AND wire_nliO_w_lg_dataout718w(0); + wire_nlOO_w_lg_w2410w2411w(0) <= wire_nlOO_w2410w(0) AND wire_nlli_dataout; + wire_nlOO_w_lg_w2433w2434w(0) <= wire_nlOO_w2433w(0) AND wire_nlli_dataout; + wire_nlOO_w2452w(0) <= wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2449w2450w2451w(0) AND wire_nlli_dataout; + wire_nlOO_w2466w(0) <= wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2334w2335w2465w(0) AND wire_nlli_dataout; + wire_nlOO_w2481w(0) <= wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2334w2335w2336w(0) AND wire_nlli_dataout; + wire_nlOO_w2410w(0) <= wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout709w711w2408w2409w(0) AND wire_nlll_dataout; + wire_nlOO_w2433w(0) <= wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout709w2430w2431w2432w(0) AND wire_nlll_dataout; + wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2449w2450w2451w(0) <= wire_nlOO_w_lg_w_lg_w_lg_dataout2333w2449w2450w(0) AND wire_nlll_dataout; + wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2334w2335w2465w(0) <= wire_nlOO_w_lg_w_lg_w_lg_dataout2333w2334w2335w(0) AND wire_nlll_w_lg_dataout679w(0); + wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout2333w2334w2335w2336w(0) <= wire_nlOO_w_lg_w_lg_w_lg_dataout2333w2334w2335w(0) AND wire_nlll_dataout; + wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout709w711w2408w2409w(0) <= wire_nlOO_w_lg_w_lg_w_lg_dataout709w711w2408w(0) AND wire_nllO_dataout; + wire_nlOO_w_lg_w_lg_w_lg_w_lg_dataout709w2430w2431w2432w(0) <= wire_nlOO_w_lg_w_lg_w_lg_dataout709w2430w2431w(0) AND wire_nllO_dataout; + wire_nlOO_w_lg_w_lg_w_lg_dataout2333w2449w2450w(0) <= wire_nlOO_w_lg_w_lg_dataout2333w2449w(0) AND wire_nllO_dataout; + wire_nlOO_w_lg_w_lg_w_lg_dataout2333w2334w2335w(0) <= wire_nlOO_w_lg_w_lg_dataout2333w2334w(0) AND wire_nllO_dataout; + wire_nlOO_w_lg_w_lg_w_lg_dataout709w711w2408w(0) <= wire_nlOO_w_lg_w_lg_dataout709w711w(0) AND wire_nlOi_dataout; + wire_nlOO_w_lg_w_lg_w_lg_dataout709w2430w2431w(0) <= wire_nlOO_w_lg_w_lg_dataout709w2430w(0) AND wire_nlOi_dataout; + wire_nlOO_w_lg_w_lg_dataout2333w2449w(0) <= wire_nlOO_w_lg_dataout2333w(0) AND wire_nlOi_w_lg_dataout678w(0); + wire_nlOO_w_lg_w_lg_dataout2333w2334w(0) <= wire_nlOO_w_lg_dataout2333w(0) AND wire_nlOi_dataout; + wire_nlOO_w_lg_w_lg_dataout709w711w(0) <= wire_nlOO_w_lg_dataout709w(0) AND wire_nlOl_w_lg_dataout710w(0); + wire_nlOO_w_lg_w_lg_dataout709w2430w(0) <= wire_nlOO_w_lg_dataout709w(0) AND wire_nlOl_dataout; + wire_nlOO_w_lg_dataout2333w(0) <= wire_nlOO_dataout AND wire_nlOl_dataout; + wire_nlOO_w_lg_dataout709w(0) <= NOT wire_nlOO_dataout; + wire_nO_dataout <= rbisten_rx AND (((NOT rbist_sel(0)) AND wire_w_lg_w_rbist_sel_range3w4w(0)) AND (n0OO0i2 XOR n0OO0i1)); + wire_nO_w_lg_dataout1517w(0) <= NOT wire_nO_dataout; + wire_niiOl_a <= ( ni0li & ni0iO & ni0il & ni0ii & ni00O); + wire_niiOl_b <= ( "0" & "0" & "0" & "0" & "1"); + niiOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_niiOl_a, + b => wire_niiOl_b, + cin => wire_gnd, + o => wire_niiOl_o + ); + wire_niO0Ol_a <= ( nil10i & nil11O & nil11l & nil11i & niiOOO & niiOOl & niiOOi); + wire_niO0Ol_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niO0Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_niO0Ol_a, + b => wire_niO0Ol_b, + cin => wire_gnd, + o => wire_niO0Ol_o + ); + wire_niO0OO_a <= ( niiOll & niiOli & niiOiO & niiOil & niiOii & niiO0O & niiO0l); + wire_niO0OO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niO0OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_niO0OO_a, + b => wire_niO0OO_b, + cin => wire_gnd, + o => wire_niO0OO_o + ); + wire_niOi1i_a <= ( nil1Oi & nil1lO & nil1ll & nil1li & nil1iO & nil1il & nil1ii & nil10O & nil10l); + wire_niOi1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niOi1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_niOi1i_a, + b => wire_niOi1i_b, + cin => wire_gnd, + o => wire_niOi1i_o + ); + wire_nllO0i_a <= ( nll0Ol & nll0Oi & nll0lO & nll0ll & nll0li & nll0iO); + wire_nllO0i_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + nllO0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nllO0i_a, + b => wire_nllO0i_b, + cin => wire_gnd, + o => wire_nllO0i_o + ); + wire_nllOil_a <= ( nlli1l & nlli1i & nll0OO); + wire_nllOil_b <= ( "0" & "0" & "1"); + nllOil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_nllOil_a, + b => wire_nllOil_b, + cin => wire_gnd, + o => wire_nllOil_o + ); + wire_nlO00O_a <= ( nlliOO & nlliOl & nlliOi & nllilO & nllill & nllili & nlliiO & nlliil & nlliii); + wire_nlO00O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlO00O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlO00O_a, + b => wire_nlO00O_b, + cin => wire_gnd, + o => wire_nlO00O_o + ); + wire_nlO11l_a <= ( nlli0O & nlli0l & nlli0i & nlli1O); + wire_nlO11l_b <= ( "0" & "0" & "0" & "1"); + nlO11l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nlO11l_a, + b => wire_nlO11l_b, + cin => wire_gnd, + o => wire_nlO11l_o + ); + wire_n11li_i <= ( nii1i & ni0Ol & ni0Oi & ni0lO & ni0ll); + n11li : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_n11li_i, + o => wire_n11li_o + ); + wire_ni1iii_i <= ( nil00O & nil00l & nil00i & nil01O); + ni1iii : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_ni1iii_i, + o => wire_ni1iii_o + ); + wire_nii0Ol_i <= ( nil01l & nil01i & nil1OO & nil1Ol); + nii0Ol : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nii0Ol_i, + o => wire_nii0Ol_o + ); + wire_nl1OiO_i <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl1OiO : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nl1OiO_i, + o => wire_nl1OiO_o + ); + wire_n100i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n10ll_dataout & "0" & "0" & "0" & "0" & "0" & wire_n1O0l_dataout & wire_n00iO_dataout & n0O00l & n0O00O & wire_n0O11l38_w_lg_w_lg_q237w238w & n0O0il & n0O0iO & n0O0li & n0O0ll & wire_n0lOi_dataout & "0" & "0" & "0" & wire_n0Oil_dataout & wire_n0OOi_dataout & "0"); + wire_n100i_sel <= ( nii1i & ni0Ol & ni0Oi & ni0lO & ni0ll); + n100i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n100i_data, + o => wire_n100i_o, + sel => wire_n100i_sel + ); + wire_n100l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n10lO_dataout & wire_n0O11O36_w_lg_w_lg_q191w192w & wire_n1iii_dataout & wire_n1ill_dataout & wire_n0O10i34_w_lg_w_lg_q186w187w & wire_n1l0l_dataout & wire_n1O0O_dataout & wire_n00li_dataout & wire_w_lg_n0O00l135w & wire_w_lg_n0O00O134w & wire_w_lg_n0O0ii133w & wire_n0O10l32_w_lg_w_lg_q177w178w & wire_n0O10O30_w_lg_w_lg_q174w175w & wire_w_lg_n0O0li130w & wire_w_lg_n0O0ll129w & wire_w_lg_n0O0lO128w & wire_w_lg_n0O0Oi127w & wire_w_lg_n0O0Ol126w & "0" & wire_n0OiO_dataout & wire_n0OOl_dataout & "0"); + wire_n100l_sel <= ( wire_n0O1ii28_w_lg_w_lg_q159w160w & ni0Ol & ni0Oi & ni0lO & ni0ll); + n100l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n100l_data, + o => wire_n100l_o, + sel => wire_n100l_sel + ); + wire_n101i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n10il_dataout & "1" & "1" & "1" & "1" & wire_n1l0i_dataout & wire_n1O1l_dataout & wire_n000O_dataout & wire_w_lg_n0O00l135w & wire_n0iii_dataout & wire_w_lg_n0O0ii133w & wire_n0iOi_dataout & wire_w_lg_n0O0iO131w & wire_n0l0l_dataout & wire_w_lg_n0O0ll129w & wire_n0llO_dataout & wire_w_lg_n0O0Oi127w & wire_n0O1O_dataout & "0" & wire_n0O0l_dataout & wire_n0Oli_dataout & wire_ni_w_lg_dataout403w); + wire_n101i_sel <= ( nii1i & ni0Ol & ni0Oi & ni0lO & ni0ll); + n101i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n101i_data, + o => wire_n101i_o, + sel => wire_n101i_sel + ); + wire_n101l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n10iO_dataout & "0" & "0" & "0" & "0" & "0" & wire_n1O1O_dataout & wire_n00ii_dataout & n0O00l & wire_n0iil_dataout & "0" & wire_n0iOl_dataout & n0O0iO & wire_n0l0O_dataout & "0" & wire_n0lll_dataout & n0O0Oi & wire_n0O0i_dataout & "0" & wire_n0O0O_dataout & wire_n0Oll_dataout & "0"); + wire_n101l_sel <= ( nii1i & ni0Ol & ni0Oi & wire_n0lOOi46_w_lg_w_lg_q339w340w & ni0ll); + n101l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n101l_data, + o => wire_n101l_o, + sel => wire_n101l_sel + ); + wire_n101O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n0lOOl44_w_lg_w_lg_q314w315w & wire_n1i1i_dataout & wire_n1iii_dataout & wire_n0lOOO42_w_lg_w_lg_q309w310w & wire_n1iOO_dataout & wire_n1l0l_dataout & wire_n1O0i_dataout & wire_n0O11i40_w_lg_w_lg_q303w304w & "1" & "1" & "1" & wire_n0iOO_dataout & wire_w_lg_n0O0iO131w & wire_w_lg_n0O0li130w & wire_w_lg_n0O0ll129w & wire_n0llO_dataout & "1" & "1" & "1" & wire_n0Oii_dataout & wire_n0OlO_dataout & "0"); + wire_n101O_sel <= ( nii1i & ni0Ol & ni0Oi & ni0lO & ni0ll); + n101O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n101O_data, + o => wire_n101O_o, + sel => wire_n101O_sel + ); + wire_n11Ol_data <= ( ni00i & ni00i & ni00i & ni00i & ni00i & ni00i & ni00i & ni00i & ni00i & ni00i & wire_n100O_dataout & wire_n10OO_dataout & wire_n1i0O_dataout & wire_n1ili_dataout & wire_n1iOl_dataout & wire_n1l1O_dataout & wire_n1O1i_dataout & wire_n000l_dataout & wire_n0i0i_dataout & wire_n0i0O_dataout & wire_n0ili_dataout & wire_n0ilO_dataout & wire_n0l1l_dataout & wire_n0l0i_dataout & wire_n0lil_dataout & wire_n0lli_dataout & wire_n0lOO_dataout & wire_n0O1l_dataout & ni00i & ni00i & ni00i & ni00i); + wire_n11Ol_sel <= ( nii1i & ni0Ol & ni0Oi & ni0lO & ni0ll); + n11Ol : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11Ol_data, + o => wire_n11Ol_o, + sel => wire_n11Ol_sel + ); + wire_n11OO_data <= ( ni01l & ni01l & ni01l & ni01l & ni01l & ni01l & ni01l & ni01l & ni01l & ni01l & wire_n10ii_dataout & wire_n10Ol_dataout & wire_n1i0l_dataout & wire_n1iiO_dataout & wire_n1iOi_dataout & wire_n1l1l_dataout & wire_n1lOO_dataout & wire_n000i_dataout & wire_n0i1O_dataout & wire_n0i0l_dataout & wire_n0iiO_dataout & wire_n0ill_dataout & wire_n0l1i_dataout & wire_n0l1O_dataout & wire_n0lii_dataout & wire_n0liO_dataout & wire_n0lOl_dataout & wire_n0O1i_dataout & ni01l & ni01l & ni01l & ni01l); + wire_n11OO_sel <= ( nii1i & ni0Ol & ni0Oi & ni0lO & ni0ll); + n11OO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11OO_data, + o => wire_n11OO_o, + sel => wire_n11OO_sel + ); + wire_ni1iil_data <= ( "0" & "0" & "0" & n0iO1l & wire_ni1O1i_dataout & n0iOil & wire_ni010O_dataout & n0iOOl & wire_ni000i_dataout & "0" & wire_ni0i1O_dataout & n0l1ll & wire_ni0l1i_dataout & n0l0ii & n0l0Ol & "0"); + wire_ni1iil_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1iil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1iil_data, + o => wire_ni1iil_o, + sel => wire_ni1iil_sel + ); + wire_ni1iiO_data <= ( niilOO & niilOO & wire_ni1l1i_dataout & wire_ni1lil_dataout & wire_ni1lOO_dataout & niilOO & niilOO & niilOO & niilOO & niilOO & niilOO & niilOO & niilOO & niilOO & niilOO & niilOO); + wire_ni1iiO_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1iiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1iiO_data, + o => wire_ni1iiO_o, + sel => wire_ni1iiO_sel + ); + wire_ni1ili_data <= ( niiO1i & niiO1i & wire_ni1l1l_dataout & wire_ni1liO_dataout & wire_ni1O1l_dataout & wire_ni1OOl_dataout & wire_ni011l_dataout & wire_ni01Oi_dataout & wire_ni001i_dataout & wire_ni00ll_dataout & wire_ni00Ol_dataout & wire_ni0ili_dataout & wire_ni0iOi_dataout & wire_ni0lil_dataout & wire_ni0Oli_dataout & niiO1i); + wire_ni1ili_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1ili : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1ili_data, + o => wire_ni1ili_o, + sel => wire_ni1ili_sel + ); + wire_ni1ill_data <= ( niiO1l & niiO1l & wire_ni1l1O_dataout & wire_ni1lli_dataout & wire_ni1O1O_dataout & wire_ni1OOO_dataout & wire_ni011O_dataout & wire_ni01Ol_dataout & wire_ni001l_dataout & wire_ni00lO_dataout & wire_ni00OO_dataout & wire_ni0ill_dataout & wire_ni0iOl_dataout & wire_ni0liO_dataout & wire_ni0Oll_dataout & niiO1l); + wire_ni1ill_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1ill : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1ill_data, + o => wire_ni1ill_o, + sel => wire_ni1ill_sel + ); + wire_ni1ilO_data <= ( "0" & "0" & wire_ni1l0i_dataout & "1" & wire_ni1O0i_dataout & "1" & wire_ni010i_dataout & "1" & wire_ni001O_dataout & "1" & wire_ni0i1i_dataout & "1" & wire_ni0iOO_dataout & wire_ni0lli_dataout & wire_ni0OlO_dataout & wire_nii00i_dataout); + wire_ni1ilO_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1ilO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1ilO_data, + o => wire_ni1ilO_o, + sel => wire_ni1ilO_sel + ); + wire_ni1iOi_data <= ( "0" & "0" & wire_ni1l0l_dataout & "0" & "0" & wire_w_lg_n0iOil2133w & wire_ni010l_dataout & "0" & "0" & wire_w_lg_n0l10l2126w & wire_ni0i1l_dataout & "0" & "0" & wire_ni0lll_dataout & wire_ni0OOi_dataout & wire_nii00l_dataout); + wire_ni1iOi_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1iOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1iOi_data, + o => wire_ni1iOi_o, + sel => wire_ni1iOi_sel + ); + wire_ni1iOl_data <= ( "0" & "0" & wire_ni1l0O_dataout & wire_ni1lll_dataout & wire_ni1O0l_dataout & n0iOil & wire_ni010O_dataout & n0iOOl & wire_ni000i_dataout & "1" & "1" & "1" & "1" & wire_ni0llO_dataout & wire_ni0OOl_dataout & wire_nii00O_dataout); + wire_ni1iOl_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1iOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1iOl_data, + o => wire_ni1iOl_o, + sel => wire_ni1iOl_sel + ); + wire_ni1iOO_data <= ( "0" & "0" & wire_ni1lii_dataout & wire_ni1lll_dataout & wire_ni1O0l_dataout & "1" & "1" & "1" & "1" & n0l10l & wire_ni0i1O_dataout & n0l1ll & wire_ni0l1i_dataout & wire_ni0lOi_dataout & wire_ni0OOO_dataout & wire_nii0ii_dataout); + wire_ni1iOO_sel <= ( nil00O & nil00l & nil00i & nil01O); + ni1iOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1iOO_data, + o => wire_ni1iOO_o, + sel => wire_ni1iOO_sel + ); + wire_nii0iO_data <= ( "1" & "1" & "1" & "1" & "0" & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_niOi1l_dataout & "1" & "1"); + wire_nii0iO_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + nii0iO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nii0iO_data, + o => wire_nii0iO_o, + sel => wire_nii0iO_sel + ); + wire_nii0li_data <= ( "1" & "1" & "1" & "0" & "1" & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_niOi1O_dataout & "1" & "1"); + wire_nii0li_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + nii0li : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nii0li_data, + o => wire_nii0li_o, + sel => wire_nii0li_sel + ); + wire_nii0lO_data <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_niOi0l_dataout & "1" & "1"); + wire_nii0lO_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + nii0lO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nii0lO_data, + o => wire_nii0lO_o, + sel => wire_nii0lO_sel + ); + wire_nii0OO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "1" & "0" & "1" & "0" & wire_niOiii_dataout & "1" & "1"); + wire_nii0OO_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + nii0OO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nii0OO_data, + o => wire_nii0OO_o, + sel => wire_nii0OO_sel + ); + wire_niii0i_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & "0" & "0" & n0OlOi & "0" & "0" & "0" & "0" & "0" & "0" & wire_niOill_dataout & n0OlOi & n0OlOi); + wire_niii0i_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niii0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niii0i_data, + o => wire_niii0i_o, + sel => wire_niii0i_sel + ); + wire_niii0l_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & wire_niOilO_dataout & n0OlOi & n0OlOi); + wire_niii0l_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niii0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niii0l_data, + o => wire_niii0l_o, + sel => wire_niii0l_sel + ); + wire_niii0O_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & "0" & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & wire_niOiOi_dataout & n0OlOi & n0OlOi); + wire_niii0O_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niii0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niii0O_data, + o => wire_niii0O_o, + sel => wire_niii0O_sel + ); + wire_niii1i_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "0" & "0" & wire_niOiil_dataout & "1" & "1"); + wire_niii1i_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niii1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niii1i_data, + o => wire_niii1i_o, + sel => wire_niii1i_sel + ); + wire_niii1l_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "0" & "0" & wire_niOiiO_dataout & "1" & "1"); + wire_niii1l_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niii1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niii1l_data, + o => wire_niii1l_o, + sel => wire_niii1l_sel + ); + wire_niii1O_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & "0" & "0" & "0" & "0" & "0" & wire_niOili_dataout & n0OlOi & n0OlOi); + wire_niii1O_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niii1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niii1O_data, + o => wire_niii1O_o, + sel => wire_niii1O_sel + ); + wire_niiiii_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & wire_niOiOl_dataout & n0OlOi & n0OlOi); + wire_niiiii_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niiiii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niiiii_data, + o => wire_niiiii_o, + sel => wire_niiiii_sel + ); + wire_niiiil_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & "0" & "0" & n0OlOi & "0" & n0OlOi & wire_niOiOO_dataout & n0OlOi & n0OlOi); + wire_niiiil_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niiiil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niiiil_data, + o => wire_niiiil_o, + sel => wire_niiiil_sel + ); + wire_niiiiO_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & "0" & wire_niOl1i_dataout & n0OlOi & n0OlOi); + wire_niiiiO_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niiiiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niiiiO_data, + o => wire_niiiiO_o, + sel => wire_niiiiO_sel + ); + wire_niiili_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & "0" & "0" & "0" & wire_niOl1l_dataout & n0OlOi & n0OlOi); + wire_niiili_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niiili : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niiili_data, + o => wire_niiili_o, + sel => wire_niiili_sel + ); + wire_niiill_data <= ( n0OlOi & n0OlOi & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & "0" & n0OlOi & n0OlOi); + wire_niiill_sel <= ( nil01l & nil01i & nil1OO & nil1Ol); + niiill : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niiill_data, + o => wire_niiill_o, + sel => wire_niiill_sel + ); + wire_nl010i_data <= ( wire_nl01li_dataout & "1" & "1" & "1" & "1" & wire_nl0i0l_dataout & wire_w_lg_n0liOl1002w & wire_nl0l1O_dataout & wire_nl0llO_dataout & wire_nli01O_dataout & wire_nliiOl_dataout & "1" & "1" & wire_nliOiO_dataout & wire_nll11O_dataout & wire_nl_w_lg_dataout1094w); + wire_nl010i_sel <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl010i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl010i_data, + o => wire_nl010i_o, + sel => wire_nl010i_sel + ); + wire_nl010l_data <= ( wire_nl01ll_dataout & wire_nl001l_dataout & wire_nl00il_dataout & wire_nl00lO_dataout & wire_nl0i1i_dataout & wire_nl0i0O_dataout & wire_w_lg_n0liOl1002w & wire_nl0l1O_dataout & wire_nl0lOi_dataout & wire_nli00i_dataout & wire_nliiOO_dataout & wire_w_lg_n0llOO984w & "0" & wire_nliOli_dataout & wire_nll10i_dataout & "0"); + wire_nl010l_sel <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl010l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl010l_data, + o => wire_nl010l_o, + sel => wire_nl010l_sel + ); + wire_nl010O_data <= ( wire_nl01lO_dataout & wire_nl001l_dataout & wire_nl00il_dataout & wire_nl00lO_dataout & wire_nl0i1i_dataout & wire_nl0i0O_dataout & wire_w_lg_n0liOl1002w & wire_nl0l1O_dataout & wire_nl0lOl_dataout & wire_nli00l_dataout & "1" & "1" & "1" & wire_nliOll_dataout & wire_nll10l_dataout & "0"); + wire_nl010O_sel <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl010O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl010O_data, + o => wire_nl010O_o, + sel => wire_nl010O_sel + ); + wire_nl011i_data <= ( nll0il & wire_nl01Ol_dataout & wire_nl000l_dataout & wire_nl00iO_dataout & wire_nl00Oi_dataout & wire_nl0i1l_dataout & nll0il & nll0il & nll0il & nll0il & nll0il & nll0il & nll0il & nll0il & nll0il & nll0il); + wire_nl011i_sel <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl011i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl011i_data, + o => wire_nl011i_o, + sel => wire_nl011i_sel + ); + wire_nl011l_data <= ( wire_nl01il_dataout & wire_nl001i_dataout & wire_nl00ii_dataout & wire_nl00ll_dataout & wire_nl00OO_dataout & wire_nl0i0i_dataout & wire_nl0lil_dataout & wire_nl0l1l_dataout & wire_nl0lll_dataout & wire_nli01l_dataout & wire_nliiOi_dataout & wire_nliOil_dataout & nll0ii & nll0ii & nll0ii & nll0ii); + wire_nl011l_sel <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl011l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl011l_data, + o => wire_nl011l_o, + sel => wire_nl011l_sel + ); + wire_nl011O_data <= ( wire_nl01iO_dataout & wire_nl01OO_dataout & wire_nl000O_dataout & wire_nl00li_dataout & wire_nl00Ol_dataout & wire_nl0i1O_dataout & wire_nl0lii_dataout & wire_nl0l1i_dataout & wire_nl0lli_dataout & wire_nli01i_dataout & wire_nliilO_dataout & wire_nliOii_dataout & nll00O & nll00O & nll00O & nll00O); + wire_nl011O_sel <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl011O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl011O_data, + o => wire_nl011O_o, + sel => wire_nl011O_sel + ); + wire_nl01ii_data <= ( wire_nl01Oi_dataout & wire_nl001l_dataout & wire_nl00il_dataout & wire_nl00lO_dataout & wire_nl0i1i_dataout & wire_nl0i0O_dataout & "1" & wire_nl0l0i_dataout & wire_nl0lOO_dataout & wire_nli00O_dataout & wire_w_lg_n0llil989w & wire_w_lg_n0llOO984w & "0" & wire_nliOlO_dataout & wire_nll10O_dataout & "0"); + wire_nl01ii_sel <= ( nlll0i & nlll1O & nlll1l & nlll1i); + nl01ii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl01ii_data, + o => wire_nl01ii_o, + sel => wire_nl01ii_sel + ); + wire_n11ii_data <= ( "0" & wire_n1lOi_dataout & wire_n001l_dataout); + wire_n11ii_sel <= ( n0lOll & wire_n11li_o(15 DOWNTO 14)); + n11ii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11ii_data, + o => wire_n11ii_o, + sel => wire_n11ii_sel + ); + wire_n11il_data <= ( "0" & wire_n1lOl_dataout & wire_n001O_dataout); + wire_n11il_sel <= ( n0lOll & wire_n11li_o(15 DOWNTO 14)); + n11il : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11il_data, + o => wire_n11il_o, + sel => wire_n11il_sel + ); + wire_n11ll_data <= ( ni00l & wire_n10Oi_dataout & wire_n1i0i_dataout & wire_n1iil_dataout & wire_n1ilO_dataout & wire_n1l1i_dataout); + wire_n11ll_sel <= ( n0lOlO & wire_n11li_o(20 DOWNTO 16)); + n11ll : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n11ll_data, + o => wire_n11ll_o, + sel => wire_n11ll_sel + ); + wire_ni1i0l_data <= ( "0" & "1" & wire_ni0OiO_dataout); + wire_ni1i0l_sel <= ( n0iO1i & wire_ni1iii_o(2 DOWNTO 1)); + ni1i0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni1i0l_data, + o => wire_ni1i0l_o, + sel => wire_ni1i0l_sel + ); + + END RTL; --cycloneiv_hssi_rx_digi_bist_ver +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 98 mux21 49 oper_add 3 oper_selector 7 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_cdr_ctrl IS + PORT + ( + adata : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + adata_valid : IN STD_LOGIC; + early_eios : OUT STD_LOGIC; + eidle_exit : OUT STD_LOGIC; + eiosdetect_int : OUT STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + inferred_rxvalid : OUT STD_LOGIC; + ltr : OUT STD_LOGIC; + pipe_loopbk : IN STD_LOGIC; + pld_ltr : IN STD_LOGIC; + rcdr_ctrl_en : IN STD_LOGIC; + rcid_en : IN STD_LOGIC; + rcvd_clk : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmask_count : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + rrxvalid_mask : IN STD_LOGIC; + rwait_count : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxpcs_reset_int : IN STD_LOGIC; + sigdet : IN STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_cdr_ctrl; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_cdr_ctrl IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n0l0O43 : STD_LOGIC := '0'; + SIGNAL n0l0O44 : STD_LOGIC := '0'; + SIGNAL n0l1i45 : STD_LOGIC := '0'; + SIGNAL n0l1i46 : STD_LOGIC := '0'; + SIGNAL n0lli41 : STD_LOGIC := '0'; + SIGNAL n0lli42 : STD_LOGIC := '0'; + SIGNAL n0lOO39 : STD_LOGIC := '0'; + SIGNAL n0lOO40 : STD_LOGIC := '0'; + SIGNAL n0O0i35 : STD_LOGIC := '0'; + SIGNAL n0O0i36 : STD_LOGIC := '0'; + SIGNAL n0O0l33 : STD_LOGIC := '0'; + SIGNAL n0O0l34 : STD_LOGIC := '0'; + SIGNAL wire_n0O0l34_w_lg_w_lg_q200w201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O0l34_w_lg_q200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O0O31 : STD_LOGIC := '0'; + SIGNAL n0O0O32 : STD_LOGIC := '0'; + SIGNAL n0O1l37 : STD_LOGIC := '0'; + SIGNAL n0O1l38 : STD_LOGIC := '0'; + SIGNAL n0OiO29 : STD_LOGIC := '0'; + SIGNAL n0OiO30 : STD_LOGIC := '0'; + SIGNAL n0Oll27 : STD_LOGIC := '0'; + SIGNAL n0Oll28 : STD_LOGIC := '0'; + SIGNAL n0OOi25 : STD_LOGIC := '0'; + SIGNAL n0OOi26 : STD_LOGIC := '0'; + SIGNAL n0OOO23 : STD_LOGIC := '0'; + SIGNAL n0OOO24 : STD_LOGIC := '0'; + SIGNAL ni01i3 : STD_LOGIC := '0'; + SIGNAL ni01i4 : STD_LOGIC := '0'; + SIGNAL wire_ni01i4_w_lg_w_lg_q4w5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01i4_w_lg_q4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni01O1 : STD_LOGIC := '0'; + SIGNAL ni01O2 : STD_LOGIC := '0'; + SIGNAL ni10i19 : STD_LOGIC := '0'; + SIGNAL ni10i20 : STD_LOGIC := '0'; + SIGNAL wire_ni10i20_w_lg_w_lg_q111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni10i20_w_lg_q111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni10l17 : STD_LOGIC := '0'; + SIGNAL ni10l18 : STD_LOGIC := '0'; + SIGNAL ni11O21 : STD_LOGIC := '0'; + SIGNAL ni11O22 : STD_LOGIC := '0'; + SIGNAL wire_ni11O22_w_lg_w_lg_q114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni11O22_w_lg_q114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni1ii15 : STD_LOGIC := '0'; + SIGNAL ni1ii16 : STD_LOGIC := '0'; + SIGNAL ni1iO13 : STD_LOGIC := '0'; + SIGNAL ni1iO14 : STD_LOGIC := '0'; + SIGNAL ni1lO11 : STD_LOGIC := '0'; + SIGNAL ni1lO12 : STD_LOGIC := '0'; + SIGNAL wire_ni1lO12_w_lg_w_lg_q22w23w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lO12_w_lg_q22w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni1Oi10 : STD_LOGIC := '0'; + SIGNAL wire_ni1Oi10_w_lg_w_lg_q18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1Oi10_w_lg_q18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni1Oi9 : STD_LOGIC := '0'; + SIGNAL ni1Ol7 : STD_LOGIC := '0'; + SIGNAL ni1Ol8 : STD_LOGIC := '0'; + SIGNAL wire_ni1Ol8_w_lg_w_lg_q15w16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1Ol8_w_lg_q15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni1OO5 : STD_LOGIC := '0'; + SIGNAL ni1OO6 : STD_LOGIC := '0'; + SIGNAL wire_ni1OO6_w_lg_w_lg_q10w11w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1OO6_w_lg_q10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n10O : STD_LOGIC := '0'; + SIGNAL n11O : STD_LOGIC := '0'; + SIGNAL n1ii : STD_LOGIC := '0'; + SIGNAL n1il : STD_LOGIC := '0'; + SIGNAL n1iO : STD_LOGIC := '0'; + SIGNAL n1li : STD_LOGIC := '0'; + SIGNAL n1ll : STD_LOGIC := '0'; + SIGNAL n1lO : STD_LOGIC := '0'; + SIGNAL n1Oi : STD_LOGIC := '0'; + SIGNAL n1Ol : STD_LOGIC := '0'; + SIGNAL n1OO : STD_LOGIC := '0'; + SIGNAL ni0li : STD_LOGIC := '0'; + SIGNAL ni0Oi : STD_LOGIC := '0'; + SIGNAL nii0i : STD_LOGIC := '0'; + SIGNAL nii0O : STD_LOGIC := '0'; + SIGNAL niili : STD_LOGIC := '0'; + SIGNAL niOOO : STD_LOGIC := '0'; + SIGNAL nl : STD_LOGIC := '0'; + SIGNAL nl0il : STD_LOGIC := '0'; + SIGNAL nl0iO : STD_LOGIC := '0'; + SIGNAL nl0li : STD_LOGIC := '0'; + SIGNAL nl0ll : STD_LOGIC := '0'; + SIGNAL nl0lO : STD_LOGIC := '0'; + SIGNAL nl0Oi : STD_LOGIC := '0'; + SIGNAL nl0Ol : STD_LOGIC := '0'; + SIGNAL nl0OO : STD_LOGIC := '0'; + SIGNAL nl10O : STD_LOGIC := '0'; + SIGNAL nl11i : STD_LOGIC := '0'; + SIGNAL nl11l : STD_LOGIC := '0'; + SIGNAL nl11O : STD_LOGIC := '0'; + SIGNAL nl1ii : STD_LOGIC := '0'; + SIGNAL nl1il : STD_LOGIC := '0'; + SIGNAL nl1iO : STD_LOGIC := '0'; + SIGNAL nl1li : STD_LOGIC := '0'; + SIGNAL nl1ll : STD_LOGIC := '0'; + SIGNAL nli0O : STD_LOGIC := '0'; + SIGNAL nli1i : STD_LOGIC := '0'; + SIGNAL nll0l : STD_LOGIC := '0'; + SIGNAL nll0O : STD_LOGIC := '0'; + SIGNAL nll1l : STD_LOGIC := '0'; + SIGNAL nllii : STD_LOGIC := '0'; + SIGNAL nllil : STD_LOGIC := '0'; + SIGNAL nlliO : STD_LOGIC := '0'; + SIGNAL nllli : STD_LOGIC := '0'; + SIGNAL nllll : STD_LOGIC := '0'; + SIGNAL nlllO : STD_LOGIC := '0'; + SIGNAL nlO : STD_LOGIC := '0'; + SIGNAL wire_ni_CLRN : STD_LOGIC; + SIGNAL wire_ni_w_lg_w_lg_nl1li346w347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nl0iO227w228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl1li346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_n10O250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niili224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niOOO47w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl0iO227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl11i139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl1ii348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl1ll241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlO226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nl11O285w286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl11O285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nilil : STD_LOGIC := '0'; + SIGNAL wire_nilii_PRN : STD_LOGIC; + SIGNAL wire_nilii_ENA : STD_LOGIC; + SIGNAL niiii : STD_LOGIC := '0'; + SIGNAL niiil : STD_LOGIC := '0'; + SIGNAL niiiO : STD_LOGIC := '0'; + SIGNAL nl10l : STD_LOGIC := '0'; + SIGNAL wire_nl10i_CLRN : STD_LOGIC; + SIGNAL wire_nl10i_w_lg_w_lg_w_lg_nl10l321w322w323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10i_w_lg_w_lg_nl10l334w335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10i_w_lg_w_lg_nl10l321w322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10i_w_lg_nl10l334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10i_w_lg_nl10l321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_ni0ll_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_nl00i_dataout : STD_LOGIC; + SIGNAL wire_nl00l_dataout : STD_LOGIC; + SIGNAL wire_nl00O_dataout : STD_LOGIC; + SIGNAL wire_nl01i_dataout : STD_LOGIC; + SIGNAL wire_nl01l_dataout : STD_LOGIC; + SIGNAL wire_nl01O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nliii_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_n0ll_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_n0ll_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n0ll_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0ii_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0ii_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0ii_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO0O_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0O_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0O_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niill_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niill_o : STD_LOGIC; + SIGNAL wire_niill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niiOi_o : STD_LOGIC; + SIGNAL wire_niiOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niiOO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_niiOO_o : STD_LOGIC; + SIGNAL wire_niiOO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nil1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil1i_o : STD_LOGIC; + SIGNAL wire_nil1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nil1O_o : STD_LOGIC; + SIGNAL wire_nil1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niliO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_niliO_o : STD_LOGIC; + SIGNAL wire_niliO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nilli_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nilli_o : STD_LOGIC; + SIGNAL wire_nilli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_rcid_en196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l0i274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l0l248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1l337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lOi236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0Oil195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rxpcs_reset_int2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0llO262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rmask_count_range68w69w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rmask_count_range84w85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rmask_count_range92w93w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rwait_count_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rwait_count_range158w159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rwait_count_range170w171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rwait_count_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0ilO : STD_LOGIC; + SIGNAL n0iOi : STD_LOGIC; + SIGNAL n0iOl : STD_LOGIC; + SIGNAL n0iOO : STD_LOGIC; + SIGNAL n0l0i : STD_LOGIC; + SIGNAL n0l0l : STD_LOGIC; + SIGNAL n0l1l : STD_LOGIC; + SIGNAL n0l1O : STD_LOGIC; + SIGNAL n0lil : STD_LOGIC; + SIGNAL n0liO : STD_LOGIC; + SIGNAL n0llO : STD_LOGIC; + SIGNAL n0lOi : STD_LOGIC; + SIGNAL n0lOl : STD_LOGIC; + SIGNAL n0Oil : STD_LOGIC; + SIGNAL ni01l : STD_LOGIC; + SIGNAL ni11l : STD_LOGIC; + SIGNAL ni1ll : STD_LOGIC; + SIGNAL wire_w_rmask_count_range68w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rmask_count_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rmask_count_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rwait_count_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rwait_count_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rwait_count_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rwait_count_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_w_lg_rcid_en196w(0) <= rcid_en AND wire_w_lg_n0Oil195w(0); + wire_w_lg_n0l0i274w(0) <= NOT n0l0i; + wire_w_lg_n0l0l248w(0) <= NOT n0l0l; + wire_w_lg_n0l1l337w(0) <= NOT n0l1l; + wire_w_lg_n0lOi236w(0) <= NOT n0lOi; + wire_w_lg_n0Oil195w(0) <= NOT n0Oil; + wire_w_lg_rxpcs_reset_int2w(0) <= NOT rxpcs_reset_int; + wire_w_lg_n0llO262w(0) <= n0llO OR n0lOi; + wire_w_lg_w_rmask_count_range68w69w(0) <= wire_w_rmask_count_range68w(0) XOR n1iO; + wire_w_lg_w_rmask_count_range84w85w(0) <= wire_w_rmask_count_range84w(0) XOR n1lO; + wire_w_lg_w_rmask_count_range92w93w(0) <= wire_w_rmask_count_range92w(0) XOR n1Oi; + wire_w_lg_w_rwait_count_range147w148w(0) <= wire_w_rwait_count_range147w(0) XOR nll1l; + wire_w_lg_w_rwait_count_range158w159w(0) <= wire_w_rwait_count_range158w(0) XOR nllii; + wire_w_lg_w_rwait_count_range170w171w(0) <= wire_w_rwait_count_range170w(0) XOR nlliO; + wire_w_lg_w_rwait_count_range186w187w(0) <= wire_w_rwait_count_range186w(0) XOR nlllO; + early_eios <= wire_nli1O_dataout; + eidle_exit <= niOOO; + eiosdetect_int <= nii0i; + inferred_rxvalid <= wire_nli1l_dataout; + ltr <= wire_nliii_dataout; + n0ilO <= (((((((((adata(0) AND adata(1)) AND (NOT adata(2))) AND (NOT adata(3))) AND (NOT adata(4))) AND (NOT adata(5))) AND (NOT adata(6))) AND adata(7)) AND (NOT adata(8))) AND adata(9)); + n0iOi <= ((((((((((NOT adata(0)) AND (NOT adata(1))) AND adata(2)) AND adata(3)) AND adata(4)) AND adata(5)) AND adata(6)) AND (NOT adata(7))) AND adata(8)) AND (NOT adata(9))); + n0iOl <= (((((((((adata(0) AND adata(1)) AND (NOT adata(2))) AND (NOT adata(3))) AND (NOT adata(4))) AND (NOT adata(5))) AND adata(6)) AND adata(7)) AND (NOT adata(8))) AND (NOT adata(9))); + n0iOO <= ((((((((((NOT adata(0)) AND (NOT adata(1))) AND adata(2)) AND adata(3)) AND adata(4)) AND adata(5)) AND (NOT adata(6))) AND (NOT adata(7))) AND adata(8)) AND adata(9)); + n0l0i <= (nl0iO AND nll0l); + n0l0l <= ((wire_nii1i_dataout AND n0Oil) AND (n0l0O44 XOR n0l0O43)); + n0l1l <= ((wire_ni_w_lg_w_lg_nl1li346w347w(0) AND wire_ni_w_lg_nl1ii348w(0)) AND nl10O); + n0l1O <= (((nl11l OR nl11i) OR niOOO) OR niili); + n0lil <= (n0liO OR (wire_nii1i_dataout AND wire_ni_w_lg_nl1ll241w(0))); + n0liO <= ((wire_ni_w_lg_nlO226w(0) AND wire_ni_w_lg_nl0iO227w(0)) AND (n0lli42 XOR n0lli41)); + n0llO <= (wire_nii1i_dataout AND ni0li); + n0lOi <= (wire_nii1i_dataout AND ni0Oi); + n0lOl <= ((wire_ni_w_lg_nlO226w(0) AND (wire_ni_w_lg_w_lg_nl0iO227w228w(0) AND (n0O1l38 XOR n0O1l37))) AND (n0lOO40 XOR n0lOO39)); + n0Oil <= (nlO AND nl1ll); + ni01l <= '1'; + ni11l <= ((((((((NOT (wire_w_lg_w_rwait_count_range147w148w(0) XOR (NOT (n0OOO24 XOR n0OOO23)))) AND (NOT (rwait_count(1) XOR nll0O))) AND (NOT (wire_w_lg_w_rwait_count_range158w159w(0) XOR (NOT (n0OOi26 XOR n0OOi25))))) AND (NOT (rwait_count(3) XOR nllil))) AND (NOT (wire_w_lg_w_rwait_count_range170w171w(0) XOR (NOT (n0Oll28 XOR n0Oll27))))) AND (NOT (rwait_count(5) XOR nllli))) AND (NOT (rwait_count(6) XOR nllll))) AND (NOT (wire_w_lg_w_rwait_count_range186w187w(0) XOR (NOT (n0OiO30 XOR n0OiO29))))); + ni1ll <= ((((((((((NOT (rmask_count(0) XOR n11O)) AND (NOT (rmask_count(1) XOR n1ii))) AND (NOT (rmask_count(2) XOR n1il))) AND (NOT (wire_w_lg_w_rmask_count_range68w69w(0) XOR (NOT (ni1iO14 XOR ni1iO13))))) AND (NOT (rmask_count(4) XOR n1li))) AND (NOT (rmask_count(5) XOR n1ll))) AND (NOT (wire_w_lg_w_rmask_count_range84w85w(0) XOR (NOT (ni1ii16 XOR ni1ii15))))) AND (NOT (wire_w_lg_w_rmask_count_range92w93w(0) XOR (NOT (ni10l18 XOR ni10l17))))) AND (NOT (rmask_count(8) XOR n1Ol))) AND (NOT (rmask_count(9) XOR n1OO))); + wire_w_rmask_count_range68w(0) <= rmask_count(3); + wire_w_rmask_count_range84w(0) <= rmask_count(6); + wire_w_rmask_count_range92w(0) <= rmask_count(7); + wire_w_rwait_count_range147w(0) <= rwait_count(0); + wire_w_rwait_count_range158w(0) <= rwait_count(2); + wire_w_rwait_count_range170w(0) <= rwait_count(4); + wire_w_rwait_count_range186w(0) <= rwait_count(7); + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0l0O43 <= n0l0O44; + END IF; + if (now = 0 ns) then + n0l0O43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0l0O44 <= n0l0O43; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0l1i45 <= n0l1i46; + END IF; + if (now = 0 ns) then + n0l1i45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0l1i46 <= n0l1i45; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0lli41 <= n0lli42; + END IF; + if (now = 0 ns) then + n0lli41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0lli42 <= n0lli41; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0lOO39 <= n0lOO40; + END IF; + if (now = 0 ns) then + n0lOO39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0lOO40 <= n0lOO39; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O0i35 <= n0O0i36; + END IF; + if (now = 0 ns) then + n0O0i35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O0i36 <= n0O0i35; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O0l33 <= n0O0l34; + END IF; + if (now = 0 ns) then + n0O0l33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O0l34 <= n0O0l33; + END IF; + END PROCESS; + wire_n0O0l34_w_lg_w_lg_q200w201w(0) <= wire_n0O0l34_w_lg_q200w(0) AND nl10O; + wire_n0O0l34_w_lg_q200w(0) <= n0O0l34 XOR n0O0l33; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O0O31 <= n0O0O32; + END IF; + if (now = 0 ns) then + n0O0O31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O0O32 <= n0O0O31; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O1l37 <= n0O1l38; + END IF; + if (now = 0 ns) then + n0O1l37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0O1l38 <= n0O1l37; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0OiO29 <= n0OiO30; + END IF; + if (now = 0 ns) then + n0OiO29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0OiO30 <= n0OiO29; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0Oll27 <= n0Oll28; + END IF; + if (now = 0 ns) then + n0Oll27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0Oll28 <= n0Oll27; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0OOi25 <= n0OOi26; + END IF; + if (now = 0 ns) then + n0OOi25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0OOi26 <= n0OOi25; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0OOO23 <= n0OOO24; + END IF; + if (now = 0 ns) then + n0OOO23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN n0OOO24 <= n0OOO23; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni01i3 <= ni01i4; + END IF; + if (now = 0 ns) then + ni01i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni01i4 <= ni01i3; + END IF; + END PROCESS; + wire_ni01i4_w_lg_w_lg_q4w5w(0) <= wire_ni01i4_w_lg_q4w(0) AND n11O; + wire_ni01i4_w_lg_q4w(0) <= ni01i4 XOR ni01i3; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni01O1 <= ni01O2; + END IF; + if (now = 0 ns) then + ni01O1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni01O2 <= ni01O1; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni10i19 <= ni10i20; + END IF; + if (now = 0 ns) then + ni10i19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni10i20 <= ni10i19; + END IF; + END PROCESS; + wire_ni10i20_w_lg_w_lg_q111w112w(0) <= wire_ni10i20_w_lg_q111w(0) AND nllii; + wire_ni10i20_w_lg_q111w(0) <= ni10i20 XOR ni10i19; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni10l17 <= ni10l18; + END IF; + if (now = 0 ns) then + ni10l17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni10l18 <= ni10l17; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni11O21 <= ni11O22; + END IF; + if (now = 0 ns) then + ni11O21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni11O22 <= ni11O21; + END IF; + END PROCESS; + wire_ni11O22_w_lg_w_lg_q114w115w(0) <= wire_ni11O22_w_lg_q114w(0) AND nllil; + wire_ni11O22_w_lg_q114w(0) <= ni11O22 XOR ni11O21; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1ii15 <= ni1ii16; + END IF; + if (now = 0 ns) then + ni1ii15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1ii16 <= ni1ii15; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1iO13 <= ni1iO14; + END IF; + if (now = 0 ns) then + ni1iO13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1iO14 <= ni1iO13; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1lO11 <= ni1lO12; + END IF; + if (now = 0 ns) then + ni1lO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1lO12 <= ni1lO11; + END IF; + END PROCESS; + wire_ni1lO12_w_lg_w_lg_q22w23w(0) <= wire_ni1lO12_w_lg_q22w(0) AND n1OO; + wire_ni1lO12_w_lg_q22w(0) <= ni1lO12 XOR ni1lO11; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1Oi10 <= ni1Oi9; + END IF; + END PROCESS; + wire_ni1Oi10_w_lg_w_lg_q18w19w(0) <= wire_ni1Oi10_w_lg_q18w(0) AND n1Oi; + wire_ni1Oi10_w_lg_q18w(0) <= ni1Oi10 XOR ni1Oi9; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1Oi9 <= ni1Oi10; + END IF; + if (now = 0 ns) then + ni1Oi9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1Ol7 <= ni1Ol8; + END IF; + if (now = 0 ns) then + ni1Ol7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1Ol8 <= ni1Ol7; + END IF; + END PROCESS; + wire_ni1Ol8_w_lg_w_lg_q15w16w(0) <= wire_ni1Ol8_w_lg_q15w(0) AND n1lO; + wire_ni1Ol8_w_lg_q15w(0) <= ni1Ol8 XOR ni1Ol7; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1OO5 <= ni1OO6; + END IF; + if (now = 0 ns) then + ni1OO5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN ni1OO6 <= ni1OO5; + END IF; + END PROCESS; + wire_ni1OO6_w_lg_w_lg_q10w11w(0) <= wire_ni1OO6_w_lg_q10w(0) AND n1iO; + wire_ni1OO6_w_lg_q10w(0) <= ni1OO6 XOR ni1OO5; + PROCESS (rcvd_clk, wire_ni_CLRN) + BEGIN + IF (wire_ni_CLRN = '0') THEN + n10O <= '0'; + n11O <= '0'; + n1ii <= '0'; + n1il <= '0'; + n1iO <= '0'; + n1li <= '0'; + n1ll <= '0'; + n1lO <= '0'; + n1Oi <= '0'; + n1Ol <= '0'; + n1OO <= '0'; + ni0li <= '0'; + ni0Oi <= '0'; + nii0i <= '0'; + nii0O <= '0'; + niili <= '0'; + niOOO <= '0'; + nl <= '0'; + nl0il <= '0'; + nl0iO <= '0'; + nl0li <= '0'; + nl0ll <= '0'; + nl0lO <= '0'; + nl0Oi <= '0'; + nl0Ol <= '0'; + nl0OO <= '0'; + nl10O <= '0'; + nl11i <= '0'; + nl11l <= '0'; + nl11O <= '0'; + nl1ii <= '0'; + nl1il <= '0'; + nl1iO <= '0'; + nl1li <= '0'; + nl1ll <= '0'; + nli0O <= '0'; + nli1i <= '0'; + nll0l <= '0'; + nll0O <= '0'; + nll1l <= '0'; + nllii <= '0'; + nllil <= '0'; + nlliO <= '0'; + nllli <= '0'; + nllll <= '0'; + nlllO <= '0'; + nlO <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + n10O <= wire_n10i_dataout; + n11O <= wire_n01i_dataout; + n1ii <= wire_n01l_dataout; + n1il <= wire_n01O_dataout; + n1iO <= wire_n00i_dataout; + n1li <= wire_n00l_dataout; + n1ll <= wire_n00O_dataout; + n1lO <= wire_n0ii_dataout; + n1Oi <= wire_n0il_dataout; + n1Ol <= wire_n0iO_dataout; + n1OO <= wire_n0li_dataout; + ni0li <= wire_ni0ll_dataout; + ni0Oi <= ni0li; + nii0i <= nii0O; + nii0O <= wire_nil0l_dataout; + niili <= wire_niill_o; + niOOO <= wire_niiOi_o; + nl <= wire_nO_dataout; + nl0il <= pipe_loopbk; + nl0iO <= nl0li; + nl0li <= nl0ll; + nl0ll <= nl0lO; + nl0lO <= nl0Oi; + nl0Oi <= nl0Ol; + nl0Ol <= nl0OO; + nl0OO <= sigdet; + nl10O <= wire_nl1lO_dataout; + nl11i <= wire_niiOO_o; + nl11l <= wire_nil1i_o; + nl11O <= wire_nil1l_dataout; + nl1ii <= wire_nl1Oi_dataout; + nl1il <= wire_nl1Ol_dataout; + nl1iO <= wire_nl1OO_dataout; + nl1li <= wire_nl01i_dataout; + nl1ll <= nl0il; + nli0O <= wire_niliO_o; + nli1i <= wire_nilli_o; + nll0l <= wire_nll1O_dataout; + nll0O <= wire_nllOl_dataout; + nll1l <= wire_nllOi_dataout; + nllii <= wire_nllOO_dataout; + nllil <= wire_nlO1i_dataout; + nlliO <= wire_nlO1l_dataout; + nllli <= wire_nlO1O_dataout; + nllll <= wire_nlO0i_dataout; + nlllO <= wire_nlO0l_dataout; + nlO <= nl; + END IF; + END PROCESS; + wire_ni_CLRN <= ((ni01O2 XOR ni01O1) AND wire_w_lg_rxpcs_reset_int2w(0)); + wire_ni_w_lg_w_lg_nl1li346w347w(0) <= wire_ni_w_lg_nl1li346w(0) AND nl1il; + wire_ni_w_lg_w_lg_nl0iO227w228w(0) <= wire_ni_w_lg_nl0iO227w(0) AND nilil; + wire_ni_w_lg_nl1li346w(0) <= nl1li AND nl1iO; + wire_ni_w_lg_n10O250w(0) <= NOT n10O; + wire_ni_w_lg_niili224w(0) <= NOT niili; + wire_ni_w_lg_niOOO47w(0) <= NOT niOOO; + wire_ni_w_lg_nl0iO227w(0) <= NOT nl0iO; + wire_ni_w_lg_nl11i139w(0) <= NOT nl11i; + wire_ni_w_lg_nl1ii348w(0) <= NOT nl1ii; + wire_ni_w_lg_nl1ll241w(0) <= NOT nl1ll; + wire_ni_w_lg_nlO226w(0) <= NOT nlO; + wire_ni_w_lg_w_lg_nl11O285w286w(0) <= wire_ni_w_lg_nl11O285w(0) OR niili; + wire_ni_w_lg_nl11O285w(0) <= nl11O OR nl11i; + PROCESS (rcvd_clk, wire_nilii_PRN, rxpcs_reset_int) + BEGIN + IF (wire_nilii_PRN = '0') THEN + nilil <= '1'; + ELSIF (rxpcs_reset_int = '1') THEN + nilil <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + IF (wire_nilii_ENA = '1') THEN + nilil <= ni01l; + END IF; + END IF; + END PROCESS; + wire_nilii_ENA <= (nl0li AND wire_ni_w_lg_nl0iO227w(0)); + wire_nilii_PRN <= (n0l1i46 XOR n0l1i45); + PROCESS (rcvd_clk, rxpcs_reset_int, wire_nl10i_CLRN) + BEGIN + IF (rxpcs_reset_int = '1') THEN + niiii <= '1'; + niiil <= '1'; + niiiO <= '1'; + nl10l <= '1'; + ELSIF (wire_nl10i_CLRN = '0') THEN + niiii <= '0'; + niiil <= '0'; + niiiO <= '0'; + nl10l <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + niiii <= niiil; + niiil <= niiiO; + niiiO <= (NOT (nl11i OR niOOO)); + nl10l <= wire_nil1O_o; + END IF; + if (now = 0 ns) then + niiii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niiil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niiiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl10l <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl10i_CLRN <= (n0O0i36 XOR n0O0i35); + wire_nl10i_w_lg_w_lg_w_lg_nl10l321w322w323w(0) <= wire_nl10i_w_lg_w_lg_nl10l321w322w(0) OR niili; + wire_nl10i_w_lg_w_lg_nl10l334w335w(0) <= wire_nl10i_w_lg_nl10l334w(0) OR niOOO; + wire_nl10i_w_lg_w_lg_nl10l321w322w(0) <= wire_nl10i_w_lg_nl10l321w(0) OR nl11l; + wire_nl10i_w_lg_nl10l334w(0) <= nl10l OR nl11i; + wire_nl10i_w_lg_nl10l321w(0) <= nl10l OR nl11O; + wire_n00i_dataout <= wire_n0ll_o(3) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n00l_dataout <= wire_n0ll_o(4) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n00O_dataout <= wire_n0ll_o(5) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n01i_dataout <= wire_n0ll_o(0) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n01l_dataout <= wire_n0ll_o(1) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n01O_dataout <= wire_n0ll_o(2) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n0ii_dataout <= wire_n0ll_o(6) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n0il_dataout <= wire_n0ll_o(7) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n0iO_dataout <= wire_n0ll_o(8) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n0li_dataout <= wire_n0ll_o(9) AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n10i_dataout <= wire_n10l_dataout AND NOT(wire_ni_w_lg_niOOO47w(0)); + wire_n10l_dataout <= n10O OR ni1ll; + wire_ni0ll_dataout <= adata_valid AND (n0iOi OR n0ilO); + wire_nii1i_dataout <= adata_valid AND (n0iOO OR n0iOl); + wire_nil0l_dataout <= wire_nii1i_dataout AND (nl11O OR nl11l); + wire_nil1l_dataout <= wire_niOil_dataout AND nl10l; + wire_nilOi_dataout <= wire_ni_w_lg_n10O250w(0) AND NOT(n0liO); + wire_nilOl_dataout <= n10O AND NOT(n0liO); + wire_niO1i_dataout <= wire_w_lg_n0l0l248w(0) AND NOT(n0lil); + wire_niO1l_dataout <= n0l0l AND NOT(n0lil); + wire_niOii_dataout <= wire_niOli_dataout AND NOT(n0lOl); + wire_niOil_dataout <= n0llO AND NOT(n0lOl); + wire_niOiO_dataout <= wire_niOll_dataout AND NOT(n0lOl); + wire_niOli_dataout <= n0lOi AND NOT(n0llO); + wire_niOll_dataout <= wire_w_lg_n0lOi236w(0) AND NOT(n0llO); + wire_nl00i_dataout <= wire_nl0ii_o(2) WHEN niili = '1' ELSE nl1il; + wire_nl00l_dataout <= wire_nl0ii_o(3) WHEN niili = '1' ELSE nl1iO; + wire_nl00O_dataout <= wire_nl0ii_o(4) WHEN niili = '1' ELSE nl1li; + wire_nl01i_dataout <= wire_nl00O_dataout AND NOT(wire_ni_w_lg_niili224w(0)); + wire_nl01l_dataout <= wire_nl0ii_o(0) WHEN niili = '1' ELSE nl10O; + wire_nl01O_dataout <= wire_nl0ii_o(1) WHEN niili = '1' ELSE nl1ii; + wire_nl1lO_dataout <= wire_nl01l_dataout AND NOT(wire_ni_w_lg_niili224w(0)); + wire_nl1Oi_dataout <= wire_nl01O_dataout AND NOT(wire_ni_w_lg_niili224w(0)); + wire_nl1Ol_dataout <= wire_nl00i_dataout AND NOT(wire_ni_w_lg_niili224w(0)); + wire_nl1OO_dataout <= wire_nl00l_dataout AND NOT(wire_ni_w_lg_niili224w(0)); + wire_nli1l_dataout <= niiii OR NOT(rrxvalid_mask); + wire_nli1O_dataout <= nli1i AND (wire_w_lg_rcid_en196w(0) AND (n0O0O32 XOR n0O0O31)); + wire_nliii_dataout <= nli0O WHEN rcdr_ctrl_en = '1' ELSE pld_ltr; + wire_nll0i_dataout <= nll0l OR ni11l; + wire_nll1O_dataout <= wire_nll0i_dataout AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nllOi_dataout <= wire_nlO0O_o(0) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nllOl_dataout <= wire_nlO0O_o(1) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nllOO_dataout <= wire_nlO0O_o(2) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nlO0i_dataout <= wire_nlO0O_o(6) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nlO0l_dataout <= wire_nlO0O_o(7) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nlO1i_dataout <= wire_nlO0O_o(3) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nlO1l_dataout <= wire_nlO0O_o(4) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nlO1O_dataout <= wire_nlO0O_o(5) AND NOT(wire_ni_w_lg_nl11i139w(0)); + wire_nO_dataout <= gen2ngen1 WHEN rindv_rx = '1' ELSE gen2ngen1_bundle; + wire_n0ll_a <= ( wire_ni1lO12_w_lg_w_lg_q22w23w & n1Ol & wire_ni1Oi10_w_lg_w_lg_q18w19w & wire_ni1Ol8_w_lg_w_lg_q15w16w & n1ll & n1li & wire_ni1OO6_w_lg_w_lg_q10w11w & n1il & n1ii & wire_ni01i4_w_lg_w_lg_q4w5w); + wire_n0ll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_n0ll_a, + b => wire_n0ll_b, + cin => wire_gnd, + o => wire_n0ll_o + ); + wire_nl0ii_a <= ( nl1li & nl1iO & nl1il & nl1ii & wire_n0O0l34_w_lg_w_lg_q200w201w); + wire_nl0ii_b <= ( "0" & "0" & "0" & "0" & "1"); + nl0ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl0ii_a, + b => wire_nl0ii_b, + cin => wire_gnd, + o => wire_nl0ii_o + ); + wire_nlO0O_a <= ( nlllO & nllll & nllli & nlliO & wire_ni11O22_w_lg_w_lg_q114w115w & wire_ni10i20_w_lg_w_lg_q111w112w & nll0O & nll1l); + wire_nlO0O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlO0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlO0O_a, + b => wire_nlO0O_b, + cin => wire_gnd, + o => wire_nlO0O_o + ); + wire_niill_data <= ( "0" & wire_niO1l_dataout & wire_niO1l_dataout & wire_w_lg_n0l1l337w); + wire_niill_sel <= ( wire_nl10i_w_lg_w_lg_nl10l334w335w & nl11O & nl11l & niili); + niill : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_niill_data, + o => wire_niill_o, + sel => wire_niill_sel + ); + wire_niiOi_data <= ( "0" & n0l0i & wire_nilOi_dataout); + wire_niiOi_sel <= ( wire_nl10i_w_lg_w_lg_w_lg_nl10l321w322w323w & nl11i & niOOO); + niiOi : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niiOi_data, + o => wire_niiOi_o, + sel => wire_niiOi_sel + ); + wire_niiOO_data <= ( n0lOl & n0lil & n0lil & wire_w_lg_n0l0i274w & n0liO & n0l1l); + wire_niiOO_sel <= ( nl10l & nl11O & nl11l & nl11i & niOOO & niili); + niiOO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_niiOO_data, + o => wire_niiOO_o, + sel => wire_niiOO_sel + ); + wire_nil1i_data <= ( wire_niOii_dataout & wire_niO1i_dataout & "0"); + wire_nil1i_sel <= ( nl10l & nl11O & n0l1O); + nil1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nil1i_data, + o => wire_nil1i_o, + sel => wire_nil1i_sel + ); + wire_nil1O_data <= ( wire_niOiO_dataout & "0" & wire_niO1i_dataout & wire_nilOl_dataout); + wire_nil1O_sel <= ( nl10l & wire_ni_w_lg_w_lg_nl11O285w286w & nl11l & niOOO); + nil1O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nil1O_data, + o => wire_nil1O_o, + sel => wire_nil1O_sel + ); + wire_niliO_data <= ( n0lOl & n0lil & n0lil & wire_w_lg_n0l0i274w & n0liO & n0l1l); + wire_niliO_sel <= ( nl10l & nl11O & nl11l & nl11i & niOOO & niili); + niliO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_niliO_data, + o => wire_niliO_o, + sel => wire_niliO_sel + ); + wire_nilli_data <= ( wire_w_lg_n0llO262w & wire_niO1i_dataout & "0"); + wire_nilli_sel <= ( nl10l & nl11O & n0l1O); + nilli : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nilli_data, + o => wire_nilli_o, + sel => wire_nilli_sel + ); + + END RTL; --cycloneiv_hssi_rx_digi_cdr_ctrl +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 529 mux21 1169 oper_add 22 oper_decoder 15 oper_less_than 18 oper_mux 4 cycloneiv_hssi_rx_digis_ram20x16_syn 2 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_comp_chnl_top IS + PORT + ( + align_status : IN STD_LOGIC; + align_status_sync : OUT STD_LOGIC; + align_status_sync_0 : IN STD_LOGIC; + align_status_sync_2 : IN STD_LOGIC; + audi : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + audi_pre : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + cg_comp_rd_d_ch0 : IN STD_LOGIC; + cg_comp_rd_d_ch1 : IN STD_LOGIC; + cg_comp_rd_d_ch2 : IN STD_LOGIC; + cg_comp_rd_d_ch3 : IN STD_LOGIC; + cg_comp_rd_d_out : OUT STD_LOGIC; + cg_comp_wr_ch0 : IN STD_LOGIC; + cg_comp_wr_ch1 : IN STD_LOGIC; + cg_comp_wr_ch2 : IN STD_LOGIC; + cg_comp_wr_ch3 : IN STD_LOGIC; + cg_comp_wr_out : OUT STD_LOGIC; + clk_1 : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + cmpfifourst : IN STD_LOGIC; + comp_curr_st : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + cudi : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + cudi_valid : OUT STD_LOGIC; + del_cond_met_0 : IN STD_LOGIC; + del_cond_met_out : OUT STD_LOGIC; + dskwclksel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + fifo_cnt : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + fifo_ovr_0 : IN STD_LOGIC; + fifo_ovr_out : OUT STD_LOGIC; + fifo_rd_in_comp_0 : IN STD_LOGIC; + fifo_rd_in_comp_2 : IN STD_LOGIC; + fifo_rd_out_comp : OUT STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + hard_reset : IN STD_LOGIC; + inferred_rxvalid : IN STD_LOGIC; + insert_incomplete_0 : IN STD_LOGIC; + insert_incomplete_out : OUT STD_LOGIC; + is_lane0 : IN STD_LOGIC; + latency_comp_0 : IN STD_LOGIC; + latency_comp_out : OUT STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rclkcmpsq1n : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + rclkcmpsq1p : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + rclkcmpsqmd : IN STD_LOGIC; + rcmpfifourst : IN STD_LOGIC; + rdel_threshold : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + rdenable : IN STD_LOGIC; + rdfifo_almost_empty : OUT STD_LOGIC; + rdfifo_almost_full : OUT STD_LOGIC; + rdfifo_empty : OUT STD_LOGIC; + rdfifo_full : OUT STD_LOGIC; + rdwidth_rx : IN STD_LOGIC; + rempty_threshold : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rev_loop_data : OUT STD_LOGIC_VECTOR (19 DOWNTO 0); + rfreq_sel : IN STD_LOGIC; + rfull_threshold : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + rgenericfifo : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rins_threshold : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + rmatchen : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rskpsetbased : IN STD_LOGIC; + rstart_threshold : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rtruebac2bac : IN STD_LOGIC; + rwa_6g_en : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + skpos_det : OUT STD_LOGIC; + soft_reset : IN STD_LOGIC; + sudi : IN STD_LOGIC_VECTOR (27 DOWNTO 0); + sudi_pre : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + sync_status : IN STD_LOGIC; + wrenable : IN STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_comp_chnl_top; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_comp_chnl_top IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nli0O0O61 : STD_LOGIC := '0'; + SIGNAL nli0O0O62 : STD_LOGIC := '0'; + SIGNAL nliil1i59 : STD_LOGIC := '0'; + SIGNAL nliil1i60 : STD_LOGIC := '0'; + SIGNAL nliil1l57 : STD_LOGIC := '0'; + SIGNAL nliil1l58 : STD_LOGIC := '0'; + SIGNAL nliiOOi55 : STD_LOGIC := '0'; + SIGNAL nliiOOi56 : STD_LOGIC := '0'; + SIGNAL nliiOOl53 : STD_LOGIC := '0'; + SIGNAL nliiOOl54 : STD_LOGIC := '0'; + SIGNAL nliiOOO51 : STD_LOGIC := '0'; + SIGNAL nliiOOO52 : STD_LOGIC := '0'; + SIGNAL nlil01l49 : STD_LOGIC := '0'; + SIGNAL nlil01l50 : STD_LOGIC := '0'; + SIGNAL nlil0li47 : STD_LOGIC := '0'; + SIGNAL nlil0li48 : STD_LOGIC := '0'; + SIGNAL nlil0Ol45 : STD_LOGIC := '0'; + SIGNAL nlil0Ol46 : STD_LOGIC := '0'; + SIGNAL nlili0l43 : STD_LOGIC := '0'; + SIGNAL nlili0l44 : STD_LOGIC := '0'; + SIGNAL nlilill41 : STD_LOGIC := '0'; + SIGNAL nlilill42 : STD_LOGIC := '0'; + SIGNAL wire_nlilill42_w_lg_w_lg_q405w406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlilill42_w_lg_q405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlililO39 : STD_LOGIC := '0'; + SIGNAL nlililO40 : STD_LOGIC := '0'; + SIGNAL wire_nlililO40_w_lg_w_lg_q396w397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlililO40_w_lg_q396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliliOi37 : STD_LOGIC := '0'; + SIGNAL nliliOi38 : STD_LOGIC := '0'; + SIGNAL wire_nliliOi38_w_lg_w_lg_q369w370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliOi38_w_lg_q369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliliOl35 : STD_LOGIC := '0'; + SIGNAL nliliOl36 : STD_LOGIC := '0'; + SIGNAL wire_nliliOl36_w_lg_w_lg_q332w333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliOl36_w_lg_q332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliliOO33 : STD_LOGIC := '0'; + SIGNAL nliliOO34 : STD_LOGIC := '0'; + SIGNAL wire_nliliOO34_w_lg_w_lg_q166w167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliOO34_w_lg_q166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlill0l25 : STD_LOGIC := '0'; + SIGNAL nlill0l26 : STD_LOGIC := '0'; + SIGNAL wire_nlill0l26_w_lg_w_lg_q124w125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0l26_w_lg_q124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlill1i31 : STD_LOGIC := '0'; + SIGNAL nlill1i32 : STD_LOGIC := '0'; + SIGNAL wire_nlill1i32_w_lg_w_lg_q155w156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill1i32_w_lg_q155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlill1l29 : STD_LOGIC := '0'; + SIGNAL nlill1l30 : STD_LOGIC := '0'; + SIGNAL wire_nlill1l30_w_lg_w_lg_q152w153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill1l30_w_lg_q152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlill1O27 : STD_LOGIC := '0'; + SIGNAL nlill1O28 : STD_LOGIC := '0'; + SIGNAL wire_nlill1O28_w_lg_q140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlilliO23 : STD_LOGIC := '0'; + SIGNAL nlilliO24 : STD_LOGIC := '0'; + SIGNAL nlillll21 : STD_LOGIC := '0'; + SIGNAL nlillll22 : STD_LOGIC := '0'; + SIGNAL nlilO0O15 : STD_LOGIC := '0'; + SIGNAL nlilO0O16 : STD_LOGIC := '0'; + SIGNAL nlilO1i19 : STD_LOGIC := '0'; + SIGNAL nlilO1i20 : STD_LOGIC := '0'; + SIGNAL nlilO1O17 : STD_LOGIC := '0'; + SIGNAL nlilO1O18 : STD_LOGIC := '0'; + SIGNAL nlilOli13 : STD_LOGIC := '0'; + SIGNAL nlilOli14 : STD_LOGIC := '0'; + SIGNAL nlilOlO11 : STD_LOGIC := '0'; + SIGNAL nlilOlO12 : STD_LOGIC := '0'; + SIGNAL wire_nlilOlO12_w_lg_q17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlilOOl10 : STD_LOGIC := '0'; + SIGNAL nlilOOl9 : STD_LOGIC := '0'; + SIGNAL nlilOOO7 : STD_LOGIC := '0'; + SIGNAL nlilOOO8 : STD_LOGIC := '0'; + SIGNAL nliO10i3 : STD_LOGIC := '0'; + SIGNAL nliO10i4 : STD_LOGIC := '0'; + SIGNAL nliO11l5 : STD_LOGIC := '0'; + SIGNAL nliO11l6 : STD_LOGIC := '0'; + SIGNAL nliO1iO1 : STD_LOGIC := '0'; + SIGNAL nliO1iO2 : STD_LOGIC := '0'; + SIGNAL n0111i : STD_LOGIC := '0'; + SIGNAL n0111l : STD_LOGIC := '0'; + SIGNAL n1000i : STD_LOGIC := '0'; + SIGNAL n1000l : STD_LOGIC := '0'; + SIGNAL n1000O : STD_LOGIC := '0'; + SIGNAL n1001i : STD_LOGIC := '0'; + SIGNAL n1001l : STD_LOGIC := '0'; + SIGNAL n1001O : STD_LOGIC := '0'; + SIGNAL n100ii : STD_LOGIC := '0'; + SIGNAL n100il : STD_LOGIC := '0'; + SIGNAL n100li : STD_LOGIC := '0'; + SIGNAL n100ll : STD_LOGIC := '0'; + SIGNAL n100lO : STD_LOGIC := '0'; + SIGNAL n100Oi : STD_LOGIC := '0'; + SIGNAL n100Ol : STD_LOGIC := '0'; + SIGNAL n100OO : STD_LOGIC := '0'; + SIGNAL n101Ol : STD_LOGIC := '0'; + SIGNAL n101OO : STD_LOGIC := '0'; + SIGNAL n10i0i : STD_LOGIC := '0'; + SIGNAL n10i0l : STD_LOGIC := '0'; + SIGNAL n10i0O : STD_LOGIC := '0'; + SIGNAL n10i1i : STD_LOGIC := '0'; + SIGNAL n10i1l : STD_LOGIC := '0'; + SIGNAL n10i1O : STD_LOGIC := '0'; + SIGNAL n10iii : STD_LOGIC := '0'; + SIGNAL n10iil : STD_LOGIC := '0'; + SIGNAL n10iiO : STD_LOGIC := '0'; + SIGNAL n10ili : STD_LOGIC := '0'; + SIGNAL n10ill : STD_LOGIC := '0'; + SIGNAL n10ilO : STD_LOGIC := '0'; + SIGNAL n10iOl : STD_LOGIC := '0'; + SIGNAL n10iOO : STD_LOGIC := '0'; + SIGNAL n10l0i : STD_LOGIC := '0'; + SIGNAL n10l0l : STD_LOGIC := '0'; + SIGNAL n10l0O : STD_LOGIC := '0'; + SIGNAL n10l1i : STD_LOGIC := '0'; + SIGNAL n10l1l : STD_LOGIC := '0'; + SIGNAL n10l1O : STD_LOGIC := '0'; + SIGNAL n10lii : STD_LOGIC := '0'; + SIGNAL n10lil : STD_LOGIC := '0'; + SIGNAL n10liO : STD_LOGIC := '0'; + SIGNAL n10lli : STD_LOGIC := '0'; + SIGNAL n10lll : STD_LOGIC := '0'; + SIGNAL n10llO : STD_LOGIC := '0'; + SIGNAL n10lOi : STD_LOGIC := '0'; + SIGNAL n10lOl : STD_LOGIC := '0'; + SIGNAL n10lOO : STD_LOGIC := '0'; + SIGNAL n10O1i : STD_LOGIC := '0'; + SIGNAL n10O1l : STD_LOGIC := '0'; + SIGNAL n10O1O : STD_LOGIC := '0'; + SIGNAL n110iO : STD_LOGIC := '0'; + SIGNAL n110li : STD_LOGIC := '0'; + SIGNAL n110ll : STD_LOGIC := '0'; + SIGNAL n110lO : STD_LOGIC := '0'; + SIGNAL n11iil : STD_LOGIC := '0'; + SIGNAL n11iiO : STD_LOGIC := '0'; + SIGNAL n11ili : STD_LOGIC := '0'; + SIGNAL n11ill : STD_LOGIC := '0'; + SIGNAL n11ilO : STD_LOGIC := '0'; + SIGNAL n11iOi : STD_LOGIC := '0'; + SIGNAL n11iOl : STD_LOGIC := '0'; + SIGNAL n11iOO : STD_LOGIC := '0'; + SIGNAL n11O0i : STD_LOGIC := '0'; + SIGNAL n11O0l : STD_LOGIC := '0'; + SIGNAL n11O0O : STD_LOGIC := '0'; + SIGNAL n11O1i : STD_LOGIC := '0'; + SIGNAL n11O1l : STD_LOGIC := '0'; + SIGNAL n11O1O : STD_LOGIC := '0'; + SIGNAL n1l : STD_LOGIC := '0'; + SIGNAL n1liil : STD_LOGIC := '0'; + SIGNAL n1liiO : STD_LOGIC := '0'; + SIGNAL n1lili : STD_LOGIC := '0'; + SIGNAL n1ll1i : STD_LOGIC := '0'; + SIGNAL n1ll1l : STD_LOGIC := '0'; + SIGNAL n1O00i : STD_LOGIC := '0'; + SIGNAL n1O00l : STD_LOGIC := '0'; + SIGNAL n1O01l : STD_LOGIC := '0'; + SIGNAL n1O01O : STD_LOGIC := '0'; + SIGNAL ni0OOi : STD_LOGIC := '0'; + SIGNAL ni0OOl : STD_LOGIC := '0'; + SIGNAL ni0OOO : STD_LOGIC := '0'; + SIGNAL nii00i : STD_LOGIC := '0'; + SIGNAL nii00l : STD_LOGIC := '0'; + SIGNAL nii00O : STD_LOGIC := '0'; + SIGNAL nii01i : STD_LOGIC := '0'; + SIGNAL nii01l : STD_LOGIC := '0'; + SIGNAL nii01O : STD_LOGIC := '0'; + SIGNAL nii0ii : STD_LOGIC := '0'; + SIGNAL nii0il : STD_LOGIC := '0'; + SIGNAL nii0iO : STD_LOGIC := '0'; + SIGNAL nii0ll : STD_LOGIC := '0'; + SIGNAL nii0Ol : STD_LOGIC := '0'; + SIGNAL nii0OO : STD_LOGIC := '0'; + SIGNAL nii10i : STD_LOGIC := '0'; + SIGNAL nii10l : STD_LOGIC := '0'; + SIGNAL nii10O : STD_LOGIC := '0'; + SIGNAL nii11i : STD_LOGIC := '0'; + SIGNAL nii11l : STD_LOGIC := '0'; + SIGNAL nii11O : STD_LOGIC := '0'; + SIGNAL nii1ii : STD_LOGIC := '0'; + SIGNAL nii1il : STD_LOGIC := '0'; + SIGNAL nii1iO : STD_LOGIC := '0'; + SIGNAL nii1li : STD_LOGIC := '0'; + SIGNAL nii1ll : STD_LOGIC := '0'; + SIGNAL nii1lO : STD_LOGIC := '0'; + SIGNAL nii1Oi : STD_LOGIC := '0'; + SIGNAL nii1Ol : STD_LOGIC := '0'; + SIGNAL nii1OO : STD_LOGIC := '0'; + SIGNAL niii1i : STD_LOGIC := '0'; + SIGNAL niOlOl : STD_LOGIC := '0'; + SIGNAL niOlOO : STD_LOGIC := '0'; + SIGNAL niOO0i : STD_LOGIC := '0'; + SIGNAL niOO0l : STD_LOGIC := '0'; + SIGNAL niOO0O : STD_LOGIC := '0'; + SIGNAL niOO1i : STD_LOGIC := '0'; + SIGNAL niOO1l : STD_LOGIC := '0'; + SIGNAL niOO1O : STD_LOGIC := '0'; + SIGNAL niOOii : STD_LOGIC := '0'; + SIGNAL niOOil : STD_LOGIC := '0'; + SIGNAL niOOli : STD_LOGIC := '0'; + SIGNAL niOOll : STD_LOGIC := '0'; + SIGNAL niOOlO : STD_LOGIC := '0'; + SIGNAL niOOOi : STD_LOGIC := '0'; + SIGNAL niOOOl : STD_LOGIC := '0'; + SIGNAL niOOOO : STD_LOGIC := '0'; + SIGNAL nl100i : STD_LOGIC := '0'; + SIGNAL nl100l : STD_LOGIC := '0'; + SIGNAL nl100O : STD_LOGIC := '0'; + SIGNAL nl101i : STD_LOGIC := '0'; + SIGNAL nl101l : STD_LOGIC := '0'; + SIGNAL nl101O : STD_LOGIC := '0'; + SIGNAL nl10ii : STD_LOGIC := '0'; + SIGNAL nl10il : STD_LOGIC := '0'; + SIGNAL nl10iO : STD_LOGIC := '0'; + SIGNAL nl10li : STD_LOGIC := '0'; + SIGNAL nl10ll : STD_LOGIC := '0'; + SIGNAL nl10lO : STD_LOGIC := '0'; + SIGNAL nl10Oi : STD_LOGIC := '0'; + SIGNAL nl10Ol : STD_LOGIC := '0'; + SIGNAL nl10OO : STD_LOGIC := '0'; + SIGNAL nl110i : STD_LOGIC := '0'; + SIGNAL nl110l : STD_LOGIC := '0'; + SIGNAL nl110O : STD_LOGIC := '0'; + SIGNAL nl111i : STD_LOGIC := '0'; + SIGNAL nl111l : STD_LOGIC := '0'; + SIGNAL nl111O : STD_LOGIC := '0'; + SIGNAL nl11ii : STD_LOGIC := '0'; + SIGNAL nl11il : STD_LOGIC := '0'; + SIGNAL nl11iO : STD_LOGIC := '0'; + SIGNAL nl11li : STD_LOGIC := '0'; + SIGNAL nl11ll : STD_LOGIC := '0'; + SIGNAL nl11lO : STD_LOGIC := '0'; + SIGNAL nl11OO : STD_LOGIC := '0'; + SIGNAL nl1i0i : STD_LOGIC := '0'; + SIGNAL nl1i1i : STD_LOGIC := '0'; + SIGNAL nl1i1l : STD_LOGIC := '0'; + SIGNAL nl1i1O : STD_LOGIC := '0'; + SIGNAL nli0il : STD_LOGIC := '0'; + SIGNAL nli0Ol : STD_LOGIC := '0'; + SIGNAL nli0OO : STD_LOGIC := '0'; + SIGNAL nli1ll : STD_LOGIC := '0'; + SIGNAL nli1lO : STD_LOGIC := '0'; + SIGNAL nli1Oi : STD_LOGIC := '0'; + SIGNAL nli1Ol : STD_LOGIC := '0'; + SIGNAL nlii0i : STD_LOGIC := '0'; + SIGNAL nlii0l : STD_LOGIC := '0'; + SIGNAL nlii0O : STD_LOGIC := '0'; + SIGNAL nlii1i : STD_LOGIC := '0'; + SIGNAL nlii1l : STD_LOGIC := '0'; + SIGNAL nliilO : STD_LOGIC := '0'; + SIGNAL nliiOi : STD_LOGIC := '0'; + SIGNAL nlil0i : STD_LOGIC := '0'; + SIGNAL nlil0l : STD_LOGIC := '0'; + SIGNAL nlil0O : STD_LOGIC := '0'; + SIGNAL nlil1O : STD_LOGIC := '0'; + SIGNAL nlilOl : STD_LOGIC := '0'; + SIGNAL nliO01l : STD_LOGIC := '0'; + SIGNAL nliO01O : STD_LOGIC := '0'; + SIGNAL nliO1i : STD_LOGIC := '0'; + SIGNAL nlll : STD_LOGIC := '0'; + SIGNAL nlO00OO : STD_LOGIC := '0'; + SIGNAL nlOi1iO : STD_LOGIC := '0'; + SIGNAL nlOiO0i : STD_LOGIC := '0'; + SIGNAL nlOiO0l : STD_LOGIC := '0'; + SIGNAL nlOiO0O : STD_LOGIC := '0'; + SIGNAL nlOiO1O : STD_LOGIC := '0'; + SIGNAL nlOiOii : STD_LOGIC := '0'; + SIGNAL nlOl0OO : STD_LOGIC := '0'; + SIGNAL nlOli0i : STD_LOGIC := '0'; + SIGNAL nlOli0l : STD_LOGIC := '0'; + SIGNAL nlOli0O : STD_LOGIC := '0'; + SIGNAL nlOli1i : STD_LOGIC := '0'; + SIGNAL nlOli1l : STD_LOGIC := '0'; + SIGNAL nlOli1O : STD_LOGIC := '0'; + SIGNAL nlOliii : STD_LOGIC := '0'; + SIGNAL nlOliil : STD_LOGIC := '0'; + SIGNAL nlOliiO : STD_LOGIC := '0'; + SIGNAL nlOlili : STD_LOGIC := '0'; + SIGNAL nlOlilO : STD_LOGIC := '0'; + SIGNAL nlOliOO : STD_LOGIC := '0'; + SIGNAL nlOll1i : STD_LOGIC := '0'; + SIGNAL nlOll1l : STD_LOGIC := '0'; + SIGNAL wire_n1i_CLRN : STD_LOGIC; + SIGNAL wire_n1i_PRN : STD_LOGIC; + SIGNAL wire_n1i_w_lg_w_lg_w_lg_w1366w1367w1368w1369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_w1400w1401w1402w1403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w1366w1367w1368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w1400w1401w1402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w1366w1367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w1400w1401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w1366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w1400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_w_lg_nii0il1342w1343w1345w1346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_w_lg_nii1ii1376w1377w1379w1380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_w_lg_nii0il1359w1361w1363w1364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_w_lg_nii1ii1393w1395w1397w1398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_nii0il1342w1343w1345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_nii1ii1376w1377w1379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_nii0il1359w1361w1363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_w_lg_nii1ii1393w1395w1397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_nii0il1342w1343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_nii1ii1376w1377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_nii0il1359w1361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_nii1ii1393w1395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_nlilOl458w459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n100ii3078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n1liil2156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii0il1342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii1ii1376w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_niOOii1337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nlii0O548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n1000l3079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n1000O3077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n110iO2150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n110li2133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n110ll2151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n110lO3096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11iil3094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11iiO3092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11ili3090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11ill3088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11ilO3086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11iOi3084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11iOl3083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11iOO1969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11O0i2094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11O0l2093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11O1i1953w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11O1l2088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_n11O1O2096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_ni0OOl1385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_ni0OOO1383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii00i1365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii00l1344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii00O1362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii01i1349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii01O1347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii0ii1360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii0il1359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii10i1378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii10l1396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii10O1394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii11l1381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii11O1399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii1ii1393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nii1OO1351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_niOO0l1338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_niOO0O1336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nli0il643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nlil0i484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nlil0l722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nlilOl458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_nlOi1iO2144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0l0iO : STD_LOGIC := '0'; + SIGNAL ni11ll : STD_LOGIC := '0'; + SIGNAL ni11lO : STD_LOGIC := '0'; + SIGNAL ni11Ol : STD_LOGIC := '0'; + SIGNAL nlliiOO : STD_LOGIC := '0'; + SIGNAL nllil1i : STD_LOGIC := '0'; + SIGNAL nllil1l : STD_LOGIC := '0'; + SIGNAL nlllO0l : STD_LOGIC := '0'; + SIGNAL wire_ni11Oi_CLRN : STD_LOGIC; + SIGNAL wire_ni11Oi_PRN : STD_LOGIC; + SIGNAL n0111O : STD_LOGIC := '0'; + SIGNAL n0l00l : STD_LOGIC := '0'; + SIGNAL n0l00O : STD_LOGIC := '0'; + SIGNAL n0l0ii : STD_LOGIC := '0'; + SIGNAL n0l0il : STD_LOGIC := '0'; + SIGNAL n0l0li : STD_LOGIC := '0'; + SIGNAL n0l0ll : STD_LOGIC := '0'; + SIGNAL n0l0lO : STD_LOGIC := '0'; + SIGNAL n0l0Oi : STD_LOGIC := '0'; + SIGNAL n0l0Ol : STD_LOGIC := '0'; + SIGNAL n0l0OO : STD_LOGIC := '0'; + SIGNAL n0li0i : STD_LOGIC := '0'; + SIGNAL n0li0l : STD_LOGIC := '0'; + SIGNAL n0li0O : STD_LOGIC := '0'; + SIGNAL n0li1i : STD_LOGIC := '0'; + SIGNAL n0li1l : STD_LOGIC := '0'; + SIGNAL n0li1O : STD_LOGIC := '0'; + SIGNAL n0liii : STD_LOGIC := '0'; + SIGNAL n0liil : STD_LOGIC := '0'; + SIGNAL n0liiO : STD_LOGIC := '0'; + SIGNAL n0lili : STD_LOGIC := '0'; + SIGNAL n0lill : STD_LOGIC := '0'; + SIGNAL n0lilO : STD_LOGIC := '0'; + SIGNAL n0liOi : STD_LOGIC := '0'; + SIGNAL n0liOl : STD_LOGIC := '0'; + SIGNAL n0O0ll : STD_LOGIC := '0'; + SIGNAL n0O0lO : STD_LOGIC := '0'; + SIGNAL n0O0Oi : STD_LOGIC := '0'; + SIGNAL n0O0Ol : STD_LOGIC := '0'; + SIGNAL n0O0OO : STD_LOGIC := '0'; + SIGNAL n0Oiil : STD_LOGIC := '0'; + SIGNAL n0OiOl : STD_LOGIC := '0'; + SIGNAL n0OiOO : STD_LOGIC := '0'; + SIGNAL n0Ol0i : STD_LOGIC := '0'; + SIGNAL n0Ol0l : STD_LOGIC := '0'; + SIGNAL n0Ol0O : STD_LOGIC := '0'; + SIGNAL n0Ol1l : STD_LOGIC := '0'; + SIGNAL n0Ol1O : STD_LOGIC := '0'; + SIGNAL n0OO1O : STD_LOGIC := '0'; + SIGNAL n0OOli : STD_LOGIC := '0'; + SIGNAL n0OOll : STD_LOGIC := '0'; + SIGNAL n1O : STD_LOGIC := '0'; + SIGNAL ni000i : STD_LOGIC := '0'; + SIGNAL ni000l : STD_LOGIC := '0'; + SIGNAL ni00il : STD_LOGIC := '0'; + SIGNAL ni00iO : STD_LOGIC := '0'; + SIGNAL ni00Oi : STD_LOGIC := '0'; + SIGNAL ni101i : STD_LOGIC := '0'; + SIGNAL ni101l : STD_LOGIC := '0'; + SIGNAL ni110i : STD_LOGIC := '0'; + SIGNAL ni110l : STD_LOGIC := '0'; + SIGNAL ni111i : STD_LOGIC := '0'; + SIGNAL ni111l : STD_LOGIC := '0'; + SIGNAL ni111O : STD_LOGIC := '0'; + SIGNAL ni11OO : STD_LOGIC := '0'; + SIGNAL ni1i0i : STD_LOGIC := '0'; + SIGNAL ni1i0l : STD_LOGIC := '0'; + SIGNAL ni1i0O : STD_LOGIC := '0'; + SIGNAL ni1i1l : STD_LOGIC := '0'; + SIGNAL ni1i1O : STD_LOGIC := '0'; + SIGNAL ni1llO : STD_LOGIC := '0'; + SIGNAL ni1O0i : STD_LOGIC := '0'; + SIGNAL ni1O0l : STD_LOGIC := '0'; + SIGNAL ni1O0O : STD_LOGIC := '0'; + SIGNAL ni1O1l : STD_LOGIC := '0'; + SIGNAL ni1O1O : STD_LOGIC := '0'; + SIGNAL nil : STD_LOGIC := '0'; + SIGNAL nliO00i : STD_LOGIC := '0'; + SIGNAL nliO1l : STD_LOGIC := '0'; + SIGNAL nlli00O : STD_LOGIC := '0'; + SIGNAL nlli0Oi : STD_LOGIC := '0'; + SIGNAL nlli0Ol : STD_LOGIC := '0'; + SIGNAL nlli1ii : STD_LOGIC := '0'; + SIGNAL nlli1il : STD_LOGIC := '0'; + SIGNAL nlli1iO : STD_LOGIC := '0'; + SIGNAL nlli1li : STD_LOGIC := '0'; + SIGNAL nlli1ll : STD_LOGIC := '0'; + SIGNAL nllii0l : STD_LOGIC := '0'; + SIGNAL nllii0O : STD_LOGIC := '0'; + SIGNAL nllii1O : STD_LOGIC := '0'; + SIGNAL nlliiii : STD_LOGIC := '0'; + SIGNAL nlliiil : STD_LOGIC := '0'; + SIGNAL nlliiiO : STD_LOGIC := '0'; + SIGNAL nlliiO : STD_LOGIC := '0'; + SIGNAL nllil0i : STD_LOGIC := '0'; + SIGNAL nllil0l : STD_LOGIC := '0'; + SIGNAL nllil1O : STD_LOGIC := '0'; + SIGNAL nllili : STD_LOGIC := '0'; + SIGNAL nllill : STD_LOGIC := '0'; + SIGNAL nllilO : STD_LOGIC := '0'; + SIGNAL nlliOi : STD_LOGIC := '0'; + SIGNAL nlliOl : STD_LOGIC := '0'; + SIGNAL nlliOO : STD_LOGIC := '0'; + SIGNAL nlll0i : STD_LOGIC := '0'; + SIGNAL nlll0l : STD_LOGIC := '0'; + SIGNAL nlll0O : STD_LOGIC := '0'; + SIGNAL nlll10l : STD_LOGIC := '0'; + SIGNAL nlll10O : STD_LOGIC := '0'; + SIGNAL nlll1i : STD_LOGIC := '0'; + SIGNAL nlll1ii : STD_LOGIC := '0'; + SIGNAL nlll1il : STD_LOGIC := '0'; + SIGNAL nlll1iO : STD_LOGIC := '0'; + SIGNAL nlll1l : STD_LOGIC := '0'; + SIGNAL nlll1li : STD_LOGIC := '0'; + SIGNAL nlll1O : STD_LOGIC := '0'; + SIGNAL nlllii : STD_LOGIC := '0'; + SIGNAL nlllil : STD_LOGIC := '0'; + SIGNAL nllliO : STD_LOGIC := '0'; + SIGNAL nllll0O : STD_LOGIC := '0'; + SIGNAL nlllli : STD_LOGIC := '0'; + SIGNAL nllllii : STD_LOGIC := '0'; + SIGNAL nlllliO : STD_LOGIC := '0'; + SIGNAL nlllll : STD_LOGIC := '0'; + SIGNAL nllllli : STD_LOGIC := '0'; + SIGNAL nllllO : STD_LOGIC := '0'; + SIGNAL nlllO0i : STD_LOGIC := '0'; + SIGNAL nlllO0O : STD_LOGIC := '0'; + SIGNAL nlllO1i : STD_LOGIC := '0'; + SIGNAL nlllO1l : STD_LOGIC := '0'; + SIGNAL nlllO1O : STD_LOGIC := '0'; + SIGNAL nlllOi : STD_LOGIC := '0'; + SIGNAL nlllOii : STD_LOGIC := '0'; + SIGNAL nlllOil : STD_LOGIC := '0'; + SIGNAL nlllOiO : STD_LOGIC := '0'; + SIGNAL nlllOl : STD_LOGIC := '0'; + SIGNAL nlllOli : STD_LOGIC := '0'; + SIGNAL nlllOll : STD_LOGIC := '0'; + SIGNAL nlllOlO : STD_LOGIC := '0'; + SIGNAL nlllOO : STD_LOGIC := '0'; + SIGNAL nlllOOi : STD_LOGIC := '0'; + SIGNAL nlllOOl : STD_LOGIC := '0'; + SIGNAL nlllOOO : STD_LOGIC := '0'; + SIGNAL nllO0i : STD_LOGIC := '0'; + SIGNAL nllO0l : STD_LOGIC := '0'; + SIGNAL nllO10i : STD_LOGIC := '0'; + SIGNAL nllO10l : STD_LOGIC := '0'; + SIGNAL nllO10O : STD_LOGIC := '0'; + SIGNAL nllO11i : STD_LOGIC := '0'; + SIGNAL nllO11l : STD_LOGIC := '0'; + SIGNAL nllO11O : STD_LOGIC := '0'; + SIGNAL nllO1i : STD_LOGIC := '0'; + SIGNAL nllO1ii : STD_LOGIC := '0'; + SIGNAL nllO1il : STD_LOGIC := '0'; + SIGNAL nllO1iO : STD_LOGIC := '0'; + SIGNAL nllO1l : STD_LOGIC := '0'; + SIGNAL nllO1li : STD_LOGIC := '0'; + SIGNAL nllO1O : STD_LOGIC := '0'; + SIGNAL nllOOi : STD_LOGIC := '0'; + SIGNAL nllOOl : STD_LOGIC := '0'; + SIGNAL nlO00ii : STD_LOGIC := '0'; + SIGNAL nlO00li : STD_LOGIC := '0'; + SIGNAL nlO00ll : STD_LOGIC := '0'; + SIGNAL nlO00lO : STD_LOGIC := '0'; + SIGNAL nlO00Oi : STD_LOGIC := '0'; + SIGNAL nlO00Ol : STD_LOGIC := '0'; + SIGNAL nlO011i : STD_LOGIC := '0'; + SIGNAL nlO011l : STD_LOGIC := '0'; + SIGNAL nlO01l : STD_LOGIC := '0'; + SIGNAL nlO01O : STD_LOGIC := '0'; + SIGNAL nlO10li : STD_LOGIC := '0'; + SIGNAL nlO10ll : STD_LOGIC := '0'; + SIGNAL nlO10lO : STD_LOGIC := '0'; + SIGNAL nlO10Oi : STD_LOGIC := '0'; + SIGNAL nlO1i0O : STD_LOGIC := '0'; + SIGNAL nlO1Oii : STD_LOGIC := '0'; + SIGNAL nlO1OiO : STD_LOGIC := '0'; + SIGNAL nlO1OOi : STD_LOGIC := '0'; + SIGNAL nlO1OOl : STD_LOGIC := '0'; + SIGNAL nlO1OOO : STD_LOGIC := '0'; + SIGNAL wire_nii_CLRN : STD_LOGIC; + SIGNAL wire_nii_w_lg_nlllO0i3160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0l00l858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0l00O860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0l0ii862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0l0il864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0O0ll856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0O0OO843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0Oiil755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_n0Ol0O974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1i0i1702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1i0l1701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1i0O967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1llO1649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1O0i1643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1O0l1642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1O1l1647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_ni1O1O1645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlli0Oi2550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlli0Ol2562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlll10l3175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlll10O3173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlll1ii3171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlll1il3169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlll1iO3168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlll1li2467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nllllli2298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlllO0i2306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlllO1i2300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlllO1l2302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlllO1O2304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlO011i3148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlO10Oi2285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlO1Oii2349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlO1OOO3149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_nllllii47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nllllii47w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlO00ll2362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlO00lO2363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_nlO00Oi2364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni00Ol : STD_LOGIC := '0'; + SIGNAL ni0liO : STD_LOGIC := '0'; + SIGNAL ni0lli : STD_LOGIC := '0'; + SIGNAL ni0lll : STD_LOGIC := '0'; + SIGNAL ni0llO : STD_LOGIC := '0'; + SIGNAL ni0lOi : STD_LOGIC := '0'; + SIGNAL ni0lOl : STD_LOGIC := '0'; + SIGNAL ni0lOO : STD_LOGIC := '0'; + SIGNAL ni0O0i : STD_LOGIC := '0'; + SIGNAL ni0O0l : STD_LOGIC := '0'; + SIGNAL ni0O0O : STD_LOGIC := '0'; + SIGNAL ni0O1i : STD_LOGIC := '0'; + SIGNAL ni0O1l : STD_LOGIC := '0'; + SIGNAL ni0O1O : STD_LOGIC := '0'; + SIGNAL ni0Oii : STD_LOGIC := '0'; + SIGNAL ni0Oil : STD_LOGIC := '0'; + SIGNAL ni0OiO : STD_LOGIC := '0'; + SIGNAL ni0Oli : STD_LOGIC := '0'; + SIGNAL ni0Oll : STD_LOGIC := '0'; + SIGNAL ni0OlO : STD_LOGIC := '0'; + SIGNAL nii0li : STD_LOGIC := '0'; + SIGNAL nii0Oi : STD_LOGIC := '0'; + SIGNAL wire_nii0lO_CLRN : STD_LOGIC; + SIGNAL wire_nii0lO_w_lg_nii0Oi640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0Oi1i : STD_LOGIC := '0'; + SIGNAL n0Oi1l : STD_LOGIC := '0'; + SIGNAL niiOlO : STD_LOGIC := '0'; + SIGNAL niiOOi : STD_LOGIC := '0'; + SIGNAL niiOOO : STD_LOGIC := '0'; + SIGNAL nlli10i : STD_LOGIC := '0'; + SIGNAL nlli10l : STD_LOGIC := '0'; + SIGNAL nlli10O : STD_LOGIC := '0'; + SIGNAL nlO10Ol : STD_LOGIC := '0'; + SIGNAL nlO10OO : STD_LOGIC := '0'; + SIGNAL wire_niiOOl_CLRN : STD_LOGIC; + SIGNAL wire_niiOOl_PRN : STD_LOGIC; + SIGNAL nl0l : STD_LOGIC := '0'; + SIGNAL nO : STD_LOGIC := '0'; + SIGNAL wire_nl_CLRN : STD_LOGIC; + SIGNAL n100iO : STD_LOGIC := '0'; + SIGNAL n10iOi : STD_LOGIC := '0'; + SIGNAL niOOiO : STD_LOGIC := '0'; + SIGNAL nl11Ol : STD_LOGIC := '0'; + SIGNAL n0l00i : STD_LOGIC := '0'; + SIGNAL n0l01l : STD_LOGIC := '0'; + SIGNAL n0l01O : STD_LOGIC := '0'; + SIGNAL n1O00O : STD_LOGIC := '0'; + SIGNAL n1O0ii : STD_LOGIC := '0'; + SIGNAL nli01l : STD_LOGIC := '0'; + SIGNAL nli1OO : STD_LOGIC := '0'; + SIGNAL nlli11i : STD_LOGIC := '0'; + SIGNAL nlli11l : STD_LOGIC := '0'; + SIGNAL nlli11O : STD_LOGIC := '0'; + SIGNAL wire_nli01i_PRN : STD_LOGIC; + SIGNAL nl0O : STD_LOGIC := '0'; + SIGNAL nlli : STD_LOGIC := '0'; + SIGNAL nlOiOil : STD_LOGIC := '0'; + SIGNAL nlOiOli : STD_LOGIC := '0'; + SIGNAL nlOiOll : STD_LOGIC := '0'; + SIGNAL nlOiOlO : STD_LOGIC := '0'; + SIGNAL nlOiOOi : STD_LOGIC := '0'; + SIGNAL nlOiOOl : STD_LOGIC := '0'; + SIGNAL nlOiOOO : STD_LOGIC := '0'; + SIGNAL nlOl00i : STD_LOGIC := '0'; + SIGNAL nlOl00l : STD_LOGIC := '0'; + SIGNAL nlOl00O : STD_LOGIC := '0'; + SIGNAL nlOl01i : STD_LOGIC := '0'; + SIGNAL nlOl01l : STD_LOGIC := '0'; + SIGNAL nlOl01O : STD_LOGIC := '0'; + SIGNAL nlOl0ii : STD_LOGIC := '0'; + SIGNAL nlOl0il : STD_LOGIC := '0'; + SIGNAL nlOl0iO : STD_LOGIC := '0'; + SIGNAL nlOl0li : STD_LOGIC := '0'; + SIGNAL nlOl0ll : STD_LOGIC := '0'; + SIGNAL nlOl0lO : STD_LOGIC := '0'; + SIGNAL nlOl0Oi : STD_LOGIC := '0'; + SIGNAL nlOl0Ol : STD_LOGIC := '0'; + SIGNAL nlOl10i : STD_LOGIC := '0'; + SIGNAL nlOl10l : STD_LOGIC := '0'; + SIGNAL nlOl10O : STD_LOGIC := '0'; + SIGNAL nlOl11i : STD_LOGIC := '0'; + SIGNAL nlOl11l : STD_LOGIC := '0'; + SIGNAL nlOl11O : STD_LOGIC := '0'; + SIGNAL nlOl1ii : STD_LOGIC := '0'; + SIGNAL nlOl1il : STD_LOGIC := '0'; + SIGNAL nlOl1iO : STD_LOGIC := '0'; + SIGNAL nlOl1li : STD_LOGIC := '0'; + SIGNAL nlOl1ll : STD_LOGIC := '0'; + SIGNAL nlOl1lO : STD_LOGIC := '0'; + SIGNAL nlOl1Oi : STD_LOGIC := '0'; + SIGNAL nlOl1Ol : STD_LOGIC := '0'; + SIGNAL nlOl1OO : STD_LOGIC := '0'; + SIGNAL nlOlill : STD_LOGIC := '0'; + SIGNAL nlOliOl : STD_LOGIC := '0'; + SIGNAL wire_nlOliOi_PRN : STD_LOGIC; + SIGNAL wire_nlOliOi_w_lg_nlOliOl2141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n0110i_dataout : STD_LOGIC; + SIGNAL wire_n0110l_dataout : STD_LOGIC; + SIGNAL wire_n0110O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0liOO_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i_dataout : STD_LOGIC; + SIGNAL wire_n0ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0ll1i_dataout : STD_LOGIC; + SIGNAL wire_n0ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0llii_dataout : STD_LOGIC; + SIGNAL wire_n0llil_dataout : STD_LOGIC; + SIGNAL wire_n0lliO_dataout : STD_LOGIC; + SIGNAL wire_n0llli_dataout : STD_LOGIC; + SIGNAL wire_n0llll_dataout : STD_LOGIC; + SIGNAL wire_n0lllO_dataout : STD_LOGIC; + SIGNAL wire_n0llOi_dataout : STD_LOGIC; + SIGNAL wire_n0llOl_dataout : STD_LOGIC; + SIGNAL wire_n0llOO_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOii_dataout : STD_LOGIC; + SIGNAL wire_n0lOil_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOli_dataout : STD_LOGIC; + SIGNAL wire_n0lOll_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O00i_dataout : STD_LOGIC; + SIGNAL wire_n0O00l_dataout : STD_LOGIC; + SIGNAL wire_n0O00O_dataout : STD_LOGIC; + SIGNAL wire_n0O01i_dataout : STD_LOGIC; + SIGNAL wire_n0O01l_dataout : STD_LOGIC; + SIGNAL wire_n0O01O_dataout : STD_LOGIC; + SIGNAL wire_n0O0ii_dataout : STD_LOGIC; + SIGNAL wire_n0O0il_dataout : STD_LOGIC; + SIGNAL wire_n0O0iO_dataout : STD_LOGIC; + SIGNAL wire_n0O10i_dataout : STD_LOGIC; + SIGNAL wire_n0O10l_dataout : STD_LOGIC; + SIGNAL wire_n0O10O_dataout : STD_LOGIC; + SIGNAL wire_n0O11i_dataout : STD_LOGIC; + SIGNAL wire_n0O11l_dataout : STD_LOGIC; + SIGNAL wire_n0O11O_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii_dataout : STD_LOGIC; + SIGNAL wire_n0O1il_dataout : STD_LOGIC; + SIGNAL wire_n0O1iO_dataout : STD_LOGIC; + SIGNAL wire_n0O1li_dataout : STD_LOGIC; + SIGNAL wire_n0O1ll_dataout : STD_LOGIC; + SIGNAL wire_n0O1lO_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oiii_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oili_dataout : STD_LOGIC; + SIGNAL wire_n0Oill_dataout : STD_LOGIC; + SIGNAL wire_n0OilO_dataout : STD_LOGIC; + SIGNAL wire_n0OiOi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Olii_dataout : STD_LOGIC; + SIGNAL wire_n0Olil_dataout : STD_LOGIC; + SIGNAL wire_n0OliO_dataout : STD_LOGIC; + SIGNAL wire_n0Olli_dataout : STD_LOGIC; + SIGNAL wire_n0Olll_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOii_dataout : STD_LOGIC; + SIGNAL wire_n1011i_dataout : STD_LOGIC; + SIGNAL wire_n1011l_dataout : STD_LOGIC; + SIGNAL wire_n1011O_dataout : STD_LOGIC; + SIGNAL wire_n101iO_dataout : STD_LOGIC; + SIGNAL wire_n101li_dataout : STD_LOGIC; + SIGNAL wire_n101ll_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n10O0i_dataout : STD_LOGIC; + SIGNAL wire_n10O0l_dataout : STD_LOGIC; + SIGNAL wire_n10O0O_dataout : STD_LOGIC; + SIGNAL wire_n10Oii_dataout : STD_LOGIC; + SIGNAL wire_n10Oil_dataout : STD_LOGIC; + SIGNAL wire_n10OiO_dataout : STD_LOGIC; + SIGNAL wire_n10Oli_dataout : STD_LOGIC; + SIGNAL wire_n10Oll_dataout : STD_LOGIC; + SIGNAL wire_n10OlO_dataout : STD_LOGIC; + SIGNAL wire_n10OOi_dataout : STD_LOGIC; + SIGNAL wire_n10OOl_dataout : STD_LOGIC; + SIGNAL wire_n10OOO_dataout : STD_LOGIC; + SIGNAL wire_n1100i_dataout : STD_LOGIC; + SIGNAL wire_n1100l_dataout : STD_LOGIC; + SIGNAL wire_n1100O_dataout : STD_LOGIC; + SIGNAL wire_n1101i_dataout : STD_LOGIC; + SIGNAL wire_n110Oi_dataout : STD_LOGIC; + SIGNAL wire_n110Ol_dataout : STD_LOGIC; + SIGNAL wire_n1110i_dataout : STD_LOGIC; + SIGNAL wire_n1110l_dataout : STD_LOGIC; + SIGNAL wire_n1110O_dataout : STD_LOGIC; + SIGNAL wire_n1111i_dataout : STD_LOGIC; + SIGNAL wire_n1111l_dataout : STD_LOGIC; + SIGNAL wire_n1111O_dataout : STD_LOGIC; + SIGNAL wire_n111ii_dataout : STD_LOGIC; + SIGNAL wire_n111il_dataout : STD_LOGIC; + SIGNAL wire_n111iO_dataout : STD_LOGIC; + SIGNAL wire_n111li_dataout : STD_LOGIC; + SIGNAL wire_n111ll_dataout : STD_LOGIC; + SIGNAL wire_n111lO_dataout : STD_LOGIC; + SIGNAL wire_n111Oi_dataout : STD_LOGIC; + SIGNAL wire_n111Ol_dataout : STD_LOGIC; + SIGNAL wire_n111OO_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11l0i_dataout : STD_LOGIC; + SIGNAL wire_n11l0l_dataout : STD_LOGIC; + SIGNAL wire_n11l0O_dataout : STD_LOGIC; + SIGNAL wire_n11l1i_dataout : STD_LOGIC; + SIGNAL wire_n11l1l_dataout : STD_LOGIC; + SIGNAL wire_n11l1O_dataout : STD_LOGIC; + SIGNAL wire_n11lii_dataout : STD_LOGIC; + SIGNAL wire_n11lil_dataout : STD_LOGIC; + SIGNAL wire_n11liO_dataout : STD_LOGIC; + SIGNAL wire_n11lli_dataout : STD_LOGIC; + SIGNAL wire_n11lll_dataout : STD_LOGIC; + SIGNAL wire_n11llO_dataout : STD_LOGIC; + SIGNAL wire_n11lOi_dataout : STD_LOGIC; + SIGNAL wire_n11lOl_dataout : STD_LOGIC; + SIGNAL wire_n11lOO_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n11Oii_dataout : STD_LOGIC; + SIGNAL wire_n11Oil_dataout : STD_LOGIC; + SIGNAL wire_n11OiO_dataout : STD_LOGIC; + SIGNAL wire_n11Oli_dataout : STD_LOGIC; + SIGNAL wire_n11Oll_dataout : STD_LOGIC; + SIGNAL wire_n11OlO_dataout : STD_LOGIC; + SIGNAL wire_n11OOi_dataout : STD_LOGIC; + SIGNAL wire_n11OOl_dataout : STD_LOGIC; + SIGNAL wire_n11OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i00i_dataout : STD_LOGIC; + SIGNAL wire_n1i00l_dataout : STD_LOGIC; + SIGNAL wire_n1i00O_dataout : STD_LOGIC; + SIGNAL wire_n1i01i_dataout : STD_LOGIC; + SIGNAL wire_n1i01l_dataout : STD_LOGIC; + SIGNAL wire_n1i01O_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii_dataout : STD_LOGIC; + SIGNAL wire_n1i0il_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO_dataout : STD_LOGIC; + SIGNAL wire_n1i0li_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO_dataout : STD_LOGIC; + SIGNAL wire_n1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i10i_dataout : STD_LOGIC; + SIGNAL wire_n1i10l_dataout : STD_LOGIC; + SIGNAL wire_n1i10O_dataout : STD_LOGIC; + SIGNAL wire_n1i11i_dataout : STD_LOGIC; + SIGNAL wire_n1i11l_dataout : STD_LOGIC; + SIGNAL wire_n1i11O_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1il_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1li_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1ii1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O_dataout : STD_LOGIC; + SIGNAL wire_n1iiii_dataout : STD_LOGIC; + SIGNAL wire_n1iiil_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iili_dataout : STD_LOGIC; + SIGNAL wire_n1iill_dataout : STD_LOGIC; + SIGNAL wire_n1iilO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1il0i_dataout : STD_LOGIC; + SIGNAL wire_n1il0l_dataout : STD_LOGIC; + SIGNAL wire_n1il0O_dataout : STD_LOGIC; + SIGNAL wire_n1il1i_dataout : STD_LOGIC; + SIGNAL wire_n1il1l_dataout : STD_LOGIC; + SIGNAL wire_n1il1O_dataout : STD_LOGIC; + SIGNAL wire_n1ilii_dataout : STD_LOGIC; + SIGNAL wire_n1ilil_dataout : STD_LOGIC; + SIGNAL wire_n1iliO_dataout : STD_LOGIC; + SIGNAL wire_n1illi_dataout : STD_LOGIC; + SIGNAL wire_n1illl_dataout : STD_LOGIC; + SIGNAL wire_n1illO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOii_dataout : STD_LOGIC; + SIGNAL wire_n1iOil_dataout : STD_LOGIC; + SIGNAL wire_n1iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOli_dataout : STD_LOGIC; + SIGNAL wire_n1iOll_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n1l0il_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n1l0li_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l10i_dataout : STD_LOGIC; + SIGNAL wire_n1l10l_dataout : STD_LOGIC; + SIGNAL wire_n1l10O_dataout : STD_LOGIC; + SIGNAL wire_n1l11i_dataout : STD_LOGIC; + SIGNAL wire_n1l11l_dataout : STD_LOGIC; + SIGNAL wire_n1l11O_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1l1il_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l1li_dataout : STD_LOGIC; + SIGNAL wire_n1l1ll_dataout : STD_LOGIC; + SIGNAL wire_n1l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1li0i_dataout : STD_LOGIC; + SIGNAL wire_n1li1O_dataout : STD_LOGIC; + SIGNAL wire_n1lill_dataout : STD_LOGIC; + SIGNAL wire_n1lilO_dataout : STD_LOGIC; + SIGNAL wire_n1liOi_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O0il_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO_dataout : STD_LOGIC; + SIGNAL wire_n1O0li_dataout : STD_LOGIC; + SIGNAL wire_n1O0ll_dataout : STD_LOGIC; + SIGNAL wire_n1O0lO_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll_w_lg_dataout1965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O1lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1O_w_lg_dataout2153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oiil_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil_w_lg_dataout1966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oiil_w_lg_dataout2154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oiil_w_lg_dataout1941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1OiOO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n1Olii_dataout : STD_LOGIC; + SIGNAL wire_n1Olli_dataout : STD_LOGIC; + SIGNAL wire_n1Olli_w_lg_dataout2358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Olll_dataout : STD_LOGIC; + SIGNAL wire_n1Olll_w_lg_dataout2359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OlOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOii_dataout : STD_LOGIC; + SIGNAL wire_n1OOil_dataout : STD_LOGIC; + SIGNAL wire_ni_dataout : STD_LOGIC; + SIGNAL wire_ni000O_dataout : STD_LOGIC; + SIGNAL wire_ni00ii_dataout : STD_LOGIC; + SIGNAL wire_ni00li_dataout : STD_LOGIC; + SIGNAL wire_ni00ll_dataout : STD_LOGIC; + SIGNAL wire_ni00OO_dataout : STD_LOGIC; + SIGNAL wire_ni010i_dataout : STD_LOGIC; + SIGNAL wire_ni010l_dataout : STD_LOGIC; + SIGNAL wire_ni010O_dataout : STD_LOGIC; + SIGNAL wire_ni011i_dataout : STD_LOGIC; + SIGNAL wire_ni011l_dataout : STD_LOGIC; + SIGNAL wire_ni011O_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO_dataout : STD_LOGIC; + SIGNAL wire_ni0ili_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni100i_dataout : STD_LOGIC; + SIGNAL wire_ni100l_dataout : STD_LOGIC; + SIGNAL wire_ni100O_dataout : STD_LOGIC; + SIGNAL wire_ni101O_dataout : STD_LOGIC; + SIGNAL wire_ni10ii_dataout : STD_LOGIC; + SIGNAL wire_ni10il_dataout : STD_LOGIC; + SIGNAL wire_ni10iO_dataout : STD_LOGIC; + SIGNAL wire_ni10lO_dataout : STD_LOGIC; + SIGNAL wire_ni110O_dataout : STD_LOGIC; + SIGNAL wire_ni11ii_dataout : STD_LOGIC; + SIGNAL wire_ni11il_dataout : STD_LOGIC; + SIGNAL wire_ni11iO_dataout : STD_LOGIC; + SIGNAL wire_ni11li_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1iii_dataout : STD_LOGIC; + SIGNAL wire_ni1iil_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO_dataout : STD_LOGIC; + SIGNAL wire_ni1ili_dataout : STD_LOGIC; + SIGNAL wire_ni1ill_dataout : STD_LOGIC; + SIGNAL wire_ni1ilO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iOO_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l1O_dataout : STD_LOGIC; + SIGNAL wire_ni1lOi_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii_dataout : STD_LOGIC; + SIGNAL wire_ni1Oil_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli_dataout : STD_LOGIC; + SIGNAL wire_ni1Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO_dataout : STD_LOGIC; + SIGNAL wire_ni1OOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niii0i_dataout : STD_LOGIC; + SIGNAL wire_niii0l_dataout : STD_LOGIC; + SIGNAL wire_niii0O_dataout : STD_LOGIC; + SIGNAL wire_niii1l_dataout : STD_LOGIC; + SIGNAL wire_niii1O_dataout : STD_LOGIC; + SIGNAL wire_niiiii_dataout : STD_LOGIC; + SIGNAL wire_niiiil_dataout : STD_LOGIC; + SIGNAL wire_niiiiO_dataout : STD_LOGIC; + SIGNAL wire_niiili_dataout : STD_LOGIC; + SIGNAL wire_niiill_dataout : STD_LOGIC; + SIGNAL wire_niiilO_dataout : STD_LOGIC; + SIGNAL wire_niiiOi_dataout : STD_LOGIC; + SIGNAL wire_niiiOl_dataout : STD_LOGIC; + SIGNAL wire_niiiOO_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niil0i_dataout : STD_LOGIC; + SIGNAL wire_niil0l_dataout : STD_LOGIC; + SIGNAL wire_niil0O_dataout : STD_LOGIC; + SIGNAL wire_niil1i_dataout : STD_LOGIC; + SIGNAL wire_niil1l_dataout : STD_LOGIC; + SIGNAL wire_niil1O_dataout : STD_LOGIC; + SIGNAL wire_niilii_dataout : STD_LOGIC; + SIGNAL wire_niilil_dataout : STD_LOGIC; + SIGNAL wire_niiliO_dataout : STD_LOGIC; + SIGNAL wire_niilli_dataout : STD_LOGIC; + SIGNAL wire_niilll_dataout : STD_LOGIC; + SIGNAL wire_niillO_dataout : STD_LOGIC; + SIGNAL wire_niilOi_dataout : STD_LOGIC; + SIGNAL wire_niilOl_dataout : STD_LOGIC; + SIGNAL wire_niilOO_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_niiO0i_dataout : STD_LOGIC; + SIGNAL wire_niiO0l_dataout : STD_LOGIC; + SIGNAL wire_niiO0O_dataout : STD_LOGIC; + SIGNAL wire_niiO1i_dataout : STD_LOGIC; + SIGNAL wire_niiO1l_dataout : STD_LOGIC; + SIGNAL wire_niiO1O_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOii_dataout : STD_LOGIC; + SIGNAL wire_niiOil_dataout : STD_LOGIC; + SIGNAL wire_niiOiO_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOli_dataout : STD_LOGIC; + SIGNAL wire_niiOll_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil00i_dataout : STD_LOGIC; + SIGNAL wire_nil00l_dataout : STD_LOGIC; + SIGNAL wire_nil00O_dataout : STD_LOGIC; + SIGNAL wire_nil01i_dataout : STD_LOGIC; + SIGNAL wire_nil01l_dataout : STD_LOGIC; + SIGNAL wire_nil01O_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0ii_dataout : STD_LOGIC; + SIGNAL wire_nil0il_dataout : STD_LOGIC; + SIGNAL wire_nil0iO_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0li_dataout : STD_LOGIC; + SIGNAL wire_nil0ll_dataout : STD_LOGIC; + SIGNAL wire_nil0lO_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0OO_dataout : STD_LOGIC; + SIGNAL wire_nil10i_dataout : STD_LOGIC; + SIGNAL wire_nil10l_dataout : STD_LOGIC; + SIGNAL wire_nil10O_dataout : STD_LOGIC; + SIGNAL wire_nil11i_dataout : STD_LOGIC; + SIGNAL wire_nil11l_dataout : STD_LOGIC; + SIGNAL wire_nil11O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1ii_dataout : STD_LOGIC; + SIGNAL wire_nil1il_dataout : STD_LOGIC; + SIGNAL wire_nil1iO_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1li_dataout : STD_LOGIC; + SIGNAL wire_nil1ll_dataout : STD_LOGIC; + SIGNAL wire_nil1lO_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1OO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nili0i_dataout : STD_LOGIC; + SIGNAL wire_nili0l_dataout : STD_LOGIC; + SIGNAL wire_nili0O_dataout : STD_LOGIC; + SIGNAL wire_nili1i_dataout : STD_LOGIC; + SIGNAL wire_nili1l_dataout : STD_LOGIC; + SIGNAL wire_nili1O_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_niliii_dataout : STD_LOGIC; + SIGNAL wire_niliil_dataout : STD_LOGIC; + SIGNAL wire_niliiO_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_nilili_dataout : STD_LOGIC; + SIGNAL wire_nilill_dataout : STD_LOGIC; + SIGNAL wire_nililO_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_niliOi_dataout : STD_LOGIC; + SIGNAL wire_niliOl_dataout : STD_LOGIC; + SIGNAL wire_niliOO_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nill0i_dataout : STD_LOGIC; + SIGNAL wire_nill0l_dataout : STD_LOGIC; + SIGNAL wire_nill0O_dataout : STD_LOGIC; + SIGNAL wire_nill1i_dataout : STD_LOGIC; + SIGNAL wire_nill1l_dataout : STD_LOGIC; + SIGNAL wire_nill1O_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nillii_dataout : STD_LOGIC; + SIGNAL wire_nillil_dataout : STD_LOGIC; + SIGNAL wire_nilliO_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nillli_dataout : STD_LOGIC; + SIGNAL wire_nillll_dataout : STD_LOGIC; + SIGNAL wire_nilllO_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nillOi_dataout : STD_LOGIC; + SIGNAL wire_nillOl_dataout : STD_LOGIC; + SIGNAL wire_nillOO_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_nilO0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOii_dataout : STD_LOGIC; + SIGNAL wire_nilOil_dataout : STD_LOGIC; + SIGNAL wire_nilOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOli_dataout : STD_LOGIC; + SIGNAL wire_nilOll_dataout : STD_LOGIC; + SIGNAL wire_nilOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO00i_dataout : STD_LOGIC; + SIGNAL wire_niO00l_dataout : STD_LOGIC; + SIGNAL wire_niO00O_dataout : STD_LOGIC; + SIGNAL wire_niO01i_dataout : STD_LOGIC; + SIGNAL wire_niO01l_dataout : STD_LOGIC; + SIGNAL wire_niO01O_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0ii_dataout : STD_LOGIC; + SIGNAL wire_niO0il_dataout : STD_LOGIC; + SIGNAL wire_niO0iO_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0li_dataout : STD_LOGIC; + SIGNAL wire_niO0ll_dataout : STD_LOGIC; + SIGNAL wire_niO0lO_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0OO_dataout : STD_LOGIC; + SIGNAL wire_niO10i_dataout : STD_LOGIC; + SIGNAL wire_niO10l_dataout : STD_LOGIC; + SIGNAL wire_niO10O_dataout : STD_LOGIC; + SIGNAL wire_niO11i_dataout : STD_LOGIC; + SIGNAL wire_niO11l_dataout : STD_LOGIC; + SIGNAL wire_niO11O_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1ii_dataout : STD_LOGIC; + SIGNAL wire_niO1il_dataout : STD_LOGIC; + SIGNAL wire_niO1iO_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1li_dataout : STD_LOGIC; + SIGNAL wire_niO1ll_dataout : STD_LOGIC; + SIGNAL wire_niO1lO_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOiii_dataout : STD_LOGIC; + SIGNAL wire_niOiil_dataout : STD_LOGIC; + SIGNAL wire_niOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOili_dataout : STD_LOGIC; + SIGNAL wire_niOill_dataout : STD_LOGIC; + SIGNAL wire_niOilO_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOlii_dataout : STD_LOGIC; + SIGNAL wire_niOlil_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOllO_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_nl000i_dataout : STD_LOGIC; + SIGNAL wire_nl000l_dataout : STD_LOGIC; + SIGNAL wire_nl000O_dataout : STD_LOGIC; + SIGNAL wire_nl001i_dataout : STD_LOGIC; + SIGNAL wire_nl001l_dataout : STD_LOGIC; + SIGNAL wire_nl001O_dataout : STD_LOGIC; + SIGNAL wire_nl00i_dataout : STD_LOGIC; + SIGNAL wire_nl00ii_dataout : STD_LOGIC; + SIGNAL wire_nl00il_dataout : STD_LOGIC; + SIGNAL wire_nl00iO_dataout : STD_LOGIC; + SIGNAL wire_nl00l_dataout : STD_LOGIC; + SIGNAL wire_nl00li_dataout : STD_LOGIC; + SIGNAL wire_nl00ll_dataout : STD_LOGIC; + SIGNAL wire_nl00lO_dataout : STD_LOGIC; + SIGNAL wire_nl00O_dataout : STD_LOGIC; + SIGNAL wire_nl00O_w_lg_dataout123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00OO_dataout : STD_LOGIC; + SIGNAL wire_nl010i_dataout : STD_LOGIC; + SIGNAL wire_nl010l_dataout : STD_LOGIC; + SIGNAL wire_nl010O_dataout : STD_LOGIC; + SIGNAL wire_nl011i_dataout : STD_LOGIC; + SIGNAL wire_nl011l_dataout : STD_LOGIC; + SIGNAL wire_nl011O_dataout : STD_LOGIC; + SIGNAL wire_nl01i_dataout : STD_LOGIC; + SIGNAL wire_nl01ii_dataout : STD_LOGIC; + SIGNAL wire_nl01il_dataout : STD_LOGIC; + SIGNAL wire_nl01iO_dataout : STD_LOGIC; + SIGNAL wire_nl01l_dataout : STD_LOGIC; + SIGNAL wire_nl01li_dataout : STD_LOGIC; + SIGNAL wire_nl01ll_dataout : STD_LOGIC; + SIGNAL wire_nl01lO_dataout : STD_LOGIC; + SIGNAL wire_nl01O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i_w_lg_dataout4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii_w_lg_w_lg_dataout138w141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ii_w_lg_dataout138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl10l_dataout : STD_LOGIC; + SIGNAL wire_nl10O_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli00i_dataout : STD_LOGIC; + SIGNAL wire_nli00l_dataout : STD_LOGIC; + SIGNAL wire_nli00O_dataout : STD_LOGIC; + SIGNAL wire_nli01O_dataout : STD_LOGIC; + SIGNAL wire_nli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nliii_dataout : STD_LOGIC; + SIGNAL wire_nliiii_dataout : STD_LOGIC; + SIGNAL wire_nliiil_dataout : STD_LOGIC; + SIGNAL wire_nliiiO_dataout : STD_LOGIC; + SIGNAL wire_nliil_dataout : STD_LOGIC; + SIGNAL wire_nliiO_dataout : STD_LOGIC; + SIGNAL wire_nliiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlili_dataout : STD_LOGIC; + SIGNAL wire_nlilii_dataout : STD_LOGIC; + SIGNAL wire_nlilil_dataout : STD_LOGIC; + SIGNAL wire_nlill_dataout : STD_LOGIC; + SIGNAL wire_nlilO_dataout : STD_LOGIC; + SIGNAL wire_nlilOO_dataout : STD_LOGIC; + SIGNAL wire_nliO00l_dataout : STD_LOGIC; + SIGNAL wire_nliO00O_dataout : STD_LOGIC; + SIGNAL wire_nliO0i_dataout : STD_LOGIC; + SIGNAL wire_nliO0ii_dataout : STD_LOGIC; + SIGNAL wire_nliO0l_dataout : STD_LOGIC; + SIGNAL wire_nliO0O_dataout : STD_LOGIC; + SIGNAL wire_nliO1O_dataout : STD_LOGIC; + SIGNAL wire_nliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOlO_dataout : STD_LOGIC; + SIGNAL wire_nliOlO_w_lg_dataout544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nliOOi_dataout : STD_LOGIC; + SIGNAL wire_nliOOi_w_lg_dataout733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOOi_w_lg_dataout924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOOO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nll00i_dataout : STD_LOGIC; + SIGNAL wire_nll00l_dataout : STD_LOGIC; + SIGNAL wire_nll00O_dataout : STD_LOGIC; + SIGNAL wire_nll01i_dataout : STD_LOGIC; + SIGNAL wire_nll01l_dataout : STD_LOGIC; + SIGNAL wire_nll01O_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0il_dataout : STD_LOGIC; + SIGNAL wire_nll0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0li_dataout : STD_LOGIC; + SIGNAL wire_nll0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0OO_dataout : STD_LOGIC; + SIGNAL wire_nll10i_dataout : STD_LOGIC; + SIGNAL wire_nll10l_dataout : STD_LOGIC; + SIGNAL wire_nll10O_dataout : STD_LOGIC; + SIGNAL wire_nll11i_dataout : STD_LOGIC; + SIGNAL wire_nll11l_dataout : STD_LOGIC; + SIGNAL wire_nll11O_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1il_dataout : STD_LOGIC; + SIGNAL wire_nll1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1li_dataout : STD_LOGIC; + SIGNAL wire_nll1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlli01i_dataout : STD_LOGIC; + SIGNAL wire_nlli0li_dataout : STD_LOGIC; + SIGNAL wire_nlli1i_dataout : STD_LOGIC; + SIGNAL wire_nlli1l_dataout : STD_LOGIC; + SIGNAL wire_nlli1lO_dataout : STD_LOGIC; + SIGNAL wire_nlli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli1OO_dataout : STD_LOGIC; + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nllii0i_dataout : STD_LOGIC; + SIGNAL wire_nlliili_dataout : STD_LOGIC; + SIGNAL wire_nlliill_dataout : STD_LOGIC; + SIGNAL wire_nlliilO_dataout : STD_LOGIC; + SIGNAL wire_nlliiOi_dataout : STD_LOGIC; + SIGNAL wire_nlliiOl_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nllil0O_dataout : STD_LOGIC; + SIGNAL wire_nllilii_dataout : STD_LOGIC; + SIGNAL wire_nllilil_dataout : STD_LOGIC; + SIGNAL wire_nlliliO_dataout : STD_LOGIC; + SIGNAL wire_nllilli_dataout : STD_LOGIC; + SIGNAL wire_nllilll_dataout : STD_LOGIC; + SIGNAL wire_nllillO_dataout : STD_LOGIC; + SIGNAL wire_nllilOO_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nlll00i_dataout : STD_LOGIC; + SIGNAL wire_nlll00l_dataout : STD_LOGIC; + SIGNAL wire_nlll00O_dataout : STD_LOGIC; + SIGNAL wire_nlll01i_dataout : STD_LOGIC; + SIGNAL wire_nlll01l_dataout : STD_LOGIC; + SIGNAL wire_nlll01O_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii_dataout : STD_LOGIC; + SIGNAL wire_nlll0il_dataout : STD_LOGIC; + SIGNAL wire_nlll0iO_dataout : STD_LOGIC; + SIGNAL wire_nlll0li_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll_dataout : STD_LOGIC; + SIGNAL wire_nlll0lO_dataout : STD_LOGIC; + SIGNAL wire_nlll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll0OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll1OO_dataout : STD_LOGIC; + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nllli0i_dataout : STD_LOGIC; + SIGNAL wire_nllli0l_dataout : STD_LOGIC; + SIGNAL wire_nllli0O_dataout : STD_LOGIC; + SIGNAL wire_nllli1i_dataout : STD_LOGIC; + SIGNAL wire_nllli1l_dataout : STD_LOGIC; + SIGNAL wire_nllli1O_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nllllll_dataout : STD_LOGIC; + SIGNAL wire_nlllllO_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllO00i_dataout : STD_LOGIC; + SIGNAL wire_nllO00l_dataout : STD_LOGIC; + SIGNAL wire_nllO00O_dataout : STD_LOGIC; + SIGNAL wire_nllO01i_dataout : STD_LOGIC; + SIGNAL wire_nllO01l_dataout : STD_LOGIC; + SIGNAL wire_nllO01O_dataout : STD_LOGIC; + SIGNAL wire_nllO0ii_dataout : STD_LOGIC; + SIGNAL wire_nllO0il_dataout : STD_LOGIC; + SIGNAL wire_nllO0iO_dataout : STD_LOGIC; + SIGNAL wire_nllO0li_dataout : STD_LOGIC; + SIGNAL wire_nllO0ll_dataout : STD_LOGIC; + SIGNAL wire_nllO0lO_dataout : STD_LOGIC; + SIGNAL wire_nllO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nllO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nllO0OO_dataout : STD_LOGIC; + SIGNAL wire_nllO1ll_dataout : STD_LOGIC; + SIGNAL wire_nllO1lO_dataout : STD_LOGIC; + SIGNAL wire_nllO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllO1OO_dataout : STD_LOGIC; + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOi0i_dataout : STD_LOGIC; + SIGNAL wire_nllOi0l_dataout : STD_LOGIC; + SIGNAL wire_nllOi0O_dataout : STD_LOGIC; + SIGNAL wire_nllOi1i_dataout : STD_LOGIC; + SIGNAL wire_nllOi1l_dataout : STD_LOGIC; + SIGNAL wire_nllOi1O_dataout : STD_LOGIC; + SIGNAL wire_nllOiii_dataout : STD_LOGIC; + SIGNAL wire_nllOiil_dataout : STD_LOGIC; + SIGNAL wire_nllOiiO_dataout : STD_LOGIC; + SIGNAL wire_nllOili_dataout : STD_LOGIC; + SIGNAL wire_nllOill_dataout : STD_LOGIC; + SIGNAL wire_nllOilO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOl0i_dataout : STD_LOGIC; + SIGNAL wire_nllOl0l_dataout : STD_LOGIC; + SIGNAL wire_nllOl0O_dataout : STD_LOGIC; + SIGNAL wire_nllOl1i_dataout : STD_LOGIC; + SIGNAL wire_nllOl1l_dataout : STD_LOGIC; + SIGNAL wire_nllOl1O_dataout : STD_LOGIC; + SIGNAL wire_nllOlii_dataout : STD_LOGIC; + SIGNAL wire_nllOlil_dataout : STD_LOGIC; + SIGNAL wire_nllOliO_dataout : STD_LOGIC; + SIGNAL wire_nllOlli_dataout : STD_LOGIC; + SIGNAL wire_nllOlll_dataout : STD_LOGIC; + SIGNAL wire_nllOllO_dataout : STD_LOGIC; + SIGNAL wire_nllOlOi_dataout : STD_LOGIC; + SIGNAL wire_nllOlOl_dataout : STD_LOGIC; + SIGNAL wire_nllOlOO_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nllOO0i_dataout : STD_LOGIC; + SIGNAL wire_nllOO0l_dataout : STD_LOGIC; + SIGNAL wire_nllOO0O_dataout : STD_LOGIC; + SIGNAL wire_nllOO1i_dataout : STD_LOGIC; + SIGNAL wire_nllOO1l_dataout : STD_LOGIC; + SIGNAL wire_nllOO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOOii_dataout : STD_LOGIC; + SIGNAL wire_nllOOil_dataout : STD_LOGIC; + SIGNAL wire_nllOOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOOli_dataout : STD_LOGIC; + SIGNAL wire_nllOOll_dataout : STD_LOGIC; + SIGNAL wire_nllOOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlO001i_dataout : STD_LOGIC; + SIGNAL wire_nlO001l_dataout : STD_LOGIC; + SIGNAL wire_nlO00il_dataout : STD_LOGIC; + SIGNAL wire_nlO010i_dataout : STD_LOGIC; + SIGNAL wire_nlO010l_dataout : STD_LOGIC; + SIGNAL wire_nlO010O_dataout : STD_LOGIC; + SIGNAL wire_nlO011O_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01il_dataout : STD_LOGIC; + SIGNAL wire_nlO01iO_dataout : STD_LOGIC; + SIGNAL wire_nlO01li_dataout : STD_LOGIC; + SIGNAL wire_nlO01ll_dataout : STD_LOGIC; + SIGNAL wire_nlO01lO_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO01OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil_w_lg_w_lg_dataout2543w2545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oil_w_lg_dataout2543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO_w_lg_w_lg_w_lg_dataout2542w2546w2547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0OiO_w_lg_w_lg_dataout2542w2546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0OiO_w_lg_dataout2542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oli_w_lg_w_lg_dataout2228w2229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oli_w_lg_w_lg_dataout2228w2234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oli_w_lg_dataout2228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlO_w_lg_dataout2227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO100i_dataout : STD_LOGIC; + SIGNAL wire_nlO100l_dataout : STD_LOGIC; + SIGNAL wire_nlO100O_dataout : STD_LOGIC; + SIGNAL wire_nlO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO10ii_dataout : STD_LOGIC; + SIGNAL wire_nlO10il_dataout : STD_LOGIC; + SIGNAL wire_nlO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO110i_dataout : STD_LOGIC; + SIGNAL wire_nlO110l_dataout : STD_LOGIC; + SIGNAL wire_nlO110O_dataout : STD_LOGIC; + SIGNAL wire_nlO111i_dataout : STD_LOGIC; + SIGNAL wire_nlO111l_dataout : STD_LOGIC; + SIGNAL wire_nlO111O_dataout : STD_LOGIC; + SIGNAL wire_nlO11ii_dataout : STD_LOGIC; + SIGNAL wire_nlO11il_dataout : STD_LOGIC; + SIGNAL wire_nlO11iO_dataout : STD_LOGIC; + SIGNAL wire_nlO11li_dataout : STD_LOGIC; + SIGNAL wire_nlO11ll_dataout : STD_LOGIC; + SIGNAL wire_nlO11lO_dataout : STD_LOGIC; + SIGNAL wire_nlO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO11OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1ili_dataout : STD_LOGIC; + SIGNAL wire_nlO1ill_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi00i_dataout : STD_LOGIC; + SIGNAL wire_nlOi00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi00O_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i_dataout : STD_LOGIC; + SIGNAL wire_nlOi01l_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0il_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi10i_dataout : STD_LOGIC; + SIGNAL wire_nlOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlOi10l_w_lg_dataout2553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi10O_dataout : STD_LOGIC; + SIGNAL wire_nlOi11i_dataout : STD_LOGIC; + SIGNAL wire_nlOi11i_w_lg_dataout1992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi11l_dataout : STD_LOGIC; + SIGNAL wire_nlOi11O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1il_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiili_dataout : STD_LOGIC; + SIGNAL wire_nlOiill_dataout : STD_LOGIC; + SIGNAL wire_nlOiilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i_dataout : STD_LOGIC; + SIGNAL wire_nlOil0l_dataout : STD_LOGIC; + SIGNAL wire_nlOil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOil1O_dataout : STD_LOGIC; + SIGNAL wire_nlOilii_dataout : STD_LOGIC; + SIGNAL wire_nlOilil_dataout : STD_LOGIC; + SIGNAL wire_nlOiliO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOllii_dataout : STD_LOGIC; + SIGNAL wire_nlOllil_dataout : STD_LOGIC; + SIGNAL wire_nlOlliO_dataout : STD_LOGIC; + SIGNAL wire_nlOllli_dataout : STD_LOGIC; + SIGNAL wire_nlOllll_dataout : STD_LOGIC; + SIGNAL wire_nlOlllO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOi_dataout : STD_LOGIC; + SIGNAL wire_nlOllOl_dataout : STD_LOGIC; + SIGNAL wire_nlOllOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOili_dataout : STD_LOGIC; + SIGNAL wire_nlOOill_dataout : STD_LOGIC; + SIGNAL wire_nlOOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0li_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0O0li_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n0O0li_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0OOOO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0OOOO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0OOOO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1010i_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1010i_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1010i_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l0lO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1l0lO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1l0lO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O1OO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1O1OO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1O1OO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni01ii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni01ii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni01ii_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni01il_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni01il_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni01il_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1lii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1lii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1lii_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1lil_w_lg_w_o_range869w870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_lg_w_o_range872w873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_lg_w_o_range875w876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_lg_w_o_range878w879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_lg_w_o_range881w882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1lil_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1lil_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1lil_w_o_range869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_o_range872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_o_range875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_o_range878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lil_w_o_range881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1liO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1liO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_ni1liO_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl0OOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0OOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0OOi_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli1iO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli1iO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nli1iO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nllliii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nllliii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nllliii_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nllliil_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllliil_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllliil_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllliOl_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllliOl_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllliOl_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll1i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllll1i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllll1i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO000i_w_lg_w_o_range2311w2312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_lg_w_o_range2314w2315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_lg_w_o_range2317w2318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_lg_w_o_range2320w2321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_lg_w_o_range2323w2324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO000i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO000i_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO000i_w_o_range2311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_o_range2314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_o_range2317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_o_range2320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000i_w_o_range2323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO000l_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO000l_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO000l_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO001O_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO001O_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO001O_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO0lli_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlO0lli_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlO0lli_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlO101i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO101i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO101i_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlO10iO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO10iO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO10iO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011iO_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n011iO_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n011ll_i : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n011ll_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n011Oi_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011Oi_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n0OO1l_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0OO1l_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n1l00O_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1l00O_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n1l01l_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1l01l_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1l1OO_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1l1OO_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1OliO_i : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1OliO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0O1i_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0O1i_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl0O1O_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0O1O_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl0Oii_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0Oii_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliO01i_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliO01i_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliO1lO_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliO1lO_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nliO1Ol_i : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nliO1Ol_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli01O_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlli01O_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11iii_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11iii_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11iii_o : STD_LOGIC; + SIGNAL wire_n1O01i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O01i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_n1O01i_o : STD_LOGIC; + SIGNAL wire_n1O10l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1O10l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1O10l_o : STD_LOGIC; + SIGNAL wire_n1O11l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1O11l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1O11l_o : STD_LOGIC; + SIGNAL wire_n1OllO_w_lg_o2372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OllO_w_lg_o2549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OllO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OllO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OllO_o : STD_LOGIC; + SIGNAL wire_n1OlOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OlOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OlOi_o : STD_LOGIC; + SIGNAL wire_n1OOlO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OOlO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OOlO_o : STD_LOGIC; + SIGNAL wire_n1OOOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OOOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OOOi_o : STD_LOGIC; + SIGNAL wire_ni1i1i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1i1i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1i1i_o : STD_LOGIC; + SIGNAL wire_ni1lli_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1lli_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1lli_o : STD_LOGIC; + SIGNAL wire_nli1li_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli1li_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli1li_o : STD_LOGIC; + SIGNAL wire_nlilOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilOi_o : STD_LOGIC; + SIGNAL wire_nlli0iO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlli0iO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlli0iO_o : STD_LOGIC; + SIGNAL wire_nllOii_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOii_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOii_o : STD_LOGIC; + SIGNAL wire_nllOil_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOil_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOil_o : STD_LOGIC; + SIGNAL wire_nllOiO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOiO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOiO_o : STD_LOGIC; + SIGNAL wire_nllOli_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOli_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllOli_o : STD_LOGIC; + SIGNAL wire_nlO000O_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO000O_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO000O_o : STD_LOGIC; + SIGNAL wire_nllOOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOOO_o : STD_LOGIC; + SIGNAL wire_nllOOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO11i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO11i_o : STD_LOGIC; + SIGNAL wire_nlO11i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO11l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO11l_o : STD_LOGIC; + SIGNAL wire_nlO11l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO11O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO11O_o : STD_LOGIC; + SIGNAL wire_nlO11O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOll_data_in : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllOll_data_out1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllOll_data_out2 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllOll_fifo_re1 : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nllOll_fifo_re2 : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nllOll_fifo_wr : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nllOll_rst_l : STD_LOGIC; + SIGNAL wire_nllOlO_data_in : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllOlO_data_out1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllOlO_data_out2 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllOlO_fifo_re1 : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nllOlO_fifo_re2 : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nllOlO_fifo_wr : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nllOlO_rst_l : STD_LOGIC; + SIGNAL wire_w1977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rauto_speed_ena7w18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rclkcmpsqmd1968w1972w1973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rskpsetbased1947w1948w1949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rclkcmpsqmd1943w1944w1945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rclkcmpsqmd1943w1962w1963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rauto_speed_ena7w18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rclkcmpsqmd1968w1972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rskpsetbased1947w1948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlii1li1995w1996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliliil440w441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlillii120w2155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rclkcmpsqmd1943w1944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rclkcmpsqmd1943w1962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rgenericfifo32w2466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rgenericfifo32w754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rrx_pipe_enable1942w1946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rrx_pipe_enable1942w2369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rskpsetbased1868w1964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rskpsetbased1868w2360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rtruebac2bac1952w1970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rtruebac2bac1952w2367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_dskwclksel_range33w34w35w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rskpsetbased2366w2370w2371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_cg_comp_rd_d_ch01958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_cg_comp_rd_d_ch21959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_cg_comp_rd_d_ch31960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_cg_comp_wr_ch02353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_cg_comp_wr_ch22354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_cg_comp_wr_ch32355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0O1i2548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii0Oi1975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii0Ol1974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOii734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOli735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlillil2357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rauto_speed_ena7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rclkcmpsqmd1968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rgenericfifo756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rgenericfifo2468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rmatchen2152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rrx_pipe_enable2544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rskpsetbased1947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rskpsetbased2368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rskpsetbased2366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rtruebac2bac2365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_hard_reset25w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_is_lane01989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0iii2511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0l0i2530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0l0l2559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0l1O2426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0liO2283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0lli2281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0lll2279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0llO2277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0Oli2137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0OlO3187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii1li1995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii1Oi2149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliii0i2236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliil0O841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilii839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilil837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiliO835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilli968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilll798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilOO744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiO0O726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil00O1791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil0iO547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliliii460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliliil440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlill0O122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlillii120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilO0l1957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliO1il2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rclkcmpinsertpad655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rclkcmpsqmd1943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rfreq_sel6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rgenericfifo32w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rmatchen438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rrx_pipe_enable1942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rskpsetbased1868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rtruebac2bac1952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dskwclksel_range33w34w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w1977w1978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_rauto_speed_ena7w18w19w20w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rskpsetbased1868w2360w2361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_dskwclksel_range33w34w35w36w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlii0Ol1974w1976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rskpsetbased2366w2370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlilO0l1957w2352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nlilO0l1957w2352w2356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii1Oi1979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii1Ol1980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rtruebac2bac1971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli00ll : STD_LOGIC; + SIGNAL nli00lO : STD_LOGIC; + SIGNAL nli00Oi : STD_LOGIC; + SIGNAL nli00Ol : STD_LOGIC; + SIGNAL nli00OO : STD_LOGIC; + SIGNAL nli0i0i : STD_LOGIC; + SIGNAL nli0i0l : STD_LOGIC; + SIGNAL nli0i0O : STD_LOGIC; + SIGNAL nli0i1i : STD_LOGIC; + SIGNAL nli0i1l : STD_LOGIC; + SIGNAL nli0i1O : STD_LOGIC; + SIGNAL nli0iii : STD_LOGIC; + SIGNAL nli0iil : STD_LOGIC; + SIGNAL nli0iiO : STD_LOGIC; + SIGNAL nli0ili : STD_LOGIC; + SIGNAL nli0ill : STD_LOGIC; + SIGNAL nli0ilO : STD_LOGIC; + SIGNAL nli0iOi : STD_LOGIC; + SIGNAL nli0iOl : STD_LOGIC; + SIGNAL nli0iOO : STD_LOGIC; + SIGNAL nli0l0i : STD_LOGIC; + SIGNAL nli0l0l : STD_LOGIC; + SIGNAL nli0l0O : STD_LOGIC; + SIGNAL nli0l1i : STD_LOGIC; + SIGNAL nli0l1l : STD_LOGIC; + SIGNAL nli0l1O : STD_LOGIC; + SIGNAL nli0lii : STD_LOGIC; + SIGNAL nli0lil : STD_LOGIC; + SIGNAL nli0liO : STD_LOGIC; + SIGNAL nli0lli : STD_LOGIC; + SIGNAL nli0lll : STD_LOGIC; + SIGNAL nli0llO : STD_LOGIC; + SIGNAL nli0lOi : STD_LOGIC; + SIGNAL nli0lOl : STD_LOGIC; + SIGNAL nli0lOO : STD_LOGIC; + SIGNAL nli0O0i : STD_LOGIC; + SIGNAL nli0O0l : STD_LOGIC; + SIGNAL nli0O1i : STD_LOGIC; + SIGNAL nli0O1l : STD_LOGIC; + SIGNAL nli0O1O : STD_LOGIC; + SIGNAL nli0Oii : STD_LOGIC; + SIGNAL nli0Oil : STD_LOGIC; + SIGNAL nli0OiO : STD_LOGIC; + SIGNAL nli0Oli : STD_LOGIC; + SIGNAL nli0Oll : STD_LOGIC; + SIGNAL nli0OlO : STD_LOGIC; + SIGNAL nli0OOi : STD_LOGIC; + SIGNAL nli0OOl : STD_LOGIC; + SIGNAL nli0OOO : STD_LOGIC; + SIGNAL nlii00i : STD_LOGIC; + SIGNAL nlii00l : STD_LOGIC; + SIGNAL nlii00O : STD_LOGIC; + SIGNAL nlii01i : STD_LOGIC; + SIGNAL nlii01l : STD_LOGIC; + SIGNAL nlii01O : STD_LOGIC; + SIGNAL nlii0ii : STD_LOGIC; + SIGNAL nlii0il : STD_LOGIC; + SIGNAL nlii0iO : STD_LOGIC; + SIGNAL nlii0li : STD_LOGIC; + SIGNAL nlii0ll : STD_LOGIC; + SIGNAL nlii0lO : STD_LOGIC; + SIGNAL nlii0Oi : STD_LOGIC; + SIGNAL nlii0Ol : STD_LOGIC; + SIGNAL nlii0OO : STD_LOGIC; + SIGNAL nlii10i : STD_LOGIC; + SIGNAL nlii10l : STD_LOGIC; + SIGNAL nlii10O : STD_LOGIC; + SIGNAL nlii11i : STD_LOGIC; + SIGNAL nlii11l : STD_LOGIC; + SIGNAL nlii11O : STD_LOGIC; + SIGNAL nlii1ii : STD_LOGIC; + SIGNAL nlii1il : STD_LOGIC; + SIGNAL nlii1iO : STD_LOGIC; + SIGNAL nlii1li : STD_LOGIC; + SIGNAL nlii1ll : STD_LOGIC; + SIGNAL nlii1lO : STD_LOGIC; + SIGNAL nlii1Oi : STD_LOGIC; + SIGNAL nlii1Ol : STD_LOGIC; + SIGNAL nlii1OO : STD_LOGIC; + SIGNAL nliii0i : STD_LOGIC; + SIGNAL nliii0l : STD_LOGIC; + SIGNAL nliii0O : STD_LOGIC; + SIGNAL nliii1i : STD_LOGIC; + SIGNAL nliii1l : STD_LOGIC; + SIGNAL nliii1O : STD_LOGIC; + SIGNAL nliiiii : STD_LOGIC; + SIGNAL nliiiil : STD_LOGIC; + SIGNAL nliiiiO : STD_LOGIC; + SIGNAL nliiili : STD_LOGIC; + SIGNAL nliiill : STD_LOGIC; + SIGNAL nliiilO : STD_LOGIC; + SIGNAL nliiiOi : STD_LOGIC; + SIGNAL nliiiOl : STD_LOGIC; + SIGNAL nliiiOO : STD_LOGIC; + SIGNAL nliil0i : STD_LOGIC; + SIGNAL nliil0l : STD_LOGIC; + SIGNAL nliil0O : STD_LOGIC; + SIGNAL nliil1O : STD_LOGIC; + SIGNAL nliilii : STD_LOGIC; + SIGNAL nliilil : STD_LOGIC; + SIGNAL nliiliO : STD_LOGIC; + SIGNAL nliilli : STD_LOGIC; + SIGNAL nliilll : STD_LOGIC; + SIGNAL nliillO : STD_LOGIC; + SIGNAL nliilOi : STD_LOGIC; + SIGNAL nliilOl : STD_LOGIC; + SIGNAL nliilOO : STD_LOGIC; + SIGNAL nliiO0i : STD_LOGIC; + SIGNAL nliiO0l : STD_LOGIC; + SIGNAL nliiO0O : STD_LOGIC; + SIGNAL nliiO1i : STD_LOGIC; + SIGNAL nliiO1l : STD_LOGIC; + SIGNAL nliiO1O : STD_LOGIC; + SIGNAL nliiOii : STD_LOGIC; + SIGNAL nliiOil : STD_LOGIC; + SIGNAL nliiOiO : STD_LOGIC; + SIGNAL nliiOli : STD_LOGIC; + SIGNAL nliiOll : STD_LOGIC; + SIGNAL nliiOlO : STD_LOGIC; + SIGNAL nlil00i : STD_LOGIC; + SIGNAL nlil00l : STD_LOGIC; + SIGNAL nlil00O : STD_LOGIC; + SIGNAL nlil01i : STD_LOGIC; + SIGNAL nlil01O : STD_LOGIC; + SIGNAL nlil0ii : STD_LOGIC; + SIGNAL nlil0il : STD_LOGIC; + SIGNAL nlil0iO : STD_LOGIC; + SIGNAL nlil0lO : STD_LOGIC; + SIGNAL nlil0Oi : STD_LOGIC; + SIGNAL nlil10i : STD_LOGIC; + SIGNAL nlil10l : STD_LOGIC; + SIGNAL nlil10O : STD_LOGIC; + SIGNAL nlil11i : STD_LOGIC; + SIGNAL nlil11l : STD_LOGIC; + SIGNAL nlil11O : STD_LOGIC; + SIGNAL nlil1ii : STD_LOGIC; + SIGNAL nlil1il : STD_LOGIC; + SIGNAL nlil1iO : STD_LOGIC; + SIGNAL nlil1li : STD_LOGIC; + SIGNAL nlil1ll : STD_LOGIC; + SIGNAL nlil1lO : STD_LOGIC; + SIGNAL nlil1Oi : STD_LOGIC; + SIGNAL nlil1Ol : STD_LOGIC; + SIGNAL nlil1OO : STD_LOGIC; + SIGNAL nlili0i : STD_LOGIC; + SIGNAL nlili1i : STD_LOGIC; + SIGNAL nlili1l : STD_LOGIC; + SIGNAL nlili1O : STD_LOGIC; + SIGNAL nliliii : STD_LOGIC; + SIGNAL nliliil : STD_LOGIC; + SIGNAL nliliiO : STD_LOGIC; + SIGNAL nlilili : STD_LOGIC; + SIGNAL nlill0O : STD_LOGIC; + SIGNAL nlillii : STD_LOGIC; + SIGNAL nlillil : STD_LOGIC; + SIGNAL nlillOi : STD_LOGIC; + SIGNAL nlillOl : STD_LOGIC; + SIGNAL nlillOO : STD_LOGIC; + SIGNAL nlilO0l : STD_LOGIC; + SIGNAL nlilOil : STD_LOGIC; + SIGNAL nlilOiO : STD_LOGIC; + SIGNAL nliO10l : STD_LOGIC; + SIGNAL nliO11i : STD_LOGIC; + SIGNAL nliO1il : STD_LOGIC; + SIGNAL wire_w_dskwclksel_range33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rdel_threshold_range361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + COMPONENT cycloneiv_hssi_rx_digis_ram20x16_syn + GENERIC + ( + ram_width : NATURAL; + read_access_time : NATURAL; + write_access_time : NATURAL + ); + PORT + ( + clk : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + data_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fifo_re1 : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + fifo_re2 : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + fifo_wr : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + rst_l : IN STD_LOGIC + ); + END COMPONENT; + BEGIN + + wire_gnd <= '0'; + wire_vcc <= '1'; + wire_w1977w(0) <= wire_w_lg_w_lg_w_lg_rclkcmpsqmd1968w1972w1973w(0) AND wire_w_lg_w_lg_nlii0Ol1974w1976w(0); + wire_w_lg_w_lg_w_lg_rauto_speed_ena7w18w19w(0) <= wire_w_lg_w_lg_rauto_speed_ena7w18w(0) AND nlll; + wire_w_lg_w_lg_w_lg_rclkcmpsqmd1968w1972w1973w(0) <= wire_w_lg_w_lg_rclkcmpsqmd1968w1972w(0) AND n1liil; + wire_w_lg_w_lg_w_lg_rskpsetbased1947w1948w1949w(0) <= wire_w_lg_w_lg_rskpsetbased1947w1948w(0) AND wire_n1O10l_o; + wire_w_lg_w_lg_w_lg_rclkcmpsqmd1943w1944w1945w(0) <= wire_w_lg_w_lg_rclkcmpsqmd1943w1944w(0) AND nlii1OO; + wire_w_lg_w_lg_w_lg_rclkcmpsqmd1943w1962w1963w(0) <= wire_w_lg_w_lg_rclkcmpsqmd1943w1962w(0) AND nlii1OO; + wire_w_lg_w_lg_rauto_speed_ena7w18w(0) <= wire_w_lg_rauto_speed_ena7w(0) AND wire_nlilOlO12_w_lg_q17w(0); + wire_w_lg_w_lg_rclkcmpsqmd1968w1972w(0) <= wire_w_lg_rclkcmpsqmd1968w(0) AND wire_w_lg_rtruebac2bac1971w(0); + wire_w_lg_w_lg_rskpsetbased1947w1948w(0) <= wire_w_lg_rskpsetbased1947w(0) AND n1liil; + wire_w_lg_w_lg_nlii1li1995w1996w(0) <= wire_w_lg_nlii1li1995w(0) AND wire_n1li1O_dataout; + wire_w_lg_w_lg_nliliil440w441w(0) <= wire_w_lg_nliliil440w(0) AND nliliii; + wire_w_lg_w_lg_nlillii120w2155w(0) <= wire_w_lg_nlillii120w(0) AND wire_n1Oiil_w_lg_dataout2154w(0); + wire_w_lg_w_lg_rclkcmpsqmd1943w1944w(0) <= wire_w_lg_rclkcmpsqmd1943w(0) AND wire_w_lg_nlillii120w(0); + wire_w_lg_w_lg_rclkcmpsqmd1943w1962w(0) <= wire_w_lg_rclkcmpsqmd1943w(0) AND wire_n1O1lO_dataout; + wire_w_lg_w_lg_rgenericfifo32w2466w(0) <= wire_w_lg_rgenericfifo32w(0) AND nli0l1O; + wire_w_lg_w_lg_rgenericfifo32w754w(0) <= wire_w_lg_rgenericfifo32w(0) AND nliilOO; + wire_w_lg_w_lg_rrx_pipe_enable1942w1946w(0) <= wire_w_lg_rrx_pipe_enable1942w(0) AND wire_w_lg_w_lg_w_lg_rclkcmpsqmd1943w1944w1945w(0); + wire_w_lg_w_lg_rrx_pipe_enable1942w2369w(0) <= wire_w_lg_rrx_pipe_enable1942w(0) AND wire_w_lg_rskpsetbased2368w(0); + wire_w_lg_w_lg_rskpsetbased1868w1964w(0) <= wire_w_lg_rskpsetbased1868w(0) AND wire_w_lg_w_lg_w_lg_rclkcmpsqmd1943w1962w1963w(0); + wire_w_lg_w_lg_rskpsetbased1868w2360w(0) <= wire_w_lg_rskpsetbased1868w(0) AND wire_n1Olll_w_lg_dataout2359w(0); + wire_w_lg_w_lg_rtruebac2bac1952w1970w(0) <= wire_w_lg_rtruebac2bac1952w(0) AND wire_n1i_w_lg_n11iOO1969w(0); + wire_w_lg_w_lg_rtruebac2bac1952w2367w(0) <= wire_w_lg_rtruebac2bac1952w(0) AND nlO00Oi; + wire_w_lg_w_lg_w_dskwclksel_range33w34w35w(0) <= wire_w_lg_w_dskwclksel_range33w34w(0) AND rmatchen; + wire_w_lg_w_lg_w_lg_rskpsetbased2366w2370w2371w(0) <= wire_w_lg_w_lg_rskpsetbased2366w2370w(0) AND nlO01O; + wire_w_lg_cg_comp_rd_d_ch01958w(0) <= cg_comp_rd_d_ch0 AND cg_comp_rd_d_ch1; + wire_w_lg_cg_comp_rd_d_ch21959w(0) <= cg_comp_rd_d_ch2 AND wire_w_lg_cg_comp_rd_d_ch01958w(0); + wire_w_lg_cg_comp_rd_d_ch31960w(0) <= cg_comp_rd_d_ch3 AND wire_w_lg_cg_comp_rd_d_ch21959w(0); + wire_w_lg_cg_comp_wr_ch02353w(0) <= cg_comp_wr_ch0 AND cg_comp_wr_ch1; + wire_w_lg_cg_comp_wr_ch22354w(0) <= cg_comp_wr_ch2 AND wire_w_lg_cg_comp_wr_ch02353w(0); + wire_w_lg_cg_comp_wr_ch32355w(0) <= cg_comp_wr_ch3 AND wire_w_lg_cg_comp_wr_ch22354w(0); + wire_w_lg_nli0O1i2548w(0) <= nli0O1i AND wire_nlO0OiO_w_lg_w_lg_w_lg_dataout2542w2546w2547w(0); + wire_w_lg_nlii0Oi1975w(0) <= nlii0Oi AND nlii1ll; + wire_w_lg_nlii0Ol1974w(0) <= nlii0Ol AND nlii1lO; + wire_w_lg_nliiOii734w(0) <= nliiOii AND wire_nliOOi_w_lg_dataout733w(0); + wire_w_lg_nliiOli735w(0) <= nliiOli AND wire_w_lg_nliiOii734w(0); + wire_w_lg_nlillil2357w(0) <= nlillil AND wire_w_lg_w_lg_w_lg_nlilO0l1957w2352w2356w(0); + wire_w_lg_rauto_speed_ena7w(0) <= rauto_speed_ena AND wire_w_lg_rfreq_sel6w(0); + wire_w_lg_rclkcmpsqmd1968w(0) <= rclkcmpsqmd AND wire_w_lg_nlillii120w(0); + wire_w_lg_rgenericfifo756w(0) <= rgenericfifo AND wire_nii_w_lg_n0Oiil755w(0); + wire_w_lg_rgenericfifo2468w(0) <= rgenericfifo AND wire_nii_w_lg_nlll1li2467w(0); + wire_w_lg_rmatchen2152w(0) <= rmatchen AND rrx_pipe_enable; + wire_w_lg_rrx_pipe_enable2544w(0) <= rrx_pipe_enable AND nlii0OO; + wire_w_lg_rskpsetbased1947w(0) <= rskpsetbased AND wire_w_lg_w_lg_rrx_pipe_enable1942w1946w(0); + wire_w_lg_rskpsetbased2368w(0) <= rskpsetbased AND wire_w_lg_w_lg_rtruebac2bac1952w2367w(0); + wire_w_lg_rskpsetbased2366w(0) <= rskpsetbased AND wire_w_lg_rtruebac2bac2365w(0); + wire_w_lg_rtruebac2bac2365w(0) <= rtruebac2bac AND wire_nii_w_lg_nlO00Oi2364w(0); + wire_w_lg_hard_reset25w(0) <= NOT hard_reset; + wire_w_lg_is_lane01989w(0) <= NOT is_lane0; + wire_w_lg_nli0iii2511w(0) <= NOT nli0iii; + wire_w_lg_nli0l0i2530w(0) <= NOT nli0l0i; + wire_w_lg_nli0l0l2559w(0) <= NOT nli0l0l; + wire_w_lg_nli0l1O2426w(0) <= NOT nli0l1O; + wire_w_lg_nli0liO2283w(0) <= NOT nli0liO; + wire_w_lg_nli0lli2281w(0) <= NOT nli0lli; + wire_w_lg_nli0lll2279w(0) <= NOT nli0lll; + wire_w_lg_nli0llO2277w(0) <= NOT nli0llO; + wire_w_lg_nli0Oli2137w(0) <= NOT nli0Oli; + wire_w_lg_nli0OlO3187w(0) <= NOT nli0OlO; + wire_w_lg_nlii1li1995w(0) <= NOT nlii1li; + wire_w_lg_nlii1Oi2149w(0) <= NOT nlii1Oi; + wire_w_lg_nliii0i2236w(0) <= NOT nliii0i; + wire_w_lg_nliil0O841w(0) <= NOT nliil0O; + wire_w_lg_nliilii839w(0) <= NOT nliilii; + wire_w_lg_nliilil837w(0) <= NOT nliilil; + wire_w_lg_nliiliO835w(0) <= NOT nliiliO; + wire_w_lg_nliilli968w(0) <= NOT nliilli; + wire_w_lg_nliilll798w(0) <= NOT nliilll; + wire_w_lg_nliilOO744w(0) <= NOT nliilOO; + wire_w_lg_nliiO0O726w(0) <= NOT nliiO0O; + wire_w_lg_nlil00O1791w(0) <= NOT nlil00O; + wire_w_lg_nlil0iO547w(0) <= NOT nlil0iO; + wire_w_lg_nliliii460w(0) <= NOT nliliii; + wire_w_lg_nliliil440w(0) <= NOT nliliil; + wire_w_lg_nlill0O122w(0) <= NOT nlill0O; + wire_w_lg_nlillii120w(0) <= NOT nlillii; + wire_w_lg_nlilO0l1957w(0) <= NOT nlilO0l; + wire_w_lg_nliO1il2w(0) <= NOT nliO1il; + wire_w_lg_rclkcmpinsertpad655w(0) <= NOT rclkcmpinsertpad; + wire_w_lg_rclkcmpsqmd1943w(0) <= NOT rclkcmpsqmd; + wire_w_lg_rfreq_sel6w(0) <= NOT rfreq_sel; + wire_w_lg_rgenericfifo32w(0) <= NOT rgenericfifo; + wire_w_lg_rmatchen438w(0) <= NOT rmatchen; + wire_w_lg_rrx_pipe_enable1942w(0) <= NOT rrx_pipe_enable; + wire_w_lg_rskpsetbased1868w(0) <= NOT rskpsetbased; + wire_w_lg_rtruebac2bac1952w(0) <= NOT rtruebac2bac; + wire_w_lg_w_dskwclksel_range33w34w(0) <= NOT wire_w_dskwclksel_range33w(0); + wire_w_lg_w1977w1978w(0) <= wire_w1977w(0) OR n11O1l; + wire_w_lg_w_lg_w_lg_w_lg_rauto_speed_ena7w18w19w20w(0) <= wire_w_lg_w_lg_w_lg_rauto_speed_ena7w18w19w(0) OR rdwidth_rx; + wire_w_lg_w_lg_w_lg_rskpsetbased1868w2360w2361w(0) <= wire_w_lg_w_lg_rskpsetbased1868w2360w(0) OR nlO1i0O; + wire_w_lg_w_lg_w_lg_w_dskwclksel_range33w34w35w36w(0) <= wire_w_lg_w_lg_w_dskwclksel_range33w34w35w(0) OR nlilO0l; + wire_w_lg_w_lg_nlii0Ol1974w1976w(0) <= wire_w_lg_nlii0Ol1974w(0) OR wire_w_lg_nlii0Oi1975w(0); + wire_w_lg_w_lg_rskpsetbased2366w2370w(0) <= wire_w_lg_rskpsetbased2366w(0) OR wire_w_lg_w_lg_rrx_pipe_enable1942w2369w(0); + wire_w_lg_w_lg_nlilO0l1957w2352w(0) <= wire_w_lg_nlilO0l1957w(0) OR nliii0i; + wire_w_lg_w_lg_w_lg_nlilO0l1957w2352w2356w(0) <= wire_w_lg_w_lg_nlilO0l1957w2352w(0) OR wire_w_lg_cg_comp_wr_ch32355w(0); + wire_w_lg_nlii1Oi1979w(0) <= nlii1Oi OR nlO00OO; + wire_w_lg_nlii1Ol1980w(0) <= nlii1Ol OR wire_w_lg_nlii1Oi1979w(0); + wire_w_lg_rtruebac2bac1971w(0) <= rtruebac2bac OR wire_w_lg_w_lg_rtruebac2bac1952w1970w(0); + align_status_sync <= nlOiO0O; + cg_comp_rd_d_out <= wire_n1Oiil_dataout; + cg_comp_wr_out <= nlillil; + comp_curr_st <= ( nlO01l & nllOOl); + cudi <= ( wire_niOi_dataout & wire_nilO_dataout & wire_nill_dataout & wire_nili_dataout & wire_niiO_dataout & wire_niil_dataout & wire_niii_dataout & wire_ni0O_dataout & wire_ni0l_dataout & wire_ni0i_dataout & wire_ni1O_dataout & wire_ni1l_dataout & wire_ni1i_dataout & wire_n0OO_dataout & wire_n0Ol_dataout & wire_n0Oi_dataout & wire_n0lO_dataout & wire_n0ll_dataout & wire_n0li_dataout & wire_n0iO_dataout & wire_n0il_dataout & wire_n0ii_dataout & wire_n00O_dataout & wire_n00l_dataout & wire_n00i_dataout & wire_n01O_dataout & wire_n01l_dataout & wire_n01i_dataout & wire_n1OO_dataout & wire_n1Ol_dataout & wire_n1Oi_dataout & wire_n1lO_dataout); + cudi_valid <= wire_niiOi_dataout; + del_cond_met_out <= wire_n1OllO_o; + fifo_cnt <= ( wire_nl1O_dataout & wire_nl1l_dataout & wire_nl1i_dataout & wire_niOO_dataout & wire_niOl_dataout); + fifo_ovr_out <= nlO01O; + fifo_rd_out_comp <= n1lili; + insert_incomplete_out <= n1liil; + latency_comp_out <= wire_w_lg_nlillii120w(0); + nli00ll <= (nlO10lO XOR nlO10li); + nli00lO <= (((((((((wire_nlli01O_o(18) OR wire_nlli01O_o(17)) OR wire_nlli01O_o(14)) OR wire_nlli01O_o(13)) OR wire_nlli01O_o(10)) OR wire_nlli01O_o(9)) OR wire_nlli01O_o(6)) OR wire_nlli01O_o(5)) OR wire_nlli01O_o(2)) OR wire_nlli01O_o(1)); + nli00Oi <= ((((((((((wire_nlli01O_o(20) OR wire_nlli01O_o(19)) OR wire_nlli01O_o(12)) OR wire_nlli01O_o(11)) OR wire_nlli01O_o(4)) OR wire_nlli01O_o(3)) OR wire_nlli01O_o(18)) OR wire_nlli01O_o(13)) OR wire_nlli01O_o(10)) OR wire_nlli01O_o(5)) OR wire_nlli01O_o(2)); + nli00Ol <= ((((((((wire_nlli01O_o(20) OR wire_nlli01O_o(11)) OR wire_nlli01O_o(8)) OR wire_nlli01O_o(7)) OR wire_nlli01O_o(4)) OR wire_nlli01O_o(10)) OR wire_nlli01O_o(9)) OR wire_nlli01O_o(6)) OR wire_nlli01O_o(5)); + nli00OO <= ((((((((((((wire_nlli01O_o(20) OR wire_nlli01O_o(19)) OR wire_nlli01O_o(16)) OR wire_nlli01O_o(15)) OR wire_nlli01O_o(12)) OR wire_nlli01O_o(11)) OR wire_nlli01O_o(8)) OR wire_nlli01O_o(18)) OR wire_nlli01O_o(17)) OR wire_nlli01O_o(14)) OR wire_nlli01O_o(13)) OR wire_nlli01O_o(10)) OR wire_nlli01O_o(9)); + nli0i0i <= (wire_n1OlOi_o OR nllil1i); + nli0i0l <= (wire_n1OllO_o OR nllil1O); + nli0i0O <= ((((nlll1iO OR nlll1il) OR nlll1ii) OR nlll10O) OR nlll10l); + nli0i1i <= ((((wire_nlli01O_o(20) OR wire_nlli01O_o(19)) OR wire_nlli01O_o(16)) OR wire_nlli01O_o(18)) OR wire_nlli01O_o(17)); + nli0i1l <= (nli0l0i OR nlli0Oi); + nli0i1O <= ((((((NOT wire_nlO0lli_o(6)) AND (NOT (wire_nlO0lli_o(1) XOR nllii1O))) AND (NOT (wire_nlO0lli_o(2) XOR nllii0l))) AND (NOT (wire_nlO0lli_o(3) XOR nllii0O))) AND (NOT (wire_nlO0lli_o(4) XOR nlliiii))) AND (NOT (wire_nlO0lli_o(5) XOR nlliiil))); + nli0iii <= ((((wire_nii_w_lg_nlll1iO3168w(0) AND wire_nii_w_lg_nlll1il3169w(0)) AND wire_nii_w_lg_nlll1ii3171w(0)) AND wire_nii_w_lg_nlll10O3173w(0)) AND wire_nii_w_lg_nlll10l3175w(0)); + nli0iil <= ((wire_w_lg_rclkcmpsqmd1943w(0) AND (wire_w_lg_w_lg_rgenericfifo32w2466w(0) OR wire_w_lg_rgenericfifo2468w(0))) AND nli0ill); + nli0iiO <= (nli0l1i AND nli0ill); + nli0ili <= ((rclkcmpsqmd AND (nli0l1O AND (nlillOl OR nllil0l))) AND nli0ill); + nli0ill <= (wire_w_lg_rskpsetbased1868w(0) OR wire_w_lg_nli0l0i2530w(0)); + nli0ilO <= ((rskpsetbased OR (wire_w_lg_rskpsetbased1868w(0) AND wire_w_lg_nli0l1O2426w(0))) AND nli0l0i); + nli0iOi <= ((wire_w_lg_rgenericfifo32w(0) AND wire_w_lg_nli0l1O2426w(0)) OR (rgenericfifo AND nlll1li)); + nli0iOl <= ((((wire_nii_w_lg_nlllO0i2306w(0) AND wire_nii_w_lg_nlllO1O2304w(0)) AND wire_nii_w_lg_nlllO1l2302w(0)) AND wire_nii_w_lg_nlllO1i2300w(0)) AND wire_nii_w_lg_nllllli2298w(0)); + nli0iOO <= (wire_w_lg_rgenericfifo32w(0) AND nli0l1i); + nli0l0i <= ((wire_w_lg_nli0l0l2559w(0) AND (nli0O1O AND nli0i1O)) AND wire_nii_w_lg_nlli0Ol2562w(0)); + nli0l0l <= (wire_w_lg_w_lg_w_lg_rskpsetbased1868w2360w2361w(0) OR wire_n1OllO_w_lg_o2372w(0)); + nli0l0O <= ((((wire_nii_w_lg_nlO011i3148w(0) AND wire_nii_w_lg_nlO1OOO3149w(0)) AND (NOT (rstart_threshold(0) XOR nlO1OiO))) AND (NOT (rstart_threshold(1) XOR nlO1OOi))) AND (NOT (rstart_threshold(2) XOR nlO1OOl))); + nli0l1i <= (rclkcmpsqmd AND nli0l1O); + nli0l1l <= (((wire_nii_w_lg_nlllO0i3160w(0) AND wire_nii_w_lg_nlllO1l2302w(0)) AND nlllO1i) AND nllllli); + nli0l1O <= (nli0l0l OR (rskpsetbased AND nli0l0i)); + nli0lii <= (wire_w_lg_rgenericfifo32w(0) AND wire_nlOi10l_w_lg_dataout2553w(0)); + nli0lil <= (((((NOT (nllllli XOR nli0llO)) AND (NOT (nlllO1i XOR nli0lll))) AND (NOT (nlllO1l XOR nli0lli))) AND (NOT (nlllO1O XOR nli0liO))) AND (NOT (nlO10Oi XOR nlllO0i))); + nli0liO <= (wire_nii_w_lg_nlO10Oi2285w(0) AND nlO10lO); + nli0lli <= (wire_nii_w_lg_nlO10Oi2285w(0) AND (nlO10lO XOR nlO10ll)); + nli0lll <= (nlO10Oi XOR (nlO10ll XOR nli00ll)); + nli0llO <= (nlO10Oi XOR (nli00ll XOR (nlO10ll XOR nllO1li))); + nli0lOi <= ((((((((((NOT (rclkcmpsq1n(0) XOR wire_nlO0lOi_dataout)) AND (NOT (rclkcmpsq1n(1) XOR wire_nlO0lOl_dataout))) AND (NOT (rclkcmpsq1n(2) XOR wire_nlO0lOO_dataout))) AND (NOT (rclkcmpsq1n(3) XOR wire_nlO0O1i_dataout))) AND (NOT (rclkcmpsq1n(4) XOR wire_nlO0O1l_dataout))) AND (NOT (rclkcmpsq1n(5) XOR wire_nlO0O1O_dataout))) AND (NOT (rclkcmpsq1n(6) XOR wire_nlO0O0i_dataout))) AND (NOT (rclkcmpsq1n(7) XOR wire_nlO0O0l_dataout))) AND (NOT (rclkcmpsq1n(8) XOR wire_nlO0O0O_dataout))) AND (NOT (rclkcmpsq1n(9) XOR wire_nlO0Oii_dataout))); + nli0lOl <= ((((((((((NOT (rclkcmpsq1p(0) XOR wire_nlO0lOi_dataout)) AND (NOT (rclkcmpsq1p(1) XOR wire_nlO0lOl_dataout))) AND (NOT (rclkcmpsq1p(2) XOR wire_nlO0lOO_dataout))) AND (NOT (rclkcmpsq1p(3) XOR wire_nlO0O1i_dataout))) AND (NOT (rclkcmpsq1p(4) XOR wire_nlO0O1l_dataout))) AND (NOT (rclkcmpsq1p(5) XOR wire_nlO0O1O_dataout))) AND (NOT (rclkcmpsq1p(6) XOR wire_nlO0O0i_dataout))) AND (NOT (rclkcmpsq1p(7) XOR wire_nlO0O0l_dataout))) AND (NOT (rclkcmpsq1p(8) XOR wire_nlO0O0O_dataout))) AND (NOT (rclkcmpsq1p(9) XOR wire_nlO0Oii_dataout))); + nli0lOO <= (nlii0OO AND (wire_w_lg_rclkcmpsqmd1943w(0) OR nlO00ii)); + nli0O0i <= (wire_w_lg_rmatchen438w(0) OR rgenericfifo); + nli0O0l <= (rmatchen OR rgenericfifo); + nli0O1i <= (wire_nlO0OlO_w_lg_dataout2227w(0) AND wire_nlO0Oli_w_lg_w_lg_dataout2228w2234w(0)); + nli0O1l <= ((((((NOT wire_nlO0lli_o(6)) AND (NOT (wire_nlO0lli_o(1) XOR nllii1O))) AND (NOT (wire_nlO0lli_o(2) XOR nllii0l))) AND (NOT (wire_nlO0lli_o(3) XOR nllii0O))) AND (NOT (wire_nlO0lli_o(4) XOR nlliiii))) AND (NOT (wire_nlO0lli_o(5) XOR nlliiil))); + nli0O1O <= (((((NOT (rfull_threshold(0) XOR nlO1OiO)) AND (NOT (rfull_threshold(1) XOR nlO1OOi))) AND (NOT (rfull_threshold(2) XOR nlO1OOl))) AND (NOT (rfull_threshold(3) XOR nlO1OOO))) AND (NOT (rfull_threshold(4) XOR nlO011i))); + nli0Oii <= (rgenericfifo AND wire_n1i_w_lg_nlOi1iO2144w(0)); + nli0Oil <= ((wire_w_lg_rgenericfifo32w(0) AND wire_w_lg_nlii1li1995w(0)) OR nlOi1iO); + nli0OiO <= (n110ll OR n110iO); + nli0Oli <= (wire_n1i_w_lg_n110iO2150w(0) AND (wire_n1i_w_lg_n110ll2151w(0) AND wire_n1i_w_lg_n1liil2156w(0))); + nli0Oll <= (((((((wire_n1i_w_lg_n11iOl3083w(0) AND wire_n1i_w_lg_n11iOi3084w(0)) AND wire_n1i_w_lg_n11ilO3086w(0)) AND wire_n1i_w_lg_n11ill3088w(0)) AND wire_n1i_w_lg_n11ili3090w(0)) AND wire_n1i_w_lg_n11iiO3092w(0)) AND wire_n1i_w_lg_n11iil3094w(0)) AND wire_n1i_w_lg_n110lO3096w(0)); + nli0OlO <= (rgenericfifo OR wire_nlOi11i_dataout); + nli0OOi <= (wire_n1O11l_o AND (wire_n1Oiil_dataout AND (NOT ((wire_n1i_w_lg_n11O0l2093w(0) AND wire_n1i_w_lg_n11O0i2094w(0)) AND wire_n1i_w_lg_n11O1O2096w(0))))); + nli0OOl <= (wire_n1O11l_o AND nlii1Ol); + nli0OOO <= (wire_n1Oiil_dataout AND wire_n1Oi1O_dataout); + nlii00i <= ((((wire_nliO1lO_o(13) OR wire_nliO1lO_o(7)) OR wire_nliO1lO_o(4)) OR wire_nliO1lO_o(2)) OR wire_nliO1lO_o(1)); + nlii00l <= (((((((((wire_nliO01i_o(26) OR wire_nliO01i_o(25)) OR wire_nliO01i_o(11)) OR wire_nliO01i_o(8)) OR wire_nliO01i_o(7)) OR wire_nliO01i_o(4)) OR wire_nliO01i_o(14)) OR wire_nliO01i_o(13)) OR wire_nliO01i_o(2)) OR wire_nliO01i_o(1)); + nlii00O <= (wire_w_lg_rgenericfifo32w(0) AND wire_nlOi11i_w_lg_dataout1992w(0)); + nlii01i <= ((((((NOT wire_n1O1OO_o(6)) AND (NOT (wire_n1O1OO_o(1) XOR nlii00l))) AND (NOT (wire_n1O1OO_o(2) XOR nlii00i))) AND (NOT (wire_n1O1OO_o(3) XOR nlii01O))) AND (NOT (wire_n1O1OO_o(4) XOR wire_nliO1Ol_o(1)))) AND (NOT (wire_n1O1OO_o(5) XOR nlii01l))); + nlii01l <= ((((wire_nliO01i_o(30) OR wire_nliO01i_o(27)) OR wire_nliO01i_o(26)) OR wire_nliO01i_o(25)) OR wire_nliO01i_o(24)); + nlii01O <= ((((((((wire_nliO01i_o(30) OR wire_nliO01i_o(11)) OR wire_nliO01i_o(10)) OR wire_nliO01i_o(9)) OR wire_nliO01i_o(8)) OR wire_nliO01i_o(7)) OR wire_nliO01i_o(6)) OR wire_nliO01i_o(5)) OR wire_nliO01i_o(4)); + nlii0ii <= ((((((((((NOT (rclkcmpsq1n(0) XOR nlOl01O)) AND (NOT (rclkcmpsq1n(1) XOR nlOl00i))) AND (NOT (rclkcmpsq1n(2) XOR nlOl00l))) AND (NOT (rclkcmpsq1n(3) XOR nlOl00O))) AND (NOT (rclkcmpsq1n(4) XOR nlOl0ii))) AND (NOT (rclkcmpsq1n(5) XOR nlOl0il))) AND (NOT (rclkcmpsq1n(6) XOR nlOl0iO))) AND (NOT (rclkcmpsq1n(7) XOR nlOl0li))) AND (NOT (rclkcmpsq1n(8) XOR nlOl0ll))) AND (NOT (rclkcmpsq1n(9) XOR nlOl0lO))); + nlii0il <= ((((((((((NOT (rclkcmpsq1p(0) XOR nlOl01O)) AND (NOT (rclkcmpsq1p(1) XOR nlOl00i))) AND (NOT (rclkcmpsq1p(2) XOR nlOl00l))) AND (NOT (rclkcmpsq1p(3) XOR nlOl00O))) AND (NOT (rclkcmpsq1p(4) XOR nlOl0ii))) AND (NOT (rclkcmpsq1p(5) XOR nlOl0il))) AND (NOT (rclkcmpsq1p(6) XOR nlOl0iO))) AND (NOT (rclkcmpsq1p(7) XOR nlOl0li))) AND (NOT (rclkcmpsq1p(8) XOR nlOl0ll))) AND (NOT (rclkcmpsq1p(9) XOR nlOl0lO))); + nlii0iO <= ((((((((((NOT (rclkcmpsq1n(0) XOR nlOl10O)) AND (NOT (rclkcmpsq1n(1) XOR nlOl1ii))) AND (NOT (rclkcmpsq1n(2) XOR nlOl1il))) AND (NOT (rclkcmpsq1n(3) XOR nlOl1iO))) AND (NOT (rclkcmpsq1n(4) XOR nlOl1li))) AND (NOT (rclkcmpsq1n(5) XOR nlOl1ll))) AND (NOT (rclkcmpsq1n(6) XOR nlOl1lO))) AND (NOT (rclkcmpsq1n(7) XOR nlOl1Oi))) AND (NOT (rclkcmpsq1n(8) XOR nlOl1Ol))) AND (NOT (rclkcmpsq1n(9) XOR nlOl1OO))); + nlii0li <= ((((((((((NOT (rclkcmpsq1p(0) XOR nlOl10O)) AND (NOT (rclkcmpsq1p(1) XOR nlOl1ii))) AND (NOT (rclkcmpsq1p(2) XOR nlOl1il))) AND (NOT (rclkcmpsq1p(3) XOR nlOl1iO))) AND (NOT (rclkcmpsq1p(4) XOR nlOl1li))) AND (NOT (rclkcmpsq1p(5) XOR nlOl1ll))) AND (NOT (rclkcmpsq1p(6) XOR nlOl1lO))) AND (NOT (rclkcmpsq1p(7) XOR nlOl1Oi))) AND (NOT (rclkcmpsq1p(8) XOR nlOl1Ol))) AND (NOT (rclkcmpsq1p(9) XOR nlOl1OO))); + nlii0ll <= ((((((((((NOT (wire_n1OiOi_dataout XOR nlOl01O)) AND (NOT (wire_n1OiOl_dataout XOR nlOl00i))) AND (NOT (wire_n1OiOO_dataout XOR nlOl00l))) AND (NOT (wire_n1Ol1i_dataout XOR nlOl00O))) AND (NOT (wire_n1Ol1l_dataout XOR nlOl0ii))) AND (NOT (wire_n1Ol1O_dataout XOR nlOl0il))) AND (NOT (wire_n1Ol0i_dataout XOR nlOl0iO))) AND (NOT (wire_n1Ol0l_dataout XOR nlOl0li))) AND (NOT (wire_n1Ol0O_dataout XOR nlOl0ll))) AND (NOT (wire_n1Olii_dataout XOR nlOl0lO))); + nlii0lO <= ((((((((((NOT (wire_n1OlOl_dataout XOR nlOl01O)) AND (NOT (wire_n1OlOO_dataout XOR nlOl00i))) AND (NOT (wire_n1OO1i_dataout XOR nlOl00l))) AND (NOT (wire_n1OO1l_dataout XOR nlOl00O))) AND (NOT (wire_n1OO1O_dataout XOR nlOl0ii))) AND (NOT (wire_n1OO0i_dataout XOR nlOl0il))) AND (NOT (wire_n1OO0l_dataout XOR nlOl0iO))) AND (NOT (wire_n1OO0O_dataout XOR nlOl0li))) AND (NOT (wire_n1OOii_dataout XOR nlOl0ll))) AND (NOT (wire_n1OOil_dataout XOR nlOl0lO))); + nlii0Oi <= ((((((((((NOT (wire_n1OiOi_dataout XOR nlOl10O)) AND (NOT (wire_n1OiOl_dataout XOR nlOl1ii))) AND (NOT (wire_n1OiOO_dataout XOR nlOl1il))) AND (NOT (wire_n1Ol1i_dataout XOR nlOl1iO))) AND (NOT (wire_n1Ol1l_dataout XOR nlOl1li))) AND (NOT (wire_n1Ol1O_dataout XOR nlOl1ll))) AND (NOT (wire_n1Ol0i_dataout XOR nlOl1lO))) AND (NOT (wire_n1Ol0l_dataout XOR nlOl1Oi))) AND (NOT (wire_n1Ol0O_dataout XOR nlOl1Ol))) AND (NOT (wire_n1Olii_dataout XOR nlOl1OO))); + nlii0Ol <= ((((((((((NOT (wire_n1OlOl_dataout XOR nlOl10O)) AND (NOT (wire_n1OlOO_dataout XOR nlOl1ii))) AND (NOT (wire_n1OO1i_dataout XOR nlOl1il))) AND (NOT (wire_n1OO1l_dataout XOR nlOl1iO))) AND (NOT (wire_n1OO1O_dataout XOR nlOl1li))) AND (NOT (wire_n1OO0i_dataout XOR nlOl1ll))) AND (NOT (wire_n1OO0l_dataout XOR nlOl1lO))) AND (NOT (wire_n1OO0O_dataout XOR nlOl1Oi))) AND (NOT (wire_n1OOii_dataout XOR nlOl1Ol))) AND (NOT (wire_n1OOil_dataout XOR nlOl1OO))); + nlii0OO <= (nliii1l OR nliii1i); + nlii10i <= (((wire_n1i_w_lg_n100ii3078w(0) AND wire_n1i_w_lg_n1000l3079w(0)) AND n1000i) AND n1001O); + nlii10l <= ((wire_w_lg_rgenericfifo32w(0) AND wire_w_lg_w_lg_nlii1li1995w1996w(0)) OR nlii1iO); + nlii10O <= (dskwclksel(0) AND nlii1il); + nlii11i <= ((((wire_n1l1OO_o(8) OR wire_n1l1OO_o(6)) OR wire_n1l1OO_o(4)) OR wire_n1l1OO_o(2)) OR wire_n1l1OO_o(0)); + nlii11l <= (((((((wire_n1l00O_o(10) OR wire_n1l00O_o(9)) OR wire_n1l00O_o(8)) OR wire_n1l00O_o(7)) OR wire_n1l00O_o(6)) OR wire_n1l00O_o(5)) OR wire_n1l00O_o(4)) OR wire_n1l00O_o(3)); + nlii11O <= (((((((((wire_n1l00O_o(16) OR wire_n1l00O_o(15)) OR wire_n1l00O_o(14)) OR wire_n1l00O_o(13)) OR wire_n1l00O_o(12)) OR wire_n1l00O_o(11)) OR wire_n1l00O_o(10)) OR wire_n1l00O_o(9)) OR wire_n1l00O_o(8)) OR wire_n1l00O_o(7)); + nlii1ii <= ((NOT dskwclksel(0)) AND nlii1il); + nlii1il <= (wire_w_lg_is_lane01989w(0) AND nlilO0l); + nlii1iO <= (rgenericfifo AND nlOi1iO); + nlii1li <= (((wire_w_lg_nlilO0l1957w(0) OR wire_w_lg_cg_comp_rd_d_ch31960w(0)) AND wire_n1Oiil_w_lg_dataout1966w(0)) OR (wire_w_lg_w1977w1978w(0) OR wire_w_lg_nlii1Ol1980w(0))); + nlii1ll <= ((((((((((NOT (rclkcmpsq1n(0) XOR nlOiOil)) AND (NOT (rclkcmpsq1n(1) XOR nlOiOli))) AND (NOT (rclkcmpsq1n(2) XOR nlOiOll))) AND (NOT (rclkcmpsq1n(3) XOR nlOiOlO))) AND (NOT (rclkcmpsq1n(4) XOR nlOiOOi))) AND (NOT (rclkcmpsq1n(5) XOR nlOiOOl))) AND (NOT (rclkcmpsq1n(6) XOR nlOiOOO))) AND (NOT (rclkcmpsq1n(7) XOR nlOl11i))) AND (NOT (rclkcmpsq1n(8) XOR nlOl11l))) AND (NOT (rclkcmpsq1n(9) XOR nlOl11O))); + nlii1lO <= ((((((((((NOT (rclkcmpsq1p(0) XOR nlOiOil)) AND (NOT (rclkcmpsq1p(1) XOR nlOiOli))) AND (NOT (rclkcmpsq1p(2) XOR nlOiOll))) AND (NOT (rclkcmpsq1p(3) XOR nlOiOlO))) AND (NOT (rclkcmpsq1p(4) XOR nlOiOOi))) AND (NOT (rclkcmpsq1p(5) XOR nlOiOOl))) AND (NOT (rclkcmpsq1p(6) XOR nlOiOOO))) AND (NOT (rclkcmpsq1p(7) XOR nlOl11i))) AND (NOT (rclkcmpsq1p(8) XOR nlOl11l))) AND (NOT (rclkcmpsq1p(9) XOR nlOl11O))); + nlii1Oi <= (rskpsetbased AND n110ll); + nlii1Ol <= ((wire_n1Oiil_w_lg_dataout1941w(0) AND wire_w_lg_w_lg_w_lg_rskpsetbased1947w1948w1949w(0)) AND wire_n1O11l_o); + nlii1OO <= (rtruebac2bac OR (wire_w_lg_rtruebac2bac1952w(0) AND wire_n1i_w_lg_n11O1i1953w(0))); + nliii0i <= (rskpsetbased OR rclkcmpsqmd); + nliii0l <= (n0O0Ol XOR n0O0lO); + nliii0O <= ((((n0O0ll AND n0l0il) AND wire_nii_w_lg_n0l0ii862w(0)) AND wire_nii_w_lg_n0l00O860w(0)) AND n0l00l); + nliii1i <= ((((((((((NOT (wire_n1OiOi_dataout XOR wire_nlO0lOi_dataout)) AND (NOT (wire_n1OiOl_dataout XOR wire_nlO0lOl_dataout))) AND (NOT (wire_n1OiOO_dataout XOR wire_nlO0lOO_dataout))) AND (NOT (wire_n1Ol1i_dataout XOR wire_nlO0O1i_dataout))) AND (NOT (wire_n1Ol1l_dataout XOR wire_nlO0O1l_dataout))) AND (NOT (wire_n1Ol1O_dataout XOR wire_nlO0O1O_dataout))) AND (NOT (wire_n1Ol0i_dataout XOR wire_nlO0O0i_dataout))) AND (NOT (wire_n1Ol0l_dataout XOR wire_nlO0O0l_dataout))) AND (NOT (wire_n1Ol0O_dataout XOR wire_nlO0O0O_dataout))) AND (NOT (wire_n1Olii_dataout XOR wire_nlO0Oii_dataout))); + nliii1l <= ((((((((((NOT (wire_n1OlOl_dataout XOR wire_nlO0lOi_dataout)) AND (NOT (wire_n1OlOO_dataout XOR wire_nlO0lOl_dataout))) AND (NOT (wire_n1OO1i_dataout XOR wire_nlO0lOO_dataout))) AND (NOT (wire_n1OO1l_dataout XOR wire_nlO0O1i_dataout))) AND (NOT (wire_n1OO1O_dataout XOR wire_nlO0O1l_dataout))) AND (NOT (wire_n1OO0i_dataout XOR wire_nlO0O1O_dataout))) AND (NOT (wire_n1OO0l_dataout XOR wire_nlO0O0i_dataout))) AND (NOT (wire_n1OO0O_dataout XOR wire_nlO0O0l_dataout))) AND (NOT (wire_n1OOii_dataout XOR wire_nlO0O0O_dataout))) AND (NOT (wire_n1OOil_dataout XOR wire_nlO0Oii_dataout))); + nliii1O <= (wire_n1OliO_o(3) OR wire_n1OliO_o(0)); + nliiiii <= (((((((((wire_n0OO1l_o(18) OR wire_n0OO1l_o(17)) OR wire_n0OO1l_o(14)) OR wire_n0OO1l_o(13)) OR wire_n0OO1l_o(10)) OR wire_n0OO1l_o(9)) OR wire_n0OO1l_o(6)) OR wire_n0OO1l_o(5)) OR wire_n0OO1l_o(2)) OR wire_n0OO1l_o(1)); + nliiiil <= ((((((((((wire_n0OO1l_o(20) OR wire_n0OO1l_o(19)) OR wire_n0OO1l_o(18)) OR wire_n0OO1l_o(13)) OR wire_n0OO1l_o(12)) OR wire_n0OO1l_o(11)) OR wire_n0OO1l_o(10)) OR wire_n0OO1l_o(5)) OR wire_n0OO1l_o(4)) OR wire_n0OO1l_o(3)) OR wire_n0OO1l_o(2)); + nliiiiO <= ((((((((wire_n0OO1l_o(20) OR wire_n0OO1l_o(11)) OR wire_n0OO1l_o(10)) OR wire_n0OO1l_o(9)) OR wire_n0OO1l_o(8)) OR wire_n0OO1l_o(7)) OR wire_n0OO1l_o(6)) OR wire_n0OO1l_o(5)) OR wire_n0OO1l_o(4)); + nliiili <= ((((((((((((wire_n0OO1l_o(20) OR wire_n0OO1l_o(19)) OR wire_n0OO1l_o(18)) OR wire_n0OO1l_o(17)) OR wire_n0OO1l_o(16)) OR wire_n0OO1l_o(15)) OR wire_n0OO1l_o(14)) OR wire_n0OO1l_o(13)) OR wire_n0OO1l_o(12)) OR wire_n0OO1l_o(11)) OR wire_n0OO1l_o(10)) OR wire_n0OO1l_o(9)) OR wire_n0OO1l_o(8)); + nliiill <= ((((wire_n0OO1l_o(20) OR wire_n0OO1l_o(19)) OR wire_n0OO1l_o(18)) OR wire_n0OO1l_o(17)) OR wire_n0OO1l_o(16)); + nliiilO <= ((((wire_nii_w_lg_ni1i0l1701w(0) AND wire_nii_w_lg_ni1i0i1702w(0)) AND (NOT (rstart_threshold(0) XOR ni101l))) AND (NOT (rstart_threshold(1) XOR ni1i1l))) AND (NOT (rstart_threshold(2) XOR ni1i1O))); + nliiiOi <= (nliiO0O OR n0OOli); + nliiiOl <= ((((((NOT wire_n0OOOO_o(6)) AND (NOT (wire_n0OOOO_o(1) XOR n0OOll))) AND (NOT (ni111i XOR wire_n0OOOO_o(2)))) AND (NOT (ni111l XOR wire_n0OOOO_o(3)))) AND (NOT (ni111O XOR wire_n0OOOO_o(4)))) AND (NOT (ni110i XOR wire_n0OOOO_o(5)))); + nliiiOO <= (((((NOT (rfull_threshold(0) XOR ni101l)) AND (NOT (rfull_threshold(1) XOR ni1i1l))) AND (NOT (rfull_threshold(2) XOR ni1i1O))) AND (NOT (rfull_threshold(3) XOR ni1i0i))) AND (NOT (rfull_threshold(4) XOR ni1i0l))); + nliil0i <= (wire_nllOiO_o OR ni11OO); + nliil0l <= (((((NOT (n0O0ll XOR nliiliO)) AND (NOT (n0l00l XOR nliilil))) AND (NOT (n0l00O XOR nliilii))) AND (NOT (n0l0ii XOR nliil0O))) AND (NOT (n0O0OO XOR n0l0il))); + nliil0O <= (wire_nii_w_lg_n0O0OO843w(0) AND n0O0Ol); + nliil1O <= (wire_nllOli_o OR ni11lO); + nliilii <= (wire_nii_w_lg_n0O0OO843w(0) AND (n0O0Ol XOR n0O0Oi)); + nliilil <= (n0O0OO XOR (n0O0Oi XOR nliii0l)); + nliiliO <= (n0O0OO XOR (nliii0l XOR (n0O0Oi XOR n0liOl))); + nliilli <= (wire_nllOiO_o AND ((ni00Oi OR ni00iO) AND nlO01O)); + nliilll <= ((((wire_nii_w_lg_ni1O0l1642w(0) AND wire_nii_w_lg_ni1O0i1643w(0)) AND wire_nii_w_lg_ni1O1O1645w(0)) AND wire_nii_w_lg_ni1O1l1647w(0)) AND wire_nii_w_lg_ni1llO1649w(0)); + nliillO <= ((wire_w_lg_w_lg_rgenericfifo32w754w(0) OR wire_w_lg_rgenericfifo756w(0)) AND wire_w_lg_nliiO0O726w(0)); + nliilOi <= ((((ni1O0l OR ni1O0i) OR ni1O1O) OR ni1O1l) OR ni1llO); + nliilOl <= ((wire_w_lg_rgenericfifo32w(0) AND wire_w_lg_nliilOO744w(0)) OR (rgenericfifo AND n0Oiil)); + nliilOO <= (nliilli OR nliiO0O); + nliiO0i <= ((((((((((NOT (sudi(14) XOR rclkcmpsq1n(0))) AND (NOT (sudi(15) XOR rclkcmpsq1n(1)))) AND (NOT (sudi(16) XOR rclkcmpsq1n(2)))) AND (NOT (sudi(17) XOR rclkcmpsq1n(3)))) AND (NOT (sudi(18) XOR rclkcmpsq1n(4)))) AND (NOT (sudi(19) XOR rclkcmpsq1n(5)))) AND (NOT (sudi(20) XOR rclkcmpsq1n(6)))) AND (NOT (sudi(21) XOR rclkcmpsq1n(7)))) AND (NOT (sudi(22) XOR rclkcmpsq1n(8)))) AND (NOT (sudi(23) XOR rclkcmpsq1n(9)))); + nliiO0l <= ((((((((((NOT (sudi(14) XOR rclkcmpsq1p(0))) AND (NOT (sudi(15) XOR rclkcmpsq1p(1)))) AND (NOT (sudi(16) XOR rclkcmpsq1p(2)))) AND (NOT (sudi(17) XOR rclkcmpsq1p(3)))) AND (NOT (sudi(18) XOR rclkcmpsq1p(4)))) AND (NOT (sudi(19) XOR rclkcmpsq1p(5)))) AND (NOT (sudi(20) XOR rclkcmpsq1p(6)))) AND (NOT (sudi(21) XOR rclkcmpsq1p(7)))) AND (NOT (sudi(22) XOR rclkcmpsq1p(8)))) AND (NOT (sudi(23) XOR rclkcmpsq1p(9)))); + nliiO0O <= (wire_nii_w_lg_ni1i0O967w(0) AND (wire_w_lg_nliilli968w(0) AND (nliiiOO AND nliiiOl))); + nliiO1i <= (wire_w_lg_rgenericfifo32w(0) AND wire_nliOOi_w_lg_dataout924w(0)); + nliiO1l <= ((((((((((NOT (sudi(0) XOR rclkcmpsq1n(0))) AND (NOT (sudi(1) XOR rclkcmpsq1n(1)))) AND (NOT (sudi(2) XOR rclkcmpsq1n(2)))) AND (NOT (sudi(3) XOR rclkcmpsq1n(3)))) AND (NOT (sudi(4) XOR rclkcmpsq1n(4)))) AND (NOT (sudi(5) XOR rclkcmpsq1n(5)))) AND (NOT (sudi(6) XOR rclkcmpsq1n(6)))) AND (NOT (sudi(7) XOR rclkcmpsq1n(7)))) AND (NOT (sudi(8) XOR rclkcmpsq1n(8)))) AND (NOT (sudi(9) XOR rclkcmpsq1n(9)))); + nliiO1O <= ((((((((((NOT (sudi(0) XOR rclkcmpsq1p(0))) AND (NOT (sudi(1) XOR rclkcmpsq1p(1)))) AND (NOT (sudi(2) XOR rclkcmpsq1p(2)))) AND (NOT (sudi(3) XOR rclkcmpsq1p(3)))) AND (NOT (sudi(4) XOR rclkcmpsq1p(4)))) AND (NOT (sudi(5) XOR rclkcmpsq1p(5)))) AND (NOT (sudi(6) XOR rclkcmpsq1p(6)))) AND (NOT (sudi(7) XOR rclkcmpsq1p(7)))) AND (NOT (sudi(8) XOR rclkcmpsq1p(8)))) AND (NOT (sudi(9) XOR rclkcmpsq1p(9)))); + nliiOii <= (nliiOiO OR nliiOil); + nliiOil <= ((((((((((NOT (sudi(14) XOR rclkcmpsq1n(10))) AND (NOT (sudi(15) XOR rclkcmpsq1n(11)))) AND (NOT (sudi(16) XOR rclkcmpsq1n(12)))) AND (NOT (sudi(17) XOR rclkcmpsq1n(13)))) AND (NOT (sudi(18) XOR rclkcmpsq1n(14)))) AND (NOT (sudi(19) XOR rclkcmpsq1n(15)))) AND (NOT (sudi(20) XOR rclkcmpsq1n(16)))) AND (NOT (sudi(21) XOR rclkcmpsq1n(17)))) AND (NOT (sudi(22) XOR rclkcmpsq1n(18)))) AND (NOT (sudi(23) XOR rclkcmpsq1n(19)))); + nliiOiO <= ((((((((((NOT (sudi(14) XOR rclkcmpsq1p(10))) AND (NOT (sudi(15) XOR rclkcmpsq1p(11)))) AND (NOT (sudi(16) XOR rclkcmpsq1p(12)))) AND (NOT (sudi(17) XOR rclkcmpsq1p(13)))) AND (NOT (sudi(18) XOR rclkcmpsq1p(14)))) AND (NOT (sudi(19) XOR rclkcmpsq1p(15)))) AND (NOT (sudi(20) XOR rclkcmpsq1p(16)))) AND (NOT (sudi(21) XOR rclkcmpsq1p(17)))) AND (NOT (sudi(22) XOR rclkcmpsq1p(18)))) AND (NOT (sudi(23) XOR rclkcmpsq1p(19)))); + nliiOli <= (nliiOlO OR nliiOll); + nliiOll <= ((((((((((NOT (sudi(0) XOR rclkcmpsq1n(10))) AND (NOT (sudi(1) XOR rclkcmpsq1n(11)))) AND (NOT (sudi(2) XOR rclkcmpsq1n(12)))) AND (NOT (sudi(3) XOR rclkcmpsq1n(13)))) AND (NOT (sudi(4) XOR rclkcmpsq1n(14)))) AND (NOT (sudi(5) XOR rclkcmpsq1n(15)))) AND (NOT (sudi(6) XOR rclkcmpsq1n(16)))) AND (NOT (sudi(7) XOR rclkcmpsq1n(17)))) AND (NOT (sudi(8) XOR rclkcmpsq1n(18)))) AND (NOT (sudi(9) XOR rclkcmpsq1n(19)))); + nliiOlO <= ((((((((((NOT (sudi(0) XOR rclkcmpsq1p(10))) AND (NOT (sudi(1) XOR rclkcmpsq1p(11)))) AND (NOT (sudi(2) XOR rclkcmpsq1p(12)))) AND (NOT (sudi(3) XOR rclkcmpsq1p(13)))) AND (NOT (sudi(4) XOR rclkcmpsq1p(14)))) AND (NOT (sudi(5) XOR rclkcmpsq1p(15)))) AND (NOT (sudi(6) XOR rclkcmpsq1p(16)))) AND (NOT (sudi(7) XOR rclkcmpsq1p(17)))) AND (NOT (sudi(8) XOR rclkcmpsq1p(18)))) AND (NOT (sudi(9) XOR rclkcmpsq1p(19)))); + nlil00i <= (nlil0l OR nlil1O); + nlil00l <= (wire_w_lg_rgenericfifo32w(0) AND wire_nliOlO_w_lg_dataout544w(0)); + nlil00O <= (rgenericfifo OR wire_nliOlO_dataout); + nlil01i <= (((((((((wire_n011Oi_o(26) OR wire_n011Oi_o(25)) OR wire_n011Oi_o(11)) OR wire_n011Oi_o(8)) OR wire_n011Oi_o(7)) OR wire_n011Oi_o(4)) OR wire_n011Oi_o(14)) OR wire_n011Oi_o(13)) OR wire_n011Oi_o(2)) OR wire_n011Oi_o(1)); + nlil01O <= (rgenericfifo AND nli0il); + nlil0ii <= ((((((((((NOT (rclkcmpsq1n(0) XOR wire_nllOlO_data_out2(0))) AND (NOT (rclkcmpsq1n(1) XOR wire_nllOlO_data_out2(1)))) AND (NOT (rclkcmpsq1n(2) XOR wire_nllOlO_data_out2(2)))) AND (NOT (rclkcmpsq1n(3) XOR wire_nllOlO_data_out2(3)))) AND (NOT (rclkcmpsq1n(4) XOR wire_nllOlO_data_out2(4)))) AND (NOT (rclkcmpsq1n(5) XOR wire_nllOlO_data_out2(5)))) AND (NOT (rclkcmpsq1n(6) XOR wire_nllOlO_data_out2(6)))) AND (NOT (rclkcmpsq1n(7) XOR wire_nllOlO_data_out2(7)))) AND (NOT (rclkcmpsq1n(8) XOR wire_nllOlO_data_out2(8)))) AND (NOT (rclkcmpsq1n(9) XOR wire_nllOlO_data_out2(9)))); + nlil0il <= ((((((((((NOT (rclkcmpsq1p(0) XOR wire_nllOlO_data_out2(0))) AND (NOT (rclkcmpsq1p(1) XOR wire_nllOlO_data_out2(1)))) AND (NOT (rclkcmpsq1p(2) XOR wire_nllOlO_data_out2(2)))) AND (NOT (rclkcmpsq1p(3) XOR wire_nllOlO_data_out2(3)))) AND (NOT (rclkcmpsq1p(4) XOR wire_nllOlO_data_out2(4)))) AND (NOT (rclkcmpsq1p(5) XOR wire_nllOlO_data_out2(5)))) AND (NOT (rclkcmpsq1p(6) XOR wire_nllOlO_data_out2(6)))) AND (NOT (rclkcmpsq1p(7) XOR wire_nllOlO_data_out2(7)))) AND (NOT (rclkcmpsq1p(8) XOR wire_nllOlO_data_out2(8)))) AND (NOT (rclkcmpsq1p(9) XOR wire_nllOlO_data_out2(9)))); + nlil0iO <= (nlil0l OR nliliii); + nlil0lO <= ((((((((((NOT (rclkcmpsq1n(10) XOR wire_nllOll_data_out2(0))) AND (NOT (rclkcmpsq1n(11) XOR wire_nllOll_data_out2(1)))) AND (NOT (rclkcmpsq1n(12) XOR wire_nllOll_data_out2(2)))) AND (NOT (rclkcmpsq1n(13) XOR wire_nllOll_data_out2(3)))) AND (NOT (rclkcmpsq1n(14) XOR wire_nllOll_data_out2(4)))) AND (NOT (rclkcmpsq1n(15) XOR wire_nllOll_data_out2(5)))) AND (NOT (rclkcmpsq1n(16) XOR wire_nllOll_data_out2(6)))) AND (NOT (rclkcmpsq1n(17) XOR wire_nllOll_data_out2(7)))) AND (NOT (rclkcmpsq1n(18) XOR wire_nllOll_data_out2(8)))) AND (NOT (rclkcmpsq1n(19) XOR wire_nllOll_data_out2(9)))); + nlil0Oi <= ((((((((((NOT (rclkcmpsq1p(10) XOR wire_nllOll_data_out2(0))) AND (NOT (rclkcmpsq1p(11) XOR wire_nllOll_data_out2(1)))) AND (NOT (rclkcmpsq1p(12) XOR wire_nllOll_data_out2(2)))) AND (NOT (rclkcmpsq1p(13) XOR wire_nllOll_data_out2(3)))) AND (NOT (rclkcmpsq1p(14) XOR wire_nllOll_data_out2(4)))) AND (NOT (rclkcmpsq1p(15) XOR wire_nllOll_data_out2(5)))) AND (NOT (rclkcmpsq1p(16) XOR wire_nllOll_data_out2(6)))) AND (NOT (rclkcmpsq1p(17) XOR wire_nllOll_data_out2(7)))) AND (NOT (rclkcmpsq1p(18) XOR wire_nllOll_data_out2(8)))) AND (NOT (rclkcmpsq1p(19) XOR wire_nllOll_data_out2(9)))); + nlil10i <= (((((wire_n1i_w_lg_w_lg_w_lg_w_lg_nii0il1342w1343w1345w1346w(0) AND wire_n1i_w_lg_nii01O1347w(0)) AND wire_n1i_w_lg_nii01i1349w(0)) AND wire_n1i_w_lg_nii1OO1351w(0)) AND (NOT (wire_w_lg_rclkcmpinsertpad655w(0) XOR nii1Ol))) AND (NOT (rclkcmpinsertpad XOR nii01l))); + nlil10l <= (rgenericfifo AND wire_n1i_w_lg_nli0il643w(0)); + nlil10O <= (nli0il OR (wire_w_lg_rgenericfifo32w(0) AND wire_w_lg_nlil0iO547w(0))); + nlil11i <= ((wire_n1i_w_lg_w_lg_w_lg_w1400w1401w1402w1403w(0) AND (NOT (rclkcmpinsertpad XOR ni0OOi))) AND (NOT (wire_w_lg_rclkcmpinsertpad655w(0) XOR nii11i))); + nlil11l <= (((((wire_n1i_w_lg_w_lg_w_lg_w_lg_nii1ii1376w1377w1379w1380w(0) AND wire_n1i_w_lg_nii11l1381w(0)) AND wire_n1i_w_lg_ni0OOO1383w(0)) AND wire_n1i_w_lg_ni0OOl1385w(0)) AND (NOT (wire_w_lg_rclkcmpinsertpad655w(0) XOR ni0OOi))) AND (NOT (rclkcmpinsertpad XOR nii11i))); + nlil11O <= ((wire_n1i_w_lg_w_lg_w_lg_w1366w1367w1368w1369w(0) AND (NOT (rclkcmpinsertpad XOR nii1Ol))) AND (NOT (wire_w_lg_rclkcmpinsertpad655w(0) XOR nii01l))); + nlil1ii <= ((((wire_nl0O1i_o(8) OR wire_nl0O1i_o(6)) OR wire_nl0O1i_o(4)) OR wire_nl0O1i_o(2)) OR wire_nl0O1i_o(0)); + nlil1il <= (((((((wire_nl0Oii_o(10) OR wire_nl0Oii_o(9)) OR wire_nl0Oii_o(8)) OR wire_nl0Oii_o(7)) OR wire_nl0Oii_o(6)) OR wire_nl0Oii_o(5)) OR wire_nl0Oii_o(4)) OR wire_nl0Oii_o(3)); + nlil1iO <= (((((((((wire_nl0Oii_o(16) OR wire_nl0Oii_o(15)) OR wire_nl0Oii_o(14)) OR wire_nl0Oii_o(13)) OR wire_nl0Oii_o(12)) OR wire_nl0Oii_o(11)) OR wire_nl0Oii_o(10)) OR wire_nl0Oii_o(9)) OR wire_nl0Oii_o(8)) OR wire_nl0Oii_o(7)); + nlil1li <= (((wire_n1i_w_lg_niOOii1337w(0) AND wire_n1i_w_lg_niOO0l1338w(0)) AND niOO0i) AND niOO1O); + nlil1ll <= ((wire_w_lg_rgenericfifo32w(0) AND wire_n1i_w_lg_nlii0O548w(0)) OR nlil01O); + nlil1lO <= ((((((NOT wire_nli1iO_o(6)) AND (NOT (wire_nli1iO_o(1) XOR nlil01i))) AND (NOT (wire_nli1iO_o(2) XOR nlil1OO))) AND (NOT (wire_nli1iO_o(3) XOR nlil1Ol))) AND (NOT (wire_nli1iO_o(4) XOR wire_n011ll_o(1)))) AND (NOT (wire_nli1iO_o(5) XOR nlil1Oi))); + nlil1Oi <= ((((wire_n011Oi_o(30) OR wire_n011Oi_o(27)) OR wire_n011Oi_o(26)) OR wire_n011Oi_o(25)) OR wire_n011Oi_o(24)); + nlil1Ol <= ((((((((wire_n011Oi_o(30) OR wire_n011Oi_o(11)) OR wire_n011Oi_o(10)) OR wire_n011Oi_o(9)) OR wire_n011Oi_o(8)) OR wire_n011Oi_o(7)) OR wire_n011Oi_o(6)) OR wire_n011Oi_o(5)) OR wire_n011Oi_o(4)); + nlil1OO <= ((((wire_n011iO_o(13) OR wire_n011iO_o(7)) OR wire_n011iO_o(4)) OR wire_n011iO_o(2)) OR wire_n011iO_o(1)); + nlili0i <= ((((((((((NOT (rclkcmpsq1p(10) XOR ni0O1O)) AND (NOT (rclkcmpsq1p(11) XOR ni0O0i))) AND (NOT (rclkcmpsq1p(12) XOR ni0O0l))) AND (NOT (rclkcmpsq1p(13) XOR ni0O0O))) AND (NOT (rclkcmpsq1p(14) XOR ni0Oii))) AND (NOT (rclkcmpsq1p(15) XOR ni0Oil))) AND (NOT (rclkcmpsq1p(16) XOR ni0OiO))) AND (NOT (rclkcmpsq1p(17) XOR ni0Oli))) AND (NOT (rclkcmpsq1p(18) XOR ni0Oll))) AND (NOT (rclkcmpsq1p(19) XOR ni0OlO))); + nlili1i <= ((((((((((NOT (rclkcmpsq1n(0) XOR ni00Ol)) AND (NOT (rclkcmpsq1n(1) XOR ni0liO))) AND (NOT (rclkcmpsq1n(2) XOR ni0lli))) AND (NOT (rclkcmpsq1n(3) XOR ni0lll))) AND (NOT (rclkcmpsq1n(4) XOR ni0llO))) AND (NOT (rclkcmpsq1n(5) XOR ni0lOi))) AND (NOT (rclkcmpsq1n(6) XOR ni0lOl))) AND (NOT (rclkcmpsq1n(7) XOR ni0lOO))) AND (NOT (rclkcmpsq1n(8) XOR ni0O1i))) AND (NOT (rclkcmpsq1n(9) XOR ni0O1l))); + nlili1l <= ((((((((((NOT (rclkcmpsq1p(0) XOR ni00Ol)) AND (NOT (rclkcmpsq1p(1) XOR ni0liO))) AND (NOT (rclkcmpsq1p(2) XOR ni0lli))) AND (NOT (rclkcmpsq1p(3) XOR ni0lll))) AND (NOT (rclkcmpsq1p(4) XOR ni0llO))) AND (NOT (rclkcmpsq1p(5) XOR ni0lOi))) AND (NOT (rclkcmpsq1p(6) XOR ni0lOl))) AND (NOT (rclkcmpsq1p(7) XOR ni0lOO))) AND (NOT (rclkcmpsq1p(8) XOR ni0O1i))) AND (NOT (rclkcmpsq1p(9) XOR ni0O1l))); + nlili1O <= ((((((((((NOT (rclkcmpsq1n(10) XOR ni0O1O)) AND (NOT (rclkcmpsq1n(11) XOR ni0O0i))) AND (NOT (rclkcmpsq1n(12) XOR ni0O0l))) AND (NOT (rclkcmpsq1n(13) XOR ni0O0O))) AND (NOT (rclkcmpsq1n(14) XOR ni0Oii))) AND (NOT (rclkcmpsq1n(15) XOR ni0Oil))) AND (NOT (rclkcmpsq1n(16) XOR ni0OiO))) AND (NOT (rclkcmpsq1n(17) XOR ni0Oli))) AND (NOT (rclkcmpsq1n(18) XOR ni0Oll))) AND (NOT (rclkcmpsq1n(19) XOR ni0OlO))); + nliliii <= (nliO1i AND (nlii0i AND wire_w_lg_nliliil440w(0))); + nliliil <= (wire_nli1li_o OR (nlilOl AND nlil1lO)); + nliliiO <= (wire_w_lg_rmatchen438w(0) OR rgenericfifo); + nlilili <= (rmatchen OR rgenericfifo); + nlill0O <= (wire_n1li_dataout OR wire_n1iO_dataout); + nlillii <= (wire_n1O01i_o OR (n11O1i AND nlii01i)); + nlillil <= ((wire_nlO0OlO_w_lg_dataout2227w(0) AND wire_nlO0Oli_w_lg_w_lg_dataout2228w2229w(0)) AND (NOT (nli0O1O AND nli0O1l))); + nlillOi <= (wire_n1OllO_w_lg_o2549w(0) AND (wire_w_lg_nli0l0i2530w(0) AND wire_nii_w_lg_nlli0Oi2550w(0))); + nlillOl <= (((wire_w_lg_rrx_pipe_enable1942w(0) AND nli0ill) AND nli0iOi) AND nli0i0O); + nlillOO <= ((nliilOl AND wire_w_lg_nliiO0O726w(0)) AND nliilOi); + nlilO0l <= (dskwclksel(1) AND rmatchen); + nlilOil <= '0'; + nlilOiO <= (wire_w_lg_w_lg_w_lg_w_lg_rauto_speed_ena7w18w19w20w(0) OR (NOT (nlilOli14 XOR nlilOli13))); + nliO10l <= '1'; + nliO11i <= (((wire_w_lg_rauto_speed_ena7w(0) AND (nliO11l6 XOR nliO11l5)) AND n1O) OR rdwidth_rx); + nliO1il <= (wire_nlil_dataout OR soft_reset); + rdfifo_almost_empty <= wire_nll_dataout; + rdfifo_almost_full <= wire_ni_dataout; + rdfifo_empty <= wire_nli_dataout; + rdfifo_full <= wire_nlO_dataout; + rev_loop_data <= ( wire_niO1O_dataout & wire_niO1l_dataout & wire_niO1i_dataout & wire_nilOO_dataout & wire_nilOl_dataout & wire_nilOi_dataout & wire_nillO_dataout & wire_nilll_dataout & wire_nilli_dataout & wire_niliO_dataout & wire_nilil_dataout & wire_nilii_dataout & wire_nil0O_dataout & wire_nil0l_dataout & wire_nil0i_dataout & wire_nil1O_dataout & wire_nil1l_dataout & wire_nil1i_dataout & wire_niiOO_dataout & wire_niiOl_dataout); + skpos_det <= nlillil; + wire_w_dskwclksel_range33w(0) <= dskwclksel(1); + wire_w_rdel_threshold_range361w(0) <= rdel_threshold(3); + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nli0O0O61 <= nli0O0O62; + END IF; + if (now = 0 ns) then + nli0O0O61 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nli0O0O62 <= nli0O0O61; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliil1i59 <= nliil1i60; + END IF; + if (now = 0 ns) then + nliil1i59 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliil1i60 <= nliil1i59; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliil1l57 <= nliil1l58; + END IF; + if (now = 0 ns) then + nliil1l57 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliil1l58 <= nliil1l57; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliiOOi55 <= nliiOOi56; + END IF; + if (now = 0 ns) then + nliiOOi55 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliiOOi56 <= nliiOOi55; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliiOOl53 <= nliiOOl54; + END IF; + if (now = 0 ns) then + nliiOOl53 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliiOOl54 <= nliiOOl53; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliiOOO51 <= nliiOOO52; + END IF; + if (now = 0 ns) then + nliiOOO51 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliiOOO52 <= nliiOOO51; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlil01l49 <= nlil01l50; + END IF; + if (now = 0 ns) then + nlil01l49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlil01l50 <= nlil01l49; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlil0li47 <= nlil0li48; + END IF; + if (now = 0 ns) then + nlil0li47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlil0li48 <= nlil0li47; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlil0Ol45 <= nlil0Ol46; + END IF; + if (now = 0 ns) then + nlil0Ol45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlil0Ol46 <= nlil0Ol45; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlili0l43 <= nlili0l44; + END IF; + if (now = 0 ns) then + nlili0l43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlili0l44 <= nlili0l43; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilill41 <= nlilill42; + END IF; + if (now = 0 ns) then + nlilill41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilill42 <= nlilill41; + END IF; + END PROCESS; + wire_nlilill42_w_lg_w_lg_q405w406w(0) <= wire_nlilill42_w_lg_q405w(0) AND wire_w_rdel_threshold_range361w(0); + wire_nlilill42_w_lg_q405w(0) <= nlilill42 XOR nlilill41; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlililO39 <= nlililO40; + END IF; + if (now = 0 ns) then + nlililO39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlililO40 <= nlililO39; + END IF; + END PROCESS; + wire_nlililO40_w_lg_w_lg_q396w397w(0) <= wire_nlililO40_w_lg_q396w(0) AND ni1i0l; + wire_nlililO40_w_lg_q396w(0) <= nlililO40 XOR nlililO39; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliliOi37 <= nliliOi38; + END IF; + if (now = 0 ns) then + nliliOi37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliliOi38 <= nliliOi37; + END IF; + END PROCESS; + wire_nliliOi38_w_lg_w_lg_q369w370w(0) <= wire_nliliOi38_w_lg_q369w(0) AND ni1i1l; + wire_nliliOi38_w_lg_q369w(0) <= nliliOi38 XOR nliliOi37; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliliOl35 <= nliliOl36; + END IF; + if (now = 0 ns) then + nliliOl35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliliOl36 <= nliliOl35; + END IF; + END PROCESS; + wire_nliliOl36_w_lg_w_lg_q332w333w(0) <= wire_nliliOl36_w_lg_q332w(0) AND ni1i1O; + wire_nliliOl36_w_lg_q332w(0) <= nliliOl36 XOR nliliOl35; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliliOO33 <= nliliOO34; + END IF; + if (now = 0 ns) then + nliliOO33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliliOO34 <= nliliOO33; + END IF; + END PROCESS; + wire_nliliOO34_w_lg_w_lg_q166w167w(0) <= wire_nliliOO34_w_lg_q166w(0) AND wire_nlO1iO_dataout; + wire_nliliOO34_w_lg_q166w(0) <= nliliOO34 XOR nliliOO33; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill0l25 <= nlill0l26; + END IF; + if (now = 0 ns) then + nlill0l25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill0l26 <= nlill0l25; + END IF; + END PROCESS; + wire_nlill0l26_w_lg_w_lg_q124w125w(0) <= wire_nlill0l26_w_lg_q124w(0) AND nllOOl; + wire_nlill0l26_w_lg_q124w(0) <= nlill0l26 XOR nlill0l25; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill1i31 <= nlill1i32; + END IF; + if (now = 0 ns) then + nlill1i31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill1i32 <= nlill1i31; + END IF; + END PROCESS; + wire_nlill1i32_w_lg_w_lg_q155w156w(0) <= wire_nlill1i32_w_lg_q155w(0) AND wire_nlO10l_dataout; + wire_nlill1i32_w_lg_q155w(0) <= nlill1i32 XOR nlill1i31; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill1l29 <= nlill1l30; + END IF; + if (now = 0 ns) then + nlill1l29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill1l30 <= nlill1l29; + END IF; + END PROCESS; + wire_nlill1l30_w_lg_w_lg_q152w153w(0) <= wire_nlill1l30_w_lg_q152w(0) AND nllOOi; + wire_nlill1l30_w_lg_q152w(0) <= nlill1l30 XOR nlill1l29; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill1O27 <= nlill1O28; + END IF; + if (now = 0 ns) then + nlill1O27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlill1O28 <= nlill1O27; + END IF; + END PROCESS; + wire_nlill1O28_w_lg_q140w(0) <= nlill1O28 XOR nlill1O27; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilliO23 <= nlilliO24; + END IF; + if (now = 0 ns) then + nlilliO23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilliO24 <= nlilliO23; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlillll21 <= nlillll22; + END IF; + if (now = 0 ns) then + nlillll21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlillll22 <= nlillll21; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilO0O15 <= nlilO0O16; + END IF; + if (now = 0 ns) then + nlilO0O15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilO0O16 <= nlilO0O15; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilO1i19 <= nlilO1i20; + END IF; + if (now = 0 ns) then + nlilO1i19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilO1i20 <= nlilO1i19; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilO1O17 <= nlilO1O18; + END IF; + if (now = 0 ns) then + nlilO1O17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilO1O18 <= nlilO1O17; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOli13 <= nlilOli14; + END IF; + if (now = 0 ns) then + nlilOli13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOli14 <= nlilOli13; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOlO11 <= nlilOlO12; + END IF; + if (now = 0 ns) then + nlilOlO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOlO12 <= nlilOlO11; + END IF; + END PROCESS; + wire_nlilOlO12_w_lg_q17w(0) <= nlilOlO12 XOR nlilOlO11; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOOl10 <= nlilOOl9; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOOl9 <= nlilOOl10; + END IF; + if (now = 0 ns) then + nlilOOl9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOOO7 <= nlilOOO8; + END IF; + if (now = 0 ns) then + nlilOOO7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nlilOOO8 <= nlilOOO7; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliO10i3 <= nliO10i4; + END IF; + if (now = 0 ns) then + nliO10i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliO10i4 <= nliO10i3; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliO11l5 <= nliO11l6; + END IF; + if (now = 0 ns) then + nliO11l5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliO11l6 <= nliO11l5; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliO1iO1 <= nliO1iO2; + END IF; + if (now = 0 ns) then + nliO1iO1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN nliO1iO2 <= nliO1iO1; + END IF; + END PROCESS; + PROCESS (clk_2, wire_n1i_PRN, wire_n1i_CLRN) + BEGIN + IF (wire_n1i_PRN = '0') THEN + n0111i <= '1'; + n0111l <= '1'; + n1000i <= '1'; + n1000l <= '1'; + n1000O <= '1'; + n1001i <= '1'; + n1001l <= '1'; + n1001O <= '1'; + n100ii <= '1'; + n100il <= '1'; + n100li <= '1'; + n100ll <= '1'; + n100lO <= '1'; + n100Oi <= '1'; + n100Ol <= '1'; + n100OO <= '1'; + n101Ol <= '1'; + n101OO <= '1'; + n10i0i <= '1'; + n10i0l <= '1'; + n10i0O <= '1'; + n10i1i <= '1'; + n10i1l <= '1'; + n10i1O <= '1'; + n10iii <= '1'; + n10iil <= '1'; + n10iiO <= '1'; + n10ili <= '1'; + n10ill <= '1'; + n10ilO <= '1'; + n10iOl <= '1'; + n10iOO <= '1'; + n10l0i <= '1'; + n10l0l <= '1'; + n10l0O <= '1'; + n10l1i <= '1'; + n10l1l <= '1'; + n10l1O <= '1'; + n10lii <= '1'; + n10lil <= '1'; + n10liO <= '1'; + n10lli <= '1'; + n10lll <= '1'; + n10llO <= '1'; + n10lOi <= '1'; + n10lOl <= '1'; + n10lOO <= '1'; + n10O1i <= '1'; + n10O1l <= '1'; + n10O1O <= '1'; + n110iO <= '1'; + n110li <= '1'; + n110ll <= '1'; + n110lO <= '1'; + n11iil <= '1'; + n11iiO <= '1'; + n11ili <= '1'; + n11ill <= '1'; + n11ilO <= '1'; + n11iOi <= '1'; + n11iOl <= '1'; + n11iOO <= '1'; + n11O0i <= '1'; + n11O0l <= '1'; + n11O0O <= '1'; + n11O1i <= '1'; + n11O1l <= '1'; + n11O1O <= '1'; + n1l <= '1'; + n1liil <= '1'; + n1liiO <= '1'; + n1lili <= '1'; + n1ll1i <= '1'; + n1ll1l <= '1'; + n1O00i <= '1'; + n1O00l <= '1'; + n1O01l <= '1'; + n1O01O <= '1'; + ni0OOi <= '1'; + ni0OOl <= '1'; + ni0OOO <= '1'; + nii00i <= '1'; + nii00l <= '1'; + nii00O <= '1'; + nii01i <= '1'; + nii01l <= '1'; + nii01O <= '1'; + nii0ii <= '1'; + nii0il <= '1'; + nii0iO <= '1'; + nii0ll <= '1'; + nii0Ol <= '1'; + nii0OO <= '1'; + nii10i <= '1'; + nii10l <= '1'; + nii10O <= '1'; + nii11i <= '1'; + nii11l <= '1'; + nii11O <= '1'; + nii1ii <= '1'; + nii1il <= '1'; + nii1iO <= '1'; + nii1li <= '1'; + nii1ll <= '1'; + nii1lO <= '1'; + nii1Oi <= '1'; + nii1Ol <= '1'; + nii1OO <= '1'; + niii1i <= '1'; + niOlOl <= '1'; + niOlOO <= '1'; + niOO0i <= '1'; + niOO0l <= '1'; + niOO0O <= '1'; + niOO1i <= '1'; + niOO1l <= '1'; + niOO1O <= '1'; + niOOii <= '1'; + niOOil <= '1'; + niOOli <= '1'; + niOOll <= '1'; + niOOlO <= '1'; + niOOOi <= '1'; + niOOOl <= '1'; + niOOOO <= '1'; + nl100i <= '1'; + nl100l <= '1'; + nl100O <= '1'; + nl101i <= '1'; + nl101l <= '1'; + nl101O <= '1'; + nl10ii <= '1'; + nl10il <= '1'; + nl10iO <= '1'; + nl10li <= '1'; + nl10ll <= '1'; + nl10lO <= '1'; + nl10Oi <= '1'; + nl10Ol <= '1'; + nl10OO <= '1'; + nl110i <= '1'; + nl110l <= '1'; + nl110O <= '1'; + nl111i <= '1'; + nl111l <= '1'; + nl111O <= '1'; + nl11ii <= '1'; + nl11il <= '1'; + nl11iO <= '1'; + nl11li <= '1'; + nl11ll <= '1'; + nl11lO <= '1'; + nl11OO <= '1'; + nl1i0i <= '1'; + nl1i1i <= '1'; + nl1i1l <= '1'; + nl1i1O <= '1'; + nli0il <= '1'; + nli0Ol <= '1'; + nli0OO <= '1'; + nli1ll <= '1'; + nli1lO <= '1'; + nli1Oi <= '1'; + nli1Ol <= '1'; + nlii0i <= '1'; + nlii0l <= '1'; + nlii0O <= '1'; + nlii1i <= '1'; + nlii1l <= '1'; + nliilO <= '1'; + nliiOi <= '1'; + nlil0i <= '1'; + nlil0l <= '1'; + nlil0O <= '1'; + nlil1O <= '1'; + nlilOl <= '1'; + nliO01l <= '1'; + nliO01O <= '1'; + nliO1i <= '1'; + nlll <= '1'; + nlO00OO <= '1'; + nlOi1iO <= '1'; + nlOiO0i <= '1'; + nlOiO0l <= '1'; + nlOiO0O <= '1'; + nlOiO1O <= '1'; + nlOiOii <= '1'; + nlOl0OO <= '1'; + nlOli0i <= '1'; + nlOli0l <= '1'; + nlOli0O <= '1'; + nlOli1i <= '1'; + nlOli1l <= '1'; + nlOli1O <= '1'; + nlOliii <= '1'; + nlOliil <= '1'; + nlOliiO <= '1'; + nlOlili <= '1'; + nlOlilO <= '1'; + nlOliOO <= '1'; + nlOll1i <= '1'; + nlOll1l <= '1'; + ELSIF (wire_n1i_CLRN = '0') THEN + n0111i <= '0'; + n0111l <= '0'; + n1000i <= '0'; + n1000l <= '0'; + n1000O <= '0'; + n1001i <= '0'; + n1001l <= '0'; + n1001O <= '0'; + n100ii <= '0'; + n100il <= '0'; + n100li <= '0'; + n100ll <= '0'; + n100lO <= '0'; + n100Oi <= '0'; + n100Ol <= '0'; + n100OO <= '0'; + n101Ol <= '0'; + n101OO <= '0'; + n10i0i <= '0'; + n10i0l <= '0'; + n10i0O <= '0'; + n10i1i <= '0'; + n10i1l <= '0'; + n10i1O <= '0'; + n10iii <= '0'; + n10iil <= '0'; + n10iiO <= '0'; + n10ili <= '0'; + n10ill <= '0'; + n10ilO <= '0'; + n10iOl <= '0'; + n10iOO <= '0'; + n10l0i <= '0'; + n10l0l <= '0'; + n10l0O <= '0'; + n10l1i <= '0'; + n10l1l <= '0'; + n10l1O <= '0'; + n10lii <= '0'; + n10lil <= '0'; + n10liO <= '0'; + n10lli <= '0'; + n10lll <= '0'; + n10llO <= '0'; + n10lOi <= '0'; + n10lOl <= '0'; + n10lOO <= '0'; + n10O1i <= '0'; + n10O1l <= '0'; + n10O1O <= '0'; + n110iO <= '0'; + n110li <= '0'; + n110ll <= '0'; + n110lO <= '0'; + n11iil <= '0'; + n11iiO <= '0'; + n11ili <= '0'; + n11ill <= '0'; + n11ilO <= '0'; + n11iOi <= '0'; + n11iOl <= '0'; + n11iOO <= '0'; + n11O0i <= '0'; + n11O0l <= '0'; + n11O0O <= '0'; + n11O1i <= '0'; + n11O1l <= '0'; + n11O1O <= '0'; + n1l <= '0'; + n1liil <= '0'; + n1liiO <= '0'; + n1lili <= '0'; + n1ll1i <= '0'; + n1ll1l <= '0'; + n1O00i <= '0'; + n1O00l <= '0'; + n1O01l <= '0'; + n1O01O <= '0'; + ni0OOi <= '0'; + ni0OOl <= '0'; + ni0OOO <= '0'; + nii00i <= '0'; + nii00l <= '0'; + nii00O <= '0'; + nii01i <= '0'; + nii01l <= '0'; + nii01O <= '0'; + nii0ii <= '0'; + nii0il <= '0'; + nii0iO <= '0'; + nii0ll <= '0'; + nii0Ol <= '0'; + nii0OO <= '0'; + nii10i <= '0'; + nii10l <= '0'; + nii10O <= '0'; + nii11i <= '0'; + nii11l <= '0'; + nii11O <= '0'; + nii1ii <= '0'; + nii1il <= '0'; + nii1iO <= '0'; + nii1li <= '0'; + nii1ll <= '0'; + nii1lO <= '0'; + nii1Oi <= '0'; + nii1Ol <= '0'; + nii1OO <= '0'; + niii1i <= '0'; + niOlOl <= '0'; + niOlOO <= '0'; + niOO0i <= '0'; + niOO0l <= '0'; + niOO0O <= '0'; + niOO1i <= '0'; + niOO1l <= '0'; + niOO1O <= '0'; + niOOii <= '0'; + niOOil <= '0'; + niOOli <= '0'; + niOOll <= '0'; + niOOlO <= '0'; + niOOOi <= '0'; + niOOOl <= '0'; + niOOOO <= '0'; + nl100i <= '0'; + nl100l <= '0'; + nl100O <= '0'; + nl101i <= '0'; + nl101l <= '0'; + nl101O <= '0'; + nl10ii <= '0'; + nl10il <= '0'; + nl10iO <= '0'; + nl10li <= '0'; + nl10ll <= '0'; + nl10lO <= '0'; + nl10Oi <= '0'; + nl10Ol <= '0'; + nl10OO <= '0'; + nl110i <= '0'; + nl110l <= '0'; + nl110O <= '0'; + nl111i <= '0'; + nl111l <= '0'; + nl111O <= '0'; + nl11ii <= '0'; + nl11il <= '0'; + nl11iO <= '0'; + nl11li <= '0'; + nl11ll <= '0'; + nl11lO <= '0'; + nl11OO <= '0'; + nl1i0i <= '0'; + nl1i1i <= '0'; + nl1i1l <= '0'; + nl1i1O <= '0'; + nli0il <= '0'; + nli0Ol <= '0'; + nli0OO <= '0'; + nli1ll <= '0'; + nli1lO <= '0'; + nli1Oi <= '0'; + nli1Ol <= '0'; + nlii0i <= '0'; + nlii0l <= '0'; + nlii0O <= '0'; + nlii1i <= '0'; + nlii1l <= '0'; + nliilO <= '0'; + nliiOi <= '0'; + nlil0i <= '0'; + nlil0l <= '0'; + nlil0O <= '0'; + nlil1O <= '0'; + nlilOl <= '0'; + nliO01l <= '0'; + nliO01O <= '0'; + nliO1i <= '0'; + nlll <= '0'; + nlO00OO <= '0'; + nlOi1iO <= '0'; + nlOiO0i <= '0'; + nlOiO0l <= '0'; + nlOiO0O <= '0'; + nlOiO1O <= '0'; + nlOiOii <= '0'; + nlOl0OO <= '0'; + nlOli0i <= '0'; + nlOli0l <= '0'; + nlOli0O <= '0'; + nlOli1i <= '0'; + nlOli1l <= '0'; + nlOli1O <= '0'; + nlOliii <= '0'; + nlOliil <= '0'; + nlOliiO <= '0'; + nlOlili <= '0'; + nlOlilO <= '0'; + nlOliOO <= '0'; + nlOll1i <= '0'; + nlOll1l <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n0111i <= wire_n0110i_dataout; + n0111l <= wire_n0110l_dataout; + n1000i <= wire_n10Oli_dataout; + n1000l <= wire_n10Oll_dataout; + n1000O <= wire_n10OlO_dataout; + n1001i <= wire_n10Oii_dataout; + n1001l <= wire_n10Oil_dataout; + n1001O <= wire_n10OiO_dataout; + n100ii <= wire_n10OOi_dataout; + n100il <= wire_n10OOl_dataout; + n100li <= wire_n1i11i_dataout; + n100ll <= wire_n1i11l_dataout; + n100lO <= wire_n1i11O_dataout; + n100Oi <= wire_n1i10i_dataout; + n100Ol <= wire_n1i10l_dataout; + n100OO <= wire_n1i10O_dataout; + n101Ol <= wire_n10O0l_dataout; + n101OO <= wire_n10O0O_dataout; + n10i0i <= wire_n1i1li_dataout; + n10i0l <= wire_n1i1ll_dataout; + n10i0O <= wire_n1i1lO_dataout; + n10i1i <= wire_n1i1ii_dataout; + n10i1l <= wire_n1i1il_dataout; + n10i1O <= wire_n1i1iO_dataout; + n10iii <= wire_n1i1Oi_dataout; + n10iil <= wire_n1i1Ol_dataout; + n10iiO <= wire_n1i1OO_dataout; + n10ili <= wire_n1i01i_dataout; + n10ill <= wire_n1i01l_dataout; + n10ilO <= wire_n1i01O_dataout; + n10iOl <= wire_n1i00l_dataout; + n10iOO <= wire_n1i00O_dataout; + n10l0i <= wire_n1i0li_dataout; + n10l0l <= wire_n1i0ll_dataout; + n10l0O <= wire_n1i0lO_dataout; + n10l1i <= wire_n1i0ii_dataout; + n10l1l <= wire_n1i0il_dataout; + n10l1O <= wire_n1i0iO_dataout; + n10lii <= wire_n1i0Oi_dataout; + n10lil <= wire_n1i0Ol_dataout; + n10liO <= wire_n1i0OO_dataout; + n10lli <= wire_n1ii1i_dataout; + n10lll <= wire_n1ii1l_dataout; + n10llO <= wire_n1ii1O_dataout; + n10lOi <= wire_n1ii0i_dataout; + n10lOl <= wire_n1ii0l_dataout; + n10lOO <= wire_n1ii0O_dataout; + n10O1i <= wire_n1iiii_dataout; + n10O1l <= wire_n1iiil_dataout; + n10O1O <= wire_n1lill_dataout; + n110iO <= n110ll; + n110li <= wire_n110Oi_dataout; + n110ll <= wire_n110Ol_dataout; + n110lO <= wire_n11l1i_dataout; + n11iil <= wire_n11l1l_dataout; + n11iiO <= wire_n11l1O_dataout; + n11ili <= wire_n11l0i_dataout; + n11ill <= wire_n11l0l_dataout; + n11ilO <= wire_n11l0O_dataout; + n11iOi <= wire_n11lii_dataout; + n11iOl <= wire_n11lil_dataout; + n11iOO <= wire_n101iO_dataout; + n11O0i <= wire_n11Oil_dataout; + n11O0l <= wire_n11OiO_dataout; + n11O0O <= wire_n10O0i_dataout; + n11O1i <= wire_n101ll_dataout; + n11O1l <= wire_n101li_dataout; + n11O1O <= wire_n11Oii_dataout; + n1l <= wire_niO_dataout; + n1liil <= wire_n1lilO_dataout; + n1liiO <= wire_n1liOi_dataout; + n1lili <= n1ll1i; + n1ll1i <= (wire_w_lg_rgenericfifo32w(0) AND nlO1Oii); + n1ll1l <= wire_n1O0il_dataout; + n1O00i <= wire_n1O0ll_dataout; + n1O00l <= wire_n1O0lO_dataout; + n1O01l <= wire_n1O0iO_dataout; + n1O01O <= wire_n1O0li_dataout; + ni0OOi <= wire_niii1l_dataout; + ni0OOl <= wire_niii1O_dataout; + ni0OOO <= wire_niii0i_dataout; + nii00i <= wire_niilil_dataout; + nii00l <= wire_niiliO_dataout; + nii00O <= wire_niilli_dataout; + nii01i <= wire_niil0l_dataout; + nii01l <= wire_niil0O_dataout; + nii01O <= wire_niilii_dataout; + nii0ii <= wire_niilll_dataout; + nii0il <= wire_niillO_dataout; + nii0iO <= wire_niilOi_dataout; + nii0ll <= wire_niilOl_dataout; + nii0Ol <= wire_niilOO_dataout; + nii0OO <= wire_niiO1i_dataout; + nii10i <= wire_niiiil_dataout; + nii10l <= wire_niiiiO_dataout; + nii10O <= wire_niiili_dataout; + nii11i <= wire_niii0l_dataout; + nii11l <= wire_niii0O_dataout; + nii11O <= wire_niiiii_dataout; + nii1ii <= wire_niiill_dataout; + nii1il <= wire_niiilO_dataout; + nii1iO <= wire_niiiOi_dataout; + nii1li <= wire_niiiOl_dataout; + nii1ll <= wire_niiiOO_dataout; + nii1lO <= wire_niil1i_dataout; + nii1Oi <= wire_niil1l_dataout; + nii1Ol <= wire_niil1O_dataout; + nii1OO <= wire_niil0i_dataout; + niii1i <= wire_nl1i0l_dataout; + niOlOl <= wire_nl1i0O_dataout; + niOlOO <= wire_nl1iii_dataout; + niOO0i <= wire_nl1ill_dataout; + niOO0l <= wire_nl1ilO_dataout; + niOO0O <= wire_nl1iOi_dataout; + niOO1i <= wire_nl1iil_dataout; + niOO1l <= wire_nl1iiO_dataout; + niOO1O <= wire_nl1ili_dataout; + niOOii <= wire_nl1iOl_dataout; + niOOil <= wire_nl1iOO_dataout; + niOOli <= wire_nl1l1l_dataout; + niOOll <= wire_nl1l1O_dataout; + niOOlO <= wire_nl1l0i_dataout; + niOOOi <= wire_nl1l0l_dataout; + niOOOl <= wire_nl1l0O_dataout; + niOOOO <= wire_nl1lii_dataout; + nl100i <= wire_nl1Oli_dataout; + nl100l <= wire_nl1Oll_dataout; + nl100O <= wire_nl1OlO_dataout; + nl101i <= wire_nl1Oii_dataout; + nl101l <= wire_nl1Oil_dataout; + nl101O <= wire_nl1OiO_dataout; + nl10ii <= wire_nl1OOi_dataout; + nl10il <= wire_nl1OOl_dataout; + nl10iO <= wire_nl1OOO_dataout; + nl10li <= wire_nl011i_dataout; + nl10ll <= wire_nl011l_dataout; + nl10lO <= wire_nl011O_dataout; + nl10Oi <= wire_nl010i_dataout; + nl10Ol <= wire_nl010l_dataout; + nl10OO <= wire_nl010O_dataout; + nl110i <= wire_nl1lll_dataout; + nl110l <= wire_nl1llO_dataout; + nl110O <= wire_nl1lOi_dataout; + nl111i <= wire_nl1lil_dataout; + nl111l <= wire_nl1liO_dataout; + nl111O <= wire_nl1lli_dataout; + nl11ii <= wire_nl1lOl_dataout; + nl11il <= wire_nl1lOO_dataout; + nl11iO <= wire_nl1O1i_dataout; + nl11li <= wire_nl1O1l_dataout; + nl11ll <= wire_nl1O1O_dataout; + nl11lO <= wire_nl1O0i_dataout; + nl11OO <= wire_nl1O0O_dataout; + nl1i0i <= wire_nli01O_dataout; + nl1i1i <= wire_nl01ii_dataout; + nl1i1l <= wire_nl01il_dataout; + nl1i1O <= wire_nl01iO_dataout; + nli0il <= nli0Ol; + nli0Ol <= (rgenericfifo AND rdenable); + nli0OO <= nlii1i; + nli1ll <= wire_nli00i_dataout; + nli1lO <= wire_nli00l_dataout; + nli1Oi <= wire_nli00O_dataout; + nli1Ol <= wire_nli0ii_dataout; + nlii0i <= wire_nliiil_dataout; + nlii0l <= wire_nliiiO_dataout; + nlii0O <= nliilO; + nlii1i <= sync_status; + nlii1l <= wire_nliiii_dataout; + nliilO <= (wire_w_lg_rgenericfifo32w(0) AND n0Ol0O); + nliiOi <= nlil1O; + nlil0i <= wire_nlilii_dataout; + nlil0l <= wire_nlilil_dataout; + nlil0O <= wire_nlilOO_dataout; + nlil1O <= nlil0l; + nlilOl <= wire_nliO0i_dataout; + nliO01l <= wire_nliO00l_dataout; + nliO01O <= wire_nliO00O_dataout; + nliO1i <= wire_nliO1O_dataout; + nlll <= n1l; + nlO00OO <= wire_nlOi1li_dataout; + nlOi1iO <= nlOiO1O; + nlOiO0i <= nlOiO0l; + nlOiO0l <= sync_status; + nlOiO0O <= nlOiOii; + nlOiO1O <= (rgenericfifo AND rdenable); + nlOiOii <= align_status; + nlOl0OO <= wire_nlOll1O_dataout; + nlOli0i <= wire_nlOllii_dataout; + nlOli0l <= wire_nlOllil_dataout; + nlOli0O <= wire_nlOlliO_dataout; + nlOli1i <= wire_nlOll0i_dataout; + nlOli1l <= wire_nlOll0l_dataout; + nlOli1O <= wire_nlOll0O_dataout; + nlOliii <= wire_nlOllli_dataout; + nlOliil <= wire_nlOllll_dataout; + nlOliiO <= wire_nlOlllO_dataout; + nlOlili <= wire_nlOllOi_dataout; + nlOlilO <= wire_nlOllOl_dataout; + nlOliOO <= wire_nlOllOO_dataout; + nlOll1i <= wire_nlOlO1i_dataout; + nlOll1l <= n110iO; + END IF; + END PROCESS; + wire_n1i_CLRN <= ((nlilOOO8 XOR nlilOOO7) AND wire_w_lg_nliO1il2w(0)); + wire_n1i_PRN <= (nlilOOl10 XOR nlilOOl9); + wire_n1i_w_lg_w_lg_w_lg_w1366w1367w1368w1369w(0) <= wire_n1i_w_lg_w_lg_w1366w1367w1368w(0) AND nii1OO; + wire_n1i_w_lg_w_lg_w_lg_w1400w1401w1402w1403w(0) <= wire_n1i_w_lg_w_lg_w1400w1401w1402w(0) AND ni0OOl; + wire_n1i_w_lg_w_lg_w1366w1367w1368w(0) <= wire_n1i_w_lg_w1366w1367w(0) AND nii01i; + wire_n1i_w_lg_w_lg_w1400w1401w1402w(0) <= wire_n1i_w_lg_w1400w1401w(0) AND ni0OOO; + wire_n1i_w_lg_w1366w1367w(0) <= wire_n1i_w1366w(0) AND nii01O; + wire_n1i_w_lg_w1400w1401w(0) <= wire_n1i_w1400w(0) AND nii11l; + wire_n1i_w1366w(0) <= wire_n1i_w_lg_w_lg_w_lg_w_lg_nii0il1359w1361w1363w1364w(0) AND wire_n1i_w_lg_nii00i1365w(0); + wire_n1i_w1400w(0) <= wire_n1i_w_lg_w_lg_w_lg_w_lg_nii1ii1393w1395w1397w1398w(0) AND wire_n1i_w_lg_nii11O1399w(0); + wire_n1i_w_lg_w_lg_w_lg_w_lg_nii0il1342w1343w1345w1346w(0) <= wire_n1i_w_lg_w_lg_w_lg_nii0il1342w1343w1345w(0) AND nii00i; + wire_n1i_w_lg_w_lg_w_lg_w_lg_nii1ii1376w1377w1379w1380w(0) <= wire_n1i_w_lg_w_lg_w_lg_nii1ii1376w1377w1379w(0) AND nii11O; + wire_n1i_w_lg_w_lg_w_lg_w_lg_nii0il1359w1361w1363w1364w(0) <= wire_n1i_w_lg_w_lg_w_lg_nii0il1359w1361w1363w(0) AND nii00l; + wire_n1i_w_lg_w_lg_w_lg_w_lg_nii1ii1393w1395w1397w1398w(0) <= wire_n1i_w_lg_w_lg_w_lg_nii1ii1393w1395w1397w(0) AND nii10i; + wire_n1i_w_lg_w_lg_w_lg_nii0il1342w1343w1345w(0) <= wire_n1i_w_lg_w_lg_nii0il1342w1343w(0) AND wire_n1i_w_lg_nii00l1344w(0); + wire_n1i_w_lg_w_lg_w_lg_nii1ii1376w1377w1379w(0) <= wire_n1i_w_lg_w_lg_nii1ii1376w1377w(0) AND wire_n1i_w_lg_nii10i1378w(0); + wire_n1i_w_lg_w_lg_w_lg_nii0il1359w1361w1363w(0) <= wire_n1i_w_lg_w_lg_nii0il1359w1361w(0) AND wire_n1i_w_lg_nii00O1362w(0); + wire_n1i_w_lg_w_lg_w_lg_nii1ii1393w1395w1397w(0) <= wire_n1i_w_lg_w_lg_nii1ii1393w1395w(0) AND wire_n1i_w_lg_nii10l1396w(0); + wire_n1i_w_lg_w_lg_nii0il1342w1343w(0) <= wire_n1i_w_lg_nii0il1342w(0) AND nii00O; + wire_n1i_w_lg_w_lg_nii1ii1376w1377w(0) <= wire_n1i_w_lg_nii1ii1376w(0) AND nii10l; + wire_n1i_w_lg_w_lg_nii0il1359w1361w(0) <= wire_n1i_w_lg_nii0il1359w(0) AND wire_n1i_w_lg_nii0ii1360w(0); + wire_n1i_w_lg_w_lg_nii1ii1393w1395w(0) <= wire_n1i_w_lg_nii1ii1393w(0) AND wire_n1i_w_lg_nii10O1394w(0); + wire_n1i_w_lg_w_lg_nlilOl458w459w(0) <= wire_n1i_w_lg_nlilOl458w(0) AND nlil0O; + wire_n1i_w_lg_n100ii3078w(0) <= n100ii AND wire_n1i_w_lg_n1000O3077w(0); + wire_n1i_w_lg_n1liil2156w(0) <= n1liil AND wire_w_lg_w_lg_nlillii120w2155w(0); + wire_n1i_w_lg_nii0il1342w(0) <= nii0il AND nii0ii; + wire_n1i_w_lg_nii1ii1376w(0) <= nii1ii AND nii10O; + wire_n1i_w_lg_niOOii1337w(0) <= niOOii AND wire_n1i_w_lg_niOO0O1336w(0); + wire_n1i_w_lg_nlii0O548w(0) <= nlii0O AND wire_w_lg_nlil0iO547w(0); + wire_n1i_w_lg_n1000l3079w(0) <= NOT n1000l; + wire_n1i_w_lg_n1000O3077w(0) <= NOT n1000O; + wire_n1i_w_lg_n110iO2150w(0) <= NOT n110iO; + wire_n1i_w_lg_n110li2133w(0) <= NOT n110li; + wire_n1i_w_lg_n110ll2151w(0) <= NOT n110ll; + wire_n1i_w_lg_n110lO3096w(0) <= NOT n110lO; + wire_n1i_w_lg_n11iil3094w(0) <= NOT n11iil; + wire_n1i_w_lg_n11iiO3092w(0) <= NOT n11iiO; + wire_n1i_w_lg_n11ili3090w(0) <= NOT n11ili; + wire_n1i_w_lg_n11ill3088w(0) <= NOT n11ill; + wire_n1i_w_lg_n11ilO3086w(0) <= NOT n11ilO; + wire_n1i_w_lg_n11iOi3084w(0) <= NOT n11iOi; + wire_n1i_w_lg_n11iOl3083w(0) <= NOT n11iOl; + wire_n1i_w_lg_n11iOO1969w(0) <= NOT n11iOO; + wire_n1i_w_lg_n11O0i2094w(0) <= NOT n11O0i; + wire_n1i_w_lg_n11O0l2093w(0) <= NOT n11O0l; + wire_n1i_w_lg_n11O1i1953w(0) <= NOT n11O1i; + wire_n1i_w_lg_n11O1l2088w(0) <= NOT n11O1l; + wire_n1i_w_lg_n11O1O2096w(0) <= NOT n11O1O; + wire_n1i_w_lg_ni0OOl1385w(0) <= NOT ni0OOl; + wire_n1i_w_lg_ni0OOO1383w(0) <= NOT ni0OOO; + wire_n1i_w_lg_nii00i1365w(0) <= NOT nii00i; + wire_n1i_w_lg_nii00l1344w(0) <= NOT nii00l; + wire_n1i_w_lg_nii00O1362w(0) <= NOT nii00O; + wire_n1i_w_lg_nii01i1349w(0) <= NOT nii01i; + wire_n1i_w_lg_nii01O1347w(0) <= NOT nii01O; + wire_n1i_w_lg_nii0ii1360w(0) <= NOT nii0ii; + wire_n1i_w_lg_nii0il1359w(0) <= NOT nii0il; + wire_n1i_w_lg_nii10i1378w(0) <= NOT nii10i; + wire_n1i_w_lg_nii10l1396w(0) <= NOT nii10l; + wire_n1i_w_lg_nii10O1394w(0) <= NOT nii10O; + wire_n1i_w_lg_nii11l1381w(0) <= NOT nii11l; + wire_n1i_w_lg_nii11O1399w(0) <= NOT nii11O; + wire_n1i_w_lg_nii1ii1393w(0) <= NOT nii1ii; + wire_n1i_w_lg_nii1OO1351w(0) <= NOT nii1OO; + wire_n1i_w_lg_niOO0l1338w(0) <= NOT niOO0l; + wire_n1i_w_lg_niOO0O1336w(0) <= NOT niOO0O; + wire_n1i_w_lg_nli0il643w(0) <= NOT nli0il; + wire_n1i_w_lg_nlil0i484w(0) <= NOT nlil0i; + wire_n1i_w_lg_nlil0l722w(0) <= NOT nlil0l; + wire_n1i_w_lg_nlilOl458w(0) <= NOT nlilOl; + wire_n1i_w_lg_nlOi1iO2144w(0) <= NOT nlOi1iO; + PROCESS (clk_1, wire_ni11Oi_PRN, wire_ni11Oi_CLRN) + BEGIN + IF (wire_ni11Oi_PRN = '0') THEN + n0l0iO <= '1'; + ni11ll <= '1'; + ni11lO <= '1'; + ni11Ol <= '1'; + nlliiOO <= '1'; + nllil1i <= '1'; + nllil1l <= '1'; + nlllO0l <= '1'; + ELSIF (wire_ni11Oi_CLRN = '0') THEN + n0l0iO <= '0'; + ni11ll <= '0'; + ni11lO <= '0'; + ni11Ol <= '0'; + nlliiOO <= '0'; + nllil1i <= '0'; + nllil1l <= '0'; + nlllO0l <= '0'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + n0l0iO <= wire_n0ll0l_dataout; + ni11ll <= wire_ni100i_dataout; + ni11lO <= wire_ni100l_dataout; + ni11Ol <= wire_ni100O_dataout; + nlliiOO <= wire_nllilii_dataout; + nllil1i <= wire_nllilil_dataout; + nllil1l <= wire_nlliliO_dataout; + nlllO0l <= wire_nllO01i_dataout; + END IF; + if (now = 0 ns) then + n0l0iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni11ll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni11lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni11Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliiOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllil1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllil1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlllO0l <= '1' after 1 ps; + end if; + END PROCESS; + wire_ni11Oi_CLRN <= (nliil1l58 XOR nliil1l57); + wire_ni11Oi_PRN <= ((nliil1i60 XOR nliil1i59) AND wire_nl0i_w_lg_dataout4w(0)); + PROCESS (clk_1, wire_nii_CLRN) + BEGIN + IF (wire_nii_CLRN = '0') THEN + n0111O <= '0'; + n0l00l <= '0'; + n0l00O <= '0'; + n0l0ii <= '0'; + n0l0il <= '0'; + n0l0li <= '0'; + n0l0ll <= '0'; + n0l0lO <= '0'; + n0l0Oi <= '0'; + n0l0Ol <= '0'; + n0l0OO <= '0'; + n0li0i <= '0'; + n0li0l <= '0'; + n0li0O <= '0'; + n0li1i <= '0'; + n0li1l <= '0'; + n0li1O <= '0'; + n0liii <= '0'; + n0liil <= '0'; + n0liiO <= '0'; + n0lili <= '0'; + n0lill <= '0'; + n0lilO <= '0'; + n0liOi <= '0'; + n0liOl <= '0'; + n0O0ll <= '0'; + n0O0lO <= '0'; + n0O0Oi <= '0'; + n0O0Ol <= '0'; + n0O0OO <= '0'; + n0Oiil <= '0'; + n0OiOl <= '0'; + n0OiOO <= '0'; + n0Ol0i <= '0'; + n0Ol0l <= '0'; + n0Ol0O <= '0'; + n0Ol1l <= '0'; + n0Ol1O <= '0'; + n0OO1O <= '0'; + n0OOli <= '0'; + n0OOll <= '0'; + n1O <= '0'; + ni000i <= '0'; + ni000l <= '0'; + ni00il <= '0'; + ni00iO <= '0'; + ni00Oi <= '0'; + ni101i <= '0'; + ni101l <= '0'; + ni110i <= '0'; + ni110l <= '0'; + ni111i <= '0'; + ni111l <= '0'; + ni111O <= '0'; + ni11OO <= '0'; + ni1i0i <= '0'; + ni1i0l <= '0'; + ni1i0O <= '0'; + ni1i1l <= '0'; + ni1i1O <= '0'; + ni1llO <= '0'; + ni1O0i <= '0'; + ni1O0l <= '0'; + ni1O0O <= '0'; + ni1O1l <= '0'; + ni1O1O <= '0'; + nil <= '0'; + nliO00i <= '0'; + nliO1l <= '0'; + nlli00O <= '0'; + nlli0Oi <= '0'; + nlli0Ol <= '0'; + nlli1ii <= '0'; + nlli1il <= '0'; + nlli1iO <= '0'; + nlli1li <= '0'; + nlli1ll <= '0'; + nllii0l <= '0'; + nllii0O <= '0'; + nllii1O <= '0'; + nlliiii <= '0'; + nlliiil <= '0'; + nlliiiO <= '0'; + nlliiO <= '0'; + nllil0i <= '0'; + nllil0l <= '0'; + nllil1O <= '0'; + nllili <= '0'; + nllill <= '0'; + nllilO <= '0'; + nlliOi <= '0'; + nlliOl <= '0'; + nlliOO <= '0'; + nlll0i <= '0'; + nlll0l <= '0'; + nlll0O <= '0'; + nlll10l <= '0'; + nlll10O <= '0'; + nlll1i <= '0'; + nlll1ii <= '0'; + nlll1il <= '0'; + nlll1iO <= '0'; + nlll1l <= '0'; + nlll1li <= '0'; + nlll1O <= '0'; + nlllii <= '0'; + nlllil <= '0'; + nllliO <= '0'; + nllll0O <= '0'; + nlllli <= '0'; + nllllii <= '0'; + nlllliO <= '0'; + nlllll <= '0'; + nllllli <= '0'; + nllllO <= '0'; + nlllO0i <= '0'; + nlllO0O <= '0'; + nlllO1i <= '0'; + nlllO1l <= '0'; + nlllO1O <= '0'; + nlllOi <= '0'; + nlllOii <= '0'; + nlllOil <= '0'; + nlllOiO <= '0'; + nlllOl <= '0'; + nlllOli <= '0'; + nlllOll <= '0'; + nlllOlO <= '0'; + nlllOO <= '0'; + nlllOOi <= '0'; + nlllOOl <= '0'; + nlllOOO <= '0'; + nllO0i <= '0'; + nllO0l <= '0'; + nllO10i <= '0'; + nllO10l <= '0'; + nllO10O <= '0'; + nllO11i <= '0'; + nllO11l <= '0'; + nllO11O <= '0'; + nllO1i <= '0'; + nllO1ii <= '0'; + nllO1il <= '0'; + nllO1iO <= '0'; + nllO1l <= '0'; + nllO1li <= '0'; + nllO1O <= '0'; + nllOOi <= '0'; + nllOOl <= '0'; + nlO00ii <= '0'; + nlO00li <= '0'; + nlO00ll <= '0'; + nlO00lO <= '0'; + nlO00Oi <= '0'; + nlO00Ol <= '0'; + nlO011i <= '0'; + nlO011l <= '0'; + nlO01l <= '0'; + nlO01O <= '0'; + nlO10li <= '0'; + nlO10ll <= '0'; + nlO10lO <= '0'; + nlO10Oi <= '0'; + nlO1i0O <= '0'; + nlO1Oii <= '0'; + nlO1OiO <= '0'; + nlO1OOi <= '0'; + nlO1OOl <= '0'; + nlO1OOO <= '0'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + n0111O <= wire_n0110O_dataout; + n0l00l <= wire_n0ll1i_dataout; + n0l00O <= wire_n0ll1l_dataout; + n0l0ii <= wire_n0ll1O_dataout; + n0l0il <= wire_n0ll0i_dataout; + n0l0li <= wire_n0ll0O_dataout; + n0l0ll <= wire_n0llii_dataout; + n0l0lO <= wire_n0llil_dataout; + n0l0Oi <= wire_n0lliO_dataout; + n0l0Ol <= wire_n0llli_dataout; + n0l0OO <= wire_n0llll_dataout; + n0li0i <= wire_n0llOO_dataout; + n0li0l <= wire_n0lO1i_dataout; + n0li0O <= wire_n0lO1l_dataout; + n0li1i <= wire_n0lllO_dataout; + n0li1l <= wire_n0llOi_dataout; + n0li1O <= wire_n0llOl_dataout; + n0liii <= wire_n0lO1O_dataout; + n0liil <= wire_n0lO0i_dataout; + n0liiO <= wire_n0lO0l_dataout; + n0lili <= wire_n0lO0O_dataout; + n0lill <= wire_n0lOii_dataout; + n0lilO <= wire_n0lOil_dataout; + n0liOi <= wire_n0lOiO_dataout; + n0liOl <= wire_n0Oi1O_dataout; + n0O0ll <= wire_n0liOO_dataout; + n0O0lO <= wire_n0Oi0i_dataout; + n0O0Oi <= wire_n0Oi0l_dataout; + n0O0Ol <= wire_n0Oi0O_dataout; + n0O0OO <= wire_n0Oiii_dataout; + n0Oiil <= n0OiOl; + n0OiOl <= (rgenericfifo AND wrenable); + n0OiOO <= wire_n0Olii_dataout; + n0Ol0i <= wire_n0Olli_dataout; + n0Ol0l <= wire_n0Olll_dataout; + n0Ol0O <= wire_n0OO0i_dataout; + n0Ol1l <= wire_n0Olil_dataout; + n0Ol1O <= wire_n0OliO_dataout; + n0OO1O <= n0OOli; + n0OOli <= nliiO0O; + n0OOll <= wire_ni110O_dataout; + n1O <= nil; + ni000i <= wire_ni00ii_dataout; + ni000l <= wire_ni00li_dataout; + ni00il <= wire_ni00ll_dataout; + ni00iO <= wire_ni00OO_dataout; + ni00Oi <= wire_ni0iiO_dataout; + ni101i <= wire_ni10il_dataout; + ni101l <= wire_ni1iii_dataout; + ni110i <= wire_ni11li_dataout; + ni110l <= wire_ni101O_dataout; + ni111i <= wire_ni11ii_dataout; + ni111l <= wire_ni11il_dataout; + ni111O <= wire_ni11iO_dataout; + ni11OO <= wire_ni10ii_dataout; + ni1i0i <= wire_ni1ili_dataout; + ni1i0l <= wire_ni1ill_dataout; + ni1i0O <= wire_ni1lOi_dataout; + ni1i1l <= wire_ni1iil_dataout; + ni1i1O <= wire_ni1iiO_dataout; + ni1llO <= wire_ni1Oii_dataout; + ni1O0i <= wire_ni1Oli_dataout; + ni1O0l <= wire_ni1Oll_dataout; + ni1O0O <= wire_ni000O_dataout; + ni1O1l <= wire_ni1Oil_dataout; + ni1O1O <= wire_ni1OiO_dataout; + nil <= wire_niO_dataout; + nliO00i <= wire_nliO0ii_dataout; + nliO1l <= sudi(0); + nlli00O <= wire_nlli1lO_dataout; + nlli0Oi <= nli0l0i; + nlli0Ol <= wire_nllii0i_dataout; + nlli1ii <= wire_nlli1Oi_dataout; + nlli1il <= wire_nlli1Ol_dataout; + nlli1iO <= wire_nlli1OO_dataout; + nlli1li <= wire_nlli01i_dataout; + nlli1ll <= nlli0Oi; + nllii0l <= wire_nlliill_dataout; + nllii0O <= wire_nlliilO_dataout; + nllii1O <= wire_nlliili_dataout; + nlliiii <= wire_nlliiOi_dataout; + nlliiil <= wire_nlliiOl_dataout; + nlliiiO <= wire_nllil0O_dataout; + nlliiO <= sudi(1); + nllil0i <= wire_nllilll_dataout; + nllil0l <= wire_nlll1ll_dataout; + nllil1O <= wire_nllilli_dataout; + nllili <= sudi(2); + nllill <= sudi(3); + nllilO <= sudi(4); + nlliOi <= sudi(5); + nlliOl <= sudi(6); + nlliOO <= sudi(7); + nlll0i <= sudi(11); + nlll0l <= sudi(12); + nlll0O <= sudi(13); + nlll10l <= wire_nlll1lO_dataout; + nlll10O <= wire_nlll1Oi_dataout; + nlll1i <= sudi(8); + nlll1ii <= wire_nlll1Ol_dataout; + nlll1il <= wire_nlll1OO_dataout; + nlll1iO <= wire_nlll01i_dataout; + nlll1l <= sudi(9); + nlll1li <= nllll0O; + nlll1O <= sudi(10); + nlllii <= sudi(14); + nlllil <= sudi(15); + nllliO <= sudi(16); + nllll0O <= (rgenericfifo AND wrenable); + nlllli <= sudi(17); + nllllii <= wire_nllllll_dataout; + nlllliO <= wire_nlllllO_dataout; + nlllll <= sudi(18); + nllllli <= wire_nllO1ll_dataout; + nllllO <= sudi(19); + nlllO0i <= wire_nllO1OO_dataout; + nlllO0O <= wire_nllO01l_dataout; + nlllO1i <= wire_nllO1lO_dataout; + nlllO1l <= wire_nllO1Oi_dataout; + nlllO1O <= wire_nllO1Ol_dataout; + nlllOi <= sudi(20); + nlllOii <= wire_nllO01O_dataout; + nlllOil <= wire_nllO00i_dataout; + nlllOiO <= wire_nllO00l_dataout; + nlllOl <= sudi(21); + nlllOli <= wire_nllO00O_dataout; + nlllOll <= wire_nllO0ii_dataout; + nlllOlO <= wire_nllO0il_dataout; + nlllOO <= sudi(22); + nlllOOi <= wire_nllO0iO_dataout; + nlllOOl <= wire_nllO0li_dataout; + nlllOOO <= wire_nllO0ll_dataout; + nllO0i <= sudi(26); + nllO0l <= sudi(27); + nllO10i <= wire_nllO0OO_dataout; + nllO10l <= wire_nllOi1i_dataout; + nllO10O <= wire_nllOi1l_dataout; + nllO11i <= wire_nllO0lO_dataout; + nllO11l <= wire_nllO0Oi_dataout; + nllO11O <= wire_nllO0Ol_dataout; + nllO1i <= sudi(23); + nllO1ii <= wire_nllOi1O_dataout; + nllO1il <= wire_nllOi0i_dataout; + nllO1iO <= wire_nllOi0l_dataout; + nllO1l <= sudi(24); + nllO1li <= wire_nlO1i1i_dataout; + nllO1O <= sudi(25); + nllOOi <= wire_nlO11i_o; + nllOOl <= wire_nlO11l_o; + nlO00ii <= (rclkcmpsqmd AND (wire_nlOi10l_dataout AND (((nlillil OR nlO00Oi) OR nlO00lO) OR nlO00ll))); + nlO00li <= wire_nlO0i1i_dataout; + nlO00ll <= wire_nlO0i1O_dataout; + nlO00lO <= wire_nlO0i0l_dataout; + nlO00Oi <= wire_nlO0iiO_dataout; + nlO00Ol <= wire_nlO0l1O_dataout; + nlO011i <= wire_nlO01ii_dataout; + nlO011l <= wire_nlO00il_dataout; + nlO01l <= wire_nlO11O_o; + nlO01O <= wire_nllOOO_o; + nlO10li <= wire_nlO1i1l_dataout; + nlO10ll <= wire_nlO1i1O_dataout; + nlO10lO <= wire_nlO1i0i_dataout; + nlO10Oi <= wire_nlO1i0l_dataout; + nlO1i0O <= wire_nlO1Oil_dataout; + nlO1Oii <= wire_nlO1Oli_dataout; + nlO1OiO <= wire_nlO011O_dataout; + nlO1OOi <= wire_nlO010i_dataout; + nlO1OOl <= wire_nlO010l_dataout; + nlO1OOO <= wire_nlO010O_dataout; + END IF; + END PROCESS; + wire_nii_CLRN <= ((nliO10i4 XOR nliO10i3) AND wire_nl0i_w_lg_dataout4w(0)); + wire_nii_w_lg_nlllO0i3160w(0) <= nlllO0i AND wire_nii_w_lg_nlllO1O2304w(0); + wire_nii_w_lg_n0l00l858w(0) <= NOT n0l00l; + wire_nii_w_lg_n0l00O860w(0) <= NOT n0l00O; + wire_nii_w_lg_n0l0ii862w(0) <= NOT n0l0ii; + wire_nii_w_lg_n0l0il864w(0) <= NOT n0l0il; + wire_nii_w_lg_n0O0ll856w(0) <= NOT n0O0ll; + wire_nii_w_lg_n0O0OO843w(0) <= NOT n0O0OO; + wire_nii_w_lg_n0Oiil755w(0) <= NOT n0Oiil; + wire_nii_w_lg_n0Ol0O974w(0) <= NOT n0Ol0O; + wire_nii_w_lg_ni1i0i1702w(0) <= NOT ni1i0i; + wire_nii_w_lg_ni1i0l1701w(0) <= NOT ni1i0l; + wire_nii_w_lg_ni1i0O967w(0) <= NOT ni1i0O; + wire_nii_w_lg_ni1llO1649w(0) <= NOT ni1llO; + wire_nii_w_lg_ni1O0i1643w(0) <= NOT ni1O0i; + wire_nii_w_lg_ni1O0l1642w(0) <= NOT ni1O0l; + wire_nii_w_lg_ni1O1l1647w(0) <= NOT ni1O1l; + wire_nii_w_lg_ni1O1O1645w(0) <= NOT ni1O1O; + wire_nii_w_lg_nlli0Oi2550w(0) <= NOT nlli0Oi; + wire_nii_w_lg_nlli0Ol2562w(0) <= NOT nlli0Ol; + wire_nii_w_lg_nlll10l3175w(0) <= NOT nlll10l; + wire_nii_w_lg_nlll10O3173w(0) <= NOT nlll10O; + wire_nii_w_lg_nlll1ii3171w(0) <= NOT nlll1ii; + wire_nii_w_lg_nlll1il3169w(0) <= NOT nlll1il; + wire_nii_w_lg_nlll1iO3168w(0) <= NOT nlll1iO; + wire_nii_w_lg_nlll1li2467w(0) <= NOT nlll1li; + wire_nii_w_lg_nllllli2298w(0) <= NOT nllllli; + wire_nii_w_lg_nlllO0i2306w(0) <= NOT nlllO0i; + wire_nii_w_lg_nlllO1i2300w(0) <= NOT nlllO1i; + wire_nii_w_lg_nlllO1l2302w(0) <= NOT nlllO1l; + wire_nii_w_lg_nlllO1O2304w(0) <= NOT nlllO1O; + wire_nii_w_lg_nlO011i3148w(0) <= NOT nlO011i; + wire_nii_w_lg_nlO10Oi2285w(0) <= NOT nlO10Oi; + wire_nii_w_lg_nlO1Oii2349w(0) <= NOT nlO1Oii; + wire_nii_w_lg_nlO1OOO3149w(0) <= NOT nlO1OOO; + wire_nii_w_lg_w_lg_nllllii47w48w(0) <= wire_nii_w_lg_nllllii47w(0) OR nlillOi; + wire_nii_w_lg_nllllii47w(0) <= nllllii OR nlillOl; + wire_nii_w_lg_nlO00ll2362w(0) <= nlO00ll OR nlO00li; + wire_nii_w_lg_nlO00lO2363w(0) <= nlO00lO OR wire_nii_w_lg_nlO00ll2362w(0); + wire_nii_w_lg_nlO00Oi2364w(0) <= nlO00Oi OR wire_nii_w_lg_nlO00lO2363w(0); + PROCESS (clk_2, wire_nii0lO_CLRN) + BEGIN + IF (wire_nii0lO_CLRN = '0') THEN + ni00Ol <= '0'; + ni0liO <= '0'; + ni0lli <= '0'; + ni0lll <= '0'; + ni0llO <= '0'; + ni0lOi <= '0'; + ni0lOl <= '0'; + ni0lOO <= '0'; + ni0O0i <= '0'; + ni0O0l <= '0'; + ni0O0O <= '0'; + ni0O1i <= '0'; + ni0O1l <= '0'; + ni0O1O <= '0'; + ni0Oii <= '0'; + ni0Oil <= '0'; + ni0OiO <= '0'; + ni0Oli <= '0'; + ni0Oll <= '0'; + ni0OlO <= '0'; + nii0li <= '0'; + nii0Oi <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + IF (nlil0l = '0') THEN + ni00Ol <= wire_niiO1l_dataout; + ni0liO <= wire_niiO1O_dataout; + ni0lli <= wire_niiO0i_dataout; + ni0lll <= wire_niiO0l_dataout; + ni0llO <= wire_niiO0O_dataout; + ni0lOi <= wire_niiOii_dataout; + ni0lOl <= wire_niiOil_dataout; + ni0lOO <= wire_niiOiO_dataout; + ni0O0i <= wire_nil11l_dataout; + ni0O0l <= wire_nil11O_dataout; + ni0O0O <= wire_nil10i_dataout; + ni0O1i <= wire_niiOli_dataout; + ni0O1l <= wire_niiOll_dataout; + ni0O1O <= wire_nil11i_dataout; + ni0Oii <= wire_nil10l_dataout; + ni0Oil <= wire_nil10O_dataout; + ni0OiO <= wire_nil1ii_dataout; + ni0Oli <= wire_nil1il_dataout; + ni0Oll <= wire_nil1iO_dataout; + ni0OlO <= wire_nil1li_dataout; + nii0li <= wire_niliil_dataout; + nii0Oi <= wire_nilili_dataout; + END IF; + END IF; + END PROCESS; + wire_nii0lO_CLRN <= ((nliiOOi56 XOR nliiOOi55) AND wire_w_lg_nliO1il2w(0)); + wire_nii0lO_w_lg_nii0Oi640w(0) <= NOT nii0Oi; + PROCESS (clk_1, wire_niiOOl_PRN, wire_niiOOl_CLRN) + BEGIN + IF (wire_niiOOl_PRN = '0') THEN + n0Oi1i <= '1'; + n0Oi1l <= '1'; + niiOlO <= '1'; + niiOOi <= '1'; + niiOOO <= '1'; + nlli10i <= '1'; + nlli10l <= '1'; + nlli10O <= '1'; + nlO10Ol <= '1'; + nlO10OO <= '1'; + ELSIF (wire_niiOOl_CLRN = '0') THEN + n0Oi1i <= '0'; + n0Oi1l <= '0'; + niiOlO <= '0'; + niiOOi <= '0'; + niiOOO <= '0'; + nlli10i <= '0'; + nlli10l <= '0'; + nlli10O <= '0'; + nlO10Ol <= '0'; + nlO10OO <= '0'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + n0Oi1i <= wire_n0Oili_dataout; + n0Oi1l <= wire_n0OiiO_dataout; + niiOlO <= wire_n0Oill_dataout; + niiOOi <= wire_n0OilO_dataout; + niiOOO <= wire_n0OiOi_dataout; + nlli10i <= wire_nlO1ill_dataout; + nlli10l <= wire_nlO1ili_dataout; + nlli10O <= wire_nlO1iiO_dataout; + nlO10Ol <= wire_nlO1iil_dataout; + nlO10OO <= wire_nlO1iii_dataout; + END IF; + END PROCESS; + wire_niiOOl_CLRN <= (nliiOOO52 XOR nliiOOO51); + wire_niiOOl_PRN <= (nliiOOl54 XOR nliiOOl53); + PROCESS (clk_1, nliO1il, wire_nl_CLRN) + BEGIN + IF (nliO1il = '1') THEN + nl0l <= '1'; + nO <= '1'; + ELSIF (wire_nl_CLRN = '0') THEN + nl0l <= '0'; + nO <= '0'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + nl0l <= nlilOil; + nO <= nl0l; + END IF; + if (now = 0 ns) then + nl0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nO <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl_CLRN <= (nliO1iO2 XOR nliO1iO1); + PROCESS (clk_2, nliO1il) + BEGIN + IF (nliO1il = '1') THEN + n100iO <= '1'; + n10iOi <= '1'; + niOOiO <= '1'; + nl11Ol <= '1'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n100iO <= wire_n10OOO_dataout; + n10iOi <= wire_n1i00i_dataout; + niOOiO <= wire_nl1l1i_dataout; + nl11Ol <= wire_nl1O0l_dataout; + END IF; + if (now = 0 ns) then + n100iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n10iOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niOOiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl11Ol <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2, wire_nli01i_PRN) + BEGIN + IF (wire_nli01i_PRN = '0') THEN + n0l00i <= '1'; + n0l01l <= '1'; + n0l01O <= '1'; + n1O00O <= '1'; + n1O0ii <= '1'; + nli01l <= '1'; + nli1OO <= '1'; + nlli11i <= '1'; + nlli11l <= '1'; + nlli11O <= '1'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n0l00i <= wire_nli0ll_dataout; + n0l01l <= wire_nli0Oi_dataout; + n0l01O <= wire_nli0lO_dataout; + n1O00O <= wire_n1O0Ol_dataout; + n1O0ii <= wire_n1O0Oi_dataout; + nli01l <= wire_nli0iO_dataout; + nli1OO <= wire_nli0li_dataout; + nlli11i <= wire_n1Oi1l_dataout; + nlli11l <= wire_n1Oi1i_dataout; + nlli11O <= wire_n1O0OO_dataout; + END IF; + END PROCESS; + wire_nli01i_PRN <= (nlil01l50 XOR nlil01l49); + PROCESS (clk_2, hard_reset) + BEGIN + IF (hard_reset = '1') THEN + nl0O <= '1'; + nlli <= '1'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + nl0O <= wire_nllO_dataout; + nlli <= nl0O; + END IF; + if (now = 0 ns) then + nl0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2, wire_nlOliOi_PRN, nliO1il) + BEGIN + IF (wire_nlOliOi_PRN = '0') THEN + nlOiOil <= '1'; + nlOiOli <= '1'; + nlOiOll <= '1'; + nlOiOlO <= '1'; + nlOiOOi <= '1'; + nlOiOOl <= '1'; + nlOiOOO <= '1'; + nlOl00i <= '1'; + nlOl00l <= '1'; + nlOl00O <= '1'; + nlOl01i <= '1'; + nlOl01l <= '1'; + nlOl01O <= '1'; + nlOl0ii <= '1'; + nlOl0il <= '1'; + nlOl0iO <= '1'; + nlOl0li <= '1'; + nlOl0ll <= '1'; + nlOl0lO <= '1'; + nlOl0Oi <= '1'; + nlOl0Ol <= '1'; + nlOl10i <= '1'; + nlOl10l <= '1'; + nlOl10O <= '1'; + nlOl11i <= '1'; + nlOl11l <= '1'; + nlOl11O <= '1'; + nlOl1ii <= '1'; + nlOl1il <= '1'; + nlOl1iO <= '1'; + nlOl1li <= '1'; + nlOl1ll <= '1'; + nlOl1lO <= '1'; + nlOl1Oi <= '1'; + nlOl1Ol <= '1'; + nlOl1OO <= '1'; + nlOlill <= '1'; + nlOliOl <= '1'; + ELSIF (nliO1il = '1') THEN + nlOiOil <= '0'; + nlOiOli <= '0'; + nlOiOll <= '0'; + nlOiOlO <= '0'; + nlOiOOi <= '0'; + nlOiOOl <= '0'; + nlOiOOO <= '0'; + nlOl00i <= '0'; + nlOl00l <= '0'; + nlOl00O <= '0'; + nlOl01i <= '0'; + nlOl01l <= '0'; + nlOl01O <= '0'; + nlOl0ii <= '0'; + nlOl0il <= '0'; + nlOl0iO <= '0'; + nlOl0li <= '0'; + nlOl0ll <= '0'; + nlOl0lO <= '0'; + nlOl0Oi <= '0'; + nlOl0Ol <= '0'; + nlOl10i <= '0'; + nlOl10l <= '0'; + nlOl10O <= '0'; + nlOl11i <= '0'; + nlOl11l <= '0'; + nlOl11O <= '0'; + nlOl1ii <= '0'; + nlOl1il <= '0'; + nlOl1iO <= '0'; + nlOl1li <= '0'; + nlOl1ll <= '0'; + nlOl1lO <= '0'; + nlOl1Oi <= '0'; + nlOl1Ol <= '0'; + nlOl1OO <= '0'; + nlOlill <= '0'; + nlOliOl <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + IF (nlii1Oi = '0') THEN + nlOiOil <= wire_nlOlOOl_dataout; + nlOiOli <= wire_nlOlOOO_dataout; + nlOiOll <= wire_nlOO11i_dataout; + nlOiOlO <= wire_nlOO11l_dataout; + nlOiOOi <= wire_nlOO11O_dataout; + nlOiOOl <= wire_nlOO10i_dataout; + nlOiOOO <= wire_nlOO10l_dataout; + nlOl00i <= wire_nlOlO1O_dataout; + nlOl00l <= wire_nlOlO0i_dataout; + nlOl00O <= wire_nlOlO0l_dataout; + nlOl01i <= wire_nlOO00O_dataout; + nlOl01l <= wire_nlOO0ii_dataout; + nlOl01O <= wire_nlOlO1l_dataout; + nlOl0ii <= wire_nlOlO0O_dataout; + nlOl0il <= wire_nlOlOii_dataout; + nlOl0iO <= wire_nlOlOil_dataout; + nlOl0li <= wire_nlOlOiO_dataout; + nlOl0ll <= wire_nlOlOli_dataout; + nlOl0lO <= wire_nlOlOll_dataout; + nlOl0Oi <= wire_nlOlOlO_dataout; + nlOl0Ol <= wire_nlOlOOi_dataout; + nlOl10i <= wire_nlOO1iO_dataout; + nlOl10l <= wire_nlOO1li_dataout; + nlOl10O <= wire_nlOO1ll_dataout; + nlOl11i <= wire_nlOO10O_dataout; + nlOl11l <= wire_nlOO1ii_dataout; + nlOl11O <= wire_nlOO1il_dataout; + nlOl1ii <= wire_nlOO1lO_dataout; + nlOl1il <= wire_nlOO1Oi_dataout; + nlOl1iO <= wire_nlOO1Ol_dataout; + nlOl1li <= wire_nlOO1OO_dataout; + nlOl1ll <= wire_nlOO01i_dataout; + nlOl1lO <= wire_nlOO01l_dataout; + nlOl1Oi <= wire_nlOO01O_dataout; + nlOl1Ol <= wire_nlOO00i_dataout; + nlOl1OO <= wire_nlOO00l_dataout; + nlOlill <= wire_nlOOi0i_dataout; + nlOliOl <= wire_nlOOi0O_dataout; + END IF; + END IF; + END PROCESS; + wire_nlOliOi_PRN <= (nli0O0O62 XOR nli0O0O61); + wire_nlOliOi_w_lg_nlOliOl2141w(0) <= NOT nlOliOl; + wire_n00i_dataout <= wire_nll1il_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi01O_dataout; + wire_n00l_dataout <= wire_nll1iO_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi00i_dataout; + wire_n00O_dataout <= wire_nll1li_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi00l_dataout; + wire_n0110i_dataout <= n0111l AND NOT(wire_w_lg_nlil00O1791w(0)); + wire_n0110l_dataout <= n0111O AND NOT(wire_w_lg_nlil00O1791w(0)); + wire_n0110O_dataout <= wire_nlilOi_o AND (rgenericfifo OR wire_nliOOi_dataout); + wire_n01i_dataout <= wire_nll10l_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1OO_dataout; + wire_n01l_dataout <= wire_nll10O_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi01i_dataout; + wire_n01O_dataout <= wire_nll1ii_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi01l_dataout; + wire_n0ii_dataout <= wire_nll1ll_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi00O_dataout; + wire_n0il_dataout <= wire_nll1lO_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi0ii_dataout; + wire_n0iO_dataout <= wire_nll1Oi_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi0il_dataout; + wire_n0li_dataout <= wire_nll1Ol_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi0iO_dataout; + wire_n0liOO_dataout <= wire_n0lOli_dataout AND NOT(nliiO1i); + wire_n0ll_dataout <= wire_nll1OO_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi0li_dataout; + wire_n0ll0i_dataout <= wire_n0lOOl_dataout AND NOT(nliiO1i); + wire_n0ll0l_dataout <= wire_n0lOOO_dataout OR nliiO1i; + wire_n0ll0O_dataout <= wire_n0O11i_dataout AND NOT(nliiO1i); + wire_n0ll1i_dataout <= wire_n0lOll_dataout AND NOT(nliiO1i); + wire_n0ll1l_dataout <= wire_n0lOlO_dataout AND NOT(nliiO1i); + wire_n0ll1O_dataout <= wire_n0lOOi_dataout AND NOT(nliiO1i); + wire_n0llii_dataout <= wire_n0O11l_dataout AND NOT(nliiO1i); + wire_n0llil_dataout <= wire_n0O11O_dataout AND NOT(nliiO1i); + wire_n0lliO_dataout <= wire_n0O10i_dataout AND NOT(nliiO1i); + wire_n0llli_dataout <= wire_n0O10l_dataout AND NOT(nliiO1i); + wire_n0llll_dataout <= wire_n0O10O_dataout AND NOT(nliiO1i); + wire_n0lllO_dataout <= wire_n0O1ii_dataout AND NOT(nliiO1i); + wire_n0llOi_dataout <= wire_n0O1il_dataout AND NOT(nliiO1i); + wire_n0llOl_dataout <= wire_n0O1iO_dataout AND NOT(nliiO1i); + wire_n0llOO_dataout <= wire_n0O1li_dataout AND NOT(nliiO1i); + wire_n0lO_dataout <= wire_nll01i_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi0ll_dataout; + wire_n0lO0i_dataout <= wire_n0O1Ol_dataout AND NOT(nliiO1i); + wire_n0lO0l_dataout <= wire_n0O1OO_dataout AND NOT(nliiO1i); + wire_n0lO0O_dataout <= wire_n0O01i_dataout AND NOT(nliiO1i); + wire_n0lO1i_dataout <= wire_n0O1ll_dataout AND NOT(nliiO1i); + wire_n0lO1l_dataout <= wire_n0O1lO_dataout AND NOT(nliiO1i); + wire_n0lO1O_dataout <= wire_n0O1Oi_dataout AND NOT(nliiO1i); + wire_n0lOii_dataout <= wire_n0O01l_dataout AND NOT(nliiO1i); + wire_n0lOil_dataout <= wire_n0O01O_dataout AND NOT(nliiO1i); + wire_n0lOiO_dataout <= wire_n0O00i_dataout AND NOT(nliiO1i); + wire_n0lOli_dataout <= wire_n0O00l_dataout WHEN nliilOl = '1' ELSE n0O0ll; + wire_n0lOll_dataout <= wire_n0O00O_dataout WHEN nliilOl = '1' ELSE n0l00l; + wire_n0lOlO_dataout <= wire_n0O0ii_dataout WHEN nliilOl = '1' ELSE n0l00O; + wire_n0lOOi_dataout <= wire_n0O0il_dataout WHEN nliilOl = '1' ELSE n0l0ii; + wire_n0lOOl_dataout <= wire_n0O0iO_dataout WHEN nliilOl = '1' ELSE n0l0il; + wire_n0lOOO_dataout <= n0liOi WHEN nliilOl = '1' ELSE n0l0iO; + wire_n0O00i_dataout <= n0lilO WHEN nliilOl = '1' ELSE n0liOi; + wire_n0O00l_dataout <= wire_n0O0li_o(0) AND NOT(nliii0O); + wire_n0O00O_dataout <= wire_n0O0li_o(1) AND NOT(nliii0O); + wire_n0O01i_dataout <= n0liiO WHEN nliilOl = '1' ELSE n0lili; + wire_n0O01l_dataout <= n0lili WHEN nliilOl = '1' ELSE n0lill; + wire_n0O01O_dataout <= n0lill WHEN nliilOl = '1' ELSE n0lilO; + wire_n0O0ii_dataout <= wire_n0O0li_o(2) AND NOT(nliii0O); + wire_n0O0il_dataout <= wire_n0O0li_o(3) AND NOT(nliii0O); + wire_n0O0iO_dataout <= wire_n0O0li_o(4) AND NOT(nliii0O); + wire_n0O10i_dataout <= n0l0lO WHEN nliilOl = '1' ELSE n0l0Oi; + wire_n0O10l_dataout <= n0l0Oi WHEN nliilOl = '1' ELSE n0l0Ol; + wire_n0O10O_dataout <= n0l0Ol WHEN nliilOl = '1' ELSE n0l0OO; + wire_n0O11i_dataout <= n0l0iO WHEN nliilOl = '1' ELSE n0l0li; + wire_n0O11l_dataout <= n0l0li WHEN nliilOl = '1' ELSE n0l0ll; + wire_n0O11O_dataout <= n0l0ll WHEN nliilOl = '1' ELSE n0l0lO; + wire_n0O1ii_dataout <= n0l0OO WHEN nliilOl = '1' ELSE n0li1i; + wire_n0O1il_dataout <= n0li1i WHEN nliilOl = '1' ELSE n0li1l; + wire_n0O1iO_dataout <= n0li1l WHEN nliilOl = '1' ELSE n0li1O; + wire_n0O1li_dataout <= n0li1O WHEN nliilOl = '1' ELSE n0li0i; + wire_n0O1ll_dataout <= n0li0i WHEN nliilOl = '1' ELSE n0li0l; + wire_n0O1lO_dataout <= n0li0l WHEN nliilOl = '1' ELSE n0li0O; + wire_n0O1Oi_dataout <= n0li0O WHEN nliilOl = '1' ELSE n0liii; + wire_n0O1Ol_dataout <= n0liii WHEN nliilOl = '1' ELSE n0liil; + wire_n0O1OO_dataout <= n0liil WHEN nliilOl = '1' ELSE n0liiO; + wire_n0Oi_dataout <= wire_nll01l_dataout AND rwa_6g_en; + wire_n0Oi0i_dataout <= n0Oi1i AND NOT(nliiO1i); + wire_n0Oi0l_dataout <= niiOlO AND NOT(nliiO1i); + wire_n0Oi0O_dataout <= niiOOi AND NOT(nliiO1i); + wire_n0Oi1O_dataout <= n0Oi1l AND NOT(nliiO1i); + wire_n0Oiii_dataout <= niiOOO AND NOT(nliiO1i); + wire_n0OiiO_dataout <= niii1i AND NOT(nliiO1i); + wire_n0Oili_dataout <= niOlOl AND NOT(nliiO1i); + wire_n0Oill_dataout <= niOlOO AND NOT(nliiO1i); + wire_n0OilO_dataout <= niOO1i AND NOT(nliiO1i); + wire_n0OiOi_dataout <= niOO1l AND NOT(nliiO1i); + wire_n0Ol_dataout <= wire_nll01O_dataout AND rwa_6g_en; + wire_n0Olii_dataout <= nliiiii AND NOT(nliiO1i); + wire_n0Olil_dataout <= nliiiil AND NOT(nliiO1i); + wire_n0OliO_dataout <= nliiiiO AND NOT(nliiO1i); + wire_n0Olli_dataout <= nliiili AND NOT(nliiO1i); + wire_n0Olll_dataout <= nliiill AND NOT(nliiO1i); + wire_n0OO_dataout <= wire_nll00i_dataout AND rwa_6g_en; + wire_n0OO0i_dataout <= wire_n0OO0l_dataout AND wire_nliOOi_dataout; + wire_n0OO0l_dataout <= n0Ol0O OR (wire_nii_w_lg_n0Ol0O974w(0) AND nliiilO); + wire_n0OOii_dataout <= (nliiiOi OR n0OO1O) WHEN nliO11i = '1' ELSE nliiiOi; + wire_n1011i_dataout <= wire_n1010i_o(0) AND nli0OOi; + wire_n1011l_dataout <= wire_n1010i_o(1) AND nli0OOi; + wire_n1011O_dataout <= wire_n1010i_o(2) AND nli0OOi; + wire_n101iO_dataout <= n11O1l AND wire_nlOi11i_dataout; + wire_n101li_dataout <= (rclkcmpsqmd AND (nlii1li AND wire_n1i_w_lg_n11O1l2088w(0))) AND wire_nlOi11i_dataout; + wire_n101ll_dataout <= nlii1li AND wire_nlOi11i_dataout; + wire_n10i_dataout <= nl10OO WHEN rwa_6g_en = '1' ELSE n10lOl; + wire_n10l_dataout <= nl1i1i WHEN rwa_6g_en = '1' ELSE n10lOO; + wire_n10O_dataout <= nl1i1l WHEN rwa_6g_en = '1' ELSE n10O1i; + wire_n10O0i_dataout <= wire_n1iiiO_dataout AND NOT(nlii00O); + wire_n10O0l_dataout <= wire_n1iili_dataout AND NOT(nlii00O); + wire_n10O0O_dataout <= wire_n1iill_dataout AND NOT(nlii00O); + wire_n10Oii_dataout <= wire_n1iilO_dataout AND NOT(nlii00O); + wire_n10Oil_dataout <= wire_n1iiOi_dataout AND NOT(nlii00O); + wire_n10OiO_dataout <= wire_n1iiOl_dataout AND NOT(nlii00O); + wire_n10Oli_dataout <= wire_n1iiOO_dataout AND NOT(nlii00O); + wire_n10Oll_dataout <= wire_n1il1i_dataout AND NOT(nlii00O); + wire_n10OlO_dataout <= wire_n1il1l_dataout AND NOT(nlii00O); + wire_n10OOi_dataout <= wire_n1il1O_dataout AND NOT(nlii00O); + wire_n10OOl_dataout <= wire_n1il0i_dataout AND NOT(nlii00O); + wire_n10OOO_dataout <= wire_n1il0l_dataout OR nlii00O; + wire_n1100i_dataout <= wire_nlOliOi_w_lg_nlOliOl2141w(0) WHEN rclkcmpinsertpad = '1' ELSE nlOliOl; + wire_n1100l_dataout <= nlOliOl WHEN rclkcmpinsertpad = '1' ELSE wire_nlOliOi_w_lg_nlOliOl2141w(0); + wire_n1100O_dataout <= (nli0OiO OR nlOll1l) WHEN nlilOiO = '1' ELSE nli0OiO; + wire_n1101i_dataout <= nlOll1i OR nlii1li; + wire_n110Oi_dataout <= nliO01l AND NOT(nlii00O); + wire_n110Ol_dataout <= ((((n1lili AND nliO01l) AND wire_n1i_w_lg_n110li2133w(0)) AND (rskpsetbased OR nli0Oll)) AND wire_w_lg_nli0Oli2137w(0)) AND NOT(nlii00O); + wire_n1110i_dataout <= nlOiOlO WHEN nlii1li = '1' ELSE nlOli1O; + wire_n1110l_dataout <= nlOiOOi WHEN nlii1li = '1' ELSE nlOli0i; + wire_n1110O_dataout <= nlOiOOl WHEN nlii1li = '1' ELSE nlOli0l; + wire_n1111i_dataout <= nlOiOil WHEN nlii1li = '1' ELSE nlOl0OO; + wire_n1111l_dataout <= nlOiOli WHEN nlii1li = '1' ELSE nlOli1i; + wire_n1111O_dataout <= nlOiOll WHEN nlii1li = '1' ELSE nlOli1l; + wire_n111ii_dataout <= nlOiOOO WHEN nlii1li = '1' ELSE nlOli0O; + wire_n111il_dataout <= nlOl11i WHEN nlii1li = '1' ELSE nlOliii; + wire_n111iO_dataout <= nlOl11l WHEN nlii1li = '1' ELSE nlOliil; + wire_n111li_dataout <= nlOl11O WHEN nlii1li = '1' ELSE nlOliiO; + wire_n111ll_dataout <= nlOlili AND NOT(nlii1li); + wire_n111lO_dataout <= nlOl10i WHEN nlii1li = '1' ELSE nlOlill; + wire_n111Oi_dataout <= nlOlilO AND NOT(nlii1li); + wire_n111Ol_dataout <= nlOl10l WHEN nlii1li = '1' ELSE nlOliOl; + wire_n111OO_dataout <= nlOliOO AND NOT(nlii1li); + wire_n11i_dataout <= nl10lO WHEN rwa_6g_en = '1' ELSE n10lll; + wire_n11l_dataout <= nl10Oi WHEN rwa_6g_en = '1' ELSE n10llO; + wire_n11l0i_dataout <= wire_n11lll_dataout AND NOT(nlii00O); + wire_n11l0l_dataout <= wire_n11llO_dataout AND NOT(nlii00O); + wire_n11l0O_dataout <= wire_n11lOi_dataout AND NOT(nlii00O); + wire_n11l1i_dataout <= nlii1li AND NOT(nlii00O); + wire_n11l1l_dataout <= wire_n11liO_dataout AND NOT(nlii00O); + wire_n11l1O_dataout <= wire_n11lli_dataout AND NOT(nlii00O); + wire_n11lii_dataout <= wire_n11lOl_dataout AND NOT(nlii00O); + wire_n11lil_dataout <= wire_n11lOO_dataout AND NOT(nlii00O); + wire_n11liO_dataout <= n110lO AND NOT(nlii1li); + wire_n11lli_dataout <= n11iil AND NOT(nlii1li); + wire_n11lll_dataout <= n11iiO AND NOT(nlii1li); + wire_n11llO_dataout <= n11ili AND NOT(nlii1li); + wire_n11lOi_dataout <= n11ill AND NOT(nlii1li); + wire_n11lOl_dataout <= n11ilO AND NOT(nlii1li); + wire_n11lOO_dataout <= n11iOi AND NOT(nlii1li); + wire_n11O_dataout <= nl10Ol WHEN rwa_6g_en = '1' ELSE n10lOi; + wire_n11Oii_dataout <= wire_n11Oli_dataout AND wire_nlOi11i_dataout; + wire_n11Oil_dataout <= wire_n11Oll_dataout AND wire_nlOi11i_dataout; + wire_n11OiO_dataout <= wire_n11OlO_dataout AND wire_nlOi11i_dataout; + wire_n11Oli_dataout <= wire_n11OOi_dataout OR nli0OOO; + wire_n11Oll_dataout <= wire_n11OOl_dataout AND NOT(nli0OOO); + wire_n11OlO_dataout <= wire_n11OOO_dataout AND NOT(nli0OOO); + wire_n11OOi_dataout <= wire_n1010i_o(0) WHEN nli0OOl = '1' ELSE wire_n1011i_dataout; + wire_n11OOl_dataout <= wire_n1010i_o(1) WHEN nli0OOl = '1' ELSE wire_n1011l_dataout; + wire_n11OOO_dataout <= wire_n1010i_o(2) WHEN nli0OOl = '1' ELSE wire_n1011O_dataout; + wire_n1i00i_dataout <= wire_n1iOiO_dataout OR nlii00O; + wire_n1i00l_dataout <= wire_n1iOli_dataout AND NOT(nlii00O); + wire_n1i00O_dataout <= wire_n1iOll_dataout AND NOT(nlii00O); + wire_n1i01i_dataout <= wire_n1iO0O_dataout AND NOT(nlii00O); + wire_n1i01l_dataout <= wire_n1iOii_dataout AND NOT(nlii00O); + wire_n1i01O_dataout <= wire_n1iOil_dataout AND NOT(nlii00O); + wire_n1i0ii_dataout <= wire_n1iOlO_dataout AND NOT(nlii00O); + wire_n1i0il_dataout <= wire_n1iOOi_dataout AND NOT(nlii00O); + wire_n1i0iO_dataout <= wire_n1iOOl_dataout AND NOT(nlii00O); + wire_n1i0li_dataout <= wire_n1iOOO_dataout AND NOT(nlii00O); + wire_n1i0ll_dataout <= wire_n1l11i_dataout AND NOT(nlii00O); + wire_n1i0lO_dataout <= wire_n1l11l_dataout AND NOT(nlii00O); + wire_n1i0Oi_dataout <= wire_n1l11O_dataout AND NOT(nlii00O); + wire_n1i0Ol_dataout <= wire_n1l10i_dataout AND NOT(nlii00O); + wire_n1i0OO_dataout <= wire_n1l10l_dataout AND NOT(nlii00O); + wire_n1i10i_dataout <= wire_n1iliO_dataout AND NOT(nlii00O); + wire_n1i10l_dataout <= wire_n1illi_dataout AND NOT(nlii00O); + wire_n1i10O_dataout <= wire_n1illl_dataout AND NOT(nlii00O); + wire_n1i11i_dataout <= wire_n1il0O_dataout AND NOT(nlii00O); + wire_n1i11l_dataout <= wire_n1ilii_dataout AND NOT(nlii00O); + wire_n1i11O_dataout <= wire_n1ilil_dataout AND NOT(nlii00O); + wire_n1i1ii_dataout <= wire_n1illO_dataout AND NOT(nlii00O); + wire_n1i1il_dataout <= wire_n1ilOi_dataout AND NOT(nlii00O); + wire_n1i1iO_dataout <= wire_n1ilOl_dataout AND NOT(nlii00O); + wire_n1i1li_dataout <= wire_n1ilOO_dataout AND NOT(nlii00O); + wire_n1i1ll_dataout <= wire_n1iO1i_dataout AND NOT(nlii00O); + wire_n1i1lO_dataout <= wire_n1iO1l_dataout AND NOT(nlii00O); + wire_n1i1Oi_dataout <= wire_n1iO1O_dataout AND NOT(nlii00O); + wire_n1i1Ol_dataout <= wire_n1iO0i_dataout AND NOT(nlii00O); + wire_n1i1OO_dataout <= wire_n1iO0l_dataout AND NOT(nlii00O); + wire_n1ii_dataout <= nl1i1O WHEN rwa_6g_en = '1' ELSE n10O1l; + wire_n1ii0i_dataout <= wire_n1l1iO_dataout AND NOT(nlii00O); + wire_n1ii0l_dataout <= wire_n1l1li_dataout AND NOT(nlii00O); + wire_n1ii0O_dataout <= wire_n1l1ll_dataout AND NOT(nlii00O); + wire_n1ii1i_dataout <= wire_n1l10O_dataout AND NOT(nlii00O); + wire_n1ii1l_dataout <= wire_n1l1ii_dataout AND NOT(nlii00O); + wire_n1ii1O_dataout <= wire_n1l1il_dataout AND NOT(nlii00O); + wire_n1iiii_dataout <= wire_n1l1lO_dataout AND NOT(nlii00O); + wire_n1iiil_dataout <= wire_n1l1Oi_dataout AND NOT(nlii00O); + wire_n1iiiO_dataout <= nlii11i WHEN nlii10l = '1' ELSE n11O0O; + wire_n1iili_dataout <= (((wire_n1l01l_o(4) OR wire_n1l01l_o(3)) OR wire_n1l01l_o(2)) OR wire_n1l01l_o(1)) WHEN nlii10l = '1' ELSE n101Ol; + wire_n1iill_dataout <= nlii11l WHEN nlii10l = '1' ELSE n101OO; + wire_n1iilO_dataout <= nlii11O WHEN nlii10l = '1' ELSE n1001i; + wire_n1iiOi_dataout <= (((wire_n1l00O_o(18) OR wire_n1l00O_o(17)) OR wire_n1l00O_o(16)) OR wire_n1l00O_o(15)) WHEN nlii10l = '1' ELSE n1001l; + wire_n1iiOl_dataout <= wire_n1l0ii_dataout WHEN nlii10l = '1' ELSE n1001O; + wire_n1iiOO_dataout <= wire_n1l0il_dataout WHEN nlii10l = '1' ELSE n1000i; + wire_n1il_dataout <= wire_ni1i1i_o WHEN rwa_6g_en = '1' ELSE wire_nlli0iO_o; + wire_n1il0i_dataout <= n10ilO WHEN nlii10l = '1' ELSE n100il; + wire_n1il0l_dataout <= n100il WHEN nlii10l = '1' ELSE n100iO; + wire_n1il0O_dataout <= n100iO WHEN nlii10l = '1' ELSE n100li; + wire_n1il1i_dataout <= wire_n1l0iO_dataout WHEN nlii10l = '1' ELSE n1000l; + wire_n1il1l_dataout <= wire_n1l0li_dataout WHEN nlii10l = '1' ELSE n1000O; + wire_n1il1O_dataout <= wire_n1l0ll_dataout WHEN nlii10l = '1' ELSE n100ii; + wire_n1ilii_dataout <= n100li WHEN nlii10l = '1' ELSE n100ll; + wire_n1ilil_dataout <= n100ll WHEN nlii10l = '1' ELSE n100lO; + wire_n1iliO_dataout <= n100lO WHEN nlii10l = '1' ELSE n100Oi; + wire_n1illi_dataout <= n100Oi WHEN nlii10l = '1' ELSE n100Ol; + wire_n1illl_dataout <= n100Ol WHEN nlii10l = '1' ELSE n100OO; + wire_n1illO_dataout <= n100OO WHEN nlii10l = '1' ELSE n10i1i; + wire_n1ilOi_dataout <= n10i1i WHEN nlii10l = '1' ELSE n10i1l; + wire_n1ilOl_dataout <= n10i1l WHEN nlii10l = '1' ELSE n10i1O; + wire_n1ilOO_dataout <= n10i1O WHEN nlii10l = '1' ELSE n10i0i; + wire_n1iO_dataout <= wire_nllOiO_o WHEN rwa_6g_en = '1' ELSE wire_n1OllO_o; + wire_n1iO0i_dataout <= n10iii WHEN nlii10l = '1' ELSE n10iil; + wire_n1iO0l_dataout <= n10iil WHEN nlii10l = '1' ELSE n10iiO; + wire_n1iO0O_dataout <= n10iiO WHEN nlii10l = '1' ELSE n10ili; + wire_n1iO1i_dataout <= n10i0i WHEN nlii10l = '1' ELSE n10i0l; + wire_n1iO1l_dataout <= n10i0l WHEN nlii10l = '1' ELSE n10i0O; + wire_n1iO1O_dataout <= n10i0O WHEN nlii10l = '1' ELSE n10iii; + wire_n1iOii_dataout <= n10ili WHEN nlii10l = '1' ELSE n10ill; + wire_n1iOil_dataout <= n10ill WHEN nlii10l = '1' ELSE n10ilO; + wire_n1iOiO_dataout <= n10O1l WHEN nlii10l = '1' ELSE n10iOi; + wire_n1iOli_dataout <= n10iOi WHEN nlii10l = '1' ELSE n10iOl; + wire_n1iOll_dataout <= n10iOl WHEN nlii10l = '1' ELSE n10iOO; + wire_n1iOlO_dataout <= n10iOO WHEN nlii10l = '1' ELSE n10l1i; + wire_n1iOOi_dataout <= n10l1i WHEN nlii10l = '1' ELSE n10l1l; + wire_n1iOOl_dataout <= n10l1l WHEN nlii10l = '1' ELSE n10l1O; + wire_n1iOOO_dataout <= n10l1O WHEN nlii10l = '1' ELSE n10l0i; + wire_n1l0ii_dataout <= wire_n1l0lO_o(0) AND NOT(nlii10i); + wire_n1l0il_dataout <= wire_n1l0lO_o(1) AND NOT(nlii10i); + wire_n1l0iO_dataout <= wire_n1l0lO_o(2) AND NOT(nlii10i); + wire_n1l0li_dataout <= wire_n1l0lO_o(3) AND NOT(nlii10i); + wire_n1l0ll_dataout <= wire_n1l0lO_o(4) AND NOT(nlii10i); + wire_n1l10i_dataout <= n10lii WHEN nlii10l = '1' ELSE n10lil; + wire_n1l10l_dataout <= n10lil WHEN nlii10l = '1' ELSE n10liO; + wire_n1l10O_dataout <= n10liO WHEN nlii10l = '1' ELSE n10lli; + wire_n1l11i_dataout <= n10l0i WHEN nlii10l = '1' ELSE n10l0l; + wire_n1l11l_dataout <= n10l0l WHEN nlii10l = '1' ELSE n10l0O; + wire_n1l11O_dataout <= n10l0O WHEN nlii10l = '1' ELSE n10lii; + wire_n1l1ii_dataout <= n10lli WHEN nlii10l = '1' ELSE n10lll; + wire_n1l1il_dataout <= n10lll WHEN nlii10l = '1' ELSE n10llO; + wire_n1l1iO_dataout <= n10llO WHEN nlii10l = '1' ELSE n10lOi; + wire_n1l1li_dataout <= n10lOi WHEN nlii10l = '1' ELSE n10lOl; + wire_n1l1ll_dataout <= n10lOl WHEN nlii10l = '1' ELSE n10lOO; + wire_n1l1lO_dataout <= n10lOO WHEN nlii10l = '1' ELSE n10O1i; + wire_n1l1Oi_dataout <= n10O1i WHEN nlii10l = '1' ELSE n10O1l; + wire_n1li_dataout <= wire_nllOli_o WHEN rwa_6g_en = '1' ELSE wire_n1OlOi_o; + wire_n1li0i_dataout <= fifo_rd_in_comp_2 WHEN nlii10O = '1' ELSE n1lili; + wire_n1li1O_dataout <= fifo_rd_in_comp_0 WHEN nlii1ii = '1' ELSE wire_n1li0i_dataout; + wire_n1lill_dataout <= ((wire_w_lg_rgenericfifo32w(0) AND n1lili) OR nlii1iO) AND NOT(nlii00O); + wire_n1lilO_dataout <= n1liiO AND NOT(nlii00O); + wire_n1liOi_dataout <= nllOOi AND NOT(nlii00O); + wire_n1ll_dataout <= (wire_nllOil_o AND wire_nllOii_o) WHEN rwa_6g_en = '1' ELSE ((wire_n1OOOi_o AND wire_n1OOlO_o) AND (nlilO0O16 XOR nlilO0O15)); + wire_n1lO_dataout <= wire_nll11i_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1ll_dataout; + wire_n1O0il_dataout <= n1O0ii AND NOT(nlii00O); + wire_n1O0iO_dataout <= n1O00O AND NOT(nlii00O); + wire_n1O0li_dataout <= nlli11O AND NOT(nlii00O); + wire_n1O0ll_dataout <= nlli11l AND NOT(nlii00O); + wire_n1O0lO_dataout <= nlli11i AND NOT(nlii00O); + wire_n1O0Oi_dataout <= nlli00O AND NOT(nlii00O); + wire_n1O0Ol_dataout <= nlli1ii AND NOT(nlii00O); + wire_n1O0OO_dataout <= nlli1il AND NOT(nlii00O); + wire_n1O1ll_dataout <= insert_incomplete_0 WHEN nlilO0l = '1' ELSE n1liil; + wire_n1O1ll_w_lg_dataout1965w(0) <= wire_n1O1ll_dataout AND wire_w_lg_w_lg_rskpsetbased1868w1964w(0); + wire_n1O1lO_dataout <= latency_comp_0 WHEN nlilO0l = '1' ELSE wire_w_lg_nlillii120w(0); + wire_n1Oi_dataout <= wire_nll11l_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1lO_dataout; + wire_n1Oi1i_dataout <= nlli1iO AND NOT(nlii00O); + wire_n1Oi1l_dataout <= nlli1li AND NOT(nlii00O); + wire_n1Oi1O_dataout <= (rskpsetbased AND (nlii0li OR nlii0iO)) OR (wire_w_lg_rskpsetbased1868w(0) AND (nlii0il OR nlii0ii)); + wire_n1Oi1O_w_lg_dataout2153w(0) <= wire_n1Oi1O_dataout AND wire_w_lg_rmatchen2152w(0); + wire_n1Oiil_dataout <= (nlii0lO OR nlii0ll) WHEN rskpsetbased = '1' ELSE (nlii0Ol OR nlii0Oi); + wire_n1Oiil_w_lg_dataout1966w(0) <= wire_n1Oiil_dataout AND wire_n1O1ll_w_lg_dataout1965w(0); + wire_n1Oiil_w_lg_dataout2154w(0) <= wire_n1Oiil_dataout AND wire_n1Oi1O_w_lg_dataout2153w(0); + wire_n1Oiil_w_lg_dataout1941w(0) <= NOT wire_n1Oiil_dataout; + wire_n1OiOi_dataout <= rclkcmpsq1n(0) WHEN nliii1O = '1' ELSE rclkcmpsq1n(10); + wire_n1OiOl_dataout <= rclkcmpsq1n(1) WHEN nliii1O = '1' ELSE rclkcmpsq1n(11); + wire_n1OiOO_dataout <= rclkcmpsq1n(2) WHEN nliii1O = '1' ELSE rclkcmpsq1n(12); + wire_n1Ol_dataout <= wire_nll11O_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1Oi_dataout; + wire_n1Ol0i_dataout <= rclkcmpsq1n(6) WHEN nliii1O = '1' ELSE rclkcmpsq1n(16); + wire_n1Ol0l_dataout <= rclkcmpsq1n(7) WHEN nliii1O = '1' ELSE rclkcmpsq1n(17); + wire_n1Ol0O_dataout <= rclkcmpsq1n(8) WHEN nliii1O = '1' ELSE rclkcmpsq1n(18); + wire_n1Ol1i_dataout <= rclkcmpsq1n(3) WHEN nliii1O = '1' ELSE rclkcmpsq1n(13); + wire_n1Ol1l_dataout <= rclkcmpsq1n(4) WHEN nliii1O = '1' ELSE rclkcmpsq1n(14); + wire_n1Ol1O_dataout <= rclkcmpsq1n(5) WHEN nliii1O = '1' ELSE rclkcmpsq1n(15); + wire_n1Olii_dataout <= rclkcmpsq1n(9) WHEN nliii1O = '1' ELSE rclkcmpsq1n(19); + wire_n1Olli_dataout <= fifo_ovr_0 WHEN nlilO0l = '1' ELSE nlO01O; + wire_n1Olli_w_lg_dataout2358w(0) <= wire_n1Olli_dataout AND wire_w_lg_nlillil2357w(0); + wire_n1Olll_dataout <= del_cond_met_0 WHEN nlilO0l = '1' ELSE wire_n1OllO_o; + wire_n1Olll_w_lg_dataout2359w(0) <= wire_n1Olll_dataout AND wire_n1Olli_w_lg_dataout2358w(0); + wire_n1OlOl_dataout <= rclkcmpsq1p(10) WHEN nliii0i = '1' ELSE rclkcmpsq1p(0); + wire_n1OlOO_dataout <= rclkcmpsq1p(11) WHEN nliii0i = '1' ELSE rclkcmpsq1p(1); + wire_n1OO_dataout <= wire_nll10i_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1Ol_dataout; + wire_n1OO0i_dataout <= rclkcmpsq1p(15) WHEN nliii0i = '1' ELSE rclkcmpsq1p(5); + wire_n1OO0l_dataout <= rclkcmpsq1p(16) WHEN nliii0i = '1' ELSE rclkcmpsq1p(6); + wire_n1OO0O_dataout <= rclkcmpsq1p(17) WHEN nliii0i = '1' ELSE rclkcmpsq1p(7); + wire_n1OO1i_dataout <= rclkcmpsq1p(12) WHEN nliii0i = '1' ELSE rclkcmpsq1p(2); + wire_n1OO1l_dataout <= rclkcmpsq1p(13) WHEN nliii0i = '1' ELSE rclkcmpsq1p(3); + wire_n1OO1O_dataout <= rclkcmpsq1p(14) WHEN nliii0i = '1' ELSE rclkcmpsq1p(4); + wire_n1OOii_dataout <= rclkcmpsq1p(18) WHEN nliii0i = '1' ELSE rclkcmpsq1p(8); + wire_n1OOil_dataout <= rclkcmpsq1p(19) WHEN nliii0i = '1' ELSE rclkcmpsq1p(9); + wire_ni_dataout <= ni101i WHEN rwa_6g_en = '1' ELSE nllil0i; + wire_ni000O_dataout <= nliiO0O AND NOT(nliiO1i); + wire_ni00ii_dataout <= nliiO0O AND NOT(nliiO1i); + wire_ni00li_dataout <= (nliiOii AND (nliiO1O OR nliiO1l)) AND wire_nliOOi_dataout; + wire_ni00ll_dataout <= (nliiO0l OR nliiO0i) AND wire_nliOOi_dataout; + wire_ni00OO_dataout <= (wire_w_lg_nliiOli735w(0) AND wire_w_lg_nliiO0O726w(0)) OR (rtruebac2bac AND (nliiOli AND (nliiOii AND (wire_nliOOi_dataout AND ni00iO)))); + wire_ni010i_dataout <= wire_ni01ii_o(3) WHEN wire_w_lg_nliilll798w(0) = '1' ELSE ni1O1O; + wire_ni010l_dataout <= wire_ni01ii_o(4) WHEN wire_w_lg_nliilll798w(0) = '1' ELSE ni1O0i; + wire_ni010O_dataout <= wire_ni01ii_o(5) WHEN wire_w_lg_nliilll798w(0) = '1' ELSE ni1O0l; + wire_ni011i_dataout <= wire_ni01il_o(4) WHEN nliillO = '1' ELSE wire_ni010O_dataout; + wire_ni011l_dataout <= wire_ni01ii_o(1) WHEN wire_w_lg_nliilll798w(0) = '1' ELSE ni1llO; + wire_ni011O_dataout <= wire_ni01ii_o(2) WHEN wire_w_lg_nliilll798w(0) = '1' ELSE ni1O1l; + wire_ni0i_dataout <= wire_nll0il_dataout AND rwa_6g_en; + wire_ni0iiO_dataout <= wire_ni0ili_dataout OR (rtruebac2bac AND (nliiOii AND (nliiOli AND (wire_nliOOi_dataout AND ni00Oi)))); + wire_ni0ili_dataout <= ((nliiOli AND nliiOii) AND wire_w_lg_nliiO0O726w(0)) AND (wire_nliOOi_dataout AND ni00il); + wire_ni0l_dataout <= wire_nll0iO_dataout AND rwa_6g_en; + wire_ni0O_dataout <= wire_nll0li_dataout AND rwa_6g_en; + wire_ni100i_dataout <= ni11lO OR nliiO1i; + wire_ni100l_dataout <= wire_nllOli_o OR nliiO1i; + wire_ni100O_dataout <= wire_ni10iO_dataout OR nliiO1i; + wire_ni101O_dataout <= ni11OO AND NOT(nliiO1i); + wire_ni10ii_dataout <= wire_nllOiO_o AND NOT(nliiO1i); + wire_ni10il_dataout <= wire_ni10lO_dataout AND NOT(nliiO1i); + wire_ni10iO_dataout <= (nliil1O OR ni11ll) WHEN nliO11i = '1' ELSE nliil1O; + wire_ni10lO_dataout <= (nliil0i OR ni110l) WHEN nliO11i = '1' ELSE nliil0i; + wire_ni110O_dataout <= ni101l AND NOT(nliiO1i); + wire_ni11ii_dataout <= ni1i1l AND NOT(nliiO1i); + wire_ni11il_dataout <= ni1i1O AND NOT(nliiO1i); + wire_ni11iO_dataout <= ni1i0i AND NOT(nliiO1i); + wire_ni11li_dataout <= ni1i0l AND NOT(nliiO1i); + wire_ni1i_dataout <= wire_nll00l_dataout AND rwa_6g_en; + wire_ni1iii_dataout <= wire_ni1ilO_dataout AND NOT(nliiO1i); + wire_ni1iil_dataout <= wire_ni1iOi_dataout AND NOT(nliiO1i); + wire_ni1iiO_dataout <= wire_ni1iOl_dataout AND NOT(nliiO1i); + wire_ni1ili_dataout <= wire_ni1iOO_dataout AND NOT(nliiO1i); + wire_ni1ill_dataout <= wire_ni1l1i_dataout AND NOT(nliiO1i); + wire_ni1ilO_dataout <= wire_ni1l1l_dataout AND NOT(nliil0l); + wire_ni1iOi_dataout <= wire_ni1l1O_dataout AND NOT(nliil0l); + wire_ni1iOl_dataout <= n0Ol0O WHEN nliil0l = '1' ELSE wire_ni1l0i_dataout; + wire_ni1iOO_dataout <= wire_ni1l0l_dataout AND NOT(nliil0l); + wire_ni1l_dataout <= wire_nll00O_dataout AND rwa_6g_en; + wire_ni1l0i_dataout <= wire_ni1liO_o(3) WHEN wire_ni1lli_o = '1' ELSE wire_ni1lii_o(3); + wire_ni1l0l_dataout <= wire_ni1liO_o(4) WHEN wire_ni1lli_o = '1' ELSE wire_ni1lii_o(4); + wire_ni1l0O_dataout <= wire_ni1liO_o(5) WHEN wire_ni1lli_o = '1' ELSE wire_ni1lii_o(5); + wire_ni1l1i_dataout <= n0Ol0O WHEN nliil0l = '1' ELSE wire_ni1l0O_dataout; + wire_ni1l1l_dataout <= wire_ni1liO_o(1) WHEN wire_ni1lli_o = '1' ELSE wire_ni1lii_o(1); + wire_ni1l1O_dataout <= wire_ni1liO_o(2) WHEN wire_ni1lli_o = '1' ELSE wire_ni1lii_o(2); + wire_ni1lOi_dataout <= nliilli AND NOT(nliiO1i); + wire_ni1O_dataout <= wire_nll0ii_dataout AND rwa_6g_en; + wire_ni1Oii_dataout <= wire_ni1OlO_dataout AND NOT(nliiO1i); + wire_ni1Oil_dataout <= wire_ni1OOi_dataout AND NOT(nliiO1i); + wire_ni1OiO_dataout <= wire_ni1OOl_dataout AND NOT(nliiO1i); + wire_ni1Oli_dataout <= wire_ni1OOO_dataout AND NOT(nliiO1i); + wire_ni1Oll_dataout <= wire_ni011i_dataout AND NOT(nliiO1i); + wire_ni1OlO_dataout <= wire_ni01il_o(0) WHEN nliillO = '1' ELSE wire_ni011l_dataout; + wire_ni1OOi_dataout <= wire_ni01il_o(1) WHEN nliillO = '1' ELSE wire_ni011O_dataout; + wire_ni1OOl_dataout <= wire_ni01il_o(2) WHEN nliillO = '1' ELSE wire_ni010i_dataout; + wire_ni1OOO_dataout <= wire_ni01il_o(3) WHEN nliillO = '1' ELSE wire_ni010l_dataout; + wire_niii_dataout <= wire_nll0ll_dataout AND rwa_6g_en; + wire_niii0i_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nil1Oi_dataout; + wire_niii0l_dataout <= wire_niOlOi_dataout WHEN nlil0l = '1' ELSE wire_nil1Ol_dataout; + wire_niii0O_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nil1OO_dataout; + wire_niii1l_dataout <= wire_niOllO_dataout WHEN nlil0l = '1' ELSE wire_nil1ll_dataout; + wire_niii1O_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nil1lO_dataout; + wire_niiiii_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nil01i_dataout; + wire_niiiil_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nil01l_dataout; + wire_niiiiO_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nil01O_dataout; + wire_niiili_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nil00i_dataout; + wire_niiill_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nil00l_dataout; + wire_niiilO_dataout <= wire_nil00O_dataout AND NOT(nlil0l); + wire_niiiOi_dataout <= nii0li WHEN nlil0l = '1' ELSE wire_nil0ii_dataout; + wire_niiiOl_dataout <= wire_nil0il_dataout AND NOT(nlil0l); + wire_niiiOO_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nil0iO_dataout; + wire_niil_dataout <= wire_nll0lO_dataout AND rwa_6g_en; + wire_niil0i_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nil0Oi_dataout; + wire_niil0l_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nil0Ol_dataout; + wire_niil0O_dataout <= wire_niOlOi_dataout WHEN nlil0l = '1' ELSE wire_nil0OO_dataout; + wire_niil1i_dataout <= wire_nil0li_dataout AND NOT(nlil0l); + wire_niil1l_dataout <= wire_nil0ll_dataout OR nlil0l; + wire_niil1O_dataout <= wire_niOllO_dataout WHEN nlil0l = '1' ELSE wire_nil0lO_dataout; + wire_niilii_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nili1i_dataout; + wire_niilil_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nili1l_dataout; + wire_niiliO_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN nlil0l = '1' ELSE wire_nili1O_dataout; + wire_niilli_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nili0i_dataout; + wire_niilll_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nili0l_dataout; + wire_niillO_dataout <= nii0Oi WHEN nlil0l = '1' ELSE wire_nili0O_dataout; + wire_niilOi_dataout <= wire_niliii_dataout AND NOT(nlil0l); + wire_niilOl_dataout <= wire_niliiO_dataout AND NOT(nlil0l); + wire_niilOO_dataout <= wire_nilill_dataout AND NOT(nlil0l); + wire_niiO_dataout <= wire_nll0Oi_dataout AND rwa_6g_en; + wire_niiO0i_dataout <= wire_nllOll_data_out2(2) WHEN nlil10O = '1' ELSE ni0lli; + wire_niiO0l_dataout <= wire_nllOll_data_out2(3) WHEN nlil10O = '1' ELSE ni0lll; + wire_niiO0O_dataout <= wire_nllOll_data_out2(4) WHEN nlil10O = '1' ELSE ni0llO; + wire_niiO1i_dataout <= wire_nililO_dataout OR nlil0l; + wire_niiO1l_dataout <= wire_nllOll_data_out2(0) WHEN nlil10O = '1' ELSE ni00Ol; + wire_niiO1O_dataout <= wire_nllOll_data_out2(1) WHEN nlil10O = '1' ELSE ni0liO; + wire_niiOi_dataout <= wire_nliOOO_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1il_dataout; + wire_niiOii_dataout <= wire_nllOll_data_out2(5) WHEN nlil10O = '1' ELSE ni0lOi; + wire_niiOil_dataout <= wire_nllOll_data_out2(6) WHEN nlil10O = '1' ELSE ni0lOl; + wire_niiOiO_dataout <= wire_nllOll_data_out2(7) WHEN nlil10O = '1' ELSE ni0lOO; + wire_niiOl_dataout <= wire_nll11i_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1ll_dataout; + wire_niiOli_dataout <= wire_nllOll_data_out2(8) WHEN nlil10O = '1' ELSE ni0O1i; + wire_niiOll_dataout <= wire_nllOll_data_out2(9) WHEN nlil10O = '1' ELSE ni0O1l; + wire_niiOO_dataout <= wire_nll11l_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1lO_dataout; + wire_nil00i_dataout <= wire_nllOll_data_out1(8) WHEN nlil10O = '1' ELSE wire_nill0O_dataout; + wire_nil00l_dataout <= wire_nllOll_data_out1(9) WHEN nlil10O = '1' ELSE wire_nillii_dataout; + wire_nil00O_dataout <= wire_nllOll_data_out1(10) WHEN nlil10O = '1' ELSE wire_nillil_dataout; + wire_nil01i_dataout <= wire_nllOll_data_out1(5) WHEN nlil10O = '1' ELSE wire_nill1O_dataout; + wire_nil01l_dataout <= wire_nllOll_data_out1(6) WHEN nlil10O = '1' ELSE wire_nill0i_dataout; + wire_nil01O_dataout <= wire_nllOll_data_out1(7) WHEN nlil10O = '1' ELSE wire_nill0l_dataout; + wire_nil0i_dataout <= wire_nll10O_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi01i_dataout; + wire_nil0ii_dataout <= wire_nllOll_data_out1(11) WHEN nlil10O = '1' ELSE wire_nilliO_dataout; + wire_nil0il_dataout <= wire_nllOll_data_out1(12) WHEN nlil10O = '1' ELSE wire_nillli_dataout; + wire_nil0iO_dataout <= wire_nllOll_data_out1(13) WHEN nlil10O = '1' ELSE wire_nillll_dataout; + wire_nil0l_dataout <= wire_nll1ii_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi01l_dataout; + wire_nil0li_dataout <= wire_nllOll_data_out1(14) AND nlil10O; + wire_nil0ll_dataout <= wire_nllOll_data_out1(15) OR NOT(nlil10O); + wire_nil0lO_dataout <= wire_nllOlO_data_out1(0) WHEN nlil10O = '1' ELSE wire_nilllO_dataout; + wire_nil0O_dataout <= wire_nll1il_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi01O_dataout; + wire_nil0Oi_dataout <= wire_nllOlO_data_out1(1) WHEN nlil10O = '1' ELSE wire_nillOi_dataout; + wire_nil0Ol_dataout <= wire_nllOlO_data_out1(2) WHEN nlil10O = '1' ELSE wire_nillOl_dataout; + wire_nil0OO_dataout <= wire_nllOlO_data_out1(3) WHEN nlil10O = '1' ELSE wire_nillOO_dataout; + wire_nil10i_dataout <= wire_nllOlO_data_out2(3) WHEN nlil10O = '1' ELSE ni0O0O; + wire_nil10l_dataout <= wire_nllOlO_data_out2(4) WHEN nlil10O = '1' ELSE ni0Oii; + wire_nil10O_dataout <= wire_nllOlO_data_out2(5) WHEN nlil10O = '1' ELSE ni0Oil; + wire_nil11i_dataout <= wire_nllOlO_data_out2(0) WHEN nlil10O = '1' ELSE ni0O1O; + wire_nil11l_dataout <= wire_nllOlO_data_out2(1) WHEN nlil10O = '1' ELSE ni0O0i; + wire_nil11O_dataout <= wire_nllOlO_data_out2(2) WHEN nlil10O = '1' ELSE ni0O0l; + wire_nil1i_dataout <= wire_nll11O_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1Oi_dataout; + wire_nil1ii_dataout <= wire_nllOlO_data_out2(6) WHEN nlil10O = '1' ELSE ni0OiO; + wire_nil1il_dataout <= wire_nllOlO_data_out2(7) WHEN nlil10O = '1' ELSE ni0Oli; + wire_nil1iO_dataout <= wire_nllOlO_data_out2(8) WHEN nlil10O = '1' ELSE ni0Oll; + wire_nil1l_dataout <= wire_nll10i_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1Ol_dataout; + wire_nil1li_dataout <= wire_nllOlO_data_out2(9) WHEN nlil10O = '1' ELSE ni0OlO; + wire_nil1ll_dataout <= wire_nllOll_data_out1(0) WHEN nlil10O = '1' ELSE wire_niliOi_dataout; + wire_nil1lO_dataout <= wire_nllOll_data_out1(1) WHEN nlil10O = '1' ELSE wire_niliOl_dataout; + wire_nil1O_dataout <= wire_nll10l_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi1OO_dataout; + wire_nil1Oi_dataout <= wire_nllOll_data_out1(2) WHEN nlil10O = '1' ELSE wire_niliOO_dataout; + wire_nil1Ol_dataout <= wire_nllOll_data_out1(3) WHEN nlil10O = '1' ELSE wire_nill1i_dataout; + wire_nil1OO_dataout <= wire_nllOll_data_out1(4) WHEN nlil10O = '1' ELSE wire_nill1l_dataout; + wire_nili_dataout <= wire_nll0Ol_dataout AND rwa_6g_en; + wire_nili0i_dataout <= wire_nllOlO_data_out1(7) WHEN nlil10O = '1' ELSE wire_nilO0i_dataout; + wire_nili0l_dataout <= wire_nllOlO_data_out1(8) WHEN nlil10O = '1' ELSE wire_nilO0l_dataout; + wire_nili0O_dataout <= wire_nllOlO_data_out1(9) WHEN nlil10O = '1' ELSE wire_nilO0O_dataout; + wire_nili1i_dataout <= wire_nllOlO_data_out1(4) WHEN nlil10O = '1' ELSE wire_nilO1i_dataout; + wire_nili1l_dataout <= wire_nllOlO_data_out1(5) WHEN nlil10O = '1' ELSE wire_nilO1l_dataout; + wire_nili1O_dataout <= wire_nllOlO_data_out1(6) WHEN nlil10O = '1' ELSE wire_nilO1O_dataout; + wire_nilii_dataout <= wire_nll1iO_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi00i_dataout; + wire_niliii_dataout <= wire_nllOlO_data_out1(10) WHEN nlil10O = '1' ELSE wire_nilOii_dataout; + wire_niliil_dataout <= wire_nllOlO_data_out1(11) WHEN nlil10O = '1' ELSE nii0li; + wire_niliiO_dataout <= wire_nllOlO_data_out1(12) WHEN nlil10O = '1' ELSE wire_nilOil_dataout; + wire_nilil_dataout <= wire_nll1li_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi00l_dataout; + wire_nilili_dataout <= wire_nllOlO_data_out1(13) WHEN nlil10O = '1' ELSE nii0Oi; + wire_nilill_dataout <= wire_nllOlO_data_out1(14) AND nlil10O; + wire_nililO_dataout <= wire_nllOlO_data_out1(15) OR NOT(nlil10O); + wire_niliO_dataout <= wire_nll01l_dataout AND rwa_6g_en; + wire_niliOi_dataout <= ni0OOi WHEN nlil10l = '1' ELSE wire_nilOiO_dataout; + wire_niliOl_dataout <= ni0OOl WHEN nlil10l = '1' ELSE wire_nilOli_dataout; + wire_niliOO_dataout <= ni0OOO WHEN nlil10l = '1' ELSE wire_nilOll_dataout; + wire_nill_dataout <= wire_nll0OO_dataout AND rwa_6g_en; + wire_nill0i_dataout <= nii10i WHEN nlil10l = '1' ELSE wire_nilOOO_dataout; + wire_nill0l_dataout <= nii10l WHEN nlil10l = '1' ELSE wire_niO11i_dataout; + wire_nill0O_dataout <= nii10O WHEN nlil10l = '1' ELSE wire_niO11l_dataout; + wire_nill1i_dataout <= nii11i WHEN nlil10l = '1' ELSE wire_nilOlO_dataout; + wire_nill1l_dataout <= nii11l WHEN nlil10l = '1' ELSE wire_nilOOi_dataout; + wire_nill1O_dataout <= nii11O WHEN nlil10l = '1' ELSE wire_nilOOl_dataout; + wire_nilli_dataout <= wire_nll01O_dataout AND rwa_6g_en; + wire_nillii_dataout <= nii1ii WHEN nlil10l = '1' ELSE wire_niO11O_dataout; + wire_nillil_dataout <= nii1il AND nlil10l; + wire_nilliO_dataout <= nii1iO WHEN nlil10l = '1' ELSE nii0li; + wire_nilll_dataout <= wire_nll00i_dataout AND rwa_6g_en; + wire_nillli_dataout <= nii1li AND nlil10l; + wire_nillll_dataout <= nii1ll WHEN nlil10l = '1' ELSE nii0Oi; + wire_nilllO_dataout <= nii1Ol WHEN nlil10l = '1' ELSE wire_niO0iO_dataout; + wire_nillO_dataout <= wire_nll00l_dataout AND rwa_6g_en; + wire_nillOi_dataout <= nii1OO WHEN nlil10l = '1' ELSE wire_niO0li_dataout; + wire_nillOl_dataout <= nii01i WHEN nlil10l = '1' ELSE wire_niO0ll_dataout; + wire_nillOO_dataout <= nii01l WHEN nlil10l = '1' ELSE wire_niO0lO_dataout; + wire_nilO_dataout <= wire_nlli1i_dataout AND rwa_6g_en; + wire_nilO0i_dataout <= nii00O WHEN nlil10l = '1' ELSE wire_niOi1i_dataout; + wire_nilO0l_dataout <= nii0ii WHEN nlil10l = '1' ELSE wire_niOi1l_dataout; + wire_nilO0O_dataout <= nii0il WHEN nlil10l = '1' ELSE wire_niOi1O_dataout; + wire_nilO1i_dataout <= nii01O WHEN nlil10l = '1' ELSE wire_niO0Oi_dataout; + wire_nilO1l_dataout <= nii00i WHEN nlil10l = '1' ELSE wire_niO0Ol_dataout; + wire_nilO1O_dataout <= nii00l WHEN nlil10l = '1' ELSE wire_niO0OO_dataout; + wire_nilOi_dataout <= wire_nll00O_dataout AND rwa_6g_en; + wire_nilOii_dataout <= nii0iO AND nlil10l; + wire_nilOil_dataout <= nii0ll AND nlil10l; + wire_nilOiO_dataout <= wire_niO1Ol_dataout WHEN nii0Oi = '1' ELSE wire_niO10i_dataout; + wire_nilOl_dataout <= wire_nll0ii_dataout AND rwa_6g_en; + wire_nilOli_dataout <= wire_niO1OO_dataout WHEN nii0Oi = '1' ELSE wire_niO10l_dataout; + wire_nilOll_dataout <= wire_niO01i_dataout WHEN nii0Oi = '1' ELSE wire_niO10O_dataout; + wire_nilOlO_dataout <= wire_niO01l_dataout WHEN nii0Oi = '1' ELSE wire_niO1ii_dataout; + wire_nilOO_dataout <= wire_nll0il_dataout AND rwa_6g_en; + wire_nilOOi_dataout <= wire_niO01O_dataout WHEN nii0Oi = '1' ELSE wire_niO1il_dataout; + wire_nilOOl_dataout <= wire_niO00i_dataout WHEN nii0Oi = '1' ELSE wire_niO1iO_dataout; + wire_nilOOO_dataout <= wire_niO00l_dataout WHEN nii0Oi = '1' ELSE wire_niO1li_dataout; + wire_niO_dataout <= gen2ngen1 WHEN rindv_rx = '1' ELSE gen2ngen1_bundle; + wire_niO00i_dataout <= rclkcmpsq1p(15) OR nlil11l; + wire_niO00l_dataout <= rclkcmpsq1p(16) AND NOT(nlil11l); + wire_niO00O_dataout <= rclkcmpsq1p(17) OR nlil11l; + wire_niO01i_dataout <= rclkcmpsq1p(12) AND NOT(nlil11l); + wire_niO01l_dataout <= rclkcmpinsertpad WHEN nlil11l = '1' ELSE rclkcmpsq1p(13); + wire_niO01O_dataout <= rclkcmpsq1p(14) AND NOT(nlil11l); + wire_niO0i_dataout <= nliO1l WHEN rwa_6g_en = '1' ELSE wire_nlOiiOi_dataout; + wire_niO0ii_dataout <= rclkcmpsq1p(18) OR nlil11l; + wire_niO0il_dataout <= rclkcmpsq1p(19) OR nlil11l; + wire_niO0iO_dataout <= wire_niOiOl_dataout WHEN nii0Oi = '1' ELSE wire_niOi0i_dataout; + wire_niO0l_dataout <= nlliiO WHEN rwa_6g_en = '1' ELSE wire_nlOiiOl_dataout; + wire_niO0li_dataout <= wire_niOiOO_dataout WHEN nii0Oi = '1' ELSE wire_niOi0l_dataout; + wire_niO0ll_dataout <= wire_niOl1i_dataout WHEN nii0Oi = '1' ELSE wire_niOi0O_dataout; + wire_niO0lO_dataout <= wire_niOl1l_dataout WHEN nii0Oi = '1' ELSE wire_niOiii_dataout; + wire_niO0O_dataout <= nllili WHEN rwa_6g_en = '1' ELSE wire_nlOiiOO_dataout; + wire_niO0Oi_dataout <= wire_niOl1O_dataout WHEN nii0Oi = '1' ELSE wire_niOiil_dataout; + wire_niO0Ol_dataout <= wire_niOl0i_dataout WHEN nii0Oi = '1' ELSE wire_niOiiO_dataout; + wire_niO0OO_dataout <= wire_niOl0l_dataout WHEN nii0Oi = '1' ELSE wire_niOili_dataout; + wire_niO10i_dataout <= rclkcmpinsertpad WHEN nlil11i = '1' ELSE rclkcmpsq1n(10); + wire_niO10l_dataout <= rclkcmpsq1n(11) OR nlil11i; + wire_niO10O_dataout <= rclkcmpsq1n(12) OR nlil11i; + wire_niO11i_dataout <= wire_niO00O_dataout WHEN nii0Oi = '1' ELSE wire_niO1ll_dataout; + wire_niO11l_dataout <= wire_niO0ii_dataout WHEN nii0Oi = '1' ELSE wire_niO1lO_dataout; + wire_niO11O_dataout <= wire_niO0il_dataout WHEN nii0Oi = '1' ELSE wire_niO1Oi_dataout; + wire_niO1i_dataout <= wire_nll0iO_dataout AND rwa_6g_en; + wire_niO1ii_dataout <= wire_w_lg_rclkcmpinsertpad655w(0) WHEN nlil11i = '1' ELSE rclkcmpsq1n(13); + wire_niO1il_dataout <= rclkcmpsq1n(14) OR nlil11i; + wire_niO1iO_dataout <= rclkcmpsq1n(15) AND NOT(nlil11i); + wire_niO1l_dataout <= wire_nll0li_dataout AND rwa_6g_en; + wire_niO1li_dataout <= rclkcmpsq1n(16) OR nlil11i; + wire_niO1ll_dataout <= rclkcmpsq1n(17) AND NOT(nlil11i); + wire_niO1lO_dataout <= rclkcmpsq1n(18) AND NOT(nlil11i); + wire_niO1O_dataout <= wire_nll0ll_dataout AND rwa_6g_en; + wire_niO1Oi_dataout <= rclkcmpsq1n(19) AND NOT(nlil11i); + wire_niO1Ol_dataout <= wire_w_lg_rclkcmpinsertpad655w(0) WHEN nlil11l = '1' ELSE rclkcmpsq1p(10); + wire_niO1OO_dataout <= rclkcmpsq1p(11) AND NOT(nlil11l); + wire_niOi_dataout <= wire_nlli1l_dataout AND rwa_6g_en; + wire_niOi0i_dataout <= rclkcmpinsertpad WHEN nlil11O = '1' ELSE rclkcmpsq1n(10); + wire_niOi0l_dataout <= rclkcmpsq1n(11) OR nlil11O; + wire_niOi0O_dataout <= rclkcmpsq1n(12) OR nlil11O; + wire_niOi1i_dataout <= wire_niOl0O_dataout WHEN nii0Oi = '1' ELSE wire_niOill_dataout; + wire_niOi1l_dataout <= wire_niOlii_dataout WHEN nii0Oi = '1' ELSE wire_niOilO_dataout; + wire_niOi1O_dataout <= wire_niOlil_dataout WHEN nii0Oi = '1' ELSE wire_niOiOi_dataout; + wire_niOii_dataout <= nllill WHEN rwa_6g_en = '1' ELSE wire_nlOil1i_dataout; + wire_niOiii_dataout <= wire_w_lg_rclkcmpinsertpad655w(0) WHEN nlil11O = '1' ELSE rclkcmpsq1n(13); + wire_niOiil_dataout <= rclkcmpsq1n(14) OR nlil11O; + wire_niOiiO_dataout <= rclkcmpsq1n(15) AND NOT(nlil11O); + wire_niOil_dataout <= nllilO WHEN rwa_6g_en = '1' ELSE wire_nlOil1l_dataout; + wire_niOili_dataout <= rclkcmpsq1n(16) OR nlil11O; + wire_niOill_dataout <= rclkcmpsq1n(17) AND NOT(nlil11O); + wire_niOilO_dataout <= rclkcmpsq1n(18) AND NOT(nlil11O); + wire_niOiO_dataout <= nlliOi WHEN rwa_6g_en = '1' ELSE wire_nlOil1O_dataout; + wire_niOiOi_dataout <= rclkcmpsq1n(19) AND NOT(nlil11O); + wire_niOiOl_dataout <= wire_w_lg_rclkcmpinsertpad655w(0) WHEN nlil10i = '1' ELSE rclkcmpsq1p(10); + wire_niOiOO_dataout <= rclkcmpsq1p(11) AND NOT(nlil10i); + wire_niOl_dataout <= ni101l WHEN rwa_6g_en = '1' ELSE nlO1OiO; + wire_niOl0i_dataout <= rclkcmpsq1p(15) OR nlil10i; + wire_niOl0l_dataout <= rclkcmpsq1p(16) AND NOT(nlil10i); + wire_niOl0O_dataout <= rclkcmpsq1p(17) OR nlil10i; + wire_niOl1i_dataout <= rclkcmpsq1p(12) AND NOT(nlil10i); + wire_niOl1l_dataout <= rclkcmpinsertpad WHEN nlil10i = '1' ELSE rclkcmpsq1p(13); + wire_niOl1O_dataout <= rclkcmpsq1p(14) AND NOT(nlil10i); + wire_niOli_dataout <= nlliOl WHEN rwa_6g_en = '1' ELSE wire_nlOil0i_dataout; + wire_niOlii_dataout <= rclkcmpsq1p(18) OR nlil10i; + wire_niOlil_dataout <= rclkcmpsq1p(19) OR nlil10i; + wire_niOll_dataout <= nlliOO WHEN rwa_6g_en = '1' ELSE wire_nlOil0l_dataout; + wire_niOllO_dataout <= wire_nii0lO_w_lg_nii0Oi640w(0) WHEN rclkcmpinsertpad = '1' ELSE nii0Oi; + wire_niOlO_dataout <= nlll1i WHEN rwa_6g_en = '1' ELSE wire_nlOil0O_dataout; + wire_niOlOi_dataout <= nii0Oi WHEN rclkcmpinsertpad = '1' ELSE wire_nii0lO_w_lg_nii0Oi640w(0); + wire_niOO_dataout <= ni1i1l WHEN rwa_6g_en = '1' ELSE nlO1OOi; + wire_niOOi_dataout <= nlll1l WHEN rwa_6g_en = '1' ELSE wire_nlOilii_dataout; + wire_niOOl_dataout <= nlll1O WHEN rwa_6g_en = '1' ELSE wire_nlO0Oli_dataout; + wire_niOOO_dataout <= nlll0i WHEN rwa_6g_en = '1' ELSE wire_nlO0Oll_dataout; + wire_nl000i_dataout <= wire_nl0OlO_dataout WHEN nlil1ll = '1' ELSE niOOii; + wire_nl000l_dataout <= nl11lO WHEN nlil1ll = '1' ELSE niOOil; + wire_nl000O_dataout <= niOOil WHEN nlil1ll = '1' ELSE niOOiO; + wire_nl001i_dataout <= wire_nl0OiO_dataout WHEN nlil1ll = '1' ELSE niOO0i; + wire_nl001l_dataout <= wire_nl0Oli_dataout WHEN nlil1ll = '1' ELSE niOO0l; + wire_nl001O_dataout <= wire_nl0Oll_dataout WHEN nlil1ll = '1' ELSE niOO0O; + wire_nl00i_dataout <= (nlillOO OR ni1O0O) AND rwa_6g_en; + wire_nl00ii_dataout <= niOOiO WHEN nlil1ll = '1' ELSE niOOli; + wire_nl00il_dataout <= niOOli WHEN nlil1ll = '1' ELSE niOOll; + wire_nl00iO_dataout <= niOOll WHEN nlil1ll = '1' ELSE niOOlO; + wire_nl00l_dataout <= ni000i AND rwa_6g_en; + wire_nl00li_dataout <= niOOlO WHEN nlil1ll = '1' ELSE niOOOi; + wire_nl00ll_dataout <= niOOOi WHEN nlil1ll = '1' ELSE niOOOl; + wire_nl00lO_dataout <= niOOOl WHEN nlil1ll = '1' ELSE niOOOO; + wire_nl00O_dataout <= wire_nliOOi_dataout WHEN rwa_6g_en = '1' ELSE wire_nlOi10l_dataout; + wire_nl00O_w_lg_dataout123w(0) <= NOT wire_nl00O_dataout; + wire_nl00Oi_dataout <= niOOOO WHEN nlil1ll = '1' ELSE nl111i; + wire_nl00Ol_dataout <= nl111i WHEN nlil1ll = '1' ELSE nl111l; + wire_nl00OO_dataout <= nl111l WHEN nlil1ll = '1' ELSE nl111O; + wire_nl010i_dataout <= wire_nl0liO_dataout AND NOT(nlil00l); + wire_nl010l_dataout <= wire_nl0lli_dataout AND NOT(nlil00l); + wire_nl010O_dataout <= wire_nl0lll_dataout AND NOT(nlil00l); + wire_nl011i_dataout <= wire_nl0l0O_dataout AND NOT(nlil00l); + wire_nl011l_dataout <= wire_nl0lii_dataout AND NOT(nlil00l); + wire_nl011O_dataout <= wire_nl0lil_dataout AND NOT(nlil00l); + wire_nl01i_dataout <= nllO1O AND rwa_6g_en; + wire_nl01ii_dataout <= wire_nl0llO_dataout AND NOT(nlil00l); + wire_nl01il_dataout <= wire_nl0lOi_dataout AND NOT(nlil00l); + wire_nl01iO_dataout <= wire_nl0lOl_dataout AND NOT(nlil00l); + wire_nl01l_dataout <= nllO0i AND rwa_6g_en; + wire_nl01li_dataout <= nlil1ii WHEN nlil1ll = '1' ELSE niii1i; + wire_nl01ll_dataout <= (((wire_nl0O1O_o(4) OR wire_nl0O1O_o(3)) OR wire_nl0O1O_o(2)) OR wire_nl0O1O_o(1)) WHEN nlil1ll = '1' ELSE niOlOl; + wire_nl01lO_dataout <= nlil1il WHEN nlil1ll = '1' ELSE niOlOO; + wire_nl01O_dataout <= nllO0l AND rwa_6g_en; + wire_nl01Oi_dataout <= nlil1iO WHEN nlil1ll = '1' ELSE niOO1i; + wire_nl01Ol_dataout <= (((wire_nl0Oii_o(18) OR wire_nl0Oii_o(17)) OR wire_nl0Oii_o(16)) OR wire_nl0Oii_o(15)) WHEN nlil1ll = '1' ELSE niOO1l; + wire_nl01OO_dataout <= wire_nl0Oil_dataout WHEN nlil1ll = '1' ELSE niOO1O; + wire_nl0i_dataout <= nO AND NOT(scan_mode); + wire_nl0i_w_lg_dataout4w(0) <= NOT wire_nl0i_dataout; + wire_nl0i0i_dataout <= nl110O WHEN nlil1ll = '1' ELSE nl11ii; + wire_nl0i0l_dataout <= nl11ii WHEN nlil1ll = '1' ELSE nl11il; + wire_nl0i0O_dataout <= nl11il WHEN nlil1ll = '1' ELSE nl11iO; + wire_nl0i1i_dataout <= nl111O WHEN nlil1ll = '1' ELSE nl110i; + wire_nl0i1l_dataout <= nl110i WHEN nlil1ll = '1' ELSE nl110l; + wire_nl0i1O_dataout <= nl110l WHEN nlil1ll = '1' ELSE nl110O; + wire_nl0ii_dataout <= (rmatchen AND wire_w_lg_rgenericfifo32w(0)) WHEN rwa_6g_en = '1' ELSE ((wire_w_lg_rgenericfifo32w(0) AND (wire_w_lg_w_lg_w_lg_w_dskwclksel_range33w34w35w36w(0) OR (NOT (nlilO1O18 XOR nlilO1O17)))) AND (nlilO1i20 XOR nlilO1i19)); + wire_nl0ii_w_lg_w_lg_dataout138w141w(0) <= wire_nl0ii_w_lg_dataout138w(0) AND wire_nlill1O28_w_lg_q140w(0); + wire_nl0ii_w_lg_dataout138w(0) <= wire_nl0ii_dataout AND wire_nl00O_dataout; + wire_nl0iii_dataout <= nl11iO WHEN nlil1ll = '1' ELSE nl11li; + wire_nl0iil_dataout <= nl11li WHEN nlil1ll = '1' ELSE nl11ll; + wire_nl0iiO_dataout <= nl11ll WHEN nlil1ll = '1' ELSE nl11lO; + wire_nl0il_dataout <= n0l0iO WHEN rwa_6g_en = '1' ELSE nlllO0l; + wire_nl0ili_dataout <= nl1i1O WHEN nlil1ll = '1' ELSE nl11Ol; + wire_nl0ill_dataout <= nl11Ol WHEN nlil1ll = '1' ELSE nl11OO; + wire_nl0ilO_dataout <= nl11OO WHEN nlil1ll = '1' ELSE nl101i; + wire_nl0iO_dataout <= n0l0li WHEN rwa_6g_en = '1' ELSE nlllO0O; + wire_nl0iOi_dataout <= nl101i WHEN nlil1ll = '1' ELSE nl101l; + wire_nl0iOl_dataout <= nl101l WHEN nlil1ll = '1' ELSE nl101O; + wire_nl0iOO_dataout <= nl101O WHEN nlil1ll = '1' ELSE nl100i; + wire_nl0l0i_dataout <= nl10ii WHEN nlil1ll = '1' ELSE nl10il; + wire_nl0l0l_dataout <= nl10il WHEN nlil1ll = '1' ELSE nl10iO; + wire_nl0l0O_dataout <= nl10iO WHEN nlil1ll = '1' ELSE nl10li; + wire_nl0l1i_dataout <= nl100i WHEN nlil1ll = '1' ELSE nl100l; + wire_nl0l1l_dataout <= nl100l WHEN nlil1ll = '1' ELSE nl100O; + wire_nl0l1O_dataout <= nl100O WHEN nlil1ll = '1' ELSE nl10ii; + wire_nl0li_dataout <= n0l0ll WHEN rwa_6g_en = '1' ELSE nlllOii; + wire_nl0lii_dataout <= nl10li WHEN nlil1ll = '1' ELSE nl10ll; + wire_nl0lil_dataout <= nl10ll WHEN nlil1ll = '1' ELSE nl10lO; + wire_nl0liO_dataout <= nl10lO WHEN nlil1ll = '1' ELSE nl10Oi; + wire_nl0ll_dataout <= n0l0lO WHEN rwa_6g_en = '1' ELSE nlllOil; + wire_nl0lli_dataout <= nl10Oi WHEN nlil1ll = '1' ELSE nl10Ol; + wire_nl0lll_dataout <= nl10Ol WHEN nlil1ll = '1' ELSE nl10OO; + wire_nl0llO_dataout <= nl10OO WHEN nlil1ll = '1' ELSE nl1i1i; + wire_nl0lO_dataout <= n0l0Oi WHEN rwa_6g_en = '1' ELSE nlllOiO; + wire_nl0lOi_dataout <= nl1i1i WHEN nlil1ll = '1' ELSE nl1i1l; + wire_nl0lOl_dataout <= nl1i1l WHEN nlil1ll = '1' ELSE nl1i1O; + wire_nl0Oi_dataout <= n0l0Ol WHEN rwa_6g_en = '1' ELSE nlllOli; + wire_nl0Oil_dataout <= wire_nl0OOi_o(0) AND NOT(nlil1li); + wire_nl0OiO_dataout <= wire_nl0OOi_o(1) AND NOT(nlil1li); + wire_nl0Ol_dataout <= n0l0OO WHEN rwa_6g_en = '1' ELSE nlllOll; + wire_nl0Oli_dataout <= wire_nl0OOi_o(2) AND NOT(nlil1li); + wire_nl0Oll_dataout <= wire_nl0OOi_o(3) AND NOT(nlil1li); + wire_nl0OlO_dataout <= wire_nl0OOi_o(4) AND NOT(nlil1li); + wire_nl0OO_dataout <= n0li1i WHEN rwa_6g_en = '1' ELSE nlllOlO; + wire_nl10i_dataout <= ni000i WHEN rwa_6g_en = '1' ELSE nlllliO; + wire_nl10l_dataout <= nlllii AND rwa_6g_en; + wire_nl10O_dataout <= nlllil AND rwa_6g_en; + wire_nl11i_dataout <= nlll0l WHEN rwa_6g_en = '1' ELSE wire_nlO0OlO_dataout; + wire_nl11l_dataout <= nlll0O WHEN rwa_6g_en = '1' ELSE wire_nlOiliO_dataout; + wire_nl11O_dataout <= ((nlillOO OR ni1O0O) OR (NOT (nlilliO24 XOR nlilliO23))) WHEN rwa_6g_en = '1' ELSE (wire_nii_w_lg_w_lg_nllllii47w48w(0) OR (NOT (nlillll22 XOR nlillll21))); + wire_nl1i_dataout <= ni1i1O WHEN rwa_6g_en = '1' ELSE nlO1OOl; + wire_nl1i0l_dataout <= wire_nl01li_dataout AND NOT(nlil00l); + wire_nl1i0O_dataout <= wire_nl01ll_dataout AND NOT(nlil00l); + wire_nl1ii_dataout <= nllliO AND rwa_6g_en; + wire_nl1iii_dataout <= wire_nl01lO_dataout AND NOT(nlil00l); + wire_nl1iil_dataout <= wire_nl01Oi_dataout AND NOT(nlil00l); + wire_nl1iiO_dataout <= wire_nl01Ol_dataout AND NOT(nlil00l); + wire_nl1il_dataout <= nlllli AND rwa_6g_en; + wire_nl1ili_dataout <= wire_nl01OO_dataout AND NOT(nlil00l); + wire_nl1ill_dataout <= wire_nl001i_dataout AND NOT(nlil00l); + wire_nl1ilO_dataout <= wire_nl001l_dataout AND NOT(nlil00l); + wire_nl1iO_dataout <= nlllll AND rwa_6g_en; + wire_nl1iOi_dataout <= wire_nl001O_dataout AND NOT(nlil00l); + wire_nl1iOl_dataout <= wire_nl000i_dataout AND NOT(nlil00l); + wire_nl1iOO_dataout <= wire_nl000l_dataout AND NOT(nlil00l); + wire_nl1l_dataout <= ni1i0i WHEN rwa_6g_en = '1' ELSE nlO1OOO; + wire_nl1l0i_dataout <= wire_nl00iO_dataout AND NOT(nlil00l); + wire_nl1l0l_dataout <= wire_nl00li_dataout AND NOT(nlil00l); + wire_nl1l0O_dataout <= wire_nl00ll_dataout AND NOT(nlil00l); + wire_nl1l1i_dataout <= wire_nl000O_dataout OR nlil00l; + wire_nl1l1l_dataout <= wire_nl00ii_dataout AND NOT(nlil00l); + wire_nl1l1O_dataout <= wire_nl00il_dataout AND NOT(nlil00l); + wire_nl1li_dataout <= nllllO AND rwa_6g_en; + wire_nl1lii_dataout <= wire_nl00lO_dataout AND NOT(nlil00l); + wire_nl1lil_dataout <= wire_nl00Oi_dataout AND NOT(nlil00l); + wire_nl1liO_dataout <= wire_nl00Ol_dataout AND NOT(nlil00l); + wire_nl1ll_dataout <= nlllOi AND rwa_6g_en; + wire_nl1lli_dataout <= wire_nl00OO_dataout AND NOT(nlil00l); + wire_nl1lll_dataout <= wire_nl0i1i_dataout AND NOT(nlil00l); + wire_nl1llO_dataout <= wire_nl0i1l_dataout AND NOT(nlil00l); + wire_nl1lO_dataout <= nlllOl AND rwa_6g_en; + wire_nl1lOi_dataout <= wire_nl0i1O_dataout AND NOT(nlil00l); + wire_nl1lOl_dataout <= wire_nl0i0i_dataout AND NOT(nlil00l); + wire_nl1lOO_dataout <= wire_nl0i0l_dataout AND NOT(nlil00l); + wire_nl1O_dataout <= ni1i0l WHEN rwa_6g_en = '1' ELSE nlO011i; + wire_nl1O0i_dataout <= wire_nl0iiO_dataout AND NOT(nlil00l); + wire_nl1O0l_dataout <= wire_nl0ili_dataout OR nlil00l; + wire_nl1O0O_dataout <= wire_nl0ill_dataout AND NOT(nlil00l); + wire_nl1O1i_dataout <= wire_nl0i0O_dataout AND NOT(nlil00l); + wire_nl1O1l_dataout <= wire_nl0iii_dataout AND NOT(nlil00l); + wire_nl1O1O_dataout <= wire_nl0iil_dataout AND NOT(nlil00l); + wire_nl1Oi_dataout <= nlllOO AND rwa_6g_en; + wire_nl1Oii_dataout <= wire_nl0ilO_dataout AND NOT(nlil00l); + wire_nl1Oil_dataout <= wire_nl0iOi_dataout AND NOT(nlil00l); + wire_nl1OiO_dataout <= wire_nl0iOl_dataout AND NOT(nlil00l); + wire_nl1Ol_dataout <= nllO1i AND rwa_6g_en; + wire_nl1Oli_dataout <= wire_nl0iOO_dataout AND NOT(nlil00l); + wire_nl1Oll_dataout <= wire_nl0l1i_dataout AND NOT(nlil00l); + wire_nl1OlO_dataout <= wire_nl0l1l_dataout AND NOT(nlil00l); + wire_nl1OO_dataout <= nllO1l AND rwa_6g_en; + wire_nl1OOi_dataout <= wire_nl0l1O_dataout AND NOT(nlil00l); + wire_nl1OOl_dataout <= wire_nl0l0i_dataout AND NOT(nlil00l); + wire_nl1OOO_dataout <= wire_nl0l0l_dataout AND NOT(nlil00l); + wire_nli_dataout <= wire_nliiOO_dataout WHEN rwa_6g_en = '1' ELSE wire_n1100O_dataout; + wire_nli00i_dataout <= nli1OO AND NOT(nlil00l); + wire_nli00l_dataout <= n0l00i AND NOT(nlil00l); + wire_nli00O_dataout <= n0l01O AND NOT(nlil00l); + wire_nli01O_dataout <= nli01l AND NOT(nlil00l); + wire_nli0i_dataout <= n0li0l WHEN rwa_6g_en = '1' ELSE nllO11i; + wire_nli0ii_dataout <= n0l01l AND NOT(nlil00l); + wire_nli0iO_dataout <= n0OiOO AND NOT(nlil00l); + wire_nli0l_dataout <= n0li0O WHEN rwa_6g_en = '1' ELSE nllO11l; + wire_nli0li_dataout <= n0Ol1l AND NOT(nlil00l); + wire_nli0ll_dataout <= n0Ol1O AND NOT(nlil00l); + wire_nli0lO_dataout <= n0Ol0i AND NOT(nlil00l); + wire_nli0O_dataout <= n0liii WHEN rwa_6g_en = '1' ELSE nllO11O; + wire_nli0Oi_dataout <= n0Ol0l AND NOT(nlil00l); + wire_nli1i_dataout <= n0li1l WHEN rwa_6g_en = '1' ELSE nlllOOi; + wire_nli1l_dataout <= n0li1O WHEN rwa_6g_en = '1' ELSE nlllOOl; + wire_nli1O_dataout <= n0li0i WHEN rwa_6g_en = '1' ELSE nlllOOO; + wire_nliii_dataout <= n0liil WHEN rwa_6g_en = '1' ELSE nllO10i; + wire_nliiii_dataout <= ((wire_w_lg_rgenericfifo32w(0) AND nlii0O) OR nlil01O) AND NOT(nlil00l); + wire_nliiil_dataout <= nlii0l AND NOT(nlil00l); + wire_nliiiO_dataout <= nllOOi AND NOT(nlil00l); + wire_nliil_dataout <= n0liiO WHEN rwa_6g_en = '1' ELSE nllO10l; + wire_nliiO_dataout <= n0lili WHEN rwa_6g_en = '1' ELSE nllO10O; + wire_nliiOO_dataout <= (nlil00i OR nliiOi) WHEN nlilOiO = '1' ELSE nlil00i; + wire_nlil_dataout <= nlli AND NOT(scan_mode); + wire_nlili_dataout <= n0lill WHEN rwa_6g_en = '1' ELSE nllO1ii; + wire_nlilii_dataout <= n0111i AND NOT(nlil00l); + wire_nlilil_dataout <= ((nlii0O AND n0111i) AND wire_n1i_w_lg_nlil0i484w(0)) AND NOT(nlil00l); + wire_nlill_dataout <= n0lilO WHEN rwa_6g_en = '1' ELSE nllO1il; + wire_nlilO_dataout <= n0liOi WHEN rwa_6g_en = '1' ELSE nllO1iO; + wire_nlilOO_dataout <= (nlil0il OR nlil0ii) AND wire_nliOlO_dataout; + wire_nliO00l_dataout <= nliO01O AND NOT(wire_w_lg_nli0OlO3187w(0)); + wire_nliO00O_dataout <= nliO00i AND NOT(wire_w_lg_nli0OlO3187w(0)); + wire_nliO0i_dataout <= nlil0iO AND wire_nliOlO_dataout; + wire_nliO0ii_dataout <= wire_n11iii_o AND (rgenericfifo OR wire_nlOi10l_dataout); + wire_nliO0l_dataout <= ((nlil0Oi OR nlil0lO) OR (NOT (nlil0li48 XOR nlil0li47))) WHEN (wire_n1i_w_lg_w_lg_nlilOl458w459w(0) AND wire_w_lg_nliliii460w(0)) = '1' ELSE wire_nliO0O_dataout; + wire_nliO0O_dataout <= (rtruebac2bac AND (wire_w_lg_w_lg_nliliil440w441w(0) AND (nlili0l44 XOR nlili0l43))) OR ((nlili0i OR nlili1O) AND ((nlili1l OR nlili1i) OR (NOT (nlil0Ol46 XOR nlil0Ol45)))); + wire_nliO1O_dataout <= wire_nliO0l_dataout AND wire_nliOlO_dataout; + wire_nliOi_dataout <= niOOil WHEN rwa_6g_en = '1' ELSE n100il; + wire_nliOl_dataout <= niOOiO WHEN rwa_6g_en = '1' ELSE n100iO; + wire_nliOlO_dataout <= nli0OO AND NOT(nliliiO); + wire_nliOlO_w_lg_dataout544w(0) <= NOT wire_nliOlO_dataout; + wire_nliOO_dataout <= niOOli WHEN rwa_6g_en = '1' ELSE n100li; + wire_nliOOi_dataout <= sync_status AND NOT(nliliiO); + wire_nliOOi_w_lg_dataout733w(0) <= wire_nliOOi_dataout AND ni000l; + wire_nliOOi_w_lg_dataout924w(0) <= NOT wire_nliOOi_dataout; + wire_nliOOO_dataout <= nlii1l WHEN nlilili = '1' ELSE sync_status; + wire_nll_dataout <= ni11Ol WHEN rwa_6g_en = '1' ELSE nllil1l; + wire_nll00i_dataout <= nii01i WHEN nlilili = '1' ELSE sudi(16); + wire_nll00l_dataout <= nii01l WHEN nlilili = '1' ELSE sudi(17); + wire_nll00O_dataout <= nii01O WHEN nlilili = '1' ELSE sudi(18); + wire_nll01i_dataout <= nii1Oi AND nlilili; + wire_nll01l_dataout <= nii1Ol WHEN nlilili = '1' ELSE sudi(14); + wire_nll01O_dataout <= nii1OO WHEN nlilili = '1' ELSE sudi(15); + wire_nll0i_dataout <= niOOOl WHEN rwa_6g_en = '1' ELSE n100Ol; + wire_nll0ii_dataout <= nii00i WHEN nlilili = '1' ELSE sudi(19); + wire_nll0il_dataout <= nii00l WHEN nlilili = '1' ELSE sudi(20); + wire_nll0iO_dataout <= nii00O WHEN nlilili = '1' ELSE sudi(21); + wire_nll0l_dataout <= niOOOO WHEN rwa_6g_en = '1' ELSE n100OO; + wire_nll0li_dataout <= nii0ii WHEN nlilili = '1' ELSE sudi(22); + wire_nll0ll_dataout <= nii0il WHEN nlilili = '1' ELSE sudi(23); + wire_nll0lO_dataout <= nii0iO WHEN nlilili = '1' ELSE sudi(24); + wire_nll0O_dataout <= nl111i WHEN rwa_6g_en = '1' ELSE n10i1i; + wire_nll0Oi_dataout <= nii0li WHEN nlilili = '1' ELSE sudi(25); + wire_nll0Ol_dataout <= nii0ll WHEN nlilili = '1' ELSE sudi(26); + wire_nll0OO_dataout <= nii0Oi WHEN nlilili = '1' ELSE sudi(27); + wire_nll10i_dataout <= nii11i WHEN nlilili = '1' ELSE sudi(3); + wire_nll10l_dataout <= nii11l WHEN nlilili = '1' ELSE sudi(4); + wire_nll10O_dataout <= nii11O WHEN nlilili = '1' ELSE sudi(5); + wire_nll11i_dataout <= ni0OOi WHEN nlilili = '1' ELSE sudi(0); + wire_nll11l_dataout <= ni0OOl WHEN nlilili = '1' ELSE sudi(1); + wire_nll11O_dataout <= ni0OOO WHEN nlilili = '1' ELSE sudi(2); + wire_nll1i_dataout <= niOOll WHEN rwa_6g_en = '1' ELSE n100ll; + wire_nll1ii_dataout <= nii10i WHEN nlilili = '1' ELSE sudi(6); + wire_nll1il_dataout <= nii10l WHEN nlilili = '1' ELSE sudi(7); + wire_nll1iO_dataout <= nii10O WHEN nlilili = '1' ELSE sudi(8); + wire_nll1l_dataout <= niOOlO WHEN rwa_6g_en = '1' ELSE n100lO; + wire_nll1li_dataout <= nii1ii WHEN nlilili = '1' ELSE sudi(9); + wire_nll1ll_dataout <= nii1il WHEN nlilili = '1' ELSE sudi(10); + wire_nll1lO_dataout <= nii1iO WHEN nlilili = '1' ELSE sudi(11); + wire_nll1O_dataout <= niOOOi WHEN rwa_6g_en = '1' ELSE n100Oi; + wire_nll1Oi_dataout <= nii1li WHEN nlilili = '1' ELSE sudi(12); + wire_nll1Ol_dataout <= nii1ll WHEN nlilili = '1' ELSE sudi(13); + wire_nll1OO_dataout <= nii1lO AND nlilili; + wire_nlli01i_dataout <= nli0i1i AND NOT(nli0lii); + wire_nlli0li_dataout <= (nli0i1l OR nlli1ll) WHEN nliO11i = '1' ELSE nli0i1l; + wire_nlli1i_dataout <= nii0Ol AND nlilili; + wire_nlli1l_dataout <= nii0OO AND nlilili; + wire_nlli1lO_dataout <= nli00lO AND NOT(nli0lii); + wire_nlli1Oi_dataout <= nli00Oi AND NOT(nli0lii); + wire_nlli1Ol_dataout <= nli00Ol AND NOT(nli0lii); + wire_nlli1OO_dataout <= nli00OO AND NOT(nli0lii); + wire_nllii_dataout <= nl111l WHEN rwa_6g_en = '1' ELSE n10i1l; + wire_nllii0i_dataout <= nli0l0l AND NOT(nli0lii); + wire_nlliili_dataout <= nlO1OiO AND NOT(nli0lii); + wire_nlliill_dataout <= nlO1OOi AND NOT(nli0lii); + wire_nlliilO_dataout <= nlO1OOl AND NOT(nli0lii); + wire_nlliiOi_dataout <= nlO1OOO AND NOT(nli0lii); + wire_nlliiOl_dataout <= nlO011i AND NOT(nli0lii); + wire_nllil_dataout <= nl111O WHEN rwa_6g_en = '1' ELSE n10i1O; + wire_nllil0O_dataout <= nllil1O AND NOT(nli0lii); + wire_nllilii_dataout <= nllil1i OR nli0lii; + wire_nllilil_dataout <= wire_n1OlOi_o OR nli0lii; + wire_nlliliO_dataout <= wire_nllillO_dataout OR nli0lii; + wire_nllilli_dataout <= wire_n1OllO_o AND NOT(nli0lii); + wire_nllilll_dataout <= wire_nllilOO_dataout AND NOT(nli0lii); + wire_nllillO_dataout <= (nli0i0i OR nlliiOO) WHEN nliO11i = '1' ELSE nli0i0i; + wire_nllilOO_dataout <= (nli0i0l OR nlliiiO) WHEN nliO11i = '1' ELSE nli0i0l; + wire_nlliO_dataout <= nl110i WHEN rwa_6g_en = '1' ELSE n10i0i; + wire_nlll00i_dataout <= wire_nllll1i_o(2) WHEN nli0ili = '1' ELSE wire_nlll0iO_dataout; + wire_nlll00l_dataout <= wire_nllll1i_o(3) WHEN nli0ili = '1' ELSE wire_nlll0li_dataout; + wire_nlll00O_dataout <= wire_nllll1i_o(4) WHEN nli0ili = '1' ELSE wire_nlll0ll_dataout; + wire_nlll01i_dataout <= wire_nlll00O_dataout AND NOT(nli0lii); + wire_nlll01l_dataout <= wire_nllll1i_o(0) WHEN nli0ili = '1' ELSE wire_nlll0ii_dataout; + wire_nlll01O_dataout <= wire_nllll1i_o(1) WHEN nli0ili = '1' ELSE wire_nlll0il_dataout; + wire_nlll0ii_dataout <= nlll10l WHEN nli0iiO = '1' ELSE wire_nlll0lO_dataout; + wire_nlll0il_dataout <= wire_nllliOl_o(0) WHEN nli0iiO = '1' ELSE wire_nlll0Oi_dataout; + wire_nlll0iO_dataout <= wire_nllliOl_o(1) WHEN nli0iiO = '1' ELSE wire_nlll0Ol_dataout; + wire_nlll0li_dataout <= wire_nllliOl_o(2) WHEN nli0iiO = '1' ELSE wire_nlll0OO_dataout; + wire_nlll0ll_dataout <= wire_nllliOl_o(3) WHEN nli0iiO = '1' ELSE wire_nllli1i_dataout; + wire_nlll0lO_dataout <= wire_nllliil_o(0) WHEN nli0iil = '1' ELSE wire_nllli1l_dataout; + wire_nlll0Oi_dataout <= wire_nllliil_o(1) WHEN nli0iil = '1' ELSE wire_nllli1O_dataout; + wire_nlll0Ol_dataout <= wire_nllliil_o(2) WHEN nli0iil = '1' ELSE wire_nllli0i_dataout; + wire_nlll0OO_dataout <= wire_nllliil_o(3) WHEN nli0iil = '1' ELSE wire_nllli0l_dataout; + wire_nlll1ll_dataout <= nlillOl AND NOT(nli0lii); + wire_nlll1lO_dataout <= wire_nlll01l_dataout AND NOT(nli0lii); + wire_nlll1Oi_dataout <= wire_nlll01O_dataout AND NOT(nli0lii); + wire_nlll1Ol_dataout <= wire_nlll00i_dataout AND NOT(nli0lii); + wire_nlll1OO_dataout <= wire_nlll00l_dataout AND NOT(nli0lii); + wire_nllli_dataout <= nl110l WHEN rwa_6g_en = '1' ELSE n10i0l; + wire_nllli0i_dataout <= wire_nllliii_o(3) WHEN wire_w_lg_nli0iii2511w(0) = '1' ELSE nlll1ii; + wire_nllli0l_dataout <= wire_nllliii_o(4) WHEN wire_w_lg_nli0iii2511w(0) = '1' ELSE nlll1il; + wire_nllli0O_dataout <= wire_nllliii_o(5) WHEN wire_w_lg_nli0iii2511w(0) = '1' ELSE nlll1iO; + wire_nllli1i_dataout <= wire_nllliil_o(4) WHEN nli0iil = '1' ELSE wire_nllli0O_dataout; + wire_nllli1l_dataout <= wire_nllliii_o(1) WHEN wire_w_lg_nli0iii2511w(0) = '1' ELSE nlll10l; + wire_nllli1O_dataout <= wire_nllliii_o(2) WHEN wire_w_lg_nli0iii2511w(0) = '1' ELSE nlll10O; + wire_nllll_dataout <= nl110O WHEN rwa_6g_en = '1' ELSE n10i0O; + wire_nllllll_dataout <= nli0ilO AND NOT(nli0lii); + wire_nlllllO_dataout <= nli0ilO AND NOT(nli0lii); + wire_nlllO_dataout <= nl11ii WHEN rwa_6g_en = '1' ELSE n10iii; + wire_nllO_dataout <= cmpfifourst AND rcmpfifourst; + wire_nllO00i_dataout <= wire_nllOiOl_dataout AND NOT(nli0lii); + wire_nllO00l_dataout <= wire_nllOiOO_dataout AND NOT(nli0lii); + wire_nllO00O_dataout <= wire_nllOl1i_dataout AND NOT(nli0lii); + wire_nllO01i_dataout <= wire_nllOill_dataout OR nli0lii; + wire_nllO01l_dataout <= wire_nllOilO_dataout AND NOT(nli0lii); + wire_nllO01O_dataout <= wire_nllOiOi_dataout AND NOT(nli0lii); + wire_nllO0ii_dataout <= wire_nllOl1l_dataout AND NOT(nli0lii); + wire_nllO0il_dataout <= wire_nllOl1O_dataout AND NOT(nli0lii); + wire_nllO0iO_dataout <= wire_nllOl0i_dataout AND NOT(nli0lii); + wire_nllO0li_dataout <= wire_nllOl0l_dataout AND NOT(nli0lii); + wire_nllO0ll_dataout <= wire_nllOl0O_dataout AND NOT(nli0lii); + wire_nllO0lO_dataout <= wire_nllOlii_dataout AND NOT(nli0lii); + wire_nllO0Oi_dataout <= wire_nllOlil_dataout AND NOT(nli0lii); + wire_nllO0Ol_dataout <= wire_nllOliO_dataout AND NOT(nli0lii); + wire_nllO0OO_dataout <= wire_nllOlli_dataout AND NOT(nli0lii); + wire_nllO1ll_dataout <= wire_nllOi0O_dataout AND NOT(nli0lii); + wire_nllO1lO_dataout <= wire_nllOiii_dataout AND NOT(nli0lii); + wire_nllO1Oi_dataout <= wire_nllOiil_dataout AND NOT(nli0lii); + wire_nllO1Ol_dataout <= wire_nllOiiO_dataout AND NOT(nli0lii); + wire_nllO1OO_dataout <= wire_nllOili_dataout AND NOT(nli0lii); + wire_nllOi_dataout <= nl11il WHEN rwa_6g_en = '1' ELSE n10iil; + wire_nllOi0i_dataout <= wire_nllOlOl_dataout AND NOT(nli0lii); + wire_nllOi0l_dataout <= wire_nllOlOO_dataout AND NOT(nli0lii); + wire_nllOi0O_dataout <= wire_nlO100i_dataout WHEN nli0iOi = '1' ELSE wire_nllOO1i_dataout; + wire_nllOi1i_dataout <= wire_nllOlll_dataout AND NOT(nli0lii); + wire_nllOi1l_dataout <= wire_nllOllO_dataout AND NOT(nli0lii); + wire_nllOi1O_dataout <= wire_nllOlOi_dataout AND NOT(nli0lii); + wire_nllOiii_dataout <= wire_nlO100l_dataout WHEN nli0iOi = '1' ELSE wire_nllOO1l_dataout; + wire_nllOiil_dataout <= wire_nlO100O_dataout WHEN nli0iOi = '1' ELSE wire_nllOO1O_dataout; + wire_nllOiiO_dataout <= wire_nlO10ii_dataout WHEN nli0iOi = '1' ELSE wire_nllOO0i_dataout; + wire_nllOili_dataout <= wire_nlO10il_dataout WHEN nli0iOi = '1' ELSE wire_nllOO0l_dataout; + wire_nllOill_dataout <= nllO1iO WHEN nli0iOi = '1' ELSE wire_nllOO0O_dataout; + wire_nllOilO_dataout <= nlllO0l WHEN nli0iOi = '1' ELSE wire_nllOOii_dataout; + wire_nllOiOi_dataout <= nlllO0O WHEN nli0iOi = '1' ELSE wire_nllOOil_dataout; + wire_nllOiOl_dataout <= nlllOii WHEN nli0iOi = '1' ELSE wire_nllOOiO_dataout; + wire_nllOiOO_dataout <= nlllOil WHEN nli0iOi = '1' ELSE wire_nllOOli_dataout; + wire_nllOl_dataout <= nl11iO WHEN rwa_6g_en = '1' ELSE n10iiO; + wire_nllOl0i_dataout <= nlllOlO WHEN nli0iOi = '1' ELSE wire_nllOOOl_dataout; + wire_nllOl0l_dataout <= nlllOOi WHEN nli0iOi = '1' ELSE wire_nllOOOO_dataout; + wire_nllOl0O_dataout <= nlllOOl WHEN nli0iOi = '1' ELSE wire_nlO111i_dataout; + wire_nllOl1i_dataout <= nlllOiO WHEN nli0iOi = '1' ELSE wire_nllOOll_dataout; + wire_nllOl1l_dataout <= nlllOli WHEN nli0iOi = '1' ELSE wire_nllOOlO_dataout; + wire_nllOl1O_dataout <= nlllOll WHEN nli0iOi = '1' ELSE wire_nllOOOi_dataout; + wire_nllOlii_dataout <= nlllOOO WHEN nli0iOi = '1' ELSE wire_nlO111l_dataout; + wire_nllOlil_dataout <= nllO11i WHEN nli0iOi = '1' ELSE wire_nlO111O_dataout; + wire_nllOliO_dataout <= nllO11l WHEN nli0iOi = '1' ELSE wire_nlO110i_dataout; + wire_nllOlli_dataout <= nllO11O WHEN nli0iOi = '1' ELSE wire_nlO110l_dataout; + wire_nllOlll_dataout <= nllO10i WHEN nli0iOi = '1' ELSE wire_nlO110O_dataout; + wire_nllOllO_dataout <= nllO10l WHEN nli0iOi = '1' ELSE wire_nlO11ii_dataout; + wire_nllOlOi_dataout <= nllO10O WHEN nli0iOi = '1' ELSE wire_nlO11il_dataout; + wire_nllOlOl_dataout <= nllO1ii WHEN nli0iOi = '1' ELSE wire_nlO11iO_dataout; + wire_nllOlOO_dataout <= nllO1il WHEN nli0iOi = '1' ELSE wire_nlO11li_dataout; + wire_nllOO_dataout <= nl11li WHEN rwa_6g_en = '1' ELSE n10ili; + wire_nllOO0i_dataout <= wire_nlO11Ol_dataout WHEN nli0iOO = '1' ELSE nlllO1O; + wire_nllOO0l_dataout <= wire_nlO11OO_dataout WHEN nli0iOO = '1' ELSE nlllO0i; + wire_nllOO0O_dataout <= nlllO0O WHEN nli0iOO = '1' ELSE nlllO0l; + wire_nllOO1i_dataout <= wire_nlO11ll_dataout WHEN nli0iOO = '1' ELSE nllllli; + wire_nllOO1l_dataout <= wire_nlO11lO_dataout WHEN nli0iOO = '1' ELSE nlllO1i; + wire_nllOO1O_dataout <= wire_nlO11Oi_dataout WHEN nli0iOO = '1' ELSE nlllO1l; + wire_nllOOii_dataout <= nlllOii WHEN nli0iOO = '1' ELSE nlllO0O; + wire_nllOOil_dataout <= nlllOil WHEN nli0iOO = '1' ELSE nlllOii; + wire_nllOOiO_dataout <= nlllOiO WHEN nli0iOO = '1' ELSE nlllOil; + wire_nllOOli_dataout <= nlllOli WHEN nli0iOO = '1' ELSE nlllOiO; + wire_nllOOll_dataout <= nlllOll WHEN nli0iOO = '1' ELSE nlllOli; + wire_nllOOlO_dataout <= nlllOlO WHEN nli0iOO = '1' ELSE nlllOll; + wire_nllOOOi_dataout <= nlllOOi WHEN nli0iOO = '1' ELSE nlllOlO; + wire_nllOOOl_dataout <= nlllOOl WHEN nli0iOO = '1' ELSE nlllOOi; + wire_nllOOOO_dataout <= nlllOOO WHEN nli0iOO = '1' ELSE nlllOOl; + wire_nlO_dataout <= wire_n0OOii_dataout WHEN rwa_6g_en = '1' ELSE wire_nlli0li_dataout; + wire_nlO001i_dataout <= wire_nlO000l_o(4) WHEN wire_nlO000O_o = '1' ELSE wire_nlO001O_o(4); + wire_nlO001l_dataout <= wire_nlO000l_o(5) WHEN wire_nlO000O_o = '1' ELSE wire_nlO001O_o(5); + wire_nlO00il_dataout <= (nli0lOl OR nli0lOi) AND (wire_nlOi10l_dataout AND nliii0i); + wire_nlO010i_dataout <= wire_nlO01iO_dataout AND NOT(nli0lii); + wire_nlO010l_dataout <= wire_nlO01li_dataout AND NOT(nli0lii); + wire_nlO010O_dataout <= wire_nlO01ll_dataout AND NOT(nli0lii); + wire_nlO011O_dataout <= wire_nlO01il_dataout AND NOT(nli0lii); + wire_nlO01ii_dataout <= wire_nlO01lO_dataout AND NOT(nli0lii); + wire_nlO01il_dataout <= wire_nlO01Oi_dataout AND NOT(nli0lil); + wire_nlO01iO_dataout <= wire_nlO01Ol_dataout AND NOT(nli0lil); + wire_nlO01li_dataout <= nlO1Oii WHEN nli0lil = '1' ELSE wire_nlO01OO_dataout; + wire_nlO01ll_dataout <= wire_nlO001i_dataout AND NOT(nli0lil); + wire_nlO01lO_dataout <= nlO1Oii WHEN nli0lil = '1' ELSE wire_nlO001l_dataout; + wire_nlO01Oi_dataout <= wire_nlO000l_o(1) WHEN wire_nlO000O_o = '1' ELSE wire_nlO001O_o(1); + wire_nlO01Ol_dataout <= wire_nlO000l_o(2) WHEN wire_nlO000O_o = '1' ELSE wire_nlO001O_o(2); + wire_nlO01OO_dataout <= wire_nlO000l_o(3) WHEN wire_nlO000O_o = '1' ELSE wire_nlO001O_o(3); + wire_nlO0i_dataout <= nl11OO WHEN rwa_6g_en = '1' ELSE n10iOl; + wire_nlO0i0l_dataout <= nli0lOO AND (wire_nlOi10l_dataout AND nlO00Oi); + wire_nlO0i1i_dataout <= nli0lOO AND (wire_nlOi10l_dataout AND nlO00ll); + wire_nlO0i1O_dataout <= nli0lOO AND (wire_nlOi10l_dataout AND nlO00lO); + wire_nlO0iiO_dataout <= nlii0OO AND (wire_nlOi10l_dataout AND ((wire_w_lg_rclkcmpsqmd1943w(0) AND nlillil) OR nlO00ii)); + wire_nlO0l_dataout <= nl101i WHEN rwa_6g_en = '1' ELSE n10iOO; + wire_nlO0l1O_dataout <= nlii0OO AND (wire_nlOi10l_dataout AND (nli0O1i OR wire_w_lg_nliii0i2236w(0))); + wire_nlO0lOi_dataout <= audi_pre(0) WHEN dskwclksel(1) = '1' ELSE sudi_pre(0); + wire_nlO0lOl_dataout <= audi_pre(1) WHEN dskwclksel(1) = '1' ELSE sudi_pre(1); + wire_nlO0lOO_dataout <= audi_pre(2) WHEN dskwclksel(1) = '1' ELSE sudi_pre(2); + wire_nlO0O_dataout <= nl101l WHEN rwa_6g_en = '1' ELSE n10l1i; + wire_nlO0O0i_dataout <= audi_pre(6) WHEN dskwclksel(1) = '1' ELSE sudi_pre(6); + wire_nlO0O0l_dataout <= audi_pre(7) WHEN dskwclksel(1) = '1' ELSE sudi_pre(7); + wire_nlO0O0O_dataout <= audi_pre(8) WHEN dskwclksel(1) = '1' ELSE sudi_pre(8); + wire_nlO0O1i_dataout <= audi_pre(3) WHEN dskwclksel(1) = '1' ELSE sudi_pre(3); + wire_nlO0O1l_dataout <= audi_pre(4) WHEN dskwclksel(1) = '1' ELSE sudi_pre(4); + wire_nlO0O1O_dataout <= audi_pre(5) WHEN dskwclksel(1) = '1' ELSE sudi_pre(5); + wire_nlO0Oii_dataout <= audi_pre(9) WHEN dskwclksel(1) = '1' ELSE sudi_pre(9); + wire_nlO0Oil_dataout <= audi_pre(10) WHEN dskwclksel(1) = '1' ELSE sudi_pre(10); + wire_nlO0Oil_w_lg_w_lg_dataout2543w2545w(0) <= wire_nlO0Oil_w_lg_dataout2543w(0) AND wire_w_lg_rrx_pipe_enable2544w(0); + wire_nlO0Oil_w_lg_dataout2543w(0) <= NOT wire_nlO0Oil_dataout; + wire_nlO0OiO_dataout <= audi_pre(12) WHEN dskwclksel(1) = '1' ELSE sudi_pre(12); + wire_nlO0OiO_w_lg_w_lg_w_lg_dataout2542w2546w2547w(0) <= wire_nlO0OiO_w_lg_w_lg_dataout2542w2546w(0) AND nlO01O; + wire_nlO0OiO_w_lg_w_lg_dataout2542w2546w(0) <= wire_nlO0OiO_w_lg_dataout2542w(0) AND wire_nlO0Oil_w_lg_w_lg_dataout2543w2545w(0); + wire_nlO0OiO_w_lg_dataout2542w(0) <= NOT wire_nlO0OiO_dataout; + wire_nlO0Oli_dataout <= audi(10) WHEN dskwclksel(1) = '1' ELSE sudi(10); + wire_nlO0Oli_w_lg_w_lg_dataout2228w2229w(0) <= wire_nlO0Oli_w_lg_dataout2228w(0) AND nlO00Ol; + wire_nlO0Oli_w_lg_w_lg_dataout2228w2234w(0) <= wire_nlO0Oli_w_lg_dataout2228w(0) AND nlO011l; + wire_nlO0Oli_w_lg_dataout2228w(0) <= NOT wire_nlO0Oli_dataout; + wire_nlO0Oll_dataout <= audi(11) WHEN dskwclksel(1) = '1' ELSE (sudi(11) AND inferred_rxvalid); + wire_nlO0OlO_dataout <= audi(12) WHEN dskwclksel(1) = '1' ELSE sudi(12); + wire_nlO0OlO_w_lg_dataout2227w(0) <= NOT wire_nlO0OlO_dataout; + wire_nlO100i_dataout <= wire_nlO10iO_o(0) AND NOT(nli0l1l); + wire_nlO100l_dataout <= wire_nlO10iO_o(1) AND NOT(nli0l1l); + wire_nlO100O_dataout <= wire_nlO10iO_o(2) AND NOT(nli0l1l); + wire_nlO10i_dataout <= wire_n1ll_dataout AND NOT(wire_nl00O_w_lg_dataout123w(0)); + wire_nlO10ii_dataout <= wire_nlO10iO_o(3) AND NOT(nli0l1l); + wire_nlO10il_dataout <= wire_nlO10iO_o(4) AND NOT(nli0l1l); + wire_nlO10l_dataout <= wire_nlO1ii_dataout AND NOT(wire_nl00O_w_lg_dataout123w(0)); + wire_nlO10O_dataout <= wire_nlO1il_dataout AND NOT(wire_nl00O_w_lg_dataout123w(0)); + wire_nlO110i_dataout <= nllO10i WHEN nli0iOO = '1' ELSE nllO11O; + wire_nlO110l_dataout <= nllO10l WHEN nli0iOO = '1' ELSE nllO10i; + wire_nlO110O_dataout <= nllO10O WHEN nli0iOO = '1' ELSE nllO10l; + wire_nlO111i_dataout <= nllO11i WHEN nli0iOO = '1' ELSE nlllOOO; + wire_nlO111l_dataout <= nllO11l WHEN nli0iOO = '1' ELSE nllO11i; + wire_nlO111O_dataout <= nllO11O WHEN nli0iOO = '1' ELSE nllO11l; + wire_nlO11ii_dataout <= nllO1ii WHEN nli0iOO = '1' ELSE nllO10O; + wire_nlO11il_dataout <= nllO1il WHEN nli0iOO = '1' ELSE nllO1ii; + wire_nlO11iO_dataout <= nllO1iO WHEN nli0iOO = '1' ELSE nllO1il; + wire_nlO11li_dataout <= nlllO0l WHEN nli0iOO = '1' ELSE nllO1iO; + wire_nlO11ll_dataout <= wire_nlO101i_o(1) OR nli0iOl; + wire_nlO11lO_dataout <= wire_nlO101i_o(2) OR nli0iOl; + wire_nlO11Oi_dataout <= wire_nlO101i_o(3) AND NOT(nli0iOl); + wire_nlO11Ol_dataout <= wire_nlO101i_o(4) AND NOT(nli0iOl); + wire_nlO11OO_dataout <= wire_nlO101i_o(5) OR nli0iOl; + wire_nlO1i_dataout <= nl11ll WHEN rwa_6g_en = '1' ELSE n10ill; + wire_nlO1i0i_dataout <= nlli10l AND NOT(nli0lii); + wire_nlO1i0l_dataout <= nlli10i AND NOT(nli0lii); + wire_nlO1i1i_dataout <= nlO10OO AND NOT(nli0lii); + wire_nlO1i1l_dataout <= nlO10Ol AND NOT(nli0lii); + wire_nlO1i1O_dataout <= nlli10O AND NOT(nli0lii); + wire_nlO1ii_dataout <= nllOOi AND NOT(wire_n1ll_dataout); + wire_nlO1iii_dataout <= n11O0O AND NOT(nli0lii); + wire_nlO1iil_dataout <= n101Ol AND NOT(nli0lii); + wire_nlO1iiO_dataout <= n101OO AND NOT(nli0lii); + wire_nlO1il_dataout <= nlO01O AND NOT(wire_n1ll_dataout); + wire_nlO1ili_dataout <= n1001i AND NOT(nli0lii); + wire_nlO1ill_dataout <= n1001l AND NOT(nli0lii); + wire_nlO1iO_dataout <= nlO01O WHEN wire_nl00O_w_lg_dataout123w(0) = '1' ELSE wire_nlO1lO_dataout; + wire_nlO1l_dataout <= nl11lO WHEN rwa_6g_en = '1' ELSE n10ilO; + wire_nlO1li_dataout <= nllOOi WHEN wire_nl00O_w_lg_dataout123w(0) = '1' ELSE wire_nlO1Oi_dataout; + wire_nlO1ll_dataout <= wire_w_lg_nlill0O122w(0) AND NOT(wire_nl00O_w_lg_dataout123w(0)); + wire_nlO1lO_dataout <= wire_n1iO_dataout WHEN nlill0O = '1' ELSE nlO01O; + wire_nlO1O_dataout <= nl11Ol WHEN rwa_6g_en = '1' ELSE n10iOi; + wire_nlO1Oi_dataout <= wire_n1li_dataout WHEN nlill0O = '1' ELSE nllOOi; + wire_nlO1Oil_dataout <= nlillOi AND wire_nlOi10l_dataout; + wire_nlO1Oli_dataout <= wire_nlO1Oll_dataout AND wire_nlOi10l_dataout; + wire_nlO1Oll_dataout <= nlO1Oii OR (wire_nii_w_lg_nlO1Oii2349w(0) AND nli0l0O); + wire_nlO1OO_dataout <= wire_n1il_dataout AND wire_nl00O_dataout; + wire_nlOi00i_dataout <= nlOliil WHEN nli0Oli = '1' ELSE wire_nlOii0l_dataout; + wire_nlOi00l_dataout <= nlOliiO WHEN nli0Oli = '1' ELSE wire_nlOii0O_dataout; + wire_nlOi00O_dataout <= nlOlili WHEN nli0Oli = '1' ELSE wire_nlOiiii_dataout; + wire_nlOi01i_dataout <= nlOli0l WHEN nli0Oli = '1' ELSE wire_nlOii1l_dataout; + wire_nlOi01l_dataout <= nlOli0O WHEN nli0Oli = '1' ELSE wire_nlOii1O_dataout; + wire_nlOi01O_dataout <= nlOliii WHEN nli0Oli = '1' ELSE wire_nlOii0i_dataout; + wire_nlOi0ii_dataout <= nlOlill WHEN nli0Oli = '1' ELSE wire_nlOiiil_dataout; + wire_nlOi0il_dataout <= nlOlilO WHEN nli0Oli = '1' ELSE wire_nlOiiiO_dataout; + wire_nlOi0iO_dataout <= nlOliOl WHEN nli0Oli = '1' ELSE wire_nlOiili_dataout; + wire_nlOi0li_dataout <= wire_nlOiill_dataout AND NOT(nli0Oli); + wire_nlOi0ll_dataout <= wire_nlOiilO_dataout OR nli0Oli; + wire_nlOi0lO_dataout <= nlOl0OO WHEN nli0O0l = '1' ELSE wire_nlOiiOi_dataout; + wire_nlOi0Oi_dataout <= nlOli1i WHEN nli0O0l = '1' ELSE wire_nlOiiOl_dataout; + wire_nlOi0Ol_dataout <= nlOli1l WHEN nli0O0l = '1' ELSE wire_nlOiiOO_dataout; + wire_nlOi0OO_dataout <= nlOli1O WHEN nli0O0l = '1' ELSE wire_nlOil1i_dataout; + wire_nlOi10i_dataout <= nlOiO0O WHEN dskwclksel(1) = '1' ELSE nlOiO0i; + wire_nlOi10l_dataout <= wire_nlOi10O_dataout AND NOT(nli0O0i); + wire_nlOi10l_w_lg_dataout2553w(0) <= NOT wire_nlOi10l_dataout; + wire_nlOi10O_dataout <= align_status WHEN dskwclksel(1) = '1' ELSE sync_status; + wire_nlOi11i_dataout <= wire_nlOi11l_dataout AND NOT(nli0O0i); + wire_nlOi11i_w_lg_dataout1992w(0) <= NOT wire_nlOi11i_dataout; + wire_nlOi11l_dataout <= align_status_sync_0 WHEN nlii1ii = '1' ELSE wire_nlOi11O_dataout; + wire_nlOi11O_dataout <= align_status_sync_2 WHEN nlii10O = '1' ELSE wire_nlOi10i_dataout; + wire_nlOi1il_dataout <= n10O1O WHEN nli0O0l = '1' ELSE wire_nlOi10O_dataout; + wire_nlOi1li_dataout <= nli0Oli AND wire_nlOi11i_dataout; + wire_nlOi1ll_dataout <= nlOl0OO WHEN nli0Oli = '1' ELSE wire_nlOi0lO_dataout; + wire_nlOi1lO_dataout <= nlOli1i WHEN nli0Oli = '1' ELSE wire_nlOi0Oi_dataout; + wire_nlOi1Oi_dataout <= nlOli1l WHEN nli0Oli = '1' ELSE wire_nlOi0Ol_dataout; + wire_nlOi1Ol_dataout <= nlOli1O WHEN nli0Oli = '1' ELSE wire_nlOi0OO_dataout; + wire_nlOi1OO_dataout <= nlOli0i WHEN nli0Oli = '1' ELSE wire_nlOii1i_dataout; + wire_nlOii_dataout <= nl101O WHEN rwa_6g_en = '1' ELSE n10l1l; + wire_nlOii0i_dataout <= nlOliii WHEN nli0O0l = '1' ELSE wire_nlOil0l_dataout; + wire_nlOii0l_dataout <= nlOliil WHEN nli0O0l = '1' ELSE wire_nlOil0O_dataout; + wire_nlOii0O_dataout <= nlOliiO WHEN nli0O0l = '1' ELSE wire_nlOilii_dataout; + wire_nlOii1i_dataout <= nlOli0i WHEN nli0O0l = '1' ELSE wire_nlOil1l_dataout; + wire_nlOii1l_dataout <= nlOli0l WHEN nli0O0l = '1' ELSE wire_nlOil1O_dataout; + wire_nlOii1O_dataout <= nlOli0O WHEN nli0O0l = '1' ELSE wire_nlOil0i_dataout; + wire_nlOiiii_dataout <= nlOlili WHEN nli0O0l = '1' ELSE wire_nlO0Oli_dataout; + wire_nlOiiil_dataout <= nlOlill WHEN nli0O0l = '1' ELSE wire_nlOilil_dataout; + wire_nlOiiiO_dataout <= nlOlilO WHEN nli0O0l = '1' ELSE wire_nlO0OlO_dataout; + wire_nlOiili_dataout <= nlOliOl WHEN nli0O0l = '1' ELSE wire_nlOiliO_dataout; + wire_nlOiill_dataout <= nlOliOO AND nli0O0l; + wire_nlOiilO_dataout <= nlOll1i AND nli0O0l; + wire_nlOiiOi_dataout <= audi(0) WHEN dskwclksel(1) = '1' ELSE sudi(0); + wire_nlOiiOl_dataout <= audi(1) WHEN dskwclksel(1) = '1' ELSE sudi(1); + wire_nlOiiOO_dataout <= audi(2) WHEN dskwclksel(1) = '1' ELSE sudi(2); + wire_nlOil_dataout <= nl100i WHEN rwa_6g_en = '1' ELSE n10l1O; + wire_nlOil0i_dataout <= audi(6) WHEN dskwclksel(1) = '1' ELSE sudi(6); + wire_nlOil0l_dataout <= audi(7) WHEN dskwclksel(1) = '1' ELSE sudi(7); + wire_nlOil0O_dataout <= audi(8) WHEN dskwclksel(1) = '1' ELSE sudi(8); + wire_nlOil1i_dataout <= audi(3) WHEN dskwclksel(1) = '1' ELSE sudi(3); + wire_nlOil1l_dataout <= audi(4) WHEN dskwclksel(1) = '1' ELSE sudi(4); + wire_nlOil1O_dataout <= audi(5) WHEN dskwclksel(1) = '1' ELSE sudi(5); + wire_nlOilii_dataout <= audi(9) WHEN dskwclksel(1) = '1' ELSE sudi(9); + wire_nlOilil_dataout <= audi(11) WHEN dskwclksel(1) = '1' ELSE sudi(11); + wire_nlOiliO_dataout <= audi(13) WHEN dskwclksel(1) = '1' ELSE sudi(13); + wire_nlOiO_dataout <= nl100l WHEN rwa_6g_en = '1' ELSE n10l0i; + wire_nlOli_dataout <= nl100O WHEN rwa_6g_en = '1' ELSE n10l0l; + wire_nlOll_dataout <= nl10ii WHEN rwa_6g_en = '1' ELSE n10l0O; + wire_nlOll0i_dataout <= wire_nlOliOi_w_lg_nlOliOl2141w(0) WHEN nlii1Oi = '1' ELSE wire_nlOO0iO_dataout; + wire_nlOll0l_dataout <= wire_nlOliOi_w_lg_nlOliOl2141w(0) WHEN nlii1Oi = '1' ELSE wire_nlOO0li_dataout; + wire_nlOll0O_dataout <= wire_n1100l_dataout WHEN nlii1Oi = '1' ELSE wire_nlOO0ll_dataout; + wire_nlOll1O_dataout <= wire_n1100i_dataout WHEN nlii1Oi = '1' ELSE wire_nlOO0il_dataout; + wire_nlOllii_dataout <= wire_nlOliOi_w_lg_nlOliOl2141w(0) WHEN nlii1Oi = '1' ELSE wire_nlOO0lO_dataout; + wire_nlOllil_dataout <= nlOliOl WHEN nlii1Oi = '1' ELSE wire_nlOO0Oi_dataout; + wire_nlOlliO_dataout <= wire_nlOliOi_w_lg_nlOliOl2141w(0) WHEN nlii1Oi = '1' ELSE wire_nlOO0Ol_dataout; + wire_nlOllli_dataout <= nlOliOl WHEN nlii1Oi = '1' ELSE wire_nlOO0OO_dataout; + wire_nlOllll_dataout <= nlOliOl WHEN nlii1Oi = '1' ELSE wire_nlOOi1i_dataout; + wire_nlOlllO_dataout <= nlOliOl WHEN nlii1Oi = '1' ELSE wire_nlOOi1l_dataout; + wire_nlOllOi_dataout <= wire_nlOOi1O_dataout AND NOT(nlii1Oi); + wire_nlOllOl_dataout <= wire_nlOOi0l_dataout AND NOT(nlii1Oi); + wire_nlOllOO_dataout <= wire_nlOOiii_dataout AND NOT(nlii1Oi); + wire_nlOlO_dataout <= nl10il WHEN rwa_6g_en = '1' ELSE n10lii; + wire_nlOlO0i_dataout <= wire_nllOll_data_out2(2) WHEN nli0Oil = '1' ELSE nlOl00l; + wire_nlOlO0l_dataout <= wire_nllOll_data_out2(3) WHEN nli0Oil = '1' ELSE nlOl00O; + wire_nlOlO0O_dataout <= wire_nllOll_data_out2(4) WHEN nli0Oil = '1' ELSE nlOl0ii; + wire_nlOlO1i_dataout <= wire_nlOOiil_dataout OR nlii1Oi; + wire_nlOlO1l_dataout <= wire_nllOll_data_out2(0) WHEN nli0Oil = '1' ELSE nlOl01O; + wire_nlOlO1O_dataout <= wire_nllOll_data_out2(1) WHEN nli0Oil = '1' ELSE nlOl00i; + wire_nlOlOii_dataout <= wire_nllOll_data_out2(5) WHEN nli0Oil = '1' ELSE nlOl0il; + wire_nlOlOil_dataout <= wire_nllOll_data_out2(6) WHEN nli0Oil = '1' ELSE nlOl0iO; + wire_nlOlOiO_dataout <= wire_nllOll_data_out2(7) WHEN nli0Oil = '1' ELSE nlOl0li; + wire_nlOlOli_dataout <= wire_nllOll_data_out2(8) WHEN nli0Oil = '1' ELSE nlOl0ll; + wire_nlOlOll_dataout <= wire_nllOll_data_out2(9) WHEN nli0Oil = '1' ELSE nlOl0lO; + wire_nlOlOlO_dataout <= wire_nllOll_data_out2(11) WHEN nli0Oil = '1' ELSE nlOl0Oi; + wire_nlOlOOi_dataout <= wire_nllOll_data_out2(13) WHEN nli0Oil = '1' ELSE nlOl0Ol; + wire_nlOlOOl_dataout <= nlOl10O WHEN nli0Oil = '1' ELSE nlOiOil; + wire_nlOlOOO_dataout <= nlOl1ii WHEN nli0Oil = '1' ELSE nlOiOli; + wire_nlOO00i_dataout <= nlOl0ll WHEN nli0Oil = '1' ELSE nlOl1Ol; + wire_nlOO00l_dataout <= nlOl0lO WHEN nli0Oil = '1' ELSE nlOl1OO; + wire_nlOO00O_dataout <= nlOl0Oi WHEN nli0Oil = '1' ELSE nlOl01i; + wire_nlOO01i_dataout <= nlOl0il WHEN nli0Oil = '1' ELSE nlOl1ll; + wire_nlOO01l_dataout <= nlOl0iO WHEN nli0Oil = '1' ELSE nlOl1lO; + wire_nlOO01O_dataout <= nlOl0li WHEN nli0Oil = '1' ELSE nlOl1Oi; + wire_nlOO0ii_dataout <= nlOl0Ol WHEN nli0Oil = '1' ELSE nlOl01l; + wire_nlOO0il_dataout <= wire_nllOll_data_out1(0) WHEN nli0Oil = '1' ELSE wire_nlOOiiO_dataout; + wire_nlOO0iO_dataout <= wire_nllOll_data_out1(1) WHEN nli0Oil = '1' ELSE wire_nlOOili_dataout; + wire_nlOO0li_dataout <= wire_nllOll_data_out1(2) WHEN nli0Oil = '1' ELSE wire_nlOOill_dataout; + wire_nlOO0ll_dataout <= wire_nllOll_data_out1(3) WHEN nli0Oil = '1' ELSE wire_nlOOilO_dataout; + wire_nlOO0lO_dataout <= wire_nllOll_data_out1(4) WHEN nli0Oil = '1' ELSE wire_nlOOiOi_dataout; + wire_nlOO0Oi_dataout <= wire_nllOll_data_out1(5) WHEN nli0Oil = '1' ELSE wire_nlOOiOl_dataout; + wire_nlOO0Ol_dataout <= wire_nllOll_data_out1(6) WHEN nli0Oil = '1' ELSE wire_nlOOiOO_dataout; + wire_nlOO0OO_dataout <= wire_nllOll_data_out1(7) WHEN nli0Oil = '1' ELSE wire_nlOOl1i_dataout; + wire_nlOO10i_dataout <= nlOl1ll WHEN nli0Oil = '1' ELSE nlOiOOl; + wire_nlOO10l_dataout <= nlOl1lO WHEN nli0Oil = '1' ELSE nlOiOOO; + wire_nlOO10O_dataout <= nlOl1Oi WHEN nli0Oil = '1' ELSE nlOl11i; + wire_nlOO11i_dataout <= nlOl1il WHEN nli0Oil = '1' ELSE nlOiOll; + wire_nlOO11l_dataout <= nlOl1iO WHEN nli0Oil = '1' ELSE nlOiOlO; + wire_nlOO11O_dataout <= nlOl1li WHEN nli0Oil = '1' ELSE nlOiOOi; + wire_nlOO1ii_dataout <= nlOl1Ol WHEN nli0Oil = '1' ELSE nlOl11l; + wire_nlOO1il_dataout <= nlOl1OO WHEN nli0Oil = '1' ELSE nlOl11O; + wire_nlOO1iO_dataout <= nlOl01i WHEN nli0Oil = '1' ELSE nlOl10i; + wire_nlOO1li_dataout <= nlOl01l WHEN nli0Oil = '1' ELSE nlOl10l; + wire_nlOO1ll_dataout <= nlOl01O WHEN nli0Oil = '1' ELSE nlOl10O; + wire_nlOO1lO_dataout <= nlOl00i WHEN nli0Oil = '1' ELSE nlOl1ii; + wire_nlOO1Oi_dataout <= nlOl00l WHEN nli0Oil = '1' ELSE nlOl1il; + wire_nlOO1Ol_dataout <= nlOl00O WHEN nli0Oil = '1' ELSE nlOl1iO; + wire_nlOO1OO_dataout <= nlOl0ii WHEN nli0Oil = '1' ELSE nlOl1li; + wire_nlOOi_dataout <= nl10iO WHEN rwa_6g_en = '1' ELSE n10lil; + wire_nlOOi0i_dataout <= wire_nllOll_data_out1(11) WHEN nli0Oil = '1' ELSE wire_nlOOl0l_dataout; + wire_nlOOi0l_dataout <= wire_nllOll_data_out1(12) WHEN nli0Oil = '1' ELSE wire_nlOOl0O_dataout; + wire_nlOOi0O_dataout <= wire_nllOll_data_out1(13) WHEN nli0Oil = '1' ELSE wire_nlOOlii_dataout; + wire_nlOOi1i_dataout <= wire_nllOll_data_out1(8) WHEN nli0Oil = '1' ELSE wire_nlOOl1l_dataout; + wire_nlOOi1l_dataout <= wire_nllOll_data_out1(9) WHEN nli0Oil = '1' ELSE wire_nlOOl1O_dataout; + wire_nlOOi1O_dataout <= wire_nllOll_data_out1(10) WHEN nli0Oil = '1' ELSE wire_nlOOl0i_dataout; + wire_nlOOiii_dataout <= wire_nllOll_data_out1(14) WHEN nli0Oil = '1' ELSE wire_nlOOlil_dataout; + wire_nlOOiil_dataout <= wire_nllOll_data_out1(15) WHEN nli0Oil = '1' ELSE wire_nlOOliO_dataout; + wire_nlOOiiO_dataout <= wire_nlOOlOO_dataout WHEN rclkcmpsqmd = '1' ELSE nlOl0OO; + wire_nlOOili_dataout <= wire_nlOOO1i_dataout WHEN rclkcmpsqmd = '1' ELSE nlOli1i; + wire_nlOOill_dataout <= wire_nlOOO1l_dataout WHEN rclkcmpsqmd = '1' ELSE nlOli1l; + wire_nlOOilO_dataout <= wire_nlOOO1O_dataout WHEN rclkcmpsqmd = '1' ELSE nlOli1O; + wire_nlOOiOi_dataout <= wire_nlOOO0i_dataout WHEN rclkcmpsqmd = '1' ELSE nlOli0i; + wire_nlOOiOl_dataout <= wire_nlOOO0l_dataout WHEN rclkcmpsqmd = '1' ELSE nlOli0l; + wire_nlOOiOO_dataout <= wire_nlOOO0O_dataout WHEN rclkcmpsqmd = '1' ELSE nlOli0O; + wire_nlOOl_dataout <= nl10li WHEN rwa_6g_en = '1' ELSE n10liO; + wire_nlOOl0i_dataout <= wire_nlOOOli_dataout WHEN rclkcmpsqmd = '1' ELSE wire_nlOOlli_dataout; + wire_nlOOl0l_dataout <= wire_nlOOOll_dataout WHEN rclkcmpsqmd = '1' ELSE nlOlill; + wire_nlOOl0O_dataout <= wire_nlOOOlO_dataout WHEN rclkcmpsqmd = '1' ELSE wire_nlOOlll_dataout; + wire_nlOOl1i_dataout <= wire_nlOOOii_dataout WHEN rclkcmpsqmd = '1' ELSE nlOliii; + wire_nlOOl1l_dataout <= wire_nlOOOil_dataout WHEN rclkcmpsqmd = '1' ELSE nlOliil; + wire_nlOOl1O_dataout <= wire_nlOOOiO_dataout WHEN rclkcmpsqmd = '1' ELSE nlOliiO; + wire_nlOOlii_dataout <= wire_nlOOOOi_dataout WHEN rclkcmpsqmd = '1' ELSE nlOliOl; + wire_nlOOlil_dataout <= wire_nlOOOOl_dataout AND rclkcmpsqmd; + wire_nlOOliO_dataout <= wire_nlOOOOO_dataout WHEN rclkcmpsqmd = '1' ELSE wire_w_lg_rrx_pipe_enable1942w(0); + wire_nlOOlli_dataout <= wire_nlOOllO_dataout AND NOT(rrx_pipe_enable); + wire_nlOOlll_dataout <= wire_nlOOlOi_dataout AND NOT(rrx_pipe_enable); + wire_nlOOllO_dataout <= nlOlili AND nli0Oii; + wire_nlOOlOi_dataout <= nlOlilO AND nli0Oii; + wire_nlOOlOO_dataout <= nlOl10O WHEN n11O1l = '1' ELSE wire_n1111i_dataout; + wire_nlOOO_dataout <= nl10ll WHEN rwa_6g_en = '1' ELSE n10lli; + wire_nlOOO0i_dataout <= nlOl1li WHEN n11O1l = '1' ELSE wire_n1110l_dataout; + wire_nlOOO0l_dataout <= nlOl1ll WHEN n11O1l = '1' ELSE wire_n1110O_dataout; + wire_nlOOO0O_dataout <= nlOl1lO WHEN n11O1l = '1' ELSE wire_n111ii_dataout; + wire_nlOOO1i_dataout <= nlOl1ii WHEN n11O1l = '1' ELSE wire_n1111l_dataout; + wire_nlOOO1l_dataout <= nlOl1il WHEN n11O1l = '1' ELSE wire_n1111O_dataout; + wire_nlOOO1O_dataout <= nlOl1iO WHEN n11O1l = '1' ELSE wire_n1110i_dataout; + wire_nlOOOii_dataout <= nlOl1Oi WHEN n11O1l = '1' ELSE wire_n111il_dataout; + wire_nlOOOil_dataout <= nlOl1Ol WHEN n11O1l = '1' ELSE wire_n111iO_dataout; + wire_nlOOOiO_dataout <= nlOl1OO WHEN n11O1l = '1' ELSE wire_n111li_dataout; + wire_nlOOOli_dataout <= wire_n111ll_dataout AND NOT(n11O1l); + wire_nlOOOll_dataout <= nlOl01i WHEN n11O1l = '1' ELSE wire_n111lO_dataout; + wire_nlOOOlO_dataout <= wire_n111Oi_dataout AND NOT(n11O1l); + wire_nlOOOOi_dataout <= nlOl01l WHEN n11O1l = '1' ELSE wire_n111Ol_dataout; + wire_nlOOOOl_dataout <= wire_n111OO_dataout AND NOT(n11O1l); + wire_nlOOOOO_dataout <= wire_n1101i_dataout OR n11O1l; + wire_n0O0li_a <= ( n0l0il & n0l0ii & n0l00O & n0l00l & n0O0ll); + wire_n0O0li_b <= ( "0" & "0" & "0" & "0" & "1"); + n0O0li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0O0li_a, + b => wire_n0O0li_b, + cin => wire_gnd, + o => wire_n0O0li_o + ); + wire_n0OOOO_a <= ( "0" & rfull_threshold(4 DOWNTO 0) & "1"); + wire_n0OOOO_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n0OOOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0OOOO_a, + b => wire_n0OOOO_b, + cin => wire_gnd, + o => wire_n0OOOO_o + ); + wire_n1010i_a <= ( n11O0l & n11O0i & n11O1O); + wire_n1010i_b <= ( "0" & "0" & "1"); + n1010i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_n1010i_a, + b => wire_n1010i_b, + cin => wire_gnd, + o => wire_n1010i_o + ); + wire_n1l0lO_a <= ( n100ii & n1000O & n1000l & n1000i & n1001O); + wire_n1l0lO_b <= ( "0" & "0" & "0" & "0" & "1"); + n1l0lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1l0lO_a, + b => wire_n1l0lO_b, + cin => wire_gnd, + o => wire_n1l0lO_o + ); + wire_n1O1OO_a <= ( "0" & rins_threshold(4 DOWNTO 0) & "1"); + wire_n1O1OO_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1O1OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n1O1OO_a, + b => wire_n1O1OO_b, + cin => wire_gnd, + o => wire_n1O1OO_o + ); + wire_ni01ii_a <= ( ni1O0l & ni1O0i & ni1O1O & ni1O1l & ni1llO & "1"); + wire_ni01ii_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + ni01ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_ni01ii_a, + b => wire_ni01ii_b, + cin => wire_gnd, + o => wire_ni01ii_o + ); + wire_ni01il_a <= ( ni1O0l & ni1O0i & ni1O1O & ni1O1l & ni1llO); + wire_ni01il_b <= ( "0" & "0" & "0" & "0" & "1"); + ni01il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_ni01il_a, + b => wire_ni01il_b, + cin => wire_gnd, + o => wire_ni01il_o + ); + wire_ni1lii_a <= ( wire_ni1lil_w_lg_w_o_range881w882w & wire_ni1lil_w_lg_w_o_range878w879w & wire_ni1lil_w_lg_w_o_range875w876w & wire_ni1lil_w_lg_w_o_range872w873w & wire_ni1lil_w_lg_w_o_range869w870w & "1"); + wire_ni1lii_b <= ( "1" & "0" & "1" & "0" & "0" & "1"); + ni1lii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_ni1lii_a, + b => wire_ni1lii_b, + cin => wire_gnd, + o => wire_ni1lii_o + ); + wire_ni1lil_w_lg_w_o_range869w870w(0) <= NOT wire_ni1lil_w_o_range869w(0); + wire_ni1lil_w_lg_w_o_range872w873w(0) <= NOT wire_ni1lil_w_o_range872w(0); + wire_ni1lil_w_lg_w_o_range875w876w(0) <= NOT wire_ni1lil_w_o_range875w(0); + wire_ni1lil_w_lg_w_o_range878w879w(0) <= NOT wire_ni1lil_w_o_range878w(0); + wire_ni1lil_w_lg_w_o_range881w882w(0) <= NOT wire_ni1lil_w_o_range881w(0); + wire_ni1lil_a <= ( n0O0OO & nliil0O & nliilii & nliilil & nliiliO & "1"); + wire_ni1lil_b <= ( wire_nii_w_lg_n0l0il864w & wire_nii_w_lg_n0l0ii862w & wire_nii_w_lg_n0l00O860w & wire_nii_w_lg_n0l00l858w & wire_nii_w_lg_n0O0ll856w & "1"); + wire_ni1lil_w_o_range869w(0) <= wire_ni1lil_o(1); + wire_ni1lil_w_o_range872w(0) <= wire_ni1lil_o(2); + wire_ni1lil_w_o_range875w(0) <= wire_ni1lil_o(3); + wire_ni1lil_w_o_range878w(0) <= wire_ni1lil_o(4); + wire_ni1lil_w_o_range881w(0) <= wire_ni1lil_o(5); + ni1lil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_ni1lil_a, + b => wire_ni1lil_b, + cin => wire_gnd, + o => wire_ni1lil_o + ); + wire_ni1liO_a <= ( n0l0il & n0l0ii & n0l00O & n0l00l & n0O0ll & "1"); + wire_ni1liO_b <= ( wire_nii_w_lg_n0O0OO843w & wire_w_lg_nliil0O841w & wire_w_lg_nliilii839w & wire_w_lg_nliilil837w & wire_w_lg_nliiliO835w & "1"); + ni1liO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_ni1liO_a, + b => wire_ni1liO_b, + cin => wire_gnd, + o => wire_ni1liO_o + ); + wire_nl0OOi_a <= ( niOOii & niOO0O & niOO0l & niOO0i & niOO1O); + wire_nl0OOi_b <= ( "0" & "0" & "0" & "0" & "1"); + nl0OOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl0OOi_a, + b => wire_nl0OOi_b, + cin => wire_gnd, + o => wire_nl0OOi_o + ); + wire_nli1iO_a <= ( "0" & rins_threshold(4 DOWNTO 0) & "1"); + wire_nli1iO_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nli1iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nli1iO_a, + b => wire_nli1iO_b, + cin => wire_gnd, + o => wire_nli1iO_o + ); + wire_nllliii_a <= ( nlll1iO & nlll1il & nlll1ii & nlll10O & nlll10l & "1"); + wire_nllliii_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + nllliii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nllliii_a, + b => wire_nllliii_b, + cin => wire_gnd, + o => wire_nllliii_o + ); + wire_nllliil_a <= ( nlll1iO & nlll1il & nlll1ii & nlll10O & nlll10l); + wire_nllliil_b <= ( "0" & "0" & "0" & "0" & "1"); + nllliil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nllliil_a, + b => wire_nllliil_b, + cin => wire_gnd, + o => wire_nllliil_o + ); + wire_nllliOl_a <= ( nlll1iO & nlll1il & nlll1ii & nlll10O); + wire_nllliOl_b <= ( "0" & "0" & "0" & "1"); + nllliOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nllliOl_a, + b => wire_nllliOl_b, + cin => wire_gnd, + o => wire_nllliOl_o + ); + wire_nllll1i_a <= ( nlll1iO & nlll1il & nlll1ii & nlll10O & nlll10l); + wire_nllll1i_b <= ( "0" & "0" & "0" & "1" & "1"); + nllll1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nllll1i_a, + b => wire_nllll1i_b, + cin => wire_gnd, + o => wire_nllll1i_o + ); + wire_nlO000i_w_lg_w_o_range2311w2312w(0) <= NOT wire_nlO000i_w_o_range2311w(0); + wire_nlO000i_w_lg_w_o_range2314w2315w(0) <= NOT wire_nlO000i_w_o_range2314w(0); + wire_nlO000i_w_lg_w_o_range2317w2318w(0) <= NOT wire_nlO000i_w_o_range2317w(0); + wire_nlO000i_w_lg_w_o_range2320w2321w(0) <= NOT wire_nlO000i_w_o_range2320w(0); + wire_nlO000i_w_lg_w_o_range2323w2324w(0) <= NOT wire_nlO000i_w_o_range2323w(0); + wire_nlO000i_a <= ( nlO10Oi & nli0liO & nli0lli & nli0lll & nli0llO & "1"); + wire_nlO000i_b <= ( wire_nii_w_lg_nlllO0i2306w & wire_nii_w_lg_nlllO1O2304w & wire_nii_w_lg_nlllO1l2302w & wire_nii_w_lg_nlllO1i2300w & wire_nii_w_lg_nllllli2298w & "1"); + wire_nlO000i_w_o_range2311w(0) <= wire_nlO000i_o(1); + wire_nlO000i_w_o_range2314w(0) <= wire_nlO000i_o(2); + wire_nlO000i_w_o_range2317w(0) <= wire_nlO000i_o(3); + wire_nlO000i_w_o_range2320w(0) <= wire_nlO000i_o(4); + wire_nlO000i_w_o_range2323w(0) <= wire_nlO000i_o(5); + nlO000i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nlO000i_a, + b => wire_nlO000i_b, + cin => wire_gnd, + o => wire_nlO000i_o + ); + wire_nlO000l_a <= ( nlllO0i & nlllO1O & nlllO1l & nlllO1i & nllllli & "1"); + wire_nlO000l_b <= ( wire_nii_w_lg_nlO10Oi2285w & wire_w_lg_nli0liO2283w & wire_w_lg_nli0lli2281w & wire_w_lg_nli0lll2279w & wire_w_lg_nli0llO2277w & "1"); + nlO000l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nlO000l_a, + b => wire_nlO000l_b, + cin => wire_gnd, + o => wire_nlO000l_o + ); + wire_nlO001O_a <= ( wire_nlO000i_w_lg_w_o_range2323w2324w & wire_nlO000i_w_lg_w_o_range2320w2321w & wire_nlO000i_w_lg_w_o_range2317w2318w & wire_nlO000i_w_lg_w_o_range2314w2315w & wire_nlO000i_w_lg_w_o_range2311w2312w & "1"); + wire_nlO001O_b <= ( "1" & "0" & "1" & "0" & "0" & "1"); + nlO001O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nlO001O_a, + b => wire_nlO001O_b, + cin => wire_gnd, + o => wire_nlO001O_o + ); + wire_nlO0lli_a <= ( "0" & rfull_threshold(4 DOWNTO 0) & "1"); + wire_nlO0lli_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlO0lli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlO0lli_a, + b => wire_nlO0lli_b, + cin => wire_gnd, + o => wire_nlO0lli_o + ); + wire_nlO101i_a <= ( nlllO0i & nlllO1O & nlllO1l & nlllO1i & nllllli & "1"); + wire_nlO101i_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + nlO101i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nlO101i_a, + b => wire_nlO101i_b, + cin => wire_gnd, + o => wire_nlO101i_o + ); + wire_nlO10iO_a <= ( nlllO0i & nlllO1O & nlllO1l & nlllO1i & nllllli); + wire_nlO10iO_b <= ( "0" & "0" & "0" & "0" & "1"); + nlO10iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlO10iO_a, + b => wire_nlO10iO_b, + cin => wire_gnd, + o => wire_nlO10iO_o + ); + wire_n011iO_i <= ( nli1Ol & nli1Oi & nli1lO & nli1ll); + n011iO : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_n011iO_i, + o => wire_n011iO_o + ); + wire_n011ll_i <= ( nli1Ol & nli1Oi); + n011ll : oper_decoder + GENERIC MAP ( + width_i => 2, + width_o => 4 + ) + PORT MAP ( + i => wire_n011ll_i, + o => wire_n011ll_o + ); + wire_n011Oi_i <= ( nli1Ol & nli1Oi & nli1lO & nli1ll & nl1i0i); + n011Oi : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_n011Oi_i, + o => wire_n011Oi_o + ); + wire_n0OO1l_i <= ( wire_ni1l1i_dataout & wire_ni1iOO_dataout & wire_ni1iOl_dataout & wire_ni1iOi_dataout & wire_ni1ilO_dataout); + n0OO1l : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_n0OO1l_i, + o => wire_n0OO1l_o + ); + wire_n1l00O_i <= ( n100ii & n1000O & n1000l & n1000i & n1001O); + n1l00O : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_n1l00O_i, + o => wire_n1l00O_o + ); + wire_n1l01l_i <= ( n100ii & n1000l & n1000i & n1001O); + n1l01l : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_n1l01l_i, + o => wire_n1l01l_o + ); + wire_n1l1OO_i <= ( n100ii & n1000O & n1000l & n1000i); + n1l1OO : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_n1l1OO_i, + o => wire_n1l1OO_o + ); + wire_n1OliO_i <= ( rskpsetbased & rclkcmpsqmd); + n1OliO : oper_decoder + GENERIC MAP ( + width_i => 2, + width_o => 4 + ) + PORT MAP ( + i => wire_n1OliO_i, + o => wire_n1OliO_o + ); + wire_nl0O1i_i <= ( niOOii & niOO0O & niOO0l & niOO0i); + nl0O1i : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nl0O1i_i, + o => wire_nl0O1i_o + ); + wire_nl0O1O_i <= ( niOOii & niOO0l & niOO0i & niOO1O); + nl0O1O : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nl0O1O_i, + o => wire_nl0O1O_o + ); + wire_nl0Oii_i <= ( niOOii & niOO0O & niOO0l & niOO0i & niOO1O); + nl0Oii : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_nl0Oii_i, + o => wire_nl0Oii_o + ); + wire_nliO01i_i <= ( n1O00l & n1O00i & n1O01O & n1O01l & n1ll1l); + nliO01i : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_nliO01i_i, + o => wire_nliO01i_o + ); + wire_nliO1lO_i <= ( n1O00l & n1O00i & n1O01O & n1O01l); + nliO1lO : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nliO1lO_i, + o => wire_nliO1lO_o + ); + wire_nliO1Ol_i <= ( n1O00l & n1O00i); + nliO1Ol : oper_decoder + GENERIC MAP ( + width_i => 2, + width_o => 4 + ) + PORT MAP ( + i => wire_nliO1Ol_i, + o => wire_nliO1Ol_o + ); + wire_nlli01O_i <= ( wire_nlO01lO_dataout & wire_nlO01ll_dataout & wire_nlO01li_dataout & wire_nlO01iO_dataout & wire_nlO01il_dataout); + nlli01O : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_nlli01O_i, + o => wire_nlli01O_o + ); + wire_n11iii_a <= ( nlO011i & nlO1OOO & nlO1OOl & nlO1OOi & nlO1OiO); + wire_n11iii_b <= ( "0" & "0" & rempty_threshold(2 DOWNTO 0)); + n11iii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_n11iii_a, + b => wire_n11iii_b, + cin => wire_gnd, + o => wire_n11iii_o + ); + wire_n1O01i_a <= ( rins_threshold(4 DOWNTO 0)); + wire_n1O01i_b <= ( nlii01l & wire_nliO1Ol_o(1) & nlii01O & nlii00i & nlii00l); + n1O01i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_n1O01i_a, + b => wire_n1O01i_b, + cin => wire_vcc, + o => wire_n1O01i_o + ); + wire_n1O10l_a <= ( "0" & "0" & "0"); + wire_n1O10l_b <= ( n11O0l & n11O0i & n11O1O); + n1O10l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n1O10l_a, + b => wire_n1O10l_b, + cin => wire_gnd, + o => wire_n1O10l_o + ); + wire_n1O11l_a <= ( n11O0l & n11O0i & n11O1O); + wire_n1O11l_b <= ( "1" & "0" & "1"); + n1O11l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n1O11l_a, + b => wire_n1O11l_b, + cin => wire_gnd, + o => wire_n1O11l_o + ); + wire_n1OllO_w_lg_o2372w(0) <= wire_n1OllO_o AND wire_w_lg_w_lg_w_lg_rskpsetbased2366w2370w2371w(0); + wire_n1OllO_w_lg_o2549w(0) <= wire_n1OllO_o AND wire_w_lg_nli0O1i2548w(0); + wire_n1OllO_a <= ( rdel_threshold(4 DOWNTO 0)); + wire_n1OllO_b <= ( nlO011i & nlO1OOO & nlO1OOl & nlO1OOi & nlO1OiO); + n1OllO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_n1OllO_a, + b => wire_n1OllO_b, + cin => wire_gnd, + o => wire_n1OllO_o + ); + wire_n1OlOi_a <= ( nlO011i & nlO1OOO & nlO1OOl & nlO1OOi & nlO1OiO); + wire_n1OlOi_b <= ( rins_threshold(4 DOWNTO 0)); + n1OlOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_n1OlOi_a, + b => wire_n1OlOi_b, + cin => wire_gnd, + o => wire_n1OlOi_o + ); + wire_n1OOlO_a <= ( nlO011i & nlO1OOO & nlO1OOl & nlO1OOi & nlO1OiO); + wire_n1OOlO_b <= ( rdel_threshold(4 DOWNTO 0)); + n1OOlO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_n1OOlO_a, + b => wire_n1OOlO_b, + cin => wire_vcc, + o => wire_n1OOlO_o + ); + wire_n1OOOi_a <= ( rins_threshold(4 DOWNTO 0)); + wire_n1OOOi_b <= ( nlO011i & nlO1OOO & nlO1OOl & nlO1OOi & nlO1OiO); + n1OOOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_n1OOOi_a, + b => wire_n1OOOi_b, + cin => wire_vcc, + o => wire_n1OOOi_o + ); + wire_ni1i1i_a <= ( "0" & "0" & "0" & "0" & "0"); + wire_ni1i1i_b <= ( n0O0OO & nliil0O & nliilii & nliilil & nliiliO); + ni1i1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_ni1i1i_a, + b => wire_ni1i1i_b, + cin => wire_gnd, + o => wire_ni1i1i_o + ); + wire_ni1lli_a <= ( n0O0OO & nliil0O & nliilii & nliilil & nliiliO); + wire_ni1lli_b <= ( n0l0il & n0l0ii & n0l00O & n0l00l & n0O0ll); + ni1lli : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_ni1lli_a, + b => wire_ni1lli_b, + cin => wire_gnd, + o => wire_ni1lli_o + ); + wire_nli1li_a <= ( rins_threshold(4 DOWNTO 0)); + wire_nli1li_b <= ( nlil1Oi & wire_n011ll_o(1) & nlil1Ol & nlil1OO & nlil01i); + nli1li : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nli1li_a, + b => wire_nli1li_b, + cin => wire_vcc, + o => wire_nli1li_o + ); + wire_nlilOi_a <= ( ni1i0l & ni1i0i & ni1i1O & ni1i1l & ni101l); + wire_nlilOi_b <= ( "0" & "0" & rempty_threshold(2 DOWNTO 0)); + nlilOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nlilOi_a, + b => wire_nlilOi_b, + cin => wire_gnd, + o => wire_nlilOi_o + ); + wire_nlli0iO_a <= ( "0" & "0" & "0" & "0" & "0"); + wire_nlli0iO_b <= ( nlO10Oi & nli0liO & nli0lli & nli0lll & nli0llO); + nlli0iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nlli0iO_a, + b => wire_nlli0iO_b, + cin => wire_gnd, + o => wire_nlli0iO_o + ); + wire_nllOii_a <= ( wire_nlililO40_w_lg_w_lg_q396w397w & ni1i0i & ni1i1O & ni1i1l & ni101l); + wire_nllOii_b <= ( rdel_threshold(4) & wire_nlilill42_w_lg_w_lg_q405w406w & rdel_threshold(2 DOWNTO 0)); + nllOii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nllOii_a, + b => wire_nllOii_b, + cin => wire_vcc, + o => wire_nllOii_o + ); + wire_nllOil_a <= ( rins_threshold(4 DOWNTO 0)); + wire_nllOil_b <= ( ni1i0l & ni1i0i & ni1i1O & ni1i1l & ni101l); + nllOil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nllOil_a, + b => wire_nllOil_b, + cin => wire_vcc, + o => wire_nllOil_o + ); + wire_nllOiO_a <= ( rdel_threshold(4 DOWNTO 0)); + wire_nllOiO_b <= ( ni1i0l & ni1i0i & ni1i1O & wire_nliliOi38_w_lg_w_lg_q369w370w & ni101l); + nllOiO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nllOiO_a, + b => wire_nllOiO_b, + cin => wire_gnd, + o => wire_nllOiO_o + ); + wire_nllOli_a <= ( ni1i0l & ni1i0i & wire_nliliOl36_w_lg_w_lg_q332w333w & ni1i1l & ni101l); + wire_nllOli_b <= ( rins_threshold(4 DOWNTO 0)); + nllOli : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nllOli_a, + b => wire_nllOli_b, + cin => wire_gnd, + o => wire_nllOli_o + ); + wire_nlO000O_a <= ( nlO10Oi & nli0liO & nli0lli & nli0lll & nli0llO); + wire_nlO000O_b <= ( nlllO0i & nlllO1O & nlllO1l & nlllO1i & nllllli); + nlO000O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nlO000O_a, + b => wire_nlO000O_b, + cin => wire_gnd, + o => wire_nlO000O_o + ); + wire_nllOOO_data <= ( wire_nliliOO34_w_lg_w_lg_q166w167w & wire_nlO10O_dataout & nlO01O & nlO01O); + wire_nllOOO_sel <= ( nlO01l & nllOOl); + nllOOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOOO_data, + o => wire_nllOOO_o, + sel => wire_nllOOO_sel + ); + wire_nlO11i_data <= ( wire_nlO1li_dataout & wire_nlill1i32_w_lg_w_lg_q155w156w & wire_nlill1l30_w_lg_w_lg_q152w153w & nllOOi); + wire_nlO11i_sel <= ( nlO01l & nllOOl); + nlO11i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO11i_data, + o => wire_nlO11i_o, + sel => wire_nlO11i_sel + ); + wire_nlO11l_data <= ( wire_nlO1ll_dataout & wire_nlO10i_dataout & wire_nl00O_dataout & wire_nl0ii_w_lg_w_lg_dataout138w141w); + wire_nlO11l_sel <= ( nlO01l & nllOOl); + nlO11l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO11l_data, + o => wire_nlO11l_o, + sel => wire_nlO11l_sel + ); + wire_nlO11O_data <= ( wire_nl00O_dataout & wire_nl00O_dataout & wire_nlO1OO_dataout & "0"); + wire_nlO11O_sel <= ( nlO01l & wire_nlill0l26_w_lg_w_lg_q124w125w); + nlO11O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO11O_data, + o => wire_nlO11O_o, + sel => wire_nlO11O_sel + ); + wire_nllOll_data_in <= ( wire_nl10i_dataout & wire_nl11O_dataout & wire_nl11l_dataout & wire_nl11i_dataout & wire_niOOO_dataout & wire_niOOl_dataout & wire_niOOi_dataout & wire_niOlO_dataout & wire_niOll_dataout & wire_niOli_dataout & wire_niOiO_dataout & wire_niOil_dataout & wire_niOii_dataout & wire_niO0O_dataout & wire_niO0l_dataout & wire_niO0i_dataout); + wire_nllOll_fifo_re1 <= ( wire_n1ii_dataout & wire_n10O_dataout & wire_n10l_dataout & wire_n10i_dataout & wire_n11O_dataout & wire_n11l_dataout & wire_n11i_dataout & wire_nlOOO_dataout & wire_nlOOl_dataout & wire_nlOOi_dataout & wire_nlOlO_dataout & wire_nlOll_dataout & wire_nlOli_dataout & wire_nlOiO_dataout & wire_nlOil_dataout & wire_nlOii_dataout & wire_nlO0O_dataout & wire_nlO0l_dataout & wire_nlO0i_dataout & wire_nlO1O_dataout); + wire_nllOll_fifo_re2 <= ( wire_nlO1l_dataout & wire_nlO1i_dataout & wire_nllOO_dataout & wire_nllOl_dataout & wire_nllOi_dataout & wire_nlllO_dataout & wire_nllll_dataout & wire_nllli_dataout & wire_nlliO_dataout & wire_nllil_dataout & wire_nllii_dataout & wire_nll0O_dataout & wire_nll0l_dataout & wire_nll0i_dataout & wire_nll1O_dataout & wire_nll1l_dataout & wire_nll1i_dataout & wire_nliOO_dataout & wire_nliOl_dataout & wire_nliOi_dataout); + wire_nllOll_fifo_wr <= ( wire_nlilO_dataout & wire_nlill_dataout & wire_nlili_dataout & wire_nliiO_dataout & wire_nliil_dataout & wire_nliii_dataout & wire_nli0O_dataout & wire_nli0l_dataout & wire_nli0i_dataout & wire_nli1O_dataout & wire_nli1l_dataout & wire_nli1i_dataout & wire_nl0OO_dataout & wire_nl0Ol_dataout & wire_nl0Oi_dataout & wire_nl0lO_dataout & wire_nl0ll_dataout & wire_nl0li_dataout & wire_nl0iO_dataout & wire_nl0il_dataout); + wire_nllOll_rst_l <= wire_nl0i_w_lg_dataout4w(0); + nllOll : cycloneiv_hssi_rx_digis_ram20x16_syn + GENERIC MAP ( + ram_width => 16, + read_access_time => 0, + write_access_time => 0 + ) + PORT MAP ( + clk => clk_1, + data_in => wire_nllOll_data_in, + data_out1 => wire_nllOll_data_out1, + data_out2 => wire_nllOll_data_out2, + fifo_re1 => wire_nllOll_fifo_re1, + fifo_re2 => wire_nllOll_fifo_re2, + fifo_wr => wire_nllOll_fifo_wr, + rst_l => wire_nllOll_rst_l + ); + wire_nllOlO_data_in <= ( wire_nl00l_dataout & wire_nl00i_dataout & wire_nl01O_dataout & wire_nl01l_dataout & wire_nl01i_dataout & wire_nl1OO_dataout & wire_nl1Ol_dataout & wire_nl1Oi_dataout & wire_nl1lO_dataout & wire_nl1ll_dataout & wire_nl1li_dataout & wire_nl1iO_dataout & wire_nl1il_dataout & wire_nl1ii_dataout & wire_nl10O_dataout & wire_nl10l_dataout); + wire_nllOlO_fifo_re1 <= ( wire_n1ii_dataout & wire_n10O_dataout & wire_n10l_dataout & wire_n10i_dataout & wire_n11O_dataout & wire_n11l_dataout & wire_n11i_dataout & wire_nlOOO_dataout & wire_nlOOl_dataout & wire_nlOOi_dataout & wire_nlOlO_dataout & wire_nlOll_dataout & wire_nlOli_dataout & wire_nlOiO_dataout & wire_nlOil_dataout & wire_nlOii_dataout & wire_nlO0O_dataout & wire_nlO0l_dataout & wire_nlO0i_dataout & wire_nlO1O_dataout); + wire_nllOlO_fifo_re2 <= ( wire_nlO1l_dataout & wire_nlO1i_dataout & wire_nllOO_dataout & wire_nllOl_dataout & wire_nllOi_dataout & wire_nlllO_dataout & wire_nllll_dataout & wire_nllli_dataout & wire_nlliO_dataout & wire_nllil_dataout & wire_nllii_dataout & wire_nll0O_dataout & wire_nll0l_dataout & wire_nll0i_dataout & wire_nll1O_dataout & wire_nll1l_dataout & wire_nll1i_dataout & wire_nliOO_dataout & wire_nliOl_dataout & wire_nliOi_dataout); + wire_nllOlO_fifo_wr <= ( wire_nlilO_dataout & wire_nlill_dataout & wire_nlili_dataout & wire_nliiO_dataout & wire_nliil_dataout & wire_nliii_dataout & wire_nli0O_dataout & wire_nli0l_dataout & wire_nli0i_dataout & wire_nli1O_dataout & wire_nli1l_dataout & wire_nli1i_dataout & wire_nl0OO_dataout & wire_nl0Ol_dataout & wire_nl0Oi_dataout & wire_nl0lO_dataout & wire_nl0ll_dataout & wire_nl0li_dataout & wire_nl0iO_dataout & wire_nl0il_dataout); + wire_nllOlO_rst_l <= wire_nl0i_w_lg_dataout4w(0); + nllOlO : cycloneiv_hssi_rx_digis_ram20x16_syn + GENERIC MAP ( + ram_width => 16, + read_access_time => 0, + write_access_time => 0 + ) + PORT MAP ( + clk => clk_1, + data_in => wire_nllOlO_data_in, + data_out1 => wire_nllOlO_data_out1, + data_out2 => wire_nllOlO_data_out2, + fifo_re1 => wire_nllOlO_fifo_re1, + fifo_re2 => wire_nllOlO_fifo_re2, + fifo_wr => wire_nllOlO_fifo_wr, + rst_l => wire_nllOlO_rst_l + ); + + END RTL; --cycloneiv_hssi_rx_digi_comp_chnl_top +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 9.0 cbx_mgl 2008:11:18:11:51:17:SJ cbx_simgen 2008:08:06:16:30:59:SJ VERSION_END + + +-- Legal Notice: © 2003 Altera Corporation. All rights reserved. +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). Your use of Altera +-- Corporation's design tools, logic functions and other software and tools, +-- and its AMPP partner logic functions, and any output files any of the +-- foregoing (including device programming or simulation files), and any +-- associated documentation or information are expressly subject to the +-- terms and conditions of the Altera Program License Subscription Agreement +-- or other applicable license agreement, including, without limitation, that +-- your use is for the sole purpose of programming logic devices manufactured +-- by Altera and sold by Altera or its authorized distributors. Please refer +-- to the applicable agreement for further details. + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 419 mux21 1388 oper_decoder 5 oper_mux 200 oper_selector 2 cycloneiv_hssi_rx_digis_ph_fifo 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_rx_ctrl IS + PORT + ( + bytord_valid_out : OUT STD_LOGIC; + bytordplden : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + dec_data_valid : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + dec_data_valid_pre : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + dis_pc_byte : IN STD_LOGIC; + disp_err_delay : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + disp_val_delay : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + endec_rx : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + invalid_code_delay : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + ovr_undflow : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + pcs_wrapback_in : IN STD_LOGIC_VECTOR (69 DOWNTO 0); + ph_fifo_empty : OUT STD_LOGIC; + ph_fifo_full : OUT STD_LOGIC; + phystatus : OUT STD_LOGIC; + phystatus_int : IN STD_LOGIC; + pipe_data : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + pld_re : IN STD_LOGIC; + pld_wr_dis : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rauto_speed_ena : IN STD_LOGIC; + rautoinsdis : IN STD_LOGIC; + rbytord_2sym_en : IN STD_LOGIC; + rbytord_6g_mask_en : IN STD_LOGIC; + rbytord_s2gx : IN STD_LOGIC; + rbytorden : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rbytordpadval : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + rbytordpat : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + rbytordplden : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rd_enable2 : OUT STD_LOGIC; + rd_enable_centrl : IN STD_LOGIC; + rd_enable_out : OUT STD_LOGIC; + rd_enable_quad_down : IN STD_LOGIC; + rd_enable_quad_up : IN STD_LOGIC; + rdwidth : IN STD_LOGIC; + rendec_data_sel_rx : IN STD_LOGIC; + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rinvalid_code_err_only : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rpcs_wrapback_en : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rpmadatawidth : IN STD_LOGIC; + rptr_bin : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + rrx_pipe_enable : IN STD_LOGIC; + rrxfifo_dis : IN STD_LOGIC; + rrxfifo_lowlatency_en : IN STD_LOGIC; + rrxfifo_urst_en : IN STD_LOGIC; + rrxpcsbypass_en : IN STD_LOGIC; + rrxphfifopldctl_en : IN STD_LOGIC; + rsync_comp_pat : IN STD_LOGIC_VECTOR (39 DOWNTO 0); + rsync_comp_porn : IN STD_LOGIC; + rsync_comp_size : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rsync_sm_dis : IN STD_LOGIC; + running_disp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + rwa_6g_en : IN STD_LOGIC; + rx_control_dt : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rx_control_rs : IN STD_LOGIC; + rx_data_dt : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rx_data_rs : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_rd_clk : IN STD_LOGIC; + rx_we_in_centrl : IN STD_LOGIC; + rx_we_in_quad_down : IN STD_LOGIC; + rx_we_in_quad_up : IN STD_LOGIC; + rx_we_out : OUT STD_LOGIC; + rx_wr_clk : IN STD_LOGIC; + rxc : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rxd : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rxd_19 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + rxd_9 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + rxd_lpbk : OUT STD_LOGIC_VECTOR (39 DOWNTO 0); + rxfifo_urst : IN STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus_int : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxvalid : OUT STD_LOGIC; + rxvalid_int : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + sigdetni : IN STD_LOGIC; + signal_detect_out : OUT STD_LOGIC; + soft_reset : IN STD_LOGIC; + soft_reset_rclk1 : OUT STD_LOGIC; + soft_reset_wclk1 : OUT STD_LOGIC; + sync_resync_delay : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + sync_resync_pre : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + tenb_data : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + wptr_bin : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + wr_enable2 : OUT STD_LOGIC; + wr_enable_centrl : IN STD_LOGIC; + wr_enable_out : OUT STD_LOGIC; + wr_enable_quad_down : IN STD_LOGIC; + wr_enable_quad_up : IN STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_rx_ctrl; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_rx_ctrl IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL niOllOO57 : STD_LOGIC := '0'; + SIGNAL niOllOO58 : STD_LOGIC := '0'; + SIGNAL niOlO1i55 : STD_LOGIC := '0'; + SIGNAL niOlO1i56 : STD_LOGIC := '0'; + SIGNAL niOOO0i49 : STD_LOGIC := '0'; + SIGNAL niOOO0i50 : STD_LOGIC := '0'; + SIGNAL niOOO0O47 : STD_LOGIC := '0'; + SIGNAL niOOO0O48 : STD_LOGIC := '0'; + SIGNAL niOOO1l53 : STD_LOGIC := '0'; + SIGNAL niOOO1l54 : STD_LOGIC := '0'; + SIGNAL niOOO1O51 : STD_LOGIC := '0'; + SIGNAL niOOO1O52 : STD_LOGIC := '0'; + SIGNAL niOOOOO45 : STD_LOGIC := '0'; + SIGNAL niOOOOO46 : STD_LOGIC := '0'; + SIGNAL nl1010l11 : STD_LOGIC := '0'; + SIGNAL nl1010l12 : STD_LOGIC := '0'; + SIGNAL wire_nl1010l12_w_lg_w_lg_q111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1010l12_w_lg_q111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1010O10 : STD_LOGIC := '0'; + SIGNAL wire_nl1010O10_w_lg_w_lg_q106w107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1010O10_w_lg_q106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1010O9 : STD_LOGIC := '0'; + SIGNAL nl1011i15 : STD_LOGIC := '0'; + SIGNAL nl1011i16 : STD_LOGIC := '0'; + SIGNAL wire_nl1011i16_w_lg_w_lg_q221w222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1011i16_w_lg_q221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1011O13 : STD_LOGIC := '0'; + SIGNAL nl1011O14 : STD_LOGIC := '0'; + SIGNAL wire_nl1011O14_w_lg_w_lg_q214w215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1011O14_w_lg_q214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl101ii7 : STD_LOGIC := '0'; + SIGNAL nl101ii8 : STD_LOGIC := '0'; + SIGNAL wire_nl101ii8_w_lg_w_lg_q102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl101ii8_w_lg_q102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl101iO5 : STD_LOGIC := '0'; + SIGNAL nl101iO6 : STD_LOGIC := '0'; + SIGNAL nl101lO3 : STD_LOGIC := '0'; + SIGNAL nl101lO4 : STD_LOGIC := '0'; + SIGNAL nl101OO1 : STD_LOGIC := '0'; + SIGNAL nl101OO2 : STD_LOGIC := '0'; + SIGNAL nl1111i43 : STD_LOGIC := '0'; + SIGNAL nl1111i44 : STD_LOGIC := '0'; + SIGNAL nl111ii41 : STD_LOGIC := '0'; + SIGNAL nl111ii42 : STD_LOGIC := '0'; + SIGNAL nl11l0l35 : STD_LOGIC := '0'; + SIGNAL nl11l0l36 : STD_LOGIC := '0'; + SIGNAL wire_nl11l0l36_w_lg_q296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11l1l39 : STD_LOGIC := '0'; + SIGNAL nl11l1l40 : STD_LOGIC := '0'; + SIGNAL wire_nl11l1l40_w_lg_w_lg_q303w304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11l1l40_w_lg_q303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11l1O37 : STD_LOGIC := '0'; + SIGNAL nl11l1O38 : STD_LOGIC := '0'; + SIGNAL wire_nl11l1O38_w_lg_w_lg_q300w301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11l1O38_w_lg_q300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11liO33 : STD_LOGIC := '0'; + SIGNAL nl11liO34 : STD_LOGIC := '0'; + SIGNAL wire_nl11liO34_w_lg_w_lg_q291w292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11liO34_w_lg_q291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11lli31 : STD_LOGIC := '0'; + SIGNAL nl11lli32 : STD_LOGIC := '0'; + SIGNAL wire_nl11lli32_w_lg_q288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11lOl29 : STD_LOGIC := '0'; + SIGNAL nl11lOl30 : STD_LOGIC := '0'; + SIGNAL wire_nl11lOl30_w_lg_w_lg_q279w280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11lOl30_w_lg_q279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11lOO27 : STD_LOGIC := '0'; + SIGNAL nl11lOO28 : STD_LOGIC := '0'; + SIGNAL wire_nl11lOO28_w_lg_q277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11O0O25 : STD_LOGIC := '0'; + SIGNAL nl11O0O26 : STD_LOGIC := '0'; + SIGNAL wire_nl11O0O26_w_lg_w_lg_q264w265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11O0O26_w_lg_q264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11Oli23 : STD_LOGIC := '0'; + SIGNAL nl11Oli24 : STD_LOGIC := '0'; + SIGNAL wire_nl11Oli24_w_lg_w_lg_q257w258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11Oli24_w_lg_q257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11OlO21 : STD_LOGIC := '0'; + SIGNAL nl11OlO22 : STD_LOGIC := '0'; + SIGNAL wire_nl11OlO22_w_lg_w_lg_q242w243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11OlO22_w_lg_q242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11OOi19 : STD_LOGIC := '0'; + SIGNAL nl11OOi20 : STD_LOGIC := '0'; + SIGNAL wire_nl11OOi20_w_lg_w_lg_q239w240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11OOi20_w_lg_q239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl11OOO17 : STD_LOGIC := '0'; + SIGNAL nl11OOO18 : STD_LOGIC := '0'; + SIGNAL wire_nl11OOO18_w_lg_w_lg_q228w229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11OOO18_w_lg_q228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1i0i : STD_LOGIC := '0'; + SIGNAL n1i0O : STD_LOGIC := '0'; + SIGNAL n1i1O : STD_LOGIC := '0'; + SIGNAL n1iii : STD_LOGIC := '0'; + SIGNAL n1iil : STD_LOGIC := '0'; + SIGNAL n1iiO : STD_LOGIC := '0'; + SIGNAL n1ili : STD_LOGIC := '0'; + SIGNAL n1ilO : STD_LOGIC := '0'; + SIGNAL nli0iO : STD_LOGIC := '0'; + SIGNAL nlilOO : STD_LOGIC := '0'; + SIGNAL nliO0i : STD_LOGIC := '0'; + SIGNAL nliO0l : STD_LOGIC := '0'; + SIGNAL nliO0O : STD_LOGIC := '0'; + SIGNAL nliO1i : STD_LOGIC := '0'; + SIGNAL nliOii : STD_LOGIC := '0'; + SIGNAL nliOil : STD_LOGIC := '0'; + SIGNAL nliOiO : STD_LOGIC := '0'; + SIGNAL nliOli : STD_LOGIC := '0'; + SIGNAL nliOll : STD_LOGIC := '0'; + SIGNAL nliOlO : STD_LOGIC := '0'; + SIGNAL nliOOi : STD_LOGIC := '0'; + SIGNAL nliOOl : STD_LOGIC := '0'; + SIGNAL nliOOO : STD_LOGIC := '0'; + SIGNAL nll00i : STD_LOGIC := '0'; + SIGNAL nll00l : STD_LOGIC := '0'; + SIGNAL nll00O : STD_LOGIC := '0'; + SIGNAL nll01i : STD_LOGIC := '0'; + SIGNAL nll01l : STD_LOGIC := '0'; + SIGNAL nll01O : STD_LOGIC := '0'; + SIGNAL nll0ii : STD_LOGIC := '0'; + SIGNAL nll0il : STD_LOGIC := '0'; + SIGNAL nll0iO : STD_LOGIC := '0'; + SIGNAL nll0li : STD_LOGIC := '0'; + SIGNAL nll0ll : STD_LOGIC := '0'; + SIGNAL nll0lO : STD_LOGIC := '0'; + SIGNAL nll0Oi : STD_LOGIC := '0'; + SIGNAL nll0Ol : STD_LOGIC := '0'; + SIGNAL nll0OO : STD_LOGIC := '0'; + SIGNAL nll10i : STD_LOGIC := '0'; + SIGNAL nll10l : STD_LOGIC := '0'; + SIGNAL nll10O : STD_LOGIC := '0'; + SIGNAL nll11i : STD_LOGIC := '0'; + SIGNAL nll11l : STD_LOGIC := '0'; + SIGNAL nll11O : STD_LOGIC := '0'; + SIGNAL nll1ii : STD_LOGIC := '0'; + SIGNAL nll1il : STD_LOGIC := '0'; + SIGNAL nll1iO : STD_LOGIC := '0'; + SIGNAL nll1li : STD_LOGIC := '0'; + SIGNAL nll1ll : STD_LOGIC := '0'; + SIGNAL nll1lO : STD_LOGIC := '0'; + SIGNAL nll1Oi : STD_LOGIC := '0'; + SIGNAL nll1Ol : STD_LOGIC := '0'; + SIGNAL nll1OO : STD_LOGIC := '0'; + SIGNAL nlli0i : STD_LOGIC := '0'; + SIGNAL nlli0l : STD_LOGIC := '0'; + SIGNAL nlli0O : STD_LOGIC := '0'; + SIGNAL nlli1i : STD_LOGIC := '0'; + SIGNAL nlli1l : STD_LOGIC := '0'; + SIGNAL nlli1O : STD_LOGIC := '0'; + SIGNAL nlliii : STD_LOGIC := '0'; + SIGNAL nlliil : STD_LOGIC := '0'; + SIGNAL nlliiO : STD_LOGIC := '0'; + SIGNAL nllili : STD_LOGIC := '0'; + SIGNAL nllill : STD_LOGIC := '0'; + SIGNAL nllilO : STD_LOGIC := '0'; + SIGNAL nlliOi : STD_LOGIC := '0'; + SIGNAL nlliOl : STD_LOGIC := '0'; + SIGNAL nlliOO : STD_LOGIC := '0'; + SIGNAL nlll0i : STD_LOGIC := '0'; + SIGNAL nlll0l : STD_LOGIC := '0'; + SIGNAL nlll0O : STD_LOGIC := '0'; + SIGNAL nlll1i : STD_LOGIC := '0'; + SIGNAL nlll1l : STD_LOGIC := '0'; + SIGNAL nlll1O : STD_LOGIC := '0'; + SIGNAL nlllii : STD_LOGIC := '0'; + SIGNAL nlllil : STD_LOGIC := '0'; + SIGNAL nllliO : STD_LOGIC := '0'; + SIGNAL nlllli : STD_LOGIC := '0'; + SIGNAL nlllll : STD_LOGIC := '0'; + SIGNAL nllllO : STD_LOGIC := '0'; + SIGNAL nlllOi : STD_LOGIC := '0'; + SIGNAL nlllOl : STD_LOGIC := '0'; + SIGNAL nlO10Ol : STD_LOGIC := '0'; + SIGNAL nlO10OO : STD_LOGIC := '0'; + SIGNAL nlO1ili : STD_LOGIC := '0'; + SIGNAL nlOl0O : STD_LOGIC := '0'; + SIGNAL wire_n1ill_CLRN : STD_LOGIC; + SIGNAL wire_n1ill_w_lg_w_lg_nll10l275w278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_w_lg_n1ili661w662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_n1iil670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nliOOi312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nliOOO284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nll10i308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nll10l275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nll11l494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nll11O482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_n1i0i4636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_n1iii669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_n1iil658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_n1iiO656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_n1ili661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_n1ilO602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nll0ll513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ill_w_lg_nll0lO536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOiil : STD_LOGIC := '0'; + SIGNAL nl011i : STD_LOGIC := '0'; + SIGNAL nl011O : STD_LOGIC := '0'; + SIGNAL nl1OOO : STD_LOGIC := '0'; + SIGNAL wire_nl011l_CLRN : STD_LOGIC; + SIGNAL wire_nl011l_PRN : STD_LOGIC; + SIGNAL nli00i : STD_LOGIC := '0'; + SIGNAL nli1iO : STD_LOGIC := '0'; + SIGNAL wire_nli01O_PRN : STD_LOGIC; + SIGNAL nli00l : STD_LOGIC := '0'; + SIGNAL nli0il : STD_LOGIC := '0'; + SIGNAL niiO0i : STD_LOGIC := '0'; + SIGNAL niiO0l : STD_LOGIC := '0'; + SIGNAL niiO0O : STD_LOGIC := '0'; + SIGNAL niiO1O : STD_LOGIC := '0'; + SIGNAL niiOii : STD_LOGIC := '0'; + SIGNAL niiOil : STD_LOGIC := '0'; + SIGNAL niiOiO : STD_LOGIC := '0'; + SIGNAL niiOli : STD_LOGIC := '0'; + SIGNAL niiOll : STD_LOGIC := '0'; + SIGNAL niiOlO : STD_LOGIC := '0'; + SIGNAL niiOOi : STD_LOGIC := '0'; + SIGNAL niiOOl : STD_LOGIC := '0'; + SIGNAL niiOOO : STD_LOGIC := '0'; + SIGNAL nil00i : STD_LOGIC := '0'; + SIGNAL nil00l : STD_LOGIC := '0'; + SIGNAL nil00O : STD_LOGIC := '0'; + SIGNAL nil01i : STD_LOGIC := '0'; + SIGNAL nil01l : STD_LOGIC := '0'; + SIGNAL nil01O : STD_LOGIC := '0'; + SIGNAL nil0ii : STD_LOGIC := '0'; + SIGNAL nil0il : STD_LOGIC := '0'; + SIGNAL nil0iO : STD_LOGIC := '0'; + SIGNAL nil0li : STD_LOGIC := '0'; + SIGNAL nil0ll : STD_LOGIC := '0'; + SIGNAL nil0lO : STD_LOGIC := '0'; + SIGNAL nil0Oi : STD_LOGIC := '0'; + SIGNAL nil0Ol : STD_LOGIC := '0'; + SIGNAL nil0OO : STD_LOGIC := '0'; + SIGNAL nil10i : STD_LOGIC := '0'; + SIGNAL nil10l : STD_LOGIC := '0'; + SIGNAL nil10O : STD_LOGIC := '0'; + SIGNAL nil11i : STD_LOGIC := '0'; + SIGNAL nil11l : STD_LOGIC := '0'; + SIGNAL nil11O : STD_LOGIC := '0'; + SIGNAL nil1ii : STD_LOGIC := '0'; + SIGNAL nil1il : STD_LOGIC := '0'; + SIGNAL nil1iO : STD_LOGIC := '0'; + SIGNAL nil1li : STD_LOGIC := '0'; + SIGNAL nil1ll : STD_LOGIC := '0'; + SIGNAL nil1lO : STD_LOGIC := '0'; + SIGNAL nil1Oi : STD_LOGIC := '0'; + SIGNAL nil1Ol : STD_LOGIC := '0'; + SIGNAL nil1OO : STD_LOGIC := '0'; + SIGNAL nili0i : STD_LOGIC := '0'; + SIGNAL nili0l : STD_LOGIC := '0'; + SIGNAL nili0O : STD_LOGIC := '0'; + SIGNAL nili1i : STD_LOGIC := '0'; + SIGNAL nili1l : STD_LOGIC := '0'; + SIGNAL nili1O : STD_LOGIC := '0'; + SIGNAL niliii : STD_LOGIC := '0'; + SIGNAL niliil : STD_LOGIC := '0'; + SIGNAL niliiO : STD_LOGIC := '0'; + SIGNAL nilili : STD_LOGIC := '0'; + SIGNAL nilill : STD_LOGIC := '0'; + SIGNAL nililO : STD_LOGIC := '0'; + SIGNAL niliOi : STD_LOGIC := '0'; + SIGNAL niliOl : STD_LOGIC := '0'; + SIGNAL niliOO : STD_LOGIC := '0'; + SIGNAL nill0i : STD_LOGIC := '0'; + SIGNAL nill0l : STD_LOGIC := '0'; + SIGNAL nill0O : STD_LOGIC := '0'; + SIGNAL nill1i : STD_LOGIC := '0'; + SIGNAL nill1l : STD_LOGIC := '0'; + SIGNAL nill1O : STD_LOGIC := '0'; + SIGNAL nillii : STD_LOGIC := '0'; + SIGNAL nillil : STD_LOGIC := '0'; + SIGNAL nilliO : STD_LOGIC := '0'; + SIGNAL nillli : STD_LOGIC := '0'; + SIGNAL nillll : STD_LOGIC := '0'; + SIGNAL nilllO : STD_LOGIC := '0'; + SIGNAL nillOi : STD_LOGIC := '0'; + SIGNAL nillOl : STD_LOGIC := '0'; + SIGNAL nillOO : STD_LOGIC := '0'; + SIGNAL nilO0i : STD_LOGIC := '0'; + SIGNAL nilO0l : STD_LOGIC := '0'; + SIGNAL nilO0O : STD_LOGIC := '0'; + SIGNAL nilO1i : STD_LOGIC := '0'; + SIGNAL nilO1l : STD_LOGIC := '0'; + SIGNAL nilO1O : STD_LOGIC := '0'; + SIGNAL nilOii : STD_LOGIC := '0'; + SIGNAL nilOil : STD_LOGIC := '0'; + SIGNAL nilOiO : STD_LOGIC := '0'; + SIGNAL nilOli : STD_LOGIC := '0'; + SIGNAL nilOll : STD_LOGIC := '0'; + SIGNAL nilOlO : STD_LOGIC := '0'; + SIGNAL nilOOi : STD_LOGIC := '0'; + SIGNAL nilOOl : STD_LOGIC := '0'; + SIGNAL nilOOO : STD_LOGIC := '0'; + SIGNAL niO00i : STD_LOGIC := '0'; + SIGNAL niO00l : STD_LOGIC := '0'; + SIGNAL niO00O : STD_LOGIC := '0'; + SIGNAL niO01i : STD_LOGIC := '0'; + SIGNAL niO01l : STD_LOGIC := '0'; + SIGNAL niO01O : STD_LOGIC := '0'; + SIGNAL niO0ii : STD_LOGIC := '0'; + SIGNAL niO0il : STD_LOGIC := '0'; + SIGNAL niO0iO : STD_LOGIC := '0'; + SIGNAL niO0li : STD_LOGIC := '0'; + SIGNAL niO0ll : STD_LOGIC := '0'; + SIGNAL niO0lO : STD_LOGIC := '0'; + SIGNAL niO0Oi : STD_LOGIC := '0'; + SIGNAL niO0Ol : STD_LOGIC := '0'; + SIGNAL niO0OO : STD_LOGIC := '0'; + SIGNAL niO10i : STD_LOGIC := '0'; + SIGNAL niO10l : STD_LOGIC := '0'; + SIGNAL niO10O : STD_LOGIC := '0'; + SIGNAL niO11i : STD_LOGIC := '0'; + SIGNAL niO11l : STD_LOGIC := '0'; + SIGNAL niO11O : STD_LOGIC := '0'; + SIGNAL niO1ii : STD_LOGIC := '0'; + SIGNAL niO1il : STD_LOGIC := '0'; + SIGNAL niO1iO : STD_LOGIC := '0'; + SIGNAL niO1li : STD_LOGIC := '0'; + SIGNAL niO1ll : STD_LOGIC := '0'; + SIGNAL niO1lO : STD_LOGIC := '0'; + SIGNAL niO1Oi : STD_LOGIC := '0'; + SIGNAL niO1Ol : STD_LOGIC := '0'; + SIGNAL niO1OO : STD_LOGIC := '0'; + SIGNAL niOi0i : STD_LOGIC := '0'; + SIGNAL niOi0l : STD_LOGIC := '0'; + SIGNAL niOi0O : STD_LOGIC := '0'; + SIGNAL niOi1i : STD_LOGIC := '0'; + SIGNAL niOi1l : STD_LOGIC := '0'; + SIGNAL niOi1O : STD_LOGIC := '0'; + SIGNAL niOiii : STD_LOGIC := '0'; + SIGNAL nl000i : STD_LOGIC := '0'; + SIGNAL nl000l : STD_LOGIC := '0'; + SIGNAL nl000O : STD_LOGIC := '0'; + SIGNAL nl001i : STD_LOGIC := '0'; + SIGNAL nl001l : STD_LOGIC := '0'; + SIGNAL nl001O : STD_LOGIC := '0'; + SIGNAL nl00ii : STD_LOGIC := '0'; + SIGNAL nl00il : STD_LOGIC := '0'; + SIGNAL nl00iO : STD_LOGIC := '0'; + SIGNAL nl00li : STD_LOGIC := '0'; + SIGNAL nl00ll : STD_LOGIC := '0'; + SIGNAL nl00lO : STD_LOGIC := '0'; + SIGNAL nl00Oi : STD_LOGIC := '0'; + SIGNAL nl00Ol : STD_LOGIC := '0'; + SIGNAL nl00OO : STD_LOGIC := '0'; + SIGNAL nl010i : STD_LOGIC := '0'; + SIGNAL nl01li : STD_LOGIC := '0'; + SIGNAL nl01ll : STD_LOGIC := '0'; + SIGNAL nl01lO : STD_LOGIC := '0'; + SIGNAL nl01Oi : STD_LOGIC := '0'; + SIGNAL nl01Ol : STD_LOGIC := '0'; + SIGNAL nl01OO : STD_LOGIC := '0'; + SIGNAL nl0i0i : STD_LOGIC := '0'; + SIGNAL nl0i0l : STD_LOGIC := '0'; + SIGNAL nl0i0O : STD_LOGIC := '0'; + SIGNAL nl0i1i : STD_LOGIC := '0'; + SIGNAL nl0i1l : STD_LOGIC := '0'; + SIGNAL nl0i1O : STD_LOGIC := '0'; + SIGNAL nl0iii : STD_LOGIC := '0'; + SIGNAL nl0iil : STD_LOGIC := '0'; + SIGNAL nl0iiO : STD_LOGIC := '0'; + SIGNAL nl0ili : STD_LOGIC := '0'; + SIGNAL nl0ill : STD_LOGIC := '0'; + SIGNAL nl0ilO : STD_LOGIC := '0'; + SIGNAL nl0iOi : STD_LOGIC := '0'; + SIGNAL nl0iOl : STD_LOGIC := '0'; + SIGNAL nl0iOO : STD_LOGIC := '0'; + SIGNAL nl0l0i : STD_LOGIC := '0'; + SIGNAL nl0l0l : STD_LOGIC := '0'; + SIGNAL nl0l0O : STD_LOGIC := '0'; + SIGNAL nl0l1i : STD_LOGIC := '0'; + SIGNAL nl0l1l : STD_LOGIC := '0'; + SIGNAL nl0l1O : STD_LOGIC := '0'; + SIGNAL nl0lii : STD_LOGIC := '0'; + SIGNAL nl0lil : STD_LOGIC := '0'; + SIGNAL nl0liO : STD_LOGIC := '0'; + SIGNAL nl0lli : STD_LOGIC := '0'; + SIGNAL nl0lll : STD_LOGIC := '0'; + SIGNAL nl0llO : STD_LOGIC := '0'; + SIGNAL nl0lOi : STD_LOGIC := '0'; + SIGNAL nl0lOl : STD_LOGIC := '0'; + SIGNAL nl0lOO : STD_LOGIC := '0'; + SIGNAL nl0O0i : STD_LOGIC := '0'; + SIGNAL nl0O0l : STD_LOGIC := '0'; + SIGNAL nl0O0O : STD_LOGIC := '0'; + SIGNAL nl0O1i : STD_LOGIC := '0'; + SIGNAL nl0O1l : STD_LOGIC := '0'; + SIGNAL nl0O1O : STD_LOGIC := '0'; + SIGNAL nl0Oii : STD_LOGIC := '0'; + SIGNAL nl0Oil : STD_LOGIC := '0'; + SIGNAL nl0OiO : STD_LOGIC := '0'; + SIGNAL nl0Oli : STD_LOGIC := '0'; + SIGNAL nl0Oll : STD_LOGIC := '0'; + SIGNAL nl0OlO : STD_LOGIC := '0'; + SIGNAL nl0OOi : STD_LOGIC := '0'; + SIGNAL nl0OOl : STD_LOGIC := '0'; + SIGNAL nl0OOO : STD_LOGIC := '0'; + SIGNAL nli10i : STD_LOGIC := '0'; + SIGNAL nli10l : STD_LOGIC := '0'; + SIGNAL nli10O : STD_LOGIC := '0'; + SIGNAL nli11i : STD_LOGIC := '0'; + SIGNAL nli11l : STD_LOGIC := '0'; + SIGNAL nli11O : STD_LOGIC := '0'; + SIGNAL nli1il : STD_LOGIC := '0'; + SIGNAL nlO1i1O : STD_LOGIC := '0'; + SIGNAL wire_nli1ii_PRN : STD_LOGIC; + SIGNAL wire_nli1ii_w_lg_niiO0l6511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii_w_lg_niiO0O6509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii_w_lg_niiOii3801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii_w_lg_niiOil6507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii_w_lg_niOi0i600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii_w_lg_niOi0l676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii_w_lg_nl01Oi645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii_w_lg_nlO1i1O604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO1l : STD_LOGIC := '0'; + SIGNAL nlllOO : STD_LOGIC := '0'; + SIGNAL nllO0i : STD_LOGIC := '0'; + SIGNAL nllO0l : STD_LOGIC := '0'; + SIGNAL nllO0O : STD_LOGIC := '0'; + SIGNAL nllO1i : STD_LOGIC := '0'; + SIGNAL nllO1l : STD_LOGIC := '0'; + SIGNAL nllO1O : STD_LOGIC := '0'; + SIGNAL nllOii : STD_LOGIC := '0'; + SIGNAL nllOil : STD_LOGIC := '0'; + SIGNAL nllOiO : STD_LOGIC := '0'; + SIGNAL nllOli : STD_LOGIC := '0'; + SIGNAL nllOll : STD_LOGIC := '0'; + SIGNAL nllOlO : STD_LOGIC := '0'; + SIGNAL nllOOi : STD_LOGIC := '0'; + SIGNAL nllOOl : STD_LOGIC := '0'; + SIGNAL nllOOO : STD_LOGIC := '0'; + SIGNAL nlO01l : STD_LOGIC := '0'; + SIGNAL nlO10i : STD_LOGIC := '0'; + SIGNAL nlO10l : STD_LOGIC := '0'; + SIGNAL nlO10O : STD_LOGIC := '0'; + SIGNAL nlO11i : STD_LOGIC := '0'; + SIGNAL nlO11l : STD_LOGIC := '0'; + SIGNAL nlO11O : STD_LOGIC := '0'; + SIGNAL nlO1ii : STD_LOGIC := '0'; + SIGNAL nlO1il : STD_LOGIC := '0'; + SIGNAL nlO1iO : STD_LOGIC := '0'; + SIGNAL nlO1li : STD_LOGIC := '0'; + SIGNAL nlO1ll : STD_LOGIC := '0'; + SIGNAL nlO1lO : STD_LOGIC := '0'; + SIGNAL nlO1Oi : STD_LOGIC := '0'; + SIGNAL nlO1Ol : STD_LOGIC := '0'; + SIGNAL nlO1OO : STD_LOGIC := '0'; + SIGNAL wire_nlO01i_CLRN : STD_LOGIC; + SIGNAL wire_nlO01i_PRN : STD_LOGIC; + SIGNAL nlO1i1l : STD_LOGIC := '0'; + SIGNAL wire_nlO1i1i_CLRN : STD_LOGIC; + SIGNAL wire_nlO1i1i_PRN : STD_LOGIC; + SIGNAL wire_nlO1i1i_w_lg_nlO1i1l613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO1O : STD_LOGIC := '0'; + SIGNAL nlO00i : STD_LOGIC := '0'; + SIGNAL nlO00l : STD_LOGIC := '0'; + SIGNAL nlO00O : STD_LOGIC := '0'; + SIGNAL nlO01O : STD_LOGIC := '0'; + SIGNAL nlO0ii : STD_LOGIC := '0'; + SIGNAL nlO0il : STD_LOGIC := '0'; + SIGNAL nlO0iO : STD_LOGIC := '0'; + SIGNAL nlO0li : STD_LOGIC := '0'; + SIGNAL nlO0ll : STD_LOGIC := '0'; + SIGNAL nlO0lO : STD_LOGIC := '0'; + SIGNAL nlO0Oi : STD_LOGIC := '0'; + SIGNAL nlO0Ol : STD_LOGIC := '0'; + SIGNAL nlO0OO : STD_LOGIC := '0'; + SIGNAL nlOi0i : STD_LOGIC := '0'; + SIGNAL nlOi0l : STD_LOGIC := '0'; + SIGNAL nlOi0O : STD_LOGIC := '0'; + SIGNAL nlOi1i : STD_LOGIC := '0'; + SIGNAL nlOi1l : STD_LOGIC := '0'; + SIGNAL nlOi1O : STD_LOGIC := '0'; + SIGNAL nlOiii : STD_LOGIC := '0'; + SIGNAL nlOiil : STD_LOGIC := '0'; + SIGNAL nlOiiO : STD_LOGIC := '0'; + SIGNAL nlOili : STD_LOGIC := '0'; + SIGNAL nlOill : STD_LOGIC := '0'; + SIGNAL nlOilO : STD_LOGIC := '0'; + SIGNAL nlOiOi : STD_LOGIC := '0'; + SIGNAL nlOiOl : STD_LOGIC := '0'; + SIGNAL nlOiOO : STD_LOGIC := '0'; + SIGNAL nlOl0l : STD_LOGIC := '0'; + SIGNAL nlOl1i : STD_LOGIC := '0'; + SIGNAL nlOl1l : STD_LOGIC := '0'; + SIGNAL nlOl1O : STD_LOGIC := '0'; + SIGNAL wire_n0000i_dataout : STD_LOGIC; + SIGNAL wire_n0000l_dataout : STD_LOGIC; + SIGNAL wire_n0000O_dataout : STD_LOGIC; + SIGNAL wire_n0001i_dataout : STD_LOGIC; + SIGNAL wire_n0001l_dataout : STD_LOGIC; + SIGNAL wire_n0001O_dataout : STD_LOGIC; + SIGNAL wire_n000i_dataout : STD_LOGIC; + SIGNAL wire_n000ii_dataout : STD_LOGIC; + SIGNAL wire_n000il_dataout : STD_LOGIC; + SIGNAL wire_n000iO_dataout : STD_LOGIC; + SIGNAL wire_n000l_dataout : STD_LOGIC; + SIGNAL wire_n000li_dataout : STD_LOGIC; + SIGNAL wire_n000ll_dataout : STD_LOGIC; + SIGNAL wire_n000lO_dataout : STD_LOGIC; + SIGNAL wire_n000O_dataout : STD_LOGIC; + SIGNAL wire_n000Oi_dataout : STD_LOGIC; + SIGNAL wire_n000Ol_dataout : STD_LOGIC; + SIGNAL wire_n000OO_dataout : STD_LOGIC; + SIGNAL wire_n0010i_dataout : STD_LOGIC; + SIGNAL wire_n0010l_dataout : STD_LOGIC; + SIGNAL wire_n0010O_dataout : STD_LOGIC; + SIGNAL wire_n0011i_dataout : STD_LOGIC; + SIGNAL wire_n0011l_dataout : STD_LOGIC; + SIGNAL wire_n0011O_dataout : STD_LOGIC; + SIGNAL wire_n001ii_dataout : STD_LOGIC; + SIGNAL wire_n001il_dataout : STD_LOGIC; + SIGNAL wire_n001iO_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001li_dataout : STD_LOGIC; + SIGNAL wire_n001ll_dataout : STD_LOGIC; + SIGNAL wire_n001lO_dataout : STD_LOGIC; + SIGNAL wire_n001Oi_dataout : STD_LOGIC; + SIGNAL wire_n001Ol_dataout : STD_LOGIC; + SIGNAL wire_n001OO_dataout : STD_LOGIC; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00i0i_dataout : STD_LOGIC; + SIGNAL wire_n00i0l_dataout : STD_LOGIC; + SIGNAL wire_n00i0O_dataout : STD_LOGIC; + SIGNAL wire_n00i1i_dataout : STD_LOGIC; + SIGNAL wire_n00i1l_dataout : STD_LOGIC; + SIGNAL wire_n00i1O_dataout : STD_LOGIC; + SIGNAL wire_n00ii_dataout : STD_LOGIC; + SIGNAL wire_n00iii_dataout : STD_LOGIC; + SIGNAL wire_n00iil_dataout : STD_LOGIC; + SIGNAL wire_n00iiO_dataout : STD_LOGIC; + SIGNAL wire_n00il_dataout : STD_LOGIC; + SIGNAL wire_n00ili_dataout : STD_LOGIC; + SIGNAL wire_n00ill_dataout : STD_LOGIC; + SIGNAL wire_n00ilO_dataout : STD_LOGIC; + SIGNAL wire_n00iO_dataout : STD_LOGIC; + SIGNAL wire_n00iOi_dataout : STD_LOGIC; + SIGNAL wire_n00iOl_dataout : STD_LOGIC; + SIGNAL wire_n00iOO_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00l0i_dataout : STD_LOGIC; + SIGNAL wire_n00l0l_dataout : STD_LOGIC; + SIGNAL wire_n00l0O_dataout : STD_LOGIC; + SIGNAL wire_n00l1i_dataout : STD_LOGIC; + SIGNAL wire_n00l1l_dataout : STD_LOGIC; + SIGNAL wire_n00l1O_dataout : STD_LOGIC; + SIGNAL wire_n00li_dataout : STD_LOGIC; + SIGNAL wire_n00lii_dataout : STD_LOGIC; + SIGNAL wire_n00lil_dataout : STD_LOGIC; + SIGNAL wire_n00liO_dataout : STD_LOGIC; + SIGNAL wire_n00ll_dataout : STD_LOGIC; + SIGNAL wire_n00lli_dataout : STD_LOGIC; + SIGNAL wire_n00lll_dataout : STD_LOGIC; + SIGNAL wire_n00llO_dataout : STD_LOGIC; + SIGNAL wire_n00lO_dataout : STD_LOGIC; + SIGNAL wire_n00lOi_dataout : STD_LOGIC; + SIGNAL wire_n00lOl_dataout : STD_LOGIC; + SIGNAL wire_n00lOO_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n0100i_dataout : STD_LOGIC; + SIGNAL wire_n0100l_dataout : STD_LOGIC; + SIGNAL wire_n0100O_dataout : STD_LOGIC; + SIGNAL wire_n0101i_dataout : STD_LOGIC; + SIGNAL wire_n0101l_dataout : STD_LOGIC; + SIGNAL wire_n0101O_dataout : STD_LOGIC; + SIGNAL wire_n010i_dataout : STD_LOGIC; + SIGNAL wire_n010ii_dataout : STD_LOGIC; + SIGNAL wire_n010il_dataout : STD_LOGIC; + SIGNAL wire_n010iO_dataout : STD_LOGIC; + SIGNAL wire_n010l_dataout : STD_LOGIC; + SIGNAL wire_n010li_dataout : STD_LOGIC; + SIGNAL wire_n010ll_dataout : STD_LOGIC; + SIGNAL wire_n010lO_dataout : STD_LOGIC; + SIGNAL wire_n010O_dataout : STD_LOGIC; + SIGNAL wire_n010Oi_dataout : STD_LOGIC; + SIGNAL wire_n010Ol_dataout : STD_LOGIC; + SIGNAL wire_n010OO_dataout : STD_LOGIC; + SIGNAL wire_n0110i_dataout : STD_LOGIC; + SIGNAL wire_n0110l_dataout : STD_LOGIC; + SIGNAL wire_n0110O_dataout : STD_LOGIC; + SIGNAL wire_n0111i_dataout : STD_LOGIC; + SIGNAL wire_n0111l_dataout : STD_LOGIC; + SIGNAL wire_n0111O_dataout : STD_LOGIC; + SIGNAL wire_n011i_dataout : STD_LOGIC; + SIGNAL wire_n011ii_dataout : STD_LOGIC; + SIGNAL wire_n011il_dataout : STD_LOGIC; + SIGNAL wire_n011iO_dataout : STD_LOGIC; + SIGNAL wire_n011l_dataout : STD_LOGIC; + SIGNAL wire_n011li_dataout : STD_LOGIC; + SIGNAL wire_n011ll_dataout : STD_LOGIC; + SIGNAL wire_n011lO_dataout : STD_LOGIC; + SIGNAL wire_n011O_dataout : STD_LOGIC; + SIGNAL wire_n011Oi_dataout : STD_LOGIC; + SIGNAL wire_n011Ol_dataout : STD_LOGIC; + SIGNAL wire_n011OO_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01i0i_dataout : STD_LOGIC; + SIGNAL wire_n01i0l_dataout : STD_LOGIC; + SIGNAL wire_n01i0O_dataout : STD_LOGIC; + SIGNAL wire_n01i1i_dataout : STD_LOGIC; + SIGNAL wire_n01i1l_dataout : STD_LOGIC; + SIGNAL wire_n01i1O_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01iii_dataout : STD_LOGIC; + SIGNAL wire_n01iil_dataout : STD_LOGIC; + SIGNAL wire_n01iiO_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01ili_dataout : STD_LOGIC; + SIGNAL wire_n01ill_dataout : STD_LOGIC; + SIGNAL wire_n01ilO_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01iOi_dataout : STD_LOGIC; + SIGNAL wire_n01iOl_dataout : STD_LOGIC; + SIGNAL wire_n01iOO_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01l0i_dataout : STD_LOGIC; + SIGNAL wire_n01l0l_dataout : STD_LOGIC; + SIGNAL wire_n01l0O_dataout : STD_LOGIC; + SIGNAL wire_n01l1i_dataout : STD_LOGIC; + SIGNAL wire_n01l1l_dataout : STD_LOGIC; + SIGNAL wire_n01l1O_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01lii_dataout : STD_LOGIC; + SIGNAL wire_n01lil_dataout : STD_LOGIC; + SIGNAL wire_n01liO_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01lli_dataout : STD_LOGIC; + SIGNAL wire_n01lll_dataout : STD_LOGIC; + SIGNAL wire_n01llO_dataout : STD_LOGIC; + SIGNAL wire_n01lO_dataout : STD_LOGIC; + SIGNAL wire_n01lOi_dataout : STD_LOGIC; + SIGNAL wire_n01lOl_dataout : STD_LOGIC; + SIGNAL wire_n01lOO_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n01O0i_dataout : STD_LOGIC; + SIGNAL wire_n01O0l_dataout : STD_LOGIC; + SIGNAL wire_n01O0O_dataout : STD_LOGIC; + SIGNAL wire_n01O1i_dataout : STD_LOGIC; + SIGNAL wire_n01O1l_dataout : STD_LOGIC; + SIGNAL wire_n01O1O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Oii_dataout : STD_LOGIC; + SIGNAL wire_n01Oil_dataout : STD_LOGIC; + SIGNAL wire_n01OiO_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01Oli_dataout : STD_LOGIC; + SIGNAL wire_n01Oll_dataout : STD_LOGIC; + SIGNAL wire_n01OlO_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n01OOi_dataout : STD_LOGIC; + SIGNAL wire_n01OOl_dataout : STD_LOGIC; + SIGNAL wire_n01OOO_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0iii_dataout : STD_LOGIC; + SIGNAL wire_n0iil_dataout : STD_LOGIC; + SIGNAL wire_n0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0il0l_dataout : STD_LOGIC; + SIGNAL wire_n0il0O_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ilii_dataout : STD_LOGIC; + SIGNAL wire_n0ilil_dataout : STD_LOGIC; + SIGNAL wire_n0iliO_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0illi_dataout : STD_LOGIC; + SIGNAL wire_n0illl_dataout : STD_LOGIC; + SIGNAL wire_n0illO_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOi_dataout : STD_LOGIC; + SIGNAL wire_n0ilOl_dataout : STD_LOGIC; + SIGNAL wire_n0ilOO_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0iO0i_dataout : STD_LOGIC; + SIGNAL wire_n0iO0l_dataout : STD_LOGIC; + SIGNAL wire_n0iO1i_dataout : STD_LOGIC; + SIGNAL wire_n0iO1l_dataout : STD_LOGIC; + SIGNAL wire_n0iO1O_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOii_dataout : STD_LOGIC; + SIGNAL wire_n0iOil_dataout : STD_LOGIC; + SIGNAL wire_n0iOiO_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOli_dataout : STD_LOGIC; + SIGNAL wire_n0iOll_dataout : STD_LOGIC; + SIGNAL wire_n0iOlO_dataout : STD_LOGIC; + SIGNAL wire_n0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOOO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0l00i_dataout : STD_LOGIC; + SIGNAL wire_n0l00O_dataout : STD_LOGIC; + SIGNAL wire_n0l01i_dataout : STD_LOGIC; + SIGNAL wire_n0l01l_dataout : STD_LOGIC; + SIGNAL wire_n0l01O_dataout : STD_LOGIC; + SIGNAL wire_n0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0ii_dataout : STD_LOGIC; + SIGNAL wire_n0l0il_dataout : STD_LOGIC; + SIGNAL wire_n0l0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0li_dataout : STD_LOGIC; + SIGNAL wire_n0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l10i_dataout : STD_LOGIC; + SIGNAL wire_n0l10l_dataout : STD_LOGIC; + SIGNAL wire_n0l10O_dataout : STD_LOGIC; + SIGNAL wire_n0l11i_dataout : STD_LOGIC; + SIGNAL wire_n0l11O_dataout : STD_LOGIC; + SIGNAL wire_n0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1li_dataout : STD_LOGIC; + SIGNAL wire_n0l1ll_dataout : STD_LOGIC; + SIGNAL wire_n0l1lO_dataout : STD_LOGIC; + SIGNAL wire_n0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l1OO_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0li0i_dataout : STD_LOGIC; + SIGNAL wire_n0li0l_dataout : STD_LOGIC; + SIGNAL wire_n0li0O_dataout : STD_LOGIC; + SIGNAL wire_n0li1i_dataout : STD_LOGIC; + SIGNAL wire_n0li1l_dataout : STD_LOGIC; + SIGNAL wire_n0li1O_dataout : STD_LOGIC; + SIGNAL wire_n0lii_dataout : STD_LOGIC; + SIGNAL wire_n0liii_dataout : STD_LOGIC; + SIGNAL wire_n0liil_dataout : STD_LOGIC; + SIGNAL wire_n0liiO_dataout : STD_LOGIC; + SIGNAL wire_n0lili_dataout : STD_LOGIC; + SIGNAL wire_n0lill_dataout : STD_LOGIC; + SIGNAL wire_n0lilO_dataout : STD_LOGIC; + SIGNAL wire_n0liOi_dataout : STD_LOGIC; + SIGNAL wire_n0liOl_dataout : STD_LOGIC; + SIGNAL wire_n0liOO_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i_dataout : STD_LOGIC; + SIGNAL wire_n0ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0ll1i_dataout : STD_LOGIC; + SIGNAL wire_n0ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0lli_dataout : STD_LOGIC; + SIGNAL wire_n0llii_dataout : STD_LOGIC; + SIGNAL wire_n0llil_dataout : STD_LOGIC; + SIGNAL wire_n0lliO_dataout : STD_LOGIC; + SIGNAL wire_n0lll_dataout : STD_LOGIC; + SIGNAL wire_n0llli_dataout : STD_LOGIC; + SIGNAL wire_n0llll_dataout : STD_LOGIC; + SIGNAL wire_n0lllO_dataout : STD_LOGIC; + SIGNAL wire_n0llO_dataout : STD_LOGIC; + SIGNAL wire_n0llOi_dataout : STD_LOGIC; + SIGNAL wire_n0llOl_dataout : STD_LOGIC; + SIGNAL wire_n0llOO_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOii_dataout : STD_LOGIC; + SIGNAL wire_n0lOil_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOli_dataout : STD_LOGIC; + SIGNAL wire_n0lOll_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0O01i_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O10i_dataout : STD_LOGIC; + SIGNAL wire_n0O10l_dataout : STD_LOGIC; + SIGNAL wire_n0O10O_dataout : STD_LOGIC; + SIGNAL wire_n0O11i_dataout : STD_LOGIC; + SIGNAL wire_n0O11l_dataout : STD_LOGIC; + SIGNAL wire_n0O11O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii_dataout : STD_LOGIC; + SIGNAL wire_n0O1il_dataout : STD_LOGIC; + SIGNAL wire_n0O1iO_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1li_dataout : STD_LOGIC; + SIGNAL wire_n0O1ll_dataout : STD_LOGIC; + SIGNAL wire_n0O1lO_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1000i_dataout : STD_LOGIC; + SIGNAL wire_n1000l_dataout : STD_LOGIC; + SIGNAL wire_n1000O_dataout : STD_LOGIC; + SIGNAL wire_n1001i_dataout : STD_LOGIC; + SIGNAL wire_n1001l_dataout : STD_LOGIC; + SIGNAL wire_n1001O_dataout : STD_LOGIC; + SIGNAL wire_n100ii_dataout : STD_LOGIC; + SIGNAL wire_n100il_dataout : STD_LOGIC; + SIGNAL wire_n100iO_dataout : STD_LOGIC; + SIGNAL wire_n100li_dataout : STD_LOGIC; + SIGNAL wire_n100ll_dataout : STD_LOGIC; + SIGNAL wire_n100lO_dataout : STD_LOGIC; + SIGNAL wire_n100Oi_dataout : STD_LOGIC; + SIGNAL wire_n100Ol_dataout : STD_LOGIC; + SIGNAL wire_n100OO_dataout : STD_LOGIC; + SIGNAL wire_n1010i_dataout : STD_LOGIC; + SIGNAL wire_n1010l_dataout : STD_LOGIC; + SIGNAL wire_n1010O_dataout : STD_LOGIC; + SIGNAL wire_n1011i_dataout : STD_LOGIC; + SIGNAL wire_n1011l_dataout : STD_LOGIC; + SIGNAL wire_n1011O_dataout : STD_LOGIC; + SIGNAL wire_n101ii_dataout : STD_LOGIC; + SIGNAL wire_n101il_dataout : STD_LOGIC; + SIGNAL wire_n101iO_dataout : STD_LOGIC; + SIGNAL wire_n101li_dataout : STD_LOGIC; + SIGNAL wire_n101ll_dataout : STD_LOGIC; + SIGNAL wire_n101lO_dataout : STD_LOGIC; + SIGNAL wire_n101Oi_dataout : STD_LOGIC; + SIGNAL wire_n101Ol_dataout : STD_LOGIC; + SIGNAL wire_n101OO_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10i0i_dataout : STD_LOGIC; + SIGNAL wire_n10i0l_dataout : STD_LOGIC; + SIGNAL wire_n10i0O_dataout : STD_LOGIC; + SIGNAL wire_n10i1i_dataout : STD_LOGIC; + SIGNAL wire_n10i1l_dataout : STD_LOGIC; + SIGNAL wire_n10i1O_dataout : STD_LOGIC; + SIGNAL wire_n10iii_dataout : STD_LOGIC; + SIGNAL wire_n10iil_dataout : STD_LOGIC; + SIGNAL wire_n10iiO_dataout : STD_LOGIC; + SIGNAL wire_n10ili_dataout : STD_LOGIC; + SIGNAL wire_n10ill_dataout : STD_LOGIC; + SIGNAL wire_n10ilO_dataout : STD_LOGIC; + SIGNAL wire_n10iOi_dataout : STD_LOGIC; + SIGNAL wire_n10iOl_dataout : STD_LOGIC; + SIGNAL wire_n10iOO_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10l0i_dataout : STD_LOGIC; + SIGNAL wire_n10l0l_dataout : STD_LOGIC; + SIGNAL wire_n10l0O_dataout : STD_LOGIC; + SIGNAL wire_n10l1i_dataout : STD_LOGIC; + SIGNAL wire_n10l1l_dataout : STD_LOGIC; + SIGNAL wire_n10l1O_dataout : STD_LOGIC; + SIGNAL wire_n10lii_dataout : STD_LOGIC; + SIGNAL wire_n10lil_dataout : STD_LOGIC; + SIGNAL wire_n10liO_dataout : STD_LOGIC; + SIGNAL wire_n10lli_dataout : STD_LOGIC; + SIGNAL wire_n10lll_dataout : STD_LOGIC; + SIGNAL wire_n10llO_dataout : STD_LOGIC; + SIGNAL wire_n10lOi_dataout : STD_LOGIC; + SIGNAL wire_n10lOl_dataout : STD_LOGIC; + SIGNAL wire_n10lOO_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n10O0i_dataout : STD_LOGIC; + SIGNAL wire_n10O0l_dataout : STD_LOGIC; + SIGNAL wire_n10O0O_dataout : STD_LOGIC; + SIGNAL wire_n10O1i_dataout : STD_LOGIC; + SIGNAL wire_n10O1l_dataout : STD_LOGIC; + SIGNAL wire_n10O1O_dataout : STD_LOGIC; + SIGNAL wire_n10Oii_dataout : STD_LOGIC; + SIGNAL wire_n10Oil_dataout : STD_LOGIC; + SIGNAL wire_n10OiO_dataout : STD_LOGIC; + SIGNAL wire_n10Ol_dataout : STD_LOGIC; + SIGNAL wire_n10Oli_dataout : STD_LOGIC; + SIGNAL wire_n10Oll_dataout : STD_LOGIC; + SIGNAL wire_n10OlO_dataout : STD_LOGIC; + SIGNAL wire_n10OOi_dataout : STD_LOGIC; + SIGNAL wire_n10OOl_dataout : STD_LOGIC; + SIGNAL wire_n10OOO_dataout : STD_LOGIC; + SIGNAL wire_n1100i_dataout : STD_LOGIC; + SIGNAL wire_n1100l_dataout : STD_LOGIC; + SIGNAL wire_n1100O_dataout : STD_LOGIC; + SIGNAL wire_n1101i_dataout : STD_LOGIC; + SIGNAL wire_n1101l_dataout : STD_LOGIC; + SIGNAL wire_n1101O_dataout : STD_LOGIC; + SIGNAL wire_n110i_dataout : STD_LOGIC; + SIGNAL wire_n110ii_dataout : STD_LOGIC; + SIGNAL wire_n110il_dataout : STD_LOGIC; + SIGNAL wire_n110iO_dataout : STD_LOGIC; + SIGNAL wire_n110l_dataout : STD_LOGIC; + SIGNAL wire_n110li_dataout : STD_LOGIC; + SIGNAL wire_n110ll_dataout : STD_LOGIC; + SIGNAL wire_n110lO_dataout : STD_LOGIC; + SIGNAL wire_n110O_dataout : STD_LOGIC; + SIGNAL wire_n110Oi_dataout : STD_LOGIC; + SIGNAL wire_n110Ol_dataout : STD_LOGIC; + SIGNAL wire_n110OO_dataout : STD_LOGIC; + SIGNAL wire_n1110i_dataout : STD_LOGIC; + SIGNAL wire_n1110l_dataout : STD_LOGIC; + SIGNAL wire_n1110O_dataout : STD_LOGIC; + SIGNAL wire_n1111i_dataout : STD_LOGIC; + SIGNAL wire_n1111l_dataout : STD_LOGIC; + SIGNAL wire_n1111O_dataout : STD_LOGIC; + SIGNAL wire_n111i_dataout : STD_LOGIC; + SIGNAL wire_n111ii_dataout : STD_LOGIC; + SIGNAL wire_n111il_dataout : STD_LOGIC; + SIGNAL wire_n111iO_dataout : STD_LOGIC; + SIGNAL wire_n111l_dataout : STD_LOGIC; + SIGNAL wire_n111li_dataout : STD_LOGIC; + SIGNAL wire_n111ll_dataout : STD_LOGIC; + SIGNAL wire_n111lO_dataout : STD_LOGIC; + SIGNAL wire_n111O_dataout : STD_LOGIC; + SIGNAL wire_n111Oi_dataout : STD_LOGIC; + SIGNAL wire_n111Ol_dataout : STD_LOGIC; + SIGNAL wire_n111OO_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11i0i_dataout : STD_LOGIC; + SIGNAL wire_n11i0l_dataout : STD_LOGIC; + SIGNAL wire_n11i0O_dataout : STD_LOGIC; + SIGNAL wire_n11i1i_dataout : STD_LOGIC; + SIGNAL wire_n11i1l_dataout : STD_LOGIC; + SIGNAL wire_n11i1O_dataout : STD_LOGIC; + SIGNAL wire_n11ii_dataout : STD_LOGIC; + SIGNAL wire_n11iii_dataout : STD_LOGIC; + SIGNAL wire_n11iil_dataout : STD_LOGIC; + SIGNAL wire_n11iiO_dataout : STD_LOGIC; + SIGNAL wire_n11il_dataout : STD_LOGIC; + SIGNAL wire_n11ili_dataout : STD_LOGIC; + SIGNAL wire_n11ill_dataout : STD_LOGIC; + SIGNAL wire_n11ilO_dataout : STD_LOGIC; + SIGNAL wire_n11iO_dataout : STD_LOGIC; + SIGNAL wire_n11iOi_dataout : STD_LOGIC; + SIGNAL wire_n11iOl_dataout : STD_LOGIC; + SIGNAL wire_n11iOO_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11l0i_dataout : STD_LOGIC; + SIGNAL wire_n11l0l_dataout : STD_LOGIC; + SIGNAL wire_n11l0O_dataout : STD_LOGIC; + SIGNAL wire_n11l1i_dataout : STD_LOGIC; + SIGNAL wire_n11l1l_dataout : STD_LOGIC; + SIGNAL wire_n11l1O_dataout : STD_LOGIC; + SIGNAL wire_n11lii_dataout : STD_LOGIC; + SIGNAL wire_n11lil_dataout : STD_LOGIC; + SIGNAL wire_n11liO_dataout : STD_LOGIC; + SIGNAL wire_n11lli_dataout : STD_LOGIC; + SIGNAL wire_n11lll_dataout : STD_LOGIC; + SIGNAL wire_n11llO_dataout : STD_LOGIC; + SIGNAL wire_n11lOi_dataout : STD_LOGIC; + SIGNAL wire_n11lOl_dataout : STD_LOGIC; + SIGNAL wire_n11lOO_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n11O0i_dataout : STD_LOGIC; + SIGNAL wire_n11O0l_dataout : STD_LOGIC; + SIGNAL wire_n11O0O_dataout : STD_LOGIC; + SIGNAL wire_n11O1i_dataout : STD_LOGIC; + SIGNAL wire_n11O1l_dataout : STD_LOGIC; + SIGNAL wire_n11O1O_dataout : STD_LOGIC; + SIGNAL wire_n11Oii_dataout : STD_LOGIC; + SIGNAL wire_n11Oil_dataout : STD_LOGIC; + SIGNAL wire_n11OiO_dataout : STD_LOGIC; + SIGNAL wire_n11Oli_dataout : STD_LOGIC; + SIGNAL wire_n11Oll_dataout : STD_LOGIC; + SIGNAL wire_n11OlO_dataout : STD_LOGIC; + SIGNAL wire_n11OOi_dataout : STD_LOGIC; + SIGNAL wire_n11OOl_dataout : STD_LOGIC; + SIGNAL wire_n11OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1i00i_dataout : STD_LOGIC; + SIGNAL wire_n1i00l_dataout : STD_LOGIC; + SIGNAL wire_n1i00O_dataout : STD_LOGIC; + SIGNAL wire_n1i01i_dataout : STD_LOGIC; + SIGNAL wire_n1i01l_dataout : STD_LOGIC; + SIGNAL wire_n1i01O_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii_dataout : STD_LOGIC; + SIGNAL wire_n1i0il_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO_dataout : STD_LOGIC; + SIGNAL wire_n1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0li_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO_dataout : STD_LOGIC; + SIGNAL wire_n1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i10i_dataout : STD_LOGIC; + SIGNAL wire_n1i10l_dataout : STD_LOGIC; + SIGNAL wire_n1i10O_dataout : STD_LOGIC; + SIGNAL wire_n1i11i_dataout : STD_LOGIC; + SIGNAL wire_n1i11l_dataout : STD_LOGIC; + SIGNAL wire_n1i11O_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1il_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1li_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1ii1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O_dataout : STD_LOGIC; + SIGNAL wire_n1iiii_dataout : STD_LOGIC; + SIGNAL wire_n1iiil_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iili_dataout : STD_LOGIC; + SIGNAL wire_n1iill_dataout : STD_LOGIC; + SIGNAL wire_n1iilO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1il0i_dataout : STD_LOGIC; + SIGNAL wire_n1il0l_dataout : STD_LOGIC; + SIGNAL wire_n1il0O_dataout : STD_LOGIC; + SIGNAL wire_n1il1i_dataout : STD_LOGIC; + SIGNAL wire_n1il1l_dataout : STD_LOGIC; + SIGNAL wire_n1il1O_dataout : STD_LOGIC; + SIGNAL wire_n1ilii_dataout : STD_LOGIC; + SIGNAL wire_n1ilil_dataout : STD_LOGIC; + SIGNAL wire_n1iliO_dataout : STD_LOGIC; + SIGNAL wire_n1illi_dataout : STD_LOGIC; + SIGNAL wire_n1illl_dataout : STD_LOGIC; + SIGNAL wire_n1illO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOii_dataout : STD_LOGIC; + SIGNAL wire_n1iOil_dataout : STD_LOGIC; + SIGNAL wire_n1iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOli_dataout : STD_LOGIC; + SIGNAL wire_n1iOll_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1l00i_dataout : STD_LOGIC; + SIGNAL wire_n1l00l_dataout : STD_LOGIC; + SIGNAL wire_n1l00O_dataout : STD_LOGIC; + SIGNAL wire_n1l01i_dataout : STD_LOGIC; + SIGNAL wire_n1l01l_dataout : STD_LOGIC; + SIGNAL wire_n1l01O_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n1l0il_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n1l0li_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l0lO_dataout : STD_LOGIC; + SIGNAL wire_n1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO_dataout : STD_LOGIC; + SIGNAL wire_n1l10i_dataout : STD_LOGIC; + SIGNAL wire_n1l10l_dataout : STD_LOGIC; + SIGNAL wire_n1l10O_dataout : STD_LOGIC; + SIGNAL wire_n1l11i_dataout : STD_LOGIC; + SIGNAL wire_n1l11l_dataout : STD_LOGIC; + SIGNAL wire_n1l11O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1l1il_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1li_dataout : STD_LOGIC; + SIGNAL wire_n1l1ll_dataout : STD_LOGIC; + SIGNAL wire_n1l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l1OO_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1li0i_dataout : STD_LOGIC; + SIGNAL wire_n1li0l_dataout : STD_LOGIC; + SIGNAL wire_n1li0O_dataout : STD_LOGIC; + SIGNAL wire_n1li1i_dataout : STD_LOGIC; + SIGNAL wire_n1li1l_dataout : STD_LOGIC; + SIGNAL wire_n1li1O_dataout : STD_LOGIC; + SIGNAL wire_n1lii_dataout : STD_LOGIC; + SIGNAL wire_n1liii_dataout : STD_LOGIC; + SIGNAL wire_n1liil_dataout : STD_LOGIC; + SIGNAL wire_n1liiO_dataout : STD_LOGIC; + SIGNAL wire_n1lili_dataout : STD_LOGIC; + SIGNAL wire_n1lill_dataout : STD_LOGIC; + SIGNAL wire_n1lilO_dataout : STD_LOGIC; + SIGNAL wire_n1liO_dataout : STD_LOGIC; + SIGNAL wire_n1liOi_dataout : STD_LOGIC; + SIGNAL wire_n1liOl_dataout : STD_LOGIC; + SIGNAL wire_n1liOO_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1ll0i_dataout : STD_LOGIC; + SIGNAL wire_n1ll0l_dataout : STD_LOGIC; + SIGNAL wire_n1ll0O_dataout : STD_LOGIC; + SIGNAL wire_n1ll1i_dataout : STD_LOGIC; + SIGNAL wire_n1ll1l_dataout : STD_LOGIC; + SIGNAL wire_n1ll1O_dataout : STD_LOGIC; + SIGNAL wire_n1lli_dataout : STD_LOGIC; + SIGNAL wire_n1llii_dataout : STD_LOGIC; + SIGNAL wire_n1llil_dataout : STD_LOGIC; + SIGNAL wire_n1lliO_dataout : STD_LOGIC; + SIGNAL wire_n1lll_dataout : STD_LOGIC; + SIGNAL wire_n1llli_dataout : STD_LOGIC; + SIGNAL wire_n1llll_dataout : STD_LOGIC; + SIGNAL wire_n1lllO_dataout : STD_LOGIC; + SIGNAL wire_n1llOi_dataout : STD_LOGIC; + SIGNAL wire_n1llOl_dataout : STD_LOGIC; + SIGNAL wire_n1llOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O_dataout : STD_LOGIC; + SIGNAL wire_n1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOii_dataout : STD_LOGIC; + SIGNAL wire_n1lOil_dataout : STD_LOGIC; + SIGNAL wire_n1lOiO_dataout : STD_LOGIC; + SIGNAL wire_n1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOli_dataout : STD_LOGIC; + SIGNAL wire_n1lOll_dataout : STD_LOGIC; + SIGNAL wire_n1lOlO_dataout : STD_LOGIC; + SIGNAL wire_n1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1lOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOOO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O00i_dataout : STD_LOGIC; + SIGNAL wire_n1O00l_dataout : STD_LOGIC; + SIGNAL wire_n1O00O_dataout : STD_LOGIC; + SIGNAL wire_n1O01i_dataout : STD_LOGIC; + SIGNAL wire_n1O01l_dataout : STD_LOGIC; + SIGNAL wire_n1O01O_dataout : STD_LOGIC; + SIGNAL wire_n1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0ii_dataout : STD_LOGIC; + SIGNAL wire_n1O0il_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO_dataout : STD_LOGIC; + SIGNAL wire_n1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0li_dataout : STD_LOGIC; + SIGNAL wire_n1O0ll_dataout : STD_LOGIC; + SIGNAL wire_n1O0lO_dataout : STD_LOGIC; + SIGNAL wire_n1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO_dataout : STD_LOGIC; + SIGNAL wire_n1O10i_dataout : STD_LOGIC; + SIGNAL wire_n1O10l_dataout : STD_LOGIC; + SIGNAL wire_n1O10O_dataout : STD_LOGIC; + SIGNAL wire_n1O11i_dataout : STD_LOGIC; + SIGNAL wire_n1O11l_dataout : STD_LOGIC; + SIGNAL wire_n1O11O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1il_dataout : STD_LOGIC; + SIGNAL wire_n1O1iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1li_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1Oili_dataout : STD_LOGIC; + SIGNAL wire_n1Oill_dataout : STD_LOGIC; + SIGNAL wire_n1OilO_dataout : STD_LOGIC; + SIGNAL wire_n1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1OiOO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1Olii_dataout : STD_LOGIC; + SIGNAL wire_n1Olil_dataout : STD_LOGIC; + SIGNAL wire_n1OliO_dataout : STD_LOGIC; + SIGNAL wire_n1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1Olli_dataout : STD_LOGIC; + SIGNAL wire_n1Olll_dataout : STD_LOGIC; + SIGNAL wire_n1OllO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOii_dataout : STD_LOGIC; + SIGNAL wire_n1OOil_dataout : STD_LOGIC; + SIGNAL wire_n1OOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOli_dataout : STD_LOGIC; + SIGNAL wire_n1OOll_dataout : STD_LOGIC; + SIGNAL wire_n1OOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1OOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOOO_dataout : STD_LOGIC; + SIGNAL wire_ni000l_dataout : STD_LOGIC; + SIGNAL wire_ni001l_dataout : STD_LOGIC; + SIGNAL wire_ni00i_dataout : STD_LOGIC; + SIGNAL wire_ni00iO_dataout : STD_LOGIC; + SIGNAL wire_ni00l_dataout : STD_LOGIC; + SIGNAL wire_ni00li_dataout : STD_LOGIC; + SIGNAL wire_ni00ll_dataout : STD_LOGIC; + SIGNAL wire_ni00O_dataout : STD_LOGIC; + SIGNAL wire_ni00Ol_dataout : STD_LOGIC; + SIGNAL wire_ni00OO_dataout : STD_LOGIC; + SIGNAL wire_ni010i_dataout : STD_LOGIC; + SIGNAL wire_ni011l_dataout : STD_LOGIC; + SIGNAL wire_ni01i_dataout : STD_LOGIC; + SIGNAL wire_ni01il_dataout : STD_LOGIC; + SIGNAL wire_ni01l_dataout : STD_LOGIC; + SIGNAL wire_ni01ll_dataout : STD_LOGIC; + SIGNAL wire_ni01O_dataout : STD_LOGIC; + SIGNAL wire_ni01Oi_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l_dataout : STD_LOGIC; + SIGNAL wire_ni0i0O_dataout : STD_LOGIC; + SIGNAL wire_ni0i1O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0iii_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO_dataout : STD_LOGIC; + SIGNAL wire_ni0il_dataout : STD_LOGIC; + SIGNAL wire_ni0ili_dataout : STD_LOGIC; + SIGNAL wire_ni0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i_dataout : STD_LOGIC; + SIGNAL wire_ni0li_dataout : STD_LOGIC; + SIGNAL wire_ni0lil_dataout : STD_LOGIC; + SIGNAL wire_ni0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0lli_dataout : STD_LOGIC; + SIGNAL wire_ni0lll_dataout : STD_LOGIC; + SIGNAL wire_ni0llO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli_dataout : STD_LOGIC; + SIGNAL wire_ni0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni100i_dataout : STD_LOGIC; + SIGNAL wire_ni100l_dataout : STD_LOGIC; + SIGNAL wire_ni100O_dataout : STD_LOGIC; + SIGNAL wire_ni101i_dataout : STD_LOGIC; + SIGNAL wire_ni101l_dataout : STD_LOGIC; + SIGNAL wire_ni101O_dataout : STD_LOGIC; + SIGNAL wire_ni10i_dataout : STD_LOGIC; + SIGNAL wire_ni10ii_dataout : STD_LOGIC; + SIGNAL wire_ni10il_dataout : STD_LOGIC; + SIGNAL wire_ni10iO_dataout : STD_LOGIC; + SIGNAL wire_ni10l_dataout : STD_LOGIC; + SIGNAL wire_ni10li_dataout : STD_LOGIC; + SIGNAL wire_ni10ll_dataout : STD_LOGIC; + SIGNAL wire_ni10lO_dataout : STD_LOGIC; + SIGNAL wire_ni10O_dataout : STD_LOGIC; + SIGNAL wire_ni10Oi_dataout : STD_LOGIC; + SIGNAL wire_ni10Ol_dataout : STD_LOGIC; + SIGNAL wire_ni10OO_dataout : STD_LOGIC; + SIGNAL wire_ni110O_dataout : STD_LOGIC; + SIGNAL wire_ni11ii_dataout : STD_LOGIC; + SIGNAL wire_ni11il_dataout : STD_LOGIC; + SIGNAL wire_ni11iO_dataout : STD_LOGIC; + SIGNAL wire_ni11li_dataout : STD_LOGIC; + SIGNAL wire_ni11ll_dataout : STD_LOGIC; + SIGNAL wire_ni11lO_dataout : STD_LOGIC; + SIGNAL wire_ni11Oi_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol_dataout : STD_LOGIC; + SIGNAL wire_ni11OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i_dataout : STD_LOGIC; + SIGNAL wire_ni1i0l_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i1i_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O_dataout : STD_LOGIC; + SIGNAL wire_ni1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1iii_dataout : STD_LOGIC; + SIGNAL wire_ni1iil_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO_dataout : STD_LOGIC; + SIGNAL wire_ni1il_dataout : STD_LOGIC; + SIGNAL wire_ni1ili_dataout : STD_LOGIC; + SIGNAL wire_ni1ill_dataout : STD_LOGIC; + SIGNAL wire_ni1ilO_dataout : STD_LOGIC; + SIGNAL wire_ni1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iOO_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l_dataout : STD_LOGIC; + SIGNAL wire_ni1li_dataout : STD_LOGIC; + SIGNAL wire_ni1lii_dataout : STD_LOGIC; + SIGNAL wire_ni1lil_dataout : STD_LOGIC; + SIGNAL wire_ni1liO_dataout : STD_LOGIC; + SIGNAL wire_ni1liO_w_lg_dataout678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1lli_dataout : STD_LOGIC; + SIGNAL wire_ni1lli_w_lg_w_lg_w_lg_dataout679w680w681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lli_w_lg_w_lg_dataout679w680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lli_w_lg_dataout679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lll_dataout : STD_LOGIC; + SIGNAL wire_ni1lll_w_lg_dataout3799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llO_dataout : STD_LOGIC; + SIGNAL wire_ni1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1Oil_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli_dataout : STD_LOGIC; + SIGNAL wire_ni1Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1OO_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nii01l_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0iO_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0lO_dataout : STD_LOGIC; + SIGNAL wire_nii10l_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1li_dataout : STD_LOGIC; + SIGNAL wire_nii1ll_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niii0l_dataout : STD_LOGIC; + SIGNAL wire_niii0O_dataout : STD_LOGIC; + SIGNAL wire_niii1i_dataout : STD_LOGIC; + SIGNAL wire_niiili_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niil0l_dataout : STD_LOGIC; + SIGNAL wire_niil1l_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niiliO_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niilOi_dataout : STD_LOGIC; + SIGNAL wire_niilOl_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO_w_lg_dataout512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOili_dataout : STD_LOGIC; + SIGNAL wire_niOill_dataout : STD_LOGIC; + SIGNAL wire_niOilO_dataout : STD_LOGIC; + SIGNAL wire_niOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOlii_dataout : STD_LOGIC; + SIGNAL wire_niOlil_dataout : STD_LOGIC; + SIGNAL wire_niOliO_dataout : STD_LOGIC; + SIGNAL wire_niOlli_dataout : STD_LOGIC; + SIGNAL wire_niOlll_dataout : STD_LOGIC; + SIGNAL wire_niOllO_dataout : STD_LOGIC; + SIGNAL wire_niOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOl_dataout : STD_LOGIC; + SIGNAL wire_niOlOO_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOO0i_dataout : STD_LOGIC; + SIGNAL wire_niOO0l_dataout : STD_LOGIC; + SIGNAL wire_niOO0O_dataout : STD_LOGIC; + SIGNAL wire_niOO1i_dataout : STD_LOGIC; + SIGNAL wire_niOO1l_dataout : STD_LOGIC; + SIGNAL wire_niOO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOii_dataout : STD_LOGIC; + SIGNAL wire_niOOil_dataout : STD_LOGIC; + SIGNAL wire_niOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOli_dataout : STD_LOGIC; + SIGNAL wire_niOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl010l_dataout : STD_LOGIC; + SIGNAL wire_nl010O_dataout : STD_LOGIC; + SIGNAL wire_nl01ii_dataout : STD_LOGIC; + SIGNAL wire_nl01il_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl100i_dataout : STD_LOGIC; + SIGNAL wire_nl100l_dataout : STD_LOGIC; + SIGNAL wire_nl100O_dataout : STD_LOGIC; + SIGNAL wire_nl101i_dataout : STD_LOGIC; + SIGNAL wire_nl101l_dataout : STD_LOGIC; + SIGNAL wire_nl101O_dataout : STD_LOGIC; + SIGNAL wire_nl10ii_dataout : STD_LOGIC; + SIGNAL wire_nl10il_dataout : STD_LOGIC; + SIGNAL wire_nl10iO_dataout : STD_LOGIC; + SIGNAL wire_nl10li_dataout : STD_LOGIC; + SIGNAL wire_nl10ll_dataout : STD_LOGIC; + SIGNAL wire_nl10lO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10OO_dataout : STD_LOGIC; + SIGNAL wire_nl110i_dataout : STD_LOGIC; + SIGNAL wire_nl110l_dataout : STD_LOGIC; + SIGNAL wire_nl110O_dataout : STD_LOGIC; + SIGNAL wire_nl111i_dataout : STD_LOGIC; + SIGNAL wire_nl111l_dataout : STD_LOGIC; + SIGNAL wire_nl111O_dataout : STD_LOGIC; + SIGNAL wire_nl11ii_dataout : STD_LOGIC; + SIGNAL wire_nl11il_dataout : STD_LOGIC; + SIGNAL wire_nl11iO_dataout : STD_LOGIC; + SIGNAL wire_nl11li_dataout : STD_LOGIC; + SIGNAL wire_nl11ll_dataout : STD_LOGIC; + SIGNAL wire_nl11lO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i_w_lg_dataout5769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O_w_lg_dataout5768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli_w_lg_dataout535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O_dataout : STD_LOGIC; + SIGNAL wire_nli00O_w_lg_dataout647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli01l_dataout : STD_LOGIC; + SIGNAL wire_nli01l_w_lg_dataout653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0OO_dataout : STD_LOGIC; + SIGNAL wire_nli1li_dataout : STD_LOGIC; + SIGNAL wire_nli1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlii0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1O_dataout : STD_LOGIC; + SIGNAL wire_nliiii_dataout : STD_LOGIC; + SIGNAL wire_nliiil_dataout : STD_LOGIC; + SIGNAL wire_nliiiO_dataout : STD_LOGIC; + SIGNAL wire_nliili_dataout : STD_LOGIC; + SIGNAL wire_nliill_dataout : STD_LOGIC; + SIGNAL wire_nliilO_dataout : STD_LOGIC; + SIGNAL wire_nliiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlil0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O_dataout : STD_LOGIC; + SIGNAL wire_nlilii_dataout : STD_LOGIC; + SIGNAL wire_nlilil_dataout : STD_LOGIC; + SIGNAL wire_nliliO_dataout : STD_LOGIC; + SIGNAL wire_nlilli_dataout : STD_LOGIC; + SIGNAL wire_nlilll_dataout : STD_LOGIC; + SIGNAL wire_nlilOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOi_w_lg_dataout523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlilOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOl_w_lg_dataout545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ill_dataout : STD_LOGIC; + SIGNAL wire_nlO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lil_dataout : STD_LOGIC; + SIGNAL wire_nlO0liO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli_dataout : STD_LOGIC; + SIGNAL wire_nlO0lll_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1ill_dataout : STD_LOGIC; + SIGNAL wire_nlO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi00i_dataout : STD_LOGIC; + SIGNAL wire_nlOi00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi00O_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i_dataout : STD_LOGIC; + SIGNAL wire_nlOi01l_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0il_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi10i_dataout : STD_LOGIC; + SIGNAL wire_nlOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlOi10O_dataout : STD_LOGIC; + SIGNAL wire_nlOi11i_dataout : STD_LOGIC; + SIGNAL wire_nlOi11l_dataout : STD_LOGIC; + SIGNAL wire_nlOi11O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1il_dataout : STD_LOGIC; + SIGNAL wire_nlOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiili_dataout : STD_LOGIC; + SIGNAL wire_nlOiill_dataout : STD_LOGIC; + SIGNAL wire_nlOiilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i_dataout : STD_LOGIC; + SIGNAL wire_nlOil0l_dataout : STD_LOGIC; + SIGNAL wire_nlOil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOil1O_dataout : STD_LOGIC; + SIGNAL wire_nlOilii_dataout : STD_LOGIC; + SIGNAL wire_nlOilil_dataout : STD_LOGIC; + SIGNAL wire_nlOiliO_dataout : STD_LOGIC; + SIGNAL wire_nlOilli_dataout : STD_LOGIC; + SIGNAL wire_nlOilll_dataout : STD_LOGIC; + SIGNAL wire_nlOillO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOli_dataout : STD_LOGIC; + SIGNAL wire_nlOiOll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl00l_dataout : STD_LOGIC; + SIGNAL wire_nlOl00O_dataout : STD_LOGIC; + SIGNAL wire_nlOl01i_dataout : STD_LOGIC; + SIGNAL wire_nlOl01l_dataout : STD_LOGIC; + SIGNAL wire_nlOl01O_dataout : STD_LOGIC; + SIGNAL wire_nlOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl0il_dataout : STD_LOGIC; + SIGNAL wire_nlOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0li_dataout : STD_LOGIC; + SIGNAL wire_nlOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10i_dataout : STD_LOGIC; + SIGNAL wire_nlOl10l_dataout : STD_LOGIC; + SIGNAL wire_nlOl10O_dataout : STD_LOGIC; + SIGNAL wire_nlOl11i_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l_dataout : STD_LOGIC; + SIGNAL wire_nlOl11O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1il_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1li_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOli0i_dataout : STD_LOGIC; + SIGNAL wire_nlOli0l_dataout : STD_LOGIC; + SIGNAL wire_nlOli0O_dataout : STD_LOGIC; + SIGNAL wire_nlOli1i_dataout : STD_LOGIC; + SIGNAL wire_nlOli1l_dataout : STD_LOGIC; + SIGNAL wire_nlOli1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOliii_dataout : STD_LOGIC; + SIGNAL wire_nlOliil_dataout : STD_LOGIC; + SIGNAL wire_nlOliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOlili_dataout : STD_LOGIC; + SIGNAL wire_nlOlill_dataout : STD_LOGIC; + SIGNAL wire_nlOlilO_dataout : STD_LOGIC; + SIGNAL wire_nlOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOllii_dataout : STD_LOGIC; + SIGNAL wire_nlOllil_dataout : STD_LOGIC; + SIGNAL wire_nlOlliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOllli_dataout : STD_LOGIC; + SIGNAL wire_nlOllll_dataout : STD_LOGIC; + SIGNAL wire_nlOlllO_dataout : STD_LOGIC; + SIGNAL wire_nlOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOi_dataout : STD_LOGIC; + SIGNAL wire_nlOllOl_dataout : STD_LOGIC; + SIGNAL wire_nlOllOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOili_dataout : STD_LOGIC; + SIGNAL wire_nlOOill_dataout : STD_LOGIC; + SIGNAL wire_nlOOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0iO0O_i : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0iO0O_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l0lO_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l0lO_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0l1iO_i : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0l1iO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range432w434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range437w439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range441w443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range449w451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range453w455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range461w463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_lg_w_o_range465w467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_i : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_niOOi_o : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOi_w_o_range465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_o_range217w219w223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_o_range235w237w241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_o_range253w255w259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range206w208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range211w213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range217w219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range225w227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range231w233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range235w237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range245w247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range249w251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_o_range253w255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_i : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nliOi_o : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_o_range253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00O0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00O0i_o : STD_LOGIC; + SIGNAL wire_n00O0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00O0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00O0l_o : STD_LOGIC; + SIGNAL wire_n00O0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00O0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00O0O_o : STD_LOGIC; + SIGNAL wire_n00O0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00O1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00O1i_o : STD_LOGIC; + SIGNAL wire_n00O1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00O1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00O1l_o : STD_LOGIC; + SIGNAL wire_n00O1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00O1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00O1O_o : STD_LOGIC; + SIGNAL wire_n00O1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00Oii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00Oii_o : STD_LOGIC; + SIGNAL wire_n00Oii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00Oil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00Oil_o : STD_LOGIC; + SIGNAL wire_n00Oil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00OiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00OiO_o : STD_LOGIC; + SIGNAL wire_n00OiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00Oli_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00Oli_o : STD_LOGIC; + SIGNAL wire_n00Oli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00Oll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00Oll_o : STD_LOGIC; + SIGNAL wire_n00Oll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00OlO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00OlO_o : STD_LOGIC; + SIGNAL wire_n00OlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00OOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00OOi_o : STD_LOGIC; + SIGNAL wire_n00OOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00OOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00OOl_o : STD_LOGIC; + SIGNAL wire_n00OOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00OOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n00OOO_o : STD_LOGIC; + SIGNAL wire_n00OOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i00i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i00i_o : STD_LOGIC; + SIGNAL wire_n0i00i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i00l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i00l_o : STD_LOGIC; + SIGNAL wire_n0i00l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i00O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i00O_o : STD_LOGIC; + SIGNAL wire_n0i00O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i01i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i01i_o : STD_LOGIC; + SIGNAL wire_n0i01i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i01l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i01l_o : STD_LOGIC; + SIGNAL wire_n0i01l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i01O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i01O_o : STD_LOGIC; + SIGNAL wire_n0i01O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0ii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0ii_o : STD_LOGIC; + SIGNAL wire_n0i0ii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0il_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0il_o : STD_LOGIC; + SIGNAL wire_n0i0il_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0iO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0iO_o : STD_LOGIC; + SIGNAL wire_n0i0iO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0li_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0li_o : STD_LOGIC; + SIGNAL wire_n0i0li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0ll_o : STD_LOGIC; + SIGNAL wire_n0i0ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0lO_o : STD_LOGIC; + SIGNAL wire_n0i0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0Oi_o : STD_LOGIC; + SIGNAL wire_n0i0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0Ol_o : STD_LOGIC; + SIGNAL wire_n0i0Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i0OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i0OO_o : STD_LOGIC; + SIGNAL wire_n0i0OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i10i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i10i_o : STD_LOGIC; + SIGNAL wire_n0i10i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i10l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i10l_o : STD_LOGIC; + SIGNAL wire_n0i10l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i10O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i10O_o : STD_LOGIC; + SIGNAL wire_n0i10O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i11i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i11i_o : STD_LOGIC; + SIGNAL wire_n0i11i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i11l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i11l_o : STD_LOGIC; + SIGNAL wire_n0i11l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i11O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i11O_o : STD_LOGIC; + SIGNAL wire_n0i11O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1ii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1ii_o : STD_LOGIC; + SIGNAL wire_n0i1ii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1il_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1il_o : STD_LOGIC; + SIGNAL wire_n0i1il_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1iO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1iO_o : STD_LOGIC; + SIGNAL wire_n0i1iO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1li_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1li_o : STD_LOGIC; + SIGNAL wire_n0i1li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1ll_o : STD_LOGIC; + SIGNAL wire_n0i1ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1lO_o : STD_LOGIC; + SIGNAL wire_n0i1lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1Oi_o : STD_LOGIC; + SIGNAL wire_n0i1Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1Ol_o : STD_LOGIC; + SIGNAL wire_n0i1Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0i1OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0i1OO_o : STD_LOGIC; + SIGNAL wire_n0i1OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0ii0i_o : STD_LOGIC; + SIGNAL wire_n0ii0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0ii0l_o : STD_LOGIC; + SIGNAL wire_n0ii0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0ii0O_o : STD_LOGIC; + SIGNAL wire_n0ii0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0ii1i_o : STD_LOGIC; + SIGNAL wire_n0ii1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0ii1l_o : STD_LOGIC; + SIGNAL wire_n0ii1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0ii1O_o : STD_LOGIC; + SIGNAL wire_n0ii1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iiii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iiii_o : STD_LOGIC; + SIGNAL wire_n0iiii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iiil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iiil_o : STD_LOGIC; + SIGNAL wire_n0iiil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iiiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iiiO_o : STD_LOGIC; + SIGNAL wire_n0iiiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iili_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iili_o : STD_LOGIC; + SIGNAL wire_n0iili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iill_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iill_o : STD_LOGIC; + SIGNAL wire_n0iill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iilO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iilO_o : STD_LOGIC; + SIGNAL wire_n0iilO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iiOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iiOi_o : STD_LOGIC; + SIGNAL wire_n0iiOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iiOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iiOl_o : STD_LOGIC; + SIGNAL wire_n0iiOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iiOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0iiOO_o : STD_LOGIC; + SIGNAL wire_n0iiOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0il0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0il0i_o : STD_LOGIC; + SIGNAL wire_n0il0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0il1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0il1i_o : STD_LOGIC; + SIGNAL wire_n0il1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0il1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0il1l_o : STD_LOGIC; + SIGNAL wire_n0il1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0il1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0il1O_o : STD_LOGIC; + SIGNAL wire_n0il1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l00l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0l00l_o : STD_LOGIC; + SIGNAL wire_n0l00l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l11l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0l11l_o : STD_LOGIC; + SIGNAL wire_n0l11l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0O00i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O00i_o : STD_LOGIC; + SIGNAL wire_n0O00i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O00l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O00l_o : STD_LOGIC; + SIGNAL wire_n0O00l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O00O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O00O_o : STD_LOGIC; + SIGNAL wire_n0O00O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O01l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O01l_o : STD_LOGIC; + SIGNAL wire_n0O01l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O01O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O01O_o : STD_LOGIC; + SIGNAL wire_n0O01O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0ii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0ii_o : STD_LOGIC; + SIGNAL wire_n0O0ii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0il_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0il_o : STD_LOGIC; + SIGNAL wire_n0O0il_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0iO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0iO_o : STD_LOGIC; + SIGNAL wire_n0O0iO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0li_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0li_o : STD_LOGIC; + SIGNAL wire_n0O0li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0ll_o : STD_LOGIC; + SIGNAL wire_n0O0ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0lO_o : STD_LOGIC; + SIGNAL wire_n0O0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0Oi_o : STD_LOGIC; + SIGNAL wire_n0O0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0Ol_o : STD_LOGIC; + SIGNAL wire_n0O0Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0O0OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0O0OO_o : STD_LOGIC; + SIGNAL wire_n0O0OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oi0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oi0i_o : STD_LOGIC; + SIGNAL wire_n0Oi0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oi0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oi0l_o : STD_LOGIC; + SIGNAL wire_n0Oi0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oi0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oi0O_o : STD_LOGIC; + SIGNAL wire_n0Oi0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oi1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oi1i_o : STD_LOGIC; + SIGNAL wire_n0Oi1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oi1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oi1l_o : STD_LOGIC; + SIGNAL wire_n0Oi1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oi1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oi1O_o : STD_LOGIC; + SIGNAL wire_n0Oi1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oiii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oiii_o : STD_LOGIC; + SIGNAL wire_n0Oiii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oiil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oiil_o : STD_LOGIC; + SIGNAL wire_n0Oiil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OiiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OiiO_o : STD_LOGIC; + SIGNAL wire_n0OiiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oili_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oili_o : STD_LOGIC; + SIGNAL wire_n0Oili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oill_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oill_o : STD_LOGIC; + SIGNAL wire_n0Oill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OilO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OilO_o : STD_LOGIC; + SIGNAL wire_n0OilO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OiOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OiOi_o : STD_LOGIC; + SIGNAL wire_n0OiOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OiOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OiOl_o : STD_LOGIC; + SIGNAL wire_n0OiOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OiOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OiOO_o : STD_LOGIC; + SIGNAL wire_n0OiOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Ol0i_o : STD_LOGIC; + SIGNAL wire_n0Ol0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Ol0l_o : STD_LOGIC; + SIGNAL wire_n0Ol0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Ol0O_o : STD_LOGIC; + SIGNAL wire_n0Ol0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Ol1i_o : STD_LOGIC; + SIGNAL wire_n0Ol1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Ol1l_o : STD_LOGIC; + SIGNAL wire_n0Ol1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Ol1O_o : STD_LOGIC; + SIGNAL wire_n0Ol1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Olii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Olii_o : STD_LOGIC; + SIGNAL wire_n0Olii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Olil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Olil_o : STD_LOGIC; + SIGNAL wire_n0Olil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OliO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OliO_o : STD_LOGIC; + SIGNAL wire_n0OliO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Olli_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Olli_o : STD_LOGIC; + SIGNAL wire_n0Olli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Olll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Olll_o : STD_LOGIC; + SIGNAL wire_n0Olll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OllO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OllO_o : STD_LOGIC; + SIGNAL wire_n0OllO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OlOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OlOi_o : STD_LOGIC; + SIGNAL wire_n0OlOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OlOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OlOl_o : STD_LOGIC; + SIGNAL wire_n0OlOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OlOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OlOO_o : STD_LOGIC; + SIGNAL wire_n0OlOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OO0i_o : STD_LOGIC; + SIGNAL wire_n0OO0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OO0l_o : STD_LOGIC; + SIGNAL wire_n0OO0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OO0O_o : STD_LOGIC; + SIGNAL wire_n0OO0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OO1i_o : STD_LOGIC; + SIGNAL wire_n0OO1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO1l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OO1l_o : STD_LOGIC; + SIGNAL wire_n0OO1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OO1O_o : STD_LOGIC; + SIGNAL wire_n0OO1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOii_o : STD_LOGIC; + SIGNAL wire_n0OOii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOil_o : STD_LOGIC; + SIGNAL wire_n0OOil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOiO_o : STD_LOGIC; + SIGNAL wire_n0OOiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOli_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOli_o : STD_LOGIC; + SIGNAL wire_n0OOli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOll_o : STD_LOGIC; + SIGNAL wire_n0OOll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOlO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOlO_o : STD_LOGIC; + SIGNAL wire_n0OOlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOOi_o : STD_LOGIC; + SIGNAL wire_n0OOOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOOl_o : STD_LOGIC; + SIGNAL wire_n0OOOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOOO_o : STD_LOGIC; + SIGNAL wire_n0OOOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni110i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni110i_o : STD_LOGIC; + SIGNAL wire_ni110i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni110l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni110l_o : STD_LOGIC; + SIGNAL wire_ni110l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni111i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni111i_o : STD_LOGIC; + SIGNAL wire_ni111i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni111l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni111l_o : STD_LOGIC; + SIGNAL wire_ni111l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni111O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni111O_o : STD_LOGIC; + SIGNAL wire_ni111O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1i1l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_ni1i1l_o : STD_LOGIC; + SIGNAL wire_ni1i1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1l1O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni1l1O_o : STD_LOGIC; + SIGNAL wire_ni1l1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1lOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_ni1lOi_o : STD_LOGIC; + SIGNAL wire_ni1lOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1lOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_ni1lOl_o : STD_LOGIC; + SIGNAL wire_ni1lOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1lOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_ni1lOO_o : STD_LOGIC; + SIGNAL wire_ni1lOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1O1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_ni1O1i_o : STD_LOGIC; + SIGNAL wire_ni1O1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO000i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO000i_o : STD_LOGIC; + SIGNAL wire_nlO000i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO000l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO000l_o : STD_LOGIC; + SIGNAL wire_nlO000l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO000O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO000O_o : STD_LOGIC; + SIGNAL wire_nlO000O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO001i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO001i_o : STD_LOGIC; + SIGNAL wire_nlO001i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO001l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO001l_o : STD_LOGIC; + SIGNAL wire_nlO001l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO001O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO001O_o : STD_LOGIC; + SIGNAL wire_nlO001O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00ii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00ii_o : STD_LOGIC; + SIGNAL wire_nlO00ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00il_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00il_o : STD_LOGIC; + SIGNAL wire_nlO00il_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00iO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00iO_o : STD_LOGIC; + SIGNAL wire_nlO00iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00li_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00li_o : STD_LOGIC; + SIGNAL wire_nlO00li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00ll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00ll_o : STD_LOGIC; + SIGNAL wire_nlO00ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00lO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00lO_o : STD_LOGIC; + SIGNAL wire_nlO00lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Oi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00Oi_o : STD_LOGIC; + SIGNAL wire_nlO00Oi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Ol_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00Ol_o : STD_LOGIC; + SIGNAL wire_nlO00Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00OO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO00OO_o : STD_LOGIC; + SIGNAL wire_nlO00OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO010i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO010i_o : STD_LOGIC; + SIGNAL wire_nlO010i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO010l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO010l_o : STD_LOGIC; + SIGNAL wire_nlO010l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO010O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO010O_o : STD_LOGIC; + SIGNAL wire_nlO010O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO011i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO011i_o : STD_LOGIC; + SIGNAL wire_nlO011i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO011l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO011l_o : STD_LOGIC; + SIGNAL wire_nlO011l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO011O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO011O_o : STD_LOGIC; + SIGNAL wire_nlO011O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01ii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01ii_o : STD_LOGIC; + SIGNAL wire_nlO01ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01il_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01il_o : STD_LOGIC; + SIGNAL wire_nlO01il_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01iO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01iO_o : STD_LOGIC; + SIGNAL wire_nlO01iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01li_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01li_o : STD_LOGIC; + SIGNAL wire_nlO01li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01ll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01ll_o : STD_LOGIC; + SIGNAL wire_nlO01ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01lO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01lO_o : STD_LOGIC; + SIGNAL wire_nlO01lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01Oi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01Oi_o : STD_LOGIC; + SIGNAL wire_nlO01Oi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01Ol_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01Ol_o : STD_LOGIC; + SIGNAL wire_nlO01Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO01OO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO01OO_o : STD_LOGIC; + SIGNAL wire_nlO01OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0i0i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0i0i_o : STD_LOGIC; + SIGNAL wire_nlO0i0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0i0l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0i0l_o : STD_LOGIC; + SIGNAL wire_nlO0i0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0i0O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0i0O_o : STD_LOGIC; + SIGNAL wire_nlO0i0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0i1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0i1i_o : STD_LOGIC; + SIGNAL wire_nlO0i1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0i1l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0i1l_o : STD_LOGIC; + SIGNAL wire_nlO0i1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0i1O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0i1O_o : STD_LOGIC; + SIGNAL wire_nlO0i1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0iii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0iii_o : STD_LOGIC; + SIGNAL wire_nlO0iii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0iil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0iil_o : STD_LOGIC; + SIGNAL wire_nlO0iil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0iiO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0iiO_o : STD_LOGIC; + SIGNAL wire_nlO0iiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0ili_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO0ili_o : STD_LOGIC; + SIGNAL wire_nlO0ili_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1lii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1lii_o : STD_LOGIC; + SIGNAL wire_nlO1lii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1lil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1lil_o : STD_LOGIC; + SIGNAL wire_nlO1lil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1liO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1liO_o : STD_LOGIC; + SIGNAL wire_nlO1liO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1lli_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1lli_o : STD_LOGIC; + SIGNAL wire_nlO1lli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1lll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1lll_o : STD_LOGIC; + SIGNAL wire_nlO1lll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1llO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1llO_o : STD_LOGIC; + SIGNAL wire_nlO1llO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1lOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1lOi_o : STD_LOGIC; + SIGNAL wire_nlO1lOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1lOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1lOl_o : STD_LOGIC; + SIGNAL wire_nlO1lOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1lOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1lOO_o : STD_LOGIC; + SIGNAL wire_nlO1lOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1O0i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1O0i_o : STD_LOGIC; + SIGNAL wire_nlO1O0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1O0l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1O0l_o : STD_LOGIC; + SIGNAL wire_nlO1O0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1O0O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1O0O_o : STD_LOGIC; + SIGNAL wire_nlO1O0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1O1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1O1i_o : STD_LOGIC; + SIGNAL wire_nlO1O1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1O1l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1O1l_o : STD_LOGIC; + SIGNAL wire_nlO1O1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1O1O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1O1O_o : STD_LOGIC; + SIGNAL wire_nlO1O1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1Oii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1Oii_o : STD_LOGIC; + SIGNAL wire_nlO1Oii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1Oil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1Oil_o : STD_LOGIC; + SIGNAL wire_nlO1Oil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1OiO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1OiO_o : STD_LOGIC; + SIGNAL wire_nlO1OiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1Oli_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1Oli_o : STD_LOGIC; + SIGNAL wire_nlO1Oli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1Oll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1Oll_o : STD_LOGIC; + SIGNAL wire_nlO1Oll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1OlO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1OlO_o : STD_LOGIC; + SIGNAL wire_nlO1OlO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1OOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1OOi_o : STD_LOGIC; + SIGNAL wire_nlO1OOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1OOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1OOl_o : STD_LOGIC; + SIGNAL wire_nlO1OOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO1OOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO1OOO_o : STD_LOGIC; + SIGNAL wire_nlO1OOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO1l_data : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_niO1l_o : STD_LOGIC; + SIGNAL wire_niO1l_sel : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nli1l_data : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nli1l_o : STD_LOGIC; + SIGNAL wire_nli1l_sel : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1000i_data_out : STD_LOGIC_VECTOR (69 DOWNTO 0); + SIGNAL wire_nl1000i_din : STD_LOGIC_VECTOR (69 DOWNTO 0); + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_nl1000i_pcs_wrapback_in : STD_LOGIC_VECTOR (69 DOWNTO 0); + SIGNAL wire_nl1000i_ph_fifo_empty : STD_LOGIC; + SIGNAL wire_nl1000i_ph_fifo_full : STD_LOGIC; + SIGNAL wire_nl1000i_rptr_bin : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1000i_wptr_bin : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rsync_comp_porn490w492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rsync_comp_porn478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rsync_comp_porn294w297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rsync_comp_porn286w289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rautoinsdis499w510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rautoinsdis499w533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rsync_sm_dis1w511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rsync_sm_dis1w534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_invalid_code_delay_range17w515w516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl110ll484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl111OO539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rrxfifo_urst_en7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_comp_porn286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_disp_err_delay_range16w517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_disp_err_delay_range13w540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_sync_resync_delay_range514w518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_sync_resync_delay_range537w541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0i3798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0l3797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0li759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0ll758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0lO753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0Oi752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOi0i735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOi1i742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOi1l741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOi1O736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOiil729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOiiO728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOili724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOill720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOiOi714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOiOl710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOl0l692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOl0O688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOl1i706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOl1l702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOl1O698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOlil684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOO0l650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl101ll641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1110l617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl111ll574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rautoinsdis499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rbytord_s2gx660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rbytordplden683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rclkcmpinsertpad522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rdwidth639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rfreq_sel609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rinvalid_code_err_only497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rsync_sm_dis1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rwa_6g_en2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_we_in_centrl4642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_we_in_quad_down4643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rx_we_in_quad_up4644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_invalid_code_delay_range17w515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_invalid_code_delay_range14w538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4891w4918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4954w4955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4959w4960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4964w4965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4969w4970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4974w4975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4979w4980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5001w5034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5005w5038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5009w5042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5013w5046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4894w4921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5413w5464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5417w5468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5421w5472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5425w5476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5050w5081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5053w5084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5057w5088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5061w5092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5065w5096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5069w5100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4898w4925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5073w5104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5077w5108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5117w5154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5121w5158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5125w5162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5129w5166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5133w5170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5137w5174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5141w5178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5145w5182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4902w4929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4906w4933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4910w4937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4914w4941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range5249w5253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4945w4946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rsync_comp_pat_range4949w4950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rx_data_rs_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rsync_comp_porn273w274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nl11lil298w302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nl11OiO262w266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOlOO671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOO1i663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOOli631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOOOi625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1100i489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1100l493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1101l491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl110ii479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl110iO477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl110li481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl110lO485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl110lO470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11iiO473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11iOl311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11l1i307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11lil298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11lOi283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11O0i271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11O0i319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11OiO290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11OiO262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rx_data_rs_range546w549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range597w4919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range597w5017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range597w5453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range597w5569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range597w5082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range597w5149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range597w4947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range588w5373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range588w5674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range588w5736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range588w5487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range588w5607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range588w5299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range587w5375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range587w5676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range587w5738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range587w5489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range587w5609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range587w5301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range586w5304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range586w5378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range586w5679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range586w5741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range586w5492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range586w5612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range585w5307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range585w5381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range585w5682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range585w5744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range585w5495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range585w5615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range584w5310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range584w5384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range584w5685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range584w5747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range584w5498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range584w5618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range583w5313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range583w5387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range583w5688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range583w5750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range583w5501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range583w5621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range582w5316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range582w5390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range582w5691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range582w5753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range582w5504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range582w5624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range581w5319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range581w5393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range581w5694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range581w5756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range581w5507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range581w5627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range331w5396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range331w5759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range331w5630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range580w5399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range580w5762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range580w5633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range596w5019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range596w5455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range596w4922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range596w5571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range596w5085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range596w5151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range596w4951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range595w4956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range595w5022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range595w5458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range595w5574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range595w5089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range595w4926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range595w5155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range594w4961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range594w5025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range594w5461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range594w5577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range594w5093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range594w5159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range594w4930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range593w4966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range593w5028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range593w5465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range593w5580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range593w5097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range593w5163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range593w4934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range592w4971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range592w5031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range592w5469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range592w5583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range592w5101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range592w5167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range592w4938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range591w4976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range591w5035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range591w5473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range591w5586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range591w5105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range591w5171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range591w4942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range590w4981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range590w5039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range590w5477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range590w5589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range590w5109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range590w5175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range590w5296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range98w5043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range98w5592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range98w5179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range98w5358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range589w5047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range589w5595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range589w5183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tenb_data_range589w5361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOlO0i : STD_LOGIC; + SIGNAL niOlO0l : STD_LOGIC; + SIGNAL niOlO0O : STD_LOGIC; + SIGNAL niOlO1l : STD_LOGIC; + SIGNAL niOlO1O : STD_LOGIC; + SIGNAL niOlOii : STD_LOGIC; + SIGNAL niOlOil : STD_LOGIC; + SIGNAL niOlOiO : STD_LOGIC; + SIGNAL niOlOli : STD_LOGIC; + SIGNAL niOlOll : STD_LOGIC; + SIGNAL niOlOlO : STD_LOGIC; + SIGNAL niOlOOi : STD_LOGIC; + SIGNAL niOlOOl : STD_LOGIC; + SIGNAL niOlOOO : STD_LOGIC; + SIGNAL niOO00i : STD_LOGIC; + SIGNAL niOO00l : STD_LOGIC; + SIGNAL niOO00O : STD_LOGIC; + SIGNAL niOO01i : STD_LOGIC; + SIGNAL niOO01l : STD_LOGIC; + SIGNAL niOO01O : STD_LOGIC; + SIGNAL niOO0ii : STD_LOGIC; + SIGNAL niOO0il : STD_LOGIC; + SIGNAL niOO0iO : STD_LOGIC; + SIGNAL niOO0li : STD_LOGIC; + SIGNAL niOO0ll : STD_LOGIC; + SIGNAL niOO0lO : STD_LOGIC; + SIGNAL niOO0Oi : STD_LOGIC; + SIGNAL niOO0Ol : STD_LOGIC; + SIGNAL niOO0OO : STD_LOGIC; + SIGNAL niOO10i : STD_LOGIC; + SIGNAL niOO10l : STD_LOGIC; + SIGNAL niOO10O : STD_LOGIC; + SIGNAL niOO11i : STD_LOGIC; + SIGNAL niOO11l : STD_LOGIC; + SIGNAL niOO11O : STD_LOGIC; + SIGNAL niOO1ii : STD_LOGIC; + SIGNAL niOO1il : STD_LOGIC; + SIGNAL niOO1iO : STD_LOGIC; + SIGNAL niOO1li : STD_LOGIC; + SIGNAL niOO1ll : STD_LOGIC; + SIGNAL niOO1lO : STD_LOGIC; + SIGNAL niOO1Oi : STD_LOGIC; + SIGNAL niOO1Ol : STD_LOGIC; + SIGNAL niOO1OO : STD_LOGIC; + SIGNAL niOOi0i : STD_LOGIC; + SIGNAL niOOi0l : STD_LOGIC; + SIGNAL niOOi0O : STD_LOGIC; + SIGNAL niOOi1i : STD_LOGIC; + SIGNAL niOOi1l : STD_LOGIC; + SIGNAL niOOi1O : STD_LOGIC; + SIGNAL niOOiii : STD_LOGIC; + SIGNAL niOOiil : STD_LOGIC; + SIGNAL niOOiiO : STD_LOGIC; + SIGNAL niOOili : STD_LOGIC; + SIGNAL niOOill : STD_LOGIC; + SIGNAL niOOilO : STD_LOGIC; + SIGNAL niOOiOi : STD_LOGIC; + SIGNAL niOOiOl : STD_LOGIC; + SIGNAL niOOiOO : STD_LOGIC; + SIGNAL niOOl0i : STD_LOGIC; + SIGNAL niOOl0l : STD_LOGIC; + SIGNAL niOOl0O : STD_LOGIC; + SIGNAL niOOl1i : STD_LOGIC; + SIGNAL niOOl1l : STD_LOGIC; + SIGNAL niOOl1O : STD_LOGIC; + SIGNAL niOOlii : STD_LOGIC; + SIGNAL niOOlil : STD_LOGIC; + SIGNAL niOOliO : STD_LOGIC; + SIGNAL niOOlli : STD_LOGIC; + SIGNAL niOOlll : STD_LOGIC; + SIGNAL niOOllO : STD_LOGIC; + SIGNAL niOOlOi : STD_LOGIC; + SIGNAL niOOlOl : STD_LOGIC; + SIGNAL niOOlOO : STD_LOGIC; + SIGNAL niOOO0l : STD_LOGIC; + SIGNAL niOOO1i : STD_LOGIC; + SIGNAL niOOOii : STD_LOGIC; + SIGNAL niOOOil : STD_LOGIC; + SIGNAL niOOOiO : STD_LOGIC; + SIGNAL niOOOli : STD_LOGIC; + SIGNAL niOOOll : STD_LOGIC; + SIGNAL niOOOlO : STD_LOGIC; + SIGNAL niOOOOi : STD_LOGIC; + SIGNAL niOOOOl : STD_LOGIC; + SIGNAL nl1010i : STD_LOGIC; + SIGNAL nl101il : STD_LOGIC; + SIGNAL nl101ll : STD_LOGIC; + SIGNAL nl101Ol : STD_LOGIC; + SIGNAL nl1100i : STD_LOGIC; + SIGNAL nl1100l : STD_LOGIC; + SIGNAL nl1100O : STD_LOGIC; + SIGNAL nl1101i : STD_LOGIC; + SIGNAL nl1101l : STD_LOGIC; + SIGNAL nl1101O : STD_LOGIC; + SIGNAL nl110ii : STD_LOGIC; + SIGNAL nl110il : STD_LOGIC; + SIGNAL nl110iO : STD_LOGIC; + SIGNAL nl110li : STD_LOGIC; + SIGNAL nl110ll : STD_LOGIC; + SIGNAL nl110lO : STD_LOGIC; + SIGNAL nl110Oi : STD_LOGIC; + SIGNAL nl110Ol : STD_LOGIC; + SIGNAL nl110OO : STD_LOGIC; + SIGNAL nl1110i : STD_LOGIC; + SIGNAL nl1110l : STD_LOGIC; + SIGNAL nl1110O : STD_LOGIC; + SIGNAL nl1111l : STD_LOGIC; + SIGNAL nl1111O : STD_LOGIC; + SIGNAL nl111il : STD_LOGIC; + SIGNAL nl111iO : STD_LOGIC; + SIGNAL nl111li : STD_LOGIC; + SIGNAL nl111ll : STD_LOGIC; + SIGNAL nl111lO : STD_LOGIC; + SIGNAL nl111Oi : STD_LOGIC; + SIGNAL nl111Ol : STD_LOGIC; + SIGNAL nl111OO : STD_LOGIC; + SIGNAL nl11i0i : STD_LOGIC; + SIGNAL nl11i0l : STD_LOGIC; + SIGNAL nl11i0O : STD_LOGIC; + SIGNAL nl11i1i : STD_LOGIC; + SIGNAL nl11i1l : STD_LOGIC; + SIGNAL nl11i1O : STD_LOGIC; + SIGNAL nl11iii : STD_LOGIC; + SIGNAL nl11iil : STD_LOGIC; + SIGNAL nl11iiO : STD_LOGIC; + SIGNAL nl11ili : STD_LOGIC; + SIGNAL nl11ill : STD_LOGIC; + SIGNAL nl11ilO : STD_LOGIC; + SIGNAL nl11iOi : STD_LOGIC; + SIGNAL nl11iOl : STD_LOGIC; + SIGNAL nl11iOO : STD_LOGIC; + SIGNAL nl11l1i : STD_LOGIC; + SIGNAL nl11lii : STD_LOGIC; + SIGNAL nl11lil : STD_LOGIC; + SIGNAL nl11llO : STD_LOGIC; + SIGNAL nl11lOi : STD_LOGIC; + SIGNAL nl11O0i : STD_LOGIC; + SIGNAL nl11O0l : STD_LOGIC; + SIGNAL nl11O1l : STD_LOGIC; + SIGNAL nl11O1O : STD_LOGIC; + SIGNAL nl11Oil : STD_LOGIC; + SIGNAL nl11OiO : STD_LOGIC; + SIGNAL wire_w_disp_err_delay_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_disp_err_delay_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_invalid_code_delay_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_invalid_code_delay_range14w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5053w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range5249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_pat_range4949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_size_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsync_comp_size_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rx_data_rs_range546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rx_data_rs_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sync_resync_delay_range514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sync_resync_delay_range537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tenb_data_range589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + COMPONENT cycloneiv_hssi_rx_digis_ph_fifo + PORT + ( + data_out : OUT STD_LOGIC_VECTOR(69 DOWNTO 0); + din : IN STD_LOGIC_VECTOR(69 DOWNTO 0); + en : IN STD_LOGIC; + lowlatency_en : IN STD_LOGIC; + pcs_wrapback_in : IN STD_LOGIC_VECTOR(69 DOWNTO 0); + ph_fifo_empty : OUT STD_LOGIC; + ph_fifo_full : OUT STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + re : IN STD_LOGIC; + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rpcs_wrapback_en : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rst_rclk : IN STD_LOGIC; + rst_wclk : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + we : IN STD_LOGIC; + wptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + wr_clk : IN STD_LOGIC + ); + END COMPONENT; + BEGIN + + wire_vcc <= '1'; + wire_w_lg_w_lg_rsync_comp_porn490w492w(0) <= wire_w_lg_rsync_comp_porn490w(0) AND wire_w_lg_nl1101l491w(0); + wire_w_lg_w_lg_rsync_comp_porn478w480w(0) <= wire_w_lg_rsync_comp_porn478w(0) AND wire_w_lg_nl110ii479w(0); + wire_w_lg_w_lg_rsync_comp_porn294w297w(0) <= wire_w_lg_rsync_comp_porn294w(0) AND wire_nl11l0l36_w_lg_q296w(0); + wire_w_lg_w_lg_rsync_comp_porn286w289w(0) <= wire_w_lg_rsync_comp_porn286w(0) AND wire_nl11lli32_w_lg_q288w(0); + wire_w_lg_w_lg_rautoinsdis499w510w(0) <= wire_w_lg_rautoinsdis499w(0) AND wire_nlilOi_dataout; + wire_w_lg_w_lg_rautoinsdis499w533w(0) <= wire_w_lg_rautoinsdis499w(0) AND wire_nlilOl_dataout; + wire_w_lg_w_lg_rsync_sm_dis1w511w(0) <= wire_w_lg_rsync_sm_dis1w(0) AND wire_w_lg_w_lg_rautoinsdis499w510w(0); + wire_w_lg_w_lg_rsync_sm_dis1w534w(0) <= wire_w_lg_rsync_sm_dis1w(0) AND wire_w_lg_w_lg_rautoinsdis499w533w(0); + wire_w_lg_w_lg_w_invalid_code_delay_range17w515w516w(0) <= wire_w_lg_w_invalid_code_delay_range17w515w(0) AND nl111OO; + wire_w_lg_nl110ll484w(0) <= nl110ll AND rsync_comp_porn; + wire_w_lg_nl111OO539w(0) <= nl111OO AND wire_w_lg_w_invalid_code_delay_range14w538w(0); + wire_w_lg_rrxfifo_urst_en7w(0) <= rrxfifo_urst_en AND rxfifo_urst; + wire_w_lg_rsync_comp_porn632w(0) <= rsync_comp_porn AND wire_w_lg_niOOOli631w(0); + wire_w_lg_rsync_comp_porn626w(0) <= rsync_comp_porn AND wire_w_lg_niOOOOi625w(0); + wire_w_lg_rsync_comp_porn490w(0) <= rsync_comp_porn AND wire_w_lg_nl1100i489w(0); + wire_w_lg_rsync_comp_porn478w(0) <= rsync_comp_porn AND wire_w_lg_nl110iO477w(0); + wire_w_lg_rsync_comp_porn320w(0) <= rsync_comp_porn AND wire_w_lg_nl11O0i319w(0); + wire_w_lg_rsync_comp_porn310w(0) <= rsync_comp_porn AND nl11iOi; + wire_w_lg_rsync_comp_porn306w(0) <= rsync_comp_porn AND nl11iOO; + wire_w_lg_rsync_comp_porn294w(0) <= rsync_comp_porn AND nl11lii; + wire_w_lg_rsync_comp_porn282w(0) <= rsync_comp_porn AND nl11llO; + wire_w_lg_rsync_comp_porn273w(0) <= rsync_comp_porn AND nl11O1l; + wire_w_lg_rsync_comp_porn270w(0) <= rsync_comp_porn AND nl11O1O; + wire_w_lg_rsync_comp_porn286w(0) <= rsync_comp_porn AND nl11Oil; + wire_w_lg_w_disp_err_delay_range16w517w(0) <= wire_w_disp_err_delay_range16w(0) AND wire_w_lg_w_lg_w_invalid_code_delay_range17w515w516w(0); + wire_w_lg_w_disp_err_delay_range13w540w(0) <= wire_w_disp_err_delay_range13w(0) AND wire_w_lg_nl111OO539w(0); + wire_w_lg_w_sync_resync_delay_range514w518w(0) <= wire_w_sync_resync_delay_range514w(0) AND wire_w_lg_w_disp_err_delay_range16w517w(0); + wire_w_lg_w_sync_resync_delay_range537w541w(0) <= wire_w_sync_resync_delay_range537w(0) AND wire_w_lg_w_disp_err_delay_range13w540w(0); + wire_w_lg_niOlO0i3798w(0) <= NOT niOlO0i; + wire_w_lg_niOlO0l3797w(0) <= NOT niOlO0l; + wire_w_lg_niOO0li759w(0) <= NOT niOO0li; + wire_w_lg_niOO0ll758w(0) <= NOT niOO0ll; + wire_w_lg_niOO0lO753w(0) <= NOT niOO0lO; + wire_w_lg_niOO0Oi752w(0) <= NOT niOO0Oi; + wire_w_lg_niOOi0i735w(0) <= NOT niOOi0i; + wire_w_lg_niOOi1i742w(0) <= NOT niOOi1i; + wire_w_lg_niOOi1l741w(0) <= NOT niOOi1l; + wire_w_lg_niOOi1O736w(0) <= NOT niOOi1O; + wire_w_lg_niOOiil729w(0) <= NOT niOOiil; + wire_w_lg_niOOiiO728w(0) <= NOT niOOiiO; + wire_w_lg_niOOili724w(0) <= NOT niOOili; + wire_w_lg_niOOill720w(0) <= NOT niOOill; + wire_w_lg_niOOiOi714w(0) <= NOT niOOiOi; + wire_w_lg_niOOiOl710w(0) <= NOT niOOiOl; + wire_w_lg_niOOl0l692w(0) <= NOT niOOl0l; + wire_w_lg_niOOl0O688w(0) <= NOT niOOl0O; + wire_w_lg_niOOl1i706w(0) <= NOT niOOl1i; + wire_w_lg_niOOl1l702w(0) <= NOT niOOl1l; + wire_w_lg_niOOl1O698w(0) <= NOT niOOl1O; + wire_w_lg_niOOlil684w(0) <= NOT niOOlil; + wire_w_lg_niOOO0l650w(0) <= NOT niOOO0l; + wire_w_lg_nl101ll641w(0) <= NOT nl101ll; + wire_w_lg_nl1110l617w(0) <= NOT nl1110l; + wire_w_lg_nl111ll574w(0) <= NOT nl111ll; + wire_w_lg_rautoinsdis499w(0) <= NOT rautoinsdis; + wire_w_lg_rbytord_s2gx660w(0) <= NOT rbytord_s2gx; + wire_w_lg_rbytordplden683w(0) <= NOT rbytordplden; + wire_w_lg_rclkcmpinsertpad522w(0) <= NOT rclkcmpinsertpad; + wire_w_lg_rdwidth639w(0) <= NOT rdwidth; + wire_w_lg_rfreq_sel609w(0) <= NOT rfreq_sel; + wire_w_lg_rinvalid_code_err_only497w(0) <= NOT rinvalid_code_err_only; + wire_w_lg_rsync_sm_dis1w(0) <= NOT rsync_sm_dis; + wire_w_lg_rwa_6g_en2w(0) <= NOT rwa_6g_en; + wire_w_lg_rx_we_in_centrl4642w(0) <= NOT rx_we_in_centrl; + wire_w_lg_rx_we_in_quad_down4643w(0) <= NOT rx_we_in_quad_down; + wire_w_lg_rx_we_in_quad_up4644w(0) <= NOT rx_we_in_quad_up; + wire_w_lg_soft_reset607w(0) <= NOT soft_reset; + wire_w_lg_w_invalid_code_delay_range17w515w(0) <= NOT wire_w_invalid_code_delay_range17w(0); + wire_w_lg_w_invalid_code_delay_range14w538w(0) <= NOT wire_w_invalid_code_delay_range14w(0); + wire_w_lg_w_rsync_comp_pat_range4891w4918w(0) <= NOT wire_w_rsync_comp_pat_range4891w(0); + wire_w_lg_w_rsync_comp_pat_range4954w4955w(0) <= NOT wire_w_rsync_comp_pat_range4954w(0); + wire_w_lg_w_rsync_comp_pat_range4959w4960w(0) <= NOT wire_w_rsync_comp_pat_range4959w(0); + wire_w_lg_w_rsync_comp_pat_range4964w4965w(0) <= NOT wire_w_rsync_comp_pat_range4964w(0); + wire_w_lg_w_rsync_comp_pat_range4969w4970w(0) <= NOT wire_w_rsync_comp_pat_range4969w(0); + wire_w_lg_w_rsync_comp_pat_range4974w4975w(0) <= NOT wire_w_rsync_comp_pat_range4974w(0); + wire_w_lg_w_rsync_comp_pat_range4979w4980w(0) <= NOT wire_w_rsync_comp_pat_range4979w(0); + wire_w_lg_w_rsync_comp_pat_range5001w5034w(0) <= NOT wire_w_rsync_comp_pat_range5001w(0); + wire_w_lg_w_rsync_comp_pat_range5005w5038w(0) <= NOT wire_w_rsync_comp_pat_range5005w(0); + wire_w_lg_w_rsync_comp_pat_range5009w5042w(0) <= NOT wire_w_rsync_comp_pat_range5009w(0); + wire_w_lg_w_rsync_comp_pat_range5013w5046w(0) <= NOT wire_w_rsync_comp_pat_range5013w(0); + wire_w_lg_w_rsync_comp_pat_range4894w4921w(0) <= NOT wire_w_rsync_comp_pat_range4894w(0); + wire_w_lg_w_rsync_comp_pat_range5413w5464w(0) <= NOT wire_w_rsync_comp_pat_range5413w(0); + wire_w_lg_w_rsync_comp_pat_range5417w5468w(0) <= NOT wire_w_rsync_comp_pat_range5417w(0); + wire_w_lg_w_rsync_comp_pat_range5421w5472w(0) <= NOT wire_w_rsync_comp_pat_range5421w(0); + wire_w_lg_w_rsync_comp_pat_range5425w5476w(0) <= NOT wire_w_rsync_comp_pat_range5425w(0); + wire_w_lg_w_rsync_comp_pat_range5050w5081w(0) <= NOT wire_w_rsync_comp_pat_range5050w(0); + wire_w_lg_w_rsync_comp_pat_range5053w5084w(0) <= NOT wire_w_rsync_comp_pat_range5053w(0); + wire_w_lg_w_rsync_comp_pat_range5057w5088w(0) <= NOT wire_w_rsync_comp_pat_range5057w(0); + wire_w_lg_w_rsync_comp_pat_range5061w5092w(0) <= NOT wire_w_rsync_comp_pat_range5061w(0); + wire_w_lg_w_rsync_comp_pat_range5065w5096w(0) <= NOT wire_w_rsync_comp_pat_range5065w(0); + wire_w_lg_w_rsync_comp_pat_range5069w5100w(0) <= NOT wire_w_rsync_comp_pat_range5069w(0); + wire_w_lg_w_rsync_comp_pat_range4898w4925w(0) <= NOT wire_w_rsync_comp_pat_range4898w(0); + wire_w_lg_w_rsync_comp_pat_range5073w5104w(0) <= NOT wire_w_rsync_comp_pat_range5073w(0); + wire_w_lg_w_rsync_comp_pat_range5077w5108w(0) <= NOT wire_w_rsync_comp_pat_range5077w(0); + wire_w_lg_w_rsync_comp_pat_range5117w5154w(0) <= NOT wire_w_rsync_comp_pat_range5117w(0); + wire_w_lg_w_rsync_comp_pat_range5121w5158w(0) <= NOT wire_w_rsync_comp_pat_range5121w(0); + wire_w_lg_w_rsync_comp_pat_range5125w5162w(0) <= NOT wire_w_rsync_comp_pat_range5125w(0); + wire_w_lg_w_rsync_comp_pat_range5129w5166w(0) <= NOT wire_w_rsync_comp_pat_range5129w(0); + wire_w_lg_w_rsync_comp_pat_range5133w5170w(0) <= NOT wire_w_rsync_comp_pat_range5133w(0); + wire_w_lg_w_rsync_comp_pat_range5137w5174w(0) <= NOT wire_w_rsync_comp_pat_range5137w(0); + wire_w_lg_w_rsync_comp_pat_range5141w5178w(0) <= NOT wire_w_rsync_comp_pat_range5141w(0); + wire_w_lg_w_rsync_comp_pat_range5145w5182w(0) <= NOT wire_w_rsync_comp_pat_range5145w(0); + wire_w_lg_w_rsync_comp_pat_range4902w4929w(0) <= NOT wire_w_rsync_comp_pat_range4902w(0); + wire_w_lg_w_rsync_comp_pat_range4906w4933w(0) <= NOT wire_w_rsync_comp_pat_range4906w(0); + wire_w_lg_w_rsync_comp_pat_range4910w4937w(0) <= NOT wire_w_rsync_comp_pat_range4910w(0); + wire_w_lg_w_rsync_comp_pat_range4914w4941w(0) <= NOT wire_w_rsync_comp_pat_range4914w(0); + wire_w_lg_w_rsync_comp_pat_range5249w5253w(0) <= NOT wire_w_rsync_comp_pat_range5249w(0); + wire_w_lg_w_rsync_comp_pat_range4945w4946w(0) <= NOT wire_w_rsync_comp_pat_range4945w(0); + wire_w_lg_w_rsync_comp_pat_range4949w4950w(0) <= NOT wire_w_rsync_comp_pat_range4949w(0); + wire_w_lg_w_rx_data_rs_range547w548w(0) <= NOT wire_w_rx_data_rs_range547w(0); + wire_w_lg_w_lg_rsync_comp_porn273w274w(0) <= wire_w_lg_rsync_comp_porn273w(0) OR nl101il; + wire_w_lg_w_lg_nl11lil298w302w(0) <= wire_w_lg_nl11lil298w(0) OR wire_nl11l1O38_w_lg_w_lg_q300w301w(0); + wire_w_lg_w_lg_nl11OiO262w266w(0) <= wire_w_lg_nl11OiO262w(0) OR wire_nl11O0O26_w_lg_w_lg_q264w265w(0); + wire_w_lg_niOOlOO671w(0) <= niOOlOO OR wire_n1ill_w_lg_n1iil670w(0); + wire_w_lg_niOOO1i663w(0) <= niOOO1i OR wire_n1ill_w_lg_w_lg_n1ili661w662w(0); + wire_w_lg_niOOOli631w(0) <= niOOOli OR niOOOiO; + wire_w_lg_niOOOOi625w(0) <= niOOOOi OR niOOOlO; + wire_w_lg_nl1100i489w(0) <= nl1100i OR nl1101O; + wire_w_lg_nl1100l493w(0) <= nl1100l OR wire_w_lg_w_lg_rsync_comp_porn490w492w(0); + wire_w_lg_nl1101l491w(0) <= nl1101l OR nl1101i; + wire_w_lg_nl110ii479w(0) <= nl110ii OR nl1100O; + wire_w_lg_nl110iO477w(0) <= nl110iO OR nl110il; + wire_w_lg_nl110li481w(0) <= nl110li OR wire_w_lg_w_lg_rsync_comp_porn478w480w(0); + wire_w_lg_nl110lO485w(0) <= nl110lO OR wire_w_lg_nl110ll484w(0); + wire_w_lg_nl110lO470w(0) <= nl110lO OR nl110ll; + wire_w_lg_nl11iiO473w(0) <= nl11iiO OR nl11iil; + wire_w_lg_nl11iOl311w(0) <= nl11iOl OR wire_w_lg_rsync_comp_porn310w(0); + wire_w_lg_nl11l1i307w(0) <= nl11l1i OR wire_w_lg_rsync_comp_porn306w(0); + wire_w_lg_nl11lil298w(0) <= nl11lil OR wire_w_lg_w_lg_rsync_comp_porn294w297w(0); + wire_w_lg_nl11lOi283w(0) <= nl11lOi OR wire_w_lg_rsync_comp_porn282w(0); + wire_w_lg_nl11O0i271w(0) <= nl11O0i OR wire_w_lg_rsync_comp_porn270w(0); + wire_w_lg_nl11O0i319w(0) <= nl11O0i OR nl11O1O; + wire_w_lg_nl11OiO290w(0) <= nl11OiO OR wire_w_lg_w_lg_rsync_comp_porn286w289w(0); + wire_w_lg_nl11OiO262w(0) <= nl11OiO OR nl11Oil; + wire_w_lg_soft_reset8w(0) <= soft_reset OR wire_w_lg_rrxfifo_urst_en7w(0); + wire_w_lg_w_rx_data_rs_range546w549w(0) <= wire_w_rx_data_rs_range546w(0) OR wire_w_lg_w_rx_data_rs_range547w548w(0); + wire_w_lg_w_tenb_data_range597w4919w(0) <= wire_w_tenb_data_range597w(0) XOR wire_w_lg_w_rsync_comp_pat_range4891w4918w(0); + wire_w_lg_w_tenb_data_range597w5017w(0) <= wire_w_tenb_data_range597w(0) XOR wire_w_lg_w_rsync_comp_pat_range4954w4955w(0); + wire_w_lg_w_tenb_data_range597w5453w(0) <= wire_w_tenb_data_range597w(0) XOR wire_w_lg_w_rsync_comp_pat_range5001w5034w(0); + wire_w_lg_w_tenb_data_range597w5569w(0) <= wire_w_tenb_data_range597w(0) XOR wire_w_lg_w_rsync_comp_pat_range5413w5464w(0); + wire_w_lg_w_tenb_data_range597w5082w(0) <= wire_w_tenb_data_range597w(0) XOR wire_w_lg_w_rsync_comp_pat_range5050w5081w(0); + wire_w_lg_w_tenb_data_range597w5149w(0) <= wire_w_tenb_data_range597w(0) XOR wire_w_lg_w_rsync_comp_pat_range5073w5104w(0); + wire_w_lg_w_tenb_data_range597w4947w(0) <= wire_w_tenb_data_range597w(0) XOR wire_w_lg_w_rsync_comp_pat_range4945w4946w(0); + wire_w_lg_w_tenb_data_range588w5373w(0) <= wire_w_tenb_data_range588w(0) XOR wire_w_lg_w_rsync_comp_pat_range4954w4955w(0); + wire_w_lg_w_tenb_data_range588w5674w(0) <= wire_w_tenb_data_range588w(0) XOR wire_w_lg_w_rsync_comp_pat_range5001w5034w(0); + wire_w_lg_w_tenb_data_range588w5736w(0) <= wire_w_tenb_data_range588w(0) XOR wire_w_lg_w_rsync_comp_pat_range5413w5464w(0); + wire_w_lg_w_tenb_data_range588w5487w(0) <= wire_w_tenb_data_range588w(0) XOR wire_w_lg_w_rsync_comp_pat_range5050w5081w(0); + wire_w_lg_w_tenb_data_range588w5607w(0) <= wire_w_tenb_data_range588w(0) XOR wire_w_lg_w_rsync_comp_pat_range5073w5104w(0); + wire_w_lg_w_tenb_data_range588w5299w(0) <= wire_w_tenb_data_range588w(0) XOR wire_w_lg_w_rsync_comp_pat_range4945w4946w(0); + wire_w_lg_w_tenb_data_range587w5375w(0) <= wire_w_tenb_data_range587w(0) XOR wire_w_lg_w_rsync_comp_pat_range4959w4960w(0); + wire_w_lg_w_tenb_data_range587w5676w(0) <= wire_w_tenb_data_range587w(0) XOR wire_w_lg_w_rsync_comp_pat_range5005w5038w(0); + wire_w_lg_w_tenb_data_range587w5738w(0) <= wire_w_tenb_data_range587w(0) XOR wire_w_lg_w_rsync_comp_pat_range5417w5468w(0); + wire_w_lg_w_tenb_data_range587w5489w(0) <= wire_w_tenb_data_range587w(0) XOR wire_w_lg_w_rsync_comp_pat_range5053w5084w(0); + wire_w_lg_w_tenb_data_range587w5609w(0) <= wire_w_tenb_data_range587w(0) XOR wire_w_lg_w_rsync_comp_pat_range5077w5108w(0); + wire_w_lg_w_tenb_data_range587w5301w(0) <= wire_w_tenb_data_range587w(0) XOR wire_w_lg_w_rsync_comp_pat_range4949w4950w(0); + wire_w_lg_w_tenb_data_range586w5304w(0) <= wire_w_tenb_data_range586w(0) XOR wire_w_lg_w_rsync_comp_pat_range4954w4955w(0); + wire_w_lg_w_tenb_data_range586w5378w(0) <= wire_w_tenb_data_range586w(0) XOR wire_w_lg_w_rsync_comp_pat_range4964w4965w(0); + wire_w_lg_w_tenb_data_range586w5679w(0) <= wire_w_tenb_data_range586w(0) XOR wire_w_lg_w_rsync_comp_pat_range5009w5042w(0); + wire_w_lg_w_tenb_data_range586w5741w(0) <= wire_w_tenb_data_range586w(0) XOR wire_w_lg_w_rsync_comp_pat_range5421w5472w(0); + wire_w_lg_w_tenb_data_range586w5492w(0) <= wire_w_tenb_data_range586w(0) XOR wire_w_lg_w_rsync_comp_pat_range5057w5088w(0); + wire_w_lg_w_tenb_data_range586w5612w(0) <= wire_w_tenb_data_range586w(0) XOR wire_w_lg_w_rsync_comp_pat_range5117w5154w(0); + wire_w_lg_w_tenb_data_range585w5307w(0) <= wire_w_tenb_data_range585w(0) XOR wire_w_lg_w_rsync_comp_pat_range4959w4960w(0); + wire_w_lg_w_tenb_data_range585w5381w(0) <= wire_w_tenb_data_range585w(0) XOR wire_w_lg_w_rsync_comp_pat_range4969w4970w(0); + wire_w_lg_w_tenb_data_range585w5682w(0) <= wire_w_tenb_data_range585w(0) XOR wire_w_lg_w_rsync_comp_pat_range5013w5046w(0); + wire_w_lg_w_tenb_data_range585w5744w(0) <= wire_w_tenb_data_range585w(0) XOR wire_w_lg_w_rsync_comp_pat_range5425w5476w(0); + wire_w_lg_w_tenb_data_range585w5495w(0) <= wire_w_tenb_data_range585w(0) XOR wire_w_lg_w_rsync_comp_pat_range5061w5092w(0); + wire_w_lg_w_tenb_data_range585w5615w(0) <= wire_w_tenb_data_range585w(0) XOR wire_w_lg_w_rsync_comp_pat_range5121w5158w(0); + wire_w_lg_w_tenb_data_range584w5310w(0) <= wire_w_tenb_data_range584w(0) XOR wire_w_lg_w_rsync_comp_pat_range4964w4965w(0); + wire_w_lg_w_tenb_data_range584w5384w(0) <= wire_w_tenb_data_range584w(0) XOR wire_w_lg_w_rsync_comp_pat_range4974w4975w(0); + wire_w_lg_w_tenb_data_range584w5685w(0) <= wire_w_tenb_data_range584w(0) XOR wire_w_lg_w_rsync_comp_pat_range5413w5464w(0); + wire_w_lg_w_tenb_data_range584w5747w(0) <= wire_w_tenb_data_range584w(0) XOR wire_w_lg_w_rsync_comp_pat_range5050w5081w(0); + wire_w_lg_w_tenb_data_range584w5498w(0) <= wire_w_tenb_data_range584w(0) XOR wire_w_lg_w_rsync_comp_pat_range5065w5096w(0); + wire_w_lg_w_tenb_data_range584w5618w(0) <= wire_w_tenb_data_range584w(0) XOR wire_w_lg_w_rsync_comp_pat_range5125w5162w(0); + wire_w_lg_w_tenb_data_range583w5313w(0) <= wire_w_tenb_data_range583w(0) XOR wire_w_lg_w_rsync_comp_pat_range4969w4970w(0); + wire_w_lg_w_tenb_data_range583w5387w(0) <= wire_w_tenb_data_range583w(0) XOR wire_w_lg_w_rsync_comp_pat_range4979w4980w(0); + wire_w_lg_w_tenb_data_range583w5688w(0) <= wire_w_tenb_data_range583w(0) XOR wire_w_lg_w_rsync_comp_pat_range5417w5468w(0); + wire_w_lg_w_tenb_data_range583w5750w(0) <= wire_w_tenb_data_range583w(0) XOR wire_w_lg_w_rsync_comp_pat_range5053w5084w(0); + wire_w_lg_w_tenb_data_range583w5501w(0) <= wire_w_tenb_data_range583w(0) XOR wire_w_lg_w_rsync_comp_pat_range5069w5100w(0); + wire_w_lg_w_tenb_data_range583w5621w(0) <= wire_w_tenb_data_range583w(0) XOR wire_w_lg_w_rsync_comp_pat_range5129w5166w(0); + wire_w_lg_w_tenb_data_range582w5316w(0) <= wire_w_tenb_data_range582w(0) XOR wire_w_lg_w_rsync_comp_pat_range4974w4975w(0); + wire_w_lg_w_tenb_data_range582w5390w(0) <= wire_w_tenb_data_range582w(0) XOR wire_w_lg_w_rsync_comp_pat_range5001w5034w(0); + wire_w_lg_w_tenb_data_range582w5691w(0) <= wire_w_tenb_data_range582w(0) XOR wire_w_lg_w_rsync_comp_pat_range5421w5472w(0); + wire_w_lg_w_tenb_data_range582w5753w(0) <= wire_w_tenb_data_range582w(0) XOR wire_w_lg_w_rsync_comp_pat_range5057w5088w(0); + wire_w_lg_w_tenb_data_range582w5504w(0) <= wire_w_tenb_data_range582w(0) XOR wire_w_lg_w_rsync_comp_pat_range5073w5104w(0); + wire_w_lg_w_tenb_data_range582w5624w(0) <= wire_w_tenb_data_range582w(0) XOR wire_w_lg_w_rsync_comp_pat_range5133w5170w(0); + wire_w_lg_w_tenb_data_range581w5319w(0) <= wire_w_tenb_data_range581w(0) XOR wire_w_lg_w_rsync_comp_pat_range4979w4980w(0); + wire_w_lg_w_tenb_data_range581w5393w(0) <= wire_w_tenb_data_range581w(0) XOR wire_w_lg_w_rsync_comp_pat_range5005w5038w(0); + wire_w_lg_w_tenb_data_range581w5694w(0) <= wire_w_tenb_data_range581w(0) XOR wire_w_lg_w_rsync_comp_pat_range5425w5476w(0); + wire_w_lg_w_tenb_data_range581w5756w(0) <= wire_w_tenb_data_range581w(0) XOR wire_w_lg_w_rsync_comp_pat_range5061w5092w(0); + wire_w_lg_w_tenb_data_range581w5507w(0) <= wire_w_tenb_data_range581w(0) XOR wire_w_lg_w_rsync_comp_pat_range5077w5108w(0); + wire_w_lg_w_tenb_data_range581w5627w(0) <= wire_w_tenb_data_range581w(0) XOR wire_w_lg_w_rsync_comp_pat_range5137w5174w(0); + wire_w_lg_w_tenb_data_range331w5396w(0) <= wire_w_tenb_data_range331w(0) XOR wire_w_lg_w_rsync_comp_pat_range5009w5042w(0); + wire_w_lg_w_tenb_data_range331w5759w(0) <= wire_w_tenb_data_range331w(0) XOR wire_w_lg_w_rsync_comp_pat_range5065w5096w(0); + wire_w_lg_w_tenb_data_range331w5630w(0) <= wire_w_tenb_data_range331w(0) XOR wire_w_lg_w_rsync_comp_pat_range5141w5178w(0); + wire_w_lg_w_tenb_data_range580w5399w(0) <= wire_w_tenb_data_range580w(0) XOR wire_w_lg_w_rsync_comp_pat_range5013w5046w(0); + wire_w_lg_w_tenb_data_range580w5762w(0) <= wire_w_tenb_data_range580w(0) XOR wire_w_lg_w_rsync_comp_pat_range5069w5100w(0); + wire_w_lg_w_tenb_data_range580w5633w(0) <= wire_w_tenb_data_range580w(0) XOR wire_w_lg_w_rsync_comp_pat_range5145w5182w(0); + wire_w_lg_w_tenb_data_range596w5019w(0) <= wire_w_tenb_data_range596w(0) XOR wire_w_lg_w_rsync_comp_pat_range4959w4960w(0); + wire_w_lg_w_tenb_data_range596w5455w(0) <= wire_w_tenb_data_range596w(0) XOR wire_w_lg_w_rsync_comp_pat_range5005w5038w(0); + wire_w_lg_w_tenb_data_range596w4922w(0) <= wire_w_tenb_data_range596w(0) XOR wire_w_lg_w_rsync_comp_pat_range4894w4921w(0); + wire_w_lg_w_tenb_data_range596w5571w(0) <= wire_w_tenb_data_range596w(0) XOR wire_w_lg_w_rsync_comp_pat_range5417w5468w(0); + wire_w_lg_w_tenb_data_range596w5085w(0) <= wire_w_tenb_data_range596w(0) XOR wire_w_lg_w_rsync_comp_pat_range5053w5084w(0); + wire_w_lg_w_tenb_data_range596w5151w(0) <= wire_w_tenb_data_range596w(0) XOR wire_w_lg_w_rsync_comp_pat_range5077w5108w(0); + wire_w_lg_w_tenb_data_range596w4951w(0) <= wire_w_tenb_data_range596w(0) XOR wire_w_lg_w_rsync_comp_pat_range4949w4950w(0); + wire_w_lg_w_tenb_data_range595w4956w(0) <= wire_w_tenb_data_range595w(0) XOR wire_w_lg_w_rsync_comp_pat_range4954w4955w(0); + wire_w_lg_w_tenb_data_range595w5022w(0) <= wire_w_tenb_data_range595w(0) XOR wire_w_lg_w_rsync_comp_pat_range4964w4965w(0); + wire_w_lg_w_tenb_data_range595w5458w(0) <= wire_w_tenb_data_range595w(0) XOR wire_w_lg_w_rsync_comp_pat_range5009w5042w(0); + wire_w_lg_w_tenb_data_range595w5574w(0) <= wire_w_tenb_data_range595w(0) XOR wire_w_lg_w_rsync_comp_pat_range5421w5472w(0); + wire_w_lg_w_tenb_data_range595w5089w(0) <= wire_w_tenb_data_range595w(0) XOR wire_w_lg_w_rsync_comp_pat_range5057w5088w(0); + wire_w_lg_w_tenb_data_range595w4926w(0) <= wire_w_tenb_data_range595w(0) XOR wire_w_lg_w_rsync_comp_pat_range4898w4925w(0); + wire_w_lg_w_tenb_data_range595w5155w(0) <= wire_w_tenb_data_range595w(0) XOR wire_w_lg_w_rsync_comp_pat_range5117w5154w(0); + wire_w_lg_w_tenb_data_range594w4961w(0) <= wire_w_tenb_data_range594w(0) XOR wire_w_lg_w_rsync_comp_pat_range4959w4960w(0); + wire_w_lg_w_tenb_data_range594w5025w(0) <= wire_w_tenb_data_range594w(0) XOR wire_w_lg_w_rsync_comp_pat_range4969w4970w(0); + wire_w_lg_w_tenb_data_range594w5461w(0) <= wire_w_tenb_data_range594w(0) XOR wire_w_lg_w_rsync_comp_pat_range5013w5046w(0); + wire_w_lg_w_tenb_data_range594w5577w(0) <= wire_w_tenb_data_range594w(0) XOR wire_w_lg_w_rsync_comp_pat_range5425w5476w(0); + wire_w_lg_w_tenb_data_range594w5093w(0) <= wire_w_tenb_data_range594w(0) XOR wire_w_lg_w_rsync_comp_pat_range5061w5092w(0); + wire_w_lg_w_tenb_data_range594w5159w(0) <= wire_w_tenb_data_range594w(0) XOR wire_w_lg_w_rsync_comp_pat_range5121w5158w(0); + wire_w_lg_w_tenb_data_range594w4930w(0) <= wire_w_tenb_data_range594w(0) XOR wire_w_lg_w_rsync_comp_pat_range4902w4929w(0); + wire_w_lg_w_tenb_data_range593w4966w(0) <= wire_w_tenb_data_range593w(0) XOR wire_w_lg_w_rsync_comp_pat_range4964w4965w(0); + wire_w_lg_w_tenb_data_range593w5028w(0) <= wire_w_tenb_data_range593w(0) XOR wire_w_lg_w_rsync_comp_pat_range4974w4975w(0); + wire_w_lg_w_tenb_data_range593w5465w(0) <= wire_w_tenb_data_range593w(0) XOR wire_w_lg_w_rsync_comp_pat_range5413w5464w(0); + wire_w_lg_w_tenb_data_range593w5580w(0) <= wire_w_tenb_data_range593w(0) XOR wire_w_lg_w_rsync_comp_pat_range5050w5081w(0); + wire_w_lg_w_tenb_data_range593w5097w(0) <= wire_w_tenb_data_range593w(0) XOR wire_w_lg_w_rsync_comp_pat_range5065w5096w(0); + wire_w_lg_w_tenb_data_range593w5163w(0) <= wire_w_tenb_data_range593w(0) XOR wire_w_lg_w_rsync_comp_pat_range5125w5162w(0); + wire_w_lg_w_tenb_data_range593w4934w(0) <= wire_w_tenb_data_range593w(0) XOR wire_w_lg_w_rsync_comp_pat_range4906w4933w(0); + wire_w_lg_w_tenb_data_range592w4971w(0) <= wire_w_tenb_data_range592w(0) XOR wire_w_lg_w_rsync_comp_pat_range4969w4970w(0); + wire_w_lg_w_tenb_data_range592w5031w(0) <= wire_w_tenb_data_range592w(0) XOR wire_w_lg_w_rsync_comp_pat_range4979w4980w(0); + wire_w_lg_w_tenb_data_range592w5469w(0) <= wire_w_tenb_data_range592w(0) XOR wire_w_lg_w_rsync_comp_pat_range5417w5468w(0); + wire_w_lg_w_tenb_data_range592w5583w(0) <= wire_w_tenb_data_range592w(0) XOR wire_w_lg_w_rsync_comp_pat_range5053w5084w(0); + wire_w_lg_w_tenb_data_range592w5101w(0) <= wire_w_tenb_data_range592w(0) XOR wire_w_lg_w_rsync_comp_pat_range5069w5100w(0); + wire_w_lg_w_tenb_data_range592w5167w(0) <= wire_w_tenb_data_range592w(0) XOR wire_w_lg_w_rsync_comp_pat_range5129w5166w(0); + wire_w_lg_w_tenb_data_range592w4938w(0) <= wire_w_tenb_data_range592w(0) XOR wire_w_lg_w_rsync_comp_pat_range4910w4937w(0); + wire_w_lg_w_tenb_data_range591w4976w(0) <= wire_w_tenb_data_range591w(0) XOR wire_w_lg_w_rsync_comp_pat_range4974w4975w(0); + wire_w_lg_w_tenb_data_range591w5035w(0) <= wire_w_tenb_data_range591w(0) XOR wire_w_lg_w_rsync_comp_pat_range5001w5034w(0); + wire_w_lg_w_tenb_data_range591w5473w(0) <= wire_w_tenb_data_range591w(0) XOR wire_w_lg_w_rsync_comp_pat_range5421w5472w(0); + wire_w_lg_w_tenb_data_range591w5586w(0) <= wire_w_tenb_data_range591w(0) XOR wire_w_lg_w_rsync_comp_pat_range5057w5088w(0); + wire_w_lg_w_tenb_data_range591w5105w(0) <= wire_w_tenb_data_range591w(0) XOR wire_w_lg_w_rsync_comp_pat_range5073w5104w(0); + wire_w_lg_w_tenb_data_range591w5171w(0) <= wire_w_tenb_data_range591w(0) XOR wire_w_lg_w_rsync_comp_pat_range5133w5170w(0); + wire_w_lg_w_tenb_data_range591w4942w(0) <= wire_w_tenb_data_range591w(0) XOR wire_w_lg_w_rsync_comp_pat_range4914w4941w(0); + wire_w_lg_w_tenb_data_range590w4981w(0) <= wire_w_tenb_data_range590w(0) XOR wire_w_lg_w_rsync_comp_pat_range4979w4980w(0); + wire_w_lg_w_tenb_data_range590w5039w(0) <= wire_w_tenb_data_range590w(0) XOR wire_w_lg_w_rsync_comp_pat_range5005w5038w(0); + wire_w_lg_w_tenb_data_range590w5477w(0) <= wire_w_tenb_data_range590w(0) XOR wire_w_lg_w_rsync_comp_pat_range5425w5476w(0); + wire_w_lg_w_tenb_data_range590w5589w(0) <= wire_w_tenb_data_range590w(0) XOR wire_w_lg_w_rsync_comp_pat_range5061w5092w(0); + wire_w_lg_w_tenb_data_range590w5109w(0) <= wire_w_tenb_data_range590w(0) XOR wire_w_lg_w_rsync_comp_pat_range5077w5108w(0); + wire_w_lg_w_tenb_data_range590w5175w(0) <= wire_w_tenb_data_range590w(0) XOR wire_w_lg_w_rsync_comp_pat_range5137w5174w(0); + wire_w_lg_w_tenb_data_range590w5296w(0) <= wire_w_tenb_data_range590w(0) XOR wire_w_lg_w_rsync_comp_pat_range5249w5253w(0); + wire_w_lg_w_tenb_data_range98w5043w(0) <= wire_w_tenb_data_range98w(0) XOR wire_w_lg_w_rsync_comp_pat_range5009w5042w(0); + wire_w_lg_w_tenb_data_range98w5592w(0) <= wire_w_tenb_data_range98w(0) XOR wire_w_lg_w_rsync_comp_pat_range5065w5096w(0); + wire_w_lg_w_tenb_data_range98w5179w(0) <= wire_w_tenb_data_range98w(0) XOR wire_w_lg_w_rsync_comp_pat_range5141w5178w(0); + wire_w_lg_w_tenb_data_range98w5358w(0) <= wire_w_tenb_data_range98w(0) XOR wire_w_lg_w_rsync_comp_pat_range4945w4946w(0); + wire_w_lg_w_tenb_data_range589w5047w(0) <= wire_w_tenb_data_range589w(0) XOR wire_w_lg_w_rsync_comp_pat_range5013w5046w(0); + wire_w_lg_w_tenb_data_range589w5595w(0) <= wire_w_tenb_data_range589w(0) XOR wire_w_lg_w_rsync_comp_pat_range5069w5100w(0); + wire_w_lg_w_tenb_data_range589w5183w(0) <= wire_w_tenb_data_range589w(0) XOR wire_w_lg_w_rsync_comp_pat_range5145w5182w(0); + wire_w_lg_w_tenb_data_range589w5361w(0) <= wire_w_tenb_data_range589w(0) XOR wire_w_lg_w_rsync_comp_pat_range4949w4950w(0); + bytord_valid_out <= wire_nlOll_dataout; + niOlO0i <= ((wire_nli1ii_w_lg_niiOii3801w(0) OR niiO0O) OR niiO0l); + niOlO0l <= (wire_ni1lli_w_lg_dataout679w(0) OR wire_ni1lll_w_lg_dataout3799w(0)); + niOlO0O <= (wire_nli1ii_w_lg_niiO0O6509w(0) AND wire_nli1ii_w_lg_niiO0l6511w(0)); + niOlO1l <= (wire_nl1l1O_dataout AND niiO0i); + niOlO1O <= (n1i0O AND (wire_nl1l1O_dataout AND wire_ni1liO_dataout)); + niOlOii <= (niiO0O AND wire_nli1ii_w_lg_niiO0l6511w(0)); + niOlOil <= (wire_ni1lli_dataout AND wire_ni1liO_w_lg_dataout678w(0)); + niOlOiO <= ((wire_n0l1iO_o(6) OR wire_n0l1iO_o(4)) OR wire_n0l1iO_o(2)); + niOlOli <= ((((((wire_n0l0lO_o(14) OR wire_n0l0lO_o(12)) OR wire_n0l0lO_o(10)) OR wire_n0l0lO_o(8)) OR wire_n0l0lO_o(6)) OR wire_n0l0lO_o(4)) OR wire_n0l0lO_o(2)); + niOlOll <= (niOlOOi OR niOlOlO); + niOlOlO <= ((((((((((NOT (niliOi XOR (NOT rbytordpat(0)))) AND (NOT (niliOl XOR (NOT rbytordpat(1))))) AND (NOT (niliOO XOR (NOT rbytordpat(2))))) AND (NOT (nill1i XOR (NOT rbytordpat(3))))) AND (NOT (nill1l XOR (NOT rbytordpat(4))))) AND (NOT (nill1O XOR (NOT rbytordpat(5))))) AND (NOT (nill0i XOR (NOT rbytordpat(6))))) AND (NOT (nill0l XOR (NOT rbytordpat(7))))) AND (NOT (nill0O XOR (NOT rbytordpat(8))))) AND (NOT (nillii XOR (NOT rbytordpat(9))))); + niOlOOi <= ((((((((((NOT (niliOi XOR rbytordpat(0))) AND (NOT (niliOl XOR rbytordpat(1)))) AND (NOT (niliOO XOR rbytordpat(2)))) AND (NOT (nill1i XOR rbytordpat(3)))) AND (NOT (nill1l XOR rbytordpat(4)))) AND (NOT (nill1O XOR rbytordpat(5)))) AND (NOT (nill0i XOR rbytordpat(6)))) AND (NOT (nill0l XOR rbytordpat(7)))) AND (NOT (nill0O XOR rbytordpat(8)))) AND (NOT (nillii XOR rbytordpat(9)))); + niOlOOl <= ((((((((((NOT (nillOl XOR (NOT rbytordpat(10)))) AND (NOT (nillOO XOR (NOT rbytordpat(11))))) AND (NOT (nilO1i XOR (NOT rbytordpat(12))))) AND (NOT (nilO1l XOR (NOT rbytordpat(13))))) AND (NOT (nilO1O XOR (NOT rbytordpat(14))))) AND (NOT (nilO0i XOR (NOT rbytordpat(15))))) AND (NOT (nilO0l XOR (NOT rbytordpat(16))))) AND (NOT (nilO0O XOR (NOT rbytordpat(17))))) AND (NOT (nilOii XOR (NOT rbytordpat(18))))) AND (NOT (nilOil XOR (NOT rbytordpat(19))))); + niOlOOO <= ((((((((((NOT (nillOl XOR rbytordpat(10))) AND (NOT (nillOO XOR rbytordpat(11)))) AND (NOT (nilO1i XOR rbytordpat(12)))) AND (NOT (nilO1l XOR rbytordpat(13)))) AND (NOT (nilO1O XOR rbytordpat(14)))) AND (NOT (nilO0i XOR rbytordpat(15)))) AND (NOT (nilO0l XOR rbytordpat(16)))) AND (NOT (nilO0O XOR rbytordpat(17)))) AND (NOT (nilOii XOR rbytordpat(18)))) AND (NOT (nilOil XOR rbytordpat(19)))); + niOO00i <= ((((((((NOT (niliOi XOR rbytordpat(0))) AND (NOT (niliOl XOR rbytordpat(1)))) AND (NOT (niliOO XOR rbytordpat(2)))) AND (NOT (nill1i XOR rbytordpat(3)))) AND (NOT (nill1l XOR rbytordpat(4)))) AND (NOT (nill1O XOR rbytordpat(5)))) AND (NOT (nill0i XOR rbytordpat(6)))) AND (NOT (nill0l XOR rbytordpat(7)))); + niOO00l <= ((((((((NOT (nillOl XOR rbytordpat(10))) AND (NOT (nillOO XOR rbytordpat(11)))) AND (NOT (nilO1i XOR rbytordpat(12)))) AND (NOT (nilO1l XOR rbytordpat(13)))) AND (NOT (nilO1O XOR rbytordpat(14)))) AND (NOT (nilO0i XOR rbytordpat(15)))) AND (NOT (nilO0l XOR rbytordpat(16)))) AND (NOT (nilO0O XOR rbytordpat(17)))); + niOO00O <= ((((((((NOT (nillOl XOR rbytordpat(0))) AND (NOT (nillOO XOR rbytordpat(1)))) AND (NOT (nilO1i XOR rbytordpat(2)))) AND (NOT (nilO1l XOR rbytordpat(3)))) AND (NOT (nilO1O XOR rbytordpat(4)))) AND (NOT (nilO0i XOR rbytordpat(5)))) AND (NOT (nilO0l XOR rbytordpat(6)))) AND (NOT (nilO0O XOR rbytordpat(7)))); + niOO01i <= (((((((((NOT (nilOOO XOR rbytordpat(10))) AND (NOT (niO11i XOR rbytordpat(11)))) AND (NOT (niO11l XOR rbytordpat(12)))) AND (NOT (niO11O XOR rbytordpat(13)))) AND (NOT (niO10i XOR rbytordpat(14)))) AND (NOT (niO10l XOR rbytordpat(15)))) AND (NOT (niO10O XOR rbytordpat(16)))) AND (NOT (niO1ii XOR rbytordpat(17)))) AND (NOT (niO1il XOR rbytordpat(18)))); + niOO01l <= (((((((((NOT (niO01i XOR rbytordpat(10))) AND (NOT (niO01l XOR rbytordpat(11)))) AND (NOT (niO01O XOR rbytordpat(12)))) AND (NOT (niO00i XOR rbytordpat(13)))) AND (NOT (niO00l XOR rbytordpat(14)))) AND (NOT (niO00O XOR rbytordpat(15)))) AND (NOT (niO0ii XOR rbytordpat(16)))) AND (NOT (niO0il XOR rbytordpat(17)))) AND (NOT (niO0iO XOR rbytordpat(18)))); + niOO01O <= (((((((((NOT (wire_niOlOl_dataout XOR rbytordpat(10))) AND (NOT (wire_niOlOO_dataout XOR rbytordpat(11)))) AND (NOT (wire_niOO1i_dataout XOR rbytordpat(12)))) AND (NOT (wire_niOO1l_dataout XOR rbytordpat(13)))) AND (NOT (wire_niOO1O_dataout XOR rbytordpat(14)))) AND (NOT (wire_niOO0i_dataout XOR rbytordpat(15)))) AND (NOT (wire_niOO0l_dataout XOR rbytordpat(16)))) AND (NOT (wire_niOO0O_dataout XOR rbytordpat(17)))) AND (NOT (wire_niOOii_dataout XOR rbytordpat(18)))); + niOO0ii <= ((((((((NOT (nilOOO XOR rbytordpat(10))) AND (NOT (niO11i XOR rbytordpat(11)))) AND (NOT (niO11l XOR rbytordpat(12)))) AND (NOT (niO11O XOR rbytordpat(13)))) AND (NOT (niO10i XOR rbytordpat(14)))) AND (NOT (niO10l XOR rbytordpat(15)))) AND (NOT (niO10O XOR rbytordpat(16)))) AND (NOT (niO1ii XOR rbytordpat(17)))); + niOO0il <= ((((((((NOT (niO01i XOR rbytordpat(10))) AND (NOT (niO01l XOR rbytordpat(11)))) AND (NOT (niO01O XOR rbytordpat(12)))) AND (NOT (niO00i XOR rbytordpat(13)))) AND (NOT (niO00l XOR rbytordpat(14)))) AND (NOT (niO00O XOR rbytordpat(15)))) AND (NOT (niO0ii XOR rbytordpat(16)))) AND (NOT (niO0il XOR rbytordpat(17)))); + niOO0iO <= ((((((((NOT (wire_niOlOl_dataout XOR rbytordpat(10))) AND (NOT (wire_niOlOO_dataout XOR rbytordpat(11)))) AND (NOT (wire_niOO1i_dataout XOR rbytordpat(12)))) AND (NOT (wire_niOO1l_dataout XOR rbytordpat(13)))) AND (NOT (wire_niOO1O_dataout XOR rbytordpat(14)))) AND (NOT (wire_niOO0i_dataout XOR rbytordpat(15)))) AND (NOT (wire_niOO0l_dataout XOR rbytordpat(16)))) AND (NOT (wire_niOO0O_dataout XOR rbytordpat(17)))); + niOO0li <= ((((((((((NOT (niO01i XOR (NOT rbytordpat(0)))) AND (NOT (niO01l XOR (NOT rbytordpat(1))))) AND (NOT (niO01O XOR (NOT rbytordpat(2))))) AND (NOT (niO00i XOR (NOT rbytordpat(3))))) AND (NOT (niO00l XOR (NOT rbytordpat(4))))) AND (NOT (niO00O XOR (NOT rbytordpat(5))))) AND (NOT (niO0ii XOR (NOT rbytordpat(6))))) AND (NOT (niO0il XOR (NOT rbytordpat(7))))) AND (NOT (niO0iO XOR (NOT rbytordpat(8))))) AND (NOT (niO0li XOR (NOT rbytordpat(9))))); + niOO0ll <= ((((((((((NOT (niO01i XOR rbytordpat(0))) AND (NOT (niO01l XOR rbytordpat(1)))) AND (NOT (niO01O XOR rbytordpat(2)))) AND (NOT (niO00i XOR rbytordpat(3)))) AND (NOT (niO00l XOR rbytordpat(4)))) AND (NOT (niO00O XOR rbytordpat(5)))) AND (NOT (niO0ii XOR rbytordpat(6)))) AND (NOT (niO0il XOR rbytordpat(7)))) AND (NOT (niO0iO XOR rbytordpat(8)))) AND (NOT (niO0li XOR rbytordpat(9)))); + niOO0lO <= ((((((((((NOT (nilOOO XOR (NOT rbytordpat(0)))) AND (NOT (niO11i XOR (NOT rbytordpat(1))))) AND (NOT (niO11l XOR (NOT rbytordpat(2))))) AND (NOT (niO11O XOR (NOT rbytordpat(3))))) AND (NOT (niO10i XOR (NOT rbytordpat(4))))) AND (NOT (niO10l XOR (NOT rbytordpat(5))))) AND (NOT (niO10O XOR (NOT rbytordpat(6))))) AND (NOT (niO1ii XOR (NOT rbytordpat(7))))) AND (NOT (niO1il XOR (NOT rbytordpat(8))))) AND (NOT (niO1iO XOR (NOT rbytordpat(9))))); + niOO0Oi <= ((((((((((NOT (nilOOO XOR rbytordpat(0))) AND (NOT (niO11i XOR rbytordpat(1)))) AND (NOT (niO11l XOR rbytordpat(2)))) AND (NOT (niO11O XOR rbytordpat(3)))) AND (NOT (niO10i XOR rbytordpat(4)))) AND (NOT (niO10l XOR rbytordpat(5)))) AND (NOT (niO10O XOR rbytordpat(6)))) AND (NOT (niO1ii XOR rbytordpat(7)))) AND (NOT (niO1il XOR rbytordpat(8)))) AND (NOT (niO1iO XOR rbytordpat(9)))); + niOO0Ol <= (niOOi1l OR niOOi1i); + niOO0OO <= (wire_w_lg_rbytordplden683w(0) OR (wire_w_lg_niOOi1l741w(0) AND wire_w_lg_niOOi1i742w(0))); + niOO10i <= (niOO10O OR niOO10l); + niOO10l <= ((((((((((NOT (nilOOO XOR (NOT rbytordpat(10)))) AND (NOT (niO11i XOR (NOT rbytordpat(11))))) AND (NOT (niO11l XOR (NOT rbytordpat(12))))) AND (NOT (niO11O XOR (NOT rbytordpat(13))))) AND (NOT (niO10i XOR (NOT rbytordpat(14))))) AND (NOT (niO10l XOR (NOT rbytordpat(15))))) AND (NOT (niO10O XOR (NOT rbytordpat(16))))) AND (NOT (niO1ii XOR (NOT rbytordpat(17))))) AND (NOT (niO1il XOR (NOT rbytordpat(18))))) AND (NOT (niO1iO XOR (NOT rbytordpat(19))))); + niOO10O <= ((((((((((NOT (nilOOO XOR rbytordpat(10))) AND (NOT (niO11i XOR rbytordpat(11)))) AND (NOT (niO11l XOR rbytordpat(12)))) AND (NOT (niO11O XOR rbytordpat(13)))) AND (NOT (niO10i XOR rbytordpat(14)))) AND (NOT (niO10l XOR rbytordpat(15)))) AND (NOT (niO10O XOR rbytordpat(16)))) AND (NOT (niO1ii XOR rbytordpat(17)))) AND (NOT (niO1il XOR rbytordpat(18)))) AND (NOT (niO1iO XOR rbytordpat(19)))); + niOO11i <= (niOO11O OR niOO11l); + niOO11l <= ((((((((((NOT (nillOl XOR (NOT rbytordpat(0)))) AND (NOT (nillOO XOR (NOT rbytordpat(1))))) AND (NOT (nilO1i XOR (NOT rbytordpat(2))))) AND (NOT (nilO1l XOR (NOT rbytordpat(3))))) AND (NOT (nilO1O XOR (NOT rbytordpat(4))))) AND (NOT (nilO0i XOR (NOT rbytordpat(5))))) AND (NOT (nilO0l XOR (NOT rbytordpat(6))))) AND (NOT (nilO0O XOR (NOT rbytordpat(7))))) AND (NOT (nilOii XOR (NOT rbytordpat(8))))) AND (NOT (nilOil XOR (NOT rbytordpat(9))))); + niOO11O <= ((((((((((NOT (nillOl XOR rbytordpat(0))) AND (NOT (nillOO XOR rbytordpat(1)))) AND (NOT (nilO1i XOR rbytordpat(2)))) AND (NOT (nilO1l XOR rbytordpat(3)))) AND (NOT (nilO1O XOR rbytordpat(4)))) AND (NOT (nilO0i XOR rbytordpat(5)))) AND (NOT (nilO0l XOR rbytordpat(6)))) AND (NOT (nilO0O XOR rbytordpat(7)))) AND (NOT (nilOii XOR rbytordpat(8)))) AND (NOT (nilOil XOR rbytordpat(9)))); + niOO1ii <= (niOO0Oi OR niOO0lO); + niOO1il <= ((((((((((NOT (niO01i XOR (NOT rbytordpat(10)))) AND (NOT (niO01l XOR (NOT rbytordpat(11))))) AND (NOT (niO01O XOR (NOT rbytordpat(12))))) AND (NOT (niO00i XOR (NOT rbytordpat(13))))) AND (NOT (niO00l XOR (NOT rbytordpat(14))))) AND (NOT (niO00O XOR (NOT rbytordpat(15))))) AND (NOT (niO0ii XOR (NOT rbytordpat(16))))) AND (NOT (niO0il XOR (NOT rbytordpat(17))))) AND (NOT (niO0iO XOR (NOT rbytordpat(18))))) AND (NOT (niO0li XOR (NOT rbytordpat(19))))); + niOO1iO <= ((((((((((NOT (niO01i XOR rbytordpat(10))) AND (NOT (niO01l XOR rbytordpat(11)))) AND (NOT (niO01O XOR rbytordpat(12)))) AND (NOT (niO00i XOR rbytordpat(13)))) AND (NOT (niO00l XOR rbytordpat(14)))) AND (NOT (niO00O XOR rbytordpat(15)))) AND (NOT (niO0ii XOR rbytordpat(16)))) AND (NOT (niO0il XOR rbytordpat(17)))) AND (NOT (niO0iO XOR rbytordpat(18)))) AND (NOT (niO0li XOR rbytordpat(19)))); + niOO1li <= (niOO1lO OR niOO1ll); + niOO1ll <= ((((((((((NOT (wire_niOlOl_dataout XOR (NOT rbytordpat(10)))) AND (NOT (wire_niOlOO_dataout XOR (NOT rbytordpat(11))))) AND (NOT (wire_niOO1i_dataout XOR (NOT rbytordpat(12))))) AND (NOT (wire_niOO1l_dataout XOR (NOT rbytordpat(13))))) AND (NOT (wire_niOO1O_dataout XOR (NOT rbytordpat(14))))) AND (NOT (wire_niOO0i_dataout XOR (NOT rbytordpat(15))))) AND (NOT (wire_niOO0l_dataout XOR (NOT rbytordpat(16))))) AND (NOT (wire_niOO0O_dataout XOR (NOT rbytordpat(17))))) AND (NOT (wire_niOOii_dataout XOR (NOT rbytordpat(18))))) AND (NOT (wire_niOOil_dataout XOR (NOT rbytordpat(19))))); + niOO1lO <= ((((((((((NOT (wire_niOlOl_dataout XOR rbytordpat(10))) AND (NOT (wire_niOlOO_dataout XOR rbytordpat(11)))) AND (NOT (wire_niOO1i_dataout XOR rbytordpat(12)))) AND (NOT (wire_niOO1l_dataout XOR rbytordpat(13)))) AND (NOT (wire_niOO1O_dataout XOR rbytordpat(14)))) AND (NOT (wire_niOO0i_dataout XOR rbytordpat(15)))) AND (NOT (wire_niOO0l_dataout XOR rbytordpat(16)))) AND (NOT (wire_niOO0O_dataout XOR rbytordpat(17)))) AND (NOT (wire_niOOii_dataout XOR rbytordpat(18)))) AND (NOT (wire_niOOil_dataout XOR rbytordpat(19)))); + niOO1Oi <= (((((((((NOT (niliOi XOR rbytordpat(0))) AND (NOT (niliOl XOR rbytordpat(1)))) AND (NOT (niliOO XOR rbytordpat(2)))) AND (NOT (nill1i XOR rbytordpat(3)))) AND (NOT (nill1l XOR rbytordpat(4)))) AND (NOT (nill1O XOR rbytordpat(5)))) AND (NOT (nill0i XOR rbytordpat(6)))) AND (NOT (nill0l XOR rbytordpat(7)))) AND (NOT (nill0O XOR rbytordpat(8)))); + niOO1Ol <= (((((((((NOT (nillOl XOR rbytordpat(10))) AND (NOT (nillOO XOR rbytordpat(11)))) AND (NOT (nilO1i XOR rbytordpat(12)))) AND (NOT (nilO1l XOR rbytordpat(13)))) AND (NOT (nilO1O XOR rbytordpat(14)))) AND (NOT (nilO0i XOR rbytordpat(15)))) AND (NOT (nilO0l XOR rbytordpat(16)))) AND (NOT (nilO0O XOR rbytordpat(17)))) AND (NOT (nilOii XOR rbytordpat(18)))); + niOO1OO <= (((((((((NOT (nillOl XOR rbytordpat(0))) AND (NOT (nillOO XOR rbytordpat(1)))) AND (NOT (nilO1i XOR rbytordpat(2)))) AND (NOT (nilO1l XOR rbytordpat(3)))) AND (NOT (nilO1O XOR rbytordpat(4)))) AND (NOT (nilO0i XOR rbytordpat(5)))) AND (NOT (nilO0l XOR rbytordpat(6)))) AND (NOT (nilO0O XOR rbytordpat(7)))) AND (NOT (nilOii XOR rbytordpat(8)))); + niOOi0i <= ((((((((((NOT (wire_niOOOO_dataout XOR rbytordpat(0))) AND (NOT (rbytordpat(1) XOR wire_nl111i_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl111l_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl111O_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl110i_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl110l_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl110O_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl11ii_dataout))) AND (NOT (rbytordpat(8) XOR wire_nl11il_dataout))) AND (NOT (rbytordpat(9) XOR wire_nl11iO_dataout))); + niOOi0l <= (niOOiiO OR niOOiil); + niOOi0O <= ((((((((((NOT ((NOT rbytordpat(0)) XOR wire_nl1i1l_dataout)) AND (NOT ((NOT rbytordpat(1)) XOR wire_nl1i1O_dataout))) AND (NOT ((NOT rbytordpat(2)) XOR wire_nl1i0i_dataout))) AND (NOT ((NOT rbytordpat(3)) XOR wire_nl1i0l_dataout))) AND (NOT ((NOT rbytordpat(4)) XOR wire_nl1i0O_dataout))) AND (NOT ((NOT rbytordpat(5)) XOR wire_nl1iii_dataout))) AND (NOT ((NOT rbytordpat(6)) XOR wire_nl1iil_dataout))) AND (NOT ((NOT rbytordpat(7)) XOR wire_nl1iiO_dataout))) AND (NOT ((NOT rbytordpat(8)) XOR wire_nl1ili_dataout))) AND (NOT ((NOT rbytordpat(9)) XOR wire_nl1ill_dataout))); + niOOi1i <= ((((((((((NOT (wire_niOlOl_dataout XOR (NOT rbytordpat(0)))) AND (NOT (wire_niOlOO_dataout XOR (NOT rbytordpat(1))))) AND (NOT (wire_niOO1i_dataout XOR (NOT rbytordpat(2))))) AND (NOT (wire_niOO1l_dataout XOR (NOT rbytordpat(3))))) AND (NOT (wire_niOO1O_dataout XOR (NOT rbytordpat(4))))) AND (NOT (wire_niOO0i_dataout XOR (NOT rbytordpat(5))))) AND (NOT (wire_niOO0l_dataout XOR (NOT rbytordpat(6))))) AND (NOT (wire_niOO0O_dataout XOR (NOT rbytordpat(7))))) AND (NOT (wire_niOOii_dataout XOR (NOT rbytordpat(8))))) AND (NOT (wire_niOOil_dataout XOR (NOT rbytordpat(9))))); + niOOi1l <= ((((((((((NOT (wire_niOlOl_dataout XOR rbytordpat(0))) AND (NOT (wire_niOlOO_dataout XOR rbytordpat(1)))) AND (NOT (wire_niOO1i_dataout XOR rbytordpat(2)))) AND (NOT (wire_niOO1l_dataout XOR rbytordpat(3)))) AND (NOT (wire_niOO1O_dataout XOR rbytordpat(4)))) AND (NOT (wire_niOO0i_dataout XOR rbytordpat(5)))) AND (NOT (wire_niOO0l_dataout XOR rbytordpat(6)))) AND (NOT (wire_niOO0O_dataout XOR rbytordpat(7)))) AND (NOT (wire_niOOii_dataout XOR rbytordpat(8)))) AND (NOT (wire_niOOil_dataout XOR rbytordpat(9)))); + niOOi1O <= ((((((((((NOT (wire_niOOOO_dataout XOR (NOT rbytordpat(0)))) AND (NOT ((NOT rbytordpat(1)) XOR wire_nl111i_dataout))) AND (NOT ((NOT rbytordpat(2)) XOR wire_nl111l_dataout))) AND (NOT ((NOT rbytordpat(3)) XOR wire_nl111O_dataout))) AND (NOT ((NOT rbytordpat(4)) XOR wire_nl110i_dataout))) AND (NOT ((NOT rbytordpat(5)) XOR wire_nl110l_dataout))) AND (NOT ((NOT rbytordpat(6)) XOR wire_nl110O_dataout))) AND (NOT ((NOT rbytordpat(7)) XOR wire_nl11ii_dataout))) AND (NOT ((NOT rbytordpat(8)) XOR wire_nl11il_dataout))) AND (NOT ((NOT rbytordpat(9)) XOR wire_nl11iO_dataout))); + niOOiii <= ((((((((((NOT (rbytordpat(0) XOR wire_nl1i1l_dataout)) AND (NOT (rbytordpat(1) XOR wire_nl1i1O_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl1i0i_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl1i0l_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl1i0O_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl1iii_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl1iil_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl1iiO_dataout))) AND (NOT (rbytordpat(8) XOR wire_nl1ili_dataout))) AND (NOT (rbytordpat(9) XOR wire_nl1ill_dataout))); + niOOiil <= ((((((((((NOT ((NOT rbytordpat(0)) XOR wire_nl101i_dataout)) AND (NOT ((NOT rbytordpat(1)) XOR wire_nl101l_dataout))) AND (NOT ((NOT rbytordpat(2)) XOR wire_nl101O_dataout))) AND (NOT ((NOT rbytordpat(3)) XOR wire_nl100i_dataout))) AND (NOT ((NOT rbytordpat(4)) XOR wire_nl100l_dataout))) AND (NOT ((NOT rbytordpat(5)) XOR wire_nl100O_dataout))) AND (NOT ((NOT rbytordpat(6)) XOR wire_nl10ii_dataout))) AND (NOT ((NOT rbytordpat(7)) XOR wire_nl10il_dataout))) AND (NOT ((NOT rbytordpat(8)) XOR wire_nl10iO_dataout))) AND (NOT ((NOT rbytordpat(9)) XOR wire_nl10li_dataout))); + niOOiiO <= ((((((((((NOT (rbytordpat(0) XOR wire_nl101i_dataout)) AND (NOT (rbytordpat(1) XOR wire_nl101l_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl101O_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl100i_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl100l_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl100O_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl10ii_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl10il_dataout))) AND (NOT (rbytordpat(8) XOR wire_nl10iO_dataout))) AND (NOT (rbytordpat(9) XOR wire_nl10li_dataout))); + niOOili <= (((((((((NOT (niO01i XOR rbytordpat(0))) AND (NOT (niO01l XOR rbytordpat(1)))) AND (NOT (niO01O XOR rbytordpat(2)))) AND (NOT (niO00i XOR rbytordpat(3)))) AND (NOT (niO00l XOR rbytordpat(4)))) AND (NOT (niO00O XOR rbytordpat(5)))) AND (NOT (niO0ii XOR rbytordpat(6)))) AND (NOT (niO0il XOR rbytordpat(7)))) AND (NOT (niO0iO XOR rbytordpat(8)))); + niOOill <= (((((((((NOT (nilOOO XOR rbytordpat(0))) AND (NOT (niO11i XOR rbytordpat(1)))) AND (NOT (niO11l XOR rbytordpat(2)))) AND (NOT (niO11O XOR rbytordpat(3)))) AND (NOT (niO10i XOR rbytordpat(4)))) AND (NOT (niO10l XOR rbytordpat(5)))) AND (NOT (niO10O XOR rbytordpat(6)))) AND (NOT (niO1ii XOR rbytordpat(7)))) AND (NOT (niO1il XOR rbytordpat(8)))); + niOOilO <= (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOiOi714w(0)); + niOOiOi <= (((((((((NOT (wire_niOlOl_dataout XOR rbytordpat(0))) AND (NOT (wire_niOlOO_dataout XOR rbytordpat(1)))) AND (NOT (wire_niOO1i_dataout XOR rbytordpat(2)))) AND (NOT (wire_niOO1l_dataout XOR rbytordpat(3)))) AND (NOT (wire_niOO1O_dataout XOR rbytordpat(4)))) AND (NOT (wire_niOO0i_dataout XOR rbytordpat(5)))) AND (NOT (wire_niOO0l_dataout XOR rbytordpat(6)))) AND (NOT (wire_niOO0O_dataout XOR rbytordpat(7)))) AND (NOT (wire_niOOii_dataout XOR rbytordpat(8)))); + niOOiOl <= (((((((((NOT (wire_niOOOO_dataout XOR rbytordpat(0))) AND (NOT (rbytordpat(1) XOR wire_nl111i_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl111l_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl111O_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl110i_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl110l_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl110O_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl11ii_dataout))) AND (NOT (rbytordpat(8) XOR wire_nl11il_dataout))); + niOOiOO <= (((((((((NOT (rbytordpat(0) XOR wire_nl1i1l_dataout)) AND (NOT (rbytordpat(1) XOR wire_nl1i1O_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl1i0i_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl1i0l_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl1i0O_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl1iii_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl1iil_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl1iiO_dataout))) AND (NOT (rbytordpat(8) XOR wire_nl1ili_dataout))); + niOOl0i <= (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOl0l692w(0)); + niOOl0l <= ((((((((NOT (wire_niOlOl_dataout XOR rbytordpat(0))) AND (NOT (wire_niOlOO_dataout XOR rbytordpat(1)))) AND (NOT (wire_niOO1i_dataout XOR rbytordpat(2)))) AND (NOT (wire_niOO1l_dataout XOR rbytordpat(3)))) AND (NOT (wire_niOO1O_dataout XOR rbytordpat(4)))) AND (NOT (wire_niOO0i_dataout XOR rbytordpat(5)))) AND (NOT (wire_niOO0l_dataout XOR rbytordpat(6)))) AND (NOT (wire_niOO0O_dataout XOR rbytordpat(7)))); + niOOl0O <= ((((((((NOT (wire_niOOOO_dataout XOR rbytordpat(0))) AND (NOT (rbytordpat(1) XOR wire_nl111i_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl111l_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl111O_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl110i_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl110l_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl110O_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl11ii_dataout))); + niOOl1i <= (((((((((NOT (rbytordpat(0) XOR wire_nl101i_dataout)) AND (NOT (rbytordpat(1) XOR wire_nl101l_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl101O_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl100i_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl100l_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl100O_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl10ii_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl10il_dataout))) AND (NOT (rbytordpat(8) XOR wire_nl10iO_dataout))); + niOOl1l <= ((((((((NOT (niO01i XOR rbytordpat(0))) AND (NOT (niO01l XOR rbytordpat(1)))) AND (NOT (niO01O XOR rbytordpat(2)))) AND (NOT (niO00i XOR rbytordpat(3)))) AND (NOT (niO00l XOR rbytordpat(4)))) AND (NOT (niO00O XOR rbytordpat(5)))) AND (NOT (niO0ii XOR rbytordpat(6)))) AND (NOT (niO0il XOR rbytordpat(7)))); + niOOl1O <= ((((((((NOT (nilOOO XOR rbytordpat(0))) AND (NOT (niO11i XOR rbytordpat(1)))) AND (NOT (niO11l XOR rbytordpat(2)))) AND (NOT (niO11O XOR rbytordpat(3)))) AND (NOT (niO10i XOR rbytordpat(4)))) AND (NOT (niO10l XOR rbytordpat(5)))) AND (NOT (niO10O XOR rbytordpat(6)))) AND (NOT (niO1ii XOR rbytordpat(7)))); + niOOlii <= ((((((((NOT (rbytordpat(0) XOR wire_nl1i1l_dataout)) AND (NOT (rbytordpat(1) XOR wire_nl1i1O_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl1i0i_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl1i0l_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl1i0O_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl1iii_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl1iil_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl1iiO_dataout))); + niOOlil <= ((((((((NOT (rbytordpat(0) XOR wire_nl101i_dataout)) AND (NOT (rbytordpat(1) XOR wire_nl101l_dataout))) AND (NOT (rbytordpat(2) XOR wire_nl101O_dataout))) AND (NOT (rbytordpat(3) XOR wire_nl100i_dataout))) AND (NOT (rbytordpat(4) XOR wire_nl100l_dataout))) AND (NOT (rbytordpat(5) XOR wire_nl100O_dataout))) AND (NOT (rbytordpat(6) XOR wire_nl10ii_dataout))) AND (NOT (rbytordpat(7) XOR wire_nl10il_dataout))); + niOOliO <= (((wire_nli1ii_w_lg_niiOil6507w(0) AND wire_nli1ii_w_lg_niiOii3801w(0)) AND wire_nli1ii_w_lg_niiO0O6509w(0)) AND wire_nli1ii_w_lg_niiO0l6511w(0)); + niOOlli <= (wire_nl1l1O_w_lg_dataout5768w(0) AND wire_nl1l0i_w_lg_dataout5769w(0)); + niOOlll <= ((NOT rbytorden(0)) AND (NOT rbytorden(1))); + niOOllO <= ((wire_w_lg_rwa_6g_en2w(0) AND wire_w_lg_niOOlOO671w(0)) AND wire_w_lg_rbytord_s2gx660w(0)); + niOOlOi <= (wire_w_lg_rbytord_s2gx660w(0) AND (wire_w_lg_rwa_6g_en2w(0) AND (niOOlOO OR niOOO1i))); + niOOlOl <= (wire_w_lg_rbytord_s2gx660w(0) AND (wire_w_lg_rwa_6g_en2w(0) AND wire_w_lg_niOOO1i663w(0))); + niOOlOO <= (n1iiO AND wire_n1ill_w_lg_n1iil658w(0)); + niOOO0l <= (rauto_speed_ena AND dis_pc_byte); + niOOO1i <= (wire_n1ill_w_lg_n1iiO656w(0) AND n1ili); + niOOOii <= '0'; + niOOOil <= (wire_w_lg_rdwidth639w(0) AND rrxpcsbypass_en); + niOOOiO <= ((((((((((NOT wire_w_lg_w_tenb_data_range588w5736w(0)) AND (NOT wire_w_lg_w_tenb_data_range587w5738w(0))) AND (NOT wire_w_lg_w_tenb_data_range586w5741w(0))) AND (NOT wire_w_lg_w_tenb_data_range585w5744w(0))) AND (NOT wire_w_lg_w_tenb_data_range584w5747w(0))) AND (NOT wire_w_lg_w_tenb_data_range583w5750w(0))) AND (NOT wire_w_lg_w_tenb_data_range582w5753w(0))) AND (NOT wire_w_lg_w_tenb_data_range581w5756w(0))) AND (NOT wire_w_lg_w_tenb_data_range331w5759w(0))) AND (NOT wire_w_lg_w_tenb_data_range580w5762w(0))); + niOOOli <= ((((((((((NOT (tenb_data(10) XOR rsync_comp_pat(20))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(23)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(24)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(25)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(26)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(27)))) AND (NOT (tenb_data(18) XOR rsync_comp_pat(28)))) AND (NOT (tenb_data(19) XOR rsync_comp_pat(29)))); + niOOOll <= ((((((((((((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(10))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(15)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(16)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(8) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(9) XOR rsync_comp_pat(19)))) AND (NOT (tenb_data(10) XOR rsync_comp_pat(20)))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(23)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(24)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(25)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(26)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(27)))) AND (NOT (tenb_data(18) XOR rsync_comp_pat(28)))) AND (NOT (tenb_data(19) XOR rsync_comp_pat(29)))); + niOOOlO <= ((((((((NOT wire_w_lg_w_tenb_data_range588w5674w(0)) AND (NOT wire_w_lg_w_tenb_data_range587w5676w(0))) AND (NOT wire_w_lg_w_tenb_data_range586w5679w(0))) AND (NOT wire_w_lg_w_tenb_data_range585w5682w(0))) AND (NOT wire_w_lg_w_tenb_data_range584w5685w(0))) AND (NOT wire_w_lg_w_tenb_data_range583w5688w(0))) AND (NOT wire_w_lg_w_tenb_data_range582w5691w(0))) AND (NOT wire_w_lg_w_tenb_data_range581w5694w(0))); + niOOOOi <= ((((((((NOT (tenb_data(10) XOR rsync_comp_pat(16))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(19)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(20)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(23)))); + niOOOOl <= ((((((((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(8))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(9)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(10)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(15)))) AND (NOT (tenb_data(10) XOR rsync_comp_pat(16)))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(19)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(20)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(23)))); + nl1010i <= (((((((((((((((((((((((((((((((((((((((((((((wire_nliOi_o(63) OR wire_nliOi_o(62)) OR wire_nliOi_o(59)) OR wire_nliOi_o(58)) OR wire_nliOi_o(55)) OR wire_nliOi_o(54)) OR wire_nliOi_o(51)) OR wire_nliOi_o(50)) OR wire_nliOi_o(47)) OR wire_nliOi_o(46)) OR wire_nliOi_o(45)) OR wire_nliOi_o(44)) OR wire_nliOi_o(41)) OR wire_nliOi_o(40)) OR wire_nliOi_o(37)) OR wire_nliOi_o(36)) OR wire_nliOi_o(33)) OR wire_nliOi_o(32)) OR wire_nliOi_o(31)) OR wire_nliOi_o(30)) OR wire_nliOi_o(29)) OR wire_nliOi_o(28)) OR wire_nliOi_o(27)) OR wire_nliOi_o(26)) OR wire_nliOi_o(25)) OR wire_nliOi_o(24)) OR wire_nliOi_o(23)) OR wire_nliOi_o(22)) OR wire_nliOi_o(19)) OR wire_nliOi_o(18)) OR wire_nliOi_o(15)) OR wire_nliOi_o(14)) OR wire_nliOi_o(13)) OR wire_nliOi_o(12)) OR wire_nliOi_o(11)) OR wire_nliOi_o(10)) OR wire_nliOi_o(9)) OR wire_nliOi_o(8)) OR wire_nliOi_o(7)) OR wire_nliOi_o(6)) OR wire_nliOi_o(5)) OR wire_nliOi_o(4)) OR wire_nliOi_o(3)) OR wire_nliOi_o(2)) OR wire_nliOi_o(1)) OR wire_nliOi_o(0)); + nl101il <= ((((((((NOT (tenb_data(0) XOR rsync_comp_pat(8))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(9)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(10)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(15)))); + nl101ll <= (wire_w_lg_soft_reset8w(0) OR (NOT (nl101lO4 XOR nl101lO3))); + nl101Ol <= ((wire_w_lg_rsync_sm_dis1w(0) AND wire_w_lg_rwa_6g_en2w(0)) AND (nl101OO2 XOR nl101OO1)); + nl1100i <= ((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(20))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(23)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(24)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(25)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(26)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(27)))) AND (NOT (tenb_data(8) XOR rsync_comp_pat(28)))) AND (NOT (tenb_data(9) XOR rsync_comp_pat(29)))); + nl1100l <= ((((((((((((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(20))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(23)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(24)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(25)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(26)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(27)))) AND (NOT (tenb_data(8) XOR rsync_comp_pat(28)))) AND (NOT (tenb_data(9) XOR rsync_comp_pat(29)))) AND (NOT (tenb_data(10) XOR rsync_comp_pat(30)))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(31)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(32)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(33)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(34)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(35)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(36)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(37)))) AND (NOT (tenb_data(18) XOR rsync_comp_pat(38)))) AND (NOT (tenb_data(19) XOR rsync_comp_pat(39)))); + nl1100O <= ((((((((NOT wire_w_lg_w_tenb_data_range588w5487w(0)) AND (NOT wire_w_lg_w_tenb_data_range587w5489w(0))) AND (NOT wire_w_lg_w_tenb_data_range586w5492w(0))) AND (NOT wire_w_lg_w_tenb_data_range585w5495w(0))) AND (NOT wire_w_lg_w_tenb_data_range584w5498w(0))) AND (NOT wire_w_lg_w_tenb_data_range583w5501w(0))) AND (NOT wire_w_lg_w_tenb_data_range582w5504w(0))) AND (NOT wire_w_lg_w_tenb_data_range581w5507w(0))); + nl1101i <= ((((((((((NOT wire_w_lg_w_tenb_data_range588w5607w(0)) AND (NOT wire_w_lg_w_tenb_data_range587w5609w(0))) AND (NOT wire_w_lg_w_tenb_data_range586w5612w(0))) AND (NOT wire_w_lg_w_tenb_data_range585w5615w(0))) AND (NOT wire_w_lg_w_tenb_data_range584w5618w(0))) AND (NOT wire_w_lg_w_tenb_data_range583w5621w(0))) AND (NOT wire_w_lg_w_tenb_data_range582w5624w(0))) AND (NOT wire_w_lg_w_tenb_data_range581w5627w(0))) AND (NOT wire_w_lg_w_tenb_data_range331w5630w(0))) AND (NOT wire_w_lg_w_tenb_data_range580w5633w(0))); + nl1101l <= ((((((((((NOT (tenb_data(10) XOR rsync_comp_pat(30))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(31)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(32)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(33)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(34)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(35)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(36)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(37)))) AND (NOT (tenb_data(18) XOR rsync_comp_pat(38)))) AND (NOT (tenb_data(19) XOR rsync_comp_pat(39)))); + nl1101O <= ((((((((((NOT wire_w_lg_w_tenb_data_range597w5569w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w5571w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w5574w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w5577w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w5580w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w5583w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w5586w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w5589w(0))) AND (NOT wire_w_lg_w_tenb_data_range98w5592w(0))) AND (NOT wire_w_lg_w_tenb_data_range589w5595w(0))); + nl110ii <= ((((((((NOT (tenb_data(10) XOR rsync_comp_pat(24))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(25)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(26)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(27)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(28)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(29)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(30)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(31)))); + nl110il <= ((((((((NOT wire_w_lg_w_tenb_data_range597w5453w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w5455w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w5458w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w5461w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w5465w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w5469w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w5473w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w5477w(0))); + nl110iO <= ((((((((NOT (tenb_data(0) XOR rsync_comp_pat(16))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(19)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(20)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(23)))); + nl110li <= ((((((((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(16))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(19)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(20)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(21)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(22)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(23)))) AND (NOT (tenb_data(10) XOR rsync_comp_pat(24)))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(25)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(26)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(27)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(28)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(29)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(30)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(31)))); + nl110ll <= (((((((NOT (wire_w_lg_w_rsync_comp_pat_range4891w4918w(0) XOR tenb_data(10))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4894w4921w(0) XOR tenb_data(11)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4898w4925w(0) XOR tenb_data(12)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4902w4929w(0) XOR tenb_data(13)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4906w4933w(0) XOR tenb_data(14)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4910w4937w(0) XOR tenb_data(15)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4914w4941w(0) XOR tenb_data(16)))); + nl110lO <= (((((((NOT (rsync_comp_pat(0) XOR tenb_data(10))) AND (NOT (rsync_comp_pat(1) XOR tenb_data(11)))) AND (NOT (rsync_comp_pat(2) XOR tenb_data(12)))) AND (NOT (rsync_comp_pat(3) XOR tenb_data(13)))) AND (NOT (rsync_comp_pat(4) XOR tenb_data(14)))) AND (NOT (rsync_comp_pat(5) XOR tenb_data(15)))) AND (NOT (rsync_comp_pat(6) XOR tenb_data(16)))); + nl110Oi <= (((((((((((((((((((((((((((((((((((((((((((((wire_niOOi_o(63) OR wire_niOOi_o(62)) OR wire_niOOi_o(59)) OR wire_niOOi_o(58)) OR wire_niOOi_o(55)) OR wire_niOOi_o(54)) OR wire_niOOi_o(51)) OR wire_niOOi_o(50)) OR wire_niOOi_o(47)) OR wire_niOOi_o(46)) OR wire_niOOi_o(45)) OR wire_niOOi_o(44)) OR wire_niOOi_o(41)) OR wire_niOOi_o(40)) OR wire_niOOi_o(37)) OR wire_niOOi_o(36)) OR wire_niOOi_o(33)) OR wire_niOOi_o(32)) OR wire_niOOi_o(31)) OR wire_niOOi_o(30)) OR wire_niOOi_o(29)) OR wire_niOOi_o(28)) OR wire_niOOi_o(27)) OR wire_niOOi_o(26)) OR wire_niOOi_o(25)) OR wire_niOOi_o(24)) OR wire_niOOi_o(23)) OR wire_niOOi_o(22)) OR wire_niOOi_o(19)) OR wire_niOOi_o(18)) OR wire_niOOi_o(15)) OR wire_niOOi_o(14)) OR wire_niOOi_o(13)) OR wire_niOOi_o(12)) OR wire_niOOi_o(11)) OR wire_niOOi_o(10)) OR wire_niOOi_o(9)) OR wire_niOOi_o(8)) OR wire_niOOi_o(7)) OR wire_niOOi_o(6)) OR wire_niOOi_o(5)) OR wire_niOOi_o(4)) OR wire_niOOi_o(3)) OR wire_niOOi_o(2)) OR wire_niOOi_o(1)) OR wire_niOOi_o(0)); + nl110Ol <= (nl11i1l OR ((rsync_comp_porn AND nl11O0l) AND (nl11i1i OR nl110OO))); + nl110OO <= ((((((((((NOT wire_w_lg_w_tenb_data_range588w5373w(0)) AND (NOT wire_w_lg_w_tenb_data_range587w5375w(0))) AND (NOT wire_w_lg_w_tenb_data_range586w5378w(0))) AND (NOT wire_w_lg_w_tenb_data_range585w5381w(0))) AND (NOT wire_w_lg_w_tenb_data_range584w5384w(0))) AND (NOT wire_w_lg_w_tenb_data_range583w5387w(0))) AND (NOT wire_w_lg_w_tenb_data_range582w5390w(0))) AND (NOT wire_w_lg_w_tenb_data_range581w5393w(0))) AND (NOT wire_w_lg_w_tenb_data_range331w5396w(0))) AND (NOT wire_w_lg_w_tenb_data_range580w5399w(0))); + nl1110i <= (wire_nlO1i1i_w_lg_nlO1i1l613w(0) AND nl1110l); + nl1110l <= (rdwidth OR (nlOl0O AND (rauto_speed_ena AND wire_w_lg_rfreq_sel609w(0)))); + nl1110O <= '1'; + nl1111l <= (nlO1i1l AND nl1110l); + nl1111O <= (wire_n1liO_dataout OR nliO0i); + nl111il <= (niiO1O AND wire_nli1ii_w_lg_nlO1i1O604w(0)); + nl111iO <= (wire_n1ill_w_lg_n1ilO602w(0) AND wire_n1liO_dataout); + nl111li <= (wire_nli1ii_w_lg_niOi0i600w(0) AND niOi0l); + nl111ll <= ((((((wire_w_lg_w_rx_data_rs_range546w549w(0) OR (NOT rx_data_rs(2))) OR (NOT rx_data_rs(3))) OR (NOT rx_data_rs(4))) OR (NOT rx_data_rs(5))) OR (NOT rx_data_rs(6))) OR (NOT rx_data_rs(7))); + nl111lO <= (wire_nli_w_lg_dataout535w(0) AND (NOT (wire_n1ill_w_lg_nll0lO536w(0) AND wire_w_lg_w_sync_resync_delay_range537w541w(0)))); + nl111Oi <= (wire_niO_w_lg_dataout512w(0) AND (NOT (wire_n1ill_w_lg_nll0ll513w(0) AND wire_w_lg_w_sync_resync_delay_range514w518w(0)))); + nl111Ol <= (wire_w_lg_rsync_sm_dis1w(0) AND wire_w_lg_rautoinsdis499w(0)); + nl111OO <= (wire_w_lg_rinvalid_code_err_only497w(0) AND rwa_6g_en); + nl11i0i <= ((((((((NOT (tenb_data(10) XOR rsync_comp_pat(8))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(9)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(10)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(15)))); + nl11i0l <= ((((((((NOT wire_w_lg_w_tenb_data_range588w5299w(0)) AND (NOT wire_w_lg_w_tenb_data_range587w5301w(0))) AND (NOT wire_w_lg_w_tenb_data_range586w5304w(0))) AND (NOT wire_w_lg_w_tenb_data_range585w5307w(0))) AND (NOT wire_w_lg_w_tenb_data_range584w5310w(0))) AND (NOT wire_w_lg_w_tenb_data_range583w5313w(0))) AND (NOT wire_w_lg_w_tenb_data_range582w5316w(0))) AND (NOT wire_w_lg_w_tenb_data_range581w5319w(0))); + nl11i0O <= ((((((((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(0))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(1)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(2)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(3)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(4)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(5)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(6)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(7)))) AND (NOT (tenb_data(10) XOR rsync_comp_pat(8)))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(9)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(10)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(15)))); + nl11i1i <= ((((((((((NOT (tenb_data(10) XOR rsync_comp_pat(10))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(15)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(16)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(18) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(19) XOR rsync_comp_pat(19)))); + nl11i1l <= ((((((((((((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(0))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(1)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(2)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(3)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(4)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(5)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(6)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(7)))) AND (NOT (tenb_data(8) XOR rsync_comp_pat(8)))) AND (NOT (tenb_data(9) XOR rsync_comp_pat(9)))) AND (NOT (tenb_data(10) XOR rsync_comp_pat(10)))) AND (NOT (tenb_data(11) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(12) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(13) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(14) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(15) XOR rsync_comp_pat(15)))) AND (NOT (tenb_data(16) XOR rsync_comp_pat(16)))) AND (NOT (tenb_data(17) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(18) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(19) XOR rsync_comp_pat(19)))); + nl11i1O <= (nl11i0O OR (wire_w_lg_rsync_comp_porn320w(0) AND (nl11i0l OR nl11i0i))); + nl11iii <= (nl11iiO OR (rsync_comp_porn AND nl11iil)); + nl11iil <= ((((((((((NOT (wire_w_lg_w_rsync_comp_pat_range4891w4918w(0) XOR tenb_data(10))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4894w4921w(0) XOR tenb_data(11)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4898w4925w(0) XOR tenb_data(12)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4902w4929w(0) XOR tenb_data(13)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4906w4933w(0) XOR tenb_data(14)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4910w4937w(0) XOR tenb_data(15)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4914w4941w(0) XOR tenb_data(16)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range5249w5253w(0) XOR tenb_data(17)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4945w4946w(0) XOR tenb_data(18)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4949w4950w(0) XOR tenb_data(19)))); + nl11iiO <= ((((((((((NOT (rsync_comp_pat(0) XOR tenb_data(10))) AND (NOT (rsync_comp_pat(1) XOR tenb_data(11)))) AND (NOT (rsync_comp_pat(2) XOR tenb_data(12)))) AND (NOT (rsync_comp_pat(3) XOR tenb_data(13)))) AND (NOT (rsync_comp_pat(4) XOR tenb_data(14)))) AND (NOT (rsync_comp_pat(5) XOR tenb_data(15)))) AND (NOT (rsync_comp_pat(6) XOR tenb_data(16)))) AND (NOT (rsync_comp_pat(7) XOR tenb_data(17)))) AND (NOT (rsync_comp_pat(8) XOR tenb_data(18)))) AND (NOT (rsync_comp_pat(9) XOR tenb_data(19)))); + nl11ili <= (nl11ilO OR (rsync_comp_porn AND nl11ill)); + nl11ill <= ((((((((NOT (wire_w_lg_w_rsync_comp_pat_range4891w4918w(0) XOR tenb_data(10))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4894w4921w(0) XOR tenb_data(11)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4898w4925w(0) XOR tenb_data(12)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4902w4929w(0) XOR tenb_data(13)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4906w4933w(0) XOR tenb_data(14)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4910w4937w(0) XOR tenb_data(15)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range4914w4941w(0) XOR tenb_data(16)))) AND (NOT (wire_w_lg_w_rsync_comp_pat_range5249w5253w(0) XOR tenb_data(17)))); + nl11ilO <= ((((((((NOT (rsync_comp_pat(0) XOR tenb_data(10))) AND (NOT (rsync_comp_pat(1) XOR tenb_data(11)))) AND (NOT (rsync_comp_pat(2) XOR tenb_data(12)))) AND (NOT (rsync_comp_pat(3) XOR tenb_data(13)))) AND (NOT (rsync_comp_pat(4) XOR tenb_data(14)))) AND (NOT (rsync_comp_pat(5) XOR tenb_data(15)))) AND (NOT (rsync_comp_pat(6) XOR tenb_data(16)))) AND (NOT (rsync_comp_pat(7) XOR tenb_data(17)))); + nl11iOi <= ((((((((((NOT wire_w_lg_w_tenb_data_range597w5149w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w5151w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w5155w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w5159w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w5163w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w5167w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w5171w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w5175w(0))) AND (NOT wire_w_lg_w_tenb_data_range98w5179w(0))) AND (NOT wire_w_lg_w_tenb_data_range589w5183w(0))); + nl11iOl <= ((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(30))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(31)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(32)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(33)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(34)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(35)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(36)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(37)))) AND (NOT (tenb_data(8) XOR rsync_comp_pat(38)))) AND (NOT (tenb_data(9) XOR rsync_comp_pat(39)))); + nl11iOO <= ((((((((((NOT wire_w_lg_w_tenb_data_range597w5017w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w5019w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w5022w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w5025w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w5028w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w5031w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w5035w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w5039w(0))) AND (NOT wire_w_lg_w_tenb_data_range98w5043w(0))) AND (NOT wire_w_lg_w_tenb_data_range589w5047w(0))); + nl11l1i <= ((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(10))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(11)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(12)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(13)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(14)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(15)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(16)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(17)))) AND (NOT (tenb_data(8) XOR rsync_comp_pat(18)))) AND (NOT (tenb_data(9) XOR rsync_comp_pat(19)))); + nl11lii <= ((((((((((NOT wire_w_lg_w_tenb_data_range597w4919w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w4922w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w4926w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w4930w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w4934w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w4938w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w4942w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w5296w(0))) AND (NOT wire_w_lg_w_tenb_data_range98w5358w(0))) AND (NOT wire_w_lg_w_tenb_data_range589w5361w(0))); + nl11lil <= ((((((((((NOT (tenb_data(0) XOR rsync_comp_pat(0))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(1)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(2)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(3)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(4)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(5)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(6)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(7)))) AND (NOT (tenb_data(8) XOR rsync_comp_pat(8)))) AND (NOT (tenb_data(9) XOR rsync_comp_pat(9)))); + nl11llO <= ((((((((NOT wire_w_lg_w_tenb_data_range597w5082w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w5085w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w5089w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w5093w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w5097w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w5101w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w5105w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w5109w(0))); + nl11lOi <= ((((((((NOT (tenb_data(0) XOR rsync_comp_pat(24))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(25)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(26)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(27)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(28)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(29)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(30)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(31)))); + nl11O0i <= ((((((((NOT (tenb_data(0) XOR rsync_comp_pat(0))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(1)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(2)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(3)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(4)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(5)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(6)))) AND (NOT (tenb_data(7) XOR rsync_comp_pat(7)))); + nl11O0l <= (nl11lil OR nl11lii); + nl11O1l <= ((((((((NOT wire_w_lg_w_tenb_data_range597w4947w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w4951w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w4956w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w4961w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w4966w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w4971w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w4976w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w4981w(0))); + nl11O1O <= ((((((((NOT wire_w_lg_w_tenb_data_range597w4919w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w4922w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w4926w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w4930w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w4934w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w4938w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w4942w(0))) AND (NOT wire_w_lg_w_tenb_data_range590w5296w(0))); + nl11Oil <= (((((((NOT wire_w_lg_w_tenb_data_range597w4919w(0)) AND (NOT wire_w_lg_w_tenb_data_range596w4922w(0))) AND (NOT wire_w_lg_w_tenb_data_range595w4926w(0))) AND (NOT wire_w_lg_w_tenb_data_range594w4930w(0))) AND (NOT wire_w_lg_w_tenb_data_range593w4934w(0))) AND (NOT wire_w_lg_w_tenb_data_range592w4938w(0))) AND (NOT wire_w_lg_w_tenb_data_range591w4942w(0))); + nl11OiO <= (((((((NOT (tenb_data(0) XOR rsync_comp_pat(0))) AND (NOT (tenb_data(1) XOR rsync_comp_pat(1)))) AND (NOT (tenb_data(2) XOR rsync_comp_pat(2)))) AND (NOT (tenb_data(3) XOR rsync_comp_pat(3)))) AND (NOT (tenb_data(4) XOR rsync_comp_pat(4)))) AND (NOT (tenb_data(5) XOR rsync_comp_pat(5)))) AND (NOT (tenb_data(6) XOR rsync_comp_pat(6)))); + ph_fifo_empty <= wire_nl1000i_ph_fifo_empty; + ph_fifo_full <= wire_nl1000i_ph_fifo_full; + phystatus <= wire_nlOli_dataout; + pipe_data <= ( wire_nlO0ili_o & wire_nlO0iiO_o & wire_nlO0iil_o & wire_nlO0iii_o & wire_nlO0i0O_o & wire_nlO0i0l_o & wire_nlO0i0i_o & wire_nlO0i1O_o & wire_nlO0i1l_o & wire_nlO0i1i_o & wire_nlO00OO_o & wire_nlO00Ol_o & wire_nlO00Oi_o & wire_nlO00lO_o & wire_nlO00ll_o & wire_nlO00li_o & wire_nlO00iO_o & wire_nlO00il_o & wire_nlO00ii_o & wire_nlO000O_o & wire_nlO000l_o & wire_nlO000i_o & wire_nlO001O_o & wire_nlO001l_o & wire_nlO001i_o & wire_nlO01OO_o & wire_nlO01Ol_o & wire_nlO01Oi_o & wire_nlO01lO_o & wire_nlO01ll_o & wire_nlO01li_o & wire_nlO01iO_o & wire_nlO01il_o & wire_nlO01ii_o & wire_nlO010O_o & wire_nlO010l_o & wire_nlO010i_o & wire_nlO011O_o & wire_nlO011l_o & wire_nlO011i_o & wire_nlO1OOO_o & wire_nlO1OOl_o & wire_nlO1OOi_o & wire_nlO1OlO_o & wire_nlO1Oll_o & wire_nlO1Oli_o & wire_nlO1OiO_o & wire_nlO1Oil_o & wire_nlO1Oii_o & wire_nlO1O0O_o & wire_nlO1O0l_o & wire_nlO1O0i_o & wire_nlO1O1O_o & wire_nlO1O1l_o & wire_nlO1O1i_o & wire_nlO1lOO_o & wire_nlO1lOl_o & wire_nlO1lOi_o & wire_nlO1llO_o & wire_nlO1lll_o & wire_nlO1lli_o & wire_nlO1liO_o & wire_nlO1lil_o & wire_nlO1lii_o); + rd_enable2 <= niOiil; + rd_enable_out <= nl1OOO; + rptr_bin <= ( wire_nl1000i_rptr_bin(2 DOWNTO 0)); + running_disp <= ( wire_nli_dataout & wire_niO_dataout); + rx_we_out <= nlO1i1l; + rxc <= ( wire_n10i_dataout & wire_n11O_dataout & wire_n11l_dataout & wire_n11i_dataout); + rxd <= ( wire_nil_dataout & wire_nii_dataout & wire_n0O_dataout & wire_n0l_dataout & wire_n0i_dataout & wire_n1O_dataout & wire_n1l_dataout & wire_n1i_dataout & wire_nlOO_dataout & wire_nlOl_dataout & wire_nlOi_dataout & wire_nllO_dataout & wire_nlll_dataout & wire_nlli_dataout & wire_nliO_dataout & wire_nlil_dataout & wire_nlii_dataout & wire_nl0O_dataout & wire_nl0l_dataout & wire_nl0i_dataout & wire_nl1O_dataout & wire_nl1l_dataout & wire_nl1i_dataout & wire_niOO_dataout & wire_niOl_dataout & wire_niOi_dataout & wire_nilO_dataout & wire_nill_dataout & wire_nili_dataout & wire_niiO_dataout & wire_niil_dataout & wire_niii_dataout & wire_ni0O_dataout & wire_ni0l_dataout & wire_ni0i_dataout & wire_ni1O_dataout & wire_ni1l_dataout & wire_ni1i_dataout & wire_n0OO_dataout & wire_n0Ol_dataout & wire_n0Oi_dataout & wire_n0lO_dataout & wire_n0ll_dataout & wire_n0li_dataout & wire_n0iO_dataout & wire_n0il_dataout & wire_n0ii_dataout & wire_n00O_dataout & wire_n00l_dataout & wire_n00i_dataout & wire_n01O_dataout & wire_n01l_dataout & wire_n01i_dataout & wire_n1OO_dataout & wire_n1Ol_dataout & wire_n1Oi_dataout & wire_n1lO_dataout & wire_n1ll_dataout & wire_n1li_dataout & wire_n1iO_dataout & wire_n1il_dataout & wire_n1ii_dataout & wire_n10O_dataout & wire_n10l_dataout); + rxd_19 <= ( wire_nlOOi_dataout & wire_nlOlO_dataout); + rxd_9 <= ( wire_nlOOO_dataout & wire_nlOOl_dataout); + rxd_lpbk <= ( wire_nl1000i_data_out(57 DOWNTO 48) & wire_nl1000i_data_out(41 DOWNTO 32) & wire_nl1000i_data_out(25 DOWNTO 16) & wire_nl1000i_data_out(9 DOWNTO 0)); + rxstatus <= ( wire_nlOil_dataout & wire_nlOii_dataout & wire_nlO0O_dataout); + rxvalid <= wire_nlOiO_dataout; + signal_detect_out <= sigdetni; + soft_reset_rclk1 <= wire_nli01l_dataout; + soft_reset_wclk1 <= wire_nli00O_dataout; + wptr_bin <= ( wire_nl1000i_wptr_bin(2 DOWNTO 0)); + wr_enable2 <= nl010i; + wr_enable_out <= nl01li; + wire_w_disp_err_delay_range16w(0) <= disp_err_delay(0); + wire_w_disp_err_delay_range13w(0) <= disp_err_delay(1); + wire_w_invalid_code_delay_range17w(0) <= invalid_code_delay(0); + wire_w_invalid_code_delay_range14w(0) <= invalid_code_delay(1); + wire_w_rsync_comp_pat_range4891w(0) <= rsync_comp_pat(0); + wire_w_rsync_comp_pat_range4954w(0) <= rsync_comp_pat(10); + wire_w_rsync_comp_pat_range4959w(0) <= rsync_comp_pat(11); + wire_w_rsync_comp_pat_range4964w(0) <= rsync_comp_pat(12); + wire_w_rsync_comp_pat_range4969w(0) <= rsync_comp_pat(13); + wire_w_rsync_comp_pat_range4974w(0) <= rsync_comp_pat(14); + wire_w_rsync_comp_pat_range4979w(0) <= rsync_comp_pat(15); + wire_w_rsync_comp_pat_range5001w(0) <= rsync_comp_pat(16); + wire_w_rsync_comp_pat_range5005w(0) <= rsync_comp_pat(17); + wire_w_rsync_comp_pat_range5009w(0) <= rsync_comp_pat(18); + wire_w_rsync_comp_pat_range5013w(0) <= rsync_comp_pat(19); + wire_w_rsync_comp_pat_range4894w(0) <= rsync_comp_pat(1); + wire_w_rsync_comp_pat_range5413w(0) <= rsync_comp_pat(20); + wire_w_rsync_comp_pat_range5417w(0) <= rsync_comp_pat(21); + wire_w_rsync_comp_pat_range5421w(0) <= rsync_comp_pat(22); + wire_w_rsync_comp_pat_range5425w(0) <= rsync_comp_pat(23); + wire_w_rsync_comp_pat_range5050w(0) <= rsync_comp_pat(24); + wire_w_rsync_comp_pat_range5053w(0) <= rsync_comp_pat(25); + wire_w_rsync_comp_pat_range5057w(0) <= rsync_comp_pat(26); + wire_w_rsync_comp_pat_range5061w(0) <= rsync_comp_pat(27); + wire_w_rsync_comp_pat_range5065w(0) <= rsync_comp_pat(28); + wire_w_rsync_comp_pat_range5069w(0) <= rsync_comp_pat(29); + wire_w_rsync_comp_pat_range4898w(0) <= rsync_comp_pat(2); + wire_w_rsync_comp_pat_range5073w(0) <= rsync_comp_pat(30); + wire_w_rsync_comp_pat_range5077w(0) <= rsync_comp_pat(31); + wire_w_rsync_comp_pat_range5117w(0) <= rsync_comp_pat(32); + wire_w_rsync_comp_pat_range5121w(0) <= rsync_comp_pat(33); + wire_w_rsync_comp_pat_range5125w(0) <= rsync_comp_pat(34); + wire_w_rsync_comp_pat_range5129w(0) <= rsync_comp_pat(35); + wire_w_rsync_comp_pat_range5133w(0) <= rsync_comp_pat(36); + wire_w_rsync_comp_pat_range5137w(0) <= rsync_comp_pat(37); + wire_w_rsync_comp_pat_range5141w(0) <= rsync_comp_pat(38); + wire_w_rsync_comp_pat_range5145w(0) <= rsync_comp_pat(39); + wire_w_rsync_comp_pat_range4902w(0) <= rsync_comp_pat(3); + wire_w_rsync_comp_pat_range4906w(0) <= rsync_comp_pat(4); + wire_w_rsync_comp_pat_range4910w(0) <= rsync_comp_pat(5); + wire_w_rsync_comp_pat_range4914w(0) <= rsync_comp_pat(6); + wire_w_rsync_comp_pat_range5249w(0) <= rsync_comp_pat(7); + wire_w_rsync_comp_pat_range4945w(0) <= rsync_comp_pat(8); + wire_w_rsync_comp_pat_range4949w(0) <= rsync_comp_pat(9); + wire_w_rsync_comp_size_range101w(0) <= rsync_comp_size(0); + wire_w_rsync_comp_size_range105w(0) <= rsync_comp_size(1); + wire_w_rx_data_rs_range546w(0) <= rx_data_rs(0); + wire_w_rx_data_rs_range547w(0) <= rx_data_rs(1); + wire_w_sync_resync_delay_range514w(0) <= sync_resync_delay(0); + wire_w_sync_resync_delay_range537w(0) <= sync_resync_delay(1); + wire_w_tenb_data_range597w(0) <= tenb_data(0); + wire_w_tenb_data_range588w(0) <= tenb_data(10); + wire_w_tenb_data_range587w(0) <= tenb_data(11); + wire_w_tenb_data_range586w(0) <= tenb_data(12); + wire_w_tenb_data_range585w(0) <= tenb_data(13); + wire_w_tenb_data_range584w(0) <= tenb_data(14); + wire_w_tenb_data_range583w(0) <= tenb_data(15); + wire_w_tenb_data_range582w(0) <= tenb_data(16); + wire_w_tenb_data_range581w(0) <= tenb_data(17); + wire_w_tenb_data_range331w(0) <= tenb_data(18); + wire_w_tenb_data_range580w(0) <= tenb_data(19); + wire_w_tenb_data_range596w(0) <= tenb_data(1); + wire_w_tenb_data_range595w(0) <= tenb_data(2); + wire_w_tenb_data_range594w(0) <= tenb_data(3); + wire_w_tenb_data_range593w(0) <= tenb_data(4); + wire_w_tenb_data_range592w(0) <= tenb_data(5); + wire_w_tenb_data_range591w(0) <= tenb_data(6); + wire_w_tenb_data_range590w(0) <= tenb_data(7); + wire_w_tenb_data_range98w(0) <= tenb_data(8); + wire_w_tenb_data_range589w(0) <= tenb_data(9); + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOllOO57 <= niOllOO58; + END IF; + if (now = 0 ns) then + niOllOO57 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOllOO58 <= niOllOO57; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOlO1i55 <= niOlO1i56; + END IF; + if (now = 0 ns) then + niOlO1i55 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOlO1i56 <= niOlO1i55; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO0i49 <= niOOO0i50; + END IF; + if (now = 0 ns) then + niOOO0i49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO0i50 <= niOOO0i49; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO0O47 <= niOOO0O48; + END IF; + if (now = 0 ns) then + niOOO0O47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO0O48 <= niOOO0O47; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO1l53 <= niOOO1l54; + END IF; + if (now = 0 ns) then + niOOO1l53 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO1l54 <= niOOO1l53; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO1O51 <= niOOO1O52; + END IF; + if (now = 0 ns) then + niOOO1O51 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOO1O52 <= niOOO1O51; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOOOO45 <= niOOOOO46; + END IF; + if (now = 0 ns) then + niOOOOO45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN niOOOOO46 <= niOOOOO45; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1010l11 <= nl1010l12; + END IF; + if (now = 0 ns) then + nl1010l11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1010l12 <= nl1010l11; + END IF; + END PROCESS; + wire_nl1010l12_w_lg_w_lg_q111w112w(0) <= wire_nl1010l12_w_lg_q111w(0) AND rpmadatawidth; + wire_nl1010l12_w_lg_q111w(0) <= nl1010l12 XOR nl1010l11; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1010O10 <= nl1010O9; + END IF; + END PROCESS; + wire_nl1010O10_w_lg_w_lg_q106w107w(0) <= wire_nl1010O10_w_lg_q106w(0) AND wire_w_rsync_comp_size_range105w(0); + wire_nl1010O10_w_lg_q106w(0) <= nl1010O10 XOR nl1010O9; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1010O9 <= nl1010O10; + END IF; + if (now = 0 ns) then + nl1010O9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1011i15 <= nl1011i16; + END IF; + if (now = 0 ns) then + nl1011i15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1011i16 <= nl1011i15; + END IF; + END PROCESS; + wire_nl1011i16_w_lg_w_lg_q221w222w(0) <= NOT wire_nl1011i16_w_lg_q221w(0); + wire_nl1011i16_w_lg_q221w(0) <= nl1011i16 XOR nl1011i15; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1011O13 <= nl1011O14; + END IF; + if (now = 0 ns) then + nl1011O13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1011O14 <= nl1011O13; + END IF; + END PROCESS; + wire_nl1011O14_w_lg_w_lg_q214w215w(0) <= wire_nl1011O14_w_lg_q214w(0) AND wire_nliOi_w_lg_w_o_range211w213w(0); + wire_nl1011O14_w_lg_q214w(0) <= nl1011O14 XOR nl1011O13; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101ii7 <= nl101ii8; + END IF; + if (now = 0 ns) then + nl101ii7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101ii8 <= nl101ii7; + END IF; + END PROCESS; + wire_nl101ii8_w_lg_w_lg_q102w103w(0) <= wire_nl101ii8_w_lg_q102w(0) AND wire_w_rsync_comp_size_range101w(0); + wire_nl101ii8_w_lg_q102w(0) <= nl101ii8 XOR nl101ii7; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101iO5 <= nl101iO6; + END IF; + if (now = 0 ns) then + nl101iO5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101iO6 <= nl101iO5; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101lO3 <= nl101lO4; + END IF; + if (now = 0 ns) then + nl101lO3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101lO4 <= nl101lO3; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101OO1 <= nl101OO2; + END IF; + if (now = 0 ns) then + nl101OO1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl101OO2 <= nl101OO1; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1111i43 <= nl1111i44; + END IF; + if (now = 0 ns) then + nl1111i43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl1111i44 <= nl1111i43; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl111ii41 <= nl111ii42; + END IF; + if (now = 0 ns) then + nl111ii41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl111ii42 <= nl111ii41; + END IF; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11l0l35 <= nl11l0l36; + END IF; + if (now = 0 ns) then + nl11l0l35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11l0l36 <= nl11l0l35; + END IF; + END PROCESS; + wire_nl11l0l36_w_lg_q296w(0) <= nl11l0l36 XOR nl11l0l35; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11l1l39 <= nl11l1l40; + END IF; + if (now = 0 ns) then + nl11l1l39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11l1l40 <= nl11l1l39; + END IF; + END PROCESS; + wire_nl11l1l40_w_lg_w_lg_q303w304w(0) <= wire_nl11l1l40_w_lg_q303w(0) AND wire_w_lg_w_lg_nl11lil298w302w(0); + wire_nl11l1l40_w_lg_q303w(0) <= nl11l1l40 XOR nl11l1l39; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11l1O37 <= nl11l1O38; + END IF; + if (now = 0 ns) then + nl11l1O37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11l1O38 <= nl11l1O37; + END IF; + END PROCESS; + wire_nl11l1O38_w_lg_w_lg_q300w301w(0) <= NOT wire_nl11l1O38_w_lg_q300w(0); + wire_nl11l1O38_w_lg_q300w(0) <= nl11l1O38 XOR nl11l1O37; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11liO33 <= nl11liO34; + END IF; + if (now = 0 ns) then + nl11liO33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11liO34 <= nl11liO33; + END IF; + END PROCESS; + wire_nl11liO34_w_lg_w_lg_q291w292w(0) <= wire_nl11liO34_w_lg_q291w(0) AND wire_w_lg_nl11OiO290w(0); + wire_nl11liO34_w_lg_q291w(0) <= nl11liO34 XOR nl11liO33; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11lli31 <= nl11lli32; + END IF; + if (now = 0 ns) then + nl11lli31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11lli32 <= nl11lli31; + END IF; + END PROCESS; + wire_nl11lli32_w_lg_q288w(0) <= nl11lli32 XOR nl11lli31; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11lOl29 <= nl11lOl30; + END IF; + if (now = 0 ns) then + nl11lOl29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11lOl30 <= nl11lOl29; + END IF; + END PROCESS; + wire_nl11lOl30_w_lg_w_lg_q279w280w(0) <= wire_nl11lOl30_w_lg_q279w(0) AND wire_n1ill_w_lg_w_lg_nll10l275w278w(0); + wire_nl11lOl30_w_lg_q279w(0) <= nl11lOl30 XOR nl11lOl29; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11lOO27 <= nl11lOO28; + END IF; + if (now = 0 ns) then + nl11lOO27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11lOO28 <= nl11lOO27; + END IF; + END PROCESS; + wire_nl11lOO28_w_lg_q277w(0) <= nl11lOO28 XOR nl11lOO27; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11O0O25 <= nl11O0O26; + END IF; + if (now = 0 ns) then + nl11O0O25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11O0O26 <= nl11O0O25; + END IF; + END PROCESS; + wire_nl11O0O26_w_lg_w_lg_q264w265w(0) <= NOT wire_nl11O0O26_w_lg_q264w(0); + wire_nl11O0O26_w_lg_q264w(0) <= nl11O0O26 XOR nl11O0O25; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11Oli23 <= nl11Oli24; + END IF; + if (now = 0 ns) then + nl11Oli23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11Oli24 <= nl11Oli23; + END IF; + END PROCESS; + wire_nl11Oli24_w_lg_w_lg_q257w258w(0) <= NOT wire_nl11Oli24_w_lg_q257w(0); + wire_nl11Oli24_w_lg_q257w(0) <= nl11Oli24 XOR nl11Oli23; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11OlO21 <= nl11OlO22; + END IF; + if (now = 0 ns) then + nl11OlO21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11OlO22 <= nl11OlO21; + END IF; + END PROCESS; + wire_nl11OlO22_w_lg_w_lg_q242w243w(0) <= wire_nl11OlO22_w_lg_q242w(0) AND wire_nliOi_w_lg_w_lg_w_o_range235w237w241w(0); + wire_nl11OlO22_w_lg_q242w(0) <= nl11OlO22 XOR nl11OlO21; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11OOi19 <= nl11OOi20; + END IF; + if (now = 0 ns) then + nl11OOi19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11OOi20 <= nl11OOi19; + END IF; + END PROCESS; + wire_nl11OOi20_w_lg_w_lg_q239w240w(0) <= NOT wire_nl11OOi20_w_lg_q239w(0); + wire_nl11OOi20_w_lg_q239w(0) <= nl11OOi20 XOR nl11OOi19; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11OOO17 <= nl11OOO18; + END IF; + if (now = 0 ns) then + nl11OOO17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rx_wr_clk) + BEGIN + IF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN nl11OOO18 <= nl11OOO17; + END IF; + END PROCESS; + wire_nl11OOO18_w_lg_w_lg_q228w229w(0) <= wire_nl11OOO18_w_lg_q228w(0) AND wire_nliOi_w_lg_w_o_range225w227w(0); + wire_nl11OOO18_w_lg_q228w(0) <= nl11OOO18 XOR nl11OOO17; + PROCESS (clk_2, wire_n1ill_CLRN) + BEGIN + IF (wire_n1ill_CLRN = '0') THEN + n1i0i <= '0'; + n1i0O <= '0'; + n1i1O <= '0'; + n1iii <= '0'; + n1iil <= '0'; + n1iiO <= '0'; + n1ili <= '0'; + n1ilO <= '0'; + nli0iO <= '0'; + nlilOO <= '0'; + nliO0i <= '0'; + nliO0l <= '0'; + nliO0O <= '0'; + nliO1i <= '0'; + nliOii <= '0'; + nliOil <= '0'; + nliOiO <= '0'; + nliOli <= '0'; + nliOll <= '0'; + nliOlO <= '0'; + nliOOi <= '0'; + nliOOl <= '0'; + nliOOO <= '0'; + nll00i <= '0'; + nll00l <= '0'; + nll00O <= '0'; + nll01i <= '0'; + nll01l <= '0'; + nll01O <= '0'; + nll0ii <= '0'; + nll0il <= '0'; + nll0iO <= '0'; + nll0li <= '0'; + nll0ll <= '0'; + nll0lO <= '0'; + nll0Oi <= '0'; + nll0Ol <= '0'; + nll0OO <= '0'; + nll10i <= '0'; + nll10l <= '0'; + nll10O <= '0'; + nll11i <= '0'; + nll11l <= '0'; + nll11O <= '0'; + nll1ii <= '0'; + nll1il <= '0'; + nll1iO <= '0'; + nll1li <= '0'; + nll1ll <= '0'; + nll1lO <= '0'; + nll1Oi <= '0'; + nll1Ol <= '0'; + nll1OO <= '0'; + nlli0i <= '0'; + nlli0l <= '0'; + nlli0O <= '0'; + nlli1i <= '0'; + nlli1l <= '0'; + nlli1O <= '0'; + nlliii <= '0'; + nlliil <= '0'; + nlliiO <= '0'; + nllili <= '0'; + nllill <= '0'; + nllilO <= '0'; + nlliOi <= '0'; + nlliOl <= '0'; + nlliOO <= '0'; + nlll0i <= '0'; + nlll0l <= '0'; + nlll0O <= '0'; + nlll1i <= '0'; + nlll1l <= '0'; + nlll1O <= '0'; + nlllii <= '0'; + nlllil <= '0'; + nllliO <= '0'; + nlllli <= '0'; + nlllll <= '0'; + nllllO <= '0'; + nlllOi <= '0'; + nlllOl <= '0'; + nlO10Ol <= '0'; + nlO10OO <= '0'; + nlO1ili <= '0'; + nlOl0O <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n1i0i <= wire_n1iOi_dataout; + n1i0O <= wire_n1iOl_dataout; + n1i1O <= wire_n1i0l_dataout; + n1iii <= n1iil; + n1iil <= n1iiO; + n1iiO <= n1ili; + n1ili <= n1ilO; + n1ilO <= wire_n1liO_dataout; + nli0iO <= dec_data_valid(0); + nlilOO <= dec_data_valid(1); + nliO0i <= wire_n10Ol_dataout; + nliO0l <= nliOiO; + nliO0O <= nliOli; + nliO1i <= wire_nlOlii_dataout; + nliOii <= nliOll; + nliOil <= nliOlO; + nliOiO <= ovr_undflow(0); + nliOli <= ovr_undflow(1); + nliOll <= ovr_undflow(2); + nliOlO <= ovr_undflow(3); + nliOOi <= (nliOOl AND (niOOOll OR (wire_w_lg_rsync_comp_porn632w(0) AND (nl11l1i OR nl11iOO)))); + nliOOl <= nl11iii; + nliOOO <= (nll11i AND (niOOOOl OR (wire_w_lg_rsync_comp_porn626w(0) AND (nl11O1l OR nl101il)))); + nll00i <= disp_val_delay(1); + nll00l <= nll0ii; + nll00O <= nll0il; + nll01i <= nll01O; + nll01l <= nll00i; + nll01O <= disp_val_delay(0); + nll0ii <= disp_err_delay(0); + nll0il <= disp_err_delay(1); + nll0iO <= nll0ll; + nll0li <= nll0lO; + nll0ll <= wire_n000i_dataout; + nll0lO <= wire_n000l_dataout; + nll0Oi <= wire_nlOlil_dataout; + nll0Ol <= wire_nlOliO_dataout; + nll0OO <= wire_nlOlli_dataout; + nll10i <= nl11iii; + nll10l <= nl11ili; + nll10O <= nll1il; + nll11i <= nl11ili; + nll11l <= nl110Ol; + nll11O <= nl11i1O; + nll1ii <= nll1iO; + nll1il <= wire_nli1l_o; + nll1iO <= wire_niO1l_o; + nll1li <= (nl101il AND nll1lO); + nll1ll <= (nl11i0i AND nll1Oi); + nll1lO <= (nl11O0i AND nll1Ol); + nll1Oi <= (nl11ilO AND nll1OO); + nll1Ol <= nl11O0i; + nll1OO <= nl11ilO; + nlli0i <= wire_nlOlOl_dataout; + nlli0l <= wire_nlOlOO_dataout; + nlli0O <= wire_nlOO1i_dataout; + nlli1i <= wire_nlOlll_dataout; + nlli1l <= wire_nlOllO_dataout; + nlli1O <= wire_nlOlOi_dataout; + nlliii <= wire_nlOO1l_dataout; + nlliil <= wire_nlOO1O_dataout; + nlliiO <= wire_nlOO0i_dataout; + nllili <= wire_nlOO0l_dataout; + nllill <= wire_nlOO0O_dataout; + nllilO <= wire_nlOOii_dataout; + nlliOi <= wire_nlOOil_dataout; + nlliOl <= wire_nlOOiO_dataout; + nlliOO <= wire_nlOOli_dataout; + nlll0i <= wire_nlOOOl_dataout; + nlll0l <= wire_nlOOOO_dataout; + nlll0O <= wire_n111i_dataout; + nlll1i <= wire_nlOOll_dataout; + nlll1l <= wire_nlOOlO_dataout; + nlll1O <= wire_nlOOOi_dataout; + nlllii <= wire_n111l_dataout; + nlllil <= wire_n111O_dataout; + nllliO <= wire_n110i_dataout; + nlllli <= wire_n110l_dataout; + nlllll <= wire_n110O_dataout; + nllllO <= wire_n11ii_dataout; + nlllOi <= wire_n11il_dataout; + nlllOl <= wire_n11iO_dataout; + nlO10Ol <= nlO10OO; + nlO10OO <= wire_w_lg_niOOO0l650w(0); + nlO1ili <= wire_nlO1iil_dataout; + nlOl0O <= n1i1O; + END IF; + END PROCESS; + wire_n1ill_CLRN <= ((nl111ii42 XOR nl111ii41) AND wire_w_lg_soft_reset607w(0)); + wire_n1ill_w_lg_w_lg_nll10l275w278w(0) <= wire_n1ill_w_lg_nll10l275w(0) AND wire_nl11lOO28_w_lg_q277w(0); + wire_n1ill_w_lg_w_lg_n1ili661w662w(0) <= wire_n1ill_w_lg_n1ili661w(0) AND n1ilO; + wire_n1ill_w_lg_n1iil670w(0) <= n1iil AND wire_n1ill_w_lg_n1iii669w(0); + wire_n1ill_w_lg_nliOOi312w(0) <= nliOOi AND wire_w_lg_nl11iOl311w(0); + wire_n1ill_w_lg_nliOOO284w(0) <= nliOOO AND wire_w_lg_nl11lOi283w(0); + wire_n1ill_w_lg_nll10i308w(0) <= nll10i AND wire_w_lg_nl11l1i307w(0); + wire_n1ill_w_lg_nll10l275w(0) <= nll10l AND wire_w_lg_w_lg_rsync_comp_porn273w274w(0); + wire_n1ill_w_lg_nll11l494w(0) <= nll11l AND wire_w_lg_nl1100l493w(0); + wire_n1ill_w_lg_nll11O482w(0) <= nll11O AND wire_w_lg_nl110li481w(0); + wire_n1ill_w_lg_n1i0i4636w(0) <= NOT n1i0i; + wire_n1ill_w_lg_n1iii669w(0) <= NOT n1iii; + wire_n1ill_w_lg_n1iil658w(0) <= NOT n1iil; + wire_n1ill_w_lg_n1iiO656w(0) <= NOT n1iiO; + wire_n1ill_w_lg_n1ili661w(0) <= NOT n1ili; + wire_n1ill_w_lg_n1ilO602w(0) <= NOT n1ilO; + wire_n1ill_w_lg_nll0ll513w(0) <= NOT nll0ll; + wire_n1ill_w_lg_nll0lO536w(0) <= NOT nll0lO; + PROCESS (rx_rd_clk, wire_nl011l_PRN, wire_nl011l_CLRN) + BEGIN + IF (wire_nl011l_PRN = '0') THEN + niOiil <= '1'; + nl011i <= '1'; + nl011O <= '1'; + nl1OOO <= '1'; + ELSIF (wire_nl011l_CLRN = '0') THEN + niOiil <= '0'; + nl011i <= '0'; + nl011O <= '0'; + nl1OOO <= '0'; + ELSIF (rx_rd_clk = '1' AND rx_rd_clk'event) THEN + niOiil <= wire_nl010l_dataout; + nl011i <= nl011O; + nl011O <= wire_w_lg_niOOO0l650w(0); + nl1OOO <= wire_nl01il_dataout; + END IF; + END PROCESS; + wire_nl011l_CLRN <= ((niOOO1O52 XOR niOOO1O51) AND wire_nli01l_w_lg_dataout653w(0)); + wire_nl011l_PRN <= (niOOO1l54 XOR niOOO1l53); + PROCESS (rx_rd_clk, wire_nli01O_PRN) + BEGIN + IF (wire_nli01O_PRN = '0') THEN + nli00i <= '1'; + nli1iO <= '1'; + ELSIF (rx_rd_clk = '1' AND rx_rd_clk'event) THEN + nli00i <= niOOOii; + nli1iO <= nli00i; + END IF; + END PROCESS; + wire_nli01O_PRN <= ((niOOO0O48 XOR niOOO0O47) AND wire_w_lg_nl101ll641w(0)); + PROCESS (rx_wr_clk, nl101ll) + BEGIN + IF (nl101ll = '1') THEN + nli00l <= '1'; + nli0il <= '1'; + ELSIF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN + nli00l <= nli0il; + nli0il <= niOOOii; + END IF; + END PROCESS; + PROCESS (rx_wr_clk, wire_nli1ii_PRN, wire_nli00O_dataout) + BEGIN + IF (wire_nli1ii_PRN = '0') THEN + niiO0i <= '1'; + niiO0l <= '1'; + niiO0O <= '1'; + niiO1O <= '1'; + niiOii <= '1'; + niiOil <= '1'; + niiOiO <= '1'; + niiOli <= '1'; + niiOll <= '1'; + niiOlO <= '1'; + niiOOi <= '1'; + niiOOl <= '1'; + niiOOO <= '1'; + nil00i <= '1'; + nil00l <= '1'; + nil00O <= '1'; + nil01i <= '1'; + nil01l <= '1'; + nil01O <= '1'; + nil0ii <= '1'; + nil0il <= '1'; + nil0iO <= '1'; + nil0li <= '1'; + nil0ll <= '1'; + nil0lO <= '1'; + nil0Oi <= '1'; + nil0Ol <= '1'; + nil0OO <= '1'; + nil10i <= '1'; + nil10l <= '1'; + nil10O <= '1'; + nil11i <= '1'; + nil11l <= '1'; + nil11O <= '1'; + nil1ii <= '1'; + nil1il <= '1'; + nil1iO <= '1'; + nil1li <= '1'; + nil1ll <= '1'; + nil1lO <= '1'; + nil1Oi <= '1'; + nil1Ol <= '1'; + nil1OO <= '1'; + nili0i <= '1'; + nili0l <= '1'; + nili0O <= '1'; + nili1i <= '1'; + nili1l <= '1'; + nili1O <= '1'; + niliii <= '1'; + niliil <= '1'; + niliiO <= '1'; + nilili <= '1'; + nilill <= '1'; + nililO <= '1'; + niliOi <= '1'; + niliOl <= '1'; + niliOO <= '1'; + nill0i <= '1'; + nill0l <= '1'; + nill0O <= '1'; + nill1i <= '1'; + nill1l <= '1'; + nill1O <= '1'; + nillii <= '1'; + nillil <= '1'; + nilliO <= '1'; + nillli <= '1'; + nillll <= '1'; + nilllO <= '1'; + nillOi <= '1'; + nillOl <= '1'; + nillOO <= '1'; + nilO0i <= '1'; + nilO0l <= '1'; + nilO0O <= '1'; + nilO1i <= '1'; + nilO1l <= '1'; + nilO1O <= '1'; + nilOii <= '1'; + nilOil <= '1'; + nilOiO <= '1'; + nilOli <= '1'; + nilOll <= '1'; + nilOlO <= '1'; + nilOOi <= '1'; + nilOOl <= '1'; + nilOOO <= '1'; + niO00i <= '1'; + niO00l <= '1'; + niO00O <= '1'; + niO01i <= '1'; + niO01l <= '1'; + niO01O <= '1'; + niO0ii <= '1'; + niO0il <= '1'; + niO0iO <= '1'; + niO0li <= '1'; + niO0ll <= '1'; + niO0lO <= '1'; + niO0Oi <= '1'; + niO0Ol <= '1'; + niO0OO <= '1'; + niO10i <= '1'; + niO10l <= '1'; + niO10O <= '1'; + niO11i <= '1'; + niO11l <= '1'; + niO11O <= '1'; + niO1ii <= '1'; + niO1il <= '1'; + niO1iO <= '1'; + niO1li <= '1'; + niO1ll <= '1'; + niO1lO <= '1'; + niO1Oi <= '1'; + niO1Ol <= '1'; + niO1OO <= '1'; + niOi0i <= '1'; + niOi0l <= '1'; + niOi0O <= '1'; + niOi1i <= '1'; + niOi1l <= '1'; + niOi1O <= '1'; + niOiii <= '1'; + nl000i <= '1'; + nl000l <= '1'; + nl000O <= '1'; + nl001i <= '1'; + nl001l <= '1'; + nl001O <= '1'; + nl00ii <= '1'; + nl00il <= '1'; + nl00iO <= '1'; + nl00li <= '1'; + nl00ll <= '1'; + nl00lO <= '1'; + nl00Oi <= '1'; + nl00Ol <= '1'; + nl00OO <= '1'; + nl010i <= '1'; + nl01li <= '1'; + nl01ll <= '1'; + nl01lO <= '1'; + nl01Oi <= '1'; + nl01Ol <= '1'; + nl01OO <= '1'; + nl0i0i <= '1'; + nl0i0l <= '1'; + nl0i0O <= '1'; + nl0i1i <= '1'; + nl0i1l <= '1'; + nl0i1O <= '1'; + nl0iii <= '1'; + nl0iil <= '1'; + nl0iiO <= '1'; + nl0ili <= '1'; + nl0ill <= '1'; + nl0ilO <= '1'; + nl0iOi <= '1'; + nl0iOl <= '1'; + nl0iOO <= '1'; + nl0l0i <= '1'; + nl0l0l <= '1'; + nl0l0O <= '1'; + nl0l1i <= '1'; + nl0l1l <= '1'; + nl0l1O <= '1'; + nl0lii <= '1'; + nl0lil <= '1'; + nl0liO <= '1'; + nl0lli <= '1'; + nl0lll <= '1'; + nl0llO <= '1'; + nl0lOi <= '1'; + nl0lOl <= '1'; + nl0lOO <= '1'; + nl0O0i <= '1'; + nl0O0l <= '1'; + nl0O0O <= '1'; + nl0O1i <= '1'; + nl0O1l <= '1'; + nl0O1O <= '1'; + nl0Oii <= '1'; + nl0Oil <= '1'; + nl0OiO <= '1'; + nl0Oli <= '1'; + nl0Oll <= '1'; + nl0OlO <= '1'; + nl0OOi <= '1'; + nl0OOl <= '1'; + nl0OOO <= '1'; + nli10i <= '1'; + nli10l <= '1'; + nli10O <= '1'; + nli11i <= '1'; + nli11l <= '1'; + nli11O <= '1'; + nli1il <= '1'; + nlO1i1O <= '1'; + ELSIF (wire_nli00O_dataout = '1') THEN + niiO0i <= '0'; + niiO0l <= '0'; + niiO0O <= '0'; + niiO1O <= '0'; + niiOii <= '0'; + niiOil <= '0'; + niiOiO <= '0'; + niiOli <= '0'; + niiOll <= '0'; + niiOlO <= '0'; + niiOOi <= '0'; + niiOOl <= '0'; + niiOOO <= '0'; + nil00i <= '0'; + nil00l <= '0'; + nil00O <= '0'; + nil01i <= '0'; + nil01l <= '0'; + nil01O <= '0'; + nil0ii <= '0'; + nil0il <= '0'; + nil0iO <= '0'; + nil0li <= '0'; + nil0ll <= '0'; + nil0lO <= '0'; + nil0Oi <= '0'; + nil0Ol <= '0'; + nil0OO <= '0'; + nil10i <= '0'; + nil10l <= '0'; + nil10O <= '0'; + nil11i <= '0'; + nil11l <= '0'; + nil11O <= '0'; + nil1ii <= '0'; + nil1il <= '0'; + nil1iO <= '0'; + nil1li <= '0'; + nil1ll <= '0'; + nil1lO <= '0'; + nil1Oi <= '0'; + nil1Ol <= '0'; + nil1OO <= '0'; + nili0i <= '0'; + nili0l <= '0'; + nili0O <= '0'; + nili1i <= '0'; + nili1l <= '0'; + nili1O <= '0'; + niliii <= '0'; + niliil <= '0'; + niliiO <= '0'; + nilili <= '0'; + nilill <= '0'; + nililO <= '0'; + niliOi <= '0'; + niliOl <= '0'; + niliOO <= '0'; + nill0i <= '0'; + nill0l <= '0'; + nill0O <= '0'; + nill1i <= '0'; + nill1l <= '0'; + nill1O <= '0'; + nillii <= '0'; + nillil <= '0'; + nilliO <= '0'; + nillli <= '0'; + nillll <= '0'; + nilllO <= '0'; + nillOi <= '0'; + nillOl <= '0'; + nillOO <= '0'; + nilO0i <= '0'; + nilO0l <= '0'; + nilO0O <= '0'; + nilO1i <= '0'; + nilO1l <= '0'; + nilO1O <= '0'; + nilOii <= '0'; + nilOil <= '0'; + nilOiO <= '0'; + nilOli <= '0'; + nilOll <= '0'; + nilOlO <= '0'; + nilOOi <= '0'; + nilOOl <= '0'; + nilOOO <= '0'; + niO00i <= '0'; + niO00l <= '0'; + niO00O <= '0'; + niO01i <= '0'; + niO01l <= '0'; + niO01O <= '0'; + niO0ii <= '0'; + niO0il <= '0'; + niO0iO <= '0'; + niO0li <= '0'; + niO0ll <= '0'; + niO0lO <= '0'; + niO0Oi <= '0'; + niO0Ol <= '0'; + niO0OO <= '0'; + niO10i <= '0'; + niO10l <= '0'; + niO10O <= '0'; + niO11i <= '0'; + niO11l <= '0'; + niO11O <= '0'; + niO1ii <= '0'; + niO1il <= '0'; + niO1iO <= '0'; + niO1li <= '0'; + niO1ll <= '0'; + niO1lO <= '0'; + niO1Oi <= '0'; + niO1Ol <= '0'; + niO1OO <= '0'; + niOi0i <= '0'; + niOi0l <= '0'; + niOi0O <= '0'; + niOi1i <= '0'; + niOi1l <= '0'; + niOi1O <= '0'; + niOiii <= '0'; + nl000i <= '0'; + nl000l <= '0'; + nl000O <= '0'; + nl001i <= '0'; + nl001l <= '0'; + nl001O <= '0'; + nl00ii <= '0'; + nl00il <= '0'; + nl00iO <= '0'; + nl00li <= '0'; + nl00ll <= '0'; + nl00lO <= '0'; + nl00Oi <= '0'; + nl00Ol <= '0'; + nl00OO <= '0'; + nl010i <= '0'; + nl01li <= '0'; + nl01ll <= '0'; + nl01lO <= '0'; + nl01Oi <= '0'; + nl01Ol <= '0'; + nl01OO <= '0'; + nl0i0i <= '0'; + nl0i0l <= '0'; + nl0i0O <= '0'; + nl0i1i <= '0'; + nl0i1l <= '0'; + nl0i1O <= '0'; + nl0iii <= '0'; + nl0iil <= '0'; + nl0iiO <= '0'; + nl0ili <= '0'; + nl0ill <= '0'; + nl0ilO <= '0'; + nl0iOi <= '0'; + nl0iOl <= '0'; + nl0iOO <= '0'; + nl0l0i <= '0'; + nl0l0l <= '0'; + nl0l0O <= '0'; + nl0l1i <= '0'; + nl0l1l <= '0'; + nl0l1O <= '0'; + nl0lii <= '0'; + nl0lil <= '0'; + nl0liO <= '0'; + nl0lli <= '0'; + nl0lll <= '0'; + nl0llO <= '0'; + nl0lOi <= '0'; + nl0lOl <= '0'; + nl0lOO <= '0'; + nl0O0i <= '0'; + nl0O0l <= '0'; + nl0O0O <= '0'; + nl0O1i <= '0'; + nl0O1l <= '0'; + nl0O1O <= '0'; + nl0Oii <= '0'; + nl0Oil <= '0'; + nl0OiO <= '0'; + nl0Oli <= '0'; + nl0Oll <= '0'; + nl0OlO <= '0'; + nl0OOi <= '0'; + nl0OOl <= '0'; + nl0OOO <= '0'; + nli10i <= '0'; + nli10l <= '0'; + nli10O <= '0'; + nli11i <= '0'; + nli11l <= '0'; + nli11O <= '0'; + nli1il <= '0'; + nlO1i1O <= '0'; + ELSIF (rx_wr_clk = '1' AND rx_wr_clk'event) THEN + niiO0i <= wire_ni1liO_dataout; + niiO0l <= wire_niOl0O_dataout; + niiO0O <= wire_niOlii_dataout; + niiO1O <= wire_nlO1ill_dataout; + niiOii <= wire_niOlil_dataout; + niiOil <= wire_niOliO_dataout; + niiOiO <= wire_niOiiO_dataout; + niiOli <= nillOl; + niiOll <= nillOO; + niiOlO <= nilO1i; + niiOOi <= nilO1l; + niiOOl <= nilO1O; + niiOOO <= nilO0i; + nil00i <= niO1il; + nil00l <= niO1iO; + nil00O <= niO1li; + nil01i <= niO10l; + nil01l <= niO10O; + nil01O <= niO1ii; + nil0ii <= niO1ll; + nil0il <= niO1lO; + nil0iO <= niO1Oi; + nil0li <= niO1Ol; + nil0ll <= niO1OO; + nil0lO <= niO01i; + nil0Oi <= niO01l; + nil0Ol <= niO01O; + nil0OO <= niO00i; + nil10i <= nilOil; + nil10l <= nilOiO; + nil10O <= nilOli; + nil11i <= nilO0l; + nil11l <= nilO0O; + nil11O <= nilOii; + nil1ii <= nilOll; + nil1il <= nilOlO; + nil1iO <= nilOOi; + nil1li <= nilOOl; + nil1ll <= nilOOO; + nil1lO <= niO11i; + nil1Oi <= niO11l; + nil1Ol <= niO11O; + nil1OO <= niO10i; + nili0i <= niO0il; + nili0l <= niO0iO; + nili0O <= niO0li; + nili1i <= niO00l; + nili1l <= niO00O; + nili1O <= niO0ii; + niliii <= niO0ll; + niliil <= niO0lO; + niliiO <= niO0Oi; + nilili <= niO0Ol; + nilill <= niO0OO; + nililO <= niOi1i; + niliOi <= wire_niOlOl_dataout; + niliOl <= wire_niOlOO_dataout; + niliOO <= wire_niOO1i_dataout; + nill0i <= wire_niOO0l_dataout; + nill0l <= wire_niOO0O_dataout; + nill0O <= wire_niOOii_dataout; + nill1i <= wire_niOO1l_dataout; + nill1l <= wire_niOO1O_dataout; + nill1O <= wire_niOO0i_dataout; + nillii <= wire_niOOil_dataout; + nillil <= wire_niOOiO_dataout; + nilliO <= wire_niOOli_dataout; + nillli <= wire_niOOll_dataout; + nillll <= wire_niOOlO_dataout; + nilllO <= wire_niOOOi_dataout; + nillOi <= wire_niOOOl_dataout; + nillOl <= wire_niOOOO_dataout; + nillOO <= wire_nl111i_dataout; + nilO0i <= wire_nl110l_dataout; + nilO0l <= wire_nl110O_dataout; + nilO0O <= wire_nl11ii_dataout; + nilO1i <= wire_nl111l_dataout; + nilO1l <= wire_nl111O_dataout; + nilO1O <= wire_nl110i_dataout; + nilOii <= wire_nl11il_dataout; + nilOil <= wire_nl11iO_dataout; + nilOiO <= wire_nl11li_dataout; + nilOli <= wire_nl11ll_dataout; + nilOll <= wire_nl11lO_dataout; + nilOlO <= wire_nl11Oi_dataout; + nilOOi <= wire_nl11Ol_dataout; + nilOOl <= wire_nl11OO_dataout; + nilOOO <= wire_nl101i_dataout; + niO00i <= wire_nl1i0l_dataout; + niO00l <= wire_nl1i0O_dataout; + niO00O <= wire_nl1iii_dataout; + niO01i <= wire_nl1i1l_dataout; + niO01l <= wire_nl1i1O_dataout; + niO01O <= wire_nl1i0i_dataout; + niO0ii <= wire_nl1iil_dataout; + niO0il <= wire_nl1iiO_dataout; + niO0iO <= wire_nl1ili_dataout; + niO0li <= wire_nl1ill_dataout; + niO0ll <= wire_nl1ilO_dataout; + niO0lO <= wire_nl1iOi_dataout; + niO0Oi <= wire_nl1iOl_dataout; + niO0Ol <= wire_nl1iOO_dataout; + niO0OO <= wire_nl1l1i_dataout; + niO10i <= wire_nl100l_dataout; + niO10l <= wire_nl100O_dataout; + niO10O <= wire_nl10ii_dataout; + niO11i <= wire_nl101l_dataout; + niO11l <= wire_nl101O_dataout; + niO11O <= wire_nl100i_dataout; + niO1ii <= wire_nl10il_dataout; + niO1il <= wire_nl10iO_dataout; + niO1iO <= wire_nl10li_dataout; + niO1li <= wire_nl10ll_dataout; + niO1ll <= wire_nl10lO_dataout; + niO1lO <= wire_nl10Oi_dataout; + niO1Oi <= wire_nl10Ol_dataout; + niO1Ol <= wire_nl10OO_dataout; + niO1OO <= wire_nl1i1i_dataout; + niOi0i <= wire_niOl1O_dataout; + niOi0l <= niOi0O; + niOi0O <= niOiii; + niOi1i <= wire_nl1l1l_dataout; + niOi1l <= wire_nl1l1O_dataout; + niOi1O <= wire_nl1l0i_dataout; + niOiii <= bytordplden; + nl000i <= wire_nli0li_dataout; + nl000l <= wire_nli0ll_dataout; + nl000O <= wire_nli0lO_dataout; + nl001i <= pld_wr_dis; + nl001l <= nliO1i; + nl001O <= nliO1O; + nl00ii <= wire_nli0Oi_dataout; + nl00il <= wire_nli0Ol_dataout; + nl00iO <= wire_nli0OO_dataout; + nl00li <= wire_nlii1i_dataout; + nl00ll <= wire_nlii1l_dataout; + nl00lO <= wire_nlii1O_dataout; + nl00Oi <= wire_nlii0i_dataout; + nl00Ol <= wire_nlii0l_dataout; + nl00OO <= wire_nlii0O_dataout; + nl010i <= wire_nli1li_dataout; + nl01li <= wire_nli1Oi_dataout; + nl01ll <= nl01lO; + nl01lO <= wire_w_lg_niOOO0l650w(0); + nl01Oi <= (nl01OO XOR nl01Ol); + nl01Ol <= nl01OO; + nl01OO <= nl001i; + nl0i0i <= wire_nliili_dataout; + nl0i0l <= wire_nliill_dataout; + nl0i0O <= wire_nliilO_dataout; + nl0i1i <= wire_nliiii_dataout; + nl0i1l <= wire_nliiil_dataout; + nl0i1O <= wire_nliiiO_dataout; + nl0iii <= wire_nliiOi_dataout; + nl0iil <= wire_nliiOl_dataout; + nl0iiO <= wire_nliiOO_dataout; + nl0ili <= wire_nlil1i_dataout; + nl0ill <= wire_nlil1l_dataout; + nl0ilO <= wire_nlil1O_dataout; + nl0iOi <= wire_nlil0i_dataout; + nl0iOl <= wire_nlil0l_dataout; + nl0iOO <= wire_nlil0O_dataout; + nl0l0i <= wire_nlilli_dataout; + nl0l0l <= wire_nlilll_dataout; + nl0l0O <= nlO01O; + nl0l1i <= wire_nlilii_dataout; + nl0l1l <= wire_nlilil_dataout; + nl0l1O <= wire_nliliO_dataout; + nl0lii <= nlO00i; + nl0lil <= nlO00l; + nl0liO <= nlO00O; + nl0lli <= nlO0ii; + nl0lll <= nlO0il; + nl0llO <= nlO0iO; + nl0lOi <= nlO0li; + nl0lOl <= nlO0ll; + nl0lOO <= nlO0lO; + nl0O0i <= nlOi1i; + nl0O0l <= nlOi1l; + nl0O0O <= nlOi1O; + nl0O1i <= nlO0Oi; + nl0O1l <= nlO0Ol; + nl0O1O <= nlO0OO; + nl0Oii <= nlOi0i; + nl0Oil <= nlOi0l; + nl0OiO <= nlOi0O; + nl0Oli <= nlOiii; + nl0Oll <= nlOiil; + nl0OlO <= nlOiiO; + nl0OOi <= nlOili; + nl0OOl <= nlOill; + nl0OOO <= nlOilO; + nli10i <= nlOl1i; + nli10l <= nlOl1l; + nli10O <= nlOl1O; + nli11i <= nlOiOi; + nli11l <= nlOiOl; + nli11O <= nlOiOO; + nli1il <= nlOl0l; + nlO1i1O <= niiO1O; + END IF; + END PROCESS; + wire_nli1ii_PRN <= (niOOO0i50 XOR niOOO0i49); + wire_nli1ii_w_lg_niiO0l6511w(0) <= NOT niiO0l; + wire_nli1ii_w_lg_niiO0O6509w(0) <= NOT niiO0O; + wire_nli1ii_w_lg_niiOii3801w(0) <= NOT niiOii; + wire_nli1ii_w_lg_niiOil6507w(0) <= NOT niiOil; + wire_nli1ii_w_lg_niOi0i600w(0) <= NOT niOi0i; + wire_nli1ii_w_lg_niOi0l676w(0) <= NOT niOi0l; + wire_nli1ii_w_lg_nl01Oi645w(0) <= NOT nl01Oi; + wire_nli1ii_w_lg_nlO1i1O604w(0) <= NOT nlO1i1O; + PROCESS (clk_2, wire_nlO01i_PRN, wire_nlO01i_CLRN) + BEGIN + IF (wire_nlO01i_PRN = '0') THEN + nliO1l <= '1'; + nlllOO <= '1'; + nllO0i <= '1'; + nllO0l <= '1'; + nllO0O <= '1'; + nllO1i <= '1'; + nllO1l <= '1'; + nllO1O <= '1'; + nllOii <= '1'; + nllOil <= '1'; + nllOiO <= '1'; + nllOli <= '1'; + nllOll <= '1'; + nllOlO <= '1'; + nllOOi <= '1'; + nllOOl <= '1'; + nllOOO <= '1'; + nlO01l <= '1'; + nlO10i <= '1'; + nlO10l <= '1'; + nlO10O <= '1'; + nlO11i <= '1'; + nlO11l <= '1'; + nlO11O <= '1'; + nlO1ii <= '1'; + nlO1il <= '1'; + nlO1iO <= '1'; + nlO1li <= '1'; + nlO1ll <= '1'; + nlO1lO <= '1'; + nlO1Oi <= '1'; + nlO1Ol <= '1'; + nlO1OO <= '1'; + ELSIF (wire_nlO01i_CLRN = '0') THEN + nliO1l <= '0'; + nlllOO <= '0'; + nllO0i <= '0'; + nllO0l <= '0'; + nllO0O <= '0'; + nllO1i <= '0'; + nllO1l <= '0'; + nllO1O <= '0'; + nllOii <= '0'; + nllOil <= '0'; + nllOiO <= '0'; + nllOli <= '0'; + nllOll <= '0'; + nllOlO <= '0'; + nllOOi <= '0'; + nllOOl <= '0'; + nllOOO <= '0'; + nlO01l <= '0'; + nlO10i <= '0'; + nlO10l <= '0'; + nlO10O <= '0'; + nlO11i <= '0'; + nlO11l <= '0'; + nlO11O <= '0'; + nlO1ii <= '0'; + nlO1il <= '0'; + nlO1iO <= '0'; + nlO1li <= '0'; + nlO1ll <= '0'; + nlO1lO <= '0'; + nlO1Oi <= '0'; + nlO1Ol <= '0'; + nlO1OO <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + IF (nl1111l = '1') THEN + nliO1l <= nl1111O; + nlllOO <= wire_n1lOi_dataout; + nllO0i <= wire_n1O1l_dataout; + nllO0l <= wire_n1O1O_dataout; + nllO0O <= wire_n1O0i_dataout; + nllO1i <= wire_n1lOl_dataout; + nllO1l <= wire_n1lOO_dataout; + nllO1O <= wire_n1O1i_dataout; + nllOii <= wire_n1O0l_dataout; + nllOil <= wire_n1O0O_dataout; + nllOiO <= wire_n1Oii_dataout; + nllOli <= wire_n01Oi_dataout; + nllOll <= wire_n01ll_dataout; + nllOlO <= wire_n011O_dataout; + nllOOi <= wire_n010l_dataout; + nllOOl <= wire_n010O_dataout; + nllOOO <= wire_n01iO_dataout; + nlO01l <= wire_n01li_dataout; + nlO10i <= wire_n1Oll_dataout; + nlO10l <= wire_n1OlO_dataout; + nlO10O <= wire_n1OOi_dataout; + nlO11i <= wire_n1Oil_dataout; + nlO11l <= wire_n1OiO_dataout; + nlO11O <= wire_n1Oli_dataout; + nlO1ii <= wire_n1OOl_dataout; + nlO1il <= wire_n1OOO_dataout; + nlO1iO <= wire_n011i_dataout; + nlO1li <= wire_n011l_dataout; + nlO1ll <= wire_n01Ol_dataout; + nlO1lO <= wire_n01lO_dataout; + nlO1Oi <= wire_n010i_dataout; + nlO1Ol <= wire_n01ii_dataout; + nlO1OO <= wire_n01il_dataout; + END IF; + END IF; + END PROCESS; + wire_nlO01i_CLRN <= ((nl1111i44 XOR nl1111i43) AND wire_w_lg_soft_reset607w(0)); + wire_nlO01i_PRN <= (niOOOOO46 XOR niOOOOO45); + PROCESS (clk_2, wire_nlO1i1i_PRN, wire_nlO1i1i_CLRN) + BEGIN + IF (wire_nlO1i1i_PRN = '0') THEN + nlO1i1l <= '1'; + ELSIF (wire_nlO1i1i_CLRN = '0') THEN + nlO1i1l <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + nlO1i1l <= wire_nlO1i0i_dataout; + END IF; + END PROCESS; + wire_nlO1i1i_CLRN <= (niOlO1i56 XOR niOlO1i55); + wire_nlO1i1i_PRN <= ((niOllOO58 XOR niOllOO57) AND wire_w_lg_soft_reset607w(0)); + wire_nlO1i1i_w_lg_nlO1i1l613w(0) <= NOT nlO1i1l; + PROCESS (clk_2, soft_reset) + BEGIN + IF (soft_reset = '1') THEN + nliO1O <= '0'; + nlO00i <= '0'; + nlO00l <= '0'; + nlO00O <= '0'; + nlO01O <= '0'; + nlO0ii <= '0'; + nlO0il <= '0'; + nlO0iO <= '0'; + nlO0li <= '0'; + nlO0ll <= '0'; + nlO0lO <= '0'; + nlO0Oi <= '0'; + nlO0Ol <= '0'; + nlO0OO <= '0'; + nlOi0i <= '0'; + nlOi0l <= '0'; + nlOi0O <= '0'; + nlOi1i <= '0'; + nlOi1l <= '0'; + nlOi1O <= '0'; + nlOiii <= '0'; + nlOiil <= '0'; + nlOiiO <= '0'; + nlOili <= '0'; + nlOill <= '0'; + nlOilO <= '0'; + nlOiOi <= '0'; + nlOiOl <= '0'; + nlOiOO <= '0'; + nlOl0l <= '0'; + nlOl1i <= '0'; + nlOl1l <= '0'; + nlOl1O <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + IF (nl1110i = '1') THEN + nliO1O <= nl1111O; + nlO00i <= wire_n1lOl_dataout; + nlO00l <= wire_n1lOO_dataout; + nlO00O <= wire_n1O1i_dataout; + nlO01O <= wire_n1lOi_dataout; + nlO0ii <= wire_n1O1l_dataout; + nlO0il <= wire_n1O1O_dataout; + nlO0iO <= wire_n1O0i_dataout; + nlO0li <= wire_n1O0l_dataout; + nlO0ll <= wire_n1O0O_dataout; + nlO0lO <= wire_n1Oii_dataout; + nlO0Oi <= wire_n01Oi_dataout; + nlO0Ol <= wire_n01ll_dataout; + nlO0OO <= wire_n011O_dataout; + nlOi0i <= wire_n1Oil_dataout; + nlOi0l <= wire_n1OiO_dataout; + nlOi0O <= wire_n1Oli_dataout; + nlOi1i <= wire_n010l_dataout; + nlOi1l <= wire_n010O_dataout; + nlOi1O <= wire_n01iO_dataout; + nlOiii <= wire_n1Oll_dataout; + nlOiil <= wire_n1OlO_dataout; + nlOiiO <= wire_n1OOi_dataout; + nlOili <= wire_n1OOl_dataout; + nlOill <= wire_n1OOO_dataout; + nlOilO <= wire_n011i_dataout; + nlOiOi <= wire_n011l_dataout; + nlOiOl <= wire_n01Ol_dataout; + nlOiOO <= wire_n01lO_dataout; + nlOl0l <= wire_n01li_dataout; + nlOl1i <= wire_n010i_dataout; + nlOl1l <= wire_n01ii_dataout; + nlOl1O <= wire_n01il_dataout; + END IF; + END IF; + END PROCESS; + wire_n0000i_dataout <= wire_n0illl_dataout WHEN niOOliO = '1' ELSE wire_n0i1il_o; + wire_n0000l_dataout <= wire_n0illO_dataout WHEN niOOliO = '1' ELSE wire_n0i1iO_o; + wire_n0000O_dataout <= wire_n0ilOi_dataout WHEN niOOliO = '1' ELSE wire_n0i1li_o; + wire_n0001i_dataout <= wire_n0ilil_dataout WHEN niOOliO = '1' ELSE wire_n0i10l_o; + wire_n0001l_dataout <= wire_n0iliO_dataout WHEN niOOliO = '1' ELSE wire_n0i10O_o; + wire_n0001O_dataout <= wire_n0illi_dataout WHEN niOOliO = '1' ELSE wire_n0i1ii_o; + wire_n000i_dataout <= sync_resync_pre(0) WHEN nl101Ol = '1' ELSE sync_resync_delay(0); + wire_n000ii_dataout <= wire_n0ilOl_dataout WHEN niOOliO = '1' ELSE wire_n0i1ll_o; + wire_n000il_dataout <= wire_n0ilOO_dataout WHEN niOOliO = '1' ELSE wire_n0i1lO_o; + wire_n000iO_dataout <= wire_n0iO1i_dataout WHEN niOOliO = '1' ELSE wire_n0i1Oi_o; + wire_n000l_dataout <= sync_resync_pre(1) WHEN nl101Ol = '1' ELSE sync_resync_delay(1); + wire_n000li_dataout <= wire_n0iO1l_dataout WHEN niOOliO = '1' ELSE wire_n0i1Ol_o; + wire_n000ll_dataout <= wire_n0iO1O_dataout WHEN niOOliO = '1' ELSE wire_n0i1OO_o; + wire_n000lO_dataout <= wire_n0iO0i_dataout WHEN niOOliO = '1' ELSE wire_n0i01i_o; + wire_n000O_dataout <= wire_ni01i_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(0); + wire_n000Oi_dataout <= wire_n0iO0l_dataout WHEN niOOliO = '1' ELSE wire_n0i01l_o; + wire_n000Ol_dataout <= wire_n0iOii_dataout WHEN niOOliO = '1' ELSE wire_n0i01O_o; + wire_n000OO_dataout <= wire_n0iOil_dataout WHEN niOOliO = '1' ELSE wire_n0i00i_o; + wire_n0010i_dataout <= nill0l WHEN niOOliO = '1' ELSE wire_n00Oil_o; + wire_n0010l_dataout <= nill0O WHEN niOOliO = '1' ELSE wire_n00OiO_o; + wire_n0010O_dataout <= nillii WHEN niOOliO = '1' ELSE wire_n00Oli_o; + wire_n0011i_dataout <= nill1l WHEN niOOliO = '1' ELSE wire_n00O0l_o; + wire_n0011l_dataout <= nill1O WHEN niOOliO = '1' ELSE wire_n00O0O_o; + wire_n0011O_dataout <= nill0i WHEN niOOliO = '1' ELSE wire_n00Oii_o; + wire_n001ii_dataout <= nillil WHEN niOOliO = '1' ELSE wire_n00Oll_o; + wire_n001il_dataout <= nilliO WHEN niOOliO = '1' ELSE wire_n00OlO_o; + wire_n001iO_dataout <= nillli WHEN niOOliO = '1' ELSE wire_n00OOi_o; + wire_n001l_dataout <= wire_nli1l_o AND NOT((wire_w_lg_rsync_sm_dis1w(0) AND wire_nlilOi_w_lg_dataout523w(0))); + wire_n001li_dataout <= nillll WHEN niOOliO = '1' ELSE wire_n00OOl_o; + wire_n001ll_dataout <= nilllO WHEN niOOliO = '1' ELSE wire_n00OOO_o; + wire_n001lO_dataout <= nillOi WHEN niOOliO = '1' ELSE wire_n0i11i_o; + wire_n001Oi_dataout <= wire_n0il0l_dataout WHEN niOOliO = '1' ELSE wire_n0i11l_o; + wire_n001Ol_dataout <= wire_n0il0O_dataout WHEN niOOliO = '1' ELSE wire_n0i11O_o; + wire_n001OO_dataout <= wire_n0ilii_dataout WHEN niOOliO = '1' ELSE wire_n0i10i_o; + wire_n00i_dataout <= wire_nlO1O0O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(14); + wire_n00i0i_dataout <= wire_n0iOlO_dataout WHEN niOOliO = '1' ELSE wire_n0i0il_o; + wire_n00i0l_dataout <= wire_n0iOOi_dataout WHEN niOOliO = '1' ELSE wire_n0i0iO_o; + wire_n00i0O_dataout <= wire_n0iOOl_dataout WHEN niOOliO = '1' ELSE wire_n0i0li_o; + wire_n00i1i_dataout <= wire_n0iOiO_dataout WHEN niOOliO = '1' ELSE wire_n0i00l_o; + wire_n00i1l_dataout <= wire_n0iOli_dataout WHEN niOOliO = '1' ELSE wire_n0i00O_o; + wire_n00i1O_dataout <= wire_n0iOll_dataout WHEN niOOliO = '1' ELSE wire_n0i0ii_o; + wire_n00ii_dataout <= wire_ni01l_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(1); + wire_n00iii_dataout <= wire_n0iOOO_dataout WHEN niOOliO = '1' ELSE wire_n0i0ll_o; + wire_n00iil_dataout <= wire_n0l11i_dataout WHEN niOOliO = '1' ELSE wire_n0i0lO_o; + wire_n00iiO_dataout <= wire_n0l11l_o WHEN niOOliO = '1' ELSE wire_n0i0Oi_o; + wire_n00il_dataout <= wire_ni01O_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(2); + wire_n00ili_dataout <= wire_n0l11O_dataout WHEN niOOliO = '1' ELSE wire_n0i0Ol_o; + wire_n00ill_dataout <= wire_n0l10i_dataout WHEN niOOliO = '1' ELSE wire_n0i0OO_o; + wire_n00ilO_dataout <= wire_n0l10l_dataout WHEN niOOliO = '1' ELSE wire_n0ii1i_o; + wire_n00iO_dataout <= wire_ni00i_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(3); + wire_n00iOi_dataout <= wire_n0l10O_dataout WHEN niOOliO = '1' ELSE wire_n0ii1l_o; + wire_n00iOl_dataout <= wire_n0l1ii_dataout WHEN niOOliO = '1' ELSE wire_n0ii1O_o; + wire_n00iOO_dataout <= wire_n0l1li_dataout WHEN niOOliO = '1' ELSE wire_n0ii0i_o; + wire_n00l_dataout <= wire_nlO1Oii_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(15); + wire_n00l0i_dataout <= wire_n0l1Ol_dataout WHEN niOOliO = '1' ELSE wire_n0iiil_o; + wire_n00l0l_dataout <= wire_n0l1OO_dataout WHEN niOOliO = '1' ELSE wire_n0iiiO_o; + wire_n00l0O_dataout <= wire_n0l01i_dataout WHEN niOOliO = '1' ELSE wire_n0iili_o; + wire_n00l1i_dataout <= wire_n0l1ll_dataout WHEN niOOliO = '1' ELSE wire_n0ii0l_o; + wire_n00l1l_dataout <= wire_n0l1lO_dataout WHEN niOOliO = '1' ELSE wire_n0ii0O_o; + wire_n00l1O_dataout <= wire_n0l1Oi_dataout WHEN niOOliO = '1' ELSE wire_n0iiii_o; + wire_n00li_dataout <= wire_ni00l_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(4); + wire_n00lii_dataout <= wire_n0l01l_dataout WHEN niOOliO = '1' ELSE wire_n0iill_o; + wire_n00lil_dataout <= wire_n0l01O_dataout WHEN niOOliO = '1' ELSE wire_n0iilO_o; + wire_n00liO_dataout <= wire_n0l00i_dataout WHEN niOOliO = '1' ELSE wire_n0iiOi_o; + wire_n00ll_dataout <= wire_ni00O_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(5); + wire_n00lli_dataout <= wire_n0l00l_o WHEN niOOliO = '1' ELSE wire_n0iiOl_o; + wire_n00lll_dataout <= wire_n0l00O_dataout WHEN niOOliO = '1' ELSE wire_n0iiOO_o; + wire_n00llO_dataout <= wire_n0l0ii_dataout WHEN niOOliO = '1' ELSE wire_n0il1i_o; + wire_n00lO_dataout <= wire_ni0ii_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(6); + wire_n00lOi_dataout <= wire_n0l0il_dataout WHEN niOOliO = '1' ELSE wire_n0il1l_o; + wire_n00lOl_dataout <= wire_n0l0iO_dataout WHEN niOOliO = '1' ELSE wire_n0il1O_o; + wire_n00lOO_dataout <= wire_n0l0li_dataout WHEN niOOliO = '1' ELSE wire_n0il0i_o; + wire_n00O_dataout <= wire_nlO1Oil_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(16); + wire_n00Oi_dataout <= wire_ni0il_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_rs(7); + wire_n00Ol_dataout <= wire_ni0iO_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_control_rs; + wire_n00OO_dataout <= wire_ni0li_dataout WHEN rendec_data_sel_rx = '1' ELSE (rx_control_rs AND wire_w_lg_nl111ll574w(0)); + wire_n0100i_dataout <= wire_nl1iOi_dataout AND NOT(niOlOii); + wire_n0100l_dataout <= wire_nl1iOl_dataout AND NOT(niOlOii); + wire_n0100O_dataout <= wire_nl1iOO_dataout AND NOT(niOlOii); + wire_n0101i_dataout <= wire_nl1ili_dataout AND NOT(niOlOii); + wire_n0101l_dataout <= wire_nl1ill_dataout AND NOT(niOlOii); + wire_n0101O_dataout <= wire_nl1ilO_dataout AND NOT(niOlOii); + wire_n010i_dataout <= wire_n0ilO_dataout WHEN endec_rx = '1' ELSE wire_n01OO_dataout; + wire_n010ii_dataout <= wire_nl1l1i_dataout AND NOT(niOlOii); + wire_n010il_dataout <= wire_nl1l1l_dataout AND NOT(niOlOii); + wire_n010iO_dataout <= rbytordpadval(0) WHEN niOlOil = '1' ELSE wire_niOOOO_dataout; + wire_n010l_dataout <= wire_n0iOi_dataout WHEN endec_rx = '1' ELSE ovr_undflow(0); + wire_n010li_dataout <= rbytordpadval(1) WHEN niOlOil = '1' ELSE wire_nl111i_dataout; + wire_n010ll_dataout <= rbytordpadval(2) WHEN niOlOil = '1' ELSE wire_nl111l_dataout; + wire_n010lO_dataout <= rbytordpadval(3) WHEN niOlOil = '1' ELSE wire_nl111O_dataout; + wire_n010O_dataout <= wire_n0iOl_dataout WHEN endec_rx = '1' ELSE ovr_undflow(1); + wire_n010Oi_dataout <= rbytordpadval(4) WHEN niOlOil = '1' ELSE wire_nl110i_dataout; + wire_n010Ol_dataout <= rbytordpadval(5) WHEN niOlOil = '1' ELSE wire_nl110l_dataout; + wire_n010OO_dataout <= rbytordpadval(6) WHEN niOlOil = '1' ELSE wire_nl110O_dataout; + wire_n0110i_dataout <= wire_nl10Oi_dataout AND NOT(niOlOii); + wire_n0110l_dataout <= wire_nl10Ol_dataout AND NOT(niOlOii); + wire_n0110O_dataout <= wire_nl10OO_dataout AND NOT(niOlOii); + wire_n0111i_dataout <= wire_nl10li_dataout AND NOT(niOlOii); + wire_n0111l_dataout <= wire_nl10ll_dataout AND NOT(niOlOii); + wire_n0111O_dataout <= wire_nl10lO_dataout AND NOT(niOlOii); + wire_n011i_dataout <= wire_n0iiO_dataout WHEN endec_rx = '1' ELSE tenb_data(18); + wire_n011ii_dataout <= wire_nl1i1i_dataout AND NOT(niOlOii); + wire_n011il_dataout <= wire_nl1i1l_dataout AND NOT(niOlOii); + wire_n011iO_dataout <= wire_nl1i1O_dataout AND NOT(niOlOii); + wire_n011l_dataout <= wire_n0ili_dataout WHEN endec_rx = '1' ELSE tenb_data(19); + wire_n011li_dataout <= wire_nl1i0i_dataout AND NOT(niOlOii); + wire_n011ll_dataout <= wire_nl1i0l_dataout AND NOT(niOlOii); + wire_n011lO_dataout <= wire_nl1i0O_dataout AND NOT(niOlOii); + wire_n011O_dataout <= wire_n0ill_dataout WHEN endec_rx = '1' ELSE wire_n001l_dataout; + wire_n011Oi_dataout <= wire_nl1iii_dataout AND NOT(niOlOii); + wire_n011Ol_dataout <= wire_nl1iil_dataout AND NOT(niOlOii); + wire_n011OO_dataout <= wire_nl1iiO_dataout AND NOT(niOlOii); + wire_n01i_dataout <= wire_nlO1O1O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(11); + wire_n01i0i_dataout <= wire_niOOiO_dataout WHEN niOlOil = '1' ELSE wire_nl11li_dataout; + wire_n01i0l_dataout <= wire_nl11ll_dataout AND NOT(niOlOil); + wire_n01i0O_dataout <= wire_nl11lO_dataout AND NOT(niOlOil); + wire_n01i1i_dataout <= rbytordpadval(7) WHEN niOlOil = '1' ELSE wire_nl11ii_dataout; + wire_n01i1l_dataout <= rbytordpadval(8) WHEN niOlOil = '1' ELSE wire_nl11il_dataout; + wire_n01i1O_dataout <= rbytordpadval(9) WHEN niOlOil = '1' ELSE wire_nl11iO_dataout; + wire_n01ii_dataout <= wire_n0iOO_dataout WHEN endec_rx = '1' ELSE ovr_undflow(2); + wire_n01iii_dataout <= wire_nl11Oi_dataout AND NOT(niOlOil); + wire_n01iil_dataout <= wire_nl11Ol_dataout AND NOT(niOlOil); + wire_n01iiO_dataout <= wire_nl11OO_dataout AND NOT(niOlOil); + wire_n01il_dataout <= wire_n0l1i_dataout WHEN endec_rx = '1' ELSE ovr_undflow(3); + wire_n01ili_dataout <= wire_nl101i_dataout AND NOT(niOlOil); + wire_n01ill_dataout <= wire_nl101l_dataout AND NOT(niOlOil); + wire_n01ilO_dataout <= wire_nl101O_dataout AND NOT(niOlOil); + wire_n01iO_dataout <= wire_n0l1l_dataout WHEN endec_rx = '1' ELSE disp_val_delay(0); + wire_n01iOi_dataout <= wire_nl100i_dataout AND NOT(niOlOil); + wire_n01iOl_dataout <= wire_nl100l_dataout AND NOT(niOlOil); + wire_n01iOO_dataout <= wire_nl100O_dataout AND NOT(niOlOil); + wire_n01l_dataout <= wire_nlO1O0i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(12); + wire_n01l0i_dataout <= wire_nl10li_dataout AND NOT(niOlOil); + wire_n01l0l_dataout <= wire_nl10ll_dataout AND NOT(niOlOil); + wire_n01l0O_dataout <= wire_nl10lO_dataout AND NOT(niOlOil); + wire_n01l1i_dataout <= wire_nl10ii_dataout AND NOT(niOlOil); + wire_n01l1l_dataout <= wire_nl10il_dataout AND NOT(niOlOil); + wire_n01l1O_dataout <= wire_nl10iO_dataout AND NOT(niOlOil); + wire_n01li_dataout <= wire_n0l1O_dataout WHEN endec_rx = '1' ELSE disp_val_delay(1); + wire_n01lii_dataout <= wire_nl10Oi_dataout AND NOT(niOlOil); + wire_n01lil_dataout <= wire_nl10Ol_dataout AND NOT(niOlOil); + wire_n01liO_dataout <= wire_nl10OO_dataout AND NOT(niOlOil); + wire_n01ll_dataout <= wire_n0l0i_dataout WHEN endec_rx = '1' ELSE disp_err_delay(0); + wire_n01lli_dataout <= wire_nl1i1i_dataout AND NOT(niOlOil); + wire_n01lll_dataout <= wire_nl1i1l_dataout AND NOT(niOlOil); + wire_n01llO_dataout <= wire_nl1i1O_dataout AND NOT(niOlOil); + wire_n01lO_dataout <= wire_n0l0l_dataout WHEN endec_rx = '1' ELSE disp_err_delay(1); + wire_n01lOi_dataout <= wire_nl1i0i_dataout AND NOT(niOlOil); + wire_n01lOl_dataout <= wire_nl1i0l_dataout AND NOT(niOlOil); + wire_n01lOO_dataout <= wire_nl1i0O_dataout AND NOT(niOlOil); + wire_n01O_dataout <= wire_nlO1O0l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(13); + wire_n01O0i_dataout <= wire_nl1ili_dataout AND NOT(niOlOil); + wire_n01O0l_dataout <= wire_nl1ill_dataout AND NOT(niOlOil); + wire_n01O0O_dataout <= wire_nl1ilO_dataout AND NOT(niOlOil); + wire_n01O1i_dataout <= wire_nl1iii_dataout AND NOT(niOlOil); + wire_n01O1l_dataout <= wire_nl1iil_dataout AND NOT(niOlOil); + wire_n01O1O_dataout <= wire_nl1iiO_dataout AND NOT(niOlOil); + wire_n01Oi_dataout <= wire_n0l0O_dataout WHEN endec_rx = '1' ELSE wire_n000i_dataout; + wire_n01Oii_dataout <= wire_nl1iOi_dataout AND NOT(niOlOil); + wire_n01Oil_dataout <= wire_nl1iOl_dataout AND NOT(niOlOil); + wire_n01OiO_dataout <= wire_nl1iOO_dataout AND NOT(niOlOil); + wire_n01Ol_dataout <= wire_n0lii_dataout WHEN endec_rx = '1' ELSE wire_n000l_dataout; + wire_n01Oli_dataout <= wire_nl1l1i_dataout AND NOT(niOlOil); + wire_n01Oll_dataout <= wire_nl1l1l_dataout AND NOT(niOlOil); + wire_n01OlO_dataout <= niliOi WHEN niOOliO = '1' ELSE wire_n00O1i_o; + wire_n01OO_dataout <= wire_niO1l_o AND NOT((wire_w_lg_rsync_sm_dis1w(0) AND wire_nlilOl_w_lg_dataout545w(0))); + wire_n01OOi_dataout <= niliOl WHEN niOOliO = '1' ELSE wire_n00O1l_o; + wire_n01OOl_dataout <= niliOO WHEN niOOliO = '1' ELSE wire_n00O1O_o; + wire_n01OOO_dataout <= nill1i WHEN niOOliO = '1' ELSE wire_n00O0i_o; + wire_n0i_dataout <= wire_nlO0i0O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(59); + wire_n0i0i_dataout <= wire_n0lOi_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(11); + wire_n0i0l_dataout <= wire_n0lOl_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(12); + wire_n0i0O_dataout <= wire_n0lOO_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(13); + wire_n0i1i_dataout <= wire_n0lli_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(8); + wire_n0i1l_dataout <= wire_n0lll_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(9); + wire_n0i1O_dataout <= wire_n0llO_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(10); + wire_n0ii_dataout <= wire_nlO1OiO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(17); + wire_n0iii_dataout <= wire_n0O1i_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(14); + wire_n0iil_dataout <= wire_n0O1l_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_data_dt(15); + wire_n0iiO_dataout <= wire_n0O1O_dataout WHEN rendec_data_sel_rx = '1' ELSE rx_control_dt(1); + wire_n0il_dataout <= wire_nlO1Oli_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(18); + wire_n0il0l_dataout <= rbytordpadval(0) WHEN wire_n0iO0O_o(2) = '1' ELSE nillOl; + wire_n0il0O_dataout <= rbytordpadval(1) WHEN wire_n0iO0O_o(2) = '1' ELSE nillOO; + wire_n0ili_dataout <= wire_n0O0i_dataout WHEN rendec_data_sel_rx = '1' ELSE wire_nli_dataout; + wire_n0ilii_dataout <= rbytordpadval(2) WHEN wire_n0iO0O_o(2) = '1' ELSE nilO1i; + wire_n0ilil_dataout <= rbytordpadval(3) WHEN wire_n0iO0O_o(2) = '1' ELSE nilO1l; + wire_n0iliO_dataout <= rbytordpadval(4) WHEN wire_n0iO0O_o(2) = '1' ELSE nilO1O; + wire_n0ill_dataout <= wire_ni0ll_dataout WHEN rendec_data_sel_rx = '1' ELSE nll10O; + wire_n0illi_dataout <= rbytordpadval(5) WHEN wire_n0iO0O_o(2) = '1' ELSE nilO0i; + wire_n0illl_dataout <= rbytordpadval(6) WHEN wire_n0iO0O_o(2) = '1' ELSE nilO0l; + wire_n0illO_dataout <= rbytordpadval(7) WHEN wire_n0iO0O_o(2) = '1' ELSE nilO0O; + wire_n0ilO_dataout <= wire_n0O0l_dataout WHEN rendec_data_sel_rx = '1' ELSE nll1ii; + wire_n0ilOi_dataout <= rbytordpadval(8) WHEN wire_n0iO0O_o(2) = '1' ELSE nilOii; + wire_n0ilOl_dataout <= rbytordpadval(9) WHEN wire_n0iO0O_o(2) = '1' ELSE nilOil; + wire_n0ilOO_dataout <= nillil WHEN wire_n0iO0O_o(2) = '1' ELSE nilOiO; + wire_n0iO_dataout <= wire_nlO1Oll_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(19); + wire_n0iO0i_dataout <= nilOOi AND NOT(wire_n0iO0O_o(2)); + wire_n0iO0l_dataout <= nilOOl AND NOT(wire_n0iO0O_o(2)); + wire_n0iO1i_dataout <= nilOli AND NOT(wire_n0iO0O_o(2)); + wire_n0iO1l_dataout <= nilOll AND NOT(wire_n0iO0O_o(2)); + wire_n0iO1O_dataout <= nilOlO AND NOT(wire_n0iO0O_o(2)); + wire_n0iOi_dataout <= ovr_undflow(0) WHEN rendec_data_sel_rx = '1' ELSE nliO0l; + wire_n0iOii_dataout <= rbytordpadval(0) WHEN niOlOiO = '1' ELSE nilOOO; + wire_n0iOil_dataout <= rbytordpadval(1) WHEN niOlOiO = '1' ELSE niO11i; + wire_n0iOiO_dataout <= rbytordpadval(2) WHEN niOlOiO = '1' ELSE niO11l; + wire_n0iOl_dataout <= ovr_undflow(1) WHEN rendec_data_sel_rx = '1' ELSE nliO0O; + wire_n0iOli_dataout <= rbytordpadval(3) WHEN niOlOiO = '1' ELSE niO11O; + wire_n0iOll_dataout <= rbytordpadval(4) WHEN niOlOiO = '1' ELSE niO10i; + wire_n0iOlO_dataout <= rbytordpadval(5) WHEN niOlOiO = '1' ELSE niO10l; + wire_n0iOO_dataout <= ovr_undflow(2) WHEN rendec_data_sel_rx = '1' ELSE nliOii; + wire_n0iOOi_dataout <= rbytordpadval(6) WHEN niOlOiO = '1' ELSE niO10O; + wire_n0iOOl_dataout <= rbytordpadval(7) WHEN niOlOiO = '1' ELSE niO1ii; + wire_n0iOOO_dataout <= rbytordpadval(8) WHEN niOlOiO = '1' ELSE niO1il; + wire_n0l_dataout <= wire_nlO0iii_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(60); + wire_n0l00i_dataout <= rbytordpadval(9) WHEN niOlOli = '1' ELSE niO0li; + wire_n0l00O_dataout <= niO0lO AND NOT(niOlOli); + wire_n0l01i_dataout <= rbytordpadval(6) WHEN niOlOli = '1' ELSE niO0ii; + wire_n0l01l_dataout <= rbytordpadval(7) WHEN niOlOli = '1' ELSE niO0il; + wire_n0l01O_dataout <= rbytordpadval(8) WHEN niOlOli = '1' ELSE niO0iO; + wire_n0l0i_dataout <= disp_err_delay(0) WHEN rendec_data_sel_rx = '1' ELSE nll00l; + wire_n0l0ii_dataout <= niO0Oi AND NOT(niOlOli); + wire_n0l0il_dataout <= niO0Ol AND NOT(niOlOli); + wire_n0l0iO_dataout <= niO0OO AND NOT(niOlOli); + wire_n0l0l_dataout <= disp_err_delay(1) WHEN rendec_data_sel_rx = '1' ELSE nll00O; + wire_n0l0li_dataout <= niOi1i AND NOT(niOlOli); + wire_n0l0O_dataout <= wire_n000i_dataout WHEN rendec_data_sel_rx = '1' ELSE nll0iO; + wire_n0l0Oi_dataout <= wire_niOlOl_dataout WHEN niOOliO = '1' ELSE wire_n0O01l_o; + wire_n0l0Ol_dataout <= wire_niOlOO_dataout WHEN niOOliO = '1' ELSE wire_n0O01O_o; + wire_n0l0OO_dataout <= wire_niOO1i_dataout WHEN niOOliO = '1' ELSE wire_n0O00i_o; + wire_n0l10i_dataout <= niO1lO AND NOT(niOlOiO); + wire_n0l10l_dataout <= niO1Oi AND NOT(niOlOiO); + wire_n0l10O_dataout <= niO1Ol AND NOT(niOlOiO); + wire_n0l11i_dataout <= rbytordpadval(9) WHEN niOlOiO = '1' ELSE niO1iO; + wire_n0l11O_dataout <= niO1ll AND NOT(niOlOiO); + wire_n0l1i_dataout <= ovr_undflow(3) WHEN rendec_data_sel_rx = '1' ELSE nliOil; + wire_n0l1ii_dataout <= niO1OO AND NOT(niOlOiO); + wire_n0l1l_dataout <= disp_val_delay(0) WHEN rendec_data_sel_rx = '1' ELSE nll01i; + wire_n0l1li_dataout <= rbytordpadval(0) WHEN niOlOli = '1' ELSE niO01i; + wire_n0l1ll_dataout <= rbytordpadval(1) WHEN niOlOli = '1' ELSE niO01l; + wire_n0l1lO_dataout <= rbytordpadval(2) WHEN niOlOli = '1' ELSE niO01O; + wire_n0l1O_dataout <= disp_val_delay(1) WHEN rendec_data_sel_rx = '1' ELSE nll01l; + wire_n0l1Oi_dataout <= rbytordpadval(3) WHEN niOlOli = '1' ELSE niO00i; + wire_n0l1Ol_dataout <= rbytordpadval(4) WHEN niOlOli = '1' ELSE niO00l; + wire_n0l1OO_dataout <= rbytordpadval(5) WHEN niOlOli = '1' ELSE niO00O; + wire_n0li_dataout <= wire_nlO1OlO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(20); + wire_n0li0i_dataout <= wire_niOO0l_dataout WHEN niOOliO = '1' ELSE wire_n0O0il_o; + wire_n0li0l_dataout <= wire_niOO0O_dataout WHEN niOOliO = '1' ELSE wire_n0O0iO_o; + wire_n0li0O_dataout <= wire_niOOii_dataout WHEN niOOliO = '1' ELSE wire_n0O0li_o; + wire_n0li1i_dataout <= wire_niOO1l_dataout WHEN niOOliO = '1' ELSE wire_n0O00l_o; + wire_n0li1l_dataout <= wire_niOO1O_dataout WHEN niOOliO = '1' ELSE wire_n0O00O_o; + wire_n0li1O_dataout <= wire_niOO0i_dataout WHEN niOOliO = '1' ELSE wire_n0O0ii_o; + wire_n0lii_dataout <= wire_n000l_dataout WHEN rendec_data_sel_rx = '1' ELSE nll0li; + wire_n0liii_dataout <= wire_niOOil_dataout WHEN niOOliO = '1' ELSE wire_n0O0ll_o; + wire_n0liil_dataout <= wire_niOOiO_dataout WHEN niOOliO = '1' ELSE wire_n0O0lO_o; + wire_n0liiO_dataout <= wire_niOOli_dataout WHEN niOOliO = '1' ELSE wire_n0O0Oi_o; + wire_n0lili_dataout <= wire_niOOll_dataout WHEN niOOliO = '1' ELSE wire_n0O0Ol_o; + wire_n0lill_dataout <= wire_niOOlO_dataout WHEN niOOliO = '1' ELSE wire_n0O0OO_o; + wire_n0lilO_dataout <= wire_niOOOi_dataout WHEN niOOliO = '1' ELSE wire_n0Oi1i_o; + wire_n0liOi_dataout <= wire_niOOOl_dataout WHEN niOOliO = '1' ELSE wire_n0Oi1l_o; + wire_n0liOl_dataout <= wire_ni110O_dataout WHEN niOOliO = '1' ELSE wire_n0Oi1O_o; + wire_n0liOO_dataout <= wire_ni11ii_dataout WHEN niOOliO = '1' ELSE wire_n0Oi0i_o; + wire_n0ll_dataout <= wire_nlO1OOi_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(21); + wire_n0ll0i_dataout <= wire_ni11ll_dataout WHEN niOOliO = '1' ELSE wire_n0Oiil_o; + wire_n0ll0l_dataout <= wire_ni11lO_dataout WHEN niOOliO = '1' ELSE wire_n0OiiO_o; + wire_n0ll0O_dataout <= wire_ni11Oi_dataout WHEN niOOliO = '1' ELSE wire_n0Oili_o; + wire_n0ll1i_dataout <= wire_ni11il_dataout WHEN niOOliO = '1' ELSE wire_n0Oi0l_o; + wire_n0ll1l_dataout <= wire_ni11iO_dataout WHEN niOOliO = '1' ELSE wire_n0Oi0O_o; + wire_n0ll1O_dataout <= wire_ni11li_dataout WHEN niOOliO = '1' ELSE wire_n0Oiii_o; + wire_n0lli_dataout <= wire_ni10i_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0O0O_dataout; + wire_n0llii_dataout <= wire_ni11Ol_dataout WHEN niOOliO = '1' ELSE wire_n0Oill_o; + wire_n0llil_dataout <= wire_ni11OO_dataout WHEN niOOliO = '1' ELSE wire_n0OilO_o; + wire_n0lliO_dataout <= wire_ni101i_dataout WHEN niOOliO = '1' ELSE wire_n0OiOi_o; + wire_n0lll_dataout <= wire_ni10l_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0Oii_dataout; + wire_n0llli_dataout <= wire_ni101l_dataout WHEN niOOliO = '1' ELSE wire_n0OiOl_o; + wire_n0llll_dataout <= wire_ni101O_dataout WHEN niOOliO = '1' ELSE wire_n0OiOO_o; + wire_n0lllO_dataout <= wire_ni100i_dataout WHEN niOOliO = '1' ELSE wire_n0Ol1i_o; + wire_n0llO_dataout <= wire_ni10O_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0Oil_dataout; + wire_n0llOi_dataout <= wire_ni100l_dataout WHEN niOOliO = '1' ELSE wire_n0Ol1l_o; + wire_n0llOl_dataout <= wire_ni100O_dataout WHEN niOOliO = '1' ELSE wire_n0Ol1O_o; + wire_n0llOO_dataout <= wire_ni10ii_dataout WHEN niOOliO = '1' ELSE wire_n0Ol0i_o; + wire_n0lO_dataout <= wire_nlO1OOl_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(22); + wire_n0lO0i_dataout <= wire_ni10ll_dataout WHEN niOOliO = '1' ELSE wire_n0Olil_o; + wire_n0lO0l_dataout <= wire_ni10lO_dataout WHEN niOOliO = '1' ELSE wire_n0OliO_o; + wire_n0lO0O_dataout <= wire_ni10Oi_dataout WHEN niOOliO = '1' ELSE wire_n0Olli_o; + wire_n0lO1i_dataout <= wire_ni10il_dataout WHEN niOOliO = '1' ELSE wire_n0Ol0l_o; + wire_n0lO1l_dataout <= wire_ni10iO_dataout WHEN niOOliO = '1' ELSE wire_n0Ol0O_o; + wire_n0lO1O_dataout <= wire_ni10li_dataout WHEN niOOliO = '1' ELSE wire_n0Olii_o; + wire_n0lOi_dataout <= wire_ni1ii_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0OiO_dataout; + wire_n0lOii_dataout <= wire_ni10Ol_dataout WHEN niOOliO = '1' ELSE wire_n0Olll_o; + wire_n0lOil_dataout <= wire_ni10OO_dataout WHEN niOOliO = '1' ELSE wire_n0OllO_o; + wire_n0lOiO_dataout <= wire_ni1i1i_dataout WHEN niOOliO = '1' ELSE wire_n0OlOi_o; + wire_n0lOl_dataout <= wire_ni1il_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0Oli_dataout; + wire_n0lOli_dataout <= wire_ni1i1l_o WHEN niOOliO = '1' ELSE wire_n0OlOl_o; + wire_n0lOll_dataout <= wire_ni1i1O_dataout WHEN niOOliO = '1' ELSE wire_n0OlOO_o; + wire_n0lOlO_dataout <= wire_ni1i0i_dataout WHEN niOOliO = '1' ELSE wire_n0OO1i_o; + wire_n0lOO_dataout <= wire_ni1iO_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0Oll_dataout; + wire_n0lOOi_dataout <= wire_ni1i0l_dataout WHEN niOOliO = '1' ELSE wire_n0OO1l_o; + wire_n0lOOl_dataout <= wire_ni1i0O_dataout WHEN niOOliO = '1' ELSE wire_n0OO1O_o; + wire_n0lOOO_dataout <= wire_ni1iii_dataout WHEN niOOliO = '1' ELSE wire_n0OO0i_o; + wire_n0O_dataout <= wire_nlO0iil_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(61); + wire_n0O01i_dataout <= wire_ni1lil_dataout WHEN niOOliO = '1' ELSE wire_ni110l_o; + wire_n0O0i_dataout <= wire_ni1Oi_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_nli_dataout; + wire_n0O0l_dataout <= wire_ni1Ol_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_niO1l_o; + wire_n0O0O_dataout <= rclkcmpinsertpad WHEN nl111lO = '1' ELSE rx_data_dt(8); + wire_n0O10i_dataout <= wire_ni1ill_dataout WHEN niOOliO = '1' ELSE wire_n0OOil_o; + wire_n0O10l_dataout <= wire_ni1ilO_dataout WHEN niOOliO = '1' ELSE wire_n0OOiO_o; + wire_n0O10O_dataout <= wire_ni1iOi_dataout WHEN niOOliO = '1' ELSE wire_n0OOli_o; + wire_n0O11i_dataout <= wire_ni1iil_dataout WHEN niOOliO = '1' ELSE wire_n0OO0l_o; + wire_n0O11l_dataout <= wire_ni1iiO_dataout WHEN niOOliO = '1' ELSE wire_n0OO0O_o; + wire_n0O11O_dataout <= wire_ni1ili_dataout WHEN niOOliO = '1' ELSE wire_n0OOii_o; + wire_n0O1i_dataout <= wire_ni1li_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0OlO_dataout; + wire_n0O1ii_dataout <= wire_ni1iOl_dataout WHEN niOOliO = '1' ELSE wire_n0OOll_o; + wire_n0O1il_dataout <= wire_ni1iOO_dataout WHEN niOOliO = '1' ELSE wire_n0OOlO_o; + wire_n0O1iO_dataout <= wire_ni1l1i_dataout WHEN niOOliO = '1' ELSE wire_n0OOOi_o; + wire_n0O1l_dataout <= wire_ni1ll_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0OOi_dataout; + wire_n0O1li_dataout <= wire_ni1l1l_dataout WHEN niOOliO = '1' ELSE wire_n0OOOl_o; + wire_n0O1ll_dataout <= wire_ni1l1O_o WHEN niOOliO = '1' ELSE wire_n0OOOO_o; + wire_n0O1lO_dataout <= wire_ni1l0i_dataout WHEN niOOliO = '1' ELSE wire_ni111i_o; + wire_n0O1O_dataout <= wire_ni1lO_dataout WHEN wire_nlilOl_w_lg_dataout545w(0) = '1' ELSE wire_n0OOl_dataout; + wire_n0O1Oi_dataout <= wire_ni1l0l_dataout WHEN niOOliO = '1' ELSE wire_ni111l_o; + wire_n0O1Ol_dataout <= wire_ni1l0O_dataout WHEN niOOliO = '1' ELSE wire_ni111O_o; + wire_n0O1OO_dataout <= wire_ni1lii_dataout WHEN niOOliO = '1' ELSE wire_ni110i_o; + wire_n0Oi_dataout <= wire_nlO1OOO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(23); + wire_n0Oii_dataout <= rx_data_dt(9) OR nl111lO; + wire_n0Oil_dataout <= rx_data_dt(10) OR nl111lO; + wire_n0OiO_dataout <= wire_w_lg_rclkcmpinsertpad522w(0) WHEN nl111lO = '1' ELSE rx_data_dt(11); + wire_n0Ol_dataout <= wire_nlO011i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(24); + wire_n0Oli_dataout <= rx_data_dt(12) OR nl111lO; + wire_n0Oll_dataout <= rx_data_dt(13) OR nl111lO; + wire_n0OlO_dataout <= rx_data_dt(14) OR nl111lO; + wire_n0OO_dataout <= wire_nlO011l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(25); + wire_n0OOi_dataout <= rx_data_dt(15) OR nl111lO; + wire_n0OOl_dataout <= rx_control_dt(1) OR nl111lO; + wire_n1000i_dataout <= wire_nl1l1l_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1000l_dataout <= niliOi WHEN niOlO0O = '1' ELSE wire_n1i1iO_dataout; + wire_n1000O_dataout <= niliOl WHEN niOlO0O = '1' ELSE wire_n1i1li_dataout; + wire_n1001i_dataout <= wire_nl1iOl_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1001l_dataout <= wire_nl1iOO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1001O_dataout <= wire_nl1l1i_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n100ii_dataout <= niliOO WHEN niOlO0O = '1' ELSE wire_n1i1ll_dataout; + wire_n100il_dataout <= nill1i WHEN niOlO0O = '1' ELSE wire_n1i1lO_dataout; + wire_n100iO_dataout <= nill1l WHEN niOlO0O = '1' ELSE wire_n1i1Oi_dataout; + wire_n100li_dataout <= nill1O WHEN niOlO0O = '1' ELSE wire_n1i1Ol_dataout; + wire_n100ll_dataout <= nill0i WHEN niOlO0O = '1' ELSE wire_n1i1OO_dataout; + wire_n100lO_dataout <= nill0l WHEN niOlO0O = '1' ELSE wire_n1i01i_dataout; + wire_n100Oi_dataout <= nill0O WHEN niOlO0O = '1' ELSE wire_n1i01l_dataout; + wire_n100Ol_dataout <= nillii WHEN niOlO0O = '1' ELSE wire_n1i01O_dataout; + wire_n100OO_dataout <= nillil WHEN niOlO0O = '1' ELSE wire_n1i00i_dataout; + wire_n1010i_dataout <= wire_nl1i1l_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1010l_dataout <= wire_nl1i1O_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1010O_dataout <= wire_nl1i0i_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1011i_dataout <= wire_nl10Ol_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1011l_dataout <= wire_nl10OO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1011O_dataout <= wire_nl1i1i_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101ii_dataout <= wire_nl1i0l_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101il_dataout <= wire_nl1i0O_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101iO_dataout <= wire_nl1iii_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101li_dataout <= wire_nl1iil_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101ll_dataout <= wire_nl1iiO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101lO_dataout <= wire_nl1ili_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101Oi_dataout <= wire_nl1ill_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101Ol_dataout <= wire_nl1ilO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n101OO_dataout <= wire_nl1iOi_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n10i_dataout <= wire_nlO0i1O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(56); + wire_n10i0i_dataout <= nilllO WHEN niOlO0O = '1' ELSE wire_n1i0il_dataout; + wire_n10i0l_dataout <= nillOi WHEN niOlO0O = '1' ELSE wire_n1i0iO_dataout; + wire_n10i0O_dataout <= wire_n1iOOi_dataout WHEN niOlO0O = '1' ELSE wire_n1i0li_dataout; + wire_n10i1i_dataout <= nilliO WHEN niOlO0O = '1' ELSE wire_n1i00l_dataout; + wire_n10i1l_dataout <= nillli WHEN niOlO0O = '1' ELSE wire_n1i00O_dataout; + wire_n10i1O_dataout <= nillll WHEN niOlO0O = '1' ELSE wire_n1i0ii_dataout; + wire_n10iii_dataout <= wire_n1iOOl_dataout WHEN niOlO0O = '1' ELSE wire_n1i0ll_dataout; + wire_n10iil_dataout <= wire_n1iOOO_dataout WHEN niOlO0O = '1' ELSE wire_n1i0lO_dataout; + wire_n10iiO_dataout <= wire_n1l11i_dataout WHEN niOlO0O = '1' ELSE wire_n1i0Oi_dataout; + wire_n10ili_dataout <= wire_n1l11l_dataout WHEN niOlO0O = '1' ELSE wire_n1i0Ol_dataout; + wire_n10ill_dataout <= wire_n1l11O_dataout WHEN niOlO0O = '1' ELSE wire_n1i0OO_dataout; + wire_n10ilO_dataout <= wire_n1l10i_dataout WHEN niOlO0O = '1' ELSE wire_n1ii1i_dataout; + wire_n10iOi_dataout <= wire_n1l10l_dataout WHEN niOlO0O = '1' ELSE wire_n1ii1l_dataout; + wire_n10iOl_dataout <= wire_n1l10O_dataout WHEN niOlO0O = '1' ELSE wire_n1ii1O_dataout; + wire_n10iOO_dataout <= wire_n1l1ii_dataout WHEN niOlO0O = '1' ELSE wire_n1ii0i_dataout; + wire_n10l_dataout <= wire_nlO1lii_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(0); + wire_n10l0i_dataout <= wire_n1l1ll_dataout WHEN niOlO0O = '1' ELSE wire_n1iiil_dataout; + wire_n10l0l_dataout <= wire_n1l1lO_dataout WHEN niOlO0O = '1' ELSE wire_n1iiiO_dataout; + wire_n10l0O_dataout <= wire_n1l1Oi_dataout WHEN niOlO0O = '1' ELSE wire_n1iili_dataout; + wire_n10l1i_dataout <= wire_n1l1il_dataout WHEN niOlO0O = '1' ELSE wire_n1ii0l_dataout; + wire_n10l1l_dataout <= wire_n1l1iO_dataout WHEN niOlO0O = '1' ELSE wire_n1ii0O_dataout; + wire_n10l1O_dataout <= wire_n1l1li_dataout WHEN niOlO0O = '1' ELSE wire_n1iiii_dataout; + wire_n10lii_dataout <= wire_n1l1Ol_dataout WHEN niOlO0O = '1' ELSE wire_n1iill_dataout; + wire_n10lil_dataout <= wire_n1l1OO_dataout WHEN niOlO0O = '1' ELSE wire_n1iilO_dataout; + wire_n10liO_dataout <= wire_n1l01i_dataout WHEN niOlO0O = '1' ELSE wire_n1iiOi_dataout; + wire_n10lli_dataout <= wire_n1l01l_dataout WHEN niOlO0O = '1' ELSE wire_n1iiOl_dataout; + wire_n10lll_dataout <= wire_n1l01O_dataout WHEN niOlO0O = '1' ELSE wire_n1iiOO_dataout; + wire_n10llO_dataout <= wire_n1l00i_dataout WHEN niOlO0O = '1' ELSE wire_n1il1i_dataout; + wire_n10lOi_dataout <= wire_n1l00l_dataout WHEN niOlO0O = '1' ELSE wire_n1il1l_dataout; + wire_n10lOl_dataout <= wire_n1l00O_dataout WHEN niOlO0O = '1' ELSE wire_n1il1O_dataout; + wire_n10lOO_dataout <= wire_n1l0ii_dataout WHEN niOlO0O = '1' ELSE wire_n1il0i_dataout; + wire_n10O_dataout <= wire_nlO1lil_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(1); + wire_n10O0i_dataout <= wire_n1l0ll_dataout WHEN niOlO0O = '1' ELSE wire_n1ilil_dataout; + wire_n10O0l_dataout <= wire_n1l0lO_dataout WHEN niOlO0O = '1' ELSE wire_n1iliO_dataout; + wire_n10O0O_dataout <= wire_n1l0Oi_dataout WHEN niOlO0O = '1' ELSE wire_n1illi_dataout; + wire_n10O1i_dataout <= wire_n1l0il_dataout WHEN niOlO0O = '1' ELSE wire_n1il0l_dataout; + wire_n10O1l_dataout <= wire_n1l0iO_dataout WHEN niOlO0O = '1' ELSE wire_n1il0O_dataout; + wire_n10O1O_dataout <= wire_n1l0li_dataout WHEN niOlO0O = '1' ELSE wire_n1ilii_dataout; + wire_n10Oii_dataout <= wire_n1l0Ol_dataout WHEN niOlO0O = '1' ELSE wire_n1illl_dataout; + wire_n10Oil_dataout <= wire_n1l0OO_dataout WHEN niOlO0O = '1' ELSE wire_n1illO_dataout; + wire_n10OiO_dataout <= wire_n1li1i_dataout WHEN niOlO0O = '1' ELSE wire_n1ilOi_dataout; + wire_n10Ol_dataout <= wire_n1liO_dataout OR nliO0i; + wire_n10Oli_dataout <= wire_n1li1l_dataout WHEN niOlO0O = '1' ELSE wire_n1ilOl_dataout; + wire_n10Oll_dataout <= wire_n1li1O_dataout WHEN niOlO0O = '1' ELSE wire_n1ilOO_dataout; + wire_n10OlO_dataout <= wire_n1li0i_dataout WHEN niOlO0O = '1' ELSE wire_n1iO1i_dataout; + wire_n10OOi_dataout <= wire_n1li0l_dataout WHEN niOlO0O = '1' ELSE wire_n1iO1l_dataout; + wire_n10OOl_dataout <= wire_n1li0O_dataout WHEN niOlO0O = '1' ELSE wire_n1iO1O_dataout; + wire_n10OOO_dataout <= wire_n1liii_dataout WHEN niOlO0O = '1' ELSE wire_n1iO0i_dataout; + wire_n1100i_dataout <= wire_niOO1O_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl100l_dataout; + wire_n1100l_dataout <= wire_niOO0i_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl100O_dataout; + wire_n1100O_dataout <= wire_niOO0l_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10ii_dataout; + wire_n1101i_dataout <= wire_niOlOO_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl101l_dataout; + wire_n1101l_dataout <= wire_niOO1i_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl101O_dataout; + wire_n1101O_dataout <= wire_niOO1l_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl100i_dataout; + wire_n110i_dataout <= wire_n01Ol_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1ll; + wire_n110ii_dataout <= wire_niOO0O_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10il_dataout; + wire_n110il_dataout <= wire_niOOii_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10iO_dataout; + wire_n110iO_dataout <= wire_niOOil_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10li_dataout; + wire_n110l_dataout <= wire_n01lO_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1lO; + wire_n110li_dataout <= wire_niOOiO_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10ll_dataout; + wire_n110ll_dataout <= wire_niOOli_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10lO_dataout; + wire_n110lO_dataout <= wire_niOOll_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10Oi_dataout; + wire_n110O_dataout <= wire_n010i_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1Oi; + wire_n110Oi_dataout <= wire_niOOlO_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10Ol_dataout; + wire_n110Ol_dataout <= wire_niOOOi_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl10OO_dataout; + wire_n110OO_dataout <= wire_niOOOl_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1i1i_dataout; + wire_n1110i_dataout <= niO00O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl110l_dataout; + wire_n1110l_dataout <= niO0ii WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl110O_dataout; + wire_n1110O_dataout <= niO0il WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11ii_dataout; + wire_n1111i_dataout <= niO01O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl111l_dataout; + wire_n1111l_dataout <= niO00i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl111O_dataout; + wire_n1111O_dataout <= niO00l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl110i_dataout; + wire_n111i_dataout <= wire_n1OOO_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1il; + wire_n111ii_dataout <= niO0iO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11il_dataout; + wire_n111il_dataout <= niO0li WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11iO_dataout; + wire_n111iO_dataout <= niO0ll WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11li_dataout; + wire_n111l_dataout <= wire_n011i_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1iO; + wire_n111li_dataout <= niO0lO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11ll_dataout; + wire_n111ll_dataout <= niO0Oi WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11lO_dataout; + wire_n111lO_dataout <= niO0Ol WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11Oi_dataout; + wire_n111O_dataout <= wire_n011l_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1li; + wire_n111Oi_dataout <= niO0OO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11Ol_dataout; + wire_n111Ol_dataout <= niOi1i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl11OO_dataout; + wire_n111OO_dataout <= wire_niOlOl_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl101i_dataout; + wire_n11i_dataout <= wire_nlO1lOO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(8); + wire_n11i0i_dataout <= wire_nl111O_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1i0l_dataout; + wire_n11i0l_dataout <= wire_nl110i_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1i0O_dataout; + wire_n11i0O_dataout <= wire_nl110l_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1iii_dataout; + wire_n11i1i_dataout <= wire_niOOOO_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1i1l_dataout; + wire_n11i1l_dataout <= wire_nl111i_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1i1O_dataout; + wire_n11i1O_dataout <= wire_nl111l_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1i0i_dataout; + wire_n11ii_dataout <= wire_n01ii_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1Ol; + wire_n11iii_dataout <= wire_nl110O_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1iil_dataout; + wire_n11iil_dataout <= wire_nl11ii_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1iiO_dataout; + wire_n11iiO_dataout <= wire_nl11il_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1ili_dataout; + wire_n11il_dataout <= wire_n01il_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1OO; + wire_n11ili_dataout <= wire_nl11iO_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1ill_dataout; + wire_n11ill_dataout <= wire_nl11li_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1ilO_dataout; + wire_n11ilO_dataout <= wire_nl11ll_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1iOi_dataout; + wire_n11iO_dataout <= wire_n01li_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO01l; + wire_n11iOi_dataout <= wire_nl11lO_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1iOl_dataout; + wire_n11iOl_dataout <= wire_nl11Oi_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1iOO_dataout; + wire_n11iOO_dataout <= wire_nl11Ol_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1l1i_dataout; + wire_n11l_dataout <= wire_nlO011i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(24); + wire_n11l0i_dataout <= wire_nl111l_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11l0l_dataout <= wire_nl111O_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11l0O_dataout <= wire_nl110i_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11l1i_dataout <= wire_nl11OO_dataout WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl1l1l_dataout; + wire_n11l1l_dataout <= wire_niOOOO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11l1O_dataout <= wire_nl111i_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11lii_dataout <= wire_nl110l_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11lil_dataout <= wire_nl110O_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11liO_dataout <= wire_nl11ii_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11lli_dataout <= wire_nl11il_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11lll_dataout <= wire_nl11iO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11llO_dataout <= wire_nl11li_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11lOi_dataout <= wire_nl11ll_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11lOl_dataout <= wire_nl11lO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11lOO_dataout <= wire_nl11Oi_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11O_dataout <= wire_nlO001l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(40); + wire_n11O0i_dataout <= rbytordpadval(1) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl101l_dataout; + wire_n11O0l_dataout <= rbytordpadval(2) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl101O_dataout; + wire_n11O0O_dataout <= rbytordpadval(3) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl100i_dataout; + wire_n11O1i_dataout <= wire_nl11Ol_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11O1l_dataout <= wire_nl11OO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11O1O_dataout <= rbytordpadval(0) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl101i_dataout; + wire_n11Oii_dataout <= rbytordpadval(4) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl100l_dataout; + wire_n11Oil_dataout <= rbytordpadval(5) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl100O_dataout; + wire_n11OiO_dataout <= rbytordpadval(6) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl10ii_dataout; + wire_n11Oli_dataout <= rbytordpadval(7) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl10il_dataout; + wire_n11Oll_dataout <= rbytordpadval(8) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl10iO_dataout; + wire_n11OlO_dataout <= rbytordpadval(9) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl10li_dataout; + wire_n11OOi_dataout <= wire_niOOiO_dataout WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE wire_nl10ll_dataout; + wire_n11OOl_dataout <= wire_nl10lO_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n11OOO_dataout <= wire_nl10Oi_dataout AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_n1i_dataout <= wire_nlO0i1O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(56); + wire_n1i00i_dataout <= nil10l WHEN niOlOii = '1' ELSE nillil; + wire_n1i00l_dataout <= nil10O WHEN niOlOii = '1' ELSE nilliO; + wire_n1i00O_dataout <= nil1ii WHEN niOlOii = '1' ELSE nillli; + wire_n1i01i_dataout <= nil11l WHEN niOlOii = '1' ELSE nill0l; + wire_n1i01l_dataout <= nil11O WHEN niOlOii = '1' ELSE nill0O; + wire_n1i01O_dataout <= nil10i WHEN niOlOii = '1' ELSE nillii; + wire_n1i0ii_dataout <= nil1il WHEN niOlOii = '1' ELSE nillll; + wire_n1i0il_dataout <= nil1iO WHEN niOlOii = '1' ELSE nilllO; + wire_n1i0iO_dataout <= nil1li WHEN niOlOii = '1' ELSE nillOi; + wire_n1i0l_dataout <= gen2ngen1 WHEN rindv_rx = '1' ELSE gen2ngen1_bundle; + wire_n1i0li_dataout <= niliOi WHEN niOlOii = '1' ELSE nillOl; + wire_n1i0ll_dataout <= niliOl WHEN niOlOii = '1' ELSE nillOO; + wire_n1i0lO_dataout <= niliOO WHEN niOlOii = '1' ELSE nilO1i; + wire_n1i0Oi_dataout <= nill1i WHEN niOlOii = '1' ELSE nilO1l; + wire_n1i0Ol_dataout <= nill1l WHEN niOlOii = '1' ELSE nilO1O; + wire_n1i0OO_dataout <= nill1O WHEN niOlOii = '1' ELSE nilO0i; + wire_n1i10i_dataout <= wire_n1lill_dataout WHEN niOlO0O = '1' ELSE wire_n1iOil_dataout; + wire_n1i10l_dataout <= wire_n1lilO_dataout WHEN niOlO0O = '1' ELSE wire_n1iOiO_dataout; + wire_n1i10O_dataout <= wire_n1liOi_dataout WHEN niOlO0O = '1' ELSE wire_n1iOli_dataout; + wire_n1i11i_dataout <= wire_n1liil_dataout WHEN niOlO0O = '1' ELSE wire_n1iO0l_dataout; + wire_n1i11l_dataout <= wire_n1liiO_dataout WHEN niOlO0O = '1' ELSE wire_n1iO0O_dataout; + wire_n1i11O_dataout <= wire_n1lili_dataout WHEN niOlO0O = '1' ELSE wire_n1iOii_dataout; + wire_n1i1ii_dataout <= wire_n1liOl_dataout WHEN niOlO0O = '1' ELSE wire_n1iOll_dataout; + wire_n1i1il_dataout <= wire_n1liOO_dataout WHEN niOlO0O = '1' ELSE wire_n1iOlO_dataout; + wire_n1i1iO_dataout <= niiOli WHEN niOlOii = '1' ELSE niliOi; + wire_n1i1li_dataout <= niiOll WHEN niOlOii = '1' ELSE niliOl; + wire_n1i1ll_dataout <= niiOlO WHEN niOlOii = '1' ELSE niliOO; + wire_n1i1lO_dataout <= niiOOi WHEN niOlOii = '1' ELSE nill1i; + wire_n1i1Oi_dataout <= niiOOl WHEN niOlOii = '1' ELSE nill1l; + wire_n1i1Ol_dataout <= niiOOO WHEN niOlOii = '1' ELSE nill1O; + wire_n1i1OO_dataout <= nil11i WHEN niOlOii = '1' ELSE nill0i; + wire_n1ii_dataout <= wire_nlO1liO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(2); + wire_n1ii0i_dataout <= nillii WHEN niOlOii = '1' ELSE nilOil; + wire_n1ii0l_dataout <= nillil WHEN niOlOii = '1' ELSE nilOiO; + wire_n1ii0O_dataout <= nilliO WHEN niOlOii = '1' ELSE nilOli; + wire_n1ii1i_dataout <= nill0i WHEN niOlOii = '1' ELSE nilO0l; + wire_n1ii1l_dataout <= nill0l WHEN niOlOii = '1' ELSE nilO0O; + wire_n1ii1O_dataout <= nill0O WHEN niOlOii = '1' ELSE nilOii; + wire_n1iiii_dataout <= nillli WHEN niOlOii = '1' ELSE nilOll; + wire_n1iiil_dataout <= nillll WHEN niOlOii = '1' ELSE nilOlO; + wire_n1iiiO_dataout <= nilllO WHEN niOlOii = '1' ELSE nilOOi; + wire_n1iili_dataout <= nillOi WHEN niOlOii = '1' ELSE nilOOl; + wire_n1iill_dataout <= nilOOO AND NOT(niOlOii); + wire_n1iilO_dataout <= niO11i AND NOT(niOlOii); + wire_n1iiOi_dataout <= niO11l AND NOT(niOlOii); + wire_n1iiOl_dataout <= niO11O AND NOT(niOlOii); + wire_n1iiOO_dataout <= niO10i AND NOT(niOlOii); + wire_n1il_dataout <= wire_nlO1lli_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(3); + wire_n1il0i_dataout <= niO1il AND NOT(niOlOii); + wire_n1il0l_dataout <= niO1iO AND NOT(niOlOii); + wire_n1il0O_dataout <= niO1li AND NOT(niOlOii); + wire_n1il1i_dataout <= niO10l AND NOT(niOlOii); + wire_n1il1l_dataout <= niO10O AND NOT(niOlOii); + wire_n1il1O_dataout <= niO1ii AND NOT(niOlOii); + wire_n1ilii_dataout <= niO1ll AND NOT(niOlOii); + wire_n1ilil_dataout <= niO1lO AND NOT(niOlOii); + wire_n1iliO_dataout <= niO1Oi AND NOT(niOlOii); + wire_n1illi_dataout <= niO1Ol AND NOT(niOlOii); + wire_n1illl_dataout <= niO1OO AND NOT(niOlOii); + wire_n1illO_dataout <= niO01i AND NOT(niOlOii); + wire_n1ilOi_dataout <= niO01l AND NOT(niOlOii); + wire_n1ilOl_dataout <= niO01O AND NOT(niOlOii); + wire_n1ilOO_dataout <= niO00i AND NOT(niOlOii); + wire_n1iO_dataout <= wire_nlO1lll_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(4); + wire_n1iO0i_dataout <= niO0il AND NOT(niOlOii); + wire_n1iO0l_dataout <= niO0iO AND NOT(niOlOii); + wire_n1iO0O_dataout <= niO0li AND NOT(niOlOii); + wire_n1iO1i_dataout <= niO00l AND NOT(niOlOii); + wire_n1iO1l_dataout <= niO00O AND NOT(niOlOii); + wire_n1iO1O_dataout <= niO0ii AND NOT(niOlOii); + wire_n1iOi_dataout <= wire_n1l0O_dataout WHEN rbytordplden = '1' ELSE wire_n1iOO_dataout; + wire_n1iOii_dataout <= niO0ll AND NOT(niOlOii); + wire_n1iOil_dataout <= niO0lO AND NOT(niOlOii); + wire_n1iOiO_dataout <= niO0Oi AND NOT(niOlOii); + wire_n1iOl_dataout <= wire_n1lii_dataout WHEN rbytordplden = '1' ELSE wire_n1l1i_dataout; + wire_n1iOli_dataout <= niO0Ol AND NOT(niOlOii); + wire_n1iOll_dataout <= niO0OO AND NOT(niOlOii); + wire_n1iOlO_dataout <= niOi1i AND NOT(niOlOii); + wire_n1iOO_dataout <= n1i0i WHEN nl111iO = '1' ELSE wire_n1l1l_dataout; + wire_n1iOOi_dataout <= rbytordpadval(0) WHEN niOlOil = '1' ELSE nillOl; + wire_n1iOOl_dataout <= rbytordpadval(1) WHEN niOlOil = '1' ELSE nillOO; + wire_n1iOOO_dataout <= rbytordpadval(2) WHEN niOlOil = '1' ELSE nilO1i; + wire_n1l_dataout <= wire_nlO0i0i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(57); + wire_n1l00i_dataout <= niO10l AND NOT(niOlOil); + wire_n1l00l_dataout <= niO10O AND NOT(niOlOil); + wire_n1l00O_dataout <= niO1ii AND NOT(niOlOil); + wire_n1l01i_dataout <= niO11l AND NOT(niOlOil); + wire_n1l01l_dataout <= niO11O AND NOT(niOlOil); + wire_n1l01O_dataout <= niO10i AND NOT(niOlOil); + wire_n1l0ii_dataout <= niO1il AND NOT(niOlOil); + wire_n1l0il_dataout <= niO1iO AND NOT(niOlOil); + wire_n1l0iO_dataout <= niO1li AND NOT(niOlOil); + wire_n1l0li_dataout <= niO1ll AND NOT(niOlOil); + wire_n1l0ll_dataout <= niO1lO AND NOT(niOlOil); + wire_n1l0lO_dataout <= niO1Oi AND NOT(niOlOil); + wire_n1l0O_dataout <= n1i0i WHEN nl111li = '1' ELSE wire_n1l1l_dataout; + wire_n1l0Oi_dataout <= niO1Ol AND NOT(niOlOil); + wire_n1l0Ol_dataout <= niO1OO AND NOT(niOlOil); + wire_n1l0OO_dataout <= niO01i AND NOT(niOlOil); + wire_n1l10i_dataout <= rbytordpadval(6) WHEN niOlOil = '1' ELSE nilO0l; + wire_n1l10l_dataout <= rbytordpadval(7) WHEN niOlOil = '1' ELSE nilO0O; + wire_n1l10O_dataout <= rbytordpadval(8) WHEN niOlOil = '1' ELSE nilOii; + wire_n1l11i_dataout <= rbytordpadval(3) WHEN niOlOil = '1' ELSE nilO1l; + wire_n1l11l_dataout <= rbytordpadval(4) WHEN niOlOil = '1' ELSE nilO1O; + wire_n1l11O_dataout <= rbytordpadval(5) WHEN niOlOil = '1' ELSE nilO0i; + wire_n1l1i_dataout <= wire_n1l1O_dataout OR nl111iO; + wire_n1l1ii_dataout <= rbytordpadval(9) WHEN niOlOil = '1' ELSE nilOil; + wire_n1l1il_dataout <= nillil WHEN niOlOil = '1' ELSE nilOiO; + wire_n1l1iO_dataout <= nilOli AND NOT(niOlOil); + wire_n1l1l_dataout <= n1i0i OR nl111il; + wire_n1l1li_dataout <= nilOll AND NOT(niOlOil); + wire_n1l1ll_dataout <= nilOlO AND NOT(niOlOil); + wire_n1l1lO_dataout <= nilOOi AND NOT(niOlOil); + wire_n1l1O_dataout <= n1i0O AND NOT(nl111il); + wire_n1l1Oi_dataout <= nilOOl AND NOT(niOlOil); + wire_n1l1Ol_dataout <= nilOOO AND NOT(niOlOil); + wire_n1l1OO_dataout <= niO11i AND NOT(niOlOil); + wire_n1li_dataout <= wire_nlO1llO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(5); + wire_n1li0i_dataout <= niO00l AND NOT(niOlOil); + wire_n1li0l_dataout <= niO00O AND NOT(niOlOil); + wire_n1li0O_dataout <= niO0ii AND NOT(niOlOil); + wire_n1li1i_dataout <= niO01l AND NOT(niOlOil); + wire_n1li1l_dataout <= niO01O AND NOT(niOlOil); + wire_n1li1O_dataout <= niO00i AND NOT(niOlOil); + wire_n1lii_dataout <= wire_n1l1O_dataout OR nl111li; + wire_n1liii_dataout <= niO0il AND NOT(niOlOil); + wire_n1liil_dataout <= niO0iO AND NOT(niOlOil); + wire_n1liiO_dataout <= niO0li AND NOT(niOlOil); + wire_n1lili_dataout <= niO0ll AND NOT(niOlOil); + wire_n1lill_dataout <= niO0lO AND NOT(niOlOil); + wire_n1lilO_dataout <= niO0Oi AND NOT(niOlOil); + wire_n1liO_dataout <= (sync_resync_delay(0) OR sync_resync_delay(1)) WHEN rwa_6g_en = '1' ELSE wire_n1lli_dataout; + wire_n1liOi_dataout <= niO0Ol AND NOT(niOlOil); + wire_n1liOl_dataout <= niO0OO AND NOT(niOlOil); + wire_n1liOO_dataout <= niOi1i AND NOT(niOlOil); + wire_n1ll_dataout <= wire_nlO1lOi_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(6); + wire_n1ll0i_dataout <= wire_niOO1l_dataout WHEN niOlO0O = '1' ELSE wire_n1Oiil_dataout; + wire_n1ll0l_dataout <= wire_niOO1O_dataout WHEN niOlO0O = '1' ELSE wire_n1OiiO_dataout; + wire_n1ll0O_dataout <= wire_niOO0i_dataout WHEN niOlO0O = '1' ELSE wire_n1Oili_dataout; + wire_n1ll1i_dataout <= wire_niOlOl_dataout WHEN niOlO0O = '1' ELSE wire_n1Oi0l_dataout; + wire_n1ll1l_dataout <= wire_niOlOO_dataout WHEN niOlO0O = '1' ELSE wire_n1Oi0O_dataout; + wire_n1ll1O_dataout <= wire_niOO1i_dataout WHEN niOlO0O = '1' ELSE wire_n1Oiii_dataout; + wire_n1lli_dataout <= wire_n1lll_dataout WHEN rsync_sm_dis = '1' ELSE dec_data_valid_pre(0); + wire_n1llii_dataout <= wire_niOO0l_dataout WHEN niOlO0O = '1' ELSE wire_n1Oill_dataout; + wire_n1llil_dataout <= wire_niOO0O_dataout WHEN niOlO0O = '1' ELSE wire_n1OilO_dataout; + wire_n1lliO_dataout <= wire_niOOii_dataout WHEN niOlO0O = '1' ELSE wire_n1OiOi_dataout; + wire_n1lll_dataout <= sync_resync_delay(0) WHEN rpmadatawidth = '1' ELSE sync_resync_pre(0); + wire_n1llli_dataout <= wire_niOOil_dataout WHEN niOlO0O = '1' ELSE wire_n1OiOl_dataout; + wire_n1llll_dataout <= wire_niOOiO_dataout WHEN niOlO0O = '1' ELSE wire_n1OiOO_dataout; + wire_n1lllO_dataout <= wire_niOOli_dataout WHEN niOlO0O = '1' ELSE wire_n1Ol1i_dataout; + wire_n1llOi_dataout <= wire_niOOll_dataout WHEN niOlO0O = '1' ELSE wire_n1Ol1l_dataout; + wire_n1llOl_dataout <= wire_niOOlO_dataout WHEN niOlO0O = '1' ELSE wire_n1Ol1O_dataout; + wire_n1llOO_dataout <= wire_niOOOi_dataout WHEN niOlO0O = '1' ELSE wire_n1Ol0i_dataout; + wire_n1lO_dataout <= wire_nlO1lOl_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(7); + wire_n1lO0i_dataout <= wire_n010ll_dataout WHEN niOlO0O = '1' ELSE wire_n1Olil_dataout; + wire_n1lO0l_dataout <= wire_n010lO_dataout WHEN niOlO0O = '1' ELSE wire_n1OliO_dataout; + wire_n1lO0O_dataout <= wire_n010Oi_dataout WHEN niOlO0O = '1' ELSE wire_n1Olli_dataout; + wire_n1lO1i_dataout <= wire_niOOOl_dataout WHEN niOlO0O = '1' ELSE wire_n1Ol0l_dataout; + wire_n1lO1l_dataout <= wire_n010iO_dataout WHEN niOlO0O = '1' ELSE wire_n1Ol0O_dataout; + wire_n1lO1O_dataout <= wire_n010li_dataout WHEN niOlO0O = '1' ELSE wire_n1Olii_dataout; + wire_n1lOi_dataout <= wire_n000O_dataout WHEN endec_rx = '1' ELSE tenb_data(0); + wire_n1lOii_dataout <= wire_n010Ol_dataout WHEN niOlO0O = '1' ELSE wire_n1Olll_dataout; + wire_n1lOil_dataout <= wire_n010OO_dataout WHEN niOlO0O = '1' ELSE wire_n1OllO_dataout; + wire_n1lOiO_dataout <= wire_n01i1i_dataout WHEN niOlO0O = '1' ELSE wire_n1OlOi_dataout; + wire_n1lOl_dataout <= wire_n00ii_dataout WHEN endec_rx = '1' ELSE tenb_data(1); + wire_n1lOli_dataout <= wire_n01i1l_dataout WHEN niOlO0O = '1' ELSE wire_n1OlOl_dataout; + wire_n1lOll_dataout <= wire_n01i1O_dataout WHEN niOlO0O = '1' ELSE wire_n1OlOO_dataout; + wire_n1lOlO_dataout <= wire_n01i0i_dataout WHEN niOlO0O = '1' ELSE wire_n1OO1i_dataout; + wire_n1lOO_dataout <= wire_n00il_dataout WHEN endec_rx = '1' ELSE tenb_data(2); + wire_n1lOOi_dataout <= wire_n01i0l_dataout WHEN niOlO0O = '1' ELSE wire_n1OO1l_dataout; + wire_n1lOOl_dataout <= wire_n01i0O_dataout WHEN niOlO0O = '1' ELSE wire_n1OO1O_dataout; + wire_n1lOOO_dataout <= wire_n01iii_dataout WHEN niOlO0O = '1' ELSE wire_n1OO0i_dataout; + wire_n1O_dataout <= wire_nlO0i0l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(58); + wire_n1O00i_dataout <= wire_n01lll_dataout WHEN niOlO0O = '1' ELSE wire_n011il_dataout; + wire_n1O00l_dataout <= wire_n01llO_dataout WHEN niOlO0O = '1' ELSE wire_n011iO_dataout; + wire_n1O00O_dataout <= wire_n01lOi_dataout WHEN niOlO0O = '1' ELSE wire_n011li_dataout; + wire_n1O01i_dataout <= wire_n01lil_dataout WHEN niOlO0O = '1' ELSE wire_n0110l_dataout; + wire_n1O01l_dataout <= wire_n01liO_dataout WHEN niOlO0O = '1' ELSE wire_n0110O_dataout; + wire_n1O01O_dataout <= wire_n01lli_dataout WHEN niOlO0O = '1' ELSE wire_n011ii_dataout; + wire_n1O0i_dataout <= wire_n00lO_dataout WHEN endec_rx = '1' ELSE tenb_data(6); + wire_n1O0ii_dataout <= wire_n01lOl_dataout WHEN niOlO0O = '1' ELSE wire_n011ll_dataout; + wire_n1O0il_dataout <= wire_n01lOO_dataout WHEN niOlO0O = '1' ELSE wire_n011lO_dataout; + wire_n1O0iO_dataout <= wire_n01O1i_dataout WHEN niOlO0O = '1' ELSE wire_n011Oi_dataout; + wire_n1O0l_dataout <= wire_n00Oi_dataout WHEN endec_rx = '1' ELSE tenb_data(7); + wire_n1O0li_dataout <= wire_n01O1l_dataout WHEN niOlO0O = '1' ELSE wire_n011Ol_dataout; + wire_n1O0ll_dataout <= wire_n01O1O_dataout WHEN niOlO0O = '1' ELSE wire_n011OO_dataout; + wire_n1O0lO_dataout <= wire_n01O0i_dataout WHEN niOlO0O = '1' ELSE wire_n0101i_dataout; + wire_n1O0O_dataout <= wire_n00Ol_dataout WHEN endec_rx = '1' ELSE tenb_data(8); + wire_n1O0Oi_dataout <= wire_n01O0l_dataout WHEN niOlO0O = '1' ELSE wire_n0101l_dataout; + wire_n1O0Ol_dataout <= wire_n01O0O_dataout WHEN niOlO0O = '1' ELSE wire_n0101O_dataout; + wire_n1O0OO_dataout <= wire_n01Oii_dataout WHEN niOlO0O = '1' ELSE wire_n0100i_dataout; + wire_n1O10i_dataout <= wire_n01ill_dataout WHEN niOlO0O = '1' ELSE wire_n1OOil_dataout; + wire_n1O10l_dataout <= wire_n01ilO_dataout WHEN niOlO0O = '1' ELSE wire_n1OOiO_dataout; + wire_n1O10O_dataout <= wire_n01iOi_dataout WHEN niOlO0O = '1' ELSE wire_n1OOli_dataout; + wire_n1O11i_dataout <= wire_n01iil_dataout WHEN niOlO0O = '1' ELSE wire_n1OO0l_dataout; + wire_n1O11l_dataout <= wire_n01iiO_dataout WHEN niOlO0O = '1' ELSE wire_n1OO0O_dataout; + wire_n1O11O_dataout <= wire_n01ili_dataout WHEN niOlO0O = '1' ELSE wire_n1OOii_dataout; + wire_n1O1i_dataout <= wire_n00iO_dataout WHEN endec_rx = '1' ELSE tenb_data(3); + wire_n1O1ii_dataout <= wire_n01iOl_dataout WHEN niOlO0O = '1' ELSE wire_n1OOll_dataout; + wire_n1O1il_dataout <= wire_n01iOO_dataout WHEN niOlO0O = '1' ELSE wire_n1OOlO_dataout; + wire_n1O1iO_dataout <= wire_n01l1i_dataout WHEN niOlO0O = '1' ELSE wire_n1OOOi_dataout; + wire_n1O1l_dataout <= wire_n00li_dataout WHEN endec_rx = '1' ELSE tenb_data(4); + wire_n1O1li_dataout <= wire_n01l1l_dataout WHEN niOlO0O = '1' ELSE wire_n1OOOl_dataout; + wire_n1O1ll_dataout <= wire_n01l1O_dataout WHEN niOlO0O = '1' ELSE wire_n1OOOO_dataout; + wire_n1O1lO_dataout <= wire_n01l0i_dataout WHEN niOlO0O = '1' ELSE wire_n0111i_dataout; + wire_n1O1O_dataout <= wire_n00ll_dataout WHEN endec_rx = '1' ELSE tenb_data(5); + wire_n1O1Oi_dataout <= wire_n01l0l_dataout WHEN niOlO0O = '1' ELSE wire_n0111l_dataout; + wire_n1O1Ol_dataout <= wire_n01l0O_dataout WHEN niOlO0O = '1' ELSE wire_n0111O_dataout; + wire_n1O1OO_dataout <= wire_n01lii_dataout WHEN niOlO0O = '1' ELSE wire_n0110i_dataout; + wire_n1Oi_dataout <= wire_nlO1lOO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(8); + wire_n1Oi0i_dataout <= wire_n01Oll_dataout WHEN niOlO0O = '1' ELSE wire_n010il_dataout; + wire_n1Oi0l_dataout <= nillOl WHEN niOlOii = '1' ELSE wire_niOlOl_dataout; + wire_n1Oi0O_dataout <= nillOO WHEN niOlOii = '1' ELSE wire_niOlOO_dataout; + wire_n1Oi1i_dataout <= wire_n01Oil_dataout WHEN niOlO0O = '1' ELSE wire_n0100l_dataout; + wire_n1Oi1l_dataout <= wire_n01OiO_dataout WHEN niOlO0O = '1' ELSE wire_n0100O_dataout; + wire_n1Oi1O_dataout <= wire_n01Oli_dataout WHEN niOlO0O = '1' ELSE wire_n010ii_dataout; + wire_n1Oii_dataout <= wire_n00OO_dataout WHEN endec_rx = '1' ELSE tenb_data(9); + wire_n1Oiii_dataout <= nilO1i WHEN niOlOii = '1' ELSE wire_niOO1i_dataout; + wire_n1Oiil_dataout <= nilO1l WHEN niOlOii = '1' ELSE wire_niOO1l_dataout; + wire_n1OiiO_dataout <= nilO1O WHEN niOlOii = '1' ELSE wire_niOO1O_dataout; + wire_n1Oil_dataout <= wire_n0i1i_dataout WHEN endec_rx = '1' ELSE tenb_data(10); + wire_n1Oili_dataout <= nilO0i WHEN niOlOii = '1' ELSE wire_niOO0i_dataout; + wire_n1Oill_dataout <= nilO0l WHEN niOlOii = '1' ELSE wire_niOO0l_dataout; + wire_n1OilO_dataout <= nilO0O WHEN niOlOii = '1' ELSE wire_niOO0O_dataout; + wire_n1OiO_dataout <= wire_n0i1l_dataout WHEN endec_rx = '1' ELSE tenb_data(11); + wire_n1OiOi_dataout <= nilOii WHEN niOlOii = '1' ELSE wire_niOOii_dataout; + wire_n1OiOl_dataout <= nilOil WHEN niOlOii = '1' ELSE wire_niOOil_dataout; + wire_n1OiOO_dataout <= nilOiO WHEN niOlOii = '1' ELSE wire_niOOiO_dataout; + wire_n1Ol_dataout <= wire_nlO1O1i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(9); + wire_n1Ol0i_dataout <= nilOOi WHEN niOlOii = '1' ELSE wire_niOOOi_dataout; + wire_n1Ol0l_dataout <= nilOOl WHEN niOlOii = '1' ELSE wire_niOOOl_dataout; + wire_n1Ol0O_dataout <= wire_niOlOl_dataout WHEN niOlOii = '1' ELSE wire_niOOOO_dataout; + wire_n1Ol1i_dataout <= nilOli WHEN niOlOii = '1' ELSE wire_niOOli_dataout; + wire_n1Ol1l_dataout <= nilOll WHEN niOlOii = '1' ELSE wire_niOOll_dataout; + wire_n1Ol1O_dataout <= nilOlO WHEN niOlOii = '1' ELSE wire_niOOlO_dataout; + wire_n1Oli_dataout <= wire_n0i1O_dataout WHEN endec_rx = '1' ELSE tenb_data(12); + wire_n1Olii_dataout <= wire_niOlOO_dataout WHEN niOlOii = '1' ELSE wire_nl111i_dataout; + wire_n1Olil_dataout <= wire_niOO1i_dataout WHEN niOlOii = '1' ELSE wire_nl111l_dataout; + wire_n1OliO_dataout <= wire_niOO1l_dataout WHEN niOlOii = '1' ELSE wire_nl111O_dataout; + wire_n1Oll_dataout <= wire_n0i0i_dataout WHEN endec_rx = '1' ELSE tenb_data(13); + wire_n1Olli_dataout <= wire_niOO1O_dataout WHEN niOlOii = '1' ELSE wire_nl110i_dataout; + wire_n1Olll_dataout <= wire_niOO0i_dataout WHEN niOlOii = '1' ELSE wire_nl110l_dataout; + wire_n1OllO_dataout <= wire_niOO0l_dataout WHEN niOlOii = '1' ELSE wire_nl110O_dataout; + wire_n1OlO_dataout <= wire_n0i0l_dataout WHEN endec_rx = '1' ELSE tenb_data(14); + wire_n1OlOi_dataout <= wire_niOO0O_dataout WHEN niOlOii = '1' ELSE wire_nl11ii_dataout; + wire_n1OlOl_dataout <= wire_niOOii_dataout WHEN niOlOii = '1' ELSE wire_nl11il_dataout; + wire_n1OlOO_dataout <= wire_niOOil_dataout WHEN niOlOii = '1' ELSE wire_nl11iO_dataout; + wire_n1OO_dataout <= wire_nlO1O1l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(10); + wire_n1OO0i_dataout <= wire_niOOlO_dataout WHEN niOlOii = '1' ELSE wire_nl11Oi_dataout; + wire_n1OO0l_dataout <= wire_niOOOi_dataout WHEN niOlOii = '1' ELSE wire_nl11Ol_dataout; + wire_n1OO0O_dataout <= wire_niOOOl_dataout WHEN niOlOii = '1' ELSE wire_nl11OO_dataout; + wire_n1OO1i_dataout <= wire_niOOiO_dataout WHEN niOlOii = '1' ELSE wire_nl11li_dataout; + wire_n1OO1l_dataout <= wire_niOOli_dataout WHEN niOlOii = '1' ELSE wire_nl11ll_dataout; + wire_n1OO1O_dataout <= wire_niOOll_dataout WHEN niOlOii = '1' ELSE wire_nl11lO_dataout; + wire_n1OOi_dataout <= wire_n0i0O_dataout WHEN endec_rx = '1' ELSE tenb_data(15); + wire_n1OOii_dataout <= wire_nl101i_dataout AND NOT(niOlOii); + wire_n1OOil_dataout <= wire_nl101l_dataout AND NOT(niOlOii); + wire_n1OOiO_dataout <= wire_nl101O_dataout AND NOT(niOlOii); + wire_n1OOl_dataout <= wire_n0iii_dataout WHEN endec_rx = '1' ELSE tenb_data(16); + wire_n1OOli_dataout <= wire_nl100i_dataout AND NOT(niOlOii); + wire_n1OOll_dataout <= wire_nl100l_dataout AND NOT(niOlOii); + wire_n1OOlO_dataout <= wire_nl100O_dataout AND NOT(niOlOii); + wire_n1OOO_dataout <= wire_n0iil_dataout WHEN endec_rx = '1' ELSE tenb_data(17); + wire_n1OOOi_dataout <= wire_nl10ii_dataout AND NOT(niOlOii); + wire_n1OOOl_dataout <= wire_nl10il_dataout AND NOT(niOlOii); + wire_n1OOOO_dataout <= wire_nl10iO_dataout AND NOT(niOlOii); + wire_ni000l_dataout <= (niOO1Oi AND wire_ni00iO_dataout) WHEN rwa_6g_en = '1' ELSE (niOi1l AND (niOO01i AND niOO1Oi)); + wire_ni001l_dataout <= niOO1li OR rbytord_6g_mask_en; + wire_ni00i_dataout <= wire_niiOi_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_ni0OO_dataout; + wire_ni00iO_dataout <= niOO1Ol OR rbytord_6g_mask_en; + wire_ni00l_dataout <= wire_niiOl_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_nii1i_dataout; + wire_ni00li_dataout <= wire_ni00ll_dataout AND rwa_6g_en; + wire_ni00ll_dataout <= (niOO1OO AND wire_ni00Ol_dataout) WHEN rdwidth = '1' ELSE (wire_ni0iiO_dataout AND niOO1OO); + wire_ni00O_dataout <= wire_niiOO_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_nii1l_dataout; + wire_ni00Ol_dataout <= niOO01i OR rbytord_6g_mask_en; + wire_ni00OO_dataout <= wire_ni0i1O_dataout WHEN rwa_6g_en = '1' ELSE (niOi1O AND (niOO01O AND niOOill)); + wire_ni010i_dataout <= wire_ni01il_dataout WHEN rwa_6g_en = '1' ELSE (niOi1O AND (niOO1li AND niOO1ii)); + wire_ni011l_dataout <= niOO10i OR rbytord_6g_mask_en; + wire_ni01i_dataout <= wire_niili_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_ni0lO_dataout; + wire_ni01il_dataout <= (wire_nl1l0i_dataout AND (niOO1ii AND wire_ni01ll_dataout)) AND rdwidth; + wire_ni01l_dataout <= wire_niill_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_ni0Oi_dataout; + wire_ni01ll_dataout <= (niOO1iO OR niOO1il) OR rbytord_6g_mask_en; + wire_ni01O_dataout <= wire_niilO_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_ni0Ol_dataout; + wire_ni01Oi_dataout <= wire_ni01Ol_dataout AND rwa_6g_en; + wire_ni01Ol_dataout <= (wire_nl1l0i_dataout AND (wire_ni001l_dataout AND (niOO0ll OR niOO0li))) AND rdwidth; + wire_ni0i_dataout <= wire_nlO010O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(29); + wire_ni0i0l_dataout <= niOO01l OR rbytord_6g_mask_en; + wire_ni0i0O_dataout <= wire_ni0iii_dataout AND rwa_6g_en; + wire_ni0i1O_dataout <= (niOOill AND wire_ni0i0l_dataout) AND rdwidth; + wire_ni0ii_dataout <= wire_nil1i_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_nii1O_dataout; + wire_ni0iii_dataout <= (wire_ni0iiO_dataout AND niOOili) AND rdwidth; + wire_ni0iiO_dataout <= niOO01O OR rbytord_6g_mask_en; + wire_ni0il_dataout <= wire_nil1l_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_nii0i_dataout; + wire_ni0ili_dataout <= (niOO00i AND wire_ni0iOl_dataout) WHEN rwa_6g_en = '1' ELSE (niOi1O AND (niOO0ii AND niOO00i)); + wire_ni0iO_dataout <= wire_nil1O_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_nii0l_dataout; + wire_ni0iOl_dataout <= niOO00l OR rbytord_6g_mask_en; + wire_ni0iOO_dataout <= wire_ni0l1i_dataout AND rwa_6g_en; + wire_ni0l_dataout <= wire_nlO01ii_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(30); + wire_ni0l0i_dataout <= niOO0ii OR rbytord_6g_mask_en; + wire_ni0l0l_dataout <= wire_ni0lil_dataout WHEN rwa_6g_en = '1' ELSE (wire_nl1l1O_dataout AND (niOO0iO AND niOOl1O)); + wire_ni0l1i_dataout <= (niOO00O AND wire_ni0l0i_dataout) WHEN rdwidth = '1' ELSE (wire_ni0lOl_dataout AND niOO00O); + wire_ni0li_dataout <= wire_nil0i_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_niO_dataout; + wire_ni0lil_dataout <= (niOOl1O AND wire_ni0lli_dataout) AND rdwidth; + wire_ni0ll_dataout <= wire_nil0l_dataout WHEN wire_nlilOi_w_lg_dataout523w(0) = '1' ELSE wire_nli1l_o; + wire_ni0lli_dataout <= niOO0il OR rbytord_6g_mask_en; + wire_ni0lll_dataout <= wire_ni0llO_dataout AND rwa_6g_en; + wire_ni0llO_dataout <= (wire_ni0lOl_dataout AND niOOl1l) AND rdwidth; + wire_ni0lO_dataout <= rclkcmpinsertpad WHEN nl111Oi = '1' ELSE rx_data_dt(0); + wire_ni0lOl_dataout <= niOO0iO OR rbytord_6g_mask_en; + wire_ni0lOO_dataout <= (wire_nl1l1O_dataout AND (niOO0Ol AND (wire_w_lg_rbytordplden683w(0) OR (wire_w_lg_niOO0ll758w(0) AND wire_w_lg_niOO0li759w(0))))) WHEN rwa_6g_en = '1' ELSE (wire_nl1l1O_dataout AND ((wire_w_lg_rbytordplden683w(0) OR (wire_w_lg_niOO0Oi752w(0) AND wire_w_lg_niOO0lO753w(0))) AND niOO0Ol)); + wire_ni0O_dataout <= wire_nlO01il_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(31); + wire_ni0Oi_dataout <= rx_data_dt(1) OR nl111Oi; + wire_ni0Ol_dataout <= rx_data_dt(2) OR nl111Oi; + wire_ni0Oli_dataout <= (wire_nl1l1O_dataout AND (niOO0OO AND (niOOi0i OR niOOi1O))) AND rwa_6g_en; + wire_ni0OO_dataout <= wire_w_lg_rclkcmpinsertpad522w(0) WHEN nl111Oi = '1' ELSE rx_data_dt(3); + wire_ni0OOl_dataout <= wire_nii10l_dataout WHEN rwa_6g_en = '1' ELSE (wire_nl1l0i_dataout AND (niOO0OO AND niOOi0l)); + wire_ni100i_dataout <= wire_nl11Oi_dataout AND NOT(wire_n0iO0O_o(2)); + wire_ni100l_dataout <= wire_nl11Ol_dataout AND NOT(wire_n0iO0O_o(2)); + wire_ni100O_dataout <= wire_nl11OO_dataout AND NOT(wire_n0iO0O_o(2)); + wire_ni101i_dataout <= wire_niOOiO_dataout WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl11li_dataout; + wire_ni101l_dataout <= wire_nl11ll_dataout AND NOT(wire_n0iO0O_o(2)); + wire_ni101O_dataout <= wire_nl11lO_dataout AND NOT(wire_n0iO0O_o(2)); + wire_ni10i_dataout <= rx_data_dt(8) AND NOT(nl111Ol); + wire_ni10ii_dataout <= rbytordpadval(0) WHEN niOlOiO = '1' ELSE wire_nl101i_dataout; + wire_ni10il_dataout <= rbytordpadval(1) WHEN niOlOiO = '1' ELSE wire_nl101l_dataout; + wire_ni10iO_dataout <= rbytordpadval(2) WHEN niOlOiO = '1' ELSE wire_nl101O_dataout; + wire_ni10l_dataout <= rrx_pipe_enable WHEN nl111Ol = '1' ELSE rx_data_dt(9); + wire_ni10li_dataout <= rbytordpadval(3) WHEN niOlOiO = '1' ELSE wire_nl100i_dataout; + wire_ni10ll_dataout <= rbytordpadval(4) WHEN niOlOiO = '1' ELSE wire_nl100l_dataout; + wire_ni10lO_dataout <= rbytordpadval(5) WHEN niOlOiO = '1' ELSE wire_nl100O_dataout; + wire_ni10O_dataout <= rx_data_dt(10) OR nl111Ol; + wire_ni10Oi_dataout <= rbytordpadval(6) WHEN niOlOiO = '1' ELSE wire_nl10ii_dataout; + wire_ni10Ol_dataout <= rbytordpadval(7) WHEN niOlOiO = '1' ELSE wire_nl10il_dataout; + wire_ni10OO_dataout <= rbytordpadval(8) WHEN niOlOiO = '1' ELSE wire_nl10iO_dataout; + wire_ni110O_dataout <= rbytordpadval(0) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_niOOOO_dataout; + wire_ni11ii_dataout <= rbytordpadval(1) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl111i_dataout; + wire_ni11il_dataout <= rbytordpadval(2) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl111l_dataout; + wire_ni11iO_dataout <= rbytordpadval(3) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl111O_dataout; + wire_ni11li_dataout <= rbytordpadval(4) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl110i_dataout; + wire_ni11ll_dataout <= rbytordpadval(5) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl110l_dataout; + wire_ni11lO_dataout <= rbytordpadval(6) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl110O_dataout; + wire_ni11Oi_dataout <= rbytordpadval(7) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl11ii_dataout; + wire_ni11Ol_dataout <= rbytordpadval(8) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl11il_dataout; + wire_ni11OO_dataout <= rbytordpadval(9) WHEN wire_n0iO0O_o(2) = '1' ELSE wire_nl11iO_dataout; + wire_ni1i_dataout <= wire_nlO011O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(26); + wire_ni1i0i_dataout <= wire_nl10Oi_dataout AND NOT(niOlOiO); + wire_ni1i0l_dataout <= wire_nl10Ol_dataout AND NOT(niOlOiO); + wire_ni1i0O_dataout <= wire_nl10OO_dataout AND NOT(niOlOiO); + wire_ni1i1i_dataout <= rbytordpadval(9) WHEN niOlOiO = '1' ELSE wire_nl10li_dataout; + wire_ni1i1O_dataout <= wire_nl10lO_dataout AND NOT(niOlOiO); + wire_ni1ii_dataout <= rx_data_dt(11) OR nl111Ol; + wire_ni1iii_dataout <= wire_nl1i1i_dataout AND NOT(niOlOiO); + wire_ni1iil_dataout <= rbytordpadval(0) WHEN niOlOli = '1' ELSE wire_nl1i1l_dataout; + wire_ni1iiO_dataout <= rbytordpadval(1) WHEN niOlOli = '1' ELSE wire_nl1i1O_dataout; + wire_ni1il_dataout <= rx_data_dt(12) OR nl111Ol; + wire_ni1ili_dataout <= rbytordpadval(2) WHEN niOlOli = '1' ELSE wire_nl1i0i_dataout; + wire_ni1ill_dataout <= rbytordpadval(3) WHEN niOlOli = '1' ELSE wire_nl1i0l_dataout; + wire_ni1ilO_dataout <= rbytordpadval(4) WHEN niOlOli = '1' ELSE wire_nl1i0O_dataout; + wire_ni1iO_dataout <= rrx_pipe_enable WHEN nl111Ol = '1' ELSE rx_data_dt(13); + wire_ni1iOi_dataout <= rbytordpadval(5) WHEN niOlOli = '1' ELSE wire_nl1iii_dataout; + wire_ni1iOl_dataout <= rbytordpadval(6) WHEN niOlOli = '1' ELSE wire_nl1iil_dataout; + wire_ni1iOO_dataout <= rbytordpadval(7) WHEN niOlOli = '1' ELSE wire_nl1iiO_dataout; + wire_ni1l_dataout <= wire_nlO010i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(27); + wire_ni1l0i_dataout <= wire_nl1iOi_dataout AND NOT(niOlOli); + wire_ni1l0l_dataout <= wire_nl1iOl_dataout AND NOT(niOlOli); + wire_ni1l0O_dataout <= wire_nl1iOO_dataout AND NOT(niOlOli); + wire_ni1l1i_dataout <= rbytordpadval(8) WHEN niOlOli = '1' ELSE wire_nl1ili_dataout; + wire_ni1l1l_dataout <= rbytordpadval(9) WHEN niOlOli = '1' ELSE wire_nl1ill_dataout; + wire_ni1li_dataout <= rrx_pipe_enable WHEN nl111Ol = '1' ELSE rx_data_dt(14); + wire_ni1lii_dataout <= wire_nl1l1i_dataout AND NOT(niOlOli); + wire_ni1lil_dataout <= wire_nl1l1l_dataout AND NOT(niOlOli); + wire_ni1liO_dataout <= wire_ni1lOi_o AND NOT(niOOlli); + wire_ni1liO_w_lg_dataout678w(0) <= NOT wire_ni1liO_dataout; + wire_ni1ll_dataout <= rx_data_dt(15) OR nl111Ol; + wire_ni1lli_dataout <= wire_ni1lOl_o AND NOT(niOOlli); + wire_ni1lli_w_lg_w_lg_w_lg_dataout679w680w681w(0) <= wire_ni1lli_w_lg_w_lg_dataout679w680w(0) OR wire_ni1llO_dataout; + wire_ni1lli_w_lg_w_lg_dataout679w680w(0) <= wire_ni1lli_w_lg_dataout679w(0) OR wire_ni1lll_dataout; + wire_ni1lli_w_lg_dataout679w(0) <= wire_ni1lli_dataout OR wire_ni1liO_dataout; + wire_ni1lll_dataout <= wire_ni1lOO_o AND NOT(niOOlli); + wire_ni1lll_w_lg_dataout3799w(0) <= NOT wire_ni1lll_dataout; + wire_ni1llO_dataout <= wire_ni1O1i_o AND NOT(niOOlli); + wire_ni1lO_dataout <= rx_control_dt(1) OR nl111Ol; + wire_ni1O_dataout <= wire_nlO010l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(28); + wire_ni1O1l_dataout <= (wire_nl1l1O_dataout AND (niOlOll AND wire_ni1Oil_dataout)) WHEN rwa_6g_en = '1' ELSE (niOi1l AND (niOO10i AND niOlOll)); + wire_ni1Oi_dataout <= wire_ni1OO_dataout WHEN nl111Ol = '1' ELSE wire_nli_dataout; + wire_ni1Oil_dataout <= (niOlOOO OR niOlOOl) OR rbytord_6g_mask_en; + wire_ni1Ol_dataout <= wire_niO1l_o AND NOT(nl111Ol); + wire_ni1Oli_dataout <= wire_ni1Oll_dataout AND rwa_6g_en; + wire_ni1Oll_dataout <= (wire_nl1l1O_dataout AND (niOO11i AND wire_ni011l_dataout)) WHEN rdwidth = '1' ELSE (wire_nl1l1O_dataout AND (wire_ni001l_dataout AND niOO11i)); + wire_ni1OO_dataout <= wire_nli_dataout OR rrx_pipe_enable; + wire_nii_dataout <= wire_nlO0iiO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(62); + wire_nii01l_dataout <= (wire_nl1l1O_dataout AND (niOOiOi AND (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOili724w(0)))) WHEN rwa_6g_en = '1' ELSE (wire_nl1l1O_dataout AND (niOOiOi AND (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOill720w(0)))); + wire_nii0i_dataout <= rx_data_dt(7) OR nl111Oi; + wire_nii0iO_dataout <= (wire_nl1l1O_dataout AND (niOOilO AND niOOiOl)) AND rwa_6g_en; + wire_nii0l_dataout <= rx_control_dt(0) OR nl111Oi; + wire_nii0lO_dataout <= wire_niii1i_dataout WHEN rwa_6g_en = '1' ELSE (wire_nl1l0i_dataout AND (niOOilO AND niOOl1i)); + wire_nii10l_dataout <= (wire_nl1l0i_dataout AND (niOOi0l AND (wire_w_lg_rbytordplden683w(0) OR (wire_w_lg_niOOi0i735w(0) AND wire_w_lg_niOOi1O736w(0))))) AND rdwidth; + wire_nii1i_dataout <= rx_data_dt(4) OR nl111Oi; + wire_nii1l_dataout <= rx_data_dt(5) OR nl111Oi; + wire_nii1li_dataout <= wire_nii1ll_dataout AND rwa_6g_en; + wire_nii1ll_dataout <= (wire_nl1l0i_dataout AND ((wire_w_lg_rbytordplden683w(0) OR (wire_w_lg_niOOiiO728w(0) AND wire_w_lg_niOOiil729w(0))) AND (niOOiii OR niOOi0O))) AND rdwidth; + wire_nii1O_dataout <= rx_data_dt(6) OR nl111Oi; + wire_niii_dataout <= wire_nlO01iO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(32); + wire_niii0l_dataout <= wire_niii0O_dataout AND rwa_6g_en; + wire_niii0O_dataout <= (wire_nl1l0i_dataout AND ((wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOl1i706w(0)) AND niOOiOO)) AND rdwidth; + wire_niii1i_dataout <= (wire_nl1l0i_dataout AND (niOOl1i AND (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOiOl710w(0)))) AND rdwidth; + wire_niiili_dataout <= (wire_nl1l1O_dataout AND (niOOl0l AND (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOl1l702w(0)))) WHEN rwa_6g_en = '1' ELSE (wire_nl1l1O_dataout AND (niOOl0l AND (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOl1O698w(0)))); + wire_niil_dataout <= wire_nlO01li_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(33); + wire_niil0l_dataout <= wire_niiliO_dataout WHEN rwa_6g_en = '1' ELSE (wire_nl1l0i_dataout AND (niOOl0i AND niOOlil)); + wire_niil1l_dataout <= (wire_nl1l1O_dataout AND (niOOl0i AND niOOl0O)) AND rwa_6g_en; + wire_niili_dataout <= rx_data_dt(0) AND NOT(nl111Ol); + wire_niiliO_dataout <= (wire_nl1l0i_dataout AND (niOOlil AND (wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOl0O688w(0)))) AND rdwidth; + wire_niill_dataout <= rrx_pipe_enable WHEN nl111Ol = '1' ELSE rx_data_dt(1); + wire_niilO_dataout <= rx_data_dt(2) OR nl111Ol; + wire_niilOi_dataout <= wire_niilOl_dataout AND rwa_6g_en; + wire_niilOl_dataout <= (wire_nl1l0i_dataout AND ((wire_w_lg_rbytordplden683w(0) OR wire_w_lg_niOOlil684w(0)) AND niOOlii)) AND rdwidth; + wire_niiO_dataout <= wire_nlO01ll_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(34); + wire_niiOi_dataout <= rx_data_dt(3) OR nl111Ol; + wire_niiOl_dataout <= rx_data_dt(4) OR nl111Ol; + wire_niiOO_dataout <= rrx_pipe_enable WHEN nl111Ol = '1' ELSE rx_data_dt(5); + wire_nil_dataout <= wire_nlO0ili_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(63); + wire_nil0i_dataout <= wire_nil0O_dataout WHEN nl111Ol = '1' ELSE wire_niO_dataout; + wire_nil0l_dataout <= wire_nli1l_o AND NOT(nl111Ol); + wire_nil0O_dataout <= wire_niO_dataout OR rrx_pipe_enable; + wire_nil1i_dataout <= rrx_pipe_enable WHEN nl111Ol = '1' ELSE rx_data_dt(6); + wire_nil1l_dataout <= rx_data_dt(7) OR nl111Ol; + wire_nil1O_dataout <= rx_control_dt(0) OR nl111Ol; + wire_nili_dataout <= wire_nlO01lO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(35); + wire_nill_dataout <= wire_nlO01Oi_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(36); + wire_nilO_dataout <= wire_nlO01Ol_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(37); + wire_niO_dataout <= invalid_code_delay(0) WHEN rinvalid_code_err_only = '1' ELSE ((disp_err_delay(0) OR invalid_code_delay(0)) OR (NOT (nl101iO6 XOR nl101iO5))); + wire_niO_w_lg_dataout512w(0) <= wire_niO_dataout AND wire_w_lg_w_lg_rsync_sm_dis1w511w(0); + wire_niOi_dataout <= wire_nlO01OO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(38); + wire_niOiiO_dataout <= wire_niOili_dataout AND NOT(niiOiO); + wire_niOili_dataout <= wire_niOill_dataout AND NOT(niOOlli); + wire_niOill_dataout <= wire_niOilO_dataout AND (wire_ni1liO_w_lg_dataout678w(0) AND wire_ni1lli_w_lg_w_lg_w_lg_dataout679w680w681w(0)); + wire_niOilO_dataout <= n1i0O WHEN rwa_6g_en = '1' ELSE wire_niOiOi_dataout; + wire_niOiOi_dataout <= wire_niOiOl_dataout WHEN rbytord_s2gx = '1' ELSE n1i0O; + wire_niOiOl_dataout <= n1i0O WHEN rbytordplden = '1' ELSE wire_niOiOO_dataout; + wire_niOiOO_dataout <= n1i0O AND NOT(n1i0i); + wire_niOl_dataout <= wire_nlO001i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(39); + wire_niOl0i_dataout <= niOi0i OR nl111li; + wire_niOl0O_dataout <= wire_ni1liO_dataout WHEN niOOliO = '1' ELSE wire_niOlli_dataout; + wire_niOl1O_dataout <= wire_niOl0i_dataout AND NOT((wire_nli1ii_w_lg_niOi0l676w(0) AND niOi0O)); + wire_niOlii_dataout <= wire_ni1lli_dataout WHEN niOOliO = '1' ELSE wire_niOlll_dataout; + wire_niOlil_dataout <= wire_ni1lll_dataout WHEN niOOliO = '1' ELSE wire_niOllO_dataout; + wire_niOliO_dataout <= wire_ni1llO_dataout WHEN niOOliO = '1' ELSE wire_niOlOi_dataout; + wire_niOlli_dataout <= niiO0l AND NOT(niOOlli); + wire_niOlll_dataout <= niiO0O AND NOT(niOOlli); + wire_niOllO_dataout <= niiOii AND NOT(niOOlli); + wire_niOlOi_dataout <= niiOil AND NOT(niOOlli); + wire_niOlOl_dataout <= wire_nli0li_dataout WHEN rrxpcsbypass_en = '1' ELSE nl000i; + wire_niOlOO_dataout <= wire_nli0ll_dataout WHEN rrxpcsbypass_en = '1' ELSE nl000l; + wire_niOO_dataout <= wire_nlO001l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(40); + wire_niOO0i_dataout <= wire_nli0OO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00iO; + wire_niOO0l_dataout <= wire_nlii1i_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00li; + wire_niOO0O_dataout <= wire_nlii1l_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00ll; + wire_niOO1i_dataout <= wire_nli0lO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl000O; + wire_niOO1l_dataout <= wire_nli0Oi_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00ii; + wire_niOO1O_dataout <= wire_nli0Ol_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00il; + wire_niOOii_dataout <= wire_nlii1O_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00lO; + wire_niOOil_dataout <= wire_nlii0i_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00Oi; + wire_niOOiO_dataout <= wire_nlii0l_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00Ol; + wire_niOOl_dataout <= (nl11i0i AND nll1ll) WHEN tenb_data(18) = '1' ELSE (nl11i0i AND nll1OO); + wire_niOOli_dataout <= wire_nlii0O_dataout WHEN rrxpcsbypass_en = '1' ELSE nl00OO; + wire_niOOll_dataout <= wire_nliiii_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0i1i; + wire_niOOlO_dataout <= wire_nliiil_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0i1l; + wire_niOOOi_dataout <= wire_nliiiO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0i1O; + wire_niOOOl_dataout <= wire_nliili_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0i0i; + wire_niOOOO_dataout <= wire_nliill_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0i0l; + wire_nl010l_dataout <= wire_nl01ii_dataout WHEN rmaster_rx = '1' ELSE wire_nl010O_dataout; + wire_nl010O_dataout <= rd_enable_quad_up WHEN rmaster_up_rx = '1' ELSE rd_enable_quad_down; + wire_nl01ii_dataout <= nl1OOO WHEN rindv_rx = '1' ELSE rd_enable_centrl; + wire_nl01il_dataout <= (nl011i AND pld_re) WHEN rrxphfifopldctl_en = '1' ELSE nl011i; + wire_nl0i_dataout <= wire_nlO000O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(44); + wire_nl0l_dataout <= wire_nlO00ii_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(45); + wire_nl0O_dataout <= wire_nlO00il_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(46); + wire_nl100i_dataout <= nlO00O WHEN rrxpcsbypass_en = '1' ELSE nl0liO; + wire_nl100l_dataout <= nlO0ii WHEN rrxpcsbypass_en = '1' ELSE nl0lli; + wire_nl100O_dataout <= nlO0il WHEN rrxpcsbypass_en = '1' ELSE nl0lll; + wire_nl101i_dataout <= nlO01O WHEN rrxpcsbypass_en = '1' ELSE nl0l0O; + wire_nl101l_dataout <= nlO00i WHEN rrxpcsbypass_en = '1' ELSE nl0lii; + wire_nl101O_dataout <= nlO00l WHEN rrxpcsbypass_en = '1' ELSE nl0lil; + wire_nl10ii_dataout <= nlO0iO WHEN rrxpcsbypass_en = '1' ELSE nl0llO; + wire_nl10il_dataout <= nlO0li WHEN rrxpcsbypass_en = '1' ELSE nl0lOi; + wire_nl10iO_dataout <= nlO0ll WHEN rrxpcsbypass_en = '1' ELSE nl0lOl; + wire_nl10li_dataout <= nlO0lO WHEN rrxpcsbypass_en = '1' ELSE nl0lOO; + wire_nl10ll_dataout <= nlO0Oi WHEN rrxpcsbypass_en = '1' ELSE nl0O1i; + wire_nl10lO_dataout <= nlO0Ol WHEN rrxpcsbypass_en = '1' ELSE nl0O1l; + wire_nl10Oi_dataout <= nlO0OO WHEN rrxpcsbypass_en = '1' ELSE nl0O1O; + wire_nl10Ol_dataout <= nlOi1i WHEN rrxpcsbypass_en = '1' ELSE nl0O0i; + wire_nl10OO_dataout <= nlOi1l WHEN rrxpcsbypass_en = '1' ELSE nl0O0l; + wire_nl110i_dataout <= wire_nliiOO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0iiO; + wire_nl110l_dataout <= wire_nlil1i_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0ili; + wire_nl110O_dataout <= wire_nlil1l_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0ill; + wire_nl111i_dataout <= wire_nliilO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0i0O; + wire_nl111l_dataout <= wire_nliiOi_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0iii; + wire_nl111O_dataout <= wire_nliiOl_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0iil; + wire_nl11ii_dataout <= wire_nlil1O_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0ilO; + wire_nl11il_dataout <= wire_nlil0i_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0iOi; + wire_nl11iO_dataout <= wire_nlil0l_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0iOl; + wire_nl11li_dataout <= wire_nlil0O_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0iOO; + wire_nl11ll_dataout <= wire_nlilii_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0l1i; + wire_nl11lO_dataout <= wire_nlilil_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0l1l; + wire_nl11Oi_dataout <= wire_nliliO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0l1O; + wire_nl11Ol_dataout <= wire_nlilli_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0l0i; + wire_nl11OO_dataout <= wire_nlilll_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0l0l; + wire_nl1i_dataout <= wire_nlO001O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(41); + wire_nl1i0i_dataout <= nlOi0O WHEN rrxpcsbypass_en = '1' ELSE nl0OiO; + wire_nl1i0l_dataout <= nlOiii WHEN rrxpcsbypass_en = '1' ELSE nl0Oli; + wire_nl1i0O_dataout <= nlOiil WHEN rrxpcsbypass_en = '1' ELSE nl0Oll; + wire_nl1i1i_dataout <= nlOi1O WHEN rrxpcsbypass_en = '1' ELSE nl0O0O; + wire_nl1i1l_dataout <= nlOi0i WHEN rrxpcsbypass_en = '1' ELSE nl0Oii; + wire_nl1i1O_dataout <= nlOi0l WHEN rrxpcsbypass_en = '1' ELSE nl0Oil; + wire_nl1iii_dataout <= nlOiiO WHEN rrxpcsbypass_en = '1' ELSE nl0OlO; + wire_nl1iil_dataout <= nlOili WHEN rrxpcsbypass_en = '1' ELSE nl0OOi; + wire_nl1iiO_dataout <= nlOill WHEN rrxpcsbypass_en = '1' ELSE nl0OOl; + wire_nl1ili_dataout <= nlOilO WHEN rrxpcsbypass_en = '1' ELSE nl0OOO; + wire_nl1ill_dataout <= nlOiOi WHEN rrxpcsbypass_en = '1' ELSE nli11i; + wire_nl1ilO_dataout <= nlOiOl WHEN rrxpcsbypass_en = '1' ELSE nli11l; + wire_nl1iOi_dataout <= nlOiOO WHEN rrxpcsbypass_en = '1' ELSE nli11O; + wire_nl1iOl_dataout <= nlOl1i WHEN rrxpcsbypass_en = '1' ELSE nli10i; + wire_nl1iOO_dataout <= nlOl1l WHEN rrxpcsbypass_en = '1' ELSE nli10l; + wire_nl1l_dataout <= wire_nlO000i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(42); + wire_nl1l0i_dataout <= wire_nl1l0O_dataout AND NOT(niOOlOl); + wire_nl1l0i_w_lg_dataout5769w(0) <= NOT wire_nl1l0i_dataout; + wire_nl1l0l_dataout <= wire_nl1lii_dataout AND NOT(niOOlOi); + wire_nl1l0O_dataout <= wire_nl1lil_dataout AND NOT(niOOlOi); + wire_nl1l1i_dataout <= nlOl1O WHEN rrxpcsbypass_en = '1' ELSE nli10O; + wire_nl1l1l_dataout <= nlOl0l WHEN rrxpcsbypass_en = '1' ELSE nli1il; + wire_nl1l1O_dataout <= wire_nl1l0l_dataout AND NOT(niOOlOl); + wire_nl1l1O_w_lg_dataout5768w(0) <= NOT wire_nl1l1O_dataout; + wire_nl1lii_dataout <= wire_nl1liO_dataout AND NOT(niOOllO); + wire_nl1lil_dataout <= nl001O WHEN niOOllO = '1' ELSE wire_nl1lli_dataout; + wire_nl1liO_dataout <= wire_nl1lll_dataout AND NOT(niOOlll); + wire_nl1lli_dataout <= wire_nl1llO_dataout AND NOT(niOOlll); + wire_nl1lll_dataout <= niOi0i WHEN rbytordplden = '1' ELSE wire_nl1lOi_dataout; + wire_nl1llO_dataout <= niOi0i WHEN rbytordplden = '1' ELSE wire_nl1lOl_dataout; + wire_nl1lOi_dataout <= (nl00Ol OR nl0iOO) WHEN rwa_6g_en = '1' ELSE nl001l; + wire_nl1lOl_dataout <= (nli11l OR nl0O1i) WHEN rwa_6g_en = '1' ELSE nl001O; + wire_nl1O_dataout <= wire_nlO000l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(43); + wire_nli_dataout <= invalid_code_delay(1) WHEN rinvalid_code_err_only = '1' ELSE (disp_err_delay(1) OR invalid_code_delay(1)); + wire_nli_w_lg_dataout535w(0) <= wire_nli_dataout AND wire_w_lg_w_lg_rsync_sm_dis1w534w(0); + wire_nli00O_dataout <= nli00l AND NOT(scan_mode); + wire_nli00O_w_lg_dataout647w(0) <= NOT wire_nli00O_dataout; + wire_nli01l_dataout <= nli1iO AND NOT(scan_mode); + wire_nli01l_w_lg_dataout653w(0) <= NOT wire_nli01l_dataout; + wire_nli0li_dataout <= wire_n1lOi_dataout WHEN niOOOil = '1' ELSE nll0Oi; + wire_nli0ll_dataout <= wire_n1lOl_dataout WHEN niOOOil = '1' ELSE nll0Ol; + wire_nli0lO_dataout <= wire_n1lOO_dataout WHEN niOOOil = '1' ELSE nll0OO; + wire_nli0Oi_dataout <= wire_n1O1i_dataout WHEN niOOOil = '1' ELSE nlli1i; + wire_nli0Ol_dataout <= wire_n1O1l_dataout WHEN niOOOil = '1' ELSE nlli1l; + wire_nli0OO_dataout <= wire_n1O1O_dataout WHEN niOOOil = '1' ELSE nlli1O; + wire_nli1li_dataout <= wire_nli1lO_dataout WHEN rmaster_rx = '1' ELSE wire_nli1ll_dataout; + wire_nli1ll_dataout <= wr_enable_quad_up WHEN rmaster_up_rx = '1' ELSE wr_enable_quad_down; + wire_nli1lO_dataout <= nl01li WHEN rindv_rx = '1' ELSE wr_enable_centrl; + wire_nli1Oi_dataout <= (nl01ll AND wire_nli1ii_w_lg_nl01Oi645w(0)) WHEN rrxphfifopldctl_en = '1' ELSE nl01ll; + wire_nlii_dataout <= wire_nlO00iO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(47); + wire_nlii0i_dataout <= wire_n1Oii_dataout WHEN niOOOil = '1' ELSE nlliii; + wire_nlii0l_dataout <= nlliil AND NOT(niOOOil); + wire_nlii0O_dataout <= nlliiO AND NOT(niOOOil); + wire_nlii1i_dataout <= wire_n1O0i_dataout WHEN niOOOil = '1' ELSE nlli0i; + wire_nlii1l_dataout <= wire_n1O0l_dataout WHEN niOOOil = '1' ELSE nlli0l; + wire_nlii1O_dataout <= wire_n1O0O_dataout WHEN niOOOil = '1' ELSE nlli0O; + wire_nliiii_dataout <= wire_n010i_dataout WHEN niOOOil = '1' ELSE nllili; + wire_nliiil_dataout <= nllill AND NOT(niOOOil); + wire_nliiiO_dataout <= nllilO AND NOT(niOOOil); + wire_nliili_dataout <= nlliOi AND NOT(niOOOil); + wire_nliill_dataout <= wire_n1Oil_dataout WHEN niOOOil = '1' ELSE nlliOl; + wire_nliilO_dataout <= wire_n1OiO_dataout WHEN niOOOil = '1' ELSE nlliOO; + wire_nliiOi_dataout <= wire_n1Oli_dataout WHEN niOOOil = '1' ELSE nlll1i; + wire_nliiOl_dataout <= wire_n1Oll_dataout WHEN niOOOil = '1' ELSE nlll1l; + wire_nliiOO_dataout <= wire_n1OlO_dataout WHEN niOOOil = '1' ELSE nlll1O; + wire_nlil_dataout <= wire_nlO00li_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(48); + wire_nlil0i_dataout <= wire_n011i_dataout WHEN niOOOil = '1' ELSE nlllii; + wire_nlil0l_dataout <= wire_n011l_dataout WHEN niOOOil = '1' ELSE nlllil; + wire_nlil0O_dataout <= nllliO AND NOT(niOOOil); + wire_nlil1i_dataout <= wire_n1OOi_dataout WHEN niOOOil = '1' ELSE nlll0i; + wire_nlil1l_dataout <= wire_n1OOl_dataout WHEN niOOOil = '1' ELSE nlll0l; + wire_nlil1O_dataout <= wire_n1OOO_dataout WHEN niOOOil = '1' ELSE nlll0O; + wire_nlilii_dataout <= nlllli AND NOT(niOOOil); + wire_nlilil_dataout <= wire_n010i_dataout WHEN niOOOil = '1' ELSE nlllll; + wire_nliliO_dataout <= nllllO AND NOT(niOOOil); + wire_nlilli_dataout <= nlllOi AND NOT(niOOOil); + wire_nlilll_dataout <= nlllOl AND NOT(niOOOil); + wire_nlilOi_dataout <= dec_data_valid(0) WHEN nl101Ol = '1' ELSE nli0iO; + wire_nlilOi_w_lg_dataout523w(0) <= NOT wire_nlilOi_dataout; + wire_nlilOl_dataout <= dec_data_valid(1) WHEN nl101Ol = '1' ELSE nlilOO; + wire_nlilOl_w_lg_dataout545w(0) <= NOT wire_nlilOl_dataout; + wire_nliO_dataout <= wire_nlO00ll_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(49); + wire_nliOl_dataout <= (nl101il AND nll1li) WHEN tenb_data(8) = '1' ELSE (nl101il AND nll1Ol); + wire_nlli_dataout <= wire_nlO00lO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(50); + wire_nlll_dataout <= wire_nlO00Oi_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(51); + wire_nllO_dataout <= wire_nlO00Ol_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(52); + wire_nlO0ill_dataout <= niliOi WHEN niOOliO = '1' ELSE wire_nlOi0OO_dataout; + wire_nlO0ilO_dataout <= niliOl WHEN niOOliO = '1' ELSE wire_nlOii1i_dataout; + wire_nlO0iOi_dataout <= niliOO WHEN niOOliO = '1' ELSE wire_nlOii1l_dataout; + wire_nlO0iOl_dataout <= nill1i WHEN niOOliO = '1' ELSE wire_nlOii1O_dataout; + wire_nlO0iOO_dataout <= nill1l WHEN niOOliO = '1' ELSE wire_nlOii0i_dataout; + wire_nlO0l0i_dataout <= nill0O WHEN niOOliO = '1' ELSE wire_nlOiiil_dataout; + wire_nlO0l0l_dataout <= nillii WHEN niOOliO = '1' ELSE wire_nlOiiiO_dataout; + wire_nlO0l0O_dataout <= nillil WHEN niOOliO = '1' ELSE wire_nlOiili_dataout; + wire_nlO0l1i_dataout <= nill1O WHEN niOOliO = '1' ELSE wire_nlOii0l_dataout; + wire_nlO0l1l_dataout <= nill0i WHEN niOOliO = '1' ELSE wire_nlOii0O_dataout; + wire_nlO0l1O_dataout <= nill0l WHEN niOOliO = '1' ELSE wire_nlOiiii_dataout; + wire_nlO0lii_dataout <= nilliO WHEN niOOliO = '1' ELSE wire_nlOiill_dataout; + wire_nlO0lil_dataout <= nillli WHEN niOOliO = '1' ELSE wire_nlOiilO_dataout; + wire_nlO0liO_dataout <= nillll WHEN niOOliO = '1' ELSE wire_nlOiiOi_dataout; + wire_nlO0lli_dataout <= nilllO WHEN niOOliO = '1' ELSE wire_nlOiiOl_dataout; + wire_nlO0lll_dataout <= nillOi WHEN niOOliO = '1' ELSE wire_nlOiiOO_dataout; + wire_nlO0llO_dataout <= wire_nlOl00l_dataout WHEN niOOliO = '1' ELSE wire_nlOil1i_dataout; + wire_nlO0lOi_dataout <= wire_nlOl00O_dataout WHEN niOOliO = '1' ELSE wire_nlOil1l_dataout; + wire_nlO0lOl_dataout <= wire_nlOl0ii_dataout WHEN niOOliO = '1' ELSE wire_nlOil1O_dataout; + wire_nlO0lOO_dataout <= wire_nlOl0il_dataout WHEN niOOliO = '1' ELSE wire_nlOil0i_dataout; + wire_nlO0O_dataout <= rxstatus_int(0) WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(67); + wire_nlO0O0i_dataout <= wire_nlOl0lO_dataout WHEN niOOliO = '1' ELSE wire_nlOilil_dataout; + wire_nlO0O0l_dataout <= wire_nlOl0Oi_dataout WHEN niOOliO = '1' ELSE wire_nlOiliO_dataout; + wire_nlO0O0O_dataout <= wire_nlOl0Ol_dataout WHEN niOOliO = '1' ELSE wire_nlOilli_dataout; + wire_nlO0O1i_dataout <= wire_nlOl0iO_dataout WHEN niOOliO = '1' ELSE wire_nlOil0l_dataout; + wire_nlO0O1l_dataout <= wire_nlOl0li_dataout WHEN niOOliO = '1' ELSE wire_nlOil0O_dataout; + wire_nlO0O1O_dataout <= wire_nlOl0ll_dataout WHEN niOOliO = '1' ELSE wire_nlOilii_dataout; + wire_nlO0Oii_dataout <= wire_nlOl0OO_dataout WHEN niOOliO = '1' ELSE wire_nlOilll_dataout; + wire_nlO0Oil_dataout <= wire_nlOli1i_dataout WHEN niOOliO = '1' ELSE wire_nlOillO_dataout; + wire_nlO0OiO_dataout <= wire_nlOli1l_dataout WHEN niOOliO = '1' ELSE wire_nlOilOi_dataout; + wire_nlO0Oli_dataout <= wire_nlOli1O_dataout WHEN niOOliO = '1' ELSE wire_nlOilOl_dataout; + wire_nlO0Oll_dataout <= wire_nlOli0i_dataout WHEN niOOliO = '1' ELSE wire_nlOilOO_dataout; + wire_nlO0OlO_dataout <= wire_nlOli0l_dataout WHEN niOOliO = '1' ELSE wire_nlOiO1i_dataout; + wire_nlO0OOi_dataout <= wire_nlOli0O_dataout WHEN niOOliO = '1' ELSE wire_nlOiO1l_dataout; + wire_nlO0OOl_dataout <= wire_nlOliii_dataout WHEN niOOliO = '1' ELSE wire_nlOiO1O_dataout; + wire_nlO0OOO_dataout <= wire_nlOliil_dataout WHEN niOOliO = '1' ELSE wire_nlOiO0i_dataout; + wire_nlO1i0i_dataout <= wire_nlO1i0l_dataout AND nlO1ili; + wire_nlO1i0l_dataout <= wire_nlO1iii_dataout WHEN rmaster_rx = '1' ELSE wire_nlO1i0O_dataout; + wire_nlO1i0O_dataout <= wire_w_lg_rx_we_in_quad_up4644w(0) WHEN rmaster_up_rx = '1' ELSE wire_w_lg_rx_we_in_quad_down4643w(0); + wire_nlO1iii_dataout <= wire_nlO1i1i_w_lg_nlO1i1l613w(0) WHEN rindv_rx = '1' ELSE wire_w_lg_rx_we_in_centrl4642w(0); + wire_nlO1iil_dataout <= wire_nlO1iiO_dataout AND nlO10Ol; + wire_nlO1iiO_dataout <= nl010i OR nlO1ili; + wire_nlO1ill_dataout <= wire_nlO1l1l_dataout WHEN (wire_w_lg_rwa_6g_en2w(0) AND rbytord_s2gx) = '1' ELSE wire_nlO1ilO_dataout; + wire_nlO1ilO_dataout <= wire_nlO1iOi_dataout AND NOT(niOlO1l); + wire_nlO1iOi_dataout <= niiOiO OR niOlO1O; + wire_nlO1l0i_dataout <= niiOiO OR (niOlO1O AND wire_n1ill_w_lg_n1i0i4636w(0)); + wire_nlO1l1l_dataout <= wire_nlO1ilO_dataout WHEN rbytordplden = '1' ELSE wire_nlO1l1O_dataout; + wire_nlO1l1O_dataout <= wire_nlO1l0i_dataout AND NOT(niOlO1l); + wire_nlOi_dataout <= wire_nlO00OO_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(53); + wire_nlOi00i_dataout <= wire_nlOlllO_dataout WHEN niOOliO = '1' ELSE wire_nlOl1il_dataout; + wire_nlOi00l_dataout <= wire_nlOllOi_dataout WHEN niOOliO = '1' ELSE wire_nlOl1iO_dataout; + wire_nlOi00O_dataout <= wire_nlOllOl_dataout WHEN niOOliO = '1' ELSE wire_nlOl1li_dataout; + wire_nlOi01i_dataout <= wire_nlOlliO_dataout WHEN niOOliO = '1' ELSE wire_nlOl10l_dataout; + wire_nlOi01l_dataout <= wire_nlOllli_dataout WHEN niOOliO = '1' ELSE wire_nlOl10O_dataout; + wire_nlOi01O_dataout <= wire_nlOllll_dataout WHEN niOOliO = '1' ELSE wire_nlOl1ii_dataout; + wire_nlOi0ii_dataout <= wire_nlOllOO_dataout WHEN niOOliO = '1' ELSE wire_nlOl1ll_dataout; + wire_nlOi0il_dataout <= wire_nlOlO1i_dataout WHEN niOOliO = '1' ELSE wire_nlOl1lO_dataout; + wire_nlOi0iO_dataout <= wire_nlOlO1l_dataout WHEN niOOliO = '1' ELSE wire_nlOl1Oi_dataout; + wire_nlOi0li_dataout <= wire_nlOlO1O_dataout WHEN niOOliO = '1' ELSE wire_nlOl1Ol_dataout; + wire_nlOi0ll_dataout <= wire_nlOlO0i_dataout WHEN niOOliO = '1' ELSE wire_nlOl1OO_dataout; + wire_nlOi0lO_dataout <= wire_nlOlO0l_dataout WHEN niOOliO = '1' ELSE wire_nlOl01i_dataout; + wire_nlOi0Oi_dataout <= wire_nlOlO0O_dataout WHEN niOOliO = '1' ELSE wire_nlOl01l_dataout; + wire_nlOi0Ol_dataout <= wire_nlOlOii_dataout WHEN niOOliO = '1' ELSE wire_nlOl01O_dataout; + wire_nlOi0OO_dataout <= nil1ll WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niliOi; + wire_nlOi10i_dataout <= wire_nlOlilO_dataout WHEN niOOliO = '1' ELSE wire_nlOiOil_dataout; + wire_nlOi10l_dataout <= wire_nlOliOi_dataout WHEN niOOliO = '1' ELSE wire_nlOiOiO_dataout; + wire_nlOi10O_dataout <= wire_nlOliOl_dataout WHEN niOOliO = '1' ELSE wire_nlOiOli_dataout; + wire_nlOi11i_dataout <= wire_nlOliiO_dataout WHEN niOOliO = '1' ELSE wire_nlOiO0l_dataout; + wire_nlOi11l_dataout <= wire_nlOlili_dataout WHEN niOOliO = '1' ELSE wire_nlOiO0O_dataout; + wire_nlOi11O_dataout <= wire_nlOlill_dataout WHEN niOOliO = '1' ELSE wire_nlOiOii_dataout; + wire_nlOi1ii_dataout <= wire_nlOliOO_dataout WHEN niOOliO = '1' ELSE wire_nlOiOll_dataout; + wire_nlOi1il_dataout <= wire_nlOll1i_dataout WHEN niOOliO = '1' ELSE wire_nlOiOlO_dataout; + wire_nlOi1iO_dataout <= wire_nlOll1l_dataout WHEN niOOliO = '1' ELSE wire_nlOiOOi_dataout; + wire_nlOi1li_dataout <= wire_nlOll1O_dataout WHEN niOOliO = '1' ELSE wire_nlOiOOl_dataout; + wire_nlOi1ll_dataout <= wire_nlOll0i_dataout WHEN niOOliO = '1' ELSE wire_nlOiOOO_dataout; + wire_nlOi1lO_dataout <= wire_nlOll0l_dataout WHEN niOOliO = '1' ELSE wire_nlOl11i_dataout; + wire_nlOi1Oi_dataout <= wire_nlOll0O_dataout WHEN niOOliO = '1' ELSE wire_nlOl11l_dataout; + wire_nlOi1Ol_dataout <= wire_nlOllii_dataout WHEN niOOliO = '1' ELSE wire_nlOl11O_dataout; + wire_nlOi1OO_dataout <= wire_nlOllil_dataout WHEN niOOliO = '1' ELSE wire_nlOl10i_dataout; + wire_nlOii_dataout <= rxstatus_int(1) WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(68); + wire_nlOii0i_dataout <= nil1OO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nill1l; + wire_nlOii0l_dataout <= nil01i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nill1O; + wire_nlOii0O_dataout <= nil01l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nill0i; + wire_nlOii1i_dataout <= nil1lO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niliOl; + wire_nlOii1l_dataout <= nil1Oi WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niliOO; + wire_nlOii1O_dataout <= nil1Ol WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nill1i; + wire_nlOiiii_dataout <= nil01O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nill0l; + wire_nlOiiil_dataout <= nil00i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nill0O; + wire_nlOiiiO_dataout <= nil00l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nillii; + wire_nlOiili_dataout <= nil00O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nillil; + wire_nlOiill_dataout <= nil0ii WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilliO; + wire_nlOiilO_dataout <= nil0il WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nillli; + wire_nlOiiOi_dataout <= nil0iO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nillll; + wire_nlOiiOl_dataout <= nil0li WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilllO; + wire_nlOiiOO_dataout <= nil0ll WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nillOi; + wire_nlOil_dataout <= rxstatus_int(2) WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(69); + wire_nlOil0i_dataout <= nil0OO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilO1l; + wire_nlOil0l_dataout <= nili1i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilO1O; + wire_nlOil0O_dataout <= nili1l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilO0i; + wire_nlOil1i_dataout <= nil0lO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nillOl; + wire_nlOil1l_dataout <= nil0Oi WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nillOO; + wire_nlOil1O_dataout <= nil0Ol WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilO1i; + wire_nlOilii_dataout <= nili1O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilO0l; + wire_nlOilil_dataout <= nili0i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilO0O; + wire_nlOiliO_dataout <= nili0l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOii; + wire_nlOilli_dataout <= nili0O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOil; + wire_nlOilll_dataout <= niliii WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOiO; + wire_nlOillO_dataout <= niliil WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOli; + wire_nlOilOi_dataout <= niliiO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOll; + wire_nlOilOl_dataout <= nilili WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOlO; + wire_nlOilOO_dataout <= nilill WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOOi; + wire_nlOiO_dataout <= rxvalid_int WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(66); + wire_nlOiO0i_dataout <= niliOO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO11l; + wire_nlOiO0l_dataout <= nill1i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO11O; + wire_nlOiO0O_dataout <= nill1l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO10i; + wire_nlOiO1i_dataout <= nililO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOOl; + wire_nlOiO1l_dataout <= niliOi WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE nilOOO; + wire_nlOiO1O_dataout <= niliOl WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO11i; + wire_nlOiOii_dataout <= nill1O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO10l; + wire_nlOiOil_dataout <= nill0i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO10O; + wire_nlOiOiO_dataout <= nill0l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1ii; + wire_nlOiOli_dataout <= nill0O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1il; + wire_nlOiOll_dataout <= nillii WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1iO; + wire_nlOiOlO_dataout <= nillil WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1li; + wire_nlOiOOi_dataout <= nilliO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1ll; + wire_nlOiOOl_dataout <= nillli WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1lO; + wire_nlOiOOO_dataout <= nillll WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1Oi; + wire_nlOl_dataout <= wire_nlO0i1i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(54); + wire_nlOl00l_dataout <= nillOl AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl00O_dataout <= nillOO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl01i_dataout <= nilOlO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0Ol; + wire_nlOl01l_dataout <= nilOOi WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0OO; + wire_nlOl01O_dataout <= nilOOl WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niOi1i; + wire_nlOl0ii_dataout <= nilO1i AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0il_dataout <= nilO1l AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0iO_dataout <= nilO1O AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0li_dataout <= nilO0i AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0ll_dataout <= nilO0l AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0lO_dataout <= nilO0O AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0Oi_dataout <= nilOii AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0Ol_dataout <= nilOil AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl0OO_dataout <= nilOiO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOl10i_dataout <= nillOO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO01l; + wire_nlOl10l_dataout <= nilO1i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO01O; + wire_nlOl10O_dataout <= nilO1l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO00i; + wire_nlOl11i_dataout <= nilllO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1Ol; + wire_nlOl11l_dataout <= nillOi WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO1OO; + wire_nlOl11O_dataout <= nillOl WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO01i; + wire_nlOl1ii_dataout <= nilO1O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO00l; + wire_nlOl1il_dataout <= nilO0i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO00O; + wire_nlOl1iO_dataout <= nilO0l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0ii; + wire_nlOl1li_dataout <= nilO0O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0il; + wire_nlOl1ll_dataout <= nilOii WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0iO; + wire_nlOl1lO_dataout <= nilOil WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0li; + wire_nlOl1Oi_dataout <= nilOiO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0ll; + wire_nlOl1Ol_dataout <= nilOli WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0lO; + wire_nlOl1OO_dataout <= nilOll WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE niO0Oi; + wire_nlOli_dataout <= phystatus_int WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(65); + wire_nlOli0i_dataout <= nilOOi AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOli0l_dataout <= nilOOl AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOli0O_dataout <= rbytordpadval(0) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE nilOOO; + wire_nlOli1i_dataout <= nilOli AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOli1l_dataout <= nilOll AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOli1O_dataout <= nilOlO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlii_dataout <= nl1111O WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nliO1l; + wire_nlOliii_dataout <= rbytordpadval(1) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO11i; + wire_nlOliil_dataout <= rbytordpadval(2) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO11l; + wire_nlOliiO_dataout <= rbytordpadval(3) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO11O; + wire_nlOlil_dataout <= wire_n1lOi_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlllOO; + wire_nlOlili_dataout <= rbytordpadval(4) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO10i; + wire_nlOlill_dataout <= rbytordpadval(5) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO10l; + wire_nlOlilO_dataout <= rbytordpadval(6) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO10O; + wire_nlOliO_dataout <= wire_n1lOl_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllO1i; + wire_nlOliOi_dataout <= rbytordpadval(7) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO1ii; + wire_nlOliOl_dataout <= rbytordpadval(8) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO1il; + wire_nlOliOO_dataout <= rbytordpadval(9) WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO1iO; + wire_nlOll_dataout <= wire_nlO1ill_dataout WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(64); + wire_nlOll0i_dataout <= niO1Oi AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOll0l_dataout <= niO1Ol AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOll0O_dataout <= niO1OO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOll1i_dataout <= nillil WHEN wire_w_lg_niOlO0l3797w(0) = '1' ELSE niO1li; + wire_nlOll1l_dataout <= niO1ll AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOll1O_dataout <= niO1lO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlli_dataout <= wire_n1lOO_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllO1l; + wire_nlOllii_dataout <= niO01i AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOllil_dataout <= niO01l AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlliO_dataout <= niO01O AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlll_dataout <= wire_n1O1i_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllO1O; + wire_nlOllli_dataout <= niO00i AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOllll_dataout <= niO00l AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlllO_dataout <= niO00O AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOllO_dataout <= wire_n1O1l_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllO0i; + wire_nlOllOi_dataout <= niO0ii AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOllOl_dataout <= niO0il AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOllOO_dataout <= niO0iO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlO_dataout <= wire_nlO001O_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(41); + wire_nlOlO0i_dataout <= niO0Oi AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlO0l_dataout <= niO0Ol AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlO0O_dataout <= niO0OO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlO1i_dataout <= niO0li AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlO1l_dataout <= niO0ll AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlO1O_dataout <= niO0lO AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlOi_dataout <= wire_n1O1O_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllO0l; + wire_nlOlOii_dataout <= niOi1i AND NOT(wire_w_lg_niOlO0l3797w(0)); + wire_nlOlOiO_dataout <= wire_niOlOl_dataout WHEN niOOliO = '1' ELSE wire_nlOOlOi_dataout; + wire_nlOlOl_dataout <= wire_n1O0i_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllO0O; + wire_nlOlOli_dataout <= wire_niOlOO_dataout WHEN niOOliO = '1' ELSE wire_nlOOlOl_dataout; + wire_nlOlOll_dataout <= wire_niOO1i_dataout WHEN niOOliO = '1' ELSE wire_nlOOlOO_dataout; + wire_nlOlOlO_dataout <= wire_niOO1l_dataout WHEN niOOliO = '1' ELSE wire_nlOOO1i_dataout; + wire_nlOlOO_dataout <= wire_n1O0l_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOii; + wire_nlOlOOi_dataout <= wire_niOO1O_dataout WHEN niOOliO = '1' ELSE wire_nlOOO1l_dataout; + wire_nlOlOOl_dataout <= wire_niOO0i_dataout WHEN niOOliO = '1' ELSE wire_nlOOO1O_dataout; + wire_nlOlOOO_dataout <= wire_niOO0l_dataout WHEN niOOliO = '1' ELSE wire_nlOOO0i_dataout; + wire_nlOO_dataout <= wire_nlO0i1l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(55); + wire_nlOO00i_dataout <= wire_n11lll_dataout WHEN niOOliO = '1' ELSE wire_n111il_dataout; + wire_nlOO00l_dataout <= wire_n11llO_dataout WHEN niOOliO = '1' ELSE wire_n111iO_dataout; + wire_nlOO00O_dataout <= wire_n11lOi_dataout WHEN niOOliO = '1' ELSE wire_n111li_dataout; + wire_nlOO01i_dataout <= wire_n11lil_dataout WHEN niOOliO = '1' ELSE wire_n1110l_dataout; + wire_nlOO01l_dataout <= wire_n11liO_dataout WHEN niOOliO = '1' ELSE wire_n1110O_dataout; + wire_nlOO01O_dataout <= wire_n11lli_dataout WHEN niOOliO = '1' ELSE wire_n111ii_dataout; + wire_nlOO0i_dataout <= wire_n01ll_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOll; + wire_nlOO0ii_dataout <= wire_n11lOl_dataout WHEN niOOliO = '1' ELSE wire_n111ll_dataout; + wire_nlOO0il_dataout <= wire_n11lOO_dataout WHEN niOOliO = '1' ELSE wire_n111lO_dataout; + wire_nlOO0iO_dataout <= wire_n11O1i_dataout WHEN niOOliO = '1' ELSE wire_n111Oi_dataout; + wire_nlOO0l_dataout <= wire_n011O_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOlO; + wire_nlOO0li_dataout <= wire_n11O1l_dataout WHEN niOOliO = '1' ELSE wire_n111Ol_dataout; + wire_nlOO0ll_dataout <= wire_n11O1O_dataout WHEN niOOliO = '1' ELSE wire_n111OO_dataout; + wire_nlOO0lO_dataout <= wire_n11O0i_dataout WHEN niOOliO = '1' ELSE wire_n1101i_dataout; + wire_nlOO0O_dataout <= wire_n010l_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOOi; + wire_nlOO0Oi_dataout <= wire_n11O0l_dataout WHEN niOOliO = '1' ELSE wire_n1101l_dataout; + wire_nlOO0Ol_dataout <= wire_n11O0O_dataout WHEN niOOliO = '1' ELSE wire_n1101O_dataout; + wire_nlOO0OO_dataout <= wire_n11Oii_dataout WHEN niOOliO = '1' ELSE wire_n1100i_dataout; + wire_nlOO10i_dataout <= wire_niOOiO_dataout WHEN niOOliO = '1' ELSE wire_nlOOOil_dataout; + wire_nlOO10l_dataout <= wire_niOOli_dataout WHEN niOOliO = '1' ELSE wire_nlOOOiO_dataout; + wire_nlOO10O_dataout <= wire_niOOll_dataout WHEN niOOliO = '1' ELSE wire_nlOOOli_dataout; + wire_nlOO11i_dataout <= wire_niOO0O_dataout WHEN niOOliO = '1' ELSE wire_nlOOO0l_dataout; + wire_nlOO11l_dataout <= wire_niOOii_dataout WHEN niOOliO = '1' ELSE wire_nlOOO0O_dataout; + wire_nlOO11O_dataout <= wire_niOOil_dataout WHEN niOOliO = '1' ELSE wire_nlOOOii_dataout; + wire_nlOO1i_dataout <= wire_n1O0O_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOil; + wire_nlOO1ii_dataout <= wire_niOOlO_dataout WHEN niOOliO = '1' ELSE wire_nlOOOll_dataout; + wire_nlOO1il_dataout <= wire_niOOOi_dataout WHEN niOOliO = '1' ELSE wire_nlOOOlO_dataout; + wire_nlOO1iO_dataout <= wire_niOOOl_dataout WHEN niOOliO = '1' ELSE wire_nlOOOOi_dataout; + wire_nlOO1l_dataout <= wire_n1Oii_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOiO; + wire_nlOO1li_dataout <= wire_n11l1l_dataout WHEN niOOliO = '1' ELSE wire_nlOOOOl_dataout; + wire_nlOO1ll_dataout <= wire_n11l1O_dataout WHEN niOOliO = '1' ELSE wire_nlOOOOO_dataout; + wire_nlOO1lO_dataout <= wire_n11l0i_dataout WHEN niOOliO = '1' ELSE wire_n1111i_dataout; + wire_nlOO1O_dataout <= wire_n01Oi_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOli; + wire_nlOO1Oi_dataout <= wire_n11l0l_dataout WHEN niOOliO = '1' ELSE wire_n1111l_dataout; + wire_nlOO1Ol_dataout <= wire_n11l0O_dataout WHEN niOOliO = '1' ELSE wire_n1111O_dataout; + wire_nlOO1OO_dataout <= wire_n11lii_dataout WHEN niOOliO = '1' ELSE wire_n1110i_dataout; + wire_nlOOi_dataout <= wire_nlO0i0i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(57); + wire_nlOOi0i_dataout <= wire_n11Oll_dataout WHEN niOOliO = '1' ELSE wire_n110il_dataout; + wire_nlOOi0l_dataout <= wire_n11OlO_dataout WHEN niOOliO = '1' ELSE wire_n110iO_dataout; + wire_nlOOi0O_dataout <= wire_n11OOi_dataout WHEN niOOliO = '1' ELSE wire_n110li_dataout; + wire_nlOOi1i_dataout <= wire_n11Oil_dataout WHEN niOOliO = '1' ELSE wire_n1100l_dataout; + wire_nlOOi1l_dataout <= wire_n11OiO_dataout WHEN niOOliO = '1' ELSE wire_n1100O_dataout; + wire_nlOOi1O_dataout <= wire_n11Oli_dataout WHEN niOOliO = '1' ELSE wire_n110ii_dataout; + wire_nlOOii_dataout <= wire_n010O_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOOl; + wire_nlOOiii_dataout <= wire_n11OOl_dataout WHEN niOOliO = '1' ELSE wire_n110ll_dataout; + wire_nlOOiil_dataout <= wire_n11OOO_dataout WHEN niOOliO = '1' ELSE wire_n110lO_dataout; + wire_nlOOiiO_dataout <= wire_n1011i_dataout WHEN niOOliO = '1' ELSE wire_n110Oi_dataout; + wire_nlOOil_dataout <= wire_n01iO_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nllOOO; + wire_nlOOili_dataout <= wire_n1011l_dataout WHEN niOOliO = '1' ELSE wire_n110Ol_dataout; + wire_nlOOill_dataout <= wire_n1011O_dataout WHEN niOOliO = '1' ELSE wire_n110OO_dataout; + wire_nlOOilO_dataout <= wire_n1010i_dataout WHEN niOOliO = '1' ELSE wire_n11i1i_dataout; + wire_nlOOiO_dataout <= wire_n1Oil_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO11i; + wire_nlOOiOi_dataout <= wire_n1010l_dataout WHEN niOOliO = '1' ELSE wire_n11i1l_dataout; + wire_nlOOiOl_dataout <= wire_n1010O_dataout WHEN niOOliO = '1' ELSE wire_n11i1O_dataout; + wire_nlOOiOO_dataout <= wire_n101ii_dataout WHEN niOOliO = '1' ELSE wire_n11i0i_dataout; + wire_nlOOl_dataout <= wire_nlO1O1i_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(9); + wire_nlOOl0i_dataout <= wire_n101ll_dataout WHEN niOOliO = '1' ELSE wire_n11iil_dataout; + wire_nlOOl0l_dataout <= wire_n101lO_dataout WHEN niOOliO = '1' ELSE wire_n11iiO_dataout; + wire_nlOOl0O_dataout <= wire_n101Oi_dataout WHEN niOOliO = '1' ELSE wire_n11ili_dataout; + wire_nlOOl1i_dataout <= wire_n101il_dataout WHEN niOOliO = '1' ELSE wire_n11i0l_dataout; + wire_nlOOl1l_dataout <= wire_n101iO_dataout WHEN niOOliO = '1' ELSE wire_n11i0O_dataout; + wire_nlOOl1O_dataout <= wire_n101li_dataout WHEN niOOliO = '1' ELSE wire_n11iii_dataout; + wire_nlOOli_dataout <= wire_n1OiO_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO11l; + wire_nlOOlii_dataout <= wire_n101Ol_dataout WHEN niOOliO = '1' ELSE wire_n11ill_dataout; + wire_nlOOlil_dataout <= wire_n101OO_dataout WHEN niOOliO = '1' ELSE wire_n11ilO_dataout; + wire_nlOOliO_dataout <= wire_n1001i_dataout WHEN niOOliO = '1' ELSE wire_n11iOi_dataout; + wire_nlOOll_dataout <= wire_n1Oli_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO11O; + wire_nlOOlli_dataout <= wire_n1001l_dataout WHEN niOOliO = '1' ELSE wire_n11iOl_dataout; + wire_nlOOlll_dataout <= wire_n1001O_dataout WHEN niOOliO = '1' ELSE wire_n11iOO_dataout; + wire_nlOOllO_dataout <= wire_n1000i_dataout WHEN niOOliO = '1' ELSE wire_n11l1i_dataout; + wire_nlOOlO_dataout <= wire_n1Oll_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO10i; + wire_nlOOlOi_dataout <= nilOOO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOlOl_dataout; + wire_nlOOlOl_dataout <= niO11i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOlOO_dataout; + wire_nlOOlOO_dataout <= niO11l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOO1i_dataout; + wire_nlOOO_dataout <= wire_nlO011l_o WHEN rrxfifo_dis = '1' ELSE wire_nl1000i_data_out(25); + wire_nlOOO0i_dataout <= niO10O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOO0l_dataout; + wire_nlOOO0l_dataout <= niO1ii WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOO0O_dataout; + wire_nlOOO0O_dataout <= niO1il WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOii_dataout; + wire_nlOOO1i_dataout <= niO11O WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOO1l_dataout; + wire_nlOOO1l_dataout <= niO10i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOO1O_dataout; + wire_nlOOO1O_dataout <= niO10l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOO0i_dataout; + wire_nlOOOi_dataout <= wire_n1OlO_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO10l; + wire_nlOOOii_dataout <= niO1iO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOil_dataout; + wire_nlOOOil_dataout <= niO1li WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOiO_dataout; + wire_nlOOOiO_dataout <= niO1ll WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOli_dataout; + wire_nlOOOl_dataout <= wire_n1OOi_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO10O; + wire_nlOOOli_dataout <= niO1lO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOll_dataout; + wire_nlOOOll_dataout <= niO1Oi WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOlO_dataout; + wire_nlOOOlO_dataout <= niO1Ol WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOOi_dataout; + wire_nlOOOO_dataout <= wire_n1OOl_dataout WHEN wire_w_lg_nl1110l617w(0) = '1' ELSE nlO1ii; + wire_nlOOOOi_dataout <= niO1OO WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOOl_dataout; + wire_nlOOOOl_dataout <= niO01i WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_niOOOO_dataout; + wire_nlOOOOO_dataout <= niO01l WHEN wire_w_lg_niOlO0i3798w(0) = '1' ELSE wire_nl111i_dataout; + wire_n0iO0O_i <= ( wire_ni1lli_dataout & wire_ni1liO_dataout); + n0iO0O : oper_decoder + GENERIC MAP ( + width_i => 2, + width_o => 4 + ) + PORT MAP ( + i => wire_n0iO0O_i, + o => wire_n0iO0O_o + ); + wire_n0l0lO_i <= ( wire_ni1llO_dataout & wire_ni1lll_dataout & wire_ni1lli_dataout & wire_ni1liO_dataout); + n0l0lO : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_n0l0lO_i, + o => wire_n0l0lO_o + ); + wire_n0l1iO_i <= ( wire_ni1lll_dataout & wire_ni1lli_dataout & wire_ni1liO_dataout); + n0l1iO : oper_decoder + GENERIC MAP ( + width_i => 3, + width_o => 8 + ) + PORT MAP ( + i => wire_n0l1iO_i, + o => wire_n0l1iO_o + ); + wire_niOOi_w_lg_w_o_range432w434w(0) <= wire_niOOi_w_o_range432w(0) OR wire_niOOi_w_o_range433w(0); + wire_niOOi_w_lg_w_o_range437w439w(0) <= wire_niOOi_w_o_range437w(0) OR wire_niOOi_w_o_range438w(0); + wire_niOOi_w_lg_w_o_range441w443w(0) <= wire_niOOi_w_o_range441w(0) OR wire_niOOi_w_o_range442w(0); + wire_niOOi_w_lg_w_o_range445w447w(0) <= wire_niOOi_w_o_range445w(0) OR wire_niOOi_w_o_range446w(0); + wire_niOOi_w_lg_w_o_range449w451w(0) <= wire_niOOi_w_o_range449w(0) OR wire_niOOi_w_o_range450w(0); + wire_niOOi_w_lg_w_o_range453w455w(0) <= wire_niOOi_w_o_range453w(0) OR wire_niOOi_w_o_range454w(0); + wire_niOOi_w_lg_w_o_range457w459w(0) <= wire_niOOi_w_o_range457w(0) OR wire_niOOi_w_o_range458w(0); + wire_niOOi_w_lg_w_o_range461w463w(0) <= wire_niOOi_w_o_range461w(0) OR wire_niOOi_w_o_range462w(0); + wire_niOOi_w_lg_w_o_range465w467w(0) <= wire_niOOi_w_o_range465w(0) OR wire_niOOi_w_o_range466w(0); + wire_niOOi_i <= ( rwa_6g_en & rpmadatawidth & rsync_comp_size(2 DOWNTO 0) & tenb_data(18)); + wire_niOOi_w_o_range433w(0) <= wire_niOOi_o(16); + wire_niOOi_w_o_range432w(0) <= wire_niOOi_o(17); + wire_niOOi_w_o_range438w(0) <= wire_niOOi_o(20); + wire_niOOi_w_o_range437w(0) <= wire_niOOi_o(21); + wire_niOOi_w_o_range442w(0) <= wire_niOOi_o(34); + wire_niOOi_w_o_range441w(0) <= wire_niOOi_o(35); + wire_niOOi_w_o_range446w(0) <= wire_niOOi_o(38); + wire_niOOi_w_o_range445w(0) <= wire_niOOi_o(39); + wire_niOOi_w_o_range450w(0) <= wire_niOOi_o(42); + wire_niOOi_w_o_range449w(0) <= wire_niOOi_o(43); + wire_niOOi_w_o_range454w(0) <= wire_niOOi_o(48); + wire_niOOi_w_o_range453w(0) <= wire_niOOi_o(49); + wire_niOOi_w_o_range458w(0) <= wire_niOOi_o(52); + wire_niOOi_w_o_range457w(0) <= wire_niOOi_o(53); + wire_niOOi_w_o_range462w(0) <= wire_niOOi_o(56); + wire_niOOi_w_o_range461w(0) <= wire_niOOi_o(57); + wire_niOOi_w_o_range466w(0) <= wire_niOOi_o(60); + wire_niOOi_w_o_range465w(0) <= wire_niOOi_o(61); + niOOi : oper_decoder + GENERIC MAP ( + width_i => 6, + width_o => 64 + ) + PORT MAP ( + i => wire_niOOi_i, + o => wire_niOOi_o + ); + wire_nliOi_w_lg_w_lg_w_o_range217w219w223w(0) <= wire_nliOi_w_lg_w_o_range217w219w(0) OR wire_nl1011i16_w_lg_w_lg_q221w222w(0); + wire_nliOi_w_lg_w_lg_w_o_range235w237w241w(0) <= wire_nliOi_w_lg_w_o_range235w237w(0) OR wire_nl11OOi20_w_lg_w_lg_q239w240w(0); + wire_nliOi_w_lg_w_lg_w_o_range253w255w259w(0) <= wire_nliOi_w_lg_w_o_range253w255w(0) OR wire_nl11Oli24_w_lg_w_lg_q257w258w(0); + wire_nliOi_w_lg_w_o_range206w208w(0) <= wire_nliOi_w_o_range206w(0) OR wire_nliOi_w_o_range207w(0); + wire_nliOi_w_lg_w_o_range211w213w(0) <= wire_nliOi_w_o_range211w(0) OR wire_nliOi_w_o_range212w(0); + wire_nliOi_w_lg_w_o_range217w219w(0) <= wire_nliOi_w_o_range217w(0) OR wire_nliOi_w_o_range218w(0); + wire_nliOi_w_lg_w_o_range225w227w(0) <= wire_nliOi_w_o_range225w(0) OR wire_nliOi_w_o_range226w(0); + wire_nliOi_w_lg_w_o_range231w233w(0) <= wire_nliOi_w_o_range231w(0) OR wire_nliOi_w_o_range232w(0); + wire_nliOi_w_lg_w_o_range235w237w(0) <= wire_nliOi_w_o_range235w(0) OR wire_nliOi_w_o_range236w(0); + wire_nliOi_w_lg_w_o_range245w247w(0) <= wire_nliOi_w_o_range245w(0) OR wire_nliOi_w_o_range246w(0); + wire_nliOi_w_lg_w_o_range249w251w(0) <= wire_nliOi_w_o_range249w(0) OR wire_nliOi_w_o_range250w(0); + wire_nliOi_w_lg_w_o_range253w255w(0) <= wire_nliOi_w_o_range253w(0) OR wire_nliOi_w_o_range254w(0); + wire_nliOi_i <= ( rwa_6g_en & wire_nl1010l12_w_lg_w_lg_q111w112w & rsync_comp_size(2) & wire_nl1010O10_w_lg_w_lg_q106w107w & wire_nl101ii8_w_lg_w_lg_q102w103w & tenb_data(8)); + wire_nliOi_w_o_range207w(0) <= wire_nliOi_o(16); + wire_nliOi_w_o_range206w(0) <= wire_nliOi_o(17); + wire_nliOi_w_o_range212w(0) <= wire_nliOi_o(20); + wire_nliOi_w_o_range211w(0) <= wire_nliOi_o(21); + wire_nliOi_w_o_range218w(0) <= wire_nliOi_o(34); + wire_nliOi_w_o_range217w(0) <= wire_nliOi_o(35); + wire_nliOi_w_o_range226w(0) <= wire_nliOi_o(38); + wire_nliOi_w_o_range225w(0) <= wire_nliOi_o(39); + wire_nliOi_w_o_range232w(0) <= wire_nliOi_o(42); + wire_nliOi_w_o_range231w(0) <= wire_nliOi_o(43); + wire_nliOi_w_o_range236w(0) <= wire_nliOi_o(48); + wire_nliOi_w_o_range235w(0) <= wire_nliOi_o(49); + wire_nliOi_w_o_range246w(0) <= wire_nliOi_o(52); + wire_nliOi_w_o_range245w(0) <= wire_nliOi_o(53); + wire_nliOi_w_o_range250w(0) <= wire_nliOi_o(56); + wire_nliOi_w_o_range249w(0) <= wire_nliOi_o(57); + wire_nliOi_w_o_range254w(0) <= wire_nliOi_o(60); + wire_nliOi_w_o_range253w(0) <= wire_nliOi_o(61); + nliOi : oper_decoder + GENERIC MAP ( + width_i => 6, + width_o => 64 + ) + PORT MAP ( + i => wire_nliOi_i, + o => wire_nliOi_o + ); + wire_n00O0i_data <= ( nill1i & niiOOi & nill1i & nil1Ol & nill1i & niiOOi & nill1i & nil0OO & nill1i & niiOOi & nill1i & nil1Ol & nill1i & niiOOi & nill1i & nill1i); + wire_n00O0i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00O0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00O0i_data, + o => wire_n00O0i_o, + sel => wire_n00O0i_sel + ); + wire_n00O0l_data <= ( nill1l & niiOOl & nill1l & nil1OO & nill1l & niiOOl & nill1l & nili1i & nill1l & niiOOl & nill1l & nil1OO & nill1l & niiOOl & nill1l & nill1l); + wire_n00O0l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00O0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00O0l_data, + o => wire_n00O0l_o, + sel => wire_n00O0l_sel + ); + wire_n00O0O_data <= ( nill1O & niiOOO & nill1O & nil01i & nill1O & niiOOO & nill1O & nili1l & nill1O & niiOOO & nill1O & nil01i & nill1O & niiOOO & nill1O & nill1O); + wire_n00O0O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00O0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00O0O_data, + o => wire_n00O0O_o, + sel => wire_n00O0O_sel + ); + wire_n00O1i_data <= ( niliOi & niiOli & niliOi & nil1ll & niliOi & niiOli & niliOi & nil0lO & niliOi & niiOli & niliOi & nil1ll & niliOi & niiOli & niliOi & niliOi); + wire_n00O1i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00O1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00O1i_data, + o => wire_n00O1i_o, + sel => wire_n00O1i_sel + ); + wire_n00O1l_data <= ( niliOl & niiOll & niliOl & nil1lO & niliOl & niiOll & niliOl & nil0Oi & niliOl & niiOll & niliOl & nil1lO & niliOl & niiOll & niliOl & niliOl); + wire_n00O1l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00O1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00O1l_data, + o => wire_n00O1l_o, + sel => wire_n00O1l_sel + ); + wire_n00O1O_data <= ( niliOO & niiOlO & niliOO & nil1Oi & niliOO & niiOlO & niliOO & nil0Ol & niliOO & niiOlO & niliOO & nil1Oi & niliOO & niiOlO & niliOO & niliOO); + wire_n00O1O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00O1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00O1O_data, + o => wire_n00O1O_o, + sel => wire_n00O1O_sel + ); + wire_n00Oii_data <= ( nill0i & nil11i & nill0i & nil01l & nill0i & nil11i & nill0i & nili1O & nill0i & nil11i & nill0i & nil01l & nill0i & nil11i & nill0i & nill0i); + wire_n00Oii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00Oii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00Oii_data, + o => wire_n00Oii_o, + sel => wire_n00Oii_sel + ); + wire_n00Oil_data <= ( nill0l & nil11l & nill0l & nil01O & nill0l & nil11l & nill0l & nili0i & nill0l & nil11l & nill0l & nil01O & nill0l & nil11l & nill0l & nill0l); + wire_n00Oil_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00Oil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00Oil_data, + o => wire_n00Oil_o, + sel => wire_n00Oil_sel + ); + wire_n00OiO_data <= ( nill0O & nil11O & nill0O & nil00i & nill0O & nil11O & nill0O & nili0l & nill0O & nil11O & nill0O & nil00i & nill0O & nil11O & nill0O & nill0O); + wire_n00OiO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00OiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00OiO_data, + o => wire_n00OiO_o, + sel => wire_n00OiO_sel + ); + wire_n00Oli_data <= ( nillii & nil10i & nillii & nil00l & nillii & nil10i & nillii & nili0O & nillii & nil10i & nillii & nil00l & nillii & nil10i & nillii & nillii); + wire_n00Oli_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00Oli : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00Oli_data, + o => wire_n00Oli_o, + sel => wire_n00Oli_sel + ); + wire_n00Oll_data <= ( nillil & nil10l & nillil & nil00O & nillil & nil10l & nillil & niliii & nillil & nil10l & nillil & nil00O & nillil & nil10l & nillil & nillil); + wire_n00Oll_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00Oll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00Oll_data, + o => wire_n00Oll_o, + sel => wire_n00Oll_sel + ); + wire_n00OlO_data <= ( nilliO & nil10O & nilliO & nil0ii & nilliO & nil10O & nilliO & niliil & nilliO & nil10O & nilliO & nil0ii & nilliO & nil10O & nilliO & nilliO); + wire_n00OlO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00OlO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00OlO_data, + o => wire_n00OlO_o, + sel => wire_n00OlO_sel + ); + wire_n00OOi_data <= ( nillli & nil1ii & nillli & nil0il & nillli & nil1ii & nillli & niliiO & nillli & nil1ii & nillli & nil0il & nillli & nil1ii & nillli & nillli); + wire_n00OOi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00OOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00OOi_data, + o => wire_n00OOi_o, + sel => wire_n00OOi_sel + ); + wire_n00OOl_data <= ( nillll & nil1il & nillll & nil0iO & nillll & nil1il & nillll & nilili & nillll & nil1il & nillll & nil0iO & nillll & nil1il & nillll & nillll); + wire_n00OOl_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00OOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00OOl_data, + o => wire_n00OOl_o, + sel => wire_n00OOl_sel + ); + wire_n00OOO_data <= ( nilllO & nil1iO & nilllO & nil0li & nilllO & nil1iO & nilllO & nilill & nilllO & nil1iO & nilllO & nil0li & nilllO & nil1iO & nilllO & nilllO); + wire_n00OOO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n00OOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n00OOO_data, + o => wire_n00OOO_o, + sel => wire_n00OOO_sel + ); + wire_n0i00i_data <= ( niO11i & nil0Oi & niO11i & niliOl & niO11i & nil0Oi & niO11i & nillOO & niO11i & nil0Oi & niO11i & niliOl & niO11i & nil0Oi & niO11i & niO11i); + wire_n0i00i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i00i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i00i_data, + o => wire_n0i00i_o, + sel => wire_n0i00i_sel + ); + wire_n0i00l_data <= ( niO11l & nil0Ol & niO11l & niliOO & niO11l & nil0Ol & niO11l & nilO1i & niO11l & nil0Ol & niO11l & niliOO & niO11l & nil0Ol & niO11l & niO11l); + wire_n0i00l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i00l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i00l_data, + o => wire_n0i00l_o, + sel => wire_n0i00l_sel + ); + wire_n0i00O_data <= ( niO11O & nil0OO & niO11O & nill1i & niO11O & nil0OO & niO11O & nilO1l & niO11O & nil0OO & niO11O & nill1i & niO11O & nil0OO & niO11O & niO11O); + wire_n0i00O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i00O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i00O_data, + o => wire_n0i00O_o, + sel => wire_n0i00O_sel + ); + wire_n0i01i_data <= ( nilOOi & nil0li & nilOOi & nilill & nilOOi & nil0li & nilOOi & nilllO & nilOOi & nil0li & nilOOi & nilill & nilOOi & nil0li & nilOOi & nilOOi); + wire_n0i01i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i01i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i01i_data, + o => wire_n0i01i_o, + sel => wire_n0i01i_sel + ); + wire_n0i01l_data <= ( nilOOl & nil0ll & nilOOl & nililO & nilOOl & nil0ll & nilOOl & nillOi & nilOOl & nil0ll & nilOOl & nililO & nilOOl & nil0ll & nilOOl & nilOOl); + wire_n0i01l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i01l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i01l_data, + o => wire_n0i01l_o, + sel => wire_n0i01l_sel + ); + wire_n0i01O_data <= ( nilOOO & nil0lO & nilOOO & niliOi & nilOOO & nil0lO & nilOOO & nillOl & nilOOO & nil0lO & nilOOO & niliOi & nilOOO & nil0lO & nilOOO & nilOOO); + wire_n0i01O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i01O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i01O_data, + o => wire_n0i01O_o, + sel => wire_n0i01O_sel + ); + wire_n0i0ii_data <= ( niO10i & nili1i & niO10i & nill1l & niO10i & nili1i & niO10i & nilO1O & niO10i & nili1i & niO10i & nill1l & niO10i & nili1i & niO10i & niO10i); + wire_n0i0ii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0ii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0ii_data, + o => wire_n0i0ii_o, + sel => wire_n0i0ii_sel + ); + wire_n0i0il_data <= ( niO10l & nili1l & niO10l & nill1O & niO10l & nili1l & niO10l & nilO0i & niO10l & nili1l & niO10l & nill1O & niO10l & nili1l & niO10l & niO10l); + wire_n0i0il_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0il : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0il_data, + o => wire_n0i0il_o, + sel => wire_n0i0il_sel + ); + wire_n0i0iO_data <= ( niO10O & nili1O & niO10O & nill0i & niO10O & nili1O & niO10O & nilO0l & niO10O & nili1O & niO10O & nill0i & niO10O & nili1O & niO10O & niO10O); + wire_n0i0iO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0iO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0iO_data, + o => wire_n0i0iO_o, + sel => wire_n0i0iO_sel + ); + wire_n0i0li_data <= ( niO1ii & nili0i & niO1ii & nill0l & niO1ii & nili0i & niO1ii & nilO0O & niO1ii & nili0i & niO1ii & nill0l & niO1ii & nili0i & niO1ii & niO1ii); + wire_n0i0li_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0li : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0li_data, + o => wire_n0i0li_o, + sel => wire_n0i0li_sel + ); + wire_n0i0ll_data <= ( niO1il & nili0l & niO1il & nill0O & niO1il & nili0l & niO1il & nilOii & niO1il & nili0l & niO1il & nill0O & niO1il & nili0l & niO1il & niO1il); + wire_n0i0ll_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0ll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0ll_data, + o => wire_n0i0ll_o, + sel => wire_n0i0ll_sel + ); + wire_n0i0lO_data <= ( niO1iO & nili0O & niO1iO & nillii & niO1iO & nili0O & niO1iO & nilOil & niO1iO & nili0O & niO1iO & nillii & niO1iO & nili0O & niO1iO & niO1iO); + wire_n0i0lO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0lO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0lO_data, + o => wire_n0i0lO_o, + sel => wire_n0i0lO_sel + ); + wire_n0i0Oi_data <= ( niO1li & niliii & niO1li & nillil & niO1li & niliii & niO1li & nilOiO & niO1li & niliii & niO1li & nillil & niO1li & niliii & niO1li & niO1li); + wire_n0i0Oi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0Oi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0Oi_data, + o => wire_n0i0Oi_o, + sel => wire_n0i0Oi_sel + ); + wire_n0i0Ol_data <= ( niO1ll & niliil & niO1ll & nilliO & niO1ll & niliil & niO1ll & nilOli & niO1ll & niliil & niO1ll & nilliO & niO1ll & niliil & niO1ll & niO1ll); + wire_n0i0Ol_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0Ol : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0Ol_data, + o => wire_n0i0Ol_o, + sel => wire_n0i0Ol_sel + ); + wire_n0i0OO_data <= ( niO1lO & niliiO & niO1lO & nillli & niO1lO & niliiO & niO1lO & nilOll & niO1lO & niliiO & niO1lO & nillli & niO1lO & niliiO & niO1lO & niO1lO); + wire_n0i0OO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i0OO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i0OO_data, + o => wire_n0i0OO_o, + sel => wire_n0i0OO_sel + ); + wire_n0i10i_data <= ( nilO1i & nil1Oi & nilO1i & nil0Ol & nilO1i & nil1Oi & nilO1i & niliOO & nilO1i & nil1Oi & nilO1i & nil0Ol & nilO1i & nil1Oi & nilO1i & nilO1i); + wire_n0i10i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i10i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i10i_data, + o => wire_n0i10i_o, + sel => wire_n0i10i_sel + ); + wire_n0i10l_data <= ( nilO1l & nil1Ol & nilO1l & nil0OO & nilO1l & nil1Ol & nilO1l & nill1i & nilO1l & nil1Ol & nilO1l & nil0OO & nilO1l & nil1Ol & nilO1l & nilO1l); + wire_n0i10l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i10l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i10l_data, + o => wire_n0i10l_o, + sel => wire_n0i10l_sel + ); + wire_n0i10O_data <= ( nilO1O & nil1OO & nilO1O & nili1i & nilO1O & nil1OO & nilO1O & nill1l & nilO1O & nil1OO & nilO1O & nili1i & nilO1O & nil1OO & nilO1O & nilO1O); + wire_n0i10O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i10O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i10O_data, + o => wire_n0i10O_o, + sel => wire_n0i10O_sel + ); + wire_n0i11i_data <= ( nillOi & nil1li & nillOi & nil0ll & nillOi & nil1li & nillOi & nililO & nillOi & nil1li & nillOi & nil0ll & nillOi & nil1li & nillOi & nillOi); + wire_n0i11i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i11i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i11i_data, + o => wire_n0i11i_o, + sel => wire_n0i11i_sel + ); + wire_n0i11l_data <= ( nillOl & nil1ll & nillOl & nil0lO & nillOl & nil1ll & nillOl & niliOi & nillOl & nil1ll & nillOl & nil0lO & nillOl & nil1ll & nillOl & nillOl); + wire_n0i11l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i11l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i11l_data, + o => wire_n0i11l_o, + sel => wire_n0i11l_sel + ); + wire_n0i11O_data <= ( nillOO & nil1lO & nillOO & nil0Oi & nillOO & nil1lO & nillOO & niliOl & nillOO & nil1lO & nillOO & nil0Oi & nillOO & nil1lO & nillOO & nillOO); + wire_n0i11O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i11O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i11O_data, + o => wire_n0i11O_o, + sel => wire_n0i11O_sel + ); + wire_n0i1ii_data <= ( nilO0i & nil01i & nilO0i & nili1l & nilO0i & nil01i & nilO0i & nill1O & nilO0i & nil01i & nilO0i & nili1l & nilO0i & nil01i & nilO0i & nilO0i); + wire_n0i1ii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1ii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1ii_data, + o => wire_n0i1ii_o, + sel => wire_n0i1ii_sel + ); + wire_n0i1il_data <= ( nilO0l & nil01l & nilO0l & nili1O & nilO0l & nil01l & nilO0l & nill0i & nilO0l & nil01l & nilO0l & nili1O & nilO0l & nil01l & nilO0l & nilO0l); + wire_n0i1il_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1il : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1il_data, + o => wire_n0i1il_o, + sel => wire_n0i1il_sel + ); + wire_n0i1iO_data <= ( nilO0O & nil01O & nilO0O & nili0i & nilO0O & nil01O & nilO0O & nill0l & nilO0O & nil01O & nilO0O & nili0i & nilO0O & nil01O & nilO0O & nilO0O); + wire_n0i1iO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1iO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1iO_data, + o => wire_n0i1iO_o, + sel => wire_n0i1iO_sel + ); + wire_n0i1li_data <= ( nilOii & nil00i & nilOii & nili0l & nilOii & nil00i & nilOii & nill0O & nilOii & nil00i & nilOii & nili0l & nilOii & nil00i & nilOii & nilOii); + wire_n0i1li_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1li : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1li_data, + o => wire_n0i1li_o, + sel => wire_n0i1li_sel + ); + wire_n0i1ll_data <= ( nilOil & nil00l & nilOil & nili0O & nilOil & nil00l & nilOil & nillii & nilOil & nil00l & nilOil & nili0O & nilOil & nil00l & nilOil & nilOil); + wire_n0i1ll_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1ll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1ll_data, + o => wire_n0i1ll_o, + sel => wire_n0i1ll_sel + ); + wire_n0i1lO_data <= ( nilOiO & nil00O & nilOiO & niliii & nilOiO & nil00O & nilOiO & nillil & nilOiO & nil00O & nilOiO & niliii & nilOiO & nil00O & nilOiO & nilOiO); + wire_n0i1lO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1lO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1lO_data, + o => wire_n0i1lO_o, + sel => wire_n0i1lO_sel + ); + wire_n0i1Oi_data <= ( nilOli & nil0ii & nilOli & niliil & nilOli & nil0ii & nilOli & nilliO & nilOli & nil0ii & nilOli & niliil & nilOli & nil0ii & nilOli & nilOli); + wire_n0i1Oi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1Oi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1Oi_data, + o => wire_n0i1Oi_o, + sel => wire_n0i1Oi_sel + ); + wire_n0i1Ol_data <= ( nilOll & nil0il & nilOll & niliiO & nilOll & nil0il & nilOll & nillli & nilOll & nil0il & nilOll & niliiO & nilOll & nil0il & nilOll & nilOll); + wire_n0i1Ol_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1Ol : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1Ol_data, + o => wire_n0i1Ol_o, + sel => wire_n0i1Ol_sel + ); + wire_n0i1OO_data <= ( nilOlO & nil0iO & nilOlO & nilili & nilOlO & nil0iO & nilOlO & nillll & nilOlO & nil0iO & nilOlO & nilili & nilOlO & nil0iO & nilOlO & nilOlO); + wire_n0i1OO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0i1OO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0i1OO_data, + o => wire_n0i1OO_o, + sel => wire_n0i1OO_sel + ); + wire_n0ii0i_data <= ( niO01i & niliOi & niO01i & nillOl & niO01i & niliOi & niO01i & nilOOO & niO01i & niliOi & niO01i & nillOl & niO01i & niliOi & niO01i & niO01i); + wire_n0ii0i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0ii0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0ii0i_data, + o => wire_n0ii0i_o, + sel => wire_n0ii0i_sel + ); + wire_n0ii0l_data <= ( niO01l & niliOl & niO01l & nillOO & niO01l & niliOl & niO01l & niO11i & niO01l & niliOl & niO01l & nillOO & niO01l & niliOl & niO01l & niO01l); + wire_n0ii0l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0ii0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0ii0l_data, + o => wire_n0ii0l_o, + sel => wire_n0ii0l_sel + ); + wire_n0ii0O_data <= ( niO01O & niliOO & niO01O & nilO1i & niO01O & niliOO & niO01O & niO11l & niO01O & niliOO & niO01O & nilO1i & niO01O & niliOO & niO01O & niO01O); + wire_n0ii0O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0ii0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0ii0O_data, + o => wire_n0ii0O_o, + sel => wire_n0ii0O_sel + ); + wire_n0ii1i_data <= ( niO1Oi & nilili & niO1Oi & nillll & niO1Oi & nilili & niO1Oi & nilOlO & niO1Oi & nilili & niO1Oi & nillll & niO1Oi & nilili & niO1Oi & niO1Oi); + wire_n0ii1i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0ii1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0ii1i_data, + o => wire_n0ii1i_o, + sel => wire_n0ii1i_sel + ); + wire_n0ii1l_data <= ( niO1Ol & nilill & niO1Ol & nilllO & niO1Ol & nilill & niO1Ol & nilOOi & niO1Ol & nilill & niO1Ol & nilllO & niO1Ol & nilill & niO1Ol & niO1Ol); + wire_n0ii1l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0ii1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0ii1l_data, + o => wire_n0ii1l_o, + sel => wire_n0ii1l_sel + ); + wire_n0ii1O_data <= ( niO1OO & nililO & niO1OO & nillOi & niO1OO & nililO & niO1OO & nilOOl & niO1OO & nililO & niO1OO & nillOi & niO1OO & nililO & niO1OO & niO1OO); + wire_n0ii1O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0ii1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0ii1O_data, + o => wire_n0ii1O_o, + sel => wire_n0ii1O_sel + ); + wire_n0iiii_data <= ( niO00i & nill1i & niO00i & nilO1l & niO00i & nill1i & niO00i & niO11O & niO00i & nill1i & niO00i & nilO1l & niO00i & nill1i & niO00i & niO00i); + wire_n0iiii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iiii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iiii_data, + o => wire_n0iiii_o, + sel => wire_n0iiii_sel + ); + wire_n0iiil_data <= ( niO00l & nill1l & niO00l & nilO1O & niO00l & nill1l & niO00l & niO10i & niO00l & nill1l & niO00l & nilO1O & niO00l & nill1l & niO00l & niO00l); + wire_n0iiil_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iiil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iiil_data, + o => wire_n0iiil_o, + sel => wire_n0iiil_sel + ); + wire_n0iiiO_data <= ( niO00O & nill1O & niO00O & nilO0i & niO00O & nill1O & niO00O & niO10l & niO00O & nill1O & niO00O & nilO0i & niO00O & nill1O & niO00O & niO00O); + wire_n0iiiO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iiiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iiiO_data, + o => wire_n0iiiO_o, + sel => wire_n0iiiO_sel + ); + wire_n0iili_data <= ( niO0ii & nill0i & niO0ii & nilO0l & niO0ii & nill0i & niO0ii & niO10O & niO0ii & nill0i & niO0ii & nilO0l & niO0ii & nill0i & niO0ii & niO0ii); + wire_n0iili_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iili : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iili_data, + o => wire_n0iili_o, + sel => wire_n0iili_sel + ); + wire_n0iill_data <= ( niO0il & nill0l & niO0il & nilO0O & niO0il & nill0l & niO0il & niO1ii & niO0il & nill0l & niO0il & nilO0O & niO0il & nill0l & niO0il & niO0il); + wire_n0iill_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iill : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iill_data, + o => wire_n0iill_o, + sel => wire_n0iill_sel + ); + wire_n0iilO_data <= ( niO0iO & nill0O & niO0iO & nilOii & niO0iO & nill0O & niO0iO & niO1il & niO0iO & nill0O & niO0iO & nilOii & niO0iO & nill0O & niO0iO & niO0iO); + wire_n0iilO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iilO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iilO_data, + o => wire_n0iilO_o, + sel => wire_n0iilO_sel + ); + wire_n0iiOi_data <= ( niO0li & nillii & niO0li & nilOil & niO0li & nillii & niO0li & niO1iO & niO0li & nillii & niO0li & nilOil & niO0li & nillii & niO0li & niO0li); + wire_n0iiOi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iiOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iiOi_data, + o => wire_n0iiOi_o, + sel => wire_n0iiOi_sel + ); + wire_n0iiOl_data <= ( niO0ll & nillil & niO0ll & nilOiO & niO0ll & nillil & niO0ll & niO1li & niO0ll & nillil & niO0ll & nilOiO & niO0ll & nillil & niO0ll & niO0ll); + wire_n0iiOl_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iiOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iiOl_data, + o => wire_n0iiOl_o, + sel => wire_n0iiOl_sel + ); + wire_n0iiOO_data <= ( niO0lO & nilliO & niO0lO & nilOli & niO0lO & nilliO & niO0lO & niO1ll & niO0lO & nilliO & niO0lO & nilOli & niO0lO & nilliO & niO0lO & niO0lO); + wire_n0iiOO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0iiOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0iiOO_data, + o => wire_n0iiOO_o, + sel => wire_n0iiOO_sel + ); + wire_n0il0i_data <= ( niOi1i & nillOi & niOi1i & nilOOl & niOi1i & nillOi & niOi1i & niO1OO & niOi1i & nillOi & niOi1i & nilOOl & niOi1i & nillOi & niOi1i & niOi1i); + wire_n0il0i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0il0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0il0i_data, + o => wire_n0il0i_o, + sel => wire_n0il0i_sel + ); + wire_n0il1i_data <= ( niO0Oi & nillli & niO0Oi & nilOll & niO0Oi & nillli & niO0Oi & niO1lO & niO0Oi & nillli & niO0Oi & nilOll & niO0Oi & nillli & niO0Oi & niO0Oi); + wire_n0il1i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0il1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0il1i_data, + o => wire_n0il1i_o, + sel => wire_n0il1i_sel + ); + wire_n0il1l_data <= ( niO0Ol & nillll & niO0Ol & nilOlO & niO0Ol & nillll & niO0Ol & niO1Oi & niO0Ol & nillll & niO0Ol & nilOlO & niO0Ol & nillll & niO0Ol & niO0Ol); + wire_n0il1l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0il1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0il1l_data, + o => wire_n0il1l_o, + sel => wire_n0il1l_sel + ); + wire_n0il1O_data <= ( niO0OO & nilllO & niO0OO & nilOOi & niO0OO & nilllO & niO0OO & niO1Ol & niO0OO & nilllO & niO0OO & nilOOi & niO0OO & nilllO & niO0OO & niO0OO); + wire_n0il1O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0il1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0il1O_data, + o => wire_n0il1O_o, + sel => wire_n0il1O_sel + ); + wire_n0l00l_data <= ( niO0ll & nillil & niO0ll & nilOiO & niO0ll & nillil & niO0ll & niO1li & niO0ll & nillil & niO0ll & nilOiO & niO0ll & nillil & niO0ll & niO0ll); + wire_n0l00l_sel <= ( wire_ni1llO_dataout & wire_ni1lll_dataout & wire_ni1lli_dataout & wire_ni1liO_dataout); + n0l00l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0l00l_data, + o => wire_n0l00l_o, + sel => wire_n0l00l_sel + ); + wire_n0l11l_data <= ( niO1li & nillil & niO1li & nilOiO & niO1li & nillil & niO1li & niO1li); + wire_n0l11l_sel <= ( wire_ni1lll_dataout & wire_ni1lli_dataout & wire_ni1liO_dataout); + n0l11l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0l11l_data, + o => wire_n0l11l_o, + sel => wire_n0l11l_sel + ); + wire_n0O00i_data <= ( wire_niOO1i_dataout & nilO1i & wire_niOO1i_dataout & niO11l & wire_niOO1i_dataout & nilO1i & wire_niOO1i_dataout & niO01O & wire_niOO1i_dataout & nilO1i & wire_niOO1i_dataout & niO11l & wire_niOO1i_dataout & nilO1i & wire_niOO1i_dataout & wire_niOO1i_dataout); + wire_n0O00i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O00i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O00i_data, + o => wire_n0O00i_o, + sel => wire_n0O00i_sel + ); + wire_n0O00l_data <= ( wire_niOO1l_dataout & nilO1l & wire_niOO1l_dataout & niO11O & wire_niOO1l_dataout & nilO1l & wire_niOO1l_dataout & niO00i & wire_niOO1l_dataout & nilO1l & wire_niOO1l_dataout & niO11O & wire_niOO1l_dataout & nilO1l & wire_niOO1l_dataout & wire_niOO1l_dataout); + wire_n0O00l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O00l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O00l_data, + o => wire_n0O00l_o, + sel => wire_n0O00l_sel + ); + wire_n0O00O_data <= ( wire_niOO1O_dataout & nilO1O & wire_niOO1O_dataout & niO10i & wire_niOO1O_dataout & nilO1O & wire_niOO1O_dataout & niO00l & wire_niOO1O_dataout & nilO1O & wire_niOO1O_dataout & niO10i & wire_niOO1O_dataout & nilO1O & wire_niOO1O_dataout & wire_niOO1O_dataout); + wire_n0O00O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O00O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O00O_data, + o => wire_n0O00O_o, + sel => wire_n0O00O_sel + ); + wire_n0O01l_data <= ( wire_niOlOl_dataout & nillOl & wire_niOlOl_dataout & nilOOO & wire_niOlOl_dataout & nillOl & wire_niOlOl_dataout & niO01i & wire_niOlOl_dataout & nillOl & wire_niOlOl_dataout & nilOOO & wire_niOlOl_dataout & nillOl & wire_niOlOl_dataout & wire_niOlOl_dataout); + wire_n0O01l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O01l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O01l_data, + o => wire_n0O01l_o, + sel => wire_n0O01l_sel + ); + wire_n0O01O_data <= ( wire_niOlOO_dataout & nillOO & wire_niOlOO_dataout & niO11i & wire_niOlOO_dataout & nillOO & wire_niOlOO_dataout & niO01l & wire_niOlOO_dataout & nillOO & wire_niOlOO_dataout & niO11i & wire_niOlOO_dataout & nillOO & wire_niOlOO_dataout & wire_niOlOO_dataout); + wire_n0O01O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O01O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O01O_data, + o => wire_n0O01O_o, + sel => wire_n0O01O_sel + ); + wire_n0O0ii_data <= ( wire_niOO0i_dataout & nilO0i & wire_niOO0i_dataout & niO10l & wire_niOO0i_dataout & nilO0i & wire_niOO0i_dataout & niO00O & wire_niOO0i_dataout & nilO0i & wire_niOO0i_dataout & niO10l & wire_niOO0i_dataout & nilO0i & wire_niOO0i_dataout & wire_niOO0i_dataout); + wire_n0O0ii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0ii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0ii_data, + o => wire_n0O0ii_o, + sel => wire_n0O0ii_sel + ); + wire_n0O0il_data <= ( wire_niOO0l_dataout & nilO0l & wire_niOO0l_dataout & niO10O & wire_niOO0l_dataout & nilO0l & wire_niOO0l_dataout & niO0ii & wire_niOO0l_dataout & nilO0l & wire_niOO0l_dataout & niO10O & wire_niOO0l_dataout & nilO0l & wire_niOO0l_dataout & wire_niOO0l_dataout); + wire_n0O0il_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0il : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0il_data, + o => wire_n0O0il_o, + sel => wire_n0O0il_sel + ); + wire_n0O0iO_data <= ( wire_niOO0O_dataout & nilO0O & wire_niOO0O_dataout & niO1ii & wire_niOO0O_dataout & nilO0O & wire_niOO0O_dataout & niO0il & wire_niOO0O_dataout & nilO0O & wire_niOO0O_dataout & niO1ii & wire_niOO0O_dataout & nilO0O & wire_niOO0O_dataout & wire_niOO0O_dataout); + wire_n0O0iO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0iO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0iO_data, + o => wire_n0O0iO_o, + sel => wire_n0O0iO_sel + ); + wire_n0O0li_data <= ( wire_niOOii_dataout & nilOii & wire_niOOii_dataout & niO1il & wire_niOOii_dataout & nilOii & wire_niOOii_dataout & niO0iO & wire_niOOii_dataout & nilOii & wire_niOOii_dataout & niO1il & wire_niOOii_dataout & nilOii & wire_niOOii_dataout & wire_niOOii_dataout); + wire_n0O0li_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0li : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0li_data, + o => wire_n0O0li_o, + sel => wire_n0O0li_sel + ); + wire_n0O0ll_data <= ( wire_niOOil_dataout & nilOil & wire_niOOil_dataout & niO1iO & wire_niOOil_dataout & nilOil & wire_niOOil_dataout & niO0li & wire_niOOil_dataout & nilOil & wire_niOOil_dataout & niO1iO & wire_niOOil_dataout & nilOil & wire_niOOil_dataout & wire_niOOil_dataout); + wire_n0O0ll_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0ll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0ll_data, + o => wire_n0O0ll_o, + sel => wire_n0O0ll_sel + ); + wire_n0O0lO_data <= ( wire_niOOiO_dataout & nilOiO & wire_niOOiO_dataout & niO1li & wire_niOOiO_dataout & nilOiO & wire_niOOiO_dataout & niO0ll & wire_niOOiO_dataout & nilOiO & wire_niOOiO_dataout & niO1li & wire_niOOiO_dataout & nilOiO & wire_niOOiO_dataout & wire_niOOiO_dataout); + wire_n0O0lO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0lO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0lO_data, + o => wire_n0O0lO_o, + sel => wire_n0O0lO_sel + ); + wire_n0O0Oi_data <= ( wire_niOOli_dataout & nilOli & wire_niOOli_dataout & niO1ll & wire_niOOli_dataout & nilOli & wire_niOOli_dataout & niO0lO & wire_niOOli_dataout & nilOli & wire_niOOli_dataout & niO1ll & wire_niOOli_dataout & nilOli & wire_niOOli_dataout & wire_niOOli_dataout); + wire_n0O0Oi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0Oi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0Oi_data, + o => wire_n0O0Oi_o, + sel => wire_n0O0Oi_sel + ); + wire_n0O0Ol_data <= ( wire_niOOll_dataout & nilOll & wire_niOOll_dataout & niO1lO & wire_niOOll_dataout & nilOll & wire_niOOll_dataout & niO0Oi & wire_niOOll_dataout & nilOll & wire_niOOll_dataout & niO1lO & wire_niOOll_dataout & nilOll & wire_niOOll_dataout & wire_niOOll_dataout); + wire_n0O0Ol_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0Ol : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0Ol_data, + o => wire_n0O0Ol_o, + sel => wire_n0O0Ol_sel + ); + wire_n0O0OO_data <= ( wire_niOOlO_dataout & nilOlO & wire_niOOlO_dataout & niO1Oi & wire_niOOlO_dataout & nilOlO & wire_niOOlO_dataout & niO0Ol & wire_niOOlO_dataout & nilOlO & wire_niOOlO_dataout & niO1Oi & wire_niOOlO_dataout & nilOlO & wire_niOOlO_dataout & wire_niOOlO_dataout); + wire_n0O0OO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0O0OO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0O0OO_data, + o => wire_n0O0OO_o, + sel => wire_n0O0OO_sel + ); + wire_n0Oi0i_data <= ( wire_nl111i_dataout & niO11i & wire_nl111i_dataout & niO01l & wire_nl111i_dataout & niO11i & wire_nl111i_dataout & wire_niOlOO_dataout & wire_nl111i_dataout & niO11i & wire_nl111i_dataout & niO01l & wire_nl111i_dataout & niO11i & wire_nl111i_dataout & wire_nl111i_dataout); + wire_n0Oi0i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oi0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oi0i_data, + o => wire_n0Oi0i_o, + sel => wire_n0Oi0i_sel + ); + wire_n0Oi0l_data <= ( wire_nl111l_dataout & niO11l & wire_nl111l_dataout & niO01O & wire_nl111l_dataout & niO11l & wire_nl111l_dataout & wire_niOO1i_dataout & wire_nl111l_dataout & niO11l & wire_nl111l_dataout & niO01O & wire_nl111l_dataout & niO11l & wire_nl111l_dataout & wire_nl111l_dataout); + wire_n0Oi0l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oi0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oi0l_data, + o => wire_n0Oi0l_o, + sel => wire_n0Oi0l_sel + ); + wire_n0Oi0O_data <= ( wire_nl111O_dataout & niO11O & wire_nl111O_dataout & niO00i & wire_nl111O_dataout & niO11O & wire_nl111O_dataout & wire_niOO1l_dataout & wire_nl111O_dataout & niO11O & wire_nl111O_dataout & niO00i & wire_nl111O_dataout & niO11O & wire_nl111O_dataout & wire_nl111O_dataout); + wire_n0Oi0O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oi0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oi0O_data, + o => wire_n0Oi0O_o, + sel => wire_n0Oi0O_sel + ); + wire_n0Oi1i_data <= ( wire_niOOOi_dataout & nilOOi & wire_niOOOi_dataout & niO1Ol & wire_niOOOi_dataout & nilOOi & wire_niOOOi_dataout & niO0OO & wire_niOOOi_dataout & nilOOi & wire_niOOOi_dataout & niO1Ol & wire_niOOOi_dataout & nilOOi & wire_niOOOi_dataout & wire_niOOOi_dataout); + wire_n0Oi1i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oi1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oi1i_data, + o => wire_n0Oi1i_o, + sel => wire_n0Oi1i_sel + ); + wire_n0Oi1l_data <= ( wire_niOOOl_dataout & nilOOl & wire_niOOOl_dataout & niO1OO & wire_niOOOl_dataout & nilOOl & wire_niOOOl_dataout & niOi1i & wire_niOOOl_dataout & nilOOl & wire_niOOOl_dataout & niO1OO & wire_niOOOl_dataout & nilOOl & wire_niOOOl_dataout & wire_niOOOl_dataout); + wire_n0Oi1l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oi1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oi1l_data, + o => wire_n0Oi1l_o, + sel => wire_n0Oi1l_sel + ); + wire_n0Oi1O_data <= ( wire_niOOOO_dataout & nilOOO & wire_niOOOO_dataout & niO01i & wire_niOOOO_dataout & nilOOO & wire_niOOOO_dataout & wire_niOlOl_dataout & wire_niOOOO_dataout & nilOOO & wire_niOOOO_dataout & niO01i & wire_niOOOO_dataout & nilOOO & wire_niOOOO_dataout & wire_niOOOO_dataout); + wire_n0Oi1O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oi1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oi1O_data, + o => wire_n0Oi1O_o, + sel => wire_n0Oi1O_sel + ); + wire_n0Oiii_data <= ( wire_nl110i_dataout & niO10i & wire_nl110i_dataout & niO00l & wire_nl110i_dataout & niO10i & wire_nl110i_dataout & wire_niOO1O_dataout & wire_nl110i_dataout & niO10i & wire_nl110i_dataout & niO00l & wire_nl110i_dataout & niO10i & wire_nl110i_dataout & wire_nl110i_dataout); + wire_n0Oiii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oiii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oiii_data, + o => wire_n0Oiii_o, + sel => wire_n0Oiii_sel + ); + wire_n0Oiil_data <= ( wire_nl110l_dataout & niO10l & wire_nl110l_dataout & niO00O & wire_nl110l_dataout & niO10l & wire_nl110l_dataout & wire_niOO0i_dataout & wire_nl110l_dataout & niO10l & wire_nl110l_dataout & niO00O & wire_nl110l_dataout & niO10l & wire_nl110l_dataout & wire_nl110l_dataout); + wire_n0Oiil_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oiil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oiil_data, + o => wire_n0Oiil_o, + sel => wire_n0Oiil_sel + ); + wire_n0OiiO_data <= ( wire_nl110O_dataout & niO10O & wire_nl110O_dataout & niO0ii & wire_nl110O_dataout & niO10O & wire_nl110O_dataout & wire_niOO0l_dataout & wire_nl110O_dataout & niO10O & wire_nl110O_dataout & niO0ii & wire_nl110O_dataout & niO10O & wire_nl110O_dataout & wire_nl110O_dataout); + wire_n0OiiO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OiiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OiiO_data, + o => wire_n0OiiO_o, + sel => wire_n0OiiO_sel + ); + wire_n0Oili_data <= ( wire_nl11ii_dataout & niO1ii & wire_nl11ii_dataout & niO0il & wire_nl11ii_dataout & niO1ii & wire_nl11ii_dataout & wire_niOO0O_dataout & wire_nl11ii_dataout & niO1ii & wire_nl11ii_dataout & niO0il & wire_nl11ii_dataout & niO1ii & wire_nl11ii_dataout & wire_nl11ii_dataout); + wire_n0Oili_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oili : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oili_data, + o => wire_n0Oili_o, + sel => wire_n0Oili_sel + ); + wire_n0Oill_data <= ( wire_nl11il_dataout & niO1il & wire_nl11il_dataout & niO0iO & wire_nl11il_dataout & niO1il & wire_nl11il_dataout & wire_niOOii_dataout & wire_nl11il_dataout & niO1il & wire_nl11il_dataout & niO0iO & wire_nl11il_dataout & niO1il & wire_nl11il_dataout & wire_nl11il_dataout); + wire_n0Oill_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Oill : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oill_data, + o => wire_n0Oill_o, + sel => wire_n0Oill_sel + ); + wire_n0OilO_data <= ( wire_nl11iO_dataout & niO1iO & wire_nl11iO_dataout & niO0li & wire_nl11iO_dataout & niO1iO & wire_nl11iO_dataout & wire_niOOil_dataout & wire_nl11iO_dataout & niO1iO & wire_nl11iO_dataout & niO0li & wire_nl11iO_dataout & niO1iO & wire_nl11iO_dataout & wire_nl11iO_dataout); + wire_n0OilO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OilO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OilO_data, + o => wire_n0OilO_o, + sel => wire_n0OilO_sel + ); + wire_n0OiOi_data <= ( wire_nl11li_dataout & niO1li & wire_nl11li_dataout & niO0ll & wire_nl11li_dataout & niO1li & wire_nl11li_dataout & wire_niOOiO_dataout & wire_nl11li_dataout & niO1li & wire_nl11li_dataout & niO0ll & wire_nl11li_dataout & niO1li & wire_nl11li_dataout & wire_nl11li_dataout); + wire_n0OiOi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OiOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OiOi_data, + o => wire_n0OiOi_o, + sel => wire_n0OiOi_sel + ); + wire_n0OiOl_data <= ( wire_nl11ll_dataout & niO1ll & wire_nl11ll_dataout & niO0lO & wire_nl11ll_dataout & niO1ll & wire_nl11ll_dataout & wire_niOOli_dataout & wire_nl11ll_dataout & niO1ll & wire_nl11ll_dataout & niO0lO & wire_nl11ll_dataout & niO1ll & wire_nl11ll_dataout & wire_nl11ll_dataout); + wire_n0OiOl_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OiOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OiOl_data, + o => wire_n0OiOl_o, + sel => wire_n0OiOl_sel + ); + wire_n0OiOO_data <= ( wire_nl11lO_dataout & niO1lO & wire_nl11lO_dataout & niO0Oi & wire_nl11lO_dataout & niO1lO & wire_nl11lO_dataout & wire_niOOll_dataout & wire_nl11lO_dataout & niO1lO & wire_nl11lO_dataout & niO0Oi & wire_nl11lO_dataout & niO1lO & wire_nl11lO_dataout & wire_nl11lO_dataout); + wire_n0OiOO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OiOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OiOO_data, + o => wire_n0OiOO_o, + sel => wire_n0OiOO_sel + ); + wire_n0Ol0i_data <= ( wire_nl101i_dataout & niO01i & wire_nl101i_dataout & wire_niOlOl_dataout & wire_nl101i_dataout & niO01i & wire_nl101i_dataout & wire_niOOOO_dataout & wire_nl101i_dataout & niO01i & wire_nl101i_dataout & wire_niOlOl_dataout & wire_nl101i_dataout & niO01i & wire_nl101i_dataout & wire_nl101i_dataout); + wire_n0Ol0i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Ol0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Ol0i_data, + o => wire_n0Ol0i_o, + sel => wire_n0Ol0i_sel + ); + wire_n0Ol0l_data <= ( wire_nl101l_dataout & niO01l & wire_nl101l_dataout & wire_niOlOO_dataout & wire_nl101l_dataout & niO01l & wire_nl101l_dataout & wire_nl111i_dataout & wire_nl101l_dataout & niO01l & wire_nl101l_dataout & wire_niOlOO_dataout & wire_nl101l_dataout & niO01l & wire_nl101l_dataout & wire_nl101l_dataout); + wire_n0Ol0l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Ol0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Ol0l_data, + o => wire_n0Ol0l_o, + sel => wire_n0Ol0l_sel + ); + wire_n0Ol0O_data <= ( wire_nl101O_dataout & niO01O & wire_nl101O_dataout & wire_niOO1i_dataout & wire_nl101O_dataout & niO01O & wire_nl101O_dataout & wire_nl111l_dataout & wire_nl101O_dataout & niO01O & wire_nl101O_dataout & wire_niOO1i_dataout & wire_nl101O_dataout & niO01O & wire_nl101O_dataout & wire_nl101O_dataout); + wire_n0Ol0O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Ol0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Ol0O_data, + o => wire_n0Ol0O_o, + sel => wire_n0Ol0O_sel + ); + wire_n0Ol1i_data <= ( wire_nl11Oi_dataout & niO1Oi & wire_nl11Oi_dataout & niO0Ol & wire_nl11Oi_dataout & niO1Oi & wire_nl11Oi_dataout & wire_niOOlO_dataout & wire_nl11Oi_dataout & niO1Oi & wire_nl11Oi_dataout & niO0Ol & wire_nl11Oi_dataout & niO1Oi & wire_nl11Oi_dataout & wire_nl11Oi_dataout); + wire_n0Ol1i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Ol1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Ol1i_data, + o => wire_n0Ol1i_o, + sel => wire_n0Ol1i_sel + ); + wire_n0Ol1l_data <= ( wire_nl11Ol_dataout & niO1Ol & wire_nl11Ol_dataout & niO0OO & wire_nl11Ol_dataout & niO1Ol & wire_nl11Ol_dataout & wire_niOOOi_dataout & wire_nl11Ol_dataout & niO1Ol & wire_nl11Ol_dataout & niO0OO & wire_nl11Ol_dataout & niO1Ol & wire_nl11Ol_dataout & wire_nl11Ol_dataout); + wire_n0Ol1l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Ol1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Ol1l_data, + o => wire_n0Ol1l_o, + sel => wire_n0Ol1l_sel + ); + wire_n0Ol1O_data <= ( wire_nl11OO_dataout & niO1OO & wire_nl11OO_dataout & niOi1i & wire_nl11OO_dataout & niO1OO & wire_nl11OO_dataout & wire_niOOOl_dataout & wire_nl11OO_dataout & niO1OO & wire_nl11OO_dataout & niOi1i & wire_nl11OO_dataout & niO1OO & wire_nl11OO_dataout & wire_nl11OO_dataout); + wire_n0Ol1O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Ol1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Ol1O_data, + o => wire_n0Ol1O_o, + sel => wire_n0Ol1O_sel + ); + wire_n0Olii_data <= ( wire_nl100i_dataout & niO00i & wire_nl100i_dataout & wire_niOO1l_dataout & wire_nl100i_dataout & niO00i & wire_nl100i_dataout & wire_nl111O_dataout & wire_nl100i_dataout & niO00i & wire_nl100i_dataout & wire_niOO1l_dataout & wire_nl100i_dataout & niO00i & wire_nl100i_dataout & wire_nl100i_dataout); + wire_n0Olii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Olii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Olii_data, + o => wire_n0Olii_o, + sel => wire_n0Olii_sel + ); + wire_n0Olil_data <= ( wire_nl100l_dataout & niO00l & wire_nl100l_dataout & wire_niOO1O_dataout & wire_nl100l_dataout & niO00l & wire_nl100l_dataout & wire_nl110i_dataout & wire_nl100l_dataout & niO00l & wire_nl100l_dataout & wire_niOO1O_dataout & wire_nl100l_dataout & niO00l & wire_nl100l_dataout & wire_nl100l_dataout); + wire_n0Olil_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Olil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Olil_data, + o => wire_n0Olil_o, + sel => wire_n0Olil_sel + ); + wire_n0OliO_data <= ( wire_nl100O_dataout & niO00O & wire_nl100O_dataout & wire_niOO0i_dataout & wire_nl100O_dataout & niO00O & wire_nl100O_dataout & wire_nl110l_dataout & wire_nl100O_dataout & niO00O & wire_nl100O_dataout & wire_niOO0i_dataout & wire_nl100O_dataout & niO00O & wire_nl100O_dataout & wire_nl100O_dataout); + wire_n0OliO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OliO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OliO_data, + o => wire_n0OliO_o, + sel => wire_n0OliO_sel + ); + wire_n0Olli_data <= ( wire_nl10ii_dataout & niO0ii & wire_nl10ii_dataout & wire_niOO0l_dataout & wire_nl10ii_dataout & niO0ii & wire_nl10ii_dataout & wire_nl110O_dataout & wire_nl10ii_dataout & niO0ii & wire_nl10ii_dataout & wire_niOO0l_dataout & wire_nl10ii_dataout & niO0ii & wire_nl10ii_dataout & wire_nl10ii_dataout); + wire_n0Olli_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Olli : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Olli_data, + o => wire_n0Olli_o, + sel => wire_n0Olli_sel + ); + wire_n0Olll_data <= ( wire_nl10il_dataout & niO0il & wire_nl10il_dataout & wire_niOO0O_dataout & wire_nl10il_dataout & niO0il & wire_nl10il_dataout & wire_nl11ii_dataout & wire_nl10il_dataout & niO0il & wire_nl10il_dataout & wire_niOO0O_dataout & wire_nl10il_dataout & niO0il & wire_nl10il_dataout & wire_nl10il_dataout); + wire_n0Olll_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0Olll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Olll_data, + o => wire_n0Olll_o, + sel => wire_n0Olll_sel + ); + wire_n0OllO_data <= ( wire_nl10iO_dataout & niO0iO & wire_nl10iO_dataout & wire_niOOii_dataout & wire_nl10iO_dataout & niO0iO & wire_nl10iO_dataout & wire_nl11il_dataout & wire_nl10iO_dataout & niO0iO & wire_nl10iO_dataout & wire_niOOii_dataout & wire_nl10iO_dataout & niO0iO & wire_nl10iO_dataout & wire_nl10iO_dataout); + wire_n0OllO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OllO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OllO_data, + o => wire_n0OllO_o, + sel => wire_n0OllO_sel + ); + wire_n0OlOi_data <= ( wire_nl10li_dataout & niO0li & wire_nl10li_dataout & wire_niOOil_dataout & wire_nl10li_dataout & niO0li & wire_nl10li_dataout & wire_nl11iO_dataout & wire_nl10li_dataout & niO0li & wire_nl10li_dataout & wire_niOOil_dataout & wire_nl10li_dataout & niO0li & wire_nl10li_dataout & wire_nl10li_dataout); + wire_n0OlOi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OlOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OlOi_data, + o => wire_n0OlOi_o, + sel => wire_n0OlOi_sel + ); + wire_n0OlOl_data <= ( wire_nl10ll_dataout & niO0ll & wire_nl10ll_dataout & wire_niOOiO_dataout & wire_nl10ll_dataout & niO0ll & wire_nl10ll_dataout & wire_nl11li_dataout & wire_nl10ll_dataout & niO0ll & wire_nl10ll_dataout & wire_niOOiO_dataout & wire_nl10ll_dataout & niO0ll & wire_nl10ll_dataout & wire_nl10ll_dataout); + wire_n0OlOl_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OlOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OlOl_data, + o => wire_n0OlOl_o, + sel => wire_n0OlOl_sel + ); + wire_n0OlOO_data <= ( wire_nl10lO_dataout & niO0lO & wire_nl10lO_dataout & wire_niOOli_dataout & wire_nl10lO_dataout & niO0lO & wire_nl10lO_dataout & wire_nl11ll_dataout & wire_nl10lO_dataout & niO0lO & wire_nl10lO_dataout & wire_niOOli_dataout & wire_nl10lO_dataout & niO0lO & wire_nl10lO_dataout & wire_nl10lO_dataout); + wire_n0OlOO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OlOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OlOO_data, + o => wire_n0OlOO_o, + sel => wire_n0OlOO_sel + ); + wire_n0OO0i_data <= ( wire_nl1i1i_dataout & niOi1i & wire_nl1i1i_dataout & wire_niOOOl_dataout & wire_nl1i1i_dataout & niOi1i & wire_nl1i1i_dataout & wire_nl11OO_dataout & wire_nl1i1i_dataout & niOi1i & wire_nl1i1i_dataout & wire_niOOOl_dataout & wire_nl1i1i_dataout & niOi1i & wire_nl1i1i_dataout & wire_nl1i1i_dataout); + wire_n0OO0i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OO0i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0i_data, + o => wire_n0OO0i_o, + sel => wire_n0OO0i_sel + ); + wire_n0OO0l_data <= ( wire_nl1i1l_dataout & wire_niOlOl_dataout & wire_nl1i1l_dataout & wire_niOOOO_dataout & wire_nl1i1l_dataout & wire_niOlOl_dataout & wire_nl1i1l_dataout & wire_nl101i_dataout & wire_nl1i1l_dataout & wire_niOlOl_dataout & wire_nl1i1l_dataout & wire_niOOOO_dataout & wire_nl1i1l_dataout & wire_niOlOl_dataout & wire_nl1i1l_dataout & wire_nl1i1l_dataout); + wire_n0OO0l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OO0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0l_data, + o => wire_n0OO0l_o, + sel => wire_n0OO0l_sel + ); + wire_n0OO0O_data <= ( wire_nl1i1O_dataout & wire_niOlOO_dataout & wire_nl1i1O_dataout & wire_nl111i_dataout & wire_nl1i1O_dataout & wire_niOlOO_dataout & wire_nl1i1O_dataout & wire_nl101l_dataout & wire_nl1i1O_dataout & wire_niOlOO_dataout & wire_nl1i1O_dataout & wire_nl111i_dataout & wire_nl1i1O_dataout & wire_niOlOO_dataout & wire_nl1i1O_dataout & wire_nl1i1O_dataout); + wire_n0OO0O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OO0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0O_data, + o => wire_n0OO0O_o, + sel => wire_n0OO0O_sel + ); + wire_n0OO1i_data <= ( wire_nl10Oi_dataout & niO0Oi & wire_nl10Oi_dataout & wire_niOOll_dataout & wire_nl10Oi_dataout & niO0Oi & wire_nl10Oi_dataout & wire_nl11lO_dataout & wire_nl10Oi_dataout & niO0Oi & wire_nl10Oi_dataout & wire_niOOll_dataout & wire_nl10Oi_dataout & niO0Oi & wire_nl10Oi_dataout & wire_nl10Oi_dataout); + wire_n0OO1i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OO1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO1i_data, + o => wire_n0OO1i_o, + sel => wire_n0OO1i_sel + ); + wire_n0OO1l_data <= ( wire_nl10Ol_dataout & niO0Ol & wire_nl10Ol_dataout & wire_niOOlO_dataout & wire_nl10Ol_dataout & niO0Ol & wire_nl10Ol_dataout & wire_nl11Oi_dataout & wire_nl10Ol_dataout & niO0Ol & wire_nl10Ol_dataout & wire_niOOlO_dataout & wire_nl10Ol_dataout & niO0Ol & wire_nl10Ol_dataout & wire_nl10Ol_dataout); + wire_n0OO1l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OO1l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO1l_data, + o => wire_n0OO1l_o, + sel => wire_n0OO1l_sel + ); + wire_n0OO1O_data <= ( wire_nl10OO_dataout & niO0OO & wire_nl10OO_dataout & wire_niOOOi_dataout & wire_nl10OO_dataout & niO0OO & wire_nl10OO_dataout & wire_nl11Ol_dataout & wire_nl10OO_dataout & niO0OO & wire_nl10OO_dataout & wire_niOOOi_dataout & wire_nl10OO_dataout & niO0OO & wire_nl10OO_dataout & wire_nl10OO_dataout); + wire_n0OO1O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OO1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO1O_data, + o => wire_n0OO1O_o, + sel => wire_n0OO1O_sel + ); + wire_n0OOii_data <= ( wire_nl1i0i_dataout & wire_niOO1i_dataout & wire_nl1i0i_dataout & wire_nl111l_dataout & wire_nl1i0i_dataout & wire_niOO1i_dataout & wire_nl1i0i_dataout & wire_nl101O_dataout & wire_nl1i0i_dataout & wire_niOO1i_dataout & wire_nl1i0i_dataout & wire_nl111l_dataout & wire_nl1i0i_dataout & wire_niOO1i_dataout & wire_nl1i0i_dataout & wire_nl1i0i_dataout); + wire_n0OOii_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOii_data, + o => wire_n0OOii_o, + sel => wire_n0OOii_sel + ); + wire_n0OOil_data <= ( wire_nl1i0l_dataout & wire_niOO1l_dataout & wire_nl1i0l_dataout & wire_nl111O_dataout & wire_nl1i0l_dataout & wire_niOO1l_dataout & wire_nl1i0l_dataout & wire_nl100i_dataout & wire_nl1i0l_dataout & wire_niOO1l_dataout & wire_nl1i0l_dataout & wire_nl111O_dataout & wire_nl1i0l_dataout & wire_niOO1l_dataout & wire_nl1i0l_dataout & wire_nl1i0l_dataout); + wire_n0OOil_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOil_data, + o => wire_n0OOil_o, + sel => wire_n0OOil_sel + ); + wire_n0OOiO_data <= ( wire_nl1i0O_dataout & wire_niOO1O_dataout & wire_nl1i0O_dataout & wire_nl110i_dataout & wire_nl1i0O_dataout & wire_niOO1O_dataout & wire_nl1i0O_dataout & wire_nl100l_dataout & wire_nl1i0O_dataout & wire_niOO1O_dataout & wire_nl1i0O_dataout & wire_nl110i_dataout & wire_nl1i0O_dataout & wire_niOO1O_dataout & wire_nl1i0O_dataout & wire_nl1i0O_dataout); + wire_n0OOiO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOiO_data, + o => wire_n0OOiO_o, + sel => wire_n0OOiO_sel + ); + wire_n0OOli_data <= ( wire_nl1iii_dataout & wire_niOO0i_dataout & wire_nl1iii_dataout & wire_nl110l_dataout & wire_nl1iii_dataout & wire_niOO0i_dataout & wire_nl1iii_dataout & wire_nl100O_dataout & wire_nl1iii_dataout & wire_niOO0i_dataout & wire_nl1iii_dataout & wire_nl110l_dataout & wire_nl1iii_dataout & wire_niOO0i_dataout & wire_nl1iii_dataout & wire_nl1iii_dataout); + wire_n0OOli_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOli : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOli_data, + o => wire_n0OOli_o, + sel => wire_n0OOli_sel + ); + wire_n0OOll_data <= ( wire_nl1iil_dataout & wire_niOO0l_dataout & wire_nl1iil_dataout & wire_nl110O_dataout & wire_nl1iil_dataout & wire_niOO0l_dataout & wire_nl1iil_dataout & wire_nl10ii_dataout & wire_nl1iil_dataout & wire_niOO0l_dataout & wire_nl1iil_dataout & wire_nl110O_dataout & wire_nl1iil_dataout & wire_niOO0l_dataout & wire_nl1iil_dataout & wire_nl1iil_dataout); + wire_n0OOll_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOll_data, + o => wire_n0OOll_o, + sel => wire_n0OOll_sel + ); + wire_n0OOlO_data <= ( wire_nl1iiO_dataout & wire_niOO0O_dataout & wire_nl1iiO_dataout & wire_nl11ii_dataout & wire_nl1iiO_dataout & wire_niOO0O_dataout & wire_nl1iiO_dataout & wire_nl10il_dataout & wire_nl1iiO_dataout & wire_niOO0O_dataout & wire_nl1iiO_dataout & wire_nl11ii_dataout & wire_nl1iiO_dataout & wire_niOO0O_dataout & wire_nl1iiO_dataout & wire_nl1iiO_dataout); + wire_n0OOlO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOlO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOlO_data, + o => wire_n0OOlO_o, + sel => wire_n0OOlO_sel + ); + wire_n0OOOi_data <= ( wire_nl1ili_dataout & wire_niOOii_dataout & wire_nl1ili_dataout & wire_nl11il_dataout & wire_nl1ili_dataout & wire_niOOii_dataout & wire_nl1ili_dataout & wire_nl10iO_dataout & wire_nl1ili_dataout & wire_niOOii_dataout & wire_nl1ili_dataout & wire_nl11il_dataout & wire_nl1ili_dataout & wire_niOOii_dataout & wire_nl1ili_dataout & wire_nl1ili_dataout); + wire_n0OOOi_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOOi_data, + o => wire_n0OOOi_o, + sel => wire_n0OOOi_sel + ); + wire_n0OOOl_data <= ( wire_nl1ill_dataout & wire_niOOil_dataout & wire_nl1ill_dataout & wire_nl11iO_dataout & wire_nl1ill_dataout & wire_niOOil_dataout & wire_nl1ill_dataout & wire_nl10li_dataout & wire_nl1ill_dataout & wire_niOOil_dataout & wire_nl1ill_dataout & wire_nl11iO_dataout & wire_nl1ill_dataout & wire_niOOil_dataout & wire_nl1ill_dataout & wire_nl1ill_dataout); + wire_n0OOOl_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOOl_data, + o => wire_n0OOOl_o, + sel => wire_n0OOOl_sel + ); + wire_n0OOOO_data <= ( wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl11li_dataout & wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl10ll_dataout & wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl11li_dataout & wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl1ilO_dataout); + wire_n0OOOO_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + n0OOOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOOO_data, + o => wire_n0OOOO_o, + sel => wire_n0OOOO_sel + ); + wire_ni110i_data <= ( wire_nl1l1i_dataout & wire_niOOOi_dataout & wire_nl1l1i_dataout & wire_nl11Ol_dataout & wire_nl1l1i_dataout & wire_niOOOi_dataout & wire_nl1l1i_dataout & wire_nl10OO_dataout & wire_nl1l1i_dataout & wire_niOOOi_dataout & wire_nl1l1i_dataout & wire_nl11Ol_dataout & wire_nl1l1i_dataout & wire_niOOOi_dataout & wire_nl1l1i_dataout & wire_nl1l1i_dataout); + wire_ni110i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + ni110i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni110i_data, + o => wire_ni110i_o, + sel => wire_ni110i_sel + ); + wire_ni110l_data <= ( wire_nl1l1l_dataout & wire_niOOOl_dataout & wire_nl1l1l_dataout & wire_nl11OO_dataout & wire_nl1l1l_dataout & wire_niOOOl_dataout & wire_nl1l1l_dataout & wire_nl1i1i_dataout & wire_nl1l1l_dataout & wire_niOOOl_dataout & wire_nl1l1l_dataout & wire_nl11OO_dataout & wire_nl1l1l_dataout & wire_niOOOl_dataout & wire_nl1l1l_dataout & wire_nl1l1l_dataout); + wire_ni110l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + ni110l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni110l_data, + o => wire_ni110l_o, + sel => wire_ni110l_sel + ); + wire_ni111i_data <= ( wire_nl1iOi_dataout & wire_niOOli_dataout & wire_nl1iOi_dataout & wire_nl11ll_dataout & wire_nl1iOi_dataout & wire_niOOli_dataout & wire_nl1iOi_dataout & wire_nl10lO_dataout & wire_nl1iOi_dataout & wire_niOOli_dataout & wire_nl1iOi_dataout & wire_nl11ll_dataout & wire_nl1iOi_dataout & wire_niOOli_dataout & wire_nl1iOi_dataout & wire_nl1iOi_dataout); + wire_ni111i_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + ni111i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni111i_data, + o => wire_ni111i_o, + sel => wire_ni111i_sel + ); + wire_ni111l_data <= ( wire_nl1iOl_dataout & wire_niOOll_dataout & wire_nl1iOl_dataout & wire_nl11lO_dataout & wire_nl1iOl_dataout & wire_niOOll_dataout & wire_nl1iOl_dataout & wire_nl10Oi_dataout & wire_nl1iOl_dataout & wire_niOOll_dataout & wire_nl1iOl_dataout & wire_nl11lO_dataout & wire_nl1iOl_dataout & wire_niOOll_dataout & wire_nl1iOl_dataout & wire_nl1iOl_dataout); + wire_ni111l_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + ni111l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni111l_data, + o => wire_ni111l_o, + sel => wire_ni111l_sel + ); + wire_ni111O_data <= ( wire_nl1iOO_dataout & wire_niOOlO_dataout & wire_nl1iOO_dataout & wire_nl11Oi_dataout & wire_nl1iOO_dataout & wire_niOOlO_dataout & wire_nl1iOO_dataout & wire_nl10Ol_dataout & wire_nl1iOO_dataout & wire_niOOlO_dataout & wire_nl1iOO_dataout & wire_nl11Oi_dataout & wire_nl1iOO_dataout & wire_niOOlO_dataout & wire_nl1iOO_dataout & wire_nl1iOO_dataout); + wire_ni111O_sel <= ( niiOil & niiOii & niiO0O & niiO0l); + ni111O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni111O_data, + o => wire_ni111O_o, + sel => wire_ni111O_sel + ); + wire_ni1i1l_data <= ( wire_nl10ll_dataout & wire_niOOiO_dataout & wire_nl10ll_dataout & wire_nl11li_dataout & wire_nl10ll_dataout & wire_niOOiO_dataout & wire_nl10ll_dataout & wire_nl10ll_dataout); + wire_ni1i1l_sel <= ( wire_ni1lll_dataout & wire_ni1lli_dataout & wire_ni1liO_dataout); + ni1i1l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni1i1l_data, + o => wire_ni1i1l_o, + sel => wire_ni1i1l_sel + ); + wire_ni1l1O_data <= ( wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl11li_dataout & wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl10ll_dataout & wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl11li_dataout & wire_nl1ilO_dataout & wire_niOOiO_dataout & wire_nl1ilO_dataout & wire_nl1ilO_dataout); + wire_ni1l1O_sel <= ( wire_ni1llO_dataout & wire_ni1lll_dataout & wire_ni1lli_dataout & wire_ni1liO_dataout); + ni1l1O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1l1O_data, + o => wire_ni1l1O_o, + sel => wire_ni1l1O_sel + ); + wire_ni1lOi_data <= ( wire_ni1O1l_dataout & wire_ni000l_dataout & wire_ni0ili_dataout & "0" & wire_ni0lOO_dataout & wire_nii01l_dataout & wire_niiili_dataout & "0"); + wire_ni1lOi_sel <= ( rbytord_2sym_en & rbytorden(1 DOWNTO 0)); + ni1lOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni1lOi_data, + o => wire_ni1lOi_o, + sel => wire_ni1lOi_sel + ); + wire_ni1lOl_data <= ( wire_ni1Oli_dataout & wire_ni00li_dataout & wire_ni0iOO_dataout & "0" & wire_ni0Oli_dataout & wire_nii0iO_dataout & wire_niil1l_dataout & "0"); + wire_ni1lOl_sel <= ( rbytord_2sym_en & rbytorden(1 DOWNTO 0)); + ni1lOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni1lOl_data, + o => wire_ni1lOl_o, + sel => wire_ni1lOl_sel + ); + wire_ni1lOO_data <= ( wire_ni010i_dataout & wire_ni00OO_dataout & wire_ni0l0l_dataout & "0" & wire_ni0OOl_dataout & wire_nii0lO_dataout & wire_niil0l_dataout & "0"); + wire_ni1lOO_sel <= ( rbytord_2sym_en & rbytorden(1 DOWNTO 0)); + ni1lOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni1lOO_data, + o => wire_ni1lOO_o, + sel => wire_ni1lOO_sel + ); + wire_ni1O1i_data <= ( wire_ni01Oi_dataout & wire_ni0i0O_dataout & wire_ni0lll_dataout & "0" & wire_nii1li_dataout & wire_niii0l_dataout & wire_niilOi_dataout & "0"); + wire_ni1O1i_sel <= ( rbytord_2sym_en & rbytorden(1 DOWNTO 0)); + ni1O1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni1O1i_data, + o => wire_ni1O1i_o, + sel => wire_ni1O1i_sel + ); + wire_nlO000i_data <= ( wire_n00iiO_dataout & wire_n0lOli_dataout & wire_n10O1l_dataout & wire_n1O1Oi_dataout & wire_nlOi1il_dataout & wire_nlOOi0O_dataout & wire_nl10ll_dataout & wire_nl10ll_dataout); + wire_nlO000i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO000i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO000i_data, + o => wire_nlO000i_o, + sel => wire_nlO000i_sel + ); + wire_nlO000l_data <= ( wire_n00ili_dataout & wire_n0lOll_dataout & wire_n10O1O_dataout & wire_n1O1Ol_dataout & wire_nlOi1iO_dataout & wire_nlOOiii_dataout & wire_nl10lO_dataout & wire_nl10lO_dataout); + wire_nlO000l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO000l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO000l_data, + o => wire_nlO000l_o, + sel => wire_nlO000l_sel + ); + wire_nlO000O_data <= ( wire_n00ill_dataout & wire_n0lOlO_dataout & wire_n10O0i_dataout & wire_n1O1OO_dataout & wire_nlOi1li_dataout & wire_nlOOiil_dataout & wire_nl10Oi_dataout & wire_nl10Oi_dataout); + wire_nlO000O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO000O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO000O_data, + o => wire_nlO000O_o, + sel => wire_nlO000O_sel + ); + wire_nlO001i_data <= ( wire_n00i0O_dataout & wire_n0lOii_dataout & wire_n10lOl_dataout & wire_n1O1li_dataout & wire_nlOi10l_dataout & wire_nlOOi1O_dataout & wire_nl10il_dataout & wire_nl10il_dataout); + wire_nlO001i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO001i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO001i_data, + o => wire_nlO001i_o, + sel => wire_nlO001i_sel + ); + wire_nlO001l_data <= ( wire_n00iii_dataout & wire_n0lOil_dataout & wire_n10lOO_dataout & wire_n1O1ll_dataout & wire_nlOi10O_dataout & wire_nlOOi0i_dataout & wire_nl10iO_dataout & wire_nl10iO_dataout); + wire_nlO001l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO001l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO001l_data, + o => wire_nlO001l_o, + sel => wire_nlO001l_sel + ); + wire_nlO001O_data <= ( wire_n00iil_dataout & wire_n0lOiO_dataout & wire_n10O1i_dataout & wire_n1O1lO_dataout & wire_nlOi1ii_dataout & wire_nlOOi0l_dataout & wire_nl10li_dataout & wire_nl10li_dataout); + wire_nlO001O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO001O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO001O_data, + o => wire_nlO001O_o, + sel => wire_nlO001O_sel + ); + wire_nlO00ii_data <= ( wire_n00ilO_dataout & wire_n0lOOi_dataout & wire_n10O0l_dataout & wire_n1O01i_dataout & wire_nlOi1ll_dataout & wire_nlOOiiO_dataout & wire_nl10Ol_dataout & wire_nl10Ol_dataout); + wire_nlO00ii_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00ii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00ii_data, + o => wire_nlO00ii_o, + sel => wire_nlO00ii_sel + ); + wire_nlO00il_data <= ( wire_n00iOi_dataout & wire_n0lOOl_dataout & wire_n10O0O_dataout & wire_n1O01l_dataout & wire_nlOi1lO_dataout & wire_nlOOili_dataout & wire_nl10OO_dataout & wire_nl10OO_dataout); + wire_nlO00il_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00il : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00il_data, + o => wire_nlO00il_o, + sel => wire_nlO00il_sel + ); + wire_nlO00iO_data <= ( wire_n00iOl_dataout & wire_n0lOOO_dataout & wire_n10Oii_dataout & wire_n1O01O_dataout & wire_nlOi1Oi_dataout & wire_nlOOill_dataout & wire_nl1i1i_dataout & wire_nl1i1i_dataout); + wire_nlO00iO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00iO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00iO_data, + o => wire_nlO00iO_o, + sel => wire_nlO00iO_sel + ); + wire_nlO00li_data <= ( wire_n00iOO_dataout & wire_n0O11i_dataout & wire_n10Oil_dataout & wire_n1O00i_dataout & wire_nlOi1Ol_dataout & wire_nlOOilO_dataout & wire_nl1i1l_dataout & wire_nl1i1l_dataout); + wire_nlO00li_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00li : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00li_data, + o => wire_nlO00li_o, + sel => wire_nlO00li_sel + ); + wire_nlO00ll_data <= ( wire_n00l1i_dataout & wire_n0O11l_dataout & wire_n10OiO_dataout & wire_n1O00l_dataout & wire_nlOi1OO_dataout & wire_nlOOiOi_dataout & wire_nl1i1O_dataout & wire_nl1i1O_dataout); + wire_nlO00ll_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00ll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00ll_data, + o => wire_nlO00ll_o, + sel => wire_nlO00ll_sel + ); + wire_nlO00lO_data <= ( wire_n00l1l_dataout & wire_n0O11O_dataout & wire_n10Oli_dataout & wire_n1O00O_dataout & wire_nlOi01i_dataout & wire_nlOOiOl_dataout & wire_nl1i0i_dataout & wire_nl1i0i_dataout); + wire_nlO00lO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00lO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00lO_data, + o => wire_nlO00lO_o, + sel => wire_nlO00lO_sel + ); + wire_nlO00Oi_data <= ( wire_n00l1O_dataout & wire_n0O10i_dataout & wire_n10Oll_dataout & wire_n1O0ii_dataout & wire_nlOi01l_dataout & wire_nlOOiOO_dataout & wire_nl1i0l_dataout & wire_nl1i0l_dataout); + wire_nlO00Oi_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00Oi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00Oi_data, + o => wire_nlO00Oi_o, + sel => wire_nlO00Oi_sel + ); + wire_nlO00Ol_data <= ( wire_n00l0i_dataout & wire_n0O10l_dataout & wire_n10OlO_dataout & wire_n1O0il_dataout & wire_nlOi01O_dataout & wire_nlOOl1i_dataout & wire_nl1i0O_dataout & wire_nl1i0O_dataout); + wire_nlO00Ol_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00Ol : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00Ol_data, + o => wire_nlO00Ol_o, + sel => wire_nlO00Ol_sel + ); + wire_nlO00OO_data <= ( wire_n00l0l_dataout & wire_n0O10O_dataout & wire_n10OOi_dataout & wire_n1O0iO_dataout & wire_nlOi00i_dataout & wire_nlOOl1l_dataout & wire_nl1iii_dataout & wire_nl1iii_dataout); + wire_nlO00OO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO00OO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00OO_data, + o => wire_nlO00OO_o, + sel => wire_nlO00OO_sel + ); + wire_nlO010i_data <= ( wire_n000iO_dataout & wire_n0llli_dataout & wire_n10l1l_dataout & wire_n1lOOi_dataout & wire_nlO0Oil_dataout & wire_nlOO00O_dataout & wire_nl11ll_dataout & wire_nl11ll_dataout); + wire_nlO010i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO010i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO010i_data, + o => wire_nlO010i_o, + sel => wire_nlO010i_sel + ); + wire_nlO010l_data <= ( wire_n000li_dataout & wire_n0llll_dataout & wire_n10l1O_dataout & wire_n1lOOl_dataout & wire_nlO0OiO_dataout & wire_nlOO0ii_dataout & wire_nl11lO_dataout & wire_nl11lO_dataout); + wire_nlO010l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO010l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO010l_data, + o => wire_nlO010l_o, + sel => wire_nlO010l_sel + ); + wire_nlO010O_data <= ( wire_n000ll_dataout & wire_n0lllO_dataout & wire_n10l0i_dataout & wire_n1lOOO_dataout & wire_nlO0Oli_dataout & wire_nlOO0il_dataout & wire_nl11Oi_dataout & wire_nl11Oi_dataout); + wire_nlO010O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO010O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO010O_data, + o => wire_nlO010O_o, + sel => wire_nlO010O_sel + ); + wire_nlO011i_data <= ( wire_n0000O_dataout & wire_n0llii_dataout & wire_n10iOl_dataout & wire_n1lOli_dataout & wire_nlO0O0l_dataout & wire_nlOO01O_dataout & wire_nl11il_dataout & wire_nl11il_dataout); + wire_nlO011i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO011i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO011i_data, + o => wire_nlO011i_o, + sel => wire_nlO011i_sel + ); + wire_nlO011l_data <= ( wire_n000ii_dataout & wire_n0llil_dataout & wire_n10iOO_dataout & wire_n1lOll_dataout & wire_nlO0O0O_dataout & wire_nlOO00i_dataout & wire_nl11iO_dataout & wire_nl11iO_dataout); + wire_nlO011l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO011l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO011l_data, + o => wire_nlO011l_o, + sel => wire_nlO011l_sel + ); + wire_nlO011O_data <= ( wire_n000il_dataout & wire_n0lliO_dataout & wire_n10l1i_dataout & wire_n1lOlO_dataout & wire_nlO0Oii_dataout & wire_nlOO00l_dataout & wire_nl11li_dataout & wire_nl11li_dataout); + wire_nlO011O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO011O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO011O_data, + o => wire_nlO011O_o, + sel => wire_nlO011O_sel + ); + wire_nlO01ii_data <= ( wire_n000lO_dataout & wire_n0llOi_dataout & wire_n10l0l_dataout & wire_n1O11i_dataout & wire_nlO0Oll_dataout & wire_nlOO0iO_dataout & wire_nl11Ol_dataout & wire_nl11Ol_dataout); + wire_nlO01ii_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01ii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01ii_data, + o => wire_nlO01ii_o, + sel => wire_nlO01ii_sel + ); + wire_nlO01il_data <= ( wire_n000Oi_dataout & wire_n0llOl_dataout & wire_n10l0O_dataout & wire_n1O11l_dataout & wire_nlO0OlO_dataout & wire_nlOO0li_dataout & wire_nl11OO_dataout & wire_nl11OO_dataout); + wire_nlO01il_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01il : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01il_data, + o => wire_nlO01il_o, + sel => wire_nlO01il_sel + ); + wire_nlO01iO_data <= ( wire_n000Ol_dataout & wire_n0llOO_dataout & wire_n10lii_dataout & wire_n1O11O_dataout & wire_nlO0OOi_dataout & wire_nlOO0ll_dataout & wire_nl101i_dataout & wire_nl101i_dataout); + wire_nlO01iO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01iO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01iO_data, + o => wire_nlO01iO_o, + sel => wire_nlO01iO_sel + ); + wire_nlO01li_data <= ( wire_n000OO_dataout & wire_n0lO1i_dataout & wire_n10lil_dataout & wire_n1O10i_dataout & wire_nlO0OOl_dataout & wire_nlOO0lO_dataout & wire_nl101l_dataout & wire_nl101l_dataout); + wire_nlO01li_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01li : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01li_data, + o => wire_nlO01li_o, + sel => wire_nlO01li_sel + ); + wire_nlO01ll_data <= ( wire_n00i1i_dataout & wire_n0lO1l_dataout & wire_n10liO_dataout & wire_n1O10l_dataout & wire_nlO0OOO_dataout & wire_nlOO0Oi_dataout & wire_nl101O_dataout & wire_nl101O_dataout); + wire_nlO01ll_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01ll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01ll_data, + o => wire_nlO01ll_o, + sel => wire_nlO01ll_sel + ); + wire_nlO01lO_data <= ( wire_n00i1l_dataout & wire_n0lO1O_dataout & wire_n10lli_dataout & wire_n1O10O_dataout & wire_nlOi11i_dataout & wire_nlOO0Ol_dataout & wire_nl100i_dataout & wire_nl100i_dataout); + wire_nlO01lO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01lO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01lO_data, + o => wire_nlO01lO_o, + sel => wire_nlO01lO_sel + ); + wire_nlO01Oi_data <= ( wire_n00i1O_dataout & wire_n0lO0i_dataout & wire_n10lll_dataout & wire_n1O1ii_dataout & wire_nlOi11l_dataout & wire_nlOO0OO_dataout & wire_nl100l_dataout & wire_nl100l_dataout); + wire_nlO01Oi_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01Oi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01Oi_data, + o => wire_nlO01Oi_o, + sel => wire_nlO01Oi_sel + ); + wire_nlO01Ol_data <= ( wire_n00i0i_dataout & wire_n0lO0l_dataout & wire_n10llO_dataout & wire_n1O1il_dataout & wire_nlOi11O_dataout & wire_nlOOi1i_dataout & wire_nl100O_dataout & wire_nl100O_dataout); + wire_nlO01Ol_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01Ol : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01Ol_data, + o => wire_nlO01Ol_o, + sel => wire_nlO01Ol_sel + ); + wire_nlO01OO_data <= ( wire_n00i0l_dataout & wire_n0lO0O_dataout & wire_n10lOi_dataout & wire_n1O1iO_dataout & wire_nlOi10i_dataout & wire_nlOOi1l_dataout & wire_nl10ii_dataout & wire_nl10ii_dataout); + wire_nlO01OO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO01OO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO01OO_data, + o => wire_nlO01OO_o, + sel => wire_nlO01OO_sel + ); + wire_nlO0i0i_data <= ( wire_n00liO_dataout & wire_n0O1li_dataout & wire_n1i11l_dataout & wire_n1O0Oi_dataout & wire_nlOi0il_dataout & wire_nlOOl0O_dataout & wire_nl1ill_dataout & wire_nl1ill_dataout); + wire_nlO0i0i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0i0i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0i0i_data, + o => wire_nlO0i0i_o, + sel => wire_nlO0i0i_sel + ); + wire_nlO0i0l_data <= ( wire_n00lli_dataout & wire_n0O1ll_dataout & wire_n1i11O_dataout & wire_n1O0Ol_dataout & wire_nlOi0iO_dataout & wire_nlOOlii_dataout & wire_nl1ilO_dataout & wire_nl1ilO_dataout); + wire_nlO0i0l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0i0l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0i0l_data, + o => wire_nlO0i0l_o, + sel => wire_nlO0i0l_sel + ); + wire_nlO0i0O_data <= ( wire_n00lll_dataout & wire_n0O1lO_dataout & wire_n1i10i_dataout & wire_n1O0OO_dataout & wire_nlOi0li_dataout & wire_nlOOlil_dataout & wire_nl1iOi_dataout & wire_nl1iOi_dataout); + wire_nlO0i0O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0i0O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0i0O_data, + o => wire_nlO0i0O_o, + sel => wire_nlO0i0O_sel + ); + wire_nlO0i1i_data <= ( wire_n00l0O_dataout & wire_n0O1ii_dataout & wire_n10OOl_dataout & wire_n1O0li_dataout & wire_nlOi00l_dataout & wire_nlOOl1O_dataout & wire_nl1iil_dataout & wire_nl1iil_dataout); + wire_nlO0i1i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0i1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0i1i_data, + o => wire_nlO0i1i_o, + sel => wire_nlO0i1i_sel + ); + wire_nlO0i1l_data <= ( wire_n00lii_dataout & wire_n0O1il_dataout & wire_n10OOO_dataout & wire_n1O0ll_dataout & wire_nlOi00O_dataout & wire_nlOOl0i_dataout & wire_nl1iiO_dataout & wire_nl1iiO_dataout); + wire_nlO0i1l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0i1l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0i1l_data, + o => wire_nlO0i1l_o, + sel => wire_nlO0i1l_sel + ); + wire_nlO0i1O_data <= ( wire_n00lil_dataout & wire_n0O1iO_dataout & wire_n1i11i_dataout & wire_n1O0lO_dataout & wire_nlOi0ii_dataout & wire_nlOOl0l_dataout & wire_nl1ili_dataout & wire_nl1ili_dataout); + wire_nlO0i1O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0i1O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0i1O_data, + o => wire_nlO0i1O_o, + sel => wire_nlO0i1O_sel + ); + wire_nlO0iii_data <= ( wire_n00llO_dataout & wire_n0O1Oi_dataout & wire_n1i10l_dataout & wire_n1Oi1i_dataout & wire_nlOi0ll_dataout & wire_nlOOliO_dataout & wire_nl1iOl_dataout & wire_nl1iOl_dataout); + wire_nlO0iii_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0iii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0iii_data, + o => wire_nlO0iii_o, + sel => wire_nlO0iii_sel + ); + wire_nlO0iil_data <= ( wire_n00lOi_dataout & wire_n0O1Ol_dataout & wire_n1i10O_dataout & wire_n1Oi1l_dataout & wire_nlOi0lO_dataout & wire_nlOOlli_dataout & wire_nl1iOO_dataout & wire_nl1iOO_dataout); + wire_nlO0iil_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0iil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0iil_data, + o => wire_nlO0iil_o, + sel => wire_nlO0iil_sel + ); + wire_nlO0iiO_data <= ( wire_n00lOl_dataout & wire_n0O1OO_dataout & wire_n1i1ii_dataout & wire_n1Oi1O_dataout & wire_nlOi0Oi_dataout & wire_nlOOlll_dataout & wire_nl1l1i_dataout & wire_nl1l1i_dataout); + wire_nlO0iiO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0iiO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0iiO_data, + o => wire_nlO0iiO_o, + sel => wire_nlO0iiO_sel + ); + wire_nlO0ili_data <= ( wire_n00lOO_dataout & wire_n0O01i_dataout & wire_n1i1il_dataout & wire_n1Oi0i_dataout & wire_nlOi0Ol_dataout & wire_nlOOllO_dataout & wire_nl1l1l_dataout & wire_nl1l1l_dataout); + wire_nlO0ili_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO0ili : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0ili_data, + o => wire_nlO0ili_o, + sel => wire_nlO0ili_sel + ); + wire_nlO1lii_data <= ( wire_n01OlO_dataout & wire_n0l0Oi_dataout & wire_n1000l_dataout & wire_n1ll1i_dataout & wire_nlO0ill_dataout & wire_nlOlOiO_dataout & wire_niOlOl_dataout & wire_niOlOl_dataout); + wire_nlO1lii_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1lii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1lii_data, + o => wire_nlO1lii_o, + sel => wire_nlO1lii_sel + ); + wire_nlO1lil_data <= ( wire_n01OOi_dataout & wire_n0l0Ol_dataout & wire_n1000O_dataout & wire_n1ll1l_dataout & wire_nlO0ilO_dataout & wire_nlOlOli_dataout & wire_niOlOO_dataout & wire_niOlOO_dataout); + wire_nlO1lil_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1lil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1lil_data, + o => wire_nlO1lil_o, + sel => wire_nlO1lil_sel + ); + wire_nlO1liO_data <= ( wire_n01OOl_dataout & wire_n0l0OO_dataout & wire_n100ii_dataout & wire_n1ll1O_dataout & wire_nlO0iOi_dataout & wire_nlOlOll_dataout & wire_niOO1i_dataout & wire_niOO1i_dataout); + wire_nlO1liO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1liO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1liO_data, + o => wire_nlO1liO_o, + sel => wire_nlO1liO_sel + ); + wire_nlO1lli_data <= ( wire_n01OOO_dataout & wire_n0li1i_dataout & wire_n100il_dataout & wire_n1ll0i_dataout & wire_nlO0iOl_dataout & wire_nlOlOlO_dataout & wire_niOO1l_dataout & wire_niOO1l_dataout); + wire_nlO1lli_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1lli : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1lli_data, + o => wire_nlO1lli_o, + sel => wire_nlO1lli_sel + ); + wire_nlO1lll_data <= ( wire_n0011i_dataout & wire_n0li1l_dataout & wire_n100iO_dataout & wire_n1ll0l_dataout & wire_nlO0iOO_dataout & wire_nlOlOOi_dataout & wire_niOO1O_dataout & wire_niOO1O_dataout); + wire_nlO1lll_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1lll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1lll_data, + o => wire_nlO1lll_o, + sel => wire_nlO1lll_sel + ); + wire_nlO1llO_data <= ( wire_n0011l_dataout & wire_n0li1O_dataout & wire_n100li_dataout & wire_n1ll0O_dataout & wire_nlO0l1i_dataout & wire_nlOlOOl_dataout & wire_niOO0i_dataout & wire_niOO0i_dataout); + wire_nlO1llO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1llO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1llO_data, + o => wire_nlO1llO_o, + sel => wire_nlO1llO_sel + ); + wire_nlO1lOi_data <= ( wire_n0011O_dataout & wire_n0li0i_dataout & wire_n100ll_dataout & wire_n1llii_dataout & wire_nlO0l1l_dataout & wire_nlOlOOO_dataout & wire_niOO0l_dataout & wire_niOO0l_dataout); + wire_nlO1lOi_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1lOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1lOi_data, + o => wire_nlO1lOi_o, + sel => wire_nlO1lOi_sel + ); + wire_nlO1lOl_data <= ( wire_n0010i_dataout & wire_n0li0l_dataout & wire_n100lO_dataout & wire_n1llil_dataout & wire_nlO0l1O_dataout & wire_nlOO11i_dataout & wire_niOO0O_dataout & wire_niOO0O_dataout); + wire_nlO1lOl_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1lOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1lOl_data, + o => wire_nlO1lOl_o, + sel => wire_nlO1lOl_sel + ); + wire_nlO1lOO_data <= ( wire_n0010l_dataout & wire_n0li0O_dataout & wire_n100Oi_dataout & wire_n1lliO_dataout & wire_nlO0l0i_dataout & wire_nlOO11l_dataout & wire_niOOii_dataout & wire_niOOii_dataout); + wire_nlO1lOO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1lOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1lOO_data, + o => wire_nlO1lOO_o, + sel => wire_nlO1lOO_sel + ); + wire_nlO1O0i_data <= ( wire_n001iO_dataout & wire_n0lili_dataout & wire_n10i1l_dataout & wire_n1llOi_dataout & wire_nlO0lil_dataout & wire_nlOO10O_dataout & wire_niOOll_dataout & wire_niOOll_dataout); + wire_nlO1O0i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1O0i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1O0i_data, + o => wire_nlO1O0i_o, + sel => wire_nlO1O0i_sel + ); + wire_nlO1O0l_data <= ( wire_n001li_dataout & wire_n0lill_dataout & wire_n10i1O_dataout & wire_n1llOl_dataout & wire_nlO0liO_dataout & wire_nlOO1ii_dataout & wire_niOOlO_dataout & wire_niOOlO_dataout); + wire_nlO1O0l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1O0l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1O0l_data, + o => wire_nlO1O0l_o, + sel => wire_nlO1O0l_sel + ); + wire_nlO1O0O_data <= ( wire_n001ll_dataout & wire_n0lilO_dataout & wire_n10i0i_dataout & wire_n1llOO_dataout & wire_nlO0lli_dataout & wire_nlOO1il_dataout & wire_niOOOi_dataout & wire_niOOOi_dataout); + wire_nlO1O0O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1O0O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1O0O_data, + o => wire_nlO1O0O_o, + sel => wire_nlO1O0O_sel + ); + wire_nlO1O1i_data <= ( wire_n0010O_dataout & wire_n0liii_dataout & wire_n100Ol_dataout & wire_n1llli_dataout & wire_nlO0l0l_dataout & wire_nlOO11O_dataout & wire_niOOil_dataout & wire_niOOil_dataout); + wire_nlO1O1i_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1O1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1O1i_data, + o => wire_nlO1O1i_o, + sel => wire_nlO1O1i_sel + ); + wire_nlO1O1l_data <= ( wire_n001ii_dataout & wire_n0liil_dataout & wire_n100OO_dataout & wire_n1llll_dataout & wire_nlO0l0O_dataout & wire_nlOO10i_dataout & wire_niOOiO_dataout & wire_niOOiO_dataout); + wire_nlO1O1l_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1O1l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1O1l_data, + o => wire_nlO1O1l_o, + sel => wire_nlO1O1l_sel + ); + wire_nlO1O1O_data <= ( wire_n001il_dataout & wire_n0liiO_dataout & wire_n10i1i_dataout & wire_n1lllO_dataout & wire_nlO0lii_dataout & wire_nlOO10l_dataout & wire_niOOli_dataout & wire_niOOli_dataout); + wire_nlO1O1O_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1O1O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1O1O_data, + o => wire_nlO1O1O_o, + sel => wire_nlO1O1O_sel + ); + wire_nlO1Oii_data <= ( wire_n001lO_dataout & wire_n0liOi_dataout & wire_n10i0l_dataout & wire_n1lO1i_dataout & wire_nlO0lll_dataout & wire_nlOO1iO_dataout & wire_niOOOl_dataout & wire_niOOOl_dataout); + wire_nlO1Oii_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1Oii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1Oii_data, + o => wire_nlO1Oii_o, + sel => wire_nlO1Oii_sel + ); + wire_nlO1Oil_data <= ( wire_n001Oi_dataout & wire_n0liOl_dataout & wire_n10i0O_dataout & wire_n1lO1l_dataout & wire_nlO0llO_dataout & wire_nlOO1li_dataout & wire_niOOOO_dataout & wire_niOOOO_dataout); + wire_nlO1Oil_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1Oil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1Oil_data, + o => wire_nlO1Oil_o, + sel => wire_nlO1Oil_sel + ); + wire_nlO1OiO_data <= ( wire_n001Ol_dataout & wire_n0liOO_dataout & wire_n10iii_dataout & wire_n1lO1O_dataout & wire_nlO0lOi_dataout & wire_nlOO1ll_dataout & wire_nl111i_dataout & wire_nl111i_dataout); + wire_nlO1OiO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1OiO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1OiO_data, + o => wire_nlO1OiO_o, + sel => wire_nlO1OiO_sel + ); + wire_nlO1Oli_data <= ( wire_n001OO_dataout & wire_n0ll1i_dataout & wire_n10iil_dataout & wire_n1lO0i_dataout & wire_nlO0lOl_dataout & wire_nlOO1lO_dataout & wire_nl111l_dataout & wire_nl111l_dataout); + wire_nlO1Oli_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1Oli : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1Oli_data, + o => wire_nlO1Oli_o, + sel => wire_nlO1Oli_sel + ); + wire_nlO1Oll_data <= ( wire_n0001i_dataout & wire_n0ll1l_dataout & wire_n10iiO_dataout & wire_n1lO0l_dataout & wire_nlO0lOO_dataout & wire_nlOO1Oi_dataout & wire_nl111O_dataout & wire_nl111O_dataout); + wire_nlO1Oll_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1Oll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1Oll_data, + o => wire_nlO1Oll_o, + sel => wire_nlO1Oll_sel + ); + wire_nlO1OlO_data <= ( wire_n0001l_dataout & wire_n0ll1O_dataout & wire_n10ili_dataout & wire_n1lO0O_dataout & wire_nlO0O1i_dataout & wire_nlOO1Ol_dataout & wire_nl110i_dataout & wire_nl110i_dataout); + wire_nlO1OlO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1OlO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1OlO_data, + o => wire_nlO1OlO_o, + sel => wire_nlO1OlO_sel + ); + wire_nlO1OOi_data <= ( wire_n0001O_dataout & wire_n0ll0i_dataout & wire_n10ill_dataout & wire_n1lOii_dataout & wire_nlO0O1l_dataout & wire_nlOO1OO_dataout & wire_nl110l_dataout & wire_nl110l_dataout); + wire_nlO1OOi_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1OOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1OOi_data, + o => wire_nlO1OOi_o, + sel => wire_nlO1OOi_sel + ); + wire_nlO1OOl_data <= ( wire_n0000i_dataout & wire_n0ll0l_dataout & wire_n10ilO_dataout & wire_n1lOil_dataout & wire_nlO0O1O_dataout & wire_nlOO01i_dataout & wire_nl110O_dataout & wire_nl110O_dataout); + wire_nlO1OOl_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1OOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1OOl_data, + o => wire_nlO1OOl_o, + sel => wire_nlO1OOl_sel + ); + wire_nlO1OOO_data <= ( wire_n0000l_dataout & wire_n0ll0O_dataout & wire_n10iOi_dataout & wire_n1lOiO_dataout & wire_nlO0O0i_dataout & wire_nlOO01l_dataout & wire_nl11ii_dataout & wire_nl11ii_dataout); + wire_nlO1OOO_sel <= ( rwa_6g_en & rdwidth & rbytord_2sym_en); + nlO1OOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO1OOO_data, + o => wire_nlO1OOO_o, + sel => wire_nlO1OOO_sel + ); + wire_niO1l_data <= ( wire_niOOl_dataout & wire_n1ill_w_lg_nll11l494w & nl110Ol & nl11iii & wire_w_lg_nl110lO485w & wire_n1ill_w_lg_nll11O482w & nl11i1O & nl11ili & wire_w_lg_nl11iiO473w & wire_w_lg_nl110lO470w); + wire_niO1l_sel <= ( nl110Oi & wire_niOOi_w_lg_w_o_range465w467w & wire_niOOi_w_lg_w_o_range461w463w & wire_niOOi_w_lg_w_o_range457w459w & wire_niOOi_w_lg_w_o_range453w455w & wire_niOOi_w_lg_w_o_range449w451w & wire_niOOi_w_lg_w_o_range445w447w & wire_niOOi_w_lg_w_o_range441w443w & wire_niOOi_w_lg_w_o_range437w439w & wire_niOOi_w_lg_w_o_range432w434w); + niO1l : oper_selector + GENERIC MAP ( + width_data => 10, + width_sel => 10 + ) + PORT MAP ( + data => wire_niO1l_data, + o => wire_niO1l_o, + sel => wire_niO1l_sel + ); + wire_nli1l_data <= ( wire_nliOl_dataout & wire_n1ill_w_lg_nliOOi312w & wire_n1ill_w_lg_nll10i308w & wire_nl11l1l40_w_lg_w_lg_q303w304w & wire_nl11liO34_w_lg_w_lg_q291w292w & wire_n1ill_w_lg_nliOOO284w & wire_nl11lOl30_w_lg_w_lg_q279w280w & wire_w_lg_nl11O0i271w & nl11O0l & wire_w_lg_w_lg_nl11OiO262w266w); + wire_nli1l_sel <= ( nl1010i & wire_nliOi_w_lg_w_lg_w_o_range253w255w259w & wire_nliOi_w_lg_w_o_range249w251w & wire_nliOi_w_lg_w_o_range245w247w & wire_nl11OlO22_w_lg_w_lg_q242w243w & wire_nliOi_w_lg_w_o_range231w233w & wire_nl11OOO18_w_lg_w_lg_q228w229w & wire_nliOi_w_lg_w_lg_w_o_range217w219w223w & wire_nl1011O14_w_lg_w_lg_q214w215w & wire_nliOi_w_lg_w_o_range206w208w); + nli1l : oper_selector + GENERIC MAP ( + width_data => 10, + width_sel => 10 + ) + PORT MAP ( + data => wire_nli1l_data, + o => wire_nli1l_o, + sel => wire_nli1l_sel + ); + wire_nl1000i_din <= ( rxstatus_int(2 DOWNTO 0) & rxvalid_int & phystatus_int & wire_nlO1ill_dataout & wire_nlO0ili_o & wire_nlO0iiO_o & wire_nlO0iil_o & wire_nlO0iii_o & wire_nlO0i0O_o & wire_nlO0i0l_o & wire_nlO0i0i_o & wire_nlO0i1O_o & wire_nlO0i1l_o & wire_nlO0i1i_o & wire_nlO00OO_o & wire_nlO00Ol_o & wire_nlO00Oi_o & wire_nlO00lO_o & wire_nlO00ll_o & wire_nlO00li_o & wire_nlO00iO_o & wire_nlO00il_o & wire_nlO00ii_o & wire_nlO000O_o & wire_nlO000l_o & wire_nlO000i_o & wire_nlO001O_o & wire_nlO001l_o & wire_nlO001i_o & wire_nlO01OO_o & wire_nlO01Ol_o & wire_nlO01Oi_o & wire_nlO01lO_o & wire_nlO01ll_o & wire_nlO01li_o & wire_nlO01iO_o & wire_nlO01il_o & wire_nlO01ii_o & wire_nlO010O_o & wire_nlO010l_o & wire_nlO010i_o & wire_nlO011O_o & wire_nlO011l_o & wire_nlO011i_o & wire_nlO1OOO_o & wire_nlO1OOl_o & wire_nlO1OOi_o & wire_nlO1OlO_o & wire_nlO1Oll_o & wire_nlO1Oli_o & wire_nlO1OiO_o & wire_nlO1Oil_o & wire_nlO1Oii_o & wire_nlO1O0O_o & wire_nlO1O0l_o & wire_nlO1O0i_o & wire_nlO1O1O_o & wire_nlO1O1l_o & wire_nlO1O1i_o & wire_nlO1lOO_o & wire_nlO1lOl_o & wire_nlO1lOi_o & wire_nlO1llO_o & wire_nlO1lll_o & wire_nlO1lli_o & wire_nlO1liO_o & wire_nlO1lil_o & wire_nlO1lii_o); + wire_nl1000i_pcs_wrapback_in <= ( pcs_wrapback_in(69 DOWNTO 0)); + nl1000i : cycloneiv_hssi_rx_digis_ph_fifo + PORT MAP ( + data_out => wire_nl1000i_data_out, + din => wire_nl1000i_din, + en => wire_vcc, + lowlatency_en => rrxfifo_lowlatency_en, + pcs_wrapback_in => wire_nl1000i_pcs_wrapback_in, + ph_fifo_empty => wire_nl1000i_ph_fifo_empty, + ph_fifo_full => wire_nl1000i_ph_fifo_full, + rauto_speed_ena => rauto_speed_ena, + rd_clk => rx_rd_clk, + re => niOiil, + reset_pc_ptrs => reset_pc_ptrs, + reset_pc_ptrs_centrl => reset_pc_ptrs_centrl, + reset_pc_ptrs_quad_down => reset_pc_ptrs_quad_down, + reset_pc_ptrs_quad_up => reset_pc_ptrs_quad_up, + rindv_rx => rindv_rx, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + rpcs_wrapback_en => rpcs_wrapback_en, + rphfifo_regmode_rx => rphfifo_regmode_rx, + rptr_bin => wire_nl1000i_rptr_bin, + rst_rclk => wire_nli01l_dataout, + rst_wclk => wire_nli00O_dataout, + scan_mode => scan_mode, + we => nl010i, + wptr_bin => wire_nl1000i_wptr_bin, + wr_clk => rx_wr_clk + ); + + END RTL; --cycloneiv_hssi_rx_digi_rx_ctrl +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + +--synthesis_resources = lut 99 mux21 139 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_dec_chnl_top IS + PORT + ( + cascaded_8b10b_en : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data_in_valid : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + dec_ctl : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + dec_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + dec_data_valid : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + disp_err_delay : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + disp_val_delay : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + invalid_code_delay : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + ovr_undflow : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + polinv : IN STD_LOGIC; + r8b10b_dec_ibm_en : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + renpolinv : IN STD_LOGIC; + rerr_flags_sel : IN STD_LOGIC; + rlb_data : OUT STD_LOGIC_VECTOR (19 DOWNTO 0); + rrxpcsbypass_en : IN STD_LOGIC; + rst : IN STD_LOGIC; + sync_resync_delay : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + tenb_data : OUT STD_LOGIC_VECTOR (19 DOWNTO 0) + ); + END cycloneiv_hssi_rx_digi_dec_chnl_top; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_dec_chnl_top IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n0l01O43 : STD_LOGIC := '0'; + SIGNAL n0l01O44 : STD_LOGIC := '0'; + SIGNAL wire_n0l01O44_w_lg_q176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0l0li41 : STD_LOGIC := '0'; + SIGNAL n0l0li42 : STD_LOGIC := '0'; + SIGNAL n0l0lO39 : STD_LOGIC := '0'; + SIGNAL n0l0lO40 : STD_LOGIC := '0'; + SIGNAL n0li0l35 : STD_LOGIC := '0'; + SIGNAL n0li0l36 : STD_LOGIC := '0'; + SIGNAL wire_n0li0l36_w_lg_w_lg_q148w149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0li0l36_w_lg_q148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0li1i37 : STD_LOGIC := '0'; + SIGNAL n0li1i38 : STD_LOGIC := '0'; + SIGNAL n0liiO33 : STD_LOGIC := '0'; + SIGNAL n0liiO34 : STD_LOGIC := '0'; + SIGNAL wire_n0liiO34_w_lg_w_lg_q142w143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0liiO34_w_lg_q142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0liOi31 : STD_LOGIC := '0'; + SIGNAL n0liOi32 : STD_LOGIC := '0'; + SIGNAL wire_n0liOi32_w_lg_w_lg_q136w137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0liOi32_w_lg_q136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0ll0l27 : STD_LOGIC := '0'; + SIGNAL n0ll0l28 : STD_LOGIC := '0'; + SIGNAL n0ll1i29 : STD_LOGIC := '0'; + SIGNAL n0ll1i30 : STD_LOGIC := '0'; + SIGNAL wire_n0ll1i30_w_lg_w_lg_q131w132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ll1i30_w_lg_q131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0llii25 : STD_LOGIC := '0'; + SIGNAL n0llii26 : STD_LOGIC := '0'; + SIGNAL wire_n0llii26_w_lg_w_lg_q118w119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0llii26_w_lg_q118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0llll23 : STD_LOGIC := '0'; + SIGNAL n0llll24 : STD_LOGIC := '0'; + SIGNAL n0llOi21 : STD_LOGIC := '0'; + SIGNAL n0llOi22 : STD_LOGIC := '0'; + SIGNAL n0lO0l17 : STD_LOGIC := '0'; + SIGNAL n0lO0l18 : STD_LOGIC := '0'; + SIGNAL wire_n0lO0l18_w_lg_w_lg_q94w95w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lO0l18_w_lg_q94w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0lO1O19 : STD_LOGIC := '0'; + SIGNAL n0lO1O20 : STD_LOGIC := '0'; + SIGNAL n0lOiO15 : STD_LOGIC := '0'; + SIGNAL n0lOiO16 : STD_LOGIC := '0'; + SIGNAL n0lOOO13 : STD_LOGIC := '0'; + SIGNAL n0lOOO14 : STD_LOGIC := '0'; + SIGNAL wire_n0lOOO14_w_lg_w_lg_q78w79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOOO14_w_lg_q78w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O00l1 : STD_LOGIC := '0'; + SIGNAL n0O00l2 : STD_LOGIC := '0'; + SIGNAL n0O01i5 : STD_LOGIC := '0'; + SIGNAL n0O01i6 : STD_LOGIC := '0'; + SIGNAL n0O01O3 : STD_LOGIC := '0'; + SIGNAL n0O01O4 : STD_LOGIC := '0'; + SIGNAL n0O10i11 : STD_LOGIC := '0'; + SIGNAL n0O10i12 : STD_LOGIC := '0'; + SIGNAL wire_n0O10i12_w_lg_w_lg_q72w73w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O10i12_w_lg_q72w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O1ii10 : STD_LOGIC := '0'; + SIGNAL wire_n0O1ii10_w_lg_w_lg_q67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O1ii10_w_lg_q67w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0O1ii9 : STD_LOGIC := '0'; + SIGNAL n0O1ll7 : STD_LOGIC := '0'; + SIGNAL n0O1ll8 : STD_LOGIC := '0'; + SIGNAL n00O : STD_LOGIC := '0'; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1l : STD_LOGIC := '0'; + SIGNAL ni1O : STD_LOGIC := '0'; + SIGNAL niiO : STD_LOGIC := '0'; + SIGNAL nili : STD_LOGIC := '0'; + SIGNAL nilO : STD_LOGIC := '0'; + SIGNAL wire_nill_CLRN : STD_LOGIC; + SIGNAL n00i : STD_LOGIC := '0'; + SIGNAL n00l : STD_LOGIC := '0'; + SIGNAL n01i : STD_LOGIC := '0'; + SIGNAL n01l : STD_LOGIC := '0'; + SIGNAL n01O : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL n10i : STD_LOGIC := '0'; + SIGNAL n10l : STD_LOGIC := '0'; + SIGNAL n10O : STD_LOGIC := '0'; + SIGNAL n11i : STD_LOGIC := '0'; + SIGNAL n11l : STD_LOGIC := '0'; + SIGNAL n11O : STD_LOGIC := '0'; + SIGNAL n1ii : STD_LOGIC := '0'; + SIGNAL n1il : STD_LOGIC := '0'; + SIGNAL n1iO : STD_LOGIC := '0'; + SIGNAL n1li : STD_LOGIC := '0'; + SIGNAL n1ll : STD_LOGIC := '0'; + SIGNAL n1lO : STD_LOGIC := '0'; + SIGNAL n1Oi : STD_LOGIC := '0'; + SIGNAL n1Ol : STD_LOGIC := '0'; + SIGNAL n1OO : STD_LOGIC := '0'; + SIGNAL ni : STD_LOGIC := '0'; + SIGNAL ni0i : STD_LOGIC := '0'; + SIGNAL ni0l : STD_LOGIC := '0'; + SIGNAL ni0O : STD_LOGIC := '0'; + SIGNAL niii : STD_LOGIC := '0'; + SIGNAL niil : STD_LOGIC := '0'; + SIGNAL niOi : STD_LOGIC := '0'; + SIGNAL niOl : STD_LOGIC := '0'; + SIGNAL niOO : STD_LOGIC := '0'; + SIGNAL nl0i : STD_LOGIC := '0'; + SIGNAL nl0O : STD_LOGIC := '0'; + SIGNAL nl1i : STD_LOGIC := '0'; + SIGNAL nl1l : STD_LOGIC := '0'; + SIGNAL nl1O : STD_LOGIC := '0'; + SIGNAL nlO0l : STD_LOGIC := '0'; + SIGNAL nlO0O : STD_LOGIC := '0'; + SIGNAL nlOii : STD_LOGIC := '0'; + SIGNAL nlOil : STD_LOGIC := '0'; + SIGNAL nlOiO : STD_LOGIC := '0'; + SIGNAL nlOli : STD_LOGIC := '0'; + SIGNAL nlOll : STD_LOGIC := '0'; + SIGNAL nlOlO : STD_LOGIC := '0'; + SIGNAL nlOOi : STD_LOGIC := '0'; + SIGNAL nlOOl : STD_LOGIC := '0'; + SIGNAL nlOOO : STD_LOGIC := '0'; + SIGNAL wire_nlO_CLRN : STD_LOGIC; + SIGNAL wire_nlO_w_lg_nl1O97w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_nl1O64w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n000i_dataout : STD_LOGIC; + SIGNAL wire_n000l_dataout : STD_LOGIC; + SIGNAL wire_n000O_dataout : STD_LOGIC; + SIGNAL wire_n001i_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001O_dataout : STD_LOGIC; + SIGNAL wire_n00ii_dataout : STD_LOGIC; + SIGNAL wire_n00il_dataout : STD_LOGIC; + SIGNAL wire_n00iO_dataout : STD_LOGIC; + SIGNAL wire_n00li_dataout : STD_LOGIC; + SIGNAL wire_n00ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01lO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0i_w_lg_w_lg_dataout363w1002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_w_lg_dataout363w997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_w_lg_dataout363w990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_w_lg_dataout363w987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_w_lg_dataout363w890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_w_lg_dataout363w885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_w_lg_dataout363w870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_w_lg_dataout363w867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_dataout874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_dataout893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_dataout896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_w_lg_dataout363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0l_w_lg_w_lg_dataout90w975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_w_lg_dataout90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout1003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l_w_lg_dataout90w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0liO_dataout : STD_LOGIC; + SIGNAL wire_n0liO_w_lg_dataout308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lli_dataout : STD_LOGIC; + SIGNAL wire_n0lli_w_lg_dataout345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lli_w_lg_dataout319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lli_w_lg_dataout316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lli_w_lg_dataout296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lli_w_lg_dataout298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lll_dataout : STD_LOGIC; + SIGNAL wire_n0lll_w_lg_w_lg_dataout299w344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lll_w_lg_w_lg_dataout299w318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lll_w_lg_w_lg_dataout299w315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lll_w_lg_dataout295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lll_w_lg_dataout299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lll_w_lg_dataout326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0llO_dataout : STD_LOGIC; + SIGNAL wire_n0llO_w_lg_dataout293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOi_w_lg_w_lg_dataout292w294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOi_w_lg_w_lg_dataout292w335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOi_w_lg_dataout334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOi_w_lg_dataout292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOi_w_lg_dataout325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0O_w_lg_w_lg_dataout364w783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_w_lg_dataout364w777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_w_lg_dataout364w717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_w_lg_dataout364w823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_dataout847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_dataout800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_dataout794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_dataout720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O_w_lg_dataout364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl_dataout : STD_LOGIC; + SIGNAL wire_n10il_dataout : STD_LOGIC; + SIGNAL wire_n10il_w_lg_dataout381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10iO_dataout : STD_LOGIC; + SIGNAL wire_n10iO_w_lg_dataout418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10iO_w_lg_dataout392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10iO_w_lg_dataout389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10iO_w_lg_dataout369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10iO_w_lg_dataout371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10li_dataout : STD_LOGIC; + SIGNAL wire_n10li_w_lg_w_lg_dataout372w417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10li_w_lg_w_lg_dataout372w391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10li_w_lg_w_lg_dataout372w388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10li_w_lg_dataout368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10li_w_lg_dataout372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10li_w_lg_dataout399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10ll_dataout : STD_LOGIC; + SIGNAL wire_n10ll_w_lg_dataout366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10lO_dataout : STD_LOGIC; + SIGNAL wire_n10lO_w_lg_w_lg_dataout365w367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10lO_w_lg_w_lg_dataout365w408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10lO_w_lg_dataout407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10lO_w_lg_dataout365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10lO_w_lg_dataout398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n111i_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1i_w_lg_w_lg_dataout511w513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_w_lg_dataout430w542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i_w_lg_dataout508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1iii_dataout : STD_LOGIC; + SIGNAL wire_n1iil_dataout : STD_LOGIC; + SIGNAL wire_n1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1ili_dataout : STD_LOGIC; + SIGNAL wire_n1ill_dataout : STD_LOGIC; + SIGNAL wire_n1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1l_w_lg_dataout361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1i_w_lg_dataout356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1l_w_lg_dataout358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1O_w_lg_w_lg_dataout354w355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1O_w_lg_dataout359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1O_w_lg_dataout354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O_w_lg_w_lg_dataout362w873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O_w_lg_w_lg_dataout362w856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O_w_lg_dataout857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O_w_lg_dataout362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl_w_lg_dataout160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0lOl_w_lg_dataout128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni10i_dataout : STD_LOGIC; + SIGNAL wire_ni10i_w_lg_w_lg_dataout281w282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni10i_w_lg_dataout286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni10i_w_lg_dataout281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni11iO_dataout : STD_LOGIC; + SIGNAL wire_ni11iO_w_lg_w_lg_dataout104w971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni11iO_w_lg_dataout104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni11l_dataout : STD_LOGIC; + SIGNAL wire_ni11l_w_lg_dataout283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni11O_dataout : STD_LOGIC; + SIGNAL wire_ni11O_w_lg_dataout285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nii_w_lg_w_lg_dataout351w784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_dataout351w778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_dataout351w853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_w_lg_dataout351w780w781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w785w791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_dataout797w798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_w_lg_dataout351w778w779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_dataout795w796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_dataout351w780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_w_lg_w_lg_dataout351w778w779w782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_w_lg_dataout795w796w799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_w_lg_w_lg_w_lg_dataout795w796w799w802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nii_w_lg_dataout797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil_w_lg_w_lg_dataout347w831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil_w_lg_w_lg_dataout347w904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil_w_lg_dataout738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil_w_lg_dataout114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil_w_lg_dataout347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO_w_lg_w_lg_dataout348w727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_w_lg_dataout348w750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_w_lg_dataout348w908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_w_lg_dataout348w765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_w_lg_dataout348w742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_w_lg_dataout348w788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_dataout807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO00l_dataout : STD_LOGIC; + SIGNAL wire_niO00l_w_lg_dataout60w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lll_dataout : STD_LOGIC; + SIGNAL wire_nl110O_dataout : STD_LOGIC; + SIGNAL wire_nl110O_w_lg_w_lg_dataout171w680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O_w_lg_dataout171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli_w_lg_w_lg_dataout349w761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_w_lg_dataout349w921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_w_lg_dataout349w918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_w_lg_dataout349w940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_w_lg_dataout349w935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_dataout349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli_w_lg_w_lg_dataout760w762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlii_w_lg_dataout288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlil_w_lg_w_lg_dataout289w582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlil_w_lg_w_lg_dataout289w565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlil_w_lg_dataout566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlil_w_lg_dataout289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliO_w_lg_w_lg_dataout290w711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_w_lg_dataout290w706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_w_lg_dataout290w699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_w_lg_dataout290w696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_w_lg_dataout290w599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_w_lg_dataout290w594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_w_lg_dataout290w579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_w_lg_dataout290w576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_dataout583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_dataout602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_dataout605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO_w_lg_dataout290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nll_w_lg_w_lg_dataout806w808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_w_lg_dataout726w837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll_w_lg_dataout803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlli_w_lg_w_lg_dataout157w684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_w_lg_dataout157w158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlli_w_lg_dataout157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nlll_w_lg_w_lg_dataout291w488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_w_lg_dataout291w482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_w_lg_dataout291w421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_w_lg_dataout291w528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_dataout556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_dataout505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_dataout499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_dataout424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll_w_lg_dataout291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_w_lg_w_lg_dataout278w489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_dataout278w483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_dataout278w562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_w_lg_dataout278w485w486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w490w496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_dataout502w503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_w_lg_dataout278w483w484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_dataout500w501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_dataout278w485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_w_lg_w_lg_dataout278w483w484w487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_w_lg_dataout500w501w504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_w_lg_w_lg_w_lg_dataout500w501w504w507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_dataout502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01l_w_lg_dataout62w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi_w_lg_w_lg_dataout174w177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi_w_lg_w_lg_dataout274w536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi_w_lg_w_lg_dataout274w613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi_w_lg_dataout442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi_w_lg_dataout174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi_w_lg_dataout274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl_w_lg_w_lg_dataout275w431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_dataout275w454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_dataout275w617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_dataout275w469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_dataout275w446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_dataout275w493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_dataout512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_w_lg_w_lg_dataout276w649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout276w644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout276w630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout276w627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout276w465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_dataout276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_w_lg_w_lg_dataout464w466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO_dataout : STD_LOGIC; + SIGNAL wire_w_lg_w_lg_w_lg_n0llli116w120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0l00O179w180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i00i789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i00O786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i0ii804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i0il763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0illi494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0illO491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ilOi509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ilOl467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0liil145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lilO664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lilO139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lOOl81w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O11O955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O11O75w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1Ol53w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range481w792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range481w497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range481w811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range481w516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i0il757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i0ll768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i0lO774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i1ll830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0il1l535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ilOl461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iO1l472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iO1O478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iOii405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l10i332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l11l353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l1Ol280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rst8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w140w144w146w150w151w152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w140w144w146w150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w80w82w83w84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w140w144w146w150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w80w82w83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w140w144w146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w80w82w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w140w144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w80w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_n0O1li65w69w70w74w76w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n0ll0i129w133w134w138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n0O1li65w69w70w74w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_n0ll0i129w133w134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_n0O1li65w69w70w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0i00O787w790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0i0ii805w809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0illO492w495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0ilOi510w514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0ll0i129w133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0llli116w120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0lOil92w96w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n0O1li65w69w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i00O787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i01l956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i01l814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i01O815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i0ii805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i1Oi841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0i1Ol840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0il0i546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0il0l545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ilil665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ilil519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0iliO520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0illO492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ilOi510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l00O179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l0il169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l0iO170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0l0OO159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0li0i523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ll0i521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ll0i129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0ll1O522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0llli116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lO1i102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lO1l103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lOil92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0lOlO818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1iO817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1li816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1li65w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0O1OO54w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n00OiO : STD_LOGIC; + SIGNAL n00Oli : STD_LOGIC; + SIGNAL n00Oll : STD_LOGIC; + SIGNAL n00OlO : STD_LOGIC; + SIGNAL n00OOi : STD_LOGIC; + SIGNAL n00OOl : STD_LOGIC; + SIGNAL n00OOO : STD_LOGIC; + SIGNAL n0i00i : STD_LOGIC; + SIGNAL n0i00l : STD_LOGIC; + SIGNAL n0i00O : STD_LOGIC; + SIGNAL n0i01i : STD_LOGIC; + SIGNAL n0i01l : STD_LOGIC; + SIGNAL n0i01O : STD_LOGIC; + SIGNAL n0i0ii : STD_LOGIC; + SIGNAL n0i0il : STD_LOGIC; + SIGNAL n0i0iO : STD_LOGIC; + SIGNAL n0i0li : STD_LOGIC; + SIGNAL n0i0ll : STD_LOGIC; + SIGNAL n0i0lO : STD_LOGIC; + SIGNAL n0i0Oi : STD_LOGIC; + SIGNAL n0i0Ol : STD_LOGIC; + SIGNAL n0i0OO : STD_LOGIC; + SIGNAL n0i10i : STD_LOGIC; + SIGNAL n0i10l : STD_LOGIC; + SIGNAL n0i10O : STD_LOGIC; + SIGNAL n0i11i : STD_LOGIC; + SIGNAL n0i11l : STD_LOGIC; + SIGNAL n0i11O : STD_LOGIC; + SIGNAL n0i1ii : STD_LOGIC; + SIGNAL n0i1il : STD_LOGIC; + SIGNAL n0i1iO : STD_LOGIC; + SIGNAL n0i1li : STD_LOGIC; + SIGNAL n0i1ll : STD_LOGIC; + SIGNAL n0i1lO : STD_LOGIC; + SIGNAL n0i1Oi : STD_LOGIC; + SIGNAL n0i1Ol : STD_LOGIC; + SIGNAL n0i1OO : STD_LOGIC; + SIGNAL n0ii0i : STD_LOGIC; + SIGNAL n0ii0l : STD_LOGIC; + SIGNAL n0ii0O : STD_LOGIC; + SIGNAL n0ii1i : STD_LOGIC; + SIGNAL n0ii1l : STD_LOGIC; + SIGNAL n0ii1O : STD_LOGIC; + SIGNAL n0iiii : STD_LOGIC; + SIGNAL n0iiil : STD_LOGIC; + SIGNAL n0iiiO : STD_LOGIC; + SIGNAL n0iili : STD_LOGIC; + SIGNAL n0iill : STD_LOGIC; + SIGNAL n0iilO : STD_LOGIC; + SIGNAL n0iiOi : STD_LOGIC; + SIGNAL n0iiOl : STD_LOGIC; + SIGNAL n0iiOO : STD_LOGIC; + SIGNAL n0il0i : STD_LOGIC; + SIGNAL n0il0l : STD_LOGIC; + SIGNAL n0il0O : STD_LOGIC; + SIGNAL n0il1i : STD_LOGIC; + SIGNAL n0il1l : STD_LOGIC; + SIGNAL n0il1O : STD_LOGIC; + SIGNAL n0ilii : STD_LOGIC; + SIGNAL n0ilil : STD_LOGIC; + SIGNAL n0iliO : STD_LOGIC; + SIGNAL n0illi : STD_LOGIC; + SIGNAL n0illl : STD_LOGIC; + SIGNAL n0illO : STD_LOGIC; + SIGNAL n0ilOi : STD_LOGIC; + SIGNAL n0ilOl : STD_LOGIC; + SIGNAL n0ilOO : STD_LOGIC; + SIGNAL n0iO0i : STD_LOGIC; + SIGNAL n0iO0l : STD_LOGIC; + SIGNAL n0iO0O : STD_LOGIC; + SIGNAL n0iO1i : STD_LOGIC; + SIGNAL n0iO1l : STD_LOGIC; + SIGNAL n0iO1O : STD_LOGIC; + SIGNAL n0iOii : STD_LOGIC; + SIGNAL n0iOil : STD_LOGIC; + SIGNAL n0iOiO : STD_LOGIC; + SIGNAL n0iOli : STD_LOGIC; + SIGNAL n0iOll : STD_LOGIC; + SIGNAL n0iOlO : STD_LOGIC; + SIGNAL n0iOOi : STD_LOGIC; + SIGNAL n0iOOl : STD_LOGIC; + SIGNAL n0iOOO : STD_LOGIC; + SIGNAL n0l00l : STD_LOGIC; + SIGNAL n0l00O : STD_LOGIC; + SIGNAL n0l01i : STD_LOGIC; + SIGNAL n0l01l : STD_LOGIC; + SIGNAL n0l0ii : STD_LOGIC; + SIGNAL n0l0il : STD_LOGIC; + SIGNAL n0l0iO : STD_LOGIC; + SIGNAL n0l0Ol : STD_LOGIC; + SIGNAL n0l0OO : STD_LOGIC; + SIGNAL n0l10i : STD_LOGIC; + SIGNAL n0l10l : STD_LOGIC; + SIGNAL n0l10O : STD_LOGIC; + SIGNAL n0l11i : STD_LOGIC; + SIGNAL n0l11l : STD_LOGIC; + SIGNAL n0l11O : STD_LOGIC; + SIGNAL n0l1ii : STD_LOGIC; + SIGNAL n0l1il : STD_LOGIC; + SIGNAL n0l1iO : STD_LOGIC; + SIGNAL n0l1li : STD_LOGIC; + SIGNAL n0l1ll : STD_LOGIC; + SIGNAL n0l1lO : STD_LOGIC; + SIGNAL n0l1Oi : STD_LOGIC; + SIGNAL n0l1Ol : STD_LOGIC; + SIGNAL n0l1OO : STD_LOGIC; + SIGNAL n0li0i : STD_LOGIC; + SIGNAL n0li1O : STD_LOGIC; + SIGNAL n0liii : STD_LOGIC; + SIGNAL n0liil : STD_LOGIC; + SIGNAL n0lill : STD_LOGIC; + SIGNAL n0lilO : STD_LOGIC; + SIGNAL n0liOO : STD_LOGIC; + SIGNAL n0ll0i : STD_LOGIC; + SIGNAL n0ll1O : STD_LOGIC; + SIGNAL n0lliO : STD_LOGIC; + SIGNAL n0llli : STD_LOGIC; + SIGNAL n0llOO : STD_LOGIC; + SIGNAL n0lO1i : STD_LOGIC; + SIGNAL n0lO1l : STD_LOGIC; + SIGNAL n0lOii : STD_LOGIC; + SIGNAL n0lOil : STD_LOGIC; + SIGNAL n0lOll : STD_LOGIC; + SIGNAL n0lOlO : STD_LOGIC; + SIGNAL n0lOOi : STD_LOGIC; + SIGNAL n0lOOl : STD_LOGIC; + SIGNAL n0O00i : STD_LOGIC; + SIGNAL n0O01l : STD_LOGIC; + SIGNAL n0O10O : STD_LOGIC; + SIGNAL n0O11l : STD_LOGIC; + SIGNAL n0O11O : STD_LOGIC; + SIGNAL n0O1iO : STD_LOGIC; + SIGNAL n0O1li : STD_LOGIC; + SIGNAL n0O1Oi : STD_LOGIC; + SIGNAL n0O1Ol : STD_LOGIC; + SIGNAL n0O1OO : STD_LOGIC; + SIGNAL wire_w_r8b10b_dec_ibm_en_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_w_lg_w_lg_n0llli116w120w121w(0) <= wire_w_lg_w_lg_n0llli116w120w(0) AND wire_ni11iO_dataout; + wire_w_lg_w_lg_n0l00O179w180w(0) <= wire_w_lg_n0l00O179w(0) AND wire_nl110O_dataout; + wire_w_lg_n0i00i789w(0) <= n0i00i AND wire_niO_w_lg_w_lg_dataout348w788w(0); + wire_w_lg_n0i00O786w(0) <= n0i00O AND n0i00i; + wire_w_lg_n0i0ii804w(0) <= n0i0ii AND wire_nll_w_lg_dataout803w(0); + wire_w_lg_n0i0il763w(0) <= n0i0il AND wire_nli_w_lg_w_lg_dataout760w762w(0); + wire_w_lg_n0illi494w(0) <= n0illi AND wire_nlOl_w_lg_w_lg_dataout275w493w(0); + wire_w_lg_n0illO491w(0) <= n0illO AND n0illi; + wire_w_lg_n0ilOi509w(0) <= n0ilOi AND wire_n1i_w_lg_dataout508w(0); + wire_w_lg_n0ilOl467w(0) <= n0ilOl AND wire_nlOO_w_lg_w_lg_dataout464w466w(0); + wire_w_lg_n0liil145w(0) <= n0liil AND n0liii; + wire_w_lg_n0lilO664w(0) <= n0lilO AND n0ii0O; + wire_w_lg_n0lilO139w(0) <= n0lilO AND n0lill; + wire_w_lg_n0lOOl81w(0) <= n0lOOl AND n0lOOi; + wire_w_lg_n0O11O955w(0) <= n0O11O AND n00OOO; + wire_w_lg_n0O11O75w(0) <= n0O11O AND n0O11l; + wire_w_lg_n0O1Ol53w(0) <= n0O1Ol AND n0O1Oi; + wire_w_lg_w_r8b10b_dec_ibm_en_range481w792w(0) <= wire_w_r8b10b_dec_ibm_en_range481w(0) AND wire_nii_w_lg_w785w791w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range481w497w(0) <= wire_w_r8b10b_dec_ibm_en_range481w(0) AND wire_nllO_w_lg_w490w496w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range481w811w(0) <= wire_w_r8b10b_dec_ibm_en_range481w(0) AND wire_nii_w810w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range481w516w(0) <= wire_w_r8b10b_dec_ibm_en_range481w(0) AND wire_nllO_w515w(0); + wire_w_lg_n0i0il757w(0) <= NOT n0i0il; + wire_w_lg_n0i0ll768w(0) <= NOT n0i0ll; + wire_w_lg_n0i0lO774w(0) <= NOT n0i0lO; + wire_w_lg_n0i1ll830w(0) <= NOT n0i1ll; + wire_w_lg_n0il1l535w(0) <= NOT n0il1l; + wire_w_lg_n0ilOl461w(0) <= NOT n0ilOl; + wire_w_lg_n0iO1l472w(0) <= NOT n0iO1l; + wire_w_lg_n0iO1O478w(0) <= NOT n0iO1O; + wire_w_lg_n0iOii405w(0) <= NOT n0iOii; + wire_w_lg_n0l10i332w(0) <= NOT n0l10i; + wire_w_lg_n0l11l353w(0) <= NOT n0l11l; + wire_w_lg_n0l1Ol280w(0) <= NOT n0l1Ol; + wire_w_lg_rst8w(0) <= NOT rst; + wire_w_lg_w_lg_w_lg_w_lg_w_lg_w140w144w146w150w151w152w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w140w144w146w150w151w(0) OR n0li1O; + wire_w_lg_w_lg_w_lg_w_lg_w140w144w146w150w151w(0) <= wire_w_lg_w_lg_w_lg_w140w144w146w150w(0) OR n0li0i; + wire_w_lg_w_lg_w_lg_w80w82w83w84w(0) <= wire_w_lg_w_lg_w80w82w83w(0) OR n0lOll; + wire_w_lg_w_lg_w_lg_w140w144w146w150w(0) <= wire_w_lg_w_lg_w140w144w146w(0) OR wire_n0li0l36_w_lg_w_lg_q148w149w(0); + wire_w_lg_w_lg_w80w82w83w(0) <= wire_w_lg_w80w82w(0) OR n0lOlO; + wire_w_lg_w_lg_w140w144w146w(0) <= wire_w_lg_w140w144w(0) OR wire_w_lg_n0liil145w(0); + wire_w_lg_w80w82w(0) <= wire_w80w(0) OR wire_w_lg_n0lOOl81w(0); + wire_w_lg_w140w144w(0) <= wire_w140w(0) OR wire_n0liiO34_w_lg_w_lg_q142w143w(0); + wire_w80w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_n0O1li65w69w70w74w76w(0) OR wire_n0lOOO14_w_lg_w_lg_q78w79w(0); + wire_w140w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n0ll0i129w133w134w138w(0) OR wire_w_lg_n0lilO139w(0); + wire_w_lg_w_lg_w_lg_w_lg_w_lg_n0O1li65w69w70w74w76w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n0O1li65w69w70w74w(0) OR wire_w_lg_n0O11O75w(0); + wire_w_lg_w_lg_w_lg_w_lg_n0ll0i129w133w134w138w(0) <= wire_w_lg_w_lg_w_lg_n0ll0i129w133w134w(0) OR wire_n0liOi32_w_lg_w_lg_q136w137w(0); + wire_w_lg_w_lg_w_lg_w_lg_n0O1li65w69w70w74w(0) <= wire_w_lg_w_lg_w_lg_n0O1li65w69w70w(0) OR wire_n0O10i12_w_lg_w_lg_q72w73w(0); + wire_w_lg_w_lg_w_lg_n0ll0i129w133w134w(0) <= wire_w_lg_w_lg_n0ll0i129w133w(0) OR n0liOO; + wire_w_lg_w_lg_w_lg_n0O1li65w69w70w(0) <= wire_w_lg_w_lg_n0O1li65w69w(0) OR n0O10O; + wire_w_lg_w_lg_n0i00O787w790w(0) <= wire_w_lg_n0i00O787w(0) OR wire_w_lg_n0i00i789w(0); + wire_w_lg_w_lg_n0i0ii805w809w(0) <= wire_w_lg_n0i0ii805w(0) OR wire_nll_w_lg_w_lg_dataout806w808w(0); + wire_w_lg_w_lg_n0illO492w495w(0) <= wire_w_lg_n0illO492w(0) OR wire_w_lg_n0illi494w(0); + wire_w_lg_w_lg_n0ilOi510w514w(0) <= wire_w_lg_n0ilOi510w(0) OR wire_n1i_w_lg_w_lg_dataout511w513w(0); + wire_w_lg_w_lg_n0ll0i129w133w(0) <= wire_w_lg_n0ll0i129w(0) OR wire_n0ll1i30_w_lg_w_lg_q131w132w(0); + wire_w_lg_w_lg_n0llli116w120w(0) <= wire_w_lg_n0llli116w(0) OR wire_n0llii26_w_lg_w_lg_q118w119w(0); + wire_w_lg_w_lg_n0lOil92w96w(0) <= wire_w_lg_n0lOil92w(0) OR wire_n0lO0l18_w_lg_w_lg_q94w95w(0); + wire_w_lg_w_lg_n0O1li65w69w(0) <= wire_w_lg_n0O1li65w(0) OR wire_n0O1ii10_w_lg_w_lg_q67w68w(0); + wire_w_lg_n0i00O787w(0) <= n0i00O OR wire_w_lg_n0i00O786w(0); + wire_w_lg_n0i01l956w(0) <= n0i01l OR wire_w_lg_n0O11O955w(0); + wire_w_lg_n0i01l814w(0) <= n0i01l OR n0i01i; + wire_w_lg_n0i01O815w(0) <= n0i01O OR wire_w_lg_n0i01l814w(0); + wire_w_lg_n0i0ii805w(0) <= n0i0ii OR wire_w_lg_n0i0ii804w(0); + wire_w_lg_n0i1Oi841w(0) <= n0i1Oi OR wire_w_lg_n0i1Ol840w(0); + wire_w_lg_n0i1Ol840w(0) <= n0i1Ol OR n0i1ll; + wire_w_lg_n0il0i546w(0) <= n0il0i OR wire_w_lg_n0il0l545w(0); + wire_w_lg_n0il0l545w(0) <= n0il0l OR n0il1l; + wire_w_lg_n0ilil665w(0) <= n0ilil OR wire_w_lg_n0lilO664w(0); + wire_w_lg_n0ilil519w(0) <= n0ilil OR n0ilii; + wire_w_lg_n0iliO520w(0) <= n0iliO OR wire_w_lg_n0ilil519w(0); + wire_w_lg_n0illO492w(0) <= n0illO OR wire_w_lg_n0illO491w(0); + wire_w_lg_n0ilOi510w(0) <= n0ilOi OR wire_w_lg_n0ilOi509w(0); + wire_w_lg_n0l00O179w(0) <= n0l00O OR wire_nlOl_w_lg_dataout178w(0); + wire_w_lg_n0l0il169w(0) <= n0l0il OR n0l0ii; + wire_w_lg_n0l0iO170w(0) <= n0l0iO OR wire_w_lg_n0l0il169w(0); + wire_w_lg_n0l0OO159w(0) <= n0l0OO OR wire_nlli_w_lg_w_lg_dataout157w158w(0); + wire_w_lg_n0li0i523w(0) <= n0li0i OR wire_w_lg_n0ll1O522w(0); + wire_w_lg_n0ll0i521w(0) <= n0ll0i OR n0liOO; + wire_w_lg_n0ll0i129w(0) <= n0ll0i OR n0ll1O; + wire_w_lg_n0ll1O522w(0) <= n0ll1O OR wire_w_lg_n0ll0i521w(0); + wire_w_lg_n0llli116w(0) <= n0llli OR wire_niO_w_lg_dataout115w(0); + wire_w_lg_n0lO1i102w(0) <= n0lO1i OR n0llOO; + wire_w_lg_n0lO1l103w(0) <= n0lO1l OR wire_w_lg_n0lO1i102w(0); + wire_w_lg_n0lOil92w(0) <= n0lOil OR wire_n0l_w_lg_w_lg_dataout90w91w(0); + wire_w_lg_n0lOlO818w(0) <= n0lOlO OR wire_w_lg_n0O1iO817w(0); + wire_w_lg_n0O1iO817w(0) <= n0O1iO OR wire_w_lg_n0O1li816w(0); + wire_w_lg_n0O1li816w(0) <= n0O1li OR n0O10O; + wire_w_lg_n0O1li65w(0) <= n0O1li OR n0O1iO; + wire_w_lg_n0O1OO54w(0) <= n0O1OO OR wire_w_lg_n0O1Ol53w(0); + dec_ctl <= ( n0Oi & n00O); + dec_data <= ( nl1l & nl1i & niOO & niOl & niOi & nilO & nili & niiO & niil & niii & ni0O & ni0l & ni0i & ni1O & ni1l & ni1i); + dec_data_valid <= ( n0OO & n0Ol); + disp_err_delay <= ( n01O & n01l); + disp_val_delay <= ( n01i & n1OO); + invalid_code_delay <= ( n00l & n00i); + n00OiO <= (wire_n1O_dataout AND wire_n1l_dataout); + n00Oli <= wire_n1O_w_lg_w_lg_dataout362w873w(0); + n00Oll <= wire_n1O_w_lg_dataout857w(0); + n00OlO <= wire_n1O_w_lg_w_lg_dataout362w856w(0); + n00OOi <= (n0lOOl AND n00OOO); + n00OOl <= (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND wire_n1O_w_lg_w_lg_dataout362w873w(0))); + n00OOO <= wire_nii_w_lg_dataout737w(0); + n0i00i <= (wire_nll_w_lg_dataout726w(0) AND wire_nli_w_lg_dataout349w(0)); + n0i00l <= ((((((wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND (wire_n1O_dataout AND wire_n1l_dataout))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n0i1iO))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n0i1il))) OR wire_n0l_w_lg_dataout868w(0)) OR wire_n0l_w_lg_dataout871w(0)) OR wire_n0l_w_lg_dataout875w(0)); + n0i00O <= wire_niO_w_lg_w_lg_dataout348w727w(0); + n0i01i <= (n0i11i AND n0lOOi); + n0i01l <= ((n0i11i AND n00OOO) OR (n0i1lO AND n00OOO)); + n0i01O <= (n0i11i AND n0O11l); + n0i0ii <= wire_niO_w_lg_dataout723w(0); + n0i0il <= (wire_nii_w_lg_dataout848w(0) OR (wire_nii_w_lg_dataout351w(0) AND (wire_n0O_w_lg_dataout364w(0) AND (wire_n0l_w_lg_dataout90w(0) AND wire_n0i_w_lg_dataout363w(0))))); + n0i0iO <= wire_nii_w_lg_w_lg_dataout351w853w(0); + n0i0li <= wire_nii_w_lg_dataout854w(0); + n0i0ll <= ((((wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n0i10O)) OR wire_n0l_w_lg_dataout891w(0)) OR wire_n0l_w_lg_dataout894w(0)) OR wire_n0l_w_lg_dataout897w(0)); + n0i0lO <= ((((wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND wire_n1O_w_lg_w_lg_dataout362w856w(0))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND wire_n1O_w_lg_dataout857w(0)))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n0i1ii))) OR wire_n0l_w_lg_dataout886w(0)); + n0i0Oi <= (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND wire_n1O_w_lg_w_lg_dataout362w873w(0))); + n0i0Ol <= (wire_n0l_dataout AND (wire_n0i_dataout AND (wire_n1O_dataout AND wire_n1l_dataout))); + n0i0OO <= (wire_nlil_dataout AND wire_nlii_dataout); + n0i10i <= wire_niO_w_lg_dataout909w(0); + n0i10l <= wire_niO_w_lg_w_lg_dataout348w908w(0); + n0i10O <= (wire_n1O_dataout AND wire_n1l_dataout); + n0i11i <= (wire_n0l_dataout AND (wire_n0i_dataout AND (wire_n1O_dataout AND wire_n1l_dataout))); + n0i11l <= wire_niO_w_lg_dataout723w(0); + n0i11O <= wire_niO_w_lg_w_lg_dataout348w727w(0); + n0i1ii <= wire_n1O_w_lg_w_lg_dataout362w873w(0); + n0i1il <= wire_n1O_w_lg_dataout857w(0); + n0i1iO <= wire_n1O_w_lg_w_lg_dataout362w856w(0); + n0i1li <= ((((wire_nll_w_lg_dataout726w(0) AND (wire_nli_dataout AND n0i11l)) OR wire_nll_w_lg_dataout941w(0)) OR wire_nll_w_lg_dataout944w(0)) OR wire_nll_w_lg_dataout947w(0)); + n0i1ll <= (wire_ni11iO_w_lg_w_lg_dataout104w971w(0) OR (wire_ni11iO_dataout AND n0O11l)); + n0i1lO <= ((((wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n00OiO)) OR wire_n0l_w_lg_dataout1003w(0)) OR wire_n0l_w_lg_dataout894w(0)) OR wire_n0l_w_lg_dataout897w(0)); + n0i1Oi <= (wire_nii_w_lg_dataout351w(0) AND (wire_n0O_w_lg_dataout364w(0) AND (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND (wire_n1O_dataout AND wire_n1l_dataout))))); + n0i1Ol <= (wire_nii_dataout AND (wire_n0O_dataout AND wire_n0l_w_lg_dataout875w(0))); + n0i1OO <= wire_nll_w_lg_dataout725w(0); + n0ii0i <= (n0liil AND n0ii0O); + n0ii0l <= (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND wire_nlil_w_lg_w_lg_dataout289w582w(0))); + n0ii0O <= wire_nllO_w_lg_dataout441w(0); + n0ii1i <= wire_nlil_w_lg_w_lg_dataout289w582w(0); + n0ii1l <= wire_nlil_w_lg_dataout566w(0); + n0ii1O <= wire_nlil_w_lg_w_lg_dataout289w565w(0); + n0iiii <= (wire_nlli_dataout AND (wire_nliO_dataout AND (wire_nlil_dataout AND wire_nlii_dataout))); + n0iiil <= wire_nlOl_w_lg_dataout427w(0); + n0iiiO <= wire_nlOl_w_lg_w_lg_dataout275w431w(0); + n0iili <= wire_nlOl_w_lg_dataout618w(0); + n0iill <= wire_nlOl_w_lg_w_lg_dataout275w617w(0); + n0iilO <= (wire_nlil_dataout AND wire_nlii_dataout); + n0iiOi <= wire_nlil_w_lg_w_lg_dataout289w582w(0); + n0iiOl <= wire_nlil_w_lg_dataout566w(0); + n0iiOO <= wire_nlil_w_lg_w_lg_dataout289w565w(0); + n0il0i <= (wire_nllO_w_lg_dataout278w(0) AND (wire_nlll_w_lg_dataout291w(0) AND (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND (wire_nlil_dataout AND wire_nlii_dataout))))); + n0il0l <= (wire_nllO_dataout AND (wire_nlll_dataout AND wire_nlli_w_lg_dataout584w(0))); + n0il0O <= wire_n1i_w_lg_dataout429w(0); + n0il1i <= ((((wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_dataout AND n0iiil)) OR wire_n1i_w_lg_dataout650w(0)) OR wire_n1i_w_lg_dataout653w(0)) OR wire_n1i_w_lg_dataout656w(0)); + n0il1l <= (wire_nl110O_w_lg_w_lg_dataout171w680w(0) OR (wire_nl110O_dataout AND n0lill)); + n0il1O <= ((((wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0i0OO)) OR wire_nlli_w_lg_dataout712w(0)) OR wire_nlli_w_lg_dataout603w(0)) OR wire_nlli_w_lg_dataout606w(0)); + n0ilii <= (n0iiii AND n0liii); + n0ilil <= ((n0iiii AND n0ii0O) OR (n0il1O AND n0ii0O)); + n0iliO <= (n0iiii AND n0lill); + n0illi <= (wire_n1i_w_lg_dataout430w(0) AND wire_nlOO_w_lg_dataout276w(0)); + n0illl <= ((((((wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND (wire_nlil_dataout AND wire_nlii_dataout))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0iiOO))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0iiOl))) OR wire_nlli_w_lg_dataout577w(0)) OR wire_nlli_w_lg_dataout580w(0)) OR wire_nlli_w_lg_dataout584w(0)); + n0illO <= wire_nlOl_w_lg_w_lg_dataout275w431w(0); + n0ilOi <= wire_nlOl_w_lg_dataout427w(0); + n0ilOl <= (wire_nllO_w_lg_dataout557w(0) OR (wire_nllO_w_lg_dataout278w(0) AND (wire_nlll_w_lg_dataout291w(0) AND (wire_nlli_w_lg_dataout157w(0) AND wire_nliO_w_lg_dataout290w(0))))); + n0ilOO <= wire_nllO_w_lg_w_lg_dataout278w562w(0); + n0iO0i <= (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND wire_nlil_w_lg_w_lg_dataout289w582w(0))); + n0iO0l <= (wire_nlli_dataout AND (wire_nliO_dataout AND (wire_nlil_dataout AND wire_nlii_dataout))); + n0iO0O <= wire_n10lO_w_lg_w_lg_dataout365w367w(0); + n0iO1i <= wire_nllO_w_lg_dataout563w(0); + n0iO1l <= ((((wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0iilO)) OR wire_nlli_w_lg_dataout600w(0)) OR wire_nlli_w_lg_dataout603w(0)) OR wire_nlli_w_lg_dataout606w(0)); + n0iO1O <= ((((wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND wire_nlil_w_lg_w_lg_dataout289w565w(0))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND wire_nlil_w_lg_dataout566w(0)))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0iiOi))) OR wire_nlli_w_lg_dataout595w(0)); + n0iOii <= (wire_n10ll_dataout AND wire_n10li_dataout); + n0iOil <= (wire_n10ll_w_lg_dataout366w(0) AND wire_n10li_w_lg_dataout372w(0)); + n0iOiO <= (((wire_n10il_w_lg_dataout381w(0) AND ((((((wire_n10iO_w_lg_dataout371w(0) AND (wire_n10li_w_lg_dataout372w(0) AND (wire_n10lO_dataout AND wire_n10ll_dataout))) OR (wire_n10iO_w_lg_dataout371w(0) AND (wire_n10li_dataout AND n0iOlO))) OR (wire_n10iO_w_lg_dataout371w(0) AND (wire_n10li_dataout AND n0iOll))) OR wire_n10iO_w_lg_dataout389w(0)) OR wire_n10iO_w_lg_dataout392w(0)) OR wire_n10iO_w_lg_dataout369w(0))) OR (wire_n10il_dataout AND n0iOli)) AND wire_n10li_w_lg_dataout399w(0)); + n0iOli <= ((((wire_n10iO_w_lg_dataout371w(0) AND (wire_n10li_w_lg_dataout372w(0) AND wire_n10lO_w_lg_dataout407w(0))) OR (wire_n10iO_w_lg_dataout371w(0) AND (wire_n10li_w_lg_dataout372w(0) AND wire_n10lO_w_lg_w_lg_dataout365w408w(0)))) OR (wire_n10iO_w_lg_dataout371w(0) AND (wire_n10li_dataout AND n0iO0O))) OR wire_n10iO_w_lg_dataout418w(0)); + n0iOll <= wire_n10lO_w_lg_w_lg_dataout365w408w(0); + n0iOlO <= wire_n10lO_w_lg_dataout407w(0); + n0iOOi <= (wire_n10il_dataout AND ((wire_n10lO_dataout XOR wire_n10ll_dataout) AND (wire_n10li_dataout XOR wire_n10iO_dataout))); + n0iOOl <= (wire_n10il_dataout AND (wire_n10iO_w_lg_dataout371w(0) AND (wire_n10li_w_lg_dataout372w(0) AND (wire_n10lO_dataout AND wire_n10ll_dataout)))); + n0iOOO <= (wire_n1l1O_w_lg_w_lg_dataout354w355w(0) AND wire_n1l1i_w_lg_dataout356w(0)); + n0l00l <= ((((((wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_dataout427w(0))) OR (wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_dataout AND n0iill))) OR (wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_dataout AND n0iili))) OR wire_n1i_w_lg_dataout628w(0)) OR wire_n1i_w_lg_dataout631w(0)) OR wire_n1i_w_lg_dataout634w(0)); + n0l00O <= (n0il1i OR n0il0O); + n0l01i <= (wire_n10il_w_lg_dataout381w(0) AND n0iOli); + n0l01l <= (wire_n10il_dataout AND wire_n10iO_w_lg_dataout369w(0)); + n0l0ii <= (wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_w_lg_dataout275w431w(0))); + n0l0il <= ((((wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_w_lg_dataout275w617w(0))) OR (wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_dataout618w(0)))) OR (wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_dataout AND n0iiiO))) OR wire_n1i_w_lg_dataout645w(0)); + n0l0iO <= (wire_nlOl_w_lg_dataout275w(0) AND wire_nlOi_w_lg_w_lg_dataout274w613w(0)); + n0l0Ol <= (n0il1O AND n0lill); + n0l0OO <= (((wire_w_lg_n0ilil665w(0) OR (n0il1O AND n0liii)) OR n0ilii) OR n0iliO); + n0l10i <= (wire_n0llO_dataout AND wire_n0lll_dataout); + n0l10l <= (wire_n0llO_w_lg_dataout293w(0) AND wire_n0lll_w_lg_dataout299w(0)); + n0l10O <= (((wire_n0liO_w_lg_dataout308w(0) AND ((((((wire_n0lli_w_lg_dataout298w(0) AND (wire_n0lll_w_lg_dataout299w(0) AND (wire_n0lOi_dataout AND wire_n0llO_dataout))) OR (wire_n0lli_w_lg_dataout298w(0) AND (wire_n0lll_dataout AND n0l1iO))) OR (wire_n0lli_w_lg_dataout298w(0) AND (wire_n0lll_dataout AND n0l1il))) OR wire_n0lli_w_lg_dataout316w(0)) OR wire_n0lli_w_lg_dataout319w(0)) OR wire_n0lli_w_lg_dataout296w(0))) OR (wire_n0liO_dataout AND n0l1ii)) AND wire_n0lll_w_lg_dataout326w(0)); + n0l11i <= (wire_nii_w_lg_dataout351w(0) AND n0l01l); + n0l11l <= (wire_niO_dataout XOR wire_nil_dataout); + n0l11O <= wire_n0lOi_w_lg_w_lg_dataout292w294w(0); + n0l1ii <= ((((wire_n0lli_w_lg_dataout298w(0) AND (wire_n0lll_w_lg_dataout299w(0) AND wire_n0lOi_w_lg_dataout334w(0))) OR (wire_n0lli_w_lg_dataout298w(0) AND (wire_n0lll_w_lg_dataout299w(0) AND wire_n0lOi_w_lg_w_lg_dataout292w335w(0)))) OR (wire_n0lli_w_lg_dataout298w(0) AND (wire_n0lll_dataout AND n0l11O))) OR wire_n0lli_w_lg_dataout345w(0)); + n0l1il <= wire_n0lOi_w_lg_w_lg_dataout292w335w(0); + n0l1iO <= wire_n0lOi_w_lg_dataout334w(0); + n0l1li <= (wire_n0liO_dataout AND ((wire_n0lOi_dataout XOR wire_n0llO_dataout) AND (wire_n0lll_dataout XOR wire_n0lli_dataout))); + n0l1ll <= (wire_n0liO_dataout AND (wire_n0lli_w_lg_dataout298w(0) AND (wire_n0lll_w_lg_dataout299w(0) AND (wire_n0lOi_dataout AND wire_n0llO_dataout)))); + n0l1lO <= (wire_ni10i_w_lg_w_lg_dataout281w282w(0) AND wire_ni11l_w_lg_dataout283w(0)); + n0l1Oi <= (wire_nllO_w_lg_dataout278w(0) AND n0O1OO); + n0l1Ol <= (wire_nlOl_dataout XOR wire_nlOi_dataout); + n0l1OO <= (wire_n1l1O_w_lg_dataout359w(0) AND wire_n1l1i_w_lg_dataout356w(0)); + n0li0i <= (n0ii0l AND n0ii0O); + n0li1O <= (wire_nlli_dataout AND n0ii0i); + n0liii <= (wire_nllO_w_lg_w_lg_dataout278w562w(0) OR wire_nllO_w_lg_dataout563w(0)); + n0liil <= ((((wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND wire_nlil_w_lg_w_lg_dataout289w565w(0))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND wire_nlil_w_lg_dataout566w(0)))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0ii1i))) OR wire_nlli_w_lg_dataout707w(0)); + n0lill <= (wire_nllO_w_lg_dataout278w(0) AND wire_nlll_w_lg_dataout291w(0)); + n0lilO <= ((((((wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_w_lg_dataout290w(0) AND (wire_nlil_dataout AND wire_nlii_dataout))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0ii1O))) OR (wire_nlli_w_lg_dataout157w(0) AND (wire_nliO_dataout AND n0ii1l))) OR wire_nlli_w_lg_dataout697w(0)) OR wire_nlli_w_lg_dataout700w(0)) OR wire_nlli_w_lg_dataout584w(0)); + n0liOO <= (n0liil AND n0lill); + n0ll0i <= (n0ii0l AND n0lill); + n0ll1O <= (n0ii0l AND n0liii); + n0lliO <= ((((((wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_dataout723w(0))) OR (wire_nll_w_lg_dataout726w(0) AND (wire_nli_dataout AND n0i10l))) OR (wire_nll_w_lg_dataout726w(0) AND (wire_nli_dataout AND n0i10i))) OR wire_nll_w_lg_dataout919w(0)) OR wire_nll_w_lg_dataout922w(0)) OR wire_nll_w_lg_dataout925w(0)); + n0llli <= (n0i1li OR n0i1OO); + n0llOO <= (wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_w_lg_dataout348w727w(0))); + n0lO1i <= ((((wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_w_lg_dataout348w908w(0))) OR (wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_dataout909w(0)))) OR (wire_nll_w_lg_dataout726w(0) AND (wire_nli_dataout AND n0i11O))) OR wire_nll_w_lg_dataout936w(0)); + n0lO1l <= (wire_niO_w_lg_dataout348w(0) AND wire_nil_w_lg_w_lg_dataout347w904w(0)); + n0lOii <= (n0i1lO AND n0O11l); + n0lOil <= (((wire_w_lg_n0i01l956w(0) OR (n0i1lO AND n0lOOi)) OR n0i01i) OR n0i01O); + n0lOll <= (wire_n0l_dataout AND n00OOi); + n0lOlO <= (n00OOl AND n00OOO); + n0lOOi <= (wire_nii_w_lg_w_lg_dataout351w853w(0) OR wire_nii_w_lg_dataout854w(0)); + n0lOOl <= ((((wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND wire_n1O_w_lg_w_lg_dataout362w856w(0))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND wire_n1O_w_lg_dataout857w(0)))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n00Oli))) OR wire_n0l_w_lg_dataout998w(0)); + n0O00i <= ((renpolinv OR rerr_flags_sel) OR (NOT (n0O00l2 XOR n0O00l1))); + n0O01l <= '1'; + n0O10O <= (n0lOOl AND n0O11l); + n0O11l <= (wire_nii_w_lg_dataout351w(0) AND wire_n0O_w_lg_dataout364w(0)); + n0O11O <= ((((((wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_w_lg_dataout363w(0) AND (wire_n1O_dataout AND wire_n1l_dataout))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n00OlO))) OR (wire_n0l_w_lg_dataout90w(0) AND (wire_n0i_dataout AND n00Oll))) OR wire_n0l_w_lg_dataout988w(0)) OR wire_n0l_w_lg_dataout991w(0)) OR wire_n0l_w_lg_dataout875w(0)); + n0O1iO <= (n00OOl AND n0lOOi); + n0O1li <= (n00OOl AND n0O11l); + n0O1Oi <= (wire_ni10i_w_lg_dataout286w(0) AND wire_ni11l_w_lg_dataout283w(0)); + n0O1Ol <= (wire_n0liO_w_lg_dataout308w(0) AND n0l1ii); + n0O1OO <= (wire_n0liO_dataout AND wire_n0lli_w_lg_dataout296w(0)); + ovr_undflow <= ( n1lO & n1ll & n1li & n1iO); + rlb_data <= ( wire_n1i_dataout & wire_nlOO_dataout & wire_nlOl_dataout & wire_nlOi_dataout & wire_nllO_dataout & wire_nlll_dataout & wire_nlli_dataout & wire_nliO_dataout & wire_nlil_dataout & wire_nlii_dataout & wire_nll_dataout & wire_nli_dataout & wire_niO_dataout & wire_nil_dataout & wire_nii_dataout & wire_n0O_dataout & wire_n0l_dataout & wire_n0i_dataout & wire_n1O_dataout & wire_n1l_dataout); + sync_resync_delay <= ( n1Ol & n1Oi); + tenb_data <= ( wire_nlO0i_dataout & wire_nlO1O_dataout & wire_nlO1l_dataout & wire_nlO1i_dataout & wire_nllOO_dataout & wire_nllOl_dataout & wire_nllOi_dataout & wire_nlllO_dataout & wire_nllll_dataout & wire_nllli_dataout & wire_nlliO_dataout & wire_nllil_dataout & wire_nllii_dataout & wire_nll0O_dataout & wire_nll0l_dataout & wire_nll0i_dataout & wire_nll1O_dataout & wire_nll1l_dataout & wire_nll1i_dataout & wire_nliOO_dataout); + wire_w_r8b10b_dec_ibm_en_range481w(0) <= r8b10b_dec_ibm_en(1); + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0l01O43 <= n0l01O44; + END IF; + if (now = 0 ns) then + n0l01O43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0l01O44 <= n0l01O43; + END IF; + END PROCESS; + wire_n0l01O44_w_lg_q176w(0) <= n0l01O44 XOR n0l01O43; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0l0li41 <= n0l0li42; + END IF; + if (now = 0 ns) then + n0l0li41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0l0li42 <= n0l0li41; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0l0lO39 <= n0l0lO40; + END IF; + if (now = 0 ns) then + n0l0lO39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0l0lO40 <= n0l0lO39; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0li0l35 <= n0li0l36; + END IF; + if (now = 0 ns) then + n0li0l35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0li0l36 <= n0li0l35; + END IF; + END PROCESS; + wire_n0li0l36_w_lg_w_lg_q148w149w(0) <= NOT wire_n0li0l36_w_lg_q148w(0); + wire_n0li0l36_w_lg_q148w(0) <= n0li0l36 XOR n0li0l35; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0li1i37 <= n0li1i38; + END IF; + if (now = 0 ns) then + n0li1i37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0li1i38 <= n0li1i37; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0liiO33 <= n0liiO34; + END IF; + if (now = 0 ns) then + n0liiO33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0liiO34 <= n0liiO33; + END IF; + END PROCESS; + wire_n0liiO34_w_lg_w_lg_q142w143w(0) <= NOT wire_n0liiO34_w_lg_q142w(0); + wire_n0liiO34_w_lg_q142w(0) <= n0liiO34 XOR n0liiO33; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0liOi31 <= n0liOi32; + END IF; + if (now = 0 ns) then + n0liOi31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0liOi32 <= n0liOi31; + END IF; + END PROCESS; + wire_n0liOi32_w_lg_w_lg_q136w137w(0) <= NOT wire_n0liOi32_w_lg_q136w(0); + wire_n0liOi32_w_lg_q136w(0) <= n0liOi32 XOR n0liOi31; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0ll0l27 <= n0ll0l28; + END IF; + if (now = 0 ns) then + n0ll0l27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0ll0l28 <= n0ll0l27; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0ll1i29 <= n0ll1i30; + END IF; + if (now = 0 ns) then + n0ll1i29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0ll1i30 <= n0ll1i29; + END IF; + END PROCESS; + wire_n0ll1i30_w_lg_w_lg_q131w132w(0) <= NOT wire_n0ll1i30_w_lg_q131w(0); + wire_n0ll1i30_w_lg_q131w(0) <= n0ll1i30 XOR n0ll1i29; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0llii25 <= n0llii26; + END IF; + if (now = 0 ns) then + n0llii25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0llii26 <= n0llii25; + END IF; + END PROCESS; + wire_n0llii26_w_lg_w_lg_q118w119w(0) <= NOT wire_n0llii26_w_lg_q118w(0); + wire_n0llii26_w_lg_q118w(0) <= n0llii26 XOR n0llii25; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0llll23 <= n0llll24; + END IF; + if (now = 0 ns) then + n0llll23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0llll24 <= n0llll23; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0llOi21 <= n0llOi22; + END IF; + if (now = 0 ns) then + n0llOi21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0llOi22 <= n0llOi21; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lO0l17 <= n0lO0l18; + END IF; + if (now = 0 ns) then + n0lO0l17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lO0l18 <= n0lO0l17; + END IF; + END PROCESS; + wire_n0lO0l18_w_lg_w_lg_q94w95w(0) <= NOT wire_n0lO0l18_w_lg_q94w(0); + wire_n0lO0l18_w_lg_q94w(0) <= n0lO0l18 XOR n0lO0l17; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lO1O19 <= n0lO1O20; + END IF; + if (now = 0 ns) then + n0lO1O19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lO1O20 <= n0lO1O19; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOiO15 <= n0lOiO16; + END IF; + if (now = 0 ns) then + n0lOiO15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOiO16 <= n0lOiO15; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOO13 <= n0lOOO14; + END IF; + if (now = 0 ns) then + n0lOOO13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0lOOO14 <= n0lOOO13; + END IF; + END PROCESS; + wire_n0lOOO14_w_lg_w_lg_q78w79w(0) <= NOT wire_n0lOOO14_w_lg_q78w(0); + wire_n0lOOO14_w_lg_q78w(0) <= n0lOOO14 XOR n0lOOO13; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O00l1 <= n0O00l2; + END IF; + if (now = 0 ns) then + n0O00l1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O00l2 <= n0O00l1; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O01i5 <= n0O01i6; + END IF; + if (now = 0 ns) then + n0O01i5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O01i6 <= n0O01i5; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O01O3 <= n0O01O4; + END IF; + if (now = 0 ns) then + n0O01O3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O01O4 <= n0O01O3; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10i11 <= n0O10i12; + END IF; + if (now = 0 ns) then + n0O10i11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O10i12 <= n0O10i11; + END IF; + END PROCESS; + wire_n0O10i12_w_lg_w_lg_q72w73w(0) <= NOT wire_n0O10i12_w_lg_q72w(0); + wire_n0O10i12_w_lg_q72w(0) <= n0O10i12 XOR n0O10i11; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1ii10 <= n0O1ii9; + END IF; + END PROCESS; + wire_n0O1ii10_w_lg_w_lg_q67w68w(0) <= NOT wire_n0O1ii10_w_lg_q67w(0); + wire_n0O1ii10_w_lg_q67w(0) <= n0O1ii10 XOR n0O1ii9; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1ii9 <= n0O1ii10; + END IF; + if (now = 0 ns) then + n0O1ii9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1ll7 <= n0O1ll8; + END IF; + if (now = 0 ns) then + n0O1ll7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0O1ll8 <= n0O1ll7; + END IF; + END PROCESS; + PROCESS (clk_2, rst, wire_nill_CLRN) + BEGIN + IF (rst = '1') THEN + n00O <= '1'; + n0Oi <= '1'; + ni1i <= '1'; + ni1l <= '1'; + ni1O <= '1'; + niiO <= '1'; + nili <= '1'; + nilO <= '1'; + ELSIF (wire_nill_CLRN = '0') THEN + n00O <= '0'; + n0Oi <= '0'; + ni1i <= '0'; + ni1l <= '0'; + ni1O <= '0'; + niiO <= '0'; + nili <= '0'; + nilO <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n00O <= (n0l01l OR (n0l01i AND n0l1OO)); + n0Oi <= (wire_w_lg_n0O1OO54w(0) OR (NOT (n0O1ll8 XOR n0O1ll7))); + ni1i <= wire_nlOllO_dataout; + ni1l <= wire_nlOlll_dataout; + ni1O <= wire_nlOlli_dataout; + niiO <= wire_n01Oi_dataout; + nili <= wire_n01lO_dataout; + nilO <= wire_n01ll_dataout; + END IF; + if (now = 0 ns) then + n00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nili <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nilO <= '1' after 1 ps; + end if; + END PROCESS; + wire_nill_CLRN <= (n0O01i6 XOR n0O01i5); + PROCESS (clk_2, wire_nlO_CLRN) + BEGIN + IF (wire_nlO_CLRN = '0') THEN + n00i <= '0'; + n00l <= '0'; + n01i <= '0'; + n01l <= '0'; + n01O <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + n10i <= '0'; + n10l <= '0'; + n10O <= '0'; + n11i <= '0'; + n11l <= '0'; + n11O <= '0'; + n1ii <= '0'; + n1il <= '0'; + n1iO <= '0'; + n1li <= '0'; + n1ll <= '0'; + n1lO <= '0'; + n1Oi <= '0'; + n1Ol <= '0'; + n1OO <= '0'; + ni <= '0'; + ni0i <= '0'; + ni0l <= '0'; + ni0O <= '0'; + niii <= '0'; + niil <= '0'; + niOi <= '0'; + niOl <= '0'; + niOO <= '0'; + nl0i <= '0'; + nl0O <= '0'; + nl1i <= '0'; + nl1l <= '0'; + nl1O <= '0'; + nlO0l <= '0'; + nlO0O <= '0'; + nlOii <= '0'; + nlOil <= '0'; + nlOiO <= '0'; + nlOli <= '0'; + nlOll <= '0'; + nlOlO <= '0'; + nlOOi <= '0'; + nlOOl <= '0'; + nlOOO <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n00i <= wire_n0lO_dataout; + n00l <= wire_n0ll_dataout; + n01i <= wire_n0ii_dataout; + n01l <= wire_n0li_dataout; + n01O <= wire_n0iO_dataout; + n0Ol <= data_in_valid(0); + n0OO <= data_in_valid(1); + n10i <= data_in(21); + n10l <= data_in(22); + n10O <= data_in(23); + n11i <= data_in(18); + n11l <= data_in(19); + n11O <= data_in(20); + n1ii <= data_in(24); + n1il <= data_in(25); + n1iO <= data_in(14); + n1li <= data_in(15); + n1ll <= data_in(30); + n1lO <= data_in(31); + n1Oi <= data_in(11); + n1Ol <= data_in(27); + n1OO <= wire_n0il_dataout; + ni <= (renpolinv AND polinv); + ni0i <= wire_nlOliO_dataout; + ni0l <= wire_nlOlil_dataout; + ni0O <= wire_n1i0i_dataout; + niii <= wire_n1i1O_dataout; + niil <= wire_n1i1l_dataout; + niOi <= wire_n01li_dataout; + niOl <= wire_n01iO_dataout; + niOO <= wire_n0O0l_dataout; + nl0i <= ni; + nl0O <= data_in(0); + nl1i <= wire_n0O0i_dataout; + nl1l <= wire_n0O1O_dataout; + nl1O <= wire_nl0l_dataout; + nlO0l <= data_in(1); + nlO0O <= data_in(2); + nlOii <= data_in(3); + nlOil <= data_in(4); + nlOiO <= data_in(5); + nlOli <= data_in(6); + nlOll <= data_in(7); + nlOlO <= data_in(8); + nlOOi <= data_in(9); + nlOOl <= data_in(16); + nlOOO <= data_in(17); + END IF; + END PROCESS; + wire_nlO_CLRN <= ((n0O01O4 XOR n0O01O3) AND wire_w_lg_rst8w(0)); + wire_nlO_w_lg_nl1O97w(0) <= nl1O AND wire_w_lg_w_lg_n0lOil92w96w(0); + wire_nlO_w_lg_nl1O64w(0) <= NOT nl1O; + wire_n000i_dataout <= wire_n00OO_dataout WHEN n0l1li = '1' ELSE wire_n00iO_dataout; + wire_n000l_dataout <= wire_n0i1i_dataout WHEN n0l1li = '1' ELSE wire_n00li_dataout; + wire_n000O_dataout <= wire_n0i1i_dataout WHEN n0l1li = '1' ELSE wire_n00ll_dataout; + wire_n001i_dataout <= wire_n000O_dataout AND NOT(n0l1ll); + wire_n001l_dataout <= wire_n00ii_dataout AND NOT(n0l1ll); + wire_n001O_dataout <= wire_n00il_dataout AND NOT(n0l1ll); + wire_n00ii_dataout <= wire_n0i1i_dataout WHEN n0l1li = '1' ELSE wire_n00lO_dataout; + wire_n00il_dataout <= wire_n0i1i_dataout WHEN n0l1li = '1' ELSE wire_n00Oi_dataout; + wire_n00iO_dataout <= wire_nlll_dataout WHEN n0l10O = '1' ELSE n0O1Ol; + wire_n00li_dataout <= wire_nlli_dataout WHEN n0l10O = '1' ELSE wire_n0lli_w_lg_dataout298w(0); + wire_n00ll_dataout <= wire_nliO_dataout WHEN n0l10O = '1' ELSE wire_n0lll_w_lg_dataout299w(0); + wire_n00lO_dataout <= wire_nlil_dataout WHEN n0l10O = '1' ELSE wire_n0llO_w_lg_dataout293w(0); + wire_n00Oi_dataout <= wire_nlii_dataout WHEN n0l10O = '1' ELSE wire_n0lOi_w_lg_dataout292w(0); + wire_n00OO_dataout <= wire_n0i1l_dataout AND NOT(n0l10l); + wire_n01iO_dataout <= wire_n01Ol_dataout OR n0O1OO; + wire_n01li_dataout <= wire_n01OO_dataout OR n0O1OO; + wire_n01ll_dataout <= wire_n001i_dataout OR n0O1OO; + wire_n01lO_dataout <= wire_n001l_dataout AND NOT(n0O1OO); + wire_n01Oi_dataout <= wire_n001O_dataout AND NOT(n0O1OO); + wire_n01Ol_dataout <= wire_n000i_dataout OR n0l1ll; + wire_n01OO_dataout <= wire_n000l_dataout OR n0l1ll; + wire_n0i_dataout <= (NOT data_in(2)) WHEN nl0i = '1' ELSE data_in(2); + wire_n0i_w_lg_w_lg_dataout363w1002w(0) <= wire_n0i_w_lg_dataout363w(0) AND n00OiO; + wire_n0i_w_lg_w_lg_dataout363w997w(0) <= wire_n0i_w_lg_dataout363w(0) AND n00Oli; + wire_n0i_w_lg_w_lg_dataout363w990w(0) <= wire_n0i_w_lg_dataout363w(0) AND n00Oll; + wire_n0i_w_lg_w_lg_dataout363w987w(0) <= wire_n0i_w_lg_dataout363w(0) AND n00OlO; + wire_n0i_w_lg_w_lg_dataout363w890w(0) <= wire_n0i_w_lg_dataout363w(0) AND n0i10O; + wire_n0i_w_lg_w_lg_dataout363w885w(0) <= wire_n0i_w_lg_dataout363w(0) AND n0i1ii; + wire_n0i_w_lg_w_lg_dataout363w870w(0) <= wire_n0i_w_lg_dataout363w(0) AND n0i1il; + wire_n0i_w_lg_w_lg_dataout363w867w(0) <= wire_n0i_w_lg_dataout363w(0) AND n0i1iO; + wire_n0i_w_lg_dataout874w(0) <= wire_n0i_dataout AND wire_n1O_w_lg_w_lg_dataout362w873w(0); + wire_n0i_w_lg_dataout893w(0) <= wire_n0i_dataout AND wire_n1O_w_lg_w_lg_dataout362w856w(0); + wire_n0i_w_lg_dataout896w(0) <= wire_n0i_dataout AND wire_n1O_w_lg_dataout857w(0); + wire_n0i_w_lg_dataout363w(0) <= NOT wire_n0i_dataout; + wire_n0i1i_dataout <= wire_w_lg_n0l10i332w(0) AND NOT(n0l10l); + wire_n0i1l_dataout <= (NOT (wire_n0llO_dataout AND wire_n0lll_w_lg_dataout299w(0))) OR n0l10i; + wire_n0ii_dataout <= wire_nl0lll_dataout WHEN n0O00i = '1' ELSE data_in(29); + wire_n0il_dataout <= wire_ni0lOl_dataout WHEN n0O00i = '1' ELSE data_in(13); + wire_n0iO_dataout <= ((((((wire_ni0lOl_w_lg_dataout128w(0) AND wire_w_lg_w_lg_w_lg_w_lg_w_lg_w140w144w146w150w151w152w(0)) AND (n0li1i38 XOR n0li1i37)) OR (wire_ni0lOl_w_lg_dataout160w(0) AND (n0l0lO40 XOR n0l0lO39))) OR (NOT (n0l0li42 XOR n0l0li41))) OR (wire_w_lg_n0l0iO170w(0) AND wire_nl110O_w_lg_dataout171w(0))) OR wire_w_lg_w_lg_n0l00O179w180w(0)) WHEN n0O00i = '1' ELSE data_in(28); + wire_n0l_dataout <= (NOT data_in(3)) WHEN nl0i = '1' ELSE data_in(3); + wire_n0l_w_lg_w_lg_dataout90w975w(0) <= wire_n0l_w_lg_dataout90w(0) AND n00OOi; + wire_n0l_w_lg_w_lg_dataout90w91w(0) <= wire_n0l_w_lg_dataout90w(0) AND n0lOii; + wire_n0l_w_lg_dataout1003w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w1002w(0); + wire_n0l_w_lg_dataout998w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w997w(0); + wire_n0l_w_lg_dataout991w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w990w(0); + wire_n0l_w_lg_dataout988w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w987w(0); + wire_n0l_w_lg_dataout891w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w890w(0); + wire_n0l_w_lg_dataout886w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w885w(0); + wire_n0l_w_lg_dataout871w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w870w(0); + wire_n0l_w_lg_dataout868w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_w_lg_dataout363w867w(0); + wire_n0l_w_lg_dataout875w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_dataout874w(0); + wire_n0l_w_lg_dataout894w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_dataout893w(0); + wire_n0l_w_lg_dataout897w(0) <= wire_n0l_dataout AND wire_n0i_w_lg_dataout896w(0); + wire_n0l_w_lg_dataout846w(0) <= wire_n0l_dataout AND wire_n0i_dataout; + wire_n0l_w_lg_dataout90w(0) <= NOT wire_n0l_dataout; + wire_n0li_dataout <= ((((((wire_nlO_w_lg_nl1O64w(0) AND (wire_w_lg_w_lg_w_lg_w80w82w83w84w(0) OR (NOT (n0lOiO16 XOR n0lOiO15)))) OR (wire_nlO_w_lg_nl1O97w(0) AND (n0lO1O20 XOR n0lO1O19))) OR ((wire_w_lg_n0lO1l103w(0) AND wire_ni11iO_w_lg_dataout104w(0)) AND (n0llOi22 XOR n0llOi21))) OR (NOT (n0llll24 XOR n0llll23))) OR wire_w_lg_w_lg_w_lg_n0llli116w120w121w(0)) OR (NOT (n0ll0l28 XOR n0ll0l27))) WHEN n0O00i = '1' ELSE data_in(12); + wire_n0liO_dataout <= wire_nlll_dataout WHEN wire_nllO_dataout = '1' ELSE wire_nlll_w_lg_dataout291w(0); + wire_n0liO_w_lg_dataout308w(0) <= NOT wire_n0liO_dataout; + wire_n0ll_dataout <= wire_nlO01l_w_lg_dataout62w(0) WHEN n0O00i = '1' ELSE data_in(26); + wire_n0lli_dataout <= wire_nlli_dataout WHEN wire_nllO_dataout = '1' ELSE wire_nlli_w_lg_dataout157w(0); + wire_n0lli_w_lg_dataout345w(0) <= wire_n0lli_dataout AND wire_n0lll_w_lg_w_lg_dataout299w344w(0); + wire_n0lli_w_lg_dataout319w(0) <= wire_n0lli_dataout AND wire_n0lll_w_lg_w_lg_dataout299w318w(0); + wire_n0lli_w_lg_dataout316w(0) <= wire_n0lli_dataout AND wire_n0lll_w_lg_w_lg_dataout299w315w(0); + wire_n0lli_w_lg_dataout296w(0) <= wire_n0lli_dataout AND wire_n0lll_w_lg_dataout295w(0); + wire_n0lli_w_lg_dataout298w(0) <= NOT wire_n0lli_dataout; + wire_n0lll_dataout <= wire_nliO_dataout WHEN wire_nllO_dataout = '1' ELSE wire_nliO_w_lg_dataout290w(0); + wire_n0lll_w_lg_w_lg_dataout299w344w(0) <= wire_n0lll_w_lg_dataout299w(0) AND n0l11O; + wire_n0lll_w_lg_w_lg_dataout299w318w(0) <= wire_n0lll_w_lg_dataout299w(0) AND n0l1il; + wire_n0lll_w_lg_w_lg_dataout299w315w(0) <= wire_n0lll_w_lg_dataout299w(0) AND n0l1iO; + wire_n0lll_w_lg_dataout295w(0) <= wire_n0lll_dataout AND wire_n0lOi_w_lg_w_lg_dataout292w294w(0); + wire_n0lll_w_lg_dataout299w(0) <= NOT wire_n0lll_dataout; + wire_n0lll_w_lg_dataout326w(0) <= wire_n0lll_dataout OR wire_n0lOi_w_lg_dataout325w(0); + wire_n0llO_dataout <= wire_nlil_dataout WHEN wire_nllO_dataout = '1' ELSE wire_nlil_w_lg_dataout289w(0); + wire_n0llO_w_lg_dataout293w(0) <= NOT wire_n0llO_dataout; + wire_n0lO_dataout <= wire_niO00l_w_lg_dataout60w(0) WHEN n0O00i = '1' ELSE data_in(10); + wire_n0lOi_dataout <= wire_nlii_dataout WHEN wire_nllO_dataout = '1' ELSE wire_nlii_w_lg_dataout288w(0); + wire_n0lOi_w_lg_w_lg_dataout292w294w(0) <= wire_n0lOi_w_lg_dataout292w(0) AND wire_n0llO_w_lg_dataout293w(0); + wire_n0lOi_w_lg_w_lg_dataout292w335w(0) <= wire_n0lOi_w_lg_dataout292w(0) AND wire_n0llO_dataout; + wire_n0lOi_w_lg_dataout334w(0) <= wire_n0lOi_dataout AND wire_n0llO_w_lg_dataout293w(0); + wire_n0lOi_w_lg_dataout292w(0) <= NOT wire_n0lOi_dataout; + wire_n0lOi_w_lg_dataout325w(0) <= wire_n0lOi_dataout OR wire_n0llO_dataout; + wire_n0O_dataout <= (NOT data_in(4)) WHEN nl0i = '1' ELSE data_in(4); + wire_n0O_w_lg_w_lg_dataout364w783w(0) <= wire_n0O_w_lg_dataout364w(0) AND wire_n0l_w_lg_dataout90w(0); + wire_n0O_w_lg_w_lg_dataout364w777w(0) <= wire_n0O_w_lg_dataout364w(0) AND n0i00l; + wire_n0O_w_lg_w_lg_dataout364w717w(0) <= wire_n0O_w_lg_dataout364w(0) AND n0i0lO; + wire_n0O_w_lg_w_lg_dataout364w823w(0) <= wire_n0O_w_lg_dataout364w(0) AND n0lOOl; + wire_n0O_w_lg_dataout847w(0) <= wire_n0O_dataout AND wire_n0l_w_lg_dataout846w(0); + wire_n0O_w_lg_dataout800w(0) <= wire_n0O_dataout AND wire_n0l_dataout; + wire_n0O_w_lg_dataout794w(0) <= wire_n0O_dataout AND n0i00l; + wire_n0O_w_lg_dataout720w(0) <= wire_n0O_dataout AND n0i0ll; + wire_n0O_w_lg_dataout364w(0) <= NOT wire_n0O_dataout; + wire_n0O0i_dataout <= wire_n0Oii_dataout AND NOT(n0l1lO); + wire_n0O0l_dataout <= wire_n0Oil_dataout AND NOT(n0l1lO); + wire_n0O0O_dataout <= wire_n0OiO_dataout OR n0O1Oi; + wire_n0O1O_dataout <= wire_n0O0O_dataout AND NOT(n0l1lO); + wire_n0Oii_dataout <= wire_n0Oli_dataout OR n0O1Oi; + wire_n0Oil_dataout <= wire_n0Oll_dataout OR n0O1Oi; + wire_n0OiO_dataout <= wire_ni11l_dataout WHEN wire_w_lg_n0l1Ol280w(0) = '1' ELSE wire_n0OlO_dataout; + wire_n0Oli_dataout <= wire_ni11O_dataout WHEN wire_w_lg_n0l1Ol280w(0) = '1' ELSE wire_n0OOi_dataout; + wire_n0Oll_dataout <= wire_ni10i_dataout WHEN wire_w_lg_n0l1Ol280w(0) = '1' ELSE wire_n0OOl_dataout; + wire_n0OlO_dataout <= wire_nlOO_w_lg_dataout276w(0) WHEN n0l1Oi = '1' ELSE wire_nlOO_dataout; + wire_n0OOi_dataout <= wire_nlOl_w_lg_dataout275w(0) WHEN n0l1Oi = '1' ELSE wire_nlOl_dataout; + wire_n0OOl_dataout <= wire_nlOi_w_lg_dataout274w(0) WHEN n0l1Oi = '1' ELSE wire_nlOi_dataout; + wire_n10il_dataout <= wire_n0O_dataout WHEN wire_nii_dataout = '1' ELSE wire_n0O_w_lg_dataout364w(0); + wire_n10il_w_lg_dataout381w(0) <= NOT wire_n10il_dataout; + wire_n10iO_dataout <= wire_n0l_dataout WHEN wire_nii_dataout = '1' ELSE wire_n0l_w_lg_dataout90w(0); + wire_n10iO_w_lg_dataout418w(0) <= wire_n10iO_dataout AND wire_n10li_w_lg_w_lg_dataout372w417w(0); + wire_n10iO_w_lg_dataout392w(0) <= wire_n10iO_dataout AND wire_n10li_w_lg_w_lg_dataout372w391w(0); + wire_n10iO_w_lg_dataout389w(0) <= wire_n10iO_dataout AND wire_n10li_w_lg_w_lg_dataout372w388w(0); + wire_n10iO_w_lg_dataout369w(0) <= wire_n10iO_dataout AND wire_n10li_w_lg_dataout368w(0); + wire_n10iO_w_lg_dataout371w(0) <= NOT wire_n10iO_dataout; + wire_n10li_dataout <= wire_n0i_dataout WHEN wire_nii_dataout = '1' ELSE wire_n0i_w_lg_dataout363w(0); + wire_n10li_w_lg_w_lg_dataout372w417w(0) <= wire_n10li_w_lg_dataout372w(0) AND n0iO0O; + wire_n10li_w_lg_w_lg_dataout372w391w(0) <= wire_n10li_w_lg_dataout372w(0) AND n0iOll; + wire_n10li_w_lg_w_lg_dataout372w388w(0) <= wire_n10li_w_lg_dataout372w(0) AND n0iOlO; + wire_n10li_w_lg_dataout368w(0) <= wire_n10li_dataout AND wire_n10lO_w_lg_w_lg_dataout365w367w(0); + wire_n10li_w_lg_dataout372w(0) <= NOT wire_n10li_dataout; + wire_n10li_w_lg_dataout399w(0) <= wire_n10li_dataout OR wire_n10lO_w_lg_dataout398w(0); + wire_n10ll_dataout <= wire_n1O_dataout WHEN wire_nii_dataout = '1' ELSE wire_n1O_w_lg_dataout362w(0); + wire_n10ll_w_lg_dataout366w(0) <= NOT wire_n10ll_dataout; + wire_n10lO_dataout <= wire_n1l_dataout WHEN wire_nii_dataout = '1' ELSE wire_n1l_w_lg_dataout361w(0); + wire_n10lO_w_lg_w_lg_dataout365w367w(0) <= wire_n10lO_w_lg_dataout365w(0) AND wire_n10ll_w_lg_dataout366w(0); + wire_n10lO_w_lg_w_lg_dataout365w408w(0) <= wire_n10lO_w_lg_dataout365w(0) AND wire_n10ll_dataout; + wire_n10lO_w_lg_dataout407w(0) <= wire_n10lO_dataout AND wire_n10ll_w_lg_dataout366w(0); + wire_n10lO_w_lg_dataout365w(0) <= NOT wire_n10lO_dataout; + wire_n10lO_w_lg_dataout398w(0) <= wire_n10lO_dataout OR wire_n10ll_dataout; + wire_n111i_dataout <= (NOT (wire_n10ll_dataout AND wire_n10li_w_lg_dataout372w(0))) OR n0iOii; + wire_n1i_dataout <= (NOT data_in(25)) WHEN nl0i = '1' ELSE data_in(25); + wire_n1i_w_lg_w_lg_dataout511w513w(0) <= wire_n1i_w_lg_dataout511w(0) AND wire_nlOl_w_lg_dataout512w(0); + wire_n1i_w_lg_w_lg_dataout430w542w(0) <= wire_n1i_w_lg_dataout430w(0) AND n0il1i; + wire_n1i_w_lg_dataout650w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_w_lg_dataout276w649w(0); + wire_n1i_w_lg_dataout645w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_w_lg_dataout276w644w(0); + wire_n1i_w_lg_dataout631w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_w_lg_dataout276w630w(0); + wire_n1i_w_lg_dataout628w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_w_lg_dataout276w627w(0); + wire_n1i_w_lg_dataout634w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_dataout633w(0); + wire_n1i_w_lg_dataout653w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_dataout652w(0); + wire_n1i_w_lg_dataout459w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_dataout458w(0); + wire_n1i_w_lg_dataout656w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_dataout655w(0); + wire_n1i_w_lg_dataout429w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_dataout428w(0); + wire_n1i_w_lg_dataout452w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_dataout451w(0); + wire_n1i_w_lg_dataout477w(0) <= wire_n1i_dataout AND wire_nlOO_w_lg_dataout476w(0); + wire_n1i_w_lg_dataout511w(0) <= wire_n1i_dataout AND wire_nlOO_dataout; + wire_n1i_w_lg_dataout430w(0) <= NOT wire_n1i_dataout; + wire_n1i_w_lg_dataout508w(0) <= wire_n1i_dataout OR wire_nlOO_dataout; + wire_n1i0i_dataout <= wire_n1iii_dataout AND NOT(n0iOOO); + wire_n1i0l_dataout <= wire_n1iil_dataout OR n0l1OO; + wire_n1i0O_dataout <= wire_n1iiO_dataout OR n0l1OO; + wire_n1i1l_dataout <= wire_n1i0l_dataout AND NOT(n0iOOO); + wire_n1i1O_dataout <= wire_n1i0O_dataout AND NOT(n0iOOO); + wire_n1iii_dataout <= wire_n1ili_dataout OR n0l1OO; + wire_n1iil_dataout <= wire_n1l1i_dataout WHEN wire_w_lg_n0l11l353w(0) = '1' ELSE wire_n1ill_dataout; + wire_n1iiO_dataout <= wire_n1l1l_dataout WHEN wire_w_lg_n0l11l353w(0) = '1' ELSE wire_n1ilO_dataout; + wire_n1ili_dataout <= wire_n1l1O_dataout WHEN wire_w_lg_n0l11l353w(0) = '1' ELSE wire_n1iOi_dataout; + wire_n1ill_dataout <= wire_nli_w_lg_dataout349w(0) WHEN n0l11i = '1' ELSE wire_nli_dataout; + wire_n1ilO_dataout <= wire_niO_w_lg_dataout348w(0) WHEN n0l11i = '1' ELSE wire_niO_dataout; + wire_n1iOi_dataout <= wire_nil_w_lg_dataout347w(0) WHEN n0l11i = '1' ELSE wire_nil_dataout; + wire_n1l_dataout <= (NOT data_in(0)) WHEN nl0i = '1' ELSE data_in(0); + wire_n1l_w_lg_dataout361w(0) <= NOT wire_n1l_dataout; + wire_n1l1i_dataout <= wire_nli_w_lg_dataout349w(0) WHEN wire_nll_dataout = '1' ELSE wire_nli_dataout; + wire_n1l1i_w_lg_dataout356w(0) <= NOT wire_n1l1i_dataout; + wire_n1l1l_dataout <= wire_niO_w_lg_dataout348w(0) WHEN wire_nll_dataout = '1' ELSE wire_niO_dataout; + wire_n1l1l_w_lg_dataout358w(0) <= NOT wire_n1l1l_dataout; + wire_n1l1O_dataout <= wire_nil_w_lg_dataout347w(0) WHEN wire_nll_dataout = '1' ELSE wire_nil_dataout; + wire_n1l1O_w_lg_w_lg_dataout354w355w(0) <= wire_n1l1O_w_lg_dataout354w(0) AND wire_n1l1l_dataout; + wire_n1l1O_w_lg_dataout359w(0) <= wire_n1l1O_dataout AND wire_n1l1l_w_lg_dataout358w(0); + wire_n1l1O_w_lg_dataout354w(0) <= NOT wire_n1l1O_dataout; + wire_n1O_dataout <= (NOT data_in(1)) WHEN nl0i = '1' ELSE data_in(1); + wire_n1O_w_lg_w_lg_dataout362w873w(0) <= wire_n1O_w_lg_dataout362w(0) AND wire_n1l_w_lg_dataout361w(0); + wire_n1O_w_lg_w_lg_dataout362w856w(0) <= wire_n1O_w_lg_dataout362w(0) AND wire_n1l_dataout; + wire_n1O_w_lg_dataout857w(0) <= wire_n1O_dataout AND wire_n1l_w_lg_dataout361w(0); + wire_n1O_w_lg_dataout362w(0) <= NOT wire_n1O_dataout; + wire_ni0lOl_dataout <= wire_ni11iO_dataout WHEN ((wire_niO_dataout XOR wire_nil_dataout) AND n0lliO) = '1' ELSE (n0llli OR n0lO1l); + wire_ni0lOl_w_lg_dataout160w(0) <= wire_ni0lOl_dataout AND wire_w_lg_n0l0OO159w(0); + wire_ni0lOl_w_lg_dataout128w(0) <= NOT wire_ni0lOl_dataout; + wire_ni10i_dataout <= wire_nlOi_w_lg_dataout274w(0) WHEN wire_n1i_dataout = '1' ELSE wire_nlOi_dataout; + wire_ni10i_w_lg_w_lg_dataout281w282w(0) <= wire_ni10i_w_lg_dataout281w(0) AND wire_ni11O_dataout; + wire_ni10i_w_lg_dataout286w(0) <= wire_ni10i_dataout AND wire_ni11O_w_lg_dataout285w(0); + wire_ni10i_w_lg_dataout281w(0) <= NOT wire_ni10i_dataout; + wire_ni11iO_dataout <= nl1O WHEN ((wire_n0l_w_lg_w_lg_dataout90w975w(0) OR (wire_n0l_dataout AND n0lOii)) OR (n0O11O AND n0lOOi)) = '1' ELSE (n0lOil OR n0lOll); + wire_ni11iO_w_lg_w_lg_dataout104w971w(0) <= wire_ni11iO_w_lg_dataout104w(0) AND n00OOO; + wire_ni11iO_w_lg_dataout104w(0) <= NOT wire_ni11iO_dataout; + wire_ni11l_dataout <= wire_nlOO_w_lg_dataout276w(0) WHEN wire_n1i_dataout = '1' ELSE wire_nlOO_dataout; + wire_ni11l_w_lg_dataout283w(0) <= NOT wire_ni11l_dataout; + wire_ni11O_dataout <= wire_nlOl_w_lg_dataout275w(0) WHEN wire_n1i_dataout = '1' ELSE wire_nlOl_dataout; + wire_ni11O_w_lg_dataout285w(0) <= NOT wire_ni11O_dataout; + wire_nii_dataout <= (NOT data_in(5)) WHEN nl0i = '1' ELSE data_in(5); + wire_nii_w_lg_w_lg_dataout351w784w(0) <= wire_nii_w_lg_dataout351w(0) AND wire_n0O_w_lg_w_lg_dataout364w783w(0); + wire_nii_w_lg_w_lg_dataout351w778w(0) <= wire_nii_w_lg_dataout351w(0) AND wire_n0O_w_lg_w_lg_dataout364w777w(0); + wire_nii_w_lg_w_lg_dataout351w853w(0) <= wire_nii_w_lg_dataout351w(0) AND wire_n0O_dataout; + wire_nii_w_lg_w_lg_w_lg_dataout351w780w781w(0) <= wire_nii_w_lg_w_lg_dataout351w780w(0) AND n0i0lO; + wire_nii_w_lg_w785w791w(0) <= wire_nii_w785w(0) AND wire_w_lg_w_lg_n0i00O787w790w(0); + wire_nii_w810w(0) <= wire_nii_w_lg_w_lg_w_lg_w_lg_dataout795w796w799w802w(0) AND wire_w_lg_w_lg_n0i0ii805w809w(0); + wire_nii_w_lg_w_lg_dataout797w798w(0) <= wire_nii_w_lg_dataout797w(0) AND n0i0ll; + wire_nii_w_lg_dataout824w(0) <= wire_nii_dataout AND wire_n0O_w_lg_w_lg_dataout364w823w(0); + wire_nii_w_lg_dataout848w(0) <= wire_nii_dataout AND wire_n0O_w_lg_dataout847w(0); + wire_nii_w_lg_dataout801w(0) <= wire_nii_dataout AND wire_n0O_w_lg_dataout800w(0); + wire_nii_w_lg_dataout795w(0) <= wire_nii_dataout AND wire_n0O_w_lg_dataout794w(0); + wire_nii_w_lg_dataout721w(0) <= wire_nii_dataout AND wire_n0O_w_lg_dataout720w(0); + wire_nii_w_lg_dataout854w(0) <= wire_nii_dataout AND wire_n0O_w_lg_dataout364w(0); + wire_nii_w_lg_dataout737w(0) <= wire_nii_dataout AND wire_n0O_dataout; + wire_nii_w_lg_dataout351w(0) <= NOT wire_nii_dataout; + wire_nii_w_lg_w_lg_w_lg_dataout351w778w779w(0) <= wire_nii_w_lg_w_lg_dataout351w778w(0) OR n0i0Oi; + wire_nii_w_lg_w_lg_dataout795w796w(0) <= wire_nii_w_lg_dataout795w(0) OR n0i0Ol; + wire_nii_w_lg_w_lg_dataout351w780w(0) <= wire_nii_w_lg_dataout351w(0) OR wire_n0O_w_lg_dataout364w(0); + wire_nii_w_lg_w_lg_w_lg_w_lg_dataout351w778w779w782w(0) <= wire_nii_w_lg_w_lg_w_lg_dataout351w778w779w(0) OR wire_nii_w_lg_w_lg_w_lg_dataout351w780w781w(0); + wire_nii_w_lg_w_lg_w_lg_dataout795w796w799w(0) <= wire_nii_w_lg_w_lg_dataout795w796w(0) OR wire_nii_w_lg_w_lg_dataout797w798w(0); + wire_nii_w785w(0) <= wire_nii_w_lg_w_lg_w_lg_w_lg_dataout351w778w779w782w(0) OR wire_nii_w_lg_w_lg_dataout351w784w(0); + wire_nii_w_lg_w_lg_w_lg_w_lg_dataout795w796w799w802w(0) <= wire_nii_w_lg_w_lg_w_lg_dataout795w796w799w(0) OR wire_nii_w_lg_dataout801w(0); + wire_nii_w_lg_dataout797w(0) <= wire_nii_dataout OR wire_n0O_dataout; + wire_nil_dataout <= (NOT data_in(6)) WHEN nl0i = '1' ELSE data_in(6); + wire_nil_w_lg_w_lg_dataout347w831w(0) <= wire_nil_w_lg_dataout347w(0) AND n0i1li; + wire_nil_w_lg_w_lg_dataout347w904w(0) <= wire_nil_w_lg_dataout347w(0) AND n0lliO; + wire_nil_w_lg_dataout738w(0) <= wire_nil_dataout AND wire_nii_w_lg_dataout737w(0); + wire_nil_w_lg_dataout114w(0) <= wire_nil_dataout AND n0lliO; + wire_nil_w_lg_dataout347w(0) <= NOT wire_nil_dataout; + wire_niO_dataout <= (NOT data_in(7)) WHEN nl0i = '1' ELSE data_in(7); + wire_niO_w_lg_w_lg_dataout348w727w(0) <= wire_niO_w_lg_dataout348w(0) AND wire_nil_w_lg_dataout347w(0); + wire_niO_w_lg_w_lg_dataout348w750w(0) <= wire_niO_w_lg_dataout348w(0) AND wire_nii_dataout; + wire_niO_w_lg_w_lg_dataout348w908w(0) <= wire_niO_w_lg_dataout348w(0) AND wire_nil_dataout; + wire_niO_w_lg_w_lg_dataout348w765w(0) <= wire_niO_w_lg_dataout348w(0) AND n0i0iO; + wire_niO_w_lg_w_lg_dataout348w742w(0) <= wire_niO_w_lg_dataout348w(0) AND n0i0li; + wire_niO_w_lg_dataout739w(0) <= wire_niO_dataout AND wire_nil_w_lg_dataout738w(0); + wire_niO_w_lg_dataout115w(0) <= wire_niO_dataout AND wire_nil_w_lg_dataout114w(0); + wire_niO_w_lg_dataout753w(0) <= wire_niO_dataout AND wire_nii_w_lg_dataout351w(0); + wire_niO_w_lg_dataout909w(0) <= wire_niO_dataout AND wire_nil_w_lg_dataout347w(0); + wire_niO_w_lg_dataout723w(0) <= wire_niO_dataout AND wire_nil_dataout; + wire_niO_w_lg_dataout746w(0) <= wire_niO_dataout AND n0i0iO; + wire_niO_w_lg_dataout771w(0) <= wire_niO_dataout AND n0i0li; + wire_niO_w_lg_dataout348w(0) <= NOT wire_niO_dataout; + wire_niO_w_lg_w_lg_dataout348w788w(0) <= wire_niO_w_lg_dataout348w(0) OR wire_nil_w_lg_dataout347w(0); + wire_niO_w_lg_dataout807w(0) <= wire_niO_dataout OR wire_nil_dataout; + wire_niO00l_dataout <= ((NOT (wire_w_lg_n0i01O815w(0) OR wire_w_lg_n0lOlO818w(0))) AND (NOT (((n0i1OO OR n0llOO) OR ((NOT (((n0i1Ol OR n0i1Oi) OR wire_nii_w_lg_dataout824w(0)) OR (wire_nii_w_lg_dataout351w(0) AND (wire_n0O_dataout AND n0i1lO)))) AND (wire_w_lg_n0i1ll830w(0) AND (wire_nil_w_lg_w_lg_dataout347w831w(0) OR (wire_nil_dataout AND n0lO1i))))) OR ((wire_nll_w_lg_w_lg_dataout726w837w(0) OR (wire_nll_dataout AND n0lO1i)) AND wire_w_lg_n0i1Oi841w(0))))) WHEN ((NOT r8b10b_dec_ibm_en(0)) AND (NOT r8b10b_dec_ibm_en(1))) = '1' ELSE (NOT ((((((((((((((n0i0Ol OR n0i0Oi) OR (wire_nii_w_lg_dataout351w(0) AND wire_n0O_w_lg_w_lg_dataout364w717w(0))) OR wire_nii_w_lg_dataout721w(0)) OR (wire_nll_w_lg_dataout725w(0) OR (wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_w_lg_dataout348w727w(0))))) OR (wire_nli_w_lg_dataout349w(0) AND (wire_niO_w_lg_dataout348w(0) AND (wire_nil_w_lg_dataout347w(0) AND (wire_nii_w_lg_dataout351w(0) AND wire_n0O_w_lg_dataout364w(0)))))) OR wire_nli_w_lg_dataout740w(0)) OR (wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_w_lg_dataout348w742w(0)))) OR wire_nll_w_lg_dataout748w(0)) OR (((wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_w_lg_dataout348w750w(0))) OR wire_nll_w_lg_dataout755w(0)) AND wire_w_lg_n0i0il757w(0))) OR wire_w_lg_n0i0il763w(0)) OR ((wire_nll_w_lg_dataout726w(0) AND (wire_nli_w_lg_dataout349w(0) AND wire_niO_w_lg_w_lg_dataout348w765w(0))) AND wire_w_lg_n0i0ll768w(0))) OR (wire_nll_w_lg_dataout773w(0) AND wire_w_lg_n0i0lO774w(0))) OR wire_w_lg_w_r8b10b_dec_ibm_en_range481w792w(0)) OR wire_w_lg_w_r8b10b_dec_ibm_en_range481w811w(0))); + wire_niO00l_w_lg_dataout60w(0) <= NOT wire_niO00l_dataout; + wire_nl0l_dataout <= wire_nl0lll_dataout WHEN cascaded_8b10b_en = '1' ELSE wire_ni0lOl_dataout; + wire_nl0lll_dataout <= wire_nl110O_dataout WHEN ((wire_nlOl_dataout XOR wire_nlOi_dataout) AND n0l00l) = '1' ELSE (n0l00O OR n0l0iO); + wire_nl110O_dataout <= wire_ni0lOl_dataout WHEN ((wire_nlli_w_lg_w_lg_dataout157w684w(0) OR (wire_nlli_dataout AND n0l0Ol)) OR (n0lilO AND n0liii)) = '1' ELSE (n0l0OO OR n0li1O); + wire_nl110O_w_lg_w_lg_dataout171w680w(0) <= wire_nl110O_w_lg_dataout171w(0) AND n0ii0O; + wire_nl110O_w_lg_dataout171w(0) <= NOT wire_nl110O_dataout; + wire_nli_dataout <= (NOT data_in(8)) WHEN nl0i = '1' ELSE data_in(8); + wire_nli_w_lg_w_lg_dataout349w761w(0) <= wire_nli_w_lg_dataout349w(0) AND n0i00O; + wire_nli_w_lg_w_lg_dataout349w921w(0) <= wire_nli_w_lg_dataout349w(0) AND n0i10i; + wire_nli_w_lg_w_lg_dataout349w918w(0) <= wire_nli_w_lg_dataout349w(0) AND n0i10l; + wire_nli_w_lg_w_lg_dataout349w940w(0) <= wire_nli_w_lg_dataout349w(0) AND n0i11l; + wire_nli_w_lg_w_lg_dataout349w935w(0) <= wire_nli_w_lg_dataout349w(0) AND n0i11O; + wire_nli_w_lg_dataout924w(0) <= wire_nli_dataout AND wire_niO_w_lg_w_lg_dataout348w727w(0); + wire_nli_w_lg_dataout943w(0) <= wire_nli_dataout AND wire_niO_w_lg_w_lg_dataout348w908w(0); + wire_nli_w_lg_dataout740w(0) <= wire_nli_dataout AND wire_niO_w_lg_dataout739w(0); + wire_nli_w_lg_dataout754w(0) <= wire_nli_dataout AND wire_niO_w_lg_dataout753w(0); + wire_nli_w_lg_dataout946w(0) <= wire_nli_dataout AND wire_niO_w_lg_dataout909w(0); + wire_nli_w_lg_dataout724w(0) <= wire_nli_dataout AND wire_niO_w_lg_dataout723w(0); + wire_nli_w_lg_dataout747w(0) <= wire_nli_dataout AND wire_niO_w_lg_dataout746w(0); + wire_nli_w_lg_dataout772w(0) <= wire_nli_dataout AND wire_niO_w_lg_dataout771w(0); + wire_nli_w_lg_dataout760w(0) <= wire_nli_dataout AND n0i0ii; + wire_nli_w_lg_dataout349w(0) <= NOT wire_nli_dataout; + wire_nli_w_lg_w_lg_dataout760w762w(0) <= wire_nli_w_lg_dataout760w(0) OR wire_nli_w_lg_w_lg_dataout349w761w(0); + wire_nlii_dataout <= (NOT data_in(16)) WHEN nl0i = '1' ELSE data_in(16); + wire_nlii_w_lg_dataout288w(0) <= NOT wire_nlii_dataout; + wire_nlil_dataout <= (NOT data_in(17)) WHEN nl0i = '1' ELSE data_in(17); + wire_nlil_w_lg_w_lg_dataout289w582w(0) <= wire_nlil_w_lg_dataout289w(0) AND wire_nlii_w_lg_dataout288w(0); + wire_nlil_w_lg_w_lg_dataout289w565w(0) <= wire_nlil_w_lg_dataout289w(0) AND wire_nlii_dataout; + wire_nlil_w_lg_dataout566w(0) <= wire_nlil_dataout AND wire_nlii_w_lg_dataout288w(0); + wire_nlil_w_lg_dataout289w(0) <= NOT wire_nlil_dataout; + wire_nliO_dataout <= (NOT data_in(18)) WHEN nl0i = '1' ELSE data_in(18); + wire_nliO_w_lg_w_lg_dataout290w711w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0i0OO; + wire_nliO_w_lg_w_lg_dataout290w706w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0ii1i; + wire_nliO_w_lg_w_lg_dataout290w699w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0ii1l; + wire_nliO_w_lg_w_lg_dataout290w696w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0ii1O; + wire_nliO_w_lg_w_lg_dataout290w599w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0iilO; + wire_nliO_w_lg_w_lg_dataout290w594w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0iiOi; + wire_nliO_w_lg_w_lg_dataout290w579w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0iiOl; + wire_nliO_w_lg_w_lg_dataout290w576w(0) <= wire_nliO_w_lg_dataout290w(0) AND n0iiOO; + wire_nliO_w_lg_dataout583w(0) <= wire_nliO_dataout AND wire_nlil_w_lg_w_lg_dataout289w582w(0); + wire_nliO_w_lg_dataout602w(0) <= wire_nliO_dataout AND wire_nlil_w_lg_w_lg_dataout289w565w(0); + wire_nliO_w_lg_dataout605w(0) <= wire_nliO_dataout AND wire_nlil_w_lg_dataout566w(0); + wire_nliO_w_lg_dataout290w(0) <= NOT wire_nliO_dataout; + wire_nliOO_dataout <= data_in(0) WHEN rrxpcsbypass_en = '1' ELSE nl0O; + wire_nll_dataout <= (NOT data_in(9)) WHEN nl0i = '1' ELSE data_in(9); + wire_nll_w_lg_w_lg_dataout806w808w(0) <= wire_nll_w_lg_dataout806w(0) AND wire_niO_w_lg_dataout807w(0); + wire_nll_w_lg_w_lg_dataout726w837w(0) <= wire_nll_w_lg_dataout726w(0) AND n0i1li; + wire_nll_w_lg_dataout922w(0) <= wire_nll_dataout AND wire_nli_w_lg_w_lg_dataout349w921w(0); + wire_nll_w_lg_dataout919w(0) <= wire_nll_dataout AND wire_nli_w_lg_w_lg_dataout349w918w(0); + wire_nll_w_lg_dataout941w(0) <= wire_nll_dataout AND wire_nli_w_lg_w_lg_dataout349w940w(0); + wire_nll_w_lg_dataout936w(0) <= wire_nll_dataout AND wire_nli_w_lg_w_lg_dataout349w935w(0); + wire_nll_w_lg_dataout925w(0) <= wire_nll_dataout AND wire_nli_w_lg_dataout924w(0); + wire_nll_w_lg_dataout944w(0) <= wire_nll_dataout AND wire_nli_w_lg_dataout943w(0); + wire_nll_w_lg_dataout755w(0) <= wire_nll_dataout AND wire_nli_w_lg_dataout754w(0); + wire_nll_w_lg_dataout947w(0) <= wire_nll_dataout AND wire_nli_w_lg_dataout946w(0); + wire_nll_w_lg_dataout725w(0) <= wire_nll_dataout AND wire_nli_w_lg_dataout724w(0); + wire_nll_w_lg_dataout748w(0) <= wire_nll_dataout AND wire_nli_w_lg_dataout747w(0); + wire_nll_w_lg_dataout773w(0) <= wire_nll_dataout AND wire_nli_w_lg_dataout772w(0); + wire_nll_w_lg_dataout806w(0) <= wire_nll_dataout AND wire_nli_dataout; + wire_nll_w_lg_dataout726w(0) <= NOT wire_nll_dataout; + wire_nll_w_lg_dataout803w(0) <= wire_nll_dataout OR wire_nli_dataout; + wire_nll0i_dataout <= data_in(4) WHEN rrxpcsbypass_en = '1' ELSE nlOil; + wire_nll0l_dataout <= data_in(5) WHEN rrxpcsbypass_en = '1' ELSE nlOiO; + wire_nll0O_dataout <= data_in(6) WHEN rrxpcsbypass_en = '1' ELSE nlOli; + wire_nll1i_dataout <= data_in(1) WHEN rrxpcsbypass_en = '1' ELSE nlO0l; + wire_nll1l_dataout <= data_in(2) WHEN rrxpcsbypass_en = '1' ELSE nlO0O; + wire_nll1O_dataout <= data_in(3) WHEN rrxpcsbypass_en = '1' ELSE nlOii; + wire_nlli_dataout <= (NOT data_in(19)) WHEN nl0i = '1' ELSE data_in(19); + wire_nlli_w_lg_w_lg_dataout157w684w(0) <= wire_nlli_w_lg_dataout157w(0) AND n0ii0i; + wire_nlli_w_lg_w_lg_dataout157w158w(0) <= wire_nlli_w_lg_dataout157w(0) AND n0l0Ol; + wire_nlli_w_lg_dataout712w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w711w(0); + wire_nlli_w_lg_dataout707w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w706w(0); + wire_nlli_w_lg_dataout700w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w699w(0); + wire_nlli_w_lg_dataout697w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w696w(0); + wire_nlli_w_lg_dataout600w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w599w(0); + wire_nlli_w_lg_dataout595w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w594w(0); + wire_nlli_w_lg_dataout580w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w579w(0); + wire_nlli_w_lg_dataout577w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_w_lg_dataout290w576w(0); + wire_nlli_w_lg_dataout584w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_dataout583w(0); + wire_nlli_w_lg_dataout603w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_dataout602w(0); + wire_nlli_w_lg_dataout606w(0) <= wire_nlli_dataout AND wire_nliO_w_lg_dataout605w(0); + wire_nlli_w_lg_dataout555w(0) <= wire_nlli_dataout AND wire_nliO_dataout; + wire_nlli_w_lg_dataout157w(0) <= NOT wire_nlli_dataout; + wire_nllii_dataout <= data_in(7) WHEN rrxpcsbypass_en = '1' ELSE nlOll; + wire_nllil_dataout <= data_in(8) WHEN rrxpcsbypass_en = '1' ELSE nlOlO; + wire_nlliO_dataout <= data_in(9) WHEN rrxpcsbypass_en = '1' ELSE nlOOi; + wire_nlll_dataout <= (NOT data_in(20)) WHEN nl0i = '1' ELSE data_in(20); + wire_nlll_w_lg_w_lg_dataout291w488w(0) <= wire_nlll_w_lg_dataout291w(0) AND wire_nlli_w_lg_dataout157w(0); + wire_nlll_w_lg_w_lg_dataout291w482w(0) <= wire_nlll_w_lg_dataout291w(0) AND n0illl; + wire_nlll_w_lg_w_lg_dataout291w421w(0) <= wire_nlll_w_lg_dataout291w(0) AND n0iO1O; + wire_nlll_w_lg_w_lg_dataout291w528w(0) <= wire_nlll_w_lg_dataout291w(0) AND n0liil; + wire_nlll_w_lg_dataout556w(0) <= wire_nlll_dataout AND wire_nlli_w_lg_dataout555w(0); + wire_nlll_w_lg_dataout505w(0) <= wire_nlll_dataout AND wire_nlli_dataout; + wire_nlll_w_lg_dataout499w(0) <= wire_nlll_dataout AND n0illl; + wire_nlll_w_lg_dataout424w(0) <= wire_nlll_dataout AND n0iO1l; + wire_nlll_w_lg_dataout291w(0) <= NOT wire_nlll_dataout; + wire_nllli_dataout <= data_in(16) WHEN rrxpcsbypass_en = '1' ELSE nlOOl; + wire_nllll_dataout <= data_in(17) WHEN rrxpcsbypass_en = '1' ELSE nlOOO; + wire_nlllO_dataout <= data_in(18) WHEN rrxpcsbypass_en = '1' ELSE n11i; + wire_nllO_dataout <= (NOT data_in(21)) WHEN nl0i = '1' ELSE data_in(21); + wire_nllO_w_lg_w_lg_dataout278w489w(0) <= wire_nllO_w_lg_dataout278w(0) AND wire_nlll_w_lg_w_lg_dataout291w488w(0); + wire_nllO_w_lg_w_lg_dataout278w483w(0) <= wire_nllO_w_lg_dataout278w(0) AND wire_nlll_w_lg_w_lg_dataout291w482w(0); + wire_nllO_w_lg_w_lg_dataout278w562w(0) <= wire_nllO_w_lg_dataout278w(0) AND wire_nlll_dataout; + wire_nllO_w_lg_w_lg_w_lg_dataout278w485w486w(0) <= wire_nllO_w_lg_w_lg_dataout278w485w(0) AND n0iO1O; + wire_nllO_w_lg_w490w496w(0) <= wire_nllO_w490w(0) AND wire_w_lg_w_lg_n0illO492w495w(0); + wire_nllO_w515w(0) <= wire_nllO_w_lg_w_lg_w_lg_w_lg_dataout500w501w504w507w(0) AND wire_w_lg_w_lg_n0ilOi510w514w(0); + wire_nllO_w_lg_w_lg_dataout502w503w(0) <= wire_nllO_w_lg_dataout502w(0) AND n0iO1l; + wire_nllO_w_lg_dataout529w(0) <= wire_nllO_dataout AND wire_nlll_w_lg_w_lg_dataout291w528w(0); + wire_nllO_w_lg_dataout557w(0) <= wire_nllO_dataout AND wire_nlll_w_lg_dataout556w(0); + wire_nllO_w_lg_dataout506w(0) <= wire_nllO_dataout AND wire_nlll_w_lg_dataout505w(0); + wire_nllO_w_lg_dataout500w(0) <= wire_nllO_dataout AND wire_nlll_w_lg_dataout499w(0); + wire_nllO_w_lg_dataout425w(0) <= wire_nllO_dataout AND wire_nlll_w_lg_dataout424w(0); + wire_nllO_w_lg_dataout563w(0) <= wire_nllO_dataout AND wire_nlll_w_lg_dataout291w(0); + wire_nllO_w_lg_dataout441w(0) <= wire_nllO_dataout AND wire_nlll_dataout; + wire_nllO_w_lg_dataout278w(0) <= NOT wire_nllO_dataout; + wire_nllO_w_lg_w_lg_w_lg_dataout278w483w484w(0) <= wire_nllO_w_lg_w_lg_dataout278w483w(0) OR n0iO0i; + wire_nllO_w_lg_w_lg_dataout500w501w(0) <= wire_nllO_w_lg_dataout500w(0) OR n0iO0l; + wire_nllO_w_lg_w_lg_dataout278w485w(0) <= wire_nllO_w_lg_dataout278w(0) OR wire_nlll_w_lg_dataout291w(0); + wire_nllO_w_lg_w_lg_w_lg_w_lg_dataout278w483w484w487w(0) <= wire_nllO_w_lg_w_lg_w_lg_dataout278w483w484w(0) OR wire_nllO_w_lg_w_lg_w_lg_dataout278w485w486w(0); + wire_nllO_w_lg_w_lg_w_lg_dataout500w501w504w(0) <= wire_nllO_w_lg_w_lg_dataout500w501w(0) OR wire_nllO_w_lg_w_lg_dataout502w503w(0); + wire_nllO_w490w(0) <= wire_nllO_w_lg_w_lg_w_lg_w_lg_dataout278w483w484w487w(0) OR wire_nllO_w_lg_w_lg_dataout278w489w(0); + wire_nllO_w_lg_w_lg_w_lg_w_lg_dataout500w501w504w507w(0) <= wire_nllO_w_lg_w_lg_w_lg_dataout500w501w504w(0) OR wire_nllO_w_lg_dataout506w(0); + wire_nllO_w_lg_dataout502w(0) <= wire_nllO_dataout OR wire_nlll_dataout; + wire_nllOi_dataout <= data_in(19) WHEN rrxpcsbypass_en = '1' ELSE n11l; + wire_nllOl_dataout <= data_in(20) WHEN rrxpcsbypass_en = '1' ELSE n11O; + wire_nllOO_dataout <= data_in(21) WHEN rrxpcsbypass_en = '1' ELSE n10i; + wire_nlO01l_dataout <= ((NOT (wire_w_lg_n0iliO520w(0) OR wire_w_lg_n0li0i523w(0))) AND (NOT (((n0il0O OR n0l0ii) OR ((NOT (((n0il0l OR n0il0i) OR wire_nllO_w_lg_dataout529w(0)) OR (wire_nllO_w_lg_dataout278w(0) AND (wire_nlll_dataout AND n0il1O)))) AND (wire_w_lg_n0il1l535w(0) AND (wire_nlOi_w_lg_w_lg_dataout274w536w(0) OR (wire_nlOi_dataout AND n0l0il))))) OR ((wire_n1i_w_lg_w_lg_dataout430w542w(0) OR (wire_n1i_dataout AND n0l0il)) AND wire_w_lg_n0il0i546w(0))))) WHEN ((NOT r8b10b_dec_ibm_en(0)) AND (NOT r8b10b_dec_ibm_en(1))) = '1' ELSE (NOT ((((((((((((((n0iO0l OR n0iO0i) OR (wire_nllO_w_lg_dataout278w(0) AND wire_nlll_w_lg_w_lg_dataout291w421w(0))) OR wire_nllO_w_lg_dataout425w(0)) OR (wire_n1i_w_lg_dataout429w(0) OR (wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_w_lg_dataout275w431w(0))))) OR (wire_nlOO_w_lg_dataout276w(0) AND (wire_nlOl_w_lg_dataout275w(0) AND (wire_nlOi_w_lg_dataout274w(0) AND (wire_nllO_w_lg_dataout278w(0) AND wire_nlll_w_lg_dataout291w(0)))))) OR wire_nlOO_w_lg_dataout444w(0)) OR (wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_w_lg_dataout275w446w(0)))) OR wire_n1i_w_lg_dataout452w(0)) OR (((wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_w_lg_dataout275w454w(0))) OR wire_n1i_w_lg_dataout459w(0)) AND wire_w_lg_n0ilOl461w(0))) OR wire_w_lg_n0ilOl467w(0)) OR ((wire_n1i_w_lg_dataout430w(0) AND (wire_nlOO_w_lg_dataout276w(0) AND wire_nlOl_w_lg_w_lg_dataout275w469w(0))) AND wire_w_lg_n0iO1l472w(0))) OR (wire_n1i_w_lg_dataout477w(0) AND wire_w_lg_n0iO1O478w(0))) OR wire_w_lg_w_r8b10b_dec_ibm_en_range481w497w(0)) OR wire_w_lg_w_r8b10b_dec_ibm_en_range481w516w(0))); + wire_nlO01l_w_lg_dataout62w(0) <= NOT wire_nlO01l_dataout; + wire_nlO0i_dataout <= data_in(25) WHEN rrxpcsbypass_en = '1' ELSE n1il; + wire_nlO1i_dataout <= data_in(22) WHEN rrxpcsbypass_en = '1' ELSE n10l; + wire_nlO1l_dataout <= data_in(23) WHEN rrxpcsbypass_en = '1' ELSE n10O; + wire_nlO1O_dataout <= data_in(24) WHEN rrxpcsbypass_en = '1' ELSE n1ii; + wire_nlOi_dataout <= (NOT data_in(22)) WHEN nl0i = '1' ELSE data_in(22); + wire_nlOi_w_lg_w_lg_dataout174w177w(0) <= wire_nlOi_w_lg_dataout174w(0) AND wire_n0l01O44_w_lg_q176w(0); + wire_nlOi_w_lg_w_lg_dataout274w536w(0) <= wire_nlOi_w_lg_dataout274w(0) AND n0il1i; + wire_nlOi_w_lg_w_lg_dataout274w613w(0) <= wire_nlOi_w_lg_dataout274w(0) AND n0l00l; + wire_nlOi_w_lg_dataout442w(0) <= wire_nlOi_dataout AND wire_nllO_w_lg_dataout441w(0); + wire_nlOi_w_lg_dataout174w(0) <= wire_nlOi_dataout AND n0l00l; + wire_nlOi_w_lg_dataout274w(0) <= NOT wire_nlOi_dataout; + wire_nlOl_dataout <= (NOT data_in(23)) WHEN nl0i = '1' ELSE data_in(23); + wire_nlOl_w_lg_w_lg_dataout275w431w(0) <= wire_nlOl_w_lg_dataout275w(0) AND wire_nlOi_w_lg_dataout274w(0); + wire_nlOl_w_lg_w_lg_dataout275w454w(0) <= wire_nlOl_w_lg_dataout275w(0) AND wire_nllO_dataout; + wire_nlOl_w_lg_w_lg_dataout275w617w(0) <= wire_nlOl_w_lg_dataout275w(0) AND wire_nlOi_dataout; + wire_nlOl_w_lg_w_lg_dataout275w469w(0) <= wire_nlOl_w_lg_dataout275w(0) AND n0ilOO; + wire_nlOl_w_lg_w_lg_dataout275w446w(0) <= wire_nlOl_w_lg_dataout275w(0) AND n0iO1i; + wire_nlOl_w_lg_dataout178w(0) <= wire_nlOl_dataout AND wire_nlOi_w_lg_w_lg_dataout174w177w(0); + wire_nlOl_w_lg_dataout443w(0) <= wire_nlOl_dataout AND wire_nlOi_w_lg_dataout442w(0); + wire_nlOl_w_lg_dataout457w(0) <= wire_nlOl_dataout AND wire_nllO_w_lg_dataout278w(0); + wire_nlOl_w_lg_dataout618w(0) <= wire_nlOl_dataout AND wire_nlOi_w_lg_dataout274w(0); + wire_nlOl_w_lg_dataout427w(0) <= wire_nlOl_dataout AND wire_nlOi_dataout; + wire_nlOl_w_lg_dataout450w(0) <= wire_nlOl_dataout AND n0ilOO; + wire_nlOl_w_lg_dataout475w(0) <= wire_nlOl_dataout AND n0iO1i; + wire_nlOl_w_lg_dataout275w(0) <= NOT wire_nlOl_dataout; + wire_nlOl_w_lg_w_lg_dataout275w493w(0) <= wire_nlOl_w_lg_dataout275w(0) OR wire_nlOi_w_lg_dataout274w(0); + wire_nlOl_w_lg_dataout512w(0) <= wire_nlOl_dataout OR wire_nlOi_dataout; + wire_nlOlil_dataout <= wire_nlOlOi_dataout OR n0l01l; + wire_nlOliO_dataout <= wire_nlOlOl_dataout OR n0l01l; + wire_nlOlli_dataout <= wire_nlOlOO_dataout OR n0l01l; + wire_nlOlll_dataout <= wire_nlOO1i_dataout AND NOT(n0l01l); + wire_nlOllO_dataout <= wire_nlOO1l_dataout AND NOT(n0l01l); + wire_nlOlOi_dataout <= wire_nlOO1O_dataout OR n0iOOl; + wire_nlOlOl_dataout <= wire_nlOO0i_dataout OR n0iOOl; + wire_nlOlOO_dataout <= wire_nlOO0l_dataout AND NOT(n0iOOl); + wire_nlOO_dataout <= (NOT data_in(24)) WHEN nl0i = '1' ELSE data_in(24); + wire_nlOO_w_lg_w_lg_dataout276w649w(0) <= wire_nlOO_w_lg_dataout276w(0) AND n0iiil; + wire_nlOO_w_lg_w_lg_dataout276w644w(0) <= wire_nlOO_w_lg_dataout276w(0) AND n0iiiO; + wire_nlOO_w_lg_w_lg_dataout276w630w(0) <= wire_nlOO_w_lg_dataout276w(0) AND n0iili; + wire_nlOO_w_lg_w_lg_dataout276w627w(0) <= wire_nlOO_w_lg_dataout276w(0) AND n0iill; + wire_nlOO_w_lg_w_lg_dataout276w465w(0) <= wire_nlOO_w_lg_dataout276w(0) AND n0illO; + wire_nlOO_w_lg_dataout633w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_w_lg_dataout275w431w(0); + wire_nlOO_w_lg_dataout652w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_w_lg_dataout275w617w(0); + wire_nlOO_w_lg_dataout444w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_dataout443w(0); + wire_nlOO_w_lg_dataout458w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_dataout457w(0); + wire_nlOO_w_lg_dataout655w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_dataout618w(0); + wire_nlOO_w_lg_dataout428w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_dataout427w(0); + wire_nlOO_w_lg_dataout451w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_dataout450w(0); + wire_nlOO_w_lg_dataout476w(0) <= wire_nlOO_dataout AND wire_nlOl_w_lg_dataout475w(0); + wire_nlOO_w_lg_dataout464w(0) <= wire_nlOO_dataout AND n0ilOi; + wire_nlOO_w_lg_dataout276w(0) <= NOT wire_nlOO_dataout; + wire_nlOO_w_lg_w_lg_dataout464w466w(0) <= wire_nlOO_w_lg_dataout464w(0) OR wire_nlOO_w_lg_w_lg_dataout276w465w(0); + wire_nlOO0i_dataout <= wire_nlOOOO_dataout WHEN n0iOOi = '1' ELSE wire_nlOOiO_dataout; + wire_nlOO0l_dataout <= wire_nlOOOO_dataout WHEN n0iOOi = '1' ELSE wire_nlOOli_dataout; + wire_nlOO0O_dataout <= wire_nlOOOO_dataout WHEN n0iOOi = '1' ELSE wire_nlOOll_dataout; + wire_nlOO1i_dataout <= wire_nlOO0O_dataout AND NOT(n0iOOl); + wire_nlOO1l_dataout <= wire_nlOOii_dataout AND NOT(n0iOOl); + wire_nlOO1O_dataout <= wire_nlOOOl_dataout WHEN n0iOOi = '1' ELSE wire_nlOOil_dataout; + wire_nlOOii_dataout <= wire_nlOOOO_dataout WHEN n0iOOi = '1' ELSE wire_nlOOlO_dataout; + wire_nlOOil_dataout <= wire_n0O_dataout WHEN n0iOiO = '1' ELSE n0l01i; + wire_nlOOiO_dataout <= wire_n0l_dataout WHEN n0iOiO = '1' ELSE wire_n10iO_w_lg_dataout371w(0); + wire_nlOOli_dataout <= wire_n0i_dataout WHEN n0iOiO = '1' ELSE wire_n10li_w_lg_dataout372w(0); + wire_nlOOll_dataout <= wire_n1O_dataout WHEN n0iOiO = '1' ELSE wire_n10ll_w_lg_dataout366w(0); + wire_nlOOlO_dataout <= wire_n1l_dataout WHEN n0iOiO = '1' ELSE wire_n10lO_w_lg_dataout365w(0); + wire_nlOOOl_dataout <= wire_n111i_dataout AND NOT(n0iOil); + wire_nlOOOO_dataout <= wire_w_lg_n0iOii405w(0) AND NOT(n0iOil); + + END RTL; --cycloneiv_hssi_rx_digi_dec_chnl_top +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 135 mux21 124 oper_add 1 cycloneiv_hssi_rx_digis_ram16x14_syn 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_dskw_fifo IS + PORT + ( + align_det_sync : OUT STD_LOGIC; + audi : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); + audi_pre : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); + clk_1 : IN STD_LOGIC; + en_dskw_gp : IN STD_LOGIC; + en_dskw_qd : IN STD_LOGIC; + fifo_rst_rd_gp : IN STD_LOGIC; + fifo_rst_rd_qd : IN STD_LOGIC; + rcvd_clk : IN STD_LOGIC; + rd_align : OUT STD_LOGIC; + rdskchrp : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + rdskposdisp : IN STD_LOGIC; + sel_gp_md : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + sudi : IN STD_LOGIC_VECTOR (13 DOWNTO 0) + ); + END cycloneiv_hssi_rx_digi_dskw_fifo; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_dskw_fifo IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n100l17 : STD_LOGIC := '0'; + SIGNAL n100l18 : STD_LOGIC := '0'; + SIGNAL n101i21 : STD_LOGIC := '0'; + SIGNAL n101i22 : STD_LOGIC := '0'; + SIGNAL n101O19 : STD_LOGIC := '0'; + SIGNAL n101O20 : STD_LOGIC := '0'; + SIGNAL n10iO15 : STD_LOGIC := '0'; + SIGNAL n10iO16 : STD_LOGIC := '0'; + SIGNAL n10lO13 : STD_LOGIC := '0'; + SIGNAL n10lO14 : STD_LOGIC := '0'; + SIGNAL n10Ol11 : STD_LOGIC := '0'; + SIGNAL n10Ol12 : STD_LOGIC := '0'; + SIGNAL n10OO10 : STD_LOGIC := '0'; + SIGNAL wire_n10OO10_w_lg_w_lg_q39w40w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n10OO10_w_lg_q39w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n10OO9 : STD_LOGIC := '0'; + SIGNAL n110i33 : STD_LOGIC := '0'; + SIGNAL n110i34 : STD_LOGIC := '0'; + SIGNAL n110O31 : STD_LOGIC := '0'; + SIGNAL n110O32 : STD_LOGIC := '0'; + SIGNAL n111l35 : STD_LOGIC := '0'; + SIGNAL n111l36 : STD_LOGIC := '0'; + SIGNAL n11il29 : STD_LOGIC := '0'; + SIGNAL n11il30 : STD_LOGIC := '0'; + SIGNAL n11li27 : STD_LOGIC := '0'; + SIGNAL n11li28 : STD_LOGIC := '0'; + SIGNAL n11lO25 : STD_LOGIC := '0'; + SIGNAL n11lO26 : STD_LOGIC := '0'; + SIGNAL n11Ol23 : STD_LOGIC := '0'; + SIGNAL n11Ol24 : STD_LOGIC := '0'; + SIGNAL n1i0l3 : STD_LOGIC := '0'; + SIGNAL n1i0l4 : STD_LOGIC := '0'; + SIGNAL n1i1i7 : STD_LOGIC := '0'; + SIGNAL n1i1i8 : STD_LOGIC := '0'; + SIGNAL wire_n1i1i8_w_lg_w_lg_q36w37w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1i1i8_w_lg_q36w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1i1O5 : STD_LOGIC := '0'; + SIGNAL n1i1O6 : STD_LOGIC := '0'; + SIGNAL n1ili1 : STD_LOGIC := '0'; + SIGNAL n1ili2 : STD_LOGIC := '0'; + SIGNAL nlOO0l47 : STD_LOGIC := '0'; + SIGNAL nlOO0l48 : STD_LOGIC := '0'; + SIGNAL nlOOii45 : STD_LOGIC := '0'; + SIGNAL nlOOii46 : STD_LOGIC := '0'; + SIGNAL nlOOiO43 : STD_LOGIC := '0'; + SIGNAL nlOOiO44 : STD_LOGIC := '0'; + SIGNAL nlOOll41 : STD_LOGIC := '0'; + SIGNAL nlOOll42 : STD_LOGIC := '0'; + SIGNAL nlOOOi39 : STD_LOGIC := '0'; + SIGNAL nlOOOi40 : STD_LOGIC := '0'; + SIGNAL nlOOOO37 : STD_LOGIC := '0'; + SIGNAL nlOOOO38 : STD_LOGIC := '0'; + SIGNAL ni00l : STD_LOGIC := '0'; + SIGNAL ni10i : STD_LOGIC := '0'; + SIGNAL wire_ni00i_PRN : STD_LOGIC; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL ni0l : STD_LOGIC := '0'; + SIGNAL ni0O : STD_LOGIC := '0'; + SIGNAL niii : STD_LOGIC := '0'; + SIGNAL niiO : STD_LOGIC := '0'; + SIGNAL nlliO : STD_LOGIC := '0'; + SIGNAL nllli : STD_LOGIC := '0'; + SIGNAL nllll : STD_LOGIC := '0'; + SIGNAL nlllO : STD_LOGIC := '0'; + SIGNAL nllOi : STD_LOGIC := '0'; + SIGNAL nllOl : STD_LOGIC := '0'; + SIGNAL nllOO : STD_LOGIC := '0'; + SIGNAL nlO0i : STD_LOGIC := '0'; + SIGNAL nlO0l : STD_LOGIC := '0'; + SIGNAL nlO0O : STD_LOGIC := '0'; + SIGNAL nlO1i : STD_LOGIC := '0'; + SIGNAL nlO1l : STD_LOGIC := '0'; + SIGNAL nlO1O : STD_LOGIC := '0'; + SIGNAL nlOii : STD_LOGIC := '0'; + SIGNAL nlOil : STD_LOGIC := '0'; + SIGNAL nlOiO : STD_LOGIC := '0'; + SIGNAL wire_niil_PRN : STD_LOGIC; + SIGNAL wire_niil_w_lg_nlOiO60w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niil_w_lg_n0Oi337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niil_w_lg_ni0l335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niil_w_lg_ni0O333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niil_w_lg_niii332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni00O : STD_LOGIC := '0'; + SIGNAL ni01i : STD_LOGIC := '0'; + SIGNAL ni01l : STD_LOGIC := '0'; + SIGNAL ni01O : STD_LOGIC := '0'; + SIGNAL ni0ii : STD_LOGIC := '0'; + SIGNAL ni0il : STD_LOGIC := '0'; + SIGNAL ni0iO : STD_LOGIC := '0'; + SIGNAL ni0li : STD_LOGIC := '0'; + SIGNAL ni0ll : STD_LOGIC := '0'; + SIGNAL ni0lO : STD_LOGIC := '0'; + SIGNAL ni0Oi : STD_LOGIC := '0'; + SIGNAL ni0Ol : STD_LOGIC := '0'; + SIGNAL ni0OO : STD_LOGIC := '0'; + SIGNAL ni10l : STD_LOGIC := '0'; + SIGNAL ni10O : STD_LOGIC := '0'; + SIGNAL ni11l : STD_LOGIC := '0'; + SIGNAL ni11O : STD_LOGIC := '0'; + SIGNAL ni1ii : STD_LOGIC := '0'; + SIGNAL ni1il : STD_LOGIC := '0'; + SIGNAL ni1iO : STD_LOGIC := '0'; + SIGNAL ni1li : STD_LOGIC := '0'; + SIGNAL ni1ll : STD_LOGIC := '0'; + SIGNAL ni1lO : STD_LOGIC := '0'; + SIGNAL ni1Oi : STD_LOGIC := '0'; + SIGNAL ni1Ol : STD_LOGIC := '0'; + SIGNAL ni1OO : STD_LOGIC := '0'; + SIGNAL nii0i : STD_LOGIC := '0'; + SIGNAL nii0l : STD_LOGIC := '0'; + SIGNAL nii0O : STD_LOGIC := '0'; + SIGNAL nii1i : STD_LOGIC := '0'; + SIGNAL nii1l : STD_LOGIC := '0'; + SIGNAL nii1O : STD_LOGIC := '0'; + SIGNAL nl0ll : STD_LOGIC := '0'; + SIGNAL nl0lO : STD_LOGIC := '0'; + SIGNAL nl0Oi : STD_LOGIC := '0'; + SIGNAL nl0Ol : STD_LOGIC := '0'; + SIGNAL nl0OO : STD_LOGIC := '0'; + SIGNAL nli0i : STD_LOGIC := '0'; + SIGNAL nli0l : STD_LOGIC := '0'; + SIGNAL nli0O : STD_LOGIC := '0'; + SIGNAL nli1i : STD_LOGIC := '0'; + SIGNAL nli1l : STD_LOGIC := '0'; + SIGNAL nli1O : STD_LOGIC := '0'; + SIGNAL nliii : STD_LOGIC := '0'; + SIGNAL nliil : STD_LOGIC := '0'; + SIGNAL nliiO : STD_LOGIC := '0'; + SIGNAL nlili : STD_LOGIC := '0'; + SIGNAL nlill : STD_LOGIC := '0'; + SIGNAL nlilO : STD_LOGIC := '0'; + SIGNAL nliOi : STD_LOGIC := '0'; + SIGNAL nliOl : STD_LOGIC := '0'; + SIGNAL nliOO : STD_LOGIC := '0'; + SIGNAL nll0i : STD_LOGIC := '0'; + SIGNAL nll0l : STD_LOGIC := '0'; + SIGNAL nll0O : STD_LOGIC := '0'; + SIGNAL nll1i : STD_LOGIC := '0'; + SIGNAL nll1l : STD_LOGIC := '0'; + SIGNAL nll1O : STD_LOGIC := '0'; + SIGNAL nllii : STD_LOGIC := '0'; + SIGNAL nlOi : STD_LOGIC := '0'; + SIGNAL wire_nllO_CLRN : STD_LOGIC; + SIGNAL wire_nllO_w_lg_nll0i250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_nll0O249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_nliiO252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_nliOl271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_nll1i281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_nll1l288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO_w_lg_nll1O295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni : STD_LOGIC := '0'; + SIGNAL nlil : STD_LOGIC := '0'; + SIGNAL nll : STD_LOGIC := '0'; + SIGNAL nllil : STD_LOGIC := '0'; + SIGNAL wire_nlO_CLRN : STD_LOGIC; + SIGNAL wire_nlO_w_lg_nll61w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_nll63w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_nlil62w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_nll58w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0l_w_lg_dataout220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1i_w_lg_dataout200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O_w_lg_dataout210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil_w_lg_dataout233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_nl_dataout : STD_LOGIC; + SIGNAL wire_nl00i_dataout : STD_LOGIC; + SIGNAL wire_nl00l_dataout : STD_LOGIC; + SIGNAL wire_nl00O_dataout : STD_LOGIC; + SIGNAL wire_nl01i_dataout : STD_LOGIC; + SIGNAL wire_nl01l_dataout : STD_LOGIC; + SIGNAL wire_nl01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl10l_dataout : STD_LOGIC; + SIGNAL wire_nl10O_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_nO_w_lg_dataout97w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlii_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlii_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_nlii_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1iOi_addr_rd1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1iOi_addr_rd2 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1iOi_addr_wr : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1iOi_data_in : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_n1iOi_data_out1 : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_n1iOi_data_out2 : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_n1iOi_rst_l : STD_LOGIC; + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_w_lg_n1i1l54w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n10ii : STD_LOGIC; + SIGNAL n10il : STD_LOGIC; + SIGNAL n10li : STD_LOGIC; + SIGNAL n10ll : STD_LOGIC; + SIGNAL n1i0i : STD_LOGIC; + SIGNAL n1i1l : STD_LOGIC; + SIGNAL n1iii : STD_LOGIC; + SIGNAL n1iil : STD_LOGIC; + SIGNAL n1iiO : STD_LOGIC; + SIGNAL wire_w_rdskchrp_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rdskchrp_range11w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rdskchrp_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rdskchrp_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rdskchrp_range3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sudi_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sudi_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sudi_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sudi_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + COMPONENT cycloneiv_hssi_rx_digis_ram16x14_syn + GENERIC + ( + ram_width : NATURAL; + read_access_time : NATURAL; + write_access_time : NATURAL + ); + PORT + ( + addr_rd1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + addr_rd2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + addr_wr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + data_out1 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + data_out2 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + re_l : IN STD_LOGIC; + rst_l : IN STD_LOGIC; + we : IN STD_LOGIC + ); + END COMPONENT; + BEGIN + + wire_gnd <= '0'; + wire_vcc <= '1'; + wire_w_lg_n1i1l54w(0) <= NOT n1i1l; + wire_w_lg_soft_reset2w(0) <= NOT soft_reset; + align_det_sync <= nlOi; + audi <= ( nllii & nll0O & nll0l & nll0i & nll1O & nll1l & nll1i & nliOO & nliOl & nliOi & nlilO & nlill & nlili & nliiO); + audi_pre <= ( nliil & nliii & nli0O & nli0l & nli0i & nli1O & nli1l & nli1i & nl0OO & nl0Ol & nl0Oi & nl0lO & nl0ll & nii0O); + n10ii <= (((((((((((wire_nllO_w_lg_nll0O249w(0) AND wire_nllO_w_lg_nll0i250w(0)) AND (NOT (wire_n1i_dataout XOR nliiO))) AND (NOT (wire_n1l_dataout XOR nlili))) AND (NOT (wire_n1O_dataout XOR nlill))) AND (NOT (wire_n0i_dataout XOR nlilO))) AND (NOT (wire_n0l_dataout XOR nliOi))) AND (NOT (wire_n0O_dataout XOR nliOl))) AND (NOT (wire_nii_dataout XOR nliOO))) AND (NOT (wire_nil_dataout XOR nll1i))) AND (NOT (wire_niO_dataout XOR nll1l))) AND (NOT (wire_nli_dataout XOR nll1O))); + n10il <= (((((((((((wire_nllO_w_lg_nll0O249w(0) AND wire_nllO_w_lg_nll0i250w(0)) AND (NOT (wire_nllO_w_lg_nliiO252w(0) XOR (NOT (nlOOOi40 XOR nlOOOi39))))) AND (NOT (nlili XOR rdskchrp(1)))) AND (NOT (nlill XOR rdskchrp(2)))) AND (NOT (nlilO XOR rdskchrp(3)))) AND (NOT (nliOi XOR rdskchrp(4)))) AND (NOT (wire_nllO_w_lg_nliOl271w(0) XOR (NOT (nlOOll42 XOR nlOOll41))))) AND (NOT (nliOO XOR rdskchrp(6)))) AND (NOT (wire_nllO_w_lg_nll1i281w(0) XOR (NOT (nlOOiO44 XOR nlOOiO43))))) AND (NOT (wire_nllO_w_lg_nll1l288w(0) XOR (NOT (nlOOii46 XOR nlOOii45))))) AND (NOT (wire_nllO_w_lg_nll1O295w(0) XOR (NOT (nlOO0l48 XOR nlOO0l47))))); + n10li <= (n1i0i OR nlOiO); + n10ll <= ((wire_nlO_w_lg_nll61w(0) OR wire_nlO_w_lg_nll63w(0)) OR (NOT (n10lO14 XOR n10lO13))); + n1i0i <= (nll AND ((n1iil OR n1iii) OR (NOT (n1i0l4 XOR n1i0l3)))); + n1i1l <= (((wire_niil_w_lg_niii332w(0) AND wire_niil_w_lg_ni0O333w(0)) AND wire_niil_w_lg_ni0l335w(0)) AND wire_niil_w_lg_n0Oi337w(0)); + n1iii <= (((((((((((((NOT sudi(10)) AND (NOT sudi(12))) AND (NOT (wire_n1i_w_lg_dataout200w(0) XOR (NOT (n11il30 XOR n11il29))))) AND (NOT (wire_n1l_dataout XOR sudi(1)))) AND (NOT (wire_n1O_w_lg_dataout210w(0) XOR (NOT (n110O32 XOR n110O31))))) AND (NOT (wire_n0i_dataout XOR sudi(3)))) AND (NOT (wire_n0l_w_lg_dataout220w(0) XOR (NOT (n110i34 XOR n110i33))))) AND (NOT (wire_n0O_dataout XOR sudi(5)))) AND (NOT (wire_nii_dataout XOR sudi(6)))) AND (NOT (wire_nil_w_lg_dataout233w(0) XOR (NOT (n111l36 XOR n111l35))))) AND (NOT (wire_niO_dataout XOR sudi(8)))) AND (NOT (wire_nli_dataout XOR sudi(9)))) AND (nlOOOO38 XOR nlOOOO37)); + n1iil <= (((((((((((((NOT sudi(10)) AND (NOT sudi(12))) AND (NOT (sudi(0) XOR rdskchrp(0)))) AND (NOT (sudi(1) XOR rdskchrp(1)))) AND (NOT (sudi(2) XOR rdskchrp(2)))) AND (NOT ((sudi(3) XOR rdskchrp(3)) XOR (NOT (n101O20 XOR n101O19))))) AND (NOT ((sudi(4) XOR rdskchrp(4)) XOR (NOT (n101i22 XOR n101i21))))) AND (NOT (sudi(5) XOR rdskchrp(5)))) AND (NOT (sudi(6) XOR rdskchrp(6)))) AND (NOT ((sudi(7) XOR rdskchrp(7)) XOR (NOT (n11Ol24 XOR n11Ol23))))) AND (NOT (sudi(8) XOR rdskchrp(8)))) AND (NOT ((sudi(9) XOR rdskchrp(9)) XOR (NOT (n11lO26 XOR n11lO25))))) AND (n11li28 XOR n11li27)); + n1iiO <= '1'; + rd_align <= ((n10il OR n10ii) OR (NOT (n100l18 XOR n100l17))); + wire_w_rdskchrp_range21w(0) <= rdskchrp(0); + wire_w_rdskchrp_range11w(0) <= rdskchrp(5); + wire_w_rdskchrp_range7w(0) <= rdskchrp(7); + wire_w_rdskchrp_range5w(0) <= rdskchrp(8); + wire_w_rdskchrp_range3w(0) <= rdskchrp(9); + wire_w_sudi_range141w(0) <= sudi(0); + wire_w_sudi_range149w(0) <= sudi(2); + wire_w_sudi_range161w(0) <= sudi(4); + wire_w_sudi_range177w(0) <= sudi(7); + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n100l17 <= n100l18; + END IF; + if (now = 0 ns) then + n100l17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n100l18 <= n100l17; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n101i21 <= n101i22; + END IF; + if (now = 0 ns) then + n101i21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n101i22 <= n101i21; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n101O19 <= n101O20; + END IF; + if (now = 0 ns) then + n101O19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n101O20 <= n101O19; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10iO15 <= n10iO16; + END IF; + if (now = 0 ns) then + n10iO15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10iO16 <= n10iO15; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10lO13 <= n10lO14; + END IF; + if (now = 0 ns) then + n10lO13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10lO14 <= n10lO13; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10Ol11 <= n10Ol12; + END IF; + if (now = 0 ns) then + n10Ol11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10Ol12 <= n10Ol11; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10OO10 <= n10OO9; + END IF; + END PROCESS; + wire_n10OO10_w_lg_w_lg_q39w40w(0) <= wire_n10OO10_w_lg_q39w(0) AND niii; + wire_n10OO10_w_lg_q39w(0) <= n10OO10 XOR n10OO9; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n10OO9 <= n10OO10; + END IF; + if (now = 0 ns) then + n10OO9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n110i33 <= n110i34; + END IF; + if (now = 0 ns) then + n110i33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n110i34 <= n110i33; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n110O31 <= n110O32; + END IF; + if (now = 0 ns) then + n110O31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n110O32 <= n110O31; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n111l35 <= n111l36; + END IF; + if (now = 0 ns) then + n111l35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n111l36 <= n111l35; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11il29 <= n11il30; + END IF; + if (now = 0 ns) then + n11il29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11il30 <= n11il29; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11li27 <= n11li28; + END IF; + if (now = 0 ns) then + n11li27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11li28 <= n11li27; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11lO25 <= n11lO26; + END IF; + if (now = 0 ns) then + n11lO25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11lO26 <= n11lO25; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11Ol23 <= n11Ol24; + END IF; + if (now = 0 ns) then + n11Ol23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n11Ol24 <= n11Ol23; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1i0l3 <= n1i0l4; + END IF; + if (now = 0 ns) then + n1i0l3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1i0l4 <= n1i0l3; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1i1i7 <= n1i1i8; + END IF; + if (now = 0 ns) then + n1i1i7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1i1i8 <= n1i1i7; + END IF; + END PROCESS; + wire_n1i1i8_w_lg_w_lg_q36w37w(0) <= wire_n1i1i8_w_lg_q36w(0) AND ni0O; + wire_n1i1i8_w_lg_q36w(0) <= n1i1i8 XOR n1i1i7; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1i1O5 <= n1i1O6; + END IF; + if (now = 0 ns) then + n1i1O5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1i1O6 <= n1i1O5; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1ili1 <= n1ili2; + END IF; + if (now = 0 ns) then + n1ili1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN n1ili2 <= n1ili1; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOO0l47 <= nlOO0l48; + END IF; + if (now = 0 ns) then + nlOO0l47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOO0l48 <= nlOO0l47; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOii45 <= nlOOii46; + END IF; + if (now = 0 ns) then + nlOOii45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOii46 <= nlOOii45; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOiO43 <= nlOOiO44; + END IF; + if (now = 0 ns) then + nlOOiO43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOiO44 <= nlOOiO43; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOll41 <= nlOOll42; + END IF; + if (now = 0 ns) then + nlOOll41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOll42 <= nlOOll41; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOOi39 <= nlOOOi40; + END IF; + if (now = 0 ns) then + nlOOOi39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOOi40 <= nlOOOi39; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOOO37 <= nlOOOO38; + END IF; + if (now = 0 ns) then + nlOOOO37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlOOOO38 <= nlOOOO37; + END IF; + END PROCESS; + PROCESS (clk_1, wire_ni00i_PRN) + BEGIN + IF (wire_ni00i_PRN = '0') THEN + ni00l <= '1'; + ni10i <= '1'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + ni00l <= wire_nilil_dataout; + ni10i <= wire_niiil_dataout; + END IF; + if (now = 0 ns) then + ni00l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni10i <= '1' after 1 ps; + end if; + END PROCESS; + wire_ni00i_PRN <= ((n10iO16 XOR n10iO15) AND wire_w_lg_soft_reset2w(0)); + PROCESS (rcvd_clk, wire_niil_PRN, soft_reset) + BEGIN + IF (wire_niil_PRN = '0') THEN + n0Oi <= '1'; + ni0l <= '1'; + ni0O <= '1'; + niii <= '1'; + niiO <= '1'; + nlliO <= '1'; + nllli <= '1'; + nllll <= '1'; + nlllO <= '1'; + nllOi <= '1'; + nllOl <= '1'; + nllOO <= '1'; + nlO0i <= '1'; + nlO0l <= '1'; + nlO0O <= '1'; + nlO1i <= '1'; + nlO1l <= '1'; + nlO1O <= '1'; + nlOii <= '1'; + nlOil <= '1'; + nlOiO <= '1'; + ELSIF (soft_reset = '1') THEN + n0Oi <= '0'; + ni0l <= '0'; + ni0O <= '0'; + niii <= '0'; + niiO <= '0'; + nlliO <= '0'; + nllli <= '0'; + nllll <= '0'; + nlllO <= '0'; + nllOi <= '0'; + nllOl <= '0'; + nllOO <= '0'; + nlO0i <= '0'; + nlO0l <= '0'; + nlO0O <= '0'; + nlO1i <= '0'; + nlO1l <= '0'; + nlO1O <= '0'; + nlOii <= '0'; + nlOil <= '0'; + nlOiO <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + n0Oi <= wire_nili_dataout; + ni0l <= wire_nill_dataout; + ni0O <= wire_nilO_dataout; + niii <= wire_niOi_dataout; + niiO <= wire_nliO_dataout; + nlliO <= wire_nlOll_dataout; + nllli <= wire_nlOlO_dataout; + nllll <= wire_nlOOi_dataout; + nlllO <= wire_nlOOl_dataout; + nllOi <= wire_nlOOO_dataout; + nllOl <= wire_n11i_dataout; + nllOO <= wire_n11l_dataout; + nlO0i <= wire_n10O_dataout; + nlO0l <= wire_n1ii_dataout; + nlO0O <= wire_n1il_dataout; + nlO1i <= wire_n11O_dataout; + nlO1l <= wire_n10i_dataout; + nlO1O <= wire_n10l_dataout; + nlOii <= wire_n1iO_dataout; + nlOil <= wire_n1li_dataout; + nlOiO <= wire_n0Ol_dataout; + END IF; + END PROCESS; + wire_niil_PRN <= (n10Ol12 XOR n10Ol11); + wire_niil_w_lg_nlOiO60w(0) <= nlOiO AND nlOil; + wire_niil_w_lg_n0Oi337w(0) <= NOT n0Oi; + wire_niil_w_lg_ni0l335w(0) <= NOT ni0l; + wire_niil_w_lg_ni0O333w(0) <= NOT ni0O; + wire_niil_w_lg_niii332w(0) <= NOT niii; + PROCESS (clk_1, wire_nllO_CLRN) + BEGIN + IF (wire_nllO_CLRN = '0') THEN + ni00O <= '0'; + ni01i <= '0'; + ni01l <= '0'; + ni01O <= '0'; + ni0ii <= '0'; + ni0il <= '0'; + ni0iO <= '0'; + ni0li <= '0'; + ni0ll <= '0'; + ni0lO <= '0'; + ni0Oi <= '0'; + ni0Ol <= '0'; + ni0OO <= '0'; + ni10l <= '0'; + ni10O <= '0'; + ni11l <= '0'; + ni11O <= '0'; + ni1ii <= '0'; + ni1il <= '0'; + ni1iO <= '0'; + ni1li <= '0'; + ni1ll <= '0'; + ni1lO <= '0'; + ni1Oi <= '0'; + ni1Ol <= '0'; + ni1OO <= '0'; + nii0i <= '0'; + nii0l <= '0'; + nii0O <= '0'; + nii1i <= '0'; + nii1l <= '0'; + nii1O <= '0'; + nl0ll <= '0'; + nl0lO <= '0'; + nl0Oi <= '0'; + nl0Ol <= '0'; + nl0OO <= '0'; + nli0i <= '0'; + nli0l <= '0'; + nli0O <= '0'; + nli1i <= '0'; + nli1l <= '0'; + nli1O <= '0'; + nliii <= '0'; + nliil <= '0'; + nliiO <= '0'; + nlili <= '0'; + nlill <= '0'; + nlilO <= '0'; + nliOi <= '0'; + nliOl <= '0'; + nliOO <= '0'; + nll0i <= '0'; + nll0l <= '0'; + nll0O <= '0'; + nll1i <= '0'; + nll1l <= '0'; + nll1O <= '0'; + nllii <= '0'; + nlOi <= '0'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + ni00O <= wire_niliO_dataout; + ni01i <= wire_nil0l_dataout; + ni01l <= wire_nil0O_dataout; + ni01O <= wire_nilii_dataout; + ni0ii <= wire_nilli_dataout; + ni0il <= wire_nilll_dataout; + ni0iO <= wire_nillO_dataout; + ni0li <= wire_nilOi_dataout; + ni0ll <= wire_nilOl_dataout; + ni0lO <= wire_nilOO_dataout; + ni0Oi <= wire_niO1i_dataout; + ni0Ol <= wire_niO1l_dataout; + ni0OO <= wire_niO1O_dataout; + ni10l <= wire_niiiO_dataout; + ni10O <= wire_niili_dataout; + ni11l <= niiO; + ni11O <= wire_niiii_dataout; + ni1ii <= wire_niill_dataout; + ni1il <= wire_niilO_dataout; + ni1iO <= wire_niiOi_dataout; + ni1li <= wire_niiOl_dataout; + ni1ll <= wire_niiOO_dataout; + ni1lO <= wire_nil1i_dataout; + ni1Oi <= wire_nil1l_dataout; + ni1Ol <= wire_nil1O_dataout; + ni1OO <= wire_nil0i_dataout; + nii0i <= wire_niOii_dataout; + nii0l <= wire_niOil_dataout; + nii0O <= wire_n1iOi_data_out2(0); + nii1i <= wire_niO0i_dataout; + nii1l <= wire_niO0l_dataout; + nii1O <= wire_niO0O_dataout; + nl0ll <= wire_n1iOi_data_out2(1); + nl0lO <= wire_n1iOi_data_out2(2); + nl0Oi <= wire_n1iOi_data_out2(3); + nl0Ol <= wire_n1iOi_data_out2(4); + nl0OO <= wire_n1iOi_data_out2(5); + nli0i <= wire_n1iOi_data_out2(9); + nli0l <= wire_n1iOi_data_out2(10); + nli0O <= wire_n1iOi_data_out2(11); + nli1i <= wire_n1iOi_data_out2(6); + nli1l <= wire_n1iOi_data_out2(7); + nli1O <= wire_n1iOi_data_out2(8); + nliii <= wire_n1iOi_data_out2(12); + nliil <= wire_n1iOi_data_out2(13); + nliiO <= wire_n1iOi_data_out1(0); + nlili <= wire_n1iOi_data_out1(1); + nlill <= wire_n1iOi_data_out1(2); + nlilO <= wire_n1iOi_data_out1(3); + nliOi <= wire_n1iOi_data_out1(4); + nliOl <= wire_n1iOi_data_out1(5); + nliOO <= wire_n1iOi_data_out1(6); + nll0i <= wire_n1iOi_data_out1(10); + nll0l <= wire_n1iOi_data_out1(11); + nll0O <= wire_n1iOi_data_out1(12); + nll1i <= wire_n1iOi_data_out1(7); + nll1l <= wire_n1iOi_data_out1(8); + nll1O <= wire_n1iOi_data_out1(9); + nllii <= wire_n1iOi_data_out1(13); + nlOi <= ni11l; + END IF; + END PROCESS; + wire_nllO_CLRN <= ((n1i1O6 XOR n1i1O5) AND wire_w_lg_soft_reset2w(0)); + wire_nllO_w_lg_nll0i250w(0) <= NOT nll0i; + wire_nllO_w_lg_nll0O249w(0) <= NOT nll0O; + wire_nllO_w_lg_nliiO252w(0) <= nliiO XOR wire_w_rdskchrp_range21w(0); + wire_nllO_w_lg_nliOl271w(0) <= nliOl XOR wire_w_rdskchrp_range11w(0); + wire_nllO_w_lg_nll1i281w(0) <= nll1i XOR wire_w_rdskchrp_range7w(0); + wire_nllO_w_lg_nll1l288w(0) <= nll1l XOR wire_w_rdskchrp_range5w(0); + wire_nllO_w_lg_nll1O295w(0) <= nll1O XOR wire_w_rdskchrp_range3w(0); + PROCESS (rcvd_clk, soft_reset, wire_nlO_CLRN) + BEGIN + IF (soft_reset = '1') THEN + ni <= '1'; + nlil <= '1'; + nll <= '1'; + nllil <= '1'; + ELSIF (wire_nlO_CLRN = '0') THEN + ni <= '0'; + nlil <= '0'; + nll <= '0'; + nllil <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + ni <= wire_nO_dataout; + nlil <= nll; + nll <= ni; + nllil <= wire_nlOli_dataout; + END IF; + if (now = 0 ns) then + ni <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllil <= '1' after 1 ps; + end if; + END PROCESS; + wire_nlO_CLRN <= (n1ili2 XOR n1ili1); + wire_nlO_w_lg_nll61w(0) <= nll AND wire_niil_w_lg_nlOiO60w(0); + wire_nlO_w_lg_nll63w(0) <= nll AND wire_nlO_w_lg_nlil62w(0); + wire_nlO_w_lg_nlil62w(0) <= NOT nlil; + wire_nlO_w_lg_nll58w(0) <= NOT nll; + wire_n00i_dataout <= nllOO WHEN n10li = '1' ELSE nlO1i; + wire_n00l_dataout <= nlO1i WHEN n10li = '1' ELSE nlO1l; + wire_n00O_dataout <= nlO1l WHEN n10li = '1' ELSE nlO1O; + wire_n01i_dataout <= nlllO WHEN n10li = '1' ELSE nllOi; + wire_n01l_dataout <= nllOi WHEN n10li = '1' ELSE nllOl; + wire_n01O_dataout <= nllOl WHEN n10li = '1' ELSE nllOO; + wire_n0i_dataout <= rdskchrp(3) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(3)); + wire_n0ii_dataout <= nlO1O WHEN n10li = '1' ELSE nlO0i; + wire_n0il_dataout <= nlO0i WHEN n10li = '1' ELSE nlO0l; + wire_n0iO_dataout <= nlO0l WHEN n10li = '1' ELSE nlO0O; + wire_n0l_dataout <= rdskchrp(4) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(4)); + wire_n0l_w_lg_dataout220w(0) <= wire_n0l_dataout XOR wire_w_sudi_range161w(0); + wire_n0li_dataout <= nlO0O WHEN n10li = '1' ELSE nlOii; + wire_n0ll_dataout <= nlOii WHEN n10li = '1' ELSE nlOil; + wire_n0O_dataout <= rdskchrp(5) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(5)); + wire_n0Ol_dataout <= wire_n0OO_dataout AND NOT(n10ll); + wire_n0OO_dataout <= nlOiO OR n1i0i; + wire_n10i_dataout <= wire_n00l_dataout AND NOT(n10ll); + wire_n10l_dataout <= wire_n00O_dataout AND NOT(n10ll); + wire_n10O_dataout <= wire_n0ii_dataout AND NOT(n10ll); + wire_n11i_dataout <= wire_n01l_dataout AND NOT(n10ll); + wire_n11l_dataout <= wire_n01O_dataout AND NOT(n10ll); + wire_n11O_dataout <= wire_n00i_dataout AND NOT(n10ll); + wire_n1i_dataout <= rdskchrp(0) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(0)); + wire_n1i_w_lg_dataout200w(0) <= wire_n1i_dataout XOR wire_w_sudi_range141w(0); + wire_n1ii_dataout <= wire_n0il_dataout AND NOT(n10ll); + wire_n1il_dataout <= wire_n0iO_dataout AND NOT(n10ll); + wire_n1iO_dataout <= wire_n0li_dataout AND NOT(n10ll); + wire_n1l_dataout <= rdskchrp(1) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(1)); + wire_n1li_dataout <= wire_n0ll_dataout AND NOT(n10ll); + wire_n1ll_dataout <= nlOil WHEN n10li = '1' ELSE nllil; + wire_n1lO_dataout <= nllil WHEN n10li = '1' ELSE nlliO; + wire_n1O_dataout <= rdskchrp(2) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(2)); + wire_n1O_w_lg_dataout210w(0) <= wire_n1O_dataout XOR wire_w_sudi_range149w(0); + wire_n1Oi_dataout <= nlliO WHEN n10li = '1' ELSE nllli; + wire_n1Ol_dataout <= nllli WHEN n10li = '1' ELSE nllll; + wire_n1OO_dataout <= nllll WHEN n10li = '1' ELSE nlllO; + wire_nii_dataout <= rdskchrp(6) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(6)); + wire_niiii_dataout <= wire_niOiO_dataout AND NOT(wire_nl_dataout); + wire_niiil_dataout <= wire_niOli_dataout OR wire_nl_dataout; + wire_niiiO_dataout <= wire_niOll_dataout AND NOT(wire_nl_dataout); + wire_niili_dataout <= wire_niOlO_dataout AND NOT(wire_nl_dataout); + wire_niill_dataout <= wire_niOOi_dataout AND NOT(wire_nl_dataout); + wire_niilO_dataout <= wire_niOOl_dataout AND NOT(wire_nl_dataout); + wire_niiOi_dataout <= wire_niOOO_dataout AND NOT(wire_nl_dataout); + wire_niiOl_dataout <= wire_nl11i_dataout AND NOT(wire_nl_dataout); + wire_niiOO_dataout <= wire_nl11l_dataout AND NOT(wire_nl_dataout); + wire_nil_dataout <= rdskchrp(7) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(7)); + wire_nil_w_lg_dataout233w(0) <= wire_nil_dataout XOR wire_w_sudi_range177w(0); + wire_nil0i_dataout <= wire_nl10O_dataout AND NOT(wire_nl_dataout); + wire_nil0l_dataout <= wire_nl1ii_dataout AND NOT(wire_nl_dataout); + wire_nil0O_dataout <= wire_nl1il_dataout AND NOT(wire_nl_dataout); + wire_nil1i_dataout <= wire_nl11O_dataout AND NOT(wire_nl_dataout); + wire_nil1l_dataout <= wire_nl10i_dataout AND NOT(wire_nl_dataout); + wire_nil1O_dataout <= wire_nl10l_dataout AND NOT(wire_nl_dataout); + wire_nili_dataout <= wire_niOl_dataout AND NOT(wire_nlO_w_lg_nll58w(0)); + wire_nilii_dataout <= wire_nl1iO_dataout AND NOT(wire_nl_dataout); + wire_nilil_dataout <= wire_nl1li_dataout OR wire_nl_dataout; + wire_niliO_dataout <= wire_nl1ll_dataout AND NOT(wire_nl_dataout); + wire_nill_dataout <= wire_niOO_dataout AND NOT(wire_nlO_w_lg_nll58w(0)); + wire_nilli_dataout <= wire_nl1lO_dataout AND NOT(wire_nl_dataout); + wire_nilll_dataout <= wire_nl1Oi_dataout AND NOT(wire_nl_dataout); + wire_nillO_dataout <= wire_nl1Ol_dataout AND NOT(wire_nl_dataout); + wire_nilO_dataout <= wire_nl1i_dataout AND NOT(wire_nlO_w_lg_nll58w(0)); + wire_nilOi_dataout <= wire_nl1OO_dataout AND NOT(wire_nl_dataout); + wire_nilOl_dataout <= wire_nl01i_dataout AND NOT(wire_nl_dataout); + wire_nilOO_dataout <= wire_nl01l_dataout AND NOT(wire_nl_dataout); + wire_niO_dataout <= rdskchrp(8) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(8)); + wire_niO0i_dataout <= wire_nl00O_dataout AND NOT(wire_nl_dataout); + wire_niO0l_dataout <= wire_nl0ii_dataout AND NOT(wire_nl_dataout); + wire_niO0O_dataout <= wire_nl0il_dataout AND NOT(wire_nl_dataout); + wire_niO1i_dataout <= wire_nl01O_dataout AND NOT(wire_nl_dataout); + wire_niO1l_dataout <= wire_nl00i_dataout AND NOT(wire_nl_dataout); + wire_niO1O_dataout <= wire_nl00l_dataout AND NOT(wire_nl_dataout); + wire_niOi_dataout <= wire_nl1l_dataout AND NOT(wire_nlO_w_lg_nll58w(0)); + wire_niOii_dataout <= wire_nl0iO_dataout AND NOT(wire_nl_dataout); + wire_niOil_dataout <= wire_nl0li_dataout AND NOT(wire_nl_dataout); + wire_niOiO_dataout <= ni01O AND wire_nO_w_lg_dataout97w(0); + wire_niOl_dataout <= wire_nl1O_dataout OR n1i0i; + wire_niOli_dataout <= ni11O OR NOT(wire_nO_w_lg_dataout97w(0)); + wire_niOll_dataout <= ni10i AND wire_nO_w_lg_dataout97w(0); + wire_niOlO_dataout <= ni10l AND wire_nO_w_lg_dataout97w(0); + wire_niOO_dataout <= wire_nl0i_dataout AND NOT(n1i0i); + wire_niOOi_dataout <= ni10O AND wire_nO_w_lg_dataout97w(0); + wire_niOOl_dataout <= ni1ii AND wire_nO_w_lg_dataout97w(0); + wire_niOOO_dataout <= ni1il AND wire_nO_w_lg_dataout97w(0); + wire_nl_dataout <= fifo_rst_rd_gp WHEN sel_gp_md = '1' ELSE fifo_rst_rd_qd; + wire_nl00i_dataout <= ni0Oi AND wire_nO_w_lg_dataout97w(0); + wire_nl00l_dataout <= ni0Ol AND wire_nO_w_lg_dataout97w(0); + wire_nl00O_dataout <= ni0OO AND wire_nO_w_lg_dataout97w(0); + wire_nl01i_dataout <= ni0li AND wire_nO_w_lg_dataout97w(0); + wire_nl01l_dataout <= ni0ll AND wire_nO_w_lg_dataout97w(0); + wire_nl01O_dataout <= ni0lO AND wire_nO_w_lg_dataout97w(0); + wire_nl0i_dataout <= wire_nlii_o(2) WHEN wire_w_lg_n1i1l54w(0) = '1' ELSE ni0l; + wire_nl0ii_dataout <= nii1i AND wire_nO_w_lg_dataout97w(0); + wire_nl0il_dataout <= nii1l AND wire_nO_w_lg_dataout97w(0); + wire_nl0iO_dataout <= nii1O AND wire_nO_w_lg_dataout97w(0); + wire_nl0l_dataout <= wire_nlii_o(3) WHEN wire_w_lg_n1i1l54w(0) = '1' ELSE ni0O; + wire_nl0li_dataout <= nii0i AND wire_nO_w_lg_dataout97w(0); + wire_nl0O_dataout <= wire_nlii_o(4) WHEN wire_w_lg_n1i1l54w(0) = '1' ELSE niii; + wire_nl10i_dataout <= ni1lO AND wire_nO_w_lg_dataout97w(0); + wire_nl10l_dataout <= ni1Oi AND wire_nO_w_lg_dataout97w(0); + wire_nl10O_dataout <= ni1Ol AND wire_nO_w_lg_dataout97w(0); + wire_nl11i_dataout <= ni1iO AND wire_nO_w_lg_dataout97w(0); + wire_nl11l_dataout <= ni1li AND wire_nO_w_lg_dataout97w(0); + wire_nl11O_dataout <= ni1ll AND wire_nO_w_lg_dataout97w(0); + wire_nl1i_dataout <= wire_nl0l_dataout AND NOT(n1i0i); + wire_nl1ii_dataout <= ni1OO AND wire_nO_w_lg_dataout97w(0); + wire_nl1il_dataout <= ni01i AND wire_nO_w_lg_dataout97w(0); + wire_nl1iO_dataout <= ni01l AND wire_nO_w_lg_dataout97w(0); + wire_nl1l_dataout <= wire_nl0O_dataout OR n1i0i; + wire_nl1li_dataout <= nii0l OR NOT(wire_nO_w_lg_dataout97w(0)); + wire_nl1ll_dataout <= ni00l AND wire_nO_w_lg_dataout97w(0); + wire_nl1lO_dataout <= ni00O AND wire_nO_w_lg_dataout97w(0); + wire_nl1O_dataout <= wire_nlii_o(1) WHEN wire_w_lg_n1i1l54w(0) = '1' ELSE n0Oi; + wire_nl1Oi_dataout <= ni0ii AND wire_nO_w_lg_dataout97w(0); + wire_nl1Ol_dataout <= ni0il AND wire_nO_w_lg_dataout97w(0); + wire_nl1OO_dataout <= ni0iO AND wire_nO_w_lg_dataout97w(0); + wire_nli_dataout <= rdskchrp(9) WHEN rdskposdisp = '1' ELSE (NOT rdskchrp(9)); + wire_nliO_dataout <= wire_nlli_dataout OR n1i0i; + wire_nlli_dataout <= niiO AND NOT(n1i1l); + wire_nlOli_dataout <= wire_n1ll_dataout OR n10ll; + wire_nlOll_dataout <= wire_n1lO_dataout AND NOT(n10ll); + wire_nlOlO_dataout <= wire_n1Oi_dataout AND NOT(n10ll); + wire_nlOOi_dataout <= wire_n1Ol_dataout AND NOT(n10ll); + wire_nlOOl_dataout <= wire_n1OO_dataout AND NOT(n10ll); + wire_nlOOO_dataout <= wire_n01i_dataout AND NOT(n10ll); + wire_nO_dataout <= en_dskw_gp WHEN sel_gp_md = '1' ELSE en_dskw_qd; + wire_nO_w_lg_dataout97w(0) <= NOT wire_nO_dataout; + wire_nlii_a <= ( wire_n10OO10_w_lg_w_lg_q39w40w & wire_n1i1i8_w_lg_w_lg_q36w37w & ni0l & n0Oi & "1"); + wire_nlii_b <= ( "1" & "1" & "1" & "0" & "1"); + nlii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlii_a, + b => wire_nlii_b, + cin => wire_gnd, + o => wire_nlii_o + ); + wire_n1iOi_addr_rd1 <= ( nii0l & nii0i & nii1O & nii1l & nii1i & ni0OO & ni0Ol & ni0Oi & ni0lO & ni0ll & ni0li & ni0iO & ni0il & ni0ii & ni00O & ni00l); + wire_n1iOi_addr_rd2 <= ( ni01O & ni01l & ni01i & ni1OO & ni1Ol & ni1Oi & ni1lO & ni1ll & ni1li & ni1iO & ni1il & ni1ii & ni10O & ni10l & ni10i & ni11O); + wire_n1iOi_addr_wr <= ( nlOil & nlOii & nlO0O & nlO0l & nlO0i & nlO1O & nlO1l & nlO1i & nllOO & nllOl & nllOi & nlllO & nllll & nllli & nlliO & nllil); + wire_n1iOi_data_in <= ( sudi(13 DOWNTO 0)); + wire_n1iOi_rst_l <= wire_w_lg_soft_reset2w(0); + n1iOi : cycloneiv_hssi_rx_digis_ram16x14_syn + GENERIC MAP ( + ram_width => 14, + read_access_time => 0, + write_access_time => 0 + ) + PORT MAP ( + addr_rd1 => wire_n1iOi_addr_rd1, + addr_rd2 => wire_n1iOi_addr_rd2, + addr_wr => wire_n1iOi_addr_wr, + clk => rcvd_clk, + data_in => wire_n1iOi_data_in, + data_out1 => wire_n1iOi_data_out1, + data_out2 => wire_n1iOi_data_out2, + re_l => wire_gnd, + rst_l => wire_n1iOi_rst_l, + we => wire_vcc + ); + + END RTL; --cycloneiv_hssi_rx_digi_dskw_fifo +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 162 mux21 158 oper_add 7 oper_less_than 17 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_freqdet IS + PORT + ( + eidle_exit : IN STD_LOGIC; + fref : IN STD_LOGIC; + freq_lock : OUT STD_LOGIC; + fvcobyn : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + gen2ngen1_indv : IN STD_LOGIC; + hard_reset : IN STD_LOGIC; + pd : IN STD_LOGIC; + ppm_cnt_latch : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + ppm_cnt_reset : IN STD_LOGIC; + ppmsel : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + rauto_speed_ena : IN STD_LOGIC; + rforcehigh : IN STD_LOGIC; + rforcelow : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rppm_gen1_2xcnt_en : IN STD_LOGIC; + rppm_post_eidle_del : IN STD_LOGIC; + scan_mode : IN STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_freqdet; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_freqdet IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nlll0O57 : STD_LOGIC := '0'; + SIGNAL nlll0O58 : STD_LOGIC := '0'; + SIGNAL nllOOi55 : STD_LOGIC := '0'; + SIGNAL nllOOi56 : STD_LOGIC := '0'; + SIGNAL nlO00i21 : STD_LOGIC := '0'; + SIGNAL nlO00i22 : STD_LOGIC := '0'; + SIGNAL wire_nlO00i22_w_lg_w_lg_q87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO00i22_w_lg_q87w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO00l19 : STD_LOGIC := '0'; + SIGNAL nlO00l20 : STD_LOGIC := '0'; + SIGNAL wire_nlO00l20_w_lg_w_lg_q84w85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO00l20_w_lg_q84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO00O17 : STD_LOGIC := '0'; + SIGNAL nlO00O18 : STD_LOGIC := '0'; + SIGNAL wire_nlO00O18_w_lg_w_lg_q78w79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO00O18_w_lg_q78w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO01i27 : STD_LOGIC := '0'; + SIGNAL nlO01i28 : STD_LOGIC := '0'; + SIGNAL wire_nlO01i28_w_lg_w_lg_q168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO01i28_w_lg_q168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO01l25 : STD_LOGIC := '0'; + SIGNAL nlO01l26 : STD_LOGIC := '0'; + SIGNAL wire_nlO01l26_w_lg_w_lg_q165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO01l26_w_lg_q165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO01O23 : STD_LOGIC := '0'; + SIGNAL nlO01O24 : STD_LOGIC := '0'; + SIGNAL wire_nlO01O24_w_lg_w_lg_q108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO01O24_w_lg_q108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO0ii15 : STD_LOGIC := '0'; + SIGNAL nlO0ii16 : STD_LOGIC := '0'; + SIGNAL wire_nlO0ii16_w_lg_w_lg_q72w73w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0ii16_w_lg_q72w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO0iO13 : STD_LOGIC := '0'; + SIGNAL nlO0iO14 : STD_LOGIC := '0'; + SIGNAL nlO0ll11 : STD_LOGIC := '0'; + SIGNAL nlO0ll12 : STD_LOGIC := '0'; + SIGNAL nlO0Oi10 : STD_LOGIC := '0'; + SIGNAL nlO0Oi9 : STD_LOGIC := '0'; + SIGNAL nlO0Ol7 : STD_LOGIC := '0'; + SIGNAL nlO0Ol8 : STD_LOGIC := '0'; + SIGNAL nlO10i47 : STD_LOGIC := '0'; + SIGNAL nlO10i48 : STD_LOGIC := '0'; + SIGNAL wire_nlO10i48_w_lg_w_lg_q355w356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO10i48_w_lg_q355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO10l45 : STD_LOGIC := '0'; + SIGNAL nlO10l46 : STD_LOGIC := '0'; + SIGNAL nlO10O43 : STD_LOGIC := '0'; + SIGNAL nlO10O44 : STD_LOGIC := '0'; + SIGNAL nlO11i53 : STD_LOGIC := '0'; + SIGNAL nlO11i54 : STD_LOGIC := '0'; + SIGNAL nlO11l51 : STD_LOGIC := '0'; + SIGNAL nlO11l52 : STD_LOGIC := '0'; + SIGNAL wire_nlO11l52_w_lg_w_lg_q434w435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO11l52_w_lg_q434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO11O49 : STD_LOGIC := '0'; + SIGNAL nlO11O50 : STD_LOGIC := '0'; + SIGNAL wire_nlO11O50_w_lg_w_lg_q431w432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO11O50_w_lg_q431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1ii41 : STD_LOGIC := '0'; + SIGNAL nlO1ii42 : STD_LOGIC := '0'; + SIGNAL nlO1li39 : STD_LOGIC := '0'; + SIGNAL nlO1li40 : STD_LOGIC := '0'; + SIGNAL wire_nlO1li40_w_lg_w_lg_q266w267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1li40_w_lg_q266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1ll37 : STD_LOGIC := '0'; + SIGNAL nlO1ll38 : STD_LOGIC := '0'; + SIGNAL wire_nlO1ll38_w_lg_w_lg_q261w262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1ll38_w_lg_q261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1lO35 : STD_LOGIC := '0'; + SIGNAL nlO1lO36 : STD_LOGIC := '0'; + SIGNAL wire_nlO1lO36_w_lg_w_lg_q255w256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1lO36_w_lg_q255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1Oi33 : STD_LOGIC := '0'; + SIGNAL nlO1Oi34 : STD_LOGIC := '0'; + SIGNAL wire_nlO1Oi34_w_lg_w_lg_q219w220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1Oi34_w_lg_q219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1Ol31 : STD_LOGIC := '0'; + SIGNAL nlO1Ol32 : STD_LOGIC := '0'; + SIGNAL wire_nlO1Ol32_w_lg_w_lg_q182w183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1Ol32_w_lg_q182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1OO29 : STD_LOGIC := '0'; + SIGNAL nlO1OO30 : STD_LOGIC := '0'; + SIGNAL wire_nlO1OO30_w_lg_w_lg_q177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1OO30_w_lg_q177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOi0l3 : STD_LOGIC := '0'; + SIGNAL nlOi0l4 : STD_LOGIC := '0'; + SIGNAL nlOi1l5 : STD_LOGIC := '0'; + SIGNAL nlOi1l6 : STD_LOGIC := '0'; + SIGNAL nlOiil1 : STD_LOGIC := '0'; + SIGNAL nlOiil2 : STD_LOGIC := '0'; + SIGNAL n0lOO : STD_LOGIC := '0'; + SIGNAL n1i : STD_LOGIC := '0'; + SIGNAL nii : STD_LOGIC := '0'; + SIGNAL wire_n0O_CLRN : STD_LOGIC; + SIGNAL n10iO : STD_LOGIC := '0'; + SIGNAL n1ilO : STD_LOGIC := '0'; + SIGNAL wire_n1ill_CLRN : STD_LOGIC; + SIGNAL n0lOi : STD_LOGIC := '0'; + SIGNAL ni00O : STD_LOGIC := '0'; + SIGNAL wire_ni00l_CLRN : STD_LOGIC; + SIGNAL wire_ni00l_w_lg_w_lg_n0lOi8w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni00l_w_lg_n0lOi512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni00l_w_lg_n0lOi8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni00l_w_lg_w_lg_w_lg_n0lOi1w2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni00l_w_lg_w_lg_n0lOi1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni00l_w_lg_n0lOi1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl0lO : STD_LOGIC := '0'; + SIGNAL ni00i : STD_LOGIC := '0'; + SIGNAL ni01i : STD_LOGIC := '0'; + SIGNAL ni01l : STD_LOGIC := '0'; + SIGNAL ni01O : STD_LOGIC := '0'; + SIGNAL ni10i : STD_LOGIC := '0'; + SIGNAL ni10l : STD_LOGIC := '0'; + SIGNAL ni10O : STD_LOGIC := '0'; + SIGNAL ni11O : STD_LOGIC := '0'; + SIGNAL ni1ii : STD_LOGIC := '0'; + SIGNAL ni1il : STD_LOGIC := '0'; + SIGNAL ni1iO : STD_LOGIC := '0'; + SIGNAL ni1li : STD_LOGIC := '0'; + SIGNAL ni1ll : STD_LOGIC := '0'; + SIGNAL ni1lO : STD_LOGIC := '0'; + SIGNAL ni1Oi : STD_LOGIC := '0'; + SIGNAL ni1Ol : STD_LOGIC := '0'; + SIGNAL ni1OO : STD_LOGIC := '0'; + SIGNAL nl00O : STD_LOGIC := '0'; + SIGNAL nl01l : STD_LOGIC := '0'; + SIGNAL nl0Ol : STD_LOGIC := '0'; + SIGNAL wire_nl0Oi_w_lg_ni00i1130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni01i1135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni01l1133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni01O1131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni1ll1145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni1lO1143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni1Oi1141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni1Ol1139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi_w_lg_ni1OO1137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n00ii : STD_LOGIC := '0'; + SIGNAL n00il : STD_LOGIC := '0'; + SIGNAL n00iO : STD_LOGIC := '0'; + SIGNAL n00li : STD_LOGIC := '0'; + SIGNAL n00ll : STD_LOGIC := '0'; + SIGNAL n00lO : STD_LOGIC := '0'; + SIGNAL n00Oi : STD_LOGIC := '0'; + SIGNAL n00Ol : STD_LOGIC := '0'; + SIGNAL n0lli : STD_LOGIC := '0'; + SIGNAL n0lll : STD_LOGIC := '0'; + SIGNAL n0llO : STD_LOGIC := '0'; + SIGNAL n100i : STD_LOGIC := '0'; + SIGNAL n100l : STD_LOGIC := '0'; + SIGNAL n100O : STD_LOGIC := '0'; + SIGNAL n101l : STD_LOGIC := '0'; + SIGNAL n101O : STD_LOGIC := '0'; + SIGNAL n10ii : STD_LOGIC := '0'; + SIGNAL n10il : STD_LOGIC := '0'; + SIGNAL n1iOi : STD_LOGIC := '0'; + SIGNAL n1iOO : STD_LOGIC := '0'; + SIGNAL niiOl : STD_LOGIC := '0'; + SIGNAL niiOO : STD_LOGIC := '0'; + SIGNAL nil0i : STD_LOGIC := '0'; + SIGNAL nil0l : STD_LOGIC := '0'; + SIGNAL nil0O : STD_LOGIC := '0'; + SIGNAL nil1i : STD_LOGIC := '0'; + SIGNAL nil1l : STD_LOGIC := '0'; + SIGNAL nil1O : STD_LOGIC := '0'; + SIGNAL nilii : STD_LOGIC := '0'; + SIGNAL nilil : STD_LOGIC := '0'; + SIGNAL niliO : STD_LOGIC := '0'; + SIGNAL nilli : STD_LOGIC := '0'; + SIGNAL nilll : STD_LOGIC := '0'; + SIGNAL nillO : STD_LOGIC := '0'; + SIGNAL nilOi : STD_LOGIC := '0'; + SIGNAL nilOl : STD_LOGIC := '0'; + SIGNAL nilOO : STD_LOGIC := '0'; + SIGNAL niO1i : STD_LOGIC := '0'; + SIGNAL nl01i : STD_LOGIC := '0'; + SIGNAL nl0ii : STD_LOGIC := '0'; + SIGNAL nl0il : STD_LOGIC := '0'; + SIGNAL nl0iO : STD_LOGIC := '0'; + SIGNAL nl0li : STD_LOGIC := '0'; + SIGNAL nl1iO : STD_LOGIC := '0'; + SIGNAL nl1li : STD_LOGIC := '0'; + SIGNAL nli1i : STD_LOGIC := '0'; + SIGNAL wire_nl0OO_CLRN : STD_LOGIC; + SIGNAL wire_nl0OO_w_lg_n0lli15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO_w_lg_n0lll10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO_w_lg_n0llO511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO_w_lg_nl0iO515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO_w_lg_nl1li697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli1O : STD_LOGIC := '0'; + SIGNAL nliil : STD_LOGIC := '0'; + SIGNAL wire_nliii_PRN : STD_LOGIC; + SIGNAL nliiO : STD_LOGIC := '0'; + SIGNAL nlilO : STD_LOGIC := '0'; + SIGNAL wire_nlill_PRN : STD_LOGIC; + SIGNAL nlli : STD_LOGIC := '0'; + SIGNAL wire_nliO_CLRN : STD_LOGIC; + SIGNAL nlii : STD_LOGIC := '0'; + SIGNAL nlil : STD_LOGIC := '0'; + SIGNAL nliOi : STD_LOGIC := '0'; + SIGNAL nll0i : STD_LOGIC := '0'; + SIGNAL nll0l : STD_LOGIC := '0'; + SIGNAL nll0O : STD_LOGIC := '0'; + SIGNAL nll1l : STD_LOGIC := '0'; + SIGNAL nll1O : STD_LOGIC := '0'; + SIGNAL nllii : STD_LOGIC := '0'; + SIGNAL nllil : STD_LOGIC := '0'; + SIGNAL nlliO : STD_LOGIC := '0'; + SIGNAL nllli : STD_LOGIC := '0'; + SIGNAL nllll : STD_LOGIC := '0'; + SIGNAL nlllO : STD_LOGIC := '0'; + SIGNAL nllO : STD_LOGIC := '0'; + SIGNAL nllOi : STD_LOGIC := '0'; + SIGNAL nllOl : STD_LOGIC := '0'; + SIGNAL nllOO : STD_LOGIC := '0'; + SIGNAL nlO0i : STD_LOGIC := '0'; + SIGNAL nlO0l : STD_LOGIC := '0'; + SIGNAL nlO1i : STD_LOGIC := '0'; + SIGNAL nlO1l : STD_LOGIC := '0'; + SIGNAL nlO1O : STD_LOGIC := '0'; + SIGNAL nlOi : STD_LOGIC := '0'; + SIGNAL nlOO : STD_LOGIC := '0'; + SIGNAL wire_nlOl_CLRN : STD_LOGIC; + SIGNAL wire_nlOl_PRN : STD_LOGIC; + SIGNAL wire_nlOl_w_lg_w_lg_w_lg_w_lg_w1102w1104w1106w1108w1109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_w_lg_w1102w1104w1106w1108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_w1102w1104w1106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w1102w1104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w1102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_w_lg_w_lg_nlO0i1094w1096w1098w1100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_w_lg_nlO0i1094w1096w1098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_w_lg_nlO0i1094w1096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nll0i1114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nll0l1112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nll1O1116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nllil1110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nlllO1107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nllOi1105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nllOl1103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nllOO1101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nlO0i1094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nlO0l31w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nlO1i1099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nlO1l1097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl_w_lg_nlO1O1095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0i_w_lg_dataout18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0iii_dataout : STD_LOGIC; + SIGNAL wire_n0iil_dataout : STD_LOGIC; + SIGNAL wire_n0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0l_w_lg_dataout22w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0lii_dataout : STD_LOGIC; + SIGNAL wire_n0lil_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl_dataout : STD_LOGIC; + SIGNAL wire_n101i_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10li_dataout : STD_LOGIC; + SIGNAL wire_n10ll_dataout : STD_LOGIC; + SIGNAL wire_n10lO_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n10Oi_dataout : STD_LOGIC; + SIGNAL wire_n10Ol_dataout : STD_LOGIC; + SIGNAL wire_n10OO_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n11Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Ol_dataout : STD_LOGIC; + SIGNAL wire_n11OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iii_dataout : STD_LOGIC; + SIGNAL wire_n1iil_dataout : STD_LOGIC; + SIGNAL wire_n1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1ili_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0il_dataout : STD_LOGIC; + SIGNAL wire_ni0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0li_dataout : STD_LOGIC; + SIGNAL wire_ni0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0O_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00i_dataout : STD_LOGIC; + SIGNAL wire_nl00l_dataout : STD_LOGIC; + SIGNAL wire_nl01O_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nli0O_dataout : STD_LOGIC; + SIGNAL wire_nli0O_w_lg_dataout509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlili_dataout : STD_LOGIC; + SIGNAL wire_nlili_w_lg_dataout507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOl_w_lg_dataout328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_n0liO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0liO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n0liO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0OOO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0OOO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0OOO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiOi_a : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_niiOi_b : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_niiOi_o : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl0i_a : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL wire_nl0i_b : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL wire_nl0i_o : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL wire_nl0i_w_o_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1il_a : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl1il_b : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl1il_o : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl1l_a : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl1l_b : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl1l_o : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nli0l_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nli0l_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nli0l_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nli0l_w_o_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n000l_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n000l_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_n000l_o : STD_LOGIC; + SIGNAL wire_n001l_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n001l_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n001l_o : STD_LOGIC; + SIGNAL wire_n010l_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n010l_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n010l_o : STD_LOGIC; + SIGNAL wire_n011i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n011i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n011i_o : STD_LOGIC; + SIGNAL wire_n01iO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n01iO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n01iO_o : STD_LOGIC; + SIGNAL wire_n01Oi_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n01Oi_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n01Oi_o : STD_LOGIC; + SIGNAL wire_n1liO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1liO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1liO_o : STD_LOGIC; + SIGNAL wire_n1lOl_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1lOl_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1lOl_o : STD_LOGIC; + SIGNAL wire_n1O1O_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1O1O_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1O1O_o : STD_LOGIC; + SIGNAL wire_n1Oil_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oil_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oil_o : STD_LOGIC; + SIGNAL wire_n1OlO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1OlO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1OlO_o : STD_LOGIC; + SIGNAL wire_nl0l_a : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl0l_b : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nl0l_o : STD_LOGIC; + SIGNAL wire_nl1O_a : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL wire_nl1O_b : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL wire_nl1O_o : STD_LOGIC; + SIGNAL wire_nl1Ol_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1Ol_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1Ol_o : STD_LOGIC; + SIGNAL wire_nl1OO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1OO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1OO_o : STD_LOGIC; + SIGNAL wire_nli0i_a : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nli0i_b : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nli0i_o : STD_LOGIC; + SIGNAL wire_nli1l_a : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nli1l_b : STD_LOGIC_VECTOR (16 DOWNTO 0); + SIGNAL wire_nli1l_o : STD_LOGIC; + SIGNAL wire_w_lg_w_lg_nlO0li105w691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlO0li105w617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ppmsel_range1162w1184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlO0li105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlO0OO20w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOiii721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rppm_post_eidle_del136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ppmsel_range1164w1165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlllii : STD_LOGIC; + SIGNAL nlllil : STD_LOGIC; + SIGNAL nllliO : STD_LOGIC; + SIGNAL nlllli : STD_LOGIC; + SIGNAL nlllll : STD_LOGIC; + SIGNAL nllllO : STD_LOGIC; + SIGNAL nlllOi : STD_LOGIC; + SIGNAL nlllOl : STD_LOGIC; + SIGNAL nlllOO : STD_LOGIC; + SIGNAL nllO0i : STD_LOGIC; + SIGNAL nllO0l : STD_LOGIC; + SIGNAL nllO0O : STD_LOGIC; + SIGNAL nllO1i : STD_LOGIC; + SIGNAL nllO1l : STD_LOGIC; + SIGNAL nllO1O : STD_LOGIC; + SIGNAL nllOii : STD_LOGIC; + SIGNAL nllOil : STD_LOGIC; + SIGNAL nllOiO : STD_LOGIC; + SIGNAL nllOli : STD_LOGIC; + SIGNAL nllOll : STD_LOGIC; + SIGNAL nllOlO : STD_LOGIC; + SIGNAL nllOOl : STD_LOGIC; + SIGNAL nllOOO : STD_LOGIC; + SIGNAL nlO0il : STD_LOGIC; + SIGNAL nlO0li : STD_LOGIC; + SIGNAL nlO0OO : STD_LOGIC; + SIGNAL nlO1iO : STD_LOGIC; + SIGNAL nlOi0i : STD_LOGIC; + SIGNAL nlOi1i : STD_LOGIC; + SIGNAL nlOi1O : STD_LOGIC; + SIGNAL nlOiii : STD_LOGIC; + SIGNAL wire_w_ppmsel_range1162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_ppmsel_range1164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_vcc <= '1'; + wire_w_lg_w_lg_nlO0li105w691w(0) <= wire_w_lg_nlO0li105w(0) AND ni01O; + wire_w_lg_w_lg_nlO0li105w617w(0) <= wire_w_lg_nlO0li105w(0) AND nilOl; + wire_w_lg_w_ppmsel_range1162w1184w(0) <= wire_w_ppmsel_range1162w(0) AND wire_w_lg_w_ppmsel_range1164w1165w(0); + wire_w_lg_nlO0li105w(0) <= NOT nlO0li; + wire_w_lg_nlO0OO20w(0) <= NOT nlO0OO; + wire_w_lg_nlOiii721w(0) <= NOT nlOiii; + wire_w_lg_rppm_post_eidle_del136w(0) <= NOT rppm_post_eidle_del; + wire_w_lg_w_ppmsel_range1164w1165w(0) <= NOT wire_w_ppmsel_range1164w(0); + freq_lock <= wire_n11Oi_dataout; + nlllii <= (nlOi0i AND nlllil); + nlllil <= (((((ppmsel(0) AND ppmsel(1)) AND ppmsel(2)) AND ppmsel(3)) AND ppmsel(4)) AND ppmsel(5)); + nllliO <= (nlOi0i AND nlllli); + nlllli <= (((((ppmsel(0) AND ppmsel(1)) AND (NOT ppmsel(2))) AND (NOT ppmsel(3))) AND (NOT ppmsel(4))) AND (NOT ppmsel(5))); + nlllll <= (nlOi0i AND nllllO); + nllllO <= ((((wire_w_lg_w_ppmsel_range1162w1184w(0) AND (NOT ppmsel(2))) AND (NOT ppmsel(3))) AND (NOT ppmsel(4))) AND (NOT ppmsel(5))); + nlllOi <= (nlOi0i AND nlllOl); + nlllOl <= ((((((NOT ppmsel(0)) AND ppmsel(1)) AND (NOT ppmsel(2))) AND (NOT ppmsel(3))) AND (NOT ppmsel(4))) AND (NOT ppmsel(5))); + nlllOO <= (nlOi0i AND nllO1i); + nllO0i <= (nlOi0i AND nllO0l); + nllO0l <= ((((((NOT ppmsel(0)) AND wire_w_lg_w_ppmsel_range1164w1165w(0)) AND (NOT ppmsel(2))) AND ppmsel(3)) AND (NOT ppmsel(4))) AND (NOT ppmsel(5))); + nllO0O <= (nlOi0i AND nllOii); + nllO1i <= ((((((NOT ppmsel(0)) AND wire_w_lg_w_ppmsel_range1164w1165w(0)) AND ppmsel(2)) AND (NOT ppmsel(3))) AND (NOT ppmsel(4))) AND (NOT ppmsel(5))); + nllO1l <= (nlOi0i AND nllO1O); + nllO1O <= ((((wire_w_lg_w_ppmsel_range1162w1184w(0) AND (NOT ppmsel(2))) AND ppmsel(3)) AND (NOT ppmsel(4))) AND (NOT ppmsel(5))); + nllOii <= ((((((NOT ppmsel(0)) AND wire_w_lg_w_ppmsel_range1164w1165w(0)) AND (NOT ppmsel(2))) AND (NOT ppmsel(3))) AND ppmsel(4)) AND (NOT ppmsel(5))); + nllOil <= (nlOi0i AND nllOiO); + nllOiO <= ((((((NOT ppmsel(0)) AND wire_w_lg_w_ppmsel_range1164w1165w(0)) AND (NOT ppmsel(2))) AND (NOT ppmsel(3))) AND (NOT ppmsel(4))) AND ppmsel(5)); + nllOli <= (((((((n00Oi AND n00lO) AND n00ll) AND n00li) AND n00iO) AND n00il) AND n00ii) AND n1iOi); + nllOll <= (wire_nl0OO_w_lg_nl1li697w(0) AND n00Ol); + nllOlO <= (nllOOl OR nl1li); + nllOOl <= (nli1i AND nl0ii); + nllOOO <= ((((((((((((((((wire_nl0Oi_w_lg_ni00i1130w(0) AND wire_nl0Oi_w_lg_ni01O1131w(0)) AND wire_nl0Oi_w_lg_ni01l1133w(0)) AND wire_nl0Oi_w_lg_ni01i1135w(0)) AND wire_nl0Oi_w_lg_ni1OO1137w(0)) AND wire_nl0Oi_w_lg_ni1Ol1139w(0)) AND wire_nl0Oi_w_lg_ni1Oi1141w(0)) AND wire_nl0Oi_w_lg_ni1lO1143w(0)) AND wire_nl0Oi_w_lg_ni1ll1145w(0)) AND ni1li) AND ni1iO) AND ni1il) AND ni1ii) AND ni10O) AND ni10l) AND ni10i) AND ni11O); + nlO0il <= (nlii AND wire_nlOl_w_lg_nlO0l31w(0)); + nlO0li <= ((nlO0OO AND rppm_gen1_2xcnt_en) AND (nlO0ll12 XOR nlO0ll11)); + nlO0OO <= (wire_n0i_w_lg_dataout18w(0) AND rauto_speed_ena); + nlO1iO <= ((((((((wire_nlOl_w_lg_w_lg_w_lg_w_lg_w1102w1104w1106w1108w1109w(0) AND wire_nlOl_w_lg_nllil1110w(0)) AND wire_nlOl_w_lg_nll0l1112w(0)) AND wire_nlOl_w_lg_nll0i1114w(0)) AND wire_nlOl_w_lg_nll1O1116w(0)) AND (NOT (nll0O XOR wire_w_lg_rppm_post_eidle_del136w(0)))) AND (NOT (nllii XOR rppm_post_eidle_del))) AND (NOT (nlliO XOR wire_w_lg_rppm_post_eidle_del136w(0)))) AND (NOT (nllll XOR rppm_post_eidle_del))); + nlOi0i <= (((wire_ni00l_w_lg_w_lg_n0lOi8w9w(0) AND wire_nl0OO_w_lg_n0lll10w(0)) AND (nlOi0l4 XOR nlOi0l3)) AND wire_nl0OO_w_lg_n0lli15w(0)); + nlOi1i <= '1'; + nlOi1O <= '0'; + nlOiii <= (wire_ni00l_w_lg_w_lg_w_lg_n0lOi1w2w3w(0) OR (NOT (nlOiil2 XOR nlOiil1))); + ppm_cnt_latch <= ( n10il & n10ii & n100O & n100l & n100i & n101O & n101l & n1iOO); + wire_w_ppmsel_range1162w(0) <= ppmsel(0); + wire_w_ppmsel_range1164w(0) <= ppmsel(1); + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlll0O57 <= nlll0O58; + END IF; + if (now = 0 ns) then + nlll0O57 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlll0O58 <= nlll0O57; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nllOOi55 <= nllOOi56; + END IF; + if (now = 0 ns) then + nllOOi55 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nllOOi56 <= nllOOi55; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO00i21 <= nlO00i22; + END IF; + if (now = 0 ns) then + nlO00i21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO00i22 <= nlO00i21; + END IF; + END PROCESS; + wire_nlO00i22_w_lg_w_lg_q87w88w(0) <= wire_nlO00i22_w_lg_q87w(0) AND nllOO; + wire_nlO00i22_w_lg_q87w(0) <= nlO00i22 XOR nlO00i21; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO00l19 <= nlO00l20; + END IF; + if (now = 0 ns) then + nlO00l19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO00l20 <= nlO00l19; + END IF; + END PROCESS; + wire_nlO00l20_w_lg_w_lg_q84w85w(0) <= wire_nlO00l20_w_lg_q84w(0) AND nllOl; + wire_nlO00l20_w_lg_q84w(0) <= nlO00l20 XOR nlO00l19; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO00O17 <= nlO00O18; + END IF; + if (now = 0 ns) then + nlO00O17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO00O18 <= nlO00O17; + END IF; + END PROCESS; + wire_nlO00O18_w_lg_w_lg_q78w79w(0) <= wire_nlO00O18_w_lg_q78w(0) AND nllli; + wire_nlO00O18_w_lg_q78w(0) <= nlO00O18 XOR nlO00O17; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO01i27 <= nlO01i28; + END IF; + if (now = 0 ns) then + nlO01i27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO01i28 <= nlO01i27; + END IF; + END PROCESS; + wire_nlO01i28_w_lg_w_lg_q168w169w(0) <= wire_nlO01i28_w_lg_q168w(0) AND nll0l; + wire_nlO01i28_w_lg_q168w(0) <= nlO01i28 XOR nlO01i27; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO01l25 <= nlO01l26; + END IF; + if (now = 0 ns) then + nlO01l25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO01l26 <= nlO01l25; + END IF; + END PROCESS; + wire_nlO01l26_w_lg_w_lg_q165w166w(0) <= wire_nlO01l26_w_lg_q165w(0) AND nll0i; + wire_nlO01l26_w_lg_q165w(0) <= nlO01l26 XOR nlO01l25; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO01O23 <= nlO01O24; + END IF; + if (now = 0 ns) then + nlO01O23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO01O24 <= nlO01O23; + END IF; + END PROCESS; + wire_nlO01O24_w_lg_w_lg_q108w109w(0) <= wire_nlO01O24_w_lg_q108w(0) AND nlO0li; + wire_nlO01O24_w_lg_q108w(0) <= nlO01O24 XOR nlO01O23; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0ii15 <= nlO0ii16; + END IF; + if (now = 0 ns) then + nlO0ii15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0ii16 <= nlO0ii15; + END IF; + END PROCESS; + wire_nlO0ii16_w_lg_w_lg_q72w73w(0) <= wire_nlO0ii16_w_lg_q72w(0) AND nll0O; + wire_nlO0ii16_w_lg_q72w(0) <= nlO0ii16 XOR nlO0ii15; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0iO13 <= nlO0iO14; + END IF; + if (now = 0 ns) then + nlO0iO13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0iO14 <= nlO0iO13; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0ll11 <= nlO0ll12; + END IF; + if (now = 0 ns) then + nlO0ll11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0ll12 <= nlO0ll11; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0Oi10 <= nlO0Oi9; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0Oi9 <= nlO0Oi10; + END IF; + if (now = 0 ns) then + nlO0Oi9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0Ol7 <= nlO0Ol8; + END IF; + if (now = 0 ns) then + nlO0Ol7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO0Ol8 <= nlO0Ol7; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO10i47 <= nlO10i48; + END IF; + if (now = 0 ns) then + nlO10i47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO10i48 <= nlO10i47; + END IF; + END PROCESS; + wire_nlO10i48_w_lg_w_lg_q355w356w(0) <= wire_nlO10i48_w_lg_q355w(0) AND wire_w_lg_nlO0li105w(0); + wire_nlO10i48_w_lg_q355w(0) <= nlO10i48 XOR nlO10i47; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO10l45 <= nlO10l46; + END IF; + if (now = 0 ns) then + nlO10l45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO10l46 <= nlO10l45; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO10O43 <= nlO10O44; + END IF; + if (now = 0 ns) then + nlO10O43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO10O44 <= nlO10O43; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO11i53 <= nlO11i54; + END IF; + if (now = 0 ns) then + nlO11i53 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO11i54 <= nlO11i53; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO11l51 <= nlO11l52; + END IF; + if (now = 0 ns) then + nlO11l51 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO11l52 <= nlO11l51; + END IF; + END PROCESS; + wire_nlO11l52_w_lg_w_lg_q434w435w(0) <= wire_nlO11l52_w_lg_q434w(0) AND niiOl; + wire_nlO11l52_w_lg_q434w(0) <= nlO11l52 XOR nlO11l51; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO11O49 <= nlO11O50; + END IF; + if (now = 0 ns) then + nlO11O49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO11O50 <= nlO11O49; + END IF; + END PROCESS; + wire_nlO11O50_w_lg_w_lg_q431w432w(0) <= wire_nlO11O50_w_lg_q431w(0) AND wire_nli0l_w_o_range430w(0); + wire_nlO11O50_w_lg_q431w(0) <= nlO11O50 XOR nlO11O49; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1ii41 <= nlO1ii42; + END IF; + if (now = 0 ns) then + nlO1ii41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1ii42 <= nlO1ii41; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1li39 <= nlO1li40; + END IF; + if (now = 0 ns) then + nlO1li39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1li40 <= nlO1li39; + END IF; + END PROCESS; + wire_nlO1li40_w_lg_w_lg_q266w267w(0) <= wire_nlO1li40_w_lg_q266w(0) AND nlO0i; + wire_nlO1li40_w_lg_q266w(0) <= nlO1li40 XOR nlO1li39; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1ll37 <= nlO1ll38; + END IF; + if (now = 0 ns) then + nlO1ll37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1ll38 <= nlO1ll37; + END IF; + END PROCESS; + wire_nlO1ll38_w_lg_w_lg_q261w262w(0) <= wire_nlO1ll38_w_lg_q261w(0) AND nlO1i; + wire_nlO1ll38_w_lg_q261w(0) <= nlO1ll38 XOR nlO1ll37; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1lO35 <= nlO1lO36; + END IF; + if (now = 0 ns) then + nlO1lO35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1lO36 <= nlO1lO35; + END IF; + END PROCESS; + wire_nlO1lO36_w_lg_w_lg_q255w256w(0) <= wire_nlO1lO36_w_lg_q255w(0) AND nlllO; + wire_nlO1lO36_w_lg_q255w(0) <= nlO1lO36 XOR nlO1lO35; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1Oi33 <= nlO1Oi34; + END IF; + if (now = 0 ns) then + nlO1Oi33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1Oi34 <= nlO1Oi33; + END IF; + END PROCESS; + wire_nlO1Oi34_w_lg_w_lg_q219w220w(0) <= wire_nlO1Oi34_w_lg_q219w(0) AND wire_nl0i_w_o_range218w(0); + wire_nlO1Oi34_w_lg_q219w(0) <= nlO1Oi34 XOR nlO1Oi33; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1Ol31 <= nlO1Ol32; + END IF; + if (now = 0 ns) then + nlO1Ol31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1Ol32 <= nlO1Ol31; + END IF; + END PROCESS; + wire_nlO1Ol32_w_lg_w_lg_q182w183w(0) <= wire_nlO1Ol32_w_lg_q182w(0) AND nllOO; + wire_nlO1Ol32_w_lg_q182w(0) <= nlO1Ol32 XOR nlO1Ol31; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1OO29 <= nlO1OO30; + END IF; + if (now = 0 ns) then + nlO1OO29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlO1OO30 <= nlO1OO29; + END IF; + END PROCESS; + wire_nlO1OO30_w_lg_w_lg_q177w178w(0) <= wire_nlO1OO30_w_lg_q177w(0) AND nlllO; + wire_nlO1OO30_w_lg_q177w(0) <= nlO1OO30 XOR nlO1OO29; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlOi0l3 <= nlOi0l4; + END IF; + if (now = 0 ns) then + nlOi0l3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlOi0l4 <= nlOi0l3; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlOi1l5 <= nlOi1l6; + END IF; + if (now = 0 ns) then + nlOi1l5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlOi1l6 <= nlOi1l5; + END IF; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlOiil1 <= nlOiil2; + END IF; + if (now = 0 ns) then + nlOiil1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref) + BEGIN + IF (fref = '1' AND fref'event) THEN nlOiil2 <= nlOiil1; + END IF; + END PROCESS; + PROCESS (fvcobyn, wire_nli0O_dataout) + BEGIN + IF (wire_nli0O_dataout = '1') THEN + n0lOO <= '1'; + ELSIF (fvcobyn = '1' AND fvcobyn'event) THEN + n0lOO <= wire_ni0ii_dataout; + END IF; + if (now = 0 ns) then + n0lOO <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (fref, hard_reset, wire_n0O_CLRN) + BEGIN + IF (hard_reset = '0') THEN + n1i <= '1'; + nii <= '1'; + ELSIF (wire_n0O_CLRN = '0') THEN + n1i <= '0'; + nii <= '0'; + ELSIF (fref = '1' AND fref'event) THEN + n1i <= nii; + nii <= nlOi1O; + END IF; + if (now = 0 ns) then + n1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii <= '1' after 1 ps; + end if; + END PROCESS; + wire_n0O_CLRN <= (nlOi1l6 XOR nlOi1l5); + PROCESS (fref, wire_n1ill_CLRN) + BEGIN + IF (wire_n1ill_CLRN = '0') THEN + n10iO <= '0'; + n1ilO <= '0'; + ELSIF (fref = '1' AND fref'event) THEN + IF (nlOi0i = '1') THEN + n10iO <= (nlllii OR ((((((((nllOil AND wire_n1O1O_o) OR (wire_n000l_o AND nllO0O)) OR (nllO0i AND wire_n1lOl_o)) OR (wire_n001l_o AND nllO1l)) OR (nlllOO AND wire_n1liO_o)) OR (wire_n01iO_o AND nlllOi)) OR (wire_n010l_o AND nlllll)) OR (wire_n011i_o AND nllliO))); + n1ilO <= (((((((((nllOil AND wire_n000l_o) OR (nllO0O AND wire_n001l_o)) OR (nllO0i AND wire_n01Oi_o)) OR (nllO1l AND wire_n01iO_o)) OR (nlllOO AND wire_n010l_o)) OR (nlllOi AND wire_n011i_o)) OR (nlllll AND wire_n1OlO_o)) OR (nllliO AND wire_n1Oil_o)) OR nlllii); + END IF; + END IF; + END PROCESS; + wire_n1ill_CLRN <= ((nlll0O58 XOR nlll0O57) AND wire_nlili_w_lg_dataout507w(0)); + PROCESS (fref, wire_nlili_dataout, wire_ni00l_CLRN) + BEGIN + IF (wire_nlili_dataout = '1') THEN + n0lOi <= '1'; + ni00O <= '1'; + ELSIF (wire_ni00l_CLRN = '0') THEN + n0lOi <= '0'; + ni00O <= '0'; + ELSIF (fref = '1' AND fref'event) THEN + n0lOi <= wire_n0O0l_dataout; + ni00O <= wire_niO1l_dataout; + END IF; + if (now = 0 ns) then + n0lOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni00O <= '1' after 1 ps; + end if; + END PROCESS; + wire_ni00l_CLRN <= (nllOOi56 XOR nllOOi55); + wire_ni00l_w_lg_w_lg_n0lOi8w9w(0) <= wire_ni00l_w_lg_n0lOi8w(0) AND n0llO; + wire_ni00l_w_lg_n0lOi512w(0) <= n0lOi AND wire_nl0OO_w_lg_n0llO511w(0); + wire_ni00l_w_lg_n0lOi8w(0) <= NOT n0lOi; + wire_ni00l_w_lg_w_lg_w_lg_n0lOi1w2w3w(0) <= wire_ni00l_w_lg_w_lg_n0lOi1w2w(0) OR n0lli; + wire_ni00l_w_lg_w_lg_n0lOi1w2w(0) <= wire_ni00l_w_lg_n0lOi1w(0) OR n0lll; + wire_ni00l_w_lg_n0lOi1w(0) <= n0lOi OR n0llO; + PROCESS (fvcobyn, wire_nli0O_dataout) + BEGIN + IF (wire_nli0O_dataout = '1') THEN + nl0lO <= '0'; + ELSIF (fvcobyn = '1' AND fvcobyn'event) THEN + IF (nllOOO = '1') THEN + nl0lO <= nlOi1i; + END IF; + END IF; + END PROCESS; + PROCESS (fvcobyn, wire_nli0O_dataout) + BEGIN + IF (wire_nli0O_dataout = '1') THEN + ni00i <= '0'; + ni01i <= '0'; + ni01l <= '0'; + ni01O <= '0'; + ni10i <= '0'; + ni10l <= '0'; + ni10O <= '0'; + ni11O <= '0'; + ni1ii <= '0'; + ni1il <= '0'; + ni1iO <= '0'; + ni1li <= '0'; + ni1ll <= '0'; + ni1lO <= '0'; + ni1Oi <= '0'; + ni1Ol <= '0'; + ni1OO <= '0'; + nl00O <= '0'; + nl01l <= '0'; + nl0Ol <= '0'; + ELSIF (fvcobyn = '1' AND fvcobyn'event) THEN + ni00i <= wire_niiiO_dataout; + ni01i <= wire_nii0O_dataout; + ni01l <= wire_niiii_dataout; + ni01O <= wire_niiil_dataout; + ni10i <= wire_ni0iO_dataout; + ni10l <= wire_ni0li_dataout; + ni10O <= wire_ni0ll_dataout; + ni11O <= wire_ni0il_dataout; + ni1ii <= wire_ni0lO_dataout; + ni1il <= wire_ni0Oi_dataout; + ni1iO <= wire_ni0Ol_dataout; + ni1li <= wire_ni0OO_dataout; + ni1ll <= wire_nii1i_dataout; + ni1lO <= wire_nii1l_dataout; + ni1Oi <= wire_nii1O_dataout; + ni1Ol <= wire_nii0i_dataout; + ni1OO <= wire_nii0l_dataout; + nl00O <= nl1iO; + nl01l <= nl00O; + nl0Ol <= wire_nli1l_o; + END IF; + END PROCESS; + wire_nl0Oi_w_lg_ni00i1130w(0) <= NOT ni00i; + wire_nl0Oi_w_lg_ni01i1135w(0) <= NOT ni01i; + wire_nl0Oi_w_lg_ni01l1133w(0) <= NOT ni01l; + wire_nl0Oi_w_lg_ni01O1131w(0) <= NOT ni01O; + wire_nl0Oi_w_lg_ni1ll1145w(0) <= NOT ni1ll; + wire_nl0Oi_w_lg_ni1lO1143w(0) <= NOT ni1lO; + wire_nl0Oi_w_lg_ni1Oi1141w(0) <= NOT ni1Oi; + wire_nl0Oi_w_lg_ni1Ol1139w(0) <= NOT ni1Ol; + wire_nl0Oi_w_lg_ni1OO1137w(0) <= NOT ni1OO; + PROCESS (fref, wire_nl0OO_CLRN) + BEGIN + IF (wire_nl0OO_CLRN = '0') THEN + n00ii <= '0'; + n00il <= '0'; + n00iO <= '0'; + n00li <= '0'; + n00ll <= '0'; + n00lO <= '0'; + n00Oi <= '0'; + n00Ol <= '0'; + n0lli <= '0'; + n0lll <= '0'; + n0llO <= '0'; + n100i <= '0'; + n100l <= '0'; + n100O <= '0'; + n101l <= '0'; + n101O <= '0'; + n10ii <= '0'; + n10il <= '0'; + n1iOi <= '0'; + n1iOO <= '0'; + niiOl <= '0'; + niiOO <= '0'; + nil0i <= '0'; + nil0l <= '0'; + nil0O <= '0'; + nil1i <= '0'; + nil1l <= '0'; + nil1O <= '0'; + nilii <= '0'; + nilil <= '0'; + niliO <= '0'; + nilli <= '0'; + nilll <= '0'; + nillO <= '0'; + nilOi <= '0'; + nilOl <= '0'; + nilOO <= '0'; + niO1i <= '0'; + nl01i <= '0'; + nl0ii <= '0'; + nl0il <= '0'; + nl0iO <= '0'; + nl0li <= '0'; + nl1iO <= '0'; + nl1li <= '0'; + nli1i <= '0'; + ELSIF (fref = '1' AND fref'event) THEN + n00ii <= wire_n0i1i_dataout; + n00il <= wire_n0i1l_dataout; + n00iO <= wire_n0i1O_dataout; + n00li <= wire_n0i0i_dataout; + n00ll <= wire_n0i0l_dataout; + n00lO <= wire_n0i0O_dataout; + n00Oi <= wire_n0iii_dataout; + n00Ol <= wire_n0O1i_dataout; + n0lli <= wire_n0O1l_dataout; + n0lll <= wire_n0O1O_dataout; + n0llO <= wire_n0O0i_dataout; + n100i <= wire_n10Oi_dataout; + n100l <= wire_n10Ol_dataout; + n100O <= wire_n10OO_dataout; + n101l <= wire_n10ll_dataout; + n101O <= wire_n10lO_dataout; + n10ii <= wire_n1i1i_dataout; + n10il <= wire_n1i1l_dataout; + n1iOi <= wire_n00OO_dataout; + n1iOO <= wire_n10li_dataout; + niiOl <= wire_niO1O_dataout; + niiOO <= wire_niO0i_dataout; + nil0i <= wire_niOil_dataout; + nil0l <= wire_niOiO_dataout; + nil0O <= wire_niOli_dataout; + nil1i <= wire_niO0l_dataout; + nil1l <= wire_niO0O_dataout; + nil1O <= wire_niOii_dataout; + nilii <= wire_niOll_dataout; + nilil <= wire_niOlO_dataout; + niliO <= wire_niOOi_dataout; + nilli <= wire_niOOl_dataout; + nilll <= wire_niOOO_dataout; + nillO <= wire_nl11i_dataout; + nilOi <= wire_nl11l_dataout; + nilOl <= wire_nl11O_dataout; + nilOO <= wire_nl10i_dataout; + niO1i <= nl1iO; + nl01i <= wire_nl00i_dataout; + nl0ii <= nl0il; + nl0il <= nl0Ol; + nl0iO <= nl0li; + nl0li <= nl0lO; + nl1iO <= ((wire_nl1OO_o AND wire_nl1Ol_o) OR nllOOl); + nl1li <= wire_nl01O_dataout; + nli1i <= wire_nli0i_o; + END IF; + END PROCESS; + wire_nl0OO_CLRN <= ((nlO11i54 XOR nlO11i53) AND wire_nlili_w_lg_dataout507w(0)); + wire_nl0OO_w_lg_n0lli15w(0) <= NOT n0lli; + wire_nl0OO_w_lg_n0lll10w(0) <= NOT n0lll; + wire_nl0OO_w_lg_n0llO511w(0) <= NOT n0llO; + wire_nl0OO_w_lg_nl0iO515w(0) <= NOT nl0iO; + wire_nl0OO_w_lg_nl1li697w(0) <= NOT nl1li; + PROCESS (fvcobyn, wire_nliii_PRN) + BEGIN + IF (wire_nliii_PRN = '0') THEN + nli1O <= '1'; + nliil <= '1'; + ELSIF (fvcobyn = '1' AND fvcobyn'event) THEN + nli1O <= nliil; + nliil <= pd; + END IF; + if (now = 0 ns) then + nli1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliil <= '1' after 1 ps; + end if; + END PROCESS; + wire_nliii_PRN <= ((nlO10l46 XOR nlO10l45) AND wire_nliOl_w_lg_dataout328w(0)); + PROCESS (fref, wire_nlill_PRN) + BEGIN + IF (wire_nlill_PRN = '0') THEN + nliiO <= '1'; + nlilO <= '1'; + ELSIF (fref = '1' AND fref'event) THEN + nliiO <= nlilO; + nlilO <= pd; + END IF; + if (now = 0 ns) then + nliiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlilO <= '1' after 1 ps; + end if; + END PROCESS; + wire_nlill_PRN <= ((nlO10O44 XOR nlO10O43) AND wire_nliOl_w_lg_dataout328w(0)); + PROCESS (fref, wire_n0l_dataout, wire_nliO_CLRN) + BEGIN + IF (wire_n0l_dataout = '1') THEN + nlli <= '1'; + ELSIF (wire_nliO_CLRN = '0') THEN + nlli <= '0'; + ELSIF (fref = '1' AND fref'event) THEN + nlli <= (nlOi XOR nllO); + END IF; + if (now = 0 ns) then + nlli <= '1' after 1 ps; + end if; + END PROCESS; + wire_nliO_CLRN <= (nlO0iO14 XOR nlO0iO13); + PROCESS (fref, wire_nlOl_PRN, wire_nlOl_CLRN) + BEGIN + IF (wire_nlOl_PRN = '0') THEN + nlii <= '1'; + nlil <= '1'; + nliOi <= '1'; + nll0i <= '1'; + nll0l <= '1'; + nll0O <= '1'; + nll1l <= '1'; + nll1O <= '1'; + nllii <= '1'; + nllil <= '1'; + nlliO <= '1'; + nllli <= '1'; + nllll <= '1'; + nlllO <= '1'; + nllO <= '1'; + nllOi <= '1'; + nllOl <= '1'; + nllOO <= '1'; + nlO0i <= '1'; + nlO0l <= '1'; + nlO1i <= '1'; + nlO1l <= '1'; + nlO1O <= '1'; + nlOi <= '1'; + nlOO <= '1'; + ELSIF (wire_nlOl_CLRN = '0') THEN + nlii <= '0'; + nlil <= '0'; + nliOi <= '0'; + nll0i <= '0'; + nll0l <= '0'; + nll0O <= '0'; + nll1l <= '0'; + nll1O <= '0'; + nllii <= '0'; + nllil <= '0'; + nlliO <= '0'; + nllli <= '0'; + nllll <= '0'; + nlllO <= '0'; + nllO <= '0'; + nllOi <= '0'; + nllOl <= '0'; + nllOO <= '0'; + nlO0i <= '0'; + nlO0l <= '0'; + nlO1i <= '0'; + nlO1l <= '0'; + nlO1O <= '0'; + nlOi <= '0'; + nlOO <= '0'; + ELSIF (fref = '1' AND fref'event) THEN + nlii <= nlil; + nlil <= eidle_exit; + nliOi <= wire_nlO0O_dataout; + nll0i <= wire_nlOiO_dataout; + nll0l <= wire_nlOli_dataout; + nll0O <= wire_nlOll_dataout; + nll1l <= wire_nlOii_dataout; + nll1O <= wire_nlOil_dataout; + nllii <= wire_nlOlO_dataout; + nllil <= wire_nlOOi_dataout; + nlliO <= wire_nlOOl_dataout; + nllli <= wire_nlOOO_dataout; + nllll <= wire_n11i_dataout; + nlllO <= wire_n11l_dataout; + nllO <= nlOi; + nllOi <= wire_n11O_dataout; + nllOl <= wire_n10i_dataout; + nllOO <= wire_n10l_dataout; + nlO0i <= wire_n1iO_dataout; + nlO0l <= nlii; + nlO1i <= wire_n10O_dataout; + nlO1l <= wire_n1ii_dataout; + nlO1O <= wire_n1il_dataout; + nlOi <= nlOO; + nlOO <= wire_w_lg_nlO0OO20w(0); + END IF; + END PROCESS; + wire_nlOl_CLRN <= ((nlO0Ol8 XOR nlO0Ol7) AND wire_n0l_w_lg_dataout22w(0)); + wire_nlOl_PRN <= (nlO0Oi10 XOR nlO0Oi9); + wire_nlOl_w_lg_w_lg_w_lg_w_lg_w1102w1104w1106w1108w1109w(0) <= wire_nlOl_w_lg_w_lg_w_lg_w1102w1104w1106w1108w(0) AND nllli; + wire_nlOl_w_lg_w_lg_w_lg_w1102w1104w1106w1108w(0) <= wire_nlOl_w_lg_w_lg_w1102w1104w1106w(0) AND wire_nlOl_w_lg_nlllO1107w(0); + wire_nlOl_w_lg_w_lg_w1102w1104w1106w(0) <= wire_nlOl_w_lg_w1102w1104w(0) AND wire_nlOl_w_lg_nllOi1105w(0); + wire_nlOl_w_lg_w1102w1104w(0) <= wire_nlOl_w1102w(0) AND wire_nlOl_w_lg_nllOl1103w(0); + wire_nlOl_w1102w(0) <= wire_nlOl_w_lg_w_lg_w_lg_w_lg_nlO0i1094w1096w1098w1100w(0) AND wire_nlOl_w_lg_nllOO1101w(0); + wire_nlOl_w_lg_w_lg_w_lg_w_lg_nlO0i1094w1096w1098w1100w(0) <= wire_nlOl_w_lg_w_lg_w_lg_nlO0i1094w1096w1098w(0) AND wire_nlOl_w_lg_nlO1i1099w(0); + wire_nlOl_w_lg_w_lg_w_lg_nlO0i1094w1096w1098w(0) <= wire_nlOl_w_lg_w_lg_nlO0i1094w1096w(0) AND wire_nlOl_w_lg_nlO1l1097w(0); + wire_nlOl_w_lg_w_lg_nlO0i1094w1096w(0) <= wire_nlOl_w_lg_nlO0i1094w(0) AND wire_nlOl_w_lg_nlO1O1095w(0); + wire_nlOl_w_lg_nll0i1114w(0) <= NOT nll0i; + wire_nlOl_w_lg_nll0l1112w(0) <= NOT nll0l; + wire_nlOl_w_lg_nll1O1116w(0) <= NOT nll1O; + wire_nlOl_w_lg_nllil1110w(0) <= NOT nllil; + wire_nlOl_w_lg_nlllO1107w(0) <= NOT nlllO; + wire_nlOl_w_lg_nllOi1105w(0) <= NOT nllOi; + wire_nlOl_w_lg_nllOl1103w(0) <= NOT nllOl; + wire_nlOl_w_lg_nllOO1101w(0) <= NOT nllOO; + wire_nlOl_w_lg_nlO0i1094w(0) <= NOT nlO0i; + wire_nlOl_w_lg_nlO0l31w(0) <= NOT nlO0l; + wire_nlOl_w_lg_nlO1i1099w(0) <= NOT nlO1i; + wire_nlOl_w_lg_nlO1l1097w(0) <= NOT nlO1l; + wire_nlOl_w_lg_nlO1O1095w(0) <= NOT nlO1O; + wire_n00i_dataout <= wire_niii_dataout AND wire_nl0l_o; + wire_n00l_dataout <= wire_niil_dataout AND wire_nl0l_o; + wire_n00O_dataout <= wire_niiO_dataout AND wire_nl0l_o; + wire_n00OO_dataout <= wire_n0iil_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n01i_dataout <= wire_ni0i_dataout AND wire_nl0l_o; + wire_n01l_dataout <= wire_ni0l_dataout AND wire_nl0l_o; + wire_n01O_dataout <= wire_ni0O_dataout AND wire_nl0l_o; + wire_n0i_dataout <= gen2ngen1_indv WHEN rindv_rx = '1' ELSE gen2ngen1_bundle; + wire_n0i_w_lg_dataout18w(0) <= NOT wire_n0i_dataout; + wire_n0i0i_dataout <= wire_n0ilO_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0i0l_dataout <= wire_n0iOi_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0i0O_dataout <= wire_n0iOl_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0i1i_dataout <= wire_n0iiO_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0i1l_dataout <= wire_n0ili_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0i1O_dataout <= wire_n0ill_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0ii_dataout <= wire_nili_dataout AND wire_nl0l_o; + wire_n0iii_dataout <= wire_n0iOO_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0iil_dataout <= wire_n0l1i_dataout OR nllOli; + wire_n0iiO_dataout <= wire_n0l1l_dataout OR nllOli; + wire_n0il_dataout <= wire_nill_dataout AND wire_nl0l_o; + wire_n0ili_dataout <= wire_n0l1O_dataout OR nllOli; + wire_n0ill_dataout <= wire_n0l0i_dataout OR nllOli; + wire_n0ilO_dataout <= wire_n0l0l_dataout OR nllOli; + wire_n0iO_dataout <= wire_nilO_dataout AND wire_nl0l_o; + wire_n0iOi_dataout <= wire_n0l0O_dataout OR nllOli; + wire_n0iOl_dataout <= wire_n0lii_dataout OR nllOli; + wire_n0iOO_dataout <= wire_n0lil_dataout OR nllOli; + wire_n0l_dataout <= n1i AND NOT(scan_mode); + wire_n0l_w_lg_dataout22w(0) <= NOT wire_n0l_dataout; + wire_n0l0i_dataout <= wire_n0liO_o(3) WHEN nl1li = '1' ELSE n00iO; + wire_n0l0l_dataout <= wire_n0liO_o(4) WHEN nl1li = '1' ELSE n00li; + wire_n0l0O_dataout <= wire_n0liO_o(5) WHEN nl1li = '1' ELSE n00ll; + wire_n0l1i_dataout <= wire_n0liO_o(0) WHEN nl1li = '1' ELSE n1iOi; + wire_n0l1l_dataout <= wire_n0liO_o(1) WHEN nl1li = '1' ELSE n00ii; + wire_n0l1O_dataout <= wire_n0liO_o(2) WHEN nl1li = '1' ELSE n00il; + wire_n0li_dataout <= wire_niOi_dataout AND wire_nl0l_o; + wire_n0lii_dataout <= wire_n0liO_o(6) WHEN nl1li = '1' ELSE n00lO; + wire_n0lil_dataout <= wire_n0liO_o(7) WHEN nl1li = '1' ELSE n00Oi; + wire_n0ll_dataout <= wire_niOl_dataout AND wire_nl0l_o; + wire_n0lO_dataout <= wire_niOO_dataout AND wire_nl0l_o; + wire_n0O0i_dataout <= wire_n0Oil_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0O0l_dataout <= wire_n0OiO_dataout OR wire_w_lg_nlOiii721w(0); + wire_n0O0O_dataout <= n0lli WHEN nllOlO = '1' ELSE wire_n0Oll_dataout; + wire_n0O1i_dataout <= wire_n0Oli_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0O1l_dataout <= wire_n0O0O_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0O1O_dataout <= wire_n0Oii_dataout AND NOT(wire_w_lg_nlOiii721w(0)); + wire_n0Oi_dataout <= wire_nl1i_dataout AND wire_nl0l_o; + wire_n0Oii_dataout <= n0lll WHEN nllOlO = '1' ELSE wire_n0OlO_dataout; + wire_n0Oil_dataout <= n0llO WHEN nllOlO = '1' ELSE wire_n0OOi_dataout; + wire_n0OiO_dataout <= n0lOi WHEN nllOlO = '1' ELSE wire_n0OOl_dataout; + wire_n0Ol_dataout <= nlO1iO AND wire_nl1O_o; + wire_n0Oli_dataout <= n00Ol OR nllOlO; + wire_n0Oll_dataout <= wire_n0OOO_o(1) WHEN nllOll = '1' ELSE n0lli; + wire_n0OlO_dataout <= wire_n0OOO_o(2) WHEN nllOll = '1' ELSE n0lll; + wire_n0OO_dataout <= wire_nl1l_o(0) AND wire_nl1O_o; + wire_n0OOi_dataout <= wire_n0OOO_o(3) WHEN nllOll = '1' ELSE n0llO; + wire_n0OOl_dataout <= wire_n0OOO_o(4) WHEN nllOll = '1' ELSE n0lOi; + wire_n101i_dataout <= n10iO WHEN nlO0li = '1' ELSE n1ilO; + wire_n10i_dataout <= wire_n0il_dataout AND NOT(nlO0il); + wire_n10l_dataout <= wire_n0iO_dataout AND NOT(nlO0il); + wire_n10li_dataout <= wire_n1i1O_dataout AND NOT(ppm_cnt_reset); + wire_n10ll_dataout <= wire_n1i0i_dataout AND NOT(ppm_cnt_reset); + wire_n10lO_dataout <= wire_n1i0l_dataout AND NOT(ppm_cnt_reset); + wire_n10O_dataout <= wire_n0li_dataout AND NOT(nlO0il); + wire_n10Oi_dataout <= wire_n1i0O_dataout AND NOT(ppm_cnt_reset); + wire_n10Ol_dataout <= wire_n1iii_dataout AND NOT(ppm_cnt_reset); + wire_n10OO_dataout <= wire_n1iil_dataout AND NOT(ppm_cnt_reset); + wire_n11i_dataout <= wire_n00l_dataout AND NOT(nlO0il); + wire_n11l_dataout <= wire_n00O_dataout AND NOT(nlO0il); + wire_n11O_dataout <= wire_n0ii_dataout AND NOT(nlO0il); + wire_n11Oi_dataout <= wire_n11Ol_dataout OR nll1l; + wire_n11Ol_dataout <= wire_n11OO_dataout OR rforcehigh; + wire_n11OO_dataout <= wire_n101i_dataout AND NOT(rforcelow); + wire_n1i0i_dataout <= n00ii WHEN nlOi0i = '1' ELSE n101l; + wire_n1i0l_dataout <= n00il WHEN nlOi0i = '1' ELSE n101O; + wire_n1i0O_dataout <= n00iO WHEN nlOi0i = '1' ELSE n100i; + wire_n1i1i_dataout <= wire_n1iiO_dataout AND NOT(ppm_cnt_reset); + wire_n1i1l_dataout <= wire_n1ili_dataout AND NOT(ppm_cnt_reset); + wire_n1i1O_dataout <= n1iOi WHEN nlOi0i = '1' ELSE n1iOO; + wire_n1ii_dataout <= wire_n0ll_dataout AND NOT(nlO0il); + wire_n1iii_dataout <= n00li WHEN nlOi0i = '1' ELSE n100l; + wire_n1iil_dataout <= n00ll WHEN nlOi0i = '1' ELSE n100O; + wire_n1iiO_dataout <= n00lO WHEN nlOi0i = '1' ELSE n10ii; + wire_n1il_dataout <= wire_n0lO_dataout AND NOT(nlO0il); + wire_n1ili_dataout <= n00Oi WHEN nlOi0i = '1' ELSE n10il; + wire_n1iO_dataout <= wire_n0Oi_dataout AND NOT(nlO0il); + wire_n1li_dataout <= wire_n0Ol_dataout AND wire_nl0l_o; + wire_n1ll_dataout <= wire_nl1O_o AND wire_nl0l_o; + wire_n1lO_dataout <= wire_n0OO_dataout AND wire_nl0l_o; + wire_n1Oi_dataout <= wire_ni1i_dataout AND wire_nl0l_o; + wire_n1Ol_dataout <= wire_ni1l_dataout AND wire_nl0l_o; + wire_n1OO_dataout <= wire_ni1O_dataout AND wire_nl0l_o; + wire_ni0i_dataout <= wire_nl1l_o(4) AND wire_nl1O_o; + wire_ni0ii_dataout <= (NOT (wire_w_lg_w_lg_nlO0li105w691w(0) OR (nlO0li AND ni00i))) OR nl01l; + wire_ni0il_dataout <= wire_niiOi_o(0) AND NOT(nl01l); + wire_ni0iO_dataout <= wire_niiOi_o(1) AND NOT(nl01l); + wire_ni0l_dataout <= wire_nl1l_o(5) AND wire_nl1O_o; + wire_ni0li_dataout <= wire_niiOi_o(2) AND NOT(nl01l); + wire_ni0ll_dataout <= wire_niiOi_o(3) AND NOT(nl01l); + wire_ni0lO_dataout <= wire_niiOi_o(4) AND NOT(nl01l); + wire_ni0O_dataout <= wire_nl1l_o(6) AND wire_nl1O_o; + wire_ni0Oi_dataout <= wire_niiOi_o(5) AND NOT(nl01l); + wire_ni0Ol_dataout <= wire_niiOi_o(6) AND NOT(nl01l); + wire_ni0OO_dataout <= wire_niiOi_o(7) AND NOT(nl01l); + wire_ni1i_dataout <= wire_nl1l_o(1) AND wire_nl1O_o; + wire_ni1l_dataout <= wire_nl1l_o(2) AND wire_nl1O_o; + wire_ni1O_dataout <= wire_nl1l_o(3) AND wire_nl1O_o; + wire_nii0i_dataout <= wire_niiOi_o(11) AND NOT(nl01l); + wire_nii0l_dataout <= wire_niiOi_o(12) AND NOT(nl01l); + wire_nii0O_dataout <= wire_niiOi_o(13) AND NOT(nl01l); + wire_nii1i_dataout <= wire_niiOi_o(8) AND NOT(nl01l); + wire_nii1l_dataout <= wire_niiOi_o(9) AND NOT(nl01l); + wire_nii1O_dataout <= wire_niiOi_o(10) AND NOT(nl01l); + wire_niii_dataout <= wire_nl1l_o(7) AND wire_nl1O_o; + wire_niiii_dataout <= wire_niiOi_o(14) AND NOT(nl01l); + wire_niiil_dataout <= wire_niiOi_o(15) AND NOT(nl01l); + wire_niiiO_dataout <= wire_niiOi_o(16) AND NOT(nl01l); + wire_niil_dataout <= wire_nl1l_o(8) AND wire_nl1O_o; + wire_niiO_dataout <= wire_nl1l_o(9) AND wire_nl1O_o; + wire_nili_dataout <= wire_nl1l_o(10) AND wire_nl1O_o; + wire_nill_dataout <= wire_nl1l_o(11) AND wire_nl1O_o; + wire_nilO_dataout <= wire_nl1l_o(12) AND wire_nl1O_o; + wire_niO0i_dataout <= wire_nl1il_o(1) AND NOT(niO1i); + wire_niO0l_dataout <= wire_nl1il_o(2) AND NOT(niO1i); + wire_niO0O_dataout <= wire_nl1il_o(3) AND NOT(niO1i); + wire_niO1l_dataout <= (NOT (wire_w_lg_w_lg_nlO0li105w617w(0) OR (nlO0li AND nilOO))) OR niO1i; + wire_niO1O_dataout <= wire_nl1il_o(0) AND NOT(niO1i); + wire_niOi_dataout <= wire_nl1l_o(13) AND wire_nl1O_o; + wire_niOii_dataout <= wire_nl1il_o(4) AND NOT(niO1i); + wire_niOil_dataout <= wire_nl1il_o(5) AND NOT(niO1i); + wire_niOiO_dataout <= wire_nl1il_o(6) AND NOT(niO1i); + wire_niOl_dataout <= wire_nl1l_o(14) AND wire_nl1O_o; + wire_niOli_dataout <= wire_nl1il_o(7) AND NOT(niO1i); + wire_niOll_dataout <= wire_nl1il_o(8) AND NOT(niO1i); + wire_niOlO_dataout <= wire_nl1il_o(9) AND NOT(niO1i); + wire_niOO_dataout <= wire_nl1l_o(15) AND wire_nl1O_o; + wire_niOOi_dataout <= wire_nl1il_o(10) AND NOT(niO1i); + wire_niOOl_dataout <= wire_nl1il_o(11) AND NOT(niO1i); + wire_niOOO_dataout <= wire_nl1il_o(12) AND NOT(niO1i); + wire_nl00i_dataout <= wire_nl00l_dataout AND NOT(wire_nl0OO_w_lg_nl0iO515w(0)); + wire_nl00l_dataout <= (ni00O XOR n0lOO) AND ((wire_ni00l_w_lg_n0lOi512w(0) AND wire_nl0OO_w_lg_n0lll10w(0)) AND wire_nl0OO_w_lg_n0lli15w(0)); + wire_nl01O_dataout <= nl01i AND NOT(wire_nl0OO_w_lg_nl0iO515w(0)); + wire_nl10i_dataout <= wire_nl1il_o(16) AND NOT(niO1i); + wire_nl11i_dataout <= wire_nl1il_o(13) AND NOT(niO1i); + wire_nl11l_dataout <= wire_nl1il_o(14) AND NOT(niO1i); + wire_nl11O_dataout <= wire_nl1il_o(15) AND NOT(niO1i); + wire_nl1i_dataout <= wire_nl1l_o(16) AND wire_nl1O_o; + wire_nli0O_dataout <= nli1O AND NOT(scan_mode); + wire_nli0O_w_lg_dataout509w(0) <= NOT wire_nli0O_dataout; + wire_nlili_dataout <= nliiO AND NOT(scan_mode); + wire_nlili_w_lg_dataout507w(0) <= NOT wire_nlili_dataout; + wire_nliOl_dataout <= (wire_n0l_dataout OR ((nlli OR nliOi) OR (NOT (nlO1ii42 XOR nlO1ii41)))) AND NOT(scan_mode); + wire_nliOl_w_lg_dataout328w(0) <= NOT wire_nliOl_dataout; + wire_nlO0O_dataout <= wire_n1li_dataout AND NOT(nlO0il); + wire_nlOii_dataout <= wire_n1ll_dataout OR nlO0il; + wire_nlOil_dataout <= wire_n1lO_dataout OR nlO0il; + wire_nlOiO_dataout <= wire_n1Oi_dataout AND NOT(nlO0il); + wire_nlOli_dataout <= wire_n1Ol_dataout AND NOT(nlO0il); + wire_nlOll_dataout <= wire_n1OO_dataout AND NOT(nlO0il); + wire_nlOlO_dataout <= wire_n01i_dataout AND NOT(nlO0il); + wire_nlOOi_dataout <= wire_n01l_dataout AND NOT(nlO0il); + wire_nlOOl_dataout <= wire_n01O_dataout AND NOT(nlO0il); + wire_nlOOO_dataout <= wire_n00i_dataout AND NOT(nlO0il); + wire_n0liO_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n0liO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0liO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n0liO_a, + b => wire_n0liO_b, + cin => wire_gnd, + o => wire_n0liO_o + ); + wire_n0OOO_a <= ( n0lOi & n0llO & n0lll & n0lli & "1"); + wire_n0OOO_b <= ( "1" & "1" & "1" & "0" & "1"); + n0OOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0OOO_a, + b => wire_n0OOO_b, + cin => wire_gnd, + o => wire_n0OOO_o + ); + wire_niiOi_a <= ( ni00i & ni01O & ni01l & ni01i & ni1OO & ni1Ol & ni1Oi & ni1lO & ni1ll & ni1li & ni1iO & ni1il & ni1ii & ni10O & ni10l & ni10i & ni11O); + wire_niiOi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niiOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 17, + width_b => 17, + width_o => 17 + ) + PORT MAP ( + a => wire_niiOi_a, + b => wire_niiOi_b, + cin => wire_gnd, + o => wire_niiOi_o + ); + wire_nl0i_a <= ( "0" & nlO0li & wire_w_lg_nlO0li105w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlO01O24_w_lg_w_lg_q108w109w & wire_w_lg_nlO0li105w & wire_w_lg_nlO0li105w & "0" & "0" & "0" & "0" & "0"); + wire_nl0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & rppm_post_eidle_del & "1" & wire_w_lg_rppm_post_eidle_del136w & "0" & rppm_post_eidle_del & wire_w_lg_rppm_post_eidle_del136w & "0" & "0" & "0"); + wire_nl0i_w_o_range218w(0) <= wire_nl0i_o(9); + nl0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 18, + width_b => 18, + width_o => 18 + ) + PORT MAP ( + a => wire_nl0i_a, + b => wire_nl0i_b, + cin => wire_gnd, + o => wire_nl0i_o + ); + wire_nl1il_a <= ( nilOO & nilOl & nilOi & nillO & nilll & nilli & niliO & nilil & nilii & nil0O & nil0l & nil0i & nil1O & nil1l & nil1i & niiOO & niiOl); + wire_nl1il_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 17, + width_b => 17, + width_o => 17 + ) + PORT MAP ( + a => wire_nl1il_a, + b => wire_nl1il_b, + cin => wire_gnd, + o => wire_nl1il_o + ); + wire_nl1l_a <= ( wire_nlO1li40_w_lg_w_lg_q266w267w & nlO1O & nlO1l & wire_nlO1ll38_w_lg_w_lg_q261w262w & nllOO & nllOl & nllOi & wire_nlO1lO36_w_lg_w_lg_q255w256w & nllll & nllli & nlliO & nllil & nllii & nll0O & nll0l & nll0i & nll1O); + wire_nl1l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 17, + width_b => 17, + width_o => 17 + ) + PORT MAP ( + a => wire_nl1l_a, + b => wire_nl1l_b, + cin => wire_gnd, + o => wire_nl1l_o + ); + wire_nli0l_a <= ( nlO0li & wire_nlO10i48_w_lg_w_lg_q355w356w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nli0l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + wire_nli0l_w_o_range430w(0) <= wire_nli0l_o(12); + nli0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nli0l_a, + b => wire_nli0l_b, + cin => wire_gnd, + o => wire_nli0l_o + ); + wire_n000l_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n000l_b <= ( "0" & "1" & "0" & "0" & "0" & "0" & "1" & "1"); + n000l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n000l_a, + b => wire_n000l_b, + cin => wire_vcc, + o => wire_n000l_o + ); + wire_n001l_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n001l_b <= ( "0" & "0" & "1" & "0" & "0" & "0" & "1" & "0"); + n001l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n001l_a, + b => wire_n001l_b, + cin => wire_vcc, + o => wire_n001l_o + ); + wire_n010l_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n010l_b <= ( "0" & "0" & "0" & "0" & "1" & "1" & "1" & "1"); + n010l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n010l_a, + b => wire_n010l_b, + cin => wire_vcc, + o => wire_n010l_o + ); + wire_n011i_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n011i_b <= ( "0" & "0" & "0" & "0" & "1" & "0" & "1" & "0"); + n011i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n011i_a, + b => wire_n011i_b, + cin => wire_vcc, + o => wire_n011i_o + ); + wire_n01iO_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n01iO_b <= ( "0" & "0" & "0" & "1" & "0" & "0" & "1" & "0"); + n01iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n01iO_a, + b => wire_n01iO_b, + cin => wire_vcc, + o => wire_n01iO_o + ); + wire_n01Oi_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n01Oi_b <= ( "0" & "0" & "0" & "1" & "0" & "1" & "0" & "1"); + n01Oi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n01Oi_a, + b => wire_n01Oi_b, + cin => wire_vcc, + o => wire_n01Oi_o + ); + wire_n1liO_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n1liO_b <= ( "0" & "0" & "0" & "1" & "1" & "1" & "0" & "0"); + n1liO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n1liO_a, + b => wire_n1liO_b, + cin => wire_vcc, + o => wire_n1liO_o + ); + wire_n1lOl_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n1lOl_b <= ( "0" & "0" & "1" & "0" & "1" & "0" & "0" & "1"); + n1lOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n1lOl_a, + b => wire_n1lOl_b, + cin => wire_vcc, + o => wire_n1lOl_o + ); + wire_n1O1O_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n1O1O_b <= ( "1" & "0" & "0" & "0" & "0" & "1" & "0" & "1"); + n1O1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n1O1O_a, + b => wire_n1O1O_b, + cin => wire_vcc, + o => wire_n1O1O_o + ); + wire_n1Oil_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n1Oil_b <= ( "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + n1Oil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n1Oil_a, + b => wire_n1Oil_b, + cin => wire_vcc, + o => wire_n1Oil_o + ); + wire_n1OlO_a <= ( n00Oi & n00lO & n00ll & n00li & n00iO & n00il & n00ii & n1iOi); + wire_n1OlO_b <= ( "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0"); + n1OlO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n1OlO_a, + b => wire_n1OlO_b, + cin => wire_vcc, + o => wire_n1OlO_o + ); + wire_nl0l_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nl0l_b <= ( nlO0i & nlO1O & nlO1l & nlO1i & wire_nlO00i22_w_lg_w_lg_q87w88w & wire_nlO00l20_w_lg_w_lg_q84w85w & nllOi & nlllO & nllll & wire_nlO00O18_w_lg_w_lg_q78w79w & nlliO & nllil & nllii & wire_nlO0ii16_w_lg_w_lg_q72w73w & nll0l & nll0i & nll1O); + nl0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 17, + width_b => 17 + ) + PORT MAP ( + a => wire_nl0l_a, + b => wire_nl0l_b, + cin => wire_gnd, + o => wire_nl0l_o + ); + wire_nl1O_a <= ( "0" & nlO0i & nlO1O & nlO1l & nlO1i & wire_nlO1Ol32_w_lg_w_lg_q182w183w & nllOl & nllOi & wire_nlO1OO30_w_lg_w_lg_q177w178w & nllll & nllli & nlliO & nllil & nllii & nll0O & wire_nlO01i28_w_lg_w_lg_q168w169w & wire_nlO01l26_w_lg_w_lg_q165w166w & nll1O); + wire_nl1O_b <= ( wire_nl0i_o(17 DOWNTO 10) & wire_nlO1Oi34_w_lg_w_lg_q219w220w & wire_nl0i_o(8 DOWNTO 0)); + nl1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 18, + width_b => 18 + ) + PORT MAP ( + a => wire_nl1O_a, + b => wire_nl1O_b, + cin => wire_gnd, + o => wire_nl1O_o + ); + wire_nl1Ol_a <= ( n0lOi & n0llO & n0lll & n0lli); + wire_nl1Ol_b <= ( "1" & "0" & "0" & "0"); + nl1Ol : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nl1Ol_a, + b => wire_nl1Ol_b, + cin => wire_gnd, + o => wire_nl1Ol_o + ); + wire_nl1OO_a <= ( "0" & "0" & "0" & "0"); + wire_nl1OO_b <= ( n0lOi & n0llO & n0lll & n0lli); + nl1OO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nl1OO_a, + b => wire_nl1OO_b, + cin => wire_gnd, + o => wire_nl1OO_o + ); + wire_nli0i_a <= ( wire_nlO11O50_w_lg_w_lg_q431w432w & wire_nli0l_o(11 DOWNTO 0) & "0" & "0" & "0" & "0"); + wire_nli0i_b <= ( nilOO & nilOl & nilOi & nillO & nilll & nilli & niliO & nilil & nilii & nil0O & nil0l & nil0i & nil1O & nil1l & nil1i & niiOO & wire_nlO11l52_w_lg_w_lg_q434w435w); + nli0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 17, + width_b => 17 + ) + PORT MAP ( + a => wire_nli0i_a, + b => wire_nli0i_b, + cin => wire_gnd, + o => wire_nli0i_o + ); + wire_nli1l_a <= ( wire_nli0l_o(12 DOWNTO 0) & "0" & "0" & "0" & "0"); + wire_nli1l_b <= ( ni00i & ni01O & ni01l & ni01i & ni1OO & ni1Ol & ni1Oi & ni1lO & ni1ll & ni1li & ni1iO & ni1il & ni1ii & ni10O & ni10l & ni10i & ni11O); + nli1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 17, + width_b => 17 + ) + PORT MAP ( + a => wire_nli1l_a, + b => wire_nli1l_b, + cin => wire_gnd, + o => wire_nli1l_o + ); + + END RTL; --cycloneiv_hssi_rx_digi_freqdet +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 177 mux21 115 oper_add 3 oper_decoder 3 oper_less_than 2 oper_mux 1 oper_selector 4 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_eii_module IS + PORT + ( + eidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + eiosdetect_int : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + inferred_rxvalid : IN STD_LOGIC; + kcount : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + kflag : IN STD_LOGIC; + pipe_loopbk : IN STD_LOGIC; + rcvd_clk : IN STD_LOGIC; + reidle_com_detect : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + reidleinferenable : IN STD_LOGIC; + rgen1_sigdet_ena : IN STD_LOGIC; + riei_eios_priority_dis : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rwait_count : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxelecidle_int : OUT STD_LOGIC; + rxpcsrst : IN STD_LOGIC; + signaldetect : IN STD_LOGIC; + skposdetect : IN STD_LOGIC; + sudi : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + syncstatus : IN STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_eii_module; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_eii_module IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL niOi0l51 : STD_LOGIC := '0'; + SIGNAL niOi0l52 : STD_LOGIC := '0'; + SIGNAL niOi0O49 : STD_LOGIC := '0'; + SIGNAL niOi0O50 : STD_LOGIC := '0'; + SIGNAL nl000l23 : STD_LOGIC := '0'; + SIGNAL nl000l24 : STD_LOGIC := '0'; + SIGNAL nl001l25 : STD_LOGIC := '0'; + SIGNAL nl001l26 : STD_LOGIC := '0'; + SIGNAL nl00ii21 : STD_LOGIC := '0'; + SIGNAL nl00ii22 : STD_LOGIC := '0'; + SIGNAL wire_nl00ii22_w_lg_q95w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl00ll19 : STD_LOGIC := '0'; + SIGNAL nl00ll20 : STD_LOGIC := '0'; + SIGNAL wire_nl00ll20_w_lg_w_lg_q76w77w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00ll20_w_lg_q76w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl00lO17 : STD_LOGIC := '0'; + SIGNAL nl00lO18 : STD_LOGIC := '0'; + SIGNAL nl00Oi15 : STD_LOGIC := '0'; + SIGNAL nl00Oi16 : STD_LOGIC := '0'; + SIGNAL wire_nl00Oi16_w_lg_w_lg_q39w40w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00Oi16_w_lg_q39w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl00Ol13 : STD_LOGIC := '0'; + SIGNAL nl00Ol14 : STD_LOGIC := '0'; + SIGNAL wire_nl00Ol14_w_lg_w_lg_q30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00Ol14_w_lg_q30w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl011l37 : STD_LOGIC := '0'; + SIGNAL nl011l38 : STD_LOGIC := '0'; + SIGNAL wire_nl011l38_w_lg_w_lg_q208w209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011l38_w_lg_q208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl01ii35 : STD_LOGIC := '0'; + SIGNAL nl01ii36 : STD_LOGIC := '0'; + SIGNAL nl01iO33 : STD_LOGIC := '0'; + SIGNAL nl01iO34 : STD_LOGIC := '0'; + SIGNAL nl01ll31 : STD_LOGIC := '0'; + SIGNAL nl01ll32 : STD_LOGIC := '0'; + SIGNAL nl01Oi29 : STD_LOGIC := '0'; + SIGNAL nl01Oi30 : STD_LOGIC := '0'; + SIGNAL nl01OO27 : STD_LOGIC := '0'; + SIGNAL nl01OO28 : STD_LOGIC := '0'; + SIGNAL nl0i0i10 : STD_LOGIC := '0'; + SIGNAL nl0i0i9 : STD_LOGIC := '0'; + SIGNAL nl0i0l7 : STD_LOGIC := '0'; + SIGNAL nl0i0l8 : STD_LOGIC := '0'; + SIGNAL nl0i1i11 : STD_LOGIC := '0'; + SIGNAL nl0i1i12 : STD_LOGIC := '0'; + SIGNAL nl0iii5 : STD_LOGIC := '0'; + SIGNAL nl0iii6 : STD_LOGIC := '0'; + SIGNAL nl0ili3 : STD_LOGIC := '0'; + SIGNAL nl0ili4 : STD_LOGIC := '0'; + SIGNAL nl0iOi1 : STD_LOGIC := '0'; + SIGNAL nl0iOi2 : STD_LOGIC := '0'; + SIGNAL nl1lOO47 : STD_LOGIC := '0'; + SIGNAL nl1lOO48 : STD_LOGIC := '0'; + SIGNAL wire_nl1lOO48_w_lg_w_lg_q239w240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO48_w_lg_q239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1O1l45 : STD_LOGIC := '0'; + SIGNAL nl1O1l46 : STD_LOGIC := '0'; + SIGNAL wire_nl1O1l46_w_lg_q235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1Oii43 : STD_LOGIC := '0'; + SIGNAL nl1Oii44 : STD_LOGIC := '0'; + SIGNAL wire_nl1Oii44_w_lg_q227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1Oll41 : STD_LOGIC := '0'; + SIGNAL nl1Oll42 : STD_LOGIC := '0'; + SIGNAL wire_nl1Oll42_w_lg_w_lg_q218w219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1Oll42_w_lg_q218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1OOl39 : STD_LOGIC := '0'; + SIGNAL nl1OOl40 : STD_LOGIC := '0'; + SIGNAL wire_nl1OOl40_w_lg_w_lg_q213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1OOl40_w_lg_q213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0l : STD_LOGIC := '0'; + SIGNAL n0OlO : STD_LOGIC := '0'; + SIGNAL n0OOi : STD_LOGIC := '0'; + SIGNAL n0OOl : STD_LOGIC := '0'; + SIGNAL n0OOO : STD_LOGIC := '0'; + SIGNAL n1Ol : STD_LOGIC := '0'; + SIGNAL n1OlO : STD_LOGIC := '0'; + SIGNAL n1OO : STD_LOGIC := '0'; + SIGNAL ni00i : STD_LOGIC := '0'; + SIGNAL ni00l : STD_LOGIC := '0'; + SIGNAL ni00O : STD_LOGIC := '0'; + SIGNAL ni01i : STD_LOGIC := '0'; + SIGNAL ni01l : STD_LOGIC := '0'; + SIGNAL ni01O : STD_LOGIC := '0'; + SIGNAL ni0i : STD_LOGIC := '0'; + SIGNAL ni0il : STD_LOGIC := '0'; + SIGNAL ni0iO : STD_LOGIC := '0'; + SIGNAL ni0li : STD_LOGIC := '0'; + SIGNAL ni0ll : STD_LOGIC := '0'; + SIGNAL ni0lO : STD_LOGIC := '0'; + SIGNAL ni0Oi : STD_LOGIC := '0'; + SIGNAL ni0Ol : STD_LOGIC := '0'; + SIGNAL ni0OO : STD_LOGIC := '0'; + SIGNAL ni10i : STD_LOGIC := '0'; + SIGNAL ni10l : STD_LOGIC := '0'; + SIGNAL ni10O : STD_LOGIC := '0'; + SIGNAL ni11i : STD_LOGIC := '0'; + SIGNAL ni11l : STD_LOGIC := '0'; + SIGNAL ni11O : STD_LOGIC := '0'; + SIGNAL ni1ii : STD_LOGIC := '0'; + SIGNAL ni1il : STD_LOGIC := '0'; + SIGNAL ni1iO : STD_LOGIC := '0'; + SIGNAL ni1li : STD_LOGIC := '0'; + SIGNAL ni1ll : STD_LOGIC := '0'; + SIGNAL ni1lO : STD_LOGIC := '0'; + SIGNAL ni1Oi : STD_LOGIC := '0'; + SIGNAL ni1Ol : STD_LOGIC := '0'; + SIGNAL ni1OO : STD_LOGIC := '0'; + SIGNAL nii0i : STD_LOGIC := '0'; + SIGNAL nii0l : STD_LOGIC := '0'; + SIGNAL nii0O : STD_LOGIC := '0'; + SIGNAL nii1i : STD_LOGIC := '0'; + SIGNAL nii1l : STD_LOGIC := '0'; + SIGNAL nii1O : STD_LOGIC := '0'; + SIGNAL niiii : STD_LOGIC := '0'; + SIGNAL niiil : STD_LOGIC := '0'; + SIGNAL niiiO : STD_LOGIC := '0'; + SIGNAL niili : STD_LOGIC := '0'; + SIGNAL niill : STD_LOGIC := '0'; + SIGNAL niilO : STD_LOGIC := '0'; + SIGNAL niiOi : STD_LOGIC := '0'; + SIGNAL niiOl : STD_LOGIC := '0'; + SIGNAL niiOO : STD_LOGIC := '0'; + SIGNAL nil1i : STD_LOGIC := '0'; + SIGNAL nil1l : STD_LOGIC := '0'; + SIGNAL nil1O : STD_LOGIC := '0'; + SIGNAL nl : STD_LOGIC := '0'; + SIGNAL nl0l0O : STD_LOGIC := '0'; + SIGNAL nl0lli : STD_LOGIC := '0'; + SIGNAL nl0O0i : STD_LOGIC := '0'; + SIGNAL nl0O0l : STD_LOGIC := '0'; + SIGNAL nl0O0O : STD_LOGIC := '0'; + SIGNAL nl0O1i : STD_LOGIC := '0'; + SIGNAL nl0O1l : STD_LOGIC := '0'; + SIGNAL nl0O1O : STD_LOGIC := '0'; + SIGNAL nl0Oii : STD_LOGIC := '0'; + SIGNAL nl0Oil : STD_LOGIC := '0'; + SIGNAL nl0OiO : STD_LOGIC := '0'; + SIGNAL nl0Oli : STD_LOGIC := '0'; + SIGNAL nl0Oll : STD_LOGIC := '0'; + SIGNAL nl0OlO : STD_LOGIC := '0'; + SIGNAL nli0ll : STD_LOGIC := '0'; + SIGNAL nli0Oi : STD_LOGIC := '0'; + SIGNAL nli0OO : STD_LOGIC := '0'; + SIGNAL nli10l : STD_LOGIC := '0'; + SIGNAL nli10O : STD_LOGIC := '0'; + SIGNAL nli1ii : STD_LOGIC := '0'; + SIGNAL nli1il : STD_LOGIC := '0'; + SIGNAL nli1iO : STD_LOGIC := '0'; + SIGNAL nli1li : STD_LOGIC := '0'; + SIGNAL nli1ll : STD_LOGIC := '0'; + SIGNAL nli1lO : STD_LOGIC := '0'; + SIGNAL nli1Oi : STD_LOGIC := '0'; + SIGNAL nlii0i : STD_LOGIC := '0'; + SIGNAL nlii0l : STD_LOGIC := '0'; + SIGNAL nlii0O : STD_LOGIC := '0'; + SIGNAL nlii1i : STD_LOGIC := '0'; + SIGNAL nlii1l : STD_LOGIC := '0'; + SIGNAL nlii1O : STD_LOGIC := '0'; + SIGNAL nliiii : STD_LOGIC := '0'; + SIGNAL nliiil : STD_LOGIC := '0'; + SIGNAL nliiiO : STD_LOGIC := '0'; + SIGNAL nliili : STD_LOGIC := '0'; + SIGNAL nliill : STD_LOGIC := '0'; + SIGNAL nliilO : STD_LOGIC := '0'; + SIGNAL nliiOi : STD_LOGIC := '0'; + SIGNAL nliiOl : STD_LOGIC := '0'; + SIGNAL nlil : STD_LOGIC := '0'; + SIGNAL nll : STD_LOGIC := '0'; + SIGNAL nlO : STD_LOGIC := '0'; + SIGNAL wire_ni_CLRN : STD_LOGIC; + SIGNAL wire_ni_w_lg_w_lg_w_lg_w683w724w725w726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w683w684w704w705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w683w684w685w686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w631w632w633w634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w643w644w645w646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w617w618w619w620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w815w816w817w818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w829w852w853w854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w829w830w842w843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w829w830w831w897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w764w765w786w787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w764w765w766w796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w764w804w805w806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w662w663w664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w556w557w636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w564w566w567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w654w655w656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w625w626w627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w678w679w680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w732w733w734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w699w710w711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w690w691w696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w808w809w860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w800w812w813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w772w774w775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w867w868w869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w825w839w840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w751w783w784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w683w724w725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w683w684w704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w683w684w685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w669w670w671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w631w632w633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w631w648w649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w603w604w605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w643w644w645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w617w618w619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w617w638w639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w815w816w817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w829w852w853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w829w830w842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w829w830w831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w764w765w786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w764w765w766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w764w804w805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w662w663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w556w557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w564w566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w564w658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w654w655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w625w626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w678w679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w678w721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w732w733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w699w710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w699w700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w690w691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w690w707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w808w809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w800w812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w772w774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w772w880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w867w868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w825w839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w825w826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w751w783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w751w752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w683w724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w683w684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w669w670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w631w632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w631w648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w603w604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w643w644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w617w618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w617w638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w815w816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w829w852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w829w830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w764w765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w764w804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w608w661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w552w554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w652w653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w623w624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w688w689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w587w588w589w590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w577w578w580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w629w630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w601w602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w587w588w589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w575w577w578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i548w549w551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i548w549w622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i586w674w675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i586w587w588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nil1i744w746w747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i574w575w577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i574w575w666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i574w599w600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nii0i574w599w614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nil1i757w759w760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nil1O221w233w236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_w_lg_nil1O221w225w228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0i548w549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0i586w674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0i586w587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1i744w746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_ni0i23w24w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0i574w575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0i574w599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0l197w343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0l197w339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0l197w335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0O200w344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0O200w340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nii0O200w336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1i757w759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1l222w224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nil1O221w225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii0i548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii0i586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nil1i744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlO9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_n0l16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0i23w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0il366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0iO198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0li568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0ll558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0lO565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0Oi555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0Ol553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_ni0OO579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii0i574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii0l197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii0O200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii1i550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii1l576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nii1O547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niiii755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niiil753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niiiO773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niili750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niill798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niilO769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niiOi761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niiOl745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_niiOO758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nil1i757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nil1l222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nil1O221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nli0ll989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nli0OO987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nli1li907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlii0i982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlii1i985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlii1O983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlil911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nlO9w10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_n0l1088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n01i : STD_LOGIC := '0'; + SIGNAL n0ll : STD_LOGIC := '0'; + SIGNAL n0lO : STD_LOGIC := '0'; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1O : STD_LOGIC := '0'; + SIGNAL wire_ni1l_CLRN : STD_LOGIC; + SIGNAL wire_ni1l_w_lg_n0ll115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_n0Oi125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1l_w_lg_ni1i138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0i : STD_LOGIC := '0'; + SIGNAL nliO0l : STD_LOGIC := '0'; + SIGNAL nliO0O : STD_LOGIC := '0'; + SIGNAL nliO1l : STD_LOGIC := '0'; + SIGNAL nliO1O : STD_LOGIC := '0'; + SIGNAL nliOii : STD_LOGIC := '0'; + SIGNAL nliOil : STD_LOGIC := '0'; + SIGNAL nliOiO : STD_LOGIC := '0'; + SIGNAL nliOli : STD_LOGIC := '0'; + SIGNAL nliOll : STD_LOGIC := '0'; + SIGNAL nliOOi : STD_LOGIC := '0'; + SIGNAL wire_nliOlO_CLRN : STD_LOGIC; + SIGNAL wire_nliOlO_PRN : STD_LOGIC; + SIGNAL n0li : STD_LOGIC := '0'; + SIGNAL ni0ii : STD_LOGIC := '0'; + SIGNAL nl0lOO : STD_LOGIC := '0'; + SIGNAL nliO : STD_LOGIC := '0'; + SIGNAL nll10i : STD_LOGIC := '0'; + SIGNAL nlll : STD_LOGIC := '0'; + SIGNAL wire_nlli_CLRN : STD_LOGIC; + SIGNAL wire_nlli_PRN : STD_LOGIC; + SIGNAL wire_nlli_w_lg_nliO18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n000i_dataout : STD_LOGIC; + SIGNAL wire_n001i_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001O_dataout : STD_LOGIC; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00ii_dataout : STD_LOGIC; + SIGNAL wire_n00il_dataout : STD_LOGIC; + SIGNAL wire_n00iO_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00li_dataout : STD_LOGIC; + SIGNAL wire_n00ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n010i_dataout : STD_LOGIC; + SIGNAL wire_n010l_dataout : STD_LOGIC; + SIGNAL wire_n010O_dataout : STD_LOGIC; + SIGNAL wire_n011i_dataout : STD_LOGIC; + SIGNAL wire_n011l_dataout : STD_LOGIC; + SIGNAL wire_n011O_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0iii_dataout : STD_LOGIC; + SIGNAL wire_n0iil_dataout : STD_LOGIC; + SIGNAL wire_n0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0lii_dataout : STD_LOGIC; + SIGNAL wire_n0lil_dataout : STD_LOGIC; + SIGNAL wire_n0liO_dataout : STD_LOGIC; + SIGNAL wire_n0lli_dataout : STD_LOGIC; + SIGNAL wire_n0lll_dataout : STD_LOGIC; + SIGNAL wire_n0llO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli0lO_dataout : STD_LOGIC; + SIGNAL wire_nliiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O_dataout : STD_LOGIC; + SIGNAL wire_nlilii_dataout : STD_LOGIC; + SIGNAL wire_nlilil_dataout : STD_LOGIC; + SIGNAL wire_nliliO_dataout : STD_LOGIC; + SIGNAL wire_nlilli_dataout : STD_LOGIC; + SIGNAL wire_nlilll_dataout : STD_LOGIC; + SIGNAL wire_nlillO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOO_dataout : STD_LOGIC; + SIGNAL wire_nliOOl_dataout : STD_LOGIC; + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_n00O_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n00O_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n00O_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0O_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0O_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0O_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nliO1i_a : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nliO1i_b : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nliO1i_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl0OOi_i : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0OOi_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0OOO_i : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0OOO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli10i_i : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli10i_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0il_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0il_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0il_o : STD_LOGIC; + SIGNAL wire_nl0lOi_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0lOi_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_nl0lOi_o : STD_LOGIC; + SIGNAL wire_nl0lil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0lil_o : STD_LOGIC; + SIGNAL wire_nl0lil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n000l_data : STD_LOGIC_VECTOR (26 DOWNTO 0); + SIGNAL wire_n000l_o : STD_LOGIC; + SIGNAL wire_n000l_sel : STD_LOGIC_VECTOR (26 DOWNTO 0); + SIGNAL wire_n000O_data : STD_LOGIC_VECTOR (26 DOWNTO 0); + SIGNAL wire_n000O_o : STD_LOGIC; + SIGNAL wire_n000O_sel : STD_LOGIC_VECTOR (26 DOWNTO 0); + SIGNAL wire_n01lO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n01lO_o : STD_LOGIC; + SIGNAL wire_n01lO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1Oii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1Oii_o : STD_LOGIC; + SIGNAL wire_n1Oii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_w97w98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w97w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_sudi_range87w88w91w93w96w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_sudi_range87w88w91w93w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_riei_eios_priority_dis4w5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_sudi_range87w88w91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1O508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOil368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOli370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl0iiO28w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reidleinferenable365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_riei_eios_priority_dis4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rxpcsrst2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_sudi_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_sudi_range89w90w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w284w288w289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w284w288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w263w267w271w275w276w280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w263w267w271w275w276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w263w267w271w275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w263w267w271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w263w267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w242w246w247w251w255w259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w242w246w247w251w255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w242w246w247w251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w242w246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w242w246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w216w220w229w230w237w241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w216w220w229w230w237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w216w220w229w230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w216w220w229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w216w220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_nl010i206w210w211w215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_nl1OOi337w341w345w346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nl010i206w210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nl1OOi337w341w345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nl010i206w210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nl1OOi337w341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl00li92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl010i206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl110l342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11ii338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl11iO334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1i0O285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1iil281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1ili277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1iOi272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1iOO268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1l0i260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1l0O256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1l1l264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1lil252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1lli248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1lOi243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1O0l231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1Oli223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nl1OOi337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi0i : STD_LOGIC; + SIGNAL niOi1l : STD_LOGIC; + SIGNAL niOi1O : STD_LOGIC; + SIGNAL niOiii : STD_LOGIC; + SIGNAL niOiil : STD_LOGIC; + SIGNAL niOiiO : STD_LOGIC; + SIGNAL niOili : STD_LOGIC; + SIGNAL niOill : STD_LOGIC; + SIGNAL niOilO : STD_LOGIC; + SIGNAL niOiOi : STD_LOGIC; + SIGNAL niOiOl : STD_LOGIC; + SIGNAL niOiOO : STD_LOGIC; + SIGNAL niOl0i : STD_LOGIC; + SIGNAL niOl0l : STD_LOGIC; + SIGNAL niOl0O : STD_LOGIC; + SIGNAL niOl1i : STD_LOGIC; + SIGNAL niOl1l : STD_LOGIC; + SIGNAL niOl1O : STD_LOGIC; + SIGNAL niOlii : STD_LOGIC; + SIGNAL niOlil : STD_LOGIC; + SIGNAL niOliO : STD_LOGIC; + SIGNAL niOlli : STD_LOGIC; + SIGNAL niOlll : STD_LOGIC; + SIGNAL niOllO : STD_LOGIC; + SIGNAL niOlOi : STD_LOGIC; + SIGNAL niOlOl : STD_LOGIC; + SIGNAL niOlOO : STD_LOGIC; + SIGNAL niOO0i : STD_LOGIC; + SIGNAL niOO0l : STD_LOGIC; + SIGNAL niOO0O : STD_LOGIC; + SIGNAL niOO1i : STD_LOGIC; + SIGNAL niOO1l : STD_LOGIC; + SIGNAL niOO1O : STD_LOGIC; + SIGNAL niOOii : STD_LOGIC; + SIGNAL niOOil : STD_LOGIC; + SIGNAL niOOiO : STD_LOGIC; + SIGNAL niOOli : STD_LOGIC; + SIGNAL niOOll : STD_LOGIC; + SIGNAL niOOlO : STD_LOGIC; + SIGNAL niOOOi : STD_LOGIC; + SIGNAL niOOOl : STD_LOGIC; + SIGNAL niOOOO : STD_LOGIC; + SIGNAL nl000i : STD_LOGIC; + SIGNAL nl00iO : STD_LOGIC; + SIGNAL nl00li : STD_LOGIC; + SIGNAL nl00OO : STD_LOGIC; + SIGNAL nl010i : STD_LOGIC; + SIGNAL nl010l : STD_LOGIC; + SIGNAL nl010O : STD_LOGIC; + SIGNAL nl011i : STD_LOGIC; + SIGNAL nl0i0O : STD_LOGIC; + SIGNAL nl0i1O : STD_LOGIC; + SIGNAL nl0iiO : STD_LOGIC; + SIGNAL nl0ilO : STD_LOGIC; + SIGNAL nl100i : STD_LOGIC; + SIGNAL nl100l : STD_LOGIC; + SIGNAL nl100O : STD_LOGIC; + SIGNAL nl101i : STD_LOGIC; + SIGNAL nl101l : STD_LOGIC; + SIGNAL nl101O : STD_LOGIC; + SIGNAL nl10ii : STD_LOGIC; + SIGNAL nl10il : STD_LOGIC; + SIGNAL nl10iO : STD_LOGIC; + SIGNAL nl10li : STD_LOGIC; + SIGNAL nl10ll : STD_LOGIC; + SIGNAL nl10lO : STD_LOGIC; + SIGNAL nl10Oi : STD_LOGIC; + SIGNAL nl10Ol : STD_LOGIC; + SIGNAL nl10OO : STD_LOGIC; + SIGNAL nl110i : STD_LOGIC; + SIGNAL nl110l : STD_LOGIC; + SIGNAL nl110O : STD_LOGIC; + SIGNAL nl111i : STD_LOGIC; + SIGNAL nl111l : STD_LOGIC; + SIGNAL nl111O : STD_LOGIC; + SIGNAL nl11ii : STD_LOGIC; + SIGNAL nl11il : STD_LOGIC; + SIGNAL nl11iO : STD_LOGIC; + SIGNAL nl11li : STD_LOGIC; + SIGNAL nl11ll : STD_LOGIC; + SIGNAL nl11lO : STD_LOGIC; + SIGNAL nl11Oi : STD_LOGIC; + SIGNAL nl11Ol : STD_LOGIC; + SIGNAL nl11OO : STD_LOGIC; + SIGNAL nl1i0i : STD_LOGIC; + SIGNAL nl1i0l : STD_LOGIC; + SIGNAL nl1i0O : STD_LOGIC; + SIGNAL nl1i1i : STD_LOGIC; + SIGNAL nl1i1l : STD_LOGIC; + SIGNAL nl1i1O : STD_LOGIC; + SIGNAL nl1iii : STD_LOGIC; + SIGNAL nl1iil : STD_LOGIC; + SIGNAL nl1iiO : STD_LOGIC; + SIGNAL nl1ili : STD_LOGIC; + SIGNAL nl1ill : STD_LOGIC; + SIGNAL nl1ilO : STD_LOGIC; + SIGNAL nl1iOi : STD_LOGIC; + SIGNAL nl1iOl : STD_LOGIC; + SIGNAL nl1iOO : STD_LOGIC; + SIGNAL nl1l0i : STD_LOGIC; + SIGNAL nl1l0l : STD_LOGIC; + SIGNAL nl1l0O : STD_LOGIC; + SIGNAL nl1l1i : STD_LOGIC; + SIGNAL nl1l1l : STD_LOGIC; + SIGNAL nl1l1O : STD_LOGIC; + SIGNAL nl1lii : STD_LOGIC; + SIGNAL nl1lil : STD_LOGIC; + SIGNAL nl1liO : STD_LOGIC; + SIGNAL nl1lli : STD_LOGIC; + SIGNAL nl1lll : STD_LOGIC; + SIGNAL nl1llO : STD_LOGIC; + SIGNAL nl1lOi : STD_LOGIC; + SIGNAL nl1lOl : STD_LOGIC; + SIGNAL nl1O0i : STD_LOGIC; + SIGNAL nl1O0l : STD_LOGIC; + SIGNAL nl1O0O : STD_LOGIC; + SIGNAL nl1OiO : STD_LOGIC; + SIGNAL nl1Oli : STD_LOGIC; + SIGNAL nl1OOi : STD_LOGIC; + SIGNAL wire_w_rwait_count_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rwait_count_range73w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rwait_count_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sudi_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_sudi_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_vcc <= '1'; + wire_w_lg_w97w98w(0) <= wire_w97w(0) AND wire_n0il_o; + wire_w97w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_sudi_range87w88w91w93w96w(0) AND nl0iiO; + wire_w_lg_w_lg_w_lg_w_lg_w_sudi_range87w88w91w93w96w(0) <= wire_w_lg_w_lg_w_lg_w_sudi_range87w88w91w93w(0) AND wire_nl00ii22_w_lg_q95w(0); + wire_w_lg_w_lg_w_lg_w_sudi_range87w88w91w93w(0) <= wire_w_lg_w_lg_w_sudi_range87w88w91w(0) AND wire_w_lg_nl00li92w(0); + wire_w_lg_w_lg_riei_eios_priority_dis4w5w(0) <= wire_w_lg_riei_eios_priority_dis4w(0) AND eiosdetect_int; + wire_w_lg_w_lg_w_sudi_range87w88w91w(0) <= wire_w_lg_w_sudi_range87w88w(0) AND wire_w_lg_w_sudi_range89w90w(0); + wire_w_lg_niOO1O508w(0) <= NOT niOO1O; + wire_w_lg_niOOil368w(0) <= NOT niOOil; + wire_w_lg_niOOli370w(0) <= NOT niOOli; + wire_w_lg_nl0iiO28w(0) <= NOT nl0iiO; + wire_w_lg_reidleinferenable365w(0) <= NOT reidleinferenable; + wire_w_lg_riei_eios_priority_dis4w(0) <= NOT riei_eios_priority_dis; + wire_w_lg_rxpcsrst2w(0) <= NOT rxpcsrst; + wire_w_lg_w_sudi_range87w88w(0) <= NOT wire_w_sudi_range87w(0); + wire_w_lg_w_sudi_range89w90w(0) <= NOT wire_w_sudi_range89w(0); + wire_w_lg_w_lg_w284w288w289w(0) <= wire_w_lg_w284w288w(0) OR nl1i0i; + wire_w_lg_w284w288w(0) <= wire_w284w(0) OR wire_ni_w_lg_w_lg_nil1O221w287w(0); + wire_w284w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w263w267w271w275w276w280w(0) OR wire_ni_w_lg_w_lg_nil1O221w283w(0); + wire_w_lg_w_lg_w_lg_w_lg_w_lg_w263w267w271w275w276w280w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w263w267w271w275w276w(0) OR wire_ni_w_lg_w_lg_nil1O221w279w(0); + wire_w_lg_w_lg_w_lg_w_lg_w263w267w271w275w276w(0) <= wire_w_lg_w_lg_w_lg_w263w267w271w275w(0) OR nl1ill; + wire_w_lg_w_lg_w_lg_w263w267w271w275w(0) <= wire_w_lg_w_lg_w263w267w271w(0) OR wire_ni_w_lg_w_lg_nil1O221w274w(0); + wire_w_lg_w_lg_w263w267w271w(0) <= wire_w_lg_w263w267w(0) OR wire_ni_w_lg_w_lg_nil1O221w270w(0); + wire_w_lg_w263w267w(0) <= wire_w263w(0) OR wire_ni_w_lg_w_lg_nil1O221w266w(0); + wire_w263w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w242w246w247w251w255w259w(0) OR wire_ni_w_lg_w_lg_nil1O221w262w(0); + wire_w_lg_w_lg_w_lg_w_lg_w_lg_w242w246w247w251w255w259w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w242w246w247w251w255w(0) OR wire_ni_w_lg_w_lg_nil1O221w258w(0); + wire_w_lg_w_lg_w_lg_w_lg_w242w246w247w251w255w(0) <= wire_w_lg_w_lg_w_lg_w242w246w247w251w(0) OR wire_ni_w_lg_w_lg_nil1O221w254w(0); + wire_w_lg_w_lg_w_lg_w242w246w247w251w(0) <= wire_w_lg_w_lg_w242w246w247w(0) OR wire_ni_w_lg_w_lg_nil1O221w250w(0); + wire_w_lg_w_lg_w242w246w247w(0) <= wire_w_lg_w242w246w(0) OR nl1lll; + wire_w_lg_w242w246w(0) <= wire_w242w(0) OR wire_ni_w_lg_w_lg_nil1O221w245w(0); + wire_w242w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w216w220w229w230w237w241w(0) OR nl1lOl; + wire_w_lg_w_lg_w_lg_w_lg_w_lg_w216w220w229w230w237w241w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w216w220w229w230w237w(0) OR wire_nl1lOO48_w_lg_w_lg_q239w240w(0); + wire_w_lg_w_lg_w_lg_w_lg_w216w220w229w230w237w(0) <= wire_w_lg_w_lg_w_lg_w216w220w229w230w(0) OR wire_ni_w_lg_w_lg_w_lg_nil1O221w233w236w(0); + wire_w_lg_w_lg_w_lg_w216w220w229w230w(0) <= wire_w_lg_w_lg_w216w220w229w(0) OR nl1O0O; + wire_w_lg_w_lg_w216w220w229w(0) <= wire_w_lg_w216w220w(0) OR wire_ni_w_lg_w_lg_w_lg_nil1O221w225w228w(0); + wire_w_lg_w216w220w(0) <= wire_w216w(0) OR wire_nl1Oll42_w_lg_w_lg_q218w219w(0); + wire_w216w(0) <= wire_w_lg_w_lg_w_lg_w_lg_nl010i206w210w211w215w(0) OR nl1OOi; + wire_w_lg_w_lg_w_lg_w_lg_nl010i206w210w211w215w(0) <= wire_w_lg_w_lg_w_lg_nl010i206w210w211w(0) OR wire_nl1OOl40_w_lg_w_lg_q213w214w(0); + wire_w_lg_w_lg_w_lg_w_lg_nl1OOi337w341w345w346w(0) <= wire_w_lg_w_lg_w_lg_nl1OOi337w341w345w(0) OR nl1lOl; + wire_w_lg_w_lg_w_lg_nl010i206w210w211w(0) <= wire_w_lg_w_lg_nl010i206w210w(0) OR nl011i; + wire_w_lg_w_lg_w_lg_nl1OOi337w341w345w(0) <= wire_w_lg_w_lg_nl1OOi337w341w(0) OR wire_ni_w_lg_w_lg_nii0O200w344w(0); + wire_w_lg_w_lg_nl010i206w210w(0) <= wire_w_lg_nl010i206w(0) OR wire_nl011l38_w_lg_w_lg_q208w209w(0); + wire_w_lg_w_lg_nl1OOi337w341w(0) <= wire_w_lg_nl1OOi337w(0) OR wire_ni_w_lg_w_lg_nii0O200w340w(0); + wire_w_lg_nl00li92w(0) <= nl00li OR nl00iO; + wire_w_lg_nl010i206w(0) <= nl010i OR nl010O; + wire_w_lg_nl110l342w(0) <= nl110l OR nl110i; + wire_w_lg_nl11ii338w(0) <= nl11ii OR nl110O; + wire_w_lg_nl11iO334w(0) <= nl11iO OR nl11il; + wire_w_lg_nl1i0O285w(0) <= nl1i0O OR nl1i0l; + wire_w_lg_nl1iil281w(0) <= nl1iil OR nl1iii; + wire_w_lg_nl1ili277w(0) <= nl1ili OR nl1iiO; + wire_w_lg_nl1iOi272w(0) <= nl1iOi OR nl1ilO; + wire_w_lg_nl1iOO268w(0) <= nl1iOO OR nl1iOl; + wire_w_lg_nl1l0i260w(0) <= nl1l0i OR nl1l1O; + wire_w_lg_nl1l0O256w(0) <= nl1l0O OR nl1l0l; + wire_w_lg_nl1l1l264w(0) <= nl1l1l OR nl1l1i; + wire_w_lg_nl1lil252w(0) <= nl1lil OR nl1lii; + wire_w_lg_nl1lli248w(0) <= nl1lli OR nl1liO; + wire_w_lg_nl1lOi243w(0) <= nl1lOi OR nl1llO; + wire_w_lg_nl1O0l231w(0) <= nl1O0l OR nl1O0i; + wire_w_lg_nl1Oli223w(0) <= nl1Oli OR nl1OiO; + wire_w_lg_nl1OOi337w(0) <= nl1OOi OR wire_ni_w_lg_w_lg_nii0O200w336w(0); + niOi0i <= (nll10i OR niOiii); + niOi1l <= ((wire_nli10i_o(6) OR wire_nli10i_o(2)) OR wire_nli10i_o(0)); + niOi1O <= (((((((((((((((wire_ni_w_lg_nlii0i982w(0) AND wire_ni_w_lg_nlii1O983w(0)) AND wire_ni_w_lg_nlii1i985w(0)) AND wire_ni_w_lg_nli0OO987w(0)) AND wire_ni_w_lg_nli0ll989w(0)) AND (NOT (nliO1l XOR nlii1l))) AND (NOT (nliO1O XOR nlii0l))) AND (NOT (nliO0i XOR nlii0O))) AND (NOT (nliO0l XOR nliiii))) AND (NOT (nliO0O XOR nliiil))) AND (NOT (nliOii XOR nliiiO))) AND (NOT (nliOil XOR nliili))) AND (NOT (nliOiO XOR nliill))) AND (NOT (nliOli XOR nliilO))) AND (NOT (nliOll XOR nliiOi))) AND (NOT (nliOOi XOR nliiOl))); + niOiii <= (nl0OlO OR nl0lOO); + niOiil <= (wire_ni_w_lg_w_lg_w808w809w860w(0) AND wire_ni_w_lg_niiii755w(0)); + niOiiO <= ((wire_ni_w_lg_w_lg_w764w804w805w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + niOili <= ((wire_ni_w_lg_w772w774w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + niOill <= (wire_ni_w_lg_w_lg_w_lg_w829w830w831w897w(0) AND wire_ni_w_lg_niiii755w(0)); + niOilO <= (wire_ni_w_lg_w_lg_w772w774w775w(0) AND wire_ni_w_lg_niiii755w(0)); + niOiOi <= ((wire_ni_w_lg_w_lg_w829w830w831w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + niOiOl <= ((wire_ni_w_lg_w772w880w(0) AND wire_ni_w_lg_niiil753w(0)) AND wire_ni_w_lg_niiii755w(0)); + niOiOO <= (wire_ni_w_lg_w_lg_w_lg_w829w830w842w843w(0) AND niiii); + niOl0i <= (wire_ni_w_lg_w_lg_w_lg_w829w852w853w854w(0) AND niiii); + niOl0l <= (((wire_ni_w800w(0) AND wire_ni_w_lg_niiiO773w(0)) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + niOl0O <= (wire_ni_w_lg_w_lg_w_lg_w764w765w766w796w(0) AND wire_ni_w_lg_niiii755w(0)); + niOl1i <= (wire_ni_w_lg_w_lg_w_lg_w829w852w853w854w(0) AND wire_ni_w_lg_niiii755w(0)); + niOl1l <= (wire_ni_w_lg_w_lg_w867w868w869w(0) AND wire_ni_w_lg_niiii755w(0)); + niOl1O <= (((wire_ni_w856w(0) AND wire_ni_w_lg_niiiO773w(0)) AND wire_ni_w_lg_niiil753w(0)) AND wire_ni_w_lg_niiii755w(0)); + niOlii <= ((wire_ni_w_lg_w_lg_w764w765w766w(0) AND wire_ni_w_lg_niiil753w(0)) AND wire_ni_w_lg_niiii755w(0)); + niOlil <= ((wire_ni_w_lg_w751w752w(0) AND wire_ni_w_lg_niiil753w(0)) AND wire_ni_w_lg_niiii755w(0)); + niOliO <= (((((wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w608w(0) AND wire_ni_w_lg_ni0Ol553w(0)) AND wire_ni_w_lg_ni0Oi555w(0)) AND wire_ni_w_lg_ni0lO565w(0)) AND ni0ll) AND ni0li); + niOlli <= ((wire_ni_w_lg_w_lg_w603w604w605w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND wire_ni_w_lg_ni0li568w(0)); + niOlll <= (((wire_ni_w591w(0) AND wire_ni_w_lg_ni0lO565w(0)) AND wire_ni_w_lg_ni0ll558w(0)) AND wire_ni_w_lg_ni0li568w(0)); + niOllO <= ((((wire_ni_w581w(0) AND wire_ni_w_lg_ni0Oi555w(0)) AND ni0lO) AND ni0ll) AND ni0li); + niOlOi <= (wire_ni_w_lg_w_lg_w564w566w567w(0) AND wire_ni_w_lg_ni0li568w(0)); + niOlOl <= (wire_ni_w_lg_w_lg_w564w566w567w(0) AND wire_ni_w_lg_ni0li568w(0)); + niOlOO <= ((wire_ni_w_lg_w556w557w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + niOO0i <= (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (niOlOl OR niOlOi))); + niOO0l <= (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (niOO1i OR niOlOO))); + niOO0O <= (niOOll AND wire_w_lg_niOOli370w(0)); + niOO1i <= ((wire_ni_w_lg_w556w557w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + niOO1l <= ((((((((((((((((((((((((ni0ii OR ni00O) OR ni00l) OR ni00i) OR ni01O) OR ni01l) OR ni01i) OR ni1OO) OR ni1Ol) OR ni1Oi) OR ni1lO) OR ni1ll) OR ni1li) OR ni1iO) OR ni1il) OR ni1ii) OR ni10l) OR ni10i) OR ni11O) OR ni11l) OR ni11i) OR n0OOO) OR n0OOl) OR n0OOi) OR n1OlO); + niOO1O <= ((((((((((((((((((((((((ni0ii OR ni00O) OR ni00l) OR ni00i) OR ni01O) OR ni01l) OR ni1Ol) OR ni1Oi) OR ni1lO) OR ni1ll) OR ni1li) OR ni1iO) OR ni1il) OR ni1ii) OR ni10O) OR ni10l) OR ni10i) OR ni11O) OR ni11l) OR ni11i) OR n0OOO) OR n0OOl) OR n0OOi) OR n0OlO) OR n1OlO); + niOOii <= (niOOll AND niOOli); + niOOil <= (ni0iO AND (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (niOlli OR niOliO)))); + niOOiO <= (wire_w_lg_reidleinferenable365w(0) OR wire_ni_w_lg_ni0il366w(0)); + niOOli <= ((((nl010i OR nl011i) OR nl1OOi) OR nl1O0O) OR nl1lll); + niOOll <= ((((((nl010i OR nl011i) OR nl1OOi) OR nl1O0O) OR nl1lll) OR nl1ill) OR nl1i0i); + niOOlO <= (((wire_w_lg_w_lg_w_lg_w_lg_nl1OOi337w341w345w346w(0) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl111O OR nl111l)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl111i OR niOOOO)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (niOOOl OR niOOOi)))); + niOOOi <= (wire_ni_w_lg_w_lg_w_lg_w617w618w619w620w(0) AND wire_ni_w_lg_ni0li568w(0)); + niOOOl <= (wire_ni_w_lg_w_lg_w_lg_w617w618w619w620w(0) AND wire_ni_w_lg_ni0li568w(0)); + niOOOO <= (wire_ni_w_lg_w_lg_w_lg_w631w632w633w634w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl000i <= (wire_w_lg_w97w98w(0) AND (nl000l24 XOR nl000l23)); + nl00iO <= (((((((((((NOT sudi(0)) AND (NOT sudi(1))) AND sudi(2)) AND sudi(3)) AND sudi(4)) AND sudi(5)) AND sudi(6)) AND (NOT sudi(7))) AND sudi(8)) AND (NOT sudi(9))) AND (nl01iO34 XOR nl01iO33)); + nl00li <= ((((((((((sudi(0) AND sudi(1)) AND (NOT sudi(2))) AND (NOT sudi(3))) AND (NOT sudi(4))) AND (NOT sudi(5))) AND (NOT sudi(6))) AND sudi(7)) AND (NOT sudi(8))) AND sudi(9)) AND (nl01ll32 XOR nl01ll31)); + nl00OO <= (wire_n1l_dataout AND wire_w_lg_nl0iiO28w(0)); + nl010i <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOiiO OR niOiil))); + nl010l <= ((((wire_ni_w_lg_nii0l197w(0) AND wire_ni_w_lg_ni0iO198w(0)) AND wire_ni_w_lg_nii0O200w(0)) AND (nl01ii36 XOR nl01ii35)) OR nl010O); + nl010O <= (ni0iO AND (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (niOllO OR niOlll)))); + nl011i <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOill OR niOili))); + nl0i0O <= (wire_n1l_dataout AND wire_nlli_w_lg_nliO18w(0)); + nl0i1O <= ((NOT (n1Ol XOR reidle_com_detect(0))) AND (NOT (n1OO XOR reidle_com_detect(1)))); + nl0iiO <= ((((((((NOT (n01i XOR rwait_count(0))) AND (NOT (wire_ni1l_w_lg_n0ll115w(0) XOR (NOT (nl001l26 XOR nl001l25))))) AND (NOT (n0lO XOR rwait_count(2)))) AND (NOT (wire_ni1l_w_lg_n0Oi125w(0) XOR (NOT (nl01OO28 XOR nl01OO27))))) AND (NOT (n0Ol XOR rwait_count(4)))) AND (NOT (n0OO XOR rwait_count(5)))) AND (NOT (wire_ni1l_w_lg_ni1i138w(0) XOR (NOT (nl01Oi30 XOR nl01Oi29))))) AND (NOT (ni1O XOR rwait_count(7)))); + nl0ilO <= '1'; + nl100i <= ((wire_ni_w_lg_w699w700w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND wire_ni_w_lg_ni0li568w(0)); + nl100l <= ((wire_ni_w_lg_w690w707w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND wire_ni_w_lg_ni0li568w(0)); + nl100O <= (wire_ni_w_lg_w_lg_w_lg_w683w684w704w705w(0) AND ni0li); + nl101i <= (wire_ni_w_lg_w_lg_w690w691w696w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl101l <= ((wire_ni_w_lg_w_lg_w683w684w685w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl101O <= ((wire_ni_w_lg_w_lg_w683w684w685w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND wire_ni_w_lg_ni0li568w(0)); + nl10ii <= (wire_ni_w_lg_w_lg_w_lg_w683w684w704w705w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl10il <= (wire_ni_w_lg_w_lg_w699w710w711w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl10iO <= ((wire_ni_w_lg_w_lg_w683w684w704w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl10li <= ((wire_ni_w_lg_w699w710w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl10ll <= ((wire_ni_w_lg_w678w721w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND wire_ni_w_lg_ni0li568w(0)); + nl10lO <= (((wire_ni_w_lg_w669w670w(0) AND wire_ni_w_lg_ni0lO565w(0)) AND ni0ll) AND ni0li); + nl10Oi <= (((wire_ni_w728w(0) AND wire_ni_w_lg_ni0lO565w(0)) AND wire_ni_w_lg_ni0ll558w(0)) AND wire_ni_w_lg_ni0li568w(0)); + nl10Ol <= (wire_ni_w_lg_w_lg_w_lg_w683w724w725w726w(0) AND ni0li); + nl10OO <= (wire_ni_w_lg_w_lg_w_lg_w683w724w725w726w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl110i <= (wire_ni_w_lg_w_lg_w_lg_w643w644w645w646w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl110l <= ((wire_ni_w_lg_w_lg_w617w638w639w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl110O <= (wire_ni_w_lg_w_lg_w654w655w656w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl111i <= (wire_ni_w_lg_w_lg_w625w626w627w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl111l <= (wire_ni_w_lg_w_lg_w556w557w636w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl111O <= (wire_ni_w_lg_w_lg_w556w557w636w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl11ii <= ((wire_ni_w_lg_w_lg_w631w648w649w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl11il <= (wire_ni_w_lg_w_lg_w662w663w664w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl11iO <= ((wire_ni_w_lg_w564w658w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl11li <= ((wire_ni_w_lg_nii0l197w(0) AND wire_ni_w_lg_ni0iO198w(0)) AND wire_ni_w_lg_nii0O200w(0)); + nl11ll <= (((((((((((wire_w_lg_w_lg_w284w288w289w(0) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl1i1O OR nl1i1l)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl1i1i OR nl10OO)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl10Ol OR nl10Oi)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl10lO OR nl10ll)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl10li OR nl10iO)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl10il OR nl10ii)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl100O OR nl100l)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl100i OR nl101O)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl101l OR nl101i)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl11OO OR nl11Ol)))) OR (wire_ni_w_lg_nii0O200w(0) AND (wire_ni_w_lg_nii0l197w(0) AND (nl11Oi OR nl11lO)))); + nl11lO <= (wire_ni_w_lg_w_lg_w678w679w680w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl11Oi <= ((wire_ni_w_lg_w_lg_w669w670w671w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl11Ol <= ((wire_ni_w_lg_w690w691w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl11OO <= (wire_ni_w_lg_w_lg_w_lg_w683w684w685w686w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl1i0i <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOlil OR niOlii))); + nl1i0l <= ((((wire_ni_w778w(0) AND wire_ni_w_lg_niili750w(0)) AND wire_ni_w_lg_niiiO773w(0)) AND niiil) AND niiii); + nl1i0O <= (wire_ni_w_lg_w_lg_w772w774w775w(0) AND niiii); + nl1i1i <= (wire_ni_w_lg_w_lg_w732w733w734w(0) AND wire_ni_w_lg_ni0li568w(0)); + nl1i1l <= ((wire_ni_w_lg_w_lg_w683w724w725w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl1i1O <= ((wire_ni_w_lg_w732w733w(0) AND wire_ni_w_lg_ni0ll558w(0)) AND ni0li); + nl1iii <= (wire_ni_w_lg_w_lg_w_lg_w764w765w786w787w(0) AND wire_ni_w_lg_niiii755w(0)); + nl1iil <= (wire_ni_w_lg_w_lg_w751w783w784w(0) AND wire_ni_w_lg_niiii755w(0)); + nl1iiO <= ((wire_ni_w_lg_w_lg_w764w765w786w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1ili <= ((wire_ni_w_lg_w751w783w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1ill <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOl0O OR niOl0l))); + nl1ilO <= ((wire_ni_w_lg_w808w809w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1iOi <= (wire_ni_w_lg_w_lg_w_lg_w764w804w805w806w(0) AND wire_ni_w_lg_niiii755w(0)); + nl1iOl <= (wire_ni_w_lg_w_lg_w_lg_w815w816w817w818w(0) AND wire_ni_w_lg_niiii755w(0)); + nl1iOO <= (wire_ni_w_lg_w_lg_w800w812w813w(0) AND wire_ni_w_lg_niiii755w(0)); + nl1l0i <= ((wire_ni_w_lg_w825w826w(0) AND wire_ni_w_lg_niiil753w(0)) AND wire_ni_w_lg_niiii755w(0)); + nl1l0l <= (((wire_ni_w_lg_w815w816w(0) AND wire_ni_w_lg_niiiO773w(0)) AND niiil) AND niiii); + nl1l0O <= (((wire_ni_w800w(0) AND wire_ni_w_lg_niiiO773w(0)) AND niiil) AND niiii); + nl1l1i <= ((wire_ni_w_lg_w_lg_w815w816w817w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1l1l <= ((wire_ni_w_lg_w800w812w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1l1O <= ((wire_ni_w_lg_w_lg_w829w830w831w(0) AND wire_ni_w_lg_niiil753w(0)) AND wire_ni_w_lg_niiii755w(0)); + nl1lii <= (wire_ni_w_lg_w_lg_w_lg_w829w830w842w843w(0) AND wire_ni_w_lg_niiii755w(0)); + nl1lil <= (wire_ni_w_lg_w_lg_w825w839w840w(0) AND wire_ni_w_lg_niiii755w(0)); + nl1liO <= ((wire_ni_w_lg_w_lg_w829w830w842w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1lli <= ((wire_ni_w_lg_w825w839w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1lll <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOl0i OR niOl1O))); + nl1llO <= ((wire_ni_w_lg_w_lg_w764w804w805w(0) AND wire_ni_w_lg_niiil753w(0)) AND wire_ni_w_lg_niiii755w(0)); + nl1lOi <= (wire_ni_w_lg_w_lg_w808w809w860w(0) AND niiii); + nl1lOl <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOl1l OR niOl1i))); + nl1O0i <= ((wire_ni_w_lg_w_lg_w829w852w853w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1O0l <= ((wire_ni_w_lg_w867w868w(0) AND wire_ni_w_lg_niiil753w(0)) AND niiii); + nl1O0O <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOiOO OR niOiOl))); + nl1OiO <= (((wire_ni_w_lg_w829w852w(0) AND wire_ni_w_lg_niiiO773w(0)) AND niiil) AND niiii); + nl1Oli <= (((wire_ni_w867w(0) AND wire_ni_w_lg_niiiO773w(0)) AND niiil) AND niiii); + nl1OOi <= (wire_ni_w_lg_nil1O221w(0) AND (wire_ni_w_lg_nil1l222w(0) AND (niOiOi OR niOilO))); + rxelecidle_int <= wire_n1l_dataout; + wire_w_rwait_count_range75w(0) <= rwait_count(1); + wire_w_rwait_count_range73w(0) <= rwait_count(3); + wire_w_rwait_count_range70w(0) <= rwait_count(6); + wire_w_sudi_range87w(0) <= sudi(10); + wire_w_sudi_range89w(0) <= sudi(12); + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi0l51 <= niOi0l52; + END IF; + if (now = 0 ns) then + niOi0l51 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi0l52 <= niOi0l51; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi0O49 <= niOi0O50; + END IF; + if (now = 0 ns) then + niOi0O49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi0O50 <= niOi0O49; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl000l23 <= nl000l24; + END IF; + if (now = 0 ns) then + nl000l23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl000l24 <= nl000l23; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl001l25 <= nl001l26; + END IF; + if (now = 0 ns) then + nl001l25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl001l26 <= nl001l25; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00ii21 <= nl00ii22; + END IF; + if (now = 0 ns) then + nl00ii21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00ii22 <= nl00ii21; + END IF; + END PROCESS; + wire_nl00ii22_w_lg_q95w(0) <= nl00ii22 XOR nl00ii21; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00ll19 <= nl00ll20; + END IF; + if (now = 0 ns) then + nl00ll19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00ll20 <= nl00ll19; + END IF; + END PROCESS; + wire_nl00ll20_w_lg_w_lg_q76w77w(0) <= wire_nl00ll20_w_lg_q76w(0) AND n1Ol; + wire_nl00ll20_w_lg_q76w(0) <= nl00ll20 XOR nl00ll19; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00lO17 <= nl00lO18; + END IF; + if (now = 0 ns) then + nl00lO17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00lO18 <= nl00lO17; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00Oi15 <= nl00Oi16; + END IF; + if (now = 0 ns) then + nl00Oi15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00Oi16 <= nl00Oi15; + END IF; + END PROCESS; + wire_nl00Oi16_w_lg_w_lg_q39w40w(0) <= wire_nl00Oi16_w_lg_q39w(0) AND ni1i; + wire_nl00Oi16_w_lg_q39w(0) <= nl00Oi16 XOR nl00Oi15; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00Ol13 <= nl00Ol14; + END IF; + if (now = 0 ns) then + nl00Ol13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl00Ol14 <= nl00Ol13; + END IF; + END PROCESS; + wire_nl00Ol14_w_lg_w_lg_q30w31w(0) <= wire_nl00Ol14_w_lg_q30w(0) AND n01i; + wire_nl00Ol14_w_lg_q30w(0) <= nl00Ol14 XOR nl00Ol13; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl011l37 <= nl011l38; + END IF; + if (now = 0 ns) then + nl011l37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl011l38 <= nl011l37; + END IF; + END PROCESS; + wire_nl011l38_w_lg_w_lg_q208w209w(0) <= NOT wire_nl011l38_w_lg_q208w(0); + wire_nl011l38_w_lg_q208w(0) <= nl011l38 XOR nl011l37; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01ii35 <= nl01ii36; + END IF; + if (now = 0 ns) then + nl01ii35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01ii36 <= nl01ii35; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01iO33 <= nl01iO34; + END IF; + if (now = 0 ns) then + nl01iO33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01iO34 <= nl01iO33; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01ll31 <= nl01ll32; + END IF; + if (now = 0 ns) then + nl01ll31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01ll32 <= nl01ll31; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01Oi29 <= nl01Oi30; + END IF; + if (now = 0 ns) then + nl01Oi29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01Oi30 <= nl01Oi29; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01OO27 <= nl01OO28; + END IF; + if (now = 0 ns) then + nl01OO27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl01OO28 <= nl01OO27; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0i0i10 <= nl0i0i9; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0i0i9 <= nl0i0i10; + END IF; + if (now = 0 ns) then + nl0i0i9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0i0l7 <= nl0i0l8; + END IF; + if (now = 0 ns) then + nl0i0l7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0i0l8 <= nl0i0l7; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0i1i11 <= nl0i1i12; + END IF; + if (now = 0 ns) then + nl0i1i11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0i1i12 <= nl0i1i11; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0iii5 <= nl0iii6; + END IF; + if (now = 0 ns) then + nl0iii5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0iii6 <= nl0iii5; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0ili3 <= nl0ili4; + END IF; + if (now = 0 ns) then + nl0ili3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0ili4 <= nl0ili3; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0iOi1 <= nl0iOi2; + END IF; + if (now = 0 ns) then + nl0iOi1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl0iOi2 <= nl0iOi1; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1lOO47 <= nl1lOO48; + END IF; + if (now = 0 ns) then + nl1lOO47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1lOO48 <= nl1lOO47; + END IF; + END PROCESS; + wire_nl1lOO48_w_lg_w_lg_q239w240w(0) <= NOT wire_nl1lOO48_w_lg_q239w(0); + wire_nl1lOO48_w_lg_q239w(0) <= nl1lOO48 XOR nl1lOO47; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1O1l45 <= nl1O1l46; + END IF; + if (now = 0 ns) then + nl1O1l45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1O1l46 <= nl1O1l45; + END IF; + END PROCESS; + wire_nl1O1l46_w_lg_q235w(0) <= nl1O1l46 XOR nl1O1l45; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1Oii43 <= nl1Oii44; + END IF; + if (now = 0 ns) then + nl1Oii43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1Oii44 <= nl1Oii43; + END IF; + END PROCESS; + wire_nl1Oii44_w_lg_q227w(0) <= nl1Oii44 XOR nl1Oii43; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1Oll41 <= nl1Oll42; + END IF; + if (now = 0 ns) then + nl1Oll41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1Oll42 <= nl1Oll41; + END IF; + END PROCESS; + wire_nl1Oll42_w_lg_w_lg_q218w219w(0) <= NOT wire_nl1Oll42_w_lg_q218w(0); + wire_nl1Oll42_w_lg_q218w(0) <= nl1Oll42 XOR nl1Oll41; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1OOl39 <= nl1OOl40; + END IF; + if (now = 0 ns) then + nl1OOl39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nl1OOl40 <= nl1OOl39; + END IF; + END PROCESS; + wire_nl1OOl40_w_lg_w_lg_q213w214w(0) <= NOT wire_nl1OOl40_w_lg_q213w(0); + wire_nl1OOl40_w_lg_q213w(0) <= nl1OOl40 XOR nl1OOl39; + PROCESS (rcvd_clk, wire_ni_CLRN) + BEGIN + IF (wire_ni_CLRN = '0') THEN + n0l <= '0'; + n0OlO <= '0'; + n0OOi <= '0'; + n0OOl <= '0'; + n0OOO <= '0'; + n1Ol <= '0'; + n1OlO <= '0'; + n1OO <= '0'; + ni00i <= '0'; + ni00l <= '0'; + ni00O <= '0'; + ni01i <= '0'; + ni01l <= '0'; + ni01O <= '0'; + ni0i <= '0'; + ni0il <= '0'; + ni0iO <= '0'; + ni0li <= '0'; + ni0ll <= '0'; + ni0lO <= '0'; + ni0Oi <= '0'; + ni0Ol <= '0'; + ni0OO <= '0'; + ni10i <= '0'; + ni10l <= '0'; + ni10O <= '0'; + ni11i <= '0'; + ni11l <= '0'; + ni11O <= '0'; + ni1ii <= '0'; + ni1il <= '0'; + ni1iO <= '0'; + ni1li <= '0'; + ni1ll <= '0'; + ni1lO <= '0'; + ni1Oi <= '0'; + ni1Ol <= '0'; + ni1OO <= '0'; + nii0i <= '0'; + nii0l <= '0'; + nii0O <= '0'; + nii1i <= '0'; + nii1l <= '0'; + nii1O <= '0'; + niiii <= '0'; + niiil <= '0'; + niiiO <= '0'; + niili <= '0'; + niill <= '0'; + niilO <= '0'; + niiOi <= '0'; + niiOl <= '0'; + niiOO <= '0'; + nil1i <= '0'; + nil1l <= '0'; + nil1O <= '0'; + nl <= '0'; + nl0l0O <= '0'; + nl0lli <= '0'; + nl0O0i <= '0'; + nl0O0l <= '0'; + nl0O0O <= '0'; + nl0O1i <= '0'; + nl0O1l <= '0'; + nl0O1O <= '0'; + nl0Oii <= '0'; + nl0Oil <= '0'; + nl0OiO <= '0'; + nl0Oli <= '0'; + nl0Oll <= '0'; + nl0OlO <= '0'; + nli0ll <= '0'; + nli0Oi <= '0'; + nli0OO <= '0'; + nli10l <= '0'; + nli10O <= '0'; + nli1ii <= '0'; + nli1il <= '0'; + nli1iO <= '0'; + nli1li <= '0'; + nli1ll <= '0'; + nli1lO <= '0'; + nli1Oi <= '0'; + nlii0i <= '0'; + nlii0l <= '0'; + nlii0O <= '0'; + nlii1i <= '0'; + nlii1l <= '0'; + nlii1O <= '0'; + nliiii <= '0'; + nliiil <= '0'; + nliiiO <= '0'; + nliili <= '0'; + nliill <= '0'; + nliilO <= '0'; + nliiOi <= '0'; + nliiOl <= '0'; + nlil <= '0'; + nll <= '0'; + nlO <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + n0l <= nll; + n0OlO <= wire_n1OiO_dataout; + n0OOi <= wire_n1Oli_dataout; + n0OOl <= wire_n1Oll_dataout; + n0OOO <= wire_n1OOi_dataout; + n1Ol <= wire_n01l_dataout; + n1OlO <= wire_n1Oii_o; + n1OO <= wire_n01O_dataout; + ni00i <= wire_n001O_dataout; + ni00l <= wire_n000i_dataout; + ni00O <= wire_n000l_o; + ni01i <= wire_n01OO_dataout; + ni01l <= wire_n001i_dataout; + ni01O <= wire_n001l_dataout; + ni0i <= nl0i1O; + ni0il <= syncstatus; + ni0iO <= kflag; + ni0li <= sudi(0); + ni0ll <= sudi(1); + ni0lO <= sudi(2); + ni0Oi <= sudi(3); + ni0Ol <= sudi(4); + ni0OO <= sudi(5); + ni10i <= wire_n011l_dataout; + ni10l <= wire_n011O_dataout; + ni10O <= wire_n010i_dataout; + ni11i <= wire_n1OOl_dataout; + ni11l <= wire_n1OOO_dataout; + ni11O <= wire_n011i_dataout; + ni1ii <= wire_n010l_dataout; + ni1il <= wire_n010O_dataout; + ni1iO <= wire_n01ii_dataout; + ni1li <= wire_n01il_dataout; + ni1ll <= wire_n01iO_dataout; + ni1lO <= wire_n01li_dataout; + ni1Oi <= wire_n01ll_dataout; + ni1Ol <= wire_n01lO_o; + ni1OO <= wire_n01Ol_dataout; + nii0i <= sudi(9); + nii0l <= sudi(10); + nii0O <= sudi(12); + nii1i <= sudi(6); + nii1l <= sudi(7); + nii1O <= sudi(8); + niiii <= sudi(0); + niiil <= sudi(1); + niiiO <= sudi(2); + niili <= sudi(3); + niill <= sudi(4); + niilO <= sudi(5); + niiOi <= sudi(6); + niiOl <= sudi(7); + niiOO <= sudi(8); + nil1i <= sudi(9); + nil1l <= sudi(10); + nil1O <= sudi(12); + nl <= signaldetect; + nl0l0O <= nl0lli; + nl0lli <= wire_nl0lll_dataout; + nl0O0i <= wire_nl0OOO_o(0); + nl0O0l <= (wire_nli10i_o(6) OR wire_nli10i_o(5)); + nl0O0O <= ((wire_nli10i_o(2) OR wire_nli10i_o(0)) OR wire_nli10i_o(5)); + nl0O1i <= wire_nli10i_o(1); + nl0O1l <= wire_nl0OOi_o(1); + nl0O1O <= ((wire_nli10i_o(7) OR wire_nli10i_o(3)) OR wire_nli10i_o(1)); + nl0Oii <= niOi1l; + nl0Oil <= niOi1l; + nl0OiO <= niOi1l; + nl0Oli <= niOi1l; + nl0Oll <= wire_nli10i_o(6); + nl0OlO <= (NOT (((NOT (nli1il XOR nli10l)) AND (NOT (nli1iO XOR nli10O))) AND (NOT (nli1li XOR nli1ii)))); + nli0ll <= wire_nliiOO_dataout; + nli0Oi <= wire_nli0lO_dataout; + nli0OO <= wire_nlil1i_dataout; + nli10l <= nli1il; + nli10O <= nli1iO; + nli1ii <= nli1li; + nli1il <= nli1ll; + nli1iO <= nli1lO; + nli1li <= nli1Oi; + nli1ll <= eidleinfersel(0); + nli1lO <= eidleinfersel(1); + nli1Oi <= eidleinfersel(2); + nlii0i <= wire_nlil0l_dataout; + nlii0l <= wire_nlil0O_dataout; + nlii0O <= wire_nlilii_dataout; + nlii1i <= wire_nlil1l_dataout; + nlii1l <= wire_nlil1O_dataout; + nlii1O <= wire_nlil0i_dataout; + nliiii <= wire_nlilil_dataout; + nliiil <= wire_nliliO_dataout; + nliiiO <= wire_nlilli_dataout; + nliili <= wire_nlilll_dataout; + nliill <= wire_nlillO_dataout; + nliilO <= wire_nlilOi_dataout; + nliiOi <= wire_nlilOl_dataout; + nliiOl <= wire_nlilOO_dataout; + nlil <= (wire_ni_w_lg_w_lg_ni0i23w24w(0) AND (nl0i1i12 XOR nl0i1i11)); + nll <= wire_nO_dataout; + nlO <= nl; + END IF; + END PROCESS; + wire_ni_CLRN <= ((nl0iOi2 XOR nl0iOi1) AND wire_w_lg_rxpcsrst2w(0)); + wire_ni_w_lg_w_lg_w_lg_w683w724w725w726w(0) <= wire_ni_w_lg_w_lg_w683w724w725w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w_lg_w683w684w704w705w(0) <= wire_ni_w_lg_w_lg_w683w684w704w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w_lg_w683w684w685w686w(0) <= wire_ni_w_lg_w_lg_w683w684w685w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w_lg_w631w632w633w634w(0) <= wire_ni_w_lg_w_lg_w631w632w633w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w_lg_w643w644w645w646w(0) <= wire_ni_w_lg_w_lg_w643w644w645w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w_lg_w617w618w619w620w(0) <= wire_ni_w_lg_w_lg_w617w618w619w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w_lg_w815w816w817w818w(0) <= wire_ni_w_lg_w_lg_w815w816w817w(0) AND niiil; + wire_ni_w_lg_w_lg_w_lg_w829w852w853w854w(0) <= wire_ni_w_lg_w_lg_w829w852w853w(0) AND niiil; + wire_ni_w_lg_w_lg_w_lg_w829w830w842w843w(0) <= wire_ni_w_lg_w_lg_w829w830w842w(0) AND niiil; + wire_ni_w_lg_w_lg_w_lg_w829w830w831w897w(0) <= wire_ni_w_lg_w_lg_w829w830w831w(0) AND niiil; + wire_ni_w_lg_w_lg_w_lg_w764w765w786w787w(0) <= wire_ni_w_lg_w_lg_w764w765w786w(0) AND niiil; + wire_ni_w_lg_w_lg_w_lg_w764w765w766w796w(0) <= wire_ni_w_lg_w_lg_w764w765w766w(0) AND niiil; + wire_ni_w_lg_w_lg_w_lg_w764w804w805w806w(0) <= wire_ni_w_lg_w_lg_w764w804w805w(0) AND niiil; + wire_ni_w_lg_w_lg_w662w663w664w(0) <= wire_ni_w_lg_w662w663w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w556w557w636w(0) <= wire_ni_w_lg_w556w557w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w564w566w567w(0) <= wire_ni_w_lg_w564w566w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w654w655w656w(0) <= wire_ni_w_lg_w654w655w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w625w626w627w(0) <= wire_ni_w_lg_w625w626w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w678w679w680w(0) <= wire_ni_w_lg_w678w679w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w732w733w734w(0) <= wire_ni_w_lg_w732w733w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w699w710w711w(0) <= wire_ni_w_lg_w699w710w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w690w691w696w(0) <= wire_ni_w_lg_w690w691w(0) AND ni0ll; + wire_ni_w_lg_w_lg_w808w809w860w(0) <= wire_ni_w_lg_w808w809w(0) AND niiil; + wire_ni_w_lg_w_lg_w800w812w813w(0) <= wire_ni_w_lg_w800w812w(0) AND niiil; + wire_ni_w_lg_w_lg_w772w774w775w(0) <= wire_ni_w_lg_w772w774w(0) AND niiil; + wire_ni_w_lg_w_lg_w867w868w869w(0) <= wire_ni_w_lg_w867w868w(0) AND niiil; + wire_ni_w_lg_w_lg_w825w839w840w(0) <= wire_ni_w_lg_w825w839w(0) AND niiil; + wire_ni_w_lg_w_lg_w751w783w784w(0) <= wire_ni_w_lg_w751w783w(0) AND niiil; + wire_ni_w_lg_w_lg_w683w724w725w(0) <= wire_ni_w_lg_w683w724w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w683w684w704w(0) <= wire_ni_w_lg_w683w684w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w_lg_w683w684w685w(0) <= wire_ni_w_lg_w683w684w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w669w670w671w(0) <= wire_ni_w_lg_w669w670w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w631w632w633w(0) <= wire_ni_w_lg_w631w632w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w631w648w649w(0) <= wire_ni_w_lg_w631w648w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w603w604w605w(0) <= wire_ni_w_lg_w603w604w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w643w644w645w(0) <= wire_ni_w_lg_w643w644w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w_lg_w617w618w619w(0) <= wire_ni_w_lg_w617w618w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w617w638w639w(0) <= wire_ni_w_lg_w617w638w(0) AND ni0lO; + wire_ni_w_lg_w_lg_w815w816w817w(0) <= wire_ni_w_lg_w815w816w(0) AND niiiO; + wire_ni_w_lg_w_lg_w829w852w853w(0) <= wire_ni_w_lg_w829w852w(0) AND niiiO; + wire_ni_w_lg_w_lg_w829w830w842w(0) <= wire_ni_w_lg_w829w830w(0) AND wire_ni_w_lg_niiiO773w(0); + wire_ni_w_lg_w_lg_w829w830w831w(0) <= wire_ni_w_lg_w829w830w(0) AND niiiO; + wire_ni_w_lg_w_lg_w764w765w786w(0) <= wire_ni_w_lg_w764w765w(0) AND wire_ni_w_lg_niiiO773w(0); + wire_ni_w_lg_w_lg_w764w765w766w(0) <= wire_ni_w_lg_w764w765w(0) AND niiiO; + wire_ni_w_lg_w_lg_w764w804w805w(0) <= wire_ni_w_lg_w764w804w(0) AND wire_ni_w_lg_niiiO773w(0); + wire_ni_w_lg_w662w663w(0) <= wire_ni_w662w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w556w557w(0) <= wire_ni_w556w(0) AND ni0lO; + wire_ni_w_lg_w564w566w(0) <= wire_ni_w564w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w564w658w(0) <= wire_ni_w564w(0) AND ni0lO; + wire_ni_w_lg_w654w655w(0) <= wire_ni_w654w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w625w626w(0) <= wire_ni_w625w(0) AND ni0lO; + wire_ni_w_lg_w678w679w(0) <= wire_ni_w678w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w678w721w(0) <= wire_ni_w678w(0) AND ni0lO; + wire_ni_w_lg_w732w733w(0) <= wire_ni_w732w(0) AND ni0lO; + wire_ni_w_lg_w699w710w(0) <= wire_ni_w699w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w699w700w(0) <= wire_ni_w699w(0) AND ni0lO; + wire_ni_w_lg_w690w691w(0) <= wire_ni_w690w(0) AND wire_ni_w_lg_ni0lO565w(0); + wire_ni_w_lg_w690w707w(0) <= wire_ni_w690w(0) AND ni0lO; + wire_ni_w_lg_w808w809w(0) <= wire_ni_w808w(0) AND niiiO; + wire_ni_w_lg_w800w812w(0) <= wire_ni_w800w(0) AND niiiO; + wire_ni_w_lg_w772w774w(0) <= wire_ni_w772w(0) AND wire_ni_w_lg_niiiO773w(0); + wire_ni_w_lg_w772w880w(0) <= wire_ni_w772w(0) AND niiiO; + wire_ni_w_lg_w867w868w(0) <= wire_ni_w867w(0) AND niiiO; + wire_ni_w_lg_w825w839w(0) <= wire_ni_w825w(0) AND wire_ni_w_lg_niiiO773w(0); + wire_ni_w_lg_w825w826w(0) <= wire_ni_w825w(0) AND niiiO; + wire_ni_w_lg_w751w783w(0) <= wire_ni_w751w(0) AND wire_ni_w_lg_niiiO773w(0); + wire_ni_w_lg_w751w752w(0) <= wire_ni_w751w(0) AND niiiO; + wire_ni_w_lg_w683w724w(0) <= wire_ni_w683w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w_lg_w683w684w(0) <= wire_ni_w683w(0) AND ni0Oi; + wire_ni_w_lg_w669w670w(0) <= wire_ni_w669w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w_lg_w631w632w(0) <= wire_ni_w631w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w_lg_w631w648w(0) <= wire_ni_w631w(0) AND ni0Oi; + wire_ni_w_lg_w603w604w(0) <= wire_ni_w603w(0) AND ni0Oi; + wire_ni_w_lg_w643w644w(0) <= wire_ni_w643w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w_lg_w617w618w(0) <= wire_ni_w617w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w_lg_w617w638w(0) <= wire_ni_w617w(0) AND ni0Oi; + wire_ni_w_lg_w815w816w(0) <= wire_ni_w815w(0) AND niili; + wire_ni_w_lg_w829w852w(0) <= wire_ni_w829w(0) AND wire_ni_w_lg_niili750w(0); + wire_ni_w_lg_w829w830w(0) <= wire_ni_w829w(0) AND niili; + wire_ni_w_lg_w764w765w(0) <= wire_ni_w764w(0) AND wire_ni_w_lg_niili750w(0); + wire_ni_w_lg_w764w804w(0) <= wire_ni_w764w(0) AND niili; + wire_ni_w662w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w608w661w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w556w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w552w554w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w564w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w552w554w(0) AND ni0Oi; + wire_ni_w654w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w652w653w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w625w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w623w624w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w678w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w677w(0) AND ni0Oi; + wire_ni_w732w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w698w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w699w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w698w(0) AND ni0Oi; + wire_ni_w690w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w688w689w(0) AND wire_ni_w_lg_ni0Oi555w(0); + wire_ni_w728w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w688w689w(0) AND ni0Oi; + wire_ni_w591w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w587w588w589w590w(0) AND ni0Oi; + wire_ni_w808w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w799w(0) AND wire_ni_w_lg_niili750w(0); + wire_ni_w800w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w799w(0) AND niili; + wire_ni_w772w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w771w(0) AND wire_ni_w_lg_niili750w(0); + wire_ni_w856w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w771w(0) AND niili; + wire_ni_w867w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w824w(0) AND wire_ni_w_lg_niili750w(0); + wire_ni_w825w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w824w(0) AND niili; + wire_ni_w751w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w749w(0) AND wire_ni_w_lg_niili750w(0); + wire_ni_w581w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w577w578w580w(0) AND ni0Ol; + wire_ni_w683w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w682w(0) AND ni0Ol; + wire_ni_w669w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w668w(0) AND ni0Ol; + wire_ni_w631w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w629w630w(0) AND wire_ni_w_lg_ni0Ol553w(0); + wire_ni_w603w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w601w602w(0) AND ni0Ol; + wire_ni_w643w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w642w(0) AND ni0Ol; + wire_ni_w617w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w616w(0) AND wire_ni_w_lg_ni0Ol553w(0); + wire_ni_w815w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w777w(0) AND wire_ni_w_lg_niill798w(0); + wire_ni_w778w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w777w(0) AND niill; + wire_ni_w829w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w763w(0) AND wire_ni_w_lg_niill798w(0); + wire_ni_w764w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w763w(0) AND niill; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w608w661w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w608w(0) AND ni0Ol; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w552w554w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w552w(0) AND wire_ni_w_lg_ni0Ol553w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w652w653w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w652w(0) AND ni0Ol; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w623w624w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w623w(0) AND wire_ni_w_lg_ni0Ol553w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w677w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w(0) AND wire_ni_w_lg_ni0Ol553w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w698w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w(0) AND ni0Ol; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w688w689w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w688w(0) AND wire_ni_w_lg_ni0Ol553w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i586w587w588w589w590w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w587w588w589w(0) AND wire_ni_w_lg_ni0Ol553w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w799w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w(0) AND wire_ni_w_lg_niill798w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w771w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w(0) AND niill; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w824w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w(0) AND wire_ni_w_lg_niill798w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w749w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w(0) AND niill; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w577w578w580w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w575w577w578w(0) AND wire_ni_w_lg_ni0OO579w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w682w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w(0) AND wire_ni_w_lg_ni0OO579w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w668w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w629w630w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w629w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w601w602w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w601w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w642w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w(0) AND wire_ni_w_lg_ni0OO579w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w616w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w777w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w(0) AND wire_ni_w_lg_niilO769w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w763w(0) <= wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w(0) AND niilO; + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w608w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i548w549w551w(0) AND wire_ni_w_lg_ni0OO579w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w551w552w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i548w549w551w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w652w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i548w549w622w(0) AND wire_ni_w_lg_ni0OO579w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i548w549w622w623w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i548w549w622w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w676w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i586w674w675w(0) AND wire_ni_w_lg_ni0OO579w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w674w675w688w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i586w674w675w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i586w587w588w589w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i586w587w588w(0) AND ni0OO; + wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w770w(0) <= wire_ni_w_lg_w_lg_w_lg_nil1i744w746w747w(0) AND wire_ni_w_lg_niilO769w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i744w746w747w748w(0) <= wire_ni_w_lg_w_lg_w_lg_nil1i744w746w747w(0) AND niilO; + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w575w577w578w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i574w575w577w(0) AND nii1i; + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w575w666w667w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i574w575w666w(0) AND wire_ni_w_lg_nii1i550w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w629w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i574w599w600w(0) AND wire_ni_w_lg_nii1i550w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w600w601w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i574w599w600w(0) AND nii1i; + wire_ni_w_lg_w_lg_w_lg_w_lg_nii0i574w599w614w615w(0) <= wire_ni_w_lg_w_lg_w_lg_nii0i574w599w614w(0) AND wire_ni_w_lg_nii1i550w(0); + wire_ni_w_lg_w_lg_w_lg_w_lg_nil1i757w759w760w762w(0) <= wire_ni_w_lg_w_lg_w_lg_nil1i757w759w760w(0) AND wire_ni_w_lg_niiOi761w(0); + wire_ni_w_lg_w_lg_w_lg_nii0i548w549w551w(0) <= wire_ni_w_lg_w_lg_nii0i548w549w(0) AND wire_ni_w_lg_nii1i550w(0); + wire_ni_w_lg_w_lg_w_lg_nii0i548w549w622w(0) <= wire_ni_w_lg_w_lg_nii0i548w549w(0) AND nii1i; + wire_ni_w_lg_w_lg_w_lg_nii0i586w674w675w(0) <= wire_ni_w_lg_w_lg_nii0i586w674w(0) AND nii1i; + wire_ni_w_lg_w_lg_w_lg_nii0i586w587w588w(0) <= wire_ni_w_lg_w_lg_nii0i586w587w(0) AND wire_ni_w_lg_nii1i550w(0); + wire_ni_w_lg_w_lg_w_lg_nil1i744w746w747w(0) <= wire_ni_w_lg_w_lg_nil1i744w746w(0) AND niiOi; + wire_ni_w_lg_w_lg_w_lg_nii0i574w575w577w(0) <= wire_ni_w_lg_w_lg_nii0i574w575w(0) AND wire_ni_w_lg_nii1l576w(0); + wire_ni_w_lg_w_lg_w_lg_nii0i574w575w666w(0) <= wire_ni_w_lg_w_lg_nii0i574w575w(0) AND nii1l; + wire_ni_w_lg_w_lg_w_lg_nii0i574w599w600w(0) <= wire_ni_w_lg_w_lg_nii0i574w599w(0) AND wire_ni_w_lg_nii1l576w(0); + wire_ni_w_lg_w_lg_w_lg_nii0i574w599w614w(0) <= wire_ni_w_lg_w_lg_nii0i574w599w(0) AND nii1l; + wire_ni_w_lg_w_lg_w_lg_nil1i757w759w760w(0) <= wire_ni_w_lg_w_lg_nil1i757w759w(0) AND niiOl; + wire_ni_w_lg_w_lg_w_lg_nil1O221w233w236w(0) <= wire_ni_w_lg_w_lg_nil1O221w233w(0) AND wire_nl1O1l46_w_lg_q235w(0); + wire_ni_w_lg_w_lg_w_lg_nil1O221w225w228w(0) <= wire_ni_w_lg_w_lg_nil1O221w225w(0) AND wire_nl1Oii44_w_lg_q227w(0); + wire_ni_w_lg_w_lg_nii0i548w549w(0) <= wire_ni_w_lg_nii0i548w(0) AND nii1l; + wire_ni_w_lg_w_lg_nii0i586w674w(0) <= wire_ni_w_lg_nii0i586w(0) AND wire_ni_w_lg_nii1l576w(0); + wire_ni_w_lg_w_lg_nii0i586w587w(0) <= wire_ni_w_lg_nii0i586w(0) AND nii1l; + wire_ni_w_lg_w_lg_nil1i744w746w(0) <= wire_ni_w_lg_nil1i744w(0) AND wire_ni_w_lg_niiOl745w(0); + wire_ni_w_lg_w_lg_ni0i23w24w(0) <= wire_ni_w_lg_ni0i23w(0) AND nl0i1O; + wire_ni_w_lg_w_lg_nii0i574w575w(0) <= wire_ni_w_lg_nii0i574w(0) AND wire_ni_w_lg_nii1O547w(0); + wire_ni_w_lg_w_lg_nii0i574w599w(0) <= wire_ni_w_lg_nii0i574w(0) AND nii1O; + wire_ni_w_lg_w_lg_nii0l197w343w(0) <= wire_ni_w_lg_nii0l197w(0) AND wire_w_lg_nl110l342w(0); + wire_ni_w_lg_w_lg_nii0l197w339w(0) <= wire_ni_w_lg_nii0l197w(0) AND wire_w_lg_nl11ii338w(0); + wire_ni_w_lg_w_lg_nii0l197w335w(0) <= wire_ni_w_lg_nii0l197w(0) AND wire_w_lg_nl11iO334w(0); + wire_ni_w_lg_w_lg_nii0O200w344w(0) <= wire_ni_w_lg_nii0O200w(0) AND wire_ni_w_lg_w_lg_nii0l197w343w(0); + wire_ni_w_lg_w_lg_nii0O200w340w(0) <= wire_ni_w_lg_nii0O200w(0) AND wire_ni_w_lg_w_lg_nii0l197w339w(0); + wire_ni_w_lg_w_lg_nii0O200w336w(0) <= wire_ni_w_lg_nii0O200w(0) AND wire_ni_w_lg_w_lg_nii0l197w335w(0); + wire_ni_w_lg_w_lg_nil1i757w759w(0) <= wire_ni_w_lg_nil1i757w(0) AND wire_ni_w_lg_niiOO758w(0); + wire_ni_w_lg_w_lg_nil1l222w286w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1i0O285w(0); + wire_ni_w_lg_w_lg_nil1l222w282w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1iil281w(0); + wire_ni_w_lg_w_lg_nil1l222w278w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1ili277w(0); + wire_ni_w_lg_w_lg_nil1l222w273w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1iOi272w(0); + wire_ni_w_lg_w_lg_nil1l222w269w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1iOO268w(0); + wire_ni_w_lg_w_lg_nil1l222w261w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1l0i260w(0); + wire_ni_w_lg_w_lg_nil1l222w257w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1l0O256w(0); + wire_ni_w_lg_w_lg_nil1l222w265w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1l1l264w(0); + wire_ni_w_lg_w_lg_nil1l222w253w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1lil252w(0); + wire_ni_w_lg_w_lg_nil1l222w249w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1lli248w(0); + wire_ni_w_lg_w_lg_nil1l222w244w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1lOi243w(0); + wire_ni_w_lg_w_lg_nil1l222w232w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1O0l231w(0); + wire_ni_w_lg_w_lg_nil1l222w224w(0) <= wire_ni_w_lg_nil1l222w(0) AND wire_w_lg_nl1Oli223w(0); + wire_ni_w_lg_w_lg_nil1O221w287w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w286w(0); + wire_ni_w_lg_w_lg_nil1O221w283w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w282w(0); + wire_ni_w_lg_w_lg_nil1O221w279w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w278w(0); + wire_ni_w_lg_w_lg_nil1O221w274w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w273w(0); + wire_ni_w_lg_w_lg_nil1O221w270w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w269w(0); + wire_ni_w_lg_w_lg_nil1O221w262w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w261w(0); + wire_ni_w_lg_w_lg_nil1O221w258w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w257w(0); + wire_ni_w_lg_w_lg_nil1O221w266w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w265w(0); + wire_ni_w_lg_w_lg_nil1O221w254w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w253w(0); + wire_ni_w_lg_w_lg_nil1O221w250w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w249w(0); + wire_ni_w_lg_w_lg_nil1O221w245w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w244w(0); + wire_ni_w_lg_w_lg_nil1O221w233w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w232w(0); + wire_ni_w_lg_w_lg_nil1O221w225w(0) <= wire_ni_w_lg_nil1O221w(0) AND wire_ni_w_lg_w_lg_nil1l222w224w(0); + wire_ni_w_lg_nii0i548w(0) <= nii0i AND wire_ni_w_lg_nii1O547w(0); + wire_ni_w_lg_nii0i586w(0) <= nii0i AND nii1O; + wire_ni_w_lg_nil1i744w(0) <= nil1i AND niiOO; + wire_ni_w_lg_nlO9w(0) <= nlO AND nl0iiO; + wire_ni_w_lg_n0l16w(0) <= NOT n0l; + wire_ni_w_lg_ni0i23w(0) <= NOT ni0i; + wire_ni_w_lg_ni0il366w(0) <= NOT ni0il; + wire_ni_w_lg_ni0iO198w(0) <= NOT ni0iO; + wire_ni_w_lg_ni0li568w(0) <= NOT ni0li; + wire_ni_w_lg_ni0ll558w(0) <= NOT ni0ll; + wire_ni_w_lg_ni0lO565w(0) <= NOT ni0lO; + wire_ni_w_lg_ni0Oi555w(0) <= NOT ni0Oi; + wire_ni_w_lg_ni0Ol553w(0) <= NOT ni0Ol; + wire_ni_w_lg_ni0OO579w(0) <= NOT ni0OO; + wire_ni_w_lg_nii0i574w(0) <= NOT nii0i; + wire_ni_w_lg_nii0l197w(0) <= NOT nii0l; + wire_ni_w_lg_nii0O200w(0) <= NOT nii0O; + wire_ni_w_lg_nii1i550w(0) <= NOT nii1i; + wire_ni_w_lg_nii1l576w(0) <= NOT nii1l; + wire_ni_w_lg_nii1O547w(0) <= NOT nii1O; + wire_ni_w_lg_niiii755w(0) <= NOT niiii; + wire_ni_w_lg_niiil753w(0) <= NOT niiil; + wire_ni_w_lg_niiiO773w(0) <= NOT niiiO; + wire_ni_w_lg_niili750w(0) <= NOT niili; + wire_ni_w_lg_niill798w(0) <= NOT niill; + wire_ni_w_lg_niilO769w(0) <= NOT niilO; + wire_ni_w_lg_niiOi761w(0) <= NOT niiOi; + wire_ni_w_lg_niiOl745w(0) <= NOT niiOl; + wire_ni_w_lg_niiOO758w(0) <= NOT niiOO; + wire_ni_w_lg_nil1i757w(0) <= NOT nil1i; + wire_ni_w_lg_nil1l222w(0) <= NOT nil1l; + wire_ni_w_lg_nil1O221w(0) <= NOT nil1O; + wire_ni_w_lg_nli0ll989w(0) <= NOT nli0ll; + wire_ni_w_lg_nli0OO987w(0) <= NOT nli0OO; + wire_ni_w_lg_nli1li907w(0) <= NOT nli1li; + wire_ni_w_lg_nlii0i982w(0) <= NOT nlii0i; + wire_ni_w_lg_nlii1i985w(0) <= NOT nlii1i; + wire_ni_w_lg_nlii1O983w(0) <= NOT nlii1O; + wire_ni_w_lg_nlil911w(0) <= NOT nlil; + wire_ni_w_lg_w_lg_nlO9w10w(0) <= wire_ni_w_lg_nlO9w(0) OR nlil; + wire_ni_w_lg_n0l1088w(0) <= n0l OR nl0l0O; + PROCESS (rcvd_clk, wire_ni1l_CLRN, rxpcsrst, rwait_count(0), rwait_count(1), rwait_count(2), rwait_count(3), rwait_count(4), rwait_count(5), rwait_count(6), rwait_count(7)) + BEGIN + IF (wire_ni1l_CLRN = '0') THEN + n01i <= '0'; + n0ll <= '0'; + n0lO <= '0'; + n0Oi <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + ni1i <= '0'; + ni1O <= '0'; + ELSIF (rxpcsrst = '1') THEN + n01i <= rwait_count(0); + n0ll <= rwait_count(1); + n0lO <= rwait_count(2); + n0Oi <= rwait_count(3); + n0Ol <= rwait_count(4); + n0OO <= rwait_count(5); + ni1i <= rwait_count(6); + ni1O <= rwait_count(7); + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + n01i <= wire_ni0l_dataout; + n0ll <= wire_ni0O_dataout; + n0lO <= wire_niii_dataout; + n0Oi <= wire_niil_dataout; + n0Ol <= wire_niiO_dataout; + n0OO <= wire_nili_dataout; + ni1i <= wire_nill_dataout; + ni1O <= wire_nilO_dataout; + END IF; + END PROCESS; + wire_ni1l_CLRN <= (nl00lO18 XOR nl00lO17); + wire_ni1l_w_lg_n0ll115w(0) <= n0ll XOR wire_w_rwait_count_range75w(0); + wire_ni1l_w_lg_n0Oi125w(0) <= n0Oi XOR wire_w_rwait_count_range73w(0); + wire_ni1l_w_lg_ni1i138w(0) <= ni1i XOR wire_w_rwait_count_range70w(0); + PROCESS (rcvd_clk, wire_nliOlO_PRN, wire_nliOlO_CLRN) + BEGIN + IF (wire_nliOlO_PRN = '0') THEN + nliO0i <= '1'; + nliO0l <= '1'; + nliO0O <= '1'; + nliO1l <= '1'; + nliO1O <= '1'; + nliOii <= '1'; + nliOil <= '1'; + nliOiO <= '1'; + nliOli <= '1'; + nliOll <= '1'; + nliOOi <= '1'; + ELSIF (wire_nliOlO_CLRN = '0') THEN + nliO0i <= '0'; + nliO0l <= '0'; + nliO0O <= '0'; + nliO1l <= '0'; + nliO1O <= '0'; + nliOii <= '0'; + nliOil <= '0'; + nliOiO <= '0'; + nliOli <= '0'; + nliOll <= '0'; + nliOOi <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + IF (niOiii = '1') THEN + nliO0i <= nl0O1O; + nliO0l <= nl0O0i; + nliO0O <= nl0O0l; + nliO1l <= nl0O1i; + nliO1O <= nl0O1l; + nliOii <= nl0O0O; + nliOil <= nl0Oii; + nliOiO <= nl0Oil; + nliOli <= nl0OiO; + nliOll <= nl0Oli; + nliOOi <= nl0Oll; + END IF; + END IF; + END PROCESS; + wire_nliOlO_CLRN <= ((niOi0O50 XOR niOi0O49) AND wire_w_lg_rxpcsrst2w(0)); + wire_nliOlO_PRN <= (niOi0l52 XOR niOi0l51); + PROCESS (rcvd_clk, wire_nlli_PRN, wire_nlli_CLRN) + BEGIN + IF (wire_nlli_PRN = '0') THEN + n0li <= '1'; + ni0ii <= '1'; + nl0lOO <= '1'; + nliO <= '1'; + nll10i <= '1'; + nlll <= '1'; + ELSIF (wire_nlli_CLRN = '0') THEN + n0li <= '0'; + ni0ii <= '0'; + nl0lOO <= '0'; + nliO <= '0'; + nll10i <= '0'; + nlll <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + n0li <= nll10i; + ni0ii <= wire_n000O_o; + nl0lOO <= wire_nl0lii_dataout; + nliO <= wire_n1l_dataout; + nll10i <= wire_nliOOl_dataout; + nlll <= wire_n0O_dataout; + END IF; + if (now = 0 ns) then + n0li <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni0ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0lOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll10i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll <= '1' after 1 ps; + end if; + END PROCESS; + wire_nlli_CLRN <= (nl0i0l8 XOR nl0i0l7); + wire_nlli_PRN <= ((nl0i0i10 XOR nl0i0i9) AND wire_w_lg_rxpcsrst2w(0)); + wire_nlli_w_lg_nliO18w(0) <= NOT nliO; + wire_n000i_dataout <= wire_n0O0i_dataout AND ni00O; + wire_n001i_dataout <= wire_n0l0i_dataout AND ni01O; + wire_n001l_dataout <= wire_n0liO_dataout AND ni00i; + wire_n001O_dataout <= wire_n0lOl_dataout AND ni00l; + wire_n00i_dataout <= wire_n00O_o(0) WHEN nl000i = '1' ELSE n1Ol; + wire_n00ii_dataout <= niOO0l AND NOT(niOOiO); + wire_n00il_dataout <= wire_n0i0O_dataout AND NOT(niOOiO); + wire_n00iO_dataout <= wire_n0iii_dataout OR niOOiO; + wire_n00l_dataout <= wire_n00O_o(1) WHEN nl000i = '1' ELSE n1OO; + wire_n00li_dataout <= wire_n00lO_dataout AND NOT(niOOiO); + wire_n00ll_dataout <= wire_n00Oi_dataout OR niOOiO; + wire_n00lO_dataout <= niOOil AND NOT(niOO0i); + wire_n00Oi_dataout <= wire_w_lg_niOOil368w(0) AND NOT(niOO0i); + wire_n00Ol_dataout <= wire_n0i1O_dataout AND NOT(niOOiO); + wire_n00OO_dataout <= niOO0i AND NOT(niOOiO); + wire_n010i_dataout <= wire_n00OO_dataout AND ni1ii; + wire_n010l_dataout <= wire_n00OO_dataout AND ni1il; + wire_n010O_dataout <= wire_n00OO_dataout AND ni1iO; + wire_n011i_dataout <= wire_n00ii_dataout AND ni10i; + wire_n011l_dataout <= wire_n00ii_dataout AND ni10l; + wire_n011O_dataout <= wire_n00Ol_dataout AND ni01i; + wire_n01ii_dataout <= wire_n00OO_dataout AND ni1li; + wire_n01il_dataout <= wire_n00OO_dataout AND ni1ll; + wire_n01iO_dataout <= wire_n00OO_dataout AND ni1lO; + wire_n01l_dataout <= wire_n00i_dataout AND NOT(nl0i0O); + wire_n01li_dataout <= wire_n00OO_dataout AND ni1Oi; + wire_n01ll_dataout <= wire_n00OO_dataout AND ni1Ol; + wire_n01O_dataout <= wire_n00l_dataout AND NOT(nl0i0O); + wire_n01Ol_dataout <= wire_n0iil_dataout AND ni01l; + wire_n01OO_dataout <= wire_n0iiO_dataout AND ni01l; + wire_n0i0i_dataout <= wire_n0i0O_dataout AND NOT(niOO0i); + wire_n0i0l_dataout <= wire_n0iii_dataout AND NOT(niOO0i); + wire_n0i0O_dataout <= niOOil AND NOT(niOO0l); + wire_n0i1i_dataout <= wire_n0i0i_dataout AND NOT(niOOiO); + wire_n0i1l_dataout <= wire_n0i0l_dataout OR niOOiO; + wire_n0i1O_dataout <= niOO0l AND NOT(niOO0i); + wire_n0iii_dataout <= wire_w_lg_niOOil368w(0) AND NOT(niOO0l); + wire_n0iil_dataout <= wire_n0ilO_dataout AND NOT(niOOiO); + wire_n0iiO_dataout <= niOOii AND NOT(niOOiO); + wire_n0ili_dataout <= wire_n0iOi_dataout AND NOT(niOOiO); + wire_n0ill_dataout <= wire_n0iOl_dataout OR niOOiO; + wire_n0ilO_dataout <= niOO0O AND NOT(niOOii); + wire_n0iOi_dataout <= wire_n0iOO_dataout AND NOT(niOOii); + wire_n0iOl_dataout <= wire_n0l1i_dataout AND NOT(niOOii); + wire_n0iOO_dataout <= niOOil AND NOT(niOO0O); + wire_n0l0i_dataout <= niOOlO AND NOT(niOOiO); + wire_n0l0l_dataout <= wire_n0lii_dataout AND NOT(niOOiO); + wire_n0l0O_dataout <= wire_n0lil_dataout OR niOOiO; + wire_n0l1i_dataout <= wire_w_lg_niOOil368w(0) AND NOT(niOO0O); + wire_n0lii_dataout <= niOOil AND NOT(niOOlO); + wire_n0lil_dataout <= wire_w_lg_niOOil368w(0) AND NOT(niOOlO); + wire_n0liO_dataout <= nl11li AND NOT(niOOiO); + wire_n0lli_dataout <= wire_n0llO_dataout AND NOT(niOOiO); + wire_n0lll_dataout <= wire_n0lOi_dataout OR niOOiO; + wire_n0llO_dataout <= niOOil AND NOT(nl11li); + wire_n0lOi_dataout <= wire_w_lg_niOOil368w(0) AND NOT(nl11li); + wire_n0lOl_dataout <= nl11ll AND NOT(niOOiO); + wire_n0lOO_dataout <= wire_n0O1l_dataout AND NOT(niOOiO); + wire_n0O_dataout <= wire_nii_dataout OR NOT(nlO); + wire_n0O0i_dataout <= nl010l AND NOT(niOOiO); + wire_n0O0l_dataout <= wire_n0Oii_dataout AND NOT(niOOiO); + wire_n0O0O_dataout <= wire_n0Oil_dataout OR niOOiO; + wire_n0O1i_dataout <= wire_n0O1O_dataout OR niOOiO; + wire_n0O1l_dataout <= niOOil AND NOT(nl11ll); + wire_n0O1O_dataout <= wire_w_lg_niOOil368w(0) AND NOT(nl11ll); + wire_n0Oii_dataout <= niOOil AND NOT(nl010l); + wire_n0Oil_dataout <= wire_w_lg_niOOil368w(0) AND NOT(nl010l); + wire_n0OiO_dataout <= niOOil AND NOT(niOOiO); + wire_n0Oli_dataout <= wire_w_lg_niOOil368w(0) OR niOOiO; + wire_n1l_dataout <= wire_n1O_dataout WHEN reidleinferenable = '1' ELSE nlll; + wire_n1O_dataout <= nlll WHEN (wire_ni_w_lg_n0l16w(0) AND rgen1_sigdet_ena) = '1' ELSE n0li; + wire_n1OiO_dataout <= wire_n00ii_dataout AND n0OOi; + wire_n1Oli_dataout <= wire_n00ii_dataout AND n0OOl; + wire_n1Oll_dataout <= wire_n00ii_dataout AND n0OOO; + wire_n1OOi_dataout <= wire_n00ii_dataout AND ni11i; + wire_n1OOl_dataout <= wire_n00ii_dataout AND ni11l; + wire_n1OOO_dataout <= wire_n00ii_dataout AND ni11O; + wire_ni0l_dataout <= wire_nl0O_o(0) WHEN nl00OO = '1' ELSE wire_niOi_dataout; + wire_ni0O_dataout <= wire_nl0O_o(1) WHEN nl00OO = '1' ELSE wire_niOl_dataout; + wire_nii_dataout <= (NOT (wire_ni_w_lg_w_lg_nlO9w10w(0) OR (NOT (nl0iii6 XOR nl0iii5)))) WHEN nlll = '1' ELSE (wire_w_lg_w_lg_riei_eios_priority_dis4w5w(0) AND (nl0ili4 XOR nl0ili3)); + wire_niii_dataout <= wire_nl0O_o(2) WHEN nl00OO = '1' ELSE wire_niOO_dataout; + wire_niil_dataout <= wire_nl0O_o(3) WHEN nl00OO = '1' ELSE wire_nl1i_dataout; + wire_niiO_dataout <= wire_nl0O_o(4) WHEN nl00OO = '1' ELSE wire_nl1l_dataout; + wire_nili_dataout <= wire_nl0O_o(5) WHEN nl00OO = '1' ELSE wire_nl1O_dataout; + wire_nill_dataout <= wire_nl0O_o(6) WHEN nl00OO = '1' ELSE wire_nl0i_dataout; + wire_nilO_dataout <= wire_nl0O_o(7) WHEN nl00OO = '1' ELSE wire_nl0l_dataout; + wire_niOi_dataout <= n01i AND wire_n1l_dataout; + wire_niOl_dataout <= n0ll AND wire_n1l_dataout; + wire_niOO_dataout <= n0lO AND wire_n1l_dataout; + wire_nl0i_dataout <= ni1i AND wire_n1l_dataout; + wire_nl0l_dataout <= ni1O AND wire_n1l_dataout; + wire_nl0lii_dataout <= wire_nl0lil_o OR NOT(reidleinferenable); + wire_nl0lll_dataout <= syncstatus WHEN (inferred_rxvalid AND (reidle_com_detect(0) AND reidle_com_detect(1))) = '1' ELSE (inferred_rxvalid AND wire_nl0lOi_o); + wire_nl1i_dataout <= n0Oi AND wire_n1l_dataout; + wire_nl1l_dataout <= n0Ol AND wire_n1l_dataout; + wire_nl1O_dataout <= n0OO AND wire_n1l_dataout; + wire_nli0lO_dataout <= niOi1O AND NOT(niOi0i); + wire_nliiOO_dataout <= wire_nliO1i_o(0) AND NOT(niOi0i); + wire_nlil0i_dataout <= wire_nliO1i_o(4) AND NOT(niOi0i); + wire_nlil0l_dataout <= wire_nliO1i_o(5) AND NOT(niOi0i); + wire_nlil0O_dataout <= wire_nliO1i_o(6) AND NOT(niOi0i); + wire_nlil1i_dataout <= wire_nliO1i_o(1) AND NOT(niOi0i); + wire_nlil1l_dataout <= wire_nliO1i_o(2) AND NOT(niOi0i); + wire_nlil1O_dataout <= wire_nliO1i_o(3) AND NOT(niOi0i); + wire_nlilii_dataout <= wire_nliO1i_o(7) AND NOT(niOi0i); + wire_nlilil_dataout <= wire_nliO1i_o(8) AND NOT(niOi0i); + wire_nliliO_dataout <= wire_nliO1i_o(9) AND NOT(niOi0i); + wire_nlilli_dataout <= wire_nliO1i_o(10) AND NOT(niOi0i); + wire_nlilll_dataout <= wire_nliO1i_o(11) AND NOT(niOi0i); + wire_nlillO_dataout <= wire_nliO1i_o(12) AND NOT(niOi0i); + wire_nlilOi_dataout <= wire_nliO1i_o(13) AND NOT(niOi0i); + wire_nlilOl_dataout <= wire_nliO1i_o(14) AND NOT(niOi0i); + wire_nlilOO_dataout <= wire_nliO1i_o(15) AND NOT(niOi0i); + wire_nliOOl_dataout <= wire_ni_w_lg_nlil911w(0) WHEN nll10i = '1' ELSE ((eiosdetect_int AND (wire_w_lg_riei_eios_priority_dis4w(0) OR wire_ni_w_lg_nli1li907w(0))) OR nli0Oi); + wire_nO_dataout <= gen2ngen1 WHEN rindv_rx = '1' ELSE gen2ngen1_bundle; + wire_n00O_a <= ( n1OO & n1Ol); + wire_n00O_b <= ( "0" & "1"); + n00O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n00O_a, + b => wire_n00O_b, + cin => wire_gnd, + o => wire_n00O_o + ); + wire_nl0O_a <= ( ni1O & wire_nl00Oi16_w_lg_w_lg_q39w40w & n0OO & n0Ol & n0Oi & n0lO & n0ll & wire_nl00Ol14_w_lg_w_lg_q30w31w); + wire_nl0O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl0O_a, + b => wire_nl0O_b, + cin => wire_gnd, + o => wire_nl0O_o + ); + wire_nliO1i_a <= ( nliiOl & nliiOi & nliilO & nliill & nliili & nliiiO & nliiil & nliiii & nlii0O & nlii0l & nlii0i & nlii1O & nlii1l & nlii1i & nli0OO & nli0ll); + wire_nliO1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nliO1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 16, + width_b => 16, + width_o => 16 + ) + PORT MAP ( + a => wire_nliO1i_a, + b => wire_nliO1i_b, + cin => wire_gnd, + o => wire_nliO1i_o + ); + wire_nl0OOi_i <= ( nli1iO & nli1il); + nl0OOi : oper_decoder + GENERIC MAP ( + width_i => 2, + width_o => 4 + ) + PORT MAP ( + i => wire_nl0OOi_i, + o => wire_nl0OOi_o + ); + wire_nl0OOO_i <= ( n0l & nli1il); + nl0OOO : oper_decoder + GENERIC MAP ( + width_i => 2, + width_o => 4 + ) + PORT MAP ( + i => wire_nl0OOO_i, + o => wire_nl0OOO_o + ); + wire_nli10i_i <= ( n0l & nli1iO & nli1il); + nli10i : oper_decoder + GENERIC MAP ( + width_i => 3, + width_o => 8 + ) + PORT MAP ( + i => wire_nli10i_i, + o => wire_nli10i_o + ); + wire_n0il_a <= ( n1OO & wire_nl00ll20_w_lg_w_lg_q76w77w); + wire_n0il_b <= ( reidle_com_detect(1 DOWNTO 0)); + n0il : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n0il_a, + b => wire_n0il_b, + cin => wire_gnd, + o => wire_n0il_o + ); + wire_nl0lOi_a <= ( reidle_com_detect(1 DOWNTO 0)); + wire_nl0lOi_b <= ( kcount(1 DOWNTO 0)); + nl0lOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_nl0lOi_a, + b => wire_nl0lOi_b, + cin => wire_vcc, + o => wire_nl0lOi_o + ); + wire_nl0lil_data <= ( n1OlO & skposdetect & nl0l0O & wire_ni_w_lg_n0l1088w & "1" & "1" & "1" & "1"); + wire_nl0lil_sel <= ( nli1li & nli1iO & nli1il); + nl0lil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0lil_data, + o => wire_nl0lil_o, + sel => wire_nl0lil_sel + ); + wire_n000l_data <= ( wire_n0OiO_dataout & wire_n0O0l_dataout & wire_n0lOO_dataout & wire_n0lli_dataout & wire_n0l0l_dataout & wire_n0ili_dataout & wire_n0i1i_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00li_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n00il_dataout & wire_n0OiO_dataout); + wire_n000l_sel <= ( ni0ii & ni00O & ni00l & ni00i & ni01O & ni01l & ni01i & ni1OO & ni1Ol & ni1Oi & ni1lO & ni1ll & ni1li & ni1iO & ni1il & ni1ii & ni10O & ni10l & ni10i & ni11O & ni11l & ni11i & n0OOO & n0OOl & n0OOi & n0OlO & n1OlO); + n000l : oper_selector + GENERIC MAP ( + width_data => 27, + width_sel => 27 + ) + PORT MAP ( + data => wire_n000l_data, + o => wire_n000l_o, + sel => wire_n000l_sel + ); + wire_n000O_data <= ( wire_n0Oli_dataout & wire_n0O0O_dataout & wire_n0O1i_dataout & wire_n0lll_dataout & wire_n0l0O_dataout & wire_n0ill_dataout & wire_n0i1l_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00ll_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n00iO_dataout & wire_n0Oli_dataout); + wire_n000O_sel <= ( ni0ii & ni00O & ni00l & ni00i & ni01O & ni01l & ni01i & ni1OO & ni1Ol & ni1Oi & ni1lO & ni1ll & ni1li & ni1iO & ni1il & ni1ii & ni10O & ni10l & ni10i & ni11O & ni11l & ni11i & n0OOO & n0OOl & n0OOi & n0OlO & n1OlO); + n000O : oper_selector + GENERIC MAP ( + width_data => 27, + width_sel => 27 + ) + PORT MAP ( + data => wire_n000O_data, + o => wire_n000O_o, + sel => wire_n000O_sel + ); + wire_n01lO_data <= ( "0" & wire_n00OO_dataout); + wire_n01lO_sel <= ( niOO1O & wire_w_lg_niOO1O508w); + n01lO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n01lO_data, + o => wire_n01lO_o, + sel => wire_n01lO_sel + ); + wire_n1Oii_data <= ( "0" & wire_n00OO_dataout & wire_n00ii_dataout); + wire_n1Oii_sel <= ( niOO1l & ni10O & n0OlO); + n1Oii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1Oii_data, + o => wire_n1Oii_o, + sel => wire_n1Oii_sel + ); + + END RTL; --cycloneiv_hssi_rx_digi_eii_module +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + +--synthesis_resources = lut 14 mux21 120 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_pcs_channel_testbus IS + PORT + ( + chnl_test_bus_out : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); + rtest_bus_sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + test_bus_in0 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in1 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in10 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in11 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in13 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in14 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in2 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in3 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in4 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in5 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in6 : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + test_bus_in7 : IN STD_LOGIC_VECTOR (9 DOWNTO 0) + ); + END cycloneiv_hssi_rx_digi_pcs_channel_testbus; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_pcs_channel_testbus IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n000i1 : STD_LOGIC := '0'; + SIGNAL n000i2 : STD_LOGIC := '0'; + SIGNAL n001i3 : STD_LOGIC := '0'; + SIGNAL n001i4 : STD_LOGIC := '0'; + SIGNAL n010O13 : STD_LOGIC := '0'; + SIGNAL n010O14 : STD_LOGIC := '0'; + SIGNAL n01il11 : STD_LOGIC := '0'; + SIGNAL n01il12 : STD_LOGIC := '0'; + SIGNAL n01li10 : STD_LOGIC := '0'; + SIGNAL n01li9 : STD_LOGIC := '0'; + SIGNAL n01lO7 : STD_LOGIC := '0'; + SIGNAL n01lO8 : STD_LOGIC := '0'; + SIGNAL n01Ol5 : STD_LOGIC := '0'; + SIGNAL n01Ol6 : STD_LOGIC := '0'; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_ni_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nliii_dataout : STD_LOGIC; + SIGNAL wire_nliil_dataout : STD_LOGIC; + SIGNAL wire_nliiO_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlili_dataout : STD_LOGIC; + SIGNAL wire_nlill_dataout : STD_LOGIC; + SIGNAL wire_nlilO_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_w_lg_w_rtest_bus_sel_range132w146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_rtest_bus_sel_range134w135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n000O : STD_LOGIC; + SIGNAL n001O : STD_LOGIC; + SIGNAL n00ii : STD_LOGIC; + SIGNAL n00il : STD_LOGIC; + SIGNAL n00iO : STD_LOGIC; + SIGNAL n00li : STD_LOGIC; + SIGNAL n00ll : STD_LOGIC; + SIGNAL n00lO : STD_LOGIC; + SIGNAL n00Oi : STD_LOGIC; + SIGNAL n00Ol : STD_LOGIC; + SIGNAL n00OO : STD_LOGIC; + SIGNAL n0i1i : STD_LOGIC; + SIGNAL n0i1l : STD_LOGIC; + SIGNAL wire_w_rtest_bus_sel_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rtest_bus_sel_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_w_rtest_bus_sel_range132w146w(0) <= wire_w_rtest_bus_sel_range132w(0) AND wire_w_lg_w_rtest_bus_sel_range134w135w(0); + wire_w_lg_w_rtest_bus_sel_range134w135w(0) <= NOT wire_w_rtest_bus_sel_range134w(0); + chnl_test_bus_out <= ( wire_nlili_dataout & wire_nliiO_dataout & wire_nliil_dataout & wire_nliii_dataout & wire_nli0O_dataout & wire_nli0l_dataout & wire_nli0i_dataout & wire_nli1O_dataout & wire_nli1l_dataout & wire_nli1i_dataout); + n000O <= (((((NOT rtest_bus_sel(0)) AND wire_w_lg_w_rtest_bus_sel_range134w135w(0)) AND (NOT rtest_bus_sel(2))) AND (NOT rtest_bus_sel(3))) AND (n000i2 XOR n000i1)); + n00ii <= ((wire_w_lg_w_rtest_bus_sel_range132w146w(0) AND (NOT rtest_bus_sel(2))) AND (NOT rtest_bus_sel(3))); + n00il <= (((((NOT rtest_bus_sel(0)) AND rtest_bus_sel(1)) AND (NOT rtest_bus_sel(2))) AND (NOT rtest_bus_sel(3))) AND (n001i4 XOR n001i3)); + n00iO <= (((rtest_bus_sel(0) AND rtest_bus_sel(1)) AND (NOT rtest_bus_sel(2))) AND (NOT rtest_bus_sel(3))); + n00li <= (((((NOT rtest_bus_sel(0)) AND wire_w_lg_w_rtest_bus_sel_range134w135w(0)) AND rtest_bus_sel(2)) AND (NOT rtest_bus_sel(3))) AND (n01Ol6 XOR n01Ol5)); + n00ll <= ((wire_w_lg_w_rtest_bus_sel_range132w146w(0) AND rtest_bus_sel(2)) AND (NOT rtest_bus_sel(3))); + n00lO <= ((((NOT rtest_bus_sel(0)) AND rtest_bus_sel(1)) AND rtest_bus_sel(2)) AND (NOT rtest_bus_sel(3))); + n00Oi <= ((((rtest_bus_sel(0) AND rtest_bus_sel(1)) AND rtest_bus_sel(2)) AND (NOT rtest_bus_sel(3))) AND (n01lO8 XOR n01lO7)); + n00Ol <= (((((NOT rtest_bus_sel(0)) AND rtest_bus_sel(1)) AND (NOT rtest_bus_sel(2))) AND rtest_bus_sel(3)) AND (n01li10 XOR n01li9)); + n00OO <= ((((rtest_bus_sel(0) AND rtest_bus_sel(1)) AND (NOT rtest_bus_sel(2))) AND rtest_bus_sel(3)) AND (n01il12 XOR n01il11)); + n0i1i <= ((wire_w_lg_w_rtest_bus_sel_range132w146w(0) AND rtest_bus_sel(2)) AND rtest_bus_sel(3)); + n0i1l <= (((((NOT rtest_bus_sel(0)) AND rtest_bus_sel(1)) AND rtest_bus_sel(2)) AND rtest_bus_sel(3)) AND (n010O14 XOR n010O13)); + wire_w_rtest_bus_sel_range132w(0) <= rtest_bus_sel(0); + wire_w_rtest_bus_sel_range134w(0) <= rtest_bus_sel(1); + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n000i1 <= n000i2; + END IF; + if (now = 0 ns) then + n000i1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n000i2 <= n000i1; + END IF; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n001i3 <= n001i4; + END IF; + if (now = 0 ns) then + n001i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n001i4 <= n001i3; + END IF; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n010O13 <= n010O14; + END IF; + if (now = 0 ns) then + n010O13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n010O14 <= n010O13; + END IF; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01il11 <= n01il12; + END IF; + if (now = 0 ns) then + n01il11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01il12 <= n01il11; + END IF; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01li10 <= n01li9; + END IF; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01li9 <= n01li10; + END IF; + if (now = 0 ns) then + n01li9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01lO7 <= n01lO8; + END IF; + if (now = 0 ns) then + n01lO7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01lO8 <= n01lO7; + END IF; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01Ol5 <= n01Ol6; + END IF; + if (now = 0 ns) then + n01Ol5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (n001O) + BEGIN + IF (n001O = '1' AND n001O'event) THEN n01Ol6 <= n01Ol5; + END IF; + END PROCESS; + wire_n00i_dataout <= test_bus_in6(3) WHEN n00lO = '1' ELSE wire_n0Ol_dataout; + wire_n00l_dataout <= test_bus_in6(4) WHEN n00lO = '1' ELSE wire_n0OO_dataout; + wire_n00O_dataout <= test_bus_in6(5) WHEN n00lO = '1' ELSE wire_ni1i_dataout; + wire_n01i_dataout <= test_bus_in6(0) WHEN n00lO = '1' ELSE wire_n0ll_dataout; + wire_n01l_dataout <= test_bus_in6(1) WHEN n00lO = '1' ELSE wire_n0lO_dataout; + wire_n01O_dataout <= test_bus_in6(2) WHEN n00lO = '1' ELSE wire_n0Oi_dataout; + wire_n0i_dataout <= test_bus_in13(8) WHEN n0i1i = '1' ELSE wire_nl_dataout; + wire_n0ii_dataout <= test_bus_in6(6) WHEN n00lO = '1' ELSE wire_ni1l_dataout; + wire_n0il_dataout <= test_bus_in6(7) WHEN n00lO = '1' ELSE wire_ni1O_dataout; + wire_n0iO_dataout <= test_bus_in6(8) WHEN n00lO = '1' ELSE wire_ni0i_dataout; + wire_n0l_dataout <= test_bus_in13(9) WHEN n0i1i = '1' ELSE wire_nO_dataout; + wire_n0li_dataout <= test_bus_in6(9) WHEN n00lO = '1' ELSE wire_ni0l_dataout; + wire_n0ll_dataout <= test_bus_in7(0) WHEN n00Oi = '1' ELSE wire_ni0O_dataout; + wire_n0lO_dataout <= test_bus_in7(1) WHEN n00Oi = '1' ELSE wire_niii_dataout; + wire_n0O_dataout <= test_bus_in14(0) WHEN n0i1l = '1' ELSE test_bus_in0(0); + wire_n0Oi_dataout <= test_bus_in7(2) WHEN n00Oi = '1' ELSE wire_niil_dataout; + wire_n0Ol_dataout <= test_bus_in7(3) WHEN n00Oi = '1' ELSE wire_niiO_dataout; + wire_n0OO_dataout <= test_bus_in7(4) WHEN n00Oi = '1' ELSE wire_nili_dataout; + wire_n10i_dataout <= test_bus_in4(8) WHEN n00li = '1' ELSE wire_n1Ol_dataout; + wire_n10l_dataout <= test_bus_in4(9) WHEN n00li = '1' ELSE wire_n1OO_dataout; + wire_n10O_dataout <= test_bus_in5(0) WHEN n00ll = '1' ELSE wire_n01i_dataout; + wire_n11i_dataout <= test_bus_in4(5) WHEN n00li = '1' ELSE wire_n1ll_dataout; + wire_n11l_dataout <= test_bus_in4(6) WHEN n00li = '1' ELSE wire_n1lO_dataout; + wire_n11O_dataout <= test_bus_in4(7) WHEN n00li = '1' ELSE wire_n1Oi_dataout; + wire_n1i_dataout <= test_bus_in13(5) WHEN n0i1i = '1' ELSE wire_nll_dataout; + wire_n1ii_dataout <= test_bus_in5(1) WHEN n00ll = '1' ELSE wire_n01l_dataout; + wire_n1il_dataout <= test_bus_in5(2) WHEN n00ll = '1' ELSE wire_n01O_dataout; + wire_n1iO_dataout <= test_bus_in5(3) WHEN n00ll = '1' ELSE wire_n00i_dataout; + wire_n1l_dataout <= test_bus_in13(6) WHEN n0i1i = '1' ELSE wire_nlO_dataout; + wire_n1li_dataout <= test_bus_in5(4) WHEN n00ll = '1' ELSE wire_n00l_dataout; + wire_n1ll_dataout <= test_bus_in5(5) WHEN n00ll = '1' ELSE wire_n00O_dataout; + wire_n1lO_dataout <= test_bus_in5(6) WHEN n00ll = '1' ELSE wire_n0ii_dataout; + wire_n1O_dataout <= test_bus_in13(7) WHEN n0i1i = '1' ELSE wire_ni_dataout; + wire_n1Oi_dataout <= test_bus_in5(7) WHEN n00ll = '1' ELSE wire_n0il_dataout; + wire_n1Ol_dataout <= test_bus_in5(8) WHEN n00ll = '1' ELSE wire_n0iO_dataout; + wire_n1OO_dataout <= test_bus_in5(9) WHEN n00ll = '1' ELSE wire_n0li_dataout; + wire_ni_dataout <= test_bus_in14(7) WHEN n0i1l = '1' ELSE test_bus_in0(7); + wire_ni0i_dataout <= test_bus_in7(8) WHEN n00Oi = '1' ELSE wire_niOl_dataout; + wire_ni0l_dataout <= test_bus_in7(9) WHEN n00Oi = '1' ELSE wire_niOO_dataout; + wire_ni0O_dataout <= test_bus_in10(0) WHEN n00Ol = '1' ELSE wire_nl1i_dataout; + wire_ni1i_dataout <= test_bus_in7(5) WHEN n00Oi = '1' ELSE wire_nill_dataout; + wire_ni1l_dataout <= test_bus_in7(6) WHEN n00Oi = '1' ELSE wire_nilO_dataout; + wire_ni1O_dataout <= test_bus_in7(7) WHEN n00Oi = '1' ELSE wire_niOi_dataout; + wire_nii_dataout <= test_bus_in14(1) WHEN n0i1l = '1' ELSE test_bus_in0(1); + wire_niii_dataout <= test_bus_in10(1) WHEN n00Ol = '1' ELSE wire_nl1l_dataout; + wire_niil_dataout <= test_bus_in10(2) WHEN n00Ol = '1' ELSE wire_nl1O_dataout; + wire_niiO_dataout <= test_bus_in10(3) WHEN n00Ol = '1' ELSE wire_nl0i_dataout; + wire_nil_dataout <= test_bus_in14(2) WHEN n0i1l = '1' ELSE test_bus_in0(2); + wire_nili_dataout <= test_bus_in10(4) WHEN n00Ol = '1' ELSE wire_nl0l_dataout; + wire_nill_dataout <= test_bus_in10(5) WHEN n00Ol = '1' ELSE wire_nl0O_dataout; + wire_nilO_dataout <= test_bus_in10(6) WHEN n00Ol = '1' ELSE wire_nlii_dataout; + wire_niO_dataout <= test_bus_in14(3) WHEN n0i1l = '1' ELSE test_bus_in0(3); + wire_niOi_dataout <= test_bus_in10(7) WHEN n00Ol = '1' ELSE wire_nlil_dataout; + wire_niOl_dataout <= test_bus_in10(8) WHEN n00Ol = '1' ELSE wire_nliO_dataout; + wire_niOO_dataout <= test_bus_in10(9) WHEN n00Ol = '1' ELSE wire_nlli_dataout; + wire_nl_dataout <= test_bus_in14(8) WHEN n0i1l = '1' ELSE test_bus_in0(8); + wire_nl0i_dataout <= test_bus_in11(3) WHEN n00OO = '1' ELSE wire_nlOl_dataout; + wire_nl0l_dataout <= test_bus_in11(4) WHEN n00OO = '1' ELSE wire_nlOO_dataout; + wire_nl0O_dataout <= test_bus_in11(5) WHEN n00OO = '1' ELSE wire_n1i_dataout; + wire_nl1i_dataout <= test_bus_in11(0) WHEN n00OO = '1' ELSE wire_nlll_dataout; + wire_nl1l_dataout <= test_bus_in11(1) WHEN n00OO = '1' ELSE wire_nllO_dataout; + wire_nl1O_dataout <= test_bus_in11(2) WHEN n00OO = '1' ELSE wire_nlOi_dataout; + wire_nli_dataout <= test_bus_in14(4) WHEN n0i1l = '1' ELSE test_bus_in0(4); + wire_nli0i_dataout <= test_bus_in0(3) WHEN n000O = '1' ELSE wire_nliOl_dataout; + wire_nli0l_dataout <= test_bus_in0(4) WHEN n000O = '1' ELSE wire_nliOO_dataout; + wire_nli0O_dataout <= test_bus_in0(5) WHEN n000O = '1' ELSE wire_nll1i_dataout; + wire_nli1i_dataout <= test_bus_in0(0) WHEN n000O = '1' ELSE wire_nlill_dataout; + wire_nli1l_dataout <= test_bus_in0(1) WHEN n000O = '1' ELSE wire_nlilO_dataout; + wire_nli1O_dataout <= test_bus_in0(2) WHEN n000O = '1' ELSE wire_nliOi_dataout; + wire_nlii_dataout <= test_bus_in11(6) WHEN n00OO = '1' ELSE wire_n1l_dataout; + wire_nliii_dataout <= test_bus_in0(6) WHEN n000O = '1' ELSE wire_nll1l_dataout; + wire_nliil_dataout <= test_bus_in0(7) WHEN n000O = '1' ELSE wire_nll1O_dataout; + wire_nliiO_dataout <= test_bus_in0(8) WHEN n000O = '1' ELSE wire_nll0i_dataout; + wire_nlil_dataout <= test_bus_in11(7) WHEN n00OO = '1' ELSE wire_n1O_dataout; + wire_nlili_dataout <= test_bus_in0(9) WHEN n000O = '1' ELSE wire_nll0l_dataout; + wire_nlill_dataout <= test_bus_in1(0) WHEN n00ii = '1' ELSE wire_nll0O_dataout; + wire_nlilO_dataout <= test_bus_in1(1) WHEN n00ii = '1' ELSE wire_nllii_dataout; + wire_nliO_dataout <= test_bus_in11(8) WHEN n00OO = '1' ELSE wire_n0i_dataout; + wire_nliOi_dataout <= test_bus_in1(2) WHEN n00ii = '1' ELSE wire_nllil_dataout; + wire_nliOl_dataout <= test_bus_in1(3) WHEN n00ii = '1' ELSE wire_nlliO_dataout; + wire_nliOO_dataout <= test_bus_in1(4) WHEN n00ii = '1' ELSE wire_nllli_dataout; + wire_nll_dataout <= test_bus_in14(5) WHEN n0i1l = '1' ELSE test_bus_in0(5); + wire_nll0i_dataout <= test_bus_in1(8) WHEN n00ii = '1' ELSE wire_nllOl_dataout; + wire_nll0l_dataout <= test_bus_in1(9) WHEN n00ii = '1' ELSE wire_nllOO_dataout; + wire_nll0O_dataout <= test_bus_in2(0) WHEN n00il = '1' ELSE wire_nlO1i_dataout; + wire_nll1i_dataout <= test_bus_in1(5) WHEN n00ii = '1' ELSE wire_nllll_dataout; + wire_nll1l_dataout <= test_bus_in1(6) WHEN n00ii = '1' ELSE wire_nlllO_dataout; + wire_nll1O_dataout <= test_bus_in1(7) WHEN n00ii = '1' ELSE wire_nllOi_dataout; + wire_nlli_dataout <= test_bus_in11(9) WHEN n00OO = '1' ELSE wire_n0l_dataout; + wire_nllii_dataout <= test_bus_in2(1) WHEN n00il = '1' ELSE wire_nlO1l_dataout; + wire_nllil_dataout <= test_bus_in2(2) WHEN n00il = '1' ELSE wire_nlO1O_dataout; + wire_nlliO_dataout <= test_bus_in2(3) WHEN n00il = '1' ELSE wire_nlO0i_dataout; + wire_nlll_dataout <= test_bus_in13(0) WHEN n0i1i = '1' ELSE wire_n0O_dataout; + wire_nllli_dataout <= test_bus_in2(4) WHEN n00il = '1' ELSE wire_nlO0l_dataout; + wire_nllll_dataout <= test_bus_in2(5) WHEN n00il = '1' ELSE wire_nlO0O_dataout; + wire_nlllO_dataout <= test_bus_in2(6) WHEN n00il = '1' ELSE wire_nlOii_dataout; + wire_nllO_dataout <= test_bus_in13(1) WHEN n0i1i = '1' ELSE wire_nii_dataout; + wire_nllOi_dataout <= test_bus_in2(7) WHEN n00il = '1' ELSE wire_nlOil_dataout; + wire_nllOl_dataout <= test_bus_in2(8) WHEN n00il = '1' ELSE wire_nlOiO_dataout; + wire_nllOO_dataout <= test_bus_in2(9) WHEN n00il = '1' ELSE wire_nlOli_dataout; + wire_nlO_dataout <= test_bus_in14(6) WHEN n0i1l = '1' ELSE test_bus_in0(6); + wire_nlO0i_dataout <= test_bus_in3(3) WHEN n00iO = '1' ELSE wire_nlOOl_dataout; + wire_nlO0l_dataout <= test_bus_in3(4) WHEN n00iO = '1' ELSE wire_nlOOO_dataout; + wire_nlO0O_dataout <= test_bus_in3(5) WHEN n00iO = '1' ELSE wire_n11i_dataout; + wire_nlO1i_dataout <= test_bus_in3(0) WHEN n00iO = '1' ELSE wire_nlOll_dataout; + wire_nlO1l_dataout <= test_bus_in3(1) WHEN n00iO = '1' ELSE wire_nlOlO_dataout; + wire_nlO1O_dataout <= test_bus_in3(2) WHEN n00iO = '1' ELSE wire_nlOOi_dataout; + wire_nlOi_dataout <= test_bus_in13(2) WHEN n0i1i = '1' ELSE wire_nil_dataout; + wire_nlOii_dataout <= test_bus_in3(6) WHEN n00iO = '1' ELSE wire_n11l_dataout; + wire_nlOil_dataout <= test_bus_in3(7) WHEN n00iO = '1' ELSE wire_n11O_dataout; + wire_nlOiO_dataout <= test_bus_in3(8) WHEN n00iO = '1' ELSE wire_n10i_dataout; + wire_nlOl_dataout <= test_bus_in13(3) WHEN n0i1i = '1' ELSE wire_niO_dataout; + wire_nlOli_dataout <= test_bus_in3(9) WHEN n00iO = '1' ELSE wire_n10l_dataout; + wire_nlOll_dataout <= test_bus_in4(0) WHEN n00li = '1' ELSE wire_n10O_dataout; + wire_nlOlO_dataout <= test_bus_in4(1) WHEN n00li = '1' ELSE wire_n1ii_dataout; + wire_nlOO_dataout <= test_bus_in13(4) WHEN n0i1i = '1' ELSE wire_nli_dataout; + wire_nlOOi_dataout <= test_bus_in4(2) WHEN n00li = '1' ELSE wire_n1il_dataout; + wire_nlOOl_dataout <= test_bus_in4(3) WHEN n00li = '1' ELSE wire_n1iO_dataout; + wire_nlOOO_dataout <= test_bus_in4(4) WHEN n00li = '1' ELSE wire_n1li_dataout; + wire_nO_dataout <= test_bus_in14(9) WHEN n0i1l = '1' ELSE test_bus_in0(9); + + END RTL; --cycloneiv_hssi_rx_digi_pcs_channel_testbus +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + +--synthesis_resources = lut 18 mux21 19 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_iq_pipe_rx IS + PORT + ( + clk_2_b_raw : IN STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_out_pipe : OUT STD_LOGIC; + reset_pc_ptrs_in_centrl : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_down : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_up : IN STD_LOGIC; + reset_pc_ptrs_out_pipe : OUT STD_LOGIC; + rfreerun_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rpipeline_bypass_rx : IN STD_LOGIC; + rx_div2_sync_in_centrl : IN STD_LOGIC; + rx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + rx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + rx_div2_sync_out_pipe : OUT STD_LOGIC; + rx_rd_clk_raw : IN STD_LOGIC; + rx_we_in_centrl : IN STD_LOGIC; + rx_we_in_pipe_quad_down : IN STD_LOGIC; + rx_we_in_pipe_quad_up : IN STD_LOGIC; + rx_we_out_pipe : OUT STD_LOGIC; + rx_wr_clk_raw : IN STD_LOGIC; + rxrst : IN STD_LOGIC; + soft_reset_rclk1 : IN STD_LOGIC; + soft_reset_wclk1 : IN STD_LOGIC; + speed_change_in_centrl : IN STD_LOGIC; + speed_change_in_pipe_quad_down : IN STD_LOGIC; + speed_change_in_pipe_quad_up : IN STD_LOGIC; + speed_change_out_pipe : OUT STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_out_pipe : OUT STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_iq_pipe_rx; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_iq_pipe_rx IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n10i10 : STD_LOGIC := '0'; + SIGNAL n10i9 : STD_LOGIC := '0'; + SIGNAL n10l7 : STD_LOGIC := '0'; + SIGNAL n10l8 : STD_LOGIC := '0'; + SIGNAL n10O5 : STD_LOGIC := '0'; + SIGNAL n10O6 : STD_LOGIC := '0'; + SIGNAL n11O11 : STD_LOGIC := '0'; + SIGNAL n11O12 : STD_LOGIC := '0'; + SIGNAL n1il3 : STD_LOGIC := '0'; + SIGNAL n1il4 : STD_LOGIC := '0'; + SIGNAL n1ll1 : STD_LOGIC := '0'; + SIGNAL n1ll2 : STD_LOGIC := '0'; + SIGNAL nlii : STD_LOGIC := '0'; + SIGNAL nO : STD_LOGIC := '0'; + SIGNAL wire_nl_CLRN : STD_LOGIC; + SIGNAL nliO : STD_LOGIC := '0'; + SIGNAL wire_nlil_CLRN : STD_LOGIC; + SIGNAL wire_nlil_PRN : STD_LOGIC; + SIGNAL nlll : STD_LOGIC := '0'; + SIGNAL wire_nlli_PRN : STD_LOGIC; + SIGNAL nlOi : STD_LOGIC := '0'; + SIGNAL wire_nllO_CLRN : STD_LOGIC; + SIGNAL ni : STD_LOGIC := '0'; + SIGNAL wire_nlO_CLRN : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl_w_lg_dataout7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_w_lg_rmaster_rx5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rxrst2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset_rclk111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset_wclk18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1iO : STD_LOGIC; + BEGIN + + wire_w_lg_rmaster_rx5w(0) <= NOT rmaster_rx; + wire_w_lg_rxrst2w(0) <= NOT rxrst; + wire_w_lg_soft_reset_rclk111w(0) <= NOT soft_reset_rclk1; + wire_w_lg_soft_reset_wclk18w(0) <= NOT soft_reset_wclk1; + n1iO <= '1'; + rd_enable_out_pipe <= wire_nl1O_dataout; + reset_pc_ptrs_out_pipe <= wire_nl1l_dataout; + rx_div2_sync_out_pipe <= wire_nl0O_dataout; + rx_we_out_pipe <= wire_nl0l_dataout; + speed_change_out_pipe <= wire_nl1i_dataout; + wr_enable_out_pipe <= wire_nl0i_dataout; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n10i10 <= n10i9; + END IF; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n10i9 <= n10i10; + END IF; + if (now = 0 ns) then + n10i9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n10l7 <= n10l8; + END IF; + if (now = 0 ns) then + n10l7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n10l8 <= n10l7; + END IF; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n10O5 <= n10O6; + END IF; + if (now = 0 ns) then + n10O5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n10O6 <= n10O5; + END IF; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n11O11 <= n11O12; + END IF; + if (now = 0 ns) then + n11O11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n11O12 <= n11O11; + END IF; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n1il3 <= n1il4; + END IF; + if (now = 0 ns) then + n1il3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n1il4 <= n1il3; + END IF; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n1ll1 <= n1ll2; + END IF; + if (now = 0 ns) then + n1ll1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2_b_raw) + BEGIN + IF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN n1ll2 <= n1ll1; + END IF; + END PROCESS; + PROCESS (clk_2_b_raw, wire_nl_CLRN) + BEGIN + IF (wire_nl_CLRN = '0') THEN + nlii <= '0'; + nO <= '0'; + ELSIF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN + nlii <= wire_n1l_dataout; + nO <= wire_nlOO_dataout; + END IF; + END PROCESS; + wire_nl_CLRN <= ((n1ll2 XOR n1ll1) AND wire_w_lg_rxrst2w(0)); + PROCESS (rx_rd_clk_raw, wire_nlil_PRN, wire_nlil_CLRN) + BEGIN + IF (wire_nlil_PRN = '0') THEN + nliO <= '1'; + ELSIF (wire_nlil_CLRN = '0') THEN + nliO <= '0'; + ELSIF (rx_rd_clk_raw = '1' AND rx_rd_clk_raw'event) THEN + nliO <= wire_n0i_dataout; + END IF; + END PROCESS; + wire_nlil_CLRN <= ((n10i10 XOR n10i9) AND wire_w_lg_soft_reset_rclk111w(0)); + wire_nlil_PRN <= (n11O12 XOR n11O11); + PROCESS (rx_wr_clk_raw, wire_nlli_PRN, soft_reset_wclk1) + BEGIN + IF (wire_nlli_PRN = '0') THEN + nlll <= '1'; + ELSIF (soft_reset_wclk1 = '1') THEN + nlll <= '0'; + ELSIF (rx_wr_clk_raw = '1' AND rx_wr_clk_raw'event) THEN + nlll <= wire_n0O_dataout; + END IF; + END PROCESS; + wire_nlli_PRN <= (n10l8 XOR n10l7); + PROCESS (clk_2_b_raw, wire_nlOl_dataout, wire_nllO_CLRN) + BEGIN + IF (wire_nlOl_dataout = '1') THEN + nlOi <= '1'; + ELSIF (wire_nllO_CLRN = '0') THEN + nlOi <= '0'; + ELSIF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN + nlOi <= wire_nli_dataout; + END IF; + if (now = 0 ns) then + nlOi <= '1' after 1 ps; + end if; + END PROCESS; + wire_nllO_CLRN <= (n10O6 XOR n10O5); + PROCESS (clk_2_b_raw, rxrst, wire_nlO_CLRN) + BEGIN + IF (rxrst = '1') THEN + ni <= '1'; + ELSIF (wire_nlO_CLRN = '0') THEN + ni <= '0'; + ELSIF (clk_2_b_raw = '1' AND clk_2_b_raw'event) THEN + ni <= wire_nil_dataout; + END IF; + if (now = 0 ns) then + ni <= '1' after 1 ps; + end if; + END PROCESS; + wire_nlO_CLRN <= (n1il4 XOR n1il3); + wire_n0i_dataout <= wire_n0l_dataout WHEN wire_w_lg_rmaster_rx5w(0) = '1' ELSE rd_enable_in_centrl; + wire_n0l_dataout <= rd_enable_in_pipe_quad_up WHEN rmaster_up_rx = '1' ELSE rd_enable_in_pipe_quad_down; + wire_n0O_dataout <= wire_nii_dataout WHEN wire_w_lg_rmaster_rx5w(0) = '1' ELSE wr_enable_in_centrl; + wire_n1i_dataout <= speed_change_in_pipe_quad_up WHEN rmaster_up_rx = '1' ELSE speed_change_in_pipe_quad_down; + wire_n1l_dataout <= wire_n1O_dataout WHEN wire_w_lg_rmaster_rx5w(0) = '1' ELSE reset_pc_ptrs_in_centrl; + wire_n1O_dataout <= reset_pc_ptrs_in_pipe_quad_up WHEN rmaster_up_rx = '1' ELSE reset_pc_ptrs_in_pipe_quad_down; + wire_nii_dataout <= wr_enable_in_pipe_quad_up WHEN rmaster_up_rx = '1' ELSE wr_enable_in_pipe_quad_down; + wire_nil_dataout <= wire_niO_dataout WHEN wire_w_lg_rmaster_rx5w(0) = '1' ELSE rx_we_in_centrl; + wire_niO_dataout <= rx_we_in_pipe_quad_up WHEN rmaster_up_rx = '1' ELSE rx_we_in_pipe_quad_down; + wire_nl0i_dataout <= wire_n0O_dataout WHEN rpipeline_bypass_rx = '1' ELSE nlll; + wire_nl0l_dataout <= wire_nil_dataout WHEN rpipeline_bypass_rx = '1' ELSE ni; + wire_nl0O_dataout <= wire_nli_dataout WHEN rpipeline_bypass_rx = '1' ELSE nlOi; + wire_nl1i_dataout <= wire_nlOO_dataout WHEN rpipeline_bypass_rx = '1' ELSE nO; + wire_nl1l_dataout <= wire_n1l_dataout WHEN rpipeline_bypass_rx = '1' ELSE nlii; + wire_nl1O_dataout <= wire_n0i_dataout WHEN rpipeline_bypass_rx = '1' ELSE nliO; + wire_nli_dataout <= wire_nll_dataout WHEN wire_w_lg_rmaster_rx5w(0) = '1' ELSE rx_div2_sync_in_centrl; + wire_nll_dataout <= rx_div2_sync_in_pipe_quad_up WHEN rmaster_up_rx = '1' ELSE rx_div2_sync_in_pipe_quad_down; + wire_nlOl_dataout <= rxrst AND NOT(rfreerun_rx); + wire_nlOl_w_lg_dataout7w(0) <= NOT wire_nlOl_dataout; + wire_nlOO_dataout <= wire_n1i_dataout WHEN wire_w_lg_rmaster_rx5w(0) = '1' ELSE speed_change_in_centrl; + + END RTL; --cycloneiv_hssi_rx_digi_iq_pipe_rx +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 122 mux21 276 oper_add 1 oper_decoder 1 oper_less_than 1 oper_mux 36 oper_selector 10 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_prbs_ver IS + PORT + ( + cid_en : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + encdet_prbs : OUT STD_LOGIC; + prbs_done : OUT STD_LOGIC; + prbs_err : OUT STD_LOGIC; + prbs_err_lt : OUT STD_LOGIC; + rall_one_dect_only : IN STD_LOGIC; + rcid_len : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rcid_pattern : IN STD_LOGIC; + rcvd_clk : IN STD_LOGIC; + rpma_doublewidth_rx : IN STD_LOGIC; + rpmadwidth_rx : IN STD_LOGIC; + rprbs_clr_rslt_rx : IN STD_LOGIC; + rprbs_en_rx : IN STD_LOGIC; + rprbs_sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + scan_mode : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + sync_status : IN STD_LOGIC; + verify_on : OUT STD_LOGIC + ); + END cycloneiv_hssi_rx_digi_prbs_ver; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_prbs_ver IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nillOi49 : STD_LOGIC := '0'; + SIGNAL nillOi50 : STD_LOGIC := '0'; + SIGNAL wire_nillOi50_w_lg_w_lg_q242w243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nillOi50_w_lg_q242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nillOl47 : STD_LOGIC := '0'; + SIGNAL nillOl48 : STD_LOGIC := '0'; + SIGNAL wire_nillOl48_w_lg_w_lg_q239w240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nillOl48_w_lg_q239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nillOO45 : STD_LOGIC := '0'; + SIGNAL nillOO46 : STD_LOGIC := '0'; + SIGNAL wire_nillOO46_w_lg_w_lg_q235w236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nillOO46_w_lg_q235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nilO1i43 : STD_LOGIC := '0'; + SIGNAL nilO1i44 : STD_LOGIC := '0'; + SIGNAL wire_nilO1i44_w_lg_w_lg_q229w230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO1i44_w_lg_q229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nilO1O41 : STD_LOGIC := '0'; + SIGNAL nilO1O42 : STD_LOGIC := '0'; + SIGNAL wire_nilO1O42_w_lg_w_lg_q221w223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO1O42_w_lg_q221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nilOiO39 : STD_LOGIC := '0'; + SIGNAL nilOiO40 : STD_LOGIC := '0'; + SIGNAL wire_nilOiO40_w_lg_w_lg_q187w189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiO40_w_lg_q187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO00i21 : STD_LOGIC := '0'; + SIGNAL niO00i22 : STD_LOGIC := '0'; + SIGNAL wire_niO00i22_w_lg_q110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO01l23 : STD_LOGIC := '0'; + SIGNAL niO01l24 : STD_LOGIC := '0'; + SIGNAL niO0iO19 : STD_LOGIC := '0'; + SIGNAL niO0iO20 : STD_LOGIC := '0'; + SIGNAL niO0ll17 : STD_LOGIC := '0'; + SIGNAL niO0ll18 : STD_LOGIC := '0'; + SIGNAL wire_niO0ll18_w_lg_w_lg_q97w98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO0ll18_w_lg_q97w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO0lO15 : STD_LOGIC := '0'; + SIGNAL niO0lO16 : STD_LOGIC := '0'; + SIGNAL wire_niO0lO16_w_lg_w_lg_q91w92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO0lO16_w_lg_q91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO0Oi13 : STD_LOGIC := '0'; + SIGNAL niO0Oi14 : STD_LOGIC := '0'; + SIGNAL niO0OO11 : STD_LOGIC := '0'; + SIGNAL niO0OO12 : STD_LOGIC := '0'; + SIGNAL wire_niO0OO12_w_lg_w_lg_q32w33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO0OO12_w_lg_q32w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO10i35 : STD_LOGIC := '0'; + SIGNAL niO10i36 : STD_LOGIC := '0'; + SIGNAL niO10l33 : STD_LOGIC := '0'; + SIGNAL niO10l34 : STD_LOGIC := '0'; + SIGNAL niO11i37 : STD_LOGIC := '0'; + SIGNAL niO11i38 : STD_LOGIC := '0'; + SIGNAL niO1li31 : STD_LOGIC := '0'; + SIGNAL niO1li32 : STD_LOGIC := '0'; + SIGNAL wire_niO1li32_w_lg_w_lg_q159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1li32_w_lg_q159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO1ll29 : STD_LOGIC := '0'; + SIGNAL niO1ll30 : STD_LOGIC := '0'; + SIGNAL wire_niO1ll30_w_lg_w_lg_q142w143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1ll30_w_lg_q142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO1lO27 : STD_LOGIC := '0'; + SIGNAL niO1lO28 : STD_LOGIC := '0'; + SIGNAL wire_niO1lO28_w_lg_w_lg_q138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1lO28_w_lg_q138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO1Ol25 : STD_LOGIC := '0'; + SIGNAL niO1Ol26 : STD_LOGIC := '0'; + SIGNAL wire_niO1Ol26_w_lg_w_lg_q125w126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1Ol26_w_lg_q125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi0l3 : STD_LOGIC := '0'; + SIGNAL niOi0l4 : STD_LOGIC := '0'; + SIGNAL niOi1i10 : STD_LOGIC := '0'; + SIGNAL wire_niOi1i10_w_lg_w_lg_q28w29w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOi1i10_w_lg_q28w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi1i9 : STD_LOGIC := '0'; + SIGNAL niOi1l7 : STD_LOGIC := '0'; + SIGNAL niOi1l8 : STD_LOGIC := '0'; + SIGNAL wire_niOi1l8_w_lg_w_lg_q25w26w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOi1l8_w_lg_q25w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi1O5 : STD_LOGIC := '0'; + SIGNAL niOi1O6 : STD_LOGIC := '0'; + SIGNAL wire_niOi1O6_w_lg_w_lg_q20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOi1O6_w_lg_q20w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOiii1 : STD_LOGIC := '0'; + SIGNAL niOiii2 : STD_LOGIC := '0'; + SIGNAL n0i : STD_LOGIC := '0'; + SIGNAL n0l : STD_LOGIC := '0'; + SIGNAL n0O : STD_LOGIC := '0'; + SIGNAL nii : STD_LOGIC := '0'; + SIGNAL nil : STD_LOGIC := '0'; + SIGNAL niO : STD_LOGIC := '0'; + SIGNAL nl : STD_LOGIC := '0'; + SIGNAL nl0i : STD_LOGIC := '0'; + SIGNAL nl0l : STD_LOGIC := '0'; + SIGNAL nl0O : STD_LOGIC := '0'; + SIGNAL nl1i : STD_LOGIC := '0'; + SIGNAL nl1l : STD_LOGIC := '0'; + SIGNAL nl1O : STD_LOGIC := '0'; + SIGNAL nli : STD_LOGIC := '0'; + SIGNAL nlii : STD_LOGIC := '0'; + SIGNAL nlil : STD_LOGIC := '0'; + SIGNAL nliO : STD_LOGIC := '0'; + SIGNAL nll : STD_LOGIC := '0'; + SIGNAL nlO : STD_LOGIC := '0'; + SIGNAL wire_ni_CLRN : STD_LOGIC; + SIGNAL wire_ni_w_lg_w_lg_w_lg_nlO108w111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_w_lg_nlO108w111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlO108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl0i2979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl0l2977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl0O2975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl1l2983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nl1O2981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlii2973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nlil2972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_w_lg_nll2606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi : STD_LOGIC := '0'; + SIGNAL nlliO : STD_LOGIC := '0'; + SIGNAL wire_nilO_PRN : STD_LOGIC; + SIGNAL niOO : STD_LOGIC := '0'; + SIGNAL nli0lO : STD_LOGIC := '0'; + SIGNAL nlii0O : STD_LOGIC := '0'; + SIGNAL nliOl : STD_LOGIC := '0'; + SIGNAL nll0il : STD_LOGIC := '0'; + SIGNAL nll0iO : STD_LOGIC := '0'; + SIGNAL nll0li : STD_LOGIC := '0'; + SIGNAL nll0ll : STD_LOGIC := '0'; + SIGNAL nll0lO : STD_LOGIC := '0'; + SIGNAL nll0Oi : STD_LOGIC := '0'; + SIGNAL nll0Ol : STD_LOGIC := '0'; + SIGNAL nll0OO : STD_LOGIC := '0'; + SIGNAL nlli0i : STD_LOGIC := '0'; + SIGNAL nlli0l : STD_LOGIC := '0'; + SIGNAL nlli0O : STD_LOGIC := '0'; + SIGNAL nlli1i : STD_LOGIC := '0'; + SIGNAL nlli1l : STD_LOGIC := '0'; + SIGNAL nlli1O : STD_LOGIC := '0'; + SIGNAL nlliii : STD_LOGIC := '0'; + SIGNAL nlliil : STD_LOGIC := '0'; + SIGNAL nlliiO : STD_LOGIC := '0'; + SIGNAL nllili : STD_LOGIC := '0'; + SIGNAL nllill : STD_LOGIC := '0'; + SIGNAL nllilO : STD_LOGIC := '0'; + SIGNAL nlliOi : STD_LOGIC := '0'; + SIGNAL nlliOl : STD_LOGIC := '0'; + SIGNAL nlliOO : STD_LOGIC := '0'; + SIGNAL nlll0i : STD_LOGIC := '0'; + SIGNAL nlll0l : STD_LOGIC := '0'; + SIGNAL nlll0O : STD_LOGIC := '0'; + SIGNAL nlll1i : STD_LOGIC := '0'; + SIGNAL nlll1l : STD_LOGIC := '0'; + SIGNAL nlll1O : STD_LOGIC := '0'; + SIGNAL nlllii : STD_LOGIC := '0'; + SIGNAL wire_nliOi_CLRN : STD_LOGIC; + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3441w3442w3443w3444w3445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w3441w3442w3443w3444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w3441w3442w3443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w3441w3442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w3357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w3441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3350w3352w3353w3355w3356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3436w3437w3438w3439w3440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w3306w3307w3308w3309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w3350w3352w3353w3355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w3436w3437w3438w3439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w3306w3307w3308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w3350w3352w3353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w3436w3437w3438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w3306w3307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w3350w3352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w3436w3437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w3219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w2989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w3306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w3350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w3436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3215w3222w3223w3224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3215w3216w3217w3218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliii2965w2966w2987w2988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3202w3203w3205w3206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliii2993w2994w2996w2997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliiO3302w3303w3304w3305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliOO3344w3346w3347w3348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlll0i3430w3431w3433w3435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3215w3222w3223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3215w3216w3217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nlliii2965w2966w2987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3202w3203w3205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nlliii2993w2994w2996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nlliiO3302w3303w3304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nlliOO3344w3346w3347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_w_lg_nlll0i3430w3431w3433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nll0Ol3215w3222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nll0Ol3215w3216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlliii2965w2966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nll0Ol3202w3203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlliii2993w2994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlliiO3302w3303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlliOO3344w3346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlll0i3430w3431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlii0O2954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlii0O2944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nll0Ol3215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliii2965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nli0lO3213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nll0il3211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nll0iO3209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nll0li3207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nll0lO3204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nll0Ol3202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nll0OO3003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli0i2986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli0l2995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli1i2990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli1l3000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli1O2998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliii2993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliil3354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliiO3302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nllili3351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nllill3349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliOl3345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliOO3344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll0i3430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1i3434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1l3432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlliii2127w2128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlliOl1740w1741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlliOO1669w1670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlll0i1685w1686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlll1i2573w2574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlll1l2504w2505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_w_lg_nlll1O1756w1757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli0l2436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli0O2370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli0O2339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli1l2531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli1O2059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlli1O2462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliii2273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliii2127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliil2207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliiO2139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nllili2557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nllill2086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nllill2488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nllilO2017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliOi1948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliOl1740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliOl1879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlliOO1669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll0i1685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll0i1825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1i2573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1i2032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1l2504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1l1963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1O1756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliOi_w_lg_nlll1O1894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli00O : STD_LOGIC := '0'; + SIGNAL nli0ii : STD_LOGIC := '0'; + SIGNAL nli0il : STD_LOGIC := '0'; + SIGNAL nli0iO : STD_LOGIC := '0'; + SIGNAL nli0li : STD_LOGIC := '0'; + SIGNAL nli0ll : STD_LOGIC := '0'; + SIGNAL nliiO : STD_LOGIC := '0'; + SIGNAL nlili : STD_LOGIC := '0'; + SIGNAL nlill : STD_LOGIC := '0'; + SIGNAL nlilO : STD_LOGIC := '0'; + SIGNAL nliOO : STD_LOGIC := '0'; + SIGNAL nll0i : STD_LOGIC := '0'; + SIGNAL nll1i : STD_LOGIC := '0'; + SIGNAL nll1l : STD_LOGIC := '0'; + SIGNAL nlllil : STD_LOGIC := '0'; + SIGNAL wire_nll1O_w_lg_nli0li2861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_nli0li2856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_nli0li2902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_nli0li2886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_nli0li2589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_nll1l2599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_w_lg_nli0li2856w2857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_w_lg_nli0li2902w2903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1O_w_lg_w_lg_nli0li2886w2887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nll0l : STD_LOGIC := '0'; + SIGNAL nllil : STD_LOGIC := '0'; + SIGNAL wire_nllii_CLRN : STD_LOGIC; + SIGNAL wire_nllii_PRN : STD_LOGIC; + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0iii_dataout : STD_LOGIC; + SIGNAL wire_n0iil_dataout : STD_LOGIC; + SIGNAL wire_n0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0lii_dataout : STD_LOGIC; + SIGNAL wire_n0lil_dataout : STD_LOGIC; + SIGNAL wire_n0liO_dataout : STD_LOGIC; + SIGNAL wire_n0lli_dataout : STD_LOGIC; + SIGNAL wire_n0lll_dataout : STD_LOGIC; + SIGNAL wire_n0llO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n110i_dataout : STD_LOGIC; + SIGNAL wire_n111i_dataout : STD_LOGIC; + SIGNAL wire_n111l_dataout : STD_LOGIC; + SIGNAL wire_n111O_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0il_dataout : STD_LOGIC; + SIGNAL wire_ni0li_dataout : STD_LOGIC; + SIGNAL wire_ni0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_nilii_w_lg_dataout2862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilii_w_lg_dataout2621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilii_w_lg_w_lg_dataout2862w2863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_nilil_w_lg_dataout2635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00l_dataout : STD_LOGIC; + SIGNAL wire_nl00O_dataout : STD_LOGIC; + SIGNAL wire_nl01i_dataout : STD_LOGIC; + SIGNAL wire_nl01l_dataout : STD_LOGIC; + SIGNAL wire_nl01O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl10l_dataout : STD_LOGIC; + SIGNAL wire_nl10O_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0OO_dataout : STD_LOGIC; + SIGNAL wire_nli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l_dataout : STD_LOGIC; + SIGNAL wire_nlii1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1O_dataout : STD_LOGIC; + SIGNAL wire_nliiii_dataout : STD_LOGIC; + SIGNAL wire_nliiil_dataout : STD_LOGIC; + SIGNAL wire_nliil_dataout : STD_LOGIC; + SIGNAL wire_nliOil_dataout : STD_LOGIC; + SIGNAL wire_nll01i_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll0O_w_lg_dataout167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1li_dataout : STD_LOGIC; + SIGNAL wire_nll1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nllli_w_lg_dataout3262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllliO_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nlllli_dataout : STD_LOGIC; + SIGNAL wire_nlllll_dataout : STD_LOGIC; + SIGNAL wire_nllllO_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nlllOi_dataout : STD_LOGIC; + SIGNAL wire_nlllOl_dataout : STD_LOGIC; + SIGNAL wire_nlllOO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllO0i_dataout : STD_LOGIC; + SIGNAL wire_nllO0l_dataout : STD_LOGIC; + SIGNAL wire_nllO0O_dataout : STD_LOGIC; + SIGNAL wire_nllO1i_dataout : STD_LOGIC; + SIGNAL wire_nllO1l_dataout : STD_LOGIC; + SIGNAL wire_nllO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOii_dataout : STD_LOGIC; + SIGNAL wire_nllOil_dataout : STD_LOGIC; + SIGNAL wire_nllOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOli_dataout : STD_LOGIC; + SIGNAL wire_nllOll_dataout : STD_LOGIC; + SIGNAL wire_nllOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nllOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO11l_dataout : STD_LOGIC; + SIGNAL wire_nlO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_w_lg_dataout3255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_w_lg_w_lg_w3259w3260w3261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1l_w_lg_w3259w3260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1l_w3259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1l_w_lg_w_lg_w_lg_w_lg_dataout3254w3256w3257w3258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1l_w_lg_w_lg_w_lg_dataout3254w3256w3257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1l_w_lg_w_lg_dataout3254w3256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1l_w_lg_dataout3254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOili_dataout : STD_LOGIC; + SIGNAL wire_nlOill_dataout : STD_LOGIC; + SIGNAL wire_nlOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1O_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n1O_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n1O_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nil0O_i : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nil0O_o : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nill_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nill_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nill_o : STD_LOGIC; + SIGNAL wire_n100i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n100i_o : STD_LOGIC; + SIGNAL wire_n100i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n100l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n100l_o : STD_LOGIC; + SIGNAL wire_n100l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n100O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n100O_o : STD_LOGIC; + SIGNAL wire_n100O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n101i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n101i_o : STD_LOGIC; + SIGNAL wire_n101i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n101l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n101l_o : STD_LOGIC; + SIGNAL wire_n101l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n101O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n101O_o : STD_LOGIC; + SIGNAL wire_n101O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10ii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n10ii_o : STD_LOGIC; + SIGNAL wire_n10ii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10il_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n10il_o : STD_LOGIC; + SIGNAL wire_n10il_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10iO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n10iO_o : STD_LOGIC; + SIGNAL wire_n10iO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10li_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n10li_o : STD_LOGIC; + SIGNAL wire_n10li_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10ll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n10ll_o : STD_LOGIC; + SIGNAL wire_n10ll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n10lO_o : STD_LOGIC; + SIGNAL wire_n10lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n110l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n110l_o : STD_LOGIC; + SIGNAL wire_n110l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n110O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n110O_o : STD_LOGIC; + SIGNAL wire_n110O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11ii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11ii_o : STD_LOGIC; + SIGNAL wire_n11ii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11il_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11il_o : STD_LOGIC; + SIGNAL wire_n11il_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11iO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11iO_o : STD_LOGIC; + SIGNAL wire_n11iO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11li_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11li_o : STD_LOGIC; + SIGNAL wire_n11li_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11ll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11ll_o : STD_LOGIC; + SIGNAL wire_n11ll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11lO_o : STD_LOGIC; + SIGNAL wire_n11lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11Oi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11Oi_o : STD_LOGIC; + SIGNAL wire_n11Oi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11Ol_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11Ol_o : STD_LOGIC; + SIGNAL wire_n11Ol_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11OO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_n11OO_o : STD_LOGIC; + SIGNAL wire_n11OO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nii0i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nii0i_o : STD_LOGIC; + SIGNAL wire_nii0i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nii0l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nii0l_o : STD_LOGIC; + SIGNAL wire_nii0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nii0O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nii0O_o : STD_LOGIC; + SIGNAL wire_nii0O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nii1O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nii1O_o : STD_LOGIC; + SIGNAL wire_nii1O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiii_o : STD_LOGIC; + SIGNAL wire_niiii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niiiO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niiiO_o : STD_LOGIC; + SIGNAL wire_niiiO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niill_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niill_o : STD_LOGIC; + SIGNAL wire_niill_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niilO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_niilO_o : STD_LOGIC; + SIGNAL wire_niilO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliiiO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliiiO_o : STD_LOGIC; + SIGNAL wire_nliiiO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliili_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliili_o : STD_LOGIC; + SIGNAL wire_nliili_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliill_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliill_o : STD_LOGIC; + SIGNAL wire_nliill_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliilO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliilO_o : STD_LOGIC; + SIGNAL wire_nliilO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliiOi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliiOi_o : STD_LOGIC; + SIGNAL wire_nliiOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0ll_o : STD_LOGIC; + SIGNAL wire_n0ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lO_o : STD_LOGIC; + SIGNAL wire_n0lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Oi_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Oi_o : STD_LOGIC; + SIGNAL wire_n0Oi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Ol_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0Ol_o : STD_LOGIC; + SIGNAL wire_n0Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0iO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0iO_o : STD_LOGIC; + SIGNAL wire_ni0iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0lO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0lO_o : STD_LOGIC; + SIGNAL wire_ni0lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl00i_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl00i_o : STD_LOGIC; + SIGNAL wire_nl00i_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl0iO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl0iO_o : STD_LOGIC; + SIGNAL wire_nl0iO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl0OO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl0OO_o : STD_LOGIC; + SIGNAL wire_nl0OO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nli0O_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nli0O_o : STD_LOGIC; + SIGNAL wire_nli0O_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rpmadwidth_rx3059w3167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpmadwidth_rx3110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sync_status2690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sync_status2674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niil0O2953w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilii2943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilll2631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilOl2627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiO1i2625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiO1O2623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiOil2615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiOll2612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiOOi2610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil10i2600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nililO2595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niliOi2594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niliOl2593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niliOO2592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill1i2591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill1l2590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill1O2588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillil256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilliO254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillli252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillll250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilllO248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO0i209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO0l207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO0O205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO1l226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOii203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOil201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOli188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOll183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOlO181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOOi179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOOl185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOOO222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO00O146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO1Oi128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO1OO117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rall_one_dect_only477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpma_doublewidth_rx3060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rpmadwidth_rx3059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_sync_status2690w2691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_sync_status2674w2675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilli2830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilOi2828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niilOO2814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiO1l2812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiOii2796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiOli2788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niiOlO2784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil11O2779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nil00O1614w1615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nil0ii1543w1544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nil0il1472w1473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nil0iO1333w1334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nil0li1263w1264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nil0Ol1598w1599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nil0OO1527w1528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil00O1614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil01l2170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0ii1543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0il1472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0iO1333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0iO1403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0li1263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0Ol1598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0OO1527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil1Oi2155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nili1i1932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nili1l2001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nili1O2070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niil0i : STD_LOGIC; + SIGNAL niil0l : STD_LOGIC; + SIGNAL niil0O : STD_LOGIC; + SIGNAL niil1l : STD_LOGIC; + SIGNAL niil1O : STD_LOGIC; + SIGNAL niilii : STD_LOGIC; + SIGNAL niilil : STD_LOGIC; + SIGNAL niiliO : STD_LOGIC; + SIGNAL niilli : STD_LOGIC; + SIGNAL niilll : STD_LOGIC; + SIGNAL niillO : STD_LOGIC; + SIGNAL niilOi : STD_LOGIC; + SIGNAL niilOl : STD_LOGIC; + SIGNAL niilOO : STD_LOGIC; + SIGNAL niiO0i : STD_LOGIC; + SIGNAL niiO0l : STD_LOGIC; + SIGNAL niiO0O : STD_LOGIC; + SIGNAL niiO1i : STD_LOGIC; + SIGNAL niiO1l : STD_LOGIC; + SIGNAL niiO1O : STD_LOGIC; + SIGNAL niiOii : STD_LOGIC; + SIGNAL niiOil : STD_LOGIC; + SIGNAL niiOiO : STD_LOGIC; + SIGNAL niiOli : STD_LOGIC; + SIGNAL niiOll : STD_LOGIC; + SIGNAL niiOlO : STD_LOGIC; + SIGNAL niiOOi : STD_LOGIC; + SIGNAL niiOOl : STD_LOGIC; + SIGNAL niiOOO : STD_LOGIC; + SIGNAL nil00i : STD_LOGIC; + SIGNAL nil00l : STD_LOGIC; + SIGNAL nil00O : STD_LOGIC; + SIGNAL nil01i : STD_LOGIC; + SIGNAL nil01l : STD_LOGIC; + SIGNAL nil01O : STD_LOGIC; + SIGNAL nil0ii : STD_LOGIC; + SIGNAL nil0il : STD_LOGIC; + SIGNAL nil0iO : STD_LOGIC; + SIGNAL nil0li : STD_LOGIC; + SIGNAL nil0ll : STD_LOGIC; + SIGNAL nil0lO : STD_LOGIC; + SIGNAL nil0Oi : STD_LOGIC; + SIGNAL nil0Ol : STD_LOGIC; + SIGNAL nil0OO : STD_LOGIC; + SIGNAL nil10i : STD_LOGIC; + SIGNAL nil10l : STD_LOGIC; + SIGNAL nil10O : STD_LOGIC; + SIGNAL nil11i : STD_LOGIC; + SIGNAL nil11l : STD_LOGIC; + SIGNAL nil11O : STD_LOGIC; + SIGNAL nil1ii : STD_LOGIC; + SIGNAL nil1il : STD_LOGIC; + SIGNAL nil1iO : STD_LOGIC; + SIGNAL nil1li : STD_LOGIC; + SIGNAL nil1ll : STD_LOGIC; + SIGNAL nil1lO : STD_LOGIC; + SIGNAL nil1Oi : STD_LOGIC; + SIGNAL nil1Ol : STD_LOGIC; + SIGNAL nil1OO : STD_LOGIC; + SIGNAL nili0i : STD_LOGIC; + SIGNAL nili0l : STD_LOGIC; + SIGNAL nili0O : STD_LOGIC; + SIGNAL nili1i : STD_LOGIC; + SIGNAL nili1l : STD_LOGIC; + SIGNAL nili1O : STD_LOGIC; + SIGNAL niliii : STD_LOGIC; + SIGNAL niliil : STD_LOGIC; + SIGNAL niliiO : STD_LOGIC; + SIGNAL nilili : STD_LOGIC; + SIGNAL nilill : STD_LOGIC; + SIGNAL nililO : STD_LOGIC; + SIGNAL niliOi : STD_LOGIC; + SIGNAL niliOl : STD_LOGIC; + SIGNAL niliOO : STD_LOGIC; + SIGNAL nill0i : STD_LOGIC; + SIGNAL nill0l : STD_LOGIC; + SIGNAL nill0O : STD_LOGIC; + SIGNAL nill1i : STD_LOGIC; + SIGNAL nill1l : STD_LOGIC; + SIGNAL nill1O : STD_LOGIC; + SIGNAL nillii : STD_LOGIC; + SIGNAL nillil : STD_LOGIC; + SIGNAL nilliO : STD_LOGIC; + SIGNAL nillli : STD_LOGIC; + SIGNAL nillll : STD_LOGIC; + SIGNAL nilllO : STD_LOGIC; + SIGNAL nilO0i : STD_LOGIC; + SIGNAL nilO0l : STD_LOGIC; + SIGNAL nilO0O : STD_LOGIC; + SIGNAL nilO1l : STD_LOGIC; + SIGNAL nilOii : STD_LOGIC; + SIGNAL nilOil : STD_LOGIC; + SIGNAL nilOli : STD_LOGIC; + SIGNAL nilOll : STD_LOGIC; + SIGNAL nilOlO : STD_LOGIC; + SIGNAL nilOOi : STD_LOGIC; + SIGNAL nilOOl : STD_LOGIC; + SIGNAL nilOOO : STD_LOGIC; + SIGNAL niO00O : STD_LOGIC; + SIGNAL niO01i : STD_LOGIC; + SIGNAL niO0ii : STD_LOGIC; + SIGNAL niO0il : STD_LOGIC; + SIGNAL niO0Ol : STD_LOGIC; + SIGNAL niO10O : STD_LOGIC; + SIGNAL niO11l : STD_LOGIC; + SIGNAL niO11O : STD_LOGIC; + SIGNAL niO1ii : STD_LOGIC; + SIGNAL niO1il : STD_LOGIC; + SIGNAL niO1iO : STD_LOGIC; + SIGNAL niO1Oi : STD_LOGIC; + SIGNAL niO1OO : STD_LOGIC; + SIGNAL niOi0i : STD_LOGIC; + SIGNAL niOi0O : STD_LOGIC; + BEGIN + + wire_gnd <= '0'; + wire_w_lg_w_lg_rpmadwidth_rx3059w3167w(0) <= wire_w_lg_rpmadwidth_rx3059w(0) AND rpma_doublewidth_rx; + wire_w_lg_niOi0O113w(0) <= niOi0O AND wire_ni_w_lg_w_lg_w_lg_nlO108w111w112w(0); + wire_w_lg_rpmadwidth_rx3110w(0) <= rpmadwidth_rx AND wire_w_lg_rpma_doublewidth_rx3060w(0); + wire_w_lg_sync_status2690w(0) <= sync_status AND niil0O; + wire_w_lg_sync_status2674w(0) <= sync_status AND niilii; + wire_w_lg_niil0O2953w(0) <= NOT niil0O; + wire_w_lg_niilii2943w(0) <= NOT niilii; + wire_w_lg_niilll2631w(0) <= NOT niilll; + wire_w_lg_niilOl2627w(0) <= NOT niilOl; + wire_w_lg_niiO1i2625w(0) <= NOT niiO1i; + wire_w_lg_niiO1O2623w(0) <= NOT niiO1O; + wire_w_lg_niiOil2615w(0) <= NOT niiOil; + wire_w_lg_niiOll2612w(0) <= NOT niiOll; + wire_w_lg_niiOOi2610w(0) <= NOT niiOOi; + wire_w_lg_nil10i2600w(0) <= NOT nil10i; + wire_w_lg_nililO2595w(0) <= NOT nililO; + wire_w_lg_niliOi2594w(0) <= NOT niliOi; + wire_w_lg_niliOl2593w(0) <= NOT niliOl; + wire_w_lg_niliOO2592w(0) <= NOT niliOO; + wire_w_lg_nill1i2591w(0) <= NOT nill1i; + wire_w_lg_nill1l2590w(0) <= NOT nill1l; + wire_w_lg_nill1O2588w(0) <= NOT nill1O; + wire_w_lg_nillil256w(0) <= NOT nillil; + wire_w_lg_nilliO254w(0) <= NOT nilliO; + wire_w_lg_nillli252w(0) <= NOT nillli; + wire_w_lg_nillll250w(0) <= NOT nillll; + wire_w_lg_nilllO248w(0) <= NOT nilllO; + wire_w_lg_nilO0i209w(0) <= NOT nilO0i; + wire_w_lg_nilO0l207w(0) <= NOT nilO0l; + wire_w_lg_nilO0O205w(0) <= NOT nilO0O; + wire_w_lg_nilO1l226w(0) <= NOT nilO1l; + wire_w_lg_nilOii203w(0) <= NOT nilOii; + wire_w_lg_nilOil201w(0) <= NOT nilOil; + wire_w_lg_nilOli188w(0) <= NOT nilOli; + wire_w_lg_nilOll183w(0) <= NOT nilOll; + wire_w_lg_nilOlO181w(0) <= NOT nilOlO; + wire_w_lg_nilOOi179w(0) <= NOT nilOOi; + wire_w_lg_nilOOl185w(0) <= NOT nilOOl; + wire_w_lg_nilOOO222w(0) <= NOT nilOOO; + wire_w_lg_niO00O146w(0) <= NOT niO00O; + wire_w_lg_niO1Oi128w(0) <= NOT niO1Oi; + wire_w_lg_niO1OO117w(0) <= NOT niO1OO; + wire_w_lg_rall_one_dect_only477w(0) <= NOT rall_one_dect_only; + wire_w_lg_rpma_doublewidth_rx3060w(0) <= NOT rpma_doublewidth_rx; + wire_w_lg_rpmadwidth_rx3059w(0) <= NOT rpmadwidth_rx; + wire_w_lg_soft_reset7w(0) <= NOT soft_reset; + wire_w_lg_w_lg_sync_status2690w2691w(0) <= wire_w_lg_sync_status2690w(0) OR nli0li; + wire_w_lg_w_lg_sync_status2674w2675w(0) <= wire_w_lg_sync_status2674w(0) OR nli0li; + wire_w_lg_niilli2830w(0) <= niilli OR nli00O; + wire_w_lg_niilOi2828w(0) <= niilOi OR nli00O; + wire_w_lg_niilOO2814w(0) <= niilOO OR nli00O; + wire_w_lg_niiO1l2812w(0) <= niiO1l OR nli00O; + wire_w_lg_niiOii2796w(0) <= niiOii OR nli00O; + wire_w_lg_niiOli2788w(0) <= niiOli OR nli00O; + wire_w_lg_niiOlO2784w(0) <= niiOlO OR nli00O; + wire_w_lg_nil11O2779w(0) <= nil11O OR nli00O; + wire_w_lg_w_lg_nil00O1614w1615w(0) <= wire_w_lg_nil00O1614w(0) XOR nlliOi; + wire_w_lg_w_lg_nil0ii1543w1544w(0) <= wire_w_lg_nil0ii1543w(0) XOR nlliOl; + wire_w_lg_w_lg_nil0il1472w1473w(0) <= wire_w_lg_nil0il1472w(0) XOR nlliOO; + wire_w_lg_w_lg_nil0iO1333w1334w(0) <= wire_w_lg_nil0iO1333w(0) XOR nlliOi; + wire_w_lg_w_lg_nil0li1263w1264w(0) <= wire_w_lg_nil0li1263w(0) XOR nlliOi; + wire_w_lg_w_lg_nil0Ol1598w1599w(0) <= wire_w_lg_nil0Ol1598w(0) XOR nlliiO; + wire_w_lg_w_lg_nil0OO1527w1528w(0) <= wire_w_lg_nil0OO1527w(0) XOR nllili; + wire_w_lg_nil00O1614w(0) <= nil00O XOR nlliOl; + wire_w_lg_nil01l2170w(0) <= nil01l XOR nlliOi; + wire_w_lg_nil0ii1543w(0) <= nil0ii XOR nlliOO; + wire_w_lg_nil0il1472w(0) <= nil0il XOR nlll1i; + wire_w_lg_nil0iO1333w(0) <= nil0iO XOR nlliOl; + wire_w_lg_nil0iO1403w(0) <= nil0iO XOR nlll1i; + wire_w_lg_nil0li1263w(0) <= nil0li XOR nlliOO; + wire_w_lg_nil0Ol1598w(0) <= nil0Ol XOR nllili; + wire_w_lg_nil0OO1527w(0) <= nil0OO XOR nllill; + wire_w_lg_nil1Oi2155w(0) <= nil1Oi XOR nlliiO; + wire_w_lg_nili1i1932w(0) <= nili1i XOR nlliiO; + wire_w_lg_nili1l2001w(0) <= nili1l XOR nlliil; + wire_w_lg_nili1O2070w(0) <= nili1O XOR nlliii; + encdet_prbs <= nlii0O; + niil0i <= (wire_nlO1l_w_lg_w_lg_w3259w3260w3261w(0) AND wire_nllli_w_lg_dataout3262w(0)); + niil0l <= ((((wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliii2993w2994w2996w2997w(0) AND wire_nliOi_w_lg_nlli1O2998w(0)) AND nlli1l) AND nlli1i) AND nll0OO); + niil0O <= ((((((((((((((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND (NOT data_in(3))) AND (NOT data_in(4))) AND (NOT data_in(5))) AND data_in(6)) AND (NOT data_in(7))) AND (NOT data_in(8))) AND (NOT data_in(9))) AND (NOT data_in(10))) AND (NOT data_in(11))) AND data_in(12)) AND data_in(13)) AND (NOT data_in(14))) AND (NOT data_in(15))) AND (NOT data_in(16))) AND (NOT data_in(17))) AND data_in(18)) AND (NOT data_in(19))); + niil1l <= ((((((wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3441w3442w3443w3444w3445w(0) AND wire_nliOi_w_lg_nlli0l2995w(0)) AND wire_nliOi_w_lg_nlli0i2986w(0)) AND wire_nliOi_w_lg_nlli1O2998w(0)) AND wire_nliOi_w_lg_nlli1l3000w(0)) AND wire_nliOi_w_lg_nlli1i2990w(0)) AND wire_nliOi_w_lg_nll0OO3003w(0)); + niil1O <= ((((((wire_nliOi_w3357w(0) AND wire_nliOi_w_lg_nlli0l2995w(0)) AND wire_nliOi_w_lg_nlli0i2986w(0)) AND wire_nliOi_w_lg_nlli1O2998w(0)) AND wire_nliOi_w_lg_nlli1l3000w(0)) AND wire_nliOi_w_lg_nlli1i2990w(0)) AND wire_nliOi_w_lg_nll0OO3003w(0)); + niilii <= ((((((((((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND (NOT data_in(3))) AND (NOT data_in(4))) AND (NOT data_in(5))) AND data_in(6)) AND (NOT data_in(7))) AND (NOT data_in(10))) AND (NOT data_in(11))) AND (NOT data_in(12))) AND (NOT data_in(13))) AND data_in(14)) AND data_in(15)) AND (NOT data_in(16))) AND (NOT data_in(17))); + niilil <= (wire_nilil_w_lg_dataout2635w(0) AND nlii0O); + niiliO <= ((wire_nilil_dataout AND nli0li) OR nli0ll); + niilli <= (nli0li AND wire_w_lg_niilll2631w(0)); + niilll <= ((((((((((((((((((((NOT (wire_nllli_dataout XOR data_in(0))) AND (NOT (wire_nllll_dataout XOR data_in(1)))) AND (NOT (wire_nlllO_dataout XOR data_in(2)))) AND (NOT (wire_nllOi_dataout XOR data_in(3)))) AND (NOT (wire_nllOl_dataout XOR data_in(4)))) AND (NOT (wire_nllOO_dataout XOR data_in(5)))) AND (NOT (wire_nlO1i_dataout XOR data_in(6)))) AND (NOT (wire_nlO1l_dataout XOR data_in(7)))) AND (NOT (wire_nlO1O_dataout XOR data_in(8)))) AND (NOT (wire_nlO0i_dataout XOR data_in(9)))) AND (NOT (wire_nlO0l_dataout XOR data_in(10)))) AND (NOT (wire_nlO0O_dataout XOR data_in(11)))) AND (NOT (wire_nlOii_dataout XOR data_in(12)))) AND (NOT (wire_nlOil_dataout XOR data_in(13)))) AND (NOT (wire_nlOiO_dataout XOR data_in(14)))) AND (NOT (wire_nlOli_dataout XOR data_in(15)))) AND (NOT (wire_nlOll_dataout XOR data_in(16)))) AND (NOT (wire_nlOlO_dataout XOR data_in(17)))) AND (NOT (wire_nlOOi_dataout XOR data_in(18)))) AND (NOT (wire_nlOOl_dataout XOR data_in(19)))); + niillO <= ((wire_nilil_dataout AND sync_status) OR nli0li); + niilOi <= (nli0li AND wire_w_lg_niilOl2627w(0)); + niilOl <= ((((((((((((((((((((NOT (nll0OO XOR data_in(0))) AND (NOT (nlli1i XOR data_in(1)))) AND (NOT (nlli1l XOR data_in(2)))) AND (NOT (nlli1O XOR data_in(3)))) AND (NOT (nlli0i XOR data_in(4)))) AND (NOT (nlli0l XOR data_in(5)))) AND (NOT (nlli0O XOR data_in(6)))) AND (NOT (nlliii XOR data_in(7)))) AND (NOT (nlliil XOR data_in(8)))) AND (NOT (nlliiO XOR data_in(9)))) AND (NOT (nllili XOR data_in(10)))) AND (NOT (nllill XOR data_in(11)))) AND (NOT (nllilO XOR data_in(12)))) AND (NOT (nlliOi XOR data_in(13)))) AND (NOT (nlliOl XOR data_in(14)))) AND (NOT (nlliOO XOR data_in(15)))) AND (NOT (nlll1i XOR data_in(16)))) AND (NOT (nlll1l XOR data_in(17)))) AND (NOT (nlll1O XOR data_in(18)))) AND (NOT (nlll0i XOR data_in(19)))); + niilOO <= (nli0li AND wire_w_lg_niiO1i2625w(0)); + niiO0i <= (wire_nilii_w_lg_dataout2621w(0) AND nlii0O); + niiO0l <= (((((((((nlliiO AND nlliil) AND nlliii) AND nlli0O) AND nlli0l) AND nlli0i) AND nlli1O) AND nlli1l) AND nlli1i) AND nll0OO); + niiO0O <= ((wire_nliOi_w_lg_w_lg_w_lg_w3306w3307w3308w3309w(0) AND wire_nliOi_w_lg_nlli1i2990w(0)) AND wire_nliOi_w_lg_nll0OO3003w(0)); + niiO1i <= ((((((((((((((((NOT (wire_nllli_dataout XOR data_in(0))) AND (NOT (wire_nllll_dataout XOR data_in(1)))) AND (NOT (wire_nlllO_dataout XOR data_in(2)))) AND (NOT (wire_nllOi_dataout XOR data_in(3)))) AND (NOT (wire_nllOl_dataout XOR data_in(4)))) AND (NOT (wire_nllOO_dataout XOR data_in(5)))) AND (NOT (wire_nlO1i_dataout XOR data_in(6)))) AND (NOT (wire_nlO1l_dataout XOR data_in(7)))) AND (NOT (wire_nlO1O_dataout XOR data_in(10)))) AND (NOT (wire_nlO0i_dataout XOR data_in(11)))) AND (NOT (wire_nlO0l_dataout XOR data_in(12)))) AND (NOT (wire_nlO0O_dataout XOR data_in(13)))) AND (NOT (wire_nlOii_dataout XOR data_in(14)))) AND (NOT (wire_nlOil_dataout XOR data_in(15)))) AND (NOT (wire_nlOiO_dataout XOR data_in(16)))) AND (NOT (wire_nlOli_dataout XOR data_in(17)))); + niiO1l <= (nli0li AND wire_w_lg_niiO1O2623w(0)); + niiO1O <= ((((((((((((((((NOT (nll0OO XOR data_in(0))) AND (NOT (nlli1i XOR data_in(1)))) AND (NOT (nlli1l XOR data_in(2)))) AND (NOT (nlli1O XOR data_in(3)))) AND (NOT (nlli0i XOR data_in(4)))) AND (NOT (nlli0l XOR data_in(5)))) AND (NOT (nlli0O XOR data_in(6)))) AND (NOT (nlliii XOR data_in(7)))) AND (NOT (nlliil XOR data_in(10)))) AND (NOT (nlliiO XOR data_in(11)))) AND (NOT (nllili XOR data_in(12)))) AND (NOT (nllill XOR data_in(13)))) AND (NOT (nllilO XOR data_in(14)))) AND (NOT (nlliOi XOR data_in(15)))) AND (NOT (nlliOl XOR data_in(16)))) AND (NOT (nlliOO XOR data_in(17)))); + niiOii <= (nli0li AND wire_w_lg_niiOil2615w(0)); + niiOil <= ((((((((((NOT (nll0OO XOR data_in(0))) AND (NOT (nlli1i XOR data_in(1)))) AND (NOT (nlli1l XOR data_in(2)))) AND (NOT (nlli1O XOR data_in(3)))) AND (NOT (nlli0i XOR data_in(4)))) AND (NOT (nlli0l XOR data_in(5)))) AND (NOT (nlli0O XOR data_in(6)))) AND (NOT (nlliii XOR data_in(7)))) AND (NOT (nlliil XOR data_in(8)))) AND (NOT (nlliiO XOR data_in(9)))); + niiOiO <= (wire_nilii_dataout OR nli0li); + niiOli <= (nli0li AND wire_w_lg_niiOll2612w(0)); + niiOll <= ((((((((NOT (wire_nllli_dataout XOR data_in(0))) AND (NOT (wire_nllll_dataout XOR data_in(1)))) AND (NOT (wire_nlllO_dataout XOR data_in(2)))) AND (NOT (wire_nllOi_dataout XOR data_in(3)))) AND (NOT (wire_nllOl_dataout XOR data_in(4)))) AND (NOT (wire_nllOO_dataout XOR data_in(5)))) AND (NOT (wire_nlO1i_dataout XOR data_in(6)))) AND (NOT (wire_nlO1l_dataout XOR data_in(7)))); + niiOlO <= (nli0li AND wire_w_lg_niiOOi2610w(0)); + niiOOi <= ((((((((NOT (nll0OO XOR data_in(0))) AND (NOT (nlli1i XOR data_in(1)))) AND (NOT (nlli1l XOR data_in(2)))) AND (NOT (nlli1O XOR data_in(3)))) AND (NOT (nlli0i XOR data_in(4)))) AND (NOT (nlli0l XOR data_in(5)))) AND (NOT (nlli0O XOR data_in(6)))) AND (NOT (nlliii XOR data_in(7)))); + niiOOl <= (((wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3215w3222w3223w3224w(0) AND wire_nliOi_w_lg_nll0iO3209w(0)) AND wire_nliOi_w_lg_nll0il3211w(0)) AND wire_nliOi_w_lg_nli0lO3213w(0)); + niiOOO <= ((((wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3202w3203w3205w3206w(0) AND wire_nliOi_w_lg_nll0li3207w(0)) AND wire_nliOi_w_lg_nll0iO3209w(0)) AND wire_nliOi_w_lg_nll0il3211w(0)) AND wire_nliOi_w_lg_nli0lO3213w(0)); + nil00i <= (nlll0O XOR nlll1i); + nil00l <= (nlllii XOR nlll1l); + nil00O <= (nlll1i XOR nlliOO); + nil01i <= (nlll1O XOR nlliOi); + nil01l <= (nlll0i XOR nlliOl); + nil01O <= (nlll0l XOR nlliOO); + nil0ii <= (nlll1l XOR nlll1i); + nil0il <= (nlll1O XOR nlll1l); + nil0iO <= (nil0li XOR nlll1l); + nil0li <= (nlll0i XOR nlll1O); + nil0ll <= (nlliOl XOR nlliOi); + nil0lO <= (nlliOO XOR nlliOl); + nil0Oi <= (nlliOO XOR nlliOi); + nil0Ol <= (nllilO XOR nllill); + nil0OO <= (nlliOi XOR nllilO); + nil10i <= ((((((((NOT (nliO XOR nli0lO)) AND (NOT (n0i XOR nll0il))) AND (NOT (n0l XOR nll0iO))) AND (NOT (n0O XOR nll0li))) AND (NOT (nii XOR nll0ll))) AND (NOT (nil XOR nll0lO))) AND (NOT (niO XOR nll0Oi))) AND (NOT (nli XOR nll0Ol))); + nil10l <= (nlliii XOR nlli1l); + nil10O <= (nlliil XOR nlli1O); + nil11i <= (nlO AND wire_ni_w_lg_nll2606w(0)); + nil11l <= ((wire_nliOi_w3219w(0) AND wire_nliOi_w_lg_nll0il3211w(0)) AND wire_nliOi_w_lg_nli0lO3213w(0)); + nil11O <= (nli0li AND wire_w_lg_nil10i2600w(0)); + nil1ii <= (nlliiO XOR nlli0i); + nil1il <= (nllili XOR nlli0l); + nil1iO <= (nllill XOR nlli0O); + nil1li <= (nllilO XOR nlliii); + nil1ll <= (nlliOi XOR nlliil); + nil1lO <= (nlliOl XOR nlliiO); + nil1Oi <= (nlliOO XOR nllili); + nil1Ol <= (nlll1i XOR nllill); + nil1OO <= (nlll1l XOR nllilO); + nili0i <= (nlli0i XOR nlli1O); + nili0l <= (nlli0l XOR nlli0i); + nili0O <= (nlli0O XOR nlli0l); + nili1i <= (nlli0l XOR nlli1l); + nili1l <= (nlli0i XOR nlli1i); + nili1O <= (nlli1O XOR nll0OO); + niliii <= (nlliii XOR nlli0O); + niliil <= (wire_n0li_dataout OR wire_n0iO_dataout); + niliiO <= (nll1l AND nli0li); + nilili <= (((((((((((((((((((((((wire_nil0O_o(31) OR wire_nil0O_o(30)) OR wire_nil0O_o(29)) OR wire_nil0O_o(28)) OR wire_nil0O_o(27)) OR wire_nil0O_o(26)) OR wire_nil0O_o(23)) OR wire_nil0O_o(22)) OR wire_nil0O_o(21)) OR wire_nil0O_o(20)) OR wire_nil0O_o(19)) OR wire_nil0O_o(18)) OR wire_nil0O_o(15)) OR wire_nil0O_o(14)) OR wire_nil0O_o(13)) OR wire_nil0O_o(12)) OR wire_nil0O_o(11)) OR wire_nil0O_o(10)) OR wire_nil0O_o(9)) OR wire_nil0O_o(7)) OR wire_nil0O_o(6)) OR wire_nil0O_o(5)) OR wire_nil0O_o(3)) OR wire_nil0O_o(1)); + nilill <= ((((((wire_nil0O_o(25) OR wire_nil0O_o(17)) OR wire_nil0O_o(16)) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(24)) OR wire_nil0O_o(4)); + nililO <= ((((wire_nil0O_o(25) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0)) OR wire_nil0O_o(24)); + niliOi <= ((((((wire_nil0O_o(25) OR wire_nil0O_o(16)) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0)) OR wire_nil0O_o(24)) OR wire_nil0O_o(4)); + niliOl <= (((((wire_nil0O_o(25) OR wire_nil0O_o(17)) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0)) OR wire_nil0O_o(4)); + niliOO <= ((((((wire_nil0O_o(25) OR wire_nil0O_o(17)) OR wire_nil0O_o(16)) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0)) OR wire_nil0O_o(4)); + nill0i <= (((((((((((((((((((data_in(0) AND data_in(1)) AND data_in(2)) AND (NOT data_in(3))) AND (NOT data_in(4))) AND (NOT data_in(5))) AND (NOT data_in(6))) AND (NOT data_in(7))) AND (NOT data_in(8))) AND (NOT data_in(9))) AND (NOT data_in(10))) AND (NOT data_in(11))) AND (NOT data_in(12))) AND (NOT data_in(13))) AND (NOT data_in(14))) AND (NOT data_in(15))) AND (NOT data_in(16))) AND (NOT data_in(17))) AND (NOT data_in(18))) AND (NOT data_in(19))); + nill0l <= (((((((((((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND (NOT data_in(7))) AND (NOT data_in(10))) AND (NOT data_in(11))) AND (NOT data_in(12))) AND (NOT data_in(13))) AND (NOT data_in(14))) AND (NOT data_in(15))) AND (NOT data_in(16))) AND (NOT data_in(17))); + nill0O <= ((((wire_w_lg_rpmadwidth_rx3059w(0) AND wire_w_lg_rpma_doublewidth_rx3060w(0)) AND (NOT rprbs_sel(0))) AND rprbs_sel(1)) AND (NOT rprbs_sel(2))); + nill1i <= (((((wire_nil0O_o(17) OR wire_nil0O_o(16)) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0)) OR wire_nil0O_o(4)); + nill1l <= ((((((wire_nil0O_o(17) OR wire_nil0O_o(16)) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0)) OR wire_nil0O_o(24)) OR wire_nil0O_o(4)); + nill1O <= (((((((wire_nil0O_o(25) OR wire_nil0O_o(17)) OR wire_nil0O_o(16)) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0)) OR wire_nil0O_o(24)) OR wire_nil0O_o(4)); + nillii <= (((wire_w_lg_rpmadwidth_rx3110w(0) AND (NOT rprbs_sel(0))) AND (NOT rprbs_sel(1))) AND (NOT rprbs_sel(2))); + nillil <= (((((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND data_in(7)) AND data_in(8)) AND data_in(9)); + nilliO <= ((((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND (NOT data_in(3))) AND (NOT data_in(4))) AND (NOT data_in(5))) AND (NOT data_in(6))) AND data_in(7)) AND data_in(8)) AND data_in(9)); + nillli <= ((((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND (NOT data_in(3))) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND data_in(7)) AND data_in(8)) AND data_in(9)); + nillll <= ((((((((((NOT data_in(0)) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND (NOT data_in(4))) AND (NOT data_in(5))) AND (NOT data_in(6))) AND data_in(7)) AND (NOT data_in(8))) AND (NOT data_in(9))); + nilllO <= (((((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND data_in(4)) AND (NOT data_in(5))) AND (NOT data_in(6))) AND (NOT data_in(7))) AND data_in(8)) AND data_in(9)); + nilO0i <= ((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND (NOT data_in(3))) AND (NOT data_in(4))) AND (NOT data_in(5))) AND data_in(6)) AND (NOT data_in(7))); + nilO0l <= ((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND (NOT data_in(3))) AND data_in(4)) AND data_in(5)) AND (NOT data_in(6))) AND (NOT data_in(7))); + nilO0O <= ((((((((NOT data_in(0)) AND (NOT data_in(1))) AND data_in(2)) AND (NOT data_in(3))) AND data_in(4)) AND (NOT data_in(5))) AND (NOT data_in(6))) AND (NOT data_in(7))); + nilO1l <= (((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND (NOT data_in(7))); + nilOii <= (((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND (NOT data_in(4))) AND (NOT data_in(5))) AND data_in(6)) AND (NOT data_in(7))); + nilOil <= ((((((((NOT data_in(0)) AND (NOT data_in(1))) AND data_in(2)) AND (NOT data_in(3))) AND data_in(4)) AND data_in(5)) AND (NOT data_in(6))) AND (NOT data_in(7))); + nilOli <= ((((((((NOT data_in(0)) AND data_in(1)) AND (NOT data_in(2))) AND data_in(3)) AND data_in(4)) AND (NOT data_in(5))) AND data_in(6)) AND (NOT data_in(7))); + nilOll <= ((((((((NOT data_in(0)) AND (NOT data_in(1))) AND data_in(2)) AND (NOT data_in(3))) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND data_in(7)); + nilOlO <= ((((((((NOT data_in(0)) AND data_in(1)) AND (NOT data_in(2))) AND (NOT data_in(3))) AND data_in(4)) AND (NOT data_in(5))) AND data_in(6)) AND (NOT data_in(7))); + nilOOi <= ((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND data_in(3)) AND data_in(4)) AND (NOT data_in(5))) AND data_in(6)) AND data_in(7)); + nilOOl <= (((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND data_in(7)); + nilOOO <= ((((((((NOT data_in(0)) AND (NOT data_in(1))) AND (NOT data_in(2))) AND (NOT data_in(3))) AND (NOT data_in(4))) AND (NOT data_in(5))) AND (NOT data_in(6))) AND (NOT data_in(7))); + niO00O <= (((((((wire_ni_w_lg_nlil2972w(0) AND wire_ni_w_lg_nlii2973w(0)) AND wire_ni_w_lg_nl0O2975w(0)) AND wire_ni_w_lg_nl0l2977w(0)) AND wire_ni_w_lg_nl0i2979w(0)) AND wire_ni_w_lg_nl1O2981w(0)) AND wire_ni_w_lg_nl1l2983w(0)) AND nl1i); + niO01i <= (wire_w_lg_niOi0O113w(0) AND (niO01l24 XOR niO01l23)); + niO0ii <= (niOi0O AND (((nlO AND wire_nill_o) AND (niO0iO20 XOR niO0iO19)) AND niO0il)); + niO0il <= ((wire_nliOi_w2989w(0) AND wire_nliOi_w_lg_nlli1i2990w(0)) AND nll0OO); + niO0Ol <= ((((wire_w_lg_rpmadwidth_rx3059w(0) AND wire_w_lg_rpma_doublewidth_rx3060w(0)) AND (NOT rprbs_sel(0))) AND (NOT rprbs_sel(1))) AND (NOT rprbs_sel(2))); + niO10O <= '0'; + niO11l <= (((((((((((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND data_in(7)) AND data_in(10)) AND data_in(11)) AND data_in(12)) AND data_in(13)) AND data_in(14)) AND data_in(15)) AND data_in(16)) AND data_in(17)); + niO11O <= (((((((((((((((((((data_in(0) AND data_in(1)) AND data_in(2)) AND data_in(3)) AND data_in(4)) AND data_in(5)) AND data_in(6)) AND data_in(7)) AND data_in(8)) AND data_in(9)) AND data_in(10)) AND data_in(11)) AND data_in(12)) AND data_in(13)) AND data_in(14)) AND data_in(15)) AND data_in(16)) AND data_in(17)) AND data_in(18)) AND data_in(19)); + niO1ii <= ((((rpmadwidth_rx AND rpma_doublewidth_rx) AND rprbs_sel(0)) AND (NOT rprbs_sel(1))) AND (NOT rprbs_sel(2))); + niO1il <= (((wire_w_lg_w_lg_rpmadwidth_rx3059w3167w(0) AND rprbs_sel(0)) AND (NOT rprbs_sel(1))) AND (NOT rprbs_sel(2))); + niO1iO <= ((((wire_w_lg_rpmadwidth_rx3059w(0) AND wire_w_lg_rpma_doublewidth_rx3060w(0)) AND (NOT rprbs_sel(0))) AND (NOT rprbs_sel(1))) AND rprbs_sel(2)); + niO1Oi <= (((((wire_nliOi_w_lg_w_lg_nlliii2965w2966w(0) AND nlli0i) AND nlli1O) AND nlli1l) AND nlli1i) AND nll0OO); + niO1OO <= ((((wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliii2993w2994w2996w2997w(0) AND wire_nliOi_w_lg_nlli1O2998w(0)) AND wire_nliOi_w_lg_nlli1l3000w(0)) AND wire_nliOi_w_lg_nlli1i2990w(0)) AND wire_nliOi_w_lg_nll0OO3003w(0)); + niOi0i <= '1'; + niOi0O <= (nll OR ((wire_nliil_dataout AND wire_nillO_dataout) AND (niOiii2 XOR niOiii1))); + prbs_done <= nli0ll; + prbs_err <= (nli0ii OR (nli0iO OR nli0il)); + prbs_err_lt <= nli00O; + verify_on <= nli0li; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nillOi49 <= nillOi50; + END IF; + if (now = 0 ns) then + nillOi49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nillOi50 <= nillOi49; + END IF; + END PROCESS; + wire_nillOi50_w_lg_w_lg_q242w243w(0) <= wire_nillOi50_w_lg_q242w(0) AND nliOl; + wire_nillOi50_w_lg_q242w(0) <= nillOi50 XOR nillOi49; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nillOl47 <= nillOl48; + END IF; + if (now = 0 ns) then + nillOl47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nillOl48 <= nillOl47; + END IF; + END PROCESS; + wire_nillOl48_w_lg_w_lg_q239w240w(0) <= wire_nillOl48_w_lg_q239w(0) AND nlilO; + wire_nillOl48_w_lg_q239w(0) <= nillOl48 XOR nillOl47; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nillOO45 <= nillOO46; + END IF; + if (now = 0 ns) then + nillOO45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nillOO46 <= nillOO45; + END IF; + END PROCESS; + wire_nillOO46_w_lg_w_lg_q235w236w(0) <= wire_nillOO46_w_lg_q235w(0) AND nlili; + wire_nillOO46_w_lg_q235w(0) <= nillOO46 XOR nillOO45; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nilO1i43 <= nilO1i44; + END IF; + if (now = 0 ns) then + nilO1i43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nilO1i44 <= nilO1i43; + END IF; + END PROCESS; + wire_nilO1i44_w_lg_w_lg_q229w230w(0) <= wire_nilO1i44_w_lg_q229w(0) AND wire_w_lg_nilOOl185w(0); + wire_nilO1i44_w_lg_q229w(0) <= nilO1i44 XOR nilO1i43; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nilO1O41 <= nilO1O42; + END IF; + if (now = 0 ns) then + nilO1O41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nilO1O42 <= nilO1O41; + END IF; + END PROCESS; + wire_nilO1O42_w_lg_w_lg_q221w223w(0) <= wire_nilO1O42_w_lg_q221w(0) AND wire_w_lg_nilOOO222w(0); + wire_nilO1O42_w_lg_q221w(0) <= nilO1O42 XOR nilO1O41; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nilOiO39 <= nilOiO40; + END IF; + if (now = 0 ns) then + nilOiO39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN nilOiO40 <= nilOiO39; + END IF; + END PROCESS; + wire_nilOiO40_w_lg_w_lg_q187w189w(0) <= wire_nilOiO40_w_lg_q187w(0) AND wire_w_lg_nilOli188w(0); + wire_nilOiO40_w_lg_q187w(0) <= nilOiO40 XOR nilOiO39; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO00i21 <= niO00i22; + END IF; + if (now = 0 ns) then + niO00i21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO00i22 <= niO00i21; + END IF; + END PROCESS; + wire_niO00i22_w_lg_q110w(0) <= niO00i22 XOR niO00i21; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO01l23 <= niO01l24; + END IF; + if (now = 0 ns) then + niO01l23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO01l24 <= niO01l23; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0iO19 <= niO0iO20; + END IF; + if (now = 0 ns) then + niO0iO19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0iO20 <= niO0iO19; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0ll17 <= niO0ll18; + END IF; + if (now = 0 ns) then + niO0ll17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0ll18 <= niO0ll17; + END IF; + END PROCESS; + wire_niO0ll18_w_lg_w_lg_q97w98w(0) <= wire_niO0ll18_w_lg_q97w(0) AND nl0O; + wire_niO0ll18_w_lg_q97w(0) <= niO0ll18 XOR niO0ll17; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0lO15 <= niO0lO16; + END IF; + if (now = 0 ns) then + niO0lO15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0lO16 <= niO0lO15; + END IF; + END PROCESS; + wire_niO0lO16_w_lg_w_lg_q91w92w(0) <= wire_niO0lO16_w_lg_q91w(0) AND nl1l; + wire_niO0lO16_w_lg_q91w(0) <= niO0lO16 XOR niO0lO15; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0Oi13 <= niO0Oi14; + END IF; + if (now = 0 ns) then + niO0Oi13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0Oi14 <= niO0Oi13; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0OO11 <= niO0OO12; + END IF; + if (now = 0 ns) then + niO0OO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO0OO12 <= niO0OO11; + END IF; + END PROCESS; + wire_niO0OO12_w_lg_w_lg_q32w33w(0) <= wire_niO0OO12_w_lg_q32w(0) AND nlil; + wire_niO0OO12_w_lg_q32w(0) <= niO0OO12 XOR niO0OO11; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO10i35 <= niO10i36; + END IF; + if (now = 0 ns) then + niO10i35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO10i36 <= niO10i35; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO10l33 <= niO10l34; + END IF; + if (now = 0 ns) then + niO10l33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO10l34 <= niO10l33; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO11i37 <= niO11i38; + END IF; + if (now = 0 ns) then + niO11i37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO11i38 <= niO11i37; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1li31 <= niO1li32; + END IF; + if (now = 0 ns) then + niO1li31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1li32 <= niO1li31; + END IF; + END PROCESS; + wire_niO1li32_w_lg_w_lg_q159w160w(0) <= wire_niO1li32_w_lg_q159w(0) AND wire_n0OO_dataout; + wire_niO1li32_w_lg_q159w(0) <= niO1li32 XOR niO1li31; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1ll29 <= niO1ll30; + END IF; + if (now = 0 ns) then + niO1ll29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1ll30 <= niO1ll29; + END IF; + END PROCESS; + wire_niO1ll30_w_lg_w_lg_q142w143w(0) <= wire_niO1ll30_w_lg_q142w(0) AND niOi; + wire_niO1ll30_w_lg_q142w(0) <= niO1ll30 XOR niO1ll29; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1lO27 <= niO1lO28; + END IF; + if (now = 0 ns) then + niO1lO27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1lO28 <= niO1lO27; + END IF; + END PROCESS; + wire_niO1lO28_w_lg_w_lg_q138w139w(0) <= wire_niO1lO28_w_lg_q138w(0) AND nlliO; + wire_niO1lO28_w_lg_q138w(0) <= niO1lO28 XOR niO1lO27; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1Ol25 <= niO1Ol26; + END IF; + if (now = 0 ns) then + niO1Ol25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niO1Ol26 <= niO1Ol25; + END IF; + END PROCESS; + wire_niO1Ol26_w_lg_w_lg_q125w126w(0) <= wire_niO1Ol26_w_lg_q125w(0) AND wire_ni1l_dataout; + wire_niO1Ol26_w_lg_q125w(0) <= niO1Ol26 XOR niO1Ol25; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi0l3 <= niOi0l4; + END IF; + if (now = 0 ns) then + niOi0l3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi0l4 <= niOi0l3; + END IF; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi1i10 <= niOi1i9; + END IF; + END PROCESS; + wire_niOi1i10_w_lg_w_lg_q28w29w(0) <= wire_niOi1i10_w_lg_q28w(0) AND nl0O; + wire_niOi1i10_w_lg_q28w(0) <= niOi1i10 XOR niOi1i9; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi1i9 <= niOi1i10; + END IF; + if (now = 0 ns) then + niOi1i9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi1l7 <= niOi1l8; + END IF; + if (now = 0 ns) then + niOi1l7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi1l8 <= niOi1l7; + END IF; + END PROCESS; + wire_niOi1l8_w_lg_w_lg_q25w26w(0) <= wire_niOi1l8_w_lg_q25w(0) AND nl0l; + wire_niOi1l8_w_lg_q25w(0) <= niOi1l8 XOR niOi1l7; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi1O5 <= niOi1O6; + END IF; + if (now = 0 ns) then + niOi1O5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOi1O6 <= niOi1O5; + END IF; + END PROCESS; + wire_niOi1O6_w_lg_w_lg_q20w21w(0) <= wire_niOi1O6_w_lg_q20w(0) AND nl1l; + wire_niOi1O6_w_lg_q20w(0) <= niOi1O6 XOR niOi1O5; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOiii1 <= niOiii2; + END IF; + if (now = 0 ns) then + niOiii1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk) + BEGIN + IF (rcvd_clk = '1' AND rcvd_clk'event) THEN niOiii2 <= niOiii1; + END IF; + END PROCESS; + PROCESS (rcvd_clk, wire_ni_CLRN) + BEGIN + IF (wire_ni_CLRN = '0') THEN + n0i <= '0'; + n0l <= '0'; + n0O <= '0'; + nii <= '0'; + nil <= '0'; + niO <= '0'; + nl <= '0'; + nl0i <= '0'; + nl0l <= '0'; + nl0O <= '0'; + nl1i <= '0'; + nl1l <= '0'; + nl1O <= '0'; + nli <= '0'; + nlii <= '0'; + nlil <= '0'; + nliO <= '0'; + nll <= '0'; + nlO <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + n0i <= data_in(1); + n0l <= data_in(2); + n0O <= data_in(3); + nii <= data_in(4); + nil <= data_in(5); + niO <= data_in(6); + nl <= cid_en; + nl0i <= wire_nlOi_dataout; + nl0l <= wire_nlOl_dataout; + nl0O <= wire_nlOO_dataout; + nl1i <= wire_nlli_dataout; + nl1l <= wire_nlll_dataout; + nl1O <= wire_nllO_dataout; + nli <= data_in(7); + nlii <= wire_n1i_dataout; + nlil <= wire_n1l_dataout; + nliO <= data_in(0); + nll <= niOi0O; + nlO <= nl; + END IF; + END PROCESS; + wire_ni_CLRN <= ((niOi0l4 XOR niOi0l3) AND wire_w_lg_soft_reset7w(0)); + wire_ni_w_lg_w_lg_w_lg_nlO108w111w112w(0) <= wire_ni_w_lg_w_lg_nlO108w111w(0) AND niO0il; + wire_ni_w_lg_w_lg_nlO108w111w(0) <= wire_ni_w_lg_nlO108w(0) AND wire_niO00i22_w_lg_q110w(0); + wire_ni_w_lg_nlO108w(0) <= nlO AND niO00O; + wire_ni_w_lg_nl0i2979w(0) <= NOT nl0i; + wire_ni_w_lg_nl0l2977w(0) <= NOT nl0l; + wire_ni_w_lg_nl0O2975w(0) <= NOT nl0O; + wire_ni_w_lg_nl1l2983w(0) <= NOT nl1l; + wire_ni_w_lg_nl1O2981w(0) <= NOT nl1O; + wire_ni_w_lg_nlii2973w(0) <= NOT nlii; + wire_ni_w_lg_nlil2972w(0) <= NOT nlil; + wire_ni_w_lg_nll2606w(0) <= NOT nll; + PROCESS (rcvd_clk, wire_nilO_PRN, soft_reset) + BEGIN + IF (wire_nilO_PRN = '0') THEN + niOi <= '1'; + nlliO <= '1'; + ELSIF (soft_reset = '1') THEN + niOi <= '0'; + nlliO <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + IF (niO0Ol = '1') THEN + niOi <= wire_n0Oi_o; + nlliO <= wire_n0lO_o; + END IF; + END IF; + END PROCESS; + wire_nilO_PRN <= (niO0Oi14 XOR niO0Oi13); + PROCESS (rcvd_clk, soft_reset) + BEGIN + IF (soft_reset = '1') THEN + niOO <= '1'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + IF (niO0Ol = '1') THEN + niOO <= wire_n0Ol_o; + END IF; + END IF; + if (now = 0 ns) then + niOO <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (rcvd_clk, wire_nll0O_dataout, wire_nliOi_CLRN) + BEGIN + IF (wire_nll0O_dataout = '1') THEN + nli0lO <= '1'; + nlii0O <= '1'; + nliOl <= '1'; + nll0il <= '1'; + nll0iO <= '1'; + nll0li <= '1'; + nll0ll <= '1'; + nll0lO <= '1'; + nll0Oi <= '1'; + nll0Ol <= '1'; + nll0OO <= '1'; + nlli0i <= '1'; + nlli0l <= '1'; + nlli0O <= '1'; + nlli1i <= '1'; + nlli1l <= '1'; + nlli1O <= '1'; + nlliii <= '1'; + nlliil <= '1'; + nlliiO <= '1'; + nllili <= '1'; + nllill <= '1'; + nllilO <= '1'; + nlliOi <= '1'; + nlliOl <= '1'; + nlliOO <= '1'; + nlll0i <= '1'; + nlll0l <= '1'; + nlll0O <= '1'; + nlll1i <= '1'; + nlll1l <= '1'; + nlll1O <= '1'; + nlllii <= '1'; + ELSIF (wire_nliOi_CLRN = '0') THEN + nli0lO <= '0'; + nlii0O <= '0'; + nliOl <= '0'; + nll0il <= '0'; + nll0iO <= '0'; + nll0li <= '0'; + nll0ll <= '0'; + nll0lO <= '0'; + nll0Oi <= '0'; + nll0Ol <= '0'; + nll0OO <= '0'; + nlli0i <= '0'; + nlli0l <= '0'; + nlli0O <= '0'; + nlli1i <= '0'; + nlli1l <= '0'; + nlli1O <= '0'; + nlliii <= '0'; + nlliil <= '0'; + nlliiO <= '0'; + nllili <= '0'; + nllill <= '0'; + nllilO <= '0'; + nlliOi <= '0'; + nlliOl <= '0'; + nlliOO <= '0'; + nlll0i <= '0'; + nlll0l <= '0'; + nlll0O <= '0'; + nlll1i <= '0'; + nlll1l <= '0'; + nlll1O <= '0'; + nlllii <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + nli0lO <= wire_nllliO_dataout; + nlii0O <= wire_nli0Oi_dataout; + nliOl <= wire_niO0i_dataout; + nll0il <= wire_nlllli_dataout; + nll0iO <= wire_nlllll_dataout; + nll0li <= wire_nllllO_dataout; + nll0ll <= wire_nlllOi_dataout; + nll0lO <= wire_nlllOl_dataout; + nll0Oi <= wire_nlllOO_dataout; + nll0Ol <= wire_nllO1i_dataout; + nll0OO <= wire_nllO1l_dataout; + nlli0i <= wire_nllO0O_dataout; + nlli0l <= wire_nllOii_dataout; + nlli0O <= wire_nllOil_dataout; + nlli1i <= wire_nllO1O_dataout; + nlli1l <= wire_nllO0i_dataout; + nlli1O <= wire_nllO0l_dataout; + nlliii <= wire_nllOiO_dataout; + nlliil <= wire_nllOli_dataout; + nlliiO <= wire_nllOll_dataout; + nllili <= wire_nllOlO_dataout; + nllill <= wire_nllOOi_dataout; + nllilO <= wire_nllOOl_dataout; + nlliOi <= wire_nllOOO_dataout; + nlliOl <= wire_nlO11i_dataout; + nlliOO <= wire_nlO11l_dataout; + nlll0i <= wire_nlO10O_dataout; + nlll0l <= wire_nlO1ii_dataout; + nlll0O <= wire_nlO1il_dataout; + nlll1i <= wire_nlO11O_dataout; + nlll1l <= wire_nlO10i_dataout; + nlll1O <= wire_nlO10l_dataout; + nlllii <= wire_nlO1iO_dataout; + END IF; + if (now = 0 ns) then + nli0lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlii0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0li <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0ll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllili <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllill <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlllii <= '1' after 1 ps; + end if; + END PROCESS; + wire_nliOi_CLRN <= (niO11i38 XOR niO11i37); + wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3441w3442w3443w3444w3445w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w3441w3442w3443w3444w(0) AND nlli0O; + wire_nliOi_w_lg_w_lg_w_lg_w3441w3442w3443w3444w(0) <= wire_nliOi_w_lg_w_lg_w3441w3442w3443w(0) AND wire_nliOi_w_lg_nlliii2993w(0); + wire_nliOi_w_lg_w_lg_w3441w3442w3443w(0) <= wire_nliOi_w_lg_w3441w3442w(0) AND wire_nliOi_w_lg_nlliil3354w(0); + wire_nliOi_w_lg_w3441w3442w(0) <= wire_nliOi_w3441w(0) AND wire_nliOi_w_lg_nlliiO3302w(0); + wire_nliOi_w3357w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3350w3352w3353w3355w3356w(0) AND nlli0O; + wire_nliOi_w3441w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3436w3437w3438w3439w3440w(0) AND wire_nliOi_w_lg_nllili3351w(0); + wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3350w3352w3353w3355w3356w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w3350w3352w3353w3355w(0) AND wire_nliOi_w_lg_nlliii2993w(0); + wire_nliOi_w_lg_w_lg_w_lg_w_lg_w3436w3437w3438w3439w3440w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w3436w3437w3438w3439w(0) AND wire_nliOi_w_lg_nllill3349w(0); + wire_nliOi_w_lg_w_lg_w_lg_w3306w3307w3308w3309w(0) <= wire_nliOi_w_lg_w_lg_w3306w3307w3308w(0) AND nlli1l; + wire_nliOi_w_lg_w_lg_w_lg_w3350w3352w3353w3355w(0) <= wire_nliOi_w_lg_w_lg_w3350w3352w3353w(0) AND wire_nliOi_w_lg_nlliil3354w(0); + wire_nliOi_w_lg_w_lg_w_lg_w3436w3437w3438w3439w(0) <= wire_nliOi_w_lg_w_lg_w3436w3437w3438w(0) AND nllilO; + wire_nliOi_w_lg_w_lg_w3306w3307w3308w(0) <= wire_nliOi_w_lg_w3306w3307w(0) AND nlli1O; + wire_nliOi_w_lg_w_lg_w3350w3352w3353w(0) <= wire_nliOi_w_lg_w3350w3352w(0) AND wire_nliOi_w_lg_nlliiO3302w(0); + wire_nliOi_w_lg_w_lg_w3436w3437w3438w(0) <= wire_nliOi_w_lg_w3436w3437w(0) AND nlliOi; + wire_nliOi_w_lg_w3306w3307w(0) <= wire_nliOi_w3306w(0) AND nlli0i; + wire_nliOi_w_lg_w3350w3352w(0) <= wire_nliOi_w3350w(0) AND wire_nliOi_w_lg_nllili3351w(0); + wire_nliOi_w_lg_w3436w3437w(0) <= wire_nliOi_w3436w(0) AND wire_nliOi_w_lg_nlliOl3345w(0); + wire_nliOi_w3219w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3215w3216w3217w3218w(0) AND nll0iO; + wire_nliOi_w2989w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliii2965w2966w2987w2988w(0) AND nlli1l; + wire_nliOi_w3306w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliiO3302w3303w3304w3305w(0) AND nlli0l; + wire_nliOi_w3350w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliOO3344w3346w3347w3348w(0) AND wire_nliOi_w_lg_nllill3349w(0); + wire_nliOi_w3436w(0) <= wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlll0i3430w3431w3433w3435w(0) AND wire_nliOi_w_lg_nlliOO3344w(0); + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3215w3222w3223w3224w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3215w3222w3223w(0) AND nll0li; + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3215w3216w3217w3218w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3215w3216w3217w(0) AND wire_nliOi_w_lg_nll0li3207w(0); + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliii2965w2966w2987w2988w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nlliii2965w2966w2987w(0) AND nlli1O; + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nll0Ol3202w3203w3205w3206w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3202w3203w3205w(0) AND nll0ll; + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliii2993w2994w2996w2997w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nlliii2993w2994w2996w(0) AND nlli0i; + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliiO3302w3303w3304w3305w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nlliiO3302w3303w3304w(0) AND nlli0O; + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlliOO3344w3346w3347w3348w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nlliOO3344w3346w3347w(0) AND nllilO; + wire_nliOi_w_lg_w_lg_w_lg_w_lg_nlll0i3430w3431w3433w3435w(0) <= wire_nliOi_w_lg_w_lg_w_lg_nlll0i3430w3431w3433w(0) AND wire_nliOi_w_lg_nlll1i3434w(0); + wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3215w3222w3223w(0) <= wire_nliOi_w_lg_w_lg_nll0Ol3215w3222w(0) AND nll0ll; + wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3215w3216w3217w(0) <= wire_nliOi_w_lg_w_lg_nll0Ol3215w3216w(0) AND nll0ll; + wire_nliOi_w_lg_w_lg_w_lg_nlliii2965w2966w2987w(0) <= wire_nliOi_w_lg_w_lg_nlliii2965w2966w(0) AND wire_nliOi_w_lg_nlli0i2986w(0); + wire_nliOi_w_lg_w_lg_w_lg_nll0Ol3202w3203w3205w(0) <= wire_nliOi_w_lg_w_lg_nll0Ol3202w3203w(0) AND wire_nliOi_w_lg_nll0lO3204w(0); + wire_nliOi_w_lg_w_lg_w_lg_nlliii2993w2994w2996w(0) <= wire_nliOi_w_lg_w_lg_nlliii2993w2994w(0) AND wire_nliOi_w_lg_nlli0l2995w(0); + wire_nliOi_w_lg_w_lg_w_lg_nlliiO3302w3303w3304w(0) <= wire_nliOi_w_lg_w_lg_nlliiO3302w3303w(0) AND wire_nliOi_w_lg_nlliii2993w(0); + wire_nliOi_w_lg_w_lg_w_lg_nlliOO3344w3346w3347w(0) <= wire_nliOi_w_lg_w_lg_nlliOO3344w3346w(0) AND nlliOi; + wire_nliOi_w_lg_w_lg_w_lg_nlll0i3430w3431w3433w(0) <= wire_nliOi_w_lg_w_lg_nlll0i3430w3431w(0) AND wire_nliOi_w_lg_nlll1l3432w(0); + wire_nliOi_w_lg_w_lg_nll0Ol3215w3222w(0) <= wire_nliOi_w_lg_nll0Ol3215w(0) AND wire_nliOi_w_lg_nll0lO3204w(0); + wire_nliOi_w_lg_w_lg_nll0Ol3215w3216w(0) <= wire_nliOi_w_lg_nll0Ol3215w(0) AND nll0lO; + wire_nliOi_w_lg_w_lg_nlliii2965w2966w(0) <= wire_nliOi_w_lg_nlliii2965w(0) AND nlli0l; + wire_nliOi_w_lg_w_lg_nll0Ol3202w3203w(0) <= wire_nliOi_w_lg_nll0Ol3202w(0) AND nll0Oi; + wire_nliOi_w_lg_w_lg_nlliii2993w2994w(0) <= wire_nliOi_w_lg_nlliii2993w(0) AND nlli0O; + wire_nliOi_w_lg_w_lg_nlliiO3302w3303w(0) <= wire_nliOi_w_lg_nlliiO3302w(0) AND nlliil; + wire_nliOi_w_lg_w_lg_nlliOO3344w3346w(0) <= wire_nliOi_w_lg_nlliOO3344w(0) AND wire_nliOi_w_lg_nlliOl3345w(0); + wire_nliOi_w_lg_w_lg_nlll0i3430w3431w(0) <= wire_nliOi_w_lg_nlll0i3430w(0) AND nlll1O; + wire_nliOi_w_lg_nlii0O2954w(0) <= nlii0O AND wire_w_lg_niil0O2953w(0); + wire_nliOi_w_lg_nlii0O2944w(0) <= nlii0O AND wire_w_lg_niilii2943w(0); + wire_nliOi_w_lg_nll0Ol3215w(0) <= nll0Ol AND nll0Oi; + wire_nliOi_w_lg_nlliii2965w(0) <= nlliii AND nlli0O; + wire_nliOi_w_lg_nli0lO3213w(0) <= NOT nli0lO; + wire_nliOi_w_lg_nll0il3211w(0) <= NOT nll0il; + wire_nliOi_w_lg_nll0iO3209w(0) <= NOT nll0iO; + wire_nliOi_w_lg_nll0li3207w(0) <= NOT nll0li; + wire_nliOi_w_lg_nll0lO3204w(0) <= NOT nll0lO; + wire_nliOi_w_lg_nll0Ol3202w(0) <= NOT nll0Ol; + wire_nliOi_w_lg_nll0OO3003w(0) <= NOT nll0OO; + wire_nliOi_w_lg_nlli0i2986w(0) <= NOT nlli0i; + wire_nliOi_w_lg_nlli0l2995w(0) <= NOT nlli0l; + wire_nliOi_w_lg_nlli1i2990w(0) <= NOT nlli1i; + wire_nliOi_w_lg_nlli1l3000w(0) <= NOT nlli1l; + wire_nliOi_w_lg_nlli1O2998w(0) <= NOT nlli1O; + wire_nliOi_w_lg_nlliii2993w(0) <= NOT nlliii; + wire_nliOi_w_lg_nlliil3354w(0) <= NOT nlliil; + wire_nliOi_w_lg_nlliiO3302w(0) <= NOT nlliiO; + wire_nliOi_w_lg_nllili3351w(0) <= NOT nllili; + wire_nliOi_w_lg_nllill3349w(0) <= NOT nllill; + wire_nliOi_w_lg_nlliOl3345w(0) <= NOT nlliOl; + wire_nliOi_w_lg_nlliOO3344w(0) <= NOT nlliOO; + wire_nliOi_w_lg_nlll0i3430w(0) <= NOT nlll0i; + wire_nliOi_w_lg_nlll1i3434w(0) <= NOT nlll1i; + wire_nliOi_w_lg_nlll1l3432w(0) <= NOT nlll1l; + wire_nliOi_w_lg_w_lg_nlliii2127w2128w(0) <= wire_nliOi_w_lg_nlliii2127w(0) XOR nlli1l; + wire_nliOi_w_lg_w_lg_nlliOl1740w1741w(0) <= wire_nliOi_w_lg_nlliOl1740w(0) XOR nlliiO; + wire_nliOi_w_lg_w_lg_nlliOO1669w1670w(0) <= wire_nliOi_w_lg_nlliOO1669w(0) XOR nllili; + wire_nliOi_w_lg_w_lg_nlll0i1685w1686w(0) <= wire_nliOi_w_lg_nlll0i1685w(0) XOR nlliOl; + wire_nliOi_w_lg_w_lg_nlll1i2573w2574w(0) <= wire_nliOi_w_lg_nlll1i2573w(0) XOR nlll0O; + wire_nliOi_w_lg_w_lg_nlll1l2504w2505w(0) <= wire_nliOi_w_lg_nlll1l2504w(0) XOR nlllii; + wire_nliOi_w_lg_w_lg_nlll1O1756w1757w(0) <= wire_nliOi_w_lg_nlll1O1756w(0) XOR nlliOi; + wire_nliOi_w_lg_nlli0l2436w(0) <= nlli0l XOR nll0OO; + wire_nliOi_w_lg_nlli0O2370w(0) <= nlli0O XOR nlli1i; + wire_nliOi_w_lg_nlli0O2339w(0) <= nlli0O XOR nlli1O; + wire_nliOi_w_lg_nlli1l2531w(0) <= nlli1l XOR nlli1i; + wire_nliOi_w_lg_nlli1O2059w(0) <= nlli1O XOR nlli1i; + wire_nliOi_w_lg_nlli1O2462w(0) <= nlli1O XOR nlli1l; + wire_nliOi_w_lg_nlliii2273w(0) <= nlliii XOR nlli0i; + wire_nliOi_w_lg_nlliii2127w(0) <= nlliii XOR nlli1i; + wire_nliOi_w_lg_nlliil2207w(0) <= nlliil XOR nlli0l; + wire_nliOi_w_lg_nlliiO2139w(0) <= nlliiO XOR nlli0O; + wire_nliOi_w_lg_nllili2557w(0) <= nllili XOR nlliiO; + wire_nliOi_w_lg_nllill2086w(0) <= nllill XOR nlliiO; + wire_nliOi_w_lg_nllill2488w(0) <= nllill XOR nllili; + wire_nliOi_w_lg_nllilO2017w(0) <= nllilO XOR nllili; + wire_nliOi_w_lg_nlliOi1948w(0) <= nlliOi XOR nllill; + wire_nliOi_w_lg_nlliOl1740w(0) <= nlliOl XOR nllili; + wire_nliOi_w_lg_nlliOl1879w(0) <= nlliOl XOR nllilO; + wire_nliOi_w_lg_nlliOO1669w(0) <= nlliOO XOR nllill; + wire_nliOi_w_lg_nlll0i1685w(0) <= nlll0i XOR nlliOO; + wire_nliOi_w_lg_nlll0i1825w(0) <= nlll0i XOR nlll1l; + wire_nliOi_w_lg_nlll1i2573w(0) <= nlll1i XOR nlli1O; + wire_nliOi_w_lg_nlll1i2032w(0) <= nlll1i XOR nlliOl; + wire_nliOi_w_lg_nlll1l2504w(0) <= nlll1l XOR nlli0i; + wire_nliOi_w_lg_nlll1l1963w(0) <= nlll1l XOR nlliOO; + wire_nliOi_w_lg_nlll1O1756w(0) <= nlll1O XOR nlliOl; + wire_nliOi_w_lg_nlll1O1894w(0) <= nlll1O XOR nlll1i; + PROCESS (rcvd_clk, wire_nll0O_dataout) + BEGIN + IF (wire_nll0O_dataout = '1') THEN + nli00O <= '0'; + nli0ii <= '0'; + nli0il <= '0'; + nli0iO <= '0'; + nli0li <= '0'; + nli0ll <= '0'; + nliiO <= '0'; + nlili <= '0'; + nlill <= '0'; + nlilO <= '0'; + nliOO <= '0'; + nll0i <= '0'; + nll1i <= '0'; + nll1l <= '0'; + nlllil <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + nli00O <= wire_nli0Ol_dataout; + nli0ii <= nli0il; + nli0il <= nli0iO; + nli0iO <= wire_nli0OO_dataout; + nli0li <= wire_nlii1l_dataout; + nli0ll <= wire_nlii1i_dataout; + nliiO <= wire_nilOO_dataout; + nlili <= wire_niO1i_dataout; + nlill <= wire_niO1l_dataout; + nlilO <= wire_niO1O_dataout; + nliOO <= niO11l; + nll0i <= rprbs_en_rx; + nll1i <= niO11O; + nll1l <= nll0i; + nlllil <= wire_nilOl_dataout; + END IF; + END PROCESS; + wire_nll1O_w_lg_nli0li2861w(0) <= nli0li AND niil0i; + wire_nll1O_w_lg_nli0li2856w(0) <= nli0li AND niil0l; + wire_nll1O_w_lg_nli0li2902w(0) <= nli0li AND niil1l; + wire_nll1O_w_lg_nli0li2886w(0) <= nli0li AND niil1O; + wire_nll1O_w_lg_nli0li2589w(0) <= NOT nli0li; + wire_nll1O_w_lg_nll1l2599w(0) <= NOT nll1l; + wire_nll1O_w_lg_w_lg_nli0li2856w2857w(0) <= wire_nll1O_w_lg_nli0li2856w(0) OR nli0ll; + wire_nll1O_w_lg_w_lg_nli0li2902w2903w(0) <= wire_nll1O_w_lg_nli0li2902w(0) OR nli0ll; + wire_nll1O_w_lg_w_lg_nli0li2886w2887w(0) <= wire_nll1O_w_lg_nli0li2886w(0) OR nli0ll; + PROCESS (rcvd_clk, wire_nllii_PRN, wire_nllii_CLRN) + BEGIN + IF (wire_nllii_PRN = '0') THEN + nll0l <= '1'; + nllil <= '1'; + ELSIF (wire_nllii_CLRN = '0') THEN + nll0l <= '0'; + nllil <= '0'; + ELSIF (rcvd_clk = '1' AND rcvd_clk'event) THEN + nll0l <= nllil; + nllil <= niO10O; + END IF; + if (now = 0 ns) then + nll0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllil <= '1' after 1 ps; + end if; + END PROCESS; + wire_nllii_CLRN <= (niO10l34 XOR niO10l33); + wire_nllii_PRN <= ((niO10i36 XOR niO10i35) AND wire_w_lg_soft_reset7w(0)); + wire_n00i_dataout <= nlll0i AND niO1iO; + wire_n00l_dataout <= nlll1O AND niO1iO; + wire_n00O_dataout <= nlll1l AND niO1iO; + wire_n01i_dataout <= nlllii AND niO1iO; + wire_n01l_dataout <= nlll0O AND niO1iO; + wire_n01O_dataout <= nlll0l AND niO1iO; + wire_n0i0l_dataout <= wire_n0iOi_dataout AND NOT(wire_n0li_dataout); + wire_n0i0O_dataout <= wire_n0iOl_dataout OR wire_n0li_dataout; + wire_n0ii_dataout <= nlll1i AND niO1iO; + wire_n0iii_dataout <= wire_n0iOO_dataout AND NOT(wire_n0li_dataout); + wire_n0iil_dataout <= wire_n0l1i_dataout OR wire_n0li_dataout; + wire_n0iiO_dataout <= wire_n0l1l_dataout OR wire_n0li_dataout; + wire_n0il_dataout <= nlliOO AND niO1iO; + wire_n0ili_dataout <= wire_n0l1O_dataout AND NOT(wire_n0li_dataout); + wire_n0ill_dataout <= wire_n0l0i_dataout OR wire_n0li_dataout; + wire_n0ilO_dataout <= wire_n0l0l_dataout AND NOT(wire_n0li_dataout); + wire_n0iO_dataout <= wire_n0ll_o AND niO0Ol; + wire_n0iOi_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nll0OO; + wire_n0iOl_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nlli1i; + wire_n0iOO_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nlli1l; + wire_n0l0i_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nlli0O; + wire_n0l0l_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nlliii; + wire_n0l0O_dataout <= nll0OO WHEN niliil = '1' ELSE ((nili0O XOR nlli1i) XOR nll0OO); + wire_n0l1i_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nlli1O; + wire_n0l1l_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nlli0i; + wire_n0l1O_dataout <= rcid_pattern WHEN wire_n0iO_dataout = '1' ELSE nlli0l; + wire_n0li_dataout <= niOO AND niO0Ol; + wire_n0lii_dataout <= nlli1i WHEN niliil = '1' ELSE ((niliii XOR nlli1l) XOR nlli1i); + wire_n0lil_dataout <= nlli1l WHEN niliil = '1' ELSE (((((niliii XOR nlli0l) XOR nlli1O) XOR nlli1l) XOR nlli1i) XOR nll0OO); + wire_n0liO_dataout <= nlli1O WHEN niliil = '1' ELSE (((((nlliii XOR nlli0l) XOR nlli0i) XOR nlli1O) XOR nlli1l) XOR nll0OO); + wire_n0lli_dataout <= nlli0i WHEN niliil = '1' ELSE (nili0i XOR nll0OO); + wire_n0lll_dataout <= nlli0l WHEN niliil = '1' ELSE (nili0l XOR nlli1i); + wire_n0llO_dataout <= nlli0O WHEN niliil = '1' ELSE (nili0O XOR nlli1l); + wire_n0lOi_dataout <= nlliii WHEN niliil = '1' ELSE (niliii XOR nlli1O); + wire_n0lOl_dataout <= nlliil OR NOT(niliil); + wire_n0lOO_dataout <= nlliiO OR NOT(niliil); + wire_n0O0i_dataout <= nlliOi OR NOT(niliil); + wire_n0O0l_dataout <= nlliOl OR NOT(niliil); + wire_n0O0O_dataout <= nlliOO OR NOT(niliil); + wire_n0O1i_dataout <= nllili OR NOT(niliil); + wire_n0O1l_dataout <= nllill OR NOT(niliil); + wire_n0O1O_dataout <= nllilO OR NOT(niliil); + wire_n0Oii_dataout <= nlll1i OR NOT(niliil); + wire_n0Oil_dataout <= nlll1l OR NOT(niliil); + wire_n0OiO_dataout <= nlll1O OR NOT(niliil); + wire_n0Oli_dataout <= nlll0i OR NOT(niliil); + wire_n0Oll_dataout <= nlll0l OR NOT(niliil); + wire_n0OlO_dataout <= nlll0O OR NOT(niliil); + wire_n0OO_dataout <= niO01i OR niO0ii; + wire_n0OOi_dataout <= nlllii OR NOT(niliil); + wire_n10i_dataout <= nlll1O WHEN niO1il = '1' ELSE wire_n00l_dataout; + wire_n10l_dataout <= nlll1l WHEN niO1il = '1' ELSE wire_n00O_dataout; + wire_n10O_dataout <= nlll1i WHEN niO1il = '1' ELSE wire_n0ii_dataout; + wire_n110i_dataout <= wire_n0ilO_dataout WHEN wire_nil0O_o(0) = '1' ELSE nll0Ol; + wire_n111i_dataout <= wire_n0iiO_dataout WHEN wire_nil0O_o(0) = '1' ELSE nll0ll; + wire_n111l_dataout <= wire_n0ili_dataout WHEN wire_nil0O_o(0) = '1' ELSE nll0lO; + wire_n111O_dataout <= wire_n0ill_dataout WHEN wire_nil0O_o(0) = '1' ELSE nll0Oi; + wire_n11i_dataout <= nlll0O WHEN niO1il = '1' ELSE wire_n01l_dataout; + wire_n11l_dataout <= nlll0l WHEN niO1il = '1' ELSE wire_n01O_dataout; + wire_n11O_dataout <= nlll0i WHEN niO1il = '1' ELSE wire_n00i_dataout; + wire_n1i_dataout <= wire_n1O_o(7) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(6); + wire_n1ii_dataout <= nlliOO WHEN niO1il = '1' ELSE wire_n0il_dataout; + wire_n1il_dataout <= nlliOl AND niO1il; + wire_n1iO_dataout <= nlliOi AND niO1il; + wire_n1l_dataout <= wire_n1O_o(8) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(7); + wire_n1li_dataout <= nllilO AND niO1il; + wire_n1ll_dataout <= nllill AND niO1il; + wire_n1lO_dataout <= nllili AND niO1il; + wire_n1Oi_dataout <= nlliiO AND niO1il; + wire_n1Ol_dataout <= nlliil AND niO1il; + wire_n1OO_dataout <= nlliii AND niO1il; + wire_ni0i_dataout <= niO1OO AND NOT(niO01i); + wire_ni0il_dataout <= nli0lO OR NOT(nilill); + wire_ni0li_dataout <= nll0iO OR NOT(nilill); + wire_ni0ll_dataout <= nll0li OR NOT(nilill); + wire_ni0Ol_dataout <= nll0lO OR NOT(nilill); + wire_ni0OO_dataout <= nll0Oi OR NOT(nilill); + wire_ni1i_dataout <= wire_ni1O_dataout AND NOT(niO0ii); + wire_ni1l_dataout <= wire_ni0i_dataout AND NOT(niO0ii); + wire_ni1O_dataout <= wire_w_lg_niO1OO117w(0) OR niO01i; + wire_nii1i_dataout <= nll0Ol OR NOT(nilill); + wire_nilii_dataout <= wire_nilOi_dataout WHEN rall_one_dect_only = '1' ELSE wire_nillO_dataout; + wire_nilii_w_lg_dataout2862w(0) <= wire_nilii_dataout AND wire_nll1O_w_lg_nli0li2861w(0); + wire_nilii_w_lg_dataout2621w(0) <= NOT wire_nilii_dataout; + wire_nilii_w_lg_w_lg_dataout2862w2863w(0) <= wire_nilii_w_lg_dataout2862w(0) OR nli0ll; + wire_nilil_dataout <= (nll1i AND nill0i) WHEN niO1ii = '1' ELSE wire_niliO_dataout; + wire_nilil_w_lg_dataout2635w(0) <= NOT wire_nilil_dataout; + wire_niliO_dataout <= (nliOO AND nill0l) AND niO1il; + wire_nillO_dataout <= nlllil WHEN niO0Ol = '1' ELSE wire_niO0O_dataout; + wire_nilOi_dataout <= wire_nli1i_dataout WHEN niO0Ol = '1' ELSE wire_niO0l_dataout; + wire_nilOl_dataout <= wire_nli1l_dataout WHEN niO0Ol = '1' ELSE wire_niOii_dataout; + wire_nilOO_dataout <= wire_nli1O_dataout WHEN niO0Ol = '1' ELSE wire_niOil_dataout; + wire_niO0i_dataout <= wire_nli0O_o WHEN niO0Ol = '1' ELSE wire_niOlO_dataout; + wire_niO0l_dataout <= wire_niOOl_dataout AND NOT(nill0O); + wire_niO0O_dataout <= nlllil WHEN nill0O = '1' ELSE wire_niOOi_dataout; + wire_niO1i_dataout <= wire_nli0i_dataout WHEN niO0Ol = '1' ELSE wire_niOiO_dataout; + wire_niO1l_dataout <= wire_nli1i_dataout WHEN niO0Ol = '1' ELSE wire_niOli_dataout; + wire_niO1O_dataout <= wire_nli0l_dataout WHEN niO0Ol = '1' ELSE wire_niOll_dataout; + wire_niOii_dataout <= wire_nl0li_dataout WHEN nill0O = '1' ELSE wire_niOOO_dataout; + wire_niOil_dataout <= wire_nl0ll_dataout WHEN nill0O = '1' ELSE wire_nl11i_dataout; + wire_niOiO_dataout <= wire_nl0lO_dataout WHEN nill0O = '1' ELSE wire_nl11l_dataout; + wire_niOli_dataout <= wire_nl0Oi_dataout WHEN nill0O = '1' ELSE wire_nl11O_dataout; + wire_niOll_dataout <= wire_nl0Ol_dataout WHEN nill0O = '1' ELSE wire_nl10i_dataout; + wire_niOlO_dataout <= wire_nl0OO_o WHEN nill0O = '1' ELSE wire_nl10l_dataout; + wire_niOOi_dataout <= nlllil WHEN niO1iO = '1' ELSE wire_nl10O_dataout; + wire_niOOl_dataout <= wire_nl00l_dataout WHEN niO1iO = '1' ELSE wire_nl1ii_dataout; + wire_niOOO_dataout <= wire_nl00O_dataout WHEN niO1iO = '1' ELSE wire_nl1il_dataout; + wire_nl00l_dataout <= nilO1l AND nlill; + wire_nl00O_dataout <= nilOOO AND nliiO; + wire_nl01i_dataout <= nillll AND nlili; + wire_nl01l_dataout <= nillli AND nlill; + wire_nl01O_dataout <= nilliO AND nlilO; + wire_nl0ii_dataout <= nilOOO AND nlili; + wire_nl0il_dataout <= nilOOl AND nliOl; + wire_nl0li_dataout <= nilOil AND nliiO; + wire_nl0ll_dataout <= nilOii AND nlili; + wire_nl0lO_dataout <= nilO0O AND nlill; + wire_nl0Oi_dataout <= nilO0l AND nlilO; + wire_nl0Ol_dataout <= nilO0i AND nliOl; + wire_nl10i_dataout <= wire_nl0il_dataout WHEN niO1iO = '1' ELSE wire_nl1lO_dataout; + wire_nl10l_dataout <= wire_nl0iO_o WHEN niO1iO = '1' ELSE wire_nl1Oi_dataout; + wire_nl10O_dataout <= nlllil AND nillii; + wire_nl11i_dataout <= wire_nl0ii_dataout WHEN niO1iO = '1' ELSE wire_nl1iO_dataout; + wire_nl11l_dataout <= wire_nl00l_dataout WHEN niO1iO = '1' ELSE wire_nl1li_dataout; + wire_nl11O_dataout <= wire_nli1i_dataout WHEN niO1iO = '1' ELSE wire_nl1ll_dataout; + wire_nl1ii_dataout <= wire_nl1Ol_dataout AND nillii; + wire_nl1il_dataout <= wire_nl1OO_dataout WHEN nillii = '1' ELSE nlllil; + wire_nl1iO_dataout <= wire_nl01i_dataout WHEN nillii = '1' ELSE nliiO; + wire_nl1li_dataout <= wire_nl01l_dataout WHEN nillii = '1' ELSE nlili; + wire_nl1ll_dataout <= wire_nl01O_dataout WHEN nillii = '1' ELSE nlill; + wire_nl1lO_dataout <= wire_nl1Ol_dataout WHEN nillii = '1' ELSE nlilO; + wire_nl1Oi_dataout <= wire_nl00i_o WHEN nillii = '1' ELSE nliOl; + wire_nl1Ol_dataout <= nillil AND nliOl; + wire_nl1OO_dataout <= nilllO AND nliiO; + wire_nli0i_dataout <= nilOll AND nlill; + wire_nli0l_dataout <= nilOli AND nliOl; + wire_nli0Oi_dataout <= wire_nlii1O_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nli0Ol_dataout <= wire_nlii0l_dataout AND NOT(wire_nll1O_w_lg_nll1l2599w(0)); + wire_nli0OO_dataout <= wire_nliiii_dataout AND NOT(wire_nll1O_w_lg_nll1l2599w(0)); + wire_nli1i_dataout <= nilOOl AND nlilO; + wire_nli1l_dataout <= nilOOi AND nliiO; + wire_nli1O_dataout <= nilOlO AND nlili; + wire_nlii0i_dataout <= nli0li WHEN rprbs_clr_rslt_rx = '1' ELSE wire_nliiOi_o; + wire_nlii0l_dataout <= wire_nliill_o AND NOT(rprbs_clr_rslt_rx); + wire_nlii1i_dataout <= wire_nliiil_dataout AND NOT(wire_nll1O_w_lg_nll1l2599w(0)); + wire_nlii1l_dataout <= wire_nlii0i_dataout AND NOT(wire_nll1O_w_lg_nll1l2599w(0)); + wire_nlii1O_dataout <= nlii0O WHEN rprbs_clr_rslt_rx = '1' ELSE wire_nliiiO_o; + wire_nliiii_dataout <= wire_nliilO_o AND NOT(rprbs_clr_rslt_rx); + wire_nliiil_dataout <= wire_nliili_o AND NOT(rprbs_clr_rslt_rx); + wire_nliil_dataout <= nilOOl WHEN rcid_pattern = '1' ELSE nilOOO; + wire_nliOil_dataout <= ((nli0li AND niiO0l) OR nli0ll) WHEN rall_one_dect_only = '1' ELSE ((nli0li AND niiO0O) OR nli0ll); + wire_nll01i_dataout <= ((nli0li AND nil11l) OR nli0ll) AND NOT(nil11i); + wire_nll0O_dataout <= nll0l AND NOT(scan_mode); + wire_nll0O_w_lg_dataout167w(0) <= NOT wire_nll0O_dataout; + wire_nll1li_dataout <= wire_nll1OO_dataout WHEN rall_one_dect_only = '1' ELSE wire_nll1ll_dataout; + wire_nll1ll_dataout <= ((nli0li AND niiOOl) OR nli0ll) AND NOT(nil11i); + wire_nll1OO_dataout <= wire_nll01i_dataout WHEN nlO = '1' ELSE ((nli0li AND niiOOO) OR nli0ll); + wire_nlli_dataout <= wire_n1O_o(1) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(0); + wire_nlll_dataout <= wire_n1O_o(2) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(1); + wire_nllli_dataout <= nlllii WHEN niO1ii = '1' ELSE wire_nlOOO_dataout; + wire_nllli_w_lg_dataout3262w(0) <= NOT wire_nllli_dataout; + wire_nllliO_dataout <= wire_nlO1li_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllll_dataout <= nlll0O WHEN niO1ii = '1' ELSE wire_n11i_dataout; + wire_nlllli_dataout <= wire_nlO1ll_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlllll_dataout <= wire_nlO1lO_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllllO_dataout <= wire_nlO1Oi_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlllO_dataout <= nlll0l WHEN niO1ii = '1' ELSE wire_n11l_dataout; + wire_nlllOi_dataout <= wire_nlO1Ol_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlllOl_dataout <= wire_nlO1OO_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlllOO_dataout <= wire_nlO01i_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllO_dataout <= wire_n1O_o(3) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(2); + wire_nllO0i_dataout <= wire_nlO00l_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllO0l_dataout <= wire_nlO00O_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllO0O_dataout <= wire_nlO0ii_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllO1i_dataout <= wire_nlO01l_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllO1l_dataout <= wire_nlO01O_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllO1O_dataout <= wire_nlO00i_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOi_dataout <= nlll0i WHEN niO1ii = '1' ELSE wire_n11O_dataout; + wire_nllOii_dataout <= wire_nlO0il_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOil_dataout <= wire_nlO0iO_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOiO_dataout <= wire_nlO0li_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOl_dataout <= nlll1O WHEN niO1ii = '1' ELSE wire_n10i_dataout; + wire_nllOli_dataout <= wire_nlO0ll_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOll_dataout <= wire_nlO0lO_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOlO_dataout <= wire_nlO0Oi_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOO_dataout <= nlll1l WHEN niO1ii = '1' ELSE wire_n10l_dataout; + wire_nllOOi_dataout <= wire_nlO0Ol_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOOl_dataout <= wire_nlO0OO_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nllOOO_dataout <= wire_nlOi1i_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO00i_dataout <= wire_nii0i_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOl0l_dataout; + wire_nlO00l_dataout <= wire_nii0l_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOl0O_dataout; + wire_nlO00O_dataout <= wire_nii0O_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOlii_dataout; + wire_nlO01i_dataout <= wire_ni0OO_dataout WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOl1l_dataout; + wire_nlO01l_dataout <= wire_nii1i_dataout WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOl1O_dataout; + wire_nlO01O_dataout <= wire_nii1O_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOl0i_dataout; + wire_nlO0i_dataout <= nlliOi WHEN niO1ii = '1' ELSE wire_n1iO_dataout; + wire_nlO0ii_dataout <= wire_niiii_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOlil_dataout; + wire_nlO0il_dataout <= (NOT (((wire_nil0O_o(25) OR wire_nil0O_o(17)) OR wire_nil0O_o(16)) OR wire_nil0O_o(8))) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOliO_dataout; + wire_nlO0iO_dataout <= wire_niiiO_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOlli_dataout; + wire_nlO0l_dataout <= nllilO WHEN niO1ii = '1' ELSE wire_n1li_dataout; + wire_nlO0li_dataout <= (NOT ((wire_nil0O_o(25) OR wire_nil0O_o(17)) OR wire_nil0O_o(16))) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOlll_dataout; + wire_nlO0ll_dataout <= wire_niill_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOllO_dataout; + wire_nlO0lO_dataout <= wire_niilO_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOlOi_dataout; + wire_nlO0O_dataout <= nllill WHEN niO1ii = '1' ELSE wire_n1ll_dataout; + wire_nlO0Oi_dataout <= (NOT (((wire_nil0O_o(25) OR wire_nil0O_o(8)) OR wire_nil0O_o(2)) OR wire_nil0O_o(0))) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOlOl_dataout; + wire_nlO0Ol_dataout <= wire_w_lg_nililO2595w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOlOO_dataout; + wire_nlO0OO_dataout <= wire_w_lg_niliOi2594w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOO1i_dataout; + wire_nlO10i_dataout <= wire_nlOi0l_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO10l_dataout <= wire_nlOi0O_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO10O_dataout <= wire_nlOiii_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO11i_dataout <= wire_nlOi1l_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO11l_dataout <= wire_nlOi1O_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO11O_dataout <= wire_nlOi0i_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO1i_dataout <= nlll1i WHEN niO1ii = '1' ELSE wire_n10O_dataout; + wire_nlO1i_w_lg_dataout3255w(0) <= NOT wire_nlO1i_dataout; + wire_nlO1ii_dataout <= wire_nlOiil_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO1il_dataout <= wire_nlOiiO_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO1iO_dataout <= wire_nlOili_dataout OR wire_nll1O_w_lg_nll1l2599w(0); + wire_nlO1l_dataout <= nlliOO WHEN niO1ii = '1' ELSE wire_n1ii_dataout; + wire_nlO1l_w_lg_w_lg_w3259w3260w3261w(0) <= wire_nlO1l_w_lg_w3259w3260w(0) AND wire_nllll_dataout; + wire_nlO1l_w_lg_w3259w3260w(0) <= wire_nlO1l_w3259w(0) AND wire_nlllO_dataout; + wire_nlO1l_w3259w(0) <= wire_nlO1l_w_lg_w_lg_w_lg_w_lg_dataout3254w3256w3257w3258w(0) AND wire_nllOi_dataout; + wire_nlO1l_w_lg_w_lg_w_lg_w_lg_dataout3254w3256w3257w3258w(0) <= wire_nlO1l_w_lg_w_lg_w_lg_dataout3254w3256w3257w(0) AND wire_nllOl_dataout; + wire_nlO1l_w_lg_w_lg_w_lg_dataout3254w3256w3257w(0) <= wire_nlO1l_w_lg_w_lg_dataout3254w3256w(0) AND wire_nllOO_dataout; + wire_nlO1l_w_lg_w_lg_dataout3254w3256w(0) <= wire_nlO1l_w_lg_dataout3254w(0) AND wire_nlO1i_w_lg_dataout3255w(0); + wire_nlO1l_w_lg_dataout3254w(0) <= NOT wire_nlO1l_dataout; + wire_nlO1li_dataout <= wire_ni0il_dataout WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOill_dataout; + wire_nlO1ll_dataout <= wire_ni0iO_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOilO_dataout; + wire_nlO1lO_dataout <= wire_ni0li_dataout WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOiOi_dataout; + wire_nlO1O_dataout <= nlliOl WHEN niO1ii = '1' ELSE wire_n1il_dataout; + wire_nlO1Oi_dataout <= wire_ni0ll_dataout WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOiOl_dataout; + wire_nlO1Ol_dataout <= wire_ni0lO_o WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOiOO_dataout; + wire_nlO1OO_dataout <= wire_ni0Ol_dataout WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOl1i_dataout; + wire_nlOi_dataout <= wire_n1O_o(4) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(3); + wire_nlOi0i_dataout <= wire_w_lg_niliOO2592w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOO0l_dataout; + wire_nlOi0l_dataout <= wire_w_lg_nill1i2591w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOO0O_dataout; + wire_nlOi0O_dataout <= wire_w_lg_nill1l2590w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOOii_dataout; + wire_nlOi1i_dataout <= wire_w_lg_niliOi2594w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOO1l_dataout; + wire_nlOi1l_dataout <= wire_w_lg_niliOl2593w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOO1O_dataout; + wire_nlOi1O_dataout <= wire_w_lg_nill1O2588w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOO0i_dataout; + wire_nlOii_dataout <= nllili WHEN niO1ii = '1' ELSE wire_n1lO_dataout; + wire_nlOiii_dataout <= wire_w_lg_nill1l2590w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOOil_dataout; + wire_nlOiil_dataout <= wire_w_lg_nill1l2590w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOOiO_dataout; + wire_nlOiiO_dataout <= wire_w_lg_nill1l2590w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOOli_dataout; + wire_nlOil_dataout <= nlliiO WHEN niO1ii = '1' ELSE wire_n1Oi_dataout; + wire_nlOili_dataout <= wire_w_lg_nill1O2588w(0) WHEN wire_nll1O_w_lg_nli0li2589w(0) = '1' ELSE wire_nlOOll_dataout; + wire_nlOill_dataout <= wire_nlOOlO_dataout WHEN niliiO = '1' ELSE nli0lO; + wire_nlOilO_dataout <= wire_nlOOOi_dataout WHEN niliiO = '1' ELSE nll0il; + wire_nlOiO_dataout <= nlliil WHEN niO1ii = '1' ELSE wire_n1Ol_dataout; + wire_nlOiOi_dataout <= wire_nlOOOl_dataout WHEN niliiO = '1' ELSE nll0iO; + wire_nlOiOl_dataout <= wire_nlOOOO_dataout WHEN niliiO = '1' ELSE nll0li; + wire_nlOiOO_dataout <= wire_n111i_dataout WHEN niliiO = '1' ELSE nll0ll; + wire_nlOl_dataout <= wire_n1O_o(5) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(4); + wire_nlOl0i_dataout <= wire_n110l_o WHEN niliiO = '1' ELSE nll0OO; + wire_nlOl0l_dataout <= wire_n110O_o WHEN niliiO = '1' ELSE nlli1i; + wire_nlOl0O_dataout <= wire_n11ii_o WHEN niliiO = '1' ELSE nlli1l; + wire_nlOl1i_dataout <= wire_n111l_dataout WHEN niliiO = '1' ELSE nll0lO; + wire_nlOl1l_dataout <= wire_n111O_dataout WHEN niliiO = '1' ELSE nll0Oi; + wire_nlOl1O_dataout <= wire_n110i_dataout WHEN niliiO = '1' ELSE nll0Ol; + wire_nlOli_dataout <= nlliii WHEN niO1ii = '1' ELSE wire_n1OO_dataout; + wire_nlOlii_dataout <= wire_n11il_o WHEN niliiO = '1' ELSE nlli1O; + wire_nlOlil_dataout <= wire_n11iO_o WHEN niliiO = '1' ELSE nlli0i; + wire_nlOliO_dataout <= wire_n11li_o WHEN niliiO = '1' ELSE nlli0l; + wire_nlOll_dataout <= nlli0O AND niO1ii; + wire_nlOlli_dataout <= wire_n11ll_o WHEN niliiO = '1' ELSE nlli0O; + wire_nlOlll_dataout <= wire_n11lO_o WHEN niliiO = '1' ELSE nlliii; + wire_nlOllO_dataout <= wire_n11Oi_o WHEN niliiO = '1' ELSE nlliil; + wire_nlOlO_dataout <= nlli0l AND niO1ii; + wire_nlOlOi_dataout <= wire_n11Ol_o WHEN niliiO = '1' ELSE nlliiO; + wire_nlOlOl_dataout <= wire_n11OO_o WHEN niliiO = '1' ELSE nllili; + wire_nlOlOO_dataout <= wire_n101i_o WHEN niliiO = '1' ELSE nllill; + wire_nlOO_dataout <= wire_n1O_o(6) WHEN wire_n0iO_dataout = '1' ELSE rcid_len(5); + wire_nlOO0i_dataout <= wire_n100l_o WHEN niliiO = '1' ELSE nlliOO; + wire_nlOO0l_dataout <= wire_n100O_o WHEN niliiO = '1' ELSE nlll1i; + wire_nlOO0O_dataout <= wire_n10ii_o WHEN niliiO = '1' ELSE nlll1l; + wire_nlOO1i_dataout <= wire_n101l_o WHEN niliiO = '1' ELSE nllilO; + wire_nlOO1l_dataout <= wire_n101O_o WHEN niliiO = '1' ELSE nlliOi; + wire_nlOO1O_dataout <= wire_n100i_o WHEN niliiO = '1' ELSE nlliOl; + wire_nlOOi_dataout <= nlli0i AND niO1ii; + wire_nlOOii_dataout <= wire_n10il_o WHEN niliiO = '1' ELSE nlll1O; + wire_nlOOil_dataout <= wire_n10iO_o WHEN niliiO = '1' ELSE nlll0i; + wire_nlOOiO_dataout <= wire_n10li_o WHEN niliiO = '1' ELSE nlll0l; + wire_nlOOl_dataout <= nlli1O AND niO1ii; + wire_nlOOli_dataout <= wire_n10ll_o WHEN niliiO = '1' ELSE nlll0O; + wire_nlOOll_dataout <= wire_n10lO_o WHEN niliiO = '1' ELSE nlllii; + wire_nlOOlO_dataout <= wire_n0i0l_dataout WHEN wire_nil0O_o(0) = '1' ELSE nli0lO; + wire_nlOOO_dataout <= nlllii WHEN niO1il = '1' ELSE wire_n01i_dataout; + wire_nlOOOi_dataout <= wire_n0i0O_dataout WHEN wire_nil0O_o(0) = '1' ELSE nll0il; + wire_nlOOOl_dataout <= wire_n0iii_dataout WHEN wire_nil0O_o(0) = '1' ELSE nll0iO; + wire_nlOOOO_dataout <= wire_n0iil_dataout WHEN wire_nil0O_o(0) = '1' ELSE nll0li; + wire_n1O_a <= ( wire_niO0OO12_w_lg_w_lg_q32w33w & nlii & wire_niOi1i10_w_lg_w_lg_q28w29w & wire_niOi1l8_w_lg_w_lg_q25w26w & nl0i & nl1O & wire_niOi1O6_w_lg_w_lg_q20w21w & nl1i & "1"); + wire_n1O_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_n1O_a, + b => wire_n1O_b, + cin => wire_gnd, + o => wire_n1O_o + ); + wire_nil0O_i <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nil0O : oper_decoder + GENERIC MAP ( + width_i => 5, + width_o => 32 + ) + PORT MAP ( + i => wire_nil0O_i, + o => wire_nil0O_o + ); + wire_nill_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + wire_nill_b <= ( nlil & nlii & wire_niO0ll18_w_lg_w_lg_q97w98w & nl0l & nl0i & nl1O & wire_niO0lO16_w_lg_w_lg_q91w92w & nl1i); + nill : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nill_a, + b => wire_nill_b, + cin => wire_gnd, + o => wire_nill_o + ); + wire_n100i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1OO & wire_w_lg_w_lg_nil00O1614w1615w & "0" & "0" & "0" & "0" & "0" & "0" & nil00i & wire_w_lg_w_lg_nil0Ol1598w1599w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlli0O & "0" & "0" & "0" & wire_n0O0l_dataout); + wire_n100i_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n100i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n100i_data, + o => wire_n100i_o, + sel => wire_n100i_sel + ); + wire_n100l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil01i & wire_w_lg_w_lg_nil0ii1543w1544w & "0" & "0" & "0" & "0" & "0" & "0" & nil00l & wire_w_lg_w_lg_nil0OO1527w1528w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlliii & "0" & "0" & "0" & wire_n0O0O_dataout); + wire_n100l_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n100l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n100l_data, + o => wire_n100l_o, + sel => wire_n100l_sel + ); + wire_n100O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil01l & wire_w_lg_w_lg_nil0il1472w1473w & "0" & "0" & "0" & "0" & "0" & "0" & nll0OO & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlliil & "0" & "0" & "0" & wire_n0Oii_dataout); + wire_n100O_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n100O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n100O_data, + o => wire_n100O_o, + sel => wire_n100O_sel + ); + wire_n101i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1lO & wire_nliOi_w_lg_nlll0i1825w & "0" & "0" & "0" & "0" & "0" & "0" & nil01i & nil0Oi & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlli1O & "0" & "0" & "0" & wire_n0O1l_dataout); + wire_n101i_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n101i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n101i_data, + o => wire_n101i_o, + sel => wire_n101i_sel + ); + wire_n101l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1Oi & wire_nliOi_w_lg_w_lg_nlll1O1756w1757w & "0" & "0" & "0" & "0" & "0" & "0" & nil01l & wire_nliOi_w_lg_w_lg_nlliOl1740w1741w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlli0i & "0" & "0" & "0" & wire_n0O1O_dataout); + wire_n101l_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n101l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n101l_data, + o => wire_n101l_o, + sel => wire_n101l_sel + ); + wire_n101O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1Ol & wire_nliOi_w_lg_w_lg_nlll0i1685w1686w & "0" & "0" & "0" & "0" & "0" & "0" & nil01O & wire_nliOi_w_lg_w_lg_nlliOO1669w1670w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlli0l & "0" & "0" & "0" & wire_n0O0i_dataout); + wire_n101O_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n101O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n101O_data, + o => wire_n101O_o, + sel => wire_n101O_sel + ); + wire_n10ii_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil01O & wire_w_lg_nil0iO1403w & "0" & "0" & "0" & "0" & "0" & "0" & nlli1i & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlliiO & "0" & "0" & "0" & wire_n0Oil_dataout); + wire_n10ii_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n10ii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n10ii_data, + o => wire_n10ii_o, + sel => wire_n10ii_sel + ); + wire_n10il_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil00i & wire_w_lg_w_lg_nil0iO1333w1334w & "0" & "0" & "0" & "0" & "0" & "0" & nlli1l & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nllili & "0" & "0" & "0" & wire_n0OiO_dataout); + wire_n10il_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n10il : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n10il_data, + o => wire_n10il_o, + sel => wire_n10il_sel + ); + wire_n10iO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil00l & wire_w_lg_w_lg_nil0li1263w1264w & "0" & "0" & "0" & "0" & "0" & "0" & nlli1O & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nllill & "0" & "0" & "0" & wire_n0Oli_dataout); + wire_n10iO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n10iO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n10iO_data, + o => wire_n10iO_o, + sel => wire_n10iO_sel + ); + wire_n10li_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nll0OO & "1" & "0" & "0" & "0" & "0" & "0" & "0" & nlli0i & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nllilO & "0" & "0" & "0" & wire_n0Oll_dataout); + wire_n10li_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n10li : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n10li_data, + o => wire_n10li_o, + sel => wire_n10li_sel + ); + wire_n10ll_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nlli1i & "1" & "0" & "0" & "0" & "0" & "0" & "0" & nlli0l & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlliOi & "0" & "0" & "0" & wire_n0OlO_dataout); + wire_n10ll_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n10ll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n10ll_data, + o => wire_n10ll_o, + sel => wire_n10ll_sel + ); + wire_n10lO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nlli1l & "1" & "0" & "0" & "0" & "0" & "0" & "0" & nlli0O & "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlliOl & "0" & "0" & "0" & wire_n0OOi_dataout); + wire_n10lO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n10lO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n10lO_data, + o => wire_n10lO_o, + sel => wire_n10lO_sel + ); + wire_n110l_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_w_lg_nlll1i2573w2574w & nil0ll & "0" & "0" & "0" & "0" & "0" & "0" & nil10l & wire_nliOi_w_lg_nllili2557w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & nili1O & "0" & "0" & "0" & nil1Oi & "0" & wire_nliOi_w_lg_nlli1l2531w & "0" & wire_n0l0O_dataout); + wire_n110l_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n110l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n110l_data, + o => wire_n110l_o, + sel => wire_n110l_sel + ); + wire_n110O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_w_lg_nlll1l2504w2505w & nil0lO & "0" & "0" & "0" & "0" & "0" & "0" & nil10O & wire_nliOi_w_lg_nllill2488w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & nili1l & "0" & "0" & "0" & nil1Ol & "0" & wire_nliOi_w_lg_nlli1O2462w & "0" & wire_n0lii_dataout); + wire_n110O_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n110O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n110O_data, + o => wire_n110O_o, + sel => wire_n110O_sel + ); + wire_n11ii_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_nlli0l2436w & nil00O & "0" & "0" & "0" & "0" & "0" & "0" & nil1ii & nil0Ol & "0" & "0" & "0" & "0" & "0" & "0" & "0" & nili1i & "0" & "0" & "0" & nil1OO & "0" & nili0i & "0" & wire_n0lil_dataout); + wire_n11ii_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11ii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11ii_data, + o => wire_n11ii_o, + sel => wire_n11ii_sel + ); + wire_n11il_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_nlli0O2370w & nil0ii & "0" & "0" & "0" & "0" & "0" & "0" & nil1il & nil0OO & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_nlli0O2339w & "0" & "0" & "0" & nil01i & "0" & nili0l & "0" & wire_n0liO_dataout); + wire_n11il_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11il : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11il_data, + o => wire_n11il_o, + sel => wire_n11il_sel + ); + wire_n11iO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil10l & nil0il & "0" & "0" & "0" & "0" & "0" & "0" & nil1iO & nil0ll & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_nlliii2273w & "0" & "0" & "0" & nil01l & "0" & nili0O & "0" & wire_n0lli_dataout); + wire_n11iO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11iO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11iO_data, + o => wire_n11iO_o, + sel => wire_n11iO_sel + ); + wire_n11li_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil10O & nil0li & "0" & "0" & "0" & "0" & "0" & "0" & nil1li & nil0lO & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_nlliil2207w & "0" & "0" & "0" & nil01O & "0" & niliii & "0" & wire_n0lll_dataout); + wire_n11li_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11li : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11li_data, + o => wire_n11li_o, + sel => wire_n11li_sel + ); + wire_n11ll_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1ii & wire_w_lg_nil01l2170w & "0" & "0" & "0" & "0" & "0" & "0" & nil1ll & wire_w_lg_nil1Oi2155w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOi_w_lg_nlliiO2139w & "0" & "0" & "0" & nil00i & "0" & wire_nliOi_w_lg_w_lg_nlliii2127w2128w & "0" & wire_n0llO_dataout); + wire_n11ll_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11ll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11ll_data, + o => wire_n11ll_o, + sel => wire_n11ll_sel + ); + wire_n11lO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1il & nil0Oi & "0" & "0" & "0" & "0" & "0" & "0" & nil1lO & wire_nliOi_w_lg_nllill2086w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_w_lg_nili1O2070w & "0" & "0" & "0" & nil00l & "0" & wire_nliOi_w_lg_nlli1O2059w & "0" & wire_n0lOi_dataout); + wire_n11lO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11lO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11lO_data, + o => wire_n11lO_o, + sel => wire_n11lO_sel + ); + wire_n11Oi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1iO & wire_nliOi_w_lg_nlll1i2032w & "0" & "0" & "0" & "0" & "0" & "0" & nil1Oi & wire_nliOi_w_lg_nllilO2017w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_w_lg_nili1l2001w & "0" & "0" & "0" & nll0OO & "0" & "0" & "0" & wire_n0lOl_dataout); + wire_n11Oi_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11Oi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11Oi_data, + o => wire_n11Oi_o, + sel => wire_n11Oi_sel + ); + wire_n11Ol_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1li & wire_nliOi_w_lg_nlll1l1963w & "0" & "0" & "0" & "0" & "0" & "0" & nil1Ol & wire_nliOi_w_lg_nlliOi1948w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_w_lg_nili1i1932w & "0" & "0" & "0" & nlli1i & "0" & "0" & "0" & wire_n0lOO_dataout); + wire_n11Ol_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11Ol : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11Ol_data, + o => wire_n11Ol_o, + sel => wire_n11Ol_sel + ); + wire_n11OO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & nil1ll & wire_nliOi_w_lg_nlll1O1894w & "0" & "0" & "0" & "0" & "0" & "0" & nil1OO & wire_nliOi_w_lg_nlliOl1879w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0" & "0" & nlli1l & "0" & "0" & "0" & wire_n0O1i_dataout); + wire_n11OO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + n11OO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_n11OO_data, + o => wire_n11OO_o, + sel => wire_n11OO_sel + ); + wire_nii0i_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_w_lg_rall_one_dect_only477w & "1" & "1" & "1" & "0" & "1" & "1" & "1" & wire_w_lg_rall_one_dect_only477w); + wire_nii0i_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nii0i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nii0i_data, + o => wire_nii0i_o, + sel => wire_nii0i_sel + ); + wire_nii0l_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & rall_one_dect_only); + wire_nii0l_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nii0l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nii0l_data, + o => wire_nii0l_o, + sel => wire_nii0l_sel + ); + wire_nii0O_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_w_lg_rall_one_dect_only477w); + wire_nii0O_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nii0O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nii0O_data, + o => wire_nii0O_o, + sel => wire_nii0O_sel + ); + wire_nii1O_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_w_lg_rall_one_dect_only477w & "1" & "1" & "1" & "0" & "1" & "0" & "1" & wire_w_lg_rall_one_dect_only477w); + wire_nii1O_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nii1O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nii1O_data, + o => wire_nii1O_o, + sel => wire_nii1O_sel + ); + wire_niiii_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_w_lg_rall_one_dect_only477w & "1" & "1" & "1" & "1" & "1" & "1" & "1" & rall_one_dect_only); + wire_niiii_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + niiii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiii_data, + o => wire_niiii_o, + sel => wire_niiii_sel + ); + wire_niiiO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_w_lg_rall_one_dect_only477w & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1"); + wire_niiiO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + niiiO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niiiO_data, + o => wire_niiiO_o, + sel => wire_niiiO_sel + ); + wire_niill_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & rall_one_dect_only & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "0"); + wire_niill_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + niill : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niill_data, + o => wire_niill_o, + sel => wire_niill_sel + ); + wire_niilO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & rall_one_dect_only & "1" & "1" & "1" & "1" & "1" & "0" & "1" & "0"); + wire_niilO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + niilO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_niilO_data, + o => wire_niilO_o, + sel => wire_niilO_sel + ); + wire_nliiiO_data <= ( nlii0O & nlii0O & nlii0O & nlii0O & nlii0O & nlii0O & niilil & wire_nliOi_w_lg_nlii0O2954w & nlii0O & nlii0O & nlii0O & nlii0O & nlii0O & nlii0O & niilil & wire_nliOi_w_lg_nlii0O2944w & nlii0O & nlii0O & nlii0O & nlii0O & nlii0O & nlii0O & nlii0O & niiO0i & nlii0O & nlii0O & nlii0O & niiO0i & nlii0O & niiO0i & nlii0O & niiO0i); + wire_nliiiO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nliiiO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nliiiO_data, + o => wire_nliiiO_o, + sel => wire_nliiiO_sel + ); + wire_nliili_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & niiliO & wire_nll1O_w_lg_w_lg_nli0li2902w2903w & "0" & "0" & "0" & "0" & "0" & "0" & niiliO & wire_nll1O_w_lg_w_lg_nli0li2886w2887w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nliOil_dataout & "0" & "0" & "0" & wire_nilii_w_lg_w_lg_dataout2862w2863w & "0" & wire_nll1O_w_lg_w_lg_nli0li2856w2857w & "0" & wire_nll1li_dataout); + wire_nliili_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nliili : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nliili_data, + o => wire_nliili_o, + sel => wire_nliili_sel + ); + wire_nliill_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & wire_w_lg_niilli2830w & wire_w_lg_niilOi2828w & "0" & "0" & "0" & "0" & "0" & "0" & wire_w_lg_niilOO2814w & wire_w_lg_niiO1l2812w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_w_lg_niiOii2796w & "0" & "0" & "0" & wire_w_lg_niiOli2788w & "0" & wire_w_lg_niiOlO2784w & "0" & wire_w_lg_nil11O2779w); + wire_nliill_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nliill : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nliill_data, + o => wire_nliill_o, + sel => wire_nliill_sel + ); + wire_nliilO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & niilli & niilOi & "0" & "0" & "0" & "0" & "0" & "0" & niilOO & niiO1l & "0" & "0" & "0" & "0" & "0" & "0" & "0" & niiOii & "0" & "0" & "0" & niiOli & "0" & niiOlO & "0" & nil11O); + wire_nliilO_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nliilO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nliilO_data, + o => wire_nliilO_o, + sel => wire_nliilO_sel + ); + wire_nliiOi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & niillO & wire_w_lg_w_lg_sync_status2690w2691w & "0" & "0" & "0" & "0" & "0" & "0" & niillO & wire_w_lg_w_lg_sync_status2674w2675w & "0" & "0" & "0" & "0" & "0" & "0" & "0" & niiOiO & "0" & "0" & "0" & niiOiO & "0" & niiOiO & "0" & niiOiO); + wire_nliiOi_sel <= ( rpma_doublewidth_rx & rpmadwidth_rx & rprbs_sel(2 DOWNTO 0)); + nliiOi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nliiOi_data, + o => wire_nliiOi_o, + sel => wire_nliiOi_sel + ); + wire_n0ll_data <= ( "0" & wire_niO1li32_w_lg_w_lg_q159w160w & "1"); + wire_n0ll_sel <= ( niOO & niOi & nlliO); + n0ll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0ll_data, + o => wire_n0ll_o, + sel => wire_n0ll_sel + ); + wire_n0lO_data <= ( "0" & niO0ii & wire_w_lg_niO00O146w); + wire_n0lO_sel <= ( niOO & wire_niO1ll30_w_lg_w_lg_q142w143w & wire_niO1lO28_w_lg_w_lg_q138w139w); + n0lO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0lO_data, + o => wire_n0lO_o, + sel => wire_n0lO_sel + ); + wire_n0Oi_data <= ( niO1Oi & wire_ni1i_dataout & niO00O); + wire_n0Oi_sel <= ( niOO & niOi & nlliO); + n0Oi : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0Oi_data, + o => wire_n0Oi_o, + sel => wire_n0Oi_sel + ); + wire_n0Ol_data <= ( wire_w_lg_niO1Oi128w & wire_niO1Ol26_w_lg_w_lg_q125w126w & "0"); + wire_n0Ol_sel <= ( niOO & niOi & nlliO); + n0Ol : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0Ol_data, + o => wire_n0Ol_o, + sel => wire_n0Ol_sel + ); + wire_ni0iO_data <= ( "1" & nll0il & rall_one_dect_only); + wire_ni0iO_sel <= ( nilili & nilill & wire_nil0O_o(0)); + ni0iO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni0iO_data, + o => wire_ni0iO_o, + sel => wire_ni0iO_sel + ); + wire_ni0lO_data <= ( "1" & nll0ll & rall_one_dect_only); + wire_ni0lO_sel <= ( nilili & nilill & wire_nil0O_o(0)); + ni0lO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni0lO_data, + o => wire_ni0lO_o, + sel => wire_ni0lO_sel + ); + wire_nl00i_data <= ( wire_w_lg_nillil256w & wire_w_lg_nilliO254w & wire_w_lg_nillli252w & wire_w_lg_nillll250w & wire_w_lg_nilllO248w & "1"); + wire_nl00i_sel <= ( wire_nillOi50_w_lg_w_lg_q242w243w & wire_nillOl48_w_lg_w_lg_q239w240w & nlill & wire_nillOO46_w_lg_w_lg_q235w236w & nliiO & nlllil); + nl00i : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl00i_data, + o => wire_nl00i_o, + sel => wire_nl00i_sel + ); + wire_nl0iO_data <= ( wire_nilO1i44_w_lg_w_lg_q229w230w & wire_w_lg_nilOOl185w & wire_w_lg_nilO1l226w & wire_w_lg_nilOOO222w & wire_nilO1O42_w_lg_w_lg_q221w223w & "1"); + wire_nl0iO_sel <= ( nliOl & nlilO & nlill & nlili & nliiO & nlllil); + nl0iO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl0iO_data, + o => wire_nl0iO_o, + sel => wire_nl0iO_sel + ); + wire_nl0OO_data <= ( wire_w_lg_nilO0i209w & wire_w_lg_nilO0l207w & wire_w_lg_nilO0O205w & wire_w_lg_nilOii203w & wire_w_lg_nilOil201w & "1"); + wire_nl0OO_sel <= ( nliOl & nlilO & nlill & nlili & nliiO & nlllil); + nl0OO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl0OO_data, + o => wire_nl0OO_o, + sel => wire_nl0OO_sel + ); + wire_nli0O_data <= ( wire_nilOiO40_w_lg_w_lg_q187w189w & wire_w_lg_nilOOl185w & wire_w_lg_nilOll183w & wire_w_lg_nilOlO181w & wire_w_lg_nilOOi179w & "1"); + wire_nli0O_sel <= ( nliOl & nlilO & nlill & nlili & nliiO & nlllil); + nli0O : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nli0O_data, + o => wire_nli0O_o, + sel => wire_nli0O_sel + ); + + END RTL; --cycloneiv_hssi_rx_digi_prbs_ver +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 577 mux21 929 oper_add 13 oper_less_than 8 oper_mux 157 oper_selector 81 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rx_digi_wordalign IS + PORT + ( + a1a2_k1k2_flag : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + a1a2_size : IN STD_LOGIC; + adata : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); + adata_valid : OUT STD_LOGIC; + autobytealign_dis : IN STD_LOGIC; + bitloc_rev_en : IN STD_LOGIC; + bitslip : IN STD_LOGIC; + byte_rev_en : IN STD_LOGIC; + cg_syncpat : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : IN STD_LOGIC; + comp_pat : IN STD_LOGIC_VECTOR (39 DOWNTO 0); + comp_pat_porn : IN STD_LOGIC; + comp_pat_size : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + disable_rx_disp : IN STD_LOGIC; + dwidth : IN STD_LOGIC; + encdet_prbs : IN STD_LOGIC; + encdt : IN STD_LOGIC; + enumber : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + gnumber : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + ib_invalid_code : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + kchar : OUT STD_LOGIC; + kcount : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); + knumber : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + lpbk_en : IN STD_LOGIC; + max_rlv_sel : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + pipe_loose_sync : IN STD_LOGIC; + pmadwidth : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + polinv_en : IN STD_LOGIC; + prbs_en : IN STD_LOGIC; + pudi : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + pudr : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + r8b10b_dec_ibm_en : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rauto_speed_ena : IN STD_LOGIC; + rbitloc_rev_en : IN STD_LOGIC; + rbyte_rev_en : IN STD_LOGIC; + rencdt_rising : IN STD_LOGIC; + resync_badcg_en : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rforce_sig_det_pcs : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rkchar : IN STD_LOGIC; + rlv : OUT STD_LOGIC; + rlv_en : IN STD_LOGIC; + rlv_lt : OUT STD_LOGIC; + rosbased : IN STD_LOGIC; + rosnumber : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + rpolinv_en : IN STD_LOGIC; + rrxpcsbypass_en : IN STD_LOGIC; + rst : IN STD_LOGIC; + rst1 : OUT STD_LOGIC; + scan_mode : IN STD_LOGIC; + signal_detect : IN STD_LOGIC; + signal_detect_rcvdclk : OUT STD_LOGIC; + sudi : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + sudi_pre : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); + sync_sm_dis : IN STD_LOGIC; + sync_status : OUT STD_LOGIC; + testbus : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); + wa_6g_en : IN STD_LOGIC; + wa_boundary : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END cycloneiv_hssi_rx_digi_wordalign; + + ARCHITECTURE RTL OF cycloneiv_hssi_rx_digi_wordalign IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n1i00OO49 : STD_LOGIC := '0'; + SIGNAL n1i00OO50 : STD_LOGIC := '0'; + SIGNAL n1i0lOi47 : STD_LOGIC := '0'; + SIGNAL n1i0lOi48 : STD_LOGIC := '0'; + SIGNAL n1i0O0i43 : STD_LOGIC := '0'; + SIGNAL n1i0O0i44 : STD_LOGIC := '0'; + SIGNAL wire_n1i0O0i44_w_lg_q340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1i0O1l45 : STD_LOGIC := '0'; + SIGNAL n1i0O1l46 : STD_LOGIC := '0'; + SIGNAL n1i0Oil41 : STD_LOGIC := '0'; + SIGNAL n1i0Oil42 : STD_LOGIC := '0'; + SIGNAL n1i0Oli39 : STD_LOGIC := '0'; + SIGNAL n1i0Oli40 : STD_LOGIC := '0'; + SIGNAL wire_n1i0Oli40_w_lg_q324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1i0OlO37 : STD_LOGIC := '0'; + SIGNAL n1i0OlO38 : STD_LOGIC := '0'; + SIGNAL n1i0OOl35 : STD_LOGIC := '0'; + SIGNAL n1i0OOl36 : STD_LOGIC := '0'; + SIGNAL n1ii00O19 : STD_LOGIC := '0'; + SIGNAL n1ii00O20 : STD_LOGIC := '0'; + SIGNAL n1ii0ii17 : STD_LOGIC := '0'; + SIGNAL n1ii0ii18 : STD_LOGIC := '0'; + SIGNAL n1ii0ll15 : STD_LOGIC := '0'; + SIGNAL n1ii0ll16 : STD_LOGIC := '0'; + SIGNAL wire_n1ii0ll16_w_lg_w_lg_q179w180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ii0ll16_w_lg_q179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1ii0OO13 : STD_LOGIC := '0'; + SIGNAL n1ii0OO14 : STD_LOGIC := '0'; + SIGNAL n1ii10l33 : STD_LOGIC := '0'; + SIGNAL n1ii10l34 : STD_LOGIC := '0'; + SIGNAL n1ii1ii31 : STD_LOGIC := '0'; + SIGNAL n1ii1ii32 : STD_LOGIC := '0'; + SIGNAL wire_n1ii1ii32_w_lg_w_lg_q274w275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ii1ii32_w_lg_q274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1ii1il29 : STD_LOGIC := '0'; + SIGNAL n1ii1il30 : STD_LOGIC := '0'; + SIGNAL wire_n1ii1il30_w_lg_w_lg_q270w271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ii1il30_w_lg_q270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1ii1iO27 : STD_LOGIC := '0'; + SIGNAL n1ii1iO28 : STD_LOGIC := '0'; + SIGNAL wire_n1ii1iO28_w_lg_w_lg_q258w259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ii1iO28_w_lg_q258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1ii1li25 : STD_LOGIC := '0'; + SIGNAL n1ii1li26 : STD_LOGIC := '0'; + SIGNAL wire_n1ii1li26_w_lg_w_lg_q243w244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ii1li26_w_lg_q243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1ii1ll23 : STD_LOGIC := '0'; + SIGNAL n1ii1ll24 : STD_LOGIC := '0'; + SIGNAL wire_n1ii1ll24_w_lg_w_lg_q240w241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ii1ll24_w_lg_q240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1ii1Oi21 : STD_LOGIC := '0'; + SIGNAL n1ii1Oi22 : STD_LOGIC := '0'; + SIGNAL n1iii0i11 : STD_LOGIC := '0'; + SIGNAL n1iii0i12 : STD_LOGIC := '0'; + SIGNAL n1iii0O10 : STD_LOGIC := '0'; + SIGNAL n1iii0O9 : STD_LOGIC := '0'; + SIGNAL n1iiiil7 : STD_LOGIC := '0'; + SIGNAL n1iiiil8 : STD_LOGIC := '0'; + SIGNAL n1iiiOl5 : STD_LOGIC := '0'; + SIGNAL n1iiiOl6 : STD_LOGIC := '0'; + SIGNAL n1iil0O1 : STD_LOGIC := '0'; + SIGNAL n1iil0O2 : STD_LOGIC := '0'; + SIGNAL n1iil1i3 : STD_LOGIC := '0'; + SIGNAL n1iil1i4 : STD_LOGIC := '0'; + SIGNAL wire_n1iil1i4_w_lg_q7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni0li : STD_LOGIC := '0'; + SIGNAL ni0Ol : STD_LOGIC := '0'; + SIGNAL wire_ni0Oi_CLRN : STD_LOGIC; + SIGNAL n01000i : STD_LOGIC := '0'; + SIGNAL n01000l : STD_LOGIC := '0'; + SIGNAL n01000O : STD_LOGIC := '0'; + SIGNAL n01001i : STD_LOGIC := '0'; + SIGNAL n01001l : STD_LOGIC := '0'; + SIGNAL n01001O : STD_LOGIC := '0'; + SIGNAL n0100ii : STD_LOGIC := '0'; + SIGNAL n0100il : STD_LOGIC := '0'; + SIGNAL n0101il : STD_LOGIC := '0'; + SIGNAL n0101iO : STD_LOGIC := '0'; + SIGNAL n0101li : STD_LOGIC := '0'; + SIGNAL n0101ll : STD_LOGIC := '0'; + SIGNAL n0101lO : STD_LOGIC := '0'; + SIGNAL n0101Oi : STD_LOGIC := '0'; + SIGNAL n0101Ol : STD_LOGIC := '0'; + SIGNAL n0101OO : STD_LOGIC := '0'; + SIGNAL n010Ol : STD_LOGIC := '0'; + SIGNAL n010OO : STD_LOGIC := '0'; + SIGNAL n0110i : STD_LOGIC := '0'; + SIGNAL n0110l : STD_LOGIC := '0'; + SIGNAL n0110O : STD_LOGIC := '0'; + SIGNAL n0111i : STD_LOGIC := '0'; + SIGNAL n0111l : STD_LOGIC := '0'; + SIGNAL n0111O : STD_LOGIC := '0'; + SIGNAL n011ii : STD_LOGIC := '0'; + SIGNAL n011il : STD_LOGIC := '0'; + SIGNAL n011iO : STD_LOGIC := '0'; + SIGNAL n011l0i : STD_LOGIC := '0'; + SIGNAL n011l0l : STD_LOGIC := '0'; + SIGNAL n011l0O : STD_LOGIC := '0'; + SIGNAL n011l1l : STD_LOGIC := '0'; + SIGNAL n011l1O : STD_LOGIC := '0'; + SIGNAL n011li : STD_LOGIC := '0'; + SIGNAL n011lii : STD_LOGIC := '0'; + SIGNAL n011lil : STD_LOGIC := '0'; + SIGNAL n011liO : STD_LOGIC := '0'; + SIGNAL n011ll : STD_LOGIC := '0'; + SIGNAL n011lli : STD_LOGIC := '0'; + SIGNAL n011lll : STD_LOGIC := '0'; + SIGNAL n011llO : STD_LOGIC := '0'; + SIGNAL n011lO : STD_LOGIC := '0'; + SIGNAL n011lOi : STD_LOGIC := '0'; + SIGNAL n011lOl : STD_LOGIC := '0'; + SIGNAL n011lOO : STD_LOGIC := '0'; + SIGNAL n011O0i : STD_LOGIC := '0'; + SIGNAL n011O1i : STD_LOGIC := '0'; + SIGNAL n011O1l : STD_LOGIC := '0'; + SIGNAL n011O1O : STD_LOGIC := '0'; + SIGNAL n011Oi : STD_LOGIC := '0'; + SIGNAL n01i0i : STD_LOGIC := '0'; + SIGNAL n01i0l : STD_LOGIC := '0'; + SIGNAL n01i0O : STD_LOGIC := '0'; + SIGNAL n01i1i : STD_LOGIC := '0'; + SIGNAL n01i1l : STD_LOGIC := '0'; + SIGNAL n01i1O : STD_LOGIC := '0'; + SIGNAL n01iii : STD_LOGIC := '0'; + SIGNAL n01iil : STD_LOGIC := '0'; + SIGNAL n01iiO : STD_LOGIC := '0'; + SIGNAL n01ili : STD_LOGIC := '0'; + SIGNAL n01ill : STD_LOGIC := '0'; + SIGNAL n1l00O : STD_LOGIC := '0'; + SIGNAL n1l0ii : STD_LOGIC := '0'; + SIGNAL n1l0il : STD_LOGIC := '0'; + SIGNAL n1l0iO : STD_LOGIC := '0'; + SIGNAL n1l0li : STD_LOGIC := '0'; + SIGNAL n1l0ll : STD_LOGIC := '0'; + SIGNAL n1l0lO : STD_LOGIC := '0'; + SIGNAL n1l0Oi : STD_LOGIC := '0'; + SIGNAL n1liii : STD_LOGIC := '0'; + SIGNAL n1O01i : STD_LOGIC := '0'; + SIGNAL n1O01O : STD_LOGIC := '0'; + SIGNAL n1O1ll : STD_LOGIC := '0'; + SIGNAL n1O1lO : STD_LOGIC := '0'; + SIGNAL n1O1Oi : STD_LOGIC := '0'; + SIGNAL n1O1Ol : STD_LOGIC := '0'; + SIGNAL n1O1OO : STD_LOGIC := '0'; + SIGNAL n1Oi0i : STD_LOGIC := '0'; + SIGNAL n1Oi0l : STD_LOGIC := '0'; + SIGNAL n1Oi0O : STD_LOGIC := '0'; + SIGNAL n1Oi1O : STD_LOGIC := '0'; + SIGNAL n1OilO : STD_LOGIC := '0'; + SIGNAL n1OiOi : STD_LOGIC := '0'; + SIGNAL n1OiOl : STD_LOGIC := '0'; + SIGNAL n1OiOO : STD_LOGIC := '0'; + SIGNAL n1Ol00i : STD_LOGIC := '0'; + SIGNAL n1Ol00l : STD_LOGIC := '0'; + SIGNAL n1Ol00O : STD_LOGIC := '0'; + SIGNAL n1Ol01i : STD_LOGIC := '0'; + SIGNAL n1Ol01l : STD_LOGIC := '0'; + SIGNAL n1Ol01O : STD_LOGIC := '0'; + SIGNAL n1Ol0ii : STD_LOGIC := '0'; + SIGNAL n1Ol0il : STD_LOGIC := '0'; + SIGNAL n1Ol1Ol : STD_LOGIC := '0'; + SIGNAL n1Ol1OO : STD_LOGIC := '0'; + SIGNAL n1Oli0i : STD_LOGIC := '0'; + SIGNAL n1OO00i : STD_LOGIC := '0'; + SIGNAL n1OO01i : STD_LOGIC := '0'; + SIGNAL n1OO01l : STD_LOGIC := '0'; + SIGNAL n1OO0iO : STD_LOGIC := '0'; + SIGNAL n1OO0li : STD_LOGIC := '0'; + SIGNAL n1OO0ll : STD_LOGIC := '0'; + SIGNAL n1OO0lO : STD_LOGIC := '0'; + SIGNAL n1OO1lO : STD_LOGIC := '0'; + SIGNAL n1OO1Oi : STD_LOGIC := '0'; + SIGNAL n1OO1Ol : STD_LOGIC := '0'; + SIGNAL n1OO1OO : STD_LOGIC := '0'; + SIGNAL n1OOi0i : STD_LOGIC := '0'; + SIGNAL n1OOi1O : STD_LOGIC := '0'; + SIGNAL n1OOOl : STD_LOGIC := '0'; + SIGNAL n1OOOO : STD_LOGIC := '0'; + SIGNAL ni0iO : STD_LOGIC := '0'; + SIGNAL ni0OO : STD_LOGIC := '0'; + SIGNAL niii0i : STD_LOGIC := '0'; + SIGNAL niii0l : STD_LOGIC := '0'; + SIGNAL niii0O : STD_LOGIC := '0'; + SIGNAL niiill : STD_LOGIC := '0'; + SIGNAL nil00i : STD_LOGIC := '0'; + SIGNAL nil00l : STD_LOGIC := '0'; + SIGNAL nil00O : STD_LOGIC := '0'; + SIGNAL nil01i : STD_LOGIC := '0'; + SIGNAL nil01l : STD_LOGIC := '0'; + SIGNAL nil01O : STD_LOGIC := '0'; + SIGNAL nil0ii : STD_LOGIC := '0'; + SIGNAL nil0il : STD_LOGIC := '0'; + SIGNAL nil0iO : STD_LOGIC := '0'; + SIGNAL nil0li : STD_LOGIC := '0'; + SIGNAL nil0ll : STD_LOGIC := '0'; + SIGNAL nil0lO : STD_LOGIC := '0'; + SIGNAL nil0Oi : STD_LOGIC := '0'; + SIGNAL nil0Ol : STD_LOGIC := '0'; + SIGNAL nil0OO : STD_LOGIC := '0'; + SIGNAL nil1il : STD_LOGIC := '0'; + SIGNAL nil1iO : STD_LOGIC := '0'; + SIGNAL nil1li : STD_LOGIC := '0'; + SIGNAL nil1ll : STD_LOGIC := '0'; + SIGNAL nil1lO : STD_LOGIC := '0'; + SIGNAL nil1Ol : STD_LOGIC := '0'; + SIGNAL nil1OO : STD_LOGIC := '0'; + SIGNAL nili0i : STD_LOGIC := '0'; + SIGNAL nili0l : STD_LOGIC := '0'; + SIGNAL nili0O : STD_LOGIC := '0'; + SIGNAL nili1i : STD_LOGIC := '0'; + SIGNAL nili1l : STD_LOGIC := '0'; + SIGNAL nili1O : STD_LOGIC := '0'; + SIGNAL niliii : STD_LOGIC := '0'; + SIGNAL niliil : STD_LOGIC := '0'; + SIGNAL niliiO : STD_LOGIC := '0'; + SIGNAL nilili : STD_LOGIC := '0'; + SIGNAL nilill : STD_LOGIC := '0'; + SIGNAL nililO : STD_LOGIC := '0'; + SIGNAL niliOi : STD_LOGIC := '0'; + SIGNAL niliOl : STD_LOGIC := '0'; + SIGNAL niliOO : STD_LOGIC := '0'; + SIGNAL nill0i : STD_LOGIC := '0'; + SIGNAL nill0l : STD_LOGIC := '0'; + SIGNAL nill1i : STD_LOGIC := '0'; + SIGNAL nill1l : STD_LOGIC := '0'; + SIGNAL nill1O : STD_LOGIC := '0'; + SIGNAL niOlii : STD_LOGIC := '0'; + SIGNAL niOlil : STD_LOGIC := '0'; + SIGNAL niOlli : STD_LOGIC := '0'; + SIGNAL niOlll : STD_LOGIC := '0'; + SIGNAL niOllO : STD_LOGIC := '0'; + SIGNAL niOlOi : STD_LOGIC := '0'; + SIGNAL niOlOl : STD_LOGIC := '0'; + SIGNAL niOlOO : STD_LOGIC := '0'; + SIGNAL niOO0i : STD_LOGIC := '0'; + SIGNAL niOO1i : STD_LOGIC := '0'; + SIGNAL niOO1l : STD_LOGIC := '0'; + SIGNAL niOO1O : STD_LOGIC := '0'; + SIGNAL niOOOO : STD_LOGIC := '0'; + SIGNAL nl010il : STD_LOGIC := '0'; + SIGNAL nl010iO : STD_LOGIC := '0'; + SIGNAL nl010li : STD_LOGIC := '0'; + SIGNAL nl010ll : STD_LOGIC := '0'; + SIGNAL nl010lO : STD_LOGIC := '0'; + SIGNAL nl010Oi : STD_LOGIC := '0'; + SIGNAL nl010Ol : STD_LOGIC := '0'; + SIGNAL nl010OO : STD_LOGIC := '0'; + SIGNAL nl0110i : STD_LOGIC := '0'; + SIGNAL nl0110l : STD_LOGIC := '0'; + SIGNAL nl0110O : STD_LOGIC := '0'; + SIGNAL nl0111i : STD_LOGIC := '0'; + SIGNAL nl0111l : STD_LOGIC := '0'; + SIGNAL nl0111O : STD_LOGIC := '0'; + SIGNAL nl011ii : STD_LOGIC := '0'; + SIGNAL nl011il : STD_LOGIC := '0'; + SIGNAL nl011iO : STD_LOGIC := '0'; + SIGNAL nl011li : STD_LOGIC := '0'; + SIGNAL nl011ll : STD_LOGIC := '0'; + SIGNAL nl011lO : STD_LOGIC := '0'; + SIGNAL nl01i0i : STD_LOGIC := '0'; + SIGNAL nl01i0l : STD_LOGIC := '0'; + SIGNAL nl01i0O : STD_LOGIC := '0'; + SIGNAL nl01i1i : STD_LOGIC := '0'; + SIGNAL nl01i1l : STD_LOGIC := '0'; + SIGNAL nl01i1O : STD_LOGIC := '0'; + SIGNAL nl01iii : STD_LOGIC := '0'; + SIGNAL nl01iil : STD_LOGIC := '0'; + SIGNAL nl01iiO : STD_LOGIC := '0'; + SIGNAL nl01ili : STD_LOGIC := '0'; + SIGNAL nl01ill : STD_LOGIC := '0'; + SIGNAL nl01ilO : STD_LOGIC := '0'; + SIGNAL nl01iOi : STD_LOGIC := '0'; + SIGNAL nl01iOl : STD_LOGIC := '0'; + SIGNAL nl01iOO : STD_LOGIC := '0'; + SIGNAL nl01l0i : STD_LOGIC := '0'; + SIGNAL nl01l0l : STD_LOGIC := '0'; + SIGNAL nl01l0O : STD_LOGIC := '0'; + SIGNAL nl01l1i : STD_LOGIC := '0'; + SIGNAL nl01l1l : STD_LOGIC := '0'; + SIGNAL nl01l1O : STD_LOGIC := '0'; + SIGNAL nl01lii : STD_LOGIC := '0'; + SIGNAL nl01lil : STD_LOGIC := '0'; + SIGNAL nl01liO : STD_LOGIC := '0'; + SIGNAL nl01lli : STD_LOGIC := '0'; + SIGNAL nl01lll : STD_LOGIC := '0'; + SIGNAL nl01llO : STD_LOGIC := '0'; + SIGNAL nl01lOi : STD_LOGIC := '0'; + SIGNAL nl01lOl : STD_LOGIC := '0'; + SIGNAL nl01lOO : STD_LOGIC := '0'; + SIGNAL nl01O1i : STD_LOGIC := '0'; + SIGNAL nl01O1l : STD_LOGIC := '0'; + SIGNAL nl01O1O : STD_LOGIC := '0'; + SIGNAL nl100l : STD_LOGIC := '0'; + SIGNAL nl100O : STD_LOGIC := '0'; + SIGNAL nl10ii : STD_LOGIC := '0'; + SIGNAL nl10Ol : STD_LOGIC := '0'; + SIGNAL nl110i : STD_LOGIC := '0'; + SIGNAL nl110l : STD_LOGIC := '0'; + SIGNAL nl110O : STD_LOGIC := '0'; + SIGNAL nl111i : STD_LOGIC := '0'; + SIGNAL nl111l : STD_LOGIC := '0'; + SIGNAL nl111O : STD_LOGIC := '0'; + SIGNAL nl11ii : STD_LOGIC := '0'; + SIGNAL nl11il : STD_LOGIC := '0'; + SIGNAL nl11iO : STD_LOGIC := '0'; + SIGNAL nl1ill : STD_LOGIC := '0'; + SIGNAL nl1ilO : STD_LOGIC := '0'; + SIGNAL nl1l1l : STD_LOGIC := '0'; + SIGNAL nl1lii : STD_LOGIC := '0'; + SIGNAL nl1liii : STD_LOGIC := '0'; + SIGNAL nl1liil : STD_LOGIC := '0'; + SIGNAL nl1lOi : STD_LOGIC := '0'; + SIGNAL nl1Oiil : STD_LOGIC := '0'; + SIGNAL nl1OiiO : STD_LOGIC := '0'; + SIGNAL nl1Oili : STD_LOGIC := '0'; + SIGNAL nl1Oill : STD_LOGIC := '0'; + SIGNAL nl1OilO : STD_LOGIC := '0'; + SIGNAL nl1OiOi : STD_LOGIC := '0'; + SIGNAL nl1OiOl : STD_LOGIC := '0'; + SIGNAL nl1OiOO : STD_LOGIC := '0'; + SIGNAL nl1Ol0i : STD_LOGIC := '0'; + SIGNAL nl1Ol0l : STD_LOGIC := '0'; + SIGNAL nl1Ol0O : STD_LOGIC := '0'; + SIGNAL nl1Ol1i : STD_LOGIC := '0'; + SIGNAL nl1Ol1l : STD_LOGIC := '0'; + SIGNAL nl1Ol1O : STD_LOGIC := '0'; + SIGNAL nl1Olii : STD_LOGIC := '0'; + SIGNAL nl1Olil : STD_LOGIC := '0'; + SIGNAL nl1OliO : STD_LOGIC := '0'; + SIGNAL nl1Olli : STD_LOGIC := '0'; + SIGNAL nl1Olll : STD_LOGIC := '0'; + SIGNAL nl1OllO : STD_LOGIC := '0'; + SIGNAL nl1OlOi : STD_LOGIC := '0'; + SIGNAL nl1OlOl : STD_LOGIC := '0'; + SIGNAL nl1OlOO : STD_LOGIC := '0'; + SIGNAL nl1OO0i : STD_LOGIC := '0'; + SIGNAL nl1OO0l : STD_LOGIC := '0'; + SIGNAL nl1OO0O : STD_LOGIC := '0'; + SIGNAL nl1OO1i : STD_LOGIC := '0'; + SIGNAL nl1OO1l : STD_LOGIC := '0'; + SIGNAL nl1OO1O : STD_LOGIC := '0'; + SIGNAL nl1OOii : STD_LOGIC := '0'; + SIGNAL nl1OOil : STD_LOGIC := '0'; + SIGNAL nl1OOiO : STD_LOGIC := '0'; + SIGNAL nl1OOli : STD_LOGIC := '0'; + SIGNAL nl1OOll : STD_LOGIC := '0'; + SIGNAL nl1OOlO : STD_LOGIC := '0'; + SIGNAL nl1OOOi : STD_LOGIC := '0'; + SIGNAL nl1OOOl : STD_LOGIC := '0'; + SIGNAL nl1OOOO : STD_LOGIC := '0'; + SIGNAL nliiOl : STD_LOGIC := '0'; + SIGNAL nliiOO : STD_LOGIC := '0'; + SIGNAL nlil0i : STD_LOGIC := '0'; + SIGNAL nlil0l : STD_LOGIC := '0'; + SIGNAL nlil0O : STD_LOGIC := '0'; + SIGNAL nlil1i : STD_LOGIC := '0'; + SIGNAL nlil1l : STD_LOGIC := '0'; + SIGNAL nlil1O : STD_LOGIC := '0'; + SIGNAL nlilii : STD_LOGIC := '0'; + SIGNAL nlilll : STD_LOGIC := '0'; + SIGNAL nlillO : STD_LOGIC := '0'; + SIGNAL nlilOi : STD_LOGIC := '0'; + SIGNAL nlilOl : STD_LOGIC := '0'; + SIGNAL nlilOO : STD_LOGIC := '0'; + SIGNAL nliO0i : STD_LOGIC := '0'; + SIGNAL nliO0l : STD_LOGIC := '0'; + SIGNAL nliO0O : STD_LOGIC := '0'; + SIGNAL nliO1i : STD_LOGIC := '0'; + SIGNAL nliO1l : STD_LOGIC := '0'; + SIGNAL nliO1O : STD_LOGIC := '0'; + SIGNAL nliOii : STD_LOGIC := '0'; + SIGNAL nliOil : STD_LOGIC := '0'; + SIGNAL nliOiO : STD_LOGIC := '0'; + SIGNAL nliOli : STD_LOGIC := '0'; + SIGNAL nliOll : STD_LOGIC := '0'; + SIGNAL nliOlO : STD_LOGIC := '0'; + SIGNAL nliOOi : STD_LOGIC := '0'; + SIGNAL nliOOl : STD_LOGIC := '0'; + SIGNAL nliOOO : STD_LOGIC := '0'; + SIGNAL nll000i : STD_LOGIC := '0'; + SIGNAL nll000l : STD_LOGIC := '0'; + SIGNAL nll000O : STD_LOGIC := '0'; + SIGNAL nll001i : STD_LOGIC := '0'; + SIGNAL nll001l : STD_LOGIC := '0'; + SIGNAL nll001O : STD_LOGIC := '0'; + SIGNAL nll00ii : STD_LOGIC := '0'; + SIGNAL nll00il : STD_LOGIC := '0'; + SIGNAL nll00iO : STD_LOGIC := '0'; + SIGNAL nll00li : STD_LOGIC := '0'; + SIGNAL nll00ll : STD_LOGIC := '0'; + SIGNAL nll00lO : STD_LOGIC := '0'; + SIGNAL nll00Oi : STD_LOGIC := '0'; + SIGNAL nll00Ol : STD_LOGIC := '0'; + SIGNAL nll00OO : STD_LOGIC := '0'; + SIGNAL nll01ll : STD_LOGIC := '0'; + SIGNAL nll01lO : STD_LOGIC := '0'; + SIGNAL nll01Oi : STD_LOGIC := '0'; + SIGNAL nll01Ol : STD_LOGIC := '0'; + SIGNAL nll01OO : STD_LOGIC := '0'; + SIGNAL nll0i0i : STD_LOGIC := '0'; + SIGNAL nll0i0l : STD_LOGIC := '0'; + SIGNAL nll0i0O : STD_LOGIC := '0'; + SIGNAL nll0i1i : STD_LOGIC := '0'; + SIGNAL nll0i1l : STD_LOGIC := '0'; + SIGNAL nll0i1O : STD_LOGIC := '0'; + SIGNAL nll0iii : STD_LOGIC := '0'; + SIGNAL nll0iil : STD_LOGIC := '0'; + SIGNAL nll0iiO : STD_LOGIC := '0'; + SIGNAL nll0ili : STD_LOGIC := '0'; + SIGNAL nll0ill : STD_LOGIC := '0'; + SIGNAL nll0ilO : STD_LOGIC := '0'; + SIGNAL nll0iOi : STD_LOGIC := '0'; + SIGNAL nll0iOl : STD_LOGIC := '0'; + SIGNAL nll0iOO : STD_LOGIC := '0'; + SIGNAL nll0l0i : STD_LOGIC := '0'; + SIGNAL nll0l0l : STD_LOGIC := '0'; + SIGNAL nll0l0O : STD_LOGIC := '0'; + SIGNAL nll0l1i : STD_LOGIC := '0'; + SIGNAL nll0l1l : STD_LOGIC := '0'; + SIGNAL nll0l1O : STD_LOGIC := '0'; + SIGNAL nll0lii : STD_LOGIC := '0'; + SIGNAL nll0lil : STD_LOGIC := '0'; + SIGNAL nll0liO : STD_LOGIC := '0'; + SIGNAL nll0lli : STD_LOGIC := '0'; + SIGNAL nll0lll : STD_LOGIC := '0'; + SIGNAL nll0llO : STD_LOGIC := '0'; + SIGNAL nll0lOi : STD_LOGIC := '0'; + SIGNAL nll0lOl : STD_LOGIC := '0'; + SIGNAL nll0lOO : STD_LOGIC := '0'; + SIGNAL nll0O0i : STD_LOGIC := '0'; + SIGNAL nll0O0l : STD_LOGIC := '0'; + SIGNAL nll0O0O : STD_LOGIC := '0'; + SIGNAL nll0O1i : STD_LOGIC := '0'; + SIGNAL nll0O1l : STD_LOGIC := '0'; + SIGNAL nll0O1O : STD_LOGIC := '0'; + SIGNAL nll0Oii : STD_LOGIC := '0'; + SIGNAL nll0Oil : STD_LOGIC := '0'; + SIGNAL nll0OiO : STD_LOGIC := '0'; + SIGNAL nll0Oli : STD_LOGIC := '0'; + SIGNAL nll0Oll : STD_LOGIC := '0'; + SIGNAL nll0OlO : STD_LOGIC := '0'; + SIGNAL nll0OOi : STD_LOGIC := '0'; + SIGNAL nll0OOl : STD_LOGIC := '0'; + SIGNAL nll0OOO : STD_LOGIC := '0'; + SIGNAL nll10i : STD_LOGIC := '0'; + SIGNAL nll11i : STD_LOGIC := '0'; + SIGNAL nll11l : STD_LOGIC := '0'; + SIGNAL nll11O : STD_LOGIC := '0'; + SIGNAL nlli00i : STD_LOGIC := '0'; + SIGNAL nlli00l : STD_LOGIC := '0'; + SIGNAL nlli00O : STD_LOGIC := '0'; + SIGNAL nlli01i : STD_LOGIC := '0'; + SIGNAL nlli01l : STD_LOGIC := '0'; + SIGNAL nlli01O : STD_LOGIC := '0'; + SIGNAL nlli0ii : STD_LOGIC := '0'; + SIGNAL nlli0il : STD_LOGIC := '0'; + SIGNAL nlli0iO : STD_LOGIC := '0'; + SIGNAL nlli0li : STD_LOGIC := '0'; + SIGNAL nlli0ll : STD_LOGIC := '0'; + SIGNAL nlli0lO : STD_LOGIC := '0'; + SIGNAL nlli0Oi : STD_LOGIC := '0'; + SIGNAL nlli0Ol : STD_LOGIC := '0'; + SIGNAL nlli0OO : STD_LOGIC := '0'; + SIGNAL nlli10i : STD_LOGIC := '0'; + SIGNAL nlli10l : STD_LOGIC := '0'; + SIGNAL nlli10O : STD_LOGIC := '0'; + SIGNAL nlli11i : STD_LOGIC := '0'; + SIGNAL nlli11l : STD_LOGIC := '0'; + SIGNAL nlli11O : STD_LOGIC := '0'; + SIGNAL nlli1ii : STD_LOGIC := '0'; + SIGNAL nlli1il : STD_LOGIC := '0'; + SIGNAL nlli1iO : STD_LOGIC := '0'; + SIGNAL nlli1li : STD_LOGIC := '0'; + SIGNAL nlli1ll : STD_LOGIC := '0'; + SIGNAL nlli1lO : STD_LOGIC := '0'; + SIGNAL nlli1Oi : STD_LOGIC := '0'; + SIGNAL nlli1Ol : STD_LOGIC := '0'; + SIGNAL nlli1OO : STD_LOGIC := '0'; + SIGNAL nllii0i : STD_LOGIC := '0'; + SIGNAL nllii0l : STD_LOGIC := '0'; + SIGNAL nllii1i : STD_LOGIC := '0'; + SIGNAL nllii1l : STD_LOGIC := '0'; + SIGNAL nllii1O : STD_LOGIC := '0'; + SIGNAL nllll1i : STD_LOGIC := '0'; + SIGNAL nlllOl : STD_LOGIC := '0'; + SIGNAL nlllOO : STD_LOGIC := '0'; + SIGNAL nlO : STD_LOGIC := '0'; + SIGNAL nlO000i : STD_LOGIC := '0'; + SIGNAL nlO000l : STD_LOGIC := '0'; + SIGNAL nlO000O : STD_LOGIC := '0'; + SIGNAL nlO001i : STD_LOGIC := '0'; + SIGNAL nlO001l : STD_LOGIC := '0'; + SIGNAL nlO001O : STD_LOGIC := '0'; + SIGNAL nlO00ii : STD_LOGIC := '0'; + SIGNAL nlO00il : STD_LOGIC := '0'; + SIGNAL nlO00iO : STD_LOGIC := '0'; + SIGNAL nlO00li : STD_LOGIC := '0'; + SIGNAL nlO00ll : STD_LOGIC := '0'; + SIGNAL nlO00lO : STD_LOGIC := '0'; + SIGNAL nlO00Oi : STD_LOGIC := '0'; + SIGNAL nlO00Ol : STD_LOGIC := '0'; + SIGNAL nlO00OO : STD_LOGIC := '0'; + SIGNAL nlO010i : STD_LOGIC := '0'; + SIGNAL nlO010l : STD_LOGIC := '0'; + SIGNAL nlO011i : STD_LOGIC := '0'; + SIGNAL nlO011l : STD_LOGIC := '0'; + SIGNAL nlO011O : STD_LOGIC := '0'; + SIGNAL nlO01ii : STD_LOGIC := '0'; + SIGNAL nlO01il : STD_LOGIC := '0'; + SIGNAL nlO01iO : STD_LOGIC := '0'; + SIGNAL nlO01li : STD_LOGIC := '0'; + SIGNAL nlO01ll : STD_LOGIC := '0'; + SIGNAL nlO01lO : STD_LOGIC := '0'; + SIGNAL nlO01Oi : STD_LOGIC := '0'; + SIGNAL nlO01Ol : STD_LOGIC := '0'; + SIGNAL nlO01OO : STD_LOGIC := '0'; + SIGNAL nlO0i0i : STD_LOGIC := '0'; + SIGNAL nlO0i0l : STD_LOGIC := '0'; + SIGNAL nlO0i0O : STD_LOGIC := '0'; + SIGNAL nlO0i1i : STD_LOGIC := '0'; + SIGNAL nlO0i1l : STD_LOGIC := '0'; + SIGNAL nlO0i1O : STD_LOGIC := '0'; + SIGNAL nlO0iii : STD_LOGIC := '0'; + SIGNAL nlO0iil : STD_LOGIC := '0'; + SIGNAL nlO0iiO : STD_LOGIC := '0'; + SIGNAL nlO0ili : STD_LOGIC := '0'; + SIGNAL nlO0ill : STD_LOGIC := '0'; + SIGNAL nlO0ilO : STD_LOGIC := '0'; + SIGNAL nlO0l1i : STD_LOGIC := '0'; + SIGNAL nlO0l1l : STD_LOGIC := '0'; + SIGNAL nlO0l1O : STD_LOGIC := '0'; + SIGNAL nlOi0ll : STD_LOGIC := '0'; + SIGNAL nlOi0lO : STD_LOGIC := '0'; + SIGNAL nlOi0Oi : STD_LOGIC := '0'; + SIGNAL nlOi0Ol : STD_LOGIC := '0'; + SIGNAL nlOi0OO : STD_LOGIC := '0'; + SIGNAL nlOii0i : STD_LOGIC := '0'; + SIGNAL nlOii0l : STD_LOGIC := '0'; + SIGNAL nlOii0O : STD_LOGIC := '0'; + SIGNAL nlOii1i : STD_LOGIC := '0'; + SIGNAL nlOii1l : STD_LOGIC := '0'; + SIGNAL nlOii1O : STD_LOGIC := '0'; + SIGNAL nlOiiii : STD_LOGIC := '0'; + SIGNAL nlOiiil : STD_LOGIC := '0'; + SIGNAL nlOiiiO : STD_LOGIC := '0'; + SIGNAL nlOiili : STD_LOGIC := '0'; + SIGNAL nlOiill : STD_LOGIC := '0'; + SIGNAL nlOiilO : STD_LOGIC := '0'; + SIGNAL nlOilOl : STD_LOGIC := '0'; + SIGNAL nlOilOO : STD_LOGIC := '0'; + SIGNAL nlOiO0i : STD_LOGIC := '0'; + SIGNAL nlOiO0l : STD_LOGIC := '0'; + SIGNAL nlOiO1i : STD_LOGIC := '0'; + SIGNAL nlOiO1l : STD_LOGIC := '0'; + SIGNAL nlOiO1O : STD_LOGIC := '0'; + SIGNAL nO : STD_LOGIC := '0'; + SIGNAL wire_nl_CLRN : STD_LOGIC; + SIGNAL wire_nl_w16422w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w16418w16419w16420w16421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w16418w16419w16420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w16418w16419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w16418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w16414w16415w16416w16417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w16414w16415w16416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w16414w16415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w2928w2929w2930w2931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w16414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w2928w2929w2930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w16410w16411w16412w16413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w2928w2929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w16410w16411w16412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w2928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w16410w16411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w_lg_nl1lOi2612w2925w2926w2927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w16410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlil0l2177w2182w2187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nl1lOi2612w2925w2926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nll0OOl16010w16408w16409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlil0l2177w2182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlilii2175w2180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlli01O14427w14432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlli1Ol14429w14434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlOiill322w325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nl1lOi2612w2925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nll0OOl16010w16408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_niii0i1208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1liil17114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1lOi2945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlil0l2177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlilii2175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nll0OOl16448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli01O14427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1Ol14429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO0l1l232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOi0lO395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOi0Ol387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOii0l363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOii1i379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOii1O371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOiiii355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOiiiO337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOiill322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_w_lg_nlilii2087w2094w2101w2102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w14161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlilii2087w2088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlli01O14146w14147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n0101il16151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n010Ol2709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n011l1l16150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n011l1O16156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n1OiOi2540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n1OOOl2708w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_n1OOOO2714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_niii0i1195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_niii0l3438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_niiill3373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl100l905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1ill312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1l1l1933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1liil17102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nl1lOi2612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nliiOl2604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nliiOO2596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlil0i2588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlil0l2618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlil0O2616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlil1i2594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlil1l2592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlil1O2590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlilii2911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nll01ll7899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nll01lO4501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nll0OOl16010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nll0OOO15999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli00l4491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli01i16015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli01l16013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli01O16384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli0lO15746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli0OO4494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli10i15955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli10l15944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli10O15942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli11i15988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli11l15977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli11O15966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1ii15940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1il15938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1iO15936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1li15934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1ll15932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1lO15930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1Oi15928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1Ol16019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli1OO16017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nllii0i4486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nllii1O4488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00il4415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00iO4413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00li4411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00ll4409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00lO4407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00Oi4405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00Ol4403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO00OO4401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO010l3809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO0i1i4400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlO0l1l246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOi0ll394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOi0Oi386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOi0OO378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOii0i362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOii0O354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOii1l370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOiiil336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlOiili321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlilii2087w2094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_w_lg_nlli01O14146w14153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlilii2087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nlli01O14146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl10il : STD_LOGIC := '0'; + SIGNAL nl10li : STD_LOGIC := '0'; + SIGNAL nl10ll : STD_LOGIC := '0'; + SIGNAL nl10Oi : STD_LOGIC := '0'; + SIGNAL wire_nl10lO_CLRN : STD_LOGIC; + SIGNAL wire_nl10lO_w_lg_nl10il1929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lO_w_lg_nl10li1927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lO_w_lg_nl10ll1925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lO_w_lg_nl10Oi1924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl1lil : STD_LOGIC := '0'; + SIGNAL nl1liO : STD_LOGIC := '0'; + SIGNAL nl1lli : STD_LOGIC := '0'; + SIGNAL nl1llO : STD_LOGIC := '0'; + SIGNAL nlilil : STD_LOGIC := '0'; + SIGNAL nliliO : STD_LOGIC := '0'; + SIGNAL nlilli : STD_LOGIC := '0'; + SIGNAL nll10l : STD_LOGIC := '0'; + SIGNAL nll1ii : STD_LOGIC := '0'; + SIGNAL wire_nll10O_PRN : STD_LOGIC; + SIGNAL wire_nll10O_ENA : STD_LOGIC; + SIGNAL n1O01l : STD_LOGIC := '0'; + SIGNAL n1OO01O : STD_LOGIC := '0'; + SIGNAL nil1Oi : STD_LOGIC := '0'; + SIGNAL nl0100i : STD_LOGIC := '0'; + SIGNAL nl0100l : STD_LOGIC := '0'; + SIGNAL nl0100O : STD_LOGIC := '0'; + SIGNAL nl0101i : STD_LOGIC := '0'; + SIGNAL nl0101l : STD_LOGIC := '0'; + SIGNAL nl0101O : STD_LOGIC := '0'; + SIGNAL nl010ii : STD_LOGIC := '0'; + SIGNAL nl011Oi : STD_LOGIC := '0'; + SIGNAL nl011Ol : STD_LOGIC := '0'; + SIGNAL nl011OO : STD_LOGIC := '0'; + SIGNAL nl1iOi : STD_LOGIC := '0'; + SIGNAL nl1iOl : STD_LOGIC := '0'; + SIGNAL nl1iOO : STD_LOGIC := '0'; + SIGNAL nl1l1i : STD_LOGIC := '0'; + SIGNAL nll01li : STD_LOGIC := '0'; + SIGNAL nll1il : STD_LOGIC := '0'; + SIGNAL nlli0l : STD_LOGIC := '0'; + SIGNAL nlli0O : STD_LOGIC := '0'; + SIGNAL nlliii : STD_LOGIC := '0'; + SIGNAL nllO1l : STD_LOGIC := '0'; + SIGNAL nlO010O : STD_LOGIC := '0'; + SIGNAL wire_nllO1i_CLRN : STD_LOGIC; + SIGNAL wire_nllO1i_w_lg_nil1Oi3372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO1i_w_lg_nll01li7901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i_dataout : STD_LOGIC; + SIGNAL wire_n00l_dataout : STD_LOGIC; + SIGNAL wire_n00O_dataout : STD_LOGIC; + SIGNAL wire_n0100i_dataout : STD_LOGIC; + SIGNAL wire_n0100iO_dataout : STD_LOGIC; + SIGNAL wire_n0100l_dataout : STD_LOGIC; + SIGNAL wire_n0100li_dataout : STD_LOGIC; + SIGNAL wire_n0100ll_dataout : STD_LOGIC; + SIGNAL wire_n0100lO_dataout : STD_LOGIC; + SIGNAL wire_n0100O_dataout : STD_LOGIC; + SIGNAL wire_n0100Oi_dataout : STD_LOGIC; + SIGNAL wire_n0100Ol_dataout : STD_LOGIC; + SIGNAL wire_n0100OO_dataout : STD_LOGIC; + SIGNAL wire_n01010i_dataout : STD_LOGIC; + SIGNAL wire_n01010l_dataout : STD_LOGIC; + SIGNAL wire_n01010O_dataout : STD_LOGIC; + SIGNAL wire_n01011i_dataout : STD_LOGIC; + SIGNAL wire_n01011l_dataout : STD_LOGIC; + SIGNAL wire_n01011O_dataout : STD_LOGIC; + SIGNAL wire_n0101i_dataout : STD_LOGIC; + SIGNAL wire_n0101ii_dataout : STD_LOGIC; + SIGNAL wire_n0101l_dataout : STD_LOGIC; + SIGNAL wire_n0101O_dataout : STD_LOGIC; + SIGNAL wire_n010i0i_dataout : STD_LOGIC; + SIGNAL wire_n010i0l_dataout : STD_LOGIC; + SIGNAL wire_n010i0O_dataout : STD_LOGIC; + SIGNAL wire_n010i1i_dataout : STD_LOGIC; + SIGNAL wire_n010i1l_dataout : STD_LOGIC; + SIGNAL wire_n010i1O_dataout : STD_LOGIC; + SIGNAL wire_n010ii_dataout : STD_LOGIC; + SIGNAL wire_n010iii_dataout : STD_LOGIC; + SIGNAL wire_n010iil_dataout : STD_LOGIC; + SIGNAL wire_n010iiO_dataout : STD_LOGIC; + SIGNAL wire_n010il_dataout : STD_LOGIC; + SIGNAL wire_n010ili_dataout : STD_LOGIC; + SIGNAL wire_n010iO_dataout : STD_LOGIC; + SIGNAL wire_n010li_dataout : STD_LOGIC; + SIGNAL wire_n010ll_dataout : STD_LOGIC; + SIGNAL wire_n010lO_dataout : STD_LOGIC; + SIGNAL wire_n010Oi_dataout : STD_LOGIC; + SIGNAL wire_n0110il_dataout : STD_LOGIC; + SIGNAL wire_n0110il_w_lg_dataout15757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0110iO_dataout : STD_LOGIC; + SIGNAL wire_n0110iO_w_lg_dataout16493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0110li_dataout : STD_LOGIC; + SIGNAL wire_n0110li_w_lg_dataout16491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0110ll_dataout : STD_LOGIC; + SIGNAL wire_n0110lO_dataout : STD_LOGIC; + SIGNAL wire_n0110lO_w_lg_dataout16488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0110Oi_dataout : STD_LOGIC; + SIGNAL wire_n0110Oi_w_lg_dataout16486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0110Ol_dataout : STD_LOGIC; + SIGNAL wire_n0110Ol_w_lg_dataout16484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0110OO_dataout : STD_LOGIC; + SIGNAL wire_n0110OO_w_lg_dataout16482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i0i_dataout : STD_LOGIC; + SIGNAL wire_n011i0l_dataout : STD_LOGIC; + SIGNAL wire_n011i0O_dataout : STD_LOGIC; + SIGNAL wire_n011i1i_dataout : STD_LOGIC; + SIGNAL wire_n011i1i_w_lg_dataout16480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1l_dataout : STD_LOGIC; + SIGNAL wire_n011i1l_w_lg_w_lg_w_lg_w16485w16487w16489w16490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1l_w_lg_w_lg_w16485w16487w16489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1l_w_lg_w16485w16487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1l_w16485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1l_w_lg_w_lg_w_lg_dataout16479w16481w16483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1l_w_lg_w_lg_dataout16479w16481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1l_w_lg_dataout16479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n011i1O_dataout : STD_LOGIC; + SIGNAL wire_n011iii_dataout : STD_LOGIC; + SIGNAL wire_n011iil_dataout : STD_LOGIC; + SIGNAL wire_n011iiO_dataout : STD_LOGIC; + SIGNAL wire_n011ill_dataout : STD_LOGIC; + SIGNAL wire_n011ilO_dataout : STD_LOGIC; + SIGNAL wire_n011iOi_dataout : STD_LOGIC; + SIGNAL wire_n011iOl_dataout : STD_LOGIC; + SIGNAL wire_n011iOO_dataout : STD_LOGIC; + SIGNAL wire_n011l1i_dataout : STD_LOGIC; + SIGNAL wire_n011O0l_dataout : STD_LOGIC; + SIGNAL wire_n011O0O_dataout : STD_LOGIC; + SIGNAL wire_n011Oii_dataout : STD_LOGIC; + SIGNAL wire_n011Oil_dataout : STD_LOGIC; + SIGNAL wire_n011OiO_dataout : STD_LOGIC; + SIGNAL wire_n011Ol_dataout : STD_LOGIC; + SIGNAL wire_n011Oli_dataout : STD_LOGIC; + SIGNAL wire_n011Oll_dataout : STD_LOGIC; + SIGNAL wire_n011OlO_dataout : STD_LOGIC; + SIGNAL wire_n011OO_dataout : STD_LOGIC; + SIGNAL wire_n011OOi_dataout : STD_LOGIC; + SIGNAL wire_n011OOl_dataout : STD_LOGIC; + SIGNAL wire_n011OOO_dataout : STD_LOGIC; + SIGNAL wire_n01i_dataout : STD_LOGIC; + SIGNAL wire_n01ilO_dataout : STD_LOGIC; + SIGNAL wire_n01iOi_dataout : STD_LOGIC; + SIGNAL wire_n01iOl_dataout : STD_LOGIC; + SIGNAL wire_n01iOO_dataout : STD_LOGIC; + SIGNAL wire_n01l_dataout : STD_LOGIC; + SIGNAL wire_n01l0i_dataout : STD_LOGIC; + SIGNAL wire_n01l0l_dataout : STD_LOGIC; + SIGNAL wire_n01l0O_dataout : STD_LOGIC; + SIGNAL wire_n01l1i_dataout : STD_LOGIC; + SIGNAL wire_n01l1l_dataout : STD_LOGIC; + SIGNAL wire_n01l1O_dataout : STD_LOGIC; + SIGNAL wire_n01lii_dataout : STD_LOGIC; + SIGNAL wire_n01lil_dataout : STD_LOGIC; + SIGNAL wire_n01liO_dataout : STD_LOGIC; + SIGNAL wire_n01lli_dataout : STD_LOGIC; + SIGNAL wire_n01O_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii_dataout : STD_LOGIC; + SIGNAL wire_n0il_dataout : STD_LOGIC; + SIGNAL wire_n0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0li_dataout : STD_LOGIC; + SIGNAL wire_n0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n10i_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n110ll_dataout : STD_LOGIC; + SIGNAL wire_n11i_dataout : STD_LOGIC; + SIGNAL wire_n11l_dataout : STD_LOGIC; + SIGNAL wire_n11O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii_dataout : STD_LOGIC; + SIGNAL wire_n1il_dataout : STD_LOGIC; + SIGNAL wire_n1iliii_dataout : STD_LOGIC; + SIGNAL wire_n1iliii_w_lg_w_lg_dataout17118w17148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iliii_w_lg_dataout17118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO_dataout : STD_LOGIC; + SIGNAL wire_n1l11lO_dataout : STD_LOGIC; + SIGNAL wire_n1l11lO_w_lg_dataout16770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l11lO_w_lg_dataout16758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l1Ol_w_lg_dataout173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1li_dataout : STD_LOGIC; + SIGNAL wire_n1li0l_dataout : STD_LOGIC; + SIGNAL wire_n1li0O_dataout : STD_LOGIC; + SIGNAL wire_n1li1i_dataout : STD_LOGIC; + SIGNAL wire_n1li1l_dataout : STD_LOGIC; + SIGNAL wire_n1liil_dataout : STD_LOGIC; + SIGNAL wire_n1liiO_dataout : STD_LOGIC; + SIGNAL wire_n1liO0O_dataout : STD_LOGIC; + SIGNAL wire_n1liO0O_w_lg_dataout4506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lliO_dataout : STD_LOGIC; + SIGNAL wire_n1lllii_dataout : STD_LOGIC; + SIGNAL wire_n1lllii_w_lg_w_lg_dataout16774w16804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lllii_w_lg_dataout16774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1llOl_dataout : STD_LOGIC; + SIGNAL wire_n1llOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O_dataout : STD_LOGIC; + SIGNAL wire_n1lOii_dataout : STD_LOGIC; + SIGNAL wire_n1lOil_dataout : STD_LOGIC; + SIGNAL wire_n1lOiO_dataout : STD_LOGIC; + SIGNAL wire_n1lOlO_dataout : STD_LOGIC; + SIGNAL wire_n1lOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOOO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O00i_dataout : STD_LOGIC; + SIGNAL wire_n1O00i_w_lg_dataout2967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O00l_dataout : STD_LOGIC; + SIGNAL wire_n1O00l_w_lg_dataout2965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O00O_dataout : STD_LOGIC; + SIGNAL wire_n1O0ii_dataout : STD_LOGIC; + SIGNAL wire_n1O0ii_w_lg_dataout2962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0il_dataout : STD_LOGIC; + SIGNAL wire_n1O0il_w_lg_dataout2960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0iO_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO_w_lg_dataout2958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0li_dataout : STD_LOGIC; + SIGNAL wire_n1O0li_w_lg_dataout2956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0ll_dataout : STD_LOGIC; + SIGNAL wire_n1O0ll_w_lg_w2963w2964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0ll_w2963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0ll_w_lg_w_lg_w_lg_w_lg_dataout2955w2957w2959w2961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0ll_w_lg_w_lg_w_lg_dataout2955w2957w2959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0ll_w_lg_w_lg_dataout2955w2957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0ll_w_lg_dataout2955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O10i_dataout : STD_LOGIC; + SIGNAL wire_n1O10l_dataout : STD_LOGIC; + SIGNAL wire_n1O10lO_dataout : STD_LOGIC; + SIGNAL wire_n1O10O_dataout : STD_LOGIC; + SIGNAL wire_n1O11l_dataout : STD_LOGIC; + SIGNAL wire_n1O11O_dataout : STD_LOGIC; + SIGNAL wire_n1O1iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1li_dataout : STD_LOGIC; + SIGNAL wire_n1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oili_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0li_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10O_w_lg_dataout4507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oli0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oli0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oli1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oli1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oli1O_dataout : STD_LOGIC; + SIGNAL wire_n1Ollil_dataout : STD_LOGIC; + SIGNAL wire_n1OllOi_dataout : STD_LOGIC; + SIGNAL wire_n1OllOl_dataout : STD_LOGIC; + SIGNAL wire_n1OllOO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OlOii_dataout : STD_LOGIC; + SIGNAL wire_n1OlOil_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO10i_dataout : STD_LOGIC; + SIGNAL wire_n1OO10l_dataout : STD_LOGIC; + SIGNAL wire_n1OO10O_dataout : STD_LOGIC; + SIGNAL wire_n1OO11i_dataout : STD_LOGIC; + SIGNAL wire_n1OO11O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1OO1li_dataout : STD_LOGIC; + SIGNAL wire_n1OO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOOi_w_lg_dataout2538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO_w_lg_dataout2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nii00i_dataout : STD_LOGIC; + SIGNAL wire_nii00l_dataout : STD_LOGIC; + SIGNAL wire_nii00O_dataout : STD_LOGIC; + SIGNAL wire_nii01i_dataout : STD_LOGIC; + SIGNAL wire_nii01l_dataout : STD_LOGIC; + SIGNAL wire_nii01O_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0ii_dataout : STD_LOGIC; + SIGNAL wire_nii0il_dataout : STD_LOGIC; + SIGNAL wire_nii0iO_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0li_dataout : STD_LOGIC; + SIGNAL wire_nii0ll_dataout : STD_LOGIC; + SIGNAL wire_nii0lO_dataout : STD_LOGIC; + SIGNAL wire_nii0O_dataout : STD_LOGIC; + SIGNAL wire_nii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nii0OO_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niii1i_dataout : STD_LOGIC; + SIGNAL wire_niii1l_dataout : STD_LOGIC; + SIGNAL wire_niii1O_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niiiOO_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niil0i_dataout : STD_LOGIC; + SIGNAL wire_niil0l_dataout : STD_LOGIC; + SIGNAL wire_niil0O_dataout : STD_LOGIC; + SIGNAL wire_niil1i_dataout : STD_LOGIC; + SIGNAL wire_niil1l_dataout : STD_LOGIC; + SIGNAL wire_niil1O_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niilii_dataout : STD_LOGIC; + SIGNAL wire_niilil_dataout : STD_LOGIC; + SIGNAL wire_niiliO_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilli_dataout : STD_LOGIC; + SIGNAL wire_niilll_dataout : STD_LOGIC; + SIGNAL wire_niillO_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niilOi_dataout : STD_LOGIC; + SIGNAL wire_niilOl_dataout : STD_LOGIC; + SIGNAL wire_niilOO_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_niiO0i_dataout : STD_LOGIC; + SIGNAL wire_niiO0i_w_lg_dataout2058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO0l_dataout : STD_LOGIC; + SIGNAL wire_niiO0l_w_lg_dataout2062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO0O_dataout : STD_LOGIC; + SIGNAL wire_niiO0O_w_lg_dataout2066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO1i_dataout : STD_LOGIC; + SIGNAL wire_niiO1i_w_lg_dataout2047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO1l_dataout : STD_LOGIC; + SIGNAL wire_niiO1l_w_lg_dataout2050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO1O_dataout : STD_LOGIC; + SIGNAL wire_niiO1O_w_lg_dataout2054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOii_dataout : STD_LOGIC; + SIGNAL wire_niiOii_w_lg_dataout2070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiOil_dataout : STD_LOGIC; + SIGNAL wire_niiOil_w_lg_dataout2074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiOiO_dataout : STD_LOGIC; + SIGNAL wire_niiOiO_w_lg_dataout2078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOli_dataout : STD_LOGIC; + SIGNAL wire_niiOli_w_lg_dataout2082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil10l_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nillii_dataout : STD_LOGIC; + SIGNAL wire_nillil_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nilllO_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nillOi_dataout : STD_LOGIC; + SIGNAL wire_nillOl_dataout : STD_LOGIC; + SIGNAL wire_nillOO_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_nilO0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOii_dataout : STD_LOGIC; + SIGNAL wire_nilOil_dataout : STD_LOGIC; + SIGNAL wire_nilOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOli_dataout : STD_LOGIC; + SIGNAL wire_nilOll_dataout : STD_LOGIC; + SIGNAL wire_nilOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOO_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO10l_dataout : STD_LOGIC; + SIGNAL wire_niO10O_dataout : STD_LOGIC; + SIGNAL wire_niO11i_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1ii_dataout : STD_LOGIC; + SIGNAL wire_niO1il_dataout : STD_LOGIC; + SIGNAL wire_niO1iO_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1li_dataout : STD_LOGIC; + SIGNAL wire_niO1ll_dataout : STD_LOGIC; + SIGNAL wire_niO1lO_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOiii_dataout : STD_LOGIC; + SIGNAL wire_niOiil_dataout : STD_LOGIC; + SIGNAL wire_niOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOili_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0i_w_lg_w_lg_dataout1313w3182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_w_lg_dataout1313w3202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_w_lg_dataout1313w3199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_w_lg_dataout1313w3221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_w_lg_dataout1313w3216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_w_lg_dataout1313w3018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout2997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout1320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout2981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout3017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_dataout1313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_w_lg_dataout3179w3183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0i_w_lg_w_lg_dataout3017w3019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0l_w_lg_w_lg_dataout3064w3066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_w_lg_dataout1312w3091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout1321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout2982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout1312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl0l_w_lg_dataout3061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0000i_dataout : STD_LOGIC; + SIGNAL wire_nl0000l_dataout : STD_LOGIC; + SIGNAL wire_nl0000O_dataout : STD_LOGIC; + SIGNAL wire_nl0001i_dataout : STD_LOGIC; + SIGNAL wire_nl0001l_dataout : STD_LOGIC; + SIGNAL wire_nl0001O_dataout : STD_LOGIC; + SIGNAL wire_nl000i_dataout : STD_LOGIC; + SIGNAL wire_nl000i_w_lg_dataout421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl000ii_dataout : STD_LOGIC; + SIGNAL wire_nl000il_dataout : STD_LOGIC; + SIGNAL wire_nl000iO_dataout : STD_LOGIC; + SIGNAL wire_nl000li_dataout : STD_LOGIC; + SIGNAL wire_nl000ll_dataout : STD_LOGIC; + SIGNAL wire_nl000lO_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000OO_dataout : STD_LOGIC; + SIGNAL wire_nl0010i_dataout : STD_LOGIC; + SIGNAL wire_nl0010l_dataout : STD_LOGIC; + SIGNAL wire_nl0010O_dataout : STD_LOGIC; + SIGNAL wire_nl0011i_dataout : STD_LOGIC; + SIGNAL wire_nl0011l_dataout : STD_LOGIC; + SIGNAL wire_nl0011O_dataout : STD_LOGIC; + SIGNAL wire_nl001i_dataout : STD_LOGIC; + SIGNAL wire_nl001i_w_lg_dataout415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl001ii_dataout : STD_LOGIC; + SIGNAL wire_nl001il_dataout : STD_LOGIC; + SIGNAL wire_nl001iO_dataout : STD_LOGIC; + SIGNAL wire_nl001li_dataout : STD_LOGIC; + SIGNAL wire_nl001ll_dataout : STD_LOGIC; + SIGNAL wire_nl001lO_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol_dataout : STD_LOGIC; + SIGNAL wire_nl001OO_dataout : STD_LOGIC; + SIGNAL wire_nl00i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0O_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1O_dataout : STD_LOGIC; + SIGNAL wire_nl00ii_dataout : STD_LOGIC; + SIGNAL wire_nl00ii_w_lg_dataout428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00iii_dataout : STD_LOGIC; + SIGNAL wire_nl00iil_dataout : STD_LOGIC; + SIGNAL wire_nl00iiO_dataout : STD_LOGIC; + SIGNAL wire_nl00ili_dataout : STD_LOGIC; + SIGNAL wire_nl00ill_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iOl_dataout : STD_LOGIC; + SIGNAL wire_nl00iOO_dataout : STD_LOGIC; + SIGNAL wire_nl00l_dataout : STD_LOGIC; + SIGNAL wire_nl00l1i_dataout : STD_LOGIC; + SIGNAL wire_nl00l1l_dataout : STD_LOGIC; + SIGNAL wire_nl00l1O_dataout : STD_LOGIC; + SIGNAL wire_nl00li_dataout : STD_LOGIC; + SIGNAL wire_nl00li_w_lg_dataout436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi_w_lg_dataout1914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010l_dataout : STD_LOGIC; + SIGNAL wire_nl010l_w_lg_dataout401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011i_dataout : STD_LOGIC; + SIGNAL wire_nl011l_dataout : STD_LOGIC; + SIGNAL wire_nl011O_dataout : STD_LOGIC; + SIGNAL wire_nl011O_w_lg_dataout1922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011O_w_lg_dataout446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01i_dataout : STD_LOGIC; + SIGNAL wire_nl01ii_dataout : STD_LOGIC; + SIGNAL wire_nl01ii_w_lg_dataout403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_dataout : STD_LOGIC; + SIGNAL wire_nl01li_dataout : STD_LOGIC; + SIGNAL wire_nl01li_w_lg_dataout406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi_w_lg_dataout410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01Oii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i00i_dataout : STD_LOGIC; + SIGNAL wire_nl0i00l_dataout : STD_LOGIC; + SIGNAL wire_nl0i00O_dataout : STD_LOGIC; + SIGNAL wire_nl0i01i_dataout : STD_LOGIC; + SIGNAL wire_nl0i01l_dataout : STD_LOGIC; + SIGNAL wire_nl0i01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0il_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0li_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0iili_dataout : STD_LOGIC; + SIGNAL wire_nl0iill_dataout : STD_LOGIC; + SIGNAL wire_nl0iilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0il0i_dataout : STD_LOGIC; + SIGNAL wire_nl0il0l_dataout : STD_LOGIC; + SIGNAL wire_nl0il0O_dataout : STD_LOGIC; + SIGNAL wire_nl0il1i_dataout : STD_LOGIC; + SIGNAL wire_nl0il1l_dataout : STD_LOGIC; + SIGNAL wire_nl0il1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0ilii_dataout : STD_LOGIC; + SIGNAL wire_nl0ilil_dataout : STD_LOGIC; + SIGNAL wire_nl0iliO_dataout : STD_LOGIC; + SIGNAL wire_nl0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0illi_dataout : STD_LOGIC; + SIGNAL wire_nl0illO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOli_dataout : STD_LOGIC; + SIGNAL wire_nl0iOll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l00i_dataout : STD_LOGIC; + SIGNAL wire_nl0l01i_dataout : STD_LOGIC; + SIGNAL wire_nl0l01l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0il_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l11i_dataout : STD_LOGIC; + SIGNAL wire_nl0l11l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1il_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl10l_dataout : STD_LOGIC; + SIGNAL wire_nl10O_dataout : STD_LOGIC; + SIGNAL wire_nl10OO_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l00i_dataout : STD_LOGIC; + SIGNAL wire_nl1l00l_dataout : STD_LOGIC; + SIGNAL wire_nl1l00O_dataout : STD_LOGIC; + SIGNAL wire_nl1l01i_dataout : STD_LOGIC; + SIGNAL wire_nl1l01l_dataout : STD_LOGIC; + SIGNAL wire_nl1l01O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0il_dataout : STD_LOGIC; + SIGNAL wire_nl1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0li_dataout : STD_LOGIC; + SIGNAL wire_nl1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1li_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O00l_dataout : STD_LOGIC; + SIGNAL wire_nl1O00O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli00i_dataout : STD_LOGIC; + SIGNAL wire_nli00l_dataout : STD_LOGIC; + SIGNAL wire_nli00O_dataout : STD_LOGIC; + SIGNAL wire_nli01i_dataout : STD_LOGIC; + SIGNAL wire_nli01l_dataout : STD_LOGIC; + SIGNAL wire_nli01O_dataout : STD_LOGIC; + SIGNAL wire_nli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0il_dataout : STD_LOGIC; + SIGNAL wire_nli0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0OO_dataout : STD_LOGIC; + SIGNAL wire_nli10i_dataout : STD_LOGIC; + SIGNAL wire_nli10l_dataout : STD_LOGIC; + SIGNAL wire_nli10O_dataout : STD_LOGIC; + SIGNAL wire_nli11i_dataout : STD_LOGIC; + SIGNAL wire_nli11l_dataout : STD_LOGIC; + SIGNAL wire_nli11O_dataout : STD_LOGIC; + SIGNAL wire_nli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1ii_dataout : STD_LOGIC; + SIGNAL wire_nli1il_dataout : STD_LOGIC; + SIGNAL wire_nli1iO_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1li_dataout : STD_LOGIC; + SIGNAL wire_nli1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlii0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1O_dataout : STD_LOGIC; + SIGNAL wire_nliii_dataout : STD_LOGIC; + SIGNAL wire_nliiii_dataout : STD_LOGIC; + SIGNAL wire_nliiil_dataout : STD_LOGIC; + SIGNAL wire_nliiiO_dataout : STD_LOGIC; + SIGNAL wire_nliil_dataout : STD_LOGIC; + SIGNAL wire_nliili_dataout : STD_LOGIC; + SIGNAL wire_nliill_dataout : STD_LOGIC; + SIGNAL wire_nliilO_dataout : STD_LOGIC; + SIGNAL wire_nliiO_dataout : STD_LOGIC; + SIGNAL wire_nliiOi_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlili_dataout : STD_LOGIC; + SIGNAL wire_nlill_dataout : STD_LOGIC; + SIGNAL wire_nlilO_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nll00i_dataout : STD_LOGIC; + SIGNAL wire_nll00l_dataout : STD_LOGIC; + SIGNAL wire_nll00O_dataout : STD_LOGIC; + SIGNAL wire_nll01i_dataout : STD_LOGIC; + SIGNAL wire_nll01l_dataout : STD_LOGIC; + SIGNAL wire_nll01O_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0il_dataout : STD_LOGIC; + SIGNAL wire_nll0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0li_dataout : STD_LOGIC; + SIGNAL wire_nll0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0OO_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1li_dataout : STD_LOGIC; + SIGNAL wire_nll1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1lOi_dataout : STD_LOGIC; + SIGNAL wire_nll1lOl_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nll1O0i_dataout : STD_LOGIC; + SIGNAL wire_nll1O0l_dataout : STD_LOGIC; + SIGNAL wire_nll1O0O_dataout : STD_LOGIC; + SIGNAL wire_nll1O1O_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlli0i_dataout : STD_LOGIC; + SIGNAL wire_nlli1i_dataout : STD_LOGIC; + SIGNAL wire_nlli1l_dataout : STD_LOGIC; + SIGNAL wire_nlli1O_dataout : STD_LOGIC; + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nllii0O_dataout : STD_LOGIC; + SIGNAL wire_nlliiii_dataout : STD_LOGIC; + SIGNAL wire_nlliiil_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO_dataout : STD_LOGIC; + SIGNAL wire_nlliil_dataout : STD_LOGIC; + SIGNAL wire_nlliili_dataout : STD_LOGIC; + SIGNAL wire_nlliill_dataout : STD_LOGIC; + SIGNAL wire_nlliilO_dataout : STD_LOGIC; + SIGNAL wire_nlliiO_dataout : STD_LOGIC; + SIGNAL wire_nlliiOi_dataout : STD_LOGIC; + SIGNAL wire_nlliiOl_dataout : STD_LOGIC; + SIGNAL wire_nlliiOO_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nllil0i_dataout : STD_LOGIC; + SIGNAL wire_nllil0l_dataout : STD_LOGIC; + SIGNAL wire_nllil0O_dataout : STD_LOGIC; + SIGNAL wire_nllil1i_dataout : STD_LOGIC; + SIGNAL wire_nllil1l_dataout : STD_LOGIC; + SIGNAL wire_nllil1O_dataout : STD_LOGIC; + SIGNAL wire_nllili_dataout : STD_LOGIC; + SIGNAL wire_nllilii_dataout : STD_LOGIC; + SIGNAL wire_nllilil_dataout : STD_LOGIC; + SIGNAL wire_nlliliO_dataout : STD_LOGIC; + SIGNAL wire_nllill_dataout : STD_LOGIC; + SIGNAL wire_nllilli_dataout : STD_LOGIC; + SIGNAL wire_nllilO_dataout : STD_LOGIC; + SIGNAL wire_nllilOO_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i_dataout : STD_LOGIC; + SIGNAL wire_nlliOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOO_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nlll0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0O_dataout : STD_LOGIC; + SIGNAL wire_nllli_dataout : STD_LOGIC; + SIGNAL wire_nlllii_dataout : STD_LOGIC; + SIGNAL wire_nllliil_dataout : STD_LOGIC; + SIGNAL wire_nllliil_w_lg_dataout283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllliiO_dataout : STD_LOGIC; + SIGNAL wire_nlllil_dataout : STD_LOGIC; + SIGNAL wire_nlllili_dataout : STD_LOGIC; + SIGNAL wire_nlllill_dataout : STD_LOGIC; + SIGNAL wire_nlllilO_dataout : STD_LOGIC; + SIGNAL wire_nllliO_dataout : STD_LOGIC; + SIGNAL wire_nllliOi_dataout : STD_LOGIC; + SIGNAL wire_nllliOl_dataout : STD_LOGIC; + SIGNAL wire_nllll_dataout : STD_LOGIC; + SIGNAL wire_nlllli_dataout : STD_LOGIC; + SIGNAL wire_nlllO_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllO00i_dataout : STD_LOGIC; + SIGNAL wire_nllO00i_w_lg_w_lg_w_lg_dataout4064w4065w4066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO00i_w_lg_w_lg_dataout4064w4065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO00i_w_lg_dataout4064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO00l_dataout : STD_LOGIC; + SIGNAL wire_nllO00O_dataout : STD_LOGIC; + SIGNAL wire_nllO00O_w_lg_w_lg_w_lg_dataout3960w3961w3962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO00O_w_lg_w_lg_dataout3960w3961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO00O_w_lg_dataout3960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO01i_dataout : STD_LOGIC; + SIGNAL wire_nllO01l_dataout : STD_LOGIC; + SIGNAL wire_nllO01O_dataout : STD_LOGIC; + SIGNAL wire_nllO0ii_dataout : STD_LOGIC; + SIGNAL wire_nllO0ii_w_lg_w_lg_w_lg_dataout3945w3946w3947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO0ii_w_lg_w_lg_dataout3945w3946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO0ii_w_lg_dataout3945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO0ii_w_lg_dataout4069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO0il_dataout : STD_LOGIC; + SIGNAL wire_nllO0il_w_lg_w_lg_dataout3407w4078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllO0il_w_lg_dataout3407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOi0l_dataout : STD_LOGIC; + SIGNAL wire_nllOi0O_dataout : STD_LOGIC; + SIGNAL wire_nllOi1l_dataout : STD_LOGIC; + SIGNAL wire_nllOi1O_dataout : STD_LOGIC; + SIGNAL wire_nllOiii_dataout : STD_LOGIC; + SIGNAL wire_nllOiil_dataout : STD_LOGIC; + SIGNAL wire_nllOiiO_dataout : STD_LOGIC; + SIGNAL wire_nllOili_dataout : STD_LOGIC; + SIGNAL wire_nllOill_dataout : STD_LOGIC; + SIGNAL wire_nllOilO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO_dataout : STD_LOGIC; + SIGNAL wire_nllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOl0i_dataout : STD_LOGIC; + SIGNAL wire_nllOl0l_dataout : STD_LOGIC; + SIGNAL wire_nllOl0O_dataout : STD_LOGIC; + SIGNAL wire_nllOl1i_dataout : STD_LOGIC; + SIGNAL wire_nllOl1l_dataout : STD_LOGIC; + SIGNAL wire_nllOl1O_dataout : STD_LOGIC; + SIGNAL wire_nllOlii_dataout : STD_LOGIC; + SIGNAL wire_nllOlil_dataout : STD_LOGIC; + SIGNAL wire_nllOliO_dataout : STD_LOGIC; + SIGNAL wire_nllOO_dataout : STD_LOGIC; + SIGNAL wire_nllOO0O_dataout : STD_LOGIC; + SIGNAL wire_nllOOii_dataout : STD_LOGIC; + SIGNAL wire_nllOOil_dataout : STD_LOGIC; + SIGNAL wire_nllOOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOOli_dataout : STD_LOGIC; + SIGNAL wire_nllOOll_dataout : STD_LOGIC; + SIGNAL wire_nllOOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO100i_dataout : STD_LOGIC; + SIGNAL wire_nlO100l_dataout : STD_LOGIC; + SIGNAL wire_nlO101i_dataout : STD_LOGIC; + SIGNAL wire_nlO101l_dataout : STD_LOGIC; + SIGNAL wire_nlO101O_dataout : STD_LOGIC; + SIGNAL wire_nlO110O_dataout : STD_LOGIC; + SIGNAL wire_nlO11ii_dataout : STD_LOGIC; + SIGNAL wire_nlO11il_dataout : STD_LOGIC; + SIGNAL wire_nlO11iO_dataout : STD_LOGIC; + SIGNAL wire_nlO11li_dataout : STD_LOGIC; + SIGNAL wire_nlO11ll_dataout : STD_LOGIC; + SIGNAL wire_nlO11lO_dataout : STD_LOGIC; + SIGNAL wire_nlO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO11OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1ili_dataout : STD_LOGIC; + SIGNAL wire_nlO1ill_dataout : STD_LOGIC; + SIGNAL wire_nlO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1lii_dataout : STD_LOGIC; + SIGNAL wire_nlO1lil_dataout : STD_LOGIC; + SIGNAL wire_nlO1liO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOll0O_w_lg_w_lg_dataout1212w3256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOll0O_w_lg_dataout1212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO_dataout : STD_LOGIC; + SIGNAL wire_n011ili_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n011ili_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n011ili_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1li0i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1li0i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1li0i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1li1O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1li1O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1li1O_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O0lO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1O0lO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1O0lO_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1Ol0Ol_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Ol0Ol_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Ol0Ol_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Ol0OO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1Ol0OO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1Ol0OO_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl0iiOl_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0iiOl_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0iiOl_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1iil_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1iil_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1iil_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllO1lO_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nllO1lO_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nllO1lO_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nllO1Oi_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1Oi_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1Oi_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1Ol_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1Ol_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1Ol_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1OO_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1OO_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllO1OO_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlO0l0i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0l0i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0l0i_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oill_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oill_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oill_o : STD_LOGIC; + SIGNAL wire_n1OOi1l_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_n1OOi1l_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_n1OOi1l_o : STD_LOGIC; + SIGNAL wire_nl0iiOO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0iiOO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_nl0iiOO_o : STD_LOGIC; + SIGNAL wire_nl0illl_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0illl_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0illl_o : STD_LOGIC; + SIGNAL wire_nl0iOii_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0iOii_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0iOii_o : STD_LOGIC; + SIGNAL wire_nl0l11O_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0l11O_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0l11O_o : STD_LOGIC; + SIGNAL wire_nllOO1l_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllOO1l_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nllOO1l_o : STD_LOGIC; + SIGNAL wire_nlO10Ol_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlO10Ol_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlO10Ol_o : STD_LOGIC; + SIGNAL wire_niOO0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOO0l_o : STD_LOGIC; + SIGNAL wire_niOO0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOO0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOO0O_o : STD_LOGIC; + SIGNAL wire_niOO0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOii_o : STD_LOGIC; + SIGNAL wire_niOOii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOil_o : STD_LOGIC; + SIGNAL wire_niOOil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOiO_o : STD_LOGIC; + SIGNAL wire_niOOiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOli_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOli_o : STD_LOGIC; + SIGNAL wire_niOOli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOll_o : STD_LOGIC; + SIGNAL wire_niOOll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOlO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOlO_o : STD_LOGIC; + SIGNAL wire_niOOlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOOi_o : STD_LOGIC; + SIGNAL wire_niOOOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niOOOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_niOOOl_o : STD_LOGIC; + SIGNAL wire_niOOOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl00l0i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00l0i_o : STD_LOGIC; + SIGNAL wire_nl00l0i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00l0l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00l0l_o : STD_LOGIC; + SIGNAL wire_nl00l0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00l0O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00l0O_o : STD_LOGIC; + SIGNAL wire_nl00l0O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00lii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00lii_o : STD_LOGIC; + SIGNAL wire_nl00lii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00lil_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00lil_o : STD_LOGIC; + SIGNAL wire_nl00lil_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00liO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00liO_o : STD_LOGIC; + SIGNAL wire_nl00liO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00lli_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00lli_o : STD_LOGIC; + SIGNAL wire_nl00lli_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00lll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00lll_o : STD_LOGIC; + SIGNAL wire_nl00lll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00llO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00llO_o : STD_LOGIC; + SIGNAL wire_nl00llO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00lOi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00lOi_o : STD_LOGIC; + SIGNAL wire_nl00lOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00lOl_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00lOl_o : STD_LOGIC; + SIGNAL wire_nl00lOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00lOO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00lOO_o : STD_LOGIC; + SIGNAL wire_nl00lOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00O0i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00O0i_o : STD_LOGIC; + SIGNAL wire_nl00O0i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00O0l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00O0l_o : STD_LOGIC; + SIGNAL wire_nl00O0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00O0O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00O0O_o : STD_LOGIC; + SIGNAL wire_nl00O0O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00O1i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00O1i_o : STD_LOGIC; + SIGNAL wire_nl00O1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00O1l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00O1l_o : STD_LOGIC; + SIGNAL wire_nl00O1l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00O1O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00O1O_o : STD_LOGIC; + SIGNAL wire_nl00O1O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00Oil_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00Oil_o : STD_LOGIC; + SIGNAL wire_nl00Oil_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00OiO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00OiO_o : STD_LOGIC; + SIGNAL wire_nl00OiO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00Oli_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00Oli_o : STD_LOGIC; + SIGNAL wire_nl00Oli_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00Oll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00Oll_o : STD_LOGIC; + SIGNAL wire_nl00Oll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00OlO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00OlO_o : STD_LOGIC; + SIGNAL wire_nl00OlO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00OOi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00OOi_o : STD_LOGIC; + SIGNAL wire_nl00OOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00OOl_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00OOl_o : STD_LOGIC; + SIGNAL wire_nl00OOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl00OOO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl00OOO_o : STD_LOGIC; + SIGNAL wire_nl00OOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i0Ol_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0i0Ol_o : STD_LOGIC; + SIGNAL wire_nl0i0Ol_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0i0OO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0i0OO_o : STD_LOGIC; + SIGNAL wire_nl0i0OO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0i10i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i10i_o : STD_LOGIC; + SIGNAL wire_nl0i10i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i10l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i10l_o : STD_LOGIC; + SIGNAL wire_nl0i10l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i10O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i10O_o : STD_LOGIC; + SIGNAL wire_nl0i10O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i11i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i11i_o : STD_LOGIC; + SIGNAL wire_nl0i11i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i11l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i11l_o : STD_LOGIC; + SIGNAL wire_nl0i11l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i11O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i11O_o : STD_LOGIC; + SIGNAL wire_nl0i11O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i1ii_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i1ii_o : STD_LOGIC; + SIGNAL wire_nl0i1ii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i1il_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i1il_o : STD_LOGIC; + SIGNAL wire_nl0i1il_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i1iO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i1iO_o : STD_LOGIC; + SIGNAL wire_nl0i1iO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i1li_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i1li_o : STD_LOGIC; + SIGNAL wire_nl0i1li_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i1ll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i1ll_o : STD_LOGIC; + SIGNAL wire_nl0i1ll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0i1lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl0i1lO_o : STD_LOGIC; + SIGNAL wire_nl0i1lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0ii1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0ii1i_o : STD_LOGIC; + SIGNAL wire_nl0ii1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0ii1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0ii1l_o : STD_LOGIC; + SIGNAL wire_nl0ii1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0ii1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0ii1O_o : STD_LOGIC; + SIGNAL wire_nl0ii1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0l0OO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0l0OO_o : STD_LOGIC; + SIGNAL wire_nl0l0OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0li1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0li1i_o : STD_LOGIC; + SIGNAL wire_nl0li1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OiOl_w_lg_o13575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OiOl_w_lg_o5684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OiOl_w_lg_o5615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OiOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OiOl_o : STD_LOGIC; + SIGNAL wire_nl0OiOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OiOO_w_lg_o5429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OiOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OiOO_o : STD_LOGIC; + SIGNAL wire_nl0OiOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Ol0i_w_lg_o5439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol0i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol0i_o : STD_LOGIC; + SIGNAL wire_nl0Ol0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Ol0l_w_lg_o5445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol0l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol0l_o : STD_LOGIC; + SIGNAL wire_nl0Ol0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Ol0O_w_lg_o5452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol0O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol0O_o : STD_LOGIC; + SIGNAL wire_nl0Ol0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Ol1i_w_lg_o5431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol1i_o : STD_LOGIC; + SIGNAL wire_nl0Ol1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Ol1l_w_lg_o5618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol1l_o : STD_LOGIC; + SIGNAL wire_nl0Ol1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Ol1O_w_lg_o5434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol1O_o : STD_LOGIC; + SIGNAL wire_nl0Ol1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Olii_w_lg_o5460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Olii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Olii_o : STD_LOGIC; + SIGNAL wire_nl0Olii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Olil_w_lg_o5469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Olil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Olil_o : STD_LOGIC; + SIGNAL wire_nl0Olil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OliO_w_lg_o5479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OliO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OliO_o : STD_LOGIC; + SIGNAL wire_nl0OliO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Olli_w_lg_o5490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Olli_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Olli_o : STD_LOGIC; + SIGNAL wire_nl0Olli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0Olll_w_lg_o5502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Olll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Olll_o : STD_LOGIC; + SIGNAL wire_nl0Olll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OllO_w_lg_o5515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OllO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OllO_o : STD_LOGIC; + SIGNAL wire_nl0OllO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OlOi_w_lg_o5529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OlOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OlOi_o : STD_LOGIC; + SIGNAL wire_nl0OlOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OlOl_w_lg_o5544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OlOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OlOl_o : STD_LOGIC; + SIGNAL wire_nl0OlOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OlOO_w_lg_o5560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OlOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OlOO_o : STD_LOGIC; + SIGNAL wire_nl0OlOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OO1i_w_lg_o5577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OO1i_o : STD_LOGIC; + SIGNAL wire_nl0OO1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OO1l_w_lg_o5595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO1l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OO1l_o : STD_LOGIC; + SIGNAL wire_nl0OO1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0OO1O_w_lg_o13557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO1O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0OO1O_o : STD_LOGIC; + SIGNAL wire_nl0OO1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl100i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl100i_o : STD_LOGIC; + SIGNAL wire_nl100i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl101i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl101i_o : STD_LOGIC; + SIGNAL wire_nl101i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl101l_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl101l_o : STD_LOGIC; + SIGNAL wire_nl101l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl101O_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl101O_o : STD_LOGIC; + SIGNAL wire_nl101O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl11li_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl11li_o : STD_LOGIC; + SIGNAL wire_nl11li_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl11ll_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl11ll_o : STD_LOGIC; + SIGNAL wire_nl11ll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl11lO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl11lO_o : STD_LOGIC; + SIGNAL wire_nl11lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl11Oi_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl11Oi_o : STD_LOGIC; + SIGNAL wire_nl11Oi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl11Ol_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl11Ol_o : STD_LOGIC; + SIGNAL wire_nl11Ol_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl11OO_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nl11OO_o : STD_LOGIC; + SIGNAL wire_nl11OO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1liiO_w_lg_o16992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1liiO_o : STD_LOGIC; + SIGNAL wire_nl1liiO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lili_w_lg_w_lg_o16990w17009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lili_w_lg_w_lg_o16990w16991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lili_w_lg_o16993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lili_w_lg_o16990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lili_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lili_o : STD_LOGIC; + SIGNAL wire_nl1lili_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_w_lg_o16982w17003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_o17010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_o17029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_o17032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_w_lg_o16982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lill_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lill_o : STD_LOGIC; + SIGNAL wire_nl1lill_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_w_lg_o16913w17152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_w_lg_o16913w17112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o17033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o16979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_w_lg_o16913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lilO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lilO_o : STD_LOGIC; + SIGNAL wire_nl1lilO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_w_lg_o16843w16914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_w_lg_o16843w16844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_w_lg_o16843w16907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_w_lg_o16843w16955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_o16980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_o16847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_o16925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_o16931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_w_lg_o16843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1liOi_o : STD_LOGIC; + SIGNAL wire_nl1liOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_o16842w16915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_o16842w16908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_o16842w16987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_w_lg_o16842w16910w16911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w16916w16922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w16941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_o16928w16929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_w_lg_o16842w16908w16909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_o16926w16927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_o16842w16910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_w_lg_w_lg_o16842w16908w16909w16912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_w_lg_o16926w16927w16930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w16916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_w_lg_w_lg_w_lg_o16926w16927w16930w16933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_w_lg_o16928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1liOl_o : STD_LOGIC; + SIGNAL wire_nl1liOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1liOO_w_lg_w_lg_o16856w17040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOO_w_lg_w_lg_o16856w16963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOO_w_lg_o16868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOO_w_lg_o17121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOO_w_lg_o16856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1liOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1liOO_o : STD_LOGIC; + SIGNAL wire_nl1liOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1ll0i_w_lg_o16648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1ll0i_o : STD_LOGIC; + SIGNAL wire_nl1ll0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1ll0l_w_lg_w_lg_o16646w16665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0l_w_lg_w_lg_o16646w16647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0l_w_lg_o16649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0l_w_lg_o16646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1ll0l_o : STD_LOGIC; + SIGNAL wire_nl1ll0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_w_lg_o16638w16659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_o16666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_o16685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_o16688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_w_lg_o16638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1ll0O_o : STD_LOGIC; + SIGNAL wire_nl1ll0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_w_lg_o16855w17043w17044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o17045w17046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w17053w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w16857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w16895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w16872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w17043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w16880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w17061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o17050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o16869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o17122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o16883w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o17062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o16876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o16901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o17045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o16850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o16855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_w_lg_w_lg_o16855w17043w17044w17047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_w_lg_o16855w16919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_w_lg_o16938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1ll1i_o : STD_LOGIC; + SIGNAL wire_nl1ll1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o16854w17054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o16854w16891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o16854w17093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o16854w17088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o16854w17074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o16854w17071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o17077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o17096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o17051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o16870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o16884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o17099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o16877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o16902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o16851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o16890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_o16854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o17051w17055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_w_lg_w_lg_o16890w16892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1ll1l_o : STD_LOGIC; + SIGNAL wire_nl1ll1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_w_lg_o16937w16939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_w_lg_o16853w16969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o17094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o17089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o17075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o17072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o17078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o17097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o16885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o17100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o16878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o16903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o16852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o16937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o16853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_w_lg_o16934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ll1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1ll1O_o : STD_LOGIC; + SIGNAL wire_nl1ll1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_w_lg_o16569w16808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_w_lg_o16569w16768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_w_lg_o16569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llii_o : STD_LOGIC; + SIGNAL wire_nl1llii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_w_lg_o16499w16570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_w_lg_o16499w16611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_w_lg_o16499w16563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_w_lg_o16499w16500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_o16636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_o16581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_o16503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_o16587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_w_lg_o16499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llil_o : STD_LOGIC; + SIGNAL wire_nl1llil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_o16498w16571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_o16498w16564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_o16498w16643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_w_lg_o16498w16566w16567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w16572w16578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w16597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_o16584w16585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_w_lg_o16498w16564w16565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_o16582w16583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_o16498w16566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_w_lg_w_lg_o16498w16564w16565w16568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_w_lg_o16582w16583w16586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w16572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_w_lg_w_lg_w_lg_o16582w16583w16586w16589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_w_lg_o16584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lliO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lliO_o : STD_LOGIC; + SIGNAL wire_nl1lliO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llli_w_lg_w_lg_o16512w16696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llli_w_lg_w_lg_o16512w16619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llli_w_lg_o16524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llli_w_lg_o16777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llli_w_lg_o16512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llli_o : STD_LOGIC; + SIGNAL wire_nl1llli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_w_lg_o16511w16699w16700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16701w16702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16718w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16532w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_w_lg_w_lg_o16511w16699w16700w16703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_w_lg_o16511w16575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_w_lg_o16594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llll_o : STD_LOGIC; + SIGNAL wire_nl1llll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16510w16710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16510w16749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16510w16744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16510w16730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16510w16727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16510w16547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_o16510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16707w16711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_w_lg_w_lg_o16546w16548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lllO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lllO_o : STD_LOGIC; + SIGNAL wire_nl1lllO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_w_lg_o16593w16595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_w_lg_o16509w16625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_w_lg_o16590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llOi_o : STD_LOGIC; + SIGNAL wire_nl1llOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llOl_o : STD_LOGIC; + SIGNAL wire_nl1llOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llOO_o : STD_LOGIC; + SIGNAL wire_nl1llOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lO0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lO0i_o : STD_LOGIC; + SIGNAL wire_nl1lO0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lO0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lO0l_o : STD_LOGIC; + SIGNAL wire_nl1lO0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lO0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lO0O_o : STD_LOGIC; + SIGNAL wire_nl1lO0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lO1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lO1i_o : STD_LOGIC; + SIGNAL wire_nl1lO1i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lO1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lO1l_o : STD_LOGIC; + SIGNAL wire_nl1lO1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lO1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lO1O_o : STD_LOGIC; + SIGNAL wire_nl1lO1O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOii_o : STD_LOGIC; + SIGNAL wire_nl1lOii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOil_o : STD_LOGIC; + SIGNAL wire_nl1lOil_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOiO_o : STD_LOGIC; + SIGNAL wire_nl1lOiO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOli_o : STD_LOGIC; + SIGNAL wire_nl1lOli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOll_o : STD_LOGIC; + SIGNAL wire_nl1lOll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOlO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOlO_o : STD_LOGIC; + SIGNAL wire_nl1lOlO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOOi_o : STD_LOGIC; + SIGNAL wire_nl1lOOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOOl_o : STD_LOGIC; + SIGNAL wire_nl1lOOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lOOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lOOO_o : STD_LOGIC; + SIGNAL wire_nl1lOOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O00i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O00i_o : STD_LOGIC; + SIGNAL wire_nl1O00i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O01i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O01i_o : STD_LOGIC; + SIGNAL wire_nl1O01i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O01l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O01l_o : STD_LOGIC; + SIGNAL wire_nl1O01l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O01O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O01O_o : STD_LOGIC; + SIGNAL wire_nl1O01O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O10i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O10i_o : STD_LOGIC; + SIGNAL wire_nl1O10i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O10l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O10l_o : STD_LOGIC; + SIGNAL wire_nl1O10l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O10O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O10O_o : STD_LOGIC; + SIGNAL wire_nl1O10O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O11i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O11i_o : STD_LOGIC; + SIGNAL wire_nl1O11i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O11l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O11l_o : STD_LOGIC; + SIGNAL wire_nl1O11l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O11O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O11O_o : STD_LOGIC; + SIGNAL wire_nl1O11O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1ii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1ii_o : STD_LOGIC; + SIGNAL wire_nl1O1ii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1il_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1il_o : STD_LOGIC; + SIGNAL wire_nl1O1il_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1iO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1iO_o : STD_LOGIC; + SIGNAL wire_nl1O1iO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1li_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1li_o : STD_LOGIC; + SIGNAL wire_nl1O1li_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1ll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1ll_o : STD_LOGIC; + SIGNAL wire_nl1O1ll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1lO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1lO_o : STD_LOGIC; + SIGNAL wire_nl1O1lO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1Oi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1Oi_o : STD_LOGIC; + SIGNAL wire_nl1O1Oi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1Ol_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1Ol_o : STD_LOGIC; + SIGNAL wire_nl1O1Ol_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1OO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1O1OO_o : STD_LOGIC; + SIGNAL wire_nl1O1OO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllO0iO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllO0iO_o : STD_LOGIC; + SIGNAL wire_nllO0iO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllO0li_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllO0li_o : STD_LOGIC; + SIGNAL wire_nllO0li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllO0ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllO0ll_o : STD_LOGIC; + SIGNAL wire_nllO0ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllO0lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllO0lO_o : STD_LOGIC; + SIGNAL wire_nllO0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllO0Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllO0Oi_o : STD_LOGIC; + SIGNAL wire_nllO0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllO0Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllO0Ol_o : STD_LOGIC; + SIGNAL wire_nllO0Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllO0OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllO0OO_o : STD_LOGIC; + SIGNAL wire_nllO0OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOi1i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nllOi1i_o : STD_LOGIC; + SIGNAL wire_nllOi1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0O0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0O0i_o : STD_LOGIC; + SIGNAL wire_nlO0O0i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO0OiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0OiO_o : STD_LOGIC; + SIGNAL wire_nlO0OiO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlO0OOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO0OOl_o : STD_LOGIC; + SIGNAL wire_nlO0OOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlOi00i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOi00i_o : STD_LOGIC; + SIGNAL wire_nlOi00i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlOi0iO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOi0iO_o : STD_LOGIC; + SIGNAL wire_nlOi0iO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlOi10i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOi10i_o : STD_LOGIC; + SIGNAL wire_nlOi10i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlOi1iO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOi1iO_o : STD_LOGIC; + SIGNAL wire_nlOi1iO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlOi1Ol_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOi1Ol_o : STD_LOGIC; + SIGNAL wire_nlOi1Ol_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1lili_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lili_o : STD_LOGIC; + SIGNAL wire_n1lili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lill_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lill_o : STD_LOGIC; + SIGNAL wire_n1lill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lilO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lilO_o : STD_LOGIC; + SIGNAL wire_n1lilO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1liOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1liOi_o : STD_LOGIC; + SIGNAL wire_n1liOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1liOO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1liOO_o : STD_LOGIC; + SIGNAL wire_n1liOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1ll0O_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1ll0O_o : STD_LOGIC; + SIGNAL wire_n1ll0O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1ll1i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1ll1i_o : STD_LOGIC; + SIGNAL wire_n1ll1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1ll1l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1ll1l_o : STD_LOGIC; + SIGNAL wire_n1ll1l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1ll1O_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1ll1O_o : STD_LOGIC; + SIGNAL wire_n1ll1O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1llil_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1llil_o : STD_LOGIC; + SIGNAL wire_n1llil_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1llli_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1llli_o : STD_LOGIC; + SIGNAL wire_n1llli_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1lllO_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1lllO_o : STD_LOGIC; + SIGNAL wire_n1lllO_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Oliii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oliii_o : STD_LOGIC; + SIGNAL wire_n1Oliii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oliil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Oliil_o : STD_LOGIC; + SIGNAL wire_n1Oliil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OliiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OliiO_o : STD_LOGIC; + SIGNAL wire_n1OliiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Olili_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Olili_o : STD_LOGIC; + SIGNAL wire_n1Olili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Olill_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Olill_o : STD_LOGIC; + SIGNAL wire_n1Olill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OliOi_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OliOi_o : STD_LOGIC; + SIGNAL wire_n1OliOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OliOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OliOl_o : STD_LOGIC; + SIGNAL wire_n1OliOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OliOO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1OliOO_o : STD_LOGIC; + SIGNAL wire_n1OliOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oll0l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1Oll0l_o : STD_LOGIC; + SIGNAL wire_n1Oll0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1Oll1i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oll1i_o : STD_LOGIC; + SIGNAL wire_n1Oll1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oll1l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oll1l_o : STD_LOGIC; + SIGNAL wire_n1Oll1l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Ollii_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Ollii_o : STD_LOGIC; + SIGNAL wire_n1Ollii_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1OlliO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1OlliO_o : STD_LOGIC; + SIGNAL wire_n1OlliO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1Ollll_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Ollll_o : STD_LOGIC; + SIGNAL wire_n1Ollll_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niO00i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO00i_o : STD_LOGIC; + SIGNAL wire_niO00i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO00l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO00l_o : STD_LOGIC; + SIGNAL wire_niO00l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO00O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO00O_o : STD_LOGIC; + SIGNAL wire_niO00O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO01i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO01i_o : STD_LOGIC; + SIGNAL wire_niO01i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO01l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO01l_o : STD_LOGIC; + SIGNAL wire_niO01l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO01O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO01O_o : STD_LOGIC; + SIGNAL wire_niO01O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO1Ol_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO1Ol_o : STD_LOGIC; + SIGNAL wire_niO1Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO1OO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO1OO_o : STD_LOGIC; + SIGNAL wire_niO1OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOill_w_lg_o3118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOill_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOill_o : STD_LOGIC; + SIGNAL wire_niOill_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOilO_w_lg_w_lg_o3116w3135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOilO_w_lg_w_lg_o3116w3117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOilO_w_lg_o3119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOilO_w_lg_o3116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOilO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOilO_o : STD_LOGIC; + SIGNAL wire_niOilO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_w_lg_o3108w3129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_o3136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_o3155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_o3158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_w_lg_o3108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOiOi_o : STD_LOGIC; + SIGNAL wire_niOiOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_w_lg_o1205w3260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_w_lg_o1205w1206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o3105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_w_lg_o1205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOiOl_o : STD_LOGIC; + SIGNAL wire_niOiOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_w_lg_o2973w3041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_w_lg_o2973w3035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_w_lg_o2973w2974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_o3106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_o3052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_o2977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_o3058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_w_lg_o2973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOiOO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOiOO_o : STD_LOGIC; + SIGNAL wire_niOiOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_o2972w3042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_o2972w3036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_o2972w3113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_w_lg_o2972w3038w3039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w3043w3049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w3068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_o3055w3056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o3107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o3053w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o2978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o3059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o3114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o2994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o2972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_w_lg_o2972w3036w3037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_o3053w3054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_o2972w3038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_w_lg_w_lg_o2972w3036w3037w3040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_w_lg_o3053w3054w3057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w3043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_w_lg_w_lg_w_lg_o3053w3054w3057w3060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_w_lg_o3055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOl1i_o : STD_LOGIC; + SIGNAL wire_niOl1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOl1l_w_lg_w_lg_o2983w3085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1l_w_lg_w_lg_o2983w3166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1l_w_lg_o2995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1l_w_lg_o1215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1l_w_lg_o2983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOl1l_o : STD_LOGIC; + SIGNAL wire_niOl1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_w_lg_o1314w3170w3171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o3172w3173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w3181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w2984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w3022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w2999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w1315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w3170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w3007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w3189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o3178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o2996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o1216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o3010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o3190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o3003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o3028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o1319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o3172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o2980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o1314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_w_lg_w_lg_o1314w3170w3171w3174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_w_lg_o1314w3046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_w_lg_o3065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOl1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOl1O_o : STD_LOGIC; + SIGNAL wire_niOl1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1llO_w_lg_o7418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1llO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1llO_o : STD_LOGIC; + SIGNAL wire_nll1llO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1lOO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1lOO_o : STD_LOGIC; + SIGNAL wire_nll1lOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1O1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1O1i_o : STD_LOGIC; + SIGNAL wire_nll1O1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll0i_o : STD_LOGIC; + SIGNAL wire_nlll0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1i_o : STD_LOGIC; + SIGNAL wire_nlll1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1l_o : STD_LOGIC; + SIGNAL wire_nlll1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1O_o : STD_LOGIC; + SIGNAL wire_nlll1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllll0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll0i_o : STD_LOGIC; + SIGNAL wire_nllll0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll0l_o : STD_LOGIC; + SIGNAL wire_nllll0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll0O_o : STD_LOGIC; + SIGNAL wire_nllll0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll1l_o : STD_LOGIC; + SIGNAL wire_nllll1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllll1O_o : STD_LOGIC; + SIGNAL wire_nllll1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllii_o : STD_LOGIC; + SIGNAL wire_nllllii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllil_o : STD_LOGIC; + SIGNAL wire_nllllil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllliO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllliO_o : STD_LOGIC; + SIGNAL wire_nlllliO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllli_o : STD_LOGIC; + SIGNAL wire_nllllli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllll_o : STD_LOGIC; + SIGNAL wire_nllllll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllOl_o : STD_LOGIC; + SIGNAL wire_nllllOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllllOO_o : STD_LOGIC; + SIGNAL wire_nllllOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO0i_o : STD_LOGIC; + SIGNAL wire_nlllO0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO0l_o : STD_LOGIC; + SIGNAL wire_nlllO0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO0O_o : STD_LOGIC; + SIGNAL wire_nlllO0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1i_o : STD_LOGIC; + SIGNAL wire_nlllO1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1l_o : STD_LOGIC; + SIGNAL wire_nlllO1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1O_o : STD_LOGIC; + SIGNAL wire_nlllO1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllOii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllOii_o : STD_LOGIC; + SIGNAL wire_nlllOii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllOil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllOil_o : STD_LOGIC; + SIGNAL wire_nlllOil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllOli_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlllOli_o : STD_LOGIC; + SIGNAL wire_nlllOli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlllOOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlllOOi_o : STD_LOGIC; + SIGNAL wire_nlllOOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlllOOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlllOOl_o : STD_LOGIC; + SIGNAL wire_nlllOOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlllOOO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlllOOO_o : STD_LOGIC; + SIGNAL wire_nlllOOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO10i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO10i_o : STD_LOGIC; + SIGNAL wire_nllO10i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO10l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO10l_o : STD_LOGIC; + SIGNAL wire_nllO10l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO10O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO10O_o : STD_LOGIC; + SIGNAL wire_nllO10O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO11i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO11i_o : STD_LOGIC; + SIGNAL wire_nllO11i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO11l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO11l_o : STD_LOGIC; + SIGNAL wire_nllO11l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO11O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO11O_o : STD_LOGIC; + SIGNAL wire_nllO11O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO1ii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO1ii_o : STD_LOGIC; + SIGNAL wire_nllO1ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO1iO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllO1iO_o : STD_LOGIC; + SIGNAL wire_nllO1iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rauto_speed_ena5w8w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i0O0O338w341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1ii01O227w228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1ii11O1325w1327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rauto_speed_ena5w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n10liOl3443w3446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n10ll1O3434w3435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rkchar3383w3384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w14445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i01lO1217w1218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i1Oil1323w1324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO0iOl16779w16780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO1O0l17123w17124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5053w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn5005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_comp_pat_porn4806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l1ii4519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O10i3044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O10l3062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O10O3020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O11l3047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i000O1200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i00il3236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i00il1198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0l0l388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0l1O396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0lii380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0liO372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0lll364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0lOO356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0O0O338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1Oll3180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1OlO3177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1ii01O227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1ii11i326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1ii11O1325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO011i17049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01ll16920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01Oi16917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01Ol16935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01OO16893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0i0O16788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0i0O16761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0lil16763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0liO16708w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0lli16705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0O0l16576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0Oii16573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0Oil16591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0OiO16549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1llO17132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1llO17105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1OOl17107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1OOO17052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rauto_speed_ena5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rencdt_rising4509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_wa_6g_en4496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_comp_pat_size_range1330w1333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ib_invalid_code_range3169w17048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ib_invalid_code_range3169w16704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ib_invalid_code_range3169w3175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ib_invalid_code_range3176w3184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ib_invalid_code_range3176w17056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ib_invalid_code_range3176w16712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w1328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w16385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w15676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w14444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w15643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range3034w3050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_r8b10b_dec_ibm_en_range3034w3069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_resync_badcg_en_range4511w4518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_autobytealign_dis5791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_disable_rx_disp1194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_lpbk_en4500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l00i3543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l01l3948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l01O3545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l0OO3456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l10i4528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l11i4530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l1il4527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l1li4548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10li0i3455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10li0O3453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10lili3500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10lilO3445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10liOl3443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10ll0i3493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10ll0l3386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10ll0O3433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10ll1l3437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10ll1O3434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10llii3439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10lOlO3084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O00l2717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O01l2767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O01O2739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O0il2712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O0li2685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O0Oi2526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O0Ol2525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O0OO2524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O10O3014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O1iO3025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O1li3031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O1Oi3072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oi0i2520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oi0l2490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oi0O2489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oi1i2523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oi1l2522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oi1O2521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oiii2488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oiil2487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OiiO2486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oili2485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Oill2484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OiOO2455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Ol0i2451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Ol0l2449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Ol0O2457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Ol1i2453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Ol1l2515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Ol1O2459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Olli2400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10Olll2398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OllO2505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OlOi2404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OlOl2396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OlOO2394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OO0l2345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OO0O2343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OO1i2402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OOii2480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OOil2349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OOiO2341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OOli2339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OOll2347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10OOOO2291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110iiO5931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110ili5930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110iOl5657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110l0i5646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110l0l5644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110l0O5642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110l1i5652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110l1l5650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110l1O5648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110lii5640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110lil5638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110liO5636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110lli5634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110lll5632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110llO5630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110lOi5628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110lOl5626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110lOO5624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110O1i5616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n110O1l5614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11100i14248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11100l14246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11100O14683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11101i14674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11101l14252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11101O14678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110ii14241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110il14239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110iO14689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110li14234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110ll14232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110lO14696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110Oi14227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110Ol14225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1110OO14704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11110i15016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11110l15031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11110O15047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11111i14977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11111l14989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n11111O15002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111ii15064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111il15082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111li16406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111ll14261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111lO14669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111Oi14258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111Ol14671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111OO14255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111i0i14213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111i0l14211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111i0O14723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111i1i14220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111i1l14218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111i1O14713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111iii14206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111iil14204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111iiO14734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111ili14199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111ill14197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111ilO14746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111iOi14192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111iOl14190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111iOO14759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111l0i14178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111l0l14176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111l0O14788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111l1i14185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111l1l14183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111l1O14773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111lii14171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111lil14169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111liO14804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111lli14821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111lll14839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111lOi7419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n111O1i7420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i00lO1129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i01ii1295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i01il1227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0i0i462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0i0O459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0iii457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0iil455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0iiO453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0ili451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0ill449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0ilO447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i0iOi445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i100l2498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i100O2508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i101i2943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i101O2353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i10il2355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i10ll2359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i10Ol2364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i110i2287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i110l2285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i110O2293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i111i2289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i111l2471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i111O2295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11ii2953w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11il2408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11li2410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11ll2414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11lO2419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11Oi2425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11Ol2432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11OO2440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1i0i2385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1i1l2370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1i1O2377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1iii2933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1iil2299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1iiO2171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1ili2305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1ill2310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1ilO2316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1iOi2323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1iOl2331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l0i2137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l0l2464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l0O2133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l1i2923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l1l2140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l1O2244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1lii2131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1lil2246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1liO2126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1lli2124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1lll2250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1llO2119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1lOi2117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1lOl2255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1lOO2112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1O0i2276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1O1i2110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1O1l2261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1O1O2268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1ii00i237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1ii00l231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1ii1lO236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1ii1OO229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO000i16904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO001O16898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO00ii16945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01OO16887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0l0O16618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0OiO16543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0OlO16554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0OOi16560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1OlO16962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi00i15691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi00l15690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi00O15689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi01i15694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi01l15693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi01O15692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0ii15688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0il15687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0iO15686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0li15685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0ll15684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0lO15683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0Oi15682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0Ol15681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi0OO15680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi10l16209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi10O16181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi11i16601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi1il16159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi1ll16154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOii0i15658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOii0l15657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOii0O15656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOii1i15679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOii1l15660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOii1O15659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiiii15655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiiil15654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiiiO15653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiili15652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiill15651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiilO15650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiiOi15649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiiOl15648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiiOO15647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOil1i15646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOil1l15645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiliO15632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOilli15630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOilll15621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOillO15619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOilOi15617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOilOl15615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOilOO15609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiO0i15601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiO0l15599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiO0O15597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiO1i15607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiO1l15605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiO1O15603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiOii15596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiOil15594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiOiO15592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiOli15590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOiOll15588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl00i15346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl00l15344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl01i15352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl01l15350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl01O15348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl0lO15144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl0Oi15142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl0Ol15133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl0OO15131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl10i15386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl10l15377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl10O15375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl11O15388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1ii15373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1il15371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1iO15365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1li15363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1ll15361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1lO15359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1Oi15357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1Ol15355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOl1OO15353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOli0i15119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOli0l15117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOli0O15115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOli1i15129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOli1l15127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOli1O15121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOliii15113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOliil15111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOliiO15109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlili15108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlill15106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlilO15104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOliOi15102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOliOl15100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOll0O14902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOllii14900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOllil14891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlliO14889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOllli14887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOllll14885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlllO14879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOllOi14877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOllOl14875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOllOO14873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlO0i14866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlO0l14864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlO0O14862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlO1i14871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlO1l14869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlO1O14867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOii14860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOil14858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOiO16466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOli15399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOlO15401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOOl15404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO00i15157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO00O15160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO01l15155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO0il15164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO0iO15408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO0ll15169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO0Ol15175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO10i15434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO10l15443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO10O15453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO11i15413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO11l15419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO11O15426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1ii15464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1il15476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1iO15489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1li15503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1ll15518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1lO15534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1Oi15551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1Ol15569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1OO16446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOi0l15190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOi1l15182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOiil15199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOill15209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOiOl15220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOl0l15245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOl1l15232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOlil15259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOlll15274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOlOl15290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOlOO15307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOO0i16426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOO0l14913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOO0O14423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOO1i15325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOii14915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOil14403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOiO14918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOli14384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOll14932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOlO14939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOOi14947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOOl14956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOOOO14966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rencdt_rising4504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rfreq_sel4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rkchar3383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rosbased3492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rst113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sync_sm_dis1224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_wa_6g_en4499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_comp_pat_size_range1331w1332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_resync_badcg_en_range4513w4514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_rauto_speed_ena5w8w9w10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4782w4783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4786w4787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4780w4781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4776w4777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4774w4775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4770w4771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4800w4801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4804w4805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4798w4799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4794w4795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4792w4793w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4788w4789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4764w4765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4768w4769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4762w4763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4758w4759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4756w4757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5097w5098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5095w5096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5091w5092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5089w5090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5757w5758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5743w5744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5738w5739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5061w5062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5067w5068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5065w5066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5059w5060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5055w5056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5053w5054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5079w5080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5085w5086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5083w5084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5077w5078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5073w5074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5071w5072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5043w5044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5049w5050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5047w5048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5041w5042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5037w5038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5035w5036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5025w5026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5031w5032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5029w5030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5023w5024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5019w5020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5017w5018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5007w5008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5013w5014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5011w5012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn5005w5006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4872w4873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4870w4871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4866w4867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4864w4865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4860w4861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4854w4855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4858w4859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4852w4853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4848w4849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4846w4847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4842w4843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4836w4837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4840w4841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4834w4835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4830w4831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4828w4829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4824w4825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4818w4819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4822w4823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4816w4817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4812w4813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4810w4811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_comp_pat_porn4806w4807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w176w177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n10ll0O3433w3447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w15001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w15015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w15030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w14965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w14976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w14988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w15046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w15063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w15081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w14931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w14938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w14946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n11100i14248w14955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i1l0O2133w2304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i1l0O2133w2309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i1l0O2133w2315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i1l0O2133w2322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i1l0O2133w2330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w219w2580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w176w177w181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2572w2573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2564w2565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2556w2557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2580w2581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15832w15833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15820w15821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15916w15917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15904w15905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15892w15893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15880w15881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15868w15869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15856w15857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15844w15845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15832w15833w15834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15820w15821w15822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15916w15917w15918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15904w15905w15906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15892w15893w15894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15880w15881w15882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15868w15869w15870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15856w15857w15858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15844w15845w15846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2574w2575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2566w2567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2558w2559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2582w2583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15832w15833w15834w15835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15820w15821w15822w15823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15916w15917w15918w15919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15904w15905w15906w15907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15892w15893w15894w15895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15880w15881w15882w15883w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15868w15869w15870w15871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15856w15857w15858w15859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15844w15845w15846w15847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w2574w2575w2576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w2566w2567w2568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w2558w2559w2560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w2582w2583w2584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w2574w2575w2576w2577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w2566w2567w2568w2569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w2558w2559w2560w2561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w2582w2583w2584w2585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15836w15837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15824w15825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15920w15921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15908w15909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15896w15897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15884w15885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15872w15873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15860w15861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15848w15849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15836w15837w15838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15824w15825w15826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15920w15921w15922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15908w15909w15910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15896w15897w15898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15884w15885w15886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15872w15873w15874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15860w15861w15862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15848w15849w15850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15836w15837w15838w15839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15824w15825w15826w15827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15920w15921w15922w15923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15908w15909w15910w15911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15896w15897w15898w15899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15884w15885w15886w15887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15872w15873w15874w15875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15860w15861w15862w15863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15848w15849w15850w15851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15840w15841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15828w15829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15924w15925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15912w15913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15900w15901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15888w15889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15876w15877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15864w15865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15852w15853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15840w15841w15842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15828w15829w15830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15924w15925w15926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15912w15913w15914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15900w15901w15902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15888w15889w15890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15876w15877w15878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15864w15865w15866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15852w15853w15854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15814w15815w15816w15817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15804w15805w15806w15807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15794w15795w15796w15797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15784w15785w15786w15787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15774w15775w15776w15777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15764w15765w15766w15767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15753w15754w15755w15756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15814w15815w15816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15804w15805w15806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15794w15795w15796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15784w15785w15786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15774w15775w15776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15764w15765w15766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15753w15754w15755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15814w15815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15804w15805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15794w15795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15784w15785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15774w15775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15764w15765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15753w15754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w1202w1203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w17108w17109w17110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w16764w16765w16766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15810w15811w15812w15813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15800w15801w15802w15803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15790w15791w15792w15793w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15780w15781w15782w15783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15770w15771w15772w15773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15760w15761w15762w15763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w15749w15750w15751w15752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w1202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w17108w17109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w16764w16765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15810w15811w15812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15800w15801w15802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15790w15791w15792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15780w15781w15782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15770w15771w15772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15760w15761w15762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w15749w15750w15751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w2535w2536w2537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w2551w2552w2553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w2544w2545w2546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_n1i00ll1196w1197w1199w1201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w17108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w16764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15810w15811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15800w15801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15790w15791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15780w15781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15770w15771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15760w15761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w15749w15750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2535w2536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2551w2552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2544w2545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_n1i00ll1196w1197w1199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nlOO010l17103w17104w17106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nlOO0lOl16759w16760w16762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w15749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n10O10i3045w3048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n10O10l3063w3067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_n1i00ll1196w1197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO010l17103w17104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO01Oi16918w16921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO01Ol16936w16940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO0lOl16759w16760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO0Oii16574w16577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlOO0Oil16592w16596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w15747w15809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w15747w15799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w15747w15789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w15747w15779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w15747w15769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w15747w15759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w15747w15748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w2533w2534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w2549w2550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_pmadwidth_range175w2542w2543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_lpbk_en4495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l10O4521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l1ii4522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10l1il4510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10lOOO3237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10lOOO3073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O10i3045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O10l3063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O11i3074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O1lO2970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n10O1Oi2971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111li14881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1111li14859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i000i3077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i001l1207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i00li3076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i00ll3075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i00ll1196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i01lO1217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i01Ol1210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i01OO1211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i101i2395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i101i2497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11ii2450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i11ii2507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1iii2340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1iii2473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l1i2286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1l1i2463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1O0O1326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1Oil1323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1Oll3095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n1i1OlO3094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO000O16840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO00ii16841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO010l16948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO010l17103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO010O16949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO011i16972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01ii16950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01iO17133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01iO16946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01li16947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01Oi16918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO01Ol16936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0i1l16769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0ilO16773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0iOl16779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0l0i16772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0liO16629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0lli16628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0lOl16604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0lOl16759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0lOO16605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0O0i16603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0O1i16606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0O1O16789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0O1O16602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0Oii16574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0Oil16592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO0OOO16496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1lil17113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1O0l17123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1O1O17117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1Oli17116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOO1OOO16973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOi11i16497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOiO15611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOlOiO15589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1OO15345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOO1OO15367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOO0i15123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlOOOO0i15101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w15747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pmadwidth_range175w2542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n10000i : STD_LOGIC; + SIGNAL n10000l : STD_LOGIC; + SIGNAL n10000O : STD_LOGIC; + SIGNAL n10001i : STD_LOGIC; + SIGNAL n10001l : STD_LOGIC; + SIGNAL n10001O : STD_LOGIC; + SIGNAL n1000ii : STD_LOGIC; + SIGNAL n1000il : STD_LOGIC; + SIGNAL n1000iO : STD_LOGIC; + SIGNAL n1000li : STD_LOGIC; + SIGNAL n1000ll : STD_LOGIC; + SIGNAL n1000lO : STD_LOGIC; + SIGNAL n1000Oi : STD_LOGIC; + SIGNAL n1000Ol : STD_LOGIC; + SIGNAL n1000OO : STD_LOGIC; + SIGNAL n10010i : STD_LOGIC; + SIGNAL n10010l : STD_LOGIC; + SIGNAL n10010O : STD_LOGIC; + SIGNAL n10011i : STD_LOGIC; + SIGNAL n10011l : STD_LOGIC; + SIGNAL n10011O : STD_LOGIC; + SIGNAL n1001ii : STD_LOGIC; + SIGNAL n1001il : STD_LOGIC; + SIGNAL n1001iO : STD_LOGIC; + SIGNAL n1001li : STD_LOGIC; + SIGNAL n1001ll : STD_LOGIC; + SIGNAL n1001lO : STD_LOGIC; + SIGNAL n1001Oi : STD_LOGIC; + SIGNAL n1001Ol : STD_LOGIC; + SIGNAL n1001OO : STD_LOGIC; + SIGNAL n100i0i : STD_LOGIC; + SIGNAL n100i0l : STD_LOGIC; + SIGNAL n100i0O : STD_LOGIC; + SIGNAL n100i1i : STD_LOGIC; + SIGNAL n100i1l : STD_LOGIC; + SIGNAL n100i1O : STD_LOGIC; + SIGNAL n100iii : STD_LOGIC; + SIGNAL n100iil : STD_LOGIC; + SIGNAL n100iiO : STD_LOGIC; + SIGNAL n100ili : STD_LOGIC; + SIGNAL n100ill : STD_LOGIC; + SIGNAL n100ilO : STD_LOGIC; + SIGNAL n100iOi : STD_LOGIC; + SIGNAL n100iOl : STD_LOGIC; + SIGNAL n100iOO : STD_LOGIC; + SIGNAL n100l0i : STD_LOGIC; + SIGNAL n100l0l : STD_LOGIC; + SIGNAL n100l0O : STD_LOGIC; + SIGNAL n100l1i : STD_LOGIC; + SIGNAL n100l1l : STD_LOGIC; + SIGNAL n100l1O : STD_LOGIC; + SIGNAL n100lii : STD_LOGIC; + SIGNAL n100lil : STD_LOGIC; + SIGNAL n100liO : STD_LOGIC; + SIGNAL n100lli : STD_LOGIC; + SIGNAL n100lll : STD_LOGIC; + SIGNAL n100llO : STD_LOGIC; + SIGNAL n100lOi : STD_LOGIC; + SIGNAL n100lOl : STD_LOGIC; + SIGNAL n100lOO : STD_LOGIC; + SIGNAL n100O0i : STD_LOGIC; + SIGNAL n100O0l : STD_LOGIC; + SIGNAL n100O0O : STD_LOGIC; + SIGNAL n100O1i : STD_LOGIC; + SIGNAL n100O1l : STD_LOGIC; + SIGNAL n100O1O : STD_LOGIC; + SIGNAL n100Oii : STD_LOGIC; + SIGNAL n100Oil : STD_LOGIC; + SIGNAL n100OiO : STD_LOGIC; + SIGNAL n100Oli : STD_LOGIC; + SIGNAL n100Oll : STD_LOGIC; + SIGNAL n100OlO : STD_LOGIC; + SIGNAL n100OOi : STD_LOGIC; + SIGNAL n100OOl : STD_LOGIC; + SIGNAL n100OOO : STD_LOGIC; + SIGNAL n10100i : STD_LOGIC; + SIGNAL n10100l : STD_LOGIC; + SIGNAL n10100O : STD_LOGIC; + SIGNAL n10101i : STD_LOGIC; + SIGNAL n10101l : STD_LOGIC; + SIGNAL n10101O : STD_LOGIC; + SIGNAL n1010ii : STD_LOGIC; + SIGNAL n1010il : STD_LOGIC; + SIGNAL n1010iO : STD_LOGIC; + SIGNAL n1010li : STD_LOGIC; + SIGNAL n1010ll : STD_LOGIC; + SIGNAL n1010lO : STD_LOGIC; + SIGNAL n1010Oi : STD_LOGIC; + SIGNAL n1010Ol : STD_LOGIC; + SIGNAL n1010OO : STD_LOGIC; + SIGNAL n10110i : STD_LOGIC; + SIGNAL n10110l : STD_LOGIC; + SIGNAL n10110O : STD_LOGIC; + SIGNAL n10111i : STD_LOGIC; + SIGNAL n10111l : STD_LOGIC; + SIGNAL n10111O : STD_LOGIC; + SIGNAL n1011ii : STD_LOGIC; + SIGNAL n1011il : STD_LOGIC; + SIGNAL n1011iO : STD_LOGIC; + SIGNAL n1011li : STD_LOGIC; + SIGNAL n1011ll : STD_LOGIC; + SIGNAL n1011lO : STD_LOGIC; + SIGNAL n1011Oi : STD_LOGIC; + SIGNAL n1011Ol : STD_LOGIC; + SIGNAL n1011OO : STD_LOGIC; + SIGNAL n101i0i : STD_LOGIC; + SIGNAL n101i0l : STD_LOGIC; + SIGNAL n101i0O : STD_LOGIC; + SIGNAL n101i1i : STD_LOGIC; + SIGNAL n101i1l : STD_LOGIC; + SIGNAL n101i1O : STD_LOGIC; + SIGNAL n101iii : STD_LOGIC; + SIGNAL n101iil : STD_LOGIC; + SIGNAL n101iiO : STD_LOGIC; + SIGNAL n101ili : STD_LOGIC; + SIGNAL n101ill : STD_LOGIC; + SIGNAL n101ilO : STD_LOGIC; + SIGNAL n101iOi : STD_LOGIC; + SIGNAL n101iOl : STD_LOGIC; + SIGNAL n101iOO : STD_LOGIC; + SIGNAL n101l0i : STD_LOGIC; + SIGNAL n101l0l : STD_LOGIC; + SIGNAL n101l0O : STD_LOGIC; + SIGNAL n101l1i : STD_LOGIC; + SIGNAL n101l1l : STD_LOGIC; + SIGNAL n101l1O : STD_LOGIC; + SIGNAL n101lii : STD_LOGIC; + SIGNAL n101lil : STD_LOGIC; + SIGNAL n101liO : STD_LOGIC; + SIGNAL n101lli : STD_LOGIC; + SIGNAL n101lll : STD_LOGIC; + SIGNAL n101llO : STD_LOGIC; + SIGNAL n101lOi : STD_LOGIC; + SIGNAL n101lOl : STD_LOGIC; + SIGNAL n101lOO : STD_LOGIC; + SIGNAL n101O0i : STD_LOGIC; + SIGNAL n101O0l : STD_LOGIC; + SIGNAL n101O0O : STD_LOGIC; + SIGNAL n101O1i : STD_LOGIC; + SIGNAL n101O1l : STD_LOGIC; + SIGNAL n101O1O : STD_LOGIC; + SIGNAL n101Oii : STD_LOGIC; + SIGNAL n101Oil : STD_LOGIC; + SIGNAL n101OiO : STD_LOGIC; + SIGNAL n101Oli : STD_LOGIC; + SIGNAL n101Oll : STD_LOGIC; + SIGNAL n101OlO : STD_LOGIC; + SIGNAL n101OOi : STD_LOGIC; + SIGNAL n101OOl : STD_LOGIC; + SIGNAL n101OOO : STD_LOGIC; + SIGNAL n10i00i : STD_LOGIC; + SIGNAL n10i00l : STD_LOGIC; + SIGNAL n10i00O : STD_LOGIC; + SIGNAL n10i01i : STD_LOGIC; + SIGNAL n10i01l : STD_LOGIC; + SIGNAL n10i01O : STD_LOGIC; + SIGNAL n10i0ii : STD_LOGIC; + SIGNAL n10i0il : STD_LOGIC; + SIGNAL n10i0iO : STD_LOGIC; + SIGNAL n10i0li : STD_LOGIC; + SIGNAL n10i0ll : STD_LOGIC; + SIGNAL n10i0lO : STD_LOGIC; + SIGNAL n10i0Oi : STD_LOGIC; + SIGNAL n10i0Ol : STD_LOGIC; + SIGNAL n10i0OO : STD_LOGIC; + SIGNAL n10i10i : STD_LOGIC; + SIGNAL n10i10l : STD_LOGIC; + SIGNAL n10i10O : STD_LOGIC; + SIGNAL n10i11i : STD_LOGIC; + SIGNAL n10i11l : STD_LOGIC; + SIGNAL n10i11O : STD_LOGIC; + SIGNAL n10i1ii : STD_LOGIC; + SIGNAL n10i1il : STD_LOGIC; + SIGNAL n10i1iO : STD_LOGIC; + SIGNAL n10i1li : STD_LOGIC; + SIGNAL n10i1ll : STD_LOGIC; + SIGNAL n10i1lO : STD_LOGIC; + SIGNAL n10i1Oi : STD_LOGIC; + SIGNAL n10i1Ol : STD_LOGIC; + SIGNAL n10i1OO : STD_LOGIC; + SIGNAL n10ii0i : STD_LOGIC; + SIGNAL n10ii0l : STD_LOGIC; + SIGNAL n10ii0O : STD_LOGIC; + SIGNAL n10ii1i : STD_LOGIC; + SIGNAL n10ii1l : STD_LOGIC; + SIGNAL n10ii1O : STD_LOGIC; + SIGNAL n10iiii : STD_LOGIC; + SIGNAL n10iiil : STD_LOGIC; + SIGNAL n10iiiO : STD_LOGIC; + SIGNAL n10iili : STD_LOGIC; + SIGNAL n10iill : STD_LOGIC; + SIGNAL n10iilO : STD_LOGIC; + SIGNAL n10iiOi : STD_LOGIC; + SIGNAL n10iiOl : STD_LOGIC; + SIGNAL n10iiOO : STD_LOGIC; + SIGNAL n10il0i : STD_LOGIC; + SIGNAL n10il0l : STD_LOGIC; + SIGNAL n10il0O : STD_LOGIC; + SIGNAL n10il1i : STD_LOGIC; + SIGNAL n10il1l : STD_LOGIC; + SIGNAL n10il1O : STD_LOGIC; + SIGNAL n10ilii : STD_LOGIC; + SIGNAL n10ilil : STD_LOGIC; + SIGNAL n10iliO : STD_LOGIC; + SIGNAL n10illi : STD_LOGIC; + SIGNAL n10illl : STD_LOGIC; + SIGNAL n10illO : STD_LOGIC; + SIGNAL n10ilOi : STD_LOGIC; + SIGNAL n10ilOl : STD_LOGIC; + SIGNAL n10ilOO : STD_LOGIC; + SIGNAL n10iO0i : STD_LOGIC; + SIGNAL n10iO0l : STD_LOGIC; + SIGNAL n10iO0O : STD_LOGIC; + SIGNAL n10iO1i : STD_LOGIC; + SIGNAL n10iO1l : STD_LOGIC; + SIGNAL n10iO1O : STD_LOGIC; + SIGNAL n10iOii : STD_LOGIC; + SIGNAL n10iOil : STD_LOGIC; + SIGNAL n10iOiO : STD_LOGIC; + SIGNAL n10iOli : STD_LOGIC; + SIGNAL n10iOll : STD_LOGIC; + SIGNAL n10iOlO : STD_LOGIC; + SIGNAL n10iOOi : STD_LOGIC; + SIGNAL n10iOOl : STD_LOGIC; + SIGNAL n10iOOO : STD_LOGIC; + SIGNAL n10l00i : STD_LOGIC; + SIGNAL n10l00l : STD_LOGIC; + SIGNAL n10l00O : STD_LOGIC; + SIGNAL n10l01i : STD_LOGIC; + SIGNAL n10l01l : STD_LOGIC; + SIGNAL n10l01O : STD_LOGIC; + SIGNAL n10l0ii : STD_LOGIC; + SIGNAL n10l0il : STD_LOGIC; + SIGNAL n10l0iO : STD_LOGIC; + SIGNAL n10l0li : STD_LOGIC; + SIGNAL n10l0ll : STD_LOGIC; + SIGNAL n10l0lO : STD_LOGIC; + SIGNAL n10l0Oi : STD_LOGIC; + SIGNAL n10l0Ol : STD_LOGIC; + SIGNAL n10l0OO : STD_LOGIC; + SIGNAL n10l10i : STD_LOGIC; + SIGNAL n10l10l : STD_LOGIC; + SIGNAL n10l10O : STD_LOGIC; + SIGNAL n10l11i : STD_LOGIC; + SIGNAL n10l11l : STD_LOGIC; + SIGNAL n10l11O : STD_LOGIC; + SIGNAL n10l1ii : STD_LOGIC; + SIGNAL n10l1il : STD_LOGIC; + SIGNAL n10l1iO : STD_LOGIC; + SIGNAL n10l1li : STD_LOGIC; + SIGNAL n10l1ll : STD_LOGIC; + SIGNAL n10l1lO : STD_LOGIC; + SIGNAL n10l1Oi : STD_LOGIC; + SIGNAL n10l1Ol : STD_LOGIC; + SIGNAL n10l1OO : STD_LOGIC; + SIGNAL n10li0i : STD_LOGIC; + SIGNAL n10li0l : STD_LOGIC; + SIGNAL n10li0O : STD_LOGIC; + SIGNAL n10li1i : STD_LOGIC; + SIGNAL n10li1l : STD_LOGIC; + SIGNAL n10li1O : STD_LOGIC; + SIGNAL n10liii : STD_LOGIC; + SIGNAL n10liil : STD_LOGIC; + SIGNAL n10liiO : STD_LOGIC; + SIGNAL n10lili : STD_LOGIC; + SIGNAL n10lill : STD_LOGIC; + SIGNAL n10lilO : STD_LOGIC; + SIGNAL n10liOi : STD_LOGIC; + SIGNAL n10liOl : STD_LOGIC; + SIGNAL n10liOO : STD_LOGIC; + SIGNAL n10ll0i : STD_LOGIC; + SIGNAL n10ll0l : STD_LOGIC; + SIGNAL n10ll0O : STD_LOGIC; + SIGNAL n10ll1i : STD_LOGIC; + SIGNAL n10ll1l : STD_LOGIC; + SIGNAL n10ll1O : STD_LOGIC; + SIGNAL n10llii : STD_LOGIC; + SIGNAL n10llil : STD_LOGIC; + SIGNAL n10lliO : STD_LOGIC; + SIGNAL n10llli : STD_LOGIC; + SIGNAL n10llll : STD_LOGIC; + SIGNAL n10lllO : STD_LOGIC; + SIGNAL n10llOi : STD_LOGIC; + SIGNAL n10llOl : STD_LOGIC; + SIGNAL n10llOO : STD_LOGIC; + SIGNAL n10lO0i : STD_LOGIC; + SIGNAL n10lO0l : STD_LOGIC; + SIGNAL n10lO0O : STD_LOGIC; + SIGNAL n10lO1i : STD_LOGIC; + SIGNAL n10lO1l : STD_LOGIC; + SIGNAL n10lO1O : STD_LOGIC; + SIGNAL n10lOii : STD_LOGIC; + SIGNAL n10lOil : STD_LOGIC; + SIGNAL n10lOiO : STD_LOGIC; + SIGNAL n10lOli : STD_LOGIC; + SIGNAL n10lOll : STD_LOGIC; + SIGNAL n10lOlO : STD_LOGIC; + SIGNAL n10lOOi : STD_LOGIC; + SIGNAL n10lOOl : STD_LOGIC; + SIGNAL n10lOOO : STD_LOGIC; + SIGNAL n10O00i : STD_LOGIC; + SIGNAL n10O00l : STD_LOGIC; + SIGNAL n10O00O : STD_LOGIC; + SIGNAL n10O01i : STD_LOGIC; + SIGNAL n10O01l : STD_LOGIC; + SIGNAL n10O01O : STD_LOGIC; + SIGNAL n10O0ii : STD_LOGIC; + SIGNAL n10O0il : STD_LOGIC; + SIGNAL n10O0iO : STD_LOGIC; + SIGNAL n10O0li : STD_LOGIC; + SIGNAL n10O0ll : STD_LOGIC; + SIGNAL n10O0lO : STD_LOGIC; + SIGNAL n10O0Oi : STD_LOGIC; + SIGNAL n10O0Ol : STD_LOGIC; + SIGNAL n10O0OO : STD_LOGIC; + SIGNAL n10O10i : STD_LOGIC; + SIGNAL n10O10l : STD_LOGIC; + SIGNAL n10O10O : STD_LOGIC; + SIGNAL n10O11i : STD_LOGIC; + SIGNAL n10O11l : STD_LOGIC; + SIGNAL n10O11O : STD_LOGIC; + SIGNAL n10O1ii : STD_LOGIC; + SIGNAL n10O1il : STD_LOGIC; + SIGNAL n10O1iO : STD_LOGIC; + SIGNAL n10O1li : STD_LOGIC; + SIGNAL n10O1ll : STD_LOGIC; + SIGNAL n10O1lO : STD_LOGIC; + SIGNAL n10O1Oi : STD_LOGIC; + SIGNAL n10O1Ol : STD_LOGIC; + SIGNAL n10O1OO : STD_LOGIC; + SIGNAL n10Oi0i : STD_LOGIC; + SIGNAL n10Oi0l : STD_LOGIC; + SIGNAL n10Oi0O : STD_LOGIC; + SIGNAL n10Oi1i : STD_LOGIC; + SIGNAL n10Oi1l : STD_LOGIC; + SIGNAL n10Oi1O : STD_LOGIC; + SIGNAL n10Oiii : STD_LOGIC; + SIGNAL n10Oiil : STD_LOGIC; + SIGNAL n10OiiO : STD_LOGIC; + SIGNAL n10Oili : STD_LOGIC; + SIGNAL n10Oill : STD_LOGIC; + SIGNAL n10OilO : STD_LOGIC; + SIGNAL n10OiOi : STD_LOGIC; + SIGNAL n10OiOl : STD_LOGIC; + SIGNAL n10OiOO : STD_LOGIC; + SIGNAL n10Ol0i : STD_LOGIC; + SIGNAL n10Ol0l : STD_LOGIC; + SIGNAL n10Ol0O : STD_LOGIC; + SIGNAL n10Ol1i : STD_LOGIC; + SIGNAL n10Ol1l : STD_LOGIC; + SIGNAL n10Ol1O : STD_LOGIC; + SIGNAL n10Olii : STD_LOGIC; + SIGNAL n10Olil : STD_LOGIC; + SIGNAL n10OliO : STD_LOGIC; + SIGNAL n10Olli : STD_LOGIC; + SIGNAL n10Olll : STD_LOGIC; + SIGNAL n10OllO : STD_LOGIC; + SIGNAL n10OlOi : STD_LOGIC; + SIGNAL n10OlOl : STD_LOGIC; + SIGNAL n10OlOO : STD_LOGIC; + SIGNAL n10OO0i : STD_LOGIC; + SIGNAL n10OO0l : STD_LOGIC; + SIGNAL n10OO0O : STD_LOGIC; + SIGNAL n10OO1i : STD_LOGIC; + SIGNAL n10OO1l : STD_LOGIC; + SIGNAL n10OO1O : STD_LOGIC; + SIGNAL n10OOii : STD_LOGIC; + SIGNAL n10OOil : STD_LOGIC; + SIGNAL n10OOiO : STD_LOGIC; + SIGNAL n10OOli : STD_LOGIC; + SIGNAL n10OOll : STD_LOGIC; + SIGNAL n10OOlO : STD_LOGIC; + SIGNAL n10OOOi : STD_LOGIC; + SIGNAL n10OOOl : STD_LOGIC; + SIGNAL n10OOOO : STD_LOGIC; + SIGNAL n11000i : STD_LOGIC; + SIGNAL n11000l : STD_LOGIC; + SIGNAL n11000O : STD_LOGIC; + SIGNAL n11001i : STD_LOGIC; + SIGNAL n11001l : STD_LOGIC; + SIGNAL n11001O : STD_LOGIC; + SIGNAL n1100ii : STD_LOGIC; + SIGNAL n1100il : STD_LOGIC; + SIGNAL n1100iO : STD_LOGIC; + SIGNAL n1100li : STD_LOGIC; + SIGNAL n1100ll : STD_LOGIC; + SIGNAL n1100lO : STD_LOGIC; + SIGNAL n1100Oi : STD_LOGIC; + SIGNAL n1100Ol : STD_LOGIC; + SIGNAL n1100OO : STD_LOGIC; + SIGNAL n11010i : STD_LOGIC; + SIGNAL n11010l : STD_LOGIC; + SIGNAL n11010O : STD_LOGIC; + SIGNAL n11011i : STD_LOGIC; + SIGNAL n11011l : STD_LOGIC; + SIGNAL n11011O : STD_LOGIC; + SIGNAL n1101ii : STD_LOGIC; + SIGNAL n1101il : STD_LOGIC; + SIGNAL n1101iO : STD_LOGIC; + SIGNAL n1101li : STD_LOGIC; + SIGNAL n1101ll : STD_LOGIC; + SIGNAL n1101lO : STD_LOGIC; + SIGNAL n1101Oi : STD_LOGIC; + SIGNAL n1101Ol : STD_LOGIC; + SIGNAL n1101OO : STD_LOGIC; + SIGNAL n110i0i : STD_LOGIC; + SIGNAL n110i0l : STD_LOGIC; + SIGNAL n110i0O : STD_LOGIC; + SIGNAL n110i1i : STD_LOGIC; + SIGNAL n110i1l : STD_LOGIC; + SIGNAL n110i1O : STD_LOGIC; + SIGNAL n110iii : STD_LOGIC; + SIGNAL n110iil : STD_LOGIC; + SIGNAL n110iiO : STD_LOGIC; + SIGNAL n110ili : STD_LOGIC; + SIGNAL n110ill : STD_LOGIC; + SIGNAL n110ilO : STD_LOGIC; + SIGNAL n110iOi : STD_LOGIC; + SIGNAL n110iOl : STD_LOGIC; + SIGNAL n110iOO : STD_LOGIC; + SIGNAL n110l0i : STD_LOGIC; + SIGNAL n110l0l : STD_LOGIC; + SIGNAL n110l0O : STD_LOGIC; + SIGNAL n110l1i : STD_LOGIC; + SIGNAL n110l1l : STD_LOGIC; + SIGNAL n110l1O : STD_LOGIC; + SIGNAL n110lii : STD_LOGIC; + SIGNAL n110lil : STD_LOGIC; + SIGNAL n110liO : STD_LOGIC; + SIGNAL n110lli : STD_LOGIC; + SIGNAL n110lll : STD_LOGIC; + SIGNAL n110llO : STD_LOGIC; + SIGNAL n110lOi : STD_LOGIC; + SIGNAL n110lOl : STD_LOGIC; + SIGNAL n110lOO : STD_LOGIC; + SIGNAL n110O0i : STD_LOGIC; + SIGNAL n110O0l : STD_LOGIC; + SIGNAL n110O0O : STD_LOGIC; + SIGNAL n110O1i : STD_LOGIC; + SIGNAL n110O1l : STD_LOGIC; + SIGNAL n110O1O : STD_LOGIC; + SIGNAL n110Oii : STD_LOGIC; + SIGNAL n110Oil : STD_LOGIC; + SIGNAL n110OiO : STD_LOGIC; + SIGNAL n110Oli : STD_LOGIC; + SIGNAL n110Oll : STD_LOGIC; + SIGNAL n110OlO : STD_LOGIC; + SIGNAL n110OOi : STD_LOGIC; + SIGNAL n110OOl : STD_LOGIC; + SIGNAL n110OOO : STD_LOGIC; + SIGNAL n11100i : STD_LOGIC; + SIGNAL n11100l : STD_LOGIC; + SIGNAL n11100O : STD_LOGIC; + SIGNAL n11101i : STD_LOGIC; + SIGNAL n11101l : STD_LOGIC; + SIGNAL n11101O : STD_LOGIC; + SIGNAL n1110ii : STD_LOGIC; + SIGNAL n1110il : STD_LOGIC; + SIGNAL n1110iO : STD_LOGIC; + SIGNAL n1110li : STD_LOGIC; + SIGNAL n1110ll : STD_LOGIC; + SIGNAL n1110lO : STD_LOGIC; + SIGNAL n1110Oi : STD_LOGIC; + SIGNAL n1110Ol : STD_LOGIC; + SIGNAL n1110OO : STD_LOGIC; + SIGNAL n11110i : STD_LOGIC; + SIGNAL n11110l : STD_LOGIC; + SIGNAL n11110O : STD_LOGIC; + SIGNAL n11111i : STD_LOGIC; + SIGNAL n11111l : STD_LOGIC; + SIGNAL n11111O : STD_LOGIC; + SIGNAL n1111ii : STD_LOGIC; + SIGNAL n1111il : STD_LOGIC; + SIGNAL n1111iO : STD_LOGIC; + SIGNAL n1111li : STD_LOGIC; + SIGNAL n1111ll : STD_LOGIC; + SIGNAL n1111lO : STD_LOGIC; + SIGNAL n1111Oi : STD_LOGIC; + SIGNAL n1111Ol : STD_LOGIC; + SIGNAL n1111OO : STD_LOGIC; + SIGNAL n111i0i : STD_LOGIC; + SIGNAL n111i0l : STD_LOGIC; + SIGNAL n111i0O : STD_LOGIC; + SIGNAL n111i1i : STD_LOGIC; + SIGNAL n111i1l : STD_LOGIC; + SIGNAL n111i1O : STD_LOGIC; + SIGNAL n111iii : STD_LOGIC; + SIGNAL n111iil : STD_LOGIC; + SIGNAL n111iiO : STD_LOGIC; + SIGNAL n111ili : STD_LOGIC; + SIGNAL n111ill : STD_LOGIC; + SIGNAL n111ilO : STD_LOGIC; + SIGNAL n111iOi : STD_LOGIC; + SIGNAL n111iOl : STD_LOGIC; + SIGNAL n111iOO : STD_LOGIC; + SIGNAL n111l0i : STD_LOGIC; + SIGNAL n111l0l : STD_LOGIC; + SIGNAL n111l0O : STD_LOGIC; + SIGNAL n111l1i : STD_LOGIC; + SIGNAL n111l1l : STD_LOGIC; + SIGNAL n111l1O : STD_LOGIC; + SIGNAL n111lii : STD_LOGIC; + SIGNAL n111lil : STD_LOGIC; + SIGNAL n111liO : STD_LOGIC; + SIGNAL n111lli : STD_LOGIC; + SIGNAL n111lll : STD_LOGIC; + SIGNAL n111llO : STD_LOGIC; + SIGNAL n111lOi : STD_LOGIC; + SIGNAL n111lOl : STD_LOGIC; + SIGNAL n111lOO : STD_LOGIC; + SIGNAL n111O0i : STD_LOGIC; + SIGNAL n111O0l : STD_LOGIC; + SIGNAL n111O0O : STD_LOGIC; + SIGNAL n111O1i : STD_LOGIC; + SIGNAL n111O1l : STD_LOGIC; + SIGNAL n111O1O : STD_LOGIC; + SIGNAL n111Oii : STD_LOGIC; + SIGNAL n111Oil : STD_LOGIC; + SIGNAL n111OiO : STD_LOGIC; + SIGNAL n111Oli : STD_LOGIC; + SIGNAL n111Oll : STD_LOGIC; + SIGNAL n111OlO : STD_LOGIC; + SIGNAL n111OOi : STD_LOGIC; + SIGNAL n111OOl : STD_LOGIC; + SIGNAL n111OOO : STD_LOGIC; + SIGNAL n11i00i : STD_LOGIC; + SIGNAL n11i00l : STD_LOGIC; + SIGNAL n11i00O : STD_LOGIC; + SIGNAL n11i01i : STD_LOGIC; + SIGNAL n11i01l : STD_LOGIC; + SIGNAL n11i01O : STD_LOGIC; + SIGNAL n11i0ii : STD_LOGIC; + SIGNAL n11i0il : STD_LOGIC; + SIGNAL n11i0iO : STD_LOGIC; + SIGNAL n11i0li : STD_LOGIC; + SIGNAL n11i0ll : STD_LOGIC; + SIGNAL n11i0lO : STD_LOGIC; + SIGNAL n11i0Oi : STD_LOGIC; + SIGNAL n11i0Ol : STD_LOGIC; + SIGNAL n11i0OO : STD_LOGIC; + SIGNAL n11i10i : STD_LOGIC; + SIGNAL n11i10l : STD_LOGIC; + SIGNAL n11i10O : STD_LOGIC; + SIGNAL n11i11i : STD_LOGIC; + SIGNAL n11i11l : STD_LOGIC; + SIGNAL n11i11O : STD_LOGIC; + SIGNAL n11i1ii : STD_LOGIC; + SIGNAL n11i1il : STD_LOGIC; + SIGNAL n11i1iO : STD_LOGIC; + SIGNAL n11i1li : STD_LOGIC; + SIGNAL n11i1ll : STD_LOGIC; + SIGNAL n11i1lO : STD_LOGIC; + SIGNAL n11i1Oi : STD_LOGIC; + SIGNAL n11i1Ol : STD_LOGIC; + SIGNAL n11i1OO : STD_LOGIC; + SIGNAL n11ii0i : STD_LOGIC; + SIGNAL n11ii0l : STD_LOGIC; + SIGNAL n11ii0O : STD_LOGIC; + SIGNAL n11ii1i : STD_LOGIC; + SIGNAL n11ii1l : STD_LOGIC; + SIGNAL n11ii1O : STD_LOGIC; + SIGNAL n11iiii : STD_LOGIC; + SIGNAL n11iiil : STD_LOGIC; + SIGNAL n11iiiO : STD_LOGIC; + SIGNAL n11iili : STD_LOGIC; + SIGNAL n11iill : STD_LOGIC; + SIGNAL n11iilO : STD_LOGIC; + SIGNAL n11iiOi : STD_LOGIC; + SIGNAL n11iiOl : STD_LOGIC; + SIGNAL n11iiOO : STD_LOGIC; + SIGNAL n11il0i : STD_LOGIC; + SIGNAL n11il0l : STD_LOGIC; + SIGNAL n11il0O : STD_LOGIC; + SIGNAL n11il1i : STD_LOGIC; + SIGNAL n11il1l : STD_LOGIC; + SIGNAL n11il1O : STD_LOGIC; + SIGNAL n11ilii : STD_LOGIC; + SIGNAL n11ilil : STD_LOGIC; + SIGNAL n11iliO : STD_LOGIC; + SIGNAL n11illi : STD_LOGIC; + SIGNAL n11illl : STD_LOGIC; + SIGNAL n11illO : STD_LOGIC; + SIGNAL n11ilOi : STD_LOGIC; + SIGNAL n11ilOl : STD_LOGIC; + SIGNAL n11ilOO : STD_LOGIC; + SIGNAL n11iO0i : STD_LOGIC; + SIGNAL n11iO0l : STD_LOGIC; + SIGNAL n11iO0O : STD_LOGIC; + SIGNAL n11iO1i : STD_LOGIC; + SIGNAL n11iO1l : STD_LOGIC; + SIGNAL n11iO1O : STD_LOGIC; + SIGNAL n11iOii : STD_LOGIC; + SIGNAL n11iOil : STD_LOGIC; + SIGNAL n11iOiO : STD_LOGIC; + SIGNAL n11iOli : STD_LOGIC; + SIGNAL n11iOll : STD_LOGIC; + SIGNAL n11iOlO : STD_LOGIC; + SIGNAL n11iOOi : STD_LOGIC; + SIGNAL n11iOOl : STD_LOGIC; + SIGNAL n11iOOO : STD_LOGIC; + SIGNAL n11l00i : STD_LOGIC; + SIGNAL n11l00l : STD_LOGIC; + SIGNAL n11l00O : STD_LOGIC; + SIGNAL n11l01i : STD_LOGIC; + SIGNAL n11l01l : STD_LOGIC; + SIGNAL n11l01O : STD_LOGIC; + SIGNAL n11l0ii : STD_LOGIC; + SIGNAL n11l0il : STD_LOGIC; + SIGNAL n11l0iO : STD_LOGIC; + SIGNAL n11l0li : STD_LOGIC; + SIGNAL n11l0ll : STD_LOGIC; + SIGNAL n11l0lO : STD_LOGIC; + SIGNAL n11l0Oi : STD_LOGIC; + SIGNAL n11l0Ol : STD_LOGIC; + SIGNAL n11l0OO : STD_LOGIC; + SIGNAL n11l10i : STD_LOGIC; + SIGNAL n11l10l : STD_LOGIC; + SIGNAL n11l10O : STD_LOGIC; + SIGNAL n11l11i : STD_LOGIC; + SIGNAL n11l11l : STD_LOGIC; + SIGNAL n11l11O : STD_LOGIC; + SIGNAL n11l1ii : STD_LOGIC; + SIGNAL n11l1il : STD_LOGIC; + SIGNAL n11l1iO : STD_LOGIC; + SIGNAL n11l1li : STD_LOGIC; + SIGNAL n11l1ll : STD_LOGIC; + SIGNAL n11l1lO : STD_LOGIC; + SIGNAL n11l1Oi : STD_LOGIC; + SIGNAL n11l1Ol : STD_LOGIC; + SIGNAL n11l1OO : STD_LOGIC; + SIGNAL n11li0i : STD_LOGIC; + SIGNAL n11li0l : STD_LOGIC; + SIGNAL n11li0O : STD_LOGIC; + SIGNAL n11li1i : STD_LOGIC; + SIGNAL n11li1l : STD_LOGIC; + SIGNAL n11li1O : STD_LOGIC; + SIGNAL n11liii : STD_LOGIC; + SIGNAL n11liil : STD_LOGIC; + SIGNAL n11liiO : STD_LOGIC; + SIGNAL n11lili : STD_LOGIC; + SIGNAL n11lill : STD_LOGIC; + SIGNAL n11lilO : STD_LOGIC; + SIGNAL n11liOi : STD_LOGIC; + SIGNAL n11liOl : STD_LOGIC; + SIGNAL n11liOO : STD_LOGIC; + SIGNAL n11ll0i : STD_LOGIC; + SIGNAL n11ll0l : STD_LOGIC; + SIGNAL n11ll0O : STD_LOGIC; + SIGNAL n11ll1i : STD_LOGIC; + SIGNAL n11ll1l : STD_LOGIC; + SIGNAL n11ll1O : STD_LOGIC; + SIGNAL n11llii : STD_LOGIC; + SIGNAL n11llil : STD_LOGIC; + SIGNAL n11lliO : STD_LOGIC; + SIGNAL n11llli : STD_LOGIC; + SIGNAL n11llll : STD_LOGIC; + SIGNAL n11lllO : STD_LOGIC; + SIGNAL n11llOi : STD_LOGIC; + SIGNAL n11llOl : STD_LOGIC; + SIGNAL n11llOO : STD_LOGIC; + SIGNAL n11lO0i : STD_LOGIC; + SIGNAL n11lO0l : STD_LOGIC; + SIGNAL n11lO0O : STD_LOGIC; + SIGNAL n11lO1i : STD_LOGIC; + SIGNAL n11lO1l : STD_LOGIC; + SIGNAL n11lO1O : STD_LOGIC; + SIGNAL n11lOii : STD_LOGIC; + SIGNAL n11lOil : STD_LOGIC; + SIGNAL n11lOiO : STD_LOGIC; + SIGNAL n11lOli : STD_LOGIC; + SIGNAL n11lOll : STD_LOGIC; + SIGNAL n11lOlO : STD_LOGIC; + SIGNAL n11lOOi : STD_LOGIC; + SIGNAL n11lOOl : STD_LOGIC; + SIGNAL n11lOOO : STD_LOGIC; + SIGNAL n11O00i : STD_LOGIC; + SIGNAL n11O00l : STD_LOGIC; + SIGNAL n11O00O : STD_LOGIC; + SIGNAL n11O01i : STD_LOGIC; + SIGNAL n11O01l : STD_LOGIC; + SIGNAL n11O01O : STD_LOGIC; + SIGNAL n11O0ii : STD_LOGIC; + SIGNAL n11O0il : STD_LOGIC; + SIGNAL n11O0iO : STD_LOGIC; + SIGNAL n11O0li : STD_LOGIC; + SIGNAL n11O0ll : STD_LOGIC; + SIGNAL n11O0lO : STD_LOGIC; + SIGNAL n11O0Oi : STD_LOGIC; + SIGNAL n11O0Ol : STD_LOGIC; + SIGNAL n11O0OO : STD_LOGIC; + SIGNAL n11O10i : STD_LOGIC; + SIGNAL n11O10l : STD_LOGIC; + SIGNAL n11O10O : STD_LOGIC; + SIGNAL n11O11i : STD_LOGIC; + SIGNAL n11O11l : STD_LOGIC; + SIGNAL n11O11O : STD_LOGIC; + SIGNAL n11O1ii : STD_LOGIC; + SIGNAL n11O1il : STD_LOGIC; + SIGNAL n11O1iO : STD_LOGIC; + SIGNAL n11O1li : STD_LOGIC; + SIGNAL n11O1ll : STD_LOGIC; + SIGNAL n11O1lO : STD_LOGIC; + SIGNAL n11O1Oi : STD_LOGIC; + SIGNAL n11O1Ol : STD_LOGIC; + SIGNAL n11O1OO : STD_LOGIC; + SIGNAL n11Oi0i : STD_LOGIC; + SIGNAL n11Oi0l : STD_LOGIC; + SIGNAL n11Oi0O : STD_LOGIC; + SIGNAL n11Oi1i : STD_LOGIC; + SIGNAL n11Oi1l : STD_LOGIC; + SIGNAL n11Oi1O : STD_LOGIC; + SIGNAL n11Oiii : STD_LOGIC; + SIGNAL n11Oiil : STD_LOGIC; + SIGNAL n11OiiO : STD_LOGIC; + SIGNAL n11Oili : STD_LOGIC; + SIGNAL n11Oill : STD_LOGIC; + SIGNAL n11OilO : STD_LOGIC; + SIGNAL n11OiOi : STD_LOGIC; + SIGNAL n11OiOl : STD_LOGIC; + SIGNAL n11OiOO : STD_LOGIC; + SIGNAL n11Ol0i : STD_LOGIC; + SIGNAL n11Ol0l : STD_LOGIC; + SIGNAL n11Ol0O : STD_LOGIC; + SIGNAL n11Ol1i : STD_LOGIC; + SIGNAL n11Ol1l : STD_LOGIC; + SIGNAL n11Ol1O : STD_LOGIC; + SIGNAL n11Olii : STD_LOGIC; + SIGNAL n11Olil : STD_LOGIC; + SIGNAL n11OliO : STD_LOGIC; + SIGNAL n11Olli : STD_LOGIC; + SIGNAL n11Olll : STD_LOGIC; + SIGNAL n11OllO : STD_LOGIC; + SIGNAL n11OlOi : STD_LOGIC; + SIGNAL n11OlOl : STD_LOGIC; + SIGNAL n11OlOO : STD_LOGIC; + SIGNAL n11OO0i : STD_LOGIC; + SIGNAL n11OO0l : STD_LOGIC; + SIGNAL n11OO0O : STD_LOGIC; + SIGNAL n11OO1i : STD_LOGIC; + SIGNAL n11OO1l : STD_LOGIC; + SIGNAL n11OO1O : STD_LOGIC; + SIGNAL n11OOii : STD_LOGIC; + SIGNAL n11OOil : STD_LOGIC; + SIGNAL n11OOiO : STD_LOGIC; + SIGNAL n11OOli : STD_LOGIC; + SIGNAL n11OOll : STD_LOGIC; + SIGNAL n11OOlO : STD_LOGIC; + SIGNAL n11OOOi : STD_LOGIC; + SIGNAL n11OOOl : STD_LOGIC; + SIGNAL n11OOOO : STD_LOGIC; + SIGNAL n1i000i : STD_LOGIC; + SIGNAL n1i000l : STD_LOGIC; + SIGNAL n1i000O : STD_LOGIC; + SIGNAL n1i001i : STD_LOGIC; + SIGNAL n1i001l : STD_LOGIC; + SIGNAL n1i001O : STD_LOGIC; + SIGNAL n1i00ii : STD_LOGIC; + SIGNAL n1i00il : STD_LOGIC; + SIGNAL n1i00iO : STD_LOGIC; + SIGNAL n1i00li : STD_LOGIC; + SIGNAL n1i00ll : STD_LOGIC; + SIGNAL n1i00lO : STD_LOGIC; + SIGNAL n1i00Oi : STD_LOGIC; + SIGNAL n1i00Ol : STD_LOGIC; + SIGNAL n1i010i : STD_LOGIC; + SIGNAL n1i010l : STD_LOGIC; + SIGNAL n1i010O : STD_LOGIC; + SIGNAL n1i011i : STD_LOGIC; + SIGNAL n1i011l : STD_LOGIC; + SIGNAL n1i011O : STD_LOGIC; + SIGNAL n1i01ii : STD_LOGIC; + SIGNAL n1i01il : STD_LOGIC; + SIGNAL n1i01iO : STD_LOGIC; + SIGNAL n1i01li : STD_LOGIC; + SIGNAL n1i01ll : STD_LOGIC; + SIGNAL n1i01lO : STD_LOGIC; + SIGNAL n1i01Oi : STD_LOGIC; + SIGNAL n1i01Ol : STD_LOGIC; + SIGNAL n1i01OO : STD_LOGIC; + SIGNAL n1i0i0i : STD_LOGIC; + SIGNAL n1i0i0l : STD_LOGIC; + SIGNAL n1i0i0O : STD_LOGIC; + SIGNAL n1i0i1i : STD_LOGIC; + SIGNAL n1i0i1l : STD_LOGIC; + SIGNAL n1i0i1O : STD_LOGIC; + SIGNAL n1i0iii : STD_LOGIC; + SIGNAL n1i0iil : STD_LOGIC; + SIGNAL n1i0iiO : STD_LOGIC; + SIGNAL n1i0ili : STD_LOGIC; + SIGNAL n1i0ill : STD_LOGIC; + SIGNAL n1i0ilO : STD_LOGIC; + SIGNAL n1i0iOi : STD_LOGIC; + SIGNAL n1i0iOl : STD_LOGIC; + SIGNAL n1i0iOO : STD_LOGIC; + SIGNAL n1i0l0i : STD_LOGIC; + SIGNAL n1i0l0l : STD_LOGIC; + SIGNAL n1i0l0O : STD_LOGIC; + SIGNAL n1i0l1i : STD_LOGIC; + SIGNAL n1i0l1l : STD_LOGIC; + SIGNAL n1i0l1O : STD_LOGIC; + SIGNAL n1i0lii : STD_LOGIC; + SIGNAL n1i0lil : STD_LOGIC; + SIGNAL n1i0liO : STD_LOGIC; + SIGNAL n1i0lli : STD_LOGIC; + SIGNAL n1i0lll : STD_LOGIC; + SIGNAL n1i0llO : STD_LOGIC; + SIGNAL n1i0lOO : STD_LOGIC; + SIGNAL n1i0O0O : STD_LOGIC; + SIGNAL n1i0O1i : STD_LOGIC; + SIGNAL n1i0Oii : STD_LOGIC; + SIGNAL n1i100i : STD_LOGIC; + SIGNAL n1i100l : STD_LOGIC; + SIGNAL n1i100O : STD_LOGIC; + SIGNAL n1i101i : STD_LOGIC; + SIGNAL n1i101l : STD_LOGIC; + SIGNAL n1i101O : STD_LOGIC; + SIGNAL n1i10ii : STD_LOGIC; + SIGNAL n1i10il : STD_LOGIC; + SIGNAL n1i10iO : STD_LOGIC; + SIGNAL n1i10li : STD_LOGIC; + SIGNAL n1i10ll : STD_LOGIC; + SIGNAL n1i10lO : STD_LOGIC; + SIGNAL n1i10Oi : STD_LOGIC; + SIGNAL n1i10Ol : STD_LOGIC; + SIGNAL n1i10OO : STD_LOGIC; + SIGNAL n1i110i : STD_LOGIC; + SIGNAL n1i110l : STD_LOGIC; + SIGNAL n1i110O : STD_LOGIC; + SIGNAL n1i111i : STD_LOGIC; + SIGNAL n1i111l : STD_LOGIC; + SIGNAL n1i111O : STD_LOGIC; + SIGNAL n1i11ii : STD_LOGIC; + SIGNAL n1i11il : STD_LOGIC; + SIGNAL n1i11iO : STD_LOGIC; + SIGNAL n1i11li : STD_LOGIC; + SIGNAL n1i11ll : STD_LOGIC; + SIGNAL n1i11lO : STD_LOGIC; + SIGNAL n1i11Oi : STD_LOGIC; + SIGNAL n1i11Ol : STD_LOGIC; + SIGNAL n1i11OO : STD_LOGIC; + SIGNAL n1i1i0i : STD_LOGIC; + SIGNAL n1i1i0l : STD_LOGIC; + SIGNAL n1i1i0O : STD_LOGIC; + SIGNAL n1i1i1i : STD_LOGIC; + SIGNAL n1i1i1l : STD_LOGIC; + SIGNAL n1i1i1O : STD_LOGIC; + SIGNAL n1i1iii : STD_LOGIC; + SIGNAL n1i1iil : STD_LOGIC; + SIGNAL n1i1iiO : STD_LOGIC; + SIGNAL n1i1ili : STD_LOGIC; + SIGNAL n1i1ill : STD_LOGIC; + SIGNAL n1i1ilO : STD_LOGIC; + SIGNAL n1i1iOi : STD_LOGIC; + SIGNAL n1i1iOl : STD_LOGIC; + SIGNAL n1i1iOO : STD_LOGIC; + SIGNAL n1i1l0i : STD_LOGIC; + SIGNAL n1i1l0l : STD_LOGIC; + SIGNAL n1i1l0O : STD_LOGIC; + SIGNAL n1i1l1i : STD_LOGIC; + SIGNAL n1i1l1l : STD_LOGIC; + SIGNAL n1i1l1O : STD_LOGIC; + SIGNAL n1i1lii : STD_LOGIC; + SIGNAL n1i1lil : STD_LOGIC; + SIGNAL n1i1liO : STD_LOGIC; + SIGNAL n1i1lli : STD_LOGIC; + SIGNAL n1i1lll : STD_LOGIC; + SIGNAL n1i1llO : STD_LOGIC; + SIGNAL n1i1lOi : STD_LOGIC; + SIGNAL n1i1lOl : STD_LOGIC; + SIGNAL n1i1lOO : STD_LOGIC; + SIGNAL n1i1O0i : STD_LOGIC; + SIGNAL n1i1O0l : STD_LOGIC; + SIGNAL n1i1O0O : STD_LOGIC; + SIGNAL n1i1O1i : STD_LOGIC; + SIGNAL n1i1O1l : STD_LOGIC; + SIGNAL n1i1O1O : STD_LOGIC; + SIGNAL n1i1Oii : STD_LOGIC; + SIGNAL n1i1Oil : STD_LOGIC; + SIGNAL n1i1OiO : STD_LOGIC; + SIGNAL n1i1Oli : STD_LOGIC; + SIGNAL n1i1Oll : STD_LOGIC; + SIGNAL n1i1OlO : STD_LOGIC; + SIGNAL n1i1OOi : STD_LOGIC; + SIGNAL n1i1OOl : STD_LOGIC; + SIGNAL n1i1OOO : STD_LOGIC; + SIGNAL n1ii00i : STD_LOGIC; + SIGNAL n1ii00l : STD_LOGIC; + SIGNAL n1ii01i : STD_LOGIC; + SIGNAL n1ii01l : STD_LOGIC; + SIGNAL n1ii01O : STD_LOGIC; + SIGNAL n1ii0iO : STD_LOGIC; + SIGNAL n1ii0li : STD_LOGIC; + SIGNAL n1ii0Oi : STD_LOGIC; + SIGNAL n1ii0Ol : STD_LOGIC; + SIGNAL n1ii10i : STD_LOGIC; + SIGNAL n1ii10O : STD_LOGIC; + SIGNAL n1ii11i : STD_LOGIC; + SIGNAL n1ii11l : STD_LOGIC; + SIGNAL n1ii11O : STD_LOGIC; + SIGNAL n1ii1lO : STD_LOGIC; + SIGNAL n1ii1OO : STD_LOGIC; + SIGNAL n1iii1i : STD_LOGIC; + SIGNAL n1iii1l : STD_LOGIC; + SIGNAL n1iii1O : STD_LOGIC; + SIGNAL n1iiili : STD_LOGIC; + SIGNAL n1iiill : STD_LOGIC; + SIGNAL n1iiilO : STD_LOGIC; + SIGNAL n1iiiOi : STD_LOGIC; + SIGNAL n1iil0i : STD_LOGIC; + SIGNAL nlOO000i : STD_LOGIC; + SIGNAL nlOO000l : STD_LOGIC; + SIGNAL nlOO000O : STD_LOGIC; + SIGNAL nlOO001i : STD_LOGIC; + SIGNAL nlOO001l : STD_LOGIC; + SIGNAL nlOO001O : STD_LOGIC; + SIGNAL nlOO00ii : STD_LOGIC; + SIGNAL nlOO00il : STD_LOGIC; + SIGNAL nlOO00iO : STD_LOGIC; + SIGNAL nlOO00li : STD_LOGIC; + SIGNAL nlOO00ll : STD_LOGIC; + SIGNAL nlOO00lO : STD_LOGIC; + SIGNAL nlOO00Oi : STD_LOGIC; + SIGNAL nlOO00Ol : STD_LOGIC; + SIGNAL nlOO00OO : STD_LOGIC; + SIGNAL nlOO010i : STD_LOGIC; + SIGNAL nlOO010l : STD_LOGIC; + SIGNAL nlOO010O : STD_LOGIC; + SIGNAL nlOO011i : STD_LOGIC; + SIGNAL nlOO011l : STD_LOGIC; + SIGNAL nlOO011O : STD_LOGIC; + SIGNAL nlOO01ii : STD_LOGIC; + SIGNAL nlOO01il : STD_LOGIC; + SIGNAL nlOO01iO : STD_LOGIC; + SIGNAL nlOO01li : STD_LOGIC; + SIGNAL nlOO01ll : STD_LOGIC; + SIGNAL nlOO01lO : STD_LOGIC; + SIGNAL nlOO01Oi : STD_LOGIC; + SIGNAL nlOO01Ol : STD_LOGIC; + SIGNAL nlOO01OO : STD_LOGIC; + SIGNAL nlOO0i0i : STD_LOGIC; + SIGNAL nlOO0i0l : STD_LOGIC; + SIGNAL nlOO0i0O : STD_LOGIC; + SIGNAL nlOO0i1i : STD_LOGIC; + SIGNAL nlOO0i1l : STD_LOGIC; + SIGNAL nlOO0i1O : STD_LOGIC; + SIGNAL nlOO0iii : STD_LOGIC; + SIGNAL nlOO0iil : STD_LOGIC; + SIGNAL nlOO0iiO : STD_LOGIC; + SIGNAL nlOO0ili : STD_LOGIC; + SIGNAL nlOO0ill : STD_LOGIC; + SIGNAL nlOO0ilO : STD_LOGIC; + SIGNAL nlOO0iOi : STD_LOGIC; + SIGNAL nlOO0iOl : STD_LOGIC; + SIGNAL nlOO0iOO : STD_LOGIC; + SIGNAL nlOO0l0i : STD_LOGIC; + SIGNAL nlOO0l0l : STD_LOGIC; + SIGNAL nlOO0l0O : STD_LOGIC; + SIGNAL nlOO0l1i : STD_LOGIC; + SIGNAL nlOO0l1l : STD_LOGIC; + SIGNAL nlOO0l1O : STD_LOGIC; + SIGNAL nlOO0lii : STD_LOGIC; + SIGNAL nlOO0lil : STD_LOGIC; + SIGNAL nlOO0liO : STD_LOGIC; + SIGNAL nlOO0lli : STD_LOGIC; + SIGNAL nlOO0lll : STD_LOGIC; + SIGNAL nlOO0llO : STD_LOGIC; + SIGNAL nlOO0lOi : STD_LOGIC; + SIGNAL nlOO0lOl : STD_LOGIC; + SIGNAL nlOO0lOO : STD_LOGIC; + SIGNAL nlOO0O0i : STD_LOGIC; + SIGNAL nlOO0O0l : STD_LOGIC; + SIGNAL nlOO0O0O : STD_LOGIC; + SIGNAL nlOO0O1i : STD_LOGIC; + SIGNAL nlOO0O1l : STD_LOGIC; + SIGNAL nlOO0O1O : STD_LOGIC; + SIGNAL nlOO0Oii : STD_LOGIC; + SIGNAL nlOO0Oil : STD_LOGIC; + SIGNAL nlOO0OiO : STD_LOGIC; + SIGNAL nlOO0Oli : STD_LOGIC; + SIGNAL nlOO0Oll : STD_LOGIC; + SIGNAL nlOO0OlO : STD_LOGIC; + SIGNAL nlOO0OOi : STD_LOGIC; + SIGNAL nlOO0OOl : STD_LOGIC; + SIGNAL nlOO0OOO : STD_LOGIC; + SIGNAL nlOO1iOl : STD_LOGIC; + SIGNAL nlOO1iOO : STD_LOGIC; + SIGNAL nlOO1l0i : STD_LOGIC; + SIGNAL nlOO1l0l : STD_LOGIC; + SIGNAL nlOO1l0O : STD_LOGIC; + SIGNAL nlOO1l1i : STD_LOGIC; + SIGNAL nlOO1l1l : STD_LOGIC; + SIGNAL nlOO1l1O : STD_LOGIC; + SIGNAL nlOO1lii : STD_LOGIC; + SIGNAL nlOO1lil : STD_LOGIC; + SIGNAL nlOO1liO : STD_LOGIC; + SIGNAL nlOO1lli : STD_LOGIC; + SIGNAL nlOO1lll : STD_LOGIC; + SIGNAL nlOO1llO : STD_LOGIC; + SIGNAL nlOO1lOi : STD_LOGIC; + SIGNAL nlOO1lOl : STD_LOGIC; + SIGNAL nlOO1lOO : STD_LOGIC; + SIGNAL nlOO1O0i : STD_LOGIC; + SIGNAL nlOO1O0l : STD_LOGIC; + SIGNAL nlOO1O0O : STD_LOGIC; + SIGNAL nlOO1O1i : STD_LOGIC; + SIGNAL nlOO1O1l : STD_LOGIC; + SIGNAL nlOO1O1O : STD_LOGIC; + SIGNAL nlOO1Oii : STD_LOGIC; + SIGNAL nlOO1Oil : STD_LOGIC; + SIGNAL nlOO1OiO : STD_LOGIC; + SIGNAL nlOO1Oli : STD_LOGIC; + SIGNAL nlOO1Oll : STD_LOGIC; + SIGNAL nlOO1OlO : STD_LOGIC; + SIGNAL nlOO1OOi : STD_LOGIC; + SIGNAL nlOO1OOl : STD_LOGIC; + SIGNAL nlOO1OOO : STD_LOGIC; + SIGNAL nlOOi00i : STD_LOGIC; + SIGNAL nlOOi00l : STD_LOGIC; + SIGNAL nlOOi00O : STD_LOGIC; + SIGNAL nlOOi01i : STD_LOGIC; + SIGNAL nlOOi01l : STD_LOGIC; + SIGNAL nlOOi01O : STD_LOGIC; + SIGNAL nlOOi0ii : STD_LOGIC; + SIGNAL nlOOi0il : STD_LOGIC; + SIGNAL nlOOi0iO : STD_LOGIC; + SIGNAL nlOOi0li : STD_LOGIC; + SIGNAL nlOOi0ll : STD_LOGIC; + SIGNAL nlOOi0lO : STD_LOGIC; + SIGNAL nlOOi0Oi : STD_LOGIC; + SIGNAL nlOOi0Ol : STD_LOGIC; + SIGNAL nlOOi0OO : STD_LOGIC; + SIGNAL nlOOi10i : STD_LOGIC; + SIGNAL nlOOi10l : STD_LOGIC; + SIGNAL nlOOi10O : STD_LOGIC; + SIGNAL nlOOi11i : STD_LOGIC; + SIGNAL nlOOi11l : STD_LOGIC; + SIGNAL nlOOi11O : STD_LOGIC; + SIGNAL nlOOi1ii : STD_LOGIC; + SIGNAL nlOOi1il : STD_LOGIC; + SIGNAL nlOOi1iO : STD_LOGIC; + SIGNAL nlOOi1li : STD_LOGIC; + SIGNAL nlOOi1ll : STD_LOGIC; + SIGNAL nlOOi1lO : STD_LOGIC; + SIGNAL nlOOi1Oi : STD_LOGIC; + SIGNAL nlOOi1Ol : STD_LOGIC; + SIGNAL nlOOi1OO : STD_LOGIC; + SIGNAL nlOOii0i : STD_LOGIC; + SIGNAL nlOOii0l : STD_LOGIC; + SIGNAL nlOOii0O : STD_LOGIC; + SIGNAL nlOOii1i : STD_LOGIC; + SIGNAL nlOOii1l : STD_LOGIC; + SIGNAL nlOOii1O : STD_LOGIC; + SIGNAL nlOOiiii : STD_LOGIC; + SIGNAL nlOOiiil : STD_LOGIC; + SIGNAL nlOOiiiO : STD_LOGIC; + SIGNAL nlOOiili : STD_LOGIC; + SIGNAL nlOOiill : STD_LOGIC; + SIGNAL nlOOiilO : STD_LOGIC; + SIGNAL nlOOiiOi : STD_LOGIC; + SIGNAL nlOOiiOl : STD_LOGIC; + SIGNAL nlOOiiOO : STD_LOGIC; + SIGNAL nlOOil0i : STD_LOGIC; + SIGNAL nlOOil0l : STD_LOGIC; + SIGNAL nlOOil0O : STD_LOGIC; + SIGNAL nlOOil1i : STD_LOGIC; + SIGNAL nlOOil1l : STD_LOGIC; + SIGNAL nlOOil1O : STD_LOGIC; + SIGNAL nlOOilii : STD_LOGIC; + SIGNAL nlOOilil : STD_LOGIC; + SIGNAL nlOOiliO : STD_LOGIC; + SIGNAL nlOOilli : STD_LOGIC; + SIGNAL nlOOilll : STD_LOGIC; + SIGNAL nlOOillO : STD_LOGIC; + SIGNAL nlOOilOi : STD_LOGIC; + SIGNAL nlOOilOl : STD_LOGIC; + SIGNAL nlOOilOO : STD_LOGIC; + SIGNAL nlOOiO0i : STD_LOGIC; + SIGNAL nlOOiO0l : STD_LOGIC; + SIGNAL nlOOiO0O : STD_LOGIC; + SIGNAL nlOOiO1i : STD_LOGIC; + SIGNAL nlOOiO1l : STD_LOGIC; + SIGNAL nlOOiO1O : STD_LOGIC; + SIGNAL nlOOiOii : STD_LOGIC; + SIGNAL nlOOiOil : STD_LOGIC; + SIGNAL nlOOiOiO : STD_LOGIC; + SIGNAL nlOOiOli : STD_LOGIC; + SIGNAL nlOOiOll : STD_LOGIC; + SIGNAL nlOOiOlO : STD_LOGIC; + SIGNAL nlOOiOOi : STD_LOGIC; + SIGNAL nlOOiOOl : STD_LOGIC; + SIGNAL nlOOiOOO : STD_LOGIC; + SIGNAL nlOOl00i : STD_LOGIC; + SIGNAL nlOOl00l : STD_LOGIC; + SIGNAL nlOOl00O : STD_LOGIC; + SIGNAL nlOOl01i : STD_LOGIC; + SIGNAL nlOOl01l : STD_LOGIC; + SIGNAL nlOOl01O : STD_LOGIC; + SIGNAL nlOOl0ii : STD_LOGIC; + SIGNAL nlOOl0il : STD_LOGIC; + SIGNAL nlOOl0iO : STD_LOGIC; + SIGNAL nlOOl0li : STD_LOGIC; + SIGNAL nlOOl0ll : STD_LOGIC; + SIGNAL nlOOl0lO : STD_LOGIC; + SIGNAL nlOOl0Oi : STD_LOGIC; + SIGNAL nlOOl0Ol : STD_LOGIC; + SIGNAL nlOOl0OO : STD_LOGIC; + SIGNAL nlOOl10i : STD_LOGIC; + SIGNAL nlOOl10l : STD_LOGIC; + SIGNAL nlOOl10O : STD_LOGIC; + SIGNAL nlOOl11i : STD_LOGIC; + SIGNAL nlOOl11l : STD_LOGIC; + SIGNAL nlOOl11O : STD_LOGIC; + SIGNAL nlOOl1ii : STD_LOGIC; + SIGNAL nlOOl1il : STD_LOGIC; + SIGNAL nlOOl1iO : STD_LOGIC; + SIGNAL nlOOl1li : STD_LOGIC; + SIGNAL nlOOl1ll : STD_LOGIC; + SIGNAL nlOOl1lO : STD_LOGIC; + SIGNAL nlOOl1Oi : STD_LOGIC; + SIGNAL nlOOl1Ol : STD_LOGIC; + SIGNAL nlOOl1OO : STD_LOGIC; + SIGNAL nlOOli0i : STD_LOGIC; + SIGNAL nlOOli0l : STD_LOGIC; + SIGNAL nlOOli0O : STD_LOGIC; + SIGNAL nlOOli1i : STD_LOGIC; + SIGNAL nlOOli1l : STD_LOGIC; + SIGNAL nlOOli1O : STD_LOGIC; + SIGNAL nlOOliii : STD_LOGIC; + SIGNAL nlOOliil : STD_LOGIC; + SIGNAL nlOOliiO : STD_LOGIC; + SIGNAL nlOOlili : STD_LOGIC; + SIGNAL nlOOlill : STD_LOGIC; + SIGNAL nlOOlilO : STD_LOGIC; + SIGNAL nlOOliOi : STD_LOGIC; + SIGNAL nlOOliOl : STD_LOGIC; + SIGNAL nlOOliOO : STD_LOGIC; + SIGNAL nlOOll0i : STD_LOGIC; + SIGNAL nlOOll0l : STD_LOGIC; + SIGNAL nlOOll0O : STD_LOGIC; + SIGNAL nlOOll1i : STD_LOGIC; + SIGNAL nlOOll1l : STD_LOGIC; + SIGNAL nlOOll1O : STD_LOGIC; + SIGNAL nlOOllii : STD_LOGIC; + SIGNAL nlOOllil : STD_LOGIC; + SIGNAL nlOOlliO : STD_LOGIC; + SIGNAL nlOOllli : STD_LOGIC; + SIGNAL nlOOllll : STD_LOGIC; + SIGNAL nlOOlllO : STD_LOGIC; + SIGNAL nlOOllOi : STD_LOGIC; + SIGNAL nlOOllOl : STD_LOGIC; + SIGNAL nlOOllOO : STD_LOGIC; + SIGNAL nlOOlO0i : STD_LOGIC; + SIGNAL nlOOlO0l : STD_LOGIC; + SIGNAL nlOOlO0O : STD_LOGIC; + SIGNAL nlOOlO1i : STD_LOGIC; + SIGNAL nlOOlO1l : STD_LOGIC; + SIGNAL nlOOlO1O : STD_LOGIC; + SIGNAL nlOOlOii : STD_LOGIC; + SIGNAL nlOOlOil : STD_LOGIC; + SIGNAL nlOOlOiO : STD_LOGIC; + SIGNAL nlOOlOli : STD_LOGIC; + SIGNAL nlOOlOll : STD_LOGIC; + SIGNAL nlOOlOlO : STD_LOGIC; + SIGNAL nlOOlOOi : STD_LOGIC; + SIGNAL nlOOlOOl : STD_LOGIC; + SIGNAL nlOOlOOO : STD_LOGIC; + SIGNAL nlOOO00i : STD_LOGIC; + SIGNAL nlOOO00l : STD_LOGIC; + SIGNAL nlOOO00O : STD_LOGIC; + SIGNAL nlOOO01i : STD_LOGIC; + SIGNAL nlOOO01l : STD_LOGIC; + SIGNAL nlOOO01O : STD_LOGIC; + SIGNAL nlOOO0ii : STD_LOGIC; + SIGNAL nlOOO0il : STD_LOGIC; + SIGNAL nlOOO0iO : STD_LOGIC; + SIGNAL nlOOO0li : STD_LOGIC; + SIGNAL nlOOO0ll : STD_LOGIC; + SIGNAL nlOOO0lO : STD_LOGIC; + SIGNAL nlOOO0Oi : STD_LOGIC; + SIGNAL nlOOO0Ol : STD_LOGIC; + SIGNAL nlOOO0OO : STD_LOGIC; + SIGNAL nlOOO10i : STD_LOGIC; + SIGNAL nlOOO10l : STD_LOGIC; + SIGNAL nlOOO10O : STD_LOGIC; + SIGNAL nlOOO11i : STD_LOGIC; + SIGNAL nlOOO11l : STD_LOGIC; + SIGNAL nlOOO11O : STD_LOGIC; + SIGNAL nlOOO1ii : STD_LOGIC; + SIGNAL nlOOO1il : STD_LOGIC; + SIGNAL nlOOO1iO : STD_LOGIC; + SIGNAL nlOOO1li : STD_LOGIC; + SIGNAL nlOOO1ll : STD_LOGIC; + SIGNAL nlOOO1lO : STD_LOGIC; + SIGNAL nlOOO1Oi : STD_LOGIC; + SIGNAL nlOOO1Ol : STD_LOGIC; + SIGNAL nlOOO1OO : STD_LOGIC; + SIGNAL nlOOOi0i : STD_LOGIC; + SIGNAL nlOOOi0l : STD_LOGIC; + SIGNAL nlOOOi0O : STD_LOGIC; + SIGNAL nlOOOi1i : STD_LOGIC; + SIGNAL nlOOOi1l : STD_LOGIC; + SIGNAL nlOOOi1O : STD_LOGIC; + SIGNAL nlOOOiii : STD_LOGIC; + SIGNAL nlOOOiil : STD_LOGIC; + SIGNAL nlOOOiiO : STD_LOGIC; + SIGNAL nlOOOili : STD_LOGIC; + SIGNAL nlOOOill : STD_LOGIC; + SIGNAL nlOOOilO : STD_LOGIC; + SIGNAL nlOOOiOi : STD_LOGIC; + SIGNAL nlOOOiOl : STD_LOGIC; + SIGNAL nlOOOiOO : STD_LOGIC; + SIGNAL nlOOOl0i : STD_LOGIC; + SIGNAL nlOOOl0l : STD_LOGIC; + SIGNAL nlOOOl0O : STD_LOGIC; + SIGNAL nlOOOl1i : STD_LOGIC; + SIGNAL nlOOOl1l : STD_LOGIC; + SIGNAL nlOOOl1O : STD_LOGIC; + SIGNAL nlOOOlii : STD_LOGIC; + SIGNAL nlOOOlil : STD_LOGIC; + SIGNAL nlOOOliO : STD_LOGIC; + SIGNAL nlOOOlli : STD_LOGIC; + SIGNAL nlOOOlll : STD_LOGIC; + SIGNAL nlOOOllO : STD_LOGIC; + SIGNAL nlOOOlOi : STD_LOGIC; + SIGNAL nlOOOlOl : STD_LOGIC; + SIGNAL nlOOOlOO : STD_LOGIC; + SIGNAL nlOOOO0i : STD_LOGIC; + SIGNAL nlOOOO0l : STD_LOGIC; + SIGNAL nlOOOO0O : STD_LOGIC; + SIGNAL nlOOOO1i : STD_LOGIC; + SIGNAL nlOOOO1l : STD_LOGIC; + SIGNAL nlOOOO1O : STD_LOGIC; + SIGNAL nlOOOOii : STD_LOGIC; + SIGNAL nlOOOOil : STD_LOGIC; + SIGNAL nlOOOOiO : STD_LOGIC; + SIGNAL nlOOOOli : STD_LOGIC; + SIGNAL nlOOOOll : STD_LOGIC; + SIGNAL nlOOOOlO : STD_LOGIC; + SIGNAL nlOOOOOi : STD_LOGIC; + SIGNAL nlOOOOOl : STD_LOGIC; + SIGNAL nlOOOOOO : STD_LOGIC; + SIGNAL wire_w_comp_pat_size_range1330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_comp_pat_size_range1331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_ib_invalid_code_range3169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_ib_invalid_code_range3176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pmadwidth_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_r8b10b_dec_ibm_en_range3034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_resync_badcg_en_range4511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_resync_badcg_en_range4513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_vcc <= '1'; + wire_w_lg_w_lg_w_lg_rauto_speed_ena5w8w9w(0) <= wire_w_lg_w_lg_rauto_speed_ena5w8w(0) AND ni0OO; + wire_w_lg_w_lg_n1i0O0O338w341w(0) <= wire_w_lg_n1i0O0O338w(0) AND wire_n1i0O0i44_w_lg_q340w(0); + wire_w_lg_w_lg_n1ii01O227w228w(0) <= wire_w_lg_n1ii01O227w(0) AND n1ii01i; + wire_w_lg_w_lg_n1ii11O1325w1327w(0) <= wire_w_lg_n1ii11O1325w(0) AND wire_w_lg_n1i1O0O1326w(0); + wire_w_lg_w_lg_rauto_speed_ena5w8w(0) <= wire_w_lg_rauto_speed_ena5w(0) AND wire_n1iil1i4_w_lg_q7w(0); + wire_w_lg_w_lg_n10liOl3443w3446w(0) <= wire_w_lg_n10liOl3443w(0) AND niii0l; + wire_w_lg_w_lg_n10ll1O3434w3435w(0) <= wire_w_lg_n10ll1O3434w(0) AND niii0l; + wire_w_lg_w_lg_rkchar3383w3384w(0) <= wire_w_lg_rkchar3383w(0) AND niii0l; + wire_w_lg_w_lg_w_pmadwidth_range175w219w2208w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND n1i100O; + wire_w_lg_w_lg_w_pmadwidth_range175w219w2203w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND n1i10iO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w2198w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND n1i10lO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w2193w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND n1i10OO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14500w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOO0iO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14495w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOO0lO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14490w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOO0OO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14480w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOi0O; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14485w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOi1O; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14475w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOiiO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14470w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOilO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14465w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOiOO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14455w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOl0O; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14460w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOl1O; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14450w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOliO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w14445w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) AND nlOOOllO; + wire_w_lg_w_lg_n1i01lO1217w1218w(0) <= wire_w_lg_n1i01lO1217w(0) AND wire_nlOll0O_dataout; + wire_w_lg_w_lg_n1i1Oil1323w1324w(0) <= wire_w_lg_n1i1Oil1323w(0) AND n1i1OOi; + wire_w_lg_w_lg_nlOO0iOl16779w16780w(0) <= wire_w_lg_nlOO0iOl16779w(0) AND wire_n1lllii_dataout; + wire_w_lg_w_lg_nlOO1O0l17123w17124w(0) <= wire_w_lg_nlOO1O0l17123w(0) AND wire_n1iliii_dataout; + wire_w_lg_comp_pat_porn4782w(0) <= comp_pat_porn AND n10100l; + wire_w_lg_comp_pat_porn4786w(0) <= comp_pat_porn AND n10101l; + wire_w_lg_comp_pat_porn4780w(0) <= comp_pat_porn AND n1010ii; + wire_w_lg_comp_pat_porn4776w(0) <= comp_pat_porn AND n1010li; + wire_w_lg_comp_pat_porn4774w(0) <= comp_pat_porn AND n1010lO; + wire_w_lg_comp_pat_porn4770w(0) <= comp_pat_porn AND n1010OO; + wire_w_lg_comp_pat_porn4800w(0) <= comp_pat_porn AND n10110l; + wire_w_lg_comp_pat_porn4804w(0) <= comp_pat_porn AND n10111l; + wire_w_lg_comp_pat_porn4798w(0) <= comp_pat_porn AND n1011ii; + wire_w_lg_comp_pat_porn4794w(0) <= comp_pat_porn AND n1011li; + wire_w_lg_comp_pat_porn4792w(0) <= comp_pat_porn AND n1011lO; + wire_w_lg_comp_pat_porn4788w(0) <= comp_pat_porn AND n1011OO; + wire_w_lg_comp_pat_porn4764w(0) <= comp_pat_porn AND n101i0l; + wire_w_lg_comp_pat_porn4768w(0) <= comp_pat_porn AND n101i1l; + wire_w_lg_comp_pat_porn4762w(0) <= comp_pat_porn AND n101iii; + wire_w_lg_comp_pat_porn4758w(0) <= comp_pat_porn AND n101ili; + wire_w_lg_comp_pat_porn4756w(0) <= comp_pat_porn AND n101ilO; + wire_w_lg_comp_pat_porn5097w(0) <= comp_pat_porn AND n110O0O; + wire_w_lg_comp_pat_porn5095w(0) <= comp_pat_porn AND n110Oil; + wire_w_lg_comp_pat_porn5091w(0) <= comp_pat_porn AND n110Oll; + wire_w_lg_comp_pat_porn5089w(0) <= comp_pat_porn AND n110OOi; + wire_w_lg_comp_pat_porn5757w(0) <= comp_pat_porn AND n111Oil; + wire_w_lg_comp_pat_porn5743w(0) <= comp_pat_porn AND n111Oll; + wire_w_lg_comp_pat_porn5738w(0) <= comp_pat_porn AND n111OOl; + wire_w_lg_comp_pat_porn5061w(0) <= comp_pat_porn AND n11i00O; + wire_w_lg_comp_pat_porn5067w(0) <= comp_pat_porn AND n11i01i; + wire_w_lg_comp_pat_porn5065w(0) <= comp_pat_porn AND n11i01O; + wire_w_lg_comp_pat_porn5059w(0) <= comp_pat_porn AND n11i0il; + wire_w_lg_comp_pat_porn5055w(0) <= comp_pat_porn AND n11i0ll; + wire_w_lg_comp_pat_porn5053w(0) <= comp_pat_porn AND n11i0Oi; + wire_w_lg_comp_pat_porn5079w(0) <= comp_pat_porn AND n11i10O; + wire_w_lg_comp_pat_porn5085w(0) <= comp_pat_porn AND n11i11i; + wire_w_lg_comp_pat_porn5083w(0) <= comp_pat_porn AND n11i11O; + wire_w_lg_comp_pat_porn5077w(0) <= comp_pat_porn AND n11i1il; + wire_w_lg_comp_pat_porn5073w(0) <= comp_pat_porn AND n11i1ll; + wire_w_lg_comp_pat_porn5071w(0) <= comp_pat_porn AND n11i1Oi; + wire_w_lg_comp_pat_porn5043w(0) <= comp_pat_porn AND n11ii0O; + wire_w_lg_comp_pat_porn5049w(0) <= comp_pat_porn AND n11ii1i; + wire_w_lg_comp_pat_porn5047w(0) <= comp_pat_porn AND n11ii1O; + wire_w_lg_comp_pat_porn5041w(0) <= comp_pat_porn AND n11iiil; + wire_w_lg_comp_pat_porn5037w(0) <= comp_pat_porn AND n11iill; + wire_w_lg_comp_pat_porn5035w(0) <= comp_pat_porn AND n11iiOi; + wire_w_lg_comp_pat_porn5025w(0) <= comp_pat_porn AND n11il0O; + wire_w_lg_comp_pat_porn5031w(0) <= comp_pat_porn AND n11il1i; + wire_w_lg_comp_pat_porn5029w(0) <= comp_pat_porn AND n11il1O; + wire_w_lg_comp_pat_porn5023w(0) <= comp_pat_porn AND n11ilil; + wire_w_lg_comp_pat_porn5019w(0) <= comp_pat_porn AND n11illl; + wire_w_lg_comp_pat_porn5017w(0) <= comp_pat_porn AND n11ilOi; + wire_w_lg_comp_pat_porn5007w(0) <= comp_pat_porn AND n11iO0O; + wire_w_lg_comp_pat_porn5013w(0) <= comp_pat_porn AND n11iO1i; + wire_w_lg_comp_pat_porn5011w(0) <= comp_pat_porn AND n11iO1O; + wire_w_lg_comp_pat_porn5005w(0) <= comp_pat_porn AND n11iOil; + wire_w_lg_comp_pat_porn4872w(0) <= comp_pat_porn AND n11O00l; + wire_w_lg_comp_pat_porn4870w(0) <= comp_pat_porn AND n11O0ii; + wire_w_lg_comp_pat_porn4866w(0) <= comp_pat_porn AND n11O0li; + wire_w_lg_comp_pat_porn4864w(0) <= comp_pat_porn AND n11O0lO; + wire_w_lg_comp_pat_porn4860w(0) <= comp_pat_porn AND n11O0OO; + wire_w_lg_comp_pat_porn4854w(0) <= comp_pat_porn AND n11Oi0l; + wire_w_lg_comp_pat_porn4858w(0) <= comp_pat_porn AND n11Oi1l; + wire_w_lg_comp_pat_porn4852w(0) <= comp_pat_porn AND n11Oiii; + wire_w_lg_comp_pat_porn4848w(0) <= comp_pat_porn AND n11Oili; + wire_w_lg_comp_pat_porn4846w(0) <= comp_pat_porn AND n11OilO; + wire_w_lg_comp_pat_porn4842w(0) <= comp_pat_porn AND n11OiOO; + wire_w_lg_comp_pat_porn4836w(0) <= comp_pat_porn AND n11Ol0l; + wire_w_lg_comp_pat_porn4840w(0) <= comp_pat_porn AND n11Ol1l; + wire_w_lg_comp_pat_porn4834w(0) <= comp_pat_porn AND n11Olii; + wire_w_lg_comp_pat_porn4830w(0) <= comp_pat_porn AND n11Olli; + wire_w_lg_comp_pat_porn4828w(0) <= comp_pat_porn AND n11OllO; + wire_w_lg_comp_pat_porn4824w(0) <= comp_pat_porn AND n11OlOO; + wire_w_lg_comp_pat_porn4818w(0) <= comp_pat_porn AND n11OO0l; + wire_w_lg_comp_pat_porn4822w(0) <= comp_pat_porn AND n11OO1l; + wire_w_lg_comp_pat_porn4816w(0) <= comp_pat_porn AND n11OOii; + wire_w_lg_comp_pat_porn4812w(0) <= comp_pat_porn AND n11OOli; + wire_w_lg_comp_pat_porn4810w(0) <= comp_pat_porn AND n11OOlO; + wire_w_lg_comp_pat_porn4806w(0) <= comp_pat_porn AND n11OOOO; + wire_w_lg_n10l1ii4519w(0) <= n10l1ii AND wire_w_lg_w_resync_badcg_en_range4511w4518w(0); + wire_w_lg_n10O10i3044w(0) <= n10O10i AND n10O11l; + wire_w_lg_n10O10l3062w(0) <= n10O10l AND wire_niOl0l_w_lg_dataout3061w(0); + wire_w_lg_n10O10O3020w(0) <= n10O10O AND wire_niOl0i_w_lg_w_lg_dataout3017w3019w(0); + wire_w_lg_n10O11l3047w(0) <= n10O11l AND wire_niOl1O_w_lg_w_lg_o1314w3046w(0); + wire_w_lg_n1i000O1200w(0) <= n1i000O AND n1i000l; + wire_w_lg_n1i00il3236w(0) <= n1i00il AND n10llOl; + wire_w_lg_n1i00il1198w(0) <= n1i00il AND n1i00ii; + wire_w_lg_n1i0l0l388w(0) <= n1i0l0l AND wire_nl_w_lg_nlOi0Ol387w(0); + wire_w_lg_n1i0l1O396w(0) <= n1i0l1O AND wire_nl_w_lg_nlOi0lO395w(0); + wire_w_lg_n1i0lii380w(0) <= n1i0lii AND wire_nl_w_lg_nlOii1i379w(0); + wire_w_lg_n1i0liO372w(0) <= n1i0liO AND wire_nl_w_lg_nlOii1O371w(0); + wire_w_lg_n1i0lll364w(0) <= n1i0lll AND wire_nl_w_lg_nlOii0l363w(0); + wire_w_lg_n1i0lOO356w(0) <= n1i0lOO AND wire_nl_w_lg_nlOiiii355w(0); + wire_w_lg_n1i0O0O338w(0) <= n1i0O0O AND wire_nl_w_lg_nlOiiiO337w(0); + wire_w_lg_n1i1Oll3180w(0) <= n1i1Oll AND n1i01ll; + wire_w_lg_n1i1OlO3177w(0) <= n1i1OlO AND n1i01ll; + wire_w_lg_n1ii01O227w(0) <= n1ii01O AND n1ii01l; + wire_w_lg_n1ii11i326w(0) <= n1ii11i AND wire_nl_w_lg_w_lg_nlOiill322w325w(0); + wire_w_lg_n1ii11O1325w(0) <= n1ii11O AND wire_n1l1Ol_dataout; + wire_w_lg_nlOO011i17049w(0) <= nlOO011i AND nlOO1O0i; + wire_w_lg_nlOO01ll16920w(0) <= nlOO01ll AND wire_nl1ll1i_w_lg_w_lg_o16855w16919w(0); + wire_w_lg_nlOO01Oi16917w(0) <= nlOO01Oi AND nlOO01ll; + wire_w_lg_nlOO01Ol16935w(0) <= nlOO01Ol AND wire_nl1ll1O_w_lg_o16934w(0); + wire_w_lg_nlOO01OO16893w(0) <= nlOO01OO AND wire_nl1ll1l_w_lg_w_lg_o16890w16892w(0); + wire_w_lg_nlOO0i0O16788w(0) <= nlOO0i0O AND nlOO00Ol; + wire_w_lg_nlOO0i0O16761w(0) <= nlOO0i0O AND nlOO0i0l; + wire_w_lg_nlOO0lil16763w(0) <= nlOO0lil AND nlOO0i0i; + wire_w_lg_nlOO0liO16708w(0) <= nlOO0liO AND nlOO0iOi; + wire_w_lg_nlOO0lli16705w(0) <= nlOO0lli AND nlOO0iOi; + wire_w_lg_nlOO0O0l16576w(0) <= nlOO0O0l AND wire_nl1llll_w_lg_w_lg_o16511w16575w(0); + wire_w_lg_nlOO0Oii16573w(0) <= nlOO0Oii AND nlOO0O0l; + wire_w_lg_nlOO0Oil16591w(0) <= nlOO0Oil AND wire_nl1llOi_w_lg_o16590w(0); + wire_w_lg_nlOO0OiO16549w(0) <= nlOO0OiO AND wire_nl1lllO_w_lg_w_lg_o16546w16548w(0); + wire_w_lg_nlOO1llO17132w(0) <= nlOO1llO AND nlOO1l0l; + wire_w_lg_nlOO1llO17105w(0) <= nlOO1llO AND nlOO1lll; + wire_w_lg_nlOO1OOl17107w(0) <= nlOO1OOl AND nlOO1lli; + wire_w_lg_nlOO1OOO17052w(0) <= nlOO1OOO AND nlOO1O0i; + wire_w_lg_rauto_speed_ena5w(0) <= rauto_speed_ena AND wire_w_lg_rfreq_sel4w(0); + wire_w_lg_rencdt_rising4509w(0) <= rencdt_rising AND nlli0Ol; + wire_w_lg_wa_6g_en4496w(0) <= wa_6g_en AND wire_w_lg_lpbk_en4495w(0); + wire_w_lg_w_comp_pat_size_range1330w1333w(0) <= wire_w_comp_pat_size_range1330w(0) AND wire_w_lg_w_comp_pat_size_range1331w1332w(0); + wire_w_lg_w_ib_invalid_code_range3169w17048w(0) <= wire_w_ib_invalid_code_range3169w(0) AND wire_nl1ll1i_w_lg_w_lg_w_lg_w_lg_o16855w17043w17044w17047w(0); + wire_w_lg_w_ib_invalid_code_range3169w16704w(0) <= wire_w_ib_invalid_code_range3169w(0) AND wire_nl1llll_w_lg_w_lg_w_lg_w_lg_o16511w16699w16700w16703w(0); + wire_w_lg_w_ib_invalid_code_range3169w3175w(0) <= wire_w_ib_invalid_code_range3169w(0) AND wire_niOl1O_w_lg_w_lg_w_lg_w_lg_o1314w3170w3171w3174w(0); + wire_w_lg_w_ib_invalid_code_range3176w3184w(0) <= wire_w_ib_invalid_code_range3176w(0) AND wire_niOl0i_w_lg_w_lg_dataout3179w3183w(0); + wire_w_lg_w_ib_invalid_code_range3176w17056w(0) <= wire_w_ib_invalid_code_range3176w(0) AND wire_nl1ll1l_w_lg_w_lg_o17051w17055w(0); + wire_w_lg_w_ib_invalid_code_range3176w16712w(0) <= wire_w_ib_invalid_code_range3176w(0) AND wire_nl1lllO_w_lg_w_lg_o16707w16711w(0); + wire_w_lg_w_pmadwidth_range175w2186w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0); + wire_w_lg_w_pmadwidth_range175w14438w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0); + wire_w_lg_w_pmadwidth_range175w1328w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_w_lg_n1ii11O1325w1327w(0); + wire_w_lg_w_pmadwidth_range175w2181w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_nlilii2175w2180w(0); + wire_w_lg_w_pmadwidth_range175w14433w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_nlli01O14427w14432w(0); + wire_w_lg_w_pmadwidth_range175w2176w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_nlilii2175w(0); + wire_w_lg_w_pmadwidth_range175w14428w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_nlli01O14427w(0); + wire_w_lg_w_pmadwidth_range175w2103w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_w_lg_w_lg_nlilii2087w2094w2101w2102w(0); + wire_w_lg_w_pmadwidth_range175w14162w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w14161w(0); + wire_w_lg_w_pmadwidth_range175w2096w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2095w(0); + wire_w_lg_w_pmadwidth_range175w14155w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14154w(0); + wire_w_lg_w_pmadwidth_range175w2089w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_nlilii2087w2088w(0); + wire_w_lg_w_pmadwidth_range175w14148w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_w_lg_nlli01O14146w14147w(0); + wire_w_lg_w_pmadwidth_range175w14247w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n11100l14246w(0); + wire_w_lg_w_pmadwidth_range175w14253w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n11101l14252w(0); + wire_w_lg_w_pmadwidth_range175w14240w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1110il14239w(0); + wire_w_lg_w_pmadwidth_range175w14233w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1110ll14232w(0); + wire_w_lg_w_pmadwidth_range175w14226w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1110Ol14225w(0); + wire_w_lg_w_pmadwidth_range175w14262w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1111ll14261w(0); + wire_w_lg_w_pmadwidth_range175w14259w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1111Oi14258w(0); + wire_w_lg_w_pmadwidth_range175w14256w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1111OO14255w(0); + wire_w_lg_w_pmadwidth_range175w14212w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111i0l14211w(0); + wire_w_lg_w_pmadwidth_range175w14219w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111i1l14218w(0); + wire_w_lg_w_pmadwidth_range175w14205w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111iil14204w(0); + wire_w_lg_w_pmadwidth_range175w14198w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111ill14197w(0); + wire_w_lg_w_pmadwidth_range175w14191w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111iOl14190w(0); + wire_w_lg_w_pmadwidth_range175w14177w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111l0l14176w(0); + wire_w_lg_w_pmadwidth_range175w14184w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111l1l14183w(0); + wire_w_lg_w_pmadwidth_range175w14170w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n111lil14169w(0); + wire_w_lg_w_pmadwidth_range175w2172w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1i1iiO2171w(0); + wire_w_lg_w_pmadwidth_range175w2138w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1i1l0i2137w(0); + wire_w_lg_w_pmadwidth_range175w2141w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1i1l1l2140w(0); + wire_w_lg_w_pmadwidth_range175w2132w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1i1lii2131w(0); + wire_w_lg_w_pmadwidth_range175w2125w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1i1lli2124w(0); + wire_w_lg_w_pmadwidth_range175w2118w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1i1lOi2117w(0); + wire_w_lg_w_pmadwidth_range175w2111w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_n1i1O1i2110w(0); + wire_w_lg_w_pmadwidth_range175w2912w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_nlilii2911w(0); + wire_w_lg_w_pmadwidth_range175w16385w(0) <= wire_w_pmadwidth_range175w(0) AND wire_nl_w_lg_nlli01O16384w(0); + wire_w_lg_w_pmadwidth_range175w14424w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_nlOOOO0O14423w(0); + wire_w_lg_w_pmadwidth_range175w14404w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_nlOOOOil14403w(0); + wire_w_lg_w_pmadwidth_range175w14385w(0) <= wire_w_pmadwidth_range175w(0) AND wire_w_lg_nlOOOOli14384w(0); + wire_w_lg_w_pmadwidth_range175w2207w(0) <= wire_w_pmadwidth_range175w(0) AND n1i10ii; + wire_w_lg_w_pmadwidth_range175w2202w(0) <= wire_w_pmadwidth_range175w(0) AND n1i10li; + wire_w_lg_w_pmadwidth_range175w2197w(0) <= wire_w_pmadwidth_range175w(0) AND n1i10Oi; + wire_w_lg_w_pmadwidth_range175w2517w(0) <= wire_w_pmadwidth_range175w(0) AND n1i11ii; + wire_w_lg_w_pmadwidth_range175w2192w(0) <= wire_w_pmadwidth_range175w(0) AND n1i1i1i; + wire_w_lg_w_pmadwidth_range175w2482w(0) <= wire_w_pmadwidth_range175w(0) AND n1i1iii; + wire_w_lg_w_pmadwidth_range175w176w(0) <= wire_w_pmadwidth_range175w(0) AND n1ii0Ol; + wire_w_lg_w_pmadwidth_range175w15676w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOlOiO; + wire_w_lg_w_pmadwidth_range175w14499w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOO0li; + wire_w_lg_w_pmadwidth_range175w14494w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOO0Oi; + wire_w_lg_w_pmadwidth_range175w14484w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOi0i; + wire_w_lg_w_pmadwidth_range175w14489w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOi1i; + wire_w_lg_w_pmadwidth_range175w14479w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOiii; + wire_w_lg_w_pmadwidth_range175w14474w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOili; + wire_w_lg_w_pmadwidth_range175w14469w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOiOi; + wire_w_lg_w_pmadwidth_range175w14459w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOl0i; + wire_w_lg_w_pmadwidth_range175w14464w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOl1i; + wire_w_lg_w_pmadwidth_range175w14454w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOlii; + wire_w_lg_w_pmadwidth_range175w14449w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOlli; + wire_w_lg_w_pmadwidth_range175w14444w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOlOi; + wire_w_lg_w_pmadwidth_range175w15643w(0) <= wire_w_pmadwidth_range175w(0) AND nlOOOO0i; + wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16923w(0) <= wire_w_r8b10b_dec_ibm_en_range3034w(0) AND wire_nl1liOl_w_lg_w16916w16922w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16579w(0) <= wire_w_r8b10b_dec_ibm_en_range3034w(0) AND wire_nl1lliO_w_lg_w16572w16578w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range3034w3050w(0) <= wire_w_r8b10b_dec_ibm_en_range3034w(0) AND wire_niOl1i_w_lg_w3043w3049w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16942w(0) <= wire_w_r8b10b_dec_ibm_en_range3034w(0) AND wire_nl1liOl_w16941w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16598w(0) <= wire_w_r8b10b_dec_ibm_en_range3034w(0) AND wire_nl1lliO_w16597w(0); + wire_w_lg_w_r8b10b_dec_ibm_en_range3034w3069w(0) <= wire_w_r8b10b_dec_ibm_en_range3034w(0) AND wire_niOl1i_w3068w(0); + wire_w_lg_w_resync_badcg_en_range4511w4518w(0) <= wire_w_resync_badcg_en_range4511w(0) AND wire_w_lg_w_resync_badcg_en_range4513w4514w(0); + wire_w_lg_autobytealign_dis5791w(0) <= NOT autobytealign_dis; + wire_w_lg_disable_rx_disp1194w(0) <= NOT disable_rx_disp; + wire_w_lg_lpbk_en4500w(0) <= NOT lpbk_en; + wire_w_lg_n10l00i3543w(0) <= NOT n10l00i; + wire_w_lg_n10l01l3948w(0) <= NOT n10l01l; + wire_w_lg_n10l01O3545w(0) <= NOT n10l01O; + wire_w_lg_n10l0OO3456w(0) <= NOT n10l0OO; + wire_w_lg_n10l10i4528w(0) <= NOT n10l10i; + wire_w_lg_n10l11i4530w(0) <= NOT n10l11i; + wire_w_lg_n10l1il4527w(0) <= NOT n10l1il; + wire_w_lg_n10l1li4548w(0) <= NOT n10l1li; + wire_w_lg_n10li0i3455w(0) <= NOT n10li0i; + wire_w_lg_n10li0O3453w(0) <= NOT n10li0O; + wire_w_lg_n10lili3500w(0) <= NOT n10lili; + wire_w_lg_n10lilO3445w(0) <= NOT n10lilO; + wire_w_lg_n10liOl3443w(0) <= NOT n10liOl; + wire_w_lg_n10ll0i3493w(0) <= NOT n10ll0i; + wire_w_lg_n10ll0l3386w(0) <= NOT n10ll0l; + wire_w_lg_n10ll0O3433w(0) <= NOT n10ll0O; + wire_w_lg_n10ll1l3437w(0) <= NOT n10ll1l; + wire_w_lg_n10ll1O3434w(0) <= NOT n10ll1O; + wire_w_lg_n10llii3439w(0) <= NOT n10llii; + wire_w_lg_n10lOlO3084w(0) <= NOT n10lOlO; + wire_w_lg_n10O00l2717w(0) <= NOT n10O00l; + wire_w_lg_n10O01l2767w(0) <= NOT n10O01l; + wire_w_lg_n10O01O2739w(0) <= NOT n10O01O; + wire_w_lg_n10O0il2712w(0) <= NOT n10O0il; + wire_w_lg_n10O0li2685w(0) <= NOT n10O0li; + wire_w_lg_n10O0Oi2526w(0) <= NOT n10O0Oi; + wire_w_lg_n10O0Ol2525w(0) <= NOT n10O0Ol; + wire_w_lg_n10O0OO2524w(0) <= NOT n10O0OO; + wire_w_lg_n10O10O3014w(0) <= NOT n10O10O; + wire_w_lg_n10O1iO3025w(0) <= NOT n10O1iO; + wire_w_lg_n10O1li3031w(0) <= NOT n10O1li; + wire_w_lg_n10O1Oi3072w(0) <= NOT n10O1Oi; + wire_w_lg_n10Oi0i2520w(0) <= NOT n10Oi0i; + wire_w_lg_n10Oi0l2490w(0) <= NOT n10Oi0l; + wire_w_lg_n10Oi0O2489w(0) <= NOT n10Oi0O; + wire_w_lg_n10Oi1i2523w(0) <= NOT n10Oi1i; + wire_w_lg_n10Oi1l2522w(0) <= NOT n10Oi1l; + wire_w_lg_n10Oi1O2521w(0) <= NOT n10Oi1O; + wire_w_lg_n10Oiii2488w(0) <= NOT n10Oiii; + wire_w_lg_n10Oiil2487w(0) <= NOT n10Oiil; + wire_w_lg_n10OiiO2486w(0) <= NOT n10OiiO; + wire_w_lg_n10Oili2485w(0) <= NOT n10Oili; + wire_w_lg_n10Oill2484w(0) <= NOT n10Oill; + wire_w_lg_n10OiOO2455w(0) <= NOT n10OiOO; + wire_w_lg_n10Ol0i2451w(0) <= NOT n10Ol0i; + wire_w_lg_n10Ol0l2449w(0) <= NOT n10Ol0l; + wire_w_lg_n10Ol0O2457w(0) <= NOT n10Ol0O; + wire_w_lg_n10Ol1i2453w(0) <= NOT n10Ol1i; + wire_w_lg_n10Ol1l2515w(0) <= NOT n10Ol1l; + wire_w_lg_n10Ol1O2459w(0) <= NOT n10Ol1O; + wire_w_lg_n10Olli2400w(0) <= NOT n10Olli; + wire_w_lg_n10Olll2398w(0) <= NOT n10Olll; + wire_w_lg_n10OllO2505w(0) <= NOT n10OllO; + wire_w_lg_n10OlOi2404w(0) <= NOT n10OlOi; + wire_w_lg_n10OlOl2396w(0) <= NOT n10OlOl; + wire_w_lg_n10OlOO2394w(0) <= NOT n10OlOO; + wire_w_lg_n10OO0l2345w(0) <= NOT n10OO0l; + wire_w_lg_n10OO0O2343w(0) <= NOT n10OO0O; + wire_w_lg_n10OO1i2402w(0) <= NOT n10OO1i; + wire_w_lg_n10OOii2480w(0) <= NOT n10OOii; + wire_w_lg_n10OOil2349w(0) <= NOT n10OOil; + wire_w_lg_n10OOiO2341w(0) <= NOT n10OOiO; + wire_w_lg_n10OOli2339w(0) <= NOT n10OOli; + wire_w_lg_n10OOll2347w(0) <= NOT n10OOll; + wire_w_lg_n10OOOO2291w(0) <= NOT n10OOOO; + wire_w_lg_n110iiO5931w(0) <= NOT n110iiO; + wire_w_lg_n110ili5930w(0) <= NOT n110ili; + wire_w_lg_n110iOl5657w(0) <= NOT n110iOl; + wire_w_lg_n110l0i5646w(0) <= NOT n110l0i; + wire_w_lg_n110l0l5644w(0) <= NOT n110l0l; + wire_w_lg_n110l0O5642w(0) <= NOT n110l0O; + wire_w_lg_n110l1i5652w(0) <= NOT n110l1i; + wire_w_lg_n110l1l5650w(0) <= NOT n110l1l; + wire_w_lg_n110l1O5648w(0) <= NOT n110l1O; + wire_w_lg_n110lii5640w(0) <= NOT n110lii; + wire_w_lg_n110lil5638w(0) <= NOT n110lil; + wire_w_lg_n110liO5636w(0) <= NOT n110liO; + wire_w_lg_n110lli5634w(0) <= NOT n110lli; + wire_w_lg_n110lll5632w(0) <= NOT n110lll; + wire_w_lg_n110llO5630w(0) <= NOT n110llO; + wire_w_lg_n110lOi5628w(0) <= NOT n110lOi; + wire_w_lg_n110lOl5626w(0) <= NOT n110lOl; + wire_w_lg_n110lOO5624w(0) <= NOT n110lOO; + wire_w_lg_n110O1i5616w(0) <= NOT n110O1i; + wire_w_lg_n110O1l5614w(0) <= NOT n110O1l; + wire_w_lg_n11100i14248w(0) <= NOT n11100i; + wire_w_lg_n11100l14246w(0) <= NOT n11100l; + wire_w_lg_n11100O14683w(0) <= NOT n11100O; + wire_w_lg_n11101i14674w(0) <= NOT n11101i; + wire_w_lg_n11101l14252w(0) <= NOT n11101l; + wire_w_lg_n11101O14678w(0) <= NOT n11101O; + wire_w_lg_n1110ii14241w(0) <= NOT n1110ii; + wire_w_lg_n1110il14239w(0) <= NOT n1110il; + wire_w_lg_n1110iO14689w(0) <= NOT n1110iO; + wire_w_lg_n1110li14234w(0) <= NOT n1110li; + wire_w_lg_n1110ll14232w(0) <= NOT n1110ll; + wire_w_lg_n1110lO14696w(0) <= NOT n1110lO; + wire_w_lg_n1110Oi14227w(0) <= NOT n1110Oi; + wire_w_lg_n1110Ol14225w(0) <= NOT n1110Ol; + wire_w_lg_n1110OO14704w(0) <= NOT n1110OO; + wire_w_lg_n11110i15016w(0) <= NOT n11110i; + wire_w_lg_n11110l15031w(0) <= NOT n11110l; + wire_w_lg_n11110O15047w(0) <= NOT n11110O; + wire_w_lg_n11111i14977w(0) <= NOT n11111i; + wire_w_lg_n11111l14989w(0) <= NOT n11111l; + wire_w_lg_n11111O15002w(0) <= NOT n11111O; + wire_w_lg_n1111ii15064w(0) <= NOT n1111ii; + wire_w_lg_n1111il15082w(0) <= NOT n1111il; + wire_w_lg_n1111li16406w(0) <= NOT n1111li; + wire_w_lg_n1111ll14261w(0) <= NOT n1111ll; + wire_w_lg_n1111lO14669w(0) <= NOT n1111lO; + wire_w_lg_n1111Oi14258w(0) <= NOT n1111Oi; + wire_w_lg_n1111Ol14671w(0) <= NOT n1111Ol; + wire_w_lg_n1111OO14255w(0) <= NOT n1111OO; + wire_w_lg_n111i0i14213w(0) <= NOT n111i0i; + wire_w_lg_n111i0l14211w(0) <= NOT n111i0l; + wire_w_lg_n111i0O14723w(0) <= NOT n111i0O; + wire_w_lg_n111i1i14220w(0) <= NOT n111i1i; + wire_w_lg_n111i1l14218w(0) <= NOT n111i1l; + wire_w_lg_n111i1O14713w(0) <= NOT n111i1O; + wire_w_lg_n111iii14206w(0) <= NOT n111iii; + wire_w_lg_n111iil14204w(0) <= NOT n111iil; + wire_w_lg_n111iiO14734w(0) <= NOT n111iiO; + wire_w_lg_n111ili14199w(0) <= NOT n111ili; + wire_w_lg_n111ill14197w(0) <= NOT n111ill; + wire_w_lg_n111ilO14746w(0) <= NOT n111ilO; + wire_w_lg_n111iOi14192w(0) <= NOT n111iOi; + wire_w_lg_n111iOl14190w(0) <= NOT n111iOl; + wire_w_lg_n111iOO14759w(0) <= NOT n111iOO; + wire_w_lg_n111l0i14178w(0) <= NOT n111l0i; + wire_w_lg_n111l0l14176w(0) <= NOT n111l0l; + wire_w_lg_n111l0O14788w(0) <= NOT n111l0O; + wire_w_lg_n111l1i14185w(0) <= NOT n111l1i; + wire_w_lg_n111l1l14183w(0) <= NOT n111l1l; + wire_w_lg_n111l1O14773w(0) <= NOT n111l1O; + wire_w_lg_n111lii14171w(0) <= NOT n111lii; + wire_w_lg_n111lil14169w(0) <= NOT n111lil; + wire_w_lg_n111liO14804w(0) <= NOT n111liO; + wire_w_lg_n111lli14821w(0) <= NOT n111lli; + wire_w_lg_n111lll14839w(0) <= NOT n111lll; + wire_w_lg_n111lOi7419w(0) <= NOT n111lOi; + wire_w_lg_n111O1i7420w(0) <= NOT n111O1i; + wire_w_lg_n1i00lO1129w(0) <= NOT n1i00lO; + wire_w_lg_n1i01ii1295w(0) <= NOT n1i01ii; + wire_w_lg_n1i01il1227w(0) <= NOT n1i01il; + wire_w_lg_n1i0i0i462w(0) <= NOT n1i0i0i; + wire_w_lg_n1i0i0O459w(0) <= NOT n1i0i0O; + wire_w_lg_n1i0iii457w(0) <= NOT n1i0iii; + wire_w_lg_n1i0iil455w(0) <= NOT n1i0iil; + wire_w_lg_n1i0iiO453w(0) <= NOT n1i0iiO; + wire_w_lg_n1i0ili451w(0) <= NOT n1i0ili; + wire_w_lg_n1i0ill449w(0) <= NOT n1i0ill; + wire_w_lg_n1i0ilO447w(0) <= NOT n1i0ilO; + wire_w_lg_n1i0iOi445w(0) <= NOT n1i0iOi; + wire_w_lg_n1i100l2498w(0) <= NOT n1i100l; + wire_w_lg_n1i100O2508w(0) <= NOT n1i100O; + wire_w_lg_n1i101i2943w(0) <= NOT n1i101i; + wire_w_lg_n1i101O2353w(0) <= NOT n1i101O; + wire_w_lg_n1i10il2355w(0) <= NOT n1i10il; + wire_w_lg_n1i10ll2359w(0) <= NOT n1i10ll; + wire_w_lg_n1i10Ol2364w(0) <= NOT n1i10Ol; + wire_w_lg_n1i110i2287w(0) <= NOT n1i110i; + wire_w_lg_n1i110l2285w(0) <= NOT n1i110l; + wire_w_lg_n1i110O2293w(0) <= NOT n1i110O; + wire_w_lg_n1i111i2289w(0) <= NOT n1i111i; + wire_w_lg_n1i111l2471w(0) <= NOT n1i111l; + wire_w_lg_n1i111O2295w(0) <= NOT n1i111O; + wire_w_lg_n1i11ii2953w(0) <= NOT n1i11ii; + wire_w_lg_n1i11il2408w(0) <= NOT n1i11il; + wire_w_lg_n1i11li2410w(0) <= NOT n1i11li; + wire_w_lg_n1i11ll2414w(0) <= NOT n1i11ll; + wire_w_lg_n1i11lO2419w(0) <= NOT n1i11lO; + wire_w_lg_n1i11Oi2425w(0) <= NOT n1i11Oi; + wire_w_lg_n1i11Ol2432w(0) <= NOT n1i11Ol; + wire_w_lg_n1i11OO2440w(0) <= NOT n1i11OO; + wire_w_lg_n1i1i0i2385w(0) <= NOT n1i1i0i; + wire_w_lg_n1i1i1l2370w(0) <= NOT n1i1i1l; + wire_w_lg_n1i1i1O2377w(0) <= NOT n1i1i1O; + wire_w_lg_n1i1iii2933w(0) <= NOT n1i1iii; + wire_w_lg_n1i1iil2299w(0) <= NOT n1i1iil; + wire_w_lg_n1i1iiO2171w(0) <= NOT n1i1iiO; + wire_w_lg_n1i1ili2305w(0) <= NOT n1i1ili; + wire_w_lg_n1i1ill2310w(0) <= NOT n1i1ill; + wire_w_lg_n1i1ilO2316w(0) <= NOT n1i1ilO; + wire_w_lg_n1i1iOi2323w(0) <= NOT n1i1iOi; + wire_w_lg_n1i1iOl2331w(0) <= NOT n1i1iOl; + wire_w_lg_n1i1l0i2137w(0) <= NOT n1i1l0i; + wire_w_lg_n1i1l0l2464w(0) <= NOT n1i1l0l; + wire_w_lg_n1i1l0O2133w(0) <= NOT n1i1l0O; + wire_w_lg_n1i1l1i2923w(0) <= NOT n1i1l1i; + wire_w_lg_n1i1l1l2140w(0) <= NOT n1i1l1l; + wire_w_lg_n1i1l1O2244w(0) <= NOT n1i1l1O; + wire_w_lg_n1i1lii2131w(0) <= NOT n1i1lii; + wire_w_lg_n1i1lil2246w(0) <= NOT n1i1lil; + wire_w_lg_n1i1liO2126w(0) <= NOT n1i1liO; + wire_w_lg_n1i1lli2124w(0) <= NOT n1i1lli; + wire_w_lg_n1i1lll2250w(0) <= NOT n1i1lll; + wire_w_lg_n1i1llO2119w(0) <= NOT n1i1llO; + wire_w_lg_n1i1lOi2117w(0) <= NOT n1i1lOi; + wire_w_lg_n1i1lOl2255w(0) <= NOT n1i1lOl; + wire_w_lg_n1i1lOO2112w(0) <= NOT n1i1lOO; + wire_w_lg_n1i1O0i2276w(0) <= NOT n1i1O0i; + wire_w_lg_n1i1O1i2110w(0) <= NOT n1i1O1i; + wire_w_lg_n1i1O1l2261w(0) <= NOT n1i1O1l; + wire_w_lg_n1i1O1O2268w(0) <= NOT n1i1O1O; + wire_w_lg_n1ii00i237w(0) <= NOT n1ii00i; + wire_w_lg_n1ii00l231w(0) <= NOT n1ii00l; + wire_w_lg_n1ii1lO236w(0) <= NOT n1ii1lO; + wire_w_lg_n1ii1OO229w(0) <= NOT n1ii1OO; + wire_w_lg_nlOO000i16904w(0) <= NOT nlOO000i; + wire_w_lg_nlOO001O16898w(0) <= NOT nlOO001O; + wire_w_lg_nlOO00ii16945w(0) <= NOT nlOO00ii; + wire_w_lg_nlOO01OO16887w(0) <= NOT nlOO01OO; + wire_w_lg_nlOO0l0O16618w(0) <= NOT nlOO0l0O; + wire_w_lg_nlOO0OiO16543w(0) <= NOT nlOO0OiO; + wire_w_lg_nlOO0OlO16554w(0) <= NOT nlOO0OlO; + wire_w_lg_nlOO0OOi16560w(0) <= NOT nlOO0OOi; + wire_w_lg_nlOO1OlO16962w(0) <= NOT nlOO1OlO; + wire_w_lg_nlOOi00i15691w(0) <= NOT nlOOi00i; + wire_w_lg_nlOOi00l15690w(0) <= NOT nlOOi00l; + wire_w_lg_nlOOi00O15689w(0) <= NOT nlOOi00O; + wire_w_lg_nlOOi01i15694w(0) <= NOT nlOOi01i; + wire_w_lg_nlOOi01l15693w(0) <= NOT nlOOi01l; + wire_w_lg_nlOOi01O15692w(0) <= NOT nlOOi01O; + wire_w_lg_nlOOi0ii15688w(0) <= NOT nlOOi0ii; + wire_w_lg_nlOOi0il15687w(0) <= NOT nlOOi0il; + wire_w_lg_nlOOi0iO15686w(0) <= NOT nlOOi0iO; + wire_w_lg_nlOOi0li15685w(0) <= NOT nlOOi0li; + wire_w_lg_nlOOi0ll15684w(0) <= NOT nlOOi0ll; + wire_w_lg_nlOOi0lO15683w(0) <= NOT nlOOi0lO; + wire_w_lg_nlOOi0Oi15682w(0) <= NOT nlOOi0Oi; + wire_w_lg_nlOOi0Ol15681w(0) <= NOT nlOOi0Ol; + wire_w_lg_nlOOi0OO15680w(0) <= NOT nlOOi0OO; + wire_w_lg_nlOOi10l16209w(0) <= NOT nlOOi10l; + wire_w_lg_nlOOi10O16181w(0) <= NOT nlOOi10O; + wire_w_lg_nlOOi11i16601w(0) <= NOT nlOOi11i; + wire_w_lg_nlOOi1il16159w(0) <= NOT nlOOi1il; + wire_w_lg_nlOOi1ll16154w(0) <= NOT nlOOi1ll; + wire_w_lg_nlOOii0i15658w(0) <= NOT nlOOii0i; + wire_w_lg_nlOOii0l15657w(0) <= NOT nlOOii0l; + wire_w_lg_nlOOii0O15656w(0) <= NOT nlOOii0O; + wire_w_lg_nlOOii1i15679w(0) <= NOT nlOOii1i; + wire_w_lg_nlOOii1l15660w(0) <= NOT nlOOii1l; + wire_w_lg_nlOOii1O15659w(0) <= NOT nlOOii1O; + wire_w_lg_nlOOiiii15655w(0) <= NOT nlOOiiii; + wire_w_lg_nlOOiiil15654w(0) <= NOT nlOOiiil; + wire_w_lg_nlOOiiiO15653w(0) <= NOT nlOOiiiO; + wire_w_lg_nlOOiili15652w(0) <= NOT nlOOiili; + wire_w_lg_nlOOiill15651w(0) <= NOT nlOOiill; + wire_w_lg_nlOOiilO15650w(0) <= NOT nlOOiilO; + wire_w_lg_nlOOiiOi15649w(0) <= NOT nlOOiiOi; + wire_w_lg_nlOOiiOl15648w(0) <= NOT nlOOiiOl; + wire_w_lg_nlOOiiOO15647w(0) <= NOT nlOOiiOO; + wire_w_lg_nlOOil1i15646w(0) <= NOT nlOOil1i; + wire_w_lg_nlOOil1l15645w(0) <= NOT nlOOil1l; + wire_w_lg_nlOOiliO15632w(0) <= NOT nlOOiliO; + wire_w_lg_nlOOilli15630w(0) <= NOT nlOOilli; + wire_w_lg_nlOOilll15621w(0) <= NOT nlOOilll; + wire_w_lg_nlOOillO15619w(0) <= NOT nlOOillO; + wire_w_lg_nlOOilOi15617w(0) <= NOT nlOOilOi; + wire_w_lg_nlOOilOl15615w(0) <= NOT nlOOilOl; + wire_w_lg_nlOOilOO15609w(0) <= NOT nlOOilOO; + wire_w_lg_nlOOiO0i15601w(0) <= NOT nlOOiO0i; + wire_w_lg_nlOOiO0l15599w(0) <= NOT nlOOiO0l; + wire_w_lg_nlOOiO0O15597w(0) <= NOT nlOOiO0O; + wire_w_lg_nlOOiO1i15607w(0) <= NOT nlOOiO1i; + wire_w_lg_nlOOiO1l15605w(0) <= NOT nlOOiO1l; + wire_w_lg_nlOOiO1O15603w(0) <= NOT nlOOiO1O; + wire_w_lg_nlOOiOii15596w(0) <= NOT nlOOiOii; + wire_w_lg_nlOOiOil15594w(0) <= NOT nlOOiOil; + wire_w_lg_nlOOiOiO15592w(0) <= NOT nlOOiOiO; + wire_w_lg_nlOOiOli15590w(0) <= NOT nlOOiOli; + wire_w_lg_nlOOiOll15588w(0) <= NOT nlOOiOll; + wire_w_lg_nlOOl00i15346w(0) <= NOT nlOOl00i; + wire_w_lg_nlOOl00l15344w(0) <= NOT nlOOl00l; + wire_w_lg_nlOOl01i15352w(0) <= NOT nlOOl01i; + wire_w_lg_nlOOl01l15350w(0) <= NOT nlOOl01l; + wire_w_lg_nlOOl01O15348w(0) <= NOT nlOOl01O; + wire_w_lg_nlOOl0lO15144w(0) <= NOT nlOOl0lO; + wire_w_lg_nlOOl0Oi15142w(0) <= NOT nlOOl0Oi; + wire_w_lg_nlOOl0Ol15133w(0) <= NOT nlOOl0Ol; + wire_w_lg_nlOOl0OO15131w(0) <= NOT nlOOl0OO; + wire_w_lg_nlOOl10i15386w(0) <= NOT nlOOl10i; + wire_w_lg_nlOOl10l15377w(0) <= NOT nlOOl10l; + wire_w_lg_nlOOl10O15375w(0) <= NOT nlOOl10O; + wire_w_lg_nlOOl11O15388w(0) <= NOT nlOOl11O; + wire_w_lg_nlOOl1ii15373w(0) <= NOT nlOOl1ii; + wire_w_lg_nlOOl1il15371w(0) <= NOT nlOOl1il; + wire_w_lg_nlOOl1iO15365w(0) <= NOT nlOOl1iO; + wire_w_lg_nlOOl1li15363w(0) <= NOT nlOOl1li; + wire_w_lg_nlOOl1ll15361w(0) <= NOT nlOOl1ll; + wire_w_lg_nlOOl1lO15359w(0) <= NOT nlOOl1lO; + wire_w_lg_nlOOl1Oi15357w(0) <= NOT nlOOl1Oi; + wire_w_lg_nlOOl1Ol15355w(0) <= NOT nlOOl1Ol; + wire_w_lg_nlOOl1OO15353w(0) <= NOT nlOOl1OO; + wire_w_lg_nlOOli0i15119w(0) <= NOT nlOOli0i; + wire_w_lg_nlOOli0l15117w(0) <= NOT nlOOli0l; + wire_w_lg_nlOOli0O15115w(0) <= NOT nlOOli0O; + wire_w_lg_nlOOli1i15129w(0) <= NOT nlOOli1i; + wire_w_lg_nlOOli1l15127w(0) <= NOT nlOOli1l; + wire_w_lg_nlOOli1O15121w(0) <= NOT nlOOli1O; + wire_w_lg_nlOOliii15113w(0) <= NOT nlOOliii; + wire_w_lg_nlOOliil15111w(0) <= NOT nlOOliil; + wire_w_lg_nlOOliiO15109w(0) <= NOT nlOOliiO; + wire_w_lg_nlOOlili15108w(0) <= NOT nlOOlili; + wire_w_lg_nlOOlill15106w(0) <= NOT nlOOlill; + wire_w_lg_nlOOlilO15104w(0) <= NOT nlOOlilO; + wire_w_lg_nlOOliOi15102w(0) <= NOT nlOOliOi; + wire_w_lg_nlOOliOl15100w(0) <= NOT nlOOliOl; + wire_w_lg_nlOOll0O14902w(0) <= NOT nlOOll0O; + wire_w_lg_nlOOllii14900w(0) <= NOT nlOOllii; + wire_w_lg_nlOOllil14891w(0) <= NOT nlOOllil; + wire_w_lg_nlOOlliO14889w(0) <= NOT nlOOlliO; + wire_w_lg_nlOOllli14887w(0) <= NOT nlOOllli; + wire_w_lg_nlOOllll14885w(0) <= NOT nlOOllll; + wire_w_lg_nlOOlllO14879w(0) <= NOT nlOOlllO; + wire_w_lg_nlOOllOi14877w(0) <= NOT nlOOllOi; + wire_w_lg_nlOOllOl14875w(0) <= NOT nlOOllOl; + wire_w_lg_nlOOllOO14873w(0) <= NOT nlOOllOO; + wire_w_lg_nlOOlO0i14866w(0) <= NOT nlOOlO0i; + wire_w_lg_nlOOlO0l14864w(0) <= NOT nlOOlO0l; + wire_w_lg_nlOOlO0O14862w(0) <= NOT nlOOlO0O; + wire_w_lg_nlOOlO1i14871w(0) <= NOT nlOOlO1i; + wire_w_lg_nlOOlO1l14869w(0) <= NOT nlOOlO1l; + wire_w_lg_nlOOlO1O14867w(0) <= NOT nlOOlO1O; + wire_w_lg_nlOOlOii14860w(0) <= NOT nlOOlOii; + wire_w_lg_nlOOlOil14858w(0) <= NOT nlOOlOil; + wire_w_lg_nlOOlOiO16466w(0) <= NOT nlOOlOiO; + wire_w_lg_nlOOlOli15399w(0) <= NOT nlOOlOli; + wire_w_lg_nlOOlOlO15401w(0) <= NOT nlOOlOlO; + wire_w_lg_nlOOlOOl15404w(0) <= NOT nlOOlOOl; + wire_w_lg_nlOOO00i15157w(0) <= NOT nlOOO00i; + wire_w_lg_nlOOO00O15160w(0) <= NOT nlOOO00O; + wire_w_lg_nlOOO01l15155w(0) <= NOT nlOOO01l; + wire_w_lg_nlOOO0il15164w(0) <= NOT nlOOO0il; + wire_w_lg_nlOOO0iO15408w(0) <= NOT nlOOO0iO; + wire_w_lg_nlOOO0ll15169w(0) <= NOT nlOOO0ll; + wire_w_lg_nlOOO0Ol15175w(0) <= NOT nlOOO0Ol; + wire_w_lg_nlOOO10i15434w(0) <= NOT nlOOO10i; + wire_w_lg_nlOOO10l15443w(0) <= NOT nlOOO10l; + wire_w_lg_nlOOO10O15453w(0) <= NOT nlOOO10O; + wire_w_lg_nlOOO11i15413w(0) <= NOT nlOOO11i; + wire_w_lg_nlOOO11l15419w(0) <= NOT nlOOO11l; + wire_w_lg_nlOOO11O15426w(0) <= NOT nlOOO11O; + wire_w_lg_nlOOO1ii15464w(0) <= NOT nlOOO1ii; + wire_w_lg_nlOOO1il15476w(0) <= NOT nlOOO1il; + wire_w_lg_nlOOO1iO15489w(0) <= NOT nlOOO1iO; + wire_w_lg_nlOOO1li15503w(0) <= NOT nlOOO1li; + wire_w_lg_nlOOO1ll15518w(0) <= NOT nlOOO1ll; + wire_w_lg_nlOOO1lO15534w(0) <= NOT nlOOO1lO; + wire_w_lg_nlOOO1Oi15551w(0) <= NOT nlOOO1Oi; + wire_w_lg_nlOOO1Ol15569w(0) <= NOT nlOOO1Ol; + wire_w_lg_nlOOO1OO16446w(0) <= NOT nlOOO1OO; + wire_w_lg_nlOOOi0l15190w(0) <= NOT nlOOOi0l; + wire_w_lg_nlOOOi1l15182w(0) <= NOT nlOOOi1l; + wire_w_lg_nlOOOiil15199w(0) <= NOT nlOOOiil; + wire_w_lg_nlOOOill15209w(0) <= NOT nlOOOill; + wire_w_lg_nlOOOiOl15220w(0) <= NOT nlOOOiOl; + wire_w_lg_nlOOOl0l15245w(0) <= NOT nlOOOl0l; + wire_w_lg_nlOOOl1l15232w(0) <= NOT nlOOOl1l; + wire_w_lg_nlOOOlil15259w(0) <= NOT nlOOOlil; + wire_w_lg_nlOOOlll15274w(0) <= NOT nlOOOlll; + wire_w_lg_nlOOOlOl15290w(0) <= NOT nlOOOlOl; + wire_w_lg_nlOOOlOO15307w(0) <= NOT nlOOOlOO; + wire_w_lg_nlOOOO0i16426w(0) <= NOT nlOOOO0i; + wire_w_lg_nlOOOO0l14913w(0) <= NOT nlOOOO0l; + wire_w_lg_nlOOOO0O14423w(0) <= NOT nlOOOO0O; + wire_w_lg_nlOOOO1i15325w(0) <= NOT nlOOOO1i; + wire_w_lg_nlOOOOii14915w(0) <= NOT nlOOOOii; + wire_w_lg_nlOOOOil14403w(0) <= NOT nlOOOOil; + wire_w_lg_nlOOOOiO14918w(0) <= NOT nlOOOOiO; + wire_w_lg_nlOOOOli14384w(0) <= NOT nlOOOOli; + wire_w_lg_nlOOOOll14932w(0) <= NOT nlOOOOll; + wire_w_lg_nlOOOOlO14939w(0) <= NOT nlOOOOlO; + wire_w_lg_nlOOOOOi14947w(0) <= NOT nlOOOOOi; + wire_w_lg_nlOOOOOl14956w(0) <= NOT nlOOOOOl; + wire_w_lg_nlOOOOOO14966w(0) <= NOT nlOOOOOO; + wire_w_lg_rencdt_rising4504w(0) <= NOT rencdt_rising; + wire_w_lg_rfreq_sel4w(0) <= NOT rfreq_sel; + wire_w_lg_rkchar3383w(0) <= NOT rkchar; + wire_w_lg_rosbased3492w(0) <= NOT rosbased; + wire_w_lg_rst113w(0) <= NOT rst; + wire_w_lg_sync_sm_dis1224w(0) <= NOT sync_sm_dis; + wire_w_lg_wa_6g_en4499w(0) <= NOT wa_6g_en; + wire_w_lg_w_comp_pat_size_range1331w1332w(0) <= NOT wire_w_comp_pat_size_range1331w(0); + wire_w_lg_w_pmadwidth_range175w219w(0) <= NOT wire_w_pmadwidth_range175w(0); + wire_w_lg_w_resync_badcg_en_range4513w4514w(0) <= NOT wire_w_resync_badcg_en_range4513w(0); + wire_w_lg_w_lg_w_lg_w_lg_rauto_speed_ena5w8w9w10w(0) <= wire_w_lg_w_lg_w_lg_rauto_speed_ena5w8w9w(0) OR dwidth; + wire_w_lg_w_lg_comp_pat_porn4782w4783w(0) <= wire_w_lg_comp_pat_porn4782w(0) OR n10100i; + wire_w_lg_w_lg_comp_pat_porn4786w4787w(0) <= wire_w_lg_comp_pat_porn4786w(0) OR n10101i; + wire_w_lg_w_lg_comp_pat_porn4780w4781w(0) <= wire_w_lg_comp_pat_porn4780w(0) OR n10100O; + wire_w_lg_w_lg_comp_pat_porn4776w4777w(0) <= wire_w_lg_comp_pat_porn4776w(0) OR n1010iO; + wire_w_lg_w_lg_comp_pat_porn4774w4775w(0) <= wire_w_lg_comp_pat_porn4774w(0) OR n1010ll; + wire_w_lg_w_lg_comp_pat_porn4770w4771w(0) <= wire_w_lg_comp_pat_porn4770w(0) OR n1010Ol; + wire_w_lg_w_lg_comp_pat_porn4800w4801w(0) <= wire_w_lg_comp_pat_porn4800w(0) OR n10110i; + wire_w_lg_w_lg_comp_pat_porn4804w4805w(0) <= wire_w_lg_comp_pat_porn4804w(0) OR n10111i; + wire_w_lg_w_lg_comp_pat_porn4798w4799w(0) <= wire_w_lg_comp_pat_porn4798w(0) OR n10110O; + wire_w_lg_w_lg_comp_pat_porn4794w4795w(0) <= wire_w_lg_comp_pat_porn4794w(0) OR n1011iO; + wire_w_lg_w_lg_comp_pat_porn4792w4793w(0) <= wire_w_lg_comp_pat_porn4792w(0) OR n1011ll; + wire_w_lg_w_lg_comp_pat_porn4788w4789w(0) <= wire_w_lg_comp_pat_porn4788w(0) OR n1011Ol; + wire_w_lg_w_lg_comp_pat_porn4764w4765w(0) <= wire_w_lg_comp_pat_porn4764w(0) OR n101i0i; + wire_w_lg_w_lg_comp_pat_porn4768w4769w(0) <= wire_w_lg_comp_pat_porn4768w(0) OR n101i1i; + wire_w_lg_w_lg_comp_pat_porn4762w4763w(0) <= wire_w_lg_comp_pat_porn4762w(0) OR n101i0O; + wire_w_lg_w_lg_comp_pat_porn4758w4759w(0) <= wire_w_lg_comp_pat_porn4758w(0) OR n101iiO; + wire_w_lg_w_lg_comp_pat_porn4756w4757w(0) <= wire_w_lg_comp_pat_porn4756w(0) OR n101ill; + wire_w_lg_w_lg_comp_pat_porn5097w5098w(0) <= wire_w_lg_comp_pat_porn5097w(0) OR n110O0l; + wire_w_lg_w_lg_comp_pat_porn5095w5096w(0) <= wire_w_lg_comp_pat_porn5095w(0) OR n110Oii; + wire_w_lg_w_lg_comp_pat_porn5091w5092w(0) <= wire_w_lg_comp_pat_porn5091w(0) OR n110Oli; + wire_w_lg_w_lg_comp_pat_porn5089w5090w(0) <= wire_w_lg_comp_pat_porn5089w(0) OR n110OlO; + wire_w_lg_w_lg_comp_pat_porn5757w5758w(0) <= wire_w_lg_comp_pat_porn5757w(0) OR n111Oii; + wire_w_lg_w_lg_comp_pat_porn5743w5744w(0) <= wire_w_lg_comp_pat_porn5743w(0) OR n111Oli; + wire_w_lg_w_lg_comp_pat_porn5738w5739w(0) <= wire_w_lg_comp_pat_porn5738w(0) OR n111OOi; + wire_w_lg_w_lg_comp_pat_porn5061w5062w(0) <= wire_w_lg_comp_pat_porn5061w(0) OR n11i00l; + wire_w_lg_w_lg_comp_pat_porn5067w5068w(0) <= wire_w_lg_comp_pat_porn5067w(0) OR n11i1OO; + wire_w_lg_w_lg_comp_pat_porn5065w5066w(0) <= wire_w_lg_comp_pat_porn5065w(0) OR n11i01l; + wire_w_lg_w_lg_comp_pat_porn5059w5060w(0) <= wire_w_lg_comp_pat_porn5059w(0) OR n11i0ii; + wire_w_lg_w_lg_comp_pat_porn5055w5056w(0) <= wire_w_lg_comp_pat_porn5055w(0) OR n11i0li; + wire_w_lg_w_lg_comp_pat_porn5053w5054w(0) <= wire_w_lg_comp_pat_porn5053w(0) OR n11i0lO; + wire_w_lg_w_lg_comp_pat_porn5079w5080w(0) <= wire_w_lg_comp_pat_porn5079w(0) OR n11i10l; + wire_w_lg_w_lg_comp_pat_porn5085w5086w(0) <= wire_w_lg_comp_pat_porn5085w(0) OR n110OOO; + wire_w_lg_w_lg_comp_pat_porn5083w5084w(0) <= wire_w_lg_comp_pat_porn5083w(0) OR n11i11l; + wire_w_lg_w_lg_comp_pat_porn5077w5078w(0) <= wire_w_lg_comp_pat_porn5077w(0) OR n11i1ii; + wire_w_lg_w_lg_comp_pat_porn5073w5074w(0) <= wire_w_lg_comp_pat_porn5073w(0) OR n11i1li; + wire_w_lg_w_lg_comp_pat_porn5071w5072w(0) <= wire_w_lg_comp_pat_porn5071w(0) OR n11i1lO; + wire_w_lg_w_lg_comp_pat_porn5043w5044w(0) <= wire_w_lg_comp_pat_porn5043w(0) OR n11ii0l; + wire_w_lg_w_lg_comp_pat_porn5049w5050w(0) <= wire_w_lg_comp_pat_porn5049w(0) OR n11i0OO; + wire_w_lg_w_lg_comp_pat_porn5047w5048w(0) <= wire_w_lg_comp_pat_porn5047w(0) OR n11ii1l; + wire_w_lg_w_lg_comp_pat_porn5041w5042w(0) <= wire_w_lg_comp_pat_porn5041w(0) OR n11iiii; + wire_w_lg_w_lg_comp_pat_porn5037w5038w(0) <= wire_w_lg_comp_pat_porn5037w(0) OR n11iili; + wire_w_lg_w_lg_comp_pat_porn5035w5036w(0) <= wire_w_lg_comp_pat_porn5035w(0) OR n11iilO; + wire_w_lg_w_lg_comp_pat_porn5025w5026w(0) <= wire_w_lg_comp_pat_porn5025w(0) OR n11il0l; + wire_w_lg_w_lg_comp_pat_porn5031w5032w(0) <= wire_w_lg_comp_pat_porn5031w(0) OR n11iiOO; + wire_w_lg_w_lg_comp_pat_porn5029w5030w(0) <= wire_w_lg_comp_pat_porn5029w(0) OR n11il1l; + wire_w_lg_w_lg_comp_pat_porn5023w5024w(0) <= wire_w_lg_comp_pat_porn5023w(0) OR n11ilii; + wire_w_lg_w_lg_comp_pat_porn5019w5020w(0) <= wire_w_lg_comp_pat_porn5019w(0) OR n11illi; + wire_w_lg_w_lg_comp_pat_porn5017w5018w(0) <= wire_w_lg_comp_pat_porn5017w(0) OR n11illO; + wire_w_lg_w_lg_comp_pat_porn5007w5008w(0) <= wire_w_lg_comp_pat_porn5007w(0) OR n11iO0l; + wire_w_lg_w_lg_comp_pat_porn5013w5014w(0) <= wire_w_lg_comp_pat_porn5013w(0) OR n11ilOO; + wire_w_lg_w_lg_comp_pat_porn5011w5012w(0) <= wire_w_lg_comp_pat_porn5011w(0) OR n11iO1l; + wire_w_lg_w_lg_comp_pat_porn5005w5006w(0) <= wire_w_lg_comp_pat_porn5005w(0) OR n11iOii; + wire_w_lg_w_lg_comp_pat_porn4872w4873w(0) <= wire_w_lg_comp_pat_porn4872w(0) OR n11O00i; + wire_w_lg_w_lg_comp_pat_porn4870w4871w(0) <= wire_w_lg_comp_pat_porn4870w(0) OR n11O00O; + wire_w_lg_w_lg_comp_pat_porn4866w4867w(0) <= wire_w_lg_comp_pat_porn4866w(0) OR n11O0iO; + wire_w_lg_w_lg_comp_pat_porn4864w4865w(0) <= wire_w_lg_comp_pat_porn4864w(0) OR n11O0ll; + wire_w_lg_w_lg_comp_pat_porn4860w4861w(0) <= wire_w_lg_comp_pat_porn4860w(0) OR n11O0Ol; + wire_w_lg_w_lg_comp_pat_porn4854w4855w(0) <= wire_w_lg_comp_pat_porn4854w(0) OR n11Oi0i; + wire_w_lg_w_lg_comp_pat_porn4858w4859w(0) <= wire_w_lg_comp_pat_porn4858w(0) OR n11Oi1i; + wire_w_lg_w_lg_comp_pat_porn4852w4853w(0) <= wire_w_lg_comp_pat_porn4852w(0) OR n11Oi0O; + wire_w_lg_w_lg_comp_pat_porn4848w4849w(0) <= wire_w_lg_comp_pat_porn4848w(0) OR n11OiiO; + wire_w_lg_w_lg_comp_pat_porn4846w4847w(0) <= wire_w_lg_comp_pat_porn4846w(0) OR n11Oill; + wire_w_lg_w_lg_comp_pat_porn4842w4843w(0) <= wire_w_lg_comp_pat_porn4842w(0) OR n11OiOl; + wire_w_lg_w_lg_comp_pat_porn4836w4837w(0) <= wire_w_lg_comp_pat_porn4836w(0) OR n11Ol0i; + wire_w_lg_w_lg_comp_pat_porn4840w4841w(0) <= wire_w_lg_comp_pat_porn4840w(0) OR n11Ol1i; + wire_w_lg_w_lg_comp_pat_porn4834w4835w(0) <= wire_w_lg_comp_pat_porn4834w(0) OR n11Ol0O; + wire_w_lg_w_lg_comp_pat_porn4830w4831w(0) <= wire_w_lg_comp_pat_porn4830w(0) OR n11OliO; + wire_w_lg_w_lg_comp_pat_porn4828w4829w(0) <= wire_w_lg_comp_pat_porn4828w(0) OR n11Olll; + wire_w_lg_w_lg_comp_pat_porn4824w4825w(0) <= wire_w_lg_comp_pat_porn4824w(0) OR n11OlOl; + wire_w_lg_w_lg_comp_pat_porn4818w4819w(0) <= wire_w_lg_comp_pat_porn4818w(0) OR n11OO0i; + wire_w_lg_w_lg_comp_pat_porn4822w4823w(0) <= wire_w_lg_comp_pat_porn4822w(0) OR n11OO1i; + wire_w_lg_w_lg_comp_pat_porn4816w4817w(0) <= wire_w_lg_comp_pat_porn4816w(0) OR n11OO0O; + wire_w_lg_w_lg_comp_pat_porn4812w4813w(0) <= wire_w_lg_comp_pat_porn4812w(0) OR n11OOiO; + wire_w_lg_w_lg_comp_pat_porn4810w4811w(0) <= wire_w_lg_comp_pat_porn4810w(0) OR n11OOll; + wire_w_lg_w_lg_comp_pat_porn4806w4807w(0) <= wire_w_lg_comp_pat_porn4806w(0) OR n11OOOl; + wire_w_lg_w_lg_w_pmadwidth_range175w176w177w(0) <= wire_w_lg_w_pmadwidth_range175w176w(0) OR n1ii0Oi; + wire_w_lg_w_lg_n10ll0O3433w3447w(0) <= wire_w_lg_n10ll0O3433w(0) OR n10ll0l; + wire_w_lg_w_lg_n11100i14248w15001w(0) <= wire_w_lg_n11100i14248w(0) OR n11110i; + wire_w_lg_w_lg_n11100i14248w15015w(0) <= wire_w_lg_n11100i14248w(0) OR n11110l; + wire_w_lg_w_lg_n11100i14248w15030w(0) <= wire_w_lg_n11100i14248w(0) OR n11110O; + wire_w_lg_w_lg_n11100i14248w14965w(0) <= wire_w_lg_n11100i14248w(0) OR n11111i; + wire_w_lg_w_lg_n11100i14248w14976w(0) <= wire_w_lg_n11100i14248w(0) OR n11111l; + wire_w_lg_w_lg_n11100i14248w14988w(0) <= wire_w_lg_n11100i14248w(0) OR n11111O; + wire_w_lg_w_lg_n11100i14248w15046w(0) <= wire_w_lg_n11100i14248w(0) OR n1111ii; + wire_w_lg_w_lg_n11100i14248w15063w(0) <= wire_w_lg_n11100i14248w(0) OR n1111il; + wire_w_lg_w_lg_n11100i14248w15081w(0) <= wire_w_lg_n11100i14248w(0) OR n1111iO; + wire_w_lg_w_lg_n11100i14248w14931w(0) <= wire_w_lg_n11100i14248w(0) OR nlOOOOlO; + wire_w_lg_w_lg_n11100i14248w14938w(0) <= wire_w_lg_n11100i14248w(0) OR nlOOOOOi; + wire_w_lg_w_lg_n11100i14248w14946w(0) <= wire_w_lg_n11100i14248w(0) OR nlOOOOOl; + wire_w_lg_w_lg_n11100i14248w14955w(0) <= wire_w_lg_n11100i14248w(0) OR nlOOOOOO; + wire_w_lg_w_lg_n1i1l0O2133w2304w(0) <= wire_w_lg_n1i1l0O2133w(0) OR n1i1ill; + wire_w_lg_w_lg_n1i1l0O2133w2309w(0) <= wire_w_lg_n1i1l0O2133w(0) OR n1i1ilO; + wire_w_lg_w_lg_n1i1l0O2133w2315w(0) <= wire_w_lg_n1i1l0O2133w(0) OR n1i1iOi; + wire_w_lg_w_lg_n1i1l0O2133w2322w(0) <= wire_w_lg_n1i1l0O2133w(0) OR n1i1iOl; + wire_w_lg_w_lg_n1i1l0O2133w2330w(0) <= wire_w_lg_n1i1l0O2133w(0) OR n1i1iOO; + wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) OR wire_nl_w_lg_nlli0lO15746w(0); + wire_w_lg_w_lg_w_pmadwidth_range175w219w2572w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) OR nlil0i; + wire_w_lg_w_lg_w_pmadwidth_range175w219w2564w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) OR nlil0l; + wire_w_lg_w_lg_w_pmadwidth_range175w219w2556w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) OR nlil0O; + wire_w_lg_w_lg_w_pmadwidth_range175w219w2580w(0) <= wire_w_lg_w_pmadwidth_range175w219w(0) OR nlil1O; + wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w176w177w181w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w176w177w(0) OR wire_n1ii0ll16_w_lg_w_lg_q179w180w(0); + wire_w15832w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli01i; + wire_w15820w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli01l; + wire_w15916w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli1iO; + wire_w15904w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli1li; + wire_w15892w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli1ll; + wire_w15880w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli1lO; + wire_w15868w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli1Oi; + wire_w15856w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli1Ol; + wire_w15844w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR nlli1OO; + wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2572w2573w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w2572w(0) OR nlil1O; + wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2564w2565w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w2564w(0) OR nlil0i; + wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2556w2557w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w2556w(0) OR nlil0l; + wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2580w2581w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w219w2580w(0) OR nlil1l; + wire_w182w(0) <= wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w176w177w181w(0) OR n1ii0li; + wire_w_lg_w15832w15833w(0) <= wire_w15832w(0) OR nlli1OO; + wire_w_lg_w15820w15821w(0) <= wire_w15820w(0) OR nlli01i; + wire_w_lg_w15916w15917w(0) <= wire_w15916w(0) OR nlli1il; + wire_w_lg_w15904w15905w(0) <= wire_w15904w(0) OR nlli1iO; + wire_w_lg_w15892w15893w(0) <= wire_w15892w(0) OR nlli1li; + wire_w_lg_w15880w15881w(0) <= wire_w15880w(0) OR nlli1ll; + wire_w_lg_w15868w15869w(0) <= wire_w15868w(0) OR nlli1lO; + wire_w_lg_w15856w15857w(0) <= wire_w15856w(0) OR nlli1Oi; + wire_w_lg_w15844w15845w(0) <= wire_w15844w(0) OR nlli1Ol; + wire_w2574w(0) <= wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2572w2573w(0) OR nlil1l; + wire_w2566w(0) <= wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2564w2565w(0) OR nlil1O; + wire_w2558w(0) <= wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2556w2557w(0) OR nlil0i; + wire_w2582w(0) <= wire_w_lg_w_lg_w_lg_w_pmadwidth_range175w219w2580w2581w(0) OR nlil1i; + wire_w_lg_w_lg_w15832w15833w15834w(0) <= wire_w_lg_w15832w15833w(0) OR nlli1Ol; + wire_w_lg_w_lg_w15820w15821w15822w(0) <= wire_w_lg_w15820w15821w(0) OR nlli1OO; + wire_w_lg_w_lg_w15916w15917w15918w(0) <= wire_w_lg_w15916w15917w(0) OR nlli1ii; + wire_w_lg_w_lg_w15904w15905w15906w(0) <= wire_w_lg_w15904w15905w(0) OR nlli1il; + wire_w_lg_w_lg_w15892w15893w15894w(0) <= wire_w_lg_w15892w15893w(0) OR nlli1iO; + wire_w_lg_w_lg_w15880w15881w15882w(0) <= wire_w_lg_w15880w15881w(0) OR nlli1li; + wire_w_lg_w_lg_w15868w15869w15870w(0) <= wire_w_lg_w15868w15869w(0) OR nlli1ll; + wire_w_lg_w_lg_w15856w15857w15858w(0) <= wire_w_lg_w15856w15857w(0) OR nlli1lO; + wire_w_lg_w_lg_w15844w15845w15846w(0) <= wire_w_lg_w15844w15845w(0) OR nlli1Oi; + wire_w_lg_w2574w2575w(0) <= wire_w2574w(0) OR nlil1i; + wire_w_lg_w2566w2567w(0) <= wire_w2566w(0) OR nlil1l; + wire_w_lg_w2558w2559w(0) <= wire_w2558w(0) OR nlil1O; + wire_w_lg_w2582w2583w(0) <= wire_w2582w(0) OR nliiOO; + wire_w_lg_w_lg_w_lg_w15832w15833w15834w15835w(0) <= wire_w_lg_w_lg_w15832w15833w15834w(0) OR nlli1Oi; + wire_w_lg_w_lg_w_lg_w15820w15821w15822w15823w(0) <= wire_w_lg_w_lg_w15820w15821w15822w(0) OR nlli1Ol; + wire_w_lg_w_lg_w_lg_w15916w15917w15918w15919w(0) <= wire_w_lg_w_lg_w15916w15917w15918w(0) OR nlli10O; + wire_w_lg_w_lg_w_lg_w15904w15905w15906w15907w(0) <= wire_w_lg_w_lg_w15904w15905w15906w(0) OR nlli1ii; + wire_w_lg_w_lg_w_lg_w15892w15893w15894w15895w(0) <= wire_w_lg_w_lg_w15892w15893w15894w(0) OR nlli1il; + wire_w_lg_w_lg_w_lg_w15880w15881w15882w15883w(0) <= wire_w_lg_w_lg_w15880w15881w15882w(0) OR nlli1iO; + wire_w_lg_w_lg_w_lg_w15868w15869w15870w15871w(0) <= wire_w_lg_w_lg_w15868w15869w15870w(0) OR nlli1li; + wire_w_lg_w_lg_w_lg_w15856w15857w15858w15859w(0) <= wire_w_lg_w_lg_w15856w15857w15858w(0) OR nlli1ll; + wire_w_lg_w_lg_w_lg_w15844w15845w15846w15847w(0) <= wire_w_lg_w_lg_w15844w15845w15846w(0) OR nlli1lO; + wire_w_lg_w_lg_w2574w2575w2576w(0) <= wire_w_lg_w2574w2575w(0) OR nliiOO; + wire_w_lg_w_lg_w2566w2567w2568w(0) <= wire_w_lg_w2566w2567w(0) OR nlil1i; + wire_w_lg_w_lg_w2558w2559w2560w(0) <= wire_w_lg_w2558w2559w(0) OR nlil1l; + wire_w_lg_w_lg_w2582w2583w2584w(0) <= wire_w_lg_w2582w2583w(0) OR nliiOl; + wire_w15836w(0) <= wire_w_lg_w_lg_w_lg_w15832w15833w15834w15835w(0) OR nlli1lO; + wire_w15824w(0) <= wire_w_lg_w_lg_w_lg_w15820w15821w15822w15823w(0) OR nlli1Oi; + wire_w15920w(0) <= wire_w_lg_w_lg_w_lg_w15916w15917w15918w15919w(0) OR nlli10l; + wire_w15908w(0) <= wire_w_lg_w_lg_w_lg_w15904w15905w15906w15907w(0) OR nlli10O; + wire_w15896w(0) <= wire_w_lg_w_lg_w_lg_w15892w15893w15894w15895w(0) OR nlli1ii; + wire_w15884w(0) <= wire_w_lg_w_lg_w_lg_w15880w15881w15882w15883w(0) OR nlli1il; + wire_w15872w(0) <= wire_w_lg_w_lg_w_lg_w15868w15869w15870w15871w(0) OR nlli1iO; + wire_w15860w(0) <= wire_w_lg_w_lg_w_lg_w15856w15857w15858w15859w(0) OR nlli1li; + wire_w15848w(0) <= wire_w_lg_w_lg_w_lg_w15844w15845w15846w15847w(0) OR nlli1ll; + wire_w_lg_w_lg_w_lg_w2574w2575w2576w2577w(0) <= wire_w_lg_w_lg_w2574w2575w2576w(0) OR nliiOl; + wire_w_lg_w_lg_w_lg_w2566w2567w2568w2569w(0) <= wire_w_lg_w_lg_w2566w2567w2568w(0) OR nliiOO; + wire_w_lg_w_lg_w_lg_w2558w2559w2560w2561w(0) <= wire_w_lg_w_lg_w2558w2559w2560w(0) OR nlil1i; + wire_w_lg_w_lg_w_lg_w2582w2583w2584w2585w(0) <= wire_w_lg_w_lg_w2582w2583w2584w(0) OR nl1lOi; + wire_w_lg_w15836w15837w(0) <= wire_w15836w(0) OR nlli1ll; + wire_w_lg_w15824w15825w(0) <= wire_w15824w(0) OR nlli1lO; + wire_w_lg_w15920w15921w(0) <= wire_w15920w(0) OR nlli10i; + wire_w_lg_w15908w15909w(0) <= wire_w15908w(0) OR nlli10l; + wire_w_lg_w15896w15897w(0) <= wire_w15896w(0) OR nlli10O; + wire_w_lg_w15884w15885w(0) <= wire_w15884w(0) OR nlli1ii; + wire_w_lg_w15872w15873w(0) <= wire_w15872w(0) OR nlli1il; + wire_w_lg_w15860w15861w(0) <= wire_w15860w(0) OR nlli1iO; + wire_w_lg_w15848w15849w(0) <= wire_w15848w(0) OR nlli1li; + wire_w_lg_w_lg_w15836w15837w15838w(0) <= wire_w_lg_w15836w15837w(0) OR nlli1li; + wire_w_lg_w_lg_w15824w15825w15826w(0) <= wire_w_lg_w15824w15825w(0) OR nlli1ll; + wire_w_lg_w_lg_w15920w15921w15922w(0) <= wire_w_lg_w15920w15921w(0) OR nlli11O; + wire_w_lg_w_lg_w15908w15909w15910w(0) <= wire_w_lg_w15908w15909w(0) OR nlli10i; + wire_w_lg_w_lg_w15896w15897w15898w(0) <= wire_w_lg_w15896w15897w(0) OR nlli10l; + wire_w_lg_w_lg_w15884w15885w15886w(0) <= wire_w_lg_w15884w15885w(0) OR nlli10O; + wire_w_lg_w_lg_w15872w15873w15874w(0) <= wire_w_lg_w15872w15873w(0) OR nlli1ii; + wire_w_lg_w_lg_w15860w15861w15862w(0) <= wire_w_lg_w15860w15861w(0) OR nlli1il; + wire_w_lg_w_lg_w15848w15849w15850w(0) <= wire_w_lg_w15848w15849w(0) OR nlli1iO; + wire_w_lg_w_lg_w_lg_w15836w15837w15838w15839w(0) <= wire_w_lg_w_lg_w15836w15837w15838w(0) OR nlli1iO; + wire_w_lg_w_lg_w_lg_w15824w15825w15826w15827w(0) <= wire_w_lg_w_lg_w15824w15825w15826w(0) OR nlli1li; + wire_w_lg_w_lg_w_lg_w15920w15921w15922w15923w(0) <= wire_w_lg_w_lg_w15920w15921w15922w(0) OR nlli11l; + wire_w_lg_w_lg_w_lg_w15908w15909w15910w15911w(0) <= wire_w_lg_w_lg_w15908w15909w15910w(0) OR nlli11O; + wire_w_lg_w_lg_w_lg_w15896w15897w15898w15899w(0) <= wire_w_lg_w_lg_w15896w15897w15898w(0) OR nlli10i; + wire_w_lg_w_lg_w_lg_w15884w15885w15886w15887w(0) <= wire_w_lg_w_lg_w15884w15885w15886w(0) OR nlli10l; + wire_w_lg_w_lg_w_lg_w15872w15873w15874w15875w(0) <= wire_w_lg_w_lg_w15872w15873w15874w(0) OR nlli10O; + wire_w_lg_w_lg_w_lg_w15860w15861w15862w15863w(0) <= wire_w_lg_w_lg_w15860w15861w15862w(0) OR nlli1ii; + wire_w_lg_w_lg_w_lg_w15848w15849w15850w15851w(0) <= wire_w_lg_w_lg_w15848w15849w15850w(0) OR nlli1il; + wire_w15840w(0) <= wire_w_lg_w_lg_w_lg_w15836w15837w15838w15839w(0) OR nlli1il; + wire_w15828w(0) <= wire_w_lg_w_lg_w_lg_w15824w15825w15826w15827w(0) OR nlli1iO; + wire_w15924w(0) <= wire_w_lg_w_lg_w_lg_w15920w15921w15922w15923w(0) OR nlli11i; + wire_w15912w(0) <= wire_w_lg_w_lg_w_lg_w15908w15909w15910w15911w(0) OR nlli11l; + wire_w15900w(0) <= wire_w_lg_w_lg_w_lg_w15896w15897w15898w15899w(0) OR nlli11O; + wire_w15888w(0) <= wire_w_lg_w_lg_w_lg_w15884w15885w15886w15887w(0) OR nlli10i; + wire_w15876w(0) <= wire_w_lg_w_lg_w_lg_w15872w15873w15874w15875w(0) OR nlli10l; + wire_w15864w(0) <= wire_w_lg_w_lg_w_lg_w15860w15861w15862w15863w(0) OR nlli10O; + wire_w15852w(0) <= wire_w_lg_w_lg_w_lg_w15848w15849w15850w15851w(0) OR nlli1ii; + wire_w_lg_w15840w15841w(0) <= wire_w15840w(0) OR nlli1ii; + wire_w_lg_w15828w15829w(0) <= wire_w15828w(0) OR nlli1il; + wire_w_lg_w15924w15925w(0) <= wire_w15924w(0) OR nll0OOO; + wire_w_lg_w15912w15913w(0) <= wire_w15912w(0) OR nlli11i; + wire_w_lg_w15900w15901w(0) <= wire_w15900w(0) OR nlli11l; + wire_w_lg_w15888w15889w(0) <= wire_w15888w(0) OR nlli11O; + wire_w_lg_w15876w15877w(0) <= wire_w15876w(0) OR nlli10i; + wire_w_lg_w15864w15865w(0) <= wire_w15864w(0) OR nlli10l; + wire_w_lg_w15852w15853w(0) <= wire_w15852w(0) OR nlli10O; + wire_w_lg_w_lg_w15840w15841w15842w(0) <= wire_w_lg_w15840w15841w(0) OR nlli10O; + wire_w_lg_w_lg_w15828w15829w15830w(0) <= wire_w_lg_w15828w15829w(0) OR nlli1ii; + wire_w_lg_w_lg_w15924w15925w15926w(0) <= wire_w_lg_w15924w15925w(0) OR nll0OOl; + wire_w_lg_w_lg_w15912w15913w15914w(0) <= wire_w_lg_w15912w15913w(0) OR nll0OOO; + wire_w_lg_w_lg_w15900w15901w15902w(0) <= wire_w_lg_w15900w15901w(0) OR nlli11i; + wire_w_lg_w_lg_w15888w15889w15890w(0) <= wire_w_lg_w15888w15889w(0) OR nlli11l; + wire_w_lg_w_lg_w15876w15877w15878w(0) <= wire_w_lg_w15876w15877w(0) OR nlli11O; + wire_w_lg_w_lg_w15864w15865w15866w(0) <= wire_w_lg_w15864w15865w(0) OR nlli10i; + wire_w_lg_w_lg_w15852w15853w15854w(0) <= wire_w_lg_w15852w15853w(0) OR nlli10l; + wire_w_lg_w_lg_w_lg_w15814w15815w15816w15817w(0) <= wire_w_lg_w_lg_w15814w15815w15816w(0) OR nll0OOl; + wire_w_lg_w_lg_w_lg_w15804w15805w15806w15807w(0) <= wire_w_lg_w_lg_w15804w15805w15806w(0) OR nll0OOO; + wire_w_lg_w_lg_w_lg_w15794w15795w15796w15797w(0) <= wire_w_lg_w_lg_w15794w15795w15796w(0) OR nlli11i; + wire_w_lg_w_lg_w_lg_w15784w15785w15786w15787w(0) <= wire_w_lg_w_lg_w15784w15785w15786w(0) OR nlli11l; + wire_w_lg_w_lg_w_lg_w15774w15775w15776w15777w(0) <= wire_w_lg_w_lg_w15774w15775w15776w(0) OR nlli11O; + wire_w_lg_w_lg_w_lg_w15764w15765w15766w15767w(0) <= wire_w_lg_w_lg_w15764w15765w15766w(0) OR nlli10i; + wire_w_lg_w_lg_w_lg_w15753w15754w15755w15756w(0) <= wire_w_lg_w_lg_w15753w15754w15755w(0) OR nlli10l; + wire_w_lg_w_lg_w15814w15815w15816w(0) <= wire_w_lg_w15814w15815w(0) OR nll0OOO; + wire_w_lg_w_lg_w15804w15805w15806w(0) <= wire_w_lg_w15804w15805w(0) OR nlli11i; + wire_w_lg_w_lg_w15794w15795w15796w(0) <= wire_w_lg_w15794w15795w(0) OR nlli11l; + wire_w_lg_w_lg_w15784w15785w15786w(0) <= wire_w_lg_w15784w15785w(0) OR nlli11O; + wire_w_lg_w_lg_w15774w15775w15776w(0) <= wire_w_lg_w15774w15775w(0) OR nlli10i; + wire_w_lg_w_lg_w15764w15765w15766w(0) <= wire_w_lg_w15764w15765w(0) OR nlli10l; + wire_w_lg_w_lg_w15753w15754w15755w(0) <= wire_w_lg_w15753w15754w(0) OR nlli10O; + wire_w_lg_w15814w15815w(0) <= wire_w15814w(0) OR nlli11i; + wire_w_lg_w15804w15805w(0) <= wire_w15804w(0) OR nlli11l; + wire_w_lg_w15794w15795w(0) <= wire_w15794w(0) OR nlli11O; + wire_w_lg_w15784w15785w(0) <= wire_w15784w(0) OR nlli10i; + wire_w_lg_w15774w15775w(0) <= wire_w15774w(0) OR nlli10l; + wire_w_lg_w15764w15765w(0) <= wire_w15764w(0) OR nlli10O; + wire_w_lg_w15753w15754w(0) <= wire_w15753w(0) OR nlli1ii; + wire_w15814w(0) <= wire_w_lg_w_lg_w_lg_w15810w15811w15812w15813w(0) OR nlli11l; + wire_w15804w(0) <= wire_w_lg_w_lg_w_lg_w15800w15801w15802w15803w(0) OR nlli11O; + wire_w15794w(0) <= wire_w_lg_w_lg_w_lg_w15790w15791w15792w15793w(0) OR nlli10i; + wire_w15784w(0) <= wire_w_lg_w_lg_w_lg_w15780w15781w15782w15783w(0) OR nlli10l; + wire_w15774w(0) <= wire_w_lg_w_lg_w_lg_w15770w15771w15772w15773w(0) OR nlli10O; + wire_w15764w(0) <= wire_w_lg_w_lg_w_lg_w15760w15761w15762w15763w(0) OR nlli1ii; + wire_w15753w(0) <= wire_w_lg_w_lg_w_lg_w15749w15750w15751w15752w(0) OR nlli1il; + wire_w_lg_w1202w1203w(0) <= wire_w1202w(0) OR n1i001O; + wire_w_lg_w_lg_w17108w17109w17110w(0) <= wire_w_lg_w17108w17109w(0) OR nlOO1liO; + wire_w_lg_w_lg_w16764w16765w16766w(0) <= wire_w_lg_w16764w16765w(0) OR nlOO0i1O; + wire_w_lg_w_lg_w_lg_w15810w15811w15812w15813w(0) <= wire_w_lg_w_lg_w15810w15811w15812w(0) OR nlli11O; + wire_w_lg_w_lg_w_lg_w15800w15801w15802w15803w(0) <= wire_w_lg_w_lg_w15800w15801w15802w(0) OR nlli10i; + wire_w_lg_w_lg_w_lg_w15790w15791w15792w15793w(0) <= wire_w_lg_w_lg_w15790w15791w15792w(0) OR nlli10l; + wire_w_lg_w_lg_w_lg_w15780w15781w15782w15783w(0) <= wire_w_lg_w_lg_w15780w15781w15782w(0) OR nlli10O; + wire_w_lg_w_lg_w_lg_w15770w15771w15772w15773w(0) <= wire_w_lg_w_lg_w15770w15771w15772w(0) OR nlli1ii; + wire_w_lg_w_lg_w_lg_w15760w15761w15762w15763w(0) <= wire_w_lg_w_lg_w15760w15761w15762w(0) OR nlli1il; + wire_w_lg_w_lg_w_lg_w15749w15750w15751w15752w(0) <= wire_w_lg_w_lg_w15749w15750w15751w(0) OR nlli1iO; + wire_w1202w(0) <= wire_w_lg_w_lg_w_lg_w_lg_n1i00ll1196w1197w1199w1201w(0) OR n1i000i; + wire_w_lg_w17108w17109w(0) <= wire_w17108w(0) OR nlOO01ii; + wire_w_lg_w16764w16765w(0) <= wire_w16764w(0) OR nlOO0O1i; + wire_w_lg_w_lg_w15810w15811w15812w(0) <= wire_w_lg_w15810w15811w(0) OR nlli10i; + wire_w_lg_w_lg_w15800w15801w15802w(0) <= wire_w_lg_w15800w15801w(0) OR nlli10l; + wire_w_lg_w_lg_w15790w15791w15792w(0) <= wire_w_lg_w15790w15791w(0) OR nlli10O; + wire_w_lg_w_lg_w15780w15781w15782w(0) <= wire_w_lg_w15780w15781w(0) OR nlli1ii; + wire_w_lg_w_lg_w15770w15771w15772w(0) <= wire_w_lg_w15770w15771w(0) OR nlli1il; + wire_w_lg_w_lg_w15760w15761w15762w(0) <= wire_w_lg_w15760w15761w(0) OR nlli1iO; + wire_w_lg_w_lg_w15749w15750w15751w(0) <= wire_w_lg_w15749w15750w(0) OR nlli1li; + wire_w_lg_w_lg_w2535w2536w2537w(0) <= wire_w_lg_w2535w2536w(0) OR nliiOO; + wire_w_lg_w_lg_w2551w2552w2553w(0) <= wire_w_lg_w2551w2552w(0) OR nl1lOi; + wire_w_lg_w_lg_w2544w2545w2546w(0) <= wire_w_lg_w2544w2545w(0) OR nliiOl; + wire_w_lg_w_lg_w_lg_w_lg_n1i00ll1196w1197w1199w1201w(0) <= wire_w_lg_w_lg_w_lg_n1i00ll1196w1197w1199w(0) OR wire_w_lg_n1i000O1200w(0); + wire_w17108w(0) <= wire_w_lg_w_lg_w_lg_nlOO010l17103w17104w17106w(0) OR wire_w_lg_nlOO1OOl17107w(0); + wire_w16764w(0) <= wire_w_lg_w_lg_w_lg_nlOO0lOl16759w16760w16762w(0) OR wire_w_lg_nlOO0lil16763w(0); + wire_w_lg_w15810w15811w(0) <= wire_w15810w(0) OR nlli10l; + wire_w_lg_w15800w15801w(0) <= wire_w15800w(0) OR nlli10O; + wire_w_lg_w15790w15791w(0) <= wire_w15790w(0) OR nlli1ii; + wire_w_lg_w15780w15781w(0) <= wire_w15780w(0) OR nlli1il; + wire_w_lg_w15770w15771w(0) <= wire_w15770w(0) OR nlli1iO; + wire_w_lg_w15760w15761w(0) <= wire_w15760w(0) OR nlli1li; + wire_w_lg_w15749w15750w(0) <= wire_w15749w(0) OR nlli1ll; + wire_w_lg_w2535w2536w(0) <= wire_w2535w(0) OR nlil1i; + wire_w_lg_w2551w2552w(0) <= wire_w2551w(0) OR nliiOl; + wire_w_lg_w2544w2545w(0) <= wire_w2544w(0) OR nliiOO; + wire_w_lg_w_lg_w_lg_n1i00ll1196w1197w1199w(0) <= wire_w_lg_w_lg_n1i00ll1196w1197w(0) OR wire_w_lg_n1i00il1198w(0); + wire_w_lg_w_lg_w_lg_nlOO010l17103w17104w17106w(0) <= wire_w_lg_w_lg_nlOO010l17103w17104w(0) OR wire_w_lg_nlOO1llO17105w(0); + wire_w_lg_w_lg_w_lg_nlOO0lOl16759w16760w16762w(0) <= wire_w_lg_w_lg_nlOO0lOl16759w16760w(0) OR wire_w_lg_nlOO0i0O16761w(0); + wire_w15810w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w15747w15809w(0) OR nlli10O; + wire_w15800w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w15747w15799w(0) OR nlli1ii; + wire_w15790w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w15747w15789w(0) OR nlli1il; + wire_w15780w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w15747w15779w(0) OR nlli1iO; + wire_w15770w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w15747w15769w(0) OR nlli1li; + wire_w15760w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w15747w15759w(0) OR nlli1ll; + wire_w15749w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w15747w15748w(0) OR nlli1lO; + wire_w2535w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w2533w2534w(0) OR nlil1l; + wire_w2551w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w2549w2550w(0) OR nliiOO; + wire_w2544w(0) <= wire_w_lg_w_lg_w_pmadwidth_range175w2542w2543w(0) OR nlil1i; + wire_w_lg_w_lg_n10O10i3045w3048w(0) <= wire_w_lg_n10O10i3045w(0) OR wire_w_lg_n10O11l3047w(0); + wire_w_lg_w_lg_n10O10l3063w3067w(0) <= wire_w_lg_n10O10l3063w(0) OR wire_niOl0l_w_lg_w_lg_dataout3064w3066w(0); + wire_w_lg_w_lg_n1i00ll1196w1197w(0) <= wire_w_lg_n1i00ll1196w(0) OR n1i00iO; + wire_w_lg_w_lg_nlOO010l17103w17104w(0) <= wire_w_lg_nlOO010l17103w(0) OR nlOO010i; + wire_w_lg_w_lg_nlOO01Oi16918w16921w(0) <= wire_w_lg_nlOO01Oi16918w(0) OR wire_w_lg_nlOO01ll16920w(0); + wire_w_lg_w_lg_nlOO01Ol16936w16940w(0) <= wire_w_lg_nlOO01Ol16936w(0) OR wire_nl1ll1O_w_lg_w_lg_o16937w16939w(0); + wire_w_lg_w_lg_nlOO0lOl16759w16760w(0) <= wire_w_lg_nlOO0lOl16759w(0) OR nlOO0lOi; + wire_w_lg_w_lg_nlOO0Oii16574w16577w(0) <= wire_w_lg_nlOO0Oii16574w(0) OR wire_w_lg_nlOO0O0l16576w(0); + wire_w_lg_w_lg_nlOO0Oil16592w16596w(0) <= wire_w_lg_nlOO0Oil16592w(0) OR wire_nl1llOi_w_lg_w_lg_o16593w16595w(0); + wire_w_lg_w_lg_w_pmadwidth_range175w15747w15809w(0) <= wire_w_lg_w_pmadwidth_range175w15747w(0) OR nlli1ii; + wire_w_lg_w_lg_w_pmadwidth_range175w15747w15799w(0) <= wire_w_lg_w_pmadwidth_range175w15747w(0) OR nlli1il; + wire_w_lg_w_lg_w_pmadwidth_range175w15747w15789w(0) <= wire_w_lg_w_pmadwidth_range175w15747w(0) OR nlli1iO; + wire_w_lg_w_lg_w_pmadwidth_range175w15747w15779w(0) <= wire_w_lg_w_pmadwidth_range175w15747w(0) OR nlli1li; + wire_w_lg_w_lg_w_pmadwidth_range175w15747w15769w(0) <= wire_w_lg_w_pmadwidth_range175w15747w(0) OR nlli1ll; + wire_w_lg_w_lg_w_pmadwidth_range175w15747w15759w(0) <= wire_w_lg_w_pmadwidth_range175w15747w(0) OR nlli1lO; + wire_w_lg_w_lg_w_pmadwidth_range175w15747w15748w(0) <= wire_w_lg_w_pmadwidth_range175w15747w(0) OR nlli1Oi; + wire_w_lg_w_lg_w_pmadwidth_range175w2533w2534w(0) <= wire_w_lg_w_pmadwidth_range175w2533w(0) OR nlil1O; + wire_w_lg_w_lg_w_pmadwidth_range175w2549w2550w(0) <= wire_w_lg_w_pmadwidth_range175w2549w(0) OR nlil1i; + wire_w_lg_w_lg_w_pmadwidth_range175w2542w2543w(0) <= wire_w_lg_w_pmadwidth_range175w2542w(0) OR nlil1l; + wire_w_lg_lpbk_en4495w(0) <= lpbk_en OR nll01lO; + wire_w_lg_n10l10O4521w(0) <= n10l10O OR n10l10l; + wire_w_lg_n10l1ii4522w(0) <= n10l1ii OR wire_w_lg_n10l10O4521w(0); + wire_w_lg_n10l1il4510w(0) <= n10l1il OR wire_w_lg_rencdt_rising4509w(0); + wire_w_lg_n10lOOO3237w(0) <= n10lOOO OR wire_w_lg_n1i00il3236w(0); + wire_w_lg_n10lOOO3073w(0) <= n10lOOO OR n10lOOl; + wire_w_lg_n10O10i3045w(0) <= n10O10i OR wire_w_lg_n10O10i3044w(0); + wire_w_lg_n10O10l3063w(0) <= n10O10l OR wire_w_lg_n10O10l3062w(0); + wire_w_lg_n10O11i3074w(0) <= n10O11i OR wire_w_lg_n10lOOO3073w(0); + wire_w_lg_n10O1lO2970w(0) <= n10O1lO OR n10O1ll; + wire_w_lg_n10O1Oi2971w(0) <= n10O1Oi OR wire_w_lg_n10O1lO2970w(0); + wire_w_lg_n1111li14881w(0) <= n1111li OR wire_w_lg_nlOOlO0i14866w(0); + wire_w_lg_n1111li14859w(0) <= n1111li OR wire_w_lg_nlOOlOil14858w(0); + wire_w_lg_n1i000i3077w(0) <= n1i000i OR wire_w_lg_n1i00li3076w(0); + wire_w_lg_n1i001l1207w(0) <= n1i001l OR wire_niOiOl_w_lg_w_lg_o1205w1206w(0); + wire_w_lg_n1i00li3076w(0) <= n1i00li OR wire_w_lg_n1i00ll3075w(0); + wire_w_lg_n1i00ll3075w(0) <= n1i00ll OR n1i00iO; + wire_w_lg_n1i00ll1196w(0) <= n1i00ll OR n1i00li; + wire_w_lg_n1i01lO1217w(0) <= n1i01lO OR wire_niOl1O_w_lg_o1216w(0); + wire_w_lg_n1i01Ol1210w(0) <= n1i01Ol OR n1i01Oi; + wire_w_lg_n1i01OO1211w(0) <= n1i01OO OR wire_w_lg_n1i01Ol1210w(0); + wire_w_lg_n1i101i2395w(0) <= n1i101i OR wire_w_lg_n10OlOO2394w(0); + wire_w_lg_n1i101i2497w(0) <= n1i101i OR wire_w_lg_n10OO1i2402w(0); + wire_w_lg_n1i11ii2450w(0) <= n1i11ii OR wire_w_lg_n10Ol0l2449w(0); + wire_w_lg_n1i11ii2507w(0) <= n1i11ii OR wire_w_lg_n10Ol0O2457w(0); + wire_w_lg_n1i1iii2340w(0) <= n1i1iii OR wire_w_lg_n10OOli2339w(0); + wire_w_lg_n1i1iii2473w(0) <= n1i1iii OR wire_w_lg_n10OOll2347w(0); + wire_w_lg_n1i1l1i2286w(0) <= n1i1l1i OR wire_w_lg_n1i110l2285w(0); + wire_w_lg_n1i1l1i2463w(0) <= n1i1l1i OR wire_w_lg_n1i110O2293w(0); + wire_w_lg_n1i1O0O1326w(0) <= n1i1O0O OR n1i1O0l; + wire_w_lg_n1i1Oil1323w(0) <= n1i1Oil OR n1i1Oii; + wire_w_lg_n1i1Oll3095w(0) <= n1i1Oll OR wire_w_lg_n1i1OlO3094w(0); + wire_w_lg_n1i1OlO3094w(0) <= n1i1OlO OR n10lOlO; + wire_w_lg_nlOO000O16840w(0) <= nlOO000O OR nlOO000l; + wire_w_lg_nlOO00ii16841w(0) <= nlOO00ii OR wire_w_lg_nlOO000O16840w(0); + wire_w_lg_nlOO010l16948w(0) <= nlOO010l OR nlOO010i; + wire_w_lg_nlOO010l17103w(0) <= nlOO010l OR nlOO010O; + wire_w_lg_nlOO010O16949w(0) <= nlOO010O OR wire_w_lg_nlOO010l16948w(0); + wire_w_lg_nlOO011i16972w(0) <= nlOO011i OR nlOO1OlO; + wire_w_lg_nlOO01ii16950w(0) <= nlOO01ii OR wire_w_lg_nlOO010O16949w(0); + wire_w_lg_nlOO01iO17133w(0) <= nlOO01iO OR wire_w_lg_nlOO1llO17132w(0); + wire_w_lg_nlOO01iO16946w(0) <= nlOO01iO OR nlOO01il; + wire_w_lg_nlOO01li16947w(0) <= nlOO01li OR wire_w_lg_nlOO01iO16946w(0); + wire_w_lg_nlOO01Oi16918w(0) <= nlOO01Oi OR wire_w_lg_nlOO01Oi16917w(0); + wire_w_lg_nlOO01Ol16936w(0) <= nlOO01Ol OR wire_w_lg_nlOO01Ol16935w(0); + wire_w_lg_nlOO0i1l16769w(0) <= nlOO0i1l OR wire_nl1llii_w_lg_w_lg_o16569w16768w(0); + wire_w_lg_nlOO0ilO16773w(0) <= nlOO0ilO OR wire_w_lg_nlOO0l0i16772w(0); + wire_w_lg_nlOO0iOl16779w(0) <= nlOO0iOl OR wire_nl1llll_w_lg_o16778w(0); + wire_w_lg_nlOO0l0i16772w(0) <= nlOO0l0i OR nlOO0lll; + wire_w_lg_nlOO0liO16629w(0) <= nlOO0liO OR wire_w_lg_nlOO0lli16628w(0); + wire_w_lg_nlOO0lli16628w(0) <= nlOO0lli OR nlOO0l0O; + wire_w_lg_nlOO0lOl16604w(0) <= nlOO0lOl OR nlOO0lOi; + wire_w_lg_nlOO0lOl16759w(0) <= nlOO0lOl OR nlOO0lOO; + wire_w_lg_nlOO0lOO16605w(0) <= nlOO0lOO OR wire_w_lg_nlOO0lOl16604w(0); + wire_w_lg_nlOO0O0i16603w(0) <= nlOO0O0i OR wire_w_lg_nlOO0O1O16602w(0); + wire_w_lg_nlOO0O1i16606w(0) <= nlOO0O1i OR wire_w_lg_nlOO0lOO16605w(0); + wire_w_lg_nlOO0O1O16789w(0) <= nlOO0O1O OR wire_w_lg_nlOO0i0O16788w(0); + wire_w_lg_nlOO0O1O16602w(0) <= nlOO0O1O OR nlOO0O1l; + wire_w_lg_nlOO0Oii16574w(0) <= nlOO0Oii OR wire_w_lg_nlOO0Oii16573w(0); + wire_w_lg_nlOO0Oil16592w(0) <= nlOO0Oil OR wire_w_lg_nlOO0Oil16591w(0); + wire_w_lg_nlOO0OOO16496w(0) <= nlOO0OOO OR nlOO0OOl; + wire_w_lg_nlOO1lil17113w(0) <= nlOO1lil OR wire_nl1lilO_w_lg_w_lg_o16913w17112w(0); + wire_w_lg_nlOO1O0l17123w(0) <= nlOO1O0l OR wire_nl1ll1i_w_lg_o17122w(0); + wire_w_lg_nlOO1O1O17117w(0) <= nlOO1O1O OR wire_w_lg_nlOO1Oli17116w(0); + wire_w_lg_nlOO1Oli17116w(0) <= nlOO1Oli OR nlOO011l; + wire_w_lg_nlOO1OOO16973w(0) <= nlOO1OOO OR wire_w_lg_nlOO011i16972w(0); + wire_w_lg_nlOOi11i16497w(0) <= nlOOi11i OR wire_w_lg_nlOO0OOO16496w(0); + wire_w_lg_nlOOlOiO15611w(0) <= nlOOlOiO OR wire_w_lg_nlOOiOii15596w(0); + wire_w_lg_nlOOlOiO15589w(0) <= nlOOlOiO OR wire_w_lg_nlOOiOll15588w(0); + wire_w_lg_nlOOO1OO15345w(0) <= nlOOO1OO OR wire_w_lg_nlOOl00l15344w(0); + wire_w_lg_nlOOO1OO15367w(0) <= nlOOO1OO OR wire_w_lg_nlOOl01i15352w(0); + wire_w_lg_nlOOOO0i15123w(0) <= nlOOOO0i OR wire_w_lg_nlOOlili15108w(0); + wire_w_lg_nlOOOO0i15101w(0) <= nlOOOO0i OR wire_w_lg_nlOOliOl15100w(0); + wire_w_lg_w_pmadwidth_range175w2589w(0) <= wire_w_pmadwidth_range175w(0) OR wire_nl_w_lg_nlil0i2588w(0); + wire_w_lg_w_pmadwidth_range175w2608w(0) <= wire_w_pmadwidth_range175w(0) OR wire_nl_w_lg_nlil1l2592w(0); + wire_w_lg_w_pmadwidth_range175w2600w(0) <= wire_w_pmadwidth_range175w(0) OR wire_nl_w_lg_nlil1O2590w(0); + wire_w_lg_w_pmadwidth_range175w15747w(0) <= wire_w_pmadwidth_range175w(0) OR wire_nl_w_lg_nlli0lO15746w(0); + wire_w_lg_w_pmadwidth_range175w2533w(0) <= wire_w_pmadwidth_range175w(0) OR nlil0i; + wire_w_lg_w_pmadwidth_range175w2549w(0) <= wire_w_pmadwidth_range175w(0) OR nlil1l; + wire_w_lg_w_pmadwidth_range175w2542w(0) <= wire_w_pmadwidth_range175w(0) OR nlil1O; + a1a2_k1k2_flag <= ( wire_niiiO_dataout & wire_niiil_dataout & wire_niiii_dataout & wire_nii0O_dataout); + adata <= ( wire_niOili_dataout & wire_niOiiO_dataout & wire_niOiil_dataout & wire_niOiii_dataout & wire_niOi0O_dataout & wire_niOi0l_dataout & wire_niOi0i_dataout & wire_niOi1O_dataout & wire_niOi1l_dataout & wire_niOi1i_dataout); + adata_valid <= nlO01ii; + cg_syncpat <= ( wire_nlOi_dataout & wire_nllO_dataout); + kchar <= niiill; + kcount <= ( nlO0ill & nlO0ili & nlO0iiO & nlO0iil & nlO0iii & nlO0i0O & nlO0i0l & nlO0i0i & nlO0i1O & nlO0i1l); + n10000i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0l1O)) AND (NOT ((NOT comp_pat(11)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(12)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(13)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(14)) XOR nll0lii))) AND (NOT ((NOT comp_pat(15)) XOR nll0lil))) AND (NOT ((NOT comp_pat(16)) XOR nll0liO))) AND (NOT ((NOT comp_pat(17)) XOR nll0lli))) AND (NOT ((NOT comp_pat(18)) XOR nll0lll))) AND (NOT ((NOT comp_pat(19)) XOR nll0llO))); + n10000l <= (n10i10O AND ((comp_pat_porn AND n1000ii) OR n10000O)); + n10000O <= ((((((((((NOT (comp_pat(10) XOR nll0l1l)) AND (NOT (comp_pat(11) XOR nll0l1O))) AND (NOT (comp_pat(12) XOR nll0l0i))) AND (NOT (comp_pat(13) XOR nll0l0l))) AND (NOT (comp_pat(14) XOR nll0l0O))) AND (NOT (comp_pat(15) XOR nll0lii))) AND (NOT (comp_pat(16) XOR nll0lil))) AND (NOT (comp_pat(17) XOR nll0liO))) AND (NOT (comp_pat(18) XOR nll0lli))) AND (NOT (comp_pat(19) XOR nll0lll))); + n10001i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0l0i)) AND (NOT ((NOT comp_pat(11)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(12)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(13)) XOR nll0lii))) AND (NOT ((NOT comp_pat(14)) XOR nll0lil))) AND (NOT ((NOT comp_pat(15)) XOR nll0liO))) AND (NOT ((NOT comp_pat(16)) XOR nll0lli))) AND (NOT ((NOT comp_pat(17)) XOR nll0lll))) AND (NOT ((NOT comp_pat(18)) XOR nll0llO))) AND (NOT ((NOT comp_pat(19)) XOR nll0lOi))); + n10001l <= (n10i11O AND ((comp_pat_porn AND n10000i) OR n10001O)); + n10001O <= ((((((((((NOT (comp_pat(10) XOR nll0l1O)) AND (NOT (comp_pat(11) XOR nll0l0i))) AND (NOT (comp_pat(12) XOR nll0l0l))) AND (NOT (comp_pat(13) XOR nll0l0O))) AND (NOT (comp_pat(14) XOR nll0lii))) AND (NOT (comp_pat(15) XOR nll0lil))) AND (NOT (comp_pat(16) XOR nll0liO))) AND (NOT (comp_pat(17) XOR nll0lli))) AND (NOT (comp_pat(18) XOR nll0lll))) AND (NOT (comp_pat(19) XOR nll0llO))); + n1000ii <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0l1l)) AND (NOT ((NOT comp_pat(11)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(12)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(13)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(14)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(15)) XOR nll0lii))) AND (NOT ((NOT comp_pat(16)) XOR nll0lil))) AND (NOT ((NOT comp_pat(17)) XOR nll0liO))) AND (NOT ((NOT comp_pat(18)) XOR nll0lli))) AND (NOT ((NOT comp_pat(19)) XOR nll0lll))); + n1000il <= (n10i1iO AND ((comp_pat_porn AND n1000li) OR n1000iO)); + n1000iO <= ((((((((((NOT (comp_pat(10) XOR nll0l1i)) AND (NOT (comp_pat(11) XOR nll0l1l))) AND (NOT (comp_pat(12) XOR nll0l1O))) AND (NOT (comp_pat(13) XOR nll0l0i))) AND (NOT (comp_pat(14) XOR nll0l0l))) AND (NOT (comp_pat(15) XOR nll0l0O))) AND (NOT (comp_pat(16) XOR nll0lii))) AND (NOT (comp_pat(17) XOR nll0lil))) AND (NOT (comp_pat(18) XOR nll0liO))) AND (NOT (comp_pat(19) XOR nll0lli))); + n1000li <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0l1i)) AND (NOT ((NOT comp_pat(11)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(12)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(13)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(14)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(15)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(16)) XOR nll0lii))) AND (NOT ((NOT comp_pat(17)) XOR nll0lil))) AND (NOT ((NOT comp_pat(18)) XOR nll0liO))) AND (NOT ((NOT comp_pat(19)) XOR nll0lli))); + n1000ll <= (n10i1lO AND ((comp_pat_porn AND n1000Oi) OR n1000lO)); + n1000lO <= ((((((((((NOT (comp_pat(10) XOR nll0iOO)) AND (NOT (comp_pat(11) XOR nll0l1i))) AND (NOT (comp_pat(12) XOR nll0l1l))) AND (NOT (comp_pat(13) XOR nll0l1O))) AND (NOT (comp_pat(14) XOR nll0l0i))) AND (NOT (comp_pat(15) XOR nll0l0l))) AND (NOT (comp_pat(16) XOR nll0l0O))) AND (NOT (comp_pat(17) XOR nll0lii))) AND (NOT (comp_pat(18) XOR nll0lil))) AND (NOT (comp_pat(19) XOR nll0liO))); + n1000Oi <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0iOO)) AND (NOT ((NOT comp_pat(11)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(12)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(13)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(14)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(15)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(16)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(17)) XOR nll0lii))) AND (NOT ((NOT comp_pat(18)) XOR nll0lil))) AND (NOT ((NOT comp_pat(19)) XOR nll0liO))); + n1000Ol <= (((((((((((((((((((n10i1lO OR n10i1iO) OR n10i10O) OR n10i11O) OR n100OOO) OR n100OlO) OR n100OiO) OR n100O0O) OR n100O1O) OR n100lOO) OR n100llO) OR n100liO) OR n100l0O) OR n100l1O) OR n100iOO) OR n100ilO) OR n100iiO) OR n100i0O) OR n100i1O) OR n1000OO); + n1000OO <= ((comp_pat_porn AND n100i1l) OR n100i1i); + n10010i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0lil)) AND (NOT ((NOT comp_pat(11)) XOR nll0liO))) AND (NOT ((NOT comp_pat(12)) XOR nll0lli))) AND (NOT ((NOT comp_pat(13)) XOR nll0lll))) AND (NOT ((NOT comp_pat(14)) XOR nll0llO))) AND (NOT ((NOT comp_pat(15)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(16)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(17)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(18)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(19)) XOR nll0O1l))); + n10010l <= (n100O0O AND ((comp_pat_porn AND n1001ii) OR n10010O)); + n10010O <= ((((((((((NOT (comp_pat(10) XOR nll0lii)) AND (NOT (comp_pat(11) XOR nll0lil))) AND (NOT (comp_pat(12) XOR nll0liO))) AND (NOT (comp_pat(13) XOR nll0lli))) AND (NOT (comp_pat(14) XOR nll0lll))) AND (NOT (comp_pat(15) XOR nll0llO))) AND (NOT (comp_pat(16) XOR nll0lOi))) AND (NOT (comp_pat(17) XOR nll0lOl))) AND (NOT (comp_pat(18) XOR nll0lOO))) AND (NOT (comp_pat(19) XOR nll0O1i))); + n10011i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0liO)) AND (NOT ((NOT comp_pat(11)) XOR nll0lli))) AND (NOT ((NOT comp_pat(12)) XOR nll0lll))) AND (NOT ((NOT comp_pat(13)) XOR nll0llO))) AND (NOT ((NOT comp_pat(14)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(15)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(16)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(17)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(18)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(19)) XOR nll0O1O))); + n10011l <= (n100O1O AND ((comp_pat_porn AND n10010i) OR n10011O)); + n10011O <= ((((((((((NOT (comp_pat(10) XOR nll0lil)) AND (NOT (comp_pat(11) XOR nll0liO))) AND (NOT (comp_pat(12) XOR nll0lli))) AND (NOT (comp_pat(13) XOR nll0lll))) AND (NOT (comp_pat(14) XOR nll0llO))) AND (NOT (comp_pat(15) XOR nll0lOi))) AND (NOT (comp_pat(16) XOR nll0lOl))) AND (NOT (comp_pat(17) XOR nll0lOO))) AND (NOT (comp_pat(18) XOR nll0O1i))) AND (NOT (comp_pat(19) XOR nll0O1l))); + n1001ii <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0lii)) AND (NOT ((NOT comp_pat(11)) XOR nll0lil))) AND (NOT ((NOT comp_pat(12)) XOR nll0liO))) AND (NOT ((NOT comp_pat(13)) XOR nll0lli))) AND (NOT ((NOT comp_pat(14)) XOR nll0lll))) AND (NOT ((NOT comp_pat(15)) XOR nll0llO))) AND (NOT ((NOT comp_pat(16)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(17)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(18)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(19)) XOR nll0O1i))); + n1001il <= (n100OiO AND ((comp_pat_porn AND n1001li) OR n1001iO)); + n1001iO <= ((((((((((NOT (comp_pat(10) XOR nll0l0O)) AND (NOT (comp_pat(11) XOR nll0lii))) AND (NOT (comp_pat(12) XOR nll0lil))) AND (NOT (comp_pat(13) XOR nll0liO))) AND (NOT (comp_pat(14) XOR nll0lli))) AND (NOT (comp_pat(15) XOR nll0lll))) AND (NOT (comp_pat(16) XOR nll0llO))) AND (NOT (comp_pat(17) XOR nll0lOi))) AND (NOT (comp_pat(18) XOR nll0lOl))) AND (NOT (comp_pat(19) XOR nll0lOO))); + n1001li <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0l0O)) AND (NOT ((NOT comp_pat(11)) XOR nll0lii))) AND (NOT ((NOT comp_pat(12)) XOR nll0lil))) AND (NOT ((NOT comp_pat(13)) XOR nll0liO))) AND (NOT ((NOT comp_pat(14)) XOR nll0lli))) AND (NOT ((NOT comp_pat(15)) XOR nll0lll))) AND (NOT ((NOT comp_pat(16)) XOR nll0llO))) AND (NOT ((NOT comp_pat(17)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(18)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(19)) XOR nll0lOO))); + n1001ll <= (n100OlO AND ((comp_pat_porn AND n1001Oi) OR n1001lO)); + n1001lO <= ((((((((((NOT (comp_pat(10) XOR nll0l0l)) AND (NOT (comp_pat(11) XOR nll0l0O))) AND (NOT (comp_pat(12) XOR nll0lii))) AND (NOT (comp_pat(13) XOR nll0lil))) AND (NOT (comp_pat(14) XOR nll0liO))) AND (NOT (comp_pat(15) XOR nll0lli))) AND (NOT (comp_pat(16) XOR nll0lll))) AND (NOT (comp_pat(17) XOR nll0llO))) AND (NOT (comp_pat(18) XOR nll0lOi))) AND (NOT (comp_pat(19) XOR nll0lOl))); + n1001Oi <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0l0l)) AND (NOT ((NOT comp_pat(11)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(12)) XOR nll0lii))) AND (NOT ((NOT comp_pat(13)) XOR nll0lil))) AND (NOT ((NOT comp_pat(14)) XOR nll0liO))) AND (NOT ((NOT comp_pat(15)) XOR nll0lli))) AND (NOT ((NOT comp_pat(16)) XOR nll0lll))) AND (NOT ((NOT comp_pat(17)) XOR nll0llO))) AND (NOT ((NOT comp_pat(18)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(19)) XOR nll0lOl))); + n1001Ol <= (n100OOO AND ((comp_pat_porn AND n10001i) OR n1001OO)); + n1001OO <= ((((((((((NOT (comp_pat(10) XOR nll0l0i)) AND (NOT (comp_pat(11) XOR nll0l0l))) AND (NOT (comp_pat(12) XOR nll0l0O))) AND (NOT (comp_pat(13) XOR nll0lii))) AND (NOT (comp_pat(14) XOR nll0lil))) AND (NOT (comp_pat(15) XOR nll0liO))) AND (NOT (comp_pat(16) XOR nll0lli))) AND (NOT (comp_pat(17) XOR nll0lll))) AND (NOT (comp_pat(18) XOR nll0llO))) AND (NOT (comp_pat(19) XOR nll0lOi))); + n100i0i <= ((((((((((NOT (comp_pat(0) XOR nll0lil)) AND (NOT (comp_pat(1) XOR nll0liO))) AND (NOT (comp_pat(2) XOR nll0lli))) AND (NOT (comp_pat(3) XOR nll0lll))) AND (NOT (comp_pat(4) XOR nll0llO))) AND (NOT (comp_pat(5) XOR nll0lOi))) AND (NOT (comp_pat(6) XOR nll0lOl))) AND (NOT (comp_pat(7) XOR nll0lOO))) AND (NOT (comp_pat(8) XOR nll0O1i))) AND (NOT (comp_pat(9) XOR nll0O1l))); + n100i0l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0lil)) AND (NOT ((NOT comp_pat(1)) XOR nll0liO))) AND (NOT ((NOT comp_pat(2)) XOR nll0lli))) AND (NOT ((NOT comp_pat(3)) XOR nll0lll))) AND (NOT ((NOT comp_pat(4)) XOR nll0llO))) AND (NOT ((NOT comp_pat(5)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(7)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(8)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(9)) XOR nll0O1l))); + n100i0O <= ((comp_pat_porn AND n100iil) OR n100iii); + n100i1i <= ((((((((((NOT (comp_pat(0) XOR nll0liO)) AND (NOT (comp_pat(1) XOR nll0lli))) AND (NOT (comp_pat(2) XOR nll0lll))) AND (NOT (comp_pat(3) XOR nll0llO))) AND (NOT (comp_pat(4) XOR nll0lOi))) AND (NOT (comp_pat(5) XOR nll0lOl))) AND (NOT (comp_pat(6) XOR nll0lOO))) AND (NOT (comp_pat(7) XOR nll0O1i))) AND (NOT (comp_pat(8) XOR nll0O1l))) AND (NOT (comp_pat(9) XOR nll0O1O))); + n100i1l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0liO)) AND (NOT ((NOT comp_pat(1)) XOR nll0lli))) AND (NOT ((NOT comp_pat(2)) XOR nll0lll))) AND (NOT ((NOT comp_pat(3)) XOR nll0llO))) AND (NOT ((NOT comp_pat(4)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(5)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(7)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(8)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(9)) XOR nll0O1O))); + n100i1O <= ((comp_pat_porn AND n100i0l) OR n100i0i); + n100iii <= ((((((((((NOT (comp_pat(0) XOR nll0lii)) AND (NOT (comp_pat(1) XOR nll0lil))) AND (NOT (comp_pat(2) XOR nll0liO))) AND (NOT (comp_pat(3) XOR nll0lli))) AND (NOT (comp_pat(4) XOR nll0lll))) AND (NOT (comp_pat(5) XOR nll0llO))) AND (NOT (comp_pat(6) XOR nll0lOi))) AND (NOT (comp_pat(7) XOR nll0lOl))) AND (NOT (comp_pat(8) XOR nll0lOO))) AND (NOT (comp_pat(9) XOR nll0O1i))); + n100iil <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0lii)) AND (NOT ((NOT comp_pat(1)) XOR nll0lil))) AND (NOT ((NOT comp_pat(2)) XOR nll0liO))) AND (NOT ((NOT comp_pat(3)) XOR nll0lli))) AND (NOT ((NOT comp_pat(4)) XOR nll0lll))) AND (NOT ((NOT comp_pat(5)) XOR nll0llO))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(7)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(8)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(9)) XOR nll0O1i))); + n100iiO <= ((comp_pat_porn AND n100ill) OR n100ili); + n100ili <= ((((((((((NOT (comp_pat(0) XOR nll0l0O)) AND (NOT (comp_pat(1) XOR nll0lii))) AND (NOT (comp_pat(2) XOR nll0lil))) AND (NOT (comp_pat(3) XOR nll0liO))) AND (NOT (comp_pat(4) XOR nll0lli))) AND (NOT (comp_pat(5) XOR nll0lll))) AND (NOT (comp_pat(6) XOR nll0llO))) AND (NOT (comp_pat(7) XOR nll0lOi))) AND (NOT (comp_pat(8) XOR nll0lOl))) AND (NOT (comp_pat(9) XOR nll0lOO))); + n100ill <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0l0O)) AND (NOT ((NOT comp_pat(1)) XOR nll0lii))) AND (NOT ((NOT comp_pat(2)) XOR nll0lil))) AND (NOT ((NOT comp_pat(3)) XOR nll0liO))) AND (NOT ((NOT comp_pat(4)) XOR nll0lli))) AND (NOT ((NOT comp_pat(5)) XOR nll0lll))) AND (NOT ((NOT comp_pat(6)) XOR nll0llO))) AND (NOT ((NOT comp_pat(7)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(8)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(9)) XOR nll0lOO))); + n100ilO <= ((comp_pat_porn AND n100iOl) OR n100iOi); + n100iOi <= ((((((((((NOT (comp_pat(0) XOR nll0l0l)) AND (NOT (comp_pat(1) XOR nll0l0O))) AND (NOT (comp_pat(2) XOR nll0lii))) AND (NOT (comp_pat(3) XOR nll0lil))) AND (NOT (comp_pat(4) XOR nll0liO))) AND (NOT (comp_pat(5) XOR nll0lli))) AND (NOT (comp_pat(6) XOR nll0lll))) AND (NOT (comp_pat(7) XOR nll0llO))) AND (NOT (comp_pat(8) XOR nll0lOi))) AND (NOT (comp_pat(9) XOR nll0lOl))); + n100iOl <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0l0l)) AND (NOT ((NOT comp_pat(1)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(2)) XOR nll0lii))) AND (NOT ((NOT comp_pat(3)) XOR nll0lil))) AND (NOT ((NOT comp_pat(4)) XOR nll0liO))) AND (NOT ((NOT comp_pat(5)) XOR nll0lli))) AND (NOT ((NOT comp_pat(6)) XOR nll0lll))) AND (NOT ((NOT comp_pat(7)) XOR nll0llO))) AND (NOT ((NOT comp_pat(8)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(9)) XOR nll0lOl))); + n100iOO <= ((comp_pat_porn AND n100l1l) OR n100l1i); + n100l0i <= ((((((((((NOT (comp_pat(0) XOR nll0l1O)) AND (NOT (comp_pat(1) XOR nll0l0i))) AND (NOT (comp_pat(2) XOR nll0l0l))) AND (NOT (comp_pat(3) XOR nll0l0O))) AND (NOT (comp_pat(4) XOR nll0lii))) AND (NOT (comp_pat(5) XOR nll0lil))) AND (NOT (comp_pat(6) XOR nll0liO))) AND (NOT (comp_pat(7) XOR nll0lli))) AND (NOT (comp_pat(8) XOR nll0lll))) AND (NOT (comp_pat(9) XOR nll0llO))); + n100l0l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0l1O)) AND (NOT ((NOT comp_pat(1)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(2)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(3)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(4)) XOR nll0lii))) AND (NOT ((NOT comp_pat(5)) XOR nll0lil))) AND (NOT ((NOT comp_pat(6)) XOR nll0liO))) AND (NOT ((NOT comp_pat(7)) XOR nll0lli))) AND (NOT ((NOT comp_pat(8)) XOR nll0lll))) AND (NOT ((NOT comp_pat(9)) XOR nll0llO))); + n100l0O <= ((comp_pat_porn AND n100lil) OR n100lii); + n100l1i <= ((((((((((NOT (comp_pat(0) XOR nll0l0i)) AND (NOT (comp_pat(1) XOR nll0l0l))) AND (NOT (comp_pat(2) XOR nll0l0O))) AND (NOT (comp_pat(3) XOR nll0lii))) AND (NOT (comp_pat(4) XOR nll0lil))) AND (NOT (comp_pat(5) XOR nll0liO))) AND (NOT (comp_pat(6) XOR nll0lli))) AND (NOT (comp_pat(7) XOR nll0lll))) AND (NOT (comp_pat(8) XOR nll0llO))) AND (NOT (comp_pat(9) XOR nll0lOi))); + n100l1l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0l0i)) AND (NOT ((NOT comp_pat(1)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(2)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(3)) XOR nll0lii))) AND (NOT ((NOT comp_pat(4)) XOR nll0lil))) AND (NOT ((NOT comp_pat(5)) XOR nll0liO))) AND (NOT ((NOT comp_pat(6)) XOR nll0lli))) AND (NOT ((NOT comp_pat(7)) XOR nll0lll))) AND (NOT ((NOT comp_pat(8)) XOR nll0llO))) AND (NOT ((NOT comp_pat(9)) XOR nll0lOi))); + n100l1O <= ((comp_pat_porn AND n100l0l) OR n100l0i); + n100lii <= ((((((((((NOT (comp_pat(0) XOR nll0l1l)) AND (NOT (comp_pat(1) XOR nll0l1O))) AND (NOT (comp_pat(2) XOR nll0l0i))) AND (NOT (comp_pat(3) XOR nll0l0l))) AND (NOT (comp_pat(4) XOR nll0l0O))) AND (NOT (comp_pat(5) XOR nll0lii))) AND (NOT (comp_pat(6) XOR nll0lil))) AND (NOT (comp_pat(7) XOR nll0liO))) AND (NOT (comp_pat(8) XOR nll0lli))) AND (NOT (comp_pat(9) XOR nll0lll))); + n100lil <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0l1l)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(2)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(3)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(4)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(5)) XOR nll0lii))) AND (NOT ((NOT comp_pat(6)) XOR nll0lil))) AND (NOT ((NOT comp_pat(7)) XOR nll0liO))) AND (NOT ((NOT comp_pat(8)) XOR nll0lli))) AND (NOT ((NOT comp_pat(9)) XOR nll0lll))); + n100liO <= ((comp_pat_porn AND n100lll) OR n100lli); + n100lli <= ((((((((((NOT (comp_pat(0) XOR nll0l1i)) AND (NOT (comp_pat(1) XOR nll0l1l))) AND (NOT (comp_pat(2) XOR nll0l1O))) AND (NOT (comp_pat(3) XOR nll0l0i))) AND (NOT (comp_pat(4) XOR nll0l0l))) AND (NOT (comp_pat(5) XOR nll0l0O))) AND (NOT (comp_pat(6) XOR nll0lii))) AND (NOT (comp_pat(7) XOR nll0lil))) AND (NOT (comp_pat(8) XOR nll0liO))) AND (NOT (comp_pat(9) XOR nll0lli))); + n100lll <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0l1i)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(3)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(4)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(5)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(6)) XOR nll0lii))) AND (NOT ((NOT comp_pat(7)) XOR nll0lil))) AND (NOT ((NOT comp_pat(8)) XOR nll0liO))) AND (NOT ((NOT comp_pat(9)) XOR nll0lli))); + n100llO <= ((comp_pat_porn AND n100lOl) OR n100lOi); + n100lOi <= ((((((((((NOT (comp_pat(0) XOR nll0iOO)) AND (NOT (comp_pat(1) XOR nll0l1i))) AND (NOT (comp_pat(2) XOR nll0l1l))) AND (NOT (comp_pat(3) XOR nll0l1O))) AND (NOT (comp_pat(4) XOR nll0l0i))) AND (NOT (comp_pat(5) XOR nll0l0l))) AND (NOT (comp_pat(6) XOR nll0l0O))) AND (NOT (comp_pat(7) XOR nll0lii))) AND (NOT (comp_pat(8) XOR nll0lil))) AND (NOT (comp_pat(9) XOR nll0liO))); + n100lOl <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0iOO)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(4)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(5)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(6)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(7)) XOR nll0lii))) AND (NOT ((NOT comp_pat(8)) XOR nll0lil))) AND (NOT ((NOT comp_pat(9)) XOR nll0liO))); + n100lOO <= ((comp_pat_porn AND n100O1l) OR n100O1i); + n100O0i <= ((((((((((NOT (comp_pat(0) XOR nll0iOi)) AND (NOT (comp_pat(1) XOR nll0iOl))) AND (NOT (comp_pat(2) XOR nll0iOO))) AND (NOT (comp_pat(3) XOR nll0l1i))) AND (NOT (comp_pat(4) XOR nll0l1l))) AND (NOT (comp_pat(5) XOR nll0l1O))) AND (NOT (comp_pat(6) XOR nll0l0i))) AND (NOT (comp_pat(7) XOR nll0l0l))) AND (NOT (comp_pat(8) XOR nll0l0O))) AND (NOT (comp_pat(9) XOR nll0lii))); + n100O0l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0iOi)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(6)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(7)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(8)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(9)) XOR nll0lii))); + n100O0O <= ((comp_pat_porn AND n100Oil) OR n100Oii); + n100O1i <= ((((((((((NOT (comp_pat(0) XOR nll0iOl)) AND (NOT (comp_pat(1) XOR nll0iOO))) AND (NOT (comp_pat(2) XOR nll0l1i))) AND (NOT (comp_pat(3) XOR nll0l1l))) AND (NOT (comp_pat(4) XOR nll0l1O))) AND (NOT (comp_pat(5) XOR nll0l0i))) AND (NOT (comp_pat(6) XOR nll0l0l))) AND (NOT (comp_pat(7) XOR nll0l0O))) AND (NOT (comp_pat(8) XOR nll0lii))) AND (NOT (comp_pat(9) XOR nll0lil))); + n100O1l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0iOl)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(5)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(6)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(7)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(8)) XOR nll0lii))) AND (NOT ((NOT comp_pat(9)) XOR nll0lil))); + n100O1O <= ((comp_pat_porn AND n100O0l) OR n100O0i); + n100Oii <= ((((((((((NOT (comp_pat(0) XOR nll0ilO)) AND (NOT (comp_pat(1) XOR nll0iOi))) AND (NOT (comp_pat(2) XOR nll0iOl))) AND (NOT (comp_pat(3) XOR nll0iOO))) AND (NOT (comp_pat(4) XOR nll0l1i))) AND (NOT (comp_pat(5) XOR nll0l1l))) AND (NOT (comp_pat(6) XOR nll0l1O))) AND (NOT (comp_pat(7) XOR nll0l0i))) AND (NOT (comp_pat(8) XOR nll0l0l))) AND (NOT (comp_pat(9) XOR nll0l0O))); + n100Oil <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0ilO)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(7)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(8)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(9)) XOR nll0l0O))); + n100OiO <= ((comp_pat_porn AND n100Oll) OR n100Oli); + n100Oli <= ((((((((((NOT (comp_pat(0) XOR nll0ill)) AND (NOT (comp_pat(1) XOR nll0ilO))) AND (NOT (comp_pat(2) XOR nll0iOi))) AND (NOT (comp_pat(3) XOR nll0iOl))) AND (NOT (comp_pat(4) XOR nll0iOO))) AND (NOT (comp_pat(5) XOR nll0l1i))) AND (NOT (comp_pat(6) XOR nll0l1l))) AND (NOT (comp_pat(7) XOR nll0l1O))) AND (NOT (comp_pat(8) XOR nll0l0i))) AND (NOT (comp_pat(9) XOR nll0l0l))); + n100Oll <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0ill)) AND (NOT ((NOT comp_pat(1)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(7)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(8)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(9)) XOR nll0l0l))); + n100OlO <= ((comp_pat_porn AND n100OOl) OR n100OOi); + n100OOi <= ((((((((((NOT (comp_pat(0) XOR nll0ili)) AND (NOT (comp_pat(1) XOR nll0ill))) AND (NOT (comp_pat(2) XOR nll0ilO))) AND (NOT (comp_pat(3) XOR nll0iOi))) AND (NOT (comp_pat(4) XOR nll0iOl))) AND (NOT (comp_pat(5) XOR nll0iOO))) AND (NOT (comp_pat(6) XOR nll0l1i))) AND (NOT (comp_pat(7) XOR nll0l1l))) AND (NOT (comp_pat(8) XOR nll0l1O))) AND (NOT (comp_pat(9) XOR nll0l0i))); + n100OOl <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0ili)) AND (NOT ((NOT comp_pat(1)) XOR nll0ill))) AND (NOT ((NOT comp_pat(2)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(7)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(8)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(9)) XOR nll0l0i))); + n100OOO <= ((comp_pat_porn AND n10i11l) OR n10i11i); + n10100i <= ((((((((((NOT (comp_pat(20) XOR nll0lOl)) AND (NOT (comp_pat(21) XOR nll0lOO))) AND (NOT (comp_pat(22) XOR nll0O1i))) AND (NOT (comp_pat(23) XOR nll0O1l))) AND (NOT (comp_pat(24) XOR nll0O1O))) AND (NOT (comp_pat(25) XOR nll0O0i))) AND (NOT (comp_pat(26) XOR nll0O0l))) AND (NOT (comp_pat(27) XOR nll0O0O))) AND (NOT (comp_pat(28) XOR nll0Oii))) AND (NOT (comp_pat(29) XOR nll0Oil))); + n10100l <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0lOl)) AND (NOT ((NOT comp_pat(21)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(22)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(23)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(24)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(25)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(26)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(27)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(28)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(29)) XOR nll0Oil))); + n10100O <= ((((((((((NOT (comp_pat(30) XOR nll0OiO)) AND (NOT (comp_pat(31) XOR nll0Oli))) AND (NOT (comp_pat(32) XOR nll0Oll))) AND (NOT (comp_pat(33) XOR nll0OlO))) AND (NOT (comp_pat(34) XOR nll0OOi))) AND (NOT (comp_pat(35) XOR nll0OOl))) AND (NOT (comp_pat(36) XOR nll0OOO))) AND (NOT (comp_pat(37) XOR nlli11i))) AND (NOT (comp_pat(38) XOR nlli11l))) AND (NOT (comp_pat(39) XOR nlli11O))); + n10101i <= ((((((((((NOT (comp_pat(30) XOR nll0Oli)) AND (NOT (comp_pat(31) XOR nll0Oll))) AND (NOT (comp_pat(32) XOR nll0OlO))) AND (NOT (comp_pat(33) XOR nll0OOi))) AND (NOT (comp_pat(34) XOR nll0OOl))) AND (NOT (comp_pat(35) XOR nll0OOO))) AND (NOT (comp_pat(36) XOR nlli11i))) AND (NOT (comp_pat(37) XOR nlli11l))) AND (NOT (comp_pat(38) XOR nlli11O))) AND (NOT (comp_pat(39) XOR nlli10i))); + n10101l <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0Oli)) AND (NOT ((NOT comp_pat(31)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(32)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(33)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(34)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(35)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(36)) XOR nlli11i))) AND (NOT ((NOT comp_pat(37)) XOR nlli11l))) AND (NOT ((NOT comp_pat(38)) XOR nlli11O))) AND (NOT ((NOT comp_pat(39)) XOR nlli10i))); + n10101O <= (n1001Ol AND (wire_w_lg_w_lg_comp_pat_porn4780w4781w(0) AND wire_w_lg_w_lg_comp_pat_porn4782w4783w(0))); + n1010ii <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0OiO)) AND (NOT ((NOT comp_pat(31)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(32)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(33)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(34)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(35)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(36)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(37)) XOR nlli11i))) AND (NOT ((NOT comp_pat(38)) XOR nlli11l))) AND (NOT ((NOT comp_pat(39)) XOR nlli11O))); + n1010il <= (n10001l AND (wire_w_lg_w_lg_comp_pat_porn4774w4775w(0) AND wire_w_lg_w_lg_comp_pat_porn4776w4777w(0))); + n1010iO <= ((((((((((NOT (comp_pat(20) XOR nll0lOi)) AND (NOT (comp_pat(21) XOR nll0lOl))) AND (NOT (comp_pat(22) XOR nll0lOO))) AND (NOT (comp_pat(23) XOR nll0O1i))) AND (NOT (comp_pat(24) XOR nll0O1l))) AND (NOT (comp_pat(25) XOR nll0O1O))) AND (NOT (comp_pat(26) XOR nll0O0i))) AND (NOT (comp_pat(27) XOR nll0O0l))) AND (NOT (comp_pat(28) XOR nll0O0O))) AND (NOT (comp_pat(29) XOR nll0Oii))); + n1010li <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0lOi)) AND (NOT ((NOT comp_pat(21)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(22)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(23)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(24)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(25)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(26)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(27)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(28)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(29)) XOR nll0Oii))); + n1010ll <= ((((((((((NOT (comp_pat(30) XOR nll0Oil)) AND (NOT (comp_pat(31) XOR nll0OiO))) AND (NOT (comp_pat(32) XOR nll0Oli))) AND (NOT (comp_pat(33) XOR nll0Oll))) AND (NOT (comp_pat(34) XOR nll0OlO))) AND (NOT (comp_pat(35) XOR nll0OOi))) AND (NOT (comp_pat(36) XOR nll0OOl))) AND (NOT (comp_pat(37) XOR nll0OOO))) AND (NOT (comp_pat(38) XOR nlli11i))) AND (NOT (comp_pat(39) XOR nlli11l))); + n1010lO <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0Oil)) AND (NOT ((NOT comp_pat(31)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(32)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(33)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(34)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(35)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(36)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(37)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(38)) XOR nlli11i))) AND (NOT ((NOT comp_pat(39)) XOR nlli11l))); + n1010Oi <= (n10000l AND (wire_w_lg_w_lg_comp_pat_porn4768w4769w(0) AND wire_w_lg_w_lg_comp_pat_porn4770w4771w(0))); + n1010Ol <= ((((((((((NOT (comp_pat(20) XOR nll0llO)) AND (NOT (comp_pat(21) XOR nll0lOi))) AND (NOT (comp_pat(22) XOR nll0lOl))) AND (NOT (comp_pat(23) XOR nll0lOO))) AND (NOT (comp_pat(24) XOR nll0O1i))) AND (NOT (comp_pat(25) XOR nll0O1l))) AND (NOT (comp_pat(26) XOR nll0O1O))) AND (NOT (comp_pat(27) XOR nll0O0i))) AND (NOT (comp_pat(28) XOR nll0O0l))) AND (NOT (comp_pat(29) XOR nll0O0O))); + n1010OO <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0llO)) AND (NOT ((NOT comp_pat(21)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(22)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(23)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(24)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(25)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(26)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(27)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(28)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(29)) XOR nll0O0O))); + n10110i <= ((((((((((NOT (comp_pat(20) XOR nll0O1l)) AND (NOT (comp_pat(21) XOR nll0O1O))) AND (NOT (comp_pat(22) XOR nll0O0i))) AND (NOT (comp_pat(23) XOR nll0O0l))) AND (NOT (comp_pat(24) XOR nll0O0O))) AND (NOT (comp_pat(25) XOR nll0Oii))) AND (NOT (comp_pat(26) XOR nll0Oil))) AND (NOT (comp_pat(27) XOR nll0OiO))) AND (NOT (comp_pat(28) XOR nll0Oli))) AND (NOT (comp_pat(29) XOR nll0Oll))); + n10110l <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0O1l)) AND (NOT ((NOT comp_pat(21)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(22)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(23)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(24)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(25)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(26)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(27)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(28)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(29)) XOR nll0Oll))); + n10110O <= ((((((((((NOT (comp_pat(30) XOR nll0OlO)) AND (NOT (comp_pat(31) XOR nll0OOi))) AND (NOT (comp_pat(32) XOR nll0OOl))) AND (NOT (comp_pat(33) XOR nll0OOO))) AND (NOT (comp_pat(34) XOR nlli11i))) AND (NOT (comp_pat(35) XOR nlli11l))) AND (NOT (comp_pat(36) XOR nlli11O))) AND (NOT (comp_pat(37) XOR nlli10i))) AND (NOT (comp_pat(38) XOR nlli10l))) AND (NOT (comp_pat(39) XOR nlli10O))); + n10111i <= ((((((((((NOT (comp_pat(30) XOR nll0OOi)) AND (NOT (comp_pat(31) XOR nll0OOl))) AND (NOT (comp_pat(32) XOR nll0OOO))) AND (NOT (comp_pat(33) XOR nlli11i))) AND (NOT (comp_pat(34) XOR nlli11l))) AND (NOT (comp_pat(35) XOR nlli11O))) AND (NOT (comp_pat(36) XOR nlli10i))) AND (NOT (comp_pat(37) XOR nlli10l))) AND (NOT (comp_pat(38) XOR nlli10O))) AND (NOT (comp_pat(39) XOR nlli1ii))); + n10111l <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0OOi)) AND (NOT ((NOT comp_pat(31)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(32)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(33)) XOR nlli11i))) AND (NOT ((NOT comp_pat(34)) XOR nlli11l))) AND (NOT ((NOT comp_pat(35)) XOR nlli11O))) AND (NOT ((NOT comp_pat(36)) XOR nlli10i))) AND (NOT ((NOT comp_pat(37)) XOR nlli10l))) AND (NOT ((NOT comp_pat(38)) XOR nlli10O))) AND (NOT ((NOT comp_pat(39)) XOR nlli1ii))); + n10111O <= (n10010l AND (wire_w_lg_w_lg_comp_pat_porn4798w4799w(0) AND wire_w_lg_w_lg_comp_pat_porn4800w4801w(0))); + n1011ii <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0OlO)) AND (NOT ((NOT comp_pat(31)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(32)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(33)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(34)) XOR nlli11i))) AND (NOT ((NOT comp_pat(35)) XOR nlli11l))) AND (NOT ((NOT comp_pat(36)) XOR nlli11O))) AND (NOT ((NOT comp_pat(37)) XOR nlli10i))) AND (NOT ((NOT comp_pat(38)) XOR nlli10l))) AND (NOT ((NOT comp_pat(39)) XOR nlli10O))); + n1011il <= (n1001il AND (wire_w_lg_w_lg_comp_pat_porn4792w4793w(0) AND wire_w_lg_w_lg_comp_pat_porn4794w4795w(0))); + n1011iO <= ((((((((((NOT (comp_pat(20) XOR nll0O1i)) AND (NOT (comp_pat(21) XOR nll0O1l))) AND (NOT (comp_pat(22) XOR nll0O1O))) AND (NOT (comp_pat(23) XOR nll0O0i))) AND (NOT (comp_pat(24) XOR nll0O0l))) AND (NOT (comp_pat(25) XOR nll0O0O))) AND (NOT (comp_pat(26) XOR nll0Oii))) AND (NOT (comp_pat(27) XOR nll0Oil))) AND (NOT (comp_pat(28) XOR nll0OiO))) AND (NOT (comp_pat(29) XOR nll0Oli))); + n1011li <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0O1i)) AND (NOT ((NOT comp_pat(21)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(22)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(23)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(24)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(25)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(26)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(27)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(28)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(29)) XOR nll0Oli))); + n1011ll <= ((((((((((NOT (comp_pat(30) XOR nll0Oll)) AND (NOT (comp_pat(31) XOR nll0OlO))) AND (NOT (comp_pat(32) XOR nll0OOi))) AND (NOT (comp_pat(33) XOR nll0OOl))) AND (NOT (comp_pat(34) XOR nll0OOO))) AND (NOT (comp_pat(35) XOR nlli11i))) AND (NOT (comp_pat(36) XOR nlli11l))) AND (NOT (comp_pat(37) XOR nlli11O))) AND (NOT (comp_pat(38) XOR nlli10i))) AND (NOT (comp_pat(39) XOR nlli10l))); + n1011lO <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0Oll)) AND (NOT ((NOT comp_pat(31)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(32)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(33)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(34)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(35)) XOR nlli11i))) AND (NOT ((NOT comp_pat(36)) XOR nlli11l))) AND (NOT ((NOT comp_pat(37)) XOR nlli11O))) AND (NOT ((NOT comp_pat(38)) XOR nlli10i))) AND (NOT ((NOT comp_pat(39)) XOR nlli10l))); + n1011Oi <= (n1001ll AND (wire_w_lg_w_lg_comp_pat_porn4786w4787w(0) AND wire_w_lg_w_lg_comp_pat_porn4788w4789w(0))); + n1011Ol <= ((((((((((NOT (comp_pat(20) XOR nll0lOO)) AND (NOT (comp_pat(21) XOR nll0O1i))) AND (NOT (comp_pat(22) XOR nll0O1l))) AND (NOT (comp_pat(23) XOR nll0O1O))) AND (NOT (comp_pat(24) XOR nll0O0i))) AND (NOT (comp_pat(25) XOR nll0O0l))) AND (NOT (comp_pat(26) XOR nll0O0O))) AND (NOT (comp_pat(27) XOR nll0Oii))) AND (NOT (comp_pat(28) XOR nll0Oil))) AND (NOT (comp_pat(29) XOR nll0OiO))); + n1011OO <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0lOO)) AND (NOT ((NOT comp_pat(21)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(22)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(23)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(24)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(25)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(26)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(27)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(28)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(29)) XOR nll0OiO))); + n101i0i <= ((((((((((NOT (comp_pat(20) XOR nll0lll)) AND (NOT (comp_pat(21) XOR nll0llO))) AND (NOT (comp_pat(22) XOR nll0lOi))) AND (NOT (comp_pat(23) XOR nll0lOl))) AND (NOT (comp_pat(24) XOR nll0lOO))) AND (NOT (comp_pat(25) XOR nll0O1i))) AND (NOT (comp_pat(26) XOR nll0O1l))) AND (NOT (comp_pat(27) XOR nll0O1O))) AND (NOT (comp_pat(28) XOR nll0O0i))) AND (NOT (comp_pat(29) XOR nll0O0l))); + n101i0l <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0lll)) AND (NOT ((NOT comp_pat(21)) XOR nll0llO))) AND (NOT ((NOT comp_pat(22)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(23)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(24)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(25)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(26)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(27)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(28)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(29)) XOR nll0O0l))); + n101i0O <= ((((((((((NOT (comp_pat(30) XOR nll0O0O)) AND (NOT (comp_pat(31) XOR nll0Oii))) AND (NOT (comp_pat(32) XOR nll0Oil))) AND (NOT (comp_pat(33) XOR nll0OiO))) AND (NOT (comp_pat(34) XOR nll0Oli))) AND (NOT (comp_pat(35) XOR nll0Oll))) AND (NOT (comp_pat(36) XOR nll0OlO))) AND (NOT (comp_pat(37) XOR nll0OOi))) AND (NOT (comp_pat(38) XOR nll0OOl))) AND (NOT (comp_pat(39) XOR nll0OOO))); + n101i1i <= ((((((((((NOT (comp_pat(30) XOR nll0Oii)) AND (NOT (comp_pat(31) XOR nll0Oil))) AND (NOT (comp_pat(32) XOR nll0OiO))) AND (NOT (comp_pat(33) XOR nll0Oli))) AND (NOT (comp_pat(34) XOR nll0Oll))) AND (NOT (comp_pat(35) XOR nll0OlO))) AND (NOT (comp_pat(36) XOR nll0OOi))) AND (NOT (comp_pat(37) XOR nll0OOl))) AND (NOT (comp_pat(38) XOR nll0OOO))) AND (NOT (comp_pat(39) XOR nlli11i))); + n101i1l <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0Oii)) AND (NOT ((NOT comp_pat(31)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(32)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(33)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(34)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(35)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(36)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(37)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(38)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(39)) XOR nlli11i))); + n101i1O <= (n1000il AND (wire_w_lg_w_lg_comp_pat_porn4762w4763w(0) AND wire_w_lg_w_lg_comp_pat_porn4764w4765w(0))); + n101iii <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0O0O)) AND (NOT ((NOT comp_pat(31)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(32)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(33)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(34)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(35)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(36)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(37)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(38)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(39)) XOR nll0OOO))); + n101iil <= (n1000ll AND (wire_w_lg_w_lg_comp_pat_porn4756w4757w(0) AND wire_w_lg_w_lg_comp_pat_porn4758w4759w(0))); + n101iiO <= ((((((((((NOT (comp_pat(20) XOR nll0lli)) AND (NOT (comp_pat(21) XOR nll0lll))) AND (NOT (comp_pat(22) XOR nll0llO))) AND (NOT (comp_pat(23) XOR nll0lOi))) AND (NOT (comp_pat(24) XOR nll0lOl))) AND (NOT (comp_pat(25) XOR nll0lOO))) AND (NOT (comp_pat(26) XOR nll0O1i))) AND (NOT (comp_pat(27) XOR nll0O1l))) AND (NOT (comp_pat(28) XOR nll0O1O))) AND (NOT (comp_pat(29) XOR nll0O0i))); + n101ili <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0lli)) AND (NOT ((NOT comp_pat(21)) XOR nll0lll))) AND (NOT ((NOT comp_pat(22)) XOR nll0llO))) AND (NOT ((NOT comp_pat(23)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(24)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(25)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(26)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(27)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(28)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(29)) XOR nll0O0i))); + n101ill <= ((((((((((NOT (comp_pat(30) XOR nll0O0l)) AND (NOT (comp_pat(31) XOR nll0O0O))) AND (NOT (comp_pat(32) XOR nll0Oii))) AND (NOT (comp_pat(33) XOR nll0Oil))) AND (NOT (comp_pat(34) XOR nll0OiO))) AND (NOT (comp_pat(35) XOR nll0Oli))) AND (NOT (comp_pat(36) XOR nll0Oll))) AND (NOT (comp_pat(37) XOR nll0OlO))) AND (NOT (comp_pat(38) XOR nll0OOi))) AND (NOT (comp_pat(39) XOR nll0OOl))); + n101ilO <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0O0l)) AND (NOT ((NOT comp_pat(31)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(32)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(33)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(34)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(35)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(36)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(37)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(38)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(39)) XOR nll0OOl))); + n101iOi <= (((((((((((((((((((n1000ll OR n1000il) OR n10000l) OR n10001l) OR n1001Ol) OR n1001ll) OR n1001il) OR n10010l) OR n10011l) OR n101OOl) OR n101Oll) OR n101Oil) OR n101O0l) OR n101O1l) OR n101lOl) OR n101lll) OR n101lil) OR n101l0l) OR n101l1l) OR n101iOl); + n101iOl <= (n1000OO AND ((comp_pat_porn AND n101l1i) OR n101iOO)); + n101iOO <= ((((((((((NOT (comp_pat(10) XOR nll0O0i)) AND (NOT (comp_pat(11) XOR nll0O0l))) AND (NOT (comp_pat(12) XOR nll0O0O))) AND (NOT (comp_pat(13) XOR nll0Oii))) AND (NOT (comp_pat(14) XOR nll0Oil))) AND (NOT (comp_pat(15) XOR nll0OiO))) AND (NOT (comp_pat(16) XOR nll0Oli))) AND (NOT (comp_pat(17) XOR nll0Oll))) AND (NOT (comp_pat(18) XOR nll0OlO))) AND (NOT (comp_pat(19) XOR nll0OOi))); + n101l0i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0O1O)) AND (NOT ((NOT comp_pat(11)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(12)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(13)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(14)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(15)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(16)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(17)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(18)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(19)) XOR nll0OlO))); + n101l0l <= (n100i0O AND ((comp_pat_porn AND n101lii) OR n101l0O)); + n101l0O <= ((((((((((NOT (comp_pat(10) XOR nll0O1l)) AND (NOT (comp_pat(11) XOR nll0O1O))) AND (NOT (comp_pat(12) XOR nll0O0i))) AND (NOT (comp_pat(13) XOR nll0O0l))) AND (NOT (comp_pat(14) XOR nll0O0O))) AND (NOT (comp_pat(15) XOR nll0Oii))) AND (NOT (comp_pat(16) XOR nll0Oil))) AND (NOT (comp_pat(17) XOR nll0OiO))) AND (NOT (comp_pat(18) XOR nll0Oli))) AND (NOT (comp_pat(19) XOR nll0Oll))); + n101l1i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0O0i)) AND (NOT ((NOT comp_pat(11)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(12)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(13)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(14)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(15)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(16)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(17)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(18)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(19)) XOR nll0OOi))); + n101l1l <= (n100i1O AND ((comp_pat_porn AND n101l0i) OR n101l1O)); + n101l1O <= ((((((((((NOT (comp_pat(10) XOR nll0O1O)) AND (NOT (comp_pat(11) XOR nll0O0i))) AND (NOT (comp_pat(12) XOR nll0O0l))) AND (NOT (comp_pat(13) XOR nll0O0O))) AND (NOT (comp_pat(14) XOR nll0Oii))) AND (NOT (comp_pat(15) XOR nll0Oil))) AND (NOT (comp_pat(16) XOR nll0OiO))) AND (NOT (comp_pat(17) XOR nll0Oli))) AND (NOT (comp_pat(18) XOR nll0Oll))) AND (NOT (comp_pat(19) XOR nll0OlO))); + n101lii <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0O1l)) AND (NOT ((NOT comp_pat(11)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(12)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(13)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(14)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(15)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(16)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(17)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(18)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(19)) XOR nll0Oll))); + n101lil <= (n100iiO AND ((comp_pat_porn AND n101lli) OR n101liO)); + n101liO <= ((((((((((NOT (comp_pat(10) XOR nll0O1i)) AND (NOT (comp_pat(11) XOR nll0O1l))) AND (NOT (comp_pat(12) XOR nll0O1O))) AND (NOT (comp_pat(13) XOR nll0O0i))) AND (NOT (comp_pat(14) XOR nll0O0l))) AND (NOT (comp_pat(15) XOR nll0O0O))) AND (NOT (comp_pat(16) XOR nll0Oii))) AND (NOT (comp_pat(17) XOR nll0Oil))) AND (NOT (comp_pat(18) XOR nll0OiO))) AND (NOT (comp_pat(19) XOR nll0Oli))); + n101lli <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0O1i)) AND (NOT ((NOT comp_pat(11)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(12)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(13)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(14)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(15)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(16)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(17)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(18)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(19)) XOR nll0Oli))); + n101lll <= (n100ilO AND ((comp_pat_porn AND n101lOi) OR n101llO)); + n101llO <= ((((((((((NOT (comp_pat(10) XOR nll0lOO)) AND (NOT (comp_pat(11) XOR nll0O1i))) AND (NOT (comp_pat(12) XOR nll0O1l))) AND (NOT (comp_pat(13) XOR nll0O1O))) AND (NOT (comp_pat(14) XOR nll0O0i))) AND (NOT (comp_pat(15) XOR nll0O0l))) AND (NOT (comp_pat(16) XOR nll0O0O))) AND (NOT (comp_pat(17) XOR nll0Oii))) AND (NOT (comp_pat(18) XOR nll0Oil))) AND (NOT (comp_pat(19) XOR nll0OiO))); + n101lOi <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0lOO)) AND (NOT ((NOT comp_pat(11)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(12)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(13)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(14)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(15)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(16)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(17)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(18)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(19)) XOR nll0OiO))); + n101lOl <= (n100iOO AND ((comp_pat_porn AND n101O1i) OR n101lOO)); + n101lOO <= ((((((((((NOT (comp_pat(10) XOR nll0lOl)) AND (NOT (comp_pat(11) XOR nll0lOO))) AND (NOT (comp_pat(12) XOR nll0O1i))) AND (NOT (comp_pat(13) XOR nll0O1l))) AND (NOT (comp_pat(14) XOR nll0O1O))) AND (NOT (comp_pat(15) XOR nll0O0i))) AND (NOT (comp_pat(16) XOR nll0O0l))) AND (NOT (comp_pat(17) XOR nll0O0O))) AND (NOT (comp_pat(18) XOR nll0Oii))) AND (NOT (comp_pat(19) XOR nll0Oil))); + n101O0i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0lOi)) AND (NOT ((NOT comp_pat(11)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(12)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(13)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(14)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(15)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(16)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(17)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(18)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(19)) XOR nll0Oii))); + n101O0l <= (n100l0O AND ((comp_pat_porn AND n101Oii) OR n101O0O)); + n101O0O <= ((((((((((NOT (comp_pat(10) XOR nll0llO)) AND (NOT (comp_pat(11) XOR nll0lOi))) AND (NOT (comp_pat(12) XOR nll0lOl))) AND (NOT (comp_pat(13) XOR nll0lOO))) AND (NOT (comp_pat(14) XOR nll0O1i))) AND (NOT (comp_pat(15) XOR nll0O1l))) AND (NOT (comp_pat(16) XOR nll0O1O))) AND (NOT (comp_pat(17) XOR nll0O0i))) AND (NOT (comp_pat(18) XOR nll0O0l))) AND (NOT (comp_pat(19) XOR nll0O0O))); + n101O1i <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0lOl)) AND (NOT ((NOT comp_pat(11)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(12)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(13)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(14)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(15)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(16)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(17)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(18)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(19)) XOR nll0Oil))); + n101O1l <= (n100l1O AND ((comp_pat_porn AND n101O0i) OR n101O1O)); + n101O1O <= ((((((((((NOT (comp_pat(10) XOR nll0lOi)) AND (NOT (comp_pat(11) XOR nll0lOl))) AND (NOT (comp_pat(12) XOR nll0lOO))) AND (NOT (comp_pat(13) XOR nll0O1i))) AND (NOT (comp_pat(14) XOR nll0O1l))) AND (NOT (comp_pat(15) XOR nll0O1O))) AND (NOT (comp_pat(16) XOR nll0O0i))) AND (NOT (comp_pat(17) XOR nll0O0l))) AND (NOT (comp_pat(18) XOR nll0O0O))) AND (NOT (comp_pat(19) XOR nll0Oii))); + n101Oii <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0llO)) AND (NOT ((NOT comp_pat(11)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(12)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(13)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(14)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(15)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(16)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(17)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(18)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(19)) XOR nll0O0O))); + n101Oil <= (n100liO AND ((comp_pat_porn AND n101Oli) OR n101OiO)); + n101OiO <= ((((((((((NOT (comp_pat(10) XOR nll0lll)) AND (NOT (comp_pat(11) XOR nll0llO))) AND (NOT (comp_pat(12) XOR nll0lOi))) AND (NOT (comp_pat(13) XOR nll0lOl))) AND (NOT (comp_pat(14) XOR nll0lOO))) AND (NOT (comp_pat(15) XOR nll0O1i))) AND (NOT (comp_pat(16) XOR nll0O1l))) AND (NOT (comp_pat(17) XOR nll0O1O))) AND (NOT (comp_pat(18) XOR nll0O0i))) AND (NOT (comp_pat(19) XOR nll0O0l))); + n101Oli <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0lll)) AND (NOT ((NOT comp_pat(11)) XOR nll0llO))) AND (NOT ((NOT comp_pat(12)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(13)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(14)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(15)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(16)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(17)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(18)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(19)) XOR nll0O0l))); + n101Oll <= (n100llO AND ((comp_pat_porn AND n101OOi) OR n101OlO)); + n101OlO <= ((((((((((NOT (comp_pat(10) XOR nll0lli)) AND (NOT (comp_pat(11) XOR nll0lll))) AND (NOT (comp_pat(12) XOR nll0llO))) AND (NOT (comp_pat(13) XOR nll0lOi))) AND (NOT (comp_pat(14) XOR nll0lOl))) AND (NOT (comp_pat(15) XOR nll0lOO))) AND (NOT (comp_pat(16) XOR nll0O1i))) AND (NOT (comp_pat(17) XOR nll0O1l))) AND (NOT (comp_pat(18) XOR nll0O1O))) AND (NOT (comp_pat(19) XOR nll0O0i))); + n101OOi <= ((((((((((NOT ((NOT comp_pat(10)) XOR nll0lli)) AND (NOT ((NOT comp_pat(11)) XOR nll0lll))) AND (NOT ((NOT comp_pat(12)) XOR nll0llO))) AND (NOT ((NOT comp_pat(13)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(14)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(15)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(16)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(17)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(18)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(19)) XOR nll0O0i))); + n101OOl <= (n100lOO AND ((comp_pat_porn AND n10011i) OR n101OOO)); + n101OOO <= ((((((((((NOT (comp_pat(10) XOR nll0liO)) AND (NOT (comp_pat(11) XOR nll0lli))) AND (NOT (comp_pat(12) XOR nll0lll))) AND (NOT (comp_pat(13) XOR nll0llO))) AND (NOT (comp_pat(14) XOR nll0lOi))) AND (NOT (comp_pat(15) XOR nll0lOl))) AND (NOT (comp_pat(16) XOR nll0lOO))) AND (NOT (comp_pat(17) XOR nll0O1i))) AND (NOT (comp_pat(18) XOR nll0O1l))) AND (NOT (comp_pat(19) XOR nll0O1O))); + n10i00i <= ((comp_pat_porn AND n10i00O) OR n10i00l); + n10i00l <= (((((((NOT (comp_pat(0) XOR nll0lil)) AND (NOT (comp_pat(1) XOR nll0liO))) AND (NOT (comp_pat(2) XOR nll0lli))) AND (NOT (comp_pat(3) XOR nll0lll))) AND (NOT (comp_pat(4) XOR nll0llO))) AND (NOT (comp_pat(5) XOR nll0lOi))) AND (NOT (comp_pat(6) XOR nll0lOl))); + n10i00O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0lil)) AND (NOT ((NOT comp_pat(1)) XOR nll0liO))) AND (NOT ((NOT comp_pat(2)) XOR nll0lli))) AND (NOT ((NOT comp_pat(3)) XOR nll0lll))) AND (NOT ((NOT comp_pat(4)) XOR nll0llO))) AND (NOT ((NOT comp_pat(5)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOl))); + n10i01i <= ((comp_pat_porn AND n10i01O) OR n10i01l); + n10i01l <= (((((((NOT (comp_pat(0) XOR nll0liO)) AND (NOT (comp_pat(1) XOR nll0lli))) AND (NOT (comp_pat(2) XOR nll0lll))) AND (NOT (comp_pat(3) XOR nll0llO))) AND (NOT (comp_pat(4) XOR nll0lOi))) AND (NOT (comp_pat(5) XOR nll0lOl))) AND (NOT (comp_pat(6) XOR nll0lOO))); + n10i01O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0liO)) AND (NOT ((NOT comp_pat(1)) XOR nll0lli))) AND (NOT ((NOT comp_pat(2)) XOR nll0lll))) AND (NOT ((NOT comp_pat(3)) XOR nll0llO))) AND (NOT ((NOT comp_pat(4)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(5)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOO))); + n10i0ii <= ((comp_pat_porn AND n10i0iO) OR n10i0il); + n10i0il <= (((((((NOT (comp_pat(0) XOR nll0lii)) AND (NOT (comp_pat(1) XOR nll0lil))) AND (NOT (comp_pat(2) XOR nll0liO))) AND (NOT (comp_pat(3) XOR nll0lli))) AND (NOT (comp_pat(4) XOR nll0lll))) AND (NOT (comp_pat(5) XOR nll0llO))) AND (NOT (comp_pat(6) XOR nll0lOi))); + n10i0iO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0lii)) AND (NOT ((NOT comp_pat(1)) XOR nll0lil))) AND (NOT ((NOT comp_pat(2)) XOR nll0liO))) AND (NOT ((NOT comp_pat(3)) XOR nll0lli))) AND (NOT ((NOT comp_pat(4)) XOR nll0lll))) AND (NOT ((NOT comp_pat(5)) XOR nll0llO))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOi))); + n10i0li <= ((comp_pat_porn AND n10i0lO) OR n10i0ll); + n10i0ll <= (((((((NOT (comp_pat(0) XOR nll0l0O)) AND (NOT (comp_pat(1) XOR nll0lii))) AND (NOT (comp_pat(2) XOR nll0lil))) AND (NOT (comp_pat(3) XOR nll0liO))) AND (NOT (comp_pat(4) XOR nll0lli))) AND (NOT (comp_pat(5) XOR nll0lll))) AND (NOT (comp_pat(6) XOR nll0llO))); + n10i0lO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0l0O)) AND (NOT ((NOT comp_pat(1)) XOR nll0lii))) AND (NOT ((NOT comp_pat(2)) XOR nll0lil))) AND (NOT ((NOT comp_pat(3)) XOR nll0liO))) AND (NOT ((NOT comp_pat(4)) XOR nll0lli))) AND (NOT ((NOT comp_pat(5)) XOR nll0lll))) AND (NOT ((NOT comp_pat(6)) XOR nll0llO))); + n10i0Oi <= ((comp_pat_porn AND n10i0OO) OR n10i0Ol); + n10i0Ol <= (((((((NOT (comp_pat(0) XOR nll0l0l)) AND (NOT (comp_pat(1) XOR nll0l0O))) AND (NOT (comp_pat(2) XOR nll0lii))) AND (NOT (comp_pat(3) XOR nll0lil))) AND (NOT (comp_pat(4) XOR nll0liO))) AND (NOT (comp_pat(5) XOR nll0lli))) AND (NOT (comp_pat(6) XOR nll0lll))); + n10i0OO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0l0l)) AND (NOT ((NOT comp_pat(1)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(2)) XOR nll0lii))) AND (NOT ((NOT comp_pat(3)) XOR nll0lil))) AND (NOT ((NOT comp_pat(4)) XOR nll0liO))) AND (NOT ((NOT comp_pat(5)) XOR nll0lli))) AND (NOT ((NOT comp_pat(6)) XOR nll0lll))); + n10i10i <= ((((((((((NOT (comp_pat(0) XOR nll0iil)) AND (NOT (comp_pat(1) XOR nll0iiO))) AND (NOT (comp_pat(2) XOR nll0ili))) AND (NOT (comp_pat(3) XOR nll0ill))) AND (NOT (comp_pat(4) XOR nll0ilO))) AND (NOT (comp_pat(5) XOR nll0iOi))) AND (NOT (comp_pat(6) XOR nll0iOl))) AND (NOT (comp_pat(7) XOR nll0iOO))) AND (NOT (comp_pat(8) XOR nll0l1i))) AND (NOT (comp_pat(9) XOR nll0l1l))); + n10i10l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0iil)) AND (NOT ((NOT comp_pat(1)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(2)) XOR nll0ili))) AND (NOT ((NOT comp_pat(3)) XOR nll0ill))) AND (NOT ((NOT comp_pat(4)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(7)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(8)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(9)) XOR nll0l1l))); + n10i10O <= ((comp_pat_porn AND n10i1il) OR n10i1ii); + n10i11i <= ((((((((((NOT (comp_pat(0) XOR nll0iiO)) AND (NOT (comp_pat(1) XOR nll0ili))) AND (NOT (comp_pat(2) XOR nll0ill))) AND (NOT (comp_pat(3) XOR nll0ilO))) AND (NOT (comp_pat(4) XOR nll0iOi))) AND (NOT (comp_pat(5) XOR nll0iOl))) AND (NOT (comp_pat(6) XOR nll0iOO))) AND (NOT (comp_pat(7) XOR nll0l1i))) AND (NOT (comp_pat(8) XOR nll0l1l))) AND (NOT (comp_pat(9) XOR nll0l1O))); + n10i11l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0iiO)) AND (NOT ((NOT comp_pat(1)) XOR nll0ili))) AND (NOT ((NOT comp_pat(2)) XOR nll0ill))) AND (NOT ((NOT comp_pat(3)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(7)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(8)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(9)) XOR nll0l1O))); + n10i11O <= ((comp_pat_porn AND n10i10l) OR n10i10i); + n10i1ii <= ((((((((((NOT (comp_pat(0) XOR nll0iii)) AND (NOT (comp_pat(1) XOR nll0iil))) AND (NOT (comp_pat(2) XOR nll0iiO))) AND (NOT (comp_pat(3) XOR nll0ili))) AND (NOT (comp_pat(4) XOR nll0ill))) AND (NOT (comp_pat(5) XOR nll0ilO))) AND (NOT (comp_pat(6) XOR nll0iOi))) AND (NOT (comp_pat(7) XOR nll0iOl))) AND (NOT (comp_pat(8) XOR nll0iOO))) AND (NOT (comp_pat(9) XOR nll0l1i))); + n10i1il <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0iii)) AND (NOT ((NOT comp_pat(1)) XOR nll0iil))) AND (NOT ((NOT comp_pat(2)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(3)) XOR nll0ili))) AND (NOT ((NOT comp_pat(4)) XOR nll0ill))) AND (NOT ((NOT comp_pat(5)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(7)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(8)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(9)) XOR nll0l1i))); + n10i1iO <= ((comp_pat_porn AND n10i1ll) OR n10i1li); + n10i1li <= ((((((((((NOT (comp_pat(0) XOR nll0i0O)) AND (NOT (comp_pat(1) XOR nll0iii))) AND (NOT (comp_pat(2) XOR nll0iil))) AND (NOT (comp_pat(3) XOR nll0iiO))) AND (NOT (comp_pat(4) XOR nll0ili))) AND (NOT (comp_pat(5) XOR nll0ill))) AND (NOT (comp_pat(6) XOR nll0ilO))) AND (NOT (comp_pat(7) XOR nll0iOi))) AND (NOT (comp_pat(8) XOR nll0iOl))) AND (NOT (comp_pat(9) XOR nll0iOO))); + n10i1ll <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0i0O)) AND (NOT ((NOT comp_pat(1)) XOR nll0iii))) AND (NOT ((NOT comp_pat(2)) XOR nll0iil))) AND (NOT ((NOT comp_pat(3)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(4)) XOR nll0ili))) AND (NOT ((NOT comp_pat(5)) XOR nll0ill))) AND (NOT ((NOT comp_pat(6)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(7)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(8)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(9)) XOR nll0iOO))); + n10i1lO <= ((comp_pat_porn AND n10i1Ol) OR n10i1Oi); + n10i1Oi <= ((((((((((NOT (comp_pat(0) XOR nll0i0l)) AND (NOT (comp_pat(1) XOR nll0i0O))) AND (NOT (comp_pat(2) XOR nll0iii))) AND (NOT (comp_pat(3) XOR nll0iil))) AND (NOT (comp_pat(4) XOR nll0iiO))) AND (NOT (comp_pat(5) XOR nll0ili))) AND (NOT (comp_pat(6) XOR nll0ill))) AND (NOT (comp_pat(7) XOR nll0ilO))) AND (NOT (comp_pat(8) XOR nll0iOi))) AND (NOT (comp_pat(9) XOR nll0iOl))); + n10i1Ol <= ((((((((((NOT ((NOT comp_pat(0)) XOR nll0i0l)) AND (NOT ((NOT comp_pat(1)) XOR nll0i0O))) AND (NOT ((NOT comp_pat(2)) XOR nll0iii))) AND (NOT ((NOT comp_pat(3)) XOR nll0iil))) AND (NOT ((NOT comp_pat(4)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(5)) XOR nll0ili))) AND (NOT ((NOT comp_pat(6)) XOR nll0ill))) AND (NOT ((NOT comp_pat(7)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(8)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(9)) XOR nll0iOl))); + n10i1OO <= (((((((((((((((((((n10iOOi OR n10iOli) OR n10iOii) OR n10iO0i) OR n10iO1i) OR n10ilOi) OR n10illi) OR n10ilii) OR n10il0i) OR n10il1i) OR n10iiOi) OR n10iili) OR n10iiii) OR n10ii0i) OR n10ii1i) OR n10i0Oi) OR n10i0li) OR n10i0ii) OR n10i00i) OR n10i01i); + n10ii0i <= ((comp_pat_porn AND n10ii0O) OR n10ii0l); + n10ii0l <= (((((((NOT (comp_pat(0) XOR nll0l1O)) AND (NOT (comp_pat(1) XOR nll0l0i))) AND (NOT (comp_pat(2) XOR nll0l0l))) AND (NOT (comp_pat(3) XOR nll0l0O))) AND (NOT (comp_pat(4) XOR nll0lii))) AND (NOT (comp_pat(5) XOR nll0lil))) AND (NOT (comp_pat(6) XOR nll0liO))); + n10ii0O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0l1O)) AND (NOT ((NOT comp_pat(1)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(2)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(3)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(4)) XOR nll0lii))) AND (NOT ((NOT comp_pat(5)) XOR nll0lil))) AND (NOT ((NOT comp_pat(6)) XOR nll0liO))); + n10ii1i <= ((comp_pat_porn AND n10ii1O) OR n10ii1l); + n10ii1l <= (((((((NOT (comp_pat(0) XOR nll0l0i)) AND (NOT (comp_pat(1) XOR nll0l0l))) AND (NOT (comp_pat(2) XOR nll0l0O))) AND (NOT (comp_pat(3) XOR nll0lii))) AND (NOT (comp_pat(4) XOR nll0lil))) AND (NOT (comp_pat(5) XOR nll0liO))) AND (NOT (comp_pat(6) XOR nll0lli))); + n10ii1O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0l0i)) AND (NOT ((NOT comp_pat(1)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(2)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(3)) XOR nll0lii))) AND (NOT ((NOT comp_pat(4)) XOR nll0lil))) AND (NOT ((NOT comp_pat(5)) XOR nll0liO))) AND (NOT ((NOT comp_pat(6)) XOR nll0lli))); + n10iiii <= ((comp_pat_porn AND n10iiiO) OR n10iiil); + n10iiil <= (((((((NOT (comp_pat(0) XOR nll0l1l)) AND (NOT (comp_pat(1) XOR nll0l1O))) AND (NOT (comp_pat(2) XOR nll0l0i))) AND (NOT (comp_pat(3) XOR nll0l0l))) AND (NOT (comp_pat(4) XOR nll0l0O))) AND (NOT (comp_pat(5) XOR nll0lii))) AND (NOT (comp_pat(6) XOR nll0lil))); + n10iiiO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0l1l)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(2)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(3)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(4)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(5)) XOR nll0lii))) AND (NOT ((NOT comp_pat(6)) XOR nll0lil))); + n10iili <= ((comp_pat_porn AND n10iilO) OR n10iill); + n10iill <= (((((((NOT (comp_pat(0) XOR nll0l1i)) AND (NOT (comp_pat(1) XOR nll0l1l))) AND (NOT (comp_pat(2) XOR nll0l1O))) AND (NOT (comp_pat(3) XOR nll0l0i))) AND (NOT (comp_pat(4) XOR nll0l0l))) AND (NOT (comp_pat(5) XOR nll0l0O))) AND (NOT (comp_pat(6) XOR nll0lii))); + n10iilO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0l1i)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(3)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(4)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(5)) XOR nll0l0O))) AND (NOT ((NOT comp_pat(6)) XOR nll0lii))); + n10iiOi <= ((comp_pat_porn AND n10iiOO) OR n10iiOl); + n10iiOl <= (((((((NOT (comp_pat(0) XOR nll0iOO)) AND (NOT (comp_pat(1) XOR nll0l1i))) AND (NOT (comp_pat(2) XOR nll0l1l))) AND (NOT (comp_pat(3) XOR nll0l1O))) AND (NOT (comp_pat(4) XOR nll0l0i))) AND (NOT (comp_pat(5) XOR nll0l0l))) AND (NOT (comp_pat(6) XOR nll0l0O))); + n10iiOO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0iOO)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(4)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(5)) XOR nll0l0l))) AND (NOT ((NOT comp_pat(6)) XOR nll0l0O))); + n10il0i <= ((comp_pat_porn AND n10il0O) OR n10il0l); + n10il0l <= (((((((NOT (comp_pat(0) XOR nll0iOi)) AND (NOT (comp_pat(1) XOR nll0iOl))) AND (NOT (comp_pat(2) XOR nll0iOO))) AND (NOT (comp_pat(3) XOR nll0l1i))) AND (NOT (comp_pat(4) XOR nll0l1l))) AND (NOT (comp_pat(5) XOR nll0l1O))) AND (NOT (comp_pat(6) XOR nll0l0i))); + n10il0O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0iOi)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(6)) XOR nll0l0i))); + n10il1i <= ((comp_pat_porn AND n10il1O) OR n10il1l); + n10il1l <= (((((((NOT (comp_pat(0) XOR nll0iOl)) AND (NOT (comp_pat(1) XOR nll0iOO))) AND (NOT (comp_pat(2) XOR nll0l1i))) AND (NOT (comp_pat(3) XOR nll0l1l))) AND (NOT (comp_pat(4) XOR nll0l1O))) AND (NOT (comp_pat(5) XOR nll0l0i))) AND (NOT (comp_pat(6) XOR nll0l0l))); + n10il1O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0iOl)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(5)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(6)) XOR nll0l0l))); + n10ilii <= ((comp_pat_porn AND n10iliO) OR n10ilil); + n10ilil <= (((((((NOT (comp_pat(0) XOR nll0ilO)) AND (NOT (comp_pat(1) XOR nll0iOi))) AND (NOT (comp_pat(2) XOR nll0iOl))) AND (NOT (comp_pat(3) XOR nll0iOO))) AND (NOT (comp_pat(4) XOR nll0l1i))) AND (NOT (comp_pat(5) XOR nll0l1l))) AND (NOT (comp_pat(6) XOR nll0l1O))); + n10iliO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0ilO)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1O))); + n10illi <= ((comp_pat_porn AND n10illO) OR n10illl); + n10illl <= (((((((NOT (comp_pat(0) XOR nll0ill)) AND (NOT (comp_pat(1) XOR nll0ilO))) AND (NOT (comp_pat(2) XOR nll0iOi))) AND (NOT (comp_pat(3) XOR nll0iOl))) AND (NOT (comp_pat(4) XOR nll0iOO))) AND (NOT (comp_pat(5) XOR nll0l1i))) AND (NOT (comp_pat(6) XOR nll0l1l))); + n10illO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0ill)) AND (NOT ((NOT comp_pat(1)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1l))); + n10ilOi <= ((comp_pat_porn AND n10ilOO) OR n10ilOl); + n10ilOl <= (((((((NOT (comp_pat(0) XOR nll0ili)) AND (NOT (comp_pat(1) XOR nll0ill))) AND (NOT (comp_pat(2) XOR nll0ilO))) AND (NOT (comp_pat(3) XOR nll0iOi))) AND (NOT (comp_pat(4) XOR nll0iOl))) AND (NOT (comp_pat(5) XOR nll0iOO))) AND (NOT (comp_pat(6) XOR nll0l1i))); + n10ilOO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0ili)) AND (NOT ((NOT comp_pat(1)) XOR nll0ill))) AND (NOT ((NOT comp_pat(2)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1i))); + n10iO0i <= ((comp_pat_porn AND n10iO0O) OR n10iO0l); + n10iO0l <= (((((((NOT (comp_pat(0) XOR nll0iil)) AND (NOT (comp_pat(1) XOR nll0iiO))) AND (NOT (comp_pat(2) XOR nll0ili))) AND (NOT (comp_pat(3) XOR nll0ill))) AND (NOT (comp_pat(4) XOR nll0ilO))) AND (NOT (comp_pat(5) XOR nll0iOi))) AND (NOT (comp_pat(6) XOR nll0iOl))); + n10iO0O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0iil)) AND (NOT ((NOT comp_pat(1)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(2)) XOR nll0ili))) AND (NOT ((NOT comp_pat(3)) XOR nll0ill))) AND (NOT ((NOT comp_pat(4)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOl))); + n10iO1i <= ((comp_pat_porn AND n10iO1O) OR n10iO1l); + n10iO1l <= (((((((NOT (comp_pat(0) XOR nll0iiO)) AND (NOT (comp_pat(1) XOR nll0ili))) AND (NOT (comp_pat(2) XOR nll0ill))) AND (NOT (comp_pat(3) XOR nll0ilO))) AND (NOT (comp_pat(4) XOR nll0iOi))) AND (NOT (comp_pat(5) XOR nll0iOl))) AND (NOT (comp_pat(6) XOR nll0iOO))); + n10iO1O <= (((((((NOT ((NOT comp_pat(0)) XOR nll0iiO)) AND (NOT ((NOT comp_pat(1)) XOR nll0ili))) AND (NOT ((NOT comp_pat(2)) XOR nll0ill))) AND (NOT ((NOT comp_pat(3)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOO))); + n10iOii <= ((comp_pat_porn AND n10iOiO) OR n10iOil); + n10iOil <= (((((((NOT (comp_pat(0) XOR nll0iii)) AND (NOT (comp_pat(1) XOR nll0iil))) AND (NOT (comp_pat(2) XOR nll0iiO))) AND (NOT (comp_pat(3) XOR nll0ili))) AND (NOT (comp_pat(4) XOR nll0ill))) AND (NOT (comp_pat(5) XOR nll0ilO))) AND (NOT (comp_pat(6) XOR nll0iOi))); + n10iOiO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0iii)) AND (NOT ((NOT comp_pat(1)) XOR nll0iil))) AND (NOT ((NOT comp_pat(2)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(3)) XOR nll0ili))) AND (NOT ((NOT comp_pat(4)) XOR nll0ill))) AND (NOT ((NOT comp_pat(5)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOi))); + n10iOli <= ((comp_pat_porn AND n10iOlO) OR n10iOll); + n10iOll <= (((((((NOT (comp_pat(0) XOR nll0i0O)) AND (NOT (comp_pat(1) XOR nll0iii))) AND (NOT (comp_pat(2) XOR nll0iil))) AND (NOT (comp_pat(3) XOR nll0iiO))) AND (NOT (comp_pat(4) XOR nll0ili))) AND (NOT (comp_pat(5) XOR nll0ill))) AND (NOT (comp_pat(6) XOR nll0ilO))); + n10iOlO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0i0O)) AND (NOT ((NOT comp_pat(1)) XOR nll0iii))) AND (NOT ((NOT comp_pat(2)) XOR nll0iil))) AND (NOT ((NOT comp_pat(3)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(4)) XOR nll0ili))) AND (NOT ((NOT comp_pat(5)) XOR nll0ill))) AND (NOT ((NOT comp_pat(6)) XOR nll0ilO))); + n10iOOi <= ((comp_pat_porn AND n10iOOO) OR n10iOOl); + n10iOOl <= (((((((NOT (comp_pat(0) XOR nll0i0l)) AND (NOT (comp_pat(1) XOR nll0i0O))) AND (NOT (comp_pat(2) XOR nll0iii))) AND (NOT (comp_pat(3) XOR nll0iil))) AND (NOT (comp_pat(4) XOR nll0iiO))) AND (NOT (comp_pat(5) XOR nll0ili))) AND (NOT (comp_pat(6) XOR nll0ill))); + n10iOOO <= (((((((NOT ((NOT comp_pat(0)) XOR nll0i0l)) AND (NOT ((NOT comp_pat(1)) XOR nll0i0O))) AND (NOT ((NOT comp_pat(2)) XOR nll0iii))) AND (NOT ((NOT comp_pat(3)) XOR nll0iil))) AND (NOT ((NOT comp_pat(4)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(5)) XOR nll0ili))) AND (NOT ((NOT comp_pat(6)) XOR nll0ill))); + n10l00i <= ((n10ll0i AND n10lili) AND wire_w_lg_n10li0O3453w(0)); + n10l00l <= (n10ll0i AND wire_w_lg_n10lili3500w(0)); + n10l00O <= (n10l0iO AND wire_w_lg_n10l0OO3456w(0)); + n10l01i <= (wire_nllO0ii_w_lg_w_lg_w_lg_dataout3945w3946w3947w(0) OR wire_w_lg_n10l01l3948w(0)); + n10l01l <= ((((wire_nllO0il_w_lg_dataout3407w(0) OR wire_nllO00O_dataout) OR wire_nllO00i_dataout) OR wire_nllO01O_dataout) OR wire_nllO01l_dataout); + n10l01O <= (n10lili AND wire_w_lg_n10li0O3453w(0)); + n10l0ii <= ((wire_nllOO1l_o AND n10l0iO) AND n10l0OO); + n10l0il <= ((wire_nlO10Ol_o AND n10l0iO) AND n10l0OO); + n10l0iO <= (wire_w_lg_n10ll0i3493w(0) AND n10lili); + n10l0li <= (wire_w_lg_n10ll0i3493w(0) AND wire_w_lg_n10lili3500w(0)); + n10l0ll <= ((n10liil AND n10l0lO) AND n10l0OO); + n10l0lO <= (((((((((wire_nl_w_lg_nlO0i1i4400w(0) AND wire_nl_w_lg_nlO00OO4401w(0)) AND wire_nl_w_lg_nlO00Ol4403w(0)) AND wire_nl_w_lg_nlO00Oi4405w(0)) AND wire_nl_w_lg_nlO00lO4407w(0)) AND wire_nl_w_lg_nlO00ll4409w(0)) AND wire_nl_w_lg_nlO00li4411w(0)) AND wire_nl_w_lg_nlO00iO4413w(0)) AND wire_nl_w_lg_nlO00il4415w(0)) AND nlO00ii); + n10l0Oi <= ((wire_nlO10Ol_o AND n10liil) AND n10l0OO); + n10l0Ol <= (n10liil AND wire_w_lg_n10l0OO3456w(0)); + n10l0OO <= ((((((((((NOT (gnumber(0) XOR nlO01lO)) AND (NOT (gnumber(1) XOR nlO01Oi))) AND (NOT (gnumber(2) XOR nlO01Ol))) AND (NOT (gnumber(3) XOR nlO01OO))) AND (NOT (gnumber(4) XOR nlO001i))) AND (NOT (gnumber(5) XOR nlO001l))) AND (NOT (gnumber(6) XOR nlO001O))) AND (NOT (gnumber(7) XOR nlO000i))) AND (NOT (gnumber(8) XOR nlO000l))) AND (NOT (gnumber(9) XOR nlO000O))); + n10l10i <= (wire_w_lg_n10l1il4510w(0) AND (((((NOT resync_badcg_en(0)) AND wire_w_lg_w_resync_badcg_en_range4513w4514w(0)) OR (resync_badcg_en(0) AND resync_badcg_en(1))) OR wire_w_lg_n10l1ii4519w(0)) OR (wire_w_lg_n10l1ii4522w(0) AND ((NOT resync_badcg_en(0)) AND resync_badcg_en(1))))); + n10l10l <= ((((wire_n1l11lO_w_lg_dataout16758w(0) AND wire_w_lg_w_lg_w16764w16765w16766w(0)) OR wire_n1l11lO_w_lg_dataout16770w(0)) OR (wire_w_lg_nlOO0ilO16773w(0) AND wire_n1lllii_w_lg_dataout16774w(0))) OR wire_w_lg_w_lg_nlOO0iOl16779w16780w(0)); + n10l10O <= ((((wire_nl_w_lg_nl1liil17102w(0) AND wire_w_lg_w_lg_w17108w17109w17110w(0)) OR wire_nl_w_lg_nl1liil17114w(0)) OR (wire_w_lg_nlOO1O1O17117w(0) AND wire_n1iliii_w_lg_dataout17118w(0))) OR wire_w_lg_w_lg_nlOO1O0l17123w17124w(0)); + n10l11i <= (n10l11O OR n10l11l); + n10l11l <= (nll01ll AND wire_nllO1i_w_lg_nll01li7901w(0)); + n10l11O <= (wire_nl_w_lg_nll01ll7899w(0) AND nll01li); + n10l1ii <= (wire_n1liO0O_w_lg_dataout4506w(0) OR wire_n1Ol10O_w_lg_dataout4507w(0)); + n10l1il <= (wire_w_lg_rencdt_rising4504w(0) AND nllii0i); + n10l1iO <= (wire_w_lg_wa_6g_en4499w(0) OR (wire_w_lg_lpbk_en4500w(0) AND wire_nl_w_lg_nll01lO4501w(0))); + n10l1li <= ((wire_nl_w_lg_nlli0OO4494w(0) AND wire_w_lg_wa_6g_en4496w(0)) AND n1iiilO); + n10l1ll <= (wire_nllO0ii_dataout OR ((((NOT (rosnumber(0) XOR nlO01il)) AND (NOT (rosnumber(1) XOR nlO01iO))) AND (NOT (rosnumber(2) XOR nlO01li))) AND (NOT (rosnumber(3) XOR nlO01ll)))); + n10l1lO <= wire_nllO00i_w_lg_dataout4064w(0); + n10l1Oi <= (wire_nllO0il_w_lg_dataout3407w(0) OR wire_w_lg_n10l01l3948w(0)); + n10l1Ol <= (wire_nllO0il_w_lg_w_lg_dataout3407w4078w(0) OR wire_w_lg_n10l01l3948w(0)); + n10l1OO <= (wire_nllO00O_w_lg_w_lg_w_lg_dataout3960w3961w3962w(0) OR wire_w_lg_n10l01l3948w(0)); + n10li0i <= (rosbased AND wire_w_lg_n10ll0i3493w(0)); + n10li0l <= (n10liii AND wire_w_lg_n10li0O3453w(0)); + n10li0O <= ((((((((((NOT (enumber(0) XOR nlO00ii)) AND (NOT (enumber(1) XOR nlO00il))) AND (NOT (enumber(2) XOR nlO00iO))) AND (NOT (enumber(3) XOR nlO00li))) AND (NOT (enumber(4) XOR nlO00ll))) AND (NOT (enumber(5) XOR nlO00lO))) AND (NOT (enumber(6) XOR nlO00Oi))) AND (NOT (enumber(7) XOR nlO00Ol))) AND (NOT (enumber(8) XOR nlO00OO))) AND (NOT (enumber(9) XOR nlO0i1i))); + n10li1i <= ((wire_nlO10Ol_o AND n10liil) AND n10l0OO); + n10li1l <= (n10liil AND wire_w_lg_n10l0OO3456w(0)); + n10li1O <= ((n10liil AND n10l0lO) AND n10l0OO); + n10liii <= (wire_w_lg_rosbased3492w(0) AND n10ll0i); + n10liil <= (wire_w_lg_rosbased3492w(0) AND wire_w_lg_n10ll0i3493w(0)); + n10liiO <= (n10liii AND n10li0O); + n10lili <= ((((NOT (rosnumber(0) XOR wire_nlO0l0i_o(0))) AND (NOT (rosnumber(1) XOR wire_nlO0l0i_o(1)))) AND (NOT (rosnumber(2) XOR wire_nlO0l0i_o(2)))) AND (NOT (rosnumber(3) XOR wire_nlO0l0i_o(3)))); + n10lill <= (wire_w_lg_w_lg_n10liOl3443w3446w(0) AND wire_w_lg_w_lg_n10ll0O3433w3447w(0)); + n10lilO <= ((n10liOO OR (n10llii AND (n10ll0O AND n10lili))) AND n10liOl); + n10liOi <= (n10liOO AND wire_w_lg_n10liOl3443w(0)); + n10liOl <= ((((((((((NOT (knumber(0) XOR nlO0i1l)) AND (NOT (knumber(1) XOR nlO0i1O))) AND (NOT (knumber(2) XOR nlO0i0i))) AND (NOT (knumber(3) XOR nlO0i0l))) AND (NOT (knumber(4) XOR nlO0i0O))) AND (NOT (knumber(5) XOR nlO0iii))) AND (NOT (knumber(6) XOR nlO0iil))) AND (NOT (knumber(7) XOR nlO0iiO))) AND (NOT (knumber(8) XOR nlO0ili))) AND (NOT (knumber(9) XOR nlO0ill))); + n10liOO <= (wire_w_lg_n10ll0O3433w(0) AND niii0l); + n10ll0i <= ((n10ll0O AND (((rkchar AND niiill) OR wire_w_lg_w_lg_rkchar3383w3384w(0)) AND wire_w_lg_n10ll0l3386w(0))) OR nil1Oi); + n10ll0l <= ((((NOT (rosnumber(0) XOR nlO01il)) AND (NOT (rosnumber(1) XOR nlO01iO))) AND (NOT (rosnumber(2) XOR nlO01li))) AND (NOT (rosnumber(3) XOR nlO01ll))); + n10ll0O <= (((rosnumber(0) OR rosnumber(1)) OR rosnumber(2)) OR rosnumber(3)); + n10ll1i <= ((wire_w_lg_n10llii3439w(0) AND n10ll0O) OR nil1Oi); + n10ll1l <= (wire_w_lg_n10ll0O3433w(0) AND wire_w_lg_w_lg_n10ll1O3434w3435w(0)); + n10ll1O <= (((((((((knumber(0) OR knumber(1)) OR knumber(2)) OR knumber(3)) OR knumber(4)) OR knumber(5)) OR knumber(6)) OR knumber(7)) OR knumber(8)) OR knumber(9)); + n10llii <= (wire_nllO1i_w_lg_nil1Oi3372w(0) AND wire_nl_w_lg_niiill3373w(0)); + n10llil <= (wire_niOilO_o AND wire_niOill_o); + n10lliO <= wire_niOilO_w_lg_w_lg_o3116w3135w(0); + n10llli <= wire_niOilO_w_lg_o3119w(0); + n10llll <= wire_niOilO_w_lg_w_lg_o3116w3117w(0); + n10lllO <= (n1i000O AND n10llOl); + n10llOi <= (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND wire_niOilO_w_lg_w_lg_o3116w3135w(0))); + n10llOl <= wire_niOl1i_w_lg_o2994w(0); + n10llOO <= (wire_niOiOl_o AND (wire_niOiOi_o AND (wire_niOilO_o AND wire_niOill_o))); + n10lO0i <= wire_niOl1O_w_lg_o3190w(0); + n10lO0l <= wire_niOl1O_w_lg_w_lg_o1314w3189w(0); + n10lO0O <= (wire_niOl0i_dataout XOR wire_niOl1l_o); + n10lO1i <= ((((wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10llil)) OR wire_niOiOl_w_lg_o3288w(0)) OR wire_niOiOl_w_lg_o3156w(0)) OR wire_niOiOl_w_lg_o3159w(0)); + n10lO1l <= wire_niOl1O_w_lg_o2980w(0); + n10lO1O <= wire_niOl1O_w_lg_w_lg_o1314w2984w(0); + n10lOii <= (wire_niOilO_o AND wire_niOill_o); + n10lOil <= wire_niOilO_w_lg_w_lg_o3116w3135w(0); + n10lOiO <= wire_niOilO_w_lg_o3119w(0); + n10lOli <= wire_niOilO_w_lg_w_lg_o3116w3117w(0); + n10lOll <= ((((wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_dataout AND n10lO1l)) OR wire_niOl0l_w_lg_dataout3222w(0)) OR wire_niOl0l_w_lg_dataout3225w(0)) OR wire_niOl0l_w_lg_dataout3228w(0)); + n10lOlO <= (wire_nlOll0O_w_lg_w_lg_dataout1212w3256w(0) OR (wire_nlOll0O_dataout AND n1i00ii)); + n10lOOi <= wire_niOl0l_w_lg_dataout2982w(0); + n10lOOl <= (n10llOO AND n1i000l); + n10lOOO <= ((n10llOO AND n10llOl) OR (n10lO1i AND n10llOl)); + n10O00i <= (n1O01l OR n1O01i); + n10O00l <= (wire_nl_w_lg_n1OOOO2714w(0) AND wire_nl_w_lg_n1OOOl2708w(0)); + n10O00O <= (wire_nl_w_lg_n1OOOO2714w(0) AND n1OOOl); + n10O01i <= (n1O1OO OR n1O1Ol); + n10O01l <= ((((n1O01l OR n1O01i) OR n1O1OO) OR n1O1Ol) OR n1O1Oi); + n10O01O <= ((((n1O01l OR n1O01i) OR n1O1lO) OR n1O1ll) OR n1l0Oi); + n10O0ii <= (n1l0lO AND n1l0ll); + n10O0il <= (wire_nl_w_lg_n010Ol2709w(0) AND wire_nl_w_lg_n1OOOl2708w(0)); + n10O0iO <= (wire_nl_w_lg_n010Ol2709w(0) AND n1OOOl); + n10O0li <= ((((max_rlv_sel(0) OR max_rlv_sel(1)) OR max_rlv_sel(2)) OR max_rlv_sel(3)) OR max_rlv_sel(4)); + n10O0ll <= ((wire_n1O0ll_w_lg_w2963w2964w(0) AND wire_n1O00l_w_lg_dataout2965w(0)) AND wire_n1O00i_w_lg_dataout2967w(0)); + n10O0lO <= ((wire_n1O0ll_w_lg_w2963w2964w(0) AND wire_n1O00l_w_lg_dataout2965w(0)) AND wire_n1O00i_dataout); + n10O0Oi <= ((((((wire_w_lg_w_pmadwidth_range175w2600w(0) OR wire_nl_w_lg_nlil1l2592w(0)) OR wire_nl_w_lg_nlil1i2594w(0)) OR wire_nl_w_lg_nliiOO2596w(0)) OR wire_nl_w_lg_nliiOl2604w(0)) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10O0Ol <= ((((((wire_w_lg_w_pmadwidth_range175w2589w(0) OR wire_nl_w_lg_nlil1O2590w(0)) OR wire_nl_w_lg_nlil1l2592w(0)) OR wire_nl_w_lg_nlil1i2594w(0)) OR wire_nl_w_lg_nliiOO2596w(0)) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10O0OO <= ((((((wire_w_lg_w_pmadwidth_range175w2608w(0) OR wire_nl_w_lg_nlil1i2594w(0)) OR wire_nl_w_lg_nliiOO2596w(0)) OR wire_nl_w_lg_nliiOl2604w(0)) OR wire_nl_w_lg_nl1lOi2612w(0)) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10O10i <= wire_niOl1O_w_lg_w_lg_o1314w2984w(0); + n10O10l <= wire_niOl1O_w_lg_o2980w(0); + n10O10O <= (wire_niOl1i_w_lg_o3107w(0) OR (wire_niOl1i_w_lg_o2972w(0) AND (wire_niOiOO_w_lg_o2973w(0) AND (wire_niOiOl_w_lg_o1205w(0) AND wire_niOiOi_w_lg_o3108w(0))))); + n10O11i <= (n10llOO AND n1i00ii); + n10O11l <= (wire_niOl0l_w_lg_dataout1312w(0) AND wire_niOl0i_w_lg_dataout1313w(0)); + n10O11O <= ((((((wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND (wire_niOilO_o AND wire_niOill_o))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10lOli))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10lOiO))) OR wire_niOiOl_w_lg_o3130w(0)) OR wire_niOiOl_w_lg_o3133w(0)) OR wire_niOiOl_w_lg_o3137w(0)); + n10O1ii <= wire_niOl1i_w_lg_w_lg_o2972w3113w(0); + n10O1il <= wire_niOl1i_w_lg_o3114w(0); + n10O1iO <= ((((wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10lOii)) OR wire_niOiOl_w_lg_o3153w(0)) OR wire_niOiOl_w_lg_o3156w(0)) OR wire_niOiOl_w_lg_o3159w(0)); + n10O1li <= ((((wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND wire_niOilO_w_lg_w_lg_o3116w3117w(0))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND wire_niOilO_w_lg_o3119w(0)))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10lOil))) OR wire_niOiOl_w_lg_o3148w(0)); + n10O1ll <= (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND wire_niOilO_w_lg_w_lg_o3116w3135w(0))); + n10O1lO <= (wire_niOiOl_o AND (wire_niOiOi_o AND (wire_niOilO_o AND wire_niOill_o))); + n10O1Oi <= (wire_w_lg_w_ib_invalid_code_range3169w3175w(0) OR wire_w_lg_w_ib_invalid_code_range3176w3184w(0)); + n10O1Ol <= (n1O1Oi OR n1l0Oi); + n10O1OO <= (n1O1lO OR n1O1ll); + n10Oi0i <= ((((((((wire_w_lg_w_pmadwidth_range175w219w(0) OR wire_nl_w_lg_nlil1O2590w(0)) OR wire_nl_w_lg_nlil1l2592w(0)) OR wire_nl_w_lg_nlil1i2594w(0)) OR wire_nl_w_lg_nliiOO2596w(0)) OR wire_nl_w_lg_nliiOl2604w(0)) OR wire_nl_w_lg_nl1lOi2612w(0)) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oi0l <= ((wire_w_lg_w_lg_w2544w2545w2546w(0) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oi0O <= ((wire_w_lg_w_lg_w2535w2536w2537w(0) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oi1i <= ((((((((wire_w_lg_w_pmadwidth_range175w219w(0) OR wire_nl_w_lg_nlil0O2616w(0)) OR wire_nl_w_lg_nlil0l2618w(0)) OR wire_nl_w_lg_nlil0i2588w(0)) OR wire_nl_w_lg_nlil1O2590w(0)) OR wire_nl_w_lg_nlil1l2592w(0)) OR wire_nl_w_lg_nlil1i2594w(0)) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oi1l <= ((((((((wire_w_lg_w_pmadwidth_range175w219w(0) OR wire_nl_w_lg_nlil0l2618w(0)) OR wire_nl_w_lg_nlil0i2588w(0)) OR wire_nl_w_lg_nlil1O2590w(0)) OR wire_nl_w_lg_nlil1l2592w(0)) OR wire_nl_w_lg_nlil1i2594w(0)) OR wire_nl_w_lg_nliiOO2596w(0)) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oi1O <= ((((((((wire_w_lg_w_pmadwidth_range175w219w(0) OR wire_nl_w_lg_nlil0i2588w(0)) OR wire_nl_w_lg_nlil1O2590w(0)) OR wire_nl_w_lg_nlil1l2592w(0)) OR wire_nl_w_lg_nlil1i2594w(0)) OR wire_nl_w_lg_nliiOO2596w(0)) OR wire_nl_w_lg_nliiOl2604w(0)) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oiii <= ((wire_w_lg_w_lg_w2551w2552w2553w(0) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oiil <= ((wire_w_lg_w_lg_w_lg_w2558w2559w2560w2561w(0) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10OiiO <= ((wire_w_lg_w_lg_w_lg_w2566w2567w2568w2569w(0) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oili <= ((wire_w_lg_w_lg_w_lg_w2574w2575w2576w2577w(0) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10Oill <= ((wire_w_lg_w_lg_w_lg_w2582w2583w2584w2585w(0) OR wire_n1OOOi_w_lg_dataout2538w(0)) OR wire_nl_w_lg_n1OiOi2540w(0)); + n10OilO <= ((((wire_w_lg_n10Ol0O2457w(0) OR wire_w_lg_n10Ol0l2449w(0)) OR wire_w_lg_n10Ol1O2459w(0)) OR wire_w_lg_n10Ol1i2453w(0)) OR n10OiOi); + n10OiOi <= ((((((((wire_nl_w_lg_nl1lOi2945w(0) AND wire_w_lg_n1i11OO2440w(0)) AND wire_w_lg_n1i11Ol2432w(0)) AND wire_w_lg_n1i11Oi2425w(0)) AND wire_w_lg_n1i11lO2419w(0)) AND wire_w_lg_n1i11ll2414w(0)) AND wire_w_lg_n1i11li2410w(0)) AND wire_w_lg_n1i11il2408w(0)) AND wire_w_lg_n1i11ii2953w(0)); + n10OiOl <= (((wire_w_lg_n1i11ii2450w(0) OR wire_w_lg_n10Ol0i2451w(0)) OR wire_w_lg_n10Ol1i2453w(0)) OR wire_w_lg_n10OiOO2455w(0)); + n10OiOO <= ((((((((n1i100O OR wire_w_lg_n1i11OO2440w(0)) OR n1i11Ol) OR n1i11Oi) OR n1i11lO) OR n1i11ll) OR n1i11li) OR n1i11il) OR n1i11ii); + n10Ol0i <= ((((n1i100O OR wire_w_lg_n1i11ll2414w(0)) OR n1i11li) OR n1i11il) OR n1i11ii); + n10Ol0l <= (((n1i100O OR wire_w_lg_n1i11li2410w(0)) OR n1i11il) OR n1i11ii); + n10Ol0O <= (wire_w_lg_n1i11il2408w(0) OR n1i11ii); + n10Ol1i <= (((((((n1i100O OR wire_w_lg_n1i11Ol2432w(0)) OR n1i11Oi) OR n1i11lO) OR n1i11ll) OR n1i11li) OR n1i11il) OR n1i11ii); + n10Ol1l <= ((((((n1i100O OR wire_w_lg_n1i11Oi2425w(0)) OR n1i11lO) OR n1i11ll) OR n1i11li) OR n1i11il) OR n1i11ii); + n10Ol1O <= (((((n1i100O OR wire_w_lg_n1i11lO2419w(0)) OR n1i11ll) OR n1i11li) OR n1i11il) OR n1i11ii); + n10Olii <= ((((wire_w_lg_n10OO1i2402w(0) OR wire_w_lg_n10OlOO2394w(0)) OR wire_w_lg_n10OlOi2404w(0)) OR wire_w_lg_n10Olll2398w(0)) OR n10Olil); + n10Olil <= ((((((((((n1i1i0O OR n1i1i0l) AND wire_w_lg_n1i1i0i2385w(0)) AND wire_w_lg_n1i1i1O2377w(0)) AND wire_w_lg_n1i1i1l2370w(0)) AND wire_w_lg_n1i10Ol2364w(0)) AND wire_w_lg_n1i10ll2359w(0)) AND wire_w_lg_n1i10il2355w(0)) AND wire_w_lg_n1i100l2498w(0)) AND wire_w_lg_n1i101O2353w(0)) AND wire_w_lg_n1i101i2943w(0)); + n10OliO <= (((wire_w_lg_n1i101i2395w(0) OR wire_w_lg_n10OlOl2396w(0)) OR wire_w_lg_n10Olll2398w(0)) OR wire_w_lg_n10Olli2400w(0)); + n10Olli <= ((((((((wire_w_lg_n1i1i0i2385w(0) OR n1i1i1O) OR n1i1i1l) OR n1i10Ol) OR n1i10ll) OR n1i10il) OR n1i100l) OR n1i101O) OR n1i101i); + n10Olll <= (((((((wire_w_lg_n1i1i1O2377w(0) OR n1i1i1l) OR n1i10Ol) OR n1i10ll) OR n1i10il) OR n1i100l) OR n1i101O) OR n1i101i); + n10OllO <= ((((((wire_w_lg_n1i1i1l2370w(0) OR n1i10Ol) OR n1i10ll) OR n1i10il) OR n1i100l) OR n1i101O) OR n1i101i); + n10OlOi <= (((((wire_w_lg_n1i10Ol2364w(0) OR n1i10ll) OR n1i10il) OR n1i100l) OR n1i101O) OR n1i101i); + n10OlOl <= ((((wire_w_lg_n1i10ll2359w(0) OR n1i10il) OR n1i100l) OR n1i101O) OR n1i101i); + n10OlOO <= (((wire_w_lg_n1i10il2355w(0) OR n1i100l) OR n1i101O) OR n1i101i); + n10OO0i <= (((wire_w_lg_n1i1iii2340w(0) OR wire_w_lg_n10OOiO2341w(0)) OR wire_w_lg_n10OO0O2343w(0)) OR wire_w_lg_n10OO0l2345w(0)); + n10OO0l <= (((((((wire_w_lg_w_lg_n1i1l0O2133w2330w(0) OR wire_w_lg_n1i1iOl2331w(0)) OR wire_w_lg_n1i1iOi2323w(0)) OR wire_w_lg_n1i1ilO2316w(0)) OR wire_w_lg_n1i1ill2310w(0)) OR wire_w_lg_n1i1ili2305w(0)) OR n1i1iil) OR n1i1iii); + n10OO0O <= ((((((wire_w_lg_w_lg_n1i1l0O2133w2322w(0) OR wire_w_lg_n1i1iOi2323w(0)) OR wire_w_lg_n1i1ilO2316w(0)) OR wire_w_lg_n1i1ill2310w(0)) OR wire_w_lg_n1i1ili2305w(0)) OR n1i1iil) OR n1i1iii); + n10OO1i <= (wire_w_lg_n1i101O2353w(0) OR n1i101i); + n10OO1l <= ((((wire_w_lg_n10OOll2347w(0) OR wire_w_lg_n10OOli2339w(0)) OR wire_w_lg_n10OOil2349w(0)) OR wire_w_lg_n10OO0O2343w(0)) OR n10OO1O); + n10OO1O <= ((wire_nl_w_lg_w_lg_w_lg_w2928w2929w2930w2931w(0) AND wire_w_lg_n1i1iil2299w(0)) AND wire_w_lg_n1i1iii2933w(0)); + n10OOii <= (((((wire_w_lg_w_lg_n1i1l0O2133w2315w(0) OR wire_w_lg_n1i1ilO2316w(0)) OR wire_w_lg_n1i1ill2310w(0)) OR wire_w_lg_n1i1ili2305w(0)) OR n1i1iil) OR n1i1iii); + n10OOil <= ((((wire_w_lg_w_lg_n1i1l0O2133w2309w(0) OR wire_w_lg_n1i1ill2310w(0)) OR wire_w_lg_n1i1ili2305w(0)) OR n1i1iil) OR n1i1iii); + n10OOiO <= (((wire_w_lg_w_lg_n1i1l0O2133w2304w(0) OR wire_w_lg_n1i1ili2305w(0)) OR n1i1iil) OR n1i1iii); + n10OOli <= (((wire_w_lg_n1i1l0O2133w(0) OR n1i1ili) OR n1i1iil) OR n1i1iii); + n10OOll <= (wire_w_lg_n1i1iil2299w(0) OR n1i1iii); + n10OOlO <= ((((wire_w_lg_n1i110O2293w(0) OR wire_w_lg_n1i110l2285w(0)) OR wire_w_lg_n1i111O2295w(0)) OR wire_w_lg_n1i111i2289w(0)) OR n10OOOi); + n10OOOi <= ((((((((((wire_w_lg_w_pmadwidth_range175w2912w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_nlil0l2618w(0))) AND wire_w_lg_n1i1O0i2276w(0)) AND wire_w_lg_n1i1O1O2268w(0)) AND wire_w_lg_n1i1O1l2261w(0)) AND wire_w_lg_n1i1lOl2255w(0)) AND wire_w_lg_n1i1lll2250w(0)) AND wire_w_lg_n1i1lil2246w(0)) AND wire_w_lg_n1i1l0l2464w(0)) AND wire_w_lg_n1i1l1O2244w(0)) AND wire_w_lg_n1i1l1i2923w(0)); + n10OOOl <= (((wire_w_lg_n1i1l1i2286w(0) OR wire_w_lg_n1i110i2287w(0)) OR wire_w_lg_n1i111i2289w(0)) OR wire_w_lg_n10OOOO2291w(0)); + n10OOOO <= ((((((((wire_w_lg_n1i1O0i2276w(0) OR n1i1O1O) OR n1i1O1l) OR n1i1lOl) OR n1i1lll) OR n1i1lil) OR n1i1l0l) OR n1i1l1O) OR n1i1l1i); + n11000i <= ((((((((((NOT ((NOT comp_pat(0)) XOR nl01iOi)) AND (NOT ((NOT comp_pat(1)) XOR nl01iOl))) AND (NOT ((NOT comp_pat(2)) XOR nl01iOO))) AND (NOT ((NOT comp_pat(3)) XOR nl01l1i))) AND (NOT ((NOT comp_pat(4)) XOR nl01l1l))) AND (NOT ((NOT comp_pat(5)) XOR nl01l1O))) AND (NOT ((NOT comp_pat(6)) XOR nl01l0i))) AND (NOT ((NOT comp_pat(7)) XOR nl01l0l))) AND (NOT ((NOT comp_pat(8)) XOR nl01l0O))) AND (NOT ((NOT comp_pat(9)) XOR nl01lii))); + n11000l <= ((comp_pat_porn AND n1100ii) OR n11000O); + n11000O <= ((((((((NOT (comp_pat(8) XOR nl01l0O)) AND (NOT (comp_pat(9) XOR nl01lii))) AND (NOT (comp_pat(10) XOR nl01lil))) AND (NOT (comp_pat(11) XOR nl01liO))) AND (NOT (comp_pat(12) XOR nl01lli))) AND (NOT (comp_pat(13) XOR nl01lll))) AND (NOT (comp_pat(14) XOR nl01llO))) AND (NOT (comp_pat(15) XOR nl01lOi))); + n11001i <= ((((((((((NOT ((NOT comp_pat(0)) XOR nl01lil)) AND (NOT ((NOT comp_pat(1)) XOR nl01liO))) AND (NOT ((NOT comp_pat(2)) XOR nl01lli))) AND (NOT ((NOT comp_pat(3)) XOR nl01lll))) AND (NOT ((NOT comp_pat(4)) XOR nl01llO))) AND (NOT ((NOT comp_pat(5)) XOR nl01lOi))) AND (NOT ((NOT comp_pat(6)) XOR nl01lOl))) AND (NOT ((NOT comp_pat(7)) XOR nl01lOO))) AND (NOT ((NOT comp_pat(8)) XOR nl01O1i))) AND (NOT ((NOT comp_pat(9)) XOR nl01O1l))); + n11001l <= ((comp_pat_porn AND n11000i) OR n11001O); + n11001O <= ((((((((((NOT (comp_pat(0) XOR nl01iOi)) AND (NOT (comp_pat(1) XOR nl01iOl))) AND (NOT (comp_pat(2) XOR nl01iOO))) AND (NOT (comp_pat(3) XOR nl01l1i))) AND (NOT (comp_pat(4) XOR nl01l1l))) AND (NOT (comp_pat(5) XOR nl01l1O))) AND (NOT (comp_pat(6) XOR nl01l0i))) AND (NOT (comp_pat(7) XOR nl01l0l))) AND (NOT (comp_pat(8) XOR nl01l0O))) AND (NOT (comp_pat(9) XOR nl01lii))); + n1100ii <= ((((((((NOT ((NOT comp_pat(8)) XOR nl01l0O)) AND (NOT ((NOT comp_pat(9)) XOR nl01lii))) AND (NOT ((NOT comp_pat(10)) XOR nl01lil))) AND (NOT ((NOT comp_pat(11)) XOR nl01liO))) AND (NOT ((NOT comp_pat(12)) XOR nl01lli))) AND (NOT ((NOT comp_pat(13)) XOR nl01lll))) AND (NOT ((NOT comp_pat(14)) XOR nl01llO))) AND (NOT ((NOT comp_pat(15)) XOR nl01lOi))); + n1100il <= ((comp_pat_porn AND n1100li) OR n1100iO); + n1100iO <= ((((((((NOT (comp_pat(8) XOR nl01iOi)) AND (NOT (comp_pat(9) XOR nl01iOl))) AND (NOT (comp_pat(10) XOR nl01iOO))) AND (NOT (comp_pat(11) XOR nl01l1i))) AND (NOT (comp_pat(12) XOR nl01l1l))) AND (NOT (comp_pat(13) XOR nl01l1O))) AND (NOT (comp_pat(14) XOR nl01l0i))) AND (NOT (comp_pat(15) XOR nl01l0l))); + n1100li <= ((((((((NOT ((NOT comp_pat(8)) XOR nl01iOi)) AND (NOT ((NOT comp_pat(9)) XOR nl01iOl))) AND (NOT ((NOT comp_pat(10)) XOR nl01iOO))) AND (NOT ((NOT comp_pat(11)) XOR nl01l1i))) AND (NOT ((NOT comp_pat(12)) XOR nl01l1l))) AND (NOT ((NOT comp_pat(13)) XOR nl01l1O))) AND (NOT ((NOT comp_pat(14)) XOR nl01l0i))) AND (NOT ((NOT comp_pat(15)) XOR nl01l0l))); + n1100ll <= ((comp_pat_porn AND n1100Oi) OR n1100lO); + n1100lO <= ((((((((NOT (comp_pat(0) XOR nl01l0O)) AND (NOT (comp_pat(1) XOR nl01lii))) AND (NOT (comp_pat(2) XOR nl01lil))) AND (NOT (comp_pat(3) XOR nl01liO))) AND (NOT (comp_pat(4) XOR nl01lli))) AND (NOT (comp_pat(5) XOR nl01lll))) AND (NOT (comp_pat(6) XOR nl01llO))) AND (NOT (comp_pat(7) XOR nl01lOi))); + n1100Oi <= ((((((((NOT ((NOT comp_pat(0)) XOR nl01l0O)) AND (NOT ((NOT comp_pat(1)) XOR nl01lii))) AND (NOT ((NOT comp_pat(2)) XOR nl01lil))) AND (NOT ((NOT comp_pat(3)) XOR nl01liO))) AND (NOT ((NOT comp_pat(4)) XOR nl01lli))) AND (NOT ((NOT comp_pat(5)) XOR nl01lll))) AND (NOT ((NOT comp_pat(6)) XOR nl01llO))) AND (NOT ((NOT comp_pat(7)) XOR nl01lOi))); + n1100Ol <= ((comp_pat_porn AND n110i1i) OR n1100OO); + n1100OO <= ((((((((NOT (comp_pat(0) XOR nl01iOi)) AND (NOT (comp_pat(1) XOR nl01iOl))) AND (NOT (comp_pat(2) XOR nl01iOO))) AND (NOT (comp_pat(3) XOR nl01l1i))) AND (NOT (comp_pat(4) XOR nl01l1l))) AND (NOT (comp_pat(5) XOR nl01l1O))) AND (NOT (comp_pat(6) XOR nl01l0i))) AND (NOT (comp_pat(7) XOR nl01l0l))); + n11010i <= ((((((((((NOT (comp_pat(10) XOR nl01i1O)) AND (NOT (comp_pat(11) XOR nl01i0i))) AND (NOT (comp_pat(12) XOR nl01i0l))) AND (NOT (comp_pat(13) XOR nl01i0O))) AND (NOT (comp_pat(14) XOR nl01iii))) AND (NOT (comp_pat(15) XOR nl01iil))) AND (NOT (comp_pat(16) XOR nl01iiO))) AND (NOT (comp_pat(17) XOR nl01ili))) AND (NOT (comp_pat(18) XOR nl01ill))) AND (NOT (comp_pat(19) XOR nl01ilO))); + n11010l <= ((((((((((NOT ((NOT comp_pat(10)) XOR nl01i1O)) AND (NOT ((NOT comp_pat(11)) XOR nl01i0i))) AND (NOT ((NOT comp_pat(12)) XOR nl01i0l))) AND (NOT ((NOT comp_pat(13)) XOR nl01i0O))) AND (NOT ((NOT comp_pat(14)) XOR nl01iii))) AND (NOT ((NOT comp_pat(15)) XOR nl01iil))) AND (NOT ((NOT comp_pat(16)) XOR nl01iiO))) AND (NOT ((NOT comp_pat(17)) XOR nl01ili))) AND (NOT ((NOT comp_pat(18)) XOR nl01ill))) AND (NOT ((NOT comp_pat(19)) XOR nl01ilO))); + n11010O <= ((n1101Ol OR nl1Ol0O) OR (n1iiiOi AND nl1OiOi)); + n11011i <= ((((((((((NOT (comp_pat(0) XOR nl010il)) AND (NOT (comp_pat(1) XOR nl010iO))) AND (NOT (comp_pat(2) XOR nl010li))) AND (NOT (comp_pat(3) XOR nl010ll))) AND (NOT (comp_pat(4) XOR nl010lO))) AND (NOT (comp_pat(5) XOR nl010Oi))) AND (NOT (comp_pat(6) XOR nl010Ol))) AND (NOT (comp_pat(7) XOR nl010OO))) AND (NOT (comp_pat(8) XOR nl01i1i))) AND (NOT (comp_pat(9) XOR nl01i1l))); + n11011l <= ((((((((((NOT ((NOT comp_pat(0)) XOR nl010il)) AND (NOT ((NOT comp_pat(1)) XOR nl010iO))) AND (NOT ((NOT comp_pat(2)) XOR nl010li))) AND (NOT ((NOT comp_pat(3)) XOR nl010ll))) AND (NOT ((NOT comp_pat(4)) XOR nl010lO))) AND (NOT ((NOT comp_pat(5)) XOR nl010Oi))) AND (NOT ((NOT comp_pat(6)) XOR nl010Ol))) AND (NOT ((NOT comp_pat(7)) XOR nl010OO))) AND (NOT ((NOT comp_pat(8)) XOR nl01i1i))) AND (NOT ((NOT comp_pat(9)) XOR nl01i1l))); + n11011O <= ((comp_pat_porn AND n11010l) OR n11010i); + n1101ii <= ((n11001l OR nl1Ol0l) OR (n1iiiOi AND nl1OilO)); + n1101il <= ((comp_pat_porn AND n1101li) OR n1101iO); + n1101iO <= ((((((((((NOT (comp_pat(10) XOR nl01lil)) AND (NOT (comp_pat(11) XOR nl01liO))) AND (NOT (comp_pat(12) XOR nl01lli))) AND (NOT (comp_pat(13) XOR nl01lll))) AND (NOT (comp_pat(14) XOR nl01llO))) AND (NOT (comp_pat(15) XOR nl01lOi))) AND (NOT (comp_pat(16) XOR nl01lOl))) AND (NOT (comp_pat(17) XOR nl01lOO))) AND (NOT (comp_pat(18) XOR nl01O1i))) AND (NOT (comp_pat(19) XOR nl01O1l))); + n1101li <= ((((((((((NOT ((NOT comp_pat(10)) XOR nl01lil)) AND (NOT ((NOT comp_pat(11)) XOR nl01liO))) AND (NOT ((NOT comp_pat(12)) XOR nl01lli))) AND (NOT ((NOT comp_pat(13)) XOR nl01lll))) AND (NOT ((NOT comp_pat(14)) XOR nl01llO))) AND (NOT ((NOT comp_pat(15)) XOR nl01lOi))) AND (NOT ((NOT comp_pat(16)) XOR nl01lOl))) AND (NOT ((NOT comp_pat(17)) XOR nl01lOO))) AND (NOT ((NOT comp_pat(18)) XOR nl01O1i))) AND (NOT ((NOT comp_pat(19)) XOR nl01O1l))); + n1101ll <= ((comp_pat_porn AND n1101Oi) OR n1101lO); + n1101lO <= ((((((((((NOT (comp_pat(10) XOR nl01iOi)) AND (NOT (comp_pat(11) XOR nl01iOl))) AND (NOT (comp_pat(12) XOR nl01iOO))) AND (NOT (comp_pat(13) XOR nl01l1i))) AND (NOT (comp_pat(14) XOR nl01l1l))) AND (NOT (comp_pat(15) XOR nl01l1O))) AND (NOT (comp_pat(16) XOR nl01l0i))) AND (NOT (comp_pat(17) XOR nl01l0l))) AND (NOT (comp_pat(18) XOR nl01l0O))) AND (NOT (comp_pat(19) XOR nl01lii))); + n1101Oi <= ((((((((((NOT ((NOT comp_pat(10)) XOR nl01iOi)) AND (NOT ((NOT comp_pat(11)) XOR nl01iOl))) AND (NOT ((NOT comp_pat(12)) XOR nl01iOO))) AND (NOT ((NOT comp_pat(13)) XOR nl01l1i))) AND (NOT ((NOT comp_pat(14)) XOR nl01l1l))) AND (NOT ((NOT comp_pat(15)) XOR nl01l1O))) AND (NOT ((NOT comp_pat(16)) XOR nl01l0i))) AND (NOT ((NOT comp_pat(17)) XOR nl01l0l))) AND (NOT ((NOT comp_pat(18)) XOR nl01l0O))) AND (NOT ((NOT comp_pat(19)) XOR nl01lii))); + n1101Ol <= ((comp_pat_porn AND n11001i) OR n1101OO); + n1101OO <= ((((((((((NOT (comp_pat(0) XOR nl01lil)) AND (NOT (comp_pat(1) XOR nl01liO))) AND (NOT (comp_pat(2) XOR nl01lli))) AND (NOT (comp_pat(3) XOR nl01lll))) AND (NOT (comp_pat(4) XOR nl01llO))) AND (NOT (comp_pat(5) XOR nl01lOi))) AND (NOT (comp_pat(6) XOR nl01lOl))) AND (NOT (comp_pat(7) XOR nl01lOO))) AND (NOT (comp_pat(8) XOR nl01O1i))) AND (NOT (comp_pat(9) XOR nl01O1l))); + n110i0i <= (((NOT comp_pat_size(0)) AND wire_w_lg_w_comp_pat_size_range1331w1332w(0)) AND comp_pat_size(2)); + n110i0l <= ((comp_pat_size(0) AND comp_pat_size(1)) AND (NOT comp_pat_size(2))); + n110i0O <= (((NOT comp_pat_size(0)) AND comp_pat_size(1)) AND (NOT comp_pat_size(2))); + n110i1i <= ((((((((NOT ((NOT comp_pat(0)) XOR nl01iOi)) AND (NOT ((NOT comp_pat(1)) XOR nl01iOl))) AND (NOT ((NOT comp_pat(2)) XOR nl01iOO))) AND (NOT ((NOT comp_pat(3)) XOR nl01l1i))) AND (NOT ((NOT comp_pat(4)) XOR nl01l1l))) AND (NOT ((NOT comp_pat(5)) XOR nl01l1O))) AND (NOT ((NOT comp_pat(6)) XOR nl01l0i))) AND (NOT ((NOT comp_pat(7)) XOR nl01l0l))); + n110i1l <= (((NOT comp_pat_size(0)) AND comp_pat_size(1)) AND comp_pat_size(2)); + n110i1O <= (wire_w_lg_w_comp_pat_size_range1330w1333w(0) AND comp_pat_size(2)); + n110iii <= (wire_w_lg_w_comp_pat_size_range1330w1333w(0) AND (NOT comp_pat_size(2))); + n110iil <= (((NOT comp_pat_size(0)) AND wire_w_lg_w_comp_pat_size_range1331w1332w(0)) AND (NOT comp_pat_size(2))); + n110iiO <= ((((((((wire_nl0OiOl_w_lg_o5684w(0) OR wire_w_lg_n110lOO5624w(0)) OR wire_w_lg_n110lOi5628w(0)) OR wire_w_lg_n110lll5632w(0)) OR wire_w_lg_n110liO5636w(0)) OR wire_w_lg_n110lii5640w(0)) OR wire_w_lg_n110l0l5644w(0)) OR wire_w_lg_n110l1O5648w(0)) OR wire_w_lg_n110l1i5652w(0)); + n110ili <= ((((((((wire_nl0OiOl_w_lg_o5615w(0) OR wire_w_lg_n110lOO5624w(0)) OR wire_w_lg_n110lOl5626w(0)) OR wire_w_lg_n110lll5632w(0)) OR wire_w_lg_n110lli5634w(0)) OR wire_w_lg_n110lii5640w(0)) OR wire_w_lg_n110l0O5642w(0)) OR wire_w_lg_n110l1O5648w(0)) OR wire_w_lg_n110l1l5650w(0)); + n110ill <= ((((((((wire_w_lg_n110lOO5624w(0) OR wire_w_lg_n110lOl5626w(0)) OR wire_w_lg_n110lOi5628w(0)) OR wire_w_lg_n110llO5630w(0)) OR wire_w_lg_n110lii5640w(0)) OR wire_w_lg_n110l0O5642w(0)) OR wire_w_lg_n110l0l5644w(0)) OR wire_w_lg_n110l0i5646w(0)) OR wire_w_lg_n110iOl5657w(0)); + n110ilO <= ((((((((wire_w_lg_n110lll5632w(0) OR wire_w_lg_n110lli5634w(0)) OR wire_w_lg_n110liO5636w(0)) OR wire_w_lg_n110lil5638w(0)) OR wire_w_lg_n110lii5640w(0)) OR wire_w_lg_n110l0O5642w(0)) OR wire_w_lg_n110l0l5644w(0)) OR wire_w_lg_n110l0i5646w(0)) OR wire_w_lg_n110iOl5657w(0)); + n110iOi <= ((((wire_w_lg_n110l1O5648w(0) OR wire_w_lg_n110l1l5650w(0)) OR wire_w_lg_n110l1i5652w(0)) OR wire_w_lg_n110iOl5657w(0)) OR n110iOO); + n110iOl <= ((((((((((((((((((wire_nl0OiOl_w_lg_o5615w(0) OR wire_w_lg_n110O1i5616w(0)) OR (NOT (((wire_nl0Ol1l_w_lg_o5618w(0) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o))) OR wire_w_lg_n110lOO5624w(0)) OR wire_w_lg_n110lOl5626w(0)) OR wire_w_lg_n110lOi5628w(0)) OR wire_w_lg_n110llO5630w(0)) OR wire_w_lg_n110lll5632w(0)) OR wire_w_lg_n110lli5634w(0)) OR wire_w_lg_n110liO5636w(0)) OR wire_w_lg_n110lil5638w(0)) OR wire_w_lg_n110lii5640w(0)) OR wire_w_lg_n110l0O5642w(0)) OR wire_w_lg_n110l0l5644w(0)) OR wire_w_lg_n110l0i5646w(0)) OR wire_w_lg_n110l1O5648w(0)) OR wire_w_lg_n110l1l5650w(0)) OR wire_w_lg_n110l1i5652w(0)) OR n110iOO); + n110iOO <= ((((((((((((((((((wire_nl0OO1O_w_lg_o13557w(0) AND wire_nl0OO1i_w_lg_o5577w(0)) AND wire_nl0OlOO_w_lg_o5560w(0)) AND wire_nl0OlOl_w_lg_o5544w(0)) AND wire_nl0OlOi_w_lg_o5529w(0)) AND wire_nl0OllO_w_lg_o5515w(0)) AND wire_nl0Olll_w_lg_o5502w(0)) AND wire_nl0Olli_w_lg_o5490w(0)) AND wire_nl0OliO_w_lg_o5479w(0)) AND wire_nl0Olil_w_lg_o5469w(0)) AND wire_nl0Olii_w_lg_o5460w(0)) AND wire_nl0Ol0O_w_lg_o5452w(0)) AND wire_nl0Ol0l_w_lg_o5445w(0)) AND wire_nl0Ol0i_w_lg_o5439w(0)) AND wire_nl0Ol1O_w_lg_o5434w(0)) AND wire_nl0Ol1l_w_lg_o5618w(0)) AND wire_nl0Ol1i_w_lg_o5431w(0)) AND wire_nl0OiOO_w_lg_o5429w(0)) AND wire_nl0OiOl_w_lg_o13575w(0)); + n110l0i <= (((((((((((((((wire_nl0OlOl_w_lg_o5544w(0) OR wire_nl0OlOi_o) OR wire_nl0OllO_o) OR wire_nl0Olll_o) OR wire_nl0Olli_o) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110l0l <= ((((((((((((((wire_nl0OlOi_w_lg_o5529w(0) OR wire_nl0OllO_o) OR wire_nl0Olll_o) OR wire_nl0Olli_o) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110l0O <= (((((((((((((wire_nl0OllO_w_lg_o5515w(0) OR wire_nl0Olll_o) OR wire_nl0Olli_o) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110l1i <= ((((((((((((((((((wire_nl0OO1l_w_lg_o5595w(0) OR wire_nl0OO1i_o) OR wire_nl0OlOO_o) OR wire_nl0OlOl_o) OR wire_nl0OlOi_o) OR wire_nl0OllO_o) OR wire_nl0Olll_o) OR wire_nl0Olli_o) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110l1l <= (((((((((((((((((wire_nl0OO1i_w_lg_o5577w(0) OR wire_nl0OlOO_o) OR wire_nl0OlOl_o) OR wire_nl0OlOi_o) OR wire_nl0OllO_o) OR wire_nl0Olll_o) OR wire_nl0Olli_o) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110l1O <= ((((((((((((((((wire_nl0OlOO_w_lg_o5560w(0) OR wire_nl0OlOl_o) OR wire_nl0OlOi_o) OR wire_nl0OllO_o) OR wire_nl0Olll_o) OR wire_nl0Olli_o) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110lii <= ((((((((((((wire_nl0Olll_w_lg_o5502w(0) OR wire_nl0Olli_o) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110lil <= (((((((((((wire_nl0Olli_w_lg_o5490w(0) OR wire_nl0OliO_o) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110liO <= ((((((((((wire_nl0OliO_w_lg_o5479w(0) OR wire_nl0Olil_o) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110lli <= (((((((((wire_nl0Olil_w_lg_o5469w(0) OR wire_nl0Olii_o) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110lll <= ((((((((wire_nl0Olii_w_lg_o5460w(0) OR wire_nl0Ol0O_o) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110llO <= (((((((wire_nl0Ol0O_w_lg_o5452w(0) OR wire_nl0Ol0l_o) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110lOi <= ((((((wire_nl0Ol0l_w_lg_o5445w(0) OR wire_nl0Ol0i_o) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110lOl <= (((((wire_nl0Ol0i_w_lg_o5439w(0) OR wire_nl0Ol1O_o) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110lOO <= ((((wire_nl0Ol1O_w_lg_o5434w(0) OR wire_nl0Ol1l_o) OR wire_nl0Ol1i_o) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110O0i <= (n11iOli AND (wire_w_lg_w_lg_comp_pat_porn5095w5096w(0) AND wire_w_lg_w_lg_comp_pat_porn5097w5098w(0))); + n110O0l <= ((((((((NOT (comp_pat(16) XOR nll0OOl)) AND (NOT (comp_pat(17) XOR nll0OOO))) AND (NOT (comp_pat(18) XOR nlli11i))) AND (NOT (comp_pat(19) XOR nlli11l))) AND (NOT (comp_pat(20) XOR nlli11O))) AND (NOT (comp_pat(21) XOR nlli10i))) AND (NOT (comp_pat(22) XOR nlli10l))) AND (NOT (comp_pat(23) XOR nlli10O))); + n110O0O <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0OOl)) AND (NOT ((NOT comp_pat(17)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(18)) XOR nlli11i))) AND (NOT ((NOT comp_pat(19)) XOR nlli11l))) AND (NOT ((NOT comp_pat(20)) XOR nlli11O))) AND (NOT ((NOT comp_pat(21)) XOR nlli10i))) AND (NOT ((NOT comp_pat(22)) XOR nlli10l))) AND (NOT ((NOT comp_pat(23)) XOR nlli10O))); + n110O1i <= ((wire_nl0Ol1i_w_lg_o5431w(0) OR wire_nl0OiOO_o) OR wire_nl0OiOl_o); + n110O1l <= (wire_nl0OiOO_w_lg_o5429w(0) OR wire_nl0OiOl_o); + n110O1O <= (((((((((((((((n11iO0i OR n11ilOl) OR n11iliO) OR n11il0i) OR n11iiOl) OR n11iiiO) OR n11ii0i) OR n11i0Ol) OR n11i0iO) OR n11i00i) OR n11i1Ol) OR n11i1iO) OR n11i10i) OR n110OOl) OR n110OiO) OR n110O0i); + n110Oii <= ((((((((NOT (comp_pat(24) XOR nlli1ii)) AND (NOT (comp_pat(25) XOR nlli1il))) AND (NOT (comp_pat(26) XOR nlli1iO))) AND (NOT (comp_pat(27) XOR nlli1li))) AND (NOT (comp_pat(28) XOR nlli1ll))) AND (NOT (comp_pat(29) XOR nlli1lO))) AND (NOT (comp_pat(30) XOR nlli1Oi))) AND (NOT (comp_pat(31) XOR nlli1Ol))); + n110Oil <= ((((((((NOT ((NOT comp_pat(24)) XOR nlli1ii)) AND (NOT ((NOT comp_pat(25)) XOR nlli1il))) AND (NOT ((NOT comp_pat(26)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(27)) XOR nlli1li))) AND (NOT ((NOT comp_pat(28)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(29)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(30)) XOR nlli1Oi))) AND (NOT ((NOT comp_pat(31)) XOR nlli1Ol))); + n110OiO <= (n11iOOi AND (wire_w_lg_w_lg_comp_pat_porn5089w5090w(0) AND wire_w_lg_w_lg_comp_pat_porn5091w5092w(0))); + n110Oli <= ((((((((NOT (comp_pat(16) XOR nll0OiO)) AND (NOT (comp_pat(17) XOR nll0OOl))) AND (NOT (comp_pat(18) XOR nll0OOO))) AND (NOT (comp_pat(19) XOR nlli11i))) AND (NOT (comp_pat(20) XOR nlli11l))) AND (NOT (comp_pat(21) XOR nlli11O))) AND (NOT (comp_pat(22) XOR nlli10i))) AND (NOT (comp_pat(23) XOR nlli10l))); + n110Oll <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0OiO)) AND (NOT ((NOT comp_pat(17)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(18)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(19)) XOR nlli11i))) AND (NOT ((NOT comp_pat(20)) XOR nlli11l))) AND (NOT ((NOT comp_pat(21)) XOR nlli11O))) AND (NOT ((NOT comp_pat(22)) XOR nlli10i))) AND (NOT ((NOT comp_pat(23)) XOR nlli10l))); + n110OlO <= ((((((((NOT (comp_pat(24) XOR nlli10O)) AND (NOT (comp_pat(25) XOR nlli1ii))) AND (NOT (comp_pat(26) XOR nlli1il))) AND (NOT (comp_pat(27) XOR nlli1iO))) AND (NOT (comp_pat(28) XOR nlli1li))) AND (NOT (comp_pat(29) XOR nlli1ll))) AND (NOT (comp_pat(30) XOR nlli1lO))) AND (NOT (comp_pat(31) XOR nlli1Oi))); + n110OOi <= ((((((((NOT ((NOT comp_pat(24)) XOR nlli10O)) AND (NOT ((NOT comp_pat(25)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(26)) XOR nlli1il))) AND (NOT ((NOT comp_pat(27)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(28)) XOR nlli1li))) AND (NOT ((NOT comp_pat(29)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(30)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(31)) XOR nlli1Oi))); + n110OOl <= (n11l11i AND (wire_w_lg_w_lg_comp_pat_porn5083w5084w(0) AND wire_w_lg_w_lg_comp_pat_porn5085w5086w(0))); + n110OOO <= ((((((((NOT (comp_pat(16) XOR nll0Oil)) AND (NOT (comp_pat(17) XOR nll0OiO))) AND (NOT (comp_pat(18) XOR nll0OOl))) AND (NOT (comp_pat(19) XOR nll0OOO))) AND (NOT (comp_pat(20) XOR nlli11i))) AND (NOT (comp_pat(21) XOR nlli11l))) AND (NOT (comp_pat(22) XOR nlli11O))) AND (NOT (comp_pat(23) XOR nlli10i))); + n11100i <= (((((((((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n11100l <= ((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O); + n11100O <= (wire_w_lg_w_pmadwidth_range175w14240w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1110ii14241w(0))); + n11101i <= wire_w_lg_w_pmadwidth_range175w14253w(0); + n11101l <= (((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l); + n11101O <= (wire_w_lg_w_pmadwidth_range175w14247w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n11100i14248w(0))); + n1110ii <= ((((((((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO); + n1110il <= (((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i); + n1110iO <= (wire_w_lg_w_pmadwidth_range175w14233w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1110li14234w(0))); + n1110li <= (((((((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i); + n1110ll <= ((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l); + n1110lO <= (wire_w_lg_w_pmadwidth_range175w14226w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1110Oi14227w(0))); + n1110Oi <= ((((((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l); + n1110Ol <= (((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O); + n1110OO <= (wire_w_lg_w_pmadwidth_range175w14219w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111i1i14220w(0))); + n11110i <= ((((((nlli10l OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n11110l <= (((((nlli10i OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n11110O <= ((((nlli11O OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n11111i <= (((((((((nlli1il OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n11111l <= ((((((((nlli1ii OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n11111O <= (((((((nlli10O OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n1111ii <= (((nlli11l OR nlli11i) OR nll0OOO) OR nll0OOl); + n1111il <= ((nlli11i OR nll0OOO) OR nll0OOl); + n1111iO <= (nll0OOO OR nll0OOl); + n1111li <= wire_w_lg_w_pmadwidth_range175w14262w(0); + n1111ll <= ((((((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + n1111lO <= wire_w_lg_w_pmadwidth_range175w14259w(0); + n1111Oi <= (((((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO); + n1111Ol <= wire_w_lg_w_pmadwidth_range175w14256w(0); + n1111OO <= ((((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i); + n111i0i <= ((((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i); + n111i0l <= (((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il); + n111i0O <= (wire_w_lg_w_pmadwidth_range175w14205w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111iii14206w(0))); + n111i1i <= (((((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O); + n111i1l <= ((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii); + n111i1O <= (wire_w_lg_w_pmadwidth_range175w14212w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111i0i14213w(0))); + n111iii <= (((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l); + n111iil <= ((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO); + n111iiO <= (wire_w_lg_w_pmadwidth_range175w14198w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111ili14199w(0))); + n111ili <= ((((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O); + n111ill <= (((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li); + n111ilO <= (wire_w_lg_w_pmadwidth_range175w14191w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111iOi14192w(0))); + n111iOi <= (((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii); + n111iOl <= ((((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll); + n111iOO <= (wire_w_lg_w_pmadwidth_range175w14184w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111l1i14185w(0))); + n111l0i <= (((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO); + n111l0l <= ((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi); + n111l0O <= (wire_w_lg_w_pmadwidth_range175w14170w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111lii14171w(0))); + n111l1i <= ((((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il); + n111l1l <= (((wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol) OR nlli1Oi) OR nlli1lO); + n111l1O <= (wire_w_lg_w_pmadwidth_range175w14177w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n111l0i14178w(0))); + n111lii <= ((((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li); + n111lil <= (wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) OR nlli1Ol); + n111liO <= (wire_w_lg_w_pmadwidth_range175w14162w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND (NOT (((nlli1Ol OR nlli1Oi) OR nlli1lO) OR nlli1ll)))); + n111lli <= (wire_w_lg_w_pmadwidth_range175w14155w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND (NOT ((nlli1Ol OR nlli1Oi) OR nlli1lO)))); + n111lll <= (wire_w_lg_w_pmadwidth_range175w14148w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND (NOT (nlli1Ol OR nlli1Oi)))); + n111llO <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND pmadwidth(1)); + n111lOi <= (((((NOT (nl0101O XOR nl011Oi)) AND (NOT (nl0100i XOR nl011Ol))) AND (NOT (nl0100l XOR nl011OO))) AND (NOT (nl0100O XOR nl0101i))) AND (NOT (nl010ii XOR nl0101l))); + n111lOl <= (comp_pat_size(0) AND autobytealign_dis); + n111lOO <= ((NOT comp_pat_size(0)) AND autobytealign_dis); + n111O0i <= (n110i1O OR n110i1l); + n111O0l <= (n110iil OR n110i0O); + n111O0O <= ((((((((NOT (comp_pat(0) XOR nl010il)) AND (NOT (comp_pat(1) XOR nl010iO))) AND (NOT (comp_pat(2) XOR nl010li))) AND (NOT (comp_pat(3) XOR nl010ll))) AND (NOT (comp_pat(4) XOR nl010lO))) AND (NOT (comp_pat(5) XOR nl010Oi))) AND (NOT (comp_pat(6) XOR nl010Ol))) AND (NOT (comp_pat(7) XOR nl010OO))); + n111O1i <= ((((nl010ii AND nl0100O) AND nl0100l) AND nl0100i) AND nl0101O); + n111O1l <= (wa_6g_en AND autobytealign_dis); + n111O1O <= (wire_nll1lOi_dataout AND (wire_w_lg_autobytealign_dis5791w(0) AND n1iiilO)); + n111Oii <= (((((((NOT (comp_pat(0) XOR nl010il)) AND (NOT (comp_pat(1) XOR nl010iO))) AND (NOT (comp_pat(2) XOR nl010li))) AND (NOT (comp_pat(3) XOR nl010ll))) AND (NOT (comp_pat(4) XOR nl010lO))) AND (NOT (comp_pat(5) XOR nl010Oi))) AND (NOT (comp_pat(6) XOR nl010Ol))); + n111Oil <= (((((((NOT ((NOT comp_pat(0)) XOR nl010il)) AND (NOT ((NOT comp_pat(1)) XOR nl010iO))) AND (NOT ((NOT comp_pat(2)) XOR nl010li))) AND (NOT ((NOT comp_pat(3)) XOR nl010ll))) AND (NOT ((NOT comp_pat(4)) XOR nl010lO))) AND (NOT ((NOT comp_pat(5)) XOR nl010Oi))) AND (NOT ((NOT comp_pat(6)) XOR nl010Ol))); + n111OiO <= ((((((((NOT (comp_pat(8) XOR nl01i1i)) AND (NOT (comp_pat(9) XOR nl01i1l))) AND (NOT (comp_pat(10) XOR nl01i1O))) AND (NOT (comp_pat(11) XOR nl01i0i))) AND (NOT (comp_pat(12) XOR nl01i0l))) AND (NOT (comp_pat(13) XOR nl01i0O))) AND (NOT (comp_pat(14) XOR nl01iii))) AND (NOT (comp_pat(15) XOR nl01iil))); + n111Oli <= ((((((((((NOT (comp_pat(0) XOR nl01i1O)) AND (NOT (comp_pat(1) XOR nl01i0i))) AND (NOT (comp_pat(2) XOR nl01i0l))) AND (NOT (comp_pat(3) XOR nl01i0O))) AND (NOT (comp_pat(4) XOR nl01iii))) AND (NOT (comp_pat(5) XOR nl01iil))) AND (NOT (comp_pat(6) XOR nl01iiO))) AND (NOT (comp_pat(7) XOR nl01ili))) AND (NOT (comp_pat(8) XOR nl01ill))) AND (NOT (comp_pat(9) XOR nl01ilO))); + n111Oll <= ((((((((((NOT ((NOT comp_pat(0)) XOR nl01i1O)) AND (NOT ((NOT comp_pat(1)) XOR nl01i0i))) AND (NOT ((NOT comp_pat(2)) XOR nl01i0l))) AND (NOT ((NOT comp_pat(3)) XOR nl01i0O))) AND (NOT ((NOT comp_pat(4)) XOR nl01iii))) AND (NOT ((NOT comp_pat(5)) XOR nl01iil))) AND (NOT ((NOT comp_pat(6)) XOR nl01iiO))) AND (NOT ((NOT comp_pat(7)) XOR nl01ili))) AND (NOT ((NOT comp_pat(8)) XOR nl01ill))) AND (NOT ((NOT comp_pat(9)) XOR nl01ilO))); + n111OlO <= ((((((((NOT (comp_pat(0) XOR nl01i1i)) AND (NOT (comp_pat(1) XOR nl01i1l))) AND (NOT (comp_pat(2) XOR nl01i1O))) AND (NOT (comp_pat(3) XOR nl01i0i))) AND (NOT (comp_pat(4) XOR nl01i0l))) AND (NOT (comp_pat(5) XOR nl01i0O))) AND (NOT (comp_pat(6) XOR nl01iii))) AND (NOT (comp_pat(7) XOR nl01iil))); + n111OOi <= (((((((NOT (comp_pat(0) XOR nl01i1O)) AND (NOT (comp_pat(1) XOR nl01i0i))) AND (NOT (comp_pat(2) XOR nl01i0l))) AND (NOT (comp_pat(3) XOR nl01i0O))) AND (NOT (comp_pat(4) XOR nl01iii))) AND (NOT (comp_pat(5) XOR nl01iil))) AND (NOT (comp_pat(6) XOR nl01iiO))); + n111OOl <= (((((((NOT ((NOT comp_pat(0)) XOR nl01i1O)) AND (NOT ((NOT comp_pat(1)) XOR nl01i0i))) AND (NOT ((NOT comp_pat(2)) XOR nl01i0l))) AND (NOT ((NOT comp_pat(3)) XOR nl01i0O))) AND (NOT ((NOT comp_pat(4)) XOR nl01iii))) AND (NOT ((NOT comp_pat(5)) XOR nl01iil))) AND (NOT ((NOT comp_pat(6)) XOR nl01iiO))); + n111OOO <= ((comp_pat_porn AND n11011l) OR n11011i); + n11i00i <= (n11l1Oi AND (wire_w_lg_w_lg_comp_pat_porn5059w5060w(0) AND wire_w_lg_w_lg_comp_pat_porn5061w5062w(0))); + n11i00l <= ((((((((NOT (comp_pat(16) XOR nll0O0i)) AND (NOT (comp_pat(17) XOR nll0O0l))) AND (NOT (comp_pat(18) XOR nll0O0O))) AND (NOT (comp_pat(19) XOR nll0Oii))) AND (NOT (comp_pat(20) XOR nll0Oil))) AND (NOT (comp_pat(21) XOR nll0OiO))) AND (NOT (comp_pat(22) XOR nll0OOl))) AND (NOT (comp_pat(23) XOR nll0OOO))); + n11i00O <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0O0i)) AND (NOT ((NOT comp_pat(17)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(18)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(19)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(20)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(21)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(22)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(23)) XOR nll0OOO))); + n11i01i <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0O0l)) AND (NOT ((NOT comp_pat(17)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(18)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(19)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(20)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(21)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(22)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(23)) XOR nlli11i))); + n11i01l <= ((((((((NOT (comp_pat(24) XOR nlli11l)) AND (NOT (comp_pat(25) XOR nlli11O))) AND (NOT (comp_pat(26) XOR nlli10i))) AND (NOT (comp_pat(27) XOR nlli10l))) AND (NOT (comp_pat(28) XOR nlli10O))) AND (NOT (comp_pat(29) XOR nlli1ii))) AND (NOT (comp_pat(30) XOR nlli1il))) AND (NOT (comp_pat(31) XOR nlli1iO))); + n11i01O <= ((((((((NOT ((NOT comp_pat(24)) XOR nlli11l)) AND (NOT ((NOT comp_pat(25)) XOR nlli11O))) AND (NOT ((NOT comp_pat(26)) XOR nlli10i))) AND (NOT ((NOT comp_pat(27)) XOR nlli10l))) AND (NOT ((NOT comp_pat(28)) XOR nlli10O))) AND (NOT ((NOT comp_pat(29)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(30)) XOR nlli1il))) AND (NOT ((NOT comp_pat(31)) XOR nlli1iO))); + n11i0ii <= ((((((((NOT (comp_pat(24) XOR nlli11i)) AND (NOT (comp_pat(25) XOR nlli11l))) AND (NOT (comp_pat(26) XOR nlli11O))) AND (NOT (comp_pat(27) XOR nlli10i))) AND (NOT (comp_pat(28) XOR nlli10l))) AND (NOT (comp_pat(29) XOR nlli10O))) AND (NOT (comp_pat(30) XOR nlli1ii))) AND (NOT (comp_pat(31) XOR nlli1il))); + n11i0il <= ((((((((NOT ((NOT comp_pat(24)) XOR nlli11i)) AND (NOT ((NOT comp_pat(25)) XOR nlli11l))) AND (NOT ((NOT comp_pat(26)) XOR nlli11O))) AND (NOT ((NOT comp_pat(27)) XOR nlli10i))) AND (NOT ((NOT comp_pat(28)) XOR nlli10l))) AND (NOT ((NOT comp_pat(29)) XOR nlli10O))) AND (NOT ((NOT comp_pat(30)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(31)) XOR nlli1il))); + n11i0iO <= (n11l01i AND (wire_w_lg_w_lg_comp_pat_porn5053w5054w(0) AND wire_w_lg_w_lg_comp_pat_porn5055w5056w(0))); + n11i0li <= ((((((((NOT (comp_pat(16) XOR nll0O1O)) AND (NOT (comp_pat(17) XOR nll0O0i))) AND (NOT (comp_pat(18) XOR nll0O0l))) AND (NOT (comp_pat(19) XOR nll0O0O))) AND (NOT (comp_pat(20) XOR nll0Oii))) AND (NOT (comp_pat(21) XOR nll0Oil))) AND (NOT (comp_pat(22) XOR nll0OiO))) AND (NOT (comp_pat(23) XOR nll0OOl))); + n11i0ll <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0O1O)) AND (NOT ((NOT comp_pat(17)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(18)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(19)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(20)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(21)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(22)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(23)) XOR nll0OOl))); + n11i0lO <= ((((((((NOT (comp_pat(24) XOR nll0OOO)) AND (NOT (comp_pat(25) XOR nlli11i))) AND (NOT (comp_pat(26) XOR nlli11l))) AND (NOT (comp_pat(27) XOR nlli11O))) AND (NOT (comp_pat(28) XOR nlli10i))) AND (NOT (comp_pat(29) XOR nlli10l))) AND (NOT (comp_pat(30) XOR nlli10O))) AND (NOT (comp_pat(31) XOR nlli1ii))); + n11i0Oi <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0OOO)) AND (NOT ((NOT comp_pat(25)) XOR nlli11i))) AND (NOT ((NOT comp_pat(26)) XOR nlli11l))) AND (NOT ((NOT comp_pat(27)) XOR nlli11O))) AND (NOT ((NOT comp_pat(28)) XOR nlli10i))) AND (NOT ((NOT comp_pat(29)) XOR nlli10l))) AND (NOT ((NOT comp_pat(30)) XOR nlli10O))) AND (NOT ((NOT comp_pat(31)) XOR nlli1ii))); + n11i0Ol <= (n11l00i AND (wire_w_lg_w_lg_comp_pat_porn5047w5048w(0) AND wire_w_lg_w_lg_comp_pat_porn5049w5050w(0))); + n11i0OO <= ((((((((NOT (comp_pat(16) XOR nll0O1l)) AND (NOT (comp_pat(17) XOR nll0O1O))) AND (NOT (comp_pat(18) XOR nll0O0i))) AND (NOT (comp_pat(19) XOR nll0O0l))) AND (NOT (comp_pat(20) XOR nll0O0O))) AND (NOT (comp_pat(21) XOR nll0Oii))) AND (NOT (comp_pat(22) XOR nll0Oil))) AND (NOT (comp_pat(23) XOR nll0OiO))); + n11i10i <= (n11l10i AND (wire_w_lg_w_lg_comp_pat_porn5077w5078w(0) AND wire_w_lg_w_lg_comp_pat_porn5079w5080w(0))); + n11i10l <= ((((((((NOT (comp_pat(16) XOR nll0Oii)) AND (NOT (comp_pat(17) XOR nll0Oil))) AND (NOT (comp_pat(18) XOR nll0OiO))) AND (NOT (comp_pat(19) XOR nll0OOl))) AND (NOT (comp_pat(20) XOR nll0OOO))) AND (NOT (comp_pat(21) XOR nlli11i))) AND (NOT (comp_pat(22) XOR nlli11l))) AND (NOT (comp_pat(23) XOR nlli11O))); + n11i10O <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0Oii)) AND (NOT ((NOT comp_pat(17)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(18)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(19)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(20)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(21)) XOR nlli11i))) AND (NOT ((NOT comp_pat(22)) XOR nlli11l))) AND (NOT ((NOT comp_pat(23)) XOR nlli11O))); + n11i11i <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0Oil)) AND (NOT ((NOT comp_pat(17)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(18)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(19)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(20)) XOR nlli11i))) AND (NOT ((NOT comp_pat(21)) XOR nlli11l))) AND (NOT ((NOT comp_pat(22)) XOR nlli11O))) AND (NOT ((NOT comp_pat(23)) XOR nlli10i))); + n11i11l <= ((((((((NOT (comp_pat(24) XOR nlli10l)) AND (NOT (comp_pat(25) XOR nlli10O))) AND (NOT (comp_pat(26) XOR nlli1ii))) AND (NOT (comp_pat(27) XOR nlli1il))) AND (NOT (comp_pat(28) XOR nlli1iO))) AND (NOT (comp_pat(29) XOR nlli1li))) AND (NOT (comp_pat(30) XOR nlli1ll))) AND (NOT (comp_pat(31) XOR nlli1lO))); + n11i11O <= ((((((((NOT ((NOT comp_pat(24)) XOR nlli10l)) AND (NOT ((NOT comp_pat(25)) XOR nlli10O))) AND (NOT ((NOT comp_pat(26)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(27)) XOR nlli1il))) AND (NOT ((NOT comp_pat(28)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(29)) XOR nlli1li))) AND (NOT ((NOT comp_pat(30)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(31)) XOR nlli1lO))); + n11i1ii <= ((((((((NOT (comp_pat(24) XOR nlli10i)) AND (NOT (comp_pat(25) XOR nlli10l))) AND (NOT (comp_pat(26) XOR nlli10O))) AND (NOT (comp_pat(27) XOR nlli1ii))) AND (NOT (comp_pat(28) XOR nlli1il))) AND (NOT (comp_pat(29) XOR nlli1iO))) AND (NOT (comp_pat(30) XOR nlli1li))) AND (NOT (comp_pat(31) XOR nlli1ll))); + n11i1il <= ((((((((NOT ((NOT comp_pat(24)) XOR nlli10i)) AND (NOT ((NOT comp_pat(25)) XOR nlli10l))) AND (NOT ((NOT comp_pat(26)) XOR nlli10O))) AND (NOT ((NOT comp_pat(27)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(28)) XOR nlli1il))) AND (NOT ((NOT comp_pat(29)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(30)) XOR nlli1li))) AND (NOT ((NOT comp_pat(31)) XOR nlli1ll))); + n11i1iO <= (n11l1ii AND (wire_w_lg_w_lg_comp_pat_porn5071w5072w(0) AND wire_w_lg_w_lg_comp_pat_porn5073w5074w(0))); + n11i1li <= ((((((((NOT (comp_pat(16) XOR nll0O0O)) AND (NOT (comp_pat(17) XOR nll0Oii))) AND (NOT (comp_pat(18) XOR nll0Oil))) AND (NOT (comp_pat(19) XOR nll0OiO))) AND (NOT (comp_pat(20) XOR nll0OOl))) AND (NOT (comp_pat(21) XOR nll0OOO))) AND (NOT (comp_pat(22) XOR nlli11i))) AND (NOT (comp_pat(23) XOR nlli11l))); + n11i1ll <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0O0O)) AND (NOT ((NOT comp_pat(17)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(18)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(19)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(20)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(21)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(22)) XOR nlli11i))) AND (NOT ((NOT comp_pat(23)) XOR nlli11l))); + n11i1lO <= ((((((((NOT (comp_pat(24) XOR nlli11O)) AND (NOT (comp_pat(25) XOR nlli10i))) AND (NOT (comp_pat(26) XOR nlli10l))) AND (NOT (comp_pat(27) XOR nlli10O))) AND (NOT (comp_pat(28) XOR nlli1ii))) AND (NOT (comp_pat(29) XOR nlli1il))) AND (NOT (comp_pat(30) XOR nlli1iO))) AND (NOT (comp_pat(31) XOR nlli1li))); + n11i1Oi <= ((((((((NOT ((NOT comp_pat(24)) XOR nlli11O)) AND (NOT ((NOT comp_pat(25)) XOR nlli10i))) AND (NOT ((NOT comp_pat(26)) XOR nlli10l))) AND (NOT ((NOT comp_pat(27)) XOR nlli10O))) AND (NOT ((NOT comp_pat(28)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(29)) XOR nlli1il))) AND (NOT ((NOT comp_pat(30)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(31)) XOR nlli1li))); + n11i1Ol <= (n11l1li AND (wire_w_lg_w_lg_comp_pat_porn5065w5066w(0) AND wire_w_lg_w_lg_comp_pat_porn5067w5068w(0))); + n11i1OO <= ((((((((NOT (comp_pat(16) XOR nll0O0l)) AND (NOT (comp_pat(17) XOR nll0O0O))) AND (NOT (comp_pat(18) XOR nll0Oii))) AND (NOT (comp_pat(19) XOR nll0Oil))) AND (NOT (comp_pat(20) XOR nll0OiO))) AND (NOT (comp_pat(21) XOR nll0OOl))) AND (NOT (comp_pat(22) XOR nll0OOO))) AND (NOT (comp_pat(23) XOR nlli11i))); + n11ii0i <= (n11l0ii AND (wire_w_lg_w_lg_comp_pat_porn5041w5042w(0) AND wire_w_lg_w_lg_comp_pat_porn5043w5044w(0))); + n11ii0l <= ((((((((NOT (comp_pat(16) XOR nll0O1i)) AND (NOT (comp_pat(17) XOR nll0O1l))) AND (NOT (comp_pat(18) XOR nll0O1O))) AND (NOT (comp_pat(19) XOR nll0O0i))) AND (NOT (comp_pat(20) XOR nll0O0l))) AND (NOT (comp_pat(21) XOR nll0O0O))) AND (NOT (comp_pat(22) XOR nll0Oii))) AND (NOT (comp_pat(23) XOR nll0Oil))); + n11ii0O <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0O1i)) AND (NOT ((NOT comp_pat(17)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(18)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(19)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(20)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(21)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(22)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(23)) XOR nll0Oil))); + n11ii1i <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0O1l)) AND (NOT ((NOT comp_pat(17)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(18)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(19)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(20)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(21)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(22)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(23)) XOR nll0OiO))); + n11ii1l <= ((((((((NOT (comp_pat(24) XOR nll0OOl)) AND (NOT (comp_pat(25) XOR nll0OOO))) AND (NOT (comp_pat(26) XOR nlli11i))) AND (NOT (comp_pat(27) XOR nlli11l))) AND (NOT (comp_pat(28) XOR nlli11O))) AND (NOT (comp_pat(29) XOR nlli10i))) AND (NOT (comp_pat(30) XOR nlli10l))) AND (NOT (comp_pat(31) XOR nlli10O))); + n11ii1O <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0OOl)) AND (NOT ((NOT comp_pat(25)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(26)) XOR nlli11i))) AND (NOT ((NOT comp_pat(27)) XOR nlli11l))) AND (NOT ((NOT comp_pat(28)) XOR nlli11O))) AND (NOT ((NOT comp_pat(29)) XOR nlli10i))) AND (NOT ((NOT comp_pat(30)) XOR nlli10l))) AND (NOT ((NOT comp_pat(31)) XOR nlli10O))); + n11iiii <= ((((((((NOT (comp_pat(24) XOR nll0OiO)) AND (NOT (comp_pat(25) XOR nll0OOl))) AND (NOT (comp_pat(26) XOR nll0OOO))) AND (NOT (comp_pat(27) XOR nlli11i))) AND (NOT (comp_pat(28) XOR nlli11l))) AND (NOT (comp_pat(29) XOR nlli11O))) AND (NOT (comp_pat(30) XOR nlli10i))) AND (NOT (comp_pat(31) XOR nlli10l))); + n11iiil <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0OiO)) AND (NOT ((NOT comp_pat(25)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(26)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(27)) XOR nlli11i))) AND (NOT ((NOT comp_pat(28)) XOR nlli11l))) AND (NOT ((NOT comp_pat(29)) XOR nlli11O))) AND (NOT ((NOT comp_pat(30)) XOR nlli10i))) AND (NOT ((NOT comp_pat(31)) XOR nlli10l))); + n11iiiO <= (n11l0li AND (wire_w_lg_w_lg_comp_pat_porn5035w5036w(0) AND wire_w_lg_w_lg_comp_pat_porn5037w5038w(0))); + n11iili <= ((((((((NOT (comp_pat(16) XOR nll0lOO)) AND (NOT (comp_pat(17) XOR nll0O1i))) AND (NOT (comp_pat(18) XOR nll0O1l))) AND (NOT (comp_pat(19) XOR nll0O1O))) AND (NOT (comp_pat(20) XOR nll0O0i))) AND (NOT (comp_pat(21) XOR nll0O0l))) AND (NOT (comp_pat(22) XOR nll0O0O))) AND (NOT (comp_pat(23) XOR nll0Oii))); + n11iill <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0lOO)) AND (NOT ((NOT comp_pat(17)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(18)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(19)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(20)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(21)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(22)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(23)) XOR nll0Oii))); + n11iilO <= ((((((((NOT (comp_pat(24) XOR nll0Oil)) AND (NOT (comp_pat(25) XOR nll0OiO))) AND (NOT (comp_pat(26) XOR nll0OOl))) AND (NOT (comp_pat(27) XOR nll0OOO))) AND (NOT (comp_pat(28) XOR nlli11i))) AND (NOT (comp_pat(29) XOR nlli11l))) AND (NOT (comp_pat(30) XOR nlli11O))) AND (NOT (comp_pat(31) XOR nlli10i))); + n11iiOi <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0Oil)) AND (NOT ((NOT comp_pat(25)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(26)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(27)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(28)) XOR nlli11i))) AND (NOT ((NOT comp_pat(29)) XOR nlli11l))) AND (NOT ((NOT comp_pat(30)) XOR nlli11O))) AND (NOT ((NOT comp_pat(31)) XOR nlli10i))); + n11iiOl <= (n11l0Oi AND (wire_w_lg_w_lg_comp_pat_porn5029w5030w(0) AND wire_w_lg_w_lg_comp_pat_porn5031w5032w(0))); + n11iiOO <= ((((((((NOT (comp_pat(16) XOR nll0lOl)) AND (NOT (comp_pat(17) XOR nll0lOO))) AND (NOT (comp_pat(18) XOR nll0O1i))) AND (NOT (comp_pat(19) XOR nll0O1l))) AND (NOT (comp_pat(20) XOR nll0O1O))) AND (NOT (comp_pat(21) XOR nll0O0i))) AND (NOT (comp_pat(22) XOR nll0O0l))) AND (NOT (comp_pat(23) XOR nll0O0O))); + n11il0i <= (n11li1i AND (wire_w_lg_w_lg_comp_pat_porn5023w5024w(0) AND wire_w_lg_w_lg_comp_pat_porn5025w5026w(0))); + n11il0l <= ((((((((NOT (comp_pat(16) XOR nll0lOi)) AND (NOT (comp_pat(17) XOR nll0lOl))) AND (NOT (comp_pat(18) XOR nll0lOO))) AND (NOT (comp_pat(19) XOR nll0O1i))) AND (NOT (comp_pat(20) XOR nll0O1l))) AND (NOT (comp_pat(21) XOR nll0O1O))) AND (NOT (comp_pat(22) XOR nll0O0i))) AND (NOT (comp_pat(23) XOR nll0O0l))); + n11il0O <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0lOi)) AND (NOT ((NOT comp_pat(17)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(18)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(19)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(20)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(21)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(22)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(23)) XOR nll0O0l))); + n11il1i <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0lOl)) AND (NOT ((NOT comp_pat(17)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(18)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(19)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(20)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(21)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(22)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(23)) XOR nll0O0O))); + n11il1l <= ((((((((NOT (comp_pat(24) XOR nll0Oii)) AND (NOT (comp_pat(25) XOR nll0Oil))) AND (NOT (comp_pat(26) XOR nll0OiO))) AND (NOT (comp_pat(27) XOR nll0OOl))) AND (NOT (comp_pat(28) XOR nll0OOO))) AND (NOT (comp_pat(29) XOR nlli11i))) AND (NOT (comp_pat(30) XOR nlli11l))) AND (NOT (comp_pat(31) XOR nlli11O))); + n11il1O <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0Oii)) AND (NOT ((NOT comp_pat(25)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(26)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(27)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(28)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(29)) XOR nlli11i))) AND (NOT ((NOT comp_pat(30)) XOR nlli11l))) AND (NOT ((NOT comp_pat(31)) XOR nlli11O))); + n11ilii <= ((((((((NOT (comp_pat(24) XOR nll0O0O)) AND (NOT (comp_pat(25) XOR nll0Oii))) AND (NOT (comp_pat(26) XOR nll0Oil))) AND (NOT (comp_pat(27) XOR nll0OiO))) AND (NOT (comp_pat(28) XOR nll0OOl))) AND (NOT (comp_pat(29) XOR nll0OOO))) AND (NOT (comp_pat(30) XOR nlli11i))) AND (NOT (comp_pat(31) XOR nlli11l))); + n11ilil <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0O0O)) AND (NOT ((NOT comp_pat(25)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(26)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(27)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(28)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(29)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(30)) XOR nlli11i))) AND (NOT ((NOT comp_pat(31)) XOR nlli11l))); + n11iliO <= (n11li0i AND (wire_w_lg_w_lg_comp_pat_porn5017w5018w(0) AND wire_w_lg_w_lg_comp_pat_porn5019w5020w(0))); + n11illi <= ((((((((NOT (comp_pat(16) XOR nll0llO)) AND (NOT (comp_pat(17) XOR nll0lOi))) AND (NOT (comp_pat(18) XOR nll0lOl))) AND (NOT (comp_pat(19) XOR nll0lOO))) AND (NOT (comp_pat(20) XOR nll0O1i))) AND (NOT (comp_pat(21) XOR nll0O1l))) AND (NOT (comp_pat(22) XOR nll0O1O))) AND (NOT (comp_pat(23) XOR nll0O0i))); + n11illl <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0llO)) AND (NOT ((NOT comp_pat(17)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(18)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(19)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(20)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(21)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(22)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(23)) XOR nll0O0i))); + n11illO <= ((((((((NOT (comp_pat(24) XOR nll0O0l)) AND (NOT (comp_pat(25) XOR nll0O0O))) AND (NOT (comp_pat(26) XOR nll0Oii))) AND (NOT (comp_pat(27) XOR nll0Oil))) AND (NOT (comp_pat(28) XOR nll0OiO))) AND (NOT (comp_pat(29) XOR nll0OOl))) AND (NOT (comp_pat(30) XOR nll0OOO))) AND (NOT (comp_pat(31) XOR nlli11i))); + n11ilOi <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0O0l)) AND (NOT ((NOT comp_pat(25)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(26)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(27)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(28)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(29)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(30)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(31)) XOR nlli11i))); + n11ilOl <= (n11liii AND (wire_w_lg_w_lg_comp_pat_porn5011w5012w(0) AND wire_w_lg_w_lg_comp_pat_porn5013w5014w(0))); + n11ilOO <= ((((((((NOT (comp_pat(16) XOR nll0lll)) AND (NOT (comp_pat(17) XOR nll0llO))) AND (NOT (comp_pat(18) XOR nll0lOi))) AND (NOT (comp_pat(19) XOR nll0lOl))) AND (NOT (comp_pat(20) XOR nll0lOO))) AND (NOT (comp_pat(21) XOR nll0O1i))) AND (NOT (comp_pat(22) XOR nll0O1l))) AND (NOT (comp_pat(23) XOR nll0O1O))); + n11iO0i <= (n11lili AND (wire_w_lg_w_lg_comp_pat_porn5005w5006w(0) AND wire_w_lg_w_lg_comp_pat_porn5007w5008w(0))); + n11iO0l <= ((((((((NOT (comp_pat(16) XOR nll0lli)) AND (NOT (comp_pat(17) XOR nll0lll))) AND (NOT (comp_pat(18) XOR nll0llO))) AND (NOT (comp_pat(19) XOR nll0lOi))) AND (NOT (comp_pat(20) XOR nll0lOl))) AND (NOT (comp_pat(21) XOR nll0lOO))) AND (NOT (comp_pat(22) XOR nll0O1i))) AND (NOT (comp_pat(23) XOR nll0O1l))); + n11iO0O <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0lli)) AND (NOT ((NOT comp_pat(17)) XOR nll0lll))) AND (NOT ((NOT comp_pat(18)) XOR nll0llO))) AND (NOT ((NOT comp_pat(19)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(20)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(21)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(22)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(23)) XOR nll0O1l))); + n11iO1i <= ((((((((NOT ((NOT comp_pat(16)) XOR nll0lll)) AND (NOT ((NOT comp_pat(17)) XOR nll0llO))) AND (NOT ((NOT comp_pat(18)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(19)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(20)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(21)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(22)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(23)) XOR nll0O1O))); + n11iO1l <= ((((((((NOT (comp_pat(24) XOR nll0O0i)) AND (NOT (comp_pat(25) XOR nll0O0l))) AND (NOT (comp_pat(26) XOR nll0O0O))) AND (NOT (comp_pat(27) XOR nll0Oii))) AND (NOT (comp_pat(28) XOR nll0Oil))) AND (NOT (comp_pat(29) XOR nll0OiO))) AND (NOT (comp_pat(30) XOR nll0OOl))) AND (NOT (comp_pat(31) XOR nll0OOO))); + n11iO1O <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0O0i)) AND (NOT ((NOT comp_pat(25)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(26)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(27)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(28)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(29)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(30)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(31)) XOR nll0OOO))); + n11iOii <= ((((((((NOT (comp_pat(24) XOR nll0O1O)) AND (NOT (comp_pat(25) XOR nll0O0i))) AND (NOT (comp_pat(26) XOR nll0O0l))) AND (NOT (comp_pat(27) XOR nll0O0O))) AND (NOT (comp_pat(28) XOR nll0Oii))) AND (NOT (comp_pat(29) XOR nll0Oil))) AND (NOT (comp_pat(30) XOR nll0OiO))) AND (NOT (comp_pat(31) XOR nll0OOl))); + n11iOil <= ((((((((NOT ((NOT comp_pat(24)) XOR nll0O1O)) AND (NOT ((NOT comp_pat(25)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(26)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(27)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(28)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(29)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(30)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(31)) XOR nll0OOl))); + n11iOiO <= (((((((((((((((n11lili OR n11liii) OR n11li0i) OR n11li1i) OR n11l0Oi) OR n11l0li) OR n11l0ii) OR n11l00i) OR n11l01i) OR n11l1Oi) OR n11l1li) OR n11l1ii) OR n11l10i) OR n11l11i) OR n11iOOi) OR n11iOli); + n11iOli <= (n11liOl AND ((comp_pat_porn AND n11iOlO) OR n11iOll)); + n11iOll <= ((((((((NOT (comp_pat(8) XOR nll0O1l)) AND (NOT (comp_pat(9) XOR nll0O1O))) AND (NOT (comp_pat(10) XOR nll0O0i))) AND (NOT (comp_pat(11) XOR nll0O0l))) AND (NOT (comp_pat(12) XOR nll0O0O))) AND (NOT (comp_pat(13) XOR nll0Oii))) AND (NOT (comp_pat(14) XOR nll0Oil))) AND (NOT (comp_pat(15) XOR nll0OiO))); + n11iOlO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0O1l)) AND (NOT ((NOT comp_pat(9)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(10)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(11)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(12)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(13)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(14)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(15)) XOR nll0OiO))); + n11iOOi <= (n11ll1l AND ((comp_pat_porn AND n11iOOO) OR n11iOOl)); + n11iOOl <= ((((((((NOT (comp_pat(8) XOR nll0O1i)) AND (NOT (comp_pat(9) XOR nll0O1l))) AND (NOT (comp_pat(10) XOR nll0O1O))) AND (NOT (comp_pat(11) XOR nll0O0i))) AND (NOT (comp_pat(12) XOR nll0O0l))) AND (NOT (comp_pat(13) XOR nll0O0O))) AND (NOT (comp_pat(14) XOR nll0Oii))) AND (NOT (comp_pat(15) XOR nll0Oil))); + n11iOOO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0O1i)) AND (NOT ((NOT comp_pat(9)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(10)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(11)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(12)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(13)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(14)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(15)) XOR nll0Oil))); + n11l00i <= (n11lOil AND ((comp_pat_porn AND n11l00O) OR n11l00l)); + n11l00l <= ((((((((NOT (comp_pat(8) XOR nll0liO)) AND (NOT (comp_pat(9) XOR nll0lli))) AND (NOT (comp_pat(10) XOR nll0lll))) AND (NOT (comp_pat(11) XOR nll0llO))) AND (NOT (comp_pat(12) XOR nll0lOi))) AND (NOT (comp_pat(13) XOR nll0lOl))) AND (NOT (comp_pat(14) XOR nll0lOO))) AND (NOT (comp_pat(15) XOR nll0O1i))); + n11l00O <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0liO)) AND (NOT ((NOT comp_pat(9)) XOR nll0lli))) AND (NOT ((NOT comp_pat(10)) XOR nll0lll))) AND (NOT ((NOT comp_pat(11)) XOR nll0llO))) AND (NOT ((NOT comp_pat(12)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(13)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(14)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(15)) XOR nll0O1i))); + n11l01i <= (n11lO0l AND ((comp_pat_porn AND n11l01O) OR n11l01l)); + n11l01l <= ((((((((NOT (comp_pat(8) XOR nll0lli)) AND (NOT (comp_pat(9) XOR nll0lll))) AND (NOT (comp_pat(10) XOR nll0llO))) AND (NOT (comp_pat(11) XOR nll0lOi))) AND (NOT (comp_pat(12) XOR nll0lOl))) AND (NOT (comp_pat(13) XOR nll0lOO))) AND (NOT (comp_pat(14) XOR nll0O1i))) AND (NOT (comp_pat(15) XOR nll0O1l))); + n11l01O <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0lli)) AND (NOT ((NOT comp_pat(9)) XOR nll0lll))) AND (NOT ((NOT comp_pat(10)) XOR nll0llO))) AND (NOT ((NOT comp_pat(11)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(12)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(13)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(14)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(15)) XOR nll0O1l))); + n11l0ii <= (n11lOll AND ((comp_pat_porn AND n11l0iO) OR n11l0il)); + n11l0il <= ((((((((NOT (comp_pat(8) XOR nll0l0i)) AND (NOT (comp_pat(9) XOR nll0liO))) AND (NOT (comp_pat(10) XOR nll0lli))) AND (NOT (comp_pat(11) XOR nll0lll))) AND (NOT (comp_pat(12) XOR nll0llO))) AND (NOT (comp_pat(13) XOR nll0lOi))) AND (NOT (comp_pat(14) XOR nll0lOl))) AND (NOT (comp_pat(15) XOR nll0lOO))); + n11l0iO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0l0i)) AND (NOT ((NOT comp_pat(9)) XOR nll0liO))) AND (NOT ((NOT comp_pat(10)) XOR nll0lli))) AND (NOT ((NOT comp_pat(11)) XOR nll0lll))) AND (NOT ((NOT comp_pat(12)) XOR nll0llO))) AND (NOT ((NOT comp_pat(13)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(14)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(15)) XOR nll0lOO))); + n11l0li <= (n11lOOl AND ((comp_pat_porn AND n11l0lO) OR n11l0ll)); + n11l0ll <= ((((((((NOT (comp_pat(8) XOR nll0l1O)) AND (NOT (comp_pat(9) XOR nll0l0i))) AND (NOT (comp_pat(10) XOR nll0liO))) AND (NOT (comp_pat(11) XOR nll0lli))) AND (NOT (comp_pat(12) XOR nll0lll))) AND (NOT (comp_pat(13) XOR nll0llO))) AND (NOT (comp_pat(14) XOR nll0lOi))) AND (NOT (comp_pat(15) XOR nll0lOl))); + n11l0lO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0l1O)) AND (NOT ((NOT comp_pat(9)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(10)) XOR nll0liO))) AND (NOT ((NOT comp_pat(11)) XOR nll0lli))) AND (NOT ((NOT comp_pat(12)) XOR nll0lll))) AND (NOT ((NOT comp_pat(13)) XOR nll0llO))) AND (NOT ((NOT comp_pat(14)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(15)) XOR nll0lOl))); + n11l0Oi <= (n11O11l AND ((comp_pat_porn AND n11l0OO) OR n11l0Ol)); + n11l0Ol <= ((((((((NOT (comp_pat(8) XOR nll0l1l)) AND (NOT (comp_pat(9) XOR nll0l1O))) AND (NOT (comp_pat(10) XOR nll0l0i))) AND (NOT (comp_pat(11) XOR nll0liO))) AND (NOT (comp_pat(12) XOR nll0lli))) AND (NOT (comp_pat(13) XOR nll0lll))) AND (NOT (comp_pat(14) XOR nll0llO))) AND (NOT (comp_pat(15) XOR nll0lOi))); + n11l0OO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0l1l)) AND (NOT ((NOT comp_pat(9)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(10)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(11)) XOR nll0liO))) AND (NOT ((NOT comp_pat(12)) XOR nll0lli))) AND (NOT ((NOT comp_pat(13)) XOR nll0lll))) AND (NOT ((NOT comp_pat(14)) XOR nll0llO))) AND (NOT ((NOT comp_pat(15)) XOR nll0lOi))); + n11l10i <= (n11llil AND ((comp_pat_porn AND n11l10O) OR n11l10l)); + n11l10l <= ((((((((NOT (comp_pat(8) XOR nll0lOl)) AND (NOT (comp_pat(9) XOR nll0lOO))) AND (NOT (comp_pat(10) XOR nll0O1i))) AND (NOT (comp_pat(11) XOR nll0O1l))) AND (NOT (comp_pat(12) XOR nll0O1O))) AND (NOT (comp_pat(13) XOR nll0O0i))) AND (NOT (comp_pat(14) XOR nll0O0l))) AND (NOT (comp_pat(15) XOR nll0O0O))); + n11l10O <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0lOl)) AND (NOT ((NOT comp_pat(9)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(10)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(11)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(12)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(13)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(14)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(15)) XOR nll0O0O))); + n11l11i <= (n11ll0l AND ((comp_pat_porn AND n11l11O) OR n11l11l)); + n11l11l <= ((((((((NOT (comp_pat(8) XOR nll0lOO)) AND (NOT (comp_pat(9) XOR nll0O1i))) AND (NOT (comp_pat(10) XOR nll0O1l))) AND (NOT (comp_pat(11) XOR nll0O1O))) AND (NOT (comp_pat(12) XOR nll0O0i))) AND (NOT (comp_pat(13) XOR nll0O0l))) AND (NOT (comp_pat(14) XOR nll0O0O))) AND (NOT (comp_pat(15) XOR nll0Oii))); + n11l11O <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0lOO)) AND (NOT ((NOT comp_pat(9)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(10)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(11)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(12)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(13)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(14)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(15)) XOR nll0Oii))); + n11l1ii <= (n11llll AND ((comp_pat_porn AND n11l1iO) OR n11l1il)); + n11l1il <= ((((((((NOT (comp_pat(8) XOR nll0lOi)) AND (NOT (comp_pat(9) XOR nll0lOl))) AND (NOT (comp_pat(10) XOR nll0lOO))) AND (NOT (comp_pat(11) XOR nll0O1i))) AND (NOT (comp_pat(12) XOR nll0O1l))) AND (NOT (comp_pat(13) XOR nll0O1O))) AND (NOT (comp_pat(14) XOR nll0O0i))) AND (NOT (comp_pat(15) XOR nll0O0l))); + n11l1iO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0lOi)) AND (NOT ((NOT comp_pat(9)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(10)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(11)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(12)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(13)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(14)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(15)) XOR nll0O0l))); + n11l1li <= (n11llOl AND ((comp_pat_porn AND n11l1lO) OR n11l1ll)); + n11l1ll <= ((((((((NOT (comp_pat(8) XOR nll0llO)) AND (NOT (comp_pat(9) XOR nll0lOi))) AND (NOT (comp_pat(10) XOR nll0lOl))) AND (NOT (comp_pat(11) XOR nll0lOO))) AND (NOT (comp_pat(12) XOR nll0O1i))) AND (NOT (comp_pat(13) XOR nll0O1l))) AND (NOT (comp_pat(14) XOR nll0O1O))) AND (NOT (comp_pat(15) XOR nll0O0i))); + n11l1lO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0llO)) AND (NOT ((NOT comp_pat(9)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(10)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(11)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(12)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(13)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(14)) XOR nll0O1O))) AND (NOT ((NOT comp_pat(15)) XOR nll0O0i))); + n11l1Oi <= (n11lO1l AND ((comp_pat_porn AND n11l1OO) OR n11l1Ol)); + n11l1Ol <= ((((((((NOT (comp_pat(8) XOR nll0lll)) AND (NOT (comp_pat(9) XOR nll0llO))) AND (NOT (comp_pat(10) XOR nll0lOi))) AND (NOT (comp_pat(11) XOR nll0lOl))) AND (NOT (comp_pat(12) XOR nll0lOO))) AND (NOT (comp_pat(13) XOR nll0O1i))) AND (NOT (comp_pat(14) XOR nll0O1l))) AND (NOT (comp_pat(15) XOR nll0O1O))); + n11l1OO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0lll)) AND (NOT ((NOT comp_pat(9)) XOR nll0llO))) AND (NOT ((NOT comp_pat(10)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(11)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(12)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(13)) XOR nll0O1i))) AND (NOT ((NOT comp_pat(14)) XOR nll0O1l))) AND (NOT ((NOT comp_pat(15)) XOR nll0O1O))); + n11li0i <= (n11O1il AND ((comp_pat_porn AND n11li0O) OR n11li0l)); + n11li0l <= ((((((((NOT (comp_pat(8) XOR nll0iOO)) AND (NOT (comp_pat(9) XOR nll0l1i))) AND (NOT (comp_pat(10) XOR nll0l1l))) AND (NOT (comp_pat(11) XOR nll0l1O))) AND (NOT (comp_pat(12) XOR nll0l0i))) AND (NOT (comp_pat(13) XOR nll0liO))) AND (NOT (comp_pat(14) XOR nll0lli))) AND (NOT (comp_pat(15) XOR nll0lll))); + n11li0O <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0iOO)) AND (NOT ((NOT comp_pat(9)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(10)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(11)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(12)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(13)) XOR nll0liO))) AND (NOT ((NOT comp_pat(14)) XOR nll0lli))) AND (NOT ((NOT comp_pat(15)) XOR nll0lll))); + n11li1i <= (n11O10l AND ((comp_pat_porn AND n11li1O) OR n11li1l)); + n11li1l <= ((((((((NOT (comp_pat(8) XOR nll0l1i)) AND (NOT (comp_pat(9) XOR nll0l1l))) AND (NOT (comp_pat(10) XOR nll0l1O))) AND (NOT (comp_pat(11) XOR nll0l0i))) AND (NOT (comp_pat(12) XOR nll0liO))) AND (NOT (comp_pat(13) XOR nll0lli))) AND (NOT (comp_pat(14) XOR nll0lll))) AND (NOT (comp_pat(15) XOR nll0llO))); + n11li1O <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0l1i)) AND (NOT ((NOT comp_pat(9)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(10)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(11)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(12)) XOR nll0liO))) AND (NOT ((NOT comp_pat(13)) XOR nll0lli))) AND (NOT ((NOT comp_pat(14)) XOR nll0lll))) AND (NOT ((NOT comp_pat(15)) XOR nll0llO))); + n11liii <= (n11O1ll AND ((comp_pat_porn AND n11liiO) OR n11liil)); + n11liil <= ((((((((NOT (comp_pat(8) XOR nll0iOl)) AND (NOT (comp_pat(9) XOR nll0iOO))) AND (NOT (comp_pat(10) XOR nll0l1i))) AND (NOT (comp_pat(11) XOR nll0l1l))) AND (NOT (comp_pat(12) XOR nll0l1O))) AND (NOT (comp_pat(13) XOR nll0l0i))) AND (NOT (comp_pat(14) XOR nll0liO))) AND (NOT (comp_pat(15) XOR nll0lli))); + n11liiO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0iOl)) AND (NOT ((NOT comp_pat(9)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(10)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(11)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(12)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(13)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(14)) XOR nll0liO))) AND (NOT ((NOT comp_pat(15)) XOR nll0lli))); + n11lili <= (n11O1Ol AND ((comp_pat_porn AND n11lilO) OR n11lill)); + n11lill <= ((((((((NOT (comp_pat(8) XOR nll0iOi)) AND (NOT (comp_pat(9) XOR nll0iOl))) AND (NOT (comp_pat(10) XOR nll0iOO))) AND (NOT (comp_pat(11) XOR nll0l1i))) AND (NOT (comp_pat(12) XOR nll0l1l))) AND (NOT (comp_pat(13) XOR nll0l1O))) AND (NOT (comp_pat(14) XOR nll0l0i))) AND (NOT (comp_pat(15) XOR nll0liO))); + n11lilO <= ((((((((NOT ((NOT comp_pat(8)) XOR nll0iOi)) AND (NOT ((NOT comp_pat(9)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(10)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(11)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(12)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(13)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(14)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(15)) XOR nll0liO))); + n11liOi <= (((((((((((((((n11O1Ol OR n11O1ll) OR n11O1il) OR n11O10l) OR n11O11l) OR n11lOOl) OR n11lOll) OR n11lOil) OR n11lO0l) OR n11lO1l) OR n11llOl) OR n11llll) OR n11llil) OR n11ll0l) OR n11ll1l) OR n11liOl); + n11liOl <= ((comp_pat_porn AND n11ll1i) OR n11liOO); + n11liOO <= ((((((((NOT (comp_pat(0) XOR nll0liO)) AND (NOT (comp_pat(1) XOR nll0lli))) AND (NOT (comp_pat(2) XOR nll0lll))) AND (NOT (comp_pat(3) XOR nll0llO))) AND (NOT (comp_pat(4) XOR nll0lOi))) AND (NOT (comp_pat(5) XOR nll0lOl))) AND (NOT (comp_pat(6) XOR nll0lOO))) AND (NOT (comp_pat(7) XOR nll0O1i))); + n11ll0i <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0l0i)) AND (NOT ((NOT comp_pat(1)) XOR nll0liO))) AND (NOT ((NOT comp_pat(2)) XOR nll0lli))) AND (NOT ((NOT comp_pat(3)) XOR nll0lll))) AND (NOT ((NOT comp_pat(4)) XOR nll0llO))) AND (NOT ((NOT comp_pat(5)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(7)) XOR nll0lOO))); + n11ll0l <= ((comp_pat_porn AND n11llii) OR n11ll0O); + n11ll0O <= ((((((((NOT (comp_pat(0) XOR nll0l1O)) AND (NOT (comp_pat(1) XOR nll0l0i))) AND (NOT (comp_pat(2) XOR nll0liO))) AND (NOT (comp_pat(3) XOR nll0lli))) AND (NOT (comp_pat(4) XOR nll0lll))) AND (NOT (comp_pat(5) XOR nll0llO))) AND (NOT (comp_pat(6) XOR nll0lOi))) AND (NOT (comp_pat(7) XOR nll0lOl))); + n11ll1i <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0liO)) AND (NOT ((NOT comp_pat(1)) XOR nll0lli))) AND (NOT ((NOT comp_pat(2)) XOR nll0lll))) AND (NOT ((NOT comp_pat(3)) XOR nll0llO))) AND (NOT ((NOT comp_pat(4)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(5)) XOR nll0lOl))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOO))) AND (NOT ((NOT comp_pat(7)) XOR nll0O1i))); + n11ll1l <= ((comp_pat_porn AND n11ll0i) OR n11ll1O); + n11ll1O <= ((((((((NOT (comp_pat(0) XOR nll0l0i)) AND (NOT (comp_pat(1) XOR nll0liO))) AND (NOT (comp_pat(2) XOR nll0lli))) AND (NOT (comp_pat(3) XOR nll0lll))) AND (NOT (comp_pat(4) XOR nll0llO))) AND (NOT (comp_pat(5) XOR nll0lOi))) AND (NOT (comp_pat(6) XOR nll0lOl))) AND (NOT (comp_pat(7) XOR nll0lOO))); + n11llii <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0l1O)) AND (NOT ((NOT comp_pat(1)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(2)) XOR nll0liO))) AND (NOT ((NOT comp_pat(3)) XOR nll0lli))) AND (NOT ((NOT comp_pat(4)) XOR nll0lll))) AND (NOT ((NOT comp_pat(5)) XOR nll0llO))) AND (NOT ((NOT comp_pat(6)) XOR nll0lOi))) AND (NOT ((NOT comp_pat(7)) XOR nll0lOl))); + n11llil <= ((comp_pat_porn AND n11llli) OR n11lliO); + n11lliO <= ((((((((NOT (comp_pat(0) XOR nll0l1l)) AND (NOT (comp_pat(1) XOR nll0l1O))) AND (NOT (comp_pat(2) XOR nll0l0i))) AND (NOT (comp_pat(3) XOR nll0liO))) AND (NOT (comp_pat(4) XOR nll0lli))) AND (NOT (comp_pat(5) XOR nll0lll))) AND (NOT (comp_pat(6) XOR nll0llO))) AND (NOT (comp_pat(7) XOR nll0lOi))); + n11llli <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0l1l)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(2)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(3)) XOR nll0liO))) AND (NOT ((NOT comp_pat(4)) XOR nll0lli))) AND (NOT ((NOT comp_pat(5)) XOR nll0lll))) AND (NOT ((NOT comp_pat(6)) XOR nll0llO))) AND (NOT ((NOT comp_pat(7)) XOR nll0lOi))); + n11llll <= ((comp_pat_porn AND n11llOi) OR n11lllO); + n11lllO <= ((((((((NOT (comp_pat(0) XOR nll0l1i)) AND (NOT (comp_pat(1) XOR nll0l1l))) AND (NOT (comp_pat(2) XOR nll0l1O))) AND (NOT (comp_pat(3) XOR nll0l0i))) AND (NOT (comp_pat(4) XOR nll0liO))) AND (NOT (comp_pat(5) XOR nll0lli))) AND (NOT (comp_pat(6) XOR nll0lll))) AND (NOT (comp_pat(7) XOR nll0llO))); + n11llOi <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0l1i)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(3)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(4)) XOR nll0liO))) AND (NOT ((NOT comp_pat(5)) XOR nll0lli))) AND (NOT ((NOT comp_pat(6)) XOR nll0lll))) AND (NOT ((NOT comp_pat(7)) XOR nll0llO))); + n11llOl <= ((comp_pat_porn AND n11lO1i) OR n11llOO); + n11llOO <= ((((((((NOT (comp_pat(0) XOR nll0iOO)) AND (NOT (comp_pat(1) XOR nll0l1i))) AND (NOT (comp_pat(2) XOR nll0l1l))) AND (NOT (comp_pat(3) XOR nll0l1O))) AND (NOT (comp_pat(4) XOR nll0l0i))) AND (NOT (comp_pat(5) XOR nll0liO))) AND (NOT (comp_pat(6) XOR nll0lli))) AND (NOT (comp_pat(7) XOR nll0lll))); + n11lO0i <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0iOl)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(5)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(6)) XOR nll0liO))) AND (NOT ((NOT comp_pat(7)) XOR nll0lli))); + n11lO0l <= ((comp_pat_porn AND n11lOii) OR n11lO0O); + n11lO0O <= ((((((((NOT (comp_pat(0) XOR nll0iOi)) AND (NOT (comp_pat(1) XOR nll0iOl))) AND (NOT (comp_pat(2) XOR nll0iOO))) AND (NOT (comp_pat(3) XOR nll0l1i))) AND (NOT (comp_pat(4) XOR nll0l1l))) AND (NOT (comp_pat(5) XOR nll0l1O))) AND (NOT (comp_pat(6) XOR nll0l0i))) AND (NOT (comp_pat(7) XOR nll0liO))); + n11lO1i <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0iOO)) AND (NOT ((NOT comp_pat(1)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(2)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(4)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(5)) XOR nll0liO))) AND (NOT ((NOT comp_pat(6)) XOR nll0lli))) AND (NOT ((NOT comp_pat(7)) XOR nll0lll))); + n11lO1l <= ((comp_pat_porn AND n11lO0i) OR n11lO1O); + n11lO1O <= ((((((((NOT (comp_pat(0) XOR nll0iOl)) AND (NOT (comp_pat(1) XOR nll0iOO))) AND (NOT (comp_pat(2) XOR nll0l1i))) AND (NOT (comp_pat(3) XOR nll0l1l))) AND (NOT (comp_pat(4) XOR nll0l1O))) AND (NOT (comp_pat(5) XOR nll0l0i))) AND (NOT (comp_pat(6) XOR nll0liO))) AND (NOT (comp_pat(7) XOR nll0lli))); + n11lOii <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0iOi)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(3)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(6)) XOR nll0l0i))) AND (NOT ((NOT comp_pat(7)) XOR nll0liO))); + n11lOil <= ((comp_pat_porn AND n11lOli) OR n11lOiO); + n11lOiO <= ((((((((NOT (comp_pat(0) XOR nll0ilO)) AND (NOT (comp_pat(1) XOR nll0iOi))) AND (NOT (comp_pat(2) XOR nll0iOl))) AND (NOT (comp_pat(3) XOR nll0iOO))) AND (NOT (comp_pat(4) XOR nll0l1i))) AND (NOT (comp_pat(5) XOR nll0l1l))) AND (NOT (comp_pat(6) XOR nll0l1O))) AND (NOT (comp_pat(7) XOR nll0l0i))); + n11lOli <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0ilO)) AND (NOT ((NOT comp_pat(1)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(4)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1O))) AND (NOT ((NOT comp_pat(7)) XOR nll0l0i))); + n11lOll <= ((comp_pat_porn AND n11lOOi) OR n11lOlO); + n11lOlO <= ((((((((NOT (comp_pat(0) XOR nll0ill)) AND (NOT (comp_pat(1) XOR nll0ilO))) AND (NOT (comp_pat(2) XOR nll0iOi))) AND (NOT (comp_pat(3) XOR nll0iOl))) AND (NOT (comp_pat(4) XOR nll0iOO))) AND (NOT (comp_pat(5) XOR nll0l1i))) AND (NOT (comp_pat(6) XOR nll0l1l))) AND (NOT (comp_pat(7) XOR nll0l1O))); + n11lOOi <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0ill)) AND (NOT ((NOT comp_pat(1)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(2)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(5)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1l))) AND (NOT ((NOT comp_pat(7)) XOR nll0l1O))); + n11lOOl <= ((comp_pat_porn AND n11O11i) OR n11lOOO); + n11lOOO <= ((((((((NOT (comp_pat(0) XOR nll0ili)) AND (NOT (comp_pat(1) XOR nll0ill))) AND (NOT (comp_pat(2) XOR nll0ilO))) AND (NOT (comp_pat(3) XOR nll0iOi))) AND (NOT (comp_pat(4) XOR nll0iOl))) AND (NOT (comp_pat(5) XOR nll0iOO))) AND (NOT (comp_pat(6) XOR nll0l1i))) AND (NOT (comp_pat(7) XOR nll0l1l))); + n11O00i <= ((((((((((NOT (comp_pat(20) XOR nll0OOl)) AND (NOT (comp_pat(21) XOR nll0OOO))) AND (NOT (comp_pat(22) XOR nlli11i))) AND (NOT (comp_pat(23) XOR nlli11l))) AND (NOT (comp_pat(24) XOR nlli11O))) AND (NOT (comp_pat(25) XOR nlli10i))) AND (NOT (comp_pat(26) XOR nlli10l))) AND (NOT (comp_pat(27) XOR nlli10O))) AND (NOT (comp_pat(28) XOR nlli1ii))) AND (NOT (comp_pat(29) XOR nlli1il))); + n11O00l <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0OOl)) AND (NOT ((NOT comp_pat(21)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(22)) XOR nlli11i))) AND (NOT ((NOT comp_pat(23)) XOR nlli11l))) AND (NOT ((NOT comp_pat(24)) XOR nlli11O))) AND (NOT ((NOT comp_pat(25)) XOR nlli10i))) AND (NOT ((NOT comp_pat(26)) XOR nlli10l))) AND (NOT ((NOT comp_pat(27)) XOR nlli10O))) AND (NOT ((NOT comp_pat(28)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(29)) XOR nlli1il))); + n11O00O <= ((((((((((NOT (comp_pat(30) XOR nlli1iO)) AND (NOT (comp_pat(31) XOR nlli1li))) AND (NOT (comp_pat(32) XOR nlli1ll))) AND (NOT (comp_pat(33) XOR nlli1lO))) AND (NOT (comp_pat(34) XOR nlli1Oi))) AND (NOT (comp_pat(35) XOR nlli1Ol))) AND (NOT (comp_pat(36) XOR nlli1OO))) AND (NOT (comp_pat(37) XOR nlli01i))) AND (NOT (comp_pat(38) XOR nlli01l))) AND (NOT (comp_pat(39) XOR nlli01O))); + n11O01i <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0i0l)) AND (NOT ((NOT comp_pat(1)) XOR nll0i0O))) AND (NOT ((NOT comp_pat(2)) XOR nll0iii))) AND (NOT ((NOT comp_pat(3)) XOR nll0iil))) AND (NOT ((NOT comp_pat(4)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(5)) XOR nll0ili))) AND (NOT ((NOT comp_pat(6)) XOR nll0ill))) AND (NOT ((NOT comp_pat(7)) XOR nll0ilO))); + n11O01l <= (((((((((((((((((((n101iil OR n101i1O) OR n1010Oi) OR n1010il) OR n10101O) OR n1011Oi) OR n1011il) OR n10111O) OR n11OOOi) OR n11OOil) OR n11OO1O) OR n11OlOi) OR n11Olil) OR n11Ol1O) OR n11OiOi) OR n11Oiil) OR n11Oi1O) OR n11O0Oi) OR n11O0il) OR n11O01O); + n11O01O <= (n101iOl AND (wire_w_lg_w_lg_comp_pat_porn4870w4871w(0) AND wire_w_lg_w_lg_comp_pat_porn4872w4873w(0))); + n11O0ii <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli1iO)) AND (NOT ((NOT comp_pat(31)) XOR nlli1li))) AND (NOT ((NOT comp_pat(32)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(33)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(34)) XOR nlli1Oi))) AND (NOT ((NOT comp_pat(35)) XOR nlli1Ol))) AND (NOT ((NOT comp_pat(36)) XOR nlli1OO))) AND (NOT ((NOT comp_pat(37)) XOR nlli01i))) AND (NOT ((NOT comp_pat(38)) XOR nlli01l))) AND (NOT ((NOT comp_pat(39)) XOR nlli01O))); + n11O0il <= (n101l1l AND (wire_w_lg_w_lg_comp_pat_porn4864w4865w(0) AND wire_w_lg_w_lg_comp_pat_porn4866w4867w(0))); + n11O0iO <= ((((((((((NOT (comp_pat(20) XOR nll0OOi)) AND (NOT (comp_pat(21) XOR nll0OOl))) AND (NOT (comp_pat(22) XOR nll0OOO))) AND (NOT (comp_pat(23) XOR nlli11i))) AND (NOT (comp_pat(24) XOR nlli11l))) AND (NOT (comp_pat(25) XOR nlli11O))) AND (NOT (comp_pat(26) XOR nlli10i))) AND (NOT (comp_pat(27) XOR nlli10l))) AND (NOT (comp_pat(28) XOR nlli10O))) AND (NOT (comp_pat(29) XOR nlli1ii))); + n11O0li <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0OOi)) AND (NOT ((NOT comp_pat(21)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(22)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(23)) XOR nlli11i))) AND (NOT ((NOT comp_pat(24)) XOR nlli11l))) AND (NOT ((NOT comp_pat(25)) XOR nlli11O))) AND (NOT ((NOT comp_pat(26)) XOR nlli10i))) AND (NOT ((NOT comp_pat(27)) XOR nlli10l))) AND (NOT ((NOT comp_pat(28)) XOR nlli10O))) AND (NOT ((NOT comp_pat(29)) XOR nlli1ii))); + n11O0ll <= ((((((((((NOT (comp_pat(30) XOR nlli1il)) AND (NOT (comp_pat(31) XOR nlli1iO))) AND (NOT (comp_pat(32) XOR nlli1li))) AND (NOT (comp_pat(33) XOR nlli1ll))) AND (NOT (comp_pat(34) XOR nlli1lO))) AND (NOT (comp_pat(35) XOR nlli1Oi))) AND (NOT (comp_pat(36) XOR nlli1Ol))) AND (NOT (comp_pat(37) XOR nlli1OO))) AND (NOT (comp_pat(38) XOR nlli01i))) AND (NOT (comp_pat(39) XOR nlli01l))); + n11O0lO <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli1il)) AND (NOT ((NOT comp_pat(31)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(32)) XOR nlli1li))) AND (NOT ((NOT comp_pat(33)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(34)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(35)) XOR nlli1Oi))) AND (NOT ((NOT comp_pat(36)) XOR nlli1Ol))) AND (NOT ((NOT comp_pat(37)) XOR nlli1OO))) AND (NOT ((NOT comp_pat(38)) XOR nlli01i))) AND (NOT ((NOT comp_pat(39)) XOR nlli01l))); + n11O0Oi <= (n101l0l AND (wire_w_lg_w_lg_comp_pat_porn4858w4859w(0) AND wire_w_lg_w_lg_comp_pat_porn4860w4861w(0))); + n11O0Ol <= ((((((((((NOT (comp_pat(20) XOR nll0OlO)) AND (NOT (comp_pat(21) XOR nll0OOi))) AND (NOT (comp_pat(22) XOR nll0OOl))) AND (NOT (comp_pat(23) XOR nll0OOO))) AND (NOT (comp_pat(24) XOR nlli11i))) AND (NOT (comp_pat(25) XOR nlli11l))) AND (NOT (comp_pat(26) XOR nlli11O))) AND (NOT (comp_pat(27) XOR nlli10i))) AND (NOT (comp_pat(28) XOR nlli10l))) AND (NOT (comp_pat(29) XOR nlli10O))); + n11O0OO <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0OlO)) AND (NOT ((NOT comp_pat(21)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(22)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(23)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(24)) XOR nlli11i))) AND (NOT ((NOT comp_pat(25)) XOR nlli11l))) AND (NOT ((NOT comp_pat(26)) XOR nlli11O))) AND (NOT ((NOT comp_pat(27)) XOR nlli10i))) AND (NOT ((NOT comp_pat(28)) XOR nlli10l))) AND (NOT ((NOT comp_pat(29)) XOR nlli10O))); + n11O10i <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0iiO)) AND (NOT ((NOT comp_pat(1)) XOR nll0ili))) AND (NOT ((NOT comp_pat(2)) XOR nll0ill))) AND (NOT ((NOT comp_pat(3)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(7)) XOR nll0l1i))); + n11O10l <= ((comp_pat_porn AND n11O1ii) OR n11O10O); + n11O10O <= ((((((((NOT (comp_pat(0) XOR nll0iil)) AND (NOT (comp_pat(1) XOR nll0iiO))) AND (NOT (comp_pat(2) XOR nll0ili))) AND (NOT (comp_pat(3) XOR nll0ill))) AND (NOT (comp_pat(4) XOR nll0ilO))) AND (NOT (comp_pat(5) XOR nll0iOi))) AND (NOT (comp_pat(6) XOR nll0iOl))) AND (NOT (comp_pat(7) XOR nll0iOO))); + n11O11i <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0ili)) AND (NOT ((NOT comp_pat(1)) XOR nll0ill))) AND (NOT ((NOT comp_pat(2)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(3)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(4)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOO))) AND (NOT ((NOT comp_pat(6)) XOR nll0l1i))) AND (NOT ((NOT comp_pat(7)) XOR nll0l1l))); + n11O11l <= ((comp_pat_porn AND n11O10i) OR n11O11O); + n11O11O <= ((((((((NOT (comp_pat(0) XOR nll0iiO)) AND (NOT (comp_pat(1) XOR nll0ili))) AND (NOT (comp_pat(2) XOR nll0ill))) AND (NOT (comp_pat(3) XOR nll0ilO))) AND (NOT (comp_pat(4) XOR nll0iOi))) AND (NOT (comp_pat(5) XOR nll0iOl))) AND (NOT (comp_pat(6) XOR nll0iOO))) AND (NOT (comp_pat(7) XOR nll0l1i))); + n11O1ii <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0iil)) AND (NOT ((NOT comp_pat(1)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(2)) XOR nll0ili))) AND (NOT ((NOT comp_pat(3)) XOR nll0ill))) AND (NOT ((NOT comp_pat(4)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(5)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOl))) AND (NOT ((NOT comp_pat(7)) XOR nll0iOO))); + n11O1il <= ((comp_pat_porn AND n11O1li) OR n11O1iO); + n11O1iO <= ((((((((NOT (comp_pat(0) XOR nll0iii)) AND (NOT (comp_pat(1) XOR nll0iil))) AND (NOT (comp_pat(2) XOR nll0iiO))) AND (NOT (comp_pat(3) XOR nll0ili))) AND (NOT (comp_pat(4) XOR nll0ill))) AND (NOT (comp_pat(5) XOR nll0ilO))) AND (NOT (comp_pat(6) XOR nll0iOi))) AND (NOT (comp_pat(7) XOR nll0iOl))); + n11O1li <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0iii)) AND (NOT ((NOT comp_pat(1)) XOR nll0iil))) AND (NOT ((NOT comp_pat(2)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(3)) XOR nll0ili))) AND (NOT ((NOT comp_pat(4)) XOR nll0ill))) AND (NOT ((NOT comp_pat(5)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(6)) XOR nll0iOi))) AND (NOT ((NOT comp_pat(7)) XOR nll0iOl))); + n11O1ll <= ((comp_pat_porn AND n11O1Oi) OR n11O1lO); + n11O1lO <= ((((((((NOT (comp_pat(0) XOR nll0i0O)) AND (NOT (comp_pat(1) XOR nll0iii))) AND (NOT (comp_pat(2) XOR nll0iil))) AND (NOT (comp_pat(3) XOR nll0iiO))) AND (NOT (comp_pat(4) XOR nll0ili))) AND (NOT (comp_pat(5) XOR nll0ill))) AND (NOT (comp_pat(6) XOR nll0ilO))) AND (NOT (comp_pat(7) XOR nll0iOi))); + n11O1Oi <= ((((((((NOT ((NOT comp_pat(0)) XOR nll0i0O)) AND (NOT ((NOT comp_pat(1)) XOR nll0iii))) AND (NOT ((NOT comp_pat(2)) XOR nll0iil))) AND (NOT ((NOT comp_pat(3)) XOR nll0iiO))) AND (NOT ((NOT comp_pat(4)) XOR nll0ili))) AND (NOT ((NOT comp_pat(5)) XOR nll0ill))) AND (NOT ((NOT comp_pat(6)) XOR nll0ilO))) AND (NOT ((NOT comp_pat(7)) XOR nll0iOi))); + n11O1Ol <= ((comp_pat_porn AND n11O01i) OR n11O1OO); + n11O1OO <= ((((((((NOT (comp_pat(0) XOR nll0i0l)) AND (NOT (comp_pat(1) XOR nll0i0O))) AND (NOT (comp_pat(2) XOR nll0iii))) AND (NOT (comp_pat(3) XOR nll0iil))) AND (NOT (comp_pat(4) XOR nll0iiO))) AND (NOT (comp_pat(5) XOR nll0ili))) AND (NOT (comp_pat(6) XOR nll0ill))) AND (NOT (comp_pat(7) XOR nll0ilO))); + n11Oi0i <= ((((((((((NOT (comp_pat(20) XOR nll0Oll)) AND (NOT (comp_pat(21) XOR nll0OlO))) AND (NOT (comp_pat(22) XOR nll0OOi))) AND (NOT (comp_pat(23) XOR nll0OOl))) AND (NOT (comp_pat(24) XOR nll0OOO))) AND (NOT (comp_pat(25) XOR nlli11i))) AND (NOT (comp_pat(26) XOR nlli11l))) AND (NOT (comp_pat(27) XOR nlli11O))) AND (NOT (comp_pat(28) XOR nlli10i))) AND (NOT (comp_pat(29) XOR nlli10l))); + n11Oi0l <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0Oll)) AND (NOT ((NOT comp_pat(21)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(22)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(23)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(24)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(25)) XOR nlli11i))) AND (NOT ((NOT comp_pat(26)) XOR nlli11l))) AND (NOT ((NOT comp_pat(27)) XOR nlli11O))) AND (NOT ((NOT comp_pat(28)) XOR nlli10i))) AND (NOT ((NOT comp_pat(29)) XOR nlli10l))); + n11Oi0O <= ((((((((((NOT (comp_pat(30) XOR nlli10O)) AND (NOT (comp_pat(31) XOR nlli1ii))) AND (NOT (comp_pat(32) XOR nlli1il))) AND (NOT (comp_pat(33) XOR nlli1iO))) AND (NOT (comp_pat(34) XOR nlli1li))) AND (NOT (comp_pat(35) XOR nlli1ll))) AND (NOT (comp_pat(36) XOR nlli1lO))) AND (NOT (comp_pat(37) XOR nlli1Oi))) AND (NOT (comp_pat(38) XOR nlli1Ol))) AND (NOT (comp_pat(39) XOR nlli1OO))); + n11Oi1i <= ((((((((((NOT (comp_pat(30) XOR nlli1ii)) AND (NOT (comp_pat(31) XOR nlli1il))) AND (NOT (comp_pat(32) XOR nlli1iO))) AND (NOT (comp_pat(33) XOR nlli1li))) AND (NOT (comp_pat(34) XOR nlli1ll))) AND (NOT (comp_pat(35) XOR nlli1lO))) AND (NOT (comp_pat(36) XOR nlli1Oi))) AND (NOT (comp_pat(37) XOR nlli1Ol))) AND (NOT (comp_pat(38) XOR nlli1OO))) AND (NOT (comp_pat(39) XOR nlli01i))); + n11Oi1l <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli1ii)) AND (NOT ((NOT comp_pat(31)) XOR nlli1il))) AND (NOT ((NOT comp_pat(32)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(33)) XOR nlli1li))) AND (NOT ((NOT comp_pat(34)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(35)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(36)) XOR nlli1Oi))) AND (NOT ((NOT comp_pat(37)) XOR nlli1Ol))) AND (NOT ((NOT comp_pat(38)) XOR nlli1OO))) AND (NOT ((NOT comp_pat(39)) XOR nlli01i))); + n11Oi1O <= (n101lil AND (wire_w_lg_w_lg_comp_pat_porn4852w4853w(0) AND wire_w_lg_w_lg_comp_pat_porn4854w4855w(0))); + n11Oiii <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli10O)) AND (NOT ((NOT comp_pat(31)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(32)) XOR nlli1il))) AND (NOT ((NOT comp_pat(33)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(34)) XOR nlli1li))) AND (NOT ((NOT comp_pat(35)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(36)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(37)) XOR nlli1Oi))) AND (NOT ((NOT comp_pat(38)) XOR nlli1Ol))) AND (NOT ((NOT comp_pat(39)) XOR nlli1OO))); + n11Oiil <= (n101lll AND (wire_w_lg_w_lg_comp_pat_porn4846w4847w(0) AND wire_w_lg_w_lg_comp_pat_porn4848w4849w(0))); + n11OiiO <= ((((((((((NOT (comp_pat(20) XOR nll0Oli)) AND (NOT (comp_pat(21) XOR nll0Oll))) AND (NOT (comp_pat(22) XOR nll0OlO))) AND (NOT (comp_pat(23) XOR nll0OOi))) AND (NOT (comp_pat(24) XOR nll0OOl))) AND (NOT (comp_pat(25) XOR nll0OOO))) AND (NOT (comp_pat(26) XOR nlli11i))) AND (NOT (comp_pat(27) XOR nlli11l))) AND (NOT (comp_pat(28) XOR nlli11O))) AND (NOT (comp_pat(29) XOR nlli10i))); + n11Oili <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0Oli)) AND (NOT ((NOT comp_pat(21)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(22)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(23)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(24)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(25)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(26)) XOR nlli11i))) AND (NOT ((NOT comp_pat(27)) XOR nlli11l))) AND (NOT ((NOT comp_pat(28)) XOR nlli11O))) AND (NOT ((NOT comp_pat(29)) XOR nlli10i))); + n11Oill <= ((((((((((NOT (comp_pat(30) XOR nlli10l)) AND (NOT (comp_pat(31) XOR nlli10O))) AND (NOT (comp_pat(32) XOR nlli1ii))) AND (NOT (comp_pat(33) XOR nlli1il))) AND (NOT (comp_pat(34) XOR nlli1iO))) AND (NOT (comp_pat(35) XOR nlli1li))) AND (NOT (comp_pat(36) XOR nlli1ll))) AND (NOT (comp_pat(37) XOR nlli1lO))) AND (NOT (comp_pat(38) XOR nlli1Oi))) AND (NOT (comp_pat(39) XOR nlli1Ol))); + n11OilO <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli10l)) AND (NOT ((NOT comp_pat(31)) XOR nlli10O))) AND (NOT ((NOT comp_pat(32)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(33)) XOR nlli1il))) AND (NOT ((NOT comp_pat(34)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(35)) XOR nlli1li))) AND (NOT ((NOT comp_pat(36)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(37)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(38)) XOR nlli1Oi))) AND (NOT ((NOT comp_pat(39)) XOR nlli1Ol))); + n11OiOi <= (n101lOl AND (wire_w_lg_w_lg_comp_pat_porn4840w4841w(0) AND wire_w_lg_w_lg_comp_pat_porn4842w4843w(0))); + n11OiOl <= ((((((((((NOT (comp_pat(20) XOR nll0OiO)) AND (NOT (comp_pat(21) XOR nll0Oli))) AND (NOT (comp_pat(22) XOR nll0Oll))) AND (NOT (comp_pat(23) XOR nll0OlO))) AND (NOT (comp_pat(24) XOR nll0OOi))) AND (NOT (comp_pat(25) XOR nll0OOl))) AND (NOT (comp_pat(26) XOR nll0OOO))) AND (NOT (comp_pat(27) XOR nlli11i))) AND (NOT (comp_pat(28) XOR nlli11l))) AND (NOT (comp_pat(29) XOR nlli11O))); + n11OiOO <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0OiO)) AND (NOT ((NOT comp_pat(21)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(22)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(23)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(24)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(25)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(26)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(27)) XOR nlli11i))) AND (NOT ((NOT comp_pat(28)) XOR nlli11l))) AND (NOT ((NOT comp_pat(29)) XOR nlli11O))); + n11Ol0i <= ((((((((((NOT (comp_pat(20) XOR nll0Oil)) AND (NOT (comp_pat(21) XOR nll0OiO))) AND (NOT (comp_pat(22) XOR nll0Oli))) AND (NOT (comp_pat(23) XOR nll0Oll))) AND (NOT (comp_pat(24) XOR nll0OlO))) AND (NOT (comp_pat(25) XOR nll0OOi))) AND (NOT (comp_pat(26) XOR nll0OOl))) AND (NOT (comp_pat(27) XOR nll0OOO))) AND (NOT (comp_pat(28) XOR nlli11i))) AND (NOT (comp_pat(29) XOR nlli11l))); + n11Ol0l <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0Oil)) AND (NOT ((NOT comp_pat(21)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(22)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(23)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(24)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(25)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(26)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(27)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(28)) XOR nlli11i))) AND (NOT ((NOT comp_pat(29)) XOR nlli11l))); + n11Ol0O <= ((((((((((NOT (comp_pat(30) XOR nlli11O)) AND (NOT (comp_pat(31) XOR nlli10i))) AND (NOT (comp_pat(32) XOR nlli10l))) AND (NOT (comp_pat(33) XOR nlli10O))) AND (NOT (comp_pat(34) XOR nlli1ii))) AND (NOT (comp_pat(35) XOR nlli1il))) AND (NOT (comp_pat(36) XOR nlli1iO))) AND (NOT (comp_pat(37) XOR nlli1li))) AND (NOT (comp_pat(38) XOR nlli1ll))) AND (NOT (comp_pat(39) XOR nlli1lO))); + n11Ol1i <= ((((((((((NOT (comp_pat(30) XOR nlli10i)) AND (NOT (comp_pat(31) XOR nlli10l))) AND (NOT (comp_pat(32) XOR nlli10O))) AND (NOT (comp_pat(33) XOR nlli1ii))) AND (NOT (comp_pat(34) XOR nlli1il))) AND (NOT (comp_pat(35) XOR nlli1iO))) AND (NOT (comp_pat(36) XOR nlli1li))) AND (NOT (comp_pat(37) XOR nlli1ll))) AND (NOT (comp_pat(38) XOR nlli1lO))) AND (NOT (comp_pat(39) XOR nlli1Oi))); + n11Ol1l <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli10i)) AND (NOT ((NOT comp_pat(31)) XOR nlli10l))) AND (NOT ((NOT comp_pat(32)) XOR nlli10O))) AND (NOT ((NOT comp_pat(33)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(34)) XOR nlli1il))) AND (NOT ((NOT comp_pat(35)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(36)) XOR nlli1li))) AND (NOT ((NOT comp_pat(37)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(38)) XOR nlli1lO))) AND (NOT ((NOT comp_pat(39)) XOR nlli1Oi))); + n11Ol1O <= (n101O1l AND (wire_w_lg_w_lg_comp_pat_porn4834w4835w(0) AND wire_w_lg_w_lg_comp_pat_porn4836w4837w(0))); + n11Olii <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli11O)) AND (NOT ((NOT comp_pat(31)) XOR nlli10i))) AND (NOT ((NOT comp_pat(32)) XOR nlli10l))) AND (NOT ((NOT comp_pat(33)) XOR nlli10O))) AND (NOT ((NOT comp_pat(34)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(35)) XOR nlli1il))) AND (NOT ((NOT comp_pat(36)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(37)) XOR nlli1li))) AND (NOT ((NOT comp_pat(38)) XOR nlli1ll))) AND (NOT ((NOT comp_pat(39)) XOR nlli1lO))); + n11Olil <= (n101O0l AND (wire_w_lg_w_lg_comp_pat_porn4828w4829w(0) AND wire_w_lg_w_lg_comp_pat_porn4830w4831w(0))); + n11OliO <= ((((((((((NOT (comp_pat(20) XOR nll0Oii)) AND (NOT (comp_pat(21) XOR nll0Oil))) AND (NOT (comp_pat(22) XOR nll0OiO))) AND (NOT (comp_pat(23) XOR nll0Oli))) AND (NOT (comp_pat(24) XOR nll0Oll))) AND (NOT (comp_pat(25) XOR nll0OlO))) AND (NOT (comp_pat(26) XOR nll0OOi))) AND (NOT (comp_pat(27) XOR nll0OOl))) AND (NOT (comp_pat(28) XOR nll0OOO))) AND (NOT (comp_pat(29) XOR nlli11i))); + n11Olli <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0Oii)) AND (NOT ((NOT comp_pat(21)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(22)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(23)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(24)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(25)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(26)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(27)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(28)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(29)) XOR nlli11i))); + n11Olll <= ((((((((((NOT (comp_pat(30) XOR nlli11l)) AND (NOT (comp_pat(31) XOR nlli11O))) AND (NOT (comp_pat(32) XOR nlli10i))) AND (NOT (comp_pat(33) XOR nlli10l))) AND (NOT (comp_pat(34) XOR nlli10O))) AND (NOT (comp_pat(35) XOR nlli1ii))) AND (NOT (comp_pat(36) XOR nlli1il))) AND (NOT (comp_pat(37) XOR nlli1iO))) AND (NOT (comp_pat(38) XOR nlli1li))) AND (NOT (comp_pat(39) XOR nlli1ll))); + n11OllO <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli11l)) AND (NOT ((NOT comp_pat(31)) XOR nlli11O))) AND (NOT ((NOT comp_pat(32)) XOR nlli10i))) AND (NOT ((NOT comp_pat(33)) XOR nlli10l))) AND (NOT ((NOT comp_pat(34)) XOR nlli10O))) AND (NOT ((NOT comp_pat(35)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(36)) XOR nlli1il))) AND (NOT ((NOT comp_pat(37)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(38)) XOR nlli1li))) AND (NOT ((NOT comp_pat(39)) XOR nlli1ll))); + n11OlOi <= (n101Oil AND (wire_w_lg_w_lg_comp_pat_porn4822w4823w(0) AND wire_w_lg_w_lg_comp_pat_porn4824w4825w(0))); + n11OlOl <= ((((((((((NOT (comp_pat(20) XOR nll0O0O)) AND (NOT (comp_pat(21) XOR nll0Oii))) AND (NOT (comp_pat(22) XOR nll0Oil))) AND (NOT (comp_pat(23) XOR nll0OiO))) AND (NOT (comp_pat(24) XOR nll0Oli))) AND (NOT (comp_pat(25) XOR nll0Oll))) AND (NOT (comp_pat(26) XOR nll0OlO))) AND (NOT (comp_pat(27) XOR nll0OOi))) AND (NOT (comp_pat(28) XOR nll0OOl))) AND (NOT (comp_pat(29) XOR nll0OOO))); + n11OlOO <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0O0O)) AND (NOT ((NOT comp_pat(21)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(22)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(23)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(24)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(25)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(26)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(27)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(28)) XOR nll0OOl))) AND (NOT ((NOT comp_pat(29)) XOR nll0OOO))); + n11OO0i <= ((((((((((NOT (comp_pat(20) XOR nll0O0l)) AND (NOT (comp_pat(21) XOR nll0O0O))) AND (NOT (comp_pat(22) XOR nll0Oii))) AND (NOT (comp_pat(23) XOR nll0Oil))) AND (NOT (comp_pat(24) XOR nll0OiO))) AND (NOT (comp_pat(25) XOR nll0Oli))) AND (NOT (comp_pat(26) XOR nll0Oll))) AND (NOT (comp_pat(27) XOR nll0OlO))) AND (NOT (comp_pat(28) XOR nll0OOi))) AND (NOT (comp_pat(29) XOR nll0OOl))); + n11OO0l <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0O0l)) AND (NOT ((NOT comp_pat(21)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(22)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(23)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(24)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(25)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(26)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(27)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(28)) XOR nll0OOi))) AND (NOT ((NOT comp_pat(29)) XOR nll0OOl))); + n11OO0O <= ((((((((((NOT (comp_pat(30) XOR nll0OOO)) AND (NOT (comp_pat(31) XOR nlli11i))) AND (NOT (comp_pat(32) XOR nlli11l))) AND (NOT (comp_pat(33) XOR nlli11O))) AND (NOT (comp_pat(34) XOR nlli10i))) AND (NOT (comp_pat(35) XOR nlli10l))) AND (NOT (comp_pat(36) XOR nlli10O))) AND (NOT (comp_pat(37) XOR nlli1ii))) AND (NOT (comp_pat(38) XOR nlli1il))) AND (NOT (comp_pat(39) XOR nlli1iO))); + n11OO1i <= ((((((((((NOT (comp_pat(30) XOR nlli11i)) AND (NOT (comp_pat(31) XOR nlli11l))) AND (NOT (comp_pat(32) XOR nlli11O))) AND (NOT (comp_pat(33) XOR nlli10i))) AND (NOT (comp_pat(34) XOR nlli10l))) AND (NOT (comp_pat(35) XOR nlli10O))) AND (NOT (comp_pat(36) XOR nlli1ii))) AND (NOT (comp_pat(37) XOR nlli1il))) AND (NOT (comp_pat(38) XOR nlli1iO))) AND (NOT (comp_pat(39) XOR nlli1li))); + n11OO1l <= ((((((((((NOT ((NOT comp_pat(30)) XOR nlli11i)) AND (NOT ((NOT comp_pat(31)) XOR nlli11l))) AND (NOT ((NOT comp_pat(32)) XOR nlli11O))) AND (NOT ((NOT comp_pat(33)) XOR nlli10i))) AND (NOT ((NOT comp_pat(34)) XOR nlli10l))) AND (NOT ((NOT comp_pat(35)) XOR nlli10O))) AND (NOT ((NOT comp_pat(36)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(37)) XOR nlli1il))) AND (NOT ((NOT comp_pat(38)) XOR nlli1iO))) AND (NOT ((NOT comp_pat(39)) XOR nlli1li))); + n11OO1O <= (n101Oll AND (wire_w_lg_w_lg_comp_pat_porn4816w4817w(0) AND wire_w_lg_w_lg_comp_pat_porn4818w4819w(0))); + n11OOii <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0OOO)) AND (NOT ((NOT comp_pat(31)) XOR nlli11i))) AND (NOT ((NOT comp_pat(32)) XOR nlli11l))) AND (NOT ((NOT comp_pat(33)) XOR nlli11O))) AND (NOT ((NOT comp_pat(34)) XOR nlli10i))) AND (NOT ((NOT comp_pat(35)) XOR nlli10l))) AND (NOT ((NOT comp_pat(36)) XOR nlli10O))) AND (NOT ((NOT comp_pat(37)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(38)) XOR nlli1il))) AND (NOT ((NOT comp_pat(39)) XOR nlli1iO))); + n11OOil <= (n101OOl AND (wire_w_lg_w_lg_comp_pat_porn4810w4811w(0) AND wire_w_lg_w_lg_comp_pat_porn4812w4813w(0))); + n11OOiO <= ((((((((((NOT (comp_pat(20) XOR nll0O0i)) AND (NOT (comp_pat(21) XOR nll0O0l))) AND (NOT (comp_pat(22) XOR nll0O0O))) AND (NOT (comp_pat(23) XOR nll0Oii))) AND (NOT (comp_pat(24) XOR nll0Oil))) AND (NOT (comp_pat(25) XOR nll0OiO))) AND (NOT (comp_pat(26) XOR nll0Oli))) AND (NOT (comp_pat(27) XOR nll0Oll))) AND (NOT (comp_pat(28) XOR nll0OlO))) AND (NOT (comp_pat(29) XOR nll0OOi))); + n11OOli <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0O0i)) AND (NOT ((NOT comp_pat(21)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(22)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(23)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(24)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(25)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(26)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(27)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(28)) XOR nll0OlO))) AND (NOT ((NOT comp_pat(29)) XOR nll0OOi))); + n11OOll <= ((((((((((NOT (comp_pat(30) XOR nll0OOl)) AND (NOT (comp_pat(31) XOR nll0OOO))) AND (NOT (comp_pat(32) XOR nlli11i))) AND (NOT (comp_pat(33) XOR nlli11l))) AND (NOT (comp_pat(34) XOR nlli11O))) AND (NOT (comp_pat(35) XOR nlli10i))) AND (NOT (comp_pat(36) XOR nlli10l))) AND (NOT (comp_pat(37) XOR nlli10O))) AND (NOT (comp_pat(38) XOR nlli1ii))) AND (NOT (comp_pat(39) XOR nlli1il))); + n11OOlO <= ((((((((((NOT ((NOT comp_pat(30)) XOR nll0OOl)) AND (NOT ((NOT comp_pat(31)) XOR nll0OOO))) AND (NOT ((NOT comp_pat(32)) XOR nlli11i))) AND (NOT ((NOT comp_pat(33)) XOR nlli11l))) AND (NOT ((NOT comp_pat(34)) XOR nlli11O))) AND (NOT ((NOT comp_pat(35)) XOR nlli10i))) AND (NOT ((NOT comp_pat(36)) XOR nlli10l))) AND (NOT ((NOT comp_pat(37)) XOR nlli10O))) AND (NOT ((NOT comp_pat(38)) XOR nlli1ii))) AND (NOT ((NOT comp_pat(39)) XOR nlli1il))); + n11OOOi <= (n10011l AND (wire_w_lg_w_lg_comp_pat_porn4804w4805w(0) AND wire_w_lg_w_lg_comp_pat_porn4806w4807w(0))); + n11OOOl <= ((((((((((NOT (comp_pat(20) XOR nll0O1O)) AND (NOT (comp_pat(21) XOR nll0O0i))) AND (NOT (comp_pat(22) XOR nll0O0l))) AND (NOT (comp_pat(23) XOR nll0O0O))) AND (NOT (comp_pat(24) XOR nll0Oii))) AND (NOT (comp_pat(25) XOR nll0Oil))) AND (NOT (comp_pat(26) XOR nll0OiO))) AND (NOT (comp_pat(27) XOR nll0Oli))) AND (NOT (comp_pat(28) XOR nll0Oll))) AND (NOT (comp_pat(29) XOR nll0OlO))); + n11OOOO <= ((((((((((NOT ((NOT comp_pat(20)) XOR nll0O1O)) AND (NOT ((NOT comp_pat(21)) XOR nll0O0i))) AND (NOT ((NOT comp_pat(22)) XOR nll0O0l))) AND (NOT ((NOT comp_pat(23)) XOR nll0O0O))) AND (NOT ((NOT comp_pat(24)) XOR nll0Oii))) AND (NOT ((NOT comp_pat(25)) XOR nll0Oil))) AND (NOT ((NOT comp_pat(26)) XOR nll0OiO))) AND (NOT ((NOT comp_pat(27)) XOR nll0Oli))) AND (NOT ((NOT comp_pat(28)) XOR nll0Oll))) AND (NOT ((NOT comp_pat(29)) XOR nll0OlO))); + n1i000i <= (n10llOi AND n10llOl); + n1i000l <= (wire_niOl1i_w_lg_w_lg_o2972w3113w(0) OR wire_niOl1i_w_lg_o3114w(0)); + n1i000O <= ((((wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND wire_niOilO_w_lg_w_lg_o3116w3117w(0))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND wire_niOilO_w_lg_o3119w(0)))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10lliO))) OR wire_niOiOl_w_lg_o3283w(0)); + n1i001i <= (n10lO1i AND n1i00ii); + n1i001l <= (((wire_w_lg_n10lOOO3237w(0) OR (n10lO1i AND n1i000l)) OR n10lOOl) OR n10O11i); + n1i001O <= (wire_niOiOl_o AND n10lllO); + n1i00ii <= (wire_niOl1i_w_lg_o2972w(0) AND wire_niOiOO_w_lg_o2973w(0)); + n1i00il <= ((((((wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND (wire_niOilO_o AND wire_niOill_o))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10llll))) OR (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_o AND n10llli))) OR wire_niOiOl_w_lg_o3273w(0)) OR wire_niOiOl_w_lg_o3276w(0)) OR wire_niOiOl_w_lg_o3137w(0)); + n1i00iO <= (n1i000O AND n1i00ii); + n1i00li <= (n10llOi AND n1i000l); + n1i00ll <= (n10llOi AND n1i00ii); + n1i00lO <= (n1i00Ol OR n1i00Oi); + n1i00Oi <= (pmadwidth(0) AND nill0l); + n1i00Ol <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND nill0l); + n1i010i <= ((((((((NOT (comp_pat(0) XOR wire_nilllO_dataout)) AND (NOT (comp_pat(1) XOR wire_nillOi_dataout))) AND (NOT (comp_pat(2) XOR wire_nillOl_dataout))) AND (NOT (comp_pat(3) XOR wire_nillOO_dataout))) AND (NOT (comp_pat(4) XOR wire_nilO1i_dataout))) AND (NOT (comp_pat(5) XOR wire_nilO1l_dataout))) AND (NOT (comp_pat(6) XOR wire_nilO1O_dataout))) AND (NOT (comp_pat(7) XOR wire_nilO0i_dataout))); + n1i010l <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1i01ii1295w(0)); + n1i010O <= (nl1l1l AND (wire_w_lg_w_pmadwidth_range175w219w(0) AND nl1lii)); + n1i011i <= (((((((NOT ((NOT comp_pat(0)) XOR wire_nilllO_dataout)) AND (NOT ((NOT comp_pat(1)) XOR wire_nillOi_dataout))) AND (NOT ((NOT comp_pat(2)) XOR wire_nillOl_dataout))) AND (NOT ((NOT comp_pat(3)) XOR wire_nillOO_dataout))) AND (NOT ((NOT comp_pat(4)) XOR wire_nilO1i_dataout))) AND (NOT ((NOT comp_pat(5)) XOR wire_nilO1l_dataout))) AND (NOT ((NOT comp_pat(6)) XOR wire_nilO1O_dataout))); + n1i011l <= (((((((NOT (comp_pat(0) XOR wire_nilllO_dataout)) AND (NOT (comp_pat(1) XOR wire_nillOi_dataout))) AND (NOT (comp_pat(2) XOR wire_nillOl_dataout))) AND (NOT (comp_pat(3) XOR wire_nillOO_dataout))) AND (NOT (comp_pat(4) XOR wire_nilO1i_dataout))) AND (NOT (comp_pat(5) XOR wire_nilO1l_dataout))) AND (NOT (comp_pat(6) XOR wire_nilO1O_dataout))); + n1i011O <= ((((((((NOT (comp_pat(8) XOR wire_nilllO_dataout)) AND (NOT (comp_pat(9) XOR wire_nillOi_dataout))) AND (NOT (comp_pat(10) XOR wire_nillOl_dataout))) AND (NOT (comp_pat(11) XOR wire_nillOO_dataout))) AND (NOT (comp_pat(12) XOR wire_nilO1i_dataout))) AND (NOT (comp_pat(13) XOR wire_nilO1l_dataout))) AND (NOT (comp_pat(14) XOR wire_nilO1O_dataout))) AND (NOT (comp_pat(15) XOR wire_nilO0i_dataout))); + n1i01ii <= (nl1lii AND nl1l1l); + n1i01il <= (n1i01li OR n1i01iO); + n1i01iO <= (nl1lii AND wire_nl_w_lg_nl1l1l1933w(0)); + n1i01li <= (nl1lii AND nl1l1l); + n1i01ll <= ((((((wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_o2980w(0))) OR (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_dataout AND n10lO0l))) OR (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_dataout AND n10lO0i))) OR wire_niOl0l_w_lg_dataout3200w(0)) OR wire_niOl0l_w_lg_dataout3203w(0)) OR wire_niOl0l_w_lg_dataout3206w(0)); + n1i01lO <= (n10lOll OR n10lOOi); + n1i01Oi <= (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w2984w(0))); + n1i01Ol <= ((((wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w3189w(0))) OR (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_o3190w(0)))) OR (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_dataout AND n10lO1O))) OR wire_niOl0l_w_lg_dataout3217w(0)); + n1i01OO <= (wire_niOl1O_w_lg_o1314w(0) AND wire_niOl1l_w_lg_w_lg_o2983w3166w(0)); + n1i0i0i <= ((((((((wire_nl011O_w_lg_dataout446w(0) OR wire_w_lg_n1i0ilO447w(0)) OR wire_w_lg_n1i0ill449w(0)) OR wire_w_lg_n1i0ili451w(0)) OR wire_w_lg_n1i0iiO453w(0)) OR wire_w_lg_n1i0iil455w(0)) OR wire_w_lg_n1i0iii457w(0)) OR wire_w_lg_n1i0i0O459w(0)) OR n1i0i0l); + n1i0i0l <= ((((((((wire_nl00Oi_w_lg_dataout1914w(0) AND wire_nl00ii_w_lg_dataout428w(0)) AND wire_nl000i_w_lg_dataout421w(0)) AND wire_nl001i_w_lg_dataout415w(0)) AND wire_nl01Oi_w_lg_dataout410w(0)) AND wire_nl01li_w_lg_dataout406w(0)) AND wire_nl01ii_w_lg_dataout403w(0)) AND wire_nl010l_w_lg_dataout401w(0)) AND wire_nl011O_w_lg_dataout1922w(0)); + n1i0i0O <= ((((((((wire_nl00li_w_lg_dataout436w(0) OR wire_nl00ii_dataout) OR wire_nl000i_dataout) OR wire_nl001i_dataout) OR wire_nl01Oi_dataout) OR wire_nl01li_dataout) OR wire_nl01ii_dataout) OR wire_nl010l_dataout) OR wire_nl011O_dataout); + n1i0i1i <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND n1i0i1O); + n1i0i1l <= (pmadwidth(0) AND n1i0i1O); + n1i0i1O <= (((wire_nl10lO_w_lg_nl10Oi1924w(0) AND wire_nl10lO_w_lg_nl10ll1925w(0)) AND wire_nl10lO_w_lg_nl10li1927w(0)) AND wire_nl10lO_w_lg_nl10il1929w(0)); + n1i0iii <= (((((((wire_nl00ii_w_lg_dataout428w(0) OR wire_nl000i_dataout) OR wire_nl001i_dataout) OR wire_nl01Oi_dataout) OR wire_nl01li_dataout) OR wire_nl01ii_dataout) OR wire_nl010l_dataout) OR wire_nl011O_dataout); + n1i0iil <= ((((((wire_nl000i_w_lg_dataout421w(0) OR wire_nl001i_dataout) OR wire_nl01Oi_dataout) OR wire_nl01li_dataout) OR wire_nl01ii_dataout) OR wire_nl010l_dataout) OR wire_nl011O_dataout); + n1i0iiO <= (((((wire_nl001i_w_lg_dataout415w(0) OR wire_nl01Oi_dataout) OR wire_nl01li_dataout) OR wire_nl01ii_dataout) OR wire_nl010l_dataout) OR wire_nl011O_dataout); + n1i0ili <= ((((wire_nl01Oi_w_lg_dataout410w(0) OR wire_nl01li_dataout) OR wire_nl01ii_dataout) OR wire_nl010l_dataout) OR wire_nl011O_dataout); + n1i0ill <= (((wire_nl01li_w_lg_dataout406w(0) OR wire_nl01ii_dataout) OR wire_nl010l_dataout) OR wire_nl011O_dataout); + n1i0ilO <= ((wire_nl01ii_w_lg_dataout403w(0) OR wire_nl010l_dataout) OR wire_nl011O_dataout); + n1i0iOi <= (wire_nl010l_w_lg_dataout401w(0) OR wire_nl011O_dataout); + n1i0iOl <= ((((((((((NOT (wire_nli00i_dataout XOR wire_nl0i1i_dataout)) AND (NOT (wire_nli00l_dataout XOR wire_nl0i1l_dataout))) AND (NOT (wire_nli00O_dataout XOR wire_nl0i1O_dataout))) AND (NOT (wire_nli0ii_dataout XOR wire_nl0i0i_dataout))) AND (NOT (wire_nli0il_dataout XOR wire_nl0i0l_dataout))) AND (NOT (wire_nli0iO_dataout XOR wire_nl0i0O_dataout))) AND (NOT (wire_nli0li_dataout XOR wire_nl0iii_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nl0iil_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nl0iiO_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nl0ili_dataout))); + n1i0iOO <= ((((((((((NOT (comp_pat(0) XOR wire_nl0i1i_dataout)) AND (NOT (comp_pat(1) XOR wire_nl0i1l_dataout))) AND (NOT (comp_pat(2) XOR wire_nl0i1O_dataout))) AND (NOT (comp_pat(3) XOR wire_nl0i0i_dataout))) AND (NOT (comp_pat(4) XOR wire_nl0i0l_dataout))) AND (NOT (comp_pat(5) XOR wire_nl0i0O_dataout))) AND (NOT (comp_pat(6) XOR wire_nl0iii_dataout))) AND (NOT (wire_nliiiO_dataout XOR wire_nl0iil_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nl0iiO_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nl0ili_dataout))); + n1i0l0i <= ((((((((((NOT (comp_pat(0) XOR nliO0l)) AND (NOT (comp_pat(1) XOR nliO0O))) AND (NOT (comp_pat(2) XOR nliOii))) AND (NOT (comp_pat(3) XOR nliOil))) AND (NOT (comp_pat(4) XOR nliOiO))) AND (NOT (comp_pat(5) XOR nliOli))) AND (NOT (comp_pat(6) XOR nliOll))) AND (NOT (wire_nliiiO_dataout XOR wire_nl0O1l_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nl0O1O_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nl0O0i_dataout))); + n1i0l0l <= ((((((((((NOT (nliO0O XOR wire_nli00i_dataout)) AND (NOT (nliOii XOR wire_nli00l_dataout))) AND (NOT (nliOil XOR wire_nli00O_dataout))) AND (NOT (nliOiO XOR wire_nli0ii_dataout))) AND (NOT (nliOli XOR wire_nli0il_dataout))) AND (NOT (nliOll XOR wire_nli0iO_dataout))) AND (NOT (nliOlO XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nl0O0O_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nl0Oii_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nl0Oil_dataout))); + n1i0l0O <= ((((((((((NOT (comp_pat(0) XOR nliO0O)) AND (NOT (comp_pat(1) XOR nliOii))) AND (NOT (comp_pat(2) XOR nliOil))) AND (NOT (comp_pat(3) XOR nliOiO))) AND (NOT (comp_pat(4) XOR nliOli))) AND (NOT (comp_pat(5) XOR nliOll))) AND (NOT (comp_pat(6) XOR nliOlO))) AND (NOT (wire_nliiiO_dataout XOR wire_nl0O0O_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nl0Oii_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nl0Oil_dataout))); + n1i0l1i <= ((((((((((NOT (wire_nli00i_dataout XOR wire_nl0l0O_dataout)) AND (NOT (wire_nli00l_dataout XOR wire_nl0lii_dataout))) AND (NOT (wire_nli00O_dataout XOR wire_nl0lil_dataout))) AND (NOT (wire_nli0ii_dataout XOR wire_nl0liO_dataout))) AND (NOT (wire_nli0il_dataout XOR wire_nl0lli_dataout))) AND (NOT (wire_nli0iO_dataout XOR wire_nl0lll_dataout))) AND (NOT (wire_nli0li_dataout XOR wire_nl0llO_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nl0lOi_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nl0lOl_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nl0lOO_dataout))); + n1i0l1l <= ((((((((((NOT (comp_pat(0) XOR wire_nl0l0O_dataout)) AND (NOT (comp_pat(1) XOR wire_nl0lii_dataout))) AND (NOT (comp_pat(2) XOR wire_nl0lil_dataout))) AND (NOT (comp_pat(3) XOR wire_nl0liO_dataout))) AND (NOT (comp_pat(4) XOR wire_nl0lli_dataout))) AND (NOT (comp_pat(5) XOR wire_nl0lll_dataout))) AND (NOT (comp_pat(6) XOR wire_nl0llO_dataout))) AND (NOT (wire_nliiiO_dataout XOR wire_nl0lOi_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nl0lOl_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nl0lOO_dataout))); + n1i0l1O <= ((((((((((NOT (nliO0l XOR wire_nli00i_dataout)) AND (NOT (nliO0O XOR wire_nli00l_dataout))) AND (NOT (nliOii XOR wire_nli00O_dataout))) AND (NOT (nliOil XOR wire_nli0ii_dataout))) AND (NOT (nliOiO XOR wire_nli0il_dataout))) AND (NOT (nliOli XOR wire_nli0iO_dataout))) AND (NOT (nliOll XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nl0O1l_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nl0O1O_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nl0O0i_dataout))); + n1i0lii <= ((((((((((NOT (nliOii XOR wire_nli00i_dataout)) AND (NOT (nliOil XOR wire_nli00l_dataout))) AND (NOT (nliOiO XOR wire_nli00O_dataout))) AND (NOT (nliOli XOR wire_nli0ii_dataout))) AND (NOT (nliOll XOR wire_nli0il_dataout))) AND (NOT (nliOlO XOR wire_nli0iO_dataout))) AND (NOT (nliOOi XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nl0Oli_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nl0Oll_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nl0OlO_dataout))); + n1i0lil <= ((((((((((NOT (comp_pat(0) XOR nliOii)) AND (NOT (comp_pat(1) XOR nliOil))) AND (NOT (comp_pat(2) XOR nliOiO))) AND (NOT (comp_pat(3) XOR nliOli))) AND (NOT (comp_pat(4) XOR nliOll))) AND (NOT (comp_pat(5) XOR nliOlO))) AND (NOT (comp_pat(6) XOR nliOOi))) AND (NOT (wire_nliiiO_dataout XOR wire_nl0Oli_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nl0Oll_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nl0OlO_dataout))); + n1i0liO <= ((((((((((NOT (nliOil XOR wire_nli00i_dataout)) AND (NOT (nliOiO XOR wire_nli00l_dataout))) AND (NOT (nliOli XOR wire_nli00O_dataout))) AND (NOT (nliOll XOR wire_nli0ii_dataout))) AND (NOT (nliOlO XOR wire_nli0il_dataout))) AND (NOT (nliOOi XOR wire_nli0iO_dataout))) AND (NOT (nliOOl XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nl0OOl_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nl0OOO_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nli11i_dataout))); + n1i0lli <= ((((((((((NOT (comp_pat(0) XOR nliOil)) AND (NOT (comp_pat(1) XOR nliOiO))) AND (NOT (comp_pat(2) XOR nliOli))) AND (NOT (comp_pat(3) XOR nliOll))) AND (NOT (comp_pat(4) XOR nliOlO))) AND (NOT (comp_pat(5) XOR nliOOi))) AND (NOT (comp_pat(6) XOR nliOOl))) AND (NOT (wire_nliiiO_dataout XOR wire_nl0OOl_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nl0OOO_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nli11i_dataout))); + n1i0lll <= ((((((((((NOT (nliOiO XOR wire_nli00i_dataout)) AND (NOT (nliOli XOR wire_nli00l_dataout))) AND (NOT (nliOll XOR wire_nli00O_dataout))) AND (NOT (nliOlO XOR wire_nli0ii_dataout))) AND (NOT (nliOOi XOR wire_nli0il_dataout))) AND (NOT (nliOOl XOR wire_nli0iO_dataout))) AND (NOT (nliOOO XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nli11O_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nli10i_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nli10l_dataout))); + n1i0llO <= ((((((((((NOT (comp_pat(0) XOR nliOiO)) AND (NOT (comp_pat(1) XOR nliOli))) AND (NOT (comp_pat(2) XOR nliOll))) AND (NOT (comp_pat(3) XOR nliOlO))) AND (NOT (comp_pat(4) XOR nliOOi))) AND (NOT (comp_pat(5) XOR nliOOl))) AND (NOT (comp_pat(6) XOR nliOOO))) AND (NOT (wire_nliiiO_dataout XOR wire_nli11O_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nli10i_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nli10l_dataout))); + n1i0lOO <= ((((((((((NOT (nliOli XOR wire_nli00i_dataout)) AND (NOT (nliOll XOR wire_nli00l_dataout))) AND (NOT (nliOlO XOR wire_nli00O_dataout))) AND (NOT (nliOOi XOR wire_nli0ii_dataout))) AND (NOT (nliOOl XOR wire_nli0il_dataout))) AND (NOT (nliOOO XOR wire_nli0iO_dataout))) AND (NOT (nll11i XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nli1ii_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nli1il_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nli1iO_dataout))); + n1i0O0O <= ((((((((((NOT (nliOll XOR wire_nli00i_dataout)) AND (NOT (nliOlO XOR wire_nli00l_dataout))) AND (NOT (nliOOi XOR wire_nli00O_dataout))) AND (NOT (nliOOl XOR wire_nli0ii_dataout))) AND (NOT (nliOOO XOR wire_nli0il_dataout))) AND (NOT (nll11i XOR wire_nli0iO_dataout))) AND (NOT (nll11l XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nli1ll_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nli1lO_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nli1Oi_dataout))); + n1i0O1i <= ((((((((((NOT (comp_pat(0) XOR nliOli)) AND (NOT (comp_pat(1) XOR nliOll))) AND (NOT (comp_pat(2) XOR nliOlO))) AND (NOT (comp_pat(3) XOR nliOOi))) AND (NOT (comp_pat(4) XOR nliOOl))) AND (NOT (comp_pat(5) XOR nliOOO))) AND (NOT (comp_pat(6) XOR nll11i))) AND (NOT (wire_nliiiO_dataout XOR wire_nli1ii_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nli1il_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nli1iO_dataout))); + n1i0Oii <= ((((((((((NOT (comp_pat(0) XOR nliOll)) AND (NOT (comp_pat(1) XOR nliOlO))) AND (NOT (comp_pat(2) XOR nliOOi))) AND (NOT (comp_pat(3) XOR nliOOl))) AND (NOT (comp_pat(4) XOR nliOOO))) AND (NOT (comp_pat(5) XOR nll11i))) AND (NOT (comp_pat(6) XOR nll11l))) AND (NOT (wire_nliiiO_dataout XOR wire_nli1ll_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nli1lO_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nli1Oi_dataout))); + n1i100i <= (((((wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0) AND nlil1O) AND nlil1l) AND nlil1i) AND nliiOO) AND nliiOl); + n1i100l <= (wire_w_lg_w_pmadwidth_range175w2207w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w2208w(0)); + n1i100O <= ((((wire_nl_w_lg_w_lg_w_lg_nlil0l2177w2182w2187w(0) AND nlil1i) AND nliiOO) AND nliiOl) AND nl1lOi); + n1i101i <= (pmadwidth(0) AND n1i101l); + n1i101l <= ((((((wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0) AND nlil1O) AND nlil1l) AND nlil1i) AND nliiOO) AND nliiOl) AND nl1lOi); + n1i101O <= (pmadwidth(0) AND n1i100i); + n1i10ii <= ((((wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0) AND nlil1O) AND nlil1l) AND nlil1i) AND nliiOO); + n1i10il <= (wire_w_lg_w_pmadwidth_range175w2202w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w2203w(0)); + n1i10iO <= (((wire_nl_w_lg_w_lg_w_lg_nlil0l2177w2182w2187w(0) AND nlil1i) AND nliiOO) AND nliiOl); + n1i10li <= (((wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0) AND nlil1O) AND nlil1l) AND nlil1i); + n1i10ll <= (wire_w_lg_w_pmadwidth_range175w2197w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w2198w(0)); + n1i10lO <= ((wire_nl_w_lg_w_lg_w_lg_nlil0l2177w2182w2187w(0) AND nlil1i) AND nliiOO); + n1i10Oi <= ((wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0) AND nlil1O) AND nlil1l); + n1i10Ol <= (wire_w_lg_w_pmadwidth_range175w2192w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w2193w(0)); + n1i10OO <= (wire_nl_w_lg_w_lg_w_lg_nlil0l2177w2182w2187w(0) AND nlil1i); + n1i110i <= ((((wire_w_lg_n1i1lll2250w(0) OR n1i1lil) OR n1i1l0l) OR n1i1l1O) OR n1i1l1i); + n1i110l <= (((wire_w_lg_n1i1lil2246w(0) OR n1i1l0l) OR n1i1l1O) OR n1i1l1i); + n1i110O <= (wire_w_lg_n1i1l1O2244w(0) OR n1i1l1i); + n1i111i <= (((((((wire_w_lg_n1i1O1O2268w(0) OR n1i1O1l) OR n1i1lOl) OR n1i1lll) OR n1i1lil) OR n1i1l0l) OR n1i1l1O) OR n1i1l1i); + n1i111l <= ((((((wire_w_lg_n1i1O1l2261w(0) OR n1i1lOl) OR n1i1lll) OR n1i1lil) OR n1i1l0l) OR n1i1l1O) OR n1i1l1i); + n1i111O <= (((((wire_w_lg_n1i1lOl2255w(0) OR n1i1lll) OR n1i1lil) OR n1i1l0l) OR n1i1l1O) OR n1i1l1i); + n1i11ii <= (pmadwidth(0) AND n1i101l); + n1i11il <= (pmadwidth(0) AND n1i11iO); + n1i11iO <= ((((((((nlil0O AND nlil0l) AND nlil0i) AND nlil1O) AND nlil1l) AND nlil1i) AND nliiOO) AND nliiOl) AND nl1lOi); + n1i11li <= ((((((nlil0i AND nlil1O) AND nlil1l) AND nlil1i) AND nliiOO) AND nliiOl) AND nl1lOi); + n1i11ll <= (((((nlil1O AND nlil1l) AND nlil1i) AND nliiOO) AND nliiOl) AND nl1lOi); + n1i11lO <= ((((nlil1l AND nlil1i) AND nliiOO) AND nliiOl) AND nl1lOi); + n1i11Oi <= (((nlil1i AND nliiOO) AND nliiOl) AND nl1lOi); + n1i11Ol <= ((nliiOO AND nliiOl) AND nl1lOi); + n1i11OO <= (nliiOl AND nl1lOi); + n1i1i0i <= (wire_w_lg_w_pmadwidth_range175w2176w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_nlil0l2177w(0))); + n1i1i0l <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND nlil0l); + n1i1i0O <= (pmadwidth(0) AND nlilii); + n1i1i1i <= (wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0) AND nlil1O); + n1i1i1l <= (wire_w_lg_w_pmadwidth_range175w2186w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_w_lg_w_lg_nlil0l2177w2182w2187w(0))); + n1i1i1O <= (wire_w_lg_w_pmadwidth_range175w2181w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_w_lg_nlil0l2177w2182w(0))); + n1i1iii <= wire_w_lg_w_pmadwidth_range175w2141w(0); + n1i1iil <= wire_w_lg_w_pmadwidth_range175w2172w(0); + n1i1iiO <= ((((((((nlil0O OR nlil0l) OR nlil0i) OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO) OR nliiOl) OR nl1lOi); + n1i1ili <= ((((((nlil0i OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO) OR nliiOl) OR nl1lOi); + n1i1ill <= (((((nlil1O OR nlil1l) OR nlil1i) OR nliiOO) OR nliiOl) OR nl1lOi); + n1i1ilO <= ((((nlil1l OR nlil1i) OR nliiOO) OR nliiOl) OR nl1lOi); + n1i1iOi <= (((nlil1i OR nliiOO) OR nliiOl) OR nl1lOi); + n1i1iOl <= ((nliiOO OR nliiOl) OR nl1lOi); + n1i1iOO <= (nliiOl OR nl1lOi); + n1i1l0i <= (((((wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0) OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO) OR nliiOl); + n1i1l0l <= (wire_w_lg_w_pmadwidth_range175w2132w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1i1l0O2133w(0))); + n1i1l0O <= (((((((nlil0l OR nlil0i) OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO) OR nliiOl) OR nl1lOi); + n1i1l1i <= wire_w_lg_w_pmadwidth_range175w2141w(0); + n1i1l1l <= ((((((wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0) OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO) OR nliiOl) OR nl1lOi); + n1i1l1O <= wire_w_lg_w_pmadwidth_range175w2138w(0); + n1i1lii <= ((((wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0) OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO); + n1i1lil <= (wire_w_lg_w_pmadwidth_range175w2125w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1i1liO2126w(0))); + n1i1liO <= ((((((nlil0l OR nlil0i) OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO) OR nliiOl); + n1i1lli <= (((wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0) OR nlil1O) OR nlil1l) OR nlil1i); + n1i1lll <= (wire_w_lg_w_pmadwidth_range175w2118w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1i1llO2119w(0))); + n1i1llO <= (((((nlil0l OR nlil0i) OR nlil1O) OR nlil1l) OR nlil1i) OR nliiOO); + n1i1lOi <= ((wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0) OR nlil1O) OR nlil1l); + n1i1lOl <= (wire_w_lg_w_pmadwidth_range175w2111w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1i1lOO2112w(0))); + n1i1lOO <= ((((nlil0l OR nlil0i) OR nlil1O) OR nlil1l) OR nlil1i); + n1i1O0i <= (wire_w_lg_w_pmadwidth_range175w2089w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND (NOT (nlil0l OR nlil0i)))); + n1i1O0l <= (((((((NOT (wire_niOill_o XOR wire_niiO1i_w_lg_dataout2047w(0))) AND (NOT (wire_niOilO_o XOR wire_niiO1l_w_lg_dataout2050w(0)))) AND (NOT (wire_niOiOi_o XOR wire_niiO1O_w_lg_dataout2054w(0)))) AND (NOT (wire_niOiOl_o XOR wire_niiO0i_w_lg_dataout2058w(0)))) AND (NOT (wire_niOiOO_o XOR wire_niiO0l_w_lg_dataout2062w(0)))) AND (NOT (wire_niOl1i_o XOR wire_niiO0O_w_lg_dataout2066w(0)))) AND (NOT (wire_niOl1l_o XOR wire_niiOii_w_lg_dataout2070w(0)))); + n1i1O0O <= (((((((NOT (wire_niOill_o XOR wire_niiO1i_dataout)) AND (NOT (wire_niOilO_o XOR wire_niiO1l_dataout))) AND (NOT (wire_niOiOi_o XOR wire_niiO1O_dataout))) AND (NOT (wire_niOiOl_o XOR wire_niiO0i_dataout))) AND (NOT (wire_niOiOO_o XOR wire_niiO0l_dataout))) AND (NOT (wire_niOl1i_o XOR wire_niiO0O_dataout))) AND (NOT (wire_niOl1l_o XOR wire_niiOii_dataout))); + n1i1O1i <= (wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0) OR nlil1O); + n1i1O1l <= (wire_w_lg_w_pmadwidth_range175w2103w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND (NOT (((nlil0l OR nlil0i) OR nlil1O) OR nlil1l)))); + n1i1O1O <= (wire_w_lg_w_pmadwidth_range175w2096w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND (NOT ((nlil0l OR nlil0i) OR nlil1O)))); + n1i1Oii <= ((((((((((NOT (wire_niOill_o XOR wire_niiO1i_w_lg_dataout2047w(0))) AND (NOT (wire_niOilO_o XOR wire_niiO1l_w_lg_dataout2050w(0)))) AND (NOT (wire_niOiOi_o XOR wire_niiO1O_w_lg_dataout2054w(0)))) AND (NOT (wire_niOiOl_o XOR wire_niiO0i_w_lg_dataout2058w(0)))) AND (NOT (wire_niOiOO_o XOR wire_niiO0l_w_lg_dataout2062w(0)))) AND (NOT (wire_niOl1i_o XOR wire_niiO0O_w_lg_dataout2066w(0)))) AND (NOT (wire_niOl1l_o XOR wire_niiOii_w_lg_dataout2070w(0)))) AND (NOT (wire_niOl1O_o XOR wire_niiOil_w_lg_dataout2074w(0)))) AND (NOT (wire_niOl0i_dataout XOR wire_niiOiO_w_lg_dataout2078w(0)))) AND (NOT (wire_niOl0l_dataout XOR wire_niiOli_w_lg_dataout2082w(0)))); + n1i1Oil <= ((((((((((NOT (wire_niOill_o XOR wire_niiO1i_dataout)) AND (NOT (wire_niOilO_o XOR wire_niiO1l_dataout))) AND (NOT (wire_niOiOi_o XOR wire_niiO1O_dataout))) AND (NOT (wire_niOiOl_o XOR wire_niiO0i_dataout))) AND (NOT (wire_niOiOO_o XOR wire_niiO0l_dataout))) AND (NOT (wire_niOl1i_o XOR wire_niiO0O_dataout))) AND (NOT (wire_niOl1l_o XOR wire_niiOii_dataout))) AND (NOT (wire_niOl1O_o XOR wire_niiOil_dataout))) AND (NOT (wire_niOl0i_dataout XOR wire_niiOiO_dataout))) AND (NOT (wire_niOl0l_dataout XOR wire_niiOli_dataout))); + n1i1OiO <= (wire_niOl1i_o AND (wire_niOiOO_w_lg_o2973w(0) AND n1i000O)); + n1i1Oli <= (wire_niOl1i_w_lg_o2972w(0) AND (wire_niOiOO_o AND n10lO1i)); + n1i1Oll <= (wire_niOl1i_w_lg_o2972w(0) AND (wire_niOiOO_w_lg_o2973w(0) AND (wire_niOiOl_w_lg_o1205w(0) AND (wire_niOiOi_w_lg_o3108w(0) AND (wire_niOilO_o AND wire_niOill_o))))); + n1i1OlO <= (wire_niOl1i_o AND (wire_niOiOO_o AND wire_niOiOl_w_lg_o3137w(0))); + n1i1OOi <= ((NOT comp_pat_size(0)) AND comp_pat_size(1)); + n1i1OOl <= ((((((((((NOT ((NOT comp_pat(0)) XOR wire_nilllO_dataout)) AND (NOT ((NOT comp_pat(1)) XOR wire_nillOi_dataout))) AND (NOT ((NOT comp_pat(2)) XOR wire_nillOl_dataout))) AND (NOT ((NOT comp_pat(3)) XOR wire_nillOO_dataout))) AND (NOT ((NOT comp_pat(4)) XOR wire_nilO1i_dataout))) AND (NOT ((NOT comp_pat(5)) XOR wire_nilO1l_dataout))) AND (NOT ((NOT comp_pat(6)) XOR wire_nilO1O_dataout))) AND (NOT ((NOT comp_pat(7)) XOR wire_nilO0i_dataout))) AND (NOT ((NOT comp_pat(8)) XOR wire_nilO0l_dataout))) AND (NOT ((NOT comp_pat(9)) XOR wire_nilO0O_dataout))); + n1i1OOO <= ((((((((((NOT (comp_pat(0) XOR wire_nilllO_dataout)) AND (NOT (comp_pat(1) XOR wire_nillOi_dataout))) AND (NOT (comp_pat(2) XOR wire_nillOl_dataout))) AND (NOT (comp_pat(3) XOR wire_nillOO_dataout))) AND (NOT (comp_pat(4) XOR wire_nilO1i_dataout))) AND (NOT (comp_pat(5) XOR wire_nilO1l_dataout))) AND (NOT (comp_pat(6) XOR wire_nilO1O_dataout))) AND (NOT (comp_pat(7) XOR wire_nilO0i_dataout))) AND (NOT (comp_pat(8) XOR wire_nilO0l_dataout))) AND (NOT (comp_pat(9) XOR wire_nilO0O_dataout))); + n1ii00i <= (nlO0l1l AND n1ii00l); + n1ii00l <= (wire_w_lg_w_lg_n1ii01O227w228w(0) AND wire_w_lg_n1ii1OO229w(0)); + n1ii01i <= ((((wire_w_lg_n1i0ilO447w(0) OR wire_w_lg_n1i0ill449w(0)) OR wire_w_lg_n1i0iil455w(0)) OR wire_w_lg_n1i0iii457w(0)) OR wire_w_lg_n1i0i0i462w(0)); + n1ii01l <= ((((wire_w_lg_n1i0ilO447w(0) OR wire_w_lg_n1i0ill449w(0)) OR wire_w_lg_n1i0ili451w(0)) OR wire_w_lg_n1i0iiO453w(0)) OR wire_w_lg_n1i0i0i462w(0)); + n1ii01O <= (wire_nl011O_w_lg_dataout446w(0) OR wire_w_lg_n1i0i0i462w(0)); + n1ii0iO <= (wire_w_lg_disable_rx_disp1194w(0) AND ((((wire_nl_w_lg_niii0i1195w(0) AND wire_w_lg_w1202w1203w(0)) OR wire_nl_w_lg_niii0i1208w(0)) OR (wire_w_lg_n1i01OO1211w(0) AND wire_nlOll0O_w_lg_dataout1212w(0))) OR wire_w_lg_w_lg_n1i01lO1217w1218w(0))); + n1ii0li <= (wire_w_lg_sync_sm_dis1224w(0) AND nlO01ii); + n1ii0Oi <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND (sync_sm_dis AND nil1Ol)); + n1ii0Ol <= (sync_sm_dis AND nl10Ol); + n1ii10i <= wire_w_lg_w_comp_pat_size_range1330w1333w(0); + n1ii10O <= (wire_nllliil_dataout AND (NOT (wire_w_lg_w_lg_n1ii01O227w228w(0) AND wire_w_lg_n1ii1OO229w(0)))); + n1ii11i <= ((((((((((NOT (nliOlO XOR wire_nli00i_dataout)) AND (NOT (nliOOi XOR wire_nli00l_dataout))) AND (NOT (nliOOl XOR wire_nli00O_dataout))) AND (NOT (nliOOO XOR wire_nli0ii_dataout))) AND (NOT (nll11i XOR wire_nli0il_dataout))) AND (NOT (nll11l XOR wire_nli0iO_dataout))) AND (NOT (nll11O XOR wire_nli0li_dataout))) AND (NOT (wire_nli0ll_dataout XOR wire_nli1OO_dataout))) AND (NOT (wire_nli0lO_dataout XOR wire_nli01i_dataout))) AND (NOT (wire_nli0Oi_dataout XOR wire_nli01l_dataout))); + n1ii11l <= ((((((((((NOT (comp_pat(0) XOR nliOlO)) AND (NOT (comp_pat(1) XOR nliOOi))) AND (NOT (comp_pat(2) XOR nliOOl))) AND (NOT (comp_pat(3) XOR nliOOO))) AND (NOT (comp_pat(4) XOR nll11i))) AND (NOT (comp_pat(5) XOR nll11l))) AND (NOT (comp_pat(6) XOR nll11O))) AND (NOT (wire_nliiiO_dataout XOR wire_nli1OO_dataout))) AND (NOT (wire_nliili_dataout XOR wire_nli01i_dataout))) AND (NOT (wire_nliill_dataout XOR wire_nli01l_dataout))); + n1ii11O <= ((NOT comp_pat_size(0)) AND wire_w_lg_w_comp_pat_size_range1331w1332w(0)); + n1ii1lO <= (wire_nl_w_lg_nlO0l1l232w(0) AND (n1ii1Oi22 XOR n1ii1Oi21)); + n1ii1OO <= ((((wire_w_lg_n1i0iOi445w(0) OR wire_w_lg_n1i0ill449w(0)) OR wire_w_lg_n1i0iiO453w(0)) OR wire_w_lg_n1i0iii457w(0)) OR n1i0i0l); + n1iii1i <= '0'; + n1iii1l <= ((wire_w_lg_w_pmadwidth_range175w219w(0) AND pmadwidth(1)) AND (n1ii0ii18 XOR n1ii0ii17)); + n1iii1O <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND pmadwidth(1)); + n1iiili <= (n1OO0lO OR n1OO0ll); + n1iiill <= (n1Oi0O OR n1Oi0l); + n1iiilO <= (((((((n10i1OO AND n110iil) OR (n11liOi AND n110iii)) OR (n1000Ol AND n110i0O)) OR (n11iOiO AND n110i0l)) OR (n101iOi AND n110i0i)) OR (n110O1O AND n110i1O)) OR (n11O01l AND n110i1l)); + n1iiiOi <= (wire_w_lg_w_lg_w_lg_w_lg_rauto_speed_ena5w8w9w10w(0) OR (NOT (n1iiiOl6 XOR n1iiiOl5))); + n1iil0i <= '1'; + nlOO000i <= ((((wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND wire_nl1lili_w_lg_w_lg_o16990w16991w(0))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND wire_nl1lili_w_lg_o16993w(0)))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1Oii))) OR wire_nl1lilO_w_lg_o17022w(0)); + nlOO000l <= (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND wire_nl1lili_w_lg_w_lg_o16990w17009w(0))); + nlOO000O <= (wire_nl1lilO_o AND (wire_nl1lill_o AND (wire_nl1lili_o AND wire_nl1liiO_o))); + nlOO001i <= wire_nl1liOl_w_lg_w_lg_o16842w16987w(0); + nlOO001l <= wire_nl1liOl_w_lg_o16988w(0); + nlOO001O <= ((((wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1O0O)) OR wire_nl1lilO_w_lg_o17027w(0)) OR wire_nl1lilO_w_lg_o17030w(0)) OR wire_nl1lilO_w_lg_o17033w(0)); + nlOO00ii <= (wire_w_lg_w_ib_invalid_code_range3169w17048w(0) OR wire_w_lg_w_ib_invalid_code_range3176w17056w(0)); + nlOO00il <= (wire_nl1ll0l_o AND wire_nl1ll0i_o); + nlOO00iO <= wire_nl1ll0l_w_lg_w_lg_o16646w16665w(0); + nlOO00li <= wire_nl1ll0l_w_lg_o16649w(0); + nlOO00ll <= wire_nl1ll0l_w_lg_w_lg_o16646w16647w(0); + nlOO00lO <= (nlOO0lil AND nlOO00Ol); + nlOO00Oi <= (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND wire_nl1ll0l_w_lg_w_lg_o16646w16665w(0))); + nlOO00Ol <= wire_nl1lliO_w_lg_o16523w(0); + nlOO00OO <= (wire_nl1llii_o AND (wire_nl1ll0O_o AND (wire_nl1ll0l_o AND wire_nl1ll0i_o))); + nlOO010i <= (nlOO1OOl AND nlOO1lll); + nlOO010l <= (nlOO1l0i AND nlOO1lll); + nlOO010O <= (nlOO1l0i AND nlOO1lli); + nlOO011i <= (wire_nl1liOl_o AND (wire_nl1liOi_o AND wire_nl1lilO_w_lg_o17011w(0))); + nlOO011l <= (wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_w_lg_o16855w16857w(0))); + nlOO011O <= wire_nl1ll1O_w_lg_o16852w(0); + nlOO01ii <= (nlOO1l0i AND nlOO1l0l); + nlOO01il <= (nlOO1l0O AND nlOO1lli); + nlOO01iO <= ((nlOO1l0O AND nlOO1l0l) OR (nlOO1OOi AND nlOO1l0l)); + nlOO01li <= (nlOO1l0O AND nlOO1lll); + nlOO01ll <= (wire_nl1ll1O_w_lg_o16853w(0) AND wire_nl1ll1l_w_lg_o16854w(0)); + nlOO01lO <= ((((((wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND (wire_nl1lili_o AND wire_nl1liiO_o))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1OiO))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1Oil))) OR wire_nl1lilO_w_lg_o17004w(0)) OR wire_nl1lilO_w_lg_o17007w(0)) OR wire_nl1lilO_w_lg_o17011w(0)); + nlOO01Oi <= wire_nl1ll1i_w_lg_w_lg_o16855w16857w(0); + nlOO01Ol <= wire_nl1ll1i_w_lg_o16850w(0); + nlOO01OO <= (wire_nl1liOl_w_lg_o16981w(0) OR (wire_nl1liOl_w_lg_o16842w(0) AND (wire_nl1liOi_w_lg_o16843w(0) AND (wire_nl1lilO_w_lg_o16913w(0) AND wire_nl1lill_w_lg_o16982w(0))))); + nlOO0i0i <= (wire_nl1lliO_w_lg_w_lg_o16498w16643w(0) OR wire_nl1lliO_w_lg_o16644w(0)); + nlOO0i0l <= (wire_nl1lliO_w_lg_o16498w(0) AND wire_nl1llil_w_lg_o16499w(0)); + nlOO0i0O <= ((((((wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND (wire_nl1ll0l_o AND wire_nl1ll0i_o))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO00ll))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO00li))) OR wire_nl1llii_w_lg_o16821w(0)) OR wire_nl1llii_w_lg_o16824w(0)) OR wire_nl1llii_w_lg_o16667w(0)); + nlOO0i1i <= (nlOO0lii AND nlOO0i0l); + nlOO0i1l <= (((wire_w_lg_nlOO0O1O16789w(0) OR (nlOO0lii AND nlOO0i0i)) OR nlOO0O1l) OR nlOO0O0i); + nlOO0i1O <= (wire_nl1llii_o AND nlOO00lO); + nlOO0iii <= wire_nl1llll_w_lg_o16506w(0); + nlOO0iil <= wire_nl1llll_w_lg_w_lg_o16511w16513w(0); + nlOO0iiO <= wire_nl1llll_w_lg_o16718w(0); + nlOO0ili <= wire_nl1llll_w_lg_w_lg_o16511w16717w(0); + nlOO0ill <= (wire_nl1lllO_o XOR wire_nl1llli_o); + nlOO0ilO <= (wire_nl1llll_w_lg_o16511w(0) AND wire_nl1llli_w_lg_w_lg_o16512w16696w(0)); + nlOO0iOi <= ((((((wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_o16506w(0))) OR (wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_o AND nlOO0ili))) OR (wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_o AND nlOO0iiO))) OR wire_nl1llOi_w_lg_o16728w(0)) OR wire_nl1llOi_w_lg_o16731w(0)) OR wire_nl1llOi_w_lg_o16734w(0)); + nlOO0iOl <= (nlOO0l0l OR nlOO0llO); + nlOO0iOO <= (wire_nl1ll0l_o AND wire_nl1ll0i_o); + nlOO0l0i <= ((((wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_w_lg_o16511w16717w(0))) OR (wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_o16718w(0)))) OR (wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_o AND nlOO0iil))) OR wire_nl1llOi_w_lg_o16745w(0)); + nlOO0l0l <= ((((wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_o AND nlOO0iii)) OR wire_nl1llOi_w_lg_o16750w(0)) OR wire_nl1llOi_w_lg_o16753w(0)) OR wire_nl1llOi_w_lg_o16756w(0)); + nlOO0l0O <= (wire_n1lllii_w_lg_w_lg_dataout16774w16804w(0) OR (wire_n1lllii_dataout AND nlOO0i0l)); + nlOO0l1i <= wire_nl1ll0l_w_lg_w_lg_o16646w16665w(0); + nlOO0l1l <= wire_nl1ll0l_w_lg_o16649w(0); + nlOO0l1O <= wire_nl1ll0l_w_lg_w_lg_o16646w16647w(0); + nlOO0lii <= ((((wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO00il)) OR wire_nl1llii_w_lg_o16836w(0)) OR wire_nl1llii_w_lg_o16686w(0)) OR wire_nl1llii_w_lg_o16689w(0)); + nlOO0lil <= ((((wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND wire_nl1ll0l_w_lg_w_lg_o16646w16647w(0))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND wire_nl1ll0l_w_lg_o16649w(0)))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO00iO))) OR wire_nl1llii_w_lg_o16831w(0)); + nlOO0liO <= (wire_nl1lliO_w_lg_o16498w(0) AND (wire_nl1llil_w_lg_o16499w(0) AND (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND (wire_nl1ll0l_o AND wire_nl1ll0i_o))))); + nlOO0lli <= (wire_nl1lliO_o AND (wire_nl1llil_o AND wire_nl1llii_w_lg_o16667w(0))); + nlOO0lll <= (wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_w_lg_o16511w16513w(0))); + nlOO0llO <= wire_nl1llOi_w_lg_o16508w(0); + nlOO0lOi <= (nlOO0lil AND nlOO0i0l); + nlOO0lOl <= (nlOO00Oi AND nlOO0i0l); + nlOO0lOO <= (nlOO00Oi AND nlOO0i0i); + nlOO0O0i <= (nlOO00OO AND nlOO0i0l); + nlOO0O0l <= (wire_nl1llOi_w_lg_o16509w(0) AND wire_nl1lllO_w_lg_o16510w(0)); + nlOO0O0O <= ((((((wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND (wire_nl1ll0l_o AND wire_nl1ll0i_o))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO0l1O))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO0l1l))) OR wire_nl1llii_w_lg_o16660w(0)) OR wire_nl1llii_w_lg_o16663w(0)) OR wire_nl1llii_w_lg_o16667w(0)); + nlOO0O1i <= (nlOO00Oi AND nlOO00Ol); + nlOO0O1l <= (nlOO00OO AND nlOO0i0i); + nlOO0O1O <= ((nlOO00OO AND nlOO00Ol) OR (nlOO0lii AND nlOO00Ol)); + nlOO0Oii <= wire_nl1llll_w_lg_w_lg_o16511w16513w(0); + nlOO0Oil <= wire_nl1llll_w_lg_o16506w(0); + nlOO0OiO <= (wire_nl1lliO_w_lg_o16637w(0) OR (wire_nl1lliO_w_lg_o16498w(0) AND (wire_nl1llil_w_lg_o16499w(0) AND (wire_nl1llii_w_lg_o16569w(0) AND wire_nl1ll0O_w_lg_o16638w(0))))); + nlOO0Oli <= wire_nl1lliO_w_lg_w_lg_o16498w16643w(0); + nlOO0Oll <= wire_nl1lliO_w_lg_o16644w(0); + nlOO0OlO <= ((((wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO0iOO)) OR wire_nl1llii_w_lg_o16683w(0)) OR wire_nl1llii_w_lg_o16686w(0)) OR wire_nl1llii_w_lg_o16689w(0)); + nlOO0OOi <= ((((wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND wire_nl1ll0l_w_lg_w_lg_o16646w16647w(0))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND wire_nl1ll0l_w_lg_o16649w(0)))) OR (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_o AND nlOO0l1i))) OR wire_nl1llii_w_lg_o16678w(0)); + nlOO0OOl <= (wire_nl1llii_w_lg_o16569w(0) AND (wire_nl1ll0O_w_lg_o16638w(0) AND wire_nl1ll0l_w_lg_w_lg_o16646w16665w(0))); + nlOO0OOO <= (wire_nl1llii_o AND (wire_nl1ll0O_o AND (wire_nl1ll0l_o AND wire_nl1ll0i_o))); + nlOO1iOl <= (wire_nl1lili_o AND wire_nl1liiO_o); + nlOO1iOO <= wire_nl1lili_w_lg_w_lg_o16990w17009w(0); + nlOO1l0i <= (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND wire_nl1lili_w_lg_w_lg_o16990w17009w(0))); + nlOO1l0l <= wire_nl1liOl_w_lg_o16867w(0); + nlOO1l0O <= (wire_nl1lilO_o AND (wire_nl1lill_o AND (wire_nl1lili_o AND wire_nl1liiO_o))); + nlOO1l1i <= wire_nl1lili_w_lg_o16993w(0); + nlOO1l1l <= wire_nl1lili_w_lg_w_lg_o16990w16991w(0); + nlOO1l1O <= (nlOO1OOl AND nlOO1l0l); + nlOO1lii <= (nlOO1OOi AND nlOO1lll); + nlOO1lil <= (((wire_w_lg_nlOO01iO17133w(0) OR (nlOO1OOi AND nlOO1lli)) OR nlOO01il) OR nlOO01li); + nlOO1liO <= (wire_nl1lilO_o AND nlOO1l1O); + nlOO1lli <= (wire_nl1liOl_w_lg_w_lg_o16842w16987w(0) OR wire_nl1liOl_w_lg_o16988w(0)); + nlOO1lll <= (wire_nl1liOl_w_lg_o16842w(0) AND wire_nl1liOi_w_lg_o16843w(0)); + nlOO1llO <= ((((((wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND (wire_nl1lili_o AND wire_nl1liiO_o))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1l1l))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1l1i))) OR wire_nl1lilO_w_lg_o17165w(0)) OR wire_nl1lilO_w_lg_o17168w(0)) OR wire_nl1lilO_w_lg_o17011w(0)); + nlOO1lOi <= wire_nl1ll1i_w_lg_o16850w(0); + nlOO1lOl <= wire_nl1ll1i_w_lg_w_lg_o16855w16857w(0); + nlOO1lOO <= wire_nl1ll1i_w_lg_o17062w(0); + nlOO1O0i <= ((((((wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_o16850w(0))) OR (wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_o AND nlOO1O1i))) OR (wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_o AND nlOO1lOO))) OR wire_nl1ll1O_w_lg_o17072w(0)) OR wire_nl1ll1O_w_lg_o17075w(0)) OR wire_nl1ll1O_w_lg_o17078w(0)); + nlOO1O0l <= (nlOO1Oll OR nlOO011O); + nlOO1O0O <= (wire_nl1lili_o AND wire_nl1liiO_o); + nlOO1O1i <= wire_nl1ll1i_w_lg_w_lg_o16855w17061w(0); + nlOO1O1l <= (wire_nl1ll1l_o XOR wire_nl1liOO_o); + nlOO1O1O <= (wire_nl1ll1i_w_lg_o16855w(0) AND wire_nl1liOO_w_lg_w_lg_o16856w17040w(0)); + nlOO1Oii <= wire_nl1lili_w_lg_w_lg_o16990w17009w(0); + nlOO1Oil <= wire_nl1lili_w_lg_o16993w(0); + nlOO1OiO <= wire_nl1lili_w_lg_w_lg_o16990w16991w(0); + nlOO1Oli <= ((((wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_w_lg_o16855w17061w(0))) OR (wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_o17062w(0)))) OR (wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_o AND nlOO1lOl))) OR wire_nl1ll1O_w_lg_o17089w(0)); + nlOO1Oll <= ((((wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_o AND nlOO1lOi)) OR wire_nl1ll1O_w_lg_o17094w(0)) OR wire_nl1ll1O_w_lg_o17097w(0)) OR wire_nl1ll1O_w_lg_o17100w(0)); + nlOO1OlO <= (wire_n1iliii_w_lg_w_lg_dataout17118w17148w(0) OR (wire_n1iliii_dataout AND nlOO1lll)); + nlOO1OOi <= ((((wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1iOl)) OR wire_nl1lilO_w_lg_o17180w(0)) OR wire_nl1lilO_w_lg_o17030w(0)) OR wire_nl1lilO_w_lg_o17033w(0)); + nlOO1OOl <= ((((wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND wire_nl1lili_w_lg_w_lg_o16990w16991w(0))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND wire_nl1lili_w_lg_o16993w(0)))) OR (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_o AND nlOO1iOO))) OR wire_nl1lilO_w_lg_o17175w(0)); + nlOO1OOO <= (wire_nl1liOl_w_lg_o16842w(0) AND (wire_nl1liOi_w_lg_o16843w(0) AND (wire_nl1lilO_w_lg_o16913w(0) AND (wire_nl1lill_w_lg_o16982w(0) AND (wire_nl1lili_o AND wire_nl1liiO_o))))); + nlOOi00i <= ((((((((((wire_w_lg_w_pmadwidth_range175w15747w(0) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi00l <= ((((((((((wire_w_lg_w_pmadwidth_range175w15747w(0) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_nl_w_lg_nlli11i15988w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi00O <= ((((((((((wire_w_lg_w_pmadwidth_range175w15747w(0) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_nl_w_lg_nlli11i15988w(0)) OR wire_nl_w_lg_nll0OOO15999w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi01i <= ((((((((((wire_w_lg_w_pmadwidth_range175w15747w(0) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi01l <= ((((((((((wire_w_lg_w_pmadwidth_range175w15747w(0) OR wire_nl_w_lg_nlli1Oi15928w(0)) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi01O <= ((((((((((wire_w_lg_w_pmadwidth_range175w15747w(0) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0ii <= ((((((((((wire_w_lg_w_pmadwidth_range175w15747w(0) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_nl_w_lg_nlli11i15988w(0)) OR wire_nl_w_lg_nll0OOO15999w(0)) OR wire_nl_w_lg_nll0OOl16010w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0il <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli01l16013w(0)) OR wire_nl_w_lg_nlli01i16015w(0)) OR wire_nl_w_lg_nlli1OO16017w(0)) OR wire_nl_w_lg_nlli1Ol16019w(0)) OR wire_nl_w_lg_nlli1Oi15928w(0)) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0iO <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli01i16015w(0)) OR wire_nl_w_lg_nlli1OO16017w(0)) OR wire_nl_w_lg_nlli1Ol16019w(0)) OR wire_nl_w_lg_nlli1Oi15928w(0)) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0li <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli1OO16017w(0)) OR wire_nl_w_lg_nlli1Ol16019w(0)) OR wire_nl_w_lg_nlli1Oi15928w(0)) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0ll <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli1Ol16019w(0)) OR wire_nl_w_lg_nlli1Oi15928w(0)) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0lO <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli1Oi15928w(0)) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0Oi <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli1lO15930w(0)) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0Ol <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli1ll15932w(0)) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_nl_w_lg_nlli11i15988w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi0OO <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli1li15934w(0)) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_nl_w_lg_nlli11i15988w(0)) OR wire_nl_w_lg_nll0OOO15999w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOi10i <= (n1OO01i OR n1OO1OO); + nlOOi10l <= ((((n1OO01O OR n1OO01l) OR n1OO01i) OR n1OO1OO) OR n1OO1Ol); + nlOOi10O <= ((((n1OO01O OR n1OO01l) OR n1OO1Oi) OR n1OO1lO) OR n1Ol0il); + nlOOi11i <= (wire_w_lg_w_ib_invalid_code_range3169w16704w(0) OR wire_w_lg_w_ib_invalid_code_range3176w16712w(0)); + nlOOi11l <= (n1OO1Ol OR n1Ol0il); + nlOOi11O <= (n1OO1Oi OR n1OO1lO); + nlOOi1ii <= (n1OO01O OR n1OO01l); + nlOOi1il <= (wire_nl_w_lg_n011l1O16156w(0) AND wire_nl_w_lg_n011l1l16150w(0)); + nlOOi1iO <= (wire_nl_w_lg_n011l1O16156w(0) AND n011l1l); + nlOOi1li <= (n1Ol0ii AND n1Ol00O); + nlOOi1ll <= (wire_nl_w_lg_n0101il16151w(0) AND wire_nl_w_lg_n011l1l16150w(0)); + nlOOi1lO <= (wire_nl_w_lg_n0101il16151w(0) AND n011l1l); + nlOOi1Oi <= ((wire_n011i1l_w_lg_w_lg_w_lg_w16485w16487w16489w16490w(0) AND wire_n0110li_w_lg_dataout16491w(0)) AND wire_n0110iO_w_lg_dataout16493w(0)); + nlOOi1Ol <= ((wire_n011i1l_w_lg_w_lg_w_lg_w16485w16487w16489w16490w(0) AND wire_n0110li_w_lg_dataout16491w(0)) AND wire_n0110iO_dataout); + nlOOi1OO <= ((((((NOT max_rlv_sel(0)) AND (NOT max_rlv_sel(1))) AND (NOT max_rlv_sel(2))) AND (NOT max_rlv_sel(3))) AND (NOT max_rlv_sel(4))) AND (NOT max_rlv_sel(5))); + nlOOii0i <= (wire_w_lg_w_lg_w_lg_w15774w15775w15776w15777w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOii0l <= (wire_w_lg_w_lg_w_lg_w15784w15785w15786w15787w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOii0O <= (wire_w_lg_w_lg_w_lg_w15794w15795w15796w15797w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOii1i <= ((((((((((((wire_w_lg_w_lg_w_pmadwidth_range175w219w15819w(0) OR wire_nl_w_lg_nlli1iO15936w(0)) OR wire_nl_w_lg_nlli1il15938w(0)) OR wire_nl_w_lg_nlli1ii15940w(0)) OR wire_nl_w_lg_nlli10O15942w(0)) OR wire_nl_w_lg_nlli10l15944w(0)) OR wire_nl_w_lg_nlli10i15955w(0)) OR wire_nl_w_lg_nlli11O15966w(0)) OR wire_nl_w_lg_nlli11l15977w(0)) OR wire_nl_w_lg_nlli11i15988w(0)) OR wire_nl_w_lg_nll0OOO15999w(0)) OR wire_nl_w_lg_nll0OOl16010w(0)) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOii1l <= (wire_w_lg_w_lg_w_lg_w15764w15765w15766w15767w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOii1O <= (wire_w_lg_w_lg_w_lg_w15753w15754w15755w15756w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiiii <= (wire_w_lg_w_lg_w_lg_w15804w15805w15806w15807w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiiil <= (wire_w_lg_w_lg_w_lg_w15814w15815w15816w15817w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiiiO <= (wire_w_lg_w_lg_w15828w15829w15830w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiili <= (wire_w_lg_w_lg_w15840w15841w15842w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiill <= (wire_w_lg_w_lg_w15852w15853w15854w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiilO <= (wire_w_lg_w_lg_w15864w15865w15866w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiiOi <= (wire_w_lg_w_lg_w15876w15877w15878w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiiOl <= (wire_w_lg_w_lg_w15888w15889w15890w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOiiOO <= (wire_w_lg_w_lg_w15900w15901w15902w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOil0i <= ((((((((((((((((((wire_nl_w_lg_nll0OOl16448w(0) AND wire_w_lg_nlOOO1Ol15569w(0)) AND wire_w_lg_nlOOO1Oi15551w(0)) AND wire_w_lg_nlOOO1lO15534w(0)) AND wire_w_lg_nlOOO1ll15518w(0)) AND wire_w_lg_nlOOO1li15503w(0)) AND wire_w_lg_nlOOO1iO15489w(0)) AND wire_w_lg_nlOOO1il15476w(0)) AND wire_w_lg_nlOOO1ii15464w(0)) AND wire_w_lg_nlOOO10O15453w(0)) AND wire_w_lg_nlOOO10l15443w(0)) AND wire_w_lg_nlOOO10i15434w(0)) AND wire_w_lg_nlOOO11O15426w(0)) AND wire_w_lg_nlOOO11l15419w(0)) AND wire_w_lg_nlOOO11i15413w(0)) AND wire_w_lg_nlOOlOOl15404w(0)) AND wire_w_lg_nlOOlOlO15401w(0)) AND wire_w_lg_nlOOlOli15399w(0)) AND wire_w_lg_nlOOlOiO16466w(0)); + nlOOil0l <= (((((((((wire_w_lg_nlOOiOll15588w(0) OR wire_w_lg_nlOOiOli15590w(0)) OR wire_w_lg_nlOOiOii15596w(0)) OR wire_w_lg_nlOOiO0O15597w(0)) OR wire_w_lg_nlOOiO1O15603w(0)) OR wire_w_lg_nlOOiO1l15605w(0)) OR wire_w_lg_nlOOilOl15615w(0)) OR wire_w_lg_nlOOilOi15617w(0)) OR wire_w_lg_nlOOilli15630w(0)) OR wire_w_lg_nlOOiliO15632w(0)); + nlOOil0O <= (((((((wire_w_lg_nlOOlOiO15611w(0) OR wire_w_lg_nlOOiO0O15597w(0)) OR wire_w_lg_nlOOiO0l15599w(0)) OR wire_w_lg_nlOOiO0i15601w(0)) OR wire_w_lg_nlOOilOl15615w(0)) OR wire_w_lg_nlOOilOi15617w(0)) OR wire_w_lg_nlOOillO15619w(0)) OR wire_w_lg_nlOOilll15621w(0)); + nlOOil1i <= (wire_w_lg_w_lg_w15912w15913w15914w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOil1l <= (wire_w_lg_w_lg_w15924w15925w15926w(0) OR wire_n0110il_w_lg_dataout15757w(0)); + nlOOil1O <= (((((((((wire_w_lg_nlOOiOll15588w(0) OR wire_w_lg_nlOOiOiO15592w(0)) OR wire_w_lg_nlOOiOii15596w(0)) OR wire_w_lg_nlOOiO0l15599w(0)) OR wire_w_lg_nlOOiO1O15603w(0)) OR wire_w_lg_nlOOiO1i15607w(0)) OR wire_w_lg_nlOOilOl15615w(0)) OR wire_w_lg_nlOOillO15619w(0)) OR wire_w_lg_nlOOilli15630w(0)) OR nlOOil0i); + nlOOilii <= (((((((wire_w_lg_nlOOiOii15596w(0) OR wire_w_lg_nlOOiO0O15597w(0)) OR wire_w_lg_nlOOiO0l15599w(0)) OR wire_w_lg_nlOOiO0i15601w(0)) OR wire_w_lg_nlOOiO1O15603w(0)) OR wire_w_lg_nlOOiO1l15605w(0)) OR wire_w_lg_nlOOiO1i15607w(0)) OR wire_w_lg_nlOOilOO15609w(0)); + nlOOilil <= (((wire_w_lg_nlOOlOiO15589w(0) OR wire_w_lg_nlOOiOli15590w(0)) OR wire_w_lg_nlOOiOiO15592w(0)) OR wire_w_lg_nlOOiOil15594w(0)); + nlOOiliO <= ((((((((((((((((((nlOOO0iO OR wire_w_lg_nlOOO1Ol15569w(0)) OR nlOOO1Oi) OR nlOOO1lO) OR nlOOO1ll) OR nlOOO1li) OR nlOOO1iO) OR nlOOO1il) OR nlOOO1ii) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOilli <= (((((((((((((((((nlOOO0iO OR wire_w_lg_nlOOO1Oi15551w(0)) OR nlOOO1lO) OR nlOOO1ll) OR nlOOO1li) OR nlOOO1iO) OR nlOOO1il) OR nlOOO1ii) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOilll <= ((((((((((((((((nlOOO0iO OR wire_w_lg_nlOOO1lO15534w(0)) OR nlOOO1ll) OR nlOOO1li) OR nlOOO1iO) OR nlOOO1il) OR nlOOO1ii) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOillO <= (((((((((((((((nlOOO0iO OR wire_w_lg_nlOOO1ll15518w(0)) OR nlOOO1li) OR nlOOO1iO) OR nlOOO1il) OR nlOOO1ii) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOilOi <= ((((((((((((((nlOOO0iO OR wire_w_lg_nlOOO1li15503w(0)) OR nlOOO1iO) OR nlOOO1il) OR nlOOO1ii) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOilOl <= (((((((((((((nlOOO0iO OR wire_w_lg_nlOOO1iO15489w(0)) OR nlOOO1il) OR nlOOO1ii) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOilOO <= ((((((((((((nlOOO0iO OR wire_w_lg_nlOOO1il15476w(0)) OR nlOOO1ii) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiO0i <= ((((((((nlOOO0iO OR wire_w_lg_nlOOO10i15434w(0)) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiO0l <= (((((((nlOOO0iO OR wire_w_lg_nlOOO11O15426w(0)) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiO0O <= ((((((nlOOO0iO OR wire_w_lg_nlOOO11l15419w(0)) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiO1i <= (((((((((((nlOOO0iO OR wire_w_lg_nlOOO1ii15464w(0)) OR nlOOO10O) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiO1l <= ((((((((((nlOOO0iO OR wire_w_lg_nlOOO10O15453w(0)) OR nlOOO10l) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiO1O <= (((((((((nlOOO0iO OR wire_w_lg_nlOOO10l15443w(0)) OR nlOOO10i) OR nlOOO11O) OR nlOOO11l) OR nlOOO11i) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiOii <= (((((nlOOO0iO OR wire_w_lg_nlOOO11i15413w(0)) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiOil <= ((((wire_w_lg_nlOOO0iO15408w(0) OR nlOOlOOl) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiOiO <= (((wire_w_lg_nlOOlOOl15404w(0) OR nlOOlOlO) OR nlOOlOli) OR nlOOlOiO); + nlOOiOli <= ((wire_w_lg_nlOOlOlO15401w(0) OR nlOOlOli) OR nlOOlOiO); + nlOOiOll <= (wire_w_lg_nlOOlOli15399w(0) OR nlOOlOiO); + nlOOiOlO <= (((((((((wire_w_lg_nlOOl00l15344w(0) OR wire_w_lg_nlOOl01O15348w(0)) OR wire_w_lg_nlOOl01i15352w(0)) OR wire_w_lg_nlOOl1Ol15355w(0)) OR wire_w_lg_nlOOl1lO15359w(0)) OR wire_w_lg_nlOOl1li15363w(0)) OR wire_w_lg_nlOOl1il15371w(0)) OR wire_w_lg_nlOOl10O15375w(0)) OR wire_w_lg_nlOOl10i15386w(0)) OR nlOOiOOi); + nlOOiOOi <= ((((((((((((((((((((nlOOOO1O OR nlOOOO1l) AND wire_w_lg_nlOOOO1i15325w(0)) AND wire_w_lg_nlOOOlOO15307w(0)) AND wire_w_lg_nlOOOlOl15290w(0)) AND wire_w_lg_nlOOOlll15274w(0)) AND wire_w_lg_nlOOOlil15259w(0)) AND wire_w_lg_nlOOOl0l15245w(0)) AND wire_w_lg_nlOOOl1l15232w(0)) AND wire_w_lg_nlOOOiOl15220w(0)) AND wire_w_lg_nlOOOill15209w(0)) AND wire_w_lg_nlOOOiil15199w(0)) AND wire_w_lg_nlOOOi0l15190w(0)) AND wire_w_lg_nlOOOi1l15182w(0)) AND wire_w_lg_nlOOO0Ol15175w(0)) AND wire_w_lg_nlOOO0ll15169w(0)) AND wire_w_lg_nlOOO0il15164w(0)) AND wire_w_lg_nlOOO00O15160w(0)) AND wire_w_lg_nlOOO00i15157w(0)) AND wire_w_lg_nlOOO01l15155w(0)) AND wire_w_lg_nlOOO1OO16446w(0)); + nlOOiOOl <= (((((((((wire_w_lg_nlOOl00l15344w(0) OR wire_w_lg_nlOOl00i15346w(0)) OR wire_w_lg_nlOOl01i15352w(0)) OR wire_w_lg_nlOOl1OO15353w(0)) OR wire_w_lg_nlOOl1lO15359w(0)) OR wire_w_lg_nlOOl1ll15361w(0)) OR wire_w_lg_nlOOl1il15371w(0)) OR wire_w_lg_nlOOl1ii15373w(0)) OR wire_w_lg_nlOOl10i15386w(0)) OR wire_w_lg_nlOOl11O15388w(0)); + nlOOiOOO <= (((((((wire_w_lg_nlOOO1OO15367w(0) OR wire_w_lg_nlOOl1OO15353w(0)) OR wire_w_lg_nlOOl1Ol15355w(0)) OR wire_w_lg_nlOOl1Oi15357w(0)) OR wire_w_lg_nlOOl1il15371w(0)) OR wire_w_lg_nlOOl1ii15373w(0)) OR wire_w_lg_nlOOl10O15375w(0)) OR wire_w_lg_nlOOl10l15377w(0)); + nlOOl00i <= ((wire_w_lg_nlOOO00i15157w(0) OR nlOOO01l) OR nlOOO1OO); + nlOOl00l <= (wire_w_lg_nlOOO01l15155w(0) OR nlOOO1OO); + nlOOl00O <= (((((((((wire_w_lg_nlOOliOl15100w(0) OR wire_w_lg_nlOOlilO15104w(0)) OR wire_w_lg_nlOOlili15108w(0)) OR wire_w_lg_nlOOliil15111w(0)) OR wire_w_lg_nlOOli0O15115w(0)) OR wire_w_lg_nlOOli0i15119w(0)) OR wire_w_lg_nlOOli1l15127w(0)) OR wire_w_lg_nlOOl0OO15131w(0)) OR wire_w_lg_nlOOl0Oi15142w(0)) OR nlOOl0ii); + nlOOl01i <= (((((wire_w_lg_nlOOO0ll15169w(0) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl01l <= ((((wire_w_lg_nlOOO0il15164w(0) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl01O <= (((wire_w_lg_nlOOO00O15160w(0) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl0ii <= ((((wire_nl_w16422w(0) AND wire_w_lg_nlOOOOiO14918w(0)) AND wire_w_lg_nlOOOOii14915w(0)) AND wire_w_lg_nlOOOO0l14913w(0)) AND wire_w_lg_nlOOOO0i16426w(0)); + nlOOl0il <= (((((((((wire_w_lg_nlOOliOl15100w(0) OR wire_w_lg_nlOOliOi15102w(0)) OR wire_w_lg_nlOOlili15108w(0)) OR wire_w_lg_nlOOliiO15109w(0)) OR wire_w_lg_nlOOli0O15115w(0)) OR wire_w_lg_nlOOli0l15117w(0)) OR wire_w_lg_nlOOli1l15127w(0)) OR wire_w_lg_nlOOli1i15129w(0)) OR wire_w_lg_nlOOl0Oi15142w(0)) OR wire_w_lg_nlOOl0lO15144w(0)); + nlOOl0iO <= (((((((wire_w_lg_nlOOOO0i15123w(0) OR wire_w_lg_nlOOliiO15109w(0)) OR wire_w_lg_nlOOliil15111w(0)) OR wire_w_lg_nlOOliii15113w(0)) OR wire_w_lg_nlOOli1l15127w(0)) OR wire_w_lg_nlOOli1i15129w(0)) OR wire_w_lg_nlOOl0OO15131w(0)) OR wire_w_lg_nlOOl0Ol15133w(0)); + nlOOl0li <= (((((((wire_w_lg_nlOOlili15108w(0) OR wire_w_lg_nlOOliiO15109w(0)) OR wire_w_lg_nlOOliil15111w(0)) OR wire_w_lg_nlOOliii15113w(0)) OR wire_w_lg_nlOOli0O15115w(0)) OR wire_w_lg_nlOOli0l15117w(0)) OR wire_w_lg_nlOOli0i15119w(0)) OR wire_w_lg_nlOOli1O15121w(0)); + nlOOl0ll <= (((wire_w_lg_nlOOOO0i15101w(0) OR wire_w_lg_nlOOliOi15102w(0)) OR wire_w_lg_nlOOlilO15104w(0)) OR wire_w_lg_nlOOlill15106w(0)); + nlOOl0lO <= (((((((((((((((((wire_w_lg_w_lg_n11100i14248w15081w(0) OR wire_w_lg_n1111il15082w(0)) OR wire_w_lg_n1111ii15064w(0)) OR wire_w_lg_n11110O15047w(0)) OR wire_w_lg_n11110l15031w(0)) OR wire_w_lg_n11110i15016w(0)) OR wire_w_lg_n11111O15002w(0)) OR wire_w_lg_n11111l14989w(0)) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOl0Oi <= ((((((((((((((((wire_w_lg_w_lg_n11100i14248w15063w(0) OR wire_w_lg_n1111ii15064w(0)) OR wire_w_lg_n11110O15047w(0)) OR wire_w_lg_n11110l15031w(0)) OR wire_w_lg_n11110i15016w(0)) OR wire_w_lg_n11111O15002w(0)) OR wire_w_lg_n11111l14989w(0)) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOl0Ol <= (((((((((((((((wire_w_lg_w_lg_n11100i14248w15046w(0) OR wire_w_lg_n11110O15047w(0)) OR wire_w_lg_n11110l15031w(0)) OR wire_w_lg_n11110i15016w(0)) OR wire_w_lg_n11111O15002w(0)) OR wire_w_lg_n11111l14989w(0)) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOl0OO <= ((((((((((((((wire_w_lg_w_lg_n11100i14248w15030w(0) OR wire_w_lg_n11110l15031w(0)) OR wire_w_lg_n11110i15016w(0)) OR wire_w_lg_n11111O15002w(0)) OR wire_w_lg_n11111l14989w(0)) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOl10i <= (((((((((((((((((wire_w_lg_nlOOOlOO15307w(0) OR nlOOOlOl) OR nlOOOlll) OR nlOOOlil) OR nlOOOl0l) OR nlOOOl1l) OR nlOOOiOl) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl10l <= ((((((((((((((((wire_w_lg_nlOOOlOl15290w(0) OR nlOOOlll) OR nlOOOlil) OR nlOOOl0l) OR nlOOOl1l) OR nlOOOiOl) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl10O <= (((((((((((((((wire_w_lg_nlOOOlll15274w(0) OR nlOOOlil) OR nlOOOl0l) OR nlOOOl1l) OR nlOOOiOl) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl11i <= (((((((wire_w_lg_nlOOl01i15352w(0) OR wire_w_lg_nlOOl1OO15353w(0)) OR wire_w_lg_nlOOl1Ol15355w(0)) OR wire_w_lg_nlOOl1Oi15357w(0)) OR wire_w_lg_nlOOl1lO15359w(0)) OR wire_w_lg_nlOOl1ll15361w(0)) OR wire_w_lg_nlOOl1li15363w(0)) OR wire_w_lg_nlOOl1iO15365w(0)); + nlOOl11l <= (((wire_w_lg_nlOOO1OO15345w(0) OR wire_w_lg_nlOOl00i15346w(0)) OR wire_w_lg_nlOOl01O15348w(0)) OR wire_w_lg_nlOOl01l15350w(0)); + nlOOl11O <= ((((((((((((((((((wire_w_lg_nlOOOO1i15325w(0) OR nlOOOlOO) OR nlOOOlOl) OR nlOOOlll) OR nlOOOlil) OR nlOOOl0l) OR nlOOOl1l) OR nlOOOiOl) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1ii <= ((((((((((((((wire_w_lg_nlOOOlil15259w(0) OR nlOOOl0l) OR nlOOOl1l) OR nlOOOiOl) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1il <= (((((((((((((wire_w_lg_nlOOOl0l15245w(0) OR nlOOOl1l) OR nlOOOiOl) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1iO <= ((((((((((((wire_w_lg_nlOOOl1l15232w(0) OR nlOOOiOl) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1li <= (((((((((((wire_w_lg_nlOOOiOl15220w(0) OR nlOOOill) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1ll <= ((((((((((wire_w_lg_nlOOOill15209w(0) OR nlOOOiil) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1lO <= (((((((((wire_w_lg_nlOOOiil15199w(0) OR nlOOOi0l) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1Oi <= ((((((((wire_w_lg_nlOOOi0l15190w(0) OR nlOOOi1l) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1Ol <= (((((((wire_w_lg_nlOOOi1l15182w(0) OR nlOOO0Ol) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOl1OO <= ((((((wire_w_lg_nlOOO0Ol15175w(0) OR nlOOO0ll) OR nlOOO0il) OR nlOOO00O) OR nlOOO00i) OR nlOOO01l) OR nlOOO1OO); + nlOOli0i <= ((((((((((wire_w_lg_w_lg_n11100i14248w14976w(0) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOli0l <= (((((((((wire_w_lg_w_lg_n11100i14248w14965w(0) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOli0O <= ((((((((wire_w_lg_w_lg_n11100i14248w14955w(0) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOli1i <= (((((((((((((wire_w_lg_w_lg_n11100i14248w15015w(0) OR wire_w_lg_n11110i15016w(0)) OR wire_w_lg_n11111O15002w(0)) OR wire_w_lg_n11111l14989w(0)) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOli1l <= ((((((((((((wire_w_lg_w_lg_n11100i14248w15001w(0) OR wire_w_lg_n11111O15002w(0)) OR wire_w_lg_n11111l14989w(0)) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOli1O <= (((((((((((wire_w_lg_w_lg_n11100i14248w14988w(0) OR wire_w_lg_n11111l14989w(0)) OR wire_w_lg_n11111i14977w(0)) OR wire_w_lg_nlOOOOOO14966w(0)) OR wire_w_lg_nlOOOOOl14956w(0)) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOliii <= (((((((wire_w_lg_w_lg_n11100i14248w14946w(0) OR wire_w_lg_nlOOOOOi14947w(0)) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOliil <= ((((((wire_w_lg_w_lg_n11100i14248w14938w(0) OR wire_w_lg_nlOOOOlO14939w(0)) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOliiO <= (((((wire_w_lg_w_lg_n11100i14248w14931w(0) OR wire_w_lg_nlOOOOll14932w(0)) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOlili <= (((((wire_w_lg_n11100i14248w(0) OR nlOOOOll) OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOlill <= ((((n11100i OR nlOOOOiO) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOlilO <= (((wire_w_lg_nlOOOOiO14918w(0) OR nlOOOOii) OR nlOOOO0l) OR nlOOOO0i); + nlOOliOi <= ((wire_w_lg_nlOOOOii14915w(0) OR nlOOOO0l) OR nlOOOO0i); + nlOOliOl <= (wire_w_lg_nlOOOO0l14913w(0) OR nlOOOO0i); + nlOOliOO <= (((((((((wire_w_lg_nlOOlOil14858w(0) OR wire_w_lg_nlOOlO0O14862w(0)) OR wire_w_lg_nlOOlO0i14866w(0)) OR wire_w_lg_nlOOlO1l14869w(0)) OR wire_w_lg_nlOOllOO14873w(0)) OR wire_w_lg_nlOOllOi14877w(0)) OR wire_w_lg_nlOOllll14885w(0)) OR wire_w_lg_nlOOlliO14889w(0)) OR wire_w_lg_nlOOllii14900w(0)) OR nlOOll1i); + nlOOll0i <= (((((((wire_w_lg_nlOOlO0i14866w(0) OR wire_w_lg_nlOOlO1O14867w(0)) OR wire_w_lg_nlOOlO1l14869w(0)) OR wire_w_lg_nlOOlO1i14871w(0)) OR wire_w_lg_nlOOllOO14873w(0)) OR wire_w_lg_nlOOllOl14875w(0)) OR wire_w_lg_nlOOllOi14877w(0)) OR wire_w_lg_nlOOlllO14879w(0)); + nlOOll0l <= (((wire_w_lg_n1111li14859w(0) OR wire_w_lg_nlOOlOii14860w(0)) OR wire_w_lg_nlOOlO0O14862w(0)) OR wire_w_lg_nlOOlO0l14864w(0)); + nlOOll0O <= ((((((((((((((((((wire_w_lg_n111lll14839w(0) OR n111lli) OR n111liO) OR n111l0O) OR n111l1O) OR n111iOO) OR n111ilO) OR n111iiO) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOll1i <= ((((((((((((((((((((wire_w_lg_w_pmadwidth_range175w16385w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_nlli1Ol16019w(0))) AND wire_w_lg_n111lll14839w(0)) AND wire_w_lg_n111lli14821w(0)) AND wire_w_lg_n111liO14804w(0)) AND wire_w_lg_n111l0O14788w(0)) AND wire_w_lg_n111l1O14773w(0)) AND wire_w_lg_n111iOO14759w(0)) AND wire_w_lg_n111ilO14746w(0)) AND wire_w_lg_n111iiO14734w(0)) AND wire_w_lg_n111i0O14723w(0)) AND wire_w_lg_n111i1O14713w(0)) AND wire_w_lg_n1110OO14704w(0)) AND wire_w_lg_n1110lO14696w(0)) AND wire_w_lg_n1110iO14689w(0)) AND wire_w_lg_n11100O14683w(0)) AND wire_w_lg_n11101O14678w(0)) AND wire_w_lg_n11101i14674w(0)) AND wire_w_lg_n1111Ol14671w(0)) AND wire_w_lg_n1111lO14669w(0)) AND wire_w_lg_n1111li16406w(0)); + nlOOll1l <= (((((((((wire_w_lg_nlOOlOil14858w(0) OR wire_w_lg_nlOOlOii14860w(0)) OR wire_w_lg_nlOOlO0i14866w(0)) OR wire_w_lg_nlOOlO1O14867w(0)) OR wire_w_lg_nlOOllOO14873w(0)) OR wire_w_lg_nlOOllOl14875w(0)) OR wire_w_lg_nlOOllll14885w(0)) OR wire_w_lg_nlOOllli14887w(0)) OR wire_w_lg_nlOOllii14900w(0)) OR wire_w_lg_nlOOll0O14902w(0)); + nlOOll1O <= (((((((wire_w_lg_n1111li14881w(0) OR wire_w_lg_nlOOlO1O14867w(0)) OR wire_w_lg_nlOOlO1l14869w(0)) OR wire_w_lg_nlOOlO1i14871w(0)) OR wire_w_lg_nlOOllll14885w(0)) OR wire_w_lg_nlOOllli14887w(0)) OR wire_w_lg_nlOOlliO14889w(0)) OR wire_w_lg_nlOOllil14891w(0)); + nlOOllii <= (((((((((((((((((wire_w_lg_n111lli14821w(0) OR n111liO) OR n111l0O) OR n111l1O) OR n111iOO) OR n111ilO) OR n111iiO) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOllil <= ((((((((((((((((wire_w_lg_n111liO14804w(0) OR n111l0O) OR n111l1O) OR n111iOO) OR n111ilO) OR n111iiO) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlliO <= (((((((((((((((wire_w_lg_n111l0O14788w(0) OR n111l1O) OR n111iOO) OR n111ilO) OR n111iiO) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOllli <= ((((((((((((((wire_w_lg_n111l1O14773w(0) OR n111iOO) OR n111ilO) OR n111iiO) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOllll <= (((((((((((((wire_w_lg_n111iOO14759w(0) OR n111ilO) OR n111iiO) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlllO <= ((((((((((((wire_w_lg_n111ilO14746w(0) OR n111iiO) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOllOi <= (((((((((((wire_w_lg_n111iiO14734w(0) OR n111i0O) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOllOl <= ((((((((((wire_w_lg_n111i0O14723w(0) OR n111i1O) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOllOO <= (((((((((wire_w_lg_n111i1O14713w(0) OR n1110OO) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlO0i <= (((((wire_w_lg_n11100O14683w(0) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlO0l <= ((((wire_w_lg_n11101O14678w(0) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlO0O <= (((wire_w_lg_n11101i14674w(0) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlO1i <= ((((((((wire_w_lg_n1110OO14704w(0) OR n1110lO) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlO1l <= (((((((wire_w_lg_n1110lO14696w(0) OR n1110iO) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlO1O <= ((((((wire_w_lg_n1110iO14689w(0) OR n11100O) OR n11101O) OR n11101i) OR n1111Ol) OR n1111lO) OR n1111li); + nlOOlOii <= ((wire_w_lg_n1111Ol14671w(0) OR n1111lO) OR n1111li); + nlOOlOil <= (wire_w_lg_n1111lO14669w(0) OR n1111li); + nlOOlOiO <= (pmadwidth(0) AND nlOOO01i); + nlOOlOli <= (pmadwidth(0) AND nlOOlOll); + nlOOlOll <= ((((((((((((((((((nlli01l AND nlli01i) AND nlli1OO) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOlOlO <= (pmadwidth(0) AND nlOOlOOi); + nlOOlOOi <= (((((((((((((((((nlli01i AND nlli1OO) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOlOOl <= (pmadwidth(0) AND nlOOlOOO); + nlOOlOOO <= ((((((((((((((((nlli1OO AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO00i <= (pmadwidth(0) AND nlOOO00l); + nlOOO00l <= ((((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i); + nlOOO00O <= (pmadwidth(0) AND nlOOO0ii); + nlOOO01i <= ((((((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO01l <= (pmadwidth(0) AND nlOOO01O); + nlOOO01O <= (((((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO); + nlOOO0ii <= (((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l); + nlOOO0il <= (wire_w_lg_w_pmadwidth_range175w14499w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14500w(0)); + nlOOO0iO <= ((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO0li <= ((((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O); + nlOOO0ll <= (wire_w_lg_w_pmadwidth_range175w14494w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14495w(0)); + nlOOO0lO <= (((((((((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO); + nlOOO0Oi <= (((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i); + nlOOO0Ol <= (wire_w_lg_w_pmadwidth_range175w14489w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14490w(0)); + nlOOO0OO <= ((((((((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i); + nlOOO10i <= (((((((((((nlli1li AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO10l <= ((((((((((nlli1iO AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO10O <= (((((((((nlli1il AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO11i <= ((((((((((((((nlli1Oi AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO11l <= (((((((((((((nlli1lO AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO11O <= ((((((((((((nlli1ll AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO1ii <= ((((((((nlli1ii AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO1il <= (((((((nlli10O AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO1iO <= ((((((nlli10l AND nlli10i) AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO1li <= (((((nlli10i AND nlli11O) AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO1ll <= ((((nlli11O AND nlli11l) AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO1lO <= (((nlli11l AND nlli11i) AND nll0OOO) AND nll0OOl); + nlOOO1Oi <= ((nlli11i AND nll0OOO) AND nll0OOl); + nlOOO1Ol <= (nll0OOO AND nll0OOl); + nlOOO1OO <= (pmadwidth(0) AND nlOOO01i); + nlOOOi0i <= (((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O); + nlOOOi0l <= (wire_w_lg_w_pmadwidth_range175w14479w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14480w(0)); + nlOOOi0O <= ((((((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O); + nlOOOi1i <= ((((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l); + nlOOOi1l <= (wire_w_lg_w_pmadwidth_range175w14484w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14485w(0)); + nlOOOi1O <= (((((((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i) AND nlli11O) AND nlli11l); + nlOOOiii <= ((((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii); + nlOOOiil <= (wire_w_lg_w_pmadwidth_range175w14474w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14475w(0)); + nlOOOiiO <= (((((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l) AND nlli10i); + nlOOOili <= (((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO) AND nlli1il); + nlOOOill <= (wire_w_lg_w_pmadwidth_range175w14469w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14470w(0)); + nlOOOilO <= ((((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O) AND nlli10l); + nlOOOiOi <= ((((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li) AND nlli1iO); + nlOOOiOl <= (wire_w_lg_w_pmadwidth_range175w14464w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14465w(0)); + nlOOOiOO <= (((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii) AND nlli10O); + nlOOOl0i <= ((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll); + nlOOOl0l <= (wire_w_lg_w_pmadwidth_range175w14454w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14455w(0)); + nlOOOl0O <= (((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il); + nlOOOl1i <= (((((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO) AND nlli1ll) AND nlli1li); + nlOOOl1l <= (wire_w_lg_w_pmadwidth_range175w14459w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14460w(0)); + nlOOOl1O <= ((((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO) AND nlli1il) AND nlli1ii); + nlOOOlii <= (((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi) AND nlli1lO); + nlOOOlil <= (wire_w_lg_w_pmadwidth_range175w14449w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14450w(0)); + nlOOOliO <= ((wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li) AND nlli1iO); + nlOOOlli <= ((wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol) AND nlli1Oi); + nlOOOlll <= (wire_w_lg_w_pmadwidth_range175w14444w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14445w(0)); + nlOOOllO <= (wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) AND nlli1li); + nlOOOlOi <= (wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) AND nlli1Ol); + nlOOOlOl <= (wire_w_lg_w_pmadwidth_range175w14438w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0))); + nlOOOlOO <= (wire_w_lg_w_pmadwidth_range175w14433w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_w_lg_nlli1Ol14429w14434w(0))); + nlOOOO0i <= wire_w_lg_w_pmadwidth_range175w14262w(0); + nlOOOO0l <= wire_w_lg_w_pmadwidth_range175w14424w(0); + nlOOOO0O <= ((((((((((((((((((nlli01l OR nlli01i) OR nlli1OO) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + nlOOOO1i <= (wire_w_lg_w_pmadwidth_range175w14428w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_nl_w_lg_nlli1Ol14429w(0))); + nlOOOO1l <= (wire_w_lg_w_pmadwidth_range175w219w(0) AND nlli1Ol); + nlOOOO1O <= (pmadwidth(0) AND nlli01O); + nlOOOOii <= wire_w_lg_w_pmadwidth_range175w14404w(0); + nlOOOOil <= (((((((((((((((((nlli01i OR nlli1OO) OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + nlOOOOiO <= wire_w_lg_w_pmadwidth_range175w14385w(0); + nlOOOOli <= ((((((((((((((((nlli1OO OR nlli1Ol) OR nlli1Oi) OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + nlOOOOll <= ((((((((((((((nlli1Oi OR nlli1lO) OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + nlOOOOlO <= (((((((((((((nlli1lO OR nlli1ll) OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + nlOOOOOi <= ((((((((((((nlli1ll OR nlli1li) OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + nlOOOOOl <= (((((((((((nlli1li OR nlli1iO) OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + nlOOOOOO <= ((((((((((nlli1iO OR nlli1il) OR nlli1ii) OR nlli10O) OR nlli10l) OR nlli10i) OR nlli11O) OR nlli11l) OR nlli11i) OR nll0OOO) OR nll0OOl); + rlv <= wire_n0il_dataout; + rlv_lt <= wire_n0ii_dataout; + rst1 <= wire_ni0lO_dataout; + signal_detect_rcvdclk <= signal_detect; + sudi <= ( wire_nlll_dataout & wire_nlli_dataout & wire_nliO_dataout & wire_nlil_dataout & wire_nlii_dataout & wire_nl0O_dataout & wire_nl0l_dataout & wire_nl0i_dataout & wire_nl1O_dataout & wire_nl1l_dataout & wire_nl1i_dataout & wire_niOO_dataout & wire_niOl_dataout & wire_niOi_dataout & wire_nilO_dataout & wire_nill_dataout & wire_nili_dataout & wire_niiO_dataout & wire_niil_dataout & wire_niii_dataout & wire_ni0O_dataout & wire_ni0l_dataout & wire_ni0i_dataout & wire_ni1O_dataout & wire_ni1l_dataout & wire_ni1i_dataout & wire_n0OO_dataout & wire_n0Ol_dataout & wire_n0Oi_dataout & wire_n0lO_dataout & wire_n0ll_dataout & wire_n0li_dataout); + sudi_pre <= ( wire_n110ll_dataout & n1ii0iO & wire_w182w & wire_n1l1Ol_w_lg_dataout173w & wire_niOl0l_dataout & wire_niOl0i_dataout & wire_niOl1O_o & wire_niOl1l_o & wire_niOl1i_o & wire_niOiOO_o & wire_niOiOl_o & wire_niOiOi_o & wire_niOilO_o & wire_niOill_o); + sync_status <= wire_n0iO_dataout; + testbus <= ( wire_nil_dataout & wire_nii_dataout & wire_n0O_dataout & wire_n0l_dataout & wire_n0i_dataout & wire_n1O_dataout & wire_n1l_dataout & wire_n1i_dataout & wire_nlOO_dataout & wire_nlOl_dataout); + wa_boundary <= ( wire_nii0l_dataout & wire_nii0i_dataout & wire_nii1O_dataout & wire_nii1l_dataout & wire_nii1i_dataout); + wire_w_comp_pat_size_range1330w(0) <= comp_pat_size(0); + wire_w_comp_pat_size_range1331w(0) <= comp_pat_size(1); + wire_w_ib_invalid_code_range3169w(0) <= ib_invalid_code(0); + wire_w_ib_invalid_code_range3176w(0) <= ib_invalid_code(1); + wire_w_pmadwidth_range175w(0) <= pmadwidth(0); + wire_w_r8b10b_dec_ibm_en_range3034w(0) <= r8b10b_dec_ibm_en(1); + wire_w_resync_badcg_en_range4511w(0) <= resync_badcg_en(0); + wire_w_resync_badcg_en_range4513w(0) <= resync_badcg_en(1); + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i00OO49 <= n1i00OO50; + END IF; + if (now = 0 ns) then + n1i00OO49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i00OO50 <= n1i00OO49; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0lOi47 <= n1i0lOi48; + END IF; + if (now = 0 ns) then + n1i0lOi47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0lOi48 <= n1i0lOi47; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0O0i43 <= n1i0O0i44; + END IF; + if (now = 0 ns) then + n1i0O0i43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0O0i44 <= n1i0O0i43; + END IF; + END PROCESS; + wire_n1i0O0i44_w_lg_q340w(0) <= n1i0O0i44 XOR n1i0O0i43; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0O1l45 <= n1i0O1l46; + END IF; + if (now = 0 ns) then + n1i0O1l45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0O1l46 <= n1i0O1l45; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0Oil41 <= n1i0Oil42; + END IF; + if (now = 0 ns) then + n1i0Oil41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0Oil42 <= n1i0Oil41; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0Oli39 <= n1i0Oli40; + END IF; + if (now = 0 ns) then + n1i0Oli39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0Oli40 <= n1i0Oli39; + END IF; + END PROCESS; + wire_n1i0Oli40_w_lg_q324w(0) <= n1i0Oli40 XOR n1i0Oli39; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0OlO37 <= n1i0OlO38; + END IF; + if (now = 0 ns) then + n1i0OlO37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0OlO38 <= n1i0OlO37; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0OOl35 <= n1i0OOl36; + END IF; + if (now = 0 ns) then + n1i0OOl35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1i0OOl36 <= n1i0OOl35; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii00O19 <= n1ii00O20; + END IF; + if (now = 0 ns) then + n1ii00O19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii00O20 <= n1ii00O19; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii0ii17 <= n1ii0ii18; + END IF; + if (now = 0 ns) then + n1ii0ii17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii0ii18 <= n1ii0ii17; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii0ll15 <= n1ii0ll16; + END IF; + if (now = 0 ns) then + n1ii0ll15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii0ll16 <= n1ii0ll15; + END IF; + END PROCESS; + wire_n1ii0ll16_w_lg_w_lg_q179w180w(0) <= NOT wire_n1ii0ll16_w_lg_q179w(0); + wire_n1ii0ll16_w_lg_q179w(0) <= n1ii0ll16 XOR n1ii0ll15; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii0OO13 <= n1ii0OO14; + END IF; + if (now = 0 ns) then + n1ii0OO13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii0OO14 <= n1ii0OO13; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii10l33 <= n1ii10l34; + END IF; + if (now = 0 ns) then + n1ii10l33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii10l34 <= n1ii10l33; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1ii31 <= n1ii1ii32; + END IF; + if (now = 0 ns) then + n1ii1ii31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1ii32 <= n1ii1ii31; + END IF; + END PROCESS; + wire_n1ii1ii32_w_lg_w_lg_q274w275w(0) <= wire_n1ii1ii32_w_lg_q274w(0) AND nlllOO; + wire_n1ii1ii32_w_lg_q274w(0) <= n1ii1ii32 XOR n1ii1ii31; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1il29 <= n1ii1il30; + END IF; + if (now = 0 ns) then + n1ii1il29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1il30 <= n1ii1il29; + END IF; + END PROCESS; + wire_n1ii1il30_w_lg_w_lg_q270w271w(0) <= wire_n1ii1il30_w_lg_q270w(0) AND nlllOl; + wire_n1ii1il30_w_lg_q270w(0) <= n1ii1il30 XOR n1ii1il29; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1iO27 <= n1ii1iO28; + END IF; + if (now = 0 ns) then + n1ii1iO27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1iO28 <= n1ii1iO27; + END IF; + END PROCESS; + wire_n1ii1iO28_w_lg_w_lg_q258w259w(0) <= wire_n1ii1iO28_w_lg_q258w(0) AND wire_nlll0O_dataout; + wire_n1ii1iO28_w_lg_q258w(0) <= n1ii1iO28 XOR n1ii1iO27; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1li25 <= n1ii1li26; + END IF; + if (now = 0 ns) then + n1ii1li25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1li26 <= n1ii1li25; + END IF; + END PROCESS; + wire_n1ii1li26_w_lg_w_lg_q243w244w(0) <= wire_n1ii1li26_w_lg_q243w(0) AND nllO1l; + wire_n1ii1li26_w_lg_q243w(0) <= n1ii1li26 XOR n1ii1li25; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1ll23 <= n1ii1ll24; + END IF; + if (now = 0 ns) then + n1ii1ll23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1ll24 <= n1ii1ll23; + END IF; + END PROCESS; + wire_n1ii1ll24_w_lg_w_lg_q240w241w(0) <= wire_n1ii1ll24_w_lg_q240w(0) AND nlllOO; + wire_n1ii1ll24_w_lg_q240w(0) <= n1ii1ll24 XOR n1ii1ll23; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1Oi21 <= n1ii1Oi22; + END IF; + if (now = 0 ns) then + n1ii1Oi21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1ii1Oi22 <= n1ii1Oi21; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iii0i11 <= n1iii0i12; + END IF; + if (now = 0 ns) then + n1iii0i11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iii0i12 <= n1iii0i11; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iii0O10 <= n1iii0O9; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iii0O9 <= n1iii0O10; + END IF; + if (now = 0 ns) then + n1iii0O9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iiiil7 <= n1iiiil8; + END IF; + if (now = 0 ns) then + n1iiiil7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iiiil8 <= n1iiiil7; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iiiOl5 <= n1iiiOl6; + END IF; + if (now = 0 ns) then + n1iiiOl5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iiiOl6 <= n1iiiOl5; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iil0O1 <= n1iil0O2; + END IF; + if (now = 0 ns) then + n1iil0O1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iil0O2 <= n1iil0O1; + END IF; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iil1i3 <= n1iil1i4; + END IF; + if (now = 0 ns) then + n1iil1i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk) + BEGIN + IF (clk = '1' AND clk'event) THEN n1iil1i4 <= n1iil1i3; + END IF; + END PROCESS; + wire_n1iil1i4_w_lg_q7w(0) <= n1iil1i4 XOR n1iil1i3; + PROCESS (clk, rst, wire_ni0Oi_CLRN) + BEGIN + IF (rst = '1') THEN + ni0li <= '1'; + ni0Ol <= '1'; + ELSIF (wire_ni0Oi_CLRN = '0') THEN + ni0li <= '0'; + ni0Ol <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + ni0li <= ni0Ol; + ni0Ol <= n1iii1i; + END IF; + if (now = 0 ns) then + ni0li <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni0Ol <= '1' after 1 ps; + end if; + END PROCESS; + wire_ni0Oi_CLRN <= (n1ii0OO14 XOR n1ii0OO13); + PROCESS (clk, wire_nl_CLRN) + BEGIN + IF (wire_nl_CLRN = '0') THEN + n01000i <= '0'; + n01000l <= '0'; + n01000O <= '0'; + n01001i <= '0'; + n01001l <= '0'; + n01001O <= '0'; + n0100ii <= '0'; + n0100il <= '0'; + n0101il <= '0'; + n0101iO <= '0'; + n0101li <= '0'; + n0101ll <= '0'; + n0101lO <= '0'; + n0101Oi <= '0'; + n0101Ol <= '0'; + n0101OO <= '0'; + n010Ol <= '0'; + n010OO <= '0'; + n0110i <= '0'; + n0110l <= '0'; + n0110O <= '0'; + n0111i <= '0'; + n0111l <= '0'; + n0111O <= '0'; + n011ii <= '0'; + n011il <= '0'; + n011iO <= '0'; + n011l0i <= '0'; + n011l0l <= '0'; + n011l0O <= '0'; + n011l1l <= '0'; + n011l1O <= '0'; + n011li <= '0'; + n011lii <= '0'; + n011lil <= '0'; + n011liO <= '0'; + n011ll <= '0'; + n011lli <= '0'; + n011lll <= '0'; + n011llO <= '0'; + n011lO <= '0'; + n011lOi <= '0'; + n011lOl <= '0'; + n011lOO <= '0'; + n011O0i <= '0'; + n011O1i <= '0'; + n011O1l <= '0'; + n011O1O <= '0'; + n011Oi <= '0'; + n01i0i <= '0'; + n01i0l <= '0'; + n01i0O <= '0'; + n01i1i <= '0'; + n01i1l <= '0'; + n01i1O <= '0'; + n01iii <= '0'; + n01iil <= '0'; + n01iiO <= '0'; + n01ili <= '0'; + n01ill <= '0'; + n1l00O <= '0'; + n1l0ii <= '0'; + n1l0il <= '0'; + n1l0iO <= '0'; + n1l0li <= '0'; + n1l0ll <= '0'; + n1l0lO <= '0'; + n1l0Oi <= '0'; + n1liii <= '0'; + n1O01i <= '0'; + n1O01O <= '0'; + n1O1ll <= '0'; + n1O1lO <= '0'; + n1O1Oi <= '0'; + n1O1Ol <= '0'; + n1O1OO <= '0'; + n1Oi0i <= '0'; + n1Oi0l <= '0'; + n1Oi0O <= '0'; + n1Oi1O <= '0'; + n1OilO <= '0'; + n1OiOi <= '0'; + n1OiOl <= '0'; + n1OiOO <= '0'; + n1Ol00i <= '0'; + n1Ol00l <= '0'; + n1Ol00O <= '0'; + n1Ol01i <= '0'; + n1Ol01l <= '0'; + n1Ol01O <= '0'; + n1Ol0ii <= '0'; + n1Ol0il <= '0'; + n1Ol1Ol <= '0'; + n1Ol1OO <= '0'; + n1Oli0i <= '0'; + n1OO00i <= '0'; + n1OO01i <= '0'; + n1OO01l <= '0'; + n1OO0iO <= '0'; + n1OO0li <= '0'; + n1OO0ll <= '0'; + n1OO0lO <= '0'; + n1OO1lO <= '0'; + n1OO1Oi <= '0'; + n1OO1Ol <= '0'; + n1OO1OO <= '0'; + n1OOi0i <= '0'; + n1OOi1O <= '0'; + n1OOOl <= '0'; + n1OOOO <= '0'; + ni0iO <= '0'; + ni0OO <= '0'; + niii0i <= '0'; + niii0l <= '0'; + niii0O <= '0'; + niiill <= '0'; + nil00i <= '0'; + nil00l <= '0'; + nil00O <= '0'; + nil01i <= '0'; + nil01l <= '0'; + nil01O <= '0'; + nil0ii <= '0'; + nil0il <= '0'; + nil0iO <= '0'; + nil0li <= '0'; + nil0ll <= '0'; + nil0lO <= '0'; + nil0Oi <= '0'; + nil0Ol <= '0'; + nil0OO <= '0'; + nil1il <= '0'; + nil1iO <= '0'; + nil1li <= '0'; + nil1ll <= '0'; + nil1lO <= '0'; + nil1Ol <= '0'; + nil1OO <= '0'; + nili0i <= '0'; + nili0l <= '0'; + nili0O <= '0'; + nili1i <= '0'; + nili1l <= '0'; + nili1O <= '0'; + niliii <= '0'; + niliil <= '0'; + niliiO <= '0'; + nilili <= '0'; + nilill <= '0'; + nililO <= '0'; + niliOi <= '0'; + niliOl <= '0'; + niliOO <= '0'; + nill0i <= '0'; + nill0l <= '0'; + nill1i <= '0'; + nill1l <= '0'; + nill1O <= '0'; + niOlii <= '0'; + niOlil <= '0'; + niOlli <= '0'; + niOlll <= '0'; + niOllO <= '0'; + niOlOi <= '0'; + niOlOl <= '0'; + niOlOO <= '0'; + niOO0i <= '0'; + niOO1i <= '0'; + niOO1l <= '0'; + niOO1O <= '0'; + niOOOO <= '0'; + nl010il <= '0'; + nl010iO <= '0'; + nl010li <= '0'; + nl010ll <= '0'; + nl010lO <= '0'; + nl010Oi <= '0'; + nl010Ol <= '0'; + nl010OO <= '0'; + nl0110i <= '0'; + nl0110l <= '0'; + nl0110O <= '0'; + nl0111i <= '0'; + nl0111l <= '0'; + nl0111O <= '0'; + nl011ii <= '0'; + nl011il <= '0'; + nl011iO <= '0'; + nl011li <= '0'; + nl011ll <= '0'; + nl011lO <= '0'; + nl01i0i <= '0'; + nl01i0l <= '0'; + nl01i0O <= '0'; + nl01i1i <= '0'; + nl01i1l <= '0'; + nl01i1O <= '0'; + nl01iii <= '0'; + nl01iil <= '0'; + nl01iiO <= '0'; + nl01ili <= '0'; + nl01ill <= '0'; + nl01ilO <= '0'; + nl01iOi <= '0'; + nl01iOl <= '0'; + nl01iOO <= '0'; + nl01l0i <= '0'; + nl01l0l <= '0'; + nl01l0O <= '0'; + nl01l1i <= '0'; + nl01l1l <= '0'; + nl01l1O <= '0'; + nl01lii <= '0'; + nl01lil <= '0'; + nl01liO <= '0'; + nl01lli <= '0'; + nl01lll <= '0'; + nl01llO <= '0'; + nl01lOi <= '0'; + nl01lOl <= '0'; + nl01lOO <= '0'; + nl01O1i <= '0'; + nl01O1l <= '0'; + nl01O1O <= '0'; + nl100l <= '0'; + nl100O <= '0'; + nl10ii <= '0'; + nl10Ol <= '0'; + nl110i <= '0'; + nl110l <= '0'; + nl110O <= '0'; + nl111i <= '0'; + nl111l <= '0'; + nl111O <= '0'; + nl11ii <= '0'; + nl11il <= '0'; + nl11iO <= '0'; + nl1ill <= '0'; + nl1ilO <= '0'; + nl1l1l <= '0'; + nl1lii <= '0'; + nl1liii <= '0'; + nl1liil <= '0'; + nl1lOi <= '0'; + nl1Oiil <= '0'; + nl1OiiO <= '0'; + nl1Oili <= '0'; + nl1Oill <= '0'; + nl1OilO <= '0'; + nl1OiOi <= '0'; + nl1OiOl <= '0'; + nl1OiOO <= '0'; + nl1Ol0i <= '0'; + nl1Ol0l <= '0'; + nl1Ol0O <= '0'; + nl1Ol1i <= '0'; + nl1Ol1l <= '0'; + nl1Ol1O <= '0'; + nl1Olii <= '0'; + nl1Olil <= '0'; + nl1OliO <= '0'; + nl1Olli <= '0'; + nl1Olll <= '0'; + nl1OllO <= '0'; + nl1OlOi <= '0'; + nl1OlOl <= '0'; + nl1OlOO <= '0'; + nl1OO0i <= '0'; + nl1OO0l <= '0'; + nl1OO0O <= '0'; + nl1OO1i <= '0'; + nl1OO1l <= '0'; + nl1OO1O <= '0'; + nl1OOii <= '0'; + nl1OOil <= '0'; + nl1OOiO <= '0'; + nl1OOli <= '0'; + nl1OOll <= '0'; + nl1OOlO <= '0'; + nl1OOOi <= '0'; + nl1OOOl <= '0'; + nl1OOOO <= '0'; + nliiOl <= '0'; + nliiOO <= '0'; + nlil0i <= '0'; + nlil0l <= '0'; + nlil0O <= '0'; + nlil1i <= '0'; + nlil1l <= '0'; + nlil1O <= '0'; + nlilii <= '0'; + nlilll <= '0'; + nlillO <= '0'; + nlilOi <= '0'; + nlilOl <= '0'; + nlilOO <= '0'; + nliO0i <= '0'; + nliO0l <= '0'; + nliO0O <= '0'; + nliO1i <= '0'; + nliO1l <= '0'; + nliO1O <= '0'; + nliOii <= '0'; + nliOil <= '0'; + nliOiO <= '0'; + nliOli <= '0'; + nliOll <= '0'; + nliOlO <= '0'; + nliOOi <= '0'; + nliOOl <= '0'; + nliOOO <= '0'; + nll000i <= '0'; + nll000l <= '0'; + nll000O <= '0'; + nll001i <= '0'; + nll001l <= '0'; + nll001O <= '0'; + nll00ii <= '0'; + nll00il <= '0'; + nll00iO <= '0'; + nll00li <= '0'; + nll00ll <= '0'; + nll00lO <= '0'; + nll00Oi <= '0'; + nll00Ol <= '0'; + nll00OO <= '0'; + nll01ll <= '0'; + nll01lO <= '0'; + nll01Oi <= '0'; + nll01Ol <= '0'; + nll01OO <= '0'; + nll0i0i <= '0'; + nll0i0l <= '0'; + nll0i0O <= '0'; + nll0i1i <= '0'; + nll0i1l <= '0'; + nll0i1O <= '0'; + nll0iii <= '0'; + nll0iil <= '0'; + nll0iiO <= '0'; + nll0ili <= '0'; + nll0ill <= '0'; + nll0ilO <= '0'; + nll0iOi <= '0'; + nll0iOl <= '0'; + nll0iOO <= '0'; + nll0l0i <= '0'; + nll0l0l <= '0'; + nll0l0O <= '0'; + nll0l1i <= '0'; + nll0l1l <= '0'; + nll0l1O <= '0'; + nll0lii <= '0'; + nll0lil <= '0'; + nll0liO <= '0'; + nll0lli <= '0'; + nll0lll <= '0'; + nll0llO <= '0'; + nll0lOi <= '0'; + nll0lOl <= '0'; + nll0lOO <= '0'; + nll0O0i <= '0'; + nll0O0l <= '0'; + nll0O0O <= '0'; + nll0O1i <= '0'; + nll0O1l <= '0'; + nll0O1O <= '0'; + nll0Oii <= '0'; + nll0Oil <= '0'; + nll0OiO <= '0'; + nll0Oli <= '0'; + nll0Oll <= '0'; + nll0OlO <= '0'; + nll0OOi <= '0'; + nll0OOl <= '0'; + nll0OOO <= '0'; + nll10i <= '0'; + nll11i <= '0'; + nll11l <= '0'; + nll11O <= '0'; + nlli00i <= '0'; + nlli00l <= '0'; + nlli00O <= '0'; + nlli01i <= '0'; + nlli01l <= '0'; + nlli01O <= '0'; + nlli0ii <= '0'; + nlli0il <= '0'; + nlli0iO <= '0'; + nlli0li <= '0'; + nlli0ll <= '0'; + nlli0lO <= '0'; + nlli0Oi <= '0'; + nlli0Ol <= '0'; + nlli0OO <= '0'; + nlli10i <= '0'; + nlli10l <= '0'; + nlli10O <= '0'; + nlli11i <= '0'; + nlli11l <= '0'; + nlli11O <= '0'; + nlli1ii <= '0'; + nlli1il <= '0'; + nlli1iO <= '0'; + nlli1li <= '0'; + nlli1ll <= '0'; + nlli1lO <= '0'; + nlli1Oi <= '0'; + nlli1Ol <= '0'; + nlli1OO <= '0'; + nllii0i <= '0'; + nllii0l <= '0'; + nllii1i <= '0'; + nllii1l <= '0'; + nllii1O <= '0'; + nllll1i <= '0'; + nlllOl <= '0'; + nlllOO <= '0'; + nlO <= '0'; + nlO000i <= '0'; + nlO000l <= '0'; + nlO000O <= '0'; + nlO001i <= '0'; + nlO001l <= '0'; + nlO001O <= '0'; + nlO00ii <= '0'; + nlO00il <= '0'; + nlO00iO <= '0'; + nlO00li <= '0'; + nlO00ll <= '0'; + nlO00lO <= '0'; + nlO00Oi <= '0'; + nlO00Ol <= '0'; + nlO00OO <= '0'; + nlO010i <= '0'; + nlO010l <= '0'; + nlO011i <= '0'; + nlO011l <= '0'; + nlO011O <= '0'; + nlO01ii <= '0'; + nlO01il <= '0'; + nlO01iO <= '0'; + nlO01li <= '0'; + nlO01ll <= '0'; + nlO01lO <= '0'; + nlO01Oi <= '0'; + nlO01Ol <= '0'; + nlO01OO <= '0'; + nlO0i0i <= '0'; + nlO0i0l <= '0'; + nlO0i0O <= '0'; + nlO0i1i <= '0'; + nlO0i1l <= '0'; + nlO0i1O <= '0'; + nlO0iii <= '0'; + nlO0iil <= '0'; + nlO0iiO <= '0'; + nlO0ili <= '0'; + nlO0ill <= '0'; + nlO0ilO <= '0'; + nlO0l1i <= '0'; + nlO0l1l <= '0'; + nlO0l1O <= '0'; + nlOi0ll <= '0'; + nlOi0lO <= '0'; + nlOi0Oi <= '0'; + nlOi0Ol <= '0'; + nlOi0OO <= '0'; + nlOii0i <= '0'; + nlOii0l <= '0'; + nlOii0O <= '0'; + nlOii1i <= '0'; + nlOii1l <= '0'; + nlOii1O <= '0'; + nlOiiii <= '0'; + nlOiiil <= '0'; + nlOiiiO <= '0'; + nlOiili <= '0'; + nlOiill <= '0'; + nlOiilO <= '0'; + nlOilOl <= '0'; + nlOilOO <= '0'; + nlOiO0i <= '0'; + nlOiO0l <= '0'; + nlOiO1i <= '0'; + nlOiO1l <= '0'; + nlOiO1O <= '0'; + nO <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + n01000i <= wire_n010i0O_dataout; + n01000l <= wire_n010iii_dataout; + n01000O <= wire_n010iil_dataout; + n01001i <= wire_n010i1O_dataout; + n01001l <= wire_n010i0i_dataout; + n01001O <= wire_n010i0l_dataout; + n0100ii <= wire_n010iiO_dataout; + n0100il <= wire_n010ili_dataout; + n0101il <= wire_n0100li_dataout; + n0101iO <= wire_n0100ll_dataout; + n0101li <= wire_n0100lO_dataout; + n0101ll <= wire_n0100Oi_dataout; + n0101lO <= wire_n0100Ol_dataout; + n0101Oi <= wire_n0100OO_dataout; + n0101Ol <= wire_n010i1i_dataout; + n0101OO <= wire_n010i1l_dataout; + n010Ol <= wire_n01iOi_dataout; + n010OO <= wire_n01iOl_dataout; + n0110i <= wire_n0100l_dataout; + n0110l <= wire_n0100O_dataout; + n0110O <= wire_n010ii_dataout; + n0111i <= wire_n0101l_dataout; + n0111l <= wire_n0101O_dataout; + n0111O <= wire_n0100i_dataout; + n011ii <= wire_n010il_dataout; + n011il <= wire_n010iO_dataout; + n011iO <= wire_n010li_dataout; + n011l0i <= wire_n011Oil_dataout; + n011l0l <= wire_n011OiO_dataout; + n011l0O <= wire_n011Oli_dataout; + n011l1l <= wire_n011O0O_dataout; + n011l1O <= wire_n011Oii_dataout; + n011li <= wire_n010ll_dataout; + n011lii <= wire_n011Oll_dataout; + n011lil <= wire_n011OlO_dataout; + n011liO <= wire_n011OOi_dataout; + n011ll <= wire_n010lO_dataout; + n011lli <= wire_n011OOl_dataout; + n011lll <= wire_n011OOO_dataout; + n011llO <= wire_n01011i_dataout; + n011lO <= wire_n010Oi_dataout; + n011lOi <= wire_n01011l_dataout; + n011lOl <= wire_n01011O_dataout; + n011lOO <= wire_n01010i_dataout; + n011O0i <= wire_n0100iO_dataout; + n011O1i <= wire_n01010l_dataout; + n011O1l <= wire_n01010O_dataout; + n011O1O <= wire_n0101ii_dataout; + n011Oi <= wire_n01ilO_dataout; + n01i0i <= wire_n01l1O_dataout; + n01i0l <= wire_n01l0i_dataout; + n01i0O <= wire_n01l0l_dataout; + n01i1i <= wire_n01iOO_dataout; + n01i1l <= wire_n01l1i_dataout; + n01i1O <= wire_n01l1l_dataout; + n01iii <= wire_n01l0O_dataout; + n01iil <= wire_n01lii_dataout; + n01iiO <= wire_n01lil_dataout; + n01ili <= wire_n01liO_dataout; + n01ill <= wire_n01lli_dataout; + n1l00O <= wire_n1li0i_o(1); + n1l0ii <= wire_n1li0i_o(2); + n1l0il <= wire_n1li0i_o(3); + n1l0iO <= wire_n1l0Ol_dataout; + n1l0li <= wire_n1l0OO_dataout; + n1l0ll <= wire_n1li1i_dataout; + n1l0lO <= wire_n1li1l_dataout; + n1l0Oi <= wire_n1ll0O_o; + n1liii <= wire_n1li0i_o(0); + n1O01i <= wire_n1llOO_dataout; + n1O01O <= wire_n1Oiii_dataout; + n1O1ll <= wire_n1llil_o; + n1O1lO <= wire_n1lliO_dataout; + n1O1Oi <= wire_n1llli_o; + n1O1Ol <= wire_n1lllO_o; + n1O1OO <= wire_n1llOl_dataout; + n1Oi0i <= wire_n1OiiO_dataout; + n1Oi0l <= wire_n1Oili_dataout; + n1Oi0O <= n1OilO; + n1Oi1O <= wire_n1Oiil_dataout; + n1OilO <= (n011Oi OR n1OiOO); + n1OiOi <= n1OiOl; + n1OiOl <= rlv_en; + n1OiOO <= wire_n011Ol_dataout; + n1Ol00i <= wire_n1Ol0li_dataout; + n1Ol00l <= wire_n1Ol0ll_dataout; + n1Ol00O <= wire_n1Ol0lO_dataout; + n1Ol01i <= wire_n1Ol0OO_o(3); + n1Ol01l <= wire_n1Ol0OO_o(4); + n1Ol01O <= wire_n1Ol0iO_dataout; + n1Ol0ii <= wire_n1Ol0Oi_dataout; + n1Ol0il <= wire_n1Oll0l_o; + n1Ol1Ol <= wire_n1Ol0OO_o(1); + n1Ol1OO <= wire_n1Ol0OO_o(2); + n1Oli0i <= wire_n1Ol0OO_o(0); + n1OO00i <= wire_n1OO0Oi_dataout; + n1OO01i <= wire_n1OllOi_dataout; + n1OO01l <= wire_n1OllOl_dataout; + n1OO0iO <= wire_n1OO0Ol_dataout; + n1OO0li <= wire_n1OO0OO_dataout; + n1OO0ll <= wire_n1OOi1i_dataout; + n1OO0lO <= n1OOi1O; + n1OO1lO <= wire_n1Ollii_o; + n1OO1Oi <= wire_n1Ollil_dataout; + n1OO1Ol <= wire_n1OlliO_o; + n1OO1OO <= wire_n1Ollll_o; + n1OOi0i <= wire_n011O0l_dataout; + n1OOi1O <= (n011O0i OR n1OOi0i); + n1OOOl <= wire_n011OO_dataout; + n1OOOO <= wire_n0101i_dataout; + ni0iO <= (rpolinv_en AND polinv_en); + ni0OO <= nlO; + niii0i <= wire_n110ll_dataout; + niii0l <= (wire_w_lg_w_lg_n1i1Oil1323w1324w(0) OR wire_w_lg_w_pmadwidth_range175w1328w(0)); + niii0O <= nil1li; + niiill <= (((n1i1OlO OR n1i1Oll) OR (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w1315w(0)))) OR wire_niOl0l_w_lg_dataout1321w(0)); + nil00i <= wire_nillOO_dataout; + nil00l <= wire_nilO1i_dataout; + nil00O <= wire_nilO1l_dataout; + nil01i <= wire_nilllO_dataout; + nil01l <= wire_nillOi_dataout; + nil01O <= wire_nillOl_dataout; + nil0ii <= wire_nilO1O_dataout; + nil0il <= wire_nilO0i_dataout; + nil0iO <= wire_nilO0l_dataout; + nil0li <= wire_nilO0O_dataout; + nil0ll <= wire_n1l1Ol_w_lg_dataout173w(0); + nil0lO <= (n1ii0li OR (n1ii0Oi OR wire_w_lg_w_pmadwidth_range175w176w(0))); + nil0Oi <= n1ii0iO; + nil0Ol <= wire_n110ll_dataout; + nil0OO <= wire_nillil_dataout; + nil1il <= nil1ll; + nil1iO <= nil1lO; + nil1li <= wire_nil10l_dataout; + nil1ll <= n1i011O; + nil1lO <= n1i010i; + nil1Ol <= nil1OO; + nil1OO <= nl10Ol; + nili0i <= wire_niO1ii_dataout; + nili0l <= wire_niO1il_dataout; + nili0O <= wire_niO1iO_dataout; + nili1i <= wire_nillii_dataout; + nili1l <= wire_niO10l_dataout; + nili1O <= wire_niO10O_dataout; + niliii <= wire_niO1li_dataout; + niliil <= wire_niO1ll_dataout; + niliiO <= wire_niO1lO_dataout; + nilili <= nill0i; + nilill <= wire_niO1Ol_o; + nililO <= wire_niO1OO_o; + niliOi <= wire_niO01i_o; + niliOl <= wire_niO01l_o; + niliOO <= wire_niO01O_o; + nill0i <= nl1l1l; + nill0l <= niOlii; + nill1i <= wire_niO00i_o; + nill1l <= wire_niO00l_o; + nill1O <= wire_niO00O_o; + niOlii <= (rbitloc_rev_en AND bitloc_rev_en); + niOlil <= wire_niOO0l_o; + niOlli <= wire_niOO0O_o; + niOlll <= wire_niOOii_o; + niOllO <= wire_niOOil_o; + niOlOi <= wire_niOOiO_o; + niOlOl <= wire_niOOli_o; + niOlOO <= wire_niOOll_o; + niOO0i <= wire_nl11li_o; + niOO1i <= wire_niOOlO_o; + niOO1l <= wire_niOOOi_o; + niOO1O <= wire_niOOOl_o; + niOOOO <= wire_nl11ll_o; + nl010il <= nl01iOi; + nl010iO <= nl01iOl; + nl010li <= nl01iOO; + nl010ll <= nl01l1i; + nl010lO <= nl01l1l; + nl010Oi <= nl01l1O; + nl010Ol <= nl01l0i; + nl010OO <= nl01l0l; + nl0110i <= wire_nl1llll_o; + nl0110l <= wire_nl1lllO_o; + nl0110O <= wire_nl1llOi_o; + nl0111i <= wire_nl1llil_o; + nl0111l <= wire_nl1lliO_o; + nl0111O <= wire_nl1llli_o; + nl011ii <= wire_n1Ol10O_w_lg_dataout4507w(0); + nl011il <= wire_nl0l1OO_dataout; + nl011iO <= (wire_w_lg_disable_rx_disp1194w(0) AND n10l10l); + nl011li <= wire_n1O10lO_dataout; + nl011ll <= wire_nl0l0ii_dataout; + nl011lO <= wire_nl0l0il_dataout; + nl01i0i <= nl01liO; + nl01i0l <= nl01lli; + nl01i0O <= nl01lll; + nl01i1i <= nl01l0O; + nl01i1l <= nl01lii; + nl01i1O <= nl01lil; + nl01iii <= nl01llO; + nl01iil <= nl01lOi; + nl01iiO <= nl01lOl; + nl01ili <= nl01lOO; + nl01ill <= nl01O1i; + nl01ilO <= nl01O1l; + nl01iOi <= wire_nl01O0i_dataout; + nl01iOl <= wire_nl01O0l_dataout; + nl01iOO <= wire_nl01O0O_dataout; + nl01l0i <= wire_nl01Oli_dataout; + nl01l0l <= wire_nl01Oll_dataout; + nl01l0O <= wire_nl01OlO_dataout; + nl01l1i <= wire_nl01Oii_dataout; + nl01l1l <= wire_nl01Oil_dataout; + nl01l1O <= wire_nl01OiO_dataout; + nl01lii <= wire_nl01OOi_dataout; + nl01lil <= wire_nl01OOl_dataout; + nl01liO <= wire_nl01OOO_dataout; + nl01lli <= wire_nl0011i_dataout; + nl01lll <= wire_nl0011l_dataout; + nl01llO <= wire_nl0011O_dataout; + nl01lOi <= wire_nl0010i_dataout; + nl01lOl <= wire_nl0010l_dataout; + nl01lOO <= wire_nl0010O_dataout; + nl01O1i <= wire_nl001ii_dataout; + nl01O1l <= wire_nl001il_dataout; + nl01O1O <= wire_nll1lOl_dataout; + nl100l <= nl100O; + nl100O <= nl10ii; + nl10ii <= bitslip; + nl10Ol <= (NOT ((((NOT (nll1il XOR nl1iOi)) AND (NOT (nlli0l XOR nl1iOl))) AND (NOT (nlli0O XOR nl1iOO))) AND (NOT (nlliii XOR nl1l1i)))); + nl110i <= wire_nl11OO_o; + nl110l <= wire_nl101i_o; + nl110O <= wire_nl101l_o; + nl111i <= wire_nl11lO_o; + nl111l <= wire_nl11Oi_o; + nl111O <= wire_nl11Ol_o; + nl11ii <= wire_nl101O_o; + nl11il <= wire_nl100i_o; + nl11iO <= (nl100O AND wire_nl_w_lg_nl100l905w(0)); + nl1ill <= nl1ilO; + nl1ilO <= a1a2_size; + nl1l1l <= nl1ill; + nl1lii <= n1ii10O; + nl1liii <= wire_nl0l0lO_dataout; + nl1liil <= wire_n1O10lO_dataout; + nl1lOi <= nliOlO; + nl1Oiil <= (wire_nll1llO_w_lg_o7418w(0) AND (wire_w_lg_n111lOi7419w(0) AND wire_w_lg_n111O1i7420w(0))); + nl1OiiO <= wire_nl0l0ll_dataout; + nl1Oili <= nl1Ol1O; + nl1Oill <= nl1Ol0i; + nl1OilO <= nl1Ol0l; + nl1OiOi <= nl1Ol0O; + nl1OiOl <= nl1Olii; + nl1OiOO <= nl1Olil; + nl1Ol0i <= n1101il; + nl1Ol0l <= n11001l; + nl1Ol0O <= n1101Ol; + nl1Ol1i <= nl1OliO; + nl1Ol1l <= nl1Olli; + nl1Ol1O <= n1101ll; + nl1Olii <= n1100il; + nl1Olil <= n11000l; + nl1OliO <= n1100Ol; + nl1Olli <= n1100ll; + nl1Olll <= wire_nl1liiO_o; + nl1OllO <= wire_nl1lili_o; + nl1OlOi <= wire_nl1lill_o; + nl1OlOl <= wire_nl1lilO_o; + nl1OlOO <= wire_nl1liOi_o; + nl1OO0i <= wire_nl1ll1l_o; + nl1OO0l <= wire_nl1ll1O_o; + nl1OO0O <= wire_n1liO0O_w_lg_dataout4506w(0); + nl1OO1i <= wire_nl1liOl_o; + nl1OO1l <= wire_nl1liOO_o; + nl1OO1O <= wire_nl1ll1i_o; + nl1OOii <= wire_nl0l1ii_dataout; + nl1OOil <= (wire_w_lg_disable_rx_disp1194w(0) AND n10l10O); + nl1OOiO <= wire_n1l11lO_dataout; + nl1OOli <= wire_nl0l1lO_dataout; + nl1OOll <= wire_nl0l1Oi_dataout; + nl1OOlO <= wire_nl1ll0i_o; + nl1OOOi <= wire_nl1ll0l_o; + nl1OOOl <= wire_nl1ll0O_o; + nl1OOOO <= wire_nl1llii_o; + nliiOl <= nliOOi; + nliiOO <= nliOOl; + nlil0i <= nll11O; + nlil0l <= nll10i; + nlil0O <= nll10l; + nlil1i <= nliOOO; + nlil1l <= nll11i; + nlil1O <= nll11l; + nlilii <= nll1ii; + nlilll <= wire_nll1iO_dataout; + nlillO <= wire_nll1li_dataout; + nlilOi <= wire_nll1ll_dataout; + nlilOl <= wire_nll1lO_dataout; + nlilOO <= wire_nll1Oi_dataout; + nliO0i <= wire_nll01l_dataout; + nliO0l <= wire_nll01O_dataout; + nliO0O <= wire_nll00i_dataout; + nliO1i <= wire_nll1Ol_dataout; + nliO1l <= wire_nll1OO_dataout; + nliO1O <= wire_nll01i_dataout; + nliOii <= wire_nll00l_dataout; + nliOil <= wire_nll00O_dataout; + nliOiO <= wire_nll0ii_dataout; + nliOli <= wire_nll0il_dataout; + nliOll <= wire_nll0iO_dataout; + nliOlO <= wire_nll0li_dataout; + nliOOi <= wire_nll0ll_dataout; + nliOOl <= wire_nll0lO_dataout; + nliOOO <= wire_nll0Oi_dataout; + nll000i <= nll0iiO; + nll000l <= nll0ili; + nll000O <= nll0ill; + nll001i <= nll0i0O; + nll001l <= nll0iii; + nll001O <= nll0iil; + nll00ii <= nll0ilO; + nll00il <= nll0iOi; + nll00iO <= nll0iOl; + nll00li <= nll0iOO; + nll00ll <= nll0l1i; + nll00lO <= nll0l1l; + nll00Oi <= nll0l1O; + nll00Ol <= nll0l0i; + nll00OO <= nll0l0l; + nll01ll <= wire_nll1O1i_o; + nll01lO <= nll01Oi; + nll01Oi <= (signal_detect OR rforce_sig_det_pcs); + nll01Ol <= nll0i0i; + nll01OO <= nll0i0l; + nll0i0i <= nll0liO; + nll0i0l <= nll0lli; + nll0i0O <= nll0lll; + nll0i1i <= nll0l0O; + nll0i1l <= nll0lii; + nll0i1O <= nll0lil; + nll0iii <= nll0llO; + nll0iil <= nll0lOi; + nll0iiO <= nll0lOl; + nll0ili <= nll0lOO; + nll0ill <= nll0O1i; + nll0ilO <= nll0O1l; + nll0iOi <= nll0O1O; + nll0iOl <= nll0O0i; + nll0iOO <= nll0O0l; + nll0l0i <= nll0OiO; + nll0l0l <= nll0Oli; + nll0l0O <= nll0Oll; + nll0l1i <= nll0O0O; + nll0l1l <= nll0Oii; + nll0l1O <= nll0Oil; + nll0lii <= nll0OlO; + nll0lil <= nll0OOi; + nll0liO <= nll0OOl; + nll0lli <= nll0OOO; + nll0lll <= nlli11i; + nll0llO <= nlli11l; + nll0lOi <= nlli11O; + nll0lOl <= nlli10i; + nll0lOO <= nlli10l; + nll0O0i <= nlli1iO; + nll0O0l <= nlli1li; + nll0O0O <= nlli1ll; + nll0O1i <= nlli10O; + nll0O1l <= nlli1ii; + nll0O1O <= nlli1il; + nll0Oii <= nlli1lO; + nll0Oil <= nlli1Oi; + nll0OiO <= nlli1Ol; + nll0Oli <= nlli1OO; + nll0Oll <= nlli01i; + nll0OlO <= nlli01l; + nll0OOi <= nlli01O; + nll0OOl <= wire_nllii0O_dataout; + nll0OOO <= wire_nlliiii_dataout; + nll10i <= wire_nlli1l_dataout; + nll11i <= wire_nll0Ol_dataout; + nll11l <= wire_nll0OO_dataout; + nll11O <= wire_nlli1i_dataout; + nlli00i <= (nlli00O AND wire_nl_w_lg_nlli00l4491w(0)); + nlli00l <= nlli00O; + nlli00O <= nlli0ii; + nlli01i <= wire_nllilil_dataout; + nlli01l <= wire_nlliliO_dataout; + nlli01O <= wire_nllilli_dataout; + nlli0ii <= bitslip; + nlli0il <= nlli0iO; + nlli0iO <= (rbyte_rev_en AND byte_rev_en); + nlli0li <= nlli0ll; + nlli0ll <= (rbitloc_rev_en AND bitloc_rev_en); + nlli0lO <= nlli0Oi; + nlli0Oi <= rlv_en; + nlli0Ol <= (nllii0i AND wire_nl_w_lg_nllii1O4488w(0)); + nlli0OO <= wire_nllilOO_dataout; + nlli10i <= wire_nlliill_dataout; + nlli10l <= wire_nlliilO_dataout; + nlli10O <= wire_nlliiOi_dataout; + nlli11i <= wire_nlliiil_dataout; + nlli11l <= wire_nlliiiO_dataout; + nlli11O <= wire_nlliili_dataout; + nlli1ii <= wire_nlliiOl_dataout; + nlli1il <= wire_nlliiOO_dataout; + nlli1iO <= wire_nllil1i_dataout; + nlli1li <= wire_nllil1l_dataout; + nlli1ll <= wire_nllil1O_dataout; + nlli1lO <= wire_nllil0i_dataout; + nlli1Oi <= wire_nllil0l_dataout; + nlli1Ol <= wire_nllil0O_dataout; + nlli1OO <= wire_nllilii_dataout; + nllii0i <= nllii0l; + nllii0l <= encdt; + nllii1i <= nllii1l; + nllii1l <= nllii1O; + nllii1O <= nllii0i; + nllll1i <= (((wire_nllO0ii_dataout OR wire_nllO00l_dataout) OR wire_nllO00i_dataout) OR wire_nllO01l_dataout); + nlllOl <= wire_nlll1l_o; + nlllOO <= wire_nlll1O_o; + nlO <= wire_ni_dataout; + nlO000i <= wire_nlllliO_o; + nlO000l <= wire_nllllli_o; + nlO000O <= wire_nllllll_o; + nlO001i <= wire_nllll0O_o; + nlO001l <= wire_nllllii_o; + nlO001O <= wire_nllllil_o; + nlO00ii <= wire_nllllOl_o; + nlO00il <= wire_nllllOO_o; + nlO00iO <= wire_nlllO1i_o; + nlO00li <= wire_nlllO1l_o; + nlO00ll <= wire_nlllO1O_o; + nlO00lO <= wire_nlllO0i_o; + nlO00Oi <= wire_nlllO0l_o; + nlO00Ol <= wire_nlllO0O_o; + nlO00OO <= wire_nlllOii_o; + nlO010i <= (pipe_loose_sync AND (rforce_sig_det_pcs OR (signal_detect OR lpbk_en))); + nlO010l <= nlO010i; + nlO011i <= (((wire_nllO00O_dataout OR wire_nllO00l_dataout) OR wire_nllO01O_dataout) OR wire_nllO01l_dataout); + nlO011l <= (NOT ((wire_nllO0il_w_lg_dataout3407w(0) OR wire_nllO00O_dataout) OR wire_nllO00l_dataout)); + nlO011O <= wire_nllO01i_dataout; + nlO01ii <= wire_nllO1iO_o; + nlO01il <= wire_nlllill_dataout; + nlO01iO <= wire_nlllilO_dataout; + nlO01li <= wire_nllliOi_dataout; + nlO01ll <= wire_nllliOl_dataout; + nlO01lO <= wire_nllll1l_o; + nlO01Oi <= wire_nllll1O_o; + nlO01Ol <= wire_nllll0i_o; + nlO01OO <= wire_nllll0l_o; + nlO0i0i <= wire_nlllOOO_o; + nlO0i0l <= wire_nllO11i_o; + nlO0i0O <= wire_nllO11l_o; + nlO0i1i <= wire_nlllOil_o; + nlO0i1l <= wire_nlllOOi_o; + nlO0i1O <= wire_nlllOOl_o; + nlO0iii <= wire_nllO11O_o; + nlO0iil <= wire_nllO10i_o; + nlO0iiO <= wire_nllO10l_o; + nlO0ili <= wire_nllO10O_o; + nlO0ill <= wire_nllO1ii_o; + nlO0ilO <= nlO0l1i; + nlO0l1i <= prbs_en; + nlO0l1l <= nlO0l1O; + nlO0l1O <= encdt; + nlOi0ll <= n1i0l0i; + nlOi0lO <= wire_nlOi0iO_o; + nlOi0Oi <= n1i0l0O; + nlOi0Ol <= wire_nlOi00i_o; + nlOi0OO <= n1i0lil; + nlOii0i <= n1i0llO; + nlOii0l <= wire_nlOi10i_o; + nlOii0O <= n1i0O1i; + nlOii1i <= wire_nlOi1Ol_o; + nlOii1l <= n1i0lli; + nlOii1O <= wire_nlOi1iO_o; + nlOiiii <= wire_nlO0OOl_o; + nlOiiil <= n1i0Oii; + nlOiiiO <= wire_nlO0OiO_o; + nlOiili <= n1ii11l; + nlOiill <= wire_nlO0O0i_o; + nlOiilO <= n1ii11l; + nlOilOl <= n1i0Oii; + nlOilOO <= n1i0O1i; + nlOiO0i <= n1i0l0O; + nlOiO0l <= n1i0l0i; + nlOiO1i <= n1i0llO; + nlOiO1l <= n1i0lli; + nlOiO1O <= n1i0lil; + nO <= ni0iO; + END IF; + END PROCESS; + wire_nl_CLRN <= ((n1iil0O2 XOR n1iil0O1) AND wire_ni0lO_w_lg_dataout2w(0)); + wire_nl_w16422w(0) <= wire_nl_w_lg_w_lg_w_lg_w16418w16419w16420w16421w(0) AND nlOOOOll; + wire_nl_w_lg_w_lg_w_lg_w16418w16419w16420w16421w(0) <= wire_nl_w_lg_w_lg_w16418w16419w16420w(0) AND nlOOOOlO; + wire_nl_w_lg_w_lg_w16418w16419w16420w(0) <= wire_nl_w_lg_w16418w16419w(0) AND nlOOOOOi; + wire_nl_w_lg_w16418w16419w(0) <= wire_nl_w16418w(0) AND nlOOOOOl; + wire_nl_w16418w(0) <= wire_nl_w_lg_w_lg_w_lg_w16414w16415w16416w16417w(0) AND nlOOOOOO; + wire_nl_w_lg_w_lg_w_lg_w16414w16415w16416w16417w(0) <= wire_nl_w_lg_w_lg_w16414w16415w16416w(0) AND n11111i; + wire_nl_w_lg_w_lg_w16414w16415w16416w(0) <= wire_nl_w_lg_w16414w16415w(0) AND n11111l; + wire_nl_w_lg_w16414w16415w(0) <= wire_nl_w16414w(0) AND n11111O; + wire_nl_w_lg_w_lg_w_lg_w2928w2929w2930w2931w(0) <= wire_nl_w_lg_w_lg_w2928w2929w2930w(0) AND n1i1ili; + wire_nl_w16414w(0) <= wire_nl_w_lg_w_lg_w_lg_w16410w16411w16412w16413w(0) AND n11110i; + wire_nl_w_lg_w_lg_w2928w2929w2930w(0) <= wire_nl_w_lg_w2928w2929w(0) AND n1i1ill; + wire_nl_w_lg_w_lg_w_lg_w16410w16411w16412w16413w(0) <= wire_nl_w_lg_w_lg_w16410w16411w16412w(0) AND n11110l; + wire_nl_w_lg_w2928w2929w(0) <= wire_nl_w2928w(0) AND n1i1ilO; + wire_nl_w_lg_w_lg_w16410w16411w16412w(0) <= wire_nl_w_lg_w16410w16411w(0) AND n11110O; + wire_nl_w2928w(0) <= wire_nl_w_lg_w_lg_w_lg_w_lg_nl1lOi2612w2925w2926w2927w(0) AND n1i1iOi; + wire_nl_w_lg_w16410w16411w(0) <= wire_nl_w16410w(0) AND n1111ii; + wire_nl_w_lg_w_lg_w_lg_w_lg_nl1lOi2612w2925w2926w2927w(0) <= wire_nl_w_lg_w_lg_w_lg_nl1lOi2612w2925w2926w(0) AND n1i1iOl; + wire_nl_w16410w(0) <= wire_nl_w_lg_w_lg_w_lg_nll0OOl16010w16408w16409w(0) AND n1111il; + wire_nl_w_lg_w_lg_w_lg_nlil0l2177w2182w2187w(0) <= wire_nl_w_lg_w_lg_nlil0l2177w2182w(0) AND nlil1l; + wire_nl_w_lg_w_lg_w_lg_nlilii2175w2180w2185w(0) <= wire_nl_w_lg_w_lg_nlilii2175w2180w(0) AND nlil0i; + wire_nl_w_lg_w_lg_w_lg_nlli01O14427w14432w14437w(0) <= wire_nl_w_lg_w_lg_nlli01O14427w14432w(0) AND nlli1OO; + wire_nl_w_lg_w_lg_w_lg_nlli1Ol14429w14434w14439w(0) <= wire_nl_w_lg_w_lg_nlli1Ol14429w14434w(0) AND nlli1ll; + wire_nl_w_lg_w_lg_w_lg_nl1lOi2612w2925w2926w(0) <= wire_nl_w_lg_w_lg_nl1lOi2612w2925w(0) AND n1i1iOO; + wire_nl_w_lg_w_lg_w_lg_nll0OOl16010w16408w16409w(0) <= wire_nl_w_lg_w_lg_nll0OOl16010w16408w(0) AND n1111iO; + wire_nl_w_lg_w_lg_nlil0l2177w2182w(0) <= wire_nl_w_lg_nlil0l2177w(0) AND nlil1O; + wire_nl_w_lg_w_lg_nlilii2175w2180w(0) <= wire_nl_w_lg_nlilii2175w(0) AND nlil0l; + wire_nl_w_lg_w_lg_nlli01O14427w14432w(0) <= wire_nl_w_lg_nlli01O14427w(0) AND nlli01i; + wire_nl_w_lg_w_lg_nlli1Ol14429w14434w(0) <= wire_nl_w_lg_nlli1Ol14429w(0) AND nlli1lO; + wire_nl_w_lg_w_lg_nlOiill322w325w(0) <= wire_nl_w_lg_nlOiill322w(0) AND wire_n1i0Oli40_w_lg_q324w(0); + wire_nl_w_lg_w_lg_nl1lOi2612w2925w(0) <= wire_nl_w_lg_nl1lOi2612w(0) AND n1i1l0O; + wire_nl_w_lg_w_lg_nll0OOl16010w16408w(0) <= wire_nl_w_lg_nll0OOl16010w(0) AND n11100i; + wire_nl_w_lg_niii0i1208w(0) <= niii0i AND wire_w_lg_n1i001l1207w(0); + wire_nl_w_lg_nl1ill342w(0) <= nl1ill AND wire_w_lg_w_lg_n1i0O0O338w341w(0); + wire_nl_w_lg_nl1ill389w(0) <= nl1ill AND wire_w_lg_n1i0l0l388w(0); + wire_nl_w_lg_nl1ill397w(0) <= nl1ill AND wire_w_lg_n1i0l1O396w(0); + wire_nl_w_lg_nl1ill381w(0) <= nl1ill AND wire_w_lg_n1i0lii380w(0); + wire_nl_w_lg_nl1ill373w(0) <= nl1ill AND wire_w_lg_n1i0liO372w(0); + wire_nl_w_lg_nl1ill365w(0) <= nl1ill AND wire_w_lg_n1i0lll364w(0); + wire_nl_w_lg_nl1ill357w(0) <= nl1ill AND wire_w_lg_n1i0lOO356w(0); + wire_nl_w_lg_nl1ill327w(0) <= nl1ill AND wire_w_lg_n1ii11i326w(0); + wire_nl_w_lg_nl1liil17114w(0) <= nl1liil AND wire_w_lg_nlOO1lil17113w(0); + wire_nl_w_lg_nl1lOi2945w(0) <= nl1lOi AND wire_w_lg_n1i100O2508w(0); + wire_nl_w_lg_nlil0l2177w(0) <= nlil0l AND nlil0i; + wire_nl_w_lg_nlilii2175w(0) <= nlilii AND nlil0O; + wire_nl_w_lg_nll0OOl16448w(0) <= nll0OOl AND wire_w_lg_nlOOO0iO15408w(0); + wire_nl_w_lg_nlli01O14427w(0) <= nlli01O AND nlli01l; + wire_nl_w_lg_nlli1Ol14429w(0) <= nlli1Ol AND nlli1Oi; + wire_nl_w_lg_nlO0l1l232w(0) <= nlO0l1l AND wire_w_lg_n1ii00l231w(0); + wire_nl_w_lg_nlOi0lO395w(0) <= nlOi0lO AND wire_nl_w_lg_nlOi0ll394w(0); + wire_nl_w_lg_nlOi0Ol387w(0) <= nlOi0Ol AND wire_nl_w_lg_nlOi0Oi386w(0); + wire_nl_w_lg_nlOii0l363w(0) <= nlOii0l AND wire_nl_w_lg_nlOii0i362w(0); + wire_nl_w_lg_nlOii1i379w(0) <= nlOii1i AND wire_nl_w_lg_nlOi0OO378w(0); + wire_nl_w_lg_nlOii1O371w(0) <= nlOii1O AND wire_nl_w_lg_nlOii1l370w(0); + wire_nl_w_lg_nlOiiii355w(0) <= nlOiiii AND wire_nl_w_lg_nlOii0O354w(0); + wire_nl_w_lg_nlOiiiO337w(0) <= nlOiiiO AND wire_nl_w_lg_nlOiiil336w(0); + wire_nl_w_lg_nlOiill322w(0) <= nlOiill AND wire_nl_w_lg_nlOiili321w(0); + wire_nl_w_lg_w_lg_w_lg_w_lg_nlilii2087w2094w2101w2102w(0) <= NOT wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0); + wire_nl_w14161w(0) <= NOT wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0); + wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2095w(0) <= NOT wire_nl_w_lg_w_lg_nlilii2087w2094w(0); + wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14154w(0) <= NOT wire_nl_w_lg_w_lg_nlli01O14146w14153w(0); + wire_nl_w_lg_w_lg_nlilii2087w2088w(0) <= NOT wire_nl_w_lg_nlilii2087w(0); + wire_nl_w_lg_w_lg_nlli01O14146w14147w(0) <= NOT wire_nl_w_lg_nlli01O14146w(0); + wire_nl_w_lg_n0101il16151w(0) <= NOT n0101il; + wire_nl_w_lg_n010Ol2709w(0) <= NOT n010Ol; + wire_nl_w_lg_n011l1l16150w(0) <= NOT n011l1l; + wire_nl_w_lg_n011l1O16156w(0) <= NOT n011l1O; + wire_nl_w_lg_n1OiOi2540w(0) <= NOT n1OiOi; + wire_nl_w_lg_n1OOOl2708w(0) <= NOT n1OOOl; + wire_nl_w_lg_n1OOOO2714w(0) <= NOT n1OOOO; + wire_nl_w_lg_niii0i1195w(0) <= NOT niii0i; + wire_nl_w_lg_niii0l3438w(0) <= NOT niii0l; + wire_nl_w_lg_niiill3373w(0) <= NOT niiill; + wire_nl_w_lg_nl100l905w(0) <= NOT nl100l; + wire_nl_w_lg_nl1ill312w(0) <= NOT nl1ill; + wire_nl_w_lg_nl1l1l1933w(0) <= NOT nl1l1l; + wire_nl_w_lg_nl1liil17102w(0) <= NOT nl1liil; + wire_nl_w_lg_nl1lOi2612w(0) <= NOT nl1lOi; + wire_nl_w_lg_nliiOl2604w(0) <= NOT nliiOl; + wire_nl_w_lg_nliiOO2596w(0) <= NOT nliiOO; + wire_nl_w_lg_nlil0i2588w(0) <= NOT nlil0i; + wire_nl_w_lg_nlil0l2618w(0) <= NOT nlil0l; + wire_nl_w_lg_nlil0O2616w(0) <= NOT nlil0O; + wire_nl_w_lg_nlil1i2594w(0) <= NOT nlil1i; + wire_nl_w_lg_nlil1l2592w(0) <= NOT nlil1l; + wire_nl_w_lg_nlil1O2590w(0) <= NOT nlil1O; + wire_nl_w_lg_nlilii2911w(0) <= NOT nlilii; + wire_nl_w_lg_nll01ll7899w(0) <= NOT nll01ll; + wire_nl_w_lg_nll01lO4501w(0) <= NOT nll01lO; + wire_nl_w_lg_nll0OOl16010w(0) <= NOT nll0OOl; + wire_nl_w_lg_nll0OOO15999w(0) <= NOT nll0OOO; + wire_nl_w_lg_nlli00l4491w(0) <= NOT nlli00l; + wire_nl_w_lg_nlli01i16015w(0) <= NOT nlli01i; + wire_nl_w_lg_nlli01l16013w(0) <= NOT nlli01l; + wire_nl_w_lg_nlli01O16384w(0) <= NOT nlli01O; + wire_nl_w_lg_nlli0lO15746w(0) <= NOT nlli0lO; + wire_nl_w_lg_nlli0OO4494w(0) <= NOT nlli0OO; + wire_nl_w_lg_nlli10i15955w(0) <= NOT nlli10i; + wire_nl_w_lg_nlli10l15944w(0) <= NOT nlli10l; + wire_nl_w_lg_nlli10O15942w(0) <= NOT nlli10O; + wire_nl_w_lg_nlli11i15988w(0) <= NOT nlli11i; + wire_nl_w_lg_nlli11l15977w(0) <= NOT nlli11l; + wire_nl_w_lg_nlli11O15966w(0) <= NOT nlli11O; + wire_nl_w_lg_nlli1ii15940w(0) <= NOT nlli1ii; + wire_nl_w_lg_nlli1il15938w(0) <= NOT nlli1il; + wire_nl_w_lg_nlli1iO15936w(0) <= NOT nlli1iO; + wire_nl_w_lg_nlli1li15934w(0) <= NOT nlli1li; + wire_nl_w_lg_nlli1ll15932w(0) <= NOT nlli1ll; + wire_nl_w_lg_nlli1lO15930w(0) <= NOT nlli1lO; + wire_nl_w_lg_nlli1Oi15928w(0) <= NOT nlli1Oi; + wire_nl_w_lg_nlli1Ol16019w(0) <= NOT nlli1Ol; + wire_nl_w_lg_nlli1OO16017w(0) <= NOT nlli1OO; + wire_nl_w_lg_nllii0i4486w(0) <= NOT nllii0i; + wire_nl_w_lg_nllii1O4488w(0) <= NOT nllii1O; + wire_nl_w_lg_nlO00il4415w(0) <= NOT nlO00il; + wire_nl_w_lg_nlO00iO4413w(0) <= NOT nlO00iO; + wire_nl_w_lg_nlO00li4411w(0) <= NOT nlO00li; + wire_nl_w_lg_nlO00ll4409w(0) <= NOT nlO00ll; + wire_nl_w_lg_nlO00lO4407w(0) <= NOT nlO00lO; + wire_nl_w_lg_nlO00Oi4405w(0) <= NOT nlO00Oi; + wire_nl_w_lg_nlO00Ol4403w(0) <= NOT nlO00Ol; + wire_nl_w_lg_nlO00OO4401w(0) <= NOT nlO00OO; + wire_nl_w_lg_nlO010l3809w(0) <= NOT nlO010l; + wire_nl_w_lg_nlO0i1i4400w(0) <= NOT nlO0i1i; + wire_nl_w_lg_nlO0l1l246w(0) <= NOT nlO0l1l; + wire_nl_w_lg_nlOi0ll394w(0) <= NOT nlOi0ll; + wire_nl_w_lg_nlOi0Oi386w(0) <= NOT nlOi0Oi; + wire_nl_w_lg_nlOi0OO378w(0) <= NOT nlOi0OO; + wire_nl_w_lg_nlOii0i362w(0) <= NOT nlOii0i; + wire_nl_w_lg_nlOii0O354w(0) <= NOT nlOii0O; + wire_nl_w_lg_nlOii1l370w(0) <= NOT nlOii1l; + wire_nl_w_lg_nlOiiil336w(0) <= NOT nlOiiil; + wire_nl_w_lg_nlOiili321w(0) <= NOT nlOiili; + wire_nl_w_lg_w_lg_w_lg_nlilii2087w2094w2101w(0) <= wire_nl_w_lg_w_lg_nlilii2087w2094w(0) OR nlil0i; + wire_nl_w_lg_w_lg_w_lg_nlli01O14146w14153w14160w(0) <= wire_nl_w_lg_w_lg_nlli01O14146w14153w(0) OR nlli1OO; + wire_nl_w_lg_w_lg_nlilii2087w2094w(0) <= wire_nl_w_lg_nlilii2087w(0) OR nlil0l; + wire_nl_w_lg_w_lg_nlli01O14146w14153w(0) <= wire_nl_w_lg_nlli01O14146w(0) OR nlli01i; + wire_nl_w_lg_nlilii2087w(0) <= nlilii OR nlil0O; + wire_nl_w_lg_nlli01O14146w(0) <= nlli01O OR nlli01l; + PROCESS (clk, wire_nl10lO_CLRN) + BEGIN + IF (wire_nl10lO_CLRN = '0') THEN + nl10il <= '0'; + nl10li <= '0'; + nl10ll <= '0'; + nl10Oi <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + IF (nl11iO = '1') THEN + nl10il <= wire_nl10OO_dataout; + nl10li <= wire_nl1i1i_dataout; + nl10ll <= wire_nl1i1l_dataout; + nl10Oi <= wire_nl1i1O_dataout; + END IF; + END IF; + END PROCESS; + wire_nl10lO_CLRN <= ((n1i00OO50 XOR n1i00OO49) AND wire_ni0lO_w_lg_dataout2w(0)); + wire_nl10lO_w_lg_nl10il1929w(0) <= NOT nl10il; + wire_nl10lO_w_lg_nl10li1927w(0) <= NOT nl10li; + wire_nl10lO_w_lg_nl10ll1925w(0) <= NOT nl10ll; + wire_nl10lO_w_lg_nl10Oi1924w(0) <= NOT nl10Oi; + PROCESS (clk, wire_ni0lO_dataout) + BEGIN + IF (wire_ni0lO_dataout = '1') THEN + nl1lil <= '1'; + nl1liO <= '1'; + nl1lli <= '1'; + nl1llO <= '1'; + ELSIF (clk = '1' AND clk'event) THEN + IF (n1ii10O = '1') THEN + nl1lil <= wire_w_lg_n1ii1OO229w(0); + nl1liO <= n1ii01i; + nl1lli <= n1ii01l; + nl1llO <= n1ii01O; + END IF; + END IF; + if (now = 0 ns) then + nl1lil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1liO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1lli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1llO <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk, wire_nll10O_PRN, wire_ni0lO_dataout) + BEGIN + IF (wire_nll10O_PRN = '0') THEN + nlilil <= '1'; + nliliO <= '1'; + nlilli <= '1'; + nll10l <= '1'; + nll1ii <= '1'; + ELSIF (wire_ni0lO_dataout = '1') THEN + nlilil <= '0'; + nliliO <= '0'; + nlilli <= '0'; + nll10l <= '0'; + nll1ii <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + IF (wire_w_pmadwidth_range175w(0) = '1') THEN + nlilil <= nliO1O; + nliliO <= nliO0i; + nlilli <= nliO0l; + nll10l <= wire_nlli1O_dataout; + nll1ii <= wire_nlli0i_dataout; + END IF; + END IF; + END PROCESS; + wire_nll10O_ENA <= pmadwidth(0); + wire_nll10O_PRN <= (n1ii10l34 XOR n1ii10l33); + PROCESS (clk, wire_ni0lO_dataout, wire_nllO1i_CLRN) + BEGIN + IF (wire_ni0lO_dataout = '1') THEN + n1O01l <= '1'; + n1OO01O <= '1'; + nil1Oi <= '1'; + nl0100i <= '1'; + nl0100l <= '1'; + nl0100O <= '1'; + nl0101i <= '1'; + nl0101l <= '1'; + nl0101O <= '1'; + nl010ii <= '1'; + nl011Oi <= '1'; + nl011Ol <= '1'; + nl011OO <= '1'; + nl1iOi <= '1'; + nl1iOl <= '1'; + nl1iOO <= '1'; + nl1l1i <= '1'; + nll01li <= '1'; + nll1il <= '1'; + nlli0l <= '1'; + nlli0O <= '1'; + nlliii <= '1'; + nllO1l <= '1'; + nlO010O <= '1'; + ELSIF (wire_nllO1i_CLRN = '0') THEN + n1O01l <= '0'; + n1OO01O <= '0'; + nil1Oi <= '0'; + nl0100i <= '0'; + nl0100l <= '0'; + nl0100O <= '0'; + nl0101i <= '0'; + nl0101l <= '0'; + nl0101O <= '0'; + nl010ii <= '0'; + nl011Oi <= '0'; + nl011Ol <= '0'; + nl011OO <= '0'; + nl1iOi <= '0'; + nl1iOl <= '0'; + nl1iOO <= '0'; + nl1l1i <= '0'; + nll01li <= '0'; + nll1il <= '0'; + nlli0l <= '0'; + nlli0O <= '0'; + nlliii <= '0'; + nllO1l <= '0'; + nlO010O <= '0'; + ELSIF (clk = '1' AND clk'event) THEN + n1O01l <= wire_nl_w_lg_n1OiOi2540w(0); + n1OO01O <= wire_nl_w_lg_nlli0lO15746w(0); + nil1Oi <= (n1ii0iO OR wire_n1l1Ol_w_lg_dataout173w(0)); + nl0100i <= wire_nl0i1OO_dataout; + nl0100l <= wire_nl0i01i_dataout; + nl0100O <= wire_nl0i01l_dataout; + nl0101i <= nl0100O; + nl0101l <= nl010ii; + nl0101O <= wire_nl0i1Ol_dataout; + nl010ii <= wire_nl0i01O_dataout; + nl011Oi <= nl0101O; + nl011Ol <= nl0100i; + nl011OO <= nl0100l; + nl1iOi <= wire_nl1l1O_dataout; + nl1iOl <= wire_nl1l0i_dataout; + nl1iOO <= wire_nl1l0l_dataout; + nl1l1i <= wire_nl1l0O_dataout; + nll01li <= wire_nll1lOO_o; + nll1il <= wire_nlliil_dataout; + nlli0l <= wire_nlliiO_dataout; + nlli0O <= wire_nllili_dataout; + nlliii <= wire_nllill_dataout; + nllO1l <= wire_nlll0i_o; + nlO010O <= wire_nlllOli_o; + END IF; + if (now = 0 ns) then + n1O01l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1OO01O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0100i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0100l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0100O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0101i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0101l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0101O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl010ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl011Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl011Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl011OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1iOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1iOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1iOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1l1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll01li <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlli0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllO1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO010O <= '1' after 1 ps; + end if; + END PROCESS; + wire_nllO1i_CLRN <= (n1ii00O20 XOR n1ii00O19); + wire_nllO1i_w_lg_nil1Oi3372w(0) <= NOT nil1Oi; + wire_nllO1i_w_lg_nll01li7901w(0) <= NOT nll01li; + wire_n00i_dataout <= (NOT pudi(15)) WHEN nO = '1' ELSE pudi(15); + wire_n00l_dataout <= (NOT pudi(16)) WHEN nO = '1' ELSE pudi(16); + wire_n00O_dataout <= (NOT pudi(17)) WHEN nO = '1' ELSE pudi(17); + wire_n0100i_dataout <= (((wire_w_lg_n10Ol0l2449w(0) OR wire_w_lg_n10Ol0i2451w(0)) OR wire_w_lg_n10Ol1O2459w(0)) OR wire_w_lg_n10Ol1l2515w(0)) AND n1OiOi; + wire_n0100iO_dataout <= (wire_w_lg_nlOOil1l15645w(0) OR (wire_w_lg_nlOOil1i15646w(0) OR (wire_w_lg_nlOOiiOO15647w(0) OR (wire_w_lg_nlOOiiOl15648w(0) OR (wire_w_lg_nlOOiiOi15649w(0) OR (wire_w_lg_nlOOiilO15650w(0) OR (wire_w_lg_nlOOiill15651w(0) OR (wire_w_lg_nlOOiili15652w(0) OR (wire_w_lg_nlOOiiiO15653w(0) OR (wire_w_lg_nlOOiiil15654w(0) OR (wire_w_lg_nlOOiiii15655w(0) OR (wire_w_lg_nlOOii0O15656w(0) OR (wire_w_lg_nlOOii0l15657w(0) OR (wire_w_lg_nlOOii0i15658w(0) OR (wire_w_lg_nlOOii1O15659w(0) OR wire_w_lg_nlOOii1l15660w(0)))))))))))))))) AND nlli0lO; + wire_n0100l_dataout <= (wire_w_lg_n1i11ii2507w(0) OR (NOT ((wire_w_lg_n1i100O2508w(0) OR n1i11il) OR n1i11ii))) AND n1OiOi; + wire_n0100li_dataout <= (wire_w_lg_w_pmadwidth_range175w15643w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n11100i14248w(0))) AND nlli0lO; + wire_n0100ll_dataout <= nlOOl00O AND nlli0lO; + wire_n0100lO_dataout <= nlOOl0il AND nlli0lO; + wire_n0100O_dataout <= n011iO AND n1OiOi; + wire_n0100Oi_dataout <= nlOOl0iO AND nlli0lO; + wire_n0100Ol_dataout <= nlOOl0li AND nlli0lO; + wire_n0100OO_dataout <= nlOOl0ll AND nlli0lO; + wire_n01010i_dataout <= nlOOiOOl AND nlli0lO; + wire_n01010l_dataout <= nlOOiOOO AND nlli0lO; + wire_n01010O_dataout <= nlOOl11i AND nlli0lO; + wire_n01011i_dataout <= n011O1l AND nlli0lO; + wire_n01011l_dataout <= n011O1O AND nlli0lO; + wire_n01011O_dataout <= nlOOiOlO AND nlli0lO; + wire_n0101i_dataout <= (wire_w_lg_w_pmadwidth_range175w2517w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w2208w(0)) AND n1OiOi; + wire_n0101ii_dataout <= nlOOl11l AND nlli0lO; + wire_n0101l_dataout <= n10OilO AND n1OiOi; + wire_n0101O_dataout <= n10OiOl AND n1OiOi; + wire_n010i0i_dataout <= n0100ii AND nlli0lO; + wire_n010i0l_dataout <= n0100il AND nlli0lO; + wire_n010i0O_dataout <= nlOOliOO AND nlli0lO; + wire_n010i1i_dataout <= n01000i AND nlli0lO; + wire_n010i1l_dataout <= n01000l AND nlli0lO; + wire_n010i1O_dataout <= n01000O AND nlli0lO; + wire_n010ii_dataout <= n011li AND n1OiOi; + wire_n010iii_dataout <= nlOOll1l AND nlli0lO; + wire_n010iil_dataout <= nlOOll1O AND nlli0lO; + wire_n010iiO_dataout <= nlOOll0i AND nlli0lO; + wire_n010il_dataout <= n011ll AND n1OiOi; + wire_n010ili_dataout <= nlOOll0l AND nlli0lO; + wire_n010iO_dataout <= n011lO AND n1OiOi; + wire_n010li_dataout <= n10Olii AND n1OiOi; + wire_n010ll_dataout <= n10OliO AND n1OiOi; + wire_n010lO_dataout <= (((wire_w_lg_n10OlOO2394w(0) OR wire_w_lg_n10OlOl2396w(0)) OR wire_w_lg_n10OlOi2404w(0)) OR wire_w_lg_n10OllO2505w(0)) AND n1OiOi; + wire_n010Oi_dataout <= (wire_w_lg_n1i101i2497w(0) OR (NOT ((wire_w_lg_n1i100l2498w(0) OR n1i101O) OR n1i101i))) AND n1OiOi; + wire_n0110il_dataout <= nlOOi1Oi WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE nlOOi1Ol; + wire_n0110il_w_lg_dataout15757w(0) <= NOT wire_n0110il_dataout; + wire_n0110iO_dataout <= wire_n011ill_dataout AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_n0110iO_w_lg_dataout16493w(0) <= NOT wire_n0110iO_dataout; + wire_n0110li_dataout <= wire_n011ilO_dataout AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_n0110li_w_lg_dataout16491w(0) <= NOT wire_n0110li_dataout; + wire_n0110ll_dataout <= wire_n011ill_dataout WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n011i1O_dataout; + wire_n0110lO_dataout <= wire_n011ilO_dataout WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n011i0i_dataout; + wire_n0110lO_w_lg_dataout16488w(0) <= NOT wire_n0110lO_dataout; + wire_n0110Oi_dataout <= wire_n011iOi_dataout WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n011i0l_dataout; + wire_n0110Oi_w_lg_dataout16486w(0) <= NOT wire_n0110Oi_dataout; + wire_n0110Ol_dataout <= wire_n011iOl_dataout WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n011i0O_dataout; + wire_n0110Ol_w_lg_dataout16484w(0) <= NOT wire_n0110Ol_dataout; + wire_n0110OO_dataout <= wire_n011iOO_dataout WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n011iii_dataout; + wire_n0110OO_w_lg_dataout16482w(0) <= NOT wire_n0110OO_dataout; + wire_n011i0i_dataout <= wire_n011ili_o(1) AND NOT(nlOOi1OO); + wire_n011i0l_dataout <= wire_n011ili_o(2) AND NOT(nlOOi1OO); + wire_n011i0O_dataout <= wire_n011ili_o(3) AND NOT(nlOOi1OO); + wire_n011i1i_dataout <= wire_n011l1i_dataout WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n011iil_dataout; + wire_n011i1i_w_lg_dataout16480w(0) <= NOT wire_n011i1i_dataout; + wire_n011i1l_dataout <= nlOOi1OO WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n011iiO_dataout; + wire_n011i1l_w_lg_w_lg_w_lg_w16485w16487w16489w16490w(0) <= wire_n011i1l_w_lg_w_lg_w16485w16487w16489w(0) AND wire_n0110ll_dataout; + wire_n011i1l_w_lg_w_lg_w16485w16487w16489w(0) <= wire_n011i1l_w_lg_w16485w16487w(0) AND wire_n0110lO_w_lg_dataout16488w(0); + wire_n011i1l_w_lg_w16485w16487w(0) <= wire_n011i1l_w16485w(0) AND wire_n0110Oi_w_lg_dataout16486w(0); + wire_n011i1l_w16485w(0) <= wire_n011i1l_w_lg_w_lg_w_lg_dataout16479w16481w16483w(0) AND wire_n0110Ol_w_lg_dataout16484w(0); + wire_n011i1l_w_lg_w_lg_w_lg_dataout16479w16481w16483w(0) <= wire_n011i1l_w_lg_w_lg_dataout16479w16481w(0) AND wire_n0110OO_w_lg_dataout16482w(0); + wire_n011i1l_w_lg_w_lg_dataout16479w16481w(0) <= wire_n011i1l_w_lg_dataout16479w(0) AND wire_n011i1i_w_lg_dataout16480w(0); + wire_n011i1l_w_lg_dataout16479w(0) <= NOT wire_n011i1l_dataout; + wire_n011i1O_dataout <= wire_n011ili_o(0) AND NOT(nlOOi1OO); + wire_n011iii_dataout <= wire_n011ili_o(4) OR nlOOi1OO; + wire_n011iil_dataout <= wire_n011ili_o(5) AND NOT(nlOOi1OO); + wire_n011iiO_dataout <= wire_n011ili_o(6) OR nlOOi1OO; + wire_n011ill_dataout <= max_rlv_sel(0) AND NOT(nlOOi1OO); + wire_n011ilO_dataout <= max_rlv_sel(1) AND NOT(nlOOi1OO); + wire_n011iOi_dataout <= max_rlv_sel(2) AND NOT(nlOOi1OO); + wire_n011iOl_dataout <= max_rlv_sel(3) AND NOT(nlOOi1OO); + wire_n011iOO_dataout <= max_rlv_sel(4) AND NOT(nlOOi1OO); + wire_n011l1i_dataout <= max_rlv_sel(5) AND NOT(nlOOi1OO); + wire_n011O0l_dataout <= (wire_w_lg_nlOOii1i15679w(0) OR (wire_w_lg_nlOOi0OO15680w(0) OR (wire_w_lg_nlOOi0Ol15681w(0) OR (wire_w_lg_nlOOi0Oi15682w(0) OR (wire_w_lg_nlOOi0lO15683w(0) OR (wire_w_lg_nlOOi0ll15684w(0) OR (wire_w_lg_nlOOi0li15685w(0) OR (wire_w_lg_nlOOi0iO15686w(0) OR (wire_w_lg_nlOOi0il15687w(0) OR (wire_w_lg_nlOOi0ii15688w(0) OR (wire_w_lg_nlOOi00O15689w(0) OR (wire_w_lg_nlOOi00l15690w(0) OR (wire_w_lg_nlOOi00i15691w(0) OR (wire_w_lg_nlOOi01O15692w(0) OR (wire_w_lg_nlOOi01l15693w(0) OR wire_w_lg_nlOOi01i15694w(0)))))))))))))))) AND nlli0lO; + wire_n011O0O_dataout <= (nlOOOO1O OR nlOOOO1l) AND nlli0lO; + wire_n011Oii_dataout <= (wire_w_lg_w_pmadwidth_range175w15676w(0) OR wire_w_lg_w_lg_w_pmadwidth_range175w219w14500w(0)) AND nlli0lO; + wire_n011Oil_dataout <= nlOOil1O AND nlli0lO; + wire_n011OiO_dataout <= nlOOil0l AND nlli0lO; + wire_n011Ol_dataout <= (wire_w_lg_n10Oi0i2520w(0) OR (wire_w_lg_n10Oi1O2521w(0) OR (wire_w_lg_n10Oi1l2522w(0) OR (wire_w_lg_n10Oi1i2523w(0) OR (wire_w_lg_n10O0OO2524w(0) OR (wire_w_lg_n10O0Ol2525w(0) OR wire_w_lg_n10O0Oi2526w(0))))))) AND n1OiOi; + wire_n011Oli_dataout <= nlOOil0O AND nlli0lO; + wire_n011Oll_dataout <= nlOOilii AND nlli0lO; + wire_n011OlO_dataout <= nlOOilil AND nlli0lO; + wire_n011OO_dataout <= (n1i1i0O OR n1i1i0l) AND n1OiOi; + wire_n011OOi_dataout <= n011lOl AND nlli0lO; + wire_n011OOl_dataout <= n011lOO AND nlli0lO; + wire_n011OOO_dataout <= n011O1i AND nlli0lO; + wire_n01i_dataout <= (NOT pudi(12)) WHEN nO = '1' ELSE pudi(12); + wire_n01ilO_dataout <= (wire_w_lg_n10Oill2484w(0) OR (wire_w_lg_n10Oili2485w(0) OR (wire_w_lg_n10OiiO2486w(0) OR (wire_w_lg_n10Oiil2487w(0) OR (wire_w_lg_n10Oiii2488w(0) OR (wire_w_lg_n10Oi0O2489w(0) OR wire_w_lg_n10Oi0l2490w(0))))))) AND n1OiOi; + wire_n01iOi_dataout <= (wire_w_lg_w_pmadwidth_range175w2482w(0) OR (wire_w_lg_w_pmadwidth_range175w219w(0) AND wire_w_lg_n1i1l0O2133w(0))) AND n1OiOi; + wire_n01iOl_dataout <= n10OO1l AND n1OiOi; + wire_n01iOO_dataout <= n10OO0i AND n1OiOi; + wire_n01l_dataout <= (NOT pudi(13)) WHEN nO = '1' ELSE pudi(13); + wire_n01l0i_dataout <= n01iiO AND n1OiOi; + wire_n01l0l_dataout <= n01ili AND n1OiOi; + wire_n01l0O_dataout <= n01ill AND n1OiOi; + wire_n01l1i_dataout <= (((wire_w_lg_n10OOli2339w(0) OR wire_w_lg_n10OOiO2341w(0)) OR wire_w_lg_n10OOil2349w(0)) OR wire_w_lg_n10OOii2480w(0)) AND n1OiOi; + wire_n01l1l_dataout <= (wire_w_lg_n1i1iii2473w(0) OR (NOT ((n1i1l0O OR n1i1iil) OR n1i1iii))) AND n1OiOi; + wire_n01l1O_dataout <= n01iil AND n1OiOi; + wire_n01lii_dataout <= n10OOlO AND n1OiOi; + wire_n01lil_dataout <= n10OOOl AND n1OiOi; + wire_n01liO_dataout <= (((wire_w_lg_n1i110l2285w(0) OR wire_w_lg_n1i110i2287w(0)) OR wire_w_lg_n1i111O2295w(0)) OR wire_w_lg_n1i111l2471w(0)) AND n1OiOi; + wire_n01lli_dataout <= (wire_w_lg_n1i1l1i2463w(0) OR (NOT ((wire_w_lg_n1i1l0l2464w(0) OR n1i1l1O) OR n1i1l1i))) AND n1OiOi; + wire_n01O_dataout <= (NOT pudi(14)) WHEN nO = '1' ELSE pudi(14); + wire_n0i_dataout <= nl0101O WHEN wa_6g_en = '1' ELSE nl1liO; + wire_n0ii_dataout <= (((n1OO0li OR n1OO0iO) OR (NOT (n1iii0O10 XOR n1iii0O9))) OR ((n1iiiOi AND n1OO00i) AND (n1iii0i12 XOR n1iii0i11))) WHEN wa_6g_en = '1' ELSE (((n1Oi0i OR n1Oi1O) OR (n1iiiOi AND n1O01O)) OR (NOT (n1iiiil8 XOR n1iiiil7))); + wire_n0il_dataout <= n1iiili WHEN wa_6g_en = '1' ELSE n1iiill; + wire_n0iO_dataout <= nl01O1O WHEN wa_6g_en = '1' ELSE nlO01ii; + wire_n0l_dataout <= nl0100i WHEN wa_6g_en = '1' ELSE nl1lli; + wire_n0li_dataout <= wire_nl1iOOl_dataout WHEN wa_6g_en = '1' ELSE wire_nii0ii_dataout; + wire_n0ll_dataout <= wire_nl1iOOO_dataout WHEN wa_6g_en = '1' ELSE wire_nii0il_dataout; + wire_n0lO_dataout <= wire_nl1l11i_dataout WHEN wa_6g_en = '1' ELSE wire_nii0iO_dataout; + wire_n0O_dataout <= nl0100l WHEN wa_6g_en = '1' ELSE nl1llO; + wire_n0Oi_dataout <= wire_nl1l11l_dataout WHEN wa_6g_en = '1' ELSE wire_nii0li_dataout; + wire_n0Ol_dataout <= wire_nl1l11O_dataout WHEN wa_6g_en = '1' ELSE wire_nii0ll_dataout; + wire_n0OO_dataout <= wire_nl1l10i_dataout WHEN wa_6g_en = '1' ELSE wire_nii0lO_dataout; + wire_n10i_dataout <= (NOT pudi(18)) WHEN nO = '1' ELSE pudi(18); + wire_n10l_dataout <= (NOT pudi(19)) WHEN nO = '1' ELSE pudi(19); + wire_n10O_dataout <= (NOT pudi(0)) WHEN nO = '1' ELSE pudi(0); + wire_n110ll_dataout <= wire_nlOll0O_dataout WHEN ((wire_niOl1O_o XOR wire_niOl1l_o) AND n1i01ll) = '1' ELSE (n1i01lO OR n1i01OO); + wire_n11i_dataout <= (NOT pudi(15)) WHEN nO = '1' ELSE pudi(15); + wire_n11l_dataout <= (NOT pudi(16)) WHEN nO = '1' ELSE pudi(16); + wire_n11O_dataout <= (NOT pudi(17)) WHEN nO = '1' ELSE pudi(17); + wire_n1i_dataout <= nll01ll WHEN wa_6g_en = '1' ELSE nlO011l; + wire_n1ii_dataout <= (NOT pudi(1)) WHEN nO = '1' ELSE pudi(1); + wire_n1il_dataout <= (NOT pudi(2)) WHEN nO = '1' ELSE pudi(2); + wire_n1iliii_dataout <= nl1liil WHEN ((wire_nl1lilO_w_lg_w_lg_o16913w17152w(0) OR (wire_nl1lilO_o AND nlOO1lii)) OR (nlOO1llO AND nlOO1lli)) = '1' ELSE (nlOO1lil OR nlOO1liO); + wire_n1iliii_w_lg_w_lg_dataout17118w17148w(0) <= wire_n1iliii_w_lg_dataout17118w(0) AND nlOO1l0l; + wire_n1iliii_w_lg_dataout17118w(0) <= NOT wire_n1iliii_dataout; + wire_n1iO_dataout <= (NOT pudi(3)) WHEN nO = '1' ELSE pudi(3); + wire_n1l_dataout <= wire_nllO_dataout WHEN wa_6g_en = '1' ELSE nlO011O; + wire_n1l0Ol_dataout <= wire_n1li1O_o(0) WHEN wire_n1li0i_o(4) = '1' ELSE wire_n1li0l_dataout; + wire_n1l0OO_dataout <= wire_n1li1O_o(1) WHEN wire_n1li0i_o(4) = '1' ELSE wire_n1li0O_dataout; + wire_n1l11lO_dataout <= wire_n1iliii_dataout WHEN ((wire_nl1ll1i_o XOR wire_nl1liOO_o) AND nlOO1O0i) = '1' ELSE (nlOO1O0l OR nlOO1O1O); + wire_n1l11lO_w_lg_dataout16770w(0) <= wire_n1l11lO_dataout AND wire_w_lg_nlOO0i1l16769w(0); + wire_n1l11lO_w_lg_dataout16758w(0) <= NOT wire_n1l11lO_dataout; + wire_n1l1Ol_dataout <= (wire_w_lg_n10O1Oi3072w(0) AND ((NOT (wire_w_lg_n10O11i3074w(0) OR wire_w_lg_n1i000i3077w(0))) AND (NOT (((n10lOOi OR n1i01Oi) OR ((NOT (((n1i1OlO OR n1i1Oll) OR n1i1OiO) OR n1i1Oli)) AND (wire_w_lg_n10lOlO3084w(0) AND (wire_niOl1l_w_lg_w_lg_o2983w3085w(0) OR (wire_niOl1l_o AND n1i01Ol))))) OR ((wire_niOl0l_w_lg_w_lg_dataout1312w3091w(0) OR (wire_niOl0l_dataout AND n1i01Ol)) AND wire_w_lg_n1i1Oll3095w(0)))))) WHEN ((NOT r8b10b_dec_ibm_en(0)) AND (NOT r8b10b_dec_ibm_en(1))) = '1' ELSE (NOT (((((((((((((wire_w_lg_n10O1Oi2971w(0) OR (wire_niOl1i_w_lg_o2972w(0) AND wire_niOiOO_w_lg_w_lg_o2973w2974w(0))) OR wire_niOl1i_w_lg_o2978w(0)) OR (wire_niOl0l_w_lg_dataout2982w(0) OR (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w2984w(0))))) OR (wire_niOl0i_w_lg_dataout1313w(0) AND (wire_niOl1O_w_lg_o1314w(0) AND (wire_niOl1l_w_lg_o2983w(0) AND (wire_niOl1i_w_lg_o2972w(0) AND wire_niOiOO_w_lg_o2973w(0)))))) OR wire_niOl0i_w_lg_dataout2997w(0)) OR (wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w2999w(0)))) OR wire_niOl0l_w_lg_dataout3005w(0)) OR (((wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w3007w(0))) OR wire_niOl0l_w_lg_dataout3012w(0)) AND wire_w_lg_n10O10O3014w(0))) OR wire_w_lg_n10O10O3020w(0)) OR ((wire_niOl0l_w_lg_dataout1312w(0) AND (wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w3022w(0))) AND wire_w_lg_n10O1iO3025w(0))) OR (wire_niOl0l_w_lg_dataout3030w(0) AND wire_w_lg_n10O1li3031w(0))) OR wire_w_lg_w_r8b10b_dec_ibm_en_range3034w3050w(0)) OR wire_w_lg_w_r8b10b_dec_ibm_en_range3034w3069w(0))); + wire_n1l1Ol_w_lg_dataout173w(0) <= NOT wire_n1l1Ol_dataout; + wire_n1li_dataout <= (NOT pudi(4)) WHEN nO = '1' ELSE pudi(4); + wire_n1li0l_dataout <= n1l0iO AND n10O1Ol; + wire_n1li0O_dataout <= n1l0li AND n10O1Ol; + wire_n1li1i_dataout <= wire_n1li1O_o(2) WHEN wire_n1li0i_o(4) = '1' ELSE wire_n1liil_dataout; + wire_n1li1l_dataout <= wire_n1li1O_o(3) WHEN wire_n1li0i_o(4) = '1' ELSE wire_n1liiO_dataout; + wire_n1liil_dataout <= n1l0ll AND n10O1Ol; + wire_n1liiO_dataout <= n1l0lO AND n10O1Ol; + wire_n1liO0O_dataout <= (wire_w_lg_nlOO00ii16945w(0) AND ((NOT (wire_w_lg_nlOO01li16947w(0) OR wire_w_lg_nlOO01ii16950w(0))) AND (NOT (((nlOO011O OR nlOO011l) OR ((NOT (((nlOO011i OR nlOO1OOO) OR wire_nl1liOl_w_lg_o16956w(0)) OR (wire_nl1liOl_w_lg_o16842w(0) AND (wire_nl1liOi_o AND nlOO1OOi)))) AND (wire_w_lg_nlOO1OlO16962w(0) AND (wire_nl1liOO_w_lg_w_lg_o16856w16963w(0) OR (wire_nl1liOO_o AND nlOO1Oli))))) OR ((wire_nl1ll1O_w_lg_w_lg_o16853w16969w(0) OR (wire_nl1ll1O_o AND nlOO1Oli)) AND wire_w_lg_nlOO1OOO16973w(0)))))) WHEN ((NOT r8b10b_dec_ibm_en(0)) AND (NOT r8b10b_dec_ibm_en(1))) = '1' ELSE (NOT (((((((((((((wire_w_lg_nlOO00ii16841w(0) OR (wire_nl1liOl_w_lg_o16842w(0) AND wire_nl1liOi_w_lg_w_lg_o16843w16844w(0))) OR wire_nl1liOl_w_lg_o16848w(0)) OR (wire_nl1ll1O_w_lg_o16852w(0) OR (wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_w_lg_o16855w16857w(0))))) OR (wire_nl1ll1l_w_lg_o16854w(0) AND (wire_nl1ll1i_w_lg_o16855w(0) AND (wire_nl1liOO_w_lg_o16856w(0) AND (wire_nl1liOl_w_lg_o16842w(0) AND wire_nl1liOi_w_lg_o16843w(0)))))) OR wire_nl1ll1l_w_lg_o16870w(0)) OR (wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_w_lg_o16855w16872w(0)))) OR wire_nl1ll1O_w_lg_o16878w(0)) OR (((wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_w_lg_o16855w16880w(0))) OR wire_nl1ll1O_w_lg_o16885w(0)) AND wire_w_lg_nlOO01OO16887w(0))) OR wire_w_lg_nlOO01OO16893w(0)) OR ((wire_nl1ll1O_w_lg_o16853w(0) AND (wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_w_lg_o16855w16895w(0))) AND wire_w_lg_nlOO001O16898w(0))) OR (wire_nl1ll1O_w_lg_o16903w(0) AND wire_w_lg_nlOO000i16904w(0))) OR wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16923w(0)) OR wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16942w(0))); + wire_n1liO0O_w_lg_dataout4506w(0) <= NOT wire_n1liO0O_dataout; + wire_n1ll_dataout <= (NOT pudi(5)) WHEN nO = '1' ELSE pudi(5); + wire_n1lliO_dataout <= wire_n1O1iO_dataout AND n1O01i; + wire_n1lllii_dataout <= wire_n1l11lO_dataout WHEN ((wire_nl1llii_w_lg_w_lg_o16569w16808w(0) OR (wire_nl1llii_o AND nlOO0i1i)) OR (nlOO0i0O AND nlOO0i0i)) = '1' ELSE (nlOO0i1l OR nlOO0i1O); + wire_n1lllii_w_lg_w_lg_dataout16774w16804w(0) <= wire_n1lllii_w_lg_dataout16774w(0) AND nlOO00Ol; + wire_n1lllii_w_lg_dataout16774w(0) <= NOT wire_n1lllii_dataout; + wire_n1llOl_dataout <= wire_n1O1li_dataout AND n1O01i; + wire_n1llOO_dataout <= n1OiOi AND n1O01l; + wire_n1lO_dataout <= (NOT pudi(6)) WHEN nO = '1' ELSE pudi(6); + wire_n1lO0i_dataout <= n0110i AND NOT(n10O0ii); + wire_n1lO0l_dataout <= wire_n1lOil_dataout AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1lO0O_dataout <= n10O00O AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1lO1i_dataout <= n0111i AND NOT(n10O0ii); + wire_n1lO1l_dataout <= n0111l AND NOT(n10O0ii); + wire_n1lO1O_dataout <= n0111O AND NOT(n10O0ii); + wire_n1lOii_dataout <= wire_n1lOiO_dataout AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1lOil_dataout <= wire_w_lg_n10O00l2717w(0) AND NOT(n10O00O); + wire_n1lOiO_dataout <= n10O00l AND NOT(n10O00O); + wire_n1lOlO_dataout <= n010OO AND NOT(n10O0ii); + wire_n1lOOi_dataout <= n01i1i AND NOT(n10O0ii); + wire_n1lOOl_dataout <= n01i1l AND NOT(n10O0ii); + wire_n1lOOO_dataout <= n01i1O AND NOT(n10O0ii); + wire_n1O_dataout <= wire_nlOi_dataout WHEN wa_6g_en = '1' ELSE nl1lil; + wire_n1O00i_dataout <= max_rlv_sel(0) AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_n1O00i_w_lg_dataout2967w(0) <= NOT wire_n1O00i_dataout; + wire_n1O00l_dataout <= max_rlv_sel(1) AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_n1O00l_w_lg_dataout2965w(0) <= NOT wire_n1O00l_dataout; + wire_n1O00O_dataout <= max_rlv_sel(0) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n1O0lO_o(0); + wire_n1O0ii_dataout <= max_rlv_sel(1) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n1O0lO_o(1); + wire_n1O0ii_w_lg_dataout2962w(0) <= NOT wire_n1O0ii_dataout; + wire_n1O0il_dataout <= max_rlv_sel(2) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n1O0lO_o(2); + wire_n1O0il_w_lg_dataout2960w(0) <= NOT wire_n1O0il_dataout; + wire_n1O0iO_dataout <= max_rlv_sel(3) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n1O0lO_o(3); + wire_n1O0iO_w_lg_dataout2958w(0) <= NOT wire_n1O0iO_dataout; + wire_n1O0li_dataout <= max_rlv_sel(4) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n1O0lO_o(4); + wire_n1O0li_w_lg_dataout2956w(0) <= NOT wire_n1O0li_dataout; + wire_n1O0ll_dataout <= wire_w_lg_n10O0li2685w(0) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE wire_n1O0lO_o(5); + wire_n1O0ll_w_lg_w2963w2964w(0) <= wire_n1O0ll_w2963w(0) AND wire_n1O00O_dataout; + wire_n1O0ll_w2963w(0) <= wire_n1O0ll_w_lg_w_lg_w_lg_w_lg_dataout2955w2957w2959w2961w(0) AND wire_n1O0ii_w_lg_dataout2962w(0); + wire_n1O0ll_w_lg_w_lg_w_lg_w_lg_dataout2955w2957w2959w2961w(0) <= wire_n1O0ll_w_lg_w_lg_w_lg_dataout2955w2957w2959w(0) AND wire_n1O0il_w_lg_dataout2960w(0); + wire_n1O0ll_w_lg_w_lg_w_lg_dataout2955w2957w2959w(0) <= wire_n1O0ll_w_lg_w_lg_dataout2955w2957w(0) AND wire_n1O0iO_w_lg_dataout2958w(0); + wire_n1O0ll_w_lg_w_lg_dataout2955w2957w(0) <= wire_n1O0ll_w_lg_dataout2955w(0) AND wire_n1O0li_w_lg_dataout2956w(0); + wire_n1O0ll_w_lg_dataout2955w(0) <= NOT wire_n1O0ll_dataout; + wire_n1O10i_dataout <= wire_n1O10O_dataout AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1O10l_dataout <= wire_w_lg_n10O0il2712w(0) AND NOT(n10O0iO); + wire_n1O10lO_dataout <= wire_n1lllii_dataout WHEN ((wire_nl1llll_o XOR wire_nl1llli_o) AND nlOO0iOi) = '1' ELSE (nlOO0iOl OR nlOO0ilO); + wire_n1O10O_dataout <= n10O0il AND NOT(n10O0iO); + wire_n1O11l_dataout <= n10O0iO AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1O11O_dataout <= wire_n1O10l_dataout AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1O1iO_dataout <= n1OOOl AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1O1li_dataout <= wire_nl_w_lg_n1OOOl2708w(0) AND NOT(wire_nl_w_lg_n1OiOi2540w(0)); + wire_n1Oi_dataout <= (NOT pudi(7)) WHEN nO = '1' ELSE pudi(7); + wire_n1Oiii_dataout <= n1Oi1O AND n1OiOi; + wire_n1Oiil_dataout <= n1Oi0i AND n1OiOi; + wire_n1OiiO_dataout <= n1iiill AND n1OiOi; + wire_n1Oili_dataout <= wire_n1Oill_o AND n1OiOi; + wire_n1Ol_dataout <= (NOT pudi(10)) WHEN nO = '1' ELSE pudi(10); + wire_n1Ol0iO_dataout <= wire_n1Ol0Ol_o(0) WHEN wire_n1Ol0OO_o(5) = '1' ELSE wire_n1Oli1i_dataout; + wire_n1Ol0li_dataout <= wire_n1Ol0Ol_o(1) WHEN wire_n1Ol0OO_o(5) = '1' ELSE wire_n1Oli1l_dataout; + wire_n1Ol0ll_dataout <= wire_n1Ol0Ol_o(2) WHEN wire_n1Ol0OO_o(5) = '1' ELSE wire_n1Oli1O_dataout; + wire_n1Ol0lO_dataout <= wire_n1Ol0Ol_o(3) WHEN wire_n1Ol0OO_o(5) = '1' ELSE wire_n1Oli0l_dataout; + wire_n1Ol0Oi_dataout <= wire_n1Ol0Ol_o(4) WHEN wire_n1Ol0OO_o(5) = '1' ELSE wire_n1Oli0O_dataout; + wire_n1Ol10O_dataout <= (wire_w_lg_nlOOi11i16601w(0) AND ((NOT (wire_w_lg_nlOO0O0i16603w(0) OR wire_w_lg_nlOO0O1i16606w(0))) AND (NOT (((nlOO0llO OR nlOO0lll) OR ((NOT (((nlOO0lli OR nlOO0liO) OR wire_nl1lliO_w_lg_o16612w(0)) OR (wire_nl1lliO_w_lg_o16498w(0) AND (wire_nl1llil_o AND nlOO0lii)))) AND (wire_w_lg_nlOO0l0O16618w(0) AND (wire_nl1llli_w_lg_w_lg_o16512w16619w(0) OR (wire_nl1llli_o AND nlOO0l0i))))) OR ((wire_nl1llOi_w_lg_w_lg_o16509w16625w(0) OR (wire_nl1llOi_o AND nlOO0l0i)) AND wire_w_lg_nlOO0liO16629w(0)))))) WHEN ((NOT r8b10b_dec_ibm_en(0)) AND (NOT r8b10b_dec_ibm_en(1))) = '1' ELSE (NOT (((((((((((((wire_w_lg_nlOOi11i16497w(0) OR (wire_nl1lliO_w_lg_o16498w(0) AND wire_nl1llil_w_lg_w_lg_o16499w16500w(0))) OR wire_nl1lliO_w_lg_o16504w(0)) OR (wire_nl1llOi_w_lg_o16508w(0) OR (wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_w_lg_o16511w16513w(0))))) OR (wire_nl1lllO_w_lg_o16510w(0) AND (wire_nl1llll_w_lg_o16511w(0) AND (wire_nl1llli_w_lg_o16512w(0) AND (wire_nl1lliO_w_lg_o16498w(0) AND wire_nl1llil_w_lg_o16499w(0)))))) OR wire_nl1lllO_w_lg_o16526w(0)) OR (wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_w_lg_o16511w16528w(0)))) OR wire_nl1llOi_w_lg_o16534w(0)) OR (((wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_w_lg_o16511w16536w(0))) OR wire_nl1llOi_w_lg_o16541w(0)) AND wire_w_lg_nlOO0OiO16543w(0))) OR wire_w_lg_nlOO0OiO16549w(0)) OR ((wire_nl1llOi_w_lg_o16509w(0) AND (wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_w_lg_o16511w16551w(0))) AND wire_w_lg_nlOO0OlO16554w(0))) OR (wire_nl1llOi_w_lg_o16559w(0) AND wire_w_lg_nlOO0OOi16560w(0))) OR wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16579w(0)) OR wire_w_lg_w_r8b10b_dec_ibm_en_range3034w16598w(0))); + wire_n1Ol10O_w_lg_dataout4507w(0) <= NOT wire_n1Ol10O_dataout; + wire_n1Oli0l_dataout <= n1Ol00O AND nlOOi11l; + wire_n1Oli0O_dataout <= n1Ol0ii AND nlOOi11l; + wire_n1Oli1i_dataout <= n1Ol01O AND nlOOi11l; + wire_n1Oli1l_dataout <= n1Ol00i AND nlOOi11l; + wire_n1Oli1O_dataout <= n1Ol00l AND nlOOi11l; + wire_n1Ollil_dataout <= wire_n1OO1li_dataout AND n1OO01l; + wire_n1OllOi_dataout <= wire_n1OO1ll_dataout AND n1OO01l; + wire_n1OllOl_dataout <= nlli0lO AND n1OO01O; + wire_n1OllOO_dataout <= n011l0i AND NOT(nlOOi1li); + wire_n1OlO0i_dataout <= n011lil AND NOT(nlOOi1li); + wire_n1OlO0l_dataout <= wire_n1OlOil_dataout AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OlO0O_dataout <= nlOOi1iO AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OlO1i_dataout <= n011l0l AND NOT(nlOOi1li); + wire_n1OlO1l_dataout <= n011l0O AND NOT(nlOOi1li); + wire_n1OlO1O_dataout <= n011lii AND NOT(nlOOi1li); + wire_n1OlOii_dataout <= wire_n1OlOiO_dataout AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OlOil_dataout <= wire_w_lg_nlOOi1il16159w(0) AND NOT(nlOOi1iO); + wire_n1OlOiO_dataout <= nlOOi1il AND NOT(nlOOi1iO); + wire_n1OlOlO_dataout <= n0101iO AND NOT(nlOOi1li); + wire_n1OlOOi_dataout <= n0101li AND NOT(nlOOi1li); + wire_n1OlOOl_dataout <= n0101ll AND NOT(nlOOi1li); + wire_n1OlOOO_dataout <= n0101lO AND NOT(nlOOi1li); + wire_n1OO_dataout <= (NOT pudi(11)) WHEN nO = '1' ELSE pudi(11); + wire_n1OO0Oi_dataout <= n1OO0iO AND nlli0lO; + wire_n1OO0Ol_dataout <= n1OO0li AND nlli0lO; + wire_n1OO0OO_dataout <= n1iiili AND nlli0lO; + wire_n1OO10i_dataout <= wire_n1OO10O_dataout AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OO10l_dataout <= wire_n1OO1ii_dataout AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OO10O_dataout <= wire_w_lg_nlOOi1ll16154w(0) AND NOT(nlOOi1lO); + wire_n1OO11i_dataout <= n0101Oi AND NOT(nlOOi1li); + wire_n1OO11O_dataout <= nlOOi1lO AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OO1ii_dataout <= nlOOi1ll AND NOT(nlOOi1lO); + wire_n1OO1li_dataout <= n011l1l AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OO1ll_dataout <= wire_nl_w_lg_n011l1l16150w(0) AND NOT(wire_nl_w_lg_nlli0lO15746w(0)); + wire_n1OOi1i_dataout <= wire_n1OOi1l_o AND nlli0lO; + wire_n1OOOi_dataout <= n10O0ll WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE n10O0lO; + wire_n1OOOi_w_lg_dataout2538w(0) <= NOT wire_n1OOOi_dataout; + wire_ni_dataout <= gen2ngen1 WHEN rindv_rx = '1' ELSE gen2ngen1_bundle; + wire_ni0i_dataout <= wire_nl1l1il_dataout WHEN wa_6g_en = '1' ELSE wire_niii1i_dataout; + wire_ni0l_dataout <= wire_nl1iOil_dataout WHEN wa_6g_en = '1' ELSE wire_nii01i_dataout; + wire_ni0lO_dataout <= ni0li AND NOT(scan_mode); + wire_ni0lO_w_lg_dataout2w(0) <= NOT wire_ni0lO_dataout; + wire_ni0O_dataout <= wire_nl1iOiO_dataout WHEN wa_6g_en = '1' ELSE wire_nii01l_dataout; + wire_ni1i_dataout <= wire_nl1l10l_dataout WHEN wa_6g_en = '1' ELSE wire_nii0Oi_dataout; + wire_ni1l_dataout <= wire_nl1l10O_dataout WHEN wa_6g_en = '1' ELSE wire_nii0Ol_dataout; + wire_ni1O_dataout <= wire_nl1l1ii_dataout WHEN wa_6g_en = '1' ELSE wire_nii0OO_dataout; + wire_nii_dataout <= nl0100O WHEN wa_6g_en = '1' ELSE niii0l; + wire_nii00i_dataout <= nil0Ol AND NOT(rrxpcsbypass_en); + wire_nii00l_dataout <= nil0OO AND NOT(rrxpcsbypass_en); + wire_nii00O_dataout <= nili1i AND NOT(rrxpcsbypass_en); + wire_nii01i_dataout <= nil0ll AND NOT(rrxpcsbypass_en); + wire_nii01l_dataout <= nil0lO AND NOT(rrxpcsbypass_en); + wire_nii01O_dataout <= nil0Oi AND NOT(rrxpcsbypass_en); + wire_nii0i_dataout <= nl0100O WHEN wa_6g_en = '1' ELSE nl1llO; + wire_nii0ii_dataout <= nliOlO WHEN rrxpcsbypass_en = '1' ELSE nil01i; + wire_nii0il_dataout <= nliOOi WHEN rrxpcsbypass_en = '1' ELSE nil01l; + wire_nii0iO_dataout <= nliOOl WHEN rrxpcsbypass_en = '1' ELSE nil01O; + wire_nii0l_dataout <= nl010ii AND wa_6g_en; + wire_nii0li_dataout <= nliOOO WHEN rrxpcsbypass_en = '1' ELSE nil00i; + wire_nii0ll_dataout <= nll11i WHEN rrxpcsbypass_en = '1' ELSE nil00l; + wire_nii0lO_dataout <= nll11l WHEN rrxpcsbypass_en = '1' ELSE nil00O; + wire_nii0O_dataout <= wire_nl1iOlO_dataout WHEN wa_6g_en = '1' ELSE wire_nii00l_dataout; + wire_nii0Oi_dataout <= nll11O WHEN rrxpcsbypass_en = '1' ELSE nil0ii; + wire_nii0Ol_dataout <= nll10i WHEN rrxpcsbypass_en = '1' ELSE nil0il; + wire_nii0OO_dataout <= wire_niii1l_dataout WHEN rrxpcsbypass_en = '1' ELSE nil0iO; + wire_nii1i_dataout <= nl0101O WHEN wa_6g_en = '1' ELSE nl1lil; + wire_nii1l_dataout <= nl0100i WHEN wa_6g_en = '1' ELSE nl1liO; + wire_nii1O_dataout <= nl0100l WHEN wa_6g_en = '1' ELSE nl1lli; + wire_niii_dataout <= wire_nl1iOli_dataout WHEN wa_6g_en = '1' ELSE wire_nii01O_dataout; + wire_niii1i_dataout <= wire_niii1O_dataout WHEN rrxpcsbypass_en = '1' ELSE nil0li; + wire_niii1l_dataout <= nll10l AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_niii1O_dataout <= nll1ii AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_niiii_dataout <= wire_nl1iOOi_dataout WHEN wa_6g_en = '1' ELSE wire_nii00O_dataout; + wire_niiil_dataout <= wire_nl1l1OO_dataout AND wa_6g_en; + wire_niiiO_dataout <= wire_nl1l01i_dataout AND wa_6g_en; + wire_niiiOO_dataout <= comp_pat(7) WHEN nill0l = '1' ELSE comp_pat(0); + wire_niil_dataout <= wire_nl1iOll_dataout WHEN wa_6g_en = '1' ELSE wire_nii00i_dataout; + wire_niil0i_dataout <= comp_pat(3) WHEN nill0l = '1' ELSE comp_pat(4); + wire_niil0l_dataout <= comp_pat(2) WHEN nill0l = '1' ELSE comp_pat(5); + wire_niil0O_dataout <= comp_pat(1) WHEN nill0l = '1' ELSE comp_pat(6); + wire_niil1i_dataout <= comp_pat(6) WHEN nill0l = '1' ELSE comp_pat(1); + wire_niil1l_dataout <= comp_pat(5) WHEN nill0l = '1' ELSE comp_pat(2); + wire_niil1O_dataout <= comp_pat(4) WHEN nill0l = '1' ELSE comp_pat(3); + wire_niili_dataout <= (NOT pudr(0)) WHEN nO = '1' ELSE pudr(0); + wire_niilii_dataout <= comp_pat(0) WHEN nill0l = '1' ELSE comp_pat(7); + wire_niilil_dataout <= comp_pat(15) WHEN nill0l = '1' ELSE comp_pat(8); + wire_niiliO_dataout <= comp_pat(14) WHEN nill0l = '1' ELSE comp_pat(9); + wire_niill_dataout <= (NOT pudr(1)) WHEN nO = '1' ELSE pudr(1); + wire_niilli_dataout <= comp_pat(13) WHEN nill0l = '1' ELSE comp_pat(10); + wire_niilll_dataout <= comp_pat(12) WHEN nill0l = '1' ELSE comp_pat(11); + wire_niillO_dataout <= comp_pat(11) WHEN nill0l = '1' ELSE comp_pat(12); + wire_niilO_dataout <= (NOT pudr(2)) WHEN nO = '1' ELSE pudr(2); + wire_niilOi_dataout <= comp_pat(10) WHEN nill0l = '1' ELSE comp_pat(13); + wire_niilOl_dataout <= comp_pat(9) WHEN nill0l = '1' ELSE comp_pat(14); + wire_niilOO_dataout <= comp_pat(8) WHEN nill0l = '1' ELSE comp_pat(15); + wire_niiO_dataout <= wire_nl1iOlO_dataout WHEN wa_6g_en = '1' ELSE wire_nii00l_dataout; + wire_niiO0i_dataout <= comp_pat(6) WHEN nill0l = '1' ELSE comp_pat(3); + wire_niiO0i_w_lg_dataout2058w(0) <= NOT wire_niiO0i_dataout; + wire_niiO0l_dataout <= comp_pat(5) WHEN nill0l = '1' ELSE comp_pat(4); + wire_niiO0l_w_lg_dataout2062w(0) <= NOT wire_niiO0l_dataout; + wire_niiO0O_dataout <= comp_pat(4) WHEN nill0l = '1' ELSE comp_pat(5); + wire_niiO0O_w_lg_dataout2066w(0) <= NOT wire_niiO0O_dataout; + wire_niiO1i_dataout <= comp_pat(9) WHEN nill0l = '1' ELSE comp_pat(0); + wire_niiO1i_w_lg_dataout2047w(0) <= NOT wire_niiO1i_dataout; + wire_niiO1l_dataout <= comp_pat(8) WHEN nill0l = '1' ELSE comp_pat(1); + wire_niiO1l_w_lg_dataout2050w(0) <= NOT wire_niiO1l_dataout; + wire_niiO1O_dataout <= comp_pat(7) WHEN nill0l = '1' ELSE comp_pat(2); + wire_niiO1O_w_lg_dataout2054w(0) <= NOT wire_niiO1O_dataout; + wire_niiOi_dataout <= (NOT pudr(3)) WHEN nO = '1' ELSE pudr(3); + wire_niiOii_dataout <= comp_pat(3) WHEN nill0l = '1' ELSE comp_pat(6); + wire_niiOii_w_lg_dataout2070w(0) <= NOT wire_niiOii_dataout; + wire_niiOil_dataout <= comp_pat(2) WHEN nill0l = '1' ELSE comp_pat(7); + wire_niiOil_w_lg_dataout2074w(0) <= NOT wire_niiOil_dataout; + wire_niiOiO_dataout <= comp_pat(1) WHEN nill0l = '1' ELSE comp_pat(8); + wire_niiOiO_w_lg_dataout2078w(0) <= NOT wire_niiOiO_dataout; + wire_niiOl_dataout <= (NOT pudr(4)) WHEN nO = '1' ELSE pudr(4); + wire_niiOli_dataout <= comp_pat(0) WHEN nill0l = '1' ELSE comp_pat(9); + wire_niiOli_w_lg_dataout2082w(0) <= NOT wire_niiOli_dataout; + wire_niiOO_dataout <= (NOT pudr(5)) WHEN nO = '1' ELSE pudr(5); + wire_nil_dataout <= nl010ii WHEN wa_6g_en = '1' ELSE nlO01ii; + wire_nil0i_dataout <= (NOT pudr(9)) WHEN nO = '1' ELSE pudr(9); + wire_nil0l_dataout <= (NOT pudi(0)) WHEN nO = '1' ELSE pudi(0); + wire_nil0O_dataout <= (NOT pudi(1)) WHEN nO = '1' ELSE pudi(1); + wire_nil10l_dataout <= (n1i1OOO OR n1i1OOl) WHEN n1i1OOi = '1' ELSE (n1i011l OR n1i011i); + wire_nil1i_dataout <= (NOT pudr(6)) WHEN nO = '1' ELSE pudr(6); + wire_nil1l_dataout <= (NOT pudr(7)) WHEN nO = '1' ELSE pudr(7); + wire_nil1O_dataout <= (NOT pudr(8)) WHEN nO = '1' ELSE pudr(8); + wire_nili_dataout <= wire_nl1iOOi_dataout WHEN wa_6g_en = '1' ELSE wire_nii00O_dataout; + wire_nilii_dataout <= (NOT pudi(2)) WHEN nO = '1' ELSE pudi(2); + wire_nilil_dataout <= (NOT pudi(3)) WHEN nO = '1' ELSE pudi(3); + wire_niliO_dataout <= (NOT pudi(4)) WHEN nO = '1' ELSE pudi(4); + wire_nill_dataout <= wire_nl1l01l_dataout AND wa_6g_en; + wire_nilli_dataout <= (NOT pudi(5)) WHEN nO = '1' ELSE pudi(5); + wire_nillii_dataout <= ((nil1ll OR n1i011O) OR (n1iiiOi AND nil1il)) AND n1ii10i; + wire_nillil_dataout <= ((nil1lO OR n1i010i) OR (n1iiiOi AND nil1iO)) WHEN n1ii10i = '1' ELSE ((nil1li OR wire_nil10l_dataout) OR (n1iiiOi AND niii0O)); + wire_nilll_dataout <= (NOT pudi(6)) WHEN nO = '1' ELSE pudi(6); + wire_nilllO_dataout <= wire_niiiOO_dataout WHEN n1i010O = '1' ELSE wire_nilOii_dataout; + wire_nillO_dataout <= (NOT pudi(7)) WHEN nO = '1' ELSE pudi(7); + wire_nillOi_dataout <= wire_niil1i_dataout WHEN n1i010O = '1' ELSE wire_nilOil_dataout; + wire_nillOl_dataout <= wire_niil1l_dataout WHEN n1i010O = '1' ELSE wire_nilOiO_dataout; + wire_nillOO_dataout <= wire_niil1O_dataout WHEN n1i010O = '1' ELSE wire_nilOli_dataout; + wire_nilO_dataout <= wire_nl1l01O_dataout AND wa_6g_en; + wire_nilO0i_dataout <= wire_niilii_dataout WHEN n1i010O = '1' ELSE wire_nilOOl_dataout; + wire_nilO0l_dataout <= nilili WHEN n1i010O = '1' ELSE wire_nilOOO_dataout; + wire_nilO0O_dataout <= wire_niO11i_dataout AND NOT(n1i010O); + wire_nilO1i_dataout <= wire_niil0i_dataout WHEN n1i010O = '1' ELSE wire_nilOll_dataout; + wire_nilO1l_dataout <= wire_niil0l_dataout WHEN n1i010O = '1' ELSE wire_nilOlO_dataout; + wire_nilO1O_dataout <= wire_niil0O_dataout WHEN n1i010O = '1' ELSE wire_nilOOi_dataout; + wire_nilOi_dataout <= (NOT pudi(8)) WHEN nO = '1' ELSE pudi(8); + wire_nilOii_dataout <= nili1l WHEN n1i010l = '1' ELSE wire_niOill_o; + wire_nilOil_dataout <= nili1O WHEN n1i010l = '1' ELSE wire_niOilO_o; + wire_nilOiO_dataout <= nili0i WHEN n1i010l = '1' ELSE wire_niOiOi_o; + wire_nilOl_dataout <= (NOT pudi(9)) WHEN nO = '1' ELSE pudi(9); + wire_nilOli_dataout <= nili0l WHEN n1i010l = '1' ELSE wire_niOiOl_o; + wire_nilOll_dataout <= nili0O WHEN n1i010l = '1' ELSE wire_niOiOO_o; + wire_nilOlO_dataout <= niliii WHEN n1i010l = '1' ELSE wire_niOl1i_o; + wire_nilOO_dataout <= wire_nl0li_dataout WHEN n1iii1l = '1' ELSE wire_nl10l_dataout; + wire_nilOOi_dataout <= niliil WHEN n1i010l = '1' ELSE wire_niOl1l_o; + wire_nilOOl_dataout <= niliiO WHEN n1i010l = '1' ELSE wire_niOl1O_o; + wire_nilOOO_dataout <= nilili WHEN n1i010l = '1' ELSE wire_niOl0i_dataout; + wire_niO0i_dataout <= wire_nl0Ol_dataout WHEN n1iii1l = '1' ELSE wire_nl1iO_dataout; + wire_niO0l_dataout <= wire_nl0OO_dataout WHEN n1iii1l = '1' ELSE wire_nl1li_dataout; + wire_niO0O_dataout <= wire_nli1i_dataout WHEN n1iii1l = '1' ELSE wire_nl1ll_dataout; + wire_niO10l_dataout <= wire_niiiOO_dataout WHEN n1i01ii = '1' ELSE nilill; + wire_niO10O_dataout <= wire_niil1i_dataout WHEN n1i01ii = '1' ELSE nililO; + wire_niO11i_dataout <= wire_niOl0l_dataout AND NOT(n1i010l); + wire_niO1i_dataout <= wire_nl0ll_dataout WHEN n1iii1l = '1' ELSE wire_nl10O_dataout; + wire_niO1ii_dataout <= wire_niil1l_dataout WHEN n1i01ii = '1' ELSE niliOi; + wire_niO1il_dataout <= wire_niil1O_dataout WHEN n1i01ii = '1' ELSE niliOl; + wire_niO1iO_dataout <= wire_niil0i_dataout WHEN n1i01ii = '1' ELSE niliOO; + wire_niO1l_dataout <= wire_nl0lO_dataout WHEN n1iii1l = '1' ELSE wire_nl1ii_dataout; + wire_niO1li_dataout <= wire_niil0l_dataout WHEN n1i01ii = '1' ELSE nill1i; + wire_niO1ll_dataout <= wire_niil0O_dataout WHEN n1i01ii = '1' ELSE nill1l; + wire_niO1lO_dataout <= wire_niilii_dataout WHEN n1i01ii = '1' ELSE nill1O; + wire_niO1O_dataout <= wire_nl0Oi_dataout WHEN n1iii1l = '1' ELSE wire_nl1il_dataout; + wire_niOi_dataout <= wire_nl1l00i_dataout AND wa_6g_en; + wire_niOi0i_dataout <= niOlOO WHEN nill0l = '1' ELSE niOllO; + wire_niOi0l_dataout <= niOlOl WHEN nill0l = '1' ELSE niOlOi; + wire_niOi0O_dataout <= niOlOi WHEN nill0l = '1' ELSE niOlOl; + wire_niOi1i_dataout <= niOO1O WHEN nill0l = '1' ELSE niOlil; + wire_niOi1l_dataout <= niOO1l WHEN nill0l = '1' ELSE niOlli; + wire_niOi1O_dataout <= niOO1i WHEN nill0l = '1' ELSE niOlll; + wire_niOii_dataout <= wire_nli1l_dataout WHEN n1iii1l = '1' ELSE wire_nl1lO_dataout; + wire_niOiii_dataout <= niOllO WHEN nill0l = '1' ELSE niOlOO; + wire_niOiil_dataout <= niOlll WHEN nill0l = '1' ELSE niOO1i; + wire_niOiiO_dataout <= niOlli WHEN nill0l = '1' ELSE niOO1l; + wire_niOil_dataout <= wire_nli1O_dataout WHEN n1iii1l = '1' ELSE wire_nl1Oi_dataout; + wire_niOili_dataout <= niOlil WHEN nill0l = '1' ELSE niOO1O; + wire_niOiO_dataout <= wire_nli0i_dataout WHEN n1iii1l = '1' ELSE wire_nl1Ol_dataout; + wire_niOl_dataout <= wire_nl1l00l_dataout AND wa_6g_en; + wire_niOl0i_dataout <= niOOOO WHEN n1i00Oi = '1' ELSE nl11ii; + wire_niOl0i_w_lg_w_lg_dataout1313w3182w(0) <= wire_niOl0i_w_lg_dataout1313w(0) AND wire_niOl1O_w_lg_w_lg_o1314w3181w(0); + wire_niOl0i_w_lg_w_lg_dataout1313w3202w(0) <= wire_niOl0i_w_lg_dataout1313w(0) AND n10lO0i; + wire_niOl0i_w_lg_w_lg_dataout1313w3199w(0) <= wire_niOl0i_w_lg_dataout1313w(0) AND n10lO0l; + wire_niOl0i_w_lg_w_lg_dataout1313w3221w(0) <= wire_niOl0i_w_lg_dataout1313w(0) AND n10lO1l; + wire_niOl0i_w_lg_w_lg_dataout1313w3216w(0) <= wire_niOl0i_w_lg_dataout1313w(0) AND n10lO1O; + wire_niOl0i_w_lg_w_lg_dataout1313w3018w(0) <= wire_niOl0i_w_lg_dataout1313w(0) AND n10O10i; + wire_niOl0i_w_lg_dataout3205w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_w_lg_o1314w2984w(0); + wire_niOl0i_w_lg_dataout3224w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_w_lg_o1314w3189w(0); + wire_niOl0i_w_lg_dataout3179w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o3178w(0); + wire_niOl0i_w_lg_dataout2997w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o2996w(0); + wire_niOl0i_w_lg_dataout3011w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o3010w(0); + wire_niOl0i_w_lg_dataout3227w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o3190w(0); + wire_niOl0i_w_lg_dataout3004w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o3003w(0); + wire_niOl0i_w_lg_dataout3029w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o3028w(0); + wire_niOl0i_w_lg_dataout1320w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o1319w(0); + wire_niOl0i_w_lg_dataout2981w(0) <= wire_niOl0i_dataout AND wire_niOl1O_w_lg_o2980w(0); + wire_niOl0i_w_lg_dataout3017w(0) <= wire_niOl0i_dataout AND n10O10l; + wire_niOl0i_w_lg_dataout1313w(0) <= NOT wire_niOl0i_dataout; + wire_niOl0i_w_lg_w_lg_dataout3179w3183w(0) <= wire_niOl0i_w_lg_dataout3179w(0) OR wire_niOl0i_w_lg_w_lg_dataout1313w3182w(0); + wire_niOl0i_w_lg_w_lg_dataout3017w3019w(0) <= wire_niOl0i_w_lg_dataout3017w(0) OR wire_niOl0i_w_lg_w_lg_dataout1313w3018w(0); + wire_niOl0l_dataout <= niOO0i WHEN n1i00Oi = '1' ELSE nl11il; + wire_niOl0l_w_lg_w_lg_dataout3064w3066w(0) <= wire_niOl0l_w_lg_dataout3064w(0) AND wire_niOl1O_w_lg_o3065w(0); + wire_niOl0l_w_lg_w_lg_dataout1312w3091w(0) <= wire_niOl0l_w_lg_dataout1312w(0) AND n10lOll; + wire_niOl0l_w_lg_dataout3203w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_w_lg_dataout1313w3202w(0); + wire_niOl0l_w_lg_dataout3200w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_w_lg_dataout1313w3199w(0); + wire_niOl0l_w_lg_dataout3222w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_w_lg_dataout1313w3221w(0); + wire_niOl0l_w_lg_dataout3217w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_w_lg_dataout1313w3216w(0); + wire_niOl0l_w_lg_dataout3206w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout3205w(0); + wire_niOl0l_w_lg_dataout3225w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout3224w(0); + wire_niOl0l_w_lg_dataout3012w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout3011w(0); + wire_niOl0l_w_lg_dataout3228w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout3227w(0); + wire_niOl0l_w_lg_dataout3005w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout3004w(0); + wire_niOl0l_w_lg_dataout3030w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout3029w(0); + wire_niOl0l_w_lg_dataout1321w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout1320w(0); + wire_niOl0l_w_lg_dataout2982w(0) <= wire_niOl0l_dataout AND wire_niOl0i_w_lg_dataout2981w(0); + wire_niOl0l_w_lg_dataout3064w(0) <= wire_niOl0l_dataout AND wire_niOl0i_dataout; + wire_niOl0l_w_lg_dataout1312w(0) <= NOT wire_niOl0l_dataout; + wire_niOl0l_w_lg_dataout3061w(0) <= wire_niOl0l_dataout OR wire_niOl0i_dataout; + wire_niOli_dataout <= wire_nli0l_dataout WHEN n1iii1l = '1' ELSE wire_nl1OO_dataout; + wire_niOll_dataout <= wire_nli0O_dataout WHEN n1iii1l = '1' ELSE wire_nl01i_dataout; + wire_niOlO_dataout <= wire_nliii_dataout WHEN n1iii1l = '1' ELSE wire_nl01l_dataout; + wire_niOO_dataout <= wire_nl1l00O_dataout AND wa_6g_en; + wire_niOOi_dataout <= wire_nliil_dataout WHEN n1iii1l = '1' ELSE wire_nl01O_dataout; + wire_niOOl_dataout <= wire_nliiO_dataout WHEN n1iii1l = '1' ELSE wire_nl00i_dataout; + wire_niOOO_dataout <= wire_nlili_dataout WHEN n1iii1l = '1' ELSE wire_nl00l_dataout; + wire_nl0000i_dataout <= wire_nl00O1i_o WHEN n111lOl = '1' ELSE wire_nl00iiO_dataout; + wire_nl0000l_dataout <= wire_nl00O1l_o WHEN n111lOl = '1' ELSE wire_nl00ili_dataout; + wire_nl0000O_dataout <= wire_nl00O1O_o WHEN n111lOl = '1' ELSE wire_nl00ill_dataout; + wire_nl0001i_dataout <= wire_nl00lOi_o WHEN n111lOl = '1' ELSE wire_nl00i0O_dataout; + wire_nl0001l_dataout <= wire_nl00lOl_o WHEN n111lOl = '1' ELSE wire_nl00iii_dataout; + wire_nl0001O_dataout <= wire_nl00lOO_o WHEN n111lOl = '1' ELSE wire_nl00iil_dataout; + wire_nl000i_dataout <= ((wire_nl_w_lg_nl1ill312w(0) AND (n1i0lll AND nlOiO1i)) OR wire_nl_w_lg_nl1ill365w(0)) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE (n1i0llO OR n1i0lll); + wire_nl000i_w_lg_dataout421w(0) <= NOT wire_nl000i_dataout; + wire_nl000ii_dataout <= wire_nl00O0i_o WHEN n111lOl = '1' ELSE wire_nl00ilO_dataout; + wire_nl000il_dataout <= wire_nl00O0l_o WHEN n111lOl = '1' ELSE wire_nl00iOi_dataout; + wire_nl000iO_dataout <= wire_nl00O0O_o WHEN n111lOl = '1' ELSE wire_nl00iOl_dataout; + wire_nl000li_dataout <= wire_nl00iOO_dataout AND NOT(n111lOl); + wire_nl000ll_dataout <= wire_nl00l1i_dataout AND NOT(n111lOl); + wire_nl000lO_dataout <= wire_nl00l1l_dataout AND NOT(n111lOl); + wire_nl000Oi_dataout <= wire_nl00l1O_dataout AND NOT(n111lOl); + wire_nl000Ol_dataout <= wire_nl00OiO_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00lii_o; + wire_nl000OO_dataout <= wire_nl00Oli_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00lil_o; + wire_nl0010i_dataout <= wire_nl0i1il_o WHEN n111lOO = '1' ELSE wire_nl000iO_dataout; + wire_nl0010l_dataout <= wire_nl0i1iO_o WHEN n111lOO = '1' ELSE wire_nl000li_dataout; + wire_nl0010O_dataout <= wire_nl0i1li_o WHEN n111lOO = '1' ELSE wire_nl000ll_dataout; + wire_nl0011i_dataout <= wire_nl0i10l_o WHEN n111lOO = '1' ELSE wire_nl0000O_dataout; + wire_nl0011l_dataout <= wire_nl0i10O_o WHEN n111lOO = '1' ELSE wire_nl000ii_dataout; + wire_nl0011O_dataout <= wire_nl0i1ii_o WHEN n111lOO = '1' ELSE wire_nl000il_dataout; + wire_nl001i_dataout <= ((wire_nl_w_lg_nl1ill312w(0) AND (n1i0liO AND nlOiO1l)) OR wire_nl_w_lg_nl1ill373w(0)) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE (n1i0lli OR n1i0liO); + wire_nl001i_w_lg_dataout415w(0) <= NOT wire_nl001i_dataout; + wire_nl001ii_dataout <= wire_nl0i1ll_o WHEN n111lOO = '1' ELSE wire_nl000lO_dataout; + wire_nl001il_dataout <= wire_nl0i1lO_o WHEN n111lOO = '1' ELSE wire_nl000Oi_dataout; + wire_nl001iO_dataout <= wire_nl00l0O_o WHEN n111lOl = '1' ELSE wire_nl000Ol_dataout; + wire_nl001li_dataout <= wire_nl00lii_o WHEN n111lOl = '1' ELSE wire_nl000OO_dataout; + wire_nl001ll_dataout <= wire_nl00lil_o WHEN n111lOl = '1' ELSE wire_nl00i1i_dataout; + wire_nl001lO_dataout <= wire_nl00liO_o WHEN n111lOl = '1' ELSE wire_nl00i1l_dataout; + wire_nl001Oi_dataout <= wire_nl00lli_o WHEN n111lOl = '1' ELSE wire_nl00i1O_dataout; + wire_nl001Ol_dataout <= wire_nl00lll_o WHEN n111lOl = '1' ELSE wire_nl00i0i_dataout; + wire_nl001OO_dataout <= wire_nl00llO_o WHEN n111lOl = '1' ELSE wire_nl00i0l_dataout; + wire_nl00i_dataout <= (NOT pudr(14)) WHEN nO = '1' ELSE pudr(14); + wire_nl00i0i_dataout <= wire_nl00OOl_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00llO_o; + wire_nl00i0l_dataout <= wire_nl00OOO_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00lOi_o; + wire_nl00i0O_dataout <= wire_nl0i11i_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00lOl_o; + wire_nl00i1i_dataout <= wire_nl00Oll_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00liO_o; + wire_nl00i1l_dataout <= wire_nl00OlO_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00lli_o; + wire_nl00i1O_dataout <= wire_nl00OOi_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00lll_o; + wire_nl00ii_dataout <= ((wire_nl_w_lg_nl1ill312w(0) AND (n1i0lOO AND nlOilOO)) OR wire_nl_w_lg_nl1ill357w(0)) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE ((n1i0O1i OR n1i0lOO) OR (NOT (n1i0lOi48 XOR n1i0lOi47))); + wire_nl00ii_w_lg_dataout428w(0) <= NOT wire_nl00ii_dataout; + wire_nl00iii_dataout <= wire_nl0i11l_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00lOO_o; + wire_nl00iil_dataout <= wire_nl0i11O_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00O1i_o; + wire_nl00iiO_dataout <= wire_nl0i10i_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00O1l_o; + wire_nl00ili_dataout <= wire_nl0i10l_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00O1O_o; + wire_nl00ill_dataout <= wire_nl0i10O_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00O0i_o; + wire_nl00ilO_dataout <= wire_nl0i1ii_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00O0l_o; + wire_nl00iOi_dataout <= wire_nl0i1il_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00O0O_o; + wire_nl00iOl_dataout <= wire_nl0i1iO_o WHEN (NOT comp_pat_size(0)) = '1' ELSE wire_nl00l0i_o; + wire_nl00iOO_dataout <= wire_nl0i1li_o AND (NOT comp_pat_size(0)); + wire_nl00l_dataout <= (NOT pudr(15)) WHEN nO = '1' ELSE pudr(15); + wire_nl00l1i_dataout <= wire_nl0i1ll_o AND (NOT comp_pat_size(0)); + wire_nl00l1l_dataout <= wire_nl0i1lO_o AND (NOT comp_pat_size(0)); + wire_nl00l1O_dataout <= wire_nl00l0l_o AND (NOT comp_pat_size(0)); + wire_nl00li_dataout <= ((wire_nl_w_lg_nl1ill312w(0) AND (n1i0O0O AND nlOilOl)) OR (wire_nl_w_lg_nl1ill342w(0) AND (n1i0O1l46 XOR n1i0O1l45))) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE (n1i0Oii OR n1i0O0O); + wire_nl00li_w_lg_dataout436w(0) <= NOT wire_nl00li_dataout; + wire_nl00O_dataout <= (NOT pudr(16)) WHEN nO = '1' ELSE pudr(16); + wire_nl00Oi_dataout <= ((((wire_nl_w_lg_nl1ill312w(0) AND ((n1ii11i AND nlOiilO) AND (n1i0OOl36 XOR n1i0OOl35))) AND (n1i0OlO38 XOR n1i0OlO37)) OR wire_nl_w_lg_nl1ill327w(0)) OR (NOT (n1i0Oil42 XOR n1i0Oil41))) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE (n1ii11l OR n1ii11i); + wire_nl00Oi_w_lg_dataout1914w(0) <= wire_nl00Oi_dataout AND wire_nl00li_w_lg_dataout436w(0); + wire_nl010l_dataout <= (n1i0l1l OR n1i0l1i) AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_nl010l_w_lg_dataout401w(0) <= NOT wire_nl010l_dataout; + wire_nl011i_dataout <= nl10ll WHEN autobytealign_dis = '1' ELSE nl1lli; + wire_nl011l_dataout <= nl10Oi WHEN autobytealign_dis = '1' ELSE nl1llO; + wire_nl011O_dataout <= (n1i0iOO OR n1i0iOl) AND NOT(wire_w_lg_w_pmadwidth_range175w219w(0)); + wire_nl011O_w_lg_dataout1922w(0) <= NOT wire_nl011O_dataout; + wire_nl011O_w_lg_dataout446w(0) <= wire_nl011O_dataout OR wire_w_lg_n1i0iOi445w(0); + wire_nl01i_dataout <= (NOT pudr(11)) WHEN nO = '1' ELSE pudr(11); + wire_nl01ii_dataout <= ((wire_nl_w_lg_nl1ill312w(0) AND (n1i0l1O AND nlOiO0l)) OR wire_nl_w_lg_nl1ill397w(0)) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE (n1i0l0i OR n1i0l1O); + wire_nl01ii_w_lg_dataout403w(0) <= NOT wire_nl01ii_dataout; + wire_nl01l_dataout <= (NOT pudr(12)) WHEN nO = '1' ELSE pudr(12); + wire_nl01li_dataout <= ((wire_nl_w_lg_nl1ill312w(0) AND (n1i0l0l AND nlOiO0i)) OR wire_nl_w_lg_nl1ill389w(0)) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE (n1i0l0O OR n1i0l0l); + wire_nl01li_w_lg_dataout406w(0) <= NOT wire_nl01li_dataout; + wire_nl01O_dataout <= (NOT pudr(13)) WHEN nO = '1' ELSE pudr(13); + wire_nl01O0i_dataout <= wire_nl00Oil_o WHEN n111lOO = '1' ELSE wire_nl001iO_dataout; + wire_nl01O0l_dataout <= wire_nl00OiO_o WHEN n111lOO = '1' ELSE wire_nl001li_dataout; + wire_nl01O0O_dataout <= wire_nl00Oli_o WHEN n111lOO = '1' ELSE wire_nl001ll_dataout; + wire_nl01Oi_dataout <= ((wire_nl_w_lg_nl1ill312w(0) AND (n1i0lii AND nlOiO1O)) OR wire_nl_w_lg_nl1ill381w(0)) WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE (n1i0lil OR n1i0lii); + wire_nl01Oi_w_lg_dataout410w(0) <= NOT wire_nl01Oi_dataout; + wire_nl01Oii_dataout <= wire_nl00Oll_o WHEN n111lOO = '1' ELSE wire_nl001lO_dataout; + wire_nl01Oil_dataout <= wire_nl00OlO_o WHEN n111lOO = '1' ELSE wire_nl001Oi_dataout; + wire_nl01OiO_dataout <= wire_nl00OOi_o WHEN n111lOO = '1' ELSE wire_nl001Ol_dataout; + wire_nl01Oli_dataout <= wire_nl00OOl_o WHEN n111lOO = '1' ELSE wire_nl001OO_dataout; + wire_nl01Oll_dataout <= wire_nl00OOO_o WHEN n111lOO = '1' ELSE wire_nl0001i_dataout; + wire_nl01OlO_dataout <= wire_nl0i11i_o WHEN n111lOO = '1' ELSE wire_nl0001l_dataout; + wire_nl01OOi_dataout <= wire_nl0i11l_o WHEN n111lOO = '1' ELSE wire_nl0001O_dataout; + wire_nl01OOl_dataout <= wire_nl0i11O_o WHEN n111lOO = '1' ELSE wire_nl0000i_dataout; + wire_nl01OOO_dataout <= wire_nl0i10i_o WHEN n111lOO = '1' ELSE wire_nl0000l_dataout; + wire_nl0i_dataout <= wire_nl1l0li_dataout AND wa_6g_en; + wire_nl0i00i_dataout <= wire_nl0i0iO_dataout WHEN n111O1l = '1' ELSE nl0101O; + wire_nl0i00l_dataout <= wire_nl0i0li_dataout WHEN n111O1l = '1' ELSE nl0100i; + wire_nl0i00O_dataout <= wire_nl0i0ll_dataout WHEN n111O1l = '1' ELSE nl0100l; + wire_nl0i01i_dataout <= n110ill WHEN n111O1O = '1' ELSE wire_nl0i00O_dataout; + wire_nl0i01l_dataout <= n110ilO WHEN n111O1O = '1' ELSE wire_nl0i0ii_dataout; + wire_nl0i01O_dataout <= n110iOi WHEN n111O1O = '1' ELSE wire_nl0i0il_dataout; + wire_nl0i0i_dataout <= nliO0O WHEN n1ii11O = '1' ELSE wire_nl0iOl_dataout; + wire_nl0i0ii_dataout <= wire_nl0i0lO_dataout WHEN n111O1l = '1' ELSE nl0100O; + wire_nl0i0il_dataout <= wire_nl0i0Oi_dataout WHEN n111O1l = '1' ELSE nl010ii; + wire_nl0i0iO_dataout <= wire_nl0i0Ol_o AND NOT(n111O1i); + wire_nl0i0l_dataout <= nliOii WHEN n1ii11O = '1' ELSE wire_nl0iOO_dataout; + wire_nl0i0li_dataout <= wire_nl0i0OO_o AND NOT(n111O1i); + wire_nl0i0ll_dataout <= wire_nl0ii1i_o AND NOT(n111O1i); + wire_nl0i0lO_dataout <= wire_nl0ii1l_o AND NOT(n111O1i); + wire_nl0i0O_dataout <= nliOil WHEN n1ii11O = '1' ELSE wire_nl0l1i_dataout; + wire_nl0i0Oi_dataout <= wire_nl0ii1O_o AND NOT(n111O1i); + wire_nl0i1i_dataout <= nliO1O WHEN n1ii11O = '1' ELSE wire_nl0ill_dataout; + wire_nl0i1l_dataout <= nliO0i WHEN n1ii11O = '1' ELSE wire_nl0ilO_dataout; + wire_nl0i1O_dataout <= nliO0l WHEN n1ii11O = '1' ELSE wire_nl0iOi_dataout; + wire_nl0i1Ol_dataout <= wire_w_lg_n110iiO5931w(0) WHEN n111O1O = '1' ELSE wire_nl0i00i_dataout; + wire_nl0i1OO_dataout <= wire_w_lg_n110ili5930w(0) WHEN n111O1O = '1' ELSE wire_nl0i00l_dataout; + wire_nl0ii_dataout <= (NOT pudr(17)) WHEN nO = '1' ELSE pudr(17); + wire_nl0ii0i_dataout <= wire_nl0iiiO_dataout WHEN nlli00i = '1' ELSE nl0101O; + wire_nl0ii0l_dataout <= wire_nl0iili_dataout WHEN nlli00i = '1' ELSE nl0100i; + wire_nl0ii0O_dataout <= wire_nl0iill_dataout WHEN nlli00i = '1' ELSE nl0100l; + wire_nl0iii_dataout <= nliOiO WHEN n1ii11O = '1' ELSE wire_nl0l1l_dataout; + wire_nl0iiii_dataout <= wire_nl0iilO_dataout WHEN nlli00i = '1' ELSE nl0100O; + wire_nl0iiil_dataout <= wire_nl0iiOi_dataout WHEN nlli00i = '1' ELSE nl010ii; + wire_nl0iiiO_dataout <= wire_nl0iiOl_o(0) AND NOT(wire_nl0iiOO_o); + wire_nl0iil_dataout <= wire_nl0l1O_dataout AND NOT(n1ii11O); + wire_nl0iili_dataout <= wire_nl0iiOl_o(1) AND NOT(wire_nl0iiOO_o); + wire_nl0iill_dataout <= wire_nl0iiOl_o(2) AND NOT(wire_nl0iiOO_o); + wire_nl0iilO_dataout <= wire_nl0iiOl_o(3) AND NOT(wire_nl0iiOO_o); + wire_nl0iiO_dataout <= wire_nl0l0i_dataout AND NOT(n1ii11O); + wire_nl0iiOi_dataout <= wire_nl0iiOl_o(4) AND NOT(wire_nl0iiOO_o); + wire_nl0il_dataout <= (NOT pudr(18)) WHEN nO = '1' ELSE pudr(18); + wire_nl0il0i_dataout <= wire_nl0iliO_dataout WHEN nlli00i = '1' ELSE nl0100O; + wire_nl0il0l_dataout <= wire_nl0illi_dataout WHEN nlli00i = '1' ELSE nl010ii; + wire_nl0il0O_dataout <= wire_nl0iiOl_o(0) AND NOT(wire_nl0illl_o); + wire_nl0il1i_dataout <= wire_nl0il0O_dataout WHEN nlli00i = '1' ELSE nl0101O; + wire_nl0il1l_dataout <= wire_nl0ilii_dataout WHEN nlli00i = '1' ELSE nl0100i; + wire_nl0il1O_dataout <= wire_nl0ilil_dataout WHEN nlli00i = '1' ELSE nl0100l; + wire_nl0ili_dataout <= wire_nl0l0l_dataout AND NOT(n1ii11O); + wire_nl0ilii_dataout <= wire_nl0iiOl_o(1) AND NOT(wire_nl0illl_o); + wire_nl0ilil_dataout <= wire_nl0iiOl_o(2) AND NOT(wire_nl0illl_o); + wire_nl0iliO_dataout <= wire_nl0iiOl_o(3) AND NOT(wire_nl0illl_o); + wire_nl0ill_dataout <= nliO1O AND NOT(n1ii10i); + wire_nl0illi_dataout <= wire_nl0iiOl_o(4) AND NOT(wire_nl0illl_o); + wire_nl0illO_dataout <= wire_nl0iO1l_dataout WHEN nlli00i = '1' ELSE nl0101O; + wire_nl0ilO_dataout <= nliO0i AND NOT(n1ii10i); + wire_nl0ilOi_dataout <= wire_nl0iO1O_dataout WHEN nlli00i = '1' ELSE nl0100i; + wire_nl0ilOl_dataout <= wire_nl0iO0i_dataout WHEN nlli00i = '1' ELSE nl0100l; + wire_nl0ilOO_dataout <= wire_nl0iO0l_dataout WHEN nlli00i = '1' ELSE nl0100O; + wire_nl0iO_dataout <= (NOT pudr(19)) WHEN nO = '1' ELSE pudr(19); + wire_nl0iO0i_dataout <= wire_nl0iiOl_o(2) AND NOT(wire_nl0iOii_o); + wire_nl0iO0l_dataout <= wire_nl0iiOl_o(3) AND NOT(wire_nl0iOii_o); + wire_nl0iO0O_dataout <= wire_nl0iiOl_o(4) AND NOT(wire_nl0iOii_o); + wire_nl0iO1i_dataout <= wire_nl0iO0O_dataout WHEN nlli00i = '1' ELSE nl010ii; + wire_nl0iO1l_dataout <= wire_nl0iiOl_o(0) AND NOT(wire_nl0iOii_o); + wire_nl0iO1O_dataout <= wire_nl0iiOl_o(1) AND NOT(wire_nl0iOii_o); + wire_nl0iOi_dataout <= nliO0l AND NOT(n1ii10i); + wire_nl0iOil_dataout <= wire_nl0iOOi_dataout WHEN nlli00i = '1' ELSE nl0101O; + wire_nl0iOiO_dataout <= wire_nl0iOOl_dataout WHEN nlli00i = '1' ELSE nl0100i; + wire_nl0iOl_dataout <= nliO0O AND NOT(n1ii10i); + wire_nl0iOli_dataout <= wire_nl0iOOO_dataout WHEN nlli00i = '1' ELSE nl0100l; + wire_nl0iOll_dataout <= wire_nl0l11i_dataout WHEN nlli00i = '1' ELSE nl0100O; + wire_nl0iOlO_dataout <= wire_nl0l11l_dataout WHEN nlli00i = '1' ELSE nl010ii; + wire_nl0iOO_dataout <= nliOii AND NOT(n1ii10i); + wire_nl0iOOi_dataout <= wire_nl0iiOl_o(0) AND NOT(wire_nl0l11O_o); + wire_nl0iOOl_dataout <= wire_nl0iiOl_o(1) AND NOT(wire_nl0l11O_o); + wire_nl0iOOO_dataout <= wire_nl0iiOl_o(2) AND NOT(wire_nl0l11O_o); + wire_nl0l_dataout <= wire_nl1l0ll_dataout AND wa_6g_en; + wire_nl0l00i_dataout <= nl1OiiO WHEN n111O0i = '1' ELSE nl01O1O; + wire_nl0l01i_dataout <= nl1Oiil WHEN (n110i0l OR n110i0i) = '1' ELSE wire_nl0l01l_dataout; + wire_nl0l01l_dataout <= nl1liii AND n111O0i; + wire_nl0l0i_dataout <= nliOll AND NOT(n1ii10i); + wire_nl0l0ii_dataout <= ((n1100ll OR nl1Olli) OR (n1iiiOi AND nl1Ol1l)) WHEN comp_pat_size(0) = '1' ELSE n11010O; + wire_nl0l0il_dataout <= ((n11000l OR nl1Olil) OR (n1iiiOi AND nl1OiOO)) WHEN comp_pat_size(0) = '1' ELSE wire_nl0l0iO_dataout; + wire_nl0l0iO_dataout <= n11010O WHEN n111O0l = '1' ELSE ((n1101il OR nl1Ol0i) OR (n1iiiOi AND nl1Oill)); + wire_nl0l0l_dataout <= nliOlO AND NOT(n1ii10i); + wire_nl0l0ll_dataout <= nl01O1O AND NOT(wire_nll1llO_o); + wire_nl0l0lO_dataout <= nl1Oiil AND NOT(wire_nll1llO_o); + wire_nl0l0O_dataout <= nliO0i WHEN n1ii11O = '1' ELSE wire_nl0ilO_dataout; + wire_nl0l11i_dataout <= wire_nl0iiOl_o(3) AND NOT(wire_nl0l11O_o); + wire_nl0l11l_dataout <= wire_nl0iiOl_o(4) AND NOT(wire_nl0l11O_o); + wire_nl0l1i_dataout <= nliOil AND NOT(n1ii10i); + wire_nl0l1ii_dataout <= wire_nl0l1il_dataout WHEN sync_sm_dis = '1' ELSE wire_nl0l00i_dataout; + wire_nl0l1il_dataout <= nl1Oiil AND ((n110iil OR n110iii) OR n110i0O); + wire_nl0l1l_dataout <= nliOiO AND NOT(n1ii10i); + wire_nl0l1lO_dataout <= ((n1100Ol OR nl1OliO) OR (n1iiiOi AND nl1Ol1i)) WHEN comp_pat_size(0) = '1' ELSE n1101ii; + wire_nl0l1O_dataout <= nliOli AND NOT(n1ii10i); + wire_nl0l1Oi_dataout <= ((n1100il OR nl1Olii) OR (n1iiiOi AND nl1OiOl)) WHEN comp_pat_size(0) = '1' ELSE wire_nl0l1Ol_dataout; + wire_nl0l1Ol_dataout <= n1101ii WHEN n111O0l = '1' ELSE ((n1101ll OR nl1Ol1O) OR (n1iiiOi AND nl1Oili)); + wire_nl0l1OO_dataout <= wire_nl0l01i_dataout WHEN sync_sm_dis = '1' ELSE wire_nl0l00i_dataout; + wire_nl0li_dataout <= (NOT pudr(0)) WHEN nO = '1' ELSE pudr(0); + wire_nl0lii_dataout <= nliO0l WHEN n1ii11O = '1' ELSE wire_nl0iOi_dataout; + wire_nl0lil_dataout <= nliO0O WHEN n1ii11O = '1' ELSE wire_nl0iOl_dataout; + wire_nl0liO_dataout <= nliOii WHEN n1ii11O = '1' ELSE wire_nl0iOO_dataout; + wire_nl0ll_dataout <= (NOT pudr(1)) WHEN nO = '1' ELSE pudr(1); + wire_nl0lli_dataout <= nliOil WHEN n1ii11O = '1' ELSE wire_nl0l1i_dataout; + wire_nl0lll_dataout <= nliOiO WHEN n1ii11O = '1' ELSE wire_nl0l1l_dataout; + wire_nl0llO_dataout <= nliOli WHEN n1ii11O = '1' ELSE wire_nl0l1O_dataout; + wire_nl0lO_dataout <= (NOT pudr(2)) WHEN nO = '1' ELSE pudr(2); + wire_nl0lOi_dataout <= wire_nl0l0i_dataout AND NOT(n1ii11O); + wire_nl0lOl_dataout <= wire_nl0l0l_dataout AND NOT(n1ii11O); + wire_nl0lOO_dataout <= wire_nl0O1i_dataout AND NOT(n1ii11O); + wire_nl0O_dataout <= wire_nl1l1ll_dataout AND wa_6g_en; + wire_nl0O0i_dataout <= wire_nl0O0l_dataout AND NOT(n1ii11O); + wire_nl0O0l_dataout <= nliOOl AND NOT(n1ii10i); + wire_nl0O0O_dataout <= nliOOi AND NOT(n1ii11O); + wire_nl0O1i_dataout <= nliOOi AND NOT(n1ii10i); + wire_nl0O1l_dataout <= nliOlO AND NOT(n1ii11O); + wire_nl0O1O_dataout <= wire_nl0O1i_dataout AND NOT(n1ii11O); + wire_nl0Oi_dataout <= (NOT pudr(3)) WHEN nO = '1' ELSE pudr(3); + wire_nl0Oii_dataout <= wire_nl0O0l_dataout AND NOT(n1ii11O); + wire_nl0Oil_dataout <= wire_nl0OiO_dataout AND NOT(n1ii11O); + wire_nl0OiO_dataout <= nliOOO AND NOT(n1ii10i); + wire_nl0Ol_dataout <= (NOT pudr(4)) WHEN nO = '1' ELSE pudr(4); + wire_nl0Oli_dataout <= nliOOl AND NOT(n1ii11O); + wire_nl0Oll_dataout <= wire_nl0OiO_dataout AND NOT(n1ii11O); + wire_nl0OlO_dataout <= wire_nl0OOi_dataout AND NOT(n1ii11O); + wire_nl0OO_dataout <= (NOT pudr(5)) WHEN nO = '1' ELSE pudr(5); + wire_nl0OOi_dataout <= nll11i AND NOT(n1ii10i); + wire_nl0OOl_dataout <= nliOOO AND NOT(n1ii11O); + wire_nl0OOO_dataout <= wire_nl0OOi_dataout AND NOT(n1ii11O); + wire_nl10i_dataout <= wire_nl0iO_dataout AND NOT(n1iii1l); + wire_nl10l_dataout <= (NOT pudr(0)) WHEN nO = '1' ELSE pudr(0); + wire_nl10O_dataout <= (NOT pudr(1)) WHEN nO = '1' ELSE pudr(1); + wire_nl10OO_dataout <= wire_nl1i0i_dataout OR n1i0i1l; + wire_nl11i_dataout <= wire_nl00O_dataout AND NOT(n1iii1l); + wire_nl11l_dataout <= wire_nl0ii_dataout AND NOT(n1iii1l); + wire_nl11O_dataout <= wire_nl0il_dataout AND NOT(n1iii1l); + wire_nl1i_dataout <= wire_nl1l0ii_dataout AND wa_6g_en; + wire_nl1i0i_dataout <= wire_nl1iil_o(1) OR n1i0i1i; + wire_nl1i0l_dataout <= wire_nl1iil_o(2) OR n1i0i1i; + wire_nl1i0O_dataout <= wire_nl1iil_o(3) OR n1i0i1i; + wire_nl1i1i_dataout <= wire_nl1i0l_dataout AND NOT(n1i0i1l); + wire_nl1i1l_dataout <= wire_nl1i0O_dataout AND NOT(n1i0i1l); + wire_nl1i1O_dataout <= wire_nl1iii_dataout OR n1i0i1l; + wire_nl1ii_dataout <= (NOT pudr(2)) WHEN nO = '1' ELSE pudr(2); + wire_nl1iii_dataout <= wire_nl1iil_o(4) AND NOT(n1i0i1i); + wire_nl1il_dataout <= (NOT pudr(3)) WHEN nO = '1' ELSE pudr(3); + wire_nl1iO_dataout <= (NOT pudr(4)) WHEN nO = '1' ELSE pudr(4); + wire_nl1iOil_dataout <= nl1OO0O AND NOT(rrxpcsbypass_en); + wire_nl1iOiO_dataout <= nl1OOii AND NOT(rrxpcsbypass_en); + wire_nl1iOli_dataout <= nl1OOil AND NOT(rrxpcsbypass_en); + wire_nl1iOll_dataout <= nl1OOiO AND NOT(rrxpcsbypass_en); + wire_nl1iOlO_dataout <= nl1OOli AND NOT(rrxpcsbypass_en); + wire_nl1iOOi_dataout <= nl1OOll AND NOT(rrxpcsbypass_en); + wire_nl1iOOl_dataout <= nll0OOl WHEN rrxpcsbypass_en = '1' ELSE nl1Olll; + wire_nl1iOOO_dataout <= nll0OOO WHEN rrxpcsbypass_en = '1' ELSE nl1OllO; + wire_nl1l_dataout <= wire_nl1l0il_dataout AND wa_6g_en; + wire_nl1l00i_dataout <= wire_nl1l0Ol_dataout WHEN rrxpcsbypass_en = '1' ELSE nl1OOOl; + wire_nl1l00l_dataout <= wire_nl1l0OO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl1OOOO; + wire_nl1l00O_dataout <= wire_nl1li1i_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0111i; + wire_nl1l01i_dataout <= nl011lO AND NOT(rrxpcsbypass_en); + wire_nl1l01l_dataout <= wire_nl1l0lO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl1OOlO; + wire_nl1l01O_dataout <= wire_nl1l0Oi_dataout WHEN rrxpcsbypass_en = '1' ELSE nl1OOOi; + wire_nl1l0i_dataout <= nlli0l OR wire_nllliil_w_lg_dataout283w(0); + wire_nl1l0ii_dataout <= wire_nl1li1l_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0111l; + wire_nl1l0il_dataout <= wire_nl1li1O_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0111O; + wire_nl1l0iO_dataout <= wire_nl1li0i_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0110i; + wire_nl1l0l_dataout <= nlli0O OR wire_nllliil_w_lg_dataout283w(0); + wire_nl1l0li_dataout <= wire_nl1li0l_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0110l; + wire_nl1l0ll_dataout <= wire_nl1li0O_dataout WHEN rrxpcsbypass_en = '1' ELSE nl0110O; + wire_nl1l0lO_dataout <= nlli1ii WHEN n111llO = '1' ELSE nlli1iO; + wire_nl1l0O_dataout <= nlliii OR wire_nllliil_w_lg_dataout283w(0); + wire_nl1l0Oi_dataout <= nlli1il WHEN n111llO = '1' ELSE nlli1li; + wire_nl1l0Ol_dataout <= nlli1iO WHEN n111llO = '1' ELSE nlli1ll; + wire_nl1l0OO_dataout <= nlli1li WHEN n111llO = '1' ELSE nlli1lO; + wire_nl1l10i_dataout <= nlli10i WHEN rrxpcsbypass_en = '1' ELSE nl1OO1i; + wire_nl1l10l_dataout <= nlli10l WHEN rrxpcsbypass_en = '1' ELSE nl1OO1l; + wire_nl1l10O_dataout <= nlli10O WHEN rrxpcsbypass_en = '1' ELSE nl1OO1O; + wire_nl1l11i_dataout <= nlli11i WHEN rrxpcsbypass_en = '1' ELSE nl1OlOi; + wire_nl1l11l_dataout <= nlli11l WHEN rrxpcsbypass_en = '1' ELSE nl1OlOl; + wire_nl1l11O_dataout <= nlli11O WHEN rrxpcsbypass_en = '1' ELSE nl1OlOO; + wire_nl1l1ii_dataout <= wire_nl1l1iO_dataout WHEN rrxpcsbypass_en = '1' ELSE nl1OO0i; + wire_nl1l1il_dataout <= wire_nl1l1li_dataout WHEN rrxpcsbypass_en = '1' ELSE nl1OO0l; + wire_nl1l1iO_dataout <= nlli1ii AND NOT(n111llO); + wire_nl1l1li_dataout <= nlli1il AND NOT(n111llO); + wire_nl1l1ll_dataout <= nl011ii AND NOT(rrxpcsbypass_en); + wire_nl1l1lO_dataout <= nl011il AND NOT(rrxpcsbypass_en); + wire_nl1l1O_dataout <= nll1il OR wire_nllliil_w_lg_dataout283w(0); + wire_nl1l1Oi_dataout <= nl011iO AND NOT(rrxpcsbypass_en); + wire_nl1l1Ol_dataout <= nl011li AND NOT(rrxpcsbypass_en); + wire_nl1l1OO_dataout <= nl011ll AND NOT(rrxpcsbypass_en); + wire_nl1li_dataout <= (NOT pudr(5)) WHEN nO = '1' ELSE pudr(5); + wire_nl1li0i_dataout <= nlli1Ol WHEN n111llO = '1' ELSE nlli01i; + wire_nl1li0l_dataout <= nlli01l AND NOT(n111llO); + wire_nl1li0O_dataout <= nlli01O AND NOT(n111llO); + wire_nl1li1i_dataout <= nlli1ll WHEN n111llO = '1' ELSE nlli1Oi; + wire_nl1li1l_dataout <= nlli1lO WHEN n111llO = '1' ELSE nlli1Ol; + wire_nl1li1O_dataout <= nlli1Oi WHEN n111llO = '1' ELSE nlli1OO; + wire_nl1ll_dataout <= (NOT pudr(6)) WHEN nO = '1' ELSE pudr(6); + wire_nl1lO_dataout <= (NOT pudr(7)) WHEN nO = '1' ELSE pudr(7); + wire_nl1O_dataout <= wire_nl1l0iO_dataout AND wa_6g_en; + wire_nl1O00l_dataout <= nl01lii WHEN nlli0li = '1' ELSE nl01iOi; + wire_nl1O00O_dataout <= nl01l0O WHEN nlli0li = '1' ELSE nl01iOl; + wire_nl1O0ii_dataout <= nl01l0l WHEN nlli0li = '1' ELSE nl01iOO; + wire_nl1O0il_dataout <= nl01l0i WHEN nlli0li = '1' ELSE nl01l1i; + wire_nl1O0iO_dataout <= nl01l1O WHEN nlli0li = '1' ELSE nl01l1l; + wire_nl1O0li_dataout <= nl01l1l WHEN nlli0li = '1' ELSE nl01l1O; + wire_nl1O0ll_dataout <= nl01l1i WHEN nlli0li = '1' ELSE nl01l0i; + wire_nl1O0lO_dataout <= nl01iOO WHEN nlli0li = '1' ELSE nl01l0l; + wire_nl1O0Oi_dataout <= nl01iOl WHEN nlli0li = '1' ELSE nl01l0O; + wire_nl1O0Ol_dataout <= nl01iOi WHEN nlli0li = '1' ELSE nl01lii; + wire_nl1O0OO_dataout <= nl01l0l WHEN nlli0li = '1' ELSE nl01iOi; + wire_nl1Oi_dataout <= (NOT pudr(8)) WHEN nO = '1' ELSE pudr(8); + wire_nl1Oi0i_dataout <= nl01l1i WHEN nlli0li = '1' ELSE nl01l1l; + wire_nl1Oi0l_dataout <= nl01iOO WHEN nlli0li = '1' ELSE nl01l1O; + wire_nl1Oi0O_dataout <= nl01iOl WHEN nlli0li = '1' ELSE nl01l0i; + wire_nl1Oi1i_dataout <= nl01l0i WHEN nlli0li = '1' ELSE nl01iOl; + wire_nl1Oi1l_dataout <= nl01l1O WHEN nlli0li = '1' ELSE nl01iOO; + wire_nl1Oi1O_dataout <= nl01l1l WHEN nlli0li = '1' ELSE nl01l1i; + wire_nl1Oiii_dataout <= nl01iOi WHEN nlli0li = '1' ELSE nl01l0l; + wire_nl1Ol_dataout <= (NOT pudr(9)) WHEN nO = '1' ELSE pudr(9); + wire_nl1OO_dataout <= (NOT pudr(10)) WHEN nO = '1' ELSE pudr(10); + wire_nl1OOl_dataout <= nl10il WHEN autobytealign_dis = '1' ELSE nl1lil; + wire_nl1OOO_dataout <= nl10li WHEN autobytealign_dis = '1' ELSE nl1liO; + wire_nli00i_dataout <= (NOT comp_pat(0)) WHEN n1ii11O = '1' ELSE wire_nli0Ol_dataout; + wire_nli00l_dataout <= (NOT comp_pat(1)) WHEN n1ii11O = '1' ELSE wire_nli0OO_dataout; + wire_nli00O_dataout <= (NOT comp_pat(2)) WHEN n1ii11O = '1' ELSE wire_nlii1i_dataout; + wire_nli01i_dataout <= wire_nli1Ol_dataout AND NOT(n1ii11O); + wire_nli01l_dataout <= wire_nli01O_dataout AND NOT(n1ii11O); + wire_nli01O_dataout <= nll1ii AND NOT(n1ii10i); + wire_nli0i_dataout <= (NOT pudr(11)) WHEN nO = '1' ELSE pudr(11); + wire_nli0ii_dataout <= (NOT comp_pat(3)) WHEN n1ii11O = '1' ELSE wire_nlii1l_dataout; + wire_nli0il_dataout <= (NOT comp_pat(4)) WHEN n1ii11O = '1' ELSE wire_nlii1O_dataout; + wire_nli0iO_dataout <= (NOT comp_pat(5)) WHEN n1ii11O = '1' ELSE wire_nlii0i_dataout; + wire_nli0l_dataout <= (NOT pudr(12)) WHEN nO = '1' ELSE pudr(12); + wire_nli0li_dataout <= (NOT comp_pat(6)) WHEN n1ii11O = '1' ELSE wire_nlii0l_dataout; + wire_nli0ll_dataout <= wire_nlii0O_dataout AND NOT(n1ii11O); + wire_nli0lO_dataout <= wire_nliiii_dataout AND NOT(n1ii11O); + wire_nli0O_dataout <= (NOT pudr(13)) WHEN nO = '1' ELSE pudr(13); + wire_nli0Oi_dataout <= wire_nliiil_dataout AND NOT(n1ii11O); + wire_nli0Ol_dataout <= comp_pat(8) WHEN n1ii10i = '1' ELSE (NOT comp_pat(0)); + wire_nli0OO_dataout <= comp_pat(9) WHEN n1ii10i = '1' ELSE (NOT comp_pat(1)); + wire_nli10i_dataout <= wire_nli11l_dataout AND NOT(n1ii11O); + wire_nli10l_dataout <= wire_nli10O_dataout AND NOT(n1ii11O); + wire_nli10O_dataout <= nll11O AND NOT(n1ii10i); + wire_nli11i_dataout <= wire_nli11l_dataout AND NOT(n1ii11O); + wire_nli11l_dataout <= nll11l AND NOT(n1ii10i); + wire_nli11O_dataout <= nll11i AND NOT(n1ii11O); + wire_nli1i_dataout <= (NOT pudr(6)) WHEN nO = '1' ELSE pudr(6); + wire_nli1ii_dataout <= nll11l AND NOT(n1ii11O); + wire_nli1il_dataout <= wire_nli10O_dataout AND NOT(n1ii11O); + wire_nli1iO_dataout <= wire_nli1li_dataout AND NOT(n1ii11O); + wire_nli1l_dataout <= (NOT pudr(7)) WHEN nO = '1' ELSE pudr(7); + wire_nli1li_dataout <= nll10i AND NOT(n1ii10i); + wire_nli1ll_dataout <= nll11O AND NOT(n1ii11O); + wire_nli1lO_dataout <= wire_nli1li_dataout AND NOT(n1ii11O); + wire_nli1O_dataout <= (NOT pudr(10)) WHEN nO = '1' ELSE pudr(10); + wire_nli1Oi_dataout <= wire_nli1Ol_dataout AND NOT(n1ii11O); + wire_nli1Ol_dataout <= nll10l AND NOT(n1ii10i); + wire_nli1OO_dataout <= nll10i AND NOT(n1ii11O); + wire_nlii_dataout <= wire_nl1l1lO_dataout AND wa_6g_en; + wire_nlii0i_dataout <= comp_pat(13) WHEN n1ii10i = '1' ELSE (NOT comp_pat(5)); + wire_nlii0l_dataout <= comp_pat(14) WHEN n1ii10i = '1' ELSE (NOT comp_pat(6)); + wire_nlii0O_dataout <= comp_pat(15) WHEN n1ii10i = '1' ELSE (NOT comp_pat(7)); + wire_nlii1i_dataout <= comp_pat(10) WHEN n1ii10i = '1' ELSE (NOT comp_pat(2)); + wire_nlii1l_dataout <= comp_pat(11) WHEN n1ii10i = '1' ELSE (NOT comp_pat(3)); + wire_nlii1O_dataout <= comp_pat(12) WHEN n1ii10i = '1' ELSE (NOT comp_pat(4)); + wire_nliii_dataout <= (NOT pudr(14)) WHEN nO = '1' ELSE pudr(14); + wire_nliiii_dataout <= (NOT comp_pat(8)) AND NOT(n1ii10i); + wire_nliiil_dataout <= (NOT comp_pat(9)) AND NOT(n1ii10i); + wire_nliiiO_dataout <= comp_pat(7) AND NOT(n1ii11O); + wire_nliil_dataout <= (NOT pudr(15)) WHEN nO = '1' ELSE pudr(15); + wire_nliili_dataout <= wire_nliilO_dataout AND NOT(n1ii11O); + wire_nliill_dataout <= wire_nliiOi_dataout AND NOT(n1ii11O); + wire_nliilO_dataout <= comp_pat(8) AND NOT(n1ii10i); + wire_nliiO_dataout <= (NOT pudr(16)) WHEN nO = '1' ELSE pudr(16); + wire_nliiOi_dataout <= comp_pat(9) AND NOT(n1ii10i); + wire_nlil_dataout <= wire_nl1l1Oi_dataout AND wa_6g_en; + wire_nlili_dataout <= (NOT pudr(17)) WHEN nO = '1' ELSE pudr(17); + wire_nlill_dataout <= wire_n10O_dataout WHEN n1iii1O = '1' ELSE wire_nlO1i_dataout; + wire_nlilO_dataout <= wire_n1ii_dataout WHEN n1iii1O = '1' ELSE wire_nlO1l_dataout; + wire_nliO_dataout <= wire_nl1l1Ol_dataout AND wa_6g_en; + wire_nliOi_dataout <= wire_n1il_dataout WHEN n1iii1O = '1' ELSE wire_nlO1O_dataout; + wire_nliOl_dataout <= wire_n1iO_dataout WHEN n1iii1O = '1' ELSE wire_nlO0i_dataout; + wire_nliOO_dataout <= wire_n1li_dataout WHEN n1iii1O = '1' ELSE wire_nlO0l_dataout; + wire_nll00i_dataout <= nll11i WHEN pmadwidth(0) = '1' ELSE nliOOl; + wire_nll00l_dataout <= nll11l WHEN pmadwidth(0) = '1' ELSE nliOOO; + wire_nll00O_dataout <= nll11O WHEN pmadwidth(0) = '1' ELSE nll11i; + wire_nll01i_dataout <= nliOOi WHEN pmadwidth(0) = '1' ELSE nliOll; + wire_nll01l_dataout <= nliOOl WHEN pmadwidth(0) = '1' ELSE nliOlO; + wire_nll01O_dataout <= nliOOO WHEN pmadwidth(0) = '1' ELSE nliOOi; + wire_nll0i_dataout <= wire_n1Ol_dataout WHEN n1iii1O = '1' ELSE wire_nlOiO_dataout; + wire_nll0ii_dataout <= nll10i WHEN pmadwidth(0) = '1' ELSE nll11l; + wire_nll0il_dataout <= nll10l WHEN pmadwidth(0) = '1' ELSE nll11O; + wire_nll0iO_dataout <= nll1ii WHEN pmadwidth(0) = '1' ELSE nll10i; + wire_nll0l_dataout <= wire_n1OO_dataout WHEN n1iii1O = '1' ELSE wire_nlOli_dataout; + wire_nll0li_dataout <= wire_niili_dataout WHEN lpbk_en = '1' ELSE wire_nil0l_dataout; + wire_nll0ll_dataout <= wire_niill_dataout WHEN lpbk_en = '1' ELSE wire_nil0O_dataout; + wire_nll0lO_dataout <= wire_niilO_dataout WHEN lpbk_en = '1' ELSE wire_nilii_dataout; + wire_nll0O_dataout <= wire_n01i_dataout WHEN n1iii1O = '1' ELSE wire_nlOll_dataout; + wire_nll0Oi_dataout <= wire_niiOi_dataout WHEN lpbk_en = '1' ELSE wire_nilil_dataout; + wire_nll0Ol_dataout <= wire_niiOl_dataout WHEN lpbk_en = '1' ELSE wire_niliO_dataout; + wire_nll0OO_dataout <= wire_niiOO_dataout WHEN lpbk_en = '1' ELSE wire_nilli_dataout; + wire_nll1i_dataout <= wire_n1ll_dataout WHEN n1iii1O = '1' ELSE wire_nlO0O_dataout; + wire_nll1iO_dataout <= nliO0O WHEN pmadwidth(0) = '1' ELSE nliO0i; + wire_nll1l_dataout <= wire_n1lO_dataout WHEN n1iii1O = '1' ELSE wire_nlOii_dataout; + wire_nll1li_dataout <= nliOii WHEN pmadwidth(0) = '1' ELSE nliO0l; + wire_nll1ll_dataout <= nliOil WHEN pmadwidth(0) = '1' ELSE nliO0O; + wire_nll1lO_dataout <= nliOiO WHEN pmadwidth(0) = '1' ELSE nliOii; + wire_nll1lOi_dataout <= n10l1li AND n10l11O; + wire_nll1lOl_dataout <= wire_nll1O0i_dataout AND n10l11l; + wire_nll1O_dataout <= wire_n1Oi_dataout WHEN n1iii1O = '1' ELSE wire_nlOil_dataout; + wire_nll1O0i_dataout <= wire_w_lg_n10l10i4528w(0) AND NOT(n10l1iO); + wire_nll1O0l_dataout <= n10l10i OR n10l1iO; + wire_nll1O0O_dataout <= wire_w_lg_n10l1il4527w(0) AND n10l10i; + wire_nll1O1O_dataout <= wire_nll1O0O_dataout OR n10l1iO; + wire_nll1Oi_dataout <= nliOli WHEN pmadwidth(0) = '1' ELSE nliOil; + wire_nll1Ol_dataout <= nliOll WHEN pmadwidth(0) = '1' ELSE nliOiO; + wire_nll1OO_dataout <= nliOlO WHEN pmadwidth(0) = '1' ELSE nliOli; + wire_nlli_dataout <= wire_nl1l1OO_dataout AND wa_6g_en; + wire_nlli0i_dataout <= wire_nil0i_dataout WHEN lpbk_en = '1' ELSE wire_nilOl_dataout; + wire_nlli1i_dataout <= wire_nil1i_dataout WHEN lpbk_en = '1' ELSE wire_nilll_dataout; + wire_nlli1l_dataout <= wire_nil1l_dataout WHEN lpbk_en = '1' ELSE wire_nillO_dataout; + wire_nlli1O_dataout <= wire_nil1O_dataout WHEN lpbk_en = '1' ELSE wire_nilOi_dataout; + wire_nllii_dataout <= wire_n01l_dataout WHEN n1iii1O = '1' ELSE wire_nlOlO_dataout; + wire_nllii0O_dataout <= wire_nilOO_dataout WHEN lpbk_en = '1' ELSE wire_nlill_dataout; + wire_nlliiii_dataout <= wire_niO1i_dataout WHEN lpbk_en = '1' ELSE wire_nlilO_dataout; + wire_nlliiil_dataout <= wire_niO1l_dataout WHEN lpbk_en = '1' ELSE wire_nliOi_dataout; + wire_nlliiiO_dataout <= wire_niO1O_dataout WHEN lpbk_en = '1' ELSE wire_nliOl_dataout; + wire_nlliil_dataout <= wire_nllilO_dataout OR wire_nllliil_w_lg_dataout283w(0); + wire_nlliili_dataout <= wire_niO0i_dataout WHEN lpbk_en = '1' ELSE wire_nliOO_dataout; + wire_nlliill_dataout <= wire_niO0l_dataout WHEN lpbk_en = '1' ELSE wire_nll1i_dataout; + wire_nlliilO_dataout <= wire_niO0O_dataout WHEN lpbk_en = '1' ELSE wire_nll1l_dataout; + wire_nlliiO_dataout <= wire_nlliOi_dataout OR wire_nllliil_w_lg_dataout283w(0); + wire_nlliiOi_dataout <= wire_niOii_dataout WHEN lpbk_en = '1' ELSE wire_nll1O_dataout; + wire_nlliiOl_dataout <= wire_niOil_dataout WHEN lpbk_en = '1' ELSE wire_nll0i_dataout; + wire_nlliiOO_dataout <= wire_niOiO_dataout WHEN lpbk_en = '1' ELSE wire_nll0l_dataout; + wire_nllil_dataout <= wire_n01O_dataout WHEN n1iii1O = '1' ELSE wire_nlOOi_dataout; + wire_nllil0i_dataout <= wire_niOOi_dataout WHEN lpbk_en = '1' ELSE wire_nlliO_dataout; + wire_nllil0l_dataout <= wire_niOOl_dataout WHEN lpbk_en = '1' ELSE wire_nllli_dataout; + wire_nllil0O_dataout <= wire_niOOO_dataout WHEN lpbk_en = '1' ELSE wire_nllll_dataout; + wire_nllil1i_dataout <= wire_niOli_dataout WHEN lpbk_en = '1' ELSE wire_nll0O_dataout; + wire_nllil1l_dataout <= wire_niOll_dataout WHEN lpbk_en = '1' ELSE wire_nllii_dataout; + wire_nllil1O_dataout <= wire_niOlO_dataout WHEN lpbk_en = '1' ELSE wire_nllil_dataout; + wire_nllili_dataout <= wire_nlliOl_dataout OR wire_nllliil_w_lg_dataout283w(0); + wire_nllilii_dataout <= wire_nl11i_dataout WHEN lpbk_en = '1' ELSE wire_nlllO_dataout; + wire_nllilil_dataout <= wire_nl11l_dataout WHEN lpbk_en = '1' ELSE wire_nllOi_dataout; + wire_nlliliO_dataout <= wire_nl11O_dataout WHEN lpbk_en = '1' ELSE wire_nllOl_dataout; + wire_nllill_dataout <= wire_nlliOO_dataout OR wire_nllliil_w_lg_dataout283w(0); + wire_nllilli_dataout <= wire_nl10i_dataout WHEN lpbk_en = '1' ELSE wire_nllOO_dataout; + wire_nllilO_dataout <= wire_w_lg_n1ii1OO229w(0) WHEN n1ii10O = '1' ELSE nll1il; + wire_nllilOO_dataout <= wire_nlliO1i_dataout OR (nllii0l AND wire_nl_w_lg_nllii0i4486w(0)); + wire_nlliO_dataout <= wire_n00i_dataout WHEN n1iii1O = '1' ELSE wire_nlOOl_dataout; + wire_nlliO1i_dataout <= nlli0OO AND NOT(nllii1i); + wire_nlliOi_dataout <= n1ii01i WHEN n1ii10O = '1' ELSE nlli0l; + wire_nlliOl_dataout <= n1ii01l WHEN n1ii10O = '1' ELSE nlli0O; + wire_nlliOO_dataout <= n1ii01O WHEN n1ii10O = '1' ELSE nlliii; + wire_nlll_dataout <= wire_nl1l01i_dataout AND wa_6g_en; + wire_nlll0l_dataout <= n1ii00i OR n1ii1lO; + wire_nlll0O_dataout <= n1ii00i AND NOT(n1ii1lO); + wire_nllli_dataout <= wire_n00l_dataout WHEN n1iii1O = '1' ELSE wire_nlOOO_dataout; + wire_nlllii_dataout <= wire_w_lg_n1ii00i237w(0) AND NOT(n1ii1lO); + wire_nllliil_dataout <= encdet_prbs WHEN nlO0ilO = '1' ELSE wire_nllliiO_dataout; + wire_nllliil_w_lg_dataout283w(0) <= NOT wire_nllliil_dataout; + wire_nllliiO_dataout <= wire_nlllili_dataout WHEN sync_sm_dis = '1' ELSE nlO010O; + wire_nlllil_dataout <= n1ii1lO OR n1ii00i; + wire_nlllili_dataout <= wire_nlll1i_o WHEN wire_w_lg_w_pmadwidth_range175w219w(0) = '1' ELSE nlO0l1l; + wire_nlllill_dataout <= wire_nlO0l0i_o(0) AND NOT(n10l1ll); + wire_nlllilO_dataout <= wire_nlO0l0i_o(1) AND NOT(n10l1ll); + wire_nllliO_dataout <= n1ii1lO AND NOT(n1ii00i); + wire_nllliOi_dataout <= wire_nlO0l0i_o(2) AND NOT(n10l1ll); + wire_nllliOl_dataout <= wire_nlO0l0i_o(3) AND NOT(n10l1ll); + wire_nllll_dataout <= wire_n00O_dataout WHEN n1iii1O = '1' ELSE wire_n11i_dataout; + wire_nlllli_dataout <= wire_w_lg_n1ii1lO236w(0) AND NOT(n1ii00i); + wire_nlllO_dataout <= wire_n11l_dataout AND NOT(n1iii1O); + wire_nllO_dataout <= wire_nl0l0OO_o WHEN wa_6g_en = '1' ELSE niii0l; + wire_nllO00i_dataout <= wire_nllO0lO_o AND NOT(wire_nl_w_lg_nlO010l3809w(0)); + wire_nllO00i_w_lg_w_lg_w_lg_dataout4064w4065w4066w(0) <= wire_nllO00i_w_lg_w_lg_dataout4064w4065w(0) OR wire_w_lg_n10l01l3948w(0); + wire_nllO00i_w_lg_w_lg_dataout4064w4065w(0) <= wire_nllO00i_w_lg_dataout4064w(0) OR wire_nllO01l_dataout; + wire_nllO00i_w_lg_dataout4064w(0) <= wire_nllO00i_dataout OR wire_nllO01O_dataout; + wire_nllO00l_dataout <= wire_nllO0Oi_o AND NOT(wire_nl_w_lg_nlO010l3809w(0)); + wire_nllO00O_dataout <= wire_nllO0Ol_o AND NOT(wire_nl_w_lg_nlO010l3809w(0)); + wire_nllO00O_w_lg_w_lg_w_lg_dataout3960w3961w3962w(0) <= wire_nllO00O_w_lg_w_lg_dataout3960w3961w(0) OR wire_nllO01l_dataout; + wire_nllO00O_w_lg_w_lg_dataout3960w3961w(0) <= wire_nllO00O_w_lg_dataout3960w(0) OR wire_nllO01O_dataout; + wire_nllO00O_w_lg_dataout3960w(0) <= wire_nllO00O_dataout OR wire_nllO00i_dataout; + wire_nllO01i_dataout <= wire_nllO0iO_o AND NOT(wire_nl_w_lg_nlO010l3809w(0)); + wire_nllO01l_dataout <= wire_nllO0li_o AND NOT(wire_nl_w_lg_nlO010l3809w(0)); + wire_nllO01O_dataout <= wire_nllO0ll_o AND NOT(wire_nl_w_lg_nlO010l3809w(0)); + wire_nllO0ii_dataout <= wire_nllO0OO_o AND NOT(wire_nl_w_lg_nlO010l3809w(0)); + wire_nllO0ii_w_lg_w_lg_w_lg_dataout3945w3946w3947w(0) <= wire_nllO0ii_w_lg_w_lg_dataout3945w3946w(0) OR wire_nllO01l_dataout; + wire_nllO0ii_w_lg_w_lg_dataout3945w3946w(0) <= wire_nllO0ii_w_lg_dataout3945w(0) OR wire_nllO01O_dataout; + wire_nllO0ii_w_lg_dataout3945w(0) <= wire_nllO0ii_dataout OR wire_nllO00i_dataout; + wire_nllO0ii_w_lg_dataout4069w(0) <= wire_nllO0ii_dataout OR wire_nllO00O_dataout; + wire_nllO0il_dataout <= wire_nllOi1i_o OR wire_nl_w_lg_nlO010l3809w(0); + wire_nllO0il_w_lg_w_lg_dataout3407w4078w(0) <= wire_nllO0il_w_lg_dataout3407w(0) OR wire_nllO01l_dataout; + wire_nllO0il_w_lg_dataout3407w(0) <= wire_nllO0il_dataout OR wire_nllO0ii_dataout; + wire_nllOi_dataout <= wire_n11O_dataout AND NOT(n1iii1O); + wire_nllOi0l_dataout <= wire_nllOill_dataout AND NOT(n10l0li); + wire_nllOi0O_dataout <= wire_nllOilO_dataout AND NOT(n10l0li); + wire_nllOi1l_dataout <= n10l01O AND NOT(wire_w_lg_n10lili3500w(0)); + wire_nllOi1O_dataout <= wire_w_lg_n10l01O3545w(0) AND NOT(wire_w_lg_n10lili3500w(0)); + wire_nllOiii_dataout <= wire_nllOiOi_dataout AND NOT(n10l0li); + wire_nllOiil_dataout <= n10l0il AND NOT(n10l0li); + wire_nllOiiO_dataout <= wire_nllOiOl_dataout AND NOT(n10l0li); + wire_nllOili_dataout <= wire_nllOiOO_dataout AND NOT(n10l0li); + wire_nllOill_dataout <= wire_nllOl1i_dataout AND NOT(n10l0il); + wire_nllOilO_dataout <= wire_nllOl1l_dataout AND NOT(n10l0il); + wire_nllOiOi_dataout <= wire_nllOl1O_dataout AND NOT(n10l0il); + wire_nllOiOl_dataout <= n10l0ii AND NOT(n10l0il); + wire_nllOiOO_dataout <= wire_nllOl0i_dataout AND NOT(n10l0il); + wire_nllOl_dataout <= wire_n10i_dataout AND NOT(n1iii1O); + wire_nllOl0i_dataout <= wire_nllOlii_dataout AND NOT(n10l0ii); + wire_nllOl0l_dataout <= n10l00l AND NOT(n10l00O); + wire_nllOl0O_dataout <= wire_nllOlil_dataout AND NOT(n10l00O); + wire_nllOl1i_dataout <= wire_nllOl0l_dataout AND NOT(n10l0ii); + wire_nllOl1l_dataout <= n10l00O AND NOT(n10l0ii); + wire_nllOl1O_dataout <= wire_nllOl0O_dataout AND NOT(n10l0ii); + wire_nllOlii_dataout <= wire_nllOliO_dataout AND NOT(n10l00O); + wire_nllOlil_dataout <= n10l00i AND NOT(n10l00l); + wire_nllOliO_dataout <= wire_w_lg_n10l00i3543w(0) AND NOT(n10l00l); + wire_nllOO_dataout <= wire_n10l_dataout AND NOT(n1iii1O); + wire_nllOO0O_dataout <= wire_nllOOli_dataout AND NOT(n10li1i); + wire_nllOOii_dataout <= wire_nllOOll_dataout AND NOT(n10li1i); + wire_nllOOil_dataout <= wire_nllOOlO_dataout AND NOT(n10li1i); + wire_nllOOiO_dataout <= n10li1O AND NOT(n10li1i); + wire_nllOOli_dataout <= wire_nllOOOi_dataout AND NOT(n10li1O); + wire_nllOOll_dataout <= n10li1l AND NOT(n10li1O); + wire_nllOOlO_dataout <= wire_nllOOOl_dataout AND NOT(n10li1O); + wire_nllOOOi_dataout <= wire_nllOOOO_dataout AND NOT(n10li1l); + wire_nllOOOl_dataout <= n10liii AND NOT(n10li1l); + wire_nllOOOO_dataout <= wire_w_lg_n10li0i3455w(0) AND NOT(n10liii); + wire_nlO0i_dataout <= (NOT pudi(3)) WHEN nO = '1' ELSE pudi(3); + wire_nlO0l_dataout <= (NOT pudi(4)) WHEN nO = '1' ELSE pudi(4); + wire_nlO0O_dataout <= (NOT pudi(5)) WHEN nO = '1' ELSE pudi(5); + wire_nlO0O0l_dataout <= n1ii11i OR n1ii11l; + wire_nlO0Oli_dataout <= n1i0O0O OR n1i0Oii; + wire_nlO0OOO_dataout <= n1i0lOO OR n1i0O1i; + wire_nlO100i_dataout <= n10li0l AND NOT(n10liiO); + wire_nlO100l_dataout <= wire_w_lg_n10li0i3455w(0) AND NOT(n10li0l); + wire_nlO101i_dataout <= wire_nlO100i_dataout AND NOT(n10l0ll); + wire_nlO101l_dataout <= n10liiO AND NOT(n10l0ll); + wire_nlO101O_dataout <= wire_nlO100l_dataout AND NOT(n10liiO); + wire_nlO110O_dataout <= wire_nlO11ll_dataout AND NOT(n10l0Ol); + wire_nlO11ii_dataout <= wire_nlO11lO_dataout AND NOT(n10l0Ol); + wire_nlO11il_dataout <= n10l0Oi AND NOT(n10l0Ol); + wire_nlO11iO_dataout <= wire_nlO11Oi_dataout AND NOT(n10l0Ol); + wire_nlO11li_dataout <= wire_nlO11Ol_dataout AND NOT(n10l0Ol); + wire_nlO11ll_dataout <= wire_nlO11OO_dataout AND NOT(n10l0Oi); + wire_nlO11lO_dataout <= wire_nlO101i_dataout AND NOT(n10l0Oi); + wire_nlO11Oi_dataout <= n10l0ll AND NOT(n10l0Oi); + wire_nlO11Ol_dataout <= wire_nlO101l_dataout AND NOT(n10l0Oi); + wire_nlO11OO_dataout <= wire_nlO101O_dataout AND NOT(n10l0ll); + wire_nlO1i_dataout <= (NOT pudi(0)) WHEN nO = '1' ELSE pudi(0); + wire_nlO1i0i_dataout <= wire_nlO1iiO_dataout AND NOT(n10li0l); + wire_nlO1i0l_dataout <= n10liiO AND NOT(n10li0l); + wire_nlO1i0O_dataout <= wire_nlO1ili_dataout AND NOT(n10liiO); + wire_nlO1i1i_dataout <= wire_nlO1i0O_dataout AND NOT(n10li0l); + wire_nlO1i1l_dataout <= wire_nlO1iii_dataout AND NOT(n10li0l); + wire_nlO1i1O_dataout <= wire_nlO1iil_dataout AND NOT(n10li0l); + wire_nlO1iii_dataout <= wire_nlO1ill_dataout AND NOT(n10liiO); + wire_nlO1iil_dataout <= n10li1i AND NOT(n10liiO); + wire_nlO1iiO_dataout <= wire_nlO1ilO_dataout AND NOT(n10liiO); + wire_nlO1ili_dataout <= wire_nlO1iOi_dataout AND NOT(n10li1i); + wire_nlO1ill_dataout <= n10li1l AND NOT(n10li1i); + wire_nlO1ilO_dataout <= wire_nlO1iOl_dataout AND NOT(n10li1i); + wire_nlO1iOi_dataout <= wire_nlO1iOO_dataout AND NOT(n10li1l); + wire_nlO1iOl_dataout <= n10li1O AND NOT(n10li1l); + wire_nlO1iOO_dataout <= wire_w_lg_n10li0i3455w(0) AND NOT(n10li1O); + wire_nlO1l_dataout <= (NOT pudi(1)) WHEN nO = '1' ELSE pudi(1); + wire_nlO1l0i_dataout <= n10liiO AND NOT(n10liil); + wire_nlO1l0l_dataout <= wire_nlO1lil_dataout AND NOT(n10ll0i); + wire_nlO1l0O_dataout <= wire_nlO1liO_dataout AND NOT(n10ll0i); + wire_nlO1l1l_dataout <= wire_nlO101O_dataout AND NOT(n10liil); + wire_nlO1l1O_dataout <= wire_nlO100i_dataout AND NOT(n10liil); + wire_nlO1lii_dataout <= n10lill AND NOT(n10ll0i); + wire_nlO1lil_dataout <= wire_w_lg_n10lilO3445w(0) AND NOT(n10lill); + wire_nlO1liO_dataout <= n10lilO AND NOT(n10lill); + wire_nlO1O_dataout <= (NOT pudi(2)) WHEN nO = '1' ELSE pudi(2); + wire_nlO1O0i_dataout <= n10liOi AND NOT(n10ll1i); + wire_nlO1O0l_dataout <= wire_w_lg_n10lilO3445w(0) AND NOT(n10liOi); + wire_nlO1O0O_dataout <= n10lilO AND NOT(n10liOi); + wire_nlO1O1l_dataout <= wire_nlO1O0l_dataout AND NOT(n10ll1i); + wire_nlO1O1O_dataout <= wire_nlO1O0O_dataout AND NOT(n10ll1i); + wire_nlO1Oll_dataout <= n10ll1l AND NOT(wire_nl_w_lg_niii0l3438w(0)); + wire_nlO1OlO_dataout <= wire_w_lg_n10ll1l3437w(0) AND NOT(wire_nl_w_lg_niii0l3438w(0)); + wire_nlOi_dataout <= wire_nl0li1i_o AND wa_6g_en; + wire_nlOi00l_dataout <= n1i0l0l OR n1i0l0O; + wire_nlOi0li_dataout <= n1i0l1O OR n1i0l0i; + wire_nlOi10l_dataout <= n1i0lll OR n1i0llO; + wire_nlOi1li_dataout <= n1i0liO OR n1i0lli; + wire_nlOi1OO_dataout <= n1i0lii OR n1i0lil; + wire_nlOii_dataout <= (NOT pudi(6)) WHEN nO = '1' ELSE pudi(6); + wire_nlOil_dataout <= (NOT pudi(7)) WHEN nO = '1' ELSE pudi(7); + wire_nlOiO_dataout <= (NOT pudi(8)) WHEN nO = '1' ELSE pudi(8); + wire_nlOl_dataout <= n1iiilO WHEN wa_6g_en = '1' ELSE nllll1i; + wire_nlOli_dataout <= (NOT pudi(9)) WHEN nO = '1' ELSE pudi(9); + wire_nlOll_dataout <= (NOT pudi(10)) WHEN nO = '1' ELSE pudi(10); + wire_nlOll0O_dataout <= niii0i WHEN ((wire_niOiOl_w_lg_w_lg_o1205w3260w(0) OR (wire_niOiOl_o AND n1i001i)) OR (n1i00il AND n1i000l)) = '1' ELSE (n1i001l OR n1i001O); + wire_nlOll0O_w_lg_w_lg_dataout1212w3256w(0) <= wire_nlOll0O_w_lg_dataout1212w(0) AND n10llOl; + wire_nlOll0O_w_lg_dataout1212w(0) <= NOT wire_nlOll0O_dataout; + wire_nlOlO_dataout <= (NOT pudi(11)) WHEN nO = '1' ELSE pudi(11); + wire_nlOO_dataout <= nll01li WHEN wa_6g_en = '1' ELSE nlO011i; + wire_nlOOi_dataout <= (NOT pudi(12)) WHEN nO = '1' ELSE pudi(12); + wire_nlOOl_dataout <= (NOT pudi(13)) WHEN nO = '1' ELSE pudi(13); + wire_nlOOO_dataout <= (NOT pudi(14)) WHEN nO = '1' ELSE pudi(14); + wire_n011ili_a <= ( "0" & max_rlv_sel(5 DOWNTO 0)); + wire_n011ili_b <= ( "0" & "0" & "0" & max_rlv_sel(5 DOWNTO 2)); + n011ili : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n011ili_a, + b => wire_n011ili_b, + cin => wire_gnd, + o => wire_n011ili_o + ); + wire_n1li0i_a <= ( "0" & wire_n1ll1O_o & wire_n1ll1l_o & wire_n1ll1i_o & wire_n1liOO_o); + wire_n1li0i_b <= ( "0" & wire_n1liOi_o & wire_n1lilO_o & wire_n1lill_o & wire_n1lili_o); + n1li0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1li0i_a, + b => wire_n1li0i_b, + cin => wire_gnd, + o => wire_n1li0i_o + ); + wire_n1li1O_a <= ( wire_n1liiO_dataout & wire_n1liil_dataout & wire_n1li0O_dataout & wire_n1li0l_dataout); + wire_n1li1O_b <= ( "0" & "0" & "0" & "1"); + n1li1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n1li1O_a, + b => wire_n1li1O_b, + cin => wire_gnd, + o => wire_n1li1O_o + ); + wire_n1O0lO_a <= ( "0" & "0" & wire_w_lg_n10O0li2685w & max_rlv_sel(4 DOWNTO 2)); + wire_n1O0lO_b <= ( wire_w_lg_n10O0li2685w & max_rlv_sel(4 DOWNTO 0)); + n1O0lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n1O0lO_a, + b => wire_n1O0lO_b, + cin => wire_gnd, + o => wire_n1O0lO_o + ); + wire_n1Ol0Ol_a <= ( wire_n1Oli0O_dataout & wire_n1Oli0l_dataout & wire_n1Oli1O_dataout & wire_n1Oli1l_dataout & wire_n1Oli1i_dataout); + wire_n1Ol0Ol_b <= ( "0" & "0" & "0" & "0" & "1"); + n1Ol0Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1Ol0Ol_a, + b => wire_n1Ol0Ol_b, + cin => wire_gnd, + o => wire_n1Ol0Ol_o + ); + wire_n1Ol0OO_a <= ( "0" & wire_n1Oll1l_o & wire_n1Oll1i_o & wire_n1OliOO_o & wire_n1OliOl_o & wire_n1OliOi_o); + wire_n1Ol0OO_b <= ( "0" & wire_n1Olill_o & wire_n1Olili_o & wire_n1OliiO_o & wire_n1Oliil_o & wire_n1Oliii_o); + n1Ol0OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n1Ol0OO_a, + b => wire_n1Ol0OO_b, + cin => wire_gnd, + o => wire_n1Ol0OO_o + ); + wire_nl0iiOl_a <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + wire_nl0iiOl_b <= ( "0" & "0" & "0" & "0" & "1"); + nl0iiOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl0iiOl_a, + b => wire_nl0iiOl_b, + cin => wire_gnd, + o => wire_nl0iiOl_o + ); + wire_nl1iil_a <= ( nl10Oi & nl10ll & nl10li & nl10il & "1"); + wire_nl1iil_b <= ( "1" & "1" & "1" & "0" & "1"); + nl1iil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl1iil_a, + b => wire_nl1iil_b, + cin => wire_gnd, + o => wire_nl1iil_o + ); + wire_nllO1lO_a <= ( nlO0i1i & nlO00OO & nlO00Ol & nlO00Oi & nlO00lO & nlO00ll & nlO00li & nlO00iO & nlO00il & nlO00ii & "1"); + wire_nllO1lO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nllO1lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nllO1lO_a, + b => wire_nllO1lO_b, + cin => wire_gnd, + o => wire_nllO1lO_o + ); + wire_nllO1Oi_a <= ( nlO000O & nlO000l & nlO000i & nlO001O & nlO001l & nlO001i & nlO01OO & nlO01Ol & nlO01Oi & nlO01lO); + wire_nllO1Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nllO1Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nllO1Oi_a, + b => wire_nllO1Oi_b, + cin => wire_gnd, + o => wire_nllO1Oi_o + ); + wire_nllO1Ol_a <= ( nlO0i1i & nlO00OO & nlO00Ol & nlO00Oi & nlO00lO & nlO00ll & nlO00li & nlO00iO & nlO00il & nlO00ii); + wire_nllO1Ol_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nllO1Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nllO1Ol_a, + b => wire_nllO1Ol_b, + cin => wire_gnd, + o => wire_nllO1Ol_o + ); + wire_nllO1OO_a <= ( nlO0ill & nlO0ili & nlO0iiO & nlO0iil & nlO0iii & nlO0i0O & nlO0i0l & nlO0i0i & nlO0i1O & nlO0i1l); + wire_nllO1OO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nllO1OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nllO1OO_a, + b => wire_nllO1OO_b, + cin => wire_gnd, + o => wire_nllO1OO_o + ); + wire_nlO0l0i_a <= ( nlO01ll & nlO01li & nlO01iO & nlO01il); + wire_nlO0l0i_b <= ( "0" & "0" & "0" & "1"); + nlO0l0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nlO0l0i_a, + b => wire_nlO0l0i_b, + cin => wire_gnd, + o => wire_nlO0l0i_o + ); + wire_n1Oill_a <= ( wire_n1O0ll_dataout & wire_n1O0li_dataout & wire_n1O0iO_dataout & wire_n1O0il_dataout & wire_n1O0ii_dataout & wire_n1O00O_dataout & wire_n1O00l_dataout & wire_n1O00i_dataout); + wire_n1Oill_b <= ( n1l0lO & n1l0ll & n1l0li & n1l0iO & n1l0il & n1l0ii & n1l00O & n1liii); + n1Oill : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n1Oill_a, + b => wire_n1Oill_b, + cin => wire_gnd, + o => wire_n1Oill_o + ); + wire_n1OOi1l_a <= ( wire_n011i1l_dataout & wire_n011i1i_dataout & wire_n0110OO_dataout & wire_n0110Ol_dataout & wire_n0110Oi_dataout & wire_n0110lO_dataout & wire_n0110ll_dataout & wire_n0110li_dataout & wire_n0110iO_dataout & "0"); + wire_n1OOi1l_b <= ( n1Ol0ii & n1Ol00O & n1Ol00l & n1Ol00i & n1Ol01O & n1Ol01l & n1Ol01i & n1Ol1OO & n1Ol1Ol & n1Oli0i); + n1OOi1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_n1OOi1l_a, + b => wire_n1OOi1l_b, + cin => wire_gnd, + o => wire_n1OOi1l_o + ); + wire_nl0iiOO_a <= ( "1" & "0" & "0" & "1" & "1"); + wire_nl0iiOO_b <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0iiOO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl0iiOO_a, + b => wire_nl0iiOO_b, + cin => wire_vcc, + o => wire_nl0iiOO_o + ); + wire_nl0illl_a <= ( "0" & "1" & "1" & "1" & "1"); + wire_nl0illl_b <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0illl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl0illl_a, + b => wire_nl0illl_b, + cin => wire_vcc, + o => wire_nl0illl_o + ); + wire_nl0iOii_a <= ( "0" & "1" & "0" & "0" & "1"); + wire_nl0iOii_b <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0iOii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl0iOii_a, + b => wire_nl0iOii_b, + cin => wire_vcc, + o => wire_nl0iOii_o + ); + wire_nl0l11O_a <= ( "0" & "0" & "1" & "1" & "1"); + wire_nl0l11O_b <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0l11O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl0l11O_a, + b => wire_nl0l11O_b, + cin => wire_vcc, + o => wire_nl0l11O_o + ); + wire_nllOO1l_a <= ( nlO0i1i & nlO00OO & nlO00Ol & nlO00Oi & nlO00lO & nlO00ll & nlO00li & nlO00iO & nlO00il & nlO00ii); + wire_nllOO1l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nllOO1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nllOO1l_a, + b => wire_nllOO1l_b, + cin => wire_vcc, + o => wire_nllOO1l_o + ); + wire_nlO10Ol_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + wire_nlO10Ol_b <= ( nlO0i1i & nlO00OO & nlO00Ol & nlO00Oi & nlO00lO & nlO00ll & nlO00li & nlO00iO & nlO00il & nlO00ii); + nlO10Ol : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nlO10Ol_a, + b => wire_nlO10Ol_b, + cin => wire_gnd, + o => wire_nlO10Ol_o + ); + wire_niOO0l_data <= ( nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOll & nliOlO); + wire_niOO0l_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOO0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOO0l_data, + o => wire_niOO0l_o, + sel => wire_niOO0l_sel + ); + wire_niOO0O_data <= ( nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOll & nliOlO & nliOOi); + wire_niOO0O_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOO0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOO0O_data, + o => wire_niOO0O_o, + sel => wire_niOO0O_sel + ); + wire_niOOii_data <= ( nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOll & nliOlO & nliOOi & nliOOl); + wire_niOOii_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOii_data, + o => wire_niOOii_o, + sel => wire_niOOii_sel + ); + wire_niOOil_data <= ( nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOll & nliOlO & nliOOi & nliOOl & nliOOO); + wire_niOOil_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOil_data, + o => wire_niOOil_o, + sel => wire_niOOil_sel + ); + wire_niOOiO_data <= ( nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOll & nliOlO & nliOOi & nliOOl & nliOOO & nll11i); + wire_niOOiO_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOiO_data, + o => wire_niOOiO_o, + sel => wire_niOOiO_sel + ); + wire_niOOli_data <= ( nliOii & nliOii & nliOii & nliOii & nliOii & nliOii & nliOil & nliOiO & nliOli & nliOll & nliOlO & nliOOi & nliOOl & nliOOO & nll11i & nll11l); + wire_niOOli_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOli : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOli_data, + o => wire_niOOli_o, + sel => wire_niOOli_sel + ); + wire_niOOll_data <= ( nliOil & nliOil & nliOil & nliOil & nliOil & nliOil & nliOiO & nliOli & nliOll & nliOlO & nliOOi & nliOOl & nliOOO & nll11i & nll11l & nll11O); + wire_niOOll_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOll_data, + o => wire_niOOll_o, + sel => wire_niOOll_sel + ); + wire_niOOlO_data <= ( nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliOli & nliOll & nliOlO & nliOOi & nliOOl & nliOOO & nll11i & nll11l & nll11O & nll10i); + wire_niOOlO_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOlO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOlO_data, + o => wire_niOOlO_o, + sel => wire_niOOlO_sel + ); + wire_niOOOi_data <= ( nliOli & nliOli & nliOli & nliOli & nliOli & nliOli & nliOll & nliOlO & nliOOi & nliOOl & nliOOO & nll11i & nll11l & nll11O & nll10i & nll10l); + wire_niOOOi_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOOi_data, + o => wire_niOOOi_o, + sel => wire_niOOOi_sel + ); + wire_niOOOl_data <= ( nliOll & nliOll & nliOll & nliOll & nliOll & nliOll & nliOlO & nliOOi & nliOOl & nliOOO & nll11i & nll11l & nll11O & nll10i & nll10l & nll1ii); + wire_niOOOl_sel <= ( wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + niOOOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_niOOOl_data, + o => wire_niOOOl_o, + sel => wire_niOOOl_sel + ); + wire_nl00l0i_data <= ( nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0l0i & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i); + wire_nl00l0i_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00l0i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00l0i_data, + o => wire_nl00l0i_o, + sel => wire_nl00l0i_sel + ); + wire_nl00l0l_data <= ( nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0i0i & nll0lil & nll0lii & nll0l0O & nll0l0l & nll0l0i & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i); + wire_nl00l0l_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00l0l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00l0l_data, + o => wire_nl00l0l_o, + sel => wire_nl00l0l_sel + ); + wire_nl00l0O_data <= ( nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l & nll001i & nll01OO & nll01Ol); + wire_nl00l0O_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00l0O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00l0O_data, + o => wire_nl00l0O_o, + sel => wire_nl00l0O_sel + ); + wire_nl00lii_data <= ( nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l & nll001i & nll01OO); + wire_nl00lii_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00lii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00lii_data, + o => wire_nl00lii_o, + sel => wire_nl00lii_sel + ); + wire_nl00lil_data <= ( nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l & nll001i); + wire_nl00lil_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00lil : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00lil_data, + o => wire_nl00lil_o, + sel => wire_nl00lil_sel + ); + wire_nl00liO_data <= ( nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l); + wire_nl00liO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00liO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00liO_data, + o => wire_nl00liO_o, + sel => wire_nl00liO_sel + ); + wire_nl00lli_data <= ( nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O); + wire_nl00lli_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00lli : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00lli_data, + o => wire_nl00lli_o, + sel => wire_nl00lli_sel + ); + wire_nl00lll_data <= ( nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i); + wire_nl00lll_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00lll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00lll_data, + o => wire_nl00lll_o, + sel => wire_nl00lll_sel + ); + wire_nl00llO_data <= ( nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l); + wire_nl00llO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00llO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00llO_data, + o => wire_nl00llO_o, + sel => wire_nl00llO_sel + ); + wire_nl00lOi_data <= ( nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O); + wire_nl00lOi_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00lOi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00lOi_data, + o => wire_nl00lOi_o, + sel => wire_nl00lOi_sel + ); + wire_nl00lOl_data <= ( nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii); + wire_nl00lOl_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00lOl : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00lOl_data, + o => wire_nl00lOl_o, + sel => wire_nl00lOl_sel + ); + wire_nl00lOO_data <= ( nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il); + wire_nl00lOO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00lOO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00lOO_data, + o => wire_nl00lOO_o, + sel => wire_nl00lOO_sel + ); + wire_nl00O0i_data <= ( nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO); + wire_nl00O0i_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00O0i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00O0i_data, + o => wire_nl00O0i_o, + sel => wire_nl00O0i_sel + ); + wire_nl00O0l_data <= ( nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi); + wire_nl00O0l_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00O0l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00O0l_data, + o => wire_nl00O0l_o, + sel => wire_nl00O0l_sel + ); + wire_nl00O0O_data <= ( nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol); + wire_nl00O0O_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00O0O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00O0O_data, + o => wire_nl00O0O_o, + sel => wire_nl00O0O_sel + ); + wire_nl00O1i_data <= ( nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO); + wire_nl00O1i_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00O1i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00O1i_data, + o => wire_nl00O1i_o, + sel => wire_nl00O1i_sel + ); + wire_nl00O1l_data <= ( nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li); + wire_nl00O1l_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00O1l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00O1l_data, + o => wire_nl00O1l_o, + sel => wire_nl00O1l_sel + ); + wire_nl00O1O_data <= ( nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll00Ol & nll00Oi & nll00lO & nll00ll); + wire_nl00O1O_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00O1O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00O1O_data, + o => wire_nl00O1O_o, + sel => wire_nl00O1O_sel + ); + wire_nl00Oil_data <= ( nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll01Ol & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l & nll001i & nll01OO & nll01Ol); + wire_nl00Oil_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00Oil : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00Oil_data, + o => wire_nl00Oil_o, + sel => wire_nl00Oil_sel + ); + wire_nl00OiO_data <= ( nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll01OO & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l & nll001i & nll01OO); + wire_nl00OiO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00OiO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00OiO_data, + o => wire_nl00OiO_o, + sel => wire_nl00OiO_sel + ); + wire_nl00Oli_data <= ( nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll001i & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l & nll001i); + wire_nl00Oli_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00Oli : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00Oli_data, + o => wire_nl00Oli_o, + sel => wire_nl00Oli_sel + ); + wire_nl00Oll_data <= ( nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll001l & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O & nll001l); + wire_nl00Oll_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00Oll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00Oll_data, + o => wire_nl00Oll_o, + sel => wire_nl00Oll_sel + ); + wire_nl00OlO_data <= ( nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll001O & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i & nll001O); + wire_nl00OlO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00OlO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00OlO_data, + o => wire_nl00OlO_o, + sel => wire_nl00OlO_sel + ); + wire_nl00OOi_data <= ( nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll000i & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l & nll000i); + wire_nl00OOi_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00OOi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00OOi_data, + o => wire_nl00OOi_o, + sel => wire_nl00OOi_sel + ); + wire_nl00OOl_data <= ( nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll000l & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O & nll000l); + wire_nl00OOl_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00OOl : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00OOl_data, + o => wire_nl00OOl_o, + sel => wire_nl00OOl_sel + ); + wire_nl00OOO_data <= ( nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll000O & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii & nll000O); + wire_nl00OOO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl00OOO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl00OOO_data, + o => wire_nl00OOO_o, + sel => wire_nl00OOO_sel + ); + wire_nl0i0Ol_data <= ( wire_nl0ii0i_dataout & wire_nl0il1i_dataout & wire_nl0illO_dataout & wire_nl0iOil_dataout); + wire_nl0i0Ol_sel <= ( pmadwidth(1 DOWNTO 0)); + nl0i0Ol : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl0i0Ol_data, + o => wire_nl0i0Ol_o, + sel => wire_nl0i0Ol_sel + ); + wire_nl0i0OO_data <= ( wire_nl0ii0l_dataout & wire_nl0il1l_dataout & wire_nl0ilOi_dataout & wire_nl0iOiO_dataout); + wire_nl0i0OO_sel <= ( pmadwidth(1 DOWNTO 0)); + nl0i0OO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl0i0OO_data, + o => wire_nl0i0OO_o, + sel => wire_nl0i0OO_sel + ); + wire_nl0i10i_data <= ( nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll00li & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li); + wire_nl0i10i_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i10i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i10i_data, + o => wire_nl0i10i_o, + sel => wire_nl0i10i_sel + ); + wire_nl0i10l_data <= ( nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll00ll & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll); + wire_nl0i10l_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i10l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i10l_data, + o => wire_nl0i10l_o, + sel => wire_nl0i10l_sel + ); + wire_nl0i10O_data <= ( nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll00lO & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO); + wire_nl0i10O_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i10O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i10O_data, + o => wire_nl0i10O_o, + sel => wire_nl0i10O_sel + ); + wire_nl0i11i_data <= ( nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll00ii & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il & nll00ii); + wire_nl0i11i_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i11i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i11i_data, + o => wire_nl0i11i_o, + sel => wire_nl0i11i_sel + ); + wire_nl0i11l_data <= ( nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll00il & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO & nll00il); + wire_nl0i11l_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i11l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i11l_data, + o => wire_nl0i11l_o, + sel => wire_nl0i11l_sel + ); + wire_nl0i11O_data <= ( nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll00iO & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi & nll00lO & nll00ll & nll00li & nll00iO); + wire_nl0i11O_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i11O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i11O_data, + o => wire_nl0i11O_o, + sel => wire_nl0i11O_sel + ); + wire_nl0i1ii_data <= ( nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll00Oi & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol & nll00Oi); + wire_nl0i1ii_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i1ii : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i1ii_data, + o => wire_nl0i1ii_o, + sel => wire_nl0i1ii_sel + ); + wire_nl0i1il_data <= ( nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll00Ol & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO & nll00Ol); + wire_nl0i1il_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i1il : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i1il_data, + o => wire_nl0i1il_o, + sel => wire_nl0i1il_sel + ); + wire_nl0i1iO_data <= ( nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll00OO & nll0l0i & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i & nll00OO); + wire_nl0i1iO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i1iO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i1iO_data, + o => wire_nl0i1iO_o, + sel => wire_nl0i1iO_sel + ); + wire_nl0i1li_data <= ( nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0i1i & nll0l0l & nll0l0i & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l & nll0i1i); + wire_nl0i1li_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i1li : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i1li_data, + o => wire_nl0i1li_o, + sel => wire_nl0i1li_sel + ); + wire_nl0i1ll_data <= ( nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0i1l & nll0l0O & nll0l0l & nll0l0i & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O & nll0i1l); + wire_nl0i1ll_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i1ll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i1ll_data, + o => wire_nl0i1ll_o, + sel => wire_nl0i1ll_sel + ); + wire_nl0i1lO_data <= ( nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0i1O & nll0lii & nll0l0O & nll0l0l & nll0l0i & nll0l1O & nll0l1l & nll0l1i & nll0iOO & nll0iOl & nll0iOi & nll0ilO & nll0ill & nll0ili & nll0iiO & nll0iil & nll0iii & nll0i0O & nll0i0l & nll0i0i & nll0i1O); + wire_nl0i1lO_sel <= ( nl010ii & nl0100O & nl0100l & nl0100i & nl0101O); + nl0i1lO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl0i1lO_data, + o => wire_nl0i1lO_o, + sel => wire_nl0i1lO_sel + ); + wire_nl0ii1i_data <= ( wire_nl0ii0O_dataout & wire_nl0il1O_dataout & wire_nl0ilOl_dataout & wire_nl0iOli_dataout); + wire_nl0ii1i_sel <= ( pmadwidth(1 DOWNTO 0)); + nl0ii1i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl0ii1i_data, + o => wire_nl0ii1i_o, + sel => wire_nl0ii1i_sel + ); + wire_nl0ii1l_data <= ( wire_nl0iiii_dataout & wire_nl0il0i_dataout & wire_nl0ilOO_dataout & wire_nl0iOll_dataout); + wire_nl0ii1l_sel <= ( pmadwidth(1 DOWNTO 0)); + nl0ii1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl0ii1l_data, + o => wire_nl0ii1l_o, + sel => wire_nl0ii1l_sel + ); + wire_nl0ii1O_data <= ( wire_nl0iiil_dataout & wire_nl0il0l_dataout & wire_nl0iO1i_dataout & wire_nl0iOlO_dataout); + wire_nl0ii1O_sel <= ( pmadwidth(1 DOWNTO 0)); + nl0ii1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl0ii1O_data, + o => wire_nl0ii1O_o, + sel => wire_nl0ii1O_sel + ); + wire_nl0l0OO_data <= ( n111OOO & n111OOO & n111O0O & n111OOO & n111O0O & n111OOO & n111O0O & wire_w_lg_w_lg_comp_pat_porn5757w5758w); + wire_nl0l0OO_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0l0OO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0l0OO_data, + o => wire_nl0l0OO_o, + sel => wire_nl0l0OO_sel + ); + wire_nl0li1i_data <= ( n11011O & n11011O & n111OiO & n11011O & n111OiO & wire_w_lg_w_lg_comp_pat_porn5743w5744w & n111OlO & wire_w_lg_w_lg_comp_pat_porn5738w5739w); + wire_nl0li1i_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0li1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0li1i_data, + o => wire_nl0li1i_o, + sel => wire_nl0li1i_sel + ); + wire_nl0OiOl_w_lg_o13575w(0) <= NOT wire_nl0OiOl_o; + wire_nl0OiOl_w_lg_o5684w(0) <= wire_nl0OiOl_o OR wire_w_lg_n110O1i5616w(0); + wire_nl0OiOl_w_lg_o5615w(0) <= wire_nl0OiOl_o OR wire_w_lg_n110O1l5614w(0); + wire_nl0OiOl_data <= ( n10iOOi & n101iil & n11iO0i & n1000ll & n11lili & n10i1lO & n11O1Ol & n10iOOi); + wire_nl0OiOl_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OiOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OiOl_data, + o => wire_nl0OiOl_o, + sel => wire_nl0OiOl_sel + ); + wire_nl0OiOO_w_lg_o5429w(0) <= NOT wire_nl0OiOO_o; + wire_nl0OiOO_data <= ( n10iOli & n101i1O & n11ilOl & n1000il & n11liii & n10i1iO & n11O1ll & n10iOli); + wire_nl0OiOO_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OiOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OiOO_data, + o => wire_nl0OiOO_o, + sel => wire_nl0OiOO_sel + ); + wire_nl0Ol0i_w_lg_o5439w(0) <= NOT wire_nl0Ol0i_o; + wire_nl0Ol0i_data <= ( n10ilOi & n1011Oi & n11iiiO & n1001ll & n11l0li & n100OlO & n11lOOl & n10ilOi); + wire_nl0Ol0i_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Ol0i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Ol0i_data, + o => wire_nl0Ol0i_o, + sel => wire_nl0Ol0i_sel + ); + wire_nl0Ol0l_w_lg_o5445w(0) <= NOT wire_nl0Ol0l_o; + wire_nl0Ol0l_data <= ( n10illi & n1011il & n11ii0i & n1001il & n11l0ii & n100OiO & n11lOll & n10illi); + wire_nl0Ol0l_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Ol0l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Ol0l_data, + o => wire_nl0Ol0l_o, + sel => wire_nl0Ol0l_sel + ); + wire_nl0Ol0O_w_lg_o5452w(0) <= NOT wire_nl0Ol0O_o; + wire_nl0Ol0O_data <= ( n10ilii & n10111O & n11i0Ol & n10010l & n11l00i & n100O0O & n11lOil & n10ilii); + wire_nl0Ol0O_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Ol0O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Ol0O_data, + o => wire_nl0Ol0O_o, + sel => wire_nl0Ol0O_sel + ); + wire_nl0Ol1i_w_lg_o5431w(0) <= NOT wire_nl0Ol1i_o; + wire_nl0Ol1i_data <= ( n10iOii & n1010Oi & n11iliO & n10000l & n11li0i & n10i10O & n11O1il & n10iOii); + wire_nl0Ol1i_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Ol1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Ol1i_data, + o => wire_nl0Ol1i_o, + sel => wire_nl0Ol1i_sel + ); + wire_nl0Ol1l_w_lg_o5618w(0) <= NOT wire_nl0Ol1l_o; + wire_nl0Ol1l_data <= ( n10iO0i & n1010il & n11il0i & n10001l & n11li1i & n10i11O & n11O10l & n10iO0i); + wire_nl0Ol1l_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Ol1l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Ol1l_data, + o => wire_nl0Ol1l_o, + sel => wire_nl0Ol1l_sel + ); + wire_nl0Ol1O_w_lg_o5434w(0) <= NOT wire_nl0Ol1O_o; + wire_nl0Ol1O_data <= ( n10iO1i & n10101O & n11iiOl & n1001Ol & n11l0Oi & n100OOO & n11O11l & n10iO1i); + wire_nl0Ol1O_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Ol1O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Ol1O_data, + o => wire_nl0Ol1O_o, + sel => wire_nl0Ol1O_sel + ); + wire_nl0Olii_w_lg_o5460w(0) <= NOT wire_nl0Olii_o; + wire_nl0Olii_data <= ( n10il0i & n11OOOi & n11i0iO & n10011l & n11l01i & n100O1O & n11lO0l & n10il0i); + wire_nl0Olii_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Olii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Olii_data, + o => wire_nl0Olii_o, + sel => wire_nl0Olii_sel + ); + wire_nl0Olil_w_lg_o5469w(0) <= NOT wire_nl0Olil_o; + wire_nl0Olil_data <= ( n10il1i & n11OOil & n11i00i & n101OOl & n11l1Oi & n100lOO & n11lO1l & n10il1i); + wire_nl0Olil_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Olil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Olil_data, + o => wire_nl0Olil_o, + sel => wire_nl0Olil_sel + ); + wire_nl0OliO_w_lg_o5479w(0) <= NOT wire_nl0OliO_o; + wire_nl0OliO_data <= ( n10iiOi & n11OO1O & n11i1Ol & n101Oll & n11l1li & n100llO & n11llOl & n10iiOi); + wire_nl0OliO_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OliO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OliO_data, + o => wire_nl0OliO_o, + sel => wire_nl0OliO_sel + ); + wire_nl0Olli_w_lg_o5490w(0) <= NOT wire_nl0Olli_o; + wire_nl0Olli_data <= ( n10iili & n11OlOi & n11i1iO & n101Oil & n11l1ii & n100liO & n11llll & n10iili); + wire_nl0Olli_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Olli : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Olli_data, + o => wire_nl0Olli_o, + sel => wire_nl0Olli_sel + ); + wire_nl0Olll_w_lg_o5502w(0) <= NOT wire_nl0Olll_o; + wire_nl0Olll_data <= ( n10iiii & n11Olil & n11i10i & n101O0l & n11l10i & n100l0O & n11llil & n10iiii); + wire_nl0Olll_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0Olll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0Olll_data, + o => wire_nl0Olll_o, + sel => wire_nl0Olll_sel + ); + wire_nl0OllO_w_lg_o5515w(0) <= NOT wire_nl0OllO_o; + wire_nl0OllO_data <= ( n10ii0i & n11Ol1O & n110OOl & n101O1l & n11l11i & n100l1O & n11ll0l & n10ii0i); + wire_nl0OllO_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OllO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OllO_data, + o => wire_nl0OllO_o, + sel => wire_nl0OllO_sel + ); + wire_nl0OlOi_w_lg_o5529w(0) <= NOT wire_nl0OlOi_o; + wire_nl0OlOi_data <= ( n10ii1i & n11OiOi & n110OiO & n101lOl & n11iOOi & n100iOO & n11ll1l & n10ii1i); + wire_nl0OlOi_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OlOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OlOi_data, + o => wire_nl0OlOi_o, + sel => wire_nl0OlOi_sel + ); + wire_nl0OlOl_w_lg_o5544w(0) <= NOT wire_nl0OlOl_o; + wire_nl0OlOl_data <= ( n10i0Oi & n11Oiil & n110O0i & n101lll & n11iOli & n100ilO & n11liOl & n10i0Oi); + wire_nl0OlOl_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OlOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OlOl_data, + o => wire_nl0OlOl_o, + sel => wire_nl0OlOl_sel + ); + wire_nl0OlOO_w_lg_o5560w(0) <= NOT wire_nl0OlOO_o; + wire_nl0OlOO_data <= ( n10i0li & n11Oi1O & "0" & n101lil & "0" & n100iiO & "0" & n10i0li); + wire_nl0OlOO_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OlOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OlOO_data, + o => wire_nl0OlOO_o, + sel => wire_nl0OlOO_sel + ); + wire_nl0OO1i_w_lg_o5577w(0) <= NOT wire_nl0OO1i_o; + wire_nl0OO1i_data <= ( n10i0ii & n11O0Oi & "0" & n101l0l & "0" & n100i0O & "0" & n10i0ii); + wire_nl0OO1i_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OO1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OO1i_data, + o => wire_nl0OO1i_o, + sel => wire_nl0OO1i_sel + ); + wire_nl0OO1l_w_lg_o5595w(0) <= NOT wire_nl0OO1l_o; + wire_nl0OO1l_data <= ( n10i00i & n11O0il & "0" & n101l1l & "0" & n100i1O & "0" & n10i00i); + wire_nl0OO1l_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OO1l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OO1l_data, + o => wire_nl0OO1l_o, + sel => wire_nl0OO1l_sel + ); + wire_nl0OO1O_w_lg_o13557w(0) <= wire_nl0OO1O_o AND wire_nl0OO1l_w_lg_o5595w(0); + wire_nl0OO1O_data <= ( n10i01i & n11O01O & "0" & n101iOl & "0" & n1000OO & "0" & n10i01i); + wire_nl0OO1O_sel <= ( comp_pat_size(2 DOWNTO 0)); + nl0OO1O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0OO1O_data, + o => wire_nl0OO1O_o, + sel => wire_nl0OO1O_sel + ); + wire_nl100i_data <= ( nliOll & nliOll & nliOll & nliOll & nliOll & nliOll & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOll & nliOll & nliOll & nliOll & nliOll & nliOll & nliOll & nliOll & nliOll & nl11il & nl11il & nl11il & nl11il & nl11il & nl11il & nl11il & nl11il); + wire_nl100i_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl100i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl100i_data, + o => wire_nl100i_o, + sel => wire_nl100i_sel + ); + wire_nl101i_data <= ( nliOil & nliOil & nliOil & nliOil & nliOil & nliOil & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOil & nliOil & nliOil & nliOil & nliOil & nliOil & nliOil & nliOil & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli); + wire_nl101i_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl101i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl101i_data, + o => wire_nl101i_o, + sel => wire_nl101i_sel + ); + wire_nl101l_data <= ( nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliOiO & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOll); + wire_nl101l_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl101l : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl101l_data, + o => wire_nl101l_o, + sel => wire_nl101l_sel + ); + wire_nl101O_data <= ( nliOli & nliOli & nliOli & nliOli & nliOli & nliOli & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO & nliOli & nliOli & nliOli & nliOli & nliOli & nliOli & nliOli & nliOli & nliOli & nl11ii & nl11ii & nl11ii & nl11ii & nl11ii & nl11ii & nl11ii & nl11ii); + wire_nl101O_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl101O : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl101O_data, + o => wire_nl101O_o, + sel => wire_nl101O_sel + ); + wire_nl11li_data <= ( nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nlilil & nliliO & nlilli & nlilll & nlillO & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nliO1l & nlillO & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i); + wire_nl11li_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl11li : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl11li_data, + o => wire_nl11li_o, + sel => wire_nl11li_sel + ); + wire_nl11ll_data <= ( nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliliO & nlilli & nlilll & nlillO & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nliO1O & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l); + wire_nl11ll_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl11ll : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl11ll_data, + o => wire_nl11ll_o, + sel => wire_nl11ll_sel + ); + wire_nl11lO_data <= ( nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nlilli & nlilll & nlillO & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nliO0i & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O); + wire_nl11lO_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl11lO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl11lO_data, + o => wire_nl11lO_o, + sel => wire_nl11lO_sel + ); + wire_nl11Oi_data <= ( nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nlilll & nlillO & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nliO0l & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii); + wire_nl11Oi_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl11Oi : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl11Oi_data, + o => wire_nl11Oi_o, + sel => wire_nl11Oi_sel + ); + wire_nl11Ol_data <= ( nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nlillO & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliO0O & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil); + wire_nl11Ol_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl11Ol : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl11Ol_data, + o => wire_nl11Ol_o, + sel => wire_nl11Ol_sel + ); + wire_nl11OO_data <= ( nliOii & nliOii & nliOii & nliOii & nliOii & nliOii & nlilOi & nlilOl & nlilOO & nliO1i & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOii & nliOii & nliOii & nliOii & nliOii & nliOii & nliOii & nliOii & nliO1l & nliO1O & nliO0i & nliO0l & nliO0O & nliOii & nliOil & nliOiO); + wire_nl11OO_sel <= ( pmadwidth(0) & wire_nl011l_dataout & wire_nl011i_dataout & wire_nl1OOO_dataout & wire_nl1OOl_dataout); + nl11OO : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl11OO_data, + o => wire_nl11OO_o, + sel => wire_nl11OO_sel + ); + wire_nl1liiO_w_lg_o16992w(0) <= NOT wire_nl1liiO_o; + wire_nl1liiO_data <= ( wire_nl1llOl_o & wire_nl1O10i_o & wire_nl1O00l_dataout & wire_nl1O0OO_dataout); + wire_nl1liiO_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1liiO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1liiO_data, + o => wire_nl1liiO_o, + sel => wire_nl1liiO_sel + ); + wire_nl1lili_w_lg_w_lg_o16990w17009w(0) <= wire_nl1lili_w_lg_o16990w(0) AND wire_nl1liiO_w_lg_o16992w(0); + wire_nl1lili_w_lg_w_lg_o16990w16991w(0) <= wire_nl1lili_w_lg_o16990w(0) AND wire_nl1liiO_o; + wire_nl1lili_w_lg_o16993w(0) <= wire_nl1lili_o AND wire_nl1liiO_w_lg_o16992w(0); + wire_nl1lili_w_lg_o16990w(0) <= NOT wire_nl1lili_o; + wire_nl1lili_data <= ( wire_nl1llOO_o & wire_nl1O10l_o & wire_nl1O00O_dataout & wire_nl1Oi1i_dataout); + wire_nl1lili_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1lili : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lili_data, + o => wire_nl1lili_o, + sel => wire_nl1lili_sel + ); + wire_nl1lill_w_lg_w_lg_o16982w17179w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1iOl; + wire_nl1lill_w_lg_w_lg_o16982w17174w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1iOO; + wire_nl1lill_w_lg_w_lg_o16982w17167w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1l1i; + wire_nl1lill_w_lg_w_lg_o16982w17164w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1l1l; + wire_nl1lill_w_lg_w_lg_o16982w17026w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1O0O; + wire_nl1lill_w_lg_w_lg_o16982w17021w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1Oii; + wire_nl1lill_w_lg_w_lg_o16982w17006w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1Oil; + wire_nl1lill_w_lg_w_lg_o16982w17003w(0) <= wire_nl1lill_w_lg_o16982w(0) AND nlOO1OiO; + wire_nl1lill_w_lg_o17010w(0) <= wire_nl1lill_o AND wire_nl1lili_w_lg_w_lg_o16990w17009w(0); + wire_nl1lill_w_lg_o17029w(0) <= wire_nl1lill_o AND wire_nl1lili_w_lg_w_lg_o16990w16991w(0); + wire_nl1lill_w_lg_o17032w(0) <= wire_nl1lill_o AND wire_nl1lili_w_lg_o16993w(0); + wire_nl1lill_w_lg_o16982w(0) <= NOT wire_nl1lill_o; + wire_nl1lill_data <= ( wire_nl1lO1i_o & wire_nl1O10O_o & wire_nl1O0ii_dataout & wire_nl1Oi1l_dataout); + wire_nl1lill_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1lill : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lill_data, + o => wire_nl1lill_o, + sel => wire_nl1lill_sel + ); + wire_nl1lilO_w_lg_w_lg_o16913w17152w(0) <= wire_nl1lilO_w_lg_o16913w(0) AND nlOO1l1O; + wire_nl1lilO_w_lg_w_lg_o16913w17112w(0) <= wire_nl1lilO_w_lg_o16913w(0) AND nlOO1lii; + wire_nl1lilO_w_lg_o17180w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17179w(0); + wire_nl1lilO_w_lg_o17175w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17174w(0); + wire_nl1lilO_w_lg_o17168w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17167w(0); + wire_nl1lilO_w_lg_o17165w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17164w(0); + wire_nl1lilO_w_lg_o17027w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17026w(0); + wire_nl1lilO_w_lg_o17022w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17021w(0); + wire_nl1lilO_w_lg_o17007w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17006w(0); + wire_nl1lilO_w_lg_o17004w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_w_lg_o16982w17003w(0); + wire_nl1lilO_w_lg_o17011w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_o17010w(0); + wire_nl1lilO_w_lg_o17030w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_o17029w(0); + wire_nl1lilO_w_lg_o17033w(0) <= wire_nl1lilO_o AND wire_nl1lill_w_lg_o17032w(0); + wire_nl1lilO_w_lg_o16979w(0) <= wire_nl1lilO_o AND wire_nl1lill_o; + wire_nl1lilO_w_lg_o16913w(0) <= NOT wire_nl1lilO_o; + wire_nl1lilO_data <= ( wire_nl1lO1l_o & wire_nl1O1ii_o & wire_nl1O0il_dataout & wire_nl1Oi1O_dataout); + wire_nl1lilO_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1lilO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lilO_data, + o => wire_nl1lilO_o, + sel => wire_nl1lilO_sel + ); + wire_nl1liOi_w_lg_w_lg_o16843w16914w(0) <= wire_nl1liOi_w_lg_o16843w(0) AND wire_nl1lilO_w_lg_o16913w(0); + wire_nl1liOi_w_lg_w_lg_o16843w16844w(0) <= wire_nl1liOi_w_lg_o16843w(0) AND nlOO000i; + wire_nl1liOi_w_lg_w_lg_o16843w16907w(0) <= wire_nl1liOi_w_lg_o16843w(0) AND nlOO01lO; + wire_nl1liOi_w_lg_w_lg_o16843w16955w(0) <= wire_nl1liOi_w_lg_o16843w(0) AND nlOO1OOl; + wire_nl1liOi_w_lg_o16980w(0) <= wire_nl1liOi_o AND wire_nl1lilO_w_lg_o16979w(0); + wire_nl1liOi_w_lg_o16847w(0) <= wire_nl1liOi_o AND nlOO001O; + wire_nl1liOi_w_lg_o16925w(0) <= wire_nl1liOi_o AND nlOO01lO; + wire_nl1liOi_w_lg_o16931w(0) <= wire_nl1liOi_o AND wire_nl1lilO_o; + wire_nl1liOi_w_lg_o16843w(0) <= NOT wire_nl1liOi_o; + wire_nl1liOi_data <= ( wire_nl1lO1O_o & wire_nl1O1il_o & wire_nl1O0iO_dataout & wire_nl1Oi0i_dataout); + wire_nl1liOi_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1liOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1liOi_data, + o => wire_nl1liOi_o, + sel => wire_nl1liOi_sel + ); + wire_nl1liOl_w_lg_w_lg_o16842w16915w(0) <= wire_nl1liOl_w_lg_o16842w(0) AND wire_nl1liOi_w_lg_w_lg_o16843w16914w(0); + wire_nl1liOl_w_lg_w_lg_o16842w16908w(0) <= wire_nl1liOl_w_lg_o16842w(0) AND wire_nl1liOi_w_lg_w_lg_o16843w16907w(0); + wire_nl1liOl_w_lg_w_lg_o16842w16987w(0) <= wire_nl1liOl_w_lg_o16842w(0) AND wire_nl1liOi_o; + wire_nl1liOl_w_lg_w_lg_w_lg_o16842w16910w16911w(0) <= wire_nl1liOl_w_lg_w_lg_o16842w16910w(0) AND nlOO000i; + wire_nl1liOl_w_lg_w16916w16922w(0) <= wire_nl1liOl_w16916w(0) AND wire_w_lg_w_lg_nlOO01Oi16918w16921w(0); + wire_nl1liOl_w16941w(0) <= wire_nl1liOl_w_lg_w_lg_w_lg_w_lg_o16926w16927w16930w16933w(0) AND wire_w_lg_w_lg_nlOO01Ol16936w16940w(0); + wire_nl1liOl_w_lg_w_lg_o16928w16929w(0) <= wire_nl1liOl_w_lg_o16928w(0) AND nlOO001O; + wire_nl1liOl_w_lg_o16956w(0) <= wire_nl1liOl_o AND wire_nl1liOi_w_lg_w_lg_o16843w16955w(0); + wire_nl1liOl_w_lg_o16981w(0) <= wire_nl1liOl_o AND wire_nl1liOi_w_lg_o16980w(0); + wire_nl1liOl_w_lg_o16848w(0) <= wire_nl1liOl_o AND wire_nl1liOi_w_lg_o16847w(0); + wire_nl1liOl_w_lg_o16926w(0) <= wire_nl1liOl_o AND wire_nl1liOi_w_lg_o16925w(0); + wire_nl1liOl_w_lg_o16932w(0) <= wire_nl1liOl_o AND wire_nl1liOi_w_lg_o16931w(0); + wire_nl1liOl_w_lg_o16988w(0) <= wire_nl1liOl_o AND wire_nl1liOi_w_lg_o16843w(0); + wire_nl1liOl_w_lg_o16867w(0) <= wire_nl1liOl_o AND wire_nl1liOi_o; + wire_nl1liOl_w_lg_o16842w(0) <= NOT wire_nl1liOl_o; + wire_nl1liOl_w_lg_w_lg_w_lg_o16842w16908w16909w(0) <= wire_nl1liOl_w_lg_w_lg_o16842w16908w(0) OR nlOO000l; + wire_nl1liOl_w_lg_w_lg_o16926w16927w(0) <= wire_nl1liOl_w_lg_o16926w(0) OR nlOO000O; + wire_nl1liOl_w_lg_w_lg_o16842w16910w(0) <= wire_nl1liOl_w_lg_o16842w(0) OR wire_nl1liOi_w_lg_o16843w(0); + wire_nl1liOl_w_lg_w_lg_w_lg_w_lg_o16842w16908w16909w16912w(0) <= wire_nl1liOl_w_lg_w_lg_w_lg_o16842w16908w16909w(0) OR wire_nl1liOl_w_lg_w_lg_w_lg_o16842w16910w16911w(0); + wire_nl1liOl_w_lg_w_lg_w_lg_o16926w16927w16930w(0) <= wire_nl1liOl_w_lg_w_lg_o16926w16927w(0) OR wire_nl1liOl_w_lg_w_lg_o16928w16929w(0); + wire_nl1liOl_w16916w(0) <= wire_nl1liOl_w_lg_w_lg_w_lg_w_lg_o16842w16908w16909w16912w(0) OR wire_nl1liOl_w_lg_w_lg_o16842w16915w(0); + wire_nl1liOl_w_lg_w_lg_w_lg_w_lg_o16926w16927w16930w16933w(0) <= wire_nl1liOl_w_lg_w_lg_w_lg_o16926w16927w16930w(0) OR wire_nl1liOl_w_lg_o16932w(0); + wire_nl1liOl_w_lg_o16928w(0) <= wire_nl1liOl_o OR wire_nl1liOi_o; + wire_nl1liOl_data <= ( wire_nl1lO0i_o & wire_nl1O1iO_o & wire_nl1O0li_dataout & wire_nl1Oi0l_dataout); + wire_nl1liOl_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1liOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1liOl_data, + o => wire_nl1liOl_o, + sel => wire_nl1liOl_sel + ); + wire_nl1liOO_w_lg_w_lg_o16856w17040w(0) <= wire_nl1liOO_w_lg_o16856w(0) AND nlOO1O0i; + wire_nl1liOO_w_lg_w_lg_o16856w16963w(0) <= wire_nl1liOO_w_lg_o16856w(0) AND nlOO1Oll; + wire_nl1liOO_w_lg_o16868w(0) <= wire_nl1liOO_o AND wire_nl1liOl_w_lg_o16867w(0); + wire_nl1liOO_w_lg_o17121w(0) <= wire_nl1liOO_o AND nlOO1O0i; + wire_nl1liOO_w_lg_o16856w(0) <= NOT wire_nl1liOO_o; + wire_nl1liOO_data <= ( wire_nl1lO0l_o & wire_nl1O1li_o & wire_nl1O0ll_dataout & wire_nl1Oi0O_dataout); + wire_nl1liOO_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1liOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1liOO_data, + o => wire_nl1liOO_o, + sel => wire_nl1liOO_sel + ); + wire_nl1ll0i_w_lg_o16648w(0) <= NOT wire_nl1ll0i_o; + wire_nl1ll0i_data <= ( wire_nl1lOiO_o & wire_nl1O1lO_o & nl01lil & nl01l0O); + wire_nl1ll0i_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1ll0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1ll0i_data, + o => wire_nl1ll0i_o, + sel => wire_nl1ll0i_sel + ); + wire_nl1ll0l_w_lg_w_lg_o16646w16665w(0) <= wire_nl1ll0l_w_lg_o16646w(0) AND wire_nl1ll0i_w_lg_o16648w(0); + wire_nl1ll0l_w_lg_w_lg_o16646w16647w(0) <= wire_nl1ll0l_w_lg_o16646w(0) AND wire_nl1ll0i_o; + wire_nl1ll0l_w_lg_o16649w(0) <= wire_nl1ll0l_o AND wire_nl1ll0i_w_lg_o16648w(0); + wire_nl1ll0l_w_lg_o16646w(0) <= NOT wire_nl1ll0l_o; + wire_nl1ll0l_data <= ( wire_nl1lOli_o & wire_nl1O1Oi_o & nl01liO & nl01lii); + wire_nl1ll0l_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1ll0l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1ll0l_data, + o => wire_nl1ll0l_o, + sel => wire_nl1ll0l_sel + ); + wire_nl1ll0O_w_lg_w_lg_o16638w16835w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO00il; + wire_nl1ll0O_w_lg_w_lg_o16638w16830w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO00iO; + wire_nl1ll0O_w_lg_w_lg_o16638w16823w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO00li; + wire_nl1ll0O_w_lg_w_lg_o16638w16820w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO00ll; + wire_nl1ll0O_w_lg_w_lg_o16638w16682w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO0iOO; + wire_nl1ll0O_w_lg_w_lg_o16638w16677w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO0l1i; + wire_nl1ll0O_w_lg_w_lg_o16638w16662w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO0l1l; + wire_nl1ll0O_w_lg_w_lg_o16638w16659w(0) <= wire_nl1ll0O_w_lg_o16638w(0) AND nlOO0l1O; + wire_nl1ll0O_w_lg_o16666w(0) <= wire_nl1ll0O_o AND wire_nl1ll0l_w_lg_w_lg_o16646w16665w(0); + wire_nl1ll0O_w_lg_o16685w(0) <= wire_nl1ll0O_o AND wire_nl1ll0l_w_lg_w_lg_o16646w16647w(0); + wire_nl1ll0O_w_lg_o16688w(0) <= wire_nl1ll0O_o AND wire_nl1ll0l_w_lg_o16649w(0); + wire_nl1ll0O_w_lg_o16638w(0) <= NOT wire_nl1ll0O_o; + wire_nl1ll0O_data <= ( wire_nl1lOll_o & wire_nl1O1Ol_o & nl01lli & nl01lil); + wire_nl1ll0O_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1ll0O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1ll0O_data, + o => wire_nl1ll0O_o, + sel => wire_nl1ll0O_sel + ); + wire_nl1ll1i_w_lg_w_lg_w_lg_o16855w17043w17044w(0) <= wire_nl1ll1i_w_lg_w_lg_o16855w17043w(0) AND nlOO1O1l; + wire_nl1ll1i_w_lg_w_lg_o17045w17046w(0) <= wire_nl1ll1i_w_lg_o17045w(0) AND nlOO1O1l; + wire_nl1ll1i_w_lg_w_lg_o16855w17053w(0) <= wire_nl1ll1i_w_lg_o16855w(0) AND wire_w_lg_nlOO1OOO17052w(0); + wire_nl1ll1i_w_lg_w_lg_o16855w16857w(0) <= wire_nl1ll1i_w_lg_o16855w(0) AND wire_nl1liOO_w_lg_o16856w(0); + wire_nl1ll1i_w_lg_w_lg_o16855w16895w(0) <= wire_nl1ll1i_w_lg_o16855w(0) AND nlOO001i; + wire_nl1ll1i_w_lg_w_lg_o16855w16872w(0) <= wire_nl1ll1i_w_lg_o16855w(0) AND nlOO001l; + wire_nl1ll1i_w_lg_w_lg_o16855w17043w(0) <= wire_nl1ll1i_w_lg_o16855w(0) AND nlOO011i; + wire_nl1ll1i_w_lg_w_lg_o16855w16880w(0) <= wire_nl1ll1i_w_lg_o16855w(0) AND wire_nl1liOl_o; + wire_nl1ll1i_w_lg_w_lg_o16855w17061w(0) <= wire_nl1ll1i_w_lg_o16855w(0) AND wire_nl1liOO_o; + wire_nl1ll1i_w_lg_o17050w(0) <= wire_nl1ll1i_o AND wire_w_lg_nlOO011i17049w(0); + wire_nl1ll1i_w_lg_o16869w(0) <= wire_nl1ll1i_o AND wire_nl1liOO_w_lg_o16868w(0); + wire_nl1ll1i_w_lg_o17122w(0) <= wire_nl1ll1i_o AND wire_nl1liOO_w_lg_o17121w(0); + wire_nl1ll1i_w_lg_o16883w(0) <= wire_nl1ll1i_o AND wire_nl1liOl_w_lg_o16842w(0); + wire_nl1ll1i_w_lg_o17062w(0) <= wire_nl1ll1i_o AND wire_nl1liOO_w_lg_o16856w(0); + wire_nl1ll1i_w_lg_o16876w(0) <= wire_nl1ll1i_o AND nlOO001i; + wire_nl1ll1i_w_lg_o16901w(0) <= wire_nl1ll1i_o AND nlOO001l; + wire_nl1ll1i_w_lg_o17045w(0) <= wire_nl1ll1i_o AND nlOO1OOO; + wire_nl1ll1i_w_lg_o16850w(0) <= wire_nl1ll1i_o AND wire_nl1liOO_o; + wire_nl1ll1i_w_lg_o16855w(0) <= NOT wire_nl1ll1i_o; + wire_nl1ll1i_w_lg_w_lg_w_lg_w_lg_o16855w17043w17044w17047w(0) <= wire_nl1ll1i_w_lg_w_lg_w_lg_o16855w17043w17044w(0) OR wire_nl1ll1i_w_lg_w_lg_o17045w17046w(0); + wire_nl1ll1i_w_lg_w_lg_o16855w16919w(0) <= wire_nl1ll1i_w_lg_o16855w(0) OR wire_nl1liOO_w_lg_o16856w(0); + wire_nl1ll1i_w_lg_o16938w(0) <= wire_nl1ll1i_o OR wire_nl1liOO_o; + wire_nl1ll1i_data <= ( wire_nl1lO0O_o & wire_nl1O1ll_o & wire_nl1O0lO_dataout & wire_nl1Oiii_dataout); + wire_nl1ll1i_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1ll1i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1ll1i_data, + o => wire_nl1ll1i_o, + sel => wire_nl1ll1i_sel + ); + wire_nl1ll1l_w_lg_w_lg_o16854w17054w(0) <= wire_nl1ll1l_w_lg_o16854w(0) AND wire_nl1ll1i_w_lg_w_lg_o16855w17053w(0); + wire_nl1ll1l_w_lg_w_lg_o16854w16891w(0) <= wire_nl1ll1l_w_lg_o16854w(0) AND nlOO01Oi; + wire_nl1ll1l_w_lg_w_lg_o16854w17093w(0) <= wire_nl1ll1l_w_lg_o16854w(0) AND nlOO1lOi; + wire_nl1ll1l_w_lg_w_lg_o16854w17088w(0) <= wire_nl1ll1l_w_lg_o16854w(0) AND nlOO1lOl; + wire_nl1ll1l_w_lg_w_lg_o16854w17074w(0) <= wire_nl1ll1l_w_lg_o16854w(0) AND nlOO1lOO; + wire_nl1ll1l_w_lg_w_lg_o16854w17071w(0) <= wire_nl1ll1l_w_lg_o16854w(0) AND nlOO1O1i; + wire_nl1ll1l_w_lg_o17077w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_w_lg_o16855w16857w(0); + wire_nl1ll1l_w_lg_o17096w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_w_lg_o16855w17061w(0); + wire_nl1ll1l_w_lg_o17051w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_o17050w(0); + wire_nl1ll1l_w_lg_o16870w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_o16869w(0); + wire_nl1ll1l_w_lg_o16884w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_o16883w(0); + wire_nl1ll1l_w_lg_o17099w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_o17062w(0); + wire_nl1ll1l_w_lg_o16877w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_o16876w(0); + wire_nl1ll1l_w_lg_o16902w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_o16901w(0); + wire_nl1ll1l_w_lg_o16851w(0) <= wire_nl1ll1l_o AND wire_nl1ll1i_w_lg_o16850w(0); + wire_nl1ll1l_w_lg_o16890w(0) <= wire_nl1ll1l_o AND nlOO01Ol; + wire_nl1ll1l_w_lg_o16854w(0) <= NOT wire_nl1ll1l_o; + wire_nl1ll1l_w_lg_w_lg_o17051w17055w(0) <= wire_nl1ll1l_w_lg_o17051w(0) OR wire_nl1ll1l_w_lg_w_lg_o16854w17054w(0); + wire_nl1ll1l_w_lg_w_lg_o16890w16892w(0) <= wire_nl1ll1l_w_lg_o16890w(0) OR wire_nl1ll1l_w_lg_w_lg_o16854w16891w(0); + wire_nl1ll1l_data <= ( wire_nl1lOii_o & "0" & wire_nl1O0Oi_dataout & "0"); + wire_nl1ll1l_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1ll1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1ll1l_data, + o => wire_nl1ll1l_o, + sel => wire_nl1ll1l_sel + ); + wire_nl1ll1O_w_lg_w_lg_o16937w16939w(0) <= wire_nl1ll1O_w_lg_o16937w(0) AND wire_nl1ll1i_w_lg_o16938w(0); + wire_nl1ll1O_w_lg_w_lg_o16853w16969w(0) <= wire_nl1ll1O_w_lg_o16853w(0) AND nlOO1Oll; + wire_nl1ll1O_w_lg_o17094w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_w_lg_o16854w17093w(0); + wire_nl1ll1O_w_lg_o17089w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_w_lg_o16854w17088w(0); + wire_nl1ll1O_w_lg_o17075w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_w_lg_o16854w17074w(0); + wire_nl1ll1O_w_lg_o17072w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_w_lg_o16854w17071w(0); + wire_nl1ll1O_w_lg_o17078w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_o17077w(0); + wire_nl1ll1O_w_lg_o17097w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_o17096w(0); + wire_nl1ll1O_w_lg_o16885w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_o16884w(0); + wire_nl1ll1O_w_lg_o17100w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_o17099w(0); + wire_nl1ll1O_w_lg_o16878w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_o16877w(0); + wire_nl1ll1O_w_lg_o16903w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_o16902w(0); + wire_nl1ll1O_w_lg_o16852w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_w_lg_o16851w(0); + wire_nl1ll1O_w_lg_o16937w(0) <= wire_nl1ll1O_o AND wire_nl1ll1l_o; + wire_nl1ll1O_w_lg_o16853w(0) <= NOT wire_nl1ll1O_o; + wire_nl1ll1O_w_lg_o16934w(0) <= wire_nl1ll1O_o OR wire_nl1ll1l_o; + wire_nl1ll1O_data <= ( wire_nl1lOil_o & "0" & wire_nl1O0Ol_dataout & "0"); + wire_nl1ll1O_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1ll1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1ll1O_data, + o => wire_nl1ll1O_o, + sel => wire_nl1ll1O_sel + ); + wire_nl1llii_w_lg_w_lg_o16569w16808w(0) <= wire_nl1llii_w_lg_o16569w(0) AND nlOO00lO; + wire_nl1llii_w_lg_w_lg_o16569w16768w(0) <= wire_nl1llii_w_lg_o16569w(0) AND nlOO0i1i; + wire_nl1llii_w_lg_o16836w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16835w(0); + wire_nl1llii_w_lg_o16831w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16830w(0); + wire_nl1llii_w_lg_o16824w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16823w(0); + wire_nl1llii_w_lg_o16821w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16820w(0); + wire_nl1llii_w_lg_o16683w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16682w(0); + wire_nl1llii_w_lg_o16678w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16677w(0); + wire_nl1llii_w_lg_o16663w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16662w(0); + wire_nl1llii_w_lg_o16660w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_w_lg_o16638w16659w(0); + wire_nl1llii_w_lg_o16667w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_o16666w(0); + wire_nl1llii_w_lg_o16686w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_o16685w(0); + wire_nl1llii_w_lg_o16689w(0) <= wire_nl1llii_o AND wire_nl1ll0O_w_lg_o16688w(0); + wire_nl1llii_w_lg_o16635w(0) <= wire_nl1llii_o AND wire_nl1ll0O_o; + wire_nl1llii_w_lg_o16569w(0) <= NOT wire_nl1llii_o; + wire_nl1llii_data <= ( wire_nl1lOlO_o & wire_nl1O1OO_o & nl01lll & nl01liO); + wire_nl1llii_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1llii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1llii_data, + o => wire_nl1llii_o, + sel => wire_nl1llii_sel + ); + wire_nl1llil_w_lg_w_lg_o16499w16570w(0) <= wire_nl1llil_w_lg_o16499w(0) AND wire_nl1llii_w_lg_o16569w(0); + wire_nl1llil_w_lg_w_lg_o16499w16611w(0) <= wire_nl1llil_w_lg_o16499w(0) AND nlOO0lil; + wire_nl1llil_w_lg_w_lg_o16499w16563w(0) <= wire_nl1llil_w_lg_o16499w(0) AND nlOO0O0O; + wire_nl1llil_w_lg_w_lg_o16499w16500w(0) <= wire_nl1llil_w_lg_o16499w(0) AND nlOO0OOi; + wire_nl1llil_w_lg_o16636w(0) <= wire_nl1llil_o AND wire_nl1llii_w_lg_o16635w(0); + wire_nl1llil_w_lg_o16581w(0) <= wire_nl1llil_o AND nlOO0O0O; + wire_nl1llil_w_lg_o16503w(0) <= wire_nl1llil_o AND nlOO0OlO; + wire_nl1llil_w_lg_o16587w(0) <= wire_nl1llil_o AND wire_nl1llii_o; + wire_nl1llil_w_lg_o16499w(0) <= NOT wire_nl1llil_o; + wire_nl1llil_data <= ( wire_nl1lOOi_o & wire_nl1O01i_o & nl01llO & nl01lli); + wire_nl1llil_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1llil : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1llil_data, + o => wire_nl1llil_o, + sel => wire_nl1llil_sel + ); + wire_nl1lliO_w_lg_w_lg_o16498w16571w(0) <= wire_nl1lliO_w_lg_o16498w(0) AND wire_nl1llil_w_lg_w_lg_o16499w16570w(0); + wire_nl1lliO_w_lg_w_lg_o16498w16564w(0) <= wire_nl1lliO_w_lg_o16498w(0) AND wire_nl1llil_w_lg_w_lg_o16499w16563w(0); + wire_nl1lliO_w_lg_w_lg_o16498w16643w(0) <= wire_nl1lliO_w_lg_o16498w(0) AND wire_nl1llil_o; + wire_nl1lliO_w_lg_w_lg_w_lg_o16498w16566w16567w(0) <= wire_nl1lliO_w_lg_w_lg_o16498w16566w(0) AND nlOO0OOi; + wire_nl1lliO_w_lg_w16572w16578w(0) <= wire_nl1lliO_w16572w(0) AND wire_w_lg_w_lg_nlOO0Oii16574w16577w(0); + wire_nl1lliO_w16597w(0) <= wire_nl1lliO_w_lg_w_lg_w_lg_w_lg_o16582w16583w16586w16589w(0) AND wire_w_lg_w_lg_nlOO0Oil16592w16596w(0); + wire_nl1lliO_w_lg_w_lg_o16584w16585w(0) <= wire_nl1lliO_w_lg_o16584w(0) AND nlOO0OlO; + wire_nl1lliO_w_lg_o16612w(0) <= wire_nl1lliO_o AND wire_nl1llil_w_lg_w_lg_o16499w16611w(0); + wire_nl1lliO_w_lg_o16637w(0) <= wire_nl1lliO_o AND wire_nl1llil_w_lg_o16636w(0); + wire_nl1lliO_w_lg_o16582w(0) <= wire_nl1lliO_o AND wire_nl1llil_w_lg_o16581w(0); + wire_nl1lliO_w_lg_o16504w(0) <= wire_nl1lliO_o AND wire_nl1llil_w_lg_o16503w(0); + wire_nl1lliO_w_lg_o16588w(0) <= wire_nl1lliO_o AND wire_nl1llil_w_lg_o16587w(0); + wire_nl1lliO_w_lg_o16644w(0) <= wire_nl1lliO_o AND wire_nl1llil_w_lg_o16499w(0); + wire_nl1lliO_w_lg_o16523w(0) <= wire_nl1lliO_o AND wire_nl1llil_o; + wire_nl1lliO_w_lg_o16498w(0) <= NOT wire_nl1lliO_o; + wire_nl1lliO_w_lg_w_lg_w_lg_o16498w16564w16565w(0) <= wire_nl1lliO_w_lg_w_lg_o16498w16564w(0) OR nlOO0OOl; + wire_nl1lliO_w_lg_w_lg_o16582w16583w(0) <= wire_nl1lliO_w_lg_o16582w(0) OR nlOO0OOO; + wire_nl1lliO_w_lg_w_lg_o16498w16566w(0) <= wire_nl1lliO_w_lg_o16498w(0) OR wire_nl1llil_w_lg_o16499w(0); + wire_nl1lliO_w_lg_w_lg_w_lg_w_lg_o16498w16564w16565w16568w(0) <= wire_nl1lliO_w_lg_w_lg_w_lg_o16498w16564w16565w(0) OR wire_nl1lliO_w_lg_w_lg_w_lg_o16498w16566w16567w(0); + wire_nl1lliO_w_lg_w_lg_w_lg_o16582w16583w16586w(0) <= wire_nl1lliO_w_lg_w_lg_o16582w16583w(0) OR wire_nl1lliO_w_lg_w_lg_o16584w16585w(0); + wire_nl1lliO_w16572w(0) <= wire_nl1lliO_w_lg_w_lg_w_lg_w_lg_o16498w16564w16565w16568w(0) OR wire_nl1lliO_w_lg_w_lg_o16498w16571w(0); + wire_nl1lliO_w_lg_w_lg_w_lg_w_lg_o16582w16583w16586w16589w(0) <= wire_nl1lliO_w_lg_w_lg_w_lg_o16582w16583w16586w(0) OR wire_nl1lliO_w_lg_o16588w(0); + wire_nl1lliO_w_lg_o16584w(0) <= wire_nl1lliO_o OR wire_nl1llil_o; + wire_nl1lliO_data <= ( wire_nl1lOOl_o & wire_nl1O01l_o & nl01lOi & nl01lll); + wire_nl1lliO_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1lliO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lliO_data, + o => wire_nl1lliO_o, + sel => wire_nl1lliO_sel + ); + wire_nl1llli_w_lg_w_lg_o16512w16696w(0) <= wire_nl1llli_w_lg_o16512w(0) AND nlOO0iOi; + wire_nl1llli_w_lg_w_lg_o16512w16619w(0) <= wire_nl1llli_w_lg_o16512w(0) AND nlOO0l0l; + wire_nl1llli_w_lg_o16524w(0) <= wire_nl1llli_o AND wire_nl1lliO_w_lg_o16523w(0); + wire_nl1llli_w_lg_o16777w(0) <= wire_nl1llli_o AND nlOO0iOi; + wire_nl1llli_w_lg_o16512w(0) <= NOT wire_nl1llli_o; + wire_nl1llli_data <= ( wire_nl1lOOO_o & wire_nl1O01O_o & nl01lOl & nl01llO); + wire_nl1llli_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1llli : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1llli_data, + o => wire_nl1llli_o, + sel => wire_nl1llli_sel + ); + wire_nl1llll_w_lg_w_lg_w_lg_o16511w16699w16700w(0) <= wire_nl1llll_w_lg_w_lg_o16511w16699w(0) AND nlOO0ill; + wire_nl1llll_w_lg_w_lg_o16701w16702w(0) <= wire_nl1llll_w_lg_o16701w(0) AND nlOO0ill; + wire_nl1llll_w_lg_w_lg_o16511w16709w(0) <= wire_nl1llll_w_lg_o16511w(0) AND wire_w_lg_nlOO0liO16708w(0); + wire_nl1llll_w_lg_w_lg_o16511w16513w(0) <= wire_nl1llll_w_lg_o16511w(0) AND wire_nl1llli_w_lg_o16512w(0); + wire_nl1llll_w_lg_w_lg_o16511w16699w(0) <= wire_nl1llll_w_lg_o16511w(0) AND nlOO0lli; + wire_nl1llll_w_lg_w_lg_o16511w16551w(0) <= wire_nl1llll_w_lg_o16511w(0) AND nlOO0Oli; + wire_nl1llll_w_lg_w_lg_o16511w16528w(0) <= wire_nl1llll_w_lg_o16511w(0) AND nlOO0Oll; + wire_nl1llll_w_lg_w_lg_o16511w16536w(0) <= wire_nl1llll_w_lg_o16511w(0) AND wire_nl1lliO_o; + wire_nl1llll_w_lg_w_lg_o16511w16717w(0) <= wire_nl1llll_w_lg_o16511w(0) AND wire_nl1llli_o; + wire_nl1llll_w_lg_o16706w(0) <= wire_nl1llll_o AND wire_w_lg_nlOO0lli16705w(0); + wire_nl1llll_w_lg_o16525w(0) <= wire_nl1llll_o AND wire_nl1llli_w_lg_o16524w(0); + wire_nl1llll_w_lg_o16778w(0) <= wire_nl1llll_o AND wire_nl1llli_w_lg_o16777w(0); + wire_nl1llll_w_lg_o16539w(0) <= wire_nl1llll_o AND wire_nl1lliO_w_lg_o16498w(0); + wire_nl1llll_w_lg_o16718w(0) <= wire_nl1llll_o AND wire_nl1llli_w_lg_o16512w(0); + wire_nl1llll_w_lg_o16701w(0) <= wire_nl1llll_o AND nlOO0liO; + wire_nl1llll_w_lg_o16532w(0) <= wire_nl1llll_o AND nlOO0Oli; + wire_nl1llll_w_lg_o16557w(0) <= wire_nl1llll_o AND nlOO0Oll; + wire_nl1llll_w_lg_o16506w(0) <= wire_nl1llll_o AND wire_nl1llli_o; + wire_nl1llll_w_lg_o16511w(0) <= NOT wire_nl1llll_o; + wire_nl1llll_w_lg_w_lg_w_lg_w_lg_o16511w16699w16700w16703w(0) <= wire_nl1llll_w_lg_w_lg_w_lg_o16511w16699w16700w(0) OR wire_nl1llll_w_lg_w_lg_o16701w16702w(0); + wire_nl1llll_w_lg_w_lg_o16511w16575w(0) <= wire_nl1llll_w_lg_o16511w(0) OR wire_nl1llli_w_lg_o16512w(0); + wire_nl1llll_w_lg_o16594w(0) <= wire_nl1llll_o OR wire_nl1llli_o; + wire_nl1llll_data <= ( wire_nl1O11i_o & wire_nl1O00i_o & nl01lOO & nl01lOi); + wire_nl1llll_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1llll : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1llll_data, + o => wire_nl1llll_o, + sel => wire_nl1llll_sel + ); + wire_nl1lllO_w_lg_w_lg_o16510w16710w(0) <= wire_nl1lllO_w_lg_o16510w(0) AND wire_nl1llll_w_lg_w_lg_o16511w16709w(0); + wire_nl1lllO_w_lg_w_lg_o16510w16749w(0) <= wire_nl1lllO_w_lg_o16510w(0) AND nlOO0iii; + wire_nl1lllO_w_lg_w_lg_o16510w16744w(0) <= wire_nl1lllO_w_lg_o16510w(0) AND nlOO0iil; + wire_nl1lllO_w_lg_w_lg_o16510w16730w(0) <= wire_nl1lllO_w_lg_o16510w(0) AND nlOO0iiO; + wire_nl1lllO_w_lg_w_lg_o16510w16727w(0) <= wire_nl1lllO_w_lg_o16510w(0) AND nlOO0ili; + wire_nl1lllO_w_lg_w_lg_o16510w16547w(0) <= wire_nl1lllO_w_lg_o16510w(0) AND nlOO0Oii; + wire_nl1lllO_w_lg_o16733w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_w_lg_o16511w16513w(0); + wire_nl1lllO_w_lg_o16752w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_w_lg_o16511w16717w(0); + wire_nl1lllO_w_lg_o16707w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_o16706w(0); + wire_nl1lllO_w_lg_o16526w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_o16525w(0); + wire_nl1lllO_w_lg_o16540w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_o16539w(0); + wire_nl1lllO_w_lg_o16755w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_o16718w(0); + wire_nl1lllO_w_lg_o16533w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_o16532w(0); + wire_nl1lllO_w_lg_o16558w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_o16557w(0); + wire_nl1lllO_w_lg_o16507w(0) <= wire_nl1lllO_o AND wire_nl1llll_w_lg_o16506w(0); + wire_nl1lllO_w_lg_o16546w(0) <= wire_nl1lllO_o AND nlOO0Oil; + wire_nl1lllO_w_lg_o16510w(0) <= NOT wire_nl1lllO_o; + wire_nl1lllO_w_lg_w_lg_o16707w16711w(0) <= wire_nl1lllO_w_lg_o16707w(0) OR wire_nl1lllO_w_lg_w_lg_o16510w16710w(0); + wire_nl1lllO_w_lg_w_lg_o16546w16548w(0) <= wire_nl1lllO_w_lg_o16546w(0) OR wire_nl1lllO_w_lg_w_lg_o16510w16547w(0); + wire_nl1lllO_data <= ( wire_nl1O11l_o & "0" & nl01O1i & "0"); + wire_nl1lllO_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1lllO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lllO_data, + o => wire_nl1lllO_o, + sel => wire_nl1lllO_sel + ); + wire_nl1llOi_w_lg_w_lg_o16593w16595w(0) <= wire_nl1llOi_w_lg_o16593w(0) AND wire_nl1llll_w_lg_o16594w(0); + wire_nl1llOi_w_lg_w_lg_o16509w16625w(0) <= wire_nl1llOi_w_lg_o16509w(0) AND nlOO0l0l; + wire_nl1llOi_w_lg_o16750w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_w_lg_o16510w16749w(0); + wire_nl1llOi_w_lg_o16745w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_w_lg_o16510w16744w(0); + wire_nl1llOi_w_lg_o16731w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_w_lg_o16510w16730w(0); + wire_nl1llOi_w_lg_o16728w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_w_lg_o16510w16727w(0); + wire_nl1llOi_w_lg_o16734w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_o16733w(0); + wire_nl1llOi_w_lg_o16753w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_o16752w(0); + wire_nl1llOi_w_lg_o16541w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_o16540w(0); + wire_nl1llOi_w_lg_o16756w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_o16755w(0); + wire_nl1llOi_w_lg_o16534w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_o16533w(0); + wire_nl1llOi_w_lg_o16559w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_o16558w(0); + wire_nl1llOi_w_lg_o16508w(0) <= wire_nl1llOi_o AND wire_nl1lllO_w_lg_o16507w(0); + wire_nl1llOi_w_lg_o16593w(0) <= wire_nl1llOi_o AND wire_nl1lllO_o; + wire_nl1llOi_w_lg_o16509w(0) <= NOT wire_nl1llOi_o; + wire_nl1llOi_w_lg_o16590w(0) <= wire_nl1llOi_o OR wire_nl1lllO_o; + wire_nl1llOi_data <= ( wire_nl1O11O_o & "0" & nl01O1l & "0"); + wire_nl1llOi_sel <= ( pmadwidth(1 DOWNTO 0)); + nl1llOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1llOi_data, + o => wire_nl1llOi_o, + sel => wire_nl1llOi_sel + ); + wire_nl1llOl_data <= ( nl01lii & nl01O1l & nl01lil & nl01iOi); + wire_nl1llOl_sel <= ( nlli0li & nlli0il); + nl1llOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1llOl_data, + o => wire_nl1llOl_o, + sel => wire_nl1llOl_sel + ); + wire_nl1llOO_data <= ( nl01l0O & nl01O1i & nl01liO & nl01iOl); + wire_nl1llOO_sel <= ( nlli0li & nlli0il); + nl1llOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1llOO_data, + o => wire_nl1llOO_o, + sel => wire_nl1llOO_sel + ); + wire_nl1lO0i_data <= ( nl01l1l & nl01llO & nl01lOi & nl01l1O); + wire_nl1lO0i_sel <= ( nlli0li & nlli0il); + nl1lO0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lO0i_data, + o => wire_nl1lO0i_o, + sel => wire_nl1lO0i_sel + ); + wire_nl1lO0l_data <= ( nl01l1i & nl01lll & nl01lOl & nl01l0i); + wire_nl1lO0l_sel <= ( nlli0li & nlli0il); + nl1lO0l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lO0l_data, + o => wire_nl1lO0l_o, + sel => wire_nl1lO0l_sel + ); + wire_nl1lO0O_data <= ( nl01iOO & nl01lli & nl01lOO & nl01l0l); + wire_nl1lO0O_sel <= ( nlli0li & nlli0il); + nl1lO0O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lO0O_data, + o => wire_nl1lO0O_o, + sel => wire_nl1lO0O_sel + ); + wire_nl1lO1i_data <= ( nl01l0l & nl01lOO & nl01lli & nl01iOO); + wire_nl1lO1i_sel <= ( nlli0li & nlli0il); + nl1lO1i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lO1i_data, + o => wire_nl1lO1i_o, + sel => wire_nl1lO1i_sel + ); + wire_nl1lO1l_data <= ( nl01l0i & nl01lOl & nl01lll & nl01l1i); + wire_nl1lO1l_sel <= ( nlli0li & nlli0il); + nl1lO1l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lO1l_data, + o => wire_nl1lO1l_o, + sel => wire_nl1lO1l_sel + ); + wire_nl1lO1O_data <= ( nl01l1O & nl01lOi & nl01llO & nl01l1l); + wire_nl1lO1O_sel <= ( nlli0li & nlli0il); + nl1lO1O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lO1O_data, + o => wire_nl1lO1O_o, + sel => wire_nl1lO1O_sel + ); + wire_nl1lOii_data <= ( nl01iOl & nl01liO & nl01O1i & nl01l0O); + wire_nl1lOii_sel <= ( nlli0li & nlli0il); + nl1lOii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOii_data, + o => wire_nl1lOii_o, + sel => wire_nl1lOii_sel + ); + wire_nl1lOil_data <= ( nl01iOi & nl01lil & nl01O1l & nl01lii); + wire_nl1lOil_sel <= ( nlli0li & nlli0il); + nl1lOil : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOil_data, + o => wire_nl1lOil_o, + sel => wire_nl1lOil_sel + ); + wire_nl1lOiO_data <= ( nl01O1l & nl01lii & nl01iOi & nl01lil); + wire_nl1lOiO_sel <= ( nlli0li & nlli0il); + nl1lOiO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOiO_data, + o => wire_nl1lOiO_o, + sel => wire_nl1lOiO_sel + ); + wire_nl1lOli_data <= ( nl01O1i & nl01l0O & nl01iOl & nl01liO); + wire_nl1lOli_sel <= ( nlli0li & nlli0il); + nl1lOli : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOli_data, + o => wire_nl1lOli_o, + sel => wire_nl1lOli_sel + ); + wire_nl1lOll_data <= ( nl01lOO & nl01l0l & nl01iOO & nl01lli); + wire_nl1lOll_sel <= ( nlli0li & nlli0il); + nl1lOll : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOll_data, + o => wire_nl1lOll_o, + sel => wire_nl1lOll_sel + ); + wire_nl1lOlO_data <= ( nl01lOl & nl01l0i & nl01l1i & nl01lll); + wire_nl1lOlO_sel <= ( nlli0li & nlli0il); + nl1lOlO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOlO_data, + o => wire_nl1lOlO_o, + sel => wire_nl1lOlO_sel + ); + wire_nl1lOOi_data <= ( nl01lOi & nl01l1O & nl01l1l & nl01llO); + wire_nl1lOOi_sel <= ( nlli0li & nlli0il); + nl1lOOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOOi_data, + o => wire_nl1lOOi_o, + sel => wire_nl1lOOi_sel + ); + wire_nl1lOOl_data <= ( nl01llO & nl01l1l & nl01l1O & nl01lOi); + wire_nl1lOOl_sel <= ( nlli0li & nlli0il); + nl1lOOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOOl_data, + o => wire_nl1lOOl_o, + sel => wire_nl1lOOl_sel + ); + wire_nl1lOOO_data <= ( nl01lll & nl01l1i & nl01l0i & nl01lOl); + wire_nl1lOOO_sel <= ( nlli0li & nlli0il); + nl1lOOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1lOOO_data, + o => wire_nl1lOOO_o, + sel => wire_nl1lOOO_sel + ); + wire_nl1O00i_data <= ( nl01l0O & nl01iOi & nl01l0l & nl01lOi); + wire_nl1O00i_sel <= ( nlli0li & nlli0il); + nl1O00i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O00i_data, + o => wire_nl1O00i_o, + sel => wire_nl1O00i_sel + ); + wire_nl1O01i_data <= ( nl01liO & nl01l1i & nl01l1l & nl01lli); + wire_nl1O01i_sel <= ( nlli0li & nlli0il); + nl1O01i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O01i_data, + o => wire_nl1O01i_o, + sel => wire_nl1O01i_sel + ); + wire_nl1O01l_data <= ( nl01lil & nl01iOO & nl01l1O & nl01lll); + wire_nl1O01l_sel <= ( nlli0li & nlli0il); + nl1O01l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O01l_data, + o => wire_nl1O01l_o, + sel => wire_nl1O01l_sel + ); + wire_nl1O01O_data <= ( nl01lii & nl01iOl & nl01l0i & nl01llO); + wire_nl1O01O_sel <= ( nlli0li & nlli0il); + nl1O01O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O01O_data, + o => wire_nl1O01O_o, + sel => wire_nl1O01O_sel + ); + wire_nl1O10i_data <= ( nl01l0l & nl01lOi & nl01l0O & nl01iOi); + wire_nl1O10i_sel <= ( nlli0li & nlli0il); + nl1O10i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O10i_data, + o => wire_nl1O10i_o, + sel => wire_nl1O10i_sel + ); + wire_nl1O10l_data <= ( nl01l0i & nl01llO & nl01lii & nl01iOl); + wire_nl1O10l_sel <= ( nlli0li & nlli0il); + nl1O10l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O10l_data, + o => wire_nl1O10l_o, + sel => wire_nl1O10l_sel + ); + wire_nl1O10O_data <= ( nl01l1O & nl01lll & nl01lil & nl01iOO); + wire_nl1O10O_sel <= ( nlli0li & nlli0il); + nl1O10O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O10O_data, + o => wire_nl1O10O_o, + sel => wire_nl1O10O_sel + ); + wire_nl1O11i_data <= ( nl01lli & nl01iOO & nl01l0l & nl01lOO); + wire_nl1O11i_sel <= ( nlli0li & nlli0il); + nl1O11i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O11i_data, + o => wire_nl1O11i_o, + sel => wire_nl1O11i_sel + ); + wire_nl1O11l_data <= ( nl01liO & nl01iOl & nl01l0O & nl01O1i); + wire_nl1O11l_sel <= ( nlli0li & nlli0il); + nl1O11l : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O11l_data, + o => wire_nl1O11l_o, + sel => wire_nl1O11l_sel + ); + wire_nl1O11O_data <= ( nl01lil & nl01iOi & nl01lii & nl01O1l); + wire_nl1O11O_sel <= ( nlli0li & nlli0il); + nl1O11O : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O11O_data, + o => wire_nl1O11O_o, + sel => wire_nl1O11O_sel + ); + wire_nl1O1ii_data <= ( nl01l1l & nl01lli & nl01liO & nl01l1i); + wire_nl1O1ii_sel <= ( nlli0li & nlli0il); + nl1O1ii : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1ii_data, + o => wire_nl1O1ii_o, + sel => wire_nl1O1ii_sel + ); + wire_nl1O1il_data <= ( nl01l1i & nl01liO & nl01lli & nl01l1l); + wire_nl1O1il_sel <= ( nlli0li & nlli0il); + nl1O1il : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1il_data, + o => wire_nl1O1il_o, + sel => wire_nl1O1il_sel + ); + wire_nl1O1iO_data <= ( nl01iOO & nl01lil & nl01lll & nl01l1O); + wire_nl1O1iO_sel <= ( nlli0li & nlli0il); + nl1O1iO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1iO_data, + o => wire_nl1O1iO_o, + sel => wire_nl1O1iO_sel + ); + wire_nl1O1li_data <= ( nl01iOl & nl01lii & nl01llO & nl01l0i); + wire_nl1O1li_sel <= ( nlli0li & nlli0il); + nl1O1li : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1li_data, + o => wire_nl1O1li_o, + sel => wire_nl1O1li_sel + ); + wire_nl1O1ll_data <= ( nl01iOi & nl01l0O & nl01lOi & nl01l0l); + wire_nl1O1ll_sel <= ( nlli0li & nlli0il); + nl1O1ll : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1ll_data, + o => wire_nl1O1ll_o, + sel => wire_nl1O1ll_sel + ); + wire_nl1O1lO_data <= ( nl01lOi & nl01l0l & nl01iOi & nl01l0O); + wire_nl1O1lO_sel <= ( nlli0li & nlli0il); + nl1O1lO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1lO_data, + o => wire_nl1O1lO_o, + sel => wire_nl1O1lO_sel + ); + wire_nl1O1Oi_data <= ( nl01llO & nl01l0i & nl01iOl & nl01lii); + wire_nl1O1Oi_sel <= ( nlli0li & nlli0il); + nl1O1Oi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1Oi_data, + o => wire_nl1O1Oi_o, + sel => wire_nl1O1Oi_sel + ); + wire_nl1O1Ol_data <= ( nl01lll & nl01l1O & nl01iOO & nl01lil); + wire_nl1O1Ol_sel <= ( nlli0li & nlli0il); + nl1O1Ol : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1Ol_data, + o => wire_nl1O1Ol_o, + sel => wire_nl1O1Ol_sel + ); + wire_nl1O1OO_data <= ( nl01lli & nl01l1l & nl01l1i & nl01liO); + wire_nl1O1OO_sel <= ( nlli0li & nlli0il); + nl1O1OO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1OO_data, + o => wire_nl1O1OO_o, + sel => wire_nl1O1OO_sel + ); + wire_nllO0iO_data <= ( "0" & "0" & "0" & wire_w_lg_n10lili3500w & "0" & "0" & "0" & "0" & wire_nlO110O_dataout & wire_nlO1i1i_dataout & wire_nllOO0O_dataout & wire_nllOi0l_dataout & "0" & wire_nlO1l1l_dataout & "0" & "0"); + wire_nllO0iO_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllO0iO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllO0iO_data, + o => wire_nllO0iO_o, + sel => wire_nllO0iO_sel + ); + wire_nllO0li_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & n10l0Ol & wire_nlO1i1l_dataout & wire_nllOOii_dataout & wire_nllOi0O_dataout & "0" & "0" & "0" & "0"); + wire_nllO0li_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllO0li : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllO0li_data, + o => wire_nllO0li_o, + sel => wire_nllO0li_sel + ); + wire_nllO0ll_data <= ( "0" & "0" & "0" & wire_nllOi1l_dataout & "0" & "0" & "0" & "0" & wire_nlO11ii_dataout & n10li0l & wire_nllOOil_dataout & wire_nllOiii_dataout & "0" & wire_nlO1l1O_dataout & "0" & "0"); + wire_nllO0ll_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllO0ll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllO0ll_data, + o => wire_nllO0ll_o, + sel => wire_nllO0ll_sel + ); + wire_nllO0lO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlO11il_dataout & wire_nlO1i1O_dataout & n10li1i & wire_nllOiil_dataout & "0" & "0" & "0" & "0"); + wire_nllO0lO_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllO0lO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllO0lO_data, + o => wire_nllO0lO_o, + sel => wire_nllO0lO_sel + ); + wire_nllO0Oi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlO1l0l_dataout & "0" & wire_nlO1O1l_dataout & "0"); + wire_nllO0Oi_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllO0Oi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllO0Oi_data, + o => wire_nllO0Oi_o, + sel => wire_nllO0Oi_sel + ); + wire_nllO0Ol_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlO11iO_dataout & wire_nlO1i0i_dataout & wire_nllOOiO_dataout & wire_nllOiiO_dataout & wire_nlO1l0O_dataout & n10liil & wire_nlO1O1O_dataout & wire_nlO1Oll_dataout); + wire_nllO0Ol_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllO0Ol : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllO0Ol_data, + o => wire_nllO0Ol_o, + sel => wire_nllO0Ol_sel + ); + wire_nllO0OO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlO1lii_dataout & "0" & wire_nlO1O0i_dataout & wire_nlO1OlO_dataout); + wire_nllO0OO_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllO0OO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllO0OO_data, + o => wire_nllO0OO_o, + sel => wire_nllO0OO_sel + ); + wire_nllOi1i_data <= ( "1" & "1" & "1" & wire_nllOi1O_dataout & "1" & "1" & "1" & "1" & wire_nlO11li_dataout & wire_nlO1i0l_dataout & "0" & wire_nllOili_dataout & n10ll0i & wire_nlO1l0i_dataout & n10ll1i & wire_nl_w_lg_niii0l3438w); + wire_nllOi1i_sel <= ( nlO011O & nlO011l & nlO011i & nllll1i); + nllOi1i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllOi1i_data, + o => wire_nllOi1i_o, + sel => wire_nllOi1i_sel + ); + wire_nlO0O0i_data <= ( wire_nlO0O0l_dataout & "0" & n1ii11l & "0"); + wire_nlO0O0i_sel <= ( nlOiill & nlOiili); + nlO0O0i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO0O0i_data, + o => wire_nlO0O0i_o, + sel => wire_nlO0O0i_sel + ); + wire_nlO0OiO_data <= ( wire_nlO0Oli_dataout & "0" & n1i0Oii & "0"); + wire_nlO0OiO_sel <= ( nlOiiiO & nlOiiil); + nlO0OiO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO0OiO_data, + o => wire_nlO0OiO_o, + sel => wire_nlO0OiO_sel + ); + wire_nlO0OOl_data <= ( wire_nlO0OOO_dataout & "0" & n1i0O1i & "0"); + wire_nlO0OOl_sel <= ( nlOiiii & nlOii0O); + nlO0OOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlO0OOl_data, + o => wire_nlO0OOl_o, + sel => wire_nlO0OOl_sel + ); + wire_nlOi00i_data <= ( wire_nlOi00l_dataout & "0" & n1i0l0O & "0"); + wire_nlOi00i_sel <= ( nlOi0Ol & nlOi0Oi); + nlOi00i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlOi00i_data, + o => wire_nlOi00i_o, + sel => wire_nlOi00i_sel + ); + wire_nlOi0iO_data <= ( wire_nlOi0li_dataout & "0" & n1i0l0i & "0"); + wire_nlOi0iO_sel <= ( nlOi0lO & nlOi0ll); + nlOi0iO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlOi0iO_data, + o => wire_nlOi0iO_o, + sel => wire_nlOi0iO_sel + ); + wire_nlOi10i_data <= ( wire_nlOi10l_dataout & "0" & n1i0llO & "0"); + wire_nlOi10i_sel <= ( nlOii0l & nlOii0i); + nlOi10i : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlOi10i_data, + o => wire_nlOi10i_o, + sel => wire_nlOi10i_sel + ); + wire_nlOi1iO_data <= ( wire_nlOi1li_dataout & "0" & n1i0lli & "0"); + wire_nlOi1iO_sel <= ( nlOii1O & nlOii1l); + nlOi1iO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlOi1iO_data, + o => wire_nlOi1iO_o, + sel => wire_nlOi1iO_sel + ); + wire_nlOi1Ol_data <= ( wire_nlOi1OO_dataout & "0" & n1i0lil & "0"); + wire_nlOi1Ol_sel <= ( nlOii1i & nlOi0OO); + nlOi1Ol : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlOi1Ol_data, + o => wire_nlOi1Ol_o, + sel => wire_nlOi1Ol_sel + ); + wire_n1lili_data <= ( "0" & n01i0i & n1liii & n0110l); + wire_n1lili_sel <= ( n10O00i & n10O01i & n10O1Ol & n10O1OO); + n1lili : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lili_data, + o => wire_n1lili_o, + sel => wire_n1lili_sel + ); + wire_n1lill_data <= ( "0" & n01i0l & n1l00O & n0110O); + wire_n1lill_sel <= ( n10O00i & n10O01i & n10O1Ol & n10O1OO); + n1lill : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lill_data, + o => wire_n1lill_o, + sel => wire_n1lill_sel + ); + wire_n1lilO_data <= ( "0" & n01i0O & n1l0ii & n011ii); + wire_n1lilO_sel <= ( n10O00i & n10O01i & n10O1Ol & n10O1OO); + n1lilO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lilO_data, + o => wire_n1lilO_o, + sel => wire_n1lilO_sel + ); + wire_n1liOi_data <= ( "0" & n01iii & n1l0il & n011il); + wire_n1liOi_sel <= ( n10O00i & n10O01i & n10O1Ol & n10O1OO); + n1liOi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1liOi_data, + o => wire_n1liOi_o, + sel => wire_n1liOi_sel + ); + wire_n1liOO_data <= ( "0" & n010OO & wire_n1lOlO_dataout & n0111i & wire_n1lO1i_dataout); + wire_n1liOO_sel <= ( n10O00i & n10O01i & n1O1Oi & n10O1OO & n1l0Oi); + n1liOO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1liOO_data, + o => wire_n1liOO_o, + sel => wire_n1liOO_sel + ); + wire_n1ll0O_data <= ( "0" & wire_n1lO0l_dataout); + wire_n1ll0O_sel <= ( n10O01l & wire_w_lg_n10O01l2767w); + n1ll0O : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n1ll0O_data, + o => wire_n1ll0O_o, + sel => wire_n1ll0O_sel + ); + wire_n1ll1i_data <= ( "0" & n01i1i & wire_n1lOOi_dataout & n0111l & wire_n1lO1l_dataout); + wire_n1ll1i_sel <= ( n10O00i & n10O01i & n1O1Oi & n10O1OO & n1l0Oi); + n1ll1i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1ll1i_data, + o => wire_n1ll1i_o, + sel => wire_n1ll1i_sel + ); + wire_n1ll1l_data <= ( "0" & n01i1l & wire_n1lOOl_dataout & n0111O & wire_n1lO1O_dataout); + wire_n1ll1l_sel <= ( n10O00i & n10O01i & n1O1Oi & n10O1OO & n1l0Oi); + n1ll1l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1ll1l_data, + o => wire_n1ll1l_o, + sel => wire_n1ll1l_sel + ); + wire_n1ll1O_data <= ( "0" & n01i1O & wire_n1lOOO_dataout & n0110i & wire_n1lO0i_dataout); + wire_n1ll1O_sel <= ( n10O00i & n10O01i & n1O1Oi & n10O1OO & n1l0Oi); + n1ll1O : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1ll1O_data, + o => wire_n1ll1O_o, + sel => wire_n1ll1O_sel + ); + wire_n1llil_data <= ( "0" & wire_n1O11l_dataout & wire_n1O11l_dataout & wire_n1O11l_dataout & wire_n1lO0O_dataout & wire_n1lO0O_dataout & wire_n1lO0O_dataout); + wire_n1llil_sel <= ( n10O00i & n1O1OO & n1O1Ol & n1O1Oi & n1O1lO & n1O1ll & n1l0Oi); + n1llil : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_n1llil_data, + o => wire_n1llil_o, + sel => wire_n1llil_sel + ); + wire_n1llli_data <= ( "0" & wire_n1O11O_dataout); + wire_n1llli_sel <= ( n10O01O & wire_w_lg_n10O01O2739w); + n1llli : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n1llli_data, + o => wire_n1llli_o, + sel => wire_n1llli_sel + ); + wire_n1lllO_data <= ( "0" & wire_n1O10i_dataout & wire_n1O10i_dataout & wire_n1O10i_dataout & wire_n1lOii_dataout & wire_n1lOii_dataout & wire_n1lOii_dataout); + wire_n1lllO_sel <= ( n10O00i & n1O1OO & n1O1Ol & n1O1Oi & n1O1lO & n1O1ll & n1l0Oi); + n1lllO : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_n1lllO_data, + o => wire_n1lllO_o, + sel => wire_n1lllO_sel + ); + wire_n1Oliii_data <= ( "0" & n0101Ol & n1Oli0i & n011liO); + wire_n1Oliii_sel <= ( nlOOi1ii & nlOOi10i & nlOOi11l & nlOOi11O); + n1Oliii : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oliii_data, + o => wire_n1Oliii_o, + sel => wire_n1Oliii_sel + ); + wire_n1Oliil_data <= ( "0" & n0101OO & n1Ol1Ol & n011lli); + wire_n1Oliil_sel <= ( nlOOi1ii & nlOOi10i & nlOOi11l & nlOOi11O); + n1Oliil : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Oliil_data, + o => wire_n1Oliil_o, + sel => wire_n1Oliil_sel + ); + wire_n1OliiO_data <= ( "0" & n01001i & n1Ol1OO & n011lll); + wire_n1OliiO_sel <= ( nlOOi1ii & nlOOi10i & nlOOi11l & nlOOi11O); + n1OliiO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1OliiO_data, + o => wire_n1OliiO_o, + sel => wire_n1OliiO_sel + ); + wire_n1Olili_data <= ( "0" & n01001l & n1Ol01i & n011llO); + wire_n1Olili_sel <= ( nlOOi1ii & nlOOi10i & nlOOi11l & nlOOi11O); + n1Olili : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Olili_data, + o => wire_n1Olili_o, + sel => wire_n1Olili_sel + ); + wire_n1Olill_data <= ( "0" & n01001O & n1Ol01l & n011lOi); + wire_n1Olill_sel <= ( nlOOi1ii & nlOOi10i & nlOOi11l & nlOOi11O); + n1Olill : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1Olill_data, + o => wire_n1Olill_o, + sel => wire_n1Olill_sel + ); + wire_n1OliOi_data <= ( "0" & n0101iO & wire_n1OlOlO_dataout & n011l0i & wire_n1OllOO_dataout); + wire_n1OliOi_sel <= ( nlOOi1ii & nlOOi10i & n1OO1Ol & nlOOi11O & n1Ol0il); + n1OliOi : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1OliOi_data, + o => wire_n1OliOi_o, + sel => wire_n1OliOi_sel + ); + wire_n1OliOl_data <= ( "0" & n0101li & wire_n1OlOOi_dataout & n011l0l & wire_n1OlO1i_dataout); + wire_n1OliOl_sel <= ( nlOOi1ii & nlOOi10i & n1OO1Ol & nlOOi11O & n1Ol0il); + n1OliOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1OliOl_data, + o => wire_n1OliOl_o, + sel => wire_n1OliOl_sel + ); + wire_n1OliOO_data <= ( "0" & n0101ll & wire_n1OlOOl_dataout & n011l0O & wire_n1OlO1l_dataout); + wire_n1OliOO_sel <= ( nlOOi1ii & nlOOi10i & n1OO1Ol & nlOOi11O & n1Ol0il); + n1OliOO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1OliOO_data, + o => wire_n1OliOO_o, + sel => wire_n1OliOO_sel + ); + wire_n1Oll0l_data <= ( "0" & wire_n1OlO0l_dataout); + wire_n1Oll0l_sel <= ( nlOOi10l & wire_w_lg_nlOOi10l16209w); + n1Oll0l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n1Oll0l_data, + o => wire_n1Oll0l_o, + sel => wire_n1Oll0l_sel + ); + wire_n1Oll1i_data <= ( "0" & n0101lO & wire_n1OlOOO_dataout & n011lii & wire_n1OlO1O_dataout); + wire_n1Oll1i_sel <= ( nlOOi1ii & nlOOi10i & n1OO1Ol & nlOOi11O & n1Ol0il); + n1Oll1i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1Oll1i_data, + o => wire_n1Oll1i_o, + sel => wire_n1Oll1i_sel + ); + wire_n1Oll1l_data <= ( "0" & n0101Oi & wire_n1OO11i_dataout & n011lil & wire_n1OlO0i_dataout); + wire_n1Oll1l_sel <= ( nlOOi1ii & nlOOi10i & n1OO1Ol & nlOOi11O & n1Ol0il); + n1Oll1l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1Oll1l_data, + o => wire_n1Oll1l_o, + sel => wire_n1Oll1l_sel + ); + wire_n1Ollii_data <= ( "0" & wire_n1OO11O_dataout & wire_n1OO11O_dataout & wire_n1OO11O_dataout & wire_n1OlO0O_dataout & wire_n1OlO0O_dataout & wire_n1OlO0O_dataout); + wire_n1Ollii_sel <= ( nlOOi1ii & n1OO01i & n1OO1OO & n1OO1Ol & n1OO1Oi & n1OO1lO & n1Ol0il); + n1Ollii : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_n1Ollii_data, + o => wire_n1Ollii_o, + sel => wire_n1Ollii_sel + ); + wire_n1OlliO_data <= ( "0" & wire_n1OO10i_dataout); + wire_n1OlliO_sel <= ( nlOOi10O & wire_w_lg_nlOOi10O16181w); + n1OlliO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n1OlliO_data, + o => wire_n1OlliO_o, + sel => wire_n1OlliO_sel + ); + wire_n1Ollll_data <= ( "0" & wire_n1OO10l_dataout & wire_n1OO10l_dataout & wire_n1OO10l_dataout & wire_n1OlOii_dataout & wire_n1OlOii_dataout & wire_n1OlOii_dataout); + wire_n1Ollll_sel <= ( nlOOi1ii & n1OO01i & n1OO1OO & n1OO1Ol & n1OO1Oi & n1OO1lO & n1Ol0il); + n1Ollll : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_n1Ollll_data, + o => wire_n1Ollll_o, + sel => wire_n1Ollll_sel + ); + wire_niO00i_data <= ( wire_niilOi_dataout & wire_niil0l_dataout & wire_niOl1i_o); + wire_niO00i_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO00i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO00i_data, + o => wire_niO00i_o, + sel => wire_niO00i_sel + ); + wire_niO00l_data <= ( wire_niilOl_dataout & wire_niil0O_dataout & wire_niOl1l_o); + wire_niO00l_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO00l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO00l_data, + o => wire_niO00l_o, + sel => wire_niO00l_sel + ); + wire_niO00O_data <= ( wire_niilOO_dataout & wire_niilii_dataout & wire_niOl1O_o); + wire_niO00O_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO00O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO00O_data, + o => wire_niO00O_o, + sel => wire_niO00O_sel + ); + wire_niO01i_data <= ( wire_niilli_dataout & wire_niil1l_dataout & wire_niOiOi_o); + wire_niO01i_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO01i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO01i_data, + o => wire_niO01i_o, + sel => wire_niO01i_sel + ); + wire_niO01l_data <= ( wire_niilll_dataout & wire_niil1O_dataout & wire_niOiOl_o); + wire_niO01l_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO01l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO01l_data, + o => wire_niO01l_o, + sel => wire_niO01l_sel + ); + wire_niO01O_data <= ( wire_niillO_dataout & wire_niil0i_dataout & wire_niOiOO_o); + wire_niO01O_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO01O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO01O_data, + o => wire_niO01O_o, + sel => wire_niO01O_sel + ); + wire_niO1Ol_data <= ( wire_niilil_dataout & wire_niiiOO_dataout & wire_niOill_o); + wire_niO1Ol_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO1Ol : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO1Ol_data, + o => wire_niO1Ol_o, + sel => wire_niO1Ol_sel + ); + wire_niO1OO_data <= ( wire_niiliO_dataout & wire_niil1i_dataout & wire_niOilO_o); + wire_niO1OO_sel <= ( n1i01li & n1i01iO & wire_w_lg_n1i01il1227w); + niO1OO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niO1OO_data, + o => wire_niO1OO_o, + sel => wire_niO1OO_sel + ); + wire_niOill_w_lg_o3118w(0) <= NOT wire_niOill_o; + wire_niOill_data <= ( nl110O & nl11il & niOO0i); + wire_niOill_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOill : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOill_data, + o => wire_niOill_o, + sel => wire_niOill_sel + ); + wire_niOilO_w_lg_w_lg_o3116w3135w(0) <= wire_niOilO_w_lg_o3116w(0) AND wire_niOill_w_lg_o3118w(0); + wire_niOilO_w_lg_w_lg_o3116w3117w(0) <= wire_niOilO_w_lg_o3116w(0) AND wire_niOill_o; + wire_niOilO_w_lg_o3119w(0) <= wire_niOilO_o AND wire_niOill_w_lg_o3118w(0); + wire_niOilO_w_lg_o3116w(0) <= NOT wire_niOilO_o; + wire_niOilO_data <= ( nl110l & nl11ii & niOOOO); + wire_niOilO_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOilO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOilO_data, + o => wire_niOilO_o, + sel => wire_niOilO_sel + ); + wire_niOiOi_w_lg_w_lg_o3108w3287w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10llil; + wire_niOiOi_w_lg_w_lg_o3108w3282w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10lliO; + wire_niOiOi_w_lg_w_lg_o3108w3275w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10llli; + wire_niOiOi_w_lg_w_lg_o3108w3272w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10llll; + wire_niOiOi_w_lg_w_lg_o3108w3152w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10lOii; + wire_niOiOi_w_lg_w_lg_o3108w3147w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10lOil; + wire_niOiOi_w_lg_w_lg_o3108w3132w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10lOiO; + wire_niOiOi_w_lg_w_lg_o3108w3129w(0) <= wire_niOiOi_w_lg_o3108w(0) AND n10lOli; + wire_niOiOi_w_lg_o3136w(0) <= wire_niOiOi_o AND wire_niOilO_w_lg_w_lg_o3116w3135w(0); + wire_niOiOi_w_lg_o3155w(0) <= wire_niOiOi_o AND wire_niOilO_w_lg_w_lg_o3116w3117w(0); + wire_niOiOi_w_lg_o3158w(0) <= wire_niOiOi_o AND wire_niOilO_w_lg_o3119w(0); + wire_niOiOi_w_lg_o3108w(0) <= NOT wire_niOiOi_o; + wire_niOiOi_data <= ( nl110i & nl110O & nl111i); + wire_niOiOi_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOiOi : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOiOi_data, + o => wire_niOiOi_o, + sel => wire_niOiOi_sel + ); + wire_niOiOl_w_lg_w_lg_o1205w3260w(0) <= wire_niOiOl_w_lg_o1205w(0) AND n10lllO; + wire_niOiOl_w_lg_w_lg_o1205w1206w(0) <= wire_niOiOl_w_lg_o1205w(0) AND n1i001i; + wire_niOiOl_w_lg_o3288w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3287w(0); + wire_niOiOl_w_lg_o3283w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3282w(0); + wire_niOiOl_w_lg_o3276w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3275w(0); + wire_niOiOl_w_lg_o3273w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3272w(0); + wire_niOiOl_w_lg_o3153w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3152w(0); + wire_niOiOl_w_lg_o3148w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3147w(0); + wire_niOiOl_w_lg_o3133w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3132w(0); + wire_niOiOl_w_lg_o3130w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_w_lg_o3108w3129w(0); + wire_niOiOl_w_lg_o3137w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_o3136w(0); + wire_niOiOl_w_lg_o3156w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_o3155w(0); + wire_niOiOl_w_lg_o3159w(0) <= wire_niOiOl_o AND wire_niOiOi_w_lg_o3158w(0); + wire_niOiOl_w_lg_o3105w(0) <= wire_niOiOl_o AND wire_niOiOi_o; + wire_niOiOl_w_lg_o1205w(0) <= NOT wire_niOiOl_o; + wire_niOiOl_data <= ( nl111O & nl110l & nl111l); + wire_niOiOl_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOiOl : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOiOl_data, + o => wire_niOiOl_o, + sel => wire_niOiOl_sel + ); + wire_niOiOO_w_lg_w_lg_o2973w3041w(0) <= wire_niOiOO_w_lg_o2973w(0) AND wire_niOiOl_w_lg_o1205w(0); + wire_niOiOO_w_lg_w_lg_o2973w3035w(0) <= wire_niOiOO_w_lg_o2973w(0) AND n10O11O; + wire_niOiOO_w_lg_w_lg_o2973w2974w(0) <= wire_niOiOO_w_lg_o2973w(0) AND n10O1li; + wire_niOiOO_w_lg_o3106w(0) <= wire_niOiOO_o AND wire_niOiOl_w_lg_o3105w(0); + wire_niOiOO_w_lg_o3052w(0) <= wire_niOiOO_o AND n10O11O; + wire_niOiOO_w_lg_o2977w(0) <= wire_niOiOO_o AND n10O1iO; + wire_niOiOO_w_lg_o3058w(0) <= wire_niOiOO_o AND wire_niOiOl_o; + wire_niOiOO_w_lg_o2973w(0) <= NOT wire_niOiOO_o; + wire_niOiOO_data <= ( nl111l & nl110i & nl111O); + wire_niOiOO_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOiOO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOiOO_data, + o => wire_niOiOO_o, + sel => wire_niOiOO_sel + ); + wire_niOl1i_w_lg_w_lg_o2972w3042w(0) <= wire_niOl1i_w_lg_o2972w(0) AND wire_niOiOO_w_lg_w_lg_o2973w3041w(0); + wire_niOl1i_w_lg_w_lg_o2972w3036w(0) <= wire_niOl1i_w_lg_o2972w(0) AND wire_niOiOO_w_lg_w_lg_o2973w3035w(0); + wire_niOl1i_w_lg_w_lg_o2972w3113w(0) <= wire_niOl1i_w_lg_o2972w(0) AND wire_niOiOO_o; + wire_niOl1i_w_lg_w_lg_w_lg_o2972w3038w3039w(0) <= wire_niOl1i_w_lg_w_lg_o2972w3038w(0) AND n10O1li; + wire_niOl1i_w_lg_w3043w3049w(0) <= wire_niOl1i_w3043w(0) AND wire_w_lg_w_lg_n10O10i3045w3048w(0); + wire_niOl1i_w3068w(0) <= wire_niOl1i_w_lg_w_lg_w_lg_w_lg_o3053w3054w3057w3060w(0) AND wire_w_lg_w_lg_n10O10l3063w3067w(0); + wire_niOl1i_w_lg_w_lg_o3055w3056w(0) <= wire_niOl1i_w_lg_o3055w(0) AND n10O1iO; + wire_niOl1i_w_lg_o3107w(0) <= wire_niOl1i_o AND wire_niOiOO_w_lg_o3106w(0); + wire_niOl1i_w_lg_o3053w(0) <= wire_niOl1i_o AND wire_niOiOO_w_lg_o3052w(0); + wire_niOl1i_w_lg_o2978w(0) <= wire_niOl1i_o AND wire_niOiOO_w_lg_o2977w(0); + wire_niOl1i_w_lg_o3059w(0) <= wire_niOl1i_o AND wire_niOiOO_w_lg_o3058w(0); + wire_niOl1i_w_lg_o3114w(0) <= wire_niOl1i_o AND wire_niOiOO_w_lg_o2973w(0); + wire_niOl1i_w_lg_o2994w(0) <= wire_niOl1i_o AND wire_niOiOO_o; + wire_niOl1i_w_lg_o2972w(0) <= NOT wire_niOl1i_o; + wire_niOl1i_w_lg_w_lg_w_lg_o2972w3036w3037w(0) <= wire_niOl1i_w_lg_w_lg_o2972w3036w(0) OR n10O1ll; + wire_niOl1i_w_lg_w_lg_o3053w3054w(0) <= wire_niOl1i_w_lg_o3053w(0) OR n10O1lO; + wire_niOl1i_w_lg_w_lg_o2972w3038w(0) <= wire_niOl1i_w_lg_o2972w(0) OR wire_niOiOO_w_lg_o2973w(0); + wire_niOl1i_w_lg_w_lg_w_lg_w_lg_o2972w3036w3037w3040w(0) <= wire_niOl1i_w_lg_w_lg_w_lg_o2972w3036w3037w(0) OR wire_niOl1i_w_lg_w_lg_w_lg_o2972w3038w3039w(0); + wire_niOl1i_w_lg_w_lg_w_lg_o3053w3054w3057w(0) <= wire_niOl1i_w_lg_w_lg_o3053w3054w(0) OR wire_niOl1i_w_lg_w_lg_o3055w3056w(0); + wire_niOl1i_w3043w(0) <= wire_niOl1i_w_lg_w_lg_w_lg_w_lg_o2972w3036w3037w3040w(0) OR wire_niOl1i_w_lg_w_lg_o2972w3042w(0); + wire_niOl1i_w_lg_w_lg_w_lg_w_lg_o3053w3054w3057w3060w(0) <= wire_niOl1i_w_lg_w_lg_w_lg_o3053w3054w3057w(0) OR wire_niOl1i_w_lg_o3059w(0); + wire_niOl1i_w_lg_o3055w(0) <= wire_niOl1i_o OR wire_niOiOO_o; + wire_niOl1i_data <= ( nl111i & nl111O & nl110i); + wire_niOl1i_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOl1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOl1i_data, + o => wire_niOl1i_o, + sel => wire_niOl1i_sel + ); + wire_niOl1l_w_lg_w_lg_o2983w3085w(0) <= wire_niOl1l_w_lg_o2983w(0) AND n10lOll; + wire_niOl1l_w_lg_w_lg_o2983w3166w(0) <= wire_niOl1l_w_lg_o2983w(0) AND n1i01ll; + wire_niOl1l_w_lg_o2995w(0) <= wire_niOl1l_o AND wire_niOl1i_w_lg_o2994w(0); + wire_niOl1l_w_lg_o1215w(0) <= wire_niOl1l_o AND n1i01ll; + wire_niOl1l_w_lg_o2983w(0) <= NOT wire_niOl1l_o; + wire_niOl1l_data <= ( niOOOO & nl111l & nl110l); + wire_niOl1l_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOl1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOl1l_data, + o => wire_niOl1l_o, + sel => wire_niOl1l_sel + ); + wire_niOl1O_w_lg_w_lg_w_lg_o1314w3170w3171w(0) <= wire_niOl1O_w_lg_w_lg_o1314w3170w(0) AND n10lO0O; + wire_niOl1O_w_lg_w_lg_o3172w3173w(0) <= wire_niOl1O_w_lg_o3172w(0) AND n10lO0O; + wire_niOl1O_w_lg_w_lg_o1314w3181w(0) <= wire_niOl1O_w_lg_o1314w(0) AND wire_w_lg_n1i1Oll3180w(0); + wire_niOl1O_w_lg_w_lg_o1314w2984w(0) <= wire_niOl1O_w_lg_o1314w(0) AND wire_niOl1l_w_lg_o2983w(0); + wire_niOl1O_w_lg_w_lg_o1314w3022w(0) <= wire_niOl1O_w_lg_o1314w(0) AND n10O1ii; + wire_niOl1O_w_lg_w_lg_o1314w2999w(0) <= wire_niOl1O_w_lg_o1314w(0) AND n10O1il; + wire_niOl1O_w_lg_w_lg_o1314w1315w(0) <= wire_niOl1O_w_lg_o1314w(0) AND n1i1Oli; + wire_niOl1O_w_lg_w_lg_o1314w3170w(0) <= wire_niOl1O_w_lg_o1314w(0) AND n1i1OlO; + wire_niOl1O_w_lg_w_lg_o1314w3007w(0) <= wire_niOl1O_w_lg_o1314w(0) AND wire_niOl1i_o; + wire_niOl1O_w_lg_w_lg_o1314w3189w(0) <= wire_niOl1O_w_lg_o1314w(0) AND wire_niOl1l_o; + wire_niOl1O_w_lg_o3178w(0) <= wire_niOl1O_o AND wire_w_lg_n1i1OlO3177w(0); + wire_niOl1O_w_lg_o2996w(0) <= wire_niOl1O_o AND wire_niOl1l_w_lg_o2995w(0); + wire_niOl1O_w_lg_o1216w(0) <= wire_niOl1O_o AND wire_niOl1l_w_lg_o1215w(0); + wire_niOl1O_w_lg_o3010w(0) <= wire_niOl1O_o AND wire_niOl1i_w_lg_o2972w(0); + wire_niOl1O_w_lg_o3190w(0) <= wire_niOl1O_o AND wire_niOl1l_w_lg_o2983w(0); + wire_niOl1O_w_lg_o3003w(0) <= wire_niOl1O_o AND n10O1ii; + wire_niOl1O_w_lg_o3028w(0) <= wire_niOl1O_o AND n10O1il; + wire_niOl1O_w_lg_o1319w(0) <= wire_niOl1O_o AND n1i1OiO; + wire_niOl1O_w_lg_o3172w(0) <= wire_niOl1O_o AND n1i1Oll; + wire_niOl1O_w_lg_o2980w(0) <= wire_niOl1O_o AND wire_niOl1l_o; + wire_niOl1O_w_lg_o1314w(0) <= NOT wire_niOl1O_o; + wire_niOl1O_w_lg_w_lg_w_lg_w_lg_o1314w3170w3171w3174w(0) <= wire_niOl1O_w_lg_w_lg_w_lg_o1314w3170w3171w(0) OR wire_niOl1O_w_lg_w_lg_o3172w3173w(0); + wire_niOl1O_w_lg_w_lg_o1314w3046w(0) <= wire_niOl1O_w_lg_o1314w(0) OR wire_niOl1l_w_lg_o2983w(0); + wire_niOl1O_w_lg_o3065w(0) <= wire_niOl1O_o OR wire_niOl1l_o; + wire_niOl1O_data <= ( niOO0i & nl111i & nl110O); + wire_niOl1O_sel <= ( n1i00Ol & n1i00Oi & wire_w_lg_n1i00lO1129w); + niOl1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_niOl1O_data, + o => wire_niOl1O_o, + sel => wire_niOl1O_sel + ); + wire_nll1llO_w_lg_o7418w(0) <= NOT wire_nll1llO_o; + wire_nll1llO_data <= ( n10l1il & wire_nll1O1O_dataout & "0"); + wire_nll1llO_sel <= ( n10l11O & n10l11l & wire_w_lg_n10l11i4530w); + nll1llO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll1llO_data, + o => wire_nll1llO_o, + sel => wire_nll1llO_sel + ); + wire_nll1lOO_data <= ( wire_w_lg_n10l1li4548w & wire_nll1O0l_dataout & "1"); + wire_nll1lOO_sel <= ( n10l11O & n10l11l & wire_w_lg_n10l11i4530w); + nll1lOO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll1lOO_data, + o => wire_nll1lOO_o, + sel => wire_nll1lOO_sel + ); + wire_nll1O1i_data <= ( n10l1li & wire_nll1O0i_dataout & "0"); + wire_nll1O1i_sel <= ( n10l11O & n10l11l & wire_w_lg_n10l11i4530w); + nll1O1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll1O1i_data, + o => wire_nll1O1i_o, + sel => wire_nll1O1i_sel + ); + wire_nlll0i_data <= ( wire_nlllli_dataout & wire_nlllii_dataout & wire_nl_w_lg_nlO0l1l246w); + wire_nlll0i_sel <= ( wire_n1ii1li26_w_lg_w_lg_q243w244w & wire_n1ii1ll24_w_lg_w_lg_q240w241w & nlllOl); + nlll0i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll0i_data, + o => wire_nlll0i_o, + sel => wire_nlll0i_sel + ); + wire_nlll1i_data <= ( wire_nlllil_dataout & wire_nlll0l_dataout & "0"); + wire_nlll1i_sel <= ( nllO1l & wire_n1ii1ii32_w_lg_w_lg_q274w275w & wire_n1ii1il30_w_lg_w_lg_q270w271w); + nlll1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll1i_data, + o => wire_nlll1i_o, + sel => wire_nlll1i_sel + ); + wire_nlll1l_data <= ( wire_nllliO_dataout & n1ii1lO & nlO0l1l); + wire_nlll1l_sel <= ( nllO1l & nlllOO & nlllOl); + nlll1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll1l_data, + o => wire_nlll1l_o, + sel => wire_nlll1l_sel + ); + wire_nlll1O_data <= ( n1ii00i & wire_n1ii1iO28_w_lg_w_lg_q258w259w & "0"); + wire_nlll1O_sel <= ( nllO1l & nlllOO & nlllOl); + nlll1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll1O_data, + o => wire_nlll1O_o, + sel => wire_nlll1O_sel + ); + wire_nllll0i_data <= ( nlO01Ol & gnumber(2) & "0" & wire_nllO1Oi_o(2)); + wire_nllll0i_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllll0i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllll0i_data, + o => wire_nllll0i_o, + sel => wire_nllll0i_sel + ); + wire_nllll0l_data <= ( nlO01OO & gnumber(3) & "0" & wire_nllO1Oi_o(3)); + wire_nllll0l_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllll0l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllll0l_data, + o => wire_nllll0l_o, + sel => wire_nllll0l_sel + ); + wire_nllll0O_data <= ( nlO001i & gnumber(4) & "0" & wire_nllO1Oi_o(4)); + wire_nllll0O_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllll0O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllll0O_data, + o => wire_nllll0O_o, + sel => wire_nllll0O_sel + ); + wire_nllll1l_data <= ( nlO01lO & gnumber(0) & "0" & wire_nllO1Oi_o(0)); + wire_nllll1l_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllll1l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllll1l_data, + o => wire_nllll1l_o, + sel => wire_nllll1l_sel + ); + wire_nllll1O_data <= ( nlO01Oi & gnumber(1) & "0" & wire_nllO1Oi_o(1)); + wire_nllll1O_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllll1O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllll1O_data, + o => wire_nllll1O_o, + sel => wire_nllll1O_sel + ); + wire_nllllii_data <= ( nlO001l & gnumber(5) & "0" & wire_nllO1Oi_o(5)); + wire_nllllii_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllllii : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllllii_data, + o => wire_nllllii_o, + sel => wire_nllllii_sel + ); + wire_nllllil_data <= ( nlO001O & gnumber(6) & "0" & wire_nllO1Oi_o(6)); + wire_nllllil_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllllil : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllllil_data, + o => wire_nllllil_o, + sel => wire_nllllil_sel + ); + wire_nlllliO_data <= ( nlO000i & gnumber(7) & "0" & wire_nllO1Oi_o(7)); + wire_nlllliO_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nlllliO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllliO_data, + o => wire_nlllliO_o, + sel => wire_nlllliO_sel + ); + wire_nllllli_data <= ( nlO000l & gnumber(8) & "0" & wire_nllO1Oi_o(8)); + wire_nllllli_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllllli : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllllli_data, + o => wire_nllllli_o, + sel => wire_nllllli_sel + ); + wire_nllllll_data <= ( nlO000O & gnumber(9) & "0" & wire_nllO1Oi_o(9)); + wire_nllllll_sel <= ( n10l1Oi & wire_nllO00O_dataout & n10l1lO & wire_nllO01l_dataout); + nllllll : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllllll_data, + o => wire_nllllll_o, + sel => wire_nllllll_sel + ); + wire_nllllOl_data <= ( nlO00ii & "0" & wire_nllO1Ol_o(0) & wire_nllO1lO_o(1)); + wire_nllllOl_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nllllOl : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllllOl_data, + o => wire_nllllOl_o, + sel => wire_nllllOl_sel + ); + wire_nllllOO_data <= ( nlO00il & "0" & wire_nllO1Ol_o(1) & wire_nllO1lO_o(2)); + wire_nllllOO_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nllllOO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nllllOO_data, + o => wire_nllllOO_o, + sel => wire_nllllOO_sel + ); + wire_nlllO0i_data <= ( nlO00lO & "0" & wire_nllO1Ol_o(5) & wire_nllO1lO_o(6)); + wire_nlllO0i_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllO0i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllO0i_data, + o => wire_nlllO0i_o, + sel => wire_nlllO0i_sel + ); + wire_nlllO0l_data <= ( nlO00Oi & "0" & wire_nllO1Ol_o(6) & wire_nllO1lO_o(7)); + wire_nlllO0l_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllO0l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllO0l_data, + o => wire_nlllO0l_o, + sel => wire_nlllO0l_sel + ); + wire_nlllO0O_data <= ( nlO00Ol & "0" & wire_nllO1Ol_o(7) & wire_nllO1lO_o(8)); + wire_nlllO0O_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllO0O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllO0O_data, + o => wire_nlllO0O_o, + sel => wire_nlllO0O_sel + ); + wire_nlllO1i_data <= ( nlO00iO & "0" & wire_nllO1Ol_o(2) & wire_nllO1lO_o(3)); + wire_nlllO1i_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllO1i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllO1i_data, + o => wire_nlllO1i_o, + sel => wire_nlllO1i_sel + ); + wire_nlllO1l_data <= ( nlO00li & "0" & wire_nllO1Ol_o(3) & wire_nllO1lO_o(4)); + wire_nlllO1l_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllO1l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllO1l_data, + o => wire_nlllO1l_o, + sel => wire_nlllO1l_sel + ); + wire_nlllO1O_data <= ( nlO00ll & "0" & wire_nllO1Ol_o(4) & wire_nllO1lO_o(5)); + wire_nlllO1O_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllO1O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllO1O_data, + o => wire_nlllO1O_o, + sel => wire_nlllO1O_sel + ); + wire_nlllOii_data <= ( nlO00OO & "0" & wire_nllO1Ol_o(8) & wire_nllO1lO_o(9)); + wire_nlllOii_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllOii : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllOii_data, + o => wire_nlllOii_o, + sel => wire_nlllOii_sel + ); + wire_nlllOil_data <= ( nlO0i1i & "0" & wire_nllO1Ol_o(9) & wire_nllO1lO_o(10)); + wire_nlllOil_sel <= ( n10l1Ol & wire_nllO00O_dataout & wire_nllO01O_dataout & wire_nllO00i_dataout); + nlllOil : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlllOil_data, + o => wire_nlllOil_o, + sel => wire_nlllOil_sel + ); + wire_nlllOli_data <= ( "1" & "0" & nlO010O); + wire_nlllOli_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_w_lg_dataout4069w & wire_nllO00i_w_lg_w_lg_w_lg_dataout4064w4065w4066w); + nlllOli : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlllOli_data, + o => wire_nlllOli_o, + sel => wire_nlllOli_sel + ); + wire_nlllOOi_data <= ( "0" & wire_nllO1OO_o(0) & nlO0i1l); + wire_nlllOOi_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nlllOOi : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlllOOi_data, + o => wire_nlllOOi_o, + sel => wire_nlllOOi_sel + ); + wire_nlllOOl_data <= ( "0" & wire_nllO1OO_o(1) & nlO0i1O); + wire_nlllOOl_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nlllOOl : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlllOOl_data, + o => wire_nlllOOl_o, + sel => wire_nlllOOl_sel + ); + wire_nlllOOO_data <= ( "0" & wire_nllO1OO_o(2) & nlO0i0i); + wire_nlllOOO_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nlllOOO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlllOOO_data, + o => wire_nlllOOO_o, + sel => wire_nlllOOO_sel + ); + wire_nllO10i_data <= ( "0" & wire_nllO1OO_o(6) & nlO0iil); + wire_nllO10i_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nllO10i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO10i_data, + o => wire_nllO10i_o, + sel => wire_nllO10i_sel + ); + wire_nllO10l_data <= ( "0" & wire_nllO1OO_o(7) & nlO0iiO); + wire_nllO10l_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nllO10l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO10l_data, + o => wire_nllO10l_o, + sel => wire_nllO10l_sel + ); + wire_nllO10O_data <= ( "0" & wire_nllO1OO_o(8) & nlO0ili); + wire_nllO10O_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nllO10O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO10O_data, + o => wire_nllO10O_o, + sel => wire_nllO10O_sel + ); + wire_nllO11i_data <= ( "0" & wire_nllO1OO_o(3) & nlO0i0l); + wire_nllO11i_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nllO11i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO11i_data, + o => wire_nllO11i_o, + sel => wire_nllO11i_sel + ); + wire_nllO11l_data <= ( "0" & wire_nllO1OO_o(4) & nlO0i0O); + wire_nllO11l_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nllO11l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO11l_data, + o => wire_nllO11l_o, + sel => wire_nllO11l_sel + ); + wire_nllO11O_data <= ( "0" & wire_nllO1OO_o(5) & nlO0iii); + wire_nllO11O_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nllO11O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO11O_data, + o => wire_nllO11O_o, + sel => wire_nllO11O_sel + ); + wire_nllO1ii_data <= ( "0" & wire_nllO1OO_o(9) & nlO0ill); + wire_nllO1ii_sel <= ( wire_nllO0il_dataout & wire_nllO0ii_dataout & n10l1OO); + nllO1ii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO1ii_data, + o => wire_nllO1ii_o, + sel => wire_nllO1ii_sel + ); + wire_nllO1iO_data <= ( "0" & nlO01ii & "1"); + wire_nllO1iO_sel <= ( wire_nllO0il_dataout & n10l01i & wire_nllO00O_dataout); + nllO1iO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllO1iO_data, + o => wire_nllO1iO_o, + sel => wire_nllO1iO_sel + ); + + END RTL; --cycloneiv_hssi_rx_digi_wordalign +--synopsys translate_on +--VALID FILE + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_rx_digi IS + PORT ( + -- S. Park 3/21/08 - Removed following ports + -- disable_fifo_rd_0, + -- disable_fifo_wr_0, + -- disable_fifo_rd, + -- disable_fifo_wr, + --new for auto-nego + -- new MDIO inputs for bundling and auto speed + -- new outputs for bundling and auto speed + --new for Eidle inference + -- CDR control + -- S. Park 3/13/08 - Added for XAUI compliance + -- S. Park 3/21/08 - Added for XAUI compliance + + -- Reset inputs + hard_reset : IN STD_LOGIC; -- From MDIO_REG.V Complex function of NPOR, ENTEST etc., + rxpcs_rst : IN STD_LOGIC; -- RX PCS resets + rxpma_rst : IN STD_LOGIC; -- RX PMA reset for PPM Detect + cmpfifourst : IN STD_LOGIC; -- User reset exclusive to comp_chnl_top & below + phfifourst_rx : IN STD_LOGIC; -- User reset exclusive to rx_ctrl & below + + -- Scan inputs + scan_mode : IN STD_LOGIC; -- 1'b1 = scan mode active; + -- 1'b0 = normal mode + -- RX PCS channel inputs/outputs + encdt : IN STD_LOGIC; -- Comma Detect enable control signal from PLD + a1a2_size : IN STD_LOGIC; -- A1A2 size control signal for byte sync block + bitslip : IN STD_LOGIC; -- Bitslip control signal from PLD + rdenable_rmf : IN STD_LOGIC; -- Read enable control signal for CompFIFO + wrenable_rmf : IN STD_LOGIC; -- Write enable control signal for CompFIFO + pld_rx_clk : IN STD_LOGIC; -- Parallel receive clock from PLD + soft_reset_rclk1 : OUT STD_LOGIC; -- Synchronized reset + polinv_rx : IN STD_LOGIC; -- RX polarity inversion dynamic control signal + bitloc_rev_en : IN STD_LOGIC; -- RX bit reversal dynamic control signal + byte_rev_en : IN STD_LOGIC; -- RX byte swap dynamic control signal + rcvd_clk_pma : IN STD_LOGIC; + pudi : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- RX 10-bit code group bus from RX PMA + sigdetni : IN STD_LOGIC; -- rx signal detected from PMA + fifo_rst_rd_qd : IN STD_LOGIC; -- from master deskew sm + fifo_rst_rd_gp : IN STD_LOGIC; -- from grouping deskew sm + en_dskw_qd : IN STD_LOGIC; -- from master deskew sm + en_dskw_gp : IN STD_LOGIC; -- from grouping deskew sm + is_lane0 : IN STD_LOGIC; -- This is lane 0 if 1'b1. Hard-wired + -- when chnl_top is instantiated + align_status : IN STD_LOGIC; -- Indicate that four lanes are now + -- aligned in dskw_top + align_status_sync_0 : IN STD_LOGIC; -- Synced to clk_2 from channel 0 + align_status_sync_2 : IN STD_LOGIC; -- Synced to clk_2 from channel 2 + -- S. Park 3/21/08 - Removed below two ports + -- input disable_fifo_rd_0; // disable_fifo_rd from channel 0 + -- input disable_fifo_wr_0; // disable_fifo_wr from channel 0 + rx_data_rs : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- rx data from 10G ethernet rx state machine + rx_control_rs : IN STD_LOGIC; -- rx control from 10G ethernet rx state machine + rcvd_clk0_pma : IN STD_LOGIC; -- Recovered clock from PMA channel0 + fifo_rd_in_comp_0 : IN STD_LOGIC; -- fifo_rd_in_comp from channel 0 + fifo_rd_in_comp_2 : IN STD_LOGIC; -- fifo_rd_in_comp from channel 2 + txlp20b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- tx 20-bit code group bus to PMA + refclk_pma : IN STD_LOGIC; -- Global parallel TX PLL clock + tx_pma_clk : IN STD_LOGIC; -- Per channel TX PMA clock + fref : IN STD_LOGIC; -- Reference clock for FREQDET module + clklow : IN STD_LOGIC; -- Divided clock for FREQDET module + bytordpld : IN STD_LOGIC; -- Byte ordering dynamic control signal from PLD + wrdisable_rx : IN STD_LOGIC; -- RX phase comp. FIFO write disable control signal + rdenable_rx : IN STD_LOGIC; -- RX phase comp. FIFO read enable control signal + pma_testbus : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- PMA digital testbus output + encoder_testbus : IN STD_LOGIC_VECTOR(9 DOWNTO 0); -- Test bus from 8B10B encoder + tx_ctrl_testbus : IN STD_LOGIC_VECTOR(9 DOWNTO 0); -- Test bus from TX FIFO + -- Removed old bundling mode inputs + -- input [3:0] rxfifo_shared_sig_in_ch0; // TX FIFO shared signal from channel 0 + -- input [3:0] rxfifo_shared_sig_in_q0_ch0; // TX FIFO shared signal from channel 0 of Quad 0 + + phystatus_int : IN STD_LOGIC; + rxvalid_int : IN STD_LOGIC; + rxstatus_int : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- rate change output from upper layers. + -- frequency switch done from PMA (rising edge of old clock to rising edge of new clock) + -- for bundle + -- Electrical Idle inference mechanism select + + -- reverse parallel loopback requires 4 EIOS to be transmitted up to the upper layer. Used in the CDR + -- control block and electrical idle inference module + -- LMC 01/21/08 + + -- CDR control + -- PLD control of the CDR when rcdr_ctrl_en = 1'b0 + + -- PLD control of PRBS-CID enable + + -- S. Park 3/13/08 - Added for XAUI compliance + + -- S. Park 3/21/08 - Added for XAUI compliance + + -- removed old bundling mode outputs + -- output [3:0] rxfifo_shared_sig_out; // TX FIFO shared signal output + fifo_rd_out_comp : OUT STD_LOGIC; + rxd : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- XGMII rx data to PLD + rev_loop_data : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); -- 10 bit data from RX rate matching + -- FIFO, reverse loopback + rx_clk : OUT STD_LOGIC; -- XGMII rx clock to PLD + bisterr : OUT STD_LOGIC; -- BIST or PRBS done status signal + cg_comma : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- comma is detected in sync_chnl_top to PMA + clk_2_b : OUT STD_LOGIC; -- clk_2 to rcv_sm + rcvd_clk_pma_b : OUT STD_LOGIC; + sync_status : OUT STD_LOGIC; -- Indicate that this lane is now synchronized + -- S. Park 3/21/08 - Removed below two ports + -- output disable_fifo_rd; // disable_fifo_rd from this lane + -- output disable_fifo_wr; // disable_fifo_wr from this lane + align_status_sync : OUT STD_LOGIC; -- synced to clk_2 + dec_data_valid : OUT STD_LOGIC; + dec_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- decoded 8-bit RX data to XAUI RX SM + dec_ctl : OUT STD_LOGIC; -- decoded RX control to XAUI RX SM + running_disp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- indicate that dec_data/dec_ctl is + -- either not valid or having disparity error + selftest_done : OUT STD_LOGIC; -- Status shows that the self test checking is done + selftest_err : OUT STD_LOGIC; -- Status shows that the selftest is successful + err_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- When the self test fails, this records + -- the first byte that error occurs to. + err_ctl : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- When the self test fails, this records + -- the first byte that error occurs to. + prbs_done : OUT STD_LOGIC; -- Indicate that prbs verification is done + prbs_err_lt : OUT STD_LOGIC; -- Indicate that prbs verification is OK + -- - latched version, cleared when reset + signal_detect_out : OUT STD_LOGIC; -- SIGDET out to PLD + align_det_sync : OUT STD_LOGIC; -- Channel is aligned, present for 10 clocks + rd_align : OUT STD_LOGIC; -- Read data has an Align code group + bistdone : OUT STD_LOGIC; + rlv : OUT STD_LOGIC; + rlv_lt : OUT STD_LOGIC; -- RLV status signal to PLD + almost_fl_rmf : OUT STD_LOGIC; -- Comp FIFO almost full flag + full_rmf : OUT STD_LOGIC; -- Comp FIFO full flag + almost_mt_rmf : OUT STD_LOGIC; -- Comp FIFO almost empty flag + empty_rmf : OUT STD_LOGIC; -- Comp FIFO empty flag + freq_lock : OUT STD_LOGIC; -- Frequency lock output flag for PMA + full_rx : OUT STD_LOGIC; -- RX Phase comp. FIFO full flag + empty_rx : OUT STD_LOGIC; -- RX Phase comp. FIFO empty flag + a1a2_k1k2_flag : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- A1A2K1K2 output flag + byteord_flag : OUT STD_LOGIC; -- Byte ordering successfull output flag + rx_pipe_clk : OUT STD_LOGIC; -- Output clock for RX PIPE interface + chnl_test_bus_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- Channel digital testbus output + rx_pipe_soft_reset : OUT STD_LOGIC; -- RX PIPE soft reset + + phystatus : OUT STD_LOGIC; + rxvalid : OUT STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pipe_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + + -- speed change done to PIPE interface (i.e. auto negotiation done) + + -- Asserted when Electrical Idle is detected + + --describes word boundary + + -- CDR control + -- Asserted when K_I or K_X_I is detected on the incoming data + -- force CDR to LTR mode + + -- RX PCS CRAMs + rskpsetbased : IN STD_LOGIC; -- Enable rate matching for PCI-E/PIPE-or + -- other standards based on COMMA DEL DEL.. + rtruebac2bac : IN STD_LOGIC; -- Should be high for all standards + -- except PIPE. Back to back rate matching enable. + rcmpfifourst : IN STD_LOGIC; -- Enable cmpfifourst + rphfifourstrx : IN STD_LOGIC; -- Enable phfifourst_rx + rcomp_size : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- Pattern comparision length CRAMs + rcomp_pat : IN STD_LOGIC_VECTOR(39 DOWNTO 0); -- Sync pattern CRAMs + rrundisp : IN STD_LOGIC_VECTOR(5 DOWNTO 0); -- Run lengh violation setting CRAMs + rib_inv_cd : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Invalid code setting CRAMs for IB + rrlv_en : IN STD_LOGIC; -- RLV enable CRAM + rsync_sm_dis : IN STD_LOGIC; -- GIGE/XAUI Sync SM disable CRAM + rautobtalg_dis : IN STD_LOGIC; -- BITSLIP mode enable CRAM + rdis_rx_disp : IN STD_LOGIC; -- Receive running disparity calculation disable CRAM + rmatchen : IN STD_LOGIC; -- Clock compensation enable CRAM + rgenericfifo : IN STD_LOGIC; -- GenericFIFO mode enable CRAM + rendec_rx : IN STD_LOGIC; -- 10B/8B decoder enable CRAM + rdwidth_rx : IN STD_LOGIC; -- RX parallel interface data width selection CRAM + rlp20ben : IN STD_LOGIC; -- 20-b loopback enable CRAM + rrxfifo_dis : IN STD_LOGIC; -- RX FIFO bypassing CRAM + rpmadwidth_rx : IN STD_LOGIC; -- RX PMA to RX PCS data width selection CRAM + rpma_doublewidth_rx : IN STD_LOGIC; -- RX PMA/PCS double width (16/20) sel CRAM + renumber : IN STD_LOGIC_VECTOR(5 DOWNTO 0); -- Number of consecutive errors without + -- valid data to goto LOSS_OF_SYNC + rknumber : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Number of consecutive commas to reach + -- SYNC_ACQ from LOSS_OF_SYNC + renpolinv_rx : IN STD_LOGIC; -- Allow polarity inversion + rgnumber : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Number of consecutive good data to approach SYNC_ACQ + rclkcmpsqmd : IN STD_LOGIC; -- How many characters to match + rclkcmpsq1p : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- Programmable 20-bit encoded comp sequence pos. disp. + rclkcmpsq1n : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- Programmable 20-bit encoded comp sequence neg. disp. + rclkcmp_pipe_en : IN STD_LOGIC; -- RM PIPE-compatible mode enable + rosnumber : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Length of the ordered set + rosbased : IN STD_LOGIC; -- Enable ordered-set based algorithm + rkchar : IN STD_LOGIC; -- use kchar at cg_bad logic calculation + rcascaded_8b10b_en_rx : IN STD_LOGIC; -- Cascaded 8B/10B decoder enable CRAM + resync_badcg_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- + rencdt_rising : IN STD_LOGIC; -- encdt on rising edge enable CRAM + rcomp_pat_porn : IN STD_LOGIC; -- Positive and negative match enable CRAM + rprbsen_rx : IN STD_LOGIC; -- PRBS Verifier enable CRAM + rprbs_clr_rslt_rx : IN STD_LOGIC; -- PRBS pass/fail flag clear CRAM + rbisten_rx : IN STD_LOGIC; -- BIST Verifier enable CRAM + rbist_clr_rx : IN STD_LOGIC; -- BIST pass/fail flag clear CRAM + rwa_6g_en : IN STD_LOGIC; -- 6G word alignment enable CRAM + rbytord_2sym_en : IN STD_LOGIC; -- Enable 2 symbols byte orderring CRAM + rbysync_polinv_en : IN STD_LOGIC; -- Word alignment polarity inversion enable CRAM + rbytord_6g_mask_en : IN STD_LOGIC; -- Mask out upper byte in 6G 2 symbol comparison + rbytord_s2gx : IN STD_LOGIC; -- Byte ordering like s2gx, only once per PCS reset + rbitloc_rev_en : IN STD_LOGIC; -- Bit reversal enable CRAM + rbyte_rev_en : IN STD_LOGIC; -- Byte swap enable CRAM + rbyteorden : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Byte ordering enable CRAM + rbytordplden : IN STD_LOGIC; -- PLD control signal BYTEORDPLD enable CRAM + rphfifopldenrx : IN STD_LOGIC; -- RX phase comp. FIFO read/write enable CRAM + rautoinsdis : IN STD_LOGIC; -- Disable CRAM for auto insertion of 8'h9C + rppmsel : IN STD_LOGIC_VECTOR(5 DOWNTO 0); -- Programmable PPM ajustment CRAM + rforce0_freqdet : IN STD_LOGIC; -- Forcing FREQDET signal to low CRAM + rforce1_freqdet : IN STD_LOGIC; -- Forcing FREQDET signal to high CRAM + rbytordpat : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- Byte ordering pattern CRAM + rbytordpad : IN STD_LOGIC_VECTOR(9 DOWNTO 0); -- Byte ordering pad pattern CRAM + rforce_sig_det_pcs : IN STD_LOGIC; -- Forcing sigdet to high in PCS CRAM + rfreerun_rx : IN STD_LOGIC; -- RX_CLK out free running during RX PCS reset enable CRAM + rrcvd_clk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- RCVD_CLK domain selection CRAM + rclk_1_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- CLK_1 domain selection CRAM + rclk_2_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- CLK_2 domain selection CRAM + rrx_rd_clk_sel : IN STD_LOGIC; -- RX FIFO read clock selection CRAM + rall_one_dect_only : IN STD_LOGIC; -- PRBS Verifier detect all one only enable CRAM + rtest_bus_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Per channel test bus selection CRAMs + r8b10b_dec_ibm_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- 8B10B Decoder fix enable CRAM + rrxfifo_lowlatency_en : IN STD_LOGIC; -- RX FIFO low latency enable CRAM + rppm_cnt_reset : IN STD_LOGIC; -- PPM counter reset CRAM (latched version on Test bus) + sel_gp_md : IN STD_LOGIC; -- Select Quad or Group Mode + rclkcmpinsertpad : IN STD_LOGIC; -- Rate matching pad insertion enable CRAM + + -- CRAM for enable low-latency PCS bypass mode + -- Programmable 4 us (Gen1) of 2 us (Gen2) timer during which CDR control block controls the PPM detector. + -- Enables PCS Wrapback mode + -- CID pattern to be 0 or 1 + -- Length of CID pattern in cycles + + -- Common PCS CRAMs + rindv_rx : IN STD_LOGIC; -- RX SM bypassing CRAM + dskwclksel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Select Deskew Clock + rdskposdisp : IN STD_LOGIC; -- Match the programmed de-skew pattern only + rdskchrp : IN STD_LOGIC_VECTOR(9 DOWNTO 0); -- Programmable Deskew Char. Pos. Disp. + rendec_data_sel_rx : IN STD_LOGIC; -- RX 8B10B decoder data out selection CRAM + -- Removed old bundling mode MDIOs + -- input rphfifo_master_sel_rx; // TX Phase comp. FIFO pointers selection CRAM + + -- Common TX RX CRAM for BIST/PRBS + rprbs_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- PRBS selection CRAM + rbist_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- BIST selection CRAM + rcxpat_chnl_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- CRPAT or CJPAT selection CRAM + rstart_threshold : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rins_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rdel_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rfull_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rempty_threshold : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rinvalid_code_err_only : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rrxpcsbypass_en : IN STD_LOGIC; + rfts_count : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rpcs_wrapback_en : IN STD_LOGIC; + rcid_pattern_rx : IN STD_LOGIC; + rcid_len_rx : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- CRAM for auto negotiation module + rauto_speed_ena : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rate : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + speed_change : OUT STD_LOGIC; + -- Programmable counter threshold for pma_done_int (1ms) + -- disable EIOS priority over eidle inference + -- enable usage of signal detect under gen1 conditions when eidle + -- is enabled, eidle inference when gen2 is enabled + + -- CRAM for Eidle Inference + -- Enable/disable Electrical Idle Inference module + -- The number of COMs required to enter/exit Eidle + -- values greater than 2 entails that syncstatus is used + + -- CDR control CRAMS + -- Enable/Disable CDR control block + -- Enable CID mode (CDR) + -- Enable masking of rxvalid logic + -- Minimum programmable period of time that LTR is asserted when the CDR control block is enabled. + -- Masking period of data upon exiting EIdle; for high BER period + + -- new signal inputs for bundling + rx_div2_sync_in_centrl : IN STD_LOGIC; + rx_div2_sync_in_quad_up : IN STD_LOGIC; + rx_div2_sync_in_quad_down : IN STD_LOGIC; + reset_pc_ptrs_in_centrl : IN STD_LOGIC; + reset_pc_ptrs_in_quad_up : IN STD_LOGIC; + reset_pc_ptrs_in_quad_down : IN STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_quad_up : IN STD_LOGIC; + wr_enable_in_quad_down : IN STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_quad_up : IN STD_LOGIC; + rd_enable_in_quad_down : IN STD_LOGIC; + rx_we_in_centrl : IN STD_LOGIC; + rx_we_in_quad_up : IN STD_LOGIC; + rx_we_in_quad_down : IN STD_LOGIC; + speed_change_in_centrl : IN STD_LOGIC; + -- pipeline inputs for bundling + rx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + rx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_up : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + rx_we_in_pipe_quad_up : IN STD_LOGIC; + rx_we_in_pipe_quad_down : IN STD_LOGIC; + speed_change_in_pipe_quad_up : IN STD_LOGIC; + speed_change_in_pipe_quad_down : IN STD_LOGIC; + -- Bundle Mode Inputs for config_sel + config_sel_centrl : IN STD_LOGIC; + config_sel_quad_up : IN STD_LOGIC; + config_sel_quad_down : IN STD_LOGIC; + + -- new MDIO inputs for bundling and auto speed + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rpipeline_bypass_rx : IN STD_LOGIC; + rauto_deassert_pc_rst_cnt : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rauto_pc_en_cnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rself_sw_en_rx : IN STD_LOGIC; + + -- S. Park 2/8/08 - New CRAM inputs for PPM Detector + + -- new outputs for bundling and auto speed + rx_div2_sync_out_pipe_up : OUT STD_LOGIC; + rx_we_out_pipe_up : OUT STD_LOGIC; + wr_enable_out_pipe_up : OUT STD_LOGIC; + rd_enable_out_pipe_up : OUT STD_LOGIC; + reset_pc_ptrs_out_pipe_up : OUT STD_LOGIC; + speed_change_out_pipe_up : OUT STD_LOGIC; + rx_div2_sync_out_pipe_down : OUT STD_LOGIC; + rx_we_out_pipe_down : OUT STD_LOGIC; + wr_enable_out_pipe_down : OUT STD_LOGIC; + rd_enable_out_pipe_down : OUT STD_LOGIC; + reset_pc_ptrs_out_pipe_down : OUT STD_LOGIC; + speed_change_out_pipe_down : OUT STD_LOGIC; + + dis_pc_byte : OUT STD_LOGIC; + reset_pc_ptrs : OUT STD_LOGIC; + + -- S. Park 3/13/08 - Added for XAUI compliance + + -- S. Park 3/21/08 - Added for XAUI compliance + + -- PMA rate change control + pcie_switch : OUT STD_LOGIC; + reidleinferenable : IN STD_LOGIC; + reidle_com_detect : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + pipe_loopbk : IN STD_LOGIC; + rxelecidle_int : OUT STD_LOGIC; + rpma_done_count : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + riei_eios_priority_dis : IN STD_LOGIC; + rgen1_sigdet_ena : IN STD_LOGIC; + rerr_flags_sel : IN STD_LOGIC; + rrxpcsclkpwdn : IN STD_LOGIC; + rcdr_ctrl_en : IN STD_LOGIC; + rcid_en : IN STD_LOGIC; + rrxvalid_mask : IN STD_LOGIC; + rwait_count : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rmask_count : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + pld_ltr : IN STD_LOGIC; + early_eios : OUT STD_LOGIC; + ltr : OUT STD_LOGIC; + prbs_cid_en : IN STD_LOGIC; + wa_boundary : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + tx_div2_sync_out_pipe_up : IN STD_LOGIC; + fifo_select_out_pipe_up : IN STD_LOGIC; + tx_wr_enable_out_pipe_up : IN STD_LOGIC; + tx_rd_enable_out_pipe_up : IN STD_LOGIC; + tx_div2_sync_out_pipe_down : IN STD_LOGIC; + fifo_select_out_pipe_down : IN STD_LOGIC; + tx_wr_enable_out_pipe_down : IN STD_LOGIC; + tx_rd_enable_out_pipe_down : IN STD_LOGIC; + rwait_for_phfifo_cnt : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + rppm_post_eidle_del : IN STD_LOGIC; + rppm_gen1_2xcnt_en : IN STD_LOGIC; + cg_comp_rd_d_ch0 : IN STD_LOGIC; + cg_comp_rd_d_ch1 : IN STD_LOGIC; + cg_comp_rd_d_ch2 : IN STD_LOGIC; + cg_comp_rd_d_ch3 : IN STD_LOGIC; + cg_comp_wr_ch0 : IN STD_LOGIC; + cg_comp_wr_ch1 : IN STD_LOGIC; + cg_comp_wr_ch2 : IN STD_LOGIC; + cg_comp_wr_ch3 : IN STD_LOGIC; + cg_comp_rd_d_out : OUT STD_LOGIC; + cg_comp_wr_out : OUT STD_LOGIC; + del_cond_met_0 : IN STD_LOGIC; + fifo_ovr_0 : IN STD_LOGIC; + latency_comp_0 : IN STD_LOGIC; + insert_incomplete_0 : IN STD_LOGIC; + del_cond_met_out : OUT STD_LOGIC; + fifo_ovr_out : OUT STD_LOGIC; + latency_comp_out : OUT STD_LOGIC; + insert_incomplete_out : OUT STD_LOGIC; + pcs_wrapback_in : IN STD_LOGIC_VECTOR(69 DOWNTO 0) + ); +END cycloneiv_hssi_rx_digi; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_digi IS + COMPONENT cycloneiv_hssi_rx_digi_bist_ver + PORT ( + clk_2 : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + sync_status : IN STD_LOGIC; + rbisten_rx : IN STD_LOGIC; + rpmadwidth_rx : IN STD_LOGIC; + rpma_doublewidth_rx : IN STD_LOGIC; + rdwidth_rx : IN STD_LOGIC; + rbist_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcxpat_chnl_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rbist_clr_rx : IN STD_LOGIC; + rxd : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + rxc : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + prbs_done : IN STD_LOGIC; + prbs_err : IN STD_LOGIC; + cur_state : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + selftest_err : OUT STD_LOGIC; + selftest_done : OUT STD_LOGIC; + bisterr : OUT STD_LOGIC; + bistdone : OUT STD_LOGIC; + err_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + err_ctl : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_auto_speed_neg + PORT ( + refclk : IN STD_LOGIC; + rxpcs_rst_int : IN STD_LOGIC; + rate : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + config_sel_centrl : IN STD_LOGIC; + config_sel_quad_up : IN STD_LOGIC; + config_sel_quad_down : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + singleorbundle : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rpma_done_count : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + rauto_deassert_pc_rst_cnt : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rauto_pc_en_cnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rwait_for_phfifo_cnt : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + config_sel : OUT STD_LOGIC; + pcie_switch : OUT STD_LOGIC; + speed_change : OUT STD_LOGIC; + dis_pc_byte : OUT STD_LOGIC; + reset_pc_ptrs : OUT STD_LOGIC; + cs : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_rx_ctrl + PORT ( + soft_reset : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + rx_wr_clk : IN STD_LOGIC; + rx_rd_clk : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rrxfifo_dis : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rendec_data_sel_rx : IN STD_LOGIC; + rwa_6g_en : IN STD_LOGIC; + rrxfifo_lowlatency_en : IN STD_LOGIC; + endec_rx : IN STD_LOGIC; + rinvalid_code_err_only : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rpmadatawidth : IN STD_LOGIC; + rdwidth : IN STD_LOGIC; + rautoinsdis : IN STD_LOGIC; + rbytorden : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rbytord_2sym_en : IN STD_LOGIC; + rbytordpat : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + rbytordpadval : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rbytordplden : IN STD_LOGIC; + bytordplden : IN STD_LOGIC; + rsync_comp_size : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rsync_comp_pat : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + rsync_comp_porn : IN STD_LOGIC; + rsync_sm_dis : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rbytord_6g_mask_en : IN STD_LOGIC; + rbytord_s2gx : IN STD_LOGIC; + invalid_code_delay : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + sigdetni : IN STD_LOGIC; + dec_data_valid_pre : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dec_data_valid : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rx_data_rs : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_control_rs : IN STD_LOGIC; + rx_data_dt : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + rx_control_dt : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + tenb_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + sync_resync_pre : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + sync_resync_delay : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + disp_err_delay : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + disp_val_delay : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ovr_undflow : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rrxfifo_urst_en : IN STD_LOGIC; + rxfifo_urst : IN STD_LOGIC; + rrxphfifopldctl_en : IN STD_LOGIC; + pld_wr_dis : IN STD_LOGIC; + pld_re : IN STD_LOGIC; + rrxpcsbypass_en : IN STD_LOGIC; + phystatus_int : IN STD_LOGIC; + rxvalid_int : IN STD_LOGIC; + rxstatus_int : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + reset_pc_ptrs : IN STD_LOGIC; + reset_pc_ptrs_centrl : IN STD_LOGIC; + reset_pc_ptrs_quad_up : IN STD_LOGIC; + reset_pc_ptrs_quad_down : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + dis_pc_byte : IN STD_LOGIC; + wr_enable_centrl : IN STD_LOGIC; + wr_enable_quad_up : IN STD_LOGIC; + wr_enable_quad_down : IN STD_LOGIC; + rd_enable_centrl : IN STD_LOGIC; + rd_enable_quad_up : IN STD_LOGIC; + rd_enable_quad_down : IN STD_LOGIC; + rx_we_in_centrl : IN STD_LOGIC; + rx_we_in_quad_up : IN STD_LOGIC; + rx_we_in_quad_down : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rxd : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rxd_9 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxd_19 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + running_disp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + signal_detect_out : OUT STD_LOGIC; + rxd_lpbk : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); + rx_we_out : OUT STD_LOGIC; + ph_fifo_empty : OUT STD_LOGIC; + ph_fifo_full : OUT STD_LOGIC; + wr_enable_out : OUT STD_LOGIC; + rd_enable_out : OUT STD_LOGIC; + bytord_valid_out : OUT STD_LOGIC; + soft_reset_rclk1 : OUT STD_LOGIC; + soft_reset_wclk1 : OUT STD_LOGIC; + phystatus : OUT STD_LOGIC; + rxvalid : OUT STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pipe_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + wr_enable2 : OUT STD_LOGIC; + wptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rd_enable2 : OUT STD_LOGIC; + rptr_bin : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_wrapback_in : IN STD_LOGIC_VECTOR(69 DOWNTO 0); + rpcs_wrapback_en : IN STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_dskw_fifo + PORT ( + rcvd_clk : IN STD_LOGIC; + sudi : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + soft_reset : IN STD_LOGIC; + fifo_rst_rd_qd : IN STD_LOGIC; + fifo_rst_rd_gp : IN STD_LOGIC; + clk_1 : IN STD_LOGIC; + en_dskw_qd : IN STD_LOGIC; + en_dskw_gp : IN STD_LOGIC; + sel_gp_md : IN STD_LOGIC; + rdskposdisp : IN STD_LOGIC; + rdskchrp : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + align_det_sync : OUT STD_LOGIC; + rd_align : OUT STD_LOGIC; + audi : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + audi_pre : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_prbs_ver + PORT ( + rcvd_clk : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rprbs_clr_rslt_rx : IN STD_LOGIC; + rprbs_en_rx : IN STD_LOGIC; + rpmadwidth_rx : IN STD_LOGIC; + rpma_doublewidth_rx : IN STD_LOGIC; + rprbs_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rall_one_dect_only : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + sync_status : IN STD_LOGIC; + verify_on : OUT STD_LOGIC; + prbs_done : OUT STD_LOGIC; + prbs_err : OUT STD_LOGIC; + encdet_prbs : OUT STD_LOGIC; + cid_en : IN STD_LOGIC; + rcid_len : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rcid_pattern : IN STD_LOGIC; + prbs_err_lt : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_freqdet + PORT ( + scan_mode : IN STD_LOGIC; + ppmsel : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + fref : IN STD_LOGIC; + fvcobyn : IN STD_LOGIC; + pd : IN STD_LOGIC; + rforcehigh : IN STD_LOGIC; + rforcelow : IN STD_LOGIC; + hard_reset : IN STD_LOGIC; + ppm_cnt_reset : IN STD_LOGIC; + gen2ngen1_indv : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rppm_gen1_2xcnt_en : IN STD_LOGIC; + eidle_exit : IN STD_LOGIC; + rppm_post_eidle_del : IN STD_LOGIC; + freq_lock : OUT STD_LOGIC; + ppm_cnt_latch : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_pcs_channel_testbus + PORT ( + test_bus_in0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in2 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in3 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in4 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in5 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in6 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in7 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in10 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in11 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in13 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + test_bus_in14 : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rtest_bus_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + chnl_test_bus_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_wordalign + PORT ( + rst : IN STD_LOGIC; + clk : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + wa_6g_en : IN STD_LOGIC; + signal_detect : IN STD_LOGIC; + rforce_sig_det_pcs : IN STD_LOGIC; + lpbk_en : IN STD_LOGIC; + pmadwidth : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dwidth : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + pudi : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + pudr : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + rencdt_rising : IN STD_LOGIC; + encdt : IN STD_LOGIC; + comp_pat_porn : IN STD_LOGIC; + comp_pat : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + comp_pat_size : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + resync_badcg_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + r8b10b_dec_ibm_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + autobytealign_dis : IN STD_LOGIC; + rrxpcsbypass_en : IN STD_LOGIC; + bitslip : IN STD_LOGIC; + rlv_en : IN STD_LOGIC; + max_rlv_sel : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + disable_rx_disp : IN STD_LOGIC; + ib_invalid_code : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rpolinv_en : IN STD_LOGIC; + rbitloc_rev_en : IN STD_LOGIC; + rbyte_rev_en : IN STD_LOGIC; + polinv_en : IN STD_LOGIC; + bitloc_rev_en : IN STD_LOGIC; + byte_rev_en : IN STD_LOGIC; + sync_sm_dis : IN STD_LOGIC; + prbs_en : IN STD_LOGIC; + encdet_prbs : IN STD_LOGIC; + a1a2_size : IN STD_LOGIC; + knumber : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + gnumber : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + enumber : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rosnumber : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rosbased : IN STD_LOGIC; + rkchar : IN STD_LOGIC; + pipe_loose_sync : IN STD_LOGIC; -- ww35.2008 + signal_detect_rcvdclk : OUT STD_LOGIC; + sudi : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + sync_status : OUT STD_LOGIC; + cg_syncpat : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rlv : OUT STD_LOGIC; + rlv_lt : OUT STD_LOGIC; + a1a2_k1k2_flag : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + kchar : OUT STD_LOGIC; + wa_boundary : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sudi_pre : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + adata : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + adata_valid : OUT STD_LOGIC; + rst1 : OUT STD_LOGIC; + testbus : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + kcount : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_eii_module + PORT ( + rcvd_clk : IN STD_LOGIC; + rxpcsrst : IN STD_LOGIC; + reidleinferenable : IN STD_LOGIC; + reidle_com_detect : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rindv_rx : IN STD_LOGIC; + riei_eios_priority_dis : IN STD_LOGIC; + rgen1_sigdet_ena : IN STD_LOGIC; + rwait_count : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + skposdetect : IN STD_LOGIC; + syncstatus : IN STD_LOGIC; + sudi : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + kflag : IN STD_LOGIC; + kcount : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + eiosdetect_int : IN STD_LOGIC; + inferred_rxvalid : IN STD_LOGIC; + signaldetect : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + pipe_loopbk : IN STD_LOGIC; + rxelecidle_int : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_rxclk_ctl + PORT ( + pld_rx_clk : IN STD_LOGIC; + rcvd_clk_pma : IN STD_LOGIC; + rcvd_clk0_pma : IN STD_LOGIC; + tx_pma_clk : IN STD_LOGIC; + refclk_pma : IN STD_LOGIC; + fref : IN STD_LOGIC; + clklow : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + rx_div2_sync_centrl : IN STD_LOGIC; + rx_div2_sync_quad_up : IN STD_LOGIC; + rx_div2_sync_quad_down : IN STD_LOGIC; + rrcvd_clk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_1_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_2_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrx_rd_clk_sel : IN STD_LOGIC; + rxrst : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rdwidth_rx : IN STD_LOGIC; + rfreerun_rx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rrxpcsclkpwdn : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rself_sw_en_rx : IN STD_LOGIC; + fref_muxed : OUT STD_LOGIC; + clklow_muxed : OUT STD_LOGIC; + rcvd_clk : OUT STD_LOGIC; + clk_1_b : OUT STD_LOGIC; + clk_2_b : OUT STD_LOGIC; + rx_wr_clk : OUT STD_LOGIC; + rx_rd_clk : OUT STD_LOGIC; + rx_clk : OUT STD_LOGIC; + rcvd_clk_pma_b : OUT STD_LOGIC; + clk_2_b_raw : OUT STD_LOGIC; + rx_wr_clk_raw : OUT STD_LOGIC; + rx_rd_clk_raw : OUT STD_LOGIC; + rx_div2_sync_out : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_comp_chnl_top + PORT ( + align_status : IN STD_LOGIC; + align_status_sync : OUT STD_LOGIC; + align_status_sync_0 : IN STD_LOGIC; + align_status_sync_2 : IN STD_LOGIC; + audi : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + audi_pre : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + cg_comp_rd_d_ch0 : IN STD_LOGIC; + cg_comp_rd_d_ch1 : IN STD_LOGIC; + cg_comp_rd_d_ch2 : IN STD_LOGIC; + cg_comp_rd_d_ch3 : IN STD_LOGIC; + cg_comp_rd_d_out : OUT STD_LOGIC; + cg_comp_wr_ch0 : IN STD_LOGIC; + cg_comp_wr_ch1 : IN STD_LOGIC; + cg_comp_wr_ch2 : IN STD_LOGIC; + cg_comp_wr_ch3 : IN STD_LOGIC; + cg_comp_wr_out : OUT STD_LOGIC; + clk_1 : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + cmpfifourst : IN STD_LOGIC; + comp_curr_st : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + cudi : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + cudi_valid : OUT STD_LOGIC; + del_cond_met_0 : IN STD_LOGIC; + del_cond_met_out : OUT STD_LOGIC; + dskwclksel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + fifo_cnt : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + fifo_ovr_0 : IN STD_LOGIC; + fifo_ovr_out : OUT STD_LOGIC; + fifo_rd_in_comp_0 : IN STD_LOGIC; + fifo_rd_in_comp_2 : IN STD_LOGIC; + fifo_rd_out_comp : OUT STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + hard_reset : IN STD_LOGIC; + inferred_rxvalid : IN STD_LOGIC; + insert_incomplete_0 : IN STD_LOGIC; + insert_incomplete_out : OUT STD_LOGIC; + is_lane0 : IN STD_LOGIC; + latency_comp_0 : IN STD_LOGIC; + latency_comp_out : OUT STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rclkcmpsq1n : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + rclkcmpsq1p : IN STD_LOGIC_VECTOR (19 DOWNTO 0); + rclkcmpsqmd : IN STD_LOGIC; + rcmpfifourst : IN STD_LOGIC; + rdel_threshold : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + rdenable : IN STD_LOGIC; + rdfifo_almost_empty : OUT STD_LOGIC; + rdfifo_almost_full : OUT STD_LOGIC; + rdfifo_empty : OUT STD_LOGIC; + rdfifo_full : OUT STD_LOGIC; + rdwidth_rx : IN STD_LOGIC; + rempty_threshold : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rev_loop_data : OUT STD_LOGIC_VECTOR (19 DOWNTO 0); + rfreq_sel : IN STD_LOGIC; + rfull_threshold : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + rgenericfifo : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rins_threshold : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + rmatchen : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rskpsetbased : IN STD_LOGIC; + rstart_threshold : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rtruebac2bac : IN STD_LOGIC; + rwa_6g_en : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + skpos_det : OUT STD_LOGIC; + soft_reset : IN STD_LOGIC; + sudi : IN STD_LOGIC_VECTOR (27 DOWNTO 0); + sudi_pre : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + sync_status : IN STD_LOGIC; + wrenable : IN STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_dec_chnl_top + PORT ( + rst : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + cascaded_8b10b_en : IN STD_LOGIC; + r8b10b_dec_ibm_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_in_valid : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + renpolinv : IN STD_LOGIC; + rerr_flags_sel : IN STD_LOGIC; + polinv : IN STD_LOGIC; + rrxpcsbypass_en : IN STD_LOGIC; + dec_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + disp_err_delay : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + disp_val_delay : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + sync_resync_delay : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dec_data_valid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dec_ctl : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + invalid_code_delay : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ovr_undflow : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tenb_data : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + rlb_data : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_cdr_ctrl + PORT ( + rcvd_clk : IN STD_LOGIC; + rxpcs_reset_int : IN STD_LOGIC; + rcdr_ctrl_en : IN STD_LOGIC; + rcid_en : IN STD_LOGIC; + rrxvalid_mask : IN STD_LOGIC; + rwait_count : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rmask_count : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rindv_rx : IN STD_LOGIC; + pld_ltr : IN STD_LOGIC; + pipe_loopbk : IN STD_LOGIC; + adata : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + adata_valid : IN STD_LOGIC; + inferred_rxvalid : OUT STD_LOGIC; + eiosdetect_int : OUT STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + eidle_exit : OUT STD_LOGIC; + sigdet : IN STD_LOGIC; + early_eios : OUT STD_LOGIC; + ltr : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rx_digi_iq_pipe_rx + PORT ( + clk_2_b_raw : IN STD_LOGIC; + rx_wr_clk_raw : IN STD_LOGIC; + rx_rd_clk_raw : IN STD_LOGIC; + rxrst : IN STD_LOGIC; + soft_reset_rclk1 : IN STD_LOGIC; + soft_reset_wclk1 : IN STD_LOGIC; + rx_div2_sync_in_centrl : IN STD_LOGIC; + rx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + rx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + reset_pc_ptrs_in_centrl : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_up : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + rx_we_in_centrl : IN STD_LOGIC; + rx_we_in_pipe_quad_up : IN STD_LOGIC; + rx_we_in_pipe_quad_down : IN STD_LOGIC; + speed_change_in_centrl : IN STD_LOGIC; + speed_change_in_pipe_quad_up : IN STD_LOGIC; + speed_change_in_pipe_quad_down : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rpipeline_bypass_rx : IN STD_LOGIC; + rfreerun_rx : IN STD_LOGIC; + rx_div2_sync_out_pipe : OUT STD_LOGIC; + rx_we_out_pipe : OUT STD_LOGIC; + wr_enable_out_pipe : OUT STD_LOGIC; + rd_enable_out_pipe : OUT STD_LOGIC; + reset_pc_ptrs_out_pipe : OUT STD_LOGIC; + speed_change_out_pipe : OUT STD_LOGIC + ); + END COMPONENT; + + + -- new signals in this module for bundling and auto speed + SIGNAL clk_2_b_raw : STD_LOGIC; + SIGNAL rx_wr_clk_raw : STD_LOGIC; + SIGNAL rx_rd_clk_raw : STD_LOGIC; + SIGNAL nc_new_bundle1 : STD_LOGIC; + SIGNAL nc_new_bundle2 : STD_LOGIC; + SIGNAL nc_new_bundle3 : STD_LOGIC; + SIGNAL rx_we_out_testbus : STD_LOGIC; + SIGNAL config_sel_nc : STD_LOGIC; + + -- Wiring Section + -- to rcv_sm in centrl_macro + SIGNAL rcvd_clk : STD_LOGIC; -- Recovered data clock + SIGNAL rx_rd_clk : STD_LOGIC; + SIGNAL rx_data_9_rc : STD_LOGIC_VECTOR(1 DOWNTO 0); -- rx data bit 9 from rx_ctrl + -- when 10-bit code-group is passing + -- over XGMII + SIGNAL rx_data_19_rc : STD_LOGIC_VECTOR(1 DOWNTO 0); -- rx data bit 19 from rx_ctrl + -- when 10-bit code-group is passing + -- over XGMII + SIGNAL rx_control_rc_16 : STD_LOGIC_VECTOR(3 DOWNTO 0); -- XGMII rx control from rx_ctrl + SIGNAL sync_status_st : STD_LOGIC; -- Indicate that this lane is + -- now synchronized + SIGNAL sudi : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Synchronized code group + parity + -- error status from sync_chnl_top + SIGNAL sudi_pre : STD_LOGIC_VECTOR(13 DOWNTO 0); -- 13-bit data one cycle earlier + SIGNAL cudi : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Clock-compensated code group + -- + parity + -- error status from sync_chnl_top + SIGNAL rx_data_dt : STD_LOGIC_VECTOR(15 DOWNTO 0); -- 2 decoded 8-bit rx data + SIGNAL rx_ctl_dt : STD_LOGIC_VECTOR(1 DOWNTO 0); -- 2 decoded rx controls + SIGNAL tenb_data : STD_LOGIC_VECTOR(19 DOWNTO 0); -- rx 20-bit code group bus used when + -- ENDEC is 1'b0 + SIGNAL audi : STD_LOGIC_VECTOR(13 DOWNTO 0); -- Aligned code group + parity error + -- status from dskw_top + SIGNAL audi_pre : STD_LOGIC_VECTOR(13 DOWNTO 0); + -- comma is detected in sync_chnl_top + SIGNAL disable_fifo_rd : STD_LOGIC; -- disable_fifo_rd from this lane + SIGNAL disable_fifo_wr : STD_LOGIC; -- disable_fifo_wr from this lane + -- Indicate that this lane is now + -- synchronized + -- decoded 8-bit rx data + -- decoded rx control + -- indicate that dec_data/dec_ctl + -- is either not valid or having + -- disparity error + SIGNAL invalid_code_delay : STD_LOGIC_VECTOR(1 DOWNTO 0); -- indicate that dec_data/dec_ctl is + -- having diparity error + -- Status shows that the self test + -- checking is done + -- Status shows that the selftest is + -- successful + -- When the self test fails, this + -- records the first byte that error + -- occurs to. + -- When the self test fails, this + -- records the first byte that error + -- occurs to. + -- Indicate that prbs verification is + -- done + -- Indicate that prbs verification is + -- OK - latched version, cleared when + -- ENBIST is cleared. + SIGNAL prbs_err : STD_LOGIC; + -- signal_detect to status pin/bit for + -- PMA-only operation + SIGNAL signal_detect : STD_LOGIC; + SIGNAL disp_err_delay : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL disp_val_delay : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sync_resync_delay : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL high_dec_data_valid : STD_LOGIC; + SIGNAL soft_reset_int : STD_LOGIC; + SIGNAL cudi_valid : STD_LOGIC; + SIGNAL encdet_prbs : STD_LOGIC; + SIGNAL ovr_undflow : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Signals over or underflow + -- Merged to save bit in the synchronous + -- datapath + SIGNAL clk_1_b : STD_LOGIC; + -- 10 bit data from RX rate matching + -- FIFO, reverse loopback + SIGNAL rxd_lpbk : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL rx_wr_clk : STD_LOGIC; + + SIGNAL fref_muxed : STD_LOGIC; + SIGNAL clklow_muxed : STD_LOGIC; + SIGNAL skposdetect : STD_LOGIC; + + SIGNAL ausm_cs : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- Wire for test bus + SIGNAL prbs_verify_on : STD_LOGIC; + SIGNAL word_align_testbus : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL bist_cur_state : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL wr_enable2 : STD_LOGIC; + SIGNAL rd_enable2 : STD_LOGIC; + SIGNAL wptr_bin : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rptr_bin : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL comp_fifo_cnt : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ppm_cnt : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL comp_curr_st : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL kcount : STD_LOGIC_VECTOR(9 DOWNTO 0); + + --shawn: unused wire to fix open connections () + SIGNAL rev_loop_data_enc : STD_LOGIC_VECTOR(19 DOWNTO 0); -- unused from encoder + SIGNAL signal_detect_rcvdclk_dummy : STD_LOGIC; + + --shawn: implicit declaration + SIGNAL rst1 : STD_LOGIC; + + -- S. Park 3/13/08 - New wires added for connectivity to comp_chnl_top + + -- S. Park 3/21/08 - Added wires for XAUI compliance + + --assign soft_reset_int = (scan_mode) ? 1'b0 : rxpcs_rst ; + + -- WA + SIGNAL adata : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL adata_valid : STD_LOGIC; + SIGNAL kchar : STD_LOGIC; + -- CDR control block + SIGNAL eiosdetect_int : STD_LOGIC; + SIGNAL inferred_rxvalid : STD_LOGIC; + SIGNAL eidle_exit : STD_LOGIC; + SIGNAL dec_data_valid_temp : STD_LOGIC_VECTOR(1 DOWNTO 0); --shawn - VHDL translation + -- X-HDL generated signals + + SIGNAL xhdl65 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl66 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl67 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl68 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl69 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL xhdl70 : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL xhdl71 : STD_LOGIC_VECTOR(27 DOWNTO 0); + SIGNAL xhdl72 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl73 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl74 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl75 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl76 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl77 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl78 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl79 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl80 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl81 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl82 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl83 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL xhdl84 : STD_LOGIC_VECTOR(9 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL soft_reset_rclk1_xhdl58 : STD_LOGIC; + SIGNAL fifo_rd_out_comp_xhdl22 : STD_LOGIC; + SIGNAL rxd_xhdl51 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rev_loop_data_xhdl41 : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL rx_clk_xhdl45 : STD_LOGIC; + SIGNAL bisterr_xhdl6 : STD_LOGIC; + SIGNAL cg_comma_xhdl8 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL clk_2_b_xhdl12 : STD_LOGIC; + SIGNAL rcvd_clk_pma_b_xhdl34 : STD_LOGIC; + SIGNAL align_status_sync_xhdl2 : STD_LOGIC; + SIGNAL dec_data_valid_xhdl13 : STD_LOGIC; + SIGNAL running_disp_xhdl44 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL selftest_done_xhdl55 : STD_LOGIC; + SIGNAL selftest_err_xhdl56 : STD_LOGIC; + SIGNAL err_data_xhdl20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL err_ctl_xhdl19 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL prbs_done_xhdl32 : STD_LOGIC; + SIGNAL prbs_err_lt_xhdl33 : STD_LOGIC; + SIGNAL signal_detect_out_xhdl57 : STD_LOGIC; + SIGNAL align_det_sync_xhdl1 : STD_LOGIC; + SIGNAL rd_align_xhdl35 : STD_LOGIC; + SIGNAL bistdone_xhdl5 : STD_LOGIC; + SIGNAL rlv_xhdl42 : STD_LOGIC; + SIGNAL rlv_lt_xhdl43 : STD_LOGIC; + SIGNAL almost_fl_rmf_xhdl3 : STD_LOGIC; + SIGNAL full_rmf_xhdl24 : STD_LOGIC; + SIGNAL almost_mt_rmf_xhdl4 : STD_LOGIC; + SIGNAL empty_rmf_xhdl17 : STD_LOGIC; + SIGNAL freq_lock_xhdl23 : STD_LOGIC; + SIGNAL full_rx_xhdl25 : STD_LOGIC; + SIGNAL empty_rx_xhdl18 : STD_LOGIC; + SIGNAL a1a2_k1k2_flag_xhdl0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL byteord_flag_xhdl7 : STD_LOGIC; + SIGNAL chnl_test_bus_out_xhdl11 : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL rx_pipe_soft_reset_xhdl48 : STD_LOGIC; + SIGNAL phystatus_xhdl30 : STD_LOGIC; + SIGNAL rxvalid_xhdl54 : STD_LOGIC; + SIGNAL rxstatus_xhdl53 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL pipe_data_xhdl31 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL speed_change_xhdl59 : STD_LOGIC; + SIGNAL rx_div2_sync_out_pipe_up_xhdl47 : STD_LOGIC; + SIGNAL rx_we_out_pipe_up_xhdl50 : STD_LOGIC; + SIGNAL wr_enable_out_pipe_up_xhdl64 : STD_LOGIC; + SIGNAL rd_enable_out_pipe_up_xhdl37 : STD_LOGIC; + SIGNAL reset_pc_ptrs_out_pipe_up_xhdl40 : STD_LOGIC; + SIGNAL speed_change_out_pipe_up_xhdl61 : STD_LOGIC; + SIGNAL rx_div2_sync_out_pipe_down_xhdl46 : STD_LOGIC; + SIGNAL rx_we_out_pipe_down_xhdl49 : STD_LOGIC; + SIGNAL wr_enable_out_pipe_down_xhdl63 : STD_LOGIC; + SIGNAL rd_enable_out_pipe_down_xhdl36 : STD_LOGIC; + SIGNAL reset_pc_ptrs_out_pipe_down_xhdl39 : STD_LOGIC; + SIGNAL speed_change_out_pipe_down_xhdl60 : STD_LOGIC; + SIGNAL dis_pc_byte_xhdl15 : STD_LOGIC; + SIGNAL reset_pc_ptrs_xhdl38 : STD_LOGIC; + SIGNAL pcie_switch_xhdl29 : STD_LOGIC; + SIGNAL rxelecidle_int_xhdl52 : STD_LOGIC; + SIGNAL early_eios_xhdl16 : STD_LOGIC; + SIGNAL ltr_xhdl28 : STD_LOGIC; + SIGNAL wa_boundary_xhdl62 : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cg_comp_rd_d_out_xhdl9 : STD_LOGIC; + SIGNAL cg_comp_wr_out_xhdl10 : STD_LOGIC; + SIGNAL del_cond_met_out_xhdl14 : STD_LOGIC; + SIGNAL fifo_ovr_out_xhdl21 : STD_LOGIC; + SIGNAL latency_comp_out_xhdl27 : STD_LOGIC; + SIGNAL insert_incomplete_out_xhdl26 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + soft_reset_rclk1 <= soft_reset_rclk1_xhdl58; + fifo_rd_out_comp <= fifo_rd_out_comp_xhdl22; + rxd <= rxd_xhdl51; + rev_loop_data <= rev_loop_data_xhdl41; + rx_clk <= rx_clk_xhdl45; + bisterr <= bisterr_xhdl6; + cg_comma <= cg_comma_xhdl8; + clk_2_b <= clk_2_b_xhdl12; + rcvd_clk_pma_b <= rcvd_clk_pma_b_xhdl34; + align_status_sync <= align_status_sync_xhdl2; + dec_data_valid <= dec_data_valid_xhdl13; + running_disp <= running_disp_xhdl44; + selftest_done <= selftest_done_xhdl55; + selftest_err <= selftest_err_xhdl56; + err_data <= err_data_xhdl20; + err_ctl <= err_ctl_xhdl19; + prbs_done <= prbs_done_xhdl32; + prbs_err_lt <= prbs_err_lt_xhdl33; + signal_detect_out <= signal_detect_out_xhdl57; + align_det_sync <= align_det_sync_xhdl1; + rd_align <= rd_align_xhdl35; + bistdone <= bistdone_xhdl5; + rlv <= rlv_xhdl42; + rlv_lt <= rlv_lt_xhdl43; + almost_fl_rmf <= almost_fl_rmf_xhdl3; + full_rmf <= full_rmf_xhdl24; + almost_mt_rmf <= almost_mt_rmf_xhdl4; + empty_rmf <= empty_rmf_xhdl17; + freq_lock <= freq_lock_xhdl23; + full_rx <= full_rx_xhdl25; + empty_rx <= empty_rx_xhdl18; + a1a2_k1k2_flag <= a1a2_k1k2_flag_xhdl0; + byteord_flag <= byteord_flag_xhdl7; + chnl_test_bus_out <= chnl_test_bus_out_xhdl11; + rx_pipe_soft_reset <= rx_pipe_soft_reset_xhdl48; + phystatus <= phystatus_xhdl30; + rxvalid <= rxvalid_xhdl54; + rxstatus <= rxstatus_xhdl53; + pipe_data <= pipe_data_xhdl31; + speed_change <= speed_change_xhdl59; + rx_div2_sync_out_pipe_up <= rx_div2_sync_out_pipe_up_xhdl47; + rx_we_out_pipe_up <= rx_we_out_pipe_up_xhdl50; + wr_enable_out_pipe_up <= wr_enable_out_pipe_up_xhdl64; + rd_enable_out_pipe_up <= rd_enable_out_pipe_up_xhdl37; + reset_pc_ptrs_out_pipe_up <= reset_pc_ptrs_out_pipe_up_xhdl40; + speed_change_out_pipe_up <= speed_change_out_pipe_up_xhdl61; + rx_div2_sync_out_pipe_down <= rx_div2_sync_out_pipe_down_xhdl46; + rx_we_out_pipe_down <= rx_we_out_pipe_down_xhdl49; + wr_enable_out_pipe_down <= wr_enable_out_pipe_down_xhdl63; + rd_enable_out_pipe_down <= rd_enable_out_pipe_down_xhdl36; + reset_pc_ptrs_out_pipe_down <= reset_pc_ptrs_out_pipe_down_xhdl39; + speed_change_out_pipe_down <= speed_change_out_pipe_down_xhdl60; + dis_pc_byte <= dis_pc_byte_xhdl15; + reset_pc_ptrs <= reset_pc_ptrs_xhdl38; + pcie_switch <= pcie_switch_xhdl29; + rxelecidle_int <= rxelecidle_int_xhdl52; + early_eios <= early_eios_xhdl16; + ltr <= ltr_xhdl28; + wa_boundary <= wa_boundary_xhdl62; + cg_comp_rd_d_out <= cg_comp_rd_d_out_xhdl9; + cg_comp_wr_out <= cg_comp_wr_out_xhdl10; + del_cond_met_out <= del_cond_met_out_xhdl14; + fifo_ovr_out <= fifo_ovr_out_xhdl21; + latency_comp_out <= latency_comp_out_xhdl27; + insert_incomplete_out <= insert_incomplete_out_xhdl26; + dec_data <= rx_data_dt(7 DOWNTO 0); + dec_ctl <= rx_ctl_dt(0); + sync_status <= sync_status_st; + signal_detect <= sigdetni; + soft_reset_int <= rxpcs_rst; + + -- S. Park 2/8/08 - New wires for new PPM Detector CRAMs + + -- RX PIPE interface clock + --assign rx_pipe_clk = rx_rd_clk; + rx_pipe_clk <= rx_wr_clk; + + -- Clock selection module + + + rxclk_ctl_1 : cycloneiv_hssi_rx_digi_rxclk_ctl + PORT MAP ( + pld_rx_clk => pld_rx_clk, + rcvd_clk_pma => rcvd_clk_pma, + rcvd_clk0_pma => rcvd_clk0_pma, + tx_pma_clk => tx_pma_clk, + refclk_pma => refclk_pma, + fref => fref, + clklow => clklow, + scan_mode => scan_mode, + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + rx_div2_sync_centrl => rx_div2_sync_in_centrl, + rx_div2_sync_quad_up => rx_div2_sync_in_quad_up, + rx_div2_sync_quad_down => rx_div2_sync_in_quad_down, + rrcvd_clk_sel => rrcvd_clk_sel, + rclk_1_sel => rclk_1_sel, + rclk_2_sel => rclk_2_sel, + rrx_rd_clk_sel => rrx_rd_clk_sel, + rxrst => rxpcs_rst, + rindv_rx => rindv_rx, + rdwidth_rx => rdwidth_rx, + rfreerun_rx => rfreerun_rx, + rauto_speed_ena => rauto_speed_ena, + rfreq_sel => rfreq_sel, + rrxpcsclkpwdn => rrxpcsclkpwdn, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + rself_sw_en_rx => rself_sw_en_rx, + fref_muxed => fref_muxed, + clklow_muxed => clklow_muxed, + rcvd_clk => rcvd_clk, + clk_1_b => clk_1_b, + clk_2_b => clk_2_b_xhdl12, + rx_wr_clk => rx_wr_clk, + rx_rd_clk => rx_rd_clk, + rx_clk => rx_clk_xhdl45, + rcvd_clk_pma_b => rcvd_clk_pma_b_xhdl34, + clk_2_b_raw => clk_2_b_raw, + rx_wr_clk_raw => rx_wr_clk_raw, + rx_rd_clk_raw => rx_rd_clk_raw, + rx_div2_sync_out => nc_new_bundle1 + ); + + -- Word alignment module + + + xhdl65 <= (rpma_doublewidth_rx & rpmadwidth_rx); + xhdl66 <= ("00" & rknumber); + xhdl67 <= ("00" & rgnumber); + xhdl68 <= ("0000" & renumber); + xhdl69 <= ("00" & rosnumber); + wordalign_1 : cycloneiv_hssi_rx_digi_wordalign + PORT MAP ( + rst => soft_reset_int, + clk => rcvd_clk, + scan_mode => scan_mode, + wa_6g_en => rwa_6g_en, + signal_detect => signal_detect, + rforce_sig_det_pcs => rforce_sig_det_pcs, + lpbk_en => rlp20ben, + pmadwidth => xhdl65, + dwidth => rdwidth_rx, + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + rauto_speed_ena => rauto_speed_ena, + rfreq_sel => rfreq_sel, + rindv_rx => rindv_rx, + pudi => pudi, + pudr => txlp20b, + rencdt_rising => rencdt_rising, + encdt => encdt, + comp_pat_porn => rcomp_pat_porn, + comp_pat => rcomp_pat, + comp_pat_size => rcomp_size, + resync_badcg_en => resync_badcg_en, + r8b10b_dec_ibm_en => r8b10b_dec_ibm_en, + autobytealign_dis => rautobtalg_dis, + bitslip => bitslip, + rlv_en => rrlv_en, + max_rlv_sel => rrundisp, + disable_rx_disp => rdis_rx_disp, + ib_invalid_code => rib_inv_cd, + rpolinv_en => rbysync_polinv_en, + rbitloc_rev_en => rbitloc_rev_en, + rbyte_rev_en => rbyte_rev_en, + polinv_en => polinv_rx, + bitloc_rev_en => bitloc_rev_en, + byte_rev_en => byte_rev_en, + sync_sm_dis => rsync_sm_dis, + prbs_en => rprbsen_rx, + encdet_prbs => encdet_prbs, + a1a2_size => a1a2_size, + knumber => xhdl66, + gnumber => xhdl67, + enumber => xhdl68, + rosnumber => xhdl69, + rosbased => rosbased, + rkchar => rkchar, + kchar => kchar, + signal_detect_rcvdclk => signal_detect_rcvdclk_dummy, + sudi => sudi, + sync_status => sync_status_st, + cg_syncpat => cg_comma_xhdl8, + rlv => rlv_xhdl42, + rlv_lt => rlv_lt_xhdl43, + a1a2_k1k2_flag => a1a2_k1k2_flag_xhdl0, + sudi_pre => sudi_pre, + testbus => word_align_testbus, + kcount => kcount, --new brought out from PIPE sync SM + rrxpcsbypass_en => rrxpcsbypass_en, + adata => adata, -- CDR control + adata_valid => adata_valid, + rst1 => rst1, + pipe_loose_sync => pcs_wrapback_in(60), + wa_boundary => wa_boundary_xhdl62 + ); + + -- De-skew FIFO module + + + dskw_fifo_1 : cycloneiv_hssi_rx_digi_dskw_fifo + PORT MAP ( + rcvd_clk => rcvd_clk, + -- 01/07/05 VC: Increased bus width from 13 to 14 + -- .sudi (sudi[12:0]), + sudi => sudi(13 DOWNTO 0), + soft_reset => soft_reset_int, + fifo_rst_rd_qd => fifo_rst_rd_qd, + fifo_rst_rd_gp => fifo_rst_rd_gp, + clk_1 => clk_1_b, + en_dskw_qd => en_dskw_qd, + en_dskw_gp => en_dskw_gp, + sel_gp_md => sel_gp_md, + rdskposdisp => rdskposdisp, + rdskchrp => rdskchrp, + align_det_sync => align_det_sync_xhdl1, + rd_align => rd_align_xhdl35, + audi => audi, + audi_pre => audi_pre + ); + + -- PRBS verifier module + + + xhdl70 <= (sudi(25 DOWNTO 16) & sudi(9 DOWNTO 0)); + prbs_ver_1 : cycloneiv_hssi_rx_digi_prbs_ver + PORT MAP ( + rcvd_clk => rcvd_clk, + soft_reset => soft_reset_int, + scan_mode => scan_mode, + rprbs_clr_rslt_rx => rprbs_clr_rslt_rx, + rprbs_en_rx => rprbsen_rx, + rpmadwidth_rx => rpmadwidth_rx, + rpma_doublewidth_rx => rpma_doublewidth_rx, + rprbs_sel => rprbs_sel, + rall_one_dect_only => rall_one_dect_only, + verify_on => prbs_verify_on, + cid_en => prbs_cid_en, + rcid_len => rcid_len_rx, + rcid_pattern => rcid_pattern_rx, + sync_status => sudi(11), + data_in => xhdl70, + prbs_done => prbs_done_xhdl32, + prbs_err => prbs_err, + encdet_prbs => encdet_prbs, + prbs_err_lt => prbs_err_lt_xhdl33 + ); + + -- Rate matching module + + + -- 01/07/05 VC: Increased bus width from 26 to 28 + -- to pass running disparity polarity bits + -- .sudi ({sudi[28:16], sudi[12:0]}), + xhdl71 <= (sudi(29 DOWNTO 16) & sudi(13 DOWNTO 0)); + comp_chnl_top_1 : cycloneiv_hssi_rx_digi_comp_chnl_top + PORT MAP ( + hard_reset => hard_reset, + soft_reset => soft_reset_int, + cmpfifourst => cmpfifourst, + rcmpfifourst => rcmpfifourst, + scan_mode => scan_mode, + clk_1 => clk_1_b, + clk_2 => clk_2_b_xhdl12, + sudi => xhdl71, + sudi_pre => sudi_pre, + audi => audi, + audi_pre => audi_pre, + align_status => align_status, + align_status_sync_0 => align_status_sync_0, + align_status_sync_2 => align_status_sync_2, + sync_status => sync_status_st, + inferred_rxvalid => inferred_rxvalid, + -- S. Park 3/21/08 - Removed below two ports + -- .disable_fifo_rd_0 (disable_fifo_rd_0), + -- .disable_fifo_wr_0 (disable_fifo_wr_0), + is_lane0 => is_lane0, + rdfifo_almost_full => almost_fl_rmf_xhdl3, + rdfifo_full => full_rmf_xhdl24, + rdfifo_almost_empty => almost_mt_rmf_xhdl4, + rdfifo_empty => empty_rmf_xhdl17, + dskwclksel => dskwclksel, + rmatchen => rmatchen, + rwa_6g_en => rwa_6g_en, + rgenericfifo => rgenericfifo, + rdenable => rdenable_rmf, + wrenable => wrenable_rmf, + fifo_rd_in_comp_0 => fifo_rd_in_comp_0, + fifo_rd_in_comp_2 => fifo_rd_in_comp_2, + rskpsetbased => rskpsetbased, + rtruebac2bac => rtruebac2bac, + rclkcmpsqmd => rclkcmpsqmd, + rclkcmpsq1p => rclkcmpsq1p, + rclkcmpsq1n => rclkcmpsq1n, + rclkcmpinsertpad => rclkcmpinsertpad, + rrx_pipe_enable => rclkcmp_pipe_en, + rdwidth_rx => rdwidth_rx, + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + rauto_speed_ena => rauto_speed_ena, + rfreq_sel => rfreq_sel, + rindv_rx => rindv_rx, + fifo_rd_out_comp => fifo_rd_out_comp_xhdl22, + -- S. Park 3/21/08 - Removed below two ports + -- .disable_fifo_rd (disable_fifo_rd), + -- .disable_fifo_wr (disable_fifo_wr), + align_status_sync => align_status_sync_xhdl2, + cudi => cudi, + rev_loop_data => rev_loop_data_enc, + comp_curr_st => comp_curr_st, + cudi_valid => cudi_valid, + fifo_cnt => comp_fifo_cnt, + rstart_threshold => rstart_threshold, + rins_threshold => rins_threshold, + rdel_threshold => rdel_threshold, + rfull_threshold => rfull_threshold, + rempty_threshold => rempty_threshold, + --Eidle Infer + skpos_det => skposdetect, + -- S. Park 3/13/08 - Added new ports for XAUI compliance + cg_comp_rd_d_ch0 => cg_comp_rd_d_ch0, + cg_comp_rd_d_ch1 => cg_comp_rd_d_ch1, + cg_comp_rd_d_ch2 => cg_comp_rd_d_ch2, + cg_comp_rd_d_ch3 => cg_comp_rd_d_ch3, + cg_comp_wr_ch0 => cg_comp_wr_ch0, + cg_comp_wr_ch1 => cg_comp_wr_ch1, + cg_comp_wr_ch2 => cg_comp_wr_ch2, + cg_comp_wr_ch3 => cg_comp_wr_ch3, + cg_comp_rd_d_out => cg_comp_rd_d_out_xhdl9, + cg_comp_wr_out => cg_comp_wr_out_xhdl10, + -- S. Park 3/21/08 - Added new ports for XAUI compliance + del_cond_met_0 => del_cond_met_0, + fifo_ovr_0 => fifo_ovr_0, + latency_comp_0 => latency_comp_0, + insert_incomplete_0 => insert_incomplete_0, + del_cond_met_out => del_cond_met_out_xhdl14, + fifo_ovr_out => fifo_ovr_out_xhdl21, + latency_comp_out => latency_comp_out_xhdl27, + insert_incomplete_out => insert_incomplete_out_xhdl26 + ); + + -- 10B-8B Decoder module + + + -- 01/07/05 VC: Increased bus width of cudi from 30 to 32 + -- to pass running disp polarity bit + -- .data_in({cudi[29:28],1'b0,cudi[27:15], + -- cudi[14:13],1'b0,cudi[12:0]}), + xhdl72 <= (cudi_valid & cudi_valid); + dec_chnl_top_1 : cycloneiv_hssi_rx_digi_dec_chnl_top + PORT MAP ( + rst => soft_reset_int, + clk_2 => clk_2_b_xhdl12, + cascaded_8b10b_en => rcascaded_8b10b_en_rx, + r8b10b_dec_ibm_en => r8b10b_dec_ibm_en, + data_in => cudi, + data_in_valid => xhdl72, + renpolinv => renpolinv_rx, + rerr_flags_sel => rerr_flags_sel, + polinv => polinv_rx, + dec_data => rx_data_dt, + disp_err_delay => disp_err_delay, + disp_val_delay => disp_val_delay, + sync_resync_delay => sync_resync_delay, + dec_data_valid => dec_data_valid_temp, + dec_ctl => rx_ctl_dt, + invalid_code_delay => invalid_code_delay, + ovr_undflow => ovr_undflow, + tenb_data => tenb_data, + rlb_data => rev_loop_data_xhdl41, + rrxpcsbypass_en => rrxpcsbypass_en + ); + high_dec_data_valid <= dec_data_valid_temp(1); + dec_data_valid_xhdl13 <= dec_data_valid_temp(0); + -- BIST Verifier module + + + selftest_ver_1 : cycloneiv_hssi_rx_digi_bist_ver + PORT MAP ( + clk_2 => rx_rd_clk, + soft_reset => soft_reset_rclk1_xhdl58, + sync_status => sync_status_st, + rbisten_rx => rbisten_rx, + rpmadwidth_rx => rpmadwidth_rx, + rpma_doublewidth_rx => rpma_doublewidth_rx, + rdwidth_rx => rdwidth_rx, + rbist_sel => rbist_sel, + rcxpat_chnl_sel => rcxpat_chnl_en, + rbist_clr_rx => rbist_clr_rx, + rxd => rxd_xhdl51, + rxc => rx_control_rc_16, + prbs_done => prbs_done_xhdl32, + prbs_err => prbs_err, + cur_state => bist_cur_state, + selftest_err => selftest_err_xhdl56, + selftest_done => selftest_done_xhdl55, + bisterr => bisterr_xhdl6, + bistdone => bistdone_xhdl5, + err_data => err_data_xhdl20, + err_ctl => err_ctl_xhdl19 + ); + + -- RX Phase compensation FIFO module + + + -- S. Park 11/29/07 - Phase FIFO bypass feature removed + -- .rrxfifo_dis (rrxfifo_dis), + xhdl73 <= (cudi_valid & cudi_valid); + xhdl74 <= (high_dec_data_valid & dec_data_valid_xhdl13); + xhdl75 <= (cudi(27) & cudi(11)); + rx_ctrl_1 : cycloneiv_hssi_rx_digi_rx_ctrl + PORT MAP ( + soft_reset => soft_reset_int, + clk_2 => clk_2_b_xhdl12, + rx_wr_clk => rx_wr_clk, + rx_rd_clk => rx_rd_clk, + scan_mode => scan_mode, + rrxfifo_dis => '0', + rindv_rx => rindv_rx, + rendec_data_sel_rx => rendec_data_sel_rx, + rwa_6g_en => rwa_6g_en, + rrxfifo_lowlatency_en => rrxfifo_lowlatency_en, + endec_rx => rendec_rx, + rinvalid_code_err_only => rinvalid_code_err_only, + rrx_pipe_enable => rrx_pipe_enable, + rpmadatawidth => rpmadwidth_rx, + rdwidth => rdwidth_rx, + rautoinsdis => rautoinsdis, + rbytorden => rbyteorden, + rbytord_2sym_en => rbytord_2sym_en, + rbytordpat => rbytordpat, + rbytordpadval => rbytordpad, + rbytordplden => rbytordplden, + bytordplden => bytordpld, + rbytord_6g_mask_en => rbytord_6g_mask_en, + rbytord_s2gx => rbytord_s2gx, + rsync_comp_size => rcomp_size, + rsync_comp_pat => rcomp_pat, + rsync_comp_porn => rcomp_pat_porn, + rsync_sm_dis => rsync_sm_dis, + rclkcmpinsertpad => rclkcmpinsertpad, + invalid_code_delay => invalid_code_delay, + sigdetni => sigdetni, + dec_data_valid_pre => xhdl73, + dec_data_valid => xhdl74, + rx_data_rs => rx_data_rs, + rx_control_rs => rx_control_rs, + rx_data_dt => rx_data_dt, + rx_control_dt => rx_ctl_dt, + tenb_data => tenb_data, + sync_resync_pre => xhdl75, + sync_resync_delay => sync_resync_delay, + disp_err_delay => disp_err_delay, + disp_val_delay => disp_val_delay, + ovr_undflow => ovr_undflow, + rrxfifo_urst_en => rphfifourstrx, + rxfifo_urst => phfifourst_rx, + rrxphfifopldctl_en => rphfifopldenrx, + pld_wr_dis => wrdisable_rx, + pld_re => rdenable_rx, + -- PIPE signals + phystatus_int => phystatus_int, + rxvalid_int => rxvalid_int, + rxstatus_int => rxstatus_int, + powerdown => powerdown, + rxd => rxd_xhdl51, + rxd_9 => rx_data_9_rc, + rxd_19 => rx_data_19_rc, + rxc => rx_control_rc_16, + running_disp => running_disp_xhdl44, + signal_detect_out => signal_detect_out_xhdl57, + rxd_lpbk => rxd_lpbk, + ph_fifo_empty => empty_rx_xhdl18, + ph_fifo_full => full_rx_xhdl25, + wr_enable_out => nc_new_bundle2, + rd_enable_out => nc_new_bundle3, + rx_we_out => rx_we_out_testbus, + bytord_valid_out => byteord_flag_xhdl7, + soft_reset_rclk1 => soft_reset_rclk1_xhdl58, + soft_reset_wclk1 => rx_pipe_soft_reset_xhdl48, + -- PIPE signals + phystatus => phystatus_xhdl30, + rxvalid => rxvalid_xhdl54, + rxstatus => rxstatus_xhdl53, + pipe_data => pipe_data_xhdl31, + wr_enable2 => wr_enable2, + wptr_bin => wptr_bin, + rd_enable2 => rd_enable2, + rptr_bin => rptr_bin, + rrxpcsbypass_en => rrxpcsbypass_en, + reset_pc_ptrs => reset_pc_ptrs_xhdl38, + reset_pc_ptrs_centrl => reset_pc_ptrs_in_centrl, + reset_pc_ptrs_quad_up => reset_pc_ptrs_in_quad_up, + reset_pc_ptrs_quad_down => reset_pc_ptrs_in_quad_down, + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + dis_pc_byte => dis_pc_byte_xhdl15, + wr_enable_centrl => wr_enable_in_centrl, + wr_enable_quad_up => wr_enable_in_quad_up, + wr_enable_quad_down => wr_enable_in_quad_down, + rd_enable_centrl => rd_enable_in_centrl, + rd_enable_quad_up => rd_enable_in_quad_up, + rd_enable_quad_down => rd_enable_in_quad_down, + rx_we_in_centrl => rx_we_in_centrl, + rx_we_in_quad_up => rx_we_in_quad_up, + rx_we_in_quad_down => rx_we_in_quad_down, + -- New MDIO for new bundling scheme and new PCIE features like autospeed + rauto_speed_ena => rauto_speed_ena, + rfreq_sel => rfreq_sel, + rphfifo_regmode_rx => rphfifo_regmode_rx, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + pcs_wrapback_in => pcs_wrapback_in, + rpcs_wrapback_en => rpcs_wrapback_en + ); + + -- PCS channel test bus + + + xhdl76 <= (bistdone_xhdl5 & bisterr_xhdl6 & bist_cur_state & prbs_verify_on & encdet_prbs & prbs_err_lt_xhdl33); + xhdl77 <= ('0' & rx_we_out_testbus & wr_enable2 & wptr_bin & rd_enable2 & rptr_bin); + xhdl78 <= ("00" & skposdetect & comp_curr_st & comp_fifo_cnt); + xhdl79 <= ('0' & freq_lock_xhdl23 & ppm_cnt); + xhdl80 <= ("00" & pma_testbus); + xhdl81 <= (ausm_cs & reset_pc_ptrs_xhdl38 & dis_pc_byte_xhdl15 & speed_change_xhdl59 & pcie_switch_xhdl29 & gen2ngen1 & rate); + xhdl82 <= ("00000" & inferred_rxvalid & ltr_xhdl28 & eidle_exit & early_eios_xhdl16 & eiosdetect_int); + xhdl83 <= (tx_rd_enable_out_pipe_up & tx_wr_enable_out_pipe_up & fifo_select_out_pipe_up & tx_div2_sync_out_pipe_up & reset_pc_ptrs_out_pipe_up_xhdl40 & speed_change_out_pipe_up_xhdl61 & rd_enable_out_pipe_up_xhdl37 & wr_enable_out_pipe_up_xhdl64 & rx_we_out_pipe_up_xhdl50 & rx_div2_sync_out_pipe_up_xhdl47); + xhdl84 <= (tx_rd_enable_out_pipe_down & tx_wr_enable_out_pipe_down & fifo_select_out_pipe_down & tx_div2_sync_out_pipe_down & reset_pc_ptrs_out_pipe_down_xhdl39 & speed_change_out_pipe_down_xhdl60 & rd_enable_out_pipe_down_xhdl36 & wr_enable_out_pipe_down_xhdl63 & rx_we_out_pipe_down_xhdl49 & rx_div2_sync_out_pipe_down_xhdl46); + pcs_channel_testbus_1 : cycloneiv_hssi_rx_digi_pcs_channel_testbus + PORT MAP ( + test_bus_in0 => xhdl76, + test_bus_in1 => word_align_testbus, + test_bus_in2 => encoder_testbus, + test_bus_in3 => tx_ctrl_testbus, + test_bus_in4 => xhdl77, + test_bus_in5 => xhdl78, + test_bus_in6 => xhdl79, + test_bus_in7 => xhdl80, + test_bus_in10 => xhdl81, + test_bus_in11 => xhdl82, + test_bus_in13 => xhdl83, + test_bus_in14 => xhdl84, + rtest_bus_sel => rtest_bus_sel, + chnl_test_bus_out => chnl_test_bus_out_xhdl11 + ); + + -- Frequency detector module + + + freq_det_1 : cycloneiv_hssi_rx_digi_freqdet + PORT MAP ( + scan_mode => scan_mode, + ppmsel => rppmsel, + fref => fref_muxed, + fvcobyn => clklow_muxed, + pd => '0', + rforcehigh => rforce1_freqdet, + rforcelow => rforce0_freqdet, + hard_reset => rxpma_rst, + ppm_cnt_reset => rppm_cnt_reset, + gen2ngen1_indv => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + rindv_rx => rindv_rx, + rauto_speed_ena => rauto_speed_ena, + rppm_gen1_2xcnt_en => rppm_gen1_2xcnt_en, + eidle_exit => eidle_exit, + rppm_post_eidle_del => rppm_post_eidle_del, + freq_lock => freq_lock_xhdl23, + ppm_cnt_latch => ppm_cnt + ); + + -- Auto negotiation module + + + auto_speed_neg_1 : cycloneiv_hssi_rx_digi_auto_speed_neg + PORT MAP ( + refclk => clk_2_b_xhdl12, + rxpcs_rst_int => soft_reset_int, + rauto_speed_ena => rauto_speed_ena, + singleorbundle => rindv_rx, + config_sel_centrl => config_sel_centrl, + config_sel_quad_up => config_sel_quad_up, + config_sel_quad_down => config_sel_quad_down, + rindv_rx => rindv_rx, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + rphfifo_regmode_rx => rphfifo_regmode_rx, + rate => rate, + cs => ausm_cs, + gen2ngen1 => gen2ngen1, --from PMA + speed_change => speed_change_xhdl59, --to RX PIPE, phystatus gen. + rpma_done_count => rpma_done_count, + rauto_deassert_pc_rst_cnt => rauto_deassert_pc_rst_cnt, + rauto_pc_en_cnt => rauto_pc_en_cnt, + rwait_for_phfifo_cnt => rwait_for_phfifo_cnt, + config_sel => config_sel_nc, + pcie_switch => pcie_switch_xhdl29, + dis_pc_byte => dis_pc_byte_xhdl15, + reset_pc_ptrs => reset_pc_ptrs_xhdl38 + ); + + + + electrical_idle_inference_module_1 : cycloneiv_hssi_rx_digi_eii_module + PORT MAP ( + rcvd_clk => rcvd_clk, + rxpcsrst => rst1, -- synchronized reset in rcvd_clk domain from wordalign block + reidleinferenable => reidleinferenable, + reidle_com_detect => reidle_com_detect, + rindv_rx => rindv_rx, + riei_eios_priority_dis => riei_eios_priority_dis, + rgen1_sigdet_ena => rgen1_sigdet_ena, + eidleinfersel => eidleinfersel, -- + skposdetect => skposdetect, + syncstatus => sync_status_st, + sudi => sudi(15 DOWNTO 0), + kflag => kchar, + kcount => kcount(1 DOWNTO 0), --new brought out from PIPE sync SM + eiosdetect_int => eiosdetect_int, --CDR control + inferred_rxvalid => inferred_rxvalid, + signaldetect => sigdetni, + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + pipe_loopbk => pipe_loopbk, + rwait_count => rwait_count, + rxelecidle_int => rxelecidle_int_xhdl52 + ); + + + + cdr_ctrl_1 : cycloneiv_hssi_rx_digi_cdr_ctrl + PORT MAP ( + + -- General signals + rcvd_clk => rcvd_clk, + rxpcs_reset_int => rst1, -- synchronized reset in rcvd_clk domain from wordalign block + + -- CRAM + rcdr_ctrl_en => rcdr_ctrl_en, + rcid_en => rcid_en, + rrxvalid_mask => rrxvalid_mask, + + rwait_count => rwait_count, + rmask_count => rmask_count(9 DOWNTO 0), + + rindv_rx => rindv_rx, + + -- PLD interface + pld_ltr => pld_ltr, + pipe_loopbk => pipe_loopbk, + + -- Word aligner + adata => adata, + adata_valid => adata_valid, + inferred_rxvalid => inferred_rxvalid, + + -- EIdle Inference + eiosdetect_int => eiosdetect_int, + + -- Auto Speed + gen2ngen1 => gen2ngen1, + gen2ngen1_bundle => gen2ngen1_bundle, + + -- PPM detector + eidle_exit => eidle_exit, + + -- PMA + sigdet => sigdetni, + early_eios => early_eios_xhdl16, + ltr => ltr_xhdl28 + ); + + + + iqp_out_up : cycloneiv_hssi_rx_digi_iq_pipe_rx + PORT MAP ( + clk_2_b_raw => clk_2_b_raw, + rx_wr_clk_raw => rx_wr_clk_raw, + rx_rd_clk_raw => rx_rd_clk_raw, + rxrst => rxpcs_rst, + soft_reset_rclk1 => soft_reset_rclk1_xhdl58, + soft_reset_wclk1 => rx_pipe_soft_reset_xhdl48, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + rpipeline_bypass_rx => rpipeline_bypass_rx, + rfreerun_rx => rfreerun_rx, + + rx_div2_sync_in_centrl => rx_div2_sync_in_centrl, + rx_div2_sync_in_pipe_quad_up => '0', + rx_div2_sync_in_pipe_quad_down => rx_div2_sync_in_pipe_quad_down, + reset_pc_ptrs_in_centrl => reset_pc_ptrs_in_centrl, + reset_pc_ptrs_in_pipe_quad_up => '0', + reset_pc_ptrs_in_pipe_quad_down => reset_pc_ptrs_in_pipe_quad_down, + wr_enable_in_centrl => wr_enable_in_centrl, + wr_enable_in_pipe_quad_up => '0', + wr_enable_in_pipe_quad_down => wr_enable_in_pipe_quad_down, + rd_enable_in_centrl => rd_enable_in_centrl, + rd_enable_in_pipe_quad_up => '0', + rd_enable_in_pipe_quad_down => rd_enable_in_pipe_quad_down, + rx_we_in_centrl => rx_we_in_centrl, + rx_we_in_pipe_quad_up => '0', + rx_we_in_pipe_quad_down => rx_we_in_pipe_quad_down, + speed_change_in_centrl => speed_change_in_centrl, + speed_change_in_pipe_quad_up => '0', + speed_change_in_pipe_quad_down => speed_change_in_pipe_quad_down, + + rx_div2_sync_out_pipe => rx_div2_sync_out_pipe_up_xhdl47, + rx_we_out_pipe => rx_we_out_pipe_up_xhdl50, + wr_enable_out_pipe => wr_enable_out_pipe_up_xhdl64, + rd_enable_out_pipe => rd_enable_out_pipe_up_xhdl37, + reset_pc_ptrs_out_pipe => reset_pc_ptrs_out_pipe_up_xhdl40, + speed_change_out_pipe => speed_change_out_pipe_up_xhdl61 + ); + + + + iqp_out_down : cycloneiv_hssi_rx_digi_iq_pipe_rx + PORT MAP ( + clk_2_b_raw => clk_2_b_raw, + rx_wr_clk_raw => rx_wr_clk_raw, + rx_rd_clk_raw => rx_rd_clk_raw, + rxrst => rxpcs_rst, + soft_reset_rclk1 => soft_reset_rclk1_xhdl58, + soft_reset_wclk1 => rx_pipe_soft_reset_xhdl48, + rmaster_rx => rmaster_rx, + rmaster_up_rx => rmaster_up_rx, + rpipeline_bypass_rx => rpipeline_bypass_rx, + rfreerun_rx => rfreerun_rx, + + rx_div2_sync_in_centrl => rx_div2_sync_in_centrl, + rx_div2_sync_in_pipe_quad_up => rx_div2_sync_in_pipe_quad_up, + rx_div2_sync_in_pipe_quad_down => '0', + reset_pc_ptrs_in_centrl => reset_pc_ptrs_in_centrl, + reset_pc_ptrs_in_pipe_quad_up => reset_pc_ptrs_in_pipe_quad_up, + reset_pc_ptrs_in_pipe_quad_down => '0', + wr_enable_in_centrl => wr_enable_in_centrl, + wr_enable_in_pipe_quad_up => wr_enable_in_pipe_quad_up, + wr_enable_in_pipe_quad_down => '0', + rd_enable_in_centrl => rd_enable_in_centrl, + rd_enable_in_pipe_quad_up => rd_enable_in_pipe_quad_up, + rd_enable_in_pipe_quad_down => '0', + rx_we_in_centrl => rx_we_in_centrl, + rx_we_in_pipe_quad_up => rx_we_in_pipe_quad_up, + rx_we_in_pipe_quad_down => '0', + speed_change_in_centrl => speed_change_in_centrl, + speed_change_in_pipe_quad_up => speed_change_in_pipe_quad_up, + speed_change_in_pipe_quad_down => '0', + + rx_div2_sync_out_pipe => rx_div2_sync_out_pipe_down_xhdl46, + rx_we_out_pipe => rx_we_out_pipe_down_xhdl49, + wr_enable_out_pipe => wr_enable_out_pipe_down_xhdl63, + rd_enable_out_pipe => rd_enable_out_pipe_down_xhdl36, + reset_pc_ptrs_out_pipe => reset_pc_ptrs_out_pipe_down_xhdl39, + speed_change_out_pipe => speed_change_out_pipe_down_xhdl60 + ); + +END trans; + + + +-- digi_rx--/////////////////////////////////////////////////////////////////////////////// +-- hssi_module: receiver ******************************************************// +--/////////////////////////////////////////////////////////////////////////////// + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +ENTITY cycloneiv_hssi_rx_pcs IS + GENERIC ( + + -- generic control parameters -- + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + -- tipd :interconnect path delays -- + tipd_a1a2size : VitalDelayType01 := DefpropDelay01; + tipd_alignstatus : VitalDelayType01 := DefpropDelay01; + tipd_alignstatussync : VitalDelayType01 := DefpropDelay01; + tipd_bitslip : VitalDelayType01 := DefpropDelay01; + tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01; + tipd_coreclk : VitalDelayType01 := DefpropDelay01; + tipd_datain : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_digitalreset : VitalDelayType01 := DefpropDelay01; + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_dprioin : VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_elecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_enabledeskew : VitalDelayType01 := DefpropDelay01; + tipd_enabyteord : VitalDelayType01 := DefpropDelay01; + tipd_enapatternalign : VitalDelayType01 := DefpropDelay01; + tipd_fifordin : VitalDelayType01 := DefpropDelay01; + tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01; + tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01; + tipd_hipelecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hippowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_invpol : VitalDelayType01 := DefpropDelay01; + tipd_localrefclk : VitalDelayType01 := DefpropDelay01; + tipd_masterclk : VitalDelayType01 := DefpropDelay01; + tipd_parallelfdbk : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifordenable : VitalDelayType01 := DefpropDelay01; + tipd_phfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01; + tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01; + tipd_pipepowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pipepowerstate : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_powerdn : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_prbscidenable : VitalDelayType01 := DefpropDelay01; + tipd_quadreset : VitalDelayType01 := DefpropDelay01; + tipd_recoveredclk : VitalDelayType01 := DefpropDelay01; + tipd_refclk : VitalDelayType01 := DefpropDelay01; + tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01; + tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01; + tipd_rmfifordena : VitalDelayType01 := DefpropDelay01; + tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01; + tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01; + tipd_rxfound : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_signaldetected : VitalDelayType01 := DefpropDelay01; + tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01; + tipd_xgmdatain : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); + + -- TSU/TH section + tsetup_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + + -- TCO section + tpd_coreclk_a1a2sizeout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_byteorderalignstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_ctrldetect_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_dataout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_dataoutfull_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_disperr_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_errdetect_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_patterndetect_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_rmfifodatadeleted_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_rmfifodatainserted_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_runningdisp_posedge : VitalDelayType01 := DefPropDelay01; + + -- keep for the sake of no code change --------------------------------------- + tpd_coreclk_syncstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tpd_coreclk_pipestatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_pipephydonestatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_pipedatavalid_posedge : VitalDelayType01 := DefPropDelay01; + + --//////////////////////////////////////////////////////////////////////////// + --//////////////////////////////////////////////////////////////////////////// + + lpm_type : STRING := "cycloneiv_hssi_rx_pcs"; + auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0; + auto_spd_phystatus_notify_count : INTEGER := 0; + align_ordered_set_based : STRING := "false"; + align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length; + align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>; + align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- ; + allow_align_polarity_inversion : STRING := "false"; + allow_pipe_polarity_inversion : STRING := "false"; + bit_slip_enable : STRING := "false"; + byte_order_back_compat_enable : STRING := "false"; + byte_order_invalid_code_or_run_disp_error : STRING := "false"; + byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode + byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>; + byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>; + byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165 + cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0; + cdrctrl_cid_mode_enable : STRING := "false"; + cdrctrl_enable : STRING := "false"; + cdrctrl_mask_cycle : INTEGER := 0; + cdrctrl_min_lock_to_ref_cycle : INTEGER := 0; + cdrctrl_rxvalid_mask : STRING := "false"; + channel_bonding : STRING := "none"; -- ; + channel_number : INTEGER := 0; -- ; + channel_width : INTEGER := 10; -- ; + clk1_mux_select : STRING := "recvd_clk"; -- ; + clk2_mux_select : STRING := "recvd_clk"; -- ; + clk_pd_enable : STRING := "false"; --ww47_cram_p1 + core_clock_0ppm : STRING := "false"; + datapath_low_latency_mode : STRING := "false"; + datapath_protocol : STRING := "basic"; -- replaced by protocol_hint + dec_8b_10b_compatibility_mode : STRING := "true"; + dec_8b_10b_mode : STRING := "none"; -- ; + deskew_pattern : STRING := "1100111100"; -- K28.3 + disable_auto_idle_insertion : STRING := "false"; + disable_running_disp_in_word_align : STRING := "false"; + disallow_kchar_after_pattern_ordered_set : STRING := "false"; + elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false"; + elec_idle_gen1_sigdet_enable : STRING := "false"; + elec_idle_infer_enable : STRING := "false"; + elec_idle_num_com_detect : INTEGER := 0; + enable_bit_reversal : STRING := "false"; + enable_self_test_mode : STRING := "false"; + error_from_wa_or_8b_10b_select : STRING := "false"; + force_signal_detect_dig : STRING := "false"; + hip_enable : STRING := "false"; + infiniband_invalid_code : INTEGER := 0; -- ; + insert_pad_on_underflow : STRING := "false"; + logical_channel_address : INTEGER := 0; + num_align_code_groups_in_ordered_set : INTEGER := 1; -- ; + num_align_cons_good_data : INTEGER := 3; -- wordalign; + num_align_cons_pat : INTEGER := 4; -- ; + num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num + ph_fifo_low_latency_enable : STRING := "false"; + ph_fifo_reg_mode : STRING := "false"; + ph_fifo_reset_enable : STRING := "false"; + ph_fifo_user_ctrl_enable : STRING := "false"; + phystatus_delay : INTEGER := 0; + phystatus_reset_toggle : STRING := "false"; + pipe_auto_speed_nego_enable : STRING := "false"; + prbs_all_one_detect : STRING := "false"; + prbs_cid_pattern : STRING := "false"; + prbs_cid_pattern_length : INTEGER := 0; + protocol_hint : STRING := "basic"; + rate_match_back_to_back : STRING := "false"; + rate_match_delete_threshold : INTEGER := 13; + rate_match_empty_threshold : INTEGER := 5; + rate_match_fifo_mode : STRING := "false"; -- in s2gx, bool in s4gx; + rate_match_full_threshold : INTEGER := 20; + rate_match_insert_threshold : INTEGER := 11; + rate_match_ordered_set_based : STRING := "false"; -- ; + rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>; + rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>; + rate_match_pattern_size : INTEGER := 10; -- ; + rate_match_pipe_enable : STRING := "false"; + rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom + rate_match_skip_set_based : STRING := "false"; + rate_match_start_threshold : INTEGER := 7; + rd_clk_mux_select : STRING := "int clock"; -- ; + recovered_clk_mux_select : STRING := "recovered clock"; -- ; + reset_clock_output_during_digital_reset : STRING := "false"; + run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>; + run_length_enable : STRING := "false"; + rx_detect_bypass : STRING := "false"; + rx_phfifo_wait_cnt : INTEGER := 32; + rxstatus_error_report_mode : INTEGER := 0; + self_test_mode : STRING := "incremental"; -- ; + test_bus_sel : INTEGER := 0; + use_alignment_state_machine : STRING := "false"; + use_deskew_fifo : STRING := "false"; + use_double_data_mode : STRING := "false"; + use_parallel_loopback : STRING := "false"; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000" + ); + PORT ( + a1a2size : IN STD_LOGIC := '0'; + alignstatus : IN STD_LOGIC := '0'; + alignstatussync : IN STD_LOGIC := '0'; + bitslip : IN STD_LOGIC := '0'; + cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr + coreclk : IN STD_LOGIC := '0'; + datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); --NEW: updated width + digitalreset : IN STD_LOGIC := '0'; + elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + enabledeskew : IN STD_LOGIC := '0'; + enabyteord : IN STD_LOGIC := '0'; + enapatternalign : IN STD_LOGIC := '0'; + fifordin : IN STD_LOGIC := '0'; + fiforesetrd : IN STD_LOGIC := '0'; + grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity + hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch + hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch + invpol : IN STD_LOGIC := '0'; + localrefclk : IN STD_LOGIC := '0'; + masterclk : IN STD_LOGIC := '0'; + parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); + phfifordenable : IN STD_LOGIC := '1'; + phfiforeset : IN STD_LOGIC := '0'; + phfifowrdisable : IN STD_LOGIC := '0'; + phfifox4bytesel : IN STD_LOGIC := '0'; + phfifox4rdenable : IN STD_LOGIC := '0'; + phfifox4wrclk : IN STD_LOGIC := '0'; + phfifox4wrenable : IN STD_LOGIC := '0'; + pipe8b10binvpolarity : IN STD_LOGIC := '0'; + pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0'; + pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en + quadreset : IN STD_LOGIC := '0'; + recoveredclk : IN STD_LOGIC := '0'; + refclk : IN STD_LOGIC := '0'; + revbitorderwa : IN STD_LOGIC := '0'; + rmfifordena : IN STD_LOGIC := '0'; + rmfiforeset : IN STD_LOGIC := '0'; + rmfifowrena : IN STD_LOGIC := '0'; + rxdetectvalid : IN STD_LOGIC := '0'; + rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + signaldetected : IN STD_LOGIC := '0'; + xauidelcondmet : IN STD_LOGIC := '0'; + xauififoovr : IN STD_LOGIC := '0'; + xauiinsertincomplete : IN STD_LOGIC := '0'; + xauilatencycomp : IN STD_LOGIC := '0'; + xgmctrlin : IN STD_LOGIC := '0'; + xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins --- + wareset : IN STD_LOGIC := '0'; + revbyteorderwa : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0'); + + a1a2sizeout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + a1detect : OUT STD_LOGIC; + a2detect : OUT STD_LOGIC; + adetectdeskew : OUT STD_LOGIC; + alignstatussyncout : OUT STD_LOGIC; + bistdone : OUT STD_LOGIC; + bisterr : OUT STD_LOGIC; + bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary + byteorderalignstatus : OUT STD_LOGIC; + cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD? + cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR. + clkout : OUT STD_LOGIC; + coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU + ctrldetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + dataoutfull : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- new in 6.1 + disperr : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + errdetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + fifordout : OUT STD_LOGIC; + hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0) + hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid + hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle + hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus + hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0) + k1detect : OUT STD_LOGIC; + k2detect : OUT STD_LOGIC; + patterndetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + phfifooverflow : OUT STD_LOGIC; + phfifordenableout : OUT STD_LOGIC; + phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU + phfifounderflow : OUT STD_LOGIC; + phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU + pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pipedatavalid : OUT STD_LOGIC; + pipeelecidle : OUT STD_LOGIC; + pipephydonestatus : OUT STD_LOGIC; + pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rdalign : OUT STD_LOGIC; + revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + rlv : OUT STD_LOGIC; + rmfifodatadeleted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rmfifodatainserted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rmfifoempty : OUT STD_LOGIC; + rmfifofull : OUT STD_LOGIC; + runningdisp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + signaldetect : OUT STD_LOGIC; + syncstatus : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + syncstatusdeskew : OUT STD_LOGIC; + xauidelcondmetout : OUT STD_LOGIC; + xauififoovrout : OUT STD_LOGIC; + xauiinsertincompleteout : OUT STD_LOGIC; + xauilatencycompout : OUT STD_LOGIC; + xgmctrldet : OUT STD_LOGIC; + xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + xgmdatavalid : OUT STD_LOGIC; + xgmrunningdisp : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0); + pipestatetransdoneout : OUT STD_LOGIC + ); +END cycloneiv_hssi_rx_pcs; + +ARCHITECTURE trans OF cycloneiv_hssi_rx_pcs IS + + signal xgmctrlin_ipd :STD_LOGIC; + signal pipepowerdown_ipd :STD_LOGIC_VECTOR(1 DOWNTO 0); + signal parallelfdbk_ipd :STD_LOGIC_VECTOR(19 DOWNTO 0); + signal masterclk_ipd :STD_LOGIC; + signal pipepowerstate_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal alignstatussync_ipd :STD_LOGIC; + signal powerdn_ipd :STD_LOGIC_VECTOR(1 DOWNTO 0); + signal refclk_ipd :STD_LOGIC; + signal phfifox4bytesel_ipd :STD_LOGIC; + signal bitslip_ipd :STD_LOGIC; + signal phfiforeset_ipd :STD_LOGIC; + signal dprioin_ipd :STD_LOGIC_VECTOR(399 DOWNTO 0); + signal datain_ipd :STD_LOGIC_VECTOR(19 DOWNTO 0); + signal enabledeskew_ipd :STD_LOGIC; + signal hippowerdown_ipd :STD_LOGIC_VECTOR(1 DOWNTO 0); + signal revbyteorderwa_ipd :STD_LOGIC; + signal phfifox4wrenable_ipd :STD_LOGIC; + signal dpriodisable_ipd :STD_LOGIC; + signal enabyteord_ipd :STD_LOGIC; + signal invpol_ipd :STD_LOGIC; + signal revbitorderwa_ipd :STD_LOGIC; + signal localrefclk_ipd :STD_LOGIC; + signal enapatternalign_ipd :STD_LOGIC; + signal phfifowrdisable_ipd :STD_LOGIC; + signal signaldetected_ipd :STD_LOGIC; + signal alignstatus_ipd :STD_LOGIC; + signal rxdetectvalid_ipd :STD_LOGIC; + signal quadreset_ipd :STD_LOGIC; + signal recoveredclk_ipd :STD_LOGIC; + signal phfifordenable_ipd :STD_LOGIC; + signal phfifox4wrclk_ipd :STD_LOGIC; + signal rmfifowrena_ipd :STD_LOGIC; + signal a1a2size_ipd :STD_LOGIC; + signal elecidleinfersel_ipd :STD_LOGIC_VECTOR(2 DOWNTO 0); + signal hip8b10binvpolarity_ipd :STD_LOGIC; + signal rmfiforeset_ipd :STD_LOGIC; + signal rmfifordena_ipd :STD_LOGIC; + signal hipelecidleinfersel_ipd :STD_LOGIC_VECTOR(2 DOWNTO 0); + signal phfifox4rdenable_ipd :STD_LOGIC; + signal pipe8b10binvpolarity_ipd :STD_LOGIC; + signal fifordin_ipd :STD_LOGIC; + signal prbscidenable_ipd :STD_LOGIC; + signal digitalreset_ipd :STD_LOGIC; + signal rxfound_ipd :STD_LOGIC_VECTOR(1 DOWNTO 0); + signal cdrctrllocktorefcl_ipd :STD_LOGIC; + signal fiforesetrd_ipd :STD_LOGIC; + signal xgmdatain_ipd :STD_LOGIC_VECTOR(7 DOWNTO 0); +-- -------------------------------------------------------------------------- +-- parameters in TgX but not in cycloneiv ------------------------------------ +-- --- make them local with fixed value so maximally reuse TgX code - +-- to not modifying internal codes - +-- --- total = 57 5/7/09 - +-- -------------------------------------------------------------------------- + CONSTANT auto_spd_self_switch_enable : STRING := "false"; + CONSTANT byte_order_double_data_mode_mask_enable : STRING := "false"; + CONSTANT dec_8b_10b_polarity_inv_enable : STRING := "false"; + CONSTANT elec_idle_k_detect : STRING := "false"; + CONSTANT enable_deep_align : STRING := "false"; + CONSTANT enable_deep_align_byte_swap : STRING := "false"; + CONSTANT enable_true_complement_match_in_word_align : STRING := "true"; + CONSTANT iqp_bypass : STRING := "false"; + CONSTANT iqp_ph_fifo_xn_select : INTEGER := 9999; + CONSTANT ph_fifo_disable : STRING := "false"; + CONSTANT ph_fifo_xn_mapping0 : STRING := "none"; --ww47_cram_p1 + CONSTANT ph_fifo_xn_mapping1 : STRING := "none"; --ww47_cram_p1 + CONSTANT ph_fifo_xn_mapping2 : STRING := "none"; --ww47_cram_p1 + CONSTANT ph_fifo_xn_select : INTEGER := 9999; + CONSTANT pipe_freq_scale_mode : STRING := "Data width"; + CONSTANT pipe_hip_enable : STRING := "false"; --NEW_PARAM todo: remove + CONSTANT pma_done_count : INTEGER := 53392; --ww47_cram_p1 + CONSTANT rate_match_almost_empty_threshold : INTEGER := 11; -- ; + CONSTANT rate_match_almost_full_threshold : INTEGER := 13; -- ; + CONSTANT use_deserializer_double_data_mode : STRING := "false"; + CONSTANT use_rising_edge_triggered_pattern_align : STRING := "false"; -- ; //83 para: new=23 rem=40 + CONSTANT enable_phfifo_bypass : STRING := "false"; + + +-- -------------------------------------------------------------------------- +-- Input ports in TgX but not in cycloneiv ----------------------------------- +-- --- make them wire with fixed value so maximally reuse TgX code - +-- to not modifying internal codes - +-- --- total = 60 5/7/09 - +-- -------------------------------------------------------------------------- + -- SIGNAL alignstatussync : STD_LOGIC := '0'; + SIGNAL autospdxnconfigsel : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- config_sel_centrl, quad_up, quad_down + SIGNAL autospdxnspdchg : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- From CMU.spped-change_centrl, rx3(up), rx0(down) + SIGNAL disablefifordin : STD_LOGIC := '0'; + SIGNAL disablefifowrin : STD_LOGIC := '0'; + SIGNAL hiprateswitch : STD_LOGIC := '0'; -- hip_rate + SIGNAL iqpautospdxnspgchg : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- speed_change_in_pipe_quad_up, down + SIGNAL iqpphfifoxnbytesel : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down + SIGNAL iqpphfifoxnptrsreset : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- reset_pc_ptrs_in_pipe_quad_up, down + SIGNAL iqpphfifoxnrdenable : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rd_enable_ptrs_in_pipe_quad_up, down + SIGNAL iqpphfifoxnwrclk : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rx_div2_sync_in_pipe_quad_up, down + SIGNAL iqpphfifoxnwrenable : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down + SIGNAL phfifox8bytesel : STD_LOGIC := '0'; + SIGNAL phfifox8rdenable : STD_LOGIC := '0'; + SIGNAL phfifox8wrclk : STD_LOGIC := '0'; + SIGNAL phfifox8wrenable : STD_LOGIC := '0'; + SIGNAL phfifoxnbytesel : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rx_we_in_centrl, quad_up, quad_down + SIGNAL phfifoxnptrsreset : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to both RX & TX. + SIGNAL phfifoxnrdenable : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rd_enable_in_centrl, quad_up, quad_down + SIGNAL phfifoxnwrclk : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to RX. + SIGNAL phfifoxnwrenable : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- wr_enable_in_centrl, quad_up, quad_down + SIGNAL ppmdetectdividedclk : STD_LOGIC := '0'; + SIGNAL ppmdetectrefclk : STD_LOGIC := '0'; + SIGNAL rateswitch : STD_LOGIC := '0'; + SIGNAL rateswitchisdone : STD_LOGIC := '0'; + SIGNAL rateswitchxndone : STD_LOGIC := '0'; + SIGNAL rxelecidlerateswitch : STD_LOGIC := '0'; + +-- -------------------------------------------------------------------------- +-- Output ports in TgX but not in cycloneiv ---------------------------------- +-- --- make them wire to maximally reuse TgX code - +-- to not modifying internal codes - +-- --- total = 53 5/7/09 - +-- -------------------------------------------------------------------------- + SIGNAL autospdrateswitchout : STD_LOGIC; + SIGNAL autospdspdchgout : STD_LOGIC; --ww47_out speed_chang_out_pipe + SIGNAL digitaltestout : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL disablefifordout : STD_LOGIC; + SIGNAL disablefifowrout : STD_LOGIC; + SIGNAL iqpphfifobyteselout : STD_LOGIC; --ww47_out rx_we_out_pipe + SIGNAL iqpphfifoptrsresetout : STD_LOGIC; --ww47_out reset_pc_pters_out_pipe + SIGNAL iqpphfifordenableout : STD_LOGIC; --ww47_out rd_enable_pipe_out + SIGNAL iqpphfifowrclkout : STD_LOGIC; --ww47_out rx_div2_sync_out_pipe + SIGNAL iqpphfifowrenableout : STD_LOGIC; --ww47_out wr_enable_out_pipe + SIGNAL phfifobyteselout : STD_LOGIC; + SIGNAL phfifobyteserdisableout : STD_LOGIC; --ww47_out From Auto Speed Neg to TX + SIGNAL phfifoptrsresetout : STD_LOGIC; --ww47_out From Auto Speed Neg to TX + SIGNAL phfifowrclkout : STD_LOGIC; + SIGNAL phfifowrenableout : STD_LOGIC; + SIGNAL rateswitchout : STD_LOGIC; + SIGNAL rmfifoalmostempty : STD_LOGIC; + SIGNAL rmfifoalmostfull : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- input timing signal removed + ----------------------------------------------------------------------------- + signal coreclk_ipd :STD_LOGIC; -- kept for TCO + + + COMPONENT cycloneiv_hssi_rx_digi + PORT ( + hard_reset : IN STD_LOGIC; + rxpcs_rst : IN STD_LOGIC; + rxpma_rst : IN STD_LOGIC; + cmpfifourst : IN STD_LOGIC; + phfifourst_rx : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + encdt : IN STD_LOGIC; + a1a2_size : IN STD_LOGIC; + bitslip : IN STD_LOGIC; + rdenable_rmf : IN STD_LOGIC; + wrenable_rmf : IN STD_LOGIC; + pld_rx_clk : IN STD_LOGIC; + soft_reset_rclk1 : OUT STD_LOGIC; + polinv_rx : IN STD_LOGIC; + bitloc_rev_en : IN STD_LOGIC; + byte_rev_en : IN STD_LOGIC; + rcvd_clk_pma : IN STD_LOGIC; + pudi : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + sigdetni : IN STD_LOGIC; + fifo_rst_rd_qd : IN STD_LOGIC; + fifo_rst_rd_gp : IN STD_LOGIC; + en_dskw_qd : IN STD_LOGIC; + en_dskw_gp : IN STD_LOGIC; + is_lane0 : IN STD_LOGIC; + align_status : IN STD_LOGIC; + align_status_sync_0 : IN STD_LOGIC; + align_status_sync_2 : IN STD_LOGIC; + rx_data_rs : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_control_rs : IN STD_LOGIC; + rcvd_clk0_pma : IN STD_LOGIC; + fifo_rd_in_comp_0 : IN STD_LOGIC; + fifo_rd_in_comp_2 : IN STD_LOGIC; + txlp20b : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + refclk_pma : IN STD_LOGIC; + tx_pma_clk : IN STD_LOGIC; + fref : IN STD_LOGIC; + clklow : IN STD_LOGIC; + bytordpld : IN STD_LOGIC; + wrdisable_rx : IN STD_LOGIC; + rdenable_rx : IN STD_LOGIC; + pma_testbus : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + encoder_testbus : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + tx_ctrl_testbus : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + phystatus_int : IN STD_LOGIC; + rxvalid_int : IN STD_LOGIC; + rxstatus_int : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + fifo_rd_out_comp : OUT STD_LOGIC; + rxd : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rev_loop_data : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + rx_clk : OUT STD_LOGIC; + bisterr : OUT STD_LOGIC; + cg_comma : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + clk_2_b : OUT STD_LOGIC; + rcvd_clk_pma_b : OUT STD_LOGIC; + sync_status : OUT STD_LOGIC; + align_status_sync : OUT STD_LOGIC; + dec_data_valid : OUT STD_LOGIC; + dec_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dec_ctl : OUT STD_LOGIC; + running_disp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + selftest_done : OUT STD_LOGIC; + selftest_err : OUT STD_LOGIC; + err_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + err_ctl : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + prbs_done : OUT STD_LOGIC; + prbs_err_lt : OUT STD_LOGIC; + signal_detect_out : OUT STD_LOGIC; + align_det_sync : OUT STD_LOGIC; + rd_align : OUT STD_LOGIC; + bistdone : OUT STD_LOGIC; + rlv : OUT STD_LOGIC; + rlv_lt : OUT STD_LOGIC; + almost_fl_rmf : OUT STD_LOGIC; + full_rmf : OUT STD_LOGIC; + almost_mt_rmf : OUT STD_LOGIC; + empty_rmf : OUT STD_LOGIC; + freq_lock : OUT STD_LOGIC; + full_rx : OUT STD_LOGIC; + empty_rx : OUT STD_LOGIC; + a1a2_k1k2_flag : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + byteord_flag : OUT STD_LOGIC; + rx_pipe_clk : OUT STD_LOGIC; + chnl_test_bus_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + rx_pipe_soft_reset : OUT STD_LOGIC; + phystatus : OUT STD_LOGIC; + rxvalid : OUT STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pipe_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rskpsetbased : IN STD_LOGIC; + rtruebac2bac : IN STD_LOGIC; + rcmpfifourst : IN STD_LOGIC; + rphfifourstrx : IN STD_LOGIC; + rcomp_size : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rcomp_pat : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + rrundisp : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + rib_inv_cd : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrlv_en : IN STD_LOGIC; + rsync_sm_dis : IN STD_LOGIC; + rautobtalg_dis : IN STD_LOGIC; + rdis_rx_disp : IN STD_LOGIC; + rmatchen : IN STD_LOGIC; + rgenericfifo : IN STD_LOGIC; + rendec_rx : IN STD_LOGIC; + rdwidth_rx : IN STD_LOGIC; + rlp20ben : IN STD_LOGIC; + rrxfifo_dis : IN STD_LOGIC; + rpmadwidth_rx : IN STD_LOGIC; + rpma_doublewidth_rx : IN STD_LOGIC; + renumber : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + rknumber : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + renpolinv_rx : IN STD_LOGIC; + rgnumber : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rclkcmpsqmd : IN STD_LOGIC; + rclkcmpsq1p : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + rclkcmpsq1n : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + rclkcmp_pipe_en : IN STD_LOGIC; + rosnumber : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rosbased : IN STD_LOGIC; + rkchar : IN STD_LOGIC; + rcascaded_8b10b_en_rx : IN STD_LOGIC; + resync_badcg_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rencdt_rising : IN STD_LOGIC; + rcomp_pat_porn : IN STD_LOGIC; + rprbsen_rx : IN STD_LOGIC; + rprbs_clr_rslt_rx : IN STD_LOGIC; + rbisten_rx : IN STD_LOGIC; + rbist_clr_rx : IN STD_LOGIC; + rwa_6g_en : IN STD_LOGIC; + rbytord_2sym_en : IN STD_LOGIC; + rbysync_polinv_en : IN STD_LOGIC; + rbytord_6g_mask_en : IN STD_LOGIC; + rbytord_s2gx : IN STD_LOGIC; + rbitloc_rev_en : IN STD_LOGIC; + rbyte_rev_en : IN STD_LOGIC; + rbyteorden : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rbytordplden : IN STD_LOGIC; + rphfifopldenrx : IN STD_LOGIC; + rautoinsdis : IN STD_LOGIC; + rppmsel : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + rforce0_freqdet : IN STD_LOGIC; + rforce1_freqdet : IN STD_LOGIC; + rbytordpat : IN STD_LOGIC_VECTOR(19 DOWNTO 0); + rbytordpad : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rforce_sig_det_pcs : IN STD_LOGIC; + rfreerun_rx : IN STD_LOGIC; + rrcvd_clk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_1_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_2_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrx_rd_clk_sel : IN STD_LOGIC; + rall_one_dect_only : IN STD_LOGIC; + rtest_bus_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + r8b10b_dec_ibm_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrxfifo_lowlatency_en : IN STD_LOGIC; + rppm_cnt_reset : IN STD_LOGIC; + sel_gp_md : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + dskwclksel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rdskposdisp : IN STD_LOGIC; + rdskchrp : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rendec_data_sel_rx : IN STD_LOGIC; + rprbs_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rbist_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcxpat_chnl_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rstart_threshold : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rins_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rdel_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rfull_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rempty_threshold : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rinvalid_code_err_only : IN STD_LOGIC; + rrxpcsbypass_en : IN STD_LOGIC; + rfts_count : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + rcid_pattern_rx : IN STD_LOGIC; + rcid_len_rx : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rauto_speed_ena : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rate : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + speed_change : OUT STD_LOGIC; + rx_div2_sync_in_centrl : IN STD_LOGIC; + rx_div2_sync_in_quad_up : IN STD_LOGIC; + rx_div2_sync_in_quad_down : IN STD_LOGIC; + reset_pc_ptrs_in_centrl : IN STD_LOGIC; + reset_pc_ptrs_in_quad_up : IN STD_LOGIC; + reset_pc_ptrs_in_quad_down : IN STD_LOGIC; + wr_enable_in_centrl : IN STD_LOGIC; + wr_enable_in_quad_up : IN STD_LOGIC; + wr_enable_in_quad_down : IN STD_LOGIC; + rd_enable_in_centrl : IN STD_LOGIC; + rd_enable_in_quad_up : IN STD_LOGIC; + rd_enable_in_quad_down : IN STD_LOGIC; + rx_we_in_centrl : IN STD_LOGIC; + rx_we_in_quad_up : IN STD_LOGIC; + rx_we_in_quad_down : IN STD_LOGIC; + speed_change_in_centrl : IN STD_LOGIC; + rx_div2_sync_in_pipe_quad_up : IN STD_LOGIC; + rx_div2_sync_in_pipe_quad_down : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_up : IN STD_LOGIC; + reset_pc_ptrs_in_pipe_quad_down : IN STD_LOGIC; + wr_enable_in_pipe_quad_up : IN STD_LOGIC; + wr_enable_in_pipe_quad_down : IN STD_LOGIC; + rd_enable_in_pipe_quad_up : IN STD_LOGIC; + rd_enable_in_pipe_quad_down : IN STD_LOGIC; + rx_we_in_pipe_quad_up : IN STD_LOGIC; + rx_we_in_pipe_quad_down : IN STD_LOGIC; + speed_change_in_pipe_quad_up : IN STD_LOGIC; + speed_change_in_pipe_quad_down : IN STD_LOGIC; + config_sel_centrl : IN STD_LOGIC; + config_sel_quad_up : IN STD_LOGIC; + config_sel_quad_down : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rpipeline_bypass_rx : IN STD_LOGIC; + rauto_deassert_pc_rst_cnt : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rauto_pc_en_cnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rself_sw_en_rx : IN STD_LOGIC; + rx_div2_sync_out_pipe_up : OUT STD_LOGIC; + rx_we_out_pipe_up : OUT STD_LOGIC; + wr_enable_out_pipe_up : OUT STD_LOGIC; + rd_enable_out_pipe_up : OUT STD_LOGIC; + reset_pc_ptrs_out_pipe_up : OUT STD_LOGIC; + speed_change_out_pipe_up : OUT STD_LOGIC; + rx_div2_sync_out_pipe_down : OUT STD_LOGIC; + rx_we_out_pipe_down : OUT STD_LOGIC; + wr_enable_out_pipe_down : OUT STD_LOGIC; + rd_enable_out_pipe_down : OUT STD_LOGIC; + reset_pc_ptrs_out_pipe_down : OUT STD_LOGIC; + speed_change_out_pipe_down : OUT STD_LOGIC; + dis_pc_byte : OUT STD_LOGIC; + reset_pc_ptrs : OUT STD_LOGIC; + pcie_switch : OUT STD_LOGIC; + reidleinferenable : IN STD_LOGIC; + reidle_com_detect : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + pipe_loopbk : IN STD_LOGIC; + rxelecidle_int : OUT STD_LOGIC; + rpma_done_count : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + riei_eios_priority_dis : IN STD_LOGIC; + rgen1_sigdet_ena : IN STD_LOGIC; + rrxpcsclkpwdn : IN STD_LOGIC; + rcdr_ctrl_en : IN STD_LOGIC; + rcid_en : IN STD_LOGIC; + rrxvalid_mask : IN STD_LOGIC; + rwait_count : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rmask_count : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + pld_ltr : IN STD_LOGIC; + early_eios : OUT STD_LOGIC; + ltr : OUT STD_LOGIC; + prbs_cid_en : IN STD_LOGIC; + wa_boundary : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + tx_div2_sync_out_pipe_up : IN STD_LOGIC; + fifo_select_out_pipe_up : IN STD_LOGIC; + tx_wr_enable_out_pipe_up : IN STD_LOGIC; + tx_rd_enable_out_pipe_up : IN STD_LOGIC; + tx_div2_sync_out_pipe_down : IN STD_LOGIC; + fifo_select_out_pipe_down : IN STD_LOGIC; + tx_wr_enable_out_pipe_down : IN STD_LOGIC; + tx_rd_enable_out_pipe_down : IN STD_LOGIC; + rwait_for_phfifo_cnt : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + rppm_post_eidle_del : IN STD_LOGIC; + rppm_gen1_2xcnt_en : IN STD_LOGIC; + cg_comp_rd_d_ch0 : IN STD_LOGIC; + cg_comp_rd_d_ch1 : IN STD_LOGIC; + cg_comp_rd_d_ch2 : IN STD_LOGIC; + cg_comp_rd_d_ch3 : IN STD_LOGIC; + cg_comp_wr_ch0 : IN STD_LOGIC; + cg_comp_wr_ch1 : IN STD_LOGIC; + cg_comp_wr_ch2 : IN STD_LOGIC; + cg_comp_wr_ch3 : IN STD_LOGIC; + cg_comp_rd_d_out : OUT STD_LOGIC; + cg_comp_wr_out : OUT STD_LOGIC; + del_cond_met_0 : IN STD_LOGIC; + fifo_ovr_0 : IN STD_LOGIC; + latency_comp_0 : IN STD_LOGIC; + insert_incomplete_0 : IN STD_LOGIC; + del_cond_met_out : OUT STD_LOGIC; + fifo_ovr_out : OUT STD_LOGIC; + latency_comp_out : OUT STD_LOGIC; + insert_incomplete_out : OUT STD_LOGIC; + + -- ww25.2008 + rrx_pipe_enable : IN STD_LOGIC; + rpcs_wrapback_en : IN STD_LOGIC; + rerr_flags_sel : IN STD_LOGIC; + pcs_wrapback_in : IN STD_LOGIC_VECTOR(69 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_digi_chnl_hip_spt + PORT ( + rhip_ena : IN STD_LOGIC; + pcs_rxd_ch : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + pcs_rxvalid : IN STD_LOGIC; + pcs_rxelecidle : IN STD_LOGIC; + pcs_rxstatus_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_phystatus : IN STD_LOGIC; + txpma_local_clk : IN STD_LOGIC; + txd_ch : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + hip_txd_ch : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + txdetectrxloopback : IN STD_LOGIC; + hip_txdetectrxloopback : IN STD_LOGIC; + rxpolarity : IN STD_LOGIC; + hip_rxpolarity : IN STD_LOGIC; + powerdown_ch : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + hip_powerdown_ch : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txdeemph : IN STD_LOGIC; + hip_txdeemph : IN STD_LOGIC; + txmargin_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_txmargin_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidleinfersel_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_eidleinfersel_ch : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rate : IN STD_LOGIC; + hip_rate : IN STD_LOGIC; + hip_txelecidle : IN STD_LOGIC; + rxd_ch : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + hip_rxd_ch : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + rxvalid : OUT STD_LOGIC; + hip_rxvalid : OUT STD_LOGIC; + rxelecidle : OUT STD_LOGIC; + hip_rxelecidle : OUT STD_LOGIC; + rxstatus_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + hip_rxstatus_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + phystatus : OUT STD_LOGIC; + hip_phystatus : OUT STD_LOGIC; + hip_tx_clk : OUT STD_LOGIC; + pcs_txd_ch : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); + pcs_txdetectrxloopback : OUT STD_LOGIC; + pcs_rxpolarity : OUT STD_LOGIC; + pcs_powerdown_ch : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pcs_txdeemph : OUT STD_LOGIC; + pcs_txmargin_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_eidleinfersel_ch : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + pcs_rate : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_q_pipe_interface_top + PORT ( + pipe_tx_clk : IN STD_LOGIC; + pipe_rx_clk : IN STD_LOGIC; + refclk_b : IN STD_LOGIC; + tx_pipe_reset : IN STD_LOGIC; + rx_pipe_reset : IN STD_LOGIC; + refclk_b_reset : IN STD_LOGIC; + rtx_pipe_enable : IN STD_LOGIC; + rrx_pipe_enable : IN STD_LOGIC; + rrdwidth_rx : IN STD_LOGIC; + rtx_elec_idle_delay : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + rtxswing_sel_ena : IN STD_LOGIC; + rrx_detect_bypass : IN STD_LOGIC; + rclkcmpinsertpad : IN STD_LOGIC; + rind_error_reporting : IN STD_LOGIC; + rphystatus_rst_toggle : IN STD_LOGIC; + rphystatus_delay : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txdetectrxloopback : IN STD_LOGIC; + txelecidle : IN STD_LOGIC; + powerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txdeemph : IN STD_LOGIC; + txmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txswing : IN STD_LOGIC; + txd_ch : IN STD_LOGIC_VECTOR(43 DOWNTO 0); + rxpolarity : IN STD_LOGIC; + rxvalid : OUT STD_LOGIC; + rxelecidle : OUT STD_LOGIC; + rxstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rxd_ch : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + phystatus : OUT STD_LOGIC; + revloopback : IN STD_LOGIC; + polinv_rx : IN STD_LOGIC; + txd : OUT STD_LOGIC_VECTOR(43 DOWNTO 0); + rev_loopbk : OUT STD_LOGIC; + tx_elec_idle_comp : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + speed_change : IN STD_LOGIC; + speed_change_centrl : IN STD_LOGIC; + speed_change_quad_up : IN STD_LOGIC; + speed_change_quad_down : IN STD_LOGIC; + rxd : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + polinv_rx_int : OUT STD_LOGIC; + tx_elec_idle : OUT STD_LOGIC; + txdetectrx : OUT STD_LOGIC; + powerstate : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + sigdetni : IN STD_LOGIC; -- ww25_2008 + rx_found : IN STD_LOGIC; + rx_detect_valid : IN STD_LOGIC; + rxelectricalidle : IN STD_LOGIC; + txdetectrxin : IN STD_LOGIC; + powerstatein : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + use_powerstatein : IN STD_LOGIC; + power_state_transition_done : IN STD_LOGIC; + power_state_transition_done_ena : IN STD_LOGIC; + txdeemph_int : OUT STD_LOGIC; + txmargin_int : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txswing_int : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_pcs_reset + PORT ( + hard_reset : IN STD_LOGIC; + clk_2_b : IN STD_LOGIC; + refclk_b_in : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rxpcs_rst : IN STD_LOGIC; + txpcs_rst : IN STD_LOGIC; + rxrst_int : OUT STD_LOGIC; + txrst_int : OUT STD_LOGIC + ); + END COMPONENT; + + --/////////////////////////////////////////////////////////////////////////// + -- Temp registers to reslove fixed width => varaiable width output transfer --// + --/////////////////////////////////////////////////////////////////////////// + + -- cycloneiv_modify begin cycloneiv layer to handle output width changes --- + SIGNAL a1a2sizeout_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL a1detect_reg_sr : STD_LOGIC; + SIGNAL a2detect_reg_sr : STD_LOGIC; + SIGNAL ctrldetect_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dataout_reg_sr : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL dataoutfull_sr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL disperr_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL errdetect_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL k1detect_reg_sr : STD_LOGIC; + SIGNAL k2detect_reg_sr : STD_LOGIC; + SIGNAL patterndetect_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rmfifodatadeleted_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rmfifodatainserted_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL runningdisp_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL syncstatus_reg_sr : STD_LOGIC_VECTOR(1 DOWNTO 0); + -- cycloneiv_modify end cycloneiv layer to handle output width changes ----- + + SIGNAL a1a2sizeout_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL a1detect_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL a2detect_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ctrldetect_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dataout_reg : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL disperr_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL errdetect_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL k1detect_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL k2detect_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL patterndetect_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rmfifodatadeleted_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rmfifodatainserted_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL runningdisp_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL syncstatus_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- new dprio model -- + -- Table5: PCS Per Channel RX Control Register 1 for Channel 0 + constant rrxpcsbypass_en_RXPCS_IDX_0 : integer := 0; + constant rall_one_dect_only_RXPCS_IDX_0 : integer := 1; + constant rbist_clr_rx_RXPCS_IDX_0 : integer := 2; + constant rbisten_rx_RXPCS_IDX_0 : integer := 3; + constant rprbs_clr_rslt_rx_RXPCS_IDX_0 : integer := 4; + constant rprbsen_rx_RXPCS_IDX_0 : integer := 5; + constant rrx_rd_clk_sel_RXPCS_IDX_0 : integer := 6; + constant rclk_2_sel_RXPCS_IDX_0 : integer := 7; + constant rclk_2_sel_RXPCS_IDX_1 : integer := 8; + constant rclk_1_sel_RXPCS_IDX_0 : integer := 9; + constant rclk_1_sel_RXPCS_IDX_1 : integer := 10; + constant rrcvd_clk_sel_RXPCS_IDX_0 : integer := 11; + constant rrcvd_clk_sel_RXPCS_IDX_1 : integer := 12; + constant rfreerun_rx_RXPCS_IDX_0 : integer := 13; + constant rrxurstpcs_RXPCS_IDX_0 : integer := 14; + constant reserved_0_TB5_RXPCS_IDX_0 : integer := 15; + + -- Table6: PCS Per Channel RX Control Register 2 for Channel 0 + constant rcomp_pat_32_RXPCS_IDX_0 : integer := 16; + constant rcomp_pat_33_RXPCS_IDX_0 : integer := 17; + constant rcomp_pat_34_RXPCS_IDX_0 : integer := 18; + constant rcomp_pat_35_RXPCS_IDX_0 : integer := 19; + constant rcomp_pat_36_RXPCS_IDX_0 : integer := 20; + constant rcomp_pat_37_RXPCS_IDX_0 : integer := 21; + constant rcomp_pat_38_RXPCS_IDX_0 : integer := 22; + constant rcomp_pat_39_RXPCS_IDX_0 : integer := 23; + constant rcomp_size_RXPCS_IDX_0 : integer := 24; + constant rcomp_size_RXPCS_IDX_1 : integer := 25; + constant rcomp_size_RXPCS_IDX_2 : integer := 26; + constant rcomp_pat_porn_RXPCS_IDX_0 : integer := 27; + constant rdis_rx_disp_RXPCS_IDX_0 : integer := 28; + constant rencdt_rising_RXPCS_IDX_0 : integer := 29; + constant resync_badcg_en_RXPCS_IDX_0 : integer := 30; + constant resync_badcg_en_RXPCS_IDX_1 : integer := 31; + + -- Table7: PCS Per Channel RX Control Register 3 for Channel 0 + constant rcomp_pat_16_RXPCS_IDX_0 : integer := 32; + constant rcomp_pat_17_RXPCS_IDX_0 : integer := 33; + constant rcomp_pat_18_RXPCS_IDX_0 : integer := 34; + constant rcomp_pat_19_RXPCS_IDX_0 : integer := 35; + constant rcomp_pat_20_RXPCS_IDX_0 : integer := 36; + constant rcomp_pat_21_RXPCS_IDX_0 : integer := 37; + constant rcomp_pat_22_RXPCS_IDX_0 : integer := 38; + constant rcomp_pat_23_RXPCS_IDX_0 : integer := 39; + constant rcomp_pat_24_RXPCS_IDX_0 : integer := 40; + constant rcomp_pat_25_RXPCS_IDX_0 : integer := 41; + constant rcomp_pat_26_RXPCS_IDX_0 : integer := 42; + constant rcomp_pat_27_RXPCS_IDX_0 : integer := 43; + constant rcomp_pat_28_RXPCS_IDX_0 : integer := 44; + constant rcomp_pat_29_RXPCS_IDX_0 : integer := 45; + constant rcomp_pat_30_RXPCS_IDX_0 : integer := 46; + constant rcomp_pat_31_RXPCS_IDX_0 : integer := 47; + + -- Table8: PCS Per Channel RX Control Register 4 for Channel 0 + constant rcomp_pat_0_RXPCS_IDX_0 : integer := 48; + constant rcomp_pat_1_RXPCS_IDX_0 : integer := 49; + constant rcomp_pat_2_RXPCS_IDX_0 : integer := 50; + constant rcomp_pat_3_RXPCS_IDX_0 : integer := 51; + constant rcomp_pat_4_RXPCS_IDX_0 : integer := 52; + constant rcomp_pat_5_RXPCS_IDX_0 : integer := 53; + constant rcomp_pat_6_RXPCS_IDX_0 : integer := 54; + constant rcomp_pat_7_RXPCS_IDX_0 : integer := 55; + constant rcomp_pat_8_RXPCS_IDX_0 : integer := 56; + constant rcomp_pat_9_RXPCS_IDX_0 : integer := 57; + constant rcomp_pat_10_RXPCS_IDX_0 : integer := 58; + constant rcomp_pat_11_RXPCS_IDX_0 : integer := 59; + constant rcomp_pat_12_RXPCS_IDX_0 : integer := 60; + constant rcomp_pat_13_RXPCS_IDX_0 : integer := 61; + constant rcomp_pat_14_RXPCS_IDX_0 : integer := 62; + constant rcomp_pat_15_RXPCS_IDX_0 : integer := 63; + + -- Table9: PCS Per Channel RX Control Register 5 for Channel 0 + constant rbitloc_rev_en_RXPCS_IDX_0 : integer := 64; + constant rbysync_polinv_en_RXPCS_IDX_0 : integer := 65; + constant rwa_6g_en_RXPCS_IDX_0 : integer := 66; + constant rosnumber_RXPCS_IDX_0 : integer := 67; + constant rosnumber_RXPCS_IDX_1 : integer := 68; + constant rosbased_RXPCS_IDX_0 : integer := 69; + constant rkchar_RXPCS_IDX_0 : integer := 70; + constant renumber_RXPCS_IDX_0 : integer := 71; + constant renumber_RXPCS_IDX_1 : integer := 72; + constant renumber_RXPCS_IDX_2 : integer := 73; + constant renumber_RXPCS_IDX_3 : integer := 74; + constant renumber_RXPCS_IDX_4 : integer := 75; + constant renumber_RXPCS_IDX_5 : integer := 76; + constant rib_inv_cd_RXPCS_IDX_0 : integer := 77; + constant rib_inv_cd_RXPCS_IDX_1 : integer := 78; + constant rsync_sm_dis_RXPCS_IDX_0 : integer := 79; + + -- Table10: PCS Per Channel RX Control Register 6 for Channel 0 + constant rknumber_RXPCS_IDX_0 : integer := 80; + constant rknumber_RXPCS_IDX_1 : integer := 81; + constant rknumber_RXPCS_IDX_2 : integer := 82; + constant rknumber_RXPCS_IDX_3 : integer := 83; + constant rknumber_RXPCS_IDX_4 : integer := 84; + constant rknumber_RXPCS_IDX_5 : integer := 85; + constant rknumber_RXPCS_IDX_6 : integer := 86; + constant rknumber_RXPCS_IDX_7 : integer := 87; + constant rgnumber_RXPCS_IDX_0 : integer := 88; + constant rgnumber_RXPCS_IDX_1 : integer := 89; + constant rgnumber_RXPCS_IDX_2 : integer := 90; + constant rgnumber_RXPCS_IDX_3 : integer := 91; + constant rgnumber_RXPCS_IDX_4 : integer := 92; + constant rgnumber_RXPCS_IDX_5 : integer := 93; + constant rgnumber_RXPCS_IDX_6 : integer := 94; + constant rgnumber_RXPCS_IDX_7 : integer := 95; + + -- Table11: PCS Per Channel RX Control Register 7 for Channel 0 + constant renpolinv_rx_RXPCS_IDX_0 : integer := 96; + constant rcascaded_8b10b_en_rx_RXPCS_IDX_0 : integer := 97; + constant r8b10b_dec_ibm_en_RXPCS_IDX_0 : integer := 98; + constant r8b10b_dec_ibm_en_RXPCS_IDX_1 : integer := 99; + constant rendec_rx_RXPCS_IDX_0 : integer := 100; + constant rautobtalg_dis_RXPCS_IDX_0 : integer := 101; + constant rrlv_en_RXPCS_IDX_0 : integer := 102; + constant rlp20ben_RXPCS_IDX_0 : integer := 103; + constant rforce_sig_det_pcs_RXPCS_IDX_0 : integer := 104; + constant rbyte_rev_en_RXPCS_IDX_0 : integer := 105; + constant rrundisp_RXPCS_IDX_0 : integer := 106; + constant rrundisp_RXPCS_IDX_1 : integer := 107; + constant rrundisp_RXPCS_IDX_2 : integer := 108; + constant rrundisp_RXPCS_IDX_3 : integer := 109; + constant rrundisp_RXPCS_IDX_4 : integer := 110; + constant rrundisp_RXPCS_IDX_5 : integer := 111; + + -- Table12: PCS Per Channel RX Control Register 8 for Channel 0 + constant rclkcmpsq1p_0_RXPCS_IDX_0 : integer := 112; + constant rclkcmpsq1p_1_RXPCS_IDX_0 : integer := 113; + constant rclkcmpsq1p_2_RXPCS_IDX_0 : integer := 114; + constant rclkcmpsq1p_3_RXPCS_IDX_0 : integer := 115; + constant rclkcmpsq1p_4_RXPCS_IDX_0 : integer := 116; + constant rclkcmpsq1p_5_RXPCS_IDX_0 : integer := 117; + constant rclkcmpsq1p_6_RXPCS_IDX_0 : integer := 118; + constant rclkcmpsq1p_7_RXPCS_IDX_0 : integer := 119; + constant rclkcmpsq1p_8_RXPCS_IDX_0 : integer := 120; + constant rclkcmpsq1p_9_RXPCS_IDX_0 : integer := 121; + constant rclkcmpsqmd_RXPCS_IDX_0 : integer := 122; + constant rclkcmpinsertpad_RXPCS_IDX_0 : integer := 123; + constant rtruebac2bac_RXPCS_IDX_0 : integer := 124; + constant rskpsetbased_RXPCS_IDX_0 : integer := 125; + constant rgenericfifo_RXPCS_IDX_0 : integer := 126; + constant rmatchen_RXPCS_IDX_0 : integer := 127; + + -- Table13: PCS Per Channel RX Control Register 9 for Channel 0 + constant rclkcmpsq1p_10_RXPCS_IDX_0 : integer := 128; + constant rclkcmpsq1p_11_RXPCS_IDX_0 : integer := 129; + constant rclkcmpsq1p_12_RXPCS_IDX_0 : integer := 130; + constant rclkcmpsq1p_13_RXPCS_IDX_0 : integer := 131; + constant rclkcmpsq1p_14_RXPCS_IDX_0 : integer := 132; + constant rclkcmpsq1p_15_RXPCS_IDX_0 : integer := 133; + constant rclkcmpsq1p_16_RXPCS_IDX_0 : integer := 134; + constant rclkcmpsq1p_17_RXPCS_IDX_0 : integer := 135; + constant rclkcmpsq1p_18_RXPCS_IDX_0 : integer := 136; + constant rclkcmpsq1p_19_RXPCS_IDX_0 : integer := 137; + constant reserved_0_TB13_RXPCS_IDX_0 : integer := 138; + constant rclkcmpsq1n_15_RXPCS_IDX_0 : integer := 139; + constant rclkcmpsq1n_16_RXPCS_IDX_0 : integer := 140; + constant rclkcmpsq1n_17_RXPCS_IDX_0 : integer := 141; + constant rclkcmpsq1n_18_RXPCS_IDX_0 : integer := 142; + constant rclkcmpsq1n_19_RXPCS_IDX_0 : integer := 143; + + -- Table14: PCS Per Channel RX Control Register 10 for Channel 0 + constant rclkcmpsq1n_0_RXPCS_IDX_0 : integer := 144; + constant rclkcmpsq1n_1_RXPCS_IDX_0 : integer := 145; + constant rclkcmpsq1n_2_RXPCS_IDX_0 : integer := 146; + constant rclkcmpsq1n_3_RXPCS_IDX_0 : integer := 147; + constant rclkcmpsq1n_4_RXPCS_IDX_0 : integer := 148; + constant rclkcmpsq1n_5_RXPCS_IDX_0 : integer := 149; + constant rclkcmpsq1n_6_RXPCS_IDX_0 : integer := 150; + constant rclkcmpsq1n_7_RXPCS_IDX_0 : integer := 151; + constant rclkcmpsq1n_8_RXPCS_IDX_0 : integer := 152; + constant rclkcmpsq1n_9_RXPCS_IDX_0 : integer := 153; + constant reserved_0_TB14_RXPCS_IDX_0 : integer := 154; + constant rclkcmpsq1n_10_RXPCS_IDX_0 : integer := 155; + constant rclkcmpsq1n_11_RXPCS_IDX_0 : integer := 156; + constant rclkcmpsq1n_12_RXPCS_IDX_0 : integer := 157; + constant rclkcmpsq1n_13_RXPCS_IDX_0 : integer := 158; + constant rclkcmpsq1n_14_RXPCS_IDX_0 : integer := 159; + + -- Table15: PCS Per Channel RX Control Register 11 for Channel 0 + constant rfull_threshold_RXPCS_IDX_0 : integer := 160; + constant rfull_threshold_RXPCS_IDX_1 : integer := 161; + constant rfull_threshold_RXPCS_IDX_2 : integer := 162; + constant rfull_threshold_RXPCS_IDX_3 : integer := 163; + constant rfull_threshold_RXPCS_IDX_4 : integer := 164; + constant rdel_threshold_RXPCS_IDX_0 : integer := 165; + constant rdel_threshold_RXPCS_IDX_1 : integer := 166; + constant rdel_threshold_RXPCS_IDX_2 : integer := 167; + constant rdel_threshold_RXPCS_IDX_3 : integer := 168; + constant rdel_threshold_RXPCS_IDX_4 : integer := 169; + constant rins_threshold_RXPCS_IDX_0 : integer := 170; + constant rins_threshold_RXPCS_IDX_1 : integer := 171; + constant rins_threshold_RXPCS_IDX_2 : integer := 172; + constant rins_threshold_RXPCS_IDX_3 : integer := 173; + constant rins_threshold_RXPCS_IDX_4 : integer := 174; + constant rclkcmp_pipe_en_RXPCS_IDX_0 : integer := 175; + + -- Table16: PCS Per Channel RX Control Register 12 for Channel 0 + constant rfreq_sel_RXPCS_IDX_0 : integer := 176; + constant rauto_speed_ena_RXPCS_IDX_0 : integer := 177; + constant rhip_ena_RXPCS_IDX_0 : integer := 178; + constant rpma_done_gen_ena_RXPCS_IDX_0 : integer := 179; + constant rpma_done_count_16_RXPCS_IDX_0 : integer := 180; + constant rpma_done_count_17_RXPCS_IDX_0 : integer := 181; + constant reserved_0_TB16_RXPCS_IDX_0 : integer := 182; + constant reserved_0_TB16_RXPCS_IDX_1 : integer := 183; + constant reserved_0_TB16_RXPCS_IDX_2 : integer := 184; + constant reserved_0_TB16_RXPCS_IDX_3 : integer := 185; + constant rstart_threshold_RXPCS_IDX_0 : integer := 186; + constant rstart_threshold_RXPCS_IDX_1 : integer := 187; + constant rstart_threshold_RXPCS_IDX_2 : integer := 188; + constant rempty_threshold_RXPCS_IDX_0 : integer := 189; + constant rempty_threshold_RXPCS_IDX_1 : integer := 190; + constant rempty_threshold_RXPCS_IDX_2 : integer := 191; + + -- Table17: PCS Per Channel RX Control Register 13 for Channel 0 + constant rtest_bus_sel_RXPCS_IDX_0 : integer := 192; + constant rtest_bus_sel_RXPCS_IDX_1 : integer := 193; + constant rtest_bus_sel_RXPCS_IDX_2 : integer := 194; + constant rtest_bus_sel_RXPCS_IDX_3 : integer := 195; + constant rautoinsdis_RXPCS_IDX_0 : integer := 196; + constant rphfifopldenrx_RXPCS_IDX_0 : integer := 197; + constant rbytordplden_RXPCS_IDX_0 : integer := 198; + constant rbyteorden_RXPCS_IDX_0 : integer := 199; + constant rbyteorden_RXPCS_IDX_1 : integer := 200; + constant rbytord_2sym_en_RXPCS_IDX_0 : integer := 201; + constant rinvalid_code_err_only_RXPCS_IDX_0 : integer := 202; + constant rcmpfifourst_RXPCS_IDX_0 : integer := 203; + constant rphfifourstrx_RXPCS_IDX_0 : integer := 204; + constant rdwidth_rx_RXPCS_IDX_0 : integer := 205; + constant rrxfifo_lowlatency_en_RXPCS_IDX_0 : integer := 206; + constant rrxfifo_dis_RXPCS_IDX_0 : integer := 207; + + -- Table18: PCS Per Channel RX Control Register 14 for Channel 0 + constant rbytordpat_0_RXPCS_IDX_0 : integer := 208; + constant rbytordpat_1_RXPCS_IDX_0 : integer := 209; + constant rbytordpat_2_RXPCS_IDX_0 : integer := 210; + constant rbytordpat_3_RXPCS_IDX_0 : integer := 211; + constant rbytordpat_4_RXPCS_IDX_0 : integer := 212; + constant rbytordpat_5_RXPCS_IDX_0 : integer := 213; + constant rbytordpat_6_RXPCS_IDX_0 : integer := 214; + constant rbytordpat_7_RXPCS_IDX_0 : integer := 215; + constant rbytordpat_8_RXPCS_IDX_0 : integer := 216; + constant rbytordpat_9_RXPCS_IDX_0 : integer := 217; + constant reserved_0_TB18_RXPCS_IDX_0 : integer := 218; + constant reserved_0_TB18_RXPCS_IDX_1 : integer := 219; + constant reserved_0_TB18_RXPCS_IDX_2 : integer := 220; + constant reserved_0_TB18_RXPCS_IDX_3 : integer := 221; + constant reserved_0_TB18_RXPCS_IDX_4 : integer := 222; + constant reserved_0_TB18_RXPCS_IDX_5 : integer := 223; + + -- Table19: PCS Per Channel RX Control Register 15 for Channel 0 + constant rbytordpad_RXPCS_IDX_0 : integer := 224; + constant rbytordpad_RXPCS_IDX_1 : integer := 225; + constant rbytordpad_RXPCS_IDX_2 : integer := 226; + constant rbytordpad_RXPCS_IDX_3 : integer := 227; + constant rbytordpad_RXPCS_IDX_4 : integer := 228; + constant rbytordpad_RXPCS_IDX_5 : integer := 229; + constant rbytordpad_RXPCS_IDX_6 : integer := 230; + constant rbytordpad_RXPCS_IDX_7 : integer := 231; + constant rbytordpad_RXPCS_IDX_8 : integer := 232; + constant rbytordpad_RXPCS_IDX_9 : integer := 233; + constant reserved_0_TB19_RXPCS_IDX_0 : integer := 234; + constant reserved_0_TB19_RXPCS_IDX_1 : integer := 235; + constant reserved_0_TB19_RXPCS_IDX_2 : integer := 236; + constant reserved_0_TB19_RXPCS_IDX_3 : integer := 237; + constant reserved_0_TB19_RXPCS_IDX_4 : integer := 238; + constant reserved_0_TB19_RXPCS_IDX_5 : integer := 239; + + -- Table20: PCS Per Channel RX Control Register 16 for Channel 0 + constant rload_shreg_del_RXPCS_IDX_0 : integer := 240; + constant rload_shreg_del_RXPCS_IDX_1 : integer := 241; + constant rload_shreg_del_RXPCS_IDX_2 : integer := 242; + constant rload_shreg_del_RXPCS_IDX_3 : integer := 243; + constant rload_shreg_del_RXPCS_IDX_4 : integer := 244; + constant rphystatus_rst_toggle_RXPCS_IDX_0 : integer := 245; + constant reidle_com_detect_RXPCS_IDX_0 : integer := 246; + constant reidle_com_detect_RXPCS_IDX_1 : integer := 247; + constant rk285detect_RXPCS_IDX_0 : integer := 248; + constant reidleinferenable_RXPCS_IDX_0 : integer := 249; + constant rphystatus_delay_RXPCS_IDX_0 : integer := 250; + constant rphystatus_delay_RXPCS_IDX_1 : integer := 251; + constant rphystatus_delay_RXPCS_IDX_2 : integer := 252; + constant rind_error_reporting_RXPCS_IDX_0 : integer := 253; + constant rrx_detect_bypass_RXPCS_IDX_0 : integer := 254; + constant rrx_pipe_enable_RXPCS_IDX_0 : integer := 255; + + -- Table21: PCS Per Channel RX Control Register 17 for Channel 0 + constant rpma_done_count_0_RXPCS_IDX_0 : integer := 256; + constant rpma_done_count_1_RXPCS_IDX_0 : integer := 257; + constant rpma_done_count_2_RXPCS_IDX_0 : integer := 258; + constant rpma_done_count_3_RXPCS_IDX_0 : integer := 259; + constant rpma_done_count_4_RXPCS_IDX_0 : integer := 260; + constant rpma_done_count_5_RXPCS_IDX_0 : integer := 261; + constant rpma_done_count_6_RXPCS_IDX_0 : integer := 262; + constant rpma_done_count_7_RXPCS_IDX_0 : integer := 263; + constant rpma_done_count_8_RXPCS_IDX_0 : integer := 264; + constant rpma_done_count_9_RXPCS_IDX_0 : integer := 265; + constant rpma_done_count_10_RXPCS_IDX_0 : integer := 266; + constant rpma_done_count_11_RXPCS_IDX_0 : integer := 267; + constant rpma_done_count_12_RXPCS_IDX_0 : integer := 268; + constant rpma_done_count_13_RXPCS_IDX_0 : integer := 269; + constant rpma_done_count_14_RXPCS_IDX_0 : integer := 270; + constant rpma_done_count_15_RXPCS_IDX_0 : integer := 271; + + -- Table22: PCS Per Channel RX Control Register 18 for Channel 0 + constant rbytordpat_10_RXPCS_IDX_0 : integer := 272; + constant rbytordpat_11_RXPCS_IDX_0 : integer := 273; + constant rbytordpat_12_RXPCS_IDX_0 : integer := 274; + constant rbytordpat_13_RXPCS_IDX_0 : integer := 275; + constant rbytordpat_14_RXPCS_IDX_0 : integer := 276; + constant rbytordpat_15_RXPCS_IDX_0 : integer := 277; + constant rbytordpat_16_RXPCS_IDX_0 : integer := 278; + constant rbytordpat_17_RXPCS_IDX_0 : integer := 279; + constant rbytordpat_18_RXPCS_IDX_0 : integer := 280; + constant rbytordpat_19_RXPCS_IDX_0 : integer := 281; + constant rbytord_6g_mask_en_RXPCS_IDX_0 : integer := 282; + constant rbytord_s2gx_RXPCS_IDX_0 : integer := 283; + constant reserved_0_TB22_RXPCS_IDX_0 : integer := 284; + constant rcdr_ctrl_en_RXPCS_IDX_0 : integer := 285; + constant rrxpcsclkpwdn_RXPCS_IDX_0 : integer := 286; + constant rerr_flags_sel_RXPCS_IDX_0 : integer := 287; + + -- Table23: PCS Per Channel RX Control Register 19 for Channel 0 + constant rwait_count_RXPCS_IDX_0 : integer := 288; + constant rwait_count_RXPCS_IDX_1 : integer := 289; + constant rwait_count_RXPCS_IDX_2 : integer := 290; + constant rwait_count_RXPCS_IDX_3 : integer := 291; + constant rwait_count_RXPCS_IDX_4 : integer := 292; + constant rwait_count_RXPCS_IDX_5 : integer := 293; + constant rwait_count_RXPCS_IDX_6 : integer := 294; + constant rwait_count_RXPCS_IDX_7 : integer := 295; + constant reserved_0_TB23_RXPCS_IDX_0 : integer := 296; + constant reserved_0_TB23_RXPCS_IDX_1 : integer := 297; + constant reserved_0_TB23_RXPCS_IDX_2 : integer := 298; + constant reserved_0_TB23_RXPCS_IDX_3 : integer := 299; + constant reserved_0_TB23_RXPCS_IDX_4 : integer := 300; + constant reserved_0_TB23_RXPCS_IDX_5 : integer := 301; + constant reserved_0_TB23_RXPCS_IDX_6 : integer := 302; + constant reserved_0_TB23_RXPCS_IDX_7 : integer := 303; + + -- Table24: PCS Per Channel RX Control Register 20 for Channel 0 + constant rfts_count_RXPCS_IDX_0 : integer := 304; + constant rfts_count_RXPCS_IDX_1 : integer := 305; + constant rfts_count_RXPCS_IDX_2 : integer := 306; + constant rfts_count_RXPCS_IDX_3 : integer := 307; + constant rfts_count_RXPCS_IDX_4 : integer := 308; + constant rfts_count_RXPCS_IDX_5 : integer := 309; + constant rfts_count_RXPCS_IDX_6 : integer := 310; + constant rfts_count_RXPCS_IDX_7 : integer := 311; + constant rfts_count_RXPCS_IDX_8 : integer := 312; + constant rfts_count_RXPCS_IDX_9 : integer := 313; + constant rwait_for_phfifo_cnt_RXPCS_IDX_0 : integer := 314; + constant rwait_for_phfifo_cnt_RXPCS_IDX_1 : integer := 315; + constant rwait_for_phfifo_cnt_RXPCS_IDX_2 : integer := 316; + constant rwait_for_phfifo_cnt_RXPCS_IDX_3 : integer := 317; + constant rwait_for_phfifo_cnt_RXPCS_IDX_4 : integer := 318; + constant rwait_for_phfifo_cnt_RXPCS_IDX_5 : integer := 319; + + -- Table25: PCS Per Channel RX Control Register 21 for Channel 0 + constant rppm_meas_delay_RXPCS_IDX_0 : integer := 320; + constant rcid_len_rx_RXPCS_IDX_0 : integer := 321; + constant rcid_len_rx_RXPCS_IDX_1 : integer := 322; + constant rcid_len_rx_RXPCS_IDX_2 : integer := 323; + constant rcid_len_rx_RXPCS_IDX_3 : integer := 324; + constant rcid_len_rx_RXPCS_IDX_4 : integer := 325; + constant rcid_len_rx_RXPCS_IDX_5 : integer := 326; + constant rcid_len_rx_RXPCS_IDX_6 : integer := 327; + constant rcid_len_rx_RXPCS_IDX_7 : integer := 328; + constant rcid_pattern_rx_RXPCS_IDX_0 : integer := 329; + constant rpcs_wrapback_en_RXPCS_IDX_0 : integer := 330; + constant reserved_0_TB25_RXPCS_IDX_0 : integer := 331; + constant reserved_0_TB25_RXPCS_IDX_1 : integer := 332; + constant reserved_0_TB25_RXPCS_IDX_2 : integer := 333; + constant reserved_0_TB25_RXPCS_IDX_3 : integer := 334; + constant reserved_0_TB25_RXPCS_IDX_4 : integer := 335; + + -- Table26: PCS Per Channel RX Control Register 22 for Channel 0 + constant rauto_pc_en_cnt_RXPCS_IDX_0 : integer := 336; + constant rauto_pc_en_cnt_RXPCS_IDX_1 : integer := 337; + constant rauto_pc_en_cnt_RXPCS_IDX_2 : integer := 338; + constant rauto_pc_en_cnt_RXPCS_IDX_3 : integer := 339; + constant rauto_pc_en_cnt_RXPCS_IDX_4 : integer := 340; + constant reserved_1_TB26_RXPCS_IDX_0 : integer := 341; + constant rauto_deassert_pc_rst_cnt_RXPCS_IDX_0 : integer := 342; + constant rauto_deassert_pc_rst_cnt_RXPCS_IDX_1 : integer := 343; + constant rauto_deassert_pc_rst_cnt_RXPCS_IDX_2 : integer := 344; + constant rauto_deassert_pc_rst_cnt_RXPCS_IDX_3 : integer := 345; + constant reserved_0_TB26_RXPCS_IDX_0 : integer := 346; + constant rpipeline_bypass_rx_RXPCS_IDX_0 : integer := 347; + constant rself_sw_en_rx_RXPCS_IDX_0 : integer := 348; + constant rrxvalid_mask_RXPCS_IDX_0 : integer := 349; + constant rcid_en_RXPCS_IDX_0 : integer := 350; + constant rphfifo_regmode_rx_RXPCS_IDX_0 : integer := 351; + + -- Table27: PCS Per Channel RX Control Register 23 for Channel 0 + constant rmask_count_RXPCS_IDX_0 : integer := 352; + constant rmask_count_RXPCS_IDX_1 : integer := 353; + constant rmask_count_RXPCS_IDX_2 : integer := 354; + constant rmask_count_RXPCS_IDX_3 : integer := 355; + constant rmask_count_RXPCS_IDX_4 : integer := 356; + constant rmask_count_RXPCS_IDX_5 : integer := 357; + constant rmask_count_RXPCS_IDX_6 : integer := 358; + constant rmask_count_RXPCS_IDX_7 : integer := 359; + constant rmask_count_RXPCS_IDX_8 : integer := 360; + constant rmask_count_RXPCS_IDX_9 : integer := 361; + constant rgen1_sigdet_ena_RXPCS_IDX_0 : integer := 362; + constant riei_eios_priority_dis_RXPCS_IDX_0 : integer := 363; + constant reserved_0_TB27_RXPCS_IDX_0 : integer := 364; + constant reserved_0_TB27_RXPCS_IDX_1 : integer := 365; + constant reserved_0_TB27_RXPCS_IDX_2 : integer := 366; + constant reserved_0_TB27_RXPCS_IDX_3 : integer := 367; + + -- Existing + constant rpmadwidth_rx_RX_IDX : integer := 368; + constant rpma_doublewidth_rx_RX_IDX : integer := 369; + constant rendec_data_sel_rx_RX_IDX : integer := 370; + constant rindv_rx_RX_IDX : integer := 371; + constant rdwidth_rx_RX_IDX : integer := 372; + constant rtx_idle_delay_RX_IDX_0 : integer := 373; + constant rtx_idle_delay_RX_IDX_1 : integer := 374; + constant rclkcmppos_RX_IDX : integer := 375; + constant rppmsel_RX_IDX_0 : integer := 376; + --constant rppmsel_RX_IDX_5 : integer := 377; + constant rppmsel_RX_IDX_5 : integer := 381; + constant rforce0_freqdet_RX_IDX : integer := 382; + constant rforce1_freqdet_RX_IDX : integer := 383; + constant rs_lpbk_RX_IDX : integer := 384; + constant rrx_revlb_sw_RX_IDX : integer := 385; + + -- --------------------------------------------------------------------------- + -- DPRIO input CRAM + -- --------------------------------------------------------------------------- + -- Existing + SIGNAL dprioin_dskwclksel: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_is_lane0: STD_LOGIC; + SIGNAL dprioin_rbist_sel: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rbitslip_size: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rclkcmppos: STD_LOGIC; + SIGNAL dprioin_rcxpat_chnl_en: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rdskchrp: STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL dprioin_rdskposdisp: STD_LOGIC; + SIGNAL dprioin_rendec_data_sel_rx: STD_LOGIC; + SIGNAL dprioin_rforce0_freqdet: STD_LOGIC; + SIGNAL dprioin_rforce1_freqdet: STD_LOGIC; + SIGNAL dprioin_rindv_rx: STD_LOGIC; + SIGNAL dprioin_rphfifo_master_sel_rx: STD_LOGIC; + SIGNAL dprioin_rpma_doublewidth_rx: STD_LOGIC; + SIGNAL dprioin_rpmadwidth_rx: STD_LOGIC; + SIGNAL dprioin_rppm_cnt_reset: STD_LOGIC; + SIGNAL dprioin_rppmsel: STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL dprioin_rprbs_sel: STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dprioin_rrdwidth_rx: STD_LOGIC; -- rx only + SIGNAL dprioin_rrx_revlb_sw: STD_LOGIC; + SIGNAL dprioin_rs_lpbk: STD_LOGIC; + SIGNAL dprioin_rtx_elec_idle_delay: STD_LOGIC_VECTOR(1 DOWNTO 0); -- rx only + SIGNAL dprioin_rtx_pipe_enable: STD_LOGIC; + SIGNAL dprioin_scan_mode: STD_LOGIC; + SIGNAL dprioin_sel_gp_md: STD_LOGIC; + + -- PCS Per Channel RX Control Register 1 for Channel 0 + SIGNAL dprioin_rrxpcsbypass_en : STD_LOGIC; + SIGNAL dprioin_rall_one_dect_only : STD_LOGIC; + SIGNAL dprioin_rbist_clr_rx : STD_LOGIC; + SIGNAL dprioin_rbisten_rx : STD_LOGIC; + SIGNAL dprioin_rprbs_clr_rslt_rx : STD_LOGIC; + SIGNAL dprioin_rprbsen_rx : STD_LOGIC; + SIGNAL dprioin_rrx_rd_clk_sel : STD_LOGIC; + SIGNAL dprioin_rclk_2_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rclk_1_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rrcvd_clk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rfreerun_rx : STD_LOGIC; + SIGNAL dprioin_rrxurstpcs : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB5 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 2 for Channel 0 + SIGNAL dprioin_rcomp_pat_32 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_33 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_34 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_35 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_36 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_37 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_38 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_39 : STD_LOGIC; + SIGNAL dprioin_rcomp_size : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dprioin_rcomp_pat_porn : STD_LOGIC; + SIGNAL dprioin_rdis_rx_disp : STD_LOGIC; + SIGNAL dprioin_rencdt_rising : STD_LOGIC; + SIGNAL dprioin_resync_badcg_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- PCS Per Channel RX Control Register 3 for Channel 0 + SIGNAL dprioin_rcomp_pat_16 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_17 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_18 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_19 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_20 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_21 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_22 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_23 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_24 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_25 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_26 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_27 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_28 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_29 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_30 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_31 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 4 for Channel 0 + SIGNAL dprioin_rcomp_pat_0 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_1 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_2 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_3 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_4 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_5 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_6 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_7 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_8 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_9 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_10 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_11 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_12 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_13 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_14 : STD_LOGIC; + SIGNAL dprioin_rcomp_pat_15 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 5 for Channel 0 + SIGNAL dprioin_rbitloc_rev_en : STD_LOGIC; + SIGNAL dprioin_rbysync_polinv_en : STD_LOGIC; + SIGNAL dprioin_rwa_6g_en : STD_LOGIC; + SIGNAL dprioin_rosnumber : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rosbased : STD_LOGIC; + SIGNAL dprioin_rkchar : STD_LOGIC; + SIGNAL dprioin_renumber : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL dprioin_rib_inv_cd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rsync_sm_dis : STD_LOGIC; + + -- PCS Per Channel RX Control Register 6 for Channel 0 + SIGNAL dprioin_rknumber : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dprioin_rgnumber : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- PCS Per Channel RX Control Register 7 for Channel 0 + SIGNAL dprioin_renpolinv_rx : STD_LOGIC; + SIGNAL dprioin_rcascaded_8b10b_en_rx : STD_LOGIC; + SIGNAL dprioin_r8b10b_dec_ibm_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rendec_rx : STD_LOGIC; + SIGNAL dprioin_rautobtalg_dis : STD_LOGIC; + SIGNAL dprioin_rrlv_en : STD_LOGIC; + SIGNAL dprioin_rlp20ben : STD_LOGIC; + SIGNAL dprioin_rforce_sig_det_pcs : STD_LOGIC; + SIGNAL dprioin_rbyte_rev_en : STD_LOGIC; + SIGNAL dprioin_rrundisp : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 8 for Channel 0 + SIGNAL dprioin_rclkcmpsq1p_0 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_1 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_2 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_3 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_4 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_5 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_6 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_7 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_8 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_9 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsqmd : STD_LOGIC; + SIGNAL dprioin_rclkcmpinsertpad : STD_LOGIC; + SIGNAL dprioin_rtruebac2bac : STD_LOGIC; + SIGNAL dprioin_rskpsetbased : STD_LOGIC; + SIGNAL dprioin_rgenericfifo : STD_LOGIC; + SIGNAL dprioin_rmatchen : STD_LOGIC; + + -- PCS Per Channel RX Control Register 9 for Channel 0 + SIGNAL dprioin_rclkcmpsq1p_10 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_11 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_12 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_13 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_14 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_15 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_16 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_17 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_18 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1p_19 : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB13 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_15 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_16 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_17 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_18 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_19 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 10 for Channel 0 + SIGNAL dprioin_rclkcmpsq1n_0 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_1 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_2 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_3 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_4 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_5 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_6 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_7 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_8 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_9 : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB14 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_10 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_11 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_12 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_13 : STD_LOGIC; + SIGNAL dprioin_rclkcmpsq1n_14 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 11 for Channel 0 + SIGNAL dprioin_rfull_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dprioin_rdel_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dprioin_rins_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dprioin_rclkcmp_pipe_en : STD_LOGIC; + + -- PCS Per Channel RX Control Register 12 for Channel 0 + SIGNAL dprioin_rfreq_sel : STD_LOGIC; + SIGNAL dprioin_rauto_speed_ena : STD_LOGIC; + SIGNAL dprioin_rhip_ena : STD_LOGIC; + SIGNAL dprioin_rpma_done_gen_ena : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_16 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_17 : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB16 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dprioin_rstart_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dprioin_rempty_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- PCS Per Channel RX Control Register 13 for Channel 0 + SIGNAL dprioin_rtest_bus_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dprioin_rautoinsdis : STD_LOGIC; + SIGNAL dprioin_rphfifopldenrx : STD_LOGIC; + SIGNAL dprioin_rbytordplden : STD_LOGIC; + SIGNAL dprioin_rbyteorden : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rbytord_2sym_en : STD_LOGIC; + SIGNAL dprioin_rinvalid_code_err_only : STD_LOGIC; + SIGNAL dprioin_rcmpfifourst : STD_LOGIC; + SIGNAL dprioin_rphfifourstrx : STD_LOGIC; + SIGNAL dprioin_rdwidth_rx : STD_LOGIC; + SIGNAL dprioin_rrxfifo_lowlatency_en : STD_LOGIC; + SIGNAL dprioin_rrxfifo_dis : STD_LOGIC; + + -- PCS Per Channel RX Control Register 14 for Channel 0 + SIGNAL dprioin_rbytordpat_0 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_1 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_2 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_3 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_4 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_5 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_6 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_7 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_8 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_9 : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB18 : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 15 for Channel 0 + SIGNAL dprioin_rbytordpad : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL dprioin_reserved_0_TB19 : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 16 for Channel 0 + SIGNAL dprioin_rload_shreg_del : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dprioin_rphystatus_rst_toggle : STD_LOGIC; + SIGNAL dprioin_reidle_com_detect : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dprioin_rk285detect : STD_LOGIC; + SIGNAL dprioin_reidleinferenable : STD_LOGIC; + SIGNAL dprioin_rphystatus_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dprioin_rind_error_reporting : STD_LOGIC; + SIGNAL dprioin_rrx_detect_bypass : STD_LOGIC; + SIGNAL dprioin_rrx_pipe_enable : STD_LOGIC; + + -- PCS Per Channel RX Control Register 17 for Channel 0 + SIGNAL dprioin_rpma_done_count_0 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_1 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_2 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_3 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_4 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_5 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_6 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_7 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_8 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_9 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_10 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_11 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_12 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_13 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_14 : STD_LOGIC; + SIGNAL dprioin_rpma_done_count_15 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 18 for Channel 0 + SIGNAL dprioin_rbytordpat_10 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_11 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_12 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_13 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_14 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_15 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_16 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_17 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_18 : STD_LOGIC; + SIGNAL dprioin_rbytordpat_19 : STD_LOGIC; + SIGNAL dprioin_rbytord_6g_mask_en : STD_LOGIC; + SIGNAL dprioin_rbytord_s2gx : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB22 : STD_LOGIC; + SIGNAL dprioin_rcdr_ctrl_en : STD_LOGIC; + SIGNAL dprioin_rrxpcsclkpwdn : STD_LOGIC; + SIGNAL dprioin_rerr_flags_sel : STD_LOGIC; + + -- PCS Per Channel RX Control Register 19 for Channel 0 + SIGNAL dprioin_rwait_count : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dprioin_reserved_0_TB23 : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- PCS Per Channel RX Control Register 20 for Channel 0 + SIGNAL dprioin_rfts_count : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL dprioin_rwait_for_phfifo_cnt : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 21 for Channel 0 + SIGNAL dprioin_rppm_meas_delay : STD_LOGIC; + SIGNAL dprioin_rcid_len_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dprioin_rcid_pattern_rx : STD_LOGIC; + SIGNAL dprioin_rpcs_wrapback_en : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB25 : STD_LOGIC_VECTOR(4 DOWNTO 0); + + -- PCS Per Channel RX Control Register 22 for Channel 0 + SIGNAL dprioin_rauto_pc_en_cnt : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dprioin_reserved_1_TB26 : STD_LOGIC; + SIGNAL dprioin_rauto_deassert_pc_rst_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dprioin_reserved_0_TB26 : STD_LOGIC; + SIGNAL dprioin_rpipeline_bypass_rx : STD_LOGIC; + SIGNAL dprioin_rself_sw_en_rx : STD_LOGIC; + SIGNAL dprioin_rrxvalid_mask : STD_LOGIC; + SIGNAL dprioin_rcid_en : STD_LOGIC; + SIGNAL dprioin_rphfifo_regmode_rx : STD_LOGIC; + + -- PCS Per Channel RX Control Register 23 for Channel 0 + SIGNAL dprioin_rmask_count : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL dprioin_rgen1_sigdet_ena : STD_LOGIC; + SIGNAL dprioin_riei_eios_priority_dis : STD_LOGIC; + SIGNAL dprioin_reserved_0_TB27 : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- --------------------------------------------------------------------------- + -- Initial CRAM + -- --------------------------------------------------------------------------- + -- Existing + SIGNAL init_dskwclksel: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_is_lane0: STD_LOGIC; + SIGNAL init_rbist_sel: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rbitslip_size: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rclkcmppos: STD_LOGIC; + SIGNAL init_rcxpat_chnl_en: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rdskchrp: STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL init_rdskposdisp: STD_LOGIC; + SIGNAL init_rendec_data_sel_rx: STD_LOGIC; + SIGNAL init_renpolinv_en: STD_LOGIC; + SIGNAL init_rforce0_freqdet: STD_LOGIC; + SIGNAL init_rforce1_freqdet: STD_LOGIC; + SIGNAL init_rindv_rx: STD_LOGIC; + SIGNAL init_rphfifo_master_sel_rx: STD_LOGIC; + SIGNAL init_rpma_doublewidth_rx: STD_LOGIC; + SIGNAL init_rpmadwidth_rx: STD_LOGIC; + SIGNAL init_rppm_cnt_reset: STD_LOGIC; + SIGNAL init_rppmsel: STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL init_rprbs_sel: STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rrdwidth_rx: STD_LOGIC; -- rx only + SIGNAL init_rrx_revlb_sw: STD_LOGIC; + SIGNAL init_rs_lpbk: STD_LOGIC; + SIGNAL init_rtx_elec_idle_delay: STD_LOGIC_VECTOR(1 DOWNTO 0); -- rx only + SIGNAL init_rtx_pipe_enable: STD_LOGIC; -- tx pipe + SIGNAL init_scan_mode: STD_LOGIC; + SIGNAL init_sel_gp_md: STD_LOGIC; + + -- PCS Per Channel RX Control Register 1 for Channel 0 + SIGNAL init_rrxpcsbypass_en : STD_LOGIC; + SIGNAL init_rall_one_dect_only : STD_LOGIC; + SIGNAL init_rbist_clr_rx : STD_LOGIC; + SIGNAL init_rbisten_rx : STD_LOGIC; + SIGNAL init_rprbs_clr_rslt_rx : STD_LOGIC; + SIGNAL init_rprbsen_rx : STD_LOGIC; + SIGNAL init_rrx_rd_clk_sel : STD_LOGIC; + SIGNAL init_rclk_2_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rclk_1_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rrcvd_clk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rfreerun_rx : STD_LOGIC; + SIGNAL init_rrxurstpcs : STD_LOGIC; + SIGNAL init_reserved_0_TB5 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 2 for Channel 0 + SIGNAL init_rcomp_pat_32 : STD_LOGIC; + SIGNAL init_rcomp_pat_33 : STD_LOGIC; + SIGNAL init_rcomp_pat_34 : STD_LOGIC; + SIGNAL init_rcomp_pat_35 : STD_LOGIC; + SIGNAL init_rcomp_pat_36 : STD_LOGIC; + SIGNAL init_rcomp_pat_37 : STD_LOGIC; + SIGNAL init_rcomp_pat_38 : STD_LOGIC; + SIGNAL init_rcomp_pat_39 : STD_LOGIC; + SIGNAL init_rcomp_size : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rcomp_pat_porn : STD_LOGIC; + SIGNAL init_rdis_rx_disp : STD_LOGIC; + SIGNAL init_rencdt_rising : STD_LOGIC; + SIGNAL init_resync_badcg_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- PCS Per Channel RX Control Register 3 for Channel 0 + SIGNAL init_rcomp_pat_16 : STD_LOGIC; + SIGNAL init_rcomp_pat_17 : STD_LOGIC; + SIGNAL init_rcomp_pat_18 : STD_LOGIC; + SIGNAL init_rcomp_pat_19 : STD_LOGIC; + SIGNAL init_rcomp_pat_20 : STD_LOGIC; + SIGNAL init_rcomp_pat_21 : STD_LOGIC; + SIGNAL init_rcomp_pat_22 : STD_LOGIC; + SIGNAL init_rcomp_pat_23 : STD_LOGIC; + SIGNAL init_rcomp_pat_24 : STD_LOGIC; + SIGNAL init_rcomp_pat_25 : STD_LOGIC; + SIGNAL init_rcomp_pat_26 : STD_LOGIC; + SIGNAL init_rcomp_pat_27 : STD_LOGIC; + SIGNAL init_rcomp_pat_28 : STD_LOGIC; + SIGNAL init_rcomp_pat_29 : STD_LOGIC; + SIGNAL init_rcomp_pat_30 : STD_LOGIC; + SIGNAL init_rcomp_pat_31 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 4 for Channel 0 + SIGNAL init_rcomp_pat_0 : STD_LOGIC; + SIGNAL init_rcomp_pat_1 : STD_LOGIC; + SIGNAL init_rcomp_pat_2 : STD_LOGIC; + SIGNAL init_rcomp_pat_3 : STD_LOGIC; + SIGNAL init_rcomp_pat_4 : STD_LOGIC; + SIGNAL init_rcomp_pat_5 : STD_LOGIC; + SIGNAL init_rcomp_pat_6 : STD_LOGIC; + SIGNAL init_rcomp_pat_7 : STD_LOGIC; + SIGNAL init_rcomp_pat_8 : STD_LOGIC; + SIGNAL init_rcomp_pat_9 : STD_LOGIC; + SIGNAL init_rcomp_pat_10 : STD_LOGIC; + SIGNAL init_rcomp_pat_11 : STD_LOGIC; + SIGNAL init_rcomp_pat_12 : STD_LOGIC; + SIGNAL init_rcomp_pat_13 : STD_LOGIC; + SIGNAL init_rcomp_pat_14 : STD_LOGIC; + SIGNAL init_rcomp_pat_15 : STD_LOGIC; + + SIGNAL init_rcomp_pat : STD_LOGIC_VECTOR(39 DOWNTO 0); + + -- PCS Per Channel RX Control Register 5 for Channel 0 + SIGNAL init_rbitloc_rev_en : STD_LOGIC; + SIGNAL init_rbysync_polinv_en : STD_LOGIC; + SIGNAL init_rwa_6g_en : STD_LOGIC; + SIGNAL init_rosnumber : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rosbased : STD_LOGIC; + SIGNAL init_rkchar : STD_LOGIC; + SIGNAL init_renumber : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL init_rib_inv_cd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rsync_sm_dis : STD_LOGIC; + + -- PCS Per Channel RX Control Register 6 for Channel 0 + SIGNAL init_rknumber : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL init_rgnumber : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- PCS Per Channel RX Control Register 7 for Channel 0 + SIGNAL init_renpolinv_rx : STD_LOGIC; + SIGNAL init_rcascaded_8b10b_en_rx : STD_LOGIC; + SIGNAL init_r8b10b_dec_ibm_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rendec_rx : STD_LOGIC; + SIGNAL init_rautobtalg_dis : STD_LOGIC; + SIGNAL init_rrlv_en : STD_LOGIC; + SIGNAL init_rlp20ben : STD_LOGIC; + SIGNAL init_rforce_sig_det_pcs : STD_LOGIC; + SIGNAL init_rbyte_rev_en : STD_LOGIC; + SIGNAL init_rrundisp : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 8 for Channel 0 + SIGNAL init_rclkcmpsq1p_0 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_1 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_2 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_3 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_4 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_5 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_6 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_7 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_8 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_9 : STD_LOGIC; + SIGNAL init_rclkcmpsqmd : STD_LOGIC; + SIGNAL init_rclkcmpinsertpad : STD_LOGIC; + SIGNAL init_rtruebac2bac : STD_LOGIC; + SIGNAL init_rskpsetbased : STD_LOGIC; + SIGNAL init_rgenericfifo : STD_LOGIC; + SIGNAL init_rmatchen : STD_LOGIC; + + -- PCS Per Channel RX Control Register 9 for Channel 0 + SIGNAL init_rclkcmpsq1p_10 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_11 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_12 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_13 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_14 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_15 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_16 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_17 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_18 : STD_LOGIC; + SIGNAL init_rclkcmpsq1p_19 : STD_LOGIC; + SIGNAL init_reserved_0_TB13 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_15 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_16 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_17 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_18 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_19 : STD_LOGIC; + + SIGNAL init_rclkcmpsq1p : STD_LOGIC_VECTOR(19 DOWNTO 0); + + -- PCS Per Channel RX Control Register 10 for Channel 0 + SIGNAL init_rclkcmpsq1n_0 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_1 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_2 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_3 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_4 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_5 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_6 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_7 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_8 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_9 : STD_LOGIC; + SIGNAL init_reserved_0_TB14 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_10 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_11 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_12 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_13 : STD_LOGIC; + SIGNAL init_rclkcmpsq1n_14 : STD_LOGIC; + + SIGNAL init_rclkcmpsq1n : STD_LOGIC_VECTOR(19 DOWNTO 0); + + -- PCS Per Channel RX Control Register 11 for Channel 0 + SIGNAL init_rfull_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_rdel_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_rins_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_rclkcmp_pipe_en : STD_LOGIC; + + -- PCS Per Channel RX Control Register 12 for Channel 0 + SIGNAL init_rfreq_sel : STD_LOGIC; + SIGNAL init_rauto_speed_ena : STD_LOGIC; + SIGNAL init_rhip_ena : STD_LOGIC; + SIGNAL init_rpma_done_gen_ena : STD_LOGIC; + SIGNAL init_rpma_done_count_16 : STD_LOGIC; + SIGNAL init_rpma_done_count_17 : STD_LOGIC; + SIGNAL init_reserved_0_TB16 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL init_rstart_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rempty_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- PCS Per Channel RX Control Register 13 for Channel 0 + SIGNAL init_rtest_bus_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL init_rautoinsdis : STD_LOGIC; + SIGNAL init_rphfifopldenrx : STD_LOGIC; + SIGNAL init_rbytordplden : STD_LOGIC; + SIGNAL init_rbyteorden : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rbytord_2sym_en : STD_LOGIC; + SIGNAL init_rinvalid_code_err_only : STD_LOGIC; + SIGNAL init_rcmpfifourst : STD_LOGIC; + SIGNAL init_rphfifourstrx : STD_LOGIC; + SIGNAL init_rdwidth_rx : STD_LOGIC; + SIGNAL init_rrxfifo_lowlatency_en : STD_LOGIC; + SIGNAL init_rrxfifo_dis : STD_LOGIC; + + -- PCS Per Channel RX Control Register 14 for Channel 0 + SIGNAL init_rbytordpat_0 : STD_LOGIC; + SIGNAL init_rbytordpat_1 : STD_LOGIC; + SIGNAL init_rbytordpat_2 : STD_LOGIC; + SIGNAL init_rbytordpat_3 : STD_LOGIC; + SIGNAL init_rbytordpat_4 : STD_LOGIC; + SIGNAL init_rbytordpat_5 : STD_LOGIC; + SIGNAL init_rbytordpat_6 : STD_LOGIC; + SIGNAL init_rbytordpat_7 : STD_LOGIC; + SIGNAL init_rbytordpat_8 : STD_LOGIC; + SIGNAL init_rbytordpat_9 : STD_LOGIC; + SIGNAL init_reserved_0_TB18 : STD_LOGIC_VECTOR(5 DOWNTO 0); + + SIGNAL init_rbytordpat : STD_LOGIC_VECTOR(19 DOWNTO 0); + + -- PCS Per Channel RX Control Register 15 for Channel 0 + SIGNAL init_rbytordpad : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL init_reserved_0_TB19 : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 16 for Channel 0 + SIGNAL init_rload_shreg_del : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_rphystatus_rst_toggle : STD_LOGIC; + SIGNAL init_reidle_com_detect : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rk285detect : STD_LOGIC; + SIGNAL init_reidleinferenable : STD_LOGIC; + SIGNAL init_rphystatus_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_rind_error_reporting : STD_LOGIC; + SIGNAL init_rrx_detect_bypass : STD_LOGIC; + SIGNAL init_rrx_pipe_enable : STD_LOGIC; + + -- PCS Per Channel RX Control Register 17 for Channel 0 + SIGNAL init_rpma_done_count_0 : STD_LOGIC; + SIGNAL init_rpma_done_count_1 : STD_LOGIC; + SIGNAL init_rpma_done_count_2 : STD_LOGIC; + SIGNAL init_rpma_done_count_3 : STD_LOGIC; + SIGNAL init_rpma_done_count_4 : STD_LOGIC; + SIGNAL init_rpma_done_count_5 : STD_LOGIC; + SIGNAL init_rpma_done_count_6 : STD_LOGIC; + SIGNAL init_rpma_done_count_7 : STD_LOGIC; + SIGNAL init_rpma_done_count_8 : STD_LOGIC; + SIGNAL init_rpma_done_count_9 : STD_LOGIC; + SIGNAL init_rpma_done_count_10 : STD_LOGIC; + SIGNAL init_rpma_done_count_11 : STD_LOGIC; + SIGNAL init_rpma_done_count_12 : STD_LOGIC; + SIGNAL init_rpma_done_count_13 : STD_LOGIC; + SIGNAL init_rpma_done_count_14 : STD_LOGIC; + SIGNAL init_rpma_done_count_15 : STD_LOGIC; + + SIGNAL init_rpma_done_count : STD_LOGIC_VECTOR(17 DOWNTO 0); + + -- PCS Per Channel RX Control Register 18 for Channel 0 + SIGNAL init_rbytordpat_10 : STD_LOGIC; + SIGNAL init_rbytordpat_11 : STD_LOGIC; + SIGNAL init_rbytordpat_12 : STD_LOGIC; + SIGNAL init_rbytordpat_13 : STD_LOGIC; + SIGNAL init_rbytordpat_14 : STD_LOGIC; + SIGNAL init_rbytordpat_15 : STD_LOGIC; + SIGNAL init_rbytordpat_16 : STD_LOGIC; + SIGNAL init_rbytordpat_17 : STD_LOGIC; + SIGNAL init_rbytordpat_18 : STD_LOGIC; + SIGNAL init_rbytordpat_19 : STD_LOGIC; + SIGNAL init_rbytord_6g_mask_en : STD_LOGIC; + SIGNAL init_rbytord_s2gx : STD_LOGIC; + SIGNAL init_reserved_0_TB22 : STD_LOGIC; + SIGNAL init_rcdr_ctrl_en : STD_LOGIC; + SIGNAL init_rrxpcsclkpwdn : STD_LOGIC; + SIGNAL init_rerr_flags_sel : STD_LOGIC; + + -- PCS Per Channel RX Control Register 19 for Channel 0 + SIGNAL init_rwait_count : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL init_reserved_0_TB23 : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- PCS Per Channel RX Control Register 20 for Channel 0 + SIGNAL init_rfts_count : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL init_rwait_for_phfifo_cnt : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 21 for Channel 0 + SIGNAL init_rppm_meas_delay : STD_LOGIC; + SIGNAL init_rcid_len_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL init_rcid_pattern_rx : STD_LOGIC; + SIGNAL init_rpcs_wrapback_en : STD_LOGIC; + SIGNAL init_reserved_0_TB25 : STD_LOGIC_VECTOR(4 DOWNTO 0); + + -- PCS Per Channel RX Control Register 22 for Channel 0 + SIGNAL init_rauto_pc_en_cnt : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_reserved_1_TB26 : STD_LOGIC; + SIGNAL init_rauto_deassert_pc_rst_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL init_reserved_0_TB26 : STD_LOGIC; + SIGNAL init_rpipeline_bypass_rx : STD_LOGIC; + SIGNAL init_rself_sw_en_rx : STD_LOGIC; + SIGNAL init_rrxvalid_mask : STD_LOGIC; + SIGNAL init_rcid_en : STD_LOGIC; + SIGNAL init_rphfifo_regmode_rx : STD_LOGIC; + + -- PCS Per Channel RX Control Register 23 for Channel 0 + SIGNAL init_rmask_count : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL init_rgen1_sigdet_ena : STD_LOGIC; + SIGNAL init_riei_eios_priority_dis : STD_LOGIC; + SIGNAL init_reserved_0_TB27 : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- --------------------------------------------------------------------------- + -- CRAM + -- --------------------------------------------------------------------------- + -- Existing + SIGNAL cram_dskwclksel: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_is_lane0: STD_LOGIC; + SIGNAL cram_rbist_sel: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rbitslip_size: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rclkcmppos: STD_LOGIC; + SIGNAL cram_rcxpat_chnl_en: STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rdskchrp: STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL cram_rdskposdisp: STD_LOGIC; + SIGNAL cram_rendec_data_sel_rx: STD_LOGIC; + SIGNAL cram_rforce0_freqdet: STD_LOGIC; + SIGNAL cram_rforce1_freqdet: STD_LOGIC; + SIGNAL cram_rindv_rx: STD_LOGIC; + SIGNAL cram_rphfifo_master_sel_rx: STD_LOGIC; + SIGNAL cram_rpma_doublewidth_rx: STD_LOGIC; + SIGNAL cram_rpmadwidth_rx: STD_LOGIC; + SIGNAL cram_rppm_cnt_reset: STD_LOGIC; + SIGNAL cram_rppmsel: STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL cram_rprbs_sel: STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL cram_rrdwidth_rx: STD_LOGIC; -- rx only + SIGNAL cram_rrx_revlb_sw: STD_LOGIC; + SIGNAL cram_rs_lpbk: STD_LOGIC; + SIGNAL cram_rtx_elec_idle_delay: STD_LOGIC_VECTOR(1 DOWNTO 0); -- rx only + SIGNAL cram_rtx_pipe_enable: STD_LOGIC; + SIGNAL cram_scan_mode: STD_LOGIC; + SIGNAL cram_sel_gp_md: STD_LOGIC; + + -- Existing (2) + SIGNAL dprioin_renpolinv_en: STD_LOGIC; + SIGNAL cram_renpolinv_en: STD_LOGIC; + SIGNAL init_rmaster_rx: STD_LOGIC; + SIGNAL dprioin_rmaster_rx: STD_LOGIC; + SIGNAL cram_rmaster_rx: STD_LOGIC; + SIGNAL init_rmaster_up_rx: STD_LOGIC; + SIGNAL dprioin_rmaster_up_rx: STD_LOGIC; + SIGNAL cram_rmaster_up_rx: STD_LOGIC; + SIGNAL init_rphfifourstenrx: STD_LOGIC; + SIGNAL dprioin_rphfifourstenrx: STD_LOGIC; + SIGNAL cram_rphfifourstenrx: STD_LOGIC; + SIGNAL init_rppm_gen1_2xcnt_en: STD_LOGIC; + SIGNAL dprioin_rppm_gen1_2xcnt_en: STD_LOGIC; + SIGNAL cram_rppm_gen1_2xcnt_en: STD_LOGIC; + SIGNAL init_rppm_post_eidle_del: STD_LOGIC; + SIGNAL dprioin_rppm_post_eidle_del: STD_LOGIC; + SIGNAL cram_rppm_post_eidle_del: STD_LOGIC; + SIGNAL init_rrx_fifo_dis: STD_LOGIC; + SIGNAL dprioin_rrx_fifo_dis: STD_LOGIC; + SIGNAL cram_rrx_fifo_dis: STD_LOGIC; + + -- PCS Per Channel RX Control Register 1 for Channel 0 + SIGNAL cram_rrxpcsbypass_en : STD_LOGIC; + SIGNAL cram_rall_one_dect_only : STD_LOGIC; + SIGNAL cram_rbist_clr_rx : STD_LOGIC; + SIGNAL cram_rbisten_rx : STD_LOGIC; + SIGNAL cram_rprbs_clr_rslt_rx : STD_LOGIC; + SIGNAL cram_rprbsen_rx : STD_LOGIC; + SIGNAL cram_rrx_rd_clk_sel : STD_LOGIC; + SIGNAL cram_rclk_2_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rclk_1_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rrcvd_clk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rfreerun_rx : STD_LOGIC; + SIGNAL cram_rrxurstpcs : STD_LOGIC; + SIGNAL cram_reserved_0_TB5 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 2 for Channel 0 + SIGNAL cram_rcomp_pat_32 : STD_LOGIC; + SIGNAL cram_rcomp_pat_33 : STD_LOGIC; + SIGNAL cram_rcomp_pat_34 : STD_LOGIC; + SIGNAL cram_rcomp_pat_35 : STD_LOGIC; + SIGNAL cram_rcomp_pat_36 : STD_LOGIC; + SIGNAL cram_rcomp_pat_37 : STD_LOGIC; + SIGNAL cram_rcomp_pat_38 : STD_LOGIC; + SIGNAL cram_rcomp_pat_39 : STD_LOGIC; + SIGNAL cram_rcomp_size : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL cram_rcomp_pat_porn : STD_LOGIC; + SIGNAL cram_rdis_rx_disp : STD_LOGIC; + SIGNAL cram_rencdt_rising : STD_LOGIC; + SIGNAL cram_resync_badcg_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- PCS Per Channel RX Control Register 3 for Channel 0 + SIGNAL cram_rcomp_pat_16 : STD_LOGIC; + SIGNAL cram_rcomp_pat_17 : STD_LOGIC; + SIGNAL cram_rcomp_pat_18 : STD_LOGIC; + SIGNAL cram_rcomp_pat_19 : STD_LOGIC; + SIGNAL cram_rcomp_pat_20 : STD_LOGIC; + SIGNAL cram_rcomp_pat_21 : STD_LOGIC; + SIGNAL cram_rcomp_pat_22 : STD_LOGIC; + SIGNAL cram_rcomp_pat_23 : STD_LOGIC; + SIGNAL cram_rcomp_pat_24 : STD_LOGIC; + SIGNAL cram_rcomp_pat_25 : STD_LOGIC; + SIGNAL cram_rcomp_pat_26 : STD_LOGIC; + SIGNAL cram_rcomp_pat_27 : STD_LOGIC; + SIGNAL cram_rcomp_pat_28 : STD_LOGIC; + SIGNAL cram_rcomp_pat_29 : STD_LOGIC; + SIGNAL cram_rcomp_pat_30 : STD_LOGIC; + SIGNAL cram_rcomp_pat_31 : STD_LOGIC; + + -- PCS Per Channel RX Control Register 4 for Channel 0 + SIGNAL cram_rcomp_pat_0 : STD_LOGIC; + SIGNAL cram_rcomp_pat_1 : STD_LOGIC; + SIGNAL cram_rcomp_pat_2 : STD_LOGIC; + SIGNAL cram_rcomp_pat_3 : STD_LOGIC; + SIGNAL cram_rcomp_pat_4 : STD_LOGIC; + SIGNAL cram_rcomp_pat_5 : STD_LOGIC; + SIGNAL cram_rcomp_pat_6 : STD_LOGIC; + SIGNAL cram_rcomp_pat_7 : STD_LOGIC; + SIGNAL cram_rcomp_pat_8 : STD_LOGIC; + SIGNAL cram_rcomp_pat_9 : STD_LOGIC; + SIGNAL cram_rcomp_pat_10 : STD_LOGIC; + SIGNAL cram_rcomp_pat_11 : STD_LOGIC; + SIGNAL cram_rcomp_pat_12 : STD_LOGIC; + SIGNAL cram_rcomp_pat_13 : STD_LOGIC; + SIGNAL cram_rcomp_pat_14 : STD_LOGIC; + SIGNAL cram_rcomp_pat_15 : STD_LOGIC; + + SIGNAL cram_rcomp_pat : STD_LOGIC_VECTOR(39 DOWNTO 0); + + -- PCS Per Channel RX Control Register 5 for Channel 0 + SIGNAL cram_rbitloc_rev_en : STD_LOGIC; + SIGNAL cram_rbysync_polinv_en : STD_LOGIC; + SIGNAL cram_rwa_6g_en : STD_LOGIC; + SIGNAL cram_rosnumber : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rosbased : STD_LOGIC; + SIGNAL cram_rkchar : STD_LOGIC; + SIGNAL cram_renumber : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL cram_rib_inv_cd : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rsync_sm_dis : STD_LOGIC; + + -- PCS Per Channel RX Control Register 6 for Channel 0 + SIGNAL cram_rknumber : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL cram_rgnumber : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- PCS Per Channel RX Control Register 7 for Channel 0 + SIGNAL cram_renpolinv_rx : STD_LOGIC; + SIGNAL cram_rcascaded_8b10b_en_rx : STD_LOGIC; + SIGNAL cram_r8b10b_dec_ibm_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rendec_rx : STD_LOGIC; + SIGNAL cram_rautobtalg_dis : STD_LOGIC; + SIGNAL cram_rrlv_en : STD_LOGIC; + SIGNAL cram_rlp20ben : STD_LOGIC; + SIGNAL cram_rforce_sig_det_pcs : STD_LOGIC; + SIGNAL cram_rbyte_rev_en : STD_LOGIC; + SIGNAL cram_rrundisp : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 8 for Channel 0 + SIGNAL cram_rclkcmpsq1p_0 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_1 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_2 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_3 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_4 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_5 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_6 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_7 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_8 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_9 : STD_LOGIC; + SIGNAL cram_rclkcmpsqmd : STD_LOGIC; + SIGNAL cram_rclkcmpinsertpad : STD_LOGIC; + SIGNAL cram_rtruebac2bac : STD_LOGIC; + SIGNAL cram_rskpsetbased : STD_LOGIC; + SIGNAL cram_rgenericfifo : STD_LOGIC; + SIGNAL cram_rmatchen : STD_LOGIC; + + -- PCS Per Channel RX Control Register 9 for Channel 0 + SIGNAL cram_rclkcmpsq1p_10 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_11 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_12 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_13 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_14 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_15 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_16 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_17 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_18 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1p_19 : STD_LOGIC; + SIGNAL cram_reserved_0_TB13 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_15 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_16 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_17 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_18 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_19 : STD_LOGIC; + + SIGNAL cram_rclkcmpsq1p : STD_LOGIC_VECTOR(19 DOWNTO 0); + + -- PCS Per Channel RX Control Register 10 for Channel 0 + SIGNAL cram_rclkcmpsq1n_0 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_1 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_2 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_3 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_4 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_5 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_6 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_7 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_8 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_9 : STD_LOGIC; + SIGNAL cram_reserved_0_TB14 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_10 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_11 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_12 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_13 : STD_LOGIC; + SIGNAL cram_rclkcmpsq1n_14 : STD_LOGIC; + + SIGNAL cram_rclkcmpsq1n : STD_LOGIC_VECTOR(19 DOWNTO 0); + + -- PCS Per Channel RX Control Register 11 for Channel 0 + SIGNAL cram_rfull_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cram_rdel_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cram_rins_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cram_rclkcmp_pipe_en : STD_LOGIC; + + -- PCS Per Channel RX Control Register 12 for Channel 0 + SIGNAL cram_rfreq_sel : STD_LOGIC; + SIGNAL cram_rauto_speed_ena : STD_LOGIC; + SIGNAL cram_rhip_ena : STD_LOGIC; + SIGNAL cram_rpma_done_gen_ena : STD_LOGIC; + SIGNAL cram_rpma_done_count_16 : STD_LOGIC; + SIGNAL cram_rpma_done_count_17 : STD_LOGIC; + SIGNAL cram_reserved_0_TB16 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL cram_rstart_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL cram_rempty_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- PCS Per Channel RX Control Register 13 for Channel 0 + SIGNAL cram_rtest_bus_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL cram_rautoinsdis : STD_LOGIC; + SIGNAL cram_rphfifopldenrx : STD_LOGIC; + SIGNAL cram_rbytordplden : STD_LOGIC; + SIGNAL cram_rbyteorden : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rbytord_2sym_en : STD_LOGIC; + SIGNAL cram_rinvalid_code_err_only : STD_LOGIC; + SIGNAL cram_rcmpfifourst : STD_LOGIC; + SIGNAL cram_rphfifourstrx : STD_LOGIC; + SIGNAL cram_rdwidth_rx : STD_LOGIC; + SIGNAL cram_rrxfifo_lowlatency_en : STD_LOGIC; + SIGNAL cram_rrxfifo_dis : STD_LOGIC; + + -- PCS Per Channel RX Control Register 14 for Channel 0 + SIGNAL cram_rbytordpat_0 : STD_LOGIC; + SIGNAL cram_rbytordpat_1 : STD_LOGIC; + SIGNAL cram_rbytordpat_2 : STD_LOGIC; + SIGNAL cram_rbytordpat_3 : STD_LOGIC; + SIGNAL cram_rbytordpat_4 : STD_LOGIC; + SIGNAL cram_rbytordpat_5 : STD_LOGIC; + SIGNAL cram_rbytordpat_6 : STD_LOGIC; + SIGNAL cram_rbytordpat_7 : STD_LOGIC; + SIGNAL cram_rbytordpat_8 : STD_LOGIC; + SIGNAL cram_rbytordpat_9 : STD_LOGIC; + SIGNAL cram_reserved_0_TB18 : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 15 for Channel 0 + SIGNAL cram_rbytordpad : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL cram_reserved_0_TB19 : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 16 for Channel 0 + SIGNAL cram_rload_shreg_del : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cram_rphystatus_rst_toggle : STD_LOGIC; + SIGNAL cram_reidle_com_detect : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rk285detect : STD_LOGIC; + SIGNAL cram_reidleinferenable : STD_LOGIC; + SIGNAL cram_rphystatus_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL cram_rind_error_reporting : STD_LOGIC; + SIGNAL cram_rrx_detect_bypass : STD_LOGIC; + SIGNAL cram_rrx_pipe_enable : STD_LOGIC; + + -- PCS Per Channel RX Control Register 17 for Channel 0 + SIGNAL cram_rpma_done_count_0 : STD_LOGIC; + SIGNAL cram_rpma_done_count_1 : STD_LOGIC; + SIGNAL cram_rpma_done_count_2 : STD_LOGIC; + SIGNAL cram_rpma_done_count_3 : STD_LOGIC; + SIGNAL cram_rpma_done_count_4 : STD_LOGIC; + SIGNAL cram_rpma_done_count_5 : STD_LOGIC; + SIGNAL cram_rpma_done_count_6 : STD_LOGIC; + SIGNAL cram_rpma_done_count_7 : STD_LOGIC; + SIGNAL cram_rpma_done_count_8 : STD_LOGIC; + SIGNAL cram_rpma_done_count_9 : STD_LOGIC; + SIGNAL cram_rpma_done_count_10 : STD_LOGIC; + SIGNAL cram_rpma_done_count_11 : STD_LOGIC; + SIGNAL cram_rpma_done_count_12 : STD_LOGIC; + SIGNAL cram_rpma_done_count_13 : STD_LOGIC; + SIGNAL cram_rpma_done_count_14 : STD_LOGIC; + SIGNAL cram_rpma_done_count_15 : STD_LOGIC; + + SIGNAL cram_rpma_done_count : STD_LOGIC_VECTOR(17 DOWNTO 0); + + -- PCS Per Channel RX Control Register 18 for Channel 0 + SIGNAL cram_rbytordpat_10 : STD_LOGIC; + SIGNAL cram_rbytordpat_11 : STD_LOGIC; + SIGNAL cram_rbytordpat_12 : STD_LOGIC; + SIGNAL cram_rbytordpat_13 : STD_LOGIC; + SIGNAL cram_rbytordpat_14 : STD_LOGIC; + SIGNAL cram_rbytordpat_15 : STD_LOGIC; + SIGNAL cram_rbytordpat_16 : STD_LOGIC; + SIGNAL cram_rbytordpat_17 : STD_LOGIC; + SIGNAL cram_rbytordpat_18 : STD_LOGIC; + SIGNAL cram_rbytordpat_19 : STD_LOGIC; + SIGNAL cram_rbytord_6g_mask_en : STD_LOGIC; + SIGNAL cram_rbytord_s2gx : STD_LOGIC; + SIGNAL cram_reserved_0_TB22 : STD_LOGIC; + SIGNAL cram_rcdr_ctrl_en : STD_LOGIC; + SIGNAL cram_rrxpcsclkpwdn : STD_LOGIC; + SIGNAL cram_rerr_flags_sel : STD_LOGIC; + + SIGNAL cram_rbytordpat : STD_LOGIC_VECTOR(19 DOWNTO 0); + + -- PCS Per Channel RX Control Register 19 for Channel 0 + SIGNAL cram_rwait_count : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL cram_reserved_0_TB23 : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- PCS Per Channel RX Control Register 20 for Channel 0 + SIGNAL cram_rfts_count : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL cram_rwait_for_phfifo_cnt : STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- PCS Per Channel RX Control Register 21 for Channel 0 + SIGNAL cram_rppm_meas_delay : STD_LOGIC; + SIGNAL cram_rcid_len_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL cram_rcid_pattern_rx : STD_LOGIC; + SIGNAL cram_rpcs_wrapback_en : STD_LOGIC; + SIGNAL cram_reserved_0_TB25 : STD_LOGIC_VECTOR(4 DOWNTO 0); + + -- PCS Per Channel RX Control Register 22 for Channel 0 + SIGNAL cram_rauto_pc_en_cnt : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cram_reserved_1_TB26 : STD_LOGIC; + SIGNAL cram_rauto_deassert_pc_rst_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL cram_reserved_0_TB26 : STD_LOGIC; + SIGNAL cram_rpipeline_bypass_rx : STD_LOGIC; + SIGNAL cram_rself_sw_en_rx : STD_LOGIC; + SIGNAL cram_rrxvalid_mask : STD_LOGIC; + SIGNAL cram_rcid_en : STD_LOGIC; + SIGNAL cram_rphfifo_regmode_rx : STD_LOGIC; + + -- PCS Per Channel RX Control Register 23 for Channel 0 + SIGNAL cram_rmask_count : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL cram_rgen1_sigdet_ena : STD_LOGIC; + SIGNAL cram_riei_eios_priority_dis : STD_LOGIC; + SIGNAL cram_reserved_0_TB27 : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- new dprio model end -- + + --/////////////////////////////////////////////////////////////////////////// + -- sub-block interface: pcs_reset (pr) -----------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + SIGNAL pr_in_hard_reset : STD_LOGIC; + SIGNAL pr_in_clk_2_b : STD_LOGIC; + SIGNAL pr_in_refclk_b_in : STD_LOGIC; + SIGNAL pr_in_scan_mode : STD_LOGIC; + SIGNAL pr_in_rxpcs_rst : STD_LOGIC; + SIGNAL pr_in_txpcs_rst : STD_LOGIC; + + SIGNAL pr_out_rxrst_int : STD_LOGIC; + SIGNAL pr_out_txrst_int : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- sub-block interface: chnl_hip_spt -------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + SIGNAL hs_in_eidleinfersel_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_hip_eidleinfersel_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_hip_powerdown_ch : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hs_in_hip_rate : STD_LOGIC; + SIGNAL hs_in_hip_rxpolarity : STD_LOGIC; + SIGNAL hs_in_hip_txd_ch : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL hs_in_hip_txdeemph : STD_LOGIC; + SIGNAL hs_in_hip_txdetectrxloopback : STD_LOGIC; + SIGNAL hs_in_hip_txelecidle : STD_LOGIC; + SIGNAL hs_in_hip_txmargin_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_pcs_phystatus : STD_LOGIC; + SIGNAL hs_in_pcs_rxd_ch : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL hs_in_pcs_rxelecidle : STD_LOGIC; + SIGNAL hs_in_pcs_rxstatus_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_pcs_rxvalid : STD_LOGIC; + SIGNAL hs_in_powerdown_ch : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hs_in_rate : STD_LOGIC; + SIGNAL hs_in_rhip_ena : STD_LOGIC; + SIGNAL hs_in_rxpolarity : STD_LOGIC; + SIGNAL hs_in_txd_ch : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL hs_in_txdeemph : STD_LOGIC; + SIGNAL hs_in_txdetectrxloopback : STD_LOGIC; + SIGNAL hs_in_txmargin_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_in_txpma_local_clk : STD_LOGIC; + + SIGNAL hs_out_hip_phystatus : STD_LOGIC; + SIGNAL hs_out_hip_rxd_ch : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL hs_out_hip_rxelecidle : STD_LOGIC; + SIGNAL hs_out_hip_rxstatus_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_hip_rxvalid : STD_LOGIC; + SIGNAL hs_out_hip_tx_clk : STD_LOGIC; + SIGNAL hs_out_pcs_eidleinfersel_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_pcs_powerdown_ch : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hs_out_pcs_rate : STD_LOGIC; --feed rx0.pcs_rate to cmu + SIGNAL hs_out_pcs_rxpolarity : STD_LOGIC; + SIGNAL hs_out_pcs_txd_ch : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL hs_out_pcs_txdeemph : STD_LOGIC; + SIGNAL hs_out_pcs_txdetectrxloopback : STD_LOGIC; + SIGNAL hs_out_pcs_txmargin_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_phystatus : STD_LOGIC; + SIGNAL hs_out_rxd_ch : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL hs_out_rxelecidle : STD_LOGIC; + SIGNAL hs_out_rxstatus_ch : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL hs_out_rxvalid : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- sub-block interface: pipe_interface (pi) ------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + SIGNAL pi_in_pipe_rx_clk : STD_LOGIC; -- beginning input + SIGNAL pi_in_pipe_tx_clk : STD_LOGIC; + SIGNAL pi_in_polinv_rx : STD_LOGIC; + SIGNAL pi_in_power_state_transition_done : STD_LOGIC; + SIGNAL pi_in_power_state_transition_done_ena : STD_LOGIC; + SIGNAL pi_in_powerdown : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL pi_in_refclk_b : STD_LOGIC; + SIGNAL pi_in_refclk_b_reset : STD_LOGIC; + SIGNAL pi_in_revloopback : STD_LOGIC; + SIGNAL pi_in_rx_detect_valid : STD_LOGIC; + SIGNAL pi_in_rx_found : STD_LOGIC; + SIGNAL pi_in_rx_pipe_reset : STD_LOGIC; + SIGNAL pi_in_rxbeacon : STD_LOGIC; + SIGNAL pi_in_rxd : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL pi_in_rxelectricalidle : STD_LOGIC; + SIGNAL pi_in_rxpolarity : STD_LOGIC; + SIGNAL pi_in_tx_elec_idle_comp : STD_LOGIC; + SIGNAL pi_in_tx_pipe_reset : STD_LOGIC; + SIGNAL pi_in_txcompliance : STD_LOGIC; + SIGNAL pi_in_txd_ch : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL pi_in_txdetectrxloopback : STD_LOGIC; + SIGNAL pi_in_txelecidle : STD_LOGIC; + SIGNAL pi_in_powerstatein : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL pi_in_txdetectrxin : STD_LOGIC; + + -- new cycloneiv input interfaces - ww26.5 + SIGNAL pi_in_speed_change : STD_LOGIC; -- from rx_digi - Auto Speed Negotiation Module + SIGNAL pi_in_txdeemph : STD_LOGIC; -- tx_only + SIGNAL pi_in_txmargin : STD_LOGIC_VECTOR(2 DOWNTO 0); -- tx only + SIGNAL pi_in_txswing : STD_LOGIC; -- tx only + + -- ww47 input interfaces + SIGNAL pi_in_speed_change_centrl : STD_LOGIC; + SIGNAL pi_in_speed_change_quad_up : STD_LOGIC; + SIGNAL pi_in_speed_change_quad_down : STD_LOGIC; + + -- ww25.2008 + SIGNAL pi_in_sigdetni : STD_LOGIC; + + SIGNAL pi_out_phystatus : STD_LOGIC; -- beginning output + SIGNAL pi_out_sim_state_transition_done : STD_LOGIC; + SIGNAL pi_out_polinv_rx_int : STD_LOGIC; + SIGNAL pi_out_powerstate : STD_LOGIC_VECTOR(3 DOWNTO 0); -- to both cmu and rx + SIGNAL pi_out_rev_loopbk : STD_LOGIC; + SIGNAL pi_out_rxd_ch : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL pi_out_rxelecidle : STD_LOGIC; + SIGNAL pi_out_rxstatus : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL pi_out_rxvalid : STD_LOGIC; + SIGNAL pi_out_tx_elec_idle : STD_LOGIC; + SIGNAL pi_out_txbeacon : STD_LOGIC; + SIGNAL pi_out_txd : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL pi_out_txdetectrx : STD_LOGIC; + + -- new cycloneiv output interfaces - ww26.5 + SIGNAL pi_out_txdeemph_int : STD_LOGIC; --tx only + SIGNAL pi_out_txmargin_int : STD_LOGIC_VECTOR(2 DOWNTO 0); --tx only + SIGNAL pi_out_txswing_int : STD_LOGIC; --tx only + + -- ignoring crams + SIGNAL tmp_cram_rtx_elec_idle_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); -- tx_only + SIGNAL tmp_cram_rtxswing_sel_ena : STD_LOGIC; -- tx_only + + --/////////////////////////////////////////////////////////////////////////// + -- sub-block interface: rx_digi (rd) -------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + SIGNAL rd_in_a1a2_size : STD_LOGIC; -- begin input + SIGNAL rd_in_align_status : STD_LOGIC; + SIGNAL rd_in_align_status_sync_0 : STD_LOGIC; + SIGNAL rd_in_align_status_sync_2 : STD_LOGIC; + SIGNAL rd_in_bitloc_rev_en : STD_LOGIC; + SIGNAL rd_in_bitslip : STD_LOGIC; + SIGNAL rd_in_byte_rev_en : STD_LOGIC; + SIGNAL rd_in_bytordpld : STD_LOGIC; + SIGNAL rd_in_clklow : STD_LOGIC; + SIGNAL rd_in_cmpfifourst : STD_LOGIC; + SIGNAL rd_in_en_dskw_gp : STD_LOGIC; + SIGNAL rd_in_en_dskw_qd : STD_LOGIC; + SIGNAL rd_in_encdt : STD_LOGIC; + SIGNAL rd_in_encoder_testbus : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL rd_in_fifo_rd_in_comp_0 : STD_LOGIC; + SIGNAL rd_in_fifo_rd_in_comp_2 : STD_LOGIC; + SIGNAL rd_in_fifo_rst_rd_gp : STD_LOGIC; + SIGNAL rd_in_fifo_rst_rd_qd : STD_LOGIC; + SIGNAL rd_in_fref : STD_LOGIC; + SIGNAL rd_in_hard_reset : STD_LOGIC; + SIGNAL rd_in_phfifourst_rx : STD_LOGIC; + SIGNAL rd_in_pld_rx_clk : STD_LOGIC; + SIGNAL rd_in_pma_testbus : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rd_in_polinv_rx : STD_LOGIC; + SIGNAL rd_in_pudi : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL rd_in_rcvd_clk_pma : STD_LOGIC; + SIGNAL rd_in_rcvd_clk0_pma : STD_LOGIC; + SIGNAL rd_in_rdenable_rmf : STD_LOGIC; + SIGNAL rd_in_rdenable_rx : STD_LOGIC; + SIGNAL rd_in_refclk_pma : STD_LOGIC; + SIGNAL rd_in_rx_control_rs : STD_LOGIC; + SIGNAL rd_in_rx_data_rs : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rd_in_rxpma_rst : STD_LOGIC; + SIGNAL rd_in_rxpcs_rst : STD_LOGIC; + SIGNAL rd_in_sigdetni : STD_LOGIC; + SIGNAL rd_in_tx_ctrl_testbus : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL rd_in_txlp20b : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL rd_in_txpma_local_clk : STD_LOGIC; + SIGNAL rd_in_wrdisable_rx : STD_LOGIC; + SIGNAL rd_in_wrenable_rmf : STD_LOGIC; + + -- new input interfaces in CYCLONEIV - ww26.5 + -- WYS (eidleinfersel) + SIGNAL rd_in_eidleinfersel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Electrical Idle inference mechanism select + -- WYS (rateswitchdone) + SIGNAL rd_in_gen2ngen1 : STD_LOGIC; -- frequency switch done from PMA (rising edge of old clock to rising edge of new clock) + -- WYS (rateswitchxndone) + SIGNAL rd_in_gen2ngen1_bundle : STD_LOGIC; -- for bundle + --to rx_ctrl and grouped with rxstatus_int,rxvalid_int as pipe_status_in + --impact the out phystatus + --from: rx_pipe + SIGNAL rd_in_phystatus_int : STD_LOGIC; + --from pma to auto_negotiation + --from top feeding to both rx and tx_pcs. + SIGNAL rd_in_powerdown : STD_LOGIC_VECTOR(1 DOWNTO 0); + --from tx_ctrl - WYS (rateswitch) + -- WYS (rxelecidlerateswitch) + --from rx_pipe feeding to rx_ctrl + SIGNAL rd_in_rxstatus_int : STD_LOGIC_VECTOR(2 DOWNTO 0); + --from rx_pipe feeding to rx_ctrl + SIGNAL rd_in_rxvalid_int : STD_LOGIC; + + -- ww47 RTL update - input interfaces ------------------------------------ + SIGNAL rd_in_rate : STD_LOGIC; -- rate change output from upper layers. // from digi_chnl_support + + -- CDR control + SIGNAL rd_in_pld_ltr : STD_LOGIC; -- PLD control of the CDR when rcdr_ctrl_en = 1'b0 + SIGNAL rd_in_prbs_cid_en : STD_LOGIC; -- PLD control of PRBS-CID enable + + -- new signal inputs for bundling + SIGNAL rd_in_rx_div2_sync_in_centrl : STD_LOGIC; + SIGNAL rd_in_rx_div2_sync_in_quad_up : STD_LOGIC; + SIGNAL rd_in_rx_div2_sync_in_quad_down : STD_LOGIC; + SIGNAL rd_in_reset_pc_ptrs_in_centrl : STD_LOGIC; + SIGNAL rd_in_reset_pc_ptrs_in_quad_up : STD_LOGIC; + SIGNAL rd_in_reset_pc_ptrs_in_quad_down : STD_LOGIC; + SIGNAL rd_in_wr_enable_in_centrl : STD_LOGIC; + SIGNAL rd_in_wr_enable_in_quad_up : STD_LOGIC; + SIGNAL rd_in_wr_enable_in_quad_down : STD_LOGIC; + SIGNAL rd_in_rd_enable_in_centrl : STD_LOGIC; + SIGNAL rd_in_rd_enable_in_quad_up : STD_LOGIC; + SIGNAL rd_in_rd_enable_in_quad_down : STD_LOGIC; + SIGNAL rd_in_rx_we_in_centrl : STD_LOGIC; + SIGNAL rd_in_rx_we_in_quad_up : STD_LOGIC; + SIGNAL rd_in_rx_we_in_quad_down : STD_LOGIC; + + SIGNAL rd_in_speed_change_in_centrl : STD_LOGIC; -- up/down signals are in pipe_top_interface + + -- pipeline inputs for bundling + SIGNAL rd_in_rx_div2_sync_in_pipe_quad_up : STD_LOGIC; + SIGNAL rd_in_rx_div2_sync_in_pipe_quad_down : STD_LOGIC; + SIGNAL rd_in_reset_pc_ptrs_in_pipe_quad_up : STD_LOGIC; + SIGNAL rd_in_reset_pc_ptrs_in_pipe_quad_down : STD_LOGIC; + SIGNAL rd_in_wr_enable_in_pipe_quad_up : STD_LOGIC; + SIGNAL rd_in_wr_enable_in_pipe_quad_down : STD_LOGIC; + SIGNAL rd_in_rd_enable_in_pipe_quad_up : STD_LOGIC; + SIGNAL rd_in_rd_enable_in_pipe_quad_down : STD_LOGIC; + SIGNAL rd_in_rx_we_in_pipe_quad_up : STD_LOGIC; + SIGNAL rd_in_rx_we_in_pipe_quad_down : STD_LOGIC; + SIGNAL rd_in_speed_change_in_pipe_quad_up : STD_LOGIC; + SIGNAL rd_in_speed_change_in_pipe_quad_down : STD_LOGIC; + -- Bundle Mode Inputs for config_sel + SIGNAL rd_in_config_sel_centrl : STD_LOGIC; + SIGNAL rd_in_config_sel_quad_up : STD_LOGIC; + SIGNAL rd_in_config_sel_quad_down : STD_LOGIC; + + -- output interfaces ----------------------------------------------------- + SIGNAL rd_out_a1a2_k1k2_flag : STD_LOGIC_VECTOR(3 DOWNTO 0); -- begin output + SIGNAL rd_out_align_det_sync : STD_LOGIC; + SIGNAL rd_out_align_status_sync : STD_LOGIC; + SIGNAL rd_out_almost_fl_rmf : STD_LOGIC; + SIGNAL rd_out_almost_mt_rmf : STD_LOGIC; + SIGNAL rd_out_bistdone : STD_LOGIC; + SIGNAL rd_out_bisterr : STD_LOGIC; + SIGNAL rd_out_byteord_flag : STD_LOGIC; + SIGNAL rd_out_cg_comma : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rd_out_chnl_test_bus_out : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL rd_out_clk_2_b : STD_LOGIC; + SIGNAL rd_out_dec_ctl : STD_LOGIC; + SIGNAL rd_out_dec_data : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rd_out_dec_data_valid : STD_LOGIC; + SIGNAL rd_out_empty_rmf : STD_LOGIC; + SIGNAL rd_out_empty_rx : STD_LOGIC; + SIGNAL rd_out_err_ctl : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rd_out_err_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL rd_out_fifo_rd_out_comp : STD_LOGIC; + SIGNAL rd_out_freq_lock : STD_LOGIC; + SIGNAL rd_out_full_rmf : STD_LOGIC; + SIGNAL rd_out_full_rx : STD_LOGIC; + SIGNAL rd_out_prbs_done : STD_LOGIC; + SIGNAL rd_out_prbs_err_lt : STD_LOGIC; + SIGNAL rd_out_rcvd_clk_pma_b : STD_LOGIC; + SIGNAL rd_out_rd_align : STD_LOGIC; + SIGNAL rd_out_rev_loop_data : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL rd_out_rlv : STD_LOGIC; + SIGNAL rd_out_rlv_lt : STD_LOGIC; + SIGNAL rd_out_running_disp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rd_out_rx_clk : STD_LOGIC; + SIGNAL rd_out_rx_pipe_clk : STD_LOGIC; + SIGNAL rd_out_rx_pipe_soft_reset : STD_LOGIC; + SIGNAL rd_out_rxd : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rd_out_selftest_done : STD_LOGIC; + SIGNAL rd_out_selftest_err : STD_LOGIC; + SIGNAL rd_out_signal_detect_out : STD_LOGIC; + SIGNAL rd_out_sync_status : STD_LOGIC; + + -- new output interfaces - ww26.5 + --from auto_speed_neg to nowhere + --from auto_speed_neg to nowhere to tx_digi (tx_ctrl) + -- to PLD + + SIGNAL rd_out_phystatus : STD_LOGIC; + --to PIPE's rxd (UPDATE) + SIGNAL rd_out_pipe_data : STD_LOGIC_VECTOR(63 DOWNTO 0); + -- from rx_ctrl to:nowhere + SIGNAL rd_out_soft_reset_rclk1 : STD_LOGIC; -- Synchronized reset + --from auto_speed_neg to nowhere to rx_pipe + SIGNAL rd_out_speed_change : STD_LOGIC; -- speed change done to PIPE interface (i.e. auto negotiation done) + --from electrial_idle_inference_module to PCS_TOP + + --from electrial_idle_inference_module to rx_pipe + SIGNAL rd_out_rxelecidle_int : STD_LOGIC; -- Asserted when Electrical Idle is detected + --to PLD + SIGNAL rd_out_rxstatus : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rd_out_rxvalid : STD_LOGIC; + -- values greater than 2 entails that syncstatus is used + + -- ww47 RTL output interfaces ------------------------------------------------- + + -- to PLD and then back to tx_boundary_sel of tx_pcs + SIGNAL rd_out_wa_boundary : STD_LOGIC_VECTOR(4 DOWNTO 0); --describes word boundary + + -- CDR control + SIGNAL rd_out_early_eios : STD_LOGIC; -- Asserted when K_I or K_X_I is detected on the incoming data + -- to PLD + + SIGNAL rd_out_ltr : STD_LOGIC; -- force CDR to LTR mode - to RX_PMA? + + -- new outputs for bundling and auto speed + SIGNAL rd_out_rx_div2_sync_out_pipe : STD_LOGIC; + SIGNAL rd_out_rx_we_out_pipe : STD_LOGIC; + SIGNAL rd_out_wr_enable_out_pipe : STD_LOGIC; + SIGNAL rd_out_rd_enable_out_pipe : STD_LOGIC; + SIGNAL rd_out_reset_pc_ptrs_out_pipe : STD_LOGIC; + SIGNAL rd_out_speed_change_out_pipe : STD_LOGIC; + SIGNAL rd_out_dis_pc_byte : STD_LOGIC; -- from auto_speed_neg and feed to digi_tx + SIGNAL rd_out_reset_pc_ptrs : STD_LOGIC; -- from auto_speed_neg and feed to digi_tx + SIGNAL rd_out_pcie_switch : STD_LOGIC; + + -- ww12 interfaces -------------------------------------------------------- + --feeding to cdr_ctrl and eii_module + --from rev_loopbk of tx_pipe_interface; + --tx_digi.rev_loopbk <= tx_pipe_interface.rev_loopback; (ww12 WYS todo: adding rev_loopback output port at tx_pcs) + --rx_digi.pipe_loopbk <= tx_pipe_interface.rev_loopback; (ww12 WYS todo: adding pipe_loopback input port at rx_pcs) + -- reverse parallel loopback requires 4 EIOS to be transmitted up to the upper layer. + --Used in the CDR control block and electrical idle inference module + SIGNAL rd_in_pipe_loopbk : STD_LOGIC; + + -- XAUI related ports + -- from rate_match to rate_match to achieve all channel rd/wr at same time + -- Full connection rx[i].cg_comp_rd_d_chj <= rx[j].cg_comp_rd_out + -- for Quartus simulation: using its own ptrs since we do not model delays + SIGNAL rd_out_cg_comp_rd_d_out : STD_LOGIC; + SIGNAL rd_out_cg_comp_wr_out : STD_LOGIC; + + SIGNAL rd_in_cg_comp_rd_d_ch0 : STD_LOGIC; + SIGNAL rd_in_cg_comp_rd_d_ch1 : STD_LOGIC; + SIGNAL rd_in_cg_comp_rd_d_ch2 : STD_LOGIC; + SIGNAL rd_in_cg_comp_rd_d_ch3 : STD_LOGIC; + SIGNAL rd_in_cg_comp_wr_ch0 : STD_LOGIC; + SIGNAL rd_in_cg_comp_wr_ch1 : STD_LOGIC; + SIGNAL rd_in_cg_comp_wr_ch2 : STD_LOGIC; + SIGNAL rd_in_cg_comp_wr_ch3 : STD_LOGIC; + + -- XAUI related channel 0 to rest channels in ICD + -- in Quartus sim: using its own ptrs + SIGNAL rd_out_del_cond_met_out : STD_LOGIC; + SIGNAL rd_out_fifo_ovr_out : STD_LOGIC; + SIGNAL rd_out_latency_comp_out : STD_LOGIC; + SIGNAL rd_out_insert_incomplete_out : STD_LOGIC; + + SIGNAL rd_in_del_cond_met_0 : STD_LOGIC; + SIGNAL rd_in_fifo_ovr_0 : STD_LOGIC; + SIGNAL rd_in_latency_comp_0 : STD_LOGIC; + SIGNAL rd_in_insert_incomplete_0 : STD_LOGIC; + + -- ww12 - splitting IQP into pipe_up/_down + SIGNAL rd_out_rx_div2_sync_out_pipe_up : STD_LOGIC; + SIGNAL rd_out_rx_we_out_pipe_up : STD_LOGIC; + SIGNAL rd_out_wr_enable_out_pipe_up : STD_LOGIC; + SIGNAL rd_out_rd_enable_out_pipe_up : STD_LOGIC; + SIGNAL rd_out_reset_pc_ptrs_out_pipe_up : STD_LOGIC; + SIGNAL rd_out_speed_change_out_pipe_up : STD_LOGIC; + + SIGNAL rd_out_rx_div2_sync_out_pipe_down : STD_LOGIC; + SIGNAL rd_out_rx_we_out_pipe_down : STD_LOGIC; + SIGNAL rd_out_wr_enable_out_pipe_down : STD_LOGIC; + SIGNAL rd_out_rd_enable_out_pipe_down : STD_LOGIC; + SIGNAL rd_out_reset_pc_ptrs_out_pipe_down : STD_LOGIC; + SIGNAL rd_out_speed_change_out_pipe_down : STD_LOGIC; + + -- ww12 - spliting inputs because tx_side's iqp output split + SIGNAL rd_in_tx_div2_sync_out_pipe_up : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + SIGNAL rd_in_fifo_select_out_pipe_up : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + SIGNAL rd_in_tx_wr_enable_out_pipe_up : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + SIGNAL rd_in_tx_rd_enable_out_pipe_up : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + SIGNAL rd_in_tx_div2_sync_out_pipe_down : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + SIGNAL rd_in_fifo_select_out_pipe_down : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + SIGNAL rd_in_tx_wr_enable_out_pipe_down : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + SIGNAL rd_in_tx_rd_enable_out_pipe_down : STD_LOGIC; -- from corresponding tx channels output *_out_pipe + + -- ww25.2008 interfaces -------------------------------------------------------- + SIGNAL rd_in_pcs_wrapback_in : STD_LOGIC_VECTOR(69 DOWNTO 0); + + --/////////////////////////////////////////////////////////////////////////// + -- Internal Variables ----------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL i : INTEGER; + SIGNAL j : INTEGER; + + SIGNAL tmp_reg40 : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL tmp_rcomp_size : STD_LOGIC_VECTOR(2 DOWNTO 0); + + --/////////////////////////////////////////////////////////////////////////// + -- Internal Functions ----------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + --/////////////////////////////////////////////////////////////////////////// + -- INPUT FILTERING -------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + SIGNAL a1a2size_in : STD_LOGIC; + SIGNAL alignstatus_in : STD_LOGIC; + SIGNAL alignstatussync_in : STD_LOGIC; + SIGNAL bitslip_in : STD_LOGIC; + SIGNAL coreclk_in : STD_LOGIC; + SIGNAL datain_in : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL digitalreset_in : STD_LOGIC; + SIGNAL dpriodisable_in : STD_LOGIC; + SIGNAL dprioin_in : STD_LOGIC_VECTOR(399 DOWNTO 0); -- tmp width + SIGNAL elecidleinfersel_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL enabledeskew_in : STD_LOGIC; + SIGNAL enabyteord_in : STD_LOGIC; + SIGNAL enapatternalign_in : STD_LOGIC; + SIGNAL fifordin_in : STD_LOGIC; + SIGNAL fiforesetrd_in : STD_LOGIC; + SIGNAL invpol_in : STD_LOGIC; + SIGNAL localrefclk_in : STD_LOGIC; + SIGNAL masterclk_in : STD_LOGIC; + SIGNAL parallelfdbk_in : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL phfifordenable_in : STD_LOGIC; + SIGNAL phfiforeset_in : STD_LOGIC; + SIGNAL phfifowrdisable_in : STD_LOGIC; + SIGNAL phfifox4bytesel_in : STD_LOGIC; + SIGNAL phfifox4rdenable_in : STD_LOGIC; + SIGNAL phfifox4wrclk_in : STD_LOGIC; + SIGNAL phfifox4wrenable_in : STD_LOGIC; + SIGNAL phfifox8bytesel_in : STD_LOGIC; + SIGNAL phfifox8rdenable_in : STD_LOGIC; + SIGNAL phfifox8wrclk_in : STD_LOGIC; + SIGNAL phfifox8wrenable_in : STD_LOGIC; + SIGNAL pipe8b10binvpolarity_in : STD_LOGIC; + SIGNAL pipepowerdown_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL pipepowerstate_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ppmdetectdividedclk_in : STD_LOGIC; + SIGNAL ppmdetectrefclk_in : STD_LOGIC; + SIGNAL quadreset_in : STD_LOGIC; + SIGNAL rateswitch_in : STD_LOGIC; + SIGNAL rateswitchisdone_in : STD_LOGIC; + SIGNAL rateswitchxndone_in : STD_LOGIC; + SIGNAL recoveredclk_in : STD_LOGIC; + SIGNAL refclk_in : STD_LOGIC; + SIGNAL revbitorderwa_in : STD_LOGIC; + SIGNAL revbyteorderwa_in : STD_LOGIC; + SIGNAL rmfifordena_in : STD_LOGIC; + SIGNAL rmfiforeset_in : STD_LOGIC; + SIGNAL rmfifowrena_in : STD_LOGIC; + SIGNAL rxdetectvalid_in : STD_LOGIC; + SIGNAL rxelecidlerateswitch_in : STD_LOGIC; + SIGNAL rxfound_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL signaldetected_in : STD_LOGIC; + SIGNAL xgmctrlin_in : STD_LOGIC; + SIGNAL xgmdatain_in : STD_LOGIC_VECTOR(7 DOWNTO 0); --54 ins --- + + --ww47 inputs + SIGNAL autospdxnconfigsel_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- config_sel_centrl, quad_up, quad_down + SIGNAL autospdxnspdchg_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- From CMU.spped-change_centrl, rx3(up), rx0(down) + SIGNAL cdrctrllocktorefcl_in : STD_LOGIC; -- pld_ltr + SIGNAL hip8b10binvpolarity_in : STD_LOGIC; -- hip_rxpolarity + SIGNAL hipelecidleinfersel_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- hip_eidleinfersel_ch + SIGNAL hippowerdown_in : STD_LOGIC_VECTOR(1 DOWNTO 0); -- hip_powerdown_ch + SIGNAL hiprateswitch_in : STD_LOGIC; -- hip_rate + SIGNAL iqpautospdxnspgchg_in : STD_LOGIC_VECTOR(1 DOWNTO 0); -- speed_change_in_pipe_quad_up, down + SIGNAL iqpphfifoxnbytesel_in : STD_LOGIC_VECTOR(1 DOWNTO 0); -- wr_enable_ptrs_in_pipe_quad_up, down + SIGNAL iqpphfifoxnptrsreset_in : STD_LOGIC_VECTOR(1 DOWNTO 0); -- reset_pc_ptrs_in_pipe_quad_up, down + SIGNAL iqpphfifoxnrdenable_in : STD_LOGIC_VECTOR(1 DOWNTO 0); -- rd_enable_ptrs_in_pipe_quad_up, down + SIGNAL iqpphfifoxnwrclk_in : STD_LOGIC_VECTOR(1 DOWNTO 0); -- rx_div2_sync_in_pipe_quad_up, down + SIGNAL iqpphfifoxnwrenable_in : STD_LOGIC_VECTOR(1 DOWNTO 0); -- wr_enable_ptrs_in_pipe_quad_up, down + SIGNAL phfifoxnbytesel_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- rx_we_in_centrl, quad_up, quad_down + SIGNAL phfifoxnptrsreset_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- ph fifo. From CMU to both RX & TX. + SIGNAL phfifoxnrdenable_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- rd_enable_in_centrl, quad_up, quad_down + SIGNAL phfifoxnwrclk_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- ph fifo. From CMU to RX. + SIGNAL phfifoxnwrenable_in : STD_LOGIC_VECTOR(2 DOWNTO 0); -- wr_enable_in_centrl, quad_up, quad_down + SIGNAL powerdn_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL prbscidenable_in : STD_LOGIC; -- prbs_cid_en + + -- ww12.08 inputs + SIGNAL grayelecidleinferselfromtx_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL pipeenrevparallellpbkfromtx_in : STD_LOGIC := '0'; + + --NEW: updated width + --assign disablefifordin_in = (disablefifordin == 1'b0) ? 1'b0 : 1'b1; // inverted + --assign disablefifowrin_in = (disablefifowrin == 1'b0) ? 1'b0 : 1'b1; // inverted + --/////////////////////////////////////////////////////////////////////////// + -- TIMING -- TCO/TSU/HOLD // + --/////////////////////////////////////////////////////////////////////////// + + --/////////////////////////////////////////////////////////////////////////// + -- dprio outputs // + --/////////////////////////////////////////////////////////////////////////// + SIGNAL wire_dprioout : STD_LOGIC_VECTOR(299 DOWNTO 0); + + --/////////////////////////////////////////////////////////////////////////// + -- select CRAMs between DPIRO vs. parameters -----------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL mpcs_dpriodisable : STD_LOGIC; + -- X-HDL generated signals + + SIGNAL xhdl0 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL xhdl1 : STD_LOGIC_VECTOR(1 DOWNTO 0); +BEGIN + + -------------------------------------------------------------------------- + -- Wire Delay Block -- + -------------------------------------------------------------------------- + WireDelay : BLOCK + BEGIN + VitalWireDelay (coreclk_ipd,coreclk, tipd_coreclk); -- kept for TCO + VitalWireDelay (xgmctrlin_ipd,xgmctrlin, tipd_xgmctrlin); + bits_pipepowerdown : FOR i in pipepowerdown'RANGE GENERATE + VitalWireDelay (pipepowerdown_ipd(i),pipepowerdown(i), tipd_pipepowerdown(i)); + END GENERATE; + bits_parallelfdbk : FOR i in parallelfdbk'RANGE GENERATE + VitalWireDelay (parallelfdbk_ipd(i),parallelfdbk(i), tipd_parallelfdbk(i)); + END GENERATE; + VitalWireDelay (masterclk_ipd,masterclk, tipd_masterclk); + bits_pipepowerstate : FOR i in pipepowerstate'RANGE GENERATE + VitalWireDelay (pipepowerstate_ipd(i),pipepowerstate(i), tipd_pipepowerstate(i)); + END GENERATE; + VitalWireDelay (alignstatussync_ipd,alignstatussync, tipd_alignstatussync); + bits_powerdn : FOR i in powerdn'RANGE GENERATE + VitalWireDelay (powerdn_ipd(i),powerdn(i), tipd_powerdn(i)); + END GENERATE; + VitalWireDelay (refclk_ipd,refclk, tipd_refclk); + VitalWireDelay (phfifox4bytesel_ipd,phfifox4bytesel, tipd_phfifox4bytesel); + VitalWireDelay (bitslip_ipd,bitslip, tipd_bitslip); + VitalWireDelay (phfiforeset_ipd,phfiforeset, tipd_phfiforeset); + bits_dprioin : FOR i in dprioin'RANGE GENERATE + VitalWireDelay (dprioin_ipd(i),dprioin(i), tipd_dprioin(i)); + END GENERATE; + bits_datain : FOR i in datain'RANGE GENERATE + VitalWireDelay (datain_ipd(i),datain(i), tipd_datain(i)); + END GENERATE; + VitalWireDelay (enabledeskew_ipd,enabledeskew, tipd_enabledeskew); + bits_hippowerdown : FOR i in hippowerdown'RANGE GENERATE + VitalWireDelay (hippowerdown_ipd(i),hippowerdown(i), tipd_hippowerdown(i)); + END GENERATE; + VitalWireDelay (revbyteorderwa_ipd,revbyteorderwa, tipd_revbyteorderwa); + VitalWireDelay (phfifox4wrenable_ipd,phfifox4wrenable, tipd_phfifox4wrenable); + VitalWireDelay (dpriodisable_ipd,dpriodisable, tipd_dpriodisable); + VitalWireDelay (enabyteord_ipd,enabyteord, tipd_enabyteord); + VitalWireDelay (invpol_ipd,invpol, tipd_invpol); + VitalWireDelay (revbitorderwa_ipd,revbitorderwa, tipd_revbitorderwa); + VitalWireDelay (localrefclk_ipd,localrefclk, tipd_localrefclk); + VitalWireDelay (enapatternalign_ipd,enapatternalign, tipd_enapatternalign); + VitalWireDelay (phfifowrdisable_ipd,phfifowrdisable, tipd_phfifowrdisable); + VitalWireDelay (signaldetected_ipd,signaldetected, tipd_signaldetected); + VitalWireDelay (alignstatus_ipd,alignstatus, tipd_alignstatus); + VitalWireDelay (quadreset_ipd,quadreset, tipd_quadreset); + VitalWireDelay (rxdetectvalid_ipd,rxdetectvalid, tipd_rxdetectvalid); + VitalWireDelay (recoveredclk_ipd,recoveredclk, tipd_recoveredclk); + VitalWireDelay (phfifordenable_ipd,phfifordenable, tipd_phfifordenable); + VitalWireDelay (phfifox4wrclk_ipd,phfifox4wrclk, tipd_phfifox4wrclk); + VitalWireDelay (rmfifowrena_ipd,rmfifowrena, tipd_rmfifowrena); + VitalWireDelay (a1a2size_ipd,a1a2size, tipd_a1a2size); + bits_elecidleinfersel : FOR i in elecidleinfersel'RANGE GENERATE + VitalWireDelay (elecidleinfersel_ipd(i),elecidleinfersel(i), tipd_elecidleinfersel(i)); + END GENERATE; + VitalWireDelay (hip8b10binvpolarity_ipd,hip8b10binvpolarity, tipd_hip8b10binvpolarity); + VitalWireDelay (rmfiforeset_ipd,rmfiforeset, tipd_rmfiforeset); + VitalWireDelay (coreclk_ipd,coreclk, tipd_coreclk); + VitalWireDelay (rmfifordena_ipd,rmfifordena, tipd_rmfifordena); + bits_hipelecidleinfersel : FOR i in hipelecidleinfersel'RANGE GENERATE + VitalWireDelay (hipelecidleinfersel_ipd(i),hipelecidleinfersel(i), tipd_hipelecidleinfersel(i)); + END GENERATE; + VitalWireDelay (phfifox4rdenable_ipd,phfifox4rdenable, tipd_phfifox4rdenable); + VitalWireDelay (pipe8b10binvpolarity_ipd,pipe8b10binvpolarity, tipd_pipe8b10binvpolarity); + VitalWireDelay (fifordin_ipd,fifordin, tipd_fifordin); + VitalWireDelay (prbscidenable_ipd,prbscidenable, tipd_prbscidenable); + VitalWireDelay (digitalreset_ipd,digitalreset, tipd_digitalreset); + bits_rxfound : FOR i in rxfound'RANGE GENERATE + VitalWireDelay (rxfound_ipd(i),rxfound(i), tipd_rxfound(i)); + END GENERATE; + VitalWireDelay (cdrctrllocktorefcl_ipd,cdrctrllocktorefcl, tipd_cdrctrllocktorefcl); + VitalWireDelay (fiforesetrd_ipd,fiforesetrd, tipd_fiforesetrd); + bits_xgmdatain : FOR i in xgmdatain'RANGE GENERATE + VitalWireDelay (xgmdatain_ipd(i),xgmdatain(i), tipd_xgmdatain(i)); + END GENERATE; + END BLOCK; + + + -------------------------------------------------------------------------- + -- Timing Check Section: set up and hold -- + -------------------------------------------------------------------------- + + -------------------------------------------------------------------------- + -- Path Delay Section -- + -------------------------------------------------------------------------- + --- cycloneiv_modify begin DOWNTO cycloneiv output layer to adjust width change ---- + a1a2sizeout_reg_sr <= a1a2sizeout_reg(1 DOWNTO 0); + a1detect_reg_sr <= a1detect_reg(0); + a2detect_reg_sr <= a2detect_reg(0); + ctrldetect_reg_sr <= ctrldetect_reg(1 DOWNTO 0); + dataout_reg_sr <= dataout_reg(19 DOWNTO 0); + dataoutfull_sr(15 DOWNTO 0) <= rd_out_rxd(15 DOWNTO 0); + dataoutfull_sr(31 DOWNTO 16) <= rd_out_rxd(47 DOWNTO 32); + disperr_reg_sr <= disperr_reg(1 DOWNTO 0); + errdetect_reg_sr <= errdetect_reg(1 DOWNTO 0); + k1detect_reg_sr <= k1detect_reg(0); + k2detect_reg_sr <= k2detect_reg(0); + patterndetect_reg_sr <= patterndetect_reg(1 DOWNTO 0); + rmfifodatadeleted_reg_sr <= rmfifodatadeleted_reg(1 DOWNTO 0); + rmfifodatainserted_reg_sr <= rmfifodatainserted_reg(1 DOWNTO 0); + runningdisp_reg_sr <= runningdisp_reg(1 DOWNTO 0); + syncstatus_reg_sr <= syncstatus_reg(1 DOWNTO 0); + --- cycloneiv_modify end: cycloneiv output layer to adjust width change ------ + + VITAL: PROCESS (coreclk_ipd, a1a2sizeout_reg_sr, ctrldetect_reg_sr, dataout_reg_sr, disperr_reg_sr, errdetect_reg_sr, patterndetect_reg_sr, rmfifodatadeleted_reg_sr, rmfifodatainserted_reg_sr, runningdisp_reg_sr, syncstatus_reg_sr, pi_out_rxd_ch, rd_out_byteord_flag, rd_out_full_rx, rd_out_empty_rx, hs_out_rxstatus_ch, hs_out_phystatus, hs_out_rxvalid, rd_out_rxd(13), rd_out_rxd(14), rd_out_rxd(45), rd_out_rxd(46)) + variable Tviol_phfifordenable_coreclk : std_ulogic := '0'; + variable TimingData_phfifordenable_coreclk : VitalTimingDataType := VitalTimingDataInit; + + variable pipebufferstat0_VitalGlitchData: VitalGlitchDataType; + variable pipebufferstat1_VitalGlitchData: VitalGlitchDataType; + variable pipebufferstat2_VitalGlitchData: VitalGlitchDataType; + variable pipebufferstat3_VitalGlitchData: VitalGlitchDataType; + variable byteorderalignstatus_VitalGlitchData: VitalGlitchDataType; + variable phfifooverflow_VitalGlitchData: VitalGlitchDataType; + variable phfifounderflow_VitalGlitchData: VitalGlitchDataType; + variable pipephydonestatus_VitalGlitchData: VitalGlitchDataType; + variable pipedatavalid_VitalGlitchData: VitalGlitchDataType; + variable CQDelayA1a2sizeout: TIME := 0 ns; + variable CQDelayCtrldetect: TIME := 0 ns; + variable CQDelayDataout: TIME := 0 ns; + variable CQDelayDataoutfull: TIME := 0 ns; + variable CQDelayDisperr: TIME := 0 ns; + variable CQDelayErrdetect: TIME := 0 ns; + variable CQDelayPatterndetect: TIME := 0 ns; + variable CQDelayRmfifodatadeleted: TIME := 0 ns; + variable CQDelayRmfifodatainserted: TIME := 0 ns; + variable CQDelayRunningdisp: TIME := 0 ns; + variable CQDelaySyncstatus: TIME := 0 ns; + variable CQDelayPipestatus: TIME := 0 ns; + + BEGIN + + ------------------------ + -- Timing Check Section + ------------------------ + + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_phfifordenable_coreclk, + TimingData => TimingData_phfifordenable_coreclk, + TestSignal => phfifordenable_ipd, + TestSignalName => "PHFIFORDENABLE", + RefSignal => coreclk_ipd, + RefSignalName => "CORECLK", + SetupHigh => tsetup_phfifordenable_coreclk_noedge_posedge, + SetupLow => tsetup_phfifordenable_coreclk_noedge_posedge, + HoldHigh => thold_phfifordenable_coreclk_noedge_posedge, + HoldLow => thold_phfifordenable_coreclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_RX_PCS", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + + CQDelayA1a2sizeout := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_a1a2sizeout_posedge, TRUE))); + a1a2sizeout <= TRANSPORT a1a2sizeout_reg_sr AFTER CQDelayA1a2sizeout; + + CQDelayCtrldetect := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_ctrldetect_posedge, TRUE))); + ctrldetect <= TRANSPORT ctrldetect_reg_sr AFTER CQDelayCtrldetect; + + CQDelayDataout := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_dataout_posedge, TRUE))); + dataout <= TRANSPORT dataout_reg_sr AFTER CQDelayDataout; + + CQDelayDataoutfull := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_dataoutfull_posedge, TRUE))); + dataoutfull <= TRANSPORT dataoutfull_sr AFTER CQDelayDataoutfull; + + CQDelayDisperr := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_disperr_posedge, TRUE))); + disperr <= TRANSPORT disperr_reg_sr AFTER CQDelayDisperr; + + CQDelayErrdetect := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_errdetect_posedge, TRUE))); + errdetect <= TRANSPORT errdetect_reg_sr AFTER CQDelayErrdetect; + + CQDelayPatterndetect := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_patterndetect_posedge, TRUE))); + patterndetect <= TRANSPORT patterndetect_reg_sr AFTER CQDelayPatterndetect; + + CQDelayRmfifodatadeleted := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_rmfifodatadeleted_posedge, TRUE))); + rmfifodatadeleted <= TRANSPORT rmfifodatadeleted_reg_sr AFTER CQDelayRmfifodatadeleted; + + CQDelayRmfifodatainserted := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_rmfifodatainserted_posedge, TRUE))); + rmfifodatainserted <= TRANSPORT rmfifodatainserted_reg_sr AFTER CQDelayRmfifodatainserted; + + CQDelayRunningdisp := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_runningdisp_posedge, TRUE))); + runningdisp <= TRANSPORT runningdisp_reg_sr AFTER CQDelayRunningdisp; + + CQDelaySyncstatus := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_syncstatus_posedge, TRUE))); + syncstatus <= TRANSPORT syncstatus_reg_sr AFTER CQDelaySyncstatus; + + VitalPathDelay01 ( + OutSignal => pipebufferstat(0), + OutSignalName => "PIPEBUFFERSTAT", + OutTemp => rd_out_rxd(13), + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_pipebufferstat_posedge(0), TRUE)), + GlitchData => pipebufferstat0_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => pipebufferstat(1), + OutSignalName => "PIPEBUFFERSTAT", + OutTemp => rd_out_rxd(14), + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_pipebufferstat_posedge(1), TRUE)), + GlitchData => pipebufferstat1_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => pipebufferstat(2), + OutSignalName => "PIPEBUFFERSTAT", + OutTemp => rd_out_rxd(45), + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_pipebufferstat_posedge(2), TRUE)), + GlitchData => pipebufferstat2_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => pipebufferstat(3), + OutSignalName => "PIPEBUFFERSTAT", + OutTemp => rd_out_rxd(46), + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_pipebufferstat_posedge(3), TRUE)), + GlitchData => pipebufferstat3_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => byteorderalignstatus, + OutSignalName => "BYTEORDERALIGNSTATUS", + OutTemp => rd_out_byteord_flag, + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_byteorderalignstatus_posedge, TRUE)), + GlitchData => byteorderalignstatus_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => phfifooverflow, + OutSignalName => "PHFIFOOVERFLOW", + OutTemp => rd_out_full_rx, + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_phfifooverflow_posedge, TRUE)), + GlitchData => phfifooverflow_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => phfifounderflow, + OutSignalName => "PHFIFOUNDERFLOW", + OutTemp => rd_out_empty_rx, + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_phfifounderflow_posedge, TRUE)), + GlitchData => phfifounderflow_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + CQDelayPipestatus := hssiSelectDelay ( + Paths => (0 => (coreclk_ipd'last_event, tpd_coreclk_pipestatus_posedge, TRUE))); + pipestatus <= TRANSPORT hs_out_rxstatus_ch AFTER CQDelayPipestatus; + + VitalPathDelay01 ( + OutSignal => pipephydonestatus, + OutSignalName => "PIPEPHYDONESTATUS", + OutTemp => hs_out_phystatus, + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_pipephydonestatus_posedge, TRUE)), + GlitchData => pipephydonestatus_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => pipedatavalid, + OutSignalName => "pipedatavalid", + OutTemp => hs_out_rxvalid, + Paths => (1 => (coreclk_ipd'last_event, tpd_coreclk_pipedatavalid_posedge, TRUE)), + GlitchData => pipedatavalid_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + END PROCESS; + + + a1a2size_in <= '1' WHEN (a1a2size = '1') ELSE + '0'; + alignstatus_in <= '1' WHEN (alignstatus = '1') ELSE + '0'; + alignstatussync_in <= '1' WHEN (alignstatussync = '1') ELSE + '0'; + bitslip_in <= '1' WHEN (bitslip = '1') ELSE + '0'; + coreclk_in <= '1' WHEN (coreclk = '1') ELSE + '0'; + datain_in <= "0000000000" & datain; + digitalreset_in <= '1' WHEN (digitalreset = '1') ELSE + '0'; + dpriodisable_in <= '0' WHEN (dpriodisable = '0') ELSE + '1'; + dprioin_in <= dprioin(399 DOWNTO 0); + elecidleinfersel_in <= "001" WHEN (elecidleinfersel = "001") ELSE + "000"; + enabledeskew_in <= '1' WHEN (enabledeskew = '1') ELSE + '0'; + enabyteord_in <= '1' WHEN (enabyteord = '1') ELSE + '0'; + enapatternalign_in <= '1' WHEN (enapatternalign = '1') ELSE + '0'; + fifordin_in <= '1' WHEN (fifordin = '1') ELSE + '0'; + fiforesetrd_in <= '1' WHEN (fiforesetrd = '1') ELSE + '0'; + invpol_in <= '1' WHEN (invpol = '1') ELSE + '0'; + localrefclk_in <= '1' WHEN (localrefclk = '1') ELSE + '0'; + masterclk_in <= '1' WHEN (masterclk = '1') ELSE + '0'; + parallelfdbk_in <= parallelfdbk; + phfifordenable_in <= '0' WHEN (phfifordenable = '0') ELSE + '1'; + phfiforeset_in <= '1' WHEN (phfiforeset = '1') ELSE + '0'; + phfifowrdisable_in <= '1' WHEN (phfifowrdisable = '1') ELSE + '0'; + phfifox4bytesel_in <= '1' WHEN (phfifox4bytesel = '1') ELSE + '0'; + phfifox4rdenable_in <= '1' WHEN (phfifox4rdenable = '1') ELSE + '0'; + phfifox4wrclk_in <= '1' WHEN (phfifox4wrclk = '1') ELSE + '0'; + phfifox4wrenable_in <= '1' WHEN (phfifox4wrenable = '1') ELSE + '0'; + phfifox8bytesel_in <= '1' WHEN (phfifox8bytesel = '1') ELSE + '0'; + phfifox8rdenable_in <= '1' WHEN (phfifox8rdenable = '1') ELSE + '0'; + phfifox8wrclk_in <= '1' WHEN (phfifox8wrclk = '1') ELSE + '0'; + phfifox8wrenable_in <= '1' WHEN (phfifox8wrenable = '1') ELSE + '0'; + pipe8b10binvpolarity_in <= '1' WHEN (pipe8b10binvpolarity = '1') ELSE + '0'; + pipepowerdown_in <= pipepowerdown; + pipepowerstate_in <= pipepowerstate; + ppmdetectdividedclk_in <= '1' WHEN (ppmdetectdividedclk = '1') ELSE + '0'; + ppmdetectrefclk_in <= '1' WHEN (ppmdetectrefclk = '1') ELSE + '0'; + quadreset_in <= '1' WHEN (quadreset = '1') ELSE + '0'; + rateswitch_in <= '1' WHEN (rateswitch = '1') ELSE + '0'; + rateswitchisdone_in <= '1' WHEN (rateswitchisdone = '1') ELSE + '0'; + rateswitchxndone_in <= '1' WHEN (rateswitchxndone = '1') ELSE + '0'; + recoveredclk_in <= '1' WHEN (recoveredclk = '1') ELSE + '0'; + refclk_in <= '1' WHEN (refclk = '1') ELSE + '0'; + revbitorderwa_in <= '1' WHEN (revbitorderwa = '1') ELSE + '0'; + revbyteorderwa_in <= '1' WHEN (revbyteorderwa = '1') ELSE + '0'; + rmfifordena_in <= '1' WHEN (rmfifordena = '1') ELSE + '0'; + rmfiforeset_in <= '1' WHEN (rmfiforeset = '1') ELSE + '0'; + rmfifowrena_in <= '1' WHEN (rmfifowrena = '1') ELSE + '0'; + rxdetectvalid_in <= '1' WHEN (rxdetectvalid = '1') ELSE + '0'; + rxelecidlerateswitch_in <= '1' WHEN (rxelecidlerateswitch = '1') ELSE + '0'; + rxfound_in <= rxfound; + signaldetected_in <= '1' WHEN (signaldetected = '1') ELSE + '0'; + xgmctrlin_in <= '1' WHEN (xgmctrlin = '1') ELSE + '0'; + xgmdatain_in <= xgmdatain; + autospdxnconfigsel_in <= autospdxnconfigsel; + autospdxnspdchg_in <= autospdxnspdchg; + cdrctrllocktorefcl_in <= cdrctrllocktorefcl; + hip8b10binvpolarity_in <= hip8b10binvpolarity; + hipelecidleinfersel_in <= hipelecidleinfersel; + hippowerdown_in <= hippowerdown; + hiprateswitch_in <= hiprateswitch; + iqpautospdxnspgchg_in <= iqpautospdxnspgchg; + iqpphfifoxnbytesel_in <= iqpphfifoxnbytesel; + iqpphfifoxnptrsreset_in <= iqpphfifoxnptrsreset; + iqpphfifoxnrdenable_in <= iqpphfifoxnrdenable; + iqpphfifoxnwrclk_in <= iqpphfifoxnwrclk; + iqpphfifoxnwrenable_in <= iqpphfifoxnwrenable; + phfifoxnbytesel_in <= phfifoxnbytesel; + phfifoxnptrsreset_in <= phfifoxnptrsreset; + phfifoxnrdenable_in <= phfifoxnrdenable; + phfifoxnwrclk_in <= phfifoxnwrclk; + phfifoxnwrenable_in <= phfifoxnwrenable; + powerdn_in <= powerdn; + prbscidenable_in <= prbscidenable; + -- ww12 inputs + grayelecidleinferselfromtx_in(0) <= '1' WHEN (grayelecidleinferselfromtx(0) = '1') ELSE '0'; + grayelecidleinferselfromtx_in(1) <= '1' WHEN (grayelecidleinferselfromtx(1) = '1') ELSE '0'; + grayelecidleinferselfromtx_in(2) <= '1' WHEN (grayelecidleinferselfromtx(2) = '1') ELSE '0'; + + pipeenrevparallellpbkfromtx_in <= '1' WHEN (pipeenrevparallellpbkfromtx_in = '1') ELSE '0'; + + PROCESS + + FUNCTION compute_rrundisp ( + pma_doublewidth : IN std_logic; + pma_width : IN std_logic; + run_length : IN integer) RETURN STD_LOGIC_VECTOR IS + + + VARIABLE res : std_logic_vector(5 DOWNTO 0); + VARIABLE compute_rrundisp : std_logic_vector(5 DOWNTO 0); + VARIABLE run_len_stepped : integer; + VARIABLE temp_xhdl56 : STD_LOGIC_VECTOR(1 DOWNTO 0); + VARIABLE txt : LINE; + BEGIN + temp_xhdl56 := pma_doublewidth & pma_width; + CASE temp_xhdl56 IS + WHEN "00" => + run_len_stepped := run_length / 4; + IF (run_len_stepped = 32) THEN + res := "000000"; + ELSE + res := int2bin(run_len_stepped, 6); + END IF; + WHEN "01" => + run_len_stepped := run_length / 5; + IF (run_len_stepped = 32) THEN + res := "000000"; + ELSE + res := int2bin(run_len_stepped, 6); + END IF; + WHEN "10" => + run_len_stepped := run_length / 8; + IF (run_len_stepped = 64) THEN + res := "000000"; + ELSE + res := int2bin(run_len_stepped, 6); + END IF; + WHEN "11" => + run_len_stepped := run_length / 10; + IF (run_len_stepped = 64) THEN + res := "000000"; + ELSE + res := int2bin(run_len_stepped, 6); + END IF; + WHEN OTHERS => + --WRITE(TXT,STRING'("Invalid pma_doublewidth and pma_width selection")); + -- WRITELINE(OUTPUT,TXT); + END CASE; + RETURN res; + END compute_rrundisp; + + FUNCTION compute_rprbs_sel_rx ( + pma_doublewidth : IN std_logic; + pma_width : IN std_logic; + test_mode : IN STRING) RETURN STD_LOGIC_VECTOR IS + + + VARIABLE res : std_logic_vector(2 DOWNTO 0); + VARIABLE compute_rprbs_sel_rx : std_logic_vector(2 DOWNTO 0); + VARIABLE temp_xhdl56 : STD_LOGIC_VECTOR(1 DOWNTO 0); + VARIABLE txt : LINE; + BEGIN + temp_xhdl56 := pma_doublewidth & pma_width; + CASE temp_xhdl56 IS + WHEN "00" => + IF ((test_mode = "prbs_8") OR (test_mode = "prbs8")) THEN + res := "000"; + ELSIF (test_mode = "prbs7") THEN + res := "010"; + ELSIF (test_mode = "prbs23") THEN + res := "100"; + ELSIF (test_mode = "high frequency") THEN + res := "001"; + ELSE + res := "000"; -- default + END IF; + WHEN "01" => + IF ((test_mode = "prbs_10") OR (test_mode = "prbs10")) THEN + res := "000"; + ELSIF (test_mode = "high frequency") THEN + res := "001"; + ELSIF (test_mode = "low frequency") THEN + res := "010"; + ELSIF (test_mode = "mixed frequency") THEN + res := "011"; + ELSE + res := "000"; -- default + END IF; + WHEN "10" => + IF ((test_mode = "prbs_7") OR (test_mode = "prbs7")) THEN + res := "000"; + ELSIF (test_mode = "prbs_23" OR test_mode = "prbs23") THEN + res := "001"; + ELSIF (test_mode = "high frequency") THEN + res := "010"; + ELSE + res := "000"; -- default + END IF; + WHEN "11" => + IF ((test_mode = "prbs_7") OR (test_mode = "prbs7")) THEN + res := "000"; + ELSIF ((test_mode = "prbs_23") OR (test_mode = "prbs23")) THEN + res := "001"; + ELSIF (test_mode = "high frequency") THEN + res := "010"; + ELSIF (test_mode = "low frequency") THEN + res := "011"; + ELSIF (test_mode = "mixed frequency") THEN + res := "100"; + ELSE + res := "000"; -- default + END IF; + WHEN OTHERS => + -- WRITE(TXT,STRING'("Invalid pma_doublewidth and pma_width selection")); + -- WRITELINE(OUTPUT,TXT); + + END CASE; + RETURN res; + END compute_rprbs_sel_rx; + + variable init_rpma_doublewidth_rx_var : std_logic; + variable init_rpmadwidth_rx_var : std_logic; + VARIABLE tmp_rcomp_size : std_logic_vector(2 DOWNTO 0); + VARIABLE tmp_reg40 : STD_LOGIC_VECTOR(39 DOWNTO 0); + + BEGIN + + if(alpha_tolower(use_deserializer_double_data_mode) = ("true"))then + init_rpma_doublewidth_rx <= '1'; + init_rpma_doublewidth_rx_var := '1'; + else + init_rpma_doublewidth_rx <= '0'; + init_rpma_doublewidth_rx_var := '0'; + end if; + + if((dec_8b_10b_mode = ("none")) AND ((channel_width = 8) OR (channel_width = 16) OR (channel_width = 32)))then + init_rpmadwidth_rx <= '0'; + init_rpmadwidth_rx_var := '0'; + else + init_rpmadwidth_rx <= '1'; + init_rpmadwidth_rx_var := '1'; + end if; + + init_dskwclksel(1) <= mux_select((alpha_tolower(use_deskew_fifo) = ("true")), '1', '0'); + init_dskwclksel(0) <= '0'; + init_is_lane0 <= mux_select((channel_number = 0), '1', '0'); + init_r8b10b_dec_ibm_en(0) <= mux_select((dec_8b_10b_compatibility_mode = ("true")), '1', '0'); + init_r8b10b_dec_ibm_en(1) <= '1'; + --init_ralempty <= mux_select((rate_match_almost_empty_threshold = 11), "0000", ("0000" - int2bin(rate_match_almost_empty_threshold, 4))); + --init_ralfull <= mux_select((rate_match_almost_full_threshold = 13), "0000", (int2bin(rate_match_almost_full_threshold, 4) - "0100")); + init_rall_one_dect_only <= mux_select((prbs_all_one_detect = ("true")), '1', '0'); + init_rautobtalg_dis <= mux_select((bit_slip_enable = ("true")), '1', '0'); + init_rautoinsdis <= mux_select((disable_auto_idle_insertion = ("true")), '1', '0'); + init_rbist_clr_rx <= '0'; + init_rbist_sel <= mux_select((self_test_mode = ("cjpat")), "01", mux_select((self_test_mode = ("crpat")), "10", "00")); + init_rbisten_rx <= mux_select(((enable_self_test_mode = ("true")) AND (self_test_mode = ("cjpat") OR self_test_mode = ("crpat") OR self_test_mode = ("incremental"))), '1', '0'); + init_rbitloc_rev_en <= mux_select((enable_bit_reversal = ("true")), '1', '0'); + --init_rbitslip_size <= mux_select((protocol_hint = ("pipe")), "11", mux_select((protocol_hint = ("xaui")), "10", "00")); - removed + init_rbysync_polinv_en <= mux_select((allow_align_polarity_inversion = ("true")), '1', '0'); + init_rbyte_rev_en <= mux_select((alpha_tolower(enable_deep_align_byte_swap) = ("true")), '1', '0'); + + IF (byte_order_mode = "none" ) THEN + init_rbyteorden <= "00"; + ELSIF (byte_order_mode = "8" OR byte_order_mode = "16") THEN + init_rbyteorden <= "01"; + ELSIF (byte_order_mode = "10" OR byte_order_mode = "20") THEN + init_rbyteorden <= "11"; + ELSIF (byte_order_mode = "9" OR byte_order_mode = "18") THEN + init_rbyteorden <= "10"; + ELSE + init_rbyteorden <= "ZZ"; + END IF; + + IF (byte_order_mode = "16" OR byte_order_mode = "18" OR byte_order_mode = "20") THEN + init_rbytord_2sym_en <= '1'; + ELSE + init_rbytord_2sym_en <= '0'; + END IF; + + tmp_reg40 := str2bin(byte_order_pad_pattern) ; + init_rbytordpad <= tmp_reg40(9 DOWNTO 0); + + tmp_reg40 := str2bin(byte_order_pattern) ; + init_rbytordpat(9 DOWNTO 0) <= tmp_reg40(9 DOWNTO 0); + IF (byte_order_mode = "16") THEN + init_rbytordpat(19 DOWNTO 10) <= ("00" & tmp_reg40(15 DOWNTO 8)); + ELSIF (byte_order_mode = "18") THEN + init_rbytordpat(19 DOWNTO 10) <= ("0" & tmp_reg40(17 DOWNTO 9)); + ELSE + init_rbytordpat(19 DOWNTO 10) <= tmp_reg40(19 DOWNTO 10); + END IF; + + IF (byte_order_pld_ctrl_enable = "true") THEN + init_rbytordplden <= '1'; + ELSE + init_rbytordplden <= '0'; + END IF; + + init_rcascaded_8b10b_en_rx <= mux_select((dec_8b_10b_mode = ("cascaded")), '1', '0'); + init_rclk_1_sel <= mux_select((clk1_mux_select = ("recvd_clk") OR clk1_mux_select = ("recovered clock")), "00", mux_select((clk1_mux_select = ("digital_refclk") OR clk1_mux_select = ("digital reference clock")), "01", mux_select((clk1_mux_select = ("local_refclk") OR clk1_mux_select = ("local reference clock")), "10", mux_select((clk1_mux_select = ("master_clk") OR clk1_mux_select = ("master clock")), "11", "ZZ")))); + init_rclk_2_sel <= mux_select((clk2_mux_select = ("recvd_clk") OR clk2_mux_select = ("recovered clock")), "00", mux_select((clk2_mux_select = ("digital_refclk") OR clk2_mux_select = ("digital reference clock")), "10", mux_select((clk2_mux_select = ("local_refclk") OR clk2_mux_select = ("local reference clock")), "01", mux_select((clk2_mux_select = ("core_clk") OR clk2_mux_select = ("core clk") OR clk2_mux_select = ("core clock")), "11", "ZZ")))); + init_rclkcmpinsertpad <= mux_select((insert_pad_on_underflow = ("true")), '1', '0'); + tmp_reg40 := str2bin(rate_match_pattern2) ; + init_rclkcmpsq1n <= tmp_reg40(19 DOWNTO 0); + tmp_reg40 := str2bin(rate_match_pattern1) ; + init_rclkcmpsq1p <= tmp_reg40(19 DOWNTO 0); + init_rclkcmpsqmd <= mux_select((rate_match_ordered_set_based = ("true")), '1', '0'); + init_rcmpfifourst <= mux_select((rate_match_reset_enable = ("true")), '1', '0'); + init_rcomp_pat <= str2bin(align_pattern) ; + init_rcomp_pat_porn <= mux_select((enable_true_complement_match_in_word_align = ("true")), '1', '0'); + IF (align_pattern_length = 16) THEN + IF (init_rpmadwidth_rx_var = '0' AND init_rpma_doublewidth_rx_var = '0') THEN + tmp_rcomp_size := "001"; + ELSE + tmp_rcomp_size := "011"; + END IF; + ELSE + tmp_rcomp_size := "ZZZ"; + END IF; + init_rcomp_size <= mux_select((align_pattern_length = 7), "000", mux_select((align_pattern_length = 8), "001", mux_select((align_pattern_length = 10), "010", mux_select((align_pattern_length = 16), tmp_rcomp_size, mux_select((align_pattern_length = 20), "100", mux_select((align_pattern_length = 32), "101", mux_select((align_pattern_length = 40), "110", "ZZZ"))))))); + init_rcxpat_chnl_en <= mux_select((channel_number = 1), "01", mux_select((channel_number = 2), "10", mux_select((channel_number = 3), "11", "00"))); + init_rdis_rx_disp <= mux_select((disable_running_disp_in_word_align = ("true")), '1', '0'); + tmp_reg40 := str2bin(deskew_pattern) ; + init_rdskchrp <= tmp_reg40(9 DOWNTO 0); + init_rdskposdisp <= mux_select((alpha_tolower(align_to_deskew_pattern_pos_disp_only) = ("true")), '1', '0'); + init_rdwidth_rx <= mux_select((use_double_data_mode = ("true")), '1', '0'); + init_rencdt_rising <= mux_select((alpha_tolower(use_rising_edge_triggered_pattern_align) = ("true")), '1', '0'); + init_rendec_data_sel_rx <= mux_select((protocol_hint = ("xaui")), '0', '1'); + init_rendec_rx <= mux_select((dec_8b_10b_mode /= ("none")), '1', '0'); + init_renpolinv_rx <= mux_select((allow_pipe_polarity_inversion = ("true")), '1', '0'); + init_renumber <= int2bin(num_align_loss_sync_error, 6) - "000001"; + init_resync_badcg_en <= "00"; + init_rforce_sig_det_pcs <= mux_select((force_signal_detect_dig = ("true")), '1', '0'); + init_rforce0_freqdet <= '0'; + init_rforce1_freqdet <= '0'; + init_rfreerun_rx <= mux_select((reset_clock_output_during_digital_reset = ("false")), '1', '0'); + init_rgenericfifo <= '0'; + init_rgnumber <= (int2bin(num_align_cons_good_data, 8) - "00000001"); + init_rib_inv_cd <= int2bin(infiniband_invalid_code, 2); + init_rindv_rx <= mux_select((channel_bonding = ("x4") OR channel_bonding = ("x8") OR protocol_hint = ("xaui")), '0', '1'); + init_rkchar <= mux_select((disallow_kchar_after_pattern_ordered_set = ("true")), '1', '0'); + init_rknumber <= mux_select((num_align_code_groups_in_ordered_set = 0), (int2bin(num_align_cons_pat, 8) - "00000001"), int2bin(num_align_cons_pat, 8)); + init_rlp20ben <= mux_select((use_parallel_loopback = ("true")), '1', '0'); + init_rmatchen <= mux_select((rate_match_fifo_mode = ("none") OR rate_match_fifo_mode = ("false")), '0', mux_select((rate_match_fifo_mode = ("true") OR rate_match_fifo_mode = ("normal")), '1', 'Z')); + init_rosbased <= mux_select((align_ordered_set_based = ("true")), '1', '0'); + init_rosnumber <= int2bin(num_align_code_groups_in_ordered_set, 2); + init_rphfifopldenrx <= '1'; + init_rphfifourstrx <= '1'; + init_rppm_cnt_reset <= '0'; + init_rppmsel <= "000000"; + init_rprbs_clr_rslt_rx <= '0'; + init_rprbs_sel <= compute_rprbs_sel_rx(init_rpma_doublewidth_rx_var,init_rpmadwidth_rx_var,self_test_mode); + init_rprbsen_rx <= mux_select(((enable_self_test_mode = ("true")) AND (self_test_mode /= ("incremental")) AND (self_test_mode /= ("cjpat")) AND (self_test_mode /= ("crpat"))), '1', '0'); + init_rrcvd_clk_sel <= mux_select((recovered_clk_mux_select = ("recvd_clk") OR recovered_clk_mux_select = ("recovered clock")), "00", mux_select((recovered_clk_mux_select = ("digital_refclk") OR recovered_clk_mux_select = ("digital reference clock")), "01", mux_select((recovered_clk_mux_select = ("local_refclk") OR recovered_clk_mux_select = ("local reference clock")), "10", "ZZ"))); + init_rrlv_en <= mux_select((run_length_enable = ("true")), '1', '0'); + init_rrundisp <= compute_rrundisp(init_rpma_doublewidth_rx_var,init_rpmadwidth_rx_var,run_length); + init_rrx_rd_clk_sel <= mux_select((rd_clk_mux_select = ("core_clk") OR rd_clk_mux_select = ("core clk") OR rd_clk_mux_select = ("core clock")), '1', '0'); + init_rrxfifo_dis <= mux_select((alpha_tolower(enable_phfifo_bypass) = ("true")), '1', '0'); + init_rrxfifo_lowlatency_en <= mux_select((ph_fifo_low_latency_enable = ("true")), '1', '0'); + init_rskpsetbased <= mux_select((rate_match_skip_set_based = ("true")), '1', '0'); + init_rsync_sm_dis <= mux_select((use_alignment_state_machine = ("false")), '1', '0'); + init_rtruebac2bac <= mux_select((rate_match_back_to_back = ("true")), '1', '0'); + init_rwa_6g_en <= mux_select((alpha_tolower(enable_deep_align) = ("true")), '1', '0'); + init_scan_mode <= '0'; + init_sel_gp_md <= '0'; + init_rphystatus_rst_toggle <= mux_select((phystatus_reset_toggle = ("true")), '1', '0'); + init_rrdwidth_rx <= mux_select((use_double_data_mode = ("true")), '1', '0'); + init_rrx_detect_bypass <= mux_select((rx_detect_bypass = ("true")), '1', '0'); + init_rrx_pipe_enable <= mux_select((protocol_hint = ("pcie") OR protocol_hint = ("pcie2")), '1', '0'); + init_rtx_elec_idle_delay <= "00"; + init_rtx_pipe_enable <= '0'; + init_rauto_speed_ena <= mux_select((alpha_tolower(pipe_auto_speed_nego_enable) = ("true")), '1', '0'); + init_rbytord_6g_mask_en <= mux_select((alpha_tolower(byte_order_double_data_mode_mask_enable) = ("true")), '1', '0'); + init_rbytord_s2gx <= mux_select((byte_order_back_compat_enable = ("true")), '1', '0'); + init_rclkcmp_pipe_en <= mux_select((rate_match_pipe_enable = ("true")), '1', '0'); + init_rdel_threshold <= int2bin(rate_match_delete_threshold, 5); + init_reidle_com_detect <= int2bin(elec_idle_num_com_detect, 2); + init_reidleinferenable <= mux_select((elec_idle_infer_enable = ("true")), '1', '0'); + init_rempty_threshold <= int2bin(rate_match_empty_threshold, 3); + init_renpolinv_en <= mux_select((alpha_tolower(dec_8b_10b_polarity_inv_enable) = ("true")), '1', '0'); + init_rfreq_sel <= mux_select((pipe_freq_scale_mode = ("data width")), '0', '1'); + init_rfull_threshold <= int2bin(rate_match_full_threshold, 5); + init_rind_error_reporting <= mux_select((rxstatus_error_report_mode = 0), '0', '1'); + init_rins_threshold <= int2bin(rate_match_insert_threshold, 5); + init_rinvalid_code_err_only <= mux_select((byte_order_invalid_code_or_run_disp_error = ("true")), '1', '0'); + init_rphfifourstenrx <= mux_select((ph_fifo_reset_enable = ("true")), '1', '0'); + init_rphystatus_delay <= int2bin(phystatus_delay, 3); + init_rrx_fifo_dis <= mux_select((alpha_tolower(ph_fifo_disable) = ("true")), '1', '0'); + init_rrxpcsbypass_en <= mux_select((datapath_low_latency_mode = ("true")), '1', '0'); + init_rstart_threshold <= int2bin(rate_match_start_threshold, 3); + init_rauto_deassert_pc_rst_cnt <= int2bin(auto_spd_deassert_ph_fifo_rst_count, 4); + init_rauto_pc_en_cnt <= int2bin(auto_spd_phystatus_notify_count, 5); + init_rcdr_ctrl_en <= mux_select((cdrctrl_enable = ("true")), '1', '0'); + init_rcid_en <= mux_select((cdrctrl_cid_mode_enable = ("true")), '1', '0'); + init_rcid_len_rx <= int2bin(prbs_cid_pattern_length, 8); + init_rcid_pattern_rx <= mux_select((prbs_cid_pattern = ("true")), '1', '0'); + init_rfts_count <= int2bin(cdrctrl_bypass_ppm_detector_cycle, 10); + init_rhip_ena <= mux_select((hip_enable = ("true")), '1', '0'); + init_rmask_count <= int2bin(cdrctrl_mask_cycle, 10); + IF ((channel_bonding /= "x8") OR (alpha_tolower(cycloneiv_tx_pcs_mph_fifo_xn_mapping(ph_fifo_xn_select,ph_fifo_xn_mapping0,ph_fifo_xn_mapping1,ph_fifo_xn_mapping2)) = "central")) THEN + init_rmaster_rx <= '1'; + ELSE + init_rmaster_rx <= '0'; + END IF; + -- flip + IF (alpha_tolower(cycloneiv_tx_pcs_mph_fifo_xn_mapping(ph_fifo_xn_select,ph_fifo_xn_mapping0,ph_fifo_xn_mapping1,ph_fifo_xn_mapping2)) = "down") THEN + init_rmaster_up_rx <= '1'; + ELSE + init_rmaster_up_rx <= '0'; + END IF; + init_rphfifo_regmode_rx <= mux_select((ph_fifo_reg_mode = ("true")), '1', '0'); + init_rpipeline_bypass_rx <= mux_select((alpha_tolower(iqp_bypass) = ("true")), '1', '0'); + init_rpma_done_count <= "000000000000001111"; -- int2bin(pma_done_count, 18); + init_rrxpcsclkpwdn <= mux_select((clk_pd_enable = ("true")), '1', '0'); + init_rrxvalid_mask <= mux_select((cdrctrl_rxvalid_mask = ("true")), '1', '0'); + init_rself_sw_en_rx <= mux_select((alpha_tolower(auto_spd_self_switch_enable) = ("true")), '1', '0'); + init_rtest_bus_sel <= int2bin(test_bus_sel, 4); + init_rwait_count <= int2bin(cdrctrl_min_lock_to_ref_cycle, 8); + init_rwait_for_phfifo_cnt <= int2bin(rx_phfifo_wait_cnt, 6); + init_rppm_post_eidle_del <= '0'; + init_rppm_gen1_2xcnt_en <= '0'; + + IF (elec_idle_eios_detect_priority_over_eidle_disable = "true") THEN + init_riei_eios_priority_dis <= '1'; + ELSE + init_riei_eios_priority_dis <= '0'; + END IF; + + IF (elec_idle_gen1_sigdet_enable = "true") THEN + init_rgen1_sigdet_ena <= '1'; + ELSE + init_rgen1_sigdet_ena <= '0'; + END IF; + + -- CYCLONEIV WW25.2008 ----------------------------------------------------- + IF (error_from_wa_or_8b_10b_select = "true") THEN + init_rerr_flags_sel <= '1'; + ELSE + init_rerr_flags_sel <= '0'; + END IF; + + init_rpcs_wrapback_en <= '0'; + + WAIT; + END PROCESS; + + -- Mapping Assignment -------------------------------------------------- + -- init_rcomp_pat + init_rcomp_pat_0 <= init_rcomp_pat(0); + init_rcomp_pat_1 <= init_rcomp_pat(1); + init_rcomp_pat_2 <= init_rcomp_pat(2); + init_rcomp_pat_3 <= init_rcomp_pat(3); + init_rcomp_pat_4 <= init_rcomp_pat(4); + init_rcomp_pat_5 <= init_rcomp_pat(5); + init_rcomp_pat_6 <= init_rcomp_pat(6); + init_rcomp_pat_7 <= init_rcomp_pat(7); + init_rcomp_pat_8 <= init_rcomp_pat(8); + init_rcomp_pat_9 <= init_rcomp_pat(9); + init_rcomp_pat_10 <= init_rcomp_pat(10); + init_rcomp_pat_11 <= init_rcomp_pat(11); + init_rcomp_pat_12 <= init_rcomp_pat(12); + init_rcomp_pat_13 <= init_rcomp_pat(13); + init_rcomp_pat_14 <= init_rcomp_pat(14); + init_rcomp_pat_15 <= init_rcomp_pat(15); + init_rcomp_pat_16 <= init_rcomp_pat(16); + init_rcomp_pat_17 <= init_rcomp_pat(17); + init_rcomp_pat_18 <= init_rcomp_pat(18); + init_rcomp_pat_19 <= init_rcomp_pat(19); + init_rcomp_pat_20 <= init_rcomp_pat(20); + init_rcomp_pat_21 <= init_rcomp_pat(21); + init_rcomp_pat_22 <= init_rcomp_pat(22); + init_rcomp_pat_23 <= init_rcomp_pat(23); + init_rcomp_pat_24 <= init_rcomp_pat(24); + init_rcomp_pat_25 <= init_rcomp_pat(25); + init_rcomp_pat_26 <= init_rcomp_pat(26); + init_rcomp_pat_27 <= init_rcomp_pat(27); + init_rcomp_pat_28 <= init_rcomp_pat(28); + init_rcomp_pat_29 <= init_rcomp_pat(29); + init_rcomp_pat_30 <= init_rcomp_pat(30); + init_rcomp_pat_31 <= init_rcomp_pat(31); + init_rcomp_pat_32 <= init_rcomp_pat(32); + init_rcomp_pat_33 <= init_rcomp_pat(33); + init_rcomp_pat_34 <= init_rcomp_pat(34); + init_rcomp_pat_35 <= init_rcomp_pat(35); + init_rcomp_pat_36 <= init_rcomp_pat(36); + init_rcomp_pat_37 <= init_rcomp_pat(37); + init_rcomp_pat_38 <= init_rcomp_pat(38); + init_rcomp_pat_39 <= init_rcomp_pat(39); + + --init_rclkcmpsq1p + init_rclkcmpsq1p_0 <= init_rclkcmpsq1p(0); + init_rclkcmpsq1p_1 <= init_rclkcmpsq1p(1); + init_rclkcmpsq1p_2 <= init_rclkcmpsq1p(2); + init_rclkcmpsq1p_3 <= init_rclkcmpsq1p(3); + init_rclkcmpsq1p_4 <= init_rclkcmpsq1p(4); + init_rclkcmpsq1p_5 <= init_rclkcmpsq1p(5); + init_rclkcmpsq1p_6 <= init_rclkcmpsq1p(6); + init_rclkcmpsq1p_7 <= init_rclkcmpsq1p(7); + init_rclkcmpsq1p_8 <= init_rclkcmpsq1p(8); + init_rclkcmpsq1p_9 <= init_rclkcmpsq1p(9); + init_rclkcmpsq1p_10 <= init_rclkcmpsq1p(10); + init_rclkcmpsq1p_11 <= init_rclkcmpsq1p(11); + init_rclkcmpsq1p_12 <= init_rclkcmpsq1p(12); + init_rclkcmpsq1p_13 <= init_rclkcmpsq1p(13); + init_rclkcmpsq1p_14 <= init_rclkcmpsq1p(14); + init_rclkcmpsq1p_15 <= init_rclkcmpsq1p(15); + init_rclkcmpsq1p_16 <= init_rclkcmpsq1p(16); + init_rclkcmpsq1p_17 <= init_rclkcmpsq1p(17); + init_rclkcmpsq1p_18 <= init_rclkcmpsq1p(18); + init_rclkcmpsq1p_19 <= init_rclkcmpsq1p(19); + + --init_rclkcmpsq1n + init_rclkcmpsq1n_0 <= init_rclkcmpsq1n(0); + init_rclkcmpsq1n_1 <= init_rclkcmpsq1n(1); + init_rclkcmpsq1n_2 <= init_rclkcmpsq1n(2); + init_rclkcmpsq1n_3 <= init_rclkcmpsq1n(3); + init_rclkcmpsq1n_4 <= init_rclkcmpsq1n(4); + init_rclkcmpsq1n_5 <= init_rclkcmpsq1n(5); + init_rclkcmpsq1n_6 <= init_rclkcmpsq1n(6); + init_rclkcmpsq1n_7 <= init_rclkcmpsq1n(7); + init_rclkcmpsq1n_8 <= init_rclkcmpsq1n(8); + init_rclkcmpsq1n_9 <= init_rclkcmpsq1n(9); + init_rclkcmpsq1n_10 <= init_rclkcmpsq1n(10); + init_rclkcmpsq1n_11 <= init_rclkcmpsq1n(11); + init_rclkcmpsq1n_12 <= init_rclkcmpsq1n(12); + init_rclkcmpsq1n_13 <= init_rclkcmpsq1n(13); + init_rclkcmpsq1n_14 <= init_rclkcmpsq1n(14); + init_rclkcmpsq1n_15 <= init_rclkcmpsq1n(15); + init_rclkcmpsq1n_16 <= init_rclkcmpsq1n(16); + init_rclkcmpsq1n_17 <= init_rclkcmpsq1n(17); + init_rclkcmpsq1n_18 <= init_rclkcmpsq1n(18); + init_rclkcmpsq1n_19 <= init_rclkcmpsq1n(19); + + --init_rpma_done_count + init_rpma_done_count_0 <= init_rpma_done_count(0); + init_rpma_done_count_1 <= init_rpma_done_count(1); + init_rpma_done_count_2 <= init_rpma_done_count(2); + init_rpma_done_count_3 <= init_rpma_done_count(3); + init_rpma_done_count_4 <= init_rpma_done_count(4); + init_rpma_done_count_5 <= init_rpma_done_count(5); + init_rpma_done_count_6 <= init_rpma_done_count(6); + init_rpma_done_count_7 <= init_rpma_done_count(7); + init_rpma_done_count_8 <= init_rpma_done_count(8); + init_rpma_done_count_9 <= init_rpma_done_count(9); + init_rpma_done_count_10 <= init_rpma_done_count(10); + init_rpma_done_count_11 <= init_rpma_done_count(11); + init_rpma_done_count_12 <= init_rpma_done_count(12); + init_rpma_done_count_13 <= init_rpma_done_count(13); + init_rpma_done_count_14 <= init_rpma_done_count(14); + init_rpma_done_count_15 <= init_rpma_done_count(15); + init_rpma_done_count_16 <= init_rpma_done_count(16); + init_rpma_done_count_17 <= init_rpma_done_count(17); + + --init_rbytordpat + init_rbytordpat_0 <= init_rbytordpat(0); + init_rbytordpat_1 <= init_rbytordpat(1); + init_rbytordpat_2 <= init_rbytordpat(2); + init_rbytordpat_3 <= init_rbytordpat(3); + init_rbytordpat_4 <= init_rbytordpat(4); + init_rbytordpat_5 <= init_rbytordpat(5); + init_rbytordpat_6 <= init_rbytordpat(6); + init_rbytordpat_7 <= init_rbytordpat(7); + init_rbytordpat_8 <= init_rbytordpat(8); + init_rbytordpat_9 <= init_rbytordpat(9); + init_rbytordpat_10 <= init_rbytordpat(10); + init_rbytordpat_11 <= init_rbytordpat(11); + init_rbytordpat_12 <= init_rbytordpat(12); + init_rbytordpat_13 <= init_rbytordpat(13); + init_rbytordpat_14 <= init_rbytordpat(14); + init_rbytordpat_15 <= init_rbytordpat(15); + init_rbytordpat_16 <= init_rbytordpat(16); + init_rbytordpat_17 <= init_rbytordpat(17); + init_rbytordpat_18 <= init_rbytordpat(18); + init_rbytordpat_19 <= init_rbytordpat(19); + + cram_rcomp_pat <= (cram_rcomp_pat_39 & cram_rcomp_pat_38 & cram_rcomp_pat_37 & cram_rcomp_pat_36 & cram_rcomp_pat_35 & cram_rcomp_pat_34 & cram_rcomp_pat_33 & cram_rcomp_pat_32 & cram_rcomp_pat_31 & cram_rcomp_pat_30 & + cram_rcomp_pat_29 & cram_rcomp_pat_28 & cram_rcomp_pat_27 & cram_rcomp_pat_26 & cram_rcomp_pat_25 & cram_rcomp_pat_24 & cram_rcomp_pat_23 & cram_rcomp_pat_22 & cram_rcomp_pat_21 & cram_rcomp_pat_20 & + cram_rcomp_pat_19 & cram_rcomp_pat_18 & cram_rcomp_pat_17 & cram_rcomp_pat_16 & cram_rcomp_pat_15 & cram_rcomp_pat_14 & cram_rcomp_pat_13 & cram_rcomp_pat_12 & cram_rcomp_pat_11 & cram_rcomp_pat_10 & + cram_rcomp_pat_9 & cram_rcomp_pat_8 & cram_rcomp_pat_7 & cram_rcomp_pat_6 & cram_rcomp_pat_5 & cram_rcomp_pat_4 & cram_rcomp_pat_3 & cram_rcomp_pat_2 & cram_rcomp_pat_1 & cram_rcomp_pat_0); + + cram_rclkcmpsq1p <= (cram_rclkcmpsq1p_19 & cram_rclkcmpsq1p_18 & cram_rclkcmpsq1p_17 & cram_rclkcmpsq1p_16 & cram_rclkcmpsq1p_15 & cram_rclkcmpsq1p_14 & cram_rclkcmpsq1p_13 & cram_rclkcmpsq1p_12 & cram_rclkcmpsq1p_11 & cram_rclkcmpsq1p_10 & + cram_rclkcmpsq1p_9 & cram_rclkcmpsq1p_8 & cram_rclkcmpsq1p_7 & cram_rclkcmpsq1p_6 & cram_rclkcmpsq1p_5 & cram_rclkcmpsq1p_4 & cram_rclkcmpsq1p_3 & cram_rclkcmpsq1p_2 & cram_rclkcmpsq1p_1 & cram_rclkcmpsq1p_0); + + cram_rclkcmpsq1n <= (cram_rclkcmpsq1n_19 & cram_rclkcmpsq1n_18 & cram_rclkcmpsq1n_17 & cram_rclkcmpsq1n_16 & cram_rclkcmpsq1n_15 & cram_rclkcmpsq1n_14 & cram_rclkcmpsq1n_13 & cram_rclkcmpsq1n_12 & cram_rclkcmpsq1n_11 & cram_rclkcmpsq1n_10 & + cram_rclkcmpsq1n_9 & cram_rclkcmpsq1n_8 & cram_rclkcmpsq1n_7 & cram_rclkcmpsq1n_6 & cram_rclkcmpsq1n_5 & cram_rclkcmpsq1n_4 & cram_rclkcmpsq1n_3 & cram_rclkcmpsq1n_2 & cram_rclkcmpsq1n_1 & cram_rclkcmpsq1n_0); + + cram_rpma_done_count <= (cram_rpma_done_count_17 & cram_rpma_done_count_16 & cram_rpma_done_count_15 & cram_rpma_done_count_14 & cram_rpma_done_count_13 & cram_rpma_done_count_12 & cram_rpma_done_count_11 & cram_rpma_done_count_10 & cram_rpma_done_count_9 & cram_rpma_done_count_8 & + cram_rpma_done_count_7 & cram_rpma_done_count_6 & cram_rpma_done_count_5 & cram_rpma_done_count_4 & cram_rpma_done_count_3 & cram_rpma_done_count_2 & cram_rpma_done_count_1 & cram_rpma_done_count_0); + + cram_rbytordpat <= (cram_rbytordpat_19 & cram_rbytordpat_18 & cram_rbytordpat_17 & cram_rbytordpat_16 & cram_rbytordpat_15 & cram_rbytordpat_14 & cram_rbytordpat_13 & cram_rbytordpat_12 & cram_rbytordpat_11 & cram_rbytordpat_10 & + cram_rbytordpat_9 & cram_rbytordpat_8 & cram_rbytordpat_7 & cram_rbytordpat_6 & cram_rbytordpat_5 & cram_rbytordpat_4 & cram_rbytordpat_3 & cram_rbytordpat_2 & cram_rbytordpat_1 & cram_rbytordpat_0); + + -- --------------------------------------------------------------------------- + -- Set DPRIO CRAM input from dprioin + -- --------------------------------------------------------------------------- + -- Existing + dprioin_dskwclksel <= init_dskwclksel; + dprioin_is_lane0 <= init_is_lane0; + dprioin_rbist_sel <= init_rbist_sel; + dprioin_rclkcmppos <= dprioin_in(rclkcmppos_RX_IDX); + dprioin_rcxpat_chnl_en <= init_rcxpat_chnl_en; + dprioin_rdskchrp <= init_rdskchrp; + dprioin_rdskposdisp <= init_rdskposdisp; + dprioin_rendec_data_sel_rx <= dprioin_in(rendec_data_sel_rx_RX_IDX); + dprioin_rforce0_freqdet <= dprioin_in(rforce0_freqdet_RX_IDX); + dprioin_rforce1_freqdet <= dprioin_in(rforce1_freqdet_RX_IDX); + dprioin_rindv_rx <= dprioin_in(rindv_rx_RX_IDX); + dprioin_rpma_doublewidth_rx <= dprioin_in(rpma_doublewidth_rx_RX_IDX); -- dprioin + dprioin_rpmadwidth_rx <= dprioin_in(rpmadwidth_rx_RX_IDX); -- dprioin + dprioin_rppmsel <= dprioin_in(rppmsel_RX_IDX_5 DOWNTO rppmsel_RX_IDX_0); + dprioin_rprbs_sel <= init_rprbs_sel; + dprioin_rrdwidth_rx <= dprioin_in(rdwidth_rx_RX_IDX); + dprioin_rrx_revlb_sw <= dprioin_in(rrx_revlb_sw_RX_IDX); + dprioin_rs_lpbk <= dprioin_in(rs_lpbk_RX_IDX); + dprioin_rtx_elec_idle_delay <= dprioin_in(rtx_idle_delay_RX_IDX_1 DOWNTO rtx_idle_delay_RX_IDX_0); + dprioin_rtx_pipe_enable <= init_rtx_pipe_enable; + dprioin_scan_mode <= init_scan_mode; + dprioin_sel_gp_md <= init_sel_gp_md; + + -- PCS Per Channel RX Control Register 1 for Channel 0 + dprioin_rrxpcsbypass_en <= dprioin(rrxpcsbypass_en_RXPCS_IDX_0); + dprioin_rall_one_dect_only <= dprioin(rall_one_dect_only_RXPCS_IDX_0); + dprioin_rbist_clr_rx <= dprioin(rbist_clr_rx_RXPCS_IDX_0); + dprioin_rbisten_rx <= dprioin(rbisten_rx_RXPCS_IDX_0); + dprioin_rprbs_clr_rslt_rx <= dprioin(rprbs_clr_rslt_rx_RXPCS_IDX_0); + dprioin_rprbsen_rx <= dprioin(rprbsen_rx_RXPCS_IDX_0); + dprioin_rrx_rd_clk_sel <= dprioin(rrx_rd_clk_sel_RXPCS_IDX_0); + dprioin_rclk_2_sel <= dprioin(rclk_2_sel_RXPCS_IDX_1 DOWNTO rclk_2_sel_RXPCS_IDX_0); + dprioin_rclk_1_sel <= dprioin(rclk_1_sel_RXPCS_IDX_1 DOWNTO rclk_1_sel_RXPCS_IDX_0); + dprioin_rrcvd_clk_sel <= dprioin(rrcvd_clk_sel_RXPCS_IDX_1 DOWNTO rrcvd_clk_sel_RXPCS_IDX_0); + dprioin_rfreerun_rx <= dprioin(rfreerun_rx_RXPCS_IDX_0); + dprioin_rrxurstpcs <= dprioin(rrxurstpcs_RXPCS_IDX_0); + dprioin_reserved_0_TB5 <= dprioin(reserved_0_TB5_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 2 for Channel 0 + dprioin_rcomp_pat_32 <= dprioin(rcomp_pat_32_RXPCS_IDX_0); + dprioin_rcomp_pat_33 <= dprioin(rcomp_pat_33_RXPCS_IDX_0); + dprioin_rcomp_pat_34 <= dprioin(rcomp_pat_34_RXPCS_IDX_0); + dprioin_rcomp_pat_35 <= dprioin(rcomp_pat_35_RXPCS_IDX_0); + dprioin_rcomp_pat_36 <= dprioin(rcomp_pat_36_RXPCS_IDX_0); + dprioin_rcomp_pat_37 <= dprioin(rcomp_pat_37_RXPCS_IDX_0); + dprioin_rcomp_pat_38 <= dprioin(rcomp_pat_38_RXPCS_IDX_0); + dprioin_rcomp_pat_39 <= dprioin(rcomp_pat_39_RXPCS_IDX_0); + dprioin_rcomp_size <= dprioin(rcomp_size_RXPCS_IDX_2 DOWNTO rcomp_size_RXPCS_IDX_0); + dprioin_rcomp_pat_porn <= dprioin(rcomp_pat_porn_RXPCS_IDX_0); + dprioin_rdis_rx_disp <= dprioin(rdis_rx_disp_RXPCS_IDX_0); + dprioin_rencdt_rising <= dprioin(rencdt_rising_RXPCS_IDX_0); + dprioin_resync_badcg_en <= dprioin(resync_badcg_en_RXPCS_IDX_1 DOWNTO resync_badcg_en_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 3 for Channel 0 + dprioin_rcomp_pat_16 <= dprioin(rcomp_pat_16_RXPCS_IDX_0); + dprioin_rcomp_pat_17 <= dprioin(rcomp_pat_17_RXPCS_IDX_0); + dprioin_rcomp_pat_18 <= dprioin(rcomp_pat_18_RXPCS_IDX_0); + dprioin_rcomp_pat_19 <= dprioin(rcomp_pat_19_RXPCS_IDX_0); + dprioin_rcomp_pat_20 <= dprioin(rcomp_pat_20_RXPCS_IDX_0); + dprioin_rcomp_pat_21 <= dprioin(rcomp_pat_21_RXPCS_IDX_0); + dprioin_rcomp_pat_22 <= dprioin(rcomp_pat_22_RXPCS_IDX_0); + dprioin_rcomp_pat_23 <= dprioin(rcomp_pat_23_RXPCS_IDX_0); + dprioin_rcomp_pat_24 <= dprioin(rcomp_pat_24_RXPCS_IDX_0); + dprioin_rcomp_pat_25 <= dprioin(rcomp_pat_25_RXPCS_IDX_0); + dprioin_rcomp_pat_26 <= dprioin(rcomp_pat_26_RXPCS_IDX_0); + dprioin_rcomp_pat_27 <= dprioin(rcomp_pat_27_RXPCS_IDX_0); + dprioin_rcomp_pat_28 <= dprioin(rcomp_pat_28_RXPCS_IDX_0); + dprioin_rcomp_pat_29 <= dprioin(rcomp_pat_29_RXPCS_IDX_0); + dprioin_rcomp_pat_30 <= dprioin(rcomp_pat_30_RXPCS_IDX_0); + dprioin_rcomp_pat_31 <= dprioin(rcomp_pat_31_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 4 for Channel 0 + dprioin_rcomp_pat_0 <= dprioin(rcomp_pat_0_RXPCS_IDX_0); + dprioin_rcomp_pat_1 <= dprioin(rcomp_pat_1_RXPCS_IDX_0); + dprioin_rcomp_pat_2 <= dprioin(rcomp_pat_2_RXPCS_IDX_0); + dprioin_rcomp_pat_3 <= dprioin(rcomp_pat_3_RXPCS_IDX_0); + dprioin_rcomp_pat_4 <= dprioin(rcomp_pat_4_RXPCS_IDX_0); + dprioin_rcomp_pat_5 <= dprioin(rcomp_pat_5_RXPCS_IDX_0); + dprioin_rcomp_pat_6 <= dprioin(rcomp_pat_6_RXPCS_IDX_0); + dprioin_rcomp_pat_7 <= dprioin(rcomp_pat_7_RXPCS_IDX_0); + dprioin_rcomp_pat_8 <= dprioin(rcomp_pat_8_RXPCS_IDX_0); + dprioin_rcomp_pat_9 <= dprioin(rcomp_pat_9_RXPCS_IDX_0); + dprioin_rcomp_pat_10 <= dprioin(rcomp_pat_10_RXPCS_IDX_0); + dprioin_rcomp_pat_11 <= dprioin(rcomp_pat_11_RXPCS_IDX_0); + dprioin_rcomp_pat_12 <= dprioin(rcomp_pat_12_RXPCS_IDX_0); + dprioin_rcomp_pat_13 <= dprioin(rcomp_pat_13_RXPCS_IDX_0); + dprioin_rcomp_pat_14 <= dprioin(rcomp_pat_14_RXPCS_IDX_0); + dprioin_rcomp_pat_15 <= dprioin(rcomp_pat_15_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 5 for Channel 0 + dprioin_rbitloc_rev_en <= dprioin(rbitloc_rev_en_RXPCS_IDX_0); + dprioin_rbysync_polinv_en <= dprioin(rbysync_polinv_en_RXPCS_IDX_0); + dprioin_rwa_6g_en <= dprioin(rwa_6g_en_RXPCS_IDX_0); + dprioin_rosnumber <= dprioin(rosnumber_RXPCS_IDX_1 DOWNTO rosnumber_RXPCS_IDX_0); + dprioin_rosbased <= dprioin(rosbased_RXPCS_IDX_0); + dprioin_rkchar <= dprioin(rkchar_RXPCS_IDX_0); + dprioin_renumber <= dprioin(renumber_RXPCS_IDX_5 DOWNTO renumber_RXPCS_IDX_0); + dprioin_rib_inv_cd <= dprioin(rib_inv_cd_RXPCS_IDX_1 DOWNTO rib_inv_cd_RXPCS_IDX_0); + dprioin_rsync_sm_dis <= dprioin(rsync_sm_dis_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 6 for Channel 0 + dprioin_rknumber <= dprioin(rknumber_RXPCS_IDX_7 DOWNTO rknumber_RXPCS_IDX_0); + dprioin_rgnumber <= dprioin(rgnumber_RXPCS_IDX_7 DOWNTO rgnumber_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 7 for Channel 0 + dprioin_renpolinv_rx <= dprioin(renpolinv_rx_RXPCS_IDX_0); + dprioin_rcascaded_8b10b_en_rx <= dprioin(rcascaded_8b10b_en_rx_RXPCS_IDX_0); + dprioin_r8b10b_dec_ibm_en <= dprioin(r8b10b_dec_ibm_en_RXPCS_IDX_1 DOWNTO r8b10b_dec_ibm_en_RXPCS_IDX_0); + dprioin_rendec_rx <= dprioin(rendec_rx_RXPCS_IDX_0); + dprioin_rautobtalg_dis <= dprioin(rautobtalg_dis_RXPCS_IDX_0); + dprioin_rrlv_en <= dprioin(rrlv_en_RXPCS_IDX_0); + dprioin_rlp20ben <= dprioin(rlp20ben_RXPCS_IDX_0); + dprioin_rforce_sig_det_pcs <= dprioin(rforce_sig_det_pcs_RXPCS_IDX_0); + dprioin_rbyte_rev_en <= dprioin(rbyte_rev_en_RXPCS_IDX_0); + dprioin_rrundisp <= dprioin(rrundisp_RXPCS_IDX_5 DOWNTO rrundisp_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 8 for Channel 0 + dprioin_rclkcmpsq1p_0 <= dprioin(rclkcmpsq1p_0_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_1 <= dprioin(rclkcmpsq1p_1_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_2 <= dprioin(rclkcmpsq1p_2_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_3 <= dprioin(rclkcmpsq1p_3_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_4 <= dprioin(rclkcmpsq1p_4_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_5 <= dprioin(rclkcmpsq1p_5_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_6 <= dprioin(rclkcmpsq1p_6_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_7 <= dprioin(rclkcmpsq1p_7_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_8 <= dprioin(rclkcmpsq1p_8_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_9 <= dprioin(rclkcmpsq1p_9_RXPCS_IDX_0); + dprioin_rclkcmpsqmd <= dprioin(rclkcmpsqmd_RXPCS_IDX_0); + dprioin_rclkcmpinsertpad <= dprioin(rclkcmpinsertpad_RXPCS_IDX_0); + dprioin_rtruebac2bac <= dprioin(rtruebac2bac_RXPCS_IDX_0); + dprioin_rskpsetbased <= dprioin(rskpsetbased_RXPCS_IDX_0); + dprioin_rgenericfifo <= dprioin(rgenericfifo_RXPCS_IDX_0); + dprioin_rmatchen <= dprioin(rmatchen_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 9 for Channel 0 + dprioin_rclkcmpsq1p_10 <= dprioin(rclkcmpsq1p_10_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_11 <= dprioin(rclkcmpsq1p_11_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_12 <= dprioin(rclkcmpsq1p_12_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_13 <= dprioin(rclkcmpsq1p_13_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_14 <= dprioin(rclkcmpsq1p_14_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_15 <= dprioin(rclkcmpsq1p_15_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_16 <= dprioin(rclkcmpsq1p_16_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_17 <= dprioin(rclkcmpsq1p_17_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_18 <= dprioin(rclkcmpsq1p_18_RXPCS_IDX_0); + dprioin_rclkcmpsq1p_19 <= dprioin(rclkcmpsq1p_19_RXPCS_IDX_0); + dprioin_reserved_0_TB13 <= dprioin(reserved_0_TB13_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_15 <= dprioin(rclkcmpsq1n_15_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_16 <= dprioin(rclkcmpsq1n_16_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_17 <= dprioin(rclkcmpsq1n_17_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_18 <= dprioin(rclkcmpsq1n_18_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_19 <= dprioin(rclkcmpsq1n_19_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 10 for Channel 0 + dprioin_rclkcmpsq1n_0 <= dprioin(rclkcmpsq1n_0_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_1 <= dprioin(rclkcmpsq1n_1_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_2 <= dprioin(rclkcmpsq1n_2_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_3 <= dprioin(rclkcmpsq1n_3_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_4 <= dprioin(rclkcmpsq1n_4_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_5 <= dprioin(rclkcmpsq1n_5_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_6 <= dprioin(rclkcmpsq1n_6_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_7 <= dprioin(rclkcmpsq1n_7_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_8 <= dprioin(rclkcmpsq1n_8_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_9 <= dprioin(rclkcmpsq1n_9_RXPCS_IDX_0); + dprioin_reserved_0_TB14 <= dprioin(reserved_0_TB14_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_10 <= dprioin(rclkcmpsq1n_10_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_11 <= dprioin(rclkcmpsq1n_11_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_12 <= dprioin(rclkcmpsq1n_12_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_13 <= dprioin(rclkcmpsq1n_13_RXPCS_IDX_0); + dprioin_rclkcmpsq1n_14 <= dprioin(rclkcmpsq1n_14_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 11 for Channel 0 + dprioin_rfull_threshold <= dprioin(rfull_threshold_RXPCS_IDX_4 DOWNTO rfull_threshold_RXPCS_IDX_0); + dprioin_rdel_threshold <= dprioin(rdel_threshold_RXPCS_IDX_4 DOWNTO rdel_threshold_RXPCS_IDX_0); + dprioin_rins_threshold <= dprioin(rins_threshold_RXPCS_IDX_4 DOWNTO rins_threshold_RXPCS_IDX_0); + dprioin_rclkcmp_pipe_en <= dprioin(rclkcmp_pipe_en_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 12 for Channel 0 + dprioin_rfreq_sel <= dprioin(rfreq_sel_RXPCS_IDX_0); + dprioin_rauto_speed_ena <= dprioin(rauto_speed_ena_RXPCS_IDX_0); + dprioin_rhip_ena <= dprioin(rhip_ena_RXPCS_IDX_0); + dprioin_rpma_done_gen_ena <= dprioin(rpma_done_gen_ena_RXPCS_IDX_0); + dprioin_rpma_done_count_16 <= dprioin(rpma_done_count_16_RXPCS_IDX_0); + dprioin_rpma_done_count_17 <= dprioin(rpma_done_count_17_RXPCS_IDX_0); + dprioin_reserved_0_TB16 <= dprioin(reserved_0_TB16_RXPCS_IDX_3 DOWNTO reserved_0_TB16_RXPCS_IDX_0); + dprioin_rstart_threshold <= dprioin(rstart_threshold_RXPCS_IDX_2 DOWNTO rstart_threshold_RXPCS_IDX_0); + dprioin_rempty_threshold <= dprioin(rempty_threshold_RXPCS_IDX_2 DOWNTO rempty_threshold_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 13 for Channel 0 + dprioin_rtest_bus_sel <= dprioin(rtest_bus_sel_RXPCS_IDX_3 DOWNTO rtest_bus_sel_RXPCS_IDX_0); + dprioin_rautoinsdis <= dprioin(rautoinsdis_RXPCS_IDX_0); + dprioin_rphfifopldenrx <= dprioin(rphfifopldenrx_RXPCS_IDX_0); + dprioin_rbytordplden <= dprioin(rbytordplden_RXPCS_IDX_0); + dprioin_rbyteorden <= dprioin(rbyteorden_RXPCS_IDX_1 DOWNTO rbyteorden_RXPCS_IDX_0); + dprioin_rbytord_2sym_en <= dprioin(rbytord_2sym_en_RXPCS_IDX_0); + dprioin_rinvalid_code_err_only <= dprioin(rinvalid_code_err_only_RXPCS_IDX_0); + dprioin_rcmpfifourst <= dprioin(rcmpfifourst_RXPCS_IDX_0); + dprioin_rphfifourstrx <= dprioin(rphfifourstrx_RXPCS_IDX_0); + dprioin_rdwidth_rx <= dprioin(rdwidth_rx_RXPCS_IDX_0); + dprioin_rrxfifo_lowlatency_en <= dprioin(rrxfifo_lowlatency_en_RXPCS_IDX_0); + dprioin_rrxfifo_dis <= dprioin(rrxfifo_dis_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 14 for Channel 0 + dprioin_rbytordpat_0 <= dprioin(rbytordpat_0_RXPCS_IDX_0); + dprioin_rbytordpat_1 <= dprioin(rbytordpat_1_RXPCS_IDX_0); + dprioin_rbytordpat_2 <= dprioin(rbytordpat_2_RXPCS_IDX_0); + dprioin_rbytordpat_3 <= dprioin(rbytordpat_3_RXPCS_IDX_0); + dprioin_rbytordpat_4 <= dprioin(rbytordpat_4_RXPCS_IDX_0); + dprioin_rbytordpat_5 <= dprioin(rbytordpat_5_RXPCS_IDX_0); + dprioin_rbytordpat_6 <= dprioin(rbytordpat_6_RXPCS_IDX_0); + dprioin_rbytordpat_7 <= dprioin(rbytordpat_7_RXPCS_IDX_0); + dprioin_rbytordpat_8 <= dprioin(rbytordpat_8_RXPCS_IDX_0); + dprioin_rbytordpat_9 <= dprioin(rbytordpat_9_RXPCS_IDX_0); + dprioin_reserved_0_TB18 <= dprioin(reserved_0_TB18_RXPCS_IDX_5 DOWNTO reserved_0_TB18_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 15 for Channel 0 + dprioin_rbytordpad <= dprioin(rbytordpad_RXPCS_IDX_9 DOWNTO rbytordpad_RXPCS_IDX_0); + dprioin_reserved_0_TB19 <= dprioin(reserved_0_TB19_RXPCS_IDX_5 DOWNTO reserved_0_TB19_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 16 for Channel 0 + dprioin_rload_shreg_del <= dprioin(rload_shreg_del_RXPCS_IDX_4 DOWNTO rload_shreg_del_RXPCS_IDX_0); + dprioin_rphystatus_rst_toggle <= dprioin(rphystatus_rst_toggle_RXPCS_IDX_0); + dprioin_reidle_com_detect <= dprioin(reidle_com_detect_RXPCS_IDX_1 DOWNTO reidle_com_detect_RXPCS_IDX_0); + dprioin_rk285detect <= dprioin(rk285detect_RXPCS_IDX_0); + dprioin_reidleinferenable <= dprioin(reidleinferenable_RXPCS_IDX_0); + dprioin_rphystatus_delay <= dprioin(rphystatus_delay_RXPCS_IDX_2 DOWNTO rphystatus_delay_RXPCS_IDX_0); + dprioin_rind_error_reporting <= dprioin(rind_error_reporting_RXPCS_IDX_0); + dprioin_rrx_detect_bypass <= dprioin(rrx_detect_bypass_RXPCS_IDX_0); + dprioin_rrx_pipe_enable <= dprioin(rrx_pipe_enable_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 17 for Channel 0 + dprioin_rpma_done_count_0 <= dprioin(rpma_done_count_0_RXPCS_IDX_0); + dprioin_rpma_done_count_1 <= dprioin(rpma_done_count_1_RXPCS_IDX_0); + dprioin_rpma_done_count_2 <= dprioin(rpma_done_count_2_RXPCS_IDX_0); + dprioin_rpma_done_count_3 <= dprioin(rpma_done_count_3_RXPCS_IDX_0); + dprioin_rpma_done_count_4 <= dprioin(rpma_done_count_4_RXPCS_IDX_0); + dprioin_rpma_done_count_5 <= dprioin(rpma_done_count_5_RXPCS_IDX_0); + dprioin_rpma_done_count_6 <= dprioin(rpma_done_count_6_RXPCS_IDX_0); + dprioin_rpma_done_count_7 <= dprioin(rpma_done_count_7_RXPCS_IDX_0); + dprioin_rpma_done_count_8 <= dprioin(rpma_done_count_8_RXPCS_IDX_0); + dprioin_rpma_done_count_9 <= dprioin(rpma_done_count_9_RXPCS_IDX_0); + dprioin_rpma_done_count_10 <= dprioin(rpma_done_count_10_RXPCS_IDX_0); + dprioin_rpma_done_count_11 <= dprioin(rpma_done_count_11_RXPCS_IDX_0); + dprioin_rpma_done_count_12 <= dprioin(rpma_done_count_12_RXPCS_IDX_0); + dprioin_rpma_done_count_13 <= dprioin(rpma_done_count_13_RXPCS_IDX_0); + dprioin_rpma_done_count_14 <= dprioin(rpma_done_count_14_RXPCS_IDX_0); + dprioin_rpma_done_count_15 <= dprioin(rpma_done_count_15_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 18 for Channel 0 + dprioin_rbytordpat_10 <= dprioin(rbytordpat_10_RXPCS_IDX_0); + dprioin_rbytordpat_11 <= dprioin(rbytordpat_11_RXPCS_IDX_0); + dprioin_rbytordpat_12 <= dprioin(rbytordpat_12_RXPCS_IDX_0); + dprioin_rbytordpat_13 <= dprioin(rbytordpat_13_RXPCS_IDX_0); + dprioin_rbytordpat_14 <= dprioin(rbytordpat_14_RXPCS_IDX_0); + dprioin_rbytordpat_15 <= dprioin(rbytordpat_15_RXPCS_IDX_0); + dprioin_rbytordpat_16 <= dprioin(rbytordpat_16_RXPCS_IDX_0); + dprioin_rbytordpat_17 <= dprioin(rbytordpat_17_RXPCS_IDX_0); + dprioin_rbytordpat_18 <= dprioin(rbytordpat_18_RXPCS_IDX_0); + dprioin_rbytordpat_19 <= dprioin(rbytordpat_19_RXPCS_IDX_0); + dprioin_rbytord_6g_mask_en <= dprioin(rbytord_6g_mask_en_RXPCS_IDX_0); + dprioin_rbytord_s2gx <= dprioin(rbytord_s2gx_RXPCS_IDX_0); + dprioin_reserved_0_TB22 <= dprioin(reserved_0_TB22_RXPCS_IDX_0); + dprioin_rcdr_ctrl_en <= dprioin(rcdr_ctrl_en_RXPCS_IDX_0); + dprioin_rrxpcsclkpwdn <= dprioin(rrxpcsclkpwdn_RXPCS_IDX_0); + dprioin_rerr_flags_sel <= dprioin(rerr_flags_sel_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 19 for Channel 0 + dprioin_rwait_count <= dprioin(rwait_count_RXPCS_IDX_7 DOWNTO rwait_count_RXPCS_IDX_0); + dprioin_reserved_0_TB23 <= dprioin(reserved_0_TB23_RXPCS_IDX_7 DOWNTO reserved_0_TB23_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 20 for Channel 0 + dprioin_rfts_count <= dprioin(rfts_count_RXPCS_IDX_9 DOWNTO rfts_count_RXPCS_IDX_0); + dprioin_rwait_for_phfifo_cnt <= dprioin(rwait_for_phfifo_cnt_RXPCS_IDX_5 DOWNTO rwait_for_phfifo_cnt_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 21 for Channel 0 + dprioin_rppm_meas_delay <= dprioin(rppm_meas_delay_RXPCS_IDX_0); + dprioin_rcid_len_rx <= dprioin(rcid_len_rx_RXPCS_IDX_7 DOWNTO rcid_len_rx_RXPCS_IDX_0); + dprioin_rcid_pattern_rx <= dprioin(rcid_pattern_rx_RXPCS_IDX_0); + dprioin_rpcs_wrapback_en <= dprioin(rpcs_wrapback_en_RXPCS_IDX_0); + dprioin_reserved_0_TB25 <= dprioin(reserved_0_TB25_RXPCS_IDX_4 DOWNTO reserved_0_TB25_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 22 for Channel 0 + dprioin_rauto_pc_en_cnt <= dprioin(rauto_pc_en_cnt_RXPCS_IDX_4 DOWNTO rauto_pc_en_cnt_RXPCS_IDX_0); + dprioin_reserved_1_TB26 <= dprioin(reserved_1_TB26_RXPCS_IDX_0); + dprioin_rauto_deassert_pc_rst_cnt <= dprioin(rauto_deassert_pc_rst_cnt_RXPCS_IDX_3 DOWNTO rauto_deassert_pc_rst_cnt_RXPCS_IDX_0); + dprioin_reserved_0_TB26 <= dprioin(reserved_0_TB26_RXPCS_IDX_0); + dprioin_rpipeline_bypass_rx <= dprioin(rpipeline_bypass_rx_RXPCS_IDX_0); + dprioin_rself_sw_en_rx <= dprioin(rself_sw_en_rx_RXPCS_IDX_0); + dprioin_rrxvalid_mask <= dprioin(rrxvalid_mask_RXPCS_IDX_0); + dprioin_rcid_en <= dprioin(rcid_en_RXPCS_IDX_0); + dprioin_rphfifo_regmode_rx <= dprioin(rphfifo_regmode_rx_RXPCS_IDX_0); + + -- PCS Per Channel RX Control Register 23 for Channel 0 + dprioin_rmask_count <= dprioin(rmask_count_RXPCS_IDX_9 DOWNTO rmask_count_RXPCS_IDX_0); + dprioin_rgen1_sigdet_ena <= dprioin(rgen1_sigdet_ena_RXPCS_IDX_0); + dprioin_riei_eios_priority_dis <= dprioin(riei_eios_priority_dis_RXPCS_IDX_0); + dprioin_reserved_0_TB27 <= dprioin(reserved_0_TB27_RXPCS_IDX_3 DOWNTO reserved_0_TB27_RXPCS_IDX_0); + + -- --------------------------------------------------------------------------- + -- Set DPRIO output from initial CRAM + -- --------------------------------------------------------------------------- + -- Existing + dprioout(rclkcmppos_RX_IDX) <= init_rclkcmppos; + dprioout(rendec_data_sel_rx_RX_IDX) <= init_rendec_data_sel_rx; + dprioout(rforce0_freqdet_RX_IDX) <= init_rforce0_freqdet; + dprioout(rforce1_freqdet_RX_IDX) <= init_rforce1_freqdet; + dprioout(rindv_rx_RX_IDX) <= init_rindv_rx; + dprioout(rpma_doublewidth_rx_RX_IDX) <= init_rpma_doublewidth_rx; + dprioout(rpmadwidth_rx_RX_IDX) <= init_rpmadwidth_rx; + dprioout(rppmsel_RX_IDX_5 DOWNTO rppmsel_RX_IDX_0) <= init_rppmsel; + dprioout(rdwidth_rx_RX_IDX) <= init_rrdwidth_rx; + dprioout(rtx_idle_delay_RX_IDX_1 DOWNTO rtx_idle_delay_RX_IDX_0) <= init_rtx_elec_idle_delay; + + -- PCS Per Channel RX Control Register 1 for Channel 0 + dprioout(rrxpcsbypass_en_RXPCS_IDX_0) <= init_rrxpcsbypass_en; + dprioout(rall_one_dect_only_RXPCS_IDX_0) <= init_rall_one_dect_only; + dprioout(rbist_clr_rx_RXPCS_IDX_0) <= init_rbist_clr_rx; + dprioout(rbisten_rx_RXPCS_IDX_0) <= init_rbisten_rx; + dprioout(rprbs_clr_rslt_rx_RXPCS_IDX_0) <= init_rprbs_clr_rslt_rx; + dprioout(rprbsen_rx_RXPCS_IDX_0) <= init_rprbsen_rx; + dprioout(rrx_rd_clk_sel_RXPCS_IDX_0) <= init_rrx_rd_clk_sel; + dprioout(rclk_2_sel_RXPCS_IDX_1 DOWNTO rclk_2_sel_RXPCS_IDX_0) <= init_rclk_2_sel; + dprioout(rclk_1_sel_RXPCS_IDX_1 DOWNTO rclk_1_sel_RXPCS_IDX_0) <= init_rclk_1_sel; + dprioout(rrcvd_clk_sel_RXPCS_IDX_1 DOWNTO rrcvd_clk_sel_RXPCS_IDX_0) <= init_rrcvd_clk_sel; + dprioout(rfreerun_rx_RXPCS_IDX_0) <= init_rfreerun_rx; + dprioout(rrxurstpcs_RXPCS_IDX_0) <= init_rrxurstpcs; + dprioout(reserved_0_TB5_RXPCS_IDX_0) <= init_reserved_0_TB5; + + -- PCS Per Channel RX Control Register 2 for Channel 0 + dprioout(rcomp_pat_32_RXPCS_IDX_0) <= init_rcomp_pat_32; + dprioout(rcomp_pat_33_RXPCS_IDX_0) <= init_rcomp_pat_33; + dprioout(rcomp_pat_34_RXPCS_IDX_0) <= init_rcomp_pat_34; + dprioout(rcomp_pat_35_RXPCS_IDX_0) <= init_rcomp_pat_35; + dprioout(rcomp_pat_36_RXPCS_IDX_0) <= init_rcomp_pat_36; + dprioout(rcomp_pat_37_RXPCS_IDX_0) <= init_rcomp_pat_37; + dprioout(rcomp_pat_38_RXPCS_IDX_0) <= init_rcomp_pat_38; + dprioout(rcomp_pat_39_RXPCS_IDX_0) <= init_rcomp_pat_39; + dprioout(rcomp_size_RXPCS_IDX_2 DOWNTO rcomp_size_RXPCS_IDX_0) <= init_rcomp_size; + dprioout(rcomp_pat_porn_RXPCS_IDX_0) <= init_rcomp_pat_porn; + dprioout(rdis_rx_disp_RXPCS_IDX_0) <= init_rdis_rx_disp; + dprioout(rencdt_rising_RXPCS_IDX_0) <= init_rencdt_rising; + dprioout(resync_badcg_en_RXPCS_IDX_1 DOWNTO resync_badcg_en_RXPCS_IDX_0) <= init_resync_badcg_en; + + -- PCS Per Channel RX Control Register 3 for Channel 0 + dprioout(rcomp_pat_16_RXPCS_IDX_0) <= init_rcomp_pat_16; + dprioout(rcomp_pat_17_RXPCS_IDX_0) <= init_rcomp_pat_17; + dprioout(rcomp_pat_18_RXPCS_IDX_0) <= init_rcomp_pat_18; + dprioout(rcomp_pat_19_RXPCS_IDX_0) <= init_rcomp_pat_19; + dprioout(rcomp_pat_20_RXPCS_IDX_0) <= init_rcomp_pat_20; + dprioout(rcomp_pat_21_RXPCS_IDX_0) <= init_rcomp_pat_21; + dprioout(rcomp_pat_22_RXPCS_IDX_0) <= init_rcomp_pat_22; + dprioout(rcomp_pat_23_RXPCS_IDX_0) <= init_rcomp_pat_23; + dprioout(rcomp_pat_24_RXPCS_IDX_0) <= init_rcomp_pat_24; + dprioout(rcomp_pat_25_RXPCS_IDX_0) <= init_rcomp_pat_25; + dprioout(rcomp_pat_26_RXPCS_IDX_0) <= init_rcomp_pat_26; + dprioout(rcomp_pat_27_RXPCS_IDX_0) <= init_rcomp_pat_27; + dprioout(rcomp_pat_28_RXPCS_IDX_0) <= init_rcomp_pat_28; + dprioout(rcomp_pat_29_RXPCS_IDX_0) <= init_rcomp_pat_29; + dprioout(rcomp_pat_30_RXPCS_IDX_0) <= init_rcomp_pat_30; + dprioout(rcomp_pat_31_RXPCS_IDX_0) <= init_rcomp_pat_31; + + -- PCS Per Channel RX Control Register 4 for Channel 0 + dprioout(rcomp_pat_0_RXPCS_IDX_0) <= init_rcomp_pat_0; + dprioout(rcomp_pat_1_RXPCS_IDX_0) <= init_rcomp_pat_1; + dprioout(rcomp_pat_2_RXPCS_IDX_0) <= init_rcomp_pat_2; + dprioout(rcomp_pat_3_RXPCS_IDX_0) <= init_rcomp_pat_3; + dprioout(rcomp_pat_4_RXPCS_IDX_0) <= init_rcomp_pat_4; + dprioout(rcomp_pat_5_RXPCS_IDX_0) <= init_rcomp_pat_5; + dprioout(rcomp_pat_6_RXPCS_IDX_0) <= init_rcomp_pat_6; + dprioout(rcomp_pat_7_RXPCS_IDX_0) <= init_rcomp_pat_7; + dprioout(rcomp_pat_8_RXPCS_IDX_0) <= init_rcomp_pat_8; + dprioout(rcomp_pat_9_RXPCS_IDX_0) <= init_rcomp_pat_9; + dprioout(rcomp_pat_10_RXPCS_IDX_0) <= init_rcomp_pat_10; + dprioout(rcomp_pat_11_RXPCS_IDX_0) <= init_rcomp_pat_11; + dprioout(rcomp_pat_12_RXPCS_IDX_0) <= init_rcomp_pat_12; + dprioout(rcomp_pat_13_RXPCS_IDX_0) <= init_rcomp_pat_13; + dprioout(rcomp_pat_14_RXPCS_IDX_0) <= init_rcomp_pat_14; + dprioout(rcomp_pat_15_RXPCS_IDX_0) <= init_rcomp_pat_15; + + -- PCS Per Channel RX Control Register 5 for Channel 0 + dprioout(rbitloc_rev_en_RXPCS_IDX_0) <= init_rbitloc_rev_en; + dprioout(rbysync_polinv_en_RXPCS_IDX_0) <= init_rbysync_polinv_en; + dprioout(rwa_6g_en_RXPCS_IDX_0) <= init_rwa_6g_en; + dprioout(rosnumber_RXPCS_IDX_1 DOWNTO rosnumber_RXPCS_IDX_0) <= init_rosnumber; + dprioout(rosbased_RXPCS_IDX_0) <= init_rosbased; + dprioout(rkchar_RXPCS_IDX_0) <= init_rkchar; + dprioout(renumber_RXPCS_IDX_5 DOWNTO renumber_RXPCS_IDX_0) <= init_renumber; + dprioout(rib_inv_cd_RXPCS_IDX_1 DOWNTO rib_inv_cd_RXPCS_IDX_0) <= init_rib_inv_cd; + dprioout(rsync_sm_dis_RXPCS_IDX_0) <= init_rsync_sm_dis; + + -- PCS Per Channel RX Control Register 6 for Channel 0 + dprioout(rknumber_RXPCS_IDX_7 DOWNTO rknumber_RXPCS_IDX_0) <= init_rknumber; + dprioout(rgnumber_RXPCS_IDX_7 DOWNTO rgnumber_RXPCS_IDX_0) <= init_rgnumber; + + -- PCS Per Channel RX Control Register 7 for Channel 0 + dprioout(renpolinv_rx_RXPCS_IDX_0) <= init_renpolinv_rx; + dprioout(rcascaded_8b10b_en_rx_RXPCS_IDX_0) <= init_rcascaded_8b10b_en_rx; + dprioout(r8b10b_dec_ibm_en_RXPCS_IDX_1 DOWNTO r8b10b_dec_ibm_en_RXPCS_IDX_0) <= init_r8b10b_dec_ibm_en; + dprioout(rendec_rx_RXPCS_IDX_0) <= init_rendec_rx; + dprioout(rautobtalg_dis_RXPCS_IDX_0) <= init_rautobtalg_dis; + dprioout(rrlv_en_RXPCS_IDX_0) <= init_rrlv_en; + dprioout(rlp20ben_RXPCS_IDX_0) <= init_rlp20ben; + dprioout(rforce_sig_det_pcs_RXPCS_IDX_0) <= init_rforce_sig_det_pcs; + dprioout(rbyte_rev_en_RXPCS_IDX_0) <= init_rbyte_rev_en; + dprioout(rrundisp_RXPCS_IDX_5 DOWNTO rrundisp_RXPCS_IDX_0) <= init_rrundisp; + + -- PCS Per Channel RX Control Register 8 for Channel 0 + dprioout(rclkcmpsq1p_0_RXPCS_IDX_0) <= init_rclkcmpsq1p_0; + dprioout(rclkcmpsq1p_1_RXPCS_IDX_0) <= init_rclkcmpsq1p_1; + dprioout(rclkcmpsq1p_2_RXPCS_IDX_0) <= init_rclkcmpsq1p_2; + dprioout(rclkcmpsq1p_3_RXPCS_IDX_0) <= init_rclkcmpsq1p_3; + dprioout(rclkcmpsq1p_4_RXPCS_IDX_0) <= init_rclkcmpsq1p_4; + dprioout(rclkcmpsq1p_5_RXPCS_IDX_0) <= init_rclkcmpsq1p_5; + dprioout(rclkcmpsq1p_6_RXPCS_IDX_0) <= init_rclkcmpsq1p_6; + dprioout(rclkcmpsq1p_7_RXPCS_IDX_0) <= init_rclkcmpsq1p_7; + dprioout(rclkcmpsq1p_8_RXPCS_IDX_0) <= init_rclkcmpsq1p_8; + dprioout(rclkcmpsq1p_9_RXPCS_IDX_0) <= init_rclkcmpsq1p_9; + dprioout(rclkcmpsqmd_RXPCS_IDX_0) <= init_rclkcmpsqmd; + dprioout(rclkcmpinsertpad_RXPCS_IDX_0) <= init_rclkcmpinsertpad; + dprioout(rtruebac2bac_RXPCS_IDX_0) <= init_rtruebac2bac; + dprioout(rskpsetbased_RXPCS_IDX_0) <= init_rskpsetbased; + dprioout(rgenericfifo_RXPCS_IDX_0) <= init_rgenericfifo; + dprioout(rmatchen_RXPCS_IDX_0) <= init_rmatchen; + + -- PCS Per Channel RX Control Register 9 for Channel 0 + dprioout(rclkcmpsq1p_10_RXPCS_IDX_0) <= init_rclkcmpsq1p_10; + dprioout(rclkcmpsq1p_11_RXPCS_IDX_0) <= init_rclkcmpsq1p_11; + dprioout(rclkcmpsq1p_12_RXPCS_IDX_0) <= init_rclkcmpsq1p_12; + dprioout(rclkcmpsq1p_13_RXPCS_IDX_0) <= init_rclkcmpsq1p_13; + dprioout(rclkcmpsq1p_14_RXPCS_IDX_0) <= init_rclkcmpsq1p_14; + dprioout(rclkcmpsq1p_15_RXPCS_IDX_0) <= init_rclkcmpsq1p_15; + dprioout(rclkcmpsq1p_16_RXPCS_IDX_0) <= init_rclkcmpsq1p_16; + dprioout(rclkcmpsq1p_17_RXPCS_IDX_0) <= init_rclkcmpsq1p_17; + dprioout(rclkcmpsq1p_18_RXPCS_IDX_0) <= init_rclkcmpsq1p_18; + dprioout(rclkcmpsq1p_19_RXPCS_IDX_0) <= init_rclkcmpsq1p_19; + dprioout(reserved_0_TB13_RXPCS_IDX_0) <= init_reserved_0_TB13; + dprioout(rclkcmpsq1n_15_RXPCS_IDX_0) <= init_rclkcmpsq1n_15; + dprioout(rclkcmpsq1n_16_RXPCS_IDX_0) <= init_rclkcmpsq1n_16; + dprioout(rclkcmpsq1n_17_RXPCS_IDX_0) <= init_rclkcmpsq1n_17; + dprioout(rclkcmpsq1n_18_RXPCS_IDX_0) <= init_rclkcmpsq1n_18; + dprioout(rclkcmpsq1n_19_RXPCS_IDX_0) <= init_rclkcmpsq1n_19; + + -- PCS Per Channel RX Control Register 10 for Channel 0 + dprioout(rclkcmpsq1n_0_RXPCS_IDX_0) <= init_rclkcmpsq1n_0; + dprioout(rclkcmpsq1n_1_RXPCS_IDX_0) <= init_rclkcmpsq1n_1; + dprioout(rclkcmpsq1n_2_RXPCS_IDX_0) <= init_rclkcmpsq1n_2; + dprioout(rclkcmpsq1n_3_RXPCS_IDX_0) <= init_rclkcmpsq1n_3; + dprioout(rclkcmpsq1n_4_RXPCS_IDX_0) <= init_rclkcmpsq1n_4; + dprioout(rclkcmpsq1n_5_RXPCS_IDX_0) <= init_rclkcmpsq1n_5; + dprioout(rclkcmpsq1n_6_RXPCS_IDX_0) <= init_rclkcmpsq1n_6; + dprioout(rclkcmpsq1n_7_RXPCS_IDX_0) <= init_rclkcmpsq1n_7; + dprioout(rclkcmpsq1n_8_RXPCS_IDX_0) <= init_rclkcmpsq1n_8; + dprioout(rclkcmpsq1n_9_RXPCS_IDX_0) <= init_rclkcmpsq1n_9; + dprioout(reserved_0_TB14_RXPCS_IDX_0) <= init_reserved_0_TB14; + dprioout(rclkcmpsq1n_10_RXPCS_IDX_0) <= init_rclkcmpsq1n_10; + dprioout(rclkcmpsq1n_11_RXPCS_IDX_0) <= init_rclkcmpsq1n_11; + dprioout(rclkcmpsq1n_12_RXPCS_IDX_0) <= init_rclkcmpsq1n_12; + dprioout(rclkcmpsq1n_13_RXPCS_IDX_0) <= init_rclkcmpsq1n_13; + dprioout(rclkcmpsq1n_14_RXPCS_IDX_0) <= init_rclkcmpsq1n_14; + + -- PCS Per Channel RX Control Register 11 for Channel 0 + dprioout(rfull_threshold_RXPCS_IDX_4 DOWNTO rfull_threshold_RXPCS_IDX_0) <= init_rfull_threshold; + dprioout(rdel_threshold_RXPCS_IDX_4 DOWNTO rdel_threshold_RXPCS_IDX_0) <= init_rdel_threshold; + dprioout(rins_threshold_RXPCS_IDX_4 DOWNTO rins_threshold_RXPCS_IDX_0) <= init_rins_threshold; + dprioout(rclkcmp_pipe_en_RXPCS_IDX_0) <= init_rclkcmp_pipe_en; + + -- PCS Per Channel RX Control Register 12 for Channel 0 + dprioout(rfreq_sel_RXPCS_IDX_0) <= init_rfreq_sel; + dprioout(rauto_speed_ena_RXPCS_IDX_0) <= init_rauto_speed_ena; + dprioout(rhip_ena_RXPCS_IDX_0) <= init_rhip_ena; + dprioout(rpma_done_gen_ena_RXPCS_IDX_0) <= init_rpma_done_gen_ena; + dprioout(rpma_done_count_16_RXPCS_IDX_0) <= init_rpma_done_count_16; + dprioout(rpma_done_count_17_RXPCS_IDX_0) <= init_rpma_done_count_17; + dprioout(reserved_0_TB16_RXPCS_IDX_3 DOWNTO reserved_0_TB16_RXPCS_IDX_0) <= init_reserved_0_TB16; + dprioout(rstart_threshold_RXPCS_IDX_2 DOWNTO rstart_threshold_RXPCS_IDX_0) <= init_rstart_threshold; + dprioout(rempty_threshold_RXPCS_IDX_2 DOWNTO rempty_threshold_RXPCS_IDX_0) <= init_rempty_threshold; + + -- PCS Per Channel RX Control Register 13 for Channel 0 + dprioout(rtest_bus_sel_RXPCS_IDX_3 DOWNTO rtest_bus_sel_RXPCS_IDX_0) <= init_rtest_bus_sel; + dprioout(rautoinsdis_RXPCS_IDX_0) <= init_rautoinsdis; + dprioout(rphfifopldenrx_RXPCS_IDX_0) <= init_rphfifopldenrx; + dprioout(rbytordplden_RXPCS_IDX_0) <= init_rbytordplden; + dprioout(rbyteorden_RXPCS_IDX_1 DOWNTO rbyteorden_RXPCS_IDX_0) <= init_rbyteorden; + dprioout(rbytord_2sym_en_RXPCS_IDX_0) <= init_rbytord_2sym_en; + dprioout(rinvalid_code_err_only_RXPCS_IDX_0) <= init_rinvalid_code_err_only; + dprioout(rcmpfifourst_RXPCS_IDX_0) <= init_rcmpfifourst; + dprioout(rphfifourstrx_RXPCS_IDX_0) <= init_rphfifourstrx; + dprioout(rdwidth_rx_RXPCS_IDX_0) <= init_rdwidth_rx; + dprioout(rrxfifo_lowlatency_en_RXPCS_IDX_0) <= init_rrxfifo_lowlatency_en; + dprioout(rrxfifo_dis_RXPCS_IDX_0) <= init_rrxfifo_dis; + + -- PCS Per Channel RX Control Register 14 for Channel 0 + dprioout(rbytordpat_0_RXPCS_IDX_0) <= init_rbytordpat_0; + dprioout(rbytordpat_1_RXPCS_IDX_0) <= init_rbytordpat_1; + dprioout(rbytordpat_2_RXPCS_IDX_0) <= init_rbytordpat_2; + dprioout(rbytordpat_3_RXPCS_IDX_0) <= init_rbytordpat_3; + dprioout(rbytordpat_4_RXPCS_IDX_0) <= init_rbytordpat_4; + dprioout(rbytordpat_5_RXPCS_IDX_0) <= init_rbytordpat_5; + dprioout(rbytordpat_6_RXPCS_IDX_0) <= init_rbytordpat_6; + dprioout(rbytordpat_7_RXPCS_IDX_0) <= init_rbytordpat_7; + dprioout(rbytordpat_8_RXPCS_IDX_0) <= init_rbytordpat_8; + dprioout(rbytordpat_9_RXPCS_IDX_0) <= init_rbytordpat_9; + dprioout(reserved_0_TB18_RXPCS_IDX_5 DOWNTO reserved_0_TB18_RXPCS_IDX_0) <= init_reserved_0_TB18; + + -- PCS Per Channel RX Control Register 15 for Channel 0 + dprioout(rbytordpad_RXPCS_IDX_9 DOWNTO rbytordpad_RXPCS_IDX_0) <= init_rbytordpad; + dprioout(reserved_0_TB19_RXPCS_IDX_5 DOWNTO reserved_0_TB19_RXPCS_IDX_0) <= init_reserved_0_TB19; + + -- PCS Per Channel RX Control Register 16 for Channel 0 + dprioout(rload_shreg_del_RXPCS_IDX_4 DOWNTO rload_shreg_del_RXPCS_IDX_0) <= init_rload_shreg_del; + dprioout(rphystatus_rst_toggle_RXPCS_IDX_0) <= init_rphystatus_rst_toggle; + dprioout(reidle_com_detect_RXPCS_IDX_1 DOWNTO reidle_com_detect_RXPCS_IDX_0) <= init_reidle_com_detect; + dprioout(rk285detect_RXPCS_IDX_0) <= init_rk285detect; + dprioout(reidleinferenable_RXPCS_IDX_0) <= init_reidleinferenable; + dprioout(rphystatus_delay_RXPCS_IDX_2 DOWNTO rphystatus_delay_RXPCS_IDX_0) <= init_rphystatus_delay; + dprioout(rind_error_reporting_RXPCS_IDX_0) <= init_rind_error_reporting; + dprioout(rrx_detect_bypass_RXPCS_IDX_0) <= init_rrx_detect_bypass; + dprioout(rrx_pipe_enable_RXPCS_IDX_0) <= init_rrx_pipe_enable; + + -- PCS Per Channel RX Control Register 17 for Channel 0 + dprioout(rpma_done_count_0_RXPCS_IDX_0) <= init_rpma_done_count_0; + dprioout(rpma_done_count_1_RXPCS_IDX_0) <= init_rpma_done_count_1; + dprioout(rpma_done_count_2_RXPCS_IDX_0) <= init_rpma_done_count_2; + dprioout(rpma_done_count_3_RXPCS_IDX_0) <= init_rpma_done_count_3; + dprioout(rpma_done_count_4_RXPCS_IDX_0) <= init_rpma_done_count_4; + dprioout(rpma_done_count_5_RXPCS_IDX_0) <= init_rpma_done_count_5; + dprioout(rpma_done_count_6_RXPCS_IDX_0) <= init_rpma_done_count_6; + dprioout(rpma_done_count_7_RXPCS_IDX_0) <= init_rpma_done_count_7; + dprioout(rpma_done_count_8_RXPCS_IDX_0) <= init_rpma_done_count_8; + dprioout(rpma_done_count_9_RXPCS_IDX_0) <= init_rpma_done_count_9; + dprioout(rpma_done_count_10_RXPCS_IDX_0) <= init_rpma_done_count_10; + dprioout(rpma_done_count_11_RXPCS_IDX_0) <= init_rpma_done_count_11; + dprioout(rpma_done_count_12_RXPCS_IDX_0) <= init_rpma_done_count_12; + dprioout(rpma_done_count_13_RXPCS_IDX_0) <= init_rpma_done_count_13; + dprioout(rpma_done_count_14_RXPCS_IDX_0) <= init_rpma_done_count_14; + dprioout(rpma_done_count_15_RXPCS_IDX_0) <= init_rpma_done_count_15; + + -- PCS Per Channel RX Control Register 18 for Channel 0 + dprioout(rbytordpat_10_RXPCS_IDX_0) <= init_rbytordpat_10; + dprioout(rbytordpat_11_RXPCS_IDX_0) <= init_rbytordpat_11; + dprioout(rbytordpat_12_RXPCS_IDX_0) <= init_rbytordpat_12; + dprioout(rbytordpat_13_RXPCS_IDX_0) <= init_rbytordpat_13; + dprioout(rbytordpat_14_RXPCS_IDX_0) <= init_rbytordpat_14; + dprioout(rbytordpat_15_RXPCS_IDX_0) <= init_rbytordpat_15; + dprioout(rbytordpat_16_RXPCS_IDX_0) <= init_rbytordpat_16; + dprioout(rbytordpat_17_RXPCS_IDX_0) <= init_rbytordpat_17; + dprioout(rbytordpat_18_RXPCS_IDX_0) <= init_rbytordpat_18; + dprioout(rbytordpat_19_RXPCS_IDX_0) <= init_rbytordpat_19; + dprioout(rbytord_6g_mask_en_RXPCS_IDX_0) <= init_rbytord_6g_mask_en; + dprioout(rbytord_s2gx_RXPCS_IDX_0) <= init_rbytord_s2gx; + dprioout(reserved_0_TB22_RXPCS_IDX_0) <= init_reserved_0_TB22; + dprioout(rcdr_ctrl_en_RXPCS_IDX_0) <= init_rcdr_ctrl_en; + dprioout(rrxpcsclkpwdn_RXPCS_IDX_0) <= init_rrxpcsclkpwdn; + dprioout(rerr_flags_sel_RXPCS_IDX_0) <= init_rerr_flags_sel; + + -- PCS Per Channel RX Control Register 19 for Channel 0 + dprioout(rwait_count_RXPCS_IDX_7 DOWNTO rwait_count_RXPCS_IDX_0) <= init_rwait_count; + dprioout(reserved_0_TB23_RXPCS_IDX_7 DOWNTO reserved_0_TB23_RXPCS_IDX_0) <= init_reserved_0_TB23; + + -- PCS Per Channel RX Control Register 20 for Channel 0 + dprioout(rfts_count_RXPCS_IDX_9 DOWNTO rfts_count_RXPCS_IDX_0) <= init_rfts_count; + dprioout(rwait_for_phfifo_cnt_RXPCS_IDX_5 DOWNTO rwait_for_phfifo_cnt_RXPCS_IDX_0) <= init_rwait_for_phfifo_cnt; + + -- PCS Per Channel RX Control Register 21 for Channel 0 + dprioout(rppm_meas_delay_RXPCS_IDX_0) <= init_rppm_meas_delay; + dprioout(rcid_len_rx_RXPCS_IDX_7 DOWNTO rcid_len_rx_RXPCS_IDX_0) <= init_rcid_len_rx; + dprioout(rcid_pattern_rx_RXPCS_IDX_0) <= init_rcid_pattern_rx; + dprioout(rpcs_wrapback_en_RXPCS_IDX_0) <= init_rpcs_wrapback_en; + dprioout(reserved_0_TB25_RXPCS_IDX_4 DOWNTO reserved_0_TB25_RXPCS_IDX_0) <= init_reserved_0_TB25; + + -- PCS Per Channel RX Control Register 22 for Channel 0 + dprioout(rauto_pc_en_cnt_RXPCS_IDX_4 DOWNTO rauto_pc_en_cnt_RXPCS_IDX_0) <= init_rauto_pc_en_cnt; + dprioout(reserved_1_TB26_RXPCS_IDX_0) <= init_reserved_1_TB26; + dprioout(rauto_deassert_pc_rst_cnt_RXPCS_IDX_3 DOWNTO rauto_deassert_pc_rst_cnt_RXPCS_IDX_0) <= init_rauto_deassert_pc_rst_cnt; + dprioout(reserved_0_TB26_RXPCS_IDX_0) <= init_reserved_0_TB26; + dprioout(rpipeline_bypass_rx_RXPCS_IDX_0) <= init_rpipeline_bypass_rx; + dprioout(rself_sw_en_rx_RXPCS_IDX_0) <= init_rself_sw_en_rx; + dprioout(rrxvalid_mask_RXPCS_IDX_0) <= init_rrxvalid_mask; + dprioout(rcid_en_RXPCS_IDX_0) <= init_rcid_en; + dprioout(rphfifo_regmode_rx_RXPCS_IDX_0) <= init_rphfifo_regmode_rx; + + -- PCS Per Channel RX Control Register 23 for Channel 0 + dprioout(rmask_count_RXPCS_IDX_9 DOWNTO rmask_count_RXPCS_IDX_0) <= init_rmask_count; + dprioout(rgen1_sigdet_ena_RXPCS_IDX_0) <= init_rgen1_sigdet_ena; + dprioout(riei_eios_priority_dis_RXPCS_IDX_0) <= init_riei_eios_priority_dis; + dprioout(reserved_0_TB27_RXPCS_IDX_3 DOWNTO reserved_0_TB27_RXPCS_IDX_0) <= init_reserved_0_TB27; + + -- --------------------------------------------------------------------------- + -- Set DPRIO CRAM + -- --------------------------------------------------------------------------- + dpriodisable_in <= '0' WHEN (dpriodisable = '0') ELSE '1'; + + -- Existing + cram_dskwclksel <= init_dskwclksel WHEN (dpriodisable_in /= '0') ELSE dprioin_dskwclksel; + cram_is_lane0 <= init_is_lane0 WHEN (dpriodisable_in /= '0') ELSE dprioin_is_lane0; + cram_rbist_sel <= init_rbist_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rbist_sel; + cram_rclkcmppos <= init_rclkcmppos WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmppos; + cram_rcxpat_chnl_en <= init_rcxpat_chnl_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rcxpat_chnl_en; + cram_rdskchrp <= init_rdskchrp WHEN (dpriodisable_in /= '0') ELSE dprioin_rdskchrp; + cram_rdskposdisp <= init_rdskposdisp WHEN (dpriodisable_in /= '0') ELSE dprioin_rdskposdisp; + cram_rendec_data_sel_rx <= init_rendec_data_sel_rx; -- disable reconfiguration for quad-level crams + cram_renpolinv_en <= init_renpolinv_en WHEN (dpriodisable_in /= '0') ELSE dprioin_renpolinv_en; + cram_rforce0_freqdet <= init_rforce0_freqdet WHEN (dpriodisable_in /= '0') ELSE dprioin_rforce0_freqdet; + cram_rforce1_freqdet <= init_rforce1_freqdet WHEN (dpriodisable_in /= '0') ELSE dprioin_rforce1_freqdet; + cram_rindv_rx <= init_rindv_rx; -- disable reconfiguration for quad-level crams + cram_rmaster_rx <= init_rmaster_rx; + cram_rmaster_up_rx <= init_rmaster_up_rx; + cram_rphfifourstenrx <= init_rphfifourstenrx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifourstenrx; + cram_rpma_doublewidth_rx <= init_rpma_doublewidth_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rpma_doublewidth_rx; -- enabled + cram_rpmadwidth_rx <= init_rpmadwidth_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rpmadwidth_rx; -- enabled + cram_rppm_gen1_2xcnt_en <= init_rppm_gen1_2xcnt_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rppm_gen1_2xcnt_en; + cram_rppm_post_eidle_del <= init_rppm_post_eidle_del WHEN (dpriodisable_in /= '0') ELSE dprioin_rppm_post_eidle_del; + cram_rppmsel <= init_rppmsel WHEN (dpriodisable_in /= '0') ELSE dprioin_rppmsel; + cram_rprbs_sel <= init_rprbs_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rprbs_sel; + cram_rrdwidth_rx <= init_rrdwidth_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rrdwidth_rx; + cram_rrx_fifo_dis <= init_rrx_fifo_dis WHEN (dpriodisable_in /= '0') ELSE dprioin_rrx_fifo_dis; + cram_rtx_elec_idle_delay <= init_rtx_elec_idle_delay WHEN (dpriodisable_in /= '0') ELSE dprioin_rtx_elec_idle_delay; + cram_rtx_pipe_enable <= init_rtx_pipe_enable WHEN (dpriodisable_in /= '0') ELSE dprioin_rtx_pipe_enable; + cram_scan_mode <= init_scan_mode WHEN (dpriodisable_in /= '0') ELSE dprioin_scan_mode; + cram_sel_gp_md <= init_sel_gp_md WHEN (dpriodisable_in /= '0') ELSE dprioin_sel_gp_md; + + -- PCS Per Channel RX Control Register 1 for Channel 0 + cram_rrxpcsbypass_en <= init_rrxpcsbypass_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rrxpcsbypass_en; + cram_rall_one_dect_only <= init_rall_one_dect_only WHEN (dpriodisable_in /= '0') ELSE dprioin_rall_one_dect_only; + cram_rbist_clr_rx <= init_rbist_clr_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rbist_clr_rx; + cram_rbisten_rx <= init_rbisten_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rbisten_rx; + cram_rprbs_clr_rslt_rx <= init_rprbs_clr_rslt_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rprbs_clr_rslt_rx; + cram_rprbsen_rx <= init_rprbsen_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rprbsen_rx; + cram_rrx_rd_clk_sel <= init_rrx_rd_clk_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rrx_rd_clk_sel; + cram_rclk_2_sel <= init_rclk_2_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rclk_2_sel; + cram_rclk_1_sel <= init_rclk_1_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rclk_1_sel; + cram_rrcvd_clk_sel <= init_rrcvd_clk_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rrcvd_clk_sel; + cram_rfreerun_rx <= init_rfreerun_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rfreerun_rx; + cram_rrxurstpcs <= init_rrxurstpcs WHEN (dpriodisable_in /= '0') ELSE dprioin_rrxurstpcs; + cram_reserved_0_TB5 <= init_reserved_0_TB5 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB5; + + -- PCS Per Channel RX Control Register 2 for Channel 0 + cram_rcomp_pat_32 <= init_rcomp_pat_32 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_32; + cram_rcomp_pat_33 <= init_rcomp_pat_33 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_33; + cram_rcomp_pat_34 <= init_rcomp_pat_34 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_34; + cram_rcomp_pat_35 <= init_rcomp_pat_35 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_35; + cram_rcomp_pat_36 <= init_rcomp_pat_36 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_36; + cram_rcomp_pat_37 <= init_rcomp_pat_37 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_37; + cram_rcomp_pat_38 <= init_rcomp_pat_38 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_38; + cram_rcomp_pat_39 <= init_rcomp_pat_39 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_39; + cram_rcomp_size <= init_rcomp_size WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_size; + cram_rcomp_pat_porn <= init_rcomp_pat_porn WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_porn; + cram_rdis_rx_disp <= init_rdis_rx_disp WHEN (dpriodisable_in /= '0') ELSE dprioin_rdis_rx_disp; + cram_rencdt_rising <= init_rencdt_rising WHEN (dpriodisable_in /= '0') ELSE dprioin_rencdt_rising; + cram_resync_badcg_en <= init_resync_badcg_en WHEN (dpriodisable_in /= '0') ELSE dprioin_resync_badcg_en; + + -- PCS Per Channel RX Control Register 3 for Channel 0 + cram_rcomp_pat_16 <= init_rcomp_pat_16 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_16; + cram_rcomp_pat_17 <= init_rcomp_pat_17 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_17; + cram_rcomp_pat_18 <= init_rcomp_pat_18 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_18; + cram_rcomp_pat_19 <= init_rcomp_pat_19 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_19; + cram_rcomp_pat_20 <= init_rcomp_pat_20 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_20; + cram_rcomp_pat_21 <= init_rcomp_pat_21 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_21; + cram_rcomp_pat_22 <= init_rcomp_pat_22 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_22; + cram_rcomp_pat_23 <= init_rcomp_pat_23 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_23; + cram_rcomp_pat_24 <= init_rcomp_pat_24 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_24; + cram_rcomp_pat_25 <= init_rcomp_pat_25 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_25; + cram_rcomp_pat_26 <= init_rcomp_pat_26 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_26; + cram_rcomp_pat_27 <= init_rcomp_pat_27 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_27; + cram_rcomp_pat_28 <= init_rcomp_pat_28 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_28; + cram_rcomp_pat_29 <= init_rcomp_pat_29 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_29; + cram_rcomp_pat_30 <= init_rcomp_pat_30 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_30; + cram_rcomp_pat_31 <= init_rcomp_pat_31 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_31; + + -- PCS Per Channel RX Control Register 4 for Channel 0 + cram_rcomp_pat_0 <= init_rcomp_pat_0 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_0; + cram_rcomp_pat_1 <= init_rcomp_pat_1 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_1; + cram_rcomp_pat_2 <= init_rcomp_pat_2 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_2; + cram_rcomp_pat_3 <= init_rcomp_pat_3 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_3; + cram_rcomp_pat_4 <= init_rcomp_pat_4 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_4; + cram_rcomp_pat_5 <= init_rcomp_pat_5 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_5; + cram_rcomp_pat_6 <= init_rcomp_pat_6 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_6; + cram_rcomp_pat_7 <= init_rcomp_pat_7 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_7; + cram_rcomp_pat_8 <= init_rcomp_pat_8 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_8; + cram_rcomp_pat_9 <= init_rcomp_pat_9 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_9; + cram_rcomp_pat_10 <= init_rcomp_pat_10 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_10; + cram_rcomp_pat_11 <= init_rcomp_pat_11 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_11; + cram_rcomp_pat_12 <= init_rcomp_pat_12 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_12; + cram_rcomp_pat_13 <= init_rcomp_pat_13 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_13; + cram_rcomp_pat_14 <= init_rcomp_pat_14 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_14; + cram_rcomp_pat_15 <= init_rcomp_pat_15 WHEN (dpriodisable_in /= '0') ELSE dprioin_rcomp_pat_15; + + -- PCS Per Channel RX Control Register 5 for Channel 0 + cram_rbitloc_rev_en <= init_rbitloc_rev_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rbitloc_rev_en; + cram_rbysync_polinv_en <= init_rbysync_polinv_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rbysync_polinv_en; + cram_rwa_6g_en <= init_rwa_6g_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rwa_6g_en; + cram_rosnumber <= init_rosnumber WHEN (dpriodisable_in /= '0') ELSE dprioin_rosnumber; + cram_rosbased <= init_rosbased WHEN (dpriodisable_in /= '0') ELSE dprioin_rosbased; + cram_rkchar <= init_rkchar WHEN (dpriodisable_in /= '0') ELSE dprioin_rkchar; + cram_renumber <= init_renumber WHEN (dpriodisable_in /= '0') ELSE dprioin_renumber; + cram_rib_inv_cd <= init_rib_inv_cd WHEN (dpriodisable_in /= '0') ELSE dprioin_rib_inv_cd; + cram_rsync_sm_dis <= init_rsync_sm_dis WHEN (dpriodisable_in /= '0') ELSE dprioin_rsync_sm_dis; + + -- PCS Per Channel RX Control Register 6 for Channel 0 + cram_rknumber <= init_rknumber WHEN (dpriodisable_in /= '0') ELSE dprioin_rknumber; + cram_rgnumber <= init_rgnumber WHEN (dpriodisable_in /= '0') ELSE dprioin_rgnumber; + + -- PCS Per Channel RX Control Register 7 for Channel 0 + cram_renpolinv_rx <= init_renpolinv_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_renpolinv_rx; + cram_rcascaded_8b10b_en_rx <= init_rcascaded_8b10b_en_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rcascaded_8b10b_en_rx; + cram_r8b10b_dec_ibm_en <= init_r8b10b_dec_ibm_en WHEN (dpriodisable_in /= '0') ELSE dprioin_r8b10b_dec_ibm_en; + cram_rendec_rx <= init_rendec_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rendec_rx; + cram_rautobtalg_dis <= init_rautobtalg_dis WHEN (dpriodisable_in /= '0') ELSE dprioin_rautobtalg_dis; + cram_rrlv_en <= init_rrlv_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rrlv_en; + cram_rlp20ben <= init_rlp20ben WHEN (dpriodisable_in /= '0') ELSE dprioin_rlp20ben; + cram_rforce_sig_det_pcs <= init_rforce_sig_det_pcs WHEN (dpriodisable_in /= '0') ELSE dprioin_rforce_sig_det_pcs; + cram_rbyte_rev_en <= init_rbyte_rev_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rbyte_rev_en; + cram_rrundisp <= init_rrundisp WHEN (dpriodisable_in /= '0') ELSE dprioin_rrundisp; + + -- PCS Per Channel RX Control Register 8 for Channel 0 + cram_rclkcmpsq1p_0 <= init_rclkcmpsq1p_0 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_0; + cram_rclkcmpsq1p_1 <= init_rclkcmpsq1p_1 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_1; + cram_rclkcmpsq1p_2 <= init_rclkcmpsq1p_2 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_2; + cram_rclkcmpsq1p_3 <= init_rclkcmpsq1p_3 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_3; + cram_rclkcmpsq1p_4 <= init_rclkcmpsq1p_4 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_4; + cram_rclkcmpsq1p_5 <= init_rclkcmpsq1p_5 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_5; + cram_rclkcmpsq1p_6 <= init_rclkcmpsq1p_6 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_6; + cram_rclkcmpsq1p_7 <= init_rclkcmpsq1p_7 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_7; + cram_rclkcmpsq1p_8 <= init_rclkcmpsq1p_8 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_8; + cram_rclkcmpsq1p_9 <= init_rclkcmpsq1p_9 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_9; + cram_rclkcmpsqmd <= init_rclkcmpsqmd WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsqmd; + cram_rclkcmpinsertpad <= init_rclkcmpinsertpad WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpinsertpad; + cram_rtruebac2bac <= init_rtruebac2bac WHEN (dpriodisable_in /= '0') ELSE dprioin_rtruebac2bac; + cram_rskpsetbased <= init_rskpsetbased WHEN (dpriodisable_in /= '0') ELSE dprioin_rskpsetbased; + cram_rgenericfifo <= init_rgenericfifo WHEN (dpriodisable_in /= '0') ELSE dprioin_rgenericfifo; + cram_rmatchen <= init_rmatchen WHEN (dpriodisable_in /= '0') ELSE dprioin_rmatchen; + + -- PCS Per Channel RX Control Register 9 for Channel 0 + cram_rclkcmpsq1p_10 <= init_rclkcmpsq1p_10 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_10; + cram_rclkcmpsq1p_11 <= init_rclkcmpsq1p_11 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_11; + cram_rclkcmpsq1p_12 <= init_rclkcmpsq1p_12 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_12; + cram_rclkcmpsq1p_13 <= init_rclkcmpsq1p_13 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_13; + cram_rclkcmpsq1p_14 <= init_rclkcmpsq1p_14 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_14; + cram_rclkcmpsq1p_15 <= init_rclkcmpsq1p_15 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_15; + cram_rclkcmpsq1p_16 <= init_rclkcmpsq1p_16 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_16; + cram_rclkcmpsq1p_17 <= init_rclkcmpsq1p_17 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_17; + cram_rclkcmpsq1p_18 <= init_rclkcmpsq1p_18 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_18; + cram_rclkcmpsq1p_19 <= init_rclkcmpsq1p_19 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1p_19; + cram_reserved_0_TB13 <= init_reserved_0_TB13 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB13; + cram_rclkcmpsq1n_15 <= init_rclkcmpsq1n_15 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_15; + cram_rclkcmpsq1n_16 <= init_rclkcmpsq1n_16 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_16; + cram_rclkcmpsq1n_17 <= init_rclkcmpsq1n_17 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_17; + cram_rclkcmpsq1n_18 <= init_rclkcmpsq1n_18 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_18; + cram_rclkcmpsq1n_19 <= init_rclkcmpsq1n_19 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_19; + + -- PCS Per Channel RX Control Register 10 for Channel 0 + cram_rclkcmpsq1n_0 <= init_rclkcmpsq1n_0 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_0; + cram_rclkcmpsq1n_1 <= init_rclkcmpsq1n_1 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_1; + cram_rclkcmpsq1n_2 <= init_rclkcmpsq1n_2 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_2; + cram_rclkcmpsq1n_3 <= init_rclkcmpsq1n_3 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_3; + cram_rclkcmpsq1n_4 <= init_rclkcmpsq1n_4 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_4; + cram_rclkcmpsq1n_5 <= init_rclkcmpsq1n_5 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_5; + cram_rclkcmpsq1n_6 <= init_rclkcmpsq1n_6 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_6; + cram_rclkcmpsq1n_7 <= init_rclkcmpsq1n_7 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_7; + cram_rclkcmpsq1n_8 <= init_rclkcmpsq1n_8 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_8; + cram_rclkcmpsq1n_9 <= init_rclkcmpsq1n_9 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_9; + cram_reserved_0_TB14 <= init_reserved_0_TB14 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB14; + cram_rclkcmpsq1n_10 <= init_rclkcmpsq1n_10 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_10; + cram_rclkcmpsq1n_11 <= init_rclkcmpsq1n_11 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_11; + cram_rclkcmpsq1n_12 <= init_rclkcmpsq1n_12 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_12; + cram_rclkcmpsq1n_13 <= init_rclkcmpsq1n_13 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_13; + cram_rclkcmpsq1n_14 <= init_rclkcmpsq1n_14 WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmpsq1n_14; + + -- PCS Per Channel RX Control Register 11 for Channel 0 + cram_rfull_threshold <= init_rfull_threshold WHEN (dpriodisable_in /= '0') ELSE dprioin_rfull_threshold; + cram_rdel_threshold <= init_rdel_threshold WHEN (dpriodisable_in /= '0') ELSE dprioin_rdel_threshold; + cram_rins_threshold <= init_rins_threshold WHEN (dpriodisable_in /= '0') ELSE dprioin_rins_threshold; + cram_rclkcmp_pipe_en <= init_rclkcmp_pipe_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rclkcmp_pipe_en; + + -- PCS Per Channel RX Control Register 12 for Channel 0 + cram_rfreq_sel <= init_rfreq_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rfreq_sel; + cram_rauto_speed_ena <= init_rauto_speed_ena WHEN (dpriodisable_in /= '0') ELSE dprioin_rauto_speed_ena; + cram_rhip_ena <= init_rhip_ena WHEN (dpriodisable_in /= '0') ELSE dprioin_rhip_ena; + cram_rpma_done_gen_ena <= init_rpma_done_gen_ena WHEN (dpriodisable_in /= '0') ELSE dprioin_rpma_done_gen_ena; + cram_rpma_done_count_16 <= init_rpma_done_count_16 ; + cram_rpma_done_count_17 <= init_rpma_done_count_17 ; + cram_reserved_0_TB16 <= init_reserved_0_TB16 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB16; + cram_rstart_threshold <= init_rstart_threshold WHEN (dpriodisable_in /= '0') ELSE dprioin_rstart_threshold; + cram_rempty_threshold <= init_rempty_threshold WHEN (dpriodisable_in /= '0') ELSE dprioin_rempty_threshold; + + -- PCS Per Channel RX Control Register 13 for Channel 0 + cram_rtest_bus_sel <= init_rtest_bus_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rtest_bus_sel; + cram_rautoinsdis <= init_rautoinsdis WHEN (dpriodisable_in /= '0') ELSE dprioin_rautoinsdis; + cram_rphfifopldenrx <= init_rphfifopldenrx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifopldenrx; + cram_rbytordplden <= init_rbytordplden WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordplden; + cram_rbyteorden <= init_rbyteorden WHEN (dpriodisable_in /= '0') ELSE dprioin_rbyteorden; + cram_rbytord_2sym_en <= init_rbytord_2sym_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytord_2sym_en; + cram_rinvalid_code_err_only <= init_rinvalid_code_err_only WHEN (dpriodisable_in /= '0') ELSE dprioin_rinvalid_code_err_only; + cram_rcmpfifourst <= init_rcmpfifourst WHEN (dpriodisable_in /= '0') ELSE dprioin_rcmpfifourst; + cram_rphfifourstrx <= init_rphfifourstrx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifourstrx; + cram_rdwidth_rx <= init_rdwidth_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rdwidth_rx; + cram_rrxfifo_lowlatency_en <= init_rrxfifo_lowlatency_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rrxfifo_lowlatency_en; + cram_rrxfifo_dis <= init_rrxfifo_dis WHEN (dpriodisable_in /= '0') ELSE dprioin_rrxfifo_dis; + + -- PCS Per Channel RX Control Register 14 for Channel 0 + cram_rbytordpat_0 <= init_rbytordpat_0 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_0; + cram_rbytordpat_1 <= init_rbytordpat_1 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_1; + cram_rbytordpat_2 <= init_rbytordpat_2 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_2; + cram_rbytordpat_3 <= init_rbytordpat_3 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_3; + cram_rbytordpat_4 <= init_rbytordpat_4 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_4; + cram_rbytordpat_5 <= init_rbytordpat_5 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_5; + cram_rbytordpat_6 <= init_rbytordpat_6 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_6; + cram_rbytordpat_7 <= init_rbytordpat_7 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_7; + cram_rbytordpat_8 <= init_rbytordpat_8 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_8; + cram_rbytordpat_9 <= init_rbytordpat_9 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_9; + cram_reserved_0_TB18 <= init_reserved_0_TB18 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB18; + + -- PCS Per Channel RX Control Register 15 for Channel 0 + cram_rbytordpad <= init_rbytordpad WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpad; + cram_reserved_0_TB19 <= init_reserved_0_TB19 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB19; + + -- PCS Per Channel RX Control Register 16 for Channel 0 + cram_rload_shreg_del <= init_rload_shreg_del WHEN (dpriodisable_in /= '0') ELSE dprioin_rload_shreg_del; + cram_rphystatus_rst_toggle <= init_rphystatus_rst_toggle WHEN (dpriodisable_in /= '0') ELSE dprioin_rphystatus_rst_toggle; + cram_reidle_com_detect <= init_reidle_com_detect WHEN (dpriodisable_in /= '0') ELSE dprioin_reidle_com_detect; + cram_rk285detect <= init_rk285detect WHEN (dpriodisable_in /= '0') ELSE dprioin_rk285detect; + cram_reidleinferenable <= init_reidleinferenable WHEN (dpriodisable_in /= '0') ELSE dprioin_reidleinferenable; + cram_rphystatus_delay <= init_rphystatus_delay WHEN (dpriodisable_in /= '0') ELSE dprioin_rphystatus_delay; + cram_rind_error_reporting <= init_rind_error_reporting WHEN (dpriodisable_in /= '0') ELSE dprioin_rind_error_reporting; + cram_rrx_detect_bypass <= init_rrx_detect_bypass WHEN (dpriodisable_in /= '0') ELSE dprioin_rrx_detect_bypass; + cram_rrx_pipe_enable <= init_rrx_pipe_enable WHEN (dpriodisable_in /= '0') ELSE dprioin_rrx_pipe_enable; + + -- PCS Per Channel RX Control Register 17 for Channel 0 + cram_rpma_done_count_0 <= init_rpma_done_count_0 ; + cram_rpma_done_count_1 <= init_rpma_done_count_1 ; + cram_rpma_done_count_2 <= init_rpma_done_count_2 ; + cram_rpma_done_count_3 <= init_rpma_done_count_3 ; + cram_rpma_done_count_4 <= init_rpma_done_count_4 ; + cram_rpma_done_count_5 <= init_rpma_done_count_5 ; + cram_rpma_done_count_6 <= init_rpma_done_count_6 ; + cram_rpma_done_count_7 <= init_rpma_done_count_7 ; + cram_rpma_done_count_8 <= init_rpma_done_count_8 ; + cram_rpma_done_count_9 <= init_rpma_done_count_9 ; + cram_rpma_done_count_10 <= init_rpma_done_count_10 ; + cram_rpma_done_count_11 <= init_rpma_done_count_11 ; + cram_rpma_done_count_12 <= init_rpma_done_count_12 ; + cram_rpma_done_count_13 <= init_rpma_done_count_13 ; + cram_rpma_done_count_14 <= init_rpma_done_count_14 ; + cram_rpma_done_count_15 <= init_rpma_done_count_15 ; + + -- PCS Per Channel RX Control Register 18 for Channel 0 + cram_rbytordpat_10 <= init_rbytordpat_10 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_10; + cram_rbytordpat_11 <= init_rbytordpat_11 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_11; + cram_rbytordpat_12 <= init_rbytordpat_12 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_12; + cram_rbytordpat_13 <= init_rbytordpat_13 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_13; + cram_rbytordpat_14 <= init_rbytordpat_14 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_14; + cram_rbytordpat_15 <= init_rbytordpat_15 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_15; + cram_rbytordpat_16 <= init_rbytordpat_16 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_16; + cram_rbytordpat_17 <= init_rbytordpat_17 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_17; + cram_rbytordpat_18 <= init_rbytordpat_18 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_18; + cram_rbytordpat_19 <= init_rbytordpat_19 WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytordpat_19; + cram_rbytord_6g_mask_en <= init_rbytord_6g_mask_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytord_6g_mask_en; + cram_rbytord_s2gx <= init_rbytord_s2gx WHEN (dpriodisable_in /= '0') ELSE dprioin_rbytord_s2gx; + cram_reserved_0_TB22 <= init_reserved_0_TB22 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB22; + cram_rcdr_ctrl_en <= init_rcdr_ctrl_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rcdr_ctrl_en; + cram_rrxpcsclkpwdn <= init_rrxpcsclkpwdn WHEN (dpriodisable_in /= '0') ELSE dprioin_rrxpcsclkpwdn; + cram_rerr_flags_sel <= init_rerr_flags_sel WHEN (dpriodisable_in /= '0') ELSE dprioin_rerr_flags_sel; + + -- PCS Per Channel RX Control Register 19 for Channel 0 + cram_rwait_count <= init_rwait_count WHEN (dpriodisable_in /= '0') ELSE dprioin_rwait_count; + cram_reserved_0_TB23 <= init_reserved_0_TB23 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB23; + + -- PCS Per Channel RX Control Register 20 for Channel 0 + cram_rfts_count <= init_rfts_count WHEN (dpriodisable_in /= '0') ELSE dprioin_rfts_count; + cram_rwait_for_phfifo_cnt <= init_rwait_for_phfifo_cnt WHEN (dpriodisable_in /= '0') ELSE dprioin_rwait_for_phfifo_cnt; + + -- PCS Per Channel RX Control Register 21 for Channel 0 + cram_rppm_meas_delay <= init_rppm_meas_delay WHEN (dpriodisable_in /= '0') ELSE dprioin_rppm_meas_delay; + cram_rcid_len_rx <= init_rcid_len_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rcid_len_rx; + cram_rcid_pattern_rx <= init_rcid_pattern_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rcid_pattern_rx; + cram_rpcs_wrapback_en <= init_rpcs_wrapback_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rpcs_wrapback_en; + cram_reserved_0_TB25 <= init_reserved_0_TB25 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB25; + + -- PCS Per Channel RX Control Register 22 for Channel 0 + cram_rauto_pc_en_cnt <= init_rauto_pc_en_cnt WHEN (dpriodisable_in /= '0') ELSE dprioin_rauto_pc_en_cnt; + cram_reserved_1_TB26 <= init_reserved_1_TB26 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_1_TB26; + cram_rauto_deassert_pc_rst_cnt <= init_rauto_deassert_pc_rst_cnt WHEN (dpriodisable_in /= '0') ELSE dprioin_rauto_deassert_pc_rst_cnt; + cram_reserved_0_TB26 <= init_reserved_0_TB26 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB26; + cram_rpipeline_bypass_rx <= init_rpipeline_bypass_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rpipeline_bypass_rx; + cram_rself_sw_en_rx <= init_rself_sw_en_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rself_sw_en_rx; + cram_rrxvalid_mask <= init_rrxvalid_mask WHEN (dpriodisable_in /= '0') ELSE dprioin_rrxvalid_mask; + cram_rcid_en <= init_rcid_en WHEN (dpriodisable_in /= '0') ELSE dprioin_rcid_en; + cram_rphfifo_regmode_rx <= init_rphfifo_regmode_rx WHEN (dpriodisable_in /= '0') ELSE dprioin_rphfifo_regmode_rx; + + -- PCS Per Channel RX Control Register 23 for Channel 0 + cram_rmask_count <= init_rmask_count WHEN (dpriodisable_in /= '0') ELSE dprioin_rmask_count; + cram_rgen1_sigdet_ena <= init_rgen1_sigdet_ena WHEN (dpriodisable_in /= '0') ELSE dprioin_rgen1_sigdet_ena; + cram_riei_eios_priority_dis <= init_riei_eios_priority_dis WHEN (dpriodisable_in /= '0') ELSE dprioin_riei_eios_priority_dis; + cram_reserved_0_TB27 <= init_reserved_0_TB27 WHEN (dpriodisable_in /= '0') ELSE dprioin_reserved_0_TB27; + + --/////////////////////////////////////////////////////////////////////////// + -- Connect top level output ----------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + +-- a1a2sizeout <= a1a2sizeout_reg; + a1detect <= a1detect_reg_sr; + a2detect <= a2detect_reg_sr; +-- ctrldetect <= ctrldetect_reg; +-- dataout <= dataout_reg; +-- dataoutfull <= pi_out_rxd_ch; +-- disperr <= disperr_reg; +-- errdetect <= errdetect_reg; + k1detect <= k1detect_reg_sr; + k2detect <= k2detect_reg_sr; +-- patterndetect <= patterndetect_reg; +-- rmfifodatadeleted <= rmfifodatadeleted_reg; +-- rmfifodatainserted <= rmfifodatainserted_reg; +-- runningdisp <= runningdisp_reg; +-- syncstatus <= syncstatus_reg; + + -- a1a2sizeout; - used in SONET mode + PROCESS (rd_out_rxd(8), rd_out_rxd(24), rd_out_rxd(40), rd_out_rxd(56)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + a1a2sizeout_reg(i) <= rd_out_rxd(8 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + a1a2sizeout_reg(i) <= rd_out_rxd(8 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- a1detect; [1:0] - Async from Word align, not going BYTE SERDES + PROCESS (rd_out_a1a2_k1k2_flag(0), rd_out_a1a2_k1k2_flag(2)) +VARIABLE txt : LINE; + BEGIN + FOR i IN 0 TO 1 LOOP + + -- a2detect; [0] = detecting A2 on datain[7:0]; [1] = on datain[15:8] + a1detect_reg(i) <= rd_out_a1a2_k1k2_flag(2 * i); + END LOOP; + END PROCESS; + + PROCESS (rd_out_a1a2_k1k2_flag(1), rd_out_a1a2_k1k2_flag(3)) +VARIABLE txt : LINE; + BEGIN + FOR i IN 0 TO 1 LOOP + + -- adetectdeskew; + a2detect_reg(i) <= rd_out_a1a2_k1k2_flag(1 + 2 * i); + END LOOP; + END PROCESS; + + adetectdeskew <= rd_out_align_det_sync; + + -- alignstatussyncout + alignstatussyncout <= rd_out_align_status_sync; + + -- bistdone; + bistdone <= rd_out_bistdone; + + -- bisterr; + bisterr <= rd_out_bisterr; + + -- byteorderalignstatus; +-- byteorderalignstatus <= rd_out_byteord_flag; + + -- clkout; + clkout <= rd_out_rx_clk; + + -- ctrldetect; - 8b10b used + PROCESS (rd_out_rxd(8), rd_out_rxd(24), rd_out_rxd(40), rd_out_rxd(56)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + ctrldetect_reg(i) <= rd_out_rxd(8 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + ctrldetect_reg(i) <= rd_out_rxd(8 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- dataout; - 40 => [7:0]/[9:0], [23:16]/[25:16], [39:32]/[41:32], [55:48]/[57:48] + PROCESS + VARIABLE BASIC_WIDTH : integer; + VARIABLE NUM_OF_BASIC : integer; + VARIABLE i : integer := 0; + VARIABLE j : integer := 0; + BEGIN + IF (channel_width mod 10 = 0) THEN + BASIC_WIDTH := 10; + ELSE + BASIC_WIDTH := 8; + END IF; + + NUM_OF_BASIC := channel_width/BASIC_WIDTH; + + WAIT UNTIL rd_out_rxd'EVENT; + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + WHILE ((i < NUM_OF_BASIC) AND (i < 2)) LOOP + j := 0; + WHILE (j < BASIC_WIDTH) LOOP + dataout_reg(i * BASIC_WIDTH + j) <= rd_out_rxd(i * 32 + j); + j := j + 1; + END LOOP; + i := i + 1; + END LOOP; + ELSE + i := 0; + WHILE (i < NUM_OF_BASIC) LOOP + j := 0; + WHILE (j < BASIC_WIDTH) LOOP + dataout_reg(i * BASIC_WIDTH + j) <= rd_out_rxd(i * 16 + j); + j := j + 1; + END LOOP; + i := i + 1; + END LOOP; + END IF; + END PROCESS; + + -- disperr; + PROCESS (rd_out_rxd(11), rd_out_rxd(27), rd_out_rxd(43), rd_out_rxd(59)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + disperr_reg(i) <= rd_out_rxd(11 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + disperr_reg(i) <= rd_out_rxd(11 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- dprioout + --dprioout <= ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & wire_dprioout); + + -- errdetect; + PROCESS (rd_out_rxd(9), rd_out_rxd(25), rd_out_rxd(41), rd_out_rxd(57)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + errdetect_reg(i) <= rd_out_rxd(9 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + errdetect_reg(i) <= rd_out_rxd(9 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- fifordout; + fifordout <= rd_out_fifo_rd_out_comp; + + -- k1detect; [1:0] - Async from Word align, not going BYTE SERDES + PROCESS (rd_out_a1a2_k1k2_flag(0), rd_out_a1a2_k1k2_flag(2)) +VARIABLE txt : LINE; + BEGIN + FOR i IN 0 TO 1 LOOP + + -- k2detect; [0] = detecting K2 on datain[9:0]; [1] = datain[19:20] + k1detect_reg(i) <= rd_out_a1a2_k1k2_flag(2 * i); + END LOOP; + END PROCESS; + + PROCESS (rd_out_a1a2_k1k2_flag(1), rd_out_a1a2_k1k2_flag(3)) +VARIABLE txt : LINE; + BEGIN + FOR i IN 0 TO 1 LOOP + + -- patterndetect; + k2detect_reg(i) <= rd_out_a1a2_k1k2_flag(1 + 2 * i); + END LOOP; + END PROCESS; + + PROCESS (rd_out_rxd(12), rd_out_rxd(28), rd_out_rxd(44), rd_out_rxd(60)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + patterndetect_reg(i) <= rd_out_rxd(12 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + patterndetect_reg(i) <= rd_out_rxd(12 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + -- phfifooverflow; +-- phfifooverflow <= rd_out_full_rx; + + -- phfifounderflow; +-- phfifounderflow <= rd_out_empty_rx; + + -- pipebufferstat; 4 - expect wys - may remove according ICD +-- pipebufferstat(1 DOWNTO 0) <= rd_out_rxd(14 DOWNTO 13); +-- pipebufferstat(3 DOWNTO 2) <= rd_out_rxd(46 DOWNTO 45); + + -- pipedatavalid; - UPDATE +-- pipedatavalid <= hs_out_rxvalid; -- rd_out_rxvalid; pi_out_rxvalid; + + -- pipeelecidle; + pipeelecidle <= hs_out_rxelecidle; -- pi_out_rxelecidle; + + -- pipephydonestatus; - UPDATE +-- pipephydonestatus <= hs_out_phystatus; -- rd_out_phystatus; pi_out_phystatus; + + -- pipestatus; 3 - UPDATE +-- pipestatus <= hs_out_rxstatus_ch; -- rd_out_rxstatus; pi_out_rxstatus + + -- pipestatetransdoneout + pipestatetransdoneout <= pi_out_sim_state_transition_done; + + -- rdalign; + rdalign <= rd_out_rd_align; + + -- revparallelfdbkdata; + revparallelfdbkdata <= rd_out_rev_loop_data; + + -- rlv; + rlv <= rd_out_rlv_lt; + + -- rmfifoalmostempty; + rmfifoalmostempty <= rd_out_almost_mt_rmf; + + -- rmfifoalmostfull; + rmfifoalmostfull <= rd_out_almost_fl_rmf; + + -- rmfifodatadeleted - 4; + PROCESS (rd_out_rxd(13), rd_out_rxd(29), rd_out_rxd(45), rd_out_rxd(61)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + rmfifodatadeleted_reg(i) <= rd_out_rxd(13 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + rmfifodatadeleted_reg(i) <= rd_out_rxd(13 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- rmfifodatainserted - 4; + PROCESS (rd_out_rxd(14), rd_out_rxd(30), rd_out_rxd(46), rd_out_rxd(62)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + rmfifodatainserted_reg(i) <= rd_out_rxd(14 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + rmfifodatainserted_reg(i) <= rd_out_rxd(14 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- rmfifoempty; + rmfifoempty <= rd_out_empty_rmf; + + -- rmfifofull; + rmfifofull <= rd_out_full_rmf; + + -- runningdisp - 4; + PROCESS (rd_out_rxd(15), rd_out_rxd(31), rd_out_rxd(47), rd_out_rxd(63)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + runningdisp_reg(i) <= rd_out_rxd(15 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + runningdisp_reg(i) <= rd_out_rxd(15 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- signaldetect; + signaldetect <= rd_out_signal_detect_out; + + -- syncstatus; + PROCESS (rd_out_rxd(10), rd_out_rxd(26), rd_out_rxd(42), rd_out_rxd(58)) +VARIABLE txt : LINE; + variable i : integer; + BEGIN + IF (cram_rpma_doublewidth_rx = '0' AND cram_rdwidth_rx = '1') THEN + i := 0; + while ((i < 4) AND (i < 2) ) LOOP + syncstatus_reg(i) <= rd_out_rxd(10 + 32 * i); + i := i + 1; + END LOOP; + ELSE + FOR i IN 0 TO 3 LOOP + syncstatus_reg(i) <= rd_out_rxd(10 + 16 * i); + END LOOP; + END IF; + END PROCESS; + + + -- syncstatusdeskew; + syncstatusdeskew <= rd_out_sync_status; + + -- xgmctrldet; + xgmctrldet <= rd_out_dec_ctl; + + -- xgmdataout; - 8 + xgmdataout <= rd_out_dec_data; + + -- xgmdatavalid; + xgmdatavalid <= rd_out_dec_data_valid; + + -- xgmrunningdisp; + xgmrunningdisp <= rd_out_running_disp(0); + + --/////////////////////////////////////////////////////////////////////////// + -- simulation only - pass through from ch0 to CMU -------------------------// + --/////////////////////////////////////////////////////////////////////////// + coreclkout <= coreclk_in; + phfiforesetout <= phfiforeset; + phfifowrdisableout <= phfifowrdisable_in; + + autospdrateswitchout <= rd_out_pcie_switch; -- feed to rx_cdr and tx_clk_divider? + autospdspdchgout <= rd_out_speed_change_out_pipe; -- speed_chang_out_pipe + bitslipboundaryselectout <= rd_out_wa_boundary; -- wa_boundary + cdrctrlearlyeios <= rd_out_early_eios; -- Asserted when K_I or K + cdrctrllocktorefclkout <= rd_out_ltr; -- Force CDR(RX PLL) to LTR. + hipdataout <= hs_out_hip_rxd_ch; -- hip_rxd_ch(8:0) + + -- corresponding soft signal: replacing prefix hip by pipe + hipdatavalid <= hs_out_hip_rxvalid; -- hip_rxvalid + hipelecidle <= hs_out_hip_rxelecidle; -- hip_rxelecidle + hipphydonestatus <= hs_out_hip_phystatus; -- hip_phystatus + hipstatus <= hs_out_hip_rxstatus_ch; -- hip_rxstatus_ch(2:0) + + iqpphfifobyteselout <= rd_out_rx_we_out_pipe; -- rx_we_out_pipe + iqpphfifoptrsresetout <= rd_out_reset_pc_ptrs_out_pipe; -- reset_pc_pters_out_pipe + iqpphfifordenableout <= rd_out_rd_enable_out_pipe; -- rd_enable_pipe_out + iqpphfifowrclkout <= rd_out_rx_div2_sync_out_pipe; -- rx_div2_sync_out_pipe + iqpphfifowrenableout <= rd_out_wr_enable_out_pipe; -- wr_enable_out_pipe + + phfifobyteserdisableout <= rd_out_dis_pc_byte; --From Auto Speed Neg to TX + phfifoptrsresetout <= rd_out_reset_pc_ptrs; --From Auto Speed Neg to TX + + rateswitchout <= hs_out_pcs_rate; -- rx0 feeds to CMU + + --/////////////////////////////////////////////////////////////////////////// + -- rx sub-block instantiation: pcs_reset ----------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + pr_in_hard_reset <= '1' WHEN (quadreset_in = '1') ELSE -- from top + '0'; + pr_in_clk_2_b <= rd_out_clk_2_b; -- + pr_in_refclk_b_in <= '0'; -- tx only + pr_in_scan_mode <= '0'; + pr_in_rxpcs_rst <= '1' WHEN (digitalreset_in = '1') ELSE -- from top + '0'; + pr_in_txpcs_rst <= '0'; -- for tx side + + + + mrx_pcs_reset_1 : cycloneiv_hssi_pcs_reset + PORT MAP ( + hard_reset => pr_in_hard_reset, + clk_2_b => pr_in_clk_2_b, + refclk_b_in => pr_in_refclk_b_in, + scan_mode => pr_in_scan_mode, + rxpcs_rst => pr_in_rxpcs_rst, + txpcs_rst => pr_in_txpcs_rst, + rxrst_int => pr_out_rxrst_int, + txrst_int => pr_out_txrst_int + ); + + --/////////////////////////////////////////////////////////////////////////// + -- rx sub-block instantiation: chnl_hip_support ---------------------------// + --/////////////////////////////////////////////////////////////////////////// + + hs_in_eidleinfersel_ch <= "000"; -- elecidleinfersel_in; + hs_in_hip_eidleinfersel_ch <= "000"; -- hipelecidleinfersel_in; + hs_in_hip_powerdown_ch <= hippowerdown_in; + hs_in_hip_rate <= hiprateswitch_in; + hs_in_hip_rxpolarity <= hip8b10binvpolarity_in; + hs_in_hip_txd_ch <= "ZZZZZZZZZZ"; + hs_in_hip_txdeemph <= 'Z'; + hs_in_hip_txdetectrxloopback <= 'Z'; + hs_in_hip_txelecidle <= 'Z'; + hs_in_hip_txmargin_ch <= "00Z"; + hs_in_pcs_phystatus <= rd_out_phystatus; + hs_in_pcs_rxd_ch <= rd_out_rxd(8 DOWNTO 0); + hs_in_pcs_rxelecidle <= pi_out_rxelecidle; + hs_in_pcs_rxstatus_ch <= rd_out_rxstatus; + hs_in_pcs_rxvalid <= rd_out_rxvalid; + hs_in_powerdown_ch <= powerdn_in; -- pipepowerdown_in; + hs_in_rate <= rateswitch_in; + hs_in_rhip_ena <= cram_rhip_ena; + hs_in_rxpolarity <= pipe8b10binvpolarity_in; -- fine !RTL + hs_in_txd_ch <= "ZZZZZZZZZZZ"; + hs_in_txdeemph <= 'Z'; + hs_in_txdetectrxloopback <= 'Z'; + hs_in_txmargin_ch <= "ZZZ"; + hs_in_txpma_local_clk <= 'Z'; + + mrx_hs : cycloneiv_hssi_digi_chnl_hip_spt + PORT MAP ( + + eidleinfersel_ch => hs_in_eidleinfersel_ch, + hip_eidleinfersel_ch => hs_in_hip_eidleinfersel_ch, + hip_powerdown_ch => hs_in_hip_powerdown_ch, + hip_rate => hs_in_hip_rate, + hip_rxpolarity => hs_in_hip_rxpolarity, + hip_txd_ch => hs_in_hip_txd_ch, + hip_txdeemph => hs_in_hip_txdeemph, + hip_txdetectrxloopback => hs_in_hip_txdetectrxloopback, + hip_txelecidle => hs_in_hip_txelecidle, + hip_txmargin_ch => hs_in_hip_txmargin_ch, + pcs_phystatus => hs_in_pcs_phystatus, + pcs_rxd_ch => hs_in_pcs_rxd_ch, + pcs_rxelecidle => hs_in_pcs_rxelecidle, + pcs_rxstatus_ch => hs_in_pcs_rxstatus_ch, + pcs_rxvalid => hs_in_pcs_rxvalid, + powerdown_ch => hs_in_powerdown_ch, + rate => hs_in_rate, + rhip_ena => hs_in_rhip_ena, + rxpolarity => hs_in_rxpolarity, + txd_ch => hs_in_txd_ch, + txdeemph => hs_in_txdeemph, + txdetectrxloopback => hs_in_txdetectrxloopback, + txmargin_ch => hs_in_txmargin_ch, + txpma_local_clk => hs_in_txpma_local_clk, + + hip_phystatus => hs_out_hip_phystatus, + hip_rxd_ch => hs_out_hip_rxd_ch, + hip_rxelecidle => hs_out_hip_rxelecidle, + hip_rxstatus_ch => hs_out_hip_rxstatus_ch, + hip_rxvalid => hs_out_hip_rxvalid, + hip_tx_clk => hs_out_hip_tx_clk, + pcs_eidleinfersel_ch => hs_out_pcs_eidleinfersel_ch, + pcs_powerdown_ch => hs_out_pcs_powerdown_ch, + pcs_rate => hs_out_pcs_rate, + pcs_rxpolarity => hs_out_pcs_rxpolarity, + pcs_txd_ch => hs_out_pcs_txd_ch, + pcs_txdeemph => hs_out_pcs_txdeemph, + pcs_txdetectrxloopback => hs_out_pcs_txdetectrxloopback, + pcs_txmargin_ch => hs_out_pcs_txmargin_ch, + phystatus => hs_out_phystatus, + rxd_ch => hs_out_rxd_ch, + rxelecidle => hs_out_rxelecidle, + rxstatus_ch => hs_out_rxstatus_ch, + rxvalid => hs_out_rxvalid + ); + + --/////////////////////////////////////////////////////////////////////////// + -- tx sub-block instantiation: pipe_interface -----------------------------// + --/////////////////////////////////////////////////////////////////////////// + + --assign pi_in_pipe_rx_clk = rd_out_rx_pipe_clk; + pi_in_pipe_rx_clk <= '0' WHEN (cram_rrx_pipe_enable = '0') ELSE + rd_out_rx_pipe_clk; + pi_in_pipe_tx_clk <= '0'; + pi_in_polinv_rx <= '1' WHEN (invpol_in = '1') ELSE -- from top + '0'; + pi_in_power_state_transition_done <= '0'; -- grounded in rtl - quad_top + pi_in_power_state_transition_done_ena <= '0'; -- grounded in rtl - digi_chnl + pi_in_powerdown <= pipepowerdown_in; -- from top - tx_digi + pi_in_refclk_b <= '0'; -- tx pipe + pi_in_refclk_b_reset <= '0'; -- tx pipe + pi_in_revloopback <= '0'; -- tx pipe + pi_in_rx_detect_valid <= rxdetectvalid_in; -- from top - TX_PMA + pi_in_rx_found <= rxfound_in(0); -- from top - TX_PMA + pi_in_rx_pipe_reset <= rd_out_rx_pipe_soft_reset; + pi_in_rxbeacon <= '0'; -- grounded in rtl - quad_top + --UPDATE + pi_in_rxd <= rd_out_pipe_data; -- rd_out_rxd; -- 64 bits + --UPDATE + pi_in_rxelectricalidle <= rd_out_rxelecidle_int; -- ~pma_out_sigdet; + pi_in_rxpolarity <= '1' WHEN (pipe8b10binvpolarity_in = '1') ELSE -- from top + '0'; + pi_in_tx_elec_idle_comp <= '0'; -- tx pipe + pi_in_tx_pipe_reset <= '0'; -- tx pipe + pi_in_txcompliance <= '0'; -- tx pipe + pi_in_txd_ch <= "00000000000000000000000000000000000000000000"; -- tx pipe - 44 bits + pi_in_txdetectrxloopback <= '0'; -- tx pipe + pi_in_txelecidle <= '0'; -- tx pipe + + pi_in_powerstatein <= pipepowerstate_in; -- from top - new by shawn + pi_in_txdetectrxin <= rxfound_in(1); -- from top of tx_pipe - new by shawn + + -- cycloneiv new input interfaces - ww26.5 + pi_in_speed_change <= rd_out_speed_change; + pi_in_txdeemph <= '0'; -- tx_only + pi_in_txmargin <= "000"; -- tx only + pi_in_txswing <= '0'; -- tx only + + -- ww47 new input interfaces + pi_in_speed_change_centrl <= autospdxnspdchg_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); -- like other fifo bundle + pi_in_speed_change_quad_up <= autospdxnspdchg_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); -- + pi_in_speed_change_quad_down <= autospdxnspdchg_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); -- + + -- ww25.2008 + pi_in_sigdetni <= signaldetected_in; + + -- cycloneiv new cram - ww26.5 + tmp_cram_rtx_elec_idle_delay <= "000"; -- tx_only + tmp_cram_rtxswing_sel_ena <= '0'; -- tx_only + -- [2:0] rtx_elec_idle_delay; -- tx_only + -- rtxswing_sel_ena; -- tx_only + -- rind_error_reporting; -- y + -- rphystatus_delay; -- y + + rx_pipe_interface_top_1 : cycloneiv_hssi_q_pipe_interface_top + PORT MAP ( + phystatus => pi_out_phystatus, + pipe_rx_clk => pi_in_pipe_rx_clk, + pipe_tx_clk => pi_in_pipe_tx_clk, + polinv_rx => pi_in_polinv_rx, + polinv_rx_int => pi_out_polinv_rx_int, + power_state_transition_done => pi_in_power_state_transition_done, + power_state_transition_done_ena => pi_in_power_state_transition_done_ena, + powerdown => pi_in_powerdown, + powerstate => pi_out_powerstate, + rclkcmpinsertpad => cram_rclkcmpinsertpad, + refclk_b => pi_in_refclk_b, + refclk_b_reset => pi_in_refclk_b_reset, + rev_loopbk => pi_out_rev_loopbk, + revloopback => pi_in_revloopback, + rphystatus_rst_toggle => cram_rphystatus_rst_toggle, + rrdwidth_rx => cram_rdwidth_rx, + rrx_detect_bypass => cram_rrx_detect_bypass, + rrx_pipe_enable => cram_rrx_pipe_enable, + -- .rtx_elec_idle_delay (cram_rtx_elec_idle_delay), + rtx_pipe_enable => cram_rtx_pipe_enable, + rx_detect_valid => pi_in_rx_detect_valid, + rx_found => pi_in_rx_found, + rx_pipe_reset => pi_in_rx_pipe_reset, + rxd => pi_in_rxd, + rxd_ch => pi_out_rxd_ch, + rxelecidle => pi_out_rxelecidle, + rxelectricalidle => pi_in_rxelectricalidle, + rxpolarity => pi_in_rxpolarity, + rxstatus => pi_out_rxstatus, + rxvalid => pi_out_rxvalid, + tx_elec_idle => pi_out_tx_elec_idle, + tx_elec_idle_comp => pi_in_tx_elec_idle_comp, + tx_pipe_reset => pi_in_tx_pipe_reset, + txd => pi_out_txd, + txd_ch => pi_in_txd_ch, + txdetectrx => pi_out_txdetectrx, + txdetectrxloopback => pi_in_txdetectrxloopback, + txelecidle => pi_in_txelecidle, + txdetectrxin => pi_in_txdetectrxin, -- shawn + powerstatein => pi_in_powerstatein, -- shawn + use_powerstatein => '1', + -- shawn + + -- CYCLONEIV new interfaces + speed_change => pi_in_speed_change, + txdeemph => pi_in_txdeemph, + txmargin => pi_in_txmargin, + txswing => pi_in_txswing, + + rtx_elec_idle_delay => tmp_cram_rtx_elec_idle_delay, + rtxswing_sel_ena => tmp_cram_rtxswing_sel_ena, + rind_error_reporting => cram_rind_error_reporting, + rphystatus_delay => cram_rphystatus_delay, + + txdeemph_int => pi_out_txdeemph_int, + txmargin_int => pi_out_txmargin_int, + txswing_int => pi_out_txswing_int, + + -- ww25_2008 + sigdetni => pi_in_sigdetni, + + -- WW47 + rindv_rx => cram_rindv_rx, + rmaster_rx => cram_rmaster_rx, + rmaster_up_rx => cram_rmaster_up_rx, + speed_change_centrl => pi_in_speed_change_centrl, + speed_change_quad_up => pi_in_speed_change_quad_up, + speed_change_quad_down => pi_in_speed_change_quad_down + ); + + --/////////////////////////////////////////////////////////////////////////// + -- rx sub-block instantiation: pipe_interface -----------------------------// + --/////////////////////////////////////////////////////////////////////////// + rd_in_a1a2_size <= '1' WHEN (a1a2size_in = '1') ELSE -- from top + '0'; + rd_in_align_status <= alignstatus_in; -- from top + rd_in_align_status_sync_0 <= alignstatussync_in; -- from top + rd_in_align_status_sync_2 <= alignstatussync_in; -- from top - ideally from alignstatusout of channel2 + rd_in_bitloc_rev_en <= '1' WHEN (revbitorderwa_in = '1') ELSE -- from top + '0'; + rd_in_bitslip <= '1' WHEN (bitslip_in = '1') ELSE -- from top + '0'; + rd_in_byte_rev_en <= '1' WHEN (revbyteorderwa_in = '1') ELSE -- from top + '0'; + rd_in_bytordpld <= '1' WHEN (enabyteord_in = '1') ELSE -- from top + '0'; + --UPDATE: freqdet moved to RXPMA. + rd_in_clklow <= '0'; -- VCO divided clk from CDR to freqdet + rd_in_cmpfifourst <= '1' WHEN (rmfiforeset_in = '1') ELSE -- from top + '0'; + rd_in_en_dskw_gp <= enabledeskew_in; -- from top - dskw_sm to dskw_fifo + rd_in_en_dskw_qd <= enabledeskew_in; + rd_in_encdt <= '1' WHEN (enapatternalign_in = '1') ELSE -- from top + '0'; + rd_in_encoder_testbus <= "0000000000"; -- 10 bit + rd_in_fifo_rd_in_comp_0 <= fifordin_in; -- from top + rd_in_fifo_rd_in_comp_2 <= fifordin_in; -- from top - ideally from fifordout of channel2 + rd_in_fifo_rst_rd_gp <= fiforesetrd_in; -- from top - dskw_sm to dskw_fifo + rd_in_fifo_rst_rd_qd <= fiforesetrd_in; + --UPDATE: freqdet moved to RXPMA. + rd_in_fref <= '0'; -- ref clock from CDR to freqdet + rd_in_hard_reset <= '1' WHEN (quadreset_in = '1') ELSE -- from top + '0'; + rd_in_phfifourst_rx <= '1' WHEN (phfiforeset_in = '1') ELSE -- from top + '0'; + rd_in_pld_rx_clk <= coreclk; -- coreclk_in from top + rd_in_pma_testbus <= "00000000"; -- 8 bit + rd_in_polinv_rx <= pi_out_polinv_rx_int; + rd_in_pudi <= datain_in; -- 20 bit from RX PMA + rd_in_rcvd_clk_pma <= recoveredclk_in; -- from RX PMA + rd_in_rcvd_clk0_pma <= masterclk_in; -- from top + rd_in_rdenable_rmf <= '0' WHEN (rmfifordena_in = '0') ELSE -- from top + '1'; + rd_in_rdenable_rx <= phfifordenable_in; -- from top + rd_in_refclk_pma <= refclk_in; + rd_in_rx_control_rs <= xgmctrlin_in; -- from top + rd_in_rx_data_rs <= xgmdatain_in; -- from top - 8 bit + --UPDATE: freqdet moved to RXPMA from top - to freqdet (hardreset) assuming active low + rd_in_rxpma_rst <= '0'; --(analogreset_in === 1'b1) ? 1'b0 : 1'b1; + rd_in_rxpcs_rst <= pr_out_rxrst_int; + rd_in_sigdetni <= signaldetected_in; + rd_in_tx_ctrl_testbus <= "0000000000"; -- 10 bit + rd_in_txlp20b <= parallelfdbk_in; -- from top - 20 bit + rd_in_txpma_local_clk <= localrefclk_in; -- from top + rd_in_wrdisable_rx <= phfifowrdisable_in; -- from top + rd_in_wrenable_rmf <= '0' WHEN (rmfifowrena_in = '0') ELSE -- from top + '1'; + + -- new input interfaces in CYCLONEIV - ww26.5 + rd_in_eidleinfersel <= grayelecidleinferselfromtx_in; -- elecidleinfersel_in; + rd_in_gen2ngen1 <= rateswitchisdone_in; + rd_in_gen2ngen1_bundle <= rateswitchxndone_in; + rd_in_phystatus_int <= pi_out_phystatus; + rd_in_powerdown <= hs_out_pcs_powerdown_ch; + rd_in_rxstatus_int <= pi_out_rxstatus; + rd_in_rxvalid_int <= pi_out_rxvalid; + + -- WW47 input interfaces ------------------------------------------------- + rd_in_rate <= hs_out_pcs_rate; -- rate change output from upper layers. + -- from digi_chnl_support + -- CDR control + rd_in_pld_ltr <= cdrctrllocktorefcl_in; -- PLD control of the CDR when rcdr_ctrl_en = 1'b0 + rd_in_prbs_cid_en <= prbscidenable_in; -- PLD control of PRBS-CID enable + + --todo: use "select" to access the bus + + -- SPR 311609 + rd_in_rx_div2_sync_in_centrl <= phfifox4wrclk_in; + rd_in_rx_div2_sync_in_quad_up <= phfifox4wrclk_in; + rd_in_rx_div2_sync_in_quad_down <= phfifox4wrclk_in; + rd_in_wr_enable_in_centrl <= phfifox4wrenable_in; + rd_in_wr_enable_in_quad_up <= phfifox4wrenable_in; + rd_in_wr_enable_in_quad_down <= phfifox4wrenable_in; + rd_in_rd_enable_in_centrl <= phfifox4rdenable_in; + rd_in_rd_enable_in_quad_up <= phfifox4rdenable_in; + rd_in_rd_enable_in_quad_down <= phfifox4rdenable_in; + rd_in_rx_we_in_centrl <= phfifox4bytesel_in; + rd_in_rx_we_in_quad_up <= phfifox4bytesel_in; + rd_in_rx_we_in_quad_down <= phfifox4bytesel_in; + rd_in_reset_pc_ptrs_in_centrl <= phfifoxnptrsreset_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + rd_in_reset_pc_ptrs_in_quad_up <= phfifoxnptrsreset_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + rd_in_reset_pc_ptrs_in_quad_down <= phfifoxnptrsreset_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + + -- up/down signals are in pipe_top_interface as it is the user of the signal + -- this is needed for RD because of IQP mux + rd_in_speed_change_in_centrl <= autospdxnspdchg_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + + -- Bundle Mode Inputs for config_sel + rd_in_config_sel_centrl <= autospdxnconfigsel_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + rd_in_config_sel_quad_up <= autospdxnconfigsel_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + rd_in_config_sel_quad_down <= autospdxnconfigsel_in(cycloneiv_tx_pcs_mphfifo_index(ph_fifo_xn_select)); + + -- pipeline inputs for IQ bundling + rd_in_rx_div2_sync_in_pipe_quad_up <= iqpphfifoxnwrclk_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_rx_div2_sync_in_pipe_quad_down <= iqpphfifoxnwrclk_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_reset_pc_ptrs_in_pipe_quad_up <= iqpphfifoxnptrsreset_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_reset_pc_ptrs_in_pipe_quad_down <= iqpphfifoxnptrsreset_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_wr_enable_in_pipe_quad_up <= iqpphfifoxnwrenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_wr_enable_in_pipe_quad_down <= iqpphfifoxnwrenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_rd_enable_in_pipe_quad_up <= iqpphfifoxnrdenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_rd_enable_in_pipe_quad_down <= iqpphfifoxnrdenable_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_rx_we_in_pipe_quad_up <= iqpphfifoxnbytesel_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_rx_we_in_pipe_quad_down <= iqpphfifoxnbytesel_in(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_speed_change_in_pipe_quad_up <= iqpautospdxnspgchg(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + rd_in_speed_change_in_pipe_quad_down <= iqpautospdxnspgchg(cycloneiv_tx_pcs_miqp_phfifo_index(ph_fifo_xn_select)); + + -- WW12 input interfaces ------------------------------------------------- + rd_in_pipe_loopbk <= pipeenrevparallellpbkfromtx_in; -- ww12 mega todo + + -- XAUI related - to revisit if need to + rd_in_cg_comp_rd_d_ch0 <= rd_out_cg_comp_rd_d_out; + rd_in_cg_comp_rd_d_ch1 <= rd_out_cg_comp_rd_d_out; + rd_in_cg_comp_rd_d_ch2 <= rd_out_cg_comp_rd_d_out; + rd_in_cg_comp_rd_d_ch3 <= rd_out_cg_comp_rd_d_out; + rd_in_cg_comp_wr_ch0 <= rd_out_cg_comp_wr_out; + rd_in_cg_comp_wr_ch1 <= rd_out_cg_comp_wr_out; + rd_in_cg_comp_wr_ch2 <= rd_out_cg_comp_wr_out; + rd_in_cg_comp_wr_ch3 <= rd_out_cg_comp_wr_out; + + -- XAUI related channel 0 to rest channels in ICD + -- in Quartus sim: using its own ptrs + + rd_in_del_cond_met_0 <= rd_out_del_cond_met_out; + rd_in_fifo_ovr_0 <= rd_out_fifo_ovr_out; + rd_in_latency_comp_0 <= rd_out_latency_comp_out; + rd_in_insert_incomplete_0 <= rd_out_insert_incomplete_out; + + -- SW way + rd_out_rx_div2_sync_out_pipe <= rd_out_rx_div2_sync_out_pipe_up WHEN (cram_rmaster_up_rx = '0') ELSE + rd_out_rx_div2_sync_out_pipe_down; + rd_out_rx_we_out_pipe <= rd_out_rx_we_out_pipe_up WHEN (cram_rmaster_up_rx = '0') ELSE + rd_out_rx_we_out_pipe_down; + rd_out_wr_enable_out_pipe <= rd_out_wr_enable_out_pipe_up WHEN (cram_rmaster_up_rx = '0') ELSE + rd_out_wr_enable_out_pipe_down; + rd_out_rd_enable_out_pipe <= rd_out_rd_enable_out_pipe_up WHEN (cram_rmaster_up_rx = '0') ELSE + rd_out_rd_enable_out_pipe_down; + rd_out_reset_pc_ptrs_out_pipe <= rd_out_reset_pc_ptrs_out_pipe_up WHEN (cram_rmaster_up_rx = '0') ELSE + rd_out_reset_pc_ptrs_out_pipe_down; + rd_out_speed_change_out_pipe <= rd_out_speed_change_out_pipe_up WHEN (cram_rmaster_up_rx = '0') ELSE + rd_out_speed_change_out_pipe_down; + + rd_in_tx_div2_sync_out_pipe_up <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + rd_in_fifo_select_out_pipe_up <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + rd_in_tx_wr_enable_out_pipe_up <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + rd_in_tx_rd_enable_out_pipe_up <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + rd_in_tx_div2_sync_out_pipe_down <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + rd_in_fifo_select_out_pipe_down <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + rd_in_tx_wr_enable_out_pipe_down <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + rd_in_tx_rd_enable_out_pipe_down <= 'Z'; --only impact test_bus from corresponding tx channels output *_out_pipe + + -- WW25.2008 input interfaces ----------------------------------------------- + rd_in_pcs_wrapback_in <= "0000000001000000000000000000000000000000000000000000000000000000000000"; + + + digi_rx_1 : cycloneiv_hssi_rx_digi + PORT MAP ( + rxpcs_rst => rd_in_rxpcs_rst, + hard_reset => rd_in_hard_reset, + rxpma_rst => rd_in_rxpma_rst, + cmpfifourst => rd_in_cmpfifourst, + phfifourst_rx => rd_in_phfifourst_rx, + rphfifourstrx => cram_rphfifourstrx, + scan_mode => cram_scan_mode, + encdt => rd_in_encdt, + a1a2_size => rd_in_a1a2_size, + bitslip => rd_in_bitslip, + rdenable_rmf => rd_in_rdenable_rmf, + wrenable_rmf => rd_in_wrenable_rmf, + pld_rx_clk => rd_in_pld_rx_clk, + polinv_rx => rd_in_polinv_rx, + bitloc_rev_en => rd_in_bitloc_rev_en, + byte_rev_en => rd_in_byte_rev_en, + rcvd_clk_pma => rd_in_rcvd_clk_pma, + pudi => rd_in_pudi, + sigdetni => rd_in_sigdetni, + fifo_rst_rd_qd => rd_in_fifo_rst_rd_qd, + fifo_rst_rd_gp => rd_in_fifo_rst_rd_gp, + en_dskw_qd => rd_in_en_dskw_qd, + en_dskw_gp => rd_in_en_dskw_gp, + is_lane0 => cram_is_lane0, + align_status => rd_in_align_status, + align_status_sync_0 => rd_in_align_status_sync_0, + align_status_sync_2 => rd_in_align_status_sync_2, + rx_data_rs => rd_in_rx_data_rs, + rx_control_rs => rd_in_rx_control_rs, + rcvd_clk0_pma => rd_in_rcvd_clk0_pma, + fifo_rd_in_comp_0 => rd_in_fifo_rd_in_comp_0, + fifo_rd_in_comp_2 => rd_in_fifo_rd_in_comp_2, + txlp20b => rd_in_txlp20b, + refclk_pma => rd_in_refclk_pma, + tx_pma_clk => rd_in_txpma_local_clk, + fref => rd_in_fref, + clklow => rd_in_clklow, + bytordpld => rd_in_bytordpld, + wrdisable_rx => rd_in_wrdisable_rx, + rdenable_rx => rd_in_rdenable_rx, + pma_testbus => rd_in_pma_testbus, + encoder_testbus => rd_in_encoder_testbus, + tx_ctrl_testbus => rd_in_tx_ctrl_testbus, + fifo_rd_out_comp => rd_out_fifo_rd_out_comp, + rxd => rd_out_rxd, + rev_loop_data => rd_out_rev_loop_data, + rx_clk => rd_out_rx_clk, + bisterr => rd_out_bisterr, + cg_comma => rd_out_cg_comma, + clk_2_b => rd_out_clk_2_b, + rcvd_clk_pma_b => rd_out_rcvd_clk_pma_b, + sync_status => rd_out_sync_status, + align_status_sync => rd_out_align_status_sync, + dec_data_valid => rd_out_dec_data_valid, + dec_data => rd_out_dec_data, + dec_ctl => rd_out_dec_ctl, + running_disp => rd_out_running_disp, + selftest_done => rd_out_selftest_done, + selftest_err => rd_out_selftest_err, + err_data => rd_out_err_data, + err_ctl => rd_out_err_ctl, + prbs_done => rd_out_prbs_done, + prbs_err_lt => rd_out_prbs_err_lt, + signal_detect_out => rd_out_signal_detect_out, + align_det_sync => rd_out_align_det_sync, + rd_align => rd_out_rd_align, + bistdone => rd_out_bistdone, + rlv => rd_out_rlv, + rlv_lt => rd_out_rlv_lt, + almost_fl_rmf => rd_out_almost_fl_rmf, + full_rmf => rd_out_full_rmf, + almost_mt_rmf => rd_out_almost_mt_rmf, + empty_rmf => rd_out_empty_rmf, + freq_lock => rd_out_freq_lock, + full_rx => rd_out_full_rx, + empty_rx => rd_out_empty_rx, + a1a2_k1k2_flag => rd_out_a1a2_k1k2_flag, + byteord_flag => rd_out_byteord_flag, + rx_pipe_clk => rd_out_rx_pipe_clk, + chnl_test_bus_out => rd_out_chnl_test_bus_out, + rx_pipe_soft_reset => rd_out_rx_pipe_soft_reset, + rskpsetbased => cram_rskpsetbased, + rtruebac2bac => cram_rtruebac2bac, + rcmpfifourst => cram_rcmpfifourst, + rcomp_size => cram_rcomp_size, + rcomp_pat => cram_rcomp_pat, + rrundisp => cram_rrundisp, + rib_inv_cd => cram_rib_inv_cd, + rrlv_en => cram_rrlv_en, + rsync_sm_dis => cram_rsync_sm_dis, + rautobtalg_dis => cram_rautobtalg_dis, + rdis_rx_disp => cram_rdis_rx_disp, + rmatchen => cram_rmatchen, + rgenericfifo => cram_rgenericfifo, + rendec_rx => cram_rendec_rx, + rdwidth_rx => cram_rdwidth_rx, + rlp20ben => cram_rlp20ben, + rrxfifo_dis => cram_rrxfifo_dis, + rpmadwidth_rx => cram_rpmadwidth_rx, + rpma_doublewidth_rx => cram_rpma_doublewidth_rx, + renumber => cram_renumber, + rknumber => cram_rknumber, + renpolinv_rx => cram_renpolinv_rx, + rgnumber => cram_rgnumber, + rclkcmpsqmd => cram_rclkcmpsqmd, + rclkcmpsq1p => cram_rclkcmpsq1p, + rclkcmpsq1n => cram_rclkcmpsq1n, + rosnumber => cram_rosnumber, + rosbased => cram_rosbased, + rkchar => cram_rkchar, + rcascaded_8b10b_en_rx => cram_rcascaded_8b10b_en_rx, + resync_badcg_en => cram_resync_badcg_en, + rencdt_rising => cram_rencdt_rising, + rcomp_pat_porn => cram_rcomp_pat_porn, + rprbsen_rx => cram_rprbsen_rx, + rprbs_clr_rslt_rx => cram_rprbs_clr_rslt_rx, + rbisten_rx => cram_rbisten_rx, + rbist_clr_rx => cram_rbist_clr_rx, + rwa_6g_en => cram_rwa_6g_en, + rbytord_2sym_en => cram_rbytord_2sym_en, + rbysync_polinv_en => cram_rbysync_polinv_en, + rbitloc_rev_en => cram_rbitloc_rev_en, + rbyte_rev_en => cram_rbyte_rev_en, + rbyteorden => cram_rbyteorden, + rbytordplden => cram_rbytordplden, + rphfifopldenrx => cram_rphfifopldenrx, + rautoinsdis => cram_rautoinsdis, + rppmsel => cram_rppmsel, + rforce0_freqdet => cram_rforce0_freqdet, + rforce1_freqdet => cram_rforce1_freqdet, + rbytordpat => cram_rbytordpat, + rbytordpad => cram_rbytordpad, + rforce_sig_det_pcs => cram_rforce_sig_det_pcs, + rfreerun_rx => cram_rfreerun_rx, + rrcvd_clk_sel => cram_rrcvd_clk_sel, + rclk_1_sel => cram_rclk_1_sel, + rclk_2_sel => cram_rclk_2_sel, + rrx_rd_clk_sel => cram_rrx_rd_clk_sel, + rall_one_dect_only => cram_rall_one_dect_only, + rtest_bus_sel => cram_rtest_bus_sel, + r8b10b_dec_ibm_en => cram_r8b10b_dec_ibm_en, + rrxfifo_lowlatency_en => cram_rrxfifo_lowlatency_en, + rppm_cnt_reset => cram_rppm_cnt_reset, + sel_gp_md => cram_sel_gp_md, + rclkcmpinsertpad => cram_rclkcmpinsertpad, + rindv_rx => cram_rindv_rx, + dskwclksel => cram_dskwclksel, + rdskposdisp => cram_rdskposdisp, + rdskchrp => cram_rdskchrp, + rendec_data_sel_rx => cram_rendec_data_sel_rx, + rprbs_sel => cram_rprbs_sel, + rbist_sel => cram_rbist_sel, + rcxpat_chnl_en => cram_rcxpat_chnl_en, + + -- new CYCLONEIV interfaces ---------------------------------------- + eidleinfersel => rd_in_eidleinfersel, + gen2ngen1 => rd_in_gen2ngen1, + gen2ngen1_bundle => rd_in_gen2ngen1_bundle, + phystatus_int => rd_in_phystatus_int, + powerdown => rd_in_powerdown, + rxstatus_int => rd_in_rxstatus_int, + rxvalid_int => rd_in_rxvalid_int, + + rclkcmp_pipe_en => cram_rclkcmp_pipe_en, + rrxpcsclkpwdn => cram_rrxpcsclkpwdn, + rstart_threshold => cram_rstart_threshold, + rins_threshold => cram_rins_threshold, + rdel_threshold => cram_rdel_threshold, + rfull_threshold => cram_rfull_threshold, + rempty_threshold => cram_rempty_threshold, + rinvalid_code_err_only => cram_rinvalid_code_err_only, + rrxpcsbypass_en => cram_rrxpcsbypass_en, + rauto_speed_ena => cram_rauto_speed_ena, + rfreq_sel => cram_rfreq_sel, + rpma_done_count => cram_rpma_done_count, + reidleinferenable => cram_reidleinferenable, + reidle_com_detect => cram_reidle_com_detect, + + phystatus => rd_out_phystatus, + pipe_data => rd_out_pipe_data, + soft_reset_rclk1 => rd_out_soft_reset_rclk1, + speed_change => rd_out_speed_change, + rxelecidle_int => rd_out_rxelecidle_int, + rxstatus => rd_out_rxstatus, + rxvalid => rd_out_rxvalid, + + -- ww47 input port interfaces -------------------------------- + config_sel_centrl => rd_in_config_sel_centrl, + config_sel_quad_down => rd_in_config_sel_quad_down, + config_sel_quad_up => rd_in_config_sel_quad_up, + pld_ltr => rd_in_pld_ltr, + prbs_cid_en => rd_in_prbs_cid_en, + rate => rd_in_rate, + rd_enable_in_centrl => rd_in_rd_enable_in_centrl, + rd_enable_in_pipe_quad_down => rd_in_rd_enable_in_pipe_quad_down, + rd_enable_in_pipe_quad_up => rd_in_rd_enable_in_pipe_quad_up, + rd_enable_in_quad_down => rd_in_rd_enable_in_quad_down, + rd_enable_in_quad_up => rd_in_rd_enable_in_quad_up, + reset_pc_ptrs_in_centrl => rd_in_reset_pc_ptrs_in_centrl, + reset_pc_ptrs_in_pipe_quad_down => rd_in_reset_pc_ptrs_in_pipe_quad_down, + reset_pc_ptrs_in_pipe_quad_up => rd_in_reset_pc_ptrs_in_pipe_quad_up, + reset_pc_ptrs_in_quad_down => rd_in_reset_pc_ptrs_in_quad_down, + reset_pc_ptrs_in_quad_up => rd_in_reset_pc_ptrs_in_quad_up, + rx_div2_sync_in_centrl => rd_in_rx_div2_sync_in_centrl, + rx_div2_sync_in_pipe_quad_down => rd_in_rx_div2_sync_in_pipe_quad_down, + rx_div2_sync_in_pipe_quad_up => rd_in_rx_div2_sync_in_pipe_quad_up, + rx_div2_sync_in_quad_down => rd_in_rx_div2_sync_in_quad_down, + rx_div2_sync_in_quad_up => rd_in_rx_div2_sync_in_quad_up, + rx_we_in_centrl => rd_in_rx_we_in_centrl, + rx_we_in_pipe_quad_down => rd_in_rx_we_in_pipe_quad_down, + rx_we_in_pipe_quad_up => rd_in_rx_we_in_pipe_quad_up, + rx_we_in_quad_down => rd_in_rx_we_in_quad_down, + rx_we_in_quad_up => rd_in_rx_we_in_quad_up, + speed_change_in_centrl => rd_in_speed_change_in_centrl, + speed_change_in_pipe_quad_down => rd_in_speed_change_in_pipe_quad_down, + speed_change_in_pipe_quad_up => rd_in_speed_change_in_pipe_quad_up, + wr_enable_in_centrl => rd_in_wr_enable_in_centrl, + wr_enable_in_pipe_quad_down => rd_in_wr_enable_in_pipe_quad_down, + wr_enable_in_pipe_quad_up => rd_in_wr_enable_in_pipe_quad_up, + wr_enable_in_quad_down => rd_in_wr_enable_in_quad_down, + wr_enable_in_quad_up => rd_in_wr_enable_in_quad_up, + + -- ww47 output port interfaces -------------------------------- + dis_pc_byte => rd_out_dis_pc_byte, + early_eios => rd_out_early_eios, + ltr => rd_out_ltr, + pcie_switch => rd_out_pcie_switch, + reset_pc_ptrs => rd_out_reset_pc_ptrs, + wa_boundary => rd_out_wa_boundary, + + -- ww47 CRAM interfaces -------------------------------- + rauto_deassert_pc_rst_cnt => cram_rauto_deassert_pc_rst_cnt, + rauto_pc_en_cnt => cram_rauto_pc_en_cnt, + rbytord_6g_mask_en => cram_rbytord_6g_mask_en, + rbytord_s2gx => cram_rbytord_s2gx, + --.rbytordpat (cram_rbytordpat), width change from 10 to 20 + rcdr_ctrl_en => cram_rcdr_ctrl_en, + rcid_en => cram_rcid_en, + rcid_len_rx => cram_rcid_len_rx, + rcid_pattern_rx => cram_rcid_pattern_rx, + rfts_count => cram_rfts_count, + rmask_count => cram_rmask_count, + rmaster_rx => cram_rmaster_rx, + rmaster_up_rx => cram_rmaster_up_rx, + rphfifo_regmode_rx => cram_rphfifo_regmode_rx, + rpipeline_bypass_rx => cram_rpipeline_bypass_rx, + rrxvalid_mask => cram_rrxvalid_mask, + rself_sw_en_rx => cram_rself_sw_en_rx, + --.rtest_bus_sel (cram_rtest_bus_sel), width added 1 + rwait_count => cram_rwait_count, + + -- ww12 port interfaces -------------------------------- + pipe_loopbk => rd_in_pipe_loopbk, + + -- XAUI related ports + cg_comp_rd_d_out => rd_out_cg_comp_rd_d_out, + cg_comp_wr_out => rd_out_cg_comp_wr_out, + cg_comp_rd_d_ch0 => rd_in_cg_comp_rd_d_ch0, + cg_comp_rd_d_ch1 => rd_in_cg_comp_rd_d_ch1, + cg_comp_rd_d_ch2 => rd_in_cg_comp_rd_d_ch2, + cg_comp_rd_d_ch3 => rd_in_cg_comp_rd_d_ch3, + cg_comp_wr_ch0 => rd_in_cg_comp_wr_ch0, + cg_comp_wr_ch1 => rd_in_cg_comp_wr_ch1, + cg_comp_wr_ch2 => rd_in_cg_comp_wr_ch2, + cg_comp_wr_ch3 => rd_in_cg_comp_wr_ch3, + + del_cond_met_out => rd_out_del_cond_met_out, + fifo_ovr_out => rd_out_fifo_ovr_out, + latency_comp_out => rd_out_latency_comp_out, + insert_incomplete_out => rd_out_insert_incomplete_out, + del_cond_met_0 => rd_in_del_cond_met_0, + fifo_ovr_0 => rd_in_fifo_ovr_0, + latency_comp_0 => rd_in_latency_comp_0, + insert_incomplete_0 => rd_in_insert_incomplete_0, + + -- bundle ptrs in ww12 - split up/down + rd_enable_out_pipe_up => rd_out_rd_enable_out_pipe_up, + reset_pc_ptrs_out_pipe_up => rd_out_reset_pc_ptrs_out_pipe_up, + rx_div2_sync_out_pipe_up => rd_out_rx_div2_sync_out_pipe_up, + rx_we_out_pipe_up => rd_out_rx_we_out_pipe_up, + speed_change_out_pipe_up => rd_out_speed_change_out_pipe_up, + wr_enable_out_pipe_up => rd_out_wr_enable_out_pipe_up, + + rd_enable_out_pipe_down => rd_out_rd_enable_out_pipe_down, + reset_pc_ptrs_out_pipe_down => rd_out_reset_pc_ptrs_out_pipe_down, + rx_div2_sync_out_pipe_down => rd_out_rx_div2_sync_out_pipe_down, + rx_we_out_pipe_down => rd_out_rx_we_out_pipe_down, + speed_change_out_pipe_down => rd_out_speed_change_out_pipe_down, + wr_enable_out_pipe_down => rd_out_wr_enable_out_pipe_down, + + -- tx to rx pipe ptr for testbus + fifo_select_out_pipe_up => rd_in_fifo_select_out_pipe_up, + tx_div2_sync_out_pipe_up => rd_in_tx_div2_sync_out_pipe_up, + tx_rd_enable_out_pipe_up => rd_in_tx_rd_enable_out_pipe_up, + tx_wr_enable_out_pipe_up => rd_in_tx_wr_enable_out_pipe_up, + + fifo_select_out_pipe_down => rd_in_fifo_select_out_pipe_down, + tx_div2_sync_out_pipe_down => rd_in_tx_div2_sync_out_pipe_down, + tx_rd_enable_out_pipe_down => rd_in_tx_rd_enable_out_pipe_down, + tx_wr_enable_out_pipe_down => rd_in_tx_wr_enable_out_pipe_down, + + -- ww12 CRAM interfaces -------------------------------- + rwait_for_phfifo_cnt => cram_rwait_for_phfifo_cnt, + rppm_post_eidle_del => cram_rppm_post_eidle_del, + rppm_gen1_2xcnt_en => cram_rppm_gen1_2xcnt_en, + riei_eios_priority_dis => cram_riei_eios_priority_dis, + rgen1_sigdet_ena => cram_rgen1_sigdet_ena, + + -- ww25.2008 port interface ----------------------------- + pcs_wrapback_in => rd_in_pcs_wrapback_in, + + -- ww25.2008 CRAM interface ----------------------------- + rpcs_wrapback_en => cram_rpcs_wrapback_en, + rrx_pipe_enable => cram_rrx_pipe_enable, + rerr_flags_sel => cram_rerr_flags_sel + + ); + +END trans; + +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 46 mux21 24 oper_mux 5 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_dskw_sm IS + PORT + ( + align_det_sync : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + align_status : OUT STD_LOGIC; + clk_1 : IN STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + enable_deskew : OUT STD_LOGIC; + fifo_reset_rd : OUT STD_LOGIC; + octal_mode : IN STD_LOGIC; + rd_align : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + soft_reset : IN STD_LOGIC; + sync_status : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END cycloneiv_hssi_dskw_sm; + + ARCHITECTURE RTL OF cycloneiv_hssi_dskw_sm IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nl0ll35 : STD_LOGIC := '0'; + SIGNAL nl0ll36 : STD_LOGIC := '0'; + SIGNAL wire_nl0ll36_w_lg_w_lg_q268w269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ll36_w_lg_q268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl0lO33 : STD_LOGIC := '0'; + SIGNAL nl0lO34 : STD_LOGIC := '0'; + SIGNAL wire_nl0lO34_w_lg_w_lg_q232w233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lO34_w_lg_q232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl0Oi31 : STD_LOGIC := '0'; + SIGNAL nl0Oi32 : STD_LOGIC := '0'; + SIGNAL wire_nl0Oi32_w_lg_w_lg_q227w228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi32_w_lg_q227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl0Ol29 : STD_LOGIC := '0'; + SIGNAL nl0Ol30 : STD_LOGIC := '0'; + SIGNAL wire_nl0Ol30_w_lg_w_lg_q198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol30_w_lg_q198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl0OO27 : STD_LOGIC := '0'; + SIGNAL nl0OO28 : STD_LOGIC := '0'; + SIGNAL wire_nl0OO28_w_lg_w_lg_q195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0OO28_w_lg_q195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli0i19 : STD_LOGIC := '0'; + SIGNAL nli0i20 : STD_LOGIC := '0'; + SIGNAL wire_nli0i20_w_lg_w_lg_q121w122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i20_w_lg_q121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli0l17 : STD_LOGIC := '0'; + SIGNAL nli0l18 : STD_LOGIC := '0'; + SIGNAL wire_nli0l18_w_lg_w_lg_q89w90w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l18_w_lg_q89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli1i25 : STD_LOGIC := '0'; + SIGNAL nli1i26 : STD_LOGIC := '0'; + SIGNAL wire_nli1i26_w_lg_w_lg_q165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i26_w_lg_q165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli1l23 : STD_LOGIC := '0'; + SIGNAL nli1l24 : STD_LOGIC := '0'; + SIGNAL wire_nli1l24_w_lg_w_lg_q132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1l24_w_lg_q132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli1O21 : STD_LOGIC := '0'; + SIGNAL nli1O22 : STD_LOGIC := '0'; + SIGNAL wire_nli1O22_w_lg_w_lg_q128w129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1O22_w_lg_q128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliii15 : STD_LOGIC := '0'; + SIGNAL nliii16 : STD_LOGIC := '0'; + SIGNAL nliOi13 : STD_LOGIC := '0'; + SIGNAL nliOi14 : STD_LOGIC := '0'; + SIGNAL nll0i10 : STD_LOGIC := '0'; + SIGNAL nll0i9 : STD_LOGIC := '0'; + SIGNAL nll0O7 : STD_LOGIC := '0'; + SIGNAL nll0O8 : STD_LOGIC := '0'; + SIGNAL nll1i11 : STD_LOGIC := '0'; + SIGNAL nll1i12 : STD_LOGIC := '0'; + SIGNAL nlliO5 : STD_LOGIC := '0'; + SIGNAL nlliO6 : STD_LOGIC := '0'; + SIGNAL nllll3 : STD_LOGIC := '0'; + SIGNAL nllll4 : STD_LOGIC := '0'; + SIGNAL nlO1i1 : STD_LOGIC := '0'; + SIGNAL nlO1i2 : STD_LOGIC := '0'; + SIGNAL n0il : STD_LOGIC := '0'; + SIGNAL nii : STD_LOGIC := '0'; + SIGNAL nil : STD_LOGIC := '0'; + SIGNAL nli : STD_LOGIC := '0'; + SIGNAL nllO : STD_LOGIC := '0'; + SIGNAL nlOi : STD_LOGIC := '0'; + SIGNAL nlOl : STD_LOGIC := '0'; + SIGNAL wire_niO_CLRN : STD_LOGIC; + SIGNAL wire_niO_w_lg_nil83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO_w_lg_w_lg_nil83w84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n00O : STD_LOGIC := '0'; + SIGNAL n0ii : STD_LOGIC := '0'; + SIGNAL nO : STD_LOGIC := '0'; + SIGNAL wire_nl_CLRN : STD_LOGIC; + SIGNAL wire_nl_w_lg_n00O271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl_w_lg_nO80w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0i_w_lg_dataout58w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1i_w_lg_dataout59w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_n0li_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0li_o : STD_LOGIC; + SIGNAL wire_n0li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0ll_o : STD_LOGIC; + SIGNAL wire_n0ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0lO_o : STD_LOGIC; + SIGNAL wire_n0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oi_o : STD_LOGIC; + SIGNAL wire_n0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Ol_o : STD_LOGIC; + SIGNAL wire_n0Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_nli0O126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiO158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlili82w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nll1O57w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli0O : STD_LOGIC; + SIGNAL nliiO : STD_LOGIC; + SIGNAL nlili : STD_LOGIC; + SIGNAL nlill : STD_LOGIC; + SIGNAL nlilO : STD_LOGIC; + SIGNAL nliOO : STD_LOGIC; + SIGNAL nll1O : STD_LOGIC; + SIGNAL nllil : STD_LOGIC; + SIGNAL nllli : STD_LOGIC; + SIGNAL nllOl : STD_LOGIC; + BEGIN + + wire_w_lg_nli0O126w(0) <= NOT nli0O; + wire_w_lg_nliiO158w(0) <= NOT nliiO; + wire_w_lg_nlili82w(0) <= NOT nlili; + wire_w_lg_nll1O57w(0) <= NOT nll1O; + wire_w_lg_soft_reset2w(0) <= NOT soft_reset; + align_status <= nlOl; + curr_state <= ( "0" & nlOi & nllO & n0il); + enable_deskew <= n0ii; + fifo_reset_rd <= (n0ii AND wire_nl_w_lg_n00O271w(0)); + nli0O <= wire_niO_w_lg_w_lg_nil83w84w(0); + nliiO <= (wire_niO_w_lg_w_lg_nil83w84w(0) OR (NOT (nliii16 XOR nliii15))); + nlili <= (wire_nl_w_lg_nO80w(0) AND wire_n0i_dataout); + nlill <= (nil AND wire_nliO_dataout); + nlilO <= ((((((((align_det_sync(0) AND align_det_sync(1)) AND align_det_sync(2)) AND align_det_sync(3)) AND align_det_sync(4)) AND align_det_sync(5)) AND align_det_sync(6)) AND align_det_sync(7)) AND (nliOi14 XOR nliOi13)); + nliOO <= (wire_n0i_w_lg_dataout58w(0) AND wire_n1i_w_lg_dataout59w(0)); + nll1O <= ((((((((rd_align(0) OR rd_align(1)) OR rd_align(2)) OR rd_align(3)) OR rd_align(4)) OR rd_align(5)) OR rd_align(6)) OR rd_align(7)) OR (NOT (nll0i10 XOR nll0i9))); + nllil <= (((((((rd_align(0) AND rd_align(1)) AND rd_align(2)) AND rd_align(3)) AND rd_align(4)) AND rd_align(5)) AND rd_align(6)) AND rd_align(7)); + nllli <= ((((((((sync_status(0) AND sync_status(1)) AND sync_status(2)) AND sync_status(3)) AND sync_status(4)) AND sync_status(5)) AND sync_status(6)) AND sync_status(7)) AND (nllll4 XOR nllll3)); + nllOl <= '1'; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0ll35 <= nl0ll36; + END IF; + if (now = 0 ns) then + nl0ll35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0ll36 <= nl0ll35; + END IF; + END PROCESS; + wire_nl0ll36_w_lg_w_lg_q268w269w(0) <= wire_nl0ll36_w_lg_q268w(0) AND wire_n0OO_dataout; + wire_nl0ll36_w_lg_q268w(0) <= nl0ll36 XOR nl0ll35; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0lO33 <= nl0lO34; + END IF; + if (now = 0 ns) then + nl0lO33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0lO34 <= nl0lO33; + END IF; + END PROCESS; + wire_nl0lO34_w_lg_w_lg_q232w233w(0) <= wire_nl0lO34_w_lg_q232w(0) AND wire_ni0l_dataout; + wire_nl0lO34_w_lg_q232w(0) <= nl0lO34 XOR nl0lO33; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0Oi31 <= nl0Oi32; + END IF; + if (now = 0 ns) then + nl0Oi31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0Oi32 <= nl0Oi31; + END IF; + END PROCESS; + wire_nl0Oi32_w_lg_w_lg_q227w228w(0) <= wire_nl0Oi32_w_lg_q227w(0) AND nii; + wire_nl0Oi32_w_lg_q227w(0) <= nl0Oi32 XOR nl0Oi31; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0Ol29 <= nl0Ol30; + END IF; + if (now = 0 ns) then + nl0Ol29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0Ol30 <= nl0Ol29; + END IF; + END PROCESS; + wire_nl0Ol30_w_lg_w_lg_q198w199w(0) <= wire_nl0Ol30_w_lg_q198w(0) AND wire_nili_dataout; + wire_nl0Ol30_w_lg_q198w(0) <= nl0Ol30 XOR nl0Ol29; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0OO27 <= nl0OO28; + END IF; + if (now = 0 ns) then + nl0OO27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nl0OO28 <= nl0OO27; + END IF; + END PROCESS; + wire_nl0OO28_w_lg_w_lg_q195w196w(0) <= wire_nl0OO28_w_lg_q195w(0) AND wire_nill_dataout; + wire_nl0OO28_w_lg_q195w(0) <= nl0OO28 XOR nl0OO27; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli0i19 <= nli0i20; + END IF; + if (now = 0 ns) then + nli0i19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli0i20 <= nli0i19; + END IF; + END PROCESS; + wire_nli0i20_w_lg_w_lg_q121w122w(0) <= wire_nli0i20_w_lg_q121w(0) AND nil; + wire_nli0i20_w_lg_q121w(0) <= nli0i20 XOR nli0i19; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli0l17 <= nli0l18; + END IF; + if (now = 0 ns) then + nli0l17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli0l18 <= nli0l17; + END IF; + END PROCESS; + wire_nli0l18_w_lg_w_lg_q89w90w(0) <= wire_nli0l18_w_lg_q89w(0) AND n0il; + wire_nli0l18_w_lg_q89w(0) <= nli0l18 XOR nli0l17; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli1i25 <= nli1i26; + END IF; + if (now = 0 ns) then + nli1i25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli1i26 <= nli1i25; + END IF; + END PROCESS; + wire_nli1i26_w_lg_w_lg_q165w166w(0) <= wire_nli1i26_w_lg_q165w(0) AND wire_w_lg_nli0O126w(0); + wire_nli1i26_w_lg_q165w(0) <= nli1i26 XOR nli1i25; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli1l23 <= nli1l24; + END IF; + if (now = 0 ns) then + nli1l23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli1l24 <= nli1l23; + END IF; + END PROCESS; + wire_nli1l24_w_lg_w_lg_q132w133w(0) <= wire_nli1l24_w_lg_q132w(0) AND nllO; + wire_nli1l24_w_lg_q132w(0) <= nli1l24 XOR nli1l23; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli1O21 <= nli1O22; + END IF; + if (now = 0 ns) then + nli1O21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nli1O22 <= nli1O21; + END IF; + END PROCESS; + wire_nli1O22_w_lg_w_lg_q128w129w(0) <= wire_nli1O22_w_lg_q128w(0) AND n0il; + wire_nli1O22_w_lg_q128w(0) <= nli1O22 XOR nli1O21; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nliii15 <= nliii16; + END IF; + if (now = 0 ns) then + nliii15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nliii16 <= nliii15; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nliOi13 <= nliOi14; + END IF; + if (now = 0 ns) then + nliOi13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nliOi14 <= nliOi13; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nll0i10 <= nll0i9; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nll0i9 <= nll0i10; + END IF; + if (now = 0 ns) then + nll0i9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nll0O7 <= nll0O8; + END IF; + if (now = 0 ns) then + nll0O7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nll0O8 <= nll0O7; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nll1i11 <= nll1i12; + END IF; + if (now = 0 ns) then + nll1i11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nll1i12 <= nll1i11; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlliO5 <= nlliO6; + END IF; + if (now = 0 ns) then + nlliO5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlliO6 <= nlliO5; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nllll3 <= nllll4; + END IF; + if (now = 0 ns) then + nllll3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nllll4 <= nllll3; + END IF; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlO1i1 <= nlO1i2; + END IF; + if (now = 0 ns) then + nlO1i1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_1) + BEGIN + IF (clk_1 = '1' AND clk_1'event) THEN nlO1i2 <= nlO1i1; + END IF; + END PROCESS; + PROCESS (clk_1, wire_niO_CLRN) + BEGIN + IF (wire_niO_CLRN = '0') THEN + n0il <= '0'; + nii <= '0'; + nil <= '0'; + nli <= '0'; + nllO <= '0'; + nlOi <= '0'; + nlOl <= '0'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + n0il <= wire_n0lO_o; + nii <= wire_n0ll_o; + nil <= nli; + nli <= wire_nll_dataout; + nllO <= wire_n0Oi_o; + nlOi <= wire_n0Ol_o; + nlOl <= nii; + END IF; + END PROCESS; + wire_niO_CLRN <= ((nlliO6 XOR nlliO5) AND wire_w_lg_soft_reset2w(0)); + wire_niO_w_lg_nil83w(0) <= NOT nil; + wire_niO_w_lg_w_lg_nil83w84w(0) <= wire_niO_w_lg_nil83w(0) OR nliOO; + PROCESS (clk_1, soft_reset, wire_nl_CLRN) + BEGIN + IF (soft_reset = '1') THEN + n00O <= '1'; + n0ii <= '1'; + nO <= '1'; + ELSIF (wire_nl_CLRN = '0') THEN + n00O <= '0'; + n0ii <= '0'; + nO <= '0'; + ELSIF (clk_1 = '1' AND clk_1'event) THEN + n00O <= n0ii; + n0ii <= wire_n0li_o; + nO <= n00O; + END IF; + if (now = 0 ns) then + n00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nO <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl_CLRN <= (nlO1i2 XOR nlO1i1); + wire_nl_w_lg_n00O271w(0) <= NOT n00O; + wire_nl_w_lg_nO80w(0) <= NOT nO; + wire_n0i_dataout <= nllil WHEN octal_mode = '1' ELSE ((((rd_align(0) AND rd_align(1)) AND rd_align(2)) AND rd_align(3)) AND (nll0O8 XOR nll0O7)); + wire_n0i_w_lg_dataout58w(0) <= NOT wire_n0i_dataout; + wire_n0OO_dataout <= n0ii OR nli0O; + wire_n1i_dataout <= wire_w_lg_nll1O57w(0) WHEN octal_mode = '1' ELSE (NOT ((((rd_align(0) OR rd_align(1)) OR rd_align(2)) OR rd_align(3)) OR (NOT (nll1i12 XOR nll1i11)))); + wire_n1i_w_lg_dataout59w(0) <= NOT wire_n1i_dataout; + wire_ni0i_dataout <= n0ii OR wire_niO_w_lg_nil83w(0); + wire_ni0l_dataout <= nii AND NOT(wire_niO_w_lg_nil83w(0)); + wire_ni0O_dataout <= wire_niil_dataout AND NOT(wire_niO_w_lg_nil83w(0)); + wire_ni1i_dataout <= nii AND NOT(nli0O); + wire_ni1l_dataout <= wire_n0i_w_lg_dataout58w(0) AND NOT(nli0O); + wire_niii_dataout <= wire_niiO_dataout AND NOT(wire_niO_w_lg_nil83w(0)); + wire_niil_dataout <= wire_n0i_dataout OR nliOO; + wire_niiO_dataout <= wire_n0i_w_lg_dataout58w(0) OR nliOO; + wire_nili_dataout <= wire_nilO_dataout AND NOT(wire_niO_w_lg_nil83w(0)); + wire_nill_dataout <= nliOO AND NOT(wire_niO_w_lg_nil83w(0)); + wire_nilO_dataout <= wire_n0i_w_lg_dataout58w(0) AND NOT(nliOO); + wire_niOi_dataout <= nii WHEN nliiO = '1' ELSE wire_nl1l_dataout; + wire_niOl_dataout <= n0ii OR nliiO; + wire_niOO_dataout <= wire_n0i_w_lg_dataout58w(0) AND NOT(nliiO); + wire_nl0i_dataout <= wire_w_lg_nlili82w(0) AND NOT(nliiO); + wire_nl0l_dataout <= nlili AND NOT(nliiO); + wire_nl1i_dataout <= wire_n0i_dataout AND NOT(nliiO); + wire_nl1l_dataout <= nii OR wire_n0i_dataout; + wire_nlii_dataout <= n0ii AND NOT(nlill); + wire_nliO_dataout <= nlilO WHEN octal_mode = '1' ELSE (((align_det_sync(0) AND align_det_sync(1)) AND align_det_sync(2)) AND align_det_sync(3)); + wire_nll_dataout <= nllli WHEN octal_mode = '1' ELSE (((sync_status(0) AND sync_status(1)) AND sync_status(2)) AND sync_status(3)); + wire_n0li_data <= ( wire_nl0ll36_w_lg_w_lg_q268w269w & wire_ni0i_dataout & wire_ni0i_dataout & wire_ni0i_dataout & wire_niOl_dataout & wire_niOl_dataout & wire_niOl_dataout & wire_nlii_dataout & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_n0li_sel <= ( "1" & nlOi & nllO & n0il); + n0li : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0li_data, + o => wire_n0li_o, + sel => wire_n0li_sel + ); + wire_n0ll_data <= ( wire_ni1i_dataout & wire_ni0l_dataout & wire_ni0l_dataout & wire_nl0lO34_w_lg_w_lg_q232w233w & wire_niOi_dataout & nii & wire_nl0Oi32_w_lg_w_lg_q227w228w & nii & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_n0ll_sel <= ( "1" & nlOi & nllO & n0il); + n0ll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0ll_data, + o => wire_n0ll_o, + sel => wire_n0ll_sel + ); + wire_n0lO_data <= ( wire_ni1l_dataout & wire_ni0O_dataout & wire_nl0Ol30_w_lg_w_lg_q198w199w & wire_nl0OO28_w_lg_w_lg_q195w196w & wire_niOO_dataout & wire_nl1i_dataout & wire_nl0i_dataout & nlill & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_n0lO_sel <= ( "1" & nlOi & nllO & n0il); + n0lO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0lO_data, + o => wire_n0lO_o, + sel => wire_n0lO_sel + ); + wire_n0Oi_data <= ( wire_nli1i26_w_lg_w_lg_q165w166w & wire_niii_dataout & wire_nill_dataout & "0" & wire_niOO_dataout & wire_w_lg_nliiO158w & wire_nl0l_dataout & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_n0Oi_sel <= ( "1" & nlOi & wire_nli1l24_w_lg_w_lg_q132w133w & wire_nli1O22_w_lg_w_lg_q128w129w); + n0Oi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oi_data, + o => wire_n0Oi_o, + sel => wire_n0Oi_sel + ); + wire_n0Ol_data <= ( wire_w_lg_nli0O126w & nil & nil & wire_nli0i20_w_lg_w_lg_q121w122w & wire_nl1i_dataout & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_n0Ol_sel <= ( "1" & nlOi & nllO & wire_nli0l18_w_lg_w_lg_q89w90w); + n0Ol : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Ol_data, + o => wire_n0Ol_o, + sel => wire_n0Ol_sel + ); + + END RTL; --cycloneiv_hssi_dskw_sm +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 143 mux21 336 oper_add 1 oper_decoder 1 oper_less_than 1 oper_mux 39 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_tx_sm IS + PORT + ( + curr_state : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + indv : IN STD_LOGIC; + rd_enable_sync : IN STD_LOGIC; + rxaui_s2gx_en : IN STD_LOGIC; + sm_ctl : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + sm_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + soft_reset : IN STD_LOGIC; + tx_clk : IN STD_LOGIC; + tx_ctl : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + tx_local_fault : OUT STD_LOGIC; + tx_local_fault_clr : IN STD_LOGIC; + tx_local_fault_det : OUT STD_LOGIC + ); + END cycloneiv_hssi_tx_sm; + + ARCHITECTURE RTL OF cycloneiv_hssi_tx_sm IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nil00i49 : STD_LOGIC := '0'; + SIGNAL nil00i50 : STD_LOGIC := '0'; + SIGNAL nil00l47 : STD_LOGIC := '0'; + SIGNAL nil00l48 : STD_LOGIC := '0'; + SIGNAL nili0i41 : STD_LOGIC := '0'; + SIGNAL nili0i42 : STD_LOGIC := '0'; + SIGNAL nili1i45 : STD_LOGIC := '0'; + SIGNAL nili1i46 : STD_LOGIC := '0'; + SIGNAL nili1O43 : STD_LOGIC := '0'; + SIGNAL nili1O44 : STD_LOGIC := '0'; + SIGNAL nilOll39 : STD_LOGIC := '0'; + SIGNAL nilOll40 : STD_LOGIC := '0'; + SIGNAL niO01l25 : STD_LOGIC := '0'; + SIGNAL niO01l26 : STD_LOGIC := '0'; + SIGNAL wire_niO01l26_w_lg_q89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO0il23 : STD_LOGIC := '0'; + SIGNAL niO0il24 : STD_LOGIC := '0'; + SIGNAL niO0ll21 : STD_LOGIC := '0'; + SIGNAL niO0ll22 : STD_LOGIC := '0'; + SIGNAL niO10l35 : STD_LOGIC := '0'; + SIGNAL niO10l36 : STD_LOGIC := '0'; + SIGNAL niO11i37 : STD_LOGIC := '0'; + SIGNAL niO11i38 : STD_LOGIC := '0'; + SIGNAL niO1iO33 : STD_LOGIC := '0'; + SIGNAL niO1iO34 : STD_LOGIC := '0'; + SIGNAL niO1ll31 : STD_LOGIC := '0'; + SIGNAL niO1ll32 : STD_LOGIC := '0'; + SIGNAL niO1Oi29 : STD_LOGIC := '0'; + SIGNAL niO1Oi30 : STD_LOGIC := '0'; + SIGNAL niO1OO27 : STD_LOGIC := '0'; + SIGNAL niO1OO28 : STD_LOGIC := '0'; + SIGNAL niOi0i17 : STD_LOGIC := '0'; + SIGNAL niOi0i18 : STD_LOGIC := '0'; + SIGNAL niOi1i19 : STD_LOGIC := '0'; + SIGNAL niOi1i20 : STD_LOGIC := '0'; + SIGNAL niOili15 : STD_LOGIC := '0'; + SIGNAL niOili16 : STD_LOGIC := '0'; + SIGNAL niOl0l13 : STD_LOGIC := '0'; + SIGNAL niOl0l14 : STD_LOGIC := '0'; + SIGNAL niOlli11 : STD_LOGIC := '0'; + SIGNAL niOlli12 : STD_LOGIC := '0'; + SIGNAL niOlOi10 : STD_LOGIC := '0'; + SIGNAL niOlOi9 : STD_LOGIC := '0'; + SIGNAL niOO1l7 : STD_LOGIC := '0'; + SIGNAL niOO1l8 : STD_LOGIC := '0'; + SIGNAL niOOii5 : STD_LOGIC := '0'; + SIGNAL niOOii6 : STD_LOGIC := '0'; + SIGNAL niOOll3 : STD_LOGIC := '0'; + SIGNAL niOOll4 : STD_LOGIC := '0'; + SIGNAL niOOOO1 : STD_LOGIC := '0'; + SIGNAL niOOOO2 : STD_LOGIC := '0'; + SIGNAL nlii0l : STD_LOGIC := '0'; + SIGNAL nlii0O : STD_LOGIC := '0'; + SIGNAL nliiii : STD_LOGIC := '0'; + SIGNAL nliili : STD_LOGIC := '0'; + SIGNAL nlilOl : STD_LOGIC := '0'; + SIGNAL wire_nlilOi_CLRN : STD_LOGIC; + SIGNAL wire_nlilOi_w_lg_nlilOl1869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlii0i : STD_LOGIC := '0'; + SIGNAL nlii1l : STD_LOGIC := '0'; + SIGNAL nliiil : STD_LOGIC := '0'; + SIGNAL nliiiO : STD_LOGIC := '0'; + SIGNAL nliill : STD_LOGIC := '0'; + SIGNAL nliilO : STD_LOGIC := '0'; + SIGNAL nliiOi : STD_LOGIC := '0'; + SIGNAL nliiOl : STD_LOGIC := '0'; + SIGNAL nliiOO : STD_LOGIC := '0'; + SIGNAL nlil0i : STD_LOGIC := '0'; + SIGNAL nlil0l : STD_LOGIC := '0'; + SIGNAL nlil0O : STD_LOGIC := '0'; + SIGNAL nlil1i : STD_LOGIC := '0'; + SIGNAL nlil1l : STD_LOGIC := '0'; + SIGNAL nlil1O : STD_LOGIC := '0'; + SIGNAL nlilii : STD_LOGIC := '0'; + SIGNAL nlilil : STD_LOGIC := '0'; + SIGNAL nliliO : STD_LOGIC := '0'; + SIGNAL nlilli : STD_LOGIC := '0'; + SIGNAL nlilll : STD_LOGIC := '0'; + SIGNAL nlillO : STD_LOGIC := '0'; + SIGNAL nlilOO : STD_LOGIC := '0'; + SIGNAL nliO0i : STD_LOGIC := '0'; + SIGNAL nliO0O : STD_LOGIC := '0'; + SIGNAL nliO1i : STD_LOGIC := '0'; + SIGNAL nliO1l : STD_LOGIC := '0'; + SIGNAL nliO1O : STD_LOGIC := '0'; + SIGNAL wire_nliO0l_CLRN : STD_LOGIC; + SIGNAL wire_nliO0l_w_lg_w_lg_w_lg_w1866w1868w1870w1871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_w_lg_w1866w1868w1870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_w1866w1868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w1866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_w_lg_w_lg_w_lg_nliO0O1858w1860w1862w1864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_w_lg_w_lg_nliO0O1858w1860w1862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_w_lg_nliO0O1858w1860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliill1902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliilO1900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliiOi1898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliiOl1896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliiOO1894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlil0i1886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlil0l1884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlil0O1882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlil1i1892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlil1l1890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlil1O1888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlilii1880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlilil1878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliliO1876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlilli1874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlilll1872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nlilOO1867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliO0i1859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliO0O1858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliO1i1865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliO1l1863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0l_w_lg_nliO1O1861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0l0O : STD_LOGIC := '0'; + SIGNAL n0lii : STD_LOGIC := '0'; + SIGNAL n0llO : STD_LOGIC := '0'; + SIGNAL n0lOl : STD_LOGIC := '0'; + SIGNAL n1i0i : STD_LOGIC := '0'; + SIGNAL n1i0l : STD_LOGIC := '0'; + SIGNAL n1ili : STD_LOGIC := '0'; + SIGNAL nilOi : STD_LOGIC := '0'; + SIGNAL nilOl : STD_LOGIC := '0'; + SIGNAL niOil : STD_LOGIC := '0'; + SIGNAL niOiO : STD_LOGIC := '0'; + SIGNAL niOOi : STD_LOGIC := '0'; + SIGNAL nli00i : STD_LOGIC := '0'; + SIGNAL nli10i : STD_LOGIC := '0'; + SIGNAL nli10l : STD_LOGIC := '0'; + SIGNAL nli10O : STD_LOGIC := '0'; + SIGNAL nliOii : STD_LOGIC := '0'; + SIGNAL nliOll : STD_LOGIC := '0'; + SIGNAL nliOlO : STD_LOGIC := '0'; + SIGNAL nliOO : STD_LOGIC := '0'; + SIGNAL nll0i : STD_LOGIC := '0'; + SIGNAL nll0O : STD_LOGIC := '0'; + SIGNAL nll11l : STD_LOGIC := '0'; + SIGNAL nlO01l : STD_LOGIC := '0'; + SIGNAL nlO01O : STD_LOGIC := '0'; + SIGNAL nlO0il : STD_LOGIC := '0'; + SIGNAL wire_nll0l_CLRN : STD_LOGIC; + SIGNAL wire_nll0l_PRN : STD_LOGIC; + SIGNAL wire_nll0l_w_lg_w_lg_w_lg_w_lg_nll0O365w371w1503w1504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_w_lg_w_lg_w_lg_nll0O365w371w372w373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_w_lg_w_lg_nll0O365w367w368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_w_lg_w_lg_nll0O365w371w1503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_w_lg_w_lg_nll0O365w371w372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_w_lg_nll0O365w367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_w_lg_nll0O365w371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_n0lOl378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_nilOi377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_nliOii237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_nll0i366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll0l_w_lg_nll0O365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0lil : STD_LOGIC := '0'; + SIGNAL n0liO : STD_LOGIC := '0'; + SIGNAL n0lli : STD_LOGIC := '0'; + SIGNAL n0lll : STD_LOGIC := '0'; + SIGNAL n0lOi : STD_LOGIC := '0'; + SIGNAL n1i0O : STD_LOGIC := '0'; + SIGNAL n1iii : STD_LOGIC := '0'; + SIGNAL n1iil : STD_LOGIC := '0'; + SIGNAL n1iiO : STD_LOGIC := '0'; + SIGNAL n1ill : STD_LOGIC := '0'; + SIGNAL n1ilO : STD_LOGIC := '0'; + SIGNAL niOli : STD_LOGIC := '0'; + SIGNAL nli0ll : STD_LOGIC := '0'; + SIGNAL nli0lO : STD_LOGIC := '0'; + SIGNAL nli0Oi : STD_LOGIC := '0'; + SIGNAL nli0Ol : STD_LOGIC := '0'; + SIGNAL nli0OO : STD_LOGIC := '0'; + SIGNAL nli1ii : STD_LOGIC := '0'; + SIGNAL nli1il : STD_LOGIC := '0'; + SIGNAL nlii1i : STD_LOGIC := '0'; + SIGNAL nliOil : STD_LOGIC := '0'; + SIGNAL nliOOi : STD_LOGIC := '0'; + SIGNAL nliOOl : STD_LOGIC := '0'; + SIGNAL nliOOO : STD_LOGIC := '0'; + SIGNAL nll10i : STD_LOGIC := '0'; + SIGNAL nll11i : STD_LOGIC := '0'; + SIGNAL nll11O : STD_LOGIC := '0'; + SIGNAL nll1i : STD_LOGIC := '0'; + SIGNAL nll1O : STD_LOGIC := '0'; + SIGNAL nlO00i : STD_LOGIC := '0'; + SIGNAL nlO00l : STD_LOGIC := '0'; + SIGNAL nlO00O : STD_LOGIC := '0'; + SIGNAL nlO0ii : STD_LOGIC := '0'; + SIGNAL nlO0iO : STD_LOGIC := '0'; + SIGNAL nlO0li : STD_LOGIC := '0'; + SIGNAL wire_nll1l_CLRN : STD_LOGIC; + SIGNAL wire_nll1l_w_lg_w_lg_w_lg_niOli360w361w362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1l_w_lg_niOli360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1l_w_lg_nli1il239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1l_w_lg_nll1i369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1l_w_lg_nll1O1502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nll1l_w_lg_w_lg_niOli360w361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n000i_dataout : STD_LOGIC; + SIGNAL wire_n000l_dataout : STD_LOGIC; + SIGNAL wire_n000O_dataout : STD_LOGIC; + SIGNAL wire_n001i_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001O_dataout : STD_LOGIC; + SIGNAL wire_n00ii_dataout : STD_LOGIC; + SIGNAL wire_n00il_dataout : STD_LOGIC; + SIGNAL wire_n00iO_dataout : STD_LOGIC; + SIGNAL wire_n00li_dataout : STD_LOGIC; + SIGNAL wire_n00ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n010i_dataout : STD_LOGIC; + SIGNAL wire_n010l_dataout : STD_LOGIC; + SIGNAL wire_n010O_dataout : STD_LOGIC; + SIGNAL wire_n011i_dataout : STD_LOGIC; + SIGNAL wire_n011l_dataout : STD_LOGIC; + SIGNAL wire_n011O_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01lO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0iii_dataout : STD_LOGIC; + SIGNAL wire_n0iil_dataout : STD_LOGIC; + SIGNAL wire_n0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n100i_dataout : STD_LOGIC; + SIGNAL wire_n100l_dataout : STD_LOGIC; + SIGNAL wire_n100O_dataout : STD_LOGIC; + SIGNAL wire_n101i_dataout : STD_LOGIC; + SIGNAL wire_n101l_dataout : STD_LOGIC; + SIGNAL wire_n101O_dataout : STD_LOGIC; + SIGNAL wire_n10ii_dataout : STD_LOGIC; + SIGNAL wire_n10il_dataout : STD_LOGIC; + SIGNAL wire_n10iO_dataout : STD_LOGIC; + SIGNAL wire_n10li_dataout : STD_LOGIC; + SIGNAL wire_n10ll_dataout : STD_LOGIC; + SIGNAL wire_n10lO_dataout : STD_LOGIC; + SIGNAL wire_n10Oi_dataout : STD_LOGIC; + SIGNAL wire_n10Ol_dataout : STD_LOGIC; + SIGNAL wire_n10OO_dataout : STD_LOGIC; + SIGNAL wire_n110i_dataout : STD_LOGIC; + SIGNAL wire_n110l_dataout : STD_LOGIC; + SIGNAL wire_n110O_dataout : STD_LOGIC; + SIGNAL wire_n111i_dataout : STD_LOGIC; + SIGNAL wire_n111l_dataout : STD_LOGIC; + SIGNAL wire_n111O_dataout : STD_LOGIC; + SIGNAL wire_n11ii_dataout : STD_LOGIC; + SIGNAL wire_n11il_dataout : STD_LOGIC; + SIGNAL wire_n11iO_dataout : STD_LOGIC; + SIGNAL wire_n11li_dataout : STD_LOGIC; + SIGNAL wire_n11ll_dataout : STD_LOGIC; + SIGNAL wire_n11lO_dataout : STD_LOGIC; + SIGNAL wire_n11Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Ol_dataout : STD_LOGIC; + SIGNAL wire_n11OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni00i_dataout : STD_LOGIC; + SIGNAL wire_ni00l_dataout : STD_LOGIC; + SIGNAL wire_ni00O_dataout : STD_LOGIC; + SIGNAL wire_ni01i_dataout : STD_LOGIC; + SIGNAL wire_ni01l_dataout : STD_LOGIC; + SIGNAL wire_ni01O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0il_dataout : STD_LOGIC; + SIGNAL wire_ni0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0li_dataout : STD_LOGIC; + SIGNAL wire_ni0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0OO_dataout : STD_LOGIC; + SIGNAL wire_ni10i_dataout : STD_LOGIC; + SIGNAL wire_ni10l_dataout : STD_LOGIC; + SIGNAL wire_ni10O_dataout : STD_LOGIC; + SIGNAL wire_ni11O_dataout : STD_LOGIC; + SIGNAL wire_ni1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1il_dataout : STD_LOGIC; + SIGNAL wire_ni1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1li_dataout : STD_LOGIC; + SIGNAL wire_ni1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1OO_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0O_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiil_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00i_dataout : STD_LOGIC; + SIGNAL wire_nl00l_dataout : STD_LOGIC; + SIGNAL wire_nl00O_dataout : STD_LOGIC; + SIGNAL wire_nl01l_dataout : STD_LOGIC; + SIGNAL wire_nl01O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nli01i_dataout : STD_LOGIC; + SIGNAL wire_nli01l_dataout : STD_LOGIC; + SIGNAL wire_nli01O_dataout : STD_LOGIC; + SIGNAL wire_nli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1iO_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1li_dataout : STD_LOGIC; + SIGNAL wire_nli1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1OO_dataout : STD_LOGIC; + SIGNAL wire_nliii_dataout : STD_LOGIC; + SIGNAL wire_nliil_dataout : STD_LOGIC; + SIGNAL wire_nliiO_dataout : STD_LOGIC; + SIGNAL wire_nlili_dataout : STD_LOGIC; + SIGNAL wire_nlill_dataout : STD_LOGIC; + SIGNAL wire_nlilO_dataout : STD_LOGIC; + SIGNAL wire_nliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOiO_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOli_dataout : STD_LOGIC; + SIGNAL wire_nll0il_dataout : STD_LOGIC; + SIGNAL wire_nll0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0li_dataout : STD_LOGIC; + SIGNAL wire_nll0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0OO_dataout : STD_LOGIC; + SIGNAL wire_nll10l_dataout : STD_LOGIC; + SIGNAL wire_nll10O_dataout : STD_LOGIC; + SIGNAL wire_nll1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1il_dataout : STD_LOGIC; + SIGNAL wire_nll1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1li_dataout : STD_LOGIC; + SIGNAL wire_nll1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O_dataout : STD_LOGIC; + SIGNAL wire_nlli1i_dataout : STD_LOGIC; + SIGNAL wire_nlli1l_dataout : STD_LOGIC; + SIGNAL wire_nlli1O_dataout : STD_LOGIC; + SIGNAL wire_nlliii_dataout : STD_LOGIC; + SIGNAL wire_nlliil_dataout : STD_LOGIC; + SIGNAL wire_nlliiO_dataout : STD_LOGIC; + SIGNAL wire_nllili_dataout : STD_LOGIC; + SIGNAL wire_nllill_dataout : STD_LOGIC; + SIGNAL wire_nllilO_dataout : STD_LOGIC; + SIGNAL wire_nlliOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O_dataout : STD_LOGIC; + SIGNAL wire_nlllii_dataout : STD_LOGIC; + SIGNAL wire_nlllil_dataout : STD_LOGIC; + SIGNAL wire_nllliO_dataout : STD_LOGIC; + SIGNAL wire_nlllli_dataout : STD_LOGIC; + SIGNAL wire_nlllll_dataout : STD_LOGIC; + SIGNAL wire_nllllO_dataout : STD_LOGIC; + SIGNAL wire_nlllOi_dataout : STD_LOGIC; + SIGNAL wire_nlllOl_dataout : STD_LOGIC; + SIGNAL wire_nlllOO_dataout : STD_LOGIC; + SIGNAL wire_nllO0i_dataout : STD_LOGIC; + SIGNAL wire_nllO0l_dataout : STD_LOGIC; + SIGNAL wire_nllO0O_dataout : STD_LOGIC; + SIGNAL wire_nllO1i_dataout : STD_LOGIC; + SIGNAL wire_nllO1l_dataout : STD_LOGIC; + SIGNAL wire_nllO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOii_dataout : STD_LOGIC; + SIGNAL wire_nllOil_dataout : STD_LOGIC; + SIGNAL wire_nllOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOli_dataout : STD_LOGIC; + SIGNAL wire_nllOll_dataout : STD_LOGIC; + SIGNAL wire_nllOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO11l_dataout : STD_LOGIC; + SIGNAL wire_nlO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO_dataout : STD_LOGIC; + SIGNAL wire_nli00l_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nli00l_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_nli00l_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl01i_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl01i_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1li_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1li_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1li_o : STD_LOGIC; + SIGNAL wire_n0OiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OiO_o : STD_LOGIC; + SIGNAL wire_n0OiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oli_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oli_o : STD_LOGIC; + SIGNAL wire_n0Oli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0Oll_o : STD_LOGIC; + SIGNAL wire_n0Oll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OlO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OlO_o : STD_LOGIC; + SIGNAL wire_n0OlO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOi_o : STD_LOGIC; + SIGNAL wire_n0OOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOl_o : STD_LOGIC; + SIGNAL wire_n0OOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n0OOO_o : STD_LOGIC; + SIGNAL wire_n0OOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1lii_o : STD_LOGIC; + SIGNAL wire_n1lii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1lil_o : STD_LOGIC; + SIGNAL wire_n1lil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1liO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1liO_o : STD_LOGIC; + SIGNAL wire_n1liO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lli_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1lli_o : STD_LOGIC; + SIGNAL wire_n1lli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1lll_o : STD_LOGIC; + SIGNAL wire_n1lll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1llO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1llO_o : STD_LOGIC; + SIGNAL wire_n1llO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1lOi_o : STD_LOGIC; + SIGNAL wire_n1lOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOl_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1lOl_o : STD_LOGIC; + SIGNAL wire_n1lOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_n1lOO_o : STD_LOGIC; + SIGNAL wire_n1lOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni11i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni11i_o : STD_LOGIC; + SIGNAL wire_ni11i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni11l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni11l_o : STD_LOGIC; + SIGNAL wire_ni11l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1lO_o : STD_LOGIC; + SIGNAL wire_nl1lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1Oi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1Oi_o : STD_LOGIC; + SIGNAL wire_nl1Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1Ol_o : STD_LOGIC; + SIGNAL wire_nl1Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll00i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll00i_o : STD_LOGIC; + SIGNAL wire_nll00i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll00l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll00l_o : STD_LOGIC; + SIGNAL wire_nll00l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll00O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll00O_o : STD_LOGIC; + SIGNAL wire_nll00O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll01i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll01i_o : STD_LOGIC; + SIGNAL wire_nll01i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll01l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll01l_o : STD_LOGIC; + SIGNAL wire_nll01l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll01O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll01O_o : STD_LOGIC; + SIGNAL wire_nll01O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll0ii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll0ii_o : STD_LOGIC; + SIGNAL wire_nll0ii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1Ol_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll1Ol_o : STD_LOGIC; + SIGNAL wire_nll1Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll1OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nll1OO_o : STD_LOGIC; + SIGNAL wire_nll1OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOi0l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOi0l_o : STD_LOGIC; + SIGNAL wire_nlOi0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOi0O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOi0O_o : STD_LOGIC; + SIGNAL wire_nlOi0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOiii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOiii_o : STD_LOGIC; + SIGNAL wire_nlOiii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOiil_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOiil_o : STD_LOGIC; + SIGNAL wire_nlOiil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOiiO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOiiO_o : STD_LOGIC; + SIGNAL wire_nlOiiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOili_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOili_o : STD_LOGIC; + SIGNAL wire_nlOili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOill_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOill_o : STD_LOGIC; + SIGNAL wire_nlOill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOilO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOilO_o : STD_LOGIC; + SIGNAL wire_nlOilO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOiOi_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nlOiOi_o : STD_LOGIC; + SIGNAL wire_nlOiOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_niO00O83w85w87w90w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niliOO199w201w203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nilllO168w170w172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nilOiO139w141w143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niO00O83w85w87w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rd_enable_sync357w358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_tx_ctl_range4w22w23w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niliOO199w201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nilllO168w170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nilOiO139w141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niO00O83w85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rd_enable_sync235w355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO1i223w224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0lO1500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiii208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiii226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rd_enable_sync357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range1w54w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range1w32w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range1w97w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range1w41w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range2w113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range4w151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range4w48w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range4w22w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range6w182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range6w27w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range389w1766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range945w1820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range1226w1835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range667w1797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOO206w207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0Oi238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0Ol236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nil0OO234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niliOi202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niliOl200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niliOO199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill0i191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill0l189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill0O185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill1i197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill1l195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nill1O193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillii183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilliO175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillli171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillll169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilllO168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillOi166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillOl164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nillOO162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO0i152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO0O146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO1i160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO1l158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilO1O154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOii142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOil140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOiO139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOli137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOOi132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOOl130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nilOOO128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO00i86w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO00l84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO00O83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO0ii81w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO0li76w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO0Oi71w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO0Ol69w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO0OO67w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO10i119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO11O123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niO1ii114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O53w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O60w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiil181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilO150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOl112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii65w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlil1217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliO55w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOO187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOOOi96w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rd_enable_sync235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rxaui_s2gx_en105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_ctl_range2w31w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range944w1659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range388w1592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range1225w1697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_range666w1621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_niO00O83w85w87w90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_niliOO199w201w203w204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_nilllO168w170w172w173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_nilOiO139w141w143w144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rd_enable_sync235w355w356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOO225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOO206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1i223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nil00O : STD_LOGIC; + SIGNAL nil01O : STD_LOGIC; + SIGNAL nil0ii : STD_LOGIC; + SIGNAL nil0il : STD_LOGIC; + SIGNAL nil0iO : STD_LOGIC; + SIGNAL nil0li : STD_LOGIC; + SIGNAL nil0ll : STD_LOGIC; + SIGNAL nil0lO : STD_LOGIC; + SIGNAL nil0Oi : STD_LOGIC; + SIGNAL nil0Ol : STD_LOGIC; + SIGNAL nil0OO : STD_LOGIC; + SIGNAL nili0l : STD_LOGIC; + SIGNAL nili0O : STD_LOGIC; + SIGNAL nili1l : STD_LOGIC; + SIGNAL niliii : STD_LOGIC; + SIGNAL niliil : STD_LOGIC; + SIGNAL niliiO : STD_LOGIC; + SIGNAL nilili : STD_LOGIC; + SIGNAL nilill : STD_LOGIC; + SIGNAL nililO : STD_LOGIC; + SIGNAL niliOi : STD_LOGIC; + SIGNAL niliOl : STD_LOGIC; + SIGNAL niliOO : STD_LOGIC; + SIGNAL nill0i : STD_LOGIC; + SIGNAL nill0l : STD_LOGIC; + SIGNAL nill0O : STD_LOGIC; + SIGNAL nill1i : STD_LOGIC; + SIGNAL nill1l : STD_LOGIC; + SIGNAL nill1O : STD_LOGIC; + SIGNAL nillii : STD_LOGIC; + SIGNAL nillil : STD_LOGIC; + SIGNAL nilliO : STD_LOGIC; + SIGNAL nillli : STD_LOGIC; + SIGNAL nillll : STD_LOGIC; + SIGNAL nilllO : STD_LOGIC; + SIGNAL nillOi : STD_LOGIC; + SIGNAL nillOl : STD_LOGIC; + SIGNAL nillOO : STD_LOGIC; + SIGNAL nilO0i : STD_LOGIC; + SIGNAL nilO0l : STD_LOGIC; + SIGNAL nilO0O : STD_LOGIC; + SIGNAL nilO1i : STD_LOGIC; + SIGNAL nilO1l : STD_LOGIC; + SIGNAL nilO1O : STD_LOGIC; + SIGNAL nilOii : STD_LOGIC; + SIGNAL nilOil : STD_LOGIC; + SIGNAL nilOiO : STD_LOGIC; + SIGNAL nilOli : STD_LOGIC; + SIGNAL nilOOi : STD_LOGIC; + SIGNAL nilOOl : STD_LOGIC; + SIGNAL nilOOO : STD_LOGIC; + SIGNAL niO00i : STD_LOGIC; + SIGNAL niO00l : STD_LOGIC; + SIGNAL niO00O : STD_LOGIC; + SIGNAL niO0ii : STD_LOGIC; + SIGNAL niO0li : STD_LOGIC; + SIGNAL niO0Oi : STD_LOGIC; + SIGNAL niO0Ol : STD_LOGIC; + SIGNAL niO0OO : STD_LOGIC; + SIGNAL niO10i : STD_LOGIC; + SIGNAL niO11O : STD_LOGIC; + SIGNAL niO1ii : STD_LOGIC; + SIGNAL niO1il : STD_LOGIC; + SIGNAL niOi0O : STD_LOGIC; + SIGNAL niOi1O : STD_LOGIC; + SIGNAL niOiii : STD_LOGIC; + SIGNAL niOiil : STD_LOGIC; + SIGNAL niOiiO : STD_LOGIC; + SIGNAL niOilO : STD_LOGIC; + SIGNAL niOiOi : STD_LOGIC; + SIGNAL niOiOl : STD_LOGIC; + SIGNAL niOiOO : STD_LOGIC; + SIGNAL niOl0i : STD_LOGIC; + SIGNAL niOl1i : STD_LOGIC; + SIGNAL niOl1l : STD_LOGIC; + SIGNAL niOl1O : STD_LOGIC; + SIGNAL niOlii : STD_LOGIC; + SIGNAL niOlil : STD_LOGIC; + SIGNAL niOliO : STD_LOGIC; + SIGNAL niOllO : STD_LOGIC; + SIGNAL niOlOO : STD_LOGIC; + SIGNAL niOO0i : STD_LOGIC; + SIGNAL niOO0l : STD_LOGIC; + SIGNAL niOO0O : STD_LOGIC; + SIGNAL niOO1i : STD_LOGIC; + SIGNAL niOOiO : STD_LOGIC; + SIGNAL niOOli : STD_LOGIC; + SIGNAL niOOOi : STD_LOGIC; + SIGNAL niOOOl : STD_LOGIC; + SIGNAL wire_w_tx_ctl_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_ctl_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_ctl_range4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_ctl_range6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range1226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range1225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_range666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_w_lg_w_lg_w_lg_w_lg_niO00O83w85w87w90w(0) <= wire_w_lg_w_lg_w_lg_niO00O83w85w87w(0) AND wire_niO01l26_w_lg_q89w(0); + wire_w_lg_w_lg_w_lg_niliOO199w201w203w(0) <= wire_w_lg_w_lg_niliOO199w201w(0) AND wire_w_lg_niliOi202w(0); + wire_w_lg_w_lg_w_lg_nilllO168w170w172w(0) <= wire_w_lg_w_lg_nilllO168w170w(0) AND wire_w_lg_nillli171w(0); + wire_w_lg_w_lg_w_lg_nilOiO139w141w143w(0) <= wire_w_lg_w_lg_nilOiO139w141w(0) AND wire_w_lg_nilOii142w(0); + wire_w_lg_w_lg_w_lg_niO00O83w85w87w(0) <= wire_w_lg_w_lg_niO00O83w85w(0) AND wire_w_lg_niO00i86w(0); + wire_w_lg_w_lg_rd_enable_sync357w358w(0) <= wire_w_lg_rd_enable_sync357w(0) AND nil0lO; + wire_w_lg_w_lg_w_tx_ctl_range4w22w23w(0) <= wire_w_lg_w_tx_ctl_range4w22w(0) AND niOO0i; + wire_w_lg_w_lg_niliOO199w201w(0) <= wire_w_lg_niliOO199w(0) AND wire_w_lg_niliOl200w(0); + wire_w_lg_w_lg_nilllO168w170w(0) <= wire_w_lg_nilllO168w(0) AND wire_w_lg_nillll169w(0); + wire_w_lg_w_lg_nilOiO139w141w(0) <= wire_w_lg_nilOiO139w(0) AND wire_w_lg_nilOil140w(0); + wire_w_lg_w_lg_niO00O83w85w(0) <= wire_w_lg_niO00O83w(0) AND wire_w_lg_niO00l84w(0); + wire_w_lg_w_lg_rd_enable_sync235w355w(0) <= wire_w_lg_rd_enable_sync235w(0) AND nil0iO; + wire_w_lg_w_lg_niOO1i223w224w(0) <= wire_w_lg_niOO1i223w(0) AND rxaui_s2gx_en; + wire_w_lg_nil0lO1500w(0) <= nil0lO AND wire_w_lg_nil0Oi238w(0); + wire_w_lg_niOiii208w(0) <= niOiii AND wire_w_lg_w_lg_niOiOO206w207w(0); + wire_w_lg_niOiii226w(0) <= niOiii AND wire_w_lg_niOiOO225w(0); + wire_w_lg_niOiiO176w(0) <= niOiiO AND wire_w_lg_nilliO175w(0); + wire_w_lg_niOiOi147w(0) <= niOiOi AND wire_w_lg_nilO0O146w(0); + wire_w_lg_rd_enable_sync357w(0) <= rd_enable_sync AND nil0iO; + wire_w_lg_w_tx_ctl_range1w54w(0) <= wire_w_tx_ctl_range1w(0) AND wire_w_lg_niOi0O53w(0); + wire_w_lg_w_tx_ctl_range1w32w(0) <= wire_w_tx_ctl_range1w(0) AND wire_w_lg_w_tx_ctl_range2w31w(0); + wire_w_lg_w_tx_ctl_range1w97w(0) <= wire_w_tx_ctl_range1w(0) AND niOi0O; + wire_w_lg_w_tx_ctl_range1w41w(0) <= wire_w_tx_ctl_range1w(0) AND niOlii; + wire_w_lg_w_tx_ctl_range2w113w(0) <= wire_w_tx_ctl_range2w(0) AND wire_w_lg_niOiOl112w(0); + wire_w_lg_w_tx_ctl_range4w151w(0) <= wire_w_tx_ctl_range4w(0) AND wire_w_lg_niOilO150w(0); + wire_w_lg_w_tx_ctl_range4w48w(0) <= wire_w_tx_ctl_range4w(0) AND niOilO; + wire_w_lg_w_tx_ctl_range4w22w(0) <= wire_w_tx_ctl_range4w(0) AND wire_w_tx_ctl_range6w(0); + wire_w_lg_w_tx_ctl_range6w182w(0) <= wire_w_tx_ctl_range6w(0) AND wire_w_lg_niOiil181w(0); + wire_w_lg_w_tx_ctl_range6w27w(0) <= wire_w_tx_ctl_range6w(0) AND niOlOO; + wire_w_lg_w_tx_data_range389w1766w(0) <= wire_w_tx_data_range389w(0) AND wire_w_lg_w_tx_data_range388w1592w(0); + wire_w_lg_w_tx_data_range945w1820w(0) <= wire_w_tx_data_range945w(0) AND wire_w_lg_w_tx_data_range944w1659w(0); + wire_w_lg_w_tx_data_range1226w1835w(0) <= wire_w_tx_data_range1226w(0) AND wire_w_lg_w_tx_data_range1225w1697w(0); + wire_w_lg_w_tx_data_range667w1797w(0) <= wire_w_tx_data_range667w(0) AND wire_w_lg_w_tx_data_range666w1621w(0); + wire_w_lg_w_lg_niOiOO206w207w(0) <= NOT wire_w_lg_niOiOO206w(0); + wire_w_lg_nil0Oi238w(0) <= NOT nil0Oi; + wire_w_lg_nil0Ol236w(0) <= NOT nil0Ol; + wire_w_lg_nil0OO234w(0) <= NOT nil0OO; + wire_w_lg_niliOi202w(0) <= NOT niliOi; + wire_w_lg_niliOl200w(0) <= NOT niliOl; + wire_w_lg_niliOO199w(0) <= NOT niliOO; + wire_w_lg_nill0i191w(0) <= NOT nill0i; + wire_w_lg_nill0l189w(0) <= NOT nill0l; + wire_w_lg_nill0O185w(0) <= NOT nill0O; + wire_w_lg_nill1i197w(0) <= NOT nill1i; + wire_w_lg_nill1l195w(0) <= NOT nill1l; + wire_w_lg_nill1O193w(0) <= NOT nill1O; + wire_w_lg_nillii183w(0) <= NOT nillii; + wire_w_lg_nilliO175w(0) <= NOT nilliO; + wire_w_lg_nillli171w(0) <= NOT nillli; + wire_w_lg_nillll169w(0) <= NOT nillll; + wire_w_lg_nilllO168w(0) <= NOT nilllO; + wire_w_lg_nillOi166w(0) <= NOT nillOi; + wire_w_lg_nillOl164w(0) <= NOT nillOl; + wire_w_lg_nillOO162w(0) <= NOT nillOO; + wire_w_lg_nilO0i152w(0) <= NOT nilO0i; + wire_w_lg_nilO0O146w(0) <= NOT nilO0O; + wire_w_lg_nilO1i160w(0) <= NOT nilO1i; + wire_w_lg_nilO1l158w(0) <= NOT nilO1l; + wire_w_lg_nilO1O154w(0) <= NOT nilO1O; + wire_w_lg_nilOii142w(0) <= NOT nilOii; + wire_w_lg_nilOil140w(0) <= NOT nilOil; + wire_w_lg_nilOiO139w(0) <= NOT nilOiO; + wire_w_lg_nilOli137w(0) <= NOT nilOli; + wire_w_lg_nilOOi132w(0) <= NOT nilOOi; + wire_w_lg_nilOOl130w(0) <= NOT nilOOl; + wire_w_lg_nilOOO128w(0) <= NOT nilOOO; + wire_w_lg_niO00i86w(0) <= NOT niO00i; + wire_w_lg_niO00l84w(0) <= NOT niO00l; + wire_w_lg_niO00O83w(0) <= NOT niO00O; + wire_w_lg_niO0ii81w(0) <= NOT niO0ii; + wire_w_lg_niO0li76w(0) <= NOT niO0li; + wire_w_lg_niO0Oi71w(0) <= NOT niO0Oi; + wire_w_lg_niO0Ol69w(0) <= NOT niO0Ol; + wire_w_lg_niO0OO67w(0) <= NOT niO0OO; + wire_w_lg_niO10i119w(0) <= NOT niO10i; + wire_w_lg_niO11O123w(0) <= NOT niO11O; + wire_w_lg_niO1ii114w(0) <= NOT niO1ii; + wire_w_lg_niOi0O53w(0) <= NOT niOi0O; + wire_w_lg_niOi1O60w(0) <= NOT niOi1O; + wire_w_lg_niOiil181w(0) <= NOT niOiil; + wire_w_lg_niOilO150w(0) <= NOT niOilO; + wire_w_lg_niOiOl112w(0) <= NOT niOiOl; + wire_w_lg_niOl1i156w(0) <= NOT niOl1i; + wire_w_lg_niOl1O121w(0) <= NOT niOl1O; + wire_w_lg_niOlii65w(0) <= NOT niOlii; + wire_w_lg_niOlil1217w(0) <= NOT niOlil; + wire_w_lg_niOliO55w(0) <= NOT niOliO; + wire_w_lg_niOlOO187w(0) <= NOT niOlOO; + wire_w_lg_niOOOi96w(0) <= NOT niOOOi; + wire_w_lg_rd_enable_sync235w(0) <= NOT rd_enable_sync; + wire_w_lg_rxaui_s2gx_en105w(0) <= NOT rxaui_s2gx_en; + wire_w_lg_soft_reset230w(0) <= NOT soft_reset; + wire_w_lg_w_tx_ctl_range2w31w(0) <= NOT wire_w_tx_ctl_range2w(0); + wire_w_lg_w_tx_data_range944w1659w(0) <= NOT wire_w_tx_data_range944w(0); + wire_w_lg_w_tx_data_range388w1592w(0) <= NOT wire_w_tx_data_range388w(0); + wire_w_lg_w_tx_data_range1225w1697w(0) <= NOT wire_w_tx_data_range1225w(0); + wire_w_lg_w_tx_data_range666w1621w(0) <= NOT wire_w_tx_data_range666w(0); + wire_w_lg_w_lg_w_lg_w_lg_w_lg_niO00O83w85w87w90w91w(0) <= wire_w_lg_w_lg_w_lg_w_lg_niO00O83w85w87w90w(0) OR rxaui_s2gx_en; + wire_w_lg_w_lg_w_lg_w_lg_niliOO199w201w203w204w(0) <= wire_w_lg_w_lg_w_lg_niliOO199w201w203w(0) OR rxaui_s2gx_en; + wire_w_lg_w_lg_w_lg_w_lg_nilllO168w170w172w173w(0) <= wire_w_lg_w_lg_w_lg_nilllO168w170w172w(0) OR rxaui_s2gx_en; + wire_w_lg_w_lg_w_lg_w_lg_nilOiO139w141w143w144w(0) <= wire_w_lg_w_lg_w_lg_nilOiO139w141w143w(0) OR rxaui_s2gx_en; + wire_w_lg_w_lg_w_lg_rd_enable_sync235w355w356w(0) <= wire_w_lg_w_lg_rd_enable_sync235w355w(0) OR wire_nl1li_o; + wire_w_lg_niOiOO225w(0) <= niOiOO OR niliii; + wire_w_lg_niOiOO206w(0) <= niOiOO OR nilliO; + wire_w_lg_niOO1i223w(0) <= niOO1i OR niliil; + curr_state <= ( nll0O & nll0i & nll1O & nll1i); + nil00O <= (nil0ii AND (wire_nll0l_w_lg_nilOi377w(0) AND wire_nll0l_w_lg_n0lOl378w(0))); + nil01O <= (wire_w_lg_nil0lO1500w(0) AND (((wire_nll0l_w_lg_w_lg_w_lg_nll0O365w371w372w(0) AND wire_nll1l_w_lg_nll1i369w(0)) OR wire_nll0l_w_lg_w_lg_w_lg_w_lg_nll0O365w371w1503w1504w(0)) OR (niOli AND nil0ll))); + nil0ii <= ((((((((((((((((wire_nliO0l_w_lg_w_lg_w_lg_w1866w1868w1870w1871w(0) AND wire_nliO0l_w_lg_nlilll1872w(0)) AND wire_nliO0l_w_lg_nlilli1874w(0)) AND wire_nliO0l_w_lg_nliliO1876w(0)) AND wire_nliO0l_w_lg_nlilil1878w(0)) AND wire_nliO0l_w_lg_nlilii1880w(0)) AND wire_nliO0l_w_lg_nlil0O1882w(0)) AND wire_nliO0l_w_lg_nlil0l1884w(0)) AND wire_nliO0l_w_lg_nlil0i1886w(0)) AND wire_nliO0l_w_lg_nlil1O1888w(0)) AND wire_nliO0l_w_lg_nlil1l1890w(0)) AND wire_nliO0l_w_lg_nlil1i1892w(0)) AND wire_nliO0l_w_lg_nliiOO1894w(0)) AND wire_nliO0l_w_lg_nliiOl1896w(0)) AND wire_nliO0l_w_lg_nliiOi1898w(0)) AND wire_nliO0l_w_lg_nliilO1900w(0)) AND wire_nliO0l_w_lg_nliill1902w(0)); + nil0il <= ((((wire_nll0l_w_lg_w_lg_w_lg_nll0O365w367w368w(0) AND wire_nll1l_w_lg_nll1i369w(0)) OR wire_nll0l_w_lg_w_lg_w_lg_w_lg_nll0O365w371w372w373w(0)) AND nil0lO) AND nliOii); + nil0iO <= (wire_nll0l_w_lg_w_lg_w_lg_nll0O365w367w368w(0) AND nll1i); + nil0li <= (nil0lO AND nil0ll); + nil0ll <= ((wire_nll0l_w_lg_w_lg_nll0O365w367w(0) AND wire_nll1l_w_lg_nll1O1502w(0)) AND nll1i); + nil0lO <= (niOOOi OR niOlil); + nil0Oi <= ((((nli00i OR nli1ii) OR nli10O) OR nli10l) OR nli10i); + nil0Ol <= (niOli AND wire_w_lg_nil0Oi238w(0)); + nil0OO <= (wire_w_lg_niOOOi96w(0) AND wire_w_lg_niOlil1217w(0)); + nili0l <= (wire_w_lg_w_lg_niOO1i223w224w(0) OR (wire_w_lg_niOiii226w(0) AND wire_w_lg_rxaui_s2gx_en105w(0))); + nili0O <= ((niliil AND rxaui_s2gx_en) OR ((niOiiO AND niliii) AND wire_w_lg_rxaui_s2gx_en105w(0))); + nili1l <= '1'; + niliii <= (niOl0i OR niOl1l); + niliil <= (niOOiO OR niOO0l); + niliiO <= (nilill OR ((niOl0i AND niOiOi) AND wire_w_lg_rxaui_s2gx_en105w(0))); + nilili <= ((niOl0i AND wire_w_lg_rxaui_s2gx_en105w(0)) OR nilill); + nilill <= (niOOiO AND rxaui_s2gx_en); + nililO <= ((((((((((wire_w_lg_w_tx_ctl_range6w182w(0) AND wire_w_lg_nillii183w(0)) AND wire_w_lg_nill0O185w(0)) AND wire_w_lg_niOlOO187w(0)) AND wire_w_lg_nill0l189w(0)) AND wire_w_lg_nill0i191w(0)) AND wire_w_lg_nill1O193w(0)) AND wire_w_lg_nill1l195w(0)) AND wire_w_lg_nill1i197w(0)) AND wire_w_lg_w_lg_w_lg_w_lg_niliOO199w201w203w204w(0)) OR (wire_w_lg_niOiii208w(0) AND wire_w_lg_rxaui_s2gx_en105w(0))); + niliOi <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND tx_data(29)) AND (NOT tx_data(30))) AND tx_data(31)); + niliOl <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND tx_data(29)) AND tx_data(30)) AND (NOT tx_data(31))); + niliOO <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND (NOT tx_data(29))) AND (NOT tx_data(30))) AND (NOT tx_data(31))); + nill0i <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND (NOT tx_data(29))) AND tx_data(30)) AND (NOT tx_data(31))); + nill0l <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND tx_data(29)) AND (NOT tx_data(30))) AND (NOT tx_data(31))); + nill0O <= (((((((tx_data(24) AND tx_data(25)) AND (NOT tx_data(26))) AND tx_data(27)) AND tx_data(28)) AND tx_data(29)) AND tx_data(30)) AND tx_data(31)); + nill1i <= (((((((tx_data(24) AND tx_data(25)) AND tx_data(26)) AND (NOT tx_data(27))) AND tx_data(28)) AND tx_data(29)) AND tx_data(30)) AND tx_data(31)); + nill1l <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND tx_data(29)) AND tx_data(30)) AND tx_data(31)); + nill1O <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND (NOT tx_data(29))) AND tx_data(30)) AND tx_data(31)); + nillii <= ((((((((NOT tx_data(24)) AND wire_w_lg_w_tx_data_range1225w1697w(0)) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND (NOT tx_data(29))) AND (NOT tx_data(30))) AND tx_data(31)); + nillil <= ((((((((((wire_w_lg_w_tx_ctl_range4w151w(0) AND wire_w_lg_nilO0i152w(0)) AND wire_w_lg_nilO1O154w(0)) AND wire_w_lg_niOl1i156w(0)) AND wire_w_lg_nilO1l158w(0)) AND wire_w_lg_nilO1i160w(0)) AND wire_w_lg_nillOO162w(0)) AND wire_w_lg_nillOl164w(0)) AND wire_w_lg_nillOi166w(0)) AND wire_w_lg_w_lg_w_lg_w_lg_nilllO168w170w172w173w(0)) OR (wire_w_lg_niOiiO176w(0) AND wire_w_lg_rxaui_s2gx_en105w(0))); + nilliO <= (niOl1l OR nilO0O); + nillli <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND tx_data(21)) AND (NOT tx_data(22))) AND tx_data(23)); + nillll <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND tx_data(21)) AND tx_data(22)) AND (NOT tx_data(23))); + nilllO <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND (NOT tx_data(21))) AND (NOT tx_data(22))) AND (NOT tx_data(23))); + nillOi <= (((((((tx_data(16) AND tx_data(17)) AND tx_data(18)) AND (NOT tx_data(19))) AND tx_data(20)) AND tx_data(21)) AND tx_data(22)) AND tx_data(23)); + nillOl <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND tx_data(21)) AND tx_data(22)) AND tx_data(23)); + nillOO <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND (NOT tx_data(21))) AND tx_data(22)) AND tx_data(23)); + nilO0i <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND (NOT tx_data(21))) AND (NOT tx_data(22))) AND tx_data(23)); + nilO0l <= (((((((((((((wire_w_lg_w_tx_ctl_range2w113w(0) AND wire_w_lg_niO1ii114w(0)) AND (niO10l36 XOR niO10l35)) AND wire_w_lg_niO10i119w(0)) AND wire_w_lg_niOl1O121w(0)) AND wire_w_lg_niO11O123w(0)) AND (niO11i38 XOR niO11i37)) AND wire_w_lg_nilOOO128w(0)) AND wire_w_lg_nilOOl130w(0)) AND wire_w_lg_nilOOi132w(0)) AND (nilOll40 XOR nilOll39)) AND wire_w_lg_nilOli137w(0)) AND wire_w_lg_w_lg_w_lg_w_lg_nilOiO139w141w143w144w(0)) OR (wire_w_lg_niOiOi147w(0) AND wire_w_lg_rxaui_s2gx_en105w(0))); + nilO0O <= (niOOOi OR niOl0i); + nilO1i <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND (NOT tx_data(21))) AND tx_data(22)) AND (NOT tx_data(23))); + nilO1l <= ((((((((NOT tx_data(16)) AND wire_w_lg_w_tx_data_range944w1659w(0)) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND tx_data(21)) AND (NOT tx_data(22))) AND (NOT tx_data(23))); + nilO1O <= (((((((tx_data(16) AND tx_data(17)) AND (NOT tx_data(18))) AND tx_data(19)) AND tx_data(20)) AND tx_data(21)) AND tx_data(22)) AND tx_data(23)); + nilOii <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND tx_data(13)) AND (NOT tx_data(14))) AND tx_data(15)); + nilOil <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND tx_data(13)) AND tx_data(14)) AND (NOT tx_data(15))); + nilOiO <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND (NOT tx_data(13))) AND (NOT tx_data(14))) AND (NOT tx_data(15))); + nilOli <= (((((((tx_data(8) AND tx_data(9)) AND tx_data(10)) AND (NOT tx_data(11))) AND tx_data(12)) AND tx_data(13)) AND tx_data(14)) AND tx_data(15)); + nilOOi <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND tx_data(13)) AND tx_data(14)) AND tx_data(15)); + nilOOl <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND (NOT tx_data(13))) AND tx_data(14)) AND tx_data(15)); + nilOOO <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND (NOT tx_data(13))) AND tx_data(14)) AND (NOT tx_data(15))); + niO00i <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND tx_data(5)) AND (NOT tx_data(6))) AND tx_data(7)); + niO00l <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND tx_data(5)) AND tx_data(6)) AND (NOT tx_data(7))); + niO00O <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND (NOT tx_data(5))) AND (NOT tx_data(6))) AND (NOT tx_data(7))); + niO0ii <= (((((((tx_data(0) AND tx_data(1)) AND tx_data(2)) AND (NOT tx_data(3))) AND tx_data(4)) AND tx_data(5)) AND tx_data(6)) AND tx_data(7)); + niO0li <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND tx_data(5)) AND tx_data(6)) AND tx_data(7)); + niO0Oi <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND (NOT tx_data(5))) AND tx_data(6)) AND tx_data(7)); + niO0Ol <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND (NOT tx_data(5))) AND tx_data(6)) AND (NOT tx_data(7))); + niO0OO <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND tx_data(5)) AND (NOT tx_data(6))) AND (NOT tx_data(7))); + niO10i <= (((((((tx_data(8) AND tx_data(9)) AND (NOT tx_data(10))) AND tx_data(11)) AND tx_data(12)) AND tx_data(13)) AND tx_data(14)) AND tx_data(15)); + niO11O <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND tx_data(13)) AND (NOT tx_data(14))) AND (NOT tx_data(15))); + niO1ii <= ((((((((NOT tx_data(8)) AND wire_w_lg_w_tx_data_range666w1621w(0)) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND (NOT tx_data(13))) AND (NOT tx_data(14))) AND tx_data(15)); + niO1il <= ((((((((((((((((wire_w_lg_w_tx_ctl_range1w54w(0) AND wire_w_lg_niOliO55w(0)) AND (niOi0i18 XOR niOi0i17)) AND wire_w_lg_niOi1O60w(0)) AND (niOi1i20 XOR niOi1i19)) AND wire_w_lg_niOlii65w(0)) AND wire_w_lg_niO0OO67w(0)) AND wire_w_lg_niO0Ol69w(0)) AND wire_w_lg_niO0Oi71w(0)) AND (niO0ll22 XOR niO0ll21)) AND wire_w_lg_niO0li76w(0)) AND (niO0il24 XOR niO0il23)) AND wire_w_lg_niO0ii81w(0)) AND wire_w_lg_w_lg_w_lg_w_lg_w_lg_niO00O83w85w87w90w91w(0)) AND (niO1OO28 XOR niO1OO27)) OR (((wire_w_lg_niOOOi96w(0) AND (wire_w_lg_w_tx_ctl_range1w97w(0) AND (niO1Oi30 XOR niO1Oi29))) AND (niO1ll32 XOR niO1ll31)) AND wire_w_lg_rxaui_s2gx_en105w(0))) OR (NOT (niO1iO34 XOR niO1iO33))); + niOi0O <= (((((((tx_data(0) AND tx_data(1)) AND tx_data(2)) AND (NOT tx_data(3))) AND (NOT tx_data(4))) AND (NOT tx_data(5))) AND (NOT tx_data(6))) AND (NOT tx_data(7))); + niOi1O <= (((((((tx_data(0) AND tx_data(1)) AND (NOT tx_data(2))) AND tx_data(3)) AND tx_data(4)) AND tx_data(5)) AND tx_data(6)) AND tx_data(7)); + niOiii <= (tx_ctl(3) AND niOiil); + niOiil <= (((((((tx_data(24) AND tx_data(25)) AND tx_data(26)) AND (NOT tx_data(27))) AND (NOT tx_data(28))) AND (NOT tx_data(29))) AND (NOT tx_data(30))) AND (NOT tx_data(31))); + niOiiO <= (wire_w_lg_w_tx_ctl_range4w48w(0) AND (niOili16 XOR niOili15)); + niOilO <= (((((((tx_data(16) AND tx_data(17)) AND tx_data(18)) AND (NOT tx_data(19))) AND (NOT tx_data(20))) AND (NOT tx_data(21))) AND (NOT tx_data(22))) AND (NOT tx_data(23))); + niOiOi <= (tx_ctl(1) AND niOiOl); + niOiOl <= (((((((tx_data(8) AND tx_data(9)) AND tx_data(10)) AND (NOT tx_data(11))) AND (NOT tx_data(12))) AND (NOT tx_data(13))) AND (NOT tx_data(14))) AND (NOT tx_data(15))); + niOiOO <= (tx_ctl(2) AND niOl1i); + niOl0i <= (wire_w_lg_w_tx_ctl_range1w41w(0) AND (niOl0l14 XOR niOl0l13)); + niOl1i <= ((((((wire_w_lg_w_tx_data_range945w1820w(0) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND tx_data(21)) AND tx_data(22)) AND tx_data(23)); + niOl1l <= (tx_ctl(1) AND niOl1O); + niOl1O <= ((((((wire_w_lg_w_tx_data_range667w1797w(0) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND tx_data(13)) AND tx_data(14)) AND tx_data(15)); + niOlii <= ((((((wire_w_lg_w_tx_data_range389w1766w(0) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND tx_data(5)) AND tx_data(6)) AND tx_data(7)); + niOlil <= ((((wire_w_lg_w_tx_ctl_range1w32w(0) AND (NOT tx_ctl(2))) AND (NOT tx_ctl(3))) AND (niOlli12 XOR niOlli11)) AND niOliO); + niOliO <= ((((((((NOT tx_data(0)) AND wire_w_lg_w_tx_data_range388w1592w(0)) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND (NOT tx_data(5))) AND (NOT tx_data(6))) AND tx_data(7)); + niOllO <= (wire_w_lg_w_tx_ctl_range6w27w(0) AND (niOlOi10 XOR niOlOi9)); + niOlOO <= ((((((wire_w_lg_w_tx_data_range1226w1835w(0) AND tx_data(26)) AND tx_data(27)) AND tx_data(28)) AND tx_data(29)) AND tx_data(30)) AND tx_data(31)); + niOO0i <= ((((((((((((((wire_w_lg_w_tx_data_range945w1820w(0) AND tx_data(18)) AND tx_data(19)) AND tx_data(20)) AND tx_data(21)) AND tx_data(22)) AND tx_data(23)) AND tx_data(24)) AND tx_data(25)) AND tx_data(26)) AND (NOT tx_data(27))) AND (NOT tx_data(28))) AND (NOT tx_data(29))) AND (NOT tx_data(30))) AND (NOT tx_data(31))); + niOO0l <= ((((tx_ctl(1) AND tx_ctl(2)) AND tx_ctl(3)) AND (niOOii6 XOR niOOii5)) AND niOO0O); + niOO0O <= ((((((((((((((((((((((wire_w_lg_w_tx_data_range667w1797w(0) AND tx_data(10)) AND tx_data(11)) AND tx_data(12)) AND tx_data(13)) AND tx_data(14)) AND tx_data(15)) AND tx_data(16)) AND tx_data(17)) AND tx_data(18)) AND (NOT tx_data(19))) AND (NOT tx_data(20))) AND (NOT tx_data(21))) AND (NOT tx_data(22))) AND (NOT tx_data(23))) AND tx_data(24)) AND tx_data(25)) AND tx_data(26)) AND (NOT tx_data(27))) AND (NOT tx_data(28))) AND (NOT tx_data(29))) AND (NOT tx_data(30))) AND (NOT tx_data(31))); + niOO1i <= (wire_w_lg_w_lg_w_tx_ctl_range4w22w23w(0) AND (niOO1l8 XOR niOO1l7)); + niOOiO <= (((((tx_ctl(0) AND tx_ctl(1)) AND tx_ctl(2)) AND tx_ctl(3)) AND (niOOll4 XOR niOOll3)) AND niOOli); + niOOli <= ((((((((((((((((((((((((((((((wire_w_lg_w_tx_data_range389w1766w(0) AND tx_data(2)) AND tx_data(3)) AND tx_data(4)) AND tx_data(5)) AND tx_data(6)) AND tx_data(7)) AND tx_data(8)) AND tx_data(9)) AND tx_data(10)) AND (NOT tx_data(11))) AND (NOT tx_data(12))) AND (NOT tx_data(13))) AND (NOT tx_data(14))) AND (NOT tx_data(15))) AND tx_data(16)) AND tx_data(17)) AND tx_data(18)) AND (NOT tx_data(19))) AND (NOT tx_data(20))) AND (NOT tx_data(21))) AND (NOT tx_data(22))) AND (NOT tx_data(23))) AND tx_data(24)) AND tx_data(25)) AND tx_data(26)) AND (NOT tx_data(27))) AND (NOT tx_data(28))) AND (NOT tx_data(29))) AND (NOT tx_data(30))) AND (NOT tx_data(31))); + niOOOi <= (((((tx_ctl(0) AND tx_ctl(1)) AND tx_ctl(2)) AND tx_ctl(3)) AND (niOOOO2 XOR niOOOO1)) AND niOOOl); + niOOOl <= (((((((((((((((((((((((((((((((tx_data(0) AND tx_data(1)) AND tx_data(2)) AND (NOT tx_data(3))) AND (NOT tx_data(4))) AND (NOT tx_data(5))) AND (NOT tx_data(6))) AND (NOT tx_data(7))) AND tx_data(8)) AND tx_data(9)) AND tx_data(10)) AND (NOT tx_data(11))) AND (NOT tx_data(12))) AND (NOT tx_data(13))) AND (NOT tx_data(14))) AND (NOT tx_data(15))) AND tx_data(16)) AND tx_data(17)) AND tx_data(18)) AND (NOT tx_data(19))) AND (NOT tx_data(20))) AND (NOT tx_data(21))) AND (NOT tx_data(22))) AND (NOT tx_data(23))) AND tx_data(24)) AND tx_data(25)) AND tx_data(26)) AND (NOT tx_data(27))) AND (NOT tx_data(28))) AND (NOT tx_data(29))) AND (NOT tx_data(30))) AND (NOT tx_data(31))); + sm_ctl <= ( nliOil & nll10i & nlO0li & n1ilO); + sm_data <= ( nll11O & nll11l & nll11i & nliOOO & nliOOl & nliOOi & nliOlO & nliOll & nlO0iO & nlO0il & nlO0ii & nlO00O & nlO00l & nlO00i & nlO01O & nlO01l & n1ill & n1ili & n1iiO & n1iil & n1iii & n1i0O & n1i0l & n1i0i & n0lOi & n0llO & n0lll & n0lli & n0liO & n0lil & n0lii & n0l0O); + tx_local_fault <= niOiO; + tx_local_fault_det <= n0lOl; + wire_w_tx_ctl_range1w(0) <= tx_ctl(0); + wire_w_tx_ctl_range2w(0) <= tx_ctl(1); + wire_w_tx_ctl_range4w(0) <= tx_ctl(2); + wire_w_tx_ctl_range6w(0) <= tx_ctl(3); + wire_w_tx_data_range389w(0) <= tx_data(0); + wire_w_tx_data_range945w(0) <= tx_data(16); + wire_w_tx_data_range944w(0) <= tx_data(17); + wire_w_tx_data_range388w(0) <= tx_data(1); + wire_w_tx_data_range1226w(0) <= tx_data(24); + wire_w_tx_data_range1225w(0) <= tx_data(25); + wire_w_tx_data_range667w(0) <= tx_data(8); + wire_w_tx_data_range666w(0) <= tx_data(9); + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nil00i49 <= nil00i50; + END IF; + if (now = 0 ns) then + nil00i49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nil00i50 <= nil00i49; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nil00l47 <= nil00l48; + END IF; + if (now = 0 ns) then + nil00l47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nil00l48 <= nil00l47; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nili0i41 <= nili0i42; + END IF; + if (now = 0 ns) then + nili0i41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nili0i42 <= nili0i41; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nili1i45 <= nili1i46; + END IF; + if (now = 0 ns) then + nili1i45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nili1i46 <= nili1i45; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nili1O43 <= nili1O44; + END IF; + if (now = 0 ns) then + nili1O43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nili1O44 <= nili1O43; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nilOll39 <= nilOll40; + END IF; + if (now = 0 ns) then + nilOll39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN nilOll40 <= nilOll39; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO01l25 <= niO01l26; + END IF; + if (now = 0 ns) then + niO01l25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO01l26 <= niO01l25; + END IF; + END PROCESS; + wire_niO01l26_w_lg_q89w(0) <= niO01l26 XOR niO01l25; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO0il23 <= niO0il24; + END IF; + if (now = 0 ns) then + niO0il23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO0il24 <= niO0il23; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO0ll21 <= niO0ll22; + END IF; + if (now = 0 ns) then + niO0ll21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO0ll22 <= niO0ll21; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO10l35 <= niO10l36; + END IF; + if (now = 0 ns) then + niO10l35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO10l36 <= niO10l35; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO11i37 <= niO11i38; + END IF; + if (now = 0 ns) then + niO11i37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO11i38 <= niO11i37; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1iO33 <= niO1iO34; + END IF; + if (now = 0 ns) then + niO1iO33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1iO34 <= niO1iO33; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1ll31 <= niO1ll32; + END IF; + if (now = 0 ns) then + niO1ll31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1ll32 <= niO1ll31; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1Oi29 <= niO1Oi30; + END IF; + if (now = 0 ns) then + niO1Oi29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1Oi30 <= niO1Oi29; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1OO27 <= niO1OO28; + END IF; + if (now = 0 ns) then + niO1OO27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niO1OO28 <= niO1OO27; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOi0i17 <= niOi0i18; + END IF; + if (now = 0 ns) then + niOi0i17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOi0i18 <= niOi0i17; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOi1i19 <= niOi1i20; + END IF; + if (now = 0 ns) then + niOi1i19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOi1i20 <= niOi1i19; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOili15 <= niOili16; + END IF; + if (now = 0 ns) then + niOili15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOili16 <= niOili15; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOl0l13 <= niOl0l14; + END IF; + if (now = 0 ns) then + niOl0l13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOl0l14 <= niOl0l13; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOlli11 <= niOlli12; + END IF; + if (now = 0 ns) then + niOlli11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOlli12 <= niOlli11; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOlOi10 <= niOlOi9; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOlOi9 <= niOlOi10; + END IF; + if (now = 0 ns) then + niOlOi9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOO1l7 <= niOO1l8; + END IF; + if (now = 0 ns) then + niOO1l7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOO1l8 <= niOO1l7; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOOii5 <= niOOii6; + END IF; + if (now = 0 ns) then + niOOii5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOOii6 <= niOOii5; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOOll3 <= niOOll4; + END IF; + if (now = 0 ns) then + niOOll3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOOll4 <= niOOll3; + END IF; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOOOO1 <= niOOOO2; + END IF; + if (now = 0 ns) then + niOOOO1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (tx_clk) + BEGIN + IF (tx_clk = '1' AND tx_clk'event) THEN niOOOO2 <= niOOOO1; + END IF; + END PROCESS; + PROCESS (tx_clk, soft_reset, wire_nlilOi_CLRN) + BEGIN + IF (soft_reset = '1') THEN + nlii0l <= '1'; + nlii0O <= '1'; + nliiii <= '1'; + nliili <= '1'; + nlilOl <= '1'; + ELSIF (wire_nlilOi_CLRN = '0') THEN + nlii0l <= '0'; + nlii0O <= '0'; + nliiii <= '0'; + nliili <= '0'; + nlilOl <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (niOlil = '1') THEN + nlii0l <= tx_data(2); + nlii0O <= tx_data(3); + nliiii <= tx_data(4); + nliili <= tx_data(7); + nlilOl <= tx_data(25); + END IF; + END IF; + if (now = 0 ns) then + nlii0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlii0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliili <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlilOl <= '1' after 1 ps; + end if; + END PROCESS; + wire_nlilOi_CLRN <= (nil00i50 XOR nil00i49); + wire_nlilOi_w_lg_nlilOl1869w(0) <= NOT nlilOl; + PROCESS (tx_clk, wire_nliO0l_CLRN) + BEGIN + IF (wire_nliO0l_CLRN = '0') THEN + nlii0i <= '0'; + nlii1l <= '0'; + nliiil <= '0'; + nliiiO <= '0'; + nliill <= '0'; + nliilO <= '0'; + nliiOi <= '0'; + nliiOl <= '0'; + nliiOO <= '0'; + nlil0i <= '0'; + nlil0l <= '0'; + nlil0O <= '0'; + nlil1i <= '0'; + nlil1l <= '0'; + nlil1O <= '0'; + nlilii <= '0'; + nlilil <= '0'; + nliliO <= '0'; + nlilli <= '0'; + nlilll <= '0'; + nlillO <= '0'; + nlilOO <= '0'; + nliO0i <= '0'; + nliO0O <= '0'; + nliO1i <= '0'; + nliO1l <= '0'; + nliO1O <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + IF (niOlil = '1') THEN + nlii0i <= tx_data(1); + nlii1l <= tx_data(0); + nliiil <= tx_data(5); + nliiiO <= tx_data(6); + nliill <= tx_data(8); + nliilO <= tx_data(9); + nliiOi <= tx_data(10); + nliiOl <= tx_data(11); + nliiOO <= tx_data(12); + nlil0i <= tx_data(16); + nlil0l <= tx_data(17); + nlil0O <= tx_data(18); + nlil1i <= tx_data(13); + nlil1l <= tx_data(14); + nlil1O <= tx_data(15); + nlilii <= tx_data(19); + nlilil <= tx_data(20); + nliliO <= tx_data(21); + nlilli <= tx_data(22); + nlilll <= tx_data(23); + nlillO <= tx_data(24); + nlilOO <= tx_data(26); + nliO0i <= tx_data(30); + nliO0O <= tx_data(31); + nliO1i <= tx_data(27); + nliO1l <= tx_data(28); + nliO1O <= tx_data(29); + END IF; + END IF; + END PROCESS; + wire_nliO0l_CLRN <= ((nil00l48 XOR nil00l47) AND wire_w_lg_soft_reset230w(0)); + wire_nliO0l_w_lg_w_lg_w_lg_w1866w1868w1870w1871w(0) <= wire_nliO0l_w_lg_w_lg_w1866w1868w1870w(0) AND nlillO; + wire_nliO0l_w_lg_w_lg_w1866w1868w1870w(0) <= wire_nliO0l_w_lg_w1866w1868w(0) AND wire_nlilOi_w_lg_nlilOl1869w(0); + wire_nliO0l_w_lg_w1866w1868w(0) <= wire_nliO0l_w1866w(0) AND wire_nliO0l_w_lg_nlilOO1867w(0); + wire_nliO0l_w1866w(0) <= wire_nliO0l_w_lg_w_lg_w_lg_w_lg_nliO0O1858w1860w1862w1864w(0) AND wire_nliO0l_w_lg_nliO1i1865w(0); + wire_nliO0l_w_lg_w_lg_w_lg_w_lg_nliO0O1858w1860w1862w1864w(0) <= wire_nliO0l_w_lg_w_lg_w_lg_nliO0O1858w1860w1862w(0) AND wire_nliO0l_w_lg_nliO1l1863w(0); + wire_nliO0l_w_lg_w_lg_w_lg_nliO0O1858w1860w1862w(0) <= wire_nliO0l_w_lg_w_lg_nliO0O1858w1860w(0) AND wire_nliO0l_w_lg_nliO1O1861w(0); + wire_nliO0l_w_lg_w_lg_nliO0O1858w1860w(0) <= wire_nliO0l_w_lg_nliO0O1858w(0) AND wire_nliO0l_w_lg_nliO0i1859w(0); + wire_nliO0l_w_lg_nliill1902w(0) <= NOT nliill; + wire_nliO0l_w_lg_nliilO1900w(0) <= NOT nliilO; + wire_nliO0l_w_lg_nliiOi1898w(0) <= NOT nliiOi; + wire_nliO0l_w_lg_nliiOl1896w(0) <= NOT nliiOl; + wire_nliO0l_w_lg_nliiOO1894w(0) <= NOT nliiOO; + wire_nliO0l_w_lg_nlil0i1886w(0) <= NOT nlil0i; + wire_nliO0l_w_lg_nlil0l1884w(0) <= NOT nlil0l; + wire_nliO0l_w_lg_nlil0O1882w(0) <= NOT nlil0O; + wire_nliO0l_w_lg_nlil1i1892w(0) <= NOT nlil1i; + wire_nliO0l_w_lg_nlil1l1890w(0) <= NOT nlil1l; + wire_nliO0l_w_lg_nlil1O1888w(0) <= NOT nlil1O; + wire_nliO0l_w_lg_nlilii1880w(0) <= NOT nlilii; + wire_nliO0l_w_lg_nlilil1878w(0) <= NOT nlilil; + wire_nliO0l_w_lg_nliliO1876w(0) <= NOT nliliO; + wire_nliO0l_w_lg_nlilli1874w(0) <= NOT nlilli; + wire_nliO0l_w_lg_nlilll1872w(0) <= NOT nlilll; + wire_nliO0l_w_lg_nlilOO1867w(0) <= NOT nlilOO; + wire_nliO0l_w_lg_nliO0i1859w(0) <= NOT nliO0i; + wire_nliO0l_w_lg_nliO0O1858w(0) <= NOT nliO0O; + wire_nliO0l_w_lg_nliO1i1865w(0) <= NOT nliO1i; + wire_nliO0l_w_lg_nliO1l1863w(0) <= NOT nliO1l; + wire_nliO0l_w_lg_nliO1O1861w(0) <= NOT nliO1O; + PROCESS (tx_clk, wire_nll0l_PRN, wire_nll0l_CLRN) + BEGIN + IF (wire_nll0l_PRN = '0') THEN + n0l0O <= '1'; + n0lii <= '1'; + n0llO <= '1'; + n0lOl <= '1'; + n1i0i <= '1'; + n1i0l <= '1'; + n1ili <= '1'; + nilOi <= '1'; + nilOl <= '1'; + niOil <= '1'; + niOiO <= '1'; + niOOi <= '1'; + nli00i <= '1'; + nli10i <= '1'; + nli10l <= '1'; + nli10O <= '1'; + nliOii <= '1'; + nliOll <= '1'; + nliOlO <= '1'; + nliOO <= '1'; + nll0i <= '1'; + nll0O <= '1'; + nll11l <= '1'; + nlO01l <= '1'; + nlO01O <= '1'; + nlO0il <= '1'; + ELSIF (wire_nll0l_CLRN = '0') THEN + n0l0O <= '0'; + n0lii <= '0'; + n0llO <= '0'; + n0lOl <= '0'; + n1i0i <= '0'; + n1i0l <= '0'; + n1ili <= '0'; + nilOi <= '0'; + nilOl <= '0'; + niOil <= '0'; + niOiO <= '0'; + niOOi <= '0'; + nli00i <= '0'; + nli10i <= '0'; + nli10l <= '0'; + nli10O <= '0'; + nliOii <= '0'; + nliOll <= '0'; + nliOlO <= '0'; + nliOO <= '0'; + nll0i <= '0'; + nll0O <= '0'; + nll11l <= '0'; + nlO01l <= '0'; + nlO01O <= '0'; + nlO0il <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + n0l0O <= wire_n0O1i_dataout; + n0lii <= wire_n0O1l_dataout; + n0llO <= wire_n0Oii_dataout; + n0lOl <= wire_nilOO_dataout; + n1i0i <= wire_n1iOl_dataout; + n1i0l <= wire_n1iOO_dataout; + n1ili <= wire_n1l0l_dataout; + nilOi <= wire_niO1i_dataout; + nilOl <= niOil; + niOil <= tx_local_fault_clr; + niOiO <= wire_niOll_dataout; + niOOi <= nliOO; + nli00i <= wire_nli1iO_dataout; + nli10i <= wire_nli1li_dataout; + nli10l <= wire_nli1ll_dataout; + nli10O <= wire_nli1lO_dataout; + nliOii <= wire_nliOiO_dataout; + nliOll <= wire_nll10O_dataout; + nliOlO <= wire_nll1ii_dataout; + nliOO <= indv; + nll0i <= wire_nl1Ol_o; + nll0O <= wire_nl1OO_dataout; + nll11l <= wire_nll1lO_dataout; + nlO01l <= wire_nlO0lO_dataout; + nlO01O <= wire_nlO0Oi_dataout; + nlO0il <= wire_nlOi1O_dataout; + END IF; + END PROCESS; + wire_nll0l_CLRN <= ((nili0i42 XOR nili0i41) AND wire_w_lg_soft_reset230w(0)); + wire_nll0l_PRN <= (nili1O44 XOR nili1O43); + wire_nll0l_w_lg_w_lg_w_lg_w_lg_nll0O365w371w1503w1504w(0) <= wire_nll0l_w_lg_w_lg_w_lg_nll0O365w371w1503w(0) AND nll1i; + wire_nll0l_w_lg_w_lg_w_lg_w_lg_nll0O365w371w372w373w(0) <= wire_nll0l_w_lg_w_lg_w_lg_nll0O365w371w372w(0) AND nll1i; + wire_nll0l_w_lg_w_lg_w_lg_nll0O365w367w368w(0) <= wire_nll0l_w_lg_w_lg_nll0O365w367w(0) AND nll1O; + wire_nll0l_w_lg_w_lg_w_lg_nll0O365w371w1503w(0) <= wire_nll0l_w_lg_w_lg_nll0O365w371w(0) AND wire_nll1l_w_lg_nll1O1502w(0); + wire_nll0l_w_lg_w_lg_w_lg_nll0O365w371w372w(0) <= wire_nll0l_w_lg_w_lg_nll0O365w371w(0) AND nll1O; + wire_nll0l_w_lg_w_lg_nll0O365w367w(0) <= wire_nll0l_w_lg_nll0O365w(0) AND wire_nll0l_w_lg_nll0i366w(0); + wire_nll0l_w_lg_w_lg_nll0O365w371w(0) <= wire_nll0l_w_lg_nll0O365w(0) AND nll0i; + wire_nll0l_w_lg_n0lOl378w(0) <= NOT n0lOl; + wire_nll0l_w_lg_nilOi377w(0) <= NOT nilOi; + wire_nll0l_w_lg_nliOii237w(0) <= NOT nliOii; + wire_nll0l_w_lg_nll0i366w(0) <= NOT nll0i; + wire_nll0l_w_lg_nll0O365w(0) <= NOT nll0O; + PROCESS (tx_clk, soft_reset, wire_nll1l_CLRN) + BEGIN + IF (soft_reset = '1') THEN + n0lil <= '1'; + n0liO <= '1'; + n0lli <= '1'; + n0lll <= '1'; + n0lOi <= '1'; + n1i0O <= '1'; + n1iii <= '1'; + n1iil <= '1'; + n1iiO <= '1'; + n1ill <= '1'; + n1ilO <= '1'; + niOli <= '1'; + nli0ll <= '1'; + nli0lO <= '1'; + nli0Oi <= '1'; + nli0Ol <= '1'; + nli0OO <= '1'; + nli1ii <= '1'; + nli1il <= '1'; + nlii1i <= '1'; + nliOil <= '1'; + nliOOi <= '1'; + nliOOl <= '1'; + nliOOO <= '1'; + nll10i <= '1'; + nll11i <= '1'; + nll11O <= '1'; + nll1i <= '1'; + nll1O <= '1'; + nlO00i <= '1'; + nlO00l <= '1'; + nlO00O <= '1'; + nlO0ii <= '1'; + nlO0iO <= '1'; + nlO0li <= '1'; + ELSIF (wire_nll1l_CLRN = '0') THEN + n0lil <= '0'; + n0liO <= '0'; + n0lli <= '0'; + n0lll <= '0'; + n0lOi <= '0'; + n1i0O <= '0'; + n1iii <= '0'; + n1iil <= '0'; + n1iiO <= '0'; + n1ill <= '0'; + n1ilO <= '0'; + niOli <= '0'; + nli0ll <= '0'; + nli0lO <= '0'; + nli0Oi <= '0'; + nli0Ol <= '0'; + nli0OO <= '0'; + nli1ii <= '0'; + nli1il <= '0'; + nlii1i <= '0'; + nliOil <= '0'; + nliOOi <= '0'; + nliOOl <= '0'; + nliOOO <= '0'; + nll10i <= '0'; + nll11i <= '0'; + nll11O <= '0'; + nll1i <= '0'; + nll1O <= '0'; + nlO00i <= '0'; + nlO00l <= '0'; + nlO00O <= '0'; + nlO0ii <= '0'; + nlO0iO <= '0'; + nlO0li <= '0'; + ELSIF (tx_clk = '1' AND tx_clk'event) THEN + n0lil <= wire_n0O1O_dataout; + n0liO <= wire_n0O0i_dataout; + n0lli <= wire_n0O0l_dataout; + n0lll <= wire_n0O0O_dataout; + n0lOi <= wire_n0Oil_dataout; + n1i0O <= wire_n1l1i_dataout; + n1iii <= wire_n1l1l_dataout; + n1iil <= wire_n1l1O_dataout; + n1iiO <= wire_n1l0i_dataout; + n1ill <= wire_n1l0O_dataout; + n1ilO <= wire_n0lOO_dataout; + niOli <= wire_niOOl_dataout; + nli0ll <= nli1il; + nli0lO <= nli0ll; + nli0Oi <= nli0lO; + nli0Ol <= nli0Oi; + nli0OO <= nli0Ol; + nli1ii <= wire_nli1Oi_dataout; + nli1il <= (nlii1i XOR nli0OO); + nlii1i <= nli0OO; + nliOil <= wire_nll10l_dataout; + nliOOi <= wire_nll1il_dataout; + nliOOl <= wire_nll1iO_dataout; + nliOOO <= wire_nll1li_dataout; + nll10i <= wire_nlO0ll_dataout; + nll11i <= wire_nll1ll_dataout; + nll11O <= wire_nll1Oi_dataout; + nll1i <= wire_nl1lO_o; + nll1O <= wire_nl1Oi_o; + nlO00i <= wire_nlO0Ol_dataout; + nlO00l <= wire_nlO0OO_dataout; + nlO00O <= wire_nlOi1i_dataout; + nlO0ii <= wire_nlOi1l_dataout; + nlO0iO <= wire_nlOi0i_dataout; + nlO0li <= wire_n1iOi_dataout; + END IF; + if (now = 0 ns) then + n0lil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0liO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0lli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0lll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0lOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1i0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1iii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1iil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1iiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1ill <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1ilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niOli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli0ll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli0lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli0Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli0Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli0OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlii1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliOil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliOOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliOOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliOOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll10i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll11i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll11O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO00i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO00l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO0ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO0iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO0li <= '1' after 1 ps; + end if; + END PROCESS; + wire_nll1l_CLRN <= (nili1i46 XOR nili1i45); + wire_nll1l_w_lg_w_lg_w_lg_niOli360w361w362w(0) <= wire_nll1l_w_lg_w_lg_niOli360w361w(0) AND nil0li; + wire_nll1l_w_lg_niOli360w(0) <= NOT niOli; + wire_nll1l_w_lg_nli1il239w(0) <= NOT nli1il; + wire_nll1l_w_lg_nll1i369w(0) <= NOT nll1i; + wire_nll1l_w_lg_nll1O1502w(0) <= NOT nll1O; + wire_nll1l_w_lg_w_lg_niOli360w361w(0) <= wire_nll1l_w_lg_niOli360w(0) OR nil0Oi; + wire_n000i_dataout <= wire_n011i_dataout WHEN nil0OO = '1' ELSE wire_n00lO_dataout; + wire_n000l_dataout <= wire_n011l_dataout WHEN nil0OO = '1' ELSE wire_n00Oi_dataout; + wire_n000O_dataout <= wire_n011O_dataout WHEN nil0OO = '1' ELSE wire_n00Ol_dataout; + wire_n001i_dataout <= wire_n1OOi_dataout WHEN nil0OO = '1' ELSE wire_n00iO_dataout; + wire_n001l_dataout <= wire_n1OOl_dataout WHEN nil0OO = '1' ELSE wire_n00li_dataout; + wire_n001O_dataout <= wire_n1OOO_dataout WHEN nil0OO = '1' ELSE wire_n00ll_dataout; + wire_n00ii_dataout <= nliill AND nliOii; + wire_n00il_dataout <= nliilO AND nliOii; + wire_n00iO_dataout <= nliiOi OR NOT(nliOii); + wire_n00li_dataout <= nliiOl OR NOT(nliOii); + wire_n00ll_dataout <= nliiOO OR NOT(nliOii); + wire_n00lO_dataout <= nlil1i WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_n00Oi_dataout <= nlil1l AND nliOii; + wire_n00Ol_dataout <= nlil1O WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_n00OO_dataout <= wire_n011i_dataout WHEN nil0OO = '1' ELSE wire_nllOll_dataout; + wire_n010i_dataout <= tx_ctl(1) OR niOO0l; + wire_n010l_dataout <= tx_data(8) OR niOO0l; + wire_n010O_dataout <= tx_data(9) AND NOT(niOO0l); + wire_n011i_dataout <= wire_n01li_dataout OR niliiO; + wire_n011l_dataout <= wire_n01ll_dataout AND NOT(niliiO); + wire_n011O_dataout <= wire_n01lO_dataout OR niliiO; + wire_n01ii_dataout <= tx_data(10) OR niOO0l; + wire_n01il_dataout <= tx_data(11) OR niOO0l; + wire_n01iO_dataout <= tx_data(12) OR niOO0l; + wire_n01li_dataout <= tx_data(13) OR niOO0l; + wire_n01ll_dataout <= tx_data(14) OR niOO0l; + wire_n01lO_dataout <= tx_data(15) OR niOO0l; + wire_n01Oi_dataout <= wire_n1Oli_dataout WHEN nil0OO = '1' ELSE wire_nll0l_w_lg_nliOii237w(0); + wire_n01Ol_dataout <= wire_n1Oll_dataout WHEN nil0OO = '1' ELSE wire_n00ii_dataout; + wire_n01OO_dataout <= wire_n1OlO_dataout WHEN nil0OO = '1' ELSE wire_n00il_dataout; + wire_n0i0i_dataout <= wire_n011O_dataout AND nil0OO; + wire_n0i0l_dataout <= wire_n011i_dataout WHEN nil0OO = '1' ELSE wire_n0iii_dataout; + wire_n0i0O_dataout <= wire_n011O_dataout WHEN nil0OO = '1' ELSE wire_n0iil_dataout; + wire_n0i1i_dataout <= wire_n011l_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Oi238w(0); + wire_n0i1l_dataout <= wire_n011O_dataout WHEN nil0OO = '1' ELSE wire_nllOlO_dataout; + wire_n0i1O_dataout <= wire_n011i_dataout AND nil0OO; + wire_n0iii_dataout <= nlil1i AND nliOii; + wire_n0iil_dataout <= nlil1O AND nliOii; + wire_n0iiO_dataout <= wire_n011i_dataout OR NOT(nil0OO); + wire_n0ili_dataout <= wire_n011l_dataout WHEN nil0OO = '1' ELSE nil0Ol; + wire_n0ill_dataout <= wire_n011O_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Ol236w(0); + wire_n0ilO_dataout <= wire_n1O1i_dataout OR NOT(rd_enable_sync); + wire_n0iOi_dataout <= wire_n1O1l_dataout AND rd_enable_sync; + wire_n0iOl_dataout <= wire_n1O1O_dataout AND rd_enable_sync; + wire_n0iOO_dataout <= wire_n1O0i_dataout OR NOT(rd_enable_sync); + wire_n0l0i_dataout <= wire_n1Oil_dataout AND rd_enable_sync; + wire_n0l0l_dataout <= wire_n0i0i_dataout OR NOT(rd_enable_sync); + wire_n0l1i_dataout <= wire_n1O0l_dataout OR NOT(rd_enable_sync); + wire_n0l1l_dataout <= wire_n1O0O_dataout OR NOT(rd_enable_sync); + wire_n0l1O_dataout <= wire_n0i1O_dataout OR NOT(rd_enable_sync); + wire_n0lOO_dataout <= wire_n0OiO_o OR niO1il; + wire_n0O0i_dataout <= wire_n0OOi_o OR niO1il; + wire_n0O0l_dataout <= wire_n0OOl_o OR niO1il; + wire_n0O0O_dataout <= wire_n0OOO_o OR niO1il; + wire_n0O1i_dataout <= wire_n0Oli_o AND NOT(niO1il); + wire_n0O1l_dataout <= wire_n0Oll_o OR niO1il; + wire_n0O1O_dataout <= wire_n0OlO_o OR niO1il; + wire_n0Oii_dataout <= wire_ni11i_o OR niO1il; + wire_n0Oil_dataout <= wire_ni11l_o OR niO1il; + wire_n100i_dataout <= wire_nlOO1i_dataout WHEN nil0OO = '1' ELSE wire_n100O_dataout; + wire_n100l_dataout <= nliliO AND nliOii; + wire_n100O_dataout <= nlilll AND nliOii; + wire_n101i_dataout <= wire_nlOlOl_dataout AND nil0OO; + wire_n101l_dataout <= wire_nlOO1i_dataout AND nil0OO; + wire_n101O_dataout <= wire_nlOlOl_dataout WHEN nil0OO = '1' ELSE wire_n100l_dataout; + wire_n10ii_dataout <= wire_nlOlOl_dataout OR NOT(nil0OO); + wire_n10il_dataout <= wire_nlOlOO_dataout WHEN nil0OO = '1' ELSE nil0Ol; + wire_n10iO_dataout <= wire_nlOO1i_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Ol236w(0); + wire_n10li_dataout <= wire_nlOiOl_dataout OR NOT(rd_enable_sync); + wire_n10ll_dataout <= wire_nlOiOO_dataout AND rd_enable_sync; + wire_n10lO_dataout <= wire_nlOl1i_dataout AND rd_enable_sync; + wire_n10Oi_dataout <= wire_nlOl1l_dataout OR NOT(rd_enable_sync); + wire_n10Ol_dataout <= wire_nlOl1O_dataout OR NOT(rd_enable_sync); + wire_n10OO_dataout <= wire_nlOl0i_dataout OR NOT(rd_enable_sync); + wire_n110i_dataout <= wire_nlOO1i_dataout WHEN nil0OO = '1' ELSE wire_n11lO_dataout; + wire_n110l_dataout <= nlil0i AND nliOii; + wire_n110O_dataout <= nlil0l AND nliOii; + wire_n111i_dataout <= wire_nlOlOi_dataout WHEN nil0OO = '1' ELSE wire_n11iO_dataout; + wire_n111l_dataout <= wire_nlOlOl_dataout WHEN nil0OO = '1' ELSE wire_n11li_dataout; + wire_n111O_dataout <= wire_nlOlOO_dataout WHEN nil0OO = '1' ELSE wire_n11ll_dataout; + wire_n11ii_dataout <= nlil0O OR NOT(nliOii); + wire_n11il_dataout <= nlilii OR NOT(nliOii); + wire_n11iO_dataout <= nlilil OR NOT(nliOii); + wire_n11li_dataout <= nliliO WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_n11ll_dataout <= nlilli AND nliOii; + wire_n11lO_dataout <= nlilll WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_n11Oi_dataout <= wire_nlOlOl_dataout WHEN nil0OO = '1' ELSE wire_nllOll_dataout; + wire_n11Ol_dataout <= wire_nlOlOO_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Oi238w(0); + wire_n11OO_dataout <= wire_nlOO1i_dataout WHEN nil0OO = '1' ELSE wire_nllOlO_dataout; + wire_n1i1i_dataout <= wire_n101i_dataout OR NOT(rd_enable_sync); + wire_n1i1l_dataout <= wire_nlOl0O_dataout AND rd_enable_sync; + wire_n1i1O_dataout <= wire_n101l_dataout OR NOT(rd_enable_sync); + wire_n1iOi_dataout <= wire_n1lii_o OR nilO0l; + wire_n1iOl_dataout <= wire_n1lil_o AND NOT(nilO0l); + wire_n1iOO_dataout <= wire_n1liO_o OR nilO0l; + wire_n1l0i_dataout <= wire_n1lOi_o OR nilO0l; + wire_n1l0l_dataout <= wire_n1lOl_o OR nilO0l; + wire_n1l0O_dataout <= wire_n1lOO_o OR nilO0l; + wire_n1l1i_dataout <= wire_n1lli_o OR nilO0l; + wire_n1l1l_dataout <= wire_n1lll_o OR nilO0l; + wire_n1l1O_dataout <= wire_n1llO_o OR nilO0l; + wire_n1O0i_dataout <= wire_n1OOi_dataout OR NOT(nil0OO); + wire_n1O0l_dataout <= wire_n1OOl_dataout OR NOT(nil0OO); + wire_n1O0O_dataout <= wire_n1OOO_dataout OR NOT(nil0OO); + wire_n1O1i_dataout <= wire_n1Oli_dataout OR NOT(nil0OO); + wire_n1O1l_dataout <= wire_n1Oll_dataout AND nil0OO; + wire_n1O1O_dataout <= wire_n1OlO_dataout AND nil0OO; + wire_n1Oii_dataout <= wire_n011i_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_n1Oil_dataout <= wire_n011l_dataout AND nil0OO; + wire_n1OiO_dataout <= wire_n011O_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_n1Oli_dataout <= wire_n010i_dataout OR niliiO; + wire_n1Oll_dataout <= wire_n010l_dataout AND NOT(niliiO); + wire_n1OlO_dataout <= wire_n010O_dataout AND NOT(niliiO); + wire_n1OOi_dataout <= wire_n01ii_dataout OR niliiO; + wire_n1OOl_dataout <= wire_n01il_dataout OR niliiO; + wire_n1OOO_dataout <= wire_n01iO_dataout OR niliiO; + wire_ni00i_dataout <= tx_data(6) OR nilili; + wire_ni00l_dataout <= tx_data(7) OR nilili; + wire_ni00O_dataout <= wire_ni1Oi_dataout WHEN nil0OO = '1' ELSE wire_ni0Ol_dataout; + wire_ni01i_dataout <= tx_data(3) OR nilili; + wire_ni01l_dataout <= tx_data(4) OR nilili; + wire_ni01O_dataout <= tx_data(5) OR nilili; + wire_ni0ii_dataout <= wire_ni1Ol_dataout WHEN nil0OO = '1' ELSE wire_ni0OO_dataout; + wire_ni0il_dataout <= wire_ni1OO_dataout WHEN nil0OO = '1' ELSE wire_nii1i_dataout; + wire_ni0iO_dataout <= wire_ni01i_dataout WHEN nil0OO = '1' ELSE wire_nii1l_dataout; + wire_ni0li_dataout <= wire_ni01l_dataout WHEN nil0OO = '1' ELSE wire_nii1O_dataout; + wire_ni0ll_dataout <= wire_ni01O_dataout WHEN nil0OO = '1' ELSE wire_nii0i_dataout; + wire_ni0lO_dataout <= wire_ni00i_dataout WHEN nil0OO = '1' ELSE wire_nii0l_dataout; + wire_ni0Oi_dataout <= wire_ni00l_dataout WHEN nil0OO = '1' ELSE wire_nii0O_dataout; + wire_ni0Ol_dataout <= nlii1l AND nliOii; + wire_ni0OO_dataout <= nlii0i AND nliOii; + wire_ni10i_dataout <= wire_ni1Oi_dataout AND nil0OO; + wire_ni10l_dataout <= wire_ni1Ol_dataout AND nil0OO; + wire_ni10O_dataout <= wire_ni1OO_dataout OR NOT(nil0OO); + wire_ni11O_dataout <= wire_ni1lO_dataout OR NOT(nil0OO); + wire_ni1ii_dataout <= wire_ni01i_dataout OR NOT(nil0OO); + wire_ni1il_dataout <= wire_ni01l_dataout OR NOT(nil0OO); + wire_ni1iO_dataout <= wire_ni01O_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_ni1li_dataout <= wire_ni00i_dataout AND nil0OO; + wire_ni1ll_dataout <= wire_ni00l_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_ni1lO_dataout <= tx_ctl(0) OR nilili; + wire_ni1Oi_dataout <= tx_data(0) OR nilili; + wire_ni1Ol_dataout <= tx_data(1) AND NOT(nilili); + wire_ni1OO_dataout <= tx_data(2) OR nilili; + wire_nii0i_dataout <= nliiil WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nii0l_dataout <= nliiiO AND nliOii; + wire_nii0O_dataout <= nliili WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nii1i_dataout <= nlii0l OR NOT(nliOii); + wire_nii1l_dataout <= nlii0O OR NOT(nliOii); + wire_nii1O_dataout <= nliiii OR NOT(nliOii); + wire_niiii_dataout <= wire_ni01O_dataout WHEN nil0OO = '1' ELSE wire_nllOll_dataout; + wire_niiil_dataout <= wire_ni00i_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Oi238w(0); + wire_niiiO_dataout <= wire_ni00l_dataout WHEN nil0OO = '1' ELSE wire_nllOlO_dataout; + wire_niili_dataout <= wire_ni01O_dataout AND nil0OO; + wire_niill_dataout <= wire_ni00l_dataout AND nil0OO; + wire_niilO_dataout <= wire_ni01O_dataout WHEN nil0OO = '1' ELSE wire_niiOl_dataout; + wire_niiOi_dataout <= wire_ni00l_dataout WHEN nil0OO = '1' ELSE wire_niiOO_dataout; + wire_niiOl_dataout <= nliiil AND nliOii; + wire_niiOO_dataout <= nliili AND nliOii; + wire_nil0i_dataout <= wire_ni11O_dataout OR NOT(rd_enable_sync); + wire_nil0l_dataout <= wire_ni10i_dataout AND rd_enable_sync; + wire_nil0O_dataout <= wire_ni10l_dataout AND rd_enable_sync; + wire_nil1i_dataout <= wire_ni01O_dataout OR NOT(nil0OO); + wire_nil1l_dataout <= wire_ni00i_dataout WHEN nil0OO = '1' ELSE nil0Ol; + wire_nil1O_dataout <= wire_ni00l_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Ol236w(0); + wire_nilii_dataout <= wire_ni10O_dataout OR NOT(rd_enable_sync); + wire_nilil_dataout <= wire_ni1ii_dataout OR NOT(rd_enable_sync); + wire_niliO_dataout <= wire_ni1il_dataout OR NOT(rd_enable_sync); + wire_nilli_dataout <= wire_niili_dataout OR NOT(rd_enable_sync); + wire_nilll_dataout <= wire_ni1li_dataout AND rd_enable_sync; + wire_nillO_dataout <= wire_niill_dataout OR NOT(rd_enable_sync); + wire_nilOO_dataout <= wire_niO1l_dataout AND nil0il; + wire_niO1i_dataout <= nil00O AND nil0il; + wire_niO1l_dataout <= (nilOi AND n0lOl) OR nil00O; + wire_niOll_dataout <= wire_niOlO_dataout AND NOT(nilOl); + wire_niOlO_dataout <= niOiO OR nilOi; + wire_niOOl_dataout <= wire_niOOO_dataout OR ((wire_w_lg_w_lg_w_lg_rd_enable_sync235w355w356w(0) OR wire_w_lg_w_lg_rd_enable_sync357w358w(0)) OR wire_nll1l_w_lg_w_lg_w_lg_niOli360w361w362w(0)); + wire_niOOO_dataout <= niOli AND NOT((nil0li AND nil0Ol)); + wire_nl00i_dataout <= wire_w_lg_nil0OO234w(0) AND NOT(niOOi); + wire_nl00l_dataout <= nli1il OR nil0OO; + wire_nl00O_dataout <= wire_nll1l_w_lg_nli1il239w(0) AND NOT(nil0OO); + wire_nl01l_dataout <= wire_nl00l_dataout OR niOOi; + wire_nl01O_dataout <= wire_nl00O_dataout OR niOOi; + wire_nl0ii_dataout <= wire_nl0ll_dataout OR niOOi; + wire_nl0il_dataout <= wire_nl0lO_dataout OR niOOi; + wire_nl0iO_dataout <= wire_nl0Oi_dataout AND NOT(niOOi); + wire_nl0li_dataout <= wire_nl0Ol_dataout AND NOT(niOOi); + wire_nl0ll_dataout <= wire_nl0OO_dataout OR nil0OO; + wire_nl0lO_dataout <= wire_nli1i_dataout AND NOT(nil0OO); + wire_nl0Oi_dataout <= wire_nll0l_w_lg_nliOii237w(0) AND NOT(nil0OO); + wire_nl0Ol_dataout <= nliOii AND NOT(nil0OO); + wire_nl0OO_dataout <= nli1il AND NOT(nliOii); + wire_nl1OO_dataout <= wire_nl0li_dataout AND wire_nl01i_o(7); + wire_nli01i_dataout <= wire_nli00l_o(3) WHEN nil0Oi = '1' ELSE nli10l; + wire_nli01l_dataout <= wire_nli00l_o(4) WHEN nil0Oi = '1' ELSE nli10O; + wire_nli01O_dataout <= wire_nli00l_o(5) WHEN nil0Oi = '1' ELSE nli1ii; + wire_nli0i_dataout <= wire_nli0O_dataout OR nil0OO; + wire_nli0l_dataout <= wire_nllOll_dataout AND NOT(nil0OO); + wire_nli0O_dataout <= nli1il OR wire_w_lg_nil0Oi238w(0); + wire_nli1i_dataout <= wire_nll1l_w_lg_nli1il239w(0) AND NOT(nliOii); + wire_nli1iO_dataout <= nli1il WHEN nil01O = '1' ELSE wire_nli1Ol_dataout; + wire_nli1l_dataout <= wire_nli0i_dataout OR niOOi; + wire_nli1li_dataout <= nli0ll WHEN nil01O = '1' ELSE wire_nli1OO_dataout; + wire_nli1ll_dataout <= nli0lO WHEN nil01O = '1' ELSE wire_nli01i_dataout; + wire_nli1lO_dataout <= nli0Oi WHEN nil01O = '1' ELSE wire_nli01l_dataout; + wire_nli1O_dataout <= wire_nli0l_dataout OR niOOi; + wire_nli1Oi_dataout <= wire_nli01O_dataout OR nil01O; + wire_nli1Ol_dataout <= wire_nli00l_o(1) WHEN nil0Oi = '1' ELSE nli00i; + wire_nli1OO_dataout <= wire_nli00l_o(2) WHEN nil0Oi = '1' ELSE nli10i; + wire_nliii_dataout <= wire_nliil_dataout OR niOOi; + wire_nliil_dataout <= wire_nll0l_w_lg_nliOii237w(0) OR nil0OO; + wire_nliiO_dataout <= wire_nlill_dataout OR niOOi; + wire_nlili_dataout <= wire_w_lg_nil0OO234w(0) OR niOOi; + wire_nlill_dataout <= wire_w_lg_nil0Ol236w(0) OR nil0OO; + wire_nlilO_dataout <= wire_w_lg_rd_enable_sync235w(0) OR niOOi; + wire_nliOi_dataout <= wire_nliOl_dataout AND NOT(niOOi); + wire_nliOiO_dataout <= wire_nliOli_dataout OR niOlil; + wire_nliOl_dataout <= wire_w_lg_nil0OO234w(0) AND rd_enable_sync; + wire_nliOli_dataout <= nliOii AND NOT(nil0il); + wire_nll0il_dataout <= wire_nlli1l_dataout OR NOT(nil0OO); + wire_nll0iO_dataout <= wire_nlli1O_dataout AND nil0OO; + wire_nll0li_dataout <= wire_nlli0i_dataout AND nil0OO; + wire_nll0ll_dataout <= wire_nlli0l_dataout OR NOT(nil0OO); + wire_nll0lO_dataout <= wire_nlli0O_dataout OR NOT(nil0OO); + wire_nll0Oi_dataout <= wire_nlliii_dataout OR NOT(nil0OO); + wire_nll0Ol_dataout <= wire_nlliil_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nll0OO_dataout <= wire_nlliiO_dataout AND nil0OO; + wire_nll10l_dataout <= wire_nll1Ol_o OR nililO; + wire_nll10O_dataout <= wire_nll1OO_o AND NOT(nililO); + wire_nll1ii_dataout <= wire_nll01i_o OR nililO; + wire_nll1il_dataout <= wire_nll01l_o OR nililO; + wire_nll1iO_dataout <= wire_nll01O_o OR nililO; + wire_nll1li_dataout <= wire_nll00i_o OR nililO; + wire_nll1ll_dataout <= wire_nll00l_o OR nililO; + wire_nll1lO_dataout <= wire_nll00O_o OR nililO; + wire_nll1Oi_dataout <= wire_nll0ii_o OR nililO; + wire_nlli0i_dataout <= wire_nlliOi_dataout AND NOT(nili0l); + wire_nlli0l_dataout <= wire_nlliOl_dataout OR nili0l; + wire_nlli0O_dataout <= wire_nlliOO_dataout OR nili0l; + wire_nlli1i_dataout <= wire_nllili_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nlli1l_dataout <= wire_nllill_dataout OR nili0l; + wire_nlli1O_dataout <= wire_nllilO_dataout AND NOT(nili0l); + wire_nlliii_dataout <= wire_nlll1i_dataout OR nili0l; + wire_nlliil_dataout <= wire_nlll1l_dataout OR nili0l; + wire_nlliiO_dataout <= wire_nlll1O_dataout AND NOT(nili0l); + wire_nllili_dataout <= wire_nlll0i_dataout OR nili0l; + wire_nllill_dataout <= tx_ctl(3) OR niOllO; + wire_nllilO_dataout <= tx_data(24) OR niOllO; + wire_nlliOi_dataout <= tx_data(25) AND NOT(niOllO); + wire_nlliOl_dataout <= tx_data(26) OR niOllO; + wire_nlliOO_dataout <= tx_data(27) OR niOllO; + wire_nlll0i_dataout <= tx_data(31) OR niOllO; + wire_nlll0O_dataout <= wire_nlli1l_dataout WHEN nil0OO = '1' ELSE wire_nll0l_w_lg_nliOii237w(0); + wire_nlll1i_dataout <= tx_data(28) OR niOllO; + wire_nlll1l_dataout <= tx_data(29) OR niOllO; + wire_nlll1O_dataout <= tx_data(30) OR niOllO; + wire_nlllii_dataout <= wire_nlli1O_dataout WHEN nil0OO = '1' ELSE wire_nlllOO_dataout; + wire_nlllil_dataout <= wire_nlli0i_dataout WHEN nil0OO = '1' ELSE wire_nllO1i_dataout; + wire_nllliO_dataout <= wire_nlli0l_dataout WHEN nil0OO = '1' ELSE wire_nllO1l_dataout; + wire_nlllli_dataout <= wire_nlli0O_dataout WHEN nil0OO = '1' ELSE wire_nllO1O_dataout; + wire_nlllll_dataout <= wire_nlliii_dataout WHEN nil0OO = '1' ELSE wire_nllO0i_dataout; + wire_nllllO_dataout <= wire_nlliil_dataout WHEN nil0OO = '1' ELSE wire_nllO0l_dataout; + wire_nlllOi_dataout <= wire_nlliiO_dataout WHEN nil0OO = '1' ELSE wire_nllO0O_dataout; + wire_nlllOl_dataout <= wire_nllili_dataout WHEN nil0OO = '1' ELSE wire_nllOii_dataout; + wire_nlllOO_dataout <= nlillO AND nliOii; + wire_nllO0i_dataout <= nliO1l OR NOT(nliOii); + wire_nllO0l_dataout <= nliO1O WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nllO0O_dataout <= nliO0i AND nliOii; + wire_nllO1i_dataout <= nlilOl AND nliOii; + wire_nllO1l_dataout <= nlilOO OR NOT(nliOii); + wire_nllO1O_dataout <= nliO1i OR NOT(nliOii); + wire_nllOii_dataout <= nliO0O WHEN nliOii = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nllOil_dataout <= wire_nlliil_dataout WHEN nil0OO = '1' ELSE wire_nllOll_dataout; + wire_nllOiO_dataout <= wire_nlliiO_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Oi238w(0); + wire_nllOli_dataout <= wire_nllili_dataout WHEN nil0OO = '1' ELSE wire_nllOlO_dataout; + wire_nllOll_dataout <= wire_nll1l_w_lg_nli1il239w(0) OR wire_w_lg_nil0Oi238w(0); + wire_nllOlO_dataout <= wire_nll1l_w_lg_nli1il239w(0) AND NOT(wire_w_lg_nil0Oi238w(0)); + wire_nllOOi_dataout <= wire_nlliil_dataout AND nil0OO; + wire_nllOOl_dataout <= wire_nllili_dataout AND nil0OO; + wire_nllOOO_dataout <= wire_nlliil_dataout WHEN nil0OO = '1' ELSE wire_nlO11l_dataout; + wire_nlO01i_dataout <= wire_nllOOl_dataout OR NOT(rd_enable_sync); + wire_nlO0ll_dataout <= wire_nlOi0l_o OR nillil; + wire_nlO0lO_dataout <= wire_nlOi0O_o AND NOT(nillil); + wire_nlO0Oi_dataout <= wire_nlOiii_o OR nillil; + wire_nlO0Ol_dataout <= wire_nlOiil_o OR nillil; + wire_nlO0OO_dataout <= wire_nlOiiO_o OR nillil; + wire_nlO10i_dataout <= wire_nlliil_dataout OR NOT(nil0OO); + wire_nlO10l_dataout <= wire_nlliiO_dataout WHEN nil0OO = '1' ELSE nil0Ol; + wire_nlO10O_dataout <= wire_nllili_dataout WHEN nil0OO = '1' ELSE wire_w_lg_nil0Ol236w(0); + wire_nlO11i_dataout <= wire_nllili_dataout WHEN nil0OO = '1' ELSE wire_nlO11O_dataout; + wire_nlO11l_dataout <= nliO1O AND nliOii; + wire_nlO11O_dataout <= nliO0O AND nliOii; + wire_nlO1il_dataout <= wire_nll0il_dataout OR NOT(rd_enable_sync); + wire_nlO1iO_dataout <= wire_nll0iO_dataout AND rd_enable_sync; + wire_nlO1li_dataout <= wire_nll0li_dataout AND rd_enable_sync; + wire_nlO1ll_dataout <= wire_nll0ll_dataout OR NOT(rd_enable_sync); + wire_nlO1lO_dataout <= wire_nll0lO_dataout OR NOT(rd_enable_sync); + wire_nlO1Oi_dataout <= wire_nll0Oi_dataout OR NOT(rd_enable_sync); + wire_nlO1Ol_dataout <= wire_nllOOi_dataout OR NOT(rd_enable_sync); + wire_nlO1OO_dataout <= wire_nll0OO_dataout AND rd_enable_sync; + wire_nlOi0i_dataout <= wire_nlOiOi_o OR nillil; + wire_nlOi1i_dataout <= wire_nlOili_o OR nillil; + wire_nlOi1l_dataout <= wire_nlOill_o OR nillil; + wire_nlOi1O_dataout <= wire_nlOilO_o OR nillil; + wire_nlOiOl_dataout <= wire_nlOlil_dataout OR NOT(nil0OO); + wire_nlOiOO_dataout <= wire_nlOliO_dataout AND nil0OO; + wire_nlOl0i_dataout <= wire_nlOlOi_dataout OR NOT(nil0OO); + wire_nlOl0l_dataout <= wire_nlOlOl_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nlOl0O_dataout <= wire_nlOlOO_dataout AND nil0OO; + wire_nlOl1i_dataout <= wire_nlOlli_dataout AND nil0OO; + wire_nlOl1l_dataout <= wire_nlOlll_dataout OR NOT(nil0OO); + wire_nlOl1O_dataout <= wire_nlOllO_dataout OR NOT(nil0OO); + wire_nlOlii_dataout <= wire_nlOO1i_dataout WHEN nil0OO = '1' ELSE wire_nll1l_w_lg_nli1il239w(0); + wire_nlOlil_dataout <= wire_nlOO1l_dataout OR nili0O; + wire_nlOliO_dataout <= wire_nlOO1O_dataout AND NOT(nili0O); + wire_nlOlli_dataout <= wire_nlOO0i_dataout AND NOT(nili0O); + wire_nlOlll_dataout <= wire_nlOO0l_dataout OR nili0O; + wire_nlOllO_dataout <= wire_nlOO0O_dataout OR nili0O; + wire_nlOlOi_dataout <= wire_nlOOii_dataout OR nili0O; + wire_nlOlOl_dataout <= wire_nlOOil_dataout OR nili0O; + wire_nlOlOO_dataout <= wire_nlOOiO_dataout AND NOT(nili0O); + wire_nlOO0i_dataout <= tx_data(17) AND NOT(niOO1i); + wire_nlOO0l_dataout <= tx_data(18) OR niOO1i; + wire_nlOO0O_dataout <= tx_data(19) OR niOO1i; + wire_nlOO1i_dataout <= wire_nlOOli_dataout OR nili0O; + wire_nlOO1l_dataout <= tx_ctl(2) OR niOO1i; + wire_nlOO1O_dataout <= tx_data(16) OR niOO1i; + wire_nlOOii_dataout <= tx_data(20) OR niOO1i; + wire_nlOOil_dataout <= tx_data(21) OR niOO1i; + wire_nlOOiO_dataout <= tx_data(22) OR niOO1i; + wire_nlOOli_dataout <= tx_data(23) OR niOO1i; + wire_nlOOll_dataout <= wire_nlOlil_dataout WHEN nil0OO = '1' ELSE wire_nll0l_w_lg_nliOii237w(0); + wire_nlOOlO_dataout <= wire_nlOliO_dataout WHEN nil0OO = '1' ELSE wire_n110l_dataout; + wire_nlOOOi_dataout <= wire_nlOlli_dataout WHEN nil0OO = '1' ELSE wire_n110O_dataout; + wire_nlOOOl_dataout <= wire_nlOlll_dataout WHEN nil0OO = '1' ELSE wire_n11ii_dataout; + wire_nlOOOO_dataout <= wire_nlOllO_dataout WHEN nil0OO = '1' ELSE wire_n11il_dataout; + wire_nli00l_a <= ( nli1ii & nli10O & nli10l & nli10i & nli00i & "1"); + wire_nli00l_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + nli00l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nli00l_a, + b => wire_nli00l_b, + cin => wire_gnd, + o => wire_nli00l_o + ); + wire_nl01i_i <= ( nll0O & nll0i & nll1O & nll1i); + nl01i : oper_decoder + GENERIC MAP ( + width_i => 4, + width_o => 16 + ) + PORT MAP ( + i => wire_nl01i_i, + o => wire_nl01i_o + ); + wire_nl1li_a <= ( "1" & "0" & "0" & "0"); + wire_nl1li_b <= ( nll0O & nll0i & nll1O & nll1i); + nl1li : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nl1li_a, + b => wire_nl1li_b, + cin => wire_gnd, + o => wire_nl1li_o + ); + wire_n0OiO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni11O_dataout & wire_ni11O_dataout & wire_ni11O_dataout & wire_ni11O_dataout & wire_ni11O_dataout & wire_nil0i_dataout & wire_ni11O_dataout & wire_ni11O_dataout & "1"); + wire_n0OiO_sel <= ( nll0O & nll0i & nll1O & nll1i); + n0OiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OiO_data, + o => wire_n0OiO_o, + sel => wire_n0OiO_sel + ); + wire_n0Oli_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_ni10i_dataout & wire_ni00O_dataout & wire_ni10i_dataout & wire_ni10i_dataout & wire_ni10i_dataout & wire_nil0l_dataout & wire_ni00O_dataout & wire_ni10i_dataout & "0"); + wire_n0Oli_sel <= ( nll0O & nll0i & nll1O & nll1i); + n0Oli : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oli_data, + o => wire_n0Oli_o, + sel => wire_n0Oli_sel + ); + wire_n0Oll_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_ni10l_dataout & wire_ni0ii_dataout & wire_ni10l_dataout & wire_ni10l_dataout & wire_ni10l_dataout & wire_nil0O_dataout & wire_ni0ii_dataout & wire_ni10l_dataout & "0"); + wire_n0Oll_sel <= ( nll0O & nll0i & nll1O & nll1i); + n0Oll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0Oll_data, + o => wire_n0Oll_o, + sel => wire_n0Oll_sel + ); + wire_n0OlO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni10O_dataout & wire_ni0il_dataout & wire_ni10O_dataout & wire_ni10O_dataout & wire_ni10O_dataout & wire_nilii_dataout & wire_ni0il_dataout & wire_ni10O_dataout & "1"); + wire_n0OlO_sel <= ( nll0O & nll0i & nll1O & nll1i); + n0OlO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OlO_data, + o => wire_n0OlO_o, + sel => wire_n0OlO_sel + ); + wire_n0OOi_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni1ii_dataout & wire_ni0iO_dataout & wire_ni1ii_dataout & wire_ni1ii_dataout & wire_ni1ii_dataout & wire_nilil_dataout & wire_ni0iO_dataout & wire_ni1ii_dataout & "1"); + wire_n0OOi_sel <= ( nll0O & nll0i & nll1O & nll1i); + n0OOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOi_data, + o => wire_n0OOi_o, + sel => wire_n0OOi_sel + ); + wire_n0OOl_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni1il_dataout & wire_ni0li_dataout & wire_ni1il_dataout & wire_ni1il_dataout & wire_ni1il_dataout & wire_niliO_dataout & wire_ni0li_dataout & wire_ni1il_dataout & "1"); + wire_n0OOl_sel <= ( nll0O & nll0i & nll1O & nll1i); + n0OOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOl_data, + o => wire_n0OOl_o, + sel => wire_n0OOl_sel + ); + wire_n0OOO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni1iO_dataout & wire_ni0ll_dataout & wire_niiii_dataout & wire_niiii_dataout & wire_niili_dataout & wire_nilli_dataout & wire_niilO_dataout & wire_nil1i_dataout & "1"); + wire_n0OOO_sel <= ( nll0O & nll0i & nll1O & nll1i); + n0OOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OOO_data, + o => wire_n0OOO_o, + sel => wire_n0OOO_sel + ); + wire_n1lii_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n1O1i_dataout & wire_n01Oi_dataout & wire_n1O1i_dataout & wire_n1O1i_dataout & wire_n1O1i_dataout & wire_n0ilO_dataout & wire_n01Oi_dataout & wire_n1O1i_dataout & "1"); + wire_n1lii_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1lii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lii_data, + o => wire_n1lii_o, + sel => wire_n1lii_sel + ); + wire_n1lil_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n1O1l_dataout & wire_n01Ol_dataout & wire_n1O1l_dataout & wire_n1O1l_dataout & wire_n1O1l_dataout & wire_n0iOi_dataout & wire_n01Ol_dataout & wire_n1O1l_dataout & "0"); + wire_n1lil_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1lil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lil_data, + o => wire_n1lil_o, + sel => wire_n1lil_sel + ); + wire_n1liO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n1O1O_dataout & wire_n01OO_dataout & wire_n1O1O_dataout & wire_n1O1O_dataout & wire_n1O1O_dataout & wire_n0iOl_dataout & wire_n01OO_dataout & wire_n1O1O_dataout & "0"); + wire_n1liO_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1liO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1liO_data, + o => wire_n1liO_o, + sel => wire_n1liO_sel + ); + wire_n1lli_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n1O0i_dataout & wire_n001i_dataout & wire_n1O0i_dataout & wire_n1O0i_dataout & wire_n1O0i_dataout & wire_n0iOO_dataout & wire_n001i_dataout & wire_n1O0i_dataout & "1"); + wire_n1lli_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1lli : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lli_data, + o => wire_n1lli_o, + sel => wire_n1lli_sel + ); + wire_n1lll_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n1O0l_dataout & wire_n001l_dataout & wire_n1O0l_dataout & wire_n1O0l_dataout & wire_n1O0l_dataout & wire_n0l1i_dataout & wire_n001l_dataout & wire_n1O0l_dataout & "1"); + wire_n1lll_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1lll : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lll_data, + o => wire_n1lll_o, + sel => wire_n1lll_sel + ); + wire_n1llO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n1O0O_dataout & wire_n001O_dataout & wire_n1O0O_dataout & wire_n1O0O_dataout & wire_n1O0O_dataout & wire_n0l1l_dataout & wire_n001O_dataout & wire_n1O0O_dataout & "1"); + wire_n1llO_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1llO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1llO_data, + o => wire_n1llO_o, + sel => wire_n1llO_sel + ); + wire_n1lOi_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n1Oii_dataout & wire_n000i_dataout & wire_n00OO_dataout & wire_n00OO_dataout & wire_n0i1O_dataout & wire_n0l1O_dataout & wire_n0i0l_dataout & wire_n0iiO_dataout & "1"); + wire_n1lOi_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1lOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lOi_data, + o => wire_n1lOi_o, + sel => wire_n1lOi_sel + ); + wire_n1lOl_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_n1Oil_dataout & wire_n000l_dataout & wire_n0i1i_dataout & wire_n0i1i_dataout & wire_n1Oil_dataout & wire_n0l0i_dataout & wire_n000l_dataout & wire_n0ili_dataout & "0"); + wire_n1lOl_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1lOl : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lOl_data, + o => wire_n1lOl_o, + sel => wire_n1lOl_sel + ); + wire_n1lOO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_n1OiO_dataout & wire_n000O_dataout & wire_n0i1l_dataout & wire_n0i1l_dataout & wire_n0i0i_dataout & wire_n0l0l_dataout & wire_n0i0O_dataout & wire_n0ill_dataout & "1"); + wire_n1lOO_sel <= ( nll0O & nll0i & nll1O & nll1i); + n1lOO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1lOO_data, + o => wire_n1lOO_o, + sel => wire_n1lOO_sel + ); + wire_ni11i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_ni1li_dataout & wire_ni0lO_dataout & wire_niiil_dataout & wire_niiil_dataout & wire_ni1li_dataout & wire_nilll_dataout & wire_ni0lO_dataout & wire_nil1l_dataout & "0"); + wire_ni11i_sel <= ( nll0O & nll0i & nll1O & nll1i); + ni11i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni11i_data, + o => wire_ni11i_o, + sel => wire_ni11i_sel + ); + wire_ni11l_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_ni1ll_dataout & wire_ni0Oi_dataout & wire_niiiO_dataout & wire_niiiO_dataout & wire_niill_dataout & wire_nillO_dataout & wire_niiOi_dataout & wire_nil1O_dataout & "1"); + wire_ni11l_sel <= ( nll0O & nll0i & nll1O & nll1i); + ni11l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni11l_data, + o => wire_ni11l_o, + sel => wire_ni11l_sel + ); + wire_nl1lO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nl01l_dataout & wire_nl0ii_dataout & wire_nli1l_dataout & wire_nli1l_dataout & "1" & "1" & wire_nliii_dataout & wire_nliiO_dataout & "1"); + wire_nl1lO_sel <= ( nll0O & nll0i & nll1O & nll1i); + nl1lO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1lO_data, + o => wire_nl1lO_o, + sel => wire_nl1lO_sel + ); + wire_nl1Oi_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nl01O_dataout & wire_nl0il_dataout & wire_nli1O_dataout & wire_nli1O_dataout & niOOi & wire_nlilO_dataout & niOOi & wire_nlili_dataout & "1"); + wire_nl1Oi_sel <= ( nll0O & nll0i & nll1O & nll1i); + nl1Oi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1Oi_data, + o => wire_nl1Oi_o, + sel => wire_nl1Oi_sel + ); + wire_nl1Ol_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nl00i_dataout & wire_nl0iO_dataout & wire_nl00i_dataout & wire_nl00i_dataout & wire_nl00i_dataout & wire_nliOi_dataout & wire_nl00i_dataout & "0" & "0"); + wire_nl1Ol_sel <= ( nll0O & nll0i & nll1O & nll1i); + nl1Ol : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1Ol_data, + o => wire_nl1Ol_o, + sel => wire_nl1Ol_sel + ); + wire_nll00i_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nll0Oi_dataout & wire_nlllll_dataout & wire_nll0Oi_dataout & wire_nll0Oi_dataout & wire_nll0Oi_dataout & wire_nlO1Oi_dataout & wire_nlllll_dataout & wire_nll0Oi_dataout & "1"); + wire_nll00i_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll00i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll00i_data, + o => wire_nll00i_o, + sel => wire_nll00i_sel + ); + wire_nll00l_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nll0Ol_dataout & wire_nllllO_dataout & wire_nllOil_dataout & wire_nllOil_dataout & wire_nllOOi_dataout & wire_nlO1Ol_dataout & wire_nllOOO_dataout & wire_nlO10i_dataout & "1"); + wire_nll00l_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll00l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll00l_data, + o => wire_nll00l_o, + sel => wire_nll00l_sel + ); + wire_nll00O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nll0OO_dataout & wire_nlllOi_dataout & wire_nllOiO_dataout & wire_nllOiO_dataout & wire_nll0OO_dataout & wire_nlO1OO_dataout & wire_nlllOi_dataout & wire_nlO10l_dataout & "0"); + wire_nll00O_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll00O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll00O_data, + o => wire_nll00O_o, + sel => wire_nll00O_sel + ); + wire_nll01i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nll0li_dataout & wire_nlllil_dataout & wire_nll0li_dataout & wire_nll0li_dataout & wire_nll0li_dataout & wire_nlO1li_dataout & wire_nlllil_dataout & wire_nll0li_dataout & "0"); + wire_nll01i_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll01i : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll01i_data, + o => wire_nll01i_o, + sel => wire_nll01i_sel + ); + wire_nll01l_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nll0ll_dataout & wire_nllliO_dataout & wire_nll0ll_dataout & wire_nll0ll_dataout & wire_nll0ll_dataout & wire_nlO1ll_dataout & wire_nllliO_dataout & wire_nll0ll_dataout & "1"); + wire_nll01l_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll01l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll01l_data, + o => wire_nll01l_o, + sel => wire_nll01l_sel + ); + wire_nll01O_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nll0lO_dataout & wire_nlllli_dataout & wire_nll0lO_dataout & wire_nll0lO_dataout & wire_nll0lO_dataout & wire_nlO1lO_dataout & wire_nlllli_dataout & wire_nll0lO_dataout & "1"); + wire_nll01O_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll01O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll01O_data, + o => wire_nll01O_o, + sel => wire_nll01O_sel + ); + wire_nll0ii_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlli1i_dataout & wire_nlllOl_dataout & wire_nllOli_dataout & wire_nllOli_dataout & wire_nllOOl_dataout & wire_nlO01i_dataout & wire_nlO11i_dataout & wire_nlO10O_dataout & "1"); + wire_nll0ii_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll0ii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll0ii_data, + o => wire_nll0ii_o, + sel => wire_nll0ii_sel + ); + wire_nll1Ol_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nll0il_dataout & wire_nlll0O_dataout & wire_nll0il_dataout & wire_nll0il_dataout & wire_nll0il_dataout & wire_nlO1il_dataout & wire_nlll0O_dataout & wire_nll0il_dataout & "1"); + wire_nll1Ol_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll1Ol : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll1Ol_data, + o => wire_nll1Ol_o, + sel => wire_nll1Ol_sel + ); + wire_nll1OO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nll0iO_dataout & wire_nlllii_dataout & wire_nll0iO_dataout & wire_nll0iO_dataout & wire_nll0iO_dataout & wire_nlO1iO_dataout & wire_nlllii_dataout & wire_nll0iO_dataout & "0"); + wire_nll1OO_sel <= ( nll0O & nll0i & nll1O & nll1i); + nll1OO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nll1OO_data, + o => wire_nll1OO_o, + sel => wire_nll1OO_sel + ); + wire_nlOi0l_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOiOl_dataout & wire_nlOOll_dataout & wire_nlOiOl_dataout & wire_nlOiOl_dataout & wire_nlOiOl_dataout & wire_n10li_dataout & wire_nlOOll_dataout & wire_nlOiOl_dataout & "1"); + wire_nlOi0l_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOi0l : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOi0l_data, + o => wire_nlOi0l_o, + sel => wire_nlOi0l_sel + ); + wire_nlOi0O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlOiOO_dataout & wire_nlOOlO_dataout & wire_nlOiOO_dataout & wire_nlOiOO_dataout & wire_nlOiOO_dataout & wire_n10ll_dataout & wire_nlOOlO_dataout & wire_nlOiOO_dataout & "0"); + wire_nlOi0O_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOi0O : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOi0O_data, + o => wire_nlOi0O_o, + sel => wire_nlOi0O_sel + ); + wire_nlOiii_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlOl1i_dataout & wire_nlOOOi_dataout & wire_nlOl1i_dataout & wire_nlOl1i_dataout & wire_nlOl1i_dataout & wire_n10lO_dataout & wire_nlOOOi_dataout & wire_nlOl1i_dataout & "0"); + wire_nlOiii_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOiii : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOiii_data, + o => wire_nlOiii_o, + sel => wire_nlOiii_sel + ); + wire_nlOiil_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOl1l_dataout & wire_nlOOOl_dataout & wire_nlOl1l_dataout & wire_nlOl1l_dataout & wire_nlOl1l_dataout & wire_n10Oi_dataout & wire_nlOOOl_dataout & wire_nlOl1l_dataout & "1"); + wire_nlOiil_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOiil : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOiil_data, + o => wire_nlOiil_o, + sel => wire_nlOiil_sel + ); + wire_nlOiiO_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOl1O_dataout & wire_nlOOOO_dataout & wire_nlOl1O_dataout & wire_nlOl1O_dataout & wire_nlOl1O_dataout & wire_n10Ol_dataout & wire_nlOOOO_dataout & wire_nlOl1O_dataout & "1"); + wire_nlOiiO_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOiiO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOiiO_data, + o => wire_nlOiiO_o, + sel => wire_nlOiiO_sel + ); + wire_nlOili_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOl0i_dataout & wire_n111i_dataout & wire_nlOl0i_dataout & wire_nlOl0i_dataout & wire_nlOl0i_dataout & wire_n10OO_dataout & wire_n111i_dataout & wire_nlOl0i_dataout & "1"); + wire_nlOili_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOili : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOili_data, + o => wire_nlOili_o, + sel => wire_nlOili_sel + ); + wire_nlOill_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOl0l_dataout & wire_n111l_dataout & wire_n11Oi_dataout & wire_n11Oi_dataout & wire_n101i_dataout & wire_n1i1i_dataout & wire_n101O_dataout & wire_n10ii_dataout & "1"); + wire_nlOill_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOill : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOill_data, + o => wire_nlOill_o, + sel => wire_nlOill_sel + ); + wire_nlOilO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlOl0O_dataout & wire_n111O_dataout & wire_n11Ol_dataout & wire_n11Ol_dataout & wire_nlOl0O_dataout & wire_n1i1l_dataout & wire_n111O_dataout & wire_n10il_dataout & "0"); + wire_nlOilO_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOilO : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOilO_data, + o => wire_nlOilO_o, + sel => wire_nlOilO_sel + ); + wire_nlOiOi_data <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlOlii_dataout & wire_n110i_dataout & wire_n11OO_dataout & wire_n11OO_dataout & wire_n101l_dataout & wire_n1i1O_dataout & wire_n100i_dataout & wire_n10iO_dataout & "1"); + wire_nlOiOi_sel <= ( nll0O & nll0i & nll1O & nll1i); + nlOiOi : oper_mux + GENERIC MAP ( + width_data => 16, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOiOi_data, + o => wire_nlOiOi_o, + sel => wire_nlOiOi_sel + ); + + END RTL; --cycloneiv_hssi_tx_sm +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 170 mux21 775 oper_mux 3 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_rcv_sm IS + PORT + ( + clk_2 : IN STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + dec_ctl : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + dec_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + dec_data_valid : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + indv : IN STD_LOGIC; + running_disp : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_ctl_rs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_data_rs : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + rx_local_fault : OUT STD_LOGIC; + rx_local_fault_clr : IN STD_LOGIC; + rxaui_s2gx_en : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + tx_local_fault_det : IN STD_LOGIC; + xs_link_status : OUT STD_LOGIC; + xs_link_status_set : IN STD_LOGIC + ); + END cycloneiv_hssi_rcv_sm; + + ARCHITECTURE RTL OF cycloneiv_hssi_rcv_sm IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL n0Olli45 : STD_LOGIC := '0'; + SIGNAL n0Olli46 : STD_LOGIC := '0'; + SIGNAL n0OlOl43 : STD_LOGIC := '0'; + SIGNAL n0OlOl44 : STD_LOGIC := '0'; + SIGNAL n0OO0l39 : STD_LOGIC := '0'; + SIGNAL n0OO0l40 : STD_LOGIC := '0'; + SIGNAL n0OO1l41 : STD_LOGIC := '0'; + SIGNAL n0OO1l42 : STD_LOGIC := '0'; + SIGNAL n0OOil37 : STD_LOGIC := '0'; + SIGNAL n0OOil38 : STD_LOGIC := '0'; + SIGNAL wire_n0OOil38_w_lg_w_lg_q150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0OOil38_w_lg_q150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0OOiO35 : STD_LOGIC := '0'; + SIGNAL n0OOiO36 : STD_LOGIC := '0'; + SIGNAL wire_n0OOiO36_w_lg_w_lg_q145w146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0OOiO36_w_lg_q145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0OOli33 : STD_LOGIC := '0'; + SIGNAL n0OOli34 : STD_LOGIC := '0'; + SIGNAL wire_n0OOli34_w_lg_w_lg_q129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0OOli34_w_lg_q129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0OOlO31 : STD_LOGIC := '0'; + SIGNAL n0OOlO32 : STD_LOGIC := '0'; + SIGNAL n0OOOl29 : STD_LOGIC := '0'; + SIGNAL n0OOOl30 : STD_LOGIC := '0'; + SIGNAL n0OOOO27 : STD_LOGIC := '0'; + SIGNAL n0OOOO28 : STD_LOGIC := '0'; + SIGNAL ni100l15 : STD_LOGIC := '0'; + SIGNAL ni100l16 : STD_LOGIC := '0'; + SIGNAL ni10OO13 : STD_LOGIC := '0'; + SIGNAL ni10OO14 : STD_LOGIC := '0'; + SIGNAL ni110l23 : STD_LOGIC := '0'; + SIGNAL ni110l24 : STD_LOGIC := '0'; + SIGNAL ni111l25 : STD_LOGIC := '0'; + SIGNAL ni111l26 : STD_LOGIC := '0'; + SIGNAL ni11ii21 : STD_LOGIC := '0'; + SIGNAL ni11ii22 : STD_LOGIC := '0'; + SIGNAL ni11Oi19 : STD_LOGIC := '0'; + SIGNAL ni11Oi20 : STD_LOGIC := '0'; + SIGNAL ni11OO17 : STD_LOGIC := '0'; + SIGNAL ni11OO18 : STD_LOGIC := '0'; + SIGNAL ni1i0O11 : STD_LOGIC := '0'; + SIGNAL ni1i0O12 : STD_LOGIC := '0'; + SIGNAL ni1ili10 : STD_LOGIC := '0'; + SIGNAL ni1ili9 : STD_LOGIC := '0'; + SIGNAL ni1ilO7 : STD_LOGIC := '0'; + SIGNAL ni1ilO8 : STD_LOGIC := '0'; + SIGNAL ni1l1O5 : STD_LOGIC := '0'; + SIGNAL ni1l1O6 : STD_LOGIC := '0'; + SIGNAL ni1lil3 : STD_LOGIC := '0'; + SIGNAL ni1lil4 : STD_LOGIC := '0'; + SIGNAL ni1lli1 : STD_LOGIC := '0'; + SIGNAL ni1lli2 : STD_LOGIC := '0'; + SIGNAL wire_ni1lli2_w_lg_w_lg_q3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lli2_w_lg_q3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n000i : STD_LOGIC := '0'; + SIGNAL n001O : STD_LOGIC := '0'; + SIGNAL n00ii : STD_LOGIC := '0'; + SIGNAL n01Ol : STD_LOGIC := '0'; + SIGNAL n0liO : STD_LOGIC := '0'; + SIGNAL n0lli : STD_LOGIC := '0'; + SIGNAL n0lll : STD_LOGIC := '0'; + SIGNAL n0llO : STD_LOGIC := '0'; + SIGNAL n0lOi : STD_LOGIC := '0'; + SIGNAL n0lOl : STD_LOGIC := '0'; + SIGNAL n0lOO : STD_LOGIC := '0'; + SIGNAL n0O1i : STD_LOGIC := '0'; + SIGNAL n0O1l : STD_LOGIC := '0'; + SIGNAL n10il : STD_LOGIC := '0'; + SIGNAL n10iO : STD_LOGIC := '0'; + SIGNAL n10li : STD_LOGIC := '0'; + SIGNAL n10ll : STD_LOGIC := '0'; + SIGNAL n10lO : STD_LOGIC := '0'; + SIGNAL n10Oi : STD_LOGIC := '0'; + SIGNAL n10Ol : STD_LOGIC := '0'; + SIGNAL n10OO : STD_LOGIC := '0'; + SIGNAL n11l : STD_LOGIC := '0'; + SIGNAL n1i1i : STD_LOGIC := '0'; + SIGNAL nii00i : STD_LOGIC := '0'; + SIGNAL nii00l : STD_LOGIC := '0'; + SIGNAL nii00O : STD_LOGIC := '0'; + SIGNAL nii0ii : STD_LOGIC := '0'; + SIGNAL nii0il : STD_LOGIC := '0'; + SIGNAL nii0lO : STD_LOGIC := '0'; + SIGNAL nii0Oi : STD_LOGIC := '0'; + SIGNAL niiii : STD_LOGIC := '0'; + SIGNAL niiil : STD_LOGIC := '0'; + SIGNAL niiiO : STD_LOGIC := '0'; + SIGNAL niili : STD_LOGIC := '0'; + SIGNAL niill : STD_LOGIC := '0'; + SIGNAL niilO : STD_LOGIC := '0'; + SIGNAL niiOi : STD_LOGIC := '0'; + SIGNAL niiOl : STD_LOGIC := '0'; + SIGNAL nill0i : STD_LOGIC := '0'; + SIGNAL nill1l : STD_LOGIC := '0'; + SIGNAL nill1O : STD_LOGIC := '0'; + SIGNAL nillil : STD_LOGIC := '0'; + SIGNAL nilliO : STD_LOGIC := '0'; + SIGNAL nillll : STD_LOGIC := '0'; + SIGNAL niO00i : STD_LOGIC := '0'; + SIGNAL niO00l : STD_LOGIC := '0'; + SIGNAL niO00O : STD_LOGIC := '0'; + SIGNAL niO01O : STD_LOGIC := '0'; + SIGNAL niO0ii : STD_LOGIC := '0'; + SIGNAL niO0il : STD_LOGIC := '0'; + SIGNAL niO0iO : STD_LOGIC := '0'; + SIGNAL niO0li : STD_LOGIC := '0'; + SIGNAL niO0ll : STD_LOGIC := '0'; + SIGNAL nl00i : STD_LOGIC := '0'; + SIGNAL nl00l : STD_LOGIC := '0'; + SIGNAL nl00O : STD_LOGIC := '0'; + SIGNAL nl0ii : STD_LOGIC := '0'; + SIGNAL nl0iiO : STD_LOGIC := '0'; + SIGNAL nl0il : STD_LOGIC := '0'; + SIGNAL nl0ili : STD_LOGIC := '0'; + SIGNAL nl0ill : STD_LOGIC := '0'; + SIGNAL nl0ilO : STD_LOGIC := '0'; + SIGNAL nl0iO : STD_LOGIC := '0'; + SIGNAL nl0iOi : STD_LOGIC := '0'; + SIGNAL nl0iOl : STD_LOGIC := '0'; + SIGNAL nl0iOO : STD_LOGIC := '0'; + SIGNAL nl0l1i : STD_LOGIC := '0'; + SIGNAL nl0l1l : STD_LOGIC := '0'; + SIGNAL nl0li : STD_LOGIC := '0'; + SIGNAL nl0ll : STD_LOGIC := '0'; + SIGNAL nl0lO : STD_LOGIC := '0'; + SIGNAL nl1l0O : STD_LOGIC := '0'; + SIGNAL nl1lii : STD_LOGIC := '0'; + SIGNAL nl1lil : STD_LOGIC := '0'; + SIGNAL nl1liO : STD_LOGIC := '0'; + SIGNAL nl1lli : STD_LOGIC := '0'; + SIGNAL nl1lll : STD_LOGIC := '0'; + SIGNAL nl1llO : STD_LOGIC := '0'; + SIGNAL nl1lOi : STD_LOGIC := '0'; + SIGNAL nl1lOl : STD_LOGIC := '0'; + SIGNAL nliOlO : STD_LOGIC := '0'; + SIGNAL nliOOi : STD_LOGIC := '0'; + SIGNAL nliOOl : STD_LOGIC := '0'; + SIGNAL nliOOO : STD_LOGIC := '0'; + SIGNAL nll10i : STD_LOGIC := '0'; + SIGNAL nll11i : STD_LOGIC := '0'; + SIGNAL nll11l : STD_LOGIC := '0'; + SIGNAL nll11O : STD_LOGIC := '0'; + SIGNAL nlllOO : STD_LOGIC := '0'; + SIGNAL nllO0i : STD_LOGIC := '0'; + SIGNAL nllO0l : STD_LOGIC := '0'; + SIGNAL nllO0O : STD_LOGIC := '0'; + SIGNAL nllO1i : STD_LOGIC := '0'; + SIGNAL nllO1l : STD_LOGIC := '0'; + SIGNAL nllO1O : STD_LOGIC := '0'; + SIGNAL nllOii : STD_LOGIC := '0'; + SIGNAL nlO0i : STD_LOGIC := '0'; + SIGNAL nlO0l : STD_LOGIC := '0'; + SIGNAL nlO0O : STD_LOGIC := '0'; + SIGNAL nlOii : STD_LOGIC := '0'; + SIGNAL nlOil : STD_LOGIC := '0'; + SIGNAL nlOiO : STD_LOGIC := '0'; + SIGNAL nlOli : STD_LOGIC := '0'; + SIGNAL nlOll : STD_LOGIC := '0'; + SIGNAL nlOlO : STD_LOGIC := '0'; + SIGNAL wire_n11i_CLRN : STD_LOGIC; + SIGNAL wire_n11i_PRN : STD_LOGIC; + SIGNAL wire_n11i_w_lg_nlO0l282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11i_w_lg_nlO0O281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11i_w_lg_w_lg_w_lg_w_lg_nill1l1w5w6w7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11i_w_lg_w_lg_w_lg_nill1l1w5w6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11i_w_lg_w_lg_nill1l1w5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11i_w_lg_nill1l1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n000l : STD_LOGIC := '0'; + SIGNAL n000O : STD_LOGIC := '0'; + SIGNAL n001i : STD_LOGIC := '0'; + SIGNAL n001l : STD_LOGIC := '0'; + SIGNAL n01OO : STD_LOGIC := '0'; + SIGNAL n10i : STD_LOGIC := '0'; + SIGNAL nii0iO : STD_LOGIC := '0'; + SIGNAL nii0li : STD_LOGIC := '0'; + SIGNAL nii0ll : STD_LOGIC := '0'; + SIGNAL nii0Ol : STD_LOGIC := '0'; + SIGNAL nii0OO : STD_LOGIC := '0'; + SIGNAL niii1i : STD_LOGIC := '0'; + SIGNAL niiOO : STD_LOGIC := '0'; + SIGNAL nill0l : STD_LOGIC := '0'; + SIGNAL nill0O : STD_LOGIC := '0'; + SIGNAL nillii : STD_LOGIC := '0'; + SIGNAL nillli : STD_LOGIC := '0'; + SIGNAL nll10l : STD_LOGIC := '0'; + SIGNAL nllOil : STD_LOGIC := '0'; + SIGNAL wire_n11O_CLRN : STD_LOGIC; + SIGNAL wire_n00il_dataout : STD_LOGIC; + SIGNAL wire_n00iO_dataout : STD_LOGIC; + SIGNAL wire_n00li_dataout : STD_LOGIC; + SIGNAL wire_n00ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol_dataout : STD_LOGIC; + SIGNAL wire_n00OO_dataout : STD_LOGIC; + SIGNAL wire_n010i_dataout : STD_LOGIC; + SIGNAL wire_n010l_dataout : STD_LOGIC; + SIGNAL wire_n010O_dataout : STD_LOGIC; + SIGNAL wire_n011i_dataout : STD_LOGIC; + SIGNAL wire_n011l_dataout : STD_LOGIC; + SIGNAL wire_n011O_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0iii_dataout : STD_LOGIC; + SIGNAL wire_n0iil_dataout : STD_LOGIC; + SIGNAL wire_n0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOO_dataout : STD_LOGIC; + SIGNAL wire_n100i_dataout : STD_LOGIC; + SIGNAL wire_n100l_dataout : STD_LOGIC; + SIGNAL wire_n101i_dataout : STD_LOGIC; + SIGNAL wire_n101l_dataout : STD_LOGIC; + SIGNAL wire_n101O_dataout : STD_LOGIC; + SIGNAL wire_n10l_dataout : STD_LOGIC; + SIGNAL wire_n10O_dataout : STD_LOGIC; + SIGNAL wire_n110i_dataout : STD_LOGIC; + SIGNAL wire_n110l_dataout : STD_LOGIC; + SIGNAL wire_n110O_dataout : STD_LOGIC; + SIGNAL wire_n111i_dataout : STD_LOGIC; + SIGNAL wire_n111l_dataout : STD_LOGIC; + SIGNAL wire_n111O_dataout : STD_LOGIC; + SIGNAL wire_n11ii_dataout : STD_LOGIC; + SIGNAL wire_n11il_dataout : STD_LOGIC; + SIGNAL wire_n11iO_dataout : STD_LOGIC; + SIGNAL wire_n11li_dataout : STD_LOGIC; + SIGNAL wire_n11lO_dataout : STD_LOGIC; + SIGNAL wire_n11Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Ol_dataout : STD_LOGIC; + SIGNAL wire_n11OO_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1iii_dataout : STD_LOGIC; + SIGNAL wire_n1iil_dataout : STD_LOGIC; + SIGNAL wire_n1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1ili_dataout : STD_LOGIC; + SIGNAL wire_n1ill_dataout : STD_LOGIC; + SIGNAL wire_n1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1lii_dataout : STD_LOGIC; + SIGNAL wire_n1lil_dataout : STD_LOGIC; + SIGNAL wire_n1liO_dataout : STD_LOGIC; + SIGNAL wire_n1lli_dataout : STD_LOGIC; + SIGNAL wire_n1lll_dataout : STD_LOGIC; + SIGNAL wire_n1llO_dataout : STD_LOGIC; + SIGNAL wire_n1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni_dataout : STD_LOGIC; + SIGNAL wire_ni00i_dataout : STD_LOGIC; + SIGNAL wire_ni00l_dataout : STD_LOGIC; + SIGNAL wire_ni00O_dataout : STD_LOGIC; + SIGNAL wire_ni01i_dataout : STD_LOGIC; + SIGNAL wire_ni01l_dataout : STD_LOGIC; + SIGNAL wire_ni01O_dataout : STD_LOGIC; + SIGNAL wire_ni0i_dataout : STD_LOGIC; + SIGNAL wire_ni0i_w_lg_dataout23w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0il_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l_w_lg_dataout27w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O_w_lg_dataout237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0OO_dataout : STD_LOGIC; + SIGNAL wire_ni10i_dataout : STD_LOGIC; + SIGNAL wire_ni10l_dataout : STD_LOGIC; + SIGNAL wire_ni10O_dataout : STD_LOGIC; + SIGNAL wire_ni11i_dataout : STD_LOGIC; + SIGNAL wire_ni11l_dataout : STD_LOGIC; + SIGNAL wire_ni11O_dataout : STD_LOGIC; + SIGNAL wire_ni1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1il_dataout : STD_LOGIC; + SIGNAL wire_ni1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1li_dataout : STD_LOGIC; + SIGNAL wire_ni1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O_w_lg_dataout16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1OO_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niii0i_dataout : STD_LOGIC; + SIGNAL wire_niii0l_dataout : STD_LOGIC; + SIGNAL wire_niii0O_dataout : STD_LOGIC; + SIGNAL wire_niii1l_dataout : STD_LOGIC; + SIGNAL wire_niii1O_dataout : STD_LOGIC; + SIGNAL wire_niiiii_dataout : STD_LOGIC; + SIGNAL wire_niiiil_dataout : STD_LOGIC; + SIGNAL wire_niiiiO_dataout : STD_LOGIC; + SIGNAL wire_niiili_dataout : STD_LOGIC; + SIGNAL wire_niiill_dataout : STD_LOGIC; + SIGNAL wire_niiilO_dataout : STD_LOGIC; + SIGNAL wire_niiiOi_dataout : STD_LOGIC; + SIGNAL wire_niiiOl_dataout : STD_LOGIC; + SIGNAL wire_niiiOO_dataout : STD_LOGIC; + SIGNAL wire_niil0i_dataout : STD_LOGIC; + SIGNAL wire_niil0l_dataout : STD_LOGIC; + SIGNAL wire_niil0O_dataout : STD_LOGIC; + SIGNAL wire_niil1i_dataout : STD_LOGIC; + SIGNAL wire_niil1l_dataout : STD_LOGIC; + SIGNAL wire_niil1O_dataout : STD_LOGIC; + SIGNAL wire_niilii_dataout : STD_LOGIC; + SIGNAL wire_niilil_dataout : STD_LOGIC; + SIGNAL wire_niiliO_dataout : STD_LOGIC; + SIGNAL wire_niilli_dataout : STD_LOGIC; + SIGNAL wire_niilll_dataout : STD_LOGIC; + SIGNAL wire_niillO_dataout : STD_LOGIC; + SIGNAL wire_niilOi_dataout : STD_LOGIC; + SIGNAL wire_niilOl_dataout : STD_LOGIC; + SIGNAL wire_niilOO_dataout : STD_LOGIC; + SIGNAL wire_niiO0i_dataout : STD_LOGIC; + SIGNAL wire_niiO0l_dataout : STD_LOGIC; + SIGNAL wire_niiO0O_dataout : STD_LOGIC; + SIGNAL wire_niiO1i_dataout : STD_LOGIC; + SIGNAL wire_niiO1l_dataout : STD_LOGIC; + SIGNAL wire_niiO1O_dataout : STD_LOGIC; + SIGNAL wire_niiOii_dataout : STD_LOGIC; + SIGNAL wire_niiOil_dataout : STD_LOGIC; + SIGNAL wire_niiOiO_dataout : STD_LOGIC; + SIGNAL wire_niiOli_dataout : STD_LOGIC; + SIGNAL wire_niiOll_dataout : STD_LOGIC; + SIGNAL wire_niiOlO_dataout : STD_LOGIC; + SIGNAL wire_niiOOi_dataout : STD_LOGIC; + SIGNAL wire_niiOOl_dataout : STD_LOGIC; + SIGNAL wire_niiOOO_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nil00i_dataout : STD_LOGIC; + SIGNAL wire_nil00l_dataout : STD_LOGIC; + SIGNAL wire_nil00O_dataout : STD_LOGIC; + SIGNAL wire_nil01i_dataout : STD_LOGIC; + SIGNAL wire_nil01l_dataout : STD_LOGIC; + SIGNAL wire_nil01O_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0ii_dataout : STD_LOGIC; + SIGNAL wire_nil0il_dataout : STD_LOGIC; + SIGNAL wire_nil0iO_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0li_dataout : STD_LOGIC; + SIGNAL wire_nil0ll_dataout : STD_LOGIC; + SIGNAL wire_nil0lO_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0OO_dataout : STD_LOGIC; + SIGNAL wire_nil10i_dataout : STD_LOGIC; + SIGNAL wire_nil10l_dataout : STD_LOGIC; + SIGNAL wire_nil10O_dataout : STD_LOGIC; + SIGNAL wire_nil11i_dataout : STD_LOGIC; + SIGNAL wire_nil11l_dataout : STD_LOGIC; + SIGNAL wire_nil11O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1ii_dataout : STD_LOGIC; + SIGNAL wire_nil1il_dataout : STD_LOGIC; + SIGNAL wire_nil1iO_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1li_dataout : STD_LOGIC; + SIGNAL wire_nil1ll_dataout : STD_LOGIC; + SIGNAL wire_nil1lO_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1OO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nili0i_dataout : STD_LOGIC; + SIGNAL wire_nili0l_dataout : STD_LOGIC; + SIGNAL wire_nili0O_dataout : STD_LOGIC; + SIGNAL wire_nili1i_dataout : STD_LOGIC; + SIGNAL wire_nili1l_dataout : STD_LOGIC; + SIGNAL wire_nili1O_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_niliii_dataout : STD_LOGIC; + SIGNAL wire_niliil_dataout : STD_LOGIC; + SIGNAL wire_niliiO_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_nilili_dataout : STD_LOGIC; + SIGNAL wire_nilill_dataout : STD_LOGIC; + SIGNAL wire_nililO_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_niliOi_dataout : STD_LOGIC; + SIGNAL wire_niliOl_dataout : STD_LOGIC; + SIGNAL wire_niliOO_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nill1i_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nilllO_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nillOi_dataout : STD_LOGIC; + SIGNAL wire_nillOl_dataout : STD_LOGIC; + SIGNAL wire_nillOO_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_nilO0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOii_dataout : STD_LOGIC; + SIGNAL wire_nilOil_dataout : STD_LOGIC; + SIGNAL wire_nilOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOli_dataout : STD_LOGIC; + SIGNAL wire_nilOll_dataout : STD_LOGIC; + SIGNAL wire_nilOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niO01i_dataout : STD_LOGIC; + SIGNAL wire_niO01l_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0lO_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0OO_dataout : STD_LOGIC; + SIGNAL wire_niO10i_dataout : STD_LOGIC; + SIGNAL wire_niO10l_dataout : STD_LOGIC; + SIGNAL wire_niO10O_dataout : STD_LOGIC; + SIGNAL wire_niO11i_dataout : STD_LOGIC; + SIGNAL wire_niO11l_dataout : STD_LOGIC; + SIGNAL wire_niO11O_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1ii_dataout : STD_LOGIC; + SIGNAL wire_niO1il_dataout : STD_LOGIC; + SIGNAL wire_niO1iO_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1li_dataout : STD_LOGIC; + SIGNAL wire_niO1ll_dataout : STD_LOGIC; + SIGNAL wire_niO1lO_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOii_dataout : STD_LOGIC; + SIGNAL wire_niOiii_dataout : STD_LOGIC; + SIGNAL wire_niOiil_dataout : STD_LOGIC; + SIGNAL wire_niOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOil_dataout : STD_LOGIC; + SIGNAL wire_niOili_dataout : STD_LOGIC; + SIGNAL wire_niOill_dataout : STD_LOGIC; + SIGNAL wire_niOilO_dataout : STD_LOGIC; + SIGNAL wire_niOiO_dataout : STD_LOGIC; + SIGNAL wire_niOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOlii_dataout : STD_LOGIC; + SIGNAL wire_niOlil_dataout : STD_LOGIC; + SIGNAL wire_niOliO_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlli_dataout : STD_LOGIC; + SIGNAL wire_niOlll_dataout : STD_LOGIC; + SIGNAL wire_niOllO_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOl_dataout : STD_LOGIC; + SIGNAL wire_niOlOO_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_niOO0i_dataout : STD_LOGIC; + SIGNAL wire_niOO0l_dataout : STD_LOGIC; + SIGNAL wire_niOO0O_dataout : STD_LOGIC; + SIGNAL wire_niOO1i_dataout : STD_LOGIC; + SIGNAL wire_niOO1l_dataout : STD_LOGIC; + SIGNAL wire_niOO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOii_dataout : STD_LOGIC; + SIGNAL wire_niOOil_dataout : STD_LOGIC; + SIGNAL wire_niOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOli_dataout : STD_LOGIC; + SIGNAL wire_niOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl_dataout : STD_LOGIC; + SIGNAL wire_nl000i_dataout : STD_LOGIC; + SIGNAL wire_nl000l_dataout : STD_LOGIC; + SIGNAL wire_nl000O_dataout : STD_LOGIC; + SIGNAL wire_nl001i_dataout : STD_LOGIC; + SIGNAL wire_nl001l_dataout : STD_LOGIC; + SIGNAL wire_nl001O_dataout : STD_LOGIC; + SIGNAL wire_nl00ii_dataout : STD_LOGIC; + SIGNAL wire_nl00il_dataout : STD_LOGIC; + SIGNAL wire_nl00iO_dataout : STD_LOGIC; + SIGNAL wire_nl00li_dataout : STD_LOGIC; + SIGNAL wire_nl00ll_dataout : STD_LOGIC; + SIGNAL wire_nl00lO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00OO_dataout : STD_LOGIC; + SIGNAL wire_nl010i_dataout : STD_LOGIC; + SIGNAL wire_nl010l_dataout : STD_LOGIC; + SIGNAL wire_nl010O_dataout : STD_LOGIC; + SIGNAL wire_nl011i_dataout : STD_LOGIC; + SIGNAL wire_nl011l_dataout : STD_LOGIC; + SIGNAL wire_nl011O_dataout : STD_LOGIC; + SIGNAL wire_nl01i_dataout : STD_LOGIC; + SIGNAL wire_nl01ii_dataout : STD_LOGIC; + SIGNAL wire_nl01il_dataout : STD_LOGIC; + SIGNAL wire_nl01iO_dataout : STD_LOGIC; + SIGNAL wire_nl01l_dataout : STD_LOGIC; + SIGNAL wire_nl01li_dataout : STD_LOGIC; + SIGNAL wire_nl01ll_dataout : STD_LOGIC; + SIGNAL wire_nl01lO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl100i_dataout : STD_LOGIC; + SIGNAL wire_nl100l_dataout : STD_LOGIC; + SIGNAL wire_nl100O_dataout : STD_LOGIC; + SIGNAL wire_nl101i_dataout : STD_LOGIC; + SIGNAL wire_nl101l_dataout : STD_LOGIC; + SIGNAL wire_nl101O_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl10ii_dataout : STD_LOGIC; + SIGNAL wire_nl10il_dataout : STD_LOGIC; + SIGNAL wire_nl10iO_dataout : STD_LOGIC; + SIGNAL wire_nl10l_dataout : STD_LOGIC; + SIGNAL wire_nl10li_dataout : STD_LOGIC; + SIGNAL wire_nl10ll_dataout : STD_LOGIC; + SIGNAL wire_nl10lO_dataout : STD_LOGIC; + SIGNAL wire_nl10O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10OO_dataout : STD_LOGIC; + SIGNAL wire_nl110i_dataout : STD_LOGIC; + SIGNAL wire_nl110l_dataout : STD_LOGIC; + SIGNAL wire_nl110O_dataout : STD_LOGIC; + SIGNAL wire_nl111i_dataout : STD_LOGIC; + SIGNAL wire_nl111l_dataout : STD_LOGIC; + SIGNAL wire_nl111O_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11ii_dataout : STD_LOGIC; + SIGNAL wire_nl11il_dataout : STD_LOGIC; + SIGNAL wire_nl11iO_dataout : STD_LOGIC; + SIGNAL wire_nl11l_dataout : STD_LOGIC; + SIGNAL wire_nl11li_dataout : STD_LOGIC; + SIGNAL wire_nl11ll_dataout : STD_LOGIC; + SIGNAL wire_nl11lO_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nli00i_dataout : STD_LOGIC; + SIGNAL wire_nli00l_dataout : STD_LOGIC; + SIGNAL wire_nli00O_dataout : STD_LOGIC; + SIGNAL wire_nli01i_dataout : STD_LOGIC; + SIGNAL wire_nli01l_dataout : STD_LOGIC; + SIGNAL wire_nli01O_dataout : STD_LOGIC; + SIGNAL wire_nli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0il_dataout : STD_LOGIC; + SIGNAL wire_nli0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0OO_dataout : STD_LOGIC; + SIGNAL wire_nli10i_dataout : STD_LOGIC; + SIGNAL wire_nli10l_dataout : STD_LOGIC; + SIGNAL wire_nli10O_dataout : STD_LOGIC; + SIGNAL wire_nli11i_dataout : STD_LOGIC; + SIGNAL wire_nli11l_dataout : STD_LOGIC; + SIGNAL wire_nli11O_dataout : STD_LOGIC; + SIGNAL wire_nli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1ii_dataout : STD_LOGIC; + SIGNAL wire_nli1il_dataout : STD_LOGIC; + SIGNAL wire_nli1iO_dataout : STD_LOGIC; + SIGNAL wire_nli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1li_dataout : STD_LOGIC; + SIGNAL wire_nli1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1O_dataout : STD_LOGIC; + SIGNAL wire_nli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlii0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1O_dataout : STD_LOGIC; + SIGNAL wire_nliii_dataout : STD_LOGIC; + SIGNAL wire_nliiii_dataout : STD_LOGIC; + SIGNAL wire_nliiil_dataout : STD_LOGIC; + SIGNAL wire_nliiiO_dataout : STD_LOGIC; + SIGNAL wire_nliil_dataout : STD_LOGIC; + SIGNAL wire_nliili_dataout : STD_LOGIC; + SIGNAL wire_nliill_dataout : STD_LOGIC; + SIGNAL wire_nliilO_dataout : STD_LOGIC; + SIGNAL wire_nliiO_dataout : STD_LOGIC; + SIGNAL wire_nliiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nlil0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O_dataout : STD_LOGIC; + SIGNAL wire_nlili_dataout : STD_LOGIC; + SIGNAL wire_nlilii_dataout : STD_LOGIC; + SIGNAL wire_nlilil_dataout : STD_LOGIC; + SIGNAL wire_nliliO_dataout : STD_LOGIC; + SIGNAL wire_nlill_dataout : STD_LOGIC; + SIGNAL wire_nlilli_dataout : STD_LOGIC; + SIGNAL wire_nlilll_dataout : STD_LOGIC; + SIGNAL wire_nlillO_dataout : STD_LOGIC; + SIGNAL wire_nlilO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOO_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nliO0i_dataout : STD_LOGIC; + SIGNAL wire_nliO0l_dataout : STD_LOGIC; + SIGNAL wire_nliO0O_dataout : STD_LOGIC; + SIGNAL wire_nliO1i_dataout : STD_LOGIC; + SIGNAL wire_nliO1l_dataout : STD_LOGIC; + SIGNAL wire_nliO1O_dataout : STD_LOGIC; + SIGNAL wire_nliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOii_dataout : STD_LOGIC; + SIGNAL wire_nliOil_dataout : STD_LOGIC; + SIGNAL wire_nliOiO_dataout : STD_LOGIC; + SIGNAL wire_nliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOli_dataout : STD_LOGIC; + SIGNAL wire_nliOll_dataout : STD_LOGIC; + SIGNAL wire_nliOO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nll00i_dataout : STD_LOGIC; + SIGNAL wire_nll00l_dataout : STD_LOGIC; + SIGNAL wire_nll00O_dataout : STD_LOGIC; + SIGNAL wire_nll01i_dataout : STD_LOGIC; + SIGNAL wire_nll01l_dataout : STD_LOGIC; + SIGNAL wire_nll01O_dataout : STD_LOGIC; + SIGNAL wire_nll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0il_dataout : STD_LOGIC; + SIGNAL wire_nll0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0li_dataout : STD_LOGIC; + SIGNAL wire_nll0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0OO_dataout : STD_LOGIC; + SIGNAL wire_nll10O_dataout : STD_LOGIC; + SIGNAL wire_nll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1il_dataout : STD_LOGIC; + SIGNAL wire_nll1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1li_dataout : STD_LOGIC; + SIGNAL wire_nll1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1O_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlli0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O_dataout : STD_LOGIC; + SIGNAL wire_nlli1i_dataout : STD_LOGIC; + SIGNAL wire_nlli1l_dataout : STD_LOGIC; + SIGNAL wire_nlli1O_dataout : STD_LOGIC; + SIGNAL wire_nllii_dataout : STD_LOGIC; + SIGNAL wire_nlliii_dataout : STD_LOGIC; + SIGNAL wire_nlliil_dataout : STD_LOGIC; + SIGNAL wire_nlliiO_dataout : STD_LOGIC; + SIGNAL wire_nllil_dataout : STD_LOGIC; + SIGNAL wire_nllili_dataout : STD_LOGIC; + SIGNAL wire_nllill_dataout : STD_LOGIC; + SIGNAL wire_nllilO_dataout : STD_LOGIC; + SIGNAL wire_nlliO_dataout : STD_LOGIC; + SIGNAL wire_nlliOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOO_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nlll0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O_dataout : STD_LOGIC; + SIGNAL wire_nlllii_dataout : STD_LOGIC; + SIGNAL wire_nlllil_dataout : STD_LOGIC; + SIGNAL wire_nllliO_dataout : STD_LOGIC; + SIGNAL wire_nlllli_dataout : STD_LOGIC; + SIGNAL wire_nlllll_dataout : STD_LOGIC; + SIGNAL wire_nllllO_dataout : STD_LOGIC; + SIGNAL wire_nlllOi_dataout : STD_LOGIC; + SIGNAL wire_nlllOl_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nllOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOli_dataout : STD_LOGIC; + SIGNAL wire_nllOll_dataout : STD_LOGIC; + SIGNAL wire_nllOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO11l_dataout : STD_LOGIC; + SIGNAL wire_nlO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOili_dataout : STD_LOGIC; + SIGNAL wire_nlOill_dataout : STD_LOGIC; + SIGNAL wire_nlOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO_dataout : STD_LOGIC; + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_nllOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOi_o : STD_LOGIC; + SIGNAL wire_nllOi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOl_o : STD_LOGIC; + SIGNAL wire_nllOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOO_w_lg_o126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllOO_o : STD_LOGIC; + SIGNAL wire_nllOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_ctl_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_ctl_range24w25w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_ctl_range28w29w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_ctl_range54w238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range236w285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range218w301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range202w309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range227w293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0OliO228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0OlOi219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_n0OO1i205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni101O68w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni10ii62w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni10iO60w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni10ll58w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni10Oi56w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni110i128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni111O120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni11iO95w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni11li92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni11ll89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni11lO87w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni1i0i45w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni1i1l48w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni1iil38w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_soft_reset116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range217w300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range235w284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range201w308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dec_data_range226w292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_ni111O120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_ni1i0l74w75w76w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_ni1i0l74w75w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni1i0l74w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0Oill : STD_LOGIC; + SIGNAL n0OilO : STD_LOGIC; + SIGNAL n0OiOi : STD_LOGIC; + SIGNAL n0OiOl : STD_LOGIC; + SIGNAL n0OiOO : STD_LOGIC; + SIGNAL n0Ol0i : STD_LOGIC; + SIGNAL n0Ol0l : STD_LOGIC; + SIGNAL n0Ol0O : STD_LOGIC; + SIGNAL n0Ol1i : STD_LOGIC; + SIGNAL n0Ol1l : STD_LOGIC; + SIGNAL n0Ol1O : STD_LOGIC; + SIGNAL n0Olii : STD_LOGIC; + SIGNAL n0Olil : STD_LOGIC; + SIGNAL n0OliO : STD_LOGIC; + SIGNAL n0OllO : STD_LOGIC; + SIGNAL n0OlOi : STD_LOGIC; + SIGNAL n0OO0i : STD_LOGIC; + SIGNAL n0OO1i : STD_LOGIC; + SIGNAL n0OOii : STD_LOGIC; + SIGNAL n0OOll : STD_LOGIC; + SIGNAL ni100i : STD_LOGIC; + SIGNAL ni101l : STD_LOGIC; + SIGNAL ni101O : STD_LOGIC; + SIGNAL ni10ii : STD_LOGIC; + SIGNAL ni10il : STD_LOGIC; + SIGNAL ni10iO : STD_LOGIC; + SIGNAL ni10li : STD_LOGIC; + SIGNAL ni10ll : STD_LOGIC; + SIGNAL ni10lO : STD_LOGIC; + SIGNAL ni10Oi : STD_LOGIC; + SIGNAL ni10Ol : STD_LOGIC; + SIGNAL ni110i : STD_LOGIC; + SIGNAL ni111i : STD_LOGIC; + SIGNAL ni111O : STD_LOGIC; + SIGNAL ni11iO : STD_LOGIC; + SIGNAL ni11li : STD_LOGIC; + SIGNAL ni11ll : STD_LOGIC; + SIGNAL ni11lO : STD_LOGIC; + SIGNAL ni1i0i : STD_LOGIC; + SIGNAL ni1i0l : STD_LOGIC; + SIGNAL ni1i1l : STD_LOGIC; + SIGNAL ni1i1O : STD_LOGIC; + SIGNAL ni1iil : STD_LOGIC; + SIGNAL ni1iiO : STD_LOGIC; + SIGNAL ni1iOl : STD_LOGIC; + SIGNAL ni1iOO : STD_LOGIC; + SIGNAL ni1l0l : STD_LOGIC; + SIGNAL ni1l0O : STD_LOGIC; + SIGNAL ni1l1i : STD_LOGIC; + SIGNAL ni1l1l : STD_LOGIC; + SIGNAL ni1lii : STD_LOGIC; + SIGNAL wire_w_dec_ctl_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_ctl_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_ctl_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_ctl_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dec_data_range226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_w_dec_ctl_range17w18w(0) <= wire_w_dec_ctl_range17w(0) AND ni1l0l; + wire_w_lg_w_dec_ctl_range24w25w(0) <= wire_w_dec_ctl_range24w(0) AND ni1l1i; + wire_w_lg_w_dec_ctl_range28w29w(0) <= wire_w_dec_ctl_range28w(0) AND ni1iOl; + wire_w_lg_w_dec_ctl_range54w238w(0) <= wire_w_dec_ctl_range54w(0) AND n0Oill; + wire_w_lg_w_dec_data_range236w285w(0) <= wire_w_dec_data_range236w(0) AND wire_w_lg_w_dec_data_range235w284w(0); + wire_w_lg_w_dec_data_range218w301w(0) <= wire_w_dec_data_range218w(0) AND wire_w_lg_w_dec_data_range217w300w(0); + wire_w_lg_w_dec_data_range202w309w(0) <= wire_w_dec_data_range202w(0) AND wire_w_lg_w_dec_data_range201w308w(0); + wire_w_lg_w_dec_data_range227w293w(0) <= wire_w_dec_data_range227w(0) AND wire_w_lg_w_dec_data_range226w292w(0); + wire_w_lg_n0OliO228w(0) <= NOT n0OliO; + wire_w_lg_n0OlOi219w(0) <= NOT n0OlOi; + wire_w_lg_n0OO1i205w(0) <= NOT n0OO1i; + wire_w_lg_ni101O68w(0) <= NOT ni101O; + wire_w_lg_ni10ii62w(0) <= NOT ni10ii; + wire_w_lg_ni10iO60w(0) <= NOT ni10iO; + wire_w_lg_ni10ll58w(0) <= NOT ni10ll; + wire_w_lg_ni10Oi56w(0) <= NOT ni10Oi; + wire_w_lg_ni110i128w(0) <= NOT ni110i; + wire_w_lg_ni111O120w(0) <= NOT ni111O; + wire_w_lg_ni11iO95w(0) <= NOT ni11iO; + wire_w_lg_ni11li92w(0) <= NOT ni11li; + wire_w_lg_ni11ll89w(0) <= NOT ni11ll; + wire_w_lg_ni11lO87w(0) <= NOT ni11lO; + wire_w_lg_ni1i0i45w(0) <= NOT ni1i0i; + wire_w_lg_ni1i1l48w(0) <= NOT ni1i1l; + wire_w_lg_ni1iil38w(0) <= NOT ni1iil; + wire_w_lg_soft_reset116w(0) <= NOT soft_reset; + wire_w_lg_w_dec_data_range217w300w(0) <= NOT wire_w_dec_data_range217w(0); + wire_w_lg_w_dec_data_range235w284w(0) <= NOT wire_w_dec_data_range235w(0); + wire_w_lg_w_dec_data_range201w308w(0) <= NOT wire_w_dec_data_range201w(0); + wire_w_lg_w_dec_data_range226w292w(0) <= NOT wire_w_dec_data_range226w(0); + wire_w_lg_w_lg_ni111O120w121w(0) <= wire_w_lg_ni111O120w(0) OR nlOii; + wire_w_lg_w_lg_w_lg_ni1i0l74w75w76w(0) <= wire_w_lg_w_lg_ni1i0l74w75w(0) OR ni10lO; + wire_w_lg_w_lg_ni1i0l74w75w(0) <= wire_w_lg_ni1i0l74w(0) OR ni10Ol; + wire_w_lg_ni1i0l74w(0) <= ni1i0l OR ni1i1O; + curr_state <= ( nlO0O & nlO0l); + n0Oill <= ((((((wire_w_lg_w_dec_data_range202w309w(0) AND dec_data(26)) AND dec_data(27)) AND dec_data(28)) AND dec_data(29)) AND dec_data(30)) AND dec_data(31)); + n0OilO <= (wire_n11i_w_lg_nlO0O281w(0) AND nlO0l); + n0OiOi <= (ni110i AND (NOT (((wire_ni0O_dataout OR wire_ni0l_dataout) OR wire_ni0i_dataout) OR wire_ni1O_dataout))); + n0OiOl <= (ni1iiO OR n0OOii); + n0OiOO <= (wire_ni0O_dataout OR (ni10lO AND ni101l)); + n0Ol0i <= (ni1l1l OR ni110i); + n0Ol0l <= (wire_ni1O_dataout OR (ni1i0l AND ni10li)); + n0Ol0O <= ((nii00l OR nii00i) OR nii00O); + n0Ol1i <= (nlO0O AND nlO0l); + n0Ol1l <= (ni1iiO OR n0Ol1O); + n0Ol1O <= (ni1iOO OR n0Ol0i); + n0Olii <= (wire_ni0i_dataout OR (ni1i1O AND ni10il)); + n0Olil <= (nii00O OR nii00i); + n0OliO <= ((wire_ni0i_dataout OR ni1i1O) OR (NOT (n0Olli46 XOR n0Olli45))); + n0OllO <= (wire_ni0l_dataout OR (ni10Ol AND ni100i)); + n0OlOi <= ((wire_ni0l_dataout OR ni10Ol) OR (NOT (n0OlOl44 XOR n0OlOl43))); + n0OO0i <= ((ni1iiO OR n0OOii) OR (NOT (n0OO0l40 XOR n0OO0l39))); + n0OO1i <= ((wire_ni0O_dataout OR ni10lO) OR (NOT (n0OO1l42 XOR n0OO1l41))); + n0OOii <= (ni1l1l OR ni1iOO); + n0OOll <= (wire_w_lg_ni111O120w(0) OR nl0lO); + ni100i <= (((NOT dec_ctl(2)) OR wire_w_lg_ni10ii62w(0)) OR (NOT (ni100l16 XOR ni100l15))); + ni101l <= ((NOT dec_ctl(3)) OR wire_w_lg_ni101O68w(0)); + ni101O <= ((((((((NOT dec_data(24)) AND wire_w_lg_w_dec_data_range201w308w(0)) AND dec_data(26)) AND dec_data(27)) AND dec_data(28)) AND dec_data(29)) AND dec_data(30)) AND (NOT dec_data(31))); + ni10ii <= ((((((((NOT dec_data(16)) AND wire_w_lg_w_dec_data_range217w300w(0)) AND dec_data(18)) AND dec_data(19)) AND dec_data(20)) AND dec_data(21)) AND dec_data(22)) AND (NOT dec_data(23))); + ni10il <= ((NOT dec_ctl(1)) OR wire_w_lg_ni10iO60w(0)); + ni10iO <= ((((((((NOT dec_data(8)) AND wire_w_lg_w_dec_data_range226w292w(0)) AND dec_data(10)) AND dec_data(11)) AND dec_data(12)) AND dec_data(13)) AND dec_data(14)) AND (NOT dec_data(15))); + ni10li <= ((NOT dec_ctl(0)) OR wire_w_lg_ni10ll58w(0)); + ni10ll <= ((((((((NOT dec_data(0)) AND wire_w_lg_w_dec_data_range235w284w(0)) AND dec_data(2)) AND dec_data(3)) AND dec_data(4)) AND dec_data(5)) AND dec_data(6)) AND (NOT dec_data(7))); + ni10lO <= ((NOT dec_ctl(3)) OR wire_w_lg_ni10Oi56w(0)); + ni10Oi <= ((((((((NOT dec_data(24)) AND wire_w_lg_w_dec_data_range201w308w(0)) AND dec_data(26)) AND dec_data(27)) AND dec_data(28)) AND dec_data(29)) AND (NOT dec_data(30))) AND dec_data(31)); + ni10Ol <= (((NOT dec_ctl(2)) OR wire_w_lg_ni1i1l48w(0)) OR (NOT (ni10OO14 XOR ni10OO13))); + ni110i <= ((((NOT (((ni10li OR ni10il) OR ni100i) OR ni101l)) OR (NOT (wire_w_lg_w_lg_w_lg_ni1i0l74w75w76w(0) OR (NOT (ni11OO18 XOR ni11OO17))))) OR (NOT (ni11Oi20 XOR ni11Oi19))) OR (NOT ((((((NOT dec_ctl(0)) OR wire_w_lg_ni11lO87w(0)) OR ((NOT dec_ctl(1)) OR wire_w_lg_ni11ll89w(0))) OR ((NOT dec_ctl(2)) OR wire_w_lg_ni11li92w(0))) OR (((NOT dec_ctl(3)) OR wire_w_lg_ni11iO95w(0)) OR (NOT (ni11ii22 XOR ni11ii21)))) OR (NOT (ni110l24 XOR ni110l23))))); + ni111i <= '1'; + ni111O <= (((dec_data_valid(0) AND dec_data_valid(1)) AND dec_data_valid(2)) AND dec_data_valid(3)); + ni11iO <= ((((((((NOT dec_data(24)) AND wire_w_lg_w_dec_data_range201w308w(0)) AND dec_data(26)) AND dec_data(27)) AND dec_data(28)) AND (NOT dec_data(29))) AND (NOT dec_data(30))) AND (NOT dec_data(31))); + ni11li <= ((((((((NOT dec_data(16)) AND wire_w_lg_w_dec_data_range217w300w(0)) AND dec_data(18)) AND dec_data(19)) AND dec_data(20)) AND (NOT dec_data(21))) AND (NOT dec_data(22))) AND (NOT dec_data(23))); + ni11ll <= ((((((((NOT dec_data(8)) AND wire_w_lg_w_dec_data_range226w292w(0)) AND dec_data(10)) AND dec_data(11)) AND dec_data(12)) AND (NOT dec_data(13))) AND (NOT dec_data(14))) AND (NOT dec_data(15))); + ni11lO <= ((((((((NOT dec_data(0)) AND wire_w_lg_w_dec_data_range235w284w(0)) AND dec_data(2)) AND dec_data(3)) AND dec_data(4)) AND (NOT dec_data(5))) AND (NOT dec_data(6))) AND (NOT dec_data(7))); + ni1i0i <= ((((((((NOT dec_data(8)) AND wire_w_lg_w_dec_data_range226w292w(0)) AND dec_data(10)) AND dec_data(11)) AND dec_data(12)) AND dec_data(13)) AND (NOT dec_data(14))) AND dec_data(15)); + ni1i0l <= (((NOT dec_ctl(0)) OR wire_w_lg_ni1iil38w(0)) OR (NOT (ni1i0O12 XOR ni1i0O11))); + ni1i1l <= ((((((((NOT dec_data(16)) AND wire_w_lg_w_dec_data_range217w300w(0)) AND dec_data(18)) AND dec_data(19)) AND dec_data(20)) AND dec_data(21)) AND (NOT dec_data(22))) AND dec_data(23)); + ni1i1O <= ((NOT dec_ctl(1)) OR wire_w_lg_ni1i0i45w(0)); + ni1iil <= ((((((((NOT dec_data(0)) AND wire_w_lg_w_dec_data_range235w284w(0)) AND dec_data(2)) AND dec_data(3)) AND dec_data(4)) AND dec_data(5)) AND (NOT dec_data(6))) AND dec_data(7)); + ni1iiO <= ((wire_ni0l_w_lg_dataout27w(0) AND (wire_w_lg_w_dec_ctl_range28w29w(0) AND (ni1ilO8 XOR ni1ilO7))) AND (ni1ili10 XOR ni1ili9)); + ni1iOl <= ((((((wire_w_lg_w_dec_data_range218w301w(0) AND dec_data(18)) AND dec_data(19)) AND dec_data(20)) AND dec_data(21)) AND dec_data(22)) AND dec_data(23)); + ni1iOO <= (wire_ni0i_w_lg_dataout23w(0) AND wire_w_lg_w_dec_ctl_range24w25w(0)); + ni1l0l <= ((((((wire_w_lg_w_dec_data_range236w285w(0) AND dec_data(2)) AND dec_data(3)) AND dec_data(4)) AND dec_data(5)) AND dec_data(6)) AND dec_data(7)); + ni1l0O <= (wire_n11i_w_lg_nlO0O281w(0) AND wire_n11i_w_lg_nlO0l282w(0)); + ni1l1i <= ((((((wire_w_lg_w_dec_data_range227w293w(0) AND dec_data(10)) AND dec_data(11)) AND dec_data(12)) AND dec_data(13)) AND dec_data(14)) AND dec_data(15)); + ni1l1l <= ((wire_ni1O_w_lg_dataout16w(0) AND wire_w_lg_w_dec_ctl_range17w18w(0)) AND (ni1l1O6 XOR ni1l1O5)); + ni1lii <= (wire_n11i_w_lg_w_lg_w_lg_w_lg_nill1l1w5w6w7w(0) OR (NOT (ni1lil4 XOR ni1lil3))); + rx_ctl_rs <= ( nl0ll & niiOl & n0O1i & n000O); + rx_data_rs <= ( nl0li & nl0iO & nl0il & nl0ii & nl00O & nl00l & nl00i & niiOO & niiOi & niilO & niill & niili & niiiO & niiil & niiii & n0O1l & n0lOO & n0lOl & n0lOi & n0llO & n0lll & n0lli & n0liO & n00ii & n000l & n000i & n001O & n001l & n001i & n01OO & n01Ol & n1i1i); + rx_local_fault <= n10i; + xs_link_status <= nlOll; + wire_w_dec_ctl_range17w(0) <= dec_ctl(0); + wire_w_dec_ctl_range24w(0) <= dec_ctl(1); + wire_w_dec_ctl_range28w(0) <= dec_ctl(2); + wire_w_dec_ctl_range54w(0) <= dec_ctl(3); + wire_w_dec_data_range236w(0) <= dec_data(0); + wire_w_dec_data_range218w(0) <= dec_data(16); + wire_w_dec_data_range217w(0) <= dec_data(17); + wire_w_dec_data_range235w(0) <= dec_data(1); + wire_w_dec_data_range202w(0) <= dec_data(24); + wire_w_dec_data_range201w(0) <= dec_data(25); + wire_w_dec_data_range227w(0) <= dec_data(8); + wire_w_dec_data_range226w(0) <= dec_data(9); + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Olli45 <= n0Olli46; + END IF; + if (now = 0 ns) then + n0Olli45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0Olli46 <= n0Olli45; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OlOl43 <= n0OlOl44; + END IF; + if (now = 0 ns) then + n0OlOl43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OlOl44 <= n0OlOl43; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO0l39 <= n0OO0l40; + END IF; + if (now = 0 ns) then + n0OO0l39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO0l40 <= n0OO0l39; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO1l41 <= n0OO1l42; + END IF; + if (now = 0 ns) then + n0OO1l41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OO1l42 <= n0OO1l41; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOil37 <= n0OOil38; + END IF; + if (now = 0 ns) then + n0OOil37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOil38 <= n0OOil37; + END IF; + END PROCESS; + wire_n0OOil38_w_lg_w_lg_q150w151w(0) <= wire_n0OOil38_w_lg_q150w(0) AND wire_nlO1l_dataout; + wire_n0OOil38_w_lg_q150w(0) <= n0OOil38 XOR n0OOil37; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOiO35 <= n0OOiO36; + END IF; + if (now = 0 ns) then + n0OOiO35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOiO36 <= n0OOiO35; + END IF; + END PROCESS; + wire_n0OOiO36_w_lg_w_lg_q145w146w(0) <= wire_n0OOiO36_w_lg_q145w(0) AND wire_nlO1l_dataout; + wire_n0OOiO36_w_lg_q145w(0) <= n0OOiO36 XOR n0OOiO35; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOli33 <= n0OOli34; + END IF; + if (now = 0 ns) then + n0OOli33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOli34 <= n0OOli33; + END IF; + END PROCESS; + wire_n0OOli34_w_lg_w_lg_q129w130w(0) <= wire_n0OOli34_w_lg_q129w(0) AND nlO0l; + wire_n0OOli34_w_lg_q129w(0) <= n0OOli34 XOR n0OOli33; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOlO31 <= n0OOlO32; + END IF; + if (now = 0 ns) then + n0OOlO31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOlO32 <= n0OOlO31; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOOl29 <= n0OOOl30; + END IF; + if (now = 0 ns) then + n0OOOl29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOOl30 <= n0OOOl29; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOOO27 <= n0OOOO28; + END IF; + if (now = 0 ns) then + n0OOOO27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN n0OOOO28 <= n0OOOO27; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni100l15 <= ni100l16; + END IF; + if (now = 0 ns) then + ni100l15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni100l16 <= ni100l15; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni10OO13 <= ni10OO14; + END IF; + if (now = 0 ns) then + ni10OO13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni10OO14 <= ni10OO13; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni110l23 <= ni110l24; + END IF; + if (now = 0 ns) then + ni110l23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni110l24 <= ni110l23; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni111l25 <= ni111l26; + END IF; + if (now = 0 ns) then + ni111l25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni111l26 <= ni111l25; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni11ii21 <= ni11ii22; + END IF; + if (now = 0 ns) then + ni11ii21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni11ii22 <= ni11ii21; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni11Oi19 <= ni11Oi20; + END IF; + if (now = 0 ns) then + ni11Oi19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni11Oi20 <= ni11Oi19; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni11OO17 <= ni11OO18; + END IF; + if (now = 0 ns) then + ni11OO17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni11OO18 <= ni11OO17; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1i0O11 <= ni1i0O12; + END IF; + if (now = 0 ns) then + ni1i0O11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1i0O12 <= ni1i0O11; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1ili10 <= ni1ili9; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1ili9 <= ni1ili10; + END IF; + if (now = 0 ns) then + ni1ili9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1ilO7 <= ni1ilO8; + END IF; + if (now = 0 ns) then + ni1ilO7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1ilO8 <= ni1ilO7; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1l1O5 <= ni1l1O6; + END IF; + if (now = 0 ns) then + ni1l1O5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1l1O6 <= ni1l1O5; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1lil3 <= ni1lil4; + END IF; + if (now = 0 ns) then + ni1lil3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1lil4 <= ni1lil3; + END IF; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1lli1 <= ni1lli2; + END IF; + if (now = 0 ns) then + ni1lli1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (clk_2) + BEGIN + IF (clk_2 = '1' AND clk_2'event) THEN ni1lli2 <= ni1lli1; + END IF; + END PROCESS; + wire_ni1lli2_w_lg_w_lg_q3w4w(0) <= NOT wire_ni1lli2_w_lg_q3w(0); + wire_ni1lli2_w_lg_q3w(0) <= ni1lli2 XOR ni1lli1; + PROCESS (clk_2, wire_n11i_PRN, wire_n11i_CLRN) + BEGIN + IF (wire_n11i_PRN = '0') THEN + n000i <= '1'; + n001O <= '1'; + n00ii <= '1'; + n01Ol <= '1'; + n0liO <= '1'; + n0lli <= '1'; + n0lll <= '1'; + n0llO <= '1'; + n0lOi <= '1'; + n0lOl <= '1'; + n0lOO <= '1'; + n0O1i <= '1'; + n0O1l <= '1'; + n10il <= '1'; + n10iO <= '1'; + n10li <= '1'; + n10ll <= '1'; + n10lO <= '1'; + n10Oi <= '1'; + n10Ol <= '1'; + n10OO <= '1'; + n11l <= '1'; + n1i1i <= '1'; + nii00i <= '1'; + nii00l <= '1'; + nii00O <= '1'; + nii0ii <= '1'; + nii0il <= '1'; + nii0lO <= '1'; + nii0Oi <= '1'; + niiii <= '1'; + niiil <= '1'; + niiiO <= '1'; + niili <= '1'; + niill <= '1'; + niilO <= '1'; + niiOi <= '1'; + niiOl <= '1'; + nill0i <= '1'; + nill1l <= '1'; + nill1O <= '1'; + nillil <= '1'; + nilliO <= '1'; + nillll <= '1'; + niO00i <= '1'; + niO00l <= '1'; + niO00O <= '1'; + niO01O <= '1'; + niO0ii <= '1'; + niO0il <= '1'; + niO0iO <= '1'; + niO0li <= '1'; + niO0ll <= '1'; + nl00i <= '1'; + nl00l <= '1'; + nl00O <= '1'; + nl0ii <= '1'; + nl0iiO <= '1'; + nl0il <= '1'; + nl0ili <= '1'; + nl0ill <= '1'; + nl0ilO <= '1'; + nl0iO <= '1'; + nl0iOi <= '1'; + nl0iOl <= '1'; + nl0iOO <= '1'; + nl0l1i <= '1'; + nl0l1l <= '1'; + nl0li <= '1'; + nl0ll <= '1'; + nl0lO <= '1'; + nl1l0O <= '1'; + nl1lii <= '1'; + nl1lil <= '1'; + nl1liO <= '1'; + nl1lli <= '1'; + nl1lll <= '1'; + nl1llO <= '1'; + nl1lOi <= '1'; + nl1lOl <= '1'; + nliOlO <= '1'; + nliOOi <= '1'; + nliOOl <= '1'; + nliOOO <= '1'; + nll10i <= '1'; + nll11i <= '1'; + nll11l <= '1'; + nll11O <= '1'; + nlllOO <= '1'; + nllO0i <= '1'; + nllO0l <= '1'; + nllO0O <= '1'; + nllO1i <= '1'; + nllO1l <= '1'; + nllO1O <= '1'; + nllOii <= '1'; + nlO0i <= '1'; + nlO0l <= '1'; + nlO0O <= '1'; + nlOii <= '1'; + nlOil <= '1'; + nlOiO <= '1'; + nlOli <= '1'; + nlOll <= '1'; + nlOlO <= '1'; + ELSIF (wire_n11i_CLRN = '0') THEN + n000i <= '0'; + n001O <= '0'; + n00ii <= '0'; + n01Ol <= '0'; + n0liO <= '0'; + n0lli <= '0'; + n0lll <= '0'; + n0llO <= '0'; + n0lOi <= '0'; + n0lOl <= '0'; + n0lOO <= '0'; + n0O1i <= '0'; + n0O1l <= '0'; + n10il <= '0'; + n10iO <= '0'; + n10li <= '0'; + n10ll <= '0'; + n10lO <= '0'; + n10Oi <= '0'; + n10Ol <= '0'; + n10OO <= '0'; + n11l <= '0'; + n1i1i <= '0'; + nii00i <= '0'; + nii00l <= '0'; + nii00O <= '0'; + nii0ii <= '0'; + nii0il <= '0'; + nii0lO <= '0'; + nii0Oi <= '0'; + niiii <= '0'; + niiil <= '0'; + niiiO <= '0'; + niili <= '0'; + niill <= '0'; + niilO <= '0'; + niiOi <= '0'; + niiOl <= '0'; + nill0i <= '0'; + nill1l <= '0'; + nill1O <= '0'; + nillil <= '0'; + nilliO <= '0'; + nillll <= '0'; + niO00i <= '0'; + niO00l <= '0'; + niO00O <= '0'; + niO01O <= '0'; + niO0ii <= '0'; + niO0il <= '0'; + niO0iO <= '0'; + niO0li <= '0'; + niO0ll <= '0'; + nl00i <= '0'; + nl00l <= '0'; + nl00O <= '0'; + nl0ii <= '0'; + nl0iiO <= '0'; + nl0il <= '0'; + nl0ili <= '0'; + nl0ill <= '0'; + nl0ilO <= '0'; + nl0iO <= '0'; + nl0iOi <= '0'; + nl0iOl <= '0'; + nl0iOO <= '0'; + nl0l1i <= '0'; + nl0l1l <= '0'; + nl0li <= '0'; + nl0ll <= '0'; + nl0lO <= '0'; + nl1l0O <= '0'; + nl1lii <= '0'; + nl1lil <= '0'; + nl1liO <= '0'; + nl1lli <= '0'; + nl1lll <= '0'; + nl1llO <= '0'; + nl1lOi <= '0'; + nl1lOl <= '0'; + nliOlO <= '0'; + nliOOi <= '0'; + nliOOl <= '0'; + nliOOO <= '0'; + nll10i <= '0'; + nll11i <= '0'; + nll11l <= '0'; + nll11O <= '0'; + nlllOO <= '0'; + nllO0i <= '0'; + nllO0l <= '0'; + nllO0O <= '0'; + nllO1i <= '0'; + nllO1l <= '0'; + nllO1O <= '0'; + nllOii <= '0'; + nlO0i <= '0'; + nlO0l <= '0'; + nlO0O <= '0'; + nlOii <= '0'; + nlOil <= '0'; + nlOiO <= '0'; + nlOli <= '0'; + nlOll <= '0'; + nlOlO <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n000i <= wire_n00Ol_dataout; + n001O <= wire_n00Oi_dataout; + n00ii <= wire_n0O1O_dataout; + n01Ol <= wire_n00iO_dataout; + n0liO <= wire_n0O0i_dataout; + n0lli <= wire_n0O0l_dataout; + n0lll <= wire_n0O0O_dataout; + n0llO <= wire_n0Oii_dataout; + n0lOi <= wire_n0Oil_dataout; + n0lOl <= wire_n0OiO_dataout; + n0lOO <= wire_n0Oli_dataout; + n0O1i <= wire_n0Oll_dataout; + n0O1l <= wire_nil1i_dataout; + n10il <= wire_n1i1O_dataout; + n10iO <= wire_n1i0i_dataout; + n10li <= wire_n1i0l_dataout; + n10ll <= wire_n1i0O_dataout; + n10lO <= wire_n1iii_dataout; + n10Oi <= wire_n1iil_dataout; + n10Ol <= wire_n1iiO_dataout; + n10OO <= wire_n1ili_dataout; + n11l <= rx_local_fault_clr; + n1i1i <= wire_n00il_dataout; + nii00i <= ni1iiO; + nii00l <= ni1iOO; + nii00O <= (wire_ni0O_w_lg_dataout237w(0) AND wire_w_lg_w_dec_ctl_range54w238w(0)); + nii0ii <= wire_niii1l_dataout; + nii0il <= wire_niii1O_dataout; + nii0lO <= wire_niiiii_dataout; + nii0Oi <= wire_niiiil_dataout; + niiii <= wire_nil1l_dataout; + niiil <= wire_nil1O_dataout; + niiiO <= wire_nil0i_dataout; + niili <= wire_nil0l_dataout; + niill <= wire_nil0O_dataout; + niilO <= wire_nilii_dataout; + niiOi <= wire_nilil_dataout; + niiOl <= wire_niliO_dataout; + nill0i <= wire_nillOl_dataout; + nill1l <= ni1l1l; + nill1O <= wire_nillOi_dataout; + nillil <= wire_nilO1O_dataout; + nilliO <= wire_nilO0i_dataout; + nillll <= wire_niO0lO_dataout; + niO00i <= wire_niO0Ol_dataout; + niO00l <= wire_niO0OO_dataout; + niO00O <= wire_niOi1i_dataout; + niO01O <= wire_niO0Oi_dataout; + niO0ii <= wire_niOi1l_dataout; + niO0il <= wire_niOi1O_dataout; + niO0iO <= wire_niOi0i_dataout; + niO0li <= wire_niOi0l_dataout; + niO0ll <= wire_nl1lOO_dataout; + nl00i <= wire_nl0Ol_dataout; + nl00l <= wire_nl0OO_dataout; + nl00O <= wire_nli1i_dataout; + nl0ii <= wire_nli1l_dataout; + nl0iiO <= wire_nl0l0i_dataout; + nl0il <= wire_nli1O_dataout; + nl0ili <= wire_nl0l0l_dataout; + nl0ill <= wire_nl0l0O_dataout; + nl0ilO <= wire_nl0lii_dataout; + nl0iO <= wire_nli0i_dataout; + nl0iOi <= wire_nl0lil_dataout; + nl0iOl <= wire_nl0liO_dataout; + nl0iOO <= wire_nl0lli_dataout; + nl0l1i <= wire_nl0lll_dataout; + nl0l1l <= wire_nll10O_dataout; + nl0li <= wire_nli0l_dataout; + nl0ll <= wire_nli0O_dataout; + nl0lO <= nlO0i; + nl1l0O <= wire_nl1O1i_dataout; + nl1lii <= wire_nl1O1l_dataout; + nl1lil <= wire_nl1O1O_dataout; + nl1liO <= wire_nl1O0i_dataout; + nl1lli <= wire_nl1O0l_dataout; + nl1lll <= wire_nl1O0O_dataout; + nl1llO <= wire_nl1Oii_dataout; + nl1lOi <= wire_nl1Oil_dataout; + nl1lOl <= wire_nl0l1O_dataout; + nliOlO <= wire_nll1ii_dataout; + nliOOi <= wire_nll1il_dataout; + nliOOl <= wire_nll1iO_dataout; + nliOOO <= wire_nll1li_dataout; + nll10i <= wire_nll1Ol_dataout; + nll11i <= wire_nll1ll_dataout; + nll11l <= wire_nll1lO_dataout; + nll11O <= wire_nll1Oi_dataout; + nlllOO <= wire_nllOli_dataout; + nllO0i <= wire_nllOOl_dataout; + nllO0l <= wire_nllOOO_dataout; + nllO0O <= wire_nlO11i_dataout; + nllO1i <= wire_nllOll_dataout; + nllO1l <= wire_nllOlO_dataout; + nllO1O <= wire_nllOOi_dataout; + nllOii <= wire_nlO11l_dataout; + nlO0i <= indv; + nlO0l <= wire_nllOO_w_lg_o126w(0); + nlO0O <= wire_nllOi_o; + nlOii <= nlOil; + nlOil <= tx_local_fault_det; + nlOiO <= nlOli; + nlOli <= xs_link_status_set; + nlOll <= wire_nlOOi_dataout; + nlOlO <= n11l; + END IF; + END PROCESS; + wire_n11i_CLRN <= ((n0OOOO28 XOR n0OOOO27) AND wire_w_lg_soft_reset116w(0)); + wire_n11i_PRN <= (n0OOOl30 XOR n0OOOl29); + wire_n11i_w_lg_nlO0l282w(0) <= NOT nlO0l; + wire_n11i_w_lg_nlO0O281w(0) <= NOT nlO0O; + wire_n11i_w_lg_w_lg_w_lg_w_lg_nill1l1w5w6w7w(0) <= wire_n11i_w_lg_w_lg_w_lg_nill1l1w5w6w(0) OR nii00O; + wire_n11i_w_lg_w_lg_w_lg_nill1l1w5w6w(0) <= wire_n11i_w_lg_w_lg_nill1l1w5w(0) OR nii00i; + wire_n11i_w_lg_w_lg_nill1l1w5w(0) <= wire_n11i_w_lg_nill1l1w(0) OR wire_ni1lli2_w_lg_w_lg_q3w4w(0); + wire_n11i_w_lg_nill1l1w(0) <= nill1l OR nii00l; + PROCESS (clk_2, soft_reset, wire_n11O_CLRN) + BEGIN + IF (soft_reset = '1') THEN + n000l <= '1'; + n000O <= '1'; + n001i <= '1'; + n001l <= '1'; + n01OO <= '1'; + n10i <= '1'; + nii0iO <= '1'; + nii0li <= '1'; + nii0ll <= '1'; + nii0Ol <= '1'; + nii0OO <= '1'; + niii1i <= '1'; + niiOO <= '1'; + nill0l <= '1'; + nill0O <= '1'; + nillii <= '1'; + nillli <= '1'; + nll10l <= '1'; + nllOil <= '1'; + ELSIF (wire_n11O_CLRN = '0') THEN + n000l <= '0'; + n000O <= '0'; + n001i <= '0'; + n001l <= '0'; + n01OO <= '0'; + n10i <= '0'; + nii0iO <= '0'; + nii0li <= '0'; + nii0ll <= '0'; + nii0Ol <= '0'; + nii0OO <= '0'; + niii1i <= '0'; + niiOO <= '0'; + nill0l <= '0'; + nill0O <= '0'; + nillii <= '0'; + nillli <= '0'; + nll10l <= '0'; + nllOil <= '0'; + ELSIF (clk_2 = '1' AND clk_2'event) THEN + n000l <= wire_n00OO_dataout; + n000O <= wire_n0i1i_dataout; + n001i <= wire_n00ll_dataout; + n001l <= wire_n00lO_dataout; + n01OO <= wire_n00li_dataout; + n10i <= wire_n10l_dataout; + nii0iO <= wire_niii0i_dataout; + nii0li <= wire_niii0l_dataout; + nii0ll <= wire_niii0O_dataout; + nii0Ol <= wire_niiiiO_dataout; + nii0OO <= wire_niiili_dataout; + niii1i <= wire_nilllO_dataout; + niiOO <= wire_nl0Oi_dataout; + nill0l <= wire_nillOO_dataout; + nill0O <= wire_nilO1i_dataout; + nillii <= wire_nilO1l_dataout; + nillli <= wire_nilO0l_dataout; + nll10l <= wire_nllOiO_dataout; + nllOil <= wire_n1i1l_dataout; + END IF; + if (now = 0 ns) then + n000l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n000O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n001i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n001l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n10i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii0iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii0li <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii0ll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii0Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii0OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niii1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niiOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nill0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nill0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nillii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nillli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll10l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllOil <= '1' after 1 ps; + end if; + END PROCESS; + wire_n11O_CLRN <= (ni111l26 XOR ni111l25); + wire_n00il_dataout <= wire_n0i1l_dataout AND NOT(ni1l0O); + wire_n00iO_dataout <= wire_n0i1O_dataout AND NOT(ni1l0O); + wire_n00li_dataout <= wire_n0i0i_dataout OR ni1l0O; + wire_n00ll_dataout <= wire_n0i0l_dataout OR ni1l0O; + wire_n00lO_dataout <= wire_n0i0O_dataout OR ni1l0O; + wire_n00Oi_dataout <= wire_n0iii_dataout AND NOT(ni1l0O); + wire_n00Ol_dataout <= wire_n0iil_dataout AND NOT(ni1l0O); + wire_n00OO_dataout <= wire_n0iiO_dataout OR ni1l0O; + wire_n010i_dataout <= wire_n1O1i_dataout OR n0Ol1l; + wire_n010l_dataout <= wire_n1O1l_dataout AND NOT(n0Ol1l); + wire_n010O_dataout <= wire_n1O1O_dataout AND NOT(n0Ol1l); + wire_n011i_dataout <= wire_n01li_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n011l_dataout <= wire_n1lOl_dataout OR n0Ol1l; + wire_n011O_dataout <= wire_n1lOO_dataout OR n0Ol1l; + wire_n01ii_dataout <= wire_n1O0i_dataout AND NOT(n0Ol1l); + wire_n01il_dataout <= wire_n1O0l_dataout AND NOT(n0Ol1l); + wire_n01iO_dataout <= wire_n1O0O_dataout AND NOT(n0Ol1l); + wire_n01li_dataout <= wire_n1Oii_dataout OR n0Ol1l; + wire_n0i_dataout <= nliOOO WHEN rxaui_s2gx_en = '1' ELSE nl0ilO; + wire_n0i0i_dataout <= wire_n0iOi_dataout WHEN n0Ol0O = '1' ELSE wire_nl1i_dataout; + wire_n0i0l_dataout <= wire_n0iOl_dataout WHEN n0Ol0O = '1' ELSE wire_nl1l_dataout; + wire_n0i0O_dataout <= wire_n0iOO_dataout WHEN n0Ol0O = '1' ELSE wire_nl1O_dataout; + wire_n0i1i_dataout <= wire_n0ili_dataout OR ni1l0O; + wire_n0i1l_dataout <= wire_n0ill_dataout WHEN n0Ol0O = '1' ELSE wire_niOl_dataout; + wire_n0i1O_dataout <= wire_n0ilO_dataout WHEN n0Ol0O = '1' ELSE wire_niOO_dataout; + wire_n0iii_dataout <= wire_n0l1i_dataout WHEN n0Ol0O = '1' ELSE wire_nl0i_dataout; + wire_n0iil_dataout <= wire_n0l1l_dataout WHEN n0Ol0O = '1' ELSE wire_nl0l_dataout; + wire_n0iiO_dataout <= wire_n0l1O_dataout WHEN n0Ol0O = '1' ELSE wire_nl0O_dataout; + wire_n0ili_dataout <= wire_n0l0i_dataout WHEN n0Ol0O = '1' ELSE wire_nili_dataout; + wire_n0ill_dataout <= wire_niOl_dataout AND NOT(n0Ol0l); + wire_n0ilO_dataout <= wire_niOO_dataout OR n0Ol0l; + wire_n0iOi_dataout <= wire_nl1i_dataout OR n0Ol0l; + wire_n0iOl_dataout <= wire_nl1l_dataout OR n0Ol0l; + wire_n0iOO_dataout <= wire_nl1O_dataout OR n0Ol0l; + wire_n0l_dataout <= nll11i WHEN rxaui_s2gx_en = '1' ELSE nl0iOi; + wire_n0l0i_dataout <= wire_nili_dataout OR n0Ol0l; + wire_n0l1i_dataout <= wire_nl0i_dataout OR n0Ol0l; + wire_n0l1l_dataout <= wire_nl0l_dataout OR n0Ol0l; + wire_n0l1O_dataout <= wire_nl0O_dataout OR n0Ol0l; + wire_n0O_dataout <= nll11l WHEN rxaui_s2gx_en = '1' ELSE nl0iOl; + wire_n0O0i_dataout <= wire_n0OOi_dataout AND NOT(ni1l0O); + wire_n0O0l_dataout <= wire_n0OOl_dataout AND NOT(ni1l0O); + wire_n0O0O_dataout <= wire_n0OOO_dataout AND NOT(ni1l0O); + wire_n0O1O_dataout <= wire_n0OlO_dataout AND NOT(ni1l0O); + wire_n0Oii_dataout <= wire_ni11i_dataout AND NOT(ni1l0O); + wire_n0Oil_dataout <= wire_ni11l_dataout AND NOT(ni1l0O); + wire_n0OiO_dataout <= wire_ni11O_dataout AND NOT(ni1l0O); + wire_n0Oli_dataout <= wire_ni10i_dataout AND NOT(ni1l0O); + wire_n0Oll_dataout <= wire_ni10l_dataout AND NOT(ni1l0O); + wire_n0OlO_dataout <= wire_ni0lO_dataout WHEN ni1l1l = '1' ELSE wire_ni10O_dataout; + wire_n0OOi_dataout <= wire_ni0Oi_dataout WHEN ni1l1l = '1' ELSE wire_ni1ii_dataout; + wire_n0OOl_dataout <= wire_ni0Ol_dataout WHEN ni1l1l = '1' ELSE wire_ni1il_dataout; + wire_n0OOO_dataout <= wire_ni0OO_dataout WHEN ni1l1l = '1' ELSE wire_ni1iO_dataout; + wire_n100i_dataout <= wire_nlOlli_dataout OR n0OiOO; + wire_n100l_dataout <= wire_nlOlll_dataout OR n0OiOO; + wire_n101i_dataout <= wire_nlOlii_dataout OR n0OiOO; + wire_n101l_dataout <= wire_nlOlil_dataout OR n0OiOO; + wire_n101O_dataout <= wire_nlOliO_dataout OR n0OiOO; + wire_n10l_dataout <= wire_n10O_dataout AND NOT(nlOlO); + wire_n10O_dataout <= n10i OR NOT(ni111O); + wire_n110i_dataout <= wire_nlOill_dataout OR n0OiOl; + wire_n110l_dataout <= n0OO1i WHEN n0OiOl = '1' ELSE wire_nlOilO_dataout; + wire_n110O_dataout <= n0OO1i WHEN n0OiOl = '1' ELSE wire_nlOiOi_dataout; + wire_n111i_dataout <= wire_n100l_dataout WHEN ni1lii = '1' ELSE wire_n11li_dataout; + wire_n111l_dataout <= wire_w_lg_n0OO1i205w(0) WHEN n0OiOl = '1' ELSE wire_nlOiiO_dataout; + wire_n111O_dataout <= wire_nlOili_dataout OR n0OiOl; + wire_n11ii_dataout <= n0OO1i WHEN n0OiOl = '1' ELSE wire_nlOiOl_dataout; + wire_n11il_dataout <= n0OO1i WHEN n0OiOl = '1' ELSE wire_nlOiOO_dataout; + wire_n11iO_dataout <= n0OO1i WHEN n0OiOl = '1' ELSE wire_nlOl1i_dataout; + wire_n11li_dataout <= wire_nlOl1l_dataout OR n0OiOl; + wire_n11lO_dataout <= wire_nlOl1O_dataout AND NOT(n0OiOO); + wire_n11Oi_dataout <= wire_nlOl0i_dataout OR n0OiOO; + wire_n11Ol_dataout <= wire_nlOl0l_dataout OR n0OiOO; + wire_n11OO_dataout <= wire_nlOl0O_dataout OR n0OiOO; + wire_n1i_dataout <= nliOlO WHEN rxaui_s2gx_en = '1' ELSE nl0iiO; + wire_n1i0i_dataout <= wire_n1Oli_dataout WHEN n0Ol1i = '1' ELSE wire_n1iOi_dataout; + wire_n1i0l_dataout <= wire_n1Oll_dataout WHEN n0Ol1i = '1' ELSE wire_n1iOl_dataout; + wire_n1i0O_dataout <= wire_n1OlO_dataout WHEN n0Ol1i = '1' ELSE wire_n1iOO_dataout; + wire_n1i1l_dataout <= wire_n1Oil_dataout WHEN n0Ol1i = '1' ELSE wire_n1ill_dataout; + wire_n1i1O_dataout <= wire_n1OiO_dataout WHEN n0Ol1i = '1' ELSE wire_n1ilO_dataout; + wire_n1iii_dataout <= wire_n1OOi_dataout WHEN n0Ol1i = '1' ELSE wire_n1l1i_dataout; + wire_n1iil_dataout <= wire_n1OOl_dataout WHEN n0Ol1i = '1' ELSE wire_n1l1l_dataout; + wire_n1iiO_dataout <= wire_n1OOO_dataout WHEN n0Ol1i = '1' ELSE wire_n1l1O_dataout; + wire_n1ili_dataout <= wire_n011i_dataout WHEN n0Ol1i = '1' ELSE wire_n1l0i_dataout; + wire_n1ill_dataout <= wire_n1l0l_dataout OR wire_w_lg_ni111O120w(0); + wire_n1ilO_dataout <= wire_n1l0O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1iOi_dataout <= wire_n1lii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1iOl_dataout <= wire_n1lil_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1iOO_dataout <= wire_n1liO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1l_dataout <= nliOOi WHEN rxaui_s2gx_en = '1' ELSE nl0ili; + wire_n1l0i_dataout <= wire_n1lOi_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1l0l_dataout <= wire_n1lOl_dataout OR ni110i; + wire_n1l0O_dataout <= wire_n1lOO_dataout OR ni110i; + wire_n1l1i_dataout <= wire_n1lli_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1l1l_dataout <= wire_n1lll_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1l1O_dataout <= wire_n1llO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1lii_dataout <= wire_n1O1i_dataout OR ni110i; + wire_n1lil_dataout <= wire_n1O1l_dataout AND NOT(ni110i); + wire_n1liO_dataout <= wire_n1O1O_dataout AND NOT(ni110i); + wire_n1lli_dataout <= wire_n1O0i_dataout AND NOT(ni110i); + wire_n1lll_dataout <= wire_n1O0l_dataout AND NOT(ni110i); + wire_n1llO_dataout <= wire_n1O0O_dataout AND NOT(ni110i); + wire_n1lOi_dataout <= wire_n1Oii_dataout OR ni110i; + wire_n1lOl_dataout <= dec_data(24) AND NOT(wire_ni0O_dataout); + wire_n1lOO_dataout <= dec_data(25) OR wire_ni0O_dataout; + wire_n1O_dataout <= nliOOl WHEN rxaui_s2gx_en = '1' ELSE nl0ill; + wire_n1O0i_dataout <= dec_data(29) OR wire_ni0O_dataout; + wire_n1O0l_dataout <= dec_data(30) OR wire_ni0O_dataout; + wire_n1O0O_dataout <= dec_data(31) OR wire_ni0O_dataout; + wire_n1O1i_dataout <= dec_data(26) OR wire_ni0O_dataout; + wire_n1O1l_dataout <= dec_data(27) OR wire_ni0O_dataout; + wire_n1O1O_dataout <= dec_data(28) OR wire_ni0O_dataout; + wire_n1Oii_dataout <= dec_ctl(3) OR wire_ni0O_dataout; + wire_n1Oil_dataout <= wire_n011l_dataout OR wire_w_lg_ni111O120w(0); + wire_n1OiO_dataout <= wire_n011O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1Oli_dataout <= wire_n010i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1Oll_dataout <= wire_n010l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1OlO_dataout <= wire_n010O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1OOi_dataout <= wire_n01ii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1OOl_dataout <= wire_n01il_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_n1OOO_dataout <= wire_n01iO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_ni_dataout <= n10lO WHEN rxaui_s2gx_en = '1' ELSE nllO0i; + wire_ni00i_dataout <= wire_nlll_dataout OR n0Olii; + wire_ni00l_dataout <= wire_nllO_dataout OR n0Olii; + wire_ni00O_dataout <= wire_nlOi_dataout OR n0Olii; + wire_ni01i_dataout <= wire_nlil_dataout OR n0Olii; + wire_ni01l_dataout <= wire_nliO_dataout OR n0Olii; + wire_ni01O_dataout <= wire_nlli_dataout OR n0Olii; + wire_ni0i_dataout <= running_disp(1) AND NOT(ni1l0O); + wire_ni0i_w_lg_dataout23w(0) <= NOT wire_ni0i_dataout; + wire_ni0ii_dataout <= wire_nlOl_dataout OR n0Olii; + wire_ni0il_dataout <= wire_nill_dataout OR n0Olii; + wire_ni0l_dataout <= running_disp(2) AND NOT(ni1l0O); + wire_ni0l_w_lg_dataout27w(0) <= NOT wire_ni0l_dataout; + wire_ni0lO_dataout <= wire_nlii_dataout AND NOT(n0OliO); + wire_ni0O_dataout <= running_disp(3) AND NOT(ni1l0O); + wire_ni0O_w_lg_dataout237w(0) <= NOT wire_ni0O_dataout; + wire_ni0Oi_dataout <= wire_nlil_dataout OR n0OliO; + wire_ni0Ol_dataout <= wire_nliO_dataout OR n0OliO; + wire_ni0OO_dataout <= wire_nlli_dataout OR n0OliO; + wire_ni10i_dataout <= wire_nii0i_dataout WHEN ni1l1l = '1' ELSE wire_ni1Oi_dataout; + wire_ni10l_dataout <= wire_nii0l_dataout WHEN ni1l1l = '1' ELSE wire_ni1Ol_dataout; + wire_ni10O_dataout <= wire_ni1OO_dataout WHEN n0Olil = '1' ELSE wire_nlii_dataout; + wire_ni11i_dataout <= wire_nii1i_dataout WHEN ni1l1l = '1' ELSE wire_ni1li_dataout; + wire_ni11l_dataout <= wire_nii1l_dataout WHEN ni1l1l = '1' ELSE wire_ni1ll_dataout; + wire_ni11O_dataout <= wire_nii1O_dataout WHEN ni1l1l = '1' ELSE wire_ni1lO_dataout; + wire_ni1ii_dataout <= wire_ni01i_dataout WHEN n0Olil = '1' ELSE wire_nlil_dataout; + wire_ni1il_dataout <= wire_ni01l_dataout WHEN n0Olil = '1' ELSE wire_nliO_dataout; + wire_ni1iO_dataout <= wire_ni01O_dataout WHEN n0Olil = '1' ELSE wire_nlli_dataout; + wire_ni1li_dataout <= wire_ni00i_dataout WHEN n0Olil = '1' ELSE wire_nlll_dataout; + wire_ni1ll_dataout <= wire_ni00l_dataout WHEN n0Olil = '1' ELSE wire_nllO_dataout; + wire_ni1lO_dataout <= wire_ni00O_dataout WHEN n0Olil = '1' ELSE wire_nlOi_dataout; + wire_ni1O_dataout <= running_disp(0) AND NOT(ni1l0O); + wire_ni1O_w_lg_dataout16w(0) <= NOT wire_ni1O_dataout; + wire_ni1Oi_dataout <= wire_ni0ii_dataout WHEN n0Olil = '1' ELSE wire_nlOl_dataout; + wire_ni1Ol_dataout <= wire_ni0il_dataout WHEN n0Olil = '1' ELSE wire_nill_dataout; + wire_ni1OO_dataout <= wire_nlii_dataout AND NOT(n0Olii); + wire_nii_dataout <= nll11O WHEN rxaui_s2gx_en = '1' ELSE nl0iOO; + wire_nii0i_dataout <= wire_nlOl_dataout OR n0OliO; + wire_nii0l_dataout <= wire_nill_dataout OR n0OliO; + wire_nii1i_dataout <= wire_nlll_dataout OR n0OliO; + wire_nii1l_dataout <= wire_nllO_dataout OR n0OliO; + wire_nii1O_dataout <= wire_nlOi_dataout OR n0OliO; + wire_niii0i_dataout <= wire_nil0ii_dataout WHEN n0Ol1i = '1' ELSE wire_niiiOi_dataout; + wire_niii0l_dataout <= wire_nil0il_dataout WHEN n0Ol1i = '1' ELSE wire_niiiOl_dataout; + wire_niii0O_dataout <= wire_nil0iO_dataout WHEN n0Ol1i = '1' ELSE wire_niiiOO_dataout; + wire_niii1l_dataout <= wire_nil00l_dataout WHEN n0Ol1i = '1' ELSE wire_niiill_dataout; + wire_niii1O_dataout <= wire_nil00O_dataout WHEN n0Ol1i = '1' ELSE wire_niiilO_dataout; + wire_niiiii_dataout <= wire_nil0li_dataout WHEN n0Ol1i = '1' ELSE wire_niil1i_dataout; + wire_niiiil_dataout <= wire_nil0ll_dataout WHEN n0Ol1i = '1' ELSE wire_niil1l_dataout; + wire_niiiiO_dataout <= wire_nil0lO_dataout WHEN n0Ol1i = '1' ELSE wire_niil1O_dataout; + wire_niiili_dataout <= wire_nil0Oi_dataout WHEN n0Ol1i = '1' ELSE wire_niil0i_dataout; + wire_niiill_dataout <= wire_niiOil_dataout WHEN n0OilO = '1' ELSE wire_niil0l_dataout; + wire_niiilO_dataout <= wire_niiOiO_dataout WHEN n0OilO = '1' ELSE wire_niil0O_dataout; + wire_niiiOi_dataout <= wire_niiOli_dataout WHEN n0OilO = '1' ELSE wire_niilii_dataout; + wire_niiiOl_dataout <= wire_niiOll_dataout WHEN n0OilO = '1' ELSE wire_niilil_dataout; + wire_niiiOO_dataout <= wire_niiOlO_dataout WHEN n0OilO = '1' ELSE wire_niiliO_dataout; + wire_niil0i_dataout <= wire_nil11i_dataout WHEN n0OilO = '1' ELSE wire_niilOi_dataout; + wire_niil0l_dataout <= wire_niilOl_dataout AND ni111O; + wire_niil0O_dataout <= wire_niilOO_dataout AND ni111O; + wire_niil1i_dataout <= wire_niiOOi_dataout WHEN n0OilO = '1' ELSE wire_niilli_dataout; + wire_niil1l_dataout <= wire_niiOOl_dataout WHEN n0OilO = '1' ELSE wire_niilll_dataout; + wire_niil1O_dataout <= wire_niiOOO_dataout WHEN n0OilO = '1' ELSE wire_niillO_dataout; + wire_niilii_dataout <= wire_niiO1i_dataout OR NOT(ni111O); + wire_niilil_dataout <= wire_niiO1l_dataout OR NOT(ni111O); + wire_niiliO_dataout <= wire_niiO1O_dataout OR NOT(ni111O); + wire_niilli_dataout <= wire_niiO0i_dataout AND ni111O; + wire_niilll_dataout <= wire_niiO0l_dataout AND ni111O; + wire_niillO_dataout <= wire_niiO0O_dataout OR NOT(ni111O); + wire_niilOi_dataout <= wire_niiOii_dataout OR NOT(ni111O); + wire_niilOl_dataout <= dec_data(0) OR ni110i; + wire_niilOO_dataout <= dec_data(1) OR ni110i; + wire_niiO0i_dataout <= dec_data(5) AND NOT(ni110i); + wire_niiO0l_dataout <= dec_data(6) AND NOT(ni110i); + wire_niiO0O_dataout <= dec_data(7) AND NOT(ni110i); + wire_niiO1i_dataout <= dec_data(2) OR ni110i; + wire_niiO1l_dataout <= dec_data(3) AND NOT(ni110i); + wire_niiO1O_dataout <= dec_data(4) AND NOT(ni110i); + wire_niiOii_dataout <= dec_ctl(0) OR ni110i; + wire_niiOil_dataout <= wire_nil11l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niiOiO_dataout <= wire_nil11O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niiOli_dataout <= wire_nil10i_dataout OR wire_w_lg_ni111O120w(0); + wire_niiOll_dataout <= wire_nil10l_dataout OR wire_w_lg_ni111O120w(0); + wire_niiOlO_dataout <= wire_nil10O_dataout OR wire_w_lg_ni111O120w(0); + wire_niiOOi_dataout <= wire_nil1ii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niiOOl_dataout <= wire_nil1il_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niiOOO_dataout <= wire_nil1iO_dataout OR wire_w_lg_ni111O120w(0); + wire_nil_dataout <= nllOil WHEN rxaui_s2gx_en = '1' ELSE nll10l; + wire_nil00i_dataout <= dec_ctl(0) OR n0OiOi; + wire_nil00l_dataout <= wire_nil0Ol_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nil00O_dataout <= wire_nil0OO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nil01i_dataout <= dec_data(5) AND NOT(n0OiOi); + wire_nil01l_dataout <= dec_data(6) AND NOT(n0OiOi); + wire_nil01O_dataout <= dec_data(7) AND NOT(n0OiOi); + wire_nil0i_dataout <= wire_nilOi_dataout AND NOT(ni1l0O); + wire_nil0ii_dataout <= wire_nili1i_dataout OR wire_w_lg_ni111O120w(0); + wire_nil0il_dataout <= wire_nili1l_dataout OR wire_w_lg_ni111O120w(0); + wire_nil0iO_dataout <= wire_nili1O_dataout OR wire_w_lg_ni111O120w(0); + wire_nil0l_dataout <= wire_nilOl_dataout AND NOT(ni1l0O); + wire_nil0li_dataout <= wire_nili0i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nil0ll_dataout <= wire_nili0l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nil0lO_dataout <= wire_nili0O_dataout OR wire_w_lg_ni111O120w(0); + wire_nil0O_dataout <= wire_nilOO_dataout AND NOT(ni1l0O); + wire_nil0Oi_dataout <= wire_niliii_dataout OR wire_w_lg_ni111O120w(0); + wire_nil0Ol_dataout <= wire_niliil_dataout WHEN ni1lii = '1' ELSE wire_nil11l_dataout; + wire_nil0OO_dataout <= wire_niliiO_dataout WHEN ni1lii = '1' ELSE wire_nil11O_dataout; + wire_nil10i_dataout <= wire_nil1Oi_dataout OR wire_ni1O_dataout; + wire_nil10l_dataout <= wire_nil1Ol_dataout OR wire_ni1O_dataout; + wire_nil10O_dataout <= wire_nil1OO_dataout OR wire_ni1O_dataout; + wire_nil11i_dataout <= wire_nil1li_dataout OR wire_w_lg_ni111O120w(0); + wire_nil11l_dataout <= wire_nil1ll_dataout AND NOT(wire_ni1O_dataout); + wire_nil11O_dataout <= wire_nil1lO_dataout OR wire_ni1O_dataout; + wire_nil1i_dataout <= wire_nilli_dataout AND NOT(ni1l0O); + wire_nil1ii_dataout <= wire_nil01i_dataout OR wire_ni1O_dataout; + wire_nil1il_dataout <= wire_nil01l_dataout OR wire_ni1O_dataout; + wire_nil1iO_dataout <= wire_nil01O_dataout OR wire_ni1O_dataout; + wire_nil1l_dataout <= wire_nilll_dataout AND NOT(ni1l0O); + wire_nil1li_dataout <= wire_nil00i_dataout OR wire_ni1O_dataout; + wire_nil1ll_dataout <= dec_data(0) OR n0OiOi; + wire_nil1lO_dataout <= dec_data(1) OR n0OiOi; + wire_nil1O_dataout <= wire_nillO_dataout AND NOT(ni1l0O); + wire_nil1Oi_dataout <= dec_data(2) OR n0OiOi; + wire_nil1Ol_dataout <= dec_data(3) AND NOT(n0OiOi); + wire_nil1OO_dataout <= dec_data(4) AND NOT(n0OiOi); + wire_nili_dataout <= niii1i WHEN rxaui_s2gx_en = '1' ELSE nii0OO; + wire_nili0i_dataout <= wire_niliOi_dataout WHEN ni1lii = '1' ELSE wire_nil1ii_dataout; + wire_nili0l_dataout <= wire_niliOl_dataout WHEN ni1lii = '1' ELSE wire_nil1il_dataout; + wire_nili0O_dataout <= wire_niliOO_dataout WHEN ni1lii = '1' ELSE wire_nil1iO_dataout; + wire_nili1i_dataout <= wire_nilili_dataout WHEN ni1lii = '1' ELSE wire_nil10i_dataout; + wire_nili1l_dataout <= wire_nilill_dataout WHEN ni1lii = '1' ELSE wire_nil10l_dataout; + wire_nili1O_dataout <= wire_nililO_dataout WHEN ni1lii = '1' ELSE wire_nil10O_dataout; + wire_nilii_dataout <= wire_niO1i_dataout AND NOT(ni1l0O); + wire_niliii_dataout <= wire_nill1i_dataout WHEN ni1lii = '1' ELSE wire_nil1li_dataout; + wire_niliil_dataout <= wire_nil1ll_dataout AND NOT(n0Ol0l); + wire_niliiO_dataout <= wire_nil1lO_dataout OR n0Ol0l; + wire_nilil_dataout <= wire_niO1l_dataout AND NOT(ni1l0O); + wire_nilili_dataout <= wire_nil1Oi_dataout OR n0Ol0l; + wire_nilill_dataout <= wire_nil1Ol_dataout OR n0Ol0l; + wire_nililO_dataout <= wire_nil1OO_dataout OR n0Ol0l; + wire_niliO_dataout <= wire_niO1O_dataout AND NOT(ni1l0O); + wire_niliOi_dataout <= wire_nil01i_dataout OR n0Ol0l; + wire_niliOl_dataout <= wire_nil01l_dataout OR n0Ol0l; + wire_niliOO_dataout <= wire_nil01O_dataout OR n0Ol0l; + wire_nill_dataout <= nl1lOi WHEN rxaui_s2gx_en = '1' ELSE niO0li; + wire_nill1i_dataout <= wire_nil00i_dataout OR n0Ol0l; + wire_nilli_dataout <= wire_nl1iO_dataout WHEN n0OOii = '1' ELSE wire_niO0i_dataout; + wire_nilll_dataout <= wire_nl1li_dataout WHEN n0OOii = '1' ELSE wire_niO0l_dataout; + wire_nilllO_dataout <= wire_nilO0O_dataout OR wire_nllOO_o; + wire_nillO_dataout <= wire_nl1ll_dataout WHEN n0OOii = '1' ELSE wire_niO0O_dataout; + wire_nillOi_dataout <= wire_nilOii_dataout AND NOT(wire_nllOO_o); + wire_nillOl_dataout <= wire_nilOil_dataout AND NOT(wire_nllOO_o); + wire_nillOO_dataout <= wire_nilOiO_dataout OR wire_nllOO_o; + wire_nilO_dataout <= nll10i WHEN rxaui_s2gx_en = '1' ELSE nl0l1i; + wire_nilO0i_dataout <= wire_nilOOi_dataout AND NOT(wire_nllOO_o); + wire_nilO0l_dataout <= wire_nilOOl_dataout OR wire_nllOO_o; + wire_nilO0O_dataout <= wire_nilOOO_dataout OR wire_nllOl_o; + wire_nilO1i_dataout <= wire_nilOli_dataout OR wire_nllOO_o; + wire_nilO1l_dataout <= wire_nilOll_dataout OR wire_nllOO_o; + wire_nilO1O_dataout <= wire_nilOlO_dataout AND NOT(wire_nllOO_o); + wire_nilOi_dataout <= wire_nl1lO_dataout WHEN n0OOii = '1' ELSE wire_niOii_dataout; + wire_nilOii_dataout <= wire_niO11i_dataout OR wire_nllOl_o; + wire_nilOil_dataout <= wire_niO11l_dataout OR wire_nllOl_o; + wire_nilOiO_dataout <= wire_niO11O_dataout OR wire_nllOl_o; + wire_nilOl_dataout <= wire_nl1Oi_dataout WHEN n0OOii = '1' ELSE wire_niOil_dataout; + wire_nilOli_dataout <= wire_niO10i_dataout AND NOT(wire_nllOl_o); + wire_nilOll_dataout <= wire_niO10l_dataout AND NOT(wire_nllOl_o); + wire_nilOlO_dataout <= wire_niO10O_dataout AND NOT(wire_nllOl_o); + wire_nilOO_dataout <= wire_nl1Ol_dataout WHEN n0OOii = '1' ELSE wire_niOiO_dataout; + wire_nilOOi_dataout <= wire_niO1ii_dataout AND NOT(wire_nllOl_o); + wire_nilOOl_dataout <= wire_niO1il_dataout AND NOT(wire_nllOl_o); + wire_nilOOO_dataout <= dec_ctl(0) WHEN ni1l1l = '1' ELSE wire_niO01l_dataout; + wire_niO_dataout <= n10il WHEN rxaui_s2gx_en = '1' ELSE nlllOO; + wire_niO01i_dataout <= dec_data(7) OR wire_ni1O_dataout; + wire_niO01l_dataout <= dec_ctl(0) OR wire_ni1O_dataout; + wire_niO0i_dataout <= wire_niOOi_dataout WHEN nii00O = '1' ELSE wire_nlOO_dataout; + wire_niO0l_dataout <= wire_niOOl_dataout WHEN nii00O = '1' ELSE wire_n1i_dataout; + wire_niO0lO_dataout <= wire_nl11OO_dataout WHEN n0Ol1i = '1' ELSE wire_niOi0O_dataout; + wire_niO0O_dataout <= wire_niOOO_dataout WHEN nii00O = '1' ELSE wire_n1l_dataout; + wire_niO0Oi_dataout <= wire_nl101i_dataout WHEN n0Ol1i = '1' ELSE wire_niOiii_dataout; + wire_niO0Ol_dataout <= wire_nl101l_dataout WHEN n0Ol1i = '1' ELSE wire_niOiil_dataout; + wire_niO0OO_dataout <= wire_nl101O_dataout WHEN n0Ol1i = '1' ELSE wire_niOiiO_dataout; + wire_niO10i_dataout <= dec_data(3) WHEN ni1l1l = '1' ELSE wire_niO1lO_dataout; + wire_niO10l_dataout <= dec_data(4) WHEN ni1l1l = '1' ELSE wire_niO1Oi_dataout; + wire_niO10O_dataout <= dec_data(5) WHEN ni1l1l = '1' ELSE wire_niO1Ol_dataout; + wire_niO11i_dataout <= dec_data(0) WHEN ni1l1l = '1' ELSE wire_niO1iO_dataout; + wire_niO11l_dataout <= dec_data(1) WHEN ni1l1l = '1' ELSE wire_niO1li_dataout; + wire_niO11O_dataout <= dec_data(2) WHEN ni1l1l = '1' ELSE wire_niO1ll_dataout; + wire_niO1i_dataout <= wire_nl1OO_dataout WHEN n0OOii = '1' ELSE wire_niOli_dataout; + wire_niO1ii_dataout <= dec_data(6) WHEN ni1l1l = '1' ELSE wire_niO1OO_dataout; + wire_niO1il_dataout <= dec_data(7) WHEN ni1l1l = '1' ELSE wire_niO01i_dataout; + wire_niO1iO_dataout <= dec_data(0) AND NOT(wire_ni1O_dataout); + wire_niO1l_dataout <= wire_nl01i_dataout WHEN n0OOii = '1' ELSE wire_niOll_dataout; + wire_niO1li_dataout <= dec_data(1) OR wire_ni1O_dataout; + wire_niO1ll_dataout <= dec_data(2) OR wire_ni1O_dataout; + wire_niO1lO_dataout <= dec_data(3) OR wire_ni1O_dataout; + wire_niO1O_dataout <= wire_nl01l_dataout WHEN n0OOii = '1' ELSE wire_niOlO_dataout; + wire_niO1Oi_dataout <= dec_data(4) OR wire_ni1O_dataout; + wire_niO1Ol_dataout <= dec_data(5) OR wire_ni1O_dataout; + wire_niO1OO_dataout <= dec_data(6) OR wire_ni1O_dataout; + wire_niOi_dataout <= n10OO WHEN rxaui_s2gx_en = '1' ELSE nllOii; + wire_niOi0i_dataout <= wire_nl10ii_dataout WHEN n0Ol1i = '1' ELSE wire_niOiOi_dataout; + wire_niOi0l_dataout <= wire_nl10il_dataout WHEN n0Ol1i = '1' ELSE wire_niOiOl_dataout; + wire_niOi0O_dataout <= wire_niOO1O_dataout WHEN n0OilO = '1' ELSE wire_niOiOO_dataout; + wire_niOi1i_dataout <= wire_nl100i_dataout WHEN n0Ol1i = '1' ELSE wire_niOili_dataout; + wire_niOi1l_dataout <= wire_nl100l_dataout WHEN n0Ol1i = '1' ELSE wire_niOill_dataout; + wire_niOi1O_dataout <= wire_nl100O_dataout WHEN n0Ol1i = '1' ELSE wire_niOilO_dataout; + wire_niOii_dataout <= wire_nl11i_dataout WHEN nii00O = '1' ELSE wire_n1O_dataout; + wire_niOiii_dataout <= wire_niOO0i_dataout WHEN n0OilO = '1' ELSE wire_niOl1i_dataout; + wire_niOiil_dataout <= wire_niOO0l_dataout WHEN n0OilO = '1' ELSE wire_niOl1l_dataout; + wire_niOiiO_dataout <= wire_niOO0O_dataout WHEN n0OilO = '1' ELSE wire_niOl1O_dataout; + wire_niOil_dataout <= wire_nl11l_dataout WHEN nii00O = '1' ELSE wire_n0i_dataout; + wire_niOili_dataout <= wire_niOOii_dataout WHEN n0OilO = '1' ELSE wire_niOl0i_dataout; + wire_niOill_dataout <= wire_niOOil_dataout WHEN n0OilO = '1' ELSE wire_niOl0l_dataout; + wire_niOilO_dataout <= wire_niOOiO_dataout WHEN n0OilO = '1' ELSE wire_niOl0O_dataout; + wire_niOiO_dataout <= wire_nl11O_dataout WHEN nii00O = '1' ELSE wire_n0l_dataout; + wire_niOiOi_dataout <= wire_niOOli_dataout WHEN n0OilO = '1' ELSE wire_niOlii_dataout; + wire_niOiOl_dataout <= wire_niOOll_dataout WHEN n0OilO = '1' ELSE wire_niOlil_dataout; + wire_niOiOO_dataout <= wire_niOliO_dataout AND ni111O; + wire_niOl_dataout <= nill1O WHEN rxaui_s2gx_en = '1' ELSE nii0ii; + wire_niOl0i_dataout <= wire_niOlOi_dataout AND ni111O; + wire_niOl0l_dataout <= wire_niOlOl_dataout AND ni111O; + wire_niOl0O_dataout <= wire_niOlOO_dataout AND ni111O; + wire_niOl1i_dataout <= wire_niOlli_dataout AND ni111O; + wire_niOl1l_dataout <= wire_niOlll_dataout AND ni111O; + wire_niOl1O_dataout <= wire_niOllO_dataout AND ni111O; + wire_niOli_dataout <= wire_nl10i_dataout WHEN nii00O = '1' ELSE wire_n0O_dataout; + wire_niOlii_dataout <= wire_niOO1i_dataout AND ni111O; + wire_niOlil_dataout <= wire_niOO1l_dataout AND ni111O; + wire_niOliO_dataout <= dec_data(8) OR ni110i; + wire_niOll_dataout <= wire_nl10l_dataout WHEN nii00O = '1' ELSE wire_nii_dataout; + wire_niOlli_dataout <= dec_data(9) OR ni110i; + wire_niOlll_dataout <= dec_data(10) OR ni110i; + wire_niOllO_dataout <= dec_data(11) AND NOT(ni110i); + wire_niOlO_dataout <= wire_nl10O_dataout WHEN nii00O = '1' ELSE wire_nilO_dataout; + wire_niOlOi_dataout <= dec_data(12) AND NOT(ni110i); + wire_niOlOl_dataout <= dec_data(13) AND NOT(ni110i); + wire_niOlOO_dataout <= dec_data(14) AND NOT(ni110i); + wire_niOO_dataout <= nill0i WHEN rxaui_s2gx_en = '1' ELSE nii0il; + wire_niOO0i_dataout <= wire_niOOOi_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOO0l_dataout <= wire_niOOOl_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOO0O_dataout <= wire_niOOOO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOO1i_dataout <= dec_data(15) AND NOT(ni110i); + wire_niOO1l_dataout <= dec_ctl(1) OR ni110i; + wire_niOO1O_dataout <= wire_niOOlO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOOi_dataout <= wire_nlOO_dataout AND NOT(n0OllO); + wire_niOOii_dataout <= wire_nl111i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOOil_dataout <= wire_nl111l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOOiO_dataout <= wire_nl111O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOOl_dataout <= wire_n1i_dataout OR n0OllO; + wire_niOOli_dataout <= wire_nl110i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOOll_dataout <= wire_nl110l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_niOOlO_dataout <= wire_nl110O_dataout AND NOT(wire_ni0i_dataout); + wire_niOOO_dataout <= wire_n1l_dataout OR n0OllO; + wire_niOOOi_dataout <= wire_nl11ii_dataout OR wire_ni0i_dataout; + wire_niOOOl_dataout <= wire_nl11il_dataout OR wire_ni0i_dataout; + wire_niOOOO_dataout <= wire_nl11iO_dataout OR wire_ni0i_dataout; + wire_nl_dataout <= n10Oi WHEN rxaui_s2gx_en = '1' ELSE nllO0l; + wire_nl000i_dataout <= dec_data(15) OR wire_ni0i_dataout; + wire_nl000l_dataout <= dec_ctl(1) OR wire_ni0i_dataout; + wire_nl000O_dataout <= wire_nl00OO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl001i_dataout <= dec_data(12) OR wire_ni0i_dataout; + wire_nl001l_dataout <= dec_data(13) OR wire_ni0i_dataout; + wire_nl001O_dataout <= dec_data(14) OR wire_ni0i_dataout; + wire_nl00ii_dataout <= wire_nl0i1i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00il_dataout <= wire_nl0i1l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00iO_dataout <= wire_nl0i1O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00li_dataout <= wire_nl0i0i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00ll_dataout <= wire_nl0i0l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00lO_dataout <= wire_nl0i0O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00Oi_dataout <= wire_nl0iii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00Ol_dataout <= wire_nl0iil_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl00OO_dataout <= wire_nl01lO_dataout OR n0Ol0i; + wire_nl010i_dataout <= wire_nl01Oi_dataout OR ni110i; + wire_nl010l_dataout <= wire_nl01Ol_dataout OR ni110i; + wire_nl010O_dataout <= wire_nl01OO_dataout AND NOT(ni110i); + wire_nl011i_dataout <= wire_nl01li_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl011l_dataout <= wire_nl01ll_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl011O_dataout <= wire_nl01lO_dataout OR ni110i; + wire_nl01i_dataout <= wire_nii_dataout OR n0OlOi; + wire_nl01ii_dataout <= wire_nl001i_dataout AND NOT(ni110i); + wire_nl01il_dataout <= wire_nl001l_dataout AND NOT(ni110i); + wire_nl01iO_dataout <= wire_nl001O_dataout AND NOT(ni110i); + wire_nl01l_dataout <= wire_nilO_dataout OR n0OlOi; + wire_nl01li_dataout <= wire_nl000i_dataout AND NOT(ni110i); + wire_nl01ll_dataout <= wire_nl000l_dataout OR ni110i; + wire_nl01lO_dataout <= dec_data(8) AND NOT(wire_ni0i_dataout); + wire_nl01Oi_dataout <= dec_data(9) OR wire_ni0i_dataout; + wire_nl01Ol_dataout <= dec_data(10) OR wire_ni0i_dataout; + wire_nl01OO_dataout <= dec_data(11) OR wire_ni0i_dataout; + wire_nl0i_dataout <= nillil WHEN rxaui_s2gx_en = '1' ELSE nii0lO; + wire_nl0i0i_dataout <= wire_nl001i_dataout AND NOT(n0Ol0i); + wire_nl0i0l_dataout <= wire_nl001l_dataout AND NOT(n0Ol0i); + wire_nl0i0O_dataout <= wire_nl001O_dataout AND NOT(n0Ol0i); + wire_nl0i1i_dataout <= wire_nl01Oi_dataout OR n0Ol0i; + wire_nl0i1l_dataout <= wire_nl01Ol_dataout OR n0Ol0i; + wire_nl0i1O_dataout <= wire_nl01OO_dataout AND NOT(n0Ol0i); + wire_nl0iii_dataout <= wire_nl000i_dataout AND NOT(n0Ol0i); + wire_nl0iil_dataout <= wire_nl000l_dataout OR n0Ol0i; + wire_nl0l_dataout <= nilliO WHEN rxaui_s2gx_en = '1' ELSE nii0Oi; + wire_nl0l0i_dataout <= wire_nliiii_dataout WHEN n0Ol1i = '1' ELSE wire_nl0lOi_dataout; + wire_nl0l0l_dataout <= wire_nliiil_dataout WHEN n0Ol1i = '1' ELSE wire_nl0lOl_dataout; + wire_nl0l0O_dataout <= wire_nliiiO_dataout WHEN n0Ol1i = '1' ELSE wire_nl0lOO_dataout; + wire_nl0l1O_dataout <= wire_nlii0O_dataout WHEN n0Ol1i = '1' ELSE wire_nl0llO_dataout; + wire_nl0lii_dataout <= wire_nliili_dataout WHEN n0Ol1i = '1' ELSE wire_nl0O1i_dataout; + wire_nl0lil_dataout <= wire_nliill_dataout WHEN n0Ol1i = '1' ELSE wire_nl0O1l_dataout; + wire_nl0liO_dataout <= wire_nliilO_dataout WHEN n0Ol1i = '1' ELSE wire_nl0O1O_dataout; + wire_nl0lli_dataout <= wire_nliiOi_dataout WHEN n0Ol1i = '1' ELSE wire_nl0O0i_dataout; + wire_nl0lll_dataout <= wire_nliiOl_dataout WHEN n0Ol1i = '1' ELSE wire_nl0O0l_dataout; + wire_nl0llO_dataout <= wire_nli1iO_dataout WHEN n0OilO = '1' ELSE wire_nl0O0O_dataout; + wire_nl0lOi_dataout <= wire_nli1li_dataout WHEN n0OilO = '1' ELSE wire_nl0Oii_dataout; + wire_nl0lOl_dataout <= wire_nli1ll_dataout WHEN n0OilO = '1' ELSE wire_nl0Oil_dataout; + wire_nl0lOO_dataout <= wire_nli1lO_dataout WHEN n0OilO = '1' ELSE wire_nl0OiO_dataout; + wire_nl0O_dataout <= nillli WHEN rxaui_s2gx_en = '1' ELSE nii0Ol; + wire_nl0O0i_dataout <= wire_nli01i_dataout WHEN n0OilO = '1' ELSE wire_nl0OOi_dataout; + wire_nl0O0l_dataout <= wire_nli01l_dataout WHEN n0OilO = '1' ELSE wire_nl0OOl_dataout; + wire_nl0O0O_dataout <= wire_nl0OOO_dataout AND ni111O; + wire_nl0O1i_dataout <= wire_nli1Oi_dataout WHEN n0OilO = '1' ELSE wire_nl0Oli_dataout; + wire_nl0O1l_dataout <= wire_nli1Ol_dataout WHEN n0OilO = '1' ELSE wire_nl0Oll_dataout; + wire_nl0O1O_dataout <= wire_nli1OO_dataout WHEN n0OilO = '1' ELSE wire_nl0OlO_dataout; + wire_nl0Oi_dataout <= wire_nliii_dataout OR ni1l0O; + wire_nl0Oii_dataout <= wire_nli11i_dataout AND ni111O; + wire_nl0Oil_dataout <= wire_nli11l_dataout AND ni111O; + wire_nl0OiO_dataout <= wire_nli11O_dataout AND ni111O; + wire_nl0Ol_dataout <= wire_nliil_dataout AND NOT(ni1l0O); + wire_nl0Oli_dataout <= wire_nli10i_dataout AND ni111O; + wire_nl0Oll_dataout <= wire_nli10l_dataout AND ni111O; + wire_nl0OlO_dataout <= wire_nli10O_dataout AND ni111O; + wire_nl0OO_dataout <= wire_nliiO_dataout AND NOT(ni1l0O); + wire_nl0OOi_dataout <= wire_nli1ii_dataout AND ni111O; + wire_nl0OOl_dataout <= wire_nli1il_dataout AND ni111O; + wire_nl0OOO_dataout <= dec_data(16) OR ni110i; + wire_nl100i_dataout <= wire_nl10Oi_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl100l_dataout <= wire_nl10Ol_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl100O_dataout <= wire_nl10OO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl101i_dataout <= wire_nl10li_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl101l_dataout <= wire_nl10ll_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl101O_dataout <= wire_nl10lO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl10i_dataout <= wire_n0O_dataout OR n0OllO; + wire_nl10ii_dataout <= wire_nl1i1i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl10il_dataout <= wire_nl1i1l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl10iO_dataout <= wire_nl1ilO_dataout WHEN ni1lii = '1' ELSE wire_nl1i1O_dataout; + wire_nl10l_dataout <= wire_nii_dataout OR n0OllO; + wire_nl10li_dataout <= wire_nl1iOi_dataout WHEN ni1lii = '1' ELSE wire_nl1i0i_dataout; + wire_nl10ll_dataout <= wire_nl1iOl_dataout WHEN ni1lii = '1' ELSE wire_nl1i0l_dataout; + wire_nl10lO_dataout <= wire_nl1iOO_dataout WHEN ni1lii = '1' ELSE wire_nl1i0O_dataout; + wire_nl10O_dataout <= wire_nilO_dataout OR n0OllO; + wire_nl10Oi_dataout <= wire_nl1l1i_dataout WHEN ni1lii = '1' ELSE wire_nl1iii_dataout; + wire_nl10Ol_dataout <= wire_nl1l1l_dataout WHEN ni1lii = '1' ELSE wire_nl1iil_dataout; + wire_nl10OO_dataout <= wire_nl1l1O_dataout WHEN ni1lii = '1' ELSE wire_nl1iiO_dataout; + wire_nl110i_dataout <= wire_nl11Oi_dataout OR wire_ni0i_dataout; + wire_nl110l_dataout <= wire_nl11Ol_dataout OR wire_ni0i_dataout; + wire_nl110O_dataout <= dec_data(8) OR n0OiOi; + wire_nl111i_dataout <= wire_nl11li_dataout OR wire_ni0i_dataout; + wire_nl111l_dataout <= wire_nl11ll_dataout OR wire_ni0i_dataout; + wire_nl111O_dataout <= wire_nl11lO_dataout OR wire_ni0i_dataout; + wire_nl11i_dataout <= wire_n1O_dataout OR n0OllO; + wire_nl11ii_dataout <= dec_data(9) OR n0OiOi; + wire_nl11il_dataout <= dec_data(10) OR n0OiOi; + wire_nl11iO_dataout <= dec_data(11) AND NOT(n0OiOi); + wire_nl11l_dataout <= wire_n0i_dataout OR n0OllO; + wire_nl11li_dataout <= dec_data(12) AND NOT(n0OiOi); + wire_nl11ll_dataout <= dec_data(13) AND NOT(n0OiOi); + wire_nl11lO_dataout <= dec_data(14) AND NOT(n0OiOi); + wire_nl11O_dataout <= wire_n0l_dataout OR n0OllO; + wire_nl11Oi_dataout <= dec_data(15) AND NOT(n0OiOi); + wire_nl11Ol_dataout <= dec_ctl(1) OR n0OiOi; + wire_nl11OO_dataout <= wire_nl10iO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl1i_dataout <= nill0l WHEN rxaui_s2gx_en = '1' ELSE nii0iO; + wire_nl1i0i_dataout <= wire_niOOOi_dataout OR ni1l1l; + wire_nl1i0l_dataout <= wire_niOOOl_dataout OR ni1l1l; + wire_nl1i0O_dataout <= n0OliO WHEN ni1l1l = '1' ELSE wire_niOOOO_dataout; + wire_nl1i1i_dataout <= wire_nl1l0i_dataout WHEN ni1lii = '1' ELSE wire_nl1ili_dataout; + wire_nl1i1l_dataout <= wire_nl1l0l_dataout WHEN ni1lii = '1' ELSE wire_nl1ill_dataout; + wire_nl1i1O_dataout <= wire_w_lg_n0OliO228w(0) WHEN ni1l1l = '1' ELSE wire_niOOlO_dataout; + wire_nl1iii_dataout <= n0OliO WHEN ni1l1l = '1' ELSE wire_nl111i_dataout; + wire_nl1iil_dataout <= n0OliO WHEN ni1l1l = '1' ELSE wire_nl111l_dataout; + wire_nl1iiO_dataout <= n0OliO WHEN ni1l1l = '1' ELSE wire_nl111O_dataout; + wire_nl1ili_dataout <= n0OliO WHEN ni1l1l = '1' ELSE wire_nl110i_dataout; + wire_nl1ill_dataout <= wire_nl110l_dataout OR ni1l1l; + wire_nl1ilO_dataout <= wire_nl110O_dataout AND NOT(n0Olii); + wire_nl1iO_dataout <= wire_nlOO_dataout AND NOT(n0OlOi); + wire_nl1iOi_dataout <= wire_nl11ii_dataout OR n0Olii; + wire_nl1iOl_dataout <= wire_nl11il_dataout OR n0Olii; + wire_nl1iOO_dataout <= wire_nl11iO_dataout OR n0Olii; + wire_nl1l_dataout <= nill0O WHEN rxaui_s2gx_en = '1' ELSE nii0li; + wire_nl1l0i_dataout <= wire_nl11Oi_dataout OR n0Olii; + wire_nl1l0l_dataout <= wire_nl11Ol_dataout OR n0Olii; + wire_nl1l1i_dataout <= wire_nl11li_dataout OR n0Olii; + wire_nl1l1l_dataout <= wire_nl11ll_dataout OR n0Olii; + wire_nl1l1O_dataout <= wire_nl11lO_dataout OR n0Olii; + wire_nl1li_dataout <= wire_n1i_dataout OR n0OlOi; + wire_nl1ll_dataout <= wire_n1l_dataout OR n0OlOi; + wire_nl1lO_dataout <= wire_n1O_dataout OR n0OlOi; + wire_nl1lOO_dataout <= wire_nl000O_dataout WHEN n0Ol1i = '1' ELSE wire_nl1OiO_dataout; + wire_nl1O_dataout <= nillii WHEN rxaui_s2gx_en = '1' ELSE nii0ll; + wire_nl1O0i_dataout <= wire_nl00li_dataout WHEN n0Ol1i = '1' ELSE wire_nl1OOi_dataout; + wire_nl1O0l_dataout <= wire_nl00ll_dataout WHEN n0Ol1i = '1' ELSE wire_nl1OOl_dataout; + wire_nl1O0O_dataout <= wire_nl00lO_dataout WHEN n0Ol1i = '1' ELSE wire_nl1OOO_dataout; + wire_nl1O1i_dataout <= wire_nl00ii_dataout WHEN n0Ol1i = '1' ELSE wire_nl1Oli_dataout; + wire_nl1O1l_dataout <= wire_nl00il_dataout WHEN n0Ol1i = '1' ELSE wire_nl1Oll_dataout; + wire_nl1O1O_dataout <= wire_nl00iO_dataout WHEN n0Ol1i = '1' ELSE wire_nl1OlO_dataout; + wire_nl1Oi_dataout <= wire_n0i_dataout OR n0OlOi; + wire_nl1Oii_dataout <= wire_nl00Oi_dataout WHEN n0Ol1i = '1' ELSE wire_nl011i_dataout; + wire_nl1Oil_dataout <= wire_nl00Ol_dataout WHEN n0Ol1i = '1' ELSE wire_nl011l_dataout; + wire_nl1OiO_dataout <= wire_nl011O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl1Ol_dataout <= wire_n0l_dataout OR n0OlOi; + wire_nl1Oli_dataout <= wire_nl010i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl1Oll_dataout <= wire_nl010l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl1OlO_dataout <= wire_nl010O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl1OO_dataout <= wire_n0O_dataout OR n0OlOi; + wire_nl1OOi_dataout <= wire_nl01ii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl1OOl_dataout <= wire_nl01il_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nl1OOO_dataout <= wire_nl01iO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli_dataout <= n10iO WHEN rxaui_s2gx_en = '1' ELSE nllO1i; + wire_nli00i_dataout <= wire_nli0Oi_dataout OR wire_ni0l_dataout; + wire_nli00l_dataout <= wire_nli0Ol_dataout OR wire_ni0l_dataout; + wire_nli00O_dataout <= wire_nli0OO_dataout OR wire_ni0l_dataout; + wire_nli01i_dataout <= wire_nli0li_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli01l_dataout <= wire_nli0ll_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli01O_dataout <= wire_nli0lO_dataout AND NOT(wire_ni0l_dataout); + wire_nli0i_dataout <= wire_nliOi_dataout AND NOT(ni1l0O); + wire_nli0ii_dataout <= wire_nlii1i_dataout OR wire_ni0l_dataout; + wire_nli0il_dataout <= wire_nlii1l_dataout OR wire_ni0l_dataout; + wire_nli0iO_dataout <= wire_nlii1O_dataout OR wire_ni0l_dataout; + wire_nli0l_dataout <= wire_nliOl_dataout AND NOT(ni1l0O); + wire_nli0li_dataout <= wire_nlii0i_dataout OR wire_ni0l_dataout; + wire_nli0ll_dataout <= wire_nlii0l_dataout OR wire_ni0l_dataout; + wire_nli0lO_dataout <= dec_data(16) OR n0OiOi; + wire_nli0O_dataout <= wire_nliOO_dataout AND NOT(ni1l0O); + wire_nli0Oi_dataout <= dec_data(17) OR n0OiOi; + wire_nli0Ol_dataout <= dec_data(18) OR n0OiOi; + wire_nli0OO_dataout <= dec_data(19) AND NOT(n0OiOi); + wire_nli10i_dataout <= dec_data(20) AND NOT(ni110i); + wire_nli10l_dataout <= dec_data(21) AND NOT(ni110i); + wire_nli10O_dataout <= dec_data(22) AND NOT(ni110i); + wire_nli11i_dataout <= dec_data(17) OR ni110i; + wire_nli11l_dataout <= dec_data(18) OR ni110i; + wire_nli11O_dataout <= dec_data(19) AND NOT(ni110i); + wire_nli1i_dataout <= wire_nlili_dataout AND NOT(ni1l0O); + wire_nli1ii_dataout <= dec_data(23) AND NOT(ni110i); + wire_nli1il_dataout <= dec_ctl(2) OR ni110i; + wire_nli1iO_dataout <= wire_nli01O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli1l_dataout <= wire_nlill_dataout AND NOT(ni1l0O); + wire_nli1li_dataout <= wire_nli00i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli1ll_dataout <= wire_nli00l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli1lO_dataout <= wire_nli00O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli1O_dataout <= wire_nlilO_dataout AND NOT(ni1l0O); + wire_nli1Oi_dataout <= wire_nli0ii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli1Ol_dataout <= wire_nli0il_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nli1OO_dataout <= wire_nli0iO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlii_dataout <= niO0ll WHEN rxaui_s2gx_en = '1' ELSE nillll; + wire_nlii0i_dataout <= dec_data(23) AND NOT(n0OiOi); + wire_nlii0l_dataout <= dec_ctl(2) OR n0OiOi; + wire_nlii0O_dataout <= wire_nliiOO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlii1i_dataout <= dec_data(20) AND NOT(n0OiOi); + wire_nlii1l_dataout <= dec_data(21) AND NOT(n0OiOi); + wire_nlii1O_dataout <= dec_data(22) AND NOT(n0OiOi); + wire_nliii_dataout <= wire_nll1i_dataout WHEN n0OO0i = '1' ELSE wire_nil_dataout; + wire_nliiii_dataout <= wire_nlil1i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliiil_dataout <= wire_nlil1l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliiiO_dataout <= wire_nlil1O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliil_dataout <= wire_nll1l_dataout WHEN n0OO0i = '1' ELSE wire_niO_dataout; + wire_nliili_dataout <= wire_nlil0i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliill_dataout <= wire_nlil0l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliilO_dataout <= wire_nlil0O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliiO_dataout <= wire_nll1O_dataout WHEN n0OO0i = '1' ELSE wire_nli_dataout; + wire_nliiOi_dataout <= wire_nlilii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliiOl_dataout <= wire_nlilil_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nliiOO_dataout <= wire_nliO1O_dataout WHEN ni1lii = '1' ELSE wire_nliliO_dataout; + wire_nlil_dataout <= nl1l0O WHEN rxaui_s2gx_en = '1' ELSE niO01O; + wire_nlil0i_dataout <= wire_nliOii_dataout WHEN ni1lii = '1' ELSE wire_nlilOi_dataout; + wire_nlil0l_dataout <= wire_nliOil_dataout WHEN ni1lii = '1' ELSE wire_nlilOl_dataout; + wire_nlil0O_dataout <= wire_nliOiO_dataout WHEN ni1lii = '1' ELSE wire_nlilOO_dataout; + wire_nlil1i_dataout <= wire_nliO0i_dataout WHEN ni1lii = '1' ELSE wire_nlilli_dataout; + wire_nlil1l_dataout <= wire_nliO0l_dataout WHEN ni1lii = '1' ELSE wire_nlilll_dataout; + wire_nlil1O_dataout <= wire_nliO0O_dataout WHEN ni1lii = '1' ELSE wire_nlillO_dataout; + wire_nlili_dataout <= wire_nll0i_dataout WHEN n0OO0i = '1' ELSE wire_nll_dataout; + wire_nlilii_dataout <= wire_nliOli_dataout WHEN ni1lii = '1' ELSE wire_nliO1i_dataout; + wire_nlilil_dataout <= wire_nliOll_dataout WHEN ni1lii = '1' ELSE wire_nliO1l_dataout; + wire_nliliO_dataout <= wire_w_lg_n0OlOi219w(0) WHEN n0OOii = '1' ELSE wire_nli01O_dataout; + wire_nlill_dataout <= wire_nll0l_dataout WHEN n0OO0i = '1' ELSE wire_nlO_dataout; + wire_nlilli_dataout <= wire_nli00i_dataout OR n0OOii; + wire_nlilll_dataout <= wire_nli00l_dataout OR n0OOii; + wire_nlillO_dataout <= n0OlOi WHEN n0OOii = '1' ELSE wire_nli00O_dataout; + wire_nlilO_dataout <= wire_nll0O_dataout WHEN n0OO0i = '1' ELSE wire_ni_dataout; + wire_nlilOi_dataout <= n0OlOi WHEN n0OOii = '1' ELSE wire_nli0ii_dataout; + wire_nlilOl_dataout <= n0OlOi WHEN n0OOii = '1' ELSE wire_nli0il_dataout; + wire_nlilOO_dataout <= n0OlOi WHEN n0OOii = '1' ELSE wire_nli0iO_dataout; + wire_nliO_dataout <= nl1lii WHEN rxaui_s2gx_en = '1' ELSE niO00i; + wire_nliO0i_dataout <= wire_nli0Oi_dataout OR n0OllO; + wire_nliO0l_dataout <= wire_nli0Ol_dataout OR n0OllO; + wire_nliO0O_dataout <= wire_nli0OO_dataout OR n0OllO; + wire_nliO1i_dataout <= n0OlOi WHEN n0OOii = '1' ELSE wire_nli0li_dataout; + wire_nliO1l_dataout <= wire_nli0ll_dataout OR n0OOii; + wire_nliO1O_dataout <= wire_nli0lO_dataout AND NOT(n0OllO); + wire_nliOi_dataout <= wire_nllii_dataout WHEN n0OO0i = '1' ELSE wire_nl_dataout; + wire_nliOii_dataout <= wire_nlii1i_dataout OR n0OllO; + wire_nliOil_dataout <= wire_nlii1l_dataout OR n0OllO; + wire_nliOiO_dataout <= wire_nlii1O_dataout OR n0OllO; + wire_nliOl_dataout <= wire_nllil_dataout WHEN n0OO0i = '1' ELSE wire_nO_dataout; + wire_nliOli_dataout <= wire_nlii0i_dataout OR n0OllO; + wire_nliOll_dataout <= wire_nlii0l_dataout OR n0OllO; + wire_nliOO_dataout <= wire_nlliO_dataout WHEN n0OO0i = '1' ELSE wire_niOi_dataout; + wire_nll_dataout <= n10li WHEN rxaui_s2gx_en = '1' ELSE nllO1l; + wire_nll00i_dataout <= wire_nll0Oi_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll00l_dataout <= wire_nll0Ol_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll00O_dataout <= wire_nll0OO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll01i_dataout <= wire_nll0li_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll01l_dataout <= wire_nll0ll_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll01O_dataout <= wire_nll0lO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll0i_dataout <= wire_nll_dataout OR n0OO1i; + wire_nll0ii_dataout <= wire_nlli1i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll0il_dataout <= wire_nlli1l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nll0iO_dataout <= wire_nlli1O_dataout OR ni110i; + wire_nll0l_dataout <= wire_nlO_dataout OR n0OO1i; + wire_nll0li_dataout <= wire_nlli0i_dataout OR ni110i; + wire_nll0ll_dataout <= wire_nlli0l_dataout OR ni110i; + wire_nll0lO_dataout <= wire_nlli0O_dataout AND NOT(ni110i); + wire_nll0O_dataout <= wire_ni_dataout OR n0OO1i; + wire_nll0Oi_dataout <= wire_nlliii_dataout AND NOT(ni110i); + wire_nll0Ol_dataout <= wire_nlliil_dataout AND NOT(ni110i); + wire_nll0OO_dataout <= wire_nlliiO_dataout AND NOT(ni110i); + wire_nll10O_dataout <= wire_nllilO_dataout WHEN n0Ol1i = '1' ELSE wire_nll1OO_dataout; + wire_nll1i_dataout <= wire_nil_dataout AND NOT(n0OO1i); + wire_nll1ii_dataout <= wire_nlliOi_dataout WHEN n0Ol1i = '1' ELSE wire_nll01i_dataout; + wire_nll1il_dataout <= wire_nlliOl_dataout WHEN n0Ol1i = '1' ELSE wire_nll01l_dataout; + wire_nll1iO_dataout <= wire_nlliOO_dataout WHEN n0Ol1i = '1' ELSE wire_nll01O_dataout; + wire_nll1l_dataout <= wire_niO_dataout OR n0OO1i; + wire_nll1li_dataout <= wire_nlll1i_dataout WHEN n0Ol1i = '1' ELSE wire_nll00i_dataout; + wire_nll1ll_dataout <= wire_nlll1l_dataout WHEN n0Ol1i = '1' ELSE wire_nll00l_dataout; + wire_nll1lO_dataout <= wire_nlll1O_dataout WHEN n0Ol1i = '1' ELSE wire_nll00O_dataout; + wire_nll1O_dataout <= wire_nli_dataout OR n0OO1i; + wire_nll1Oi_dataout <= wire_nlll0i_dataout WHEN n0Ol1i = '1' ELSE wire_nll0ii_dataout; + wire_nll1Ol_dataout <= wire_nlll0l_dataout WHEN n0Ol1i = '1' ELSE wire_nll0il_dataout; + wire_nll1OO_dataout <= wire_nll0iO_dataout OR wire_w_lg_ni111O120w(0); + wire_nlli_dataout <= nl1lil WHEN rxaui_s2gx_en = '1' ELSE niO00l; + wire_nlli0i_dataout <= dec_data(17) OR wire_ni0l_dataout; + wire_nlli0l_dataout <= dec_data(18) OR wire_ni0l_dataout; + wire_nlli0O_dataout <= dec_data(19) OR wire_ni0l_dataout; + wire_nlli1i_dataout <= wire_nllili_dataout AND NOT(ni110i); + wire_nlli1l_dataout <= wire_nllill_dataout OR ni110i; + wire_nlli1O_dataout <= dec_data(16) AND NOT(wire_ni0l_dataout); + wire_nllii_dataout <= wire_nl_dataout OR n0OO1i; + wire_nlliii_dataout <= dec_data(20) OR wire_ni0l_dataout; + wire_nlliil_dataout <= dec_data(21) OR wire_ni0l_dataout; + wire_nlliiO_dataout <= dec_data(22) OR wire_ni0l_dataout; + wire_nllil_dataout <= wire_nO_dataout OR n0OO1i; + wire_nllili_dataout <= dec_data(23) OR wire_ni0l_dataout; + wire_nllill_dataout <= dec_ctl(2) OR wire_ni0l_dataout; + wire_nllilO_dataout <= wire_nlll0O_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlliO_dataout <= wire_niOi_dataout OR n0OO1i; + wire_nlliOi_dataout <= wire_nlllii_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlliOl_dataout <= wire_nlllil_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlliOO_dataout <= wire_nllliO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlll_dataout <= nl1liO WHEN rxaui_s2gx_en = '1' ELSE niO00O; + wire_nlll0i_dataout <= wire_nlllOi_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlll0l_dataout <= wire_nlllOl_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlll0O_dataout <= wire_nlli1O_dataout OR n0Ol1O; + wire_nlll1i_dataout <= wire_nlllli_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlll1l_dataout <= wire_nlllll_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlll1O_dataout <= wire_nllllO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlllii_dataout <= wire_nlli0i_dataout OR n0Ol1O; + wire_nlllil_dataout <= wire_nlli0l_dataout OR n0Ol1O; + wire_nllliO_dataout <= wire_nlli0O_dataout AND NOT(n0Ol1O); + wire_nlllli_dataout <= wire_nlliii_dataout AND NOT(n0Ol1O); + wire_nlllll_dataout <= wire_nlliil_dataout AND NOT(n0Ol1O); + wire_nllllO_dataout <= wire_nlliiO_dataout AND NOT(n0Ol1O); + wire_nlllOi_dataout <= wire_nllili_dataout AND NOT(n0Ol1O); + wire_nlllOl_dataout <= wire_nllill_dataout OR n0Ol1O; + wire_nllO_dataout <= nl1lli WHEN rxaui_s2gx_en = '1' ELSE niO0ii; + wire_nllOiO_dataout <= wire_nlOlOl_dataout WHEN n0Ol1i = '1' ELSE wire_nlO11O_dataout; + wire_nllOli_dataout <= wire_nlOlOO_dataout WHEN n0Ol1i = '1' ELSE wire_nlO10i_dataout; + wire_nllOll_dataout <= wire_nlOO1i_dataout WHEN n0Ol1i = '1' ELSE wire_nlO10l_dataout; + wire_nllOlO_dataout <= wire_nlOO1l_dataout WHEN n0Ol1i = '1' ELSE wire_nlO10O_dataout; + wire_nllOOi_dataout <= wire_nlOO1O_dataout WHEN n0Ol1i = '1' ELSE wire_nlO1ii_dataout; + wire_nllOOl_dataout <= wire_nlOO0i_dataout WHEN n0Ol1i = '1' ELSE wire_nlO1il_dataout; + wire_nllOOO_dataout <= wire_nlOO0l_dataout WHEN n0Ol1i = '1' ELSE wire_nlO1iO_dataout; + wire_nlO_dataout <= n10ll WHEN rxaui_s2gx_en = '1' ELSE nllO1O; + wire_nlO00i_dataout <= wire_nlO0Oi_dataout AND ni111O; + wire_nlO00l_dataout <= wire_nlO0Ol_dataout AND ni111O; + wire_nlO00O_dataout <= dec_data(24) OR ni110i; + wire_nlO01i_dataout <= wire_nlO0li_dataout AND ni111O; + wire_nlO01l_dataout <= wire_nlO0ll_dataout AND ni111O; + wire_nlO01O_dataout <= wire_nlO0lO_dataout AND ni111O; + wire_nlO0ii_dataout <= dec_data(25) OR ni110i; + wire_nlO0il_dataout <= dec_data(26) OR ni110i; + wire_nlO0iO_dataout <= dec_data(27) AND NOT(ni110i); + wire_nlO0li_dataout <= dec_data(28) AND NOT(ni110i); + wire_nlO0ll_dataout <= dec_data(29) AND NOT(ni110i); + wire_nlO0lO_dataout <= dec_data(30) AND NOT(ni110i); + wire_nlO0Oi_dataout <= dec_data(31) AND NOT(ni110i); + wire_nlO0Ol_dataout <= dec_ctl(3) OR ni110i; + wire_nlO0OO_dataout <= wire_nlOiiO_dataout OR wire_w_lg_ni111O120w(0); + wire_nlO10i_dataout <= wire_nlOi1i_dataout WHEN n0OilO = '1' ELSE wire_nlO1Oi_dataout; + wire_nlO10l_dataout <= wire_nlOi1l_dataout WHEN n0OilO = '1' ELSE wire_nlO1Ol_dataout; + wire_nlO10O_dataout <= wire_nlOi1O_dataout WHEN n0OilO = '1' ELSE wire_nlO1OO_dataout; + wire_nlO11i_dataout <= wire_nlOO0O_dataout WHEN n0Ol1i = '1' ELSE wire_nlO1li_dataout; + wire_nlO11l_dataout <= wire_nlOOii_dataout WHEN n0Ol1i = '1' ELSE wire_nlO1ll_dataout; + wire_nlO11O_dataout <= wire_nlO0OO_dataout WHEN n0OilO = '1' ELSE wire_nlO1lO_dataout; + wire_nlO1i_dataout <= wire_w_lg_ni110i128w(0) AND NOT(n0OOll); + wire_nlO1ii_dataout <= wire_nlOi0i_dataout WHEN n0OilO = '1' ELSE wire_nlO01i_dataout; + wire_nlO1il_dataout <= wire_nlOi0l_dataout WHEN n0OilO = '1' ELSE wire_nlO01l_dataout; + wire_nlO1iO_dataout <= wire_nlOi0O_dataout WHEN n0OilO = '1' ELSE wire_nlO01O_dataout; + wire_nlO1l_dataout <= ni110i AND NOT(n0OOll); + wire_nlO1li_dataout <= wire_nlOiii_dataout WHEN n0OilO = '1' ELSE wire_nlO00i_dataout; + wire_nlO1ll_dataout <= wire_nlOiil_dataout WHEN n0OilO = '1' ELSE wire_nlO00l_dataout; + wire_nlO1lO_dataout <= wire_nlO00O_dataout OR NOT(ni111O); + wire_nlO1Oi_dataout <= wire_nlO0ii_dataout AND ni111O; + wire_nlO1Ol_dataout <= wire_nlO0il_dataout AND ni111O; + wire_nlO1OO_dataout <= wire_nlO0iO_dataout AND ni111O; + wire_nlOi_dataout <= nl1lll WHEN rxaui_s2gx_en = '1' ELSE niO0il; + wire_nlOi0i_dataout <= wire_nlOiOi_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOi0l_dataout <= wire_nlOiOl_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOi0O_dataout <= wire_nlOiOO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOi1i_dataout <= wire_nlOili_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOi1l_dataout <= wire_nlOill_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOi1O_dataout <= wire_nlOilO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOiii_dataout <= wire_nlOl1i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOiil_dataout <= wire_nlOl1l_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOiiO_dataout <= wire_nlOl1O_dataout AND NOT(wire_ni0O_dataout); + wire_nlOili_dataout <= wire_nlOl0i_dataout OR wire_ni0O_dataout; + wire_nlOill_dataout <= wire_nlOl0l_dataout OR wire_ni0O_dataout; + wire_nlOilO_dataout <= wire_nlOl0O_dataout OR wire_ni0O_dataout; + wire_nlOiOi_dataout <= wire_nlOlii_dataout OR wire_ni0O_dataout; + wire_nlOiOl_dataout <= wire_nlOlil_dataout OR wire_ni0O_dataout; + wire_nlOiOO_dataout <= wire_nlOliO_dataout OR wire_ni0O_dataout; + wire_nlOl_dataout <= nl1llO WHEN rxaui_s2gx_en = '1' ELSE niO0iO; + wire_nlOl0i_dataout <= dec_data(25) OR n0OiOi; + wire_nlOl0l_dataout <= dec_data(26) OR n0OiOi; + wire_nlOl0O_dataout <= dec_data(27) AND NOT(n0OiOi); + wire_nlOl1i_dataout <= wire_nlOlli_dataout OR wire_ni0O_dataout; + wire_nlOl1l_dataout <= wire_nlOlll_dataout OR wire_ni0O_dataout; + wire_nlOl1O_dataout <= dec_data(24) OR n0OiOi; + wire_nlOlii_dataout <= dec_data(28) AND NOT(n0OiOi); + wire_nlOlil_dataout <= dec_data(29) AND NOT(n0OiOi); + wire_nlOliO_dataout <= dec_data(30) AND NOT(n0OiOi); + wire_nlOlli_dataout <= dec_data(31) AND NOT(n0OiOi); + wire_nlOlll_dataout <= dec_ctl(3) OR n0OiOi; + wire_nlOlOl_dataout <= wire_nlOOil_dataout OR wire_w_lg_ni111O120w(0); + wire_nlOlOO_dataout <= wire_nlOOiO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOO_dataout <= nl0l1l WHEN rxaui_s2gx_en = '1' ELSE nl1lOl; + wire_nlOO0i_dataout <= wire_nlOOOi_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOO0l_dataout <= wire_nlOOOl_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOO0O_dataout <= wire_nlOOOO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOO1i_dataout <= wire_nlOOli_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOO1l_dataout <= wire_nlOOll_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOO1O_dataout <= wire_nlOOlO_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOOi_dataout <= wire_nlOOl_dataout OR nlOiO; + wire_nlOOii_dataout <= wire_n111i_dataout AND NOT(wire_w_lg_ni111O120w(0)); + wire_nlOOil_dataout <= wire_n11lO_dataout WHEN ni1lii = '1' ELSE wire_n111l_dataout; + wire_nlOOiO_dataout <= wire_n11Oi_dataout WHEN ni1lii = '1' ELSE wire_n111O_dataout; + wire_nlOOl_dataout <= nlOll AND NOT((wire_w_lg_w_lg_ni111O120w121w(0) OR (NOT (n0OOlO32 XOR n0OOlO31)))); + wire_nlOOli_dataout <= wire_n11Ol_dataout WHEN ni1lii = '1' ELSE wire_n110i_dataout; + wire_nlOOll_dataout <= wire_n11OO_dataout WHEN ni1lii = '1' ELSE wire_n110l_dataout; + wire_nlOOlO_dataout <= wire_n101i_dataout WHEN ni1lii = '1' ELSE wire_n110O_dataout; + wire_nlOOOi_dataout <= wire_n101l_dataout WHEN ni1lii = '1' ELSE wire_n11ii_dataout; + wire_nlOOOl_dataout <= wire_n101O_dataout WHEN ni1lii = '1' ELSE wire_n11il_dataout; + wire_nlOOOO_dataout <= wire_n100i_dataout WHEN ni1lii = '1' ELSE wire_n11iO_dataout; + wire_nO_dataout <= n10Ol WHEN rxaui_s2gx_en = '1' ELSE nllO0O; + wire_nllOi_data <= ( wire_nlO1i_dataout & "0" & wire_nlO1i_dataout & wire_nlO1i_dataout); + wire_nllOi_sel <= ( nlO0O & nlO0l); + nllOi : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOi_data, + o => wire_nllOi_o, + sel => wire_nllOi_sel + ); + wire_nllOl_data <= ( wire_n0OOil38_w_lg_w_lg_q150w151w & "0" & wire_n0OOiO36_w_lg_w_lg_q145w146w & wire_nlO1l_dataout); + wire_nllOl_sel <= ( nlO0O & nlO0l); + nllOl : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOl_data, + o => wire_nllOl_o, + sel => wire_nllOl_sel + ); + wire_nllOO_w_lg_o126w(0) <= NOT wire_nllOO_o; + wire_nllOO_data <= ( n0OOll & "1" & n0OOll & n0OOll); + wire_nllOO_sel <= ( nlO0O & wire_n0OOli34_w_lg_w_lg_q129w130w); + nllOO : oper_mux + GENERIC MAP ( + width_data => 4, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOO_data, + o => wire_nllOO_o, + sel => wire_nllOO_sel + ); + + END RTL; --cycloneiv_hssi_rcv_sm +--synopsys translate_on +--VALID FILE + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_quad_reset IS + PORT ( + -- Common reset inputs + -- Common reset CRAMs + -- CMU reset inputs + -- CMU reset CRAMs + -- CMU powerdown inputs + -- CMU powerdown CRAMs + -- CMU reset outputs + -- CMU powerdown outputs + -- Other outputs + + -- Common reset inputs + entest : IN STD_LOGIC; -- Test mode control from Control block + plniotri : IN STD_LOGIC; -- PLL output enable + npor : IN STD_LOGIC; -- Power on reset + frzreg : IN STD_LOGIC; -- Freeze register during power-up + pllurst : IN STD_LOGIC; -- PLL user reset + + -- Common reset CRAMs + rpllurst : IN STD_LOGIC; -- Gating CRAM for PLLURST + rpowerdown : IN STD_LOGIC; -- Quad power down CRAM + rreset : IN STD_LOGIC; -- Quad reset CRAM + + -- CMU reset inputs + rxurstcmu : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Dynamic signal for CMU[1:0]_RXPMA_RSTB + + -- CMU reset CRAMs + rrxurstcmu : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Gating CRAM for dynamic signal rxurstcmu + rrx_cmu_rst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- TXPLL / RXPLL reset + + -- CMU powerdown inputs + ucmurx_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Dynamic signal for CMU[1:0]_RX_PDB + + -- CMU powerdown CRAMs + rclk_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_powdnr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_cru_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_urx_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_rx_ib_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_powdnt : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_tx_ob_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_tx_cgb_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_rx_det_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- CMU reset outputs + cmu0_rxpma_rstb : OUT STD_LOGIC; + cmu0_txpma_rstb : OUT STD_LOGIC; + cmu0_cru_rstb : OUT STD_LOGIC; + + cmu1_rxpma_rstb : OUT STD_LOGIC; + cmu1_txpma_rstb : OUT STD_LOGIC; + cmu1_cru_rstb : OUT STD_LOGIC; + + -- CMU powerdown outputs + cmu0_rx_pdb : OUT STD_LOGIC; + cmu0_cru_pdb : OUT STD_LOGIC; + cmu0_clk_pdb : OUT STD_LOGIC; + cmu0_tx_pdb : OUT STD_LOGIC; + cmu0_cgb_pdb : OUT STD_LOGIC; + cmu0_rx_det_pdb : OUT STD_LOGIC; + + cmu1_rx_pdb : OUT STD_LOGIC; + cmu1_cru_pdb : OUT STD_LOGIC; + cmu1_clk_pdb : OUT STD_LOGIC; + cmu1_tx_pdb : OUT STD_LOGIC; + cmu1_cgb_pdb : OUT STD_LOGIC; + cmu1_rx_det_pdb : OUT STD_LOGIC; + + -- Other outputs + mdio_rst : OUT STD_LOGIC; -- MDIO reset + hard_reset : OUT STD_LOGIC; -- Output HARD_RESET signal for other MDIO modules + soft_reset_all_hssi : OUT STD_LOGIC -- Quad soft reset output + ); +END cycloneiv_hssi_cmu_quad_reset; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_quad_reset IS + + ------------------------------------ + -- Wiring section for Resets + ------------------------------------ + SIGNAL cmu0_rxpma_rst_hssi : STD_LOGIC; + SIGNAL cmu1_rxpma_rst_hssi : STD_LOGIC; + + ------------------------------------ + -- Wiring section for Powerdowns + ------------------------------------ + SIGNAL cmu0_cru_pd_hssi : STD_LOGIC; + SIGNAL cmu0_rx_pd_hssi : STD_LOGIC; + SIGNAL cmu0_tx_pd_hssi : STD_LOGIC; + SIGNAL cmu0_cgb_pd_hssi : STD_LOGIC; + SIGNAL cmu0_rx_det_pd_hssi : STD_LOGIC; + + SIGNAL cmu1_cru_pd_hssi : STD_LOGIC; + SIGNAL cmu1_rx_pd_hssi : STD_LOGIC; + SIGNAL cmu1_tx_pd_hssi : STD_LOGIC; + SIGNAL cmu1_cgb_pd_hssi : STD_LOGIC; + SIGNAL cmu1_rx_det_pd_hssi : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL hard_reset_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + hard_reset <= hard_reset_xhdl0; + + ------------------------------------ + -- Other reset outputs + ------------------------------------ + -- SP update 10/17/07 - enpll term removed from hard_reset + -- assign hard_reset = ~(plniotri & ~entest & npor & (enpll | rnenbpin) & (~pllurst | ~rpllurst)); + hard_reset_xhdl0 <= NOT((plniotri AND NOT(entest) AND npor AND (NOT(pllurst) OR NOT(rpllurst)))); + soft_reset_all_hssi <= frzreg OR rpowerdown OR rreset; + mdio_rst <= NOT((plniotri AND NOT(entest) AND npor)); + + ------------------------------------ + -- CMU reset internal signals + ------------------------------------ + cmu0_rxpma_rst_hssi <= (rxurstcmu(0) AND rrxurstcmu(0)) OR rreset; + cmu1_rxpma_rst_hssi <= (rxurstcmu(1) AND rrxurstcmu(1)) OR rreset; + + ------------------------------------ + -- CMU reset outputs + ------------------------------------ + cmu0_rxpma_rstb <= NOT((cmu0_rxpma_rst_hssi OR hard_reset_xhdl0)); + cmu0_txpma_rstb <= NOT((hard_reset_xhdl0 OR rreset)); + cmu0_cru_rstb <= NOT((hard_reset_xhdl0 OR rreset OR rrx_cmu_rst(0))); + + cmu1_rxpma_rstb <= NOT((cmu1_rxpma_rst_hssi OR hard_reset_xhdl0)); + cmu1_txpma_rstb <= NOT((hard_reset_xhdl0 OR rreset)); + cmu1_cru_rstb <= NOT((hard_reset_xhdl0 OR rreset OR rrx_cmu_rst(1))); + + ------------------------------------ + -- powerdown internal signals + ------------------------------------ + cmu0_cru_pd_hssi <= rpowerdown OR rcmu_powdnr(0) OR NOT((rcmu_cru_pdb(0))); + cmu0_rx_pd_hssi <= rpowerdown OR rcmu_powdnr(0) OR NOT((ucmurx_pdb(0) OR NOT((rcmu_urx_pdb(0))))) OR NOT((rcmu_rx_ib_pdb(0))); + cmu0_tx_pd_hssi <= rpowerdown OR rcmu_powdnt(0) OR NOT((rcmu_tx_ob_pdb(0))); + cmu0_cgb_pd_hssi <= rpowerdown OR rcmu_powdnt(0) OR NOT((rcmu_tx_cgb_pdb(0))); + cmu0_rx_det_pd_hssi <= rpowerdown OR rcmu_powdnt(0) OR NOT((rcmu_rx_det_pdb(0))); + + cmu1_cru_pd_hssi <= rpowerdown OR rcmu_powdnr(1) OR NOT((rcmu_cru_pdb(1))); + cmu1_rx_pd_hssi <= rpowerdown OR rcmu_powdnr(1) OR NOT((ucmurx_pdb(1) OR NOT((rcmu_urx_pdb(1))))) OR NOT((rcmu_rx_ib_pdb(1))); + cmu1_tx_pd_hssi <= rpowerdown OR rcmu_powdnt(1) OR NOT((rcmu_tx_ob_pdb(1))); + cmu1_cgb_pd_hssi <= rpowerdown OR rcmu_powdnt(1) OR NOT((rcmu_tx_cgb_pdb(1))); + cmu1_rx_det_pd_hssi <= rpowerdown OR rcmu_powdnt(1) OR NOT((rcmu_rx_det_pdb(1))); + + ------------------------------------ + -- powerdown outputs + ------------------------------------ + cmu0_clk_pdb <= rclk_pdb(0); + cmu0_cru_pdb <= NOT((hard_reset_xhdl0 OR cmu0_cru_pd_hssi)); + cmu0_rx_pdb <= NOT((hard_reset_xhdl0 OR cmu0_rx_pd_hssi)); + cmu0_tx_pdb <= NOT((hard_reset_xhdl0 OR cmu0_tx_pd_hssi)); + cmu0_cgb_pdb <= NOT((hard_reset_xhdl0 OR cmu0_cgb_pd_hssi)); + cmu0_rx_det_pdb <= NOT((hard_reset_xhdl0 OR cmu0_rx_det_pd_hssi)); + + cmu1_clk_pdb <= rclk_pdb(1); + cmu1_cru_pdb <= NOT((hard_reset_xhdl0 OR cmu1_cru_pd_hssi)); + cmu1_rx_pdb <= NOT((hard_reset_xhdl0 OR cmu1_rx_pd_hssi)); + cmu1_tx_pdb <= NOT((hard_reset_xhdl0 OR cmu1_tx_pd_hssi)); + cmu1_cgb_pdb <= NOT((hard_reset_xhdl0 OR cmu1_cgb_pd_hssi)); + cmu1_rx_det_pdb <= NOT((hard_reset_xhdl0 OR cmu1_rx_det_pd_hssi)); + +END trans; + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_chnl_reset IS + PORT ( + + -- Inputs from QUAD reset module + hard_reset : IN STD_LOGIC; -- hardreset signal + soft_reset_all_hssi : IN STD_LOGIC; -- soft reset for all channel + rreset : IN STD_LOGIC; -- Quad reset CRAM + rpowerdown : IN STD_LOGIC; -- Quad power down CRAM + + -- Channel Reset inputs + rxurstpma : IN STD_LOGIC; -- RX PMA user reset + rxurstpcs : IN STD_LOGIC; -- RX PCS user reset + txurstpcs : IN STD_LOGIC; -- TX PCS user reset + + -- Channel Reset CRAMs + rpowdnr : IN STD_LOGIC; -- RX channel power down CRAM + rpowdnt : IN STD_LOGIC; -- TX channel power down CRAM + rrxurstpcs : IN STD_LOGIC; -- Gating CRAM for RXURSTPCS + rtxurstpcs : IN STD_LOGIC; -- Gating CRAM for TXURSTPCS + rrxurstpma : IN STD_LOGIC; -- Gating CRAM for RXURSTPMA + rrx_cru_rst : IN STD_LOGIC; -- Channel RX PLL reset CRAMs + radce_rst : IN STD_LOGIC; -- Channel Adaptive block reset CRAMs + + -- Powerdown inputs + urx_pdb : IN STD_LOGIC; -- RX user powerdown signal + + -- Powerdown CRAMs + rurx_pdb : IN STD_LOGIC; -- Gating CRAM for urx_pdb signals + radce_pdb : IN STD_LOGIC; -- Adaptive block powerdown CRAMs + rrx_ib_pdb : IN STD_LOGIC; -- RX Input buffer and PLL powerdown CRAMs + rtx_ob_pdb : IN STD_LOGIC; -- TX Output buffer powerdown CRAMs + rtx_cgb_pdb : IN STD_LOGIC; -- TX clock generator powerdown CRAMs + rrx_cru_pdb : IN STD_LOGIC; -- RX PLL powerdown CRAMs + + -- PIPE Inputs + rtx_pipe_en : IN STD_LOGIC; -- PIPE enable CRAMs + p0_state : IN STD_LOGIC; -- PIPE P0 state indicators + p0s_state : IN STD_LOGIC; -- PIPE P0S state indicators + p2_state : IN STD_LOGIC; -- PIPE P2 state indicators + + -- Channel Reset outputs + rxpma_rstb : OUT STD_LOGIC; -- RX PMA resets (powerdown) + txpma_rstb : OUT STD_LOGIC; -- TX PMA resets (powerdown) + rxpcs_rst : OUT STD_LOGIC; -- RX PCS resets + txpcs_rst : OUT STD_LOGIC; -- TX PCS resets + cru_rstb : OUT STD_LOGIC; -- RX PLL resets + adce_rstb : OUT STD_LOGIC; -- Adaptive block resets + + -- Channel Powerdown outputs + adce_pdb : OUT STD_LOGIC; -- Adaptive block powerdown + cru_pdb : OUT STD_LOGIC; -- RX PLL powerdown + rx_pdb : OUT STD_LOGIC; -- RX powerdown + tx_pdb : OUT STD_LOGIC; -- TX driver powerdown + cgb_pdb : OUT STD_LOGIC; -- Clock generator powerdown + rx_det_pdb : OUT STD_LOGIC -- Receiver detector powerdown + ); +END cycloneiv_hssi_cmu_chnl_reset; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_chnl_reset IS + + -- Wiring section for Resets + SIGNAL rxpcsrst_hssi : STD_LOGIC; + SIGNAL txpcsrst_hssi : STD_LOGIC; + SIGNAL rxpmarst_hssi : STD_LOGIC; + + -- Wiring section for Powerdowns + SIGNAL adce_pd_hssi : STD_LOGIC; + SIGNAL cru_pd_hssi : STD_LOGIC; + SIGNAL rx_pd_hssi : STD_LOGIC; + SIGNAL tx_pd_hssi : STD_LOGIC; + SIGNAL cgb_pd_hssi : STD_LOGIC; + SIGNAL rx_det_pd_hssi : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL rxpma_rstb_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + rxpma_rstb <= rxpma_rstb_xhdl0; + + -- reset internal signals + rxpcsrst_hssi <= (rxurstpcs AND rrxurstpcs) OR rpowdnr; + txpcsrst_hssi <= (txurstpcs AND rtxurstpcs) OR rpowdnt; + rxpmarst_hssi <= (rxurstpma AND rrxurstpma) OR rreset; + + -- reset outputs + rxpma_rstb_xhdl0 <= NOT((rxpmarst_hssi OR hard_reset)); + txpma_rstb <= NOT((rreset OR hard_reset)); + cru_rstb <= NOT((hard_reset OR rreset OR rrx_cru_rst)); + adce_rstb <= rxpma_rstb_xhdl0 AND NOT((radce_rst)); + + rxpcs_rst <= rxpcsrst_hssi OR hard_reset OR soft_reset_all_hssi; + txpcs_rst <= txpcsrst_hssi OR hard_reset OR soft_reset_all_hssi; + + -- powerdown internal signals + adce_pd_hssi <= NOT((radce_pdb)) OR rpowdnr OR rpowerdown; + cru_pd_hssi <= NOT((rrx_cru_pdb)) OR rpowdnr OR rpowerdown; + rx_pd_hssi <= NOT((urx_pdb OR NOT((rurx_pdb)))) OR NOT((rrx_ib_pdb)) OR rpowdnr OR rpowerdown; + tx_pd_hssi <= NOT((rtx_ob_pdb)) OR rpowdnt OR rpowerdown; + cgb_pd_hssi <= NOT((rtx_cgb_pdb)) OR rpowdnt OR rpowerdown; + rx_det_pd_hssi <= (rtx_pipe_en AND (p0_state OR p0s_state OR p2_state)) OR rpowdnt OR rpowerdown; + + -- powerdown outputs + adce_pdb <= NOT((adce_pd_hssi OR hard_reset)); + cru_pdb <= NOT((cru_pd_hssi OR hard_reset)); + rx_pdb <= NOT((rx_pd_hssi OR hard_reset)); + tx_pdb <= NOT((tx_pd_hssi OR hard_reset)); + cgb_pdb <= NOT((cgb_pd_hssi OR hard_reset)); + rx_det_pdb <= NOT((rx_det_pd_hssi OR hard_reset)); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_auto_speed_neg IS + GENERIC ( + + -- Clocks and Resets + WAIT_RATE_CHANGE : INTEGER := 0; + WAIT_FOR_PHFIFO : INTEGER := 1; + DISABLE_PC_BYTE : INTEGER := 2; + SET_CONFIG_SEL : INTEGER := 3; + WAIT_GEN2NGEN1_CHANGE : INTEGER := 4; + WAIT_PMA_DONE_CNTR : INTEGER := 5; + DEASSERT_PC_PTR_RESET : INTEGER := 6; + WAIT_DEASSERT_RST_CNTR : INTEGER := 7; + ENABLE_PC_BYTE : INTEGER := 8; + WAIT_ENABLE_CNTR : INTEGER := 9; + SPEED_CHANGE_DONE : INTEGER := 10 + ); + PORT ( + refclk : IN STD_LOGIC; + rxpcs_rst_int : IN STD_LOGIC; + + -- Input from LTSSM (sideband). high is gen2, low is gen1. + rate : IN STD_LOGIC; + -- Input from PMA + -- PMA indication for change in frequency. transistions one cycle before actually frequency change. high is gen2, low is gen1. + gen2ngen1 : IN STD_LOGIC; + + -- Bundle Mode Inputs for config_sel + config_sel_centrl : IN STD_LOGIC; + config_sel_quad_up : IN STD_LOGIC; + config_sel_quad_down : IN STD_LOGIC; + + -- MDIO + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + singleorbundle : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rpma_done_count : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + rauto_deassert_pc_rst_cnt : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rauto_pc_en_cnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rwait_for_phfifo_cnt : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + + -- control signal output for bundle mode high is gen2, low is gen1. + config_sel : OUT STD_LOGIC; + + -- PMA rate change control + pcie_switch : OUT STD_LOGIC; + + -- RX Phase Comp + -- Handshake signal to PIPE interface to assert PhyStatus + speed_change : OUT STD_LOGIC; + + -- Phase Comp and byte ser/deser control signals + dis_pc_byte : OUT STD_LOGIC; + reset_pc_ptrs : OUT STD_LOGIC; + cs : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END cycloneiv_hssi_cmu_auto_speed_neg; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_auto_speed_neg IS + + SIGNAL set_config_sel_reg : STD_LOGIC; + SIGNAL next_state : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rate_int_reg : STD_LOGIC; + SIGNAL gen2ngen1_del : STD_LOGIC; + SIGNAL freq_switch : STD_LOGIC; + SIGNAL reset_count : STD_LOGIC; + SIGNAL count_pma_done : STD_LOGIC; + SIGNAL count_deassert_rst : STD_LOGIC; + SIGNAL count_enable_pc : STD_LOGIC; + SIGNAL rate_sync1_reg : STD_LOGIC; + SIGNAL rate_sync2_reg : STD_LOGIC; + SIGNAL counter : STD_LOGIC_VECTOR(18 DOWNTO 0); + SIGNAL counter_done : STD_LOGIC; + SIGNAL count_phfifo : STD_LOGIC; + + SIGNAL rate_edge : STD_LOGIC; + -- X-HDL generated signals + + SIGNAL xhdl2 : STD_LOGIC; + SIGNAL xhdl3 : STD_LOGIC; + SIGNAL xhdl4 : STD_LOGIC; + SIGNAL xhdl5 : STD_LOGIC; + SIGNAL xhdl6 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL config_sel_xhdl0 : STD_LOGIC; + SIGNAL cs_xhdl1 : STD_LOGIC_VECTOR(3 DOWNTO 0); +BEGIN + -- Drive referenced outputs + config_sel <= config_sel_xhdl0; + cs <= cs_xhdl1; + + --============================================================================ + -- FSM states + -- + --============================================================================ + + --============================================================================ + -- Multi-use Counter with *2 done flag capablility + -- + --============================================================================ + + + xhdl2 <= '1' WHEN (((counter(18 DOWNTO 1) = rpma_done_count(17 DOWNTO 0)) AND (gen2ngen1 = '1') AND (counter(0) = '1')) OR ((counter(17 DOWNTO 0) = rpma_done_count(17 DOWNTO 0)) AND (NOT(gen2ngen1) = '1'))) ELSE + '0'; + xhdl3 <= '1' WHEN (((counter(4 DOWNTO 1) = rauto_deassert_pc_rst_cnt(3 DOWNTO 0)) AND (gen2ngen1 = '1') AND (counter(0) = '1')) OR ((counter(3 DOWNTO 0) = rauto_deassert_pc_rst_cnt(3 DOWNTO 0)) AND (NOT(gen2ngen1) = '1'))) ELSE + '0'; + xhdl4 <= '1' WHEN (((counter(5 DOWNTO 1) = rauto_pc_en_cnt(4 DOWNTO 0)) AND (gen2ngen1 = '1') AND (counter(0) = '1')) OR ((counter(4 DOWNTO 0) = rauto_pc_en_cnt(4 DOWNTO 0)) AND (NOT(gen2ngen1) = '1'))) ELSE + '0'; + xhdl5 <= '1' WHEN (((counter(6 DOWNTO 1) = rwait_for_phfifo_cnt(5 DOWNTO 0)) AND (gen2ngen1 = '1') AND (counter(0) = '1')) OR ((counter(5 DOWNTO 0) = rwait_for_phfifo_cnt(5 DOWNTO 0)) AND (NOT(gen2ngen1) = '1'))) ELSE + '0'; + PROCESS (refclk, rxpcs_rst_int) +VARIABLE txt : LINE; + BEGIN + IF (rxpcs_rst_int = '1') THEN + counter <= TRANSPORT "0000000000000000000" AFTER 1* 1 ps; + counter_done <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk'EVENT AND refclk = '1') THEN + IF (reset_count = '1') THEN + counter <= TRANSPORT "0000000000000000000" AFTER 1* 1 ps; + counter_done <= TRANSPORT '0' AFTER 1* 1 ps; + ELSE + counter <= TRANSPORT counter + "0000000000000000001" AFTER 1* 1 ps; + IF ((NOT(counter_done)) = '1') THEN + IF (count_pma_done = '1') THEN + counter_done <= TRANSPORT xhdl2 AFTER 1* 1 ps; + ELSIF (count_deassert_rst = '1') THEN + counter_done <= TRANSPORT xhdl3 AFTER 1* 1 ps; + ELSIF (count_enable_pc = '1') THEN + counter_done <= TRANSPORT xhdl4 AFTER 1* 1 ps; + ELSIF (count_phfifo = '1') THEN + counter_done <= TRANSPORT xhdl5 AFTER 1* 1 ps; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + -- if (~count_pma_done) + -- always @ (posedge clk or posedge reset) + + --============================================================================ + -- Control signal output logic + -- + --============================================================================ + + pcie_switch <= config_sel_xhdl0 WHEN (rindv_rx = '1') ELSE + config_sel_centrl WHEN (rmaster_rx = '1') ELSE + config_sel_quad_up WHEN (rmaster_up_rx = '1') ELSE + config_sel_quad_down; + + --============================================================================ + -- Synchronization, Input & Output Logic + -- + --============================================================================ + + PROCESS (refclk, rxpcs_rst_int) +VARIABLE txt : LINE; + BEGIN + IF (rxpcs_rst_int = '1') THEN + rate_sync1_reg <= TRANSPORT '0' AFTER 1* 1 ps; + rate_sync2_reg <= TRANSPORT '0' AFTER 1* 1 ps; + rate_int_reg <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk'EVENT AND refclk = '1') THEN + rate_sync1_reg <= TRANSPORT rate AFTER 1* 1 ps; + rate_sync2_reg <= TRANSPORT rate_sync1_reg AFTER 1* 1 ps; + rate_int_reg <= TRANSPORT rate_sync2_reg AFTER 1* 1 ps; + END IF; + END PROCESS; + + -- always @ (posedge refclk or posedge reset) + + rate_edge <= '1' WHEN (rate_sync2_reg /= rate_int_reg) ELSE + '0'; + + -- convert gen2ngen1 to freq_switch + xhdl6 <= '1' WHEN (gen2ngen1_del /= gen2ngen1) ELSE + '0'; + PROCESS (refclk, rxpcs_rst_int) +VARIABLE txt : LINE; + BEGIN + IF (rxpcs_rst_int = '1') THEN + gen2ngen1_del <= TRANSPORT '0' AFTER 1* 1 ps; + freq_switch <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk'EVENT AND refclk = '1') THEN + gen2ngen1_del <= TRANSPORT gen2ngen1 AFTER 1* 1 ps; + freq_switch <= TRANSPORT xhdl6 AFTER 1* 1 ps; + END IF; + END PROCESS; + + -- always @ (posedge refclk or posedge reset) + + -- config_sel + PROCESS (refclk, rxpcs_rst_int) +VARIABLE txt : LINE; + BEGIN + IF (rxpcs_rst_int = '1') THEN + config_sel_xhdl0 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk'EVENT AND refclk = '1') THEN + IF (set_config_sel_reg = '1') THEN + config_sel_xhdl0 <= TRANSPORT rate_sync2_reg AFTER 1* 1 ps; + END IF; + END IF; + END PROCESS; + + -- always @ (posedge refclk or posedge reset) + + --============================================================================ + -- Auto Speed Negotiation State Machine + -- + --============================================================================ + -- + + PROCESS (refclk, rxpcs_rst_int) +VARIABLE txt : LINE; + BEGIN + IF (rxpcs_rst_int = '1') THEN + cs_xhdl1 <= TRANSPORT int2bin(WAIT_RATE_CHANGE, 4) AFTER 1* 1 ps; + ELSIF (refclk'EVENT AND refclk = '1') THEN + cs_xhdl1 <= TRANSPORT next_state AFTER 1* 1 ps; + END IF; + END PROCESS; + + -- always @ (posedge refclk or posedge reset) + + PROCESS (cs_xhdl1, rate_edge, rauto_speed_ena, rphfifo_regmode_rx, freq_switch, counter_done, singleorbundle) +VARIABLE txt : LINE; + BEGIN +-- IF (cs_xhdl1'EVENT) THEN + + next_state <= cs_xhdl1; + dis_pc_byte <= '0'; + reset_pc_ptrs <= '0'; + set_config_sel_reg <= '0'; + speed_change <= '0'; + reset_count <= '1'; + count_pma_done <= '0'; + count_deassert_rst <= '0'; + count_enable_pc <= '0'; + + count_phfifo <= '0'; + + CASE cs_xhdl1 IS + + -- case: WAIT_RATE_CHANGE + + WHEN "0000" => + IF ((rate_edge AND rauto_speed_ena AND singleorbundle) = '1') THEN + IF ((NOT(rphfifo_regmode_rx)) = '1') THEN + next_state <= int2bin(WAIT_FOR_PHFIFO, 4); + ELSE + next_state <= int2bin(SET_CONFIG_SEL, 4); + END IF; + END IF; + + -- case: WAIT_FOR_PHFIFO + + WHEN "0001" => + reset_count <= '0'; + count_phfifo <= '1'; + IF (counter_done = '1') THEN + next_state <= int2bin(DISABLE_PC_BYTE, 4); + END IF; + + -- case: DISABLE_PC_BYTE + + WHEN "0010" => + dis_pc_byte <= '1'; + reset_pc_ptrs <= '1'; + speed_change <= '1'; + next_state <= int2bin(SET_CONFIG_SEL, 4); + + -- case: SET_CONFIG_SEL + + WHEN "0011" => + dis_pc_byte <= '1'; + reset_pc_ptrs <= '1'; + set_config_sel_reg <= '1'; + speed_change <= '1'; + next_state <= int2bin(WAIT_GEN2NGEN1_CHANGE, 4); + + -- case: WAIT_GEN2NGEN1_CHANGE + + WHEN "0100" => + dis_pc_byte <= '1'; + reset_pc_ptrs <= '1'; + speed_change <= '1'; + IF (freq_switch = '1') THEN + next_state <= int2bin(WAIT_PMA_DONE_CNTR, 4); + END IF; + + -- case: WAIT_PMA_DONE_CNTR + + WHEN "0101" => + dis_pc_byte <= '1'; + reset_pc_ptrs <= '1'; + speed_change <= '1'; + reset_count <= '0'; + count_pma_done <= '1'; + IF (counter_done = '1') THEN + IF ((NOT(rphfifo_regmode_rx)) = '1') THEN + next_state <= int2bin(DEASSERT_PC_PTR_RESET, 4); + ELSE + next_state <= int2bin(SPEED_CHANGE_DONE, 4); + END IF; + END IF; + + -- case DEASSERT_PC_PTR_RESET + + WHEN "0110" => + dis_pc_byte <= '1'; + speed_change <= '1'; + next_state <= int2bin(WAIT_DEASSERT_RST_CNTR, 4); + + -- case: WAIT_DEASSERT_RST_CNTR + + WHEN "0111" => + dis_pc_byte <= '1'; + speed_change <= '1'; + reset_count <= '0'; + count_deassert_rst <= '1'; + IF (counter_done = '1') THEN + next_state <= int2bin(ENABLE_PC_BYTE, 4); + END IF; + + -- case: ENABLE_PC_BYTE: + + WHEN "1000" => + speed_change <= '1'; + next_state <= int2bin(WAIT_ENABLE_CNTR, 4); + + -- case: WAIT_ENABLE_CNTR: + + WHEN "1001" => + speed_change <= '1'; + reset_count <= '0'; + count_enable_pc <= '1'; + IF (counter_done = '1') THEN + next_state <= int2bin(SPEED_CHANGE_DONE, 4); + END IF; + + -- case: SPEED_CHANGE_DONE: + + WHEN "1010" => + next_state <= int2bin(WAIT_RATE_CHANGE, 4); + + -- case: default + + WHEN OTHERS => -- case(cs) + dis_pc_byte <= '0'; + reset_pc_ptrs <= '0'; + set_config_sel_reg <= '0'; + speed_change <= '0'; + reset_count <= '1'; + count_pma_done <= '0'; + count_deassert_rst <= '0'; + count_enable_pc <= '0'; + next_state <= int2bin(WAIT_RATE_CHANGE, 4); + END CASE; +-- END IF; + END PROCESS; + + +END trans; + + + +-- always @ (cs or rate_edge or rauto_speed_ena or rphfifo_regmode_rx or freq_switch or counter_done) + + +-- auto_speed_neg_centrl +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_clk_gating IS + PORT ( + + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); +END ENTITY cycloneiv_hssi_cmu_clk_gating; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_clk_gating IS +BEGIN + + clk1out_n <= NOT((select_n OR clk1)); + clk2out_n <= NOT((NOT(select_n) OR clk2)); + +END ARCHITECTURE trans; + +-- centrl_clk_gating + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_clk_ctl IS + PORT ( + + pclk_pma : IN STD_LOGIC; -- x4 PCLK from PMA CMU + refclk_dig : IN STD_LOGIC; -- External digital clock + mdc : IN STD_LOGIC; -- MDIO input clock + ser_clk : IN STD_LOGIC; -- Serial clock + ser_mode : IN STD_LOGIC; -- Serial shift configuration mode + scan_mode : IN STD_LOGIC; -- Scan mode + scan_clk : IN STD_LOGIC; -- Scan mode + rfreerun_centrl : IN STD_LOGIC; -- REFCLK_OUT free running enable CRAM + rcentrl_clk_sel : IN STD_LOGIC; -- REFCLK_PMA global clock selection CRAM + rrefclk_out_div2 : IN STD_LOGIC; -- REFCLK_OUT divide by 2 enable CRAM + hard_reset : IN STD_LOGIC; -- Hard reset input + txrst : IN STD_LOGIC; + + refclk_pma_out : OUT STD_LOGIC; -- Global TX PCS clock + mdc_b : OUT STD_LOGIC; -- Configuration output clock + refclk_out : OUT STD_LOGIC; -- REFCLK_OUT output clk + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC + ); +END cycloneiv_hssi_cmu_clk_ctl; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_clk_ctl IS + + COMPONENT cycloneiv_hssi_cmu_clk_gating + PORT ( + + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); + END COMPONENT; + + SIGNAL refclk_pma_int : STD_LOGIC; + SIGNAL refclk_out_div2_inv : STD_LOGIC; + SIGNAL hard_reset_n : STD_LOGIC; + SIGNAL refclk_out_div2 : STD_LOGIC := '1'; + + SIGNAL gen2ngen1_local_sync : STD_LOGIC; + SIGNAL dynamic_div2ndiv1 : STD_LOGIC; + + SIGNAL clk1out_n : STD_LOGIC; + SIGNAL clk2out_n : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL refclk_pma_out_xhdl1 : STD_LOGIC; + SIGNAL refclk_out_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + refclk_pma_out <= refclk_pma_out_xhdl1; + refclk_out <= refclk_out_xhdl0; + + + -- The following assignments need to be replaced with clock buffers + -- instantiation when the technology is identified later + + -- refclk_pma clock selection + refclk_pma_int <= refclk_dig WHEN (rcentrl_clk_sel = '1') ELSE + pclk_pma; + refclk_pma_out_xhdl1 <= scan_clk WHEN (scan_mode = '1') ELSE + refclk_pma_int; + + -- refclk_out logic + -- This register is used to generate divided by two clock. Div by 2 clock starts off high after reset + refclk_out_div2_inv <= (NOT(refclk_out_div2) OR NOT(gen2ngen1_local_sync)) WHEN ((rauto_speed_ena AND NOT(rfreq_sel)) = '1') ELSE + NOT(refclk_out_div2); + + hard_reset_n <= '1' WHEN (rfreerun_centrl = '1') ELSE + NOT(hard_reset); + + PROCESS (hard_reset_n, refclk_pma_out_xhdl1) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(hard_reset_n)) = '1') THEN + refclk_out_div2 <= '1'; + ELSIF (refclk_pma_out_xhdl1'EVENT AND refclk_pma_out_xhdl1 = '1') THEN + refclk_out_div2 <= refclk_out_div2_inv; + END IF; + END PROCESS; + + PROCESS (txrst, refclk_pma_out_xhdl1) +VARIABLE txt : LINE; + BEGIN + IF (txrst = '1') THEN + gen2ngen1_local_sync <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk_pma_out_xhdl1'EVENT AND refclk_pma_out_xhdl1 = '1') THEN + gen2ngen1_local_sync <= TRANSPORT gen2ngen1_bundle AFTER 1* 1 ps; + END IF; + END PROCESS; + + dynamic_div2ndiv1 <= rrefclk_out_div2 OR (gen2ngen1_local_sync AND rauto_speed_ena AND NOT(rfreq_sel)); + + + + centrl_clk_gating : cycloneiv_hssi_cmu_clk_gating + PORT MAP ( + select_n => dynamic_div2ndiv1, + clk1 => refclk_pma_out_xhdl1, + clk2 => refclk_out_div2, + clk1out_n => clk1out_n, + clk2out_n => clk2out_n + ); + + refclk_out_xhdl0 <= NOT (clk1out_n OR clk2out_n); + + -- mdc_b clock logic + mdc_b <= refclk_pma_out_xhdl1 WHEN ((scan_mode = '1') AND (ser_mode = '1')) ELSE + refclk_pma_out_xhdl1 WHEN ((scan_mode = '1') AND (ser_mode = '0')) ELSE + ser_clk WHEN ((scan_mode = '0') AND (ser_mode = '1')) ELSE + mdc WHEN ((scan_mode = '0') AND (ser_mode = '0')) ELSE + mdc; + +END trans; + + + +-- centrl_clk_ctl + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_rx_ctrl IS + PORT ( + + -- ======= + -- inputs + -- ======= + soft_reset : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + rx_rd_clk : IN STD_LOGIC; -- This replaces PLD_RX_CLK + rx_wr_clk : IN STD_LOGIC; -- divided by 1 or 2 write clock. + scan_mode : IN STD_LOGIC; -- scan enable + rrxfifo_urst_en : IN STD_LOGIC; -- Enable rxfifo_urst + rxfifo_urst : IN STD_LOGIC; -- User reset exclusive to rx_ctrl & below + rrxphfifopldctl_en : IN STD_LOGIC; -- CRAM to enable PLD controlled write/read enable + pld_wr_dis : IN STD_LOGIC; -- PLD write disable + pld_re : IN STD_LOGIC; -- PLD read eanble + dis_pc_byte : IN STD_LOGIC; + -- New MDIO for new bundling scheme and new PCIE features like autospeed + rauto_speed_ena : IN STD_LOGIC; + + -- ======= + -- outputs + -- ======= + rx_we_out : OUT STD_LOGIC; + wr_enable_out : OUT STD_LOGIC; + rd_enable_out : OUT STD_LOGIC + ); +END cycloneiv_hssi_cmu_rx_ctrl; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_rx_ctrl IS + + -- reset signals + SIGNAL local_soft_reset : STD_LOGIC; -- OR of local & global resets. + SIGNAL soft_reset_wclk0 : STD_LOGIC; + SIGNAL soft_reset_wclk1_b4scan : STD_LOGIC; + SIGNAL soft_reset_wclk1 : STD_LOGIC; -- reset for fifo_wr_clk + SIGNAL soft_reset_rclk0 : STD_LOGIC; + SIGNAL soft_reset_rclk1_b4scan : STD_LOGIC; + SIGNAL soft_reset_rclk1 : STD_LOGIC; -- reset for pld_rx_clk + + -- Channel zero output should all channel rx_we_in of rx_ctrl + + SIGNAL rd_enable0 : STD_LOGIC; + SIGNAL rd_enable0p5 : STD_LOGIC; + SIGNAL rd_enable1 : STD_LOGIC; + SIGNAL pld_wr_dis0 : STD_LOGIC; + SIGNAL pld_wr_dis1 : STD_LOGIC; + SIGNAL pld_wr_dis2 : STD_LOGIC; + SIGNAL pld_wr_dis_edge : STD_LOGIC; + SIGNAL wr_enable0 : STD_LOGIC; + SIGNAL wr_enable0p5 : STD_LOGIC; + SIGNAL wr_enable1 : STD_LOGIC; + SIGNAL wr_enable2 : STD_LOGIC; + SIGNAL rxfifo_en_clk2_0 : STD_LOGIC; + SIGNAL rxfifo_en_clk2_1 : STD_LOGIC; + SIGNAL wr_enable_clk2 : STD_LOGIC; + -- X-HDL generated signals + + SIGNAL xhdl1 : STD_LOGIC; + SIGNAL xhdl2 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL rx_we_out_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + rx_we_out <= rx_we_out_xhdl0; + + local_soft_reset <= soft_reset OR (rrxfifo_urst_en AND rxfifo_urst); + + wr_enable_out <= wr_enable1; + rd_enable_out <= rd_enable1; + + -- generate rx_wr_clk reset + PROCESS (local_soft_reset, rx_wr_clk) +VARIABLE txt : LINE; + BEGIN + IF (local_soft_reset = '1') THEN + soft_reset_wclk0 <= TRANSPORT '1' AFTER 1* 1 ps; + soft_reset_wclk1_b4scan <= TRANSPORT '1' AFTER 1* 1 ps; + ELSIF (rx_wr_clk'EVENT AND rx_wr_clk = '1') THEN + soft_reset_wclk0 <= TRANSPORT '0' AFTER 1* 1 ps; + soft_reset_wclk1_b4scan <= TRANSPORT soft_reset_wclk0 AFTER 1* 1 ps; + END IF; + END PROCESS; + + soft_reset_wclk1 <= '0' WHEN (scan_mode = '1') ELSE + soft_reset_wclk1_b4scan; + + -- generate pld_rx_clk reset + PROCESS (local_soft_reset, rx_rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (local_soft_reset = '1') THEN + soft_reset_rclk0 <= TRANSPORT '1' AFTER 1* 1 ps; + soft_reset_rclk1_b4scan <= TRANSPORT '1' AFTER 1* 1 ps; + ELSIF (rx_rd_clk'EVENT AND rx_rd_clk = '1') THEN + soft_reset_rclk0 <= TRANSPORT '0' AFTER 1* 1 ps; + soft_reset_rclk1_b4scan <= TRANSPORT soft_reset_rclk0 AFTER 1* 1 ps; + END IF; + END PROCESS; + + soft_reset_rclk1 <= '0' WHEN (scan_mode = '1') ELSE + soft_reset_rclk1_b4scan; + + -- write enable, fifo data in + xhdl1 <= (wr_enable0p5 AND NOT(pld_wr_dis_edge)) WHEN (rrxphfifopldctl_en = '1') ELSE + wr_enable0p5; + PROCESS (rx_wr_clk, soft_reset_wclk1) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_wclk1 = '1') THEN + pld_wr_dis0 <= TRANSPORT '0' AFTER 1* 1 ps; + pld_wr_dis1 <= TRANSPORT '0' AFTER 1* 1 ps; + pld_wr_dis2 <= TRANSPORT '0' AFTER 1* 1 ps; + pld_wr_dis_edge <= TRANSPORT '0' AFTER 1* 1 ps; + wr_enable0 <= TRANSPORT '0' AFTER 1* 1 ps; + wr_enable0p5 <= TRANSPORT '0' AFTER 1* 1 ps; + wr_enable1 <= TRANSPORT '0' AFTER 1* 1 ps; + wr_enable2 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (rx_wr_clk'EVENT AND rx_wr_clk = '1') THEN + pld_wr_dis0 <= TRANSPORT pld_wr_dis AFTER 1* 1 ps; + pld_wr_dis1 <= TRANSPORT pld_wr_dis0 AFTER 1* 1 ps; + pld_wr_dis2 <= TRANSPORT pld_wr_dis1 AFTER 1* 1 ps; + pld_wr_dis_edge <= TRANSPORT int2bit((pld_wr_dis2 /= pld_wr_dis1)) AFTER 1* 1 ps; + wr_enable0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1* 1 ps; + wr_enable0p5 <= TRANSPORT wr_enable0 AFTER 1* 1 ps; + wr_enable1 <= TRANSPORT xhdl1 AFTER 1* 1 ps; + wr_enable2 <= TRANSPORT wr_enable1 AFTER 1* 1 ps; + END IF; + END PROCESS; + + -- read enable + xhdl2 <= (rd_enable0p5 AND pld_re) WHEN (rrxphfifopldctl_en = '1') ELSE + rd_enable0p5; + PROCESS (rx_rd_clk, soft_reset_rclk1) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_rclk1 = '1') THEN + rd_enable0 <= TRANSPORT '0' AFTER 1* 1 ps; + rd_enable0p5 <= TRANSPORT '0' AFTER 1* 1 ps; + rd_enable1 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (rx_rd_clk'EVENT AND rx_rd_clk = '1') THEN + rd_enable0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1* 1 ps; + rd_enable0p5 <= TRANSPORT rd_enable0 AFTER 1* 1 ps; + rd_enable1 <= TRANSPORT xhdl2 AFTER 1* 1 ps; + END IF; + END PROCESS; + + -- byte de-serializer high/low select + PROCESS (clk_2, soft_reset) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset = '1') THEN + rx_we_out_xhdl0 <= TRANSPORT '1' AFTER 1* 1 ps; + rxfifo_en_clk2_0 <= TRANSPORT '0' AFTER 1* 1 ps; + rxfifo_en_clk2_1 <= TRANSPORT '0' AFTER 1* 1 ps; + wr_enable_clk2 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk_2'EVENT AND clk_2 = '1') THEN + --rxfifo_en_clk2_0 <= rxfifo_en; + -- rxfifo_en_clk2_0 <= 1'b1; + rxfifo_en_clk2_0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1* 1 ps; + + rxfifo_en_clk2_1 <= TRANSPORT rxfifo_en_clk2_0 AFTER 1* 1 ps; + IF (rxfifo_en_clk2_1 = '0') THEN + wr_enable_clk2 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (wr_enable_clk2 = '0') THEN + + wr_enable_clk2 <= TRANSPORT wr_enable2 AFTER 1* 1 ps; + END IF; + IF (wr_enable_clk2 = '1') THEN + rx_we_out_xhdl0 <= TRANSPORT NOT(rx_we_out_xhdl0) AFTER 1* 1 ps; + ELSE + rx_we_out_xhdl0 <= TRANSPORT '0' AFTER 1* 1 ps; + END IF; + END IF; + END PROCESS; + +END trans; + + + + +-- rx_ctrl_centrl + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_rxclk_gating IS + PORT ( + + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); +END ENTITY cycloneiv_hssi_cmu_rxclk_gating; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_rxclk_gating IS +BEGIN + + clk1out_n <= NOT((select_n OR clk1)); + clk2out_n <= NOT((NOT(select_n) OR clk2)); + +END ARCHITECTURE trans; + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_rxclk_ctl IS + PORT ( + + -- Clock Inputs + pld_rx_clk : IN STD_LOGIC; -- PLD clock from PLD clock trees + rcvd_clk_pma : IN STD_LOGIC; -- local recovered clock + rcvd_clk0_pma : IN STD_LOGIC; -- channel zero recovered clock + tx_pma_clk : IN STD_LOGIC; -- local TX PMA clock + refclk_pma : IN STD_LOGIC; -- Quad based clk from TXPLL + fref : IN STD_LOGIC; + clklow : IN STD_LOGIC; + + -- Control Inputs + scan_mode : IN STD_LOGIC; -- Scan mode enable signal + -- This is the soft_reset for the RX_PCS + + -- New Control Inputs + gen2ngen1 : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling + gen2ngen1_bundle : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 + rx_div2_sync_centrl : IN STD_LOGIC; -- divided clock from the central channel (x2, x4 mode) + rx_div2_sync_quad_up : IN STD_LOGIC; -- divided clock from quad above (> x4 mode) + rx_div2_sync_quad_down : IN STD_LOGIC; -- divided clock from quad below (> x4 mode) + + -- MDIO Inputs + rrcvd_clk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_1_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_2_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrx_rd_clk_sel : IN STD_LOGIC; -- Select clock for rx ph comp fifo read side + rxrst : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; -- Select between XAUI mode or indiv channel mode + rdwidth_rx : IN STD_LOGIC; -- divide by 1 or 2 before feeding to FIFO write clock + rfreerun_rx : IN STD_LOGIC; -- Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by RX PCS reset + + -- New MDIO Inputs + rauto_speed_ena : IN STD_LOGIC; -- auto speed negotiation enable + rfreq_sel : IN STD_LOGIC; -- freq scaling or data width scaling + rrxpcsclkpwdn : IN STD_LOGIC; -- RX clocking power down enable + rmaster_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rmaster_up_rx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rself_sw_en_rx : IN STD_LOGIC; -- enables self-switch to have correct /2 clock in all quads in bundle mode + + -- Removed Inputs + -- input rphfifo_master_sel_rx; // RX Phase comp. FIFO rx_div2_sync selection CRAM + -- input rx_div2_sync_in_ch0; // Connect from channel zero rx_div2_sync_out + -- input rx_div2_sync_in_q0_ch0; // Connect from channel zero rx_div2_sync_out of Master Quad + + -- Clock Outputs with CTS + fref_muxed : OUT STD_LOGIC; + clklow_muxed : OUT STD_LOGIC; + rcvd_clk : OUT STD_LOGIC; + clk_1_b : OUT STD_LOGIC; + clk_2_b : OUT STD_LOGIC; + rx_wr_clk : OUT STD_LOGIC; -- drives the rx ph comp fifo write clock tree + rx_rd_clk : OUT STD_LOGIC; -- drives the rx ph comp fifo read clock tree + + -- Clock Outputs to PLD, no CTS + rx_clk : OUT STD_LOGIC; -- drives the PLD clock tree in x1 mode, logically same as rx_wr_clk + rcvd_clk_pma_b : OUT STD_LOGIC; -- debug output clock to PLD + + -- New Clock Outputs with CTS + clk_2_b_raw : OUT STD_LOGIC; -- same as clk_2_b, but with no clock gating + rx_wr_clk_raw : OUT STD_LOGIC; -- same as rx_wr_clk, but with no clock gating + rx_rd_clk_raw : OUT STD_LOGIC; -- same as rx_rd_clk, but with no clock gating + + -- Control Outputs + rx_div2_sync_out : OUT STD_LOGIC -- inverted /2 clock. not used w/new bundling scheme. (left for safety) + ); +END cycloneiv_hssi_cmu_rxclk_ctl; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_rxclk_ctl IS + COMPONENT cycloneiv_hssi_cmu_rxclk_gating + PORT ( + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); + END COMPONENT; + + SIGNAL rx_clk_2_by2 : STD_LOGIC := '1'; + SIGNAL gen2ngen1_local_sync : STD_LOGIC; + SIGNAL counter : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL rx_div2_sync : STD_LOGIC; + SIGNAL rx_rst_n : STD_LOGIC; + SIGNAL rrcvd_clk_sel_int : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rclk_1_sel_int : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rclk_2_sel_int : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dynamic_div2ndiv1 : STD_LOGIC; + SIGNAL gen2ngen1_local : STD_LOGIC; + SIGNAL rrxpcsclkpwdn_nscan : STD_LOGIC; + SIGNAL rx_div2_this_quad : STD_LOGIC; + SIGNAL rx_div2_this_channel : STD_LOGIC; + SIGNAL rx_div2_other_quad : STD_LOGIC; + SIGNAL force_master : STD_LOGIC; + + SIGNAL select_div1_n : STD_LOGIC; + SIGNAL clk1out_n : STD_LOGIC; + SIGNAL clk2out_n : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL rx_wr_clk_xhdl3 : STD_LOGIC; + SIGNAL clk_2_b_raw_xhdl0 : STD_LOGIC; + SIGNAL rx_wr_clk_raw_xhdl4 : STD_LOGIC; + SIGNAL rx_rd_clk_raw_xhdl2 : STD_LOGIC; + SIGNAL rx_div2_sync_out_xhdl1 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + rx_wr_clk <= rx_wr_clk_xhdl3; + clk_2_b_raw <= clk_2_b_raw_xhdl0; + rx_wr_clk_raw <= rx_wr_clk_raw_xhdl4; + rx_rd_clk_raw <= rx_rd_clk_raw_xhdl2; + rx_div2_sync_out <= rx_div2_sync_out_xhdl1; + + -- Old bundle logic: + -- Select between the local synchronization signal or the global synchronization signal + --assign rx_div2_sync = rindv_rx ? rx_div2_sync_out : rx_div2_sync_in; + -- assign rx_div2_sync = (rphfifo_master_sel_rx == 1'b0) ? rx_div2_sync_in_q0_ch0 : + -- (rindv_rx == 1'b0) ? rx_div2_sync_in_ch0 : + -- (rauto_speed_ena & ~rfreq_sel) ? (rx_div2_sync_out | ~gen2ngen1_local_sync) : rx_div2_sync_out; + + PROCESS (rxrst, clk_2_b_raw_xhdl0) +VARIABLE txt : LINE; + BEGIN + IF (rxrst = '1') THEN + counter <= TRANSPORT "00" AFTER 1* 1 ps; + ELSIF (clk_2_b_raw_xhdl0'EVENT AND clk_2_b_raw_xhdl0 = '1') THEN + IF (((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_rx) AND NOT(force_master)) = '1') THEN + counter <= TRANSPORT counter + "01" AFTER 1* 1 ps; + END IF; + END IF; + END PROCESS; + + force_master <= '1' WHEN ((counter = "11") AND ((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_rx) = '1')) ELSE + '0'; + + rx_div2_sync <= rx_div2_this_quad WHEN ((rmaster_rx OR force_master) = '1') ELSE + rx_div2_other_quad; + rx_div2_this_quad <= rx_div2_this_channel WHEN ((rindv_rx OR force_master) = '1') ELSE + rx_div2_sync_centrl; + rx_div2_this_channel <= (rx_div2_sync_out_xhdl1 OR NOT(gen2ngen1_local_sync)) WHEN ((rauto_speed_ena AND NOT(rfreq_sel)) = '1') ELSE + rx_div2_sync_out_xhdl1; + rx_div2_other_quad <= rx_div2_sync_quad_up WHEN (rmaster_up_rx = '1') ELSE + rx_div2_sync_quad_down; + + gen2ngen1_local <= gen2ngen1_bundle WHEN (rindv_rx = '0') ELSE + gen2ngen1; + + PROCESS (rxrst, clk_2_b_raw_xhdl0) +VARIABLE txt : LINE; + BEGIN + IF (rxrst = '1') THEN + gen2ngen1_local_sync <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (clk_2_b_raw_xhdl0'EVENT AND clk_2_b_raw_xhdl0 = '1') THEN + gen2ngen1_local_sync <= TRANSPORT gen2ngen1_local AFTER 1* 1 ps; + END IF; + END PROCESS; + + dynamic_div2ndiv1 <= rdwidth_rx OR (gen2ngen1_local_sync AND rauto_speed_ena AND NOT(rfreq_sel)); + + -- Reset for Divide-by-2 FF and synchronization FF's for clock gating + rx_rst_n <= '1' WHEN (rfreerun_rx = '1') ELSE + NOT(rxrst); + + rrxpcsclkpwdn_nscan <= rrxpcsclkpwdn AND NOT(scan_mode); + + -- clocks are assigned below in the order in which they appear in the out flowing data path + -- RCVD_CLK selection + rrcvd_clk_sel_int <= "01" WHEN (scan_mode = '1') ELSE + rrcvd_clk_sel; + rcvd_clk <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rcvd_clk_pma WHEN (rrcvd_clk_sel_int = "00") ELSE + refclk_pma WHEN (rrcvd_clk_sel_int = "01") ELSE + tx_pma_clk WHEN (rrcvd_clk_sel_int = "10") ELSE + rcvd_clk_pma WHEN (rrcvd_clk_sel_int = "11") ELSE + rcvd_clk_pma; + + -- CLK_1 seleciton + rclk_1_sel_int <= "01" WHEN (scan_mode = '1') ELSE + rclk_1_sel; + clk_1_b <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rcvd_clk_pma WHEN (rclk_1_sel_int = "00") ELSE + refclk_pma WHEN (rclk_1_sel_int = "01") ELSE + tx_pma_clk WHEN (rclk_1_sel_int = "10") ELSE + rcvd_clk0_pma WHEN (rclk_1_sel_int = "11") ELSE + rcvd_clk_pma; + + -- CLK_2 selection + rclk_2_sel_int <= "10" WHEN (scan_mode = '1') ELSE + rclk_2_sel; + clk_2_b_raw_xhdl0 <= rcvd_clk_pma WHEN (rclk_2_sel_int = "00") ELSE + tx_pma_clk WHEN (rclk_2_sel_int = "01") ELSE + refclk_pma WHEN (rclk_2_sel_int = "10") ELSE + rcvd_clk_pma; + --change made for S3GX to remove pld_rx_clk from mux input + --(rclk_2_sel_int == 2'b10) ? refclk_pma : + --(rclk_2_sel_int == 2'b11) ? pld_rx_clk : rcvd_clk_pma; + + clk_2_b <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + clk_2_b_raw_xhdl0; + + -- This register is used to generate divided by two clock. Div by 2 clock starts off high after reset + -- No #1 on this FF as it generates a clock + PROCESS (rx_rst_n, clk_2_b_raw_xhdl0) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(rx_rst_n)) = '1') THEN + rx_clk_2_by2 <= '1'; + ELSIF (clk_2_b_raw_xhdl0'EVENT AND clk_2_b_raw_xhdl0 = '1') THEN + rx_clk_2_by2 <= rx_div2_sync; + END IF; + END PROCESS; + + rx_div2_sync_out_xhdl1 <= NOT(rx_clk_2_by2); + + -- RX FIFO write clock: could be fast or divided by 2 + -- old code: + -- assign rx_wr_clk = ((rdwidth_rx == 1'b0) || scan_mode) ? clk_2_b_raw : rx_clk_2_by2; + + select_div1_n <= NOT((scan_mode OR NOT(dynamic_div2ndiv1))); + + rxclk_gating : cycloneiv_hssi_cmu_rxclk_gating + PORT MAP ( + select_n => select_div1_n, + clk1 => clk_2_b_raw_xhdl0, + clk2 => rx_clk_2_by2, + clk1out_n => clk1out_n, + clk2out_n => clk2out_n + ); + + rx_wr_clk_raw_xhdl4 <= NOT((clk1out_n OR clk2out_n)); + + rx_wr_clk_xhdl3 <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rx_wr_clk_raw_xhdl4; + + -- RX FIFO read clock + rx_rd_clk_raw_xhdl2 <= rx_wr_clk_raw_xhdl4 WHEN ((scan_mode OR int2bit((rrx_rd_clk_sel = '0'))) = '1') ELSE + pld_rx_clk; + rx_rd_clk <= '1' WHEN (rrxpcsclkpwdn_nscan = '1') ELSE + rx_rd_clk_raw_xhdl2; + + -- RX clock out + rx_clk <= rx_wr_clk_xhdl3; -- drives PLD clock tree + + -- Recovered clock for debugging + rcvd_clk_pma_b <= rcvd_clk_pma; -- Goes out to PLD as debug clock. This clock may or may not be routed out to PLD fabric. TBD + + fref_muxed <= refclk_pma WHEN (scan_mode = '1') ELSE + '1' WHEN (rrxpcsclkpwdn = '1') ELSE + fref; + clklow_muxed <= refclk_pma WHEN (scan_mode = '1') ELSE + '1' WHEN (rrxpcsclkpwdn = '1') ELSE + clklow; + +END trans; + + + + +-- rxclk_ctl_centrl + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_tx_ctrl IS + PORT ( + + -- ====== + -- inputs + -- ====== + soft_reset : IN STD_LOGIC; -- Reset + fifo_wr_clk : IN STD_LOGIC; -- Used to be wr_clk_pos + fifo_rd_clk : IN STD_LOGIC; -- Coming from txclk_xg_ctl + refclk_b_in : IN STD_LOGIC; -- The local reference clock used by the internal + scan_mode : IN STD_LOGIC; -- scan enable + rtxfifo_urst_en : IN STD_LOGIC; -- user reset CRAM enable + txfifo_urst : IN STD_LOGIC; -- user reset + rtxphfifopldctl_en : IN STD_LOGIC; -- CRAM to enable PLD controlled write/read enable + pld_we : IN STD_LOGIC; -- PLD phase comp. fifo we, level active + pld_rd_dis : IN STD_LOGIC; -- PLD phase comp. fifo rd dis, edge active + dis_pc_byte : IN STD_LOGIC; + -- New MDIO for new bundling scheme and new PCIE features like autospeed + rauto_speed_ena : IN STD_LOGIC; + + -- ======= + -- outputs + -- ======= + wr_enable_out : OUT STD_LOGIC; -- ch0 wr_enable1 output for X4/X8 mode + rd_enable_out : OUT STD_LOGIC; -- ch0 rd_enable1 output for X4/X8 mode + fifo_select_out : OUT STD_LOGIC -- New output for Rev.B + ); +END cycloneiv_hssi_cmu_tx_ctrl; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_tx_ctrl IS + + SIGNAL wr_enable0 : STD_LOGIC; + SIGNAL wr_enable0p5 : STD_LOGIC; + SIGNAL wr_enable1 : STD_LOGIC; + SIGNAL rd_enable0 : STD_LOGIC; + SIGNAL rd_enable0p5 : STD_LOGIC; + SIGNAL rd_enable1 : STD_LOGIC; + SIGNAL rd_enable2 : STD_LOGIC; + + SIGNAL soft_reset_local : STD_LOGIC; + SIGNAL soft_reset_wclk0 : STD_LOGIC; + SIGNAL soft_reset_wclk1_b4scan : STD_LOGIC; + SIGNAL soft_reset_wclk1 : STD_LOGIC; + SIGNAL soft_reset_rclk0 : STD_LOGIC; + SIGNAL soft_reset_rclk1_b4scan : STD_LOGIC; + SIGNAL soft_reset_rclk1 : STD_LOGIC; + + SIGNAL pld_rd_dis0 : STD_LOGIC; + SIGNAL pld_rd_dis1 : STD_LOGIC; + SIGNAL pld_rd_dis2 : STD_LOGIC; + SIGNAL pld_rd_dis_edge : STD_LOGIC; + + SIGNAL txfifo_en_refclk0 : STD_LOGIC; + SIGNAL txfifo_en_refclk1 : STD_LOGIC; + SIGNAL rd_enable_sync_refclk_b_in : STD_LOGIC; + -- X-HDL generated signals + + SIGNAL xhdl1 : STD_LOGIC; + SIGNAL xhdl2 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL fifo_select_out_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + fifo_select_out <= fifo_select_out_xhdl0; + + wr_enable_out <= wr_enable1; + rd_enable_out <= rd_enable1; + + soft_reset_local <= soft_reset OR (rtxfifo_urst_en AND txfifo_urst); + + -- synchronize reset input (in refclk_b domain) + PROCESS (soft_reset_local, fifo_wr_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_local = '1') THEN + soft_reset_wclk0 <= TRANSPORT '1' AFTER 1* 1 ps; + soft_reset_wclk1_b4scan <= TRANSPORT '1' AFTER 1* 1 ps; + ELSIF (fifo_wr_clk'EVENT AND fifo_wr_clk = '1') THEN + soft_reset_wclk0 <= TRANSPORT '0' AFTER 1* 1 ps; + soft_reset_wclk1_b4scan <= TRANSPORT soft_reset_wclk0 AFTER 1* 1 ps; + END IF; + END PROCESS; + -- always @ (posedge soft_reset_local or posedge fifo_wr_clk) + + soft_reset_wclk1 <= '0' WHEN (scan_mode = '1') ELSE + soft_reset_wclk1_b4scan; + + -- synchronize reset input (in refclk_b domain) and balance it with fifo_wr_clk reset + PROCESS (soft_reset_local, fifo_rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_local = '1') THEN + soft_reset_rclk0 <= TRANSPORT '1' AFTER 1* 1 ps; + soft_reset_rclk1_b4scan <= TRANSPORT '1' AFTER 1* 1 ps; + ELSIF (fifo_rd_clk'EVENT AND fifo_rd_clk = '1') THEN + soft_reset_rclk0 <= TRANSPORT '0' AFTER 1* 1 ps; + soft_reset_rclk1_b4scan <= TRANSPORT soft_reset_rclk0 AFTER 1* 1 ps; + END IF; + END PROCESS; + -- always @ (posedge soft_reset_local or posedge fifo_rd_clk) + + soft_reset_rclk1 <= '0' WHEN (scan_mode = '1') ELSE + soft_reset_rclk1_b4scan; + + -- write enable + xhdl1 <= (wr_enable0p5 AND pld_we) WHEN (rtxphfifopldctl_en = '1') ELSE + wr_enable0p5; + PROCESS (soft_reset_wclk1, fifo_wr_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_wclk1 = '1') THEN + wr_enable0 <= TRANSPORT '0' AFTER 1* 1 ps; + wr_enable0p5 <= TRANSPORT '0' AFTER 1* 1 ps; + wr_enable1 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (fifo_wr_clk'EVENT AND fifo_wr_clk = '1') THEN + wr_enable0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1* 1 ps; + wr_enable0p5 <= TRANSPORT wr_enable0 AFTER 1* 1 ps; + wr_enable1 <= TRANSPORT xhdl1 AFTER 1* 1 ps; + END IF; + END PROCESS; + -- always @ (posedge soft_reset_wclk1 or posedge fifo_wr_clk) + + -- read enable & + -- read enable sync (for byte serializer output enable) + + xhdl2 <= (rd_enable0p5 AND NOT(pld_rd_dis_edge)) WHEN (rtxphfifopldctl_en = '1') ELSE + rd_enable0p5; + PROCESS (soft_reset_rclk1, fifo_rd_clk) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset_rclk1 = '1') THEN + pld_rd_dis0 <= TRANSPORT '0' AFTER 1* 1 ps; + pld_rd_dis1 <= TRANSPORT '0' AFTER 1* 1 ps; + pld_rd_dis2 <= TRANSPORT '0' AFTER 1* 1 ps; + pld_rd_dis_edge <= TRANSPORT '0' AFTER 1* 1 ps; + rd_enable0 <= TRANSPORT '0' AFTER 1* 1 ps; + rd_enable0p5 <= TRANSPORT '0' AFTER 1* 1 ps; + rd_enable1 <= TRANSPORT '0' AFTER 1* 1 ps; + rd_enable2 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (fifo_rd_clk'EVENT AND fifo_rd_clk = '1') THEN + pld_rd_dis0 <= TRANSPORT pld_rd_dis AFTER 1* 1 ps; + pld_rd_dis1 <= TRANSPORT pld_rd_dis0 AFTER 1* 1 ps; + pld_rd_dis2 <= TRANSPORT pld_rd_dis1 AFTER 1* 1 ps; + pld_rd_dis_edge <= TRANSPORT int2bit((pld_rd_dis2 /= pld_rd_dis1)) AFTER 1* 1 ps; + rd_enable0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1* 1 ps; + rd_enable0p5 <= TRANSPORT rd_enable0 AFTER 1* 1 ps; + rd_enable1 <= TRANSPORT xhdl2 AFTER 1* 1 ps; + + rd_enable2 <= TRANSPORT rd_enable1 AFTER 1* 1 ps; + END IF; + END PROCESS; + -- always @ (posedge soft_reset_rclk1 or posedge fifo_rd_clk) + + -- byte serializer high/low select + PROCESS (soft_reset, refclk_b_in) +VARIABLE txt : LINE; + BEGIN + IF (soft_reset = '1') THEN + rd_enable_sync_refclk_b_in <= TRANSPORT '0' AFTER 1* 1 ps; + txfifo_en_refclk0 <= TRANSPORT '0' AFTER 1* 1 ps; + txfifo_en_refclk1 <= TRANSPORT '0' AFTER 1* 1 ps; + fifo_select_out_xhdl0 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk_b_in'EVENT AND refclk_b_in = '1') THEN + txfifo_en_refclk0 <= TRANSPORT NOT((rauto_speed_ena AND dis_pc_byte)) AFTER 1* 1 ps; + + txfifo_en_refclk1 <= TRANSPORT txfifo_en_refclk0 AFTER 1* 1 ps; + IF (txfifo_en_refclk1 = '0') THEN + rd_enable_sync_refclk_b_in <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (rd_enable_sync_refclk_b_in = '0') THEN + + rd_enable_sync_refclk_b_in <= TRANSPORT rd_enable2 AFTER 1* 1 ps; + END IF; + IF (rd_enable_sync_refclk_b_in = '1') THEN + fifo_select_out_xhdl0 <= TRANSPORT NOT(fifo_select_out_xhdl0) AFTER 1* 1 ps; + ELSE + fifo_select_out_xhdl0 <= TRANSPORT '0' AFTER 1* 1 ps; + END IF; + END IF; + END PROCESS; + +END trans; + + +-- always @ (posedge soft_reset or posedge refclk_b_in) + + +-- tx_ctrl_centrl + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_txclk_gating IS + PORT ( + + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); +END ENTITY cycloneiv_hssi_cmu_txclk_gating; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_txclk_gating IS +BEGIN + + clk1out_n <= NOT((select_n OR clk1)); + clk2out_n <= NOT((NOT(select_n) OR clk2)); + +END ARCHITECTURE trans; + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_txclk_ctl IS + PORT ( + + -- Clock Inputs + pld_tx_clk : IN STD_LOGIC; -- PLD clock from PLD clock trees, the transmit clock from XGMII. + refclk_pma : IN STD_LOGIC; -- Quad based clk from TXPLL + txpma_local_clk : IN STD_LOGIC; -- Local channel TX PMA clock. + + -- Control Inputs + txrst : IN STD_LOGIC; -- reset for the tx_pcs + scan_mode : IN STD_LOGIC; -- Scan mode enable signal for selecting scan_clk from refclk_pma + + -- New Control Inputs + gen2ngen1 : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling + gen2ngen1_bundle : IN STD_LOGIC; -- from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 + tx_div2_sync_centrl : IN STD_LOGIC; -- divided clock from the central channel (x2, x4 mode) + tx_div2_sync_quad_up : IN STD_LOGIC; -- divided clock from quad above (> x4 mode) + tx_div2_sync_quad_down : IN STD_LOGIC; -- divided clock from quad below (> x4 mode) + + -- MDIO Inputs + rindv_tx : IN STD_LOGIC; -- Selects between indiv chan. mode and bundled mode + rtxwrclksel : IN STD_LOGIC; -- Selects which clock writes into FIFO + rtxrdclksel : IN STD_LOGIC; -- Selects which clock reads from FIFO and also clocks reest of TX logic + rdwidth_tx : IN STD_LOGIC; -- divide by 1 or 2 before feeding to FIFO read clock + rfreerun_tx : IN STD_LOGIC; -- Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by TX PCS reset + + -- New MDIO Inputs + rauto_speed_ena : IN STD_LOGIC; -- auto speed negotiation enable + rfreq_sel : IN STD_LOGIC; -- freq scaling or data width scaling + rtxpcsclkpwdn : IN STD_LOGIC; -- TX clocking power down enable + rmaster_tx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rmaster_up_tx : IN STD_LOGIC; -- New bundle mode MDIO, selects master quad + rself_sw_en_tx : IN STD_LOGIC; -- enables self-switch to have correct /2 clock in all quads in bundle mode + + -- Removed Inputs + -- input tx_div2_sync_in_ch0; // from the channel zero tx_div2_sync_out + -- input tx_div2_sync_in_q0_ch0; // From channel0 of Master Quad + -- input rphfifo_master_sel_tx; // TX Phase comp. FIFO tx_div2_sync selection CRAM + + -- Clock Outputs wtih CTS + refclk_b : OUT STD_LOGIC; -- Drives the tx channel clock + wr_clk_pos : OUT STD_LOGIC; -- Drives tx phase comp fifo write side + fifo_rd_clk : OUT STD_LOGIC; -- Drives tx phase comp fifo read side + + -- Clock Outputs to PLD, w/o CTS + tx_clk_out : OUT STD_LOGIC; -- Drives to the PLD clock tree -- unconnected + + -- New Clock Outputs with CTS + refclk_b_raw : OUT STD_LOGIC; -- same as refclk_b, but with no clock gating + wr_clk_pos_raw : OUT STD_LOGIC; -- same as wr_clk_pos, but with no clock gating + fifo_rd_clk_raw : OUT STD_LOGIC; -- same as fifo_rd_clk, but with no clock gating + + -- Control Outputs + tx_div2_sync_out : OUT STD_LOGIC -- Synchronizes the divided by two clock + ); +END cycloneiv_hssi_cmu_txclk_ctl; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_txclk_ctl IS + COMPONENT cycloneiv_hssi_cmu_txclk_gating IS + PORT ( + select_n : IN STD_LOGIC; + clk1 : IN STD_LOGIC; + clk2 : IN STD_LOGIC; + clk1out_n : OUT STD_LOGIC; + clk2out_n : OUT STD_LOGIC + ); + END COMPONENT; + + SIGNAL fifo_rd_clk_by2 : STD_LOGIC := '1'; + SIGNAL gen2ngen1_local_sync : STD_LOGIC; + SIGNAL counter : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL tx_rst_n : STD_LOGIC; + SIGNAL tx_div2_sync : STD_LOGIC; + SIGNAL dynamic_div2ndiv1 : STD_LOGIC; + SIGNAL gen2ngen1_local : STD_LOGIC; + SIGNAL tx_div2_this_quad : STD_LOGIC; + SIGNAL tx_div2_this_channel : STD_LOGIC; + SIGNAL tx_div2_other_quad : STD_LOGIC; + SIGNAL force_master : STD_LOGIC; + SIGNAL rtxpcsclkpwdn_nscan : STD_LOGIC; + + SIGNAL select_div1_n : STD_LOGIC; + SIGNAL clk1out_n : STD_LOGIC; + SIGNAL clk2out_n : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL fifo_rd_clk_xhdl0 : STD_LOGIC; + SIGNAL refclk_b_raw_xhdl2 : STD_LOGIC; + SIGNAL wr_clk_pos_raw_xhdl4 : STD_LOGIC; + SIGNAL fifo_rd_clk_raw_xhdl1 : STD_LOGIC; + SIGNAL tx_div2_sync_out_xhdl3 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + fifo_rd_clk <= fifo_rd_clk_xhdl0; + refclk_b_raw <= refclk_b_raw_xhdl2; + wr_clk_pos_raw <= wr_clk_pos_raw_xhdl4; + fifo_rd_clk_raw <= fifo_rd_clk_raw_xhdl1; + tx_div2_sync_out <= tx_div2_sync_out_xhdl3; + + + -- Old bundle logic: + -- Select between the local synchronization signal or the global synchronization signal (either from Channel0 or + -- Channel0 of Master Quad + --assign tx_div2_sync = rindv_tx ? tx_div2_sync_out : tx_div2_sync_in; + -- assign tx_div2_sync = (rphfifo_master_sel_tx == 1'b0) ? tx_div2_sync_in_q0_ch0 : + -- (rindv_tx == 1'b0) ? tx_div2_sync_in_ch0 : + -- (rauto_speed_ena & ~rfreq_sel) ? (tx_div2_sync_out | ~gen2ngen1_local_sync) : tx_div2_sync_out; + -- + + PROCESS (txrst, refclk_b_raw_xhdl2) +VARIABLE txt : LINE; + BEGIN + IF (txrst = '1') THEN + counter <= TRANSPORT "00" AFTER 1* 1 ps; + ELSIF (refclk_b_raw_xhdl2'EVENT AND refclk_b_raw_xhdl2 = '1') THEN + IF (((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_tx) AND NOT(force_master)) = '1') THEN + counter <= TRANSPORT counter + "01" AFTER 1* 1 ps; + END IF; + END IF; + END PROCESS; + + force_master <= '1' WHEN ((counter = "11") AND ((rauto_speed_ena AND NOT(rfreq_sel) AND rself_sw_en_tx) = '1')) ELSE + '0'; + + tx_div2_sync <= tx_div2_this_quad WHEN ((rmaster_tx OR force_master) = '1') ELSE + tx_div2_other_quad; + tx_div2_this_quad <= tx_div2_this_channel WHEN ((rindv_tx OR force_master) = '1') ELSE + tx_div2_sync_centrl; + tx_div2_this_channel <= (tx_div2_sync_out_xhdl3 OR NOT(gen2ngen1_local_sync)) WHEN ((rauto_speed_ena AND NOT(rfreq_sel)) = '1') ELSE + tx_div2_sync_out_xhdl3; + tx_div2_other_quad <= tx_div2_sync_quad_up WHEN (rmaster_up_tx = '1') ELSE + tx_div2_sync_quad_down; + + gen2ngen1_local <= gen2ngen1_bundle WHEN (rindv_tx = '0') ELSE + gen2ngen1; + + PROCESS (txrst, refclk_b_raw_xhdl2) +VARIABLE txt : LINE; + BEGIN + IF (txrst = '1') THEN + gen2ngen1_local_sync <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (refclk_b_raw_xhdl2'EVENT AND refclk_b_raw_xhdl2 = '1') THEN + gen2ngen1_local_sync <= TRANSPORT gen2ngen1_local AFTER 1* 1 ps; + END IF; + END PROCESS; + + dynamic_div2ndiv1 <= rdwidth_tx OR (gen2ngen1_local_sync AND rauto_speed_ena AND NOT(rfreq_sel)); + + -- Reset for Divide-by-2 FF + tx_rst_n <= '1' WHEN (rfreerun_tx = '1') ELSE + NOT(txrst); + + rtxpcsclkpwdn_nscan <= rtxpcsclkpwdn AND NOT(scan_mode); + + -- Full speed clock for TX PCS + refclk_b_raw_xhdl2 <= refclk_pma WHEN ((scan_mode OR rtxrdclksel) = '1') ELSE + txpma_local_clk; + + refclk_b <= '1' WHEN (rtxpcsclkpwdn_nscan = '1') ELSE + refclk_b_raw_xhdl2; + + -- Divide-by-2 FF + PROCESS (tx_rst_n, refclk_b_raw_xhdl2) +VARIABLE txt : LINE; + BEGIN + IF ((NOT(tx_rst_n)) = '1') THEN + fifo_rd_clk_by2 <= '1'; + ELSIF (refclk_b_raw_xhdl2'EVENT AND refclk_b_raw_xhdl2 = '1') THEN + fifo_rd_clk_by2 <= tx_div2_sync; -- local divided clock + END IF; + END PROCESS; + + tx_div2_sync_out_xhdl3 <= NOT(fifo_rd_clk_by2); + + -- TX FIFO read clock: could be fast or divided by 2 + -- old code: + -- assign fifo_rd_clk = ((rdwidth_tx == 1'b0) || scan_mode) ? refclk_b_raw : fifo_rd_clk_by2; + + select_div1_n <= NOT((scan_mode OR NOT(dynamic_div2ndiv1))); + + txclk_gating : cycloneiv_hssi_cmu_txclk_gating + PORT MAP ( + select_n => select_div1_n, + clk1 => refclk_b_raw_xhdl2, + clk2 => fifo_rd_clk_by2, + clk1out_n => clk1out_n, + clk2out_n => clk2out_n + ); + + fifo_rd_clk_raw_xhdl1 <= NOT((clk1out_n OR clk2out_n)); + + fifo_rd_clk_xhdl0 <= '1' WHEN (rtxpcsclkpwdn_nscan = '1') ELSE + fifo_rd_clk_raw_xhdl1; + + -- TX FIFO write clock: used internal clock when in BIST or scan or HIP + wr_clk_pos_raw_xhdl4 <= fifo_rd_clk_raw_xhdl1 WHEN ((scan_mode OR rtxwrclksel) = '1') ELSE + pld_tx_clk; + wr_clk_pos <= '1' WHEN (rtxpcsclkpwdn_nscan = '1') ELSE + wr_clk_pos_raw_xhdl4; + + -- TX Clock Out + tx_clk_out <= fifo_rd_clk_xhdl0; -- drives PLD clock tree + +END trans; + + + + +-- txclk_ctl_cenrtl + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_bit IS + PORT ( + + reset : IN STD_LOGIC; -- reset + clk : IN STD_LOGIC; -- clock + sig_in : IN STD_LOGIC; -- signal input + ext_in : IN STD_LOGIC; -- external input port + serial_mode : IN STD_LOGIC; -- serial shift mode enable + si : IN STD_LOGIC; -- scan input + shift : IN STD_LOGIC; -- 1'b1=shift in data from si into scan flop + -- 1'b0=load data from sig_in into scan flop + mdio_dis : IN STD_LOGIC; -- 1'b1=choose ext_in to the sig_out mux + -- 1'b0=choose so to the sign_out mux + sig_out : OUT STD_LOGIC; -- signal output + so : OUT STD_LOGIC -- scan output + ); +END cycloneiv_hssi_cmu_dprio_bit; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_bit IS + + SIGNAL cram_int : STD_LOGIC; + SIGNAL set_int : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL so_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + so <= so_xhdl0; + + -- select signal output + sig_out <= (so_xhdl0 AND NOT(shift)) WHEN (serial_mode = '1') ELSE + (cram_int); + cram_int <= (ext_in) WHEN (mdio_dis = '1') ELSE + (so_xhdl0); + + -- Set signal for the flop + set_int <= '0' WHEN (shift = '1' OR reset = '1') ELSE + ext_in; + + -- scan flop + PROCESS (reset, set_int, clk) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + so_xhdl0 <= '0'; + ELSIF (set_int = '1') THEN + so_xhdl0 <= '1'; + ELSIF (clk'EVENT AND clk = '1') THEN + IF ((shift AND serial_mode) = '1') THEN + so_xhdl0 <= si; + ELSE + + so_xhdl0 <= sig_in; + END IF; + END IF; + END PROCESS; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_bit_pma IS + PORT ( + + reset : IN STD_LOGIC; -- reset + clk : IN STD_LOGIC; -- clock + sig_in : IN STD_LOGIC; -- signal input + ext_in : IN STD_LOGIC; -- external input port + serial_mode : IN STD_LOGIC; -- serial shift mode enable + si : IN STD_LOGIC; -- scan input + shift : IN STD_LOGIC; -- 1'b1=shift in data from si into scan flop + -- 1'b0=load data from sig_in into scan flop + mdio_dis : IN STD_LOGIC; -- 1'b1=choose ext_in to the sig_out mux + -- 1'b0=choose so to the sign_out mux + pma_cram_test : IN STD_LOGIC; --1'b1: choose the previous output of this register + --1'b0: choose either si or input from DPRIO SM (sig_in) + sig_out : OUT STD_LOGIC; -- signal output + so : OUT STD_LOGIC -- scan output + ); +END cycloneiv_hssi_cmu_dprio_bit_pma; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_bit_pma IS + + SIGNAL cram_int : STD_LOGIC; + SIGNAL set_int : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL sig_out_xhdl0 : STD_LOGIC; + SIGNAL so_xhdl1 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + sig_out <= sig_out_xhdl0; + so <= so_xhdl1; + + -- select signal output + sig_out_xhdl0 <= (so_xhdl1 AND NOT(shift)) WHEN (serial_mode = '1') ELSE + (cram_int); + cram_int <= (ext_in) WHEN (mdio_dis = '1') ELSE + (so_xhdl1); + + -- Set signal for the flop + set_int <= '0' WHEN (shift = '1'OR reset = '1') ELSE + ext_in; + + -- scan flop + PROCESS (reset, set_int, clk) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + so_xhdl1 <= '0'; + ELSIF (set_int = '1') THEN + so_xhdl1 <= '1'; + ELSIF (clk'EVENT AND clk = '1') THEN + IF (pma_cram_test = '1') THEN + so_xhdl1 <= sig_out_xhdl0; + ELSIF ((shift AND serial_mode) = '1') THEN + so_xhdl1 <= si; + ELSE + + so_xhdl1 <= sig_in; + END IF; + END IF; + END PROCESS; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_16bit IS + PORT ( + + reset : IN STD_LOGIC; -- reset + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; -- clock + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- signal input + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- external port input + serial_mode : IN STD_LOGIC; -- serial shift mode enable + si : IN STD_LOGIC; -- scan input + shift : IN STD_LOGIC; -- 1'b1=shift in data from si into scan flop + -- 1'b0=load data from sig_in into scan flop + mdio_dis : IN STD_LOGIC; -- + -- 1'b1=output CRAM + -- 1'b0=output MDIO control register + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- signal output + so : OUT STD_LOGIC -- scan output + ); +END cycloneiv_hssi_cmu_dprio_16bit; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_16bit IS + COMPONENT cycloneiv_hssi_cmu_dprio_bit + PORT ( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC; + ext_in : IN STD_LOGIC; + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + sig_out : OUT STD_LOGIC; + so : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL signal_in_int : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL chain : STD_LOGIC_VECTOR(14 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL sig_out_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL so_xhdl1 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + sig_out <= sig_out_xhdl0; + so <= so_xhdl1; + + signal_in_int <= sig_in WHEN ((("000000000000000" & mdio_wr) AND int2bin((reg_addr = target_addr), 16)) /= "0000000000000000") ELSE + (so_xhdl1 & chain); + + + + ctrl_reg_bit_0 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(0), + ext_in => ext_in(0), + serial_mode => serial_mode, + si => si, + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(0), + so => chain(0) + ); + + + + ctrl_reg_bit_1 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(1), + ext_in => ext_in(1), + serial_mode => serial_mode, + si => chain(0), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(1), + so => chain(1) + ); + + + + ctrl_reg_bit_2 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(2), + ext_in => ext_in(2), + serial_mode => serial_mode, + si => chain(1), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(2), + so => chain(2) + ); + + + + ctrl_reg_bit_3 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(3), + ext_in => ext_in(3), + serial_mode => serial_mode, + si => chain(2), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(3), + so => chain(3) + ); + + + + ctrl_reg_bit_4 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(4), + ext_in => ext_in(4), + serial_mode => serial_mode, + si => chain(3), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(4), + so => chain(4) + ); + + + + ctrl_reg_bit_5 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(5), + ext_in => ext_in(5), + serial_mode => serial_mode, + si => chain(4), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(5), + so => chain(5) + ); + + + + ctrl_reg_bit_6 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(6), + ext_in => ext_in(6), + serial_mode => serial_mode, + si => chain(5), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(6), + so => chain(6) + ); + + + + ctrl_reg_bit_7 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(7), + ext_in => ext_in(7), + serial_mode => serial_mode, + si => chain(6), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(7), + so => chain(7) + ); + + + + ctrl_reg_bit_8 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(8), + ext_in => ext_in(8), + serial_mode => serial_mode, + si => chain(7), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(8), + so => chain(8) + ); + + + + ctrl_reg_bit_9 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(9), + ext_in => ext_in(9), + serial_mode => serial_mode, + si => chain(8), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(9), + so => chain(9) + ); + + + + ctrl_reg_bit_10 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(10), + ext_in => ext_in(10), + serial_mode => serial_mode, + si => chain(9), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(10), + so => chain(10) + ); + + + + ctrl_reg_bit_11 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(11), + ext_in => ext_in(11), + serial_mode => serial_mode, + si => chain(10), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(11), + so => chain(11) + ); + + + + ctrl_reg_bit_12 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(12), + ext_in => ext_in(12), + serial_mode => serial_mode, + si => chain(11), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(12), + so => chain(12) + ); + + + + ctrl_reg_bit_13 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(13), + ext_in => ext_in(13), + serial_mode => serial_mode, + si => chain(12), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(13), + so => chain(13) + ); + + + + ctrl_reg_bit_14 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(14), + ext_in => ext_in(14), + serial_mode => serial_mode, + si => chain(13), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(14), + so => chain(14) + ); + + + + ctrl_reg_bit_15 : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(15), + ext_in => ext_in(15), + serial_mode => serial_mode, + si => chain(14), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(15), + so => so_xhdl1 + ); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_16bit_pma IS + PORT ( + + reset : IN STD_LOGIC; -- reset + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; -- clock + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- signal input + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- external port input + serial_mode : IN STD_LOGIC; -- serial shift mode enable + si : IN STD_LOGIC; -- scan input + shift : IN STD_LOGIC; -- 1'b1=shift in data from si into scan flop + -- 1'b0=load data from sig_in into scan flop + mdio_dis : IN STD_LOGIC; -- + -- 1'b1=output CRAM + -- 1'b0=output MDIO control register + pma_cram_test : IN STD_LOGIC; --1'b1: choose the previous output of this register + --1'b0: choose either si or input from DPRIO SM (sig_in) + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- signal output + so : OUT STD_LOGIC -- scan output + ); +END cycloneiv_hssi_cmu_dprio_16bit_pma; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_16bit_pma IS + COMPONENT cycloneiv_hssi_cmu_dprio_bit_pma + PORT ( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC; + ext_in : IN STD_LOGIC; + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + sig_out : OUT STD_LOGIC; + so : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL signal_in_int : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL chain : STD_LOGIC_VECTOR(14 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL sig_out_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL so_xhdl1 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + sig_out <= sig_out_xhdl0; + so <= so_xhdl1; + + signal_in_int <= sig_in WHEN ((("000000000000000" & mdio_wr) AND int2bin((reg_addr = target_addr), 16)) /= "0000000000000000") ELSE + (so_xhdl1 & chain); + + + + ctrl_reg_bit_pma_0 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(0), + ext_in => ext_in(0), + serial_mode => serial_mode, + si => si, + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(0), + so => chain(0) + ); + + + + ctrl_reg_bit_pma_1 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(1), + ext_in => ext_in(1), + serial_mode => serial_mode, + si => chain(0), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(1), + so => chain(1) + ); + + + + ctrl_reg_bit_pma_2 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(2), + ext_in => ext_in(2), + serial_mode => serial_mode, + si => chain(1), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(2), + so => chain(2) + ); + + + + ctrl_reg_bit_pma_3 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(3), + ext_in => ext_in(3), + serial_mode => serial_mode, + si => chain(2), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(3), + so => chain(3) + ); + + + + ctrl_reg_bit_pma_4 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(4), + ext_in => ext_in(4), + serial_mode => serial_mode, + si => chain(3), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(4), + so => chain(4) + ); + + + + ctrl_reg_bit_pma_5 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(5), + ext_in => ext_in(5), + serial_mode => serial_mode, + si => chain(4), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(5), + so => chain(5) + ); + + + + ctrl_reg_bit_pma_6 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(6), + ext_in => ext_in(6), + serial_mode => serial_mode, + si => chain(5), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(6), + so => chain(6) + ); + + + + ctrl_reg_bit_pma_7 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(7), + ext_in => ext_in(7), + serial_mode => serial_mode, + si => chain(6), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(7), + so => chain(7) + ); + + + + ctrl_reg_bit_pma_8 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(8), + ext_in => ext_in(8), + serial_mode => serial_mode, + si => chain(7), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(8), + so => chain(8) + ); + + + + ctrl_reg_bit_pma_9 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(9), + ext_in => ext_in(9), + serial_mode => serial_mode, + si => chain(8), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(9), + so => chain(9) + ); + + + + ctrl_reg_bit_pma_10 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(10), + ext_in => ext_in(10), + serial_mode => serial_mode, + si => chain(9), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(10), + so => chain(10) + ); + + + + ctrl_reg_bit_pma_11 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(11), + ext_in => ext_in(11), + serial_mode => serial_mode, + si => chain(10), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(11), + so => chain(11) + ); + + + + ctrl_reg_bit_pma_12 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(12), + ext_in => ext_in(12), + serial_mode => serial_mode, + si => chain(11), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(12), + so => chain(12) + ); + + + + ctrl_reg_bit_pma_13 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(13), + ext_in => ext_in(13), + serial_mode => serial_mode, + si => chain(12), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(13), + so => chain(13) + ); + + + + ctrl_reg_bit_pma_14 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(14), + ext_in => ext_in(14), + serial_mode => serial_mode, + si => chain(13), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(14), + so => chain(14) + ); + + + + ctrl_reg_bit_pma_15 : cycloneiv_hssi_cmu_dprio_bit_pma + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(15), + ext_in => ext_in(15), + serial_mode => serial_mode, + si => chain(14), + shift => shift, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => sig_out_xhdl0(15), + so => so_xhdl1 + ); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_reg_chnl IS + PORT ( + -- CSR input + -- DPRIO register output + + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + ext_chnl_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + targ_addr_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + out_chnl_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + + so : OUT STD_LOGIC + ); +END cycloneiv_hssi_cmu_dprio_reg_chnl; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_reg_chnl IS + COMPONENT cycloneiv_hssi_cmu_dprio_16bit + PORT ( + reset : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_16bit_pma + PORT ( + reset : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL chain : STD_LOGIC_VECTOR(51 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL out_chnl_ctrl_1_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_2_xhdl11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_3_xhdl22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_4_xhdl33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_5_xhdl44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_6_xhdl48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_7_xhdl49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_8_xhdl50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_9_xhdl51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_10_xhdl1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_11_xhdl2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_12_xhdl3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_13_xhdl4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_14_xhdl5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_15_xhdl6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_16_xhdl7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_17_xhdl8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_18_xhdl9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_19_xhdl10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_20_xhdl12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_21_xhdl13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_22_xhdl14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_23_xhdl15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_24_xhdl16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_25_xhdl17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_26_xhdl18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_27_xhdl19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_28_xhdl20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_29_xhdl21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_30_xhdl23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_31_xhdl24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_32_xhdl25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_33_xhdl26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_34_xhdl27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_35_xhdl28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_36_xhdl29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_37_xhdl30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_38_xhdl31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_39_xhdl32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_40_xhdl34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_41_xhdl35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_42_xhdl36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_43_xhdl37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_44_xhdl38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_45_xhdl39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_46_xhdl40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_47_xhdl41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_48_xhdl42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_49_xhdl43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_50_xhdl45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_51_xhdl46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_52_xhdl47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_53_xhdl48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL so_xhdl52 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + out_chnl_ctrl_1 <= out_chnl_ctrl_1_xhdl0; + out_chnl_ctrl_2 <= out_chnl_ctrl_2_xhdl11; + out_chnl_ctrl_3 <= out_chnl_ctrl_3_xhdl22; + out_chnl_ctrl_4 <= out_chnl_ctrl_4_xhdl33; + out_chnl_ctrl_5 <= out_chnl_ctrl_5_xhdl44; + out_chnl_ctrl_6 <= out_chnl_ctrl_6_xhdl48; + out_chnl_ctrl_7 <= out_chnl_ctrl_7_xhdl49; + out_chnl_ctrl_8 <= out_chnl_ctrl_8_xhdl50; + out_chnl_ctrl_9 <= out_chnl_ctrl_9_xhdl51; + out_chnl_ctrl_10 <= out_chnl_ctrl_10_xhdl1; + out_chnl_ctrl_11 <= out_chnl_ctrl_11_xhdl2; + out_chnl_ctrl_12 <= out_chnl_ctrl_12_xhdl3; + out_chnl_ctrl_13 <= out_chnl_ctrl_13_xhdl4; + out_chnl_ctrl_14 <= out_chnl_ctrl_14_xhdl5; + out_chnl_ctrl_15 <= out_chnl_ctrl_15_xhdl6; + out_chnl_ctrl_16 <= out_chnl_ctrl_16_xhdl7; + out_chnl_ctrl_17 <= out_chnl_ctrl_17_xhdl8; + out_chnl_ctrl_18 <= out_chnl_ctrl_18_xhdl9; + out_chnl_ctrl_19 <= out_chnl_ctrl_19_xhdl10; + out_chnl_ctrl_20 <= out_chnl_ctrl_20_xhdl12; + out_chnl_ctrl_21 <= out_chnl_ctrl_21_xhdl13; + out_chnl_ctrl_22 <= out_chnl_ctrl_22_xhdl14; + out_chnl_ctrl_23 <= out_chnl_ctrl_23_xhdl15; + out_chnl_ctrl_24 <= out_chnl_ctrl_24_xhdl16; + out_chnl_ctrl_25 <= out_chnl_ctrl_25_xhdl17; + out_chnl_ctrl_26 <= out_chnl_ctrl_26_xhdl18; + out_chnl_ctrl_27 <= out_chnl_ctrl_27_xhdl19; + out_chnl_ctrl_28 <= out_chnl_ctrl_28_xhdl20; + out_chnl_ctrl_29 <= out_chnl_ctrl_29_xhdl21; + out_chnl_ctrl_30 <= out_chnl_ctrl_30_xhdl23; + out_chnl_ctrl_31 <= out_chnl_ctrl_31_xhdl24; + out_chnl_ctrl_32 <= out_chnl_ctrl_32_xhdl25; + out_chnl_ctrl_33 <= out_chnl_ctrl_33_xhdl26; + out_chnl_ctrl_34 <= out_chnl_ctrl_34_xhdl27; + out_chnl_ctrl_35 <= out_chnl_ctrl_35_xhdl28; + out_chnl_ctrl_36 <= out_chnl_ctrl_36_xhdl29; + out_chnl_ctrl_37 <= out_chnl_ctrl_37_xhdl30; + out_chnl_ctrl_38 <= out_chnl_ctrl_38_xhdl31; + out_chnl_ctrl_39 <= out_chnl_ctrl_39_xhdl32; + out_chnl_ctrl_40 <= out_chnl_ctrl_40_xhdl34; + out_chnl_ctrl_41 <= out_chnl_ctrl_41_xhdl35; + out_chnl_ctrl_42 <= out_chnl_ctrl_42_xhdl36; + out_chnl_ctrl_43 <= out_chnl_ctrl_43_xhdl37; + out_chnl_ctrl_44 <= out_chnl_ctrl_44_xhdl38; + out_chnl_ctrl_45 <= out_chnl_ctrl_45_xhdl39; + out_chnl_ctrl_46 <= out_chnl_ctrl_46_xhdl40; + out_chnl_ctrl_47 <= out_chnl_ctrl_47_xhdl41; + out_chnl_ctrl_48 <= out_chnl_ctrl_48_xhdl42; + out_chnl_ctrl_49 <= out_chnl_ctrl_49_xhdl43; + out_chnl_ctrl_50 <= out_chnl_ctrl_50_xhdl45; + out_chnl_ctrl_51 <= out_chnl_ctrl_51_xhdl46; + out_chnl_ctrl_52 <= out_chnl_ctrl_52_xhdl47; + out_chnl_ctrl_53 <= out_chnl_ctrl_53_xhdl48; + so <= so_xhdl52; + + + + chnl_ctrl_1 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_1, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_1, + serial_mode => serial_mode, + si => si, + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_1_xhdl0, + so => chain(0) + ); + + + + chnl_ctrl_2 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_2, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_2, + serial_mode => serial_mode, + si => chain(0), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_2_xhdl11, + so => chain(1) + ); + + + + chnl_ctrl_3 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_3, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_3, + serial_mode => serial_mode, + si => chain(1), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_3_xhdl22, + so => chain(2) + ); + + + + chnl_ctrl_4 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_4, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_4, + serial_mode => serial_mode, + si => chain(2), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_4_xhdl33, + so => chain(3) + ); + + + + chnl_ctrl_5 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_5, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_5, + serial_mode => serial_mode, + si => chain(3), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_5_xhdl44, + so => chain(4) + ); + + + + chnl_ctrl_6 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_6, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_6, + serial_mode => serial_mode, + si => chain(4), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_6_xhdl48, + so => chain(5) + ); + + + + chnl_ctrl_7 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_7, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_7, + serial_mode => serial_mode, + si => chain(5), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_7_xhdl49, + so => chain(6) + ); + + + + chnl_ctrl_8 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_8, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_8, + serial_mode => serial_mode, + si => chain(6), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_8_xhdl50, + so => chain(7) + ); + + + + chnl_ctrl_9 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_9, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_9, + serial_mode => serial_mode, + si => chain(7), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_9_xhdl51, + so => chain(8) + ); + + + + chnl_ctrl_10 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_10, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_10, + serial_mode => serial_mode, + si => chain(8), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_10_xhdl1, + so => chain(9) + ); + + + + chnl_ctrl_11 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_11, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_11, + serial_mode => serial_mode, + si => chain(9), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_11_xhdl2, + so => chain(10) + ); + + + + chnl_ctrl_12 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_12, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_12, + serial_mode => serial_mode, + si => chain(10), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_12_xhdl3, + so => chain(11) + ); + + + + chnl_ctrl_13 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_13, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_13, + serial_mode => serial_mode, + si => chain(11), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_13_xhdl4, + so => chain(12) + ); + + + + chnl_ctrl_14 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_14, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_14, + serial_mode => serial_mode, + si => chain(12), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_14_xhdl5, + so => chain(13) + ); + + + + chnl_ctrl_15 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_15, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_15, + serial_mode => serial_mode, + si => chain(13), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_15_xhdl6, + so => chain(14) + ); + + + + chnl_ctrl_16 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_16, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_16, + serial_mode => serial_mode, + si => chain(14), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_16_xhdl7, + so => chain(15) + ); + + + + chnl_ctrl_17 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_17, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_17, + serial_mode => serial_mode, + si => chain(15), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_17_xhdl8, + so => chain(16) + ); + + + + chnl_ctrl_18 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_18, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_18, + serial_mode => serial_mode, + si => chain(16), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_18_xhdl9, + so => chain(17) + ); + + + + chnl_ctrl_19 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_19, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_19, + serial_mode => serial_mode, + si => chain(17), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_19_xhdl10, + so => chain(18) + ); + + + + chnl_ctrl_20 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_20, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_20, + serial_mode => serial_mode, + si => chain(18), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_20_xhdl12, + so => chain(19) + ); + + + + chnl_ctrl_21 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_21, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_21, + serial_mode => serial_mode, + si => chain(19), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_21_xhdl13, + so => chain(20) + ); + + + + chnl_ctrl_22 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_22, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_22, + serial_mode => serial_mode, + si => chain(20), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_22_xhdl14, + so => chain(21) + ); + + + + chnl_ctrl_23 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_23, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_23, + serial_mode => serial_mode, + si => chain(21), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_23_xhdl15, + so => chain(22) + ); + + + + chnl_ctrl_24 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_24, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_24, + serial_mode => serial_mode, + si => chain(22), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_24_xhdl16, + so => chain(23) + ); + + + + chnl_ctrl_25 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_25, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_25, + serial_mode => serial_mode, + si => chain(23), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_25_xhdl17, + so => chain(24) + ); + + + + chnl_ctrl_26 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_26, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_26, + serial_mode => serial_mode, + si => chain(24), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_26_xhdl18, + so => chain(25) + ); + + + + chnl_ctrl_27 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_27, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_27, + serial_mode => serial_mode, + si => chain(25), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_chnl_ctrl_27_xhdl19, + so => chain(26) + ); + + + + chnl_ctrl_28 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_28, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_28, + serial_mode => serial_mode, + si => chain(26), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_28_xhdl20, + so => chain(27) + ); + + + + chnl_ctrl_29 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_29, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_29, + serial_mode => serial_mode, + si => chain(27), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_29_xhdl21, + so => chain(28) + ); + + + + chnl_ctrl_30 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_30, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_30, + serial_mode => serial_mode, + si => chain(28), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_30_xhdl23, + so => chain(29) + ); + + + + chnl_ctrl_31 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_31, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_31, + serial_mode => serial_mode, + si => chain(29), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_31_xhdl24, + so => chain(30) + ); + + + + chnl_ctrl_32 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_32, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_32, + serial_mode => serial_mode, + si => chain(30), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_32_xhdl25, + so => chain(31) + ); + + + + chnl_ctrl_33 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_33, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_33, + serial_mode => serial_mode, + si => chain(31), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_33_xhdl26, + so => chain(32) + ); + + + + chnl_ctrl_34 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_34, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_34, + serial_mode => serial_mode, + si => chain(32), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_34_xhdl27, + so => chain(33) + ); + + + + chnl_ctrl_35 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_35, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_35, + serial_mode => serial_mode, + si => chain(33), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_35_xhdl28, + so => chain(34) + ); + + + + chnl_ctrl_36 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_36, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_36, + serial_mode => serial_mode, + si => chain(34), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_36_xhdl29, + so => chain(35) + ); + + + + chnl_ctrl_37 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_37, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_37, + serial_mode => serial_mode, + si => chain(35), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_37_xhdl30, + so => chain(36) + ); + + + + chnl_ctrl_38 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_38, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_38, + serial_mode => serial_mode, + si => chain(36), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_38_xhdl31, + so => chain(37) + ); + + + + chnl_ctrl_39 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_39, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_39, + serial_mode => serial_mode, + si => chain(37), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_39_xhdl32, + so => chain(38) + ); + + + + chnl_ctrl_40 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_40, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_40, + serial_mode => serial_mode, + si => chain(38), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_40_xhdl34, + so => chain(39) + ); + + + + chnl_ctrl_41 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_41, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_41, + serial_mode => serial_mode, + si => chain(39), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_41_xhdl35, + so => chain(40) + ); + + + + chnl_ctrl_42 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_42, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_42, + serial_mode => serial_mode, + si => chain(40), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_42_xhdl36, + so => chain(41) + ); + + + + chnl_ctrl_43 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_43, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_43, + serial_mode => serial_mode, + si => chain(41), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_43_xhdl37, + so => chain(42) + ); + + + + chnl_ctrl_44 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_44, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_44, + serial_mode => serial_mode, + si => chain(42), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_44_xhdl38, + so => chain(43) + ); + + + + chnl_ctrl_45 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_45, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_45, + serial_mode => serial_mode, + si => chain(43), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_45_xhdl39, + so => chain(44) + ); + + + + chnl_ctrl_46 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_46, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_46, + serial_mode => serial_mode, + si => chain(44), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_46_xhdl40, + so => chain(45) + ); + + + + chnl_ctrl_47 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_47, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_47, + serial_mode => serial_mode, + si => chain(45), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_47_xhdl41, + so => chain(46) + ); + + + + chnl_ctrl_48 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_48, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_48, + serial_mode => serial_mode, + si => chain(46), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_48_xhdl42, + so => chain(47) + ); + + + + chnl_ctrl_49 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_49, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_49, + serial_mode => serial_mode, + si => chain(47), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_49_xhdl43, + so => chain(48) + ); + + + + chnl_ctrl_50 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_50, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_50, + serial_mode => serial_mode, + si => chain(48), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_50_xhdl45, + so => chain(49) + ); + + + + chnl_ctrl_51 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_51, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_51, + serial_mode => serial_mode, + si => chain(49), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_51_xhdl46, + so => chain(50) + ); + + + + chnl_ctrl_52 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_52, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_52, + serial_mode => serial_mode, + si => chain(50), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_52_xhdl47, + so => chain(51) + ); + + chnl_ctrl_53 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_53, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_chnl_ctrl_53, + serial_mode => serial_mode, + si => chain(51), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_chnl_ctrl_53_xhdl48, + so => so_xhdl52 + ); + + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_chnl_bus_out_mux IS + PORT ( + + chnl_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + chnl_ctrl_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END cycloneiv_hssi_cmu_dprio_chnl_bus_out_mux; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_chnl_bus_out_mux IS +BEGIN + + chnl_ctrl_out <= chnl_ctrl_in1 WHEN (reg_addr = hw_address_ctrl_in1) ELSE + chnl_ctrl_in2 WHEN (reg_addr = hw_address_ctrl_in2) ELSE + chnl_ctrl_in3 WHEN (reg_addr = hw_address_ctrl_in3) ELSE + chnl_ctrl_in4 WHEN (reg_addr = hw_address_ctrl_in4) ELSE + chnl_ctrl_in5 WHEN (reg_addr = hw_address_ctrl_in5) ELSE + chnl_ctrl_in6 WHEN (reg_addr = hw_address_ctrl_in6) ELSE + chnl_ctrl_in7 WHEN (reg_addr = hw_address_ctrl_in7) ELSE + chnl_ctrl_in8 WHEN (reg_addr = hw_address_ctrl_in8) ELSE + chnl_ctrl_in9 WHEN (reg_addr = hw_address_ctrl_in9) ELSE + chnl_ctrl_in10 WHEN (reg_addr = hw_address_ctrl_in10) ELSE + chnl_ctrl_in11 WHEN (reg_addr = hw_address_ctrl_in11) ELSE + chnl_ctrl_in12 WHEN (reg_addr = hw_address_ctrl_in12) ELSE + chnl_ctrl_in13 WHEN (reg_addr = hw_address_ctrl_in13) ELSE + chnl_ctrl_in14 WHEN (reg_addr = hw_address_ctrl_in14) ELSE + chnl_ctrl_in15 WHEN (reg_addr = hw_address_ctrl_in15) ELSE + chnl_ctrl_in16 WHEN (reg_addr = hw_address_ctrl_in16) ELSE + chnl_ctrl_in17 WHEN (reg_addr = hw_address_ctrl_in17) ELSE + chnl_ctrl_in18 WHEN (reg_addr = hw_address_ctrl_in18) ELSE + chnl_ctrl_in19 WHEN (reg_addr = hw_address_ctrl_in19) ELSE + chnl_ctrl_in20 WHEN (reg_addr = hw_address_ctrl_in20) ELSE + chnl_ctrl_in21 WHEN (reg_addr = hw_address_ctrl_in21) ELSE + chnl_ctrl_in22 WHEN (reg_addr = hw_address_ctrl_in22) ELSE + chnl_ctrl_in23 WHEN (reg_addr = hw_address_ctrl_in23) ELSE + chnl_ctrl_in24 WHEN (reg_addr = hw_address_ctrl_in24) ELSE + chnl_ctrl_in25 WHEN (reg_addr = hw_address_ctrl_in25) ELSE + chnl_ctrl_in26 WHEN (reg_addr = hw_address_ctrl_in26) ELSE + chnl_ctrl_in27 WHEN (reg_addr = hw_address_ctrl_in27) ELSE + chnl_ctrl_in28 WHEN (reg_addr = hw_address_ctrl_in28) ELSE + chnl_ctrl_in29 WHEN (reg_addr = hw_address_ctrl_in29) ELSE + chnl_ctrl_in30 WHEN (reg_addr = hw_address_ctrl_in30) ELSE + chnl_ctrl_in31 WHEN (reg_addr = hw_address_ctrl_in31) ELSE + chnl_ctrl_in32 WHEN (reg_addr = hw_address_ctrl_in32) ELSE + chnl_ctrl_in33 WHEN (reg_addr = hw_address_ctrl_in33) ELSE + chnl_ctrl_in34 WHEN (reg_addr = hw_address_ctrl_in34) ELSE + chnl_ctrl_in35 WHEN (reg_addr = hw_address_ctrl_in35) ELSE + chnl_ctrl_in36 WHEN (reg_addr = hw_address_ctrl_in36) ELSE + chnl_ctrl_in37 WHEN (reg_addr = hw_address_ctrl_in37) ELSE + chnl_ctrl_in38 WHEN (reg_addr = hw_address_ctrl_in38) ELSE + chnl_ctrl_in39 WHEN (reg_addr = hw_address_ctrl_in39) ELSE + chnl_ctrl_in40 WHEN (reg_addr = hw_address_ctrl_in40) ELSE + chnl_ctrl_in41 WHEN (reg_addr = hw_address_ctrl_in41) ELSE + chnl_ctrl_in42 WHEN (reg_addr = hw_address_ctrl_in42) ELSE + chnl_ctrl_in43 WHEN (reg_addr = hw_address_ctrl_in43) ELSE + chnl_ctrl_in44 WHEN (reg_addr = hw_address_ctrl_in44) ELSE + chnl_ctrl_in45 WHEN (reg_addr = hw_address_ctrl_in45) ELSE + chnl_ctrl_in46 WHEN (reg_addr = hw_address_ctrl_in46) ELSE + chnl_ctrl_in47 WHEN (reg_addr = hw_address_ctrl_in47) ELSE + chnl_ctrl_in48 WHEN (reg_addr = hw_address_ctrl_in48) ELSE + chnl_ctrl_in49 WHEN (reg_addr = hw_address_ctrl_in49) ELSE + chnl_ctrl_in50 WHEN (reg_addr = hw_address_ctrl_in50) ELSE + chnl_ctrl_in51 WHEN (reg_addr = hw_address_ctrl_in51) ELSE + chnl_ctrl_in52 WHEN (reg_addr = hw_address_ctrl_in52) ELSE + chnl_ctrl_in53 WHEN (reg_addr = hw_address_ctrl_in53) ELSE + "0000000000000000"; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_chnl_top IS + PORT ( + + mdio_rst : IN STD_LOGIC; -- DPRIO reset input + mdio_wr : IN STD_LOGIC; -- DPRIO register write enable + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- DPRIO register address from SM + mdc : IN STD_LOGIC; -- DPRIO clock + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- DPRIO data in from SM + serial_mode : IN STD_LOGIC; -- DPRIO serial mode enable + mdio_dis : IN STD_LOGIC; -- DPRIO disable signal (using CSR input) + pma_cram_test : IN STD_LOGIC; -- For TE/PE increased coverage for PMA DPRIO cell + ser_shift_load : IN STD_LOGIC; -- DPRIO serial shift or load control signal + si : IN STD_LOGIC; -- DPRIO serial input + -- DPRIO channel base address ID, tells which channel/central DPRIO + -- register is located + csr_chnl_in : IN STD_LOGIC_VECTOR(831 DOWNTO 0); -- CSR inputs + csr_chnl_in_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- CSR inputs + dprio_chnl_id : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + dp_chnl_out : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); -- DP + dp_chnl_out_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- outputs + + so : OUT STD_LOGIC; -- DPRIO serial out + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) -- DPRIO dataout + ); +END cycloneiv_hssi_cmu_dprio_chnl_top; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_chnl_top IS + COMPONENT cycloneiv_hssi_cmu_dprio_reg_chnl + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + ext_chnl_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_chnl_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + out_chnl_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_chnl_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + + so : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_chnl_bus_out_mux + PORT ( + chnl_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + chnl_ctrl_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + --//////////////////////////////////////////////////////////////////////// + -- begin of CRAM output ------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + -- CRAM output + -- TX PCS CRAMs + SIGNAL rforce_kchar : STD_LOGIC; -- Force /K/ char CRAM + SIGNAL rforce_echar : STD_LOGIC; -- Force /E/ char CRAM + SIGNAL rtxfifo_dis : STD_LOGIC; -- TX FIFO disable CRAM + SIGNAL rib_force_disp : STD_LOGIC; -- Disparity force CRAM in IB mode + SIGNAL rtxfifo_lowlatency_en : STD_LOGIC; -- TX FIFO low latency enable CRAM + SIGNAL rdwidth_tx : STD_LOGIC; -- TX parallel interface data width CRAM + SIGNAL rge_xaui_tx : STD_LOGIC; -- GIGE Idle test enable CRAM + SIGNAL rphfifopldentx : STD_LOGIC; -- TX phase comp. FIFO PLD read/write enable CRAM + SIGNAL rphfifoursttx : STD_LOGIC; -- TX phase comp. FIFO user reset enable CRAM + SIGNAL rtxurstpcs : STD_LOGIC; -- TX PCS user reset enable CRAm + SIGNAL rfreerun_tx : STD_LOGIC; -- TX_CLK out free running during TX PCS reset enable CRAM + SIGNAL rtxwrclksel : STD_LOGIC; -- TX FIFO write clock selection CRAM + SIGNAL rtxrdclksel : STD_LOGIC; -- TX FIFO read clock selection CRAM + SIGNAL rrev_loopbk : STD_LOGIC; -- CRAM - Enable dynamic Reverse, PIPE mode + SIGNAL rforce_disp : STD_LOGIC; -- Acting with TXD[9, 19] forces current disparity to 1 or 0 + SIGNAL rendec_tx : STD_LOGIC; -- Enable 8B/10B encoder CRAM + SIGNAL r8b10b_enc_ibm_en : STD_LOGIC; -- 8B10B Encoder fix enable CRAM + SIGNAL rcascaded_8b10b_en_tx : STD_LOGIC; -- Caascaded 8b/10b encoder enable CRAM + SIGNAL rensymswap_tx : STD_LOGIC; -- TX symbol swap enable CRAM + SIGNAL renpolinv_tx : STD_LOGIC; -- TX Polarity inversion enable CRAM + SIGNAL renbitrev_tx : STD_LOGIC; -- TX bit reversal enable CRAM + SIGNAL rprbsen_tx : STD_LOGIC; -- PRBS generator enable CRAM + SIGNAL rprbs_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- PRBS selection CRAM + SIGNAL rbisten_tx : STD_LOGIC; -- BIST generator enable CRAM + SIGNAL rbist_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- BIST selection CRAM + SIGNAL rcxpat_chnl_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- CRPAT or CJPAT selection CRAM + SIGNAL rtxpcsbypass_en : STD_LOGIC; -- Bypass TX PCS CRAM + SIGNAL rtx_pipe_enable : STD_LOGIC; -- TX PIPE interface enable CRAM + SIGNAL rtx_idle_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); -- PIPE TxElecIdle delay value CRAM + SIGNAL rtxswing_sel_ena : STD_LOGIC; -- Txswing select enable CRAM + SIGNAL rtxpcsclkpwdn : STD_LOGIC; -- Enables/Disables all clocks to TX PCS + SIGNAL rcid_pattern_tx : STD_LOGIC; -- Select CID pattern to be 0 or 1 + SIGNAL rcid_len_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Length of CID pattern in cycles + SIGNAL rself_sw_en_tx : STD_LOGIC; -- En/Disable self switch circuit for clk divider in TX clk circuit + SIGNAL rpipeline_bypass_tx : STD_LOGIC; -- Use/Don't use pipeline registers for TX inter-quad signals + SIGNAL rphfifo_regmode_tx : STD_LOGIC; -- Enable TX phase comp register mode + SIGNAL rtxbitslip_en : STD_LOGIC; -- 1: Enable TX bitslip for CPRI, 0: Normal operation (default) + + -- RX PCS CRAMs + SIGNAL rrxurstpcs : STD_LOGIC; -- RX PCS user reset enable CRAm + SIGNAL rfreerun_rx : STD_LOGIC; -- RX_CLK out free running during RX PCS reset enable CRAM + SIGNAL rrcvd_clk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- RCVD_CLK domain selection CRAM + SIGNAL rclk_1_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- CLK_1 domain selection CRAM + SIGNAL rclk_2_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- CLK_2 domain selection CRAM + SIGNAL rrx_rd_clk_sel : STD_LOGIC; -- RX FIFO read clock selection CRAM + SIGNAL rprbsen_rx : STD_LOGIC; -- PRBS Verifier enable CRAM + SIGNAL rprbs_clr_rslt_rx : STD_LOGIC; -- PRBS pass/fail flag clear CRAM + SIGNAL rbisten_rx : STD_LOGIC; -- BIST Verifier enable CRAM + SIGNAL rbist_clr_rx : STD_LOGIC; -- BIST pass/fail flag clear CRAM + SIGNAL rall_one_dect_only : STD_LOGIC; -- PRBS Verifier detect all one only enable CRAM + SIGNAL rrxpcsbypass_en : STD_LOGIC; -- RX PCS bypass CRAM + SIGNAL resync_badcg_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- + SIGNAL rencdt_rising : STD_LOGIC; -- encdt on rising edge enable CRAM + SIGNAL rdis_rx_disp : STD_LOGIC; -- Receive running disparity calculation disable CRAM + SIGNAL rcomp_pat_porn : STD_LOGIC; -- Positive and negative match enable CRAM + SIGNAL rcomp_size : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Pattern comparision length CRAMs + SIGNAL rcomp_pat : STD_LOGIC_VECTOR(39 DOWNTO 0); -- Sync pattern CRAMs + SIGNAL rsync_sm_dis : STD_LOGIC; -- GIGE/XAUI Sync SM disable CRAM + SIGNAL rib_inv_cd : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Invalid code setting CRAMs for IB + SIGNAL renumber : STD_LOGIC_VECTOR(5 DOWNTO 0); -- Number of consecutive errors without valid data to goto LOSS_OF_SYNC + SIGNAL rkchar : STD_LOGIC; -- use kchar at cg_bad logic calculation + SIGNAL rosbased : STD_LOGIC; -- Enable ordered-set based algorithm + SIGNAL rosnumber : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Length of the ordered set + SIGNAL rwa_6g_en : STD_LOGIC; -- 6G word alignment enable CRAM + SIGNAL rbysync_polinv_en : STD_LOGIC; -- Word alignment polarity inversion enable CRAM + SIGNAL rbitloc_rev_en : STD_LOGIC; -- Bit reversal enable CRAM + SIGNAL rgnumber : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Number of consecutive good data to approach SYNC_ACQ + SIGNAL rknumber : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC + SIGNAL rrundisp : STD_LOGIC_VECTOR(5 DOWNTO 0); -- Run lengh violation setting CRAMs + SIGNAL rbyte_rev_en : STD_LOGIC; -- Byte swap enable CRAM + SIGNAL rforce_sig_det_pcs : STD_LOGIC; -- Forcing sigdet to high in PCS CRAM + SIGNAL rlp20ben : STD_LOGIC; -- 20-b loopback enable CRAM + SIGNAL rrlv_en : STD_LOGIC; -- RLV enable CRAM + SIGNAL rautobtalg_dis : STD_LOGIC; -- BITSLIP mode enable CRAM + SIGNAL rendec_rx : STD_LOGIC; -- 10B/8B decoder enable CRAM + SIGNAL r8b10b_dec_ibm_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- 8B10B Decoder fix enable CRAM + SIGNAL rcascaded_8b10b_en_rx : STD_LOGIC; -- Cascaded 8B/10B decoder enable CRAM + SIGNAL renpolinv_rx : STD_LOGIC; -- Allow polarity inversion + SIGNAL rmatchen : STD_LOGIC; -- Clock compensation enable CRAM + SIGNAL rgenericfifo : STD_LOGIC; -- GenericFIFO mode enable CRAM + SIGNAL rskpsetbased : STD_LOGIC; -- Enable rate matching for PCI-E/PIPE, other standards based on COMMA DEL DEL.. + SIGNAL rtruebac2bac : STD_LOGIC; -- Enabled (high) for all standards except PIPE. Back to back rate match enable. + SIGNAL rclkcmpinsertpad : STD_LOGIC; -- Rate matching pad insertion enable CRAM + SIGNAL rclkcmpsqmd : STD_LOGIC; -- How many characters to match + SIGNAL rclkcmpsq1p : STD_LOGIC_VECTOR(19 DOWNTO 0); -- Programmable 20-bit encoded comp sequence pos. disp. + SIGNAL rclkcmpsq1n : STD_LOGIC_VECTOR(19 DOWNTO 0); -- Programmable 20-bit encoded comp sequence neg. disp. + SIGNAL rclkcmp_pipe_en : STD_LOGIC; -- RM FIFO Pipe-compatible mode enable CRAM + SIGNAL rins_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Rate Match FIFO programmable insertion threshold CRAMs + SIGNAL rdel_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Rate Match FIFO programmable delettion threshold CRAMs + SIGNAL rfull_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Rate Match FIFO programmable full condition threshold CRAMs + SIGNAL rempty_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Rate Match FIFO programmable empty condition threshold CRAMs + SIGNAL rstart_threshold : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Rate Match FIFO programmable start point CRAMs + SIGNAL rpma_done_count : STD_LOGIC_VECTOR(17 DOWNTO 0); -- Programmable counter threshold for pma_done_int (1ms) + SIGNAL rpma_done_gen_ena : STD_LOGIC; -- Enable/Disable internal generation of PMA_DONE + SIGNAL rhip_ena : STD_LOGIC; -- Enable/Disable Hard IP + SIGNAL rauto_speed_ena : STD_LOGIC; -- Enable/Disable Auto Speed Negotiation + SIGNAL rfreq_sel : STD_LOGIC; -- 1: Frequency Scaling, 0: Data width scaling + SIGNAL rrxfifo_dis : STD_LOGIC; -- RX FIFO bypassing CRAM + SIGNAL rrxfifo_lowlatency_en : STD_LOGIC; -- RX FIFO low latency enable CRAM + SIGNAL rdwidth_rx : STD_LOGIC; -- RX parallel interface data width selection CRAM + SIGNAL rphfifourstrx : STD_LOGIC; -- Enable phfifourst_rx + SIGNAL rcmpfifourst : STD_LOGIC; -- Enable cmpfifourst + SIGNAL rinvalid_code_err_only : STD_LOGIC; -- enable error (EDB) replacement only on invalid code-group in RX FIFO + SIGNAL rbytord_2sym_en : STD_LOGIC; -- Enable 2 symbols byte orderring CRAM + SIGNAL rbyteorden : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Byte ordering enable CRAM + SIGNAL rbytordplden : STD_LOGIC; -- PLD control signal BYTEORDPLD enable CRAM + SIGNAL rphfifopldenrx : STD_LOGIC; -- RX phase comp. FIFO read/write enable CRAM + SIGNAL rautoinsdis : STD_LOGIC; -- Disable CRAM for auto insertion of 8'h9C + SIGNAL rtest_bus_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Per channel test bus selection CRAMs + SIGNAL rbytordpat : STD_LOGIC_VECTOR(19 DOWNTO 0); -- Byte ordering pattern CRAM + SIGNAL rbytordpad : STD_LOGIC_VECTOR(9 DOWNTO 0); -- Byte ordering pad pattern CRAM + SIGNAL rrx_pipe_enable : STD_LOGIC; -- RX PIPE interface enable CRAM + SIGNAL rrx_detect_bypass : STD_LOGIC; -- PMA RX detection bypass enable CRAM + SIGNAL rind_error_reporting : STD_LOGIC; -- Enable individual reporting for rxstatus in 8b/10b error and disparity error + SIGNAL rphystatus_delay : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Programmable dleay for the PHYSTATUS flag when power transtition + SIGNAL reidleinferenable : STD_LOGIC; -- Enable Electrical Idle inference module + SIGNAL rk285detect : STD_LOGIC; -- Enable detection of K28.7 in PMA for EIdle exit + SIGNAL reidle_com_detect : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Thet number of COMs required to enter/exit EIdle + SIGNAL rphystatus_rst_toggle : STD_LOGIC; -- Enable option for PIPE PHY_STATUS wire toggle upon exitting reset + SIGNAL rload_shreg_del : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Programmable delay to allow for loading of the shadow registers before re-enabling the clock driving the PCS logic + SIGNAL rrxpcsclkpwdn : STD_LOGIC; -- Enables/Disables all clocks to RX PCS + SIGNAL rcdr_ctrl_en : STD_LOGIC; -- Enable/Disable CDR control block + SIGNAL rbytord_s2gx : STD_LOGIC; -- 0: S4GX Byte ordering (trigger on every WA lock), 1: S2GX BO behavior + SIGNAL rbytord_6g_mask_en : STD_LOGIC; -- 0: 6G BO normal operation, 1: mask out upper byte + SIGNAL rwait_count : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Minimum programmable period of time that LTR is asserted when CDR is enabled + SIGNAL rwait_for_phfifo_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Counter timeout value to delay disabling of phase comp FIFO after rate change + SIGNAL rfts_count : STD_LOGIC_VECTOR(9 DOWNTO 0); -- Programmable timer during which CDR control block controls PPM detector + SIGNAL rcid_pattern_rx : STD_LOGIC; -- Select CID pattern to be 0 or 1 + SIGNAL rcid_len_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Length of CID pattern in cycles + SIGNAL rppm_meas_delay : STD_LOGIC; -- 0: Wait 200, 1: Wait 400 cycles before starting post-eidle-exit PPM measurement + SIGNAL rphfifo_regmode_rx : STD_LOGIC; -- Enable RX phase comp register mode + SIGNAL rcid_en : STD_LOGIC; -- PIPE only, enable generation of early_eios by CDR to place in protected CID mode + SIGNAL rrxvalid_mask : STD_LOGIC; -- PIPE only, enables masking of rxvalid by CDR control block + SIGNAL rself_sw_en_rx : STD_LOGIC; -- En/Disable self switch circuit for clk divider in TX clk circuit + SIGNAL rpipeline_bypass_rx : STD_LOGIC; -- Use/Don't use pipeline registers for TX inter-quad signals + SIGNAL rauto_deassert_pc_rst_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Programmable counter threshold for timing to release sync reset to PC ptrs + SIGNAL rauto_pc_en_cnt : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Programmable counter threshold for timing to delay phystatus notification to upper layer + SIGNAL riei_eios_priority_dis : STD_LOGIC; -- Disable EIOS detection priority over EIdle Inference when EIdle Inference is enabled + SIGNAL rgen1_sigdet_ena : STD_LOGIC; -- Usage of signal detect under Gen 1 conditions when EIdle Inference is enabled + SIGNAL rmask_count : STD_LOGIC_VECTOR(9 DOWNTO 0); -- Programmable counter to mask out the high bit error period upon exiting electrical + -- idle in terms of number of gen1 cycles + + --////////////// + -- TX PMA CRAMs + --////////////// + SIGNAL rvod_sel_non_pcie : STD_LOGIC_VECTOR(2 DOWNTO 0); -- TX wire buffer Vod switching control CRAMs + SIGNAL rvod_sela : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rvod_selb : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rvod_selc : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rvod_seld : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rpowdnt : STD_LOGIC; -- TX channel power down CRAM + SIGNAL rpre_em_1t_no_pcie : STD_LOGIC_VECTOR(4 DOWNTO 0); -- TX wire buffer pre-emphasis switching control for 1st post tap + SIGNAL rpre_em_1t_a : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rpre_em_1t_b : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rpre_em_1t_c : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rpre_em_2t : STD_LOGIC_VECTOR(3 DOWNTO 0); -- TX wire buffer pre-emphasis switching control for 2nd post tap + SIGNAL rpre_em_pt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- TX wire buffer pre-emphasis switching control for pre-tap + SIGNAL rtx_term_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- TX's Differential Termination selction CRAMs + SIGNAL rtx_vtt : STD_LOGIC_VECTOR(1 DOWNTO 0); -- TX's Common-mode driver selection control CRAMs + SIGNAL rtx_lst : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Low Speed Test Selection CRAMs. + SIGNAL rslew : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Slew rate control for TX + SIGNAL rsig_inv_ptap : STD_LOGIC; -- Signal invert for Pre-tap + SIGNAL rsig_inv_2t : STD_LOGIC; -- Signal invert for 2nd Post tap + SIGNAL rrx_det : STD_LOGIC_VECTOR(1 DOWNTO 0); -- RAM bit for RX signal detect + SIGNAL rlowv : STD_LOGIC; -- 0: cascaded current source/sink, 1: bypass cascaded current source/sink + SIGNAL r_dft_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Design for testing selection to check decoder outputs of main tap, 1st post tap, 2nd + -- post tap, and pre-tap + SIGNAL rtx_ob_pdb : STD_LOGIC; -- TX Power down CRAM (1: normal operation, 0: power down) + + --Serializer - Clock Generation Block (SER-CGB) CRAMs + SIGNAL rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Single channel mode (X1 mode) enable CRAM (individual clock drives individual Serializer) + SIGNAL rcgb_cmu_sel : STD_LOGIC; -- CMU selection CRAM in CLKGENBUF_6G block + SIGNAL rcgb_m_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Division ratio selection CRAM for input clock in CLKGENBU /net/grouse/nobackup F_6G block + SIGNAL rpma_doublewidth_tx : STD_LOGIC; -- TX PCS to TX PMA double data width (16/20) enable CRAM (S2GX RPMA_DOUBLEWIDTH_TX) + SIGNAL rpmadwidth_tx : STD_LOGIC; -- TX PCS to TX PMA data width (8/10)selection CRAM (S2GX RPMADWIDTH_TX) + SIGNAL rcgb_delay_sel : STD_LOGIC; -- Insert 6 gates delay CRAM for CLKMUX in TX channel + SIGNAL rs_lpbk : STD_LOGIC; -- reverse loop back control CRAM + SIGNAL rdynamic_sw : STD_LOGIC; -- 0: disable dynamic switch, 1: enable dynamic switch + SIGNAL rpclksel : STD_LOGIC; -- 0: select local pclk, 1: select global pclk + SIGNAL rtx_cgb_pdb : STD_LOGIC; -- Power down CRAM for CLKGENBUF, CLKMUX, and Serializer in TX channel (1: normal operation) + + --C_TX_RX CRAMs + SIGNAL riqclk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- RX path CLKMUX selection CRAM to select either iqclk or pldclk + SIGNAL rrefclk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- RX path REFCLKMUX selection CRAM + SIGNAL rvcobypass : STD_LOGIC; -- RX clock selection sent to PCS + SIGNAL rrevlb_sw : STD_LOGIC; -- Switch select signal for TX_RLPBK + SIGNAL rimpctrl : STD_LOGIC; -- Control calibration bi-direction buffer + SIGNAL rrx_refclk : STD_LOGIC; -- RAM bit to choose RX clock to train CDR + SIGNAL rpcs_sd_sel : STD_LOGIC; -- 0: select analog signal detect output, 1: select digital signal detect output + + --Reserved CRAMs for TX PMA and RX PMA + SIGNAL rpma_reserved : STD_LOGIC_VECTOR(31 DOWNTO 0); --Reserved bits for RX/TX PMA channel divided into 2 sixteen bit busses + --End TX CRAMs + + --////////////// + -- RX PMA CRAMs + --////////////// + SIGNAL rrx_lst : STD_LOGIC_VECTOR(4 DOWNTO 0); -- ATB Control Bits (refer to ATB table for details) + SIGNAL rrx_bit_dc : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Select pin for DC gain 0db, 3db, 6db, 9db and 12 db + SIGNAL rrx_s_rdlpbk : STD_LOGIC; -- Loopback control pin + SIGNAL rrx_vtt : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Control bits for common mode driver + SIGNAL rrx_term_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- RX's Differential Termination selection CRAMs + SIGNAL rrx_sdlv : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Control bits for Signal Detect hysteresis (TBD) + SIGNAL rrx_oc_en : STD_LOGIC; -- Offset Cancellation control (TBD) + SIGNAL rrx_oc : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Offset Cancellation control (TBD) + SIGNAL rrx_sd_force : STD_LOGIC; -- Signal detect override + SIGNAL rrx_test : STD_LOGIC; -- Loopback to test ADCE and EQ stages + SIGNAL rrxurstpma : STD_LOGIC; -- Enable CRAM for RXURSTPMA dynamic signal + SIGNAL rrx_sd_on : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Control bits for Signal Detect + SIGNAL rrx_sd_off : STD_LOGIC_VECTOR(4 DOWNTO 0); -- Control bits for Signal Detect + SIGNAL rrx_oc_calpd : STD_LOGIC; -- Offset cancellation calibration mode + SIGNAL rurx_pdb : STD_LOGIC; -- RX/DFE power down + SIGNAL rrx_ib_pdb : STD_LOGIC; -- RX Power down CRAM (1: normal operation, 0: power down) + SIGNAL rpowdnr : STD_LOGIC; -- RX channel power down CRAM + + -- CDR CRAMs + SIGNAL rcru_div2 : STD_LOGIC; -- Reference clock divided by two enable CRAMS + SIGNAL rcru_m_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Division ratio selection of input clock + SIGNAL rcru_m : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Programmable Control. Select among 1,4,5,8,10,16,20 and 25. + SIGNAL rcru_l : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Programmable Control. Select among 1,2, and 4. + SIGNAL rcru_ctl0 : STD_LOGIC; -- CTL0 is Programmable Control CRAMs for Ring VCO frequency range control + SIGNAL rcru_crplctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Ripple capacitor control CRAM: + SIGNAL rcru_pfdbwctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); -- RXPLL PFD mode BW control CRAMS (resistor control in loop filter for PFD mode) + SIGNAL rcru_pdbwctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); -- RXPLL PD mode BW control CRAMS (resistor control in loop filter for PD mode) + SIGNAL rcru_rlbk : STD_LOGIC; -- Enable reverse serial loopback from RX CDR to TX wire buffer with main tab + SIGNAL rcru_lst : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Low speed test selection CRAM + SIGNAL rcru_testen : STD_LOGIC; -- Charge Pump Current test mode control CRAM in RXPLL + SIGNAL rcru_testupen : STD_LOGIC; -- Charge Pump UP current test control CRAM in RXPLL + SIGNAL rcru_testdnen : STD_LOGIC; -- Charge Pump DOWN current test control CRAM in RXPLL + SIGNAL rcru_isel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- RXPLL charge pump current control CRAM + SIGNAL rcru_iselpd : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Charge pump current control CRAM at PD mode + + SIGNAL rcp_mode : STD_LOGIC; -- Charge pump mode select CRAM + SIGNAL rltd : STD_LOGIC; -- Lock to Data enable signal (0: normal operation) + SIGNAL rltr : STD_LOGIC; -- Lock to Reference enable signal (0: normal operation) + SIGNAL rrx_cru_pdb : STD_LOGIC; -- Power down CRAM for CRU in RX channel (1: normal operation) + SIGNAL rrx_cru_rst : STD_LOGIC; -- CRU reset CRAM (1: normal operation) + SIGNAL rcru_cmu_mode : STD_LOGIC; -- Used to disable the buffers in the L-counter when the CDR is configured just as a + -- TXPLL + SIGNAL rcru_ignore_phslck : STD_LOGIC; -- Used in LCK2REFCTRL block that will override Lock Detect outcome + SIGNAL rcru_sd_sel : STD_LOGIC; -- Select signal detect wire either from analog signal detect or digital signal detect blocks for CDR + SIGNAL rcru_pdfl : STD_LOGIC; -- Fast Lock control. Use when the data is suddently switched to a different phase (esp 90 degree out of phase) + SIGNAL rcru_pdof_test : STD_LOGIC_VECTOR(2 DOWNTO 0); -- These RAM bits are used to characterize the offset of SALATCHs inside the BBPD + SIGNAL rcru_rgla_isel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Increase 1.8V regulator wire voltage. + + SIGNAL rcru_pdof_0i : STD_LOGIC_VECTOR(3 DOWNTO 0); -- BBPD SALATCH offset control. Latch connects to CLK0. Choose either Left or Right, not both. + SIGNAL rcru_pdof_90i : STD_LOGIC_VECTOR(3 DOWNTO 0); -- BBPD SALATCH offset control. Latch connects to CLK90. Choose either Left or Right, not both. + SIGNAL rcru_pdof_180i : STD_LOGIC_VECTOR(3 DOWNTO 0); -- BBPD SALATCH offset control. Latch connects to CLK180. Choose either Left or Right, not both. + SIGNAL rcru_pdof_270i : STD_LOGIC_VECTOR(3 DOWNTO 0); -- BBPD SALATCH offset control. Latch connects to CLK270. Choose either Left or Right, not both. + + --Reserved CRAMs for RX PMA (declared above) + --wire [15:0] rpma_reserved[15:0]; //Reserved bits for RX PMA channel + + --DeSerializer CRAMs + SIGNAL rpma_doublewidth_rx : STD_LOGIC; -- RX PMA to RX PCS double data width (16/20) enable CRAM (S2GX RPMA_DOUBLEWIDTH_RX) + SIGNAL rpmadwidth_rx : STD_LOGIC; -- RX PMA to RX PCS data width (8/10) selection CRAM (S2GX RPMADWIDTH_RX) + SIGNAL rtest_fastsd : STD_LOGIC; -- Mux select between Fast SD circuit and Test signal + SIGNAL rfastsd : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Controls Fast Signal Detect Logic + SIGNAL rppmsel : STD_LOGIC_VECTOR(5 DOWNTO 0); -- Programmable PPM ajustment CRAM + SIGNAL rforce0_freqdet : STD_LOGIC; -- Forcing FREQDET signal to low CRAM + SIGNAL rforce1_freqdet : STD_LOGIC; -- Forcing FREQDET signal to high CRAM + SIGNAL rppm_cnt_reset : STD_LOGIC; -- PPM counter reset CRAM (latched version on Test bus) + + --DFE CRAMs + SIGNAL r_dfe_1t : STD_LOGIC_VECTOR(2 DOWNTO 0); -- DFE 1st tap setting + SIGNAL r_dfe_2t : STD_LOGIC_VECTOR(2 DOWNTO 0); -- DFE 2nd tap setting + SIGNAL rppm_post_eidle_del : STD_LOGIC; + SIGNAL rppm_gen1_2xcnt_en : STD_LOGIC; + + --ADCE CRAMs + SIGNAL reqa_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL reqb_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL reqc_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL reqd_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL reqv_set : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rlock_lf_ovd : STD_LOGIC; -- Overdrive the dependency of ADAPT_DONE on low-frequency path + SIGNAL rseq_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Used to select the sequence of adaptation (these bits for characterization only) + SIGNAL radce_adapt : STD_LOGIC; -- This signal is used in conjunction with ADCE_PDB + SIGNAL rrgen_set : STD_LOGIC_VECTOR(2 DOWNTO 0); -- These are the 3 MSB bits controlling the D2A + SIGNAL rclkdiv : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Effective division ratio for LFCLK and HFCLK + SIGNAL rhyst_lf : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Sets low-frequency path programmable digital filtering. When set to 000 the digital filter is bypassed. + SIGNAL rdc_freq : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Sets corner frequency for the DC block. + SIGNAL rhyst_hf : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Sets high-frequency path programmable digital filtering. When set to 000 the digital filter is bypassed. + SIGNAL rf_lpf : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Sets corner frequency for the LPF. + SIGNAL rf_hpf : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Sets corner frequency for the HPF. + SIGNAL rrgen_vod : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Sets RGEN amplitude + SIGNAL rrgen_bw : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Sets corner frequency of RGEN. + SIGNAL rrect_adj : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Sets rectifier leaker and amplifier current. + SIGNAL rd2a_res : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Sets the D2A resolution. Default is 8 bit resolution. Adaptation time may be faster for lower resolution, but jitter may be increased. + SIGNAL rlf_os : STD_LOGIC_VECTOR(3 DOWNTO 0); -- These bits are for characterization purposes only. These bits will allow cancellation of systematic offset in the low frequency loop + SIGNAL rhf_os : STD_LOGIC_VECTOR(3 DOWNTO 0); -- These bits are for characterization purposes only. These bits will allow cancellation of systematic offset in the high frequency loop. + SIGNAL radce_rst : STD_LOGIC; -- Presets counters in adaptive engine + SIGNAL radce_pdb : STD_LOGIC; -- Used in conjunction with RADCE_ADAPT + SIGNAL radce_hflck : STD_LOGIC_VECTOR(14 DOWNTO 0); -- These bits are used in the HF portion of the adapt macro + SIGNAL radce_lflck : STD_LOGIC_VECTOR(14 DOWNTO 0); -- These bits are used in the adapt_done macro + SIGNAL radce_digital : STD_LOGIC_VECTOR(9 DOWNTO 0); -- Reserved bits + + --End RX CRAMs + + --//////////////////////////////////////////////////////////////////////// + -- end of CRAM output --------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + SIGNAL targ_addr_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL out_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_chnl_ctrl_53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL so_xhdl54 : STD_LOGIC; + SIGNAL mbus_out_xhdl53 : STD_LOGIC_VECTOR(15 DOWNTO 0); +BEGIN + -- Drive referenced outputs + so <= so_xhdl54; + mbus_out <= mbus_out_xhdl53; + + --//////////////////////////////////////////////////////////////////////// + -- begin of CRAM output ------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + dp_chnl_out(15 DOWNTO 0) <= out_chnl_ctrl_1; + dp_chnl_out(31 DOWNTO 16) <= out_chnl_ctrl_2; + dp_chnl_out(47 DOWNTO 32) <= out_chnl_ctrl_3; + dp_chnl_out(63 DOWNTO 48) <= out_chnl_ctrl_4; + dp_chnl_out(79 DOWNTO 64) <= out_chnl_ctrl_5; + dp_chnl_out(95 DOWNTO 80) <= out_chnl_ctrl_6; + dp_chnl_out(111 DOWNTO 96) <= out_chnl_ctrl_7; + dp_chnl_out(127 DOWNTO 112) <= out_chnl_ctrl_8; + dp_chnl_out(143 DOWNTO 128) <= out_chnl_ctrl_9; + dp_chnl_out(159 DOWNTO 144) <= out_chnl_ctrl_10; + dp_chnl_out(175 DOWNTO 160) <= out_chnl_ctrl_11; + dp_chnl_out(191 DOWNTO 176) <= out_chnl_ctrl_12; + dp_chnl_out(207 DOWNTO 192) <= out_chnl_ctrl_13; + dp_chnl_out(223 DOWNTO 208) <= out_chnl_ctrl_14; + dp_chnl_out(239 DOWNTO 224) <= out_chnl_ctrl_15; + dp_chnl_out(255 DOWNTO 240) <= out_chnl_ctrl_16; + dp_chnl_out(271 DOWNTO 256) <= out_chnl_ctrl_17; + dp_chnl_out(287 DOWNTO 272) <= out_chnl_ctrl_18; + dp_chnl_out(303 DOWNTO 288) <= out_chnl_ctrl_19; + dp_chnl_out(319 DOWNTO 304) <= out_chnl_ctrl_20; + dp_chnl_out(335 DOWNTO 320) <= out_chnl_ctrl_21; + dp_chnl_out(351 DOWNTO 336) <= out_chnl_ctrl_22; + dp_chnl_out(367 DOWNTO 352) <= out_chnl_ctrl_23; + dp_chnl_out(383 DOWNTO 368) <= out_chnl_ctrl_24; + dp_chnl_out(399 DOWNTO 384) <= out_chnl_ctrl_25; + dp_chnl_out(415 DOWNTO 400) <= out_chnl_ctrl_26; + dp_chnl_out(431 DOWNTO 416) <= out_chnl_ctrl_27; + dp_chnl_out(447 DOWNTO 432) <= out_chnl_ctrl_28; + dp_chnl_out(463 DOWNTO 448) <= out_chnl_ctrl_29; + dp_chnl_out(479 DOWNTO 464) <= out_chnl_ctrl_30; + dp_chnl_out(495 DOWNTO 480) <= out_chnl_ctrl_31; + dp_chnl_out(511 DOWNTO 496) <= out_chnl_ctrl_32; + dp_chnl_out(527 DOWNTO 512) <= out_chnl_ctrl_33; + dp_chnl_out(543 DOWNTO 528) <= out_chnl_ctrl_34; + dp_chnl_out(559 DOWNTO 544) <= out_chnl_ctrl_35; + dp_chnl_out(575 DOWNTO 560) <= out_chnl_ctrl_36; + dp_chnl_out(591 DOWNTO 576) <= out_chnl_ctrl_37; + dp_chnl_out(607 DOWNTO 592) <= out_chnl_ctrl_38; + dp_chnl_out(623 DOWNTO 608) <= out_chnl_ctrl_39; + dp_chnl_out(639 DOWNTO 624) <= out_chnl_ctrl_40; + dp_chnl_out(655 DOWNTO 640) <= out_chnl_ctrl_41; + dp_chnl_out(671 DOWNTO 656) <= out_chnl_ctrl_42; + dp_chnl_out_reserved(15 DOWNTO 0) <= out_chnl_ctrl_43; -- Table43 not part of regular csr + dp_chnl_out(687 DOWNTO 672) <= out_chnl_ctrl_44; + dp_chnl_out(703 DOWNTO 688) <= out_chnl_ctrl_45; + dp_chnl_out(719 DOWNTO 704) <= out_chnl_ctrl_46; + dp_chnl_out(735 DOWNTO 720) <= out_chnl_ctrl_47; + dp_chnl_out(751 DOWNTO 736) <= out_chnl_ctrl_48; + dp_chnl_out(767 DOWNTO 752) <= out_chnl_ctrl_49; + dp_chnl_out(783 DOWNTO 768) <= out_chnl_ctrl_50; + dp_chnl_out(799 DOWNTO 784) <= out_chnl_ctrl_51; + dp_chnl_out(815 DOWNTO 800) <= out_chnl_ctrl_52; + dp_chnl_out(831 DOWNTO 816) <= out_chnl_ctrl_53; + + --//////////////////////////////////////////////////////////////////////// + -- end of CRAM output --------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + -- Control register address assignment + -- PCS channel address space + targ_addr_ctrl_1 <= (dprio_chnl_id & "000000000000") + "0000000000000000"; + targ_addr_ctrl_2 <= (dprio_chnl_id & "000000000000") + "0000000000000001"; + targ_addr_ctrl_3 <= (dprio_chnl_id & "000000000000") + "0000000000000010"; + targ_addr_ctrl_4 <= (dprio_chnl_id & "000000000000") + "0000000000000011"; + targ_addr_ctrl_5 <= (dprio_chnl_id & "010000000000") + "0000000000000000"; + targ_addr_ctrl_6 <= (dprio_chnl_id & "010000000000") + "0000000000000001"; + targ_addr_ctrl_7 <= (dprio_chnl_id & "010000000000") + "0000000000000010"; + targ_addr_ctrl_8 <= (dprio_chnl_id & "010000000000") + "0000000000000011"; + targ_addr_ctrl_9 <= (dprio_chnl_id & "010000000000") + "0000000000000100"; + targ_addr_ctrl_10 <= (dprio_chnl_id & "010000000000") + "0000000000000101"; + targ_addr_ctrl_11 <= (dprio_chnl_id & "010000000000") + "0000000000000110"; + targ_addr_ctrl_12 <= (dprio_chnl_id & "010000000000") + "0000000000000111"; + targ_addr_ctrl_13 <= (dprio_chnl_id & "010000000000") + "0000000000001000"; + targ_addr_ctrl_14 <= (dprio_chnl_id & "010000000000") + "0000000000001001"; + targ_addr_ctrl_15 <= (dprio_chnl_id & "010000000000") + "0000000000001010"; + targ_addr_ctrl_16 <= (dprio_chnl_id & "010000000000") + "0000000000001011"; + targ_addr_ctrl_17 <= (dprio_chnl_id & "010000000000") + "0000000000001100"; + targ_addr_ctrl_18 <= (dprio_chnl_id & "010000000000") + "0000000000001101"; + targ_addr_ctrl_19 <= (dprio_chnl_id & "010000000000") + "0000000000001110"; + targ_addr_ctrl_20 <= (dprio_chnl_id & "010000000000") + "0000000000001111"; + targ_addr_ctrl_21 <= (dprio_chnl_id & "010000000000") + "0000000000010000"; + targ_addr_ctrl_22 <= (dprio_chnl_id & "010000000000") + "0000000000010001"; + targ_addr_ctrl_23 <= (dprio_chnl_id & "010000000000") + "0000000000010010"; + targ_addr_ctrl_24 <= (dprio_chnl_id & "010000000000") + "0000000000010011"; + targ_addr_ctrl_25 <= (dprio_chnl_id & "010000000000") + "0000000000010100"; + targ_addr_ctrl_26 <= (dprio_chnl_id & "010000000000") + "0000000000010101"; + targ_addr_ctrl_27 <= (dprio_chnl_id & "010000000000") + "0000000000010110"; + + -- PMA channel address space + targ_addr_ctrl_28 <= (dprio_chnl_id & "100000000000") + "0000000000000000"; + targ_addr_ctrl_29 <= (dprio_chnl_id & "100000000000") + "0000000000000001"; + targ_addr_ctrl_30 <= (dprio_chnl_id & "100000000000") + "0000000000000010"; + targ_addr_ctrl_31 <= (dprio_chnl_id & "100000000000") + "0000000000000011"; + targ_addr_ctrl_32 <= (dprio_chnl_id & "100000000000") + "0000000000000100"; + targ_addr_ctrl_33 <= (dprio_chnl_id & "100000000000") + "0000000000000101"; + targ_addr_ctrl_34 <= (dprio_chnl_id & "100000000000") + "0000000000000110"; + targ_addr_ctrl_35 <= (dprio_chnl_id & "100000000000") + "0000000000000111"; + targ_addr_ctrl_36 <= (dprio_chnl_id & "110000000000") + "0000000000000000"; + targ_addr_ctrl_37 <= (dprio_chnl_id & "110000000000") + "0000000000000001"; + targ_addr_ctrl_38 <= (dprio_chnl_id & "110000000000") + "0000000000000010"; + targ_addr_ctrl_39 <= (dprio_chnl_id & "110000000000") + "0000000000000011"; + targ_addr_ctrl_40 <= (dprio_chnl_id & "110000000000") + "0000000000000100"; + targ_addr_ctrl_41 <= (dprio_chnl_id & "110000000000") + "0000000000000101"; + targ_addr_ctrl_42 <= (dprio_chnl_id & "110000000000") + "0000000000000110"; + targ_addr_ctrl_43 <= (dprio_chnl_id & "110000000000") + "0000000000000111"; + targ_addr_ctrl_44 <= (dprio_chnl_id & "110000000000") + "0000000000001000"; + targ_addr_ctrl_45 <= (dprio_chnl_id & "110000000000") + "0000000000001001"; + targ_addr_ctrl_46 <= (dprio_chnl_id & "110000000000") + "0000000000001010"; + targ_addr_ctrl_47 <= (dprio_chnl_id & "110000000000") + "0000000000001011"; + targ_addr_ctrl_48 <= (dprio_chnl_id & "110000000000") + "0000000000001100"; + targ_addr_ctrl_49 <= (dprio_chnl_id & "110000000000") + "0000000000001101"; + targ_addr_ctrl_50 <= (dprio_chnl_id & "110000000000") + "0000000000001110"; + targ_addr_ctrl_51 <= (dprio_chnl_id & "110000000000") + "0000000000001111"; + targ_addr_ctrl_52 <= (dprio_chnl_id & "110000000000") + "0000000000010000"; + targ_addr_ctrl_53 <= (dprio_chnl_id & "110000000000") + "0000000000010001"; + + -- CRAM output assignment + -- TX PCS CRAMs + -- TX PCS Per channel control register 1 + rforce_kchar <= out_chnl_ctrl_1(15); + rforce_echar <= out_chnl_ctrl_1(14); + rtxfifo_dis <= out_chnl_ctrl_1(13); + rib_force_disp <= out_chnl_ctrl_1(12); + rtxfifo_lowlatency_en <= out_chnl_ctrl_1(11); + rdwidth_tx <= out_chnl_ctrl_1(10); + rge_xaui_tx <= out_chnl_ctrl_1(9); + rphfifopldentx <= out_chnl_ctrl_1(8); + rphfifoursttx <= out_chnl_ctrl_1(7); + rtxurstpcs <= out_chnl_ctrl_1(5); + rfreerun_tx <= out_chnl_ctrl_1(4); + rtxwrclksel <= out_chnl_ctrl_1(3); + rtxrdclksel <= out_chnl_ctrl_1(2); + rrev_loopbk <= out_chnl_ctrl_1(1); + rforce_disp <= out_chnl_ctrl_1(0); + -- TX PCS Per channel control register 2 + rendec_tx <= out_chnl_ctrl_2(15); + r8b10b_enc_ibm_en <= out_chnl_ctrl_2(14); + rcascaded_8b10b_en_tx <= out_chnl_ctrl_2(13); + rensymswap_tx <= out_chnl_ctrl_2(12); + renpolinv_tx <= out_chnl_ctrl_2(11); + renbitrev_tx <= out_chnl_ctrl_2(10); + rprbsen_tx <= out_chnl_ctrl_2(9); + rprbs_sel <= out_chnl_ctrl_2(8 DOWNTO 6); + rbisten_tx <= out_chnl_ctrl_2(5); + rbist_sel <= out_chnl_ctrl_2(4 DOWNTO 3); + rcxpat_chnl_en <= out_chnl_ctrl_2(2 DOWNTO 1); + rtxpcsbypass_en <= out_chnl_ctrl_2(0); + -- TX PCS Per channel control register 3 + rtx_pipe_enable <= out_chnl_ctrl_3(15); + rtx_idle_delay <= out_chnl_ctrl_3(14 DOWNTO 12); + rtxswing_sel_ena <= out_chnl_ctrl_3(11); + rtxpcsclkpwdn <= out_chnl_ctrl_3(10); + rcid_pattern_tx <= out_chnl_ctrl_3(9); + rcid_len_tx <= out_chnl_ctrl_3(8 DOWNTO 1); + + -- TX PCS Per channel control register 4 + rself_sw_en_tx <= out_chnl_ctrl_4(15); + rpipeline_bypass_tx <= out_chnl_ctrl_4(14); + rphfifo_regmode_tx <= out_chnl_ctrl_4(13); + rtxbitslip_en <= out_chnl_ctrl_4(12); + + -- RX PCS CRAMs + -- RX PCS Per channel control register 1 + rrxurstpcs <= out_chnl_ctrl_5(14); + rfreerun_rx <= out_chnl_ctrl_5(13); + rrcvd_clk_sel <= out_chnl_ctrl_5(12 DOWNTO 11); + rclk_1_sel <= out_chnl_ctrl_5(10 DOWNTO 9); + rclk_2_sel <= out_chnl_ctrl_5(8 DOWNTO 7); + rrx_rd_clk_sel <= out_chnl_ctrl_5(6); + rprbsen_rx <= out_chnl_ctrl_5(5); + rprbs_clr_rslt_rx <= out_chnl_ctrl_5(4); + rbisten_rx <= out_chnl_ctrl_5(3); + rbist_clr_rx <= out_chnl_ctrl_5(2); + rall_one_dect_only <= out_chnl_ctrl_5(1); + rrxpcsbypass_en <= out_chnl_ctrl_5(0); + -- RX PCS Per channel control register 2 + resync_badcg_en <= out_chnl_ctrl_6(15 DOWNTO 14); + rencdt_rising <= out_chnl_ctrl_6(13); + rdis_rx_disp <= out_chnl_ctrl_6(12); + rcomp_pat_porn <= out_chnl_ctrl_6(11); + rcomp_size <= out_chnl_ctrl_6(10 DOWNTO 8); + rcomp_pat(39 DOWNTO 32) <= out_chnl_ctrl_6(7 DOWNTO 0); + -- RX PCS Per channel control register 3 + rcomp_pat(31 DOWNTO 16) <= out_chnl_ctrl_7(15 DOWNTO 0); + -- RX PCS Per channel control register 4 + rcomp_pat(15 DOWNTO 0) <= out_chnl_ctrl_8(15 DOWNTO 0); + -- RX PCS Per channel control register 5 + rsync_sm_dis <= out_chnl_ctrl_9(15); + rib_inv_cd <= out_chnl_ctrl_9(14 DOWNTO 13); + renumber <= out_chnl_ctrl_9(12 DOWNTO 7); + rkchar <= out_chnl_ctrl_9(6); + rosbased <= out_chnl_ctrl_9(5); + rosnumber <= out_chnl_ctrl_9(4 DOWNTO 3); + rwa_6g_en <= out_chnl_ctrl_9(2); + rbysync_polinv_en <= out_chnl_ctrl_9(1); + rbitloc_rev_en <= out_chnl_ctrl_9(0); + -- RX PCS Per channel control register 6 + rgnumber <= out_chnl_ctrl_10(15 DOWNTO 8); + rknumber <= out_chnl_ctrl_10(7 DOWNTO 0); + -- RX PCS Per channel control register 7 + rrundisp <= out_chnl_ctrl_11(15 DOWNTO 10); + rbyte_rev_en <= out_chnl_ctrl_11(9); + rforce_sig_det_pcs <= out_chnl_ctrl_11(8); + rlp20ben <= out_chnl_ctrl_11(7); + rrlv_en <= out_chnl_ctrl_11(6); + rautobtalg_dis <= out_chnl_ctrl_11(5); + rendec_rx <= out_chnl_ctrl_11(4); + r8b10b_dec_ibm_en <= out_chnl_ctrl_11(3 DOWNTO 2); + rcascaded_8b10b_en_rx <= out_chnl_ctrl_11(1); + renpolinv_rx <= out_chnl_ctrl_11(0); + -- RX PCS Per channel control register 8 + rmatchen <= out_chnl_ctrl_12(15); + rgenericfifo <= out_chnl_ctrl_12(14); + rskpsetbased <= out_chnl_ctrl_12(13); + rtruebac2bac <= out_chnl_ctrl_12(12); + rclkcmpinsertpad <= out_chnl_ctrl_12(11); + rclkcmpsqmd <= out_chnl_ctrl_12(10); + rclkcmpsq1p(9 DOWNTO 0) <= out_chnl_ctrl_12(9 DOWNTO 0); + -- RX PCS Per channel control register 9 + rclkcmpsq1p(19 DOWNTO 10) <= out_chnl_ctrl_13(9 DOWNTO 0); + rclkcmpsq1n(19 DOWNTO 15) <= out_chnl_ctrl_13(15 DOWNTO 11); + -- RX PCS Per channel control register 10 + rclkcmpsq1n(14 DOWNTO 10) <= out_chnl_ctrl_14(15 DOWNTO 11); + rclkcmpsq1n(9 DOWNTO 0) <= out_chnl_ctrl_14(9 DOWNTO 0); + -- RX PCS Per channel control register 11 + rclkcmp_pipe_en <= out_chnl_ctrl_15(15); + rins_threshold <= out_chnl_ctrl_15(14 DOWNTO 10); + rdel_threshold <= out_chnl_ctrl_15(9 DOWNTO 5); + rfull_threshold <= out_chnl_ctrl_15(4 DOWNTO 0); + -- RX PCS Per channel control register 12 + rempty_threshold <= out_chnl_ctrl_16(15 DOWNTO 13); + rstart_threshold <= out_chnl_ctrl_16(12 DOWNTO 10); + rpma_done_count(17 DOWNTO 16) <= out_chnl_ctrl_16(5 DOWNTO 4); + rpma_done_gen_ena <= out_chnl_ctrl_16(3); + rhip_ena <= out_chnl_ctrl_16(2); + rauto_speed_ena <= out_chnl_ctrl_16(1); + rfreq_sel <= out_chnl_ctrl_16(0); + -- RX PCS Per channel control register 13 + rrxfifo_dis <= out_chnl_ctrl_17(15); + rrxfifo_lowlatency_en <= out_chnl_ctrl_17(14); + rdwidth_rx <= out_chnl_ctrl_17(13); + rphfifourstrx <= out_chnl_ctrl_17(12); + rcmpfifourst <= out_chnl_ctrl_17(11); + rinvalid_code_err_only <= out_chnl_ctrl_17(10); + rbytord_2sym_en <= out_chnl_ctrl_17(9); + rbyteorden <= out_chnl_ctrl_17(8 DOWNTO 7); + rbytordplden <= out_chnl_ctrl_17(6); + rphfifopldenrx <= out_chnl_ctrl_17(5); + rautoinsdis <= out_chnl_ctrl_17(4); + rtest_bus_sel(3 DOWNTO 0) <= out_chnl_ctrl_17(3 DOWNTO 0); + -- RX PCS Per channel control register 14 + rbytordpat(9 DOWNTO 0) <= out_chnl_ctrl_18(9 DOWNTO 0); + -- RX PCS Per channel control register 15 + rbytordpad <= out_chnl_ctrl_19(9 DOWNTO 0); + -- RX PCS Per channel control register 16 + rrx_pipe_enable <= out_chnl_ctrl_20(15); + rrx_detect_bypass <= out_chnl_ctrl_20(14); + rind_error_reporting <= out_chnl_ctrl_20(13); + rphystatus_delay <= out_chnl_ctrl_20(12 DOWNTO 10); + reidleinferenable <= out_chnl_ctrl_20(9); + rk285detect <= out_chnl_ctrl_20(8); + reidle_com_detect <= out_chnl_ctrl_20(7 DOWNTO 6); + rphystatus_rst_toggle <= out_chnl_ctrl_20(5); + rload_shreg_del <= out_chnl_ctrl_20(4 DOWNTO 0); + -- RX PCS Per channel control register 17 + rpma_done_count(15 DOWNTO 0) <= out_chnl_ctrl_21(15 DOWNTO 0); + -- RX PCS Per channel control register 18 + rrxpcsclkpwdn <= out_chnl_ctrl_22(14); + rcdr_ctrl_en <= out_chnl_ctrl_22(13); + rbytord_s2gx <= out_chnl_ctrl_22(11); + rbytord_6g_mask_en <= out_chnl_ctrl_22(10); + rbytordpat(19 DOWNTO 10) <= out_chnl_ctrl_22(9 DOWNTO 0); + -- RX PCS Per channel control register 19 + rwait_count(7 DOWNTO 0) <= out_chnl_ctrl_23(7 DOWNTO 0); + -- RX PCS Per channel control register 20 + rwait_for_phfifo_cnt(3 DOWNTO 0) <= out_chnl_ctrl_24(13 DOWNTO 10); + rfts_count(9 DOWNTO 0) <= out_chnl_ctrl_24(9 DOWNTO 0); + -- RX PCS Per channel control register 21 + rcid_pattern_rx <= out_chnl_ctrl_25(9); + rcid_len_rx(7 DOWNTO 0) <= out_chnl_ctrl_25(8 DOWNTO 1); + rppm_meas_delay <= out_chnl_ctrl_25(0); + -- RX PCS Per channel control register 22 + rphfifo_regmode_rx <= out_chnl_ctrl_26(15); + rcid_en <= out_chnl_ctrl_26(14); + rrxvalid_mask <= out_chnl_ctrl_26(13); + rself_sw_en_rx <= out_chnl_ctrl_26(12); + rpipeline_bypass_rx <= out_chnl_ctrl_26(11); + rauto_deassert_pc_rst_cnt(3 DOWNTO 0) <= out_chnl_ctrl_26(9 DOWNTO 6); + rauto_pc_en_cnt(4 DOWNTO 0) <= out_chnl_ctrl_26(4 DOWNTO 0); + -- RX PCS Per channel control register 23 + riei_eios_priority_dis <= out_chnl_ctrl_27(11); + rgen1_sigdet_ena <= out_chnl_ctrl_27(10); + rmask_count(9 DOWNTO 0) <= out_chnl_ctrl_27(9 DOWNTO 0); + + --End PCS CRAMs + + -- TX PMA CRAMs + -- TX PMA Per channel control register 1 + rvod_sel_non_pcie(2 DOWNTO 0) <= out_chnl_ctrl_28(15 DOWNTO 13); + rvod_sela(2 DOWNTO 0) <= out_chnl_ctrl_28(12 DOWNTO 10); + rvod_selb(2 DOWNTO 0) <= out_chnl_ctrl_28(9 DOWNTO 7); + rvod_selc(2 DOWNTO 0) <= out_chnl_ctrl_28(6 DOWNTO 4); + rvod_seld(2 DOWNTO 0) <= out_chnl_ctrl_28(3 DOWNTO 1); + rpowdnt <= out_chnl_ctrl_28(0); + -- TX PMA Per channel control register 2 + rpre_em_1t_no_pcie(4 DOWNTO 0) <= out_chnl_ctrl_29(15 DOWNTO 11); + rpre_em_1t_a(4 DOWNTO 0) <= out_chnl_ctrl_29(10 DOWNTO 6); + rpre_em_1t_b(4 DOWNTO 0) <= out_chnl_ctrl_29(5 DOWNTO 1); + -- TX PMA Per channel control register 3 + rpre_em_1t_c(4 DOWNTO 0) <= out_chnl_ctrl_30(12 DOWNTO 8); + rpre_em_2t(3 DOWNTO 0) <= out_chnl_ctrl_30(7 DOWNTO 4); + rpre_em_pt(3 DOWNTO 0) <= out_chnl_ctrl_30(3 DOWNTO 0); + -- TX PMA Per channel control register 4 + rtx_term_sel(2 DOWNTO 0) <= out_chnl_ctrl_31(15 DOWNTO 13); + rtx_vtt(1 DOWNTO 0) <= out_chnl_ctrl_31(12 DOWNTO 11); + rtx_lst(3 DOWNTO 0) <= out_chnl_ctrl_31(10 DOWNTO 7); + rslew(1 DOWNTO 0) <= out_chnl_ctrl_31(6 DOWNTO 5); + rsig_inv_ptap <= out_chnl_ctrl_31(4); + rsig_inv_2t <= out_chnl_ctrl_31(3); + rrx_det(1 DOWNTO 0) <= out_chnl_ctrl_31(2 DOWNTO 1); + rlowv <= out_chnl_ctrl_31(0); + -- TX PMA Per channel control register 5 + r_dft_sel(2 DOWNTO 0) <= out_chnl_ctrl_32(15 DOWNTO 13); + rtx_ob_pdb <= out_chnl_ctrl_32(11); + -- TX PMA Per channel control register 6 + rcgb_x_en(1 DOWNTO 0) <= out_chnl_ctrl_33(15 DOWNTO 14); + rcgb_cmu_sel <= out_chnl_ctrl_33(13); + rcgb_m_sel(1 DOWNTO 0) <= out_chnl_ctrl_33(12 DOWNTO 11); + rpma_doublewidth_tx <= out_chnl_ctrl_33(10); + rpmadwidth_tx <= out_chnl_ctrl_33(9); + rcgb_delay_sel <= out_chnl_ctrl_33(8); + rs_lpbk <= out_chnl_ctrl_33(7); + rdynamic_sw <= out_chnl_ctrl_33(6); + rpclksel <= out_chnl_ctrl_33(5); + rtx_cgb_pdb <= out_chnl_ctrl_33(4); + -- TX PMA Per channel control register 7 + riqclk_sel(1 DOWNTO 0) <= out_chnl_ctrl_34(15 DOWNTO 14); + rrefclk_sel(1 DOWNTO 0) <= out_chnl_ctrl_34(13 DOWNTO 12); + rvcobypass <= out_chnl_ctrl_34(11); + rrevlb_sw <= out_chnl_ctrl_34(10); + rimpctrl <= out_chnl_ctrl_34(5); + rrx_refclk <= out_chnl_ctrl_34(4); + rpcs_sd_sel <= out_chnl_ctrl_34(3); + -- TX PMA Per channel control register 8 + rpma_reserved(31 DOWNTO 16) <= out_chnl_ctrl_35(15 DOWNTO 0); + + --RX PMA CRAMs + -- RX PMA Per channel control register 1 + rrx_lst(4 DOWNTO 0) <= out_chnl_ctrl_36(15 DOWNTO 11); + rrx_bit_dc(3 DOWNTO 0) <= out_chnl_ctrl_36(10 DOWNTO 7); + rrx_s_rdlpbk <= out_chnl_ctrl_36(6); + rrx_vtt(2 DOWNTO 0) <= out_chnl_ctrl_36(5 DOWNTO 3); + rrx_term_sel(2 DOWNTO 0) <= out_chnl_ctrl_36(2 DOWNTO 0); + -- RX PMA Per channel control register 2 + rrx_sdlv(3 DOWNTO 0) <= out_chnl_ctrl_37(15 DOWNTO 12); + rrx_oc_en <= out_chnl_ctrl_37(11); + rrx_oc(7 DOWNTO 0) <= out_chnl_ctrl_37(10 DOWNTO 3); + rrx_sd_force <= out_chnl_ctrl_37(2); + rrx_test <= out_chnl_ctrl_37(1); + rrxurstpma <= out_chnl_ctrl_37(0); + -- RX PMA Per channel control register 3 + rrx_sd_on(3 DOWNTO 0) <= out_chnl_ctrl_38(15 DOWNTO 12); + rrx_sd_off(4 DOWNTO 0) <= out_chnl_ctrl_38(11 DOWNTO 7); + rrx_oc_calpd <= out_chnl_ctrl_38(6); + rurx_pdb <= out_chnl_ctrl_38(5); + rrx_ib_pdb <= out_chnl_ctrl_38(4); + rpowdnr <= out_chnl_ctrl_38(3); + -- RX PMA Per channel control register 4 + rcru_div2 <= out_chnl_ctrl_39(15); + rcru_m_sel(1 DOWNTO 0) <= out_chnl_ctrl_39(14 DOWNTO 13); + rcru_m(3 DOWNTO 0) <= out_chnl_ctrl_39(12 DOWNTO 9); + rcru_l(1 DOWNTO 0) <= out_chnl_ctrl_39(8 DOWNTO 7); + rcru_ctl0 <= out_chnl_ctrl_39(6); + rcru_crplctrl(1 DOWNTO 0) <= out_chnl_ctrl_39(5 DOWNTO 4); + rcru_pfdbwctrl(1 DOWNTO 0) <= out_chnl_ctrl_39(3 DOWNTO 2); + rcru_pdbwctrl(1 DOWNTO 0) <= out_chnl_ctrl_39(1 DOWNTO 0); + -- RX PMA Per channel control register 5 + rcru_rlbk <= out_chnl_ctrl_40(15); + rcru_lst(3 DOWNTO 0) <= out_chnl_ctrl_40(14 DOWNTO 11); + rcru_testen <= out_chnl_ctrl_40(10); + rcru_testupen <= out_chnl_ctrl_40(9); + rcru_testdnen <= out_chnl_ctrl_40(8); + rcru_isel(2 DOWNTO 0) <= out_chnl_ctrl_40(7 DOWNTO 5); + rcru_iselpd(2 DOWNTO 0) <= out_chnl_ctrl_40(4 DOWNTO 2); + -- RX PMA Per channel control register 6 + rcp_mode <= out_chnl_ctrl_41(15); + rltd <= out_chnl_ctrl_41(14); + rltr <= out_chnl_ctrl_41(13); + rrx_cru_pdb <= out_chnl_ctrl_41(12); + rrx_cru_rst <= out_chnl_ctrl_41(11); + rcru_cmu_mode <= out_chnl_ctrl_41(10); + rcru_ignore_phslck <= out_chnl_ctrl_41(9); + rcru_sd_sel <= out_chnl_ctrl_41(7); + rcru_pdfl <= out_chnl_ctrl_41(6); + rcru_pdof_test(2 DOWNTO 0) <= out_chnl_ctrl_41(5 DOWNTO 3); + rcru_rgla_isel(2 DOWNTO 0) <= out_chnl_ctrl_41(2 DOWNTO 0); + -- RX PMA Per channel control register 7 + rcru_pdof_0i(3 DOWNTO 0) <= out_chnl_ctrl_42(15 DOWNTO 12); + rcru_pdof_90i(3 DOWNTO 0) <= out_chnl_ctrl_42(11 DOWNTO 8); + rcru_pdof_180i(3 DOWNTO 0) <= out_chnl_ctrl_42(7 DOWNTO 4); + rcru_pdof_270i(3 DOWNTO 0) <= out_chnl_ctrl_42(3 DOWNTO 0); + -- RX PMA Per channel control register 8 + --reye_monitor(7 DOWNTO 0) =out_chnl_ctrl_43[7:0]; + -- RX PMA Per channel control register 9 + rpma_reserved(15 DOWNTO 0) <= out_chnl_ctrl_44(15 DOWNTO 0); + -- RX PMA Per channel control register 10 + rpma_doublewidth_rx <= out_chnl_ctrl_45(15); + rpmadwidth_rx <= out_chnl_ctrl_45(14); + rtest_fastsd <= out_chnl_ctrl_45(13); + rfastsd(3 DOWNTO 0) <= out_chnl_ctrl_45(12 DOWNTO 9); + rppmsel(5 DOWNTO 0) <= out_chnl_ctrl_45(8 DOWNTO 3); + rforce0_freqdet <= out_chnl_ctrl_45(2); + rforce1_freqdet <= out_chnl_ctrl_45(1); + rppm_cnt_reset <= out_chnl_ctrl_45(0); + -- RX PMA Per channel control register 11 + r_dfe_1t(2 DOWNTO 0) <= out_chnl_ctrl_46(15 DOWNTO 13); + r_dfe_2t(2 DOWNTO 0) <= out_chnl_ctrl_46(12 DOWNTO 10); + rppm_post_eidle_del <= out_chnl_ctrl_46(9); + rppm_gen1_2xcnt_en <= out_chnl_ctrl_46(8); + -- RX PMA Per channel control register 12 + reqa_set <= out_chnl_ctrl_47(14 DOWNTO 12); + reqb_set <= out_chnl_ctrl_47(11 DOWNTO 9); + reqc_set <= out_chnl_ctrl_47(8 DOWNTO 6); + reqd_set <= out_chnl_ctrl_47(5 DOWNTO 3); + reqv_set <= out_chnl_ctrl_47(2 DOWNTO 0); + -- RX PMA Per channel control register 13 + rlock_lf_ovd <= out_chnl_ctrl_48(15); + rseq_sel(1 DOWNTO 0) <= out_chnl_ctrl_48(14 DOWNTO 13); + radce_adapt <= out_chnl_ctrl_48(12); + rrgen_set(2 DOWNTO 0) <= out_chnl_ctrl_48(11 DOWNTO 9); + rclkdiv(3 DOWNTO 0) <= out_chnl_ctrl_48(8 DOWNTO 5); + rhyst_lf(2 DOWNTO 0) <= out_chnl_ctrl_48(4 DOWNTO 2); + rdc_freq(1 DOWNTO 0) <= out_chnl_ctrl_48(1 DOWNTO 0); + -- RX PMA Per channel control register 14 + rhyst_hf(2 DOWNTO 0) <= out_chnl_ctrl_49(15 DOWNTO 13); + rf_lpf(1 DOWNTO 0) <= out_chnl_ctrl_49(6 DOWNTO 5); + rf_hpf(1 DOWNTO 0) <= out_chnl_ctrl_49(4 DOWNTO 3); + rrgen_vod(2 DOWNTO 0) <= out_chnl_ctrl_49(2 DOWNTO 0); + -- RX PMA Per channel control register 15 + rrgen_bw(1 DOWNTO 0) <= out_chnl_ctrl_50(15 DOWNTO 14); + rrect_adj(1 DOWNTO 0) <= out_chnl_ctrl_50(13 DOWNTO 12); + rd2a_res(1 DOWNTO 0) <= out_chnl_ctrl_50(11 DOWNTO 10); + rlf_os(3 DOWNTO 0) <= out_chnl_ctrl_50(9 DOWNTO 6); + rhf_os(3 DOWNTO 0) <= out_chnl_ctrl_50(5 DOWNTO 2); + radce_rst <= out_chnl_ctrl_50(1); + radce_pdb <= out_chnl_ctrl_50(0); + -- RX PMA Per channel control register 16 + radce_hflck(14 DOWNTO 0) <= out_chnl_ctrl_51(14 DOWNTO 0); + -- RX PMA Per channel control register 16 + radce_lflck(14 DOWNTO 0) <= out_chnl_ctrl_52(14 DOWNTO 0); + -- RX PMA Per channel control register 18 + radce_digital <= out_chnl_ctrl_53(9 DOWNTO 0); + + + + reg_chnl_inst : cycloneiv_hssi_cmu_dprio_reg_chnl + PORT MAP ( + mdio_rst => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + mdc => mdc, + mbus_in => mbus_in, + serial_mode => serial_mode, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + ser_shift_load => ser_shift_load, + si => si, + -- CSR input + ext_chnl_ctrl_1 => csr_chnl_in(15 DOWNTO 0), + ext_chnl_ctrl_2 => csr_chnl_in(31 DOWNTO 16), + ext_chnl_ctrl_3 => csr_chnl_in(47 DOWNTO 32), + ext_chnl_ctrl_4 => csr_chnl_in(63 DOWNTO 48), + ext_chnl_ctrl_5 => csr_chnl_in(79 DOWNTO 64), + ext_chnl_ctrl_6 => csr_chnl_in(95 DOWNTO 80), + ext_chnl_ctrl_7 => csr_chnl_in(111 DOWNTO 96), + ext_chnl_ctrl_8 => csr_chnl_in(127 DOWNTO 112), + ext_chnl_ctrl_9 => csr_chnl_in(143 DOWNTO 128), + ext_chnl_ctrl_10 => csr_chnl_in(159 DOWNTO 144), + ext_chnl_ctrl_11 => csr_chnl_in(175 DOWNTO 160), + ext_chnl_ctrl_12 => csr_chnl_in(191 DOWNTO 176), + ext_chnl_ctrl_13 => csr_chnl_in(207 DOWNTO 192), + ext_chnl_ctrl_14 => csr_chnl_in(223 DOWNTO 208), + ext_chnl_ctrl_15 => csr_chnl_in(239 DOWNTO 224), + ext_chnl_ctrl_16 => csr_chnl_in(255 DOWNTO 240), + ext_chnl_ctrl_17 => csr_chnl_in(271 DOWNTO 256), + ext_chnl_ctrl_18 => csr_chnl_in(287 DOWNTO 272), + ext_chnl_ctrl_19 => csr_chnl_in(303 DOWNTO 288), + ext_chnl_ctrl_20 => csr_chnl_in(319 DOWNTO 304), + ext_chnl_ctrl_21 => csr_chnl_in(335 DOWNTO 320), + ext_chnl_ctrl_22 => csr_chnl_in(351 DOWNTO 336), + ext_chnl_ctrl_23 => csr_chnl_in(367 DOWNTO 352), + ext_chnl_ctrl_24 => csr_chnl_in(383 DOWNTO 368), + ext_chnl_ctrl_25 => csr_chnl_in(399 DOWNTO 384), + ext_chnl_ctrl_26 => csr_chnl_in(415 DOWNTO 400), + ext_chnl_ctrl_27 => csr_chnl_in(431 DOWNTO 416), + ext_chnl_ctrl_28 => csr_chnl_in(447 DOWNTO 432), + ext_chnl_ctrl_29 => csr_chnl_in(463 DOWNTO 448), + ext_chnl_ctrl_30 => csr_chnl_in(479 DOWNTO 464), + ext_chnl_ctrl_31 => csr_chnl_in(495 DOWNTO 480), + ext_chnl_ctrl_32 => csr_chnl_in(511 DOWNTO 496), + ext_chnl_ctrl_33 => csr_chnl_in(527 DOWNTO 512), + ext_chnl_ctrl_34 => csr_chnl_in(543 DOWNTO 528), + ext_chnl_ctrl_35 => csr_chnl_in(559 DOWNTO 544), + ext_chnl_ctrl_36 => csr_chnl_in(575 DOWNTO 560), + ext_chnl_ctrl_37 => csr_chnl_in(591 DOWNTO 576), + ext_chnl_ctrl_38 => csr_chnl_in(607 DOWNTO 592), + ext_chnl_ctrl_39 => csr_chnl_in(623 DOWNTO 608), + ext_chnl_ctrl_40 => csr_chnl_in(639 DOWNTO 624), + ext_chnl_ctrl_41 => csr_chnl_in(655 DOWNTO 640), + ext_chnl_ctrl_42 => csr_chnl_in(671 DOWNTO 656), + ext_chnl_ctrl_43 => csr_chnl_in_reserved(15 DOWNTO 0), + ext_chnl_ctrl_44 => csr_chnl_in(687 DOWNTO 672), + ext_chnl_ctrl_45 => csr_chnl_in(703 DOWNTO 688), + ext_chnl_ctrl_46 => csr_chnl_in(719 DOWNTO 704), + ext_chnl_ctrl_47 => csr_chnl_in(735 DOWNTO 720), + ext_chnl_ctrl_48 => csr_chnl_in(751 DOWNTO 736), + ext_chnl_ctrl_49 => csr_chnl_in(767 DOWNTO 752), + ext_chnl_ctrl_50 => csr_chnl_in(783 DOWNTO 768), + ext_chnl_ctrl_51 => csr_chnl_in(799 DOWNTO 784), + ext_chnl_ctrl_52 => csr_chnl_in(815 DOWNTO 800), + ext_chnl_ctrl_53 => csr_chnl_in(831 DOWNTO 816), + targ_addr_ctrl_1 => targ_addr_ctrl_1, + targ_addr_ctrl_2 => targ_addr_ctrl_2, + targ_addr_ctrl_3 => targ_addr_ctrl_3, + targ_addr_ctrl_4 => targ_addr_ctrl_4, + targ_addr_ctrl_5 => targ_addr_ctrl_5, + targ_addr_ctrl_6 => targ_addr_ctrl_6, + targ_addr_ctrl_7 => targ_addr_ctrl_7, + targ_addr_ctrl_8 => targ_addr_ctrl_8, + targ_addr_ctrl_9 => targ_addr_ctrl_9, + targ_addr_ctrl_10 => targ_addr_ctrl_10, + targ_addr_ctrl_11 => targ_addr_ctrl_11, + targ_addr_ctrl_12 => targ_addr_ctrl_12, + targ_addr_ctrl_13 => targ_addr_ctrl_13, + targ_addr_ctrl_14 => targ_addr_ctrl_14, + targ_addr_ctrl_15 => targ_addr_ctrl_15, + targ_addr_ctrl_16 => targ_addr_ctrl_16, + targ_addr_ctrl_17 => targ_addr_ctrl_17, + targ_addr_ctrl_18 => targ_addr_ctrl_18, + targ_addr_ctrl_19 => targ_addr_ctrl_19, + targ_addr_ctrl_20 => targ_addr_ctrl_20, + targ_addr_ctrl_21 => targ_addr_ctrl_21, + targ_addr_ctrl_22 => targ_addr_ctrl_22, + targ_addr_ctrl_23 => targ_addr_ctrl_23, + targ_addr_ctrl_24 => targ_addr_ctrl_24, + targ_addr_ctrl_25 => targ_addr_ctrl_25, + targ_addr_ctrl_26 => targ_addr_ctrl_26, + targ_addr_ctrl_27 => targ_addr_ctrl_27, + targ_addr_ctrl_28 => targ_addr_ctrl_28, + targ_addr_ctrl_29 => targ_addr_ctrl_29, + targ_addr_ctrl_30 => targ_addr_ctrl_30, + targ_addr_ctrl_31 => targ_addr_ctrl_31, + targ_addr_ctrl_32 => targ_addr_ctrl_32, + targ_addr_ctrl_33 => targ_addr_ctrl_33, + targ_addr_ctrl_34 => targ_addr_ctrl_34, + targ_addr_ctrl_35 => targ_addr_ctrl_35, + targ_addr_ctrl_36 => targ_addr_ctrl_36, + targ_addr_ctrl_37 => targ_addr_ctrl_37, + targ_addr_ctrl_38 => targ_addr_ctrl_38, + targ_addr_ctrl_39 => targ_addr_ctrl_39, + targ_addr_ctrl_40 => targ_addr_ctrl_40, + targ_addr_ctrl_41 => targ_addr_ctrl_41, + targ_addr_ctrl_42 => targ_addr_ctrl_42, + targ_addr_ctrl_43 => targ_addr_ctrl_43, + targ_addr_ctrl_44 => targ_addr_ctrl_44, + targ_addr_ctrl_45 => targ_addr_ctrl_45, + targ_addr_ctrl_46 => targ_addr_ctrl_46, + targ_addr_ctrl_47 => targ_addr_ctrl_47, + targ_addr_ctrl_48 => targ_addr_ctrl_48, + targ_addr_ctrl_49 => targ_addr_ctrl_49, + targ_addr_ctrl_50 => targ_addr_ctrl_50, + targ_addr_ctrl_51 => targ_addr_ctrl_51, + targ_addr_ctrl_52 => targ_addr_ctrl_52, + targ_addr_ctrl_53 => targ_addr_ctrl_53, + -- DPRIO register output + out_chnl_ctrl_1 => out_chnl_ctrl_1, + out_chnl_ctrl_2 => out_chnl_ctrl_2, + out_chnl_ctrl_3 => out_chnl_ctrl_3, + out_chnl_ctrl_4 => out_chnl_ctrl_4, + out_chnl_ctrl_5 => out_chnl_ctrl_5, + out_chnl_ctrl_6 => out_chnl_ctrl_6, + out_chnl_ctrl_7 => out_chnl_ctrl_7, + out_chnl_ctrl_8 => out_chnl_ctrl_8, + out_chnl_ctrl_9 => out_chnl_ctrl_9, + out_chnl_ctrl_10 => out_chnl_ctrl_10, + out_chnl_ctrl_11 => out_chnl_ctrl_11, + out_chnl_ctrl_12 => out_chnl_ctrl_12, + out_chnl_ctrl_13 => out_chnl_ctrl_13, + out_chnl_ctrl_14 => out_chnl_ctrl_14, + out_chnl_ctrl_15 => out_chnl_ctrl_15, + out_chnl_ctrl_16 => out_chnl_ctrl_16, + out_chnl_ctrl_17 => out_chnl_ctrl_17, + out_chnl_ctrl_18 => out_chnl_ctrl_18, + out_chnl_ctrl_19 => out_chnl_ctrl_19, + out_chnl_ctrl_20 => out_chnl_ctrl_20, + out_chnl_ctrl_21 => out_chnl_ctrl_21, + out_chnl_ctrl_22 => out_chnl_ctrl_22, + out_chnl_ctrl_23 => out_chnl_ctrl_23, + out_chnl_ctrl_24 => out_chnl_ctrl_24, + out_chnl_ctrl_25 => out_chnl_ctrl_25, + out_chnl_ctrl_26 => out_chnl_ctrl_26, + out_chnl_ctrl_27 => out_chnl_ctrl_27, + out_chnl_ctrl_28 => out_chnl_ctrl_28, + out_chnl_ctrl_29 => out_chnl_ctrl_29, + out_chnl_ctrl_30 => out_chnl_ctrl_30, + out_chnl_ctrl_31 => out_chnl_ctrl_31, + out_chnl_ctrl_32 => out_chnl_ctrl_32, + out_chnl_ctrl_33 => out_chnl_ctrl_33, + out_chnl_ctrl_34 => out_chnl_ctrl_34, + out_chnl_ctrl_35 => out_chnl_ctrl_35, + out_chnl_ctrl_36 => out_chnl_ctrl_36, + out_chnl_ctrl_37 => out_chnl_ctrl_37, + out_chnl_ctrl_38 => out_chnl_ctrl_38, + out_chnl_ctrl_39 => out_chnl_ctrl_39, + out_chnl_ctrl_40 => out_chnl_ctrl_40, + out_chnl_ctrl_41 => out_chnl_ctrl_41, + out_chnl_ctrl_42 => out_chnl_ctrl_42, + out_chnl_ctrl_43 => out_chnl_ctrl_43, + out_chnl_ctrl_44 => out_chnl_ctrl_44, + out_chnl_ctrl_45 => out_chnl_ctrl_45, + out_chnl_ctrl_46 => out_chnl_ctrl_46, + out_chnl_ctrl_47 => out_chnl_ctrl_47, + out_chnl_ctrl_48 => out_chnl_ctrl_48, + out_chnl_ctrl_49 => out_chnl_ctrl_49, + out_chnl_ctrl_50 => out_chnl_ctrl_50, + out_chnl_ctrl_51 => out_chnl_ctrl_51, + out_chnl_ctrl_52 => out_chnl_ctrl_52, + out_chnl_ctrl_53 => out_chnl_ctrl_53, + + so => so_xhdl54 + ); + + -- MBUS_OUT muxing + + + mbus_mux : cycloneiv_hssi_cmu_dprio_chnl_bus_out_mux + PORT MAP ( + chnl_ctrl_in1 => out_chnl_ctrl_1, + chnl_ctrl_in2 => out_chnl_ctrl_2, + chnl_ctrl_in3 => out_chnl_ctrl_3, + chnl_ctrl_in4 => out_chnl_ctrl_4, + chnl_ctrl_in5 => out_chnl_ctrl_5, + chnl_ctrl_in6 => out_chnl_ctrl_6, + chnl_ctrl_in7 => out_chnl_ctrl_7, + chnl_ctrl_in8 => out_chnl_ctrl_8, + chnl_ctrl_in9 => out_chnl_ctrl_9, + chnl_ctrl_in10 => out_chnl_ctrl_10, + chnl_ctrl_in11 => out_chnl_ctrl_11, + chnl_ctrl_in12 => out_chnl_ctrl_12, + chnl_ctrl_in13 => out_chnl_ctrl_13, + chnl_ctrl_in14 => out_chnl_ctrl_14, + chnl_ctrl_in15 => out_chnl_ctrl_15, + chnl_ctrl_in16 => out_chnl_ctrl_16, + chnl_ctrl_in17 => out_chnl_ctrl_17, + chnl_ctrl_in18 => out_chnl_ctrl_18, + chnl_ctrl_in19 => out_chnl_ctrl_19, + chnl_ctrl_in20 => out_chnl_ctrl_20, + chnl_ctrl_in21 => out_chnl_ctrl_21, + chnl_ctrl_in22 => out_chnl_ctrl_22, + chnl_ctrl_in23 => out_chnl_ctrl_23, + chnl_ctrl_in24 => out_chnl_ctrl_24, + chnl_ctrl_in25 => out_chnl_ctrl_25, + chnl_ctrl_in26 => out_chnl_ctrl_26, + chnl_ctrl_in27 => out_chnl_ctrl_27, + chnl_ctrl_in28 => out_chnl_ctrl_28, + chnl_ctrl_in29 => out_chnl_ctrl_29, + chnl_ctrl_in30 => out_chnl_ctrl_30, + chnl_ctrl_in31 => out_chnl_ctrl_31, + chnl_ctrl_in32 => out_chnl_ctrl_32, + chnl_ctrl_in33 => out_chnl_ctrl_33, + chnl_ctrl_in34 => out_chnl_ctrl_34, + chnl_ctrl_in35 => out_chnl_ctrl_35, + chnl_ctrl_in36 => out_chnl_ctrl_36, + chnl_ctrl_in37 => out_chnl_ctrl_37, + chnl_ctrl_in38 => out_chnl_ctrl_38, + chnl_ctrl_in39 => out_chnl_ctrl_39, + chnl_ctrl_in40 => out_chnl_ctrl_40, + chnl_ctrl_in41 => out_chnl_ctrl_41, + chnl_ctrl_in42 => out_chnl_ctrl_42, + chnl_ctrl_in43 => out_chnl_ctrl_43, + chnl_ctrl_in44 => out_chnl_ctrl_44, + chnl_ctrl_in45 => out_chnl_ctrl_45, + chnl_ctrl_in46 => out_chnl_ctrl_46, + chnl_ctrl_in47 => out_chnl_ctrl_47, + chnl_ctrl_in48 => out_chnl_ctrl_48, + chnl_ctrl_in49 => out_chnl_ctrl_49, + chnl_ctrl_in50 => out_chnl_ctrl_50, + chnl_ctrl_in51 => out_chnl_ctrl_51, + chnl_ctrl_in52 => out_chnl_ctrl_52, + chnl_ctrl_in53 => out_chnl_ctrl_53, + hw_address_ctrl_in1 => targ_addr_ctrl_1, + hw_address_ctrl_in2 => targ_addr_ctrl_2, + hw_address_ctrl_in3 => targ_addr_ctrl_3, + hw_address_ctrl_in4 => targ_addr_ctrl_4, + hw_address_ctrl_in5 => targ_addr_ctrl_5, + hw_address_ctrl_in6 => targ_addr_ctrl_6, + hw_address_ctrl_in7 => targ_addr_ctrl_7, + hw_address_ctrl_in8 => targ_addr_ctrl_8, + hw_address_ctrl_in9 => targ_addr_ctrl_9, + hw_address_ctrl_in10 => targ_addr_ctrl_10, + hw_address_ctrl_in11 => targ_addr_ctrl_11, + hw_address_ctrl_in12 => targ_addr_ctrl_12, + hw_address_ctrl_in13 => targ_addr_ctrl_13, + hw_address_ctrl_in14 => targ_addr_ctrl_14, + hw_address_ctrl_in15 => targ_addr_ctrl_15, + hw_address_ctrl_in16 => targ_addr_ctrl_16, + hw_address_ctrl_in17 => targ_addr_ctrl_17, + hw_address_ctrl_in18 => targ_addr_ctrl_18, + hw_address_ctrl_in19 => targ_addr_ctrl_19, + hw_address_ctrl_in20 => targ_addr_ctrl_20, + hw_address_ctrl_in21 => targ_addr_ctrl_21, + hw_address_ctrl_in22 => targ_addr_ctrl_22, + hw_address_ctrl_in23 => targ_addr_ctrl_23, + hw_address_ctrl_in24 => targ_addr_ctrl_24, + hw_address_ctrl_in25 => targ_addr_ctrl_25, + hw_address_ctrl_in26 => targ_addr_ctrl_26, + hw_address_ctrl_in27 => targ_addr_ctrl_27, + hw_address_ctrl_in28 => targ_addr_ctrl_28, + hw_address_ctrl_in29 => targ_addr_ctrl_29, + hw_address_ctrl_in30 => targ_addr_ctrl_30, + hw_address_ctrl_in31 => targ_addr_ctrl_31, + hw_address_ctrl_in32 => targ_addr_ctrl_32, + hw_address_ctrl_in33 => targ_addr_ctrl_33, + hw_address_ctrl_in34 => targ_addr_ctrl_34, + hw_address_ctrl_in35 => targ_addr_ctrl_35, + hw_address_ctrl_in36 => targ_addr_ctrl_36, + hw_address_ctrl_in37 => targ_addr_ctrl_37, + hw_address_ctrl_in38 => targ_addr_ctrl_38, + hw_address_ctrl_in39 => targ_addr_ctrl_39, + hw_address_ctrl_in40 => targ_addr_ctrl_40, + hw_address_ctrl_in41 => targ_addr_ctrl_41, + hw_address_ctrl_in42 => targ_addr_ctrl_42, + hw_address_ctrl_in43 => targ_addr_ctrl_43, + hw_address_ctrl_in44 => targ_addr_ctrl_44, + hw_address_ctrl_in45 => targ_addr_ctrl_45, + hw_address_ctrl_in46 => targ_addr_ctrl_46, + hw_address_ctrl_in47 => targ_addr_ctrl_47, + hw_address_ctrl_in48 => targ_addr_ctrl_48, + hw_address_ctrl_in49 => targ_addr_ctrl_49, + hw_address_ctrl_in50 => targ_addr_ctrl_50, + hw_address_ctrl_in51 => targ_addr_ctrl_51, + hw_address_ctrl_in52 => targ_addr_ctrl_52, + hw_address_ctrl_in53 => targ_addr_ctrl_53, + reg_addr => reg_addr, + chnl_ctrl_out => mbus_out_xhdl53 + ); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_status IS + GENERIC ( + + XGXS_STATUS1 : INTEGER := 24580; + XGXS_STATUS2 : INTEGER := 24581; + XGXS_LANE_STATUS : INTEGER := 24582 + ); + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_rd : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dev_addr_0 : IN STD_LOGIC; + mdc : IN STD_LOGIC; + serial_mode : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + mbus_out_ch0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_ch1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_ch2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_ch3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_centrl : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- Status inputs + align_status : IN STD_LOGIC; + sync_status : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + xs_link_status : IN STD_LOGIC; + rx_local_fault : IN STD_LOGIC; + tx_local_fault : IN STD_LOGIC; + -- Outputs + rxs_link_status_set : OUT STD_LOGIC; + rtx_rx_local_fault_clr : OUT STD_LOGIC; + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); +END cycloneiv_hssi_cmu_dprio_status; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_status IS + COMPONENT cycloneiv_hssi_cmu_dprio_bit + PORT ( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC; + ext_in : IN STD_LOGIC; + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + sig_out : OUT STD_LOGIC; + so : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL chain : STD_LOGIC; + SIGNAL xs_link_status_rd : STD_LOGIC; + SIGNAL tx_rx_local_fault_status_rd : STD_LOGIC; + SIGNAL local_fault : STD_LOGIC; + SIGNAL xs_tx_local_fault : STD_LOGIC; + SIGNAL xs_rx_local_fault : STD_LOGIC; + SIGNAL xgxs_stat1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL xgxs_stat2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL xgxs_lane_stat_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL rxs_link_status_set_xhdl1 : STD_LOGIC; + SIGNAL rtx_rx_local_fault_clr_xhdl0 : STD_LOGIC; + SIGNAL so_xhdl2 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + rxs_link_status_set <= rxs_link_status_set_xhdl1; + rtx_rx_local_fault_clr <= rtx_rx_local_fault_clr_xhdl0; + so <= so_xhdl2; + + -- Status register address parameters + + -- XGXS_STATUS1 and XGXS_STATUS2 status registers + xs_link_status_rd <= mdio_rd AND int2bit(reg_addr = ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR(XGXS_STATUS1, 16)); + tx_rx_local_fault_status_rd <= mdio_rd AND int2bit(reg_addr = ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR(XGXS_STATUS2, 16)); + + -- Status registers + local_fault <= tx_local_fault OR rx_local_fault; + xs_tx_local_fault <= tx_local_fault WHEN (dev_addr_0 = '1') ELSE + rx_local_fault; + xs_rx_local_fault <= rx_local_fault WHEN (dev_addr_0 = '1') ELSE + tx_local_fault; + + xgxs_stat1_reg <= ("00000000" & local_fault & "0000" & xs_link_status & "10"); + xgxs_stat2_reg <= ("1000" & xs_rx_local_fault & xs_tx_local_fault & "0000000000"); + xgxs_lane_stat_reg <= ("000" & align_status & "11000000" & sync_status); + + -- Single control bits + + + xs_link_status_set : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => mdio_rst, + clk => mdc, + sig_in => xs_link_status_rd, + ext_in => '0', + serial_mode => serial_mode, + si => si, + shift => ser_shift_load, + mdio_dis => '0', + sig_out => rxs_link_status_set_xhdl1, + so => chain + ); + + + + tx_rx_local_fault_clr : cycloneiv_hssi_cmu_dprio_bit + PORT MAP ( + reset => mdio_rst, + clk => mdc, + sig_in => tx_rx_local_fault_status_rd, + ext_in => '0', + serial_mode => serial_mode, + si => chain, + shift => ser_shift_load, + mdio_dis => '0', + sig_out => rtx_rx_local_fault_clr_xhdl0, + so => so_xhdl2 + ); + + mbus_out <= + xgxs_stat1_reg WHEN (reg_addr = XGXS_STATUS1) else + xgxs_stat2_reg WHEN (reg_addr = XGXS_STATUS2) else + xgxs_lane_stat_reg WHEN (reg_addr = XGXS_LANE_STATUS) else + -- Muxing for Central PCS registers + mbus_out_centrl WHEN (reg_addr = (X"6000" + X"0000")) else + mbus_out_centrl WHEN (reg_addr = (X"6000" + X"0001")) else + mbus_out_centrl WHEN (reg_addr = (X"6000" + X"0002")) else + mbus_out_centrl WHEN (reg_addr = (X"6000" + X"0003")) else + -- Muxing for CMU PMA registers + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0000")) else + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0001")) else + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0002")) else + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0003")) else + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0004")) else + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0005")) else + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0006")) else + mbus_out_centrl WHEN (reg_addr = (X"4800" + X"0007")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0000")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0001")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0002")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0003")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0004")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0005")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0006")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0007")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0008")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"0009")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"000A")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"000B")) else + mbus_out_centrl WHEN (reg_addr = (X"4C00" + X"000C")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0000")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0001")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0002")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0003")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0004")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0005")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0006")) else + mbus_out_centrl WHEN (reg_addr = (X"5800" + X"0007")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0000")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0001")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0002")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0003")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0004")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0005")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0006")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0007")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0008")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"0009")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"000A")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"000B")) else + mbus_out_centrl WHEN (reg_addr = (X"5C00" + X"000C")) else + -- Muxing for PCS channel0 registers + mbus_out_ch0 WHEN (reg_addr = (X"0000" + X"0000")) else + mbus_out_ch0 WHEN (reg_addr = (X"0000" + X"0001")) else + mbus_out_ch0 WHEN (reg_addr = (X"0000" + X"0002")) else + mbus_out_ch0 WHEN (reg_addr = (X"0000" + X"0003")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0000")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0001")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0002")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0003")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0004")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0005")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0006")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0007")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0008")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0009")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"000A")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"000B")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"000C")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"000D")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"000E")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"000F")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0010")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0011")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0012")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0013")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0014")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0015")) else + mbus_out_ch0 WHEN (reg_addr = (X"0400" + X"0016")) else + -- Muxing for PMA channel0 registers + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0000")) else + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0001")) else + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0002")) else + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0003")) else + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0004")) else + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0005")) else + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0006")) else + mbus_out_ch0 WHEN (reg_addr = (X"0800" + X"0007")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0000")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0001")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0002")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0003")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0004")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0005")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0006")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0007")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0008")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0009")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"000A")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"000B")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"000C")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"000D")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"000E")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"000F")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0010")) else + mbus_out_ch0 WHEN (reg_addr = (X"0C00" + X"0011")) else + -- Muxing for PCS channel1 registers + mbus_out_ch1 WHEN (reg_addr = (X"1000" + X"0000")) else + mbus_out_ch1 WHEN (reg_addr = (X"1000" + X"0001")) else + mbus_out_ch1 WHEN (reg_addr = (X"1000" + X"0002")) else + mbus_out_ch1 WHEN (reg_addr = (X"1000" + X"0003")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0000")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0001")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0002")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0003")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0004")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0005")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0006")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0007")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0008")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0009")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"000A")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"000B")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"000C")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"000D")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"000E")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"000F")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0010")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0011")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0012")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0013")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0014")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0015")) else + mbus_out_ch1 WHEN (reg_addr = (X"1400" + X"0016")) else + -- Muxing for PMA channel1 registers + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0000")) else + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0001")) else + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0002")) else + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0003")) else + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0004")) else + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0005")) else + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0006")) else + mbus_out_ch1 WHEN (reg_addr = (X"1800" + X"0007")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0000")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0001")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0002")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0003")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0004")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0005")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0006")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0007")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0008")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0009")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"000A")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"000B")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"000C")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"000D")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"000E")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"000F")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0010")) else + mbus_out_ch1 WHEN (reg_addr = (X"1C00" + X"0011")) else + -- Muxing for PCS channel2 registers + mbus_out_ch2 WHEN (reg_addr = (X"2000" + X"0000")) else + mbus_out_ch2 WHEN (reg_addr = (X"2000" + X"0001")) else + mbus_out_ch2 WHEN (reg_addr = (X"2000" + X"0002")) else + mbus_out_ch2 WHEN (reg_addr = (X"2000" + X"0003")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0000")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0001")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0002")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0003")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0004")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0005")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0006")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0007")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0008")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0009")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"000A")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"000B")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"000C")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"000D")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"000E")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"000F")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0010")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0011")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0012")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0013")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0014")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0015")) else + mbus_out_ch2 WHEN (reg_addr = (X"2400" + X"0016")) else + -- Muxing for PMA channel2 registers + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0000")) else + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0001")) else + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0002")) else + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0003")) else + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0004")) else + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0005")) else + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0006")) else + mbus_out_ch2 WHEN (reg_addr = (X"2800" + X"0007")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0000")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0001")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0002")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0003")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0004")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0005")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0006")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0007")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0008")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0009")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"000A")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"000B")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"000C")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"000D")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"000E")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"000F")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0010")) else + mbus_out_ch2 WHEN (reg_addr = (X"2C00" + X"0011")) else + -- Muxing for PCS channel3 registers + mbus_out_ch3 WHEN (reg_addr = (X"3000" + X"0000")) else + mbus_out_ch3 WHEN (reg_addr = (X"3000" + X"0001")) else + mbus_out_ch3 WHEN (reg_addr = (X"3000" + X"0002")) else + mbus_out_ch3 WHEN (reg_addr = (X"3000" + X"0003")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0000")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0001")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0002")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0003")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0004")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0005")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0006")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0007")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0008")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0009")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"000A")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"000B")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"000C")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"000D")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"000E")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"000F")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0010")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0011")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0012")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0013")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0014")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0015")) else + mbus_out_ch3 WHEN (reg_addr = (X"3400" + X"0016")) else + -- Muxing for PMA channel3 registers + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0000")) else + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0001")) else + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0002")) else + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0003")) else + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0004")) else + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0005")) else + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0006")) else + mbus_out_ch3 WHEN (reg_addr = (X"3800" + X"0007")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0000")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0001")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0002")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0003")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0004")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0005")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0006")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0007")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0008")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0009")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"000A")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"000B")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"000C")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"000D")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"000E")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"000F")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0010")) else + mbus_out_ch3 WHEN (reg_addr = (X"3C00" + X"0011")) else + X"0000"; + +END trans; + + + +-- MDIO readout data +-- Muxing for status registers + +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 33 mux21 32 oper_add 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_cmu_dprio_addr IS + PORT + ( + incr_addr : IN STD_LOGIC; + mdc : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + reg_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + reset : IN STD_LOGIC; + shift_addr : IN STD_LOGIC + ); + END cycloneiv_hssi_cmu_dprio_addr; + + ARCHITECTURE RTL OF cycloneiv_hssi_cmu_dprio_addr IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nlO0i15 : STD_LOGIC := '0'; + SIGNAL nlO0i16 : STD_LOGIC := '0'; + SIGNAL nlO0l13 : STD_LOGIC := '0'; + SIGNAL nlO0l14 : STD_LOGIC := '0'; + SIGNAL nlO0O11 : STD_LOGIC := '0'; + SIGNAL nlO0O12 : STD_LOGIC := '0'; + SIGNAL wire_nlO0O12_w_lg_w_lg_q45w46w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O12_w_lg_q45w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOii10 : STD_LOGIC := '0'; + SIGNAL wire_nlOii10_w_lg_w_lg_q37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii10_w_lg_q37w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOii9 : STD_LOGIC := '0'; + SIGNAL nlOil7 : STD_LOGIC := '0'; + SIGNAL nlOil8 : STD_LOGIC := '0'; + SIGNAL wire_nlOil8_w_lg_w_lg_q33w34w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOil8_w_lg_q33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOiO5 : STD_LOGIC := '0'; + SIGNAL nlOiO6 : STD_LOGIC := '0'; + SIGNAL wire_nlOiO6_w_lg_w_lg_q30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO6_w_lg_q30w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOli3 : STD_LOGIC := '0'; + SIGNAL nlOli4 : STD_LOGIC := '0'; + SIGNAL wire_nlOli4_w_lg_w_lg_q25w26w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOli4_w_lg_q25w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOOi1 : STD_LOGIC := '0'; + SIGNAL nlOOi2 : STD_LOGIC := '0'; + SIGNAL n0il : STD_LOGIC := '0'; + SIGNAL n0iO : STD_LOGIC := '0'; + SIGNAL n0li : STD_LOGIC := '0'; + SIGNAL n0ll : STD_LOGIC := '0'; + SIGNAL n0lO : STD_LOGIC := '0'; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL ni0i : STD_LOGIC := '0'; + SIGNAL ni0l : STD_LOGIC := '0'; + SIGNAL ni0O : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1l : STD_LOGIC := '0'; + SIGNAL ni1O : STD_LOGIC := '0'; + SIGNAL niii : STD_LOGIC := '0'; + SIGNAL niil : STD_LOGIC := '0'; + SIGNAL nili : STD_LOGIC := '0'; + SIGNAL wire_niiO_CLRN : STD_LOGIC; + SIGNAL wire_niiO_PRN : STD_LOGIC; + SIGNAL wire_niiO_w_lg_w14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w14w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w13w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w7w8w9w10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w7w8w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_niil1w2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_niil1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_niil1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_ni_a : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni_b : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_ni_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_w_lg_nlOlO19w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reset98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1O : STD_LOGIC; + SIGNAL nlOll : STD_LOGIC; + SIGNAL nlOlO : STD_LOGIC; + BEGIN + + wire_gnd <= '0'; + wire_w_lg_nlOlO19w(0) <= NOT nlOlO; + wire_w_lg_reset98w(0) <= NOT reset; + nlO1O <= '1'; + nlOll <= (wire_w_lg_nlOlO19w(0) AND incr_addr); + nlOlO <= (wire_niiO_w_lg_w14w15w(0) AND (nlOOi2 XOR nlOOi1)); + reg_addr <= ( niil & niii & ni0O & ni0l & ni0i & ni1O & ni1l & ni1i & n0OO & n0Ol & n0Oi & n0lO & n0ll & n0li & n0iO & n0il); + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0i15 <= nlO0i16; + END IF; + if (now = 0 ns) then + nlO0i15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0i16 <= nlO0i15; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0l13 <= nlO0l14; + END IF; + if (now = 0 ns) then + nlO0l13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0l14 <= nlO0l13; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0O11 <= nlO0O12; + END IF; + if (now = 0 ns) then + nlO0O11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0O12 <= nlO0O11; + END IF; + END PROCESS; + wire_nlO0O12_w_lg_w_lg_q45w46w(0) <= wire_nlO0O12_w_lg_q45w(0) AND niil; + wire_nlO0O12_w_lg_q45w(0) <= nlO0O12 XOR nlO0O11; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOii10 <= nlOii9; + END IF; + END PROCESS; + wire_nlOii10_w_lg_w_lg_q37w38w(0) <= wire_nlOii10_w_lg_q37w(0) AND ni1l; + wire_nlOii10_w_lg_q37w(0) <= nlOii10 XOR nlOii9; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOii9 <= nlOii10; + END IF; + if (now = 0 ns) then + nlOii9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOil7 <= nlOil8; + END IF; + if (now = 0 ns) then + nlOil7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOil8 <= nlOil7; + END IF; + END PROCESS; + wire_nlOil8_w_lg_w_lg_q33w34w(0) <= wire_nlOil8_w_lg_q33w(0) AND n0OO; + wire_nlOil8_w_lg_q33w(0) <= nlOil8 XOR nlOil7; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOiO5 <= nlOiO6; + END IF; + if (now = 0 ns) then + nlOiO5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOiO6 <= nlOiO5; + END IF; + END PROCESS; + wire_nlOiO6_w_lg_w_lg_q30w31w(0) <= wire_nlOiO6_w_lg_q30w(0) AND n0Ol; + wire_nlOiO6_w_lg_q30w(0) <= nlOiO6 XOR nlOiO5; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOli3 <= nlOli4; + END IF; + if (now = 0 ns) then + nlOli3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOli4 <= nlOli3; + END IF; + END PROCESS; + wire_nlOli4_w_lg_w_lg_q25w26w(0) <= wire_nlOli4_w_lg_q25w(0) AND n0ll; + wire_nlOli4_w_lg_q25w(0) <= nlOli4 XOR nlOli3; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOOi1 <= nlOOi2; + END IF; + if (now = 0 ns) then + nlOOi1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOOi2 <= nlOOi1; + END IF; + END PROCESS; + PROCESS (mdc, wire_niiO_PRN, wire_niiO_CLRN) + BEGIN + IF (wire_niiO_PRN = '0') THEN + n0il <= '1'; + n0iO <= '1'; + n0li <= '1'; + n0ll <= '1'; + n0lO <= '1'; + n0Oi <= '1'; + n0Ol <= '1'; + n0OO <= '1'; + ni0i <= '1'; + ni0l <= '1'; + ni0O <= '1'; + ni1i <= '1'; + ni1l <= '1'; + ni1O <= '1'; + niii <= '1'; + niil <= '1'; + nili <= '1'; + ELSIF (wire_niiO_CLRN = '0') THEN + n0il <= '0'; + n0iO <= '0'; + n0li <= '0'; + n0ll <= '0'; + n0lO <= '0'; + n0Oi <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + ni0i <= '0'; + ni0l <= '0'; + ni0O <= '0'; + ni1i <= '0'; + ni1l <= '0'; + ni1O <= '0'; + niii <= '0'; + niil <= '0'; + nili <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + n0il <= wire_nill_dataout; + n0iO <= wire_nilO_dataout; + n0li <= wire_niOi_dataout; + n0ll <= wire_niOl_dataout; + n0lO <= wire_niOO_dataout; + n0Oi <= wire_nl1i_dataout; + n0Ol <= wire_nl1l_dataout; + n0OO <= wire_nl1O_dataout; + ni0i <= wire_nlii_dataout; + ni0l <= wire_nlil_dataout; + ni0O <= wire_nliO_dataout; + ni1i <= wire_nl0i_dataout; + ni1l <= wire_nl0l_dataout; + ni1O <= wire_nl0O_dataout; + niii <= wire_nlli_dataout; + niil <= wire_nlll_dataout; + nili <= mdio_in; + END IF; + END PROCESS; + wire_niiO_CLRN <= ((nlO0l14 XOR nlO0l13) AND wire_w_lg_reset98w(0)); + wire_niiO_PRN <= (nlO0i16 XOR nlO0i15); + wire_niiO_w_lg_w14w15w(0) <= wire_niiO_w14w(0) AND n0il; + wire_niiO_w14w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w13w(0) AND n0iO; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w13w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w(0) AND n0li; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w(0) AND n0ll; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w(0) <= wire_niiO_w_lg_w_lg_w_lg_w7w8w9w10w(0) AND n0lO; + wire_niiO_w_lg_w_lg_w_lg_w7w8w9w10w(0) <= wire_niiO_w_lg_w_lg_w7w8w9w(0) AND n0Oi; + wire_niiO_w_lg_w_lg_w7w8w9w(0) <= wire_niiO_w_lg_w7w8w(0) AND n0Ol; + wire_niiO_w_lg_w7w8w(0) <= wire_niiO_w7w(0) AND n0OO; + wire_niiO_w7w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w6w(0) AND ni1i; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w6w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w(0) AND ni1l; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w(0) AND ni1O; + wire_niiO_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w(0) <= wire_niiO_w_lg_w_lg_w_lg_niil1w2w3w(0) AND ni0i; + wire_niiO_w_lg_w_lg_w_lg_niil1w2w3w(0) <= wire_niiO_w_lg_w_lg_niil1w2w(0) AND ni0l; + wire_niiO_w_lg_w_lg_niil1w2w(0) <= wire_niiO_w_lg_niil1w(0) AND ni0O; + wire_niiO_w_lg_niil1w(0) <= niil AND niii; + wire_n0i_dataout <= wire_ni_o(7) WHEN nlOll = '1' ELSE n0OO; + wire_n0l_dataout <= wire_ni_o(8) WHEN nlOll = '1' ELSE ni1i; + wire_n0O_dataout <= wire_ni_o(9) WHEN nlOll = '1' ELSE ni1l; + wire_n1i_dataout <= wire_ni_o(4) WHEN nlOll = '1' ELSE n0lO; + wire_n1l_dataout <= wire_ni_o(5) WHEN nlOll = '1' ELSE n0Oi; + wire_n1O_dataout <= wire_ni_o(6) WHEN nlOll = '1' ELSE n0Ol; + wire_nii_dataout <= wire_ni_o(10) WHEN nlOll = '1' ELSE ni1O; + wire_nil_dataout <= wire_ni_o(11) WHEN nlOll = '1' ELSE ni0i; + wire_nill_dataout <= nili WHEN shift_addr = '1' ELSE wire_nllO_dataout; + wire_nilO_dataout <= n0il WHEN shift_addr = '1' ELSE wire_nlOi_dataout; + wire_niO_dataout <= wire_ni_o(12) WHEN nlOll = '1' ELSE ni0l; + wire_niOi_dataout <= n0iO WHEN shift_addr = '1' ELSE wire_nlOl_dataout; + wire_niOl_dataout <= n0li WHEN shift_addr = '1' ELSE wire_nlOO_dataout; + wire_niOO_dataout <= n0ll WHEN shift_addr = '1' ELSE wire_n1i_dataout; + wire_nl0i_dataout <= n0OO WHEN shift_addr = '1' ELSE wire_n0l_dataout; + wire_nl0l_dataout <= ni1i WHEN shift_addr = '1' ELSE wire_n0O_dataout; + wire_nl0O_dataout <= ni1l WHEN shift_addr = '1' ELSE wire_nii_dataout; + wire_nl1i_dataout <= n0lO WHEN shift_addr = '1' ELSE wire_n1l_dataout; + wire_nl1l_dataout <= n0Oi WHEN shift_addr = '1' ELSE wire_n1O_dataout; + wire_nl1O_dataout <= n0Ol WHEN shift_addr = '1' ELSE wire_n0i_dataout; + wire_nli_dataout <= wire_ni_o(13) WHEN nlOll = '1' ELSE ni0O; + wire_nlii_dataout <= ni1O WHEN shift_addr = '1' ELSE wire_nil_dataout; + wire_nlil_dataout <= ni0i WHEN shift_addr = '1' ELSE wire_niO_dataout; + wire_nliO_dataout <= ni0l WHEN shift_addr = '1' ELSE wire_nli_dataout; + wire_nll_dataout <= wire_ni_o(14) WHEN nlOll = '1' ELSE niii; + wire_nlli_dataout <= ni0O WHEN shift_addr = '1' ELSE wire_nll_dataout; + wire_nlll_dataout <= niii WHEN shift_addr = '1' ELSE wire_nlO_dataout; + wire_nllO_dataout <= wire_ni_o(0) WHEN nlOll = '1' ELSE n0il; + wire_nlO_dataout <= wire_ni_o(15) WHEN nlOll = '1' ELSE niil; + wire_nlOi_dataout <= wire_ni_o(1) WHEN nlOll = '1' ELSE n0iO; + wire_nlOl_dataout <= wire_ni_o(2) WHEN nlOll = '1' ELSE n0li; + wire_nlOO_dataout <= wire_ni_o(3) WHEN nlOll = '1' ELSE n0ll; + wire_ni_a <= ( wire_nlO0O12_w_lg_w_lg_q45w46w & niii & ni0O & ni0l & ni0i & ni1O & wire_nlOii10_w_lg_w_lg_q37w38w & ni1i & wire_nlOil8_w_lg_w_lg_q33w34w & wire_nlOiO6_w_lg_w_lg_q30w31w & n0Oi & n0lO & wire_nlOli4_w_lg_w_lg_q25w26w & n0li & n0iO & n0il); + wire_ni_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + ni : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 16, + width_b => 16, + width_o => 16 + ) + PORT MAP ( + a => wire_ni_a, + b => wire_ni_b, + cin => wire_gnd, + o => wire_ni_o + ); + + END RTL; --cycloneiv_hssi_cmu_dprio_addr +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 17 mux21 10 oper_add 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_cmu_dprio_cnt IS + PORT + ( + cnt_eq_0 : OUT STD_LOGIC; + cnt_val : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + ld_cnt : IN STD_LOGIC; + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC + ); + END cycloneiv_hssi_cmu_dprio_cnt; + + ARCHITECTURE RTL OF cycloneiv_hssi_cmu_dprio_cnt IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL ni0O10 : STD_LOGIC := '0'; + SIGNAL ni0O9 : STD_LOGIC := '0'; + SIGNAL ni1O11 : STD_LOGIC := '0'; + SIGNAL ni1O12 : STD_LOGIC := '0'; + SIGNAL niiO7 : STD_LOGIC := '0'; + SIGNAL niiO8 : STD_LOGIC := '0'; + SIGNAL nili5 : STD_LOGIC := '0'; + SIGNAL nili6 : STD_LOGIC := '0'; + SIGNAL nill3 : STD_LOGIC := '0'; + SIGNAL nill4 : STD_LOGIC := '0'; + SIGNAL wire_nill4_w_lg_w_lg_q16w17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nill4_w_lg_q16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi1 : STD_LOGIC := '0'; + SIGNAL niOi2 : STD_LOGIC := '0'; + SIGNAL n1i : STD_LOGIC := '0'; + SIGNAL ni : STD_LOGIC := '0'; + SIGNAL nlOi : STD_LOGIC := '0'; + SIGNAL nlOl : STD_LOGIC := '0'; + SIGNAL nlOO : STD_LOGIC := '0'; + SIGNAL wire_nlO_CLRN : STD_LOGIC; + SIGNAL wire_nlO_PRN : STD_LOGIC; + SIGNAL wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_w_lg_w_lg_ni1w2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_w_lg_ni1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_ni1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nl_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_nl_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_w_lg_ld_cnt51w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l50w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reset33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni0l : STD_LOGIC; + SIGNAL niil : STD_LOGIC; + SIGNAL nilO : STD_LOGIC; + BEGIN + + wire_gnd <= '0'; + wire_w_lg_ld_cnt51w(0) <= NOT ld_cnt; + wire_w_lg_ni0l50w(0) <= NOT ni0l; + wire_w_lg_reset33w(0) <= NOT reset; + cnt_eq_0 <= ((wire_w_lg_ni0l50w(0) AND wire_w_lg_ld_cnt51w(0)) AND (ni1O12 XOR ni1O11)); + ni0l <= (wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w(0) OR (NOT (ni0O10 XOR ni0O9))); + niil <= '1'; + nilO <= (wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w(0) OR (NOT (niOi2 XOR niOi1))); + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni0O10 <= ni0O9; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni0O9 <= ni0O10; + END IF; + if (now = 0 ns) then + ni0O9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni1O11 <= ni1O12; + END IF; + if (now = 0 ns) then + ni1O11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni1O12 <= ni1O11; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niiO7 <= niiO8; + END IF; + if (now = 0 ns) then + niiO7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niiO8 <= niiO7; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nili5 <= nili6; + END IF; + if (now = 0 ns) then + nili5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nili6 <= nili5; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nill3 <= nill4; + END IF; + if (now = 0 ns) then + nill3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nill4 <= nill3; + END IF; + END PROCESS; + wire_nill4_w_lg_w_lg_q16w17w(0) <= wire_nill4_w_lg_q16w(0) AND n1i; + wire_nill4_w_lg_q16w(0) <= nill4 XOR nill3; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOi1 <= niOi2; + END IF; + if (now = 0 ns) then + niOi1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOi2 <= niOi1; + END IF; + END PROCESS; + PROCESS (mdc, wire_nlO_PRN, wire_nlO_CLRN) + BEGIN + IF (wire_nlO_PRN = '0') THEN + n1i <= '1'; + ni <= '1'; + nlOi <= '1'; + nlOl <= '1'; + nlOO <= '1'; + ELSIF (wire_nlO_CLRN = '0') THEN + n1i <= '0'; + ni <= '0'; + nlOi <= '0'; + nlOl <= '0'; + nlOO <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + n1i <= wire_n0O_dataout; + ni <= wire_n1l_dataout; + nlOi <= wire_n1O_dataout; + nlOl <= wire_n0i_dataout; + nlOO <= wire_n0l_dataout; + END IF; + END PROCESS; + wire_nlO_CLRN <= ((nili6 XOR nili5) AND wire_w_lg_reset33w(0)); + wire_nlO_PRN <= (niiO8 XOR niiO7); + wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w(0) <= wire_nlO_w_lg_w_lg_w_lg_ni1w2w3w(0) OR nlOi; + wire_nlO_w_lg_w_lg_w_lg_ni1w2w3w(0) <= wire_nlO_w_lg_w_lg_ni1w2w(0) OR nlOl; + wire_nlO_w_lg_w_lg_ni1w2w(0) <= wire_nlO_w_lg_ni1w(0) OR nlOO; + wire_nlO_w_lg_ni1w(0) <= ni OR n1i; + wire_n0i_dataout <= cnt_val(2) WHEN ld_cnt = '1' ELSE wire_niO_dataout; + wire_n0l_dataout <= cnt_val(3) WHEN ld_cnt = '1' ELSE wire_nli_dataout; + wire_n0O_dataout <= cnt_val(4) WHEN ld_cnt = '1' ELSE wire_nll_dataout; + wire_n1l_dataout <= cnt_val(0) WHEN ld_cnt = '1' ELSE wire_nii_dataout; + wire_n1O_dataout <= cnt_val(1) WHEN ld_cnt = '1' ELSE wire_nil_dataout; + wire_nii_dataout <= wire_nl_o(1) WHEN nilO = '1' ELSE ni; + wire_nil_dataout <= wire_nl_o(2) WHEN nilO = '1' ELSE nlOi; + wire_niO_dataout <= wire_nl_o(3) WHEN nilO = '1' ELSE nlOl; + wire_nli_dataout <= wire_nl_o(4) WHEN nilO = '1' ELSE nlOO; + wire_nll_dataout <= wire_nl_o(5) WHEN nilO = '1' ELSE n1i; + wire_nl_a <= ( wire_nill4_w_lg_w_lg_q16w17w & nlOO & nlOl & nlOi & ni & "1"); + wire_nl_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + nl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nl_a, + b => wire_nl_b, + cin => wire_gnd, + o => wire_nl_o + ); + + END RTL; --cycloneiv_hssi_cmu_dprio_cnt +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + +--synthesis_resources = lut 47 mux21 36 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_hssi_cmu_dprio_ctl_data IS + PORT + ( + data_enable_n : OUT STD_LOGIC; + dev_addr : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + latch_ctl : IN STD_LOGIC; + ld_data : IN STD_LOGIC; + mbus_in : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + mbus_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + mdc : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + mdio_out : OUT STD_LOGIC; + opcode : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + port_addr : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + reset : IN STD_LOGIC; + shift_in : IN STD_LOGIC; + shift_out : IN STD_LOGIC; + valid_addr : OUT STD_LOGIC; + valid_addr_lt : IN STD_LOGIC + ); + END cycloneiv_hssi_cmu_dprio_ctl_data; + + ARCHITECTURE RTL OF cycloneiv_hssi_cmu_dprio_ctl_data IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nilll25 : STD_LOGIC := '0'; + SIGNAL nilll26 : STD_LOGIC := '0'; + SIGNAL nilOi23 : STD_LOGIC := '0'; + SIGNAL nilOi24 : STD_LOGIC := '0'; + SIGNAL nilOO21 : STD_LOGIC := '0'; + SIGNAL nilOO22 : STD_LOGIC := '0'; + SIGNAL niO0i17 : STD_LOGIC := '0'; + SIGNAL niO0i18 : STD_LOGIC := '0'; + SIGNAL niO0O15 : STD_LOGIC := '0'; + SIGNAL niO0O16 : STD_LOGIC := '0'; + SIGNAL niO1l19 : STD_LOGIC := '0'; + SIGNAL niO1l20 : STD_LOGIC := '0'; + SIGNAL niOil13 : STD_LOGIC := '0'; + SIGNAL niOil14 : STD_LOGIC := '0'; + SIGNAL niOiO11 : STD_LOGIC := '0'; + SIGNAL niOiO12 : STD_LOGIC := '0'; + SIGNAL niOlO10 : STD_LOGIC := '0'; + SIGNAL niOlO9 : STD_LOGIC := '0'; + SIGNAL niOOl7 : STD_LOGIC := '0'; + SIGNAL niOOl8 : STD_LOGIC := '0'; + SIGNAL nl10l3 : STD_LOGIC := '0'; + SIGNAL nl10l4 : STD_LOGIC := '0'; + SIGNAL nl11l5 : STD_LOGIC := '0'; + SIGNAL nl11l6 : STD_LOGIC := '0'; + SIGNAL nl1iO1 : STD_LOGIC := '0'; + SIGNAL nl1iO2 : STD_LOGIC := '0'; + SIGNAL wire_nl1iO2_w_lg_q6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1li : STD_LOGIC := '0'; + SIGNAL n1lO : STD_LOGIC := '0'; + SIGNAL wire_n1ll_PRN : STD_LOGIC; + SIGNAL n00i : STD_LOGIC := '0'; + SIGNAL n00l : STD_LOGIC := '0'; + SIGNAL n00O : STD_LOGIC := '0'; + SIGNAL n01l : STD_LOGIC := '0'; + SIGNAL n01O : STD_LOGIC := '0'; + SIGNAL n0ii : STD_LOGIC := '0'; + SIGNAL n0il : STD_LOGIC := '0'; + SIGNAL n0iO : STD_LOGIC := '0'; + SIGNAL n0li : STD_LOGIC := '0'; + SIGNAL n0ll : STD_LOGIC := '0'; + SIGNAL n0lO : STD_LOGIC := '0'; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL n1iO : STD_LOGIC := '0'; + SIGNAL n1Oi : STD_LOGIC := '0'; + SIGNAL ni0i : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1l : STD_LOGIC := '0'; + SIGNAL wire_ni1O_CLRN : STD_LOGIC; + SIGNAL wire_ni1O_w_lg_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_w_lg_w_lg_ni1i2w4w7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_w_lg_ni1i2w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0Oi34w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0lO33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0OO3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_ni1i2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n00i107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n00l115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0li84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0ll92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_w_lg_reset30w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_out48w49w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_out48w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOll : STD_LOGIC; + SIGNAL nl10i : STD_LOGIC; + SIGNAL nl11i : STD_LOGIC; + SIGNAL nl11O : STD_LOGIC; + SIGNAL nl1ii : STD_LOGIC; + SIGNAL nl1il : STD_LOGIC; + SIGNAL wire_w_dev_addr_range106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dev_addr_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_port_addr_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_port_addr_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_reset30w(0) <= NOT reset; + wire_w_lg_w_lg_shift_out48w49w(0) <= wire_w_lg_shift_out48w(0) OR n01l; + wire_w_lg_shift_out48w(0) <= shift_out OR ld_data; + data_enable_n <= (NOT ((wire_w_lg_w_lg_shift_out48w49w(0) AND (nl10i OR valid_addr_lt)) AND (niO0O16 XOR niO0O15))); + mbus_in <= ( ni0i & ni1l & ni1i & n0OO & n0Ol & n0Oi & n0lO & n0ll & n0li & n0iO & n0il & n0ii & n00O & n00l & n00i & n01O); + mdio_out <= wire_nl_dataout; + niOll <= (((n0Oi AND n0lO) OR (wire_ni1O_w_lg_n0Oi34w(0) AND (niOOl8 XOR niOOl7))) OR (NOT (niOlO10 XOR niOlO9))); + nl10i <= (wire_ni1O_w_lg_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w9w(0) AND (nl10l4 XOR nl10l3)); + nl11i <= '1'; + nl11O <= (shift_in OR shift_out); + nl1ii <= ((((((NOT (n01O XOR dev_addr(0))) AND (NOT (wire_ni1O_w_lg_n00i107w(0) XOR (NOT (nilOO22 XOR nilOO21))))) AND (NOT (wire_ni1O_w_lg_n00l115w(0) XOR (NOT (nilOi24 XOR nilOi23))))) AND (NOT (n00O XOR dev_addr(3)))) AND (NOT (n0ii XOR dev_addr(4)))) AND (nilll26 XOR nilll25)); + nl1il <= (((((NOT (n0il XOR port_addr(0))) AND (NOT (n0iO XOR port_addr(1)))) AND (NOT (wire_ni1O_w_lg_n0li84w(0) XOR (NOT (niO0i18 XOR niO0i17))))) AND (NOT (wire_ni1O_w_lg_n0ll92w(0) XOR (NOT (niO1l20 XOR niO1l19))))) AND (NOT (n0lO XOR port_addr(4)))); + opcode <= ( n1lO & n1li); + valid_addr <= nl10i; + wire_w_dev_addr_range106w(0) <= dev_addr(1); + wire_w_dev_addr_range114w(0) <= dev_addr(2); + wire_w_port_addr_range83w(0) <= port_addr(2); + wire_w_port_addr_range91w(0) <= port_addr(3); + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilll25 <= nilll26; + END IF; + if (now = 0 ns) then + nilll25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilll26 <= nilll25; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOi23 <= nilOi24; + END IF; + if (now = 0 ns) then + nilOi23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOi24 <= nilOi23; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOO21 <= nilOO22; + END IF; + if (now = 0 ns) then + nilOO21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOO22 <= nilOO21; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0i17 <= niO0i18; + END IF; + if (now = 0 ns) then + niO0i17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0i18 <= niO0i17; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0O15 <= niO0O16; + END IF; + if (now = 0 ns) then + niO0O15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0O16 <= niO0O15; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO1l19 <= niO1l20; + END IF; + if (now = 0 ns) then + niO1l19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO1l20 <= niO1l19; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOil13 <= niOil14; + END IF; + if (now = 0 ns) then + niOil13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOil14 <= niOil13; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOiO11 <= niOiO12; + END IF; + if (now = 0 ns) then + niOiO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOiO12 <= niOiO11; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOlO10 <= niOlO9; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOlO9 <= niOlO10; + END IF; + if (now = 0 ns) then + niOlO9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOOl7 <= niOOl8; + END IF; + if (now = 0 ns) then + niOOl7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOOl8 <= niOOl7; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl10l3 <= nl10l4; + END IF; + if (now = 0 ns) then + nl10l3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl10l4 <= nl10l3; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl11l5 <= nl11l6; + END IF; + if (now = 0 ns) then + nl11l5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl11l6 <= nl11l5; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl1iO1 <= nl1iO2; + END IF; + if (now = 0 ns) then + nl1iO1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl1iO2 <= nl1iO1; + END IF; + END PROCESS; + wire_nl1iO2_w_lg_q6w(0) <= nl1iO2 XOR nl1iO1; + PROCESS (mdc, wire_n1ll_PRN, reset) + BEGIN + IF (wire_n1ll_PRN = '0') THEN + n1li <= '1'; + n1lO <= '1'; + ELSIF (reset = '1') THEN + n1li <= '0'; + n1lO <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + IF (latch_ctl = '1') THEN + n1li <= n0lO; + n1lO <= n0Oi; + END IF; + END IF; + END PROCESS; + wire_n1ll_PRN <= (niOil14 XOR niOil13); + PROCESS (mdc, wire_ni1O_CLRN) + BEGIN + IF (wire_ni1O_CLRN = '0') THEN + n00i <= '0'; + n00l <= '0'; + n00O <= '0'; + n01l <= '0'; + n01O <= '0'; + n0ii <= '0'; + n0il <= '0'; + n0iO <= '0'; + n0li <= '0'; + n0ll <= '0'; + n0lO <= '0'; + n0Oi <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + n1iO <= '0'; + n1Oi <= '0'; + ni0i <= '0'; + ni1i <= '0'; + ni1l <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + n00i <= wire_ni0O_dataout; + n00l <= wire_niii_dataout; + n00O <= wire_niil_dataout; + n01l <= wire_n1Ol_dataout; + n01O <= wire_ni0l_dataout; + n0ii <= wire_niiO_dataout; + n0il <= wire_nili_dataout; + n0iO <= wire_nill_dataout; + n0li <= wire_nilO_dataout; + n0ll <= wire_niOi_dataout; + n0lO <= wire_niOl_dataout; + n0Oi <= wire_niOO_dataout; + n0Ol <= wire_nl1i_dataout; + n0OO <= wire_nl1l_dataout; + n1iO <= wire_n1OO_dataout; + n1Oi <= mdio_in; + ni0i <= wire_nl0l_dataout; + ni1i <= wire_nl1O_dataout; + ni1l <= wire_nl0i_dataout; + END IF; + END PROCESS; + wire_ni1O_CLRN <= ((nl11l6 XOR nl11l5) AND wire_w_lg_reset30w(0)); + wire_ni1O_w_lg_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w9w(0) <= wire_ni1O_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w(0) AND nl1ii; + wire_ni1O_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w(0) <= wire_ni1O_w_lg_w_lg_w_lg_ni1i2w4w7w(0) AND nl1il; + wire_ni1O_w_lg_w_lg_w_lg_ni1i2w4w7w(0) <= wire_ni1O_w_lg_w_lg_ni1i2w4w(0) AND wire_nl1iO2_w_lg_q6w(0); + wire_ni1O_w_lg_w_lg_ni1i2w4w(0) <= wire_ni1O_w_lg_ni1i2w(0) AND wire_ni1O_w_lg_n0OO3w(0); + wire_ni1O_w_lg_n0Oi34w(0) <= n0Oi AND wire_ni1O_w_lg_n0lO33w(0); + wire_ni1O_w_lg_n0lO33w(0) <= NOT n0lO; + wire_ni1O_w_lg_n0OO3w(0) <= NOT n0OO; + wire_ni1O_w_lg_ni1i2w(0) <= NOT ni1i; + wire_ni1O_w_lg_n00i107w(0) <= n00i XOR wire_w_dev_addr_range106w(0); + wire_ni1O_w_lg_n00l115w(0) <= n00l XOR wire_w_dev_addr_range114w(0); + wire_ni1O_w_lg_n0li84w(0) <= n0li XOR wire_w_port_addr_range83w(0); + wire_ni1O_w_lg_n0ll92w(0) <= n0ll XOR wire_w_port_addr_range91w(0); + wire_n0i_dataout <= n0OO WHEN nl11O = '1' ELSE ni1i; + wire_n0l_dataout <= ni1i WHEN nl11O = '1' ELSE ni1l; + wire_n0O_dataout <= ni1l WHEN nl11O = '1' ELSE ni0i; + wire_n1i_dataout <= n0lO WHEN nl11O = '1' ELSE n0Oi; + wire_n1l_dataout <= n0Oi WHEN nl11O = '1' ELSE n0Ol; + wire_n1O_dataout <= n0Ol WHEN nl11O = '1' ELSE n0OO; + wire_n1Ol_dataout <= niOll WHEN latch_ctl = '1' ELSE ((n01l AND n1iO) AND (niOiO12 XOR niOiO11)); + wire_n1OO_dataout <= niOll AND latch_ctl; + wire_ni0l_dataout <= mbus_out(15) WHEN ld_data = '1' ELSE wire_nl0O_dataout; + wire_ni0O_dataout <= mbus_out(0) WHEN ld_data = '1' ELSE wire_nlii_dataout; + wire_niii_dataout <= mbus_out(1) WHEN ld_data = '1' ELSE wire_nlil_dataout; + wire_niil_dataout <= mbus_out(2) WHEN ld_data = '1' ELSE wire_nliO_dataout; + wire_niiO_dataout <= mbus_out(3) WHEN ld_data = '1' ELSE wire_nlli_dataout; + wire_nili_dataout <= mbus_out(4) WHEN ld_data = '1' ELSE wire_nlll_dataout; + wire_nill_dataout <= mbus_out(5) WHEN ld_data = '1' ELSE wire_nllO_dataout; + wire_nilO_dataout <= mbus_out(6) WHEN ld_data = '1' ELSE wire_nlOi_dataout; + wire_niOi_dataout <= mbus_out(7) WHEN ld_data = '1' ELSE wire_nlOl_dataout; + wire_niOl_dataout <= mbus_out(8) WHEN ld_data = '1' ELSE wire_nlOO_dataout; + wire_niOO_dataout <= mbus_out(9) WHEN ld_data = '1' ELSE wire_n1i_dataout; + wire_nl_dataout <= mbus_out(15) WHEN ld_data = '1' ELSE wire_nO_dataout; + wire_nl0i_dataout <= mbus_out(13) WHEN ld_data = '1' ELSE wire_n0l_dataout; + wire_nl0l_dataout <= mbus_out(14) WHEN ld_data = '1' ELSE wire_n0O_dataout; + wire_nl0O_dataout <= n1Oi WHEN nl11O = '1' ELSE n01O; + wire_nl1i_dataout <= mbus_out(10) WHEN ld_data = '1' ELSE wire_n1l_dataout; + wire_nl1l_dataout <= mbus_out(11) WHEN ld_data = '1' ELSE wire_n1O_dataout; + wire_nl1O_dataout <= mbus_out(12) WHEN ld_data = '1' ELSE wire_n0i_dataout; + wire_nlii_dataout <= n01O WHEN nl11O = '1' ELSE n00i; + wire_nlil_dataout <= n00i WHEN nl11O = '1' ELSE n00l; + wire_nliO_dataout <= n00l WHEN nl11O = '1' ELSE n00O; + wire_nlli_dataout <= n00O WHEN nl11O = '1' ELSE n0ii; + wire_nlll_dataout <= n0ii WHEN nl11O = '1' ELSE n0il; + wire_nllO_dataout <= n0il WHEN nl11O = '1' ELSE n0iO; + wire_nlOi_dataout <= n0iO WHEN nl11O = '1' ELSE n0li; + wire_nlOl_dataout <= n0li WHEN nl11O = '1' ELSE n0ll; + wire_nlOO_dataout <= n0ll WHEN nl11O = '1' ELSE n0lO; + wire_nO_dataout <= ni0i AND shift_out; + + END RTL; --cycloneiv_hssi_cmu_dprio_ctl_data +--synopsys translate_on +--VALID FILE + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_sm IS + GENERIC ( + + IDLE : INTEGER := 0; + PREAMBLE : INTEGER := 1; + CONTROL : INTEGER := 2; + TURN_ARND_0 : INTEGER := 3; + TURN_ARND_1 : INTEGER := 4; + ADDR_DATA : INTEGER := 5; + ADDR_OP : INTEGER := 0; + WR_OP : INTEGER := 1; + RD_INC_OP : INTEGER := 2; + RD_OP : INTEGER := 3 + ); + PORT ( + mdc : IN STD_LOGIC; -- Clock for MDIO interface + mdio_in : IN STD_LOGIC; -- Signal bit data + reset : IN STD_LOGIC; -- Active high Hard Reset + opcode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- 2 bit opcode from mdio_ctl_data module + -- 00 - Address + -- 01 - Write + -- 10 - Read with no post Increment + -- 11 - Read with post increment + valid_addr : IN STD_LOGIC; -- When set the Port and Dev Address + -- corresponds to this module + cnt_eq_0 : IN STD_LOGIC; -- From mdio_cnt module, down counter is 0 + shift_in : OUT STD_LOGIC; -- Shift in enable for either data or control + shift_out : OUT STD_LOGIC; -- Shift out enable for mdio_ctl_data + latch_ctl : OUT STD_LOGIC; -- Latch the Opcode, to mdio_ctl_data + incr_addr : OUT STD_LOGIC; -- Increment signal for mdio_addr + mdio_wr : OUT STD_LOGIC; -- This is used for writing the mdio registers + mdio_rd : OUT STD_LOGIC; -- This is used for clearing the mdio status registers + shift_addr : OUT STD_LOGIC; -- Shift in Enable for mdio_addr + ld_data : OUT STD_LOGIC; -- When set, the shift register is mdio_ctl_data is parallely + -- loaded with the data from mdio_reg module + --output ld_data_d; + ld_cnt : OUT STD_LOGIC; -- Load Down counter + cnt_val : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Value to load the down counter + valid_addr_lt : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END cycloneiv_hssi_cmu_dprio_sm; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_sm IS + + --wire ld_data_d; + + -- Allowed states for curr_state and next_state + + -- Decode for opcode + + SIGNAL next_state : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL cnt_val_xhdl0 : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL curr_state_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0); +BEGIN + -- Drive referenced outputs + cnt_val <= cnt_val_xhdl0; + curr_state <= curr_state_xhdl1; + + -- Latch Curr State + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + curr_state_xhdl1 <= int2bin(IDLE, 3); + ELSIF (mdc'EVENT AND mdc = '1') THEN + curr_state_xhdl1 <= next_state; + END IF; + END PROCESS; + + -- Next State loic for mdio_sm + + PROCESS (curr_state_xhdl1, mdio_in, cnt_eq_0, valid_addr, opcode) +VARIABLE txt : LINE; + BEGIN +-- shawn manual fix IF (curr_state_xhdl1'EVENT) THEN + + CASE curr_state_xhdl1 IS + + WHEN "000" => + IF (mdio_in = '1') THEN + next_state <= int2bin(PREAMBLE, 3); + ELSE + next_state <= int2bin(IDLE, 3); + END IF; + WHEN "001" => + IF ((NOT(mdio_in) AND NOT(cnt_eq_0)) = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSIF ((NOT(mdio_in) AND cnt_eq_0) = '1') THEN + next_state <= int2bin(CONTROL, 3); + ELSE + next_state <= int2bin(PREAMBLE, 3); + END IF; + + WHEN "010" => + IF (cnt_eq_0 = '1') THEN + IF ((NOT(mdio_in)) = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSE + next_state <= int2bin(TURN_ARND_0, 3); + END IF; + ELSE + next_state <= int2bin(CONTROL, 3); + END IF; + + WHEN "011" => + IF ((mdio_in OR NOT(valid_addr)) = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSIF (opcode = int2bin(WR_OP, 2) OR opcode = int2bin(ADDR_OP, 2)) THEN + next_state <= int2bin(TURN_ARND_1, 3); + ELSE + next_state <= int2bin(ADDR_DATA, 3); + END IF; + -- if (mdio_in) + -- next_state <= IDLE; + -- else + + WHEN "100" => + next_state <= int2bin(ADDR_DATA, 3); + + WHEN "101" => + IF ((cnt_eq_0 AND mdio_in) = '1' AND (opcode = int2bin(WR_OP, 2) OR opcode = int2bin(ADDR_OP, 2))) THEN + next_state <= int2bin(PREAMBLE, 3); + ELSIF (cnt_eq_0 = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSE + next_state <= int2bin(ADDR_DATA, 3); + END IF; + + WHEN OTHERS => + next_state <= int2bin(IDLE, 3); + END CASE; +-- shawn manual fix END IF; + END PROCESS; + + -- Valid_addr_lt is used to enable mdio_out + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + valid_addr_lt <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (valid_addr = '1' AND curr_state_xhdl1 = int2bin(TURN_ARND_0, 3)) THEN + valid_addr_lt <= '1'; + ELSIF (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND cnt_eq_0 = '1') THEN + valid_addr_lt <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for shift_in, This signal is used for shifting in + -- control logic, during all commands, and data during + -- Write command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + shift_in <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(PREAMBLE, 3) AND next_state = int2bin(CONTROL, 3)) OR (next_state = int2bin(CONTROL, 3)) OR (next_state = int2bin(ADDR_DATA, 3) AND opcode = int2bin(WR_OP, 2))) THEN + shift_in <= '1'; + ELSE + shift_in <= '0'; + END IF; + END IF; + END PROCESS; + + -- Shift_out logic, shift_out is set when data is shifted out on + -- a RD_OP or RD_INC_OP command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + shift_out <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3)) OR (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND (opcode = int2bin(RD_OP, 2) OR opcode = int2bin(RD_INC_OP, 2)) AND ((NOT(cnt_eq_0))) = '1')) THEN + shift_out <= '1'; + ELSE + shift_out <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for latch_ctl, this signal is used for latching the opcode + -- This signal is set when in Control state and moving to TURN_ARND_0 + -- state + + PROCESS (cnt_eq_0, curr_state_xhdl1) +VARIABLE txt : LINE; + BEGIN + IF (curr_state_xhdl1'EVENT) THEN + + -- Logic for incr_addr, incr_addr is set for opcode RD_INC_OP and + -- after completely shifting out the read data for the current command + + latch_ctl <= cnt_eq_0 AND int2bit(curr_state_xhdl1 = int2bin(CONTROL, 3)); + END IF; + END PROCESS; + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + incr_addr <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND cnt_eq_0 = '1' AND opcode = int2bin(RD_INC_OP, 2)) THEN + incr_addr <= '1'; + ELSE + incr_addr <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for shift addr, this bit is set when moving to ADDR_DATA + -- state and when in ADDR_DATA state for ADDR_OP command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + shift_addr <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (next_state = int2bin(ADDR_DATA, 3) AND opcode = int2bin(ADDR_OP, 2)) THEN + shift_addr <= '1'; + ELSE + shift_addr <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for mdio_wr, this bit is set when moving from ADDR_DATA to the + -- IDLE for a WR_OP command + -- Logic for mdio_rd, this bit is set when moving from ADDR_DATA to the + -- IDLE for a RD_OP/RD_INC_OP command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + mdio_wr <= '0'; + mdio_rd <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND cnt_eq_0 = '1') THEN + IF (opcode = int2bin(WR_OP, 2)) THEN + mdio_wr <= '1'; + ELSE + mdio_wr <= '0'; + END IF; + IF (opcode = int2bin(RD_OP, 2) OR opcode = int2bin(RD_INC_OP, 2)) THEN + mdio_rd <= '1'; + ELSE + mdio_rd <= '0'; + END IF; + ELSE + mdio_wr <= '0'; + mdio_rd <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for ld_data, this signal is used for parallely loading the + -- shift register in mdio_ctl_data module with the data from mdio_reg + -- module. This set is set for RD_OP and RD_INC_OP commands when the + -- SM transitions from TURN_ARND_0 to ADDR_DATA state + -- assign ld_data_d = (curr_state == TURN_ARND_0 && (opcode == RD_OP | opcode == RD_INC_OP)); + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + ld_data <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + ld_data <= int2bit((curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3))); + END IF; + END PROCESS; + + -- Logic for ld_cnt, this signal is used for loading the down counter + -- with cnt_val signal. This signal is set when going to + -- CONTROL state or ADDR_DATA state or PREAMBLE states + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + ld_cnt <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(IDLE, 3) AND next_state = int2bin(PREAMBLE, 3)) OR (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND next_state = int2bin(PREAMBLE, 3)) OR (curr_state_xhdl1 = int2bin(PREAMBLE, 3) AND next_state = int2bin(CONTROL, 3)) OR (curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3)) OR (curr_state_xhdl1 = int2bin(TURN_ARND_1, 3) AND next_state = int2bin(ADDR_DATA, 3))) THEN + ld_cnt <= '1'; + ELSE + ld_cnt <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for cnt_val, this counter value is used for sown counting + -- the mdio_cnt, when the counter reaches zero, the cnt_eq_0 is + -- set. The counter is loading with 31 for PREAMBLE, 13 for + -- CONTROL, and 15 for ADDR_DATA + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + cnt_val_xhdl0 <= "00000"; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(IDLE, 3) OR curr_state_xhdl1 = int2bin(ADDR_DATA, 3)) AND next_state = int2bin(PREAMBLE, 3)) THEN + cnt_val_xhdl0 <= "11110"; + ELSIF (curr_state_xhdl1 = int2bin(PREAMBLE, 3) AND next_state = int2bin(CONTROL, 3)) THEN + cnt_val_xhdl0 <= "01100"; + ELSIF (curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3)) THEN + cnt_val_xhdl0 <= "01110"; + ELSIF (curr_state_xhdl1 = int2bin(TURN_ARND_1, 3) AND next_state = int2bin(ADDR_DATA, 3)) THEN + cnt_val_xhdl0 <= "01110"; + ELSE + cnt_val_xhdl0 <= cnt_val_xhdl0; + END IF; + END IF; + END PROCESS; + +END trans; + + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_reg_centrl IS + PORT ( + -- CSR input + -- DPRIO register output + + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + ext_centrl_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + targ_addr_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + out_centrl_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + + so : OUT STD_LOGIC + ); +END cycloneiv_hssi_cmu_dprio_reg_centrl; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_reg_centrl IS + COMPONENT cycloneiv_hssi_cmu_dprio_16bit + PORT ( + reset : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_16bit_pma + PORT ( + reset : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL chain : STD_LOGIC_VECTOR(44 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL out_centrl_ctrl_1_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_2_xhdl11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_3_xhdl22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_4_xhdl33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_5_xhdl39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_6_xhdl40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_7_xhdl41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_8_xhdl42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_9_xhdl43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_10_xhdl1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_11_xhdl2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_12_xhdl3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_13_xhdl4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_14_xhdl5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_15_xhdl6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_16_xhdl7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_17_xhdl8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_18_xhdl9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_19_xhdl10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_20_xhdl12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_21_xhdl13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_22_xhdl14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_23_xhdl15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_24_xhdl16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_25_xhdl17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_26_xhdl18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_27_xhdl19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_28_xhdl20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_29_xhdl21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_30_xhdl23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_31_xhdl24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_32_xhdl25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_33_xhdl26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_34_xhdl27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_35_xhdl28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_36_xhdl29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_37_xhdl30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_38_xhdl31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_39_xhdl32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_40_xhdl34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_41_xhdl35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_42_xhdl36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_43_xhdl37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_44_xhdl38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_45_tmp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_46_tmp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL so_tmp : STD_LOGIC; +BEGIN + -- Drive referenced outputs + out_centrl_ctrl_1 <= out_centrl_ctrl_1_xhdl0; + out_centrl_ctrl_2 <= out_centrl_ctrl_2_xhdl11; + out_centrl_ctrl_3 <= out_centrl_ctrl_3_xhdl22; + out_centrl_ctrl_4 <= out_centrl_ctrl_4_xhdl33; + out_centrl_ctrl_5 <= out_centrl_ctrl_5_xhdl39; + out_centrl_ctrl_6 <= out_centrl_ctrl_6_xhdl40; + out_centrl_ctrl_7 <= out_centrl_ctrl_7_xhdl41; + out_centrl_ctrl_8 <= out_centrl_ctrl_8_xhdl42; + out_centrl_ctrl_9 <= out_centrl_ctrl_9_xhdl43; + out_centrl_ctrl_10 <= out_centrl_ctrl_10_xhdl1; + out_centrl_ctrl_11 <= out_centrl_ctrl_11_xhdl2; + out_centrl_ctrl_12 <= out_centrl_ctrl_12_xhdl3; + out_centrl_ctrl_13 <= out_centrl_ctrl_13_xhdl4; + out_centrl_ctrl_14 <= out_centrl_ctrl_14_xhdl5; + out_centrl_ctrl_15 <= out_centrl_ctrl_15_xhdl6; + out_centrl_ctrl_16 <= out_centrl_ctrl_16_xhdl7; + out_centrl_ctrl_17 <= out_centrl_ctrl_17_xhdl8; + out_centrl_ctrl_18 <= out_centrl_ctrl_18_xhdl9; + out_centrl_ctrl_19 <= out_centrl_ctrl_19_xhdl10; + out_centrl_ctrl_20 <= out_centrl_ctrl_20_xhdl12; + out_centrl_ctrl_21 <= out_centrl_ctrl_21_xhdl13; + out_centrl_ctrl_22 <= out_centrl_ctrl_22_xhdl14; + out_centrl_ctrl_23 <= out_centrl_ctrl_23_xhdl15; + out_centrl_ctrl_24 <= out_centrl_ctrl_24_xhdl16; + out_centrl_ctrl_25 <= out_centrl_ctrl_25_xhdl17; + out_centrl_ctrl_26 <= out_centrl_ctrl_26_xhdl18; + out_centrl_ctrl_27 <= out_centrl_ctrl_27_xhdl19; + out_centrl_ctrl_28 <= out_centrl_ctrl_28_xhdl20; + out_centrl_ctrl_29 <= out_centrl_ctrl_29_xhdl21; + out_centrl_ctrl_30 <= out_centrl_ctrl_30_xhdl23; + out_centrl_ctrl_31 <= out_centrl_ctrl_31_xhdl24; + out_centrl_ctrl_32 <= out_centrl_ctrl_32_xhdl25; + out_centrl_ctrl_33 <= out_centrl_ctrl_33_xhdl26; + out_centrl_ctrl_34 <= out_centrl_ctrl_34_xhdl27; + out_centrl_ctrl_35 <= out_centrl_ctrl_35_xhdl28; + out_centrl_ctrl_36 <= out_centrl_ctrl_36_xhdl29; + out_centrl_ctrl_37 <= out_centrl_ctrl_37_xhdl30; + out_centrl_ctrl_38 <= out_centrl_ctrl_38_xhdl31; + out_centrl_ctrl_39 <= out_centrl_ctrl_39_xhdl32; + out_centrl_ctrl_40 <= out_centrl_ctrl_40_xhdl34; + out_centrl_ctrl_41 <= out_centrl_ctrl_41_xhdl35; + out_centrl_ctrl_42 <= out_centrl_ctrl_42_xhdl36; + out_centrl_ctrl_43 <= out_centrl_ctrl_43_xhdl37; + out_centrl_ctrl_44 <= out_centrl_ctrl_44_xhdl38; + out_centrl_ctrl_45 <= out_centrl_ctrl_45_tmp; + out_centrl_ctrl_46 <= out_centrl_ctrl_46_tmp; + + so <= so_tmp; + + + + centrl_ctrl_1 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_1, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_1, + serial_mode => serial_mode, + si => si, + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_1_xhdl0, + so => chain(0) + ); + + + + centrl_ctrl_2 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_2, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_2, + serial_mode => serial_mode, + si => chain(0), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_2_xhdl11, + so => chain(1) + ); + + + + centrl_ctrl_3 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_3, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_3, + serial_mode => serial_mode, + si => chain(1), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_3_xhdl22, + so => chain(2) + ); + + + + centrl_ctrl_4 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_4, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_4, + serial_mode => serial_mode, + si => chain(2), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_4_xhdl33, + so => chain(3) + ); + + + + centrl_ctrl_5 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_5, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_5, + serial_mode => serial_mode, + si => chain(3), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_5_xhdl39, + so => chain(4) + ); + + + + centrl_ctrl_6 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_6, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_6, + serial_mode => serial_mode, + si => chain(4), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_6_xhdl40, + so => chain(5) + ); + + + + centrl_ctrl_7 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_7, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_7, + serial_mode => serial_mode, + si => chain(5), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_7_xhdl41, + so => chain(6) + ); + + + + centrl_ctrl_8 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_8, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_8, + serial_mode => serial_mode, + si => chain(6), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_8_xhdl42, + so => chain(7) + ); + + + + centrl_ctrl_9 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_9, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_9, + serial_mode => serial_mode, + si => chain(7), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_9_xhdl43, + so => chain(8) + ); + + + + centrl_ctrl_10 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_10, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_10, + serial_mode => serial_mode, + si => chain(8), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_10_xhdl1, + so => chain(9) + ); + + + + centrl_ctrl_11 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_11, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_11, + serial_mode => serial_mode, + si => chain(9), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_11_xhdl2, + so => chain(10) + ); + + + + centrl_ctrl_12 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_12, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_12, + serial_mode => serial_mode, + si => chain(10), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_12_xhdl3, + so => chain(11) + ); + + + + centrl_ctrl_13 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_13, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_13, + serial_mode => serial_mode, + si => chain(11), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_13_xhdl4, + so => chain(12) + ); + + + + centrl_ctrl_14 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_14, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_14, + serial_mode => serial_mode, + si => chain(12), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_14_xhdl5, + so => chain(13) + ); + + + + centrl_ctrl_15 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_15, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_15, + serial_mode => serial_mode, + si => chain(13), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_15_xhdl6, + so => chain(14) + ); + + + + centrl_ctrl_16 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_16, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_16, + serial_mode => serial_mode, + si => chain(14), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_16_xhdl7, + so => chain(15) + ); + + + + centrl_ctrl_17 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_17, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_17, + serial_mode => serial_mode, + si => chain(15), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_17_xhdl8, + so => chain(16) + ); + + + + centrl_ctrl_18 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_18, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_18, + serial_mode => serial_mode, + si => chain(16), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_18_xhdl9, + so => chain(17) + ); + + + + centrl_ctrl_19 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_19, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_19, + serial_mode => serial_mode, + si => chain(17), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_19_xhdl10, + so => chain(18) + ); + + + + centrl_ctrl_20 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_20, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_20, + serial_mode => serial_mode, + si => chain(18), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_20_xhdl12, + so => chain(19) + ); + + + + centrl_ctrl_21 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_21, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_21, + serial_mode => serial_mode, + si => chain(19), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_21_xhdl13, + so => chain(20) + ); + + + + centrl_ctrl_22 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_22, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_22, + serial_mode => serial_mode, + si => chain(20), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_22_xhdl14, + so => chain(21) + ); + + + + centrl_ctrl_23 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_23, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_23, + serial_mode => serial_mode, + si => chain(21), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_23_xhdl15, + so => chain(22) + ); + + + + centrl_ctrl_24 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_24, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_24, + serial_mode => serial_mode, + si => chain(22), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_24_xhdl16, + so => chain(23) + ); + + + + centrl_ctrl_25 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_25, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_25, + serial_mode => serial_mode, + si => chain(23), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_25_xhdl17, + so => chain(24) + ); + + + + centrl_ctrl_26 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_26, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_26, + serial_mode => serial_mode, + si => chain(24), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_26_xhdl18, + so => chain(25) + ); + + + + centrl_ctrl_27 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_27, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_27, + serial_mode => serial_mode, + si => chain(25), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_27_xhdl19, + so => chain(26) + ); + + + + centrl_ctrl_28 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_28, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_28, + serial_mode => serial_mode, + si => chain(26), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_28_xhdl20, + so => chain(27) + ); + + + + centrl_ctrl_29 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_29, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_29, + serial_mode => serial_mode, + si => chain(27), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_29_xhdl21, + so => chain(28) + ); + + + + centrl_ctrl_30 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_30, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_30, + serial_mode => serial_mode, + si => chain(28), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_30_xhdl23, + so => chain(29) + ); + + + + centrl_ctrl_31 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_31, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_31, + serial_mode => serial_mode, + si => chain(29), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_31_xhdl24, + so => chain(30) + ); + + + + centrl_ctrl_32 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_32, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_32, + serial_mode => serial_mode, + si => chain(30), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_32_xhdl25, + so => chain(31) + ); + + + + centrl_ctrl_33 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_33, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_33, + serial_mode => serial_mode, + si => chain(31), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_33_xhdl26, + so => chain(32) + ); + + + + centrl_ctrl_34 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_34, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_34, + serial_mode => serial_mode, + si => chain(32), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_34_xhdl27, + so => chain(33) + ); + + + + centrl_ctrl_35 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_35, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_35, + serial_mode => serial_mode, + si => chain(33), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_35_xhdl28, + so => chain(34) + ); + + + + centrl_ctrl_36 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_36, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_36, + serial_mode => serial_mode, + si => chain(34), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_36_xhdl29, + so => chain(35) + ); + + + + centrl_ctrl_37 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_37, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_37, + serial_mode => serial_mode, + si => chain(35), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_37_xhdl30, + so => chain(36) + ); + + + + centrl_ctrl_38 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_38, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_38, + serial_mode => serial_mode, + si => chain(36), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_38_xhdl31, + so => chain(37) + ); + + + + centrl_ctrl_39 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_39, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_39, + serial_mode => serial_mode, + si => chain(37), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_39_xhdl32, + so => chain(38) + ); + + + + centrl_ctrl_40 : cycloneiv_hssi_cmu_dprio_16bit_pma + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_40, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_40, + serial_mode => serial_mode, + si => chain(38), + shift => ser_shift_load, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + sig_out => out_centrl_ctrl_40_xhdl34, + so => chain(39) + ); + + + + centrl_ctrl_41 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_41, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_41, + serial_mode => serial_mode, + si => chain(39), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_centrl_ctrl_41_xhdl35, + so => chain(40) + ); + + + + centrl_ctrl_42 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_42, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_42, + serial_mode => serial_mode, + si => chain(40), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_centrl_ctrl_42_xhdl36, + so => chain(41) + ); + + + + centrl_ctrl_43 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_43, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_43, + serial_mode => serial_mode, + si => chain(41), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_centrl_ctrl_43_xhdl37, + so => chain(42) + ); + + + + centrl_ctrl_44 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_44, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_44, + serial_mode => serial_mode, + si => chain(42), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_centrl_ctrl_44_xhdl38, + so => chain(43) + ); + + -- new ww25 + centrl_ctrl_45 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_45, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_45, + serial_mode => serial_mode, + si => chain(43), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_centrl_ctrl_45_tmp, + so => chain(44) + ); + + centrl_ctrl_46 : cycloneiv_hssi_cmu_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_46, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_centrl_ctrl_46, + serial_mode => serial_mode, + si => chain(44), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_centrl_ctrl_46_tmp, + so => so_tmp + ); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_centrl_bus_out_mux IS + PORT ( + + centrl_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + hw_address_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + centrl_ctrl_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END cycloneiv_hssi_cmu_dprio_centrl_bus_out_mux; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_centrl_bus_out_mux IS +BEGIN + + centrl_ctrl_out <= centrl_ctrl_in1 WHEN (reg_addr = hw_address_ctrl_in1) ELSE + centrl_ctrl_in2 WHEN (reg_addr = hw_address_ctrl_in2) ELSE + centrl_ctrl_in3 WHEN (reg_addr = hw_address_ctrl_in3) ELSE + centrl_ctrl_in4 WHEN (reg_addr = hw_address_ctrl_in4) ELSE + centrl_ctrl_in5 WHEN (reg_addr = hw_address_ctrl_in5) ELSE + centrl_ctrl_in6 WHEN (reg_addr = hw_address_ctrl_in6) ELSE + centrl_ctrl_in7 WHEN (reg_addr = hw_address_ctrl_in7) ELSE + centrl_ctrl_in8 WHEN (reg_addr = hw_address_ctrl_in8) ELSE + centrl_ctrl_in9 WHEN (reg_addr = hw_address_ctrl_in9) ELSE + centrl_ctrl_in10 WHEN (reg_addr = hw_address_ctrl_in10) ELSE + centrl_ctrl_in11 WHEN (reg_addr = hw_address_ctrl_in11) ELSE + centrl_ctrl_in12 WHEN (reg_addr = hw_address_ctrl_in12) ELSE + centrl_ctrl_in13 WHEN (reg_addr = hw_address_ctrl_in13) ELSE + centrl_ctrl_in14 WHEN (reg_addr = hw_address_ctrl_in14) ELSE + centrl_ctrl_in15 WHEN (reg_addr = hw_address_ctrl_in15) ELSE + centrl_ctrl_in16 WHEN (reg_addr = hw_address_ctrl_in16) ELSE + centrl_ctrl_in17 WHEN (reg_addr = hw_address_ctrl_in17) ELSE + centrl_ctrl_in18 WHEN (reg_addr = hw_address_ctrl_in18) ELSE + centrl_ctrl_in19 WHEN (reg_addr = hw_address_ctrl_in19) ELSE + centrl_ctrl_in20 WHEN (reg_addr = hw_address_ctrl_in20) ELSE + centrl_ctrl_in21 WHEN (reg_addr = hw_address_ctrl_in21) ELSE + centrl_ctrl_in22 WHEN (reg_addr = hw_address_ctrl_in22) ELSE + centrl_ctrl_in23 WHEN (reg_addr = hw_address_ctrl_in23) ELSE + centrl_ctrl_in24 WHEN (reg_addr = hw_address_ctrl_in24) ELSE + centrl_ctrl_in25 WHEN (reg_addr = hw_address_ctrl_in25) ELSE + centrl_ctrl_in26 WHEN (reg_addr = hw_address_ctrl_in26) ELSE + centrl_ctrl_in27 WHEN (reg_addr = hw_address_ctrl_in27) ELSE + centrl_ctrl_in28 WHEN (reg_addr = hw_address_ctrl_in28) ELSE + centrl_ctrl_in29 WHEN (reg_addr = hw_address_ctrl_in29) ELSE + centrl_ctrl_in30 WHEN (reg_addr = hw_address_ctrl_in30) ELSE + centrl_ctrl_in31 WHEN (reg_addr = hw_address_ctrl_in31) ELSE + centrl_ctrl_in32 WHEN (reg_addr = hw_address_ctrl_in32) ELSE + centrl_ctrl_in33 WHEN (reg_addr = hw_address_ctrl_in33) ELSE + centrl_ctrl_in34 WHEN (reg_addr = hw_address_ctrl_in34) ELSE + centrl_ctrl_in35 WHEN (reg_addr = hw_address_ctrl_in35) ELSE + centrl_ctrl_in36 WHEN (reg_addr = hw_address_ctrl_in36) ELSE + centrl_ctrl_in37 WHEN (reg_addr = hw_address_ctrl_in37) ELSE + centrl_ctrl_in38 WHEN (reg_addr = hw_address_ctrl_in38) ELSE + centrl_ctrl_in39 WHEN (reg_addr = hw_address_ctrl_in39) ELSE + centrl_ctrl_in40 WHEN (reg_addr = hw_address_ctrl_in40) ELSE + centrl_ctrl_in41 WHEN (reg_addr = hw_address_ctrl_in41) ELSE + centrl_ctrl_in42 WHEN (reg_addr = hw_address_ctrl_in42) ELSE + centrl_ctrl_in43 WHEN (reg_addr = hw_address_ctrl_in43) ELSE + centrl_ctrl_in44 WHEN (reg_addr = hw_address_ctrl_in44) ELSE + centrl_ctrl_in45 WHEN (reg_addr = hw_address_ctrl_in45) ELSE + centrl_ctrl_in46 WHEN (reg_addr = hw_address_ctrl_in46) ELSE + "0000000000000000"; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_centrl_top IS + PORT ( + mdio_rst : IN STD_LOGIC; -- DPRIO reset input + mdio_wr : IN STD_LOGIC; -- DPRIO register write enable + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- DPRIO register address from SM + mdc : IN STD_LOGIC; -- DPRIO clock + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- DPRIO data in from SM + serial_mode : IN STD_LOGIC; -- DPRIO serial mode enable + mdio_dis : IN STD_LOGIC; -- DPRIO disable signal (using CSR input) + pma_cram_test : IN STD_LOGIC; -- PLD dynamic signal for PMA DPRIO cell for coverage for PE/TE + ser_shift_load : IN STD_LOGIC; -- DPRIO serial shift or load control signal + si : IN STD_LOGIC; -- DPRIO serial input + csr_centrl_in : IN STD_LOGIC_VECTOR(703 DOWNTO 0); -- CSR inputs + csr_centrl_in_reserved : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + dp_centrl_out : OUT STD_LOGIC_VECTOR(703 DOWNTO 0); -- CSR inputs + dp_centrl_out_reserved : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + so : OUT STD_LOGIC; -- DPRIO serial out + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) -- DPRIO dataout + ); +END ENTITY cycloneiv_hssi_cmu_dprio_centrl_top; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_centrl_top IS + COMPONENT cycloneiv_hssi_cmu_dprio_centrl_bus_out_mux IS + PORT ( + centrl_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + centrl_ctrl_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_reg_centrl IS + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + ext_centrl_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_centrl_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_centrl_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + + --//////////////////////////////////////////////////////////////////////// + -- begin of CRAM output ------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + -- CRAM output + -- Central PCS CRAMs + SIGNAL rs_lpbk_all : STD_LOGIC; -- Global serial loopback enable CRAM + SIGNAL rpowerdown : STD_LOGIC; -- Output CRAM of RPOWERDOWN + SIGNAL rtest_bus_centrl_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Central Test bus selection CRAMs + SIGNAL rx16_x12_sel_tx : STD_LOGIC; -- Enable/Disable x16/x12 + SIGNAL rx16_x12_sel_rx : STD_LOGIC; -- Enable/Disable x16/x12 + SIGNAL rphfifo_master_sel_tx : STD_LOGIC; -- TX Phase comp. FIFO pointers selection CRAM + SIGNAL rphfifo_master_sel_rx : STD_LOGIC; -- TX Phase comp. FIFO pointers selection CRAM + SIGNAL rendec_data_sel_tx : STD_LOGIC; -- TX 8B10B encoder data in selection CRAM + SIGNAL rendec_data_sel_rx : STD_LOGIC; -- RX 8B10B decoder data out selection CRAM + SIGNAL rnenbpin : STD_LOGIC; -- Output CRAM of RNENBPIN + SIGNAL rpllurst : STD_LOGIC; -- Output CRAM of RPLLURST + SIGNAL rreset : STD_LOGIC; -- Output CRAM of RRESET + SIGNAL rdeskewen : STD_LOGIC; -- Deskew function enable CRAM + SIGNAL rindv_tx : STD_LOGIC; -- TX SM bypassing CRAM + SIGNAL rindv_rx : STD_LOGIC; -- RX SM bypassing CRAM + SIGNAL rfreerun_centrl : STD_LOGIC; -- REFCLK_OUT free running enable CRAM + SIGNAL rcentrl_clk_sel : STD_LOGIC; -- REFCLK_PMA global clock selection CRAM + SIGNAL rrefclk_out_div2 : STD_LOGIC; -- REFCLK_OUT divide by 2 enable CRAM + SIGNAL rxaui_s2gx_en_rx : STD_LOGIC; -- Enable S2GX XAUI RX SM behavior + SIGNAL ralgnopt : STD_LOGIC; -- De-skew SM Hysteresis Option + SIGNAL rdskposdisp : STD_LOGIC; -- Match the programmed de-skew pattern only + SIGNAL rdskchrp : STD_LOGIC_VECTOR(9 DOWNTO 0); -- Programmable Deskew Char. Pos. Disp. + SIGNAL rxaui_s2gx_en_tx : STD_LOGIC; -- Enable S2GX XAUI TX SM behavior + SIGNAL rpcs_centrl_rsvd_cram : STD_LOGIC_VECTOR(10 DOWNTO 0); -- Central PCS reserved CRAMs + SIGNAL rmaster_rx : STD_LOGIC; -- Please see S4GX DPRIO spreadsheet for description + SIGNAL rmaster_up_rx : STD_LOGIC; + SIGNAL rmaster_tx : STD_LOGIC; + SIGNAL rmaster_up_tx : STD_LOGIC; + + -- CMU0 PMA CRAMs + -- Clock Output Buffer - refer to PMA TX section for description + SIGNAL rcmu0_vod_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_powdnt : STD_LOGIC; + SIGNAL rcmu0_pre_em_1t : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rcmu0_pre_em_2t : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_pre_em_pt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_tx_term_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_tx_vtt : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_tx_lst : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_rslew : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_sig_inv_ptap : STD_LOGIC; + SIGNAL rcmu0_sig_inv_2t : STD_LOGIC; + SIGNAL rcmu0_rx_det : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_lowv : STD_LOGIC; + SIGNAL rcmu0_tx_dft_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_tx_ob_pdb : STD_LOGIC; + + -- Central Clock Generation (refer to CGB section for description) + -- Serializer (Refer to serializer section for description) + SIGNAL rcmu0_cgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_cgb_cmu_sel : STD_LOGIC; + SIGNAL rcmu0_cgb_m_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_pma_doublewidth_tx : STD_LOGIC; + SIGNAL rcmu0_pmadwidth_tx : STD_LOGIC; + SIGNAL rcmu0_delay_sel : STD_LOGIC; + SIGNAL rcmu0_dynamic_sw : STD_LOGIC; + SIGNAL rcmu0_pclksel : STD_LOGIC; + SIGNAL rcmu0_tx_cgb_pdb : STD_LOGIC; + SIGNAL rcmu0_iqsel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_refsel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_vcobypass : STD_LOGIC; + SIGNAL rcmu0_revlb_sw : STD_LOGIC; + SIGNAL rcmu0_pcs_sd_sel : STD_LOGIC; + SIGNAL rcmu0_reserved : STD_LOGIC_VECTOR(31 DOWNTO 0); --divided into 2 sixteen bit busses + + -- CMU0 RX CRAMs + -- CDR/TXPLL - refer to CDR section for description + SIGNAL rcmu0_rx_lst : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rcmu0_rx_bit_dc : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_s_rdlpbk : STD_LOGIC; + SIGNAL rcmu0_rx_vtt : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_term : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_rx_sdlv : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_rx_oc_en : STD_LOGIC; + SIGNAL rcmu0_rx_oc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rcmu0_sd_force : STD_LOGIC; + SIGNAL rcmu0_rx_test : STD_LOGIC; + SIGNAL rcmu0_rxurst : STD_LOGIC; + SIGNAL rcmu0_rx_sd_on : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_rx_sd_off : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rcmu0_rx_oc_calpd : STD_LOGIC; + SIGNAL rcmu0_urx_pdb : STD_LOGIC; + SIGNAL rcmu0_rx_ib_pdb : STD_LOGIC; + SIGNAL rcmu0_powdnr : STD_LOGIC; + SIGNAL rcmu0_div2 : STD_LOGIC; + SIGNAL rcmu0_m_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_m : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_l : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_ctl0 : STD_LOGIC; + SIGNAL rcmu0_crplctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_pfdbwctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_pdbwctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_rlbk : STD_LOGIC; + SIGNAL rcmu0_lst : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_testen : STD_LOGIC; + SIGNAL rcmu0_testupen : STD_LOGIC; + SIGNAL rcmu0_testdnen : STD_LOGIC; + SIGNAL rcmu0_isel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_iselpd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_rcp_mode : STD_LOGIC; + SIGNAL rcmu0_cru_pdb : STD_LOGIC; + SIGNAL rcmu0_rx_cmu_rst : STD_LOGIC; + SIGNAL rcmu0_cmu_mode : STD_LOGIC; + SIGNAL rcmu0_ignore_phslck : STD_LOGIC; + SIGNAL rcmu0_sd_sel : STD_LOGIC; + SIGNAL rcmu0_pdfl : STD_LOGIC; + SIGNAL rcmu0_pdof_test : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_rgla_isel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_pdof_0i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_pdof_90i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_pdof_180i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_pdof_270i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_eye_monitor : STD_LOGIC_VECTOR(7 DOWNTO 0); + + --wire [15:0] rcmu0_reserved[15:0]; declared above + -- DeSerializer - refer to deserializer section for description + SIGNAL rcmu0_pma_doublewidth_rx : STD_LOGIC; + SIGNAL rcmu0_pmadwidth_rx : STD_LOGIC; + SIGNAL rcmu0_test_fastsd : STD_LOGIC; + SIGNAL rcmu0_fastsd : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu0_ppmsel : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL rcmu0_force0_freqdet : STD_LOGIC; + SIGNAL rcmu0_force1_freqdet : STD_LOGIC; + + --DFE + SIGNAL rcmu0_dfe_1t : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu0_dfe_2t : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX/D2A - Refer to RX and ADCE for description + SIGNAL rcmu0_eqa_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_eqb_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_eqc_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_eqd_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_eqv_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_d2a_res : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL rcmu0_clk_div2 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu0_ht_sel : STD_LOGIC; + SIGNAL rcmu0_fbclk_sel : STD_LOGIC; + SIGNAL rcmu0_clk_pdb : STD_LOGIC; + SIGNAL rcmu0_rx_det_pdb : STD_LOGIC; + SIGNAL rcmu0_iqclk_sel : STD_LOGIC; + SIGNAL rcmu0_detect_on : STD_LOGIC; + -- END CMU0 CRAMs + + -- CMU1 PMA CRAMs + -- Clock Output Buffer - refer to PMA TX section for description + SIGNAL rcmu1_vod_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_powdnt : STD_LOGIC; + SIGNAL rcmu1_pre_em_1t : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rcmu1_pre_em_2t : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_pre_em_pt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_tx_term_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_tx_vtt : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_tx_lst : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_rslew : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_sig_inv_ptap : STD_LOGIC; + SIGNAL rcmu1_sig_inv_2t : STD_LOGIC; + SIGNAL rcmu1_rx_det : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_lowv : STD_LOGIC; + SIGNAL rcmu1_tx_dft_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_tx_ob_pdb : STD_LOGIC; + + -- Central Clock Generation (refer to CGB section for description) + -- Serializer (Refer to serializer section for description) + SIGNAL rcmu1_cgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_cgb_cmu_sel : STD_LOGIC; + SIGNAL rcmu1_cgb_m_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_pma_doublewidth_tx : STD_LOGIC; + SIGNAL rcmu1_pmadwidth_tx : STD_LOGIC; + SIGNAL rcmu1_delay_sel : STD_LOGIC; + SIGNAL rcmu1_dynamic_sw : STD_LOGIC; + SIGNAL rcmu1_pclksel : STD_LOGIC; + SIGNAL rcmu1_tx_cgb_pdb : STD_LOGIC; + SIGNAL rcmu1_iqsel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_refsel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_vcobypass : STD_LOGIC; + SIGNAL rcmu1_revlb_sw : STD_LOGIC; + SIGNAL rcmu1_pcs_sd_sel : STD_LOGIC; + SIGNAL rcmu1_reserved : STD_LOGIC_VECTOR(31 DOWNTO 0); --divided into 2 sixteen bit busses + + -- cmu1 RX CRAMs + -- CDR/TXPLL - refer to CDR section for description + SIGNAL rcmu1_rx_lst : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rcmu1_rx_bit_dc : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_s_rdlpbk : STD_LOGIC; + SIGNAL rcmu1_rx_vtt : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_term : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_rx_sdlv : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_rx_oc_en : STD_LOGIC; + SIGNAL rcmu1_rx_oc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rcmu1_sd_force : STD_LOGIC; + SIGNAL rcmu1_rx_test : STD_LOGIC; + SIGNAL rcmu1_rxurst : STD_LOGIC; + SIGNAL rcmu1_rx_sd_on : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_rx_sd_off : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL rcmu1_rx_oc_calpd : STD_LOGIC; + SIGNAL rcmu1_urx_pdb : STD_LOGIC; + SIGNAL rcmu1_rx_ib_pdb : STD_LOGIC; + SIGNAL rcmu1_powdnr : STD_LOGIC; + SIGNAL rcmu1_div2 : STD_LOGIC; + SIGNAL rcmu1_m_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_m : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_l : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_ctl0 : STD_LOGIC; + SIGNAL rcmu1_crplctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_pfdbwctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_pdbwctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_rlbk : STD_LOGIC; + SIGNAL rcmu1_lst : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_testen : STD_LOGIC; + SIGNAL rcmu1_testupen : STD_LOGIC; + SIGNAL rcmu1_testdnen : STD_LOGIC; + SIGNAL rcmu1_isel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_iselpd : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_rcp_mode : STD_LOGIC; + SIGNAL rcmu1_cru_pdb : STD_LOGIC; + SIGNAL rcmu1_rx_cmu_rst : STD_LOGIC; + SIGNAL rcmu1_cmu_mode : STD_LOGIC; + SIGNAL rcmu1_ignore_phslck : STD_LOGIC; + SIGNAL rcmu1_sd_sel : STD_LOGIC; + SIGNAL rcmu1_pdfl : STD_LOGIC; + SIGNAL rcmu1_pdof_test : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_rgla_isel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_pdof_0i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_pdof_90i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_pdof_180i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_pdof_270i : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_eye_monitor : STD_LOGIC_VECTOR(7 DOWNTO 0); + + --wire [15:0] rcmu1_reserved[15:0]; //declared above + -- DeSerializer - refer to deserializer section for description + SIGNAL rcmu1_pma_doublewidth_rx : STD_LOGIC; + SIGNAL rcmu1_pmadwidth_rx : STD_LOGIC; + SIGNAL rcmu1_test_fastsd : STD_LOGIC; + SIGNAL rcmu1_fastsd : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcmu1_ppmsel : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL rcmu1_force0_freqdet : STD_LOGIC; + SIGNAL rcmu1_force1_freqdet : STD_LOGIC; + + --DFE + SIGNAL rcmu1_dfe_1t : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rcmu1_dfe_2t : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- RX/D2A - Refer to RX and ADCE for description + SIGNAL rcmu1_eqa_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_eqb_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_eqc_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_eqd_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_eqv_set : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_d2a_res : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL rcmu1_clk_div2 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rcmu1_ht_sel : STD_LOGIC; + SIGNAL rcmu1_fbclk_sel : STD_LOGIC; + SIGNAL rcmu1_clk_pdb : STD_LOGIC; + SIGNAL rcmu1_rx_det_pdb : STD_LOGIC; + SIGNAL rcmu1_iqclk_sel : STD_LOGIC; + SIGNAL rcmu1_detect_on : STD_LOGIC; + -- END CMU1 CRAMs + + --//////////////////////////////////////////////////////////////////////// + -- end of CRAM output --------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + SIGNAL targ_addr_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL out_centrl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_centrl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL so_xhdl1 : STD_LOGIC; + SIGNAL mbus_out_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); +BEGIN + -- Drive referenced outputs + so <= so_xhdl1; + mbus_out <= mbus_out_xhdl0; + + --//////////////////////////////////////////////////////////////////////// + -- begin of CRAM output ------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + dp_centrl_out(15 DOWNTO 0) <= out_centrl_ctrl_1; + dp_centrl_out(31 DOWNTO 16) <= out_centrl_ctrl_2; + dp_centrl_out(47 DOWNTO 32) <= out_centrl_ctrl_3; + dp_centrl_out(63 DOWNTO 48) <= out_centrl_ctrl_4; + dp_centrl_out(79 DOWNTO 64) <= out_centrl_ctrl_5; + dp_centrl_out(95 DOWNTO 80) <= out_centrl_ctrl_6; + dp_centrl_out(111 DOWNTO 96) <= out_centrl_ctrl_7; + dp_centrl_out(127 DOWNTO 112) <= out_centrl_ctrl_8; + dp_centrl_out(143 DOWNTO 128) <= out_centrl_ctrl_9; + dp_centrl_out(159 DOWNTO 144) <= out_centrl_ctrl_10; + dp_centrl_out(175 DOWNTO 160) <= out_centrl_ctrl_11; + dp_centrl_out(191 DOWNTO 176) <= out_centrl_ctrl_12; + dp_centrl_out(207 DOWNTO 192) <= out_centrl_ctrl_13; + dp_centrl_out(223 DOWNTO 208) <= out_centrl_ctrl_14; + dp_centrl_out(239 DOWNTO 224) <= out_centrl_ctrl_15; + dp_centrl_out_reserved(15 DOWNTO 0) <= out_centrl_ctrl_16; + dp_centrl_out(255 DOWNTO 240) <= out_centrl_ctrl_17; + dp_centrl_out(271 DOWNTO 256) <= out_centrl_ctrl_18; + dp_centrl_out(287 DOWNTO 272) <= out_centrl_ctrl_19; + dp_centrl_out(303 DOWNTO 288) <= out_centrl_ctrl_20; + dp_centrl_out(319 DOWNTO 304) <= out_centrl_ctrl_21; + dp_centrl_out(335 DOWNTO 320) <= out_centrl_ctrl_22; + dp_centrl_out(351 DOWNTO 336) <= out_centrl_ctrl_23; + dp_centrl_out(367 DOWNTO 352) <= out_centrl_ctrl_24; + dp_centrl_out(383 DOWNTO 368) <= out_centrl_ctrl_25; + dp_centrl_out(399 DOWNTO 384) <= out_centrl_ctrl_26; + dp_centrl_out(415 DOWNTO 400) <= out_centrl_ctrl_27; + dp_centrl_out(431 DOWNTO 416) <= out_centrl_ctrl_28; + dp_centrl_out(447 DOWNTO 432) <= out_centrl_ctrl_29; + dp_centrl_out(463 DOWNTO 448) <= out_centrl_ctrl_30; + dp_centrl_out(479 DOWNTO 464) <= out_centrl_ctrl_31; + dp_centrl_out(495 DOWNTO 480) <= out_centrl_ctrl_32; + dp_centrl_out(511 DOWNTO 496) <= out_centrl_ctrl_33; + dp_centrl_out(527 DOWNTO 512) <= out_centrl_ctrl_34; + dp_centrl_out(543 DOWNTO 528) <= out_centrl_ctrl_35; + dp_centrl_out(559 DOWNTO 544) <= out_centrl_ctrl_36; + dp_centrl_out_reserved(31 DOWNTO 16) <= out_centrl_ctrl_37; + dp_centrl_out(575 DOWNTO 560) <= out_centrl_ctrl_38; + dp_centrl_out(591 DOWNTO 576) <= out_centrl_ctrl_39; + dp_centrl_out(607 DOWNTO 592) <= out_centrl_ctrl_40; + dp_centrl_out(623 DOWNTO 608) <= out_centrl_ctrl_41; + dp_centrl_out(639 DOWNTO 624) <= out_centrl_ctrl_42; + dp_centrl_out(655 DOWNTO 640) <= out_centrl_ctrl_43; + dp_centrl_out(671 DOWNTO 656) <= out_centrl_ctrl_44; + dp_centrl_out(687 DOWNTO 672) <= out_centrl_ctrl_45; + dp_centrl_out(703 DOWNTO 688) <= out_centrl_ctrl_46; + + --//////////////////////////////////////////////////////////////////////// + -- end of CRAM output --------------------------------------------------- + --//////////////////////////////////////////////////////////////////////// + + -- Control register address assignment + -- CMU0 PMA address space + targ_addr_ctrl_1 <= "0100100000000000" + "0000000000000000"; + targ_addr_ctrl_2 <= "0100100000000000" + "0000000000000001"; + targ_addr_ctrl_3 <= "0100100000000000" + "0000000000000010"; + targ_addr_ctrl_4 <= "0100100000000000" + "0000000000000011"; + targ_addr_ctrl_5 <= "0100100000000000" + "0000000000000100"; + targ_addr_ctrl_6 <= "0100100000000000" + "0000000000000101"; + targ_addr_ctrl_7 <= "0100100000000000" + "0000000000000110"; + targ_addr_ctrl_8 <= "0100100000000000" + "0000000000000111"; + targ_addr_ctrl_9 <= "0100110000000000" + "0000000000000000"; + targ_addr_ctrl_10 <= "0100110000000000" + "0000000000000001"; + targ_addr_ctrl_11 <= "0100110000000000" + "0000000000000010"; + targ_addr_ctrl_12 <= "0100110000000000" + "0000000000000011"; + targ_addr_ctrl_13 <= "0100110000000000" + "0000000000000100"; + targ_addr_ctrl_14 <= "0100110000000000" + "0000000000000101"; + targ_addr_ctrl_15 <= "0100110000000000" + "0000000000000110"; + targ_addr_ctrl_16 <= "0100110000000000" + "0000000000000111"; + targ_addr_ctrl_17 <= "0100110000000000" + "0000000000001000"; + targ_addr_ctrl_18 <= "0100110000000000" + "0000000000001001"; + targ_addr_ctrl_19 <= "0100110000000000" + "0000000000001010"; + targ_addr_ctrl_20 <= "0100110000000000" + "0000000000001011"; + targ_addr_ctrl_21 <= "0100110000000000" + "0000000000001100"; + + -- CMU1 PMA address space + targ_addr_ctrl_22 <= "0101100000000000" + "0000000000000000"; + targ_addr_ctrl_23 <= "0101100000000000" + "0000000000000001"; + targ_addr_ctrl_24 <= "0101100000000000" + "0000000000000010"; + targ_addr_ctrl_25 <= "0101100000000000" + "0000000000000011"; + targ_addr_ctrl_26 <= "0101100000000000" + "0000000000000100"; + targ_addr_ctrl_27 <= "0101100000000000" + "0000000000000101"; + targ_addr_ctrl_28 <= "0101100000000000" + "0000000000000110"; + targ_addr_ctrl_29 <= "0101100000000000" + "0000000000000111"; + targ_addr_ctrl_30 <= "0101110000000000" + "0000000000000000"; + targ_addr_ctrl_31 <= "0101110000000000" + "0000000000000001"; + targ_addr_ctrl_32 <= "0101110000000000" + "0000000000000010"; + targ_addr_ctrl_33 <= "0101110000000000" + "0000000000000011"; + targ_addr_ctrl_34 <= "0101110000000000" + "0000000000000100"; + targ_addr_ctrl_35 <= "0101110000000000" + "0000000000000101"; + targ_addr_ctrl_36 <= "0101110000000000" + "0000000000000110"; + targ_addr_ctrl_37 <= "0101110000000000" + "0000000000000111"; + targ_addr_ctrl_38 <= "0101110000000000" + "0000000000001000"; + targ_addr_ctrl_39 <= "0101110000000000" + "0000000000001001"; + targ_addr_ctrl_40 <= "0101110000000000" + "0000000000001010"; + targ_addr_ctrl_41 <= "0101110000000000" + "0000000000001011"; + targ_addr_ctrl_42 <= "0101110000000000" + "0000000000001100"; + + -- Central PCS address space + targ_addr_ctrl_43 <= "0110000000000000" + "0000000000000000"; + targ_addr_ctrl_44 <= "0110000000000000" + "0000000000000001"; + targ_addr_ctrl_45 <= "0110000000000000" + "0000000000000010"; + targ_addr_ctrl_46 <= "0110000000000000" + "0000000000000011"; + + -- CRAM output assignment + -- CMU0 PMA CRAMs + -- CMU0 control register 1 + rcmu0_vod_sel(2 DOWNTO 0) <= out_centrl_ctrl_1(15 DOWNTO 13); + rcmu0_powdnt <= out_centrl_ctrl_1(0); + -- CMU0 control register 2 + rcmu0_pre_em_1t(4 DOWNTO 0) <= out_centrl_ctrl_2(15 DOWNTO 11); + -- CMU0 control register 3 + rcmu0_pre_em_2t(3 DOWNTO 0) <= out_centrl_ctrl_3(7 DOWNTO 4); + rcmu0_pre_em_pt(3 DOWNTO 0) <= out_centrl_ctrl_3(3 DOWNTO 0); + -- CMU0 control register 4 + rcmu0_tx_term_sel(2 DOWNTO 0) <= out_centrl_ctrl_4(15 DOWNTO 13); + rcmu0_tx_vtt(1 DOWNTO 0) <= out_centrl_ctrl_4(12 DOWNTO 11); + rcmu0_tx_lst(3 DOWNTO 0) <= out_centrl_ctrl_4(10 DOWNTO 7); + rcmu0_rslew(1 DOWNTO 0) <= out_centrl_ctrl_4(6 DOWNTO 5); + rcmu0_sig_inv_ptap <= out_centrl_ctrl_4(4); + rcmu0_sig_inv_2t <= out_centrl_ctrl_4(3); + rcmu0_rx_det(1 DOWNTO 0) <= out_centrl_ctrl_4(2 DOWNTO 1); + rcmu0_lowv <= out_centrl_ctrl_4(0); + -- CMU0 control register 5 + rcmu0_tx_dft_sel(2 DOWNTO 0) <= out_centrl_ctrl_5(15 DOWNTO 13); + rcmu0_tx_ob_pdb <= out_centrl_ctrl_5(11); + -- CMU0 control register 6 + rcmu0_cgb_x_en(1 DOWNTO 0) <= out_centrl_ctrl_6(15 DOWNTO 14); + rcmu0_cgb_cmu_sel <= out_centrl_ctrl_6(13); + rcmu0_cgb_m_sel(1 DOWNTO 0) <= out_centrl_ctrl_6(12 DOWNTO 11); + rcmu0_pma_doublewidth_tx <= out_centrl_ctrl_6(10); + rcmu0_pmadwidth_tx <= out_centrl_ctrl_6(9); + rcmu0_delay_sel <= out_centrl_ctrl_6(8); + rcmu0_dynamic_sw <= out_centrl_ctrl_6(6); + rcmu0_pclksel <= out_centrl_ctrl_6(5); + rcmu0_tx_cgb_pdb <= out_centrl_ctrl_6(4); + -- CMU0 control register 7 + rcmu0_iqsel(1 DOWNTO 0) <= out_centrl_ctrl_7(15 DOWNTO 14); + rcmu0_refsel(1 DOWNTO 0) <= out_centrl_ctrl_7(13 DOWNTO 12); + rcmu0_vcobypass <= out_centrl_ctrl_7(11); + rcmu0_revlb_sw <= out_centrl_ctrl_7(10); + rcmu0_pcs_sd_sel <= out_centrl_ctrl_7(3); + -- CMU0 control register 8 + rcmu0_reserved(31 DOWNTO 16) <= out_centrl_ctrl_8(15 DOWNTO 0); + -- CMU0 RX CRAMs + -- CMU0 control register 9 + rcmu0_rx_lst(4 DOWNTO 0) <= out_centrl_ctrl_9(15 DOWNTO 11); + rcmu0_rx_bit_dc(3 DOWNTO 0) <= out_centrl_ctrl_9(10 DOWNTO 7); + rcmu0_s_rdlpbk <= out_centrl_ctrl_9(6); + rcmu0_rx_vtt(2 DOWNTO 0) <= out_centrl_ctrl_9(5 DOWNTO 3); + rcmu0_term(2 DOWNTO 0) <= out_centrl_ctrl_9(2 DOWNTO 0); + -- CMU0 control register 10 + rcmu0_rx_sdlv(3 DOWNTO 0) <= out_centrl_ctrl_10(15 DOWNTO 12); + rcmu0_rx_oc_en <= out_centrl_ctrl_10(11); + rcmu0_rx_oc(7 DOWNTO 0) <= out_centrl_ctrl_10(10 DOWNTO 3); + rcmu0_sd_force <= out_centrl_ctrl_10(2); + rcmu0_rx_test <= out_centrl_ctrl_10(1); + rcmu0_rxurst <= out_centrl_ctrl_10(0); + -- CMU0 control register 11 + rcmu0_rx_sd_on(3 DOWNTO 0) <= out_centrl_ctrl_11(15 DOWNTO 12); + rcmu0_rx_sd_off(4 DOWNTO 0) <= out_centrl_ctrl_11(11 DOWNTO 7); + rcmu0_rx_oc_calpd <= out_centrl_ctrl_11(6); + rcmu0_urx_pdb <= out_centrl_ctrl_11(5); + rcmu0_rx_ib_pdb <= out_centrl_ctrl_11(4); + rcmu0_powdnr <= out_centrl_ctrl_11(3); + -- CMU0 control register 12 + rcmu0_div2 <= out_centrl_ctrl_12(15); + rcmu0_m_sel(1 DOWNTO 0) <= out_centrl_ctrl_12(14 DOWNTO 13); + rcmu0_m(3 DOWNTO 0) <= out_centrl_ctrl_12(12 DOWNTO 9); + rcmu0_l(1 DOWNTO 0) <= out_centrl_ctrl_12(8 DOWNTO 7); + rcmu0_ctl0 <= out_centrl_ctrl_12(6); + rcmu0_crplctrl(1 DOWNTO 0) <= out_centrl_ctrl_12(5 DOWNTO 4); + rcmu0_pfdbwctrl(1 DOWNTO 0) <= out_centrl_ctrl_12(3 DOWNTO 2); + rcmu0_pdbwctrl(1 DOWNTO 0) <= out_centrl_ctrl_12(1 DOWNTO 0); + -- CMU0 control register 13 + rcmu0_rlbk <= out_centrl_ctrl_13(15); + rcmu0_lst(3 DOWNTO 0) <= out_centrl_ctrl_13(14 DOWNTO 11); + rcmu0_testen <= out_centrl_ctrl_13(10); + rcmu0_testupen <= out_centrl_ctrl_13(9); + rcmu0_testdnen <= out_centrl_ctrl_13(8); + rcmu0_isel(2 DOWNTO 0) <= out_centrl_ctrl_13(7 DOWNTO 5); + rcmu0_iselpd(2 DOWNTO 0) <= out_centrl_ctrl_13(4 DOWNTO 2); + -- CMU0 control register 14 + rcmu0_rcp_mode <= out_centrl_ctrl_14(15); + rcmu0_cru_pdb <= out_centrl_ctrl_14(12); + rcmu0_rx_cmu_rst <= out_centrl_ctrl_14(11); + rcmu0_cmu_mode <= out_centrl_ctrl_14(10); + rcmu0_ignore_phslck <= out_centrl_ctrl_14(9); + rcmu0_sd_sel <= out_centrl_ctrl_14(7); + rcmu0_pdfl <= out_centrl_ctrl_14(6); + rcmu0_pdof_test(2 DOWNTO 0) <= out_centrl_ctrl_14(5 DOWNTO 3); + rcmu0_rgla_isel(2 DOWNTO 0) <= out_centrl_ctrl_14(2 DOWNTO 0); + -- CMU0 control register 15 + rcmu0_pdof_0i(3 DOWNTO 0) <= out_centrl_ctrl_15(15 DOWNTO 12); + rcmu0_pdof_90i(3 DOWNTO 0) <= out_centrl_ctrl_15(11 DOWNTO 8); + rcmu0_pdof_180i(3 DOWNTO 0) <= out_centrl_ctrl_15(7 DOWNTO 4); + rcmu0_pdof_270i(3 DOWNTO 0) <= out_centrl_ctrl_15(3 DOWNTO 0); + -- CMU0 control register 16 + rcmu0_eye_monitor(7 DOWNTO 0) <= out_centrl_ctrl_16(7 DOWNTO 0); + -- CMU0 control register 17 + rcmu0_reserved(15 DOWNTO 0) <= out_centrl_ctrl_17(15 DOWNTO 0); + -- CMU0 control register 18 + rcmu0_pma_doublewidth_rx <= out_centrl_ctrl_18(15); + rcmu0_pmadwidth_rx <= out_centrl_ctrl_18(14); + rcmu0_test_fastsd <= out_centrl_ctrl_18(13); + rcmu0_fastsd(3 DOWNTO 0) <= out_centrl_ctrl_18(12 DOWNTO 9); + rcmu0_ppmsel(5 DOWNTO 0) <= out_centrl_ctrl_18(8 DOWNTO 3); + rcmu0_force0_freqdet <= out_centrl_ctrl_18(2); + rcmu0_force1_freqdet <= out_centrl_ctrl_18(1); + -- CMU0 control register 19 + rcmu0_dfe_1t(2 DOWNTO 0) <= out_centrl_ctrl_19(15 DOWNTO 13); + rcmu0_dfe_2t(2 DOWNTO 0) <= out_centrl_ctrl_19(12 DOWNTO 10); + -- CMU0 control register 20 + rcmu0_eqa_set(1 DOWNTO 0) <= out_centrl_ctrl_20(13 DOWNTO 12); + rcmu0_eqb_set(1 DOWNTO 0) <= out_centrl_ctrl_20(10 DOWNTO 9); + rcmu0_eqc_set(1 DOWNTO 0) <= out_centrl_ctrl_20(7 DOWNTO 6); + rcmu0_eqd_set(1 DOWNTO 0) <= out_centrl_ctrl_20(4 DOWNTO 3); + rcmu0_eqv_set(1 DOWNTO 0) <= out_centrl_ctrl_20(1 DOWNTO 0); + -- CMU0 control register 21 + rcmu0_d2a_res(5 DOWNTO 0) <= out_centrl_ctrl_21(15 DOWNTO 10); + rcmu0_clk_div2(1 DOWNTO 0) <= out_centrl_ctrl_21(9 DOWNTO 8); + rcmu0_ht_sel <= out_centrl_ctrl_21(7); + rcmu0_fbclk_sel <= out_centrl_ctrl_21(6); + rcmu0_clk_pdb <= out_centrl_ctrl_21(5); + rcmu0_rx_det_pdb <= out_centrl_ctrl_21(4); + rcmu0_iqclk_sel <= out_centrl_ctrl_21(2); + rcmu0_detect_on <= out_centrl_ctrl_21(1); + -- END CMU0 CRAMs + + -- CMU1 PMA CRAMs + -- CMU1 control register 1 + rcmu1_vod_sel(2 DOWNTO 0) <= out_centrl_ctrl_22(15 DOWNTO 13); + rcmu1_powdnt <= out_centrl_ctrl_22(0); + -- CMU1 control register 2 + rcmu1_pre_em_1t(4 DOWNTO 0) <= out_centrl_ctrl_23(15 DOWNTO 11); + -- CMU1 control register 3 + rcmu1_pre_em_2t(3 DOWNTO 0) <= out_centrl_ctrl_24(7 DOWNTO 4); + rcmu1_pre_em_pt(3 DOWNTO 0) <= out_centrl_ctrl_24(3 DOWNTO 0); + -- CMU1 control register 4 + rcmu1_tx_term_sel(2 DOWNTO 0) <= out_centrl_ctrl_25(15 DOWNTO 13); + rcmu1_tx_vtt(1 DOWNTO 0) <= out_centrl_ctrl_25(12 DOWNTO 11); + rcmu1_tx_lst(3 DOWNTO 0) <= out_centrl_ctrl_25(10 DOWNTO 7); + rcmu1_rslew(1 DOWNTO 0) <= out_centrl_ctrl_25(6 DOWNTO 5); + rcmu1_sig_inv_ptap <= out_centrl_ctrl_25(4); + rcmu1_sig_inv_2t <= out_centrl_ctrl_25(3); + rcmu1_rx_det(1 DOWNTO 0) <= out_centrl_ctrl_25(2 DOWNTO 1); + rcmu1_lowv <= out_centrl_ctrl_25(0); + -- CMU1 control register 5 + rcmu1_tx_dft_sel(2 DOWNTO 0) <= out_centrl_ctrl_26(15 DOWNTO 13); + rcmu1_tx_ob_pdb <= out_centrl_ctrl_26(11); + -- CMU1 control register 6 + rcmu1_cgb_x_en(1 DOWNTO 0) <= out_centrl_ctrl_27(15 DOWNTO 14); + rcmu1_cgb_cmu_sel <= out_centrl_ctrl_27(13); + rcmu1_cgb_m_sel(1 DOWNTO 0) <= out_centrl_ctrl_27(12 DOWNTO 11); + rcmu1_pma_doublewidth_tx <= out_centrl_ctrl_27(10); + rcmu1_pmadwidth_tx <= out_centrl_ctrl_27(9); + rcmu1_delay_sel <= out_centrl_ctrl_27(8); + rcmu1_dynamic_sw <= out_centrl_ctrl_27(6); + rcmu1_pclksel <= out_centrl_ctrl_27(5); + rcmu1_tx_cgb_pdb <= out_centrl_ctrl_27(4); + -- CMU1 control register 7 + rcmu1_iqsel <= out_centrl_ctrl_28(15 DOWNTO 14); + rcmu1_refsel(1 DOWNTO 0) <= out_centrl_ctrl_28(13 DOWNTO 12); + rcmu1_vcobypass <= out_centrl_ctrl_28(11); + rcmu1_revlb_sw <= out_centrl_ctrl_28(10); + rcmu1_pcs_sd_sel <= out_centrl_ctrl_28(3); + -- CMU1 control register 8 + rcmu1_reserved(31 DOWNTO 16) <= out_centrl_ctrl_29(15 DOWNTO 0); + -- CMU1 RX CRAMs + -- CMU1 control register 9 + rcmu1_rx_lst(4 DOWNTO 0) <= out_centrl_ctrl_30(15 DOWNTO 11); + rcmu1_rx_bit_dc(3 DOWNTO 0) <= out_centrl_ctrl_30(10 DOWNTO 7); + rcmu1_s_rdlpbk <= out_centrl_ctrl_30(6); + rcmu1_rx_vtt(2 DOWNTO 0) <= out_centrl_ctrl_30(5 DOWNTO 3); + rcmu1_term(2 DOWNTO 0) <= out_centrl_ctrl_30(2 DOWNTO 0); + -- CMU1 control register 10 + rcmu1_rx_sdlv(3 DOWNTO 0) <= out_centrl_ctrl_31(15 DOWNTO 12); + rcmu1_rx_oc_en <= out_centrl_ctrl_31(11); + rcmu1_rx_oc(7 DOWNTO 0) <= out_centrl_ctrl_31(10 DOWNTO 3); + rcmu1_sd_force <= out_centrl_ctrl_31(2); + rcmu1_rx_test <= out_centrl_ctrl_31(1); + rcmu1_rxurst <= out_centrl_ctrl_31(0); + -- CMU1 control register 11 + rcmu1_rx_sd_on(3 DOWNTO 0) <= out_centrl_ctrl_32(15 DOWNTO 12); + rcmu1_rx_sd_off(4 DOWNTO 0) <= out_centrl_ctrl_32(11 DOWNTO 7); + rcmu1_rx_oc_calpd <= out_centrl_ctrl_32(6); + rcmu1_urx_pdb <= out_centrl_ctrl_32(5); + rcmu1_rx_ib_pdb <= out_centrl_ctrl_32(4); + rcmu1_powdnr <= out_centrl_ctrl_32(3); + -- CMU1 control register 12 + rcmu1_div2 <= out_centrl_ctrl_33(15); + rcmu1_m_sel(1 DOWNTO 0) <= out_centrl_ctrl_33(14 DOWNTO 13); + rcmu1_m(3 DOWNTO 0) <= out_centrl_ctrl_33(12 DOWNTO 9); + rcmu1_l(1 DOWNTO 0) <= out_centrl_ctrl_33(8 DOWNTO 7); + rcmu1_ctl0 <= out_centrl_ctrl_33(6); + rcmu1_crplctrl(1 DOWNTO 0) <= out_centrl_ctrl_33(5 DOWNTO 4); + rcmu1_pfdbwctrl(1 DOWNTO 0) <= out_centrl_ctrl_33(3 DOWNTO 2); + rcmu1_pdbwctrl(1 DOWNTO 0) <= out_centrl_ctrl_33(1 DOWNTO 0); + -- CMU1 control register 13 + rcmu1_rlbk <= out_centrl_ctrl_34(15); + rcmu1_lst(3 DOWNTO 0) <= out_centrl_ctrl_34(14 DOWNTO 11); + rcmu1_testen <= out_centrl_ctrl_34(10); + rcmu1_testupen <= out_centrl_ctrl_34(9); + rcmu1_testdnen <= out_centrl_ctrl_34(8); + rcmu1_isel(2 DOWNTO 0) <= out_centrl_ctrl_34(7 DOWNTO 5); + rcmu1_iselpd(2 DOWNTO 0) <= out_centrl_ctrl_34(4 DOWNTO 2); + -- CMU1 control register 14 + rcmu1_rcp_mode <= out_centrl_ctrl_35(15); + rcmu1_cru_pdb <= out_centrl_ctrl_35(12); + rcmu1_rx_cmu_rst <= out_centrl_ctrl_35(11); + rcmu1_cmu_mode <= out_centrl_ctrl_35(10); + rcmu1_ignore_phslck <= out_centrl_ctrl_35(9); + rcmu1_sd_sel <= out_centrl_ctrl_35(7); + rcmu1_pdfl <= out_centrl_ctrl_35(6); + rcmu1_pdof_test(2 DOWNTO 0) <= out_centrl_ctrl_35(5 DOWNTO 3); + rcmu1_rgla_isel(2 DOWNTO 0) <= out_centrl_ctrl_35(2 DOWNTO 0); + -- CMU1 control register 15 + rcmu1_pdof_0i(3 DOWNTO 0) <= out_centrl_ctrl_36(15 DOWNTO 12); + rcmu1_pdof_90i(3 DOWNTO 0) <= out_centrl_ctrl_36(11 DOWNTO 8); + rcmu1_pdof_180i(3 DOWNTO 0) <= out_centrl_ctrl_36(7 DOWNTO 4); + rcmu1_pdof_270i(3 DOWNTO 0) <= out_centrl_ctrl_36(3 DOWNTO 0); + -- CMU1 control register 16 + rcmu1_eye_monitor(7 DOWNTO 0) <= out_centrl_ctrl_37(7 DOWNTO 0); + -- CMU1 control register 17 + rcmu1_reserved(15 DOWNTO 0) <= out_centrl_ctrl_38(15 DOWNTO 0); + -- CMU1 control register 18 + rcmu1_pma_doublewidth_rx <= out_centrl_ctrl_39(15); + rcmu1_pmadwidth_rx <= out_centrl_ctrl_39(14); + rcmu1_test_fastsd <= out_centrl_ctrl_39(13); + rcmu1_fastsd(3 DOWNTO 0) <= out_centrl_ctrl_39(12 DOWNTO 9); + rcmu1_ppmsel(5 DOWNTO 0) <= out_centrl_ctrl_39(8 DOWNTO 3); + rcmu1_force0_freqdet <= out_centrl_ctrl_39(2); + rcmu1_force1_freqdet <= out_centrl_ctrl_39(1); + -- CMU1 control register 19 + rcmu1_dfe_1t(2 DOWNTO 0) <= out_centrl_ctrl_40(15 DOWNTO 13); + rcmu1_dfe_2t(2 DOWNTO 0) <= out_centrl_ctrl_40(12 DOWNTO 10); + -- CMU1 control register 20 + rcmu1_eqa_set(1 DOWNTO 0) <= out_centrl_ctrl_41(13 DOWNTO 12); + rcmu1_eqb_set(1 DOWNTO 0) <= out_centrl_ctrl_41(10 DOWNTO 9); + rcmu1_eqc_set(1 DOWNTO 0) <= out_centrl_ctrl_41(7 DOWNTO 6); + rcmu1_eqd_set(1 DOWNTO 0) <= out_centrl_ctrl_41(4 DOWNTO 3); + rcmu1_eqv_set(1 DOWNTO 0) <= out_centrl_ctrl_41(1 DOWNTO 0); + -- CMU1 control register 21 + rcmu1_d2a_res(5 DOWNTO 0) <= out_centrl_ctrl_42(15 DOWNTO 10); + rcmu1_clk_div2(1 DOWNTO 0) <= out_centrl_ctrl_42(9 DOWNTO 8); + rcmu1_ht_sel <= out_centrl_ctrl_42(7); + rcmu1_fbclk_sel <= out_centrl_ctrl_42(6); + rcmu1_clk_pdb <= out_centrl_ctrl_42(5); + rcmu1_rx_det_pdb <= out_centrl_ctrl_42(4); + rcmu1_iqclk_sel <= out_centrl_ctrl_42(2); + rcmu1_detect_on <= out_centrl_ctrl_42(1); + -- END CMU1 CRAMs + + -- Central PCS CRAMs + -- PCS central channel control register: DTE XS register + rs_lpbk_all <= out_centrl_ctrl_43(14); + rpowerdown <= out_centrl_ctrl_43(11); + -- PCS central channel control register 1 + rtest_bus_centrl_sel(3) <= out_centrl_ctrl_44(15); + rx16_x12_sel_tx <= out_centrl_ctrl_44(14); + rx16_x12_sel_rx <= out_centrl_ctrl_44(13); + rtest_bus_centrl_sel(2 DOWNTO 0) <= out_centrl_ctrl_44(12 DOWNTO 10); + rphfifo_master_sel_tx <= out_centrl_ctrl_44(9); + rphfifo_master_sel_rx <= out_centrl_ctrl_44(8); + rendec_data_sel_tx <= out_centrl_ctrl_44(7); + rendec_data_sel_rx <= out_centrl_ctrl_44(6); + rnenbpin <= out_centrl_ctrl_44(5); + rpllurst <= out_centrl_ctrl_44(4); + rreset <= out_centrl_ctrl_44(3); + rdeskewen <= out_centrl_ctrl_44(2); + rindv_tx <= out_centrl_ctrl_44(1); + rindv_rx <= out_centrl_ctrl_44(0); + -- PCS central channel control register 2 + rfreerun_centrl <= out_centrl_ctrl_45(15); + rcentrl_clk_sel <= out_centrl_ctrl_45(14); + rrefclk_out_div2 <= out_centrl_ctrl_45(13); + rxaui_s2gx_en_rx <= out_centrl_ctrl_45(12); + ralgnopt <= out_centrl_ctrl_45(11); + rdskposdisp <= out_centrl_ctrl_45(10); + rdskchrp <= out_centrl_ctrl_45(9 DOWNTO 0); + -- PCS central channel control register 3 + rxaui_s2gx_en_tx <= out_centrl_ctrl_46(15); + rpcs_centrl_rsvd_cram <= out_centrl_ctrl_46(14 DOWNTO 4); + rmaster_rx <= out_centrl_ctrl_46(3); + rmaster_up_rx <= out_centrl_ctrl_46(2); + rmaster_tx <= out_centrl_ctrl_46(1); + rmaster_up_tx <= out_centrl_ctrl_46(0); + + -- DPRIO registers + + + reg_centrl_inst : cycloneiv_hssi_cmu_dprio_reg_centrl + PORT MAP ( + mdio_rst => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + mdc => mdc, + mbus_in => mbus_in, + serial_mode => serial_mode, + mdio_dis => mdio_dis, + pma_cram_test => pma_cram_test, + ser_shift_load => ser_shift_load, + si => si, + -- CSR input + ext_centrl_ctrl_1 => csr_centrl_in(15 DOWNTO 0), + ext_centrl_ctrl_2 => csr_centrl_in(31 DOWNTO 16), + ext_centrl_ctrl_3 => csr_centrl_in(47 DOWNTO 32), + ext_centrl_ctrl_4 => csr_centrl_in(63 DOWNTO 48), + ext_centrl_ctrl_5 => csr_centrl_in(79 DOWNTO 64), + ext_centrl_ctrl_6 => csr_centrl_in(95 DOWNTO 80), + ext_centrl_ctrl_7 => csr_centrl_in(111 DOWNTO 96), + ext_centrl_ctrl_8 => csr_centrl_in(127 DOWNTO 112), + ext_centrl_ctrl_9 => csr_centrl_in(143 DOWNTO 128), + ext_centrl_ctrl_10 => csr_centrl_in(159 DOWNTO 144), + ext_centrl_ctrl_11 => csr_centrl_in(175 DOWNTO 160), + ext_centrl_ctrl_12 => csr_centrl_in(191 DOWNTO 176), + ext_centrl_ctrl_13 => csr_centrl_in(207 DOWNTO 192), + ext_centrl_ctrl_14 => csr_centrl_in(223 DOWNTO 208), + ext_centrl_ctrl_15 => csr_centrl_in(239 DOWNTO 224), + ext_centrl_ctrl_16 => csr_centrl_in_reserved(15 DOWNTO 0), + ext_centrl_ctrl_17 => csr_centrl_in(255 DOWNTO 240), + ext_centrl_ctrl_18 => csr_centrl_in(271 DOWNTO 256), + ext_centrl_ctrl_19 => csr_centrl_in(287 DOWNTO 272), + ext_centrl_ctrl_20 => csr_centrl_in(303 DOWNTO 288), + ext_centrl_ctrl_21 => csr_centrl_in(319 DOWNTO 304), + ext_centrl_ctrl_22 => csr_centrl_in(335 DOWNTO 320), + ext_centrl_ctrl_23 => csr_centrl_in(351 DOWNTO 336), + ext_centrl_ctrl_24 => csr_centrl_in(367 DOWNTO 352), + ext_centrl_ctrl_25 => csr_centrl_in(383 DOWNTO 368), + ext_centrl_ctrl_26 => csr_centrl_in(399 DOWNTO 384), + ext_centrl_ctrl_27 => csr_centrl_in(415 DOWNTO 400), + ext_centrl_ctrl_28 => csr_centrl_in(431 DOWNTO 416), + ext_centrl_ctrl_29 => csr_centrl_in(447 DOWNTO 432), + ext_centrl_ctrl_30 => csr_centrl_in(463 DOWNTO 448), + ext_centrl_ctrl_31 => csr_centrl_in(479 DOWNTO 464), + ext_centrl_ctrl_32 => csr_centrl_in(495 DOWNTO 480), + ext_centrl_ctrl_33 => csr_centrl_in(511 DOWNTO 496), + ext_centrl_ctrl_34 => csr_centrl_in(527 DOWNTO 512), + ext_centrl_ctrl_35 => csr_centrl_in(543 DOWNTO 528), + ext_centrl_ctrl_36 => csr_centrl_in(559 DOWNTO 544), + ext_centrl_ctrl_37 => csr_centrl_in_reserved(31 DOWNTO 16), + ext_centrl_ctrl_38 => csr_centrl_in(575 DOWNTO 560), + ext_centrl_ctrl_39 => csr_centrl_in(591 DOWNTO 576), + ext_centrl_ctrl_40 => csr_centrl_in(607 DOWNTO 592), + ext_centrl_ctrl_41 => csr_centrl_in(623 DOWNTO 608), + ext_centrl_ctrl_42 => csr_centrl_in(639 DOWNTO 624), + ext_centrl_ctrl_43 => csr_centrl_in(655 DOWNTO 640), + ext_centrl_ctrl_44 => csr_centrl_in(671 DOWNTO 656), + ext_centrl_ctrl_45 => csr_centrl_in(687 DOWNTO 672), + ext_centrl_ctrl_46 => csr_centrl_in(703 DOWNTO 688), + targ_addr_ctrl_1 => targ_addr_ctrl_1, + targ_addr_ctrl_2 => targ_addr_ctrl_2, + targ_addr_ctrl_3 => targ_addr_ctrl_3, + targ_addr_ctrl_4 => targ_addr_ctrl_4, + targ_addr_ctrl_5 => targ_addr_ctrl_5, + targ_addr_ctrl_6 => targ_addr_ctrl_6, + targ_addr_ctrl_7 => targ_addr_ctrl_7, + targ_addr_ctrl_8 => targ_addr_ctrl_8, + targ_addr_ctrl_9 => targ_addr_ctrl_9, + targ_addr_ctrl_10 => targ_addr_ctrl_10, + targ_addr_ctrl_11 => targ_addr_ctrl_11, + targ_addr_ctrl_12 => targ_addr_ctrl_12, + targ_addr_ctrl_13 => targ_addr_ctrl_13, + targ_addr_ctrl_14 => targ_addr_ctrl_14, + targ_addr_ctrl_15 => targ_addr_ctrl_15, + targ_addr_ctrl_16 => targ_addr_ctrl_16, + targ_addr_ctrl_17 => targ_addr_ctrl_17, + targ_addr_ctrl_18 => targ_addr_ctrl_18, + targ_addr_ctrl_19 => targ_addr_ctrl_19, + targ_addr_ctrl_20 => targ_addr_ctrl_20, + targ_addr_ctrl_21 => targ_addr_ctrl_21, + targ_addr_ctrl_22 => targ_addr_ctrl_22, + targ_addr_ctrl_23 => targ_addr_ctrl_23, + targ_addr_ctrl_24 => targ_addr_ctrl_24, + targ_addr_ctrl_25 => targ_addr_ctrl_25, + targ_addr_ctrl_26 => targ_addr_ctrl_26, + targ_addr_ctrl_27 => targ_addr_ctrl_27, + targ_addr_ctrl_28 => targ_addr_ctrl_28, + targ_addr_ctrl_29 => targ_addr_ctrl_29, + targ_addr_ctrl_30 => targ_addr_ctrl_30, + targ_addr_ctrl_31 => targ_addr_ctrl_31, + targ_addr_ctrl_32 => targ_addr_ctrl_32, + targ_addr_ctrl_33 => targ_addr_ctrl_33, + targ_addr_ctrl_34 => targ_addr_ctrl_34, + targ_addr_ctrl_35 => targ_addr_ctrl_35, + targ_addr_ctrl_36 => targ_addr_ctrl_36, + targ_addr_ctrl_37 => targ_addr_ctrl_37, + targ_addr_ctrl_38 => targ_addr_ctrl_38, + targ_addr_ctrl_39 => targ_addr_ctrl_39, + targ_addr_ctrl_40 => targ_addr_ctrl_40, + targ_addr_ctrl_41 => targ_addr_ctrl_41, + targ_addr_ctrl_42 => targ_addr_ctrl_42, + targ_addr_ctrl_43 => targ_addr_ctrl_43, + targ_addr_ctrl_44 => targ_addr_ctrl_44, + targ_addr_ctrl_45 => targ_addr_ctrl_45, + targ_addr_ctrl_46 => targ_addr_ctrl_46, + -- DPRIO register output + out_centrl_ctrl_1 => out_centrl_ctrl_1, + out_centrl_ctrl_2 => out_centrl_ctrl_2, + out_centrl_ctrl_3 => out_centrl_ctrl_3, + out_centrl_ctrl_4 => out_centrl_ctrl_4, + out_centrl_ctrl_5 => out_centrl_ctrl_5, + out_centrl_ctrl_6 => out_centrl_ctrl_6, + out_centrl_ctrl_7 => out_centrl_ctrl_7, + out_centrl_ctrl_8 => out_centrl_ctrl_8, + out_centrl_ctrl_9 => out_centrl_ctrl_9, + out_centrl_ctrl_10 => out_centrl_ctrl_10, + out_centrl_ctrl_11 => out_centrl_ctrl_11, + out_centrl_ctrl_12 => out_centrl_ctrl_12, + out_centrl_ctrl_13 => out_centrl_ctrl_13, + out_centrl_ctrl_14 => out_centrl_ctrl_14, + out_centrl_ctrl_15 => out_centrl_ctrl_15, + out_centrl_ctrl_16 => out_centrl_ctrl_16, + out_centrl_ctrl_17 => out_centrl_ctrl_17, + out_centrl_ctrl_18 => out_centrl_ctrl_18, + out_centrl_ctrl_19 => out_centrl_ctrl_19, + out_centrl_ctrl_20 => out_centrl_ctrl_20, + out_centrl_ctrl_21 => out_centrl_ctrl_21, + out_centrl_ctrl_22 => out_centrl_ctrl_22, + out_centrl_ctrl_23 => out_centrl_ctrl_23, + out_centrl_ctrl_24 => out_centrl_ctrl_24, + out_centrl_ctrl_25 => out_centrl_ctrl_25, + out_centrl_ctrl_26 => out_centrl_ctrl_26, + out_centrl_ctrl_27 => out_centrl_ctrl_27, + out_centrl_ctrl_28 => out_centrl_ctrl_28, + out_centrl_ctrl_29 => out_centrl_ctrl_29, + out_centrl_ctrl_30 => out_centrl_ctrl_30, + out_centrl_ctrl_31 => out_centrl_ctrl_31, + out_centrl_ctrl_32 => out_centrl_ctrl_32, + out_centrl_ctrl_33 => out_centrl_ctrl_33, + out_centrl_ctrl_34 => out_centrl_ctrl_34, + out_centrl_ctrl_35 => out_centrl_ctrl_35, + out_centrl_ctrl_36 => out_centrl_ctrl_36, + out_centrl_ctrl_37 => out_centrl_ctrl_37, + out_centrl_ctrl_38 => out_centrl_ctrl_38, + out_centrl_ctrl_39 => out_centrl_ctrl_39, + out_centrl_ctrl_40 => out_centrl_ctrl_40, + out_centrl_ctrl_41 => out_centrl_ctrl_41, + out_centrl_ctrl_42 => out_centrl_ctrl_42, + out_centrl_ctrl_43 => out_centrl_ctrl_43, + out_centrl_ctrl_44 => out_centrl_ctrl_44, + out_centrl_ctrl_45 => out_centrl_ctrl_45, + out_centrl_ctrl_46 => out_centrl_ctrl_46, + so => so_xhdl1 + ); + + -- MBUS_OUT muxing for central channel + + + mbus_mux_inst : cycloneiv_hssi_cmu_dprio_centrl_bus_out_mux + PORT MAP ( + centrl_ctrl_in1 => out_centrl_ctrl_1, + centrl_ctrl_in2 => out_centrl_ctrl_2, + centrl_ctrl_in3 => out_centrl_ctrl_3, + centrl_ctrl_in4 => out_centrl_ctrl_4, + centrl_ctrl_in5 => out_centrl_ctrl_5, + centrl_ctrl_in6 => out_centrl_ctrl_6, + centrl_ctrl_in7 => out_centrl_ctrl_7, + centrl_ctrl_in8 => out_centrl_ctrl_8, + centrl_ctrl_in9 => out_centrl_ctrl_9, + centrl_ctrl_in10 => out_centrl_ctrl_10, + centrl_ctrl_in11 => out_centrl_ctrl_11, + centrl_ctrl_in12 => out_centrl_ctrl_12, + centrl_ctrl_in13 => out_centrl_ctrl_13, + centrl_ctrl_in14 => out_centrl_ctrl_14, + centrl_ctrl_in15 => out_centrl_ctrl_15, + centrl_ctrl_in16 => out_centrl_ctrl_16, + centrl_ctrl_in17 => out_centrl_ctrl_17, + centrl_ctrl_in18 => out_centrl_ctrl_18, + centrl_ctrl_in19 => out_centrl_ctrl_19, + centrl_ctrl_in20 => out_centrl_ctrl_20, + centrl_ctrl_in21 => out_centrl_ctrl_21, + centrl_ctrl_in22 => out_centrl_ctrl_22, + centrl_ctrl_in23 => out_centrl_ctrl_23, + centrl_ctrl_in24 => out_centrl_ctrl_24, + centrl_ctrl_in25 => out_centrl_ctrl_25, + centrl_ctrl_in26 => out_centrl_ctrl_26, + centrl_ctrl_in27 => out_centrl_ctrl_27, + centrl_ctrl_in28 => out_centrl_ctrl_28, + centrl_ctrl_in29 => out_centrl_ctrl_29, + centrl_ctrl_in30 => out_centrl_ctrl_30, + centrl_ctrl_in31 => out_centrl_ctrl_31, + centrl_ctrl_in32 => out_centrl_ctrl_32, + centrl_ctrl_in33 => out_centrl_ctrl_33, + centrl_ctrl_in34 => out_centrl_ctrl_34, + centrl_ctrl_in35 => out_centrl_ctrl_35, + centrl_ctrl_in36 => out_centrl_ctrl_36, + centrl_ctrl_in37 => out_centrl_ctrl_37, + centrl_ctrl_in38 => out_centrl_ctrl_38, + centrl_ctrl_in39 => out_centrl_ctrl_39, + centrl_ctrl_in40 => out_centrl_ctrl_40, + centrl_ctrl_in41 => out_centrl_ctrl_41, + centrl_ctrl_in42 => out_centrl_ctrl_42, + centrl_ctrl_in43 => out_centrl_ctrl_43, + centrl_ctrl_in44 => out_centrl_ctrl_44, + centrl_ctrl_in45 => out_centrl_ctrl_45, + centrl_ctrl_in46 => out_centrl_ctrl_46, + hw_address_ctrl_in1 => targ_addr_ctrl_1, + hw_address_ctrl_in2 => targ_addr_ctrl_2, + hw_address_ctrl_in3 => targ_addr_ctrl_3, + hw_address_ctrl_in4 => targ_addr_ctrl_4, + hw_address_ctrl_in5 => targ_addr_ctrl_5, + hw_address_ctrl_in6 => targ_addr_ctrl_6, + hw_address_ctrl_in7 => targ_addr_ctrl_7, + hw_address_ctrl_in8 => targ_addr_ctrl_8, + hw_address_ctrl_in9 => targ_addr_ctrl_9, + hw_address_ctrl_in10 => targ_addr_ctrl_10, + hw_address_ctrl_in11 => targ_addr_ctrl_11, + hw_address_ctrl_in12 => targ_addr_ctrl_12, + hw_address_ctrl_in13 => targ_addr_ctrl_13, + hw_address_ctrl_in14 => targ_addr_ctrl_14, + hw_address_ctrl_in15 => targ_addr_ctrl_15, + hw_address_ctrl_in16 => targ_addr_ctrl_16, + hw_address_ctrl_in17 => targ_addr_ctrl_17, + hw_address_ctrl_in18 => targ_addr_ctrl_18, + hw_address_ctrl_in19 => targ_addr_ctrl_19, + hw_address_ctrl_in20 => targ_addr_ctrl_20, + hw_address_ctrl_in21 => targ_addr_ctrl_21, + hw_address_ctrl_in22 => targ_addr_ctrl_22, + hw_address_ctrl_in23 => targ_addr_ctrl_23, + hw_address_ctrl_in24 => targ_addr_ctrl_24, + hw_address_ctrl_in25 => targ_addr_ctrl_25, + hw_address_ctrl_in26 => targ_addr_ctrl_26, + hw_address_ctrl_in27 => targ_addr_ctrl_27, + hw_address_ctrl_in28 => targ_addr_ctrl_28, + hw_address_ctrl_in29 => targ_addr_ctrl_29, + hw_address_ctrl_in30 => targ_addr_ctrl_30, + hw_address_ctrl_in31 => targ_addr_ctrl_31, + hw_address_ctrl_in32 => targ_addr_ctrl_32, + hw_address_ctrl_in33 => targ_addr_ctrl_33, + hw_address_ctrl_in34 => targ_addr_ctrl_34, + hw_address_ctrl_in35 => targ_addr_ctrl_35, + hw_address_ctrl_in36 => targ_addr_ctrl_36, + hw_address_ctrl_in37 => targ_addr_ctrl_37, + hw_address_ctrl_in38 => targ_addr_ctrl_38, + hw_address_ctrl_in39 => targ_addr_ctrl_39, + hw_address_ctrl_in40 => targ_addr_ctrl_40, + hw_address_ctrl_in41 => targ_addr_ctrl_41, + hw_address_ctrl_in42 => targ_addr_ctrl_42, + hw_address_ctrl_in43 => targ_addr_ctrl_43, + hw_address_ctrl_in44 => targ_addr_ctrl_44, + hw_address_ctrl_in45 => targ_addr_ctrl_45, + hw_address_ctrl_in46 => targ_addr_ctrl_46, + reg_addr => reg_addr, + centrl_ctrl_out => mbus_out_xhdl0 + ); + +END ARCHITECTURE trans; + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; + +ENTITY cycloneiv_hssi_cmu_dprio_map_index IS + GENERIC ( + -- Simulation Only + clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1"; + + pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll0_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll0_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll0_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll0_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll0_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll0_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll1_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll1_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll1_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll1_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll1_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll1_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll2_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll2_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll2_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll2_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll2_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll2_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll3_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll3_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll3_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll3_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll3_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll3_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll4_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll4_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll4_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll4_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll4_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll4_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll5_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll5_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll5_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll5_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll5_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll5_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + + pll0_logical_to_physical_mapping : INTEGER := 0; + pll1_logical_to_physical_mapping : INTEGER := 1; + pll2_logical_to_physical_mapping : INTEGER := 2; + pll3_logical_to_physical_mapping : INTEGER := 3; + pll4_logical_to_physical_mapping : INTEGER := 4; + pll5_logical_to_physical_mapping : INTEGER := 5; + + refclk_divider0_logical_to_physical_mapping : INTEGER := 0; + refclk_divider1_logical_to_physical_mapping : INTEGER := 1; + + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + rx4_logical_to_physical_mapping : INTEGER := 4; + rx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + tx4_logical_to_physical_mapping : INTEGER := 4; + tx5_logical_to_physical_mapping : INTEGER := 5; + + + tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport" + ); + PORT ( + pll0_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll0_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll1_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll1_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll2_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll2_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll3_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll3_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll4_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll4_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll5_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll5_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + txpma0_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma0_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma0_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma0_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma1_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma1_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma1_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma1_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma2_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma2_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma2_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma2_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma3_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma3_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma3_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma3_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma4_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma4_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma4_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma4_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma5_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma5_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma5_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma5_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + clkdiv0_init_inclk_select : IN STD_LOGIC; + clkdiv0_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv0_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv0_dp_inclk_select : OUT STD_LOGIC; + clkdiv1_init_inclk_select : IN STD_LOGIC; + clkdiv1_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv1_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv1_dp_inclk_select : OUT STD_LOGIC; + clkdiv2_init_inclk_select : IN STD_LOGIC; + clkdiv2_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv2_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv2_dp_inclk_select : OUT STD_LOGIC; + clkdiv3_init_inclk_select : IN STD_LOGIC; + clkdiv3_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv3_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv3_dp_inclk_select : OUT STD_LOGIC; + clkdiv4_init_inclk_select : IN STD_LOGIC; + clkdiv4_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv4_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv4_dp_inclk_select : OUT STD_LOGIC; + clkdiv5_init_inclk_select : IN STD_LOGIC; + clkdiv5_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv5_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv5_dp_inclk_select : OUT STD_LOGIC + ); +END cycloneiv_hssi_cmu_dprio_map_index; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_map_index IS + SIGNAL gnd_wire : STD_LOGIC := '0'; + SIGNAL vcc_wire : STD_LOGIC := '1'; + +-- types --------------------------------------------------------------- +type DPRIO_REG_ARRAY_OF_INT is array (natural range <>) of integer; +type DPRIO_REG_ARRAY_OF_VEC is array (natural range <>) of std_logic_vector(4 downto 0); +type DPRIO_REG_ARRAY_OF_VEC1 is array (natural range <>) of std_logic; +type DPRIO_REG_ARRAY_OF_VEC2 is array (natural range <>) of std_logic_vector(1 downto 0); + +-- common functions ---------------------------------------------------- +FUNCTION dprio_reg_to_int(arg : IN STD_LOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER; +BEGIN + result := 0; + FOR i IN arg'RANGE LOOP + IF arg(i) = '1' THEN + result := result + 2**i; + END IF; + END LOOP; + RETURN result; +END dprio_reg_to_int; + +--------------------------------------------------------------------------- +-- PLL clock selection ---------------------------------------------------- +--------------------------------------------------------------------------- + +constant PLL_CLOCK_SELECT_CLKREFCLK0 : INTEGER := 0; +constant PLL_CLOCK_SELECT_CLKREFCLK1 : INTEGER := 1; +constant PLL_CLOCK_SELECT_IQ2 : INTEGER := 2; +constant PLL_CLOCK_SELECT_IQ3 : INTEGER := 3; +constant PLL_CLOCK_SELECT_IQ4 : INTEGER := 4; +constant PLL_CLOCK_SELECT_IQ5 : INTEGER := 5; +constant PLL_CLOCK_SELECT_IQ6 : INTEGER := 6; +constant PLL_CLOCK_SELECT_IQ7 : INTEGER := 7; +constant PLL_CLOCK_SELECT_PLD_CLK : INTEGER := 8; +constant PLL_CLOCK_SELECT_GPLL_CLK : INTEGER := 9; +constant PLL_CLOCK_SELECT_ERR : INTEGER := 10; + +FUNCTION convert_pll_clock_cram_to_phyport ( + rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pldiq : IN STD_LOGIC_VECTOR(1 DOWNTO 0)) RETURN INTEGER IS + + VARIABLE res : INTEGER := PLL_CLOCK_SELECT_ERR; + VARIABLE tmp_in : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; +BEGIN + tmp_in := rrefclk_sel & pldiq; + if (rrefclk_sel = "00") THEN + res := PLL_CLOCK_SELECT_CLKREFCLK0; + ELSIF (rrefclk_sel = "01") THEN + res := PLL_CLOCK_SELECT_CLKREFCLK1; + ELSE + CASE tmp_in IS + WHEN "1000" => res := PLL_CLOCK_SELECT_IQ2; + WHEN "1001" => res := PLL_CLOCK_SELECT_IQ3; + WHEN "1010" => res := PLL_CLOCK_SELECT_IQ4; + WHEN "1100" => res := PLL_CLOCK_SELECT_IQ5; + WHEN "1101" => res := PLL_CLOCK_SELECT_IQ6; + WHEN "1110" => res := PLL_CLOCK_SELECT_IQ7; + WHEN "1011" => res := PLL_CLOCK_SELECT_PLD_CLK; + WHEN "1111" => res := PLL_CLOCK_SELECT_GPLL_CLK; + WHEN OTHERS => res := PLL_CLOCK_SELECT_ERR; + END CASE; + END IF; + + RETURN res; +END convert_pll_clock_cram_to_phyport; + +-- input is at most 15 characters +FUNCTION convert_pll_phyport_str_to_phyport_enum ( + phyport_str : IN STRING) RETURN INTEGER IS + VARIABLE res : INTEGER := 0; +BEGIN + IF (phyport_str = "iq2") THEN + res := PLL_CLOCK_SELECT_IQ2; + ELSIF (phyport_str = "iq3") THEN + res := PLL_CLOCK_SELECT_IQ3; + ELSIF (phyport_str = "iq4") THEN + res := PLL_CLOCK_SELECT_IQ4; + ELSIF (phyport_str = "iq5") THEN + res := PLL_CLOCK_SELECT_IQ5; + ELSIF (phyport_str = "iq6") THEN + res := PLL_CLOCK_SELECT_IQ6; + ELSIF (phyport_str = "iq7") THEN + res := PLL_CLOCK_SELECT_IQ7; + ELSIF (phyport_str = "refclk0" OR phyport_str = "clkrefclk0") THEN + res := PLL_CLOCK_SELECT_CLKREFCLK0; + ELSIF (phyport_str = "refclk1" OR phyport_str = "clkrefclk1") THEN + res := PLL_CLOCK_SELECT_CLKREFCLK1; + ELSIF (phyport_str = "pld_clk") THEN + res := PLL_CLOCK_SELECT_PLD_CLK; + ELSIF (phyport_str = "gpll_clk") THEN + res := PLL_CLOCK_SELECT_GPLL_CLK; + ELSE -- like "none" + res := PLL_CLOCK_SELECT_ERR; + END IF; + + RETURN res; +END convert_pll_phyport_str_to_phyport_enum; + +-- common to all PLL channels +SIGNAL pll_clock_phyport_to_cram : DPRIO_REG_ARRAY_OF_VEC (10 DOWNTO 0) := (OTHERS => "00000"); + +-- READ --------------- ch0 +SIGNAL pll0_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (9 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_pll0_clock_select_vec : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll0_clock_select : INTEGER := 0; +SIGNAL pll0_clock_phyport : INTEGER := 0; +SIGNAL pll0_clock_cram : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll0_clock_cram_phy : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); + +-- Write --------------- ch0 +SIGNAL pll0_clock_phyport_out : INTEGER := 0; +SIGNAL pll0_clock_phyport_out_logic : INTEGER := 0; +SIGNAL pll0_clock_select_out_logic : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll0_clock_select_out : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + +-- READ --------------- ch1 +SIGNAL pll1_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (9 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_pll1_clock_select_vec : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll1_clock_select : INTEGER := 0; +SIGNAL pll1_clock_phyport : INTEGER := 0; +SIGNAL pll1_clock_cram : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll1_clock_cram_phy : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); + +-- Write --------------- ch1 +SIGNAL pll1_clock_phyport_out : INTEGER := 0; +SIGNAL pll1_clock_phyport_out_logic : INTEGER := 0; +SIGNAL pll1_clock_select_out_logic : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll1_clock_select_out : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + +-- READ --------------- ch2 +SIGNAL pll2_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (9 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_pll2_clock_select_vec : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll2_clock_select : INTEGER := 0; +SIGNAL pll2_clock_phyport : INTEGER := 0; +SIGNAL pll2_clock_cram : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll2_clock_cram_phy : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); + +-- Write --------------- ch2 +SIGNAL pll2_clock_phyport_out : INTEGER := 0; +SIGNAL pll2_clock_phyport_out_logic : INTEGER := 0; +SIGNAL pll2_clock_select_out_logic : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll2_clock_select_out : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + +-- READ --------------- ch3 +SIGNAL pll3_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (9 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_pll3_clock_select_vec : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll3_clock_select : INTEGER := 0; +SIGNAL pll3_clock_phyport : INTEGER := 0; +SIGNAL pll3_clock_cram : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll3_clock_cram_phy : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); + +-- Write --------------- ch3 +SIGNAL pll3_clock_phyport_out : INTEGER := 0; +SIGNAL pll3_clock_phyport_out_logic : INTEGER := 0; +SIGNAL pll3_clock_select_out_logic : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll3_clock_select_out : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + +-- READ --------------- ch4 +SIGNAL pll4_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (9 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_pll4_clock_select_vec : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll4_clock_select : INTEGER := 0; +SIGNAL pll4_clock_phyport : INTEGER := 0; +SIGNAL pll4_clock_cram : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll4_clock_cram_phy : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); + +-- Write --------------- ch4 +SIGNAL pll4_clock_phyport_out : INTEGER := 0; +SIGNAL pll4_clock_phyport_out_logic : INTEGER := 0; +SIGNAL pll4_clock_select_out_logic : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll4_clock_select_out : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + +-- READ --------------- ch5 +SIGNAL pll5_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (9 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_pll5_clock_select_vec : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll5_clock_select : INTEGER := 0; +SIGNAL pll5_clock_phyport : INTEGER := 0; +SIGNAL pll5_clock_cram : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll5_clock_cram_phy : STD_LOGIC_VECTOR (4 DOWNTO 0) := (OTHERS => '0'); + +-- Write --------------- ch5 +SIGNAL pll5_clock_phyport_out : INTEGER := 0; +SIGNAL pll5_clock_phyport_out_logic : INTEGER := 0; +SIGNAL pll5_clock_select_out_logic : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); +SIGNAL pll5_clock_select_out : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + +--------------------------------------------------------------------------- +-- TX PMA selection ------------------------------------------------------- +--------------------------------------------------------------------------- + +constant TXPMA_CLKIN_SELECT_X1 : INTEGER := 0; +constant TXPMA_CLKIN_SELECT_X4 : INTEGER := 1; +constant TXPMA_CLKIN_SELECT_XN_TOP : INTEGER := 2; +constant TXPMA_CLKIN_SELECT_XN_BOTTOM : INTEGER := 3; +constant TXPMA_CLKIN_SELECT_HT : INTEGER := 4; +constant TXPMA_CLKIN_SELECT_ERR : INTEGER := 7; + +FUNCTION convert_txpma_clock_cram_to_phyport ( + rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0)) RETURN INTEGER IS + VARIABLE res : INTEGER := 0; +BEGIN + CASE rcgb_x_en IS + WHEN "00" => res := TXPMA_CLKIN_SELECT_X1; + WHEN "01" => res := TXPMA_CLKIN_SELECT_X4; + WHEN "10" => res := TXPMA_CLKIN_SELECT_XN_TOP; + WHEN "11" => res := TXPMA_CLKIN_SELECT_XN_BOTTOM; + WHEN OTHERS => res := TXPMA_CLKIN_SELECT_ERR; + END CASE; + + RETURN res; +END convert_txpma_clock_cram_to_phyport; + +-- input is at most 20 characters +FUNCTION convert_txpma_phyport_str_to_phyport_enum ( + phyport_str : IN STRING ) RETURN INTEGER IS + + VARIABLE res : INTEGER := 0; +BEGIN + IF (phyport_str = "x1" OR phyport_str = "X1") THEN + res := TXPMA_CLKIN_SELECT_X1; + ELSIF (phyport_str = "x4" OR phyport_str = "X4") THEN + res := TXPMA_CLKIN_SELECT_X4; + ELSIF (phyport_str = "xn_top" OR phyport_str = "XN_TOP") THEN + res := TXPMA_CLKIN_SELECT_XN_TOP; + ELSIF (phyport_str = "xn_bottom" OR phyport_str = "XN_BOTTOM") THEN + res := TXPMA_CLKIN_SELECT_XN_BOTTOM; + ELSIF (phyport_str = "hypertransport" OR phyport_str = "HYPERTRANSPORT") THEN + res := TXPMA_CLKIN_SELECT_HT; + ELSE -- like "none" + res := TXPMA_CLKIN_SELECT_ERR; + END IF; + + RETURN res; +END convert_txpma_phyport_str_to_phyport_enum; + +-- common to all channels ------------------------------------------------ + -- phyport to cram - include error string +SIGNAL txpma_clock_phyport_to_cram : DPRIO_REG_ARRAY_OF_VEC2 (7 DOWNTO 0) := (OTHERS => "00"); + +-- READ --------------- ch0 + -- map table - index to phyport integer +SIGNAL txpma0_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (4 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_txpma0_clock_select_vec : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma0_clock_select : INTEGER := 0; +SIGNAL txpma0_clock_phyport : INTEGER := 0; +SIGNAL txpma0_clock_cram : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +SIGNAL txpma0_clock_cram_phy : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +-- Write --------------- ch0 +SIGNAL txpma0_clock_phyport_out : INTEGER := 0; +SIGNAL txpma0_clock_phyport_out_logic : INTEGER := 0; +SIGNAL txpma0_clock_select_out_logic : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma0_clock_select_out : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; + +-- READ --------------- ch1 + -- map table - index to phyport integer +SIGNAL txpma1_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (4 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_txpma1_clock_select_vec : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma1_clock_select : INTEGER := 0; +SIGNAL txpma1_clock_phyport : INTEGER := 0; +SIGNAL txpma1_clock_cram : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +SIGNAL txpma1_clock_cram_phy : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +-- Write --------------- ch1 +SIGNAL txpma1_clock_phyport_out : INTEGER := 0; +SIGNAL txpma1_clock_phyport_out_logic : INTEGER := 0; +SIGNAL txpma1_clock_select_out_logic : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma1_clock_select_out : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; + +-- READ --------------- ch2 + -- map table - index to phyport integer +SIGNAL txpma2_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (4 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_txpma2_clock_select_vec : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma2_clock_select : INTEGER := 0; +SIGNAL txpma2_clock_phyport : INTEGER := 0; +SIGNAL txpma2_clock_cram : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +SIGNAL txpma2_clock_cram_phy : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +-- Write --------------- ch2 +SIGNAL txpma2_clock_phyport_out : INTEGER := 0; +SIGNAL txpma2_clock_phyport_out_logic : INTEGER := 0; +SIGNAL txpma2_clock_select_out_logic : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma2_clock_select_out : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; + +-- READ --------------- ch3 + -- map table - index to phyport integer +SIGNAL txpma3_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (4 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_txpma3_clock_select_vec : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma3_clock_select : INTEGER := 0; +SIGNAL txpma3_clock_phyport : INTEGER := 0; +SIGNAL txpma3_clock_cram : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +SIGNAL txpma3_clock_cram_phy : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +-- Write --------------- ch3 +SIGNAL txpma3_clock_phyport_out : INTEGER := 0; +SIGNAL txpma3_clock_phyport_out_logic : INTEGER := 0; +SIGNAL txpma3_clock_select_out_logic : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma3_clock_select_out : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; + +-- READ --------------- ch4 + -- map table - index to phyport integer +SIGNAL txpma4_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (4 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_txpma4_clock_select_vec : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma4_clock_select : INTEGER := 0; +SIGNAL txpma4_clock_phyport : INTEGER := 0; +SIGNAL txpma4_clock_cram : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +SIGNAL txpma4_clock_cram_phy : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +-- Write --------------- ch4 +SIGNAL txpma4_clock_phyport_out : INTEGER := 0; +SIGNAL txpma4_clock_phyport_out_logic : INTEGER := 0; +SIGNAL txpma4_clock_select_out_logic : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma4_clock_select_out : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; + +-- READ --------------- ch5 + -- map table - index to phyport integer +SIGNAL txpma5_clock_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (4 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_txpma5_clock_select_vec : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma5_clock_select : INTEGER := 0; +SIGNAL txpma5_clock_phyport : INTEGER := 0; +SIGNAL txpma5_clock_cram : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +SIGNAL txpma5_clock_cram_phy : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; +-- Write --------------- ch5 +SIGNAL txpma5_clock_phyport_out : INTEGER := 0; +SIGNAL txpma5_clock_phyport_out_logic : INTEGER := 0; +SIGNAL txpma5_clock_select_out_logic : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; +SIGNAL txpma5_clock_select_out : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; + +--------------------------------------------------------------------------- +-- PLL0/PLL1 selection ---------------------------------------------------- +--------------------------------------------------------------------------- + +constant CLKDIV_INCLK_SELECT_PLL0 : INTEGER := 0; +constant CLKDIV_INCLK_SELECT_PLL1 : INTEGER := 1; +constant CLKDIV_INCLK_SELECT_ERR : INTEGER := 2; + +FUNCTION convert_clkdiv_pll_cram_to_phyport ( + rcgb_cmu_sel : IN STD_LOGIC) RETURN INTEGER IS + + VARIABLE res : INTEGER := 0; +BEGIN + CASE rcgb_cmu_sel IS + WHEN '0' => res := CLKDIV_INCLK_SELECT_PLL0; + WHEN '1' => res := CLKDIV_INCLK_SELECT_PLL1; + WHEN OTHERS => res := CLKDIV_INCLK_SELECT_ERR; + END CASE; + + RETURN res; +END convert_clkdiv_pll_cram_to_phyport; + +FUNCTION convert_clkdiv_pll_phyport_str_to_phyport_enum( + phyport_str : IN STRING) RETURN INTEGER IS + + VARIABLE res : INTEGER := 0; +BEGIN + IF (phyport_str = "pll0") THEN + res := CLKDIV_INCLK_SELECT_PLL0; + ELSIF (phyport_str = "pll1") THEN + res := CLKDIV_INCLK_SELECT_PLL1; + ELSE -- like "none" + res := CLKDIV_INCLK_SELECT_ERR; + END IF; + + RETURN res; + +END convert_clkdiv_pll_phyport_str_to_phyport_enum; + +-- common to all PLL channels +SIGNAL clkdiv_pll_phyport_to_cram : DPRIO_REG_ARRAY_OF_VEC1 (2 DOWNTO 0) := (OTHERS => '0'); + +-- READ --------------- ch0 +SIGNAL clkdiv0_pll_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (1 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_clkdiv0_pll_select : STD_LOGIC := '0'; +SIGNAL clkdiv0_pll_select : INTEGER := 0; +SIGNAL clkdiv0_pll_phyport : INTEGER := 0; +SIGNAL clkdiv0_pll_cram : STD_LOGIC := '0'; +SIGNAL clkdiv0_pll_cram_phy : STD_LOGIC := '0'; +-- Write --------------- ch0 +SIGNAL clkdiv0_pll_phyport_out : INTEGER := 0; +SIGNAL clkdiv0_pll_phyport_out_logic : INTEGER := 0; +SIGNAL clkdiv0_pll_select_out_logic : STD_LOGIC := '0'; +SIGNAL clkdiv0_pll_select_out : STD_LOGIC := '0'; + +-- READ --------------- ch1 +SIGNAL clkdiv1_pll_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (1 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_clkdiv1_pll_select : STD_LOGIC := '0'; +SIGNAL clkdiv1_pll_select : INTEGER := 0; +SIGNAL clkdiv1_pll_phyport : INTEGER := 0; +SIGNAL clkdiv1_pll_cram : STD_LOGIC := '0'; +SIGNAL clkdiv1_pll_cram_phy : STD_LOGIC := '0'; +-- Write --------------- ch1 +SIGNAL clkdiv1_pll_phyport_out : INTEGER := 0; +SIGNAL clkdiv1_pll_phyport_out_logic : INTEGER := 0; +SIGNAL clkdiv1_pll_select_out_logic : STD_LOGIC := '0'; +SIGNAL clkdiv1_pll_select_out : STD_LOGIC := '0'; + +-- READ --------------- ch2 +SIGNAL clkdiv2_pll_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (1 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_clkdiv2_pll_select : STD_LOGIC := '0'; +SIGNAL clkdiv2_pll_select : INTEGER := 0; +SIGNAL clkdiv2_pll_phyport : INTEGER := 0; +SIGNAL clkdiv2_pll_cram : STD_LOGIC := '0'; +SIGNAL clkdiv2_pll_cram_phy : STD_LOGIC := '0'; +-- Write --------------- ch2 +SIGNAL clkdiv2_pll_phyport_out : INTEGER := 0; +SIGNAL clkdiv2_pll_phyport_out_logic : INTEGER := 0; +SIGNAL clkdiv2_pll_select_out_logic : STD_LOGIC := '0'; +SIGNAL clkdiv2_pll_select_out : STD_LOGIC := '0'; + +-- READ --------------- ch3 +SIGNAL clkdiv3_pll_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (1 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_clkdiv3_pll_select : STD_LOGIC := '0'; +SIGNAL clkdiv3_pll_select : INTEGER := 0; +SIGNAL clkdiv3_pll_phyport : INTEGER := 0; +SIGNAL clkdiv3_pll_cram : STD_LOGIC := '0'; +SIGNAL clkdiv3_pll_cram_phy : STD_LOGIC := '0'; +-- Write --------------- ch3 +SIGNAL clkdiv3_pll_phyport_out : INTEGER := 0; +SIGNAL clkdiv3_pll_phyport_out_logic : INTEGER := 0; +SIGNAL clkdiv3_pll_select_out_logic : STD_LOGIC := '0'; +SIGNAL clkdiv3_pll_select_out : STD_LOGIC := '0'; + +-- READ --------------- ch4 +SIGNAL clkdiv4_pll_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (1 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_clkdiv4_pll_select : STD_LOGIC := '0'; +SIGNAL clkdiv4_pll_select : INTEGER := 0; +SIGNAL clkdiv4_pll_phyport : INTEGER := 0; +SIGNAL clkdiv4_pll_cram : STD_LOGIC := '0'; +SIGNAL clkdiv4_pll_cram_phy : STD_LOGIC := '0'; +-- Write --------------- ch4 +SIGNAL clkdiv4_pll_phyport_out : INTEGER := 0; +SIGNAL clkdiv4_pll_phyport_out_logic : INTEGER := 0; +SIGNAL clkdiv4_pll_select_out_logic : STD_LOGIC := '0'; +SIGNAL clkdiv4_pll_select_out : STD_LOGIC := '0'; + +-- READ --------------- ch5 +SIGNAL clkdiv5_pll_index_to_phyport : DPRIO_REG_ARRAY_OF_INT (1 DOWNTO 0) := (OTHERS => 0); +SIGNAL tmp_clkdiv5_pll_select : STD_LOGIC := '0'; +SIGNAL clkdiv5_pll_select : INTEGER := 0; +SIGNAL clkdiv5_pll_phyport : INTEGER := 0; +SIGNAL clkdiv5_pll_cram : STD_LOGIC := '0'; +SIGNAL clkdiv5_pll_cram_phy : STD_LOGIC := '0'; +-- Write --------------- ch5 +SIGNAL clkdiv5_pll_phyport_out : INTEGER := 0; +SIGNAL clkdiv5_pll_phyport_out_logic : INTEGER := 0; +SIGNAL clkdiv5_pll_select_out_logic : STD_LOGIC := '0'; +SIGNAL clkdiv5_pll_select_out : STD_LOGIC := '0'; + + +BEGIN + +--------------------------------------------------------------------------- +-- PLL clock selection ---------------------------------------------------- +--------------------------------------------------------------------------- + +PROCESS -- initialize the TABLE + VARIABLE init_table : STD_LOGIC := '1'; + VARIABLE tmp_int : INTEGER := 0; + + BEGIN + IF (init_table = '1') THEN + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_IQ2) <= "10U00"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_IQ3) <= "10U01"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_IQ4) <= "10U10"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_IQ5) <= "11U00"; -- skip + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_IQ6) <= "11U01"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_IQ7) <= "11U10"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_PLD_CLK) <= "10U11"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_GPLL_CLK) <= "11U11"; + -- iqsel below is donot care so take default for preventing X values passing around + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_CLKREFCLK0) <= "00U00"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_CLKREFCLK1) <= "01U00"; + pll_clock_phyport_to_cram(PLL_CLOCK_SELECT_ERR) <= "11111"; + + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk0_logical_to_physical_mapping); + pll0_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk1_logical_to_physical_mapping); + pll0_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk2_logical_to_physical_mapping); + pll0_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk3_logical_to_physical_mapping); + pll0_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk4_logical_to_physical_mapping); + pll0_clock_index_to_phyport(4) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk5_logical_to_physical_mapping); + pll0_clock_index_to_phyport(5) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk6_logical_to_physical_mapping); + pll0_clock_index_to_phyport(6) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk7_logical_to_physical_mapping); + pll0_clock_index_to_phyport(7) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk8_logical_to_physical_mapping); + pll0_clock_index_to_phyport(8) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll0_inclk9_logical_to_physical_mapping); + pll0_clock_index_to_phyport(9) <= tmp_int; + + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk0_logical_to_physical_mapping); + pll1_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk1_logical_to_physical_mapping); + pll1_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk2_logical_to_physical_mapping); + pll1_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk3_logical_to_physical_mapping); + pll1_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk4_logical_to_physical_mapping); + pll1_clock_index_to_phyport(4) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk5_logical_to_physical_mapping); + pll1_clock_index_to_phyport(5) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk6_logical_to_physical_mapping); + pll1_clock_index_to_phyport(6) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk7_logical_to_physical_mapping); + pll1_clock_index_to_phyport(7) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk8_logical_to_physical_mapping); + pll1_clock_index_to_phyport(8) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll1_inclk9_logical_to_physical_mapping); + pll1_clock_index_to_phyport(9) <= tmp_int; + + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk0_logical_to_physical_mapping); + pll2_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk1_logical_to_physical_mapping); + pll2_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk2_logical_to_physical_mapping); + pll2_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk3_logical_to_physical_mapping); + pll2_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk4_logical_to_physical_mapping); + pll2_clock_index_to_phyport(4) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk5_logical_to_physical_mapping); + pll2_clock_index_to_phyport(5) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk6_logical_to_physical_mapping); + pll2_clock_index_to_phyport(6) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk7_logical_to_physical_mapping); + pll2_clock_index_to_phyport(7) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk8_logical_to_physical_mapping); + pll2_clock_index_to_phyport(8) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll2_inclk9_logical_to_physical_mapping); + pll2_clock_index_to_phyport(9) <= tmp_int; + + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk0_logical_to_physical_mapping); + pll3_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk1_logical_to_physical_mapping); + pll3_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk2_logical_to_physical_mapping); + pll3_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk3_logical_to_physical_mapping); + pll3_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk4_logical_to_physical_mapping); + pll3_clock_index_to_phyport(4) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk5_logical_to_physical_mapping); + pll3_clock_index_to_phyport(5) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk6_logical_to_physical_mapping); + pll3_clock_index_to_phyport(6) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk7_logical_to_physical_mapping); + pll3_clock_index_to_phyport(7) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk8_logical_to_physical_mapping); + pll3_clock_index_to_phyport(8) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll3_inclk9_logical_to_physical_mapping); + pll3_clock_index_to_phyport(9) <= tmp_int; + + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk0_logical_to_physical_mapping); + pll4_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk1_logical_to_physical_mapping); + pll4_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk2_logical_to_physical_mapping); + pll4_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk3_logical_to_physical_mapping); + pll4_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk4_logical_to_physical_mapping); + pll4_clock_index_to_phyport(4) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk5_logical_to_physical_mapping); + pll4_clock_index_to_phyport(5) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk6_logical_to_physical_mapping); + pll4_clock_index_to_phyport(6) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk7_logical_to_physical_mapping); + pll4_clock_index_to_phyport(7) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk8_logical_to_physical_mapping); + pll4_clock_index_to_phyport(8) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll4_inclk9_logical_to_physical_mapping); + pll4_clock_index_to_phyport(9) <= tmp_int; + + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk0_logical_to_physical_mapping); + pll5_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk1_logical_to_physical_mapping); + pll5_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk2_logical_to_physical_mapping); + pll5_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk3_logical_to_physical_mapping); + pll5_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk4_logical_to_physical_mapping); + pll5_clock_index_to_phyport(4) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk5_logical_to_physical_mapping); + pll5_clock_index_to_phyport(5) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk6_logical_to_physical_mapping); + pll5_clock_index_to_phyport(6) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk7_logical_to_physical_mapping); + pll5_clock_index_to_phyport(7) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk8_logical_to_physical_mapping); + pll5_clock_index_to_phyport(8) <= tmp_int; + tmp_int := convert_pll_phyport_str_to_phyport_enum(pll5_inclk9_logical_to_physical_mapping); + pll5_clock_index_to_phyport(9) <= tmp_int; + + init_table := '0'; + END IF; + + WAIT; +END PROCESS; -- end of initializing tables + +-- DPRIO read - logical pll channel +tmp_pll0_clock_select_vec <= pll0_init_pfd_clk_sel WHEN + ( (pll0_init_pfd_clk_sel(0) = '0' OR pll0_init_pfd_clk_sel(0) = '1') AND + (pll0_init_pfd_clk_sel(1) = '0' OR pll0_init_pfd_clk_sel(1) = '1') AND + (pll0_init_pfd_clk_sel(2) = '0' OR pll0_init_pfd_clk_sel(2) = '1') AND + (pll0_init_pfd_clk_sel(3) = '0' OR pll0_init_pfd_clk_sel(3) = '1')) ELSE + "0000"; + +pll0_clock_select <= dprio_reg_to_int(tmp_pll0_clock_select_vec); +pll0_clock_phyport <= pll0_clock_index_to_phyport(pll0_clock_select); + +pll0_clock_cram <= pll_clock_phyport_to_cram(pll0_clock_phyport); + +-- switch to physical pll number +pll0_clock_cram_phy <= pll0_clock_cram WHEN (pll0_logical_to_physical_mapping = 0) ELSE + pll1_clock_cram WHEN (pll1_logical_to_physical_mapping = 0) ELSE + pll2_clock_cram WHEN (pll2_logical_to_physical_mapping = 0) ELSE + pll3_clock_cram WHEN (pll3_logical_to_physical_mapping = 0) ELSE + pll4_clock_cram WHEN (pll4_logical_to_physical_mapping = 0) ELSE + pll5_clock_cram WHEN (pll5_logical_to_physical_mapping = 0) ELSE + pll0_clock_cram; + +pll0_csr_riqclk_sel <= pll0_clock_cram_phy(1 DOWNTO 0); +pll0_csr_rrefclk_sel <= pll0_clock_cram_phy(4 DOWNTO 3); + +-- DPRIO write - CRAM on physical +pll0_clock_phyport_out <= convert_pll_clock_cram_to_phyport(pll0_dp_rrefclk_sel, pll0_dp_riqclk_sel); + -- but the map is on logic channel +pll0_clock_phyport_out_logic <= pll0_clock_phyport_out WHEN (pll0_logical_to_physical_mapping = 0) ELSE + pll1_clock_phyport_out WHEN (pll0_logical_to_physical_mapping = 1) ELSE + pll2_clock_phyport_out WHEN (pll0_logical_to_physical_mapping = 2) ELSE + pll3_clock_phyport_out WHEN (pll0_logical_to_physical_mapping = 3) ELSE + pll4_clock_phyport_out WHEN (pll0_logical_to_physical_mapping = 4) ELSE + pll5_clock_phyport_out WHEN (pll0_logical_to_physical_mapping = 5) ELSE + pll0_clock_phyport_out; + +pll0_clock_select_out_logic <= "0000" WHEN (pll0_clock_index_to_phyport(0) = pll0_clock_phyport_out_logic) ELSE + "0001" WHEN (pll0_clock_index_to_phyport(1) = pll0_clock_phyport_out_logic) ELSE + "0010" WHEN (pll0_clock_index_to_phyport(2) = pll0_clock_phyport_out_logic) ELSE + "0011" WHEN (pll0_clock_index_to_phyport(3) = pll0_clock_phyport_out_logic) ELSE + "0100" WHEN (pll0_clock_index_to_phyport(4) = pll0_clock_phyport_out_logic) ELSE + "0101" WHEN (pll0_clock_index_to_phyport(5) = pll0_clock_phyport_out_logic) ELSE + "0110" WHEN (pll0_clock_index_to_phyport(6) = pll0_clock_phyport_out_logic) ELSE + "0111" WHEN (pll0_clock_index_to_phyport(7) = pll0_clock_phyport_out_logic) ELSE + "1000" WHEN (pll0_clock_index_to_phyport(8) = pll0_clock_phyport_out_logic) ELSE + "1001" WHEN (pll0_clock_index_to_phyport(9) = pll0_clock_phyport_out_logic) ELSE + "1111"; -- invalid cram values + -- back to physical +pll0_clock_select_out <= pll0_clock_select_out_logic WHEN (pll0_logical_to_physical_mapping = 0) ELSE + pll1_clock_select_out_logic WHEN (pll1_logical_to_physical_mapping = 0) ELSE + pll2_clock_select_out_logic WHEN (pll2_logical_to_physical_mapping = 0) ELSE + pll3_clock_select_out_logic WHEN (pll3_logical_to_physical_mapping = 0) ELSE + pll4_clock_select_out_logic WHEN (pll4_logical_to_physical_mapping = 0) ELSE + pll5_clock_select_out_logic WHEN (pll5_logical_to_physical_mapping = 0) ELSE + pll0_clock_select_out_logic; + +pll0_dp_pfd_clk_sel <= pll0_clock_select_out; + + +-- DPRIO read - logical pll channel +tmp_pll1_clock_select_vec <= pll1_init_pfd_clk_sel WHEN + ( (pll1_init_pfd_clk_sel(0) = '0' OR pll1_init_pfd_clk_sel(0) = '1') AND + (pll1_init_pfd_clk_sel(1) = '0' OR pll1_init_pfd_clk_sel(1) = '1') AND + (pll1_init_pfd_clk_sel(2) = '0' OR pll1_init_pfd_clk_sel(2) = '1') AND + (pll1_init_pfd_clk_sel(3) = '0' OR pll1_init_pfd_clk_sel(3) = '1')) ELSE + "0000"; + +pll1_clock_select <= dprio_reg_to_int(tmp_pll1_clock_select_vec); +pll1_clock_phyport <= pll1_clock_index_to_phyport(pll1_clock_select); + +pll1_clock_cram <= pll_clock_phyport_to_cram(pll1_clock_phyport); + +-- switch to physical pll number +pll1_clock_cram_phy <= pll0_clock_cram WHEN (pll0_logical_to_physical_mapping = 1) ELSE + pll1_clock_cram WHEN (pll1_logical_to_physical_mapping = 1) ELSE + pll2_clock_cram WHEN (pll2_logical_to_physical_mapping = 1) ELSE + pll3_clock_cram WHEN (pll3_logical_to_physical_mapping = 1) ELSE + pll4_clock_cram WHEN (pll4_logical_to_physical_mapping = 1) ELSE + pll5_clock_cram WHEN (pll5_logical_to_physical_mapping = 1) ELSE + pll1_clock_cram; + +pll1_csr_riqclk_sel <= pll1_clock_cram_phy(1 DOWNTO 0); +pll1_csr_rrefclk_sel <= pll1_clock_cram_phy(4 DOWNTO 3); + +-- DPRIO write - CRAM on physical +pll1_clock_phyport_out <= convert_pll_clock_cram_to_phyport(pll1_dp_rrefclk_sel, pll1_dp_riqclk_sel); + -- but the map is on logic channel +pll1_clock_phyport_out_logic <= pll0_clock_phyport_out WHEN (pll1_logical_to_physical_mapping = 0) ELSE + pll1_clock_phyport_out WHEN (pll1_logical_to_physical_mapping = 1) ELSE + pll2_clock_phyport_out WHEN (pll1_logical_to_physical_mapping = 2) ELSE + pll3_clock_phyport_out WHEN (pll1_logical_to_physical_mapping = 3) ELSE + pll4_clock_phyport_out WHEN (pll1_logical_to_physical_mapping = 4) ELSE + pll5_clock_phyport_out WHEN (pll1_logical_to_physical_mapping = 5) ELSE + pll1_clock_phyport_out; + +pll1_clock_select_out_logic <= "0000" WHEN (pll1_clock_index_to_phyport(0) = pll1_clock_phyport_out_logic) ELSE + "0001" WHEN (pll1_clock_index_to_phyport(1) = pll1_clock_phyport_out_logic) ELSE + "0010" WHEN (pll1_clock_index_to_phyport(2) = pll1_clock_phyport_out_logic) ELSE + "0011" WHEN (pll1_clock_index_to_phyport(3) = pll1_clock_phyport_out_logic) ELSE + "0100" WHEN (pll1_clock_index_to_phyport(4) = pll1_clock_phyport_out_logic) ELSE + "0101" WHEN (pll1_clock_index_to_phyport(5) = pll1_clock_phyport_out_logic) ELSE + "0110" WHEN (pll1_clock_index_to_phyport(6) = pll1_clock_phyport_out_logic) ELSE + "0111" WHEN (pll1_clock_index_to_phyport(7) = pll1_clock_phyport_out_logic) ELSE + "1000" WHEN (pll1_clock_index_to_phyport(8) = pll1_clock_phyport_out_logic) ELSE + "1001" WHEN (pll1_clock_index_to_phyport(9) = pll1_clock_phyport_out_logic) ELSE + "1111"; -- invalid cram values + -- back to physical +pll1_clock_select_out <= pll0_clock_select_out_logic WHEN (pll0_logical_to_physical_mapping = 1) ELSE + pll1_clock_select_out_logic WHEN (pll1_logical_to_physical_mapping = 1) ELSE + pll2_clock_select_out_logic WHEN (pll2_logical_to_physical_mapping = 1) ELSE + pll3_clock_select_out_logic WHEN (pll3_logical_to_physical_mapping = 1) ELSE + pll4_clock_select_out_logic WHEN (pll4_logical_to_physical_mapping = 1) ELSE + pll5_clock_select_out_logic WHEN (pll5_logical_to_physical_mapping = 1) ELSE + pll1_clock_select_out_logic; + +pll1_dp_pfd_clk_sel <= pll1_clock_select_out; + + +-- DPRIO read - logical pll channel +tmp_pll2_clock_select_vec <= pll2_init_pfd_clk_sel WHEN + ( (pll2_init_pfd_clk_sel(0) = '0' OR pll2_init_pfd_clk_sel(0) = '1') AND + (pll2_init_pfd_clk_sel(1) = '0' OR pll2_init_pfd_clk_sel(1) = '1') AND + (pll2_init_pfd_clk_sel(2) = '0' OR pll2_init_pfd_clk_sel(2) = '1') AND + (pll2_init_pfd_clk_sel(3) = '0' OR pll2_init_pfd_clk_sel(3) = '1')) ELSE + "0000"; + +pll2_clock_select <= dprio_reg_to_int(tmp_pll2_clock_select_vec); +pll2_clock_phyport <= pll2_clock_index_to_phyport(pll2_clock_select); + +pll2_clock_cram <= pll_clock_phyport_to_cram(pll2_clock_phyport); + +-- switch to physical pll number +pll2_clock_cram_phy <= pll0_clock_cram WHEN (pll0_logical_to_physical_mapping = 2) ELSE + pll1_clock_cram WHEN (pll1_logical_to_physical_mapping = 2) ELSE + pll2_clock_cram WHEN (pll2_logical_to_physical_mapping = 2) ELSE + pll3_clock_cram WHEN (pll3_logical_to_physical_mapping = 2) ELSE + pll4_clock_cram WHEN (pll4_logical_to_physical_mapping = 2) ELSE + pll5_clock_cram WHEN (pll5_logical_to_physical_mapping = 2) ELSE + pll2_clock_cram; + +pll2_csr_riqclk_sel <= pll2_clock_cram_phy(1 DOWNTO 0); +pll2_csr_rrefclk_sel <= pll2_clock_cram_phy(4 DOWNTO 3); + +-- DPRIO write - CRAM on physical +pll2_clock_phyport_out <= convert_pll_clock_cram_to_phyport(pll2_dp_rrefclk_sel, pll2_dp_riqclk_sel); + -- but the map is on logic channel +pll2_clock_phyport_out_logic <= pll0_clock_phyport_out WHEN (pll2_logical_to_physical_mapping = 0) ELSE + pll1_clock_phyport_out WHEN (pll2_logical_to_physical_mapping = 1) ELSE + pll2_clock_phyport_out WHEN (pll2_logical_to_physical_mapping = 2) ELSE + pll3_clock_phyport_out WHEN (pll2_logical_to_physical_mapping = 3) ELSE + pll4_clock_phyport_out WHEN (pll2_logical_to_physical_mapping = 4) ELSE + pll5_clock_phyport_out WHEN (pll2_logical_to_physical_mapping = 5) ELSE + pll2_clock_phyport_out; + +pll2_clock_select_out_logic <= "0000" WHEN (pll2_clock_index_to_phyport(0) = pll2_clock_phyport_out_logic) ELSE + "0001" WHEN (pll2_clock_index_to_phyport(1) = pll2_clock_phyport_out_logic) ELSE + "0010" WHEN (pll2_clock_index_to_phyport(2) = pll2_clock_phyport_out_logic) ELSE + "0011" WHEN (pll2_clock_index_to_phyport(3) = pll2_clock_phyport_out_logic) ELSE + "0100" WHEN (pll2_clock_index_to_phyport(4) = pll2_clock_phyport_out_logic) ELSE + "0101" WHEN (pll2_clock_index_to_phyport(5) = pll2_clock_phyport_out_logic) ELSE + "0110" WHEN (pll2_clock_index_to_phyport(6) = pll2_clock_phyport_out_logic) ELSE + "0111" WHEN (pll2_clock_index_to_phyport(7) = pll2_clock_phyport_out_logic) ELSE + "1000" WHEN (pll2_clock_index_to_phyport(8) = pll2_clock_phyport_out_logic) ELSE + "1001" WHEN (pll2_clock_index_to_phyport(9) = pll2_clock_phyport_out_logic) ELSE + "1111"; -- invalid cram values + -- back to physical +pll2_clock_select_out <= pll0_clock_select_out_logic WHEN (pll0_logical_to_physical_mapping = 2) ELSE + pll1_clock_select_out_logic WHEN (pll1_logical_to_physical_mapping = 2) ELSE + pll2_clock_select_out_logic WHEN (pll2_logical_to_physical_mapping = 2) ELSE + pll3_clock_select_out_logic WHEN (pll3_logical_to_physical_mapping = 2) ELSE + pll4_clock_select_out_logic WHEN (pll4_logical_to_physical_mapping = 2) ELSE + pll5_clock_select_out_logic WHEN (pll5_logical_to_physical_mapping = 2) ELSE + pll2_clock_select_out_logic; + +pll2_dp_pfd_clk_sel <= pll2_clock_select_out; + + +-- DPRIO read - logical pll channel +tmp_pll3_clock_select_vec <= pll3_init_pfd_clk_sel WHEN + ( (pll3_init_pfd_clk_sel(0) = '0' OR pll3_init_pfd_clk_sel(0) = '1') AND + (pll3_init_pfd_clk_sel(1) = '0' OR pll3_init_pfd_clk_sel(1) = '1') AND + (pll3_init_pfd_clk_sel(2) = '0' OR pll3_init_pfd_clk_sel(2) = '1') AND + (pll3_init_pfd_clk_sel(3) = '0' OR pll3_init_pfd_clk_sel(3) = '1')) ELSE + "0000"; + +pll3_clock_select <= dprio_reg_to_int(tmp_pll3_clock_select_vec); +pll3_clock_phyport <= pll3_clock_index_to_phyport(pll3_clock_select); + +pll3_clock_cram <= pll_clock_phyport_to_cram(pll3_clock_phyport); + +-- switch to physical pll number +pll3_clock_cram_phy <= pll0_clock_cram WHEN (pll0_logical_to_physical_mapping = 3) ELSE + pll1_clock_cram WHEN (pll1_logical_to_physical_mapping = 3) ELSE + pll2_clock_cram WHEN (pll2_logical_to_physical_mapping = 3) ELSE + pll3_clock_cram WHEN (pll3_logical_to_physical_mapping = 3) ELSE + pll4_clock_cram WHEN (pll4_logical_to_physical_mapping = 3) ELSE + pll5_clock_cram WHEN (pll5_logical_to_physical_mapping = 3) ELSE + pll3_clock_cram; + +pll3_csr_riqclk_sel <= pll3_clock_cram_phy(1 DOWNTO 0); +pll3_csr_rrefclk_sel <= pll3_clock_cram_phy(4 DOWNTO 3); + +-- DPRIO write - CRAM on physical +pll3_clock_phyport_out <= convert_pll_clock_cram_to_phyport(pll3_dp_rrefclk_sel, pll3_dp_riqclk_sel); + -- but the map is on logic channel +pll3_clock_phyport_out_logic <= pll0_clock_phyport_out WHEN (pll3_logical_to_physical_mapping = 0) ELSE + pll1_clock_phyport_out WHEN (pll3_logical_to_physical_mapping = 1) ELSE + pll2_clock_phyport_out WHEN (pll3_logical_to_physical_mapping = 2) ELSE + pll3_clock_phyport_out WHEN (pll3_logical_to_physical_mapping = 3) ELSE + pll4_clock_phyport_out WHEN (pll3_logical_to_physical_mapping = 4) ELSE + pll5_clock_phyport_out WHEN (pll3_logical_to_physical_mapping = 5) ELSE + pll3_clock_phyport_out; + +pll3_clock_select_out_logic <= "0000" WHEN (pll3_clock_index_to_phyport(0) = pll3_clock_phyport_out_logic) ELSE + "0001" WHEN (pll3_clock_index_to_phyport(1) = pll3_clock_phyport_out_logic) ELSE + "0010" WHEN (pll3_clock_index_to_phyport(2) = pll3_clock_phyport_out_logic) ELSE + "0011" WHEN (pll3_clock_index_to_phyport(3) = pll3_clock_phyport_out_logic) ELSE + "0100" WHEN (pll3_clock_index_to_phyport(4) = pll3_clock_phyport_out_logic) ELSE + "0101" WHEN (pll3_clock_index_to_phyport(5) = pll3_clock_phyport_out_logic) ELSE + "0110" WHEN (pll3_clock_index_to_phyport(6) = pll3_clock_phyport_out_logic) ELSE + "0111" WHEN (pll3_clock_index_to_phyport(7) = pll3_clock_phyport_out_logic) ELSE + "1000" WHEN (pll3_clock_index_to_phyport(8) = pll3_clock_phyport_out_logic) ELSE + "1001" WHEN (pll3_clock_index_to_phyport(9) = pll3_clock_phyport_out_logic) ELSE + "1111"; -- invalid cram values + -- back to physical +pll3_clock_select_out <= pll0_clock_select_out_logic WHEN (pll0_logical_to_physical_mapping = 3) ELSE + pll1_clock_select_out_logic WHEN (pll1_logical_to_physical_mapping = 3) ELSE + pll2_clock_select_out_logic WHEN (pll2_logical_to_physical_mapping = 3) ELSE + pll3_clock_select_out_logic WHEN (pll3_logical_to_physical_mapping = 3) ELSE + pll4_clock_select_out_logic WHEN (pll4_logical_to_physical_mapping = 3) ELSE + pll5_clock_select_out_logic WHEN (pll5_logical_to_physical_mapping = 3) ELSE + pll3_clock_select_out_logic; + +pll3_dp_pfd_clk_sel <= pll3_clock_select_out; + + +-- DPRIO read - logical pll channel +tmp_pll4_clock_select_vec <= pll4_init_pfd_clk_sel WHEN + ( (pll4_init_pfd_clk_sel(0) = '0' OR pll4_init_pfd_clk_sel(0) = '1') AND + (pll4_init_pfd_clk_sel(1) = '0' OR pll4_init_pfd_clk_sel(1) = '1') AND + (pll4_init_pfd_clk_sel(2) = '0' OR pll4_init_pfd_clk_sel(2) = '1') AND + (pll4_init_pfd_clk_sel(3) = '0' OR pll4_init_pfd_clk_sel(3) = '1')) ELSE + "0000"; + +pll4_clock_select <= dprio_reg_to_int(tmp_pll4_clock_select_vec); +pll4_clock_phyport <= pll4_clock_index_to_phyport(pll4_clock_select); + +pll4_clock_cram <= pll_clock_phyport_to_cram(pll4_clock_phyport); + +-- switch to physical pll number +pll4_clock_cram_phy <= pll0_clock_cram WHEN (pll0_logical_to_physical_mapping = 4) ELSE + pll1_clock_cram WHEN (pll1_logical_to_physical_mapping = 4) ELSE + pll2_clock_cram WHEN (pll2_logical_to_physical_mapping = 4) ELSE + pll3_clock_cram WHEN (pll3_logical_to_physical_mapping = 4) ELSE + pll4_clock_cram WHEN (pll4_logical_to_physical_mapping = 4) ELSE + pll5_clock_cram WHEN (pll5_logical_to_physical_mapping = 4) ELSE + pll4_clock_cram; + +pll4_csr_riqclk_sel <= pll4_clock_cram_phy(1 DOWNTO 0); +pll4_csr_rrefclk_sel <= pll4_clock_cram_phy(4 DOWNTO 3); + +-- DPRIO write - CRAM on physical +pll4_clock_phyport_out <= convert_pll_clock_cram_to_phyport(pll4_dp_rrefclk_sel, pll4_dp_riqclk_sel); + -- but the map is on logic channel +pll4_clock_phyport_out_logic <= pll0_clock_phyport_out WHEN (pll4_logical_to_physical_mapping = 0) ELSE + pll1_clock_phyport_out WHEN (pll4_logical_to_physical_mapping = 1) ELSE + pll2_clock_phyport_out WHEN (pll4_logical_to_physical_mapping = 2) ELSE + pll3_clock_phyport_out WHEN (pll4_logical_to_physical_mapping = 3) ELSE + pll4_clock_phyport_out WHEN (pll4_logical_to_physical_mapping = 4) ELSE + pll5_clock_phyport_out WHEN (pll4_logical_to_physical_mapping = 5) ELSE + pll4_clock_phyport_out; + +pll4_clock_select_out_logic <= "0000" WHEN (pll4_clock_index_to_phyport(0) = pll4_clock_phyport_out_logic) ELSE + "0001" WHEN (pll4_clock_index_to_phyport(1) = pll4_clock_phyport_out_logic) ELSE + "0010" WHEN (pll4_clock_index_to_phyport(2) = pll4_clock_phyport_out_logic) ELSE + "0011" WHEN (pll4_clock_index_to_phyport(3) = pll4_clock_phyport_out_logic) ELSE + "0100" WHEN (pll4_clock_index_to_phyport(4) = pll4_clock_phyport_out_logic) ELSE + "0101" WHEN (pll4_clock_index_to_phyport(5) = pll4_clock_phyport_out_logic) ELSE + "0110" WHEN (pll4_clock_index_to_phyport(6) = pll4_clock_phyport_out_logic) ELSE + "0111" WHEN (pll4_clock_index_to_phyport(7) = pll4_clock_phyport_out_logic) ELSE + "1000" WHEN (pll4_clock_index_to_phyport(8) = pll4_clock_phyport_out_logic) ELSE + "1001" WHEN (pll4_clock_index_to_phyport(9) = pll4_clock_phyport_out_logic) ELSE + "1111"; -- invalid cram values + -- back to physical +pll4_clock_select_out <= pll0_clock_select_out_logic WHEN (pll0_logical_to_physical_mapping = 4) ELSE + pll1_clock_select_out_logic WHEN (pll1_logical_to_physical_mapping = 4) ELSE + pll2_clock_select_out_logic WHEN (pll2_logical_to_physical_mapping = 4) ELSE + pll3_clock_select_out_logic WHEN (pll3_logical_to_physical_mapping = 4) ELSE + pll4_clock_select_out_logic WHEN (pll4_logical_to_physical_mapping = 4) ELSE + pll5_clock_select_out_logic WHEN (pll5_logical_to_physical_mapping = 4) ELSE + pll4_clock_select_out_logic; + +pll4_dp_pfd_clk_sel <= pll4_clock_select_out; + + +-- DPRIO read - logical pll channel +tmp_pll5_clock_select_vec <= pll5_init_pfd_clk_sel WHEN + ( (pll5_init_pfd_clk_sel(0) = '0' OR pll5_init_pfd_clk_sel(0) = '1') AND + (pll5_init_pfd_clk_sel(1) = '0' OR pll5_init_pfd_clk_sel(1) = '1') AND + (pll5_init_pfd_clk_sel(2) = '0' OR pll5_init_pfd_clk_sel(2) = '1') AND + (pll5_init_pfd_clk_sel(3) = '0' OR pll5_init_pfd_clk_sel(3) = '1')) ELSE + "0000"; + +pll5_clock_select <= dprio_reg_to_int(tmp_pll5_clock_select_vec); +pll5_clock_phyport <= pll5_clock_index_to_phyport(pll5_clock_select); + +pll5_clock_cram <= pll_clock_phyport_to_cram(pll5_clock_phyport); + +-- switch to physical pll number +pll5_clock_cram_phy <= pll0_clock_cram WHEN (pll0_logical_to_physical_mapping = 5) ELSE + pll1_clock_cram WHEN (pll1_logical_to_physical_mapping = 5) ELSE + pll2_clock_cram WHEN (pll2_logical_to_physical_mapping = 5) ELSE + pll3_clock_cram WHEN (pll3_logical_to_physical_mapping = 5) ELSE + pll4_clock_cram WHEN (pll4_logical_to_physical_mapping = 5) ELSE + pll5_clock_cram WHEN (pll5_logical_to_physical_mapping = 5) ELSE + pll5_clock_cram; + +pll5_csr_riqclk_sel <= pll5_clock_cram_phy(1 DOWNTO 0); +pll5_csr_rrefclk_sel <= pll5_clock_cram_phy(4 DOWNTO 3); + +-- DPRIO write - CRAM on physical +pll5_clock_phyport_out <= convert_pll_clock_cram_to_phyport(pll5_dp_rrefclk_sel, pll5_dp_riqclk_sel); + -- but the map is on logic channel +pll5_clock_phyport_out_logic <= pll0_clock_phyport_out WHEN (pll5_logical_to_physical_mapping = 0) ELSE + pll1_clock_phyport_out WHEN (pll5_logical_to_physical_mapping = 1) ELSE + pll2_clock_phyport_out WHEN (pll5_logical_to_physical_mapping = 2) ELSE + pll3_clock_phyport_out WHEN (pll5_logical_to_physical_mapping = 3) ELSE + pll4_clock_phyport_out WHEN (pll5_logical_to_physical_mapping = 4) ELSE + pll5_clock_phyport_out WHEN (pll5_logical_to_physical_mapping = 5) ELSE + pll5_clock_phyport_out; + +pll5_clock_select_out_logic <= "0000" WHEN (pll5_clock_index_to_phyport(0) = pll5_clock_phyport_out_logic) ELSE + "0001" WHEN (pll5_clock_index_to_phyport(1) = pll5_clock_phyport_out_logic) ELSE + "0010" WHEN (pll5_clock_index_to_phyport(2) = pll5_clock_phyport_out_logic) ELSE + "0011" WHEN (pll5_clock_index_to_phyport(3) = pll5_clock_phyport_out_logic) ELSE + "0100" WHEN (pll5_clock_index_to_phyport(4) = pll5_clock_phyport_out_logic) ELSE + "0101" WHEN (pll5_clock_index_to_phyport(5) = pll5_clock_phyport_out_logic) ELSE + "0110" WHEN (pll5_clock_index_to_phyport(6) = pll5_clock_phyport_out_logic) ELSE + "0111" WHEN (pll5_clock_index_to_phyport(7) = pll5_clock_phyport_out_logic) ELSE + "1000" WHEN (pll5_clock_index_to_phyport(8) = pll5_clock_phyport_out_logic) ELSE + "1001" WHEN (pll5_clock_index_to_phyport(9) = pll5_clock_phyport_out_logic) ELSE + "1111"; -- invalid cram values + -- back to physical +pll5_clock_select_out <= pll0_clock_select_out_logic WHEN (pll0_logical_to_physical_mapping = 5) ELSE + pll1_clock_select_out_logic WHEN (pll1_logical_to_physical_mapping = 5) ELSE + pll2_clock_select_out_logic WHEN (pll2_logical_to_physical_mapping = 5) ELSE + pll3_clock_select_out_logic WHEN (pll3_logical_to_physical_mapping = 5) ELSE + pll4_clock_select_out_logic WHEN (pll4_logical_to_physical_mapping = 5) ELSE + pll5_clock_select_out_logic WHEN (pll5_logical_to_physical_mapping = 5) ELSE + pll5_clock_select_out_logic; + +pll5_dp_pfd_clk_sel <= pll5_clock_select_out; + + + +--------------------------------------------------------------------------- +-- TXPMA clock selection -------------------------------------------------- +--------------------------------------------------------------------------- + +PROCESS -- initialize the TABLE + VARIABLE init_table : STD_LOGIC := '1'; + VARIABLE tmp_int : INTEGER := 0; + + BEGIN + IF (init_table = '1') THEN + txpma_clock_phyport_to_cram(TXPMA_CLKIN_SELECT_X1) <= "00"; + txpma_clock_phyport_to_cram(TXPMA_CLKIN_SELECT_X4) <= "01"; + txpma_clock_phyport_to_cram(TXPMA_CLKIN_SELECT_XN_TOP) <= "10"; + txpma_clock_phyport_to_cram(TXPMA_CLKIN_SELECT_XN_BOTTOM) <= "11"; + txpma_clock_phyport_to_cram(TXPMA_CLKIN_SELECT_HT) <= "00"; + txpma_clock_phyport_to_cram(TXPMA_CLKIN_SELECT_ERR) <= "11"; + + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk0_logical_to_physical_mapping); + txpma0_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk1_logical_to_physical_mapping); + txpma0_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk2_logical_to_physical_mapping); + txpma0_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk3_logical_to_physical_mapping); + txpma0_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk4_logical_to_physical_mapping); + txpma0_clock_index_to_phyport(4) <= tmp_int; + + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk0_logical_to_physical_mapping); + txpma1_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk1_logical_to_physical_mapping); + txpma1_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk2_logical_to_physical_mapping); + txpma1_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk3_logical_to_physical_mapping); + txpma1_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk4_logical_to_physical_mapping); + txpma1_clock_index_to_phyport(4) <= tmp_int; + + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk0_logical_to_physical_mapping); + txpma2_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk1_logical_to_physical_mapping); + txpma2_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk2_logical_to_physical_mapping); + txpma2_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk3_logical_to_physical_mapping); + txpma2_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk4_logical_to_physical_mapping); + txpma2_clock_index_to_phyport(4) <= tmp_int; + + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk0_logical_to_physical_mapping); + txpma3_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk1_logical_to_physical_mapping); + txpma3_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk2_logical_to_physical_mapping); + txpma3_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk3_logical_to_physical_mapping); + txpma3_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk4_logical_to_physical_mapping); + txpma3_clock_index_to_phyport(4) <= tmp_int; + + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk0_logical_to_physical_mapping); + txpma4_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk1_logical_to_physical_mapping); + txpma4_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk2_logical_to_physical_mapping); + txpma4_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk3_logical_to_physical_mapping); + txpma4_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk4_logical_to_physical_mapping); + txpma4_clock_index_to_phyport(4) <= tmp_int; + + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk0_logical_to_physical_mapping); + txpma5_clock_index_to_phyport(0) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk1_logical_to_physical_mapping); + txpma5_clock_index_to_phyport(1) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk2_logical_to_physical_mapping); + txpma5_clock_index_to_phyport(2) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk3_logical_to_physical_mapping); + txpma5_clock_index_to_phyport(3) <= tmp_int; + tmp_int := convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk4_logical_to_physical_mapping); + txpma5_clock_index_to_phyport(4) <= tmp_int; + init_table := '0'; + END IF; + + WAIT; +END PROCESS; -- end of initializing tables + +-- DPRIO read - physical pll channel +tmp_txpma0_clock_select_vec <= txpma0_init_clkin_sel WHEN + ( (txpma0_init_clkin_sel(0) = '0' OR txpma0_init_clkin_sel(0) = '1') AND + (txpma0_init_clkin_sel(1) = '0' OR txpma0_init_clkin_sel(1) = '1') AND + (txpma0_init_clkin_sel(2) = '0' OR txpma0_init_clkin_sel(2) = '1') ) ELSE + "000"; + +txpma0_clock_select <= dprio_reg_to_int(tmp_txpma0_clock_select_vec); + +txpma0_clock_phyport <= txpma0_clock_index_to_phyport(txpma0_clock_select); +txpma0_clock_cram <= txpma_clock_phyport_to_cram(0) WHEN (txpma0_clock_phyport = 0) ELSE + txpma_clock_phyport_to_cram(1) WHEN (txpma0_clock_phyport = 1) ELSE + txpma_clock_phyport_to_cram(2) WHEN (txpma0_clock_phyport = 2) ELSE + txpma_clock_phyport_to_cram(3) WHEN (txpma0_clock_phyport = 3) ELSE + txpma_clock_phyport_to_cram(4) WHEN (txpma0_clock_phyport = 4) ELSE + txpma_clock_phyport_to_cram(7) WHEN (txpma0_clock_phyport = 7)ELSE + txpma_clock_phyport_to_cram(0); + +txpma0_clock_cram_phy <= txpma0_clock_cram WHEN (tx0_logical_to_physical_mapping = 0) ELSE + txpma1_clock_cram WHEN (tx1_logical_to_physical_mapping = 0) ELSE + txpma2_clock_cram WHEN (tx2_logical_to_physical_mapping = 0) ELSE + txpma3_clock_cram WHEN (tx3_logical_to_physical_mapping = 0) ELSE + txpma4_clock_cram WHEN (tx4_logical_to_physical_mapping = 0) ELSE + txpma5_clock_cram WHEN (tx5_logical_to_physical_mapping = 0) ELSE + txpma0_clock_cram; +txpma0_csr_rcgb_x_en <= txpma0_clock_cram_phy; + +-- DPRIO write - CRAM on physical +txpma0_clock_phyport_out <= convert_txpma_clock_cram_to_phyport(txpma0_dp_rcgb_x_en); + -- but the map is on logic channel +txpma0_clock_phyport_out_logic <= txpma0_clock_phyport_out WHEN (tx0_logical_to_physical_mapping = 0) ELSE + txpma1_clock_phyport_out WHEN (tx0_logical_to_physical_mapping = 1) ELSE + txpma2_clock_phyport_out WHEN (tx0_logical_to_physical_mapping = 2) ELSE + txpma3_clock_phyport_out WHEN (tx0_logical_to_physical_mapping = 3) ELSE + txpma4_clock_phyport_out WHEN (tx0_logical_to_physical_mapping = 4) ELSE + txpma5_clock_phyport_out WHEN (tx0_logical_to_physical_mapping = 5) ELSE + txpma0_clock_phyport_out; + +txpma0_clock_select_out_logic <= "000" WHEN (txpma0_clock_index_to_phyport(0) = txpma0_clock_phyport_out_logic) ELSE + "001" WHEN (txpma0_clock_index_to_phyport(1) = txpma0_clock_phyport_out_logic) ELSE + "010" WHEN (txpma0_clock_index_to_phyport(2) = txpma0_clock_phyport_out_logic) ELSE + "011" WHEN (txpma0_clock_index_to_phyport(3) = txpma0_clock_phyport_out_logic) ELSE + "100" WHEN (txpma0_clock_index_to_phyport(4) = txpma0_clock_phyport_out_logic) ELSE + "111"; -- invalid cram values + -- back to physical +txpma0_clock_select_out <= txpma0_clock_select_out_logic WHEN (tx0_logical_to_physical_mapping = 0) ELSE + txpma1_clock_select_out_logic WHEN (tx1_logical_to_physical_mapping = 0) ELSE + txpma2_clock_select_out_logic WHEN (tx2_logical_to_physical_mapping = 0) ELSE + txpma3_clock_select_out_logic WHEN (tx3_logical_to_physical_mapping = 0) ELSE + txpma4_clock_select_out_logic WHEN (tx4_logical_to_physical_mapping = 0) ELSE + txpma5_clock_select_out_logic WHEN (tx5_logical_to_physical_mapping = 0) ELSE + txpma0_clock_select_out_logic; + +txpma0_dp_clkin_sel <= txpma0_clock_select_out; + + +-- DPRIO read - physical pll channel +tmp_txpma1_clock_select_vec <= txpma1_init_clkin_sel WHEN + ( (txpma1_init_clkin_sel(0) = '0' OR txpma1_init_clkin_sel(0) = '1') AND + (txpma1_init_clkin_sel(1) = '0' OR txpma1_init_clkin_sel(1) = '1') AND + (txpma1_init_clkin_sel(2) = '0' OR txpma1_init_clkin_sel(2) = '1') ) ELSE + "000"; + +txpma1_clock_select <= dprio_reg_to_int(tmp_txpma1_clock_select_vec); + +txpma1_clock_phyport <= txpma1_clock_index_to_phyport(txpma1_clock_select); +txpma1_clock_cram <= txpma_clock_phyport_to_cram(0) WHEN (txpma1_clock_phyport = 0) ELSE + txpma_clock_phyport_to_cram(1) WHEN (txpma1_clock_phyport = 1) ELSE + txpma_clock_phyport_to_cram(2) WHEN (txpma1_clock_phyport = 2) ELSE + txpma_clock_phyport_to_cram(3) WHEN (txpma1_clock_phyport = 3) ELSE + txpma_clock_phyport_to_cram(4) WHEN (txpma1_clock_phyport = 4) ELSE + txpma_clock_phyport_to_cram(7) WHEN (txpma1_clock_phyport = 7)ELSE + txpma_clock_phyport_to_cram(0); + +txpma1_clock_cram_phy <= txpma0_clock_cram WHEN (tx0_logical_to_physical_mapping = 1) ELSE + txpma1_clock_cram WHEN (tx1_logical_to_physical_mapping = 1) ELSE + txpma2_clock_cram WHEN (tx2_logical_to_physical_mapping = 1) ELSE + txpma3_clock_cram WHEN (tx3_logical_to_physical_mapping = 1) ELSE + txpma4_clock_cram WHEN (tx4_logical_to_physical_mapping = 1) ELSE + txpma5_clock_cram WHEN (tx5_logical_to_physical_mapping = 1) ELSE + txpma0_clock_cram; +txpma1_csr_rcgb_x_en <= txpma1_clock_cram_phy; + +-- DPRIO write - CRAM on physical +txpma1_clock_phyport_out <= convert_txpma_clock_cram_to_phyport(txpma1_dp_rcgb_x_en); + -- but the map is on logic channel +txpma1_clock_phyport_out_logic <= txpma0_clock_phyport_out WHEN (tx1_logical_to_physical_mapping = 0) ELSE + txpma1_clock_phyport_out WHEN (tx1_logical_to_physical_mapping = 1) ELSE + txpma2_clock_phyport_out WHEN (tx1_logical_to_physical_mapping = 2) ELSE + txpma3_clock_phyport_out WHEN (tx1_logical_to_physical_mapping = 3) ELSE + txpma4_clock_phyport_out WHEN (tx1_logical_to_physical_mapping = 4) ELSE + txpma5_clock_phyport_out WHEN (tx1_logical_to_physical_mapping = 5) ELSE + txpma0_clock_phyport_out; + +txpma1_clock_select_out_logic <= "000" WHEN (txpma1_clock_index_to_phyport(0) = txpma1_clock_phyport_out_logic) ELSE + "001" WHEN (txpma1_clock_index_to_phyport(1) = txpma1_clock_phyport_out_logic) ELSE + "010" WHEN (txpma1_clock_index_to_phyport(2) = txpma1_clock_phyport_out_logic) ELSE + "011" WHEN (txpma1_clock_index_to_phyport(3) = txpma1_clock_phyport_out_logic) ELSE + "100" WHEN (txpma1_clock_index_to_phyport(4) = txpma1_clock_phyport_out_logic) ELSE + "111"; -- invalid cram values + -- back to physical +txpma1_clock_select_out <= txpma0_clock_select_out_logic WHEN (tx0_logical_to_physical_mapping = 1) ELSE + txpma1_clock_select_out_logic WHEN (tx1_logical_to_physical_mapping = 1) ELSE + txpma2_clock_select_out_logic WHEN (tx2_logical_to_physical_mapping = 1) ELSE + txpma3_clock_select_out_logic WHEN (tx3_logical_to_physical_mapping = 1) ELSE + txpma4_clock_select_out_logic WHEN (tx4_logical_to_physical_mapping = 1) ELSE + txpma5_clock_select_out_logic WHEN (tx5_logical_to_physical_mapping = 1) ELSE + txpma0_clock_select_out_logic; + +txpma1_dp_clkin_sel <= txpma1_clock_select_out; + + +-- DPRIO read - physical pll channel +tmp_txpma2_clock_select_vec <= txpma2_init_clkin_sel WHEN + ( (txpma2_init_clkin_sel(0) = '0' OR txpma2_init_clkin_sel(0) = '1') AND + (txpma2_init_clkin_sel(1) = '0' OR txpma2_init_clkin_sel(1) = '1') AND + (txpma2_init_clkin_sel(2) = '0' OR txpma2_init_clkin_sel(2) = '1') ) ELSE + "000"; + +txpma2_clock_select <= dprio_reg_to_int(tmp_txpma2_clock_select_vec); + +txpma2_clock_phyport <= txpma2_clock_index_to_phyport(txpma2_clock_select); +txpma2_clock_cram <= txpma_clock_phyport_to_cram(0) WHEN (txpma2_clock_phyport = 0) ELSE + txpma_clock_phyport_to_cram(1) WHEN (txpma2_clock_phyport = 1) ELSE + txpma_clock_phyport_to_cram(2) WHEN (txpma2_clock_phyport = 2) ELSE + txpma_clock_phyport_to_cram(3) WHEN (txpma2_clock_phyport = 3) ELSE + txpma_clock_phyport_to_cram(4) WHEN (txpma2_clock_phyport = 4) ELSE + txpma_clock_phyport_to_cram(7) WHEN (txpma2_clock_phyport = 7)ELSE + txpma_clock_phyport_to_cram(0); + +txpma2_clock_cram_phy <= txpma0_clock_cram WHEN (tx0_logical_to_physical_mapping = 2) ELSE + txpma1_clock_cram WHEN (tx1_logical_to_physical_mapping = 2) ELSE + txpma2_clock_cram WHEN (tx2_logical_to_physical_mapping = 2) ELSE + txpma3_clock_cram WHEN (tx3_logical_to_physical_mapping = 2) ELSE + txpma4_clock_cram WHEN (tx4_logical_to_physical_mapping = 2) ELSE + txpma5_clock_cram WHEN (tx5_logical_to_physical_mapping = 2) ELSE + txpma2_clock_cram; +txpma2_csr_rcgb_x_en <= txpma2_clock_cram_phy; + +-- DPRIO write - CRAM on physical +txpma2_clock_phyport_out <= convert_txpma_clock_cram_to_phyport(txpma2_dp_rcgb_x_en); + -- but the map is on logic channel +txpma2_clock_phyport_out_logic <= txpma0_clock_phyport_out WHEN (tx2_logical_to_physical_mapping = 0) ELSE + txpma1_clock_phyport_out WHEN (tx2_logical_to_physical_mapping = 1) ELSE + txpma2_clock_phyport_out WHEN (tx2_logical_to_physical_mapping = 2) ELSE + txpma3_clock_phyport_out WHEN (tx2_logical_to_physical_mapping = 3) ELSE + txpma4_clock_phyport_out WHEN (tx2_logical_to_physical_mapping = 4) ELSE + txpma5_clock_phyport_out WHEN (tx2_logical_to_physical_mapping = 5) ELSE + txpma2_clock_phyport_out; + +txpma2_clock_select_out_logic <= "000" WHEN (txpma2_clock_index_to_phyport(0) = txpma2_clock_phyport_out_logic) ELSE + "001" WHEN (txpma2_clock_index_to_phyport(1) = txpma2_clock_phyport_out_logic) ELSE + "010" WHEN (txpma2_clock_index_to_phyport(2) = txpma2_clock_phyport_out_logic) ELSE + "011" WHEN (txpma2_clock_index_to_phyport(3) = txpma2_clock_phyport_out_logic) ELSE + "100" WHEN (txpma2_clock_index_to_phyport(4) = txpma2_clock_phyport_out_logic) ELSE + "111"; -- invalid cram values + -- back to physical +txpma2_clock_select_out <= txpma0_clock_select_out_logic WHEN (tx0_logical_to_physical_mapping = 2) ELSE + txpma1_clock_select_out_logic WHEN (tx1_logical_to_physical_mapping = 2) ELSE + txpma2_clock_select_out_logic WHEN (tx2_logical_to_physical_mapping = 2) ELSE + txpma3_clock_select_out_logic WHEN (tx3_logical_to_physical_mapping = 2) ELSE + txpma4_clock_select_out_logic WHEN (tx4_logical_to_physical_mapping = 2) ELSE + txpma5_clock_select_out_logic WHEN (tx5_logical_to_physical_mapping = 2) ELSE + txpma2_clock_select_out_logic; + +txpma2_dp_clkin_sel <= txpma2_clock_select_out; + + +-- DPRIO read - physical pll channel +tmp_txpma3_clock_select_vec <= txpma3_init_clkin_sel WHEN + ( (txpma3_init_clkin_sel(0) = '0' OR txpma3_init_clkin_sel(0) = '1') AND + (txpma3_init_clkin_sel(1) = '0' OR txpma3_init_clkin_sel(1) = '1') AND + (txpma3_init_clkin_sel(2) = '0' OR txpma3_init_clkin_sel(2) = '1') ) ELSE + "000"; + +txpma3_clock_select <= dprio_reg_to_int(tmp_txpma3_clock_select_vec); + +txpma3_clock_phyport <= txpma3_clock_index_to_phyport(txpma3_clock_select); +txpma3_clock_cram <= txpma_clock_phyport_to_cram(0) WHEN (txpma3_clock_phyport = 0) ELSE + txpma_clock_phyport_to_cram(1) WHEN (txpma3_clock_phyport = 1) ELSE + txpma_clock_phyport_to_cram(2) WHEN (txpma3_clock_phyport = 2) ELSE + txpma_clock_phyport_to_cram(3) WHEN (txpma3_clock_phyport = 3) ELSE + txpma_clock_phyport_to_cram(4) WHEN (txpma3_clock_phyport = 4) ELSE + txpma_clock_phyport_to_cram(7) WHEN (txpma3_clock_phyport = 7)ELSE + txpma_clock_phyport_to_cram(0); + +txpma3_clock_cram_phy <= txpma0_clock_cram WHEN (tx0_logical_to_physical_mapping = 3) ELSE + txpma1_clock_cram WHEN (tx1_logical_to_physical_mapping = 3) ELSE + txpma2_clock_cram WHEN (tx2_logical_to_physical_mapping = 3) ELSE + txpma3_clock_cram WHEN (tx3_logical_to_physical_mapping = 3) ELSE + txpma4_clock_cram WHEN (tx4_logical_to_physical_mapping = 3) ELSE + txpma5_clock_cram WHEN (tx5_logical_to_physical_mapping = 3) ELSE + txpma3_clock_cram; +txpma3_csr_rcgb_x_en <= txpma3_clock_cram_phy; + +-- DPRIO write - CRAM on physical +txpma3_clock_phyport_out <= convert_txpma_clock_cram_to_phyport(txpma3_dp_rcgb_x_en); + -- but the map is on logic channel +txpma3_clock_phyport_out_logic <= txpma0_clock_phyport_out WHEN (tx3_logical_to_physical_mapping = 0) ELSE + txpma1_clock_phyport_out WHEN (tx3_logical_to_physical_mapping = 1) ELSE + txpma2_clock_phyport_out WHEN (tx3_logical_to_physical_mapping = 2) ELSE + txpma3_clock_phyport_out WHEN (tx3_logical_to_physical_mapping = 3) ELSE + txpma4_clock_phyport_out WHEN (tx3_logical_to_physical_mapping = 4) ELSE + txpma5_clock_phyport_out WHEN (tx3_logical_to_physical_mapping = 5) ELSE + txpma3_clock_phyport_out; + +txpma3_clock_select_out_logic <= "000" WHEN (txpma3_clock_index_to_phyport(0) = txpma3_clock_phyport_out_logic) ELSE + "001" WHEN (txpma3_clock_index_to_phyport(1) = txpma3_clock_phyport_out_logic) ELSE + "010" WHEN (txpma3_clock_index_to_phyport(2) = txpma3_clock_phyport_out_logic) ELSE + "011" WHEN (txpma3_clock_index_to_phyport(3) = txpma3_clock_phyport_out_logic) ELSE + "100" WHEN (txpma3_clock_index_to_phyport(4) = txpma3_clock_phyport_out_logic) ELSE + "111"; -- invalid cram values + -- back to physical +txpma3_clock_select_out <= txpma0_clock_select_out_logic WHEN (tx0_logical_to_physical_mapping = 3) ELSE + txpma1_clock_select_out_logic WHEN (tx1_logical_to_physical_mapping = 3) ELSE + txpma2_clock_select_out_logic WHEN (tx2_logical_to_physical_mapping = 3) ELSE + txpma3_clock_select_out_logic WHEN (tx3_logical_to_physical_mapping = 3) ELSE + txpma4_clock_select_out_logic WHEN (tx4_logical_to_physical_mapping = 3) ELSE + txpma5_clock_select_out_logic WHEN (tx5_logical_to_physical_mapping = 3) ELSE + txpma3_clock_select_out_logic; + +txpma3_dp_clkin_sel <= txpma3_clock_select_out; + + +-- DPRIO read - physical pll channel +tmp_txpma4_clock_select_vec <= txpma4_init_clkin_sel WHEN + ( (txpma4_init_clkin_sel(0) = '0' OR txpma4_init_clkin_sel(0) = '1') AND + (txpma4_init_clkin_sel(1) = '0' OR txpma4_init_clkin_sel(1) = '1') AND + (txpma4_init_clkin_sel(2) = '0' OR txpma4_init_clkin_sel(2) = '1') ) ELSE + "000"; + +txpma4_clock_select <= dprio_reg_to_int(tmp_txpma4_clock_select_vec); + +txpma4_clock_phyport <= txpma4_clock_index_to_phyport(txpma4_clock_select); +txpma4_clock_cram <= txpma_clock_phyport_to_cram(0) WHEN (txpma4_clock_phyport = 0) ELSE + txpma_clock_phyport_to_cram(1) WHEN (txpma4_clock_phyport = 1) ELSE + txpma_clock_phyport_to_cram(2) WHEN (txpma4_clock_phyport = 2) ELSE + txpma_clock_phyport_to_cram(3) WHEN (txpma4_clock_phyport = 3) ELSE + txpma_clock_phyport_to_cram(4) WHEN (txpma4_clock_phyport = 4) ELSE + txpma_clock_phyport_to_cram(7) WHEN (txpma4_clock_phyport = 7)ELSE + txpma_clock_phyport_to_cram(0); + +txpma4_clock_cram_phy <= txpma0_clock_cram WHEN (tx0_logical_to_physical_mapping = 4) ELSE + txpma1_clock_cram WHEN (tx1_logical_to_physical_mapping = 4) ELSE + txpma2_clock_cram WHEN (tx2_logical_to_physical_mapping = 4) ELSE + txpma3_clock_cram WHEN (tx3_logical_to_physical_mapping = 4) ELSE + txpma4_clock_cram WHEN (tx4_logical_to_physical_mapping = 4) ELSE + txpma5_clock_cram WHEN (tx5_logical_to_physical_mapping = 4) ELSE + txpma4_clock_cram; +txpma4_csr_rcgb_x_en <= txpma4_clock_cram_phy; + +-- DPRIO write - CRAM on physical +txpma4_clock_phyport_out <= convert_txpma_clock_cram_to_phyport(txpma4_dp_rcgb_x_en); + -- but the map is on logic channel +txpma4_clock_phyport_out_logic <= txpma0_clock_phyport_out WHEN (tx4_logical_to_physical_mapping = 0) ELSE + txpma1_clock_phyport_out WHEN (tx4_logical_to_physical_mapping = 1) ELSE + txpma2_clock_phyport_out WHEN (tx4_logical_to_physical_mapping = 2) ELSE + txpma3_clock_phyport_out WHEN (tx4_logical_to_physical_mapping = 3) ELSE + txpma4_clock_phyport_out WHEN (tx4_logical_to_physical_mapping = 4) ELSE + txpma5_clock_phyport_out WHEN (tx4_logical_to_physical_mapping = 5) ELSE + txpma4_clock_phyport_out; + +txpma4_clock_select_out_logic <= "000" WHEN (txpma4_clock_index_to_phyport(0) = txpma4_clock_phyport_out_logic) ELSE + "001" WHEN (txpma4_clock_index_to_phyport(1) = txpma4_clock_phyport_out_logic) ELSE + "010" WHEN (txpma4_clock_index_to_phyport(2) = txpma4_clock_phyport_out_logic) ELSE + "011" WHEN (txpma4_clock_index_to_phyport(3) = txpma4_clock_phyport_out_logic) ELSE + "100" WHEN (txpma4_clock_index_to_phyport(4) = txpma4_clock_phyport_out_logic) ELSE + "111"; -- invalid cram values + -- back to physical +txpma4_clock_select_out <= txpma0_clock_select_out_logic WHEN (tx0_logical_to_physical_mapping = 4) ELSE + txpma1_clock_select_out_logic WHEN (tx1_logical_to_physical_mapping = 4) ELSE + txpma2_clock_select_out_logic WHEN (tx2_logical_to_physical_mapping = 4) ELSE + txpma3_clock_select_out_logic WHEN (tx3_logical_to_physical_mapping = 4) ELSE + txpma4_clock_select_out_logic WHEN (tx4_logical_to_physical_mapping = 4) ELSE + txpma5_clock_select_out_logic WHEN (tx5_logical_to_physical_mapping = 4) ELSE + txpma4_clock_select_out_logic; + +txpma4_dp_clkin_sel <= txpma4_clock_select_out; + + +-- DPRIO read - physical pll channel +tmp_txpma5_clock_select_vec <= txpma5_init_clkin_sel WHEN + ( (txpma5_init_clkin_sel(0) = '0' OR txpma5_init_clkin_sel(0) = '1') AND + (txpma5_init_clkin_sel(1) = '0' OR txpma5_init_clkin_sel(1) = '1') AND + (txpma5_init_clkin_sel(2) = '0' OR txpma5_init_clkin_sel(2) = '1') ) ELSE + "000"; + +txpma5_clock_select <= dprio_reg_to_int(tmp_txpma5_clock_select_vec); + +txpma5_clock_phyport <= txpma5_clock_index_to_phyport(txpma5_clock_select); +txpma5_clock_cram <= txpma_clock_phyport_to_cram(0) WHEN (txpma5_clock_phyport = 0) ELSE + txpma_clock_phyport_to_cram(1) WHEN (txpma5_clock_phyport = 1) ELSE + txpma_clock_phyport_to_cram(2) WHEN (txpma5_clock_phyport = 2) ELSE + txpma_clock_phyport_to_cram(3) WHEN (txpma5_clock_phyport = 3) ELSE + txpma_clock_phyport_to_cram(4) WHEN (txpma5_clock_phyport = 4) ELSE + txpma_clock_phyport_to_cram(7) WHEN (txpma5_clock_phyport = 7)ELSE + txpma_clock_phyport_to_cram(0); + +txpma5_clock_cram_phy <= txpma0_clock_cram WHEN (tx0_logical_to_physical_mapping = 5) ELSE + txpma1_clock_cram WHEN (tx1_logical_to_physical_mapping = 5) ELSE + txpma2_clock_cram WHEN (tx2_logical_to_physical_mapping = 5) ELSE + txpma3_clock_cram WHEN (tx3_logical_to_physical_mapping = 5) ELSE + txpma4_clock_cram WHEN (tx4_logical_to_physical_mapping = 5) ELSE + txpma5_clock_cram WHEN (tx5_logical_to_physical_mapping = 5) ELSE + txpma5_clock_cram; +txpma5_csr_rcgb_x_en <= txpma5_clock_cram_phy; + +-- DPRIO write - CRAM on physical +txpma5_clock_phyport_out <= convert_txpma_clock_cram_to_phyport(txpma5_dp_rcgb_x_en); + -- but the map is on logic channel +txpma5_clock_phyport_out_logic <= txpma0_clock_phyport_out WHEN (tx5_logical_to_physical_mapping = 0) ELSE + txpma1_clock_phyport_out WHEN (tx5_logical_to_physical_mapping = 1) ELSE + txpma2_clock_phyport_out WHEN (tx5_logical_to_physical_mapping = 2) ELSE + txpma3_clock_phyport_out WHEN (tx5_logical_to_physical_mapping = 3) ELSE + txpma4_clock_phyport_out WHEN (tx5_logical_to_physical_mapping = 4) ELSE + txpma5_clock_phyport_out WHEN (tx5_logical_to_physical_mapping = 5) ELSE + txpma5_clock_phyport_out; + +txpma5_clock_select_out_logic <= "000" WHEN (txpma5_clock_index_to_phyport(0) = txpma5_clock_phyport_out_logic) ELSE + "001" WHEN (txpma5_clock_index_to_phyport(1) = txpma5_clock_phyport_out_logic) ELSE + "010" WHEN (txpma5_clock_index_to_phyport(2) = txpma5_clock_phyport_out_logic) ELSE + "011" WHEN (txpma5_clock_index_to_phyport(3) = txpma5_clock_phyport_out_logic) ELSE + "100" WHEN (txpma5_clock_index_to_phyport(4) = txpma5_clock_phyport_out_logic) ELSE + "111"; -- invalid cram values + -- back to physical +txpma5_clock_select_out <= txpma0_clock_select_out_logic WHEN (tx0_logical_to_physical_mapping = 5) ELSE + txpma1_clock_select_out_logic WHEN (tx1_logical_to_physical_mapping = 5) ELSE + txpma2_clock_select_out_logic WHEN (tx2_logical_to_physical_mapping = 5) ELSE + txpma3_clock_select_out_logic WHEN (tx3_logical_to_physical_mapping = 5) ELSE + txpma4_clock_select_out_logic WHEN (tx4_logical_to_physical_mapping = 5) ELSE + txpma5_clock_select_out_logic WHEN (tx5_logical_to_physical_mapping = 5) ELSE + txpma5_clock_select_out_logic; + +txpma5_dp_clkin_sel <= txpma5_clock_select_out; + +--------------------------------------------------------------------------- +-- PLL0/PLL1 selection ---------------------------------------------------- +--------------------------------------------------------------------------- + +PROCESS -- initialize the TABLE + VARIABLE init_table : STD_LOGIC := '1'; + VARIABLE tmp_int : INTEGER := 0; + + BEGIN + IF (init_table = '1') THEN + clkdiv_pll_phyport_to_cram(CLKDIV_INCLK_SELECT_PLL0) <= '0'; + clkdiv_pll_phyport_to_cram(CLKDIV_INCLK_SELECT_PLL1) <= '1'; + clkdiv_pll_phyport_to_cram(CLKDIV_INCLK_SELECT_ERR) <= '1'; + + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv0_inclk0_logical_to_physical_mapping); + clkdiv0_pll_index_to_phyport(0) <= tmp_int; + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv0_inclk1_logical_to_physical_mapping); + clkdiv0_pll_index_to_phyport(1) <= tmp_int; + + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv1_inclk0_logical_to_physical_mapping); + clkdiv1_pll_index_to_phyport(0) <= tmp_int; + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv1_inclk1_logical_to_physical_mapping); + clkdiv1_pll_index_to_phyport(1) <= tmp_int; + + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv2_inclk0_logical_to_physical_mapping); + clkdiv2_pll_index_to_phyport(0) <= tmp_int; + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv2_inclk1_logical_to_physical_mapping); + clkdiv2_pll_index_to_phyport(1) <= tmp_int; + + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv3_inclk0_logical_to_physical_mapping); + clkdiv3_pll_index_to_phyport(0) <= tmp_int; + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv3_inclk1_logical_to_physical_mapping); + clkdiv3_pll_index_to_phyport(1) <= tmp_int; + + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv4_inclk0_logical_to_physical_mapping); + clkdiv4_pll_index_to_phyport(0) <= tmp_int; + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv4_inclk1_logical_to_physical_mapping); + clkdiv4_pll_index_to_phyport(1) <= tmp_int; + + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv5_inclk0_logical_to_physical_mapping); + clkdiv5_pll_index_to_phyport(0) <= tmp_int; + tmp_int := convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv5_inclk1_logical_to_physical_mapping); + clkdiv5_pll_index_to_phyport(1) <= tmp_int; + + init_table := '0'; + END IF; + + WAIT; +END PROCESS; -- end of initializing tables + +-- DPRIO read - logical clkdiv channel +tmp_clkdiv0_pll_select <= clkdiv0_init_inclk_select WHEN (clkdiv0_init_inclk_select = '0' OR clkdiv0_init_inclk_select = '1') ELSE '0'; +clkdiv0_pll_select <= 0 WHEN (tmp_clkdiv0_pll_select = '0') ELSE 1; +clkdiv0_pll_phyport <= clkdiv0_pll_index_to_phyport(clkdiv0_pll_select); + +clkdiv0_pll_cram <= clkdiv_pll_phyport_to_cram(clkdiv0_pll_phyport); + +-- switch to physical pll number +clkdiv0_pll_cram_phy <= clkdiv0_pll_cram WHEN (tx0_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_cram WHEN (tx1_logical_to_physical_mapping = 0) ELSE + clkdiv2_pll_cram WHEN (tx2_logical_to_physical_mapping = 0) ELSE + clkdiv3_pll_cram WHEN (tx3_logical_to_physical_mapping = 0) ELSE + clkdiv4_pll_cram WHEN (tx4_logical_to_physical_mapping = 0) ELSE + clkdiv5_pll_cram WHEN (tx5_logical_to_physical_mapping = 0) ELSE + clkdiv0_pll_cram; + +clkdiv0_csr_rcgb_cmu_sel <= clkdiv0_pll_cram_phy; + +-- DPRIO write - CRAM on physical +clkdiv0_pll_phyport_out <= convert_clkdiv_pll_cram_to_phyport(clkdiv0_dp_rcgb_cmu_sel); + -- but the map is on logic channel +clkdiv0_pll_phyport_out_logic <= clkdiv0_pll_phyport_out WHEN (tx0_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_phyport_out WHEN (tx0_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_phyport_out WHEN (tx0_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_phyport_out WHEN (tx0_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_phyport_out WHEN (tx0_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_phyport_out WHEN (tx0_logical_to_physical_mapping = 5) ELSE + clkdiv0_pll_phyport_out; + +clkdiv0_pll_select_out_logic <= '0' WHEN (clkdiv0_pll_index_to_phyport(0) = clkdiv0_pll_phyport_out_logic) ELSE + '1' WHEN (clkdiv0_pll_index_to_phyport(1) = clkdiv0_pll_phyport_out_logic) ELSE + '1'; + -- back to physical +clkdiv0_pll_select_out <= clkdiv0_pll_select_out_logic WHEN (tx0_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_select_out_logic WHEN (tx1_logical_to_physical_mapping = 0) ELSE + clkdiv2_pll_select_out_logic WHEN (tx2_logical_to_physical_mapping = 0) ELSE + clkdiv3_pll_select_out_logic WHEN (tx3_logical_to_physical_mapping = 0) ELSE + clkdiv4_pll_select_out_logic WHEN (tx4_logical_to_physical_mapping = 0) ELSE + clkdiv5_pll_select_out_logic WHEN (tx5_logical_to_physical_mapping = 0) ELSE + clkdiv0_pll_select_out_logic; + +clkdiv0_dp_inclk_select <= clkdiv0_pll_select_out; + + +-- DPRIO read - logical clkdiv channel +tmp_clkdiv1_pll_select <= clkdiv1_init_inclk_select WHEN (clkdiv1_init_inclk_select = '0' OR clkdiv1_init_inclk_select = '1') ELSE '0'; +clkdiv1_pll_select <= 0 WHEN (tmp_clkdiv1_pll_select = '0') ELSE 1; +clkdiv1_pll_phyport <= clkdiv1_pll_index_to_phyport(clkdiv1_pll_select); + +clkdiv1_pll_cram <= clkdiv_pll_phyport_to_cram(clkdiv1_pll_phyport); + +-- switch to physical pll number +clkdiv1_pll_cram_phy <= clkdiv0_pll_cram WHEN (tx0_logical_to_physical_mapping = 1) ELSE + clkdiv1_pll_cram WHEN (tx1_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_cram WHEN (tx2_logical_to_physical_mapping = 1) ELSE + clkdiv3_pll_cram WHEN (tx3_logical_to_physical_mapping = 1) ELSE + clkdiv4_pll_cram WHEN (tx4_logical_to_physical_mapping = 1) ELSE + clkdiv5_pll_cram WHEN (tx5_logical_to_physical_mapping = 1) ELSE + clkdiv1_pll_cram; + +clkdiv1_csr_rcgb_cmu_sel <= clkdiv1_pll_cram_phy; + +-- DPRIO write - CRAM on physical +clkdiv1_pll_phyport_out <= convert_clkdiv_pll_cram_to_phyport(clkdiv1_dp_rcgb_cmu_sel); + -- but the map is on logic channel +clkdiv1_pll_phyport_out_logic <= clkdiv0_pll_phyport_out WHEN (tx1_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_phyport_out WHEN (tx1_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_phyport_out WHEN (tx1_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_phyport_out WHEN (tx1_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_phyport_out WHEN (tx1_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_phyport_out WHEN (tx1_logical_to_physical_mapping = 5) ELSE + clkdiv1_pll_phyport_out; + +clkdiv1_pll_select_out_logic <= '0' WHEN (clkdiv1_pll_index_to_phyport(0) = clkdiv1_pll_phyport_out_logic) ELSE + '1' WHEN (clkdiv1_pll_index_to_phyport(1) = clkdiv1_pll_phyport_out_logic) ELSE + '1'; + -- back to physical +clkdiv1_pll_select_out <= clkdiv0_pll_select_out_logic WHEN (tx0_logical_to_physical_mapping = 1) ELSE + clkdiv1_pll_select_out_logic WHEN (tx1_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_select_out_logic WHEN (tx2_logical_to_physical_mapping = 1) ELSE + clkdiv3_pll_select_out_logic WHEN (tx3_logical_to_physical_mapping = 1) ELSE + clkdiv4_pll_select_out_logic WHEN (tx4_logical_to_physical_mapping = 1) ELSE + clkdiv5_pll_select_out_logic WHEN (tx5_logical_to_physical_mapping = 1) ELSE + clkdiv1_pll_select_out_logic; + +clkdiv1_dp_inclk_select <= clkdiv1_pll_select_out; + + +-- DPRIO read - logical clkdiv channel +tmp_clkdiv2_pll_select <= clkdiv2_init_inclk_select WHEN (clkdiv2_init_inclk_select = '0' OR clkdiv2_init_inclk_select = '1') ELSE '0'; +clkdiv2_pll_select <= 0 WHEN (tmp_clkdiv2_pll_select = '0') ELSE 1; +clkdiv2_pll_phyport <= clkdiv2_pll_index_to_phyport(clkdiv2_pll_select); + +clkdiv2_pll_cram <= clkdiv_pll_phyport_to_cram(clkdiv2_pll_phyport); + +-- switch to physical pll number +clkdiv2_pll_cram_phy <= clkdiv0_pll_cram WHEN (tx0_logical_to_physical_mapping = 2) ELSE + clkdiv1_pll_cram WHEN (tx1_logical_to_physical_mapping = 2) ELSE + clkdiv2_pll_cram WHEN (tx2_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_cram WHEN (tx3_logical_to_physical_mapping = 2) ELSE + clkdiv4_pll_cram WHEN (tx4_logical_to_physical_mapping = 2) ELSE + clkdiv5_pll_cram WHEN (tx5_logical_to_physical_mapping = 2) ELSE + clkdiv2_pll_cram; + +clkdiv2_csr_rcgb_cmu_sel <= clkdiv2_pll_cram_phy; + +-- DPRIO write - CRAM on physical +clkdiv2_pll_phyport_out <= convert_clkdiv_pll_cram_to_phyport(clkdiv2_dp_rcgb_cmu_sel); + -- but the map is on logic channel +clkdiv2_pll_phyport_out_logic <= clkdiv0_pll_phyport_out WHEN (tx2_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_phyport_out WHEN (tx2_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_phyport_out WHEN (tx2_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_phyport_out WHEN (tx2_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_phyport_out WHEN (tx2_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_phyport_out WHEN (tx2_logical_to_physical_mapping = 5) ELSE + clkdiv2_pll_phyport_out; + +clkdiv2_pll_select_out_logic <= '0' WHEN (clkdiv2_pll_index_to_phyport(0) = clkdiv2_pll_phyport_out_logic) ELSE + '1' WHEN (clkdiv2_pll_index_to_phyport(1) = clkdiv2_pll_phyport_out_logic) ELSE + '1'; + -- back to physical +clkdiv2_pll_select_out <= clkdiv0_pll_select_out_logic WHEN (tx0_logical_to_physical_mapping = 2) ELSE + clkdiv1_pll_select_out_logic WHEN (tx1_logical_to_physical_mapping = 2) ELSE + clkdiv2_pll_select_out_logic WHEN (tx2_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_select_out_logic WHEN (tx3_logical_to_physical_mapping = 2) ELSE + clkdiv4_pll_select_out_logic WHEN (tx4_logical_to_physical_mapping = 2) ELSE + clkdiv5_pll_select_out_logic WHEN (tx5_logical_to_physical_mapping = 2) ELSE + clkdiv2_pll_select_out_logic; + +clkdiv2_dp_inclk_select <= clkdiv2_pll_select_out; + + +-- DPRIO read - logical clkdiv channel +tmp_clkdiv3_pll_select <= clkdiv3_init_inclk_select WHEN (clkdiv3_init_inclk_select = '0' OR clkdiv3_init_inclk_select = '1') ELSE '0'; +clkdiv3_pll_select <= 0 WHEN (tmp_clkdiv3_pll_select = '0') ELSE 1; +clkdiv3_pll_phyport <= clkdiv3_pll_index_to_phyport(clkdiv3_pll_select); + +clkdiv3_pll_cram <= clkdiv_pll_phyport_to_cram(clkdiv3_pll_phyport); + +-- switch to physical pll number +clkdiv3_pll_cram_phy <= clkdiv0_pll_cram WHEN (tx0_logical_to_physical_mapping = 3) ELSE + clkdiv1_pll_cram WHEN (tx1_logical_to_physical_mapping = 3) ELSE + clkdiv2_pll_cram WHEN (tx2_logical_to_physical_mapping = 3) ELSE + clkdiv3_pll_cram WHEN (tx3_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_cram WHEN (tx4_logical_to_physical_mapping = 3) ELSE + clkdiv5_pll_cram WHEN (tx5_logical_to_physical_mapping = 3) ELSE + clkdiv3_pll_cram; + +clkdiv3_csr_rcgb_cmu_sel <= clkdiv3_pll_cram_phy; + +-- DPRIO write - CRAM on physical +clkdiv3_pll_phyport_out <= convert_clkdiv_pll_cram_to_phyport(clkdiv3_dp_rcgb_cmu_sel); + -- but the map is on logic channel +clkdiv3_pll_phyport_out_logic <= clkdiv0_pll_phyport_out WHEN (tx3_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_phyport_out WHEN (tx3_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_phyport_out WHEN (tx3_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_phyport_out WHEN (tx3_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_phyport_out WHEN (tx3_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_phyport_out WHEN (tx3_logical_to_physical_mapping = 5) ELSE + clkdiv3_pll_phyport_out; + +clkdiv3_pll_select_out_logic <= '0' WHEN (clkdiv3_pll_index_to_phyport(0) = clkdiv3_pll_phyport_out_logic) ELSE + '1' WHEN (clkdiv3_pll_index_to_phyport(1) = clkdiv3_pll_phyport_out_logic) ELSE + '1'; + -- back to physical +clkdiv3_pll_select_out <= clkdiv0_pll_select_out_logic WHEN (tx0_logical_to_physical_mapping = 3) ELSE + clkdiv1_pll_select_out_logic WHEN (tx1_logical_to_physical_mapping = 3) ELSE + clkdiv2_pll_select_out_logic WHEN (tx2_logical_to_physical_mapping = 3) ELSE + clkdiv3_pll_select_out_logic WHEN (tx3_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_select_out_logic WHEN (tx4_logical_to_physical_mapping = 3) ELSE + clkdiv5_pll_select_out_logic WHEN (tx5_logical_to_physical_mapping = 3) ELSE + clkdiv3_pll_select_out_logic; + +clkdiv3_dp_inclk_select <= clkdiv3_pll_select_out; + + +-- DPRIO read - logical clkdiv channel +tmp_clkdiv4_pll_select <= clkdiv4_init_inclk_select WHEN (clkdiv4_init_inclk_select = '0' OR clkdiv4_init_inclk_select = '1') ELSE '0'; +clkdiv4_pll_select <= 0 WHEN (tmp_clkdiv4_pll_select = '0') ELSE 1; +clkdiv4_pll_phyport <= clkdiv4_pll_index_to_phyport(clkdiv4_pll_select); + +clkdiv4_pll_cram <= clkdiv_pll_phyport_to_cram(clkdiv4_pll_phyport); + +-- switch to physical pll number +clkdiv4_pll_cram_phy <= clkdiv0_pll_cram WHEN (tx0_logical_to_physical_mapping = 4) ELSE + clkdiv1_pll_cram WHEN (tx1_logical_to_physical_mapping = 4) ELSE + clkdiv2_pll_cram WHEN (tx2_logical_to_physical_mapping = 4) ELSE + clkdiv3_pll_cram WHEN (tx3_logical_to_physical_mapping = 4) ELSE + clkdiv4_pll_cram WHEN (tx4_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_cram WHEN (tx5_logical_to_physical_mapping = 4) ELSE + clkdiv4_pll_cram; + +clkdiv4_csr_rcgb_cmu_sel <= clkdiv4_pll_cram_phy; + +-- DPRIO write - CRAM on physical +clkdiv4_pll_phyport_out <= convert_clkdiv_pll_cram_to_phyport(clkdiv4_dp_rcgb_cmu_sel); + -- but the map is on logic channel +clkdiv4_pll_phyport_out_logic <= clkdiv0_pll_phyport_out WHEN (tx4_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_phyport_out WHEN (tx4_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_phyport_out WHEN (tx4_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_phyport_out WHEN (tx4_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_phyport_out WHEN (tx4_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_phyport_out WHEN (tx4_logical_to_physical_mapping = 5) ELSE + clkdiv4_pll_phyport_out; + +clkdiv4_pll_select_out_logic <= '0' WHEN (clkdiv4_pll_index_to_phyport(0) = clkdiv4_pll_phyport_out_logic) ELSE + '1' WHEN (clkdiv4_pll_index_to_phyport(1) = clkdiv4_pll_phyport_out_logic) ELSE + '1'; + -- back to physical +clkdiv4_pll_select_out <= clkdiv0_pll_select_out_logic WHEN (tx0_logical_to_physical_mapping = 4) ELSE + clkdiv1_pll_select_out_logic WHEN (tx1_logical_to_physical_mapping = 4) ELSE + clkdiv2_pll_select_out_logic WHEN (tx2_logical_to_physical_mapping = 4) ELSE + clkdiv3_pll_select_out_logic WHEN (tx3_logical_to_physical_mapping = 4) ELSE + clkdiv4_pll_select_out_logic WHEN (tx4_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_select_out_logic WHEN (tx5_logical_to_physical_mapping = 4) ELSE + clkdiv4_pll_select_out_logic; + +clkdiv4_dp_inclk_select <= clkdiv4_pll_select_out; + + +-- DPRIO read - logical clkdiv channel +tmp_clkdiv5_pll_select <= clkdiv5_init_inclk_select WHEN (clkdiv5_init_inclk_select = '0' OR clkdiv5_init_inclk_select = '1') ELSE '0'; +clkdiv5_pll_select <= 0 WHEN (tmp_clkdiv5_pll_select = '0') ELSE 1; +clkdiv5_pll_phyport <= clkdiv5_pll_index_to_phyport(clkdiv5_pll_select); + +clkdiv5_pll_cram <= clkdiv_pll_phyport_to_cram(clkdiv5_pll_phyport); + +-- switch to physical pll number +clkdiv5_pll_cram_phy <= clkdiv0_pll_cram WHEN (tx0_logical_to_physical_mapping = 5) ELSE + clkdiv1_pll_cram WHEN (tx1_logical_to_physical_mapping = 5) ELSE + clkdiv2_pll_cram WHEN (tx2_logical_to_physical_mapping = 5) ELSE + clkdiv3_pll_cram WHEN (tx3_logical_to_physical_mapping = 5) ELSE + clkdiv4_pll_cram WHEN (tx4_logical_to_physical_mapping = 5) ELSE + clkdiv5_pll_cram WHEN (tx5_logical_to_physical_mapping = 5) ELSE + clkdiv5_pll_cram; + +clkdiv5_csr_rcgb_cmu_sel <= clkdiv5_pll_cram_phy; + +-- DPRIO write - CRAM on physical +clkdiv5_pll_phyport_out <= convert_clkdiv_pll_cram_to_phyport(clkdiv5_dp_rcgb_cmu_sel); + -- but the map is on logic channel +clkdiv5_pll_phyport_out_logic <= clkdiv0_pll_phyport_out WHEN (tx5_logical_to_physical_mapping = 0) ELSE + clkdiv1_pll_phyport_out WHEN (tx5_logical_to_physical_mapping = 1) ELSE + clkdiv2_pll_phyport_out WHEN (tx5_logical_to_physical_mapping = 2) ELSE + clkdiv3_pll_phyport_out WHEN (tx5_logical_to_physical_mapping = 3) ELSE + clkdiv4_pll_phyport_out WHEN (tx5_logical_to_physical_mapping = 4) ELSE + clkdiv5_pll_phyport_out WHEN (tx5_logical_to_physical_mapping = 5) ELSE + clkdiv5_pll_phyport_out; + +clkdiv5_pll_select_out_logic <= '0' WHEN (clkdiv5_pll_index_to_phyport(0) = clkdiv5_pll_phyport_out_logic) ELSE + '1' WHEN (clkdiv5_pll_index_to_phyport(1) = clkdiv5_pll_phyport_out_logic) ELSE + '1'; + -- back to physical +clkdiv5_pll_select_out <= clkdiv0_pll_select_out_logic WHEN (tx0_logical_to_physical_mapping = 5) ELSE + clkdiv1_pll_select_out_logic WHEN (tx1_logical_to_physical_mapping = 5) ELSE + clkdiv2_pll_select_out_logic WHEN (tx2_logical_to_physical_mapping = 5) ELSE + clkdiv3_pll_select_out_logic WHEN (tx3_logical_to_physical_mapping = 5) ELSE + clkdiv4_pll_select_out_logic WHEN (tx4_logical_to_physical_mapping = 5) ELSE + clkdiv5_pll_select_out_logic WHEN (tx5_logical_to_physical_mapping = 5) ELSE + clkdiv5_pll_select_out_logic; + +clkdiv5_dp_inclk_select <= clkdiv5_pll_select_out; + +END trans; + +--///////////////////////////////////////////////////////////////////////////// +-- DPRIO INDEX TABLE --------------------------------------------------------// +--///////////////////////////////////////////////////////////////////////////// + +-- make sure indices with _DP_ in the middle to distiguish from rx/tx + +-- ******************************************************************* +-- RXPLL and CMUPLL must have same indices since they share same Atom +-- ******************************************************************* + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_map IS + GENERIC ( + + -- external parameters + -- Simulation Only + clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1"; + + pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll0_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll0_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll0_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll0_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll0_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll0_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll1_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll1_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll1_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll1_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll1_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll1_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll2_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll2_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll2_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll2_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll2_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll2_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll3_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll3_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll3_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll3_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll3_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll3_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll4_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll4_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll4_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll4_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll4_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll4_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll5_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll5_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll5_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll5_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll5_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll5_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + + pll0_logical_to_physical_mapping : INTEGER := 0; + pll1_logical_to_physical_mapping : INTEGER := 1; + pll2_logical_to_physical_mapping : INTEGER := 2; + pll3_logical_to_physical_mapping : INTEGER := 3; + pll4_logical_to_physical_mapping : INTEGER := 4; + pll5_logical_to_physical_mapping : INTEGER := 5; + + refclk_divider0_logical_to_physical_mapping : INTEGER := 0; + refclk_divider1_logical_to_physical_mapping : INTEGER := 1; + + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + rx4_logical_to_physical_mapping : INTEGER := 4; + rx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + tx4_logical_to_physical_mapping : INTEGER := 4; + tx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + + -- DEBUG dump + + sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps + sim_dump_filename : STRING := "sim_dprio_dump.txt" + ); + PORT ( + cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0); + cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0); + refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + + ch0_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch1_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch2_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch3_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch0_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ch1_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ch2_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ch3_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dp_centrl_out : IN STD_LOGIC_VECTOR(703 DOWNTO 0); + dp_centrl_out_reserved : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + ch0_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch1_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch2_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch3_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch0_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + ch1_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + ch2_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + ch3_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + csr_centrl_in : OUT STD_LOGIC_VECTOR(703 DOWNTO 0); + csr_centrl_in_reserved : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0); + refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0) + ); +END cycloneiv_hssi_cmu_dprio_map; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_map IS + + COMPONENT cycloneiv_hssi_cmu_dprio_map_index + GENERIC ( + -- Simulation Only + clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1"; + + pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll0_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll0_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll0_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll0_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll0_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll0_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll1_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll1_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll1_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll1_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll1_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll1_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll2_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll2_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll2_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll2_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll2_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll2_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll3_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll3_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll3_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll3_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll3_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll3_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll4_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll4_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll4_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll4_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll4_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll4_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll5_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll5_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll5_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll5_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll5_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll5_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + + pll0_logical_to_physical_mapping : INTEGER := 0; + pll1_logical_to_physical_mapping : INTEGER := 1; + pll2_logical_to_physical_mapping : INTEGER := 2; + pll3_logical_to_physical_mapping : INTEGER := 3; + pll4_logical_to_physical_mapping : INTEGER := 4; + pll5_logical_to_physical_mapping : INTEGER := 5; + + refclk_divider0_logical_to_physical_mapping : INTEGER := 0; + refclk_divider1_logical_to_physical_mapping : INTEGER := 1; + + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + rx4_logical_to_physical_mapping : INTEGER := 4; + rx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + tx4_logical_to_physical_mapping : INTEGER := 4; + tx5_logical_to_physical_mapping : INTEGER := 5; + + + tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport" + ); + PORT ( + pll0_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll0_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll0_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll1_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll1_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll1_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll2_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll2_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll2_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll3_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll3_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll3_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll4_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll4_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll4_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pll5_init_pfd_clk_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + pll5_dp_riqclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_dp_rrefclk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_csr_riqclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_csr_rrefclk_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pll5_dp_pfd_clk_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + txpma0_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma0_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma0_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma0_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma1_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma1_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma1_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma1_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma2_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma2_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma2_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma2_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma3_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma3_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma3_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma3_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma4_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma4_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma4_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma4_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + txpma5_init_clkin_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + txpma5_csr_rcgb_x_en : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma5_dp_rcgb_x_en : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + txpma5_dp_clkin_sel : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + clkdiv0_init_inclk_select : IN STD_LOGIC; + clkdiv0_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv0_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv0_dp_inclk_select : OUT STD_LOGIC; + clkdiv1_init_inclk_select : IN STD_LOGIC; + clkdiv1_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv1_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv1_dp_inclk_select : OUT STD_LOGIC; + clkdiv2_init_inclk_select : IN STD_LOGIC; + clkdiv2_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv2_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv2_dp_inclk_select : OUT STD_LOGIC; + clkdiv3_init_inclk_select : IN STD_LOGIC; + clkdiv3_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv3_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv3_dp_inclk_select : OUT STD_LOGIC; + clkdiv4_init_inclk_select : IN STD_LOGIC; + clkdiv4_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv4_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv4_dp_inclk_select : OUT STD_LOGIC; + clkdiv5_init_inclk_select : IN STD_LOGIC; + clkdiv5_csr_rcgb_cmu_sel : OUT STD_LOGIC; + clkdiv5_dp_rcgb_cmu_sel : IN STD_LOGIC; + clkdiv5_dp_inclk_select : OUT STD_LOGIC + ); + END COMPONENT; + +-- Table1: PCS Per Channel TX Control Register 1 for Channel 0 +constant rforce_disp_DP_TXPCS_IDX_0 : integer := 0; +constant rrev_loopbk_DP_TXPCS_IDX_0 : integer := 1; +constant rtxrdclksel_DP_TXPCS_IDX_0 : integer := 2; +constant rtxwrclksel_DP_TXPCS_IDX_0 : integer := 3; +constant rfreerun_tx_DP_TXPCS_IDX_0 : integer := 4; +constant rtxurstpcs_DP_TXPCS_IDX_0 : integer := 5; +constant reserved_0_TB1_DP_TXPCS_IDX_0 : integer := 6; +constant rphfifoursttx_DP_TXPCS_IDX_0 : integer := 7; +constant rphfifopldentx_DP_TXPCS_IDX_0 : integer := 8; +constant rge_xaui_tx_DP_TXPCS_IDX_0 : integer := 9; +constant rdwidth_tx_DP_TXPCS_IDX_0 : integer := 10; +constant rtxfifo_lowlatency_en_DP_TXPCS_IDX_0 : integer := 11; +constant rib_force_disp_DP_TXPCS_IDX_0 : integer := 12; +constant rtxfifo_dis_DP_TXPCS_IDX_0 : integer := 13; +constant rforce_echar_DP_TXPCS_IDX_0 : integer := 14; +constant rforce_kchar_DP_TXPCS_IDX_0 : integer := 15; + +-- Table2: PCS Per Channel TX Control Register 2 for Channel 0 +constant rtxpcsbypass_en_DP_TXPCS_IDX_0 : integer := 16; +constant rcxpat_chnl_en_DP_TXPCS_IDX_0 : integer := 17; +constant rcxpat_chnl_en_DP_TXPCS_IDX_1 : integer := 18; +constant rbist_sel_DP_TXPCS_IDX_0 : integer := 19; +constant rbist_sel_DP_TXPCS_IDX_1 : integer := 20; +constant rbisten_tx_DP_TXPCS_IDX_0 : integer := 21; +constant rprbs_sel_DP_TXPCS_IDX_0 : integer := 22; +constant rprbs_sel_DP_TXPCS_IDX_1 : integer := 23; +constant rprbs_sel_DP_TXPCS_IDX_2 : integer := 24; +constant rprbsen_tx_DP_TXPCS_IDX_0 : integer := 25; +constant renbitrev_tx_DP_TXPCS_IDX_0 : integer := 26; +constant renpolinv_tx_DP_TXPCS_IDX_0 : integer := 27; +constant reserved_1_TB2_DP_TXPCS_IDX_0 : integer := 28; +constant reserved_0_TB2_DP_TXPCS_IDX_0 : integer := 29; +constant r8b10b_enc_ibm_en_DP_TXPCS_IDX_0 : integer := 30; +constant rendec_tx_DP_TXPCS_IDX_0 : integer := 31; + +-- Table3: PCS Per Channel TX Control Register 3 for Channel 0 +constant reserved_0_TB3_DP_TXPCS_IDX_0 : integer := 32; +constant rcid_len_tx_DP_TXPCS_IDX_0 : integer := 33; +constant rcid_len_tx_DP_TXPCS_IDX_1 : integer := 34; +constant rcid_len_tx_DP_TXPCS_IDX_2 : integer := 35; +constant rcid_len_tx_DP_TXPCS_IDX_3 : integer := 36; +constant rcid_len_tx_DP_TXPCS_IDX_4 : integer := 37; +constant rcid_len_tx_DP_TXPCS_IDX_5 : integer := 38; +constant rcid_len_tx_DP_TXPCS_IDX_6 : integer := 39; +constant rcid_len_tx_DP_TXPCS_IDX_7 : integer := 40; +constant rcid_pattern_tx_DP_TXPCS_IDX_0 : integer := 41; +constant rtxpcsclkpwdn_DP_TXPCS_IDX_0 : integer := 42; +constant rtxswing_sel_ena_DP_TXPCS_IDX_0 : integer := 43; +constant rtx_elec_idle_delay_DP_TXPCS_IDX_0 : integer := 44; +constant rtx_elec_idle_delay_DP_TXPCS_IDX_1 : integer := 45; +constant rtx_elec_idle_delay_DP_TXPCS_IDX_2 : integer := 46; +constant rtx_pipe_enable_DP_TXPCS_IDX_0 : integer := 47; + +-- Table4: PCS Per Channel TX Control Register 4 for Channel 0 +constant reserved_0_TB4_DP_TXPCS_IDX_0 : integer := 48; +constant reserved_0_TB4_DP_TXPCS_IDX_1 : integer := 49; +constant reserved_0_TB4_DP_TXPCS_IDX_2 : integer := 50; +constant reserved_0_TB4_DP_TXPCS_IDX_3 : integer := 51; +constant reserved_0_TB4_DP_TXPCS_IDX_4 : integer := 52; +constant reserved_0_TB4_DP_TXPCS_IDX_5 : integer := 53; +constant reserved_0_TB4_DP_TXPCS_IDX_6 : integer := 54; +constant reserved_0_TB4_DP_TXPCS_IDX_7 : integer := 55; +constant reserved_0_TB4_DP_TXPCS_IDX_8 : integer := 56; +constant reserved_0_TB4_DP_TXPCS_IDX_9 : integer := 57; +constant reserved_0_TB4_DP_TXPCS_IDX_10 : integer := 58; +constant reserved_0_TB4_DP_TXPCS_IDX_11 : integer := 59; +constant rtxbitslip_en_DP_TXPCS_IDX_0 : integer := 60; +constant rphfifo_regmode_tx_DP_TXPCS_IDX_0 : integer := 61; +constant rpipeline_bypass_tx_DP_TXPCS_IDX_0 : integer := 62; +constant rself_sw_en_tx_DP_TXPCS_IDX_0 : integer := 63; + +-- Table5: PCS Per Channel RX Control Register 1 for Channel 0 +constant rrxpcsbypass_en_DP_RXPCS_IDX_0 : integer := 0; +constant rall_one_dect_only_DP_RXPCS_IDX_0 : integer := 1; +constant rbist_clr_rx_DP_RXPCS_IDX_0 : integer := 2; +constant rbisten_rx_DP_RXPCS_IDX_0 : integer := 3; +constant rprbs_clr_rslt_rx_DP_RXPCS_IDX_0 : integer := 4; +constant rprbsen_rx_DP_RXPCS_IDX_0 : integer := 5; +constant rrx_rd_clk_sel_DP_RXPCS_IDX_0 : integer := 6; +constant rclk_2_sel_DP_RXPCS_IDX_0 : integer := 7; +constant rclk_2_sel_DP_RXPCS_IDX_1 : integer := 8; +constant rclk_1_sel_DP_RXPCS_IDX_0 : integer := 9; +constant rclk_1_sel_DP_RXPCS_IDX_1 : integer := 10; +constant rrcvd_clk_sel_DP_RXPCS_IDX_0 : integer := 11; +constant rrcvd_clk_sel_DP_RXPCS_IDX_1 : integer := 12; +constant rfreerun_rx_DP_RXPCS_IDX_0 : integer := 13; +constant rrxurstpcs_DP_RXPCS_IDX_0 : integer := 14; +constant reserved_0_TB5_DP_RXPCS_IDX_0 : integer := 15; + +-- Table6: PCS Per Channel RX Control Register 2 for Channel 0 +constant reserved_3_TB6_DP_RXPCS_IDX_0 : integer := 16; +constant reserved_3_TB6_33_DP_RXPCS_IDX_0 : integer := 17; +constant reserved_3_TB6_34_DP_RXPCS_IDX_0 : integer := 18; +constant reserved_3_TB6_35_DP_RXPCS_IDX_0 : integer := 19; +constant reserved_3_TB6_36_DP_RXPCS_IDX_0 : integer := 20; +constant reserved_3_TB6_37_DP_RXPCS_IDX_0 : integer := 21; +constant reserved_3_TB6_38_DP_RXPCS_IDX_0 : integer := 22; +constant reserved_3_TB6_39_DP_RXPCS_IDX_0 : integer := 23; +constant rcomp_size_DP_RXPCS_IDX_0 : integer := 24; +constant rcomp_size_DP_RXPCS_IDX_1 : integer := 25; +constant rcomp_size_DP_RXPCS_IDX_2 : integer := 26; +constant reserved_2_TB6_DP_RXPCS_IDX_0 : integer := 27; +constant rdis_rx_disp_DP_RXPCS_IDX_0 : integer := 28; +constant reserved_1_TB6_DP_RXPCS_IDX_0 : integer := 29; +constant reserved_0_TB6_DP_RXPCS_IDX_0 : integer := 30; +constant reserved_0_TB6_DP_RXPCS_IDX_1 : integer := 31; + +-- Table7: PCS Per Channel RX Control Register 3 for Channel 0 +constant rcomp_pat_16_DP_RXPCS_IDX_0 : integer := 32; +constant rcomp_pat_17_DP_RXPCS_IDX_0 : integer := 33; +constant rcomp_pat_18_DP_RXPCS_IDX_0 : integer := 34; +constant rcomp_pat_19_DP_RXPCS_IDX_0 : integer := 35; +constant rcomp_pat_20_DP_RXPCS_IDX_0 : integer := 36; +constant rcomp_pat_21_DP_RXPCS_IDX_0 : integer := 37; +constant rcomp_pat_22_DP_RXPCS_IDX_0 : integer := 38; +constant rcomp_pat_23_DP_RXPCS_IDX_0 : integer := 39; +constant rcomp_pat_24_DP_RXPCS_IDX_0 : integer := 40; +constant rcomp_pat_25_DP_RXPCS_IDX_0 : integer := 41; +constant rcomp_pat_26_DP_RXPCS_IDX_0 : integer := 42; +constant rcomp_pat_27_DP_RXPCS_IDX_0 : integer := 43; +constant rcomp_pat_28_DP_RXPCS_IDX_0 : integer := 44; +constant rcomp_pat_29_DP_RXPCS_IDX_0 : integer := 45; +constant rcomp_pat_30_DP_RXPCS_IDX_0 : integer := 46; +constant rcomp_pat_31_DP_RXPCS_IDX_0 : integer := 47; + +-- Table8: PCS Per Channel RX Control Register 4 for Channel 0 +constant rcomp_pat_0_DP_RXPCS_IDX_0 : integer := 48; +constant rcomp_pat_1_DP_RXPCS_IDX_0 : integer := 49; +constant rcomp_pat_2_DP_RXPCS_IDX_0 : integer := 50; +constant rcomp_pat_3_DP_RXPCS_IDX_0 : integer := 51; +constant rcomp_pat_4_DP_RXPCS_IDX_0 : integer := 52; +constant rcomp_pat_5_DP_RXPCS_IDX_0 : integer := 53; +constant rcomp_pat_6_DP_RXPCS_IDX_0 : integer := 54; +constant rcomp_pat_7_DP_RXPCS_IDX_0 : integer := 55; +constant rcomp_pat_8_DP_RXPCS_IDX_0 : integer := 56; +constant rcomp_pat_9_DP_RXPCS_IDX_0 : integer := 57; +constant rcomp_pat_10_DP_RXPCS_IDX_0 : integer := 58; +constant rcomp_pat_11_DP_RXPCS_IDX_0 : integer := 59; +constant rcomp_pat_12_DP_RXPCS_IDX_0 : integer := 60; +constant rcomp_pat_13_DP_RXPCS_IDX_0 : integer := 61; +constant rcomp_pat_14_DP_RXPCS_IDX_0 : integer := 62; +constant rcomp_pat_15_DP_RXPCS_IDX_0 : integer := 63; + +-- Table9: PCS Per Channel RX Control Register 5 for Channel 0 +constant rbitloc_rev_en_DP_RXPCS_IDX_0 : integer := 64; +constant rbysync_polinv_en_DP_RXPCS_IDX_0 : integer := 65; +constant reserved_0_TB9_DP_RXPCS_IDX_0 : integer := 66; +constant rosnumber_DP_RXPCS_IDX_0 : integer := 67; +constant rosnumber_DP_RXPCS_IDX_1 : integer := 68; +constant rosbased_DP_RXPCS_IDX_0 : integer := 69; +constant rkchar_DP_RXPCS_IDX_0 : integer := 70; +constant renumber_DP_RXPCS_IDX_0 : integer := 71; +constant renumber_DP_RXPCS_IDX_1 : integer := 72; +constant renumber_DP_RXPCS_IDX_2 : integer := 73; +constant renumber_DP_RXPCS_IDX_3 : integer := 74; +constant renumber_DP_RXPCS_IDX_4 : integer := 75; +constant renumber_DP_RXPCS_IDX_5 : integer := 76; +constant rib_inv_cd_DP_RXPCS_IDX_0 : integer := 77; +constant rib_inv_cd_DP_RXPCS_IDX_1 : integer := 78; +constant rsync_sm_dis_DP_RXPCS_IDX_0 : integer := 79; + +-- Table10: PCS Per Channel RX Control Register 6 for Channel 0 +constant rknumber_DP_RXPCS_IDX_0 : integer := 80; +constant rknumber_DP_RXPCS_IDX_1 : integer := 81; +constant rknumber_DP_RXPCS_IDX_2 : integer := 82; +constant rknumber_DP_RXPCS_IDX_3 : integer := 83; +constant rknumber_DP_RXPCS_IDX_4 : integer := 84; +constant rknumber_DP_RXPCS_IDX_5 : integer := 85; +constant rknumber_DP_RXPCS_IDX_6 : integer := 86; +constant rknumber_DP_RXPCS_IDX_7 : integer := 87; +constant rgnumber_DP_RXPCS_IDX_0 : integer := 88; +constant rgnumber_DP_RXPCS_IDX_1 : integer := 89; +constant rgnumber_DP_RXPCS_IDX_2 : integer := 90; +constant rgnumber_DP_RXPCS_IDX_3 : integer := 91; +constant rgnumber_DP_RXPCS_IDX_4 : integer := 92; +constant rgnumber_DP_RXPCS_IDX_5 : integer := 93; +constant rgnumber_DP_RXPCS_IDX_6 : integer := 94; +constant rgnumber_DP_RXPCS_IDX_7 : integer := 95; + +-- Table11: PCS Per Channel RX Control Register 7 for Channel 0 +constant renpolinv_rx_DP_RXPCS_IDX_0 : integer := 96; +constant reserved_0_TB11_DP_RXPCS_IDX_0 : integer := 97; +constant r8b10b_dec_ibm_en_DP_RXPCS_IDX_0 : integer := 98; +constant r8b10b_dec_ibm_en_DP_RXPCS_IDX_1 : integer := 99; +constant rendec_rx_DP_RXPCS_IDX_0 : integer := 100; +constant rautobtalg_dis_DP_RXPCS_IDX_0 : integer := 101; +constant rrlv_en_DP_RXPCS_IDX_0 : integer := 102; +constant rlp20ben_DP_RXPCS_IDX_0 : integer := 103; +constant rforce_sig_det_pcs_DP_RXPCS_IDX_0 : integer := 104; +constant reserved_1_TB11_DP_RXPCS_IDX_0 : integer := 105; +constant rrundisp_DP_RXPCS_IDX_0 : integer := 106; +constant rrundisp_DP_RXPCS_IDX_1 : integer := 107; +constant rrundisp_DP_RXPCS_IDX_2 : integer := 108; +constant rrundisp_DP_RXPCS_IDX_3 : integer := 109; +constant rrundisp_DP_RXPCS_IDX_4 : integer := 110; +constant rrundisp_DP_RXPCS_IDX_5 : integer := 111; + +-- Table12: PCS Per Channel RX Control Register 8 for Channel 0 +constant rclkcmpsq1p_DP_RXPCS_IDX_0 : integer := 112; +constant rclkcmpsq1p_DP_RXPCS_IDX_1 : integer := 113; +constant rclkcmpsq1p_DP_RXPCS_IDX_2 : integer := 114; +constant rclkcmpsq1p_DP_RXPCS_IDX_3 : integer := 115; +constant rclkcmpsq1p_DP_RXPCS_IDX_4 : integer := 116; +constant rclkcmpsq1p_DP_RXPCS_IDX_5 : integer := 117; +constant rclkcmpsq1p_DP_RXPCS_IDX_6 : integer := 118; +constant rclkcmpsq1p_DP_RXPCS_IDX_7 : integer := 119; +constant rclkcmpsq1p_DP_RXPCS_IDX_8 : integer := 120; +constant rclkcmpsq1p_DP_RXPCS_IDX_9 : integer := 121; +constant rclkcmpsqmd_DP_RXPCS_IDX_0 : integer := 122; +constant rclkcmpinsertpad_DP_RXPCS_IDX_0 : integer := 123; +constant rtruebac2bac_DP_RXPCS_IDX_0 : integer := 124; +constant rskpsetbased_DP_RXPCS_IDX_0 : integer := 125; +constant rgenericfifo_DP_RXPCS_IDX_0 : integer := 126; +constant rmatchen_DP_RXPCS_IDX_0 : integer := 127; + +-- Table13: PCS Per Channel RX Control Register 9 for Channel 0 +constant rclkcmpsq1p_10_DP_RXPCS_IDX_0 : integer := 128; +constant rclkcmpsq1p_11_DP_RXPCS_IDX_0 : integer := 129; +constant rclkcmpsq1p_12_DP_RXPCS_IDX_0 : integer := 130; +constant rclkcmpsq1p_13_DP_RXPCS_IDX_0 : integer := 131; +constant rclkcmpsq1p_14_DP_RXPCS_IDX_0 : integer := 132; +constant rclkcmpsq1p_15_DP_RXPCS_IDX_0 : integer := 133; +constant rclkcmpsq1p_16_DP_RXPCS_IDX_0 : integer := 134; +constant rclkcmpsq1p_17_DP_RXPCS_IDX_0 : integer := 135; +constant rclkcmpsq1p_18_DP_RXPCS_IDX_0 : integer := 136; +constant rclkcmpsq1p_19_DP_RXPCS_IDX_0 : integer := 137; +constant reserved_0_TB13_DP_RXPCS_IDX_0 : integer := 138; +constant rclkcmpsq1n_15_DP_RXPCS_IDX_0 : integer := 139; +constant rclkcmpsq1n_16_DP_RXPCS_IDX_0 : integer := 140; +constant rclkcmpsq1n_17_DP_RXPCS_IDX_0 : integer := 141; +constant rclkcmpsq1n_18_DP_RXPCS_IDX_0 : integer := 142; +constant rclkcmpsq1n_19_DP_RXPCS_IDX_0 : integer := 143; + +-- Table14: PCS Per Channel RX Control Register 10 for Channel 0 +constant rclkcmpsq1n_0_DP_RXPCS_IDX_0 : integer := 144; +constant rclkcmpsq1n_1_DP_RXPCS_IDX_0 : integer := 145; +constant rclkcmpsq1n_2_DP_RXPCS_IDX_0 : integer := 146; +constant rclkcmpsq1n_3_DP_RXPCS_IDX_0 : integer := 147; +constant rclkcmpsq1n_4_DP_RXPCS_IDX_0 : integer := 148; +constant rclkcmpsq1n_5_DP_RXPCS_IDX_0 : integer := 149; +constant rclkcmpsq1n_6_DP_RXPCS_IDX_0 : integer := 150; +constant rclkcmpsq1n_7_DP_RXPCS_IDX_0 : integer := 151; +constant rclkcmpsq1n_8_DP_RXPCS_IDX_0 : integer := 152; +constant rclkcmpsq1n_9_DP_RXPCS_IDX_0 : integer := 153; +constant reserved_0_TB14_DP_RXPCS_IDX_0 : integer := 154; +constant rclkcmpsq1n_10_DP_RXPCS_IDX_0 : integer := 155; +constant rclkcmpsq1n_11_DP_RXPCS_IDX_0 : integer := 156; +constant rclkcmpsq1n_12_DP_RXPCS_IDX_0 : integer := 157; +constant rclkcmpsq1n_13_DP_RXPCS_IDX_0 : integer := 158; +constant rclkcmpsq1n_14_DP_RXPCS_IDX_0 : integer := 159; + +-- Table15: PCS Per Channel RX Control Register 11 for Channel 0 +constant rfull_threshold_DP_RXPCS_IDX_0 : integer := 160; +constant rfull_threshold_DP_RXPCS_IDX_1 : integer := 161; +constant rfull_threshold_DP_RXPCS_IDX_2 : integer := 162; +constant rfull_threshold_DP_RXPCS_IDX_3 : integer := 163; +constant rfull_threshold_DP_RXPCS_IDX_4 : integer := 164; +constant rdel_threshold_DP_RXPCS_IDX_0 : integer := 165; +constant rdel_threshold_DP_RXPCS_IDX_1 : integer := 166; +constant rdel_threshold_DP_RXPCS_IDX_2 : integer := 167; +constant rdel_threshold_DP_RXPCS_IDX_3 : integer := 168; +constant rdel_threshold_DP_RXPCS_IDX_4 : integer := 169; +constant rins_threshold_DP_RXPCS_IDX_0 : integer := 170; +constant rins_threshold_DP_RXPCS_IDX_1 : integer := 171; +constant rins_threshold_DP_RXPCS_IDX_2 : integer := 172; +constant rins_threshold_DP_RXPCS_IDX_3 : integer := 173; +constant rins_threshold_DP_RXPCS_IDX_4 : integer := 174; +constant rclkcmp_pipe_en_DP_RXPCS_IDX_0 : integer := 175; + +-- Table16: PCS Per Channel RX Control Register 12 for Channel 0 +constant rfreq_sel_DP_RXPCS_IDX : integer := 176; +constant reserved_2_TB16_DP_RXPCS_IDX_1 : integer := 177; +constant rhip_ena_DP_RXPCS_IDX_0 : integer := 178; +constant rpma_done_gen_ena_DP_RXPCS_IDX_0 : integer := 179; +constant reserved_1_TB16_DP_RXPCS_IDX_0 : integer := 180; +constant reserved_1_TB16_DP_RXPCS_IDX_1 : integer := 181; +constant reserved_0_TB16_DP_RXPCS_IDX_0 : integer := 182; +constant reserved_0_TB16_DP_RXPCS_IDX_1 : integer := 183; +constant reserved_0_TB16_DP_RXPCS_IDX_2 : integer := 184; +constant reserved_0_TB16_DP_RXPCS_IDX_3 : integer := 185; +constant rstart_threshold_DP_RXPCS_IDX_0 : integer := 186; +constant rstart_threshold_DP_RXPCS_IDX_1 : integer := 187; +constant rstart_threshold_DP_RXPCS_IDX_2 : integer := 188; +constant rempty_threshold_DP_RXPCS_IDX_0 : integer := 189; +constant rempty_threshold_DP_RXPCS_IDX_1 : integer := 190; +constant rempty_threshold_DP_RXPCS_IDX_2 : integer := 191; + + +-- Table17: PCS Per Channel RX Control Register 13 for Channel 0 +constant rtest_bus_sel_DP_RXPCS_IDX_0 : integer := 192; +constant rtest_bus_sel_DP_RXPCS_IDX_1 : integer := 193; +constant rtest_bus_sel_DP_RXPCS_IDX_2 : integer := 194; +constant rtest_bus_sel_DP_RXPCS_IDX_3 : integer := 195; +constant rautoinsdis_DP_RXPCS_IDX_0 : integer := 196; +constant rphfifopldenrx_DP_RXPCS_IDX_0 : integer := 197; +constant rbytordplden_DP_RXPCS_IDX_0 : integer := 198; +constant rbyteorden_DP_RXPCS_IDX_0 : integer := 199; +constant rbyteorden_DP_RXPCS_IDX_1 : integer := 200; +constant rbytord_2sym_en_DP_RXPCS_IDX_0 : integer := 201; +constant rinvalid_code_err_only_DP_RXPCS_IDX_0 : integer := 202; +constant rcmpfifourst_DP_RXPCS_IDX_0 : integer := 203; +constant rphfifourstrx_DP_RXPCS_IDX_0 : integer := 204; +constant rdwidth_rx_DP_RXPCS_IDX_0 : integer := 205; +constant rrxfifo_lowlatency_en_DP_RXPCS_IDX_0 : integer := 206; +constant rrxfifo_dis_DP_RXPCS_IDX_0 : integer := 207; + +-- Table18: PCS Per Channel RX Control Register 14 for Channel 0 +constant rbytordpat_0_DP_RXPCS_IDX_0 : integer := 208; +constant rbytordpat_1_DP_RXPCS_IDX_0 : integer := 209; +constant rbytordpat_2_DP_RXPCS_IDX_0 : integer := 210; +constant rbytordpat_3_DP_RXPCS_IDX_0 : integer := 211; +constant rbytordpat_4_DP_RXPCS_IDX_0 : integer := 212; +constant rbytordpat_5_DP_RXPCS_IDX_0 : integer := 213; +constant rbytordpat_6_DP_RXPCS_IDX_0 : integer := 214; +constant rbytordpat_7_DP_RXPCS_IDX_0 : integer := 215; +constant rbytordpat_8_DP_RXPCS_IDX_0 : integer := 216; +constant rbytordpat_9_DP_RXPCS_IDX_0 : integer := 217; +constant reserved_0_TB18_DP_RXPCS_IDX_0 : integer := 218; +constant reserved_0_TB18_DP_RXPCS_IDX_1 : integer := 219; +constant reserved_0_TB18_DP_RXPCS_IDX_2 : integer := 220; +constant reserved_0_TB18_DP_RXPCS_IDX_3 : integer := 221; +constant reserved_0_TB18_DP_RXPCS_IDX_4 : integer := 222; +constant reserved_0_TB18_DP_RXPCS_IDX_5 : integer := 223; + +-- Table19: PCS Per Channel RX Control Register 15 for Channel 0 +constant rbytordpad_DP_RXPCS_IDX_0 : integer := 224; +constant rbytordpad_DP_RXPCS_IDX_1 : integer := 225; +constant rbytordpad_DP_RXPCS_IDX_2 : integer := 226; +constant rbytordpad_DP_RXPCS_IDX_3 : integer := 227; +constant rbytordpad_DP_RXPCS_IDX_4 : integer := 228; +constant rbytordpad_DP_RXPCS_IDX_5 : integer := 229; +constant rbytordpad_DP_RXPCS_IDX_6 : integer := 230; +constant rbytordpad_DP_RXPCS_IDX_7 : integer := 231; +constant rbytordpad_DP_RXPCS_IDX_8 : integer := 232; +constant rbytordpad_DP_RXPCS_IDX_9 : integer := 233; +constant reserved_0_TB19_DP_RXPCS_IDX_0 : integer := 234; +constant reserved_0_TB19_DP_RXPCS_IDX_1 : integer := 235; +constant reserved_0_TB19_DP_RXPCS_IDX_2 : integer := 236; +constant reserved_0_TB19_DP_RXPCS_IDX_3 : integer := 237; +constant reserved_0_TB19_DP_RXPCS_IDX_4 : integer := 238; +constant reserved_0_TB19_DP_RXPCS_IDX_5 : integer := 239; + +-- Table20: PCS Per Channel RX Control Register 16 for Channel 0 +constant rload_shreg_del_DP_RXPCS_IDX_0 : integer := 240; +constant rload_shreg_del_DP_RXPCS_IDX_1 : integer := 241; +constant rload_shreg_del_DP_RXPCS_IDX_2 : integer := 242; +constant rload_shreg_del_DP_RXPCS_IDX_3 : integer := 243; +constant rload_shreg_del_DP_RXPCS_IDX_4 : integer := 244; +constant rphystatus_rst_toggle_DP_RXPCS_IDX_0 : integer := 245; +constant reidle_com_detect_DP_RXPCS_IDX_0 : integer := 246; +constant reidle_com_detect_DP_RXPCS_IDX_1 : integer := 247; +constant rk285detect_DP_RXPCS_IDX_0 : integer := 248; +constant reidleinferenable_DP_RXPCS_IDX_0 : integer := 249; +constant rphystatus_delay_DP_RXPCS_IDX_0 : integer := 250; +constant rphystatus_delay_DP_RXPCS_IDX_1 : integer := 251; +constant rphystatus_delay_DP_RXPCS_IDX_2 : integer := 252; +constant rind_error_reporting_DP_RXPCS_IDX_0 : integer := 253; +constant rrx_detect_bypass_DP_RXPCS_IDX_0 : integer := 254; +constant rrx_pipe_enable_DP_RXPCS_IDX_0 : integer := 255; + +-- Table21: PCS Per Channel RX Control Register 17 for Channel 0 +constant rpma_done_count_0_DP_RXPCS_IDX_0 : integer := 256; +constant rpma_done_count_1_DP_RXPCS_IDX_0 : integer := 257; +constant rpma_done_count_2_DP_RXPCS_IDX_0 : integer := 258; +constant rpma_done_count_3_DP_RXPCS_IDX_0 : integer := 259; +constant rpma_done_count_4_DP_RXPCS_IDX_0 : integer := 260; +constant rpma_done_count_5_DP_RXPCS_IDX_0 : integer := 261; +constant rpma_done_count_6_DP_RXPCS_IDX_0 : integer := 262; +constant rpma_done_count_7_DP_RXPCS_IDX_0 : integer := 263; +constant rpma_done_count_8_DP_RXPCS_IDX_0 : integer := 264; +constant rpma_done_count_9_DP_RXPCS_IDX_0 : integer := 265; +constant rpma_done_count_10_DP_RXPCS_IDX_0 : integer := 266; +constant rpma_done_count_11_DP_RXPCS_IDX_0 : integer := 267; +constant rpma_done_count_12_DP_RXPCS_IDX_0 : integer := 268; +constant rpma_done_count_13_DP_RXPCS_IDX_0 : integer := 269; +constant rpma_done_count_14_DP_RXPCS_IDX_0 : integer := 270; +constant rpma_done_count_15_DP_RXPCS_IDX_0 : integer := 271; + +-- Table22: PCS Per Channel RX Control Register 18 for Channel 0 +constant reserved_0_TB22_DP_RXPCS_IDX_0 : integer := 272; +constant reserved_0_TB22_DP_RXPCS_IDX_1 : integer := 273; +constant reserved_0_TB22_DP_RXPCS_IDX_2 : integer := 274; +constant reserved_0_TB22_DP_RXPCS_IDX_3 : integer := 275; +constant reserved_0_TB22_DP_RXPCS_IDX_4 : integer := 276; +constant reserved_0_TB22_DP_RXPCS_IDX_5 : integer := 277; +constant reserved_0_TB22_DP_RXPCS_IDX_6 : integer := 278; +constant reserved_0_TB22_DP_RXPCS_IDX_7 : integer := 279; +constant reserved_0_TB22_DP_RXPCS_IDX_8 : integer := 280; +constant reserved_1_TB22_DP_RXPCS_IDX_0 : integer := 281; +constant rbytord_6g_mask_en_DP_RXPCS_IDX_0 : integer := 282; +constant rbytord_s2gx_DP_RXPCS_IDX_0 : integer := 283; +constant reserved_2_TB22_DP_RXPCS_IDX_0 : integer := 284; +constant rcdr_ctrl_en_DP_RXPCS_IDX_0 : integer := 285; +constant rrxpcsclkpwdn_DP_RXPCS_IDX_0 : integer := 286; +constant rerr_flags_sel_DP_RXPCS_IDX_0 : integer := 287; + +-- Table23: PCS Per Channel RX Control Register 19 for Channel 0 +constant rwait_count_DP_RXPCS_IDX_0 : integer := 288; +constant rwait_count_DP_RXPCS_IDX_1 : integer := 289; +constant rwait_count_DP_RXPCS_IDX_2 : integer := 290; +constant rwait_count_DP_RXPCS_IDX_3 : integer := 291; +constant rwait_count_DP_RXPCS_IDX_4 : integer := 292; +constant rwait_count_DP_RXPCS_IDX_5 : integer := 293; +constant rwait_count_DP_RXPCS_IDX_6 : integer := 294; +constant rwait_count_DP_RXPCS_IDX_7 : integer := 295; +constant reserved_0_TB23_DP_RXPCS_IDX_0 : integer := 296; +constant reserved_0_TB23_DP_RXPCS_IDX_1 : integer := 297; +constant reserved_0_TB23_DP_RXPCS_IDX_2 : integer := 298; +constant reserved_0_TB23_DP_RXPCS_IDX_3 : integer := 299; +constant reserved_0_TB23_DP_RXPCS_IDX_4 : integer := 300; +constant reserved_0_TB23_DP_RXPCS_IDX_5 : integer := 301; +constant reserved_0_TB23_DP_RXPCS_IDX_6 : integer := 302; +constant reserved_0_TB23_DP_RXPCS_IDX_7 : integer := 303; + +-- Table24: PCS Per Channel RX Control Register 20 for Channel 0 +constant rfts_count_DP_RXPCS_IDX_0 : integer := 304; +constant rfts_count_DP_RXPCS_IDX_1 : integer := 305; +constant rfts_count_DP_RXPCS_IDX_2 : integer := 306; +constant rfts_count_DP_RXPCS_IDX_3 : integer := 307; +constant rfts_count_DP_RXPCS_IDX_4 : integer := 308; +constant rfts_count_DP_RXPCS_IDX_5 : integer := 309; +constant rfts_count_DP_RXPCS_IDX_6 : integer := 310; +constant rfts_count_DP_RXPCS_IDX_7 : integer := 311; +constant rfts_count_DP_RXPCS_IDX_8 : integer := 312; +constant rfts_count_DP_RXPCS_IDX_9 : integer := 313; +constant rwait_for_phfifo_cnt_DP_RXPCS_IDX_0 : integer := 314; +constant rwait_for_phfifo_cnt_DP_RXPCS_IDX_1 : integer := 315; +constant rwait_for_phfifo_cnt_DP_RXPCS_IDX_2 : integer := 316; +constant rwait_for_phfifo_cnt_DP_RXPCS_IDX_3 : integer := 317; +constant rwait_for_phfifo_cnt_DP_RXPCS_IDX_4 : integer := 318; +constant rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : integer := 319; + +-- Table25: PCS Per Channel RX Control Register 21 for Channel 0 +constant rppm_meas_delay_DP_RXPCS_IDX_0 : integer := 320; +constant rcid_len_rx_DP_RXPCS_IDX_0 : integer := 321; +constant rcid_len_rx_DP_RXPCS_IDX_1 : integer := 322; +constant rcid_len_rx_DP_RXPCS_IDX_2 : integer := 323; +constant rcid_len_rx_DP_RXPCS_IDX_3 : integer := 324; +constant rcid_len_rx_DP_RXPCS_IDX_4 : integer := 325; +constant rcid_len_rx_DP_RXPCS_IDX_5 : integer := 326; +constant rcid_len_rx_DP_RXPCS_IDX_6 : integer := 327; +constant rcid_len_rx_DP_RXPCS_IDX_7 : integer := 328; +constant rcid_pattern_rx_DP_RXPCS_IDX_0 : integer := 329; +constant rpcs_wrapback_en_DP_RXPCS_IDX_0 : integer := 330; +constant reserved_0_TB25_DP_RXPCS_IDX_0 : integer := 331; +constant reserved_0_TB25_DP_RXPCS_IDX_1 : integer := 332; +constant reserved_0_TB25_DP_RXPCS_IDX_2 : integer := 333; +constant reserved_0_TB25_DP_RXPCS_IDX_3 : integer := 334; +constant reserved_0_TB25_DP_RXPCS_IDX_4 : integer := 335; + +-- Table26: PCS Per Channel RX Control Register 22 for Channel 0 +constant rauto_pc_en_cnt_DP_RXPCS_IDX_0 : integer := 336; +constant rauto_pc_en_cnt_DP_RXPCS_IDX_1 : integer := 337; +constant rauto_pc_en_cnt_DP_RXPCS_IDX_2 : integer := 338; +constant rauto_pc_en_cnt_DP_RXPCS_IDX_3 : integer := 339; +constant rauto_pc_en_cnt_DP_RXPCS_IDX_4 : integer := 340; +constant reserved_1_TB26_DP_RXPCS_IDX_0 : integer := 341; +constant rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_0 : integer := 342; +constant rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_1 : integer := 343; +constant rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_2 : integer := 344; +constant rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_3 : integer := 345; +constant reserved_0_TB26_DP_RXPCS_IDX_0 : integer := 346; +constant rpipeline_bypass_rx_DP_RXPCS_IDX_0 : integer := 347; +constant rself_sw_en_rx_DP_RXPCS_IDX_0 : integer := 348; +constant rrxvalid_mask_DP_RXPCS_IDX_0 : integer := 349; +constant rcid_en_DP_RXPCS_IDX_0 : integer := 350; +constant rphfifo_regmode_rx_DP_RXPCS_IDX_0 : integer := 351; + +-- Table27: PCS Per Channel RX Control Register 23 for Channel 0 +constant rmask_count_DP_RXPCS_IDX_0 : integer := 352; +constant rmask_count_DP_RXPCS_IDX_1 : integer := 353; +constant rmask_count_DP_RXPCS_IDX_2 : integer := 354; +constant rmask_count_DP_RXPCS_IDX_3 : integer := 355; +constant rmask_count_DP_RXPCS_IDX_4 : integer := 356; +constant rmask_count_DP_RXPCS_IDX_5 : integer := 357; +constant rmask_count_DP_RXPCS_IDX_6 : integer := 358; +constant rmask_count_DP_RXPCS_IDX_7 : integer := 359; +constant rmask_count_DP_RXPCS_IDX_8 : integer := 360; +constant rmask_count_DP_RXPCS_IDX_9 : integer := 361; +constant rgen1_sigdet_ena_DP_RXPCS_IDX_0 : integer := 362; +constant riei_eios_priority_dis_DP_RXPCS_IDX_0 : integer := 363; +constant reserved_0_TB27_DP_RXPCS_IDX_0 : integer := 364; +constant reserved_0_TB27_DP_RXPCS_IDX_1 : integer := 365; +constant reserved_0_TB27_DP_RXPCS_IDX_2 : integer := 366; +constant reserved_0_TB27_DP_RXPCS_IDX_3 : integer := 367; + +-- Table28: PMA Per Channel TX Control Register 1 for Channel 0 +constant rpowdnt_TXPMA_IDX_0 : integer := 0; +constant reserved_0_TB28_TXPMA_IDX_1 : integer := 1; +constant reserved_0_TB28_TXPMA_IDX_2 : integer := 2; +constant reserved_0_TB28_TXPMA_IDX_3 : integer := 3; +constant reserved_0_TB28_TXPMA_IDX_4 : integer := 4; +constant reserved_0_TB28_TXPMA_IDX_5 : integer := 5; +constant reserved_0_TB28_TXPMA_IDX_6 : integer := 6; +constant reserved_0_TB28_TXPMA_IDX_7 : integer := 7; +constant reserved_0_TB28_TXPMA_IDX_8 : integer := 8; +constant reserved_0_TB28_TXPMA_IDX_9 : integer := 9; +constant reserved_0_TB28_TXPMA_IDX_10 : integer := 10; +constant reserved_0_TB28_TXPMA_IDX_11 : integer := 11; +constant reserved_0_TB28_TXPMA_IDX_12 : integer := 12; +constant rvod_sel_non_pcie_TXPMA_IDX_0 : integer := 13; +constant rvod_sel_non_pcie_TXPMA_IDX_1 : integer := 14; +constant rvod_sel_non_pcie_TXPMA_IDX_2 : integer := 15; + +-- Table29: PMA Per Channel TX Control Register 2 for Channel 0 +constant reserved_0_TB29_TXPMA_IDX_0 : integer := 16; +constant reserved_0_TB29_TXPMA_IDX_1 : integer := 17; +constant reserved_0_TB29_TXPMA_IDX_2 : integer := 18; +constant reserved_0_TB29_TXPMA_IDX_3 : integer := 19; +constant reserved_0_TB29_TXPMA_IDX_4 : integer := 20; +constant reserved_0_TB29_TXPMA_IDX_5 : integer := 21; +constant reserved_0_TB29_TXPMA_IDX_6 : integer := 22; +constant reserved_0_TB29_TXPMA_IDX_7 : integer := 23; +constant reserved_0_TB29_TXPMA_IDX_8 : integer := 24; +constant reserved_0_TB29_TXPMA_IDX_9 : integer := 25; +constant reserved_0_TB29_TXPMA_IDX_10 : integer := 26; +constant rpre_em_1t_no_pcie_TXPMA_IDX_0 : integer := 27; +constant rpre_em_1t_no_pcie_TXPMA_IDX_1 : integer := 28; +constant rpre_em_1t_no_pcie_TXPMA_IDX_2 : integer := 29; +constant rpre_em_1t_no_pcie_TXPMA_IDX_3 : integer := 30; +constant rpre_em_1t_no_pcie_TXPMA_IDX_4 : integer := 31; + +-- Table30: PMA Per Channel TX Control Register 3 for Channel 0 +constant reserved_0_TB30_TXPMA_IDX_0 : integer := 32; +constant reserved_0_TB30_TXPMA_IDX_1 : integer := 33; +constant reserved_0_TB30_TXPMA_IDX_2 : integer := 34; +constant reserved_0_TB30_TXPMA_IDX_3 : integer := 35; +constant reserved_0_TB30_TXPMA_IDX_4 : integer := 36; +constant reserved_0_TB30_TXPMA_IDX_5 : integer := 37; +constant reserved_0_TB30_TXPMA_IDX_6 : integer := 38; +constant reserved_0_TB30_TXPMA_IDX_7 : integer := 39; +constant reserved_0_TB30_TXPMA_IDX_8 : integer := 40; +constant reserved_0_TB30_TXPMA_IDX_9 : integer := 41; +constant reserved_0_TB30_TXPMA_IDX_10 : integer := 42; +constant reserved_0_TB30_TXPMA_IDX_11 : integer := 43; +constant reserved_0_TB30_TXPMA_IDX_12 : integer := 44; +constant reserved_0_TB30_TXPMA_IDX_13 : integer := 45; +constant reserved_0_TB30_TXPMA_IDX_14 : integer := 46; +constant reserved_0_TB30_TXPMA_IDX_15 : integer := 47; + +-- Table31: PMA Per Channel TX Control Register 4 for Channel 0 +constant rlowv_TXPMA_IDX_0 : integer := 48; +constant rrx_det_TXPMA_IDX_0 : integer := 49; +constant rrx_det_TXPMA_IDX_1 : integer := 50; +constant reserved_0_TB31_TXPMA_IDX_3 : integer := 51; +constant reserved_0_TB31_TXPMA_IDX_4 : integer := 52; +constant rslew_TXPMA_IDX_0 : integer := 53; +constant rslew_TXPMA_IDX_1 : integer := 54; +constant rtx_lst_TXPMA_IDX_0 : integer := 55; +constant rtx_lst_TXPMA_IDX_1 : integer := 56; +constant rtx_lst_TXPMA_IDX_2 : integer := 57; +constant rtx_lst_TXPMA_IDX_3 : integer := 58; +constant rtx_vtt_TXPMA_IDX_0 : integer := 59; +constant rtx_vtt_TXPMA_IDX_1 : integer := 60; +constant rtx_term_sel_TXPMA_IDX_0 : integer := 61; +constant rtx_term_sel_TXPMA_IDX_1 : integer := 62; +constant rtx_term_sel_TXPMA_IDX_2 : integer := 63; + +-- Table32: PMA Per Channel TX Control Register 5 for Channel 0 +constant reserved_1_TB32_TXPMA_IDX_0 : integer := 64; +constant reserved_1_TB32_TXPMA_IDX_1 : integer := 65; +constant reserved_1_TB32_TXPMA_IDX_2 : integer := 66; +constant reserved_1_TB32_TXPMA_IDX_3 : integer := 67; +constant reserved_1_TB32_TXPMA_IDX_4 : integer := 68; +constant reserved_1_TB32_TXPMA_IDX_5 : integer := 69; +constant reserved_1_TB32_TXPMA_IDX_6 : integer := 70; +constant reserved_1_TB32_TXPMA_IDX_7 : integer := 71; +constant reserved_1_TB32_TXPMA_IDX_8 : integer := 72; +constant reserved_1_TB32_TXPMA_IDX_9 : integer := 73; +constant reserved_1_TB32_TXPMA_IDX_10 : integer := 74; +constant rtx_ob_pdb_TXPMA_IDX_0 : integer := 75; +constant reserved_0_TB32_TXPMA_IDX_0 : integer := 76; +constant r_dft_sel_TXPMA_IDX_0 : integer := 77; +constant r_dft_sel_TXPMA_IDX_1 : integer := 78; +constant r_dft_sel_TXPMA_IDX_2 : integer := 79; + +-- Table33: PMA Per Channel TX Control Register 6 for Channel 0 +constant reserved_0_TB33_DP_TXPMA_IDX_0 : integer := 80; +constant reserved_0_TB33_DP_TXPMA_IDX_1 : integer := 81; +constant reserved_0_TB33_DP_TXPMA_IDX_2 : integer := 82; +constant reserved_0_TB33_DP_TXPMA_IDX_3 : integer := 83; +constant rtx_cgb_pdb_DP_TXPMA_IDX_0 : integer := 84; +constant rpclksel_DP_TXPMA_IDX_0 : integer := 85; +constant rdynamic_sw_DP_TXPMA_IDX_0 : integer := 86; +constant rs_lpbk_DP_TXPMA_IDX_0 : integer := 87; +constant rcgb_delay_sel_DP_TXPMA_IDX_0 : integer := 88; +constant rpmadwidth_tx_DP_TXPMA_IDX_0 : integer := 89; +constant rpma_doublewidth_tx_DP_TXPMA_IDX_0 : integer := 90; +constant rcgb_m_sel_DP_TXPMA_IDX_0 : integer := 91; +constant rcgb_m_sel_DP_TXPMA_IDX_1 : integer := 92; +constant rcgb_cmu_sel_DP_TXPMA_IDX_0 : integer := 93; +constant rcgb_x_en_DP_TXPMA_IDX_0 : integer := 94; +constant rcgb_x_en_DP_TXPMA_IDX_1 : integer := 95; + +-- Table35: PMA Per Channel TX Control Register 8 for Channel 0 +constant rpma_reserved_0_TB35_TXPMA_IDX_0 : integer := 96; +constant rpma_reserved_0_TB35_TXPMA_IDX_1 : integer := 97; +constant rpma_reserved_0_TB35_TXPMA_IDX_2 : integer := 98; +constant rpma_reserved_0_TB35_TXPMA_IDX_3 : integer := 99; +constant rpma_reserved_0_TB35_TXPMA_IDX_4 : integer := 100; +constant rpma_reserved_0_TB35_TXPMA_IDX_5 : integer := 101; +constant rpma_reserved_0_TB35_TXPMA_IDX_6 : integer := 102; +constant rpma_reserved_0_TB35_TXPMA_IDX_7 : integer := 103; +constant rpma_reserved_0_TB35_TXPMA_IDX_8 : integer := 104; +constant rpma_reserved_0_TB35_TXPMA_IDX_9 : integer := 105; +constant rpma_reserved_0_TB35_TXPMA_IDX_10 : integer := 106; +constant rpma_reserved_0_TB35_TXPMA_IDX_11 : integer := 107; +constant rpma_reserved_0_TB35_TXPMA_IDX_12 : integer := 108; +constant rpma_reserved_0_TB35_TXPMA_IDX_13 : integer := 109; +constant rpma_reserved_0_TB35_TXPMA_IDX_14 : integer := 110; +constant rpma_reserved_0_TB35_TXPMA_IDX_15 : integer := 111; + +-- Table34: PMA Per Channel TX Control Register 7 for Channel 0 (RX PMA) +constant ricdr_reserved_0_TB34_TXPMA_IDX_0 : integer := 0; +constant ricdr_reserved_0_TB34_TXPMA_IDX_1 : integer := 1; +constant ricdr_reserved_1_TB34_TXPMA_IDX_0 : integer := 2; +constant ricdr_reserved_1_TB34_TXPMA_IDX_1 : integer := 3; +constant ricdr_reserved_2_TB34_TXPMA_IDX_0 : integer := 4; +constant ricdr_reserved_2_TB34_TXPMA_IDX_1 : integer := 5; +constant ricdr_ssc_enable : integer := 6; +constant ricdr_en_local_clkdiv : integer := 7; +constant ricdr_rlocdiv_TXPMA_IDX_0 : integer := 8; +constant ricdr_rlocdiv_TXPMA_IDX_1 : integer := 9; +constant ricdr_rlocdiv_TXPMA_IDX_2 : integer := 10; +constant ricdr_rlocdiv_TXPMA_IDX_3 : integer := 11; +constant ricdr_rlocdiv_TXPMA_IDX_4 : integer := 12; +constant ricdr_rlocdiv_TXPMA_IDX_5 : integer := 13; +constant ricdr_rlocdiv_TXPMA_IDX_6 : integer := 14; +constant ricdr_rlocdiv_TXPMA_IDX_7 : integer := 15; + + +-- Table36: PMA Per Channel RX Control Register 1 for Channel 0 +constant rrx_term_sel_RXPMA_IDX_0 : integer := 16; +constant rrx_term_sel_RXPMA_IDX_1 : integer := 17; +constant rrx_term_sel_RXPMA_IDX_2 : integer := 18; +constant rrx_vtt_RXPMA_IDX_0 : integer := 19; +constant rrx_vtt_RXPMA_IDX_1 : integer := 20; +constant rrx_vtt_RXPMA_IDX_2 : integer := 21; +constant rrx_s_rdlpbk_RXPMA_IDX_0 : integer := 22; +constant rrx_bit_dc_RXPMA_IDX_0 : integer := 23; +constant rrx_bit_dc_RXPMA_IDX_1 : integer := 24; +constant rrx_bit_dc_RXPMA_IDX_2 : integer := 25; +constant rrx_bit_dc_RXPMA_IDX_3 : integer := 26; +constant rrx_lst_RXPMA_IDX_0 : integer := 27; +constant rrx_lst_RXPMA_IDX_1 : integer := 28; +constant rrx_lst_RXPMA_IDX_2 : integer := 29; +constant rrx_lst_RXPMA_IDX_3 : integer := 30; +constant rrx_lst_RXPMA_IDX_4 : integer := 31; + +-- Table37: PMA Per Channel RX Control Register 2 for Channel 0 +constant rrxurstpma_RXPMA_IDX_0 : integer := 32; +constant rrx_test_RXPMA_IDX_0 : integer := 33; +constant rrx_sd_force_RXPMA_IDX_0 : integer := 34; +constant rrx_oc_RXPMA_IDX_0 : integer := 35; +constant rrx_oc_RXPMA_IDX_1 : integer := 36; +constant rrx_oc_RXPMA_IDX_2 : integer := 37; +constant rrx_oc_RXPMA_IDX_3 : integer := 38; +constant rrx_oc_RXPMA_IDX_4 : integer := 39; +constant rrx_oc_RXPMA_IDX_5 : integer := 40; +constant rrx_oc_RXPMA_IDX_6 : integer := 41; +constant rrx_oc_RXPMA_IDX_7 : integer := 42; +constant rrx_oc_en_RXPMA_IDX_0 : integer := 43; +constant rrx_sdlv_RXPMA_IDX_0 : integer := 44; +constant rrx_sdlv_RXPMA_IDX_1 : integer := 45; +constant rrx_sdlv_RXPMA_IDX_2 : integer := 46; +constant rrx_sdlv_RXPMA_IDX_3 : integer := 47; + +-- Table38: PMA Per Channel RX Control Register 3 for Channel 0 +constant reserved_0_TB38_RXPMA_IDX_0 : integer := 48; +constant reserved_0_TB38_RXPMA_IDX_1 : integer := 49; +constant reserved_0_TB38_RXPMA_IDX_2 : integer := 50; +constant rpowdnr_RXPMA_IDX_0 : integer := 51; +constant rrx_ib_pdb_RXPMA_IDX_0 : integer := 52; +constant rurx_pdb_RXPMA_IDX_0 : integer := 53; +constant rrx_oc_calpd_RXPMA_IDX_0 : integer := 54; +constant rrx_sd_off_RXPMA_IDX_0 : integer := 55; +constant rrx_sd_off_RXPMA_IDX_1 : integer := 56; +constant rrx_sd_off_RXPMA_IDX_2 : integer := 57; +constant rrx_sd_off_RXPMA_IDX_3 : integer := 58; +constant rrx_sd_off_RXPMA_IDX_4 : integer := 59; +constant rrx_sd_on_RXPMA_IDX_0 : integer := 60; +constant rrx_sd_on_RXPMA_IDX_1 : integer := 61; +constant rrx_sd_on_RXPMA_IDX_2 : integer := 62; +constant rrx_sd_on_RXPMA_IDX_3 : integer := 63; + +-- Table39: PMA Per Channel RX Control Register 4 for Channel 0 +constant ricdr_freq_sel_pi_IDX_0 : integer := 64; +constant ricdr_freq_sel_pi_IDX_1 : integer := 65; +constant ricdr_rdefact_IDX_0 : integer := 66; +constant ricdr_rdefact_IDX_1 : integer := 67; +constant ricdr_rdefact_IDX_2 : integer := 68; +constant ricdr_rdefact_IDX_3 : integer := 69; +constant ricdr_rcl_prst_IDX_0 : integer := 70; +constant ricdr_rcl_prst_IDX_1 : integer := 71; +constant ricdr_rcl_prst_IDX_2 : integer := 72; +constant ricdr_rcl_prst_IDX_3 : integer := 73; +constant ricdr_rcl_prst_IDX_4 : integer := 74; +constant ricdr_rcl_prst_IDX_5 : integer := 75; +constant ricdr_rcl_prst_IDX_6 : integer := 76; +constant ricdr_rcl_prst_IDX_7 : integer := 77; +constant ricdr_rcl_hi_DP : integer := 78; +constant ricdr_rcl_lo_DP : integer := 79; + +-- Table40: PMA Per Channel RX Control Register 5 for Channel 0 +constant ricdr_rcl_hi_tb40_IDX_0 : integer := 80; +constant ricdr_rcl_hi_tb40_IDX_1 : integer := 81; +constant ricdr_rcl_hi_tb40_IDX_2 : integer := 82; +constant ricdr_rcl_hi_tb40_IDX_3 : integer := 83; +constant ricdr_rcl_hi_tb40_IDX_4 : integer := 84; +constant ricdr_rcl_hi_tb40_IDX_5 : integer := 85; +constant ricdr_rcl_hi_tb40_IDX_6 : integer := 86; +constant ricdr_rcl_hi_tb40_IDX_7 : integer := 87; +constant ricdr_rcl_lo_tb40_IDX_0 : integer := 88; +constant ricdr_rcl_lo_tb40_IDX_1 : integer := 89; +constant ricdr_rcl_lo_tb40_IDX_2 : integer := 90; +constant ricdr_rcl_lo_tb40_IDX_3 : integer := 91; +constant ricdr_rcl_lo_tb40_IDX_4 : integer := 92; +constant ricdr_rcl_lo_tb40_IDX_5 : integer := 93; +constant ricdr_rcl_lo_tb40_IDX_6 : integer := 94; +constant ricdr_rcl_lo_tb40_IDX_7 : integer := 95; + +-- Table41: PMA Per Channel RX Control Register 6 for Channel 0 +constant reserved_0_tb41_IDX_0 : integer := 96; +constant reserved_1_tb41_IDX_0 : integer := 97; +constant reserved_2_tb41_IDX_0 : integer := 98; +constant reserved_2_tb41_IDX_1 : integer := 99; +constant reserved_2_tb41_IDX_2 : integer := 100; +constant reserved_2_tb41_IDX_3 : integer := 101; +constant reserved_3_tb41_IDX_0 : integer := 102; +constant reserved_3_tb41_IDX_1 : integer := 103; +constant rclocktree_reserved_tb41_IDX_0 : integer := 104; +constant rclocktree_reserved_tb41_IDX_1 : integer := 105; +constant reserved_4_tb41_IDX_0 : integer := 106; +constant reserved_5_tb41_IDX_0 : integer := 107; +constant rrx_cru_pdb_IDX_0 : integer := 108; +constant rltr_IDX_0 : integer := 109; +constant rltd_IDX_0 : integer := 110; +constant reserved_6_tb41_IDX_0 : integer := 111; + +-- Table42: PMA Per Channel RX Control Register 7 for Channel 0 +constant rphsel_clkdivrx_RXPMA_IDX_0 : integer := 112; +constant rrisedge_RXPMA_IDX_0 : integer := 113; +constant rpdof_en_RXPMA_IDX_0 : integer := 114; +constant rcntfact_RXPMA_IDX_0 : integer := 115; +constant rcntfact_RXPMA_IDX_1 : integer := 116; +constant rcntfact_RXPMA_IDX_2 : integer := 117; +constant rcntfact2_RXPMA_IDX_0 : integer := 118; +constant rcntfact2_RXPMA_IDX_1 : integer := 119; +constant rcntfact2_RXPMA_IDX_2 : integer := 120; +constant ropt1_RXPMA_IDX_0 : integer := 121; +constant rrtest_RXPMA_IDX_0 : integer := 122; +constant rrtest2_RXPMA_IDX_0 : integer := 123; +constant ricdrclkout_RXPMA_IDX_0 : integer := 124; +constant rtxfclkout_RXPMA_IDX_0 : integer := 125; +constant rjtaglp_RXPMA_IDX_2 : integer := 126; +constant reserved_0_tb42_IDX_0 : integer := 127; + +-- Table43: PMA Per Channel RX Control Register 8 for Channel 0 +constant rloopback1_RXPMA_IDX_0 : integer := 128; +constant rloopback2_RXPMA_IDX_0 : integer := 129; +constant rloopback3_RXPMA_IDX_0 : integer := 130; +constant rendpa_RXPMA_IDX_0 : integer := 131; +constant rup_RXPMA_IDX_0 : integer := 132; +constant rdn_RXPMA_IDX_0 : integer := 133; +constant rtxclk_en_b_RXPMA_IDX_0 : integer := 134; +constant rtxclk_en_t_RXPMA_IDX_0 : integer := 135; +constant rfrefmx_RXPMA_IDX_0 : integer := 136; +constant rtxclk_divmx_RXPMA_IDX_0 : integer := 137; +constant rtxloadmx_RXPMA_IDX_0 : integer := 138; +constant rtxfclkmx_RXPMA_IDX_0 : integer := 139; +constant rntri_icdrtree_RXPMA_IDX_0 : integer := 140; +constant rntri_lvdstree_RXPMA_IDX_0 : integer := 141; +constant rsel_lvdstree_RXPMA_IDX_0 : integer := 142; +constant reserved_0_TB43_RXPMA_IDX_0 : integer := 143; + +-- Table44: PMA Per Channel RX Control Register 9 for Channel 0 +constant rclk_sd_RXPMA_IDX_0 : integer := 144; +constant rclk_sd_RXPMA_IDX_1 : integer := 145; +constant rtestenp_sd_RXPMA_IDX_0 : integer := 146; +constant rtestenn_sd_RXPMA_IDX_0 : integer := 147; +constant rshiften_RXPMA_IDX_0 : integer := 148; +constant radd_RXPMA_IDX_0 : integer := 149; +constant radd_RXPMA_IDX_1 : integer := 150; +constant rsub_RXPMA_IDX_0 : integer := 151; +constant rsub_RXPMA_IDX_1 : integer := 152; +constant rphenable_RXPMA_IDX_0 : integer := 153; +constant rprst_RXPMA_IDX_0 : integer := 154; +constant rprst_RXPMA_IDX_1 : integer := 155; +constant rprst_RXPMA_IDX_2 : integer := 156; +constant rprst_RXPMA_IDX_3 : integer := 157; +constant rprst_RXPMA_IDX_4 : integer := 158; +constant rprst_RXPMA_IDX_5 : integer := 159; + +-- Table45: PMA Per Channel RX Control Register 10 for Channel 0 +constant rppm_cnt_reset_RXPMA_IDX_0 : integer := 160; +constant rforce1_freqdet_RXPMA_IDX_1 : integer := 161; +constant rforce0_freqdet_RXPMA_IDX_0 : integer := 162; +constant rppmsel_RXPMA_IDX_0 : integer := 163; +constant rppmsel_RXPMA_IDX_1 : integer := 164; +constant rppmsel_RXPMA_IDX_2 : integer := 165; +constant rppmsel_RXPMA_IDX_3 : integer := 166; +constant rppmsel_RXPMA_IDX_4 : integer := 167; +constant rppmsel_RXPMA_IDX_5 : integer := 168; +constant reserved_0_TB45_RXPMA_IDX_0 : integer := 169; +constant reserved_0_TB45_RXPMA_IDX_1 : integer := 170; +constant reserved_0_TB45_RXPMA_IDX_2 : integer := 171; +constant reserved_0_TB45_RXPMA_IDX_3 : integer := 172; +constant reserved_1_TB45_RXPMA_IDX_4 : integer := 173; +constant rpmadwidth_rx_RXPMA_IDX_0 : integer := 174; +constant reserved_2_TB45_RXPMA_IDX_0 : integer := 175; + +-- Table46: PMA Per Channel RX Control Register 11 for Channel 0 +constant reserved_0_TB46_RXPMA_IDX_0 : integer := 176; +constant reserved_0_TB46_RXPMA_IDX_1 : integer := 177; +constant reserved_0_TB46_RXPMA_IDX_2 : integer := 178; +constant reserved_0_TB46_RXPMA_IDX_3 : integer := 179; +constant reserved_0_TB46_RXPMA_IDX_4 : integer := 180; +constant reserved_0_TB46_RXPMA_IDX_5 : integer := 181; +constant reserved_0_TB46_RXPMA_IDX_6 : integer := 182; +constant reserved_0_TB46_RXPMA_IDX_7 : integer := 183; +constant rppm_gen1_2xcnt_en_RXPMA_IDX_0 : integer := 184; +constant rppm_post_eidle_del_RXPMA_IDX_0 : integer := 185; +constant r_dfe_2t_RXPMA_IDX_0 : integer := 186; +constant r_dfe_2t_RXPMA_IDX_1 : integer := 187; +constant r_dfe_2t_RXPMA_IDX_2 : integer := 188; +constant r_dfe_1t_RXPMA_IDX_0 : integer := 189; +constant r_dfe_1t_RXPMA_IDX_1 : integer := 190; +constant r_dfe_1t_RXPMA_IDX_2 : integer := 191; + +-- Table47: PMA Per Channel RX Control Register 12 for Channel 0 +constant reqv_set_RXPMA_IDX_0 : integer := 192; +constant reqv_set_RXPMA_IDX_1 : integer := 193; +constant reqv_set_RXPMA_IDX_2 : integer := 194; +constant reqd_set_RXPMA_IDX_0 : integer := 195; +constant reqd_set_RXPMA_IDX_1 : integer := 196; +constant reqd_set_RXPMA_IDX_2 : integer := 197; +constant reqc_set_RXPMA_IDX_0 : integer := 198; +constant reqc_set_RXPMA_IDX_1 : integer := 199; +constant reqc_set_RXPMA_IDX_2 : integer := 200; +constant reqb_set_RXPMA_IDX_0 : integer := 201; +constant reqb_set_RXPMA_IDX_1 : integer := 202; +constant reqb_set_RXPMA_IDX_2 : integer := 203; +constant reqa_set_RXPMA_IDX_0 : integer := 204; +constant reqa_set_RXPMA_IDX_1 : integer := 205; +constant reqa_set_RXPMA_IDX_2 : integer := 206; +constant reserved_0_TB47_RXPMA_IDX_0 : integer := 207; +--------------------------------------------------------------- +-- Manual section due to one ICD CRAM mapped to multiple Atoms +--------------------------------------------------------------- +-- Manual: TX_PCS section ------------------------------------- +constant rauto_speed_ena_DP_TXPCS_IDX : integer := 64; +constant rendec_data_sel_tx_DP_TXPCS_IDX : integer := 65; +constant rfreq_sel_DP_TXPCS_IDX : integer := 66; +constant rhip_ena_DP_TXPCS_IDX : integer := 67; +constant rindv_tx_DP_TXPCS_IDX : integer := 68; +constant rphfifo_master_sel_tx_TXPCS_IDX : integer := 69; +constant rpma_doublewidth_tx_TXPCS_IDX : integer := 70; +constant rpmadwidth_tx_DP_TXPCS_IDX : integer := 71; +constant rtx_cmu_sel_DP_TXPCS_IDX : integer := 72; +constant rmaster_tx_DP_TXPCS_IDX : integer := 73; +constant rmaster_up_tx_DP_TXPCS_IDX : integer := 74; + +-- Manual: RX PMA section ------------------------------------- +constant rloopback1 : integer := 203; +constant rloopback3 : integer := 204; +constant rrevlb_sw_RXPMA_IDX : integer := 291; +constant rs_lpbk_DP_RXPMA_IDX : integer := 292; -- match rx_pma.RRX_S_LPBK_RXPMA_IDX +constant rpmadwidth_rx_RXPCS_IDX : integer := 368; +constant rpma_doublewidth_rx_DP_RXPCS_IDX : integer := 369; + +-- RX portion of global_ctrl 1 +--constant rphfifo_master_sel_rx_DP_RXPCS_IDX +constant rendec_data_sel_rx_DP_RXPCS_IDX : integer := 370; +constant rdeskewen_DP_RXPCS_IDX : integer := 371; +constant rindv_rx_DP_RXPCS_IDX : integer := 372; + +-- RX portion of global_ctrl 2 +constant rdskposdisp_DP_RXPCS_IDX : integer := 373; +--constant ralgnopt_DP_RXPCS_IDX +--constant rdskchrp[9:0] + +-- RX portion of global_ctrl 3 +constant rmaster_rx_DP_RXPCS_IDX : integer := 374; +constant rmaster_up_rx_DP_RXPCS_IDX : integer := 375; + +-- not used - legacy from rx_pcs.v +constant rdwidth_rx_DP_RXPCS_IDX : integer := 380; +constant rtx_idle_delay_DP_RXPCS_IDX_0 : integer := 381; +constant rtx_idle_delay_DP_RXPCS_IDX_1 : integer := 382; +constant rclkcmppos_DP_RXPCS_IDX : integer := 383; +constant rppmsel_DP_RXPCS_IDX_0 : integer := 384; +constant rppmsel_DP_RXPCS_IDX_5 : integer := 385; +constant rforce0_freqdet_DP_RXPCS_IDX : integer := 386; +constant rforce1_freqdet_DP_RXPCS_IDX : integer := 387; +constant rs_lpbk_DP_RXPCS_IDX : integer := 388; +constant rrx_revlb_sw_DP_RXPCS_IDX : integer := 389; + +-- central clock divider section +constant rfreerun_centrl_DP_CLOCK_DIV_IDX : integer := 10; +constant rcentrl_clk_sel_DP_CLOCK_DIV_IDX : integer := 11; +constant rrefclk_out_div2_DP_CLOCK_DIV_IDX : integer := 12; + +-- CMU-central PCS section - (FIFO ptr, xaui sm) +--constant rxaui_s2gx_en_rx_DP_CENTRL_PCS_IDX : integer := 10; +--constant rxaui_s2gx_en_tx_DP_CENTRL_PCS_IDX : integer := 11; + +-- Manual: PLL (only rx_cdr_pll uses it: table 33 & 59) -------------- +constant rdynamic_sw_DP_PLL_IDX_0 : integer := 70; -- continue PLL index + +--==================================================================== +-- Manually added code to handle PLL clock select indices = +--==================================================================== +constant PFD_CLK_SELECT_DP_PLL_IDX_0 : integer := 100; +constant PFD_CLK_SELECT_DP_PLL_IDX_1 : integer := 101; +constant PFD_CLK_SELECT_DP_PLL_IDX_2 : integer := 102; +constant PFD_CLK_SELECT_DP_PLL_IDX_3 : integer := 103; + +SIGNAL pll0_init_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); -- logical index from (log0)PLL_Atom +SIGNAL pll0_dp_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); -- logical index to (Phy0)PLL_Atom +SIGNAL pll0_csr_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); -- PHY to DPRIO +SIGNAL pll0_csr_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll0_dp_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); -- PHY from DPRIO +SIGNAL pll0_dp_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + +SIGNAL pll1_init_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll1_dp_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll1_csr_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll1_csr_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll1_dp_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll1_dp_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + +SIGNAL pll2_init_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll2_dp_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll2_csr_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll2_csr_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll2_dp_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll2_dp_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + +SIGNAL pll3_init_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll3_dp_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll3_csr_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll3_csr_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll3_dp_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll3_dp_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + +SIGNAL pll4_init_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll4_dp_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll4_csr_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll4_csr_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll4_dp_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll4_dp_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + +SIGNAL pll5_init_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll5_dp_pfd_clk_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); +SIGNAL pll5_csr_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll5_csr_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll5_dp_riqclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); +SIGNAL pll5_dp_rrefclk_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + +--==================================================================== +-- Manually added code to handle TXPMA clock select indices = +--==================================================================== +constant CLKIN_SELECT_DP_TXPMA_IDX_0 : integer := 200; +constant CLKIN_SELECT_DP_TXPMA_IDX_1 : integer := 201; +constant CLKIN_SELECT_DP_TXPMA_IDX_2 : integer := 202; + +SIGNAL txpma0_init_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index from log0 Atom +SIGNAL txpma0_dp_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index to PHY0 Atom +SIGNAL txpma0_csr_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY to DPRIO +SIGNAL txpma0_dp_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY from DPRIO + +SIGNAL txpma1_init_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index from PHY0 Atom +SIGNAL txpma1_dp_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index to PHY0 Atom +SIGNAL txpma1_csr_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY to DPRIO +SIGNAL txpma1_dp_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY from DPRIO + +SIGNAL txpma2_init_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index from PHY0 Atom +SIGNAL txpma2_dp_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index to PHY0 Atom +SIGNAL txpma2_csr_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY to DPRIO +SIGNAL txpma2_dp_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY from DPRIO + +SIGNAL txpma3_init_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index from PHY0 Atom +SIGNAL txpma3_dp_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index to PHY0 Atom +SIGNAL txpma3_csr_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY to DPRIO +SIGNAL txpma3_dp_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY from DPRIO + +SIGNAL txpma4_init_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index from PHY0 Atom +SIGNAL txpma4_dp_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index to PHY0 Atom +SIGNAL txpma4_csr_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY to DPRIO +SIGNAL txpma4_dp_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY from DPRIO + +SIGNAL txpma5_init_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index from PHY0 Atom +SIGNAL txpma5_dp_clkin_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); -- logical index to PHY0 Atom +SIGNAL txpma5_csr_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY to DPRIO +SIGNAL txpma5_dp_rcgb_x_en : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PHY from DPRIO + +--==================================================================== +-- Manually added code to handle clkdiv PLL0/1 select = +--==================================================================== +constant INCLK_SELECT_DP_CLOCK_DIV_IDX : integer := 0; + +SIGNAL clkdiv0_init_inclk_select : STD_LOGIC; -- logical index from logic Atom +SIGNAL clkdiv0_dp_inclk_select : STD_LOGIC; -- logical index to PHY Atom +SIGNAL clkdiv0_csr_rcgb_cmu_sel : STD_LOGIC; -- PHY to DPRIO +SIGNAL clkdiv0_dp_rcgb_cmu_sel : STD_LOGIC; -- PHY from DPRIO + +SIGNAL clkdiv1_init_inclk_select : STD_LOGIC; -- logical index from PHY1 Atom +SIGNAL clkdiv1_dp_inclk_select : STD_LOGIC; -- logical index to PHY1 Atom +SIGNAL clkdiv1_csr_rcgb_cmu_sel : STD_LOGIC; -- PHY to DPRIO +SIGNAL clkdiv1_dp_rcgb_cmu_sel : STD_LOGIC; -- PHY from DPRIO + +SIGNAL clkdiv2_init_inclk_select : STD_LOGIC; -- logical index from PHY2 Atom +SIGNAL clkdiv2_dp_inclk_select : STD_LOGIC; -- logical index to PHY2 Atom +SIGNAL clkdiv2_csr_rcgb_cmu_sel : STD_LOGIC; -- PHY to DPRIO +SIGNAL clkdiv2_dp_rcgb_cmu_sel : STD_LOGIC; -- PHY from DPRIO + +SIGNAL clkdiv3_init_inclk_select : STD_LOGIC; -- logical index from PHY3 Atom +SIGNAL clkdiv3_dp_inclk_select : STD_LOGIC; -- logical index to PHY3 Atom +SIGNAL clkdiv3_csr_rcgb_cmu_sel : STD_LOGIC; -- PHY to DPRIO +SIGNAL clkdiv3_dp_rcgb_cmu_sel : STD_LOGIC; -- PHY from DPRIO + +SIGNAL clkdiv4_init_inclk_select : STD_LOGIC; -- logical index from PHY4 Atom +SIGNAL clkdiv4_dp_inclk_select : STD_LOGIC; -- logical index to PHY4 Atom +SIGNAL clkdiv4_csr_rcgb_cmu_sel : STD_LOGIC; -- PHY to DPRIO +SIGNAL clkdiv4_dp_rcgb_cmu_sel : STD_LOGIC; -- PHY from DPRIO + +SIGNAL clkdiv5_init_inclk_select : STD_LOGIC; -- logical index from PHY5 Atom +SIGNAL clkdiv5_dp_inclk_select : STD_LOGIC; -- logical index to PHY5 Atom +SIGNAL clkdiv5_csr_rcgb_cmu_sel : STD_LOGIC; -- PHY to DPRIO +SIGNAL clkdiv5_dp_rcgb_cmu_sel : STD_LOGIC; -- PHY from DPRIO + +--------------------------------------------------------------- +-- Phy channel in ICD ----------------------------------------- +--------------------------------------------------------------- +SIGNAL ch0_in_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +-- reserved +SIGNAL ch0_in_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +SIGNAL ch0_in_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_in_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_in_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_in_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch0_out_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch1_out_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch2_out_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ch3_out_chnl_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + +--------------------------------------------------------------- +-- TXPCS CRAM ------------------------------------------------- +--------------------------------------------------------------- +SIGNAL ch0_txpcsdprioin_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch1_txpcsdprioin_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch2_txpcsdprioin_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch3_txpcsdprioin_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); + +SIGNAL ch0_txpcsdprioin_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch1_txpcsdprioin_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch2_txpcsdprioin_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch3_txpcsdprioin_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); + +SIGNAL ch0_txpcsdprioout_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch1_txpcsdprioout_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch2_txpcsdprioout_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch3_txpcsdprioout_logic : STD_LOGIC_VECTOR(149 DOWNTO 0); + +SIGNAL ch0_txpcsdprioout_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch1_txpcsdprioout_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch2_txpcsdprioout_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); +SIGNAL ch3_txpcsdprioout_phy : STD_LOGIC_VECTOR(149 DOWNTO 0); + +--------------------------------------------------------------- +-- RXPCS CRAM ------------------------------------------------- +--------------------------------------------------------------- +SIGNAL ch0_rxpcsdprioin_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch1_rxpcsdprioin_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch2_rxpcsdprioin_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch3_rxpcsdprioin_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); + +SIGNAL ch0_rxpcsdprioin_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch1_rxpcsdprioin_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch2_rxpcsdprioin_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch3_rxpcsdprioin_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); + +SIGNAL ch0_rxpcsdprioout_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch1_rxpcsdprioout_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch2_rxpcsdprioout_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch3_rxpcsdprioout_logic : STD_LOGIC_VECTOR(399 DOWNTO 0); + +SIGNAL ch0_rxpcsdprioout_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch1_rxpcsdprioout_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch2_rxpcsdprioout_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); +SIGNAL ch3_rxpcsdprioout_phy : STD_LOGIC_VECTOR(399 DOWNTO 0); + +--------------------------------------------------------------- +-- TXPMA CRAM ------------------------------------------------- +--------------------------------------------------------------- +SIGNAL ch0_txpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_txpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_txpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_txpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_txpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_txpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); + +SIGNAL ch0_txpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_txpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_txpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_txpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_txpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_txpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); + + +SIGNAL ch0_txpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_txpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_txpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_txpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_txpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_txpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); + + +SIGNAL ch0_txpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_txpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_txpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_txpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_txpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_txpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); + + + +--------------------------------------------------------------- +-- RXPMA CRAM ------------------------------------------------- +--------------------------------------------------------------- +SIGNAL ch0_rxpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxpmadprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); + +SIGNAL ch0_rxpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxpmadprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); + +SIGNAL ch0_rxpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxpmadprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); + +SIGNAL ch0_rxpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxpmadprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); + +--------------------------------------------------------------- +-- PLL CRAM ------------------------------------------------- +--------------------------------------------------------------- +SIGNAL ch0_rxplldprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxplldprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxplldprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxplldprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxtxplldprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxtxplldprioin_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); + +SIGNAL ch0_rxplldprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxplldprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxplldprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxplldprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxtxplldprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxtxplldprioin_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); + +SIGNAL ch0_rxplldprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxplldprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxplldprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxplldprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxtxplldprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxtxplldprioout_logic : STD_LOGIC_VECTOR(299 DOWNTO 0); + +SIGNAL ch0_rxplldprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch1_rxplldprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch2_rxplldprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch3_rxplldprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch4_rxtxplldprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); +SIGNAL ch5_rxtxplldprioout_phy : STD_LOGIC_VECTOR(299 DOWNTO 0); + +--------------------------------------------------------------- +-- CMUDivider CRAM -------------------------------------------- +--------------------------------------------------------------- +SIGNAL ch0_cmudividerdprioin_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch1_cmudividerdprioin_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch2_cmudividerdprioin_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch3_cmudividerdprioin_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch4_cmudividerdprioin_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch5_cmudividerdprioin_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); + +SIGNAL ch0_cmudividerdprioin_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch1_cmudividerdprioin_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch2_cmudividerdprioin_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch3_cmudividerdprioin_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch4_cmudividerdprioin_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch5_cmudividerdprioin_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); + +SIGNAL ch0_cmudividerdprioout_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch1_cmudividerdprioout_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch2_cmudividerdprioout_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch3_cmudividerdprioout_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch4_cmudividerdprioout_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch5_cmudividerdprioout_logic : STD_LOGIC_VECTOR(99 DOWNTO 0); + +SIGNAL ch0_cmudividerdprioout_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch1_cmudividerdprioout_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch2_cmudividerdprioout_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch3_cmudividerdprioout_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch4_cmudividerdprioout_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); +SIGNAL ch5_cmudividerdprioout_phy : STD_LOGIC_VECTOR(99 DOWNTO 0); + +--==================================================================== +-- Manually added code to handle 5th/6th PMA = +-- === begin = +-- use ch4/5_in_chnl ch4/5_out_chnl interacting with Quartus Int Con = +-- use cmu0 and cmu1 to interface ICD/Phy = +--==================================================================== +SIGNAL ch4_in_chnl_ctrl_28, cmu0_in_centrl_ctrl_1 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_29, cmu0_in_centrl_ctrl_2 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_30, cmu0_in_centrl_ctrl_3 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_31, cmu0_in_centrl_ctrl_4 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_32, cmu0_in_centrl_ctrl_5 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_33, cmu0_in_centrl_ctrl_6 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_34, cmu0_in_centrl_ctrl_7 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_35, cmu0_in_centrl_ctrl_8 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_36, cmu0_in_centrl_ctrl_9 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_37, cmu0_in_centrl_ctrl_10 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_38, cmu0_in_centrl_ctrl_11 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_39, cmu0_in_centrl_ctrl_12 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_40, cmu0_in_centrl_ctrl_13 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_41, cmu0_in_centrl_ctrl_14 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_42, cmu0_in_centrl_ctrl_15 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_43, cmu0_in_centrl_ctrl_16 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_44, cmu0_in_centrl_ctrl_17 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_45, cmu0_in_centrl_ctrl_18 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_46, cmu0_in_centrl_ctrl_19 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_in_chnl_ctrl_47, cmu0_in_centrl_ctrl_20 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +SIGNAL ch5_in_chnl_ctrl_28, cmu1_in_centrl_ctrl_1 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_29, cmu1_in_centrl_ctrl_2 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_30, cmu1_in_centrl_ctrl_3 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_31, cmu1_in_centrl_ctrl_4 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_32, cmu1_in_centrl_ctrl_5 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_33, cmu1_in_centrl_ctrl_6 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_34, cmu1_in_centrl_ctrl_7 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_35, cmu1_in_centrl_ctrl_8 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_36, cmu1_in_centrl_ctrl_9 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_37, cmu1_in_centrl_ctrl_10 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_38, cmu1_in_centrl_ctrl_11 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_39, cmu1_in_centrl_ctrl_12 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_40, cmu1_in_centrl_ctrl_13 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_41, cmu1_in_centrl_ctrl_14 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_42, cmu1_in_centrl_ctrl_15 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_43, cmu1_in_centrl_ctrl_16 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_44, cmu1_in_centrl_ctrl_17 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_45, cmu1_in_centrl_ctrl_18 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_46, cmu1_in_centrl_ctrl_19 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_in_chnl_ctrl_47, cmu1_in_centrl_ctrl_20 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +-- CMU only or global +SIGNAL cmu0_in_centrl_ctrl_21, cmu1_in_centrl_ctrl_21 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL cmu_in_centrl_global_0, cmu_in_centrl_global_1 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL cmu_in_centrl_global_2, cmu_in_centrl_global_3 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +SIGNAL ch4_out_chnl_ctrl_28, cmu0_out_centrl_ctrl_1 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_29, cmu0_out_centrl_ctrl_2 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_30, cmu0_out_centrl_ctrl_3 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_31, cmu0_out_centrl_ctrl_4 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_32, cmu0_out_centrl_ctrl_5 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_33, cmu0_out_centrl_ctrl_6 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_34, cmu0_out_centrl_ctrl_7 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_35, cmu0_out_centrl_ctrl_8 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_36, cmu0_out_centrl_ctrl_9 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_37, cmu0_out_centrl_ctrl_10 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_38, cmu0_out_centrl_ctrl_11 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_39, cmu0_out_centrl_ctrl_12 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_40, cmu0_out_centrl_ctrl_13 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_41, cmu0_out_centrl_ctrl_14 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_42, cmu0_out_centrl_ctrl_15 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_43, cmu0_out_centrl_ctrl_16 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_44, cmu0_out_centrl_ctrl_17 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_45, cmu0_out_centrl_ctrl_18 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_46, cmu0_out_centrl_ctrl_19 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch4_out_chnl_ctrl_47, cmu0_out_centrl_ctrl_20 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +SIGNAL ch5_out_chnl_ctrl_28, cmu1_out_centrl_ctrl_1 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_29, cmu1_out_centrl_ctrl_2 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_30, cmu1_out_centrl_ctrl_3 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_31, cmu1_out_centrl_ctrl_4 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_32, cmu1_out_centrl_ctrl_5 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_33, cmu1_out_centrl_ctrl_6 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_34, cmu1_out_centrl_ctrl_7 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_35, cmu1_out_centrl_ctrl_8 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_36, cmu1_out_centrl_ctrl_9 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_37, cmu1_out_centrl_ctrl_10 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_38, cmu1_out_centrl_ctrl_11 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_39, cmu1_out_centrl_ctrl_12 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_40, cmu1_out_centrl_ctrl_13 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_41, cmu1_out_centrl_ctrl_14 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_42, cmu1_out_centrl_ctrl_15 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_43, cmu1_out_centrl_ctrl_16 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_44, cmu1_out_centrl_ctrl_17 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_45, cmu1_out_centrl_ctrl_18 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_46, cmu1_out_centrl_ctrl_19 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL ch5_out_chnl_ctrl_47, cmu1_out_centrl_ctrl_20 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +-- CMU only or global +SIGNAL cmu0_out_centrl_ctrl_21, cmu1_out_centrl_ctrl_21 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL cmu_out_centrl_global_0, cmu_out_centrl_global_1 : STD_LOGIC_VECTOR (15 DOWNTO 0); +SIGNAL cmu_out_centrl_global_2, cmu_out_centrl_global_3 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +--============================================================ +-- Manually added code to handle 5th/6th PMA ================= +-- === end = +--============================================================ + +BEGIN + +--------------------------------------------------------------- +-- read in para and populate csr ------------------------------ +--------------------------------------------------------------- +-- TXPCS +ch0_txpcsdprioin_logic <= txpcsdprioin (149 DOWNTO 0); +ch1_txpcsdprioin_logic <= txpcsdprioin (299 DOWNTO 150); +ch2_txpcsdprioin_logic <= txpcsdprioin (449 DOWNTO 300); +ch3_txpcsdprioin_logic <= txpcsdprioin (599 DOWNTO 450); +-- RXPCS +ch0_rxpcsdprioin_logic <= rxpcsdprioin (399 DOWNTO 0); +ch1_rxpcsdprioin_logic <= rxpcsdprioin (799 DOWNTO 400); +ch2_rxpcsdprioin_logic <= rxpcsdprioin (1199 DOWNTO 800); +ch3_rxpcsdprioin_logic <= rxpcsdprioin (1599 DOWNTO 1200); +-- TXPMA +ch0_txpmadprioin_logic <= txpmadprioin (299 DOWNTO 0); +ch1_txpmadprioin_logic <= txpmadprioin (599 DOWNTO 300); +ch2_txpmadprioin_logic <= txpmadprioin (899 DOWNTO 600); +ch3_txpmadprioin_logic <= txpmadprioin (1199 DOWNTO 900); + +-- RXPMA +ch0_rxpmadprioin_logic <= rxpmadprioin (299 DOWNTO 0); +ch1_rxpmadprioin_logic <= rxpmadprioin (599 DOWNTO 300); +ch2_rxpmadprioin_logic <= rxpmadprioin (899 DOWNTO 600); +ch3_rxpmadprioin_logic <= rxpmadprioin (1199 DOWNTO 900); + +-- PLL +ch0_rxplldprioin_logic <= cmuplldprioin (299 DOWNTO 0); +ch1_rxplldprioin_logic <= cmuplldprioin (599 DOWNTO 300); +ch2_rxplldprioin_logic <= cmuplldprioin (899 DOWNTO 600); +ch3_rxplldprioin_logic <= cmuplldprioin (1199 DOWNTO 900); +ch4_rxtxplldprioin_logic <= cmuplldprioin (1499 DOWNTO 1200); +ch5_rxtxplldprioin_logic <= cmuplldprioin (1799 DOWNTO 1500); +-- CMUDivider +ch0_cmudividerdprioin_logic <= cmudividerdprioin (99 DOWNTO 0); +ch1_cmudividerdprioin_logic <= cmudividerdprioin (199 DOWNTO 100); +ch2_cmudividerdprioin_logic <= cmudividerdprioin (299 DOWNTO 200); +ch3_cmudividerdprioin_logic <= cmudividerdprioin (399 DOWNTO 300); +ch4_cmudividerdprioin_logic <= cmudividerdprioin (499 DOWNTO 400); +ch5_cmudividerdprioin_logic <= cmudividerdprioin (599 DOWNTO 500); + +-- ------- logic to physical mapping ------------------------- +-- TXPCS +ch0_txpcsdprioin_phy <= ch0_txpcsdprioin_logic WHEN (tx0_logical_to_physical_mapping = 0) ELSE + ch1_txpcsdprioin_logic WHEN (tx1_logical_to_physical_mapping = 0) ELSE + ch2_txpcsdprioin_logic WHEN (tx2_logical_to_physical_mapping = 0) ELSE + ch3_txpcsdprioin_logic WHEN (tx3_logical_to_physical_mapping = 0) ELSE + ch0_txpcsdprioin_logic; + +ch1_txpcsdprioin_phy <= ch0_txpcsdprioin_logic WHEN (tx0_logical_to_physical_mapping = 1) ELSE + ch1_txpcsdprioin_logic WHEN (tx1_logical_to_physical_mapping = 1) ELSE + ch2_txpcsdprioin_logic WHEN (tx2_logical_to_physical_mapping = 1) ELSE + ch3_txpcsdprioin_logic WHEN (tx3_logical_to_physical_mapping = 1) ELSE + ch1_txpcsdprioin_logic; + +ch2_txpcsdprioin_phy <= ch0_txpcsdprioin_logic WHEN (tx0_logical_to_physical_mapping = 2) ELSE + ch1_txpcsdprioin_logic WHEN (tx1_logical_to_physical_mapping = 2) ELSE + ch2_txpcsdprioin_logic WHEN (tx2_logical_to_physical_mapping = 2) ELSE + ch3_txpcsdprioin_logic WHEN (tx3_logical_to_physical_mapping = 2) ELSE + ch2_txpcsdprioin_logic; + +ch3_txpcsdprioin_phy <= ch0_txpcsdprioin_logic WHEN (tx0_logical_to_physical_mapping = 3) ELSE + ch1_txpcsdprioin_logic WHEN (tx1_logical_to_physical_mapping = 3) ELSE + ch2_txpcsdprioin_logic WHEN (tx2_logical_to_physical_mapping = 3) ELSE + ch3_txpcsdprioin_logic WHEN (tx3_logical_to_physical_mapping = 3) ELSE + ch3_txpcsdprioin_logic; + +-- RXPCS +ch0_rxpcsdprioin_phy <= ch0_rxpcsdprioin_logic WHEN (rx0_logical_to_physical_mapping = 0) ELSE + ch1_rxpcsdprioin_logic WHEN (rx1_logical_to_physical_mapping = 0) ELSE + ch2_rxpcsdprioin_logic WHEN (rx2_logical_to_physical_mapping = 0) ELSE + ch3_rxpcsdprioin_logic WHEN (rx3_logical_to_physical_mapping = 0) ELSE + ch0_rxpcsdprioin_logic; + +ch1_rxpcsdprioin_phy <= ch0_rxpcsdprioin_logic WHEN (rx0_logical_to_physical_mapping = 1) ELSE + ch1_rxpcsdprioin_logic WHEN (rx1_logical_to_physical_mapping = 1) ELSE + ch2_rxpcsdprioin_logic WHEN (rx2_logical_to_physical_mapping = 1) ELSE + ch3_rxpcsdprioin_logic WHEN (rx3_logical_to_physical_mapping = 1) ELSE + ch1_rxpcsdprioin_logic; + +ch2_rxpcsdprioin_phy <= ch0_rxpcsdprioin_logic WHEN (rx0_logical_to_physical_mapping = 2) ELSE + ch1_rxpcsdprioin_logic WHEN (rx1_logical_to_physical_mapping = 2) ELSE + ch2_rxpcsdprioin_logic WHEN (rx2_logical_to_physical_mapping = 2) ELSE + ch3_rxpcsdprioin_logic WHEN (rx3_logical_to_physical_mapping = 2) ELSE + ch2_rxpcsdprioin_logic; + +ch3_rxpcsdprioin_phy <= ch0_rxpcsdprioin_logic WHEN (rx0_logical_to_physical_mapping = 3) ELSE + ch1_rxpcsdprioin_logic WHEN (rx1_logical_to_physical_mapping = 3) ELSE + ch2_rxpcsdprioin_logic WHEN (rx2_logical_to_physical_mapping = 3) ELSE + ch3_rxpcsdprioin_logic WHEN (rx3_logical_to_physical_mapping = 3) ELSE + ch3_rxpcsdprioin_logic; + +-- TXPMA +ch0_txpmadprioin_phy <= ch0_txpmadprioin_logic WHEN (tx0_logical_to_physical_mapping = 0) ELSE + ch1_txpmadprioin_logic WHEN (tx1_logical_to_physical_mapping = 0) ELSE + ch2_txpmadprioin_logic WHEN (tx2_logical_to_physical_mapping = 0) ELSE + ch3_txpmadprioin_logic WHEN (tx3_logical_to_physical_mapping = 0) ELSE + ch4_txpmadprioin_logic WHEN (tx4_logical_to_physical_mapping = 0) ELSE + ch5_txpmadprioin_logic WHEN (tx5_logical_to_physical_mapping = 0) ELSE + ch0_txpmadprioin_logic; + +ch1_txpmadprioin_phy <= ch0_txpmadprioin_logic WHEN (tx0_logical_to_physical_mapping = 1) ELSE + ch1_txpmadprioin_logic WHEN (tx1_logical_to_physical_mapping = 1) ELSE + ch2_txpmadprioin_logic WHEN (tx2_logical_to_physical_mapping = 1) ELSE + ch3_txpmadprioin_logic WHEN (tx3_logical_to_physical_mapping = 1) ELSE + ch4_txpmadprioin_logic WHEN (tx4_logical_to_physical_mapping = 1) ELSE + ch5_txpmadprioin_logic WHEN (tx5_logical_to_physical_mapping = 1) ELSE + ch1_txpmadprioin_logic; + +ch2_txpmadprioin_phy <= ch0_txpmadprioin_logic WHEN (tx0_logical_to_physical_mapping = 2) ELSE + ch1_txpmadprioin_logic WHEN (tx1_logical_to_physical_mapping = 2) ELSE + ch2_txpmadprioin_logic WHEN (tx2_logical_to_physical_mapping = 2) ELSE + ch3_txpmadprioin_logic WHEN (tx3_logical_to_physical_mapping = 2) ELSE + ch4_txpmadprioin_logic WHEN (tx4_logical_to_physical_mapping = 2) ELSE + ch5_txpmadprioin_logic WHEN (tx5_logical_to_physical_mapping = 2) ELSE + ch2_txpmadprioin_logic; + +ch3_txpmadprioin_phy <= ch0_txpmadprioin_logic WHEN (tx0_logical_to_physical_mapping = 3) ELSE + ch1_txpmadprioin_logic WHEN (tx1_logical_to_physical_mapping = 3) ELSE + ch2_txpmadprioin_logic WHEN (tx2_logical_to_physical_mapping = 3) ELSE + ch3_txpmadprioin_logic WHEN (tx3_logical_to_physical_mapping = 3) ELSE + ch4_txpmadprioin_logic WHEN (tx4_logical_to_physical_mapping = 3) ELSE + ch5_txpmadprioin_logic WHEN (tx5_logical_to_physical_mapping = 3) ELSE + ch3_txpmadprioin_logic; + +ch4_txpmadprioin_phy <= ch0_txpmadprioin_logic WHEN (tx0_logical_to_physical_mapping = 4) ELSE + ch1_txpmadprioin_logic WHEN (tx1_logical_to_physical_mapping = 4) ELSE + ch2_txpmadprioin_logic WHEN (tx2_logical_to_physical_mapping = 4) ELSE + ch3_txpmadprioin_logic WHEN (tx3_logical_to_physical_mapping = 4) ELSE + ch4_txpmadprioin_logic WHEN (tx4_logical_to_physical_mapping = 4) ELSE + ch5_txpmadprioin_logic WHEN (tx5_logical_to_physical_mapping = 4) ELSE + ch4_txpmadprioin_logic; + +ch5_txpmadprioin_phy <= ch0_txpmadprioin_logic WHEN (tx0_logical_to_physical_mapping = 5) ELSE + ch1_txpmadprioin_logic WHEN (tx1_logical_to_physical_mapping = 5) ELSE + ch2_txpmadprioin_logic WHEN (tx2_logical_to_physical_mapping = 5) ELSE + ch3_txpmadprioin_logic WHEN (tx3_logical_to_physical_mapping = 5) ELSE + ch4_txpmadprioin_logic WHEN (tx4_logical_to_physical_mapping = 5) ELSE + ch5_txpmadprioin_logic WHEN (tx5_logical_to_physical_mapping = 5) ELSE + ch5_txpmadprioin_logic; + +-- RXPMA +ch0_rxpmadprioin_phy <= ch0_rxpmadprioin_logic WHEN (rx0_logical_to_physical_mapping = 0) ELSE + ch1_rxpmadprioin_logic WHEN (rx1_logical_to_physical_mapping = 0) ELSE + ch2_rxpmadprioin_logic WHEN (rx2_logical_to_physical_mapping = 0) ELSE + ch3_rxpmadprioin_logic WHEN (rx3_logical_to_physical_mapping = 0) ELSE + ch4_rxpmadprioin_logic WHEN (rx4_logical_to_physical_mapping = 0) ELSE + ch5_rxpmadprioin_logic WHEN (rx5_logical_to_physical_mapping = 0) ELSE + ch0_rxpmadprioin_logic; + +ch1_rxpmadprioin_phy <= ch0_rxpmadprioin_logic WHEN (rx0_logical_to_physical_mapping = 1) ELSE + ch1_rxpmadprioin_logic WHEN (rx1_logical_to_physical_mapping = 1) ELSE + ch2_rxpmadprioin_logic WHEN (rx2_logical_to_physical_mapping = 1) ELSE + ch3_rxpmadprioin_logic WHEN (rx3_logical_to_physical_mapping = 1) ELSE + ch4_rxpmadprioin_logic WHEN (rx4_logical_to_physical_mapping = 1) ELSE + ch5_rxpmadprioin_logic WHEN (rx5_logical_to_physical_mapping = 1) ELSE + ch1_rxpmadprioin_logic; + +ch2_rxpmadprioin_phy <= ch0_rxpmadprioin_logic WHEN (rx0_logical_to_physical_mapping = 2) ELSE + ch1_rxpmadprioin_logic WHEN (rx1_logical_to_physical_mapping = 2) ELSE + ch2_rxpmadprioin_logic WHEN (rx2_logical_to_physical_mapping = 2) ELSE + ch3_rxpmadprioin_logic WHEN (rx3_logical_to_physical_mapping = 2) ELSE + ch4_rxpmadprioin_logic WHEN (rx4_logical_to_physical_mapping = 2) ELSE + ch5_rxpmadprioin_logic WHEN (rx5_logical_to_physical_mapping = 2) ELSE + ch2_rxpmadprioin_logic; + +ch3_rxpmadprioin_phy <= ch0_rxpmadprioin_logic WHEN (rx0_logical_to_physical_mapping = 3) ELSE + ch1_rxpmadprioin_logic WHEN (rx1_logical_to_physical_mapping = 3) ELSE + ch2_rxpmadprioin_logic WHEN (rx2_logical_to_physical_mapping = 3) ELSE + ch3_rxpmadprioin_logic WHEN (rx3_logical_to_physical_mapping = 3) ELSE + ch4_rxpmadprioin_logic WHEN (rx4_logical_to_physical_mapping = 3) ELSE + ch5_rxpmadprioin_logic WHEN (rx5_logical_to_physical_mapping = 3) ELSE + ch3_rxpmadprioin_logic; + +ch4_rxpmadprioin_phy <= ch0_rxpmadprioin_logic WHEN (rx0_logical_to_physical_mapping = 4) ELSE + ch1_rxpmadprioin_logic WHEN (rx1_logical_to_physical_mapping = 4) ELSE + ch2_rxpmadprioin_logic WHEN (rx2_logical_to_physical_mapping = 4) ELSE + ch3_rxpmadprioin_logic WHEN (rx3_logical_to_physical_mapping = 4) ELSE + ch4_rxpmadprioin_logic WHEN (rx4_logical_to_physical_mapping = 4) ELSE + ch5_rxpmadprioin_logic WHEN (rx5_logical_to_physical_mapping = 4) ELSE + ch4_rxpmadprioin_logic; + +ch5_rxpmadprioin_phy <= ch0_rxpmadprioin_logic WHEN (rx0_logical_to_physical_mapping = 5) ELSE + ch1_rxpmadprioin_logic WHEN (rx1_logical_to_physical_mapping = 5) ELSE + ch2_rxpmadprioin_logic WHEN (rx2_logical_to_physical_mapping = 5) ELSE + ch3_rxpmadprioin_logic WHEN (rx3_logical_to_physical_mapping = 5) ELSE + ch4_rxpmadprioin_logic WHEN (rx4_logical_to_physical_mapping = 5) ELSE + ch5_rxpmadprioin_logic WHEN (rx5_logical_to_physical_mapping = 5) ELSE + ch5_rxpmadprioin_logic; + +-- PLL +ch0_rxplldprioin_phy <= ch0_rxplldprioin_logic WHEN (pll0_logical_to_physical_mapping = 0) ELSE + ch1_rxplldprioin_logic WHEN (pll1_logical_to_physical_mapping = 0) ELSE + ch2_rxplldprioin_logic WHEN (pll2_logical_to_physical_mapping = 0) ELSE + ch3_rxplldprioin_logic WHEN (pll3_logical_to_physical_mapping = 0) ELSE + ch4_rxtxplldprioin_logic WHEN (pll4_logical_to_physical_mapping = 0) ELSE + ch5_rxtxplldprioin_logic WHEN (pll5_logical_to_physical_mapping = 0) ELSE + ch0_rxplldprioin_logic; + +ch1_rxplldprioin_phy <= ch0_rxplldprioin_logic WHEN (pll0_logical_to_physical_mapping = 1) ELSE + ch1_rxplldprioin_logic WHEN (pll1_logical_to_physical_mapping = 1) ELSE + ch2_rxplldprioin_logic WHEN (pll2_logical_to_physical_mapping = 1) ELSE + ch3_rxplldprioin_logic WHEN (pll3_logical_to_physical_mapping = 1) ELSE + ch4_rxtxplldprioin_logic WHEN (pll4_logical_to_physical_mapping = 1) ELSE + ch5_rxtxplldprioin_logic WHEN (pll5_logical_to_physical_mapping = 1) ELSE + ch1_rxplldprioin_logic; + +ch2_rxplldprioin_phy <= ch0_rxplldprioin_logic WHEN (pll0_logical_to_physical_mapping = 2) ELSE + ch1_rxplldprioin_logic WHEN (pll1_logical_to_physical_mapping = 2) ELSE + ch2_rxplldprioin_logic WHEN (pll2_logical_to_physical_mapping = 2) ELSE + ch3_rxplldprioin_logic WHEN (pll3_logical_to_physical_mapping = 2) ELSE + ch4_rxtxplldprioin_logic WHEN (pll4_logical_to_physical_mapping = 2) ELSE + ch5_rxtxplldprioin_logic WHEN (pll5_logical_to_physical_mapping = 2) ELSE + ch2_rxplldprioin_logic; + +ch3_rxplldprioin_phy <= ch0_rxplldprioin_logic WHEN (pll0_logical_to_physical_mapping = 3) ELSE + ch1_rxplldprioin_logic WHEN (pll1_logical_to_physical_mapping = 3) ELSE + ch2_rxplldprioin_logic WHEN (pll2_logical_to_physical_mapping = 3) ELSE + ch3_rxplldprioin_logic WHEN (pll3_logical_to_physical_mapping = 3) ELSE + ch4_rxtxplldprioin_logic WHEN (pll4_logical_to_physical_mapping = 3) ELSE + ch5_rxtxplldprioin_logic WHEN (pll5_logical_to_physical_mapping = 3) ELSE + ch3_rxplldprioin_logic; + +ch4_rxtxplldprioin_phy <= ch0_rxplldprioin_logic WHEN (pll0_logical_to_physical_mapping = 4) ELSE + ch1_rxplldprioin_logic WHEN (pll1_logical_to_physical_mapping = 4) ELSE + ch2_rxplldprioin_logic WHEN (pll2_logical_to_physical_mapping = 4) ELSE + ch3_rxplldprioin_logic WHEN (pll3_logical_to_physical_mapping = 4) ELSE + ch4_rxtxplldprioin_logic WHEN (pll4_logical_to_physical_mapping = 4) ELSE + ch5_rxtxplldprioin_logic WHEN (pll5_logical_to_physical_mapping = 4) ELSE + ch4_rxtxplldprioin_logic; + +ch5_rxtxplldprioin_phy <= ch0_rxplldprioin_logic WHEN (pll0_logical_to_physical_mapping = 5) ELSE + ch1_rxplldprioin_logic WHEN (pll1_logical_to_physical_mapping = 5) ELSE + ch2_rxplldprioin_logic WHEN (pll2_logical_to_physical_mapping = 5) ELSE + ch3_rxplldprioin_logic WHEN (pll3_logical_to_physical_mapping = 5) ELSE + ch4_rxtxplldprioin_logic WHEN (pll4_logical_to_physical_mapping = 5) ELSE + ch5_rxtxplldprioin_logic WHEN (pll5_logical_to_physical_mapping = 5) ELSE + ch5_rxtxplldprioin_logic; + +-- CMUDivider +ch0_cmudividerdprioin_phy <= ch0_cmudividerdprioin_logic WHEN (tx0_logical_to_physical_mapping = 0) ELSE + ch1_cmudividerdprioin_logic WHEN (tx1_logical_to_physical_mapping = 0) ELSE + ch2_cmudividerdprioin_logic WHEN (tx2_logical_to_physical_mapping = 0) ELSE + ch3_cmudividerdprioin_logic WHEN (tx3_logical_to_physical_mapping = 0) ELSE + ch4_cmudividerdprioin_logic WHEN (tx4_logical_to_physical_mapping = 0) ELSE + ch5_cmudividerdprioin_logic WHEN (tx5_logical_to_physical_mapping = 0) ELSE + ch0_cmudividerdprioin_logic; + +ch1_cmudividerdprioin_phy <= ch0_cmudividerdprioin_logic WHEN (tx0_logical_to_physical_mapping = 1) ELSE + ch1_cmudividerdprioin_logic WHEN (tx1_logical_to_physical_mapping = 1) ELSE + ch2_cmudividerdprioin_logic WHEN (tx2_logical_to_physical_mapping = 1) ELSE + ch3_cmudividerdprioin_logic WHEN (tx3_logical_to_physical_mapping = 1) ELSE + ch4_cmudividerdprioin_logic WHEN (tx4_logical_to_physical_mapping = 1) ELSE + ch5_cmudividerdprioin_logic WHEN (tx5_logical_to_physical_mapping = 1) ELSE + ch1_cmudividerdprioin_logic; + +ch2_cmudividerdprioin_phy <= ch0_cmudividerdprioin_logic WHEN (tx0_logical_to_physical_mapping = 2) ELSE + ch1_cmudividerdprioin_logic WHEN (tx1_logical_to_physical_mapping = 2) ELSE + ch2_cmudividerdprioin_logic WHEN (tx2_logical_to_physical_mapping = 2) ELSE + ch3_cmudividerdprioin_logic WHEN (tx3_logical_to_physical_mapping = 2) ELSE + ch4_cmudividerdprioin_logic WHEN (tx4_logical_to_physical_mapping = 2) ELSE + ch5_cmudividerdprioin_logic WHEN (tx5_logical_to_physical_mapping = 2) ELSE + ch2_cmudividerdprioin_logic; + +ch3_cmudividerdprioin_phy <= ch0_cmudividerdprioin_logic WHEN (tx0_logical_to_physical_mapping = 3) ELSE + ch1_cmudividerdprioin_logic WHEN (tx1_logical_to_physical_mapping = 3) ELSE + ch2_cmudividerdprioin_logic WHEN (tx2_logical_to_physical_mapping = 3) ELSE + ch3_cmudividerdprioin_logic WHEN (tx3_logical_to_physical_mapping = 3) ELSE + ch4_cmudividerdprioin_logic WHEN (tx4_logical_to_physical_mapping = 3) ELSE + ch5_cmudividerdprioin_logic WHEN (tx5_logical_to_physical_mapping = 3) ELSE + ch3_cmudividerdprioin_logic; + +ch4_cmudividerdprioin_phy <= ch0_cmudividerdprioin_logic WHEN (tx0_logical_to_physical_mapping = 4) ELSE + ch1_cmudividerdprioin_logic WHEN (tx1_logical_to_physical_mapping = 4) ELSE + ch2_cmudividerdprioin_logic WHEN (tx2_logical_to_physical_mapping = 4) ELSE + ch3_cmudividerdprioin_logic WHEN (tx3_logical_to_physical_mapping = 4) ELSE + ch4_cmudividerdprioin_logic WHEN (tx4_logical_to_physical_mapping = 4) ELSE + ch5_cmudividerdprioin_logic WHEN (tx5_logical_to_physical_mapping = 4) ELSE + ch4_cmudividerdprioin_logic; + +ch5_cmudividerdprioin_phy <= ch0_cmudividerdprioin_logic WHEN (tx0_logical_to_physical_mapping = 5) ELSE + ch1_cmudividerdprioin_logic WHEN (tx1_logical_to_physical_mapping = 5) ELSE + ch2_cmudividerdprioin_logic WHEN (tx2_logical_to_physical_mapping = 5) ELSE + ch3_cmudividerdprioin_logic WHEN (tx3_logical_to_physical_mapping = 5) ELSE + ch4_cmudividerdprioin_logic WHEN (tx4_logical_to_physical_mapping = 5) ELSE + ch5_cmudividerdprioin_logic WHEN (tx5_logical_to_physical_mapping = 5) ELSE + ch5_cmudividerdprioin_logic; + +-- -------- SW ordering ------------------------------------ +--TXPCS +ch0_in_chnl_ctrl_1 <= ch0_txpcsdprioin_phy (rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0); +ch1_in_chnl_ctrl_1 <= ch1_txpcsdprioin_phy (rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0); +ch2_in_chnl_ctrl_1 <= ch2_txpcsdprioin_phy (rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0); +ch3_in_chnl_ctrl_1 <= ch3_txpcsdprioin_phy (rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0); + +ch0_in_chnl_ctrl_2 <= ch0_txpcsdprioin_phy (rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0); +ch1_in_chnl_ctrl_2 <= ch1_txpcsdprioin_phy (rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0); +ch2_in_chnl_ctrl_2 <= ch2_txpcsdprioin_phy (rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0); +ch3_in_chnl_ctrl_2 <= ch3_txpcsdprioin_phy (rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0); + +ch0_in_chnl_ctrl_3 <= ch0_txpcsdprioin_phy (rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0); +ch1_in_chnl_ctrl_3 <= ch1_txpcsdprioin_phy (rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0); +ch2_in_chnl_ctrl_3 <= ch2_txpcsdprioin_phy (rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0); +ch3_in_chnl_ctrl_3 <= ch3_txpcsdprioin_phy (rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0); + +ch0_in_chnl_ctrl_4 <= ch0_txpcsdprioin_phy (rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0); +ch1_in_chnl_ctrl_4 <= ch1_txpcsdprioin_phy (rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0); +ch2_in_chnl_ctrl_4 <= ch2_txpcsdprioin_phy (rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0); +ch3_in_chnl_ctrl_4 <= ch3_txpcsdprioin_phy (rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0); + +ch0_in_chnl_ctrl_5 <= ch0_rxpcsdprioin_phy (reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_5 <= ch1_rxpcsdprioin_phy (reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_5 <= ch2_rxpcsdprioin_phy (reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_5 <= ch3_rxpcsdprioin_phy (reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_6 <= ch0_rxpcsdprioin_phy (reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_6 <= ch1_rxpcsdprioin_phy (reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_6 <= ch2_rxpcsdprioin_phy (reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_6 <= ch3_rxpcsdprioin_phy (reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_7 <= ch0_rxpcsdprioin_phy (rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_7 <= ch1_rxpcsdprioin_phy (rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_7 <= ch2_rxpcsdprioin_phy (rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_7 <= ch3_rxpcsdprioin_phy (rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_8 <= ch0_rxpcsdprioin_phy (rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_8 <= ch1_rxpcsdprioin_phy (rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_8 <= ch2_rxpcsdprioin_phy (rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_8 <= ch3_rxpcsdprioin_phy (rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_9 <= ch0_rxpcsdprioin_phy (rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_9 <= ch1_rxpcsdprioin_phy (rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_9 <= ch2_rxpcsdprioin_phy (rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_9 <= ch3_rxpcsdprioin_phy (rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_10 <= ch0_rxpcsdprioin_phy (rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_10 <= ch1_rxpcsdprioin_phy (rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_10 <= ch2_rxpcsdprioin_phy (rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_10 <= ch3_rxpcsdprioin_phy (rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_11 <= ch0_rxpcsdprioin_phy (rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_11 <= ch1_rxpcsdprioin_phy (rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_11 <= ch2_rxpcsdprioin_phy (rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_11 <= ch3_rxpcsdprioin_phy (rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_12 <= ch0_rxpcsdprioin_phy (rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_12 <= ch1_rxpcsdprioin_phy (rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_12 <= ch2_rxpcsdprioin_phy (rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_12 <= ch3_rxpcsdprioin_phy (rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_13 <= ch0_rxpcsdprioin_phy (rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_13 <= ch1_rxpcsdprioin_phy (rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_13 <= ch2_rxpcsdprioin_phy (rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_13 <= ch3_rxpcsdprioin_phy (rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_14 <= ch0_rxpcsdprioin_phy (rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_14 <= ch1_rxpcsdprioin_phy (rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_14 <= ch2_rxpcsdprioin_phy (rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_14 <= ch3_rxpcsdprioin_phy (rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_15 <= ch0_rxpcsdprioin_phy (rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_15 <= ch1_rxpcsdprioin_phy (rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_15 <= ch2_rxpcsdprioin_phy (rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_15 <= ch3_rxpcsdprioin_phy (rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_16 <= ch0_rxpcsdprioin_phy (rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX); +ch1_in_chnl_ctrl_16 <= ch1_rxpcsdprioin_phy (rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX); +ch2_in_chnl_ctrl_16 <= ch2_rxpcsdprioin_phy (rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX); +ch3_in_chnl_ctrl_16 <= ch3_rxpcsdprioin_phy (rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX); + +ch0_in_chnl_ctrl_17 <= ch0_rxpcsdprioin_phy (rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_17 <= ch1_rxpcsdprioin_phy (rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_17 <= ch2_rxpcsdprioin_phy (rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_17 <= ch3_rxpcsdprioin_phy (rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_18 <= ch0_rxpcsdprioin_phy (reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_18 <= ch1_rxpcsdprioin_phy (reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_18 <= ch2_rxpcsdprioin_phy (reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_18 <= ch3_rxpcsdprioin_phy (reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_19 <= ch0_rxpcsdprioin_phy (reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_19 <= ch1_rxpcsdprioin_phy (reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_19 <= ch2_rxpcsdprioin_phy (reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_19 <= ch3_rxpcsdprioin_phy (reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_20 <= ch0_rxpcsdprioin_phy (rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_20 <= ch1_rxpcsdprioin_phy (rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_20 <= ch2_rxpcsdprioin_phy (rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_20 <= ch3_rxpcsdprioin_phy (rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_21 <= ch0_rxpcsdprioin_phy (rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_21 <= ch1_rxpcsdprioin_phy (rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_21 <= ch2_rxpcsdprioin_phy (rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_21 <= ch3_rxpcsdprioin_phy (rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_22 <= ch0_rxpcsdprioin_phy (rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_22 <= ch1_rxpcsdprioin_phy (rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_22 <= ch2_rxpcsdprioin_phy (rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_22 <= ch3_rxpcsdprioin_phy (rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_23 <= ch0_rxpcsdprioin_phy (reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_23 <= ch1_rxpcsdprioin_phy (reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_23 <= ch2_rxpcsdprioin_phy (reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_23 <= ch3_rxpcsdprioin_phy (reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_24 <= ch0_rxpcsdprioin_phy (rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_24 <= ch1_rxpcsdprioin_phy (rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_24 <= ch2_rxpcsdprioin_phy (rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_24 <= ch3_rxpcsdprioin_phy (rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_25 <= ch0_rxpcsdprioin_phy (reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_25 <= ch1_rxpcsdprioin_phy (reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_25 <= ch2_rxpcsdprioin_phy (reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_25 <= ch3_rxpcsdprioin_phy (reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_26 <= ch0_rxpcsdprioin_phy (rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_26 <= ch1_rxpcsdprioin_phy (rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_26 <= ch2_rxpcsdprioin_phy (rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_26 <= ch3_rxpcsdprioin_phy (rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0); + +ch0_in_chnl_ctrl_27 <= ch0_rxpcsdprioin_phy (reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0); +ch1_in_chnl_ctrl_27 <= ch1_rxpcsdprioin_phy (reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0); +ch2_in_chnl_ctrl_27 <= ch2_rxpcsdprioin_phy (reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0); +ch3_in_chnl_ctrl_27 <= ch3_rxpcsdprioin_phy (reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0); + +--TXPMA +ch0_in_chnl_ctrl_28 <= ch0_txpmadprioin_phy (rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0); +ch1_in_chnl_ctrl_28 <= ch1_txpmadprioin_phy (rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0); +ch2_in_chnl_ctrl_28 <= ch2_txpmadprioin_phy (rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0); +ch3_in_chnl_ctrl_28 <= ch3_txpmadprioin_phy (rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0); +ch4_in_chnl_ctrl_28 <= ch4_txpmadprioin_phy (rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0); +ch5_in_chnl_ctrl_28 <= ch5_txpmadprioin_phy (rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_29 <= ch0_txpmadprioin_phy (rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0); +ch1_in_chnl_ctrl_29 <= ch1_txpmadprioin_phy (rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0); +ch2_in_chnl_ctrl_29 <= ch2_txpmadprioin_phy (rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0); +ch3_in_chnl_ctrl_29 <= ch3_txpmadprioin_phy (rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0); +ch4_in_chnl_ctrl_29 <= ch4_txpmadprioin_phy (rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0); +ch5_in_chnl_ctrl_29 <= ch5_txpmadprioin_phy (rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_30 <= ch0_txpmadprioin_phy (reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0); +ch1_in_chnl_ctrl_30 <= ch1_txpmadprioin_phy (reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0); +ch2_in_chnl_ctrl_30 <= ch2_txpmadprioin_phy (reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0); +ch3_in_chnl_ctrl_30 <= ch3_txpmadprioin_phy (reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0); +ch4_in_chnl_ctrl_30 <= ch4_txpmadprioin_phy (reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0); +ch5_in_chnl_ctrl_30 <= ch5_txpmadprioin_phy (reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_31 <= ch0_txpmadprioin_phy (rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0); +ch1_in_chnl_ctrl_31 <= ch1_txpmadprioin_phy (rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0); +ch2_in_chnl_ctrl_31 <= ch2_txpmadprioin_phy (rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0); +ch3_in_chnl_ctrl_31 <= ch3_txpmadprioin_phy (rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0); +ch4_in_chnl_ctrl_31 <= ch4_txpmadprioin_phy (rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0); +ch5_in_chnl_ctrl_31 <= ch5_txpmadprioin_phy (rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_32 <= ch0_txpmadprioin_phy (r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0); +ch1_in_chnl_ctrl_32 <= ch1_txpmadprioin_phy (r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0); +ch2_in_chnl_ctrl_32 <= ch2_txpmadprioin_phy (r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0); +ch3_in_chnl_ctrl_32 <= ch3_txpmadprioin_phy (r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0); +ch4_in_chnl_ctrl_32 <= ch4_txpmadprioin_phy (r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0); +ch5_in_chnl_ctrl_32 <= ch5_txpmadprioin_phy (r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0); + +-- performed in manual section between table33 splits between tx_pma and clock divider +--ch0_in_chnl_ctrl_33 <= ch0_txpmadprioin_phy (rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +--ch1_in_chnl_ctrl_33 <= ch1_txpmadprioin_phy (rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +--ch2_in_chnl_ctrl_33 <= ch2_txpmadprioin_phy (rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +--ch3_in_chnl_ctrl_33 <= ch3_txpmadprioin_phy (rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +--ch4_in_chnl_ctrl_33 <= ch4_txpmadprioin_phy (rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +--ch5_in_chnl_ctrl_33 <= ch5_txpmadprioin_phy (rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_34 <= ch0_rxpmadprioin_phy (ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0); +ch1_in_chnl_ctrl_34 <= ch1_rxpmadprioin_phy (ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0); +ch2_in_chnl_ctrl_34 <= ch2_rxpmadprioin_phy (ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0); +ch3_in_chnl_ctrl_34 <= ch3_rxpmadprioin_phy (ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0); +ch4_in_chnl_ctrl_34 <= ch3_rxpmadprioin_phy (ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0); +ch5_in_chnl_ctrl_34 <= ch3_rxpmadprioin_phy (ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_35 <= ch0_txpmadprioin_phy (rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0); +ch1_in_chnl_ctrl_35 <= ch1_txpmadprioin_phy (rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0); +ch2_in_chnl_ctrl_35 <= ch2_txpmadprioin_phy (rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0); +ch3_in_chnl_ctrl_35 <= ch3_txpmadprioin_phy (rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0); +ch4_in_chnl_ctrl_35 <= ch4_txpmadprioin_phy (rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0); +ch5_in_chnl_ctrl_35 <= ch5_txpmadprioin_phy (rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_36 <= ch0_rxpmadprioin_phy (rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0); +ch1_in_chnl_ctrl_36 <= ch1_rxpmadprioin_phy (rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0); +ch2_in_chnl_ctrl_36 <= ch2_rxpmadprioin_phy (rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0); +ch3_in_chnl_ctrl_36 <= ch3_rxpmadprioin_phy (rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0); +ch4_in_chnl_ctrl_36 <= ch4_rxpmadprioin_phy (rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0); +ch5_in_chnl_ctrl_36 <= ch5_rxpmadprioin_phy (rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0); + +ch0_in_chnl_ctrl_37 <= ch0_rxpmadprioin_phy (rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0); +ch1_in_chnl_ctrl_37 <= ch1_rxpmadprioin_phy (rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0); +ch2_in_chnl_ctrl_37 <= ch2_rxpmadprioin_phy (rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0); +ch3_in_chnl_ctrl_37 <= ch3_rxpmadprioin_phy (rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0); +ch4_in_chnl_ctrl_37 <= ch4_rxpmadprioin_phy (rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0); +ch5_in_chnl_ctrl_37 <= ch5_rxpmadprioin_phy (rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0); + +ch0_in_chnl_ctrl_38 <= ch0_rxpmadprioin_phy (rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0); +ch1_in_chnl_ctrl_38 <= ch1_rxpmadprioin_phy (rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0); +ch2_in_chnl_ctrl_38 <= ch2_rxpmadprioin_phy (rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0); +ch3_in_chnl_ctrl_38 <= ch3_rxpmadprioin_phy (rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0); +ch4_in_chnl_ctrl_38 <= ch4_rxpmadprioin_phy (rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0); +ch5_in_chnl_ctrl_38 <= ch5_rxpmadprioin_phy (rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0); + +ch0_in_chnl_ctrl_39 <= ch0_rxpmadprioin_phy (ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0); +ch1_in_chnl_ctrl_39 <= ch1_rxpmadprioin_phy (ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0); +ch2_in_chnl_ctrl_39 <= ch2_rxpmadprioin_phy (ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0); +ch3_in_chnl_ctrl_39 <= ch3_rxpmadprioin_phy (ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0); +ch4_in_chnl_ctrl_39 <= ch4_rxpmadprioin_phy (ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0); +ch5_in_chnl_ctrl_39 <= ch5_rxpmadprioin_phy (ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0); + +-- some bit like bit[15] is from tx_pma - moved to Manual section for CYCLONEIV +ch0_in_chnl_ctrl_40 <= ch0_rxpmadprioin_phy (ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0); +ch1_in_chnl_ctrl_40 <= ch1_rxpmadprioin_phy (ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0); +ch2_in_chnl_ctrl_40 <= ch2_rxpmadprioin_phy (ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0); +ch3_in_chnl_ctrl_40 <= ch3_rxpmadprioin_phy (ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0); +ch4_in_chnl_ctrl_40 <= ch4_rxpmadprioin_phy (ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0); +ch5_in_chnl_ctrl_40 <= ch5_rxpmadprioin_phy (ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0); + +ch0_in_chnl_ctrl_41 <= ch0_rxpmadprioin_phy (reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0); +ch1_in_chnl_ctrl_41 <= ch1_rxpmadprioin_phy (reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0); +ch2_in_chnl_ctrl_41 <= ch2_rxpmadprioin_phy (reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0); +ch3_in_chnl_ctrl_41 <= ch3_rxpmadprioin_phy (reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0); +ch4_in_chnl_ctrl_41 <= ch4_rxpmadprioin_phy (reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0); +ch5_in_chnl_ctrl_41 <= ch5_rxpmadprioin_phy (reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0); + +ch0_in_chnl_ctrl_42 <= ch0_rxpmadprioin_phy (reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0); +ch1_in_chnl_ctrl_42 <= ch1_rxpmadprioin_phy (reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0); +ch2_in_chnl_ctrl_42 <= ch2_rxpmadprioin_phy (reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0); +ch3_in_chnl_ctrl_42 <= ch3_rxpmadprioin_phy (reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0); +ch4_in_chnl_ctrl_42 <= ch4_rxpmadprioin_phy (reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0); +ch5_in_chnl_ctrl_42 <= ch5_rxpmadprioin_phy (reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0); + +-- reserved +ch0_in_chnl_ctrl_43 <= ch0_rxpmadprioin_phy (reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0); +ch1_in_chnl_ctrl_43 <= ch1_rxpmadprioin_phy (reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0); +ch2_in_chnl_ctrl_43 <= ch2_rxpmadprioin_phy (reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0); +ch3_in_chnl_ctrl_43 <= ch3_rxpmadprioin_phy (reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0); +ch4_in_chnl_ctrl_43 <= ch4_rxpmadprioin_phy (reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0); +ch5_in_chnl_ctrl_43 <= ch5_rxpmadprioin_phy (reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0); + +ch0_in_chnl_ctrl_44 <= ch0_rxpmadprioin_phy (rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0); +ch1_in_chnl_ctrl_44 <= ch1_rxpmadprioin_phy (rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0); +ch2_in_chnl_ctrl_44 <= ch2_rxpmadprioin_phy (rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0); +ch3_in_chnl_ctrl_44 <= ch3_rxpmadprioin_phy (rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0); +ch4_in_chnl_ctrl_44 <= ch4_rxpmadprioin_phy (rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0); +ch5_in_chnl_ctrl_44 <= ch5_rxpmadprioin_phy (rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0); + +ch0_in_chnl_ctrl_45 <= ch0_rxpmadprioin_phy (reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0); +ch1_in_chnl_ctrl_45 <= ch1_rxpmadprioin_phy (reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0); +ch2_in_chnl_ctrl_45 <= ch2_rxpmadprioin_phy (reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0); +ch3_in_chnl_ctrl_45 <= ch3_rxpmadprioin_phy (reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0); +ch4_in_chnl_ctrl_45 <= ch4_rxpmadprioin_phy (reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0); +ch5_in_chnl_ctrl_45 <= ch5_rxpmadprioin_phy (reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0); + +ch0_in_chnl_ctrl_46 <= ch0_rxpmadprioin_phy (r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0); +ch1_in_chnl_ctrl_46 <= ch1_rxpmadprioin_phy (r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0); +ch2_in_chnl_ctrl_46 <= ch2_rxpmadprioin_phy (r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0); +ch3_in_chnl_ctrl_46 <= ch3_rxpmadprioin_phy (r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0); +ch4_in_chnl_ctrl_46 <= ch4_rxpmadprioin_phy (r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0); +ch5_in_chnl_ctrl_46 <= ch5_rxpmadprioin_phy (r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0); + +ch0_in_chnl_ctrl_47 <= ch0_rxpmadprioin_phy (reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0); +ch1_in_chnl_ctrl_47 <= ch1_rxpmadprioin_phy (reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0); +ch2_in_chnl_ctrl_47 <= ch2_rxpmadprioin_phy (reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0); +ch3_in_chnl_ctrl_47 <= ch3_rxpmadprioin_phy (reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0); +ch4_in_chnl_ctrl_47 <= ch4_rxpmadprioin_phy (reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0); +ch5_in_chnl_ctrl_47 <= ch5_rxpmadprioin_phy (reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0); + +-- -------- HW ordering ------------------------------------ +--TXPCS +ch0_csr_chnl_in(15 DOWNTO 0) <= ch0_in_chnl_ctrl_1; +ch1_csr_chnl_in(15 DOWNTO 0) <= ch1_in_chnl_ctrl_1; +ch2_csr_chnl_in(15 DOWNTO 0) <= ch2_in_chnl_ctrl_1; +ch3_csr_chnl_in(15 DOWNTO 0) <= ch3_in_chnl_ctrl_1; + +ch0_csr_chnl_in(31 DOWNTO 16) <= ch0_in_chnl_ctrl_2; +ch1_csr_chnl_in(31 DOWNTO 16) <= ch1_in_chnl_ctrl_2; +ch2_csr_chnl_in(31 DOWNTO 16) <= ch2_in_chnl_ctrl_2; +ch3_csr_chnl_in(31 DOWNTO 16) <= ch3_in_chnl_ctrl_2; + +ch0_csr_chnl_in(47 DOWNTO 32) <= ch0_in_chnl_ctrl_3; +ch1_csr_chnl_in(47 DOWNTO 32) <= ch1_in_chnl_ctrl_3; +ch2_csr_chnl_in(47 DOWNTO 32) <= ch2_in_chnl_ctrl_3; +ch3_csr_chnl_in(47 DOWNTO 32) <= ch3_in_chnl_ctrl_3; + +ch0_csr_chnl_in(63 DOWNTO 48) <= ch0_in_chnl_ctrl_4; +ch1_csr_chnl_in(63 DOWNTO 48) <= ch1_in_chnl_ctrl_4; +ch2_csr_chnl_in(63 DOWNTO 48) <= ch2_in_chnl_ctrl_4; +ch3_csr_chnl_in(63 DOWNTO 48) <= ch3_in_chnl_ctrl_4; + +ch0_csr_chnl_in(79 DOWNTO 64) <= ch0_in_chnl_ctrl_5; +ch1_csr_chnl_in(79 DOWNTO 64) <= ch1_in_chnl_ctrl_5; +ch2_csr_chnl_in(79 DOWNTO 64) <= ch2_in_chnl_ctrl_5; +ch3_csr_chnl_in(79 DOWNTO 64) <= ch3_in_chnl_ctrl_5; + +ch0_csr_chnl_in(95 DOWNTO 80) <= ch0_in_chnl_ctrl_6; +ch1_csr_chnl_in(95 DOWNTO 80) <= ch1_in_chnl_ctrl_6; +ch2_csr_chnl_in(95 DOWNTO 80) <= ch2_in_chnl_ctrl_6; +ch3_csr_chnl_in(95 DOWNTO 80) <= ch3_in_chnl_ctrl_6; + +ch0_csr_chnl_in(111 DOWNTO 96) <= ch0_in_chnl_ctrl_7; +ch1_csr_chnl_in(111 DOWNTO 96) <= ch1_in_chnl_ctrl_7; +ch2_csr_chnl_in(111 DOWNTO 96) <= ch2_in_chnl_ctrl_7; +ch3_csr_chnl_in(111 DOWNTO 96) <= ch3_in_chnl_ctrl_7; + +ch0_csr_chnl_in(127 DOWNTO 112) <= ch0_in_chnl_ctrl_8; +ch1_csr_chnl_in(127 DOWNTO 112) <= ch1_in_chnl_ctrl_8; +ch2_csr_chnl_in(127 DOWNTO 112) <= ch2_in_chnl_ctrl_8; +ch3_csr_chnl_in(127 DOWNTO 112) <= ch3_in_chnl_ctrl_8; + +ch0_csr_chnl_in(143 DOWNTO 128) <= ch0_in_chnl_ctrl_9; +ch1_csr_chnl_in(143 DOWNTO 128) <= ch1_in_chnl_ctrl_9; +ch2_csr_chnl_in(143 DOWNTO 128) <= ch2_in_chnl_ctrl_9; +ch3_csr_chnl_in(143 DOWNTO 128) <= ch3_in_chnl_ctrl_9; + +ch0_csr_chnl_in(159 DOWNTO 144) <= ch0_in_chnl_ctrl_10; +ch1_csr_chnl_in(159 DOWNTO 144) <= ch1_in_chnl_ctrl_10; +ch2_csr_chnl_in(159 DOWNTO 144) <= ch2_in_chnl_ctrl_10; +ch3_csr_chnl_in(159 DOWNTO 144) <= ch3_in_chnl_ctrl_10; + +ch0_csr_chnl_in(175 DOWNTO 160) <= ch0_in_chnl_ctrl_11; +ch1_csr_chnl_in(175 DOWNTO 160) <= ch1_in_chnl_ctrl_11; +ch2_csr_chnl_in(175 DOWNTO 160) <= ch2_in_chnl_ctrl_11; +ch3_csr_chnl_in(175 DOWNTO 160) <= ch3_in_chnl_ctrl_11; + +ch0_csr_chnl_in(191 DOWNTO 176) <= ch0_in_chnl_ctrl_12; +ch1_csr_chnl_in(191 DOWNTO 176) <= ch1_in_chnl_ctrl_12; +ch2_csr_chnl_in(191 DOWNTO 176) <= ch2_in_chnl_ctrl_12; +ch3_csr_chnl_in(191 DOWNTO 176) <= ch3_in_chnl_ctrl_12; + +ch0_csr_chnl_in(207 DOWNTO 192) <= ch0_in_chnl_ctrl_13; +ch1_csr_chnl_in(207 DOWNTO 192) <= ch1_in_chnl_ctrl_13; +ch2_csr_chnl_in(207 DOWNTO 192) <= ch2_in_chnl_ctrl_13; +ch3_csr_chnl_in(207 DOWNTO 192) <= ch3_in_chnl_ctrl_13; + +ch0_csr_chnl_in(223 DOWNTO 208) <= ch0_in_chnl_ctrl_14; +ch1_csr_chnl_in(223 DOWNTO 208) <= ch1_in_chnl_ctrl_14; +ch2_csr_chnl_in(223 DOWNTO 208) <= ch2_in_chnl_ctrl_14; +ch3_csr_chnl_in(223 DOWNTO 208) <= ch3_in_chnl_ctrl_14; + +ch0_csr_chnl_in(239 DOWNTO 224) <= ch0_in_chnl_ctrl_15; +ch1_csr_chnl_in(239 DOWNTO 224) <= ch1_in_chnl_ctrl_15; +ch2_csr_chnl_in(239 DOWNTO 224) <= ch2_in_chnl_ctrl_15; +ch3_csr_chnl_in(239 DOWNTO 224) <= ch3_in_chnl_ctrl_15; + +ch0_csr_chnl_in(255 DOWNTO 240) <= ch0_in_chnl_ctrl_16; +ch1_csr_chnl_in(255 DOWNTO 240) <= ch1_in_chnl_ctrl_16; +ch2_csr_chnl_in(255 DOWNTO 240) <= ch2_in_chnl_ctrl_16; +ch3_csr_chnl_in(255 DOWNTO 240) <= ch3_in_chnl_ctrl_16; + +ch0_csr_chnl_in(271 DOWNTO 256) <= ch0_in_chnl_ctrl_17; +ch1_csr_chnl_in(271 DOWNTO 256) <= ch1_in_chnl_ctrl_17; +ch2_csr_chnl_in(271 DOWNTO 256) <= ch2_in_chnl_ctrl_17; +ch3_csr_chnl_in(271 DOWNTO 256) <= ch3_in_chnl_ctrl_17; + +ch0_csr_chnl_in(287 DOWNTO 272) <= ch0_in_chnl_ctrl_18; +ch1_csr_chnl_in(287 DOWNTO 272) <= ch1_in_chnl_ctrl_18; +ch2_csr_chnl_in(287 DOWNTO 272) <= ch2_in_chnl_ctrl_18; +ch3_csr_chnl_in(287 DOWNTO 272) <= ch3_in_chnl_ctrl_18; + +ch0_csr_chnl_in(303 DOWNTO 288) <= ch0_in_chnl_ctrl_19; +ch1_csr_chnl_in(303 DOWNTO 288) <= ch1_in_chnl_ctrl_19; +ch2_csr_chnl_in(303 DOWNTO 288) <= ch2_in_chnl_ctrl_19; +ch3_csr_chnl_in(303 DOWNTO 288) <= ch3_in_chnl_ctrl_19; + +ch0_csr_chnl_in(319 DOWNTO 304) <= ch0_in_chnl_ctrl_20; +ch1_csr_chnl_in(319 DOWNTO 304) <= ch1_in_chnl_ctrl_20; +ch2_csr_chnl_in(319 DOWNTO 304) <= ch2_in_chnl_ctrl_20; +ch3_csr_chnl_in(319 DOWNTO 304) <= ch3_in_chnl_ctrl_20; + +ch0_csr_chnl_in(335 DOWNTO 320) <= ch0_in_chnl_ctrl_21; +ch1_csr_chnl_in(335 DOWNTO 320) <= ch1_in_chnl_ctrl_21; +ch2_csr_chnl_in(335 DOWNTO 320) <= ch2_in_chnl_ctrl_21; +ch3_csr_chnl_in(335 DOWNTO 320) <= ch3_in_chnl_ctrl_21; + +ch0_csr_chnl_in(351 DOWNTO 336) <= ch0_in_chnl_ctrl_22; +ch1_csr_chnl_in(351 DOWNTO 336) <= ch1_in_chnl_ctrl_22; +ch2_csr_chnl_in(351 DOWNTO 336) <= ch2_in_chnl_ctrl_22; +ch3_csr_chnl_in(351 DOWNTO 336) <= ch3_in_chnl_ctrl_22; + +ch0_csr_chnl_in(367 DOWNTO 352) <= ch0_in_chnl_ctrl_23; +ch1_csr_chnl_in(367 DOWNTO 352) <= ch1_in_chnl_ctrl_23; +ch2_csr_chnl_in(367 DOWNTO 352) <= ch2_in_chnl_ctrl_23; +ch3_csr_chnl_in(367 DOWNTO 352) <= ch3_in_chnl_ctrl_23; + +ch0_csr_chnl_in(383 DOWNTO 368) <= ch0_in_chnl_ctrl_24; +ch1_csr_chnl_in(383 DOWNTO 368) <= ch1_in_chnl_ctrl_24; +ch2_csr_chnl_in(383 DOWNTO 368) <= ch2_in_chnl_ctrl_24; +ch3_csr_chnl_in(383 DOWNTO 368) <= ch3_in_chnl_ctrl_24; + +ch0_csr_chnl_in(399 DOWNTO 384) <= ch0_in_chnl_ctrl_25; +ch1_csr_chnl_in(399 DOWNTO 384) <= ch1_in_chnl_ctrl_25; +ch2_csr_chnl_in(399 DOWNTO 384) <= ch2_in_chnl_ctrl_25; +ch3_csr_chnl_in(399 DOWNTO 384) <= ch3_in_chnl_ctrl_25; + +ch0_csr_chnl_in(415 DOWNTO 400) <= ch0_in_chnl_ctrl_26; +ch1_csr_chnl_in(415 DOWNTO 400) <= ch1_in_chnl_ctrl_26; +ch2_csr_chnl_in(415 DOWNTO 400) <= ch2_in_chnl_ctrl_26; +ch3_csr_chnl_in(415 DOWNTO 400) <= ch3_in_chnl_ctrl_26; + +ch0_csr_chnl_in(431 DOWNTO 416) <= ch0_in_chnl_ctrl_27; +ch1_csr_chnl_in(431 DOWNTO 416) <= ch1_in_chnl_ctrl_27; +ch2_csr_chnl_in(431 DOWNTO 416) <= ch2_in_chnl_ctrl_27; +ch3_csr_chnl_in(431 DOWNTO 416) <= ch3_in_chnl_ctrl_27; + +--TXPMA +ch0_csr_chnl_in(447 DOWNTO 432) <= ch0_in_chnl_ctrl_28; +ch1_csr_chnl_in(447 DOWNTO 432) <= ch1_in_chnl_ctrl_28; +ch2_csr_chnl_in(447 DOWNTO 432) <= ch2_in_chnl_ctrl_28; +ch3_csr_chnl_in(447 DOWNTO 432) <= ch3_in_chnl_ctrl_28; +--ch4_csr_chnl_in(447 DOWNTO 432) <= ch4_in_chnl_ctrl_28; HW is cmu0_csr_in +--ch5_csr_chnl_in(447 DOWNTO 432) <= ch5_in_chnl_ctrl_28; CMU index 0 - 20 + +ch0_csr_chnl_in(463 DOWNTO 448) <= ch0_in_chnl_ctrl_29; +ch1_csr_chnl_in(463 DOWNTO 448) <= ch1_in_chnl_ctrl_29; +ch2_csr_chnl_in(463 DOWNTO 448) <= ch2_in_chnl_ctrl_29; +ch3_csr_chnl_in(463 DOWNTO 448) <= ch3_in_chnl_ctrl_29; +--ch4_csr_chnl_in(463 DOWNTO 448) <= ch4_in_chnl_ctrl_29; +--ch5_csr_chnl_in(463 DOWNTO 448) <= ch5_in_chnl_ctrl_29; + +ch0_csr_chnl_in(479 DOWNTO 464) <= ch0_in_chnl_ctrl_30; +ch1_csr_chnl_in(479 DOWNTO 464) <= ch1_in_chnl_ctrl_30; +ch2_csr_chnl_in(479 DOWNTO 464) <= ch2_in_chnl_ctrl_30; +ch3_csr_chnl_in(479 DOWNTO 464) <= ch3_in_chnl_ctrl_30; +--ch4_csr_chnl_in(479 DOWNTO 464) <= ch4_in_chnl_ctrl_30; +--ch5_csr_chnl_in(479 DOWNTO 464) <= ch5_in_chnl_ctrl_30; + +ch0_csr_chnl_in(495 DOWNTO 480) <= ch0_in_chnl_ctrl_31; +ch1_csr_chnl_in(495 DOWNTO 480) <= ch1_in_chnl_ctrl_31; +ch2_csr_chnl_in(495 DOWNTO 480) <= ch2_in_chnl_ctrl_31; +ch3_csr_chnl_in(495 DOWNTO 480) <= ch3_in_chnl_ctrl_31; +--ch4_csr_chnl_in(495 DOWNTO 480) <= ch4_in_chnl_ctrl_31; +--ch5_csr_chnl_in(495 DOWNTO 480) <= ch5_in_chnl_ctrl_31; + +ch0_csr_chnl_in(511 DOWNTO 496) <= ch0_in_chnl_ctrl_32; +ch1_csr_chnl_in(511 DOWNTO 496) <= ch1_in_chnl_ctrl_32; +ch2_csr_chnl_in(511 DOWNTO 496) <= ch2_in_chnl_ctrl_32; +ch3_csr_chnl_in(511 DOWNTO 496) <= ch3_in_chnl_ctrl_32; +--ch4_csr_chnl_in(511 DOWNTO 496) <= ch4_in_chnl_ctrl_32; +--ch5_csr_chnl_in(511 DOWNTO 496) <= ch5_in_chnl_ctrl_32; + +ch0_csr_chnl_in(527 DOWNTO 512) <= ch0_in_chnl_ctrl_33; +ch1_csr_chnl_in(527 DOWNTO 512) <= ch1_in_chnl_ctrl_33; +ch2_csr_chnl_in(527 DOWNTO 512) <= ch2_in_chnl_ctrl_33; +ch3_csr_chnl_in(527 DOWNTO 512) <= ch3_in_chnl_ctrl_33; +--ch4_csr_chnl_in(527 DOWNTO 512) <= ch4_in_chnl_ctrl_33; +--ch5_csr_chnl_in(527 DOWNTO 512) <= ch5_in_chnl_ctrl_33; + +ch0_csr_chnl_in(543 DOWNTO 528) <= ch0_in_chnl_ctrl_34; +ch1_csr_chnl_in(543 DOWNTO 528) <= ch1_in_chnl_ctrl_34; +ch2_csr_chnl_in(543 DOWNTO 528) <= ch2_in_chnl_ctrl_34; +ch3_csr_chnl_in(543 DOWNTO 528) <= ch3_in_chnl_ctrl_34; +--ch4_csr_chnl_in(543 DOWNTO 528) <= ch4_in_chnl_ctrl_34; +--ch5_csr_chnl_in(543 DOWNTO 528) <= ch5_in_chnl_ctrl_34; + +ch0_csr_chnl_in(559 DOWNTO 544) <= ch0_in_chnl_ctrl_35; +ch1_csr_chnl_in(559 DOWNTO 544) <= ch1_in_chnl_ctrl_35; +ch2_csr_chnl_in(559 DOWNTO 544) <= ch2_in_chnl_ctrl_35; +ch3_csr_chnl_in(559 DOWNTO 544) <= ch3_in_chnl_ctrl_35; +--ch4_csr_chnl_in(559 DOWNTO 544) <= ch4_in_chnl_ctrl_35; +--ch5_csr_chnl_in(559 DOWNTO 544) <= ch5_in_chnl_ctrl_35; + +ch0_csr_chnl_in(575 DOWNTO 560) <= ch0_in_chnl_ctrl_36; +ch1_csr_chnl_in(575 DOWNTO 560) <= ch1_in_chnl_ctrl_36; +ch2_csr_chnl_in(575 DOWNTO 560) <= ch2_in_chnl_ctrl_36; +ch3_csr_chnl_in(575 DOWNTO 560) <= ch3_in_chnl_ctrl_36; +--ch4_csr_chnl_in(575 DOWNTO 560) <= ch4_in_chnl_ctrl_36; +--ch5_csr_chnl_in(575 DOWNTO 560) <= ch5_in_chnl_ctrl_36; + +ch0_csr_chnl_in(591 DOWNTO 576) <= ch0_in_chnl_ctrl_37; +ch1_csr_chnl_in(591 DOWNTO 576) <= ch1_in_chnl_ctrl_37; +ch2_csr_chnl_in(591 DOWNTO 576) <= ch2_in_chnl_ctrl_37; +ch3_csr_chnl_in(591 DOWNTO 576) <= ch3_in_chnl_ctrl_37; +--ch4_csr_chnl_in(591 DOWNTO 576) <= ch4_in_chnl_ctrl_37; +--ch5_csr_chnl_in(591 DOWNTO 576) <= ch5_in_chnl_ctrl_37; + +ch0_csr_chnl_in(607 DOWNTO 592) <= ch0_in_chnl_ctrl_38; +ch1_csr_chnl_in(607 DOWNTO 592) <= ch1_in_chnl_ctrl_38; +ch2_csr_chnl_in(607 DOWNTO 592) <= ch2_in_chnl_ctrl_38; +ch3_csr_chnl_in(607 DOWNTO 592) <= ch3_in_chnl_ctrl_38; +--ch4_csr_chnl_in(607 DOWNTO 592) <= ch4_in_chnl_ctrl_38; +--ch5_csr_chnl_in(607 DOWNTO 592) <= ch5_in_chnl_ctrl_38; + +ch0_csr_chnl_in(623 DOWNTO 608) <= ch0_in_chnl_ctrl_39; +ch1_csr_chnl_in(623 DOWNTO 608) <= ch1_in_chnl_ctrl_39; +ch2_csr_chnl_in(623 DOWNTO 608) <= ch2_in_chnl_ctrl_39; +ch3_csr_chnl_in(623 DOWNTO 608) <= ch3_in_chnl_ctrl_39; +--ch4_csr_chnl_in(623 DOWNTO 608) <= ch4_in_chnl_ctrl_39; +--ch5_csr_chnl_in(623 DOWNTO 608) <= ch5_in_chnl_ctrl_39; + +ch0_csr_chnl_in(639 DOWNTO 624) <= ch0_in_chnl_ctrl_40; +ch1_csr_chnl_in(639 DOWNTO 624) <= ch1_in_chnl_ctrl_40; +ch2_csr_chnl_in(639 DOWNTO 624) <= ch2_in_chnl_ctrl_40; +ch3_csr_chnl_in(639 DOWNTO 624) <= ch3_in_chnl_ctrl_40; +--ch4_csr_chnl_in(639 DOWNTO 624) <= ch4_in_chnl_ctrl_40; +--ch5_csr_chnl_in(639 DOWNTO 624) <= ch5_in_chnl_ctrl_40; + +ch0_csr_chnl_in(655 DOWNTO 640) <= ch0_in_chnl_ctrl_41; +ch1_csr_chnl_in(655 DOWNTO 640) <= ch1_in_chnl_ctrl_41; +ch2_csr_chnl_in(655 DOWNTO 640) <= ch2_in_chnl_ctrl_41; +ch3_csr_chnl_in(655 DOWNTO 640) <= ch3_in_chnl_ctrl_41; +--ch4_csr_chnl_in(655 DOWNTO 640) <= ch4_in_chnl_ctrl_41; +--ch5_csr_chnl_in(655 DOWNTO 640) <= ch5_in_chnl_ctrl_41; + +ch0_csr_chnl_in(671 DOWNTO 656) <= ch0_in_chnl_ctrl_42; +ch1_csr_chnl_in(671 DOWNTO 656) <= ch1_in_chnl_ctrl_42; +ch2_csr_chnl_in(671 DOWNTO 656) <= ch2_in_chnl_ctrl_42; +ch3_csr_chnl_in(671 DOWNTO 656) <= ch3_in_chnl_ctrl_42; +--ch4_csr_chnl_in(671 DOWNTO 656) <= ch4_in_chnl_ctrl_42; +--ch5_csr_chnl_in(671 DOWNTO 656) <= ch5_in_chnl_ctrl_42; + +ch0_csr_chnl_in_reserved(15 DOWNTO 0) <= ch0_in_chnl_ctrl_43; +ch1_csr_chnl_in_reserved(15 DOWNTO 0) <= ch1_in_chnl_ctrl_43; +ch2_csr_chnl_in_reserved(15 DOWNTO 0) <= ch2_in_chnl_ctrl_43; +ch3_csr_chnl_in_reserved(15 DOWNTO 0) <= ch3_in_chnl_ctrl_43; +--ch4_csr_chnl_in(15 DOWNTO 0) <= ch4_in_chnl_ctrl_43; +--ch5_csr_chnl_in(15 DOWNTO 0) <= ch5_in_chnl_ctrl_43; + +ch0_csr_chnl_in(687 DOWNTO 672) <= ch0_in_chnl_ctrl_44; +ch1_csr_chnl_in(687 DOWNTO 672) <= ch1_in_chnl_ctrl_44; +ch2_csr_chnl_in(687 DOWNTO 672) <= ch2_in_chnl_ctrl_44; +ch3_csr_chnl_in(687 DOWNTO 672) <= ch3_in_chnl_ctrl_44; +--ch4_csr_chnl_in(687 DOWNTO 672) <= ch4_in_chnl_ctrl_44; +--ch5_csr_chnl_in(687 DOWNTO 672) <= ch5_in_chnl_ctrl_44; + +ch0_csr_chnl_in(703 DOWNTO 688) <= ch0_in_chnl_ctrl_45; +ch1_csr_chnl_in(703 DOWNTO 688) <= ch1_in_chnl_ctrl_45; +ch2_csr_chnl_in(703 DOWNTO 688) <= ch2_in_chnl_ctrl_45; +ch3_csr_chnl_in(703 DOWNTO 688) <= ch3_in_chnl_ctrl_45; +--ch4_csr_chnl_in(703 DOWNTO 688) <= ch4_in_chnl_ctrl_45; +--ch5_csr_chnl_in(703 DOWNTO 688) <= ch5_in_chnl_ctrl_45; + +ch0_csr_chnl_in(719 DOWNTO 704) <= ch0_in_chnl_ctrl_46; +ch1_csr_chnl_in(719 DOWNTO 704) <= ch1_in_chnl_ctrl_46; +ch2_csr_chnl_in(719 DOWNTO 704) <= ch2_in_chnl_ctrl_46; +ch3_csr_chnl_in(719 DOWNTO 704) <= ch3_in_chnl_ctrl_46; +--ch4_csr_chnl_in(719 DOWNTO 704) <= ch4_in_chnl_ctrl_46; +--ch5_csr_chnl_in(719 DOWNTO 704) <= ch5_in_chnl_ctrl_46; + +ch0_csr_chnl_in(735 DOWNTO 720) <= ch0_in_chnl_ctrl_47; +ch1_csr_chnl_in(735 DOWNTO 720) <= ch1_in_chnl_ctrl_47; +ch2_csr_chnl_in(735 DOWNTO 720) <= ch2_in_chnl_ctrl_47; +ch3_csr_chnl_in(735 DOWNTO 720) <= ch3_in_chnl_ctrl_47; +--ch4_csr_chnl_in(735 DOWNTO 720) <= ch4_in_chnl_ctrl_47; +--ch5_csr_chnl_in(735 DOWNTO 720) <= ch5_in_chnl_ctrl_47; + + +--------------------------------------------------------------- +-- Read DPRIOIN ----------------------------------------------- +--------------------------------------------------------------- + +-- -------- HW ordering ------------------------------------ +--TXPCS +ch0_out_chnl_ctrl_1 <= ch0_dp_chnl_out(15 DOWNTO 0); +ch1_out_chnl_ctrl_1 <= ch1_dp_chnl_out(15 DOWNTO 0); +ch2_out_chnl_ctrl_1 <= ch2_dp_chnl_out(15 DOWNTO 0); +ch3_out_chnl_ctrl_1 <= ch3_dp_chnl_out(15 DOWNTO 0); + +ch0_out_chnl_ctrl_2 <= ch0_dp_chnl_out(31 DOWNTO 16); +ch1_out_chnl_ctrl_2 <= ch1_dp_chnl_out(31 DOWNTO 16); +ch2_out_chnl_ctrl_2 <= ch2_dp_chnl_out(31 DOWNTO 16); +ch3_out_chnl_ctrl_2 <= ch3_dp_chnl_out(31 DOWNTO 16); + +ch0_out_chnl_ctrl_3 <= ch0_dp_chnl_out(47 DOWNTO 32); +ch1_out_chnl_ctrl_3 <= ch1_dp_chnl_out(47 DOWNTO 32); +ch2_out_chnl_ctrl_3 <= ch2_dp_chnl_out(47 DOWNTO 32); +ch3_out_chnl_ctrl_3 <= ch3_dp_chnl_out(47 DOWNTO 32); + +ch0_out_chnl_ctrl_4 <= ch0_dp_chnl_out(63 DOWNTO 48); +ch1_out_chnl_ctrl_4 <= ch1_dp_chnl_out(63 DOWNTO 48); +ch2_out_chnl_ctrl_4 <= ch2_dp_chnl_out(63 DOWNTO 48); +ch3_out_chnl_ctrl_4 <= ch3_dp_chnl_out(63 DOWNTO 48); + +ch0_out_chnl_ctrl_5 <= ch0_dp_chnl_out(79 DOWNTO 64); +ch1_out_chnl_ctrl_5 <= ch1_dp_chnl_out(79 DOWNTO 64); +ch2_out_chnl_ctrl_5 <= ch2_dp_chnl_out(79 DOWNTO 64); +ch3_out_chnl_ctrl_5 <= ch3_dp_chnl_out(79 DOWNTO 64); + +ch0_out_chnl_ctrl_6 <= ch0_dp_chnl_out(95 DOWNTO 80); +ch1_out_chnl_ctrl_6 <= ch1_dp_chnl_out(95 DOWNTO 80); +ch2_out_chnl_ctrl_6 <= ch2_dp_chnl_out(95 DOWNTO 80); +ch3_out_chnl_ctrl_6 <= ch3_dp_chnl_out(95 DOWNTO 80); + +ch0_out_chnl_ctrl_7 <= ch0_dp_chnl_out(111 DOWNTO 96); +ch1_out_chnl_ctrl_7 <= ch1_dp_chnl_out(111 DOWNTO 96); +ch2_out_chnl_ctrl_7 <= ch2_dp_chnl_out(111 DOWNTO 96); +ch3_out_chnl_ctrl_7 <= ch3_dp_chnl_out(111 DOWNTO 96); + +ch0_out_chnl_ctrl_8 <= ch0_dp_chnl_out(127 DOWNTO 112); +ch1_out_chnl_ctrl_8 <= ch1_dp_chnl_out(127 DOWNTO 112); +ch2_out_chnl_ctrl_8 <= ch2_dp_chnl_out(127 DOWNTO 112); +ch3_out_chnl_ctrl_8 <= ch3_dp_chnl_out(127 DOWNTO 112); + +ch0_out_chnl_ctrl_9 <= ch0_dp_chnl_out(143 DOWNTO 128); +ch1_out_chnl_ctrl_9 <= ch1_dp_chnl_out(143 DOWNTO 128); +ch2_out_chnl_ctrl_9 <= ch2_dp_chnl_out(143 DOWNTO 128); +ch3_out_chnl_ctrl_9 <= ch3_dp_chnl_out(143 DOWNTO 128); + +ch0_out_chnl_ctrl_10 <= ch0_dp_chnl_out(159 DOWNTO 144); +ch1_out_chnl_ctrl_10 <= ch1_dp_chnl_out(159 DOWNTO 144); +ch2_out_chnl_ctrl_10 <= ch2_dp_chnl_out(159 DOWNTO 144); +ch3_out_chnl_ctrl_10 <= ch3_dp_chnl_out(159 DOWNTO 144); + +ch0_out_chnl_ctrl_11 <= ch0_dp_chnl_out(175 DOWNTO 160); +ch1_out_chnl_ctrl_11 <= ch1_dp_chnl_out(175 DOWNTO 160); +ch2_out_chnl_ctrl_11 <= ch2_dp_chnl_out(175 DOWNTO 160); +ch3_out_chnl_ctrl_11 <= ch3_dp_chnl_out(175 DOWNTO 160); + +ch0_out_chnl_ctrl_12 <= ch0_dp_chnl_out(191 DOWNTO 176); +ch1_out_chnl_ctrl_12 <= ch1_dp_chnl_out(191 DOWNTO 176); +ch2_out_chnl_ctrl_12 <= ch2_dp_chnl_out(191 DOWNTO 176); +ch3_out_chnl_ctrl_12 <= ch3_dp_chnl_out(191 DOWNTO 176); + +ch0_out_chnl_ctrl_13 <= ch0_dp_chnl_out(207 DOWNTO 192); +ch1_out_chnl_ctrl_13 <= ch1_dp_chnl_out(207 DOWNTO 192); +ch2_out_chnl_ctrl_13 <= ch2_dp_chnl_out(207 DOWNTO 192); +ch3_out_chnl_ctrl_13 <= ch3_dp_chnl_out(207 DOWNTO 192); + +ch0_out_chnl_ctrl_14 <= ch0_dp_chnl_out(223 DOWNTO 208); +ch1_out_chnl_ctrl_14 <= ch1_dp_chnl_out(223 DOWNTO 208); +ch2_out_chnl_ctrl_14 <= ch2_dp_chnl_out(223 DOWNTO 208); +ch3_out_chnl_ctrl_14 <= ch3_dp_chnl_out(223 DOWNTO 208); + +ch0_out_chnl_ctrl_15 <= ch0_dp_chnl_out(239 DOWNTO 224); +ch1_out_chnl_ctrl_15 <= ch1_dp_chnl_out(239 DOWNTO 224); +ch2_out_chnl_ctrl_15 <= ch2_dp_chnl_out(239 DOWNTO 224); +ch3_out_chnl_ctrl_15 <= ch3_dp_chnl_out(239 DOWNTO 224); + +ch0_out_chnl_ctrl_16 <= ch0_dp_chnl_out(255 DOWNTO 240); +ch1_out_chnl_ctrl_16 <= ch1_dp_chnl_out(255 DOWNTO 240); +ch2_out_chnl_ctrl_16 <= ch2_dp_chnl_out(255 DOWNTO 240); +ch3_out_chnl_ctrl_16 <= ch3_dp_chnl_out(255 DOWNTO 240); + +ch0_out_chnl_ctrl_17 <= ch0_dp_chnl_out(271 DOWNTO 256); +ch1_out_chnl_ctrl_17 <= ch1_dp_chnl_out(271 DOWNTO 256); +ch2_out_chnl_ctrl_17 <= ch2_dp_chnl_out(271 DOWNTO 256); +ch3_out_chnl_ctrl_17 <= ch3_dp_chnl_out(271 DOWNTO 256); + +ch0_out_chnl_ctrl_18 <= ch0_dp_chnl_out(287 DOWNTO 272); +ch1_out_chnl_ctrl_18 <= ch1_dp_chnl_out(287 DOWNTO 272); +ch2_out_chnl_ctrl_18 <= ch2_dp_chnl_out(287 DOWNTO 272); +ch3_out_chnl_ctrl_18 <= ch3_dp_chnl_out(287 DOWNTO 272); + +ch0_out_chnl_ctrl_19 <= ch0_dp_chnl_out(303 DOWNTO 288); +ch1_out_chnl_ctrl_19 <= ch1_dp_chnl_out(303 DOWNTO 288); +ch2_out_chnl_ctrl_19 <= ch2_dp_chnl_out(303 DOWNTO 288); +ch3_out_chnl_ctrl_19 <= ch3_dp_chnl_out(303 DOWNTO 288); + +ch0_out_chnl_ctrl_20 <= ch0_dp_chnl_out(319 DOWNTO 304); +ch1_out_chnl_ctrl_20 <= ch1_dp_chnl_out(319 DOWNTO 304); +ch2_out_chnl_ctrl_20 <= ch2_dp_chnl_out(319 DOWNTO 304); +ch3_out_chnl_ctrl_20 <= ch3_dp_chnl_out(319 DOWNTO 304); + +ch0_out_chnl_ctrl_21 <= ch0_dp_chnl_out(335 DOWNTO 320); +ch1_out_chnl_ctrl_21 <= ch1_dp_chnl_out(335 DOWNTO 320); +ch2_out_chnl_ctrl_21 <= ch2_dp_chnl_out(335 DOWNTO 320); +ch3_out_chnl_ctrl_21 <= ch3_dp_chnl_out(335 DOWNTO 320); + +ch0_out_chnl_ctrl_22 <= ch0_dp_chnl_out(351 DOWNTO 336); +ch1_out_chnl_ctrl_22 <= ch1_dp_chnl_out(351 DOWNTO 336); +ch2_out_chnl_ctrl_22 <= ch2_dp_chnl_out(351 DOWNTO 336); +ch3_out_chnl_ctrl_22 <= ch3_dp_chnl_out(351 DOWNTO 336); + +ch0_out_chnl_ctrl_23 <= ch0_dp_chnl_out(367 DOWNTO 352); +ch1_out_chnl_ctrl_23 <= ch1_dp_chnl_out(367 DOWNTO 352); +ch2_out_chnl_ctrl_23 <= ch2_dp_chnl_out(367 DOWNTO 352); +ch3_out_chnl_ctrl_23 <= ch3_dp_chnl_out(367 DOWNTO 352); + +ch0_out_chnl_ctrl_24 <= ch0_dp_chnl_out(383 DOWNTO 368); +ch1_out_chnl_ctrl_24 <= ch1_dp_chnl_out(383 DOWNTO 368); +ch2_out_chnl_ctrl_24 <= ch2_dp_chnl_out(383 DOWNTO 368); +ch3_out_chnl_ctrl_24 <= ch3_dp_chnl_out(383 DOWNTO 368); + +ch0_out_chnl_ctrl_25 <= ch0_dp_chnl_out(399 DOWNTO 384); +ch1_out_chnl_ctrl_25 <= ch1_dp_chnl_out(399 DOWNTO 384); +ch2_out_chnl_ctrl_25 <= ch2_dp_chnl_out(399 DOWNTO 384); +ch3_out_chnl_ctrl_25 <= ch3_dp_chnl_out(399 DOWNTO 384); + +ch0_out_chnl_ctrl_26 <= ch0_dp_chnl_out(415 DOWNTO 400); +ch1_out_chnl_ctrl_26 <= ch1_dp_chnl_out(415 DOWNTO 400); +ch2_out_chnl_ctrl_26 <= ch2_dp_chnl_out(415 DOWNTO 400); +ch3_out_chnl_ctrl_26 <= ch3_dp_chnl_out(415 DOWNTO 400); + +ch0_out_chnl_ctrl_27 <= ch0_dp_chnl_out(431 DOWNTO 416); +ch1_out_chnl_ctrl_27 <= ch1_dp_chnl_out(431 DOWNTO 416); +ch2_out_chnl_ctrl_27 <= ch2_dp_chnl_out(431 DOWNTO 416); +ch3_out_chnl_ctrl_27 <= ch3_dp_chnl_out(431 DOWNTO 416); + +--TXPMA +ch0_out_chnl_ctrl_28 <= ch0_dp_chnl_out(447 DOWNTO 432); +ch1_out_chnl_ctrl_28 <= ch1_dp_chnl_out(447 DOWNTO 432); +ch2_out_chnl_ctrl_28 <= ch2_dp_chnl_out(447 DOWNTO 432); +ch3_out_chnl_ctrl_28 <= ch3_dp_chnl_out(447 DOWNTO 432); +--ch4_out_chnl_ctrl_28 <= ch4_dp_chnl_out(447 DOWNTO 432); +--ch5_out_chnl_ctrl_28 <= ch5_dp_chnl_out(447 DOWNTO 432); + +ch0_out_chnl_ctrl_29 <= ch0_dp_chnl_out(463 DOWNTO 448); +ch1_out_chnl_ctrl_29 <= ch1_dp_chnl_out(463 DOWNTO 448); +ch2_out_chnl_ctrl_29 <= ch2_dp_chnl_out(463 DOWNTO 448); +ch3_out_chnl_ctrl_29 <= ch3_dp_chnl_out(463 DOWNTO 448); +--ch4_out_chnl_ctrl_29 <= ch4_dp_chnl_out(463 DOWNTO 448); +--ch5_out_chnl_ctrl_29 <= ch5_dp_chnl_out(463 DOWNTO 448); + +ch0_out_chnl_ctrl_30 <= ch0_dp_chnl_out(479 DOWNTO 464); +ch1_out_chnl_ctrl_30 <= ch1_dp_chnl_out(479 DOWNTO 464); +ch2_out_chnl_ctrl_30 <= ch2_dp_chnl_out(479 DOWNTO 464); +ch3_out_chnl_ctrl_30 <= ch3_dp_chnl_out(479 DOWNTO 464); +--ch4_out_chnl_ctrl_30 <= ch4_dp_chnl_out(479 DOWNTO 464); +--ch5_out_chnl_ctrl_30 <= ch5_dp_chnl_out(479 DOWNTO 464); + +ch0_out_chnl_ctrl_31 <= ch0_dp_chnl_out(495 DOWNTO 480); +ch1_out_chnl_ctrl_31 <= ch1_dp_chnl_out(495 DOWNTO 480); +ch2_out_chnl_ctrl_31 <= ch2_dp_chnl_out(495 DOWNTO 480); +ch3_out_chnl_ctrl_31 <= ch3_dp_chnl_out(495 DOWNTO 480); +--ch4_out_chnl_ctrl_31 <= ch4_dp_chnl_out(495 DOWNTO 480); +--ch5_out_chnl_ctrl_31 <= ch5_dp_chnl_out(495 DOWNTO 480); + +ch0_out_chnl_ctrl_32 <= ch0_dp_chnl_out(511 DOWNTO 496); +ch1_out_chnl_ctrl_32 <= ch1_dp_chnl_out(511 DOWNTO 496); +ch2_out_chnl_ctrl_32 <= ch2_dp_chnl_out(511 DOWNTO 496); +ch3_out_chnl_ctrl_32 <= ch3_dp_chnl_out(511 DOWNTO 496); +--ch4_out_chnl_ctrl_32 <= ch4_dp_chnl_out(511 DOWNTO 496); +--ch5_out_chnl_ctrl_32 <= ch5_dp_chnl_out(511 DOWNTO 496); + +ch0_out_chnl_ctrl_33 <= ch0_dp_chnl_out(527 DOWNTO 512); +ch1_out_chnl_ctrl_33 <= ch1_dp_chnl_out(527 DOWNTO 512); +ch2_out_chnl_ctrl_33 <= ch2_dp_chnl_out(527 DOWNTO 512); +ch3_out_chnl_ctrl_33 <= ch3_dp_chnl_out(527 DOWNTO 512); +--ch4_out_chnl_ctrl_33 <= ch4_dp_chnl_out(527 DOWNTO 512); +--ch5_out_chnl_ctrl_33 <= ch5_dp_chnl_out(527 DOWNTO 512); + +ch0_out_chnl_ctrl_34 <= ch0_dp_chnl_out(543 DOWNTO 528); +ch1_out_chnl_ctrl_34 <= ch1_dp_chnl_out(543 DOWNTO 528); +ch2_out_chnl_ctrl_34 <= ch2_dp_chnl_out(543 DOWNTO 528); +ch3_out_chnl_ctrl_34 <= ch3_dp_chnl_out(543 DOWNTO 528); +--ch4_out_chnl_ctrl_34 <= ch4_dp_chnl_out(543 DOWNTO 528); +--ch5_out_chnl_ctrl_34 <= ch5_dp_chnl_out(543 DOWNTO 528); + +ch0_out_chnl_ctrl_35 <= ch0_dp_chnl_out(559 DOWNTO 544); +ch1_out_chnl_ctrl_35 <= ch1_dp_chnl_out(559 DOWNTO 544); +ch2_out_chnl_ctrl_35 <= ch2_dp_chnl_out(559 DOWNTO 544); +ch3_out_chnl_ctrl_35 <= ch3_dp_chnl_out(559 DOWNTO 544); +--ch4_out_chnl_ctrl_35 <= ch4_dp_chnl_out(559 DOWNTO 544); +--ch5_out_chnl_ctrl_35 <= ch5_dp_chnl_out(559 DOWNTO 544); + +ch0_out_chnl_ctrl_36 <= ch0_dp_chnl_out(575 DOWNTO 560); +ch1_out_chnl_ctrl_36 <= ch1_dp_chnl_out(575 DOWNTO 560); +ch2_out_chnl_ctrl_36 <= ch2_dp_chnl_out(575 DOWNTO 560); +ch3_out_chnl_ctrl_36 <= ch3_dp_chnl_out(575 DOWNTO 560); +--ch4_out_chnl_ctrl_36 <= ch4_dp_chnl_out(575 DOWNTO 560); +--ch5_out_chnl_ctrl_36 <= ch5_dp_chnl_out(575 DOWNTO 560); + +ch0_out_chnl_ctrl_37 <= ch0_dp_chnl_out(591 DOWNTO 576); +ch1_out_chnl_ctrl_37 <= ch1_dp_chnl_out(591 DOWNTO 576); +ch2_out_chnl_ctrl_37 <= ch2_dp_chnl_out(591 DOWNTO 576); +ch3_out_chnl_ctrl_37 <= ch3_dp_chnl_out(591 DOWNTO 576); +--ch4_out_chnl_ctrl_37 <= ch4_dp_chnl_out(591 DOWNTO 576); +--ch5_out_chnl_ctrl_37 <= ch5_dp_chnl_out(591 DOWNTO 576); + +ch0_out_chnl_ctrl_38 <= ch0_dp_chnl_out(607 DOWNTO 592); +ch1_out_chnl_ctrl_38 <= ch1_dp_chnl_out(607 DOWNTO 592); +ch2_out_chnl_ctrl_38 <= ch2_dp_chnl_out(607 DOWNTO 592); +ch3_out_chnl_ctrl_38 <= ch3_dp_chnl_out(607 DOWNTO 592); +--ch4_out_chnl_ctrl_38 <= ch4_dp_chnl_out(607 DOWNTO 592); +--ch5_out_chnl_ctrl_38 <= ch5_dp_chnl_out(607 DOWNTO 592); + +ch0_out_chnl_ctrl_39 <= ch0_dp_chnl_out(623 DOWNTO 608); +ch1_out_chnl_ctrl_39 <= ch1_dp_chnl_out(623 DOWNTO 608); +ch2_out_chnl_ctrl_39 <= ch2_dp_chnl_out(623 DOWNTO 608); +ch3_out_chnl_ctrl_39 <= ch3_dp_chnl_out(623 DOWNTO 608); +--ch4_out_chnl_ctrl_39 <= ch4_dp_chnl_out(623 DOWNTO 608); +--ch5_out_chnl_ctrl_39 <= ch5_dp_chnl_out(623 DOWNTO 608); + +ch0_out_chnl_ctrl_40 <= ch0_dp_chnl_out(639 DOWNTO 624); +ch1_out_chnl_ctrl_40 <= ch1_dp_chnl_out(639 DOWNTO 624); +ch2_out_chnl_ctrl_40 <= ch2_dp_chnl_out(639 DOWNTO 624); +ch3_out_chnl_ctrl_40 <= ch3_dp_chnl_out(639 DOWNTO 624); +--ch4_out_chnl_ctrl_40 <= ch4_dp_chnl_out(639 DOWNTO 624); +--ch5_out_chnl_ctrl_40 <= ch5_dp_chnl_out(639 DOWNTO 624); + +ch0_out_chnl_ctrl_41 <= ch0_dp_chnl_out(655 DOWNTO 640); +ch1_out_chnl_ctrl_41 <= ch1_dp_chnl_out(655 DOWNTO 640); +ch2_out_chnl_ctrl_41 <= ch2_dp_chnl_out(655 DOWNTO 640); +ch3_out_chnl_ctrl_41 <= ch3_dp_chnl_out(655 DOWNTO 640); +--ch4_out_chnl_ctrl_41 <= ch4_dp_chnl_out(655 DOWNTO 640); +--ch5_out_chnl_ctrl_41 <= ch5_dp_chnl_out(655 DOWNTO 640); + +ch0_out_chnl_ctrl_42 <= ch0_dp_chnl_out(671 DOWNTO 656); +ch1_out_chnl_ctrl_42 <= ch1_dp_chnl_out(671 DOWNTO 656); +ch2_out_chnl_ctrl_42 <= ch2_dp_chnl_out(671 DOWNTO 656); +ch3_out_chnl_ctrl_42 <= ch3_dp_chnl_out(671 DOWNTO 656); +--ch4_out_chnl_ctrl_42 <= ch4_dp_chnl_out(671 DOWNTO 656); +--ch5_out_chnl_ctrl_42 <= ch5_dp_chnl_out(671 DOWNTO 656); + +-- reserved +ch0_out_chnl_ctrl_43 <= ch0_dp_chnl_out_reserved(15 DOWNTO 0); +ch1_out_chnl_ctrl_43 <= ch1_dp_chnl_out_reserved(15 DOWNTO 0); +ch2_out_chnl_ctrl_43 <= ch2_dp_chnl_out_reserved(15 DOWNTO 0); +ch3_out_chnl_ctrl_43 <= ch3_dp_chnl_out_reserved(15 DOWNTO 0); +--ch4_out_chnl_ctrl_43 <= ch4_dp_chnl_out(15 DOWNTO 0); +--ch5_out_chnl_ctrl_43 <= ch5_dp_chnl_out(15 DOWNTO 0); + +ch0_out_chnl_ctrl_44 <= ch0_dp_chnl_out(687 DOWNTO 672); +ch1_out_chnl_ctrl_44 <= ch1_dp_chnl_out(687 DOWNTO 672); +ch2_out_chnl_ctrl_44 <= ch2_dp_chnl_out(687 DOWNTO 672); +ch3_out_chnl_ctrl_44 <= ch3_dp_chnl_out(687 DOWNTO 672); +--ch4_out_chnl_ctrl_44 <= ch4_dp_chnl_out(687 DOWNTO 672); +--ch5_out_chnl_ctrl_44 <= ch5_dp_chnl_out(687 DOWNTO 672); + +ch0_out_chnl_ctrl_45 <= ch0_dp_chnl_out(703 DOWNTO 688); +ch1_out_chnl_ctrl_45 <= ch1_dp_chnl_out(703 DOWNTO 688); +ch2_out_chnl_ctrl_45 <= ch2_dp_chnl_out(703 DOWNTO 688); +ch3_out_chnl_ctrl_45 <= ch3_dp_chnl_out(703 DOWNTO 688); +--ch4_out_chnl_ctrl_45 <= ch4_dp_chnl_out(703 DOWNTO 688); +--ch5_out_chnl_ctrl_45 <= ch5_dp_chnl_out(703 DOWNTO 688); + +ch0_out_chnl_ctrl_46 <= ch0_dp_chnl_out(719 DOWNTO 704); +ch1_out_chnl_ctrl_46 <= ch1_dp_chnl_out(719 DOWNTO 704); +ch2_out_chnl_ctrl_46 <= ch2_dp_chnl_out(719 DOWNTO 704); +ch3_out_chnl_ctrl_46 <= ch3_dp_chnl_out(719 DOWNTO 704); +--ch4_out_chnl_ctrl_46 <= ch4_dp_chnl_out(719 DOWNTO 704); +--ch5_out_chnl_ctrl_46 <= ch5_dp_chnl_out(719 DOWNTO 704); + +ch0_out_chnl_ctrl_47 <= ch0_dp_chnl_out(735 DOWNTO 720); +ch1_out_chnl_ctrl_47 <= ch1_dp_chnl_out(735 DOWNTO 720); +ch2_out_chnl_ctrl_47 <= ch2_dp_chnl_out(735 DOWNTO 720); +ch3_out_chnl_ctrl_47 <= ch3_dp_chnl_out(735 DOWNTO 720); +--ch4_out_chnl_ctrl_47 <= ch4_dp_chnl_out(735 DOWNTO 720); +--ch5_out_chnl_ctrl_47 <= ch5_dp_chnl_out(735 DOWNTO 720); + +-- -------- SW ordering ------------------------------------ +--TXPCS +ch0_txpcsdprioout_phy(rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0) <= ch0_out_chnl_ctrl_1; +ch1_txpcsdprioout_phy(rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0) <= ch1_out_chnl_ctrl_1; +ch2_txpcsdprioout_phy(rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0) <= ch2_out_chnl_ctrl_1; +ch3_txpcsdprioout_phy(rforce_kchar_DP_TXPCS_IDX_0 DOWNTO rforce_disp_DP_TXPCS_IDX_0) <= ch3_out_chnl_ctrl_1; + +ch0_txpcsdprioout_phy(rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0) <= ch0_out_chnl_ctrl_2; +ch1_txpcsdprioout_phy(rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0) <= ch1_out_chnl_ctrl_2; +ch2_txpcsdprioout_phy(rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0) <= ch2_out_chnl_ctrl_2; +ch3_txpcsdprioout_phy(rendec_tx_DP_TXPCS_IDX_0 DOWNTO rtxpcsbypass_en_DP_TXPCS_IDX_0) <= ch3_out_chnl_ctrl_2; + +ch0_txpcsdprioout_phy(rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0) <= ch0_out_chnl_ctrl_3; +ch1_txpcsdprioout_phy(rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0) <= ch1_out_chnl_ctrl_3; +ch2_txpcsdprioout_phy(rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0) <= ch2_out_chnl_ctrl_3; +ch3_txpcsdprioout_phy(rtx_pipe_enable_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB3_DP_TXPCS_IDX_0) <= ch3_out_chnl_ctrl_3; + +ch0_txpcsdprioout_phy(rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0) <= ch0_out_chnl_ctrl_4; +ch1_txpcsdprioout_phy(rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0) <= ch1_out_chnl_ctrl_4; +ch2_txpcsdprioout_phy(rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0) <= ch2_out_chnl_ctrl_4; +ch3_txpcsdprioout_phy(rself_sw_en_tx_DP_TXPCS_IDX_0 DOWNTO reserved_0_TB4_DP_TXPCS_IDX_0) <= ch3_out_chnl_ctrl_4; + +ch0_rxpcsdprioout_phy(reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_5; +ch1_rxpcsdprioout_phy(reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_5; +ch2_rxpcsdprioout_phy(reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_5; +ch3_rxpcsdprioout_phy(reserved_0_TB5_DP_RXPCS_IDX_0 DOWNTO rrxpcsbypass_en_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_5; + +ch0_rxpcsdprioout_phy(reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_6; +ch1_rxpcsdprioout_phy(reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_6; +ch2_rxpcsdprioout_phy(reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_6; +ch3_rxpcsdprioout_phy(reserved_0_TB6_DP_RXPCS_IDX_1 DOWNTO reserved_3_TB6_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_6; + +ch0_rxpcsdprioout_phy(rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_7; +ch1_rxpcsdprioout_phy(rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_7; +ch2_rxpcsdprioout_phy(rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_7; +ch3_rxpcsdprioout_phy(rcomp_pat_31_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_16_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_7; + +ch0_rxpcsdprioout_phy(rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_8; +ch1_rxpcsdprioout_phy(rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_8; +ch2_rxpcsdprioout_phy(rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_8; +ch3_rxpcsdprioout_phy(rcomp_pat_15_DP_RXPCS_IDX_0 DOWNTO rcomp_pat_0_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_8; + +ch0_rxpcsdprioout_phy(rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_9; +ch1_rxpcsdprioout_phy(rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_9; +ch2_rxpcsdprioout_phy(rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_9; +ch3_rxpcsdprioout_phy(rsync_sm_dis_DP_RXPCS_IDX_0 DOWNTO rbitloc_rev_en_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_9; + +ch0_rxpcsdprioout_phy(rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_10; +ch1_rxpcsdprioout_phy(rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_10; +ch2_rxpcsdprioout_phy(rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_10; +ch3_rxpcsdprioout_phy(rgnumber_DP_RXPCS_IDX_7 DOWNTO rknumber_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_10; + +ch0_rxpcsdprioout_phy(rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_11; +ch1_rxpcsdprioout_phy(rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_11; +ch2_rxpcsdprioout_phy(rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_11; +ch3_rxpcsdprioout_phy(rrundisp_DP_RXPCS_IDX_5 DOWNTO renpolinv_rx_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_11; + +ch0_rxpcsdprioout_phy(rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_12; +ch1_rxpcsdprioout_phy(rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_12; +ch2_rxpcsdprioout_phy(rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_12; +ch3_rxpcsdprioout_phy(rmatchen_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_12; + +ch0_rxpcsdprioout_phy(rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_13; +ch1_rxpcsdprioout_phy(rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_13; +ch2_rxpcsdprioout_phy(rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_13; +ch3_rxpcsdprioout_phy(rclkcmpsq1n_19_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1p_10_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_13; + +ch0_rxpcsdprioout_phy(rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_14; +ch1_rxpcsdprioout_phy(rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_14; +ch2_rxpcsdprioout_phy(rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_14; +ch3_rxpcsdprioout_phy(rclkcmpsq1n_14_DP_RXPCS_IDX_0 DOWNTO rclkcmpsq1n_0_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_14; + +ch0_rxpcsdprioout_phy(rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_15; +ch1_rxpcsdprioout_phy(rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_15; +ch2_rxpcsdprioout_phy(rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_15; +ch3_rxpcsdprioout_phy(rclkcmp_pipe_en_DP_RXPCS_IDX_0 DOWNTO rfull_threshold_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_15; + +ch0_rxpcsdprioout_phy(rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX) <= ch0_out_chnl_ctrl_16; +ch1_rxpcsdprioout_phy(rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX) <= ch1_out_chnl_ctrl_16; +ch2_rxpcsdprioout_phy(rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX) <= ch2_out_chnl_ctrl_16; +ch3_rxpcsdprioout_phy(rempty_threshold_DP_RXPCS_IDX_2 DOWNTO rfreq_sel_DP_RXPCS_IDX) <= ch3_out_chnl_ctrl_16; + +ch0_rxpcsdprioout_phy(rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_17; +ch1_rxpcsdprioout_phy(rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_17; +ch2_rxpcsdprioout_phy(rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_17; +ch3_rxpcsdprioout_phy(rrxfifo_dis_DP_RXPCS_IDX_0 DOWNTO rtest_bus_sel_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_17; + +ch0_rxpcsdprioout_phy(reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_18; +ch1_rxpcsdprioout_phy(reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_18; +ch2_rxpcsdprioout_phy(reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_18; +ch3_rxpcsdprioout_phy(reserved_0_TB18_DP_RXPCS_IDX_5 DOWNTO rbytordpat_0_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_18; + +ch0_rxpcsdprioout_phy(reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_19; +ch1_rxpcsdprioout_phy(reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_19; +ch2_rxpcsdprioout_phy(reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_19; +ch3_rxpcsdprioout_phy(reserved_0_TB19_DP_RXPCS_IDX_5 DOWNTO rbytordpad_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_19; + +ch0_rxpcsdprioout_phy(rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_20; +ch1_rxpcsdprioout_phy(rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_20; +ch2_rxpcsdprioout_phy(rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_20; +ch3_rxpcsdprioout_phy(rrx_pipe_enable_DP_RXPCS_IDX_0 DOWNTO rload_shreg_del_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_20; + +ch0_rxpcsdprioout_phy(rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_21; +ch1_rxpcsdprioout_phy(rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_21; +ch2_rxpcsdprioout_phy(rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_21; +ch3_rxpcsdprioout_phy(rpma_done_count_15_DP_RXPCS_IDX_0 DOWNTO rpma_done_count_0_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_21; + +ch0_rxpcsdprioout_phy(rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_22; +ch1_rxpcsdprioout_phy(rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_22; +ch2_rxpcsdprioout_phy(rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_22; +ch3_rxpcsdprioout_phy(rerr_flags_sel_DP_RXPCS_IDX_0 DOWNTO reserved_0_TB22_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_22; + +ch0_rxpcsdprioout_phy(reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_23; +ch1_rxpcsdprioout_phy(reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_23; +ch2_rxpcsdprioout_phy(reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_23; +ch3_rxpcsdprioout_phy(reserved_0_TB23_DP_RXPCS_IDX_7 DOWNTO rwait_count_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_23; + +ch0_rxpcsdprioout_phy(rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_24; +ch1_rxpcsdprioout_phy(rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_24; +ch2_rxpcsdprioout_phy(rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_24; +ch3_rxpcsdprioout_phy(rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 DOWNTO rfts_count_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_24; + +ch0_rxpcsdprioout_phy(reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_25; +ch1_rxpcsdprioout_phy(reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_25; +ch2_rxpcsdprioout_phy(reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_25; +ch3_rxpcsdprioout_phy(reserved_0_TB25_DP_RXPCS_IDX_4 DOWNTO rppm_meas_delay_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_25; + +ch0_rxpcsdprioout_phy(rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_26; +ch1_rxpcsdprioout_phy(rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_26; +ch2_rxpcsdprioout_phy(rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_26; +ch3_rxpcsdprioout_phy(rphfifo_regmode_rx_DP_RXPCS_IDX_0 DOWNTO rauto_pc_en_cnt_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_26; + +ch0_rxpcsdprioout_phy(reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0) <= ch0_out_chnl_ctrl_27; +ch1_rxpcsdprioout_phy(reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0) <= ch1_out_chnl_ctrl_27; +ch2_rxpcsdprioout_phy(reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0) <= ch2_out_chnl_ctrl_27; +ch3_rxpcsdprioout_phy(reserved_0_TB27_DP_RXPCS_IDX_3 DOWNTO rmask_count_DP_RXPCS_IDX_0) <= ch3_out_chnl_ctrl_27; + +--TXPMA +ch0_txpmadprioout_phy(rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_28; +ch1_txpmadprioout_phy(rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_28; +ch2_txpmadprioout_phy(rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_28; +ch3_txpmadprioout_phy(rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_28; +ch4_txpmadprioout_phy(rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_28; +ch5_txpmadprioout_phy(rvod_sel_non_pcie_TXPMA_IDX_2 DOWNTO rpowdnt_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_28; + +ch0_txpmadprioout_phy(rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_29; +ch1_txpmadprioout_phy(rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_29; +ch2_txpmadprioout_phy(rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_29; +ch3_txpmadprioout_phy(rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_29; +ch4_txpmadprioout_phy(rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_29; +ch5_txpmadprioout_phy(rpre_em_1t_no_pcie_TXPMA_IDX_4 DOWNTO reserved_0_TB29_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_29; + +ch0_txpmadprioout_phy(reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_30; +ch1_txpmadprioout_phy(reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_30; +ch2_txpmadprioout_phy(reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_30; +ch3_txpmadprioout_phy(reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_30; +ch4_txpmadprioout_phy(reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_30; +ch5_txpmadprioout_phy(reserved_0_TB30_TXPMA_IDX_15 DOWNTO reserved_0_TB30_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_30; + +ch0_txpmadprioout_phy(rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_31; +ch1_txpmadprioout_phy(rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_31; +ch2_txpmadprioout_phy(rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_31; +ch3_txpmadprioout_phy(rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_31; +ch4_txpmadprioout_phy(rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_31; +ch5_txpmadprioout_phy(rtx_term_sel_TXPMA_IDX_2 DOWNTO rlowv_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_31; + +ch0_txpmadprioout_phy(r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_32; +ch1_txpmadprioout_phy(r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_32; +ch2_txpmadprioout_phy(r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_32; +ch3_txpmadprioout_phy(r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_32; +ch4_txpmadprioout_phy(r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_32; +ch5_txpmadprioout_phy(r_dft_sel_TXPMA_IDX_2 DOWNTO reserved_1_TB32_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_32; + +-- does not hurt for tx_pma to receiver clock_divider cram - bit[7] goes to rx_pma - manual section +-- ch0_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33; +-- ch1_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33; +-- ch2_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33; +-- ch3_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33; +-- ch4_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33; +-- ch5_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33; + +ch0_rxpmadprioout_phy(ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_34; +ch1_rxpmadprioout_phy(ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_34; +ch2_rxpmadprioout_phy(ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_34; +ch3_rxpmadprioout_phy(ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_34; +ch4_rxpmadprioout_phy(ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_34; +ch5_rxpmadprioout_phy(ricdr_rlocdiv_TXPMA_IDX_7 DOWNTO ricdr_reserved_0_TB34_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_34; + +ch0_txpmadprioout_phy(rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_35; +ch1_txpmadprioout_phy(rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_35; +ch2_txpmadprioout_phy(rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_35; +ch3_txpmadprioout_phy(rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_35; +ch4_txpmadprioout_phy(rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_35; +ch5_txpmadprioout_phy(rpma_reserved_0_TB35_TXPMA_IDX_15 DOWNTO rpma_reserved_0_TB35_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_35; + +ch0_rxpmadprioout_phy(rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_36; +ch1_rxpmadprioout_phy(rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_36; +ch2_rxpmadprioout_phy(rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_36; +ch3_rxpmadprioout_phy(rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_36; +ch4_rxpmadprioout_phy(rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_36; +ch5_rxpmadprioout_phy(rrx_lst_RXPMA_IDX_4 DOWNTO rrx_term_sel_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_36; + +ch0_rxpmadprioout_phy(rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_37; +ch1_rxpmadprioout_phy(rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_37; +ch2_rxpmadprioout_phy(rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_37; +ch3_rxpmadprioout_phy(rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_37; +ch4_rxpmadprioout_phy(rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_37; +ch5_rxpmadprioout_phy(rrx_sdlv_RXPMA_IDX_3 DOWNTO rrxurstpma_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_37; + +ch0_rxpmadprioout_phy(rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_38; +ch1_rxpmadprioout_phy(rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_38; +ch2_rxpmadprioout_phy(rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_38; +ch3_rxpmadprioout_phy(rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_38; +ch4_rxpmadprioout_phy(rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_38; +ch5_rxpmadprioout_phy(rrx_sd_on_RXPMA_IDX_3 DOWNTO reserved_0_TB38_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_38; + +ch0_rxpmadprioout_phy(ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0) <= ch0_out_chnl_ctrl_39; +ch1_rxpmadprioout_phy(ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0) <= ch1_out_chnl_ctrl_39; +ch2_rxpmadprioout_phy(ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0) <= ch2_out_chnl_ctrl_39; +ch3_rxpmadprioout_phy(ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0) <= ch3_out_chnl_ctrl_39; +ch4_rxpmadprioout_phy(ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0) <= ch4_out_chnl_ctrl_39; +ch5_rxpmadprioout_phy(ricdr_rcl_lo_DP DOWNTO ricdr_freq_sel_pi_IDX_0) <= ch5_out_chnl_ctrl_39; + +ch0_rxpmadprioout_phy(ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0) <= ch0_out_chnl_ctrl_40; +ch1_rxpmadprioout_phy(ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0) <= ch1_out_chnl_ctrl_40; +ch2_rxpmadprioout_phy(ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0) <= ch2_out_chnl_ctrl_40; +ch3_rxpmadprioout_phy(ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0) <= ch3_out_chnl_ctrl_40; +ch4_rxpmadprioout_phy(ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0) <= ch4_out_chnl_ctrl_40; +ch5_rxpmadprioout_phy(ricdr_rcl_lo_tb40_IDX_7 DOWNTO ricdr_rcl_hi_tb40_IDX_0) <= ch5_out_chnl_ctrl_40; + +ch0_rxpmadprioout_phy(reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0) <= ch0_out_chnl_ctrl_41; +ch1_rxpmadprioout_phy(reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0) <= ch1_out_chnl_ctrl_41; +ch2_rxpmadprioout_phy(reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0) <= ch2_out_chnl_ctrl_41; +ch3_rxpmadprioout_phy(reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0) <= ch3_out_chnl_ctrl_41; +ch4_rxpmadprioout_phy(reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0) <= ch4_out_chnl_ctrl_41; +ch5_rxpmadprioout_phy(reserved_6_tb41_IDX_0 DOWNTO reserved_0_tb41_IDX_0) <= ch5_out_chnl_ctrl_41; + +ch0_rxpmadprioout_phy(reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_42; +ch1_rxpmadprioout_phy(reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_42; +ch2_rxpmadprioout_phy(reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_42; +ch3_rxpmadprioout_phy(reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_42; +ch4_rxpmadprioout_phy(reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_42; +ch5_rxpmadprioout_phy(reserved_0_tb42_IDX_0 DOWNTO rphsel_clkdivrx_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_42; + +-- reserved +ch0_rxpmadprioout_phy(reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_43; +ch1_rxpmadprioout_phy(reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_43; +ch2_rxpmadprioout_phy(reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_43; +ch3_rxpmadprioout_phy(reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_43; +ch4_rxpmadprioout_phy(reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_43; +ch5_rxpmadprioout_phy(reserved_0_TB43_RXPMA_IDX_0 DOWNTO rloopback1_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_43; + +ch0_rxpmadprioout_phy(rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_44; +ch1_rxpmadprioout_phy(rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_44; +ch2_rxpmadprioout_phy(rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_44; +ch3_rxpmadprioout_phy(rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_44; +ch4_rxpmadprioout_phy(rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_44; +ch5_rxpmadprioout_phy(rprst_RXPMA_IDX_5 DOWNTO rclk_sd_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_44; + +ch0_rxpmadprioout_phy(reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_45; +ch1_rxpmadprioout_phy(reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_45; +ch2_rxpmadprioout_phy(reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_45; +ch3_rxpmadprioout_phy(reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_45; +ch4_rxpmadprioout_phy(reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_45; +ch5_rxpmadprioout_phy(reserved_2_TB45_RXPMA_IDX_0 DOWNTO rppm_cnt_reset_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_45; + +ch0_rxpmadprioout_phy(r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_46; +ch1_rxpmadprioout_phy(r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_46; +ch2_rxpmadprioout_phy(r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_46; +ch3_rxpmadprioout_phy(r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_46; +ch4_rxpmadprioout_phy(r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_46; +ch5_rxpmadprioout_phy(r_dfe_1t_RXPMA_IDX_2 DOWNTO reserved_0_TB46_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_46; + +ch0_rxpmadprioout_phy(reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0) <= ch0_out_chnl_ctrl_47; +ch1_rxpmadprioout_phy(reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0) <= ch1_out_chnl_ctrl_47; +ch2_rxpmadprioout_phy(reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0) <= ch2_out_chnl_ctrl_47; +ch3_rxpmadprioout_phy(reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0) <= ch3_out_chnl_ctrl_47; +ch4_rxpmadprioout_phy(reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0) <= ch4_out_chnl_ctrl_47; +ch5_rxpmadprioout_phy(reserved_0_TB47_RXPMA_IDX_0 DOWNTO reqv_set_RXPMA_IDX_0) <= ch5_out_chnl_ctrl_47; + +--------------------------------------------------------------- +-- Manual section due to one ICD CRAM mapped to multiple Atoms +--------------------------------------------------------------- +-- RX_PCS ----------------------------------------------------- +ch0_rxpcsdprioout_phy(rpmadwidth_rx_RXPCS_IDX) <= ch0_out_chnl_ctrl_45(14); +ch1_rxpcsdprioout_phy(rpmadwidth_rx_RXPCS_IDX) <= ch1_out_chnl_ctrl_45(14); +ch2_rxpcsdprioout_phy(rpmadwidth_rx_RXPCS_IDX) <= ch2_out_chnl_ctrl_45(14); +ch3_rxpcsdprioout_phy(rpmadwidth_rx_RXPCS_IDX) <= ch3_out_chnl_ctrl_45(14); + +ch0_rxpcsdprioout_phy(rpma_doublewidth_rx_DP_RXPCS_IDX) <= ch0_out_chnl_ctrl_45(15); +ch1_rxpcsdprioout_phy(rpma_doublewidth_rx_DP_RXPCS_IDX) <= ch1_out_chnl_ctrl_45(15); +ch2_rxpcsdprioout_phy(rpma_doublewidth_rx_DP_RXPCS_IDX) <= ch2_out_chnl_ctrl_45(15); +ch3_rxpcsdprioout_phy(rpma_doublewidth_rx_DP_RXPCS_IDX) <= ch3_out_chnl_ctrl_45(15); + +-- ---------------------------------------------------------------------------------------------------------------- +-- Manual section - global CRAMs to individual channels +-- ---------------------------------------------------------------------------------------------------------------- + +-- global ctrl 1 - centrl_ctrl_44 +ch0_rxpcsdprioout_phy(rendec_data_sel_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(6); +ch1_rxpcsdprioout_phy(rendec_data_sel_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(6); +ch2_rxpcsdprioout_phy(rendec_data_sel_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(6); +ch3_rxpcsdprioout_phy(rendec_data_sel_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(6); + +ch0_rxpcsdprioout_phy(rdeskewen_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(2); +ch1_rxpcsdprioout_phy(rdeskewen_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(2); +ch2_rxpcsdprioout_phy(rdeskewen_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(2); +ch3_rxpcsdprioout_phy(rdeskewen_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(2); + +ch0_rxpcsdprioout_phy(rindv_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(0); +ch1_rxpcsdprioout_phy(rindv_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(0); +ch2_rxpcsdprioout_phy(rindv_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(0); +ch3_rxpcsdprioout_phy(rindv_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_1(0); + +-- global ctrl 2 - centrl_ctrl_45 +ch0_rxpcsdprioout_phy(rdskposdisp_DP_RXPCS_IDX) <= cmu_out_centrl_global_2(10); +ch1_rxpcsdprioout_phy(rdskposdisp_DP_RXPCS_IDX) <= cmu_out_centrl_global_2(10); +ch2_rxpcsdprioout_phy(rdskposdisp_DP_RXPCS_IDX) <= cmu_out_centrl_global_2(10); +ch3_rxpcsdprioout_phy(rdskposdisp_DP_RXPCS_IDX) <= cmu_out_centrl_global_2(10); + +-- global ctrl 3 - centrl_ctrl_46 +ch0_rxpcsdprioout_phy(rmaster_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(3); +ch1_rxpcsdprioout_phy(rmaster_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(3); +ch2_rxpcsdprioout_phy(rmaster_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(3); +ch3_rxpcsdprioout_phy(rmaster_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(3); + +ch0_rxpcsdprioout_phy(rmaster_up_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(2); +ch1_rxpcsdprioout_phy(rmaster_up_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(2); +ch2_rxpcsdprioout_phy(rmaster_up_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(2); +ch3_rxpcsdprioout_phy(rmaster_up_rx_DP_RXPCS_IDX) <= cmu_out_centrl_global_3(2); + +-- TX_PCS ----------------------------------------------------- +ch0_txpcsdprioout_phy(rfreq_sel_DP_TXPCS_IDX) <= ch0_out_chnl_ctrl_16(0); +ch1_txpcsdprioout_phy(rfreq_sel_DP_TXPCS_IDX) <= ch1_out_chnl_ctrl_16(0); +ch2_txpcsdprioout_phy(rfreq_sel_DP_TXPCS_IDX) <= ch2_out_chnl_ctrl_16(0); +ch3_txpcsdprioout_phy(rfreq_sel_DP_TXPCS_IDX) <= ch3_out_chnl_ctrl_16(0); + +ch0_txpcsdprioout_phy(rauto_speed_ena_DP_TXPCS_IDX) <= ch0_out_chnl_ctrl_16(1); +ch1_txpcsdprioout_phy(rauto_speed_ena_DP_TXPCS_IDX) <= ch1_out_chnl_ctrl_16(1); +ch2_txpcsdprioout_phy(rauto_speed_ena_DP_TXPCS_IDX) <= ch2_out_chnl_ctrl_16(1); +ch3_txpcsdprioout_phy(rauto_speed_ena_DP_TXPCS_IDX) <= ch3_out_chnl_ctrl_16(1); + +ch0_txpcsdprioout_phy(rhip_ena_DP_TXPCS_IDX) <= ch0_out_chnl_ctrl_16(2); +ch1_txpcsdprioout_phy(rhip_ena_DP_TXPCS_IDX) <= ch1_out_chnl_ctrl_16(2); +ch2_txpcsdprioout_phy(rhip_ena_DP_TXPCS_IDX) <= ch2_out_chnl_ctrl_16(2); +ch3_txpcsdprioout_phy(rhip_ena_DP_TXPCS_IDX) <= ch3_out_chnl_ctrl_16(2); + +ch0_txpcsdprioout_phy(rpma_doublewidth_tx_TXPCS_IDX) <= ch0_out_chnl_ctrl_33(10); +ch1_txpcsdprioout_phy(rpma_doublewidth_tx_TXPCS_IDX) <= ch1_out_chnl_ctrl_33(10); +ch2_txpcsdprioout_phy(rpma_doublewidth_tx_TXPCS_IDX) <= ch2_out_chnl_ctrl_33(10); +ch3_txpcsdprioout_phy(rpma_doublewidth_tx_TXPCS_IDX) <= ch3_out_chnl_ctrl_33(10); + +ch0_txpcsdprioout_phy(rpmadwidth_tx_DP_TXPCS_IDX) <= ch0_out_chnl_ctrl_33(9); +ch1_txpcsdprioout_phy(rpmadwidth_tx_DP_TXPCS_IDX) <= ch1_out_chnl_ctrl_33(9); +ch2_txpcsdprioout_phy(rpmadwidth_tx_DP_TXPCS_IDX) <= ch2_out_chnl_ctrl_33(9); +ch3_txpcsdprioout_phy(rpmadwidth_tx_DP_TXPCS_IDX) <= ch3_out_chnl_ctrl_33(9); + +-- global control 1 - cetnrl_ctrl_44 +ch0_txpcsdprioout_phy(rendec_data_sel_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(7); +ch1_txpcsdprioout_phy(rendec_data_sel_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(7); +ch2_txpcsdprioout_phy(rendec_data_sel_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(7); +ch3_txpcsdprioout_phy(rendec_data_sel_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(7); + +ch0_txpcsdprioout_phy(rindv_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(1); +ch1_txpcsdprioout_phy(rindv_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(1); +ch2_txpcsdprioout_phy(rindv_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(1); +ch3_txpcsdprioout_phy(rindv_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_1(1); + +-- global control 3 - cetnrl_ctrl_46 +ch0_txpcsdprioout_phy(rmaster_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(1); +ch1_txpcsdprioout_phy(rmaster_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(1); +ch2_txpcsdprioout_phy(rmaster_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(1); +ch3_txpcsdprioout_phy(rmaster_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(1); + +ch0_txpcsdprioout_phy(rmaster_up_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(0); +ch1_txpcsdprioout_phy(rmaster_up_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(0); +ch2_txpcsdprioout_phy(rmaster_up_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(0); +ch3_txpcsdprioout_phy(rmaster_up_tx_DP_TXPCS_IDX) <= cmu_out_centrl_global_3(0); + +-- global control 2 - cetnrl_ctrl_44 to central clock divider only +ch4_cmudividerdprioout_phy(rfreerun_centrl_DP_CLOCK_DIV_IDX) <= cmu_out_centrl_global_2(15); +ch5_cmudividerdprioout_phy(rfreerun_centrl_DP_CLOCK_DIV_IDX) <= cmu_out_centrl_global_2(15); + +ch4_cmudividerdprioout_phy(rcentrl_clk_sel_DP_CLOCK_DIV_IDX) <= cmu_out_centrl_global_2(14); +ch5_cmudividerdprioout_phy(rcentrl_clk_sel_DP_CLOCK_DIV_IDX) <= cmu_out_centrl_global_2(14); + +ch4_cmudividerdprioout_phy(rrefclk_out_div2_DP_CLOCK_DIV_IDX) <= cmu_out_centrl_global_2(13); +ch5_cmudividerdprioout_phy(rrefclk_out_div2_DP_CLOCK_DIV_IDX) <= cmu_out_centrl_global_2(13); + +-- RX_PMA --------------------------------------------------------- +ch0_rxpmadprioout_phy(rs_lpbk_DP_RXPMA_IDX) <= ch0_out_chnl_ctrl_33(7); +ch1_rxpmadprioout_phy(rs_lpbk_DP_RXPMA_IDX) <= ch1_out_chnl_ctrl_33(7); +ch2_rxpmadprioout_phy(rs_lpbk_DP_RXPMA_IDX) <= ch2_out_chnl_ctrl_33(7); +ch3_rxpmadprioout_phy(rs_lpbk_DP_RXPMA_IDX) <= ch3_out_chnl_ctrl_33(7); +ch4_rxpmadprioout_phy(rs_lpbk_DP_RXPMA_IDX) <= ch4_out_chnl_ctrl_33(7); +ch5_rxpmadprioout_phy(rs_lpbk_DP_RXPMA_IDX) <= ch5_out_chnl_ctrl_33(7); + +ch0_rxpmadprioout_phy(rrevlb_sw_RXPMA_IDX) <= ch0_out_chnl_ctrl_34(10); +ch1_rxpmadprioout_phy(rrevlb_sw_RXPMA_IDX) <= ch1_out_chnl_ctrl_34(10); +ch2_rxpmadprioout_phy(rrevlb_sw_RXPMA_IDX) <= ch2_out_chnl_ctrl_34(10); +ch3_rxpmadprioout_phy(rrevlb_sw_RXPMA_IDX) <= ch3_out_chnl_ctrl_34(10); +ch4_rxpmadprioout_phy(rrevlb_sw_RXPMA_IDX) <= ch2_out_chnl_ctrl_34(10); +ch5_rxpmadprioout_phy(rrevlb_sw_RXPMA_IDX) <= ch3_out_chnl_ctrl_34(10); + +-- table40[15] = rcru_rlbk (revere_lpbk) using rs_lpbk_IDX to map to tx_pam.rtx_rlpbk RTL name +ch0_txpmadprioout_phy(rs_lpbk_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_40(15); +ch1_txpmadprioout_phy(rs_lpbk_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_40(15); +ch2_txpmadprioout_phy(rs_lpbk_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_40(15); +ch3_txpmadprioout_phy(rs_lpbk_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_40(15); +ch4_txpmadprioout_phy(rs_lpbk_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_40(15); +ch5_txpmadprioout_phy(rs_lpbk_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_40(15); + +-- table 43[0] = rloopback1 to map to tx pma +ch0_txpmadprioout_phy(rloopback1) <= ch0_out_chnl_ctrl_43(0); +ch1_txpmadprioout_phy(rloopback1) <= ch1_out_chnl_ctrl_43(0); +ch2_txpmadprioout_phy(rloopback1) <= ch2_out_chnl_ctrl_43(0); +ch3_txpmadprioout_phy(rloopback1) <= ch3_out_chnl_ctrl_43(0); +ch4_txpmadprioout_phy(rloopback1) <= ch4_out_chnl_ctrl_43(0); +ch5_txpmadprioout_phy(rloopback1) <= ch5_out_chnl_ctrl_43(0); +-- table 43[2] = rloopback1 to map to tx pma +ch0_txpmadprioout_phy(rloopback3) <= ch0_out_chnl_ctrl_43(2); +ch1_txpmadprioout_phy(rloopback3) <= ch1_out_chnl_ctrl_43(2); +ch2_txpmadprioout_phy(rloopback3) <= ch2_out_chnl_ctrl_43(2); +ch3_txpmadprioout_phy(rloopback3) <= ch3_out_chnl_ctrl_43(2); +ch4_txpmadprioout_phy(rloopback3) <= ch4_out_chnl_ctrl_43(2); +ch5_txpmadprioout_phy(rloopback3) <= ch5_out_chnl_ctrl_43(2); +-- CMUDivider ------------------------------------------------------------------ +-- Table33: PMA Per Channel TX Control Register 6 for Channel 0 +-- Table33 is split between clock divider and TX_PMA + +-- TX_PMA portion of dprio - does not hurt to receive clock divider cram +-- - already implemented in the same section as other TX_PMA ctrl + +-- Output - CMU Clock Divider Portion +ch0_cmudividerdprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(6); +ch1_cmudividerdprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33(6); +ch2_cmudividerdprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33(6); +ch3_cmudividerdprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33(6); +ch4_cmudividerdprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33(6); +ch5_cmudividerdprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33(6); + +--Output - TX PMA +ch0_txpmadprioout_phy(rpmadwidth_tx_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(9); +ch1_txpmadprioout_phy(rpmadwidth_tx_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33(9); +ch2_txpmadprioout_phy(rpmadwidth_tx_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33(9); +ch3_txpmadprioout_phy(rpmadwidth_tx_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33(9); +ch4_txpmadprioout_phy(rpmadwidth_tx_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33(9); +ch5_txpmadprioout_phy(rpmadwidth_tx_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33(9); + +ch0_cmudividerdprioout_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(10); +ch1_cmudividerdprioout_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33(10); +ch2_cmudividerdprioout_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33(10); +ch3_cmudividerdprioout_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33(10); +ch4_cmudividerdprioout_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33(10); +ch5_cmudividerdprioout_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33(10); + +ch0_cmudividerdprioout_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(12 DOWNTO 11); +ch1_cmudividerdprioout_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33(12 DOWNTO 11); +ch2_cmudividerdprioout_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33(12 DOWNTO 11); +ch3_cmudividerdprioout_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33(12 DOWNTO 11); +ch4_cmudividerdprioout_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33(12 DOWNTO 11); +ch5_cmudividerdprioout_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33(12 DOWNTO 11); + +ch0_cmudividerdprioout_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(13); +ch1_cmudividerdprioout_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33(13); +ch2_cmudividerdprioout_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33(13); +ch3_cmudividerdprioout_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33(13); +ch4_cmudividerdprioout_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33(13); +ch5_cmudividerdprioout_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33(13); + +-- TX_PMA portion +-- bit(7) goes to rx_pma +ch0_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_delay_sel_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(15 DOWNTO 8); +ch1_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_delay_sel_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33(15 DOWNTO 8); +ch2_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_delay_sel_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33(15 DOWNTO 8); +ch3_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_delay_sel_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33(15 DOWNTO 8); +ch4_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_delay_sel_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33(15 DOWNTO 8); +ch5_txpmadprioout_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_delay_sel_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33(15 DOWNTO 8); +-- this bit is from table_40 (rx_pma) bit(15) +-- ch0_txpmadprioout_phy(rs_lpbk_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(7); +ch0_txpmadprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch0_out_chnl_ctrl_33(6 DOWNTO 0); +ch1_txpmadprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch1_out_chnl_ctrl_33(6 DOWNTO 0); +ch2_txpmadprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch2_out_chnl_ctrl_33(6 DOWNTO 0); +ch3_txpmadprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch3_out_chnl_ctrl_33(6 DOWNTO 0); +ch4_txpmadprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch4_out_chnl_ctrl_33(6 DOWNTO 0); +ch5_txpmadprioout_phy(rdynamic_sw_DP_TXPMA_IDX_0 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0) <= ch5_out_chnl_ctrl_33(6 DOWNTO 0); + +-- PLL portion - rx_cdr needs dynamic_sw for gating +-- For x4 gen2: there is no channel clock divider so one has to use centrl_clk_div (to get init_) +-- For HIP genx1: centrl clk div sets enable_dynamic_divider = true and tied rate=1 (293245) - incompatible with rx_pll +-- using centrl clk_div data in x4 and chl_div in x1 - here cmu_out_centrl_global[0] = rx[0].rindv_rx +ch0_rxplldprioout_phy(rdynamic_sw_DP_PLL_IDX_0) <= ch4_out_chnl_ctrl_33(6) WHEN (cmu_out_centrl_global_1(0) = '0') ELSE ch0_out_chnl_ctrl_33(6); +ch1_rxplldprioout_phy(rdynamic_sw_DP_PLL_IDX_0) <= ch4_out_chnl_ctrl_33(6) WHEN (cmu_out_centrl_global_1(0) = '0') ELSE ch1_out_chnl_ctrl_33(6); +ch2_rxplldprioout_phy(rdynamic_sw_DP_PLL_IDX_0) <= ch4_out_chnl_ctrl_33(6) WHEN (cmu_out_centrl_global_1(0) = '0') ELSE ch2_out_chnl_ctrl_33(6); +ch3_rxplldprioout_phy(rdynamic_sw_DP_PLL_IDX_0) <= ch4_out_chnl_ctrl_33(6) WHEN (cmu_out_centrl_global_1(0) = '0') ELSE ch3_out_chnl_ctrl_33(6); + +-- not needed below if we do not switch rx_cdr_pll into txpll +ch4_rxtxplldprioout_phy(rdynamic_sw_DP_PLL_IDX_0) <= ch4_out_chnl_ctrl_33(6); +ch5_rxtxplldprioout_phy(rdynamic_sw_DP_PLL_IDX_0) <= ch5_out_chnl_ctrl_33(6); + +-- Input portion of CLOCK_DIVIDER in table 33 +ch0_in_chnl_ctrl_33(6) <= ch0_cmudividerdprioin_phy(rdynamic_sw_DP_TXPMA_IDX_0) ; +ch1_in_chnl_ctrl_33(6) <= ch1_cmudividerdprioin_phy(rdynamic_sw_DP_TXPMA_IDX_0) ; +ch2_in_chnl_ctrl_33(6) <= ch2_cmudividerdprioin_phy(rdynamic_sw_DP_TXPMA_IDX_0) ; +ch3_in_chnl_ctrl_33(6) <= ch3_cmudividerdprioin_phy(rdynamic_sw_DP_TXPMA_IDX_0) ; +ch4_in_chnl_ctrl_33(6) <= ch4_cmudividerdprioin_phy(rdynamic_sw_DP_TXPMA_IDX_0) ; +ch5_in_chnl_ctrl_33(6) <= ch5_cmudividerdprioin_phy(rdynamic_sw_DP_TXPMA_IDX_0) ; +ch0_in_chnl_ctrl_33(12 DOWNTO 11) <= ch0_cmudividerdprioin_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) ; +ch1_in_chnl_ctrl_33(12 DOWNTO 11) <= ch1_cmudividerdprioin_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) ; +ch2_in_chnl_ctrl_33(12 DOWNTO 11) <= ch2_cmudividerdprioin_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) ; +ch3_in_chnl_ctrl_33(12 DOWNTO 11) <= ch3_cmudividerdprioin_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) ; +ch4_in_chnl_ctrl_33(12 DOWNTO 11) <= ch4_cmudividerdprioin_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) ; +ch5_in_chnl_ctrl_33(12 DOWNTO 11) <= ch5_cmudividerdprioin_phy(rcgb_m_sel_DP_TXPMA_IDX_1 DOWNTO rcgb_m_sel_DP_TXPMA_IDX_0) ; +-- Handled in inclk_select manual section of clock_div +--ch0_in_chnl_ctrl_33(13) <= ch0_cmudividerdprioin_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) ; +--ch1_in_chnl_ctrl_33(13) <= ch1_cmudividerdprioin_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) ; +--ch2_in_chnl_ctrl_33(13) <= ch2_cmudividerdprioin_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) ; +--ch3_in_chnl_ctrl_33(13) <= ch3_cmudividerdprioin_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) ; +--ch4_in_chnl_ctrl_33(13) <= ch4_cmudividerdprioin_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) ; +--ch5_in_chnl_ctrl_33(13) <= ch5_cmudividerdprioin_phy(rcgb_cmu_sel_DP_TXPMA_IDX_0) ; + +-- Input DOWNTO portion of TX_PMA in table 33 +ch0_in_chnl_ctrl_33(3 DOWNTO 0) <= ch0_txpmadprioin_phy(reserved_0_TB33_DP_TXPMA_IDX_3 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +ch1_in_chnl_ctrl_33(3 DOWNTO 0) <= ch1_txpmadprioin_phy(reserved_0_TB33_DP_TXPMA_IDX_3 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +ch2_in_chnl_ctrl_33(3 DOWNTO 0) <= ch2_txpmadprioin_phy(reserved_0_TB33_DP_TXPMA_IDX_3 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +ch3_in_chnl_ctrl_33(3 DOWNTO 0) <= ch3_txpmadprioin_phy(reserved_0_TB33_DP_TXPMA_IDX_3 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +ch4_in_chnl_ctrl_33(3 DOWNTO 0) <= ch4_txpmadprioin_phy(reserved_0_TB33_DP_TXPMA_IDX_3 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +ch5_in_chnl_ctrl_33(3 DOWNTO 0) <= ch5_txpmadprioin_phy(reserved_0_TB33_DP_TXPMA_IDX_3 DOWNTO reserved_0_TB33_DP_TXPMA_IDX_0); +ch0_in_chnl_ctrl_33(4) <= ch0_txpmadprioin_phy(rtx_cgb_pdb_DP_TXPMA_IDX_0); +ch1_in_chnl_ctrl_33(4) <= ch1_txpmadprioin_phy(rtx_cgb_pdb_DP_TXPMA_IDX_0); +ch2_in_chnl_ctrl_33(4) <= ch2_txpmadprioin_phy(rtx_cgb_pdb_DP_TXPMA_IDX_0); +ch3_in_chnl_ctrl_33(4) <= ch3_txpmadprioin_phy(rtx_cgb_pdb_DP_TXPMA_IDX_0); +ch4_in_chnl_ctrl_33(4) <= ch4_txpmadprioin_phy(rtx_cgb_pdb_DP_TXPMA_IDX_0); +ch5_in_chnl_ctrl_33(4) <= ch5_txpmadprioin_phy(rtx_cgb_pdb_DP_TXPMA_IDX_0); +ch0_in_chnl_ctrl_33(5) <= ch0_txpmadprioin_phy(rpclksel_DP_TXPMA_IDX_0); +ch1_in_chnl_ctrl_33(5) <= ch1_txpmadprioin_phy(rpclksel_DP_TXPMA_IDX_0); +ch2_in_chnl_ctrl_33(5) <= ch2_txpmadprioin_phy(rpclksel_DP_TXPMA_IDX_0); +ch3_in_chnl_ctrl_33(5) <= ch3_txpmadprioin_phy(rpclksel_DP_TXPMA_IDX_0); +ch4_in_chnl_ctrl_33(5) <= ch4_txpmadprioin_phy(rpclksel_DP_TXPMA_IDX_0); +ch5_in_chnl_ctrl_33(5) <= ch5_txpmadprioin_phy(rpclksel_DP_TXPMA_IDX_0); + +-- clock divide(6) + +-- allow_serial_loopback mapped into rx_pma.RRX_S_LPBK_RXPMA_IDX - ICD XLS cram doc error +ch0_in_chnl_ctrl_33(7) <= ch0_rxpmadprioin_phy(rs_lpbk_DP_RXPMA_IDX); +ch1_in_chnl_ctrl_33(7) <= ch1_rxpmadprioin_phy(rs_lpbk_DP_RXPMA_IDX); +ch2_in_chnl_ctrl_33(7) <= ch2_rxpmadprioin_phy(rs_lpbk_DP_RXPMA_IDX); +ch3_in_chnl_ctrl_33(7) <= ch3_rxpmadprioin_phy(rs_lpbk_DP_RXPMA_IDX); +ch4_in_chnl_ctrl_33(7) <= ch4_rxpmadprioin_phy(rs_lpbk_DP_RXPMA_IDX); +ch5_in_chnl_ctrl_33(7) <= ch5_rxpmadprioin_phy(rs_lpbk_DP_RXPMA_IDX); + +ch0_in_chnl_ctrl_33(8) <= ch0_txpmadprioin_phy(rcgb_delay_sel_DP_TXPMA_IDX_0); +ch1_in_chnl_ctrl_33(8) <= ch1_txpmadprioin_phy(rcgb_delay_sel_DP_TXPMA_IDX_0); +ch2_in_chnl_ctrl_33(8) <= ch2_txpmadprioin_phy(rcgb_delay_sel_DP_TXPMA_IDX_0); +ch3_in_chnl_ctrl_33(8) <= ch3_txpmadprioin_phy(rcgb_delay_sel_DP_TXPMA_IDX_0); +ch4_in_chnl_ctrl_33(8) <= ch4_txpmadprioin_phy(rcgb_delay_sel_DP_TXPMA_IDX_0); +ch5_in_chnl_ctrl_33(8) <= ch5_txpmadprioin_phy(rcgb_delay_sel_DP_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_33(9) <= ch0_txpmadprioin_phy(rpmadwidth_tx_DP_TXPMA_IDX_0); +ch1_in_chnl_ctrl_33(9) <= ch1_txpmadprioin_phy(rpmadwidth_tx_DP_TXPMA_IDX_0); +ch2_in_chnl_ctrl_33(9) <= ch2_txpmadprioin_phy(rpmadwidth_tx_DP_TXPMA_IDX_0); +ch3_in_chnl_ctrl_33(9) <= ch3_txpmadprioin_phy(rpmadwidth_tx_DP_TXPMA_IDX_0); +-- spr 317392 - when clock divider is used as global (x4) but corresponding tx_pma not available +-- ch4, 5 <--> with corresponding CMU_CTRL registers (in this case table 59) +ch4_in_chnl_ctrl_33(9) <= ch4_cmudividerdprioin_phy(rpmadwidth_tx_DP_TXPMA_IDX_0); +ch5_in_chnl_ctrl_33(9) <= ch5_cmudividerdprioin_phy(rpmadwidth_tx_DP_TXPMA_IDX_0); + +ch0_in_chnl_ctrl_33(10) <= ch0_txpmadprioin_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0); +ch1_in_chnl_ctrl_33(10) <= ch1_txpmadprioin_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0); +ch2_in_chnl_ctrl_33(10) <= ch2_txpmadprioin_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0); +ch3_in_chnl_ctrl_33(10) <= ch3_txpmadprioin_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0); +-- same as rpmadwidth +ch4_in_chnl_ctrl_33(10) <= ch4_cmudividerdprioin_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0); +ch5_in_chnl_ctrl_33(10) <= ch5_cmudividerdprioin_phy(rpma_doublewidth_tx_DP_TXPMA_IDX_0); +-- clock_divider(12 DOWNTO 11) +-- clock_divider(13) +-- Handled in clkin_select manual section next +--ch0_in_chnl_ctrl_33(15 DOWNTO 14) <= ch0_txpmadprioin_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_x_en_DP_TXPMA_IDX_0); +--ch1_in_chnl_ctrl_33(15 DOWNTO 14) <= ch1_txpmadprioin_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_x_en_DP_TXPMA_IDX_0); +--ch2_in_chnl_ctrl_33(15 DOWNTO 14) <= ch2_txpmadprioin_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_x_en_DP_TXPMA_IDX_0); +--ch3_in_chnl_ctrl_33(15 DOWNTO 14) <= ch3_txpmadprioin_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_x_en_DP_TXPMA_IDX_0); +--ch4_in_chnl_ctrl_33(15 DOWNTO 14) <= ch4_txpmadprioin_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_x_en_DP_TXPMA_IDX_0); +--ch5_in_chnl_ctrl_33(15 DOWNTO 14) <= ch5_txpmadprioin_phy(rcgb_x_en_DP_TXPMA_IDX_1 DOWNTO rcgb_x_en_DP_TXPMA_IDX_0); + +-- Table 40: +-- bit(15) goes to TX_PMA - moved to Manual section as this CRAM sends to TX_PMA + +-- table40(15) <= rcru_rlbk (revere_lpbk) using rs_lpbk_DP_IDX to map to tx_pam.rtx_rlpbk RTL name +-- cstan +--ch0_in_chnl_ctrl_40(15) <= ch0_txpmadprioin_phy(rs_lpbk_DP_TXPMA_IDX_0); +--ch1_in_chnl_ctrl_40(15) <= ch1_txpmadprioin_phy(rs_lpbk_DP_TXPMA_IDX_0); +--ch2_in_chnl_ctrl_40(15) <= ch2_txpmadprioin_phy(rs_lpbk_DP_TXPMA_IDX_0); +--ch3_in_chnl_ctrl_40(15) <= ch3_txpmadprioin_phy(rs_lpbk_DP_TXPMA_IDX_0); +--ch4_in_chnl_ctrl_40(15) <= ch4_txpmadprioin_phy(rs_lpbk_DP_TXPMA_IDX_0); +--ch5_in_chnl_ctrl_40(15) <= ch5_txpmadprioin_phy(rs_lpbk_DP_TXPMA_IDX_0); + +-- rest bits from RX_PLL +--ch0_in_chnl_ctrl_40(14 DOWNTO 0) <= ch0_rxplldprioin_phy(rcru_lst_DP_PLL_IDX_3 DOWNTO reserved_0_TB40_DP_PLL_IDX_0); +--ch1_in_chnl_ctrl_40(14 DOWNTO 0) <= ch1_rxplldprioin_phy(rcru_lst_DP_PLL_IDX_3 DOWNTO reserved_0_TB40_DP_PLL_IDX_0); +--ch2_in_chnl_ctrl_40(14 DOWNTO 0) <= ch2_rxplldprioin_phy(rcru_lst_DP_PLL_IDX_3 DOWNTO reserved_0_TB40_DP_PLL_IDX_0); +--ch3_in_chnl_ctrl_40(14 DOWNTO 0) <= ch3_rxplldprioin_phy(rcru_lst_DP_PLL_IDX_3 DOWNTO reserved_0_TB40_DP_PLL_IDX_0); +--ch4_in_chnl_ctrl_40(14 DOWNTO 0) <= ch4_rxtxplldprioin_phy(rcru_lst_DP_PLL_IDX_3 DOWNTO reserved_0_TB40_DP_PLL_IDX_0); +--ch5_in_chnl_ctrl_40(14 DOWNTO 0) <= ch5_rxtxplldprioin_phy(rcru_lst_DP_PLL_IDX_3 DOWNTO reserved_0_TB40_DP_PLL_IDX_0); + +-- ---------------------------------------------------------------------------------------------------------------- +-- Manual section - inputs: only ch0 --> global CRAMs +-- ---------------------------------------------------------------------------------------------------------------- + +-- Extra word in CMU (no correspondence in channel) - not modeled in MIF and SIM +cmu0_in_centrl_ctrl_21 <= "0000000000000000"; +cmu1_in_centrl_ctrl_21 <= "0000000000000000"; + +-- global ctrl 0 - centrl_ctrl_43 - table 75 +cmu_in_centrl_global_0 <= "0000000000000000"; + +-- global ctrl 1 - centrl_ctrl_44 +cmu_in_centrl_global_1(15 DOWNTO 8) <= "00000000"; +cmu_in_centrl_global_1(7) <= ch0_txpcsdprioin_phy(rendec_data_sel_tx_DP_TXPCS_IDX); +cmu_in_centrl_global_1(6) <= ch0_rxpcsdprioin_phy(rendec_data_sel_rx_DP_RXPCS_IDX); +cmu_in_centrl_global_1(5 DOWNTO 3) <= "000"; +cmu_in_centrl_global_1(2) <= ch0_rxpcsdprioin_phy(rdeskewen_DP_RXPCS_IDX); +cmu_in_centrl_global_1(1) <= ch0_txpcsdprioin_phy(rindv_tx_DP_TXPCS_IDX); +cmu_in_centrl_global_1(0) <= ch0_rxpcsdprioin_phy(rindv_rx_DP_RXPCS_IDX); + +-- global ctrl 2 - centrl_ctrl_45 +cmu_in_centrl_global_2(15) <= ch4_cmudividerdprioin_phy(rfreerun_centrl_DP_CLOCK_DIV_IDX); +cmu_in_centrl_global_2(14) <= ch4_cmudividerdprioin_phy(rcentrl_clk_sel_DP_CLOCK_DIV_IDX); +cmu_in_centrl_global_2(13) <= ch4_cmudividerdprioin_phy(rrefclk_out_div2_DP_CLOCK_DIV_IDX); + +cmu_in_centrl_global_2(12 DOWNTO 11) <= "00"; +cmu_in_centrl_global_2(10) <= ch0_rxpcsdprioin_phy(rdskposdisp_DP_RXPCS_IDX); +cmu_in_centrl_global_2(9 DOWNTO 0) <= "0000000000"; + +-- global ctrl 3 - centrl_ctrl_46 +cmu_in_centrl_global_3(15 DOWNTO 4) <= "000000000000"; +cmu_in_centrl_global_3(3) <= ch0_rxpcsdprioin_phy(rmaster_rx_DP_RXPCS_IDX); +cmu_in_centrl_global_3(2) <= ch0_rxpcsdprioin_phy(rmaster_up_rx_DP_RXPCS_IDX); +cmu_in_centrl_global_3(1) <= ch0_txpcsdprioin_phy(rmaster_tx_DP_TXPCS_IDX); +cmu_in_centrl_global_3(0) <= ch0_txpcsdprioin_phy(rmaster_up_tx_DP_TXPCS_IDX); + +--==================================================================== +-- Manually added code to handle PLL clock select = +--==================================================================== + +-- Table 34 - pll's pfd_clk_select ----------------------------------- + +-- preparing inputs to index_cram_map +pll0_init_pfd_clk_sel <= ch0_rxplldprioin_logic(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0); +pll0_dp_riqclk_sel <= ch0_out_chnl_ctrl_34(15 DOWNTO 14); +pll0_dp_rrefclk_sel <= ch0_out_chnl_ctrl_34(13 DOWNTO 12); + +-- using outputs from index_cram_map +ch0_rxplldprioout_phy(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0) <= pll0_dp_pfd_clk_sel; + +-- preparing inputs to index_cram_map +pll1_init_pfd_clk_sel <= ch1_rxplldprioin_logic(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0); +pll1_dp_riqclk_sel <= ch1_out_chnl_ctrl_34(15 DOWNTO 14); +pll1_dp_rrefclk_sel <= ch1_out_chnl_ctrl_34(13 DOWNTO 12); + +-- using outputs from index_cram_map +ch1_rxplldprioout_phy(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0) <= pll1_dp_pfd_clk_sel; +ch1_in_chnl_ctrl_34(15 DOWNTO 14) <= pll1_csr_riqclk_sel; +ch1_in_chnl_ctrl_34(13 DOWNTO 12) <= pll1_csr_rrefclk_sel; + +-- preparing inputs to index_cram_map +pll2_init_pfd_clk_sel <= ch2_rxplldprioin_logic(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0); +pll2_dp_riqclk_sel <= ch2_out_chnl_ctrl_34(15 DOWNTO 14); +pll2_dp_rrefclk_sel <= ch2_out_chnl_ctrl_34(13 DOWNTO 12); + +-- using outputs from index_cram_map +ch2_rxplldprioout_phy(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0) <= pll2_dp_pfd_clk_sel; +ch2_in_chnl_ctrl_34(15 DOWNTO 14) <= pll2_csr_riqclk_sel; +ch2_in_chnl_ctrl_34(13 DOWNTO 12) <= pll2_csr_rrefclk_sel; + +-- preparing inputs to index_cram_map +pll3_init_pfd_clk_sel <= ch3_rxplldprioin_logic(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0); +pll3_dp_riqclk_sel <= ch3_out_chnl_ctrl_34(15 DOWNTO 14); +pll3_dp_rrefclk_sel <= ch3_out_chnl_ctrl_34(13 DOWNTO 12); + +-- using outputs from index_cram_map +ch3_rxplldprioout_phy(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0) <= pll3_dp_pfd_clk_sel; +ch3_in_chnl_ctrl_34(15 DOWNTO 14) <= pll3_csr_riqclk_sel; +ch3_in_chnl_ctrl_34(13 DOWNTO 12) <= pll3_csr_rrefclk_sel; + +-- preparing inputs to index_cram_map +pll4_init_pfd_clk_sel <= ch4_rxtxplldprioin_logic(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0); +pll4_dp_riqclk_sel <= ch4_out_chnl_ctrl_34(15 DOWNTO 14); +pll4_dp_rrefclk_sel <= ch4_out_chnl_ctrl_34(13 DOWNTO 12); + +-- using outputs from index_cram_map +ch4_rxtxplldprioout_phy(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0) <= pll4_dp_pfd_clk_sel; +ch4_in_chnl_ctrl_34(15 DOWNTO 14) <= pll4_csr_riqclk_sel; +ch4_in_chnl_ctrl_34(13 DOWNTO 12) <= pll4_csr_rrefclk_sel; + +-- preparing inputs to index_cram_map +pll5_init_pfd_clk_sel <= ch5_rxtxplldprioin_logic(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0); +pll5_dp_riqclk_sel <= ch5_out_chnl_ctrl_34(15 DOWNTO 14); +pll5_dp_rrefclk_sel <= ch5_out_chnl_ctrl_34(13 DOWNTO 12); + +-- using outputs from index_cram_map +ch5_rxtxplldprioout_phy(PFD_CLK_SELECT_DP_PLL_IDX_3 DOWNTO PFD_CLK_SELECT_DP_PLL_IDX_0) <= pll5_dp_pfd_clk_sel; +ch5_in_chnl_ctrl_34(15 DOWNTO 14) <= pll5_csr_riqclk_sel; +ch5_in_chnl_ctrl_34(13 DOWNTO 12) <= pll5_csr_rrefclk_sel; + +--==================================================================== +-- Manually added code to handle TX PMA clock select = +--==================================================================== + +-- Table 33 - TX PMA's clkin_select --------------------------------- + +-- preparing inputs to index_cram_map +txpma0_init_clkin_sel <= ch0_txpmadprioin_logic(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0); +txpma0_dp_rcgb_x_en <= ch0_out_chnl_ctrl_33(15 DOWNTO 14); + +-- using outputs from index_cram_map +ch0_txpmadprioout_phy(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0) <= txpma0_dp_clkin_sel; +ch0_in_chnl_ctrl_33(15 DOWNTO 14) <= txpma0_csr_rcgb_x_en; + +-- preparing inputs to index_cram_map +txpma1_init_clkin_sel <= ch1_txpmadprioin_logic(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0); +txpma1_dp_rcgb_x_en <= ch1_out_chnl_ctrl_33(15 DOWNTO 14); + +-- using outputs from index_cram_map +ch1_txpmadprioout_phy(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0) <= txpma1_dp_clkin_sel; +ch1_in_chnl_ctrl_33(15 DOWNTO 14) <= txpma1_csr_rcgb_x_en; + +-- preparing inputs to index_cram_map +txpma2_init_clkin_sel <= ch2_txpmadprioin_logic(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0); +txpma2_dp_rcgb_x_en <= ch2_out_chnl_ctrl_33(15 DOWNTO 14); + +-- using outputs from index_cram_map +ch2_txpmadprioout_phy(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0) <= txpma2_dp_clkin_sel; +ch2_in_chnl_ctrl_33(15 DOWNTO 14) <= txpma2_csr_rcgb_x_en; + +-- preparing inputs to index_cram_map +txpma3_init_clkin_sel <= ch3_txpmadprioin_logic(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0); +txpma3_dp_rcgb_x_en <= ch3_out_chnl_ctrl_33(15 DOWNTO 14); + +-- using outputs from index_cram_map +ch3_txpmadprioout_phy(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0) <= txpma3_dp_clkin_sel; +ch3_in_chnl_ctrl_33(15 DOWNTO 14) <= txpma3_csr_rcgb_x_en; + +-- preparing inputs to index_cram_map +txpma4_init_clkin_sel <= ch4_txpmadprioin_logic(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0); +txpma4_dp_rcgb_x_en <= ch4_out_chnl_ctrl_33(15 DOWNTO 14); + +-- using outputs from index_cram_map +ch4_txpmadprioout_phy(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0) <= txpma4_dp_clkin_sel; +ch4_in_chnl_ctrl_33(15 DOWNTO 14) <= txpma4_csr_rcgb_x_en; + +-- preparing inputs to index_cram_map +txpma5_init_clkin_sel <= ch5_txpmadprioin_logic(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0); +txpma5_dp_rcgb_x_en <= ch5_out_chnl_ctrl_33(15 DOWNTO 14); + +-- using outputs from index_cram_map +ch5_txpmadprioout_phy(CLKIN_SELECT_DP_TXPMA_IDX_2 DOWNTO CLKIN_SELECT_DP_TXPMA_IDX_0) <= txpma5_dp_clkin_sel; +ch5_in_chnl_ctrl_33(15 DOWNTO 14) <= txpma5_csr_rcgb_x_en; + +--==================================================================== +-- Manually added code to handle clkdiv PLL0/1 select = +--==================================================================== + +-- Table 33 - clock divider's inclk_select -------------------------- + +-- preparing inputs to index_cram_map +clkdiv0_init_inclk_select <= ch0_cmudividerdprioin_logic(INCLK_SELECT_DP_CLOCK_DIV_IDX); +clkdiv0_dp_rcgb_cmu_sel <= ch0_out_chnl_ctrl_33(13); + +-- using outputs from index_cram_map +ch0_cmudividerdprioout_phy(INCLK_SELECT_DP_CLOCK_DIV_IDX) <= clkdiv0_dp_inclk_select; +ch0_in_chnl_ctrl_33(13) <= clkdiv0_csr_rcgb_cmu_sel; + +-- preparing inputs to index_cram_map +clkdiv1_init_inclk_select <= ch1_cmudividerdprioin_logic(INCLK_SELECT_DP_CLOCK_DIV_IDX); +clkdiv1_dp_rcgb_cmu_sel <= ch1_out_chnl_ctrl_33(13); + +-- using outputs from index_cram_map +ch1_cmudividerdprioout_phy(INCLK_SELECT_DP_CLOCK_DIV_IDX) <= clkdiv1_dp_inclk_select; +ch1_in_chnl_ctrl_33(13) <= clkdiv1_csr_rcgb_cmu_sel; + +-- preparing inputs to index_cram_map +clkdiv2_init_inclk_select <= ch2_cmudividerdprioin_logic(INCLK_SELECT_DP_CLOCK_DIV_IDX); +clkdiv2_dp_rcgb_cmu_sel <= ch2_out_chnl_ctrl_33(13); + +-- using outputs from index_cram_map +ch2_cmudividerdprioout_phy(INCLK_SELECT_DP_CLOCK_DIV_IDX) <= clkdiv2_dp_inclk_select; +ch2_in_chnl_ctrl_33(13) <= clkdiv2_csr_rcgb_cmu_sel; + +-- preparing inputs to index_cram_map +clkdiv3_init_inclk_select <= ch3_cmudividerdprioin_logic(INCLK_SELECT_DP_CLOCK_DIV_IDX); +clkdiv3_dp_rcgb_cmu_sel <= ch3_out_chnl_ctrl_33(13); + +-- using outputs from index_cram_map +ch3_cmudividerdprioout_phy(INCLK_SELECT_DP_CLOCK_DIV_IDX) <= clkdiv3_dp_inclk_select; +ch3_in_chnl_ctrl_33(13) <= clkdiv3_csr_rcgb_cmu_sel; + +-- preparing inputs to index_cram_map +clkdiv4_init_inclk_select <= ch4_cmudividerdprioin_logic(INCLK_SELECT_DP_CLOCK_DIV_IDX); +clkdiv4_dp_rcgb_cmu_sel <= ch4_out_chnl_ctrl_33(13); + +-- using outputs from index_cram_map +ch4_cmudividerdprioout_phy(INCLK_SELECT_DP_CLOCK_DIV_IDX) <= clkdiv4_dp_inclk_select; +ch4_in_chnl_ctrl_33(13) <= clkdiv4_csr_rcgb_cmu_sel; + +-- preparing inputs to index_cram_map +clkdiv5_init_inclk_select <= ch5_cmudividerdprioin_logic(INCLK_SELECT_DP_CLOCK_DIV_IDX); +clkdiv5_dp_rcgb_cmu_sel <= ch5_out_chnl_ctrl_33(13); + +-- using outputs from index_cram_map +ch5_cmudividerdprioout_phy(INCLK_SELECT_DP_CLOCK_DIV_IDX) <= clkdiv5_dp_inclk_select; +ch5_in_chnl_ctrl_33(13) <= clkdiv5_csr_rcgb_cmu_sel; + +--==================================================================== +-- Instantiating the map resolver = +--==================================================================== + +m_clksel_index_cram_map : cycloneiv_hssi_cmu_dprio_map_index + GENERIC MAP ( + rx0_logical_to_physical_mapping => rx0_logical_to_physical_mapping, + rx1_logical_to_physical_mapping => rx1_logical_to_physical_mapping, + rx2_logical_to_physical_mapping => rx2_logical_to_physical_mapping, + rx3_logical_to_physical_mapping => rx3_logical_to_physical_mapping, + rx4_logical_to_physical_mapping => 0, + rx5_logical_to_physical_mapping => 0, + tx0_logical_to_physical_mapping => tx0_logical_to_physical_mapping, + tx1_logical_to_physical_mapping => tx1_logical_to_physical_mapping, + tx2_logical_to_physical_mapping => tx2_logical_to_physical_mapping, + tx3_logical_to_physical_mapping => tx3_logical_to_physical_mapping, + tx4_logical_to_physical_mapping => 0, + tx5_logical_to_physical_mapping => 0, + tx0_pma_inclk0_logical_to_physical_mapping => tx0_pma_inclk0_logical_to_physical_mapping, + tx0_pma_inclk1_logical_to_physical_mapping => tx0_pma_inclk1_logical_to_physical_mapping, + tx0_pma_inclk2_logical_to_physical_mapping => tx0_pma_inclk2_logical_to_physical_mapping, + tx0_pma_inclk3_logical_to_physical_mapping => tx0_pma_inclk3_logical_to_physical_mapping, + tx0_pma_inclk4_logical_to_physical_mapping => tx0_pma_inclk4_logical_to_physical_mapping, + tx1_pma_inclk0_logical_to_physical_mapping => tx1_pma_inclk0_logical_to_physical_mapping, + tx1_pma_inclk1_logical_to_physical_mapping => tx1_pma_inclk1_logical_to_physical_mapping, + tx1_pma_inclk2_logical_to_physical_mapping => tx1_pma_inclk2_logical_to_physical_mapping, + tx1_pma_inclk3_logical_to_physical_mapping => tx1_pma_inclk3_logical_to_physical_mapping, + tx1_pma_inclk4_logical_to_physical_mapping => tx1_pma_inclk4_logical_to_physical_mapping, + tx2_pma_inclk0_logical_to_physical_mapping => tx2_pma_inclk0_logical_to_physical_mapping, + tx2_pma_inclk1_logical_to_physical_mapping => tx2_pma_inclk1_logical_to_physical_mapping, + tx2_pma_inclk2_logical_to_physical_mapping => tx2_pma_inclk2_logical_to_physical_mapping, + tx2_pma_inclk3_logical_to_physical_mapping => tx2_pma_inclk3_logical_to_physical_mapping, + tx2_pma_inclk4_logical_to_physical_mapping => tx2_pma_inclk4_logical_to_physical_mapping, + tx3_pma_inclk0_logical_to_physical_mapping => tx3_pma_inclk0_logical_to_physical_mapping, + tx3_pma_inclk1_logical_to_physical_mapping => tx3_pma_inclk1_logical_to_physical_mapping, + tx3_pma_inclk2_logical_to_physical_mapping => tx3_pma_inclk2_logical_to_physical_mapping, + tx3_pma_inclk3_logical_to_physical_mapping => tx3_pma_inclk3_logical_to_physical_mapping, + tx3_pma_inclk4_logical_to_physical_mapping => tx3_pma_inclk4_logical_to_physical_mapping, + tx4_pma_inclk0_logical_to_physical_mapping => tx4_pma_inclk0_logical_to_physical_mapping, + tx4_pma_inclk1_logical_to_physical_mapping => tx4_pma_inclk1_logical_to_physical_mapping, + tx4_pma_inclk2_logical_to_physical_mapping => tx4_pma_inclk2_logical_to_physical_mapping, + tx4_pma_inclk3_logical_to_physical_mapping => tx4_pma_inclk3_logical_to_physical_mapping, + tx4_pma_inclk4_logical_to_physical_mapping => tx4_pma_inclk4_logical_to_physical_mapping, + tx5_pma_inclk0_logical_to_physical_mapping => tx5_pma_inclk0_logical_to_physical_mapping, + tx5_pma_inclk1_logical_to_physical_mapping => tx5_pma_inclk1_logical_to_physical_mapping, + tx5_pma_inclk2_logical_to_physical_mapping => tx5_pma_inclk2_logical_to_physical_mapping, + tx5_pma_inclk3_logical_to_physical_mapping => tx5_pma_inclk3_logical_to_physical_mapping, + tx5_pma_inclk4_logical_to_physical_mapping => tx5_pma_inclk4_logical_to_physical_mapping + ) + PORT MAP ( + pll0_init_pfd_clk_sel => pll0_init_pfd_clk_sel, -- input + pll0_csr_riqclk_sel => pll0_csr_riqclk_sel, + pll0_csr_rrefclk_sel => pll0_csr_rrefclk_sel, + pll0_dp_riqclk_sel => pll0_dp_riqclk_sel, -- input + pll0_dp_rrefclk_sel => pll0_dp_rrefclk_sel, -- input + pll0_dp_pfd_clk_sel => pll0_dp_pfd_clk_sel, + pll1_init_pfd_clk_sel => pll1_init_pfd_clk_sel, -- input + pll1_csr_riqclk_sel => pll1_csr_riqclk_sel, + pll1_csr_rrefclk_sel => pll1_csr_rrefclk_sel, + pll1_dp_riqclk_sel => pll1_dp_riqclk_sel, -- input + pll1_dp_rrefclk_sel => pll1_dp_rrefclk_sel, -- input + pll1_dp_pfd_clk_sel => pll1_dp_pfd_clk_sel, + pll2_init_pfd_clk_sel => pll2_init_pfd_clk_sel, -- input + pll2_csr_riqclk_sel => pll2_csr_riqclk_sel, + pll2_csr_rrefclk_sel => pll2_csr_rrefclk_sel, + pll2_dp_riqclk_sel => pll2_dp_riqclk_sel, -- input + pll2_dp_rrefclk_sel => pll2_dp_rrefclk_sel, -- input + pll2_dp_pfd_clk_sel => pll2_dp_pfd_clk_sel, + pll3_init_pfd_clk_sel => pll3_init_pfd_clk_sel, -- input + pll3_csr_riqclk_sel => pll3_csr_riqclk_sel, + pll3_csr_rrefclk_sel => pll3_csr_rrefclk_sel, + pll3_dp_riqclk_sel => pll3_dp_riqclk_sel, -- input + pll3_dp_rrefclk_sel => pll3_dp_rrefclk_sel, -- input + pll3_dp_pfd_clk_sel => pll3_dp_pfd_clk_sel, + pll4_init_pfd_clk_sel => pll4_init_pfd_clk_sel, -- input + pll4_csr_riqclk_sel => pll4_csr_riqclk_sel, + pll4_csr_rrefclk_sel => pll4_csr_rrefclk_sel, + pll4_dp_riqclk_sel => pll4_dp_riqclk_sel, -- input + pll4_dp_rrefclk_sel => pll4_dp_rrefclk_sel, -- input + pll4_dp_pfd_clk_sel => pll4_dp_pfd_clk_sel, + pll5_init_pfd_clk_sel => pll5_init_pfd_clk_sel, -- input + pll5_csr_riqclk_sel => pll5_csr_riqclk_sel, + pll5_csr_rrefclk_sel => pll5_csr_rrefclk_sel, + pll5_dp_riqclk_sel => pll5_dp_riqclk_sel, -- input + pll5_dp_rrefclk_sel => pll5_dp_rrefclk_sel, -- input + pll5_dp_pfd_clk_sel => pll5_dp_pfd_clk_sel, + + txpma0_init_clkin_sel => txpma0_init_clkin_sel, -- input + txpma0_csr_rcgb_x_en => txpma0_csr_rcgb_x_en, + txpma0_dp_rcgb_x_en => txpma0_dp_rcgb_x_en, -- input + txpma0_dp_clkin_sel => txpma0_dp_clkin_sel, + txpma1_init_clkin_sel => txpma1_init_clkin_sel, -- input + txpma1_csr_rcgb_x_en => txpma1_csr_rcgb_x_en, + txpma1_dp_rcgb_x_en => txpma1_dp_rcgb_x_en, -- input + txpma1_dp_clkin_sel => txpma1_dp_clkin_sel, + txpma2_init_clkin_sel => txpma2_init_clkin_sel, -- input + txpma2_csr_rcgb_x_en => txpma2_csr_rcgb_x_en, + txpma2_dp_rcgb_x_en => txpma2_dp_rcgb_x_en, -- input + txpma2_dp_clkin_sel => txpma2_dp_clkin_sel, + txpma3_init_clkin_sel => txpma3_init_clkin_sel, -- input + txpma3_csr_rcgb_x_en => txpma3_csr_rcgb_x_en, + txpma3_dp_rcgb_x_en => txpma3_dp_rcgb_x_en, -- input + txpma3_dp_clkin_sel => txpma3_dp_clkin_sel, + txpma4_init_clkin_sel => txpma4_init_clkin_sel, -- input + txpma4_csr_rcgb_x_en => txpma4_csr_rcgb_x_en, + txpma4_dp_rcgb_x_en => txpma4_dp_rcgb_x_en, -- input + txpma4_dp_clkin_sel => txpma4_dp_clkin_sel, + txpma5_init_clkin_sel => txpma5_init_clkin_sel, -- input + txpma5_csr_rcgb_x_en => txpma5_csr_rcgb_x_en, + txpma5_dp_rcgb_x_en => txpma5_dp_rcgb_x_en, -- input + txpma5_dp_clkin_sel => txpma5_dp_clkin_sel, + + clkdiv0_init_inclk_select => clkdiv0_init_inclk_select, + clkdiv0_csr_rcgb_cmu_sel => clkdiv0_csr_rcgb_cmu_sel, + clkdiv0_dp_rcgb_cmu_sel => clkdiv0_dp_rcgb_cmu_sel, + clkdiv0_dp_inclk_select => clkdiv0_dp_inclk_select, + clkdiv1_init_inclk_select => clkdiv1_init_inclk_select, + clkdiv1_csr_rcgb_cmu_sel => clkdiv1_csr_rcgb_cmu_sel, + clkdiv1_dp_rcgb_cmu_sel => clkdiv1_dp_rcgb_cmu_sel, + clkdiv1_dp_inclk_select => clkdiv1_dp_inclk_select, + clkdiv2_init_inclk_select => clkdiv2_init_inclk_select, + clkdiv2_csr_rcgb_cmu_sel => clkdiv2_csr_rcgb_cmu_sel, + clkdiv2_dp_rcgb_cmu_sel => clkdiv2_dp_rcgb_cmu_sel, + clkdiv2_dp_inclk_select => clkdiv2_dp_inclk_select, + clkdiv3_init_inclk_select => clkdiv3_init_inclk_select, + clkdiv3_csr_rcgb_cmu_sel => clkdiv3_csr_rcgb_cmu_sel, + clkdiv3_dp_rcgb_cmu_sel => clkdiv3_dp_rcgb_cmu_sel, + clkdiv3_dp_inclk_select => clkdiv3_dp_inclk_select, + clkdiv4_init_inclk_select => clkdiv4_init_inclk_select, + clkdiv4_csr_rcgb_cmu_sel => clkdiv4_csr_rcgb_cmu_sel, + clkdiv4_dp_rcgb_cmu_sel => clkdiv4_dp_rcgb_cmu_sel, + clkdiv4_dp_inclk_select => clkdiv4_dp_inclk_select, + clkdiv5_init_inclk_select => clkdiv5_init_inclk_select, + clkdiv5_csr_rcgb_cmu_sel => clkdiv5_csr_rcgb_cmu_sel, + clkdiv5_dp_rcgb_cmu_sel => clkdiv5_dp_rcgb_cmu_sel, + clkdiv5_dp_inclk_select => clkdiv5_dp_inclk_select +); + +--==================================================================== +-- Manually added code to handle logical indices = +-- === end = +--==================================================================== + +-- ------- physical to logic mapping ------------------------- +-- TXPCS +ch0_txpcsdprioout_logic <= ch0_txpcsdprioout_phy WHEN (tx0_logical_to_physical_mapping = 0) ELSE + ch1_txpcsdprioout_phy WHEN (tx0_logical_to_physical_mapping = 1) ELSE + ch2_txpcsdprioout_phy WHEN (tx0_logical_to_physical_mapping = 2) ELSE + ch3_txpcsdprioout_phy WHEN (tx0_logical_to_physical_mapping = 3) ELSE + ch0_txpcsdprioout_phy; + +ch1_txpcsdprioout_logic <= ch0_txpcsdprioout_phy WHEN (tx1_logical_to_physical_mapping = 0) ELSE + ch1_txpcsdprioout_phy WHEN (tx1_logical_to_physical_mapping = 1) ELSE + ch2_txpcsdprioout_phy WHEN (tx1_logical_to_physical_mapping = 2) ELSE + ch3_txpcsdprioout_phy WHEN (tx1_logical_to_physical_mapping = 3) ELSE + ch1_txpcsdprioout_phy; + +ch2_txpcsdprioout_logic <= ch0_txpcsdprioout_phy WHEN (tx2_logical_to_physical_mapping = 0) ELSE + ch1_txpcsdprioout_phy WHEN (tx2_logical_to_physical_mapping = 1) ELSE + ch2_txpcsdprioout_phy WHEN (tx2_logical_to_physical_mapping = 2) ELSE + ch3_txpcsdprioout_phy WHEN (tx2_logical_to_physical_mapping = 3) ELSE + ch2_txpcsdprioout_phy; + +ch3_txpcsdprioout_logic <= ch0_txpcsdprioout_phy WHEN (tx3_logical_to_physical_mapping = 0) ELSE + ch1_txpcsdprioout_phy WHEN (tx3_logical_to_physical_mapping = 1) ELSE + ch2_txpcsdprioout_phy WHEN (tx3_logical_to_physical_mapping = 2) ELSE + ch3_txpcsdprioout_phy WHEN (tx3_logical_to_physical_mapping = 3) ELSE + ch3_txpcsdprioout_phy; + +-- RXPCS +ch0_rxpcsdprioout_logic <= ch0_rxpcsdprioout_phy WHEN (rx0_logical_to_physical_mapping = 0) ELSE + ch1_rxpcsdprioout_phy WHEN (rx0_logical_to_physical_mapping = 1) ELSE + ch2_rxpcsdprioout_phy WHEN (rx0_logical_to_physical_mapping = 2) ELSE + ch3_rxpcsdprioout_phy WHEN (rx0_logical_to_physical_mapping = 3) ELSE + ch0_rxpcsdprioout_phy; + +ch1_rxpcsdprioout_logic <= ch0_rxpcsdprioout_phy WHEN (rx1_logical_to_physical_mapping = 0) ELSE + ch1_rxpcsdprioout_phy WHEN (rx1_logical_to_physical_mapping = 1) ELSE + ch2_rxpcsdprioout_phy WHEN (rx1_logical_to_physical_mapping = 2) ELSE + ch3_rxpcsdprioout_phy WHEN (rx1_logical_to_physical_mapping = 3) ELSE + ch1_rxpcsdprioout_phy; + +ch2_rxpcsdprioout_logic <= ch0_rxpcsdprioout_phy WHEN (rx2_logical_to_physical_mapping = 0) ELSE + ch1_rxpcsdprioout_phy WHEN (rx2_logical_to_physical_mapping = 1) ELSE + ch2_rxpcsdprioout_phy WHEN (rx2_logical_to_physical_mapping = 2) ELSE + ch3_rxpcsdprioout_phy WHEN (rx2_logical_to_physical_mapping = 3) ELSE + ch2_rxpcsdprioout_phy; + +ch3_rxpcsdprioout_logic <= ch0_rxpcsdprioout_phy WHEN (rx3_logical_to_physical_mapping = 0) ELSE + ch1_rxpcsdprioout_phy WHEN (rx3_logical_to_physical_mapping = 1) ELSE + ch2_rxpcsdprioout_phy WHEN (rx3_logical_to_physical_mapping = 2) ELSE + ch3_rxpcsdprioout_phy WHEN (rx3_logical_to_physical_mapping = 3) ELSE + ch3_rxpcsdprioout_phy; + +-- TXPMA +ch0_txpmadprioout_logic <= ch0_txpmadprioout_phy WHEN (tx0_logical_to_physical_mapping = 0) ELSE + ch1_txpmadprioout_phy WHEN (tx0_logical_to_physical_mapping = 1) ELSE + ch2_txpmadprioout_phy WHEN (tx0_logical_to_physical_mapping = 2) ELSE + ch3_txpmadprioout_phy WHEN (tx0_logical_to_physical_mapping = 3) ELSE + ch4_txpmadprioout_phy WHEN (tx0_logical_to_physical_mapping = 4) ELSE + ch5_txpmadprioout_phy WHEN (tx0_logical_to_physical_mapping = 5) ELSE + ch0_txpmadprioout_phy; + +ch1_txpmadprioout_logic <= ch0_txpmadprioout_phy WHEN (tx1_logical_to_physical_mapping = 0) ELSE + ch1_txpmadprioout_phy WHEN (tx1_logical_to_physical_mapping = 1) ELSE + ch2_txpmadprioout_phy WHEN (tx1_logical_to_physical_mapping = 2) ELSE + ch3_txpmadprioout_phy WHEN (tx1_logical_to_physical_mapping = 3) ELSE + ch4_txpmadprioout_phy WHEN (tx1_logical_to_physical_mapping = 4) ELSE + ch5_txpmadprioout_phy WHEN (tx1_logical_to_physical_mapping = 5) ELSE + ch1_txpmadprioout_phy; + +ch2_txpmadprioout_logic <= ch0_txpmadprioout_phy WHEN (tx2_logical_to_physical_mapping = 0) ELSE + ch1_txpmadprioout_phy WHEN (tx2_logical_to_physical_mapping = 1) ELSE + ch2_txpmadprioout_phy WHEN (tx2_logical_to_physical_mapping = 2) ELSE + ch3_txpmadprioout_phy WHEN (tx2_logical_to_physical_mapping = 3) ELSE + ch4_txpmadprioout_phy WHEN (tx2_logical_to_physical_mapping = 4) ELSE + ch5_txpmadprioout_phy WHEN (tx2_logical_to_physical_mapping = 5) ELSE + ch2_txpmadprioout_phy; + +ch3_txpmadprioout_logic <= ch0_txpmadprioout_phy WHEN (tx3_logical_to_physical_mapping = 0) ELSE + ch1_txpmadprioout_phy WHEN (tx3_logical_to_physical_mapping = 1) ELSE + ch2_txpmadprioout_phy WHEN (tx3_logical_to_physical_mapping = 2) ELSE + ch3_txpmadprioout_phy WHEN (tx3_logical_to_physical_mapping = 3) ELSE + ch4_txpmadprioout_phy WHEN (tx3_logical_to_physical_mapping = 4) ELSE + ch5_txpmadprioout_phy WHEN (tx3_logical_to_physical_mapping = 5) ELSE + ch3_txpmadprioout_phy; + +ch4_txpmadprioout_logic <= ch0_txpmadprioout_phy WHEN (tx4_logical_to_physical_mapping = 0) ELSE + ch1_txpmadprioout_phy WHEN (tx4_logical_to_physical_mapping = 1) ELSE + ch2_txpmadprioout_phy WHEN (tx4_logical_to_physical_mapping = 2) ELSE + ch3_txpmadprioout_phy WHEN (tx4_logical_to_physical_mapping = 3) ELSE + ch4_txpmadprioout_phy WHEN (tx4_logical_to_physical_mapping = 4) ELSE + ch5_txpmadprioout_phy WHEN (tx4_logical_to_physical_mapping = 5) ELSE + ch4_txpmadprioout_phy; + +ch5_txpmadprioout_logic <= ch0_txpmadprioout_phy WHEN (tx5_logical_to_physical_mapping = 0) ELSE + ch1_txpmadprioout_phy WHEN (tx5_logical_to_physical_mapping = 1) ELSE + ch2_txpmadprioout_phy WHEN (tx5_logical_to_physical_mapping = 2) ELSE + ch3_txpmadprioout_phy WHEN (tx5_logical_to_physical_mapping = 3) ELSE + ch4_txpmadprioout_phy WHEN (tx5_logical_to_physical_mapping = 4) ELSE + ch5_txpmadprioout_phy WHEN (tx5_logical_to_physical_mapping = 5) ELSE + ch5_txpmadprioout_phy; + +-- RXPMA +ch0_rxpmadprioout_logic <= ch0_rxpmadprioout_phy WHEN (rx0_logical_to_physical_mapping = 0) ELSE + ch1_rxpmadprioout_phy WHEN (rx0_logical_to_physical_mapping = 1) ELSE + ch2_rxpmadprioout_phy WHEN (rx0_logical_to_physical_mapping = 2) ELSE + ch3_rxpmadprioout_phy WHEN (rx0_logical_to_physical_mapping = 3) ELSE + ch4_rxpmadprioout_phy WHEN (rx0_logical_to_physical_mapping = 4) ELSE + ch5_rxpmadprioout_phy WHEN (rx0_logical_to_physical_mapping = 5) ELSE + ch0_rxpmadprioout_phy; + +ch1_rxpmadprioout_logic <= ch0_rxpmadprioout_phy WHEN (rx1_logical_to_physical_mapping = 0) ELSE + ch1_rxpmadprioout_phy WHEN (rx1_logical_to_physical_mapping = 1) ELSE + ch2_rxpmadprioout_phy WHEN (rx1_logical_to_physical_mapping = 2) ELSE + ch3_rxpmadprioout_phy WHEN (rx1_logical_to_physical_mapping = 3) ELSE + ch4_rxpmadprioout_phy WHEN (rx1_logical_to_physical_mapping = 4) ELSE + ch5_rxpmadprioout_phy WHEN (rx1_logical_to_physical_mapping = 5) ELSE + ch1_rxpmadprioout_phy; + +ch2_rxpmadprioout_logic <= ch0_rxpmadprioout_phy WHEN (rx2_logical_to_physical_mapping = 0) ELSE + ch1_rxpmadprioout_phy WHEN (rx2_logical_to_physical_mapping = 1) ELSE + ch2_rxpmadprioout_phy WHEN (rx2_logical_to_physical_mapping = 2) ELSE + ch3_rxpmadprioout_phy WHEN (rx2_logical_to_physical_mapping = 3) ELSE + ch4_rxpmadprioout_phy WHEN (rx2_logical_to_physical_mapping = 4) ELSE + ch5_rxpmadprioout_phy WHEN (rx2_logical_to_physical_mapping = 5) ELSE + ch2_rxpmadprioout_phy; + +ch3_rxpmadprioout_logic <= ch0_rxpmadprioout_phy WHEN (rx3_logical_to_physical_mapping = 0) ELSE + ch1_rxpmadprioout_phy WHEN (rx3_logical_to_physical_mapping = 1) ELSE + ch2_rxpmadprioout_phy WHEN (rx3_logical_to_physical_mapping = 2) ELSE + ch3_rxpmadprioout_phy WHEN (rx3_logical_to_physical_mapping = 3) ELSE + ch4_rxpmadprioout_phy WHEN (rx3_logical_to_physical_mapping = 4) ELSE + ch5_rxpmadprioout_phy WHEN (rx3_logical_to_physical_mapping = 5) ELSE + ch3_rxpmadprioout_phy; + +ch4_rxpmadprioout_logic <= ch0_rxpmadprioout_phy WHEN (rx4_logical_to_physical_mapping = 0) ELSE + ch1_rxpmadprioout_phy WHEN (rx4_logical_to_physical_mapping = 1) ELSE + ch2_rxpmadprioout_phy WHEN (rx4_logical_to_physical_mapping = 2) ELSE + ch3_rxpmadprioout_phy WHEN (rx4_logical_to_physical_mapping = 3) ELSE + ch4_rxpmadprioout_phy WHEN (rx4_logical_to_physical_mapping = 4) ELSE + ch5_rxpmadprioout_phy WHEN (rx4_logical_to_physical_mapping = 5) ELSE + ch4_rxpmadprioout_phy; + +ch5_rxpmadprioout_logic <= ch0_rxpmadprioout_phy WHEN (rx5_logical_to_physical_mapping = 0) ELSE + ch1_rxpmadprioout_phy WHEN (rx5_logical_to_physical_mapping = 1) ELSE + ch2_rxpmadprioout_phy WHEN (rx5_logical_to_physical_mapping = 2) ELSE + ch3_rxpmadprioout_phy WHEN (rx5_logical_to_physical_mapping = 3) ELSE + ch4_rxpmadprioout_phy WHEN (rx5_logical_to_physical_mapping = 4) ELSE + ch5_rxpmadprioout_phy WHEN (rx5_logical_to_physical_mapping = 5) ELSE + ch5_rxpmadprioout_phy; + +-- PLL +ch0_rxplldprioout_logic <= ch0_rxplldprioout_phy WHEN (pll0_logical_to_physical_mapping = 0) ELSE + ch1_rxplldprioout_phy WHEN (pll0_logical_to_physical_mapping = 1) ELSE + ch2_rxplldprioout_phy WHEN (pll0_logical_to_physical_mapping = 2) ELSE + ch3_rxplldprioout_phy WHEN (pll0_logical_to_physical_mapping = 3) ELSE + ch0_rxplldprioout_phy; + +ch1_rxplldprioout_logic <= ch0_rxplldprioout_phy WHEN (pll1_logical_to_physical_mapping = 0) ELSE + ch1_rxplldprioout_phy WHEN (pll1_logical_to_physical_mapping = 1) ELSE + ch2_rxplldprioout_phy WHEN (pll1_logical_to_physical_mapping = 2) ELSE + ch3_rxplldprioout_phy WHEN (pll1_logical_to_physical_mapping = 3) ELSE + ch1_rxplldprioout_phy; + +ch2_rxplldprioout_logic <= ch0_rxplldprioout_phy WHEN (pll2_logical_to_physical_mapping = 0) ELSE + ch1_rxplldprioout_phy WHEN (pll2_logical_to_physical_mapping = 1) ELSE + ch2_rxplldprioout_phy WHEN (pll2_logical_to_physical_mapping = 2) ELSE + ch3_rxplldprioout_phy WHEN (pll2_logical_to_physical_mapping = 3) ELSE + ch2_rxplldprioout_phy; + +ch3_rxplldprioout_logic <= ch0_rxplldprioout_phy WHEN (pll3_logical_to_physical_mapping = 0) ELSE + ch1_rxplldprioout_phy WHEN (pll3_logical_to_physical_mapping = 1) ELSE + ch2_rxplldprioout_phy WHEN (pll3_logical_to_physical_mapping = 2) ELSE + ch3_rxplldprioout_phy WHEN (pll3_logical_to_physical_mapping = 3) ELSE + ch3_rxplldprioout_phy; + +ch4_rxtxplldprioout_logic <= ch4_rxtxplldprioout_phy WHEN (pll4_logical_to_physical_mapping = 4) ELSE + ch5_rxtxplldprioin_phy; + +ch5_rxtxplldprioout_logic <= ch5_rxtxplldprioout_phy WHEN (pll5_logical_to_physical_mapping = 5) ELSE + ch4_rxtxplldprioin_phy; + +-- CMUDivider +ch0_cmudividerdprioout_logic <= ch0_cmudividerdprioout_phy WHEN (tx0_logical_to_physical_mapping = 0) ELSE + ch1_cmudividerdprioout_phy WHEN (tx0_logical_to_physical_mapping = 1) ELSE + ch2_cmudividerdprioout_phy WHEN (tx0_logical_to_physical_mapping = 2) ELSE + ch3_cmudividerdprioout_phy WHEN (tx0_logical_to_physical_mapping = 3) ELSE + ch4_cmudividerdprioout_phy WHEN (tx0_logical_to_physical_mapping = 4) ELSE + ch5_cmudividerdprioout_phy WHEN (tx0_logical_to_physical_mapping = 5) ELSE + ch0_cmudividerdprioout_phy; + +ch1_cmudividerdprioout_logic <= ch0_cmudividerdprioout_phy WHEN (tx1_logical_to_physical_mapping = 0) ELSE + ch1_cmudividerdprioout_phy WHEN (tx1_logical_to_physical_mapping = 1) ELSE + ch2_cmudividerdprioout_phy WHEN (tx1_logical_to_physical_mapping = 2) ELSE + ch3_cmudividerdprioout_phy WHEN (tx1_logical_to_physical_mapping = 3) ELSE + ch4_cmudividerdprioout_phy WHEN (tx1_logical_to_physical_mapping = 4) ELSE + ch5_cmudividerdprioout_phy WHEN (tx1_logical_to_physical_mapping = 5) ELSE + ch1_cmudividerdprioout_phy; + +ch2_cmudividerdprioout_logic <= ch0_cmudividerdprioout_phy WHEN (tx2_logical_to_physical_mapping = 0) ELSE + ch1_cmudividerdprioout_phy WHEN (tx2_logical_to_physical_mapping = 1) ELSE + ch2_cmudividerdprioout_phy WHEN (tx2_logical_to_physical_mapping = 2) ELSE + ch3_cmudividerdprioout_phy WHEN (tx2_logical_to_physical_mapping = 3) ELSE + ch4_cmudividerdprioout_phy WHEN (tx2_logical_to_physical_mapping = 4) ELSE + ch5_cmudividerdprioout_phy WHEN (tx2_logical_to_physical_mapping = 5) ELSE + ch2_cmudividerdprioout_phy; + +ch3_cmudividerdprioout_logic <= ch0_cmudividerdprioout_phy WHEN (tx3_logical_to_physical_mapping = 0) ELSE + ch1_cmudividerdprioout_phy WHEN (tx3_logical_to_physical_mapping = 1) ELSE + ch2_cmudividerdprioout_phy WHEN (tx3_logical_to_physical_mapping = 2) ELSE + ch3_cmudividerdprioout_phy WHEN (tx3_logical_to_physical_mapping = 3) ELSE + ch4_cmudividerdprioout_phy WHEN (tx3_logical_to_physical_mapping = 4) ELSE + ch5_cmudividerdprioout_phy WHEN (tx3_logical_to_physical_mapping = 5) ELSE + ch3_cmudividerdprioout_phy; + +ch4_cmudividerdprioout_logic <= ch0_cmudividerdprioout_phy WHEN (tx4_logical_to_physical_mapping = 0) ELSE + ch1_cmudividerdprioout_phy WHEN (tx4_logical_to_physical_mapping = 1) ELSE + ch2_cmudividerdprioout_phy WHEN (tx4_logical_to_physical_mapping = 2) ELSE + ch3_cmudividerdprioout_phy WHEN (tx4_logical_to_physical_mapping = 3) ELSE + ch4_cmudividerdprioout_phy WHEN (tx4_logical_to_physical_mapping = 4) ELSE + ch5_cmudividerdprioout_phy WHEN (tx4_logical_to_physical_mapping = 5) ELSE + ch4_cmudividerdprioout_phy; + +ch5_cmudividerdprioout_logic <= ch0_cmudividerdprioout_phy WHEN (tx5_logical_to_physical_mapping = 0) ELSE + ch1_cmudividerdprioout_phy WHEN (tx5_logical_to_physical_mapping = 1) ELSE + ch2_cmudividerdprioout_phy WHEN (tx5_logical_to_physical_mapping = 2) ELSE + ch3_cmudividerdprioout_phy WHEN (tx5_logical_to_physical_mapping = 3) ELSE + ch4_cmudividerdprioout_phy WHEN (tx5_logical_to_physical_mapping = 4) ELSE + ch5_cmudividerdprioout_phy WHEN (tx5_logical_to_physical_mapping = 5) ELSE + ch5_cmudividerdprioout_phy; + +-- ------- output -------------------------------------------- +-- TXPCS +txpcsdprioout(149 DOWNTO 0) <= ch0_txpcsdprioout_logic; +txpcsdprioout(299 DOWNTO 150) <= ch1_txpcsdprioout_logic; +txpcsdprioout(449 DOWNTO 300) <= ch2_txpcsdprioout_logic; +txpcsdprioout(599 DOWNTO 450) <= ch3_txpcsdprioout_logic; +-- RXPCS +rxpcsdprioout(399 DOWNTO 0) <= ch0_rxpcsdprioout_logic; +rxpcsdprioout(799 DOWNTO 400) <= ch1_rxpcsdprioout_logic; +rxpcsdprioout(1199 DOWNTO 800) <= ch2_rxpcsdprioout_logic; +rxpcsdprioout(1599 DOWNTO 1200) <= ch3_rxpcsdprioout_logic; +-- TXPMA +txpmadprioout(299 DOWNTO 0) <= ch0_txpmadprioout_logic; +txpmadprioout(599 DOWNTO 300) <= ch1_txpmadprioout_logic; +txpmadprioout(899 DOWNTO 600) <= ch2_txpmadprioout_logic; +txpmadprioout(1199 DOWNTO 900) <= ch3_txpmadprioout_logic; + +-- RXPMA +rxpmadprioout(299 DOWNTO 0) <= ch0_rxpmadprioout_logic; +rxpmadprioout(599 DOWNTO 300) <= ch1_rxpmadprioout_logic; +rxpmadprioout(899 DOWNTO 600) <= ch2_rxpmadprioout_logic; +rxpmadprioout(1199 DOWNTO 900) <= ch3_rxpmadprioout_logic; + +-- PLL +cmuplldprioout(299 DOWNTO 0) <= ch0_rxplldprioout_logic; +cmuplldprioout(599 DOWNTO 300) <= ch1_rxplldprioout_logic; +cmuplldprioout(899 DOWNTO 600) <= ch2_rxplldprioout_logic; +cmuplldprioout(1199 DOWNTO 900) <= ch3_rxplldprioout_logic; +cmuplldprioout(1499 DOWNTO 1200) <= ch4_rxtxplldprioout_logic; +cmuplldprioout(1799 DOWNTO 1500) <= ch5_rxtxplldprioout_logic; + +-- CMUDivider +cmudividerdprioout (99 DOWNTO 0) <= ch0_cmudividerdprioout_logic; +cmudividerdprioout (199 DOWNTO 100) <= ch1_cmudividerdprioout_logic; +cmudividerdprioout (299 DOWNTO 200) <= ch2_cmudividerdprioout_logic; +cmudividerdprioout (399 DOWNTO 300) <= ch3_cmudividerdprioout_logic; +cmudividerdprioout (499 DOWNTO 400) <= ch4_cmudividerdprioout_logic; +cmudividerdprioout (599 DOWNTO 500) <= ch5_cmudividerdprioout_logic; + + +--============================================================ +-- Manually added code to handle 5th/6th PMA ================= +-- === begin = +--============================================================ + +-- centrl CSR physcial --------------------------------------- +cmu0_in_centrl_ctrl_1 <= ch4_in_chnl_ctrl_28; +cmu0_in_centrl_ctrl_2 <= ch4_in_chnl_ctrl_29; +cmu0_in_centrl_ctrl_3 <= ch4_in_chnl_ctrl_30; +cmu0_in_centrl_ctrl_4 <= ch4_in_chnl_ctrl_31; +cmu0_in_centrl_ctrl_5 <= ch4_in_chnl_ctrl_32; +cmu0_in_centrl_ctrl_6 <= ch4_in_chnl_ctrl_33; +cmu0_in_centrl_ctrl_7 <= ch4_in_chnl_ctrl_34; +cmu0_in_centrl_ctrl_8 <= ch4_in_chnl_ctrl_35; +cmu0_in_centrl_ctrl_9 <= ch4_in_chnl_ctrl_36; +cmu0_in_centrl_ctrl_10 <= ch4_in_chnl_ctrl_37; +cmu0_in_centrl_ctrl_11 <= ch4_in_chnl_ctrl_38; +cmu0_in_centrl_ctrl_12 <= ch4_in_chnl_ctrl_39; +cmu0_in_centrl_ctrl_13 <= ch4_in_chnl_ctrl_40; +cmu0_in_centrl_ctrl_14 <= ch4_in_chnl_ctrl_41; +cmu0_in_centrl_ctrl_15 <= ch4_in_chnl_ctrl_42; +cmu0_in_centrl_ctrl_16 <= ch4_in_chnl_ctrl_43; +cmu0_in_centrl_ctrl_17 <= ch4_in_chnl_ctrl_44; +cmu0_in_centrl_ctrl_18 <= ch4_in_chnl_ctrl_45; +cmu0_in_centrl_ctrl_19 <= ch4_in_chnl_ctrl_46; +cmu0_in_centrl_ctrl_20 <= ch4_in_chnl_ctrl_47; + +cmu1_in_centrl_ctrl_1 <= ch5_in_chnl_ctrl_28; +cmu1_in_centrl_ctrl_2 <= ch5_in_chnl_ctrl_29; +cmu1_in_centrl_ctrl_3 <= ch5_in_chnl_ctrl_30; +cmu1_in_centrl_ctrl_4 <= ch5_in_chnl_ctrl_31; +cmu1_in_centrl_ctrl_5 <= ch5_in_chnl_ctrl_32; +cmu1_in_centrl_ctrl_6 <= ch5_in_chnl_ctrl_33; +cmu1_in_centrl_ctrl_7 <= ch5_in_chnl_ctrl_34; +cmu1_in_centrl_ctrl_8 <= ch5_in_chnl_ctrl_35; +cmu1_in_centrl_ctrl_9 <= ch5_in_chnl_ctrl_36; +cmu1_in_centrl_ctrl_10 <= ch5_in_chnl_ctrl_37; +cmu1_in_centrl_ctrl_11 <= ch5_in_chnl_ctrl_38; +cmu1_in_centrl_ctrl_12 <= ch5_in_chnl_ctrl_39; +cmu1_in_centrl_ctrl_13 <= ch5_in_chnl_ctrl_40; +cmu1_in_centrl_ctrl_14 <= ch5_in_chnl_ctrl_41; +cmu1_in_centrl_ctrl_15 <= ch5_in_chnl_ctrl_42; +cmu1_in_centrl_ctrl_16 <= ch5_in_chnl_ctrl_43; +cmu1_in_centrl_ctrl_17 <= ch5_in_chnl_ctrl_44; +cmu1_in_centrl_ctrl_18 <= ch5_in_chnl_ctrl_45; +cmu1_in_centrl_ctrl_19 <= ch5_in_chnl_ctrl_46; +cmu1_in_centrl_ctrl_20 <= ch5_in_chnl_ctrl_47; + +csr_centrl_in(15 DOWNTO 0) <= cmu0_in_centrl_ctrl_1; +csr_centrl_in(31 DOWNTO 16) <= cmu0_in_centrl_ctrl_2; +csr_centrl_in(47 DOWNTO 32) <= cmu0_in_centrl_ctrl_3; +csr_centrl_in(63 DOWNTO 48) <= cmu0_in_centrl_ctrl_4; +csr_centrl_in(79 DOWNTO 64) <= cmu0_in_centrl_ctrl_5; +csr_centrl_in(95 DOWNTO 80) <= cmu0_in_centrl_ctrl_6; +csr_centrl_in(111 DOWNTO 96) <= cmu0_in_centrl_ctrl_7; +csr_centrl_in(127 DOWNTO 112) <= cmu0_in_centrl_ctrl_8; +csr_centrl_in(143 DOWNTO 128) <= cmu0_in_centrl_ctrl_9; +csr_centrl_in(159 DOWNTO 144) <= cmu0_in_centrl_ctrl_10; +csr_centrl_in(175 DOWNTO 160) <= cmu0_in_centrl_ctrl_11; +csr_centrl_in(191 DOWNTO 176) <= cmu0_in_centrl_ctrl_12; +csr_centrl_in(207 DOWNTO 192) <= cmu0_in_centrl_ctrl_13; +csr_centrl_in(223 DOWNTO 208) <= cmu0_in_centrl_ctrl_14; +csr_centrl_in(239 DOWNTO 224) <= cmu0_in_centrl_ctrl_15; +csr_centrl_in_reserved(15 DOWNTO 0) <= cmu0_in_centrl_ctrl_16; +csr_centrl_in(255 DOWNTO 240) <= cmu0_in_centrl_ctrl_17; +csr_centrl_in(271 DOWNTO 256) <= cmu0_in_centrl_ctrl_18; +csr_centrl_in(287 DOWNTO 272) <= cmu0_in_centrl_ctrl_19; +csr_centrl_in(303 DOWNTO 288) <= cmu0_in_centrl_ctrl_20; +csr_centrl_in(319 DOWNTO 304) <= cmu0_in_centrl_ctrl_21; -- cmu only + +csr_centrl_in(335 DOWNTO 320) <= cmu1_in_centrl_ctrl_1; +csr_centrl_in(351 DOWNTO 336) <= cmu1_in_centrl_ctrl_2; +csr_centrl_in(367 DOWNTO 352) <= cmu1_in_centrl_ctrl_3; +csr_centrl_in(383 DOWNTO 368) <= cmu1_in_centrl_ctrl_4; +csr_centrl_in(399 DOWNTO 384) <= cmu1_in_centrl_ctrl_5; +csr_centrl_in(415 DOWNTO 400) <= cmu1_in_centrl_ctrl_6; +csr_centrl_in(431 DOWNTO 416) <= cmu1_in_centrl_ctrl_7; +csr_centrl_in(447 DOWNTO 432) <= cmu1_in_centrl_ctrl_8; +csr_centrl_in(463 DOWNTO 448) <= cmu1_in_centrl_ctrl_9; +csr_centrl_in(479 DOWNTO 464) <= cmu1_in_centrl_ctrl_10; +csr_centrl_in(495 DOWNTO 480) <= cmu1_in_centrl_ctrl_11; +csr_centrl_in(511 DOWNTO 496) <= cmu1_in_centrl_ctrl_12; +csr_centrl_in(527 DOWNTO 512) <= cmu1_in_centrl_ctrl_13; +csr_centrl_in(543 DOWNTO 528) <= cmu1_in_centrl_ctrl_14; +csr_centrl_in(559 DOWNTO 544) <= cmu1_in_centrl_ctrl_15; +csr_centrl_in_reserved(31 DOWNTO 16) <= cmu1_in_centrl_ctrl_16; +csr_centrl_in(575 DOWNTO 560) <= cmu1_in_centrl_ctrl_17; +csr_centrl_in(591 DOWNTO 576) <= cmu1_in_centrl_ctrl_18; +csr_centrl_in(607 DOWNTO 592) <= cmu1_in_centrl_ctrl_19; +csr_centrl_in(623 DOWNTO 608) <= cmu1_in_centrl_ctrl_20; +csr_centrl_in(639 DOWNTO 624) <= cmu1_in_centrl_ctrl_21; -- cmu only Table 74 + +csr_centrl_in(655 DOWNTO 640) <= cmu_in_centrl_global_0; -- global XAUI etc. Table 75 +csr_centrl_in(671 DOWNTO 656) <= cmu_in_centrl_global_1; +csr_centrl_in(687 DOWNTO 672) <= cmu_in_centrl_global_2; +csr_centrl_in(703 DOWNTO 688) <= cmu_in_centrl_global_3; + +-- centrl DPRIO out physcial --------------------------------- +cmu0_out_centrl_ctrl_1 <= dp_centrl_out(15 DOWNTO 0) ; +cmu0_out_centrl_ctrl_2 <= dp_centrl_out(31 DOWNTO 16) ; +cmu0_out_centrl_ctrl_3 <= dp_centrl_out(47 DOWNTO 32) ; +cmu0_out_centrl_ctrl_4 <= dp_centrl_out(63 DOWNTO 48) ; +cmu0_out_centrl_ctrl_5 <= dp_centrl_out(79 DOWNTO 64) ; +cmu0_out_centrl_ctrl_6 <= dp_centrl_out(95 DOWNTO 80) ; +cmu0_out_centrl_ctrl_7 <= dp_centrl_out(111 DOWNTO 96) ; +cmu0_out_centrl_ctrl_8 <= dp_centrl_out(127 DOWNTO 112) ; +cmu0_out_centrl_ctrl_9 <= dp_centrl_out(143 DOWNTO 128) ; +cmu0_out_centrl_ctrl_10 <= dp_centrl_out(159 DOWNTO 144) ; +cmu0_out_centrl_ctrl_11 <= dp_centrl_out(175 DOWNTO 160) ; +cmu0_out_centrl_ctrl_12 <= dp_centrl_out(191 DOWNTO 176) ; +cmu0_out_centrl_ctrl_13 <= dp_centrl_out(207 DOWNTO 192) ; +cmu0_out_centrl_ctrl_14 <= dp_centrl_out(223 DOWNTO 208) ; +cmu0_out_centrl_ctrl_15 <= dp_centrl_out(239 DOWNTO 224) ; +cmu0_out_centrl_ctrl_16 <= dp_centrl_out_reserved(15 DOWNTO 0); +cmu0_out_centrl_ctrl_17 <= dp_centrl_out(255 DOWNTO 240) ; +cmu0_out_centrl_ctrl_18 <= dp_centrl_out(271 DOWNTO 256) ; +cmu0_out_centrl_ctrl_19 <= dp_centrl_out(287 DOWNTO 272) ; +cmu0_out_centrl_ctrl_20 <= dp_centrl_out(303 DOWNTO 288) ; +cmu0_out_centrl_ctrl_21 <= dp_centrl_out(319 DOWNTO 304) ; + +cmu1_out_centrl_ctrl_1 <= dp_centrl_out(335 DOWNTO 320) ; +cmu1_out_centrl_ctrl_2 <= dp_centrl_out(351 DOWNTO 336) ; +cmu1_out_centrl_ctrl_3 <= dp_centrl_out(367 DOWNTO 352) ; +cmu1_out_centrl_ctrl_4 <= dp_centrl_out(383 DOWNTO 368) ; +cmu1_out_centrl_ctrl_5 <= dp_centrl_out(399 DOWNTO 384) ; +cmu1_out_centrl_ctrl_6 <= dp_centrl_out(415 DOWNTO 400) ; +cmu1_out_centrl_ctrl_7 <= dp_centrl_out(431 DOWNTO 416) ; +cmu1_out_centrl_ctrl_8 <= dp_centrl_out(447 DOWNTO 432) ; +cmu1_out_centrl_ctrl_9 <= dp_centrl_out(463 DOWNTO 448) ; +cmu1_out_centrl_ctrl_10 <= dp_centrl_out(479 DOWNTO 464) ; +cmu1_out_centrl_ctrl_11 <= dp_centrl_out(495 DOWNTO 480) ; +cmu1_out_centrl_ctrl_12 <= dp_centrl_out(511 DOWNTO 496) ; +cmu1_out_centrl_ctrl_13 <= dp_centrl_out(527 DOWNTO 512) ; +cmu1_out_centrl_ctrl_14 <= dp_centrl_out(543 DOWNTO 528) ; +cmu1_out_centrl_ctrl_15 <= dp_centrl_out(559 DOWNTO 544) ; +cmu1_out_centrl_ctrl_16 <= dp_centrl_out_reserved(31 DOWNTO 16); +cmu1_out_centrl_ctrl_17 <= dp_centrl_out(575 DOWNTO 560) ; +cmu1_out_centrl_ctrl_18 <= dp_centrl_out(591 DOWNTO 576) ; +cmu1_out_centrl_ctrl_19 <= dp_centrl_out(607 DOWNTO 592) ; +cmu1_out_centrl_ctrl_20 <= dp_centrl_out(623 DOWNTO 608) ; +cmu1_out_centrl_ctrl_21 <= dp_centrl_out(639 DOWNTO 624) ; + +cmu_out_centrl_global_0 <= dp_centrl_out(655 DOWNTO 640) ; -- global XAUI etc. Tables 75 +cmu_out_centrl_global_1 <= dp_centrl_out(671 DOWNTO 656) ; +cmu_out_centrl_global_2 <= dp_centrl_out(687 DOWNTO 672) ; +cmu_out_centrl_global_3 <= dp_centrl_out(703 DOWNTO 688) ; + +ch4_out_chnl_ctrl_28 <= cmu0_out_centrl_ctrl_1; +ch4_out_chnl_ctrl_29 <= cmu0_out_centrl_ctrl_2; +ch4_out_chnl_ctrl_30 <= cmu0_out_centrl_ctrl_3; +ch4_out_chnl_ctrl_31 <= cmu0_out_centrl_ctrl_4; +ch4_out_chnl_ctrl_32 <= cmu0_out_centrl_ctrl_5; +ch4_out_chnl_ctrl_33 <= cmu0_out_centrl_ctrl_6; +ch4_out_chnl_ctrl_34 <= cmu0_out_centrl_ctrl_7; +ch4_out_chnl_ctrl_35 <= cmu0_out_centrl_ctrl_8; +ch4_out_chnl_ctrl_36 <= cmu0_out_centrl_ctrl_9; +ch4_out_chnl_ctrl_37 <= cmu0_out_centrl_ctrl_10; +ch4_out_chnl_ctrl_38 <= cmu0_out_centrl_ctrl_11; +ch4_out_chnl_ctrl_39 <= cmu0_out_centrl_ctrl_12; +ch4_out_chnl_ctrl_40 <= cmu0_out_centrl_ctrl_13; +ch4_out_chnl_ctrl_41 <= cmu0_out_centrl_ctrl_14; +ch4_out_chnl_ctrl_42 <= cmu0_out_centrl_ctrl_15; +ch4_out_chnl_ctrl_43 <= cmu0_out_centrl_ctrl_16; +ch4_out_chnl_ctrl_44 <= cmu0_out_centrl_ctrl_17; +ch4_out_chnl_ctrl_45 <= cmu0_out_centrl_ctrl_18; +ch4_out_chnl_ctrl_46 <= cmu0_out_centrl_ctrl_19; +ch4_out_chnl_ctrl_47 <= cmu0_out_centrl_ctrl_20; + +ch5_out_chnl_ctrl_28 <= cmu1_out_centrl_ctrl_1; +ch5_out_chnl_ctrl_29 <= cmu1_out_centrl_ctrl_2; +ch5_out_chnl_ctrl_30 <= cmu1_out_centrl_ctrl_3; +ch5_out_chnl_ctrl_31 <= cmu1_out_centrl_ctrl_4; +ch5_out_chnl_ctrl_32 <= cmu1_out_centrl_ctrl_5; +ch5_out_chnl_ctrl_33 <= cmu1_out_centrl_ctrl_6; +ch5_out_chnl_ctrl_34 <= cmu1_out_centrl_ctrl_7; +ch5_out_chnl_ctrl_35 <= cmu1_out_centrl_ctrl_8; +ch5_out_chnl_ctrl_36 <= cmu1_out_centrl_ctrl_9; +ch5_out_chnl_ctrl_37 <= cmu1_out_centrl_ctrl_10; +ch5_out_chnl_ctrl_38 <= cmu1_out_centrl_ctrl_11; +ch5_out_chnl_ctrl_39 <= cmu1_out_centrl_ctrl_12; +ch5_out_chnl_ctrl_40 <= cmu1_out_centrl_ctrl_13; +ch5_out_chnl_ctrl_41 <= cmu1_out_centrl_ctrl_14; +ch5_out_chnl_ctrl_42 <= cmu1_out_centrl_ctrl_15; +ch5_out_chnl_ctrl_43 <= cmu1_out_centrl_ctrl_16; +ch5_out_chnl_ctrl_44 <= cmu1_out_centrl_ctrl_17; +ch5_out_chnl_ctrl_45 <= cmu1_out_centrl_ctrl_18; +ch5_out_chnl_ctrl_46 <= cmu1_out_centrl_ctrl_19; +ch5_out_chnl_ctrl_47 <= cmu1_out_centrl_ctrl_20; + +--============================================================ +-- Manually added code to handle 5th/6th PMA ================= +-- === end = +--============================================================ + + +END trans; + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +ENTITY cycloneiv_hssi_cmu_dprio_top IS + GENERIC ( + -- Simulation Only + clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1"; + + pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll0_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll0_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll0_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll0_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll0_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll0_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll1_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll1_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll1_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll1_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll1_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll1_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll2_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll2_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll2_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll2_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll2_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll2_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll3_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll3_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll3_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll3_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll3_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll3_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll4_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll4_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll4_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll4_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll4_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll4_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll5_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll5_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll5_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll5_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll5_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll5_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + + pll0_logical_to_physical_mapping : INTEGER := 0; + pll1_logical_to_physical_mapping : INTEGER := 1; + pll2_logical_to_physical_mapping : INTEGER := 2; + pll3_logical_to_physical_mapping : INTEGER := 3; + pll4_logical_to_physical_mapping : INTEGER := 4; + pll5_logical_to_physical_mapping : INTEGER := 5; + + refclk_divider0_logical_to_physical_mapping : INTEGER := 0; + refclk_divider1_logical_to_physical_mapping : INTEGER := 1; + + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + rx4_logical_to_physical_mapping : INTEGER := 4; + rx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + tx4_logical_to_physical_mapping : INTEGER := 4; + tx5_logical_to_physical_mapping : INTEGER := 5; + + + tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + + sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps + sim_dump_filename : STRING := "sim_dprio_dump.txt" + ); + PORT ( + sync_status : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + align_status : IN STD_LOGIC; + + -- MDIO inputs/outpus + mdio_in : IN STD_LOGIC; + mdc : IN STD_LOGIC; + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + + mdio_dis : IN STD_LOGIC; -- 1'b1=output CRAM (para), 1'b0=output MDIO control register + dprioload : IN STD_LOGIC; -- load MDIO control register with CRAM_ext (parameter). SER_SHFIT_LOAD? + mdio_rst : IN STD_LOGIC; + + refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + + refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + + mdio_out : OUT STD_LOGIC; + data_enable_n : OUT STD_LOGIC; + mdio_curr_st : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END cycloneiv_hssi_cmu_dprio_top; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu_dprio_top IS + COMPONENT cycloneiv_hssi_cmu_dprio_addr + PORT ( + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + shift_addr : IN STD_LOGIC; + incr_addr : IN STD_LOGIC; + reg_addr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_ctl_data + PORT ( + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + shift_in : IN STD_LOGIC; + shift_out : IN STD_LOGIC; + ld_data : IN STD_LOGIC; + latch_ctl : IN STD_LOGIC; + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + valid_addr_lt : IN STD_LOGIC; + mbus_out : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdio_out : OUT STD_LOGIC; + data_enable_n : OUT STD_LOGIC; + mbus_in : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + opcode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + valid_addr : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_centrl_top + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + csr_centrl_in : IN STD_LOGIC_VECTOR(703 DOWNTO 0); + csr_centrl_in_reserved : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + dp_centrl_out : OUT STD_LOGIC_VECTOR(703 DOWNTO 0); + dp_centrl_out_reserved : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + so : OUT STD_LOGIC; + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_map + GENERIC ( + -- Simulation Only + clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1"; + + pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll0_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll0_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll0_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll0_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll0_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll0_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll1_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll1_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll1_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll1_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll1_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll1_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll2_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll2_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll2_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll2_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll2_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll2_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll3_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll3_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll3_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll3_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll3_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll3_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll4_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll4_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll4_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll4_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll4_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll4_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll5_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll5_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll5_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll5_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll5_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll5_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + + + pll0_logical_to_physical_mapping : INTEGER := 0; + pll1_logical_to_physical_mapping : INTEGER := 1; + pll2_logical_to_physical_mapping : INTEGER := 2; + pll3_logical_to_physical_mapping : INTEGER := 3; + pll4_logical_to_physical_mapping : INTEGER := 4; + pll5_logical_to_physical_mapping : INTEGER := 5; + + refclk_divider0_logical_to_physical_mapping : INTEGER := 0; + refclk_divider1_logical_to_physical_mapping : INTEGER := 1; + + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + rx4_logical_to_physical_mapping : INTEGER := 4; + rx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + tx4_logical_to_physical_mapping : INTEGER := 4; + tx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + + sim_dump_dprio_internal_reg_at_time : INTEGER := 0; + sim_dump_filename : STRING := "sim_dprio_dump.txt" + ); + PORT ( + cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0); + cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0); + refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + + ch0_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch1_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch2_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch3_dp_chnl_out : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + ch0_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ch1_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ch2_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ch3_dp_chnl_out_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dp_centrl_out : IN STD_LOGIC_VECTOR(703 DOWNTO 0); + dp_centrl_out_reserved : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + ch0_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch1_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch2_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch3_csr_chnl_in : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + ch0_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + ch1_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + ch2_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + ch3_csr_chnl_in_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + csr_centrl_in : OUT STD_LOGIC_VECTOR(703 DOWNTO 0); + csr_centrl_in_reserved : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0); + refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_cnt + PORT ( + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC; + ld_cnt : IN STD_LOGIC; + cnt_val : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + cnt_eq_0 : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_chnl_top + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + pma_cram_test : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + csr_chnl_in : IN STD_LOGIC_VECTOR(831 DOWNTO 0); + csr_chnl_in_reserved : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dprio_chnl_id : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dp_chnl_out : OUT STD_LOGIC_VECTOR(831 DOWNTO 0); + dp_chnl_out_reserved : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC; + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_status + GENERIC ( + XGXS_STATUS1 : INTEGER := 24580; + XGXS_STATUS2 : INTEGER := 24581; + XGXS_LANE_STATUS : INTEGER := 24582 + ); + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_rd : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + dev_addr_0 : IN STD_LOGIC; + mdc : IN STD_LOGIC; + serial_mode : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + mbus_out_ch0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_ch1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_ch2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_ch3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mbus_out_centrl : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + align_status : IN STD_LOGIC; + sync_status : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + xs_link_status : IN STD_LOGIC; + rx_local_fault : IN STD_LOGIC; + tx_local_fault : IN STD_LOGIC; + rxs_link_status_set : OUT STD_LOGIC; + rtx_rx_local_fault_clr : OUT STD_LOGIC; + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_sm + GENERIC ( + IDLE : INTEGER := 0; + PREAMBLE : INTEGER := 1; + CONTROL : INTEGER := 2; + TURN_ARND_0 : INTEGER := 3; + TURN_ARND_1 : INTEGER := 4; + ADDR_DATA : INTEGER := 5; + ADDR_OP : INTEGER := 0; + WR_OP : INTEGER := 1; + RD_INC_OP : INTEGER := 2; + RD_OP : INTEGER := 3 + ); + PORT ( + mdc : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + reset : IN STD_LOGIC; + opcode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + valid_addr : IN STD_LOGIC; + cnt_eq_0 : IN STD_LOGIC; + shift_in : OUT STD_LOGIC; + shift_out : OUT STD_LOGIC; + latch_ctl : OUT STD_LOGIC; + incr_addr : OUT STD_LOGIC; + mdio_wr : OUT STD_LOGIC; + mdio_rd : OUT STD_LOGIC; + shift_addr : OUT STD_LOGIC; + ld_data : OUT STD_LOGIC; + ld_cnt : OUT STD_LOGIC; + cnt_val : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + valid_addr_lt : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT; + + + -- -------------------------------------------------------------------- + -- status reg --------------------------------------------------------- + -- -------------------------------------------------------------------- + + SIGNAL gnd_wire : STD_LOGIC; + SIGNAL vcc_wire : STD_LOGIC; + + SIGNAL so_status : STD_LOGIC; + SIGNAL rxs_link_status_set : STD_LOGIC; + SIGNAL rtx_rx_local_fault_clr : STD_LOGIC; + + -- -------------------------------------------------------------------- + -- interface to channel ----------------------------------------------- + -- -------------------------------------------------------------------- + SIGNAL csr_chnl_in_ch0 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- CSR inputs + SIGNAL csr_chnl_in_ch1 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- CSR inputs + SIGNAL csr_chnl_in_ch2 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- CSR inputs + SIGNAL csr_chnl_in_ch3 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- CSR inputs + SIGNAL csr_chnl_in_reserved_ch0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL csr_chnl_in_reserved_ch1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL csr_chnl_in_reserved_ch2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL csr_chnl_in_reserved_ch3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL dprio_chnl_id0 : STD_LOGIC_VECTOR(3 DOWNTO 0); -- DPRIO channel base address ID + SIGNAL dprio_chnl_id1 : STD_LOGIC_VECTOR(3 DOWNTO 0); -- DPRIO channel base address ID + SIGNAL dprio_chnl_id2 : STD_LOGIC_VECTOR(3 DOWNTO 0); -- DPRIO channel base address ID + SIGNAL dprio_chnl_id3 : STD_LOGIC_VECTOR(3 DOWNTO 0); -- DPRIO channel base address ID + + SIGNAL si_ch0 : STD_LOGIC; + SIGNAL si_ch1 : STD_LOGIC; + SIGNAL si_ch2 : STD_LOGIC; + SIGNAL si_ch3 : STD_LOGIC; + + SIGNAL dp_chnl_out_ch0 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- + SIGNAL dp_chnl_out_ch1 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- + SIGNAL dp_chnl_out_ch2 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- + SIGNAL dp_chnl_out_ch3 : STD_LOGIC_VECTOR(831 DOWNTO 0); -- + SIGNAL dp_chnl_out_reserved_ch0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL dp_chnl_out_reserved_ch1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL dp_chnl_out_reserved_ch2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL dp_chnl_out_reserved_ch3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL so_ch0 : STD_LOGIC; + SIGNAL so_ch1 : STD_LOGIC; + SIGNAL so_ch2 : STD_LOGIC; + SIGNAL so_ch3 : STD_LOGIC; + + SIGNAL mbus_out_ch0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL mbus_out_ch1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL mbus_out_ch2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL mbus_out_ch3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- -------------------------------------------------------------------- + -- interface to cmu --------------------------------------------------- + -- -------------------------------------------------------------------- + SIGNAL csr_centrl_in : STD_LOGIC_VECTOR(703 DOWNTO 0); -- CSR inputs + SIGNAL csr_centrl_in_reserved : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL si_centrl : STD_LOGIC; + + SIGNAL dp_centrl_out : STD_LOGIC_VECTOR(703 DOWNTO 0); -- CSR inputs + SIGNAL dp_centrl_out_reserved : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL mbus_out_centrl : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL so_centrl : STD_LOGIC; + + -- -------------------------------------------------------------------- + -- new in CYCLONEIV common -------------------------------------------------- + -- -------------------------------------------------------------------- + + -- input -------------------- + -- PLD dynamic signal for PMA DPRIO cell for coverage for PE/TE + SIGNAL pma_cram_test : STD_LOGIC; + SIGNAL serial_mode : STD_LOGIC; + + -- unused ports to be moved into reg + SIGNAL jtag_mode : STD_LOGIC; + SIGNAL jtag_shift_load : STD_LOGIC; + SIGNAL jtag_si : STD_LOGIC; + SIGNAL jtag_so : STD_LOGIC; -- wire + + -- status signals generated by PCS + SIGNAL tx_local_fault : STD_LOGIC; -- from tx_sm + SIGNAL rx_local_fault : STD_LOGIC; -- from rcv_sm + SIGNAL xs_link_status : STD_LOGIC; -- from rcv_sm + + SIGNAL local_fault_ext : STD_LOGIC; -- Status signal wire + SIGNAL xs_link_status_ext : STD_LOGIC; -- Status signal wire + SIGNAL rx_local_fault_ext : STD_LOGIC; -- Status signal wire + SIGNAL tx_local_fault_ext : STD_LOGIC; -- Status signal wire + + -- interconnect wires -------------------------------------------------- + + -- wires from addr + SIGNAL reg_addr : STD_LOGIC_VECTOR(15 DOWNTO 0); -- addr --> reg + + -- wires from sm + SIGNAL shift_addr : STD_LOGIC; -- sm --> addr + SIGNAL incr_addr : STD_LOGIC; -- sm --> addr + + SIGNAL ld_cnt : STD_LOGIC; -- sm --> cnt + SIGNAL cnt_val : STD_LOGIC_VECTOR(4 DOWNTO 0); -- sm --> cnt + SIGNAL ld_data : STD_LOGIC; -- sm --> cnt + + SIGNAL shift_in : STD_LOGIC; -- sm --> ctl_data + SIGNAL shift_out : STD_LOGIC; -- sm --> ctl_data + SIGNAL latch_ctl : STD_LOGIC; -- sm --> ctl_data + SIGNAL valid_addr_lt : STD_LOGIC; -- sm --> ctl_data + + SIGNAL mdio_wr : STD_LOGIC; -- sm --> reg + SIGNAL mdio_rd : STD_LOGIC; -- sm --> reg + + SIGNAL curr_state : STD_LOGIC_VECTOR(2 DOWNTO 0); -- sm --> top (../../pcs_central_testbus in central_chnnl) + + -- wires from cnt + SIGNAL cnt_eq_0 : STD_LOGIC; -- cnt --> sm + + -- wires from ctl_data + SIGNAL mbus_in : STD_LOGIC_VECTOR(15 DOWNTO 0); -- ctl_data --> reg + SIGNAL valid_addr : STD_LOGIC; -- ctl_data --> sm + SIGNAL opcode : STD_LOGIC_VECTOR(1 DOWNTO 0); -- ctl_data --> sm + + -- ctl_data --> top + -- ctl_data --> top + + -- wires from reg + SIGNAL mbus_out : STD_LOGIC_VECTOR(15 DOWNTO 0); -- reg --> ctl_data + + --wires to reg + SIGNAL dev_addr_0 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL cmudividerdprioout_xhdl0 : STD_LOGIC_VECTOR(599 DOWNTO 0); + SIGNAL cmuplldprioout_xhdl1 : STD_LOGIC_VECTOR(1799 DOWNTO 0); + SIGNAL refclkdividerdprioout_xhdl4 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rxpcsdprioout_xhdl5 : STD_LOGIC_VECTOR(1599 DOWNTO 0); + SIGNAL rxpmadprioout_xhdl6 : STD_LOGIC_VECTOR(1199 DOWNTO 0); + SIGNAL txpcsdprioout_xhdl7 : STD_LOGIC_VECTOR(599 DOWNTO 0); + SIGNAL txpmadprioout_xhdl8 : STD_LOGIC_VECTOR(1199 DOWNTO 0); + SIGNAL mdio_out_xhdl3 : STD_LOGIC; + SIGNAL data_enable_n_xhdl2 : STD_LOGIC; + SIGNAL rxpmadprioin_int : STD_LOGIC_VECTOR(1199 DOWNTO 0); + SIGNAL cmuplldprioin_int : STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0'); + SIGNAL cmudividerdprioin_int : STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0'); + + +BEGIN + -- Drive referenced outputs + refclkdividerdprioout <= refclkdividerdprioout_xhdl4; + rxpcsdprioout <= rxpcsdprioout_xhdl5; + rxpmadprioout <= rxpmadprioout_xhdl6(1199 DOWNTO 0); + txpcsdprioout <= txpcsdprioout_xhdl7; + txpmadprioout <= txpmadprioout_xhdl8; + mdio_out <= mdio_out_xhdl3; + data_enable_n <= data_enable_n_xhdl2; + + -- primary input/output connections --------------------------------------- + + -- outputs + mdio_curr_st <= curr_state; -- from SM + + -- module instantiatations ------------------------------------------------ + + -- from top + + mdio_addr_1 : cycloneiv_hssi_cmu_dprio_addr + PORT MAP ( + reset => mdio_rst, + mdc => mdc, -- from top + mdio_in => mdio_in, -- from top + shift_addr => shift_addr, -- from sm + incr_addr => incr_addr, -- from sm + reg_addr => reg_addr -- To (16-bit reg addr) reg + ); + + + + mdio_cnt_1 : cycloneiv_hssi_cmu_dprio_cnt + PORT MAP ( + reset => mdio_rst, + mdc => mdc, + ld_cnt => ld_cnt, -- from sm + cnt_val => cnt_val, -- from sm + cnt_eq_0 => cnt_eq_0 -- to sm + ); + + + + mdio_sm_1 : cycloneiv_hssi_cmu_dprio_sm + PORT MAP ( + reset => mdio_rst, + mdio_in => mdio_in, -- from top + mdc => mdc, + opcode => opcode, -- from ctl_data + valid_addr => valid_addr, -- from ctl_data + cnt_eq_0 => cnt_eq_0, -- from cnt + shift_addr => shift_addr, -- to addr + incr_addr => incr_addr, -- to addr + mdio_wr => mdio_wr, -- to reg + mdio_rd => mdio_rd, -- to reg + shift_in => shift_in, -- to ctl_data + shift_out => shift_out, -- to ctl_data + latch_ctl => latch_ctl, -- to ctl_data + ld_data => ld_data, -- to ctl_data + valid_addr_lt => valid_addr_lt, -- to cnt_data + ld_cnt => ld_cnt, -- to cnt + cnt_val => cnt_val, -- to cnt (5-bit) + curr_state => curr_state -- to top + ); + + + + mdio_ctl_data_1 : cycloneiv_hssi_cmu_dprio_ctl_data + PORT MAP ( + reset => mdio_rst, + mdc => mdc, + mdio_in => mdio_in, + shift_in => shift_in, -- from sm + shift_out => shift_out, -- frm sm + ld_data => ld_data, -- from sm + latch_ctl => latch_ctl, -- from sm + port_addr => port_addr, + dev_addr => dev_addr, + valid_addr_lt => valid_addr_lt, -- from sm + mbus_out => mbus_out, -- from reg + mdio_out => mdio_out_xhdl3, -- to top + mbus_in => mbus_in, -- to reg + opcode => opcode, -- to sm + valid_addr => valid_addr, -- to sm + data_enable_n => data_enable_n_xhdl2 -- to top + ); + + -- -------------------------------------------------------------------- + -- Status registers and MBUS_OUT muxing for whole QUAD ---------------- + -- -------------------------------------------------------------------- + gnd_wire <= '0'; + vcc_wire <= '1'; + + dev_addr_0 <= dev_addr(0); + + + + status_reg : cycloneiv_hssi_cmu_dprio_status + PORT MAP ( + mdio_rst => mdio_rst, + mdio_rd => mdio_rd, + reg_addr => reg_addr, + dev_addr_0 => dev_addr(0), + mdc => mdc, + serial_mode => gnd_wire, + ser_shift_load => '0', + si => '0', + mbus_out_ch0 => mbus_out_ch0, + mbus_out_ch1 => mbus_out_ch1, + mbus_out_ch2 => mbus_out_ch2, + mbus_out_ch3 => mbus_out_ch3, + mbus_out_centrl => mbus_out_centrl, + align_status => align_status, + sync_status => sync_status, + xs_link_status => xs_link_status, + rx_local_fault => rx_local_fault, + tx_local_fault => tx_local_fault, + rxs_link_status_set => rxs_link_status_set, + rtx_rx_local_fault_clr => rtx_rx_local_fault_clr, + mbus_out => mbus_out, -- to ctrl_data + so => so_status + ); + + -- -------------------------------------------------------------------- + -- common ------------------------------------------------------------- + -- -------------------------------------------------------------------- + pma_cram_test <= '0'; + serial_mode <= '0'; + + -- -------------------------------------------------------------------- + -- cmu --------------------------------------------------------------- + -- -------------------------------------------------------------------- + si_centrl <= 'X'; + + md_reg_centrl : cycloneiv_hssi_cmu_dprio_centrl_top + PORT MAP ( + mdio_rst => mdio_rst, -- from top + mdio_wr => mdio_wr, -- from sm + reg_addr => reg_addr, -- from addr + mdc => mdc, -- from top + mbus_in => mbus_in, -- from ctrl_data + serial_mode => serial_mode, -- new: + mdio_dis => mdio_dis, -- from top + pma_cram_test => pma_cram_test, -- new: + -- .dprioload(dprioload), // from top + ser_shift_load => dprioload, -- from top + si => si_centrl, -- new + csr_centrl_in => csr_centrl_in, -- new + csr_centrl_in_reserved => csr_centrl_in_reserved, + -- .align_status (align_status), // moved to status_reg_ctrl + -- .sync_status (sync_status), // moved to status_reg_ctrl + -- .mdio_rd(mdio_rd), // moved to status_reg_ctrl + -- .dev_addr_0 (dev_addr_0), // moved to status_reg_ctrl + + dp_centrl_out => dp_centrl_out, -- to top + dp_centrl_out_reserved => dp_centrl_out_reserved, + + so => so_centrl, -- to ctrl_data + mbus_out => mbus_out_centrl -- to status_reg + ); + + -- -------------------------------------------------------------------- + -- channel ------------------------------------------------------------ + -- -------------------------------------------------------------------- + + dprio_chnl_id0 <= "0000"; + dprio_chnl_id1 <= "0001"; + dprio_chnl_id2 <= "0010"; + dprio_chnl_id3 <= "0011"; + + si_ch0 <= 'X'; + si_ch1 <= 'X'; + si_ch2 <= 'X'; + si_ch3 <= 'X'; + + md_reg_ch0 : cycloneiv_hssi_cmu_dprio_chnl_top + PORT MAP ( + mdio_rst => mdio_rst, -- from top + mdio_wr => mdio_wr, -- from sm + reg_addr => reg_addr, -- from addr + mdc => mdc, -- from top + mbus_in => mbus_in, -- from ctrl_data + serial_mode => serial_mode, -- new: + mdio_dis => mdio_dis, -- from top + pma_cram_test => pma_cram_test, -- new: + ser_shift_load => dprioload, -- from top + si => si_ch0, -- new + csr_chnl_in => csr_chnl_in_ch0, -- new + csr_chnl_in_reserved => csr_chnl_in_reserved_ch0, + dprio_chnl_id => dprio_chnl_id0, -- new - not in centrl + + dp_chnl_out => dp_chnl_out_ch0, -- to top + dp_chnl_out_reserved => dp_chnl_out_reserved_ch0, + so => so_ch0, -- to ctrl_data + mbus_out => mbus_out_ch0 -- to status_reg + ); + + + + md_reg_ch1 : cycloneiv_hssi_cmu_dprio_chnl_top + PORT MAP ( + mdio_rst => mdio_rst, -- from top + mdio_wr => mdio_wr, -- from sm + reg_addr => reg_addr, -- from addr + mdc => mdc, -- from top + mbus_in => mbus_in, -- from ctrl_data + serial_mode => serial_mode, -- new: + mdio_dis => mdio_dis, -- from top + pma_cram_test => pma_cram_test, -- new: + ser_shift_load => dprioload, -- from top + si => si_ch1, -- new + csr_chnl_in => csr_chnl_in_ch1, -- new + csr_chnl_in_reserved => csr_chnl_in_reserved_ch1, + dprio_chnl_id => dprio_chnl_id1, -- new - not in centrl + + dp_chnl_out => dp_chnl_out_ch1, -- to top + dp_chnl_out_reserved => dp_chnl_out_reserved_ch1, + so => so_ch1, -- to ctrl_data + mbus_out => mbus_out_ch1 -- to status_reg + ); + + + + md_reg_ch2 : cycloneiv_hssi_cmu_dprio_chnl_top + PORT MAP ( + mdio_rst => mdio_rst, -- from top + mdio_wr => mdio_wr, -- from sm + reg_addr => reg_addr, -- from addr + mdc => mdc, -- from top + mbus_in => mbus_in, -- from ctrl_data + serial_mode => serial_mode, -- new: + mdio_dis => mdio_dis, -- from top + pma_cram_test => pma_cram_test, -- new: + ser_shift_load => dprioload, -- from top + si => si_ch2, -- new + csr_chnl_in => csr_chnl_in_ch2, -- new + csr_chnl_in_reserved => csr_chnl_in_reserved_ch2, + dprio_chnl_id => dprio_chnl_id2, -- new - not in centrl + + dp_chnl_out => dp_chnl_out_ch2, -- to top + dp_chnl_out_reserved => dp_chnl_out_reserved_ch2, + so => so_ch2, -- to ctrl_data + mbus_out => mbus_out_ch2 -- to status_reg + ); + + + + md_reg_ch3 : cycloneiv_hssi_cmu_dprio_chnl_top + PORT MAP ( + mdio_rst => mdio_rst, -- from top + mdio_wr => mdio_wr, -- from sm + reg_addr => reg_addr, -- from addr + mdc => mdc, -- from top + mbus_in => mbus_in, -- from ctrl_data + serial_mode => serial_mode, -- new: + mdio_dis => mdio_dis, -- from top + pma_cram_test => pma_cram_test, -- new: + ser_shift_load => dprioload, -- from top + si => si_ch3, -- new + csr_chnl_in => csr_chnl_in_ch3, -- new + csr_chnl_in_reserved => csr_chnl_in_reserved_ch3, + dprio_chnl_id => dprio_chnl_id3, -- new - not in centrl + + dp_chnl_out => dp_chnl_out_ch3, -- to top + dp_chnl_out_reserved => dp_chnl_out_reserved_ch3, + so => so_ch3, -- to ctrl_data + mbus_out => mbus_out_ch3 -- to status_reg + ); + + -- -------------------------------------------------------------------- + -- DPRIO SW <--> ICD ------------------------------------------------- + -- -------------------------------------------------------------------- + + + m_map : cycloneiv_hssi_cmu_dprio_map + GENERIC MAP ( + clkdiv0_inclk0_logical_to_physical_mapping => clkdiv0_inclk0_logical_to_physical_mapping, + clkdiv0_inclk1_logical_to_physical_mapping => clkdiv0_inclk1_logical_to_physical_mapping, + clkdiv1_inclk0_logical_to_physical_mapping => clkdiv1_inclk0_logical_to_physical_mapping, + clkdiv1_inclk1_logical_to_physical_mapping => clkdiv1_inclk1_logical_to_physical_mapping, + clkdiv2_inclk0_logical_to_physical_mapping => clkdiv2_inclk0_logical_to_physical_mapping, + clkdiv2_inclk1_logical_to_physical_mapping => clkdiv2_inclk1_logical_to_physical_mapping, + clkdiv3_inclk0_logical_to_physical_mapping => clkdiv3_inclk0_logical_to_physical_mapping, + clkdiv3_inclk1_logical_to_physical_mapping => clkdiv3_inclk1_logical_to_physical_mapping, + clkdiv4_inclk0_logical_to_physical_mapping => clkdiv4_inclk0_logical_to_physical_mapping, + clkdiv4_inclk1_logical_to_physical_mapping => clkdiv4_inclk1_logical_to_physical_mapping, + clkdiv5_inclk0_logical_to_physical_mapping => clkdiv5_inclk0_logical_to_physical_mapping, + clkdiv5_inclk1_logical_to_physical_mapping => clkdiv5_inclk1_logical_to_physical_mapping, + + pll0_inclk0_logical_to_physical_mapping => pll0_inclk0_logical_to_physical_mapping, + pll0_inclk1_logical_to_physical_mapping => pll0_inclk1_logical_to_physical_mapping, + pll0_inclk2_logical_to_physical_mapping => pll0_inclk2_logical_to_physical_mapping, + pll0_inclk3_logical_to_physical_mapping => pll0_inclk3_logical_to_physical_mapping, + pll0_inclk4_logical_to_physical_mapping => pll0_inclk4_logical_to_physical_mapping, + pll0_inclk5_logical_to_physical_mapping => pll0_inclk5_logical_to_physical_mapping, + pll0_inclk6_logical_to_physical_mapping => pll0_inclk6_logical_to_physical_mapping, + pll0_inclk7_logical_to_physical_mapping => pll0_inclk7_logical_to_physical_mapping, + pll0_inclk8_logical_to_physical_mapping => pll0_inclk8_logical_to_physical_mapping, + pll0_inclk9_logical_to_physical_mapping => pll0_inclk9_logical_to_physical_mapping, + pll1_inclk0_logical_to_physical_mapping => pll1_inclk0_logical_to_physical_mapping, + pll1_inclk1_logical_to_physical_mapping => pll1_inclk1_logical_to_physical_mapping, + pll1_inclk2_logical_to_physical_mapping => pll1_inclk2_logical_to_physical_mapping, + pll1_inclk3_logical_to_physical_mapping => pll1_inclk3_logical_to_physical_mapping, + pll1_inclk4_logical_to_physical_mapping => pll1_inclk4_logical_to_physical_mapping, + pll1_inclk5_logical_to_physical_mapping => pll1_inclk5_logical_to_physical_mapping, + pll1_inclk6_logical_to_physical_mapping => pll1_inclk6_logical_to_physical_mapping, + pll1_inclk7_logical_to_physical_mapping => pll1_inclk7_logical_to_physical_mapping, + pll1_inclk8_logical_to_physical_mapping => pll1_inclk8_logical_to_physical_mapping, + pll1_inclk9_logical_to_physical_mapping => pll1_inclk9_logical_to_physical_mapping, + pll2_inclk0_logical_to_physical_mapping => pll2_inclk0_logical_to_physical_mapping, + pll2_inclk1_logical_to_physical_mapping => pll2_inclk1_logical_to_physical_mapping, + pll2_inclk2_logical_to_physical_mapping => pll2_inclk2_logical_to_physical_mapping, + pll2_inclk3_logical_to_physical_mapping => pll2_inclk3_logical_to_physical_mapping, + pll2_inclk4_logical_to_physical_mapping => pll2_inclk4_logical_to_physical_mapping, + pll2_inclk5_logical_to_physical_mapping => pll2_inclk5_logical_to_physical_mapping, + pll2_inclk6_logical_to_physical_mapping => pll2_inclk6_logical_to_physical_mapping, + pll2_inclk7_logical_to_physical_mapping => pll2_inclk7_logical_to_physical_mapping, + pll2_inclk8_logical_to_physical_mapping => pll2_inclk8_logical_to_physical_mapping, + pll2_inclk9_logical_to_physical_mapping => pll2_inclk9_logical_to_physical_mapping, + pll3_inclk0_logical_to_physical_mapping => pll3_inclk0_logical_to_physical_mapping, + pll3_inclk1_logical_to_physical_mapping => pll3_inclk1_logical_to_physical_mapping, + pll3_inclk2_logical_to_physical_mapping => pll3_inclk2_logical_to_physical_mapping, + pll3_inclk3_logical_to_physical_mapping => pll3_inclk3_logical_to_physical_mapping, + pll3_inclk4_logical_to_physical_mapping => pll3_inclk4_logical_to_physical_mapping, + pll3_inclk5_logical_to_physical_mapping => pll3_inclk5_logical_to_physical_mapping, + pll3_inclk6_logical_to_physical_mapping => pll3_inclk6_logical_to_physical_mapping, + pll3_inclk7_logical_to_physical_mapping => pll3_inclk7_logical_to_physical_mapping, + pll3_inclk8_logical_to_physical_mapping => pll3_inclk8_logical_to_physical_mapping, + pll3_inclk9_logical_to_physical_mapping => pll3_inclk9_logical_to_physical_mapping, + pll4_inclk0_logical_to_physical_mapping => pll4_inclk0_logical_to_physical_mapping, + pll4_inclk1_logical_to_physical_mapping => pll4_inclk1_logical_to_physical_mapping, + pll4_inclk2_logical_to_physical_mapping => pll4_inclk2_logical_to_physical_mapping, + pll4_inclk3_logical_to_physical_mapping => pll4_inclk3_logical_to_physical_mapping, + pll4_inclk4_logical_to_physical_mapping => pll4_inclk4_logical_to_physical_mapping, + pll4_inclk5_logical_to_physical_mapping => pll4_inclk5_logical_to_physical_mapping, + pll4_inclk6_logical_to_physical_mapping => pll4_inclk6_logical_to_physical_mapping, + pll4_inclk7_logical_to_physical_mapping => pll4_inclk7_logical_to_physical_mapping, + pll4_inclk8_logical_to_physical_mapping => pll4_inclk8_logical_to_physical_mapping, + pll4_inclk9_logical_to_physical_mapping => pll4_inclk9_logical_to_physical_mapping, + pll5_inclk0_logical_to_physical_mapping => pll5_inclk0_logical_to_physical_mapping, + pll5_inclk1_logical_to_physical_mapping => pll5_inclk1_logical_to_physical_mapping, + pll5_inclk2_logical_to_physical_mapping => pll5_inclk2_logical_to_physical_mapping, + pll5_inclk3_logical_to_physical_mapping => pll5_inclk3_logical_to_physical_mapping, + pll5_inclk4_logical_to_physical_mapping => pll5_inclk4_logical_to_physical_mapping, + pll5_inclk5_logical_to_physical_mapping => pll5_inclk5_logical_to_physical_mapping, + pll5_inclk6_logical_to_physical_mapping => pll5_inclk6_logical_to_physical_mapping, + pll5_inclk7_logical_to_physical_mapping => pll5_inclk7_logical_to_physical_mapping, + pll5_inclk8_logical_to_physical_mapping => pll5_inclk8_logical_to_physical_mapping, + pll5_inclk9_logical_to_physical_mapping => pll5_inclk9_logical_to_physical_mapping, + pll0_logical_to_physical_mapping => pll0_logical_to_physical_mapping, + pll1_logical_to_physical_mapping => pll1_logical_to_physical_mapping, + pll2_logical_to_physical_mapping => pll2_logical_to_physical_mapping, + pll3_logical_to_physical_mapping => pll3_logical_to_physical_mapping, + pll4_logical_to_physical_mapping => pll4_logical_to_physical_mapping, + pll5_logical_to_physical_mapping => pll5_logical_to_physical_mapping, + refclk_divider0_logical_to_physical_mapping => refclk_divider0_logical_to_physical_mapping, + refclk_divider1_logical_to_physical_mapping => refclk_divider1_logical_to_physical_mapping, + rx0_logical_to_physical_mapping => rx0_logical_to_physical_mapping, + rx1_logical_to_physical_mapping => rx1_logical_to_physical_mapping, + rx2_logical_to_physical_mapping => rx2_logical_to_physical_mapping, + rx3_logical_to_physical_mapping => rx3_logical_to_physical_mapping, + rx4_logical_to_physical_mapping => rx4_logical_to_physical_mapping, + rx5_logical_to_physical_mapping => rx5_logical_to_physical_mapping, + tx0_logical_to_physical_mapping => tx0_logical_to_physical_mapping, + tx1_logical_to_physical_mapping => tx1_logical_to_physical_mapping, + tx2_logical_to_physical_mapping => tx2_logical_to_physical_mapping, + tx3_logical_to_physical_mapping => tx3_logical_to_physical_mapping, + tx4_logical_to_physical_mapping => tx4_logical_to_physical_mapping, + tx5_logical_to_physical_mapping => tx5_logical_to_physical_mapping, + + tx0_pma_inclk0_logical_to_physical_mapping => tx0_pma_inclk0_logical_to_physical_mapping, + tx0_pma_inclk1_logical_to_physical_mapping => tx0_pma_inclk1_logical_to_physical_mapping, + tx0_pma_inclk2_logical_to_physical_mapping => tx0_pma_inclk2_logical_to_physical_mapping, + tx0_pma_inclk3_logical_to_physical_mapping => tx0_pma_inclk3_logical_to_physical_mapping, + tx0_pma_inclk4_logical_to_physical_mapping => tx0_pma_inclk4_logical_to_physical_mapping, + tx1_pma_inclk0_logical_to_physical_mapping => tx1_pma_inclk0_logical_to_physical_mapping, + tx1_pma_inclk1_logical_to_physical_mapping => tx1_pma_inclk1_logical_to_physical_mapping, + tx1_pma_inclk2_logical_to_physical_mapping => tx1_pma_inclk2_logical_to_physical_mapping, + tx1_pma_inclk3_logical_to_physical_mapping => tx1_pma_inclk3_logical_to_physical_mapping, + tx1_pma_inclk4_logical_to_physical_mapping => tx1_pma_inclk4_logical_to_physical_mapping, + tx2_pma_inclk0_logical_to_physical_mapping => tx2_pma_inclk0_logical_to_physical_mapping, + tx2_pma_inclk1_logical_to_physical_mapping => tx2_pma_inclk1_logical_to_physical_mapping, + tx2_pma_inclk2_logical_to_physical_mapping => tx2_pma_inclk2_logical_to_physical_mapping, + tx2_pma_inclk3_logical_to_physical_mapping => tx2_pma_inclk3_logical_to_physical_mapping, + tx2_pma_inclk4_logical_to_physical_mapping => tx2_pma_inclk4_logical_to_physical_mapping, + tx3_pma_inclk0_logical_to_physical_mapping => tx3_pma_inclk0_logical_to_physical_mapping, + tx3_pma_inclk1_logical_to_physical_mapping => tx3_pma_inclk1_logical_to_physical_mapping, + tx3_pma_inclk2_logical_to_physical_mapping => tx3_pma_inclk2_logical_to_physical_mapping, + tx3_pma_inclk3_logical_to_physical_mapping => tx3_pma_inclk3_logical_to_physical_mapping, + tx3_pma_inclk4_logical_to_physical_mapping => tx3_pma_inclk4_logical_to_physical_mapping, + tx4_pma_inclk0_logical_to_physical_mapping => tx4_pma_inclk0_logical_to_physical_mapping, + tx4_pma_inclk1_logical_to_physical_mapping => tx4_pma_inclk1_logical_to_physical_mapping, + tx4_pma_inclk2_logical_to_physical_mapping => tx4_pma_inclk2_logical_to_physical_mapping, + tx4_pma_inclk3_logical_to_physical_mapping => tx4_pma_inclk3_logical_to_physical_mapping, + tx4_pma_inclk4_logical_to_physical_mapping => tx4_pma_inclk4_logical_to_physical_mapping, + tx5_pma_inclk0_logical_to_physical_mapping => tx5_pma_inclk0_logical_to_physical_mapping, + tx5_pma_inclk1_logical_to_physical_mapping => tx5_pma_inclk1_logical_to_physical_mapping, + tx5_pma_inclk2_logical_to_physical_mapping => tx5_pma_inclk2_logical_to_physical_mapping, + tx5_pma_inclk3_logical_to_physical_mapping => tx5_pma_inclk3_logical_to_physical_mapping, + tx5_pma_inclk4_logical_to_physical_mapping => tx5_pma_inclk4_logical_to_physical_mapping, + + sim_dump_dprio_internal_reg_at_time => sim_dump_dprio_internal_reg_at_time, + sim_dump_filename => sim_dump_filename + ) + + PORT MAP ( + + cmudividerdprioin => cmudividerdprioin_int, + cmuplldprioin => cmuplldprioin_int, + refclkdividerdprioin => refclkdividerdprioin, + rxpcsdprioin => rxpcsdprioin, + rxpmadprioin => rxpmadprioin, + txpcsdprioin => txpcsdprioin, + txpmadprioin => txpmadprioin, + + ch0_dp_chnl_out => dp_chnl_out_ch0, + ch1_dp_chnl_out => dp_chnl_out_ch1, + ch2_dp_chnl_out => dp_chnl_out_ch2, + ch3_dp_chnl_out => dp_chnl_out_ch3, + ch0_dp_chnl_out_reserved => dp_chnl_out_reserved_ch0, + ch1_dp_chnl_out_reserved => dp_chnl_out_reserved_ch1, + ch2_dp_chnl_out_reserved => dp_chnl_out_reserved_ch2, + ch3_dp_chnl_out_reserved => dp_chnl_out_reserved_ch3, + dp_centrl_out => dp_centrl_out, + dp_centrl_out_reserved => dp_centrl_out_reserved, + + ch0_csr_chnl_in => csr_chnl_in_ch0, + ch1_csr_chnl_in => csr_chnl_in_ch1, + ch2_csr_chnl_in => csr_chnl_in_ch2, + ch3_csr_chnl_in => csr_chnl_in_ch3, + ch0_csr_chnl_in_reserved => csr_chnl_in_reserved_ch0, + ch1_csr_chnl_in_reserved => csr_chnl_in_reserved_ch1, + ch2_csr_chnl_in_reserved => csr_chnl_in_reserved_ch2, + ch3_csr_chnl_in_reserved => csr_chnl_in_reserved_ch3, + csr_centrl_in => csr_centrl_in, + csr_centrl_in_reserved => csr_centrl_in_reserved, + + cmudividerdprioout => cmudividerdprioout_xhdl0, + cmuplldprioout => cmuplldprioout_xhdl1, + refclkdividerdprioout => refclkdividerdprioout_xhdl4, + rxpcsdprioout => rxpcsdprioout_xhdl5, + rxpmadprioout => rxpmadprioout_xhdl6, + txpcsdprioout => txpcsdprioout_xhdl7, + txpmadprioout => txpmadprioout_xhdl8 + ); + +END trans; + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_hssi_components.all; + +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +ENTITY cycloneiv_hssi_cmu IS + GENERIC ( + + -- generic control parameters -- + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + + -- tipd :interconnect path delays -- + tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01; + tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txclk : VitalDelayType01 := DefpropDelay01; + tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_scanclk : VitalDelayType01 := DefpropDelay01; + --tipd_rateswitchdonein : VitalDelayType01 := DefpropDelay01; + tipd_rdenablesync : VitalDelayType01 := DefpropDelay01; + tipd_dpclk : VitalDelayType01 := DefpropDelay01; + tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01); + --tipd_txpllreset : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + --tipd_refclkdividerdprioin : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dprioin : VitalDelayType01 := DefpropDelay01; + --tipd_rateswitch : VitalDelayType01 := DefpropDelay01; + tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); + --tipd_rxclk : VitalDelayType01 := DefpropDelay01; + tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01; + tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01; + tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_scanmode : VitalDelayType01 := DefpropDelay01; + tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01; + --tipd_cmuplldprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_txcoreclk : VitalDelayType01 := DefpropDelay01; + tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01); + --tipd_cmudividerdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01; + tipd_dprioload : VitalDelayType01 := DefpropDelay01; + --tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_quadreset : VitalDelayType01 := DefpropDelay01; + tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01; + tipd_scanshift : VitalDelayType01 := DefpropDelay01; + tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_recovclk : VitalDelayType01 := DefpropDelay01; + tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); + + -- TSU/TH section + tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + + -- TCO section + tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01; + + lpm_type : STRING := "cycloneiv_hssi_cmu"; + --analog_test_bus_enable : STRING := "false"; + auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0; + auto_spd_phystatus_notify_count : INTEGER := 0; + --bonded_quad_mode : STRING := "none"; + --bypass_bandgap : STRING := "false"; + --central_test_bus_select : INTEGER := 0; + --cmu_type : STRING := "regular"; + coreclk_out_gated_by_quad_reset : STRING := "false"; -- cycloneiv_new + devaddr : INTEGER := 1; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + in_xaui_mode : STRING := "false"; + --migrated_from_prev_family : STRING := "false"; + --num_con_align_chars_for_align : INTEGER := 4; + --num_con_errors_for_align_loss : INTEGER := 2; + --num_con_good_data_for_align_approach : INTEGER := 3; + --offset_all_errors_align : STRING := "false"; + pipe_auto_speed_nego_enable : STRING := "false"; + --pipe_freq_scale_mode : STRING := "Data width"; + --pma_done_count : INTEGER := 0; + portaddr : INTEGER := 1; + --rx0_auto_spd_self_switch_enable : STRING := "false"; + rx0_channel_bonding : STRING := "none"; + rx0_clk1_mux_select : STRING := "recovered clock"; + rx0_clk2_mux_select : STRING := "recovered clock"; + rx0_clk_pd_enable : STRING := "false"; + rx0_ph_fifo_reg_mode : STRING := "false"; + rx0_ph_fifo_reset_enable : STRING := "false"; + rx0_ph_fifo_user_ctrl_enable : STRING := "false"; + --rx0_phfifo_wait_cnt : INTEGER := 0; + rx0_rd_clk_mux_select : STRING := "int clock"; + rx0_recovered_clk_mux_select : STRING := "recovered clock"; + rx0_reset_clock_output_during_digital_reset : STRING := "false"; + rx0_use_double_data_mode : STRING := "false"; + --rx_master_direction : STRING := "none"; + rx_xaui_sm_backward_compatible_enable : STRING := "false"; + select_refclk_dig : STRING := "false"; -- cycloneiv_new + --test_mode : STRING := "false"; + --tx0_auto_spd_self_switch_enable : STRING := "false"; + tx0_channel_bonding : STRING := "none"; + tx0_clk_pd_enable : STRING := "false"; + --tx0_ph_fifo_reg_mode : STRING := "false"; + tx0_ph_fifo_reset_enable : STRING := "false"; + tx0_ph_fifo_user_ctrl_enable : STRING := "false"; + tx0_rd_clk_mux_select : STRING := "int clock"; + tx0_reset_clock_output_during_digital_reset : STRING := "false"; + tx0_use_double_data_mode : STRING := "false"; + tx0_wr_clk_mux_select : STRING := "int_clk"; + --tx_master_direction : STRING := "none"; + --tx_pll0_used_as_rx_cdr : STRING := "false"; + --tx_pll1_used_as_rx_cdr : STRING := "false"; + tx_xaui_sm_backward_compatible_enable : STRING := "false"; + use_coreclk_out_post_divider : STRING := "false"; -- cycloneiv_new + use_deskew_fifo : STRING := "false"; + --vcceh_voltage : STRING := "3.0V"; + --vcceh_voltage_user_specified_auto : STRING := "true"; + --protocol_hint : STRING := "basic"; + rx_logical_to_physical_mapping : INTEGER := 0; + tx_logical_to_physical_mapping : INTEGER := 0; + pll_logical_to_physical_mapping : INTEGER := 0; + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + + -- Simulation Only + + sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps + sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs + ); + PORT ( + adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + --cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0'); + --cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0'); + dpclk : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC := '0'; + dprioload : IN STD_LOGIC := '0'; + -- extra10gin : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (others => '0'); + fixedclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + --lccmurtestbussel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + nonuserfromcal : IN STD_LOGIC := '0'; + pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47 + quadreset : IN STD_LOGIC := '0'; + --rateswitch : IN STD_LOGIC := '0'; + --rateswitchdonein : IN STD_LOGIC := '0'; + rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rdenablesync : IN STD_LOGIC := '0'; + recovclk : IN STD_LOGIC := '0'; + refclkdig : IN STD_LOGIC := '0'; -- cycloneiv_new + --refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + rxanalogreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + --rxclk : IN STD_LOGIC := '0'; + rxcoreclk : IN STD_LOGIC := '0'; + rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0'); + rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0'); + rxphfifordenable : IN STD_LOGIC := '0'; + rxphfiforeset : IN STD_LOGIC := '0'; + rxphfifowrdisable : IN STD_LOGIC := '0'; + rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0'); + rxpowerdown : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + scanclk : IN STD_LOGIC := '0'; + --scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (others => '0'); + scanmode : IN STD_LOGIC := '0'; + scanshift : IN STD_LOGIC := '0'; + syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + testin : IN STD_LOGIC_VECTOR(1999 DOWNTO 0) := (others => '0'); + txclk : IN STD_LOGIC := '0'; + txcoreclk : IN STD_LOGIC := '0'; + txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0'); + txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0'); + txphfiforddisable : IN STD_LOGIC := '0'; + txphfiforeset : IN STD_LOGIC := '0'; + txphfifowrenable : IN STD_LOGIC := '0'; + --txpllreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0'); + + alignstatus : OUT STD_LOGIC; + --autospdx4configsel : OUT STD_LOGIC; + --autospdx4rateswitchout : OUT STD_LOGIC; + --autospdx4spdchg : OUT STD_LOGIC; + --clkdivpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + --cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + --cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0); + coreclkout : OUT STD_LOGIC; -- stnngray_new + digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + dpriodisableout : OUT STD_LOGIC; + dpriooe : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC; + enabledeskew : OUT STD_LOGIC; + --extra10gout : OUT STD_LOGIC; + fiforesetrd : OUT STD_LOGIC; + --lccmutestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + --phfifiox4ptrsreset : OUT STD_LOGIC; + --pllpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + --pllresetout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + quadresetout : OUT STD_LOGIC; + --refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + refclkout : OUT STD_LOGIC; -- cycloneiv_new + --rxadcepowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + --rxadceresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxcrupowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + --rxcruresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxibpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxphfifox4byteselout : OUT STD_LOGIC; + rxphfifox4wrclkout : OUT STD_LOGIC; + rxphfifox4rdenableout : OUT STD_LOGIC; + rxphfifox4wrenableout : OUT STD_LOGIC; + rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + --scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0); + testout : OUT STD_LOGIC_VECTOR(2399 DOWNTO 0); + txanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txdividerpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txobpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + txphfifox4byteselout : OUT STD_LOGIC; + txphfifox4rdclkout : OUT STD_LOGIC; + txphfifox4rdenableout : OUT STD_LOGIC; + txphfifox4wrenableout : OUT STD_LOGIC; + txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0) + ); +END cycloneiv_hssi_cmu; + +ARCHITECTURE trans OF cycloneiv_hssi_cmu IS + + signal txphfiforddisable_ipd :STD_LOGIC; + signal txctrl_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal rxdatain_ipd :STD_LOGIC_VECTOR(31 DOWNTO 0); + signal txclk_ipd :STD_LOGIC; + signal syncstatus_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal rxpcsdprioin_ipd :STD_LOGIC_VECTOR(1599 DOWNTO 0); + signal txdigitalreset_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal txdatain_ipd :STD_LOGIC_VECTOR(31 DOWNTO 0); + signal scanclk_ipd :STD_LOGIC; + signal rdenablesync_ipd :STD_LOGIC; + signal dpclk_ipd :STD_LOGIC; + signal rxphfiforeset_ipd :STD_LOGIC; + signal testin_ipd :STD_LOGIC_VECTOR(9999 DOWNTO 0); + signal rxrunningdisp_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal rxdatavalid_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal txpcsdprioin_ipd :STD_LOGIC_VECTOR(599 DOWNTO 0); + signal dprioin_ipd :STD_LOGIC; + signal rxctrl_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal rxanalogreset_ipd :STD_LOGIC_VECTOR(5 DOWNTO 0); + signal txphfifowrenable_ipd :STD_LOGIC; + signal rxphfifowrdisable_ipd :STD_LOGIC; + signal rdalign_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal fixedclk_ipd :STD_LOGIC_VECTOR(5 DOWNTO 0); + signal dpriodisable_ipd :STD_LOGIC; + signal scanmode_ipd :STD_LOGIC; + signal rxphfifordenable_ipd :STD_LOGIC; + signal txphfiforeset_ipd :STD_LOGIC; + signal txcoreclk_ipd :STD_LOGIC; + signal adet_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal rxdigitalreset_ipd :STD_LOGIC_VECTOR(3 DOWNTO 0); + signal rxpmadprioin_ipd :STD_LOGIC_VECTOR(1799 DOWNTO 0); + signal rxcoreclk_ipd :STD_LOGIC; + signal dprioload_ipd :STD_LOGIC; + signal quadreset_ipd :STD_LOGIC; + signal nonuserfromcal_ipd :STD_LOGIC; + signal scanshift_ipd :STD_LOGIC; + signal txpmadprioin_ipd :STD_LOGIC_VECTOR(1799 DOWNTO 0); + signal recovclk_ipd :STD_LOGIC; + signal rxpowerdown_ipd :STD_LOGIC_VECTOR(5 DOWNTO 0); +-- -------------------------------------------------------------------------- +-- parameters in TgX but not in cycloneiv ------------------------------------ +-- --- make them local with fixed value so maximally reuse TgX code - +-- to not modifying internal codes - +-- -------------------------------------------------------------------------- + CONSTANT analog_test_bus_enable : STRING := "false"; + CONSTANT bonded_quad_mode : STRING := "none"; + CONSTANT bypass_bandgap : STRING := "false"; + CONSTANT central_test_bus_select : INTEGER := 0; + CONSTANT cmu_type : STRING := "regular"; + CONSTANT migrated_from_prev_family : STRING := "false"; + CONSTANT num_con_align_chars_for_align : INTEGER := 4; + CONSTANT num_con_errors_for_align_loss : INTEGER := 2; + CONSTANT num_con_good_data_for_align_approach : INTEGER := 3; + CONSTANT offset_all_errors_align : STRING := "false"; + CONSTANT pipe_freq_scale_mode : STRING := "Data width"; + CONSTANT pma_done_count : INTEGER := 0; + CONSTANT rx0_auto_spd_self_switch_enable : STRING := "false"; + CONSTANT rx0_phfifo_wait_cnt : INTEGER := 0; + CONSTANT rx_master_direction : STRING := "none"; + CONSTANT test_mode : STRING := "false"; + CONSTANT tx0_auto_spd_self_switch_enable : STRING := "false"; + CONSTANT tx0_ph_fifo_reg_mode : STRING := "false"; + CONSTANT tx_master_direction : STRING := "none"; + CONSTANT tx_pll0_used_as_rx_cdr : STRING := "false"; + CONSTANT tx_pll1_used_as_rx_cdr : STRING := "false"; + CONSTANT vcceh_voltage : STRING := "3.0V"; + CONSTANT vcceh_voltage_user_specified_auto : STRING := "true"; + CONSTANT protocol_hint : STRING := "basic"; + + +-- -------------------------------------------------------------------------- +-- Input ports in TgX but not in cycloneiv ----------------------------------- +-- --- make them wire with fixed value so maximally reuse TgX code - +-- to not modifying internal codes - +-- -------------------------------------------------------------------------- + + SIGNAL cmudividerdprioin : STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0'); + SIGNAL cmuplldprioin : STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0'); + SIGNAL extra10gin : STD_LOGIC_VECTOR(6 DOWNTO 0) := (others => '0'); + SIGNAL lccmurtestbussel : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + SIGNAL rateswitch : STD_LOGIC := '0'; + SIGNAL rateswitchdonein : STD_LOGIC := '0'; + SIGNAL refclkdividerdprioin : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + SIGNAL rxclk : STD_LOGIC := '0'; + SIGNAL scanin : STD_LOGIC_VECTOR(22 DOWNTO 0) := (others => '0'); + SIGNAL txpllreset : STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + + +-- -------------------------------------------------------------------------- +-- Output ports in TgX but not in cycloneiv ---------------------------------- +-- --- make them wire to maximally reuse TgX code - +-- to not modifying internal codes - +-- -------------------------------------------------------------------------- + + SIGNAL autospdx4configsel : STD_LOGIC; + SIGNAL autospdx4rateswitchout : STD_LOGIC; + SIGNAL autospdx4spdchg : STD_LOGIC; + SIGNAL clkdivpowerdn : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cmudividerdprioout : STD_LOGIC_VECTOR(599 DOWNTO 0); + SIGNAL cmuplldprioout : STD_LOGIC_VECTOR(1799 DOWNTO 0); + SIGNAL extra10gout : STD_LOGIC; + SIGNAL lccmutestbus : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL phfifiox4ptrsreset : STD_LOGIC; + SIGNAL pllpowerdn : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL pllresetout : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL refclkdividerdprioout : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rxadcepowerdown : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxadceresetout : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxcruresetout : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL scanout : STD_LOGIC_VECTOR(22 DOWNTO 0); + +-- -------------------------------------------------------------------------- +-- Ports width mismatches between TgX and Cyclone IV GX -------------------------- +-- --- have to modify internal code - +-- -------------------------------------------------------------------------- +-- +-- port_dir port_name TgX_width Cyclone IV GX_width note +-- -------------------------------------------------------------------------- +-- in fixedclk 6 4 +-- in rxanalogreset 6 4 +-- in rxpowerdown 6 4 +-- +-- out rxanalogresetout 6 4 +-- out rxibpowerdown 6 4 +-- out txanalogresetout 6 4 +-- out txdetectrxpowerdown 6 4 +-- out txobpowerdown 6 4 + +-- -------------------------------------------------------------------------- +-- Cyclone IV GX specific ------------------------------------------------------- - +-- -------------------------------------------------------------------------- + +SIGNAL coreclkout_div2_clkin : STD_LOGIC := '0'; +SIGNAL coreclkout_div2_clkout : STD_LOGIC := '0'; +SIGNAL coreclkout_div2_reset : STD_LOGIC := '0'; +SIGNAL refclkout_tmp : STD_LOGIC := '0'; + +-- -------------------------------------------------------------------------- +-- Behavior TgX model starting here ----------------------------------------- +-- -------------------------------------------------------------------------- + + COMPONENT cycloneiv_hssi_dskw_sm + PORT ( + soft_reset : IN STD_LOGIC; + clk_1 : IN STD_LOGIC; + octal_mode : IN STD_LOGIC; + align_det_sync : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rd_align : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + sync_status : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + align_status : OUT STD_LOGIC; + enable_deskew : OUT STD_LOGIC; + fifo_reset_rd : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_chnl_reset + PORT ( + hard_reset : IN STD_LOGIC; + soft_reset_all_hssi : IN STD_LOGIC; + rreset : IN STD_LOGIC; + rpowerdown : IN STD_LOGIC; + rxurstpma : IN STD_LOGIC; + rxurstpcs : IN STD_LOGIC; + txurstpcs : IN STD_LOGIC; + rpowdnr : IN STD_LOGIC; + rpowdnt : IN STD_LOGIC; + rrxurstpcs : IN STD_LOGIC; + rtxurstpcs : IN STD_LOGIC; + rrxurstpma : IN STD_LOGIC; + rrx_cru_rst : IN STD_LOGIC; + radce_rst : IN STD_LOGIC; + urx_pdb : IN STD_LOGIC; + rurx_pdb : IN STD_LOGIC; + radce_pdb : IN STD_LOGIC; + rrx_ib_pdb : IN STD_LOGIC; + rtx_ob_pdb : IN STD_LOGIC; + rtx_cgb_pdb : IN STD_LOGIC; + rrx_cru_pdb : IN STD_LOGIC; + rtx_pipe_en : IN STD_LOGIC; + p0_state : IN STD_LOGIC; + p0s_state : IN STD_LOGIC; + p2_state : IN STD_LOGIC; + rxpma_rstb : OUT STD_LOGIC; + txpma_rstb : OUT STD_LOGIC; + rxpcs_rst : OUT STD_LOGIC; + txpcs_rst : OUT STD_LOGIC; + cru_rstb : OUT STD_LOGIC; + adce_rstb : OUT STD_LOGIC; + adce_pdb : OUT STD_LOGIC; + cru_pdb : OUT STD_LOGIC; + rx_pdb : OUT STD_LOGIC; + tx_pdb : OUT STD_LOGIC; + cgb_pdb : OUT STD_LOGIC; + rx_det_pdb : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_rxclk_ctl + PORT ( + pld_rx_clk : IN STD_LOGIC; + rcvd_clk_pma : IN STD_LOGIC; + rcvd_clk0_pma : IN STD_LOGIC; + tx_pma_clk : IN STD_LOGIC; + refclk_pma : IN STD_LOGIC; + fref : IN STD_LOGIC; + clklow : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + rx_div2_sync_centrl : IN STD_LOGIC; + rx_div2_sync_quad_up : IN STD_LOGIC; + rx_div2_sync_quad_down : IN STD_LOGIC; + rrcvd_clk_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_1_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_2_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrx_rd_clk_sel : IN STD_LOGIC; + rxrst : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rdwidth_rx : IN STD_LOGIC; + rfreerun_rx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rrxpcsclkpwdn : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rself_sw_en_rx : IN STD_LOGIC; + fref_muxed : OUT STD_LOGIC; + clklow_muxed : OUT STD_LOGIC; + rcvd_clk : OUT STD_LOGIC; + clk_1_b : OUT STD_LOGIC; + clk_2_b : OUT STD_LOGIC; + rx_wr_clk : OUT STD_LOGIC; + rx_rd_clk : OUT STD_LOGIC; + rx_clk : OUT STD_LOGIC; + rcvd_clk_pma_b : OUT STD_LOGIC; + clk_2_b_raw : OUT STD_LOGIC; + rx_wr_clk_raw : OUT STD_LOGIC; + rx_rd_clk_raw : OUT STD_LOGIC; + rx_div2_sync_out : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_rcv_sm + PORT ( + clk_2 : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + indv : IN STD_LOGIC; + dec_data_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dec_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + dec_ctl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + running_disp : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_local_fault_clr : IN STD_LOGIC; + xs_link_status_set : IN STD_LOGIC; + tx_local_fault_det : IN STD_LOGIC; + rxaui_s2gx_en : IN STD_LOGIC; + rx_data_rs : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rx_ctl_rs : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_local_fault : OUT STD_LOGIC; + xs_link_status : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_txclk_ctl + PORT ( + pld_tx_clk : IN STD_LOGIC; + refclk_pma : IN STD_LOGIC; + txpma_local_clk : IN STD_LOGIC; + txrst : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC; + tx_div2_sync_centrl : IN STD_LOGIC; + tx_div2_sync_quad_up : IN STD_LOGIC; + tx_div2_sync_quad_down : IN STD_LOGIC; + rindv_tx : IN STD_LOGIC; + rtxwrclksel : IN STD_LOGIC; + rtxrdclksel : IN STD_LOGIC; + rdwidth_tx : IN STD_LOGIC; + rfreerun_tx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + rtxpcsclkpwdn : IN STD_LOGIC; + rmaster_tx : IN STD_LOGIC; + rmaster_up_tx : IN STD_LOGIC; + rself_sw_en_tx : IN STD_LOGIC; + refclk_b : OUT STD_LOGIC; + wr_clk_pos : OUT STD_LOGIC; + fifo_rd_clk : OUT STD_LOGIC; + tx_clk_out : OUT STD_LOGIC; + refclk_b_raw : OUT STD_LOGIC; + wr_clk_pos_raw : OUT STD_LOGIC; + fifo_rd_clk_raw : OUT STD_LOGIC; + tx_div2_sync_out : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_auto_speed_neg + GENERIC ( + WAIT_RATE_CHANGE : INTEGER := 0; + WAIT_FOR_PHFIFO : INTEGER := 1; + DISABLE_PC_BYTE : INTEGER := 2; + SET_CONFIG_SEL : INTEGER := 3; + WAIT_GEN2NGEN1_CHANGE : INTEGER := 4; + WAIT_PMA_DONE_CNTR : INTEGER := 5; + DEASSERT_PC_PTR_RESET : INTEGER := 6; + WAIT_DEASSERT_RST_CNTR : INTEGER := 7; + ENABLE_PC_BYTE : INTEGER := 8; + WAIT_ENABLE_CNTR : INTEGER := 9; + SPEED_CHANGE_DONE : INTEGER := 10 + ); + PORT ( + refclk : IN STD_LOGIC; + rxpcs_rst_int : IN STD_LOGIC; + rate : IN STD_LOGIC; + gen2ngen1 : IN STD_LOGIC; + config_sel_centrl : IN STD_LOGIC; + config_sel_quad_up : IN STD_LOGIC; + config_sel_quad_down : IN STD_LOGIC; + rindv_rx : IN STD_LOGIC; + rmaster_rx : IN STD_LOGIC; + rmaster_up_rx : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + singleorbundle : IN STD_LOGIC; + rphfifo_regmode_rx : IN STD_LOGIC; + rpma_done_count : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + rauto_deassert_pc_rst_cnt : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rauto_pc_en_cnt : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rwait_for_phfifo_cnt : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + config_sel : OUT STD_LOGIC; + pcie_switch : OUT STD_LOGIC; + speed_change : OUT STD_LOGIC; + dis_pc_byte : OUT STD_LOGIC; + reset_pc_ptrs : OUT STD_LOGIC; + cs : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_dprio_top + GENERIC ( + -- Simulation Only + clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1"; + clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0"; + clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1"; + + pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll0_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll0_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll0_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll0_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll0_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll0_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll1_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll1_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll1_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll1_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll1_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll1_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll2_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll2_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll2_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll2_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll2_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll2_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll3_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll3_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll3_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll3_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll3_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll3_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll4_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll4_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll4_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll4_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll4_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll4_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0"; + pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1"; + pll5_inclk2_logical_to_physical_mapping : STRING := "iq2"; + pll5_inclk3_logical_to_physical_mapping : STRING := "iq3"; + pll5_inclk4_logical_to_physical_mapping : STRING := "iq4"; + pll5_inclk5_logical_to_physical_mapping : STRING := "iq5"; + pll5_inclk6_logical_to_physical_mapping : STRING := "iq6"; + pll5_inclk7_logical_to_physical_mapping : STRING := "iq7"; + pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk"; + pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk"; + + pll0_logical_to_physical_mapping : INTEGER := 0; + pll1_logical_to_physical_mapping : INTEGER := 1; + pll2_logical_to_physical_mapping : INTEGER := 2; + pll3_logical_to_physical_mapping : INTEGER := 3; + pll4_logical_to_physical_mapping : INTEGER := 4; + pll5_logical_to_physical_mapping : INTEGER := 5; + + refclk_divider0_logical_to_physical_mapping : INTEGER := 0; + refclk_divider1_logical_to_physical_mapping : INTEGER := 1; + + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + rx4_logical_to_physical_mapping : INTEGER := 4; + rx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + tx4_logical_to_physical_mapping : INTEGER := 4; + tx5_logical_to_physical_mapping : INTEGER := 5; + + tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1"; + tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4"; + tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top"; + tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom"; + tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport"; + + sim_dump_dprio_internal_reg_at_time : INTEGER := 0; + sim_dump_filename : STRING := "sim_dprio_dump.txt" + ); + PORT ( + sync_status : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + align_status : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + mdc : IN STD_LOGIC; + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + mdio_dis : IN STD_LOGIC; + dprioload : IN STD_LOGIC; + mdio_rst : IN STD_LOGIC; + refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0); + refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + mdio_out : OUT STD_LOGIC; + data_enable_n : OUT STD_LOGIC; + mdio_curr_st : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_clk_ctl + PORT ( + pclk_pma : IN STD_LOGIC; + refclk_dig : IN STD_LOGIC; + mdc : IN STD_LOGIC; + ser_clk : IN STD_LOGIC; + ser_mode : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + scan_clk : IN STD_LOGIC; + rfreerun_centrl : IN STD_LOGIC; + rcentrl_clk_sel : IN STD_LOGIC; + rrefclk_out_div2 : IN STD_LOGIC; + hard_reset : IN STD_LOGIC; + txrst : IN STD_LOGIC; + refclk_pma_out : OUT STD_LOGIC; + mdc_b : OUT STD_LOGIC; + refclk_out : OUT STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rfreq_sel : IN STD_LOGIC; + gen2ngen1_bundle : IN STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_tx_sm + PORT ( + tx_clk : IN STD_LOGIC; + soft_reset : IN STD_LOGIC; + tx_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + tx_ctl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_local_fault_clr : IN STD_LOGIC; + indv : IN STD_LOGIC; + rd_enable_sync : IN STD_LOGIC; + rxaui_s2gx_en : IN STD_LOGIC; + sm_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + sm_ctl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_local_fault_det : OUT STD_LOGIC; + tx_local_fault : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_rx_ctrl + PORT ( + soft_reset : IN STD_LOGIC; + clk_2 : IN STD_LOGIC; + rx_rd_clk : IN STD_LOGIC; + rx_wr_clk : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rrxfifo_urst_en : IN STD_LOGIC; + rxfifo_urst : IN STD_LOGIC; + rrxphfifopldctl_en : IN STD_LOGIC; + pld_wr_dis : IN STD_LOGIC; + pld_re : IN STD_LOGIC; + dis_pc_byte : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + rx_we_out : OUT STD_LOGIC; + wr_enable_out : OUT STD_LOGIC; + rd_enable_out : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_quad_reset + PORT ( + entest : IN STD_LOGIC; + plniotri : IN STD_LOGIC; + npor : IN STD_LOGIC; + frzreg : IN STD_LOGIC; + pllurst : IN STD_LOGIC; + rpllurst : IN STD_LOGIC; + rpowerdown : IN STD_LOGIC; + rreset : IN STD_LOGIC; + rxurstcmu : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrxurstcmu : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rrx_cmu_rst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ucmurx_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rclk_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_powdnr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_cru_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_urx_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_rx_ib_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_powdnt : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_tx_ob_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_tx_cgb_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + rcmu_rx_det_pdb : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + cmu0_rxpma_rstb : OUT STD_LOGIC; + cmu0_txpma_rstb : OUT STD_LOGIC; + cmu0_cru_rstb : OUT STD_LOGIC; + cmu1_rxpma_rstb : OUT STD_LOGIC; + cmu1_txpma_rstb : OUT STD_LOGIC; + cmu1_cru_rstb : OUT STD_LOGIC; + cmu0_rx_pdb : OUT STD_LOGIC; + cmu0_cru_pdb : OUT STD_LOGIC; + cmu0_clk_pdb : OUT STD_LOGIC; + cmu0_tx_pdb : OUT STD_LOGIC; + cmu0_cgb_pdb : OUT STD_LOGIC; + cmu0_rx_det_pdb : OUT STD_LOGIC; + cmu1_rx_pdb : OUT STD_LOGIC; + cmu1_cru_pdb : OUT STD_LOGIC; + cmu1_clk_pdb : OUT STD_LOGIC; + cmu1_tx_pdb : OUT STD_LOGIC; + cmu1_cgb_pdb : OUT STD_LOGIC; + cmu1_rx_det_pdb : OUT STD_LOGIC; + mdio_rst : OUT STD_LOGIC; + hard_reset : OUT STD_LOGIC; + soft_reset_all_hssi : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_hssi_cmu_tx_ctrl + PORT ( + soft_reset : IN STD_LOGIC; + fifo_wr_clk : IN STD_LOGIC; + fifo_rd_clk : IN STD_LOGIC; + refclk_b_in : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + rtxfifo_urst_en : IN STD_LOGIC; + txfifo_urst : IN STD_LOGIC; + rtxphfifopldctl_en : IN STD_LOGIC; + pld_we : IN STD_LOGIC; + pld_rd_dis : IN STD_LOGIC; + dis_pc_byte : IN STD_LOGIC; + rauto_speed_ena : IN STD_LOGIC; + wr_enable_out : OUT STD_LOGIC; + rd_enable_out : OUT STD_LOGIC; + fifo_select_out : OUT STD_LOGIC + ); + END COMPONENT; + + --///////////////////////////////////////////////////////////////////////// + -- const wire ---------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + SIGNAL vcc_wire : STD_LOGIC; + SIGNAL gnd_wire : STD_LOGIC; + SIGNAL dummy_wire : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- optimization -------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + SIGNAL init_in_xaui_mode : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- ww47 new CRAMs ------------------------------------------------------ // + --///////////////////////////////////////////////////////////////////////// + SIGNAL init_rauto_deassert_pc_rst_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL init_rauto_pc_en_cnt : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_rauto_speed_ena : STD_LOGIC; + SIGNAL init_rclk_1_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rclk_2_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rdwidth_rx : STD_LOGIC; + SIGNAL init_rdwidth_tx : STD_LOGIC; + SIGNAL init_rfreerun_rx : STD_LOGIC; + SIGNAL init_rfreerun_tx : STD_LOGIC; + SIGNAL init_rfreq_sel : STD_LOGIC; + SIGNAL init_rindv_rx : STD_LOGIC; + SIGNAL init_rindv_tx : STD_LOGIC; + SIGNAL init_rmaster_rx : STD_LOGIC; + SIGNAL init_rmaster_tx : STD_LOGIC; + SIGNAL init_rmaster_up_rx : STD_LOGIC; + SIGNAL init_rmaster_up_tx : STD_LOGIC; + SIGNAL init_rphfifo_regmode_rx : STD_LOGIC; + SIGNAL init_rpma_done_count : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL init_rrcvd_clk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_rrx_rd_clk_sel : STD_LOGIC; + SIGNAL init_rrxfifo_urst_en : STD_LOGIC; + SIGNAL init_rrxpcsclkpwdn : STD_LOGIC; + SIGNAL init_rrxphfifopldctl_en : STD_LOGIC; + SIGNAL init_rself_sw_en_rx : STD_LOGIC; + SIGNAL init_rself_sw_en_tx : STD_LOGIC; + SIGNAL init_rtxpcsclkpwdn : STD_LOGIC; + SIGNAL init_rtxphfifopldctl_en : STD_LOGIC; + SIGNAL init_rtxrdclksel : STD_LOGIC; + SIGNAL init_rtxwrclksel : STD_LOGIC; + SIGNAL init_scan_mode : STD_LOGIC; + + -- cram used in centrl_clk_ctl but not in WYS + SIGNAL init_rfreerun_centrl : STD_LOGIC; + SIGNAL init_rcentrl_clk_sel : STD_LOGIC; + SIGNAL init_rrefclk_out_div2 : STD_LOGIC; + + SIGNAL init_rtxfifo_urst_en : STD_LOGIC; -- used in txctrl + + SIGNAL cram_rauto_deassert_pc_rst_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL cram_rauto_pc_en_cnt : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cram_rauto_speed_ena : STD_LOGIC; + SIGNAL cram_rclk_1_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rclk_2_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rdwidth_rx : STD_LOGIC; + SIGNAL cram_rdwidth_tx : STD_LOGIC; + SIGNAL cram_rfreerun_rx : STD_LOGIC; + SIGNAL cram_rfreerun_tx : STD_LOGIC; + SIGNAL cram_rfreq_sel : STD_LOGIC; + SIGNAL cram_rindv_rx : STD_LOGIC; + SIGNAL cram_rindv_tx : STD_LOGIC; + SIGNAL cram_rmaster_rx : STD_LOGIC; + SIGNAL cram_rmaster_tx : STD_LOGIC; + SIGNAL cram_rmaster_up_rx : STD_LOGIC; + SIGNAL cram_rmaster_up_tx : STD_LOGIC; + SIGNAL cram_rphfifo_regmode_rx : STD_LOGIC; + SIGNAL cram_rpma_done_count : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL cram_rrcvd_clk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL cram_rrx_rd_clk_sel : STD_LOGIC; + SIGNAL cram_rrxfifo_urst_en : STD_LOGIC; + SIGNAL cram_rrxpcsclkpwdn : STD_LOGIC; + SIGNAL cram_rrxphfifopldctl_en : STD_LOGIC; + SIGNAL cram_rself_sw_en_rx : STD_LOGIC; + SIGNAL cram_rself_sw_en_tx : STD_LOGIC; + SIGNAL cram_rtxpcsclkpwdn : STD_LOGIC; + SIGNAL cram_rtxphfifopldctl_en : STD_LOGIC; + SIGNAL cram_rtxrdclksel : STD_LOGIC; + SIGNAL cram_rtxwrclksel : STD_LOGIC; + SIGNAL cram_scan_mode : STD_LOGIC; + + -- cram used in centrl_clk_ctl but not in WYS + SIGNAL cram_rfreerun_centrl : STD_LOGIC := '1'; + SIGNAL cram_rcentrl_clk_sel : STD_LOGIC := '0'; + SIGNAL cram_rrefclk_out_div2 : STD_LOGIC := '0'; + + SIGNAL cram_rtxfifo_urst_en : STD_LOGIC; -- used in txctrl + + -- ww12_RTL update + SIGNAL init_rxaui_s2gx_en_rx : STD_LOGIC; + SIGNAL init_rxaui_s2gx_en_tx : STD_LOGIC; + SIGNAL cram_rxaui_s2gx_en_rx : STD_LOGIC; + SIGNAL cram_rxaui_s2gx_en_tx : STD_LOGIC; + + SIGNAL init_rwait_for_phfifo_cnt : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL cram_rwait_for_phfifo_cnt : STD_LOGIC_VECTOR(5 DOWNTO 0); + + --/////////////////////////////////////////////////////////////////////////// + -- INPUT Filtering --------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + SIGNAL dpclk_in : STD_LOGIC; + SIGNAL dpriodisable_in : STD_LOGIC; + SIGNAL dprioin_in : STD_LOGIC; + SIGNAL dprioload_in : STD_LOGIC; + SIGNAL fixedclk_in : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL quadreset_in : STD_LOGIC; + SIGNAL rxanalogreset_in : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL rxclk_in : STD_LOGIC; + SIGNAL rxdigitalreset_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxpowerdown_in : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL txclk_in : STD_LOGIC; + SIGNAL txdigitalreset_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txpllreset_in : STD_LOGIC_VECTOR(1 DOWNTO 0); --NEW + + -- new added in ww47 + SIGNAL rateswitch_in : STD_LOGIC; + SIGNAL rateswitchdonein_in : STD_LOGIC; + SIGNAL rxcoreclk_in : STD_LOGIC; + SIGNAL rxphfifordenable_in : STD_LOGIC; + SIGNAL rxphfiforeset_in : STD_LOGIC; + SIGNAL rxphfifowrdisable_in : STD_LOGIC; + SIGNAL scanclk_in : STD_LOGIC; + SIGNAL scanin_in : STD_LOGIC_VECTOR(22 DOWNTO 0); + SIGNAL scanmode_in : STD_LOGIC; + SIGNAL scanshift_in : STD_LOGIC; + SIGNAL txcoreclk_in : STD_LOGIC; + SIGNAL txphfiforddisable_in : STD_LOGIC; + SIGNAL txphfiforeset_in : STD_LOGIC; + SIGNAL txphfifowrenable_in : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- TIMING -- TCO/TSU/HOLD // + --/////////////////////////////////////////////////////////////////////////// + SIGNAL dprioout_tim : STD_LOGIC; + SIGNAL dpriooe_tim : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- quad_reset ---------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + SIGNAL qr_in_entest : STD_LOGIC; -- Test mode control from Control block + SIGNAL qr_in_plniotri : STD_LOGIC; -- PLL output enable + SIGNAL qr_in_npor : STD_LOGIC; -- Power on reset + SIGNAL qr_in_frzreg : STD_LOGIC; -- Freeze register during power-up + SIGNAL qr_in_pllurst : STD_LOGIC; -- PLL user reset + -- Reset CRAMs + SIGNAL qr_cram_rpllurst : STD_LOGIC; -- Gating CRAM for PLLURST + SIGNAL qr_cram_rpowerdown : STD_LOGIC; -- Quad power down CRAM + SIGNAL qr_cram_rreset : STD_LOGIC; -- Quad reset CRAM + + -- Reset outputs + SIGNAL qr_out_cmu_rstb : STD_LOGIC; -- CMU reset + SIGNAL qr_out_mdio_rst : STD_LOGIC; -- MDIO reset + SIGNAL qr_out_hard_reset : STD_LOGIC; -- Output HARD_RESET signal for other MDIO modules + SIGNAL qr_out_soft_reset_all_hssi : STD_LOGIC; -- Quad soft reset output + + -- new in ww47 ------------------------------------------- + -- CMU reset inputs + SIGNAL qr_in_rxurstcmu : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Dynamic signal for CMU[1:0]_RXPMA_RSTB + + -- CMU qr_cram_reset CRAMs + SIGNAL qr_cram_rrxurstcmu : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Gating CRAM for dynamic signal qr_cram_rxurstcmu + SIGNAL qr_cram_rrx_cmu_rst : STD_LOGIC_VECTOR(1 DOWNTO 0); -- TXPLL / qr_cram_rXPLL qr_cram_reset + + -- CMU powerdown inputs + SIGNAL qr_in_ucmurx_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); -- Dynamic signal for CMU[1:0]_RX_PDB + + -- CMU powerdown CRAMs + SIGNAL qr_cram_rclk_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_powdnr : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_cru_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_urx_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_rx_ib_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_powdnt : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_tx_ob_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_tx_cgb_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL qr_cram_rcmu_rx_det_pdb : STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- CMU reset outputs - moved to chnl reset + SIGNAL qr_out_cmu0_rxpma_rstb : STD_LOGIC; + SIGNAL qr_out_cmu0_txpma_rstb : STD_LOGIC; + SIGNAL qr_out_cmu0_cru_rstb : STD_LOGIC; + + SIGNAL qr_out_cmu1_rxpma_rstb : STD_LOGIC; + SIGNAL qr_out_cmu1_txpma_rstb : STD_LOGIC; + SIGNAL qr_out_cmu1_cru_rstb : STD_LOGIC; + + -- CMU powerdown outputs - moved to chnl reset + SIGNAL qr_out_cmu0_rx_pdb : STD_LOGIC; + SIGNAL qr_out_cmu0_cru_pdb : STD_LOGIC; + SIGNAL qr_out_cmu0_clk_pdb : STD_LOGIC; + SIGNAL qr_out_cmu0_tx_pdb : STD_LOGIC; + SIGNAL qr_out_cmu0_cgb_pdb : STD_LOGIC; + SIGNAL qr_out_cmu0_rx_det_pdb : STD_LOGIC; + + SIGNAL qr_out_cmu1_rx_pdb : STD_LOGIC; + SIGNAL qr_out_cmu1_cru_pdb : STD_LOGIC; + SIGNAL qr_out_cmu1_clk_pdb : STD_LOGIC; + SIGNAL qr_out_cmu1_tx_pdb : STD_LOGIC; + SIGNAL qr_out_cmu1_cgb_pdb : STD_LOGIC; + SIGNAL qr_out_cmu1_rx_det_pdb : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- channel_reset ------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + -- Inputs from QUAD reset module + SIGNAL chr_in_hard_reset : STD_LOGIC; -- hardreset signal + SIGNAL chr_in_soft_reset_all_hssi : STD_LOGIC; -- soft reset for all channel + SIGNAL chr_in_rreset : STD_LOGIC; -- Quad reset CRAM + SIGNAL chr_in_rpowerdown : STD_LOGIC; -- Quad power down CRAM + + -- Channel Reset inputs + SIGNAL chr_in_rxurstpma : STD_LOGIC_VECTOR(5 DOWNTO 0); -- RX PMA user reset - all ch + SIGNAL chr_in_rxurstpcs : STD_LOGIC_VECTOR(3 DOWNTO 0); -- RX PCS user reset + SIGNAL chr_in_txurstpcs : STD_LOGIC_VECTOR(3 DOWNTO 0); -- TX PCS user reset + + -- Channel Reset CRAMs + SIGNAL chr_in_rpowdnr : STD_LOGIC; -- RX channel power down CRAM + SIGNAL chr_in_rpowdnt : STD_LOGIC; -- TX channel power down CRAM + SIGNAL chr_in_rrxurstpcs : STD_LOGIC; -- Gating CRAM for RXURSTPCS + SIGNAL chr_in_rtxurstpcs : STD_LOGIC; -- Gating CRAM for TXURSTPCS + SIGNAL chr_in_rrxurstpma : STD_LOGIC; -- Gating CRAM for RXURSTPMA + SIGNAL chr_in_rrx_cru_rst : STD_LOGIC; -- Channel RX PLL reset CRAMs + SIGNAL chr_in_radce_rst : STD_LOGIC; -- Channel Adaptive block reset CRAMs + + -- Powerdown inputs + SIGNAL chr_in_urx_pdb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- RX user powerdown signal - all ch + + -- Powerdown CRAMs + SIGNAL chr_in_rurx_pdb : STD_LOGIC; -- Gating CRAM for urx_pdb signals + SIGNAL chr_in_radce_pdb : STD_LOGIC; -- Adaptive block powerdown CRAMs + SIGNAL chr_in_rrx_ib_pdb : STD_LOGIC; -- RX Input buffer and PLL powerdown CRAMs + SIGNAL chr_in_rtx_ob_pdb : STD_LOGIC; -- TX Output buffer powerdown CRAMs + SIGNAL chr_in_rtx_cgb_pdb : STD_LOGIC; -- TX clock generator powerdown CRAMs + SIGNAL chr_in_rrx_cru_pdb : STD_LOGIC; -- RX PLL powerdown CRAMs + + -- PIPE Inputs + SIGNAL chr_in_rtx_pipe_en : STD_LOGIC; -- PIPE enable CRAMs + SIGNAL chr_in_p0_state : STD_LOGIC; -- PIPE P0 state indicators + SIGNAL chr_in_p0s_state : STD_LOGIC; -- PIPE P0S state indicators + SIGNAL chr_in_p2_state : STD_LOGIC; -- PIPE P2 state indicators + + -- Channel Reset outputs + SIGNAL chr_out_rxpma_rstb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- RX PMA resets (powerdown) + SIGNAL chr_out_txpma_rstb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- TX PMA resets (powerdown) + SIGNAL chr_out_rxpcs_rst : STD_LOGIC_VECTOR(3 DOWNTO 0); -- RX PCS resets - extra dummy for 4/5 + SIGNAL chr_out_txpcs_rst : STD_LOGIC_VECTOR(3 DOWNTO 0); -- TX PCS resets - extra dummy for 4/5 + SIGNAL chr_out_cru_rstb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- RX PLL resets + SIGNAL chr_out_adce_rstb : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Adaptive block resets + + -- Channel Powerdown outputs + SIGNAL chr_out_adce_pdb : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Adaptive block powerdown + SIGNAL chr_out_cru_pdb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- RX PLL powerdown + SIGNAL chr_out_rx_pdb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- RX powerdown + SIGNAL chr_out_tx_pdb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- TX driver powerdown + SIGNAL chr_out_cgb_pdb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- Clock generator powerdown + SIGNAL chr_out_rx_det_pdb : STD_LOGIC_VECTOR(5 DOWNTO 0); -- Receiver detector powerdown + + --///////////////////////////////////////////////////////////////////////// + -- centrl_clk_ctl ------------------------------------------------------ // + --///////////////////////////////////////////////////////////////////////// + + -- S2GX style + SIGNAL refclk_pma_out : STD_LOGIC; -- output - Global TX PCS clock + SIGNAL mdc_b : STD_LOGIC; -- MD Clock + -- refclk_out moved to clock_divider + + SIGNAL centrlclk_ctl_in_pclk_pma : STD_LOGIC; -- x4 PCLK from PMA CMU + SIGNAL centrlclk_ctl_in_refclk_dig : STD_LOGIC; -- External digital clock + SIGNAL centrlclk_ctl_in_mdc : STD_LOGIC; -- MDIO input clock + SIGNAL centrlclk_ctl_in_ser_clk : STD_LOGIC; -- Serial clock + SIGNAL centrlclk_ctl_in_ser_mode : STD_LOGIC; -- Serial shift configuration mode + SIGNAL centrlclk_ctl_in_scan_mode : STD_LOGIC; -- Scan mode + SIGNAL centrlclk_ctl_in_scan_clk : STD_LOGIC; -- Scan mode + SIGNAL centrlclk_ctl_in_rfreerun_centrl : STD_LOGIC; -- REFCLK_OUT free running enable CRAM + SIGNAL centrlclk_ctl_in_rcentrl_clk_sel : STD_LOGIC; -- REFCLK_PMA global clock selection CRAM + SIGNAL centrlclk_ctl_in_rrefclk_out_div2 : STD_LOGIC; -- REFCLK_OUT divide by 2 enable CRAM + SIGNAL centrlclk_ctl_in_hard_reset : STD_LOGIC; -- Hard reset input + SIGNAL centrlclk_ctl_in_txrst : STD_LOGIC; + + SIGNAL centrlclk_ctl_in_gen2ngen1_bundle : STD_LOGIC; + + SIGNAL centrlclk_ctl_out_refclk_pma_out : STD_LOGIC; -- Global TX PCS clock + SIGNAL centrlclk_ctl_out_mdc_b : STD_LOGIC; -- Configuration output clock + SIGNAL centrlclk_ctl_out_refclk_out : STD_LOGIC; -- REFCLK_OUT output clk + + --///////////////////////////////////////////////////////////////////////// + -- rxclk_ctl_ctrl ------------------------------------------------------ // + --///////////////////////////////////////////////////////////////////////// + + -- S2GX portion ---------------------------------------------------------- + SIGNAL clk_1_b : STD_LOGIC; -- output - feeding to Deskew SM only + SIGNAL clk_2_b : STD_LOGIC; -- output - to RCV_SM, centrl_reset + + SIGNAL rxclk_ctl_in_pld_rx_clk : STD_LOGIC; + SIGNAL rxclk_ctl_in_rcvd_clk0_pma : STD_LOGIC; + SIGNAL rxclk_ctl_in_refclk_pma : STD_LOGIC; + SIGNAL rxclk_ctl_in_scan_mode : STD_LOGIC; + SIGNAL rxclk_ctl_in_gen2ngen1_bundle : STD_LOGIC; + SIGNAL rxclk_ctl_in_rx_div2_sync_centrl : STD_LOGIC; + SIGNAL rxclk_ctl_in_rrcvd_clk_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rxclk_ctl_in_rclk_1_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rxclk_ctl_in_rclk_2_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rxclk_ctl_in_rrx_rd_clk_sel : STD_LOGIC; + SIGNAL rxclk_ctl_in_rxrst : STD_LOGIC; + SIGNAL rxclk_ctl_in_rindv_rx : STD_LOGIC; + SIGNAL rxclk_ctl_in_rdwidth_rx : STD_LOGIC; + SIGNAL rxclk_ctl_in_rfreerun_rx : STD_LOGIC; + SIGNAL rxclk_ctl_in_rauto_speed_ena : STD_LOGIC; + SIGNAL rxclk_ctl_in_rfreq_sel : STD_LOGIC; + SIGNAL rxclk_ctl_in_rrxpcsclkpwdn : STD_LOGIC; + SIGNAL rxclk_ctl_in_rmaster_rx : STD_LOGIC; + SIGNAL rxclk_ctl_in_rmaster_up_rx : STD_LOGIC; + + SIGNAL rxclk_ctl_out_clk_1_b : STD_LOGIC; + SIGNAL rxclk_ctl_out_clk_2_b : STD_LOGIC; + SIGNAL rxclk_ctl_out_rx_wr_clk : STD_LOGIC; + SIGNAL rxclk_ctl_out_rx_rd_clk : STD_LOGIC; + SIGNAL rxclk_ctl_out_rx_div2_sync_out : STD_LOGIC; + + --unused outputs - connected for VHDL convertions and non-x (no single dummy) + SIGNAL rxclk_ctl_out_fref_muxed : STD_LOGIC; + SIGNAL rxclk_ctl_out_clklow_muxed : STD_LOGIC; + SIGNAL rxclk_ctl_out_rcvd_clk : STD_LOGIC; + SIGNAL rxclk_ctl_out_rx_clk : STD_LOGIC; + SIGNAL rxclk_ctl_out_rcvd_clk_pma_b : STD_LOGIC; + SIGNAL rxclk_ctl_out_clk_2_b_raw : STD_LOGIC; + SIGNAL rxclk_ctl_out_rx_wr_clk_raw : STD_LOGIC; + SIGNAL rxclk_ctl_out_rx_rd_clk_raw : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- txclk_ctl_ctrl ------------------------------------------------------ // + --///////////////////////////////////////////////////////////////////////// + + -- s2gx portion + SIGNAL refclk_b : STD_LOGIC; -- output to centrl_reset and TX_SM + + -- CYCLONEIV for bundling + SIGNAL txclk_ctl_in_pld_tx_clk : STD_LOGIC; + SIGNAL txclk_ctl_in_refclk_pma : STD_LOGIC; + SIGNAL txclk_ctl_in_txrst : STD_LOGIC; + SIGNAL txclk_ctl_in_scan_mode : STD_LOGIC; + SIGNAL txclk_ctl_in_gen2ngen1_bundle : STD_LOGIC; + SIGNAL txclk_ctl_in_tx_div2_sync_centrl : STD_LOGIC; + + SIGNAL txclk_ctl_out_refclk_b : STD_LOGIC; + SIGNAL txclk_ctl_out_wr_clk_pos : STD_LOGIC; + SIGNAL txclk_ctl_out_fifo_rd_clk : STD_LOGIC; + SIGNAL txclk_ctl_out_tx_div2_sync_out : STD_LOGIC; + + --unused outputs - connected for VHDL convertions and non-x (no single dummy) + SIGNAL txclk_ctl_out_tx_clk_out : STD_LOGIC; + SIGNAL txclk_ctl_out_refclk_b_raw : STD_LOGIC; + SIGNAL txclk_ctl_out_wr_clk_pos_raw : STD_LOGIC; + SIGNAL txclk_ctl_out_fifo_rd_clk_raw : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- centrl_reset -------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + SIGNAL rxrst_int : STD_LOGIC; -- to DSKW,RCV_SM, div2 on rxclk_sel (ignore) + SIGNAL txrst_int : STD_LOGIC; + + SIGNAL txrst_sync1 : STD_LOGIC := '0'; + SIGNAL txrst_sync2 : STD_LOGIC := '0'; + SIGNAL rxrst_sync1 : STD_LOGIC := '0'; + SIGNAL rxrst_sync2 : STD_LOGIC := '0'; + + --///////////////////////////////////////////////////////////////////////// + -- auto_speed_neg ------------------------------------------------------ // + --///////////////////////////////////////////////////////////////////////// + SIGNAL auto_in_refclk : STD_LOGIC; + SIGNAL auto_in_rxpcs_rst_int : STD_LOGIC; + SIGNAL auto_in_rate : STD_LOGIC; -- high gen2 and low gen1 + SIGNAL auto_in_gen2ngen1 : STD_LOGIC; + SIGNAL auto_in_config_sel_centrl : STD_LOGIC; + SIGNAL auto_in_config_sel_quad_up : STD_LOGIC; + SIGNAL auto_in_config_sel_quad_down : STD_LOGIC; + SIGNAL auto_in_singleorbundle : STD_LOGIC; + + -- control signal output for bundle mode high is gen2, low is gen1 + SIGNAL auto_out_config_sel : STD_LOGIC; + -- PMA rate change control + SIGNAL auto_out_pcie_switch : STD_LOGIC; + -- RX Phase Comp + -- Handshake signal to PIPE interface to assert PhyStatus + SIGNAL auto_out_speed_change : STD_LOGIC; + -- Phase Comp and byte ser/deser control signals + SIGNAL auto_out_dis_pc_byte : STD_LOGIC; + SIGNAL auto_out_reset_pc_ptrs : STD_LOGIC; + SIGNAL auto_out_cs : STD_LOGIC_VECTOR(3 DOWNTO 0); + + --///////////////////////////////////////////////////////////////////////// + -- rx_ctl_ctrl --------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + SIGNAL rxctrl_in_soft_reset : STD_LOGIC; + SIGNAL rxctrl_in_clk_2 : STD_LOGIC; + SIGNAL rxctrl_in_rx_rd_clk : STD_LOGIC; -- This replaces PLD_RX_CLK + SIGNAL rxctrl_in_rx_wr_clk : STD_LOGIC; -- divided by 1 or 2 write clockwire rxctrl_in_ + SIGNAL rxctrl_in_scan_mode : STD_LOGIC; -- scan enable + SIGNAL rxctrl_in_rxfifo_urst : STD_LOGIC; -- User reset exclusive to rx_ctrl & below + SIGNAL rxctrl_in_pld_wr_dis : STD_LOGIC; -- PLD write disable + SIGNAL rxctrl_in_pld_re : STD_LOGIC; -- PLD read eanble + SIGNAL rxctrl_in_dis_pc_byte : STD_LOGIC; + + SIGNAL rxctrl_out_rx_we_out : STD_LOGIC; + SIGNAL rxctrl_out_wr_enable_out : STD_LOGIC; + SIGNAL rxctrl_out_rd_enable_out : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- tx_ctl_ctrl --------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + SIGNAL txctrl_in_soft_reset : STD_LOGIC; -- Reset + SIGNAL txctrl_in_fifo_wr_clk : STD_LOGIC; -- Used to be wr_clk_pos + SIGNAL txctrl_in_fifo_rd_clk : STD_LOGIC; -- Coming from txclk_xg_ctl + SIGNAL txctrl_in_refclk_b_in : STD_LOGIC; -- The local reference clock used by the internal + SIGNAL txctrl_in_scan_mode : STD_LOGIC; -- scan enable + SIGNAL txctrl_in_txfifo_urst : STD_LOGIC; -- user reset + SIGNAL txctrl_in_pld_we : STD_LOGIC; -- PLD phase compwire txctrl_in_ fifo we, level active + SIGNAL txctrl_in_pld_rd_dis : STD_LOGIC; -- PLD phase compwire txctrl_in_ fifo rd dis, edge active + SIGNAL txctrl_in_dis_pc_byte : STD_LOGIC; + + SIGNAL txctrl_out_wr_enable_out : STD_LOGIC; -- ch0 wr_enable1 output for X4/X8 mode + SIGNAL txctrl_out_rd_enable_out : STD_LOGIC; -- ch0 rd_enable1 output for X4/X8 mode + SIGNAL txctrl_out_fifo_select_out : STD_LOGIC; -- New output for Revwire txctrl_in_B + + --///////////////////////////////////////////////////////////////////////// + -- DSKW SM ------------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + SIGNAL dskw_curr_st : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL alignstatus_int : STD_LOGIC; -- feeding to PLD and DPRIO + + SIGNAL dskw_sm_clk : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- TX SM --------------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + SIGNAL rtx_rx_local_fault_clr_int : STD_LOGIC; -- from DPRIO + SIGNAL rindv_tx_int : STD_LOGIC; + + SIGNAL tx_curr_st : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tx_local_fault_det : STD_LOGIC; -- output to rx_sm + SIGNAL tx_local_fault_int : STD_LOGIC; -- feeding nowhere + + SIGNAL tx_sm_clk : STD_LOGIC; + SIGNAL tx_sm_datain : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL tx_sm_ctrlin : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tx_sm_rdenablesyncin : STD_LOGIC; + + --///////////////////////////////////////////////////////////////////////// + -- RX SM --------------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + SIGNAL rindv_rx_int : STD_LOGIC; -- from DPRIO + SIGNAL rxs_link_status_set_int : STD_LOGIC; -- from DPRIO + SIGNAL xs_link_status_int : STD_LOGIC; + + SIGNAL rx_local_fault_int : STD_LOGIC; -- feeding DPRIO + SIGNAL xlink_status_int : STD_LOGIC; -- feeding DPRIO + SIGNAL rcv_curr_st : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL rcv_sm_clk : STD_LOGIC; + SIGNAL rcv_sm_decdatavalid : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcv_sm_decdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL rcv_sm_decctl : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rcv_sm_rxrunningdisp : STD_LOGIC_VECTOR(3 DOWNTO 0); + + --///////////////////////////////////////////////////////////////////////// + -- DPRIO --------------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + SIGNAL port_addr : STD_LOGIC_VECTOR(4 DOWNTO 0); -- convert from top parameter + SIGNAL dev_addr : STD_LOGIC_VECTOR(4 DOWNTO 0); -- convert from top parameter + SIGNAL mdio_rst : STD_LOGIC; + SIGNAL cmudprioin : STD_LOGIC_VECTOR(29 DOWNTO 0); --local wrt cmu todo: rem + SIGNAL cmudprioout : STD_LOGIC_VECTOR(29 DOWNTO 0); --local wrt cmu todo: rem + SIGNAL mdio_curr_st : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL mdio_in : STD_LOGIC; + + SIGNAL mdio_rst_reg : STD_LOGIC; + -- X-HDL generated signals + + SIGNAL xhdl13 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL xhdl14 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL xhdl15 : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL cmudividerdprioout_xhdl0 : STD_LOGIC_VECTOR(599 DOWNTO 0); + SIGNAL cmuplldprioout_xhdl1 : STD_LOGIC_VECTOR(1799 DOWNTO 0); + SIGNAL enabledeskew_xhdl2 : STD_LOGIC; + SIGNAL fiforesetrd_xhdl3 : STD_LOGIC; + SIGNAL refclkdividerdprioout_xhdl4 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL rxctrlout_xhdl5 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxdataout_xhdl6 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL rxpcsdprioout_xhdl7 : STD_LOGIC_VECTOR(1599 DOWNTO 0); + SIGNAL rxpmadprioout_xhdl8 : STD_LOGIC_VECTOR(1199 DOWNTO 0); + SIGNAL txctrlout_xhdl9 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txdataout_xhdl10 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL txpcsdprioout_xhdl11 : STD_LOGIC_VECTOR(599 DOWNTO 0); + SIGNAL txpmadprioout_xhdl12 : STD_LOGIC_VECTOR(1199 DOWNTO 0); +BEGIN + + ------------------------ + -- Wire Delay Block -- + ------------------------ + WireDelay : BLOCK + BEGIN + VitalWireDelay (txphfiforddisable_ipd,txphfiforddisable, tipd_txphfiforddisable); + bits_txctrl : FOR i in txctrl'RANGE GENERATE + VitalWireDelay (txctrl_ipd(i),txctrl(i), tipd_txctrl(i)); + END GENERATE; + bits_rxdatain : FOR i in rxdatain'RANGE GENERATE + VitalWireDelay (rxdatain_ipd(i),rxdatain(i), tipd_rxdatain(i)); + END GENERATE; + VitalWireDelay (txclk_ipd,txclk, tipd_txclk); + bits_syncstatus : FOR i in syncstatus'RANGE GENERATE + VitalWireDelay (syncstatus_ipd(i),syncstatus(i), tipd_syncstatus(i)); + END GENERATE; + bits_rxpcsdprioin : FOR i in rxpcsdprioin'RANGE GENERATE + VitalWireDelay (rxpcsdprioin_ipd(i),rxpcsdprioin(i), tipd_rxpcsdprioin(i)); + END GENERATE; + bits_txdigitalreset : FOR i in txdigitalreset'RANGE GENERATE + VitalWireDelay (txdigitalreset_ipd(i),txdigitalreset(i), tipd_txdigitalreset(i)); + END GENERATE; + bits_txdatain : FOR i in txdatain'RANGE GENERATE + VitalWireDelay (txdatain_ipd(i),txdatain(i), tipd_txdatain(i)); + END GENERATE; + VitalWireDelay (scanclk_ipd,scanclk, tipd_scanclk); + VitalWireDelay (rdenablesync_ipd,rdenablesync, tipd_rdenablesync); + VitalWireDelay (dpclk_ipd,dpclk, tipd_dpclk); + VitalWireDelay (rxphfiforeset_ipd,rxphfiforeset, tipd_rxphfiforeset); + bits_testin : FOR i in testin'RANGE GENERATE + VitalWireDelay (testin_ipd(i),testin(i), tipd_testin(i)); + END GENERATE; + bits_rxrunningdisp : FOR i in rxrunningdisp'RANGE GENERATE + VitalWireDelay (rxrunningdisp_ipd(i),rxrunningdisp(i), tipd_rxrunningdisp(i)); + END GENERATE; + bits_rxdatavalid : FOR i in rxdatavalid'RANGE GENERATE + VitalWireDelay (rxdatavalid_ipd(i),rxdatavalid(i), tipd_rxdatavalid(i)); + END GENERATE; + bits_txpcsdprioin : FOR i in txpcsdprioin'RANGE GENERATE + VitalWireDelay (txpcsdprioin_ipd(i),txpcsdprioin(i), tipd_txpcsdprioin(i)); + END GENERATE; + VitalWireDelay (dprioin_ipd,dprioin, tipd_dprioin); + bits_rxctrl : FOR i in rxctrl'RANGE GENERATE + VitalWireDelay (rxctrl_ipd(i),rxctrl(i), tipd_rxctrl(i)); + END GENERATE; + bits_rxanalogreset : FOR i in rxanalogreset'RANGE GENERATE + VitalWireDelay (rxanalogreset_ipd(i),rxanalogreset(i), tipd_rxanalogreset(i)); + END GENERATE; + VitalWireDelay (txphfifowrenable_ipd,txphfifowrenable, tipd_txphfifowrenable); + VitalWireDelay (rxphfifowrdisable_ipd,rxphfifowrdisable, tipd_rxphfifowrdisable); + bits_rdalign : FOR i in rdalign'RANGE GENERATE + VitalWireDelay (rdalign_ipd(i),rdalign(i), tipd_rdalign(i)); + END GENERATE; + bits_fixedclk : FOR i in fixedclk'RANGE GENERATE + VitalWireDelay (fixedclk_ipd(i),fixedclk(i), tipd_fixedclk(i)); + END GENERATE; + VitalWireDelay (dpriodisable_ipd,dpriodisable, tipd_dpriodisable); + VitalWireDelay (rxphfifordenable_ipd,rxphfifordenable, tipd_rxphfifordenable); + VitalWireDelay (scanmode_ipd,scanmode, tipd_scanmode); + bits_rxpmadprioin : FOR i in rxpmadprioin'RANGE GENERATE + VitalWireDelay (rxpmadprioin_ipd(i),rxpmadprioin(i), tipd_rxpmadprioin(i)); + END GENERATE; + bits_rxdigitalreset : FOR i in rxdigitalreset'RANGE GENERATE + VitalWireDelay (rxdigitalreset_ipd(i),rxdigitalreset(i), tipd_rxdigitalreset(i)); + END GENERATE; + bits_adet : FOR i in adet'RANGE GENERATE + VitalWireDelay (adet_ipd(i),adet(i), tipd_adet(i)); + END GENERATE; + VitalWireDelay (txcoreclk_ipd,txcoreclk, tipd_txcoreclk); + VitalWireDelay (txphfiforeset_ipd,txphfiforeset, tipd_txphfiforeset); + VitalWireDelay (rxcoreclk_ipd,rxcoreclk, tipd_rxcoreclk); + VitalWireDelay (dprioload_ipd,dprioload, tipd_dprioload); + VitalWireDelay (quadreset_ipd,quadreset, tipd_quadreset); + VitalWireDelay (nonuserfromcal_ipd,nonuserfromcal, tipd_nonuserfromcal); + VitalWireDelay (scanshift_ipd,scanshift, tipd_scanshift); + bits_txpmadprioin : FOR i in txpmadprioin'RANGE GENERATE + VitalWireDelay (txpmadprioin_ipd(i),txpmadprioin(i), tipd_txpmadprioin(i)); + END GENERATE; + bits_rxpowerdown : FOR i in rxpowerdown'RANGE GENERATE + VitalWireDelay (rxpowerdown_ipd(i),rxpowerdown(i), tipd_rxpowerdown(i)); + END GENERATE; + VitalWireDelay (recovclk_ipd,recovclk, tipd_recovclk); + END BLOCK; + + ------------------------ + -- Functionality Section -- + ------------------------ + -- Drive referenced outputs + cmudividerdprioout <= cmudividerdprioout_xhdl0; + cmuplldprioout <= cmuplldprioout_xhdl1; + enabledeskew <= enabledeskew_xhdl2; + fiforesetrd <= fiforesetrd_xhdl3; + refclkdividerdprioout <= refclkdividerdprioout_xhdl4; + rxctrlout <= rxctrlout_xhdl5; + rxdataout <= rxdataout_xhdl6; + rxpcsdprioout <= rxpcsdprioout_xhdl7; + rxpmadprioout <= rxpmadprioout_xhdl8; + txctrlout <= txctrlout_xhdl9; + txdataout <= txdataout_xhdl10; + txpcsdprioout <= txpcsdprioout_xhdl11; + txpmadprioout <= txpmadprioout_xhdl12; + + --/////////////////////////////////////////////////////////////////////////// + -- Const wires ------------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + vcc_wire <= '1'; + gnd_wire <= '0'; + + -- VITAL Timing + + VITAL : PROCESS(dpclk_in, dprioin_in, dprioout_tim, dpriooe_tim) + variable Tviol_dprioin_dpclk : std_ulogic := '0'; + variable TimingData_dprioin_dpclk : VitalTimingDataType := VitalTimingDataInit; + variable dprioout_VitalGlitchData: VitalGlitchDataType; + variable dpriooe_VitalGlitchData: VitalGlitchDataType; + + BEGIN + + ----------------------- + -- Timing Check Section + ----------------------- + + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_dprioin_dpclk, + TimingData => TimingData_dprioin_dpclk, + TestSignal => dprioin_in, + TestSignalName => "DPRIOIN", + RefSignal => dpclk_in, + RefSignalName => "DPCLK", + SetUpHigh => tsetup_dprioin_dpclk_noedge_posedge, + SetUpLow => tsetup_dprioin_dpclk_noedge_posedge, + HoldHigh => thold_dprioin_dpclk_noedge_posedge, + HoldLow => thold_dprioin_dpclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/CYCLONEIV_HSSI_CMU", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + end if; + + --------------------- + -- Path Delay Section + --------------------- + + VitalPathDelay01 ( + OutSignal => dprioout, + OutSignalName => "DPRIOOUT", + OutTemp => dprioout_tim, + Paths => (1 => (dpclk_in'last_event, tpd_dpclk_dprioout_posedge, TRUE)), + GlitchData => dprioout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => dpriooe, + OutSignalName => "DPRIOOE", + OutTemp => dpriooe_tim, + Paths => (1 => (dpclk_in'last_event, tpd_dpclk_dpriooe_posedge, TRUE)), + GlitchData => dpriooe_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + END PROCESS; + + --/////////////////////////////////////////////////////////////////////////// + -- process param ----------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + PROCESS + BEGIN + init_rauto_deassert_pc_rst_cnt <= int2bin(auto_spd_deassert_ph_fifo_rst_count, 4); + init_rauto_pc_en_cnt <= int2bin(auto_spd_phystatus_notify_count, 5); + init_rauto_speed_ena <= mux_select(alpha_tolower(pipe_auto_speed_nego_enable) = ("true"), '1', '0'); + + init_rclk_1_sel <= mux_select((rx0_clk1_mux_select = ("recvd_clk") OR rx0_clk1_mux_select = ("recovered clock")), "00", mux_select((rx0_clk1_mux_select = ("digital_refclk") OR rx0_clk1_mux_select = ("digital reference clock")), "01", mux_select((rx0_clk1_mux_select = ("local_refclk") OR rx0_clk1_mux_select = ("local reference clock")), "10", mux_select((rx0_clk1_mux_select = ("master_clk") OR rx0_clk1_mux_select = ("master clk") OR rx0_clk1_mux_select = ("master clock")), "11", "ZZ")))); + init_rclk_2_sel <= mux_select((rx0_clk2_mux_select = ("recvd_clk") OR rx0_clk2_mux_select = ("recovered clock")), "00", mux_select((rx0_clk2_mux_select = ("digital_refclk") OR rx0_clk2_mux_select = ("digital reference clock")), "10", mux_select((rx0_clk2_mux_select = ("local_refclk") OR rx0_clk2_mux_select = ("local reference clock")), "01", mux_select((rx0_clk2_mux_select = ("core_clk") OR rx0_clk2_mux_select = ("core clk") OR rx0_clk2_mux_select = ("core clock")), "11", "ZZ")))); + init_rdwidth_rx <= mux_select((rx0_use_double_data_mode = ("true")), '1', '0'); + init_rdwidth_tx <= mux_select((tx0_use_double_data_mode = ("true")), '1', '0'); + init_rfreerun_rx <= mux_select((rx0_reset_clock_output_during_digital_reset = ("false")), '1', '0'); + init_rfreerun_tx <= mux_select((tx0_reset_clock_output_during_digital_reset = ("false")), '1', '0'); -- "Data width" + init_rfreq_sel <= mux_select((pipe_freq_scale_mode = ("data width")), '0', '1'); + init_rindv_rx <= mux_select((rx0_channel_bonding = ("x4") OR rx0_channel_bonding = ("x8") OR alpha_tolower(in_xaui_mode) = ("true")), '0', '1'); + init_rindv_tx <= mux_select((tx0_channel_bonding = ("x4") OR tx0_channel_bonding = ("x8") OR alpha_tolower(in_xaui_mode) = ("true")), '0', '1'); + init_rmaster_rx <= mux_select((alpha_tolower(rx_master_direction) = ("none")), '1', '0'); + init_rmaster_tx <= mux_select((alpha_tolower(tx_master_direction) = ("none")), '1', '0'); + init_rmaster_up_rx <= mux_select((alpha_tolower(rx_master_direction) = ("up")), '1', '0'); + init_rmaster_up_tx <= mux_select((alpha_tolower(tx_master_direction) = ("up")), '1', '0'); + init_rphfifo_regmode_rx <= mux_select((rx0_ph_fifo_reg_mode = ("true")), '1', '0'); + init_rpma_done_count <= "000000000000001111"; -- int2bin(pma_done_count, 18); + init_rrcvd_clk_sel <= mux_select((rx0_recovered_clk_mux_select = ("recvd_clk") OR rx0_recovered_clk_mux_select = ("recovered clock")), "00", mux_select((rx0_recovered_clk_mux_select = ("digital_refclk") OR rx0_recovered_clk_mux_select = ("digital reference clock")), "01", mux_select((rx0_recovered_clk_mux_select = ("local_refclk") OR rx0_recovered_clk_mux_select = ("local reference clock")), "10", "ZZ"))); + init_rrx_rd_clk_sel <= mux_select((rx0_rd_clk_mux_select = ("core_clk") OR rx0_rd_clk_mux_select = ("core clk") OR rx0_rd_clk_mux_select = ("core clock")), '1', '0'); + init_rrxfifo_urst_en <= mux_select((rx0_ph_fifo_reset_enable = ("true")), '1', '0'); + init_rrxpcsclkpwdn <= mux_select((rx0_clk_pd_enable = ("true")), '1', '0'); + init_rrxphfifopldctl_en <= mux_select((rx0_ph_fifo_user_ctrl_enable = ("true")), '1', '0'); + init_rself_sw_en_rx <= mux_select((alpha_tolower(rx0_auto_spd_self_switch_enable) = ("true")), '1', '0'); + init_rself_sw_en_tx <= mux_select((alpha_tolower(tx0_auto_spd_self_switch_enable) = ("true")), '1', '0'); + init_rtxpcsclkpwdn <= mux_select((tx0_clk_pd_enable = ("true")), '1', '0'); + init_rtxphfifopldctl_en <= mux_select((tx0_ph_fifo_user_ctrl_enable = ("true")), '1', '0'); -- TxFifo Rd clock 1=refclk_pma, 0=local_refclk_pma + init_rtxrdclksel <= mux_select((tx0_rd_clk_mux_select = ("central")), '1', '0'); + init_rtxwrclksel <= mux_select((tx0_wr_clk_mux_select = ("int_clk") OR tx0_wr_clk_mux_select = ("int clk") OR tx0_wr_clk_mux_select = ("internal clock")), '1', '0'); -- TxFifo Write clk. 1=int_clk; 0=pld_tx_clk + + -- cram used in centrl_clk_ctl but not in WYS + init_scan_mode <= '0'; -- REFCLK_OUT free running enable CRAM + + -- cycloneiv_new + init_rfreerun_centrl <= mux_select((coreclk_out_gated_by_quad_reset = ("true")), '0', '1'); -- flipped + init_rcentrl_clk_sel <= mux_select((select_refclk_dig = ("true")), '1', '0'); + init_rrefclk_out_div2 <= mux_select((use_coreclk_out_post_divider = ("true")), '1', '0'); + + IF (tx0_ph_fifo_reset_enable = "true") THEN + init_rtxfifo_urst_en <= '1'; + ELSE + init_rtxfifo_urst_en <= '0'; + END IF; + + -- ww12_RTL + IF (alpha_tolower(rx_xaui_sm_backward_compatible_enable) = "true") THEN + init_rxaui_s2gx_en_rx <= '1'; + ELSE + init_rxaui_s2gx_en_rx <= '0'; + END IF; + + IF (alpha_tolower(tx_xaui_sm_backward_compatible_enable) = "true") THEN + init_rxaui_s2gx_en_tx <= '1'; + ELSE + init_rxaui_s2gx_en_tx <= '0'; + END IF; + + init_rwait_for_phfifo_cnt <= "100000"; -- todo + + --init_in_xaui_mode <= '0'; + init_in_xaui_mode <= mux_select((alpha_tolower(in_xaui_mode) = ("true") OR alpha_tolower(use_deskew_fifo) = ("true")), '1', '0'); + + WAIT; + END PROCESS; + + --/////////////////////////////////////////////////////////////////////////// + -- CRAM -------------------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + cram_rauto_deassert_pc_rst_cnt <= init_rauto_deassert_pc_rst_cnt; + cram_rauto_pc_en_cnt <= init_rauto_pc_en_cnt; + cram_rauto_speed_ena <= init_rauto_speed_ena; + cram_rclk_1_sel <= init_rclk_1_sel; + cram_rclk_2_sel <= init_rclk_2_sel; + cram_rdwidth_rx <= init_rdwidth_rx; + cram_rdwidth_tx <= init_rdwidth_tx; + cram_rfreerun_rx <= init_rfreerun_rx; + cram_rfreerun_tx <= init_rfreerun_tx; + cram_rfreq_sel <= init_rfreq_sel; + cram_rindv_rx <= init_rindv_rx; + cram_rindv_tx <= init_rindv_tx; + cram_rmaster_rx <= init_rmaster_rx; + cram_rmaster_tx <= init_rmaster_tx; + cram_rmaster_up_rx <= init_rmaster_up_rx; + cram_rmaster_up_tx <= init_rmaster_up_tx; + cram_rphfifo_regmode_rx <= init_rphfifo_regmode_rx; + cram_rpma_done_count <= init_rpma_done_count; + cram_rrcvd_clk_sel <= init_rrcvd_clk_sel; + cram_rrx_rd_clk_sel <= init_rrx_rd_clk_sel; + cram_rrxfifo_urst_en <= init_rrxfifo_urst_en; + cram_rrxpcsclkpwdn <= init_rrxpcsclkpwdn; + cram_rrxphfifopldctl_en <= init_rrxphfifopldctl_en; + cram_rself_sw_en_rx <= init_rself_sw_en_rx; + cram_rself_sw_en_tx <= init_rself_sw_en_tx; + cram_rtxpcsclkpwdn <= init_rtxpcsclkpwdn; + cram_rtxphfifopldctl_en <= init_rtxphfifopldctl_en; + cram_rtxrdclksel <= init_rtxrdclksel; + cram_rtxwrclksel <= init_rtxwrclksel; + cram_scan_mode <= init_scan_mode; + + -- cram used in centrl_clk_ctl but not in WYS + cram_rfreerun_centrl <= init_rfreerun_centrl; + cram_rcentrl_clk_sel <= init_rcentrl_clk_sel; + cram_rrefclk_out_div2 <= init_rrefclk_out_div2; + + cram_rtxfifo_urst_en <= init_rtxfifo_urst_en; -- used in txctrl + + -- ww12_RTL + cram_rxaui_s2gx_en_rx <= init_rxaui_s2gx_en_rx; + cram_rxaui_s2gx_en_tx <= init_rxaui_s2gx_en_tx; + cram_rwait_for_phfifo_cnt <= init_rwait_for_phfifo_cnt; + + --/////////////////////////////////////////////////////////////////////////// + -- INPUT Filtering --------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + dpclk_in <= '1' WHEN (dpclk = '1') ELSE + '0'; + dpriodisable_in <= '0' WHEN (dpriodisable = '0') ELSE + '1'; + dprioin_in <= dprioin; + + dprioload_in <= '1' WHEN (dprioload = '1') ELSE + '0'; + fixedclk_in(0) <= '1' WHEN (fixedclk(0) = '1') ELSE + '0'; + fixedclk_in(1) <= '1' WHEN (fixedclk(1) = '1') ELSE + '0'; + fixedclk_in(2) <= '1' WHEN (fixedclk(2) = '1') ELSE + '0'; + fixedclk_in(3) <= '1' WHEN (fixedclk(3) = '1') ELSE + '0'; + fixedclk_in(4) <= '0'; -- cycloneiv_modify + fixedclk_in(5) <= '0'; -- cycloneiv_modify + + --assign quadenable_in = (quadenable === 1'b0) ? 1'b0 : 1'b1; + quadreset_in <= '1' WHEN (quadreset = '1') ELSE + '0'; + rxanalogreset_in(0) <= '1' WHEN (rxanalogreset(0) = '1') ELSE + '0'; + rxanalogreset_in(1) <= '1' WHEN (rxanalogreset(1) = '1') ELSE + '0'; + rxanalogreset_in(2) <= '1' WHEN (rxanalogreset(2) = '1') ELSE + '0'; + rxanalogreset_in(3) <= '1' WHEN (rxanalogreset(3) = '1') ELSE + '0'; + rxanalogreset_in(4) <= '0'; -- cycloneiv_modify + rxanalogreset_in(5) <= '0'; -- cycloneiv_modify + + rxclk_in <= '1' WHEN (rxclk = '1') ELSE + '0'; + rxdigitalreset_in(0) <= '1' WHEN (rxdigitalreset(0) = '1') ELSE + '0'; + rxdigitalreset_in(1) <= '1' WHEN (rxdigitalreset(1) = '1') ELSE + '0'; + rxdigitalreset_in(2) <= '1' WHEN (rxdigitalreset(2) = '1') ELSE + '0'; + rxdigitalreset_in(3) <= '1' WHEN (rxdigitalreset(3) = '1') ELSE + '0'; + rxpowerdown_in(0) <= '0' WHEN (rxpowerdown(0) = '1') ELSE --inverted + '1'; + rxpowerdown_in(1) <= '0' WHEN (rxpowerdown(1) = '1') ELSE --inverted + '1'; + rxpowerdown_in(2) <= '0' WHEN (rxpowerdown(2) = '1') ELSE --inverted + '1'; + rxpowerdown_in(3) <= '0' WHEN (rxpowerdown(3) = '1') ELSE --inverted + '1'; + rxpowerdown_in(4) <= '1'; --inverted -- cycloneiv_modify + rxpowerdown_in(5) <= '1'; --inverted -- cycloneiv_modify + + txclk_in <= '1' WHEN (txclk = '1') ELSE + '0'; + txdigitalreset_in(0) <= '1' WHEN (txdigitalreset(0) = '1') ELSE + '0'; + txdigitalreset_in(1) <= '1' WHEN (txdigitalreset(1) = '1') ELSE + '0'; + txdigitalreset_in(2) <= '1' WHEN (txdigitalreset(2) = '1') ELSE + '0'; + txdigitalreset_in(3) <= '1' WHEN (txdigitalreset(3) = '1') ELSE + '0'; + txpllreset_in(0) <= '1' WHEN (txpllreset(0) = '1') ELSE + '0'; + txpllreset_in(1) <= '1' WHEN (txpllreset(1) = '1') ELSE + '0'; + + -- new one added in ww47 + rateswitch_in <= rateswitch; + rateswitchdonein_in <= rateswitchdonein; + rxcoreclk_in <= rxcoreclk; + rxphfifordenable_in <= rxphfifordenable; + rxphfiforeset_in <= rxphfiforeset; + rxphfifowrdisable_in <= rxphfifowrdisable; + scanclk_in <= '1' WHEN (scanclk = '1') ELSE + '0'; + scanin_in <= "00000000000000000000001" WHEN (scanin = "00000000000000000000001") ELSE + "00000000000000000000000"; + scanmode_in <= '1' WHEN (scanmode = '1') ELSE + '0'; + scanshift_in <= '1' WHEN (scanshift = '1') ELSE + '0'; + txcoreclk_in <= txcoreclk; + txphfiforddisable_in <= txphfiforddisable; + txphfiforeset_in <= txphfiforeset; + txphfifowrenable_in <= txphfifowrenable; + + --/////////////////////////////////////////////////////////////////////////// + -- TIMING -- TCO/TSU/HOLD // + --/////////////////////////////////////////////////////////////////////////// + + dprioout <= dprioout_tim; + dpriooe <= dpriooe_tim; + + --///////////////////////////////////////////////////////////////////////// + -- quad_reset inst ----------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + qr_in_entest <= '0'; -- Test mode control from Control block + qr_in_plniotri <= '1'; -- PLL output enable + qr_in_npor <= '1'; -- Power on reset + qr_in_frzreg <= '0'; -- Freeze register during power-up + qr_in_pllurst <= '1' WHEN (quadreset_in = '1') ELSE -- PLL user reset + '0'; + + -- enable corresponding port by default in simulation + qr_cram_rpllurst <= '1'; -- Gating CRAM for PLLURST + qr_cram_rpowerdown <= '0'; -- Quad power down CRAM + qr_cram_rreset <= '0'; -- Quad reset CRAM - scan_mode ? 1'b0 : rreset; + + -- new in ww47 ---------------------------------------------------- + + -- CMU0/1 reset - moved rx_pll, rx_pma and tx_pma resets to chnl reset [4:5] + -- but kept CMU_PLL (LC_PLL) resets in Quadreset + qr_in_rxurstcmu <= txpllreset_in; + qr_in_ucmurx_pdb <= "00"; + + -- CMU qr_cram_reset CRAMs + qr_cram_rrxurstcmu <= "11"; -- Gating CRAM for dynamic signal rxurstcmu + qr_cram_rrx_cmu_rst <= "00"; -- TXPLL / RXPLL reset + + -- CMU powerdown CRAMs + qr_cram_rclk_pdb <= "00"; --generating cmu0/1_clk_pdb + qr_cram_rcmu_powdnr <= "00"; + qr_cram_rcmu_cru_pdb <= "11"; + qr_cram_rcmu_urx_pdb <= "11"; + qr_cram_rcmu_rx_ib_pdb <= "11"; + qr_cram_rcmu_powdnt <= "00"; + qr_cram_rcmu_tx_ob_pdb <= "11"; + qr_cram_rcmu_tx_cgb_pdb <= "11"; + qr_cram_rcmu_rx_det_pdb <= "11"; + + -- Moved cmu0/cmu1 reset/powerdown out to channel reset + -- still controls cmu_pll/cmu_clk_divider and hardreset + + + quad_reset_1 : cycloneiv_hssi_cmu_quad_reset + PORT MAP ( + entest => qr_in_entest, + plniotri => qr_in_plniotri, + npor => qr_in_npor, + frzreg => qr_in_frzreg, + pllurst => qr_in_pllurst, + rpllurst => qr_cram_rpllurst, + rreset => qr_cram_rreset, + rpowerdown => qr_cram_rpowerdown, + + -- CMU reset inputs + rxurstcmu => qr_in_rxurstcmu, + -- CMU reset CRAMs + rrxurstcmu => qr_cram_rrxurstcmu, + rrx_cmu_rst => qr_cram_rrx_cmu_rst, + -- CMU powerdown inputs + ucmurx_pdb => qr_in_ucmurx_pdb, + -- CMU powerdown CRAMs + rclk_pdb => qr_cram_rclk_pdb, + rcmu_powdnr => qr_cram_rcmu_powdnr, + rcmu_cru_pdb => qr_cram_rcmu_cru_pdb, + rcmu_urx_pdb => qr_cram_rcmu_urx_pdb, + rcmu_rx_ib_pdb => qr_cram_rcmu_rx_ib_pdb, + rcmu_powdnt => qr_cram_rcmu_powdnt, + rcmu_tx_ob_pdb => qr_cram_rcmu_tx_ob_pdb, + rcmu_tx_cgb_pdb => qr_cram_rcmu_tx_cgb_pdb, + rcmu_rx_det_pdb => qr_cram_rcmu_rx_det_pdb, + -- CMU reset outputs + cmu0_rxpma_rstb => qr_out_cmu0_rxpma_rstb, + cmu0_txpma_rstb => qr_out_cmu0_txpma_rstb, + cmu0_cru_rstb => qr_out_cmu0_cru_rstb, + cmu1_rxpma_rstb => qr_out_cmu1_rxpma_rstb, + cmu1_txpma_rstb => qr_out_cmu1_txpma_rstb, + cmu1_cru_rstb => qr_out_cmu1_cru_rstb, + -- CMU powerdown outputs + cmu0_rx_pdb => qr_out_cmu0_rx_pdb, + cmu0_cru_pdb => qr_out_cmu0_cru_pdb, + cmu0_clk_pdb => qr_out_cmu0_clk_pdb, + cmu0_tx_pdb => qr_out_cmu0_tx_pdb, + cmu0_cgb_pdb => qr_out_cmu0_cgb_pdb, + cmu0_rx_det_pdb => qr_out_cmu0_rx_det_pdb, + cmu1_rx_pdb => qr_out_cmu1_rx_pdb, + cmu1_cru_pdb => qr_out_cmu1_cru_pdb, + cmu1_clk_pdb => qr_out_cmu1_clk_pdb, + cmu1_tx_pdb => qr_out_cmu1_tx_pdb, + cmu1_cgb_pdb => qr_out_cmu1_cgb_pdb, + cmu1_rx_det_pdb => qr_out_cmu1_rx_det_pdb, + -- Other outputs + mdio_rst => qr_out_mdio_rst, + hard_reset => qr_out_hard_reset, + soft_reset_all_hssi => qr_out_soft_reset_all_hssi + ); + + --///////////////////////////////////////////////////////////////////////// + -- chnl_reset inst ----------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + chr_in_hard_reset <= qr_out_hard_reset; -- hardreset signal + chr_in_soft_reset_all_hssi <= qr_out_soft_reset_all_hssi; -- soft reset for all channel + chr_in_rreset <= qr_cram_rreset; -- Quad reset CRAM + chr_in_rpowerdown <= qr_cram_rpowerdown; -- Quad power down CRAM + + -- Channel Reset inputs + chr_in_rxurstpma <= rxanalogreset_in; -- RX PMA user reset + chr_in_rxurstpcs <= rxdigitalreset_in; -- RX PCS user reset + chr_in_txurstpcs <= txdigitalreset_in; -- TX PCS user reset + + -- Channel Reset CRAMs + chr_in_rpowdnr <= '0'; -- RX channel power down CRAM + chr_in_rpowdnt <= '0'; -- TX channel power down CRAM + chr_in_rrxurstpcs <= '1'; -- Gating CRAM for RXURSTPCS + chr_in_rtxurstpcs <= '1'; -- Gating CRAM for TXURSTPCS + chr_in_rrxurstpma <= '1'; -- Gating CRAM for RXURSTPMA + chr_in_rrx_cru_rst <= '0'; -- Channel RX PLL reset CRAMs + chr_in_radce_rst <= '0'; -- Channel Adaptive block reset CRAMs + + -- Powerdown inputs + chr_in_urx_pdb <= rxpowerdown_in; -- RX user powerdown signal + + -- Powerdown CRAMs - active low + chr_in_rurx_pdb <= '1'; -- Gating CRAM for urx_pdb signals + chr_in_radce_pdb <= '1'; -- Adaptive block powerdown CRAMs + chr_in_rrx_ib_pdb <= '1'; -- RX Input buffer and PLL powerdown CRAMs + chr_in_rtx_ob_pdb <= '1'; -- TX Output buffer powerdown CRAMs + chr_in_rtx_cgb_pdb <= '1'; -- TX clock generator powerdown CRAMs + chr_in_rrx_cru_pdb <= '1'; -- RX PLL powerdown CRAMs + + -- PIPE Inputs + chr_in_rtx_pipe_en <= '0'; -- PIPE enable CRAMs + --todo: revisit - signal from tx_PIPE_INTERFACE_TOP + chr_in_p0_state <= '0'; -- PIPE P0 state indicators + chr_in_p0s_state <= '0'; -- PIPE P0S state indicators + chr_in_p2_state <= '0'; -- PIPE P2 state indicators + + -- Channel-based reset logic (for both PCS and PMA channel) + chnl_reset0 : cycloneiv_hssi_cmu_chnl_reset + PORT MAP ( + hard_reset => chr_in_hard_reset, + soft_reset_all_hssi => chr_in_soft_reset_all_hssi, + rreset => chr_in_rreset, + rpowerdown => chr_in_rpowerdown, + rxurstpma => chr_in_rxurstpma(0), + rxurstpcs => chr_in_rxurstpcs(0), + txurstpcs => chr_in_txurstpcs(0), + rpowdnr => chr_in_rpowdnr, + rpowdnt => chr_in_rpowdnt, + rrxurstpcs => chr_in_rrxurstpcs, + rtxurstpcs => chr_in_rtxurstpcs, + rrxurstpma => chr_in_rrxurstpma, + rrx_cru_rst => chr_in_rrx_cru_rst, + radce_rst => chr_in_radce_rst, + urx_pdb => chr_in_urx_pdb(0), + rurx_pdb => chr_in_rurx_pdb, + radce_pdb => chr_in_radce_pdb, + rrx_ib_pdb => chr_in_rrx_ib_pdb, + rtx_ob_pdb => chr_in_rtx_ob_pdb, + rtx_cgb_pdb => chr_in_rtx_cgb_pdb, + rrx_cru_pdb => chr_in_rrx_cru_pdb, + rtx_pipe_en => chr_in_rtx_pipe_en, + p0_state => chr_in_p0_state, + p0s_state => chr_in_p0s_state, + p2_state => chr_in_p2_state, + + rxpma_rstb => chr_out_rxpma_rstb(0), + txpma_rstb => chr_out_txpma_rstb(0), + rxpcs_rst => chr_out_rxpcs_rst(0), + txpcs_rst => chr_out_txpcs_rst(0), + cru_rstb => chr_out_cru_rstb(0), + adce_rstb => chr_out_adce_rstb(0), + adce_pdb => chr_out_adce_pdb(0), + cru_pdb => chr_out_cru_pdb(0), + rx_pdb => chr_out_rx_pdb(0), + tx_pdb => chr_out_tx_pdb(0), + cgb_pdb => chr_out_cgb_pdb(0), + rx_det_pdb => chr_out_rx_det_pdb(0) + ); + + chnl_reset1 : cycloneiv_hssi_cmu_chnl_reset + PORT MAP ( + hard_reset => chr_in_hard_reset, + soft_reset_all_hssi => chr_in_soft_reset_all_hssi, + rreset => chr_in_rreset, + rpowerdown => chr_in_rpowerdown, + rxurstpma => chr_in_rxurstpma(1), + rxurstpcs => chr_in_rxurstpcs(1), + txurstpcs => chr_in_txurstpcs(1), + rpowdnr => chr_in_rpowdnr, + rpowdnt => chr_in_rpowdnt, + rrxurstpcs => chr_in_rrxurstpcs, + rtxurstpcs => chr_in_rtxurstpcs, + rrxurstpma => chr_in_rrxurstpma, + rrx_cru_rst => chr_in_rrx_cru_rst, + radce_rst => chr_in_radce_rst, + urx_pdb => chr_in_urx_pdb(1), + rurx_pdb => chr_in_rurx_pdb, + radce_pdb => chr_in_radce_pdb, + rrx_ib_pdb => chr_in_rrx_ib_pdb, + rtx_ob_pdb => chr_in_rtx_ob_pdb, + rtx_cgb_pdb => chr_in_rtx_cgb_pdb, + rrx_cru_pdb => chr_in_rrx_cru_pdb, + rtx_pipe_en => chr_in_rtx_pipe_en, + p0_state => chr_in_p0_state, + p0s_state => chr_in_p0s_state, + p2_state => chr_in_p2_state, + + rxpma_rstb => chr_out_rxpma_rstb(1), + txpma_rstb => chr_out_txpma_rstb(1), + rxpcs_rst => chr_out_rxpcs_rst(1), + txpcs_rst => chr_out_txpcs_rst(1), + cru_rstb => chr_out_cru_rstb(1), + adce_rstb => chr_out_adce_rstb(1), + adce_pdb => chr_out_adce_pdb(1), + cru_pdb => chr_out_cru_pdb(1), + rx_pdb => chr_out_rx_pdb(1), + tx_pdb => chr_out_tx_pdb(1), + cgb_pdb => chr_out_cgb_pdb(1), + rx_det_pdb => chr_out_rx_det_pdb(1) + ); + + chnl_reset2 : cycloneiv_hssi_cmu_chnl_reset + PORT MAP ( + hard_reset => chr_in_hard_reset, + soft_reset_all_hssi => chr_in_soft_reset_all_hssi, + rreset => chr_in_rreset, + rpowerdown => chr_in_rpowerdown, + rxurstpma => chr_in_rxurstpma(2), + rxurstpcs => chr_in_rxurstpcs(2), + txurstpcs => chr_in_txurstpcs(2), + rpowdnr => chr_in_rpowdnr, + rpowdnt => chr_in_rpowdnt, + rrxurstpcs => chr_in_rrxurstpcs, + rtxurstpcs => chr_in_rtxurstpcs, + rrxurstpma => chr_in_rrxurstpma, + rrx_cru_rst => chr_in_rrx_cru_rst, + radce_rst => chr_in_radce_rst, + urx_pdb => chr_in_urx_pdb(2), + rurx_pdb => chr_in_rurx_pdb, + radce_pdb => chr_in_radce_pdb, + rrx_ib_pdb => chr_in_rrx_ib_pdb, + rtx_ob_pdb => chr_in_rtx_ob_pdb, + rtx_cgb_pdb => chr_in_rtx_cgb_pdb, + rrx_cru_pdb => chr_in_rrx_cru_pdb, + rtx_pipe_en => chr_in_rtx_pipe_en, + p0_state => chr_in_p0_state, + p0s_state => chr_in_p0s_state, + p2_state => chr_in_p2_state, + + rxpma_rstb => chr_out_rxpma_rstb(2), + txpma_rstb => chr_out_txpma_rstb(2), + rxpcs_rst => chr_out_rxpcs_rst(2), + txpcs_rst => chr_out_txpcs_rst(2), + cru_rstb => chr_out_cru_rstb(2), + adce_rstb => chr_out_adce_rstb(2), + adce_pdb => chr_out_adce_pdb(2), + cru_pdb => chr_out_cru_pdb(2), + rx_pdb => chr_out_rx_pdb(2), + tx_pdb => chr_out_tx_pdb(2), + cgb_pdb => chr_out_cgb_pdb(2), + rx_det_pdb => chr_out_rx_det_pdb(2) + ); + + chnl_reset3 : cycloneiv_hssi_cmu_chnl_reset + PORT MAP ( + hard_reset => chr_in_hard_reset, + soft_reset_all_hssi => chr_in_soft_reset_all_hssi, + rreset => chr_in_rreset, + rpowerdown => chr_in_rpowerdown, + rxurstpma => chr_in_rxurstpma(3), + rxurstpcs => chr_in_rxurstpcs(3), + txurstpcs => chr_in_txurstpcs(3), + rpowdnr => chr_in_rpowdnr, + rpowdnt => chr_in_rpowdnt, + rrxurstpcs => chr_in_rrxurstpcs, + rtxurstpcs => chr_in_rtxurstpcs, + rrxurstpma => chr_in_rrxurstpma, + rrx_cru_rst => chr_in_rrx_cru_rst, + radce_rst => chr_in_radce_rst, + urx_pdb => chr_in_urx_pdb(3), + rurx_pdb => chr_in_rurx_pdb, + radce_pdb => chr_in_radce_pdb, + rrx_ib_pdb => chr_in_rrx_ib_pdb, + rtx_ob_pdb => chr_in_rtx_ob_pdb, + rtx_cgb_pdb => chr_in_rtx_cgb_pdb, + rrx_cru_pdb => chr_in_rrx_cru_pdb, + rtx_pipe_en => chr_in_rtx_pipe_en, + p0_state => chr_in_p0_state, + p0s_state => chr_in_p0s_state, + p2_state => chr_in_p2_state, + + rxpma_rstb => chr_out_rxpma_rstb(3), + txpma_rstb => chr_out_txpma_rstb(3), + rxpcs_rst => chr_out_rxpcs_rst(3), + txpcs_rst => chr_out_txpcs_rst(3), + cru_rstb => chr_out_cru_rstb(3), + adce_rstb => chr_out_adce_rstb(3), + adce_pdb => chr_out_adce_pdb(3), + cru_pdb => chr_out_cru_pdb(3), + rx_pdb => chr_out_rx_pdb(3), + tx_pdb => chr_out_tx_pdb(3), + cgb_pdb => chr_out_cgb_pdb(3), + rx_det_pdb => chr_out_rx_det_pdb(3) + ); + + -- channel 4 + + cmu0_reset : cycloneiv_hssi_cmu_chnl_reset + PORT MAP ( + hard_reset => chr_in_hard_reset, + soft_reset_all_hssi => chr_in_soft_reset_all_hssi, + rreset => chr_in_rreset, + rpowerdown => chr_in_rpowerdown, + rxurstpma => chr_in_rxurstpma(4), + rxurstpcs => gnd_wire, + txurstpcs => gnd_wire, + rpowdnr => chr_in_rpowdnr, + rpowdnt => chr_in_rpowdnt, + rrxurstpcs => chr_in_rrxurstpcs, + rtxurstpcs => chr_in_rtxurstpcs, + rrxurstpma => chr_in_rrxurstpma, + rrx_cru_rst => chr_in_rrx_cru_rst, + radce_rst => chr_in_radce_rst, + urx_pdb => chr_in_urx_pdb(4), + rurx_pdb => chr_in_rurx_pdb, + radce_pdb => chr_in_radce_pdb, + rrx_ib_pdb => chr_in_rrx_ib_pdb, + rtx_ob_pdb => chr_in_rtx_ob_pdb, + rtx_cgb_pdb => chr_in_rtx_cgb_pdb, + rrx_cru_pdb => chr_in_rrx_cru_pdb, + rtx_pipe_en => chr_in_rtx_pipe_en, + p0_state => chr_in_p0_state, + p0s_state => chr_in_p0s_state, + p2_state => chr_in_p2_state, + + rxpma_rstb => chr_out_rxpma_rstb(4), + txpma_rstb => chr_out_txpma_rstb(4), + rxpcs_rst => dummy_wire, + txpcs_rst => dummy_wire, + cru_rstb => chr_out_cru_rstb(4), + adce_rstb => dummy_wire, + adce_pdb => dummy_wire, + cru_pdb => chr_out_cru_pdb(4), + rx_pdb => chr_out_rx_pdb(4), + tx_pdb => chr_out_tx_pdb(4), + cgb_pdb => chr_out_cgb_pdb(4), + rx_det_pdb => chr_out_rx_det_pdb(4) + ); + -- channel 5 + + cmu1_reset : cycloneiv_hssi_cmu_chnl_reset + PORT MAP ( + hard_reset => chr_in_hard_reset, + soft_reset_all_hssi => chr_in_soft_reset_all_hssi, + rreset => chr_in_rreset, + rpowerdown => chr_in_rpowerdown, + rxurstpma => chr_in_rxurstpma(5), + rxurstpcs => gnd_wire, + txurstpcs => gnd_wire, + rpowdnr => chr_in_rpowdnr, + rpowdnt => chr_in_rpowdnt, + rrxurstpcs => chr_in_rrxurstpcs, + rtxurstpcs => chr_in_rtxurstpcs, + rrxurstpma => chr_in_rrxurstpma, + rrx_cru_rst => chr_in_rrx_cru_rst, + radce_rst => chr_in_radce_rst, + urx_pdb => chr_in_urx_pdb(5), + rurx_pdb => chr_in_rurx_pdb, + radce_pdb => chr_in_radce_pdb, + rrx_ib_pdb => chr_in_rrx_ib_pdb, + rtx_ob_pdb => chr_in_rtx_ob_pdb, + rtx_cgb_pdb => chr_in_rtx_cgb_pdb, + rrx_cru_pdb => chr_in_rrx_cru_pdb, + rtx_pipe_en => chr_in_rtx_pipe_en, + p0_state => chr_in_p0_state, + p0s_state => chr_in_p0s_state, + p2_state => chr_in_p2_state, + + rxpma_rstb => chr_out_rxpma_rstb(5), + txpma_rstb => chr_out_txpma_rstb(5), + rxpcs_rst => dummy_wire, + txpcs_rst => dummy_wire, + cru_rstb => chr_out_cru_rstb(5), + adce_rstb => dummy_wire, + adce_pdb => dummy_wire, + cru_pdb => chr_out_cru_pdb(5), + rx_pdb => chr_out_rx_pdb(5), + tx_pdb => chr_out_tx_pdb(5), + cgb_pdb => chr_out_cgb_pdb(5), + rx_det_pdb => chr_out_rx_det_pdb(5) + ); + + --///////////////////////////////////////////////////////////////////////// + -- centrl_clk_ctl ------------------------------------------------------ // + --///////////////////////////////////////////////////////////////////////// + + refclk_pma_out <= centrlclk_ctl_out_refclk_pma_out; -- txclk_in <= pclk/digitalrefclkout + mdc_b <= centrlclk_ctl_out_mdc_b; -- dpclk_in; + + -- refclk_out is moved to (cmu) clock_divider atom: + -- it has /2 and gen2ngen1 bundle logic and rfreq_sel control + + centrlclk_ctl_in_pclk_pma <= txclk_in; --todo: WYS to add x4 PCLK from PMA CMU + centrlclk_ctl_in_refclk_dig <= txclk_in; --todo: External digital clock - moved to cmu_clock_divider + centrlclk_ctl_in_mdc <= dpclk_in; -- MDIO input clock + centrlclk_ctl_in_ser_clk <= '0'; -- Serial clock + centrlclk_ctl_in_ser_mode <= '0'; -- Serial shift configuration mode + centrlclk_ctl_in_scan_mode <= scanmode_in; -- Scan mode + centrlclk_ctl_in_scan_clk <= scanclk_in; -- Scan mode + centrlclk_ctl_in_hard_reset <= qr_out_hard_reset; -- Hard reset input + centrlclk_ctl_in_txrst <= txrst_int; + + centrlclk_ctl_in_gen2ngen1_bundle <= rateswitchdonein_in; + + mcmu_centrlclk_ctl : cycloneiv_hssi_cmu_clk_ctl + PORT MAP ( + pclk_pma => centrlclk_ctl_in_pclk_pma, + refclk_dig => centrlclk_ctl_in_refclk_dig, + mdc => centrlclk_ctl_in_mdc, + ser_clk => centrlclk_ctl_in_ser_clk, + ser_mode => centrlclk_ctl_in_ser_mode, + scan_mode => centrlclk_ctl_in_scan_mode, + scan_clk => centrlclk_ctl_in_scan_clk, + rfreerun_centrl => cram_rfreerun_centrl, + rcentrl_clk_sel => cram_rcentrl_clk_sel, + rrefclk_out_div2 => cram_rrefclk_out_div2, + hard_reset => centrlclk_ctl_in_hard_reset, + txrst => centrlclk_ctl_in_txrst, + rauto_speed_ena => cram_rauto_speed_ena, + rfreq_sel => cram_rfreq_sel, + gen2ngen1_bundle => centrlclk_ctl_in_gen2ngen1_bundle, + + refclk_pma_out => centrlclk_ctl_out_refclk_pma_out, + mdc_b => centrlclk_ctl_out_mdc_b, + refclk_out => centrlclk_ctl_out_refclk_out + ); + + --///////////////////////////////////////////////////////////////////////// + -- rxclk_ctl_ctrl inst ------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + -- for S2GX portion + clk_1_b <= rxclk_ctl_out_clk_1_b; --recovclk - from ch0 of recover_clk + clk_2_b <= rxclk_ctl_out_clk_2_b; --rxclk_in - masterclk in XAUI, not work for other x4 + + -- for CYCLONEIV bundling - + -- - copy rx_ch0 clocking select info here to generate FIFO_bundle_ptrs_centrl + rxclk_ctl_in_pld_rx_clk <= rxcoreclk_in; + rxclk_ctl_in_rcvd_clk0_pma <= recovclk; + rxclk_ctl_in_refclk_pma <= centrlclk_ctl_out_refclk_pma_out; + rxclk_ctl_in_scan_mode <= scanmode_in; + rxclk_ctl_in_gen2ngen1_bundle <= rateswitchdonein_in; + rxclk_ctl_in_rx_div2_sync_centrl <= rxclk_ctl_out_rx_div2_sync_out; + rxclk_ctl_in_rxrst <= txrst_int; -- from centrl_reset + + mcmu_rxclk_ctl : cycloneiv_hssi_cmu_rxclk_ctl + PORT MAP ( + pld_rx_clk => rxclk_ctl_in_pld_rx_clk, + rcvd_clk_pma => gnd_wire, + rcvd_clk0_pma => rxclk_ctl_in_rcvd_clk0_pma, + tx_pma_clk => gnd_wire, + refclk_pma => rxclk_ctl_in_refclk_pma, + fref => gnd_wire, + clklow => gnd_wire, + scan_mode => rxclk_ctl_in_scan_mode, + gen2ngen1 => rxclk_ctl_in_gen2ngen1_bundle, -- ww35.2008 gnd_wire, + gen2ngen1_bundle => rxclk_ctl_in_gen2ngen1_bundle, + rx_div2_sync_centrl => rxclk_ctl_in_rx_div2_sync_centrl, + rx_div2_sync_quad_up => gnd_wire, + rx_div2_sync_quad_down => gnd_wire, + rrcvd_clk_sel => cram_rrcvd_clk_sel, + rclk_1_sel => cram_rclk_1_sel, + rclk_2_sel => cram_rclk_2_sel, + rrx_rd_clk_sel => cram_rrx_rd_clk_sel, + + rxrst => rxclk_ctl_in_rxrst, + + rindv_rx => vcc_wire, -- ww35.2008 cram_rindv_rx, + rdwidth_rx => cram_rdwidth_rx, + rfreerun_rx => cram_rfreerun_rx, + rauto_speed_ena => cram_rauto_speed_ena, + rfreq_sel => cram_rfreq_sel, + rrxpcsclkpwdn => gnd_wire, + rmaster_rx => vcc_wire, -- ww35.2008 cram_rmaster_rx, + rmaster_up_rx => cram_rmaster_up_rx, + rself_sw_en_rx => gnd_wire, + + fref_muxed => rxclk_ctl_out_fref_muxed, + clklow_muxed => rxclk_ctl_out_clklow_muxed, + rcvd_clk => rxclk_ctl_out_rcvd_clk, + clk_1_b => rxclk_ctl_out_clk_1_b, + clk_2_b => rxclk_ctl_out_clk_2_b, + rx_wr_clk => rxclk_ctl_out_rx_wr_clk, + rx_rd_clk => rxclk_ctl_out_rx_rd_clk, + rx_clk => rxclk_ctl_out_rx_clk, + rcvd_clk_pma_b => rxclk_ctl_out_rcvd_clk_pma_b, + clk_2_b_raw => rxclk_ctl_out_clk_2_b_raw, + rx_wr_clk_raw => rxclk_ctl_out_rx_wr_clk_raw, + rx_rd_clk_raw => rxclk_ctl_out_rx_rd_clk_raw, + rx_div2_sync_out => rxclk_ctl_out_rx_div2_sync_out + ); + + --///////////////////////////////////////////////////////////////////////// + -- txclk_ctl_centrl inst ------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + -- s2gx style + refclk_b <= refclk_pma_out; -- output to centrl_reset and TX_SM + + -- CYCLONEIV for bundling + txclk_ctl_in_pld_tx_clk <= txcoreclk_in; + txclk_ctl_in_refclk_pma <= centrlclk_ctl_out_refclk_pma_out; + txclk_ctl_in_txrst <= txrst_int; + txclk_ctl_in_scan_mode <= scanmode_in; + txclk_ctl_in_gen2ngen1_bundle <= rateswitchdonein_in; + txclk_ctl_in_tx_div2_sync_centrl <= txclk_ctl_out_tx_div2_sync_out; + + -- Clock selection logic and muxes for refclk_b + + mcmu_txclk_ctl : cycloneiv_hssi_cmu_txclk_ctl + PORT MAP ( + pld_tx_clk => txclk_ctl_in_pld_tx_clk, + refclk_pma => txclk_ctl_in_refclk_pma, + txpma_local_clk => gnd_wire, + txrst => txclk_ctl_in_txrst, + scan_mode => txclk_ctl_in_scan_mode, + gen2ngen1 => txclk_ctl_in_gen2ngen1_bundle, -- ww35.2008 gnd_wire, + gen2ngen1_bundle => txclk_ctl_in_gen2ngen1_bundle, + tx_div2_sync_centrl => txclk_ctl_out_tx_div2_sync_out, + tx_div2_sync_quad_up => gnd_wire, + tx_div2_sync_quad_down => gnd_wire, + rindv_tx => vcc_wire, -- ww35.2008 cram_rindv_tx, + rtxwrclksel => cram_rtxwrclksel, + rtxrdclksel => cram_rtxrdclksel, + rdwidth_tx => cram_rdwidth_tx, + rfreerun_tx => cram_rfreerun_tx, + rauto_speed_ena => cram_rauto_speed_ena, + rfreq_sel => cram_rfreq_sel, + rtxpcsclkpwdn => gnd_wire, + rmaster_tx => vcc_wire, -- ww35.2008 cram_rmaster_tx, + rmaster_up_tx => cram_rmaster_up_tx, + rself_sw_en_tx => gnd_wire, + + refclk_b => txclk_ctl_out_refclk_b, + wr_clk_pos => txclk_ctl_out_wr_clk_pos, + fifo_rd_clk => txclk_ctl_out_fifo_rd_clk, + tx_clk_out => txclk_ctl_out_tx_clk_out, + refclk_b_raw => txclk_ctl_out_refclk_b_raw, + wr_clk_pos_raw => txclk_ctl_out_wr_clk_pos_raw, + fifo_rd_clk_raw => txclk_ctl_out_fifo_rd_clk_raw, + tx_div2_sync_out => txclk_ctl_out_tx_div2_sync_out + ); + + --///////////////////////////////////////////////////////////////////////// + -- centrl_reset -------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + PROCESS (qr_out_hard_reset, clk_2_b) +VARIABLE txt : LINE; + BEGIN + IF (qr_out_hard_reset = '1') THEN + rxrst_sync2 <= '1'; + rxrst_sync1 <= '1'; + ELSIF (clk_2_b'EVENT AND clk_2_b = '1') THEN + rxrst_sync2 <= TRANSPORT rxrst_sync1 AFTER 1 ps; + rxrst_sync1 <= chr_out_rxpcs_rst(0); + END IF; + END PROCESS; + + + PROCESS (qr_out_hard_reset, refclk_b) +VARIABLE txt : LINE; + BEGIN + IF (qr_out_hard_reset = '1') THEN + txrst_sync2 <= '1'; + txrst_sync1 <= '1'; + ELSIF (refclk_b'EVENT AND refclk_b = '1') THEN + txrst_sync2 <= TRANSPORT txrst_sync1 AFTER 1 ps; + txrst_sync1 <= chr_out_txpcs_rst(0); + END IF; + END PROCESS; + + + txrst_int <= txrst_sync2; + rxrst_int <= rxrst_sync2; + + --///////////////////////////////////////////////////////////////////////// + -- auto_speed_neg ------------------------------------------------------ // + --///////////////////////////////////////////////////////////////////////// + + auto_in_refclk <= rxclk_ctl_out_clk_2_b; + auto_in_rxpcs_rst_int <= rxrst_int; + auto_in_rate <= rateswitch_in; -- high gen2 and low gen1 + auto_in_gen2ngen1 <= rateswitchdonein_in; + auto_in_config_sel_centrl <= auto_out_config_sel; + auto_in_config_sel_quad_up <= '0'; + auto_in_config_sel_quad_down <= '0'; + auto_in_singleorbundle <= (NOT(cram_rindv_rx) AND cram_rmaster_rx); + + mcmu_auto : cycloneiv_hssi_cmu_auto_speed_neg + PORT MAP ( + refclk => auto_in_refclk, + rxpcs_rst_int => auto_in_rxpcs_rst_int, + rate => auto_in_rate, + gen2ngen1 => auto_in_gen2ngen1, + config_sel_centrl => auto_in_config_sel_centrl, + config_sel_quad_up => auto_in_config_sel_quad_up, + config_sel_quad_down => auto_in_config_sel_quad_down, + rindv_rx => cram_rindv_rx, + rmaster_rx => cram_rmaster_rx, + rmaster_up_rx => cram_rmaster_up_rx, + rauto_speed_ena => cram_rauto_speed_ena, + singleorbundle => auto_in_singleorbundle, + rphfifo_regmode_rx => cram_rphfifo_regmode_rx, + rpma_done_count => cram_rpma_done_count, + rauto_deassert_pc_rst_cnt => cram_rauto_deassert_pc_rst_cnt, + rauto_pc_en_cnt => cram_rauto_pc_en_cnt, + rwait_for_phfifo_cnt => cram_rwait_for_phfifo_cnt, + config_sel => auto_out_config_sel, + pcie_switch => auto_out_pcie_switch, + speed_change => auto_out_speed_change, + dis_pc_byte => auto_out_dis_pc_byte, + reset_pc_ptrs => auto_out_reset_pc_ptrs, + cs => auto_out_cs + ); + + --///////////////////////////////////////////////////////////////////////// + -- rx_ctl_ctrl --------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + rxctrl_in_soft_reset <= rxrst_int; -- from centrl_reset + rxctrl_in_clk_2 <= rxclk_ctl_out_clk_2_b; + rxctrl_in_rx_rd_clk <= rxclk_ctl_out_rx_rd_clk; + rxctrl_in_rx_wr_clk <= rxclk_ctl_out_rx_wr_clk; + rxctrl_in_scan_mode <= scanmode_in; + rxctrl_in_rxfifo_urst <= rxphfiforeset_in; + rxctrl_in_pld_wr_dis <= rxphfifowrdisable_in; + rxctrl_in_pld_re <= rxphfifordenable_in; + rxctrl_in_dis_pc_byte <= auto_out_dis_pc_byte; + + mcmu_rx_ctrl : cycloneiv_hssi_cmu_rx_ctrl + PORT MAP ( + soft_reset => rxctrl_in_soft_reset, + clk_2 => rxctrl_in_clk_2, + rx_rd_clk => rxctrl_in_rx_rd_clk, + rx_wr_clk => rxctrl_in_rx_wr_clk, + scan_mode => rxctrl_in_scan_mode, + rrxfifo_urst_en => cram_rrxfifo_urst_en, + rxfifo_urst => rxctrl_in_rxfifo_urst, + rrxphfifopldctl_en => cram_rrxphfifopldctl_en, + pld_wr_dis => rxctrl_in_pld_wr_dis, + pld_re => rxctrl_in_pld_re, + dis_pc_byte => rxctrl_in_dis_pc_byte, + rauto_speed_ena => cram_rauto_speed_ena, + + rx_we_out => rxctrl_out_rx_we_out, + wr_enable_out => rxctrl_out_wr_enable_out, + rd_enable_out => rxctrl_out_rd_enable_out + ); + + --///////////////////////////////////////////////////////////////////////// + -- rx_ctl_ctrl --------------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + txctrl_in_soft_reset <= txrst_int; + txctrl_in_fifo_wr_clk <= txclk_ctl_out_wr_clk_pos; + txctrl_in_fifo_rd_clk <= txclk_ctl_out_fifo_rd_clk; + txctrl_in_refclk_b_in <= txclk_ctl_out_refclk_b; + txctrl_in_scan_mode <= scanmode_in; + txctrl_in_txfifo_urst <= txphfiforeset_in; + txctrl_in_pld_we <= txphfifowrenable_in; + txctrl_in_pld_rd_dis <= txphfiforddisable_in; + txctrl_in_dis_pc_byte <= auto_out_dis_pc_byte; + + mcmu_tx_ctrl : cycloneiv_hssi_cmu_tx_ctrl + PORT MAP ( + soft_reset => txctrl_in_soft_reset, + fifo_wr_clk => txctrl_in_fifo_wr_clk, + fifo_rd_clk => txctrl_in_fifo_rd_clk, + refclk_b_in => txctrl_in_refclk_b_in, + scan_mode => txctrl_in_scan_mode, + rtxfifo_urst_en => cram_rtxfifo_urst_en, + txfifo_urst => txctrl_in_txfifo_urst, + rtxphfifopldctl_en => cram_rtxphfifopldctl_en, + pld_we => txctrl_in_pld_we, + pld_rd_dis => txctrl_in_pld_rd_dis, + dis_pc_byte => txctrl_in_dis_pc_byte, + rauto_speed_ena => cram_rauto_speed_ena, + + wr_enable_out => txctrl_out_wr_enable_out, + rd_enable_out => txctrl_out_rd_enable_out, + fifo_select_out => txctrl_out_fifo_select_out + ); + + + --///////////////////////////////////////////////////////////////////////// + -- instantiate DSKW SM ------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + dskw_sm_clk <= clk_1_b WHEN (init_in_xaui_mode = '1') ELSE + '0'; + + --.clk_1 (clk_1_b), + xhdl13 <= ("1111" & adet); + xhdl14 <= ("1111" & rdalign); + xhdl15 <= ("1111" & syncstatus); + dskw_sm_1 : cycloneiv_hssi_dskw_sm + PORT MAP ( + soft_reset => rxrst_int, + clk_1 => dskw_sm_clk, + octal_mode => '0', + align_det_sync => xhdl13, + rd_align => xhdl14, + sync_status => xhdl15, + align_status => alignstatus_int, + enable_deskew => enabledeskew_xhdl2, + fifo_reset_rd => fiforesetrd_xhdl3, + curr_state => dskw_curr_st + ); + + --///////////////////////////////////////////////////////////////////////// + -- instantiate TX SM --------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + tx_sm_clk <= refclk_b WHEN (init_in_xaui_mode = '1') ELSE + '0'; + tx_sm_datain <= txdatain WHEN (init_in_xaui_mode = '1') ELSE + "00000000000000000000000000000000"; + tx_sm_ctrlin <= txctrl WHEN (init_in_xaui_mode = '1') ELSE + "0000"; + tx_sm_rdenablesyncin <= rdenablesync WHEN (init_in_xaui_mode = '1') ELSE + '0'; + + rtx_rx_local_fault_clr_int <= '0'; + rindv_tx_int <= '0'; -- tx sm just sends K when set + + tx_sm_1 : cycloneiv_hssi_tx_sm + PORT MAP ( + tx_clk => tx_sm_clk, + --.tx_clk (refclk_b), + soft_reset => txrst_int, + indv => rindv_tx_int, + tx_data => tx_sm_datain, + --.tx_data (txdatain), + tx_ctl => tx_sm_ctrlin, + --.tx_ctl (txctrl), + rd_enable_sync => tx_sm_rdenablesyncin, + --.rd_enable_sync (rdenablesync), + tx_local_fault_clr => gnd_wire, --shared with tx_sm + sm_data => txdataout_xhdl10, + sm_ctl => txctrlout_xhdl9, + tx_local_fault_det => tx_local_fault_det, -- to rcv_sm + tx_local_fault => tx_local_fault_int, + curr_state => tx_curr_st, + rxaui_s2gx_en => cram_rxaui_s2gx_en_tx + ); + + --///////////////////////////////////////////////////////////////////////// + -- instantiate RX SM --------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + rcv_sm_clk <= clk_2_b WHEN (init_in_xaui_mode = '1') ELSE + '0'; + rcv_sm_decdatavalid <= rxdatavalid WHEN (init_in_xaui_mode = '1') ELSE + "0001"; + rcv_sm_decdata <= rxdatain WHEN (init_in_xaui_mode = '1') ELSE + "00000000000000000000000000000000"; + rcv_sm_decctl <= rxctrl WHEN (init_in_xaui_mode = '1') ELSE + "0000"; + rcv_sm_rxrunningdisp <= rxrunningdisp WHEN (init_in_xaui_mode = '1') ELSE + "0000"; + + rindv_rx_int <= '0'; + rxs_link_status_set_int <= '0'; + + rcv_sm_1 : cycloneiv_hssi_rcv_sm + PORT MAP ( + clk_2 => rcv_sm_clk, + soft_reset => rxrst_int, + indv => rindv_rx_int, + dec_data_valid => rcv_sm_decdatavalid, + dec_data => rcv_sm_decdata, + dec_ctl => rcv_sm_decctl, + running_disp => rcv_sm_rxrunningdisp, + rx_local_fault_clr => gnd_wire, --shared with tx_sm + xs_link_status_set => gnd_wire, + tx_local_fault_det => tx_local_fault_det, -- from tx_sm + rx_data_rs => rxdataout_xhdl6, + rx_ctl_rs => rxctrlout_xhdl5, + rx_local_fault => rx_local_fault_int, + xs_link_status => xs_link_status_int, + curr_state => rcv_curr_st, + rxaui_s2gx_en => cram_rxaui_s2gx_en_rx + ); + + --///////////////////////////////////////////////////////////////////////// + -- instantiate DPRIO_CONTROL_TOP --------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + port_addr <= int2bin(portaddr, 5) - "00001"; --port_address-1; int (1-based into 0-based) to 5'b conversion + dev_addr <= int2bin(devaddr, 5) - "00001"; --device_address-1; int (1-based into 0-based)to 5'b conversion + + mdio_in <= dprioin_in; + mdio_rst <= mdio_rst_reg; -- ~(plniotri & ~entest & npor); + PROCESS + BEGIN + mdio_rst_reg <= '1'; + WAIT FOR 1000 ps; + mdio_rst_reg <= '0'; + WAIT; + END PROCESS; + + cmudprioin <= "00000000000000000000000000000X"; + + control_top_0 : cycloneiv_hssi_cmu_dprio_top + GENERIC MAP ( + + rx0_logical_to_physical_mapping => rx0_logical_to_physical_mapping, + rx1_logical_to_physical_mapping => rx1_logical_to_physical_mapping, + rx2_logical_to_physical_mapping => rx2_logical_to_physical_mapping, + rx3_logical_to_physical_mapping => rx3_logical_to_physical_mapping, + tx0_logical_to_physical_mapping => tx0_logical_to_physical_mapping, + tx1_logical_to_physical_mapping => tx1_logical_to_physical_mapping, + tx2_logical_to_physical_mapping => tx2_logical_to_physical_mapping, + tx3_logical_to_physical_mapping => tx3_logical_to_physical_mapping, + + sim_dump_dprio_internal_reg_at_time => sim_dump_dprio_internal_reg_at_time, + sim_dump_filename => sim_dump_filename + ) + PORT MAP ( + refclkdividerdprioin => refclkdividerdprioin, + rxpcsdprioin => rxpcsdprioin, + rxpmadprioin => rxpmadprioin, + txpcsdprioin => txpcsdprioin, + txpmadprioin => txpmadprioin, + refclkdividerdprioout => refclkdividerdprioout_xhdl4, + rxpcsdprioout => rxpcsdprioout_xhdl7, + rxpmadprioout => rxpmadprioout_xhdl8, + txpcsdprioout => txpcsdprioout_xhdl11, + txpmadprioout => txpmadprioout_xhdl12, + sync_status => syncstatus, + align_status => alignstatus_int, + dprioload => dprioload_in, + mdio_in => mdio_in, + mdc => dpclk_in, + port_addr => port_addr, + dev_addr => dev_addr, + mdio_dis => dpriodisable_in, + mdio_rst => mdio_rst, + mdio_out => dprioout_tim, + data_enable_n => dpriooe_tim, + mdio_curr_st => mdio_curr_st + ); + + --///////////////////////////////////////////////////////////////////////// + -- establish outputs --------------------------------------------------- // + --///////////////////////////////////////////////////////////////////////// + + alignstatus <= alignstatus_int; -- from dskw_sm + dpriodisableout <= dpriodisable_in; -- from top + digitaltestout <= "000000000X"; -- 10 Test ports + + -- reset and powerdown - everything turns into Active High --------------- + pllresetout <= ( (NOT(qr_out_cmu1_cru_rstb) OR NOT(qr_out_cmu1_rxpma_rstb)) & (NOT(qr_out_cmu0_cru_rstb) OR NOT(qr_out_cmu0_rxpma_rstb)) ); + quadresetout <= qr_out_hard_reset; + + rxadceresetout <= NOT(chr_out_adce_rstb); + rxanalogresetout <= NOT(chr_out_rxpma_rstb(3 DOWNTO 0)); + rxcruresetout <= (NOT(chr_out_cru_rstb)) OR (NOT(chr_out_rxpma_rstb)); + rxdigitalresetout <= chr_out_rxpcs_rst; + txanalogresetout <= NOT(chr_out_txpma_rstb(3 DOWNTO 0)); + txdigitalresetout <= chr_out_txpcs_rst; + + clkdivpowerdn <= (NOT(qr_out_cmu1_cgb_pdb) & NOT(qr_out_cmu0_cgb_pdb)); + pllpowerdn <= (NOT(qr_out_cmu1_cru_pdb) & NOT(qr_out_cmu0_cru_pdb)); + + rxadcepowerdown <= NOT(chr_out_adce_pdb); + rxcrupowerdown <= NOT(chr_out_cru_pdb(3 DOWNTO 0)); + rxibpowerdown <= NOT(chr_out_rx_pdb(3 DOWNTO 0)); -- cycloneiv_modify + txdetectrxpowerdown <= NOT(chr_out_rx_det_pdb(3 DOWNTO 0)); + txdividerpowerdown <= NOT(chr_out_cgb_pdb(3 DOWNTO 0)); + txobpowerdown <= NOT(chr_out_tx_pdb(3 DOWNTO 0)); -- cycloneiv_modify + + -- ww47_out + autospdx4configsel <= auto_out_config_sel; + autospdx4rateswitchout <= auto_out_pcie_switch; + autospdx4spdchg <= auto_out_speed_change; + phfifiox4ptrsreset <= auto_out_reset_pc_ptrs; + rxphfifox4byteselout <= rxctrl_out_rx_we_out; + rxphfifox4wrclkout <= rxclk_ctl_out_rx_div2_sync_out; + rxphfifox4rdenableout <= rxctrl_out_rd_enable_out; + rxphfifox4wrenableout <= rxctrl_out_wr_enable_out; + scanout <= "ZZZZZZZZZZZZZZZZZZZZZZZ"; + txphfifox4byteselout <= txctrl_out_fifo_select_out; + txphfifox4rdclkout <= txclk_ctl_out_tx_div2_sync_out; + txphfifox4rdenableout <= txctrl_out_rd_enable_out; + txphfifox4wrenableout <= txctrl_out_wr_enable_out; + +--------------------------------------------------------------------------- +-- Cyclone IV GX specific ------------------------------------------------------ +-- - refclkout, coreclkout generations -- +--------------------------------------------------------------------------- + +coreclkout_div2_clkin <= refclkout_tmp AND cram_rrefclk_out_div2; +coreclkout_div2_reset <= refclkout_tmp AND ( NOT cram_rfreerun_centrl); + +PROCESS(coreclkout_div2_clkin, coreclkout_div2_reset) +BEGIN + IF (coreclkout_div2_reset'EVENT AND coreclkout_div2_reset = '1')THEN + coreclkout_div2_clkout <= '0'; + ELSIF (coreclkout_div2_clkin'EVENT AND coreclkout_div2_clkin = '1') THEN + coreclkout_div2_clkout <= (NOT coreclkout_div2_clkout); + END IF; +END PROCESS; + + +refclkout_tmp <= refclkdig WHEN (cram_rcentrl_clk_sel = '1') ELSE txclk; + +refclkout <= refclkout_tmp; +coreclkout <= coreclkout_div2_clkout WHEN (cram_rrefclk_out_div2 = '1') ELSE refclkout_tmp; + +END trans; + + +-- +-- +-- no digital behavior to simulate +-- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +USE WORK.cycloneiv_hssi_components.ALL; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; + +ENTITY cycloneiv_hssi_calibration_block IS + GENERIC ( + -- generic control parameters -- + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + -- tipd :interconnect path delays -- + tipd_clk : VitalDelayType01 := DefpropDelay01; + lpm_type : string := "cycloneiv_hssi_calibration_block"; + cont_cal_mode : string := "false"; + enable_rx_cal_tw : string := "false"; + enable_tx_cal_tw : string := "false"; + migrated_from_prev_family : string := "false"; + rtest : string := "false"; + rx_cal_wt_value : integer := 0; + send_rx_cal_status : string := "true"; + tx_cal_wt_value : integer := 1); + PORT ( + clk : IN std_logic := '0'; + powerdn : IN std_logic := '0'; + testctrl : IN std_logic := '0'; + calibrationstatus : OUT std_logic_vector(4 DOWNTO 0); + nonusertocmu : OUT std_logic + ); +END cycloneiv_hssi_calibration_block; + +ARCHITECTURE sim_calib_arch OF cycloneiv_hssi_calibration_block IS + + SIGNAL calibrationstatus_xhdl1 : std_logic_vector(4 DOWNTO 0) := "11111"; + +BEGIN + calibrationstatus <= calibrationstatus_xhdl1; + +END sim_calib_arch; diff --git a/Common/sim/altera/cycloneiv_hssi_components.vhd b/Common/sim/altera/cycloneiv_hssi_components.vhd new file mode 100644 index 0000000..9243297 --- /dev/null +++ b/Common/sim/altera/cycloneiv_hssi_components.vhd @@ -0,0 +1,1354 @@ +-- Copyright (C) Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; + +USE IEEE.vital_timing.ALL; +USE IEEE.vital_primitives.ALL; + + +package CYCLONEIV_HSSI_COMPONENTS is + + + +-- VITAL constants BEGIN +-- default generic values + CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns); + CONSTANT DefSetupHoldCnst : TIME := 0 ns; + CONSTANT DefPulseWdthCnst : TIME := 0 ns; +-- default control options +-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent; +-- change default delay type to Transport : for spr 68748 + CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport; + CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE; + CONSTANT DefGlitchXOn : BOOLEAN := FALSE; + CONSTANT DefMsgOnChecks : BOOLEAN := TRUE; + CONSTANT DefXOnChecks : BOOLEAN := TRUE; +-- output strength mapping + -- UX01ZWHL- + CONSTANT PullUp : VitalOutputMapType := "UX01HX01X"; + CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X"; + CONSTANT PullDown : VitalOutputMapType := "UX01LX01X"; +-- primitive result strength mapping + CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' ); + CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' ); + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) +-- VITAL constants END + +-- GENERIC utility functions BEGIN +function bin2int (s : std_logic_vector) return integer; +function bin2int (s : std_logic) return integer; +function int2bit (arg : boolean) return std_logic; +function str2bin (s : string) return std_logic_vector; +function str2int (s : string) return integer; +function int2bin (arg : integer; size : integer) return std_logic_vector; +function int2bin (arg : boolean; size : integer) return std_logic_vector; +function int2bit (arg : integer) return std_logic; + +function tx_top_ctrl_in_width( + double_data_mode : string; + ser_double_data_mode : string +) return integer; +function rx_top_a1k1_out_width(des_double_data_mode : string) return integer; +function rx_top_ctrl_out_width( + double_data_mode : string; + des_double_data_mode : string +) return integer; + +function rx_top_basic_width (channel_width : integer) return integer; +function rx_top_num_of_basic (channel_width : integer) return integer; + + +function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME; +function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector; +function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector; +function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic; +function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic; +function reduction_or (val : std_logic_vector) return std_logic; +function reduction_nor (val : std_logic_vector) return std_logic; +function reduction_xor (val : std_logic_vector) return std_logic; +function reduction_and (val : std_logic_vector) return std_logic; +function reduction_nand (val : std_logic_vector) return std_logic; +function alpha_tolower (given_string : string) return string; + +function cycloneiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string; +function cycloneiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer; +function cycloneiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer; + + +-- GENERIC utility functions END + + +TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE); + + +-- +-- cycloneiv_hssi_tx_pma +-- + +COMPONENT cycloneiv_hssi_tx_pma +GENERIC ( + enable_diagnostic_loopback : STRING := "false"; + enable_reverse_serial_loopback : STRING := "false"; + enable_txclkout_loopback : STRING := "false"; + lpm_type : STRING := "cycloneiv_hssi_tx_pma"; + channel_number : INTEGER := 0; + common_mode : STRING := "0.65V"; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + logical_channel_address : INTEGER := 0; + preemp_tap_1 : INTEGER := 0; + protocol_hint : STRING := "basic"; + effective_data_rate : STRING := "unused"; + rx_detect : INTEGER := 0; + serialization_factor : INTEGER := 8; + slew_rate : STRING := "low"; + termination : STRING := "OCT 100 Ohms"; + use_external_termination : STRING := "false"; + use_rx_detect : STRING := "false"; + vod_selection : INTEGER := 0 +); +PORT ( + cgbpowerdn : IN STD_LOGIC := '0'; + datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); + detectrxpowerdown : IN STD_LOGIC := '0'; + diagnosticlpbkin : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0'); + fastrefclk0in : IN STD_LOGIC := '0'; + forceelecidle : IN STD_LOGIC := '0'; + powerdn : IN STD_LOGIC := '0'; + refclk0in : IN STD_LOGIC := '0'; + refclk0inpulse : IN STD_LOGIC := '0'; + reverselpbkin : IN STD_LOGIC := '0'; + rxdetectclk : IN STD_LOGIC := '0'; + rxdetecten : IN STD_LOGIC := '0'; + txpmareset : IN STD_LOGIC := '0'; + clockout : OUT STD_LOGIC; + dataout : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0); + rxdetectvalidout : OUT STD_LOGIC; + rxfoundout : OUT STD_LOGIC; + seriallpbkout : OUT STD_LOGIC +); +END COMPONENT; + +-- +-- cycloneiv_hssi_rx_pma +-- + +COMPONENT cycloneiv_hssi_rx_pma + GENERIC ( + lpm_type : STRING := "cycloneiv_hssi_rx_pma"; + allow_serial_loopback : STRING := "false"; + channel_number : INTEGER := 0; + common_mode : STRING := "0.82V"; + deserialization_factor : INTEGER := 8; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + enable_local_divider : STRING := "false"; + enable_dpa_shift : STRING := "false"; + enable_initial_phase_selection : STRING := "false"; + enable_pd_counter_accumulate_mode : STRING := "false"; + enable_ltd : STRING := "false"; + enable_ltr : STRING := "false"; + eq_dc_gain : INTEGER := 0; + eq_setting : INTEGER := 1; + force_signal_detect : STRING := "true"; + initial_phase_value : INTEGER := 0; + logical_channel_address : INTEGER := 0; + offset_cancellation : INTEGER := 0; + pi_frequency_selector : INTEGER := 0; + ppm_gen1_2_xcnt_en : INTEGER := 1; + ppm_post_eidle : INTEGER := 0; + pd1_counter_setting : INTEGER := 5; + pd2_counter_setting : INTEGER := 5; + pd_rising_edge_only : STRING := "false"; + phase_step_add_setting : INTEGER := 2; + phase_step_sub_setting : INTEGER := 1; + ppmselect : INTEGER := 0; + protocol_hint : STRING := "basic"; + effective_data_rate : STRING := "unused"; + send_reverse_serial_loopback_data : STRING := "false"; + send_reverse_serial_loopback_recovered_clk : STRING := "false"; + signal_detect_hysteresis : INTEGER := 4; + signal_detect_hysteresis_valid_threshold : INTEGER := 1; + signal_detect_loss_threshold : INTEGER := 1; + termination : STRING := "OCT 100 Ohms"; + use_external_termination : STRING := "false"; + loop_1_digital_filter : INTEGER := 8; + enable_second_order_loop : STRING := "false" + ); + PORT ( + crupowerdn : IN STD_LOGIC := '0'; + datain : IN STD_LOGIC := '0'; + deserclock : IN STD_LOGIC := '0'; + dpashift : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0'); + locktodata : IN STD_LOGIC := '0'; + locktoref : IN STD_LOGIC := '0'; + powerdn : IN STD_LOGIC := '0'; + ppmdetectrefclk : IN STD_LOGIC := '0'; + rxpmareset : IN STD_LOGIC := '0'; + seriallpbkin : IN STD_LOGIC := '0'; + testbussel : IN STD_LOGIC_VECTOR(3 DOWNTO 0):= (others => '0'); + analogtestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + clockout : OUT STD_LOGIC; + datastrobeout : OUT STD_LOGIC; + diagnosticlpbkout : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0); + freqlocked : OUT STD_LOGIC; + locktorefout : OUT STD_LOGIC; + recoverdataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + reverselpbkout : OUT STD_LOGIC; + signaldetect : OUT STD_LOGIC + ); +END COMPONENT; + +-- +-- cycloneiv_hssi_tx_pcs +-- + +COMPONENT cycloneiv_hssi_tx_pcs + GENERIC ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_coreclk : VitalDelayType01 := DefpropDelay01; + tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_detectrxloop : VitalDelayType01 := DefpropDelay01; + tipd_digitalreset : VitalDelayType01 := DefpropDelay01; + tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01; + tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01; + tipd_forceelecidle : VitalDelayType01 := DefpropDelay01; + tipd_freezptr : VitalDelayType01 := DefpropDelay01; + tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01; + tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01; + tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01; + tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_invpol : VitalDelayType01 := DefpropDelay01; + tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_localrefclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01; + tipd_phfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01; + tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01; + tipd_pipetxswing : VitalDelayType01 := DefpropDelay01; + tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_prbscidenable : VitalDelayType01 := DefpropDelay01; + tipd_quadreset : VitalDelayType01 := DefpropDelay01; + tipd_rateswitch : VitalDelayType01 := DefpropDelay01; + tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01; + tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01; + tipd_refclk : VitalDelayType01 := DefpropDelay01; + tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_xgmctrl : VitalDelayType01 := DefpropDelay01; + tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); + tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01; + lpm_type : STRING := "cycloneiv_hssi_tx_pcs"; + allow_polarity_inversion : STRING := "false"; + bitslip_enable : STRING := "false"; + channel_bonding : STRING := "none"; -- none, x8, x4 + channel_number : INTEGER := 0; + channel_width : INTEGER := 8; + core_clock_0ppm : STRING := "false"; + datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL= + datapath_protocol : STRING := "basic"; --replaced by protocol_hint + disable_ph_low_latency_mode : STRING := "false"; + disparity_mode : STRING := "none"; -- legacy, new, none + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6> + enable_bit_reversal : STRING := "false"; + enable_idle_selection : STRING := "false"; + enable_phfifo_bypass : STRING := "false"; + enable_reverse_parallel_loopback : STRING := "false"; + enable_self_test_mode : STRING := "false"; + enc_8b_10b_compatibility_mode : STRING := "true"; + enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none + force_echar : STRING := "false"; + force_kchar : STRING := "false"; + hip_enable : STRING := "false"; + logical_channel_address : INTEGER := 0; + migrated_from_prev_family : STRING := "false"; + ph_fifo_reg_mode : STRING := "false"; + ph_fifo_reset_enable : STRING := "false"; + ph_fifo_user_ctrl_enable : STRING := "false"; + pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL= + prbs_cid_pattern : STRING := "false"; + prbs_cid_pattern_length : INTEGER := 0; + protocol_hint : STRING := "basic"; + refclk_select : STRING := "local"; -- cmu_clk_divider + reset_clock_output_during_digital_reset : STRING := "false"; + self_test_mode : STRING := "incremental"; + use_double_data_mode : STRING := "false"; + wr_clk_mux_select : STRING := "core_clk" -- INT_CLK // int_clk + ); + PORT ( + bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0'); + coreclk : IN STD_LOGIC := '0'; + ctrlenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); + datainfull : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE + detectrxloop : IN STD_LOGIC := '0'; + digitalreset : IN STD_LOGIC := '0'; + dispval : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0'); + elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + enrevparallellpbk : IN STD_LOGIC := '0'; + forcedisp : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); --fix_width + forceelecidle : IN STD_LOGIC := '0'; + hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); + hipdetectrxloop : IN STD_LOGIC := '0'; + hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + hipforceelecidle : IN STD_LOGIC := '0'; + hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + invpol : IN STD_LOGIC := '0'; + localrefclk : IN STD_LOGIC := '0'; + phfiforddisable : IN STD_LOGIC := '0'; + phfiforeset : IN STD_LOGIC := '0'; + phfifowrenable : IN STD_LOGIC := '1'; + phfifox4bytesel : IN STD_LOGIC := '0'; + phfifox4rdclk : IN STD_LOGIC := '0'; + phfifox4rdenable : IN STD_LOGIC := '0'; + phfifox4wrenable : IN STD_LOGIC := '0'; + pipestatetransdone : IN STD_LOGIC := '0'; + pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing + powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + prbscidenable : IN STD_LOGIC := '0'; + quadreset : IN STD_LOGIC := '0'; + refclk : IN STD_LOGIC := '0'; + revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); + xgmctrl : IN STD_LOGIC := '0'; + xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + clkout : OUT STD_LOGIC; + coreclkout : OUT STD_LOGIC; + dataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0); + forceelecidleout : OUT STD_LOGIC; + grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + hiptxclkout : OUT STD_LOGIC; + parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + phfifooverflow : OUT STD_LOGIC; + phfiforddisableout : OUT STD_LOGIC; + phfiforesetout : OUT STD_LOGIC; + phfifounderflow : OUT STD_LOGIC; + phfifowrenableout : OUT STD_LOGIC; + pipeenrevparallellpbkout : OUT STD_LOGIC; + pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rdenablesync : OUT STD_LOGIC; + txdetectrx : OUT STD_LOGIC; + xgmctrlenable : OUT STD_LOGIC; + xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +-- +-- cycloneiv_hssi_rx_pcs +-- + +COMPONENT cycloneiv_hssi_rx_pcs + GENERIC ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + tipd_a1a2size : VitalDelayType01 := DefpropDelay01; + tipd_alignstatus : VitalDelayType01 := DefpropDelay01; + tipd_alignstatussync : VitalDelayType01 := DefpropDelay01; + tipd_bitslip : VitalDelayType01 := DefpropDelay01; + tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01; + tipd_coreclk : VitalDelayType01 := DefpropDelay01; + tipd_datain : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_digitalreset : VitalDelayType01 := DefpropDelay01; + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_dprioin : VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_elecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_enabledeskew : VitalDelayType01 := DefpropDelay01; + tipd_enabyteord : VitalDelayType01 := DefpropDelay01; + tipd_enapatternalign : VitalDelayType01 := DefpropDelay01; + tipd_fifordin : VitalDelayType01 := DefpropDelay01; + tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01; + tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01; + tipd_hipelecidleinfersel : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_hippowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_invpol : VitalDelayType01 := DefpropDelay01; + tipd_localrefclk : VitalDelayType01 := DefpropDelay01; + tipd_masterclk : VitalDelayType01 := DefpropDelay01; + tipd_parallelfdbk : VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phfifordenable : VitalDelayType01 := DefpropDelay01; + tipd_phfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01; + tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01; + tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01; + tipd_pipepowerdown : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pipepowerstate : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_powerdn : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_prbscidenable : VitalDelayType01 := DefpropDelay01; + tipd_quadreset : VitalDelayType01 := DefpropDelay01; + tipd_recoveredclk : VitalDelayType01 := DefpropDelay01; + tipd_refclk : VitalDelayType01 := DefpropDelay01; + tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01; + tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01; + tipd_rmfifordena : VitalDelayType01 := DefpropDelay01; + tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01; + tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01; + tipd_rxfound : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_signaldetected : VitalDelayType01 := DefpropDelay01; + tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01; + tipd_xgmdatain : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); + tsetup_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_phfifordenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_coreclk_a1a2sizeout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_byteorderalignstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_ctrldetect_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_dataout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_dataoutfull_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_disperr_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_errdetect_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_patterndetect_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_rmfifodatadeleted_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_rmfifodatainserted_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_runningdisp_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_syncstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tpd_coreclk_pipestatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_pipephydonestatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_coreclk_pipedatavalid_posedge : VitalDelayType01 := DefPropDelay01; + lpm_type : STRING := "cycloneiv_hssi_rx_pcs"; + auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0; + auto_spd_phystatus_notify_count : INTEGER := 0; + align_ordered_set_based : STRING := "false"; + align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length; + align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>; + align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- ; + allow_align_polarity_inversion : STRING := "false"; + allow_pipe_polarity_inversion : STRING := "false"; + bit_slip_enable : STRING := "false"; + byte_order_back_compat_enable : STRING := "false"; + byte_order_invalid_code_or_run_disp_error : STRING := "false"; + byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode + byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>; + byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>; + byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165 + cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0; + cdrctrl_cid_mode_enable : STRING := "false"; + cdrctrl_enable : STRING := "false"; + cdrctrl_mask_cycle : INTEGER := 0; + cdrctrl_min_lock_to_ref_cycle : INTEGER := 0; + cdrctrl_rxvalid_mask : STRING := "false"; + channel_bonding : STRING := "none"; -- ; + channel_number : INTEGER := 0; -- ; + channel_width : INTEGER := 10; -- ; + clk1_mux_select : STRING := "recvd_clk"; -- ; + clk2_mux_select : STRING := "recvd_clk"; -- ; + clk_pd_enable : STRING := "false"; --ww47_cram_p1 + core_clock_0ppm : STRING := "false"; + datapath_low_latency_mode : STRING := "false"; + datapath_protocol : STRING := "basic"; -- replaced by protocol_hint + dec_8b_10b_compatibility_mode : STRING := "true"; + dec_8b_10b_mode : STRING := "none"; -- ; + deskew_pattern : STRING := "1100111100"; -- K28.3 + disable_auto_idle_insertion : STRING := "false"; + disable_running_disp_in_word_align : STRING := "false"; + disallow_kchar_after_pattern_ordered_set : STRING := "false"; + elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false"; + elec_idle_gen1_sigdet_enable : STRING := "false"; + elec_idle_infer_enable : STRING := "false"; + elec_idle_num_com_detect : INTEGER := 0; + enable_bit_reversal : STRING := "false"; + enable_self_test_mode : STRING := "false"; + error_from_wa_or_8b_10b_select : STRING := "false"; + force_signal_detect_dig : STRING := "false"; + hip_enable : STRING := "false"; + infiniband_invalid_code : INTEGER := 0; -- ; + insert_pad_on_underflow : STRING := "false"; + logical_channel_address : INTEGER := 0; + num_align_code_groups_in_ordered_set : INTEGER := 1; -- ; + num_align_cons_good_data : INTEGER := 3; -- wordalign; + num_align_cons_pat : INTEGER := 4; -- ; + num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num + ph_fifo_low_latency_enable : STRING := "false"; + ph_fifo_reg_mode : STRING := "false"; + ph_fifo_reset_enable : STRING := "false"; + ph_fifo_user_ctrl_enable : STRING := "false"; + phystatus_delay : INTEGER := 0; + phystatus_reset_toggle : STRING := "false"; + pipe_auto_speed_nego_enable : STRING := "false"; + prbs_all_one_detect : STRING := "false"; + prbs_cid_pattern : STRING := "false"; + prbs_cid_pattern_length : INTEGER := 0; + protocol_hint : STRING := "basic"; + rate_match_back_to_back : STRING := "false"; + rate_match_delete_threshold : INTEGER := 13; + rate_match_empty_threshold : INTEGER := 5; + rate_match_fifo_mode : STRING := "false"; -- in s2gx, bool in s4gx; + rate_match_full_threshold : INTEGER := 20; + rate_match_insert_threshold : INTEGER := 11; + rate_match_ordered_set_based : STRING := "false"; -- ; + rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>; + rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>; + rate_match_pattern_size : INTEGER := 10; -- ; + rate_match_pipe_enable : STRING := "false"; + rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom + rate_match_skip_set_based : STRING := "false"; + rate_match_start_threshold : INTEGER := 7; + rd_clk_mux_select : STRING := "int clock"; -- ; + recovered_clk_mux_select : STRING := "recovered clock"; -- ; + reset_clock_output_during_digital_reset : STRING := "false"; + run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>; + run_length_enable : STRING := "false"; + rx_detect_bypass : STRING := "false"; + rx_phfifo_wait_cnt : INTEGER := 32; + rxstatus_error_report_mode : INTEGER := 0; + self_test_mode : STRING := "incremental"; -- ; + test_bus_sel : INTEGER := 0; + use_alignment_state_machine : STRING := "false"; + use_deskew_fifo : STRING := "false"; + use_double_data_mode : STRING := "false"; + use_parallel_loopback : STRING := "false"; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000" + ); + PORT ( + a1a2size : IN STD_LOGIC := '0'; + alignstatus : IN STD_LOGIC := '0'; + alignstatussync : IN STD_LOGIC := '0'; + bitslip : IN STD_LOGIC := '0'; + cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr + coreclk : IN STD_LOGIC := '0'; + datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0'); --NEW: updated width + digitalreset : IN STD_LOGIC := '0'; + elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + enabledeskew : IN STD_LOGIC := '0'; + enabyteord : IN STD_LOGIC := '0'; + enapatternalign : IN STD_LOGIC := '0'; + fifordin : IN STD_LOGIC := '0'; + fiforesetrd : IN STD_LOGIC := '0'; + grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); + hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity + hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch + hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch + invpol : IN STD_LOGIC := '0'; + localrefclk : IN STD_LOGIC := '0'; + masterclk : IN STD_LOGIC := '0'; + parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); + phfifordenable : IN STD_LOGIC := '1'; + phfiforeset : IN STD_LOGIC := '0'; + phfifowrdisable : IN STD_LOGIC := '0'; + phfifox4bytesel : IN STD_LOGIC := '0'; + phfifox4rdenable : IN STD_LOGIC := '0'; + phfifox4wrclk : IN STD_LOGIC := '0'; + phfifox4wrenable : IN STD_LOGIC := '0'; + pipe8b10binvpolarity : IN STD_LOGIC := '0'; + pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0'; + pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); + powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en + quadreset : IN STD_LOGIC := '0'; + recoveredclk : IN STD_LOGIC := '0'; + refclk : IN STD_LOGIC := '0'; + revbitorderwa : IN STD_LOGIC := '0'; + rmfifordena : IN STD_LOGIC := '0'; + rmfiforeset : IN STD_LOGIC := '0'; + rmfifowrena : IN STD_LOGIC := '0'; + rxdetectvalid : IN STD_LOGIC := '0'; + rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); + signaldetected : IN STD_LOGIC := '0'; + xauidelcondmet : IN STD_LOGIC := '0'; + xauififoovr : IN STD_LOGIC := '0'; + xauiinsertincomplete : IN STD_LOGIC := '0'; + xauilatencycomp : IN STD_LOGIC := '0'; + xgmctrlin : IN STD_LOGIC := '0'; + xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins --- + wareset : IN STD_LOGIC := '0'; + revbyteorderwa : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0'); + a1a2sizeout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + a1detect : OUT STD_LOGIC; + a2detect : OUT STD_LOGIC; + adetectdeskew : OUT STD_LOGIC; + alignstatussyncout : OUT STD_LOGIC; + bistdone : OUT STD_LOGIC; + bisterr : OUT STD_LOGIC; + bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary + byteorderalignstatus : OUT STD_LOGIC; + cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD? + cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR. + clkout : OUT STD_LOGIC; + coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU + ctrldetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + dataoutfull : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- new in 6.1 + disperr : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + errdetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + fifordout : OUT STD_LOGIC; + hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0) + hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid + hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle + hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus + hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0) + k1detect : OUT STD_LOGIC; + k2detect : OUT STD_LOGIC; + patterndetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + phfifooverflow : OUT STD_LOGIC; + phfifordenableout : OUT STD_LOGIC; + phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU + phfifounderflow : OUT STD_LOGIC; + phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU + pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + pipedatavalid : OUT STD_LOGIC; + pipeelecidle : OUT STD_LOGIC; + pipephydonestatus : OUT STD_LOGIC; + pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + rdalign : OUT STD_LOGIC; + revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + rlv : OUT STD_LOGIC; + rmfifodatadeleted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rmfifodatainserted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rmfifoempty : OUT STD_LOGIC; + rmfifofull : OUT STD_LOGIC; + runningdisp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + signaldetect : OUT STD_LOGIC; + syncstatus : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + syncstatusdeskew : OUT STD_LOGIC; + xauidelcondmetout : OUT STD_LOGIC; + xauififoovrout : OUT STD_LOGIC; + xauiinsertincompleteout : OUT STD_LOGIC; + xauilatencycompout : OUT STD_LOGIC; + xgmctrldet : OUT STD_LOGIC; + xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + xgmdatavalid : OUT STD_LOGIC; + xgmrunningdisp : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0); + pipestatetransdoneout : OUT STD_LOGIC + ); +END COMPONENT; + +-- +-- cycloneiv_hssi_cmu +-- + +COMPONENT cycloneiv_hssi_cmu + GENERIC ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01; + tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txclk : VitalDelayType01 := DefpropDelay01; + tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_scanclk : VitalDelayType01 := DefpropDelay01; + tipd_rdenablesync : VitalDelayType01 := DefpropDelay01; + tipd_dpclk : VitalDelayType01 := DefpropDelay01; + tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dprioin : VitalDelayType01 := DefpropDelay01; + tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01; + tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01; + tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_scanmode : VitalDelayType01 := DefpropDelay01; + tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01; + tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01; + tipd_txcoreclk : VitalDelayType01 := DefpropDelay01; + tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01; + tipd_dprioload : VitalDelayType01 := DefpropDelay01; + tipd_quadreset : VitalDelayType01 := DefpropDelay01; + tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01; + tipd_scanshift : VitalDelayType01 := DefpropDelay01; + tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_recovclk : VitalDelayType01 := DefpropDelay01; + tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01); + tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01; + lpm_type : STRING := "cycloneiv_hssi_cmu"; + auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0; + auto_spd_phystatus_notify_count : INTEGER := 0; + coreclk_out_gated_by_quad_reset : STRING := "false"; -- cycloneiv_new + devaddr : INTEGER := 1; + dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000"; + in_xaui_mode : STRING := "false"; + pipe_auto_speed_nego_enable : STRING := "false"; + portaddr : INTEGER := 1; + rx0_channel_bonding : STRING := "none"; + rx0_clk1_mux_select : STRING := "recovered clock"; + rx0_clk2_mux_select : STRING := "recovered clock"; + rx0_clk_pd_enable : STRING := "false"; + rx0_ph_fifo_reg_mode : STRING := "false"; + rx0_ph_fifo_reset_enable : STRING := "false"; + rx0_ph_fifo_user_ctrl_enable : STRING := "false"; + rx0_rd_clk_mux_select : STRING := "int clock"; + rx0_recovered_clk_mux_select : STRING := "recovered clock"; + rx0_reset_clock_output_during_digital_reset : STRING := "false"; + rx0_use_double_data_mode : STRING := "false"; + rx_xaui_sm_backward_compatible_enable : STRING := "false"; + select_refclk_dig : STRING := "false"; -- cycloneiv_new + tx0_channel_bonding : STRING := "none"; + tx0_clk_pd_enable : STRING := "false"; + tx0_ph_fifo_reset_enable : STRING := "false"; + tx0_ph_fifo_user_ctrl_enable : STRING := "false"; + tx0_rd_clk_mux_select : STRING := "int clock"; + tx0_reset_clock_output_during_digital_reset : STRING := "false"; + tx0_use_double_data_mode : STRING := "false"; + tx0_wr_clk_mux_select : STRING := "int_clk"; + tx_xaui_sm_backward_compatible_enable : STRING := "false"; + use_coreclk_out_post_divider : STRING := "false"; -- cycloneiv_new + use_deskew_fifo : STRING := "false"; + rx_logical_to_physical_mapping : INTEGER := 0; + tx_logical_to_physical_mapping : INTEGER := 0; + pll_logical_to_physical_mapping : INTEGER := 0; + rx0_logical_to_physical_mapping : INTEGER := 0; + rx1_logical_to_physical_mapping : INTEGER := 1; + rx2_logical_to_physical_mapping : INTEGER := 2; + rx3_logical_to_physical_mapping : INTEGER := 3; + tx0_logical_to_physical_mapping : INTEGER := 0; + tx1_logical_to_physical_mapping : INTEGER := 1; + tx2_logical_to_physical_mapping : INTEGER := 2; + tx3_logical_to_physical_mapping : INTEGER := 3; + sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps + sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs + ); + PORT ( + adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + dpclk : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC := '0'; + dprioload : IN STD_LOGIC := '0'; + fixedclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + nonuserfromcal : IN STD_LOGIC := '0'; + pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47 + quadreset : IN STD_LOGIC := '0'; + rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rdenablesync : IN STD_LOGIC := '0'; + recovclk : IN STD_LOGIC := '0'; + refclkdig : IN STD_LOGIC := '0'; -- cycloneiv_new + rxanalogreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxcoreclk : IN STD_LOGIC := '0'; + rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0'); + rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0'); + rxphfifordenable : IN STD_LOGIC := '0'; + rxphfiforeset : IN STD_LOGIC := '0'; + rxphfifowrdisable : IN STD_LOGIC := '0'; + rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0'); + rxpowerdown : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + scanclk : IN STD_LOGIC := '0'; + scanmode : IN STD_LOGIC := '0'; + scanshift : IN STD_LOGIC := '0'; + syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + testin : IN STD_LOGIC_VECTOR(1999 DOWNTO 0) := (others => '0'); + txclk : IN STD_LOGIC := '0'; + txcoreclk : IN STD_LOGIC := '0'; + txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0'); + txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); + txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0'); + txphfiforddisable : IN STD_LOGIC := '0'; + txphfiforeset : IN STD_LOGIC := '0'; + txphfifowrenable : IN STD_LOGIC := '0'; + txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (others => '0'); + alignstatus : OUT STD_LOGIC; + coreclkout : OUT STD_LOGIC; -- stnngray_new + digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); + dpriodisableout : OUT STD_LOGIC; + dpriooe : OUT STD_LOGIC; + dprioout : OUT STD_LOGIC; + enabledeskew : OUT STD_LOGIC; + fiforesetrd : OUT STD_LOGIC; + quadresetout : OUT STD_LOGIC; + refclkout : OUT STD_LOGIC; -- cycloneiv_new + rxanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxcrupowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxibpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0); + rxphfifox4byteselout : OUT STD_LOGIC; + rxphfifox4wrclkout : OUT STD_LOGIC; + rxphfifox4rdenableout : OUT STD_LOGIC; + rxphfifox4wrenableout : OUT STD_LOGIC; + rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0); + testout : OUT STD_LOGIC_VECTOR(2399 DOWNTO 0); + txanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txdividerpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txobpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0); + txphfifox4byteselout : OUT STD_LOGIC; + txphfifox4rdclkout : OUT STD_LOGIC; + txphfifox4rdenableout : OUT STD_LOGIC; + txphfifox4wrenableout : OUT STD_LOGIC; + txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0) + ); +END COMPONENT; + +-- +-- cycloneiv_hssi_calibration_block +-- + +COMPONENT cycloneiv_hssi_calibration_block + GENERIC ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + tipd_clk : VitalDelayType01 := DefpropDelay01; + lpm_type : string := "cycloneiv_hssi_calibration_block"; + cont_cal_mode : string := "false"; + enable_rx_cal_tw : string := "false"; + enable_tx_cal_tw : string := "false"; + migrated_from_prev_family : string := "false"; + rtest : string := "false"; + rx_cal_wt_value : integer := 0; + send_rx_cal_status : string := "true"; + tx_cal_wt_value : integer := 1); + PORT ( + clk : IN std_logic := '0'; + powerdn : IN std_logic := '0'; + testctrl : IN std_logic := '0'; + calibrationstatus : OUT std_logic_vector(4 DOWNTO 0); + nonusertocmu : OUT std_logic + ); +END COMPONENT; + +end cycloneiv_hssi_components; + +package body CYCLONEIV_HSSI_COMPONENTS is + + +function bin2int (s : std_logic_vector) return integer is + + constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : std_logic) return integer is + constant temp : std_logic := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + +function str2bin (s : string) return std_logic_vector is +variable len : integer := s'length; +variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0'); +variable i : integer; +begin + for i in 1 to len loop + case s(i) is + when '0' => result(len - i) := '0'; + when '1' => result(len - i) := '1'; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + end loop; + return result; +end; + +function str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; + +function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + +function int2bin (arg : boolean; size : integer) return std_logic_vector is + variable result : std_logic_vector(size-1 downto 0); + begin + if(arg)then + result := (OTHERS => '1'); + else + result := (OTHERS => '0'); + end if; + return result; + end int2bin; + +function int2bit (arg : integer) return std_logic is + variable int_val : integer := arg; + variable result : std_logic; + begin + + if (int_val = 0) then + result := '0'; + else + result := '1'; + end if; + + return result; +end int2bit; + +function int2bit (arg : boolean) return std_logic is + variable int_val : boolean := arg; + variable result : std_logic; + begin + + if (int_val ) then + result := '1'; + else + result := '0'; + end if; + + return result; +end int2bit; + +function tx_top_ctrl_in_width(double_data_mode : string; + ser_double_data_mode : string + ) return integer is + variable real_widthb : integer; + begin + real_widthb := 1; + if (ser_double_data_mode = "true" AND double_data_mode = "true") then + real_widthb := 4; + elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then + real_widthb := 1; + else + real_widthb := 2; + end if; + + return real_widthb; + end tx_top_ctrl_in_width; + +function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is + variable real_widthb : integer; + begin + if (des_double_data_mode = "true") then + real_widthb := 2; + else + real_widthb := 1; + end if; + return real_widthb; + end rx_top_a1k1_out_width; + +function rx_top_ctrl_out_width(double_data_mode : string; + des_double_data_mode : string + ) return integer is + variable real_widthb : integer; + begin + real_widthb := 1; + if (des_double_data_mode = "true" AND double_data_mode = "true") then + real_widthb := 4; + elsif (des_double_data_mode = "false" AND double_data_mode = "false") then + real_widthb := 1; + else + real_widthb := 2; + end if; + + return real_widthb; + end rx_top_ctrl_out_width; + +function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS + +variable Temp : TIME; +variable TransitionTime : TIME := TIME'HIGH; +variable PathDelay : TIME := TIME'HIGH; + +begin + + for i IN Paths'RANGE loop + next when not Paths(i).PathCondition; + + next when Paths(i).InputChangeTime > TransitionTime; + + Temp := Paths(i).PathDelay(tr01); + + if Paths(i).InputChangeTime < TransitionTime then + PathDelay := Temp; + else + if Temp < PathDelay then + PathDelay := Temp; + end if; + end if; + TransitionTime := Paths(i).InputChangeTime; + end loop; + + return PathDelay; + +end; + +function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is +variable dataout : std_logic_vector(data1'range); + begin + if(sel) then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + +function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is +variable dataout : std_logic; + begin + if(sel) then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + +function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is +variable dataout : std_logic_vector(data1'range); + begin + if(sel = '1') then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + +function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is +variable dataout : std_logic; + begin + if(sel = '1') then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + +function rx_top_basic_width (channel_width : integer) return integer is +variable basic_width : integer; +begin + if (channel_width mod 10 = 0) then + basic_width := 10; + else + basic_width := 8; + end if; + return(basic_width); +end rx_top_basic_width; + +function rx_top_num_of_basic (channel_width : integer) return integer is +variable num_of_basic : integer; +begin + if (channel_width mod 10 = 0) then + num_of_basic := channel_width/10; + else + num_of_basic := channel_width/8; + end if; + return(num_of_basic); +end rx_top_num_of_basic; + +function reduction_or ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '0'; + begin + for i in val'range loop + result := result or val(i); + end loop; + return(result); +end reduction_or; + +function reduction_nor ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '0'; + begin + for i in val'range loop + result := result or val(i); + end loop; + return(not result); +end reduction_nor; + +function reduction_xor ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '0'; + begin + for i in val'range loop + result := result xor val(i); + end loop; + return(result); +end reduction_xor; + +function reduction_and ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '1'; + begin + for i in val'range loop + result := result and val(i); + end loop; + return(result); +end reduction_and; + +function reduction_nand ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '1'; + begin + for i in val'range loop + result := result and val(i); + end loop; + return(not result); +end reduction_nand; + +function alpha_tolower (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 25) := " "; + +begin + for i in 1 to string_length loop + case given_string(i) is + when 'A' => result_string(i) := 'a'; + when 'B' => result_string(i) := 'b'; + when 'C' => result_string(i) := 'c'; + when 'D' => result_string(i) := 'd'; + when 'E' => result_string(i) := 'e'; + when 'F' => result_string(i) := 'f'; + when 'G' => result_string(i) := 'g'; + when 'H' => result_string(i) := 'h'; + when 'I' => result_string(i) := 'i'; + when 'J' => result_string(i) := 'j'; + when 'K' => result_string(i) := 'k'; + when 'L' => result_string(i) := 'l'; + when 'M' => result_string(i) := 'm'; + when 'N' => result_string(i) := 'n'; + when 'O' => result_string(i) := 'o'; + when 'P' => result_string(i) := 'p'; + when 'Q' => result_string(i) := 'q'; + when 'R' => result_string(i) := 'r'; + when 'S' => result_string(i) := 's'; + when 'T' => result_string(i) := 't'; + when 'U' => result_string(i) := 'u'; + when 'V' => result_string(i) := 'v'; + when 'W' => result_string(i) := 'w'; + when 'X' => result_string(i) := 'x'; + when 'Y' => result_string(i) := 'y'; + when 'Z' => result_string(i) := 'z'; + when others => result_string(i) := given_string(i); + end case; + end loop; + return (result_string(1 to string_length)); +end alpha_tolower; + + +function cycloneiv_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is +begin + CASE ph_fifo_xn_select IS + WHEN 0 => RETURN ph_fifo_xn_mapping0; + WHEN 1 => RETURN ph_fifo_xn_mapping1; + WHEN 2 => RETURN ph_fifo_xn_mapping2; + WHEN OTHERS => RETURN "none"; + END CASE; +end cycloneiv_tx_pcs_mph_fifo_xn_mapping; + + +function cycloneiv_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is +variable fifo_index : integer; +begin + if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then + fifo_index := ph_fifo_xn_select; + else + fifo_index := 0; + end if; + return(fifo_index); +end cycloneiv_tx_pcs_mphfifo_index; + +function cycloneiv_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is +variable fifo_index : integer; +begin + if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then + fifo_index := ph_fifo_xn_select; + else + fifo_index := 0; + end if; + return(fifo_index); +end cycloneiv_tx_pcs_miqp_phfifo_index; + + + + + +end CYCLONEIV_HSSI_COMPONENTS; diff --git a/Common/sim/altera/cycloneiv_pcie_hip_atoms.vhd b/Common/sim/altera/cycloneiv_pcie_hip_atoms.vhd new file mode 100644 index 0000000..1aa44b4 --- /dev/null +++ b/Common/sim/altera/cycloneiv_pcie_hip_atoms.vhd @@ -0,0 +1,219747 @@ +-- Copyright (C) 2007 - Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +------------------------------------------------------------------------------- +-- -- +-- Containing VHDL Model for the Atoms: -- +-- -- +-- cycloneiv_hssi_pcie_hip -- +-- -- +------------------------------------------------------------------------------- + + + +-- ----------------------------------------------------------- +-- +-- Module Name : cycloneiv_pciehip_param +-- +-- Description : process parameters +-- +-- ----------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_param IS + GENERIC ( + + advanced_errors : STRING := "false"; + allow_rx_valid_empty : STRING := "false"; -- ww27.2008 + bar0_64bit_mem_space : STRING := "true"; + bar0_io_space : STRING := "false"; + bar0_prefetchable : STRING := "true"; + bar0_size_mask : INTEGER := 32; + bar1_64bit_mem_space : STRING := "false"; + bar1_io_space : STRING := "false"; + bar1_prefetchable : STRING := "false"; + bar1_size_mask : INTEGER := 4; + bar2_64bit_mem_space : STRING := "false"; + bar2_io_space : STRING := "false"; + bar2_prefetchable : STRING := "false"; + bar2_size_mask : INTEGER := 4; + bar3_64bit_mem_space : STRING := "false"; + bar3_io_space : STRING := "false"; + bar3_prefetchable : STRING := "false"; + bar3_size_mask : INTEGER := 4; + bar4_64bit_mem_space : STRING := "false"; + bar4_io_space : STRING := "false"; + bar4_prefetchable : STRING := "false"; + bar4_size_mask : INTEGER := 4; + bar5_64bit_mem_space : STRING := "false"; + bar5_io_space : STRING := "false"; + bar5_prefetchable : STRING := "false"; + bar5_size_mask : INTEGER := 4; + bar_io_window_size : STRING := "NONE"; + bar_prefetchable : INTEGER := 0; + base_address : INTEGER := 0; + bridge_port_ssid_support : STRING := "false"; + bridge_port_vga_enable : STRING := "false"; + bypass_cdc : STRING := "false"; + bypass_tl : STRING := "false"; + class_code : INTEGER := 16711680; + completion_timeout : STRING := "ABCD"; + core_clk_divider : INTEGER := 1; + core_clk_source : STRING := "PLL_FIXED_CLK"; + credit_buffer_allocation_aux : STRING := "BALANCED"; + deemphasis_enable : STRING := "false"; + device_address : INTEGER := 0; + device_id : INTEGER := 1; + device_number : INTEGER := 0; + diffclock_nfts_count : INTEGER := 128; + disable_async_l2_logic : STRING := "false"; -- ww27.2008 + disable_cdc_clk_ppm : STRING := "true"; + disable_link_x2_support : STRING := "false"; + disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + dll_active_report_support : STRING := "false"; + ei_delay_powerdown_count : INTEGER := 10; + eie_before_nfts_count : INTEGER := 4; + enable_adapter_half_rate_mode : STRING := "false"; + enable_ch0_pclk_out : STRING := "true"; + enable_completion_timeout_disable : STRING := "true"; + enable_coreclk_out_half_rate : STRING := "false"; + enable_ecrc_check : STRING := "true"; + enable_ecrc_gen : STRING := "true"; + enable_function_msi_support : STRING := "true"; + enable_function_msix_support : STRING := "false"; + enable_gen2_core : STRING := "true"; + enable_hip_x1_loopback : STRING := "false"; + enable_l1_aspm : STRING := "false"; + enable_msi_64bit_addressing : STRING := "true"; + enable_msi_masking : STRING := "false"; + enable_rcv0buf_a_we : STRING := "true"; + enable_rcv0buf_b_re : STRING := "true"; + enable_rcv0buf_output_regs : STRING := "false"; + enable_rcv1buf_a_we : STRING := "true"; + enable_rcv1buf_b_re : STRING := "true"; + enable_rcv1buf_output_regs : STRING := "false"; + enable_retrybuf_a_we : STRING := "true"; + enable_retrybuf_b_re : STRING := "true"; + enable_retrybuf_ecc : STRING := "false"; -- ww12 + enable_retrybuf_output_regs : STRING := "false"; + enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx0buf_ecc : STRING := "false"; -- ww12 + enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx1buf_ecc : STRING := "false"; -- ww12 + enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx_buffer_checking : STRING := "false"; + enable_rx_ei_l0s_exit_refined : STRING := "false"; + enable_rx_reordering : STRING := "true"; + enable_slot_register : STRING := "false"; + endpoint_l0_latency : INTEGER := 0; + endpoint_l1_latency : INTEGER := 0; + expansion_base_address_register : INTEGER := 0; + extend_tag_field : STRING := "false"; + fc_init_timer : INTEGER := 1024; + flow_control_timeout_count : INTEGER := 200; + flow_control_update_count : INTEGER := 30; + gen2_diffclock_nfts_count : INTEGER := 255; + gen2_lane_rate_mode : STRING := "false"; + gen2_sameclock_nfts_count : INTEGER := 255; + hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + iei_logic : STRING := "DISABLE"; + indicator : INTEGER := 7; + l01_entry_latency : INTEGER := 31; + l0_exit_latency_diffclock : INTEGER := 6; + l0_exit_latency_sameclock : INTEGER := 6; + l1_exit_latency_diffclock : INTEGER := 0; + l1_exit_latency_sameclock : INTEGER := 0; + lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000"; + low_priority_vc : INTEGER := 0; + max_link_width : INTEGER := 4; + max_payload_size : INTEGER := 2; + maximum_current : INTEGER := 0; + migrated_from_prev_family : STRING := "false"; + millisecond_cycle_count : INTEGER := 0; + mram_bist_settings : STRING := ""; + msi_function_count : INTEGER := 2; + msix_pba_bir : INTEGER := 0; + msix_pba_offset : INTEGER := 0; + msix_table_bir : INTEGER := 0; + msix_table_offset : INTEGER := 0; + msix_table_size : INTEGER := 0; + no_command_completed : STRING := "true"; + no_soft_reset : STRING := "false"; + pcie_mode : STRING := "SHARED_MODE"; + pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; + port_link_number : INTEGER := 1; + port_address : INTEGER := 0; + register_pipe_signals : STRING := "false"; + retry_buffer_last_active_address : INTEGER := 4095; + retry_buffer_memory_settings : INTEGER := 0; + revision_id : INTEGER := 1; + rx0_adap_fifo_full_value : INTEGER := 9; + rx1_adap_fifo_full_value : INTEGER := 9; + rx_cdc_full_value : INTEGER := 12; + rx_idl_os_count : INTEGER := 0; + rx_ptr0_nonposted_dpram_max : INTEGER := 0; + rx_ptr0_nonposted_dpram_min : INTEGER := 0; + rx_ptr0_posted_dpram_max : INTEGER := 0; + rx_ptr0_posted_dpram_min : INTEGER := 0; + rx_ptr1_nonposted_dpram_max : INTEGER := 0; + rx_ptr1_nonposted_dpram_min : INTEGER := 0; + rx_ptr1_posted_dpram_max : INTEGER := 0; + rx_ptr1_posted_dpram_min : INTEGER := 0; + sameclock_nfts_count : INTEGER := 128; + single_rx_detect : INTEGER := 0; + skp_os_schedule_count : INTEGER := 0; + slot_number : INTEGER := 0; + slot_power_limit : INTEGER := 0; + slot_power_scale : INTEGER := 0; + ssid : INTEGER := 0; + ssvid : INTEGER := 0; + subsystem_device_id : INTEGER := 1; + subsystem_vendor_id : INTEGER := 4466; + surprise_down_error_support : STRING := "false"; + tx0_adap_fifo_full_value : INTEGER := 11; + tx1_adap_fifo_full_value : INTEGER := 11; + tx_cdc_full_value : INTEGER := 12; + tx_cdc_stop_dummy_full_value : INTEGER := 11; + use_crc_forwarding : STRING := "false"; + vc0_clk_enable : STRING := "true"; + vc0_rx_buffer_memory_settings : INTEGER := 0; + vc0_rx_flow_ctrl_compl_data : INTEGER := 448; + vc0_rx_flow_ctrl_compl_header : INTEGER := 112; + vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc0_rx_flow_ctrl_posted_data : INTEGER := 360; + vc0_rx_flow_ctrl_posted_header : INTEGER := 50; + vc1_clk_enable : STRING := "false"; + vc1_rx_buffer_memory_settings : INTEGER := 0; + vc1_rx_flow_ctrl_compl_data : INTEGER := 448; + vc1_rx_flow_ctrl_compl_header : INTEGER := 112; + vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc1_rx_flow_ctrl_posted_data : INTEGER := 360; + vc1_rx_flow_ctrl_posted_header : INTEGER := 50; + vc_arbitration : INTEGER := 1; + vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + vendor_id : INTEGER := 4466 + ); + PORT ( + test_in : IN STD_LOGIC := '0'; + csr_hip_in : OUT STD_LOGIC_VECTOR(1759 DOWNTO 0) + ); +END cycloneiv_pciehip_param; + +ARCHITECTURE trans OF cycloneiv_pciehip_param IS + + --//////////////////////////////////////////////////////////////////////////// + -- parameter list copied from top_level atom -------------------------------// + --//////////////////////////////////////////////////////////////////////////// + + --//////////////////////////////////////////////////////////////////////////// + -- temporary signals added to patch the conversion function - non-RTL // + --//////////////////////////////////////////////////////////////////////////// + SIGNAL init_use_crc_forwarding : STD_LOGIC; + + --//////////////////////////////////////////////////////////////////////////// + -- k-bits init values regiser version - total 40----------------------------// + -- // + -- k-bits definition and map to ext_* is from hip_top.v out_hip -> k_bits // + -- // + --//////////////////////////////////////////////////////////////////////////// + + -- configuration signals + SIGNAL init_k_gbl : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL init_k_dev : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_k_port : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- clk-stealing enable signals for the MRAMs + SIGNAL init_k_clk_x8_sel_rtry : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL init_k_clk_x8_sel_rcv0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL init_k_clk_x8_sel_rcv1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- ECC enable signals for the MRAMs + SIGNAL init_k_ecc_enable_rtry : STD_LOGIC; + SIGNAL init_k_ecc_enable_rcv0 : STD_LOGIC; + SIGNAL init_k_ecc_enable_rcv1 : STD_LOGIC; + + -- clk mux selections + SIGNAL init_k_pclk_sel : STD_LOGIC; + SIGNAL init_k_core_clk_source_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL init_k_core_clk_div_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL init_k_core_clk_out_sel : STD_LOGIC; + SIGNAL init_k_core_clk_dbg_sel : STD_LOGIC; + + -- RX,TX debug signal selection + SIGNAL init_k_pipex1_dbg_sel : STD_LOGIC; + + -- Electrical Idle Inferral enable + SIGNAL init_k_iei_enable : STD_LOGIC_VECTOR(5 DOWNTO 0); + + --reg [383:0] init_k_conf_func0; + --reg [227:0] init_k_bar_func0; + SIGNAL init_k_cnt : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL init_k_vc0 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_vc1 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_vc2 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_vc3 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_vc4 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_vc5 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_vc6 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_vc7 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL init_k_rtry : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL init_k_ptr0 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL init_k_ptr1 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL init_k_hip : STD_LOGIC_VECTOR(22 DOWNTO 0); + SIGNAL init_k_mem_bist : STD_LOGIC_VECTOR(74 DOWNTO 0); + SIGNAL init_k_rtry_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL init_k_rcv0_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL init_k_rcv1_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + --SIGNAL init_k_rcv_mem0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + --SIGNAL init_k_rcv_mem1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- Misc. functions for the MRAMs + SIGNAL init_k_rtry_outreg : STD_LOGIC; + SIGNAL init_k_rtry_raen2 : STD_LOGIC; + SIGNAL init_k_rtry_rben1 : STD_LOGIC; + + SIGNAL init_k_rcv0_outreg : STD_LOGIC; + SIGNAL init_k_rcv0_raen2 : STD_LOGIC; + SIGNAL init_k_rcv0_rben1 : STD_LOGIC; + + SIGNAL init_k_rcv1_outreg : STD_LOGIC; + SIGNAL init_k_rcv1_raen2 : STD_LOGIC; + SIGNAL init_k_rcv1_rben1 : STD_LOGIC; + + -- softtwisted k-bits names ----------------------------------------------- + SIGNAL init_k_conf : STD_LOGIC_VECTOR(383 DOWNTO 0); + SIGNAL init_k_bar : STD_LOGIC_VECTOR(227 DOWNTO 0); + + --//////////////////////////////////////////////////////////////////////////// + -- k-bits declarations - total 44-------------------------------------------// + --//////////////////////////////////////////////////////////////////////////// + + -- configuration signals + SIGNAL k_gbl : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL k_dev : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL k_port : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- clk-stealing enable signals for the MRAMs + SIGNAL k_clk_x8_sel_rtry : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL k_clk_x8_sel_rcv0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL k_clk_x8_sel_rcv1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- ECC enable signals for the MRAMs + SIGNAL k_ecc_enable_rtry : STD_LOGIC; + SIGNAL k_ecc_enable_rcv0 : STD_LOGIC; + SIGNAL k_ecc_enable_rcv1 : STD_LOGIC; + + -- clk mux selections + SIGNAL k_pclk_sel : STD_LOGIC; + SIGNAL k_core_clk_source_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL k_core_clk_div_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL k_core_clk_out_sel : STD_LOGIC; + SIGNAL k_core_clk_dbg_sel : STD_LOGIC; + + -- RX,TX debug signal selection + SIGNAL k_pipex1_dbg_sel : STD_LOGIC; + + -- Electrical Idle Inferral enable + SIGNAL k_iei_enable : STD_LOGIC_VECTOR(5 DOWNTO 0); + + SIGNAL k_conf_func0 : STD_LOGIC_VECTOR(383 DOWNTO 0); + SIGNAL k_bar_func0 : STD_LOGIC_VECTOR(227 DOWNTO 0); + SIGNAL k_cnt : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL k_vc0 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc1 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc2 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc3 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc4 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc5 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc6 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc7 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_rtry : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL k_ptr0 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL k_ptr1 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL k_hip : STD_LOGIC_VECTOR(22 DOWNTO 0); + SIGNAL k_mem_bist : STD_LOGIC_VECTOR(74 DOWNTO 0); + SIGNAL k_rtry_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL k_rcv0_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL k_rcv1_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + --SIGNAL k_rcv_mem0 : STD_LOGIC_VECTOR(15 DOWNTO 0); -- no longer existed in HIP_TOP RTL shawn + --SIGNAL k_rcv_mem1 : STD_LOGIC_VECTOR(15 DOWNTO 0); -- no longer existed in HIP_TOP RTL shawn + + + -- Misc. functions for the MRAMs + -- no longer in hip_top RTL but parameter still existed at WYS - Shawn + SIGNAL k_rtry_outreg : STD_LOGIC; + SIGNAL k_rtry_raen2 : STD_LOGIC; + SIGNAL k_rtry_rben1 : STD_LOGIC; + + SIGNAL k_rcv0_outreg : STD_LOGIC; + SIGNAL k_rcv0_raen2 : STD_LOGIC; + SIGNAL k_rcv0_rben1 : STD_LOGIC; + + SIGNAL k_rcv1_outreg : STD_LOGIC; + SIGNAL k_rcv1_raen2 : STD_LOGIC; + SIGNAL k_rcv1_rben1 : STD_LOGIC; + + --//////////////////////////////////////////////////////////////////////////// + -- DPRIO registers - total 111 ---------------------------------------------// + --//////////////////////////////////////////////////////////////////////////// + SIGNAL ext_hip_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_54 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_55 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_56 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_57 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_58 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_59 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_60 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_61 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_62 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_63 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_64 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_65 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_66 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_67 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_68 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_69 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_70 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_71 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_72 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_73 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_74 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_75 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_76 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_77 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_78 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_79 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_80 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_81 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_82 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_83 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_84 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_85 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_86 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_87 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_88 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_89 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_90 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_91 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_92 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_93 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_94 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_95 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_96 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_97 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_98 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_99 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_100 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_101 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_102 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_103 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_104 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_105 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_106 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_107 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_108 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_109 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL ext_hip_ctrl_110 : STD_LOGIC_VECTOR(15 DOWNTO 0); +BEGIN + + --//////////////////////////////////////////////////////////////////// + -- funtions assisting conversion of parameters ---------------------// + --//////////////////////////////////////////////////////////////////// + + -- purpose: Calculate the k_ptr values based on the supplied parameters + -- calc_k_ptr + -- Reserve Space for the NonPosted Headers (and also NonPosted Data) + + --nonp_siz = ((k_vc[27:20])) * 2; -- updated 07.ww51 + + -- function to convert at most 8-bit long string to binary + + --//////////////////////////////////////////////////////////////////////////// + -- initialize temporary signals -- non-RTL -------------------------------- // + --//////////////////////////////////////////////////////////////////////////// + --initial begin + -- + --end + + PROCESS + FUNCTION calc_k_ptr( + k_vc : IN STD_LOGIC_VECTOR(55 DOWNTO 0); + init_use_crc_forwarding : IN STD_LOGIC) RETURN STD_LOGIC_VECTOR IS + VARIABLE post_min : STD_LOGIC_VECTOR(8 DOWNTO 0); + VARIABLE post_max : STD_LOGIC_VECTOR(8 DOWNTO 0); + VARIABLE nonp_min : STD_LOGIC_VECTOR(8 DOWNTO 0); + VARIABLE nonp_max : STD_LOGIC_VECTOR(8 DOWNTO 0); + VARIABLE nonp_siz : INTEGER; + VARIABLE calc_k_ptr : STD_LOGIC_VECTOR(35 DOWNTO 0); + BEGIN + post_min := "000000000"; + nonp_max := "111111111"; + IF (init_use_crc_forwarding = '1') THEN + nonp_siz :=bin2int(k_vc(27 DOWNTO 20)) * 3; + ELSE + nonp_siz := bin2int(k_vc(27 DOWNTO 20)) * 2; + END IF; + post_max := nonp_max - int2bin(nonp_siz,9); + nonp_min := post_max + "000000001"; + calc_k_ptr := ((nonp_max & nonp_min & post_max & post_min)); + RETURN calc_k_ptr; + END calc_k_ptr; + + + variable init_use_crc_forwarding_var : std_logic; + variable init_k_vc0_var : STD_LOGIC_VECTOR(55 DOWNTO 0); + variable init_k_vc1_var : STD_LOGIC_VECTOR(55 DOWNTO 0); + BEGIN + --///////////////////////////////////////////////////////////////////// + -- parameter to k_bits conversion - script generated ----------------// + --///////////////////////////////////////////////////////////////////// + init_use_crc_forwarding_var := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), '1', '0'); -- pcie 1.1+ + init_k_gbl(0) <= '1'; + init_k_gbl(7 DOWNTO 1) <= vc_enable ; + init_k_gbl(8) <= '1'; + init_k_gbl(9) <= (mux_select((alpha_tolower(enable_slot_register) = ("true")), '1', '0')); + init_k_gbl(11 DOWNTO 10) <= "00"; + init_k_gbl(15 DOWNTO 12) <= ((mux_select((alpha_tolower(pcie_mode) = ("ep_native")), "0000", "0000")) OR (mux_select((alpha_tolower(pcie_mode) = ("ep_legacy")), "0001", "0000")) OR (mux_select((alpha_tolower(pcie_mode) = ("rp")), "0010", "0000")) OR (mux_select((alpha_tolower(pcie_mode) = ("sw_up")), "0011", "0000")) OR (mux_select((alpha_tolower(pcie_mode) = ("sw_dn")), "0100", "0000")) OR (mux_select((alpha_tolower(pcie_mode) = ("bridge")), "0101", "0000")) OR (mux_select((alpha_tolower(pcie_mode) = ("switch_mode")), "1110", "0000")) OR (mux_select((alpha_tolower(pcie_mode) = ("shared_mode")), "1111", "0000")) OR "0000"); -- lane mask + init_k_gbl(22 DOWNTO 16) <= "0000000"; + init_k_gbl(23) <= (mux_select((alpha_tolower(bypass_cdc) = ("true")), '0', '1')); + init_k_gbl(24) <= (mux_select((alpha_tolower(disable_cdc_clk_ppm) = ("true")), '1', '0')); + init_k_gbl(25) <= '0'; + init_k_gbl(26) <= (mux_select((alpha_tolower(enable_rx_reordering) = ("true")), '1', '0')); + init_k_gbl(27) <= (mux_select((alpha_tolower(enable_rx_buffer_checking) = ("true")), '1', '0')); + init_k_gbl(31 DOWNTO 28) <= int2bin(single_rx_detect, 4); + init_k_gbl(32) <= (mux_select((alpha_tolower(use_crc_forwarding) = ("true")), '1', '0')); + init_k_gbl(33) <= (mux_select((alpha_tolower(bypass_tl) = ("true")), '1', '0')); + init_k_gbl(34) <= (mux_select((alpha_tolower(gen2_lane_rate_mode) = ("true")), '1', '0')); + init_k_gbl(42 DOWNTO 35) <= lane_mask ; + init_k_gbl(43) <= (mux_select((alpha_tolower(disable_link_x2_support) = ("true")), '1', '0')); -- reserve + init_k_gbl(63 DOWNTO 44) <= "00000000000000000000"; + init_k_port(7 DOWNTO 0) <= int2bin(port_link_number, 8); + init_k_dev(4 DOWNTO 0) <= int2bin(device_number, 5); + init_k_core_clk_out_sel <= (mux_select((alpha_tolower(enable_coreclk_out_half_rate) = ("true")), '1', '0')); + init_k_core_clk_div_sel <= mux_select((core_clk_divider = 1), "000", mux_select((core_clk_divider = 2), "001", mux_select((core_clk_divider = 4), "011", mux_select((core_clk_divider = 8), "101", mux_select((core_clk_divider = 16), "111", "000"))))); + init_k_core_clk_source_sel(1 DOWNTO 0) <= ((mux_select((alpha_tolower(core_clk_source) = ("pll_fixed_clk")), "00", "00")) OR (mux_select((alpha_tolower(core_clk_source) = ("pclk")), "01", "00")) OR (mux_select((alpha_tolower(core_clk_source) = ("core_clk_in")), "10", "00")) OR "00"); + init_k_pclk_sel <= (mux_select((alpha_tolower(enable_ch0_pclk_out) = ("true")), '1', '0')); + init_k_pipex1_dbg_sel <= (mux_select((alpha_tolower(enable_hip_x1_loopback) = ("true")), '1', '0')); + IF (alpha_tolower(iei_logic) = "disable") THEN + init_k_iei_enable(5 DOWNTO 0) <= "001001"; + ELSIF (alpha_tolower(iei_logic) = "iei_idid") THEN + init_k_iei_enable(5 DOWNTO 0) <= "100100"; + ELSIF (alpha_tolower(iei_logic) = "iei_idis") THEN + init_k_iei_enable(5 DOWNTO 0) <= "100101"; + ELSIF (alpha_tolower(iei_logic) = "iei_isii") THEN + init_k_iei_enable(5 DOWNTO 0) <= "110110"; + ELSIF (alpha_tolower(iei_logic) = "iei_iiis") THEN + init_k_iei_enable(5 DOWNTO 0) <= "110101"; + ELSE + init_k_iei_enable(5 DOWNTO 0) <= "000000"; + END IF; + init_k_clk_x8_sel_rcv0 <= int2bin(enable_rx0buf_x8_clk_stealing, 4); + init_k_clk_x8_sel_rcv1 <= int2bin(enable_rx1buf_x8_clk_stealing, 4); + init_k_clk_x8_sel_rtry <= int2bin(enable_retrybuf_x8_clk_stealing, 4); + init_k_ecc_enable_rcv0 <= (mux_select((alpha_tolower(enable_rx0buf_ecc) = ("true")), '1', '0')); + init_k_ecc_enable_rcv1 <= (mux_select((alpha_tolower(enable_rx1buf_ecc) = ("true")), '1', '0')); + init_k_ecc_enable_rtry <= (mux_select((alpha_tolower(enable_retrybuf_ecc) = ("true")), '1', '0')); + init_k_rtry_outreg <= (mux_select((alpha_tolower(enable_retrybuf_output_regs) = ("true")), '1', '0')); + init_k_rtry_raen2 <= (mux_select((alpha_tolower(enable_retrybuf_a_we) = ("true")), '1', '0')); + init_k_rtry_rben1 <= (mux_select((alpha_tolower(enable_retrybuf_b_re) = ("true")), '1', '0')); + init_k_rcv0_outreg <= (mux_select((alpha_tolower(enable_rcv0buf_output_regs) = ("true")), '1', '0')); + init_k_rcv0_raen2 <= (mux_select((alpha_tolower(enable_rcv0buf_a_we) = ("true")), '1', '0')); + init_k_rcv0_rben1 <= (mux_select((alpha_tolower(enable_rcv0buf_b_re) = ("true")), '1', '0')); + init_k_rcv1_outreg <= (mux_select((alpha_tolower(enable_rcv1buf_output_regs) = ("true")), '1', '0')); + init_k_rcv1_raen2 <= (mux_select((alpha_tolower(enable_rcv1buf_a_we) = ("true")), '1', '0')); + init_k_rcv1_rben1 <= (mux_select((alpha_tolower(enable_rcv1buf_b_re) = ("true")), '1', '0')); + init_k_conf(15 DOWNTO 0) <= int2bin(vendor_id, 16); + init_k_conf(31 DOWNTO 16) <= int2bin(device_id, 16); + init_k_conf(39 DOWNTO 32) <= int2bin(revision_id, 8); + init_k_conf(63 DOWNTO 40) <= int2bin(class_code, 24); + init_k_conf(79 DOWNTO 64) <= int2bin(subsystem_vendor_id, 16); + init_k_conf(95 DOWNTO 80) <= int2bin(subsystem_device_id, 16); + init_k_conf(96) <= (mux_select((alpha_tolower(no_soft_reset) = ("true")), '1', '0')); -- PME Clock + init_k_conf(101 DOWNTO 97) <= "00000"; + init_k_conf(104 DOWNTO 102) <= int2bin(maximum_current, 3); -- D1 D2 + init_k_conf(106 DOWNTO 105) <= "00"; + init_k_conf(111 DOWNTO 107) <= pme_state_enable ; + init_k_conf(112) <= (mux_select((alpha_tolower(advanced_errors) = ("true")), '1', '0')); + init_k_conf(115 DOWNTO 113) <= int2bin(low_priority_vc, 3); + init_k_conf(119 DOWNTO 116) <= int2bin(vc_arbitration, 4); + init_k_conf(127 DOWNTO 120) <= disable_snoop_packet ; + init_k_conf(130 DOWNTO 128) <= int2bin(max_payload_size, 3); + init_k_conf(131) <= (mux_select((alpha_tolower(surprise_down_error_support) = ("true")), '1', '0')); + init_k_conf(132) <= (mux_select((alpha_tolower(dll_active_report_support) = ("true")), '1', '0')); + init_k_conf(133) <= (mux_select((alpha_tolower(extend_tag_field) = ("true")), '1', '0')); + init_k_conf(136 DOWNTO 134) <= int2bin(endpoint_l0_latency, 3); + init_k_conf(139 DOWNTO 137) <= int2bin(endpoint_l1_latency, 3); + init_k_conf(142 DOWNTO 140) <= int2bin(indicator, 3); -- role base + init_k_conf(143) <= '1'; + init_k_conf(145 DOWNTO 144) <= int2bin(slot_power_scale, 2); + init_k_conf(151 DOWNTO 146) <= int2bin(max_link_width, 6); -- l0s ASPM + init_k_conf(152) <= '1'; + init_k_conf(153) <= (mux_select((alpha_tolower(enable_l1_aspm) = ("true")), '1', '0')); + init_k_conf(156 DOWNTO 154) <= int2bin(l1_exit_latency_sameclock, 3); + init_k_conf(159 DOWNTO 157) <= int2bin(l1_exit_latency_diffclock, 3); + init_k_conf(166 DOWNTO 160) <= hot_plug_support ; + init_k_conf(169 DOWNTO 167) <= "000"; + init_k_conf(177 DOWNTO 170) <= int2bin(slot_power_limit, 8); -- electromechanical lock present + init_k_conf(178) <= '0'; + init_k_conf(191 DOWNTO 179) <= int2bin(slot_number, 13); + init_k_conf(199 DOWNTO 192) <= int2bin(diffclock_nfts_count, 8); + init_k_conf(207 DOWNTO 200) <= int2bin(sameclock_nfts_count, 8); + init_k_conf(211 DOWNTO 208) <= ((mux_select((alpha_tolower(completion_timeout) = ("none")), "0000", "0000")) OR (mux_select((alpha_tolower(completion_timeout) = ("a")), "0001", "0000")) OR (mux_select((alpha_tolower(completion_timeout) = ("b")), "0010", "0000")) OR (mux_select((alpha_tolower(completion_timeout) = ("ab")), "0011", "0000")) OR (mux_select((alpha_tolower(completion_timeout) = ("bc")), "0110", "0000")) OR (mux_select((alpha_tolower(completion_timeout) = ("abc")), "0111", "0000")) OR (mux_select((alpha_tolower(completion_timeout) = ("bcd")), "1110", "0000")) OR (mux_select((alpha_tolower(completion_timeout) = ("abcd")), "1111", "0000")) OR "0000"); + init_k_conf(212) <= (mux_select((alpha_tolower(enable_completion_timeout_disable) = ("true")), '1', '0')); -- reserve + init_k_conf(215 DOWNTO 213) <= "000"; + init_k_conf(216) <= (mux_select((alpha_tolower(enable_ecrc_gen) = ("true")), '1', '0')); + init_k_conf(217) <= (mux_select((alpha_tolower(enable_ecrc_check) = ("true")), '1', '0')); + init_k_conf(218) <= (mux_select((alpha_tolower(no_command_completed) = ("true")), '1', '0')); + init_k_conf(221 DOWNTO 219) <= int2bin(msi_function_count, 3); + init_k_conf(222) <= (mux_select((alpha_tolower(enable_msi_64bit_addressing) = ("true")), '1', '0')); + init_k_conf(223) <= (mux_select((alpha_tolower(enable_msi_masking) = ("true")), '1', '0')); + init_k_conf(224) <= (mux_select((alpha_tolower(enable_function_msi_support) = ("true")), '1', '0')); -- interrupt pins + init_k_conf(229 DOWNTO 225) <= "00001"; + init_k_conf(230) <= (mux_select((alpha_tolower(enable_function_msix_support) = ("true")), '1', '0')); + init_k_conf(233 DOWNTO 231) <= int2bin(msix_pba_bir, 3); + init_k_conf(262 DOWNTO 234) <= int2bin(msix_pba_offset, 29); + init_k_conf(265 DOWNTO 263) <= int2bin(msix_table_bir, 3); + init_k_conf(294 DOWNTO 266) <= int2bin(msix_table_offset, 29); + init_k_conf(305 DOWNTO 295) <= int2bin(msix_table_size, 11); + init_k_conf(306) <= (mux_select((alpha_tolower(bridge_port_vga_enable) = ("true")), '1', '0')); + init_k_conf(307) <= (mux_select((alpha_tolower(bridge_port_ssid_support) = ("true")), '1', '0')); + init_k_conf(323 DOWNTO 308) <= int2bin(ssvid, 16); + init_k_conf(339 DOWNTO 324) <= int2bin(ssid, 16); + init_k_conf(343 DOWNTO 340) <= int2bin(eie_before_nfts_count, 4); + init_k_conf(351 DOWNTO 344) <= int2bin(gen2_diffclock_nfts_count, 8); + init_k_conf(359 DOWNTO 352) <= int2bin(gen2_sameclock_nfts_count, 8); + init_k_conf(360) <= (mux_select((alpha_tolower(deemphasis_enable) = ("true")), '1', '0')); + init_k_conf(364 DOWNTO 361) <= (mux_select((alpha_tolower(enable_gen2_core) = ("true")), "0010", "0000")); + init_k_conf(367 DOWNTO 365) <= int2bin(l0_exit_latency_sameclock, 3); + init_k_conf(370 DOWNTO 368) <= int2bin(l0_exit_latency_diffclock, 3); + init_k_conf(371) <= (mux_select((alpha_tolower(enable_rx_ei_l0s_exit_refined) = ("true")), '1', '0')); -- reserve + IF (alpha_tolower(disable_async_l2_logic) = "true") THEN + init_k_conf(372) <= '1'; + ELSE + init_k_conf(372) <= '0'; + END IF; + init_k_conf(383 DOWNTO 373) <= "00000000000"; + init_k_hip(0) <= (mux_select((alpha_tolower(enable_adapter_half_rate_mode) = ("true")), '1', '0')); + init_k_hip(1) <= (mux_select((alpha_tolower(vc0_clk_enable) = ("true")), '1', '0')); + init_k_hip(2) <= '0'; -- cycloneiv + init_k_hip(3) <= (mux_select((alpha_tolower(register_pipe_signals) = ("true")), '1', '0')); + init_k_hip(7 DOWNTO 4) <= int2bin(rx0_adap_fifo_full_value, 4); + init_k_hip(11 DOWNTO 8) <= int2bin(rx1_adap_fifo_full_value, 4); + init_k_hip(16 DOWNTO 12) <= int2bin(tx0_adap_fifo_full_value, 5); + init_k_hip(21 DOWNTO 17) <= int2bin(tx1_adap_fifo_full_value, 5); + IF (alpha_tolower(allow_rx_valid_empty) = "true") THEN + init_k_hip(22) <= '1'; + ELSE + init_k_hip(22) <= '0'; + END IF; + init_k_bar(0) <= (mux_select((alpha_tolower(bar0_io_space) = ("true")), '1', '0')); + init_k_bar(2 DOWNTO 1) <= (mux_select((alpha_tolower(bar0_64bit_mem_space) = ("true")), "10", "00")); + init_k_bar(3) <= (mux_select((alpha_tolower(bar0_prefetchable) = ("true")), '1', '0')); + IF (alpha_tolower(bar0_64bit_mem_space) = ("true")) THEN + init_k_bar(63 DOWNTO 4) <= To_StdLogicVector("111111111111111111111111111111111111111111111111111111111111" SLL bin2int(int2bin(bar0_size_mask, 60) - "000000000000000000000000000000000000000000000000000000000100")); + ELSE + init_k_bar(31 DOWNTO 4) <= To_StdLogicVector("1111111111111111111111111111" SLL bin2int(int2bin(bar0_size_mask, 28) - "0000000000000000000000000100")); + init_k_bar(32) <= (mux_select((alpha_tolower(bar1_io_space) = ("true")), '1', '0')); + init_k_bar(34 DOWNTO 33) <= (mux_select((alpha_tolower(bar1_64bit_mem_space) = ("true")), "10", "00")); + init_k_bar(35) <= (mux_select((alpha_tolower(bar1_prefetchable) = ("true")), '1', '0')); + init_k_bar(63 DOWNTO 36) <= To_StdLogicVector("1111111111111111111111111111" SLL bin2int(int2bin(bar1_size_mask, 28) - "0000000000000000000000000100")); + END IF; + init_k_bar(64) <= (mux_select((alpha_tolower(bar2_io_space) = ("true")), '1', '0')); + init_k_bar(66 DOWNTO 65) <= (mux_select((alpha_tolower(bar2_64bit_mem_space) = ("true")), "10", "00")); + init_k_bar(67) <= (mux_select((alpha_tolower(bar2_prefetchable) = ("true")), '1', '0')); + IF (alpha_tolower(bar2_64bit_mem_space) = ("true")) THEN + init_k_bar(127 DOWNTO 68) <= To_StdLogicVector("111111111111111111111111111111111111111111111111111111111111" SLL bin2int(int2bin(bar2_size_mask, 60) - "000000000000000000000000000000000000000000000000000000000100")); + ELSE + init_k_bar(95 DOWNTO 68) <= To_StdLogicVector("1111111111111111111111111111" SLL bin2int(int2bin(bar2_size_mask, 28) - "0000000000000000000000000100")); + init_k_bar(96) <= (mux_select((alpha_tolower(bar3_io_space) = ("true")), '1', '0')); + init_k_bar(98 DOWNTO 97) <= (mux_select((alpha_tolower(bar3_64bit_mem_space) = ("true")), "10", "00")); + init_k_bar(99) <= (mux_select((alpha_tolower(bar3_prefetchable) = ("true")), '1', '0')); + init_k_bar(127 DOWNTO 100) <= To_StdLogicVector("1111111111111111111111111111" SLL bin2int(int2bin(bar3_size_mask, 28) - "0000000000000000000000000100")); + END IF; + init_k_bar(128) <= (mux_select((alpha_tolower(bar4_io_space) = ("true")), '1', '0')); + init_k_bar(130 DOWNTO 129) <= (mux_select((alpha_tolower(bar4_64bit_mem_space) = ("true")), "10", "00")); + init_k_bar(131) <= (mux_select((alpha_tolower(bar4_prefetchable) = ("true")), '1', '0')); + IF (alpha_tolower(bar4_64bit_mem_space) = ("true")) THEN + init_k_bar(191 DOWNTO 132) <= To_StdLogicVector("111111111111111111111111111111111111111111111111111111111111" SLL bin2int(int2bin(bar4_size_mask, 60) - "000000000000000000000000000000000000000000000000000000000100")); + ELSE + init_k_bar(159 DOWNTO 132) <= To_StdLogicVector("1111111111111111111111111111" SLL bin2int(int2bin(bar4_size_mask, 28) - "0000000000000000000000000100")); + init_k_bar(160) <= (mux_select((alpha_tolower(bar5_io_space) = ("true")), '1', '0')); + init_k_bar(162 DOWNTO 161) <= (mux_select((alpha_tolower(bar5_64bit_mem_space) = ("true")), "10", "00")); + init_k_bar(163) <= (mux_select((alpha_tolower(bar5_prefetchable) = ("true")), '1', '0')); + init_k_bar(191 DOWNTO 164) <= To_StdLogicVector("1111111111111111111111111111" SLL bin2int(int2bin(bar5_size_mask, 28) - "0000000000000000000000000100")); + END IF; + IF (expansion_base_address_register > 0) THEN + init_k_bar(223 DOWNTO 192) <= To_StdLogicVector("11111111111111111111111111111111" SLL expansion_base_address_register); + ELSE + init_k_bar(223 DOWNTO 192) <= int2bin(expansion_base_address_register, 32); + END IF; + init_k_bar(225 DOWNTO 224) <= ((mux_select((alpha_tolower(bar_io_window_size) = ("none")), "00", "00")) OR (mux_select((alpha_tolower(bar_io_window_size) = ("16bit")), "01", "00")) OR (mux_select((alpha_tolower(bar_io_window_size) = ("32bit")), "10", "00")) OR "00"); + IF (bar_prefetchable = 32) THEN + init_k_bar(227 DOWNTO 226) <= "01"; + ELSIF (bar_prefetchable = 64) THEN + init_k_bar(227 DOWNTO 226) <= "01"; + ELSE + init_k_bar(227 DOWNTO 226) <= "00"; + END IF; + init_k_cnt(35 DOWNTO 0) <= "000000000000000000000000000000000000"; + init_k_cnt(39 DOWNTO 36) <= int2bin(rx_cdc_full_value, 4); + init_k_cnt(43 DOWNTO 40) <= int2bin(tx_cdc_full_value, 4); + init_k_cnt(51 DOWNTO 44) <= int2bin(rx_idl_os_count, 8); + init_k_cnt(52) <= '0'; + init_k_cnt(56 DOWNTO 53) <= int2bin(tx_cdc_stop_dummy_full_value, 4); + init_k_cnt(64 DOWNTO 57) <= int2bin(ei_delay_powerdown_count, 8); + init_k_cnt(84 DOWNTO 65) <= int2bin(millisecond_cycle_count, 20); + init_k_cnt(95 DOWNTO 85) <= int2bin(skp_os_schedule_count, 11); + init_k_cnt(106 DOWNTO 96) <= int2bin(fc_init_timer, 11); + init_k_cnt(111 DOWNTO 107) <= int2bin(l01_entry_latency, 5); + init_k_cnt(116 DOWNTO 112) <= int2bin(flow_control_update_count, 5); + init_k_cnt(127 DOWNTO 120) <= int2bin(flow_control_timeout_count, 8); + IF (alpha_tolower(credit_buffer_allocation_aux) = ("balanced")) THEN + init_k_vc0_var(7 DOWNTO 0) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00001100", "00010000"); + init_k_vc0_var(19 DOWNTO 8) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000001010000", "000001010000"); + init_k_vc0_var(27 DOWNTO 20) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00001100", "00010100"); + init_k_vc0_var(35 DOWNTO 28) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000000", "00000000"); + init_k_vc0_var(43 DOWNTO 36) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00011100", "00011100"); + init_k_vc0_var(55 DOWNTO 44) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000001110000", "000001110000"); + + init_k_vc1_var(7 DOWNTO 0) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00001100", "00010000"); + init_k_vc1_var(19 DOWNTO 8) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000001010000", "000001010000"); + init_k_vc1_var(27 DOWNTO 20) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00001100", "00010100"); + init_k_vc1_var(35 DOWNTO 28) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000000", "00000000"); + init_k_vc1_var(43 DOWNTO 36) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00011100", "00011100"); + init_k_vc1_var(55 DOWNTO 44) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000001110000", "000001110000"); + + init_k_ptr0 <= calc_k_ptr(init_k_vc0_var, init_use_crc_forwarding_var); + init_k_ptr1 <= calc_k_ptr(init_k_vc1_var, init_use_crc_forwarding_var); + ELSIF (alpha_tolower(credit_buffer_allocation_aux) = ("initiator")) THEN + init_k_vc0_var(7 DOWNTO 0) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00001000", "00001000"); + init_k_vc0_var(19 DOWNTO 8) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000001000000", "000001000000"); + init_k_vc0_var(27 DOWNTO 20) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000110", "00001000"); + init_k_vc0_var(35 DOWNTO 28) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000000", "00000000"); + init_k_vc0_var(43 DOWNTO 36) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00100011", "00100100"); + init_k_vc0_var(55 DOWNTO 44) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000010001000", "000010001100"); + + init_k_vc1_var(7 DOWNTO 0) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00001000", "00001000"); + init_k_vc1_var(19 DOWNTO 8) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000001000000", "000001000000"); + init_k_vc1_var(27 DOWNTO 20) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000110", "00001000"); + init_k_vc1_var(35 DOWNTO 28) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000000", "00000000"); + init_k_vc1_var(43 DOWNTO 36) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00100011", "00100100"); + init_k_vc1_var(55 DOWNTO 44) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000010001000", "000010001100"); + + init_k_ptr0 <= calc_k_ptr(init_k_vc0_var, init_use_crc_forwarding_var); + init_k_ptr1 <= calc_k_ptr(init_k_vc1_var, init_use_crc_forwarding_var); + ELSIF (alpha_tolower(credit_buffer_allocation_aux) = ("target")) THEN + init_k_vc0_var(7 DOWNTO 0) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00010110", "00011100"); + init_k_vc0_var(19 DOWNTO 8) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000010100001", "000010110000"); + init_k_vc0_var(27 DOWNTO 20) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00011100", "00100000"); + init_k_vc0_var(35 DOWNTO 28) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000000", "00000000"); + init_k_vc0_var(43 DOWNTO 36) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000100", "00000100"); + init_k_vc0_var(55 DOWNTO 44) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000000010000", "000000010000"); + + init_k_vc1_var(7 DOWNTO 0) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00010110", "00011100"); + init_k_vc1_var(19 DOWNTO 8) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000010100001", "000010110000"); + init_k_vc1_var(27 DOWNTO 20) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00011100", "00100000"); + init_k_vc1_var(35 DOWNTO 28) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000000", "00000000"); + init_k_vc1_var(43 DOWNTO 36) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "00000100", "00000100"); + init_k_vc1_var(55 DOWNTO 44) := mux_select((alpha_tolower(use_crc_forwarding) = ("true")), "000000010000", "000000010000"); + + init_k_ptr0 <= calc_k_ptr(init_k_vc0_var, init_use_crc_forwarding_var); + init_k_ptr1 <= calc_k_ptr(init_k_vc1_var, init_use_crc_forwarding_var); + ELSIF (alpha_tolower(credit_buffer_allocation_aux) = ("absolute")) THEN + init_k_vc0_var(7 DOWNTO 0) := int2bin(vc0_rx_flow_ctrl_posted_header, 8); + init_k_vc0_var(19 DOWNTO 8) := int2bin(vc0_rx_flow_ctrl_posted_data, 12); + init_k_vc0_var(27 DOWNTO 20) := int2bin(vc0_rx_flow_ctrl_nonposted_header, 8); + init_k_vc0_var(35 DOWNTO 28) := int2bin(vc0_rx_flow_ctrl_nonposted_data, 8); + init_k_vc0_var(43 DOWNTO 36) := int2bin(vc0_rx_flow_ctrl_compl_header, 8); + init_k_vc0_var(55 DOWNTO 44) := int2bin(vc0_rx_flow_ctrl_compl_data, 12); + init_k_vc1_var(7 DOWNTO 0) := int2bin(vc1_rx_flow_ctrl_posted_header, 8); + init_k_vc1_var(19 DOWNTO 8) := int2bin(vc1_rx_flow_ctrl_posted_data, 12); + init_k_vc1_var(27 DOWNTO 20) := int2bin(vc1_rx_flow_ctrl_nonposted_header, 8); + init_k_vc1_var(35 DOWNTO 28) := int2bin(vc1_rx_flow_ctrl_nonposted_data, 8); + init_k_vc1_var(43 DOWNTO 36) := int2bin(vc1_rx_flow_ctrl_compl_header, 8); + + init_k_vc1_var(55 DOWNTO 44) := int2bin(vc1_rx_flow_ctrl_compl_data, 12); + init_k_ptr0(8 DOWNTO 0) <= int2bin(rx_ptr0_posted_dpram_min, 9); + init_k_ptr0(17 DOWNTO 9) <= int2bin(rx_ptr0_posted_dpram_max, 9); + init_k_ptr0(26 DOWNTO 18) <= int2bin(rx_ptr0_nonposted_dpram_min, 9); + init_k_ptr0(35 DOWNTO 27) <= int2bin(rx_ptr0_nonposted_dpram_max, 9); + init_k_ptr1(8 DOWNTO 0) <= int2bin(rx_ptr1_posted_dpram_min, 9); + init_k_ptr1(17 DOWNTO 9) <= int2bin(rx_ptr1_posted_dpram_max, 9); + init_k_ptr1(26 DOWNTO 18) <= int2bin(rx_ptr1_nonposted_dpram_min, 9); + init_k_ptr1(35 DOWNTO 27) <= int2bin(rx_ptr1_nonposted_dpram_max, 9); + END IF; + + -- 273577: overwrite to advertise infinite complete after calc_k_ptr + init_k_vc0_var(55 DOWNTO 36) := "00000000000000000000"; + init_k_vc1_var(55 DOWNTO 36) := "00000000000000000000"; + + init_k_rtry(10 DOWNTO 0) <= int2bin(retry_buffer_last_active_address, 11); + init_k_rtry_mem(29 DOWNTO 0) <= int2bin(retry_buffer_memory_settings, 30); + init_k_rcv0_mem(29 DOWNTO 0) <= int2bin(vc0_rx_buffer_memory_settings,30); + init_k_rcv1_mem(29 DOWNTO 0) <= int2bin(vc1_rx_buffer_memory_settings,30); --mram_bist_settings; + --init_k_rcv_mem0(15 DOWNTO 0) <= int2bin(vc0_rx_buffer_memory_settings, 16); + --init_k_rcv_mem1(15 DOWNTO 0) <= int2bin(vc1_rx_buffer_memory_settings, 16); --mram_bist_settings; + init_k_mem_bist(74 DOWNTO 0) <= "000000000000000000000000000000000000000000000000000000000000000000000000000"; + init_k_core_clk_dbg_sel <= '0'; + + init_use_crc_forwarding <= init_use_crc_forwarding_var; + init_k_vc1 <= init_k_vc1_var; + init_k_vc0 <= init_k_vc0_var; + + WAIT; + + END PROCESS; + + + --///////////////////////////////////////////////////////////////////// + -- init registers to k_bits ----------------------------------------// + --///////////////////////////////////////////////////////////////////// + + k_bar_func0 <= init_k_bar; --sw param name twisted + k_clk_x8_sel_rcv0 <= init_k_clk_x8_sel_rcv0; + k_clk_x8_sel_rcv1 <= init_k_clk_x8_sel_rcv1; + k_clk_x8_sel_rtry <= init_k_clk_x8_sel_rtry; + k_cnt <= init_k_cnt; + k_conf_func0 <= init_k_conf; -- sw param name twisted + k_core_clk_div_sel <= init_k_core_clk_div_sel; + k_core_clk_out_sel <= init_k_core_clk_out_sel; + k_core_clk_source_sel <= init_k_core_clk_source_sel; + k_dev <= init_k_dev; + k_ecc_enable_rtry <= init_k_ecc_enable_rtry; + k_ecc_enable_rcv0 <= init_k_ecc_enable_rcv0; + k_ecc_enable_rcv1 <= init_k_ecc_enable_rcv1; + k_gbl <= init_k_gbl; + k_hip <= init_k_hip; + k_iei_enable <= init_k_iei_enable; + k_mem_bist <= init_k_mem_bist; + k_pclk_sel <= init_k_pclk_sel; + k_pipex1_dbg_sel <= init_k_pipex1_dbg_sel; + k_port <= init_k_port; + k_ptr0 <= init_k_ptr0; + k_ptr1 <= init_k_ptr1; + --k_rcv_mem0 <= init_k_rcv_mem0; + --k_rcv_mem1 <= init_k_rcv_mem1; + k_rcv0_mem <= init_k_rcv0_mem; + k_rcv0_outreg <= init_k_rcv0_outreg; + k_rcv0_raen2 <= init_k_rcv0_raen2; + k_rcv0_rben1 <= init_k_rcv0_rben1; + k_rcv1_mem <= init_k_rcv1_mem; + k_rcv1_outreg <= init_k_rcv1_outreg; + k_rcv1_raen2 <= init_k_rcv1_raen2; + k_rcv1_rben1 <= init_k_rcv1_rben1; + k_rtry <= init_k_rtry; + k_rtry_mem <= init_k_rtry_mem; + k_rtry_outreg <= init_k_rtry_outreg; + k_rtry_raen2 <= init_k_rtry_raen2; + k_rtry_rben1 <= init_k_rtry_rben1; + k_vc0 <= init_k_vc0; + k_vc1 <= init_k_vc1; + k_vc2 <= init_k_vc2; + k_vc3 <= init_k_vc3; + k_vc4 <= init_k_vc4; + k_vc5 <= init_k_vc5; + k_vc6 <= init_k_vc6; + k_vc7 <= init_k_vc7; + + k_core_clk_dbg_sel <= init_k_core_clk_dbg_sel; + + --///////////////////////////////////////////////////////////////////// + -- k_bits to dprio registers ---------------------------------------// + --///////////////////////////////////////////////////////////////////// + + ext_hip_ctrl_1 <= k_gbl(15 DOWNTO 0); + ext_hip_ctrl_2 <= k_gbl(31 DOWNTO 16); + ext_hip_ctrl_3 <= k_gbl(47 DOWNTO 32); + ext_hip_ctrl_4 <= k_gbl(63 DOWNTO 48); + ext_hip_ctrl_5(15 DOWNTO 11) <= k_dev(4 DOWNTO 0); + ext_hip_ctrl_5(7 DOWNTO 0) <= k_port(7 DOWNTO 0); + + -- Register 6[6:0] for clk mux selection, bit [7] to select + -- dbg_pipex1_rx or dbg_pipex1_tx signals, bit [8] to enable IEI logic + ext_hip_ctrl_7(8 DOWNTO 7) <= k_clk_x8_sel_rtry(3 DOWNTO 2); + ext_hip_ctrl_7(6 DOWNTO 5) <= k_clk_x8_sel_rcv1(3 DOWNTO 2); + ext_hip_ctrl_7(4 DOWNTO 3) <= k_clk_x8_sel_rcv0(3 DOWNTO 2); + ext_hip_ctrl_6(15 DOWNTO 14) <= k_clk_x8_sel_rtry(1 DOWNTO 0); + ext_hip_ctrl_6(13 DOWNTO 12) <= k_clk_x8_sel_rcv1(1 DOWNTO 0); + ext_hip_ctrl_6(11 DOWNTO 10) <= k_clk_x8_sel_rcv0(1 DOWNTO 0); + -- ext_hip_ctrl_6(9 DOWNTO 8) <= k_iei_enable; + + ext_hip_ctrl_6(7) <= k_pipex1_dbg_sel; + + ext_hip_ctrl_6(6) <= k_pclk_sel; + ext_hip_ctrl_6(5 DOWNTO 4) <= k_core_clk_source_sel; + ext_hip_ctrl_6(3 DOWNTO 1) <= k_core_clk_div_sel; + ext_hip_ctrl_6(0) <= k_core_clk_out_sel; + ext_hip_ctrl_7(9) <= k_core_clk_dbg_sel; + + -- Register 7 is used for Adapter functions + + ext_hip_ctrl_7(0) <= k_ecc_enable_rcv0; + ext_hip_ctrl_7(1) <= k_ecc_enable_rcv1; + ext_hip_ctrl_7(2) <= k_ecc_enable_rtry; + ext_hip_ctrl_7(15 DOWNTO 12) <= k_hip(7 DOWNTO 4); + + -- Register 8 is used for Adapter functions + + ext_hip_ctrl_8(3 DOWNTO 0) <= k_hip(11 DOWNTO 8); + ext_hip_ctrl_8(8 DOWNTO 4) <= k_hip(16 DOWNTO 12); + ext_hip_ctrl_8(14 DOWNTO 9) <= k_hip(22 DOWNTO 17); + + ext_hip_ctrl_9 <= k_conf_func0(15 DOWNTO 0); + ext_hip_ctrl_10 <= k_conf_func0(31 DOWNTO 16); + ext_hip_ctrl_11 <= k_conf_func0(47 DOWNTO 32); + ext_hip_ctrl_12 <= k_conf_func0(63 DOWNTO 48); + ext_hip_ctrl_13 <= k_conf_func0(79 DOWNTO 64); + ext_hip_ctrl_14 <= k_conf_func0(95 DOWNTO 80); + ext_hip_ctrl_15 <= k_conf_func0(111 DOWNTO 96); + ext_hip_ctrl_16 <= k_conf_func0(127 DOWNTO 112); + ext_hip_ctrl_17 <= k_conf_func0(143 DOWNTO 128); + ext_hip_ctrl_18 <= k_conf_func0(159 DOWNTO 144); + ext_hip_ctrl_19 <= k_conf_func0(175 DOWNTO 160); + ext_hip_ctrl_20 <= k_conf_func0(191 DOWNTO 176); + ext_hip_ctrl_21 <= k_conf_func0(207 DOWNTO 192); + ext_hip_ctrl_22 <= k_conf_func0(223 DOWNTO 208); + ext_hip_ctrl_23 <= k_conf_func0(239 DOWNTO 224); + ext_hip_ctrl_24 <= k_conf_func0(255 DOWNTO 240); + ext_hip_ctrl_25 <= k_conf_func0(271 DOWNTO 256); + ext_hip_ctrl_26 <= k_conf_func0(287 DOWNTO 272); + ext_hip_ctrl_27 <= k_conf_func0(303 DOWNTO 288); + ext_hip_ctrl_28 <= k_conf_func0(319 DOWNTO 304); + ext_hip_ctrl_29 <= k_conf_func0(335 DOWNTO 320); + ext_hip_ctrl_30 <= k_conf_func0(351 DOWNTO 336); + ext_hip_ctrl_31 <= k_conf_func0(367 DOWNTO 352); + ext_hip_ctrl_32 <= k_conf_func0(383 DOWNTO 368); + ext_hip_ctrl_33 <= k_bar_func0(15 DOWNTO 0); + ext_hip_ctrl_34 <= k_bar_func0(31 DOWNTO 16); + ext_hip_ctrl_35 <= k_bar_func0(47 DOWNTO 32); + ext_hip_ctrl_36 <= k_bar_func0(63 DOWNTO 48); + ext_hip_ctrl_37 <= k_bar_func0(79 DOWNTO 64); + ext_hip_ctrl_38 <= k_bar_func0(95 DOWNTO 80); + ext_hip_ctrl_39 <= k_bar_func0(111 DOWNTO 96); + ext_hip_ctrl_40 <= k_bar_func0(127 DOWNTO 112); + ext_hip_ctrl_41 <= k_bar_func0(143 DOWNTO 128); + ext_hip_ctrl_42 <= k_bar_func0(159 DOWNTO 144); + ext_hip_ctrl_43 <= k_bar_func0(175 DOWNTO 160); + ext_hip_ctrl_44 <= k_bar_func0(191 DOWNTO 176); + ext_hip_ctrl_45 <= k_bar_func0(207 DOWNTO 192); + ext_hip_ctrl_46 <= k_bar_func0(223 DOWNTO 208); + ext_hip_ctrl_47(3 DOWNTO 0) <= k_bar_func0(227 DOWNTO 224); + ext_hip_ctrl_48 <= k_cnt(15 DOWNTO 0); + ext_hip_ctrl_49 <= k_cnt(31 DOWNTO 16); + ext_hip_ctrl_50 <= k_cnt(47 DOWNTO 32); + ext_hip_ctrl_51 <= k_cnt(63 DOWNTO 48); + ext_hip_ctrl_52 <= k_cnt(79 DOWNTO 64); + ext_hip_ctrl_53 <= k_cnt(95 DOWNTO 80); + ext_hip_ctrl_54 <= k_cnt(111 DOWNTO 96); + ext_hip_ctrl_55 <= k_cnt(127 DOWNTO 112); + ext_hip_ctrl_56 <= k_vc0(15 DOWNTO 0); + ext_hip_ctrl_57 <= k_vc0(31 DOWNTO 16); + ext_hip_ctrl_58 <= k_vc0(47 DOWNTO 32); + ext_hip_ctrl_59(7 DOWNTO 0) <= k_vc0(55 DOWNTO 48); + ext_hip_ctrl_60 <= k_vc1(15 DOWNTO 0); + ext_hip_ctrl_61 <= k_vc1(31 DOWNTO 16); + ext_hip_ctrl_62 <= k_vc1(47 DOWNTO 32); + ext_hip_ctrl_63(7 DOWNTO 0) <= k_vc1(55 DOWNTO 48); + ext_hip_ctrl_64 <= k_vc2(15 DOWNTO 0); + ext_hip_ctrl_65 <= k_vc2(31 DOWNTO 16); + ext_hip_ctrl_66 <= k_vc2(47 DOWNTO 32); + ext_hip_ctrl_67(7 DOWNTO 0) <= k_vc2(55 DOWNTO 48); + ext_hip_ctrl_68 <= k_vc3(15 DOWNTO 0); + ext_hip_ctrl_69 <= k_vc3(31 DOWNTO 16); + ext_hip_ctrl_70 <= k_vc3(47 DOWNTO 32); + ext_hip_ctrl_71(7 DOWNTO 0) <= k_vc3(55 DOWNTO 48); + ext_hip_ctrl_72 <= k_vc4(15 DOWNTO 0); + ext_hip_ctrl_73 <= k_vc4(31 DOWNTO 16); + ext_hip_ctrl_74 <= k_vc4(47 DOWNTO 32); + ext_hip_ctrl_75(7 DOWNTO 0) <= k_vc4(55 DOWNTO 48); + ext_hip_ctrl_76 <= k_vc5(15 DOWNTO 0); + ext_hip_ctrl_77 <= k_vc5(31 DOWNTO 16); + ext_hip_ctrl_78 <= k_vc5(47 DOWNTO 32); + ext_hip_ctrl_79(7 DOWNTO 0) <= k_vc5(55 DOWNTO 48); + ext_hip_ctrl_80 <= k_vc6(15 DOWNTO 0); + ext_hip_ctrl_81 <= k_vc6(31 DOWNTO 16); + ext_hip_ctrl_82 <= k_vc6(47 DOWNTO 32); + ext_hip_ctrl_83(7 DOWNTO 0) <= k_vc6(55 DOWNTO 48); + ext_hip_ctrl_84 <= k_vc7(15 DOWNTO 0); + ext_hip_ctrl_85 <= k_vc7(31 DOWNTO 16); + ext_hip_ctrl_86 <= k_vc7(47 DOWNTO 32); + ext_hip_ctrl_87(7 DOWNTO 0) <= k_vc7(55 DOWNTO 48); + ext_hip_ctrl_88(15 DOWNTO 12) <= k_hip(3 DOWNTO 0); + ext_hip_ctrl_88(10 DOWNTO 0) <= k_rtry(10 DOWNTO 0); + ext_hip_ctrl_89 <= k_ptr0(15 DOWNTO 0); + ext_hip_ctrl_90 <= k_ptr0(31 DOWNTO 16); + ext_hip_ctrl_91(3 DOWNTO 0) <= k_ptr0(35 DOWNTO 32); + ext_hip_ctrl_92 <= k_ptr1(15 DOWNTO 0); + ext_hip_ctrl_93 <= k_ptr1(31 DOWNTO 16); + ext_hip_ctrl_94(3 DOWNTO 0) <= k_ptr1(35 DOWNTO 32); + ext_hip_ctrl_95 <= k_mem_bist(15 DOWNTO 0); + ext_hip_ctrl_96 <= k_mem_bist(31 DOWNTO 16); + ext_hip_ctrl_97 <= k_mem_bist(47 DOWNTO 32); + ext_hip_ctrl_98 <= k_mem_bist(63 DOWNTO 48); + ext_hip_ctrl_99(10 DOWNTO 0) <= k_mem_bist(74 DOWNTO 64); + + ext_hip_ctrl_100(14 DOWNTO 0) <= k_rtry_mem(14 DOWNTO 0) ; + ext_hip_ctrl_101(14 DOWNTO 0) <= k_rcv0_mem(14 DOWNTO 0) ; + ext_hip_ctrl_102(14 DOWNTO 0) <= k_rcv1_mem(14 DOWNTO 0) ; + + ext_hip_ctrl_103(14 DOWNTO 0) <= k_rtry_mem(29 DOWNTO 15) ; + ext_hip_ctrl_104(14 DOWNTO 0) <= k_rcv0_mem(29 DOWNTO 15) ; + ext_hip_ctrl_105(14 DOWNTO 0) <= k_rcv1_mem(29 DOWNTO 15) ; + ext_hip_ctrl_106(5 DOWNTO 0) <= k_iei_enable ; + + --///////////////////////////////////////////////////////////////////// + -- ext_hip_ctrl to csr_hip_in ---------------------------------------// + --///////////////////////////////////////////////////////////////////// + + csr_hip_in(15 DOWNTO 0) <= ext_hip_ctrl_1; + csr_hip_in(31 DOWNTO 16) <= ext_hip_ctrl_2; + csr_hip_in(47 DOWNTO 32) <= ext_hip_ctrl_3; + csr_hip_in(63 DOWNTO 48) <= ext_hip_ctrl_4; + csr_hip_in(79 DOWNTO 64) <= ext_hip_ctrl_5; + csr_hip_in(95 DOWNTO 80) <= ext_hip_ctrl_6; + csr_hip_in(111 DOWNTO 96) <= ext_hip_ctrl_7; + csr_hip_in(127 DOWNTO 112) <= ext_hip_ctrl_8; + csr_hip_in(143 DOWNTO 128) <= ext_hip_ctrl_9; + csr_hip_in(159 DOWNTO 144) <= ext_hip_ctrl_10; + csr_hip_in(175 DOWNTO 160) <= ext_hip_ctrl_11; + csr_hip_in(191 DOWNTO 176) <= ext_hip_ctrl_12; + csr_hip_in(207 DOWNTO 192) <= ext_hip_ctrl_13; + csr_hip_in(223 DOWNTO 208) <= ext_hip_ctrl_14; + csr_hip_in(239 DOWNTO 224) <= ext_hip_ctrl_15; + csr_hip_in(255 DOWNTO 240) <= ext_hip_ctrl_16; + csr_hip_in(271 DOWNTO 256) <= ext_hip_ctrl_17; + csr_hip_in(287 DOWNTO 272) <= ext_hip_ctrl_18; + csr_hip_in(303 DOWNTO 288) <= ext_hip_ctrl_19; + csr_hip_in(319 DOWNTO 304) <= ext_hip_ctrl_20; + csr_hip_in(335 DOWNTO 320) <= ext_hip_ctrl_21; + csr_hip_in(351 DOWNTO 336) <= ext_hip_ctrl_22; + csr_hip_in(367 DOWNTO 352) <= ext_hip_ctrl_23; + csr_hip_in(383 DOWNTO 368) <= ext_hip_ctrl_24; + csr_hip_in(399 DOWNTO 384) <= ext_hip_ctrl_25; + csr_hip_in(415 DOWNTO 400) <= ext_hip_ctrl_26; + csr_hip_in(431 DOWNTO 416) <= ext_hip_ctrl_27; + csr_hip_in(447 DOWNTO 432) <= ext_hip_ctrl_28; + csr_hip_in(463 DOWNTO 448) <= ext_hip_ctrl_29; + csr_hip_in(479 DOWNTO 464) <= ext_hip_ctrl_30; + csr_hip_in(495 DOWNTO 480) <= ext_hip_ctrl_31; + csr_hip_in(511 DOWNTO 496) <= ext_hip_ctrl_32; + csr_hip_in(527 DOWNTO 512) <= ext_hip_ctrl_33; + csr_hip_in(543 DOWNTO 528) <= ext_hip_ctrl_34; + csr_hip_in(559 DOWNTO 544) <= ext_hip_ctrl_35; + csr_hip_in(575 DOWNTO 560) <= ext_hip_ctrl_36; + csr_hip_in(591 DOWNTO 576) <= ext_hip_ctrl_37; + csr_hip_in(607 DOWNTO 592) <= ext_hip_ctrl_38; + csr_hip_in(623 DOWNTO 608) <= ext_hip_ctrl_39; + csr_hip_in(639 DOWNTO 624) <= ext_hip_ctrl_40; + csr_hip_in(655 DOWNTO 640) <= ext_hip_ctrl_41; + csr_hip_in(671 DOWNTO 656) <= ext_hip_ctrl_42; + csr_hip_in(687 DOWNTO 672) <= ext_hip_ctrl_43; + csr_hip_in(703 DOWNTO 688) <= ext_hip_ctrl_44; + csr_hip_in(719 DOWNTO 704) <= ext_hip_ctrl_45; + csr_hip_in(735 DOWNTO 720) <= ext_hip_ctrl_46; + csr_hip_in(751 DOWNTO 736) <= ext_hip_ctrl_47; + csr_hip_in(767 DOWNTO 752) <= ext_hip_ctrl_48; + csr_hip_in(783 DOWNTO 768) <= ext_hip_ctrl_49; + csr_hip_in(799 DOWNTO 784) <= ext_hip_ctrl_50; + csr_hip_in(815 DOWNTO 800) <= ext_hip_ctrl_51; + csr_hip_in(831 DOWNTO 816) <= ext_hip_ctrl_52; + csr_hip_in(847 DOWNTO 832) <= ext_hip_ctrl_53; + csr_hip_in(863 DOWNTO 848) <= ext_hip_ctrl_54; + csr_hip_in(879 DOWNTO 864) <= ext_hip_ctrl_55; + csr_hip_in(895 DOWNTO 880) <= ext_hip_ctrl_56; + csr_hip_in(911 DOWNTO 896) <= ext_hip_ctrl_57; + csr_hip_in(927 DOWNTO 912) <= ext_hip_ctrl_58; + csr_hip_in(943 DOWNTO 928) <= ext_hip_ctrl_59; + csr_hip_in(959 DOWNTO 944) <= ext_hip_ctrl_60; + csr_hip_in(975 DOWNTO 960) <= ext_hip_ctrl_61; + csr_hip_in(991 DOWNTO 976) <= ext_hip_ctrl_62; + csr_hip_in(1007 DOWNTO 992) <= ext_hip_ctrl_63; + csr_hip_in(1023 DOWNTO 1008) <= ext_hip_ctrl_64; + csr_hip_in(1039 DOWNTO 1024) <= ext_hip_ctrl_65; + csr_hip_in(1055 DOWNTO 1040) <= ext_hip_ctrl_66; + csr_hip_in(1071 DOWNTO 1056) <= ext_hip_ctrl_67; + csr_hip_in(1087 DOWNTO 1072) <= ext_hip_ctrl_68; + csr_hip_in(1103 DOWNTO 1088) <= ext_hip_ctrl_69; + csr_hip_in(1119 DOWNTO 1104) <= ext_hip_ctrl_70; + csr_hip_in(1135 DOWNTO 1120) <= ext_hip_ctrl_71; + csr_hip_in(1151 DOWNTO 1136) <= ext_hip_ctrl_72; + csr_hip_in(1167 DOWNTO 1152) <= ext_hip_ctrl_73; + csr_hip_in(1183 DOWNTO 1168) <= ext_hip_ctrl_74; + csr_hip_in(1199 DOWNTO 1184) <= ext_hip_ctrl_75; + csr_hip_in(1215 DOWNTO 1200) <= ext_hip_ctrl_76; + csr_hip_in(1231 DOWNTO 1216) <= ext_hip_ctrl_77; + csr_hip_in(1247 DOWNTO 1232) <= ext_hip_ctrl_78; + csr_hip_in(1263 DOWNTO 1248) <= ext_hip_ctrl_79; + csr_hip_in(1279 DOWNTO 1264) <= ext_hip_ctrl_80; + csr_hip_in(1295 DOWNTO 1280) <= ext_hip_ctrl_81; + csr_hip_in(1311 DOWNTO 1296) <= ext_hip_ctrl_82; + csr_hip_in(1327 DOWNTO 1312) <= ext_hip_ctrl_83; + csr_hip_in(1343 DOWNTO 1328) <= ext_hip_ctrl_84; + csr_hip_in(1359 DOWNTO 1344) <= ext_hip_ctrl_85; + csr_hip_in(1375 DOWNTO 1360) <= ext_hip_ctrl_86; + csr_hip_in(1391 DOWNTO 1376) <= ext_hip_ctrl_87; + csr_hip_in(1407 DOWNTO 1392) <= ext_hip_ctrl_88; + csr_hip_in(1423 DOWNTO 1408) <= ext_hip_ctrl_89; + csr_hip_in(1439 DOWNTO 1424) <= ext_hip_ctrl_90; + csr_hip_in(1455 DOWNTO 1440) <= ext_hip_ctrl_91; + csr_hip_in(1471 DOWNTO 1456) <= ext_hip_ctrl_92; + csr_hip_in(1487 DOWNTO 1472) <= ext_hip_ctrl_93; + csr_hip_in(1503 DOWNTO 1488) <= ext_hip_ctrl_94; + csr_hip_in(1519 DOWNTO 1504) <= ext_hip_ctrl_95; + csr_hip_in(1535 DOWNTO 1520) <= ext_hip_ctrl_96; + csr_hip_in(1551 DOWNTO 1536) <= ext_hip_ctrl_97; + csr_hip_in(1567 DOWNTO 1552) <= ext_hip_ctrl_98; + csr_hip_in(1583 DOWNTO 1568) <= ext_hip_ctrl_99; + csr_hip_in(1599 DOWNTO 1584) <= ext_hip_ctrl_100; + csr_hip_in(1615 DOWNTO 1600) <= ext_hip_ctrl_101; + csr_hip_in(1631 DOWNTO 1616) <= ext_hip_ctrl_102; + + csr_hip_in(1647 DOWNTO 1632) <= ext_hip_ctrl_103 ; + csr_hip_in(1663 DOWNTO 1648) <= ext_hip_ctrl_104 ; + csr_hip_in(1679 DOWNTO 1664) <= ext_hip_ctrl_105 ; + csr_hip_in(1695 DOWNTO 1680) <= ext_hip_ctrl_106 ; + csr_hip_in(1711 DOWNTO 1696) <= ext_hip_ctrl_107 ; + csr_hip_in(1727 DOWNTO 1712) <= ext_hip_ctrl_108 ; + csr_hip_in(1743 DOWNTO 1728) <= ext_hip_ctrl_109 ; + csr_hip_in(1759 DOWNTO 1744) <= ext_hip_ctrl_110 ; + +END trans; + + + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_unsigned.all; + +--====Revision Log================ +--Rev: 1.6 Fri Mar 14 14:14:11 PDT 2008 + +--**************************************************************************** +--Copyright 2007 -- Altera Corporation +--This confidential code was developed by and is owned by Altera Corporation +--Please do not distribute, copy, modify or reproduce +--without proper written authorization. Please destroy all +--copies immediately upon receipt if you have not received such authorization. +--**************************************************************************** + +--********************************************************* +-- Description +-- This module contains clock generations of pclk_out, core_clk and core_clk_out clocks. +-- pclk goes to the Phy MAC, core_clk to TL/DLL, and core_clk_out to the PLD core. +-- When in Scan mode (scan_en=1), all output clocks follow core_clk_in from the PLD +-- core. When in normal operation, the clocks derive their sources from different +-- inputs based on the CRAMs r_pclk_sel, r_core_clk_source_sel. +-- r_pclk_sel=0 : pclk_central drives pclk_out +-- r_pclk_sel=1 : pclk_ch0 drives pclk_out +-- r_core_clk_source_sel=00 : pll_fixed_clk (500MHz) drives core_clk +-- =01 : pclk_out drives core_clk +-- =10 : core_clk_in drives core_clk +-- =11 : pll_fixed_clk drives core_clk +-- core_clk can be divided down by ratios as shown below: +-- r_core_clk_div_sel =000: div-by-1 core_clk +-- =001: div-by-2 core_clk +-- =010: div_by_1 core_clk +-- =011: div_by_4 core_clk +-- =100: div_by_1 core_clk +-- =101: div_by_8 core_clk +-- =110: div_by_1 core_clk +-- =111: div_by_16 core_clk +-- r_core_clk_out_sel =0 : core_clk_out is div_by_1 version of core_clk +-- =1 : core_clk_out is div_by_2 version of core_clk +-- +--********************************************************* + +ENTITY cycloneiv_pciehip_clkmux IS + PORT ( + + resetn : IN STD_LOGIC; -- resetn for clock dividers + scan_mode : IN STD_LOGIC; -- Scan Enable + pclk_ch0 : IN STD_LOGIC; -- PCLK from Channel 0 + pclk_central : IN STD_LOGIC; -- PCLK from Central block + pll_fixed_clk : IN STD_LOGIC; -- 500MHz clock from PMA PLL + core_clk_in : IN STD_LOGIC; -- input clock from PLD core + r_pclk_sel : IN STD_LOGIC; -- RAM bit to select source for PCLK + r_core_clk_source_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- RAM bits to select core_clk source + r_core_clk_div_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- RAM bits to select division factor for core_clk + r_core_clk_out_sel : IN STD_LOGIC; -- RAM bit to select div-by-2 core_clk to PLD + r_core_clk_dbg_sel : IN STD_LOGIC; -- RAM bit to select core_clk to PHY MAC + + pclk_out : OUT STD_LOGIC; -- PCLK output to PHY MAC + core_clk : OUT STD_LOGIC; -- core_clk output to TL and DLL + core_clk_out : OUT STD_LOGIC -- core_clk output to the PLD core + ); +END cycloneiv_pciehip_clkmux; + +ARCHITECTURE trans OF cycloneiv_pciehip_clkmux IS + + SIGNAL core_clk_by1 : STD_LOGIC; + SIGNAL srst1 : STD_LOGIC; + SIGNAL srst_coreclkout1 : STD_LOGIC; + + SIGNAL srst0 : STD_LOGIC; + SIGNAL srst1_int : STD_LOGIC; + SIGNAL srst_coreclkout0 : STD_LOGIC; + SIGNAL srst_coreclkout1_int : STD_LOGIC; + SIGNAL core_clk_int : STD_LOGIC; + SIGNAL core_clk_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL core_clk_by2 : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL pclk_out_xhdl1 : STD_LOGIC; + SIGNAL core_clk_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + pclk_out <= pclk_out_xhdl1; + core_clk <= core_clk_xhdl0; + + -- ======================== + -- pclk source selection + -- ======================== + -- Select between the Channel 0 PCLK and the central PCLK + pclk_out_xhdl1 <= core_clk_in WHEN ((scan_mode OR r_core_clk_dbg_sel) = '1') ELSE -- Scan always uses core_clk_in, otherwise + pclk_ch0 WHEN (r_pclk_sel = '1') ELSE + pclk_central; + -- default to pclk_central + -- ======================== + -- core_clk source selection + -- ======================== + + -- clocks are assigned below in the order in which they appear in the out flowing clock path + -- to core_clk_out pin + core_clk_by1 <= core_clk_in WHEN (scan_mode = '1') ELSE + pclk_out_xhdl1 WHEN (r_core_clk_source_sel = "01") ELSE + core_clk_in WHEN (r_core_clk_source_sel = "10") ELSE + pll_fixed_clk; + + -- create sync. reset + PROCESS (resetn, core_clk_by1) + BEGIN + IF ((NOT(resetn)) = '1') THEN + srst0 <= '1'; + srst1_int <= '1'; + ELSIF (core_clk_by1'EVENT AND core_clk_by1 = '1') THEN + srst0 <= '0'; + srst1_int <= srst0; + END IF; + END PROCESS; + + + -- Block the reset signal when in Scan mode + srst1 <= '0' WHEN (scan_mode = '1') ELSE + srst1_int; + + -- core_clk division + -- if (reset) + PROCESS (srst1, core_clk_by1) + BEGIN + IF (srst1 = '1') THEN + core_clk_int <= '0'; + core_clk_cnt <= "0000"; + ELSIF (core_clk_by1'EVENT AND core_clk_by1 = '1') THEN + + core_clk_cnt <= core_clk_cnt + "0001"; + CASE r_core_clk_div_sel(2 DOWNTO 1) IS -- div-by-4 + WHEN "01" => -- div-by-8 + core_clk_int <= TRANSPORT core_clk_cnt(1) AFTER 1* 1 ps; + WHEN "10" => -- div-by-16 + core_clk_int <= TRANSPORT core_clk_cnt(2) AFTER 1* 1 ps; + WHEN "11" => -- div-by-2 + core_clk_int <= TRANSPORT core_clk_cnt(3) AFTER 1* 1 ps; + WHEN OTHERS => + core_clk_int <= TRANSPORT core_clk_cnt(0) AFTER 1* 1 ps; + END CASE; + END IF; + END PROCESS; + + + core_clk_xhdl0 <= core_clk_by1 WHEN ((scan_mode = '1') OR (r_core_clk_div_sel(0) = '0')) ELSE -- core_clk to TL and DLL + core_clk_int; + + -- ======================== + -- core_clk_out selection + -- ======================== + -- This register is used to generate divided by two clock. + + -- always @(negedge resetn or posedge core_clk_by1) + PROCESS (resetn, core_clk_xhdl0) + BEGIN + IF ((NOT(resetn)) = '1') THEN + srst_coreclkout0 <= '1'; + srst_coreclkout1_int <= '1'; + ELSIF (core_clk_xhdl0'EVENT AND core_clk_xhdl0 = '1') THEN + srst_coreclkout0 <= '0'; + srst_coreclkout1_int <= srst_coreclkout0; + END IF; + END PROCESS; + + + -- Block the reset signal when in Scan mode + srst_coreclkout1 <= '0' WHEN (scan_mode = '1') ELSE + srst_coreclkout1_int; + + PROCESS (srst_coreclkout1, core_clk_xhdl0) + BEGIN + IF (srst_coreclkout1 = '1') THEN + core_clk_by2 <= TRANSPORT '0' AFTER 1* 1 ps; + ELSIF (core_clk_xhdl0'EVENT AND core_clk_xhdl0 = '1') THEN + core_clk_by2 <= NOT(core_clk_by2); + END IF; + END PROCESS; + + + core_clk_out <= core_clk_by2 WHEN (r_core_clk_out_sel = '1') ELSE + core_clk_xhdl0; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_dprio_bit IS + PORT ( + + reset : IN STD_LOGIC; -- reset + clk : IN STD_LOGIC; -- clock + sig_in : IN STD_LOGIC; -- signal input + ext_in : IN STD_LOGIC; -- external input port + serial_mode : IN STD_LOGIC; -- serial shift mode enable + si : IN STD_LOGIC; -- scan input + shift : IN STD_LOGIC; -- 1'b1=shift in data from si into scan flop + -- 1'b0=load data from sig_in into scan flop + mdio_dis : IN STD_LOGIC; -- 1'b1=choose ext_in to the sig_out mux + -- 1'b0=choose so to the sign_out mux + sig_out : OUT STD_LOGIC; -- signal output + so : OUT STD_LOGIC -- scan output + ); +END cycloneiv_pciehip_dprio_bit; + +ARCHITECTURE trans OF cycloneiv_pciehip_dprio_bit IS + + SIGNAL cram_int : STD_LOGIC; + SIGNAL set_int : STD_LOGIC; + + -- Declare intermediate signals for referenced outputs + SIGNAL so_xhdl0 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + so <= so_xhdl0; + + -- select signal output + sig_out <= (so_xhdl0 AND NOT(shift)) WHEN (serial_mode = '1') ELSE + (cram_int); + cram_int <= (ext_in) WHEN (mdio_dis = '1') ELSE + (so_xhdl0); + + -- Set signal for the flop + set_int <= '0' WHEN (shift = '1' OR reset = '1') ELSE + ext_in; + + -- scan flop + PROCESS (reset, set_int, clk) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + so_xhdl0 <= '0'; + ELSIF (set_int = '1') THEN + so_xhdl0 <= '1'; + ELSIF (clk'EVENT AND clk = '1') THEN + IF ((shift AND serial_mode) = '1') THEN + so_xhdl0 <= si; + ELSE + + so_xhdl0 <= sig_in; + END IF; + END IF; + END PROCESS; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_dprio_16bit IS + PORT ( + + reset : IN STD_LOGIC; -- reset + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; -- clock + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- signal input + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- external port input + serial_mode : IN STD_LOGIC; -- serial shift mode enable + si : IN STD_LOGIC; -- scan input + shift : IN STD_LOGIC; -- 1'b1=shift in data from si into scan flop + -- 1'b0=load data from sig_in into scan flop + mdio_dis : IN STD_LOGIC; -- + -- 1'b1=output CRAM + -- 1'b0=output MDIO control register + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- signal output + so : OUT STD_LOGIC -- scan output + ); +END cycloneiv_pciehip_dprio_16bit; + +ARCHITECTURE trans OF cycloneiv_pciehip_dprio_16bit IS + COMPONENT cycloneiv_pciehip_dprio_bit + PORT ( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC; + ext_in : IN STD_LOGIC; + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + sig_out : OUT STD_LOGIC; + so : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL signal_in_int : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL chain : STD_LOGIC_VECTOR(14 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL sig_out_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL so_xhdl1 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + sig_out <= sig_out_xhdl0; + so <= so_xhdl1; + + signal_in_int <= sig_in WHEN ((("000000000000000" & mdio_wr) AND int2bin((reg_addr = target_addr), 16)) /= "0000000000000000") ELSE + (so_xhdl1 & chain); + + + + ctrl_reg_bit_0 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(0), + ext_in => ext_in(0), + serial_mode => serial_mode, + si => si, + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(0), + so => chain(0) + ); + + + + ctrl_reg_bit_1 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(1), + ext_in => ext_in(1), + serial_mode => serial_mode, + si => chain(0), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(1), + so => chain(1) + ); + + + + ctrl_reg_bit_2 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(2), + ext_in => ext_in(2), + serial_mode => serial_mode, + si => chain(1), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(2), + so => chain(2) + ); + + + + ctrl_reg_bit_3 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(3), + ext_in => ext_in(3), + serial_mode => serial_mode, + si => chain(2), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(3), + so => chain(3) + ); + + + + ctrl_reg_bit_4 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(4), + ext_in => ext_in(4), + serial_mode => serial_mode, + si => chain(3), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(4), + so => chain(4) + ); + + + + ctrl_reg_bit_5 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(5), + ext_in => ext_in(5), + serial_mode => serial_mode, + si => chain(4), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(5), + so => chain(5) + ); + + + + ctrl_reg_bit_6 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(6), + ext_in => ext_in(6), + serial_mode => serial_mode, + si => chain(5), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(6), + so => chain(6) + ); + + + + ctrl_reg_bit_7 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(7), + ext_in => ext_in(7), + serial_mode => serial_mode, + si => chain(6), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(7), + so => chain(7) + ); + + + + ctrl_reg_bit_8 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(8), + ext_in => ext_in(8), + serial_mode => serial_mode, + si => chain(7), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(8), + so => chain(8) + ); + + + + ctrl_reg_bit_9 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(9), + ext_in => ext_in(9), + serial_mode => serial_mode, + si => chain(8), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(9), + so => chain(9) + ); + + + + ctrl_reg_bit_10 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(10), + ext_in => ext_in(10), + serial_mode => serial_mode, + si => chain(9), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(10), + so => chain(10) + ); + + + + ctrl_reg_bit_11 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(11), + ext_in => ext_in(11), + serial_mode => serial_mode, + si => chain(10), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(11), + so => chain(11) + ); + + + + ctrl_reg_bit_12 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(12), + ext_in => ext_in(12), + serial_mode => serial_mode, + si => chain(11), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(12), + so => chain(12) + ); + + + + ctrl_reg_bit_13 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(13), + ext_in => ext_in(13), + serial_mode => serial_mode, + si => chain(12), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(13), + so => chain(13) + ); + + + + ctrl_reg_bit_14 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(14), + ext_in => ext_in(14), + serial_mode => serial_mode, + si => chain(13), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(14), + so => chain(14) + ); + + + + ctrl_reg_bit_15 : cycloneiv_pciehip_dprio_bit + PORT MAP ( + reset => reset, + clk => clk, + sig_in => signal_in_int(15), + ext_in => ext_in(15), + serial_mode => serial_mode, + si => chain(14), + shift => shift, + mdio_dis => mdio_dis, + sig_out => sig_out_xhdl0(15), + so => so_xhdl1 + ); + +END trans; + + +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 33 mux21 32 oper_add 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_pciehip_dprio_addr IS + PORT + ( + incr_addr : IN STD_LOGIC; + mdc : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + reg_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + reset : IN STD_LOGIC; + shift_addr : IN STD_LOGIC + ); + END cycloneiv_pciehip_dprio_addr; + + ARCHITECTURE RTL OF cycloneiv_pciehip_dprio_addr IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nlO0i15 : STD_LOGIC := '0'; + SIGNAL nlO0i16 : STD_LOGIC := '0'; + SIGNAL nlO0l13 : STD_LOGIC := '0'; + SIGNAL nlO0l14 : STD_LOGIC := '0'; + SIGNAL nlO0O11 : STD_LOGIC := '0'; + SIGNAL nlO0O12 : STD_LOGIC := '0'; + SIGNAL wire_nlO0O12_w_lg_w_lg_q45w46w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O12_w_lg_q45w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOii10 : STD_LOGIC := '0'; + SIGNAL wire_nlOii10_w_lg_w_lg_q37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii10_w_lg_q37w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOii9 : STD_LOGIC := '0'; + SIGNAL nlOil7 : STD_LOGIC := '0'; + SIGNAL nlOil8 : STD_LOGIC := '0'; + SIGNAL wire_nlOil8_w_lg_w_lg_q33w34w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOil8_w_lg_q33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOiO5 : STD_LOGIC := '0'; + SIGNAL nlOiO6 : STD_LOGIC := '0'; + SIGNAL wire_nlOiO6_w_lg_w_lg_q30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO6_w_lg_q30w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOli3 : STD_LOGIC := '0'; + SIGNAL nlOli4 : STD_LOGIC := '0'; + SIGNAL wire_nlOli4_w_lg_w_lg_q25w26w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOli4_w_lg_q25w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlOOi1 : STD_LOGIC := '0'; + SIGNAL nlOOi2 : STD_LOGIC := '0'; + SIGNAL n0il : STD_LOGIC := '0'; + SIGNAL n0iO : STD_LOGIC := '0'; + SIGNAL n0li : STD_LOGIC := '0'; + SIGNAL n0ll : STD_LOGIC := '0'; + SIGNAL n0lO : STD_LOGIC := '0'; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL ni0i : STD_LOGIC := '0'; + SIGNAL ni0l : STD_LOGIC := '0'; + SIGNAL ni0O : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1l : STD_LOGIC := '0'; + SIGNAL ni1O : STD_LOGIC := '0'; + SIGNAL niii : STD_LOGIC := '0'; + SIGNAL niil : STD_LOGIC := '0'; + SIGNAL nili : STD_LOGIC := '0'; + SIGNAL wire_niiO_CLRN : STD_LOGIC; + SIGNAL wire_niiO_PRN : STD_LOGIC; + SIGNAL wire_niiO_w_lg_w14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w14w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w13w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w7w8w9w10w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w7w8w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_w_lg_niil1w2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_w_lg_niil1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niiO_w_lg_niil1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nlO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_ni_a : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_ni_b : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_ni_o : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_w_lg_nlOlO19w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reset98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO1O : STD_LOGIC; + SIGNAL nlOll : STD_LOGIC; + SIGNAL nlOlO : STD_LOGIC; + BEGIN + + wire_gnd <= '0'; + wire_w_lg_nlOlO19w(0) <= NOT nlOlO; + wire_w_lg_reset98w(0) <= NOT reset; + nlO1O <= '1'; + nlOll <= (wire_w_lg_nlOlO19w(0) AND incr_addr); + nlOlO <= (wire_niiO_w_lg_w14w15w(0) AND (nlOOi2 XOR nlOOi1)); + reg_addr <= ( niil & niii & ni0O & ni0l & ni0i & ni1O & ni1l & ni1i & n0OO & n0Ol & n0Oi & n0lO & n0ll & n0li & n0iO & n0il); + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0i15 <= nlO0i16; + END IF; + if (now = 0 ns) then + nlO0i15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0i16 <= nlO0i15; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0l13 <= nlO0l14; + END IF; + if (now = 0 ns) then + nlO0l13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0l14 <= nlO0l13; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0O11 <= nlO0O12; + END IF; + if (now = 0 ns) then + nlO0O11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlO0O12 <= nlO0O11; + END IF; + END PROCESS; + wire_nlO0O12_w_lg_w_lg_q45w46w(0) <= wire_nlO0O12_w_lg_q45w(0) AND niil; + wire_nlO0O12_w_lg_q45w(0) <= nlO0O12 XOR nlO0O11; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOii10 <= nlOii9; + END IF; + END PROCESS; + wire_nlOii10_w_lg_w_lg_q37w38w(0) <= wire_nlOii10_w_lg_q37w(0) AND ni1l; + wire_nlOii10_w_lg_q37w(0) <= nlOii10 XOR nlOii9; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOii9 <= nlOii10; + END IF; + if (now = 0 ns) then + nlOii9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOil7 <= nlOil8; + END IF; + if (now = 0 ns) then + nlOil7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOil8 <= nlOil7; + END IF; + END PROCESS; + wire_nlOil8_w_lg_w_lg_q33w34w(0) <= wire_nlOil8_w_lg_q33w(0) AND n0OO; + wire_nlOil8_w_lg_q33w(0) <= nlOil8 XOR nlOil7; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOiO5 <= nlOiO6; + END IF; + if (now = 0 ns) then + nlOiO5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOiO6 <= nlOiO5; + END IF; + END PROCESS; + wire_nlOiO6_w_lg_w_lg_q30w31w(0) <= wire_nlOiO6_w_lg_q30w(0) AND n0Ol; + wire_nlOiO6_w_lg_q30w(0) <= nlOiO6 XOR nlOiO5; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOli3 <= nlOli4; + END IF; + if (now = 0 ns) then + nlOli3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOli4 <= nlOli3; + END IF; + END PROCESS; + wire_nlOli4_w_lg_w_lg_q25w26w(0) <= wire_nlOli4_w_lg_q25w(0) AND n0ll; + wire_nlOli4_w_lg_q25w(0) <= nlOli4 XOR nlOli3; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOOi1 <= nlOOi2; + END IF; + if (now = 0 ns) then + nlOOi1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nlOOi2 <= nlOOi1; + END IF; + END PROCESS; + PROCESS (mdc, wire_niiO_PRN, wire_niiO_CLRN) + BEGIN + IF (wire_niiO_PRN = '0') THEN + n0il <= '1'; + n0iO <= '1'; + n0li <= '1'; + n0ll <= '1'; + n0lO <= '1'; + n0Oi <= '1'; + n0Ol <= '1'; + n0OO <= '1'; + ni0i <= '1'; + ni0l <= '1'; + ni0O <= '1'; + ni1i <= '1'; + ni1l <= '1'; + ni1O <= '1'; + niii <= '1'; + niil <= '1'; + nili <= '1'; + ELSIF (wire_niiO_CLRN = '0') THEN + n0il <= '0'; + n0iO <= '0'; + n0li <= '0'; + n0ll <= '0'; + n0lO <= '0'; + n0Oi <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + ni0i <= '0'; + ni0l <= '0'; + ni0O <= '0'; + ni1i <= '0'; + ni1l <= '0'; + ni1O <= '0'; + niii <= '0'; + niil <= '0'; + nili <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + n0il <= wire_nill_dataout; + n0iO <= wire_nilO_dataout; + n0li <= wire_niOi_dataout; + n0ll <= wire_niOl_dataout; + n0lO <= wire_niOO_dataout; + n0Oi <= wire_nl1i_dataout; + n0Ol <= wire_nl1l_dataout; + n0OO <= wire_nl1O_dataout; + ni0i <= wire_nlii_dataout; + ni0l <= wire_nlil_dataout; + ni0O <= wire_nliO_dataout; + ni1i <= wire_nl0i_dataout; + ni1l <= wire_nl0l_dataout; + ni1O <= wire_nl0O_dataout; + niii <= wire_nlli_dataout; + niil <= wire_nlll_dataout; + nili <= mdio_in; + END IF; + END PROCESS; + wire_niiO_CLRN <= ((nlO0l14 XOR nlO0l13) AND wire_w_lg_reset98w(0)); + wire_niiO_PRN <= (nlO0i16 XOR nlO0i15); + wire_niiO_w_lg_w14w15w(0) <= wire_niiO_w14w(0) AND n0il; + wire_niiO_w14w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w13w(0) AND n0iO; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w13w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w(0) AND n0li; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w12w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w(0) AND n0ll; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w7w8w9w10w11w(0) <= wire_niiO_w_lg_w_lg_w_lg_w7w8w9w10w(0) AND n0lO; + wire_niiO_w_lg_w_lg_w_lg_w7w8w9w10w(0) <= wire_niiO_w_lg_w_lg_w7w8w9w(0) AND n0Oi; + wire_niiO_w_lg_w_lg_w7w8w9w(0) <= wire_niiO_w_lg_w7w8w(0) AND n0Ol; + wire_niiO_w_lg_w7w8w(0) <= wire_niiO_w7w(0) AND n0OO; + wire_niiO_w7w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w6w(0) AND ni1i; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w6w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w(0) AND ni1l; + wire_niiO_w_lg_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w5w(0) <= wire_niiO_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w(0) AND ni1O; + wire_niiO_w_lg_w_lg_w_lg_w_lg_niil1w2w3w4w(0) <= wire_niiO_w_lg_w_lg_w_lg_niil1w2w3w(0) AND ni0i; + wire_niiO_w_lg_w_lg_w_lg_niil1w2w3w(0) <= wire_niiO_w_lg_w_lg_niil1w2w(0) AND ni0l; + wire_niiO_w_lg_w_lg_niil1w2w(0) <= wire_niiO_w_lg_niil1w(0) AND ni0O; + wire_niiO_w_lg_niil1w(0) <= niil AND niii; + wire_n0i_dataout <= wire_ni_o(7) WHEN nlOll = '1' ELSE n0OO; + wire_n0l_dataout <= wire_ni_o(8) WHEN nlOll = '1' ELSE ni1i; + wire_n0O_dataout <= wire_ni_o(9) WHEN nlOll = '1' ELSE ni1l; + wire_n1i_dataout <= wire_ni_o(4) WHEN nlOll = '1' ELSE n0lO; + wire_n1l_dataout <= wire_ni_o(5) WHEN nlOll = '1' ELSE n0Oi; + wire_n1O_dataout <= wire_ni_o(6) WHEN nlOll = '1' ELSE n0Ol; + wire_nii_dataout <= wire_ni_o(10) WHEN nlOll = '1' ELSE ni1O; + wire_nil_dataout <= wire_ni_o(11) WHEN nlOll = '1' ELSE ni0i; + wire_nill_dataout <= nili WHEN shift_addr = '1' ELSE wire_nllO_dataout; + wire_nilO_dataout <= n0il WHEN shift_addr = '1' ELSE wire_nlOi_dataout; + wire_niO_dataout <= wire_ni_o(12) WHEN nlOll = '1' ELSE ni0l; + wire_niOi_dataout <= n0iO WHEN shift_addr = '1' ELSE wire_nlOl_dataout; + wire_niOl_dataout <= n0li WHEN shift_addr = '1' ELSE wire_nlOO_dataout; + wire_niOO_dataout <= n0ll WHEN shift_addr = '1' ELSE wire_n1i_dataout; + wire_nl0i_dataout <= n0OO WHEN shift_addr = '1' ELSE wire_n0l_dataout; + wire_nl0l_dataout <= ni1i WHEN shift_addr = '1' ELSE wire_n0O_dataout; + wire_nl0O_dataout <= ni1l WHEN shift_addr = '1' ELSE wire_nii_dataout; + wire_nl1i_dataout <= n0lO WHEN shift_addr = '1' ELSE wire_n1l_dataout; + wire_nl1l_dataout <= n0Oi WHEN shift_addr = '1' ELSE wire_n1O_dataout; + wire_nl1O_dataout <= n0Ol WHEN shift_addr = '1' ELSE wire_n0i_dataout; + wire_nli_dataout <= wire_ni_o(13) WHEN nlOll = '1' ELSE ni0O; + wire_nlii_dataout <= ni1O WHEN shift_addr = '1' ELSE wire_nil_dataout; + wire_nlil_dataout <= ni0i WHEN shift_addr = '1' ELSE wire_niO_dataout; + wire_nliO_dataout <= ni0l WHEN shift_addr = '1' ELSE wire_nli_dataout; + wire_nll_dataout <= wire_ni_o(14) WHEN nlOll = '1' ELSE niii; + wire_nlli_dataout <= ni0O WHEN shift_addr = '1' ELSE wire_nll_dataout; + wire_nlll_dataout <= niii WHEN shift_addr = '1' ELSE wire_nlO_dataout; + wire_nllO_dataout <= wire_ni_o(0) WHEN nlOll = '1' ELSE n0il; + wire_nlO_dataout <= wire_ni_o(15) WHEN nlOll = '1' ELSE niil; + wire_nlOi_dataout <= wire_ni_o(1) WHEN nlOll = '1' ELSE n0iO; + wire_nlOl_dataout <= wire_ni_o(2) WHEN nlOll = '1' ELSE n0li; + wire_nlOO_dataout <= wire_ni_o(3) WHEN nlOll = '1' ELSE n0ll; + wire_ni_a <= ( wire_nlO0O12_w_lg_w_lg_q45w46w & niii & ni0O & ni0l & ni0i & ni1O & wire_nlOii10_w_lg_w_lg_q37w38w & ni1i & wire_nlOil8_w_lg_w_lg_q33w34w & wire_nlOiO6_w_lg_w_lg_q30w31w & n0Oi & n0lO & wire_nlOli4_w_lg_w_lg_q25w26w & n0li & n0iO & n0il); + wire_ni_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + ni : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 16, + width_b => 16, + width_o => 16 + ) + PORT MAP ( + a => wire_ni_a, + b => wire_ni_b, + cin => wire_gnd, + o => wire_ni_o + ); + + END RTL; --cycloneiv_pciehip_dprio_addr +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 17 mux21 10 oper_add 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_pciehip_dprio_cnt IS + PORT + ( + cnt_eq_0 : OUT STD_LOGIC; + cnt_val : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + ld_cnt : IN STD_LOGIC; + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC + ); + END cycloneiv_pciehip_dprio_cnt; + + ARCHITECTURE RTL OF cycloneiv_pciehip_dprio_cnt IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL ni0O10 : STD_LOGIC := '0'; + SIGNAL ni0O9 : STD_LOGIC := '0'; + SIGNAL ni1O11 : STD_LOGIC := '0'; + SIGNAL ni1O12 : STD_LOGIC := '0'; + SIGNAL niiO7 : STD_LOGIC := '0'; + SIGNAL niiO8 : STD_LOGIC := '0'; + SIGNAL nili5 : STD_LOGIC := '0'; + SIGNAL nili6 : STD_LOGIC := '0'; + SIGNAL nill3 : STD_LOGIC := '0'; + SIGNAL nill4 : STD_LOGIC := '0'; + SIGNAL wire_nill4_w_lg_w_lg_q16w17w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nill4_w_lg_q16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi1 : STD_LOGIC := '0'; + SIGNAL niOi2 : STD_LOGIC := '0'; + SIGNAL n1i : STD_LOGIC := '0'; + SIGNAL ni : STD_LOGIC := '0'; + SIGNAL nlOi : STD_LOGIC := '0'; + SIGNAL nlOl : STD_LOGIC := '0'; + SIGNAL nlOO : STD_LOGIC := '0'; + SIGNAL wire_nlO_CLRN : STD_LOGIC; + SIGNAL wire_nlO_PRN : STD_LOGIC; + SIGNAL wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_w_lg_w_lg_ni1w2w3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_w_lg_ni1w2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO_w_lg_ni1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_nii_dataout : STD_LOGIC; + SIGNAL wire_nil_dataout : STD_LOGIC; + SIGNAL wire_niO_dataout : STD_LOGIC; + SIGNAL wire_nli_dataout : STD_LOGIC; + SIGNAL wire_nll_dataout : STD_LOGIC; + SIGNAL wire_nl_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_nl_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_w_lg_ld_cnt51w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_ni0l50w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reset33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni0l : STD_LOGIC; + SIGNAL niil : STD_LOGIC; + SIGNAL nilO : STD_LOGIC; + BEGIN + + wire_gnd <= '0'; + wire_w_lg_ld_cnt51w(0) <= NOT ld_cnt; + wire_w_lg_ni0l50w(0) <= NOT ni0l; + wire_w_lg_reset33w(0) <= NOT reset; + cnt_eq_0 <= ((wire_w_lg_ni0l50w(0) AND wire_w_lg_ld_cnt51w(0)) AND (ni1O12 XOR ni1O11)); + ni0l <= (wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w(0) OR (NOT (ni0O10 XOR ni0O9))); + niil <= '1'; + nilO <= (wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w(0) OR (NOT (niOi2 XOR niOi1))); + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni0O10 <= ni0O9; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni0O9 <= ni0O10; + END IF; + if (now = 0 ns) then + ni0O9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni1O11 <= ni1O12; + END IF; + if (now = 0 ns) then + ni1O11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN ni1O12 <= ni1O11; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niiO7 <= niiO8; + END IF; + if (now = 0 ns) then + niiO7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niiO8 <= niiO7; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nili5 <= nili6; + END IF; + if (now = 0 ns) then + nili5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nili6 <= nili5; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nill3 <= nill4; + END IF; + if (now = 0 ns) then + nill3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nill4 <= nill3; + END IF; + END PROCESS; + wire_nill4_w_lg_w_lg_q16w17w(0) <= wire_nill4_w_lg_q16w(0) AND n1i; + wire_nill4_w_lg_q16w(0) <= nill4 XOR nill3; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOi1 <= niOi2; + END IF; + if (now = 0 ns) then + niOi1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOi2 <= niOi1; + END IF; + END PROCESS; + PROCESS (mdc, wire_nlO_PRN, wire_nlO_CLRN) + BEGIN + IF (wire_nlO_PRN = '0') THEN + n1i <= '1'; + ni <= '1'; + nlOi <= '1'; + nlOl <= '1'; + nlOO <= '1'; + ELSIF (wire_nlO_CLRN = '0') THEN + n1i <= '0'; + ni <= '0'; + nlOi <= '0'; + nlOl <= '0'; + nlOO <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + n1i <= wire_n0O_dataout; + ni <= wire_n1l_dataout; + nlOi <= wire_n1O_dataout; + nlOl <= wire_n0i_dataout; + nlOO <= wire_n0l_dataout; + END IF; + END PROCESS; + wire_nlO_CLRN <= ((nili6 XOR nili5) AND wire_w_lg_reset33w(0)); + wire_nlO_PRN <= (niiO8 XOR niiO7); + wire_nlO_w_lg_w_lg_w_lg_w_lg_ni1w2w3w4w(0) <= wire_nlO_w_lg_w_lg_w_lg_ni1w2w3w(0) OR nlOi; + wire_nlO_w_lg_w_lg_w_lg_ni1w2w3w(0) <= wire_nlO_w_lg_w_lg_ni1w2w(0) OR nlOl; + wire_nlO_w_lg_w_lg_ni1w2w(0) <= wire_nlO_w_lg_ni1w(0) OR nlOO; + wire_nlO_w_lg_ni1w(0) <= ni OR n1i; + wire_n0i_dataout <= cnt_val(2) WHEN ld_cnt = '1' ELSE wire_niO_dataout; + wire_n0l_dataout <= cnt_val(3) WHEN ld_cnt = '1' ELSE wire_nli_dataout; + wire_n0O_dataout <= cnt_val(4) WHEN ld_cnt = '1' ELSE wire_nll_dataout; + wire_n1l_dataout <= cnt_val(0) WHEN ld_cnt = '1' ELSE wire_nii_dataout; + wire_n1O_dataout <= cnt_val(1) WHEN ld_cnt = '1' ELSE wire_nil_dataout; + wire_nii_dataout <= wire_nl_o(1) WHEN nilO = '1' ELSE ni; + wire_nil_dataout <= wire_nl_o(2) WHEN nilO = '1' ELSE nlOi; + wire_niO_dataout <= wire_nl_o(3) WHEN nilO = '1' ELSE nlOl; + wire_nli_dataout <= wire_nl_o(4) WHEN nilO = '1' ELSE nlOO; + wire_nll_dataout <= wire_nl_o(5) WHEN nilO = '1' ELSE n1i; + wire_nl_a <= ( wire_nill4_w_lg_w_lg_q16w17w & nlOO & nlOl & nlOi & ni & "1"); + wire_nl_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + nl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_nl_a, + b => wire_nl_b, + cin => wire_gnd, + o => wire_nl_o + ); + + END RTL; --cycloneiv_pciehip_dprio_cnt +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + +--synthesis_resources = lut 47 mux21 36 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_pciehip_dprio_ctl_data IS + PORT + ( + data_enable_n : OUT STD_LOGIC; + dev_addr : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + latch_ctl : IN STD_LOGIC; + ld_data : IN STD_LOGIC; + mbus_in : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + mbus_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + mdc : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + mdio_out : OUT STD_LOGIC; + opcode : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + port_addr : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + reset : IN STD_LOGIC; + shift_in : IN STD_LOGIC; + shift_out : IN STD_LOGIC; + valid_addr : OUT STD_LOGIC; + valid_addr_lt : IN STD_LOGIC + ); + END cycloneiv_pciehip_dprio_ctl_data; + + ARCHITECTURE RTL OF cycloneiv_pciehip_dprio_ctl_data IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nilll25 : STD_LOGIC := '0'; + SIGNAL nilll26 : STD_LOGIC := '0'; + SIGNAL nilOi23 : STD_LOGIC := '0'; + SIGNAL nilOi24 : STD_LOGIC := '0'; + SIGNAL nilOO21 : STD_LOGIC := '0'; + SIGNAL nilOO22 : STD_LOGIC := '0'; + SIGNAL niO0i17 : STD_LOGIC := '0'; + SIGNAL niO0i18 : STD_LOGIC := '0'; + SIGNAL niO0O15 : STD_LOGIC := '0'; + SIGNAL niO0O16 : STD_LOGIC := '0'; + SIGNAL niO1l19 : STD_LOGIC := '0'; + SIGNAL niO1l20 : STD_LOGIC := '0'; + SIGNAL niOil13 : STD_LOGIC := '0'; + SIGNAL niOil14 : STD_LOGIC := '0'; + SIGNAL niOiO11 : STD_LOGIC := '0'; + SIGNAL niOiO12 : STD_LOGIC := '0'; + SIGNAL niOlO10 : STD_LOGIC := '0'; + SIGNAL niOlO9 : STD_LOGIC := '0'; + SIGNAL niOOl7 : STD_LOGIC := '0'; + SIGNAL niOOl8 : STD_LOGIC := '0'; + SIGNAL nl10l3 : STD_LOGIC := '0'; + SIGNAL nl10l4 : STD_LOGIC := '0'; + SIGNAL nl11l5 : STD_LOGIC := '0'; + SIGNAL nl11l6 : STD_LOGIC := '0'; + SIGNAL nl1iO1 : STD_LOGIC := '0'; + SIGNAL nl1iO2 : STD_LOGIC := '0'; + SIGNAL wire_nl1iO2_w_lg_q6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1li : STD_LOGIC := '0'; + SIGNAL n1lO : STD_LOGIC := '0'; + SIGNAL wire_n1ll_PRN : STD_LOGIC; + SIGNAL n00i : STD_LOGIC := '0'; + SIGNAL n00l : STD_LOGIC := '0'; + SIGNAL n00O : STD_LOGIC := '0'; + SIGNAL n01l : STD_LOGIC := '0'; + SIGNAL n01O : STD_LOGIC := '0'; + SIGNAL n0ii : STD_LOGIC := '0'; + SIGNAL n0il : STD_LOGIC := '0'; + SIGNAL n0iO : STD_LOGIC := '0'; + SIGNAL n0li : STD_LOGIC := '0'; + SIGNAL n0ll : STD_LOGIC := '0'; + SIGNAL n0lO : STD_LOGIC := '0'; + SIGNAL n0Oi : STD_LOGIC := '0'; + SIGNAL n0Ol : STD_LOGIC := '0'; + SIGNAL n0OO : STD_LOGIC := '0'; + SIGNAL n1iO : STD_LOGIC := '0'; + SIGNAL n1Oi : STD_LOGIC := '0'; + SIGNAL ni0i : STD_LOGIC := '0'; + SIGNAL ni1i : STD_LOGIC := '0'; + SIGNAL ni1l : STD_LOGIC := '0'; + SIGNAL wire_ni1O_CLRN : STD_LOGIC; + SIGNAL wire_ni1O_w_lg_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w9w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_w_lg_w_lg_ni1i2w4w7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_w_lg_ni1i2w4w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0Oi34w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0lO33w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0OO3w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_ni1i2w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n00i107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n00l115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0li84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1O_w_lg_n0ll92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i_dataout : STD_LOGIC; + SIGNAL wire_n0l_dataout : STD_LOGIC; + SIGNAL wire_n0O_dataout : STD_LOGIC; + SIGNAL wire_n1i_dataout : STD_LOGIC; + SIGNAL wire_n1l_dataout : STD_LOGIC; + SIGNAL wire_n1O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O_dataout : STD_LOGIC; + SIGNAL wire_niii_dataout : STD_LOGIC; + SIGNAL wire_niil_dataout : STD_LOGIC; + SIGNAL wire_niiO_dataout : STD_LOGIC; + SIGNAL wire_nili_dataout : STD_LOGIC; + SIGNAL wire_nill_dataout : STD_LOGIC; + SIGNAL wire_nilO_dataout : STD_LOGIC; + SIGNAL wire_niOi_dataout : STD_LOGIC; + SIGNAL wire_niOl_dataout : STD_LOGIC; + SIGNAL wire_niOO_dataout : STD_LOGIC; + SIGNAL wire_nl_dataout : STD_LOGIC; + SIGNAL wire_nl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O_dataout : STD_LOGIC; + SIGNAL wire_nlii_dataout : STD_LOGIC; + SIGNAL wire_nlil_dataout : STD_LOGIC; + SIGNAL wire_nliO_dataout : STD_LOGIC; + SIGNAL wire_nlli_dataout : STD_LOGIC; + SIGNAL wire_nlll_dataout : STD_LOGIC; + SIGNAL wire_nllO_dataout : STD_LOGIC; + SIGNAL wire_nlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO_dataout : STD_LOGIC; + SIGNAL wire_nO_dataout : STD_LOGIC; + SIGNAL wire_w_lg_reset30w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_out48w49w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_out48w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOll : STD_LOGIC; + SIGNAL nl10i : STD_LOGIC; + SIGNAL nl11i : STD_LOGIC; + SIGNAL nl11O : STD_LOGIC; + SIGNAL nl1ii : STD_LOGIC; + SIGNAL nl1il : STD_LOGIC; + SIGNAL wire_w_dev_addr_range106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dev_addr_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_port_addr_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_port_addr_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_w_lg_reset30w(0) <= NOT reset; + wire_w_lg_w_lg_shift_out48w49w(0) <= wire_w_lg_shift_out48w(0) OR n01l; + wire_w_lg_shift_out48w(0) <= shift_out OR ld_data; + data_enable_n <= (NOT ((wire_w_lg_w_lg_shift_out48w49w(0) AND (nl10i OR valid_addr_lt)) AND (niO0O16 XOR niO0O15))); + mbus_in <= ( ni0i & ni1l & ni1i & n0OO & n0Ol & n0Oi & n0lO & n0ll & n0li & n0iO & n0il & n0ii & n00O & n00l & n00i & n01O); + mdio_out <= wire_nl_dataout; + niOll <= (((n0Oi AND n0lO) OR (wire_ni1O_w_lg_n0Oi34w(0) AND (niOOl8 XOR niOOl7))) OR (NOT (niOlO10 XOR niOlO9))); + nl10i <= (wire_ni1O_w_lg_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w9w(0) AND (nl10l4 XOR nl10l3)); + nl11i <= '1'; + nl11O <= (shift_in OR shift_out); + nl1ii <= ((((((NOT (n01O XOR dev_addr(0))) AND (NOT (wire_ni1O_w_lg_n00i107w(0) XOR (NOT (nilOO22 XOR nilOO21))))) AND (NOT (wire_ni1O_w_lg_n00l115w(0) XOR (NOT (nilOi24 XOR nilOi23))))) AND (NOT (n00O XOR dev_addr(3)))) AND (NOT (n0ii XOR dev_addr(4)))) AND (nilll26 XOR nilll25)); + nl1il <= (((((NOT (n0il XOR port_addr(0))) AND (NOT (n0iO XOR port_addr(1)))) AND (NOT (wire_ni1O_w_lg_n0li84w(0) XOR (NOT (niO0i18 XOR niO0i17))))) AND (NOT (wire_ni1O_w_lg_n0ll92w(0) XOR (NOT (niO1l20 XOR niO1l19))))) AND (NOT (n0lO XOR port_addr(4)))); + opcode <= ( n1lO & n1li); + valid_addr <= nl10i; + wire_w_dev_addr_range106w(0) <= dev_addr(1); + wire_w_dev_addr_range114w(0) <= dev_addr(2); + wire_w_port_addr_range83w(0) <= port_addr(2); + wire_w_port_addr_range91w(0) <= port_addr(3); + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilll25 <= nilll26; + END IF; + if (now = 0 ns) then + nilll25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilll26 <= nilll25; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOi23 <= nilOi24; + END IF; + if (now = 0 ns) then + nilOi23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOi24 <= nilOi23; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOO21 <= nilOO22; + END IF; + if (now = 0 ns) then + nilOO21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nilOO22 <= nilOO21; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0i17 <= niO0i18; + END IF; + if (now = 0 ns) then + niO0i17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0i18 <= niO0i17; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0O15 <= niO0O16; + END IF; + if (now = 0 ns) then + niO0O15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO0O16 <= niO0O15; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO1l19 <= niO1l20; + END IF; + if (now = 0 ns) then + niO1l19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niO1l20 <= niO1l19; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOil13 <= niOil14; + END IF; + if (now = 0 ns) then + niOil13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOil14 <= niOil13; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOiO11 <= niOiO12; + END IF; + if (now = 0 ns) then + niOiO11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOiO12 <= niOiO11; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOlO10 <= niOlO9; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOlO9 <= niOlO10; + END IF; + if (now = 0 ns) then + niOlO9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOOl7 <= niOOl8; + END IF; + if (now = 0 ns) then + niOOl7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN niOOl8 <= niOOl7; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl10l3 <= nl10l4; + END IF; + if (now = 0 ns) then + nl10l3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl10l4 <= nl10l3; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl11l5 <= nl11l6; + END IF; + if (now = 0 ns) then + nl11l5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl11l6 <= nl11l5; + END IF; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl1iO1 <= nl1iO2; + END IF; + if (now = 0 ns) then + nl1iO1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (mdc) + BEGIN + IF (mdc = '1' AND mdc'event) THEN nl1iO2 <= nl1iO1; + END IF; + END PROCESS; + wire_nl1iO2_w_lg_q6w(0) <= nl1iO2 XOR nl1iO1; + PROCESS (mdc, wire_n1ll_PRN, reset) + BEGIN + IF (wire_n1ll_PRN = '0') THEN + n1li <= '1'; + n1lO <= '1'; + ELSIF (reset = '1') THEN + n1li <= '0'; + n1lO <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + IF (latch_ctl = '1') THEN + n1li <= n0lO; + n1lO <= n0Oi; + END IF; + END IF; + END PROCESS; + wire_n1ll_PRN <= (niOil14 XOR niOil13); + PROCESS (mdc, wire_ni1O_CLRN) + BEGIN + IF (wire_ni1O_CLRN = '0') THEN + n00i <= '0'; + n00l <= '0'; + n00O <= '0'; + n01l <= '0'; + n01O <= '0'; + n0ii <= '0'; + n0il <= '0'; + n0iO <= '0'; + n0li <= '0'; + n0ll <= '0'; + n0lO <= '0'; + n0Oi <= '0'; + n0Ol <= '0'; + n0OO <= '0'; + n1iO <= '0'; + n1Oi <= '0'; + ni0i <= '0'; + ni1i <= '0'; + ni1l <= '0'; + ELSIF (mdc = '1' AND mdc'event) THEN + n00i <= wire_ni0O_dataout; + n00l <= wire_niii_dataout; + n00O <= wire_niil_dataout; + n01l <= wire_n1Ol_dataout; + n01O <= wire_ni0l_dataout; + n0ii <= wire_niiO_dataout; + n0il <= wire_nili_dataout; + n0iO <= wire_nill_dataout; + n0li <= wire_nilO_dataout; + n0ll <= wire_niOi_dataout; + n0lO <= wire_niOl_dataout; + n0Oi <= wire_niOO_dataout; + n0Ol <= wire_nl1i_dataout; + n0OO <= wire_nl1l_dataout; + n1iO <= wire_n1OO_dataout; + n1Oi <= mdio_in; + ni0i <= wire_nl0l_dataout; + ni1i <= wire_nl1O_dataout; + ni1l <= wire_nl0i_dataout; + END IF; + END PROCESS; + wire_ni1O_CLRN <= ((nl11l6 XOR nl11l5) AND wire_w_lg_reset30w(0)); + wire_ni1O_w_lg_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w9w(0) <= wire_ni1O_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w(0) AND nl1ii; + wire_ni1O_w_lg_w_lg_w_lg_w_lg_ni1i2w4w7w8w(0) <= wire_ni1O_w_lg_w_lg_w_lg_ni1i2w4w7w(0) AND nl1il; + wire_ni1O_w_lg_w_lg_w_lg_ni1i2w4w7w(0) <= wire_ni1O_w_lg_w_lg_ni1i2w4w(0) AND wire_nl1iO2_w_lg_q6w(0); + wire_ni1O_w_lg_w_lg_ni1i2w4w(0) <= wire_ni1O_w_lg_ni1i2w(0) AND wire_ni1O_w_lg_n0OO3w(0); + wire_ni1O_w_lg_n0Oi34w(0) <= n0Oi AND wire_ni1O_w_lg_n0lO33w(0); + wire_ni1O_w_lg_n0lO33w(0) <= NOT n0lO; + wire_ni1O_w_lg_n0OO3w(0) <= NOT n0OO; + wire_ni1O_w_lg_ni1i2w(0) <= NOT ni1i; + wire_ni1O_w_lg_n00i107w(0) <= n00i XOR wire_w_dev_addr_range106w(0); + wire_ni1O_w_lg_n00l115w(0) <= n00l XOR wire_w_dev_addr_range114w(0); + wire_ni1O_w_lg_n0li84w(0) <= n0li XOR wire_w_port_addr_range83w(0); + wire_ni1O_w_lg_n0ll92w(0) <= n0ll XOR wire_w_port_addr_range91w(0); + wire_n0i_dataout <= n0OO WHEN nl11O = '1' ELSE ni1i; + wire_n0l_dataout <= ni1i WHEN nl11O = '1' ELSE ni1l; + wire_n0O_dataout <= ni1l WHEN nl11O = '1' ELSE ni0i; + wire_n1i_dataout <= n0lO WHEN nl11O = '1' ELSE n0Oi; + wire_n1l_dataout <= n0Oi WHEN nl11O = '1' ELSE n0Ol; + wire_n1O_dataout <= n0Ol WHEN nl11O = '1' ELSE n0OO; + wire_n1Ol_dataout <= niOll WHEN latch_ctl = '1' ELSE ((n01l AND n1iO) AND (niOiO12 XOR niOiO11)); + wire_n1OO_dataout <= niOll AND latch_ctl; + wire_ni0l_dataout <= mbus_out(15) WHEN ld_data = '1' ELSE wire_nl0O_dataout; + wire_ni0O_dataout <= mbus_out(0) WHEN ld_data = '1' ELSE wire_nlii_dataout; + wire_niii_dataout <= mbus_out(1) WHEN ld_data = '1' ELSE wire_nlil_dataout; + wire_niil_dataout <= mbus_out(2) WHEN ld_data = '1' ELSE wire_nliO_dataout; + wire_niiO_dataout <= mbus_out(3) WHEN ld_data = '1' ELSE wire_nlli_dataout; + wire_nili_dataout <= mbus_out(4) WHEN ld_data = '1' ELSE wire_nlll_dataout; + wire_nill_dataout <= mbus_out(5) WHEN ld_data = '1' ELSE wire_nllO_dataout; + wire_nilO_dataout <= mbus_out(6) WHEN ld_data = '1' ELSE wire_nlOi_dataout; + wire_niOi_dataout <= mbus_out(7) WHEN ld_data = '1' ELSE wire_nlOl_dataout; + wire_niOl_dataout <= mbus_out(8) WHEN ld_data = '1' ELSE wire_nlOO_dataout; + wire_niOO_dataout <= mbus_out(9) WHEN ld_data = '1' ELSE wire_n1i_dataout; + wire_nl_dataout <= mbus_out(15) WHEN ld_data = '1' ELSE wire_nO_dataout; + wire_nl0i_dataout <= mbus_out(13) WHEN ld_data = '1' ELSE wire_n0l_dataout; + wire_nl0l_dataout <= mbus_out(14) WHEN ld_data = '1' ELSE wire_n0O_dataout; + wire_nl0O_dataout <= n1Oi WHEN nl11O = '1' ELSE n01O; + wire_nl1i_dataout <= mbus_out(10) WHEN ld_data = '1' ELSE wire_n1l_dataout; + wire_nl1l_dataout <= mbus_out(11) WHEN ld_data = '1' ELSE wire_n1O_dataout; + wire_nl1O_dataout <= mbus_out(12) WHEN ld_data = '1' ELSE wire_n0i_dataout; + wire_nlii_dataout <= n01O WHEN nl11O = '1' ELSE n00i; + wire_nlil_dataout <= n00i WHEN nl11O = '1' ELSE n00l; + wire_nliO_dataout <= n00l WHEN nl11O = '1' ELSE n00O; + wire_nlli_dataout <= n00O WHEN nl11O = '1' ELSE n0ii; + wire_nlll_dataout <= n0ii WHEN nl11O = '1' ELSE n0il; + wire_nllO_dataout <= n0il WHEN nl11O = '1' ELSE n0iO; + wire_nlOi_dataout <= n0iO WHEN nl11O = '1' ELSE n0li; + wire_nlOl_dataout <= n0li WHEN nl11O = '1' ELSE n0ll; + wire_nlOO_dataout <= n0ll WHEN nl11O = '1' ELSE n0lO; + wire_nO_dataout <= ni0i AND shift_out; + + END RTL; --cycloneiv_pciehip_dprio_ctl_data +--synopsys translate_on +--VALID FILE + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_dprio_sm IS + GENERIC ( + + IDLE : INTEGER := 0; + PREAMBLE : INTEGER := 1; + CONTROL : INTEGER := 2; + TURN_ARND_0 : INTEGER := 3; + TURN_ARND_1 : INTEGER := 4; + ADDR_DATA : INTEGER := 5; + ADDR_OP : INTEGER := 0; + WR_OP : INTEGER := 1; + RD_INC_OP : INTEGER := 2; + RD_OP : INTEGER := 3 + ); + PORT ( + mdc : IN STD_LOGIC; -- Clock for MDIO interface + mdio_in : IN STD_LOGIC; -- Signal bit data + reset : IN STD_LOGIC; -- Active high Hard Reset + opcode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- 2 bit opcode from mdio_ctl_data module + -- 00 - Address + -- 01 - Write + -- 10 - Read with no post Increment + -- 11 - Read with post increment + valid_addr : IN STD_LOGIC; -- When set the Port and Dev Address + -- corresponds to this module + cnt_eq_0 : IN STD_LOGIC; -- From mdio_cnt module, down counter is 0 + shift_in : OUT STD_LOGIC; -- Shift in enable for either data or control + shift_out : OUT STD_LOGIC; -- Shift out enable for mdio_ctl_data + latch_ctl : OUT STD_LOGIC; -- Latch the Opcode, to mdio_ctl_data + incr_addr : OUT STD_LOGIC; -- Increment signal for mdio_addr + mdio_wr : OUT STD_LOGIC; -- This is used for writing the mdio registers + mdio_rd : OUT STD_LOGIC; -- This is used for clearing the mdio status registers + shift_addr : OUT STD_LOGIC; -- Shift in Enable for mdio_addr + ld_data : OUT STD_LOGIC; -- When set, the shift register is mdio_ctl_data is parallely + -- loaded with the data from mdio_reg module + --output ld_data_d; + ld_cnt : OUT STD_LOGIC; -- Load Down counter + cnt_val : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Value to load the down counter + valid_addr_lt : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END cycloneiv_pciehip_dprio_sm; + +ARCHITECTURE trans OF cycloneiv_pciehip_dprio_sm IS + + --wire ld_data_d; + + -- Allowed states for curr_state and next_state + + -- Decode for opcode + + SIGNAL next_state : STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL cnt_val_xhdl0 : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL curr_state_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0); +BEGIN + -- Drive referenced outputs + cnt_val <= cnt_val_xhdl0; + curr_state <= curr_state_xhdl1; + + -- Latch Curr State + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + curr_state_xhdl1 <= int2bin(IDLE, 3); + ELSIF (mdc'EVENT AND mdc = '1') THEN + curr_state_xhdl1 <= next_state; + END IF; + END PROCESS; + + -- Next State loic for mdio_sm + + PROCESS (curr_state_xhdl1, mdio_in, cnt_eq_0, valid_addr, opcode) +VARIABLE txt : LINE; + BEGIN +-- shawn manual fix IF (curr_state_xhdl1'EVENT) THEN + + CASE curr_state_xhdl1 IS + + WHEN "000" => + IF (mdio_in = '1') THEN + next_state <= int2bin(PREAMBLE, 3); + ELSE + next_state <= int2bin(IDLE, 3); + END IF; + WHEN "001" => + IF ((NOT(mdio_in) AND NOT(cnt_eq_0)) = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSIF ((NOT(mdio_in) AND cnt_eq_0) = '1') THEN + next_state <= int2bin(CONTROL, 3); + ELSE + next_state <= int2bin(PREAMBLE, 3); + END IF; + + WHEN "010" => + IF (cnt_eq_0 = '1') THEN + IF ((NOT(mdio_in)) = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSE + next_state <= int2bin(TURN_ARND_0, 3); + END IF; + ELSE + next_state <= int2bin(CONTROL, 3); + END IF; + + WHEN "011" => + IF ((mdio_in OR NOT(valid_addr)) = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSIF (opcode = int2bin(WR_OP, 2) OR opcode = int2bin(ADDR_OP, 2)) THEN + next_state <= int2bin(TURN_ARND_1, 3); + ELSE + next_state <= int2bin(ADDR_DATA, 3); + END IF; + -- if (mdio_in) + -- next_state <= IDLE; + -- else + + WHEN "100" => + next_state <= int2bin(ADDR_DATA, 3); + + WHEN "101" => + IF ((cnt_eq_0 AND mdio_in) = '1' AND (opcode = int2bin(WR_OP, 2) OR opcode = int2bin(ADDR_OP, 2))) THEN + next_state <= int2bin(PREAMBLE, 3); + ELSIF (cnt_eq_0 = '1') THEN + next_state <= int2bin(IDLE, 3); + ELSE + next_state <= int2bin(ADDR_DATA, 3); + END IF; + + WHEN OTHERS => + next_state <= int2bin(IDLE, 3); + END CASE; +-- shawn manual fix END IF; + END PROCESS; + + -- Valid_addr_lt is used to enable mdio_out + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + valid_addr_lt <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (valid_addr = '1' AND curr_state_xhdl1 = int2bin(TURN_ARND_0, 3)) THEN + valid_addr_lt <= '1'; + ELSIF (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND cnt_eq_0 = '1') THEN + valid_addr_lt <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for shift_in, This signal is used for shifting in + -- control logic, during all commands, and data during + -- Write command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + shift_in <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(PREAMBLE, 3) AND next_state = int2bin(CONTROL, 3)) OR (next_state = int2bin(CONTROL, 3)) OR (next_state = int2bin(ADDR_DATA, 3) AND opcode = int2bin(WR_OP, 2))) THEN + shift_in <= '1'; + ELSE + shift_in <= '0'; + END IF; + END IF; + END PROCESS; + + -- Shift_out logic, shift_out is set when data is shifted out on + -- a RD_OP or RD_INC_OP command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + shift_out <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3)) OR (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND (opcode = int2bin(RD_OP, 2) OR opcode = int2bin(RD_INC_OP, 2)) AND ((NOT(cnt_eq_0))) = '1')) THEN + shift_out <= '1'; + ELSE + shift_out <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for latch_ctl, this signal is used for latching the opcode + -- This signal is set when in Control state and moving to TURN_ARND_0 + -- state + + PROCESS (cnt_eq_0, curr_state_xhdl1) +VARIABLE txt : LINE; + BEGIN + IF (curr_state_xhdl1'EVENT) THEN + + -- Logic for incr_addr, incr_addr is set for opcode RD_INC_OP and + -- after completely shifting out the read data for the current command + + latch_ctl <= cnt_eq_0 AND int2bin((curr_state_xhdl1 = int2bin(CONTROL, 3)), 3)(0); + END IF; + END PROCESS; + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + incr_addr <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND cnt_eq_0 = '1' AND opcode = int2bin(RD_INC_OP, 2)) THEN + incr_addr <= '1'; + ELSE + incr_addr <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for shift addr, this bit is set when moving to ADDR_DATA + -- state and when in ADDR_DATA state for ADDR_OP command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + shift_addr <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (next_state = int2bin(ADDR_DATA, 3) AND opcode = int2bin(ADDR_OP, 2)) THEN + shift_addr <= '1'; + ELSE + shift_addr <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for mdio_wr, this bit is set when moving from ADDR_DATA to the + -- IDLE for a WR_OP command + -- Logic for mdio_rd, this bit is set when moving from ADDR_DATA to the + -- IDLE for a RD_OP/RD_INC_OP command + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + mdio_wr <= '0'; + mdio_rd <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND cnt_eq_0 = '1') THEN + IF (opcode = int2bin(WR_OP, 2)) THEN + mdio_wr <= '1'; + ELSE + mdio_wr <= '0'; + END IF; + IF (opcode = int2bin(RD_OP, 2) OR opcode = int2bin(RD_INC_OP, 2)) THEN + mdio_rd <= '1'; + ELSE + mdio_rd <= '0'; + END IF; + ELSE + mdio_wr <= '0'; + mdio_rd <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for ld_data, this signal is used for parallely loading the + -- shift register in mdio_ctl_data module with the data from mdio_reg + -- module. This set is set for RD_OP and RD_INC_OP commands when the + -- SM transitions from TURN_ARND_0 to ADDR_DATA state + -- assign ld_data_d = (curr_state == TURN_ARND_0 && (opcode == RD_OP | opcode == RD_INC_OP)); + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + ld_data <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + ld_data <= int2bit((curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3))); + END IF; + END PROCESS; + + -- Logic for ld_cnt, this signal is used for loading the down counter + -- with cnt_val signal. This signal is set when going to + -- CONTROL state or ADDR_DATA state or PREAMBLE states + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + ld_cnt <= '0'; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(IDLE, 3) AND next_state = int2bin(PREAMBLE, 3)) OR (curr_state_xhdl1 = int2bin(ADDR_DATA, 3) AND next_state = int2bin(PREAMBLE, 3)) OR (curr_state_xhdl1 = int2bin(PREAMBLE, 3) AND next_state = int2bin(CONTROL, 3)) OR (curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3)) OR (curr_state_xhdl1 = int2bin(TURN_ARND_1, 3) AND next_state = int2bin(ADDR_DATA, 3))) THEN + ld_cnt <= '1'; + ELSE + ld_cnt <= '0'; + END IF; + END IF; + END PROCESS; + + -- Logic for cnt_val, this counter value is used for sown counting + -- the mdio_cnt, when the counter reaches zero, the cnt_eq_0 is + -- set. The counter is loading with 31 for PREAMBLE, 13 for + -- CONTROL, and 15 for ADDR_DATA + + PROCESS (reset, mdc) +VARIABLE txt : LINE; + BEGIN + IF (reset = '1') THEN + cnt_val_xhdl0 <= "00000"; + ELSIF (mdc'EVENT AND mdc = '1') THEN + IF ((curr_state_xhdl1 = int2bin(IDLE, 3) OR curr_state_xhdl1 = int2bin(ADDR_DATA, 3)) AND next_state = int2bin(PREAMBLE, 3)) THEN + cnt_val_xhdl0 <= "11110"; + ELSIF (curr_state_xhdl1 = int2bin(PREAMBLE, 3) AND next_state = int2bin(CONTROL, 3)) THEN + cnt_val_xhdl0 <= "01100"; + ELSIF (curr_state_xhdl1 = int2bin(TURN_ARND_0, 3) AND next_state = int2bin(ADDR_DATA, 3)) THEN + cnt_val_xhdl0 <= "01110"; + ELSIF (curr_state_xhdl1 = int2bin(TURN_ARND_1, 3) AND next_state = int2bin(ADDR_DATA, 3)) THEN + cnt_val_xhdl0 <= "01110"; + ELSE + cnt_val_xhdl0 <= cnt_val_xhdl0; + END IF; + END IF; + END PROCESS; + +END trans; + + + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + +ENTITY cycloneiv_pciehip_dprio_bus_out_mux IS + PORT ( + + hip_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + hip_ctrl_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END ENTITY cycloneiv_pciehip_dprio_bus_out_mux; + +ARCHITECTURE trans OF cycloneiv_pciehip_dprio_bus_out_mux IS +BEGIN + + hip_ctrl_out <= hip_ctrl_in1 WHEN (reg_addr = hw_address_ctrl_in1) ELSE + hip_ctrl_in2 WHEN (reg_addr = hw_address_ctrl_in2) ELSE + hip_ctrl_in3 WHEN (reg_addr = hw_address_ctrl_in3) ELSE + hip_ctrl_in4 WHEN (reg_addr = hw_address_ctrl_in4) ELSE + hip_ctrl_in5 WHEN (reg_addr = hw_address_ctrl_in5) ELSE + hip_ctrl_in6 WHEN (reg_addr = hw_address_ctrl_in6) ELSE + hip_ctrl_in7 WHEN (reg_addr = hw_address_ctrl_in7) ELSE + hip_ctrl_in8 WHEN (reg_addr = hw_address_ctrl_in8) ELSE + hip_ctrl_in9 WHEN (reg_addr = hw_address_ctrl_in9) ELSE + hip_ctrl_in10 WHEN (reg_addr = hw_address_ctrl_in10) ELSE + hip_ctrl_in11 WHEN (reg_addr = hw_address_ctrl_in11) ELSE + hip_ctrl_in12 WHEN (reg_addr = hw_address_ctrl_in12) ELSE + hip_ctrl_in13 WHEN (reg_addr = hw_address_ctrl_in13) ELSE + hip_ctrl_in14 WHEN (reg_addr = hw_address_ctrl_in14) ELSE + hip_ctrl_in15 WHEN (reg_addr = hw_address_ctrl_in15) ELSE + hip_ctrl_in16 WHEN (reg_addr = hw_address_ctrl_in16) ELSE + hip_ctrl_in17 WHEN (reg_addr = hw_address_ctrl_in17) ELSE + hip_ctrl_in18 WHEN (reg_addr = hw_address_ctrl_in18) ELSE + hip_ctrl_in19 WHEN (reg_addr = hw_address_ctrl_in19) ELSE + hip_ctrl_in20 WHEN (reg_addr = hw_address_ctrl_in20) ELSE + hip_ctrl_in21 WHEN (reg_addr = hw_address_ctrl_in21) ELSE + hip_ctrl_in22 WHEN (reg_addr = hw_address_ctrl_in22) ELSE + hip_ctrl_in23 WHEN (reg_addr = hw_address_ctrl_in23) ELSE + hip_ctrl_in24 WHEN (reg_addr = hw_address_ctrl_in24) ELSE + hip_ctrl_in25 WHEN (reg_addr = hw_address_ctrl_in25) ELSE + hip_ctrl_in26 WHEN (reg_addr = hw_address_ctrl_in26) ELSE + hip_ctrl_in27 WHEN (reg_addr = hw_address_ctrl_in27) ELSE + hip_ctrl_in28 WHEN (reg_addr = hw_address_ctrl_in28) ELSE + hip_ctrl_in29 WHEN (reg_addr = hw_address_ctrl_in29) ELSE + hip_ctrl_in30 WHEN (reg_addr = hw_address_ctrl_in30) ELSE + hip_ctrl_in31 WHEN (reg_addr = hw_address_ctrl_in31) ELSE + hip_ctrl_in32 WHEN (reg_addr = hw_address_ctrl_in32) ELSE + hip_ctrl_in33 WHEN (reg_addr = hw_address_ctrl_in33) ELSE + hip_ctrl_in34 WHEN (reg_addr = hw_address_ctrl_in34) ELSE + hip_ctrl_in35 WHEN (reg_addr = hw_address_ctrl_in35) ELSE + hip_ctrl_in36 WHEN (reg_addr = hw_address_ctrl_in36) ELSE + hip_ctrl_in37 WHEN (reg_addr = hw_address_ctrl_in37) ELSE + hip_ctrl_in38 WHEN (reg_addr = hw_address_ctrl_in38) ELSE + hip_ctrl_in39 WHEN (reg_addr = hw_address_ctrl_in39) ELSE + hip_ctrl_in40 WHEN (reg_addr = hw_address_ctrl_in40) ELSE + hip_ctrl_in41 WHEN (reg_addr = hw_address_ctrl_in41) ELSE + hip_ctrl_in42 WHEN (reg_addr = hw_address_ctrl_in42) ELSE + hip_ctrl_in43 WHEN (reg_addr = hw_address_ctrl_in43) ELSE + hip_ctrl_in44 WHEN (reg_addr = hw_address_ctrl_in44) ELSE + hip_ctrl_in45 WHEN (reg_addr = hw_address_ctrl_in45) ELSE + hip_ctrl_in46 WHEN (reg_addr = hw_address_ctrl_in46) ELSE + hip_ctrl_in47 WHEN (reg_addr = hw_address_ctrl_in47) ELSE + hip_ctrl_in48 WHEN (reg_addr = hw_address_ctrl_in48) ELSE + hip_ctrl_in49 WHEN (reg_addr = hw_address_ctrl_in49) ELSE + hip_ctrl_in50 WHEN (reg_addr = hw_address_ctrl_in50) ELSE + hip_ctrl_in51 WHEN (reg_addr = hw_address_ctrl_in51) ELSE + hip_ctrl_in52 WHEN (reg_addr = hw_address_ctrl_in52) ELSE + hip_ctrl_in53 WHEN (reg_addr = hw_address_ctrl_in53) ELSE + hip_ctrl_in54 WHEN (reg_addr = hw_address_ctrl_in54) ELSE + hip_ctrl_in55 WHEN (reg_addr = hw_address_ctrl_in55) ELSE + hip_ctrl_in56 WHEN (reg_addr = hw_address_ctrl_in56) ELSE + hip_ctrl_in57 WHEN (reg_addr = hw_address_ctrl_in57) ELSE + hip_ctrl_in58 WHEN (reg_addr = hw_address_ctrl_in58) ELSE + hip_ctrl_in59 WHEN (reg_addr = hw_address_ctrl_in59) ELSE + hip_ctrl_in60 WHEN (reg_addr = hw_address_ctrl_in60) ELSE + hip_ctrl_in61 WHEN (reg_addr = hw_address_ctrl_in61) ELSE + hip_ctrl_in62 WHEN (reg_addr = hw_address_ctrl_in62) ELSE + hip_ctrl_in63 WHEN (reg_addr = hw_address_ctrl_in63) ELSE + hip_ctrl_in64 WHEN (reg_addr = hw_address_ctrl_in64) ELSE + hip_ctrl_in65 WHEN (reg_addr = hw_address_ctrl_in65) ELSE + hip_ctrl_in66 WHEN (reg_addr = hw_address_ctrl_in66) ELSE + hip_ctrl_in67 WHEN (reg_addr = hw_address_ctrl_in67) ELSE + hip_ctrl_in68 WHEN (reg_addr = hw_address_ctrl_in68) ELSE + hip_ctrl_in69 WHEN (reg_addr = hw_address_ctrl_in69) ELSE + hip_ctrl_in70 WHEN (reg_addr = hw_address_ctrl_in70) ELSE + hip_ctrl_in71 WHEN (reg_addr = hw_address_ctrl_in71) ELSE + hip_ctrl_in72 WHEN (reg_addr = hw_address_ctrl_in72) ELSE + hip_ctrl_in73 WHEN (reg_addr = hw_address_ctrl_in73) ELSE + hip_ctrl_in74 WHEN (reg_addr = hw_address_ctrl_in74) ELSE + hip_ctrl_in75 WHEN (reg_addr = hw_address_ctrl_in75) ELSE + hip_ctrl_in76 WHEN (reg_addr = hw_address_ctrl_in76) ELSE + hip_ctrl_in77 WHEN (reg_addr = hw_address_ctrl_in77) ELSE + hip_ctrl_in78 WHEN (reg_addr = hw_address_ctrl_in78) ELSE + hip_ctrl_in79 WHEN (reg_addr = hw_address_ctrl_in79) ELSE + hip_ctrl_in80 WHEN (reg_addr = hw_address_ctrl_in80) ELSE + hip_ctrl_in81 WHEN (reg_addr = hw_address_ctrl_in81) ELSE + hip_ctrl_in82 WHEN (reg_addr = hw_address_ctrl_in82) ELSE + hip_ctrl_in83 WHEN (reg_addr = hw_address_ctrl_in83) ELSE + hip_ctrl_in84 WHEN (reg_addr = hw_address_ctrl_in84) ELSE + hip_ctrl_in85 WHEN (reg_addr = hw_address_ctrl_in85) ELSE + hip_ctrl_in86 WHEN (reg_addr = hw_address_ctrl_in86) ELSE + hip_ctrl_in87 WHEN (reg_addr = hw_address_ctrl_in87) ELSE + hip_ctrl_in88 WHEN (reg_addr = hw_address_ctrl_in88) ELSE + hip_ctrl_in89 WHEN (reg_addr = hw_address_ctrl_in89) ELSE + hip_ctrl_in90 WHEN (reg_addr = hw_address_ctrl_in90) ELSE + hip_ctrl_in91 WHEN (reg_addr = hw_address_ctrl_in91) ELSE + hip_ctrl_in92 WHEN (reg_addr = hw_address_ctrl_in92) ELSE + hip_ctrl_in93 WHEN (reg_addr = hw_address_ctrl_in93) ELSE + hip_ctrl_in94 WHEN (reg_addr = hw_address_ctrl_in94) ELSE + hip_ctrl_in95 WHEN (reg_addr = hw_address_ctrl_in95) ELSE + hip_ctrl_in96 WHEN (reg_addr = hw_address_ctrl_in96) ELSE + hip_ctrl_in97 WHEN (reg_addr = hw_address_ctrl_in97) ELSE + hip_ctrl_in98 WHEN (reg_addr = hw_address_ctrl_in98) ELSE + hip_ctrl_in99 WHEN (reg_addr = hw_address_ctrl_in99) ELSE + hip_ctrl_in100 WHEN (reg_addr = hw_address_ctrl_in100) ELSE + hip_ctrl_in101 WHEN (reg_addr = hw_address_ctrl_in101) ELSE + hip_ctrl_in102 WHEN (reg_addr = hw_address_ctrl_in102) ELSE + hip_ctrl_in103 WHEN (reg_addr = hw_address_ctrl_in103) ELSE + hip_ctrl_in104 WHEN (reg_addr = hw_address_ctrl_in104) ELSE + hip_ctrl_in105 WHEN (reg_addr = hw_address_ctrl_in105) ELSE + hip_ctrl_in106 WHEN (reg_addr = hw_address_ctrl_in106) ELSE + hip_ctrl_in107 WHEN (reg_addr = hw_address_ctrl_in107) ELSE + hip_ctrl_in108 WHEN (reg_addr = hw_address_ctrl_in108) ELSE + hip_ctrl_in109 WHEN (reg_addr = hw_address_ctrl_in109) ELSE + hip_ctrl_in110 WHEN (reg_addr = hw_address_ctrl_in110) ELSE + "0000000000000000"; + +END ARCHITECTURE trans; + + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + + +ENTITY cycloneiv_pciehip_dprio_reg IS + PORT ( + -- CSR input + + -- DPRIO register output + + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + ext_hip_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + targ_addr_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + out_hip_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_54 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_55 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_56 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_57 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_58 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_59 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_60 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_61 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_62 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_63 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_64 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_65 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_66 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_67 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_68 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_69 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_70 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_71 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_72 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_73 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_74 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_75 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_76 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_77 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_78 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_79 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_80 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_81 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_82 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_83 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_84 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_85 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_86 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_87 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_88 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_89 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_90 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_91 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_92 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_93 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_94 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_95 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_96 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_97 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_98 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_99 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_100 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_101 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_102 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_103 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_104 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_105 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_106 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_107 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_108 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_109 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_110 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); +END ENTITY cycloneiv_pciehip_dprio_reg; + +ARCHITECTURE trans OF cycloneiv_pciehip_dprio_reg IS + COMPONENT cycloneiv_pciehip_dprio_16bit IS + PORT ( + reset : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + target_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clk : IN STD_LOGIC; + sig_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + si : IN STD_LOGIC; + shift : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + sig_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL chain : STD_LOGIC_VECTOR(108 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL out_hip_ctrl_1_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_2_xhdl22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_3_xhdl33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_4_xhdl44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_5_xhdl55 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_6_xhdl66 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_7_xhdl77 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_8_xhdl88 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_9_xhdl99 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_10_xhdl1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_11_xhdl12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_12_xhdl14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_13_xhdl15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_14_xhdl16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_15_xhdl17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_16_xhdl18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_17_xhdl19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_18_xhdl20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_19_xhdl21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_20_xhdl23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_21_xhdl24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_22_xhdl25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_23_xhdl26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_24_xhdl27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_25_xhdl28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_26_xhdl29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_27_xhdl30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_28_xhdl31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_29_xhdl32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_30_xhdl34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_31_xhdl35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_32_xhdl36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_33_xhdl37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_34_xhdl38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_35_xhdl39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_36_xhdl40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_37_xhdl41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_38_xhdl42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_39_xhdl43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_40_xhdl45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_41_xhdl46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_42_xhdl47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_43_xhdl48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_44_xhdl49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_45_xhdl50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_46_xhdl51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_47_xhdl52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_48_xhdl53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_49_xhdl54 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_50_xhdl56 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_51_xhdl57 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_52_xhdl58 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_53_xhdl59 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_54_xhdl60 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_55_xhdl61 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_56_xhdl62 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_57_xhdl63 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_58_xhdl64 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_59_xhdl65 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_60_xhdl67 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_61_xhdl68 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_62_xhdl69 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_63_xhdl70 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_64_xhdl71 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_65_xhdl72 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_66_xhdl73 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_67_xhdl74 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_68_xhdl75 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_69_xhdl76 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_70_xhdl78 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_71_xhdl79 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_72_xhdl80 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_73_xhdl81 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_74_xhdl82 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_75_xhdl83 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_76_xhdl84 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_77_xhdl85 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_78_xhdl86 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_79_xhdl87 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_80_xhdl89 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_81_xhdl90 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_82_xhdl91 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_83_xhdl92 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_84_xhdl93 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_85_xhdl94 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_86_xhdl95 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_87_xhdl96 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_88_xhdl97 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_89_xhdl98 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_90_xhdl100 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_91_xhdl101 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_92_xhdl102 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_93_xhdl103 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_94_xhdl104 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_95_xhdl105 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_96_xhdl106 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_97_xhdl107 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_98_xhdl108 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_99_xhdl109 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_100_xhdl2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_101_xhdl3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_102_xhdl4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_103_xhdl5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_104_xhdl6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_105_xhdl7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_106_xhdl8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_107_xhdl9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_108_xhdl10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_109_xhdl11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_110_xhdl13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL so_xhdl110 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + out_hip_ctrl_1 <= out_hip_ctrl_1_xhdl0; + out_hip_ctrl_2 <= out_hip_ctrl_2_xhdl22; + out_hip_ctrl_3 <= out_hip_ctrl_3_xhdl33; + out_hip_ctrl_4 <= out_hip_ctrl_4_xhdl44; + out_hip_ctrl_5 <= out_hip_ctrl_5_xhdl55; + out_hip_ctrl_6 <= out_hip_ctrl_6_xhdl66; + out_hip_ctrl_7 <= out_hip_ctrl_7_xhdl77; + out_hip_ctrl_8 <= out_hip_ctrl_8_xhdl88; + out_hip_ctrl_9 <= out_hip_ctrl_9_xhdl99; + out_hip_ctrl_10 <= out_hip_ctrl_10_xhdl1; + out_hip_ctrl_11 <= out_hip_ctrl_11_xhdl12; + out_hip_ctrl_12 <= out_hip_ctrl_12_xhdl14; + out_hip_ctrl_13 <= out_hip_ctrl_13_xhdl15; + out_hip_ctrl_14 <= out_hip_ctrl_14_xhdl16; + out_hip_ctrl_15 <= out_hip_ctrl_15_xhdl17; + out_hip_ctrl_16 <= out_hip_ctrl_16_xhdl18; + out_hip_ctrl_17 <= out_hip_ctrl_17_xhdl19; + out_hip_ctrl_18 <= out_hip_ctrl_18_xhdl20; + out_hip_ctrl_19 <= out_hip_ctrl_19_xhdl21; + out_hip_ctrl_20 <= out_hip_ctrl_20_xhdl23; + out_hip_ctrl_21 <= out_hip_ctrl_21_xhdl24; + out_hip_ctrl_22 <= out_hip_ctrl_22_xhdl25; + out_hip_ctrl_23 <= out_hip_ctrl_23_xhdl26; + out_hip_ctrl_24 <= out_hip_ctrl_24_xhdl27; + out_hip_ctrl_25 <= out_hip_ctrl_25_xhdl28; + out_hip_ctrl_26 <= out_hip_ctrl_26_xhdl29; + out_hip_ctrl_27 <= out_hip_ctrl_27_xhdl30; + out_hip_ctrl_28 <= out_hip_ctrl_28_xhdl31; + out_hip_ctrl_29 <= out_hip_ctrl_29_xhdl32; + out_hip_ctrl_30 <= out_hip_ctrl_30_xhdl34; + out_hip_ctrl_31 <= out_hip_ctrl_31_xhdl35; + out_hip_ctrl_32 <= out_hip_ctrl_32_xhdl36; + out_hip_ctrl_33 <= out_hip_ctrl_33_xhdl37; + out_hip_ctrl_34 <= out_hip_ctrl_34_xhdl38; + out_hip_ctrl_35 <= out_hip_ctrl_35_xhdl39; + out_hip_ctrl_36 <= out_hip_ctrl_36_xhdl40; + out_hip_ctrl_37 <= out_hip_ctrl_37_xhdl41; + out_hip_ctrl_38 <= out_hip_ctrl_38_xhdl42; + out_hip_ctrl_39 <= out_hip_ctrl_39_xhdl43; + out_hip_ctrl_40 <= out_hip_ctrl_40_xhdl45; + out_hip_ctrl_41 <= out_hip_ctrl_41_xhdl46; + out_hip_ctrl_42 <= out_hip_ctrl_42_xhdl47; + out_hip_ctrl_43 <= out_hip_ctrl_43_xhdl48; + out_hip_ctrl_44 <= out_hip_ctrl_44_xhdl49; + out_hip_ctrl_45 <= out_hip_ctrl_45_xhdl50; + out_hip_ctrl_46 <= out_hip_ctrl_46_xhdl51; + out_hip_ctrl_47 <= out_hip_ctrl_47_xhdl52; + out_hip_ctrl_48 <= out_hip_ctrl_48_xhdl53; + out_hip_ctrl_49 <= out_hip_ctrl_49_xhdl54; + out_hip_ctrl_50 <= out_hip_ctrl_50_xhdl56; + out_hip_ctrl_51 <= out_hip_ctrl_51_xhdl57; + out_hip_ctrl_52 <= out_hip_ctrl_52_xhdl58; + out_hip_ctrl_53 <= out_hip_ctrl_53_xhdl59; + out_hip_ctrl_54 <= out_hip_ctrl_54_xhdl60; + out_hip_ctrl_55 <= out_hip_ctrl_55_xhdl61; + out_hip_ctrl_56 <= out_hip_ctrl_56_xhdl62; + out_hip_ctrl_57 <= out_hip_ctrl_57_xhdl63; + out_hip_ctrl_58 <= out_hip_ctrl_58_xhdl64; + out_hip_ctrl_59 <= out_hip_ctrl_59_xhdl65; + out_hip_ctrl_60 <= out_hip_ctrl_60_xhdl67; + out_hip_ctrl_61 <= out_hip_ctrl_61_xhdl68; + out_hip_ctrl_62 <= out_hip_ctrl_62_xhdl69; + out_hip_ctrl_63 <= out_hip_ctrl_63_xhdl70; + out_hip_ctrl_64 <= out_hip_ctrl_64_xhdl71; + out_hip_ctrl_65 <= out_hip_ctrl_65_xhdl72; + out_hip_ctrl_66 <= out_hip_ctrl_66_xhdl73; + out_hip_ctrl_67 <= out_hip_ctrl_67_xhdl74; + out_hip_ctrl_68 <= out_hip_ctrl_68_xhdl75; + out_hip_ctrl_69 <= out_hip_ctrl_69_xhdl76; + out_hip_ctrl_70 <= out_hip_ctrl_70_xhdl78; + out_hip_ctrl_71 <= out_hip_ctrl_71_xhdl79; + out_hip_ctrl_72 <= out_hip_ctrl_72_xhdl80; + out_hip_ctrl_73 <= out_hip_ctrl_73_xhdl81; + out_hip_ctrl_74 <= out_hip_ctrl_74_xhdl82; + out_hip_ctrl_75 <= out_hip_ctrl_75_xhdl83; + out_hip_ctrl_76 <= out_hip_ctrl_76_xhdl84; + out_hip_ctrl_77 <= out_hip_ctrl_77_xhdl85; + out_hip_ctrl_78 <= out_hip_ctrl_78_xhdl86; + out_hip_ctrl_79 <= out_hip_ctrl_79_xhdl87; + out_hip_ctrl_80 <= out_hip_ctrl_80_xhdl89; + out_hip_ctrl_81 <= out_hip_ctrl_81_xhdl90; + out_hip_ctrl_82 <= out_hip_ctrl_82_xhdl91; + out_hip_ctrl_83 <= out_hip_ctrl_83_xhdl92; + out_hip_ctrl_84 <= out_hip_ctrl_84_xhdl93; + out_hip_ctrl_85 <= out_hip_ctrl_85_xhdl94; + out_hip_ctrl_86 <= out_hip_ctrl_86_xhdl95; + out_hip_ctrl_87 <= out_hip_ctrl_87_xhdl96; + out_hip_ctrl_88 <= out_hip_ctrl_88_xhdl97; + out_hip_ctrl_89 <= out_hip_ctrl_89_xhdl98; + out_hip_ctrl_90 <= out_hip_ctrl_90_xhdl100; + out_hip_ctrl_91 <= out_hip_ctrl_91_xhdl101; + out_hip_ctrl_92 <= out_hip_ctrl_92_xhdl102; + out_hip_ctrl_93 <= out_hip_ctrl_93_xhdl103; + out_hip_ctrl_94 <= out_hip_ctrl_94_xhdl104; + out_hip_ctrl_95 <= out_hip_ctrl_95_xhdl105; + out_hip_ctrl_96 <= out_hip_ctrl_96_xhdl106; + out_hip_ctrl_97 <= out_hip_ctrl_97_xhdl107; + out_hip_ctrl_98 <= out_hip_ctrl_98_xhdl108; + out_hip_ctrl_99 <= out_hip_ctrl_99_xhdl109; + out_hip_ctrl_100 <= out_hip_ctrl_100_xhdl2; + out_hip_ctrl_101 <= out_hip_ctrl_101_xhdl3; + out_hip_ctrl_102 <= out_hip_ctrl_102_xhdl4; + out_hip_ctrl_103 <= out_hip_ctrl_103_xhdl5; + out_hip_ctrl_104 <= out_hip_ctrl_104_xhdl6; + out_hip_ctrl_105 <= out_hip_ctrl_105_xhdl7; + out_hip_ctrl_106 <= out_hip_ctrl_106_xhdl8; + out_hip_ctrl_107 <= out_hip_ctrl_107_xhdl9; + out_hip_ctrl_108 <= out_hip_ctrl_108_xhdl10; + out_hip_ctrl_109 <= out_hip_ctrl_109_xhdl11; + out_hip_ctrl_110 <= out_hip_ctrl_110_xhdl13; + so <= so_xhdl110; + + + + centrl_ctrl_1 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_1, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_1, + serial_mode => serial_mode, + si => si, + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_1_xhdl0, + so => chain(0) + ); + + + + centrl_ctrl_2 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_2, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_2, + serial_mode => serial_mode, + si => chain(0), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_2_xhdl22, + so => chain(1) + ); + + + + centrl_ctrl_3 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_3, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_3, + serial_mode => serial_mode, + si => chain(1), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_3_xhdl33, + so => chain(2) + ); + + + + centrl_ctrl_4 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_4, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_4, + serial_mode => serial_mode, + si => chain(2), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_4_xhdl44, + so => chain(3) + ); + + + + centrl_ctrl_5 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_5, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_5, + serial_mode => serial_mode, + si => chain(3), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_5_xhdl55, + so => chain(4) + ); + + + + centrl_ctrl_6 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_6, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_6, + serial_mode => serial_mode, + si => chain(4), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_6_xhdl66, + so => chain(5) + ); + + + + centrl_ctrl_7 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_7, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_7, + serial_mode => serial_mode, + si => chain(5), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_7_xhdl77, + so => chain(6) + ); + + + + centrl_ctrl_8 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_8, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_8, + serial_mode => serial_mode, + si => chain(6), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_8_xhdl88, + so => chain(7) + ); + + + + centrl_ctrl_9 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_9, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_9, + serial_mode => serial_mode, + si => chain(7), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_9_xhdl99, + so => chain(8) + ); + + + + centrl_ctrl_10 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_10, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_10, + serial_mode => serial_mode, + si => chain(8), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_10_xhdl1, + so => chain(9) + ); + + + + centrl_ctrl_11 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_11, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_11, + serial_mode => serial_mode, + si => chain(9), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_11_xhdl12, + so => chain(10) + ); + + + + centrl_ctrl_12 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_12, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_12, + serial_mode => serial_mode, + si => chain(10), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_12_xhdl14, + so => chain(11) + ); + + + + centrl_ctrl_13 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_13, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_13, + serial_mode => serial_mode, + si => chain(11), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_13_xhdl15, + so => chain(12) + ); + + + + centrl_ctrl_14 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_14, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_14, + serial_mode => serial_mode, + si => chain(12), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_14_xhdl16, + so => chain(13) + ); + + + + centrl_ctrl_15 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_15, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_15, + serial_mode => serial_mode, + si => chain(13), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_15_xhdl17, + so => chain(14) + ); + + + + centrl_ctrl_16 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_16, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_16, + serial_mode => serial_mode, + si => chain(14), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_16_xhdl18, + so => chain(15) + ); + + + + centrl_ctrl_17 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_17, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_17, + serial_mode => serial_mode, + si => chain(15), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_17_xhdl19, + so => chain(16) + ); + + + + centrl_ctrl_18 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_18, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_18, + serial_mode => serial_mode, + si => chain(16), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_18_xhdl20, + so => chain(17) + ); + + + + centrl_ctrl_19 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_19, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_19, + serial_mode => serial_mode, + si => chain(17), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_19_xhdl21, + so => chain(18) + ); + + + + centrl_ctrl_20 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_20, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_20, + serial_mode => serial_mode, + si => chain(18), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_20_xhdl23, + so => chain(19) + ); + + + + centrl_ctrl_21 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_21, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_21, + serial_mode => serial_mode, + si => chain(19), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_21_xhdl24, + so => chain(20) + ); + + + + centrl_ctrl_22 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_22, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_22, + serial_mode => serial_mode, + si => chain(20), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_22_xhdl25, + so => chain(21) + ); + + + + centrl_ctrl_23 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_23, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_23, + serial_mode => serial_mode, + si => chain(21), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_23_xhdl26, + so => chain(22) + ); + + + + centrl_ctrl_24 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_24, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_24, + serial_mode => serial_mode, + si => chain(22), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_24_xhdl27, + so => chain(23) + ); + + + + centrl_ctrl_25 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_25, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_25, + serial_mode => serial_mode, + si => chain(23), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_25_xhdl28, + so => chain(24) + ); + + + + centrl_ctrl_26 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_26, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_26, + serial_mode => serial_mode, + si => chain(24), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_26_xhdl29, + so => chain(25) + ); + + + + centrl_ctrl_27 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_27, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_27, + serial_mode => serial_mode, + si => chain(25), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_27_xhdl30, + so => chain(26) + ); + + + + centrl_ctrl_28 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_28, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_28, + serial_mode => serial_mode, + si => chain(26), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_28_xhdl31, + so => chain(27) + ); + + + + centrl_ctrl_29 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_29, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_29, + serial_mode => serial_mode, + si => chain(27), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_29_xhdl32, + so => chain(28) + ); + + + + centrl_ctrl_30 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_30, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_30, + serial_mode => serial_mode, + si => chain(28), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_30_xhdl34, + so => chain(29) + ); + + + + centrl_ctrl_31 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_31, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_31, + serial_mode => serial_mode, + si => chain(29), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_31_xhdl35, + so => chain(30) + ); + + + + centrl_ctrl_32 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_32, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_32, + serial_mode => serial_mode, + si => chain(30), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_32_xhdl36, + so => chain(31) + ); + + + + centrl_ctrl_33 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_33, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_33, + serial_mode => serial_mode, + si => chain(31), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_33_xhdl37, + so => chain(32) + ); + + + + centrl_ctrl_34 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_34, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_34, + serial_mode => serial_mode, + si => chain(32), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_34_xhdl38, + so => chain(33) + ); + + + + centrl_ctrl_35 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_35, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_35, + serial_mode => serial_mode, + si => chain(33), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_35_xhdl39, + so => chain(34) + ); + + + + centrl_ctrl_36 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_36, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_36, + serial_mode => serial_mode, + si => chain(34), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_36_xhdl40, + so => chain(35) + ); + + + + centrl_ctrl_37 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_37, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_37, + serial_mode => serial_mode, + si => chain(35), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_37_xhdl41, + so => chain(36) + ); + + + + centrl_ctrl_38 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_38, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_38, + serial_mode => serial_mode, + si => chain(36), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_38_xhdl42, + so => chain(37) + ); + + + + centrl_ctrl_39 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_39, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_39, + serial_mode => serial_mode, + si => chain(37), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_39_xhdl43, + so => chain(38) + ); + + + + centrl_ctrl_40 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_40, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_40, + serial_mode => serial_mode, + si => chain(38), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_40_xhdl45, + so => chain(39) + ); + + + + centrl_ctrl_41 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_41, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_41, + serial_mode => serial_mode, + si => chain(39), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_41_xhdl46, + so => chain(40) + ); + + + + centrl_ctrl_42 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_42, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_42, + serial_mode => serial_mode, + si => chain(40), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_42_xhdl47, + so => chain(41) + ); + + + + centrl_ctrl_43 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_43, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_43, + serial_mode => serial_mode, + si => chain(41), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_43_xhdl48, + so => chain(42) + ); + + + + centrl_ctrl_44 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_44, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_44, + serial_mode => serial_mode, + si => chain(42), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_44_xhdl49, + so => chain(43) + ); + + + + centrl_ctrl_45 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_45, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_45, + serial_mode => serial_mode, + si => chain(43), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_45_xhdl50, + so => chain(44) + ); + + + + centrl_ctrl_46 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_46, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_46, + serial_mode => serial_mode, + si => chain(44), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_46_xhdl51, + so => chain(45) + ); + + + + centrl_ctrl_47 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_47, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_47, + serial_mode => serial_mode, + si => chain(45), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_47_xhdl52, + so => chain(46) + ); + + + + centrl_ctrl_48 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_48, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_48, + serial_mode => serial_mode, + si => chain(46), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_48_xhdl53, + so => chain(47) + ); + + + + centrl_ctrl_49 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_49, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_49, + serial_mode => serial_mode, + si => chain(47), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_49_xhdl54, + so => chain(48) + ); + + + + centrl_ctrl_50 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_50, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_50, + serial_mode => serial_mode, + si => chain(48), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_50_xhdl56, + so => chain(49) + ); + + + + centrl_ctrl_51 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_51, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_51, + serial_mode => serial_mode, + si => chain(49), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_51_xhdl57, + so => chain(50) + ); + + + + centrl_ctrl_52 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_52, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_52, + serial_mode => serial_mode, + si => chain(50), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_52_xhdl58, + so => chain(51) + ); + + + + centrl_ctrl_53 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_53, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_53, + serial_mode => serial_mode, + si => chain(51), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_53_xhdl59, + so => chain(52) + ); + + + + centrl_ctrl_54 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_54, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_54, + serial_mode => serial_mode, + si => chain(52), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_54_xhdl60, + so => chain(53) + ); + + + + centrl_ctrl_55 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_55, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_55, + serial_mode => serial_mode, + si => chain(53), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_55_xhdl61, + so => chain(54) + ); + + + + centrl_ctrl_56 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_56, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_56, + serial_mode => serial_mode, + si => chain(54), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_56_xhdl62, + so => chain(55) + ); + + + + centrl_ctrl_57 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_57, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_57, + serial_mode => serial_mode, + si => chain(55), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_57_xhdl63, + so => chain(56) + ); + + + + centrl_ctrl_58 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_58, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_58, + serial_mode => serial_mode, + si => chain(56), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_58_xhdl64, + so => chain(57) + ); + + + + centrl_ctrl_59 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_59, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_59, + serial_mode => serial_mode, + si => chain(57), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_59_xhdl65, + so => chain(58) + ); + + + + centrl_ctrl_60 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_60, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_60, + serial_mode => serial_mode, + si => chain(58), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_60_xhdl67, + so => chain(59) + ); + + + + centrl_ctrl_61 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_61, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_61, + serial_mode => serial_mode, + si => chain(59), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_61_xhdl68, + so => chain(60) + ); + + + + centrl_ctrl_62 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_62, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_62, + serial_mode => serial_mode, + si => chain(60), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_62_xhdl69, + so => chain(61) + ); + + + + centrl_ctrl_63 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_63, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_63, + serial_mode => serial_mode, + si => chain(61), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_63_xhdl70, + so => chain(62) + ); + + + + centrl_ctrl_64 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_64, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_64, + serial_mode => serial_mode, + si => chain(62), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_64_xhdl71, + so => chain(63) + ); + + + + centrl_ctrl_65 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_65, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_65, + serial_mode => serial_mode, + si => chain(63), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_65_xhdl72, + so => chain(64) + ); + + + + centrl_ctrl_66 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_66, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_66, + serial_mode => serial_mode, + si => chain(64), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_66_xhdl73, + so => chain(65) + ); + + + + centrl_ctrl_67 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_67, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_67, + serial_mode => serial_mode, + si => chain(65), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_67_xhdl74, + so => chain(66) + ); + + + + centrl_ctrl_68 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_68, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_68, + serial_mode => serial_mode, + si => chain(66), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_68_xhdl75, + so => chain(67) + ); + + + + centrl_ctrl_69 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_69, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_69, + serial_mode => serial_mode, + si => chain(67), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_69_xhdl76, + so => chain(68) + ); + + + + centrl_ctrl_70 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_70, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_70, + serial_mode => serial_mode, + si => chain(68), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_70_xhdl78, + so => chain(69) + ); + + + + centrl_ctrl_71 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_71, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_71, + serial_mode => serial_mode, + si => chain(69), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_71_xhdl79, + so => chain(70) + ); + + + + centrl_ctrl_72 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_72, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_72, + serial_mode => serial_mode, + si => chain(70), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_72_xhdl80, + so => chain(71) + ); + + + + centrl_ctrl_73 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_73, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_73, + serial_mode => serial_mode, + si => chain(71), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_73_xhdl81, + so => chain(72) + ); + + + + centrl_ctrl_74 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_74, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_74, + serial_mode => serial_mode, + si => chain(72), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_74_xhdl82, + so => chain(73) + ); + + + + centrl_ctrl_75 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_75, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_75, + serial_mode => serial_mode, + si => chain(73), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_75_xhdl83, + so => chain(74) + ); + + + + centrl_ctrl_76 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_76, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_76, + serial_mode => serial_mode, + si => chain(74), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_76_xhdl84, + so => chain(75) + ); + + + + centrl_ctrl_77 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_77, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_77, + serial_mode => serial_mode, + si => chain(75), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_77_xhdl85, + so => chain(76) + ); + + + + centrl_ctrl_78 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_78, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_78, + serial_mode => serial_mode, + si => chain(76), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_78_xhdl86, + so => chain(77) + ); + + + + centrl_ctrl_79 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_79, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_79, + serial_mode => serial_mode, + si => chain(77), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_79_xhdl87, + so => chain(78) + ); + + + + centrl_ctrl_80 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_80, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_80, + serial_mode => serial_mode, + si => chain(78), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_80_xhdl89, + so => chain(79) + ); + + + + centrl_ctrl_81 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_81, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_81, + serial_mode => serial_mode, + si => chain(79), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_81_xhdl90, + so => chain(80) + ); + + + + centrl_ctrl_82 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_82, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_82, + serial_mode => serial_mode, + si => chain(80), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_82_xhdl91, + so => chain(81) + ); + + + + centrl_ctrl_83 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_83, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_83, + serial_mode => serial_mode, + si => chain(81), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_83_xhdl92, + so => chain(82) + ); + + + + centrl_ctrl_84 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_84, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_84, + serial_mode => serial_mode, + si => chain(82), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_84_xhdl93, + so => chain(83) + ); + + + + centrl_ctrl_85 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_85, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_85, + serial_mode => serial_mode, + si => chain(83), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_85_xhdl94, + so => chain(84) + ); + + + + centrl_ctrl_86 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_86, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_86, + serial_mode => serial_mode, + si => chain(84), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_86_xhdl95, + so => chain(85) + ); + + + + centrl_ctrl_87 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_87, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_87, + serial_mode => serial_mode, + si => chain(85), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_87_xhdl96, + so => chain(86) + ); + + + + centrl_ctrl_88 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_88, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_88, + serial_mode => serial_mode, + si => chain(86), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_88_xhdl97, + so => chain(87) + ); + + + + centrl_ctrl_89 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_89, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_89, + serial_mode => serial_mode, + si => chain(87), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_89_xhdl98, + so => chain(88) + ); + + + + centrl_ctrl_90 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_90, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_90, + serial_mode => serial_mode, + si => chain(88), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_90_xhdl100, + so => chain(89) + ); + + + + centrl_ctrl_91 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_91, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_91, + serial_mode => serial_mode, + si => chain(89), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_91_xhdl101, + so => chain(90) + ); + + + + centrl_ctrl_92 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_92, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_92, + serial_mode => serial_mode, + si => chain(90), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_92_xhdl102, + so => chain(91) + ); + + + + centrl_ctrl_93 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_93, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_93, + serial_mode => serial_mode, + si => chain(91), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_93_xhdl103, + so => chain(92) + ); + + + + centrl_ctrl_94 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_94, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_94, + serial_mode => serial_mode, + si => chain(92), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_94_xhdl104, + so => chain(93) + ); + + + + centrl_ctrl_95 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_95, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_95, + serial_mode => serial_mode, + si => chain(93), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_95_xhdl105, + so => chain(94) + ); + + + + centrl_ctrl_96 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_96, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_96, + serial_mode => serial_mode, + si => chain(94), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_96_xhdl106, + so => chain(95) + ); + + + + centrl_ctrl_97 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_97, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_97, + serial_mode => serial_mode, + si => chain(95), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_97_xhdl107, + so => chain(96) + ); + + + + centrl_ctrl_98 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_98, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_98, + serial_mode => serial_mode, + si => chain(96), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_98_xhdl108, + so => chain(97) + ); + + + + centrl_ctrl_99 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_99, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_99, + serial_mode => serial_mode, + si => chain(97), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_99_xhdl109, + so => chain(98) + ); + + + + centrl_ctrl_100 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_100, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_100, + serial_mode => serial_mode, + si => chain(98), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_100_xhdl2, + so => chain(99) + ); + + + + centrl_ctrl_101 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_101, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_101, + serial_mode => serial_mode, + si => chain(99), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_101_xhdl3, + so => chain(100) + ); + + + + centrl_ctrl_102 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_102, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_102, + serial_mode => serial_mode, + si => chain(100), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_102_xhdl4, + so => chain(101) + ); + + + + centrl_ctrl_103 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_103, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_103, + serial_mode => serial_mode, + si => chain(101), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_103_xhdl5, + so => chain(102) + ); + + + + centrl_ctrl_104 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_104, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_104, + serial_mode => serial_mode, + si => chain(102), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_104_xhdl6, + so => chain(103) + ); + + + + centrl_ctrl_105 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_105, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_105, + serial_mode => serial_mode, + si => chain(103), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_105_xhdl7, + so => chain(104) + ); + + + + centrl_ctrl_106 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_106, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_106, + serial_mode => serial_mode, + si => chain(104), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_106_xhdl8, + so => chain(105) + ); + + + + centrl_ctrl_107 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_107, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_107, + serial_mode => serial_mode, + si => chain(105), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_107_xhdl9, + so => chain(106) + ); + + + + centrl_ctrl_108 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_108, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_108, + serial_mode => serial_mode, + si => chain(106), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_108_xhdl10, + so => chain(107) + ); + + + + centrl_ctrl_109 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_109, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_109, + serial_mode => serial_mode, + si => chain(107), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_109_xhdl11, + so => chain(108) + ); + + + + centrl_ctrl_110 : cycloneiv_pciehip_dprio_16bit + PORT MAP ( + reset => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + target_addr => targ_addr_ctrl_110, + clk => mdc, + sig_in => mbus_in, + ext_in => ext_hip_ctrl_110, + serial_mode => serial_mode, + si => chain(108), + shift => ser_shift_load, + mdio_dis => mdio_dis, + sig_out => out_hip_ctrl_110_xhdl13, + so => so_xhdl110 + ); + +END ARCHITECTURE trans; + + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_unsigned.all; + +ENTITY cycloneiv_pciehip_dprio_reg_top IS + PORT ( + + mdio_rst : IN STD_LOGIC; -- DPRIO reset input + mdio_wr : IN STD_LOGIC; -- DPRIO register write enable + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- DPRIO register address from SM + mdc : IN STD_LOGIC; -- DPRIO clock + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- DPRIO data in from SM + serial_mode : IN STD_LOGIC; -- DPRIO serial mode enable + mdio_dis : IN STD_LOGIC; -- DPRIO disable signal (using CSR input) + ser_shift_load : IN STD_LOGIC; -- DPRIO serial shift or load control signal + si : IN STD_LOGIC; -- DPRIO serial input + csr_hip_in : IN STD_LOGIC_VECTOR(1759 DOWNTO 0); -- CSR inputs + hip_base_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- DPRIO HIP base address + + so : OUT STD_LOGIC; -- DPRIO serial out + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- DPRIO dataout + -- CRAM output + out_hip_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_54 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_55 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_56 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_57 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_58 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_59 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_60 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_61 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_62 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_63 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_64 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_65 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_66 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_67 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_68 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_69 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_70 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_71 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_72 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_73 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_74 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_75 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_76 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_77 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_78 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_79 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_80 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_81 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_82 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_83 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_84 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_85 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_86 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_87 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_88 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_89 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_90 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_91 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_92 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_93 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_94 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_95 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_96 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_97 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_98 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_99 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_100 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_101 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_102 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_103 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_104 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_105 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_106 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_107 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_108 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_109 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_110 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END ENTITY cycloneiv_pciehip_dprio_reg_top; + +ARCHITECTURE trans OF cycloneiv_pciehip_dprio_reg_top IS + COMPONENT cycloneiv_pciehip_dprio_reg IS + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + ext_hip_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + ext_hip_ctrl_110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + targ_addr_ctrl_110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_54 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_55 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_56 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_57 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_58 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_59 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_60 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_61 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_62 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_63 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_64 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_65 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_66 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_67 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_68 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_69 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_70 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_71 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_72 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_73 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_74 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_75 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_76 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_77 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_78 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_79 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_80 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_81 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_82 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_83 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_84 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_85 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_86 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_87 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_88 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_89 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_90 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_91 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_92 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_93 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_94 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_95 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_96 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_97 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_98 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_99 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_100 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_101 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_102 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_103 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_104 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_105 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_106 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_107 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_108 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_109 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_110 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + so : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_dprio_bus_out_mux IS + PORT ( + hip_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_in110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in6 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in7 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in8 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in9 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in12 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in13 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in14 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in15 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in16 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in17 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in19 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in20 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in21 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in23 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in24 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in25 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in26 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in27 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in28 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in29 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in30 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in31 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in32 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in33 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in34 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in35 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in36 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in37 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in38 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in39 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in40 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in41 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in42 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in43 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in44 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in45 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in46 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in47 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in48 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in49 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in50 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in51 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in52 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in53 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in54 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in55 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in56 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in57 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in58 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in59 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in60 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in61 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in62 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in63 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in64 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in65 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in66 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in67 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in68 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in69 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in70 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in71 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in72 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in73 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in74 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in75 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in76 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in77 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in78 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in79 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in80 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in81 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in82 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in83 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in84 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in85 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in86 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in87 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in88 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in89 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in90 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in91 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in92 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in93 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in94 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in95 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in96 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in97 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in98 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in99 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in100 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in101 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in102 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in103 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in104 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in105 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in106 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in107 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in108 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in109 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hw_address_ctrl_in110 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + hip_ctrl_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + + -- Wiring + SIGNAL targ_addr_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_54 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_55 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_56 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_57 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_58 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_59 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_60 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_61 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_62 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_63 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_64 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_65 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_66 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_67 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_68 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_69 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_70 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_71 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_72 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_73 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_74 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_75 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_76 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_77 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_78 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_79 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_80 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_81 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_82 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_83 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_84 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_85 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_86 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_87 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_88 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_89 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_90 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_91 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_92 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_93 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_94 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_95 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_96 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_97 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_98 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_99 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_100 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_101 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_102 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_103 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_104 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_105 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_106 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_107 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_108 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_109 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL targ_addr_ctrl_110 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL so_xhdl111 : STD_LOGIC; + SIGNAL mbus_out_xhdl0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_1_xhdl1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_2_xhdl23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_3_xhdl34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_4_xhdl45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_5_xhdl56 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_6_xhdl67 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_7_xhdl78 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_8_xhdl89 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_9_xhdl100 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_10_xhdl2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_11_xhdl13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_12_xhdl15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_13_xhdl16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_14_xhdl17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_15_xhdl18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_16_xhdl19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_17_xhdl20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_18_xhdl21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_19_xhdl22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_20_xhdl24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_21_xhdl25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_22_xhdl26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_23_xhdl27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_24_xhdl28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_25_xhdl29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_26_xhdl30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_27_xhdl31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_28_xhdl32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_29_xhdl33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_30_xhdl35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_31_xhdl36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_32_xhdl37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_33_xhdl38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_34_xhdl39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_35_xhdl40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_36_xhdl41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_37_xhdl42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_38_xhdl43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_39_xhdl44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_40_xhdl46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_41_xhdl47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_42_xhdl48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_43_xhdl49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_44_xhdl50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_45_xhdl51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_46_xhdl52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_47_xhdl53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_48_xhdl54 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_49_xhdl55 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_50_xhdl57 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_51_xhdl58 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_52_xhdl59 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_53_xhdl60 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_54_xhdl61 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_55_xhdl62 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_56_xhdl63 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_57_xhdl64 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_58_xhdl65 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_59_xhdl66 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_60_xhdl68 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_61_xhdl69 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_62_xhdl70 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_63_xhdl71 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_64_xhdl72 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_65_xhdl73 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_66_xhdl74 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_67_xhdl75 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_68_xhdl76 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_69_xhdl77 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_70_xhdl79 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_71_xhdl80 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_72_xhdl81 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_73_xhdl82 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_74_xhdl83 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_75_xhdl84 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_76_xhdl85 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_77_xhdl86 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_78_xhdl87 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_79_xhdl88 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_80_xhdl90 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_81_xhdl91 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_82_xhdl92 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_83_xhdl93 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_84_xhdl94 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_85_xhdl95 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_86_xhdl96 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_87_xhdl97 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_88_xhdl98 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_89_xhdl99 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_90_xhdl101 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_91_xhdl102 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_92_xhdl103 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_93_xhdl104 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_94_xhdl105 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_95_xhdl106 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_96_xhdl107 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_97_xhdl108 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_98_xhdl109 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_99_xhdl110 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_100_xhdl3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_101_xhdl4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_102_xhdl5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_103_xhdl6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_104_xhdl7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_105_xhdl8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_106_xhdl9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_107_xhdl10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_108_xhdl11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_109_xhdl12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_110_xhdl14 : STD_LOGIC_VECTOR(15 DOWNTO 0); +BEGIN + -- Drive referenced outputs + so <= so_xhdl111; + mbus_out <= mbus_out_xhdl0; + out_hip_ctrl_1 <= out_hip_ctrl_1_xhdl1; + out_hip_ctrl_2 <= out_hip_ctrl_2_xhdl23; + out_hip_ctrl_3 <= out_hip_ctrl_3_xhdl34; + out_hip_ctrl_4 <= out_hip_ctrl_4_xhdl45; + out_hip_ctrl_5 <= out_hip_ctrl_5_xhdl56; + out_hip_ctrl_6 <= out_hip_ctrl_6_xhdl67; + out_hip_ctrl_7 <= out_hip_ctrl_7_xhdl78; + out_hip_ctrl_8 <= out_hip_ctrl_8_xhdl89; + out_hip_ctrl_9 <= out_hip_ctrl_9_xhdl100; + out_hip_ctrl_10 <= out_hip_ctrl_10_xhdl2; + out_hip_ctrl_11 <= out_hip_ctrl_11_xhdl13; + out_hip_ctrl_12 <= out_hip_ctrl_12_xhdl15; + out_hip_ctrl_13 <= out_hip_ctrl_13_xhdl16; + out_hip_ctrl_14 <= out_hip_ctrl_14_xhdl17; + out_hip_ctrl_15 <= out_hip_ctrl_15_xhdl18; + out_hip_ctrl_16 <= out_hip_ctrl_16_xhdl19; + out_hip_ctrl_17 <= out_hip_ctrl_17_xhdl20; + out_hip_ctrl_18 <= out_hip_ctrl_18_xhdl21; + out_hip_ctrl_19 <= out_hip_ctrl_19_xhdl22; + out_hip_ctrl_20 <= out_hip_ctrl_20_xhdl24; + out_hip_ctrl_21 <= out_hip_ctrl_21_xhdl25; + out_hip_ctrl_22 <= out_hip_ctrl_22_xhdl26; + out_hip_ctrl_23 <= out_hip_ctrl_23_xhdl27; + out_hip_ctrl_24 <= out_hip_ctrl_24_xhdl28; + out_hip_ctrl_25 <= out_hip_ctrl_25_xhdl29; + out_hip_ctrl_26 <= out_hip_ctrl_26_xhdl30; + out_hip_ctrl_27 <= out_hip_ctrl_27_xhdl31; + out_hip_ctrl_28 <= out_hip_ctrl_28_xhdl32; + out_hip_ctrl_29 <= out_hip_ctrl_29_xhdl33; + out_hip_ctrl_30 <= out_hip_ctrl_30_xhdl35; + out_hip_ctrl_31 <= out_hip_ctrl_31_xhdl36; + out_hip_ctrl_32 <= out_hip_ctrl_32_xhdl37; + out_hip_ctrl_33 <= out_hip_ctrl_33_xhdl38; + out_hip_ctrl_34 <= out_hip_ctrl_34_xhdl39; + out_hip_ctrl_35 <= out_hip_ctrl_35_xhdl40; + out_hip_ctrl_36 <= out_hip_ctrl_36_xhdl41; + out_hip_ctrl_37 <= out_hip_ctrl_37_xhdl42; + out_hip_ctrl_38 <= out_hip_ctrl_38_xhdl43; + out_hip_ctrl_39 <= out_hip_ctrl_39_xhdl44; + out_hip_ctrl_40 <= out_hip_ctrl_40_xhdl46; + out_hip_ctrl_41 <= out_hip_ctrl_41_xhdl47; + out_hip_ctrl_42 <= out_hip_ctrl_42_xhdl48; + out_hip_ctrl_43 <= out_hip_ctrl_43_xhdl49; + out_hip_ctrl_44 <= out_hip_ctrl_44_xhdl50; + out_hip_ctrl_45 <= out_hip_ctrl_45_xhdl51; + out_hip_ctrl_46 <= out_hip_ctrl_46_xhdl52; + out_hip_ctrl_47 <= out_hip_ctrl_47_xhdl53; + out_hip_ctrl_48 <= out_hip_ctrl_48_xhdl54; + out_hip_ctrl_49 <= out_hip_ctrl_49_xhdl55; + out_hip_ctrl_50 <= out_hip_ctrl_50_xhdl57; + out_hip_ctrl_51 <= out_hip_ctrl_51_xhdl58; + out_hip_ctrl_52 <= out_hip_ctrl_52_xhdl59; + out_hip_ctrl_53 <= out_hip_ctrl_53_xhdl60; + out_hip_ctrl_54 <= out_hip_ctrl_54_xhdl61; + out_hip_ctrl_55 <= out_hip_ctrl_55_xhdl62; + out_hip_ctrl_56 <= out_hip_ctrl_56_xhdl63; + out_hip_ctrl_57 <= out_hip_ctrl_57_xhdl64; + out_hip_ctrl_58 <= out_hip_ctrl_58_xhdl65; + out_hip_ctrl_59 <= out_hip_ctrl_59_xhdl66; + out_hip_ctrl_60 <= out_hip_ctrl_60_xhdl68; + out_hip_ctrl_61 <= out_hip_ctrl_61_xhdl69; + out_hip_ctrl_62 <= out_hip_ctrl_62_xhdl70; + out_hip_ctrl_63 <= out_hip_ctrl_63_xhdl71; + out_hip_ctrl_64 <= out_hip_ctrl_64_xhdl72; + out_hip_ctrl_65 <= out_hip_ctrl_65_xhdl73; + out_hip_ctrl_66 <= out_hip_ctrl_66_xhdl74; + out_hip_ctrl_67 <= out_hip_ctrl_67_xhdl75; + out_hip_ctrl_68 <= out_hip_ctrl_68_xhdl76; + out_hip_ctrl_69 <= out_hip_ctrl_69_xhdl77; + out_hip_ctrl_70 <= out_hip_ctrl_70_xhdl79; + out_hip_ctrl_71 <= out_hip_ctrl_71_xhdl80; + out_hip_ctrl_72 <= out_hip_ctrl_72_xhdl81; + out_hip_ctrl_73 <= out_hip_ctrl_73_xhdl82; + out_hip_ctrl_74 <= out_hip_ctrl_74_xhdl83; + out_hip_ctrl_75 <= out_hip_ctrl_75_xhdl84; + out_hip_ctrl_76 <= out_hip_ctrl_76_xhdl85; + out_hip_ctrl_77 <= out_hip_ctrl_77_xhdl86; + out_hip_ctrl_78 <= out_hip_ctrl_78_xhdl87; + out_hip_ctrl_79 <= out_hip_ctrl_79_xhdl88; + out_hip_ctrl_80 <= out_hip_ctrl_80_xhdl90; + out_hip_ctrl_81 <= out_hip_ctrl_81_xhdl91; + out_hip_ctrl_82 <= out_hip_ctrl_82_xhdl92; + out_hip_ctrl_83 <= out_hip_ctrl_83_xhdl93; + out_hip_ctrl_84 <= out_hip_ctrl_84_xhdl94; + out_hip_ctrl_85 <= out_hip_ctrl_85_xhdl95; + out_hip_ctrl_86 <= out_hip_ctrl_86_xhdl96; + out_hip_ctrl_87 <= out_hip_ctrl_87_xhdl97; + out_hip_ctrl_88 <= out_hip_ctrl_88_xhdl98; + out_hip_ctrl_89 <= out_hip_ctrl_89_xhdl99; + out_hip_ctrl_90 <= out_hip_ctrl_90_xhdl101; + out_hip_ctrl_91 <= out_hip_ctrl_91_xhdl102; + out_hip_ctrl_92 <= out_hip_ctrl_92_xhdl103; + out_hip_ctrl_93 <= out_hip_ctrl_93_xhdl104; + out_hip_ctrl_94 <= out_hip_ctrl_94_xhdl105; + out_hip_ctrl_95 <= out_hip_ctrl_95_xhdl106; + out_hip_ctrl_96 <= out_hip_ctrl_96_xhdl107; + out_hip_ctrl_97 <= out_hip_ctrl_97_xhdl108; + out_hip_ctrl_98 <= out_hip_ctrl_98_xhdl109; + out_hip_ctrl_99 <= out_hip_ctrl_99_xhdl110; + out_hip_ctrl_100 <= out_hip_ctrl_100_xhdl3; + out_hip_ctrl_101 <= out_hip_ctrl_101_xhdl4; + out_hip_ctrl_102 <= out_hip_ctrl_102_xhdl5; + out_hip_ctrl_103 <= out_hip_ctrl_103_xhdl6; + out_hip_ctrl_104 <= out_hip_ctrl_104_xhdl7; + out_hip_ctrl_105 <= out_hip_ctrl_105_xhdl8; + out_hip_ctrl_106 <= out_hip_ctrl_106_xhdl9; + out_hip_ctrl_107 <= out_hip_ctrl_107_xhdl10; + out_hip_ctrl_108 <= out_hip_ctrl_108_xhdl11; + out_hip_ctrl_109 <= out_hip_ctrl_109_xhdl12; + out_hip_ctrl_110 <= out_hip_ctrl_110_xhdl14; + + -- Control register address assignment + targ_addr_ctrl_1 <= ("10000000" & hip_base_addr) + "0000000000000001"; + targ_addr_ctrl_2 <= ("10000000" & hip_base_addr) + "0000000000000010"; + targ_addr_ctrl_3 <= ("10000000" & hip_base_addr) + "0000000000000011"; + targ_addr_ctrl_4 <= ("10000000" & hip_base_addr) + "0000000000000100"; + targ_addr_ctrl_5 <= ("10000000" & hip_base_addr) + "0000000000000101"; + targ_addr_ctrl_6 <= ("10000000" & hip_base_addr) + "0000000000000110"; + targ_addr_ctrl_7 <= ("10000000" & hip_base_addr) + "0000000000000111"; + targ_addr_ctrl_8 <= ("10000000" & hip_base_addr) + "0000000000001000"; + targ_addr_ctrl_9 <= ("10000000" & hip_base_addr) + "0000000000001001"; + targ_addr_ctrl_10 <= ("10000000" & hip_base_addr) + "0000000000001010"; + targ_addr_ctrl_11 <= ("10000000" & hip_base_addr) + "0000000000001011"; + targ_addr_ctrl_12 <= ("10000000" & hip_base_addr) + "0000000000001100"; + targ_addr_ctrl_13 <= ("10000000" & hip_base_addr) + "0000000000001101"; + targ_addr_ctrl_14 <= ("10000000" & hip_base_addr) + "0000000000001110"; + targ_addr_ctrl_15 <= ("10000000" & hip_base_addr) + "0000000000001111"; + targ_addr_ctrl_16 <= ("10000000" & hip_base_addr) + "0000000000010000"; + targ_addr_ctrl_17 <= ("10000000" & hip_base_addr) + "0000000000010001"; + targ_addr_ctrl_18 <= ("10000000" & hip_base_addr) + "0000000000010010"; + targ_addr_ctrl_19 <= ("10000000" & hip_base_addr) + "0000000000010011"; + targ_addr_ctrl_20 <= ("10000000" & hip_base_addr) + "0000000000010100"; + targ_addr_ctrl_21 <= ("10000000" & hip_base_addr) + "0000000000010101"; + targ_addr_ctrl_22 <= ("10000000" & hip_base_addr) + "0000000000010110"; + targ_addr_ctrl_23 <= ("10000000" & hip_base_addr) + "0000000000010111"; + targ_addr_ctrl_24 <= ("10000000" & hip_base_addr) + "0000000000011000"; + targ_addr_ctrl_25 <= ("10000000" & hip_base_addr) + "0000000000011001"; + targ_addr_ctrl_26 <= ("10000000" & hip_base_addr) + "0000000000011010"; + targ_addr_ctrl_27 <= ("10000000" & hip_base_addr) + "0000000000011011"; + targ_addr_ctrl_28 <= ("10000000" & hip_base_addr) + "0000000000011100"; + targ_addr_ctrl_29 <= ("10000000" & hip_base_addr) + "0000000000011101"; + targ_addr_ctrl_30 <= ("10000000" & hip_base_addr) + "0000000000011110"; + targ_addr_ctrl_31 <= ("10000000" & hip_base_addr) + "0000000000011111"; + targ_addr_ctrl_32 <= ("10000000" & hip_base_addr) + "0000000000100000"; + targ_addr_ctrl_33 <= ("10000000" & hip_base_addr) + "0000000000100001"; + targ_addr_ctrl_34 <= ("10000000" & hip_base_addr) + "0000000000100010"; + targ_addr_ctrl_35 <= ("10000000" & hip_base_addr) + "0000000000100011"; + targ_addr_ctrl_36 <= ("10000000" & hip_base_addr) + "0000000000100100"; + targ_addr_ctrl_37 <= ("10000000" & hip_base_addr) + "0000000000100101"; + targ_addr_ctrl_38 <= ("10000000" & hip_base_addr) + "0000000000100110"; + targ_addr_ctrl_39 <= ("10000000" & hip_base_addr) + "0000000000100111"; + targ_addr_ctrl_40 <= ("10000000" & hip_base_addr) + "0000000000101000"; + targ_addr_ctrl_41 <= ("10000000" & hip_base_addr) + "0000000000101001"; + targ_addr_ctrl_42 <= ("10000000" & hip_base_addr) + "0000000000101010"; + targ_addr_ctrl_43 <= ("10000000" & hip_base_addr) + "0000000000101011"; + targ_addr_ctrl_44 <= ("10000000" & hip_base_addr) + "0000000000101100"; + targ_addr_ctrl_45 <= ("10000000" & hip_base_addr) + "0000000000101101"; + targ_addr_ctrl_46 <= ("10000000" & hip_base_addr) + "0000000000101110"; + targ_addr_ctrl_47 <= ("10000000" & hip_base_addr) + "0000000000101111"; + targ_addr_ctrl_48 <= ("10000000" & hip_base_addr) + "0000000000110000"; + targ_addr_ctrl_49 <= ("10000000" & hip_base_addr) + "0000000000110001"; + targ_addr_ctrl_50 <= ("10000000" & hip_base_addr) + "0000000000110010"; + targ_addr_ctrl_51 <= ("10000000" & hip_base_addr) + "0000000000110011"; + targ_addr_ctrl_52 <= ("10000000" & hip_base_addr) + "0000000000110100"; + targ_addr_ctrl_53 <= ("10000000" & hip_base_addr) + "0000000000110101"; + targ_addr_ctrl_54 <= ("10000000" & hip_base_addr) + "0000000000110110"; + targ_addr_ctrl_55 <= ("10000000" & hip_base_addr) + "0000000000110111"; + targ_addr_ctrl_56 <= ("10000000" & hip_base_addr) + "0000000000111000"; + targ_addr_ctrl_57 <= ("10000000" & hip_base_addr) + "0000000000111001"; + targ_addr_ctrl_58 <= ("10000000" & hip_base_addr) + "0000000000111010"; + targ_addr_ctrl_59 <= ("10000000" & hip_base_addr) + "0000000000111011"; + targ_addr_ctrl_60 <= ("10000000" & hip_base_addr) + "0000000000111100"; + targ_addr_ctrl_61 <= ("10000000" & hip_base_addr) + "0000000000111101"; + targ_addr_ctrl_62 <= ("10000000" & hip_base_addr) + "0000000000111110"; + targ_addr_ctrl_63 <= ("10000000" & hip_base_addr) + "0000000000111111"; + targ_addr_ctrl_64 <= ("10000000" & hip_base_addr) + "0000000001000000"; + targ_addr_ctrl_65 <= ("10000000" & hip_base_addr) + "0000000001000001"; + targ_addr_ctrl_66 <= ("10000000" & hip_base_addr) + "0000000001000010"; + targ_addr_ctrl_67 <= ("10000000" & hip_base_addr) + "0000000001000011"; + targ_addr_ctrl_68 <= ("10000000" & hip_base_addr) + "0000000001000100"; + targ_addr_ctrl_69 <= ("10000000" & hip_base_addr) + "0000000001000101"; + targ_addr_ctrl_70 <= ("10000000" & hip_base_addr) + "0000000001000110"; + targ_addr_ctrl_71 <= ("10000000" & hip_base_addr) + "0000000001000111"; + targ_addr_ctrl_72 <= ("10000000" & hip_base_addr) + "0000000001001000"; + targ_addr_ctrl_73 <= ("10000000" & hip_base_addr) + "0000000001001001"; + targ_addr_ctrl_74 <= ("10000000" & hip_base_addr) + "0000000001001010"; + targ_addr_ctrl_75 <= ("10000000" & hip_base_addr) + "0000000001001011"; + targ_addr_ctrl_76 <= ("10000000" & hip_base_addr) + "0000000001001100"; + targ_addr_ctrl_77 <= ("10000000" & hip_base_addr) + "0000000001001101"; + targ_addr_ctrl_78 <= ("10000000" & hip_base_addr) + "0000000001001110"; + targ_addr_ctrl_79 <= ("10000000" & hip_base_addr) + "0000000001001111"; + targ_addr_ctrl_80 <= ("10000000" & hip_base_addr) + "0000000001010000"; + targ_addr_ctrl_81 <= ("10000000" & hip_base_addr) + "0000000001010001"; + targ_addr_ctrl_82 <= ("10000000" & hip_base_addr) + "0000000001010010"; + targ_addr_ctrl_83 <= ("10000000" & hip_base_addr) + "0000000001010011"; + targ_addr_ctrl_84 <= ("10000000" & hip_base_addr) + "0000000001010100"; + targ_addr_ctrl_85 <= ("10000000" & hip_base_addr) + "0000000001010101"; + targ_addr_ctrl_86 <= ("10000000" & hip_base_addr) + "0000000001010110"; + targ_addr_ctrl_87 <= ("10000000" & hip_base_addr) + "0000000001010111"; + targ_addr_ctrl_88 <= ("10000000" & hip_base_addr) + "0000000001011000"; + targ_addr_ctrl_89 <= ("10000000" & hip_base_addr) + "0000000001011001"; + targ_addr_ctrl_90 <= ("10000000" & hip_base_addr) + "0000000001011010"; + targ_addr_ctrl_91 <= ("10000000" & hip_base_addr) + "0000000001011011"; + targ_addr_ctrl_92 <= ("10000000" & hip_base_addr) + "0000000001011100"; + targ_addr_ctrl_93 <= ("10000000" & hip_base_addr) + "0000000001011101"; + targ_addr_ctrl_94 <= ("10000000" & hip_base_addr) + "0000000001011110"; + targ_addr_ctrl_95 <= ("10000000" & hip_base_addr) + "0000000001011111"; + targ_addr_ctrl_96 <= ("10000000" & hip_base_addr) + "0000000001100000"; + targ_addr_ctrl_97 <= ("10000000" & hip_base_addr) + "0000000001100001"; + targ_addr_ctrl_98 <= ("10000000" & hip_base_addr) + "0000000001100010"; + targ_addr_ctrl_99 <= ("10000000" & hip_base_addr) + "0000000001100011"; + targ_addr_ctrl_100 <= ("10000000" & hip_base_addr) + "0000000001100100"; + targ_addr_ctrl_101 <= ("10000000" & hip_base_addr) + "0000000001100101"; + targ_addr_ctrl_102 <= ("10000000" & hip_base_addr) + "0000000001100110"; + targ_addr_ctrl_103 <= ("10000000" & hip_base_addr) + "0000000001100111"; + targ_addr_ctrl_104 <= ("10000000" & hip_base_addr) + "0000000001101000"; + targ_addr_ctrl_105 <= ("10000000" & hip_base_addr) + "0000000001101001"; + targ_addr_ctrl_106 <= ("10000000" & hip_base_addr) + "0000000001101010"; + targ_addr_ctrl_107 <= ("10000000" & hip_base_addr) + "0000000001101011"; + targ_addr_ctrl_108 <= ("10000000" & hip_base_addr) + "0000000001101100"; + targ_addr_ctrl_109 <= ("10000000" & hip_base_addr) + "0000000001101101"; + targ_addr_ctrl_110 <= ("10000000" & hip_base_addr) + "0000000001101110"; + + -- CRAM output assignment + + -- DPRIO registers + + + dprio_reg_1 : cycloneiv_pciehip_dprio_reg + PORT MAP ( + mdio_rst => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + mdc => mdc, + mbus_in => mbus_in, + serial_mode => serial_mode, + mdio_dis => mdio_dis, + ser_shift_load => ser_shift_load, + si => si, + -- CSR input + ext_hip_ctrl_1 => csr_hip_in(15 DOWNTO 0), + ext_hip_ctrl_2 => csr_hip_in(31 DOWNTO 16), + ext_hip_ctrl_3 => csr_hip_in(47 DOWNTO 32), + ext_hip_ctrl_4 => csr_hip_in(63 DOWNTO 48), + ext_hip_ctrl_5 => csr_hip_in(79 DOWNTO 64), + ext_hip_ctrl_6 => csr_hip_in(95 DOWNTO 80), + ext_hip_ctrl_7 => csr_hip_in(111 DOWNTO 96), + ext_hip_ctrl_8 => csr_hip_in(127 DOWNTO 112), + ext_hip_ctrl_9 => csr_hip_in(143 DOWNTO 128), + ext_hip_ctrl_10 => csr_hip_in(159 DOWNTO 144), + ext_hip_ctrl_11 => csr_hip_in(175 DOWNTO 160), + ext_hip_ctrl_12 => csr_hip_in(191 DOWNTO 176), + ext_hip_ctrl_13 => csr_hip_in(207 DOWNTO 192), + ext_hip_ctrl_14 => csr_hip_in(223 DOWNTO 208), + ext_hip_ctrl_15 => csr_hip_in(239 DOWNTO 224), + ext_hip_ctrl_16 => csr_hip_in(255 DOWNTO 240), + ext_hip_ctrl_17 => csr_hip_in(271 DOWNTO 256), + ext_hip_ctrl_18 => csr_hip_in(287 DOWNTO 272), + ext_hip_ctrl_19 => csr_hip_in(303 DOWNTO 288), + ext_hip_ctrl_20 => csr_hip_in(319 DOWNTO 304), + ext_hip_ctrl_21 => csr_hip_in(335 DOWNTO 320), + ext_hip_ctrl_22 => csr_hip_in(351 DOWNTO 336), + ext_hip_ctrl_23 => csr_hip_in(367 DOWNTO 352), + ext_hip_ctrl_24 => csr_hip_in(383 DOWNTO 368), + ext_hip_ctrl_25 => csr_hip_in(399 DOWNTO 384), + ext_hip_ctrl_26 => csr_hip_in(415 DOWNTO 400), + ext_hip_ctrl_27 => csr_hip_in(431 DOWNTO 416), + ext_hip_ctrl_28 => csr_hip_in(447 DOWNTO 432), + ext_hip_ctrl_29 => csr_hip_in(463 DOWNTO 448), + ext_hip_ctrl_30 => csr_hip_in(479 DOWNTO 464), + ext_hip_ctrl_31 => csr_hip_in(495 DOWNTO 480), + ext_hip_ctrl_32 => csr_hip_in(511 DOWNTO 496), + ext_hip_ctrl_33 => csr_hip_in(527 DOWNTO 512), + ext_hip_ctrl_34 => csr_hip_in(543 DOWNTO 528), + ext_hip_ctrl_35 => csr_hip_in(559 DOWNTO 544), + ext_hip_ctrl_36 => csr_hip_in(575 DOWNTO 560), + ext_hip_ctrl_37 => csr_hip_in(591 DOWNTO 576), + ext_hip_ctrl_38 => csr_hip_in(607 DOWNTO 592), + ext_hip_ctrl_39 => csr_hip_in(623 DOWNTO 608), + ext_hip_ctrl_40 => csr_hip_in(639 DOWNTO 624), + ext_hip_ctrl_41 => csr_hip_in(655 DOWNTO 640), + ext_hip_ctrl_42 => csr_hip_in(671 DOWNTO 656), + ext_hip_ctrl_43 => csr_hip_in(687 DOWNTO 672), + ext_hip_ctrl_44 => csr_hip_in(703 DOWNTO 688), + ext_hip_ctrl_45 => csr_hip_in(719 DOWNTO 704), + ext_hip_ctrl_46 => csr_hip_in(735 DOWNTO 720), + ext_hip_ctrl_47 => csr_hip_in(751 DOWNTO 736), + ext_hip_ctrl_48 => csr_hip_in(767 DOWNTO 752), + ext_hip_ctrl_49 => csr_hip_in(783 DOWNTO 768), + ext_hip_ctrl_50 => csr_hip_in(799 DOWNTO 784), + ext_hip_ctrl_51 => csr_hip_in(815 DOWNTO 800), + ext_hip_ctrl_52 => csr_hip_in(831 DOWNTO 816), + ext_hip_ctrl_53 => csr_hip_in(847 DOWNTO 832), + ext_hip_ctrl_54 => csr_hip_in(863 DOWNTO 848), + ext_hip_ctrl_55 => csr_hip_in(879 DOWNTO 864), + ext_hip_ctrl_56 => csr_hip_in(895 DOWNTO 880), + ext_hip_ctrl_57 => csr_hip_in(911 DOWNTO 896), + ext_hip_ctrl_58 => csr_hip_in(927 DOWNTO 912), + ext_hip_ctrl_59 => csr_hip_in(943 DOWNTO 928), + ext_hip_ctrl_60 => csr_hip_in(959 DOWNTO 944), + ext_hip_ctrl_61 => csr_hip_in(975 DOWNTO 960), + ext_hip_ctrl_62 => csr_hip_in(991 DOWNTO 976), + ext_hip_ctrl_63 => csr_hip_in(1007 DOWNTO 992), + ext_hip_ctrl_64 => csr_hip_in(1023 DOWNTO 1008), + ext_hip_ctrl_65 => csr_hip_in(1039 DOWNTO 1024), + ext_hip_ctrl_66 => csr_hip_in(1055 DOWNTO 1040), + ext_hip_ctrl_67 => csr_hip_in(1071 DOWNTO 1056), + ext_hip_ctrl_68 => csr_hip_in(1087 DOWNTO 1072), + ext_hip_ctrl_69 => csr_hip_in(1103 DOWNTO 1088), + ext_hip_ctrl_70 => csr_hip_in(1119 DOWNTO 1104), + ext_hip_ctrl_71 => csr_hip_in(1135 DOWNTO 1120), + ext_hip_ctrl_72 => csr_hip_in(1151 DOWNTO 1136), + ext_hip_ctrl_73 => csr_hip_in(1167 DOWNTO 1152), + ext_hip_ctrl_74 => csr_hip_in(1183 DOWNTO 1168), + ext_hip_ctrl_75 => csr_hip_in(1199 DOWNTO 1184), + ext_hip_ctrl_76 => csr_hip_in(1215 DOWNTO 1200), + ext_hip_ctrl_77 => csr_hip_in(1231 DOWNTO 1216), + ext_hip_ctrl_78 => csr_hip_in(1247 DOWNTO 1232), + ext_hip_ctrl_79 => csr_hip_in(1263 DOWNTO 1248), + ext_hip_ctrl_80 => csr_hip_in(1279 DOWNTO 1264), + ext_hip_ctrl_81 => csr_hip_in(1295 DOWNTO 1280), + ext_hip_ctrl_82 => csr_hip_in(1311 DOWNTO 1296), + ext_hip_ctrl_83 => csr_hip_in(1327 DOWNTO 1312), + ext_hip_ctrl_84 => csr_hip_in(1343 DOWNTO 1328), + ext_hip_ctrl_85 => csr_hip_in(1359 DOWNTO 1344), + ext_hip_ctrl_86 => csr_hip_in(1375 DOWNTO 1360), + ext_hip_ctrl_87 => csr_hip_in(1391 DOWNTO 1376), + ext_hip_ctrl_88 => csr_hip_in(1407 DOWNTO 1392), + ext_hip_ctrl_89 => csr_hip_in(1423 DOWNTO 1408), + ext_hip_ctrl_90 => csr_hip_in(1439 DOWNTO 1424), + ext_hip_ctrl_91 => csr_hip_in(1455 DOWNTO 1440), + ext_hip_ctrl_92 => csr_hip_in(1471 DOWNTO 1456), + ext_hip_ctrl_93 => csr_hip_in(1487 DOWNTO 1472), + ext_hip_ctrl_94 => csr_hip_in(1503 DOWNTO 1488), + ext_hip_ctrl_95 => csr_hip_in(1519 DOWNTO 1504), + ext_hip_ctrl_96 => csr_hip_in(1535 DOWNTO 1520), + ext_hip_ctrl_97 => csr_hip_in(1551 DOWNTO 1536), + ext_hip_ctrl_98 => csr_hip_in(1567 DOWNTO 1552), + ext_hip_ctrl_99 => csr_hip_in(1583 DOWNTO 1568), + ext_hip_ctrl_100 => csr_hip_in(1599 DOWNTO 1584), + ext_hip_ctrl_101 => csr_hip_in(1615 DOWNTO 1600), + ext_hip_ctrl_102 => csr_hip_in(1631 DOWNTO 1616), + ext_hip_ctrl_103 => csr_hip_in(1647 DOWNTO 1632), + ext_hip_ctrl_104 => csr_hip_in(1663 DOWNTO 1648), + ext_hip_ctrl_105 => csr_hip_in(1679 DOWNTO 1664), + ext_hip_ctrl_106 => csr_hip_in(1695 DOWNTO 1680), + ext_hip_ctrl_107 => csr_hip_in(1711 DOWNTO 1696), + ext_hip_ctrl_108 => csr_hip_in(1727 DOWNTO 1712), + ext_hip_ctrl_109 => csr_hip_in(1743 DOWNTO 1728), + ext_hip_ctrl_110 => csr_hip_in(1759 DOWNTO 1744), + targ_addr_ctrl_1 => targ_addr_ctrl_1, + targ_addr_ctrl_2 => targ_addr_ctrl_2, + targ_addr_ctrl_3 => targ_addr_ctrl_3, + targ_addr_ctrl_4 => targ_addr_ctrl_4, + targ_addr_ctrl_5 => targ_addr_ctrl_5, + targ_addr_ctrl_6 => targ_addr_ctrl_6, + targ_addr_ctrl_7 => targ_addr_ctrl_7, + targ_addr_ctrl_8 => targ_addr_ctrl_8, + targ_addr_ctrl_9 => targ_addr_ctrl_9, + targ_addr_ctrl_10 => targ_addr_ctrl_10, + targ_addr_ctrl_11 => targ_addr_ctrl_11, + targ_addr_ctrl_12 => targ_addr_ctrl_12, + targ_addr_ctrl_13 => targ_addr_ctrl_13, + targ_addr_ctrl_14 => targ_addr_ctrl_14, + targ_addr_ctrl_15 => targ_addr_ctrl_15, + targ_addr_ctrl_16 => targ_addr_ctrl_16, + targ_addr_ctrl_17 => targ_addr_ctrl_17, + targ_addr_ctrl_18 => targ_addr_ctrl_18, + targ_addr_ctrl_19 => targ_addr_ctrl_19, + targ_addr_ctrl_20 => targ_addr_ctrl_20, + targ_addr_ctrl_21 => targ_addr_ctrl_21, + targ_addr_ctrl_22 => targ_addr_ctrl_22, + targ_addr_ctrl_23 => targ_addr_ctrl_23, + targ_addr_ctrl_24 => targ_addr_ctrl_24, + targ_addr_ctrl_25 => targ_addr_ctrl_25, + targ_addr_ctrl_26 => targ_addr_ctrl_26, + targ_addr_ctrl_27 => targ_addr_ctrl_27, + targ_addr_ctrl_28 => targ_addr_ctrl_28, + targ_addr_ctrl_29 => targ_addr_ctrl_29, + targ_addr_ctrl_30 => targ_addr_ctrl_30, + targ_addr_ctrl_31 => targ_addr_ctrl_31, + targ_addr_ctrl_32 => targ_addr_ctrl_32, + targ_addr_ctrl_33 => targ_addr_ctrl_33, + targ_addr_ctrl_34 => targ_addr_ctrl_34, + targ_addr_ctrl_35 => targ_addr_ctrl_35, + targ_addr_ctrl_36 => targ_addr_ctrl_36, + targ_addr_ctrl_37 => targ_addr_ctrl_37, + targ_addr_ctrl_38 => targ_addr_ctrl_38, + targ_addr_ctrl_39 => targ_addr_ctrl_39, + targ_addr_ctrl_40 => targ_addr_ctrl_40, + targ_addr_ctrl_41 => targ_addr_ctrl_41, + targ_addr_ctrl_42 => targ_addr_ctrl_42, + targ_addr_ctrl_43 => targ_addr_ctrl_43, + targ_addr_ctrl_44 => targ_addr_ctrl_44, + targ_addr_ctrl_45 => targ_addr_ctrl_45, + targ_addr_ctrl_46 => targ_addr_ctrl_46, + targ_addr_ctrl_47 => targ_addr_ctrl_47, + targ_addr_ctrl_48 => targ_addr_ctrl_48, + targ_addr_ctrl_49 => targ_addr_ctrl_49, + targ_addr_ctrl_50 => targ_addr_ctrl_50, + targ_addr_ctrl_51 => targ_addr_ctrl_51, + targ_addr_ctrl_52 => targ_addr_ctrl_52, + targ_addr_ctrl_53 => targ_addr_ctrl_53, + targ_addr_ctrl_54 => targ_addr_ctrl_54, + targ_addr_ctrl_55 => targ_addr_ctrl_55, + targ_addr_ctrl_56 => targ_addr_ctrl_56, + targ_addr_ctrl_57 => targ_addr_ctrl_57, + targ_addr_ctrl_58 => targ_addr_ctrl_58, + targ_addr_ctrl_59 => targ_addr_ctrl_59, + targ_addr_ctrl_60 => targ_addr_ctrl_60, + targ_addr_ctrl_61 => targ_addr_ctrl_61, + targ_addr_ctrl_62 => targ_addr_ctrl_62, + targ_addr_ctrl_63 => targ_addr_ctrl_63, + targ_addr_ctrl_64 => targ_addr_ctrl_64, + targ_addr_ctrl_65 => targ_addr_ctrl_65, + targ_addr_ctrl_66 => targ_addr_ctrl_66, + targ_addr_ctrl_67 => targ_addr_ctrl_67, + targ_addr_ctrl_68 => targ_addr_ctrl_68, + targ_addr_ctrl_69 => targ_addr_ctrl_69, + targ_addr_ctrl_70 => targ_addr_ctrl_70, + targ_addr_ctrl_71 => targ_addr_ctrl_71, + targ_addr_ctrl_72 => targ_addr_ctrl_72, + targ_addr_ctrl_73 => targ_addr_ctrl_73, + targ_addr_ctrl_74 => targ_addr_ctrl_74, + targ_addr_ctrl_75 => targ_addr_ctrl_75, + targ_addr_ctrl_76 => targ_addr_ctrl_76, + targ_addr_ctrl_77 => targ_addr_ctrl_77, + targ_addr_ctrl_78 => targ_addr_ctrl_78, + targ_addr_ctrl_79 => targ_addr_ctrl_79, + targ_addr_ctrl_80 => targ_addr_ctrl_80, + targ_addr_ctrl_81 => targ_addr_ctrl_81, + targ_addr_ctrl_82 => targ_addr_ctrl_82, + targ_addr_ctrl_83 => targ_addr_ctrl_83, + targ_addr_ctrl_84 => targ_addr_ctrl_84, + targ_addr_ctrl_85 => targ_addr_ctrl_85, + targ_addr_ctrl_86 => targ_addr_ctrl_86, + targ_addr_ctrl_87 => targ_addr_ctrl_87, + targ_addr_ctrl_88 => targ_addr_ctrl_88, + targ_addr_ctrl_89 => targ_addr_ctrl_89, + targ_addr_ctrl_90 => targ_addr_ctrl_90, + targ_addr_ctrl_91 => targ_addr_ctrl_91, + targ_addr_ctrl_92 => targ_addr_ctrl_92, + targ_addr_ctrl_93 => targ_addr_ctrl_93, + targ_addr_ctrl_94 => targ_addr_ctrl_94, + targ_addr_ctrl_95 => targ_addr_ctrl_95, + targ_addr_ctrl_96 => targ_addr_ctrl_96, + targ_addr_ctrl_97 => targ_addr_ctrl_97, + targ_addr_ctrl_98 => targ_addr_ctrl_98, + targ_addr_ctrl_99 => targ_addr_ctrl_99, + targ_addr_ctrl_100 => targ_addr_ctrl_100, + targ_addr_ctrl_101 => targ_addr_ctrl_101, + targ_addr_ctrl_102 => targ_addr_ctrl_102, + targ_addr_ctrl_103 => targ_addr_ctrl_103, + targ_addr_ctrl_104 => targ_addr_ctrl_104, + targ_addr_ctrl_105 => targ_addr_ctrl_105, + targ_addr_ctrl_106 => targ_addr_ctrl_106, + targ_addr_ctrl_107 => targ_addr_ctrl_107, + targ_addr_ctrl_108 => targ_addr_ctrl_108, + targ_addr_ctrl_109 => targ_addr_ctrl_109, + targ_addr_ctrl_110 => targ_addr_ctrl_110, + -- DPRIO register output + out_hip_ctrl_1 => out_hip_ctrl_1_xhdl1, + out_hip_ctrl_2 => out_hip_ctrl_2_xhdl23, + out_hip_ctrl_3 => out_hip_ctrl_3_xhdl34, + out_hip_ctrl_4 => out_hip_ctrl_4_xhdl45, + out_hip_ctrl_5 => out_hip_ctrl_5_xhdl56, + out_hip_ctrl_6 => out_hip_ctrl_6_xhdl67, + out_hip_ctrl_7 => out_hip_ctrl_7_xhdl78, + out_hip_ctrl_8 => out_hip_ctrl_8_xhdl89, + out_hip_ctrl_9 => out_hip_ctrl_9_xhdl100, + out_hip_ctrl_10 => out_hip_ctrl_10_xhdl2, + out_hip_ctrl_11 => out_hip_ctrl_11_xhdl13, + out_hip_ctrl_12 => out_hip_ctrl_12_xhdl15, + out_hip_ctrl_13 => out_hip_ctrl_13_xhdl16, + out_hip_ctrl_14 => out_hip_ctrl_14_xhdl17, + out_hip_ctrl_15 => out_hip_ctrl_15_xhdl18, + out_hip_ctrl_16 => out_hip_ctrl_16_xhdl19, + out_hip_ctrl_17 => out_hip_ctrl_17_xhdl20, + out_hip_ctrl_18 => out_hip_ctrl_18_xhdl21, + out_hip_ctrl_19 => out_hip_ctrl_19_xhdl22, + out_hip_ctrl_20 => out_hip_ctrl_20_xhdl24, + out_hip_ctrl_21 => out_hip_ctrl_21_xhdl25, + out_hip_ctrl_22 => out_hip_ctrl_22_xhdl26, + out_hip_ctrl_23 => out_hip_ctrl_23_xhdl27, + out_hip_ctrl_24 => out_hip_ctrl_24_xhdl28, + out_hip_ctrl_25 => out_hip_ctrl_25_xhdl29, + out_hip_ctrl_26 => out_hip_ctrl_26_xhdl30, + out_hip_ctrl_27 => out_hip_ctrl_27_xhdl31, + out_hip_ctrl_28 => out_hip_ctrl_28_xhdl32, + out_hip_ctrl_29 => out_hip_ctrl_29_xhdl33, + out_hip_ctrl_30 => out_hip_ctrl_30_xhdl35, + out_hip_ctrl_31 => out_hip_ctrl_31_xhdl36, + out_hip_ctrl_32 => out_hip_ctrl_32_xhdl37, + out_hip_ctrl_33 => out_hip_ctrl_33_xhdl38, + out_hip_ctrl_34 => out_hip_ctrl_34_xhdl39, + out_hip_ctrl_35 => out_hip_ctrl_35_xhdl40, + out_hip_ctrl_36 => out_hip_ctrl_36_xhdl41, + out_hip_ctrl_37 => out_hip_ctrl_37_xhdl42, + out_hip_ctrl_38 => out_hip_ctrl_38_xhdl43, + out_hip_ctrl_39 => out_hip_ctrl_39_xhdl44, + out_hip_ctrl_40 => out_hip_ctrl_40_xhdl46, + out_hip_ctrl_41 => out_hip_ctrl_41_xhdl47, + out_hip_ctrl_42 => out_hip_ctrl_42_xhdl48, + out_hip_ctrl_43 => out_hip_ctrl_43_xhdl49, + out_hip_ctrl_44 => out_hip_ctrl_44_xhdl50, + out_hip_ctrl_45 => out_hip_ctrl_45_xhdl51, + out_hip_ctrl_46 => out_hip_ctrl_46_xhdl52, + out_hip_ctrl_47 => out_hip_ctrl_47_xhdl53, + out_hip_ctrl_48 => out_hip_ctrl_48_xhdl54, + out_hip_ctrl_49 => out_hip_ctrl_49_xhdl55, + out_hip_ctrl_50 => out_hip_ctrl_50_xhdl57, + out_hip_ctrl_51 => out_hip_ctrl_51_xhdl58, + out_hip_ctrl_52 => out_hip_ctrl_52_xhdl59, + out_hip_ctrl_53 => out_hip_ctrl_53_xhdl60, + out_hip_ctrl_54 => out_hip_ctrl_54_xhdl61, + out_hip_ctrl_55 => out_hip_ctrl_55_xhdl62, + out_hip_ctrl_56 => out_hip_ctrl_56_xhdl63, + out_hip_ctrl_57 => out_hip_ctrl_57_xhdl64, + out_hip_ctrl_58 => out_hip_ctrl_58_xhdl65, + out_hip_ctrl_59 => out_hip_ctrl_59_xhdl66, + out_hip_ctrl_60 => out_hip_ctrl_60_xhdl68, + out_hip_ctrl_61 => out_hip_ctrl_61_xhdl69, + out_hip_ctrl_62 => out_hip_ctrl_62_xhdl70, + out_hip_ctrl_63 => out_hip_ctrl_63_xhdl71, + out_hip_ctrl_64 => out_hip_ctrl_64_xhdl72, + out_hip_ctrl_65 => out_hip_ctrl_65_xhdl73, + out_hip_ctrl_66 => out_hip_ctrl_66_xhdl74, + out_hip_ctrl_67 => out_hip_ctrl_67_xhdl75, + out_hip_ctrl_68 => out_hip_ctrl_68_xhdl76, + out_hip_ctrl_69 => out_hip_ctrl_69_xhdl77, + out_hip_ctrl_70 => out_hip_ctrl_70_xhdl79, + out_hip_ctrl_71 => out_hip_ctrl_71_xhdl80, + out_hip_ctrl_72 => out_hip_ctrl_72_xhdl81, + out_hip_ctrl_73 => out_hip_ctrl_73_xhdl82, + out_hip_ctrl_74 => out_hip_ctrl_74_xhdl83, + out_hip_ctrl_75 => out_hip_ctrl_75_xhdl84, + out_hip_ctrl_76 => out_hip_ctrl_76_xhdl85, + out_hip_ctrl_77 => out_hip_ctrl_77_xhdl86, + out_hip_ctrl_78 => out_hip_ctrl_78_xhdl87, + out_hip_ctrl_79 => out_hip_ctrl_79_xhdl88, + out_hip_ctrl_80 => out_hip_ctrl_80_xhdl90, + out_hip_ctrl_81 => out_hip_ctrl_81_xhdl91, + out_hip_ctrl_82 => out_hip_ctrl_82_xhdl92, + out_hip_ctrl_83 => out_hip_ctrl_83_xhdl93, + out_hip_ctrl_84 => out_hip_ctrl_84_xhdl94, + out_hip_ctrl_85 => out_hip_ctrl_85_xhdl95, + out_hip_ctrl_86 => out_hip_ctrl_86_xhdl96, + out_hip_ctrl_87 => out_hip_ctrl_87_xhdl97, + out_hip_ctrl_88 => out_hip_ctrl_88_xhdl98, + out_hip_ctrl_89 => out_hip_ctrl_89_xhdl99, + out_hip_ctrl_90 => out_hip_ctrl_90_xhdl101, + out_hip_ctrl_91 => out_hip_ctrl_91_xhdl102, + out_hip_ctrl_92 => out_hip_ctrl_92_xhdl103, + out_hip_ctrl_93 => out_hip_ctrl_93_xhdl104, + out_hip_ctrl_94 => out_hip_ctrl_94_xhdl105, + out_hip_ctrl_95 => out_hip_ctrl_95_xhdl106, + out_hip_ctrl_96 => out_hip_ctrl_96_xhdl107, + out_hip_ctrl_97 => out_hip_ctrl_97_xhdl108, + out_hip_ctrl_98 => out_hip_ctrl_98_xhdl109, + out_hip_ctrl_99 => out_hip_ctrl_99_xhdl110, + out_hip_ctrl_100 => out_hip_ctrl_100_xhdl3, + out_hip_ctrl_101 => out_hip_ctrl_101_xhdl4, + out_hip_ctrl_102 => out_hip_ctrl_102_xhdl5, + out_hip_ctrl_103 => out_hip_ctrl_103_xhdl6, + out_hip_ctrl_104 => out_hip_ctrl_104_xhdl7, + out_hip_ctrl_105 => out_hip_ctrl_105_xhdl8, + out_hip_ctrl_106 => out_hip_ctrl_106_xhdl9, + out_hip_ctrl_107 => out_hip_ctrl_107_xhdl10, + out_hip_ctrl_108 => out_hip_ctrl_108_xhdl11, + out_hip_ctrl_109 => out_hip_ctrl_109_xhdl12, + out_hip_ctrl_110 => out_hip_ctrl_110_xhdl14, + so => so_xhdl111 + ); + + -- MBUS_OUT muxing for central channel + + + mbus_mux : cycloneiv_pciehip_dprio_bus_out_mux + PORT MAP ( + hip_ctrl_in1 => out_hip_ctrl_1_xhdl1, + hip_ctrl_in2 => out_hip_ctrl_2_xhdl23, + hip_ctrl_in3 => out_hip_ctrl_3_xhdl34, + hip_ctrl_in4 => out_hip_ctrl_4_xhdl45, + hip_ctrl_in5 => out_hip_ctrl_5_xhdl56, + hip_ctrl_in6 => out_hip_ctrl_6_xhdl67, + hip_ctrl_in7 => out_hip_ctrl_7_xhdl78, + hip_ctrl_in8 => out_hip_ctrl_8_xhdl89, + hip_ctrl_in9 => out_hip_ctrl_9_xhdl100, + hip_ctrl_in10 => out_hip_ctrl_10_xhdl2, + hip_ctrl_in11 => out_hip_ctrl_11_xhdl13, + hip_ctrl_in12 => out_hip_ctrl_12_xhdl15, + hip_ctrl_in13 => out_hip_ctrl_13_xhdl16, + hip_ctrl_in14 => out_hip_ctrl_14_xhdl17, + hip_ctrl_in15 => out_hip_ctrl_15_xhdl18, + hip_ctrl_in16 => out_hip_ctrl_16_xhdl19, + hip_ctrl_in17 => out_hip_ctrl_17_xhdl20, + hip_ctrl_in18 => out_hip_ctrl_18_xhdl21, + hip_ctrl_in19 => out_hip_ctrl_19_xhdl22, + hip_ctrl_in20 => out_hip_ctrl_20_xhdl24, + hip_ctrl_in21 => out_hip_ctrl_21_xhdl25, + hip_ctrl_in22 => out_hip_ctrl_22_xhdl26, + hip_ctrl_in23 => out_hip_ctrl_23_xhdl27, + hip_ctrl_in24 => out_hip_ctrl_24_xhdl28, + hip_ctrl_in25 => out_hip_ctrl_25_xhdl29, + hip_ctrl_in26 => out_hip_ctrl_26_xhdl30, + hip_ctrl_in27 => out_hip_ctrl_27_xhdl31, + hip_ctrl_in28 => out_hip_ctrl_28_xhdl32, + hip_ctrl_in29 => out_hip_ctrl_29_xhdl33, + hip_ctrl_in30 => out_hip_ctrl_30_xhdl35, + hip_ctrl_in31 => out_hip_ctrl_31_xhdl36, + hip_ctrl_in32 => out_hip_ctrl_32_xhdl37, + hip_ctrl_in33 => out_hip_ctrl_33_xhdl38, + hip_ctrl_in34 => out_hip_ctrl_34_xhdl39, + hip_ctrl_in35 => out_hip_ctrl_35_xhdl40, + hip_ctrl_in36 => out_hip_ctrl_36_xhdl41, + hip_ctrl_in37 => out_hip_ctrl_37_xhdl42, + hip_ctrl_in38 => out_hip_ctrl_38_xhdl43, + hip_ctrl_in39 => out_hip_ctrl_39_xhdl44, + hip_ctrl_in40 => out_hip_ctrl_40_xhdl46, + hip_ctrl_in41 => out_hip_ctrl_41_xhdl47, + hip_ctrl_in42 => out_hip_ctrl_42_xhdl48, + hip_ctrl_in43 => out_hip_ctrl_43_xhdl49, + hip_ctrl_in44 => out_hip_ctrl_44_xhdl50, + hip_ctrl_in45 => out_hip_ctrl_45_xhdl51, + hip_ctrl_in46 => out_hip_ctrl_46_xhdl52, + hip_ctrl_in47 => out_hip_ctrl_47_xhdl53, + hip_ctrl_in48 => out_hip_ctrl_48_xhdl54, + hip_ctrl_in49 => out_hip_ctrl_49_xhdl55, + hip_ctrl_in50 => out_hip_ctrl_50_xhdl57, + hip_ctrl_in51 => out_hip_ctrl_51_xhdl58, + hip_ctrl_in52 => out_hip_ctrl_52_xhdl59, + hip_ctrl_in53 => out_hip_ctrl_53_xhdl60, + hip_ctrl_in54 => out_hip_ctrl_54_xhdl61, + hip_ctrl_in55 => out_hip_ctrl_55_xhdl62, + hip_ctrl_in56 => out_hip_ctrl_56_xhdl63, + hip_ctrl_in57 => out_hip_ctrl_57_xhdl64, + hip_ctrl_in58 => out_hip_ctrl_58_xhdl65, + hip_ctrl_in59 => out_hip_ctrl_59_xhdl66, + hip_ctrl_in60 => out_hip_ctrl_60_xhdl68, + hip_ctrl_in61 => out_hip_ctrl_61_xhdl69, + hip_ctrl_in62 => out_hip_ctrl_62_xhdl70, + hip_ctrl_in63 => out_hip_ctrl_63_xhdl71, + hip_ctrl_in64 => out_hip_ctrl_64_xhdl72, + hip_ctrl_in65 => out_hip_ctrl_65_xhdl73, + hip_ctrl_in66 => out_hip_ctrl_66_xhdl74, + hip_ctrl_in67 => out_hip_ctrl_67_xhdl75, + hip_ctrl_in68 => out_hip_ctrl_68_xhdl76, + hip_ctrl_in69 => out_hip_ctrl_69_xhdl77, + hip_ctrl_in70 => out_hip_ctrl_70_xhdl79, + hip_ctrl_in71 => out_hip_ctrl_71_xhdl80, + hip_ctrl_in72 => out_hip_ctrl_72_xhdl81, + hip_ctrl_in73 => out_hip_ctrl_73_xhdl82, + hip_ctrl_in74 => out_hip_ctrl_74_xhdl83, + hip_ctrl_in75 => out_hip_ctrl_75_xhdl84, + hip_ctrl_in76 => out_hip_ctrl_76_xhdl85, + hip_ctrl_in77 => out_hip_ctrl_77_xhdl86, + hip_ctrl_in78 => out_hip_ctrl_78_xhdl87, + hip_ctrl_in79 => out_hip_ctrl_79_xhdl88, + hip_ctrl_in80 => out_hip_ctrl_80_xhdl90, + hip_ctrl_in81 => out_hip_ctrl_81_xhdl91, + hip_ctrl_in82 => out_hip_ctrl_82_xhdl92, + hip_ctrl_in83 => out_hip_ctrl_83_xhdl93, + hip_ctrl_in84 => out_hip_ctrl_84_xhdl94, + hip_ctrl_in85 => out_hip_ctrl_85_xhdl95, + hip_ctrl_in86 => out_hip_ctrl_86_xhdl96, + hip_ctrl_in87 => out_hip_ctrl_87_xhdl97, + hip_ctrl_in88 => out_hip_ctrl_88_xhdl98, + hip_ctrl_in89 => out_hip_ctrl_89_xhdl99, + hip_ctrl_in90 => out_hip_ctrl_90_xhdl101, + hip_ctrl_in91 => out_hip_ctrl_91_xhdl102, + hip_ctrl_in92 => out_hip_ctrl_92_xhdl103, + hip_ctrl_in93 => out_hip_ctrl_93_xhdl104, + hip_ctrl_in94 => out_hip_ctrl_94_xhdl105, + hip_ctrl_in95 => out_hip_ctrl_95_xhdl106, + hip_ctrl_in96 => out_hip_ctrl_96_xhdl107, + hip_ctrl_in97 => out_hip_ctrl_97_xhdl108, + hip_ctrl_in98 => out_hip_ctrl_98_xhdl109, + hip_ctrl_in99 => out_hip_ctrl_99_xhdl110, + hip_ctrl_in100 => out_hip_ctrl_100_xhdl3, + hip_ctrl_in101 => out_hip_ctrl_101_xhdl4, + hip_ctrl_in102 => out_hip_ctrl_102_xhdl5, + hip_ctrl_in103 => out_hip_ctrl_103_xhdl6, + hip_ctrl_in104 => out_hip_ctrl_104_xhdl7, + hip_ctrl_in105 => out_hip_ctrl_105_xhdl8, + hip_ctrl_in106 => out_hip_ctrl_106_xhdl9, + hip_ctrl_in107 => out_hip_ctrl_107_xhdl10, + hip_ctrl_in108 => out_hip_ctrl_108_xhdl11, + hip_ctrl_in109 => out_hip_ctrl_109_xhdl12, + hip_ctrl_in110 => out_hip_ctrl_110_xhdl14, + hw_address_ctrl_in1 => targ_addr_ctrl_1, + hw_address_ctrl_in2 => targ_addr_ctrl_2, + hw_address_ctrl_in3 => targ_addr_ctrl_3, + hw_address_ctrl_in4 => targ_addr_ctrl_4, + hw_address_ctrl_in5 => targ_addr_ctrl_5, + hw_address_ctrl_in6 => targ_addr_ctrl_6, + hw_address_ctrl_in7 => targ_addr_ctrl_7, + hw_address_ctrl_in8 => targ_addr_ctrl_8, + hw_address_ctrl_in9 => targ_addr_ctrl_9, + hw_address_ctrl_in10 => targ_addr_ctrl_10, + hw_address_ctrl_in11 => targ_addr_ctrl_11, + hw_address_ctrl_in12 => targ_addr_ctrl_12, + hw_address_ctrl_in13 => targ_addr_ctrl_13, + hw_address_ctrl_in14 => targ_addr_ctrl_14, + hw_address_ctrl_in15 => targ_addr_ctrl_15, + hw_address_ctrl_in16 => targ_addr_ctrl_16, + hw_address_ctrl_in17 => targ_addr_ctrl_17, + hw_address_ctrl_in18 => targ_addr_ctrl_18, + hw_address_ctrl_in19 => targ_addr_ctrl_19, + hw_address_ctrl_in20 => targ_addr_ctrl_20, + hw_address_ctrl_in21 => targ_addr_ctrl_21, + hw_address_ctrl_in22 => targ_addr_ctrl_22, + hw_address_ctrl_in23 => targ_addr_ctrl_23, + hw_address_ctrl_in24 => targ_addr_ctrl_24, + hw_address_ctrl_in25 => targ_addr_ctrl_25, + hw_address_ctrl_in26 => targ_addr_ctrl_26, + hw_address_ctrl_in27 => targ_addr_ctrl_27, + hw_address_ctrl_in28 => targ_addr_ctrl_28, + hw_address_ctrl_in29 => targ_addr_ctrl_29, + hw_address_ctrl_in30 => targ_addr_ctrl_30, + hw_address_ctrl_in31 => targ_addr_ctrl_31, + hw_address_ctrl_in32 => targ_addr_ctrl_32, + hw_address_ctrl_in33 => targ_addr_ctrl_33, + hw_address_ctrl_in34 => targ_addr_ctrl_34, + hw_address_ctrl_in35 => targ_addr_ctrl_35, + hw_address_ctrl_in36 => targ_addr_ctrl_36, + hw_address_ctrl_in37 => targ_addr_ctrl_37, + hw_address_ctrl_in38 => targ_addr_ctrl_38, + hw_address_ctrl_in39 => targ_addr_ctrl_39, + hw_address_ctrl_in40 => targ_addr_ctrl_40, + hw_address_ctrl_in41 => targ_addr_ctrl_41, + hw_address_ctrl_in42 => targ_addr_ctrl_42, + hw_address_ctrl_in43 => targ_addr_ctrl_43, + hw_address_ctrl_in44 => targ_addr_ctrl_44, + hw_address_ctrl_in45 => targ_addr_ctrl_45, + hw_address_ctrl_in46 => targ_addr_ctrl_46, + hw_address_ctrl_in47 => targ_addr_ctrl_47, + hw_address_ctrl_in48 => targ_addr_ctrl_48, + hw_address_ctrl_in49 => targ_addr_ctrl_49, + hw_address_ctrl_in50 => targ_addr_ctrl_50, + hw_address_ctrl_in51 => targ_addr_ctrl_51, + hw_address_ctrl_in52 => targ_addr_ctrl_52, + hw_address_ctrl_in53 => targ_addr_ctrl_53, + hw_address_ctrl_in54 => targ_addr_ctrl_54, + hw_address_ctrl_in55 => targ_addr_ctrl_55, + hw_address_ctrl_in56 => targ_addr_ctrl_56, + hw_address_ctrl_in57 => targ_addr_ctrl_57, + hw_address_ctrl_in58 => targ_addr_ctrl_58, + hw_address_ctrl_in59 => targ_addr_ctrl_59, + hw_address_ctrl_in60 => targ_addr_ctrl_60, + hw_address_ctrl_in61 => targ_addr_ctrl_61, + hw_address_ctrl_in62 => targ_addr_ctrl_62, + hw_address_ctrl_in63 => targ_addr_ctrl_63, + hw_address_ctrl_in64 => targ_addr_ctrl_64, + hw_address_ctrl_in65 => targ_addr_ctrl_65, + hw_address_ctrl_in66 => targ_addr_ctrl_66, + hw_address_ctrl_in67 => targ_addr_ctrl_67, + hw_address_ctrl_in68 => targ_addr_ctrl_68, + hw_address_ctrl_in69 => targ_addr_ctrl_69, + hw_address_ctrl_in70 => targ_addr_ctrl_70, + hw_address_ctrl_in71 => targ_addr_ctrl_71, + hw_address_ctrl_in72 => targ_addr_ctrl_72, + hw_address_ctrl_in73 => targ_addr_ctrl_73, + hw_address_ctrl_in74 => targ_addr_ctrl_74, + hw_address_ctrl_in75 => targ_addr_ctrl_75, + hw_address_ctrl_in76 => targ_addr_ctrl_76, + hw_address_ctrl_in77 => targ_addr_ctrl_77, + hw_address_ctrl_in78 => targ_addr_ctrl_78, + hw_address_ctrl_in79 => targ_addr_ctrl_79, + hw_address_ctrl_in80 => targ_addr_ctrl_80, + hw_address_ctrl_in81 => targ_addr_ctrl_81, + hw_address_ctrl_in82 => targ_addr_ctrl_82, + hw_address_ctrl_in83 => targ_addr_ctrl_83, + hw_address_ctrl_in84 => targ_addr_ctrl_84, + hw_address_ctrl_in85 => targ_addr_ctrl_85, + hw_address_ctrl_in86 => targ_addr_ctrl_86, + hw_address_ctrl_in87 => targ_addr_ctrl_87, + hw_address_ctrl_in88 => targ_addr_ctrl_88, + hw_address_ctrl_in89 => targ_addr_ctrl_89, + hw_address_ctrl_in90 => targ_addr_ctrl_90, + hw_address_ctrl_in91 => targ_addr_ctrl_91, + hw_address_ctrl_in92 => targ_addr_ctrl_92, + hw_address_ctrl_in93 => targ_addr_ctrl_93, + hw_address_ctrl_in94 => targ_addr_ctrl_94, + hw_address_ctrl_in95 => targ_addr_ctrl_95, + hw_address_ctrl_in96 => targ_addr_ctrl_96, + hw_address_ctrl_in97 => targ_addr_ctrl_97, + hw_address_ctrl_in98 => targ_addr_ctrl_98, + hw_address_ctrl_in99 => targ_addr_ctrl_99, + hw_address_ctrl_in100 => targ_addr_ctrl_100, + hw_address_ctrl_in101 => targ_addr_ctrl_101, + hw_address_ctrl_in102 => targ_addr_ctrl_102, + hw_address_ctrl_in103 => targ_addr_ctrl_103, + hw_address_ctrl_in104 => targ_addr_ctrl_104, + hw_address_ctrl_in105 => targ_addr_ctrl_105, + hw_address_ctrl_in106 => targ_addr_ctrl_106, + hw_address_ctrl_in107 => targ_addr_ctrl_107, + hw_address_ctrl_in108 => targ_addr_ctrl_108, + hw_address_ctrl_in109 => targ_addr_ctrl_109, + hw_address_ctrl_in110 => targ_addr_ctrl_110, + reg_addr => reg_addr, + hip_ctrl_out => mbus_out_xhdl0 + ); + +END ARCHITECTURE trans; + + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + +--====Revision Log================ +--Rev: 1.5 Wed Mar 19 13:08:01 PDT 2008 + +ENTITY cycloneiv_pciehip_hip_dprio_top IS + PORT ( + + -- MDIO inputs/outpus + mdc : IN STD_LOGIC; -- MDIO Interface clock + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- 5 bit device address + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- 5 bit port address + mdio_in : IN STD_LOGIC; -- Single bit data-in for MDIO Interface + mdio_dis : IN STD_LOGIC; -- MDIO disable input (using CSR) + -- 1'b1=output CRAM + -- 1'b0=output MDIO control register + mdio_rst : IN STD_LOGIC; -- MDIO reset from Quad reset + + serial_mode : IN STD_LOGIC; -- Serial programming mode enable + ser_shift_load : IN STD_LOGIC; -- Serial programming mode shift/load control + ser_si : IN STD_LOGIC; -- Serial programming mode data in + csr_hip_in : IN STD_LOGIC_VECTOR(1759 DOWNTO 0); -- CSR inputs + hip_base_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- DPRIO HIP base address + + ser_so : OUT STD_LOGIC; -- Serial programming mode data out + mdio_out : OUT STD_LOGIC; -- Single bit data-out for MDIO Interface + data_enable_n : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- MDIO current state for digital testbus + + -- CRAM output + out_hip_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_54 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_55 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_56 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_57 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_58 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_59 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_60 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_61 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_62 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_63 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_64 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_65 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_66 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_67 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_68 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_69 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_70 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_71 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_72 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_73 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_74 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_75 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_76 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_77 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_78 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_79 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_80 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_81 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_82 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_83 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_84 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_85 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_86 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_87 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_88 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_89 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_90 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_91 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_92 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_93 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_94 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_95 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_96 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_97 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_98 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_99 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_100 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_101 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_102 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_103 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_104 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_105 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_106 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_107 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_108 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_109 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_110 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END ENTITY cycloneiv_pciehip_hip_dprio_top; + +ARCHITECTURE trans OF cycloneiv_pciehip_hip_dprio_top IS + COMPONENT cycloneiv_pciehip_dprio_sm IS + GENERIC ( + + IDLE : INTEGER := 0; + PREAMBLE : INTEGER := 1; + CONTROL : INTEGER := 2; + TURN_ARND_0 : INTEGER := 3; + TURN_ARND_1 : INTEGER := 4; + ADDR_DATA : INTEGER := 5; + ADDR_OP : INTEGER := 0; + WR_OP : INTEGER := 1; + RD_INC_OP : INTEGER := 2; + RD_OP : INTEGER := 3 + ); + PORT ( + mdc : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + reset : IN STD_LOGIC; + opcode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + valid_addr : IN STD_LOGIC; + cnt_eq_0 : IN STD_LOGIC; + shift_in : OUT STD_LOGIC; + shift_out : OUT STD_LOGIC; + latch_ctl : OUT STD_LOGIC; + incr_addr : OUT STD_LOGIC; + mdio_wr : OUT STD_LOGIC; + mdio_rd : OUT STD_LOGIC; + shift_addr : OUT STD_LOGIC; + ld_data : OUT STD_LOGIC; + ld_cnt : OUT STD_LOGIC; + cnt_val : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + valid_addr_lt : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_dprio_ctl_data IS + PORT ( + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + shift_in : IN STD_LOGIC; + shift_out : IN STD_LOGIC; + ld_data : IN STD_LOGIC; + latch_ctl : IN STD_LOGIC; + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + valid_addr_lt : IN STD_LOGIC; + mbus_out : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdio_out : OUT STD_LOGIC; + data_enable_n : OUT STD_LOGIC; + mbus_in : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + opcode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + valid_addr : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_dprio_cnt IS + PORT ( + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC; + ld_cnt : IN STD_LOGIC; + cnt_val : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + cnt_eq_0 : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_dprio_reg_top IS + PORT ( + mdio_rst : IN STD_LOGIC; + mdio_wr : IN STD_LOGIC; + reg_addr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + mdc : IN STD_LOGIC; + mbus_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + serial_mode : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + si : IN STD_LOGIC; + csr_hip_in : IN STD_LOGIC_VECTOR(1759 DOWNTO 0); + hip_base_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + so : OUT STD_LOGIC; + mbus_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_54 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_55 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_56 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_57 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_58 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_59 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_60 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_61 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_62 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_63 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_64 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_65 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_66 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_67 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_68 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_69 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_70 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_71 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_72 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_73 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_74 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_75 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_76 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_77 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_78 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_79 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_80 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_81 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_82 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_83 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_84 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_85 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_86 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_87 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_88 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_89 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_90 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_91 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_92 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_93 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_94 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_95 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_96 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_97 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_98 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_99 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_100 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_101 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_102 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_103 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_104 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_105 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_106 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_107 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_108 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_109 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_110 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_dprio_addr IS + PORT ( + mdc : IN STD_LOGIC; + reset : IN STD_LOGIC; + mdio_in : IN STD_LOGIC; + shift_addr : IN STD_LOGIC; + incr_addr : IN STD_LOGIC; + reg_addr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + + -- Wiring section + SIGNAL mdio_rd : STD_LOGIC; -- MDIO read from SM + SIGNAL mbus_out : STD_LOGIC_VECTOR(15 DOWNTO 0); -- Data out to mdio_ctrl + SIGNAL shift_addr : STD_LOGIC; + SIGNAL incr_addr : STD_LOGIC; + SIGNAL ld_cnt : STD_LOGIC; + SIGNAL cnt_val : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL cnt_eq_0 : STD_LOGIC; + SIGNAL opcode : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL valid_addr : STD_LOGIC; + SIGNAL shift_in : STD_LOGIC; + SIGNAL shift_out : STD_LOGIC; + SIGNAL ld_data : STD_LOGIC; + SIGNAL latch_ctl : STD_LOGIC; + SIGNAL valid_addr_lt : STD_LOGIC; + -- Single bit data-out for MDIO Interface + SIGNAL mdio_wr : STD_LOGIC; -- MDIO write from SM + SIGNAL reg_addr : STD_LOGIC_VECTOR(15 DOWNTO 0); -- Register address from mdio_addr module + SIGNAL mbus_in : STD_LOGIC_VECTOR(15 DOWNTO 0); -- data to channel and central MDIO registers + + -- Declare intermediate signals for referenced outputs + SIGNAL ser_so_xhdl113 : STD_LOGIC; + SIGNAL mdio_out_xhdl2 : STD_LOGIC; + SIGNAL data_enable_n_xhdl1 : STD_LOGIC; + SIGNAL curr_state_xhdl0 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL out_hip_ctrl_1_xhdl3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_2_xhdl25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_3_xhdl36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_4_xhdl47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_5_xhdl58 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_6_xhdl69 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_7_xhdl80 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_8_xhdl91 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_9_xhdl102 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_10_xhdl4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_11_xhdl15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_12_xhdl17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_13_xhdl18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_14_xhdl19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_15_xhdl20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_16_xhdl21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_17_xhdl22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_18_xhdl23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_19_xhdl24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_20_xhdl26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_21_xhdl27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_22_xhdl28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_23_xhdl29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_24_xhdl30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_25_xhdl31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_26_xhdl32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_27_xhdl33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_28_xhdl34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_29_xhdl35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_30_xhdl37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_31_xhdl38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_32_xhdl39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_33_xhdl40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_34_xhdl41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_35_xhdl42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_36_xhdl43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_37_xhdl44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_38_xhdl45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_39_xhdl46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_40_xhdl48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_41_xhdl49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_42_xhdl50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_43_xhdl51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_44_xhdl52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_45_xhdl53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_46_xhdl54 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_47_xhdl55 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_48_xhdl56 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_49_xhdl57 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_50_xhdl59 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_51_xhdl60 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_52_xhdl61 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_53_xhdl62 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_54_xhdl63 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_55_xhdl64 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_56_xhdl65 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_57_xhdl66 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_58_xhdl67 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_59_xhdl68 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_60_xhdl70 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_61_xhdl71 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_62_xhdl72 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_63_xhdl73 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_64_xhdl74 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_65_xhdl75 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_66_xhdl76 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_67_xhdl77 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_68_xhdl78 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_69_xhdl79 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_70_xhdl81 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_71_xhdl82 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_72_xhdl83 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_73_xhdl84 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_74_xhdl85 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_75_xhdl86 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_76_xhdl87 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_77_xhdl88 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_78_xhdl89 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_79_xhdl90 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_80_xhdl92 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_81_xhdl93 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_82_xhdl94 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_83_xhdl95 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_84_xhdl96 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_85_xhdl97 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_86_xhdl98 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_87_xhdl99 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_88_xhdl100 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_89_xhdl101 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_90_xhdl103 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_91_xhdl104 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_92_xhdl105 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_93_xhdl106 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_94_xhdl107 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_95_xhdl108 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_96_xhdl109 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_97_xhdl110 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_98_xhdl111 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_99_xhdl112 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_100_xhdl5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_101_xhdl6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_102_xhdl7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_103_xhdl8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_104_xhdl9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_105_xhdl10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_106_xhdl11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_107_xhdl12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_108_xhdl13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_109_xhdl14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_110_xhdl16 : STD_LOGIC_VECTOR(15 DOWNTO 0); +BEGIN + -- Drive referenced outputs + ser_so <= ser_so_xhdl113; + mdio_out <= mdio_out_xhdl2; + data_enable_n <= data_enable_n_xhdl1; + curr_state <= curr_state_xhdl0; + out_hip_ctrl_1 <= out_hip_ctrl_1_xhdl3; + out_hip_ctrl_2 <= out_hip_ctrl_2_xhdl25; + out_hip_ctrl_3 <= out_hip_ctrl_3_xhdl36; + out_hip_ctrl_4 <= out_hip_ctrl_4_xhdl47; + out_hip_ctrl_5 <= out_hip_ctrl_5_xhdl58; + out_hip_ctrl_6 <= out_hip_ctrl_6_xhdl69; + out_hip_ctrl_7 <= out_hip_ctrl_7_xhdl80; + out_hip_ctrl_8 <= out_hip_ctrl_8_xhdl91; + out_hip_ctrl_9 <= out_hip_ctrl_9_xhdl102; + out_hip_ctrl_10 <= out_hip_ctrl_10_xhdl4; + out_hip_ctrl_11 <= out_hip_ctrl_11_xhdl15; + out_hip_ctrl_12 <= out_hip_ctrl_12_xhdl17; + out_hip_ctrl_13 <= out_hip_ctrl_13_xhdl18; + out_hip_ctrl_14 <= out_hip_ctrl_14_xhdl19; + out_hip_ctrl_15 <= out_hip_ctrl_15_xhdl20; + out_hip_ctrl_16 <= out_hip_ctrl_16_xhdl21; + out_hip_ctrl_17 <= out_hip_ctrl_17_xhdl22; + out_hip_ctrl_18 <= out_hip_ctrl_18_xhdl23; + out_hip_ctrl_19 <= out_hip_ctrl_19_xhdl24; + out_hip_ctrl_20 <= out_hip_ctrl_20_xhdl26; + out_hip_ctrl_21 <= out_hip_ctrl_21_xhdl27; + out_hip_ctrl_22 <= out_hip_ctrl_22_xhdl28; + out_hip_ctrl_23 <= out_hip_ctrl_23_xhdl29; + out_hip_ctrl_24 <= out_hip_ctrl_24_xhdl30; + out_hip_ctrl_25 <= out_hip_ctrl_25_xhdl31; + out_hip_ctrl_26 <= out_hip_ctrl_26_xhdl32; + out_hip_ctrl_27 <= out_hip_ctrl_27_xhdl33; + out_hip_ctrl_28 <= out_hip_ctrl_28_xhdl34; + out_hip_ctrl_29 <= out_hip_ctrl_29_xhdl35; + out_hip_ctrl_30 <= out_hip_ctrl_30_xhdl37; + out_hip_ctrl_31 <= out_hip_ctrl_31_xhdl38; + out_hip_ctrl_32 <= out_hip_ctrl_32_xhdl39; + out_hip_ctrl_33 <= out_hip_ctrl_33_xhdl40; + out_hip_ctrl_34 <= out_hip_ctrl_34_xhdl41; + out_hip_ctrl_35 <= out_hip_ctrl_35_xhdl42; + out_hip_ctrl_36 <= out_hip_ctrl_36_xhdl43; + out_hip_ctrl_37 <= out_hip_ctrl_37_xhdl44; + out_hip_ctrl_38 <= out_hip_ctrl_38_xhdl45; + out_hip_ctrl_39 <= out_hip_ctrl_39_xhdl46; + out_hip_ctrl_40 <= out_hip_ctrl_40_xhdl48; + out_hip_ctrl_41 <= out_hip_ctrl_41_xhdl49; + out_hip_ctrl_42 <= out_hip_ctrl_42_xhdl50; + out_hip_ctrl_43 <= out_hip_ctrl_43_xhdl51; + out_hip_ctrl_44 <= out_hip_ctrl_44_xhdl52; + out_hip_ctrl_45 <= out_hip_ctrl_45_xhdl53; + out_hip_ctrl_46 <= out_hip_ctrl_46_xhdl54; + out_hip_ctrl_47 <= out_hip_ctrl_47_xhdl55; + out_hip_ctrl_48 <= out_hip_ctrl_48_xhdl56; + out_hip_ctrl_49 <= out_hip_ctrl_49_xhdl57; + out_hip_ctrl_50 <= out_hip_ctrl_50_xhdl59; + out_hip_ctrl_51 <= out_hip_ctrl_51_xhdl60; + out_hip_ctrl_52 <= out_hip_ctrl_52_xhdl61; + out_hip_ctrl_53 <= out_hip_ctrl_53_xhdl62; + out_hip_ctrl_54 <= out_hip_ctrl_54_xhdl63; + out_hip_ctrl_55 <= out_hip_ctrl_55_xhdl64; + out_hip_ctrl_56 <= out_hip_ctrl_56_xhdl65; + out_hip_ctrl_57 <= out_hip_ctrl_57_xhdl66; + out_hip_ctrl_58 <= out_hip_ctrl_58_xhdl67; + out_hip_ctrl_59 <= out_hip_ctrl_59_xhdl68; + out_hip_ctrl_60 <= out_hip_ctrl_60_xhdl70; + out_hip_ctrl_61 <= out_hip_ctrl_61_xhdl71; + out_hip_ctrl_62 <= out_hip_ctrl_62_xhdl72; + out_hip_ctrl_63 <= out_hip_ctrl_63_xhdl73; + out_hip_ctrl_64 <= out_hip_ctrl_64_xhdl74; + out_hip_ctrl_65 <= out_hip_ctrl_65_xhdl75; + out_hip_ctrl_66 <= out_hip_ctrl_66_xhdl76; + out_hip_ctrl_67 <= out_hip_ctrl_67_xhdl77; + out_hip_ctrl_68 <= out_hip_ctrl_68_xhdl78; + out_hip_ctrl_69 <= out_hip_ctrl_69_xhdl79; + out_hip_ctrl_70 <= out_hip_ctrl_70_xhdl81; + out_hip_ctrl_71 <= out_hip_ctrl_71_xhdl82; + out_hip_ctrl_72 <= out_hip_ctrl_72_xhdl83; + out_hip_ctrl_73 <= out_hip_ctrl_73_xhdl84; + out_hip_ctrl_74 <= out_hip_ctrl_74_xhdl85; + out_hip_ctrl_75 <= out_hip_ctrl_75_xhdl86; + out_hip_ctrl_76 <= out_hip_ctrl_76_xhdl87; + out_hip_ctrl_77 <= out_hip_ctrl_77_xhdl88; + out_hip_ctrl_78 <= out_hip_ctrl_78_xhdl89; + out_hip_ctrl_79 <= out_hip_ctrl_79_xhdl90; + out_hip_ctrl_80 <= out_hip_ctrl_80_xhdl92; + out_hip_ctrl_81 <= out_hip_ctrl_81_xhdl93; + out_hip_ctrl_82 <= out_hip_ctrl_82_xhdl94; + out_hip_ctrl_83 <= out_hip_ctrl_83_xhdl95; + out_hip_ctrl_84 <= out_hip_ctrl_84_xhdl96; + out_hip_ctrl_85 <= out_hip_ctrl_85_xhdl97; + out_hip_ctrl_86 <= out_hip_ctrl_86_xhdl98; + out_hip_ctrl_87 <= out_hip_ctrl_87_xhdl99; + out_hip_ctrl_88 <= out_hip_ctrl_88_xhdl100; + out_hip_ctrl_89 <= out_hip_ctrl_89_xhdl101; + out_hip_ctrl_90 <= out_hip_ctrl_90_xhdl103; + out_hip_ctrl_91 <= out_hip_ctrl_91_xhdl104; + out_hip_ctrl_92 <= out_hip_ctrl_92_xhdl105; + out_hip_ctrl_93 <= out_hip_ctrl_93_xhdl106; + out_hip_ctrl_94 <= out_hip_ctrl_94_xhdl107; + out_hip_ctrl_95 <= out_hip_ctrl_95_xhdl108; + out_hip_ctrl_96 <= out_hip_ctrl_96_xhdl109; + out_hip_ctrl_97 <= out_hip_ctrl_97_xhdl110; + out_hip_ctrl_98 <= out_hip_ctrl_98_xhdl111; + out_hip_ctrl_99 <= out_hip_ctrl_99_xhdl112; + out_hip_ctrl_100 <= out_hip_ctrl_100_xhdl5; + out_hip_ctrl_101 <= out_hip_ctrl_101_xhdl6; + out_hip_ctrl_102 <= out_hip_ctrl_102_xhdl7; + out_hip_ctrl_103 <= out_hip_ctrl_103_xhdl8; + out_hip_ctrl_104 <= out_hip_ctrl_104_xhdl9; + out_hip_ctrl_105 <= out_hip_ctrl_105_xhdl10; + out_hip_ctrl_106 <= out_hip_ctrl_106_xhdl11; + out_hip_ctrl_107 <= out_hip_ctrl_107_xhdl12; + out_hip_ctrl_108 <= out_hip_ctrl_108_xhdl13; + out_hip_ctrl_109 <= out_hip_ctrl_109_xhdl14; + out_hip_ctrl_110 <= out_hip_ctrl_110_xhdl16; + + -- Central MDIO registers + + + dprio_reg_1 : cycloneiv_pciehip_dprio_reg_top + PORT MAP ( + mdio_rst => mdio_rst, + mdio_wr => mdio_wr, + reg_addr => reg_addr, + mdc => mdc, + mbus_in => mbus_in, + serial_mode => serial_mode, + mdio_dis => mdio_dis, + ser_shift_load => ser_shift_load, + si => ser_si, + csr_hip_in => csr_hip_in, + hip_base_addr => hip_base_addr, + so => ser_so_xhdl113, + mbus_out => mbus_out, + -- DPRIO register output + out_hip_ctrl_1 => out_hip_ctrl_1_xhdl3, + out_hip_ctrl_2 => out_hip_ctrl_2_xhdl25, + out_hip_ctrl_3 => out_hip_ctrl_3_xhdl36, + out_hip_ctrl_4 => out_hip_ctrl_4_xhdl47, + out_hip_ctrl_5 => out_hip_ctrl_5_xhdl58, + out_hip_ctrl_6 => out_hip_ctrl_6_xhdl69, + out_hip_ctrl_7 => out_hip_ctrl_7_xhdl80, + out_hip_ctrl_8 => out_hip_ctrl_8_xhdl91, + out_hip_ctrl_9 => out_hip_ctrl_9_xhdl102, + out_hip_ctrl_10 => out_hip_ctrl_10_xhdl4, + out_hip_ctrl_11 => out_hip_ctrl_11_xhdl15, + out_hip_ctrl_12 => out_hip_ctrl_12_xhdl17, + out_hip_ctrl_13 => out_hip_ctrl_13_xhdl18, + out_hip_ctrl_14 => out_hip_ctrl_14_xhdl19, + out_hip_ctrl_15 => out_hip_ctrl_15_xhdl20, + out_hip_ctrl_16 => out_hip_ctrl_16_xhdl21, + out_hip_ctrl_17 => out_hip_ctrl_17_xhdl22, + out_hip_ctrl_18 => out_hip_ctrl_18_xhdl23, + out_hip_ctrl_19 => out_hip_ctrl_19_xhdl24, + out_hip_ctrl_20 => out_hip_ctrl_20_xhdl26, + out_hip_ctrl_21 => out_hip_ctrl_21_xhdl27, + out_hip_ctrl_22 => out_hip_ctrl_22_xhdl28, + out_hip_ctrl_23 => out_hip_ctrl_23_xhdl29, + out_hip_ctrl_24 => out_hip_ctrl_24_xhdl30, + out_hip_ctrl_25 => out_hip_ctrl_25_xhdl31, + out_hip_ctrl_26 => out_hip_ctrl_26_xhdl32, + out_hip_ctrl_27 => out_hip_ctrl_27_xhdl33, + out_hip_ctrl_28 => out_hip_ctrl_28_xhdl34, + out_hip_ctrl_29 => out_hip_ctrl_29_xhdl35, + out_hip_ctrl_30 => out_hip_ctrl_30_xhdl37, + out_hip_ctrl_31 => out_hip_ctrl_31_xhdl38, + out_hip_ctrl_32 => out_hip_ctrl_32_xhdl39, + out_hip_ctrl_33 => out_hip_ctrl_33_xhdl40, + out_hip_ctrl_34 => out_hip_ctrl_34_xhdl41, + out_hip_ctrl_35 => out_hip_ctrl_35_xhdl42, + out_hip_ctrl_36 => out_hip_ctrl_36_xhdl43, + out_hip_ctrl_37 => out_hip_ctrl_37_xhdl44, + out_hip_ctrl_38 => out_hip_ctrl_38_xhdl45, + out_hip_ctrl_39 => out_hip_ctrl_39_xhdl46, + out_hip_ctrl_40 => out_hip_ctrl_40_xhdl48, + out_hip_ctrl_41 => out_hip_ctrl_41_xhdl49, + out_hip_ctrl_42 => out_hip_ctrl_42_xhdl50, + out_hip_ctrl_43 => out_hip_ctrl_43_xhdl51, + out_hip_ctrl_44 => out_hip_ctrl_44_xhdl52, + out_hip_ctrl_45 => out_hip_ctrl_45_xhdl53, + out_hip_ctrl_46 => out_hip_ctrl_46_xhdl54, + out_hip_ctrl_47 => out_hip_ctrl_47_xhdl55, + out_hip_ctrl_48 => out_hip_ctrl_48_xhdl56, + out_hip_ctrl_49 => out_hip_ctrl_49_xhdl57, + out_hip_ctrl_50 => out_hip_ctrl_50_xhdl59, + out_hip_ctrl_51 => out_hip_ctrl_51_xhdl60, + out_hip_ctrl_52 => out_hip_ctrl_52_xhdl61, + out_hip_ctrl_53 => out_hip_ctrl_53_xhdl62, + out_hip_ctrl_54 => out_hip_ctrl_54_xhdl63, + out_hip_ctrl_55 => out_hip_ctrl_55_xhdl64, + out_hip_ctrl_56 => out_hip_ctrl_56_xhdl65, + out_hip_ctrl_57 => out_hip_ctrl_57_xhdl66, + out_hip_ctrl_58 => out_hip_ctrl_58_xhdl67, + out_hip_ctrl_59 => out_hip_ctrl_59_xhdl68, + out_hip_ctrl_60 => out_hip_ctrl_60_xhdl70, + out_hip_ctrl_61 => out_hip_ctrl_61_xhdl71, + out_hip_ctrl_62 => out_hip_ctrl_62_xhdl72, + out_hip_ctrl_63 => out_hip_ctrl_63_xhdl73, + out_hip_ctrl_64 => out_hip_ctrl_64_xhdl74, + out_hip_ctrl_65 => out_hip_ctrl_65_xhdl75, + out_hip_ctrl_66 => out_hip_ctrl_66_xhdl76, + out_hip_ctrl_67 => out_hip_ctrl_67_xhdl77, + out_hip_ctrl_68 => out_hip_ctrl_68_xhdl78, + out_hip_ctrl_69 => out_hip_ctrl_69_xhdl79, + out_hip_ctrl_70 => out_hip_ctrl_70_xhdl81, + out_hip_ctrl_71 => out_hip_ctrl_71_xhdl82, + out_hip_ctrl_72 => out_hip_ctrl_72_xhdl83, + out_hip_ctrl_73 => out_hip_ctrl_73_xhdl84, + out_hip_ctrl_74 => out_hip_ctrl_74_xhdl85, + out_hip_ctrl_75 => out_hip_ctrl_75_xhdl86, + out_hip_ctrl_76 => out_hip_ctrl_76_xhdl87, + out_hip_ctrl_77 => out_hip_ctrl_77_xhdl88, + out_hip_ctrl_78 => out_hip_ctrl_78_xhdl89, + out_hip_ctrl_79 => out_hip_ctrl_79_xhdl90, + out_hip_ctrl_80 => out_hip_ctrl_80_xhdl92, + out_hip_ctrl_81 => out_hip_ctrl_81_xhdl93, + out_hip_ctrl_82 => out_hip_ctrl_82_xhdl94, + out_hip_ctrl_83 => out_hip_ctrl_83_xhdl95, + out_hip_ctrl_84 => out_hip_ctrl_84_xhdl96, + out_hip_ctrl_85 => out_hip_ctrl_85_xhdl97, + out_hip_ctrl_86 => out_hip_ctrl_86_xhdl98, + out_hip_ctrl_87 => out_hip_ctrl_87_xhdl99, + out_hip_ctrl_88 => out_hip_ctrl_88_xhdl100, + out_hip_ctrl_89 => out_hip_ctrl_89_xhdl101, + out_hip_ctrl_90 => out_hip_ctrl_90_xhdl103, + out_hip_ctrl_91 => out_hip_ctrl_91_xhdl104, + out_hip_ctrl_92 => out_hip_ctrl_92_xhdl105, + out_hip_ctrl_93 => out_hip_ctrl_93_xhdl106, + out_hip_ctrl_94 => out_hip_ctrl_94_xhdl107, + out_hip_ctrl_95 => out_hip_ctrl_95_xhdl108, + out_hip_ctrl_96 => out_hip_ctrl_96_xhdl109, + out_hip_ctrl_97 => out_hip_ctrl_97_xhdl110, + out_hip_ctrl_98 => out_hip_ctrl_98_xhdl111, + out_hip_ctrl_99 => out_hip_ctrl_99_xhdl112, + out_hip_ctrl_100 => out_hip_ctrl_100_xhdl5, + out_hip_ctrl_101 => out_hip_ctrl_101_xhdl6, + out_hip_ctrl_102 => out_hip_ctrl_102_xhdl7, + out_hip_ctrl_103 => out_hip_ctrl_103_xhdl8, + out_hip_ctrl_104 => out_hip_ctrl_104_xhdl9, + out_hip_ctrl_105 => out_hip_ctrl_105_xhdl10, + out_hip_ctrl_106 => out_hip_ctrl_106_xhdl11, + out_hip_ctrl_107 => out_hip_ctrl_107_xhdl12, + out_hip_ctrl_108 => out_hip_ctrl_108_xhdl13, + out_hip_ctrl_109 => out_hip_ctrl_109_xhdl14, + out_hip_ctrl_110 => out_hip_ctrl_110_xhdl16 + ); + + -- DPRIO address decoding + + + dprio_addr_1 : cycloneiv_pciehip_dprio_addr + PORT MAP ( + reset => mdio_rst, + mdc => mdc, + mdio_in => mdio_in, + shift_addr => shift_addr, + incr_addr => incr_addr, + reg_addr => reg_addr + ); + + -- DPRIO counter + + + dprio_cnt_1 : cycloneiv_pciehip_dprio_cnt + PORT MAP ( + reset => mdio_rst, + mdc => mdc, + ld_cnt => ld_cnt, + cnt_val => cnt_val, + cnt_eq_0 => cnt_eq_0 + ); + + -- DPRIO SM + + + dprio_sm_1 : cycloneiv_pciehip_dprio_sm + PORT MAP ( + reset => mdio_rst, + mdio_in => mdio_in, + mdc => mdc, + opcode => opcode, + valid_addr => valid_addr, + cnt_eq_0 => cnt_eq_0, + shift_in => shift_in, + shift_out => shift_out, + latch_ctl => latch_ctl, + incr_addr => incr_addr, + mdio_wr => mdio_wr, + mdio_rd => mdio_rd, + shift_addr => shift_addr, + ld_data => ld_data, + ld_cnt => ld_cnt, + cnt_val => cnt_val, + valid_addr_lt => valid_addr_lt, + curr_state => curr_state_xhdl0 + ); + + -- DPRIO data control + + + dprio_ctl_data_1 : cycloneiv_pciehip_dprio_ctl_data + PORT MAP ( + reset => mdio_rst, + mdc => mdc, + mdio_in => mdio_in, + shift_in => shift_in, + shift_out => shift_out, + ld_data => ld_data, + latch_ctl => latch_ctl, + port_addr => port_addr, + dev_addr => dev_addr, + valid_addr_lt => valid_addr_lt, + mbus_out => mbus_out, + mdio_out => mdio_out_xhdl2, + mbus_in => mbus_in, + opcode => opcode, + valid_addr => valid_addr, + data_enable_n => data_enable_n_xhdl1 + ); + +END ARCHITECTURE trans; + + + +------------------------------------------------------------------------------- +-- Result Bit Computing Module +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_compute_bit IS + PORT ( + datain : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + s : IN STD_LOGIC; + r : OUT STD_LOGIC + ); +END cycloneiv_pciehip_compute_bit; + +ARCHITECTURE trans OF cycloneiv_pciehip_compute_bit IS +BEGIN + -- begin + r <= datain(0) XOR datain(1) XOR datain(2) XOR datain(3) XOR datain(4) XOR datain(5) XOR datain(6) XOR datain(7) XOR datain(10) XOR datain(13) XOR datain(14) XOR datain(17) XOR datain(20) XOR datain(23) XOR datain(24) XOR datain(27) XOR datain(35) XOR datain(43) XOR datain(46) XOR datain(47) XOR datain(51) XOR datain(52) XOR datain(53) XOR datain(56) XOR datain(57) XOR datain(58) XOR s; + +END trans; + + +-- end + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_ecc_gen IS + PORT ( + datain : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- Data on which ECC is required + syndrome : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Syndrome uses 8'h00 while generating + -- Result + result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END cycloneiv_pciehip_ecc_gen; + +ARCHITECTURE trans OF cycloneiv_pciehip_ecc_gen IS + COMPONENT cycloneiv_pciehip_compute_bit + PORT ( + datain : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + s : IN STD_LOGIC; + r : OUT STD_LOGIC + ); + END COMPONENT; + + -- X-HDL generated signals + + SIGNAL xhdl6 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL xhdl7 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL xhdl8 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL xhdl9 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL xhdl10 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL xhdl11 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL xhdl12 : STD_LOGIC_VECTOR(63 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL result_xhdl0 : STD_LOGIC_VECTOR(7 DOWNTO 0); +BEGIN + -- Drive referenced outputs + result <= result_xhdl0; + + ------------------------------------------------------------------------------- + -- Instantiate Result Compute block for 8 bits + ------------------------------------------------------------------------------- + + + cb_0 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => datain, + s => syndrome(0), + r => result_xhdl0(0) + ); + + + xhdl6 <= (datain(7 DOWNTO 0) & datain(63 DOWNTO 8)); + cb_1 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => xhdl6, + s => syndrome(1), + r => result_xhdl0(1) + ); + + + xhdl7 <= (datain(15 DOWNTO 0) & datain(63 DOWNTO 16)); + cb_2 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => xhdl7, + s => syndrome(2), + r => result_xhdl0(2) + ); + + + xhdl8 <= (datain(23 DOWNTO 0) & datain(63 DOWNTO 24)); + cb_3 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => xhdl8, + s => syndrome(3), + r => result_xhdl0(3) + ); + + + xhdl9 <= (datain(31 DOWNTO 0) & datain(63 DOWNTO 32)); + cb_4 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => xhdl9, + s => syndrome(4), + r => result_xhdl0(4) + ); + + + xhdl10 <= (datain(39 DOWNTO 0) & datain(63 DOWNTO 40)); + cb_5 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => xhdl10, + s => syndrome(5), + r => result_xhdl0(5) + ); + + + xhdl11 <= (datain(47 DOWNTO 0) & datain(63 DOWNTO 48)); + cb_6 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => xhdl11, + s => syndrome(6), + r => result_xhdl0(6) + ); + + + xhdl12 <= (datain(55 DOWNTO 0) & datain(63 DOWNTO 56)); + cb_7 : cycloneiv_pciehip_compute_bit + PORT MAP ( + datain => xhdl12, + s => syndrome(7), + r => result_xhdl0(7) + ); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_ecc_chk IS + PORT ( + enable_ecc : IN STD_LOGIC; -- Active High Enable ECC + datain : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- Data on which ECC is required + syndrome : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Syndrome uses the result stored during ECC gen + dataout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- Single bit Corrected Data + single_err : OUT STD_LOGIC; -- Single Bit Error Detected + -- Multiple Bit Error detected + multi_err : OUT STD_LOGIC + ); +END cycloneiv_pciehip_ecc_chk; + +ARCHITECTURE trans OF cycloneiv_pciehip_ecc_chk IS + COMPONENT cycloneiv_pciehip_ecc_gen + PORT ( + datain : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + syndrome : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + + + ------------------------------------------------------------------------------- + -- Declare wires + ------------------------------------------------------------------------------- + SIGNAL correct_data : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL result : STD_LOGIC_VECTOR(7 DOWNTO 0); +BEGIN + + ------------------------------------------------------------------------------- + -- Instantiate ECC Generator Block, to generate the result + ------------------------------------------------------------------------------- + + + cycloneiv_pciehip_ecc_gen_inst : cycloneiv_pciehip_ecc_gen + PORT MAP ( + datain => datain, + syndrome => syndrome, + result => result + ); + + single_err <= '1' WHEN (reduction_or(result) = '1' AND reduction_xor((result)) = '1' AND enable_ecc = '1') ELSE + '0'; + multi_err <= '1' WHEN (reduction_or(result) = '1' AND reduction_xor((result)) = '0' AND enable_ecc = '1') ELSE + '0'; + + ------------------------------------------------------------------------------- + -- Check which bit is error by looking at the result polynomial + -- Designed based on the Paper:c3343, SEC-DEC Codecs, Figure 3 & Figure 5 + ------------------------------------------------------------------------------- + PROCESS (result) +VARIABLE txt : LINE; + BEGIN + CASE result IS + WHEN "00100011" => + correct_data <= "0000000000000000000000000000000000000000000000000000000000000001"; + WHEN "01000011" => + correct_data <= "0000000000000000000000000000000000000000000000000000000000000010"; + WHEN "10000011" => + correct_data <= "0000000000000000000000000000000000000000000000000000000000000100"; + WHEN "00111101" => + correct_data <= "0000000000000000000000000000000000000000000000000000000000001000"; + WHEN "01000101" => + correct_data <= "0000000000000000000000000000000000000000000000000000000000010000"; + WHEN "10000101" => + correct_data <= "0000000000000000000000000000000000000000000000000000000000100000"; + WHEN "10001001" => + correct_data <= "0000000000000000000000000000000000000000000000000000000001000000"; + + WHEN "01001001" => + correct_data <= "0000000000000000000000000000000000000000000000000000000010000000"; + WHEN "01000110" => + correct_data <= "0000000000000000000000000000000000000000000000000000000100000000"; + WHEN "10000110" => + correct_data <= "0000000000000000000000000000000000000000000000000000001000000000"; + WHEN "00000111" => + correct_data <= "0000000000000000000000000000000000000000000000000000010000000000"; + WHEN "01111010" => + correct_data <= "0000000000000000000000000000000000000000000000000000100000000000"; + WHEN "10001010" => + correct_data <= "0000000000000000000000000000000000000000000000000001000000000000"; + WHEN "00001011" => + correct_data <= "0000000000000000000000000000000000000000000000000010000000000000"; + WHEN "00010011" => + correct_data <= "0000000000000000000000000000000000000000000000000100000000000000"; + + WHEN "10010010" => + correct_data <= "0000000000000000000000000000000000000000000000001000000000000000"; + WHEN "10001100" => + correct_data <= "0000000000000000000000000000000000000000000000010000000000000000"; + WHEN "00001101" => + correct_data <= "0000000000000000000000000000000000000000000000100000000000000000"; + WHEN "00001110" => + correct_data <= "0000000000000000000000000000000000000000000001000000000000000000"; + WHEN "11110100" => + correct_data <= "0000000000000000000000000000000000000000000010000000000000000000"; + WHEN "00010101" => + correct_data <= "0000000000000000000000000000000000000000000100000000000000000000"; + WHEN "00010110" => + correct_data <= "0000000000000000000000000000000000000000001000000000000000000000"; + WHEN "00100110" => + correct_data <= "0000000000000000000000000000000000000000010000000000000000000000"; + + WHEN "00100101" => + correct_data <= "0000000000000000000000000000000000000000100000000000000000000000"; + WHEN "00011001" => + correct_data <= "0000000000000000000000000000000000000001000000000000000000000000"; + WHEN "00011010" => + correct_data <= "0000000000000000000000000000000000000010000000000000000000000000"; + WHEN "00011100" => + correct_data <= "0000000000000000000000000000000000000100000000000000000000000000"; + WHEN "11101001" => + correct_data <= "0000000000000000000000000000000000001000000000000000000000000000"; + WHEN "00101010" => + correct_data <= "0000000000000000000000000000000000010000000000000000000000000000"; + WHEN "00101100" => + correct_data <= "0000000000000000000000000000000000100000000000000000000000000000"; + WHEN "01001100" => + correct_data <= "0000000000000000000000000000000001000000000000000000000000000000"; + + WHEN "01001010" => + correct_data <= "0000000000000000000000000000000010000000000000000000000000000000"; + WHEN "00110010" => + correct_data <= "0000000000000000000000000000000100000000000000000000000000000000"; + WHEN "00110100" => + correct_data <= "0000000000000000000000000000001000000000000000000000000000000000"; + WHEN "00111000" => + correct_data <= "0000000000000000000000000000010000000000000000000000000000000000"; + WHEN "11010011" => + correct_data <= "0000000000000000000000000000100000000000000000000000000000000000"; + WHEN "01010100" => + correct_data <= "0000000000000000000000000001000000000000000000000000000000000000"; + WHEN "01011000" => + correct_data <= "0000000000000000000000000010000000000000000000000000000000000000"; + WHEN "10011000" => + correct_data <= "0000000000000000000000000100000000000000000000000000000000000000"; + + WHEN "10010100" => + correct_data <= "0000000000000000000000001000000000000000000000000000000000000000"; + WHEN "01100100" => + correct_data <= "0000000000000000000000010000000000000000000000000000000000000000"; + WHEN "01101000" => + correct_data <= "0000000000000000000000100000000000000000000000000000000000000000"; + WHEN "01110000" => + correct_data <= "0000000000000000000001000000000000000000000000000000000000000000"; + WHEN "10100111" => + correct_data <= "0000000000000000000010000000000000000000000000000000000000000000"; + WHEN "10101000" => + correct_data <= "0000000000000000000100000000000000000000000000000000000000000000"; + WHEN "10110000" => + correct_data <= "0000000000000000001000000000000000000000000000000000000000000000"; + WHEN "00110001" => + correct_data <= "0000000000000000010000000000000000000000000000000000000000000000"; + + WHEN "00101001" => + correct_data <= "0000000000000000100000000000000000000000000000000000000000000000"; + WHEN "11001000" => + correct_data <= "0000000000000001000000000000000000000000000000000000000000000000"; + WHEN "11010000" => + correct_data <= "0000000000000010000000000000000000000000000000000000000000000000"; + WHEN "11100000" => + correct_data <= "0000000000000100000000000000000000000000000000000000000000000000"; + WHEN "01001111" => + correct_data <= "0000000000001000000000000000000000000000000000000000000000000000"; + WHEN "01010001" => + correct_data <= "0000000000010000000000000000000000000000000000000000000000000000"; + WHEN "01100001" => + correct_data <= "0000000000100000000000000000000000000000000000000000000000000000"; + WHEN "01100010" => + correct_data <= "0000000001000000000000000000000000000000000000000000000000000000"; + + WHEN "01010010" => + correct_data <= "0000000010000000000000000000000000000000000000000000000000000000"; + WHEN "10010001" => + correct_data <= "0000000100000000000000000000000000000000000000000000000000000000"; + WHEN "10100001" => + correct_data <= "0000001000000000000000000000000000000000000000000000000000000000"; + WHEN "11000001" => + correct_data <= "0000010000000000000000000000000000000000000000000000000000000000"; + WHEN "10011110" => + correct_data <= "0000100000000000000000000000000000000000000000000000000000000000"; + WHEN "10100010" => + correct_data <= "0001000000000000000000000000000000000000000000000000000000000000"; + WHEN "11000010" => + correct_data <= "0010000000000000000000000000000000000000000000000000000000000000"; + WHEN "11000100" => + correct_data <= "0100000000000000000000000000000000000000000000000000000000000000"; + WHEN "10100100" => + correct_data <= "1000000000000000000000000000000000000000000000000000000000000000"; + WHEN OTHERS => + correct_data <= "0000000000000000000000000000000000000000000000000000000000000000"; + END CASE; + END PROCESS; + + ------------------------------------------------------------------------------- + -- Generate Final corrected Data, Flip the data bit based on the correct_data + ------------------------------------------------------------------------------- + dataout <= (datain XOR correct_data) WHEN (enable_ecc = '1') ELSE + datain; + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_ecc_decoder IS + PORT ( + + flag : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + derr : OUT STD_LOGIC; + derr_cor : OUT STD_LOGIC + ); +END cycloneiv_pciehip_ecc_decoder; + +ARCHITECTURE trans OF cycloneiv_pciehip_ecc_decoder IS +BEGIN + + derr <= flag(2) AND NOT((flag(1))) AND flag(0); + derr_cor <= NOT((flag(2))) AND flag(1) AND flag(0); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_pulse_ext IS + PORT ( + + core_clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + srst : IN STD_LOGIC; + derr_cor : IN STD_LOGIC; + derr_cor_ext : OUT STD_LOGIC + ); +END cycloneiv_pciehip_pulse_ext; + +ARCHITECTURE trans OF cycloneiv_pciehip_pulse_ext IS + + SIGNAL n1 : STD_LOGIC; + SIGNAL n2 : STD_LOGIC; +BEGIN + + -- Pulse width extender + + PROCESS (rstn, core_clk) +VARIABLE txt : LINE; + BEGIN + IF (rstn = '0') THEN + n1 <= '0'; + ELSIF (core_clk'EVENT AND core_clk = '1') THEN + IF (srst = '1') THEN + n1 <= '0'; + ELSE + n1 <= derr_cor; + END IF; + END IF; + END PROCESS; + + n2 <= n1 OR derr_cor; + + PROCESS (rstn, core_clk) +VARIABLE txt : LINE; + BEGIN + IF (rstn = '0') THEN + derr_cor_ext <= '0'; + ELSIF (core_clk'EVENT AND core_clk = '1') THEN + IF (srst = '1') THEN + derr_cor_ext <= '0'; + ELSE + derr_cor_ext <= n2; + END IF; + END IF; + END PROCESS; + +END trans; + + + +--------------------------------------------------------------- +-- +-- hip_mram +-- +-- MRAM implementation for DPRAM used in Receive and Retry buffers +-- +-- +--------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY cycloneiv_pciehip_hip_mram IS + GENERIC ( + + ADDR_WIDTH : INTEGER := 14; + DATA_WIDTH : INTEGER := 72 + ); + PORT ( + + dprio_mram_in : IN STD_LOGIC_VECTOR(16 DOWNTO 0); + + wrclock : IN STD_LOGIC; + wren : IN STD_LOGIC; + rden : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + rdclock : IN STD_LOGIC; + rdaddress : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + addrstallA : IN STD_LOGIC; + addrstallB : IN STD_LOGIC; + + r0_regscanin : IN STD_LOGIC; + r1_regscanin : IN STD_LOGIC; + r2_regscanin : IN STD_LOGIC; + r3_regscanin : IN STD_LOGIC; + r4_regscanin : IN STD_LOGIC; + r5_regscanin : IN STD_LOGIC; + r6_regscanin : IN STD_LOGIC; + r7_regscanin : IN STD_LOGIC; + + rsclk : IN STD_LOGIC; + rscen : IN STD_LOGIC; + rscin : IN STD_LOGIC; + rscsel : IN STD_LOGIC; + rscrst : IN STD_LOGIC; + id : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- output [63:0] q; + q : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + + DFT_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rscout : OUT STD_LOGIC; + r0_regscanout : OUT STD_LOGIC; + r1_regscanout : OUT STD_LOGIC; + r2_regscanout : OUT STD_LOGIC; + r3_regscanout : OUT STD_LOGIC; + r4_regscanout : OUT STD_LOGIC; + r5_regscanout : OUT STD_LOGIC; + r6_regscanout : OUT STD_LOGIC; + r7_regscanout : OUT STD_LOGIC; + nfrzdrv : IN STD_LOGIC; + frzreg : IN STD_LOGIC; + frzlogic : IN STD_LOGIC; + wrap_back_data : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + + flag : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + prv_mram : IN STD_LOGIC; + mram_hip_test_enable : IN STD_LOGIC; + scanen : IN STD_LOGIC; + enscan : IN STD_LOGIC + ); +END cycloneiv_pciehip_hip_mram; + +ARCHITECTURE trans OF cycloneiv_pciehip_hip_mram IS + COMPONENT altsyncram + GENERIC ( + width_a : INTEGER := 1; + widthad_a : INTEGER := 1; + numwords_a : INTEGER := 0; + outdata_reg_a : STRING := "UNREGISTERED"; + address_aclr_a : STRING := "NONE"; + outdata_aclr_a : STRING := "NONE"; + indata_aclr_a : STRING := "NONE"; + wrcontrol_aclr_a : STRING := "NONE"; + byteena_aclr_a : STRING := "NONE"; + width_byteena_a : INTEGER := 1; + width_b : INTEGER := 1; + widthad_b : INTEGER := 1; + numwords_b : INTEGER := 0; + rdcontrol_reg_b : STRING := "CLOCK1"; + address_reg_b : STRING := "CLOCK1"; + outdata_reg_b : STRING := "UNREGISTERED"; + outdata_aclr_b : STRING := "NONE"; + rdcontrol_aclr_b : STRING := "NONE"; + indata_reg_b : STRING := "CLOCK1"; + wrcontrol_wraddress_reg_b : STRING := "CLOCK1"; + byteena_reg_b : STRING := "CLOCK1"; + indata_aclr_b : STRING := "NONE"; + wrcontrol_aclr_b : STRING := "NONE"; + address_aclr_b : STRING := "NONE"; + byteena_aclr_b : STRING := "NONE"; + width_byteena_b : INTEGER := 1; + clock_enable_input_a : STRING := "NORMAL"; + clock_enable_output_a : STRING := "NORMAL"; + clock_enable_input_b : STRING := "NORMAL"; + clock_enable_output_b : STRING := "NORMAL"; + clock_enable_core_a : STRING := "USE_INPUT_CLKEN"; + clock_enable_core_b : STRING := "USE_INPUT_CLKEN"; + read_during_write_mode_port_a : STRING := "NEW_DATA_NO_NBE_READ"; + read_during_write_mode_port_b : STRING := "NEW_DATA_NO_NBE_READ"; + enable_ecc : STRING := "FALSE"; + operation_mode : STRING := "BIDIR_DUAL_PORT"; + byte_size : INTEGER := 0; + read_during_write_mode_mixed_ports : STRING := "DONT_CARE"; + sim_show_memory_data_in_port_b_layout : string := "OFF"; + ram_block_type : STRING := "AUTO"; + init_file : STRING := "UNUSED"; + init_file_layout : STRING := "UNUSED"; + maximum_depth : INTEGER := 0; + intended_device_family : STRING := "Stratix"; + lpm_hint : STRING := "UNUSED"; + lpm_type : STRING := "altsyncram"; + implement_in_les : STRING := "OFF"; + power_up_uninitialized : STRING := "FALSE" + ); + PORT ( + wren_a : IN STD_LOGIC; + wren_b : IN STD_LOGIC; + rden_a : IN STD_LOGIC; + rden_b : IN STD_LOGIC; + data_a : IN STD_LOGIC_VECTOR(width_a - 1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR(width_b - 1 DOWNTO 0); + address_a : IN STD_LOGIC_VECTOR(widthad_a - 1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR(widthad_b - 1 DOWNTO 0); + clock0 : IN STD_LOGIC; + clock1 : IN STD_LOGIC; + clocken0 : IN STD_LOGIC; + clocken1 : IN STD_LOGIC; + clocken2 : IN STD_LOGIC; + clocken3 : IN STD_LOGIC; + aclr0 : IN STD_LOGIC; + aclr1 : IN STD_LOGIC; + byteena_a : IN STD_LOGIC_VECTOR(width_byteena_a - 1 DOWNTO 0); + byteena_b : IN STD_LOGIC_VECTOR(width_byteena_b - 1 DOWNTO 0); + addressstall_a : IN STD_LOGIC; + addressstall_b : IN STD_LOGIC; + q_a : OUT STD_LOGIC_VECTOR(width_a - 1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR(width_b - 1 DOWNTO 0); + eccstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); + END COMPONENT; + + SIGNAL rxcorea : STD_LOGIC_VECTOR(32 DOWNTO 0); + SIGNAL rxcoreb : STD_LOGIC_VECTOR(32 DOWNTO 0); + -- X-HDL generated signals + + SIGNAL xhdl13 : STD_LOGIC_VECTOR(71 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL q_xhdl1 : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); +BEGIN + -- Drive referenced outputs + q <= q_xhdl1; + + DFT_out <= "00000000"; -- Hard-wired ID for redundancy repair; set to all 0's for now + rscout <= '0'; + flag <= "000"; + + r0_regscanout <= '0'; + r1_regscanout <= '0'; + r2_regscanout <= '0'; + r3_regscanout <= '0'; + r4_regscanout <= '0'; + r5_regscanout <= '0'; + r6_regscanout <= '0'; + r7_regscanout <= '0'; + -- MRAM + + + + xhdl13 <= '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1' & '1'; + altsyncram_component : altsyncram + GENERIC MAP( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + enable_ecc => "FALSE", + intended_device_family => "Stratix III", + lpm_type => "altsyncram", + numwords_a => 16384, + numwords_b => 16384, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "UNREGISTERED", + ram_block_type => "M144K", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => ADDR_WIDTH, -- 14, + widthad_b => ADDR_WIDTH, -- 14, + width_a => DATA_WIDTH, -- 72, + width_b => DATA_WIDTH, -- 72, + width_byteena_a => 1 + ) + + PORT MAP ( + addressstall_a => addrstallA, + addressstall_b => addrstallB, + wren_a => wren, + clock0 => wrclock, + address_a => wraddress, + address_b => rdaddress, + data_a => data, + q_b => q_xhdl1, + aclr0 => '0', + aclr1 => '0', + byteena_a => "1", + byteena_b => "1", + clock1 => '1', + clocken0 => '1', + clocken1 => '1', + clocken2 => '1', + clocken3 => '1', + data_b => xhdl13, + rden_a => '1', + rden_b => '1', + wren_b => '0' + ); + +END trans; + + +--.eccstatus (), +--.q_a (), +--.rden_b (rden), +-- altsyncram_component.numwords_a = 2^ADDR_WIDTH, +-- altsyncram_component.numwords_b = 2^ADDR_WIDTH, +-- altsyncram_component.outdata_reg_b = "CLOCK0", + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_mram_top IS + GENERIC ( + -- Added bits[18:17]:clk-stealing enable, bit[16] for ECC enable + -- Async Reset for ECC error pulse width extender and BIST + -- Sync Reset for ECC error pulse width extender + -- Enable for BIST + -- DPRIO inputs for BIST + -- Enable for Redundancy Scan, to be tested w/ full model later + -- Scan Enable for Redundancy testing, to be tested w/ full model later + -- Redundancy scan input from previous MRAM in the chain + -- Scan Input for Redundancy testing, to be tested w/ full model later + -- Scan Select for Redundancy testing, to be tested w/ full model later + -- Scan reset for Redundancy testing, to be tested w/ full model later + -- Scan Clock for Redundancy testing, to be tested w/ full model later + -- Hard-wired ID for Redundancy repair + -- RegScan Enable for MRAM I/O scan chain, to be tested w/ full model later + -- RegScan Input for MRAM I/O scan chain, to be tested w/ full model later + -- Signal to disable WE of MRAM during RegScan + -- Scan Enable for BIST debug logic + -- Scan Input for BIST debug logic + -- Input to choose between normal mode inputs and BIST inputs to MRAM + -- Input to choose between extended and non-extended uncorrected error flags + -- RegScan Output for MRAM I/O scan chain, to be tested w/ full model later + -- Scan Output for Redundancy testing, to be tested w/ full model later + -- Scan Output for BIST debug logic + -- BIST Done indicator for Port A + -- BIST Done indicator for Port B + -- BIST pass/fail indicator + -- ECC uncorrected error signal + -- ECC corrected error signal (extended) + -- Freeze signal from PLD Control Block + -- Freeze signal from PLD Control Block + -- Freeze signal from PLD Control Block + -- Scan mode signal to disable clock stealing + + ADDR_WIDTH : INTEGER := 14; + DATA_WIDTH : INTEGER := 72 + ); + PORT ( + core_clk : IN STD_LOGIC; + dprio_mram_in : IN STD_LOGIC_VECTOR(34 DOWNTO 0); + addrA : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + addrB : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + wren : IN STD_LOGIC; + + dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + rstn : IN STD_LOGIC; + srst : IN STD_LOGIC; + bisten : IN STD_LOGIC; + dprio_bist_in : IN STD_LOGIC_VECTOR(74 DOWNTO 0); + enscan : IN STD_LOGIC; + rscen : IN STD_LOGIC; + prv_mram : IN STD_LOGIC; + rscin : IN STD_LOGIC; + rscsel : IN STD_LOGIC; + rscrst : IN STD_LOGIC; + rsclk : IN STD_LOGIC; + id : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + scanen : IN STD_LOGIC; + scanin : IN STD_LOGIC; + mram_hip_test_enable : IN STD_LOGIC; + bist_scanen : IN STD_LOGIC; + bist_scanin : IN STD_LOGIC; + testen : IN STD_LOGIC; + uncor_err_ext_en : IN STD_LOGIC; + + scanout : OUT STD_LOGIC; + + rscout : OUT STD_LOGIC; + bist_scanout : OUT STD_LOGIC; + bistdoneA : OUT STD_LOGIC; + bistdoneB : OUT STD_LOGIC; + pass : OUT STD_LOGIC; + derr : OUT STD_LOGIC; + derr_cor_ext : OUT STD_LOGIC; + nfrzdrv : IN STD_LOGIC; + frzreg : IN STD_LOGIC; + frzlogic : IN STD_LOGIC; + scan_mode : IN STD_LOGIC + ); +END cycloneiv_pciehip_mram_top; + +ARCHITECTURE trans OF cycloneiv_pciehip_mram_top IS + COMPONENT cycloneiv_pciehip_ecc_chk + PORT ( + enable_ecc : IN STD_LOGIC; + datain : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + syndrome : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dataout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + single_err : OUT STD_LOGIC; + multi_err : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_ecc_decoder + PORT ( + flag : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + derr : OUT STD_LOGIC; + derr_cor : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_hip_mram + GENERIC ( + ADDR_WIDTH : INTEGER := 14; + DATA_WIDTH : INTEGER := 72 + ); + PORT ( + dprio_mram_in : IN STD_LOGIC_VECTOR(16 DOWNTO 0); + wrclock : IN STD_LOGIC; + wren : IN STD_LOGIC; + rden : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + rdclock : IN STD_LOGIC; + rdaddress : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + addrstallA : IN STD_LOGIC; + addrstallB : IN STD_LOGIC; + r0_regscanin : IN STD_LOGIC; + r1_regscanin : IN STD_LOGIC; + r2_regscanin : IN STD_LOGIC; + r3_regscanin : IN STD_LOGIC; + r4_regscanin : IN STD_LOGIC; + r5_regscanin : IN STD_LOGIC; + r6_regscanin : IN STD_LOGIC; + r7_regscanin : IN STD_LOGIC; + rsclk : IN STD_LOGIC; + rscen : IN STD_LOGIC; + rscin : IN STD_LOGIC; + rscsel : IN STD_LOGIC; + rscrst : IN STD_LOGIC; + id : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + DFT_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rscout : OUT STD_LOGIC; + r0_regscanout : OUT STD_LOGIC; + r1_regscanout : OUT STD_LOGIC; + r2_regscanout : OUT STD_LOGIC; + r3_regscanout : OUT STD_LOGIC; + r4_regscanout : OUT STD_LOGIC; + r5_regscanout : OUT STD_LOGIC; + r6_regscanout : OUT STD_LOGIC; + r7_regscanout : OUT STD_LOGIC; + nfrzdrv : IN STD_LOGIC; + frzreg : IN STD_LOGIC; + frzlogic : IN STD_LOGIC; + wrap_back_data : IN STD_LOGIC_VECTOR(71 DOWNTO 0); + flag : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + prv_mram : IN STD_LOGIC; + mram_hip_test_enable : IN STD_LOGIC; + scanen : IN STD_LOGIC; + enscan : IN STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_pulse_ext + PORT ( + core_clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + srst : IN STD_LOGIC; + derr_cor : IN STD_LOGIC; + derr_cor_ext : OUT STD_LOGIC + ); + END COMPONENT; + + + SIGNAL rdclock_dummy : STD_LOGIC; -- shawn + + SIGNAL dout_int : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + + SIGNAL DFT_out : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL addrstallA_bist : STD_LOGIC; + SIGNAL addrstallB_bist : STD_LOGIC; + SIGNAL addrstallA : STD_LOGIC; + SIGNAL addrstallB : STD_LOGIC; + SIGNAL writedata : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + SIGNAL din : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + -- cycloneiv + --SIGNAL addrA_bist : STD_LOGIC_VECTOR(13 DOWNTO 0); + --SIGNAL addrB_bist : STD_LOGIC_VECTOR(13 DOWNTO 0); + --SIGNAL adwr : STD_LOGIC_VECTOR(13 DOWNTO 0); + --SIGNAL adrd : STD_LOGIC_VECTOR(13 DOWNTO 0); + SIGNAL addrA_bist : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + SIGNAL addrB_bist : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + SIGNAL adwr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + SIGNAL adrd : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + SIGNAL wren_bist : STD_LOGIC; + SIGNAL write_en : STD_LOGIC; + SIGNAL r0_regscanout : STD_LOGIC; + SIGNAL r1_regscanout : STD_LOGIC; + SIGNAL r2_regscanout : STD_LOGIC; + SIGNAL r3_regscanout : STD_LOGIC; + SIGNAL r4_regscanout : STD_LOGIC; + SIGNAL r5_regscanout : STD_LOGIC; + SIGNAL r6_regscanout : STD_LOGIC; + -- wire derr_cor; + + SIGNAL derr_int : STD_LOGIC; + SIGNAL derr_cor_int : STD_LOGIC; + SIGNAL derr_int_ext : STD_LOGIC; + SIGNAL derr_int_nc : STD_LOGIC; + SIGNAL derr_cor_int_nc : STD_LOGIC; + + SIGNAL flag : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL wrap_back_data : STD_LOGIC_VECTOR(71 DOWNTO 0); + + SIGNAL core_clk_int : STD_LOGIC; + SIGNAL temp : STD_LOGIC_VECTOR(63 DOWNTO 0); + -- X-HDL generated signals + + SIGNAL xhdl13 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL xhdl14 : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL scanout_xhdl4 : STD_LOGIC; + SIGNAL rscout_xhdl3 : STD_LOGIC; + SIGNAL derr_cor_ext_xhdl2 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + scanout <= scanout_xhdl4; + rscout <= rscout_xhdl3; + derr_cor_ext <= derr_cor_ext_xhdl2; + + -- wire [32:0] rxcorea; + -- wire [32:0] rxcoreb; + + addrstallA <= addrstallA_bist WHEN (testen = '1') ELSE + '0'; + addrstallB <= addrstallB_bist WHEN (testen = '1') ELSE + '0'; + adwr <= addrA_bist WHEN (testen = '1') ELSE + addrA; + adrd <= addrB_bist WHEN (testen = '1') ELSE + addrB; + write_en <= wren_bist WHEN (testen = '1') ELSE + wren; + din <= writedata WHEN (testen = '1') ELSE + data; + + -- assign rxcorea = 33'h000000000; // hard-wired to 0's for now; change this to program MRAM setting + -- assign rxcoreb = 33'h000000000; // hard-wired to 0's for now; change this to program MRAM setting + + -- Instantiate the BIST muxes for Ports A and B + + core_clk_int <= core_clk; + dout(70 DOWNTO 63) <= temp(63 DOWNTO 56); + dout(61 DOWNTO 54) <= temp(55 DOWNTO 48); + dout(52 DOWNTO 45) <= temp(47 DOWNTO 40); + dout(43 DOWNTO 36) <= temp(39 DOWNTO 32); + dout(34 DOWNTO 27) <= temp(31 DOWNTO 24); + dout(25 DOWNTO 18) <= temp(23 DOWNTO 16); + dout(16 DOWNTO 9) <= temp(15 DOWNTO 8); + dout(7 DOWNTO 0) <= temp(7 DOWNTO 0); + + + xhdl13 <= (dout_int(70 DOWNTO 63) & dout_int(61 DOWNTO 54) & dout_int(52 DOWNTO 45) & dout_int(43 DOWNTO 36) & dout_int(34 DOWNTO 27) & dout_int(25 DOWNTO 18) & dout_int(16 DOWNTO 9) & dout_int(7 DOWNTO 0)); + xhdl14 <= (dout_int(71) & dout_int(62) & dout_int(53) & dout_int(44) & dout_int(35) & dout_int(26) & dout_int(17) & dout_int(8)); + u_ecc_chk : cycloneiv_pciehip_ecc_chk + PORT MAP ( + enable_ecc => dprio_mram_in(16), + datain => xhdl13, + syndrome => xhdl14, + dataout => temp, + single_err => derr_cor_int, + multi_err => derr_int + ); + + dout(71) <= '0'; + dout(62) <= '0'; + dout(53) <= '0'; + dout(44) <= '0'; + dout(35) <= '0'; + dout(26) <= '0'; + dout(17) <= '0'; + dout(8) <= '0'; + + -- Full-model buffer w/ REGSCAN, redundancy scan + + + memory : cycloneiv_pciehip_hip_mram + GENERIC MAP ( + ADDR_WIDTH => ADDR_WIDTH, -- cycloneiv: 14 + DATA_WIDTH => DATA_WIDTH + ) + PORT MAP ( + dprio_mram_in => dprio_mram_in(16 DOWNTO 0), + wrclock => core_clk_int, + wren => write_en, + rden => '1', + -- .rden(dprio_mram_in[18]), + wraddress => adwr, + data => din, + rdaddress => adrd, + addrstallA => addrstallA, + addrstallB => addrstallB, + r0_regscanin => scanin, + r1_regscanin => r0_regscanout, + r2_regscanin => r1_regscanout, + r3_regscanin => r2_regscanout, + r4_regscanin => r3_regscanout, + r5_regscanin => r4_regscanout, + r6_regscanin => r5_regscanout, + r7_regscanin => r6_regscanout, + rsclk => rsclk, + rscen => rscen, + rscin => rscin, + rscsel => rscsel, + rscrst => rscrst, + id => id, + q => dout_int, + flag => flag, + DFT_out => DFT_out, + rscout => rscout_xhdl3, + r0_regscanout => r0_regscanout, + r1_regscanout => r1_regscanout, + r2_regscanout => r2_regscanout, + r3_regscanout => r3_regscanout, + r4_regscanout => r4_regscanout, + r5_regscanout => r5_regscanout, + r6_regscanout => r6_regscanout, + r7_regscanout => scanout_xhdl4, + nfrzdrv => nfrzdrv, + frzreg => frzreg, + frzlogic => frzlogic, + wrap_back_data => wrap_back_data, + enscan => enscan, + scanen => scanen, + prv_mram => prv_mram, + rdclock => rdclock_dummy, -- shawn + mram_hip_test_enable => mram_hip_test_enable + ); + + -- Instantiate decoding logic for MRAM ECC flags + + + + ed : cycloneiv_pciehip_ecc_decoder + PORT MAP ( + flag => flag, + derr => derr_int_nc, + derr_cor => derr_cor_int_nc + ); + + -- Instantiate Pulse width extenders + + + + pe0 : cycloneiv_pciehip_pulse_ext + PORT MAP ( + core_clk => core_clk, + rstn => rstn, + srst => srst, + derr_cor => derr_int, + derr_cor_ext => derr_int_ext + ); + + derr <= derr_int_ext WHEN (uncor_err_ext_en = '1') ELSE + derr_int; + + + + pe1 : cycloneiv_pciehip_pulse_ext + PORT MAP ( + core_clk => core_clk, + rstn => rstn, + srst => srst, + derr_cor => derr_cor_int, + derr_cor_ext => derr_cor_ext_xhdl2 + ); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_pciexp_dcfiforam IS + GENERIC ( + + addr_width : INTEGER := 4; + data_width : INTEGER := 32 + ); + PORT ( + data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0); + wren : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0); + wrclock : IN STD_LOGIC; + rdclock : IN STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END cycloneiv_pciehip_pciexp_dcfiforam; + +ARCHITECTURE trans OF cycloneiv_pciehip_pciexp_dcfiforam IS + TYPE type_xhdl0 IS ARRAY (0 TO 2 ** addr_width - 1) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); + + + SIGNAL ram_block : type_xhdl0; + SIGNAL rdaddr_r : STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + SIGNAL wraddr_r : STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + SIGNAL wren_r : STD_LOGIC; + SIGNAL wrdata_r : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); +BEGIN + + -- Write process + PROCESS (wrclock) +VARIABLE txt : LINE; + BEGIN + IF (wrclock'EVENT AND wrclock = '1') THEN + wren_r <= wren; + wraddr_r <= wraddress; + wrdata_r <= data; + IF (wren_r = '1') THEN + ram_block(bin2int(wraddr_r)) <= wrdata_r; + END IF; + END IF; + END PROCESS; + + -- Read process + PROCESS (rdclock) +VARIABLE txt : LINE; + BEGIN + IF (rdclock'EVENT AND rdclock = '1') THEN + rdaddr_r <= rdaddress; + END IF; + END PROCESS; + q <= ram_block(bin2int(rdaddr_r)); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_pciexp_dcram_rtry IS + GENERIC ( + + addr_width : INTEGER := 4; + data_width : INTEGER := 32 + ); + PORT ( + + wrclock : IN STD_LOGIC; + wren : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); + rdclock : IN STD_LOGIC; + rdaddress : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END cycloneiv_pciehip_pciexp_dcram_rtry; + +ARCHITECTURE trans OF cycloneiv_pciehip_pciexp_dcram_rtry IS + TYPE type_xhdl1 IS ARRAY ((2**addr_width) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); + + + -- ------------------------------------------------------------- + + SIGNAL ram_block : type_xhdl1; + SIGNAL read_addr_r : STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + SIGNAL wraddr_r : STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + SIGNAL wren_r : STD_LOGIC; + SIGNAL wrdata_r : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); +BEGIN + + -- Write process + PROCESS (wrclock) +VARIABLE txt : LINE; + BEGIN + IF (wrclock'EVENT AND wrclock = '1') THEN + wren_r <= wren; + wraddr_r <= wraddress; + + wrdata_r <= data; + IF (wren_r = '1') THEN + ram_block(bin2int(wraddr_r)) <= wrdata_r; + END IF; + END IF; + END PROCESS; + + -- Read process + PROCESS (rdclock) +VARIABLE txt : LINE; + BEGIN + IF (rdclock'EVENT AND rdclock = '1') THEN + read_addr_r <= rdaddress; + END IF; + END PROCESS; + + q <= ram_block(bin2int(read_addr_r)); + +END trans; + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +ENTITY cycloneiv_pciehip_pciexp_dcram_rxvc IS + GENERIC ( + + addr_width : INTEGER := 4; + data_width : INTEGER := 32 + ); + PORT ( + + wrclock : IN STD_LOGIC; + wren : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); + rdclock : IN STD_LOGIC; + rdaddress : IN STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END cycloneiv_pciehip_pciexp_dcram_rxvc; + +ARCHITECTURE trans OF cycloneiv_pciehip_pciexp_dcram_rxvc IS + TYPE type_xhdl2 IS ARRAY ((2**addr_width) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); + + + -- ------------------------------------------------------------- + + SIGNAL ram_block : type_xhdl2; + SIGNAL read_addr_r : STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + SIGNAL wraddr_r : STD_LOGIC_VECTOR(addr_width - 1 DOWNTO 0); + SIGNAL wren_r : STD_LOGIC; + SIGNAL wrdata_r : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); +BEGIN + + -- Write process + PROCESS (wrclock) +VARIABLE txt : LINE; + BEGIN + IF (wrclock'EVENT AND wrclock = '1') THEN + wren_r <= wren; + wraddr_r <= wraddress; + + wrdata_r <= data; + IF (wren_r = '1') THEN + ram_block(bin2int(wraddr_r)) <= wrdata_r; + END IF; + END IF; + END PROCESS; + + -- Read process + PROCESS (rdclock) +VARIABLE txt : LINE; + BEGIN + IF (rdclock'EVENT AND rdclock = '1') THEN + read_addr_r <= rdaddress; + END IF; + END PROCESS; + + q <= ram_block(bin2int(read_addr_r)); + +END trans; + + +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + +--synthesis_resources = lut 808 mux21 840 oper_add 40 oper_less_than 16 oper_mux 24 oper_selector 32 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_pciehip_iei_detect IS + PORT + ( + datain_ch0 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + datain_ch1 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + datain_ch2 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + datain_ch3 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + datain_ch4 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + datain_ch5 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + datain_ch6 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + datain_ch7 : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + eidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + enable_inf_ei : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + pclk : IN STD_LOGIC; + prstn : IN STD_LOGIC; + rate : IN STD_LOGIC; + rxelecidle : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rxelecidle_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxupdatefc : IN STD_LOGIC; + rxvalid : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + test_in_0 : IN STD_LOGIC; + uclk : IN STD_LOGIC; + urstn : IN STD_LOGIC + ); + END cycloneiv_pciehip_iei_detect; + + ARCHITECTURE RTL OF cycloneiv_pciehip_iei_detect IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL nli00OO67 : STD_LOGIC := '0'; + SIGNAL nli00OO68 : STD_LOGIC := '0'; + SIGNAL nli0i1i65 : STD_LOGIC := '0'; + SIGNAL nli0i1i66 : STD_LOGIC := '0'; + SIGNAL nli0O0i63 : STD_LOGIC := '0'; + SIGNAL nli0O0i64 : STD_LOGIC := '0'; + SIGNAL nli0O0l61 : STD_LOGIC := '0'; + SIGNAL nli0O0l62 : STD_LOGIC := '0'; + SIGNAL nli1iiO71 : STD_LOGIC := '0'; + SIGNAL nli1iiO72 : STD_LOGIC := '0'; + SIGNAL nli1OlO69 : STD_LOGIC := '0'; + SIGNAL nli1OlO70 : STD_LOGIC := '0'; + SIGNAL nlii0il59 : STD_LOGIC := '0'; + SIGNAL nlii0il60 : STD_LOGIC := '0'; + SIGNAL nliilll57 : STD_LOGIC := '0'; + SIGNAL nliilll58 : STD_LOGIC := '0'; + SIGNAL nlil1Ol55 : STD_LOGIC := '0'; + SIGNAL nlil1Ol56 : STD_LOGIC := '0'; + SIGNAL nliliOl53 : STD_LOGIC := '0'; + SIGNAL nliliOl54 : STD_LOGIC := '0'; + SIGNAL nliliOO51 : STD_LOGIC := '0'; + SIGNAL nliliOO52 : STD_LOGIC := '0'; + SIGNAL nlill0O45 : STD_LOGIC := '0'; + SIGNAL nlill0O46 : STD_LOGIC := '0'; + SIGNAL nlill1i49 : STD_LOGIC := '0'; + SIGNAL nlill1i50 : STD_LOGIC := '0'; + SIGNAL nlill1l47 : STD_LOGIC := '0'; + SIGNAL nlill1l48 : STD_LOGIC := '0'; + SIGNAL nlillOl43 : STD_LOGIC := '0'; + SIGNAL nlillOl44 : STD_LOGIC := '0'; + SIGNAL nlilO0i41 : STD_LOGIC := '0'; + SIGNAL nlilO0i42 : STD_LOGIC := '0'; + SIGNAL nlilOiO39 : STD_LOGIC := '0'; + SIGNAL nlilOiO40 : STD_LOGIC := '0'; + SIGNAL nliO01O23 : STD_LOGIC := '0'; + SIGNAL nliO01O24 : STD_LOGIC := '0'; + SIGNAL wire_nliO01O24_w_lg_w_lg_q161w162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO01O24_w_lg_q161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0iO21 : STD_LOGIC := '0'; + SIGNAL nliO0iO22 : STD_LOGIC := '0'; + SIGNAL wire_nliO0iO22_w_lg_w_lg_q123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0iO22_w_lg_q123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0li19 : STD_LOGIC := '0'; + SIGNAL nliO0li20 : STD_LOGIC := '0'; + SIGNAL wire_nliO0li20_w_lg_w_lg_q120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0li20_w_lg_q120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0ll17 : STD_LOGIC := '0'; + SIGNAL nliO0ll18 : STD_LOGIC := '0'; + SIGNAL wire_nliO0ll18_w_lg_w_lg_q91w92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0ll18_w_lg_q91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0lO15 : STD_LOGIC := '0'; + SIGNAL nliO0lO16 : STD_LOGIC := '0'; + SIGNAL wire_nliO0lO16_w_lg_w_lg_q85w86w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0lO16_w_lg_q85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0Oi13 : STD_LOGIC := '0'; + SIGNAL nliO0Oi14 : STD_LOGIC := '0'; + SIGNAL wire_nliO0Oi14_w_lg_w_lg_q54w55w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0Oi14_w_lg_q54w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0Ol11 : STD_LOGIC := '0'; + SIGNAL nliO0Ol12 : STD_LOGIC := '0'; + SIGNAL wire_nliO0Ol12_w_lg_w_lg_q50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0Ol12_w_lg_q50w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0OO10 : STD_LOGIC := '0'; + SIGNAL wire_nliO0OO10_w_lg_w_lg_q46w47w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO0OO10_w_lg_q46w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO0OO9 : STD_LOGIC := '0'; + SIGNAL nliO10i35 : STD_LOGIC := '0'; + SIGNAL nliO10i36 : STD_LOGIC := '0'; + SIGNAL wire_nliO10i36_w_lg_w_lg_q257w258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO10i36_w_lg_q257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO10l33 : STD_LOGIC := '0'; + SIGNAL nliO10l34 : STD_LOGIC := '0'; + SIGNAL wire_nliO10l34_w_lg_w_lg_q231w232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO10l34_w_lg_q231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO10O31 : STD_LOGIC := '0'; + SIGNAL nliO10O32 : STD_LOGIC := '0'; + SIGNAL wire_nliO10O32_w_lg_w_lg_q225w226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliO10O32_w_lg_q225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliO11i37 : STD_LOGIC := '0'; + SIGNAL nliO11i38 : STD_LOGIC := '0'; + SIGNAL nliO1il29 : STD_LOGIC := '0'; + SIGNAL nliO1il30 : STD_LOGIC := '0'; + SIGNAL nliO1li27 : STD_LOGIC := '0'; + SIGNAL nliO1li28 : STD_LOGIC := '0'; + SIGNAL nliO1lO25 : STD_LOGIC := '0'; + SIGNAL nliO1lO26 : STD_LOGIC := '0'; + SIGNAL nliOi0i3 : STD_LOGIC := '0'; + SIGNAL nliOi0i4 : STD_LOGIC := '0'; + SIGNAL nliOi1i7 : STD_LOGIC := '0'; + SIGNAL nliOi1i8 : STD_LOGIC := '0'; + SIGNAL nliOi1l5 : STD_LOGIC := '0'; + SIGNAL nliOi1l6 : STD_LOGIC := '0'; + SIGNAL nliOiiO1 : STD_LOGIC := '0'; + SIGNAL nliOiiO2 : STD_LOGIC := '0'; + SIGNAL n0iO0O : STD_LOGIC := '0'; + SIGNAL n0iOil : STD_LOGIC := '0'; + SIGNAL wire_n0iOii_PRN : STD_LOGIC; + SIGNAL n1l0l : STD_LOGIC := '0'; + SIGNAL n1l1O : STD_LOGIC := '0'; + SIGNAL wire_n1l0i_PRN : STD_LOGIC; + SIGNAL n1ll0l : STD_LOGIC := '0'; + SIGNAL n1ll1O : STD_LOGIC := '0'; + SIGNAL wire_n1ll0i_CLRN : STD_LOGIC; + SIGNAL wire_n1ll0i_PRN : STD_LOGIC; + SIGNAL nii1iO : STD_LOGIC := '0'; + SIGNAL nii1ll : STD_LOGIC := '0'; + SIGNAL wire_nii1li_CLRN : STD_LOGIC; + SIGNAL nl00lO : STD_LOGIC := '0'; + SIGNAL nl00Ol : STD_LOGIC := '0'; + SIGNAL wire_nl00Oi_PRN : STD_LOGIC; + SIGNAL n0001l : STD_LOGIC := '0'; + SIGNAL n011OO : STD_LOGIC := '0'; + SIGNAL n0i0iO : STD_LOGIC := '0'; + SIGNAL n0iiiO : STD_LOGIC := '0'; + SIGNAL n0iOiO : STD_LOGIC := '0'; + SIGNAL n0iOli : STD_LOGIC := '0'; + SIGNAL n0iOll : STD_LOGIC := '0'; + SIGNAL n0iOlO : STD_LOGIC := '0'; + SIGNAL n0Oi1O : STD_LOGIC := '0'; + SIGNAL n100O : STD_LOGIC := '0'; + SIGNAL n10OOl : STD_LOGIC := '0'; + SIGNAL n110O : STD_LOGIC := '0'; + SIGNAL n11OlO : STD_LOGIC := '0'; + SIGNAL n1l00O : STD_LOGIC := '0'; + SIGNAL n1l0O : STD_LOGIC := '0'; + SIGNAL n1l10O : STD_LOGIC := '0'; + SIGNAL n1lii : STD_LOGIC := '0'; + SIGNAL n1lil : STD_LOGIC := '0'; + SIGNAL n1liO : STD_LOGIC := '0'; + SIGNAL n1ll0O : STD_LOGIC := '0'; + SIGNAL n1llii : STD_LOGIC := '0'; + SIGNAL n1llil : STD_LOGIC := '0'; + SIGNAL n1lliO : STD_LOGIC := '0'; + SIGNAL ni0ilO : STD_LOGIC := '0'; + SIGNAL ni0llO : STD_LOGIC := '0'; + SIGNAL ni1i0l : STD_LOGIC := '0'; + SIGNAL ni1OO : STD_LOGIC := '0'; + SIGNAL nii1lO : STD_LOGIC := '0'; + SIGNAL nii1Oi : STD_LOGIC := '0'; + SIGNAL nii1Ol : STD_LOGIC := '0'; + SIGNAL nii1OO : STD_LOGIC := '0'; + SIGNAL nill0O : STD_LOGIC := '0'; + SIGNAL niOlil : STD_LOGIC := '0'; + SIGNAL nl00OO : STD_LOGIC := '0'; + SIGNAL nl01O : STD_LOGIC := '0'; + SIGNAL nl0i1i : STD_LOGIC := '0'; + SIGNAL nl0i1l : STD_LOGIC := '0'; + SIGNAL nl0i1O : STD_LOGIC := '0'; + SIGNAL nl1lOO : STD_LOGIC := '0'; + SIGNAL nl1OOO : STD_LOGIC := '0'; + SIGNAL nliOiO : STD_LOGIC := '0'; + SIGNAL nll10lO : STD_LOGIC := '0'; + SIGNAL nll1ilO : STD_LOGIC := '0'; + SIGNAL nll1OlO : STD_LOGIC := '0'; + SIGNAL nll1OOi : STD_LOGIC := '0'; + SIGNAL nll1OOl : STD_LOGIC := '0'; + SIGNAL nll1OOO : STD_LOGIC := '0'; + SIGNAL nllii0O : STD_LOGIC := '0'; + SIGNAL nllliil : STD_LOGIC := '0'; + SIGNAL nllOiOO : STD_LOGIC := '0'; + SIGNAL nllOll : STD_LOGIC := '0'; + SIGNAL nllOlOO : STD_LOGIC := '0'; + SIGNAL nlO0liO : STD_LOGIC := '0'; + SIGNAL nlO101i : STD_LOGIC := '0'; + SIGNAL nlO101l : STD_LOGIC := '0'; + SIGNAL nlO101O : STD_LOGIC := '0'; + SIGNAL nlO11OO : STD_LOGIC := '0'; + SIGNAL nlOilll : STD_LOGIC := '0'; + SIGNAL nlOlO1O : STD_LOGIC := '0'; + SIGNAL nlOO11O : STD_LOGIC := '0'; + SIGNAL nlOOi0i : STD_LOGIC := '0'; + SIGNAL nlOOi0l : STD_LOGIC := '0'; + SIGNAL nlOOi0O : STD_LOGIC := '0'; + SIGNAL nlOOi1O : STD_LOGIC := '0'; + SIGNAL wire_nl01l_PRN : STD_LOGIC; + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_n0iOlO1995w1999w2000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_n0iOlO1988w1990w1992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_n1liO370w374w375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_n1liO363w365w367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_n1lliO2531w2535w2536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_n1lliO2524w2526w2528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nii1OO1458w1462w1463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nii1OO1451w1453w1455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nl0i1O922w926w927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nl0i1O915w917w919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nll1OOO4143w4147w4148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nll1OOO4136w4138w4140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nlO101O3607w3611w3612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nlO101O3600w3602w3604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nlOOi0O3069w3073w3074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_nlOOi0O3062w3064w3066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n0iOlO1995w1999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n0iOlO1995w1996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n0iOlO1988w1990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n1liO370w374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n1liO370w371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n1liO363w365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n1lliO2531w2535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n1lliO2531w2532w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_n1lliO2524w2526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nii1OO1458w1462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nii1OO1458w1459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nii1OO1451w1453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nl0i1O922w926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nl0i1O922w923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nl0i1O915w917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nll1OOO4143w4147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nll1OOO4143w4144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nll1OOO4136w4138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nlO101O3607w3611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nlO101O3607w3608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nlO101O3600w3602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nlOOi0O3069w3073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nlOOi0O3069w3070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_nlOOi0O3062w3064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n0iOlO1995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n0iOlO1988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1liO370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1liO363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1lliO2531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1lliO2524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nii1OO1458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nii1OO1451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nl0i1O922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nl0i1O915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nll1OOO4143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nll1OOO4136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlO101O3607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlO101O3600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlOOi0O3069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlOOi0O3062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n0i0iO2046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n0iOiO1991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n0iOli1989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n0iOll1994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n0iOlO2226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n110O421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1l0O366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1l10O2584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1lii364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1lil369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1liO612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1ll0O2527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1llii2525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1llil2530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_n1lliO2764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_ni0ilO1510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nii1lO1454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nii1Oi1452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nii1Ol1457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nii1OO1690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nl00OO918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nl0i1i916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nl0i1l921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nl0i1O1153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nl1lOO973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nll10lO4195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nll1OlO4139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nll1OOi4137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nll1OOl4142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nll1OOO4375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nllOiOO3658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlO101i3601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlO101l3606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlO101O3838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlO11OO3603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlOlO1O3122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlOOi0i3063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlOOi0l3068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlOOi0O3302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_nlOOi1O3065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_n0iOlO1988w1990w1992w1993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_n1liO363w365w367w368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_n1lliO2524w2526w2528w2529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_nii1OO1451w1453w1455w1456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_nl0i1O915w917w919w920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_nll1OOO4136w4138w4140w4141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_nlO101O3600w3602w3604w3605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l_w_lg_w_lg_w_lg_w_lg_nlOOi0O3062w3064w3066w3067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n000il : STD_LOGIC := '0'; + SIGNAL n000iO : STD_LOGIC := '0'; + SIGNAL n000li : STD_LOGIC := '0'; + SIGNAL n000ll : STD_LOGIC := '0'; + SIGNAL n000lO : STD_LOGIC := '0'; + SIGNAL n000Oi : STD_LOGIC := '0'; + SIGNAL n000Ol : STD_LOGIC := '0'; + SIGNAL n000OO : STD_LOGIC := '0'; + SIGNAL n00i0i : STD_LOGIC := '0'; + SIGNAL n00i0l : STD_LOGIC := '0'; + SIGNAL n00i0O : STD_LOGIC := '0'; + SIGNAL n00i1i : STD_LOGIC := '0'; + SIGNAL n00i1l : STD_LOGIC := '0'; + SIGNAL n00i1O : STD_LOGIC := '0'; + SIGNAL n00ili : STD_LOGIC := '0'; + SIGNAL n00iOi : STD_LOGIC := '0'; + SIGNAL n00iOl : STD_LOGIC := '0'; + SIGNAL n0110i : STD_LOGIC := '0'; + SIGNAL n0110l : STD_LOGIC := '0'; + SIGNAL n0110O : STD_LOGIC := '0'; + SIGNAL n0111i : STD_LOGIC := '0'; + SIGNAL n0111l : STD_LOGIC := '0'; + SIGNAL n0111O : STD_LOGIC := '0'; + SIGNAL n011ii : STD_LOGIC := '0'; + SIGNAL n011il : STD_LOGIC := '0'; + SIGNAL n011iO : STD_LOGIC := '0'; + SIGNAL n011li : STD_LOGIC := '0'; + SIGNAL n011ll : STD_LOGIC := '0'; + SIGNAL n011lO : STD_LOGIC := '0'; + SIGNAL n011Oi : STD_LOGIC := '0'; + SIGNAL n011Ol : STD_LOGIC := '0'; + SIGNAL n0i0i : STD_LOGIC := '0'; + SIGNAL n0i0ii : STD_LOGIC := '0'; + SIGNAL n0i0il : STD_LOGIC := '0'; + SIGNAL n0i0l : STD_LOGIC := '0'; + SIGNAL n0i0li : STD_LOGIC := '0'; + SIGNAL n0i0O : STD_LOGIC := '0'; + SIGNAL n0iili : STD_LOGIC := '0'; + SIGNAL n0iill : STD_LOGIC := '0'; + SIGNAL n0iilO : STD_LOGIC := '0'; + SIGNAL n0iiOi : STD_LOGIC := '0'; + SIGNAL n0iiOl : STD_LOGIC := '0'; + SIGNAL n0iiOO : STD_LOGIC := '0'; + SIGNAL n0il1i : STD_LOGIC := '0'; + SIGNAL n0iO0l : STD_LOGIC := '0'; + SIGNAL n0iO1l : STD_LOGIC := '0'; + SIGNAL n0iOOi : STD_LOGIC := '0'; + SIGNAL n0iOOl : STD_LOGIC := '0'; + SIGNAL n0l0i : STD_LOGIC := '0'; + SIGNAL n0l0l : STD_LOGIC := '0'; + SIGNAL n0l0O : STD_LOGIC := '0'; + SIGNAL n0l1l : STD_LOGIC := '0'; + SIGNAL n0l1O : STD_LOGIC := '0'; + SIGNAL n0lii : STD_LOGIC := '0'; + SIGNAL n0lil : STD_LOGIC := '0'; + SIGNAL n0liO : STD_LOGIC := '0'; + SIGNAL n0lli : STD_LOGIC := '0'; + SIGNAL n0llii : STD_LOGIC := '0'; + SIGNAL n0llil : STD_LOGIC := '0'; + SIGNAL n0lliO : STD_LOGIC := '0'; + SIGNAL n0lll : STD_LOGIC := '0'; + SIGNAL n0llO : STD_LOGIC := '0'; + SIGNAL n0lO0l : STD_LOGIC := '0'; + SIGNAL n0lO0O : STD_LOGIC := '0'; + SIGNAL n0lOi : STD_LOGIC := '0'; + SIGNAL n0lOii : STD_LOGIC := '0'; + SIGNAL n0lOil : STD_LOGIC := '0'; + SIGNAL n0lOiO : STD_LOGIC := '0'; + SIGNAL n0lOl : STD_LOGIC := '0'; + SIGNAL n0lOli : STD_LOGIC := '0'; + SIGNAL n0lOll : STD_LOGIC := '0'; + SIGNAL n0lOlO : STD_LOGIC := '0'; + SIGNAL n0lOO : STD_LOGIC := '0'; + SIGNAL n0lOOi : STD_LOGIC := '0'; + SIGNAL n0lOOl : STD_LOGIC := '0'; + SIGNAL n0lOOO : STD_LOGIC := '0'; + SIGNAL n0O00i : STD_LOGIC := '0'; + SIGNAL n0O00l : STD_LOGIC := '0'; + SIGNAL n0O00O : STD_LOGIC := '0'; + SIGNAL n0O01i : STD_LOGIC := '0'; + SIGNAL n0O01l : STD_LOGIC := '0'; + SIGNAL n0O01O : STD_LOGIC := '0'; + SIGNAL n0O0i : STD_LOGIC := '0'; + SIGNAL n0O0ii : STD_LOGIC := '0'; + SIGNAL n0O0il : STD_LOGIC := '0'; + SIGNAL n0O0iO : STD_LOGIC := '0'; + SIGNAL n0O0l : STD_LOGIC := '0'; + SIGNAL n0O0li : STD_LOGIC := '0'; + SIGNAL n0O0ll : STD_LOGIC := '0'; + SIGNAL n0O0lO : STD_LOGIC := '0'; + SIGNAL n0O0O : STD_LOGIC := '0'; + SIGNAL n0O0Oi : STD_LOGIC := '0'; + SIGNAL n0O0Ol : STD_LOGIC := '0'; + SIGNAL n0O0OO : STD_LOGIC := '0'; + SIGNAL n0O10i : STD_LOGIC := '0'; + SIGNAL n0O10l : STD_LOGIC := '0'; + SIGNAL n0O10O : STD_LOGIC := '0'; + SIGNAL n0O11i : STD_LOGIC := '0'; + SIGNAL n0O11l : STD_LOGIC := '0'; + SIGNAL n0O11O : STD_LOGIC := '0'; + SIGNAL n0O1i : STD_LOGIC := '0'; + SIGNAL n0O1ii : STD_LOGIC := '0'; + SIGNAL n0O1il : STD_LOGIC := '0'; + SIGNAL n0O1iO : STD_LOGIC := '0'; + SIGNAL n0O1l : STD_LOGIC := '0'; + SIGNAL n0O1li : STD_LOGIC := '0'; + SIGNAL n0O1ll : STD_LOGIC := '0'; + SIGNAL n0O1lO : STD_LOGIC := '0'; + SIGNAL n0O1O : STD_LOGIC := '0'; + SIGNAL n0O1Oi : STD_LOGIC := '0'; + SIGNAL n0O1Ol : STD_LOGIC := '0'; + SIGNAL n0O1OO : STD_LOGIC := '0'; + SIGNAL n0Oi1i : STD_LOGIC := '0'; + SIGNAL n0Oi1l : STD_LOGIC := '0'; + SIGNAL n0Oii : STD_LOGIC := '0'; + SIGNAL n0Oil : STD_LOGIC := '0'; + SIGNAL n0OiO : STD_LOGIC := '0'; + SIGNAL n0Oli : STD_LOGIC := '0'; + SIGNAL n0Oll : STD_LOGIC := '0'; + SIGNAL n0OlO : STD_LOGIC := '0'; + SIGNAL n0OOi : STD_LOGIC := '0'; + SIGNAL n0OOl : STD_LOGIC := '0'; + SIGNAL n0OOO : STD_LOGIC := '0'; + SIGNAL n10ii : STD_LOGIC := '0'; + SIGNAL n10il : STD_LOGIC := '0'; + SIGNAL n10iO : STD_LOGIC := '0'; + SIGNAL n10li : STD_LOGIC := '0'; + SIGNAL n10ll : STD_LOGIC := '0'; + SIGNAL n10lO : STD_LOGIC := '0'; + SIGNAL n10Oi : STD_LOGIC := '0'; + SIGNAL n1101i : STD_LOGIC := '0'; + SIGNAL n1101l : STD_LOGIC := '0'; + SIGNAL n1101O : STD_LOGIC := '0'; + SIGNAL n110i : STD_LOGIC := '0'; + SIGNAL n110l : STD_LOGIC := '0'; + SIGNAL n110Ol : STD_LOGIC := '0'; + SIGNAL n110OO : STD_LOGIC := '0'; + SIGNAL n11i0i : STD_LOGIC := '0'; + SIGNAL n11i0l : STD_LOGIC := '0'; + SIGNAL n11i0O : STD_LOGIC := '0'; + SIGNAL n11i1i : STD_LOGIC := '0'; + SIGNAL n11i1l : STD_LOGIC := '0'; + SIGNAL n11i1O : STD_LOGIC := '0'; + SIGNAL n11ii : STD_LOGIC := '0'; + SIGNAL n11iii : STD_LOGIC := '0'; + SIGNAL n11iil : STD_LOGIC := '0'; + SIGNAL n11iiO : STD_LOGIC := '0'; + SIGNAL n11ili : STD_LOGIC := '0'; + SIGNAL n11ill : STD_LOGIC := '0'; + SIGNAL n11ilO : STD_LOGIC := '0'; + SIGNAL n11iOi : STD_LOGIC := '0'; + SIGNAL n11iOl : STD_LOGIC := '0'; + SIGNAL n11iOO : STD_LOGIC := '0'; + SIGNAL n11l0i : STD_LOGIC := '0'; + SIGNAL n11l0l : STD_LOGIC := '0'; + SIGNAL n11l0O : STD_LOGIC := '0'; + SIGNAL n11l1i : STD_LOGIC := '0'; + SIGNAL n11l1l : STD_LOGIC := '0'; + SIGNAL n11l1O : STD_LOGIC := '0'; + SIGNAL n11lii : STD_LOGIC := '0'; + SIGNAL n11lil : STD_LOGIC := '0'; + SIGNAL n11liO : STD_LOGIC := '0'; + SIGNAL n11lli : STD_LOGIC := '0'; + SIGNAL n11lll : STD_LOGIC := '0'; + SIGNAL n11llO : STD_LOGIC := '0'; + SIGNAL n11lOi : STD_LOGIC := '0'; + SIGNAL n11lOl : STD_LOGIC := '0'; + SIGNAL n11lOO : STD_LOGIC := '0'; + SIGNAL n11O0i : STD_LOGIC := '0'; + SIGNAL n11O0l : STD_LOGIC := '0'; + SIGNAL n11O0O : STD_LOGIC := '0'; + SIGNAL n11O1i : STD_LOGIC := '0'; + SIGNAL n11O1l : STD_LOGIC := '0'; + SIGNAL n11O1O : STD_LOGIC := '0'; + SIGNAL n11Oii : STD_LOGIC := '0'; + SIGNAL n11Oil : STD_LOGIC := '0'; + SIGNAL n11OiO : STD_LOGIC := '0'; + SIGNAL n11Oli : STD_LOGIC := '0'; + SIGNAL n11Oll : STD_LOGIC := '0'; + SIGNAL n1i01i : STD_LOGIC := '0'; + SIGNAL n1i01l : STD_LOGIC := '0'; + SIGNAL n1i01O : STD_LOGIC := '0'; + SIGNAL n1i0ii : STD_LOGIC := '0'; + SIGNAL n1i0li : STD_LOGIC := '0'; + SIGNAL n1i0ll : STD_LOGIC := '0'; + SIGNAL n1i10l : STD_LOGIC := '0'; + SIGNAL n1i10O : STD_LOGIC := '0'; + SIGNAL n1i1ii : STD_LOGIC := '0'; + SIGNAL n1i1il : STD_LOGIC := '0'; + SIGNAL n1i1iO : STD_LOGIC := '0'; + SIGNAL n1i1li : STD_LOGIC := '0'; + SIGNAL n1i1ll : STD_LOGIC := '0'; + SIGNAL n1i1lO : STD_LOGIC := '0'; + SIGNAL n1i1Oi : STD_LOGIC := '0'; + SIGNAL n1i1Ol : STD_LOGIC := '0'; + SIGNAL n1i1OO : STD_LOGIC := '0'; + SIGNAL n1iOl : STD_LOGIC := '0'; + SIGNAL n1l0ii : STD_LOGIC := '0'; + SIGNAL n1l0il : STD_LOGIC := '0'; + SIGNAL n1l0iO : STD_LOGIC := '0'; + SIGNAL n1l0li : STD_LOGIC := '0'; + SIGNAL n1l0ll : STD_LOGIC := '0'; + SIGNAL n1l0lO : STD_LOGIC := '0'; + SIGNAL n1l0Oi : STD_LOGIC := '0'; + SIGNAL n1l10i : STD_LOGIC := '0'; + SIGNAL n1l10l : STD_LOGIC := '0'; + SIGNAL n1l1ii : STD_LOGIC := '0'; + SIGNAL n1l1l : STD_LOGIC := '0'; + SIGNAL n1liOl : STD_LOGIC := '0'; + SIGNAL n1ll1l : STD_LOGIC := '0'; + SIGNAL n1lli : STD_LOGIC := '0'; + SIGNAL n1lll : STD_LOGIC := '0'; + SIGNAL n1llli : STD_LOGIC := '0'; + SIGNAL n1llll : STD_LOGIC := '0'; + SIGNAL n1Oi0i : STD_LOGIC := '0'; + SIGNAL n1Oi0l : STD_LOGIC := '0'; + SIGNAL n1Oi0O : STD_LOGIC := '0'; + SIGNAL n1Ol0i : STD_LOGIC := '0'; + SIGNAL n1Ol0l : STD_LOGIC := '0'; + SIGNAL n1Ol0O : STD_LOGIC := '0'; + SIGNAL n1Ol1l : STD_LOGIC := '0'; + SIGNAL n1Ol1O : STD_LOGIC := '0'; + SIGNAL n1Olii : STD_LOGIC := '0'; + SIGNAL n1Olil : STD_LOGIC := '0'; + SIGNAL n1OliO : STD_LOGIC := '0'; + SIGNAL n1Olli : STD_LOGIC := '0'; + SIGNAL n1Olll : STD_LOGIC := '0'; + SIGNAL n1OllO : STD_LOGIC := '0'; + SIGNAL n1OlOi : STD_LOGIC := '0'; + SIGNAL n1OlOl : STD_LOGIC := '0'; + SIGNAL n1OlOO : STD_LOGIC := '0'; + SIGNAL n1OO0i : STD_LOGIC := '0'; + SIGNAL n1OO0l : STD_LOGIC := '0'; + SIGNAL n1OO0O : STD_LOGIC := '0'; + SIGNAL n1OO1i : STD_LOGIC := '0'; + SIGNAL n1OO1l : STD_LOGIC := '0'; + SIGNAL n1OO1O : STD_LOGIC := '0'; + SIGNAL n1OOii : STD_LOGIC := '0'; + SIGNAL n1OOil : STD_LOGIC := '0'; + SIGNAL n1OOiO : STD_LOGIC := '0'; + SIGNAL n1OOli : STD_LOGIC := '0'; + SIGNAL n1OOll : STD_LOGIC := '0'; + SIGNAL n1OOlO : STD_LOGIC := '0'; + SIGNAL n1OOOi : STD_LOGIC := '0'; + SIGNAL n1OOOl : STD_LOGIC := '0'; + SIGNAL n1OOOO : STD_LOGIC := '0'; + SIGNAL ni0ili : STD_LOGIC := '0'; + SIGNAL ni0ill : STD_LOGIC := '0'; + SIGNAL ni0iOi : STD_LOGIC := '0'; + SIGNAL ni0lOi : STD_LOGIC := '0'; + SIGNAL ni0lOl : STD_LOGIC := '0'; + SIGNAL ni0lOO : STD_LOGIC := '0'; + SIGNAL ni0O0i : STD_LOGIC := '0'; + SIGNAL ni0O1i : STD_LOGIC := '0'; + SIGNAL ni0O1l : STD_LOGIC := '0'; + SIGNAL ni0O1O : STD_LOGIC := '0'; + SIGNAL ni10i : STD_LOGIC := '0'; + SIGNAL ni10l : STD_LOGIC := '0'; + SIGNAL ni10O : STD_LOGIC := '0'; + SIGNAL ni11i : STD_LOGIC := '0'; + SIGNAL ni11l : STD_LOGIC := '0'; + SIGNAL ni11O : STD_LOGIC := '0'; + SIGNAL ni1ii : STD_LOGIC := '0'; + SIGNAL ni1il : STD_LOGIC := '0'; + SIGNAL ni1ill : STD_LOGIC := '0'; + SIGNAL ni1ilO : STD_LOGIC := '0'; + SIGNAL ni1iO : STD_LOGIC := '0'; + SIGNAL ni1iOi : STD_LOGIC := '0'; + SIGNAL ni1iOl : STD_LOGIC := '0'; + SIGNAL ni1iOO : STD_LOGIC := '0'; + SIGNAL ni1l0i : STD_LOGIC := '0'; + SIGNAL ni1l0l : STD_LOGIC := '0'; + SIGNAL ni1l0O : STD_LOGIC := '0'; + SIGNAL ni1l1i : STD_LOGIC := '0'; + SIGNAL ni1l1l : STD_LOGIC := '0'; + SIGNAL ni1l1O : STD_LOGIC := '0'; + SIGNAL ni1li : STD_LOGIC := '0'; + SIGNAL ni1lii : STD_LOGIC := '0'; + SIGNAL ni1lil : STD_LOGIC := '0'; + SIGNAL ni1liO : STD_LOGIC := '0'; + SIGNAL ni1ll : STD_LOGIC := '0'; + SIGNAL ni1lO : STD_LOGIC := '0'; + SIGNAL ni1lOi : STD_LOGIC := '0'; + SIGNAL ni1O1i : STD_LOGIC := '0'; + SIGNAL ni1O1l : STD_LOGIC := '0'; + SIGNAL ni1Oi : STD_LOGIC := '0'; + SIGNAL ni1Ol : STD_LOGIC := '0'; + SIGNAL nii01i : STD_LOGIC := '0'; + SIGNAL nii01l : STD_LOGIC := '0'; + SIGNAL nii10l : STD_LOGIC := '0'; + SIGNAL nii1il : STD_LOGIC := '0'; + SIGNAL niiOli : STD_LOGIC := '0'; + SIGNAL niiOll : STD_LOGIC := '0'; + SIGNAL niiOlO : STD_LOGIC := '0'; + SIGNAL nil00i : STD_LOGIC := '0'; + SIGNAL nil00l : STD_LOGIC := '0'; + SIGNAL nil00O : STD_LOGIC := '0'; + SIGNAL nil01i : STD_LOGIC := '0'; + SIGNAL nil01l : STD_LOGIC := '0'; + SIGNAL nil01O : STD_LOGIC := '0'; + SIGNAL nil0ii : STD_LOGIC := '0'; + SIGNAL nil0il : STD_LOGIC := '0'; + SIGNAL nil0iO : STD_LOGIC := '0'; + SIGNAL nil0li : STD_LOGIC := '0'; + SIGNAL nil0ll : STD_LOGIC := '0'; + SIGNAL nil0lO : STD_LOGIC := '0'; + SIGNAL nil0Oi : STD_LOGIC := '0'; + SIGNAL nil0Ol : STD_LOGIC := '0'; + SIGNAL nil0OO : STD_LOGIC := '0'; + SIGNAL nil1il : STD_LOGIC := '0'; + SIGNAL nil1iO : STD_LOGIC := '0'; + SIGNAL nil1li : STD_LOGIC := '0'; + SIGNAL nil1ll : STD_LOGIC := '0'; + SIGNAL nil1lO : STD_LOGIC := '0'; + SIGNAL nil1Oi : STD_LOGIC := '0'; + SIGNAL nil1Ol : STD_LOGIC := '0'; + SIGNAL nil1OO : STD_LOGIC := '0'; + SIGNAL nili0i : STD_LOGIC := '0'; + SIGNAL nili0l : STD_LOGIC := '0'; + SIGNAL nili0O : STD_LOGIC := '0'; + SIGNAL nili1i : STD_LOGIC := '0'; + SIGNAL nili1l : STD_LOGIC := '0'; + SIGNAL nili1O : STD_LOGIC := '0'; + SIGNAL niliii : STD_LOGIC := '0'; + SIGNAL niliil : STD_LOGIC := '0'; + SIGNAL niliiO : STD_LOGIC := '0'; + SIGNAL nilili : STD_LOGIC := '0'; + SIGNAL nilill : STD_LOGIC := '0'; + SIGNAL nililO : STD_LOGIC := '0'; + SIGNAL niliOi : STD_LOGIC := '0'; + SIGNAL niliOl : STD_LOGIC := '0'; + SIGNAL niliOO : STD_LOGIC := '0'; + SIGNAL nill0i : STD_LOGIC := '0'; + SIGNAL nill0l : STD_LOGIC := '0'; + SIGNAL nill1i : STD_LOGIC := '0'; + SIGNAL nill1l : STD_LOGIC := '0'; + SIGNAL nill1O : STD_LOGIC := '0'; + SIGNAL niOlOl : STD_LOGIC := '0'; + SIGNAL niOlOO : STD_LOGIC := '0'; + SIGNAL niOO0i : STD_LOGIC := '0'; + SIGNAL niOO0l : STD_LOGIC := '0'; + SIGNAL niOO0O : STD_LOGIC := '0'; + SIGNAL niOO1i : STD_LOGIC := '0'; + SIGNAL niOO1l : STD_LOGIC := '0'; + SIGNAL niOO1O : STD_LOGIC := '0'; + SIGNAL niOOii : STD_LOGIC := '0'; + SIGNAL niOOil : STD_LOGIC := '0'; + SIGNAL niOOiO : STD_LOGIC := '0'; + SIGNAL niOOli : STD_LOGIC := '0'; + SIGNAL niOOll : STD_LOGIC := '0'; + SIGNAL niOOlO : STD_LOGIC := '0'; + SIGNAL nl00il : STD_LOGIC := '0'; + SIGNAL nl00ll : STD_LOGIC := '0'; + SIGNAL nl010i : STD_LOGIC := '0'; + SIGNAL nl010l : STD_LOGIC := '0'; + SIGNAL nl010O : STD_LOGIC := '0'; + SIGNAL nl011i : STD_LOGIC := '0'; + SIGNAL nl011l : STD_LOGIC := '0'; + SIGNAL nl011O : STD_LOGIC := '0'; + SIGNAL nl01ii : STD_LOGIC := '0'; + SIGNAL nl0i0i : STD_LOGIC := '0'; + SIGNAL nl0i0l : STD_LOGIC := '0'; + SIGNAL nl0iO : STD_LOGIC := '0'; + SIGNAL nl0li : STD_LOGIC := '0'; + SIGNAL nl0ll : STD_LOGIC := '0'; + SIGNAL nl0lO : STD_LOGIC := '0'; + SIGNAL nl0Oi : STD_LOGIC := '0'; + SIGNAL nl0Ol : STD_LOGIC := '0'; + SIGNAL nl0OO : STD_LOGIC := '0'; + SIGNAL nl110i : STD_LOGIC := '0'; + SIGNAL nl110l : STD_LOGIC := '0'; + SIGNAL nl111i : STD_LOGIC := '0'; + SIGNAL nl1lOi : STD_LOGIC := '0'; + SIGNAL nl1lOl : STD_LOGIC := '0'; + SIGNAL nl1O1i : STD_LOGIC := '0'; + SIGNAL nli0i : STD_LOGIC := '0'; + SIGNAL nli0l : STD_LOGIC := '0'; + SIGNAL nli0ll : STD_LOGIC := '0'; + SIGNAL nli0lO : STD_LOGIC := '0'; + SIGNAL nli0O : STD_LOGIC := '0'; + SIGNAL nli0Oi : STD_LOGIC := '0'; + SIGNAL nli0Ol : STD_LOGIC := '0'; + SIGNAL nli0OO : STD_LOGIC := '0'; + SIGNAL nli1i : STD_LOGIC := '0'; + SIGNAL nli1l : STD_LOGIC := '0'; + SIGNAL nli1O : STD_LOGIC := '0'; + SIGNAL nli1Oi : STD_LOGIC := '0'; + SIGNAL nli1Ol : STD_LOGIC := '0'; + SIGNAL nli1OO : STD_LOGIC := '0'; + SIGNAL nlii0i : STD_LOGIC := '0'; + SIGNAL nlii0l : STD_LOGIC := '0'; + SIGNAL nlii0O : STD_LOGIC := '0'; + SIGNAL nlii1i : STD_LOGIC := '0'; + SIGNAL nlii1l : STD_LOGIC := '0'; + SIGNAL nlii1O : STD_LOGIC := '0'; + SIGNAL nliiii : STD_LOGIC := '0'; + SIGNAL nliiil : STD_LOGIC := '0'; + SIGNAL nliiiO : STD_LOGIC := '0'; + SIGNAL nliil : STD_LOGIC := '0'; + SIGNAL nliili : STD_LOGIC := '0'; + SIGNAL nliill : STD_LOGIC := '0'; + SIGNAL nliilO : STD_LOGIC := '0'; + SIGNAL nliiOi : STD_LOGIC := '0'; + SIGNAL nliiOl : STD_LOGIC := '0'; + SIGNAL nliiOO : STD_LOGIC := '0'; + SIGNAL nlil0i : STD_LOGIC := '0'; + SIGNAL nlil0l : STD_LOGIC := '0'; + SIGNAL nlil0O : STD_LOGIC := '0'; + SIGNAL nlil1i : STD_LOGIC := '0'; + SIGNAL nlil1l : STD_LOGIC := '0'; + SIGNAL nlil1O : STD_LOGIC := '0'; + SIGNAL nlilii : STD_LOGIC := '0'; + SIGNAL nlilil : STD_LOGIC := '0'; + SIGNAL nliliO : STD_LOGIC := '0'; + SIGNAL nlilli : STD_LOGIC := '0'; + SIGNAL nlilll : STD_LOGIC := '0'; + SIGNAL nlillO : STD_LOGIC := '0'; + SIGNAL nlilOi : STD_LOGIC := '0'; + SIGNAL nlilOl : STD_LOGIC := '0'; + SIGNAL nlilOO : STD_LOGIC := '0'; + SIGNAL nliO0i : STD_LOGIC := '0'; + SIGNAL nliO0l : STD_LOGIC := '0'; + SIGNAL nliO0O : STD_LOGIC := '0'; + SIGNAL nliO1i : STD_LOGIC := '0'; + SIGNAL nliO1l : STD_LOGIC := '0'; + SIGNAL nliO1O : STD_LOGIC := '0'; + SIGNAL nliOii : STD_LOGIC := '0'; + SIGNAL nliOil : STD_LOGIC := '0'; + SIGNAL nliOiOi : STD_LOGIC := '0'; + SIGNAL nliOl1i : STD_LOGIC := '0'; + SIGNAL nliOl1l : STD_LOGIC := '0'; + SIGNAL nll011i : STD_LOGIC := '0'; + SIGNAL nll011l : STD_LOGIC := '0'; + SIGNAL nll0lli : STD_LOGIC := '0'; + SIGNAL nll0lll : STD_LOGIC := '0'; + SIGNAL nll0llO : STD_LOGIC := '0'; + SIGNAL nll0Oil : STD_LOGIC := '0'; + SIGNAL nll0OiO : STD_LOGIC := '0'; + SIGNAL nll0Oli : STD_LOGIC := '0'; + SIGNAL nll0Oll : STD_LOGIC := '0'; + SIGNAL nll0OlO : STD_LOGIC := '0'; + SIGNAL nll0OOi : STD_LOGIC := '0'; + SIGNAL nll0OOl : STD_LOGIC := '0'; + SIGNAL nll0OOO : STD_LOGIC := '0'; + SIGNAL nll10li : STD_LOGIC := '0'; + SIGNAL nll10ll : STD_LOGIC := '0'; + SIGNAL nll10Oi : STD_LOGIC := '0'; + SIGNAL nll1iOi : STD_LOGIC := '0'; + SIGNAL nll1iOl : STD_LOGIC := '0'; + SIGNAL nll1iOO : STD_LOGIC := '0'; + SIGNAL nll1l0i : STD_LOGIC := '0'; + SIGNAL nll1l1i : STD_LOGIC := '0'; + SIGNAL nll1l1l : STD_LOGIC := '0'; + SIGNAL nll1l1O : STD_LOGIC := '0'; + SIGNAL nll1O0l : STD_LOGIC := '0'; + SIGNAL nll1Oil : STD_LOGIC := '0'; + SIGNAL nlli00i : STD_LOGIC := '0'; + SIGNAL nlli00l : STD_LOGIC := '0'; + SIGNAL nlli00O : STD_LOGIC := '0'; + SIGNAL nlli01i : STD_LOGIC := '0'; + SIGNAL nlli01l : STD_LOGIC := '0'; + SIGNAL nlli01O : STD_LOGIC := '0'; + SIGNAL nlli0ii : STD_LOGIC := '0'; + SIGNAL nlli0il : STD_LOGIC := '0'; + SIGNAL nlli0iO : STD_LOGIC := '0'; + SIGNAL nlli0li : STD_LOGIC := '0'; + SIGNAL nlli0ll : STD_LOGIC := '0'; + SIGNAL nlli0lO : STD_LOGIC := '0'; + SIGNAL nlli0Oi : STD_LOGIC := '0'; + SIGNAL nlli0Ol : STD_LOGIC := '0'; + SIGNAL nlli0OO : STD_LOGIC := '0'; + SIGNAL nlli10i : STD_LOGIC := '0'; + SIGNAL nlli10l : STD_LOGIC := '0'; + SIGNAL nlli10O : STD_LOGIC := '0'; + SIGNAL nlli11i : STD_LOGIC := '0'; + SIGNAL nlli11l : STD_LOGIC := '0'; + SIGNAL nlli11O : STD_LOGIC := '0'; + SIGNAL nlli1ii : STD_LOGIC := '0'; + SIGNAL nlli1il : STD_LOGIC := '0'; + SIGNAL nlli1iO : STD_LOGIC := '0'; + SIGNAL nlli1li : STD_LOGIC := '0'; + SIGNAL nlli1ll : STD_LOGIC := '0'; + SIGNAL nlli1lO : STD_LOGIC := '0'; + SIGNAL nlli1Oi : STD_LOGIC := '0'; + SIGNAL nlli1Ol : STD_LOGIC := '0'; + SIGNAL nlli1OO : STD_LOGIC := '0'; + SIGNAL nllii0i : STD_LOGIC := '0'; + SIGNAL nllii0l : STD_LOGIC := '0'; + SIGNAL nllii1i : STD_LOGIC := '0'; + SIGNAL nllii1l : STD_LOGIC := '0'; + SIGNAL nllii1O : STD_LOGIC := '0'; + SIGNAL nllliOl : STD_LOGIC := '0'; + SIGNAL nllliOO : STD_LOGIC := '0'; + SIGNAL nllll0i : STD_LOGIC := '0'; + SIGNAL nllll0l : STD_LOGIC := '0'; + SIGNAL nllll0O : STD_LOGIC := '0'; + SIGNAL nllll1i : STD_LOGIC := '0'; + SIGNAL nllll1l : STD_LOGIC := '0'; + SIGNAL nllll1O : STD_LOGIC := '0'; + SIGNAL nllllii : STD_LOGIC := '0'; + SIGNAL nllllil : STD_LOGIC := '0'; + SIGNAL nlllliO : STD_LOGIC := '0'; + SIGNAL nllllli : STD_LOGIC := '0'; + SIGNAL nllllll : STD_LOGIC := '0'; + SIGNAL nlllllO : STD_LOGIC := '0'; + SIGNAL nlllO0i : STD_LOGIC := '0'; + SIGNAL nlllO0l : STD_LOGIC := '0'; + SIGNAL nlllO1i : STD_LOGIC := '0'; + SIGNAL nllOiOi : STD_LOGIC := '0'; + SIGNAL nllOiOl : STD_LOGIC := '0'; + SIGNAL nllOl1i : STD_LOGIC := '0'; + SIGNAL nllOO0i : STD_LOGIC := '0'; + SIGNAL nllOO0l : STD_LOGIC := '0'; + SIGNAL nllOO0O : STD_LOGIC := '0'; + SIGNAL nllOO1i : STD_LOGIC := '0'; + SIGNAL nllOO1l : STD_LOGIC := '0'; + SIGNAL nllOO1O : STD_LOGIC := '0'; + SIGNAL nllOOii : STD_LOGIC := '0'; + SIGNAL nlO000i : STD_LOGIC := '0'; + SIGNAL nlO000l : STD_LOGIC := '0'; + SIGNAL nlO000O : STD_LOGIC := '0'; + SIGNAL nlO001i : STD_LOGIC := '0'; + SIGNAL nlO001l : STD_LOGIC := '0'; + SIGNAL nlO001O : STD_LOGIC := '0'; + SIGNAL nlO00ii : STD_LOGIC := '0'; + SIGNAL nlO00il : STD_LOGIC := '0'; + SIGNAL nlO00iO : STD_LOGIC := '0'; + SIGNAL nlO00l : STD_LOGIC := '0'; + SIGNAL nlO00li : STD_LOGIC := '0'; + SIGNAL nlO00ll : STD_LOGIC := '0'; + SIGNAL nlO00lO : STD_LOGIC := '0'; + SIGNAL nlO00Oi : STD_LOGIC := '0'; + SIGNAL nlO00Ol : STD_LOGIC := '0'; + SIGNAL nlO00OO : STD_LOGIC := '0'; + SIGNAL nlO01ll : STD_LOGIC := '0'; + SIGNAL nlO01lO : STD_LOGIC := '0'; + SIGNAL nlO01Oi : STD_LOGIC := '0'; + SIGNAL nlO01Ol : STD_LOGIC := '0'; + SIGNAL nlO01OO : STD_LOGIC := '0'; + SIGNAL nlO0i0i : STD_LOGIC := '0'; + SIGNAL nlO0i0l : STD_LOGIC := '0'; + SIGNAL nlO0i0O : STD_LOGIC := '0'; + SIGNAL nlO0i1i : STD_LOGIC := '0'; + SIGNAL nlO0i1l : STD_LOGIC := '0'; + SIGNAL nlO0i1O : STD_LOGIC := '0'; + SIGNAL nlO0iii : STD_LOGIC := '0'; + SIGNAL nlO0iil : STD_LOGIC := '0'; + SIGNAL nlO0iiO : STD_LOGIC := '0'; + SIGNAL nlO0ili : STD_LOGIC := '0'; + SIGNAL nlO0ill : STD_LOGIC := '0'; + SIGNAL nlO0ilO : STD_LOGIC := '0'; + SIGNAL nlO0iO : STD_LOGIC := '0'; + SIGNAL nlO0iOi : STD_LOGIC := '0'; + SIGNAL nlO0iOl : STD_LOGIC := '0'; + SIGNAL nlO0iOO : STD_LOGIC := '0'; + SIGNAL nlO0l0i : STD_LOGIC := '0'; + SIGNAL nlO0l0l : STD_LOGIC := '0'; + SIGNAL nlO0l0O : STD_LOGIC := '0'; + SIGNAL nlO0l1i : STD_LOGIC := '0'; + SIGNAL nlO0l1l : STD_LOGIC := '0'; + SIGNAL nlO0l1O : STD_LOGIC := '0'; + SIGNAL nlO0li : STD_LOGIC := '0'; + SIGNAL nlO0lii : STD_LOGIC := '0'; + SIGNAL nlO0lil : STD_LOGIC := '0'; + SIGNAL nlO100i : STD_LOGIC := '0'; + SIGNAL nlO100l : STD_LOGIC := '0'; + SIGNAL nlO10i : STD_LOGIC := '0'; + SIGNAL nlO10l : STD_LOGIC := '0'; + SIGNAL nlO10O : STD_LOGIC := '0'; + SIGNAL nlO11il : STD_LOGIC := '0'; + SIGNAL nlO11l : STD_LOGIC := '0'; + SIGNAL nlO11ll : STD_LOGIC := '0'; + SIGNAL nlO11O : STD_LOGIC := '0'; + SIGNAL nlO1ii : STD_LOGIC := '0'; + SIGNAL nlO1il : STD_LOGIC := '0'; + SIGNAL nlO1iO : STD_LOGIC := '0'; + SIGNAL nlO1li : STD_LOGIC := '0'; + SIGNAL nlO1ll : STD_LOGIC := '0'; + SIGNAL nlO1lO : STD_LOGIC := '0'; + SIGNAL nlO1Oi : STD_LOGIC := '0'; + SIGNAL nlO1Ol : STD_LOGIC := '0'; + SIGNAL nlO1OO : STD_LOGIC := '0'; + SIGNAL nlO1OOi : STD_LOGIC := '0'; + SIGNAL nlO1OOl : STD_LOGIC := '0'; + SIGNAL nlO1OOO : STD_LOGIC := '0'; + SIGNAL nlOiO0i : STD_LOGIC := '0'; + SIGNAL nlOiO0l : STD_LOGIC := '0'; + SIGNAL nlOiO0O : STD_LOGIC := '0'; + SIGNAL nlOiO1l : STD_LOGIC := '0'; + SIGNAL nlOiO1O : STD_LOGIC := '0'; + SIGNAL nlOiOii : STD_LOGIC := '0'; + SIGNAL nlOiOil : STD_LOGIC := '0'; + SIGNAL nlOiOiO : STD_LOGIC := '0'; + SIGNAL nlOiOli : STD_LOGIC := '0'; + SIGNAL nlOiOll : STD_LOGIC := '0'; + SIGNAL nlOiOlO : STD_LOGIC := '0'; + SIGNAL nlOiOOi : STD_LOGIC := '0'; + SIGNAL nlOiOOl : STD_LOGIC := '0'; + SIGNAL nlOiOOO : STD_LOGIC := '0'; + SIGNAL nlOl10i : STD_LOGIC := '0'; + SIGNAL nlOl1ii : STD_LOGIC := '0'; + SIGNAL nlOl1il : STD_LOGIC := '0'; + SIGNAL nlOlO0i : STD_LOGIC := '0'; + SIGNAL nlOlO1i : STD_LOGIC := '0'; + SIGNAL nlOlO1l : STD_LOGIC := '0'; + SIGNAL nlOO0ll : STD_LOGIC := '0'; + SIGNAL nlOO0Ol : STD_LOGIC := '0'; + SIGNAL nlOO10i : STD_LOGIC := '0'; + SIGNAL nlOO10l : STD_LOGIC := '0'; + SIGNAL nlOO10O : STD_LOGIC := '0'; + SIGNAL nlOO1ii : STD_LOGIC := '0'; + SIGNAL nlOO1il : STD_LOGIC := '0'; + SIGNAL nlOO1iO : STD_LOGIC := '0'; + SIGNAL nlOO1li : STD_LOGIC := '0'; + SIGNAL nlOOiii : STD_LOGIC := '0'; + SIGNAL nlOOiil : STD_LOGIC := '0'; + SIGNAL wire_nliii_CLRN : STD_LOGIC; + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w2757w2758w2759w2760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w2117w2118w2120w2132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w494w496w508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w3193w3194w3196w3208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w3295w3296w3297w3298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w2655w2656w2658w2670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w2219w2220w2221w2222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w1581w1582w1584w1596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w1683w1684w1685w1686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w606w607w608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w1044w1045w1047w1059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w4266w4267w4269w4281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w4368w4369w4370w4371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w3729w3730w3732w3744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w1146w1147w1148w1149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w3831w3832w3833w3834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2740w2741w2742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3278w3279w3280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2202w2203w2204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1666w1667w1668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w589w590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w4351w4352w4353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1129w1130w1131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3814w3815w3816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2757w2758w2759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2747w2749w2750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2117w2118w2120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w494w496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3193w3194w3196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3295w3296w3297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3285w3287w3288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2655w2656w2658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2219w2220w2221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w2209w2211w2212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1581w1582w1584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1683w1684w1685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1673w1675w1676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w606w607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w597w598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1044w1045w1047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w4266w4267w4269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w4368w4369w4370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w4358w4360w4361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3729w3730w3732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1146w1147w1148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w1136w1138w1139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3831w3832w3833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w3821w3823w3824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2740w2741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2753w2754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3278w3279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3291w3292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2202w2203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2215w2216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1666w1667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1679w1680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w4351w4352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w4364w4365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1129w1130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1142w1143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3814w3815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3827w3828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2725w2726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2757w2758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2747w2749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2716w2717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2117w2118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3193w3194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3263w3264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3295w3296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3285w3287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3254w3255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2655w2656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2187w2188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2219w2220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2209w2211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w2178w2179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1581w1582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1651w1652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1683w1684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1673w1675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1642w1643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1044w1045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w4266w4267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w4336w4337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w4368w4369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w4358w4360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w4327w4328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3729w3730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1114w1115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1146w1147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1136w1138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w1105w1106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3799w3800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3831w3832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3821w3823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w3790w3791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w587w588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0lll526w527w528w529w530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0Oli473w487w489w491w493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0Oli473w474w475w476w477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w2178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w569w571w572w573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w562w563w564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w4327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w1105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w3790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w2739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w2705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0liO510w511w513w514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lOlO2134w2135w2137w2138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1ll2081w2082w2084w2085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oil456w457w459w460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n11i0O3210w3211w3213w3214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n11l0l3157w3158w3160w3161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w3277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w3243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OliO2672w2673w2675w2676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOil2619w2620w2622w2623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w2201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w2167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nil0Ol1545w1546w1548w1549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nil1OO1598w1599w1601w1602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w1665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w1631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlii1O1061w1062w1064w1065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil1l1008w1009w1011w1012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nll0OOO4283w4284w4286w4287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli1Ol4230w4231w4233w4234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w4350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w4316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO001O3746w3747w3749w3750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i1l3693w3694w3696w3697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w1128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w1094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w3813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w3779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2721w2723w2724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2713w2744w2746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2713w2714w2715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lll526w527w528w529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lOOl2150w2151w2152w2153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1Oi2097w2111w2113w2115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1Oi2097w2098w2099w2100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oli473w487w489w491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oli473w474w475w476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n11iil3226w3227w3228w3229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n11lii3173w3187w3189w3191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n11lii3173w3174w3175w3176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3259w3261w3262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3251w3282w3284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3251w3252w3253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1Olll2688w2689w2690w2691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOli2635w2649w2651w2653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOli2635w2636w2637w2638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2183w2185w2186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2175w2206w2208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2175w2176w2177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nil01l1614w1615w1616w1617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nili1i1561w1575w1577w1579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nili1i1561w1562w1563w1564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1647w1649w1650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1639w1670w1672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1639w1640w1641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlii0l1077w1078w1079w1080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w569w571w572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w561w562w563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil0i1024w1038w1040w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil0i1024w1025w1026w1027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli01i4246w4260w4262w4264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli01i4246w4247w4248w4249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli11l4299w4300w4301w4302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4332w4334w4335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4324w4355w4357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4324w4325w4326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO000l3762w3763w3764w3765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i0i3709w3723w3725w3727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i0i3709w3710w3711w3712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1110w1112w1113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1102w1133w1135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1102w1103w1104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3795w3797w3798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3818w3820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3788w3789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n00i0O2730w2731w2732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0liO510w511w513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0lOlO2134w2135w2137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0O1ll2081w2082w2084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0Oil456w457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n11i0O3210w3211w3213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n11l0l3157w3158w3160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1i01O3268w3269w3270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1OliO2672w2673w2675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1OOil2619w2620w2622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_ni1liO2192w2193w2194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nil0Ol1545w1546w1548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nil1OO1598w1599w1601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_niOOlO1656w1657w1658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlii1O1061w1062w1064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nliil550w551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nliil578w579w580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlil1l1008w1009w1011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nll0OOO4283w4284w4286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlli1Ol4230w4231w4233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlllllO4341w4342w4343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO001O3746w3747w3749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO0i1l3693w3694w3696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO1OO1119w1120w1121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3804w3805w3806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2721w2723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2713w2744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2713w2714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0lll526w527w528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0lOOl2150w2151w2152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0O1Oi2097w2111w2113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0O1Oi2097w2098w2099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0Oli473w487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n0Oli473w474w475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n11iil3226w3227w3228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n11lii3173w3187w3189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n11lii3173w3174w3175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3259w3261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3251w3282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3251w3252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1Olll2688w2689w2690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1OOli2635w2649w2651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_n1OOli2635w2636w2637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2183w2185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2175w2206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2175w2176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nil01l1614w1615w1616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nili1i1561w1575w1577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nili1i1561w1562w1563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1647w1649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1639w1670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1639w1640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlii0l1077w1078w1079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nliil560w569w571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nliil560w561w592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nliil560w561w562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlil0i1024w1038w1040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlil0i1024w1025w1026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlli01i4246w4260w4262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlli01i4246w4247w4248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlli11l4299w4300w4301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4332w4334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4324w4355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4324w4325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO000l3762w3763w3764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO0i0i3709w3723w3725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO0i0i3709w3710w3711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1110w1112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1102w1133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1102w1103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3795w3797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n00i0O2702w2703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n00i0O2730w2731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0iiOl2055w2056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0liO510w511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0lOlO2134w2135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0O1ll2081w2082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0Oil456w457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n10ll430w431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n11i0O3210w3211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n11l0l3157w3158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1i01O3240w3241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1i01O3268w3269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1l0ll2593w2594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1OliO2672w2673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1OOil2619w2620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_ni0O1l1519w1520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_ni1liO2164w2165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_ni1liO2192w2193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nil0Ol1545w1546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nil1OO1598w1599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_niOOlO1628w1629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_niOOlO1656w1657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nl010l982w983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlii1O1061w1062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nliil550w551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nliil578w579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlil1l1008w1009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nll0OOO4283w4284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nll1l1l4204w4205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlli1Ol4230w4231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlllllO4313w4314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlllllO4341w4342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nllOO0l3667w3668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO001O3746w3747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO0i1l3693w3694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO1OO1091w1092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO1OO1119w1120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlOiOOO3776w3777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlOiOOO3804w3805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlOO1il3131w3132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n00i0O2712w2721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n00i0O2712w2713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0lll526w527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0lOOl2150w2151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0O1Oi2097w2111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0O1Oi2097w2098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0Oli473w487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n0Oli473w474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n11iil3226w3227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n11lii3173w3187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n11lii3173w3174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1i01O3250w3259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1i01O3250w3251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1Olll2688w2689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1OOli2635w2649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_n1OOli2635w2636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_ni1liO2174w2183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_ni1liO2174w2175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nil01l1614w1615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nili1i1561w1575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nili1i1561w1562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_niOOlO1638w1647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_niOOlO1638w1639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nl0Ol282w283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlii0l1077w1078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nliil560w569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nliil560w561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlil0i1024w1038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlil0i1024w1025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlli01i4246w4260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlli01i4246w4247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlli11l4299w4300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlllllO4323w4332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlllllO4323w4324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO000l3762w3763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO0i0i3709w3723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO0i0i3709w3710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO1OO1101w1110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlO1OO1101w1102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlOiOOO3786w3795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_w_lg_nlOiOOO3786w3787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i0O2702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i0O2730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0iiOl2055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0liO510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0lOlO2134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1ll2081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0Oil456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n10ll430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11i0O3210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11l0l3157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i01O3240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i01O3268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1l0ll2593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OliO2672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OOil2619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni0O1l1519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1liO2164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1liO2192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0Ol1545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil1OO1598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOlO1628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOlO1656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl010l982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl0Oi294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlii1O1061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliil550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliil578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlil1l1008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nll0OOO4283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nll1l1l4204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1Ol4230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlllllO4313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlllllO4341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllOO0l3667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO001O3746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO0i1l3693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1OO1091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1OO1119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOOO3776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOOO3804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOO1il3131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n000ll2557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n000Oi2453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n000Ol2709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n000OO2707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i0i2722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i0l2701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i0O2712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i1i2748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i1l2733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00i1O2745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n00ili2237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0iilO2054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0iiOi2059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0iO0l2011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0l0O512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0l1O515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0lll526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0lO0O2139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0lOiO2136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0lOOl2150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O0i495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O0l458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O0O492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O10l2086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O10O2121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1ii2119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1il2083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1iO2116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1l461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1li2114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1ll2112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1lO2110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1O497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0O1Oi2097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0Oii490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0Oil488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0OiO486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n0Oli473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n10iO429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n10li434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n110OO3215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11i1O3212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11iil3226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11iOl3162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11iOO3197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11l0i3190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11l0l3188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11l0O3186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11l1i3195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11l1l3159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11l1O3192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n11lii3173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i01i3260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i01l3239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i01O3250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i0ii2775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i1il3095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i1li2991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i1ll3247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i1lO3245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i1Oi3286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i1Ol3271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1i1OO3283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1l0iO2592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1l0li2597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1l1l386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1ll1l2549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1Ol0O2674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1Ol1O2677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1Olll2688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OO0i2657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OO0l2621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OO0O2654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OO1l2624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OO1O2659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OOii2652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OOil2650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OOiO2648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_n1OOli2635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni0lOO1518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni0O1i1523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1iOl2019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1l0i2210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1l0l2195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1l0O2207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1l1i1917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1l1l2171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1l1O2169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1lii2184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1lil2163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1liO2174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_ni1lOi1701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nii1il1475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil01l1614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0il1550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0iO1585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0li1583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0ll1547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0lO1580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0Oi1578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0Ol1576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil0OO1574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil1iO1603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nil1lO1600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nili1i1561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOO0i1380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOO0l1635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOO0O1633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOO1l1483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOii1674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOil1659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOiO1671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOli1648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOll1627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_niOOlO1638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl00ll938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl010i986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl011O981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl0lO394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl0Ol282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl0OO557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nl111i1164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli0i593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli0l570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli0lO1066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli0O549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli0OO1063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli1i555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli1l596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nli1O581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlii0l1077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliil560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliill1013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliilO1048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliiOi1046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliiOl1010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliiOO1043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlil0i1024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlil1i1041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlil1l1039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlil1O1037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nliOiOi4386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nll0OiO4288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nll0OlO4285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nll1iOO4203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nll1l1i4208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nll1Oil4160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli01i4246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli11l4299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1il4235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1iO4270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1li4268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1ll4232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1lO4265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1Oi4263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1Ol4261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlli1OO4259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllll0i4065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllll0l4320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllll0O4318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllll1l4168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllllii4359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllllil4344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlllliO4356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllllli4333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllllll4312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlllllO4323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlllO1i3849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllOO0i3671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nllOO1O3666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO000l3762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO00l627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO00ll3698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO00lO3733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO00Oi3731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO00Ol3695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO00OO3728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO01lO3751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO01OO3748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO0i0i3709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO0i1i3726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO0i1l3724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO0i1O3722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO10l946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO11ll3623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1ii844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1il1098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1iO1096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1li1137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1ll1122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1lO1134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1Oi1111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1Ol1090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlO1OO1101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiO0l3631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOii3529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOil3783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOiO3781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOli3822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOll3807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOlO3819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOOi3796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOOl3775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOiOOO3786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOl10i3313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOO0Ol3087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOO10O3130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliii_w_lg_nlOO1ii3135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nll1OiO : STD_LOGIC := '0'; + SIGNAL nll1Oll : STD_LOGIC := '0'; + SIGNAL wire_nll1Oli_CLRN : STD_LOGIC; + SIGNAL n00iii : STD_LOGIC := '0'; + SIGNAL n1i00i : STD_LOGIC := '0'; + SIGNAL ni1lli : STD_LOGIC := '0'; + SIGNAL niOOOi : STD_LOGIC := '0'; + SIGNAL nliOili : STD_LOGIC := '0'; + SIGNAL nllllOi : STD_LOGIC := '0'; + SIGNAL nlO01l : STD_LOGIC := '0'; + SIGNAL nlOl11i : STD_LOGIC := '0'; + SIGNAL wire_nlO01i_PRN : STD_LOGIC; + SIGNAL n00ilO : STD_LOGIC := '0'; + SIGNAL n1i0iO : STD_LOGIC := '0'; + SIGNAL ni1lOO : STD_LOGIC := '0'; + SIGNAL nl111O : STD_LOGIC := '0'; + SIGNAL nliOiOO : STD_LOGIC := '0'; + SIGNAL nlllO1O : STD_LOGIC := '0'; + SIGNAL nlO0il : STD_LOGIC := '0'; + SIGNAL nlOl10O : STD_LOGIC := '0'; + SIGNAL wire_nlO0ii_CLRN : STD_LOGIC; + SIGNAL wire_nlO0ii_PRN : STD_LOGIC; + SIGNAL n00ill : STD_LOGIC := '0'; + SIGNAL n00iOO : STD_LOGIC := '0'; + SIGNAL n00l1i : STD_LOGIC := '0'; + SIGNAL n1i0il : STD_LOGIC := '0'; + SIGNAL n1i0lO : STD_LOGIC := '0'; + SIGNAL n1i0Oi : STD_LOGIC := '0'; + SIGNAL ni1lOl : STD_LOGIC := '0'; + SIGNAL ni1O0i : STD_LOGIC := '0'; + SIGNAL ni1O1O : STD_LOGIC := '0'; + SIGNAL nl110O : STD_LOGIC := '0'; + SIGNAL nl111l : STD_LOGIC := '0'; + SIGNAL nl11ii : STD_LOGIC := '0'; + SIGNAL nliOiOl : STD_LOGIC := '0'; + SIGNAL nliOl0i : STD_LOGIC := '0'; + SIGNAL nliOl1O : STD_LOGIC := '0'; + SIGNAL nlllO0O : STD_LOGIC := '0'; + SIGNAL nlllO1l : STD_LOGIC := '0'; + SIGNAL nlllOii : STD_LOGIC := '0'; + SIGNAL nlO00O : STD_LOGIC := '0'; + SIGNAL nlO0ll : STD_LOGIC := '0'; + SIGNAL nlO0Oi : STD_LOGIC := '0'; + SIGNAL nlOl10l : STD_LOGIC := '0'; + SIGNAL nlOl1iO : STD_LOGIC := '0'; + SIGNAL nlOl1li : STD_LOGIC := '0'; + SIGNAL wire_nlO0lO_CLRN : STD_LOGIC; + SIGNAL wire_nlO0lO_w_lg_n00iOO2233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0lO_w_lg_n1i0lO2771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0lO_w_lg_ni1O1O1697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0lO_w_lg_nl110O1160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0lO_w_lg_nliOl1O4382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0lO_w_lg_nlllO0O3845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0lO_w_lg_nlO0ll619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0lO_w_lg_nlOl1iO3309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlO11lO : STD_LOGIC := '0'; + SIGNAL nlO11Ol : STD_LOGIC := '0'; + SIGNAL wire_nlO11Oi_PRN : STD_LOGIC; + SIGNAL nlOO0OO : STD_LOGIC := '0'; + SIGNAL nlOOi1l : STD_LOGIC := '0'; + SIGNAL wire_nlOOi1i_CLRN : STD_LOGIC; + SIGNAL wire_nlOOi1i_PRN : STD_LOGIC; + SIGNAL wire_n0001i_dataout : STD_LOGIC; + SIGNAL wire_n0001O_dataout : STD_LOGIC; + SIGNAL wire_n0010i_dataout : STD_LOGIC; + SIGNAL wire_n0010l_dataout : STD_LOGIC; + SIGNAL wire_n0010O_dataout : STD_LOGIC; + SIGNAL wire_n0011i_dataout : STD_LOGIC; + SIGNAL wire_n0011O_dataout : STD_LOGIC; + SIGNAL wire_n001i_dataout : STD_LOGIC; + SIGNAL wire_n001ii_dataout : STD_LOGIC; + SIGNAL wire_n001il_dataout : STD_LOGIC; + SIGNAL wire_n001iO_dataout : STD_LOGIC; + SIGNAL wire_n001l_dataout : STD_LOGIC; + SIGNAL wire_n001ll_dataout : STD_LOGIC; + SIGNAL wire_n001lO_dataout : STD_LOGIC; + SIGNAL wire_n001O_dataout : STD_LOGIC; + SIGNAL wire_n001Oi_dataout : STD_LOGIC; + SIGNAL wire_n001Ol_dataout : STD_LOGIC; + SIGNAL wire_n001OO_dataout : STD_LOGIC; + SIGNAL wire_n00iil_dataout : STD_LOGIC; + SIGNAL wire_n00l0l_dataout : STD_LOGIC; + SIGNAL wire_n00l1l_dataout : STD_LOGIC; + SIGNAL wire_n0100i_dataout : STD_LOGIC; + SIGNAL wire_n0100l_dataout : STD_LOGIC; + SIGNAL wire_n0100O_dataout : STD_LOGIC; + SIGNAL wire_n0101i_dataout : STD_LOGIC; + SIGNAL wire_n0101l_dataout : STD_LOGIC; + SIGNAL wire_n0101O_dataout : STD_LOGIC; + SIGNAL wire_n010ii_dataout : STD_LOGIC; + SIGNAL wire_n010il_dataout : STD_LOGIC; + SIGNAL wire_n010iO_dataout : STD_LOGIC; + SIGNAL wire_n010li_dataout : STD_LOGIC; + SIGNAL wire_n010ll_dataout : STD_LOGIC; + SIGNAL wire_n010lO_dataout : STD_LOGIC; + SIGNAL wire_n010Oi_dataout : STD_LOGIC; + SIGNAL wire_n010Ol_dataout : STD_LOGIC; + SIGNAL wire_n010OO_dataout : STD_LOGIC; + SIGNAL wire_n01i0i_dataout : STD_LOGIC; + SIGNAL wire_n01i0l_dataout : STD_LOGIC; + SIGNAL wire_n01i0O_dataout : STD_LOGIC; + SIGNAL wire_n01i1i_dataout : STD_LOGIC; + SIGNAL wire_n01i1l_dataout : STD_LOGIC; + SIGNAL wire_n01i1O_dataout : STD_LOGIC; + SIGNAL wire_n01ii_dataout : STD_LOGIC; + SIGNAL wire_n01iii_dataout : STD_LOGIC; + SIGNAL wire_n01iiO_dataout : STD_LOGIC; + SIGNAL wire_n01il_dataout : STD_LOGIC; + SIGNAL wire_n01ili_dataout : STD_LOGIC; + SIGNAL wire_n01ill_dataout : STD_LOGIC; + SIGNAL wire_n01ilO_dataout : STD_LOGIC; + SIGNAL wire_n01iO_dataout : STD_LOGIC; + SIGNAL wire_n01iOi_dataout : STD_LOGIC; + SIGNAL wire_n01iOl_dataout : STD_LOGIC; + SIGNAL wire_n01iOO_dataout : STD_LOGIC; + SIGNAL wire_n01l0i_dataout : STD_LOGIC; + SIGNAL wire_n01l0l_dataout : STD_LOGIC; + SIGNAL wire_n01l0O_dataout : STD_LOGIC; + SIGNAL wire_n01l1i_dataout : STD_LOGIC; + SIGNAL wire_n01l1l_dataout : STD_LOGIC; + SIGNAL wire_n01l1O_dataout : STD_LOGIC; + SIGNAL wire_n01li_dataout : STD_LOGIC; + SIGNAL wire_n01lii_dataout : STD_LOGIC; + SIGNAL wire_n01lil_dataout : STD_LOGIC; + SIGNAL wire_n01liO_dataout : STD_LOGIC; + SIGNAL wire_n01ll_dataout : STD_LOGIC; + SIGNAL wire_n01lli_dataout : STD_LOGIC; + SIGNAL wire_n01lll_dataout : STD_LOGIC; + SIGNAL wire_n01llO_dataout : STD_LOGIC; + SIGNAL wire_n01lO_dataout : STD_LOGIC; + SIGNAL wire_n01lOi_dataout : STD_LOGIC; + SIGNAL wire_n01lOl_dataout : STD_LOGIC; + SIGNAL wire_n01lOO_dataout : STD_LOGIC; + SIGNAL wire_n01O0i_dataout : STD_LOGIC; + SIGNAL wire_n01O0l_dataout : STD_LOGIC; + SIGNAL wire_n01O0O_dataout : STD_LOGIC; + SIGNAL wire_n01O1i_dataout : STD_LOGIC; + SIGNAL wire_n01O1l_dataout : STD_LOGIC; + SIGNAL wire_n01O1O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol_dataout : STD_LOGIC; + SIGNAL wire_n01Oli_dataout : STD_LOGIC; + SIGNAL wire_n01Oll_dataout : STD_LOGIC; + SIGNAL wire_n01OlO_dataout : STD_LOGIC; + SIGNAL wire_n01OO_dataout : STD_LOGIC; + SIGNAL wire_n01OOi_dataout : STD_LOGIC; + SIGNAL wire_n01OOl_dataout : STD_LOGIC; + SIGNAL wire_n01OOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0OO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii0l_dataout : STD_LOGIC; + SIGNAL wire_n0ii0O_dataout : STD_LOGIC; + SIGNAL wire_n0ii1i_dataout : STD_LOGIC; + SIGNAL wire_n0ii1l_dataout : STD_LOGIC; + SIGNAL wire_n0ii1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiii_dataout : STD_LOGIC; + SIGNAL wire_n0iiil_dataout : STD_LOGIC; + SIGNAL wire_n0ili_dataout : STD_LOGIC; + SIGNAL wire_n0ill_dataout : STD_LOGIC; + SIGNAL wire_n0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0li_dataout : STD_LOGIC; + SIGNAL wire_n0l0ll_dataout : STD_LOGIC; + SIGNAL wire_n0l0lO_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l10l_dataout : STD_LOGIC; + SIGNAL wire_n0l10O_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0l1il_dataout : STD_LOGIC; + SIGNAL wire_n0l1iO_dataout : STD_LOGIC; + SIGNAL wire_n0li0i_dataout : STD_LOGIC; + SIGNAL wire_n0li0l_dataout : STD_LOGIC; + SIGNAL wire_n0li0O_dataout : STD_LOGIC; + SIGNAL wire_n0li1i_dataout : STD_LOGIC; + SIGNAL wire_n0li1l_dataout : STD_LOGIC; + SIGNAL wire_n0li1O_dataout : STD_LOGIC; + SIGNAL wire_n0llOi_dataout : STD_LOGIC; + SIGNAL wire_n0llOl_dataout : STD_LOGIC; + SIGNAL wire_n0llOO_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oiii_dataout : STD_LOGIC; + SIGNAL wire_n0Oiil_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oili_dataout : STD_LOGIC; + SIGNAL wire_n0Oill_dataout : STD_LOGIC; + SIGNAL wire_n0OilO_dataout : STD_LOGIC; + SIGNAL wire_n0OiOi_dataout : STD_LOGIC; + SIGNAL wire_n0OiOl_dataout : STD_LOGIC; + SIGNAL wire_n0OiOO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n0Olii_dataout : STD_LOGIC; + SIGNAL wire_n0Olil_dataout : STD_LOGIC; + SIGNAL wire_n0OliO_dataout : STD_LOGIC; + SIGNAL wire_n0Olli_dataout : STD_LOGIC; + SIGNAL wire_n0OllO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlOl_dataout : STD_LOGIC; + SIGNAL wire_n0OlOO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOii_dataout : STD_LOGIC; + SIGNAL wire_n0OOil_dataout : STD_LOGIC; + SIGNAL wire_n0OOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OOli_dataout : STD_LOGIC; + SIGNAL wire_n0OOll_dataout : STD_LOGIC; + SIGNAL wire_n0OOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOOO_dataout : STD_LOGIC; + SIGNAL wire_n1000i_dataout : STD_LOGIC; + SIGNAL wire_n1000O_dataout : STD_LOGIC; + SIGNAL wire_n1001i_dataout : STD_LOGIC; + SIGNAL wire_n1001l_dataout : STD_LOGIC; + SIGNAL wire_n1001O_dataout : STD_LOGIC; + SIGNAL wire_n100i_dataout : STD_LOGIC; + SIGNAL wire_n100ii_dataout : STD_LOGIC; + SIGNAL wire_n100il_dataout : STD_LOGIC; + SIGNAL wire_n100iO_dataout : STD_LOGIC; + SIGNAL wire_n100l_dataout : STD_LOGIC; + SIGNAL wire_n100li_dataout : STD_LOGIC; + SIGNAL wire_n100ll_dataout : STD_LOGIC; + SIGNAL wire_n100lO_dataout : STD_LOGIC; + SIGNAL wire_n100Oi_dataout : STD_LOGIC; + SIGNAL wire_n100Ol_dataout : STD_LOGIC; + SIGNAL wire_n100OO_dataout : STD_LOGIC; + SIGNAL wire_n1010i_dataout : STD_LOGIC; + SIGNAL wire_n1010l_dataout : STD_LOGIC; + SIGNAL wire_n1010O_dataout : STD_LOGIC; + SIGNAL wire_n1011i_dataout : STD_LOGIC; + SIGNAL wire_n1011l_dataout : STD_LOGIC; + SIGNAL wire_n1011O_dataout : STD_LOGIC; + SIGNAL wire_n101i_dataout : STD_LOGIC; + SIGNAL wire_n101ii_dataout : STD_LOGIC; + SIGNAL wire_n101il_dataout : STD_LOGIC; + SIGNAL wire_n101iO_dataout : STD_LOGIC; + SIGNAL wire_n101l_dataout : STD_LOGIC; + SIGNAL wire_n101li_dataout : STD_LOGIC; + SIGNAL wire_n101ll_dataout : STD_LOGIC; + SIGNAL wire_n101lO_dataout : STD_LOGIC; + SIGNAL wire_n101O_dataout : STD_LOGIC; + SIGNAL wire_n101Oi_dataout : STD_LOGIC; + SIGNAL wire_n101Ol_dataout : STD_LOGIC; + SIGNAL wire_n101OO_dataout : STD_LOGIC; + SIGNAL wire_n10i0i_dataout : STD_LOGIC; + SIGNAL wire_n10i0l_dataout : STD_LOGIC; + SIGNAL wire_n10i0O_dataout : STD_LOGIC; + SIGNAL wire_n10i1i_dataout : STD_LOGIC; + SIGNAL wire_n10i1l_dataout : STD_LOGIC; + SIGNAL wire_n10i1O_dataout : STD_LOGIC; + SIGNAL wire_n10iii_dataout : STD_LOGIC; + SIGNAL wire_n10iil_dataout : STD_LOGIC; + SIGNAL wire_n10iiO_dataout : STD_LOGIC; + SIGNAL wire_n10ili_dataout : STD_LOGIC; + SIGNAL wire_n10ill_dataout : STD_LOGIC; + SIGNAL wire_n10ilO_dataout : STD_LOGIC; + SIGNAL wire_n10iOi_dataout : STD_LOGIC; + SIGNAL wire_n10iOl_dataout : STD_LOGIC; + SIGNAL wire_n10iOO_dataout : STD_LOGIC; + SIGNAL wire_n10l1i_dataout : STD_LOGIC; + SIGNAL wire_n10l1l_dataout : STD_LOGIC; + SIGNAL wire_n10l1O_dataout : STD_LOGIC; + SIGNAL wire_n10lii_dataout : STD_LOGIC; + SIGNAL wire_n10lil_dataout : STD_LOGIC; + SIGNAL wire_n10liO_dataout : STD_LOGIC; + SIGNAL wire_n10lli_dataout : STD_LOGIC; + SIGNAL wire_n10lll_dataout : STD_LOGIC; + SIGNAL wire_n10llO_dataout : STD_LOGIC; + SIGNAL wire_n10lOi_dataout : STD_LOGIC; + SIGNAL wire_n10lOO_dataout : STD_LOGIC; + SIGNAL wire_n10O0i_dataout : STD_LOGIC; + SIGNAL wire_n10O0l_dataout : STD_LOGIC; + SIGNAL wire_n10O0O_dataout : STD_LOGIC; + SIGNAL wire_n10O1i_dataout : STD_LOGIC; + SIGNAL wire_n10O1l_dataout : STD_LOGIC; + SIGNAL wire_n10O1O_dataout : STD_LOGIC; + SIGNAL wire_n10Oil_dataout : STD_LOGIC; + SIGNAL wire_n10OiO_dataout : STD_LOGIC; + SIGNAL wire_n10Oli_dataout : STD_LOGIC; + SIGNAL wire_n10Oll_dataout : STD_LOGIC; + SIGNAL wire_n10OlO_dataout : STD_LOGIC; + SIGNAL wire_n10OOi_dataout : STD_LOGIC; + SIGNAL wire_n10OOO_dataout : STD_LOGIC; + SIGNAL wire_n110ii_dataout : STD_LOGIC; + SIGNAL wire_n110il_dataout : STD_LOGIC; + SIGNAL wire_n110iO_dataout : STD_LOGIC; + SIGNAL wire_n110li_dataout : STD_LOGIC; + SIGNAL wire_n110ll_dataout : STD_LOGIC; + SIGNAL wire_n11lO_dataout : STD_LOGIC; + SIGNAL wire_n11Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Ol_dataout : STD_LOGIC; + SIGNAL wire_n11OO_dataout : STD_LOGIC; + SIGNAL wire_n11OOi_dataout : STD_LOGIC; + SIGNAL wire_n11OOl_dataout : STD_LOGIC; + SIGNAL wire_n11OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i00l_dataout : STD_LOGIC; + SIGNAL wire_n1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1l00i_dataout : STD_LOGIC; + SIGNAL wire_n1l00l_dataout : STD_LOGIC; + SIGNAL wire_n1l01i_dataout : STD_LOGIC; + SIGNAL wire_n1l01l_dataout : STD_LOGIC; + SIGNAL wire_n1l01O_dataout : STD_LOGIC; + SIGNAL wire_n1l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l1OO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O_dataout : STD_LOGIC; + SIGNAL wire_n1O01i_dataout : STD_LOGIC; + SIGNAL wire_n1O01l_dataout : STD_LOGIC; + SIGNAL wire_n1O01O_dataout : STD_LOGIC; + SIGNAL wire_n1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1il_dataout : STD_LOGIC; + SIGNAL wire_n1O1iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1li_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO_dataout : STD_LOGIC; + SIGNAL wire_n1Oili_dataout : STD_LOGIC; + SIGNAL wire_n1Oill_dataout : STD_LOGIC; + SIGNAL wire_n1OilO_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiOl_dataout : STD_LOGIC; + SIGNAL wire_ni00i_dataout : STD_LOGIC; + SIGNAL wire_ni00l_dataout : STD_LOGIC; + SIGNAL wire_ni00O_dataout : STD_LOGIC; + SIGNAL wire_ni01i_dataout : STD_LOGIC; + SIGNAL wire_ni01l_dataout : STD_LOGIC; + SIGNAL wire_ni01O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0il_dataout : STD_LOGIC; + SIGNAL wire_ni0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O_dataout : STD_LOGIC; + SIGNAL wire_ni0li_dataout : STD_LOGIC; + SIGNAL wire_ni0lii_dataout : STD_LOGIC; + SIGNAL wire_ni0lil_dataout : STD_LOGIC; + SIGNAL wire_ni0liO_dataout : STD_LOGIC; + SIGNAL wire_ni0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0lli_dataout : STD_LOGIC; + SIGNAL wire_ni0lll_dataout : STD_LOGIC; + SIGNAL wire_ni0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0OO_dataout : STD_LOGIC; + SIGNAL wire_ni100i_dataout : STD_LOGIC; + SIGNAL wire_ni100O_dataout : STD_LOGIC; + SIGNAL wire_ni101i_dataout : STD_LOGIC; + SIGNAL wire_ni101l_dataout : STD_LOGIC; + SIGNAL wire_ni101O_dataout : STD_LOGIC; + SIGNAL wire_ni10ii_dataout : STD_LOGIC; + SIGNAL wire_ni10il_dataout : STD_LOGIC; + SIGNAL wire_ni10iO_dataout : STD_LOGIC; + SIGNAL wire_ni10li_dataout : STD_LOGIC; + SIGNAL wire_ni10ll_dataout : STD_LOGIC; + SIGNAL wire_ni10lO_dataout : STD_LOGIC; + SIGNAL wire_ni10Ol_dataout : STD_LOGIC; + SIGNAL wire_ni10OO_dataout : STD_LOGIC; + SIGNAL wire_ni110i_dataout : STD_LOGIC; + SIGNAL wire_ni110l_dataout : STD_LOGIC; + SIGNAL wire_ni110O_dataout : STD_LOGIC; + SIGNAL wire_ni111i_dataout : STD_LOGIC; + SIGNAL wire_ni111l_dataout : STD_LOGIC; + SIGNAL wire_ni111O_dataout : STD_LOGIC; + SIGNAL wire_ni11ii_dataout : STD_LOGIC; + SIGNAL wire_ni11il_dataout : STD_LOGIC; + SIGNAL wire_ni11iO_dataout : STD_LOGIC; + SIGNAL wire_ni11Oi_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol_dataout : STD_LOGIC; + SIGNAL wire_ni11OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i1i_dataout : STD_LOGIC; + SIGNAL wire_ni1i1l_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O_dataout : STD_LOGIC; + SIGNAL wire_ni1lll_dataout : STD_LOGIC; + SIGNAL wire_ni1O0l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oil_dataout : STD_LOGIC; + SIGNAL wire_nii0i_dataout : STD_LOGIC; + SIGNAL wire_nii0il_dataout : STD_LOGIC; + SIGNAL wire_nii0iO_dataout : STD_LOGIC; + SIGNAL wire_nii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0li_dataout : STD_LOGIC; + SIGNAL wire_nii0ll_dataout : STD_LOGIC; + SIGNAL wire_nii0lO_dataout : STD_LOGIC; + SIGNAL wire_nii0O_dataout : STD_LOGIC; + SIGNAL wire_nii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1O_dataout : STD_LOGIC; + SIGNAL wire_niiii_dataout : STD_LOGIC; + SIGNAL wire_niiiO_dataout : STD_LOGIC; + SIGNAL wire_niiiOi_dataout : STD_LOGIC; + SIGNAL wire_niiiOl_dataout : STD_LOGIC; + SIGNAL wire_niiiOO_dataout : STD_LOGIC; + SIGNAL wire_niil0i_dataout : STD_LOGIC; + SIGNAL wire_niil0l_dataout : STD_LOGIC; + SIGNAL wire_niil0O_dataout : STD_LOGIC; + SIGNAL wire_niil1i_dataout : STD_LOGIC; + SIGNAL wire_niil1l_dataout : STD_LOGIC; + SIGNAL wire_niil1O_dataout : STD_LOGIC; + SIGNAL wire_niili_dataout : STD_LOGIC; + SIGNAL wire_niilii_dataout : STD_LOGIC; + SIGNAL wire_niilil_dataout : STD_LOGIC; + SIGNAL wire_niiliO_dataout : STD_LOGIC; + SIGNAL wire_niill_dataout : STD_LOGIC; + SIGNAL wire_niilO_dataout : STD_LOGIC; + SIGNAL wire_niiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOO_dataout : STD_LOGIC; + SIGNAL wire_nil0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O_dataout : STD_LOGIC; + SIGNAL wire_nil10i_dataout : STD_LOGIC; + SIGNAL wire_nil10l_dataout : STD_LOGIC; + SIGNAL wire_nil11i_dataout : STD_LOGIC; + SIGNAL wire_nil11l_dataout : STD_LOGIC; + SIGNAL wire_nil11O_dataout : STD_LOGIC; + SIGNAL wire_nil1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O_dataout : STD_LOGIC; + SIGNAL wire_nilii_dataout : STD_LOGIC; + SIGNAL wire_nilil_dataout : STD_LOGIC; + SIGNAL wire_niliO_dataout : STD_LOGIC; + SIGNAL wire_nilli_dataout : STD_LOGIC; + SIGNAL wire_nillii_dataout : STD_LOGIC; + SIGNAL wire_nillil_dataout : STD_LOGIC; + SIGNAL wire_nilliO_dataout : STD_LOGIC; + SIGNAL wire_nilll_dataout : STD_LOGIC; + SIGNAL wire_nillli_dataout : STD_LOGIC; + SIGNAL wire_nillll_dataout : STD_LOGIC; + SIGNAL wire_nilllO_dataout : STD_LOGIC; + SIGNAL wire_nillO_dataout : STD_LOGIC; + SIGNAL wire_nillOi_dataout : STD_LOGIC; + SIGNAL wire_nillOl_dataout : STD_LOGIC; + SIGNAL wire_nillOO_dataout : STD_LOGIC; + SIGNAL wire_nilO0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOii_dataout : STD_LOGIC; + SIGNAL wire_nilOil_dataout : STD_LOGIC; + SIGNAL wire_nilOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOli_dataout : STD_LOGIC; + SIGNAL wire_nilOll_dataout : STD_LOGIC; + SIGNAL wire_nilOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOO_dataout : STD_LOGIC; + SIGNAL wire_niO00i_dataout : STD_LOGIC; + SIGNAL wire_niO00l_dataout : STD_LOGIC; + SIGNAL wire_niO00O_dataout : STD_LOGIC; + SIGNAL wire_niO01i_dataout : STD_LOGIC; + SIGNAL wire_niO01l_dataout : STD_LOGIC; + SIGNAL wire_niO01O_dataout : STD_LOGIC; + SIGNAL wire_niO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0ii_dataout : STD_LOGIC; + SIGNAL wire_niO0il_dataout : STD_LOGIC; + SIGNAL wire_niO0iO_dataout : STD_LOGIC; + SIGNAL wire_niO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0li_dataout : STD_LOGIC; + SIGNAL wire_niO0ll_dataout : STD_LOGIC; + SIGNAL wire_niO0lO_dataout : STD_LOGIC; + SIGNAL wire_niO0O_dataout : STD_LOGIC; + SIGNAL wire_niO10i_dataout : STD_LOGIC; + SIGNAL wire_niO10l_dataout : STD_LOGIC; + SIGNAL wire_niO10O_dataout : STD_LOGIC; + SIGNAL wire_niO11i_dataout : STD_LOGIC; + SIGNAL wire_niO11l_dataout : STD_LOGIC; + SIGNAL wire_niO11O_dataout : STD_LOGIC; + SIGNAL wire_niO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1ii_dataout : STD_LOGIC; + SIGNAL wire_niO1il_dataout : STD_LOGIC; + SIGNAL wire_niO1iO_dataout : STD_LOGIC; + SIGNAL wire_niO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1li_dataout : STD_LOGIC; + SIGNAL wire_niO1ll_dataout : STD_LOGIC; + SIGNAL wire_niO1lO_dataout : STD_LOGIC; + SIGNAL wire_niO1O_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOiii_dataout : STD_LOGIC; + SIGNAL wire_niOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOili_dataout : STD_LOGIC; + SIGNAL wire_niOill_dataout : STD_LOGIC; + SIGNAL wire_niOilO_dataout : STD_LOGIC; + SIGNAL wire_niOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOli_dataout : STD_LOGIC; + SIGNAL wire_niOlii_dataout : STD_LOGIC; + SIGNAL wire_niOliO_dataout : STD_LOGIC; + SIGNAL wire_niOll_dataout : STD_LOGIC; + SIGNAL wire_niOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00i_dataout : STD_LOGIC; + SIGNAL wire_nl01i_dataout : STD_LOGIC; + SIGNAL wire_nl0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl10i_dataout : STD_LOGIC; + SIGNAL wire_nl10l_dataout : STD_LOGIC; + SIGNAL wire_nl10O_dataout : STD_LOGIC; + SIGNAL wire_nl11i_dataout : STD_LOGIC; + SIGNAL wire_nl11il_dataout : STD_LOGIC; + SIGNAL wire_nl11ll_dataout : STD_LOGIC; + SIGNAL wire_nl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl_dataout : STD_LOGIC; + SIGNAL wire_nli00i_dataout : STD_LOGIC; + SIGNAL wire_nli00l_dataout : STD_LOGIC; + SIGNAL wire_nli00O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0il_dataout : STD_LOGIC; + SIGNAL wire_nliOill_dataout : STD_LOGIC; + SIGNAL wire_nliOl0l_dataout : STD_LOGIC; + SIGNAL wire_nliOli_dataout : STD_LOGIC; + SIGNAL wire_nliOlil_dataout : STD_LOGIC; + SIGNAL wire_nliOll_dataout : STD_LOGIC; + SIGNAL wire_nliOlO_dataout : STD_LOGIC; + SIGNAL wire_nliOOi_dataout : STD_LOGIC; + SIGNAL wire_nliOOl_dataout : STD_LOGIC; + SIGNAL wire_nliOOO_dataout : STD_LOGIC; + SIGNAL wire_nll00i_dataout : STD_LOGIC; + SIGNAL wire_nll00l_dataout : STD_LOGIC; + SIGNAL wire_nll00O_dataout : STD_LOGIC; + SIGNAL wire_nll00Oi_dataout : STD_LOGIC; + SIGNAL wire_nll00Ol_dataout : STD_LOGIC; + SIGNAL wire_nll00OO_dataout : STD_LOGIC; + SIGNAL wire_nll01i_dataout : STD_LOGIC; + SIGNAL wire_nll01il_dataout : STD_LOGIC; + SIGNAL wire_nll01iO_dataout : STD_LOGIC; + SIGNAL wire_nll01li_dataout : STD_LOGIC; + SIGNAL wire_nll01ll_dataout : STD_LOGIC; + SIGNAL wire_nll01lO_dataout : STD_LOGIC; + SIGNAL wire_nll01O_dataout : STD_LOGIC; + SIGNAL wire_nll0i0i_dataout : STD_LOGIC; + SIGNAL wire_nll0i0l_dataout : STD_LOGIC; + SIGNAL wire_nll0i0O_dataout : STD_LOGIC; + SIGNAL wire_nll0i1i_dataout : STD_LOGIC; + SIGNAL wire_nll0i1l_dataout : STD_LOGIC; + SIGNAL wire_nll0i1O_dataout : STD_LOGIC; + SIGNAL wire_nll0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0iii_dataout : STD_LOGIC; + SIGNAL wire_nll0iil_dataout : STD_LOGIC; + SIGNAL wire_nll0iiO_dataout : STD_LOGIC; + SIGNAL wire_nll0il_dataout : STD_LOGIC; + SIGNAL wire_nll0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0li_dataout : STD_LOGIC; + SIGNAL wire_nll0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0O0i_dataout : STD_LOGIC; + SIGNAL wire_nll0O0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O1i_dataout : STD_LOGIC; + SIGNAL wire_nll0O1l_dataout : STD_LOGIC; + SIGNAL wire_nll0O1O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0OO_dataout : STD_LOGIC; + SIGNAL wire_nll10i_dataout : STD_LOGIC; + SIGNAL wire_nll10l_dataout : STD_LOGIC; + SIGNAL wire_nll10O_dataout : STD_LOGIC; + SIGNAL wire_nll11i_dataout : STD_LOGIC; + SIGNAL wire_nll11l_dataout : STD_LOGIC; + SIGNAL wire_nll11O_dataout : STD_LOGIC; + SIGNAL wire_nll1i0i_dataout : STD_LOGIC; + SIGNAL wire_nll1i0l_dataout : STD_LOGIC; + SIGNAL wire_nll1i0O_dataout : STD_LOGIC; + SIGNAL wire_nll1i1O_dataout : STD_LOGIC; + SIGNAL wire_nll1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1iii_dataout : STD_LOGIC; + SIGNAL wire_nll1iil_dataout : STD_LOGIC; + SIGNAL wire_nll1iiO_dataout : STD_LOGIC; + SIGNAL wire_nll1il_dataout : STD_LOGIC; + SIGNAL wire_nll1ili_dataout : STD_LOGIC; + SIGNAL wire_nll1ill_dataout : STD_LOGIC; + SIGNAL wire_nll1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1li_dataout : STD_LOGIC; + SIGNAL wire_nll1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O_dataout : STD_LOGIC; + SIGNAL wire_nlli1i_dataout : STD_LOGIC; + SIGNAL wire_nlli1l_dataout : STD_LOGIC; + SIGNAL wire_nlli1O_dataout : STD_LOGIC; + SIGNAL wire_nlliii_dataout : STD_LOGIC; + SIGNAL wire_nlliiii_dataout : STD_LOGIC; + SIGNAL wire_nlliiil_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO_dataout : STD_LOGIC; + SIGNAL wire_nlliil_dataout : STD_LOGIC; + SIGNAL wire_nlliili_dataout : STD_LOGIC; + SIGNAL wire_nlliill_dataout : STD_LOGIC; + SIGNAL wire_nlliilO_dataout : STD_LOGIC; + SIGNAL wire_nlliiO_dataout : STD_LOGIC; + SIGNAL wire_nlliiOi_dataout : STD_LOGIC; + SIGNAL wire_nlliiOl_dataout : STD_LOGIC; + SIGNAL wire_nlliiOO_dataout : STD_LOGIC; + SIGNAL wire_nllil0i_dataout : STD_LOGIC; + SIGNAL wire_nllil0l_dataout : STD_LOGIC; + SIGNAL wire_nllil0O_dataout : STD_LOGIC; + SIGNAL wire_nllil1i_dataout : STD_LOGIC; + SIGNAL wire_nllil1l_dataout : STD_LOGIC; + SIGNAL wire_nllil1O_dataout : STD_LOGIC; + SIGNAL wire_nllili_dataout : STD_LOGIC; + SIGNAL wire_nllilii_dataout : STD_LOGIC; + SIGNAL wire_nllilil_dataout : STD_LOGIC; + SIGNAL wire_nlliliO_dataout : STD_LOGIC; + SIGNAL wire_nllill_dataout : STD_LOGIC; + SIGNAL wire_nllilli_dataout : STD_LOGIC; + SIGNAL wire_nllilll_dataout : STD_LOGIC; + SIGNAL wire_nllillO_dataout : STD_LOGIC; + SIGNAL wire_nllilO_dataout : STD_LOGIC; + SIGNAL wire_nllilOi_dataout : STD_LOGIC; + SIGNAL wire_nllilOO_dataout : STD_LOGIC; + SIGNAL wire_nlliO0i_dataout : STD_LOGIC; + SIGNAL wire_nlliO0l_dataout : STD_LOGIC; + SIGNAL wire_nlliO0O_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i_dataout : STD_LOGIC; + SIGNAL wire_nlliO1l_dataout : STD_LOGIC; + SIGNAL wire_nlliO1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOii_dataout : STD_LOGIC; + SIGNAL wire_nlliOil_dataout : STD_LOGIC; + SIGNAL wire_nlliOiO_dataout : STD_LOGIC; + SIGNAL wire_nlliOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOli_dataout : STD_LOGIC; + SIGNAL wire_nlliOll_dataout : STD_LOGIC; + SIGNAL wire_nlliOlO_dataout : STD_LOGIC; + SIGNAL wire_nlliOO_dataout : STD_LOGIC; + SIGNAL wire_nlliOOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOOO_dataout : STD_LOGIC; + SIGNAL wire_nlll00i_dataout : STD_LOGIC; + SIGNAL wire_nlll00l_dataout : STD_LOGIC; + SIGNAL wire_nlll00O_dataout : STD_LOGIC; + SIGNAL wire_nlll01i_dataout : STD_LOGIC; + SIGNAL wire_nlll01l_dataout : STD_LOGIC; + SIGNAL wire_nlll01O_dataout : STD_LOGIC; + SIGNAL wire_nlll0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii_dataout : STD_LOGIC; + SIGNAL wire_nlll0iO_dataout : STD_LOGIC; + SIGNAL wire_nlll0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0li_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll_dataout : STD_LOGIC; + SIGNAL wire_nlll0lO_dataout : STD_LOGIC; + SIGNAL wire_nlll0O_dataout : STD_LOGIC; + SIGNAL wire_nlll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll0OO_dataout : STD_LOGIC; + SIGNAL wire_nlll10i_dataout : STD_LOGIC; + SIGNAL wire_nlll10l_dataout : STD_LOGIC; + SIGNAL wire_nlll10O_dataout : STD_LOGIC; + SIGNAL wire_nlll11i_dataout : STD_LOGIC; + SIGNAL wire_nlll11l_dataout : STD_LOGIC; + SIGNAL wire_nlll11O_dataout : STD_LOGIC; + SIGNAL wire_nlll1ii_dataout : STD_LOGIC; + SIGNAL wire_nlll1il_dataout : STD_LOGIC; + SIGNAL wire_nlll1iO_dataout : STD_LOGIC; + SIGNAL wire_nlll1li_dataout : STD_LOGIC; + SIGNAL wire_nlll1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1lO_dataout : STD_LOGIC; + SIGNAL wire_nllli0i_dataout : STD_LOGIC; + SIGNAL wire_nllli0l_dataout : STD_LOGIC; + SIGNAL wire_nllli0O_dataout : STD_LOGIC; + SIGNAL wire_nllli1l_dataout : STD_LOGIC; + SIGNAL wire_nllli1O_dataout : STD_LOGIC; + SIGNAL wire_nlllii_dataout : STD_LOGIC; + SIGNAL wire_nllliii_dataout : STD_LOGIC; + SIGNAL wire_nllliiO_dataout : STD_LOGIC; + SIGNAL wire_nlllil_dataout : STD_LOGIC; + SIGNAL wire_nllliO_dataout : STD_LOGIC; + SIGNAL wire_nlllli_dataout : STD_LOGIC; + SIGNAL wire_nllllO_dataout : STD_LOGIC; + SIGNAL wire_nllllOl_dataout : STD_LOGIC; + SIGNAL wire_nlllOi_dataout : STD_LOGIC; + SIGNAL wire_nlllOil_dataout : STD_LOGIC; + SIGNAL wire_nlllOl_dataout : STD_LOGIC; + SIGNAL wire_nlllOll_dataout : STD_LOGIC; + SIGNAL wire_nlllOO_dataout : STD_LOGIC; + SIGNAL wire_nllO0l_dataout : STD_LOGIC; + SIGNAL wire_nllO0O_dataout : STD_LOGIC; + SIGNAL wire_nllO1i_dataout : STD_LOGIC; + SIGNAL wire_nllO1l_dataout : STD_LOGIC; + SIGNAL wire_nllO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOii_dataout : STD_LOGIC; + SIGNAL wire_nllOil_dataout : STD_LOGIC; + SIGNAL wire_nllOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOl0O_dataout : STD_LOGIC; + SIGNAL wire_nllOli_dataout : STD_LOGIC; + SIGNAL wire_nllOlii_dataout : STD_LOGIC; + SIGNAL wire_nllOlil_dataout : STD_LOGIC; + SIGNAL wire_nllOliO_dataout : STD_LOGIC; + SIGNAL wire_nllOlli_dataout : STD_LOGIC; + SIGNAL wire_nllOlll_dataout : STD_LOGIC; + SIGNAL wire_nllOllO_dataout : STD_LOGIC; + SIGNAL wire_nllOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOlOi_dataout : STD_LOGIC; + SIGNAL wire_nllOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO010i_dataout : STD_LOGIC; + SIGNAL wire_nlO010l_dataout : STD_LOGIC; + SIGNAL wire_nlO010O_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01il_dataout : STD_LOGIC; + SIGNAL wire_nlO01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli_dataout : STD_LOGIC; + SIGNAL wire_nlO0lll_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO10ll_dataout : STD_LOGIC; + SIGNAL wire_nlO10lO_dataout : STD_LOGIC; + SIGNAL wire_nlO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO10OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1lii_dataout : STD_LOGIC; + SIGNAL wire_nlO1lil_dataout : STD_LOGIC; + SIGNAL wire_nlO1liO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lli_dataout : STD_LOGIC; + SIGNAL wire_nlO1lll_dataout : STD_LOGIC; + SIGNAL wire_nlO1llO_dataout : STD_LOGIC; + SIGNAL wire_nlOi00i_dataout : STD_LOGIC; + SIGNAL wire_nlOi00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi00O_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i_dataout : STD_LOGIC; + SIGNAL wire_nlOi01l_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0il_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi10i_dataout : STD_LOGIC; + SIGNAL wire_nlOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlOi10O_dataout : STD_LOGIC; + SIGNAL wire_nlOi11i_dataout : STD_LOGIC; + SIGNAL wire_nlOi11O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1il_dataout : STD_LOGIC; + SIGNAL wire_nlOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiili_dataout : STD_LOGIC; + SIGNAL wire_nlOiilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOil0l_dataout : STD_LOGIC; + SIGNAL wire_nlOil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOil1O_dataout : STD_LOGIC; + SIGNAL wire_nlOilii_dataout : STD_LOGIC; + SIGNAL wire_nlOilil_dataout : STD_LOGIC; + SIGNAL wire_nlOiliO_dataout : STD_LOGIC; + SIGNAL wire_nlOilli_dataout : STD_LOGIC; + SIGNAL wire_nlOillO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n000i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n000i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n000i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0011l_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0011l_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0011l_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001li_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001li_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001li_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n01iil_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n01iil_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n01iil_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n01Oii_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n01Oii_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n01Oii_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n0liii_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0liii_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0liii_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0Olll_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n0Olll_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n0Olll_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n1000l_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n1000l_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n1000l_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n10l0i_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n10l0i_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n10l0i_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_n10lOl_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n10lOl_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n10lOl_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n10Oii_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n10Oii_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n10Oii_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1111i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1111i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1111i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O00i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O00i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O00i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni100l_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni100l_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni100l_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni10Oi_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni10Oi_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni10Oi_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni11li_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_ni11li_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_ni11li_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niiil_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niiil_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niiil_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niilli_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niilli_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_niilli_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nilOOl_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nilOOl_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nilOOl_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niO0Oi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niO0Oi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niO0Oi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niOii_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niOii_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niOii_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niOiil_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niOiil_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niOiil_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niOl1i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niOl1i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_niOl1i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl0OOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0OOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl0OOi_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl11l_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl11l_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl11l_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1li_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1li_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1li_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nll01l_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nll01l_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nll01l_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nll0ili_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nll0ili_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nll0ili_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllilOl_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nllilOl_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nllilOl_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlll0il_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlll0il_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlll0il_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlll1i_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlll1i_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlll1i_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlll1Oi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlll1Oi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlll1Oi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nllli1i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nllli1i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nllli1i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlllll_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlllll_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlllll_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nllO0i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nllO0i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nllO0i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlO1lOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO1lOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO1lOi_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOi11l_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlOi11l_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlOi11l_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlOii1i_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlOii1i_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlOii1i_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlOiill_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlOiill_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlOiill_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlOil0i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlOil0i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlOil0i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n010O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_n010O_o : STD_LOGIC; + SIGNAL wire_n0l01i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l01i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l01i_o : STD_LOGIC; + SIGNAL wire_n0l0iO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l0iO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l0iO_o : STD_LOGIC; + SIGNAL wire_n1lOOi_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOOi_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOOi_o : STD_LOGIC; + SIGNAL wire_n1O10O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O10O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O10O_o : STD_LOGIC; + SIGNAL wire_n1OOi_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OOi_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OOi_o : STD_LOGIC; + SIGNAL wire_niii0i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii0i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii0i_o : STD_LOGIC; + SIGNAL wire_niiilO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiilO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niiilO_o : STD_LOGIC; + SIGNAL wire_nl0lii_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0lii_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0lii_o : STD_LOGIC; + SIGNAL wire_nl0lOO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0lOO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl0lOO_o : STD_LOGIC; + SIGNAL wire_nll000i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll000i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll000i_o : STD_LOGIC; + SIGNAL wire_nll00lO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll00lO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nll00lO_o : STD_LOGIC; + SIGNAL wire_nlO1iii_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO1iii_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO1iii_o : STD_LOGIC; + SIGNAL wire_nlO1iOO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO1iOO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO1iOO_o : STD_LOGIC; + SIGNAL wire_nlOOlli_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOOlli_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOOlli_o : STD_LOGIC; + SIGNAL wire_nlOOO1O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOOO1O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOOO1O_o : STD_LOGIC; + SIGNAL wire_n0iii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0iii_o : STD_LOGIC; + SIGNAL wire_n0iii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0iil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0iil_o : STD_LOGIC; + SIGNAL wire_n0iil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0iiO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0iiO_o : STD_LOGIC; + SIGNAL wire_n0iiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0llli_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0llli_o : STD_LOGIC; + SIGNAL wire_n0llli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0llll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0llll_o : STD_LOGIC; + SIGNAL wire_n0llll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0lllO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0lllO_o : STD_LOGIC; + SIGNAL wire_n0lllO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1100i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1100i_o : STD_LOGIC; + SIGNAL wire_n1100i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1100l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1100l_o : STD_LOGIC; + SIGNAL wire_n1100l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1100O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1100O_o : STD_LOGIC; + SIGNAL wire_n1100O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1Oiii_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oiii_o : STD_LOGIC; + SIGNAL wire_n1Oiii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1Oiil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oiil_o : STD_LOGIC; + SIGNAL wire_n1Oiil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1OiiO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1OiiO_o : STD_LOGIC; + SIGNAL wire_n1OiiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niiOOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niiOOi_o : STD_LOGIC; + SIGNAL wire_niiOOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niiOOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niiOOl_o : STD_LOGIC; + SIGNAL wire_niiOOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niiOOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_niiOOO_o : STD_LOGIC; + SIGNAL wire_niiOOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli01i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli01i_o : STD_LOGIC; + SIGNAL wire_nli01i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli01l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli01l_o : STD_LOGIC; + SIGNAL wire_nli01l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli01O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nli01O_o : STD_LOGIC; + SIGNAL wire_nli01O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0lOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nll0lOi_o : STD_LOGIC; + SIGNAL wire_nll0lOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0lOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nll0lOl_o : STD_LOGIC; + SIGNAL wire_nll0lOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll0lOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nll0lOO_o : STD_LOGIC; + SIGNAL wire_nll0lOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO011i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO011i_o : STD_LOGIC; + SIGNAL wire_nlO011i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO011l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO011l_o : STD_LOGIC; + SIGNAL wire_nlO011l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO011O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlO011O_o : STD_LOGIC; + SIGNAL wire_nlO011O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0i0ll_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0i0ll_o : STD_LOGIC; + SIGNAL wire_n0i0ll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0i0lO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0i0lO_o : STD_LOGIC; + SIGNAL wire_n0i0lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0i0Oi_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0i0Oi_o : STD_LOGIC; + SIGNAL wire_n0i0Oi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0i0Ol_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0i0Ol_o : STD_LOGIC; + SIGNAL wire_n0i0Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11il_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n11il_o : STD_LOGIC; + SIGNAL wire_n11il_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n11iO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11iO_o : STD_LOGIC; + SIGNAL wire_n11iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11li_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11li_o : STD_LOGIC; + SIGNAL wire_n11li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11ll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11ll_o : STD_LOGIC; + SIGNAL wire_n11ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l1il_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1l1il_o : STD_LOGIC; + SIGNAL wire_n1l1il_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1l1iO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l1iO_o : STD_LOGIC; + SIGNAL wire_n1l1iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l1li_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l1li_o : STD_LOGIC; + SIGNAL wire_n1l1li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l1ll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l1ll_o : STD_LOGIC; + SIGNAL wire_n1l1ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0iOl_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0iOl_o : STD_LOGIC; + SIGNAL wire_ni0iOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_ni0iOO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0iOO_o : STD_LOGIC; + SIGNAL wire_ni0iOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0l1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0l1i_o : STD_LOGIC; + SIGNAL wire_ni0l1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0l1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni0l1l_o : STD_LOGIC; + SIGNAL wire_ni0l1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1O0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1O0i_o : STD_LOGIC; + SIGNAL wire_nl1O0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1O0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1O0l_o : STD_LOGIC; + SIGNAL wire_nl1O0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1O1l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1l_o : STD_LOGIC; + SIGNAL wire_nl1O1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1O1O_o : STD_LOGIC; + SIGNAL wire_nl1O1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll10Ol_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll10Ol_o : STD_LOGIC; + SIGNAL wire_nll10Ol_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nll10OO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll10OO_o : STD_LOGIC; + SIGNAL wire_nll10OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1i1i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1i1i_o : STD_LOGIC; + SIGNAL wire_nll1i1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1i1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nll1i1l_o : STD_LOGIC; + SIGNAL wire_nll1i1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOl0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOl0i_o : STD_LOGIC; + SIGNAL wire_nllOl0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOl0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOl0l_o : STD_LOGIC; + SIGNAL wire_nllOl0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOl1l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOl1l_o : STD_LOGIC; + SIGNAL wire_nllOl1l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nllOl1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nllOl1O_o : STD_LOGIC; + SIGNAL wire_nllOl1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlOlO0l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlOlO0l_o : STD_LOGIC; + SIGNAL wire_nlOlO0l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlOlO0O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlOlO0O_o : STD_LOGIC; + SIGNAL wire_nlOlO0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlOlOii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlOlOii_o : STD_LOGIC; + SIGNAL wire_nlOlOii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlOlOil_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlOlOil_o : STD_LOGIC; + SIGNAL wire_nlOlOil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nli01li3598w3616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nli0iOl3060w3078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nli1lii4134w4152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlii11O2522w2540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliii0O1986w2004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliiOiO1449w1467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlil0lO913w931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlilOil361w379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nli01ii3619w3621w3622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nli0ill3083w3085w3086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nli0OOO2545w2547w2548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nli1l0i4156w4158w4159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nliii1O2007w2009w2010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nliiO0O1471w1473w1474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nlil0iO934w936w937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_nlilO1O382w384w385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli00Ol3136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli010i3620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli01ii3619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli01Oi3669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli01Oi3673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0iil3084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0ill3083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0l1l3133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0l1l3137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0O1O2598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0OlO2546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0OOO2545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1iil4209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1l0i4156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1l1i4157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1lli4206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1lli4210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1Oll3672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii0ii2060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii0OO2008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii10O2595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii10O2599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliii1O2007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiiiO2057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiiiO2061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilli1524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiO0O1471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiO1O1472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOlO1521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOlO1525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil00O935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil0iO934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil0OO984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil0OO988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil1Oi987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlill0l435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlillOi383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilO1O382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilOOi432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilOOi436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_enable_inf_ei_range40w540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli00lO3310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli01li3598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli01ll3615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli01Oi3676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli01OO3675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0i1O3024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0iOl3060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0iOO3077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0l0i3139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0l1l3140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0O1i2772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli0Oii2486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1i0O4383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1ill4098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1lii4134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1lil4151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1lli4213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1llO4212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1OiO3846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nli1OOl3562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii00l2234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii0li1950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii10i2539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii10O2602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii11O2522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlii1il2601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliii0O1986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiiii2003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiiiO2064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiill2063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilil1698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliilOi1413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOiO1449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOli1466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOlO1528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nliiOOl1527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil01i877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil0lO913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil0Oi930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil0OO991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlil1ll1161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlili1l990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlill1O620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlillil325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilOil361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilOll378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilOOi439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilOOO438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_test_in_0466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_enable_inf_ei_range41w539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nli01ii3619w3621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nli0ill3083w3085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nli0OOO2545w2547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nli1l0i4156w4158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliii1O2007w2009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nliiO0O1471w1473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlil0iO934w936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_nlilO1O382w384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_nlilO1l293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_eidleinfersel_range23w200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_eidleinfersel_range22w207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli000i : STD_LOGIC; + SIGNAL nli000l : STD_LOGIC; + SIGNAL nli000O : STD_LOGIC; + SIGNAL nli001i : STD_LOGIC; + SIGNAL nli001l : STD_LOGIC; + SIGNAL nli001O : STD_LOGIC; + SIGNAL nli00ii : STD_LOGIC; + SIGNAL nli00il : STD_LOGIC; + SIGNAL nli00iO : STD_LOGIC; + SIGNAL nli00li : STD_LOGIC; + SIGNAL nli00ll : STD_LOGIC; + SIGNAL nli00lO : STD_LOGIC; + SIGNAL nli00Oi : STD_LOGIC; + SIGNAL nli00Ol : STD_LOGIC; + SIGNAL nli010i : STD_LOGIC; + SIGNAL nli010l : STD_LOGIC; + SIGNAL nli010O : STD_LOGIC; + SIGNAL nli011i : STD_LOGIC; + SIGNAL nli011l : STD_LOGIC; + SIGNAL nli011O : STD_LOGIC; + SIGNAL nli01ii : STD_LOGIC; + SIGNAL nli01il : STD_LOGIC; + SIGNAL nli01iO : STD_LOGIC; + SIGNAL nli01li : STD_LOGIC; + SIGNAL nli01ll : STD_LOGIC; + SIGNAL nli01lO : STD_LOGIC; + SIGNAL nli01Oi : STD_LOGIC; + SIGNAL nli01Ol : STD_LOGIC; + SIGNAL nli01OO : STD_LOGIC; + SIGNAL nli0i0i : STD_LOGIC; + SIGNAL nli0i0l : STD_LOGIC; + SIGNAL nli0i0O : STD_LOGIC; + SIGNAL nli0i1l : STD_LOGIC; + SIGNAL nli0i1O : STD_LOGIC; + SIGNAL nli0iii : STD_LOGIC; + SIGNAL nli0iil : STD_LOGIC; + SIGNAL nli0iiO : STD_LOGIC; + SIGNAL nli0ili : STD_LOGIC; + SIGNAL nli0ill : STD_LOGIC; + SIGNAL nli0ilO : STD_LOGIC; + SIGNAL nli0iOi : STD_LOGIC; + SIGNAL nli0iOl : STD_LOGIC; + SIGNAL nli0iOO : STD_LOGIC; + SIGNAL nli0l0i : STD_LOGIC; + SIGNAL nli0l0l : STD_LOGIC; + SIGNAL nli0l0O : STD_LOGIC; + SIGNAL nli0l1i : STD_LOGIC; + SIGNAL nli0l1l : STD_LOGIC; + SIGNAL nli0l1O : STD_LOGIC; + SIGNAL nli0lii : STD_LOGIC; + SIGNAL nli0lil : STD_LOGIC; + SIGNAL nli0liO : STD_LOGIC; + SIGNAL nli0lli : STD_LOGIC; + SIGNAL nli0lll : STD_LOGIC; + SIGNAL nli0llO : STD_LOGIC; + SIGNAL nli0lOi : STD_LOGIC; + SIGNAL nli0lOl : STD_LOGIC; + SIGNAL nli0lOO : STD_LOGIC; + SIGNAL nli0O0O : STD_LOGIC; + SIGNAL nli0O1i : STD_LOGIC; + SIGNAL nli0O1l : STD_LOGIC; + SIGNAL nli0O1O : STD_LOGIC; + SIGNAL nli0Oii : STD_LOGIC; + SIGNAL nli0Oil : STD_LOGIC; + SIGNAL nli0OiO : STD_LOGIC; + SIGNAL nli0Oli : STD_LOGIC; + SIGNAL nli0Oll : STD_LOGIC; + SIGNAL nli0OlO : STD_LOGIC; + SIGNAL nli0OOi : STD_LOGIC; + SIGNAL nli0OOl : STD_LOGIC; + SIGNAL nli0OOO : STD_LOGIC; + SIGNAL nli1i0O : STD_LOGIC; + SIGNAL nli1iii : STD_LOGIC; + SIGNAL nli1iil : STD_LOGIC; + SIGNAL nli1ili : STD_LOGIC; + SIGNAL nli1ill : STD_LOGIC; + SIGNAL nli1ilO : STD_LOGIC; + SIGNAL nli1iOi : STD_LOGIC; + SIGNAL nli1iOl : STD_LOGIC; + SIGNAL nli1iOO : STD_LOGIC; + SIGNAL nli1l0i : STD_LOGIC; + SIGNAL nli1l0l : STD_LOGIC; + SIGNAL nli1l0O : STD_LOGIC; + SIGNAL nli1l1i : STD_LOGIC; + SIGNAL nli1l1l : STD_LOGIC; + SIGNAL nli1l1O : STD_LOGIC; + SIGNAL nli1lii : STD_LOGIC; + SIGNAL nli1lil : STD_LOGIC; + SIGNAL nli1liO : STD_LOGIC; + SIGNAL nli1lli : STD_LOGIC; + SIGNAL nli1lll : STD_LOGIC; + SIGNAL nli1llO : STD_LOGIC; + SIGNAL nli1lOi : STD_LOGIC; + SIGNAL nli1lOl : STD_LOGIC; + SIGNAL nli1lOO : STD_LOGIC; + SIGNAL nli1O0i : STD_LOGIC; + SIGNAL nli1O0l : STD_LOGIC; + SIGNAL nli1O0O : STD_LOGIC; + SIGNAL nli1O1i : STD_LOGIC; + SIGNAL nli1O1l : STD_LOGIC; + SIGNAL nli1O1O : STD_LOGIC; + SIGNAL nli1Oii : STD_LOGIC; + SIGNAL nli1Oil : STD_LOGIC; + SIGNAL nli1OiO : STD_LOGIC; + SIGNAL nli1Oli : STD_LOGIC; + SIGNAL nli1Oll : STD_LOGIC; + SIGNAL nli1OOi : STD_LOGIC; + SIGNAL nli1OOl : STD_LOGIC; + SIGNAL nli1OOO : STD_LOGIC; + SIGNAL nlii00i : STD_LOGIC; + SIGNAL nlii00l : STD_LOGIC; + SIGNAL nlii00O : STD_LOGIC; + SIGNAL nlii01i : STD_LOGIC; + SIGNAL nlii01l : STD_LOGIC; + SIGNAL nlii01O : STD_LOGIC; + SIGNAL nlii0ii : STD_LOGIC; + SIGNAL nlii0iO : STD_LOGIC; + SIGNAL nlii0li : STD_LOGIC; + SIGNAL nlii0ll : STD_LOGIC; + SIGNAL nlii0lO : STD_LOGIC; + SIGNAL nlii0Oi : STD_LOGIC; + SIGNAL nlii0Ol : STD_LOGIC; + SIGNAL nlii0OO : STD_LOGIC; + SIGNAL nlii10i : STD_LOGIC; + SIGNAL nlii10l : STD_LOGIC; + SIGNAL nlii10O : STD_LOGIC; + SIGNAL nlii11i : STD_LOGIC; + SIGNAL nlii11l : STD_LOGIC; + SIGNAL nlii11O : STD_LOGIC; + SIGNAL nlii1ii : STD_LOGIC; + SIGNAL nlii1il : STD_LOGIC; + SIGNAL nlii1iO : STD_LOGIC; + SIGNAL nlii1li : STD_LOGIC; + SIGNAL nlii1ll : STD_LOGIC; + SIGNAL nlii1lO : STD_LOGIC; + SIGNAL nlii1Oi : STD_LOGIC; + SIGNAL nlii1Ol : STD_LOGIC; + SIGNAL nlii1OO : STD_LOGIC; + SIGNAL nliii0i : STD_LOGIC; + SIGNAL nliii0l : STD_LOGIC; + SIGNAL nliii0O : STD_LOGIC; + SIGNAL nliii1i : STD_LOGIC; + SIGNAL nliii1l : STD_LOGIC; + SIGNAL nliii1O : STD_LOGIC; + SIGNAL nliiiii : STD_LOGIC; + SIGNAL nliiiil : STD_LOGIC; + SIGNAL nliiiiO : STD_LOGIC; + SIGNAL nliiili : STD_LOGIC; + SIGNAL nliiill : STD_LOGIC; + SIGNAL nliiilO : STD_LOGIC; + SIGNAL nliiiOi : STD_LOGIC; + SIGNAL nliiiOl : STD_LOGIC; + SIGNAL nliiiOO : STD_LOGIC; + SIGNAL nliil0i : STD_LOGIC; + SIGNAL nliil0l : STD_LOGIC; + SIGNAL nliil0O : STD_LOGIC; + SIGNAL nliil1i : STD_LOGIC; + SIGNAL nliil1l : STD_LOGIC; + SIGNAL nliil1O : STD_LOGIC; + SIGNAL nliilii : STD_LOGIC; + SIGNAL nliilil : STD_LOGIC; + SIGNAL nliiliO : STD_LOGIC; + SIGNAL nliilli : STD_LOGIC; + SIGNAL nliillO : STD_LOGIC; + SIGNAL nliilOi : STD_LOGIC; + SIGNAL nliilOl : STD_LOGIC; + SIGNAL nliilOO : STD_LOGIC; + SIGNAL nliiO0i : STD_LOGIC; + SIGNAL nliiO0l : STD_LOGIC; + SIGNAL nliiO0O : STD_LOGIC; + SIGNAL nliiO1i : STD_LOGIC; + SIGNAL nliiO1l : STD_LOGIC; + SIGNAL nliiO1O : STD_LOGIC; + SIGNAL nliiOii : STD_LOGIC; + SIGNAL nliiOil : STD_LOGIC; + SIGNAL nliiOiO : STD_LOGIC; + SIGNAL nliiOli : STD_LOGIC; + SIGNAL nliiOll : STD_LOGIC; + SIGNAL nliiOlO : STD_LOGIC; + SIGNAL nliiOOi : STD_LOGIC; + SIGNAL nliiOOl : STD_LOGIC; + SIGNAL nliiOOO : STD_LOGIC; + SIGNAL nlil00i : STD_LOGIC; + SIGNAL nlil00l : STD_LOGIC; + SIGNAL nlil00O : STD_LOGIC; + SIGNAL nlil01i : STD_LOGIC; + SIGNAL nlil01l : STD_LOGIC; + SIGNAL nlil01O : STD_LOGIC; + SIGNAL nlil0ii : STD_LOGIC; + SIGNAL nlil0il : STD_LOGIC; + SIGNAL nlil0iO : STD_LOGIC; + SIGNAL nlil0li : STD_LOGIC; + SIGNAL nlil0ll : STD_LOGIC; + SIGNAL nlil0lO : STD_LOGIC; + SIGNAL nlil0Oi : STD_LOGIC; + SIGNAL nlil0Ol : STD_LOGIC; + SIGNAL nlil0OO : STD_LOGIC; + SIGNAL nlil10i : STD_LOGIC; + SIGNAL nlil10l : STD_LOGIC; + SIGNAL nlil10O : STD_LOGIC; + SIGNAL nlil11i : STD_LOGIC; + SIGNAL nlil11l : STD_LOGIC; + SIGNAL nlil11O : STD_LOGIC; + SIGNAL nlil1ii : STD_LOGIC; + SIGNAL nlil1il : STD_LOGIC; + SIGNAL nlil1iO : STD_LOGIC; + SIGNAL nlil1li : STD_LOGIC; + SIGNAL nlil1ll : STD_LOGIC; + SIGNAL nlil1lO : STD_LOGIC; + SIGNAL nlil1Oi : STD_LOGIC; + SIGNAL nlil1OO : STD_LOGIC; + SIGNAL nlili0i : STD_LOGIC; + SIGNAL nlili0l : STD_LOGIC; + SIGNAL nlili0O : STD_LOGIC; + SIGNAL nlili1i : STD_LOGIC; + SIGNAL nlili1l : STD_LOGIC; + SIGNAL nlili1O : STD_LOGIC; + SIGNAL nliliii : STD_LOGIC; + SIGNAL nliliil : STD_LOGIC; + SIGNAL nliliiO : STD_LOGIC; + SIGNAL nlilili : STD_LOGIC; + SIGNAL nlilill : STD_LOGIC; + SIGNAL nlililO : STD_LOGIC; + SIGNAL nliliOi : STD_LOGIC; + SIGNAL nlill0i : STD_LOGIC; + SIGNAL nlill0l : STD_LOGIC; + SIGNAL nlill1O : STD_LOGIC; + SIGNAL nlillii : STD_LOGIC; + SIGNAL nlillil : STD_LOGIC; + SIGNAL nlilliO : STD_LOGIC; + SIGNAL nlillli : STD_LOGIC; + SIGNAL nlillll : STD_LOGIC; + SIGNAL nlilllO : STD_LOGIC; + SIGNAL nlillOi : STD_LOGIC; + SIGNAL nlilO0O : STD_LOGIC; + SIGNAL nlilO1i : STD_LOGIC; + SIGNAL nlilO1l : STD_LOGIC; + SIGNAL nlilO1O : STD_LOGIC; + SIGNAL nlilOii : STD_LOGIC; + SIGNAL nlilOil : STD_LOGIC; + SIGNAL nlilOll : STD_LOGIC; + SIGNAL nlilOlO : STD_LOGIC; + SIGNAL nlilOOi : STD_LOGIC; + SIGNAL nlilOOl : STD_LOGIC; + SIGNAL nlilOOO : STD_LOGIC; + SIGNAL nliO00i : STD_LOGIC; + SIGNAL nliO00l : STD_LOGIC; + SIGNAL nliO00O : STD_LOGIC; + SIGNAL nliO01i : STD_LOGIC; + SIGNAL nliO01l : STD_LOGIC; + SIGNAL nliO0ii : STD_LOGIC; + SIGNAL nliO0il : STD_LOGIC; + SIGNAL nliO11O : STD_LOGIC; + SIGNAL nliO1ii : STD_LOGIC; + SIGNAL nliO1Ol : STD_LOGIC; + SIGNAL nliO1OO : STD_LOGIC; + SIGNAL nliOiii : STD_LOGIC; + SIGNAL wire_w_eidleinfersel_range23w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_eidleinfersel_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_enable_inf_ei_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_enable_inf_ei_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0); + BEGIN + + wire_gnd <= '0'; + wire_vcc <= '1'; + wire_w_lg_w_lg_nli01li3598w3616w(0) <= wire_w_lg_nli01li3598w(0) AND nli011i; + wire_w_lg_w_lg_nli0iOl3060w3078w(0) <= wire_w_lg_nli0iOl3060w(0) AND nli0i0l; + wire_w_lg_w_lg_nli1lii4134w4152w(0) <= wire_w_lg_nli1lii4134w(0) AND nli1iOi; + wire_w_lg_w_lg_nlii11O2522w2540w(0) <= wire_w_lg_nlii11O2522w(0) AND nli0OiO; + wire_w_lg_w_lg_nliii0O1986w2004w(0) <= wire_w_lg_nliii0O1986w(0) AND nlii0lO; + wire_w_lg_w_lg_nliiOiO1449w1467w(0) <= wire_w_lg_nliiOiO1449w(0) AND nliilOO; + wire_w_lg_w_lg_nlil0lO913w931w(0) <= wire_w_lg_nlil0lO913w(0) AND nlil01O; + wire_w_lg_w_lg_nlilOil361w379w(0) <= wire_w_lg_nlilOil361w(0) AND nlillli; + wire_w_lg_w_lg_w_lg_nli01ii3619w3621w3622w(0) <= wire_w_lg_w_lg_nli01ii3619w3621w(0) AND nli011l; + wire_w_lg_w_lg_w_lg_nli0ill3083w3085w3086w(0) <= wire_w_lg_w_lg_nli0ill3083w3085w(0) AND nli0i0O; + wire_w_lg_w_lg_w_lg_nli0OOO2545w2547w2548w(0) <= wire_w_lg_w_lg_nli0OOO2545w2547w(0) AND nli0Oli; + wire_w_lg_w_lg_w_lg_nli1l0i4156w4158w4159w(0) <= wire_w_lg_w_lg_nli1l0i4156w4158w(0) AND nli1iOl; + wire_w_lg_w_lg_w_lg_nliii1O2007w2009w2010w(0) <= wire_w_lg_w_lg_nliii1O2007w2009w(0) AND nlii0Oi; + wire_w_lg_w_lg_w_lg_nliiO0O1471w1473w1474w(0) <= wire_w_lg_w_lg_nliiO0O1471w1473w(0) AND nliiO1i; + wire_w_lg_w_lg_w_lg_nlil0iO934w936w937w(0) <= wire_w_lg_w_lg_nlil0iO934w936w(0) AND nlil00i; + wire_w_lg_w_lg_w_lg_nlilO1O382w384w385w(0) <= wire_w_lg_w_lg_nlilO1O382w384w(0) AND nlillll; + wire_w_lg_nli00Ol3136w(0) <= nli00Ol AND wire_nliii_w_lg_nlOO1ii3135w(0); + wire_w_lg_nli010i3620w(0) <= nli010i AND nlO11lO; + wire_w_lg_nli01ii3619w(0) <= nli01ii AND nlO11Ol; + wire_w_lg_nli01Oi3669w(0) <= nli01Oi AND wire_nliii_w_lg_w_lg_nllOO0l3667w3668w(0); + wire_w_lg_nli01Oi3673w(0) <= nli01Oi AND wire_w_lg_nli1Oll3672w(0); + wire_w_lg_nli0iil3084w(0) <= nli0iil AND nlOO0OO; + wire_w_lg_nli0ill3083w(0) <= nli0ill AND nlOOi1l; + wire_w_lg_nli0l1l3133w(0) <= nli0l1l AND wire_nliii_w_lg_w_lg_nlOO1il3131w3132w(0); + wire_w_lg_nli0l1l3137w(0) <= nli0l1l AND wire_w_lg_nli00Ol3136w(0); + wire_w_lg_nli0O1O2598w(0) <= nli0O1O AND wire_nliii_w_lg_n1l0li2597w(0); + wire_w_lg_nli0OlO2546w(0) <= nli0OlO AND n1ll1O; + wire_w_lg_nli0OOO2545w(0) <= nli0OOO AND n1ll0l; + wire_w_lg_nli1iil4209w(0) <= nli1iil AND wire_nliii_w_lg_nll1l1i4208w(0); + wire_w_lg_nli1l0i4156w(0) <= nli1l0i AND nll1Oll; + wire_w_lg_nli1l1i4157w(0) <= nli1l1i AND nll1OiO; + wire_w_lg_nli1lli4206w(0) <= nli1lli AND wire_nliii_w_lg_w_lg_nll1l1l4204w4205w(0); + wire_w_lg_nli1lli4210w(0) <= nli1lli AND wire_w_lg_nli1iil4209w(0); + wire_w_lg_nli1Oll3672w(0) <= nli1Oll AND wire_nliii_w_lg_nllOO0i3671w(0); + wire_w_lg_nlii0ii2060w(0) <= nlii0ii AND wire_nliii_w_lg_n0iiOi2059w(0); + wire_w_lg_nlii0OO2008w(0) <= nlii0OO AND n0iO0O; + wire_w_lg_nlii10O2595w(0) <= nlii10O AND wire_nliii_w_lg_w_lg_n1l0ll2593w2594w(0); + wire_w_lg_nlii10O2599w(0) <= nlii10O AND wire_w_lg_nli0O1O2598w(0); + wire_w_lg_nliii1O2007w(0) <= nliii1O AND n0iOil; + wire_w_lg_nliiiiO2057w(0) <= nliiiiO AND wire_nliii_w_lg_w_lg_n0iiOl2055w2056w(0); + wire_w_lg_nliiiiO2061w(0) <= nliiiiO AND wire_w_lg_nlii0ii2060w(0); + wire_w_lg_nliilli1524w(0) <= nliilli AND wire_nliii_w_lg_ni0O1i1523w(0); + wire_w_lg_nliiO0O1471w(0) <= nliiO0O AND nii1ll; + wire_w_lg_nliiO1O1472w(0) <= nliiO1O AND nii1iO; + wire_w_lg_nliiOlO1521w(0) <= nliiOlO AND wire_nliii_w_lg_w_lg_ni0O1l1519w1520w(0); + wire_w_lg_nliiOlO1525w(0) <= nliiOlO AND wire_w_lg_nliilli1524w(0); + wire_w_lg_nlil00O935w(0) <= nlil00O AND nl00lO; + wire_w_lg_nlil0iO934w(0) <= nlil0iO AND nl00Ol; + wire_w_lg_nlil0OO984w(0) <= nlil0OO AND wire_nliii_w_lg_w_lg_nl010l982w983w(0); + wire_w_lg_nlil0OO988w(0) <= nlil0OO AND wire_w_lg_nlil1Oi987w(0); + wire_w_lg_nlil1Oi987w(0) <= nlil1Oi AND wire_nliii_w_lg_nl010i986w(0); + wire_w_lg_nlill0l435w(0) <= nlill0l AND wire_nliii_w_lg_n10li434w(0); + wire_w_lg_nlillOi383w(0) <= nlillOi AND n1l1O; + wire_w_lg_nlilO1O382w(0) <= nlilO1O AND n1l0l; + wire_w_lg_nlilOOi432w(0) <= nlilOOi AND wire_nliii_w_lg_w_lg_n10ll430w431w(0); + wire_w_lg_nlilOOi436w(0) <= nlilOOi AND wire_w_lg_nlill0l435w(0); + wire_w_lg_w_enable_inf_ei_range40w540w(0) <= wire_w_enable_inf_ei_range40w(0) AND wire_w_lg_w_enable_inf_ei_range41w539w(0); + wire_w_lg_nli00lO3310w(0) <= NOT nli00lO; + wire_w_lg_nli01li3598w(0) <= NOT nli01li; + wire_w_lg_nli01ll3615w(0) <= NOT nli01ll; + wire_w_lg_nli01Oi3676w(0) <= NOT nli01Oi; + wire_w_lg_nli01OO3675w(0) <= NOT nli01OO; + wire_w_lg_nli0i1O3024w(0) <= NOT nli0i1O; + wire_w_lg_nli0iOl3060w(0) <= NOT nli0iOl; + wire_w_lg_nli0iOO3077w(0) <= NOT nli0iOO; + wire_w_lg_nli0l0i3139w(0) <= NOT nli0l0i; + wire_w_lg_nli0l1l3140w(0) <= NOT nli0l1l; + wire_w_lg_nli0O1i2772w(0) <= NOT nli0O1i; + wire_w_lg_nli0Oii2486w(0) <= NOT nli0Oii; + wire_w_lg_nli1i0O4383w(0) <= NOT nli1i0O; + wire_w_lg_nli1ill4098w(0) <= NOT nli1ill; + wire_w_lg_nli1lii4134w(0) <= NOT nli1lii; + wire_w_lg_nli1lil4151w(0) <= NOT nli1lil; + wire_w_lg_nli1lli4213w(0) <= NOT nli1lli; + wire_w_lg_nli1llO4212w(0) <= NOT nli1llO; + wire_w_lg_nli1OiO3846w(0) <= NOT nli1OiO; + wire_w_lg_nli1OOl3562w(0) <= NOT nli1OOl; + wire_w_lg_nlii00l2234w(0) <= NOT nlii00l; + wire_w_lg_nlii0li1950w(0) <= NOT nlii0li; + wire_w_lg_nlii10i2539w(0) <= NOT nlii10i; + wire_w_lg_nlii10O2602w(0) <= NOT nlii10O; + wire_w_lg_nlii11O2522w(0) <= NOT nlii11O; + wire_w_lg_nlii1il2601w(0) <= NOT nlii1il; + wire_w_lg_nliii0O1986w(0) <= NOT nliii0O; + wire_w_lg_nliiiii2003w(0) <= NOT nliiiii; + wire_w_lg_nliiiiO2064w(0) <= NOT nliiiiO; + wire_w_lg_nliiill2063w(0) <= NOT nliiill; + wire_w_lg_nliilil1698w(0) <= NOT nliilil; + wire_w_lg_nliilOi1413w(0) <= NOT nliilOi; + wire_w_lg_nliiOiO1449w(0) <= NOT nliiOiO; + wire_w_lg_nliiOli1466w(0) <= NOT nliiOli; + wire_w_lg_nliiOlO1528w(0) <= NOT nliiOlO; + wire_w_lg_nliiOOl1527w(0) <= NOT nliiOOl; + wire_w_lg_nlil01i877w(0) <= NOT nlil01i; + wire_w_lg_nlil0lO913w(0) <= NOT nlil0lO; + wire_w_lg_nlil0Oi930w(0) <= NOT nlil0Oi; + wire_w_lg_nlil0OO991w(0) <= NOT nlil0OO; + wire_w_lg_nlil1ll1161w(0) <= NOT nlil1ll; + wire_w_lg_nlili1l990w(0) <= NOT nlili1l; + wire_w_lg_nlill1O620w(0) <= NOT nlill1O; + wire_w_lg_nlillil325w(0) <= NOT nlillil; + wire_w_lg_nlilOil361w(0) <= NOT nlilOil; + wire_w_lg_nlilOll378w(0) <= NOT nlilOll; + wire_w_lg_nlilOOi439w(0) <= NOT nlilOOi; + wire_w_lg_nlilOOO438w(0) <= NOT nlilOOO; + wire_w_lg_test_in_0466w(0) <= NOT test_in_0; + wire_w_lg_w_enable_inf_ei_range41w539w(0) <= NOT wire_w_enable_inf_ei_range41w(0); + wire_w_lg_w_lg_nli01ii3619w3621w(0) <= wire_w_lg_nli01ii3619w(0) OR wire_w_lg_nli010i3620w(0); + wire_w_lg_w_lg_nli0ill3083w3085w(0) <= wire_w_lg_nli0ill3083w(0) OR wire_w_lg_nli0iil3084w(0); + wire_w_lg_w_lg_nli0OOO2545w2547w(0) <= wire_w_lg_nli0OOO2545w(0) OR wire_w_lg_nli0OlO2546w(0); + wire_w_lg_w_lg_nli1l0i4156w4158w(0) <= wire_w_lg_nli1l0i4156w(0) OR wire_w_lg_nli1l1i4157w(0); + wire_w_lg_w_lg_nliii1O2007w2009w(0) <= wire_w_lg_nliii1O2007w(0) OR wire_w_lg_nlii0OO2008w(0); + wire_w_lg_w_lg_nliiO0O1471w1473w(0) <= wire_w_lg_nliiO0O1471w(0) OR wire_w_lg_nliiO1O1472w(0); + wire_w_lg_w_lg_nlil0iO934w936w(0) <= wire_w_lg_nlil0iO934w(0) OR wire_w_lg_nlil00O935w(0); + wire_w_lg_w_lg_nlilO1O382w384w(0) <= wire_w_lg_nlilO1O382w(0) OR wire_w_lg_nlillOi383w(0); + wire_w_lg_nlilO1l293w(0) <= nlilO1l OR nlilO1i; + wire_w_lg_w_eidleinfersel_range23w200w(0) <= wire_w_eidleinfersel_range23w(0) XOR nl0li; + wire_w_lg_w_eidleinfersel_range22w207w(0) <= wire_w_eidleinfersel_range22w(0) XOR nl0ll; + nli000i <= ((((((nlO0lil AND nlO0lii) AND nlO0l0O) AND nlO0l0l) AND nlO0l0i) AND nlO0l1O) AND nlO0l1l); + nli000l <= ((((wire_nliii_w3766w(0) AND wire_nliii_w_lg_nlO01lO3751w(0)) AND (NOT (test_in_0 XOR nlO01Ol))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO01OO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO000i))); + nli000O <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO001O3746w3747w3749w3750w(0) AND wire_nliii_w_lg_nlO01lO3751w(0)) AND (NOT (test_in_0 XOR nlO01Oi))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO000i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO000l))); + nli001i <= (((wire_nliii_w3780w(0) AND wire_nliii_w_lg_nlOiOiO3781w(0)) AND wire_nliii_w_lg_nlOiOil3783w(0)) AND nlOiOii); + nli001l <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nli001O <= ((((((nlO0l1i AND nlO0iOO) AND nlO0iOl) AND nlO0iOi) AND nlO0ilO) AND nlO0ill) AND nlO0ili); + nli00ii <= (wire_nliii_w_lg_w_lg_w_lg_w3729w3730w3732w3744w(0) AND wire_nliii_w_lg_nlO00ll3698w(0)); + nli00il <= ((((wire_nliii_w3729w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO00ll))) AND (NOT (test_in_0 XOR nlO00lO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO00Oi))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO00Ol))); + nli00iO <= ((wire_nliii_w_lg_w_lg_w3729w3730w3732w(0) AND wire_nliii_w_lg_nlO00lO3733w(0)) AND nlO00ll); + nli00li <= ((((wire_nliii_w3713w(0) AND wire_nliii_w_lg_nlO00ll3698w(0)) AND (NOT (test_in_0 XOR nlO00Oi))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO00Ol))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO0i1O))); + nli00ll <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i1l3693w3694w3696w3697w(0) AND wire_nliii_w_lg_nlO00ll3698w(0)) AND (NOT (test_in_0 XOR nlO00lO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO0i1O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlO0i0i))); + nli00lO <= (nlOl1iO XOR nlOl10l); + nli00Oi <= (((wire_nliii_w_lg_w3263w3264w(0) AND wire_nliii_w_lg_n1i1lO3245w(0)) AND wire_nliii_w_lg_n1i1ll3247w(0)) AND n1i1li); + nli00Ol <= (nlOO1il AND nlOO10O); + nli010i <= (nlOiO0O AND (nli010O OR nli010l)); + nli010l <= (wire_nliii_w_lg_w_lg_w_lg_w3831w3832w3833w3834w(0) AND wire_nliii_w_lg_nlOiOii3529w(0)); + nli010O <= ((wire_nliii_w_lg_w3827w3828w(0) AND wire_nliii_w_lg_nlOiOil3783w(0)) AND wire_nliii_w_lg_nlOiOii3529w(0)); + nli011i <= (wire_nl01l_w_lg_w_lg_nlO101O3600w3602w(0) AND nlO11OO); + nli011l <= (((wire_nl01l_w_lg_nlO101O3838w(0) AND wire_nl01l_w_lg_nlO101l3606w(0)) AND wire_nl01l_w_lg_nlO101i3601w(0)) AND wire_nl01l_w_lg_nlO11OO3603w(0)); + nli011O <= ((nli01ll OR nli01li) AND nlO100i); + nli01ii <= (nlOiO0O AND (nli01iO OR nli01il)); + nli01il <= ((wire_nliii_w_lg_w_lg_w3821w3823w3824w(0) AND wire_nliii_w_lg_nlOiOil3783w(0)) AND wire_nliii_w_lg_nlOiOii3529w(0)); + nli01iO <= (wire_nliii_w_lg_w_lg_w3814w3815w3816w(0) AND wire_nliii_w_lg_nlOiOii3529w(0)); + nli01li <= (wire_nliii_w_lg_nlOiOii3529w(0) AND nlOiO0O); + nli01ll <= (nlOiO0O AND nli01lO); + nli01lO <= (((((wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3804w3805w3806w(0) AND wire_nliii_w_lg_nlOiOll3807w(0)) AND nlOiOli) AND nlOiOiO) AND nlOiOil) AND nlOiOii); + nli01Oi <= (nlOiO0O AND nli01Ol); + nli01Ol <= (((wire_nliii_w_lg_w3790w3791w(0) AND wire_nliii_w_lg_nlOiOiO3781w(0)) AND wire_nliii_w_lg_nlOiOil3783w(0)) AND nlOiOii); + nli01OO <= (nlOiO0O AND nli001i); + nli0i0i <= ((nli0iOl OR nli0i0O) OR (nli0iOO AND nli0i0l)); + nli0i0l <= (wire_nl01l_w_lg_w_lg_nlOOi0O3062w3064w(0) AND nlOOi1O); + nli0i0O <= (((wire_nl01l_w_lg_nlOOi0O3302w(0) AND wire_nl01l_w_lg_nlOOi0l3068w(0)) AND wire_nl01l_w_lg_nlOOi0i3063w(0)) AND wire_nl01l_w_lg_nlOOi1O3065w(0)); + nli0i1l <= (wire_nl01l_w_lg_w_lg_nlOOi0O3069w3070w(0) AND nlOOi1O); + nli0i1O <= ((wire_nl01l_w_lg_nlOOi0O3062w(0) AND nlOOi0i) AND nlOOi1O); + nli0iii <= ((nli0iOO OR nli0iOl) AND nlOOiii); + nli0iil <= (n1i1iO AND (nli0ili OR nli0iiO)); + nli0iiO <= (wire_nliii_w_lg_w_lg_w_lg_w3295w3296w3297w3298w(0) AND wire_nliii_w_lg_n1i1li2991w(0)); + nli0ili <= ((wire_nliii_w_lg_w3291w3292w(0) AND wire_nliii_w_lg_n1i1ll3247w(0)) AND wire_nliii_w_lg_n1i1li2991w(0)); + nli0ill <= (n1i1iO AND (nli0iOi OR nli0ilO)); + nli0ilO <= ((wire_nliii_w_lg_w_lg_w3285w3287w3288w(0) AND wire_nliii_w_lg_n1i1ll3247w(0)) AND wire_nliii_w_lg_n1i1li2991w(0)); + nli0iOi <= (wire_nliii_w_lg_w_lg_w3278w3279w3280w(0) AND wire_nliii_w_lg_n1i1li2991w(0)); + nli0iOl <= (wire_nliii_w_lg_n1i1li2991w(0) AND n1i1iO); + nli0iOO <= (n1i1iO AND nli0l1i); + nli0l0i <= (n1i1iO AND nli0l0l); + nli0l0l <= (((wire_nliii_w3244w(0) AND wire_nliii_w_lg_n1i1lO3245w(0)) AND wire_nliii_w_lg_n1i1ll3247w(0)) AND n1i1li); + nli0l0O <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nli0l1i <= (((((wire_nliii_w_lg_w_lg_w_lg_n1i01O3268w3269w3270w(0) AND wire_nliii_w_lg_n1i1Ol3271w(0)) AND n1i1Oi) AND n1i1lO) AND n1i1ll) AND n1i1li); + nli0l1l <= (n1i1iO AND nli0l1O); + nli0l1O <= (((wire_nliii_w_lg_w3254w3255w(0) AND wire_nliii_w_lg_n1i1lO3245w(0)) AND wire_nliii_w_lg_n1i1ll3247w(0)) AND n1i1li); + nli0lii <= ((((((n11O0i AND n11O1O) AND n11O1l) AND n11O1i) AND n11lOO) AND n11lOl) AND n11lOi); + nli0lil <= ((((((n11Oll AND n11Oli) AND n11OiO) AND n11Oil) AND n11Oii) AND n11O0O) AND n11O0l); + nli0liO <= ((((wire_nliii_w3230w(0) AND wire_nliii_w_lg_n110OO3215w(0)) AND (NOT (test_in_0 XOR n11i1l))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11i1O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11iii))); + nli0lli <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n11i0O3210w3211w3213w3214w(0) AND wire_nliii_w_lg_n110OO3215w(0)) AND (NOT (test_in_0 XOR n11i1i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11iii))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11iil))); + nli0lll <= (wire_nliii_w_lg_w_lg_w_lg_w3193w3194w3196w3208w(0) AND wire_nliii_w_lg_n11iOl3162w(0)); + nli0llO <= ((((wire_nliii_w3193w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11iOl))) AND (NOT (test_in_0 XOR n11iOO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11l1i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11l1l))); + nli0lOi <= ((wire_nliii_w_lg_w_lg_w3193w3194w3196w(0) AND wire_nliii_w_lg_n11iOO3197w(0)) AND n11iOl); + nli0lOl <= ((((wire_nliii_w3177w(0) AND wire_nliii_w_lg_n11iOl3162w(0)) AND (NOT (test_in_0 XOR n11l1i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11l1l))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11l0O))); + nli0lOO <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n11l0l3157w3158w3160w3161w(0) AND wire_nliii_w_lg_n11iOl3162w(0)) AND (NOT (test_in_0 XOR n11iOO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11l0O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n11lii))); + nli0O0O <= (wire_nl01l_w_lg_w_lg_n1lliO2531w2532w(0) AND n1ll0O); + nli0O1i <= (n1i0lO XOR n1i0il); + nli0O1l <= (((wire_nliii_w_lg_w2725w2726w(0) AND wire_nliii_w_lg_n000OO2707w(0)) AND wire_nliii_w_lg_n000Ol2709w(0)) AND n000Oi); + nli0O1O <= (n1l0ll AND n1l0iO); + nli0Oii <= ((wire_nl01l_w_lg_n1lliO2524w(0) AND n1llii) AND n1ll0O); + nli0Oil <= ((nlii11O OR nli0Oli) OR (nlii10i AND nli0OiO)); + nli0OiO <= (wire_nl01l_w_lg_w_lg_n1lliO2524w2526w(0) AND n1ll0O); + nli0Oli <= (((wire_nl01l_w_lg_n1lliO2764w(0) AND wire_nl01l_w_lg_n1llil2530w(0)) AND wire_nl01l_w_lg_n1llii2525w(0)) AND wire_nl01l_w_lg_n1ll0O2527w(0)); + nli0Oll <= ((nlii10i OR nlii11O) AND n1llli); + nli0OlO <= (n000lO AND (nli0OOl OR nli0OOi)); + nli0OOi <= (wire_nliii_w_lg_w_lg_w_lg_w2757w2758w2759w2760w(0) AND wire_nliii_w_lg_n000Oi2453w(0)); + nli0OOl <= ((wire_nliii_w_lg_w2753w2754w(0) AND wire_nliii_w_lg_n000Ol2709w(0)) AND wire_nliii_w_lg_n000Oi2453w(0)); + nli0OOO <= (n000lO AND (nlii11l OR nlii11i)); + nli1i0O <= (nliOl1O XOR nliOiOl); + nli1iii <= (((wire_nliii_w_lg_w4336w4337w(0) AND wire_nliii_w_lg_nllll0O4318w(0)) AND wire_nliii_w_lg_nllll0l4320w(0)) AND nllll0i); + nli1iil <= (nll1l1l AND nll1iOO); + nli1ili <= (wire_nl01l_w_lg_w_lg_nll1OOO4143w4144w(0) AND nll1OlO); + nli1ill <= ((wire_nl01l_w_lg_nll1OOO4136w(0) AND nll1OOi) AND nll1OlO); + nli1ilO <= ((nli1lii OR nli1iOl) OR (nli1lil AND nli1iOi)); + nli1iOi <= (wire_nl01l_w_lg_w_lg_nll1OOO4136w4138w(0) AND nll1OlO); + nli1iOl <= (((wire_nl01l_w_lg_nll1OOO4375w(0) AND wire_nl01l_w_lg_nll1OOl4142w(0)) AND wire_nl01l_w_lg_nll1OOi4137w(0)) AND wire_nl01l_w_lg_nll1OlO4139w(0)); + nli1iOO <= ((nli1lil OR nli1lii) AND nll011i); + nli1l0i <= (nllll1O AND (nli1l0O OR nli1l0l)); + nli1l0l <= ((wire_nliii_w_lg_w_lg_w4358w4360w4361w(0) AND wire_nliii_w_lg_nllll0l4320w(0)) AND wire_nliii_w_lg_nllll0i4065w(0)); + nli1l0O <= (wire_nliii_w_lg_w_lg_w4351w4352w4353w(0) AND wire_nliii_w_lg_nllll0i4065w(0)); + nli1l1i <= (nllll1O AND (nli1l1O OR nli1l1l)); + nli1l1l <= (wire_nliii_w_lg_w_lg_w_lg_w4368w4369w4370w4371w(0) AND wire_nliii_w_lg_nllll0i4065w(0)); + nli1l1O <= ((wire_nliii_w_lg_w4364w4365w(0) AND wire_nliii_w_lg_nllll0l4320w(0)) AND wire_nliii_w_lg_nllll0i4065w(0)); + nli1lii <= (wire_nliii_w_lg_nllll0i4065w(0) AND nllll1O); + nli1lil <= (nllll1O AND nli1liO); + nli1liO <= (((((wire_nliii_w_lg_w_lg_w_lg_nlllllO4341w4342w4343w(0) AND wire_nliii_w_lg_nllllil4344w(0)) AND nllllii) AND nllll0O) AND nllll0l) AND nllll0i); + nli1lli <= (nllll1O AND nli1lll); + nli1lll <= (((wire_nliii_w_lg_w4327w4328w(0) AND wire_nliii_w_lg_nllll0O4318w(0)) AND wire_nliii_w_lg_nllll0l4320w(0)) AND nllll0i); + nli1llO <= (nllll1O AND nli1lOi); + nli1lOi <= (((wire_nliii_w4317w(0) AND wire_nliii_w_lg_nllll0O4318w(0)) AND wire_nliii_w_lg_nllll0l4320w(0)) AND nllll0i); + nli1lOl <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nli1lOO <= ((((((nlli0Oi AND nlli0lO) AND nlli0ll) AND nlli0li) AND nlli0iO) AND nlli0il) AND nlli0ii); + nli1O0i <= (wire_nliii_w_lg_w_lg_w_lg_w4266w4267w4269w4281w(0) AND wire_nliii_w_lg_nlli1il4235w(0)); + nli1O0l <= ((((wire_nliii_w4266w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli1il))) AND (NOT (test_in_0 XOR nlli1iO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli1li))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli1ll))); + nli1O0O <= ((wire_nliii_w_lg_w_lg_w4266w4267w4269w(0) AND wire_nliii_w_lg_nlli1iO4270w(0)) AND nlli1il); + nli1O1i <= ((((((nllii0l AND nllii0i) AND nllii1O) AND nllii1l) AND nllii1i) AND nlli0OO) AND nlli0Ol); + nli1O1l <= ((((wire_nliii_w4303w(0) AND wire_nliii_w_lg_nll0OiO4288w(0)) AND (NOT (test_in_0 XOR nll0Oll))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nll0OlO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli11i))); + nli1O1O <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nll0OOO4283w4284w4286w4287w(0) AND wire_nliii_w_lg_nll0OiO4288w(0)) AND (NOT (test_in_0 XOR nll0Oli))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli11i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli11l))); + nli1Oii <= ((((wire_nliii_w4250w(0) AND wire_nliii_w_lg_nlli1il4235w(0)) AND (NOT (test_in_0 XOR nlli1li))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli1ll))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli1OO))); + nli1Oil <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli1Ol4230w4231w4233w4234w(0) AND wire_nliii_w_lg_nlli1il4235w(0)) AND (NOT (test_in_0 XOR nlli1iO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli1OO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlli01i))); + nli1OiO <= (nlllO0O XOR nlllO1l); + nli1Oli <= (((wire_nliii_w_lg_w3799w3800w(0) AND wire_nliii_w_lg_nlOiOiO3781w(0)) AND wire_nliii_w_lg_nlOiOil3783w(0)) AND nlOiOii); + nli1Oll <= (nllOO0l AND nllOO1O); + nli1OOi <= (wire_nl01l_w_lg_w_lg_nlO101O3607w3608w(0) AND nlO11OO); + nli1OOl <= ((wire_nl01l_w_lg_nlO101O3600w(0) AND nlO101i) AND nlO11OO); + nli1OOO <= ((nli01li OR nli011l) OR (nli01ll AND nli011i)); + nlii00i <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOil2619w2620w2622w2623w(0) AND wire_nliii_w_lg_n1OO1l2624w(0)) AND (NOT (test_in_0 XOR n1OO1O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1OOiO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1OOli))); + nlii00l <= (n00iOO XOR n00ill); + nlii00O <= (((wire_nliii_w_lg_w2187w2188w(0) AND wire_nliii_w_lg_ni1l1O2169w(0)) AND wire_nliii_w_lg_ni1l1l2171w(0)) AND ni1l1i); + nlii01i <= ((((wire_nliii_w2655w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1OO1l))) AND (NOT (test_in_0 XOR n1OO1O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1OO0i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1OO0l))); + nlii01l <= ((wire_nliii_w_lg_w_lg_w2655w2656w2658w(0) AND wire_nliii_w_lg_n1OO1O2659w(0)) AND n1OO1l); + nlii01O <= ((((wire_nliii_w2639w(0) AND wire_nliii_w_lg_n1OO1l2624w(0)) AND (NOT (test_in_0 XOR n1OO0i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1OO0l))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1OOiO))); + nlii0ii <= (n0iiOl AND n0iilO); + nlii0iO <= (wire_nl01l_w_lg_w_lg_n0iOlO1995w1996w(0) AND n0iOiO); + nlii0li <= ((wire_nl01l_w_lg_n0iOlO1988w(0) AND n0iOli) AND n0iOiO); + nlii0ll <= ((nliii0O OR nlii0Oi) OR (nliiiii AND nlii0lO)); + nlii0lO <= (wire_nl01l_w_lg_w_lg_n0iOlO1988w1990w(0) AND n0iOiO); + nlii0Oi <= (((wire_nl01l_w_lg_n0iOlO2226w(0) AND wire_nl01l_w_lg_n0iOll1994w(0)) AND wire_nl01l_w_lg_n0iOli1989w(0)) AND wire_nl01l_w_lg_n0iOiO1991w(0)); + nlii0Ol <= ((nliiiii OR nliii0O) AND n0iOOi); + nlii0OO <= (ni1iOO AND (nliii1l OR nliii1i)); + nlii10i <= (n000lO AND nlii10l); + nlii10l <= (((((wire_nliii_w_lg_w_lg_w_lg_n00i0O2730w2731w2732w(0) AND wire_nliii_w_lg_n00i1l2733w(0)) AND n00i1i) AND n000OO) AND n000Ol) AND n000Oi); + nlii10O <= (n000lO AND nlii1ii); + nlii11i <= ((wire_nliii_w_lg_w_lg_w2747w2749w2750w(0) AND wire_nliii_w_lg_n000Ol2709w(0)) AND wire_nliii_w_lg_n000Oi2453w(0)); + nlii11l <= (wire_nliii_w_lg_w_lg_w2740w2741w2742w(0) AND wire_nliii_w_lg_n000Oi2453w(0)); + nlii11O <= (wire_nliii_w_lg_n000Oi2453w(0) AND n000lO); + nlii1ii <= (((wire_nliii_w_lg_w2716w2717w(0) AND wire_nliii_w_lg_n000OO2707w(0)) AND wire_nliii_w_lg_n000Ol2709w(0)) AND n000Oi); + nlii1il <= (n000lO AND nlii1iO); + nlii1iO <= (((wire_nliii_w2706w(0) AND wire_nliii_w_lg_n000OO2707w(0)) AND wire_nliii_w_lg_n000Ol2709w(0)) AND n000Oi); + nlii1li <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nlii1ll <= ((((((n011ii AND n0110O) AND n0110l) AND n0110i) AND n0111O) AND n0111l) AND n0111i); + nlii1lO <= ((((((n011Ol AND n011Oi) AND n011lO) AND n011ll) AND n011li) AND n011iO) AND n011il); + nlii1Oi <= ((((wire_nliii_w2692w(0) AND wire_nliii_w_lg_n1Ol1O2677w(0)) AND (NOT (test_in_0 XOR n1Ol0l))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1Ol0O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1Olli))); + nlii1Ol <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OliO2672w2673w2675w2676w(0) AND wire_nliii_w_lg_n1Ol1O2677w(0)) AND (NOT (test_in_0 XOR n1Ol0i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1Olli))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n1Olll))); + nlii1OO <= (wire_nliii_w_lg_w_lg_w_lg_w2655w2656w2658w2670w(0) AND wire_nliii_w_lg_n1OO1l2624w(0)); + nliii0i <= ((wire_nliii_w_lg_w_lg_w2209w2211w2212w(0) AND wire_nliii_w_lg_ni1l1l2171w(0)) AND wire_nliii_w_lg_ni1l1i1917w(0)); + nliii0l <= (wire_nliii_w_lg_w_lg_w2202w2203w2204w(0) AND wire_nliii_w_lg_ni1l1i1917w(0)); + nliii0O <= (wire_nliii_w_lg_ni1l1i1917w(0) AND ni1iOO); + nliii1i <= (wire_nliii_w_lg_w_lg_w_lg_w2219w2220w2221w2222w(0) AND wire_nliii_w_lg_ni1l1i1917w(0)); + nliii1l <= ((wire_nliii_w_lg_w2215w2216w(0) AND wire_nliii_w_lg_ni1l1l2171w(0)) AND wire_nliii_w_lg_ni1l1i1917w(0)); + nliii1O <= (ni1iOO AND (nliii0l OR nliii0i)); + nliiiii <= (ni1iOO AND nliiiil); + nliiiil <= (((((wire_nliii_w_lg_w_lg_w_lg_ni1liO2192w2193w2194w(0) AND wire_nliii_w_lg_ni1l0l2195w(0)) AND ni1l0i) AND ni1l1O) AND ni1l1l) AND ni1l1i); + nliiiiO <= (ni1iOO AND nliiili); + nliiili <= (((wire_nliii_w_lg_w2178w2179w(0) AND wire_nliii_w_lg_ni1l1O2169w(0)) AND wire_nliii_w_lg_ni1l1l2171w(0)) AND ni1l1i); + nliiill <= (ni1iOO AND nliiilO); + nliiilO <= (((wire_nliii_w2168w(0) AND wire_nliii_w_lg_ni1l1O2169w(0)) AND wire_nliii_w_lg_ni1l1l2171w(0)) AND ni1l1i); + nliiiOi <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nliiiOl <= ((((((n0O0li AND n0O0iO) AND n0O0il) AND n0O0ii) AND n0O00O) AND n0O00l) AND n0O00i); + nliiiOO <= ((((((n0Oi1l AND n0Oi1i) AND n0O0OO) AND n0O0Ol) AND n0O0Oi) AND n0O0lO) AND n0O0ll); + nliil0i <= ((((wire_nliii_w2117w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O10l))) AND (NOT (test_in_0 XOR n0O10O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O1ii))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O1il))); + nliil0l <= ((wire_nliii_w_lg_w_lg_w2117w2118w2120w(0) AND wire_nliii_w_lg_n0O10O2121w(0)) AND n0O10l); + nliil0O <= ((((wire_nliii_w2101w(0) AND wire_nliii_w_lg_n0O10l2086w(0)) AND (NOT (test_in_0 XOR n0O1ii))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O1il))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O1lO))); + nliil1i <= ((((wire_nliii_w2154w(0) AND wire_nliii_w_lg_n0lO0O2139w(0)) AND (NOT (test_in_0 XOR n0lOil))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0lOiO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0lOOi))); + nliil1l <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lOlO2134w2135w2137w2138w(0) AND wire_nliii_w_lg_n0lO0O2139w(0)) AND (NOT (test_in_0 XOR n0lOii))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0lOOi))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0lOOl))); + nliil1O <= (wire_nliii_w_lg_w_lg_w_lg_w2117w2118w2120w2132w(0) AND wire_nliii_w_lg_n0O10l2086w(0)); + nliilii <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1ll2081w2082w2084w2085w(0) AND wire_nliii_w_lg_n0O10l2086w(0)) AND (NOT (test_in_0 XOR n0O10O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O1lO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O1Oi))); + nliilil <= (ni1O1O XOR ni1lOl); + nliiliO <= (((wire_nliii_w_lg_w1651w1652w(0) AND wire_nliii_w_lg_niOO0O1633w(0)) AND wire_nliii_w_lg_niOO0l1635w(0)) AND niOO0i); + nliilli <= (ni0O1l AND ni0lOO); + nliillO <= (wire_nl01l_w_lg_w_lg_nii1OO1458w1459w(0) AND nii1lO); + nliilOi <= ((wire_nl01l_w_lg_nii1OO1451w(0) AND nii1Oi) AND nii1lO); + nliilOl <= ((nliiOiO OR nliiO1i) OR (nliiOli AND nliilOO)); + nliilOO <= (wire_nl01l_w_lg_w_lg_nii1OO1451w1453w(0) AND nii1lO); + nliiO0i <= (wire_nliii_w_lg_w_lg_w_lg_w1683w1684w1685w1686w(0) AND wire_nliii_w_lg_niOO0i1380w(0)); + nliiO0l <= ((wire_nliii_w_lg_w1679w1680w(0) AND wire_nliii_w_lg_niOO0l1635w(0)) AND wire_nliii_w_lg_niOO0i1380w(0)); + nliiO0O <= (niOO1O AND (nliiOil OR nliiOii)); + nliiO1i <= (((wire_nl01l_w_lg_nii1OO1690w(0) AND wire_nl01l_w_lg_nii1Ol1457w(0)) AND wire_nl01l_w_lg_nii1Oi1452w(0)) AND wire_nl01l_w_lg_nii1lO1454w(0)); + nliiO1l <= ((nliiOli OR nliiOiO) AND nii01i); + nliiO1O <= (niOO1O AND (nliiO0l OR nliiO0i)); + nliiOii <= ((wire_nliii_w_lg_w_lg_w1673w1675w1676w(0) AND wire_nliii_w_lg_niOO0l1635w(0)) AND wire_nliii_w_lg_niOO0i1380w(0)); + nliiOil <= (wire_nliii_w_lg_w_lg_w1666w1667w1668w(0) AND wire_nliii_w_lg_niOO0i1380w(0)); + nliiOiO <= (wire_nliii_w_lg_niOO0i1380w(0) AND niOO1O); + nliiOli <= (niOO1O AND nliiOll); + nliiOll <= (((((wire_nliii_w_lg_w_lg_w_lg_niOOlO1656w1657w1658w(0) AND wire_nliii_w_lg_niOOil1659w(0)) AND niOOii) AND niOO0O) AND niOO0l) AND niOO0i); + nliiOlO <= (niOO1O AND nliiOOi); + nliiOOi <= (((wire_nliii_w_lg_w1642w1643w(0) AND wire_nliii_w_lg_niOO0O1633w(0)) AND wire_nliii_w_lg_niOO0l1635w(0)) AND niOO0i); + nliiOOl <= (niOO1O AND nliiOOO); + nliiOOO <= (((wire_nliii_w1632w(0) AND wire_nliii_w_lg_niOO0O1633w(0)) AND wire_nliii_w_lg_niOO0l1635w(0)) AND niOO0i); + nlil00i <= (((wire_nl01l_w_lg_nl0i1O1153w(0) AND wire_nl01l_w_lg_nl0i1l921w(0)) AND wire_nl01l_w_lg_nl0i1i916w(0)) AND wire_nl01l_w_lg_nl00OO918w(0)); + nlil00l <= ((nlil0Oi OR nlil0lO) AND nl0i0i); + nlil00O <= (nlO10O AND (nlil0il OR nlil0ii)); + nlil01i <= ((wire_nl01l_w_lg_nl0i1O915w(0) AND nl0i1i) AND nl00OO); + nlil01l <= ((nlil0lO OR nlil00i) OR (nlil0Oi AND nlil01O)); + nlil01O <= (wire_nl01l_w_lg_w_lg_nl0i1O915w917w(0) AND nl00OO); + nlil0ii <= (wire_nliii_w_lg_w_lg_w_lg_w1146w1147w1148w1149w(0) AND wire_nliii_w_lg_nlO1ii844w(0)); + nlil0il <= ((wire_nliii_w_lg_w1142w1143w(0) AND wire_nliii_w_lg_nlO1il1098w(0)) AND wire_nliii_w_lg_nlO1ii844w(0)); + nlil0iO <= (nlO10O AND (nlil0ll OR nlil0li)); + nlil0li <= ((wire_nliii_w_lg_w_lg_w1136w1138w1139w(0) AND wire_nliii_w_lg_nlO1il1098w(0)) AND wire_nliii_w_lg_nlO1ii844w(0)); + nlil0ll <= (wire_nliii_w_lg_w_lg_w1129w1130w1131w(0) AND wire_nliii_w_lg_nlO1ii844w(0)); + nlil0lO <= (wire_nliii_w_lg_nlO1ii844w(0) AND nlO10O); + nlil0Oi <= (nlO10O AND nlil0Ol); + nlil0Ol <= (((((wire_nliii_w_lg_w_lg_w_lg_nlO1OO1119w1120w1121w(0) AND wire_nliii_w_lg_nlO1ll1122w(0)) AND nlO1li) AND nlO1iO) AND nlO1il) AND nlO1ii); + nlil0OO <= (nlO10O AND nlili1i); + nlil10i <= ((((wire_nliii_w1618w(0) AND wire_nliii_w_lg_nil1iO1603w(0)) AND (NOT (test_in_0 XOR nil1ll))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil1lO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil01i))); + nlil10l <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nil1OO1598w1599w1601w1602w(0) AND wire_nliii_w_lg_nil1iO1603w(0)) AND (NOT (test_in_0 XOR nil1li))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil01i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil01l))); + nlil10O <= (wire_nliii_w_lg_w_lg_w_lg_w1581w1582w1584w1596w(0) AND wire_nliii_w_lg_nil0il1550w(0)); + nlil11i <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nlil11l <= ((((((niliOi AND nililO) AND nilill) AND nilili) AND niliiO) AND niliil) AND niliii); + nlil11O <= ((((((nill0l AND nill0i) AND nill1O) AND nill1l) AND nill1i) AND niliOO) AND niliOl); + nlil1ii <= ((((wire_nliii_w1581w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil0il))) AND (NOT (test_in_0 XOR nil0iO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil0li))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil0ll))); + nlil1il <= ((wire_nliii_w_lg_w_lg_w1581w1582w1584w(0) AND wire_nliii_w_lg_nil0iO1585w(0)) AND nil0il); + nlil1iO <= ((((wire_nliii_w1565w(0) AND wire_nliii_w_lg_nil0il1550w(0)) AND (NOT (test_in_0 XOR nil0li))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil0ll))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil0OO))); + nlil1li <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nil0Ol1545w1546w1548w1549w(0) AND wire_nliii_w_lg_nil0il1550w(0)) AND (NOT (test_in_0 XOR nil0iO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nil0OO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nili1i))); + nlil1ll <= (nl110O XOR nl111l); + nlil1lO <= (((wire_nliii_w_lg_w1114w1115w(0) AND wire_nliii_w_lg_nlO1iO1096w(0)) AND wire_nliii_w_lg_nlO1il1098w(0)) AND nlO1ii); + nlil1Oi <= (nl010l AND nl011O); + nlil1OO <= (wire_nl01l_w_lg_w_lg_nl0i1O922w923w(0) AND nl00OO); + nlili0i <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nlili0l <= ((((((nliO1i AND nlilOO) AND nlilOl) AND nlilOi) AND nlillO) AND nlilll) AND nlilli); + nlili0O <= ((((((nliOil AND nliOii) AND nliO0O) AND nliO0l) AND nliO0i) AND nliO1O) AND nliO1l); + nlili1i <= (((wire_nliii_w_lg_w1105w1106w(0) AND wire_nliii_w_lg_nlO1iO1096w(0)) AND wire_nliii_w_lg_nlO1il1098w(0)) AND nlO1ii); + nlili1l <= (nlO10O AND nlili1O); + nlili1O <= (((wire_nliii_w1095w(0) AND wire_nliii_w_lg_nlO1iO1096w(0)) AND wire_nliii_w_lg_nlO1il1098w(0)) AND nlO1ii); + nliliii <= ((((wire_nliii_w1081w(0) AND wire_nliii_w_lg_nli0lO1066w(0)) AND (NOT (test_in_0 XOR nli0Ol))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nli0OO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlii0i))); + nliliil <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nlii1O1061w1062w1064w1065w(0) AND wire_nliii_w_lg_nli0lO1066w(0)) AND (NOT (test_in_0 XOR nli0Oi))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlii0i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlii0l))); + nliliiO <= (wire_nliii_w_lg_w_lg_w_lg_w1044w1045w1047w1059w(0) AND wire_nliii_w_lg_nliill1013w(0)); + nlilili <= ((((wire_nliii_w1044w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nliill))) AND (NOT (test_in_0 XOR nliilO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nliiOi))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nliiOl))); + nlilill <= ((wire_nliii_w_lg_w_lg_w1044w1045w1047w(0) AND wire_nliii_w_lg_nliilO1048w(0)) AND nliill); + nlililO <= ((((wire_nliii_w1028w(0) AND wire_nliii_w_lg_nliill1013w(0)) AND (NOT (test_in_0 XOR nliiOi))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nliiOl))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlil1O))); + nliliOi <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil1l1008w1009w1011w1012w(0) AND wire_nliii_w_lg_nliill1013w(0)) AND (NOT (test_in_0 XOR nliilO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlil1O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR nlil0i))); + nlill0i <= (((wire_nliii_w574w(0) AND wire_nliii_w_lg_nli1i555w(0)) AND wire_nliii_w_lg_nl0OO557w(0)) AND nl0Ol); + nlill0l <= (n10ll AND n10iO); + nlill1O <= (nlO0ll XOR nlO00O); + nlillii <= (wire_nl01l_w_lg_w_lg_n1liO370w371w(0) AND n1l0O); + nlillil <= ((wire_nl01l_w_lg_n1liO363w(0) AND n1lii) AND n1l0O); + nlilliO <= ((nlilOil OR nlillll) OR (nlilOll AND nlillli)); + nlillli <= (wire_nl01l_w_lg_w_lg_n1liO363w365w(0) AND n1l0O); + nlillll <= (((wire_nl01l_w_lg_n1liO612w(0) AND wire_nl01l_w_lg_n1lil369w(0)) AND wire_nl01l_w_lg_n1lii364w(0)) AND wire_nl01l_w_lg_n1l0O366w(0)); + nlilllO <= ((nlilOll OR nlilOil) AND n1lli); + nlillOi <= (wire_nliii_w_lg_nl0Oi294w(0) AND (nlillOl44 XOR nlillOl43)); + nlilO0O <= ((wire_nliii_w_lg_w597w598w(0) AND wire_nliii_w_lg_nl0OO557w(0)) AND wire_nliii_w_lg_nl0Ol282w(0)); + nlilO1i <= (wire_nliii_w_lg_w_lg_w606w607w608w(0) AND wire_nliii_w_lg_nl0Ol282w(0)); + nlilO1l <= ((wire_nliii_w602w(0) AND wire_nliii_w_lg_nl0OO557w(0)) AND wire_nliii_w_lg_nl0Ol282w(0)); + nlilO1O <= (nl0Oi AND ((nlilOii OR nlilO0O) OR (NOT (nlilO0i42 XOR nlilO0i41)))); + nlilOii <= (wire_nliii_w_lg_w589w590w(0) AND wire_nliii_w_lg_nl0Ol282w(0)); + nlilOil <= (wire_nliii_w_lg_w_lg_nl0Ol282w283w(0) AND (nlilOiO40 XOR nlilOiO39)); + nlilOll <= (nl0Oi AND nlilOlO); + nlilOlO <= (((((wire_nliii_w_lg_w_lg_w_lg_nliil578w579w580w(0) AND wire_nliii_w_lg_nli1O581w(0)) AND nli1l) AND nli1i) AND nl0OO) AND nl0Ol); + nlilOOi <= (nl0Oi AND nlilOOl); + nlilOOl <= (((wire_nliii_w565w(0) AND wire_nliii_w_lg_nli1i555w(0)) AND wire_nliii_w_lg_nl0OO557w(0)) AND nl0Ol); + nlilOOO <= ((nl0Oi AND nliO11O) AND (nliO11i38 XOR nliO11i37)); + nliO00i <= (wire_nliii_w_lg_w_lg_w494w496w508w(0) AND wire_nliii_w_lg_n0O1l461w(0)); + nliO00l <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0Oli473w487w489w491w493w(0) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O1l))) AND (NOT (test_in_0 XOR n0O1O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O0i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O0l))); + nliO00O <= ((wire_nliii_w_lg_w494w496w(0) AND wire_nliii_w_lg_n0O1O497w(0)) AND n0O1l); + nliO01i <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0lll526w527w528w529w530w(0) AND wire_nliii_w_lg_n0l1O515w(0)) AND (NOT (test_in_0 XOR n0l0l))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0l0O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0lli))); + nliO01l <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n0liO510w511w513w514w(0) AND wire_nliii_w_lg_n0l1O515w(0)) AND (NOT (test_in_0 XOR n0l0i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0lli))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0lll))); + nliO0ii <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0Oli473w474w475w476w477w(0) AND wire_nliii_w_lg_n0O1l461w(0)) AND (NOT (test_in_0 XOR n0O0i))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0O0l))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0OiO))); + nliO0il <= ((((wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oil456w457w459w460w(0) AND wire_nliii_w_lg_n0O1l461w(0)) AND (NOT (test_in_0 XOR n0O1O))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0OiO))) AND (NOT (wire_w_lg_test_in_0466w(0) XOR n0Oli))); + nliO11O <= (((wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w554w(0) AND wire_nliii_w_lg_nli1i555w(0)) AND wire_nliii_w_lg_nl0OO557w(0)) AND nl0Ol); + nliO1ii <= ((((wire_w_lg_w_enable_inf_ei_range40w540w(0) AND (NOT enable_inf_ei(2))) AND (NOT enable_inf_ei(3))) AND (NOT enable_inf_ei(4))) AND (NOT enable_inf_ei(5))); + nliO1Ol <= ((((((ni1ii AND ni10O) AND ni10l) AND ni10i) AND ni11O) AND ni11l) AND ni11i); + nliO1OO <= ((((((ni1Ol AND ni1Oi) AND ni1lO) AND ni1ll) AND ni1li) AND ni1iO) AND ni1il); + nliOiii <= '1'; + rxelecidle <= ( ni1OO & nliOiO & nill0O & n0Oi1O & n011OO & n11OlO & nlO0liO & nllii0O); + wire_w_eidleinfersel_range23w(0) <= eidleinfersel(1); + wire_w_eidleinfersel_range22w(0) <= eidleinfersel(2); + wire_w_enable_inf_ei_range40w(0) <= enable_inf_ei(0); + wire_w_enable_inf_ei_range41w(0) <= enable_inf_ei(1); + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli00OO67 <= nli00OO68; + END IF; + if (now = 0 ns) then + nli00OO67 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli00OO68 <= nli00OO67; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli0i1i65 <= nli0i1i66; + END IF; + if (now = 0 ns) then + nli0i1i65 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli0i1i66 <= nli0i1i65; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli0O0i63 <= nli0O0i64; + END IF; + if (now = 0 ns) then + nli0O0i63 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli0O0i64 <= nli0O0i63; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli0O0l61 <= nli0O0l62; + END IF; + if (now = 0 ns) then + nli0O0l61 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli0O0l62 <= nli0O0l61; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli1iiO71 <= nli1iiO72; + END IF; + if (now = 0 ns) then + nli1iiO71 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli1iiO72 <= nli1iiO71; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli1OlO69 <= nli1OlO70; + END IF; + if (now = 0 ns) then + nli1OlO69 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nli1OlO70 <= nli1OlO69; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlii0il59 <= nlii0il60; + END IF; + if (now = 0 ns) then + nlii0il59 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlii0il60 <= nlii0il59; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliilll57 <= nliilll58; + END IF; + if (now = 0 ns) then + nliilll57 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliilll58 <= nliilll57; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlil1Ol55 <= nlil1Ol56; + END IF; + if (now = 0 ns) then + nlil1Ol55 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlil1Ol56 <= nlil1Ol55; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliliOl53 <= nliliOl54; + END IF; + if (now = 0 ns) then + nliliOl53 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliliOl54 <= nliliOl53; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliliOO51 <= nliliOO52; + END IF; + if (now = 0 ns) then + nliliOO51 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliliOO52 <= nliliOO51; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlill0O45 <= nlill0O46; + END IF; + if (now = 0 ns) then + nlill0O45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlill0O46 <= nlill0O45; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlill1i49 <= nlill1i50; + END IF; + if (now = 0 ns) then + nlill1i49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlill1i50 <= nlill1i49; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlill1l47 <= nlill1l48; + END IF; + if (now = 0 ns) then + nlill1l47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlill1l48 <= nlill1l47; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlillOl43 <= nlillOl44; + END IF; + if (now = 0 ns) then + nlillOl43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlillOl44 <= nlillOl43; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlilO0i41 <= nlilO0i42; + END IF; + if (now = 0 ns) then + nlilO0i41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlilO0i42 <= nlilO0i41; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlilOiO39 <= nlilOiO40; + END IF; + if (now = 0 ns) then + nlilOiO39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nlilOiO40 <= nlilOiO39; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO01O23 <= nliO01O24; + END IF; + if (now = 0 ns) then + nliO01O23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO01O24 <= nliO01O23; + END IF; + END PROCESS; + wire_nliO01O24_w_lg_w_lg_q161w162w(0) <= wire_nliO01O24_w_lg_q161w(0) AND n0l0l; + wire_nliO01O24_w_lg_q161w(0) <= nliO01O24 XOR nliO01O23; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0iO21 <= nliO0iO22; + END IF; + if (now = 0 ns) then + nliO0iO21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0iO22 <= nliO0iO21; + END IF; + END PROCESS; + wire_nliO0iO22_w_lg_w_lg_q123w124w(0) <= wire_nliO0iO22_w_lg_q123w(0) AND n0O0O; + wire_nliO0iO22_w_lg_q123w(0) <= nliO0iO22 XOR nliO0iO21; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0li19 <= nliO0li20; + END IF; + if (now = 0 ns) then + nliO0li19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0li20 <= nliO0li19; + END IF; + END PROCESS; + wire_nliO0li20_w_lg_w_lg_q120w121w(0) <= wire_nliO0li20_w_lg_q120w(0) AND n0O0l; + wire_nliO0li20_w_lg_q120w(0) <= nliO0li20 XOR nliO0li19; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0ll17 <= nliO0ll18; + END IF; + if (now = 0 ns) then + nliO0ll17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0ll18 <= nliO0ll17; + END IF; + END PROCESS; + wire_nliO0ll18_w_lg_w_lg_q91w92w(0) <= wire_nliO0ll18_w_lg_q91w(0) AND ni1ii; + wire_nliO0ll18_w_lg_q91w(0) <= nliO0ll18 XOR nliO0ll17; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0lO15 <= nliO0lO16; + END IF; + if (now = 0 ns) then + nliO0lO15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0lO16 <= nliO0lO15; + END IF; + END PROCESS; + wire_nliO0lO16_w_lg_w_lg_q85w86w(0) <= wire_nliO0lO16_w_lg_q85w(0) AND ni11O; + wire_nliO0lO16_w_lg_q85w(0) <= nliO0lO16 XOR nliO0lO15; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0Oi13 <= nliO0Oi14; + END IF; + if (now = 0 ns) then + nliO0Oi13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0Oi14 <= nliO0Oi13; + END IF; + END PROCESS; + wire_nliO0Oi14_w_lg_w_lg_q54w55w(0) <= wire_nliO0Oi14_w_lg_q54w(0) AND ni1ll; + wire_nliO0Oi14_w_lg_q54w(0) <= nliO0Oi14 XOR nliO0Oi13; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0Ol11 <= nliO0Ol12; + END IF; + if (now = 0 ns) then + nliO0Ol11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0Ol12 <= nliO0Ol11; + END IF; + END PROCESS; + wire_nliO0Ol12_w_lg_w_lg_q50w51w(0) <= wire_nliO0Ol12_w_lg_q50w(0) AND ni1iO; + wire_nliO0Ol12_w_lg_q50w(0) <= nliO0Ol12 XOR nliO0Ol11; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0OO10 <= nliO0OO9; + END IF; + END PROCESS; + wire_nliO0OO10_w_lg_w_lg_q46w47w(0) <= wire_nliO0OO10_w_lg_q46w(0) AND ni1il; + wire_nliO0OO10_w_lg_q46w(0) <= nliO0OO10 XOR nliO0OO9; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO0OO9 <= nliO0OO10; + END IF; + if (now = 0 ns) then + nliO0OO9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO10i35 <= nliO10i36; + END IF; + if (now = 0 ns) then + nliO10i35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO10i36 <= nliO10i35; + END IF; + END PROCESS; + wire_nliO10i36_w_lg_w_lg_q257w258w(0) <= wire_nliO10i36_w_lg_q257w(0) AND nl0iO; + wire_nliO10i36_w_lg_q257w(0) <= nliO10i36 XOR nliO10i35; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO10l33 <= nliO10l34; + END IF; + if (now = 0 ns) then + nliO10l33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO10l34 <= nliO10l33; + END IF; + END PROCESS; + wire_nliO10l34_w_lg_w_lg_q231w232w(0) <= wire_nliO10l34_w_lg_q231w(0) AND wire_n0ili_dataout; + wire_nliO10l34_w_lg_q231w(0) <= nliO10l34 XOR nliO10l33; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO10O31 <= nliO10O32; + END IF; + if (now = 0 ns) then + nliO10O31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO10O32 <= nliO10O31; + END IF; + END PROCESS; + wire_nliO10O32_w_lg_w_lg_q225w226w(0) <= wire_nliO10O32_w_lg_q225w(0) AND nl0li; + wire_nliO10O32_w_lg_q225w(0) <= nliO10O32 XOR nliO10O31; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO11i37 <= nliO11i38; + END IF; + if (now = 0 ns) then + nliO11i37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO11i38 <= nliO11i37; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO1il29 <= nliO1il30; + END IF; + if (now = 0 ns) then + nliO1il29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO1il30 <= nliO1il29; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO1li27 <= nliO1li28; + END IF; + if (now = 0 ns) then + nliO1li27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO1li28 <= nliO1li27; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO1lO25 <= nliO1lO26; + END IF; + if (now = 0 ns) then + nliO1lO25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliO1lO26 <= nliO1lO25; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOi0i3 <= nliOi0i4; + END IF; + if (now = 0 ns) then + nliOi0i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOi0i4 <= nliOi0i3; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOi1i7 <= nliOi1i8; + END IF; + if (now = 0 ns) then + nliOi1i7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOi1i8 <= nliOi1i7; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOi1l5 <= nliOi1l6; + END IF; + if (now = 0 ns) then + nliOi1l5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOi1l6 <= nliOi1l5; + END IF; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOiiO1 <= nliOiiO2; + END IF; + if (now = 0 ns) then + nliOiiO1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (pclk) + BEGIN + IF (pclk = '1' AND pclk'event) THEN nliOiiO2 <= nliOiiO1; + END IF; + END PROCESS; + PROCESS (pclk, wire_n0iOii_PRN, prstn) + BEGIN + IF (wire_n0iOii_PRN = '0') THEN + n0iO0O <= '1'; + n0iOil <= '1'; + ELSIF (prstn = '0') THEN + n0iO0O <= '0'; + n0iOil <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_n0l0iO_o = '1') THEN + n0iO0O <= nlii0OO; + n0iOil <= nliii1O; + END IF; + END IF; + END PROCESS; + wire_n0iOii_PRN <= (nlii0il60 XOR nlii0il59); + PROCESS (pclk, wire_n1l0i_PRN, prstn) + BEGIN + IF (wire_n1l0i_PRN = '0') THEN + n1l0l <= '1'; + n1l1O <= '1'; + ELSIF (prstn = '0') THEN + n1l0l <= '0'; + n1l1O <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_n010O_o = '1') THEN + n1l0l <= nlilO1O; + n1l1O <= nlillOi; + END IF; + END IF; + END PROCESS; + wire_n1l0i_PRN <= (nlill0O46 XOR nlill0O45); + PROCESS (pclk, wire_n1ll0i_PRN, wire_n1ll0i_CLRN) + BEGIN + IF (wire_n1ll0i_PRN = '0') THEN + n1ll0l <= '1'; + n1ll1O <= '1'; + ELSIF (wire_n1ll0i_CLRN = '0') THEN + n1ll0l <= '0'; + n1ll1O <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_n1O10O_o = '1') THEN + n1ll0l <= nli0OOO; + n1ll1O <= nli0OlO; + END IF; + END IF; + END PROCESS; + wire_n1ll0i_CLRN <= ((nli0O0l62 XOR nli0O0l61) AND prstn); + wire_n1ll0i_PRN <= (nli0O0i64 XOR nli0O0i63); + PROCESS (pclk, wire_nii1li_CLRN) + BEGIN + IF (wire_nii1li_CLRN = '0') THEN + nii1iO <= '0'; + nii1ll <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_niiilO_o = '1') THEN + nii1iO <= nliiO1O; + nii1ll <= nliiO0O; + END IF; + END IF; + END PROCESS; + wire_nii1li_CLRN <= ((nliilll58 XOR nliilll57) AND prstn); + PROCESS (pclk, wire_nl00Oi_PRN, prstn) + BEGIN + IF (wire_nl00Oi_PRN = '0') THEN + nl00lO <= '1'; + nl00Ol <= '1'; + ELSIF (prstn = '0') THEN + nl00lO <= '0'; + nl00Ol <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_nl0lOO_o = '1') THEN + nl00lO <= nlil00O; + nl00Ol <= nlil0iO; + END IF; + END IF; + END PROCESS; + wire_nl00Oi_PRN <= (nlil1Ol56 XOR nlil1Ol55); + PROCESS (pclk, wire_nl01l_PRN) + BEGIN + IF (wire_nl01l_PRN = '0') THEN + n0001l <= '1'; + n011OO <= '1'; + n0i0iO <= '1'; + n0iiiO <= '1'; + n0iOiO <= '1'; + n0iOli <= '1'; + n0iOll <= '1'; + n0iOlO <= '1'; + n0Oi1O <= '1'; + n100O <= '1'; + n10OOl <= '1'; + n110O <= '1'; + n11OlO <= '1'; + n1l00O <= '1'; + n1l0O <= '1'; + n1l10O <= '1'; + n1lii <= '1'; + n1lil <= '1'; + n1liO <= '1'; + n1ll0O <= '1'; + n1llii <= '1'; + n1llil <= '1'; + n1lliO <= '1'; + ni0ilO <= '1'; + ni0llO <= '1'; + ni1i0l <= '1'; + ni1OO <= '1'; + nii1lO <= '1'; + nii1Oi <= '1'; + nii1Ol <= '1'; + nii1OO <= '1'; + nill0O <= '1'; + niOlil <= '1'; + nl00OO <= '1'; + nl01O <= '1'; + nl0i1i <= '1'; + nl0i1l <= '1'; + nl0i1O <= '1'; + nl1lOO <= '1'; + nl1OOO <= '1'; + nliOiO <= '1'; + nll10lO <= '1'; + nll1ilO <= '1'; + nll1OlO <= '1'; + nll1OOi <= '1'; + nll1OOl <= '1'; + nll1OOO <= '1'; + nllii0O <= '1'; + nllliil <= '1'; + nllOiOO <= '1'; + nllOll <= '1'; + nllOlOO <= '1'; + nlO0liO <= '1'; + nlO101i <= '1'; + nlO101l <= '1'; + nlO101O <= '1'; + nlO11OO <= '1'; + nlOilll <= '1'; + nlOlO1O <= '1'; + nlOO11O <= '1'; + nlOOi0i <= '1'; + nlOOi0l <= '1'; + nlOOi0O <= '1'; + nlOOi1O <= '1'; + ELSIF (pclk = '1' AND pclk'event) THEN + n0001l <= rxelecidle_in(3); + n011OO <= wire_n0001O_dataout; + n0i0iO <= wire_n0i0Oi_o; + n0iiiO <= wire_n0i0Ol_o; + n0iOiO <= wire_n0l0li_dataout; + n0iOli <= wire_n0l0ll_dataout; + n0iOll <= wire_n0l0lO_dataout; + n0iOlO <= wire_n0l0Oi_dataout; + n0Oi1O <= wire_ni1i0O_dataout; + n100O <= wire_n11ll_o; + n10OOl <= rxelecidle_in(2); + n110O <= wire_n11li_o; + n11OlO <= wire_n10OOO_dataout; + n1l00O <= wire_n1l1ll_o; + n1l0O <= wire_n01ii_dataout; + n1l10O <= wire_n1l1li_o; + n1lii <= wire_n01il_dataout; + n1lil <= wire_n01iO_dataout; + n1liO <= wire_n01li_dataout; + n1ll0O <= wire_n1O1ii_dataout; + n1llii <= wire_n1O1il_dataout; + n1llil <= wire_n1O1iO_dataout; + n1lliO <= wire_n1O1li_dataout; + ni0ilO <= wire_ni0l1i_o; + ni0llO <= wire_ni0l1l_o; + ni1i0l <= rxelecidle_in(4); + ni1OO <= wire_nl00i_dataout; + nii1lO <= wire_niiiOi_dataout; + nii1Oi <= wire_niiiOl_dataout; + nii1Ol <= wire_niiiOO_dataout; + nii1OO <= wire_niil1i_dataout; + nill0O <= wire_niOliO_dataout; + niOlil <= rxelecidle_in(5); + nl00OO <= wire_nl0O1i_dataout; + nl01O <= rxelecidle_in(7); + nl0i1i <= wire_nl0O1l_dataout; + nl0i1l <= wire_nl0O1O_dataout; + nl0i1O <= wire_nl0O0i_dataout; + nl1lOO <= wire_nl1O0i_o; + nl1OOO <= wire_nl1O0l_o; + nliOiO <= wire_nllOlO_dataout; + nll10lO <= wire_nll1i1i_o; + nll1ilO <= wire_nll1i1l_o; + nll1OlO <= wire_nll00Oi_dataout; + nll1OOi <= wire_nll00Ol_dataout; + nll1OOl <= wire_nll00OO_dataout; + nll1OOO <= wire_nll0i1i_dataout; + nllii0O <= wire_nllliiO_dataout; + nllliil <= rxelecidle_in(0); + nllOiOO <= wire_nllOl0i_o; + nllOll <= rxelecidle_in(6); + nllOlOO <= wire_nllOl0l_o; + nlO0liO <= wire_nlOillO_dataout; + nlO101i <= wire_nlO1l1l_dataout; + nlO101l <= wire_nlO1l1O_dataout; + nlO101O <= wire_nlO1l0i_dataout; + nlO11OO <= wire_nlO1l1i_dataout; + nlOilll <= rxelecidle_in(1); + nlOlO1O <= wire_nlOlOii_o; + nlOO11O <= wire_nlOlOil_o; + nlOOi0i <= wire_nlOOO0l_dataout; + nlOOi0l <= wire_nlOOO0O_dataout; + nlOOi0O <= wire_nlOOOii_dataout; + nlOOi1O <= wire_nlOOO0i_dataout; + END IF; + if (now = 0 ns) then + n0001l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n011OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i0iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iiiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOlO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0Oi1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n100O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n10OOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n110O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11OlO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l10O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1lii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1lil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1liO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1ll0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1llii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1llil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1lliO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni0ilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni0llO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1i0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii1lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii1Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii1Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nii1OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nill0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niOlil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl00OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl01O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0i1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0i1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl0i1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1lOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1OOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliOiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll10lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1ilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1OlO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1OOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1OOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll1OOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllii0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllliil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllOiOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllOll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nllOlOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO0liO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO101i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO101l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO101O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO11OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOilll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOlO1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOO11O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOOi0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOOi0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOOi0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOOi1O <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl01l_PRN <= ((nliOi1i8 XOR nliOi1i7) AND prstn); + wire_nl01l_w_lg_w_lg_w_lg_n0iOlO1995w1999w2000w(0) <= wire_nl01l_w_lg_w_lg_n0iOlO1995w1999w(0) AND n0iOiO; + wire_nl01l_w_lg_w_lg_w_lg_n0iOlO1988w1990w1992w(0) <= wire_nl01l_w_lg_w_lg_n0iOlO1988w1990w(0) AND wire_nl01l_w_lg_n0iOiO1991w(0); + wire_nl01l_w_lg_w_lg_w_lg_n1liO370w374w375w(0) <= wire_nl01l_w_lg_w_lg_n1liO370w374w(0) AND n1l0O; + wire_nl01l_w_lg_w_lg_w_lg_n1liO363w365w367w(0) <= wire_nl01l_w_lg_w_lg_n1liO363w365w(0) AND wire_nl01l_w_lg_n1l0O366w(0); + wire_nl01l_w_lg_w_lg_w_lg_n1lliO2531w2535w2536w(0) <= wire_nl01l_w_lg_w_lg_n1lliO2531w2535w(0) AND n1ll0O; + wire_nl01l_w_lg_w_lg_w_lg_n1lliO2524w2526w2528w(0) <= wire_nl01l_w_lg_w_lg_n1lliO2524w2526w(0) AND wire_nl01l_w_lg_n1ll0O2527w(0); + wire_nl01l_w_lg_w_lg_w_lg_nii1OO1458w1462w1463w(0) <= wire_nl01l_w_lg_w_lg_nii1OO1458w1462w(0) AND nii1lO; + wire_nl01l_w_lg_w_lg_w_lg_nii1OO1451w1453w1455w(0) <= wire_nl01l_w_lg_w_lg_nii1OO1451w1453w(0) AND wire_nl01l_w_lg_nii1lO1454w(0); + wire_nl01l_w_lg_w_lg_w_lg_nl0i1O922w926w927w(0) <= wire_nl01l_w_lg_w_lg_nl0i1O922w926w(0) AND nl00OO; + wire_nl01l_w_lg_w_lg_w_lg_nl0i1O915w917w919w(0) <= wire_nl01l_w_lg_w_lg_nl0i1O915w917w(0) AND wire_nl01l_w_lg_nl00OO918w(0); + wire_nl01l_w_lg_w_lg_w_lg_nll1OOO4143w4147w4148w(0) <= wire_nl01l_w_lg_w_lg_nll1OOO4143w4147w(0) AND nll1OlO; + wire_nl01l_w_lg_w_lg_w_lg_nll1OOO4136w4138w4140w(0) <= wire_nl01l_w_lg_w_lg_nll1OOO4136w4138w(0) AND wire_nl01l_w_lg_nll1OlO4139w(0); + wire_nl01l_w_lg_w_lg_w_lg_nlO101O3607w3611w3612w(0) <= wire_nl01l_w_lg_w_lg_nlO101O3607w3611w(0) AND nlO11OO; + wire_nl01l_w_lg_w_lg_w_lg_nlO101O3600w3602w3604w(0) <= wire_nl01l_w_lg_w_lg_nlO101O3600w3602w(0) AND wire_nl01l_w_lg_nlO11OO3603w(0); + wire_nl01l_w_lg_w_lg_w_lg_nlOOi0O3069w3073w3074w(0) <= wire_nl01l_w_lg_w_lg_nlOOi0O3069w3073w(0) AND nlOOi1O; + wire_nl01l_w_lg_w_lg_w_lg_nlOOi0O3062w3064w3066w(0) <= wire_nl01l_w_lg_w_lg_nlOOi0O3062w3064w(0) AND wire_nl01l_w_lg_nlOOi1O3065w(0); + wire_nl01l_w_lg_w_lg_n0iOlO1995w1999w(0) <= wire_nl01l_w_lg_n0iOlO1995w(0) AND wire_nl01l_w_lg_n0iOli1989w(0); + wire_nl01l_w_lg_w_lg_n0iOlO1995w1996w(0) <= wire_nl01l_w_lg_n0iOlO1995w(0) AND n0iOli; + wire_nl01l_w_lg_w_lg_n0iOlO1988w1990w(0) <= wire_nl01l_w_lg_n0iOlO1988w(0) AND wire_nl01l_w_lg_n0iOli1989w(0); + wire_nl01l_w_lg_w_lg_n1liO370w374w(0) <= wire_nl01l_w_lg_n1liO370w(0) AND wire_nl01l_w_lg_n1lii364w(0); + wire_nl01l_w_lg_w_lg_n1liO370w371w(0) <= wire_nl01l_w_lg_n1liO370w(0) AND n1lii; + wire_nl01l_w_lg_w_lg_n1liO363w365w(0) <= wire_nl01l_w_lg_n1liO363w(0) AND wire_nl01l_w_lg_n1lii364w(0); + wire_nl01l_w_lg_w_lg_n1lliO2531w2535w(0) <= wire_nl01l_w_lg_n1lliO2531w(0) AND wire_nl01l_w_lg_n1llii2525w(0); + wire_nl01l_w_lg_w_lg_n1lliO2531w2532w(0) <= wire_nl01l_w_lg_n1lliO2531w(0) AND n1llii; + wire_nl01l_w_lg_w_lg_n1lliO2524w2526w(0) <= wire_nl01l_w_lg_n1lliO2524w(0) AND wire_nl01l_w_lg_n1llii2525w(0); + wire_nl01l_w_lg_w_lg_nii1OO1458w1462w(0) <= wire_nl01l_w_lg_nii1OO1458w(0) AND wire_nl01l_w_lg_nii1Oi1452w(0); + wire_nl01l_w_lg_w_lg_nii1OO1458w1459w(0) <= wire_nl01l_w_lg_nii1OO1458w(0) AND nii1Oi; + wire_nl01l_w_lg_w_lg_nii1OO1451w1453w(0) <= wire_nl01l_w_lg_nii1OO1451w(0) AND wire_nl01l_w_lg_nii1Oi1452w(0); + wire_nl01l_w_lg_w_lg_nl0i1O922w926w(0) <= wire_nl01l_w_lg_nl0i1O922w(0) AND wire_nl01l_w_lg_nl0i1i916w(0); + wire_nl01l_w_lg_w_lg_nl0i1O922w923w(0) <= wire_nl01l_w_lg_nl0i1O922w(0) AND nl0i1i; + wire_nl01l_w_lg_w_lg_nl0i1O915w917w(0) <= wire_nl01l_w_lg_nl0i1O915w(0) AND wire_nl01l_w_lg_nl0i1i916w(0); + wire_nl01l_w_lg_w_lg_nll1OOO4143w4147w(0) <= wire_nl01l_w_lg_nll1OOO4143w(0) AND wire_nl01l_w_lg_nll1OOi4137w(0); + wire_nl01l_w_lg_w_lg_nll1OOO4143w4144w(0) <= wire_nl01l_w_lg_nll1OOO4143w(0) AND nll1OOi; + wire_nl01l_w_lg_w_lg_nll1OOO4136w4138w(0) <= wire_nl01l_w_lg_nll1OOO4136w(0) AND wire_nl01l_w_lg_nll1OOi4137w(0); + wire_nl01l_w_lg_w_lg_nlO101O3607w3611w(0) <= wire_nl01l_w_lg_nlO101O3607w(0) AND wire_nl01l_w_lg_nlO101i3601w(0); + wire_nl01l_w_lg_w_lg_nlO101O3607w3608w(0) <= wire_nl01l_w_lg_nlO101O3607w(0) AND nlO101i; + wire_nl01l_w_lg_w_lg_nlO101O3600w3602w(0) <= wire_nl01l_w_lg_nlO101O3600w(0) AND wire_nl01l_w_lg_nlO101i3601w(0); + wire_nl01l_w_lg_w_lg_nlOOi0O3069w3073w(0) <= wire_nl01l_w_lg_nlOOi0O3069w(0) AND wire_nl01l_w_lg_nlOOi0i3063w(0); + wire_nl01l_w_lg_w_lg_nlOOi0O3069w3070w(0) <= wire_nl01l_w_lg_nlOOi0O3069w(0) AND nlOOi0i; + wire_nl01l_w_lg_w_lg_nlOOi0O3062w3064w(0) <= wire_nl01l_w_lg_nlOOi0O3062w(0) AND wire_nl01l_w_lg_nlOOi0i3063w(0); + wire_nl01l_w_lg_n0iOlO1995w(0) <= n0iOlO AND wire_nl01l_w_lg_n0iOll1994w(0); + wire_nl01l_w_lg_n0iOlO1988w(0) <= n0iOlO AND n0iOll; + wire_nl01l_w_lg_n1liO370w(0) <= n1liO AND wire_nl01l_w_lg_n1lil369w(0); + wire_nl01l_w_lg_n1liO363w(0) <= n1liO AND n1lil; + wire_nl01l_w_lg_n1lliO2531w(0) <= n1lliO AND wire_nl01l_w_lg_n1llil2530w(0); + wire_nl01l_w_lg_n1lliO2524w(0) <= n1lliO AND n1llil; + wire_nl01l_w_lg_nii1OO1458w(0) <= nii1OO AND wire_nl01l_w_lg_nii1Ol1457w(0); + wire_nl01l_w_lg_nii1OO1451w(0) <= nii1OO AND nii1Ol; + wire_nl01l_w_lg_nl0i1O922w(0) <= nl0i1O AND wire_nl01l_w_lg_nl0i1l921w(0); + wire_nl01l_w_lg_nl0i1O915w(0) <= nl0i1O AND nl0i1l; + wire_nl01l_w_lg_nll1OOO4143w(0) <= nll1OOO AND wire_nl01l_w_lg_nll1OOl4142w(0); + wire_nl01l_w_lg_nll1OOO4136w(0) <= nll1OOO AND nll1OOl; + wire_nl01l_w_lg_nlO101O3607w(0) <= nlO101O AND wire_nl01l_w_lg_nlO101l3606w(0); + wire_nl01l_w_lg_nlO101O3600w(0) <= nlO101O AND nlO101l; + wire_nl01l_w_lg_nlOOi0O3069w(0) <= nlOOi0O AND wire_nl01l_w_lg_nlOOi0l3068w(0); + wire_nl01l_w_lg_nlOOi0O3062w(0) <= nlOOi0O AND nlOOi0l; + wire_nl01l_w_lg_n0i0iO2046w(0) <= NOT n0i0iO; + wire_nl01l_w_lg_n0iOiO1991w(0) <= NOT n0iOiO; + wire_nl01l_w_lg_n0iOli1989w(0) <= NOT n0iOli; + wire_nl01l_w_lg_n0iOll1994w(0) <= NOT n0iOll; + wire_nl01l_w_lg_n0iOlO2226w(0) <= NOT n0iOlO; + wire_nl01l_w_lg_n110O421w(0) <= NOT n110O; + wire_nl01l_w_lg_n1l0O366w(0) <= NOT n1l0O; + wire_nl01l_w_lg_n1l10O2584w(0) <= NOT n1l10O; + wire_nl01l_w_lg_n1lii364w(0) <= NOT n1lii; + wire_nl01l_w_lg_n1lil369w(0) <= NOT n1lil; + wire_nl01l_w_lg_n1liO612w(0) <= NOT n1liO; + wire_nl01l_w_lg_n1ll0O2527w(0) <= NOT n1ll0O; + wire_nl01l_w_lg_n1llii2525w(0) <= NOT n1llii; + wire_nl01l_w_lg_n1llil2530w(0) <= NOT n1llil; + wire_nl01l_w_lg_n1lliO2764w(0) <= NOT n1lliO; + wire_nl01l_w_lg_ni0ilO1510w(0) <= NOT ni0ilO; + wire_nl01l_w_lg_nii1lO1454w(0) <= NOT nii1lO; + wire_nl01l_w_lg_nii1Oi1452w(0) <= NOT nii1Oi; + wire_nl01l_w_lg_nii1Ol1457w(0) <= NOT nii1Ol; + wire_nl01l_w_lg_nii1OO1690w(0) <= NOT nii1OO; + wire_nl01l_w_lg_nl00OO918w(0) <= NOT nl00OO; + wire_nl01l_w_lg_nl0i1i916w(0) <= NOT nl0i1i; + wire_nl01l_w_lg_nl0i1l921w(0) <= NOT nl0i1l; + wire_nl01l_w_lg_nl0i1O1153w(0) <= NOT nl0i1O; + wire_nl01l_w_lg_nl1lOO973w(0) <= NOT nl1lOO; + wire_nl01l_w_lg_nll10lO4195w(0) <= NOT nll10lO; + wire_nl01l_w_lg_nll1OlO4139w(0) <= NOT nll1OlO; + wire_nl01l_w_lg_nll1OOi4137w(0) <= NOT nll1OOi; + wire_nl01l_w_lg_nll1OOl4142w(0) <= NOT nll1OOl; + wire_nl01l_w_lg_nll1OOO4375w(0) <= NOT nll1OOO; + wire_nl01l_w_lg_nllOiOO3658w(0) <= NOT nllOiOO; + wire_nl01l_w_lg_nlO101i3601w(0) <= NOT nlO101i; + wire_nl01l_w_lg_nlO101l3606w(0) <= NOT nlO101l; + wire_nl01l_w_lg_nlO101O3838w(0) <= NOT nlO101O; + wire_nl01l_w_lg_nlO11OO3603w(0) <= NOT nlO11OO; + wire_nl01l_w_lg_nlOlO1O3122w(0) <= NOT nlOlO1O; + wire_nl01l_w_lg_nlOOi0i3063w(0) <= NOT nlOOi0i; + wire_nl01l_w_lg_nlOOi0l3068w(0) <= NOT nlOOi0l; + wire_nl01l_w_lg_nlOOi0O3302w(0) <= NOT nlOOi0O; + wire_nl01l_w_lg_nlOOi1O3065w(0) <= NOT nlOOi1O; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_n0iOlO1988w1990w1992w1993w(0) <= wire_nl01l_w_lg_w_lg_w_lg_n0iOlO1988w1990w1992w(0) OR nlii0iO; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_n1liO363w365w367w368w(0) <= wire_nl01l_w_lg_w_lg_w_lg_n1liO363w365w367w(0) OR nlillii; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_n1lliO2524w2526w2528w2529w(0) <= wire_nl01l_w_lg_w_lg_w_lg_n1lliO2524w2526w2528w(0) OR nli0O0O; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_nii1OO1451w1453w1455w1456w(0) <= wire_nl01l_w_lg_w_lg_w_lg_nii1OO1451w1453w1455w(0) OR nliillO; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_nl0i1O915w917w919w920w(0) <= wire_nl01l_w_lg_w_lg_w_lg_nl0i1O915w917w919w(0) OR nlil1OO; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_nll1OOO4136w4138w4140w4141w(0) <= wire_nl01l_w_lg_w_lg_w_lg_nll1OOO4136w4138w4140w(0) OR nli1ili; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_nlO101O3600w3602w3604w3605w(0) <= wire_nl01l_w_lg_w_lg_w_lg_nlO101O3600w3602w3604w(0) OR nli1OOi; + wire_nl01l_w_lg_w_lg_w_lg_w_lg_nlOOi0O3062w3064w3066w3067w(0) <= wire_nl01l_w_lg_w_lg_w_lg_nlOOi0O3062w3064w3066w(0) OR nli0i1l; + PROCESS (pclk, wire_nliii_CLRN) + BEGIN + IF (wire_nliii_CLRN = '0') THEN + n000il <= '0'; + n000iO <= '0'; + n000li <= '0'; + n000ll <= '0'; + n000lO <= '0'; + n000Oi <= '0'; + n000Ol <= '0'; + n000OO <= '0'; + n00i0i <= '0'; + n00i0l <= '0'; + n00i0O <= '0'; + n00i1i <= '0'; + n00i1l <= '0'; + n00i1O <= '0'; + n00ili <= '0'; + n00iOi <= '0'; + n00iOl <= '0'; + n0110i <= '0'; + n0110l <= '0'; + n0110O <= '0'; + n0111i <= '0'; + n0111l <= '0'; + n0111O <= '0'; + n011ii <= '0'; + n011il <= '0'; + n011iO <= '0'; + n011li <= '0'; + n011ll <= '0'; + n011lO <= '0'; + n011Oi <= '0'; + n011Ol <= '0'; + n0i0i <= '0'; + n0i0ii <= '0'; + n0i0il <= '0'; + n0i0l <= '0'; + n0i0li <= '0'; + n0i0O <= '0'; + n0iili <= '0'; + n0iill <= '0'; + n0iilO <= '0'; + n0iiOi <= '0'; + n0iiOl <= '0'; + n0iiOO <= '0'; + n0il1i <= '0'; + n0iO0l <= '0'; + n0iO1l <= '0'; + n0iOOi <= '0'; + n0iOOl <= '0'; + n0l0i <= '0'; + n0l0l <= '0'; + n0l0O <= '0'; + n0l1l <= '0'; + n0l1O <= '0'; + n0lii <= '0'; + n0lil <= '0'; + n0liO <= '0'; + n0lli <= '0'; + n0llii <= '0'; + n0llil <= '0'; + n0lliO <= '0'; + n0lll <= '0'; + n0llO <= '0'; + n0lO0l <= '0'; + n0lO0O <= '0'; + n0lOi <= '0'; + n0lOii <= '0'; + n0lOil <= '0'; + n0lOiO <= '0'; + n0lOl <= '0'; + n0lOli <= '0'; + n0lOll <= '0'; + n0lOlO <= '0'; + n0lOO <= '0'; + n0lOOi <= '0'; + n0lOOl <= '0'; + n0lOOO <= '0'; + n0O00i <= '0'; + n0O00l <= '0'; + n0O00O <= '0'; + n0O01i <= '0'; + n0O01l <= '0'; + n0O01O <= '0'; + n0O0i <= '0'; + n0O0ii <= '0'; + n0O0il <= '0'; + n0O0iO <= '0'; + n0O0l <= '0'; + n0O0li <= '0'; + n0O0ll <= '0'; + n0O0lO <= '0'; + n0O0O <= '0'; + n0O0Oi <= '0'; + n0O0Ol <= '0'; + n0O0OO <= '0'; + n0O10i <= '0'; + n0O10l <= '0'; + n0O10O <= '0'; + n0O11i <= '0'; + n0O11l <= '0'; + n0O11O <= '0'; + n0O1i <= '0'; + n0O1ii <= '0'; + n0O1il <= '0'; + n0O1iO <= '0'; + n0O1l <= '0'; + n0O1li <= '0'; + n0O1ll <= '0'; + n0O1lO <= '0'; + n0O1O <= '0'; + n0O1Oi <= '0'; + n0O1Ol <= '0'; + n0O1OO <= '0'; + n0Oi1i <= '0'; + n0Oi1l <= '0'; + n0Oii <= '0'; + n0Oil <= '0'; + n0OiO <= '0'; + n0Oli <= '0'; + n0Oll <= '0'; + n0OlO <= '0'; + n0OOi <= '0'; + n0OOl <= '0'; + n0OOO <= '0'; + n10ii <= '0'; + n10il <= '0'; + n10iO <= '0'; + n10li <= '0'; + n10ll <= '0'; + n10lO <= '0'; + n10Oi <= '0'; + n1101i <= '0'; + n1101l <= '0'; + n1101O <= '0'; + n110i <= '0'; + n110l <= '0'; + n110Ol <= '0'; + n110OO <= '0'; + n11i0i <= '0'; + n11i0l <= '0'; + n11i0O <= '0'; + n11i1i <= '0'; + n11i1l <= '0'; + n11i1O <= '0'; + n11ii <= '0'; + n11iii <= '0'; + n11iil <= '0'; + n11iiO <= '0'; + n11ili <= '0'; + n11ill <= '0'; + n11ilO <= '0'; + n11iOi <= '0'; + n11iOl <= '0'; + n11iOO <= '0'; + n11l0i <= '0'; + n11l0l <= '0'; + n11l0O <= '0'; + n11l1i <= '0'; + n11l1l <= '0'; + n11l1O <= '0'; + n11lii <= '0'; + n11lil <= '0'; + n11liO <= '0'; + n11lli <= '0'; + n11lll <= '0'; + n11llO <= '0'; + n11lOi <= '0'; + n11lOl <= '0'; + n11lOO <= '0'; + n11O0i <= '0'; + n11O0l <= '0'; + n11O0O <= '0'; + n11O1i <= '0'; + n11O1l <= '0'; + n11O1O <= '0'; + n11Oii <= '0'; + n11Oil <= '0'; + n11OiO <= '0'; + n11Oli <= '0'; + n11Oll <= '0'; + n1i01i <= '0'; + n1i01l <= '0'; + n1i01O <= '0'; + n1i0ii <= '0'; + n1i0li <= '0'; + n1i0ll <= '0'; + n1i10l <= '0'; + n1i10O <= '0'; + n1i1ii <= '0'; + n1i1il <= '0'; + n1i1iO <= '0'; + n1i1li <= '0'; + n1i1ll <= '0'; + n1i1lO <= '0'; + n1i1Oi <= '0'; + n1i1Ol <= '0'; + n1i1OO <= '0'; + n1iOl <= '0'; + n1l0ii <= '0'; + n1l0il <= '0'; + n1l0iO <= '0'; + n1l0li <= '0'; + n1l0ll <= '0'; + n1l0lO <= '0'; + n1l0Oi <= '0'; + n1l10i <= '0'; + n1l10l <= '0'; + n1l1ii <= '0'; + n1l1l <= '0'; + n1liOl <= '0'; + n1ll1l <= '0'; + n1lli <= '0'; + n1lll <= '0'; + n1llli <= '0'; + n1llll <= '0'; + n1Oi0i <= '0'; + n1Oi0l <= '0'; + n1Oi0O <= '0'; + n1Ol0i <= '0'; + n1Ol0l <= '0'; + n1Ol0O <= '0'; + n1Ol1l <= '0'; + n1Ol1O <= '0'; + n1Olii <= '0'; + n1Olil <= '0'; + n1OliO <= '0'; + n1Olli <= '0'; + n1Olll <= '0'; + n1OllO <= '0'; + n1OlOi <= '0'; + n1OlOl <= '0'; + n1OlOO <= '0'; + n1OO0i <= '0'; + n1OO0l <= '0'; + n1OO0O <= '0'; + n1OO1i <= '0'; + n1OO1l <= '0'; + n1OO1O <= '0'; + n1OOii <= '0'; + n1OOil <= '0'; + n1OOiO <= '0'; + n1OOli <= '0'; + n1OOll <= '0'; + n1OOlO <= '0'; + n1OOOi <= '0'; + n1OOOl <= '0'; + n1OOOO <= '0'; + ni0ili <= '0'; + ni0ill <= '0'; + ni0iOi <= '0'; + ni0lOi <= '0'; + ni0lOl <= '0'; + ni0lOO <= '0'; + ni0O0i <= '0'; + ni0O1i <= '0'; + ni0O1l <= '0'; + ni0O1O <= '0'; + ni10i <= '0'; + ni10l <= '0'; + ni10O <= '0'; + ni11i <= '0'; + ni11l <= '0'; + ni11O <= '0'; + ni1ii <= '0'; + ni1il <= '0'; + ni1ill <= '0'; + ni1ilO <= '0'; + ni1iO <= '0'; + ni1iOi <= '0'; + ni1iOl <= '0'; + ni1iOO <= '0'; + ni1l0i <= '0'; + ni1l0l <= '0'; + ni1l0O <= '0'; + ni1l1i <= '0'; + ni1l1l <= '0'; + ni1l1O <= '0'; + ni1li <= '0'; + ni1lii <= '0'; + ni1lil <= '0'; + ni1liO <= '0'; + ni1ll <= '0'; + ni1lO <= '0'; + ni1lOi <= '0'; + ni1O1i <= '0'; + ni1O1l <= '0'; + ni1Oi <= '0'; + ni1Ol <= '0'; + nii01i <= '0'; + nii01l <= '0'; + nii10l <= '0'; + nii1il <= '0'; + niiOli <= '0'; + niiOll <= '0'; + niiOlO <= '0'; + nil00i <= '0'; + nil00l <= '0'; + nil00O <= '0'; + nil01i <= '0'; + nil01l <= '0'; + nil01O <= '0'; + nil0ii <= '0'; + nil0il <= '0'; + nil0iO <= '0'; + nil0li <= '0'; + nil0ll <= '0'; + nil0lO <= '0'; + nil0Oi <= '0'; + nil0Ol <= '0'; + nil0OO <= '0'; + nil1il <= '0'; + nil1iO <= '0'; + nil1li <= '0'; + nil1ll <= '0'; + nil1lO <= '0'; + nil1Oi <= '0'; + nil1Ol <= '0'; + nil1OO <= '0'; + nili0i <= '0'; + nili0l <= '0'; + nili0O <= '0'; + nili1i <= '0'; + nili1l <= '0'; + nili1O <= '0'; + niliii <= '0'; + niliil <= '0'; + niliiO <= '0'; + nilili <= '0'; + nilill <= '0'; + nililO <= '0'; + niliOi <= '0'; + niliOl <= '0'; + niliOO <= '0'; + nill0i <= '0'; + nill0l <= '0'; + nill1i <= '0'; + nill1l <= '0'; + nill1O <= '0'; + niOlOl <= '0'; + niOlOO <= '0'; + niOO0i <= '0'; + niOO0l <= '0'; + niOO0O <= '0'; + niOO1i <= '0'; + niOO1l <= '0'; + niOO1O <= '0'; + niOOii <= '0'; + niOOil <= '0'; + niOOiO <= '0'; + niOOli <= '0'; + niOOll <= '0'; + niOOlO <= '0'; + nl00il <= '0'; + nl00ll <= '0'; + nl010i <= '0'; + nl010l <= '0'; + nl010O <= '0'; + nl011i <= '0'; + nl011l <= '0'; + nl011O <= '0'; + nl01ii <= '0'; + nl0i0i <= '0'; + nl0i0l <= '0'; + nl0iO <= '0'; + nl0li <= '0'; + nl0ll <= '0'; + nl0lO <= '0'; + nl0Oi <= '0'; + nl0Ol <= '0'; + nl0OO <= '0'; + nl110i <= '0'; + nl110l <= '0'; + nl111i <= '0'; + nl1lOi <= '0'; + nl1lOl <= '0'; + nl1O1i <= '0'; + nli0i <= '0'; + nli0l <= '0'; + nli0ll <= '0'; + nli0lO <= '0'; + nli0O <= '0'; + nli0Oi <= '0'; + nli0Ol <= '0'; + nli0OO <= '0'; + nli1i <= '0'; + nli1l <= '0'; + nli1O <= '0'; + nli1Oi <= '0'; + nli1Ol <= '0'; + nli1OO <= '0'; + nlii0i <= '0'; + nlii0l <= '0'; + nlii0O <= '0'; + nlii1i <= '0'; + nlii1l <= '0'; + nlii1O <= '0'; + nliiii <= '0'; + nliiil <= '0'; + nliiiO <= '0'; + nliil <= '0'; + nliili <= '0'; + nliill <= '0'; + nliilO <= '0'; + nliiOi <= '0'; + nliiOl <= '0'; + nliiOO <= '0'; + nlil0i <= '0'; + nlil0l <= '0'; + nlil0O <= '0'; + nlil1i <= '0'; + nlil1l <= '0'; + nlil1O <= '0'; + nlilii <= '0'; + nlilil <= '0'; + nliliO <= '0'; + nlilli <= '0'; + nlilll <= '0'; + nlillO <= '0'; + nlilOi <= '0'; + nlilOl <= '0'; + nlilOO <= '0'; + nliO0i <= '0'; + nliO0l <= '0'; + nliO0O <= '0'; + nliO1i <= '0'; + nliO1l <= '0'; + nliO1O <= '0'; + nliOii <= '0'; + nliOil <= '0'; + nliOiOi <= '0'; + nliOl1i <= '0'; + nliOl1l <= '0'; + nll011i <= '0'; + nll011l <= '0'; + nll0lli <= '0'; + nll0lll <= '0'; + nll0llO <= '0'; + nll0Oil <= '0'; + nll0OiO <= '0'; + nll0Oli <= '0'; + nll0Oll <= '0'; + nll0OlO <= '0'; + nll0OOi <= '0'; + nll0OOl <= '0'; + nll0OOO <= '0'; + nll10li <= '0'; + nll10ll <= '0'; + nll10Oi <= '0'; + nll1iOi <= '0'; + nll1iOl <= '0'; + nll1iOO <= '0'; + nll1l0i <= '0'; + nll1l1i <= '0'; + nll1l1l <= '0'; + nll1l1O <= '0'; + nll1O0l <= '0'; + nll1Oil <= '0'; + nlli00i <= '0'; + nlli00l <= '0'; + nlli00O <= '0'; + nlli01i <= '0'; + nlli01l <= '0'; + nlli01O <= '0'; + nlli0ii <= '0'; + nlli0il <= '0'; + nlli0iO <= '0'; + nlli0li <= '0'; + nlli0ll <= '0'; + nlli0lO <= '0'; + nlli0Oi <= '0'; + nlli0Ol <= '0'; + nlli0OO <= '0'; + nlli10i <= '0'; + nlli10l <= '0'; + nlli10O <= '0'; + nlli11i <= '0'; + nlli11l <= '0'; + nlli11O <= '0'; + nlli1ii <= '0'; + nlli1il <= '0'; + nlli1iO <= '0'; + nlli1li <= '0'; + nlli1ll <= '0'; + nlli1lO <= '0'; + nlli1Oi <= '0'; + nlli1Ol <= '0'; + nlli1OO <= '0'; + nllii0i <= '0'; + nllii0l <= '0'; + nllii1i <= '0'; + nllii1l <= '0'; + nllii1O <= '0'; + nllliOl <= '0'; + nllliOO <= '0'; + nllll0i <= '0'; + nllll0l <= '0'; + nllll0O <= '0'; + nllll1i <= '0'; + nllll1l <= '0'; + nllll1O <= '0'; + nllllii <= '0'; + nllllil <= '0'; + nlllliO <= '0'; + nllllli <= '0'; + nllllll <= '0'; + nlllllO <= '0'; + nlllO0i <= '0'; + nlllO0l <= '0'; + nlllO1i <= '0'; + nllOiOi <= '0'; + nllOiOl <= '0'; + nllOl1i <= '0'; + nllOO0i <= '0'; + nllOO0l <= '0'; + nllOO0O <= '0'; + nllOO1i <= '0'; + nllOO1l <= '0'; + nllOO1O <= '0'; + nllOOii <= '0'; + nlO000i <= '0'; + nlO000l <= '0'; + nlO000O <= '0'; + nlO001i <= '0'; + nlO001l <= '0'; + nlO001O <= '0'; + nlO00ii <= '0'; + nlO00il <= '0'; + nlO00iO <= '0'; + nlO00l <= '0'; + nlO00li <= '0'; + nlO00ll <= '0'; + nlO00lO <= '0'; + nlO00Oi <= '0'; + nlO00Ol <= '0'; + nlO00OO <= '0'; + nlO01ll <= '0'; + nlO01lO <= '0'; + nlO01Oi <= '0'; + nlO01Ol <= '0'; + nlO01OO <= '0'; + nlO0i0i <= '0'; + nlO0i0l <= '0'; + nlO0i0O <= '0'; + nlO0i1i <= '0'; + nlO0i1l <= '0'; + nlO0i1O <= '0'; + nlO0iii <= '0'; + nlO0iil <= '0'; + nlO0iiO <= '0'; + nlO0ili <= '0'; + nlO0ill <= '0'; + nlO0ilO <= '0'; + nlO0iO <= '0'; + nlO0iOi <= '0'; + nlO0iOl <= '0'; + nlO0iOO <= '0'; + nlO0l0i <= '0'; + nlO0l0l <= '0'; + nlO0l0O <= '0'; + nlO0l1i <= '0'; + nlO0l1l <= '0'; + nlO0l1O <= '0'; + nlO0li <= '0'; + nlO0lii <= '0'; + nlO0lil <= '0'; + nlO100i <= '0'; + nlO100l <= '0'; + nlO10i <= '0'; + nlO10l <= '0'; + nlO10O <= '0'; + nlO11il <= '0'; + nlO11l <= '0'; + nlO11ll <= '0'; + nlO11O <= '0'; + nlO1ii <= '0'; + nlO1il <= '0'; + nlO1iO <= '0'; + nlO1li <= '0'; + nlO1ll <= '0'; + nlO1lO <= '0'; + nlO1Oi <= '0'; + nlO1Ol <= '0'; + nlO1OO <= '0'; + nlO1OOi <= '0'; + nlO1OOl <= '0'; + nlO1OOO <= '0'; + nlOiO0i <= '0'; + nlOiO0l <= '0'; + nlOiO0O <= '0'; + nlOiO1l <= '0'; + nlOiO1O <= '0'; + nlOiOii <= '0'; + nlOiOil <= '0'; + nlOiOiO <= '0'; + nlOiOli <= '0'; + nlOiOll <= '0'; + nlOiOlO <= '0'; + nlOiOOi <= '0'; + nlOiOOl <= '0'; + nlOiOOO <= '0'; + nlOl10i <= '0'; + nlOl1ii <= '0'; + nlOl1il <= '0'; + nlOlO0i <= '0'; + nlOlO1i <= '0'; + nlOlO1l <= '0'; + nlOO0ll <= '0'; + nlOO0Ol <= '0'; + nlOO10i <= '0'; + nlOO10l <= '0'; + nlOO10O <= '0'; + nlOO1ii <= '0'; + nlOO1il <= '0'; + nlOO1iO <= '0'; + nlOO1li <= '0'; + nlOOiii <= '0'; + nlOOiil <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + n000il <= eidleinfersel(0); + n000iO <= eidleinfersel(1); + n000li <= eidleinfersel(2); + n000ll <= n000lO; + n000lO <= rxvalid(3); + n000Oi <= datain_ch3(8); + n000Ol <= datain_ch3(0); + n000OO <= datain_ch3(1); + n00i0i <= datain_ch3(5); + n00i0l <= datain_ch3(6); + n00i0O <= datain_ch3(7); + n00i1i <= datain_ch3(2); + n00i1l <= datain_ch3(3); + n00i1O <= datain_ch3(4); + n00ili <= wire_n00iil_dataout; + n00iOi <= n00iOl; + n00iOl <= n00ilO; + n0110i <= wire_n01OOi_dataout; + n0110l <= wire_n01OOl_dataout; + n0110O <= wire_n01OOO_dataout; + n0111i <= wire_n01Oli_dataout; + n0111l <= wire_n01Oll_dataout; + n0111O <= wire_n01OlO_dataout; + n011ii <= wire_n0011i_dataout; + n011il <= wire_n0011O_dataout; + n011iO <= wire_n0010i_dataout; + n011li <= wire_n0010l_dataout; + n011ll <= wire_n0010O_dataout; + n011lO <= wire_n001ii_dataout; + n011Oi <= wire_n001il_dataout; + n011Ol <= wire_n001iO_dataout; + n0i0i <= wire_n0iii_o; + n0i0ii <= wire_n0i0ll_o; + n0i0il <= wire_n0i0lO_o; + n0i0l <= wire_n0iil_o; + n0i0li <= ((((nliiiiO AND n0iili) OR wire_w_lg_nliiiiO2057w(0)) OR wire_w_lg_nliiiiO2061w(0)) OR (wire_w_lg_nliiill2063w(0) AND (wire_w_lg_nliiiiO2064w(0) AND (nlii0ii AND n0iiOi)))); + n0i0O <= wire_ni01i_dataout; + n0iili <= (nliiiiO AND n0iill); + n0iill <= (nliiiiO AND n0iOOi); + n0iilO <= n0iiOi; + n0iiOi <= nliiiiO; + n0iiOl <= n0iiOO; + n0iiOO <= n0iOOi; + n0il1i <= (n0iOOi AND (nliiill OR (ni1iOO AND nlii00O))); + n0iO0l <= wire_n0l10l_dataout; + n0iO1l <= (wire_w_lg_w_lg_w_lg_nliii1O2007w2009w2010w(0) AND wire_nliii_w_lg_n0iO0l2011w(0)); + n0iOOi <= nliiill; + n0iOOl <= wire_n0lllO_o; + n0l0i <= wire_ni00i_dataout; + n0l0l <= wire_ni00l_dataout; + n0l0O <= wire_ni00O_dataout; + n0l1l <= wire_ni01l_dataout; + n0l1O <= wire_ni01O_dataout; + n0lii <= wire_ni0ii_dataout; + n0lil <= wire_ni0il_dataout; + n0liO <= wire_ni0iO_dataout; + n0lli <= wire_ni0li_dataout; + n0llii <= wire_n0llli_o; + n0llil <= wire_n0llll_o; + n0lliO <= wire_n0Oi0i_dataout; + n0lll <= wire_ni0ll_dataout; + n0llO <= wire_niiiO_dataout; + n0lO0l <= wire_n0Oi0l_dataout; + n0lO0O <= wire_n0Oi0O_dataout; + n0lOi <= wire_niili_dataout; + n0lOii <= wire_n0Oiii_dataout; + n0lOil <= wire_n0Oiil_dataout; + n0lOiO <= wire_n0OiiO_dataout; + n0lOl <= wire_niill_dataout; + n0lOli <= wire_n0Oili_dataout; + n0lOll <= wire_n0Oill_dataout; + n0lOlO <= wire_n0OilO_dataout; + n0lOO <= wire_niilO_dataout; + n0lOOi <= wire_n0OiOi_dataout; + n0lOOl <= wire_n0OiOl_dataout; + n0lOOO <= wire_n0OllO_dataout; + n0O00i <= wire_ni11Oi_dataout; + n0O00l <= wire_ni11Ol_dataout; + n0O00O <= wire_ni11OO_dataout; + n0O01i <= (NOT (((NOT (eidleinfersel(0) XOR ni1ill)) AND (NOT (eidleinfersel(1) XOR ni1ilO))) AND (NOT (eidleinfersel(2) XOR ni1iOi)))); + n0O01l <= nliiiOl; + n0O01O <= nliiiOO; + n0O0i <= wire_nil1i_dataout; + n0O0ii <= wire_ni101i_dataout; + n0O0il <= wire_ni101l_dataout; + n0O0iO <= wire_ni101O_dataout; + n0O0l <= wire_nil1l_dataout; + n0O0li <= wire_ni100i_dataout; + n0O0ll <= wire_ni100O_dataout; + n0O0lO <= wire_ni10ii_dataout; + n0O0O <= wire_nil1O_dataout; + n0O0Oi <= wire_ni10il_dataout; + n0O0Ol <= wire_ni10iO_dataout; + n0O0OO <= wire_ni10li_dataout; + n0O10i <= wire_n0OO1i_dataout; + n0O10l <= wire_n0OO1l_dataout; + n0O10O <= wire_n0OO1O_dataout; + n0O11i <= wire_n0OlOi_dataout; + n0O11l <= wire_n0OlOl_dataout; + n0O11O <= wire_n0OlOO_dataout; + n0O1i <= wire_niiOi_dataout; + n0O1ii <= wire_n0OO0i_dataout; + n0O1il <= wire_n0OO0l_dataout; + n0O1iO <= wire_n0OO0O_dataout; + n0O1l <= wire_niiOl_dataout; + n0O1li <= wire_n0OOii_dataout; + n0O1ll <= wire_n0OOil_dataout; + n0O1lO <= wire_n0OOiO_dataout; + n0O1O <= wire_niiOO_dataout; + n0O1Oi <= wire_n0OOli_dataout; + n0O1Ol <= (n0O01i OR n0llii); + n0O1OO <= (n0O01i OR n0llil); + n0Oi1i <= wire_ni10ll_dataout; + n0Oi1l <= wire_ni10lO_dataout; + n0Oii <= wire_nil0i_dataout; + n0Oil <= wire_nil0l_dataout; + n0OiO <= wire_nil0O_dataout; + n0Oli <= wire_nilii_dataout; + n0Oll <= (n0OOi OR n0i0i); + n0OlO <= (n0OOi OR n0i0l); + n0OOi <= (NOT (((NOT (eidleinfersel(0) XOR nl0iO)) AND (NOT (wire_w_lg_w_eidleinfersel_range23w200w(0) XOR (NOT (nliO1lO26 XOR nliO1lO25))))) AND (NOT (wire_w_lg_w_eidleinfersel_range22w207w(0) XOR (NOT (nliO1li28 XOR nliO1li27)))))); + n0OOl <= nliO1Ol; + n0OOO <= nliO1OO; + n10ii <= (nlilOOi AND n10il); + n10il <= (nlilOOi AND n1lli); + n10iO <= n10li; + n10li <= nlilOOi; + n10ll <= n10lO; + n10lO <= n1lli; + n10Oi <= (n1lli AND (nlilOOO OR (nl0Oi AND nlill0i))); + n1101i <= wire_n1100i_o; + n1101l <= wire_n1100l_o; + n1101O <= wire_n11OOi_dataout; + n110i <= wire_n11il_o; + n110l <= wire_n11iO_o; + n110Ol <= wire_n11OOl_dataout; + n110OO <= wire_n11OOO_dataout; + n11i0i <= wire_n1010i_dataout; + n11i0l <= wire_n1010l_dataout; + n11i0O <= wire_n1010O_dataout; + n11i1i <= wire_n1011i_dataout; + n11i1l <= wire_n1011l_dataout; + n11i1O <= wire_n1011O_dataout; + n11ii <= ((((nlilOOi AND n10ii) OR wire_w_lg_nlilOOi432w(0)) OR wire_w_lg_nlilOOi436w(0)) OR (wire_w_lg_nlilOOO438w(0) AND (wire_w_lg_nlilOOi439w(0) AND (nlill0l AND n10li)))); + n11iii <= wire_n101ii_dataout; + n11iil <= wire_n101il_dataout; + n11iiO <= wire_n1000O_dataout; + n11ili <= wire_n100ii_dataout; + n11ill <= wire_n100il_dataout; + n11ilO <= wire_n100iO_dataout; + n11iOi <= wire_n100li_dataout; + n11iOl <= wire_n100ll_dataout; + n11iOO <= wire_n100lO_dataout; + n11l0i <= wire_n10i1i_dataout; + n11l0l <= wire_n10i1l_dataout; + n11l0O <= wire_n10i1O_dataout; + n11l1i <= wire_n100Oi_dataout; + n11l1l <= wire_n100Ol_dataout; + n11l1O <= wire_n100OO_dataout; + n11lii <= wire_n10i0i_dataout; + n11lil <= (n11lli OR n1101i); + n11liO <= (n11lli OR n1101l); + n11lli <= (NOT (((NOT (eidleinfersel(0) XOR n1i10l)) AND (NOT (eidleinfersel(1) XOR n1i10O))) AND (NOT (eidleinfersel(2) XOR n1i1ii)))); + n11lll <= nli0lii; + n11llO <= nli0lil; + n11lOi <= wire_n10lii_dataout; + n11lOl <= wire_n10lil_dataout; + n11lOO <= wire_n10liO_dataout; + n11O0i <= wire_n10lOi_dataout; + n11O0l <= wire_n10lOO_dataout; + n11O0O <= wire_n10O1i_dataout; + n11O1i <= wire_n10lli_dataout; + n11O1l <= wire_n10lll_dataout; + n11O1O <= wire_n10llO_dataout; + n11Oii <= wire_n10O1l_dataout; + n11Oil <= wire_n10O1O_dataout; + n11OiO <= wire_n10O0i_dataout; + n11Oli <= wire_n10O0l_dataout; + n11Oll <= wire_n10O0O_dataout; + n1i01i <= datain_ch2(5); + n1i01l <= datain_ch2(6); + n1i01O <= datain_ch2(7); + n1i0ii <= wire_n1i00l_dataout; + n1i0li <= n1i0ll; + n1i0ll <= n1i0iO; + n1i10l <= eidleinfersel(0); + n1i10O <= eidleinfersel(1); + n1i1ii <= eidleinfersel(2); + n1i1il <= n1i1iO; + n1i1iO <= rxvalid(2); + n1i1li <= datain_ch2(8); + n1i1ll <= datain_ch2(0); + n1i1lO <= datain_ch2(1); + n1i1Oi <= datain_ch2(2); + n1i1Ol <= datain_ch2(3); + n1i1OO <= datain_ch2(4); + n1iOl <= (wire_w_lg_w_lg_w_lg_nlilO1O382w384w385w(0) AND wire_nliii_w_lg_n1l1l386w(0)); + n1l0ii <= (nlii10O AND n1l0il); + n1l0il <= (nlii10O AND n1llli); + n1l0iO <= n1l0li; + n1l0li <= nlii10O; + n1l0ll <= n1l0lO; + n1l0lO <= n1llli; + n1l0Oi <= (n1llli AND (nlii1il OR (n000lO AND nli0O1l))); + n1l10i <= wire_n1l1il_o; + n1l10l <= wire_n1l1iO_o; + n1l1ii <= ((((nlii10O AND n1l0ii) OR wire_w_lg_nlii10O2595w(0)) OR wire_w_lg_nlii10O2599w(0)) OR (wire_w_lg_nlii1il2601w(0) AND (wire_w_lg_nlii10O2602w(0) AND (nli0O1O AND n1l0li)))); + n1l1l <= wire_n1O1l_dataout; + n1liOl <= (wire_w_lg_w_lg_w_lg_nli0OOO2545w2547w2548w(0) AND wire_nliii_w_lg_n1ll1l2549w(0)); + n1ll1l <= wire_n1lO1l_dataout; + n1lli <= nlilOOO; + n1lll <= wire_n0iiO_o; + n1llli <= nlii1il; + n1llll <= wire_n1OiiO_o; + n1Oi0i <= wire_n1Oiii_o; + n1Oi0l <= wire_n1Oiil_o; + n1Oi0O <= wire_n0101i_dataout; + n1Ol0i <= wire_n0100i_dataout; + n1Ol0l <= wire_n0100l_dataout; + n1Ol0O <= wire_n0100O_dataout; + n1Ol1l <= wire_n0101l_dataout; + n1Ol1O <= wire_n0101O_dataout; + n1Olii <= wire_n010ii_dataout; + n1Olil <= wire_n010il_dataout; + n1OliO <= wire_n010iO_dataout; + n1Olli <= wire_n010li_dataout; + n1Olll <= wire_n010ll_dataout; + n1OllO <= wire_n01iiO_dataout; + n1OlOi <= wire_n01ili_dataout; + n1OlOl <= wire_n01ill_dataout; + n1OlOO <= wire_n01ilO_dataout; + n1OO0i <= wire_n01l1i_dataout; + n1OO0l <= wire_n01l1l_dataout; + n1OO0O <= wire_n01l1O_dataout; + n1OO1i <= wire_n01iOi_dataout; + n1OO1l <= wire_n01iOl_dataout; + n1OO1O <= wire_n01iOO_dataout; + n1OOii <= wire_n01l0i_dataout; + n1OOil <= wire_n01l0l_dataout; + n1OOiO <= wire_n01l0O_dataout; + n1OOli <= wire_n01lii_dataout; + n1OOll <= (n1OOOi OR n1Oi0i); + n1OOlO <= (n1OOOi OR n1Oi0l); + n1OOOi <= (NOT (((NOT (eidleinfersel(0) XOR n000il)) AND (NOT (eidleinfersel(1) XOR n000iO))) AND (NOT (eidleinfersel(2) XOR n000li)))); + n1OOOl <= nlii1ll; + n1OOOO <= nlii1lO; + ni0ili <= wire_ni0iOl_o; + ni0ill <= wire_ni0iOO_o; + ni0iOi <= ((((nliiOlO AND ni0lOi) OR wire_w_lg_nliiOlO1521w(0)) OR wire_w_lg_nliiOlO1525w(0)) OR (wire_w_lg_nliiOOl1527w(0) AND (wire_w_lg_nliiOlO1528w(0) AND (nliilli AND ni0O1i)))); + ni0lOi <= (nliiOlO AND ni0lOl); + ni0lOl <= (nliiOlO AND nii01i); + ni0lOO <= ni0O1i; + ni0O0i <= (nii01i AND (nliiOOl OR (niOO1O AND nliiliO))); + ni0O1i <= nliiOlO; + ni0O1l <= ni0O1O; + ni0O1O <= nii01i; + ni10i <= wire_niOOi_dataout; + ni10l <= wire_niOOl_dataout; + ni10O <= wire_niOOO_dataout; + ni11i <= wire_niOli_dataout; + ni11l <= wire_niOll_dataout; + ni11O <= wire_niOlO_dataout; + ni1ii <= wire_nl11i_dataout; + ni1il <= wire_nl11O_dataout; + ni1ill <= eidleinfersel(0); + ni1ilO <= eidleinfersel(1); + ni1iO <= wire_nl10i_dataout; + ni1iOi <= eidleinfersel(2); + ni1iOl <= ni1iOO; + ni1iOO <= rxvalid(4); + ni1l0i <= datain_ch4(2); + ni1l0l <= datain_ch4(3); + ni1l0O <= datain_ch4(4); + ni1l1i <= datain_ch4(8); + ni1l1l <= datain_ch4(0); + ni1l1O <= datain_ch4(1); + ni1li <= wire_nl10l_dataout; + ni1lii <= datain_ch4(5); + ni1lil <= datain_ch4(6); + ni1liO <= datain_ch4(7); + ni1ll <= wire_nl10O_dataout; + ni1lO <= wire_nl1ii_dataout; + ni1lOi <= wire_ni1lll_dataout; + ni1O1i <= ni1O1l; + ni1O1l <= ni1lOO; + ni1Oi <= wire_nl1il_dataout; + ni1Ol <= wire_nl1iO_dataout; + nii01i <= nliiOOl; + nii01l <= wire_niiOOO_o; + nii10l <= (wire_w_lg_w_lg_w_lg_nliiO0O1471w1473w1474w(0) AND wire_nliii_w_lg_nii1il1475w(0)); + nii1il <= wire_nii0il_dataout; + niiOli <= wire_niiOOi_o; + niiOll <= wire_niiOOl_o; + niiOlO <= wire_nillii_dataout; + nil00i <= wire_niO11i_dataout; + nil00l <= wire_niO11l_dataout; + nil00O <= wire_niO11O_dataout; + nil01i <= wire_nilO1i_dataout; + nil01l <= wire_nilO1l_dataout; + nil01O <= wire_nilOOO_dataout; + nil0ii <= wire_niO10i_dataout; + nil0il <= wire_niO10l_dataout; + nil0iO <= wire_niO10O_dataout; + nil0li <= wire_niO1ii_dataout; + nil0ll <= wire_niO1il_dataout; + nil0lO <= wire_niO1iO_dataout; + nil0Oi <= wire_niO1li_dataout; + nil0Ol <= wire_niO1ll_dataout; + nil0OO <= wire_niO1lO_dataout; + nil1il <= wire_nillil_dataout; + nil1iO <= wire_nilliO_dataout; + nil1li <= wire_nillli_dataout; + nil1ll <= wire_nillll_dataout; + nil1lO <= wire_nilllO_dataout; + nil1Oi <= wire_nillOi_dataout; + nil1Ol <= wire_nillOl_dataout; + nil1OO <= wire_nillOO_dataout; + nili0i <= (NOT (((NOT (eidleinfersel(0) XOR niOlOl)) AND (NOT (eidleinfersel(1) XOR niOlOO))) AND (NOT (eidleinfersel(2) XOR niOO1i)))); + nili0l <= nlil11l; + nili0O <= nlil11O; + nili1i <= wire_niO1Oi_dataout; + nili1l <= (nili0i OR niiOli); + nili1O <= (nili0i OR niiOll); + niliii <= wire_niOi1i_dataout; + niliil <= wire_niOi1l_dataout; + niliiO <= wire_niOi1O_dataout; + nilili <= wire_niOi0i_dataout; + nilill <= wire_niOi0l_dataout; + nililO <= wire_niOi0O_dataout; + niliOi <= wire_niOiii_dataout; + niliOl <= wire_niOiiO_dataout; + niliOO <= wire_niOili_dataout; + nill0i <= wire_niOiOl_dataout; + nill0l <= wire_niOiOO_dataout; + nill1i <= wire_niOill_dataout; + nill1l <= wire_niOilO_dataout; + nill1O <= wire_niOiOi_dataout; + niOlOl <= eidleinfersel(0); + niOlOO <= eidleinfersel(1); + niOO0i <= datain_ch5(8); + niOO0l <= datain_ch5(0); + niOO0O <= datain_ch5(1); + niOO1i <= eidleinfersel(2); + niOO1l <= niOO1O; + niOO1O <= rxvalid(5); + niOOii <= datain_ch5(2); + niOOil <= datain_ch5(3); + niOOiO <= datain_ch5(4); + niOOli <= datain_ch5(5); + niOOll <= datain_ch5(6); + niOOlO <= datain_ch5(7); + nl00il <= (wire_w_lg_w_lg_w_lg_nlil0iO934w936w937w(0) AND wire_nliii_w_lg_nl00ll938w(0)); + nl00ll <= wire_nl0ill_dataout; + nl010i <= nlil0OO; + nl010l <= nl010O; + nl010O <= nl0i0i; + nl011i <= (nlil0OO AND nl011l); + nl011l <= (nlil0OO AND nl0i0i); + nl011O <= nl010i; + nl01ii <= (nl0i0i AND (nlili1l OR (nlO10O AND nlil1lO))); + nl0i0i <= nlili1l; + nl0i0l <= wire_nli01O_o; + nl0iO <= eidleinfersel(0); + nl0li <= eidleinfersel(1); + nl0ll <= eidleinfersel(2); + nl0lO <= nl0Oi; + nl0Oi <= rxvalid(7); + nl0Ol <= datain_ch7(8); + nl0OO <= datain_ch7(0); + nl110i <= nl110l; + nl110l <= nl111O; + nl111i <= wire_niOOOl_dataout; + nl1lOi <= wire_nl1O1l_o; + nl1lOl <= wire_nl1O1O_o; + nl1O1i <= ((((nlil0OO AND nl011i) OR wire_w_lg_nlil0OO984w(0)) OR wire_w_lg_nlil0OO988w(0)) OR (wire_w_lg_nlili1l990w(0) AND (wire_w_lg_nlil0OO991w(0) AND (nlil1Oi AND nl010i)))); + nli0i <= datain_ch7(4); + nli0l <= datain_ch7(5); + nli0ll <= wire_nliOll_dataout; + nli0lO <= wire_nliOlO_dataout; + nli0O <= datain_ch7(6); + nli0Oi <= wire_nliOOi_dataout; + nli0Ol <= wire_nliOOl_dataout; + nli0OO <= wire_nliOOO_dataout; + nli1i <= datain_ch7(1); + nli1l <= datain_ch7(2); + nli1O <= datain_ch7(3); + nli1Oi <= wire_nli01i_o; + nli1Ol <= wire_nli01l_o; + nli1OO <= wire_nliOli_dataout; + nlii0i <= wire_nll10i_dataout; + nlii0l <= wire_nll10l_dataout; + nlii0O <= wire_nll01O_dataout; + nlii1i <= wire_nll11i_dataout; + nlii1l <= wire_nll11l_dataout; + nlii1O <= wire_nll11O_dataout; + nliiii <= wire_nll00i_dataout; + nliiil <= wire_nll00l_dataout; + nliiiO <= wire_nll00O_dataout; + nliil <= datain_ch7(7); + nliili <= wire_nll0ii_dataout; + nliill <= wire_nll0il_dataout; + nliilO <= wire_nll0iO_dataout; + nliiOi <= wire_nll0li_dataout; + nliiOl <= wire_nll0ll_dataout; + nliiOO <= wire_nll0lO_dataout; + nlil0i <= wire_nlli1i_dataout; + nlil0l <= (nlilii OR nli1Oi); + nlil0O <= (nlilii OR nli1Ol); + nlil1i <= wire_nll0Oi_dataout; + nlil1l <= wire_nll0Ol_dataout; + nlil1O <= wire_nll0OO_dataout; + nlilii <= (NOT (((NOT (eidleinfersel(0) XOR nlO11l)) AND (NOT (eidleinfersel(1) XOR nlO11O))) AND (NOT (eidleinfersel(2) XOR nlO10i)))); + nlilil <= nlili0l; + nliliO <= nlili0O; + nlilli <= wire_nlll0i_dataout; + nlilll <= wire_nlll0l_dataout; + nlillO <= wire_nlll0O_dataout; + nlilOi <= wire_nlllii_dataout; + nlilOl <= wire_nlllil_dataout; + nlilOO <= wire_nllliO_dataout; + nliO0i <= wire_nlllOl_dataout; + nliO0l <= wire_nlllOO_dataout; + nliO0O <= wire_nllO1i_dataout; + nliO1i <= wire_nlllli_dataout; + nliO1l <= wire_nllllO_dataout; + nliO1O <= wire_nlllOi_dataout; + nliOii <= wire_nllO1l_dataout; + nliOil <= wire_nllO1O_dataout; + nliOiOi <= wire_nliOill_dataout; + nliOl1i <= nliOl1l; + nliOl1l <= nliOiOO; + nll011i <= nli1llO; + nll011l <= wire_nll0lOO_o; + nll0lli <= wire_nll0lOi_o; + nll0lll <= wire_nll0lOl_o; + nll0llO <= wire_nlliiii_dataout; + nll0Oil <= wire_nlliiil_dataout; + nll0OiO <= wire_nlliiiO_dataout; + nll0Oli <= wire_nlliili_dataout; + nll0Oll <= wire_nlliill_dataout; + nll0OlO <= wire_nlliilO_dataout; + nll0OOi <= wire_nlliiOi_dataout; + nll0OOl <= wire_nlliiOl_dataout; + nll0OOO <= wire_nlliiOO_dataout; + nll10li <= wire_nll10Ol_o; + nll10ll <= wire_nll10OO_o; + nll10Oi <= ((((nli1lli AND nll1iOi) OR wire_w_lg_nli1lli4206w(0)) OR wire_w_lg_nli1lli4210w(0)) OR (wire_w_lg_nli1llO4212w(0) AND (wire_w_lg_nli1lli4213w(0) AND (nli1iil AND nll1l1i)))); + nll1iOi <= (nli1lli AND nll1iOl); + nll1iOl <= (nli1lli AND nll011i); + nll1iOO <= nll1l1i; + nll1l0i <= (nll011i AND (nli1llO OR (nllll1O AND nli1iii))); + nll1l1i <= nli1lli; + nll1l1l <= nll1l1O; + nll1l1O <= nll011i; + nll1O0l <= (wire_w_lg_w_lg_w_lg_nli1l0i4156w4158w4159w(0) AND wire_nliii_w_lg_nll1Oil4160w(0)); + nll1Oil <= wire_nll01il_dataout; + nlli00i <= (NOT (((NOT (eidleinfersel(0) XOR nllliOl)) AND (NOT (eidleinfersel(1) XOR nllliOO))) AND (NOT (eidleinfersel(2) XOR nllll1i)))); + nlli00l <= nli1lOO; + nlli00O <= nli1O1i; + nlli01i <= wire_nlliOOi_dataout; + nlli01l <= (nlli00i OR nll0lli); + nlli01O <= (nlli00i OR nll0lll); + nlli0ii <= wire_nlll01i_dataout; + nlli0il <= wire_nlll01l_dataout; + nlli0iO <= wire_nlll01O_dataout; + nlli0li <= wire_nlll00i_dataout; + nlli0ll <= wire_nlll00l_dataout; + nlli0lO <= wire_nlll00O_dataout; + nlli0Oi <= wire_nlll0ii_dataout; + nlli0Ol <= wire_nlll0iO_dataout; + nlli0OO <= wire_nlll0li_dataout; + nlli10i <= wire_nlliO1i_dataout; + nlli10l <= wire_nlliO1l_dataout; + nlli10O <= wire_nlliO1O_dataout; + nlli11i <= wire_nllil1i_dataout; + nlli11l <= wire_nllil1l_dataout; + nlli11O <= wire_nllilOO_dataout; + nlli1ii <= wire_nlliO0i_dataout; + nlli1il <= wire_nlliO0l_dataout; + nlli1iO <= wire_nlliO0O_dataout; + nlli1li <= wire_nlliOii_dataout; + nlli1ll <= wire_nlliOil_dataout; + nlli1lO <= wire_nlliOiO_dataout; + nlli1Oi <= wire_nlliOli_dataout; + nlli1Ol <= wire_nlliOll_dataout; + nlli1OO <= wire_nlliOlO_dataout; + nllii0i <= wire_nlll0Ol_dataout; + nllii0l <= wire_nlll0OO_dataout; + nllii1i <= wire_nlll0ll_dataout; + nllii1l <= wire_nlll0lO_dataout; + nllii1O <= wire_nlll0Oi_dataout; + nllliOl <= eidleinfersel(0); + nllliOO <= eidleinfersel(1); + nllll0i <= datain_ch0(8); + nllll0l <= datain_ch0(0); + nllll0O <= datain_ch0(1); + nllll1i <= eidleinfersel(2); + nllll1l <= nllll1O; + nllll1O <= rxvalid(0); + nllllii <= datain_ch0(2); + nllllil <= datain_ch0(3); + nlllliO <= datain_ch0(4); + nllllli <= datain_ch0(5); + nllllll <= datain_ch0(6); + nlllllO <= datain_ch0(7); + nlllO0i <= nlllO0l; + nlllO0l <= nlllO1O; + nlllO1i <= wire_nllllOl_dataout; + nllOiOi <= wire_nllOl1l_o; + nllOiOl <= wire_nllOl1O_o; + nllOl1i <= ((((nli01Oi AND nllOO1i) OR wire_w_lg_nli01Oi3669w(0)) OR wire_w_lg_nli01Oi3673w(0)) OR (wire_w_lg_nli01OO3675w(0) AND (wire_w_lg_nli01Oi3676w(0) AND (nli1Oll AND nllOO0i)))); + nllOO0i <= nli01Oi; + nllOO0l <= nllOO0O; + nllOO0O <= nlO100i; + nllOO1i <= (nli01Oi AND nllOO1l); + nllOO1l <= (nli01Oi AND nlO100i); + nllOO1O <= nllOO0i; + nllOOii <= (nlO100i AND (nli01OO OR (nlOiO0O AND nli1Oli))); + nlO000i <= wire_nlO0O0i_dataout; + nlO000l <= wire_nlO0O0l_dataout; + nlO000O <= wire_nlOi11O_dataout; + nlO001i <= wire_nlO0O1i_dataout; + nlO001l <= wire_nlO0O1l_dataout; + nlO001O <= wire_nlO0O1O_dataout; + nlO00ii <= wire_nlOi10i_dataout; + nlO00il <= wire_nlOi10l_dataout; + nlO00iO <= wire_nlOi10O_dataout; + nlO00l <= wire_nlO01O_dataout; + nlO00li <= wire_nlOi1ii_dataout; + nlO00ll <= wire_nlOi1il_dataout; + nlO00lO <= wire_nlOi1iO_dataout; + nlO00Oi <= wire_nlOi1li_dataout; + nlO00Ol <= wire_nlOi1ll_dataout; + nlO00OO <= wire_nlOi1lO_dataout; + nlO01ll <= wire_nlO0lll_dataout; + nlO01lO <= wire_nlO0llO_dataout; + nlO01Oi <= wire_nlO0lOi_dataout; + nlO01Ol <= wire_nlO0lOl_dataout; + nlO01OO <= wire_nlO0lOO_dataout; + nlO0i0i <= wire_nlOi01i_dataout; + nlO0i0l <= (nlO0iii OR nlO1OOi); + nlO0i0O <= (nlO0iii OR nlO1OOl); + nlO0i1i <= wire_nlOi1Oi_dataout; + nlO0i1l <= wire_nlOi1Ol_dataout; + nlO0i1O <= wire_nlOi1OO_dataout; + nlO0iii <= (NOT (((NOT (eidleinfersel(0) XOR nlOiO1l)) AND (NOT (eidleinfersel(1) XOR nlOiO1O))) AND (NOT (eidleinfersel(2) XOR nlOiO0i)))); + nlO0iil <= nli001O; + nlO0iiO <= nli000i; + nlO0ili <= wire_nlOii0i_dataout; + nlO0ill <= wire_nlOii0l_dataout; + nlO0ilO <= wire_nlOii0O_dataout; + nlO0iO <= nlO0li; + nlO0iOi <= wire_nlOiiii_dataout; + nlO0iOl <= wire_nlOiiil_dataout; + nlO0iOO <= wire_nlOiiiO_dataout; + nlO0l0i <= wire_nlOiiOl_dataout; + nlO0l0l <= wire_nlOiiOO_dataout; + nlO0l0O <= wire_nlOil1i_dataout; + nlO0l1i <= wire_nlOiili_dataout; + nlO0l1l <= wire_nlOiilO_dataout; + nlO0l1O <= wire_nlOiiOi_dataout; + nlO0li <= nlO0il; + nlO0lii <= wire_nlOil1l_dataout; + nlO0lil <= wire_nlOil1O_dataout; + nlO100i <= nli01OO; + nlO100l <= wire_nlO011O_o; + nlO10i <= eidleinfersel(2); + nlO10l <= nlO10O; + nlO10O <= rxvalid(6); + nlO11il <= (wire_w_lg_w_lg_w_lg_nli01ii3619w3621w3622w(0) AND wire_nliii_w_lg_nlO11ll3623w(0)); + nlO11l <= eidleinfersel(0); + nlO11ll <= wire_nlO10ll_dataout; + nlO11O <= eidleinfersel(1); + nlO1ii <= datain_ch6(8); + nlO1il <= datain_ch6(0); + nlO1iO <= datain_ch6(1); + nlO1li <= datain_ch6(2); + nlO1ll <= datain_ch6(3); + nlO1lO <= datain_ch6(4); + nlO1Oi <= datain_ch6(5); + nlO1Ol <= datain_ch6(6); + nlO1OO <= datain_ch6(7); + nlO1OOi <= wire_nlO011i_o; + nlO1OOl <= wire_nlO011l_o; + nlO1OOO <= wire_nlO0lli_dataout; + nlOiO0i <= eidleinfersel(2); + nlOiO0l <= nlOiO0O; + nlOiO0O <= rxvalid(1); + nlOiO1l <= eidleinfersel(0); + nlOiO1O <= eidleinfersel(1); + nlOiOii <= datain_ch1(8); + nlOiOil <= datain_ch1(0); + nlOiOiO <= datain_ch1(1); + nlOiOli <= datain_ch1(2); + nlOiOll <= datain_ch1(3); + nlOiOlO <= datain_ch1(4); + nlOiOOi <= datain_ch1(5); + nlOiOOl <= datain_ch1(6); + nlOiOOO <= datain_ch1(7); + nlOl10i <= wire_nlOl11l_dataout; + nlOl1ii <= nlOl1il; + nlOl1il <= nlOl10O; + nlOlO0i <= ((((nli0l1l AND nlOO10i) OR wire_w_lg_nli0l1l3133w(0)) OR wire_w_lg_nli0l1l3137w(0)) OR (wire_w_lg_nli0l0i3139w(0) AND (wire_w_lg_nli0l1l3140w(0) AND (nli00Ol AND nlOO1ii)))); + nlOlO1i <= wire_nlOlO0l_o; + nlOlO1l <= wire_nlOlO0O_o; + nlOO0ll <= (wire_w_lg_w_lg_w_lg_nli0ill3083w3085w3086w(0) AND wire_nliii_w_lg_nlOO0Ol3087w(0)); + nlOO0Ol <= wire_nlOOiOl_dataout; + nlOO10i <= (nli0l1l AND nlOO10l); + nlOO10l <= (nli0l1l AND nlOOiii); + nlOO10O <= nlOO1ii; + nlOO1ii <= nli0l1l; + nlOO1il <= nlOO1iO; + nlOO1iO <= nlOOiii; + nlOO1li <= (nlOOiii AND (nli0l0i OR (n1i1iO AND nli00Oi))); + nlOOiii <= nli0l0i; + nlOOiil <= wire_n1100O_o; + END IF; + END PROCESS; + wire_nliii_CLRN <= ((nliOiiO2 XOR nliOiiO1) AND prstn); + wire_nliii_w_lg_w_lg_w_lg_w2757w2758w2759w2760w(0) <= wire_nliii_w_lg_w_lg_w2757w2758w2759w(0) AND n000Ol; + wire_nliii_w_lg_w_lg_w_lg_w2117w2118w2120w2132w(0) <= wire_nliii_w_lg_w_lg_w2117w2118w2120w(0) AND n0O10O; + wire_nliii_w_lg_w_lg_w494w496w508w(0) <= wire_nliii_w_lg_w494w496w(0) AND n0O1O; + wire_nliii_w_lg_w_lg_w_lg_w3193w3194w3196w3208w(0) <= wire_nliii_w_lg_w_lg_w3193w3194w3196w(0) AND n11iOO; + wire_nliii_w_lg_w_lg_w_lg_w3295w3296w3297w3298w(0) <= wire_nliii_w_lg_w_lg_w3295w3296w3297w(0) AND n1i1ll; + wire_nliii_w_lg_w_lg_w_lg_w2655w2656w2658w2670w(0) <= wire_nliii_w_lg_w_lg_w2655w2656w2658w(0) AND n1OO1O; + wire_nliii_w_lg_w_lg_w_lg_w2219w2220w2221w2222w(0) <= wire_nliii_w_lg_w_lg_w2219w2220w2221w(0) AND ni1l1l; + wire_nliii_w_lg_w_lg_w_lg_w1581w1582w1584w1596w(0) <= wire_nliii_w_lg_w_lg_w1581w1582w1584w(0) AND nil0iO; + wire_nliii_w_lg_w_lg_w_lg_w1683w1684w1685w1686w(0) <= wire_nliii_w_lg_w_lg_w1683w1684w1685w(0) AND niOO0l; + wire_nliii_w_lg_w_lg_w606w607w608w(0) <= wire_nliii_w_lg_w606w607w(0) AND nl0OO; + wire_nliii_w_lg_w_lg_w_lg_w1044w1045w1047w1059w(0) <= wire_nliii_w_lg_w_lg_w1044w1045w1047w(0) AND nliilO; + wire_nliii_w_lg_w_lg_w_lg_w4266w4267w4269w4281w(0) <= wire_nliii_w_lg_w_lg_w4266w4267w4269w(0) AND nlli1iO; + wire_nliii_w_lg_w_lg_w_lg_w4368w4369w4370w4371w(0) <= wire_nliii_w_lg_w_lg_w4368w4369w4370w(0) AND nllll0l; + wire_nliii_w_lg_w_lg_w_lg_w3729w3730w3732w3744w(0) <= wire_nliii_w_lg_w_lg_w3729w3730w3732w(0) AND nlO00lO; + wire_nliii_w_lg_w_lg_w_lg_w1146w1147w1148w1149w(0) <= wire_nliii_w_lg_w_lg_w1146w1147w1148w(0) AND nlO1il; + wire_nliii_w_lg_w_lg_w_lg_w3831w3832w3833w3834w(0) <= wire_nliii_w_lg_w_lg_w3831w3832w3833w(0) AND nlOiOil; + wire_nliii_w_lg_w_lg_w2740w2741w2742w(0) <= wire_nliii_w_lg_w2740w2741w(0) AND n000Ol; + wire_nliii_w_lg_w_lg_w3278w3279w3280w(0) <= wire_nliii_w_lg_w3278w3279w(0) AND n1i1ll; + wire_nliii_w_lg_w_lg_w2202w2203w2204w(0) <= wire_nliii_w_lg_w2202w2203w(0) AND ni1l1l; + wire_nliii_w_lg_w_lg_w1666w1667w1668w(0) <= wire_nliii_w_lg_w1666w1667w(0) AND niOO0l; + wire_nliii_w_lg_w589w590w(0) <= wire_nliii_w589w(0) AND nl0OO; + wire_nliii_w_lg_w_lg_w4351w4352w4353w(0) <= wire_nliii_w_lg_w4351w4352w(0) AND nllll0l; + wire_nliii_w_lg_w_lg_w1129w1130w1131w(0) <= wire_nliii_w_lg_w1129w1130w(0) AND nlO1il; + wire_nliii_w_lg_w_lg_w3814w3815w3816w(0) <= wire_nliii_w_lg_w3814w3815w(0) AND nlOiOil; + wire_nliii_w_lg_w_lg_w2757w2758w2759w(0) <= wire_nliii_w_lg_w2757w2758w(0) AND wire_nliii_w_lg_n000OO2707w(0); + wire_nliii_w_lg_w_lg_w2747w2749w2750w(0) <= wire_nliii_w_lg_w2747w2749w(0) AND n000OO; + wire_nliii_w_lg_w_lg_w2117w2118w2120w(0) <= wire_nliii_w_lg_w2117w2118w(0) AND wire_nliii_w_lg_n0O1ii2119w(0); + wire_nliii_w_lg_w494w496w(0) <= wire_nliii_w494w(0) AND wire_nliii_w_lg_n0O0i495w(0); + wire_nliii_w_lg_w_lg_w3193w3194w3196w(0) <= wire_nliii_w_lg_w3193w3194w(0) AND wire_nliii_w_lg_n11l1i3195w(0); + wire_nliii_w_lg_w_lg_w3295w3296w3297w(0) <= wire_nliii_w_lg_w3295w3296w(0) AND wire_nliii_w_lg_n1i1lO3245w(0); + wire_nliii_w_lg_w_lg_w3285w3287w3288w(0) <= wire_nliii_w_lg_w3285w3287w(0) AND n1i1lO; + wire_nliii_w_lg_w_lg_w2655w2656w2658w(0) <= wire_nliii_w_lg_w2655w2656w(0) AND wire_nliii_w_lg_n1OO0i2657w(0); + wire_nliii_w_lg_w_lg_w2219w2220w2221w(0) <= wire_nliii_w_lg_w2219w2220w(0) AND wire_nliii_w_lg_ni1l1O2169w(0); + wire_nliii_w_lg_w_lg_w2209w2211w2212w(0) <= wire_nliii_w_lg_w2209w2211w(0) AND ni1l1O; + wire_nliii_w_lg_w_lg_w1581w1582w1584w(0) <= wire_nliii_w_lg_w1581w1582w(0) AND wire_nliii_w_lg_nil0li1583w(0); + wire_nliii_w_lg_w_lg_w1683w1684w1685w(0) <= wire_nliii_w_lg_w1683w1684w(0) AND wire_nliii_w_lg_niOO0O1633w(0); + wire_nliii_w_lg_w_lg_w1673w1675w1676w(0) <= wire_nliii_w_lg_w1673w1675w(0) AND niOO0O; + wire_nliii_w_lg_w606w607w(0) <= wire_nliii_w606w(0) AND wire_nliii_w_lg_nli1i555w(0); + wire_nliii_w_lg_w597w598w(0) <= wire_nliii_w597w(0) AND nli1i; + wire_nliii_w_lg_w_lg_w1044w1045w1047w(0) <= wire_nliii_w_lg_w1044w1045w(0) AND wire_nliii_w_lg_nliiOi1046w(0); + wire_nliii_w_lg_w_lg_w4266w4267w4269w(0) <= wire_nliii_w_lg_w4266w4267w(0) AND wire_nliii_w_lg_nlli1li4268w(0); + wire_nliii_w_lg_w_lg_w4368w4369w4370w(0) <= wire_nliii_w_lg_w4368w4369w(0) AND wire_nliii_w_lg_nllll0O4318w(0); + wire_nliii_w_lg_w_lg_w4358w4360w4361w(0) <= wire_nliii_w_lg_w4358w4360w(0) AND nllll0O; + wire_nliii_w_lg_w_lg_w3729w3730w3732w(0) <= wire_nliii_w_lg_w3729w3730w(0) AND wire_nliii_w_lg_nlO00Oi3731w(0); + wire_nliii_w_lg_w_lg_w1146w1147w1148w(0) <= wire_nliii_w_lg_w1146w1147w(0) AND wire_nliii_w_lg_nlO1iO1096w(0); + wire_nliii_w_lg_w_lg_w1136w1138w1139w(0) <= wire_nliii_w_lg_w1136w1138w(0) AND nlO1iO; + wire_nliii_w_lg_w_lg_w3831w3832w3833w(0) <= wire_nliii_w_lg_w3831w3832w(0) AND wire_nliii_w_lg_nlOiOiO3781w(0); + wire_nliii_w_lg_w_lg_w3821w3823w3824w(0) <= wire_nliii_w_lg_w3821w3823w(0) AND nlOiOiO; + wire_nliii_w_lg_w2740w2741w(0) <= wire_nliii_w2740w(0) AND wire_nliii_w_lg_n000OO2707w(0); + wire_nliii_w_lg_w2753w2754w(0) <= wire_nliii_w2753w(0) AND n000OO; + wire_nliii_w_lg_w3278w3279w(0) <= wire_nliii_w3278w(0) AND wire_nliii_w_lg_n1i1lO3245w(0); + wire_nliii_w_lg_w3291w3292w(0) <= wire_nliii_w3291w(0) AND n1i1lO; + wire_nliii_w_lg_w2202w2203w(0) <= wire_nliii_w2202w(0) AND wire_nliii_w_lg_ni1l1O2169w(0); + wire_nliii_w_lg_w2215w2216w(0) <= wire_nliii_w2215w(0) AND ni1l1O; + wire_nliii_w_lg_w1666w1667w(0) <= wire_nliii_w1666w(0) AND wire_nliii_w_lg_niOO0O1633w(0); + wire_nliii_w_lg_w1679w1680w(0) <= wire_nliii_w1679w(0) AND niOO0O; + wire_nliii_w589w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w587w588w(0) AND wire_nliii_w_lg_nli1i555w(0); + wire_nliii_w602w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w601w(0) AND nli1i; + wire_nliii_w_lg_w4351w4352w(0) <= wire_nliii_w4351w(0) AND wire_nliii_w_lg_nllll0O4318w(0); + wire_nliii_w_lg_w4364w4365w(0) <= wire_nliii_w4364w(0) AND nllll0O; + wire_nliii_w_lg_w1129w1130w(0) <= wire_nliii_w1129w(0) AND wire_nliii_w_lg_nlO1iO1096w(0); + wire_nliii_w_lg_w1142w1143w(0) <= wire_nliii_w1142w(0) AND nlO1iO; + wire_nliii_w_lg_w3814w3815w(0) <= wire_nliii_w3814w(0) AND wire_nliii_w_lg_nlOiOiO3781w(0); + wire_nliii_w_lg_w3827w3828w(0) <= wire_nliii_w3827w(0) AND nlOiOiO; + wire_nliii_w_lg_w2725w2726w(0) <= wire_nliii_w2725w(0) AND n00i1i; + wire_nliii_w_lg_w2757w2758w(0) <= wire_nliii_w2757w(0) AND n00i1i; + wire_nliii_w_lg_w2747w2749w(0) <= wire_nliii_w2747w(0) AND wire_nliii_w_lg_n00i1i2748w(0); + wire_nliii_w_lg_w2716w2717w(0) <= wire_nliii_w2716w(0) AND n00i1i; + wire_nliii_w_lg_w2117w2118w(0) <= wire_nliii_w2117w(0) AND wire_nliii_w_lg_n0O1il2083w(0); + wire_nliii_w494w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0Oli473w487w489w491w493w(0) AND wire_nliii_w_lg_n0O0l458w(0); + wire_nliii_w_lg_w3193w3194w(0) <= wire_nliii_w3193w(0) AND wire_nliii_w_lg_n11l1l3159w(0); + wire_nliii_w_lg_w3263w3264w(0) <= wire_nliii_w3263w(0) AND n1i1Oi; + wire_nliii_w_lg_w3295w3296w(0) <= wire_nliii_w3295w(0) AND n1i1Oi; + wire_nliii_w_lg_w3285w3287w(0) <= wire_nliii_w3285w(0) AND wire_nliii_w_lg_n1i1Oi3286w(0); + wire_nliii_w_lg_w3254w3255w(0) <= wire_nliii_w3254w(0) AND n1i1Oi; + wire_nliii_w_lg_w2655w2656w(0) <= wire_nliii_w2655w(0) AND wire_nliii_w_lg_n1OO0l2621w(0); + wire_nliii_w_lg_w2187w2188w(0) <= wire_nliii_w2187w(0) AND ni1l0i; + wire_nliii_w_lg_w2219w2220w(0) <= wire_nliii_w2219w(0) AND ni1l0i; + wire_nliii_w_lg_w2209w2211w(0) <= wire_nliii_w2209w(0) AND wire_nliii_w_lg_ni1l0i2210w(0); + wire_nliii_w_lg_w2178w2179w(0) <= wire_nliii_w2178w(0) AND ni1l0i; + wire_nliii_w_lg_w1581w1582w(0) <= wire_nliii_w1581w(0) AND wire_nliii_w_lg_nil0ll1547w(0); + wire_nliii_w_lg_w1651w1652w(0) <= wire_nliii_w1651w(0) AND niOOii; + wire_nliii_w_lg_w1683w1684w(0) <= wire_nliii_w1683w(0) AND niOOii; + wire_nliii_w_lg_w1673w1675w(0) <= wire_nliii_w1673w(0) AND wire_nliii_w_lg_niOOii1674w(0); + wire_nliii_w_lg_w1642w1643w(0) <= wire_nliii_w1642w(0) AND niOOii; + wire_nliii_w574w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w569w571w572w573w(0) AND nli1l; + wire_nliii_w606w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w605w(0) AND nli1l; + wire_nliii_w597w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w595w(0) AND wire_nliii_w_lg_nli1l596w(0); + wire_nliii_w565w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w562w563w564w(0) AND nli1l; + wire_nliii_w_lg_w1044w1045w(0) <= wire_nliii_w1044w(0) AND wire_nliii_w_lg_nliiOl1010w(0); + wire_nliii_w_lg_w4266w4267w(0) <= wire_nliii_w4266w(0) AND wire_nliii_w_lg_nlli1ll4232w(0); + wire_nliii_w_lg_w4336w4337w(0) <= wire_nliii_w4336w(0) AND nllllii; + wire_nliii_w_lg_w4368w4369w(0) <= wire_nliii_w4368w(0) AND nllllii; + wire_nliii_w_lg_w4358w4360w(0) <= wire_nliii_w4358w(0) AND wire_nliii_w_lg_nllllii4359w(0); + wire_nliii_w_lg_w4327w4328w(0) <= wire_nliii_w4327w(0) AND nllllii; + wire_nliii_w_lg_w3729w3730w(0) <= wire_nliii_w3729w(0) AND wire_nliii_w_lg_nlO00Ol3695w(0); + wire_nliii_w_lg_w1114w1115w(0) <= wire_nliii_w1114w(0) AND nlO1li; + wire_nliii_w_lg_w1146w1147w(0) <= wire_nliii_w1146w(0) AND nlO1li; + wire_nliii_w_lg_w1136w1138w(0) <= wire_nliii_w1136w(0) AND wire_nliii_w_lg_nlO1li1137w(0); + wire_nliii_w_lg_w1105w1106w(0) <= wire_nliii_w1105w(0) AND nlO1li; + wire_nliii_w_lg_w3799w3800w(0) <= wire_nliii_w3799w(0) AND nlOiOli; + wire_nliii_w_lg_w3831w3832w(0) <= wire_nliii_w3831w(0) AND nlOiOli; + wire_nliii_w_lg_w3821w3823w(0) <= wire_nliii_w3821w(0) AND wire_nliii_w_lg_nlOiOli3822w(0); + wire_nliii_w_lg_w3790w3791w(0) <= wire_nliii_w3790w(0) AND nlOiOli; + wire_nliii_w2740w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w2739w(0) AND n00i1i; + wire_nliii_w2753w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w2705w(0) AND wire_nliii_w_lg_n00i1i2748w(0); + wire_nliii_w2706w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w2705w(0) AND n00i1i; + wire_nliii_w3278w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w3277w(0) AND n1i1Oi; + wire_nliii_w3291w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w3243w(0) AND wire_nliii_w_lg_n1i1Oi3286w(0); + wire_nliii_w3244w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w3243w(0) AND n1i1Oi; + wire_nliii_w2202w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w2201w(0) AND ni1l0i; + wire_nliii_w2215w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w2167w(0) AND wire_nliii_w_lg_ni1l0i2210w(0); + wire_nliii_w2168w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w2167w(0) AND ni1l0i; + wire_nliii_w1666w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w1665w(0) AND niOOii; + wire_nliii_w1679w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w1631w(0) AND wire_nliii_w_lg_niOOii1674w(0); + wire_nliii_w1632w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w1631w(0) AND niOOii; + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w587w588w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w587w(0) AND nli1l; + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w601w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w(0) AND wire_nliii_w_lg_nli1l596w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w554w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w(0) AND nli1l; + wire_nliii_w4351w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w4350w(0) AND nllllii; + wire_nliii_w4364w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w4316w(0) AND wire_nliii_w_lg_nllllii4359w(0); + wire_nliii_w4317w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w4316w(0) AND nllllii; + wire_nliii_w1129w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w1128w(0) AND nlO1li; + wire_nliii_w1142w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w1094w(0) AND wire_nliii_w_lg_nlO1li1137w(0); + wire_nliii_w1095w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w1094w(0) AND nlO1li; + wire_nliii_w3814w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w3813w(0) AND nlOiOli; + wire_nliii_w3827w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w3779w(0) AND wire_nliii_w_lg_nlOiOli3822w(0); + wire_nliii_w3780w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w3779w(0) AND nlOiOli; + wire_nliii_w2725w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2721w2723w2724w(0) AND n00i1l; + wire_nliii_w2757w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2713w2744w2746w(0) AND wire_nliii_w_lg_n00i1l2733w(0); + wire_nliii_w2747w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2713w2744w2746w(0) AND n00i1l; + wire_nliii_w2716w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2713w2714w2715w(0) AND n00i1l; + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0lll526w527w528w529w530w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lll526w527w528w529w(0) AND n0l0i; + wire_nliii_w2154w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lOOl2150w2151w2152w2153w(0) AND n0lOii; + wire_nliii_w2117w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1Oi2097w2111w2113w2115w(0) AND wire_nliii_w_lg_n0O1iO2116w(0); + wire_nliii_w2101w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1Oi2097w2098w2099w2100w(0) AND n0O10O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0Oli473w487w489w491w493w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oli473w487w489w491w(0) AND wire_nliii_w_lg_n0O0O492w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_n0Oli473w474w475w476w477w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oli473w474w475w476w(0) AND n0O1O; + wire_nliii_w3230w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n11iil3226w3227w3228w3229w(0) AND n11i1i; + wire_nliii_w3193w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n11lii3173w3187w3189w3191w(0) AND wire_nliii_w_lg_n11l1O3192w(0); + wire_nliii_w3177w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n11lii3173w3174w3175w3176w(0) AND n11iOO; + wire_nliii_w3263w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3259w3261w3262w(0) AND n1i1Ol; + wire_nliii_w3295w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3251w3282w3284w(0) AND wire_nliii_w_lg_n1i1Ol3271w(0); + wire_nliii_w3285w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3251w3282w3284w(0) AND n1i1Ol; + wire_nliii_w3254w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3251w3252w3253w(0) AND n1i1Ol; + wire_nliii_w2692w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1Olll2688w2689w2690w2691w(0) AND n1Ol0i; + wire_nliii_w2655w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOli2635w2649w2651w2653w(0) AND wire_nliii_w_lg_n1OO0O2654w(0); + wire_nliii_w2639w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOli2635w2636w2637w2638w(0) AND n1OO1O; + wire_nliii_w2187w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2183w2185w2186w(0) AND ni1l0l; + wire_nliii_w2219w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2175w2206w2208w(0) AND wire_nliii_w_lg_ni1l0l2195w(0); + wire_nliii_w2209w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2175w2206w2208w(0) AND ni1l0l; + wire_nliii_w2178w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2175w2176w2177w(0) AND ni1l0l; + wire_nliii_w1618w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nil01l1614w1615w1616w1617w(0) AND nil1li; + wire_nliii_w1581w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nili1i1561w1575w1577w1579w(0) AND wire_nliii_w_lg_nil0lO1580w(0); + wire_nliii_w1565w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nili1i1561w1562w1563w1564w(0) AND nil0iO; + wire_nliii_w1651w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1647w1649w1650w(0) AND niOOil; + wire_nliii_w1683w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1639w1670w1672w(0) AND wire_nliii_w_lg_niOOil1659w(0); + wire_nliii_w1673w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1639w1670w1672w(0) AND niOOil; + wire_nliii_w1642w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1639w1640w1641w(0) AND niOOil; + wire_nliii_w1081w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlii0l1077w1078w1079w1080w(0) AND nli0Oi; + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w569w571w572w573w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w569w571w572w(0) AND nli1O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w605w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w(0) AND wire_nliii_w_lg_nli1O581w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w595w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w(0) AND nli1O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_w_lg_nliil560w561w562w563w564w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w561w562w563w(0) AND nli1O; + wire_nliii_w1044w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil0i1024w1038w1040w1042w(0) AND wire_nliii_w_lg_nliiOO1043w(0); + wire_nliii_w1028w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil0i1024w1025w1026w1027w(0) AND nliilO; + wire_nliii_w4266w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli01i4246w4260w4262w4264w(0) AND wire_nliii_w_lg_nlli1lO4265w(0); + wire_nliii_w4250w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli01i4246w4247w4248w4249w(0) AND nlli1iO; + wire_nliii_w4303w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli11l4299w4300w4301w4302w(0) AND nll0Oli; + wire_nliii_w4336w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4332w4334w4335w(0) AND nllllil; + wire_nliii_w4368w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4324w4355w4357w(0) AND wire_nliii_w_lg_nllllil4344w(0); + wire_nliii_w4358w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4324w4355w4357w(0) AND nllllil; + wire_nliii_w4327w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4324w4325w4326w(0) AND nllllil; + wire_nliii_w3766w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO000l3762w3763w3764w3765w(0) AND nlO01Oi; + wire_nliii_w3729w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i0i3709w3723w3725w3727w(0) AND wire_nliii_w_lg_nlO00OO3728w(0); + wire_nliii_w3713w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i0i3709w3710w3711w3712w(0) AND nlO00lO; + wire_nliii_w1114w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1110w1112w1113w(0) AND nlO1ll; + wire_nliii_w1146w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1102w1133w1135w(0) AND wire_nliii_w_lg_nlO1ll1122w(0); + wire_nliii_w1136w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1102w1133w1135w(0) AND nlO1ll; + wire_nliii_w1105w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1102w1103w1104w(0) AND nlO1ll; + wire_nliii_w3799w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3795w3797w3798w(0) AND nlOiOll; + wire_nliii_w3831w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3818w3820w(0) AND wire_nliii_w_lg_nlOiOll3807w(0); + wire_nliii_w3821w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3818w3820w(0) AND nlOiOll; + wire_nliii_w3790w(0) <= wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3788w3789w(0) AND nlOiOll; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w2739w(0) <= wire_nliii_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w(0) AND wire_nliii_w_lg_n00i1l2733w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w2705w(0) <= wire_nliii_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w(0) AND n00i1l; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0liO510w511w513w514w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0liO510w511w513w(0) AND n0l0l; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lOlO2134w2135w2137w2138w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0lOlO2134w2135w2137w(0) AND n0lOil; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1ll2081w2082w2084w2085w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0O1ll2081w2082w2084w(0) AND n0O1ii; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oil456w457w459w460w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0Oil456w457w459w(0) AND n0O0i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n11i0O3210w3211w3213w3214w(0) <= wire_nliii_w_lg_w_lg_w_lg_n11i0O3210w3211w3213w(0) AND n11i1l; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n11l0l3157w3158w3160w3161w(0) <= wire_nliii_w_lg_w_lg_w_lg_n11l0l3157w3158w3160w(0) AND n11l1i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w3277w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w(0) AND wire_nliii_w_lg_n1i1Ol3271w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w3243w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w(0) AND n1i1Ol; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OliO2672w2673w2675w2676w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1OliO2672w2673w2675w(0) AND n1Ol0l; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOil2619w2620w2622w2623w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1OOil2619w2620w2622w(0) AND n1OO0i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w2201w(0) <= wire_nliii_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w(0) AND wire_nliii_w_lg_ni1l0l2195w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w2167w(0) <= wire_nliii_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w(0) AND ni1l0l; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nil0Ol1545w1546w1548w1549w(0) <= wire_nliii_w_lg_w_lg_w_lg_nil0Ol1545w1546w1548w(0) AND nil0li; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nil1OO1598w1599w1601w1602w(0) <= wire_nliii_w_lg_w_lg_w_lg_nil1OO1598w1599w1601w(0) AND nil1ll; + wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w1665w(0) <= wire_nliii_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w(0) AND wire_nliii_w_lg_niOOil1659w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w1631w(0) <= wire_nliii_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w(0) AND niOOil; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlii1O1061w1062w1064w1065w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlii1O1061w1062w1064w(0) AND nli0Ol; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w587w(0) <= wire_nliii_w_lg_w_lg_w_lg_nliil550w551w552w(0) AND wire_nliii_w_lg_nli1O581w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil550w551w552w553w(0) <= wire_nliii_w_lg_w_lg_w_lg_nliil550w551w552w(0) AND nli1O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil1l1008w1009w1011w1012w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlil1l1008w1009w1011w(0) AND nliiOi; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nll0OOO4283w4284w4286w4287w(0) <= wire_nliii_w_lg_w_lg_w_lg_nll0OOO4283w4284w4286w(0) AND nll0Oll; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli1Ol4230w4231w4233w4234w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlli1Ol4230w4231w4233w(0) AND nlli1li; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w4350w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w(0) AND wire_nliii_w_lg_nllllil4344w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w4316w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w(0) AND nllllil; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO001O3746w3747w3749w3750w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO001O3746w3747w3749w(0) AND nlO01Ol; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i1l3693w3694w3696w3697w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO0i1l3693w3694w3696w(0) AND nlO00Oi; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w1128w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w(0) AND wire_nliii_w_lg_nlO1ll1122w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w1094w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w(0) AND nlO1ll; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w3813w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w(0) AND wire_nliii_w_lg_nlOiOll3807w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w3779w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w(0) AND nlOiOll; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2721w2723w2724w(0) <= wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2721w2723w(0) AND n00i1O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2713w2744w2746w(0) <= wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2713w2744w(0) AND wire_nliii_w_lg_n00i1O2745w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n00i0O2712w2713w2714w2715w(0) <= wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2713w2714w(0) AND n00i1O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lll526w527w528w529w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0lll526w527w528w(0) AND n0lii; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0lOOl2150w2151w2152w2153w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0lOOl2150w2151w2152w(0) AND n0lOli; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1Oi2097w2111w2113w2115w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0O1Oi2097w2111w2113w(0) AND wire_nliii_w_lg_n0O1li2114w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0O1Oi2097w2098w2099w2100w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0O1Oi2097w2098w2099w(0) AND n0O1iO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oli473w487w489w491w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0Oli473w487w489w(0) AND wire_nliii_w_lg_n0Oii490w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n0Oli473w474w475w476w(0) <= wire_nliii_w_lg_w_lg_w_lg_n0Oli473w474w475w(0) AND n0O0O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n11iil3226w3227w3228w3229w(0) <= wire_nliii_w_lg_w_lg_w_lg_n11iil3226w3227w3228w(0) AND n11i0i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n11lii3173w3187w3189w3191w(0) <= wire_nliii_w_lg_w_lg_w_lg_n11lii3173w3187w3189w(0) AND wire_nliii_w_lg_n11l0i3190w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n11lii3173w3174w3175w3176w(0) <= wire_nliii_w_lg_w_lg_w_lg_n11lii3173w3174w3175w(0) AND n11l1O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3259w3261w3262w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3259w3261w(0) AND n1i1OO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3251w3282w3284w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3251w3282w(0) AND wire_nliii_w_lg_n1i1OO3283w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1i01O3250w3251w3252w3253w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3251w3252w(0) AND n1i1OO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1Olll2688w2689w2690w2691w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1Olll2688w2689w2690w(0) AND n1Olii; + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOli2635w2649w2651w2653w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1OOli2635w2649w2651w(0) AND wire_nliii_w_lg_n1OOii2652w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_n1OOli2635w2636w2637w2638w(0) <= wire_nliii_w_lg_w_lg_w_lg_n1OOli2635w2636w2637w(0) AND n1OO0O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2183w2185w2186w(0) <= wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2183w2185w(0) AND ni1l0O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2175w2206w2208w(0) <= wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2175w2206w(0) AND wire_nliii_w_lg_ni1l0O2207w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_ni1liO2174w2175w2176w2177w(0) <= wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2175w2176w(0) AND ni1l0O; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nil01l1614w1615w1616w1617w(0) <= wire_nliii_w_lg_w_lg_w_lg_nil01l1614w1615w1616w(0) AND nil1Oi; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nili1i1561w1575w1577w1579w(0) <= wire_nliii_w_lg_w_lg_w_lg_nili1i1561w1575w1577w(0) AND wire_nliii_w_lg_nil0Oi1578w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nili1i1561w1562w1563w1564w(0) <= wire_nliii_w_lg_w_lg_w_lg_nili1i1561w1562w1563w(0) AND nil0lO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1647w1649w1650w(0) <= wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1647w1649w(0) AND niOOiO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1639w1670w1672w(0) <= wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1639w1670w(0) AND wire_nliii_w_lg_niOOiO1671w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_niOOlO1638w1639w1640w1641w(0) <= wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1639w1640w(0) AND niOOiO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlii0l1077w1078w1079w1080w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlii0l1077w1078w1079w(0) AND nlii1i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w569w571w572w(0) <= wire_nliii_w_lg_w_lg_w_lg_nliil560w569w571w(0) AND nli0i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w561w592w594w(0) <= wire_nliii_w_lg_w_lg_w_lg_nliil560w561w592w(0) AND wire_nliii_w_lg_nli0i593w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nliil560w561w562w563w(0) <= wire_nliii_w_lg_w_lg_w_lg_nliil560w561w562w(0) AND nli0i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil0i1024w1038w1040w1042w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlil0i1024w1038w1040w(0) AND wire_nliii_w_lg_nlil1i1041w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlil0i1024w1025w1026w1027w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlil0i1024w1025w1026w(0) AND nliiOO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli01i4246w4260w4262w4264w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlli01i4246w4260w4262w(0) AND wire_nliii_w_lg_nlli1Oi4263w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli01i4246w4247w4248w4249w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlli01i4246w4247w4248w(0) AND nlli1lO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlli11l4299w4300w4301w4302w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlli11l4299w4300w4301w(0) AND nll0OOi; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4332w4334w4335w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4332w4334w(0) AND nlllliO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4324w4355w4357w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4324w4355w(0) AND wire_nliii_w_lg_nlllliO4356w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlllllO4323w4324w4325w4326w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4324w4325w(0) AND nlllliO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO000l3762w3763w3764w3765w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO000l3762w3763w3764w(0) AND nlO001i; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i0i3709w3723w3725w3727w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO0i0i3709w3723w3725w(0) AND wire_nliii_w_lg_nlO0i1i3726w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO0i0i3709w3710w3711w3712w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO0i0i3709w3710w3711w(0) AND nlO00OO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1110w1112w1113w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1110w1112w(0) AND nlO1lO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1102w1133w1135w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1102w1133w(0) AND wire_nliii_w_lg_nlO1lO1134w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlO1OO1101w1102w1103w1104w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1102w1103w(0) AND nlO1lO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3795w3797w3798w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3795w3797w(0) AND nlOiOlO; + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3818w3820w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3818w(0) AND wire_nliii_w_lg_nlOiOlO3819w(0); + wire_nliii_w_lg_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3788w3789w(0) <= wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3788w(0) AND nlOiOlO; + wire_nliii_w_lg_w_lg_w_lg_n00i0O2702w2703w2704w(0) <= wire_nliii_w_lg_w_lg_n00i0O2702w2703w(0) AND n00i1O; + wire_nliii_w_lg_w_lg_w_lg_n00i0O2730w2731w2732w(0) <= wire_nliii_w_lg_w_lg_n00i0O2730w2731w(0) AND n00i1O; + wire_nliii_w_lg_w_lg_w_lg_n0liO510w511w513w(0) <= wire_nliii_w_lg_w_lg_n0liO510w511w(0) AND wire_nliii_w_lg_n0l0O512w(0); + wire_nliii_w_lg_w_lg_w_lg_n0lOlO2134w2135w2137w(0) <= wire_nliii_w_lg_w_lg_n0lOlO2134w2135w(0) AND wire_nliii_w_lg_n0lOiO2136w(0); + wire_nliii_w_lg_w_lg_w_lg_n0O1ll2081w2082w2084w(0) <= wire_nliii_w_lg_w_lg_n0O1ll2081w2082w(0) AND wire_nliii_w_lg_n0O1il2083w(0); + wire_nliii_w_lg_w_lg_w_lg_n0Oil456w457w459w(0) <= wire_nliii_w_lg_w_lg_n0Oil456w457w(0) AND wire_nliii_w_lg_n0O0l458w(0); + wire_nliii_w_lg_w_lg_w_lg_n11i0O3210w3211w3213w(0) <= wire_nliii_w_lg_w_lg_n11i0O3210w3211w(0) AND wire_nliii_w_lg_n11i1O3212w(0); + wire_nliii_w_lg_w_lg_w_lg_n11l0l3157w3158w3160w(0) <= wire_nliii_w_lg_w_lg_n11l0l3157w3158w(0) AND wire_nliii_w_lg_n11l1l3159w(0); + wire_nliii_w_lg_w_lg_w_lg_n1i01O3240w3241w3242w(0) <= wire_nliii_w_lg_w_lg_n1i01O3240w3241w(0) AND n1i1OO; + wire_nliii_w_lg_w_lg_w_lg_n1i01O3268w3269w3270w(0) <= wire_nliii_w_lg_w_lg_n1i01O3268w3269w(0) AND n1i1OO; + wire_nliii_w_lg_w_lg_w_lg_n1OliO2672w2673w2675w(0) <= wire_nliii_w_lg_w_lg_n1OliO2672w2673w(0) AND wire_nliii_w_lg_n1Ol0O2674w(0); + wire_nliii_w_lg_w_lg_w_lg_n1OOil2619w2620w2622w(0) <= wire_nliii_w_lg_w_lg_n1OOil2619w2620w(0) AND wire_nliii_w_lg_n1OO0l2621w(0); + wire_nliii_w_lg_w_lg_w_lg_ni1liO2164w2165w2166w(0) <= wire_nliii_w_lg_w_lg_ni1liO2164w2165w(0) AND ni1l0O; + wire_nliii_w_lg_w_lg_w_lg_ni1liO2192w2193w2194w(0) <= wire_nliii_w_lg_w_lg_ni1liO2192w2193w(0) AND ni1l0O; + wire_nliii_w_lg_w_lg_w_lg_nil0Ol1545w1546w1548w(0) <= wire_nliii_w_lg_w_lg_nil0Ol1545w1546w(0) AND wire_nliii_w_lg_nil0ll1547w(0); + wire_nliii_w_lg_w_lg_w_lg_nil1OO1598w1599w1601w(0) <= wire_nliii_w_lg_w_lg_nil1OO1598w1599w(0) AND wire_nliii_w_lg_nil1lO1600w(0); + wire_nliii_w_lg_w_lg_w_lg_niOOlO1628w1629w1630w(0) <= wire_nliii_w_lg_w_lg_niOOlO1628w1629w(0) AND niOOiO; + wire_nliii_w_lg_w_lg_w_lg_niOOlO1656w1657w1658w(0) <= wire_nliii_w_lg_w_lg_niOOlO1656w1657w(0) AND niOOiO; + wire_nliii_w_lg_w_lg_w_lg_nlii1O1061w1062w1064w(0) <= wire_nliii_w_lg_w_lg_nlii1O1061w1062w(0) AND wire_nliii_w_lg_nli0OO1063w(0); + wire_nliii_w_lg_w_lg_w_lg_nliil550w551w552w(0) <= wire_nliii_w_lg_w_lg_nliil550w551w(0) AND nli0i; + wire_nliii_w_lg_w_lg_w_lg_nliil578w579w580w(0) <= wire_nliii_w_lg_w_lg_nliil578w579w(0) AND nli0i; + wire_nliii_w_lg_w_lg_w_lg_nlil1l1008w1009w1011w(0) <= wire_nliii_w_lg_w_lg_nlil1l1008w1009w(0) AND wire_nliii_w_lg_nliiOl1010w(0); + wire_nliii_w_lg_w_lg_w_lg_nll0OOO4283w4284w4286w(0) <= wire_nliii_w_lg_w_lg_nll0OOO4283w4284w(0) AND wire_nliii_w_lg_nll0OlO4285w(0); + wire_nliii_w_lg_w_lg_w_lg_nlli1Ol4230w4231w4233w(0) <= wire_nliii_w_lg_w_lg_nlli1Ol4230w4231w(0) AND wire_nliii_w_lg_nlli1ll4232w(0); + wire_nliii_w_lg_w_lg_w_lg_nlllllO4313w4314w4315w(0) <= wire_nliii_w_lg_w_lg_nlllllO4313w4314w(0) AND nlllliO; + wire_nliii_w_lg_w_lg_w_lg_nlllllO4341w4342w4343w(0) <= wire_nliii_w_lg_w_lg_nlllllO4341w4342w(0) AND nlllliO; + wire_nliii_w_lg_w_lg_w_lg_nlO001O3746w3747w3749w(0) <= wire_nliii_w_lg_w_lg_nlO001O3746w3747w(0) AND wire_nliii_w_lg_nlO01OO3748w(0); + wire_nliii_w_lg_w_lg_w_lg_nlO0i1l3693w3694w3696w(0) <= wire_nliii_w_lg_w_lg_nlO0i1l3693w3694w(0) AND wire_nliii_w_lg_nlO00Ol3695w(0); + wire_nliii_w_lg_w_lg_w_lg_nlO1OO1091w1092w1093w(0) <= wire_nliii_w_lg_w_lg_nlO1OO1091w1092w(0) AND nlO1lO; + wire_nliii_w_lg_w_lg_w_lg_nlO1OO1119w1120w1121w(0) <= wire_nliii_w_lg_w_lg_nlO1OO1119w1120w(0) AND nlO1lO; + wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3776w3777w3778w(0) <= wire_nliii_w_lg_w_lg_nlOiOOO3776w3777w(0) AND nlOiOlO; + wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3804w3805w3806w(0) <= wire_nliii_w_lg_w_lg_nlOiOOO3804w3805w(0) AND nlOiOlO; + wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2721w2723w(0) <= wire_nliii_w_lg_w_lg_n00i0O2712w2721w(0) AND wire_nliii_w_lg_n00i0i2722w(0); + wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2713w2744w(0) <= wire_nliii_w_lg_w_lg_n00i0O2712w2713w(0) AND wire_nliii_w_lg_n00i0i2722w(0); + wire_nliii_w_lg_w_lg_w_lg_n00i0O2712w2713w2714w(0) <= wire_nliii_w_lg_w_lg_n00i0O2712w2713w(0) AND n00i0i; + wire_nliii_w_lg_w_lg_w_lg_n0lll526w527w528w(0) <= wire_nliii_w_lg_w_lg_n0lll526w527w(0) AND n0lil; + wire_nliii_w_lg_w_lg_w_lg_n0lOOl2150w2151w2152w(0) <= wire_nliii_w_lg_w_lg_n0lOOl2150w2151w(0) AND n0lOll; + wire_nliii_w_lg_w_lg_w_lg_n0O1Oi2097w2111w2113w(0) <= wire_nliii_w_lg_w_lg_n0O1Oi2097w2111w(0) AND wire_nliii_w_lg_n0O1ll2112w(0); + wire_nliii_w_lg_w_lg_w_lg_n0O1Oi2097w2098w2099w(0) <= wire_nliii_w_lg_w_lg_n0O1Oi2097w2098w(0) AND n0O1li; + wire_nliii_w_lg_w_lg_w_lg_n0Oli473w487w489w(0) <= wire_nliii_w_lg_w_lg_n0Oli473w487w(0) AND wire_nliii_w_lg_n0Oil488w(0); + wire_nliii_w_lg_w_lg_w_lg_n0Oli473w474w475w(0) <= wire_nliii_w_lg_w_lg_n0Oli473w474w(0) AND n0Oii; + wire_nliii_w_lg_w_lg_w_lg_n11iil3226w3227w3228w(0) <= wire_nliii_w_lg_w_lg_n11iil3226w3227w(0) AND n11i0l; + wire_nliii_w_lg_w_lg_w_lg_n11lii3173w3187w3189w(0) <= wire_nliii_w_lg_w_lg_n11lii3173w3187w(0) AND wire_nliii_w_lg_n11l0l3188w(0); + wire_nliii_w_lg_w_lg_w_lg_n11lii3173w3174w3175w(0) <= wire_nliii_w_lg_w_lg_n11lii3173w3174w(0) AND n11l0i; + wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3259w3261w(0) <= wire_nliii_w_lg_w_lg_n1i01O3250w3259w(0) AND wire_nliii_w_lg_n1i01i3260w(0); + wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3251w3282w(0) <= wire_nliii_w_lg_w_lg_n1i01O3250w3251w(0) AND wire_nliii_w_lg_n1i01i3260w(0); + wire_nliii_w_lg_w_lg_w_lg_n1i01O3250w3251w3252w(0) <= wire_nliii_w_lg_w_lg_n1i01O3250w3251w(0) AND n1i01i; + wire_nliii_w_lg_w_lg_w_lg_n1Olll2688w2689w2690w(0) <= wire_nliii_w_lg_w_lg_n1Olll2688w2689w(0) AND n1Olil; + wire_nliii_w_lg_w_lg_w_lg_n1OOli2635w2649w2651w(0) <= wire_nliii_w_lg_w_lg_n1OOli2635w2649w(0) AND wire_nliii_w_lg_n1OOil2650w(0); + wire_nliii_w_lg_w_lg_w_lg_n1OOli2635w2636w2637w(0) <= wire_nliii_w_lg_w_lg_n1OOli2635w2636w(0) AND n1OOii; + wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2183w2185w(0) <= wire_nliii_w_lg_w_lg_ni1liO2174w2183w(0) AND wire_nliii_w_lg_ni1lii2184w(0); + wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2175w2206w(0) <= wire_nliii_w_lg_w_lg_ni1liO2174w2175w(0) AND wire_nliii_w_lg_ni1lii2184w(0); + wire_nliii_w_lg_w_lg_w_lg_ni1liO2174w2175w2176w(0) <= wire_nliii_w_lg_w_lg_ni1liO2174w2175w(0) AND ni1lii; + wire_nliii_w_lg_w_lg_w_lg_nil01l1614w1615w1616w(0) <= wire_nliii_w_lg_w_lg_nil01l1614w1615w(0) AND nil1Ol; + wire_nliii_w_lg_w_lg_w_lg_nili1i1561w1575w1577w(0) <= wire_nliii_w_lg_w_lg_nili1i1561w1575w(0) AND wire_nliii_w_lg_nil0Ol1576w(0); + wire_nliii_w_lg_w_lg_w_lg_nili1i1561w1562w1563w(0) <= wire_nliii_w_lg_w_lg_nili1i1561w1562w(0) AND nil0Oi; + wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1647w1649w(0) <= wire_nliii_w_lg_w_lg_niOOlO1638w1647w(0) AND wire_nliii_w_lg_niOOli1648w(0); + wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1639w1670w(0) <= wire_nliii_w_lg_w_lg_niOOlO1638w1639w(0) AND wire_nliii_w_lg_niOOli1648w(0); + wire_nliii_w_lg_w_lg_w_lg_niOOlO1638w1639w1640w(0) <= wire_nliii_w_lg_w_lg_niOOlO1638w1639w(0) AND niOOli; + wire_nliii_w_lg_w_lg_w_lg_nlii0l1077w1078w1079w(0) <= wire_nliii_w_lg_w_lg_nlii0l1077w1078w(0) AND nlii1l; + wire_nliii_w_lg_w_lg_w_lg_nliil560w569w571w(0) <= wire_nliii_w_lg_w_lg_nliil560w569w(0) AND wire_nliii_w_lg_nli0l570w(0); + wire_nliii_w_lg_w_lg_w_lg_nliil560w561w592w(0) <= wire_nliii_w_lg_w_lg_nliil560w561w(0) AND wire_nliii_w_lg_nli0l570w(0); + wire_nliii_w_lg_w_lg_w_lg_nliil560w561w562w(0) <= wire_nliii_w_lg_w_lg_nliil560w561w(0) AND nli0l; + wire_nliii_w_lg_w_lg_w_lg_nlil0i1024w1038w1040w(0) <= wire_nliii_w_lg_w_lg_nlil0i1024w1038w(0) AND wire_nliii_w_lg_nlil1l1039w(0); + wire_nliii_w_lg_w_lg_w_lg_nlil0i1024w1025w1026w(0) <= wire_nliii_w_lg_w_lg_nlil0i1024w1025w(0) AND nlil1i; + wire_nliii_w_lg_w_lg_w_lg_nlli01i4246w4260w4262w(0) <= wire_nliii_w_lg_w_lg_nlli01i4246w4260w(0) AND wire_nliii_w_lg_nlli1Ol4261w(0); + wire_nliii_w_lg_w_lg_w_lg_nlli01i4246w4247w4248w(0) <= wire_nliii_w_lg_w_lg_nlli01i4246w4247w(0) AND nlli1Oi; + wire_nliii_w_lg_w_lg_w_lg_nlli11l4299w4300w4301w(0) <= wire_nliii_w_lg_w_lg_nlli11l4299w4300w(0) AND nll0OOl; + wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4332w4334w(0) <= wire_nliii_w_lg_w_lg_nlllllO4323w4332w(0) AND wire_nliii_w_lg_nllllli4333w(0); + wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4324w4355w(0) <= wire_nliii_w_lg_w_lg_nlllllO4323w4324w(0) AND wire_nliii_w_lg_nllllli4333w(0); + wire_nliii_w_lg_w_lg_w_lg_nlllllO4323w4324w4325w(0) <= wire_nliii_w_lg_w_lg_nlllllO4323w4324w(0) AND nllllli; + wire_nliii_w_lg_w_lg_w_lg_nlO000l3762w3763w3764w(0) <= wire_nliii_w_lg_w_lg_nlO000l3762w3763w(0) AND nlO001l; + wire_nliii_w_lg_w_lg_w_lg_nlO0i0i3709w3723w3725w(0) <= wire_nliii_w_lg_w_lg_nlO0i0i3709w3723w(0) AND wire_nliii_w_lg_nlO0i1l3724w(0); + wire_nliii_w_lg_w_lg_w_lg_nlO0i0i3709w3710w3711w(0) <= wire_nliii_w_lg_w_lg_nlO0i0i3709w3710w(0) AND nlO0i1i; + wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1110w1112w(0) <= wire_nliii_w_lg_w_lg_nlO1OO1101w1110w(0) AND wire_nliii_w_lg_nlO1Oi1111w(0); + wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1102w1133w(0) <= wire_nliii_w_lg_w_lg_nlO1OO1101w1102w(0) AND wire_nliii_w_lg_nlO1Oi1111w(0); + wire_nliii_w_lg_w_lg_w_lg_nlO1OO1101w1102w1103w(0) <= wire_nliii_w_lg_w_lg_nlO1OO1101w1102w(0) AND nlO1Oi; + wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3795w3797w(0) <= wire_nliii_w_lg_w_lg_nlOiOOO3786w3795w(0) AND wire_nliii_w_lg_nlOiOOi3796w(0); + wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3818w(0) <= wire_nliii_w_lg_w_lg_nlOiOOO3786w3787w(0) AND wire_nliii_w_lg_nlOiOOi3796w(0); + wire_nliii_w_lg_w_lg_w_lg_nlOiOOO3786w3787w3788w(0) <= wire_nliii_w_lg_w_lg_nlOiOOO3786w3787w(0) AND nlOiOOi; + wire_nliii_w_lg_w_lg_n00i0O2702w2703w(0) <= wire_nliii_w_lg_n00i0O2702w(0) AND n00i0i; + wire_nliii_w_lg_w_lg_n00i0O2730w2731w(0) <= wire_nliii_w_lg_n00i0O2730w(0) AND n00i0i; + wire_nliii_w_lg_w_lg_n0iiOl2055w2056w(0) <= wire_nliii_w_lg_n0iiOl2055w(0) AND n0iiOi; + wire_nliii_w_lg_w_lg_n0liO510w511w(0) <= wire_nliii_w_lg_n0liO510w(0) AND n0lii; + wire_nliii_w_lg_w_lg_n0lOlO2134w2135w(0) <= wire_nliii_w_lg_n0lOlO2134w(0) AND n0lOli; + wire_nliii_w_lg_w_lg_n0O1ll2081w2082w(0) <= wire_nliii_w_lg_n0O1ll2081w(0) AND n0O1iO; + wire_nliii_w_lg_w_lg_n0Oil456w457w(0) <= wire_nliii_w_lg_n0Oil456w(0) AND n0O0O; + wire_nliii_w_lg_w_lg_n10ll430w431w(0) <= wire_nliii_w_lg_n10ll430w(0) AND n10li; + wire_nliii_w_lg_w_lg_n11i0O3210w3211w(0) <= wire_nliii_w_lg_n11i0O3210w(0) AND n11i0i; + wire_nliii_w_lg_w_lg_n11l0l3157w3158w(0) <= wire_nliii_w_lg_n11l0l3157w(0) AND n11l1O; + wire_nliii_w_lg_w_lg_n1i01O3240w3241w(0) <= wire_nliii_w_lg_n1i01O3240w(0) AND n1i01i; + wire_nliii_w_lg_w_lg_n1i01O3268w3269w(0) <= wire_nliii_w_lg_n1i01O3268w(0) AND n1i01i; + wire_nliii_w_lg_w_lg_n1l0ll2593w2594w(0) <= wire_nliii_w_lg_n1l0ll2593w(0) AND n1l0li; + wire_nliii_w_lg_w_lg_n1OliO2672w2673w(0) <= wire_nliii_w_lg_n1OliO2672w(0) AND n1Olii; + wire_nliii_w_lg_w_lg_n1OOil2619w2620w(0) <= wire_nliii_w_lg_n1OOil2619w(0) AND n1OO0O; + wire_nliii_w_lg_w_lg_ni0O1l1519w1520w(0) <= wire_nliii_w_lg_ni0O1l1519w(0) AND ni0O1i; + wire_nliii_w_lg_w_lg_ni1liO2164w2165w(0) <= wire_nliii_w_lg_ni1liO2164w(0) AND ni1lii; + wire_nliii_w_lg_w_lg_ni1liO2192w2193w(0) <= wire_nliii_w_lg_ni1liO2192w(0) AND ni1lii; + wire_nliii_w_lg_w_lg_nil0Ol1545w1546w(0) <= wire_nliii_w_lg_nil0Ol1545w(0) AND nil0lO; + wire_nliii_w_lg_w_lg_nil1OO1598w1599w(0) <= wire_nliii_w_lg_nil1OO1598w(0) AND nil1Oi; + wire_nliii_w_lg_w_lg_niOOlO1628w1629w(0) <= wire_nliii_w_lg_niOOlO1628w(0) AND niOOli; + wire_nliii_w_lg_w_lg_niOOlO1656w1657w(0) <= wire_nliii_w_lg_niOOlO1656w(0) AND niOOli; + wire_nliii_w_lg_w_lg_nl010l982w983w(0) <= wire_nliii_w_lg_nl010l982w(0) AND nl010i; + wire_nliii_w_lg_w_lg_nlii1O1061w1062w(0) <= wire_nliii_w_lg_nlii1O1061w(0) AND nlii1i; + wire_nliii_w_lg_w_lg_nliil550w551w(0) <= wire_nliii_w_lg_nliil550w(0) AND nli0l; + wire_nliii_w_lg_w_lg_nliil578w579w(0) <= wire_nliii_w_lg_nliil578w(0) AND nli0l; + wire_nliii_w_lg_w_lg_nlil1l1008w1009w(0) <= wire_nliii_w_lg_nlil1l1008w(0) AND nliiOO; + wire_nliii_w_lg_w_lg_nll0OOO4283w4284w(0) <= wire_nliii_w_lg_nll0OOO4283w(0) AND nll0OOi; + wire_nliii_w_lg_w_lg_nll1l1l4204w4205w(0) <= wire_nliii_w_lg_nll1l1l4204w(0) AND nll1l1i; + wire_nliii_w_lg_w_lg_nlli1Ol4230w4231w(0) <= wire_nliii_w_lg_nlli1Ol4230w(0) AND nlli1lO; + wire_nliii_w_lg_w_lg_nlllllO4313w4314w(0) <= wire_nliii_w_lg_nlllllO4313w(0) AND nllllli; + wire_nliii_w_lg_w_lg_nlllllO4341w4342w(0) <= wire_nliii_w_lg_nlllllO4341w(0) AND nllllli; + wire_nliii_w_lg_w_lg_nllOO0l3667w3668w(0) <= wire_nliii_w_lg_nllOO0l3667w(0) AND nllOO0i; + wire_nliii_w_lg_w_lg_nlO001O3746w3747w(0) <= wire_nliii_w_lg_nlO001O3746w(0) AND nlO001i; + wire_nliii_w_lg_w_lg_nlO0i1l3693w3694w(0) <= wire_nliii_w_lg_nlO0i1l3693w(0) AND nlO00OO; + wire_nliii_w_lg_w_lg_nlO1OO1091w1092w(0) <= wire_nliii_w_lg_nlO1OO1091w(0) AND nlO1Oi; + wire_nliii_w_lg_w_lg_nlO1OO1119w1120w(0) <= wire_nliii_w_lg_nlO1OO1119w(0) AND nlO1Oi; + wire_nliii_w_lg_w_lg_nlOiOOO3776w3777w(0) <= wire_nliii_w_lg_nlOiOOO3776w(0) AND nlOiOOi; + wire_nliii_w_lg_w_lg_nlOiOOO3804w3805w(0) <= wire_nliii_w_lg_nlOiOOO3804w(0) AND nlOiOOi; + wire_nliii_w_lg_w_lg_nlOO1il3131w3132w(0) <= wire_nliii_w_lg_nlOO1il3131w(0) AND nlOO1ii; + wire_nliii_w_lg_w_lg_n00i0O2712w2721w(0) <= wire_nliii_w_lg_n00i0O2712w(0) AND wire_nliii_w_lg_n00i0l2701w(0); + wire_nliii_w_lg_w_lg_n00i0O2712w2713w(0) <= wire_nliii_w_lg_n00i0O2712w(0) AND n00i0l; + wire_nliii_w_lg_w_lg_n0lll526w527w(0) <= wire_nliii_w_lg_n0lll526w(0) AND n0liO; + wire_nliii_w_lg_w_lg_n0lOOl2150w2151w(0) <= wire_nliii_w_lg_n0lOOl2150w(0) AND n0lOlO; + wire_nliii_w_lg_w_lg_n0O1Oi2097w2111w(0) <= wire_nliii_w_lg_n0O1Oi2097w(0) AND wire_nliii_w_lg_n0O1lO2110w(0); + wire_nliii_w_lg_w_lg_n0O1Oi2097w2098w(0) <= wire_nliii_w_lg_n0O1Oi2097w(0) AND n0O1ll; + wire_nliii_w_lg_w_lg_n0Oli473w487w(0) <= wire_nliii_w_lg_n0Oli473w(0) AND wire_nliii_w_lg_n0OiO486w(0); + wire_nliii_w_lg_w_lg_n0Oli473w474w(0) <= wire_nliii_w_lg_n0Oli473w(0) AND n0Oil; + wire_nliii_w_lg_w_lg_n11iil3226w3227w(0) <= wire_nliii_w_lg_n11iil3226w(0) AND n11i0O; + wire_nliii_w_lg_w_lg_n11lii3173w3187w(0) <= wire_nliii_w_lg_n11lii3173w(0) AND wire_nliii_w_lg_n11l0O3186w(0); + wire_nliii_w_lg_w_lg_n11lii3173w3174w(0) <= wire_nliii_w_lg_n11lii3173w(0) AND n11l0l; + wire_nliii_w_lg_w_lg_n1i01O3250w3259w(0) <= wire_nliii_w_lg_n1i01O3250w(0) AND wire_nliii_w_lg_n1i01l3239w(0); + wire_nliii_w_lg_w_lg_n1i01O3250w3251w(0) <= wire_nliii_w_lg_n1i01O3250w(0) AND n1i01l; + wire_nliii_w_lg_w_lg_n1Olll2688w2689w(0) <= wire_nliii_w_lg_n1Olll2688w(0) AND n1OliO; + wire_nliii_w_lg_w_lg_n1OOli2635w2649w(0) <= wire_nliii_w_lg_n1OOli2635w(0) AND wire_nliii_w_lg_n1OOiO2648w(0); + wire_nliii_w_lg_w_lg_n1OOli2635w2636w(0) <= wire_nliii_w_lg_n1OOli2635w(0) AND n1OOil; + wire_nliii_w_lg_w_lg_ni1liO2174w2183w(0) <= wire_nliii_w_lg_ni1liO2174w(0) AND wire_nliii_w_lg_ni1lil2163w(0); + wire_nliii_w_lg_w_lg_ni1liO2174w2175w(0) <= wire_nliii_w_lg_ni1liO2174w(0) AND ni1lil; + wire_nliii_w_lg_w_lg_nil01l1614w1615w(0) <= wire_nliii_w_lg_nil01l1614w(0) AND nil1OO; + wire_nliii_w_lg_w_lg_nili1i1561w1575w(0) <= wire_nliii_w_lg_nili1i1561w(0) AND wire_nliii_w_lg_nil0OO1574w(0); + wire_nliii_w_lg_w_lg_nili1i1561w1562w(0) <= wire_nliii_w_lg_nili1i1561w(0) AND nil0Ol; + wire_nliii_w_lg_w_lg_niOOlO1638w1647w(0) <= wire_nliii_w_lg_niOOlO1638w(0) AND wire_nliii_w_lg_niOOll1627w(0); + wire_nliii_w_lg_w_lg_niOOlO1638w1639w(0) <= wire_nliii_w_lg_niOOlO1638w(0) AND niOOll; + wire_nliii_w_lg_w_lg_nl0Ol282w283w(0) <= wire_nliii_w_lg_nl0Ol282w(0) AND nl0Oi; + wire_nliii_w_lg_w_lg_nlii0l1077w1078w(0) <= wire_nliii_w_lg_nlii0l1077w(0) AND nlii1O; + wire_nliii_w_lg_w_lg_nliil560w569w(0) <= wire_nliii_w_lg_nliil560w(0) AND wire_nliii_w_lg_nli0O549w(0); + wire_nliii_w_lg_w_lg_nliil560w561w(0) <= wire_nliii_w_lg_nliil560w(0) AND nli0O; + wire_nliii_w_lg_w_lg_nlil0i1024w1038w(0) <= wire_nliii_w_lg_nlil0i1024w(0) AND wire_nliii_w_lg_nlil1O1037w(0); + wire_nliii_w_lg_w_lg_nlil0i1024w1025w(0) <= wire_nliii_w_lg_nlil0i1024w(0) AND nlil1l; + wire_nliii_w_lg_w_lg_nlli01i4246w4260w(0) <= wire_nliii_w_lg_nlli01i4246w(0) AND wire_nliii_w_lg_nlli1OO4259w(0); + wire_nliii_w_lg_w_lg_nlli01i4246w4247w(0) <= wire_nliii_w_lg_nlli01i4246w(0) AND nlli1Ol; + wire_nliii_w_lg_w_lg_nlli11l4299w4300w(0) <= wire_nliii_w_lg_nlli11l4299w(0) AND nll0OOO; + wire_nliii_w_lg_w_lg_nlllllO4323w4332w(0) <= wire_nliii_w_lg_nlllllO4323w(0) AND wire_nliii_w_lg_nllllll4312w(0); + wire_nliii_w_lg_w_lg_nlllllO4323w4324w(0) <= wire_nliii_w_lg_nlllllO4323w(0) AND nllllll; + wire_nliii_w_lg_w_lg_nlO000l3762w3763w(0) <= wire_nliii_w_lg_nlO000l3762w(0) AND nlO001O; + wire_nliii_w_lg_w_lg_nlO0i0i3709w3723w(0) <= wire_nliii_w_lg_nlO0i0i3709w(0) AND wire_nliii_w_lg_nlO0i1O3722w(0); + wire_nliii_w_lg_w_lg_nlO0i0i3709w3710w(0) <= wire_nliii_w_lg_nlO0i0i3709w(0) AND nlO0i1l; + wire_nliii_w_lg_w_lg_nlO1OO1101w1110w(0) <= wire_nliii_w_lg_nlO1OO1101w(0) AND wire_nliii_w_lg_nlO1Ol1090w(0); + wire_nliii_w_lg_w_lg_nlO1OO1101w1102w(0) <= wire_nliii_w_lg_nlO1OO1101w(0) AND nlO1Ol; + wire_nliii_w_lg_w_lg_nlOiOOO3786w3795w(0) <= wire_nliii_w_lg_nlOiOOO3786w(0) AND wire_nliii_w_lg_nlOiOOl3775w(0); + wire_nliii_w_lg_w_lg_nlOiOOO3786w3787w(0) <= wire_nliii_w_lg_nlOiOOO3786w(0) AND nlOiOOl; + wire_nliii_w_lg_n00i0O2702w(0) <= n00i0O AND wire_nliii_w_lg_n00i0l2701w(0); + wire_nliii_w_lg_n00i0O2730w(0) <= n00i0O AND n00i0l; + wire_nliii_w_lg_n0iiOl2055w(0) <= n0iiOl AND wire_nliii_w_lg_n0iilO2054w(0); + wire_nliii_w_lg_n0liO510w(0) <= n0liO AND n0lil; + wire_nliii_w_lg_n0lOlO2134w(0) <= n0lOlO AND n0lOll; + wire_nliii_w_lg_n0O1ll2081w(0) <= n0O1ll AND n0O1li; + wire_nliii_w_lg_n0Oil456w(0) <= n0Oil AND n0Oii; + wire_nliii_w_lg_n10ll430w(0) <= n10ll AND wire_nliii_w_lg_n10iO429w(0); + wire_nliii_w_lg_n11i0O3210w(0) <= n11i0O AND n11i0l; + wire_nliii_w_lg_n11l0l3157w(0) <= n11l0l AND n11l0i; + wire_nliii_w_lg_n1i01O3240w(0) <= n1i01O AND wire_nliii_w_lg_n1i01l3239w(0); + wire_nliii_w_lg_n1i01O3268w(0) <= n1i01O AND n1i01l; + wire_nliii_w_lg_n1l0ll2593w(0) <= n1l0ll AND wire_nliii_w_lg_n1l0iO2592w(0); + wire_nliii_w_lg_n1OliO2672w(0) <= n1OliO AND n1Olil; + wire_nliii_w_lg_n1OOil2619w(0) <= n1OOil AND n1OOii; + wire_nliii_w_lg_ni0O1l1519w(0) <= ni0O1l AND wire_nliii_w_lg_ni0lOO1518w(0); + wire_nliii_w_lg_ni1liO2164w(0) <= ni1liO AND wire_nliii_w_lg_ni1lil2163w(0); + wire_nliii_w_lg_ni1liO2192w(0) <= ni1liO AND ni1lil; + wire_nliii_w_lg_nil0Ol1545w(0) <= nil0Ol AND nil0Oi; + wire_nliii_w_lg_nil1OO1598w(0) <= nil1OO AND nil1Ol; + wire_nliii_w_lg_niOOlO1628w(0) <= niOOlO AND wire_nliii_w_lg_niOOll1627w(0); + wire_nliii_w_lg_niOOlO1656w(0) <= niOOlO AND niOOll; + wire_nliii_w_lg_nl010l982w(0) <= nl010l AND wire_nliii_w_lg_nl011O981w(0); + wire_nliii_w_lg_nl0Oi294w(0) <= nl0Oi AND wire_w_lg_nlilO1l293w(0); + wire_nliii_w_lg_nlii1O1061w(0) <= nlii1O AND nlii1l; + wire_nliii_w_lg_nliil550w(0) <= nliil AND wire_nliii_w_lg_nli0O549w(0); + wire_nliii_w_lg_nliil578w(0) <= nliil AND nli0O; + wire_nliii_w_lg_nlil1l1008w(0) <= nlil1l AND nlil1i; + wire_nliii_w_lg_nll0OOO4283w(0) <= nll0OOO AND nll0OOl; + wire_nliii_w_lg_nll1l1l4204w(0) <= nll1l1l AND wire_nliii_w_lg_nll1iOO4203w(0); + wire_nliii_w_lg_nlli1Ol4230w(0) <= nlli1Ol AND nlli1Oi; + wire_nliii_w_lg_nlllllO4313w(0) <= nlllllO AND wire_nliii_w_lg_nllllll4312w(0); + wire_nliii_w_lg_nlllllO4341w(0) <= nlllllO AND nllllll; + wire_nliii_w_lg_nllOO0l3667w(0) <= nllOO0l AND wire_nliii_w_lg_nllOO1O3666w(0); + wire_nliii_w_lg_nlO001O3746w(0) <= nlO001O AND nlO001l; + wire_nliii_w_lg_nlO0i1l3693w(0) <= nlO0i1l AND nlO0i1i; + wire_nliii_w_lg_nlO1OO1091w(0) <= nlO1OO AND wire_nliii_w_lg_nlO1Ol1090w(0); + wire_nliii_w_lg_nlO1OO1119w(0) <= nlO1OO AND nlO1Ol; + wire_nliii_w_lg_nlOiOOO3776w(0) <= nlOiOOO AND wire_nliii_w_lg_nlOiOOl3775w(0); + wire_nliii_w_lg_nlOiOOO3804w(0) <= nlOiOOO AND nlOiOOl; + wire_nliii_w_lg_nlOO1il3131w(0) <= nlOO1il AND wire_nliii_w_lg_nlOO10O3130w(0); + wire_nliii_w_lg_n000ll2557w(0) <= NOT n000ll; + wire_nliii_w_lg_n000Oi2453w(0) <= NOT n000Oi; + wire_nliii_w_lg_n000Ol2709w(0) <= NOT n000Ol; + wire_nliii_w_lg_n000OO2707w(0) <= NOT n000OO; + wire_nliii_w_lg_n00i0i2722w(0) <= NOT n00i0i; + wire_nliii_w_lg_n00i0l2701w(0) <= NOT n00i0l; + wire_nliii_w_lg_n00i0O2712w(0) <= NOT n00i0O; + wire_nliii_w_lg_n00i1i2748w(0) <= NOT n00i1i; + wire_nliii_w_lg_n00i1l2733w(0) <= NOT n00i1l; + wire_nliii_w_lg_n00i1O2745w(0) <= NOT n00i1O; + wire_nliii_w_lg_n00ili2237w(0) <= NOT n00ili; + wire_nliii_w_lg_n0iilO2054w(0) <= NOT n0iilO; + wire_nliii_w_lg_n0iiOi2059w(0) <= NOT n0iiOi; + wire_nliii_w_lg_n0iO0l2011w(0) <= NOT n0iO0l; + wire_nliii_w_lg_n0l0O512w(0) <= NOT n0l0O; + wire_nliii_w_lg_n0l1O515w(0) <= NOT n0l1O; + wire_nliii_w_lg_n0lll526w(0) <= NOT n0lll; + wire_nliii_w_lg_n0lO0O2139w(0) <= NOT n0lO0O; + wire_nliii_w_lg_n0lOiO2136w(0) <= NOT n0lOiO; + wire_nliii_w_lg_n0lOOl2150w(0) <= NOT n0lOOl; + wire_nliii_w_lg_n0O0i495w(0) <= NOT n0O0i; + wire_nliii_w_lg_n0O0l458w(0) <= NOT n0O0l; + wire_nliii_w_lg_n0O0O492w(0) <= NOT n0O0O; + wire_nliii_w_lg_n0O10l2086w(0) <= NOT n0O10l; + wire_nliii_w_lg_n0O10O2121w(0) <= NOT n0O10O; + wire_nliii_w_lg_n0O1ii2119w(0) <= NOT n0O1ii; + wire_nliii_w_lg_n0O1il2083w(0) <= NOT n0O1il; + wire_nliii_w_lg_n0O1iO2116w(0) <= NOT n0O1iO; + wire_nliii_w_lg_n0O1l461w(0) <= NOT n0O1l; + wire_nliii_w_lg_n0O1li2114w(0) <= NOT n0O1li; + wire_nliii_w_lg_n0O1ll2112w(0) <= NOT n0O1ll; + wire_nliii_w_lg_n0O1lO2110w(0) <= NOT n0O1lO; + wire_nliii_w_lg_n0O1O497w(0) <= NOT n0O1O; + wire_nliii_w_lg_n0O1Oi2097w(0) <= NOT n0O1Oi; + wire_nliii_w_lg_n0Oii490w(0) <= NOT n0Oii; + wire_nliii_w_lg_n0Oil488w(0) <= NOT n0Oil; + wire_nliii_w_lg_n0OiO486w(0) <= NOT n0OiO; + wire_nliii_w_lg_n0Oli473w(0) <= NOT n0Oli; + wire_nliii_w_lg_n10iO429w(0) <= NOT n10iO; + wire_nliii_w_lg_n10li434w(0) <= NOT n10li; + wire_nliii_w_lg_n110OO3215w(0) <= NOT n110OO; + wire_nliii_w_lg_n11i1O3212w(0) <= NOT n11i1O; + wire_nliii_w_lg_n11iil3226w(0) <= NOT n11iil; + wire_nliii_w_lg_n11iOl3162w(0) <= NOT n11iOl; + wire_nliii_w_lg_n11iOO3197w(0) <= NOT n11iOO; + wire_nliii_w_lg_n11l0i3190w(0) <= NOT n11l0i; + wire_nliii_w_lg_n11l0l3188w(0) <= NOT n11l0l; + wire_nliii_w_lg_n11l0O3186w(0) <= NOT n11l0O; + wire_nliii_w_lg_n11l1i3195w(0) <= NOT n11l1i; + wire_nliii_w_lg_n11l1l3159w(0) <= NOT n11l1l; + wire_nliii_w_lg_n11l1O3192w(0) <= NOT n11l1O; + wire_nliii_w_lg_n11lii3173w(0) <= NOT n11lii; + wire_nliii_w_lg_n1i01i3260w(0) <= NOT n1i01i; + wire_nliii_w_lg_n1i01l3239w(0) <= NOT n1i01l; + wire_nliii_w_lg_n1i01O3250w(0) <= NOT n1i01O; + wire_nliii_w_lg_n1i0ii2775w(0) <= NOT n1i0ii; + wire_nliii_w_lg_n1i1il3095w(0) <= NOT n1i1il; + wire_nliii_w_lg_n1i1li2991w(0) <= NOT n1i1li; + wire_nliii_w_lg_n1i1ll3247w(0) <= NOT n1i1ll; + wire_nliii_w_lg_n1i1lO3245w(0) <= NOT n1i1lO; + wire_nliii_w_lg_n1i1Oi3286w(0) <= NOT n1i1Oi; + wire_nliii_w_lg_n1i1Ol3271w(0) <= NOT n1i1Ol; + wire_nliii_w_lg_n1i1OO3283w(0) <= NOT n1i1OO; + wire_nliii_w_lg_n1l0iO2592w(0) <= NOT n1l0iO; + wire_nliii_w_lg_n1l0li2597w(0) <= NOT n1l0li; + wire_nliii_w_lg_n1l1l386w(0) <= NOT n1l1l; + wire_nliii_w_lg_n1ll1l2549w(0) <= NOT n1ll1l; + wire_nliii_w_lg_n1Ol0O2674w(0) <= NOT n1Ol0O; + wire_nliii_w_lg_n1Ol1O2677w(0) <= NOT n1Ol1O; + wire_nliii_w_lg_n1Olll2688w(0) <= NOT n1Olll; + wire_nliii_w_lg_n1OO0i2657w(0) <= NOT n1OO0i; + wire_nliii_w_lg_n1OO0l2621w(0) <= NOT n1OO0l; + wire_nliii_w_lg_n1OO0O2654w(0) <= NOT n1OO0O; + wire_nliii_w_lg_n1OO1l2624w(0) <= NOT n1OO1l; + wire_nliii_w_lg_n1OO1O2659w(0) <= NOT n1OO1O; + wire_nliii_w_lg_n1OOii2652w(0) <= NOT n1OOii; + wire_nliii_w_lg_n1OOil2650w(0) <= NOT n1OOil; + wire_nliii_w_lg_n1OOiO2648w(0) <= NOT n1OOiO; + wire_nliii_w_lg_n1OOli2635w(0) <= NOT n1OOli; + wire_nliii_w_lg_ni0lOO1518w(0) <= NOT ni0lOO; + wire_nliii_w_lg_ni0O1i1523w(0) <= NOT ni0O1i; + wire_nliii_w_lg_ni1iOl2019w(0) <= NOT ni1iOl; + wire_nliii_w_lg_ni1l0i2210w(0) <= NOT ni1l0i; + wire_nliii_w_lg_ni1l0l2195w(0) <= NOT ni1l0l; + wire_nliii_w_lg_ni1l0O2207w(0) <= NOT ni1l0O; + wire_nliii_w_lg_ni1l1i1917w(0) <= NOT ni1l1i; + wire_nliii_w_lg_ni1l1l2171w(0) <= NOT ni1l1l; + wire_nliii_w_lg_ni1l1O2169w(0) <= NOT ni1l1O; + wire_nliii_w_lg_ni1lii2184w(0) <= NOT ni1lii; + wire_nliii_w_lg_ni1lil2163w(0) <= NOT ni1lil; + wire_nliii_w_lg_ni1liO2174w(0) <= NOT ni1liO; + wire_nliii_w_lg_ni1lOi1701w(0) <= NOT ni1lOi; + wire_nliii_w_lg_nii1il1475w(0) <= NOT nii1il; + wire_nliii_w_lg_nil01l1614w(0) <= NOT nil01l; + wire_nliii_w_lg_nil0il1550w(0) <= NOT nil0il; + wire_nliii_w_lg_nil0iO1585w(0) <= NOT nil0iO; + wire_nliii_w_lg_nil0li1583w(0) <= NOT nil0li; + wire_nliii_w_lg_nil0ll1547w(0) <= NOT nil0ll; + wire_nliii_w_lg_nil0lO1580w(0) <= NOT nil0lO; + wire_nliii_w_lg_nil0Oi1578w(0) <= NOT nil0Oi; + wire_nliii_w_lg_nil0Ol1576w(0) <= NOT nil0Ol; + wire_nliii_w_lg_nil0OO1574w(0) <= NOT nil0OO; + wire_nliii_w_lg_nil1iO1603w(0) <= NOT nil1iO; + wire_nliii_w_lg_nil1lO1600w(0) <= NOT nil1lO; + wire_nliii_w_lg_nili1i1561w(0) <= NOT nili1i; + wire_nliii_w_lg_niOO0i1380w(0) <= NOT niOO0i; + wire_nliii_w_lg_niOO0l1635w(0) <= NOT niOO0l; + wire_nliii_w_lg_niOO0O1633w(0) <= NOT niOO0O; + wire_nliii_w_lg_niOO1l1483w(0) <= NOT niOO1l; + wire_nliii_w_lg_niOOii1674w(0) <= NOT niOOii; + wire_nliii_w_lg_niOOil1659w(0) <= NOT niOOil; + wire_nliii_w_lg_niOOiO1671w(0) <= NOT niOOiO; + wire_nliii_w_lg_niOOli1648w(0) <= NOT niOOli; + wire_nliii_w_lg_niOOll1627w(0) <= NOT niOOll; + wire_nliii_w_lg_niOOlO1638w(0) <= NOT niOOlO; + wire_nliii_w_lg_nl00ll938w(0) <= NOT nl00ll; + wire_nliii_w_lg_nl010i986w(0) <= NOT nl010i; + wire_nliii_w_lg_nl011O981w(0) <= NOT nl011O; + wire_nliii_w_lg_nl0lO394w(0) <= NOT nl0lO; + wire_nliii_w_lg_nl0Ol282w(0) <= NOT nl0Ol; + wire_nliii_w_lg_nl0OO557w(0) <= NOT nl0OO; + wire_nliii_w_lg_nl111i1164w(0) <= NOT nl111i; + wire_nliii_w_lg_nli0i593w(0) <= NOT nli0i; + wire_nliii_w_lg_nli0l570w(0) <= NOT nli0l; + wire_nliii_w_lg_nli0lO1066w(0) <= NOT nli0lO; + wire_nliii_w_lg_nli0O549w(0) <= NOT nli0O; + wire_nliii_w_lg_nli0OO1063w(0) <= NOT nli0OO; + wire_nliii_w_lg_nli1i555w(0) <= NOT nli1i; + wire_nliii_w_lg_nli1l596w(0) <= NOT nli1l; + wire_nliii_w_lg_nli1O581w(0) <= NOT nli1O; + wire_nliii_w_lg_nlii0l1077w(0) <= NOT nlii0l; + wire_nliii_w_lg_nliil560w(0) <= NOT nliil; + wire_nliii_w_lg_nliill1013w(0) <= NOT nliill; + wire_nliii_w_lg_nliilO1048w(0) <= NOT nliilO; + wire_nliii_w_lg_nliiOi1046w(0) <= NOT nliiOi; + wire_nliii_w_lg_nliiOl1010w(0) <= NOT nliiOl; + wire_nliii_w_lg_nliiOO1043w(0) <= NOT nliiOO; + wire_nliii_w_lg_nlil0i1024w(0) <= NOT nlil0i; + wire_nliii_w_lg_nlil1i1041w(0) <= NOT nlil1i; + wire_nliii_w_lg_nlil1l1039w(0) <= NOT nlil1l; + wire_nliii_w_lg_nlil1O1037w(0) <= NOT nlil1O; + wire_nliii_w_lg_nliOiOi4386w(0) <= NOT nliOiOi; + wire_nliii_w_lg_nll0OiO4288w(0) <= NOT nll0OiO; + wire_nliii_w_lg_nll0OlO4285w(0) <= NOT nll0OlO; + wire_nliii_w_lg_nll1iOO4203w(0) <= NOT nll1iOO; + wire_nliii_w_lg_nll1l1i4208w(0) <= NOT nll1l1i; + wire_nliii_w_lg_nll1Oil4160w(0) <= NOT nll1Oil; + wire_nliii_w_lg_nlli01i4246w(0) <= NOT nlli01i; + wire_nliii_w_lg_nlli11l4299w(0) <= NOT nlli11l; + wire_nliii_w_lg_nlli1il4235w(0) <= NOT nlli1il; + wire_nliii_w_lg_nlli1iO4270w(0) <= NOT nlli1iO; + wire_nliii_w_lg_nlli1li4268w(0) <= NOT nlli1li; + wire_nliii_w_lg_nlli1ll4232w(0) <= NOT nlli1ll; + wire_nliii_w_lg_nlli1lO4265w(0) <= NOT nlli1lO; + wire_nliii_w_lg_nlli1Oi4263w(0) <= NOT nlli1Oi; + wire_nliii_w_lg_nlli1Ol4261w(0) <= NOT nlli1Ol; + wire_nliii_w_lg_nlli1OO4259w(0) <= NOT nlli1OO; + wire_nliii_w_lg_nllll0i4065w(0) <= NOT nllll0i; + wire_nliii_w_lg_nllll0l4320w(0) <= NOT nllll0l; + wire_nliii_w_lg_nllll0O4318w(0) <= NOT nllll0O; + wire_nliii_w_lg_nllll1l4168w(0) <= NOT nllll1l; + wire_nliii_w_lg_nllllii4359w(0) <= NOT nllllii; + wire_nliii_w_lg_nllllil4344w(0) <= NOT nllllil; + wire_nliii_w_lg_nlllliO4356w(0) <= NOT nlllliO; + wire_nliii_w_lg_nllllli4333w(0) <= NOT nllllli; + wire_nliii_w_lg_nllllll4312w(0) <= NOT nllllll; + wire_nliii_w_lg_nlllllO4323w(0) <= NOT nlllllO; + wire_nliii_w_lg_nlllO1i3849w(0) <= NOT nlllO1i; + wire_nliii_w_lg_nllOO0i3671w(0) <= NOT nllOO0i; + wire_nliii_w_lg_nllOO1O3666w(0) <= NOT nllOO1O; + wire_nliii_w_lg_nlO000l3762w(0) <= NOT nlO000l; + wire_nliii_w_lg_nlO00l627w(0) <= NOT nlO00l; + wire_nliii_w_lg_nlO00ll3698w(0) <= NOT nlO00ll; + wire_nliii_w_lg_nlO00lO3733w(0) <= NOT nlO00lO; + wire_nliii_w_lg_nlO00Oi3731w(0) <= NOT nlO00Oi; + wire_nliii_w_lg_nlO00Ol3695w(0) <= NOT nlO00Ol; + wire_nliii_w_lg_nlO00OO3728w(0) <= NOT nlO00OO; + wire_nliii_w_lg_nlO01lO3751w(0) <= NOT nlO01lO; + wire_nliii_w_lg_nlO01OO3748w(0) <= NOT nlO01OO; + wire_nliii_w_lg_nlO0i0i3709w(0) <= NOT nlO0i0i; + wire_nliii_w_lg_nlO0i1i3726w(0) <= NOT nlO0i1i; + wire_nliii_w_lg_nlO0i1l3724w(0) <= NOT nlO0i1l; + wire_nliii_w_lg_nlO0i1O3722w(0) <= NOT nlO0i1O; + wire_nliii_w_lg_nlO10l946w(0) <= NOT nlO10l; + wire_nliii_w_lg_nlO11ll3623w(0) <= NOT nlO11ll; + wire_nliii_w_lg_nlO1ii844w(0) <= NOT nlO1ii; + wire_nliii_w_lg_nlO1il1098w(0) <= NOT nlO1il; + wire_nliii_w_lg_nlO1iO1096w(0) <= NOT nlO1iO; + wire_nliii_w_lg_nlO1li1137w(0) <= NOT nlO1li; + wire_nliii_w_lg_nlO1ll1122w(0) <= NOT nlO1ll; + wire_nliii_w_lg_nlO1lO1134w(0) <= NOT nlO1lO; + wire_nliii_w_lg_nlO1Oi1111w(0) <= NOT nlO1Oi; + wire_nliii_w_lg_nlO1Ol1090w(0) <= NOT nlO1Ol; + wire_nliii_w_lg_nlO1OO1101w(0) <= NOT nlO1OO; + wire_nliii_w_lg_nlOiO0l3631w(0) <= NOT nlOiO0l; + wire_nliii_w_lg_nlOiOii3529w(0) <= NOT nlOiOii; + wire_nliii_w_lg_nlOiOil3783w(0) <= NOT nlOiOil; + wire_nliii_w_lg_nlOiOiO3781w(0) <= NOT nlOiOiO; + wire_nliii_w_lg_nlOiOli3822w(0) <= NOT nlOiOli; + wire_nliii_w_lg_nlOiOll3807w(0) <= NOT nlOiOll; + wire_nliii_w_lg_nlOiOlO3819w(0) <= NOT nlOiOlO; + wire_nliii_w_lg_nlOiOOi3796w(0) <= NOT nlOiOOi; + wire_nliii_w_lg_nlOiOOl3775w(0) <= NOT nlOiOOl; + wire_nliii_w_lg_nlOiOOO3786w(0) <= NOT nlOiOOO; + wire_nliii_w_lg_nlOl10i3313w(0) <= NOT nlOl10i; + wire_nliii_w_lg_nlOO0Ol3087w(0) <= NOT nlOO0Ol; + wire_nliii_w_lg_nlOO10O3130w(0) <= NOT nlOO10O; + wire_nliii_w_lg_nlOO1ii3135w(0) <= NOT nlOO1ii; + PROCESS (pclk, wire_nll1Oli_CLRN) + BEGIN + IF (wire_nll1Oli_CLRN = '0') THEN + nll1OiO <= '0'; + nll1Oll <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_nll00lO_o = '1') THEN + nll1OiO <= nli1l1i; + nll1Oll <= nli1l0i; + END IF; + END IF; + END PROCESS; + wire_nll1Oli_CLRN <= ((nli1iiO72 XOR nli1iiO71) AND prstn); + PROCESS (uclk, wire_nlO01i_PRN) + BEGIN + IF (wire_nlO01i_PRN = '0') THEN + n00iii <= '1'; + n1i00i <= '1'; + ni1lli <= '1'; + niOOOi <= '1'; + nliOili <= '1'; + nllllOi <= '1'; + nlO01l <= '1'; + nlOl11i <= '1'; + ELSIF (uclk = '1' AND uclk'event) THEN + n00iii <= n00iOi; + n1i00i <= n1i0li; + ni1lli <= ni1O1i; + niOOOi <= nl110i; + nliOili <= nliOl1i; + nllllOi <= nlllO0i; + nlO01l <= nlO0iO; + nlOl11i <= nlOl1ii; + END IF; + END PROCESS; + wire_nlO01i_PRN <= (nliliOl54 XOR nliliOl53); + PROCESS (pclk, wire_nlO0ii_PRN, wire_nlO0ii_CLRN) + BEGIN + IF (wire_nlO0ii_PRN = '0') THEN + n00ilO <= '1'; + n1i0iO <= '1'; + ni1lOO <= '1'; + nl111O <= '1'; + nliOiOO <= '1'; + nlllO1O <= '1'; + nlO0il <= '1'; + nlOl10O <= '1'; + ELSIF (wire_nlO0ii_CLRN = '0') THEN + n00ilO <= '0'; + n1i0iO <= '0'; + ni1lOO <= '0'; + nl111O <= '0'; + nliOiOO <= '0'; + nlllO1O <= '0'; + nlO0il <= '0'; + nlOl10O <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + n00ilO <= n00iOO; + n1i0iO <= n1i0lO; + ni1lOO <= ni1O1O; + nl111O <= nl110O; + nliOiOO <= nliOl1O; + nlllO1O <= nlllO0O; + nlO0il <= nlO0ll; + nlOl10O <= nlOl1iO; + END IF; + END PROCESS; + wire_nlO0ii_CLRN <= (nlill1i50 XOR nlill1i49); + wire_nlO0ii_PRN <= (nliliOO52 XOR nliliOO51); + PROCESS (uclk, wire_nlO0lO_CLRN) + BEGIN + IF (wire_nlO0lO_CLRN = '0') THEN + n00ill <= '0'; + n00iOO <= '0'; + n00l1i <= '0'; + n1i0il <= '0'; + n1i0lO <= '0'; + n1i0Oi <= '0'; + ni1lOl <= '0'; + ni1O0i <= '0'; + ni1O1O <= '0'; + nl110O <= '0'; + nl111l <= '0'; + nl11ii <= '0'; + nliOiOl <= '0'; + nliOl0i <= '0'; + nliOl1O <= '0'; + nlllO0O <= '0'; + nlllO1l <= '0'; + nlllOii <= '0'; + nlO00O <= '0'; + nlO0ll <= '0'; + nlO0Oi <= '0'; + nlOl10l <= '0'; + nlOl1iO <= '0'; + nlOl1li <= '0'; + ELSIF (uclk = '1' AND uclk'event) THEN + n00ill <= n00iii; + n00iOO <= wire_n00l1l_dataout; + n00l1i <= wire_n00l0l_dataout; + n1i0il <= n1i00i; + n1i0lO <= wire_n1i0Ol_dataout; + n1i0Oi <= wire_n1ii1l_dataout; + ni1lOl <= ni1lli; + ni1O0i <= wire_ni1Oil_dataout; + ni1O1O <= wire_ni1O0l_dataout; + nl110O <= wire_nl11il_dataout; + nl111l <= niOOOi; + nl11ii <= wire_nl11ll_dataout; + nliOiOl <= nliOili; + nliOl0i <= wire_nliOlil_dataout; + nliOl1O <= wire_nliOl0l_dataout; + nlllO0O <= wire_nlllOil_dataout; + nlllO1l <= nllllOi; + nlllOii <= wire_nlllOll_dataout; + nlO00O <= nlO01l; + nlO0ll <= wire_nlO0Ol_dataout; + nlO0Oi <= wire_nlOi1l_dataout; + nlOl10l <= nlOl11i; + nlOl1iO <= wire_nlOl1ll_dataout; + nlOl1li <= wire_nlOl1Ol_dataout; + END IF; + END PROCESS; + wire_nlO0lO_CLRN <= ((nlill1l48 XOR nlill1l47) AND urstn); + wire_nlO0lO_w_lg_n00iOO2233w(0) <= NOT n00iOO; + wire_nlO0lO_w_lg_n1i0lO2771w(0) <= NOT n1i0lO; + wire_nlO0lO_w_lg_ni1O1O1697w(0) <= NOT ni1O1O; + wire_nlO0lO_w_lg_nl110O1160w(0) <= NOT nl110O; + wire_nlO0lO_w_lg_nliOl1O4382w(0) <= NOT nliOl1O; + wire_nlO0lO_w_lg_nlllO0O3845w(0) <= NOT nlllO0O; + wire_nlO0lO_w_lg_nlO0ll619w(0) <= NOT nlO0ll; + wire_nlO0lO_w_lg_nlOl1iO3309w(0) <= NOT nlOl1iO; + PROCESS (pclk, wire_nlO11Oi_PRN, prstn) + BEGIN + IF (wire_nlO11Oi_PRN = '0') THEN + nlO11lO <= '1'; + nlO11Ol <= '1'; + ELSIF (prstn = '0') THEN + nlO11lO <= '0'; + nlO11Ol <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_nlO1iOO_o = '1') THEN + nlO11lO <= nli010i; + nlO11Ol <= nli01ii; + END IF; + END IF; + END PROCESS; + wire_nlO11Oi_PRN <= (nli1OlO70 XOR nli1OlO69); + PROCESS (pclk, wire_nlOOi1i_PRN, wire_nlOOi1i_CLRN) + BEGIN + IF (wire_nlOOi1i_PRN = '0') THEN + nlOO0OO <= '1'; + nlOOi1l <= '1'; + ELSIF (wire_nlOOi1i_CLRN = '0') THEN + nlOO0OO <= '0'; + nlOOi1l <= '0'; + ELSIF (pclk = '1' AND pclk'event) THEN + IF (wire_nlOOO1O_o = '1') THEN + nlOO0OO <= nli0iil; + nlOOi1l <= nli0ill; + END IF; + END IF; + END PROCESS; + wire_nlOOi1i_CLRN <= ((nli0i1i66 XOR nli0i1i65) AND prstn); + wire_nlOOi1i_PRN <= (nli00OO68 XOR nli00OO67); + wire_n0001i_dataout <= n0001l AND enable_inf_ei(0); + wire_n0001O_dataout <= ((wire_n001lO_dataout OR wire_n001ll_dataout) OR wire_n001Oi_dataout) WHEN rate = '1' ELSE ((wire_n001OO_dataout OR wire_n001Ol_dataout) OR wire_n0001i_dataout); + wire_n0010i_dataout <= wire_n001li_o(1) AND NOT(n1OOlO); + wire_n0010l_dataout <= wire_n001li_o(2) AND NOT(n1OOlO); + wire_n0010O_dataout <= wire_n001li_o(3) AND NOT(n1OOlO); + wire_n0011i_dataout <= wire_n0011l_o(6) AND NOT(n1OOll); + wire_n0011O_dataout <= wire_n001li_o(0) AND NOT(n1OOlO); + wire_n001i_dataout <= wire_n000i_o(2) AND nlilliO; + wire_n001ii_dataout <= wire_n001li_o(4) AND NOT(n1OOlO); + wire_n001il_dataout <= wire_n001li_o(5) AND NOT(n1OOlO); + wire_n001iO_dataout <= wire_n001li_o(6) AND NOT(n1OOlO); + wire_n001l_dataout <= wire_n000i_o(3) AND nlilliO; + wire_n001ll_dataout <= n1llll AND enable_inf_ei(5); + wire_n001lO_dataout <= n1l00O AND enable_inf_ei(4); + wire_n001O_dataout <= wire_n000i_o(4) AND nlilliO; + wire_n001Oi_dataout <= n0001l AND enable_inf_ei(3); + wire_n001Ol_dataout <= n1llll AND enable_inf_ei(2); + wire_n001OO_dataout <= n1l00O AND enable_inf_ei(1); + wire_n00iil_dataout <= wire_nliii_w_lg_n00ili2237w(0) WHEN (n00iOl XOR n00iOi) = '1' ELSE n00ili; + wire_n00l0l_dataout <= n00l1i WHEN nlii00l = '1' ELSE rxupdatefc; + wire_n00l1l_dataout <= wire_nlO0lO_w_lg_n00iOO2233w(0) WHEN (wire_w_lg_nlii00l2234w(0) AND (rxupdatefc XOR n00l1i)) = '1' ELSE n00iOO; + wire_n0100i_dataout <= wire_n010OO_dataout AND NOT(n1OOll); + wire_n0100l_dataout <= wire_n01i1i_dataout AND NOT(n1OOll); + wire_n0100O_dataout <= wire_n01i1l_dataout AND NOT(n1OOll); + wire_n0101i_dataout <= wire_n010lO_dataout AND NOT(n1OOll); + wire_n0101l_dataout <= wire_n010Oi_dataout AND NOT(n1OOll); + wire_n0101O_dataout <= wire_n010Ol_dataout AND NOT(n1OOll); + wire_n010ii_dataout <= wire_n01i1O_dataout AND NOT(n1OOll); + wire_n010il_dataout <= wire_n01i0i_dataout AND NOT(n1OOll); + wire_n010iO_dataout <= wire_n01i0l_dataout AND NOT(n1OOll); + wire_n010li_dataout <= wire_n01i0O_dataout AND NOT(n1OOll); + wire_n010ll_dataout <= wire_n01iii_dataout AND NOT(n1OOll); + wire_n010lO_dataout <= n1Oi0O OR nlii1Oi; + wire_n010Oi_dataout <= n1Ol1l OR nlii1Ol; + wire_n010Ol_dataout <= wire_n01iil_o(0) WHEN n1OOOl = '1' ELSE n1Ol1O; + wire_n010OO_dataout <= wire_n01iil_o(1) WHEN n1OOOl = '1' ELSE n1Ol0i; + wire_n01i0i_dataout <= wire_n01iil_o(5) WHEN n1OOOl = '1' ELSE n1Olil; + wire_n01i0l_dataout <= wire_n01iil_o(6) WHEN n1OOOl = '1' ELSE n1OliO; + wire_n01i0O_dataout <= wire_n01iil_o(7) WHEN n1OOOl = '1' ELSE n1Olli; + wire_n01i1i_dataout <= wire_n01iil_o(2) WHEN n1OOOl = '1' ELSE n1Ol0l; + wire_n01i1l_dataout <= wire_n01iil_o(3) WHEN n1OOOl = '1' ELSE n1Ol0O; + wire_n01i1O_dataout <= wire_n01iil_o(4) WHEN n1OOOl = '1' ELSE n1Olii; + wire_n01ii_dataout <= wire_n01ll_dataout OR nlilllO; + wire_n01iii_dataout <= wire_n01iil_o(8) WHEN n1OOOl = '1' ELSE n1Olll; + wire_n01iiO_dataout <= wire_n01lil_dataout AND NOT(n1OOlO); + wire_n01il_dataout <= wire_n01lO_dataout AND NOT(nlilllO); + wire_n01ili_dataout <= wire_n01liO_dataout AND NOT(n1OOlO); + wire_n01ill_dataout <= wire_n01lli_dataout AND NOT(n1OOlO); + wire_n01ilO_dataout <= wire_n01lll_dataout AND NOT(n1OOlO); + wire_n01iO_dataout <= wire_n01Oi_dataout OR nlilllO; + wire_n01iOi_dataout <= wire_n01llO_dataout AND NOT(n1OOlO); + wire_n01iOl_dataout <= wire_n01lOi_dataout AND NOT(n1OOlO); + wire_n01iOO_dataout <= wire_n01lOl_dataout AND NOT(n1OOlO); + wire_n01l0i_dataout <= wire_n01O1O_dataout AND NOT(n1OOlO); + wire_n01l0l_dataout <= wire_n01O0i_dataout AND NOT(n1OOlO); + wire_n01l0O_dataout <= wire_n01O0l_dataout AND NOT(n1OOlO); + wire_n01l1i_dataout <= wire_n01lOO_dataout AND NOT(n1OOlO); + wire_n01l1l_dataout <= wire_n01O1i_dataout AND NOT(n1OOlO); + wire_n01l1O_dataout <= wire_n01O1l_dataout AND NOT(n1OOlO); + wire_n01li_dataout <= wire_n01Ol_dataout OR nlilllO; + wire_n01lii_dataout <= wire_n01O0O_dataout AND NOT(n1OOlO); + wire_n01lil_dataout <= n1OllO OR nlii1OO; + wire_n01liO_dataout <= n1OlOi OR nlii01i; + wire_n01ll_dataout <= wire_n01OO_dataout WHEN wire_w_lg_nlillil325w(0) = '1' ELSE n1l0O; + wire_n01lli_dataout <= n1OlOl OR nlii01l; + wire_n01lll_dataout <= n1OlOO OR nlii01O; + wire_n01llO_dataout <= n1OO1i OR nlii00i; + wire_n01lO_dataout <= wire_n001i_dataout WHEN wire_w_lg_nlillil325w(0) = '1' ELSE n1lii; + wire_n01lOi_dataout <= wire_n01Oii_o(0) WHEN n1OOOO = '1' ELSE n1OO1l; + wire_n01lOl_dataout <= wire_n01Oii_o(1) WHEN n1OOOO = '1' ELSE n1OO1O; + wire_n01lOO_dataout <= wire_n01Oii_o(2) WHEN n1OOOO = '1' ELSE n1OO0i; + wire_n01O0i_dataout <= wire_n01Oii_o(6) WHEN n1OOOO = '1' ELSE n1OOil; + wire_n01O0l_dataout <= wire_n01Oii_o(7) WHEN n1OOOO = '1' ELSE n1OOiO; + wire_n01O0O_dataout <= wire_n01Oii_o(8) WHEN n1OOOO = '1' ELSE n1OOli; + wire_n01O1i_dataout <= wire_n01Oii_o(3) WHEN n1OOOO = '1' ELSE n1OO0l; + wire_n01O1l_dataout <= wire_n01Oii_o(4) WHEN n1OOOO = '1' ELSE n1OO0O; + wire_n01O1O_dataout <= wire_n01Oii_o(5) WHEN n1OOOO = '1' ELSE n1OOii; + wire_n01Oi_dataout <= wire_n001l_dataout WHEN wire_w_lg_nlillil325w(0) = '1' ELSE n1lil; + wire_n01Ol_dataout <= wire_n001O_dataout WHEN wire_w_lg_nlillil325w(0) = '1' ELSE n1liO; + wire_n01Oli_dataout <= wire_n0011l_o(0) AND NOT(n1OOll); + wire_n01Oll_dataout <= wire_n0011l_o(1) AND NOT(n1OOll); + wire_n01OlO_dataout <= wire_n0011l_o(2) AND NOT(n1OOll); + wire_n01OO_dataout <= wire_n000i_o(1) AND nlilliO; + wire_n01OOi_dataout <= wire_n0011l_o(3) AND NOT(n1OOll); + wire_n01OOl_dataout <= wire_n0011l_o(4) AND NOT(n1OOll); + wire_n01OOO_dataout <= wire_n0011l_o(5) AND NOT(n1OOll); + wire_n0i0OO_dataout <= n0iiiO OR wire_nliii_w_lg_ni1iOl2019w(0); + wire_n0ii0i_dataout <= wire_n0iiil_dataout AND NOT(n0i0li); + wire_n0ii0l_dataout <= n0i0ii AND NOT(ni1iOl); + wire_n0ii0O_dataout <= n0i0il AND NOT(ni1iOl); + wire_n0ii1i_dataout <= wire_n0ii0l_dataout AND NOT(n0i0li); + wire_n0ii1l_dataout <= wire_n0ii0O_dataout OR n0i0li; + wire_n0ii1O_dataout <= wire_n0iiii_dataout AND NOT(n0i0li); + wire_n0iiii_dataout <= n0i0iO OR ni1iOl; + wire_n0iiil_dataout <= n0iiiO AND NOT(ni1iOl); + wire_n0ili_dataout <= n100O WHEN nliO1ii = '1' ELSE nl01O; + wire_n0ill_dataout <= nl0Oi OR rate; + wire_n0ilO_dataout <= n0lOO AND NOT(rate); + wire_n0iOi_dataout <= n0lOi WHEN rate = '1' ELSE n0llO; + wire_n0iOl_dataout <= ((n0O1i OR n0l1l) OR (NOT (nliO1il30 XOR nliO1il29))) WHEN rate = '1' ELSE (n0lOO OR n0i0O); + wire_n0l0li_dataout <= wire_n0l0Ol_dataout OR nlii0Ol; + wire_n0l0ll_dataout <= wire_n0l0OO_dataout AND NOT(nlii0Ol); + wire_n0l0lO_dataout <= wire_n0li1i_dataout OR nlii0Ol; + wire_n0l0Oi_dataout <= wire_n0li1l_dataout OR nlii0Ol; + wire_n0l0Ol_dataout <= wire_n0li1O_dataout WHEN wire_w_lg_nlii0li1950w(0) = '1' ELSE n0iOiO; + wire_n0l0OO_dataout <= wire_n0li0i_dataout WHEN wire_w_lg_nlii0li1950w(0) = '1' ELSE n0iOli; + wire_n0l10l_dataout <= wire_n0l10O_dataout AND NOT(nlii0Ol); + wire_n0l10O_dataout <= wire_n0l1ii_dataout OR (wire_w_lg_nliiiii2003w(0) AND wire_w_lg_w_lg_nliii0O1986w2004w(0)); + wire_n0l1ii_dataout <= wire_n0l1il_dataout OR (wire_w_lg_nliii0O1986w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_n0iOlO1988w1990w1992w1993w(0) OR (wire_nl01l_w_lg_w_lg_n0iOlO1995w1996w(0) AND wire_nl01l_w_lg_n0iOiO1991w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_n0iOlO1995w1999w2000w(0))); + wire_n0l1il_dataout <= wire_n0l1iO_dataout OR (wire_w_lg_nliii0O1986w(0) AND nlii0iO); + wire_n0l1iO_dataout <= n0iO0l OR (wire_n0l01i_o AND (((nliii1O XOR n0iOil) OR (nlii0OO XOR n0iO0O)) OR (NOT (n0iOil XOR n0iO0O)))); + wire_n0li0i_dataout <= wire_n0liii_o(2) AND nlii0ll; + wire_n0li0l_dataout <= wire_n0liii_o(3) AND nlii0ll; + wire_n0li0O_dataout <= wire_n0liii_o(4) AND nlii0ll; + wire_n0li1i_dataout <= wire_n0li0l_dataout WHEN wire_w_lg_nlii0li1950w(0) = '1' ELSE n0iOll; + wire_n0li1l_dataout <= wire_n0li0O_dataout WHEN wire_w_lg_nlii0li1950w(0) = '1' ELSE n0iOlO; + wire_n0li1O_dataout <= wire_n0liii_o(1) AND nlii0ll; + wire_n0llOi_dataout <= n0iiiO WHEN nliiiOi = '1' ELSE ni1i0l; + wire_n0llOl_dataout <= ni1iOO OR rate; + wire_n0llOO_dataout <= n0O11O AND NOT(rate); + wire_n0lO1i_dataout <= n0O11i WHEN rate = '1' ELSE n0lOOO; + wire_n0lO1l_dataout <= (n0O10i OR n0lO0l) WHEN rate = '1' ELSE (n0O11O OR n0lliO); + wire_n0Oi0i_dataout <= wire_n0OiOO_dataout AND NOT(n0O1Ol); + wire_n0Oi0l_dataout <= wire_n0Ol1i_dataout AND NOT(n0O1Ol); + wire_n0Oi0O_dataout <= wire_n0Ol1l_dataout AND NOT(n0O1Ol); + wire_n0Oiii_dataout <= wire_n0Ol1O_dataout AND NOT(n0O1Ol); + wire_n0Oiil_dataout <= wire_n0Ol0i_dataout AND NOT(n0O1Ol); + wire_n0OiiO_dataout <= wire_n0Ol0l_dataout AND NOT(n0O1Ol); + wire_n0Oili_dataout <= wire_n0Ol0O_dataout AND NOT(n0O1Ol); + wire_n0Oill_dataout <= wire_n0Olii_dataout AND NOT(n0O1Ol); + wire_n0OilO_dataout <= wire_n0Olil_dataout AND NOT(n0O1Ol); + wire_n0OiOi_dataout <= wire_n0OliO_dataout AND NOT(n0O1Ol); + wire_n0OiOl_dataout <= wire_n0Olli_dataout AND NOT(n0O1Ol); + wire_n0OiOO_dataout <= n0lliO OR nliil1i; + wire_n0Ol0i_dataout <= wire_n0Olll_o(2) WHEN n0O01l = '1' ELSE n0lOil; + wire_n0Ol0l_dataout <= wire_n0Olll_o(3) WHEN n0O01l = '1' ELSE n0lOiO; + wire_n0Ol0O_dataout <= wire_n0Olll_o(4) WHEN n0O01l = '1' ELSE n0lOli; + wire_n0Ol1i_dataout <= n0lO0l OR nliil1l; + wire_n0Ol1l_dataout <= wire_n0Olll_o(0) WHEN n0O01l = '1' ELSE n0lO0O; + wire_n0Ol1O_dataout <= wire_n0Olll_o(1) WHEN n0O01l = '1' ELSE n0lOii; + wire_n0Olii_dataout <= wire_n0Olll_o(5) WHEN n0O01l = '1' ELSE n0lOll; + wire_n0Olil_dataout <= wire_n0Olll_o(6) WHEN n0O01l = '1' ELSE n0lOlO; + wire_n0OliO_dataout <= wire_n0Olll_o(7) WHEN n0O01l = '1' ELSE n0lOOi; + wire_n0Olli_dataout <= wire_n0Olll_o(8) WHEN n0O01l = '1' ELSE n0lOOl; + wire_n0OllO_dataout <= wire_n0OOll_dataout AND NOT(n0O1OO); + wire_n0OlOi_dataout <= wire_n0OOlO_dataout AND NOT(n0O1OO); + wire_n0OlOl_dataout <= wire_n0OOOi_dataout AND NOT(n0O1OO); + wire_n0OlOO_dataout <= wire_n0OOOl_dataout AND NOT(n0O1OO); + wire_n0OO0i_dataout <= wire_ni111O_dataout AND NOT(n0O1OO); + wire_n0OO0l_dataout <= wire_ni110i_dataout AND NOT(n0O1OO); + wire_n0OO0O_dataout <= wire_ni110l_dataout AND NOT(n0O1OO); + wire_n0OO1i_dataout <= wire_n0OOOO_dataout AND NOT(n0O1OO); + wire_n0OO1l_dataout <= wire_ni111i_dataout AND NOT(n0O1OO); + wire_n0OO1O_dataout <= wire_ni111l_dataout AND NOT(n0O1OO); + wire_n0OOii_dataout <= wire_ni110O_dataout AND NOT(n0O1OO); + wire_n0OOil_dataout <= wire_ni11ii_dataout AND NOT(n0O1OO); + wire_n0OOiO_dataout <= wire_ni11il_dataout AND NOT(n0O1OO); + wire_n0OOli_dataout <= wire_ni11iO_dataout AND NOT(n0O1OO); + wire_n0OOll_dataout <= n0lOOO OR nliil1O; + wire_n0OOlO_dataout <= n0O11i OR nliil0i; + wire_n0OOOi_dataout <= n0O11l OR nliil0l; + wire_n0OOOl_dataout <= n0O11O OR nliil0O; + wire_n0OOOO_dataout <= n0O10i OR nliilii; + wire_n1000i_dataout <= wire_n1000l_o(8) WHEN n11lll = '1' ELSE n11iil; + wire_n1000O_dataout <= wire_n10i0l_dataout AND NOT(n11liO); + wire_n1001i_dataout <= wire_n1000l_o(5) WHEN n11lll = '1' ELSE n11i0l; + wire_n1001l_dataout <= wire_n1000l_o(6) WHEN n11lll = '1' ELSE n11i0O; + wire_n1001O_dataout <= wire_n1000l_o(7) WHEN n11lll = '1' ELSE n11iii; + wire_n100i_dataout <= n110O OR nl0lO; + wire_n100ii_dataout <= wire_n10i0O_dataout AND NOT(n11liO); + wire_n100il_dataout <= wire_n10iii_dataout AND NOT(n11liO); + wire_n100iO_dataout <= wire_n10iil_dataout AND NOT(n11liO); + wire_n100l_dataout <= n100O AND NOT(nl0lO); + wire_n100li_dataout <= wire_n10iiO_dataout AND NOT(n11liO); + wire_n100ll_dataout <= wire_n10ili_dataout AND NOT(n11liO); + wire_n100lO_dataout <= wire_n10ill_dataout AND NOT(n11liO); + wire_n100Oi_dataout <= wire_n10ilO_dataout AND NOT(n11liO); + wire_n100Ol_dataout <= wire_n10iOi_dataout AND NOT(n11liO); + wire_n100OO_dataout <= wire_n10iOl_dataout AND NOT(n11liO); + wire_n1010i_dataout <= wire_n101OO_dataout AND NOT(n11lil); + wire_n1010l_dataout <= wire_n1001i_dataout AND NOT(n11lil); + wire_n1010O_dataout <= wire_n1001l_dataout AND NOT(n11lil); + wire_n1011i_dataout <= wire_n101lO_dataout AND NOT(n11lil); + wire_n1011l_dataout <= wire_n101Oi_dataout AND NOT(n11lil); + wire_n1011O_dataout <= wire_n101Ol_dataout AND NOT(n11lil); + wire_n101i_dataout <= wire_n100l_dataout AND NOT(n11ii); + wire_n101ii_dataout <= wire_n1001O_dataout AND NOT(n11lil); + wire_n101il_dataout <= wire_n1000i_dataout AND NOT(n11lil); + wire_n101iO_dataout <= n1101O OR nli0liO; + wire_n101l_dataout <= n110i AND NOT(nl0lO); + wire_n101li_dataout <= n110Ol OR nli0lli; + wire_n101ll_dataout <= wire_n1000l_o(0) WHEN n11lll = '1' ELSE n110OO; + wire_n101lO_dataout <= wire_n1000l_o(1) WHEN n11lll = '1' ELSE n11i1i; + wire_n101O_dataout <= n110l AND NOT(nl0lO); + wire_n101Oi_dataout <= wire_n1000l_o(2) WHEN n11lll = '1' ELSE n11i1l; + wire_n101Ol_dataout <= wire_n1000l_o(3) WHEN n11lll = '1' ELSE n11i1O; + wire_n101OO_dataout <= wire_n1000l_o(4) WHEN n11lll = '1' ELSE n11i0i; + wire_n10i0i_dataout <= wire_n10l1O_dataout AND NOT(n11liO); + wire_n10i0l_dataout <= n11iiO OR nli0lll; + wire_n10i0O_dataout <= n11ili OR nli0llO; + wire_n10i1i_dataout <= wire_n10iOO_dataout AND NOT(n11liO); + wire_n10i1l_dataout <= wire_n10l1i_dataout AND NOT(n11liO); + wire_n10i1O_dataout <= wire_n10l1l_dataout AND NOT(n11liO); + wire_n10iii_dataout <= n11ill OR nli0lOi; + wire_n10iil_dataout <= n11ilO OR nli0lOl; + wire_n10iiO_dataout <= n11iOi OR nli0lOO; + wire_n10ili_dataout <= wire_n10l0i_o(0) WHEN n11llO = '1' ELSE n11iOl; + wire_n10ill_dataout <= wire_n10l0i_o(1) WHEN n11llO = '1' ELSE n11iOO; + wire_n10ilO_dataout <= wire_n10l0i_o(2) WHEN n11llO = '1' ELSE n11l1i; + wire_n10iOi_dataout <= wire_n10l0i_o(3) WHEN n11llO = '1' ELSE n11l1l; + wire_n10iOl_dataout <= wire_n10l0i_o(4) WHEN n11llO = '1' ELSE n11l1O; + wire_n10iOO_dataout <= wire_n10l0i_o(5) WHEN n11llO = '1' ELSE n11l0i; + wire_n10l1i_dataout <= wire_n10l0i_o(6) WHEN n11llO = '1' ELSE n11l0l; + wire_n10l1l_dataout <= wire_n10l0i_o(7) WHEN n11llO = '1' ELSE n11l0O; + wire_n10l1O_dataout <= wire_n10l0i_o(8) WHEN n11llO = '1' ELSE n11lii; + wire_n10lii_dataout <= wire_n10lOl_o(0) AND NOT(n11lil); + wire_n10lil_dataout <= wire_n10lOl_o(1) AND NOT(n11lil); + wire_n10liO_dataout <= wire_n10lOl_o(2) AND NOT(n11lil); + wire_n10lli_dataout <= wire_n10lOl_o(3) AND NOT(n11lil); + wire_n10lll_dataout <= wire_n10lOl_o(4) AND NOT(n11lil); + wire_n10llO_dataout <= wire_n10lOl_o(5) AND NOT(n11lil); + wire_n10lOi_dataout <= wire_n10lOl_o(6) AND NOT(n11lil); + wire_n10lOO_dataout <= wire_n10Oii_o(0) AND NOT(n11liO); + wire_n10O0i_dataout <= wire_n10Oii_o(4) AND NOT(n11liO); + wire_n10O0l_dataout <= wire_n10Oii_o(5) AND NOT(n11liO); + wire_n10O0O_dataout <= wire_n10Oii_o(6) AND NOT(n11liO); + wire_n10O1i_dataout <= wire_n10Oii_o(1) AND NOT(n11liO); + wire_n10O1l_dataout <= wire_n10Oii_o(2) AND NOT(n11liO); + wire_n10O1O_dataout <= wire_n10Oii_o(3) AND NOT(n11liO); + wire_n10Oil_dataout <= nlOOiil AND enable_inf_ei(5); + wire_n10OiO_dataout <= nlOO11O AND enable_inf_ei(4); + wire_n10Oli_dataout <= n10OOl AND enable_inf_ei(3); + wire_n10Oll_dataout <= nlOOiil AND enable_inf_ei(2); + wire_n10OlO_dataout <= nlOO11O AND enable_inf_ei(1); + wire_n10OOi_dataout <= n10OOl AND enable_inf_ei(0); + wire_n10OOO_dataout <= ((wire_n10OiO_dataout OR wire_n10Oil_dataout) OR wire_n10Oli_dataout) WHEN rate = '1' ELSE ((wire_n10OlO_dataout OR wire_n10Oll_dataout) OR wire_n10OOi_dataout); + wire_n110ii_dataout <= nlOO11O WHEN nli0l0O = '1' ELSE n10OOl; + wire_n110il_dataout <= n1i1iO OR rate; + wire_n110iO_dataout <= n11ilO AND NOT(rate); + wire_n110li_dataout <= n11ili WHEN rate = '1' ELSE n11iiO; + wire_n110ll_dataout <= (n11iOi OR n110Ol) WHEN rate = '1' ELSE (n11ilO OR n1101O); + wire_n11lO_dataout <= n100O OR wire_nliii_w_lg_nl0lO394w(0); + wire_n11Oi_dataout <= wire_n101l_dataout AND NOT(n11ii); + wire_n11Ol_dataout <= wire_n101O_dataout OR n11ii; + wire_n11OO_dataout <= wire_n100i_dataout AND NOT(n11ii); + wire_n11OOi_dataout <= wire_n101iO_dataout AND NOT(n11lil); + wire_n11OOl_dataout <= wire_n101li_dataout AND NOT(n11lil); + wire_n11OOO_dataout <= wire_n101ll_dataout AND NOT(n11lil); + wire_n1i00l_dataout <= wire_nliii_w_lg_n1i0ii2775w(0) WHEN (n1i0ll XOR n1i0li) = '1' ELSE n1i0ii; + wire_n1i0Ol_dataout <= wire_nlO0lO_w_lg_n1i0lO2771w(0) WHEN (wire_w_lg_nli0O1i2772w(0) AND (rxupdatefc XOR n1i0Oi)) = '1' ELSE n1i0lO; + wire_n1ii1l_dataout <= n1i0Oi WHEN nli0O1i = '1' ELSE rxupdatefc; + wire_n1l00i_dataout <= n1l10O OR n000ll; + wire_n1l00l_dataout <= n1l00O AND NOT(n000ll); + wire_n1l01i_dataout <= wire_n1l00l_dataout AND NOT(n1l1ii); + wire_n1l01l_dataout <= n1l10i AND NOT(n000ll); + wire_n1l01O_dataout <= n1l10l AND NOT(n000ll); + wire_n1l1lO_dataout <= n1l00O OR wire_nliii_w_lg_n000ll2557w(0); + wire_n1l1Oi_dataout <= wire_n1l01l_dataout AND NOT(n1l1ii); + wire_n1l1Ol_dataout <= wire_n1l01O_dataout OR n1l1ii; + wire_n1l1OO_dataout <= wire_n1l00i_dataout AND NOT(n1l1ii); + wire_n1lO0i_dataout <= wire_n1lO0l_dataout OR (wire_w_lg_nlii11O2522w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_n1lliO2524w2526w2528w2529w(0) OR (wire_nl01l_w_lg_w_lg_n1lliO2531w2532w(0) AND wire_nl01l_w_lg_n1ll0O2527w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_n1lliO2531w2535w2536w(0))); + wire_n1lO0l_dataout <= wire_n1lO0O_dataout OR (wire_w_lg_nlii11O2522w(0) AND nli0O0O); + wire_n1lO0O_dataout <= n1ll1l OR (wire_n1lOOi_o AND (((nli0OOO XOR n1ll0l) OR (nli0OlO XOR n1ll1O)) OR (NOT (n1ll0l XOR n1ll1O)))); + wire_n1lO1l_dataout <= wire_n1lO1O_dataout AND NOT(nli0Oll); + wire_n1lO1O_dataout <= wire_n1lO0i_dataout OR (wire_w_lg_nlii10i2539w(0) AND wire_w_lg_w_lg_nlii11O2522w2540w(0)); + wire_n1O01i_dataout <= wire_n1O00i_o(2) AND nli0Oil; + wire_n1O01l_dataout <= wire_n1O00i_o(3) AND nli0Oil; + wire_n1O01O_dataout <= wire_n1O00i_o(4) AND nli0Oil; + wire_n1O0i_dataout <= wire_n1O0l_dataout OR (wire_w_lg_nlilOil361w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_n1liO363w365w367w368w(0) OR (wire_nl01l_w_lg_w_lg_n1liO370w371w(0) AND wire_nl01l_w_lg_n1l0O366w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_n1liO370w374w375w(0))); + wire_n1O0l_dataout <= wire_n1O0O_dataout OR (wire_w_lg_nlilOil361w(0) AND nlillii); + wire_n1O0O_dataout <= n1l1l OR (wire_n1OOi_o AND (((nlilO1O XOR n1l0l) OR (nlillOi XOR n1l1O)) OR (NOT (n1l0l XOR n1l1O)))); + wire_n1O1ii_dataout <= wire_n1O1ll_dataout OR nli0Oll; + wire_n1O1il_dataout <= wire_n1O1lO_dataout AND NOT(nli0Oll); + wire_n1O1iO_dataout <= wire_n1O1Oi_dataout OR nli0Oll; + wire_n1O1l_dataout <= wire_n1O1O_dataout AND NOT(nlilllO); + wire_n1O1li_dataout <= wire_n1O1Ol_dataout OR nli0Oll; + wire_n1O1ll_dataout <= wire_n1O1OO_dataout WHEN wire_w_lg_nli0Oii2486w(0) = '1' ELSE n1ll0O; + wire_n1O1lO_dataout <= wire_n1O01i_dataout WHEN wire_w_lg_nli0Oii2486w(0) = '1' ELSE n1llii; + wire_n1O1O_dataout <= wire_n1O0i_dataout OR (wire_w_lg_nlilOll378w(0) AND wire_w_lg_w_lg_nlilOil361w379w(0)); + wire_n1O1Oi_dataout <= wire_n1O01l_dataout WHEN wire_w_lg_nli0Oii2486w(0) = '1' ELSE n1llil; + wire_n1O1Ol_dataout <= wire_n1O01O_dataout WHEN wire_w_lg_nli0Oii2486w(0) = '1' ELSE n1lliO; + wire_n1O1OO_dataout <= wire_n1O00i_o(1) AND nli0Oil; + wire_n1Oili_dataout <= n1l00O WHEN nlii1li = '1' ELSE n0001l; + wire_n1Oill_dataout <= n000lO OR rate; + wire_n1OilO_dataout <= n1OlOO AND NOT(rate); + wire_n1OiOi_dataout <= n1OlOi WHEN rate = '1' ELSE n1OllO; + wire_n1OiOl_dataout <= (n1OO1i OR n1Ol1l) WHEN rate = '1' ELSE (n1OlOO OR n1Oi0O); + wire_ni00i_dataout <= wire_ni0OO_dataout AND NOT(n0Oll); + wire_ni00l_dataout <= wire_nii1i_dataout AND NOT(n0Oll); + wire_ni00O_dataout <= wire_nii1l_dataout AND NOT(n0Oll); + wire_ni01i_dataout <= wire_ni0lO_dataout AND NOT(n0Oll); + wire_ni01l_dataout <= wire_ni0Oi_dataout AND NOT(n0Oll); + wire_ni01O_dataout <= wire_ni0Ol_dataout AND NOT(n0Oll); + wire_ni0ii_dataout <= wire_nii1O_dataout AND NOT(n0Oll); + wire_ni0il_dataout <= wire_nii0i_dataout AND NOT(n0Oll); + wire_ni0iO_dataout <= wire_nii0l_dataout AND NOT(n0Oll); + wire_ni0l0i_dataout <= wire_ni0lil_dataout AND NOT(ni0iOi); + wire_ni0l0l_dataout <= wire_ni0liO_dataout OR ni0iOi; + wire_ni0l0O_dataout <= wire_ni0lli_dataout AND NOT(ni0iOi); + wire_ni0l1O_dataout <= ni0llO OR wire_nliii_w_lg_niOO1l1483w(0); + wire_ni0li_dataout <= wire_nii0O_dataout AND NOT(n0Oll); + wire_ni0lii_dataout <= wire_ni0lll_dataout AND NOT(ni0iOi); + wire_ni0lil_dataout <= ni0ili AND NOT(niOO1l); + wire_ni0liO_dataout <= ni0ill AND NOT(niOO1l); + wire_ni0ll_dataout <= wire_niiii_dataout AND NOT(n0Oll); + wire_ni0lli_dataout <= ni0ilO OR niOO1l; + wire_ni0lll_dataout <= ni0llO AND NOT(niOO1l); + wire_ni0lO_dataout <= n0i0O OR nliO01i; + wire_ni0Oi_dataout <= n0l1l OR nliO01l; + wire_ni0Ol_dataout <= wire_niiil_o(0) WHEN n0OOl = '1' ELSE n0l1O; + wire_ni0OO_dataout <= wire_niiil_o(1) WHEN n0OOl = '1' ELSE n0l0i; + wire_ni100i_dataout <= wire_ni100l_o(6) AND NOT(n0O1Ol); + wire_ni100O_dataout <= wire_ni10Oi_o(0) AND NOT(n0O1OO); + wire_ni101i_dataout <= wire_ni100l_o(3) AND NOT(n0O1Ol); + wire_ni101l_dataout <= wire_ni100l_o(4) AND NOT(n0O1Ol); + wire_ni101O_dataout <= wire_ni100l_o(5) AND NOT(n0O1Ol); + wire_ni10ii_dataout <= wire_ni10Oi_o(1) AND NOT(n0O1OO); + wire_ni10il_dataout <= wire_ni10Oi_o(2) AND NOT(n0O1OO); + wire_ni10iO_dataout <= wire_ni10Oi_o(3) AND NOT(n0O1OO); + wire_ni10li_dataout <= wire_ni10Oi_o(4) AND NOT(n0O1OO); + wire_ni10ll_dataout <= wire_ni10Oi_o(5) AND NOT(n0O1OO); + wire_ni10lO_dataout <= wire_ni10Oi_o(6) AND NOT(n0O1OO); + wire_ni10Ol_dataout <= n0iOOl AND enable_inf_ei(5); + wire_ni10OO_dataout <= n0iiiO AND enable_inf_ei(4); + wire_ni110i_dataout <= wire_ni11li_o(3) WHEN n0O01O = '1' ELSE n0O1il; + wire_ni110l_dataout <= wire_ni11li_o(4) WHEN n0O01O = '1' ELSE n0O1iO; + wire_ni110O_dataout <= wire_ni11li_o(5) WHEN n0O01O = '1' ELSE n0O1li; + wire_ni111i_dataout <= wire_ni11li_o(0) WHEN n0O01O = '1' ELSE n0O10l; + wire_ni111l_dataout <= wire_ni11li_o(1) WHEN n0O01O = '1' ELSE n0O10O; + wire_ni111O_dataout <= wire_ni11li_o(2) WHEN n0O01O = '1' ELSE n0O1ii; + wire_ni11ii_dataout <= wire_ni11li_o(6) WHEN n0O01O = '1' ELSE n0O1ll; + wire_ni11il_dataout <= wire_ni11li_o(7) WHEN n0O01O = '1' ELSE n0O1lO; + wire_ni11iO_dataout <= wire_ni11li_o(8) WHEN n0O01O = '1' ELSE n0O1Oi; + wire_ni11Oi_dataout <= wire_ni100l_o(0) AND NOT(n0O1Ol); + wire_ni11Ol_dataout <= wire_ni100l_o(1) AND NOT(n0O1Ol); + wire_ni11OO_dataout <= wire_ni100l_o(2) AND NOT(n0O1Ol); + wire_ni1i0i_dataout <= ni1i0l AND enable_inf_ei(0); + wire_ni1i0O_dataout <= ((wire_ni10OO_dataout OR wire_ni10Ol_dataout) OR wire_ni1i1i_dataout) WHEN rate = '1' ELSE ((wire_ni1i1O_dataout OR wire_ni1i1l_dataout) OR wire_ni1i0i_dataout); + wire_ni1i1i_dataout <= ni1i0l AND enable_inf_ei(3); + wire_ni1i1l_dataout <= n0iOOl AND enable_inf_ei(2); + wire_ni1i1O_dataout <= n0iiiO AND enable_inf_ei(1); + wire_ni1lll_dataout <= wire_nliii_w_lg_ni1lOi1701w(0) WHEN (ni1O1l XOR ni1O1i) = '1' ELSE ni1lOi; + wire_ni1O0l_dataout <= wire_nlO0lO_w_lg_ni1O1O1697w(0) WHEN (wire_w_lg_nliilil1698w(0) AND (rxupdatefc XOR ni1O0i)) = '1' ELSE ni1O1O; + wire_ni1Oil_dataout <= ni1O0i WHEN nliilil = '1' ELSE rxupdatefc; + wire_nii0i_dataout <= wire_niiil_o(5) WHEN n0OOl = '1' ELSE n0lil; + wire_nii0il_dataout <= wire_nii0iO_dataout AND NOT(nliiO1l); + wire_nii0iO_dataout <= wire_nii0li_dataout OR (wire_w_lg_nliiOli1466w(0) AND wire_w_lg_w_lg_nliiOiO1449w1467w(0)); + wire_nii0l_dataout <= wire_niiil_o(6) WHEN n0OOl = '1' ELSE n0liO; + wire_nii0li_dataout <= wire_nii0ll_dataout OR (wire_w_lg_nliiOiO1449w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_nii1OO1451w1453w1455w1456w(0) OR (wire_nl01l_w_lg_w_lg_nii1OO1458w1459w(0) AND wire_nl01l_w_lg_nii1lO1454w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_nii1OO1458w1462w1463w(0))); + wire_nii0ll_dataout <= wire_nii0lO_dataout OR (wire_w_lg_nliiOiO1449w(0) AND nliillO); + wire_nii0lO_dataout <= nii1il OR (wire_niii0i_o AND (((nliiO0O XOR nii1ll) OR (nliiO1O XOR nii1iO)) OR (NOT (nii1ll XOR nii1iO)))); + wire_nii0O_dataout <= wire_niiil_o(7) WHEN n0OOl = '1' ELSE n0lli; + wire_nii1i_dataout <= wire_niiil_o(2) WHEN n0OOl = '1' ELSE n0l0l; + wire_nii1l_dataout <= wire_niiil_o(3) WHEN n0OOl = '1' ELSE n0l0O; + wire_nii1O_dataout <= wire_niiil_o(4) WHEN n0OOl = '1' ELSE n0lii; + wire_niiii_dataout <= wire_niiil_o(8) WHEN n0OOl = '1' ELSE n0lll; + wire_niiiO_dataout <= wire_nilil_dataout AND NOT(n0OlO); + wire_niiiOi_dataout <= wire_niil1l_dataout OR nliiO1l; + wire_niiiOl_dataout <= wire_niil1O_dataout AND NOT(nliiO1l); + wire_niiiOO_dataout <= wire_niil0i_dataout OR nliiO1l; + wire_niil0i_dataout <= wire_niilil_dataout WHEN wire_w_lg_nliilOi1413w(0) = '1' ELSE nii1Ol; + wire_niil0l_dataout <= wire_niiliO_dataout WHEN wire_w_lg_nliilOi1413w(0) = '1' ELSE nii1OO; + wire_niil0O_dataout <= wire_niilli_o(1) AND nliilOl; + wire_niil1i_dataout <= wire_niil0l_dataout OR nliiO1l; + wire_niil1l_dataout <= wire_niil0O_dataout WHEN wire_w_lg_nliilOi1413w(0) = '1' ELSE nii1lO; + wire_niil1O_dataout <= wire_niilii_dataout WHEN wire_w_lg_nliilOi1413w(0) = '1' ELSE nii1Oi; + wire_niili_dataout <= wire_niliO_dataout AND NOT(n0OlO); + wire_niilii_dataout <= wire_niilli_o(2) AND nliilOl; + wire_niilil_dataout <= wire_niilli_o(3) AND nliilOl; + wire_niiliO_dataout <= wire_niilli_o(4) AND nliilOl; + wire_niill_dataout <= wire_nilli_dataout AND NOT(n0OlO); + wire_niilO_dataout <= wire_nilll_dataout AND NOT(n0OlO); + wire_niiOi_dataout <= wire_nillO_dataout AND NOT(n0OlO); + wire_niiOl_dataout <= wire_nilOi_dataout AND NOT(n0OlO); + wire_niiOO_dataout <= wire_nilOl_dataout AND NOT(n0OlO); + wire_nil0i_dataout <= wire_niO1O_dataout AND NOT(n0OlO); + wire_nil0l_dataout <= wire_niO0i_dataout AND NOT(n0OlO); + wire_nil0O_dataout <= wire_niO0l_dataout AND NOT(n0OlO); + wire_nil10i_dataout <= nil00i WHEN rate = '1' ELSE nil01O; + wire_nil10l_dataout <= (nil0ii OR nil1il) WHEN rate = '1' ELSE (nil00O OR niiOlO); + wire_nil11i_dataout <= ni0llO WHEN nlil11i = '1' ELSE niOlil; + wire_nil11l_dataout <= niOO1O OR rate; + wire_nil11O_dataout <= nil00O AND NOT(rate); + wire_nil1i_dataout <= wire_nilOO_dataout AND NOT(n0OlO); + wire_nil1l_dataout <= wire_niO1i_dataout AND NOT(n0OlO); + wire_nil1O_dataout <= wire_niO1l_dataout AND NOT(n0OlO); + wire_nilii_dataout <= wire_niO0O_dataout AND NOT(n0OlO); + wire_nilil_dataout <= n0llO OR nliO00i; + wire_niliO_dataout <= n0lOi OR nliO00l; + wire_nilli_dataout <= n0lOl OR nliO00O; + wire_nillii_dataout <= wire_nilO1O_dataout AND NOT(nili1l); + wire_nillil_dataout <= wire_nilO0i_dataout AND NOT(nili1l); + wire_nilliO_dataout <= wire_nilO0l_dataout AND NOT(nili1l); + wire_nilll_dataout <= n0lOO OR nliO0ii; + wire_nillli_dataout <= wire_nilO0O_dataout AND NOT(nili1l); + wire_nillll_dataout <= wire_nilOii_dataout AND NOT(nili1l); + wire_nilllO_dataout <= wire_nilOil_dataout AND NOT(nili1l); + wire_nillO_dataout <= n0O1i OR nliO0il; + wire_nillOi_dataout <= wire_nilOiO_dataout AND NOT(nili1l); + wire_nillOl_dataout <= wire_nilOli_dataout AND NOT(nili1l); + wire_nillOO_dataout <= wire_nilOll_dataout AND NOT(nili1l); + wire_nilO0i_dataout <= nil1il OR nlil10l; + wire_nilO0l_dataout <= wire_nilOOl_o(0) WHEN nili0l = '1' ELSE nil1iO; + wire_nilO0O_dataout <= wire_nilOOl_o(1) WHEN nili0l = '1' ELSE nil1li; + wire_nilO1i_dataout <= wire_nilOlO_dataout AND NOT(nili1l); + wire_nilO1l_dataout <= wire_nilOOi_dataout AND NOT(nili1l); + wire_nilO1O_dataout <= niiOlO OR nlil10i; + wire_nilOi_dataout <= wire_niOii_o(0) WHEN n0OOO = '1' ELSE n0O1l; + wire_nilOii_dataout <= wire_nilOOl_o(2) WHEN nili0l = '1' ELSE nil1ll; + wire_nilOil_dataout <= wire_nilOOl_o(3) WHEN nili0l = '1' ELSE nil1lO; + wire_nilOiO_dataout <= wire_nilOOl_o(4) WHEN nili0l = '1' ELSE nil1Oi; + wire_nilOl_dataout <= wire_niOii_o(1) WHEN n0OOO = '1' ELSE n0O1O; + wire_nilOli_dataout <= wire_nilOOl_o(5) WHEN nili0l = '1' ELSE nil1Ol; + wire_nilOll_dataout <= wire_nilOOl_o(6) WHEN nili0l = '1' ELSE nil1OO; + wire_nilOlO_dataout <= wire_nilOOl_o(7) WHEN nili0l = '1' ELSE nil01i; + wire_nilOO_dataout <= wire_niOii_o(2) WHEN n0OOO = '1' ELSE n0O0i; + wire_nilOOi_dataout <= wire_nilOOl_o(8) WHEN nili0l = '1' ELSE nil01l; + wire_nilOOO_dataout <= wire_niO1Ol_dataout AND NOT(nili1O); + wire_niO00i_dataout <= wire_niO0Oi_o(0) WHEN nili0O = '1' ELSE nil0il; + wire_niO00l_dataout <= wire_niO0Oi_o(1) WHEN nili0O = '1' ELSE nil0iO; + wire_niO00O_dataout <= wire_niO0Oi_o(2) WHEN nili0O = '1' ELSE nil0li; + wire_niO01i_dataout <= nil00l OR nlil1il; + wire_niO01l_dataout <= nil00O OR nlil1iO; + wire_niO01O_dataout <= nil0ii OR nlil1li; + wire_niO0i_dataout <= wire_niOii_o(6) WHEN n0OOO = '1' ELSE n0Oil; + wire_niO0ii_dataout <= wire_niO0Oi_o(3) WHEN nili0O = '1' ELSE nil0ll; + wire_niO0il_dataout <= wire_niO0Oi_o(4) WHEN nili0O = '1' ELSE nil0lO; + wire_niO0iO_dataout <= wire_niO0Oi_o(5) WHEN nili0O = '1' ELSE nil0Oi; + wire_niO0l_dataout <= wire_niOii_o(7) WHEN n0OOO = '1' ELSE n0OiO; + wire_niO0li_dataout <= wire_niO0Oi_o(6) WHEN nili0O = '1' ELSE nil0Ol; + wire_niO0ll_dataout <= wire_niO0Oi_o(7) WHEN nili0O = '1' ELSE nil0OO; + wire_niO0lO_dataout <= wire_niO0Oi_o(8) WHEN nili0O = '1' ELSE nili1i; + wire_niO0O_dataout <= wire_niOii_o(8) WHEN n0OOO = '1' ELSE n0Oli; + wire_niO10i_dataout <= wire_niO01O_dataout AND NOT(nili1O); + wire_niO10l_dataout <= wire_niO00i_dataout AND NOT(nili1O); + wire_niO10O_dataout <= wire_niO00l_dataout AND NOT(nili1O); + wire_niO11i_dataout <= wire_niO1OO_dataout AND NOT(nili1O); + wire_niO11l_dataout <= wire_niO01i_dataout AND NOT(nili1O); + wire_niO11O_dataout <= wire_niO01l_dataout AND NOT(nili1O); + wire_niO1i_dataout <= wire_niOii_o(3) WHEN n0OOO = '1' ELSE n0O0l; + wire_niO1ii_dataout <= wire_niO00O_dataout AND NOT(nili1O); + wire_niO1il_dataout <= wire_niO0ii_dataout AND NOT(nili1O); + wire_niO1iO_dataout <= wire_niO0il_dataout AND NOT(nili1O); + wire_niO1l_dataout <= wire_niOii_o(4) WHEN n0OOO = '1' ELSE n0O0O; + wire_niO1li_dataout <= wire_niO0iO_dataout AND NOT(nili1O); + wire_niO1ll_dataout <= wire_niO0li_dataout AND NOT(nili1O); + wire_niO1lO_dataout <= wire_niO0ll_dataout AND NOT(nili1O); + wire_niO1O_dataout <= wire_niOii_o(5) WHEN n0OOO = '1' ELSE n0Oii; + wire_niO1Oi_dataout <= wire_niO0lO_dataout AND NOT(nili1O); + wire_niO1Ol_dataout <= nil01O OR nlil10O; + wire_niO1OO_dataout <= nil00i OR nlil1ii; + wire_niOi0i_dataout <= wire_niOiil_o(3) AND NOT(nili1l); + wire_niOi0l_dataout <= wire_niOiil_o(4) AND NOT(nili1l); + wire_niOi0O_dataout <= wire_niOiil_o(5) AND NOT(nili1l); + wire_niOi1i_dataout <= wire_niOiil_o(0) AND NOT(nili1l); + wire_niOi1l_dataout <= wire_niOiil_o(1) AND NOT(nili1l); + wire_niOi1O_dataout <= wire_niOiil_o(2) AND NOT(nili1l); + wire_niOiii_dataout <= wire_niOiil_o(6) AND NOT(nili1l); + wire_niOiiO_dataout <= wire_niOl1i_o(0) AND NOT(nili1O); + wire_niOili_dataout <= wire_niOl1i_o(1) AND NOT(nili1O); + wire_niOill_dataout <= wire_niOl1i_o(2) AND NOT(nili1O); + wire_niOilO_dataout <= wire_niOl1i_o(3) AND NOT(nili1O); + wire_niOiOi_dataout <= wire_niOl1i_o(4) AND NOT(nili1O); + wire_niOiOl_dataout <= wire_niOl1i_o(5) AND NOT(nili1O); + wire_niOiOO_dataout <= wire_niOl1i_o(6) AND NOT(nili1O); + wire_niOl0i_dataout <= niOlil AND enable_inf_ei(3); + wire_niOl0l_dataout <= nii01l AND enable_inf_ei(2); + wire_niOl0O_dataout <= ni0llO AND enable_inf_ei(1); + wire_niOl1l_dataout <= nii01l AND enable_inf_ei(5); + wire_niOl1O_dataout <= ni0llO AND enable_inf_ei(4); + wire_niOli_dataout <= wire_nl11l_o(0) AND NOT(n0Oll); + wire_niOlii_dataout <= niOlil AND enable_inf_ei(0); + wire_niOliO_dataout <= ((wire_niOl1O_dataout OR wire_niOl1l_dataout) OR wire_niOl0i_dataout) WHEN rate = '1' ELSE ((wire_niOl0O_dataout OR wire_niOl0l_dataout) OR wire_niOlii_dataout); + wire_niOll_dataout <= wire_nl11l_o(1) AND NOT(n0Oll); + wire_niOlO_dataout <= wire_nl11l_o(2) AND NOT(n0Oll); + wire_niOOi_dataout <= wire_nl11l_o(3) AND NOT(n0Oll); + wire_niOOl_dataout <= wire_nl11l_o(4) AND NOT(n0Oll); + wire_niOOO_dataout <= wire_nl11l_o(5) AND NOT(n0Oll); + wire_niOOOl_dataout <= wire_nliii_w_lg_nl111i1164w(0) WHEN (nl110l XOR nl110i) = '1' ELSE nl111i; + wire_nl00i_dataout <= (((wire_nl1lO_dataout OR wire_nl1ll_dataout) OR (NOT (nliOi1l6 XOR nliOi1l5))) OR wire_nl1Oi_dataout) WHEN rate = '1' ELSE (((wire_nl1OO_dataout OR wire_nl1Ol_dataout) OR (NOT (nliOi0i4 XOR nliOi0i3))) OR wire_nl01i_dataout); + wire_nl01i_dataout <= nl01O AND enable_inf_ei(0); + wire_nl0ill_dataout <= wire_nl0ilO_dataout AND NOT(nlil00l); + wire_nl0ilO_dataout <= wire_nl0iOi_dataout OR (wire_w_lg_nlil0Oi930w(0) AND wire_w_lg_w_lg_nlil0lO913w931w(0)); + wire_nl0iOi_dataout <= wire_nl0iOl_dataout OR (wire_w_lg_nlil0lO913w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_nl0i1O915w917w919w920w(0) OR (wire_nl01l_w_lg_w_lg_nl0i1O922w923w(0) AND wire_nl01l_w_lg_nl00OO918w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_nl0i1O922w926w927w(0))); + wire_nl0iOl_dataout <= wire_nl0iOO_dataout OR (wire_w_lg_nlil0lO913w(0) AND nlil1OO); + wire_nl0iOO_dataout <= nl00ll OR (wire_nl0lii_o AND (((nlil0iO XOR nl00Ol) OR (nlil00O XOR nl00lO)) OR (NOT (nl00Ol XOR nl00lO)))); + wire_nl0O0i_dataout <= wire_nl0Oil_dataout OR nlil00l; + wire_nl0O0l_dataout <= wire_nl0OiO_dataout WHEN wire_w_lg_nlil01i877w(0) = '1' ELSE nl00OO; + wire_nl0O0O_dataout <= wire_nl0Oli_dataout WHEN wire_w_lg_nlil01i877w(0) = '1' ELSE nl0i1i; + wire_nl0O1i_dataout <= wire_nl0O0l_dataout OR nlil00l; + wire_nl0O1l_dataout <= wire_nl0O0O_dataout AND NOT(nlil00l); + wire_nl0O1O_dataout <= wire_nl0Oii_dataout OR nlil00l; + wire_nl0Oii_dataout <= wire_nl0Oll_dataout WHEN wire_w_lg_nlil01i877w(0) = '1' ELSE nl0i1l; + wire_nl0Oil_dataout <= wire_nl0OlO_dataout WHEN wire_w_lg_nlil01i877w(0) = '1' ELSE nl0i1O; + wire_nl0OiO_dataout <= wire_nl0OOi_o(1) AND nlil01l; + wire_nl0Oli_dataout <= wire_nl0OOi_o(2) AND nlil01l; + wire_nl0Oll_dataout <= wire_nl0OOi_o(3) AND nlil01l; + wire_nl0OlO_dataout <= wire_nl0OOi_o(4) AND nlil01l; + wire_nl10i_dataout <= wire_nl1li_o(1) AND NOT(n0OlO); + wire_nl10l_dataout <= wire_nl1li_o(2) AND NOT(n0OlO); + wire_nl10O_dataout <= wire_nl1li_o(3) AND NOT(n0OlO); + wire_nl11i_dataout <= wire_nl11l_o(6) AND NOT(n0Oll); + wire_nl11il_dataout <= wire_nlO0lO_w_lg_nl110O1160w(0) WHEN (wire_w_lg_nlil1ll1161w(0) AND (rxupdatefc XOR nl11ii)) = '1' ELSE nl110O; + wire_nl11ll_dataout <= nl11ii WHEN nlil1ll = '1' ELSE rxupdatefc; + wire_nl11O_dataout <= wire_nl1li_o(0) AND NOT(n0OlO); + wire_nl1ii_dataout <= wire_nl1li_o(4) AND NOT(n0OlO); + wire_nl1il_dataout <= wire_nl1li_o(5) AND NOT(n0OlO); + wire_nl1iO_dataout <= wire_nl1li_o(6) AND NOT(n0OlO); + wire_nl1ll_dataout <= n1lll AND enable_inf_ei(5); + wire_nl1lO_dataout <= n100O AND enable_inf_ei(4); + wire_nl1O0O_dataout <= nl1OOO OR wire_nliii_w_lg_nlO10l946w(0); + wire_nl1Oi_dataout <= nl01O AND enable_inf_ei(3); + wire_nl1Oii_dataout <= wire_nl1Oll_dataout AND NOT(nl1O1i); + wire_nl1Oil_dataout <= wire_nl1OlO_dataout OR nl1O1i; + wire_nl1OiO_dataout <= wire_nl1OOi_dataout AND NOT(nl1O1i); + wire_nl1Ol_dataout <= n1lll AND enable_inf_ei(2); + wire_nl1Oli_dataout <= wire_nl1OOl_dataout AND NOT(nl1O1i); + wire_nl1Oll_dataout <= nl1lOi AND NOT(nlO10l); + wire_nl1OlO_dataout <= nl1lOl AND NOT(nlO10l); + wire_nl1OO_dataout <= n100O AND enable_inf_ei(1); + wire_nl1OOi_dataout <= nl1lOO OR nlO10l; + wire_nl1OOl_dataout <= nl1OOO AND NOT(nlO10l); + wire_nli00i_dataout <= nl1OOO WHEN nlili0i = '1' ELSE nllOll; + wire_nli00l_dataout <= nlO10O OR rate; + wire_nli00O_dataout <= nliiiO AND NOT(rate); + wire_nli0ii_dataout <= nliiii WHEN rate = '1' ELSE nlii0O; + wire_nli0il_dataout <= (nliili OR nli0ll) WHEN rate = '1' ELSE (nliiiO OR nli1OO); + wire_nliOill_dataout <= wire_nliii_w_lg_nliOiOi4386w(0) WHEN (nliOl1l XOR nliOl1i) = '1' ELSE nliOiOi; + wire_nliOl0l_dataout <= wire_nlO0lO_w_lg_nliOl1O4382w(0) WHEN (wire_w_lg_nli1i0O4383w(0) AND (rxupdatefc XOR nliOl0i)) = '1' ELSE nliOl1O; + wire_nliOli_dataout <= wire_nll10O_dataout AND NOT(nlil0l); + wire_nliOlil_dataout <= nliOl0i WHEN nli1i0O = '1' ELSE rxupdatefc; + wire_nliOll_dataout <= wire_nll1ii_dataout AND NOT(nlil0l); + wire_nliOlO_dataout <= wire_nll1il_dataout AND NOT(nlil0l); + wire_nliOOi_dataout <= wire_nll1iO_dataout AND NOT(nlil0l); + wire_nliOOl_dataout <= wire_nll1li_dataout AND NOT(nlil0l); + wire_nliOOO_dataout <= wire_nll1ll_dataout AND NOT(nlil0l); + wire_nll00i_dataout <= wire_nlli1O_dataout AND NOT(nlil0O); + wire_nll00l_dataout <= wire_nlli0i_dataout AND NOT(nlil0O); + wire_nll00O_dataout <= wire_nlli0l_dataout AND NOT(nlil0O); + wire_nll00Oi_dataout <= wire_nll0i1l_dataout OR nli1iOO; + wire_nll00Ol_dataout <= wire_nll0i1O_dataout AND NOT(nli1iOO); + wire_nll00OO_dataout <= wire_nll0i0i_dataout OR nli1iOO; + wire_nll01i_dataout <= wire_nll01l_o(8) WHEN nlilil = '1' ELSE nlii0l; + wire_nll01il_dataout <= wire_nll01iO_dataout AND NOT(nli1iOO); + wire_nll01iO_dataout <= wire_nll01li_dataout OR (wire_w_lg_nli1lil4151w(0) AND wire_w_lg_w_lg_nli1lii4134w4152w(0)); + wire_nll01li_dataout <= wire_nll01ll_dataout OR (wire_w_lg_nli1lii4134w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_nll1OOO4136w4138w4140w4141w(0) OR (wire_nl01l_w_lg_w_lg_nll1OOO4143w4144w(0) AND wire_nl01l_w_lg_nll1OlO4139w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_nll1OOO4143w4147w4148w(0))); + wire_nll01ll_dataout <= wire_nll01lO_dataout OR (wire_w_lg_nli1lii4134w(0) AND nli1ili); + wire_nll01lO_dataout <= nll1Oil OR (wire_nll000i_o AND (((nli1l0i XOR nll1Oll) OR (nli1l1i XOR nll1OiO)) OR (NOT (nll1Oll XOR nll1OiO)))); + wire_nll01O_dataout <= wire_nlli1l_dataout AND NOT(nlil0O); + wire_nll0i0i_dataout <= wire_nll0iil_dataout WHEN wire_w_lg_nli1ill4098w(0) = '1' ELSE nll1OOl; + wire_nll0i0l_dataout <= wire_nll0iiO_dataout WHEN wire_w_lg_nli1ill4098w(0) = '1' ELSE nll1OOO; + wire_nll0i0O_dataout <= wire_nll0ili_o(1) AND nli1ilO; + wire_nll0i1i_dataout <= wire_nll0i0l_dataout OR nli1iOO; + wire_nll0i1l_dataout <= wire_nll0i0O_dataout WHEN wire_w_lg_nli1ill4098w(0) = '1' ELSE nll1OlO; + wire_nll0i1O_dataout <= wire_nll0iii_dataout WHEN wire_w_lg_nli1ill4098w(0) = '1' ELSE nll1OOi; + wire_nll0ii_dataout <= wire_nlli0O_dataout AND NOT(nlil0O); + wire_nll0iii_dataout <= wire_nll0ili_o(2) AND nli1ilO; + wire_nll0iil_dataout <= wire_nll0ili_o(3) AND nli1ilO; + wire_nll0iiO_dataout <= wire_nll0ili_o(4) AND nli1ilO; + wire_nll0il_dataout <= wire_nlliii_dataout AND NOT(nlil0O); + wire_nll0iO_dataout <= wire_nlliil_dataout AND NOT(nlil0O); + wire_nll0li_dataout <= wire_nlliiO_dataout AND NOT(nlil0O); + wire_nll0ll_dataout <= wire_nllili_dataout AND NOT(nlil0O); + wire_nll0lO_dataout <= wire_nllill_dataout AND NOT(nlil0O); + wire_nll0O0i_dataout <= nlli10i WHEN rate = '1' ELSE nlli11O; + wire_nll0O0l_dataout <= (nlli1ii OR nll0Oil) WHEN rate = '1' ELSE (nlli10O OR nll0llO); + wire_nll0O1i_dataout <= nll1ilO WHEN nli1lOl = '1' ELSE nllliil; + wire_nll0O1l_dataout <= nllll1O OR rate; + wire_nll0O1O_dataout <= nlli10O AND NOT(rate); + wire_nll0Oi_dataout <= wire_nllilO_dataout AND NOT(nlil0O); + wire_nll0Ol_dataout <= wire_nlliOi_dataout AND NOT(nlil0O); + wire_nll0OO_dataout <= wire_nlliOl_dataout AND NOT(nlil0O); + wire_nll10i_dataout <= wire_nll1OO_dataout AND NOT(nlil0l); + wire_nll10l_dataout <= wire_nll01i_dataout AND NOT(nlil0l); + wire_nll10O_dataout <= nli1OO OR nliliii; + wire_nll11i_dataout <= wire_nll1lO_dataout AND NOT(nlil0l); + wire_nll11l_dataout <= wire_nll1Oi_dataout AND NOT(nlil0l); + wire_nll11O_dataout <= wire_nll1Ol_dataout AND NOT(nlil0l); + wire_nll1i0i_dataout <= wire_nll1iil_dataout AND NOT(nll10Oi); + wire_nll1i0l_dataout <= wire_nll1iiO_dataout OR nll10Oi; + wire_nll1i0O_dataout <= wire_nll1ili_dataout AND NOT(nll10Oi); + wire_nll1i1O_dataout <= nll1ilO OR wire_nliii_w_lg_nllll1l4168w(0); + wire_nll1ii_dataout <= nli0ll OR nliliil; + wire_nll1iii_dataout <= wire_nll1ill_dataout AND NOT(nll10Oi); + wire_nll1iil_dataout <= nll10li AND NOT(nllll1l); + wire_nll1iiO_dataout <= nll10ll AND NOT(nllll1l); + wire_nll1il_dataout <= wire_nll01l_o(0) WHEN nlilil = '1' ELSE nli0lO; + wire_nll1ili_dataout <= nll10lO OR nllll1l; + wire_nll1ill_dataout <= nll1ilO AND NOT(nllll1l); + wire_nll1iO_dataout <= wire_nll01l_o(1) WHEN nlilil = '1' ELSE nli0Oi; + wire_nll1li_dataout <= wire_nll01l_o(2) WHEN nlilil = '1' ELSE nli0Ol; + wire_nll1ll_dataout <= wire_nll01l_o(3) WHEN nlilil = '1' ELSE nli0OO; + wire_nll1lO_dataout <= wire_nll01l_o(4) WHEN nlilil = '1' ELSE nlii1i; + wire_nll1Oi_dataout <= wire_nll01l_o(5) WHEN nlilil = '1' ELSE nlii1l; + wire_nll1Ol_dataout <= wire_nll01l_o(6) WHEN nlilil = '1' ELSE nlii1O; + wire_nll1OO_dataout <= wire_nll01l_o(7) WHEN nlilil = '1' ELSE nlii0i; + wire_nlli0i_dataout <= nliiil OR nlilill; + wire_nlli0l_dataout <= nliiiO OR nlililO; + wire_nlli0O_dataout <= nliili OR nliliOi; + wire_nlli1i_dataout <= wire_nlliOO_dataout AND NOT(nlil0O); + wire_nlli1l_dataout <= nlii0O OR nliliiO; + wire_nlli1O_dataout <= nliiii OR nlilili; + wire_nlliii_dataout <= wire_nlll1i_o(0) WHEN nliliO = '1' ELSE nliill; + wire_nlliiii_dataout <= wire_nllil1O_dataout AND NOT(nlli01l); + wire_nlliiil_dataout <= wire_nllil0i_dataout AND NOT(nlli01l); + wire_nlliiiO_dataout <= wire_nllil0l_dataout AND NOT(nlli01l); + wire_nlliil_dataout <= wire_nlll1i_o(1) WHEN nliliO = '1' ELSE nliilO; + wire_nlliili_dataout <= wire_nllil0O_dataout AND NOT(nlli01l); + wire_nlliill_dataout <= wire_nllilii_dataout AND NOT(nlli01l); + wire_nlliilO_dataout <= wire_nllilil_dataout AND NOT(nlli01l); + wire_nlliiO_dataout <= wire_nlll1i_o(2) WHEN nliliO = '1' ELSE nliiOi; + wire_nlliiOi_dataout <= wire_nlliliO_dataout AND NOT(nlli01l); + wire_nlliiOl_dataout <= wire_nllilli_dataout AND NOT(nlli01l); + wire_nlliiOO_dataout <= wire_nllilll_dataout AND NOT(nlli01l); + wire_nllil0i_dataout <= nll0Oil OR nli1O1O; + wire_nllil0l_dataout <= wire_nllilOl_o(0) WHEN nlli00l = '1' ELSE nll0OiO; + wire_nllil0O_dataout <= wire_nllilOl_o(1) WHEN nlli00l = '1' ELSE nll0Oli; + wire_nllil1i_dataout <= wire_nllillO_dataout AND NOT(nlli01l); + wire_nllil1l_dataout <= wire_nllilOi_dataout AND NOT(nlli01l); + wire_nllil1O_dataout <= nll0llO OR nli1O1l; + wire_nllili_dataout <= wire_nlll1i_o(3) WHEN nliliO = '1' ELSE nliiOl; + wire_nllilii_dataout <= wire_nllilOl_o(2) WHEN nlli00l = '1' ELSE nll0Oll; + wire_nllilil_dataout <= wire_nllilOl_o(3) WHEN nlli00l = '1' ELSE nll0OlO; + wire_nlliliO_dataout <= wire_nllilOl_o(4) WHEN nlli00l = '1' ELSE nll0OOi; + wire_nllill_dataout <= wire_nlll1i_o(4) WHEN nliliO = '1' ELSE nliiOO; + wire_nllilli_dataout <= wire_nllilOl_o(5) WHEN nlli00l = '1' ELSE nll0OOl; + wire_nllilll_dataout <= wire_nllilOl_o(6) WHEN nlli00l = '1' ELSE nll0OOO; + wire_nllillO_dataout <= wire_nllilOl_o(7) WHEN nlli00l = '1' ELSE nlli11i; + wire_nllilO_dataout <= wire_nlll1i_o(5) WHEN nliliO = '1' ELSE nlil1i; + wire_nllilOi_dataout <= wire_nllilOl_o(8) WHEN nlli00l = '1' ELSE nlli11l; + wire_nllilOO_dataout <= wire_nlliOOl_dataout AND NOT(nlli01O); + wire_nlliO0i_dataout <= wire_nlll11O_dataout AND NOT(nlli01O); + wire_nlliO0l_dataout <= wire_nlll10i_dataout AND NOT(nlli01O); + wire_nlliO0O_dataout <= wire_nlll10l_dataout AND NOT(nlli01O); + wire_nlliO1i_dataout <= wire_nlliOOO_dataout AND NOT(nlli01O); + wire_nlliO1l_dataout <= wire_nlll11i_dataout AND NOT(nlli01O); + wire_nlliO1O_dataout <= wire_nlll11l_dataout AND NOT(nlli01O); + wire_nlliOi_dataout <= wire_nlll1i_o(6) WHEN nliliO = '1' ELSE nlil1l; + wire_nlliOii_dataout <= wire_nlll10O_dataout AND NOT(nlli01O); + wire_nlliOil_dataout <= wire_nlll1ii_dataout AND NOT(nlli01O); + wire_nlliOiO_dataout <= wire_nlll1il_dataout AND NOT(nlli01O); + wire_nlliOl_dataout <= wire_nlll1i_o(7) WHEN nliliO = '1' ELSE nlil1O; + wire_nlliOli_dataout <= wire_nlll1iO_dataout AND NOT(nlli01O); + wire_nlliOll_dataout <= wire_nlll1li_dataout AND NOT(nlli01O); + wire_nlliOlO_dataout <= wire_nlll1ll_dataout AND NOT(nlli01O); + wire_nlliOO_dataout <= wire_nlll1i_o(8) WHEN nliliO = '1' ELSE nlil0i; + wire_nlliOOi_dataout <= wire_nlll1lO_dataout AND NOT(nlli01O); + wire_nlliOOl_dataout <= nlli11O OR nli1O0i; + wire_nlliOOO_dataout <= nlli10i OR nli1O0l; + wire_nlll00i_dataout <= wire_nlll0il_o(3) AND NOT(nlli01l); + wire_nlll00l_dataout <= wire_nlll0il_o(4) AND NOT(nlli01l); + wire_nlll00O_dataout <= wire_nlll0il_o(5) AND NOT(nlli01l); + wire_nlll01i_dataout <= wire_nlll0il_o(0) AND NOT(nlli01l); + wire_nlll01l_dataout <= wire_nlll0il_o(1) AND NOT(nlli01l); + wire_nlll01O_dataout <= wire_nlll0il_o(2) AND NOT(nlli01l); + wire_nlll0i_dataout <= wire_nlllll_o(0) AND NOT(nlil0l); + wire_nlll0ii_dataout <= wire_nlll0il_o(6) AND NOT(nlli01l); + wire_nlll0iO_dataout <= wire_nllli1i_o(0) AND NOT(nlli01O); + wire_nlll0l_dataout <= wire_nlllll_o(1) AND NOT(nlil0l); + wire_nlll0li_dataout <= wire_nllli1i_o(1) AND NOT(nlli01O); + wire_nlll0ll_dataout <= wire_nllli1i_o(2) AND NOT(nlli01O); + wire_nlll0lO_dataout <= wire_nllli1i_o(3) AND NOT(nlli01O); + wire_nlll0O_dataout <= wire_nlllll_o(2) AND NOT(nlil0l); + wire_nlll0Oi_dataout <= wire_nllli1i_o(4) AND NOT(nlli01O); + wire_nlll0Ol_dataout <= wire_nllli1i_o(5) AND NOT(nlli01O); + wire_nlll0OO_dataout <= wire_nllli1i_o(6) AND NOT(nlli01O); + wire_nlll10i_dataout <= wire_nlll1Oi_o(0) WHEN nlli00O = '1' ELSE nlli1il; + wire_nlll10l_dataout <= wire_nlll1Oi_o(1) WHEN nlli00O = '1' ELSE nlli1iO; + wire_nlll10O_dataout <= wire_nlll1Oi_o(2) WHEN nlli00O = '1' ELSE nlli1li; + wire_nlll11i_dataout <= nlli10l OR nli1O0O; + wire_nlll11l_dataout <= nlli10O OR nli1Oii; + wire_nlll11O_dataout <= nlli1ii OR nli1Oil; + wire_nlll1ii_dataout <= wire_nlll1Oi_o(3) WHEN nlli00O = '1' ELSE nlli1ll; + wire_nlll1il_dataout <= wire_nlll1Oi_o(4) WHEN nlli00O = '1' ELSE nlli1lO; + wire_nlll1iO_dataout <= wire_nlll1Oi_o(5) WHEN nlli00O = '1' ELSE nlli1Oi; + wire_nlll1li_dataout <= wire_nlll1Oi_o(6) WHEN nlli00O = '1' ELSE nlli1Ol; + wire_nlll1ll_dataout <= wire_nlll1Oi_o(7) WHEN nlli00O = '1' ELSE nlli1OO; + wire_nlll1lO_dataout <= wire_nlll1Oi_o(8) WHEN nlli00O = '1' ELSE nlli01i; + wire_nllli0i_dataout <= nllliil AND enable_inf_ei(3); + wire_nllli0l_dataout <= nll011l AND enable_inf_ei(2); + wire_nllli0O_dataout <= nll1ilO AND enable_inf_ei(1); + wire_nllli1l_dataout <= nll011l AND enable_inf_ei(5); + wire_nllli1O_dataout <= nll1ilO AND enable_inf_ei(4); + wire_nlllii_dataout <= wire_nlllll_o(3) AND NOT(nlil0l); + wire_nllliii_dataout <= nllliil AND enable_inf_ei(0); + wire_nllliiO_dataout <= ((wire_nllli1O_dataout OR wire_nllli1l_dataout) OR wire_nllli0i_dataout) WHEN rate = '1' ELSE ((wire_nllli0O_dataout OR wire_nllli0l_dataout) OR wire_nllliii_dataout); + wire_nlllil_dataout <= wire_nlllll_o(4) AND NOT(nlil0l); + wire_nllliO_dataout <= wire_nlllll_o(5) AND NOT(nlil0l); + wire_nlllli_dataout <= wire_nlllll_o(6) AND NOT(nlil0l); + wire_nllllO_dataout <= wire_nllO0i_o(0) AND NOT(nlil0O); + wire_nllllOl_dataout <= wire_nliii_w_lg_nlllO1i3849w(0) WHEN (nlllO0l XOR nlllO0i) = '1' ELSE nlllO1i; + wire_nlllOi_dataout <= wire_nllO0i_o(1) AND NOT(nlil0O); + wire_nlllOil_dataout <= wire_nlO0lO_w_lg_nlllO0O3845w(0) WHEN (wire_w_lg_nli1OiO3846w(0) AND (rxupdatefc XOR nlllOii)) = '1' ELSE nlllO0O; + wire_nlllOl_dataout <= wire_nllO0i_o(2) AND NOT(nlil0O); + wire_nlllOll_dataout <= nlllOii WHEN nli1OiO = '1' ELSE rxupdatefc; + wire_nlllOO_dataout <= wire_nllO0i_o(3) AND NOT(nlil0O); + wire_nllO0l_dataout <= nl0i0l AND enable_inf_ei(5); + wire_nllO0O_dataout <= nl1OOO AND enable_inf_ei(4); + wire_nllO1i_dataout <= wire_nllO0i_o(4) AND NOT(nlil0O); + wire_nllO1l_dataout <= wire_nllO0i_o(5) AND NOT(nlil0O); + wire_nllO1O_dataout <= wire_nllO0i_o(6) AND NOT(nlil0O); + wire_nllOii_dataout <= nllOll AND enable_inf_ei(3); + wire_nllOil_dataout <= nl0i0l AND enable_inf_ei(2); + wire_nllOiO_dataout <= nl1OOO AND enable_inf_ei(1); + wire_nllOl0O_dataout <= nllOlOO OR wire_nliii_w_lg_nlOiO0l3631w(0); + wire_nllOli_dataout <= nllOll AND enable_inf_ei(0); + wire_nllOlii_dataout <= wire_nllOlll_dataout AND NOT(nllOl1i); + wire_nllOlil_dataout <= wire_nllOllO_dataout OR nllOl1i; + wire_nllOliO_dataout <= wire_nllOlOi_dataout AND NOT(nllOl1i); + wire_nllOlli_dataout <= wire_nllOlOl_dataout AND NOT(nllOl1i); + wire_nllOlll_dataout <= nllOiOi AND NOT(nlOiO0l); + wire_nllOllO_dataout <= nllOiOl AND NOT(nlOiO0l); + wire_nllOlO_dataout <= ((wire_nllO0O_dataout OR wire_nllO0l_dataout) OR wire_nllOii_dataout) WHEN rate = '1' ELSE ((wire_nllOiO_dataout OR wire_nllOil_dataout) OR wire_nllOli_dataout); + wire_nllOlOi_dataout <= nllOiOO OR nlOiO0l; + wire_nllOlOl_dataout <= nllOlOO AND NOT(nlOiO0l); + wire_nlO010i_dataout <= nllOlOO WHEN nli001l = '1' ELSE nlOilll; + wire_nlO010l_dataout <= nlOiO0O OR rate; + wire_nlO010O_dataout <= nlO00iO AND NOT(rate); + wire_nlO01ii_dataout <= nlO00ii WHEN rate = '1' ELSE nlO000O; + wire_nlO01il_dataout <= (nlO00li OR nlO01ll) WHEN rate = '1' ELSE (nlO00iO OR nlO1OOO); + wire_nlO01O_dataout <= wire_nliii_w_lg_nlO00l627w(0) WHEN (nlO0li XOR nlO0iO) = '1' ELSE nlO00l; + wire_nlO0lli_dataout <= wire_nlO0O0O_dataout AND NOT(nlO0i0l); + wire_nlO0lll_dataout <= wire_nlO0Oii_dataout AND NOT(nlO0i0l); + wire_nlO0llO_dataout <= wire_nlO0Oil_dataout AND NOT(nlO0i0l); + wire_nlO0lOi_dataout <= wire_nlO0OiO_dataout AND NOT(nlO0i0l); + wire_nlO0lOl_dataout <= wire_nlO0Oli_dataout AND NOT(nlO0i0l); + wire_nlO0lOO_dataout <= wire_nlO0Oll_dataout AND NOT(nlO0i0l); + wire_nlO0O0i_dataout <= wire_nlO0OOO_dataout AND NOT(nlO0i0l); + wire_nlO0O0l_dataout <= wire_nlOi11i_dataout AND NOT(nlO0i0l); + wire_nlO0O0O_dataout <= nlO1OOO OR nli000l; + wire_nlO0O1i_dataout <= wire_nlO0OlO_dataout AND NOT(nlO0i0l); + wire_nlO0O1l_dataout <= wire_nlO0OOi_dataout AND NOT(nlO0i0l); + wire_nlO0O1O_dataout <= wire_nlO0OOl_dataout AND NOT(nlO0i0l); + wire_nlO0Oii_dataout <= nlO01ll OR nli000O; + wire_nlO0Oil_dataout <= wire_nlOi11l_o(0) WHEN nlO0iil = '1' ELSE nlO01lO; + wire_nlO0OiO_dataout <= wire_nlOi11l_o(1) WHEN nlO0iil = '1' ELSE nlO01Oi; + wire_nlO0Ol_dataout <= wire_nlO0lO_w_lg_nlO0ll619w(0) WHEN (wire_w_lg_nlill1O620w(0) AND (rxupdatefc XOR nlO0Oi)) = '1' ELSE nlO0ll; + wire_nlO0Oli_dataout <= wire_nlOi11l_o(2) WHEN nlO0iil = '1' ELSE nlO01Ol; + wire_nlO0Oll_dataout <= wire_nlOi11l_o(3) WHEN nlO0iil = '1' ELSE nlO01OO; + wire_nlO0OlO_dataout <= wire_nlOi11l_o(4) WHEN nlO0iil = '1' ELSE nlO001i; + wire_nlO0OOi_dataout <= wire_nlOi11l_o(5) WHEN nlO0iil = '1' ELSE nlO001l; + wire_nlO0OOl_dataout <= wire_nlOi11l_o(6) WHEN nlO0iil = '1' ELSE nlO001O; + wire_nlO0OOO_dataout <= wire_nlOi11l_o(7) WHEN nlO0iil = '1' ELSE nlO000i; + wire_nlO10ll_dataout <= wire_nlO10lO_dataout AND NOT(nli011O); + wire_nlO10lO_dataout <= wire_nlO10Oi_dataout OR (wire_w_lg_nli01ll3615w(0) AND wire_w_lg_w_lg_nli01li3598w3616w(0)); + wire_nlO10Oi_dataout <= wire_nlO10Ol_dataout OR (wire_w_lg_nli01li3598w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_nlO101O3600w3602w3604w3605w(0) OR (wire_nl01l_w_lg_w_lg_nlO101O3607w3608w(0) AND wire_nl01l_w_lg_nlO11OO3603w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_nlO101O3607w3611w3612w(0))); + wire_nlO10Ol_dataout <= wire_nlO10OO_dataout OR (wire_w_lg_nli01li3598w(0) AND nli1OOi); + wire_nlO10OO_dataout <= nlO11ll OR (wire_nlO1iii_o AND (((nli01ii XOR nlO11Ol) OR (nli010i XOR nlO11lO)) OR (NOT (nlO11Ol XOR nlO11lO)))); + wire_nlO1l0i_dataout <= wire_nlO1lil_dataout OR nli011O; + wire_nlO1l0l_dataout <= wire_nlO1liO_dataout WHEN wire_w_lg_nli1OOl3562w(0) = '1' ELSE nlO11OO; + wire_nlO1l0O_dataout <= wire_nlO1lli_dataout WHEN wire_w_lg_nli1OOl3562w(0) = '1' ELSE nlO101i; + wire_nlO1l1i_dataout <= wire_nlO1l0l_dataout OR nli011O; + wire_nlO1l1l_dataout <= wire_nlO1l0O_dataout AND NOT(nli011O); + wire_nlO1l1O_dataout <= wire_nlO1lii_dataout OR nli011O; + wire_nlO1lii_dataout <= wire_nlO1lll_dataout WHEN wire_w_lg_nli1OOl3562w(0) = '1' ELSE nlO101l; + wire_nlO1lil_dataout <= wire_nlO1llO_dataout WHEN wire_w_lg_nli1OOl3562w(0) = '1' ELSE nlO101O; + wire_nlO1liO_dataout <= wire_nlO1lOi_o(1) AND nli1OOO; + wire_nlO1lli_dataout <= wire_nlO1lOi_o(2) AND nli1OOO; + wire_nlO1lll_dataout <= wire_nlO1lOi_o(3) AND nli1OOO; + wire_nlO1llO_dataout <= wire_nlO1lOi_o(4) AND nli1OOO; + wire_nlOi00i_dataout <= nlO00il OR nli00iO; + wire_nlOi00l_dataout <= nlO00iO OR nli00li; + wire_nlOi00O_dataout <= nlO00li OR nli00ll; + wire_nlOi01i_dataout <= wire_nlOi0OO_dataout AND NOT(nlO0i0O); + wire_nlOi01l_dataout <= nlO000O OR nli00ii; + wire_nlOi01O_dataout <= nlO00ii OR nli00il; + wire_nlOi0ii_dataout <= wire_nlOii1i_o(0) WHEN nlO0iiO = '1' ELSE nlO00ll; + wire_nlOi0il_dataout <= wire_nlOii1i_o(1) WHEN nlO0iiO = '1' ELSE nlO00lO; + wire_nlOi0iO_dataout <= wire_nlOii1i_o(2) WHEN nlO0iiO = '1' ELSE nlO00Oi; + wire_nlOi0li_dataout <= wire_nlOii1i_o(3) WHEN nlO0iiO = '1' ELSE nlO00Ol; + wire_nlOi0ll_dataout <= wire_nlOii1i_o(4) WHEN nlO0iiO = '1' ELSE nlO00OO; + wire_nlOi0lO_dataout <= wire_nlOii1i_o(5) WHEN nlO0iiO = '1' ELSE nlO0i1i; + wire_nlOi0Oi_dataout <= wire_nlOii1i_o(6) WHEN nlO0iiO = '1' ELSE nlO0i1l; + wire_nlOi0Ol_dataout <= wire_nlOii1i_o(7) WHEN nlO0iiO = '1' ELSE nlO0i1O; + wire_nlOi0OO_dataout <= wire_nlOii1i_o(8) WHEN nlO0iiO = '1' ELSE nlO0i0i; + wire_nlOi10i_dataout <= wire_nlOi01O_dataout AND NOT(nlO0i0O); + wire_nlOi10l_dataout <= wire_nlOi00i_dataout AND NOT(nlO0i0O); + wire_nlOi10O_dataout <= wire_nlOi00l_dataout AND NOT(nlO0i0O); + wire_nlOi11i_dataout <= wire_nlOi11l_o(8) WHEN nlO0iil = '1' ELSE nlO000l; + wire_nlOi11O_dataout <= wire_nlOi01l_dataout AND NOT(nlO0i0O); + wire_nlOi1ii_dataout <= wire_nlOi00O_dataout AND NOT(nlO0i0O); + wire_nlOi1il_dataout <= wire_nlOi0ii_dataout AND NOT(nlO0i0O); + wire_nlOi1iO_dataout <= wire_nlOi0il_dataout AND NOT(nlO0i0O); + wire_nlOi1l_dataout <= nlO0Oi WHEN nlill1O = '1' ELSE rxupdatefc; + wire_nlOi1li_dataout <= wire_nlOi0iO_dataout AND NOT(nlO0i0O); + wire_nlOi1ll_dataout <= wire_nlOi0li_dataout AND NOT(nlO0i0O); + wire_nlOi1lO_dataout <= wire_nlOi0ll_dataout AND NOT(nlO0i0O); + wire_nlOi1Oi_dataout <= wire_nlOi0lO_dataout AND NOT(nlO0i0O); + wire_nlOi1Ol_dataout <= wire_nlOi0Oi_dataout AND NOT(nlO0i0O); + wire_nlOi1OO_dataout <= wire_nlOi0Ol_dataout AND NOT(nlO0i0O); + wire_nlOii0i_dataout <= wire_nlOiill_o(0) AND NOT(nlO0i0l); + wire_nlOii0l_dataout <= wire_nlOiill_o(1) AND NOT(nlO0i0l); + wire_nlOii0O_dataout <= wire_nlOiill_o(2) AND NOT(nlO0i0l); + wire_nlOiiii_dataout <= wire_nlOiill_o(3) AND NOT(nlO0i0l); + wire_nlOiiil_dataout <= wire_nlOiill_o(4) AND NOT(nlO0i0l); + wire_nlOiiiO_dataout <= wire_nlOiill_o(5) AND NOT(nlO0i0l); + wire_nlOiili_dataout <= wire_nlOiill_o(6) AND NOT(nlO0i0l); + wire_nlOiilO_dataout <= wire_nlOil0i_o(0) AND NOT(nlO0i0O); + wire_nlOiiOi_dataout <= wire_nlOil0i_o(1) AND NOT(nlO0i0O); + wire_nlOiiOl_dataout <= wire_nlOil0i_o(2) AND NOT(nlO0i0O); + wire_nlOiiOO_dataout <= wire_nlOil0i_o(3) AND NOT(nlO0i0O); + wire_nlOil0l_dataout <= nlO100l AND enable_inf_ei(5); + wire_nlOil0O_dataout <= nllOlOO AND enable_inf_ei(4); + wire_nlOil1i_dataout <= wire_nlOil0i_o(4) AND NOT(nlO0i0O); + wire_nlOil1l_dataout <= wire_nlOil0i_o(5) AND NOT(nlO0i0O); + wire_nlOil1O_dataout <= wire_nlOil0i_o(6) AND NOT(nlO0i0O); + wire_nlOilii_dataout <= nlOilll AND enable_inf_ei(3); + wire_nlOilil_dataout <= nlO100l AND enable_inf_ei(2); + wire_nlOiliO_dataout <= nllOlOO AND enable_inf_ei(1); + wire_nlOilli_dataout <= nlOilll AND enable_inf_ei(0); + wire_nlOillO_dataout <= ((wire_nlOil0O_dataout OR wire_nlOil0l_dataout) OR wire_nlOilii_dataout) WHEN rate = '1' ELSE ((wire_nlOiliO_dataout OR wire_nlOilil_dataout) OR wire_nlOilli_dataout); + wire_nlOl11l_dataout <= wire_nliii_w_lg_nlOl10i3313w(0) WHEN (nlOl1il XOR nlOl1ii) = '1' ELSE nlOl10i; + wire_nlOl1ll_dataout <= wire_nlO0lO_w_lg_nlOl1iO3309w(0) WHEN (wire_w_lg_nli00lO3310w(0) AND (rxupdatefc XOR nlOl1li)) = '1' ELSE nlOl1iO; + wire_nlOl1Ol_dataout <= nlOl1li WHEN nli00lO = '1' ELSE rxupdatefc; + wire_nlOlOiO_dataout <= nlOO11O OR wire_nliii_w_lg_n1i1il3095w(0); + wire_nlOlOli_dataout <= wire_nlOlOOl_dataout AND NOT(nlOlO0i); + wire_nlOlOll_dataout <= wire_nlOlOOO_dataout OR nlOlO0i; + wire_nlOlOlO_dataout <= wire_nlOO11i_dataout AND NOT(nlOlO0i); + wire_nlOlOOi_dataout <= wire_nlOO11l_dataout AND NOT(nlOlO0i); + wire_nlOlOOl_dataout <= nlOlO1i AND NOT(n1i1il); + wire_nlOlOOO_dataout <= nlOlO1l AND NOT(n1i1il); + wire_nlOO11i_dataout <= nlOlO1O OR n1i1il; + wire_nlOO11l_dataout <= nlOO11O AND NOT(n1i1il); + wire_nlOOiOl_dataout <= wire_nlOOiOO_dataout AND NOT(nli0iii); + wire_nlOOiOO_dataout <= wire_nlOOl1i_dataout OR (wire_w_lg_nli0iOO3077w(0) AND wire_w_lg_w_lg_nli0iOl3060w3078w(0)); + wire_nlOOl1i_dataout <= wire_nlOOl1l_dataout OR (wire_w_lg_nli0iOl3060w(0) AND ((wire_nl01l_w_lg_w_lg_w_lg_w_lg_nlOOi0O3062w3064w3066w3067w(0) OR (wire_nl01l_w_lg_w_lg_nlOOi0O3069w3070w(0) AND wire_nl01l_w_lg_nlOOi1O3065w(0))) OR wire_nl01l_w_lg_w_lg_w_lg_nlOOi0O3069w3073w3074w(0))); + wire_nlOOl1l_dataout <= wire_nlOOl1O_dataout OR (wire_w_lg_nli0iOl3060w(0) AND nli0i1l); + wire_nlOOl1O_dataout <= nlOO0Ol OR (wire_nlOOlli_o AND (((nli0ill XOR nlOOi1l) OR (nli0iil XOR nlOO0OO)) OR (NOT (nlOOi1l XOR nlOO0OO)))); + wire_nlOOO0i_dataout <= wire_nlOOOil_dataout OR nli0iii; + wire_nlOOO0l_dataout <= wire_nlOOOiO_dataout AND NOT(nli0iii); + wire_nlOOO0O_dataout <= wire_nlOOOli_dataout OR nli0iii; + wire_nlOOOii_dataout <= wire_nlOOOll_dataout OR nli0iii; + wire_nlOOOil_dataout <= wire_nlOOOlO_dataout WHEN wire_w_lg_nli0i1O3024w(0) = '1' ELSE nlOOi1O; + wire_nlOOOiO_dataout <= wire_nlOOOOi_dataout WHEN wire_w_lg_nli0i1O3024w(0) = '1' ELSE nlOOi0i; + wire_nlOOOli_dataout <= wire_nlOOOOl_dataout WHEN wire_w_lg_nli0i1O3024w(0) = '1' ELSE nlOOi0l; + wire_nlOOOll_dataout <= wire_nlOOOOO_dataout WHEN wire_w_lg_nli0i1O3024w(0) = '1' ELSE nlOOi0O; + wire_nlOOOlO_dataout <= wire_n1111i_o(1) AND nli0i0i; + wire_nlOOOOi_dataout <= wire_n1111i_o(2) AND nli0i0i; + wire_nlOOOOl_dataout <= wire_n1111i_o(3) AND nli0i0i; + wire_nlOOOOO_dataout <= wire_n1111i_o(4) AND nli0i0i; + wire_n000i_a <= ( n1liO & n1lil & n1lii & n1l0O & "1"); + wire_n000i_b <= ( "1" & "1" & "1" & "0" & "1"); + n000i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n000i_a, + b => wire_n000i_b, + cin => wire_gnd, + o => wire_n000i_o + ); + wire_n0011l_a <= ( n011ii & n0110O & n0110l & n0110i & n0111O & n0111l & n0111i); + wire_n0011l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0011l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0011l_a, + b => wire_n0011l_b, + cin => wire_gnd, + o => wire_n0011l_o + ); + wire_n001li_a <= ( n011Ol & n011Oi & n011lO & n011ll & n011li & n011iO & n011il); + wire_n001li_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n001li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n001li_a, + b => wire_n001li_b, + cin => wire_gnd, + o => wire_n001li_o + ); + wire_n01iil_a <= ( n1Olll & n1Olli & n1OliO & n1Olil & n1Olii & n1Ol0O & n1Ol0l & n1Ol0i & n1Ol1O); + wire_n01iil_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n01iil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_n01iil_a, + b => wire_n01iil_b, + cin => wire_gnd, + o => wire_n01iil_o + ); + wire_n01Oii_a <= ( n1OOli & n1OOiO & n1OOil & n1OOii & n1OO0O & n1OO0l & n1OO0i & n1OO1O & n1OO1l); + wire_n01Oii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n01Oii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_n01Oii_a, + b => wire_n01Oii_b, + cin => wire_gnd, + o => wire_n01Oii_o + ); + wire_n0liii_a <= ( n0iOlO & n0iOll & n0iOli & n0iOiO & "1"); + wire_n0liii_b <= ( "1" & "1" & "1" & "0" & "1"); + n0liii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0liii_a, + b => wire_n0liii_b, + cin => wire_gnd, + o => wire_n0liii_o + ); + wire_n0Olll_a <= ( n0lOOl & n0lOOi & n0lOlO & n0lOll & n0lOli & n0lOiO & n0lOil & n0lOii & n0lO0O); + wire_n0Olll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0Olll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_n0Olll_a, + b => wire_n0Olll_b, + cin => wire_gnd, + o => wire_n0Olll_o + ); + wire_n1000l_a <= ( n11iil & n11iii & n11i0O & n11i0l & n11i0i & n11i1O & n11i1l & n11i1i & n110OO); + wire_n1000l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n1000l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_n1000l_a, + b => wire_n1000l_b, + cin => wire_gnd, + o => wire_n1000l_o + ); + wire_n10l0i_a <= ( n11lii & n11l0O & n11l0l & n11l0i & n11l1O & n11l1l & n11l1i & n11iOO & n11iOl); + wire_n10l0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n10l0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_n10l0i_a, + b => wire_n10l0i_b, + cin => wire_gnd, + o => wire_n10l0i_o + ); + wire_n10lOl_a <= ( n11O0i & n11O1O & n11O1l & n11O1i & n11lOO & n11lOl & n11lOi); + wire_n10lOl_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n10lOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n10lOl_a, + b => wire_n10lOl_b, + cin => wire_gnd, + o => wire_n10lOl_o + ); + wire_n10Oii_a <= ( n11Oll & n11Oli & n11OiO & n11Oil & n11Oii & n11O0O & n11O0l); + wire_n10Oii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n10Oii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n10Oii_a, + b => wire_n10Oii_b, + cin => wire_gnd, + o => wire_n10Oii_o + ); + wire_n1111i_a <= ( nlOOi0O & nlOOi0l & nlOOi0i & nlOOi1O & "1"); + wire_n1111i_b <= ( "1" & "1" & "1" & "0" & "1"); + n1111i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1111i_a, + b => wire_n1111i_b, + cin => wire_gnd, + o => wire_n1111i_o + ); + wire_n1O00i_a <= ( n1lliO & n1llil & n1llii & n1ll0O & "1"); + wire_n1O00i_b <= ( "1" & "1" & "1" & "0" & "1"); + n1O00i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1O00i_a, + b => wire_n1O00i_b, + cin => wire_gnd, + o => wire_n1O00i_o + ); + wire_ni100l_a <= ( n0O0li & n0O0iO & n0O0il & n0O0ii & n0O00O & n0O00l & n0O00i); + wire_ni100l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + ni100l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_ni100l_a, + b => wire_ni100l_b, + cin => wire_gnd, + o => wire_ni100l_o + ); + wire_ni10Oi_a <= ( n0Oi1l & n0Oi1i & n0O0OO & n0O0Ol & n0O0Oi & n0O0lO & n0O0ll); + wire_ni10Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + ni10Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_ni10Oi_a, + b => wire_ni10Oi_b, + cin => wire_gnd, + o => wire_ni10Oi_o + ); + wire_ni11li_a <= ( n0O1Oi & n0O1lO & n0O1ll & n0O1li & n0O1iO & n0O1il & n0O1ii & n0O10O & n0O10l); + wire_ni11li_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + ni11li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_ni11li_a, + b => wire_ni11li_b, + cin => wire_gnd, + o => wire_ni11li_o + ); + wire_niiil_a <= ( n0lll & n0lli & n0liO & n0lil & n0lii & n0l0O & wire_nliO01O24_w_lg_w_lg_q161w162w & n0l0i & n0l1O); + wire_niiil_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niiil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_niiil_a, + b => wire_niiil_b, + cin => wire_gnd, + o => wire_niiil_o + ); + wire_niilli_a <= ( nii1OO & nii1Ol & nii1Oi & nii1lO & "1"); + wire_niilli_b <= ( "1" & "1" & "1" & "0" & "1"); + niilli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_niilli_a, + b => wire_niilli_b, + cin => wire_gnd, + o => wire_niilli_o + ); + wire_nilOOl_a <= ( nil01l & nil01i & nil1OO & nil1Ol & nil1Oi & nil1lO & nil1ll & nil1li & nil1iO); + wire_nilOOl_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nilOOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nilOOl_a, + b => wire_nilOOl_b, + cin => wire_gnd, + o => wire_nilOOl_o + ); + wire_niO0Oi_a <= ( nili1i & nil0OO & nil0Ol & nil0Oi & nil0lO & nil0ll & nil0li & nil0iO & nil0il); + wire_niO0Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niO0Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_niO0Oi_a, + b => wire_niO0Oi_b, + cin => wire_gnd, + o => wire_niO0Oi_o + ); + wire_niOii_a <= ( n0Oli & n0OiO & n0Oil & n0Oii & wire_nliO0iO22_w_lg_w_lg_q123w124w & wire_nliO0li20_w_lg_w_lg_q120w121w & n0O0i & n0O1O & n0O1l); + wire_niOii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niOii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_niOii_a, + b => wire_niOii_b, + cin => wire_gnd, + o => wire_niOii_o + ); + wire_niOiil_a <= ( niliOi & nililO & nilill & nilili & niliiO & niliil & niliii); + wire_niOiil_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niOiil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_niOiil_a, + b => wire_niOiil_b, + cin => wire_gnd, + o => wire_niOiil_o + ); + wire_niOl1i_a <= ( nill0l & nill0i & nill1O & nill1l & nill1i & niliOO & niliOl); + wire_niOl1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + niOl1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_niOl1i_a, + b => wire_niOl1i_b, + cin => wire_gnd, + o => wire_niOl1i_o + ); + wire_nl0OOi_a <= ( nl0i1O & nl0i1l & nl0i1i & nl00OO & "1"); + wire_nl0OOi_b <= ( "1" & "1" & "1" & "0" & "1"); + nl0OOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl0OOi_a, + b => wire_nl0OOi_b, + cin => wire_gnd, + o => wire_nl0OOi_o + ); + wire_nl11l_a <= ( wire_nliO0ll18_w_lg_w_lg_q91w92w & ni10O & ni10l & ni10i & wire_nliO0lO16_w_lg_w_lg_q85w86w & ni11l & ni11i); + wire_nl11l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl11l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nl11l_a, + b => wire_nl11l_b, + cin => wire_gnd, + o => wire_nl11l_o + ); + wire_nl1li_a <= ( ni1Ol & ni1Oi & ni1lO & wire_nliO0Oi14_w_lg_w_lg_q54w55w & ni1li & wire_nliO0Ol12_w_lg_w_lg_q50w51w & wire_nliO0OO10_w_lg_w_lg_q46w47w); + wire_nl1li_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nl1li_a, + b => wire_nl1li_b, + cin => wire_gnd, + o => wire_nl1li_o + ); + wire_nll01l_a <= ( nlii0l & nlii0i & nlii1O & nlii1l & nlii1i & nli0OO & nli0Ol & nli0Oi & nli0lO); + wire_nll01l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nll01l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nll01l_a, + b => wire_nll01l_b, + cin => wire_gnd, + o => wire_nll01l_o + ); + wire_nll0ili_a <= ( nll1OOO & nll1OOl & nll1OOi & nll1OlO & "1"); + wire_nll0ili_b <= ( "1" & "1" & "1" & "0" & "1"); + nll0ili : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nll0ili_a, + b => wire_nll0ili_b, + cin => wire_gnd, + o => wire_nll0ili_o + ); + wire_nllilOl_a <= ( nlli11l & nlli11i & nll0OOO & nll0OOl & nll0OOi & nll0OlO & nll0Oll & nll0Oli & nll0OiO); + wire_nllilOl_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nllilOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nllilOl_a, + b => wire_nllilOl_b, + cin => wire_gnd, + o => wire_nllilOl_o + ); + wire_nlll0il_a <= ( nlli0Oi & nlli0lO & nlli0ll & nlli0li & nlli0iO & nlli0il & nlli0ii); + wire_nlll0il_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll0il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlll0il_a, + b => wire_nlll0il_b, + cin => wire_gnd, + o => wire_nlll0il_o + ); + wire_nlll1i_a <= ( nlil0i & nlil1O & nlil1l & nlil1i & nliiOO & nliiOl & nliiOi & nliilO & nliill); + wire_nlll1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlll1i_a, + b => wire_nlll1i_b, + cin => wire_gnd, + o => wire_nlll1i_o + ); + wire_nlll1Oi_a <= ( nlli01i & nlli1OO & nlli1Ol & nlli1Oi & nlli1lO & nlli1ll & nlli1li & nlli1iO & nlli1il); + wire_nlll1Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll1Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlll1Oi_a, + b => wire_nlll1Oi_b, + cin => wire_gnd, + o => wire_nlll1Oi_o + ); + wire_nllli1i_a <= ( nllii0l & nllii0i & nllii1O & nllii1l & nllii1i & nlli0OO & nlli0Ol); + wire_nllli1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nllli1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nllli1i_a, + b => wire_nllli1i_b, + cin => wire_gnd, + o => wire_nllli1i_o + ); + wire_nlllll_a <= ( nliO1i & nlilOO & nlilOl & nlilOi & nlillO & nlilll & nlilli); + wire_nlllll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlllll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlllll_a, + b => wire_nlllll_b, + cin => wire_gnd, + o => wire_nlllll_o + ); + wire_nllO0i_a <= ( nliOil & nliOii & nliO0O & nliO0l & nliO0i & nliO1O & nliO1l); + wire_nllO0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nllO0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nllO0i_a, + b => wire_nllO0i_b, + cin => wire_gnd, + o => wire_nllO0i_o + ); + wire_nlO1lOi_a <= ( nlO101O & nlO101l & nlO101i & nlO11OO & "1"); + wire_nlO1lOi_b <= ( "1" & "1" & "1" & "0" & "1"); + nlO1lOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlO1lOi_a, + b => wire_nlO1lOi_b, + cin => wire_gnd, + o => wire_nlO1lOi_o + ); + wire_nlOi11l_a <= ( nlO000l & nlO000i & nlO001O & nlO001l & nlO001i & nlO01OO & nlO01Ol & nlO01Oi & nlO01lO); + wire_nlOi11l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOi11l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlOi11l_a, + b => wire_nlOi11l_b, + cin => wire_gnd, + o => wire_nlOi11l_o + ); + wire_nlOii1i_a <= ( nlO0i0i & nlO0i1O & nlO0i1l & nlO0i1i & nlO00OO & nlO00Ol & nlO00Oi & nlO00lO & nlO00ll); + wire_nlOii1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOii1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlOii1i_a, + b => wire_nlOii1i_b, + cin => wire_gnd, + o => wire_nlOii1i_o + ); + wire_nlOiill_a <= ( nlO0l1i & nlO0iOO & nlO0iOl & nlO0iOi & nlO0ilO & nlO0ill & nlO0ili); + wire_nlOiill_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOiill : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlOiill_a, + b => wire_nlOiill_b, + cin => wire_gnd, + o => wire_nlOiill_o + ); + wire_nlOil0i_a <= ( nlO0lil & nlO0lii & nlO0l0O & nlO0l0l & nlO0l0i & nlO0l1O & nlO0l1l); + wire_nlOil0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOil0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlOil0i_a, + b => wire_nlOil0i_b, + cin => wire_gnd, + o => wire_nlOil0i_o + ); + wire_n010O_a <= ( n1liO & n1lil & n1lii & n1l0O); + wire_n010O_b <= ( "1" & "0" & "0" & "1"); + n010O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n010O_a, + b => wire_n010O_b, + cin => wire_vcc, + o => wire_n010O_o + ); + wire_n0l01i_a <= ( n0iOlO & n0iOll & n0iOli & n0iOiO); + wire_n0l01i_b <= ( "1" & "0" & "0" & "1"); + n0l01i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0l01i_a, + b => wire_n0l01i_b, + cin => wire_gnd, + o => wire_n0l01i_o + ); + wire_n0l0iO_a <= ( n0iOlO & n0iOll & n0iOli & n0iOiO); + wire_n0l0iO_b <= ( "1" & "0" & "0" & "1"); + n0l0iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0l0iO_a, + b => wire_n0l0iO_b, + cin => wire_vcc, + o => wire_n0l0iO_o + ); + wire_n1lOOi_a <= ( n1lliO & n1llil & n1llii & n1ll0O); + wire_n1lOOi_b <= ( "1" & "0" & "0" & "1"); + n1lOOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1lOOi_a, + b => wire_n1lOOi_b, + cin => wire_gnd, + o => wire_n1lOOi_o + ); + wire_n1O10O_a <= ( n1lliO & n1llil & n1llii & n1ll0O); + wire_n1O10O_b <= ( "1" & "0" & "0" & "1"); + n1O10O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1O10O_a, + b => wire_n1O10O_b, + cin => wire_vcc, + o => wire_n1O10O_o + ); + wire_n1OOi_a <= ( n1liO & n1lil & n1lii & n1l0O); + wire_n1OOi_b <= ( "1" & "0" & "0" & "1"); + n1OOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1OOi_a, + b => wire_n1OOi_b, + cin => wire_gnd, + o => wire_n1OOi_o + ); + wire_niii0i_a <= ( nii1OO & nii1Ol & nii1Oi & nii1lO); + wire_niii0i_b <= ( "1" & "0" & "0" & "1"); + niii0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_niii0i_a, + b => wire_niii0i_b, + cin => wire_gnd, + o => wire_niii0i_o + ); + wire_niiilO_a <= ( nii1OO & nii1Ol & nii1Oi & nii1lO); + wire_niiilO_b <= ( "1" & "0" & "0" & "1"); + niiilO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_niiilO_a, + b => wire_niiilO_b, + cin => wire_vcc, + o => wire_niiilO_o + ); + wire_nl0lii_a <= ( nl0i1O & nl0i1l & nl0i1i & nl00OO); + wire_nl0lii_b <= ( "1" & "0" & "0" & "1"); + nl0lii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nl0lii_a, + b => wire_nl0lii_b, + cin => wire_gnd, + o => wire_nl0lii_o + ); + wire_nl0lOO_a <= ( nl0i1O & nl0i1l & nl0i1i & nl00OO); + wire_nl0lOO_b <= ( "1" & "0" & "0" & "1"); + nl0lOO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nl0lOO_a, + b => wire_nl0lOO_b, + cin => wire_vcc, + o => wire_nl0lOO_o + ); + wire_nll000i_a <= ( nll1OOO & nll1OOl & nll1OOi & nll1OlO); + wire_nll000i_b <= ( "1" & "0" & "0" & "1"); + nll000i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nll000i_a, + b => wire_nll000i_b, + cin => wire_gnd, + o => wire_nll000i_o + ); + wire_nll00lO_a <= ( nll1OOO & nll1OOl & nll1OOi & nll1OlO); + wire_nll00lO_b <= ( "1" & "0" & "0" & "1"); + nll00lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nll00lO_a, + b => wire_nll00lO_b, + cin => wire_vcc, + o => wire_nll00lO_o + ); + wire_nlO1iii_a <= ( nlO101O & nlO101l & nlO101i & nlO11OO); + wire_nlO1iii_b <= ( "1" & "0" & "0" & "1"); + nlO1iii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlO1iii_a, + b => wire_nlO1iii_b, + cin => wire_gnd, + o => wire_nlO1iii_o + ); + wire_nlO1iOO_a <= ( nlO101O & nlO101l & nlO101i & nlO11OO); + wire_nlO1iOO_b <= ( "1" & "0" & "0" & "1"); + nlO1iOO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlO1iOO_a, + b => wire_nlO1iOO_b, + cin => wire_vcc, + o => wire_nlO1iOO_o + ); + wire_nlOOlli_a <= ( nlOOi0O & nlOOi0l & nlOOi0i & nlOOi1O); + wire_nlOOlli_b <= ( "1" & "0" & "0" & "1"); + nlOOlli : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlOOlli_a, + b => wire_nlOOlli_b, + cin => wire_gnd, + o => wire_nlOOlli_o + ); + wire_nlOOO1O_a <= ( nlOOi0O & nlOOi0l & nlOOi0i & nlOOi1O); + wire_nlOOO1O_b <= ( "1" & "0" & "0" & "1"); + nlOOO1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlOOO1O_a, + b => wire_nlOOO1O_b, + cin => wire_vcc, + o => wire_nlOOO1O_o + ); + wire_n0iii_data <= ( n0i0i & n0i0i & n0i0i & nlO00l & "1" & "1" & "1" & "1"); + wire_n0iii_sel <= ( nl0ll & nl0li & wire_nliO10i36_w_lg_w_lg_q257w258w); + n0iii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0iii_data, + o => wire_n0iii_o, + sel => wire_n0iii_sel + ); + wire_n0iil_data <= ( wire_n0ill_dataout & nl0Oi & n1iOl & n10Oi & "1" & "1" & "1" & "1"); + wire_n0iil_sel <= ( nl0ll & nl0li & nl0iO); + n0iil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0iil_data, + o => wire_n0iil_o, + sel => wire_n0iil_sel + ); + wire_n0iiO_data <= ( wire_n0ilO_dataout & wire_n0iOi_dataout & n0lOl & wire_n0iOl_dataout & wire_n0ili_dataout & wire_n0ili_dataout & wire_nliO10l34_w_lg_w_lg_q231w232w & wire_n0ili_dataout); + wire_n0iiO_sel <= ( nl0ll & wire_nliO10O32_w_lg_w_lg_q225w226w & nl0iO); + n0iiO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0iiO_data, + o => wire_n0iiO_o, + sel => wire_n0iiO_sel + ); + wire_n0llli_data <= ( n0llii & n0llii & n0llii & n00ili & "1" & "1" & "1" & "1"); + wire_n0llli_sel <= ( ni1iOi & ni1ilO & ni1ill); + n0llli : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0llli_data, + o => wire_n0llli_o, + sel => wire_n0llli_sel + ); + wire_n0llll_data <= ( wire_n0llOl_dataout & ni1iOO & n0iO1l & n0il1i & "1" & "1" & "1" & "1"); + wire_n0llll_sel <= ( ni1iOi & ni1ilO & ni1ill); + n0llll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0llll_data, + o => wire_n0llll_o, + sel => wire_n0llll_sel + ); + wire_n0lllO_data <= ( wire_n0llOO_dataout & wire_n0lO1i_dataout & n0O11l & wire_n0lO1l_dataout & wire_n0llOi_dataout & wire_n0llOi_dataout & wire_n0llOi_dataout & wire_n0llOi_dataout); + wire_n0lllO_sel <= ( ni1iOi & ni1ilO & ni1ill); + n0lllO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0lllO_data, + o => wire_n0lllO_o, + sel => wire_n0lllO_sel + ); + wire_n1100i_data <= ( n1101i & n1101i & n1101i & nlOl10i & "1" & "1" & "1" & "1"); + wire_n1100i_sel <= ( n1i1ii & n1i10O & n1i10l); + n1100i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1100i_data, + o => wire_n1100i_o, + sel => wire_n1100i_sel + ); + wire_n1100l_data <= ( wire_n110il_dataout & n1i1iO & nlOO0ll & nlOO1li & "1" & "1" & "1" & "1"); + wire_n1100l_sel <= ( n1i1ii & n1i10O & n1i10l); + n1100l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1100l_data, + o => wire_n1100l_o, + sel => wire_n1100l_sel + ); + wire_n1100O_data <= ( wire_n110iO_dataout & wire_n110li_dataout & n11ill & wire_n110ll_dataout & wire_n110ii_dataout & wire_n110ii_dataout & wire_n110ii_dataout & wire_n110ii_dataout); + wire_n1100O_sel <= ( n1i1ii & n1i10O & n1i10l); + n1100O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1100O_data, + o => wire_n1100O_o, + sel => wire_n1100O_sel + ); + wire_n1Oiii_data <= ( n1Oi0i & n1Oi0i & n1Oi0i & n1i0ii & "1" & "1" & "1" & "1"); + wire_n1Oiii_sel <= ( n000li & n000iO & n000il); + n1Oiii : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1Oiii_data, + o => wire_n1Oiii_o, + sel => wire_n1Oiii_sel + ); + wire_n1Oiil_data <= ( wire_n1Oill_dataout & n000lO & n1liOl & n1l0Oi & "1" & "1" & "1" & "1"); + wire_n1Oiil_sel <= ( n000li & n000iO & n000il); + n1Oiil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1Oiil_data, + o => wire_n1Oiil_o, + sel => wire_n1Oiil_sel + ); + wire_n1OiiO_data <= ( wire_n1OilO_dataout & wire_n1OiOi_dataout & n1OlOl & wire_n1OiOl_dataout & wire_n1Oili_dataout & wire_n1Oili_dataout & wire_n1Oili_dataout & wire_n1Oili_dataout); + wire_n1OiiO_sel <= ( n000li & n000iO & n000il); + n1OiiO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1OiiO_data, + o => wire_n1OiiO_o, + sel => wire_n1OiiO_sel + ); + wire_niiOOi_data <= ( niiOli & niiOli & niiOli & ni1lOi & "1" & "1" & "1" & "1"); + wire_niiOOi_sel <= ( niOO1i & niOlOO & niOlOl); + niiOOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_niiOOi_data, + o => wire_niiOOi_o, + sel => wire_niiOOi_sel + ); + wire_niiOOl_data <= ( wire_nil11l_dataout & niOO1O & nii10l & ni0O0i & "1" & "1" & "1" & "1"); + wire_niiOOl_sel <= ( niOO1i & niOlOO & niOlOl); + niiOOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_niiOOl_data, + o => wire_niiOOl_o, + sel => wire_niiOOl_sel + ); + wire_niiOOO_data <= ( wire_nil11O_dataout & wire_nil10i_dataout & nil00l & wire_nil10l_dataout & wire_nil11i_dataout & wire_nil11i_dataout & wire_nil11i_dataout & wire_nil11i_dataout); + wire_niiOOO_sel <= ( niOO1i & niOlOO & niOlOl); + niiOOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_niiOOO_data, + o => wire_niiOOO_o, + sel => wire_niiOOO_sel + ); + wire_nli01i_data <= ( nli1Oi & nli1Oi & nli1Oi & nl111i & "1" & "1" & "1" & "1"); + wire_nli01i_sel <= ( nlO10i & nlO11O & nlO11l); + nli01i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli01i_data, + o => wire_nli01i_o, + sel => wire_nli01i_sel + ); + wire_nli01l_data <= ( wire_nli00l_dataout & nlO10O & nl00il & nl01ii & "1" & "1" & "1" & "1"); + wire_nli01l_sel <= ( nlO10i & nlO11O & nlO11l); + nli01l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli01l_data, + o => wire_nli01l_o, + sel => wire_nli01l_sel + ); + wire_nli01O_data <= ( wire_nli00O_dataout & wire_nli0ii_dataout & nliiil & wire_nli0il_dataout & wire_nli00i_dataout & wire_nli00i_dataout & wire_nli00i_dataout & wire_nli00i_dataout); + wire_nli01O_sel <= ( nlO10i & nlO11O & nlO11l); + nli01O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli01O_data, + o => wire_nli01O_o, + sel => wire_nli01O_sel + ); + wire_nll0lOi_data <= ( nll0lli & nll0lli & nll0lli & nliOiOi & "1" & "1" & "1" & "1"); + wire_nll0lOi_sel <= ( nllll1i & nllliOO & nllliOl); + nll0lOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll0lOi_data, + o => wire_nll0lOi_o, + sel => wire_nll0lOi_sel + ); + wire_nll0lOl_data <= ( wire_nll0O1l_dataout & nllll1O & nll1O0l & nll1l0i & "1" & "1" & "1" & "1"); + wire_nll0lOl_sel <= ( nllll1i & nllliOO & nllliOl); + nll0lOl : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll0lOl_data, + o => wire_nll0lOl_o, + sel => wire_nll0lOl_sel + ); + wire_nll0lOO_data <= ( wire_nll0O1O_dataout & wire_nll0O0i_dataout & nlli10l & wire_nll0O0l_dataout & wire_nll0O1i_dataout & wire_nll0O1i_dataout & wire_nll0O1i_dataout & wire_nll0O1i_dataout); + wire_nll0lOO_sel <= ( nllll1i & nllliOO & nllliOl); + nll0lOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll0lOO_data, + o => wire_nll0lOO_o, + sel => wire_nll0lOO_sel + ); + wire_nlO011i_data <= ( nlO1OOi & nlO1OOi & nlO1OOi & nlllO1i & "1" & "1" & "1" & "1"); + wire_nlO011i_sel <= ( nlOiO0i & nlOiO1O & nlOiO1l); + nlO011i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO011i_data, + o => wire_nlO011i_o, + sel => wire_nlO011i_sel + ); + wire_nlO011l_data <= ( wire_nlO010l_dataout & nlOiO0O & nlO11il & nllOOii & "1" & "1" & "1" & "1"); + wire_nlO011l_sel <= ( nlOiO0i & nlOiO1O & nlOiO1l); + nlO011l : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO011l_data, + o => wire_nlO011l_o, + sel => wire_nlO011l_sel + ); + wire_nlO011O_data <= ( wire_nlO010O_dataout & wire_nlO01ii_dataout & nlO00il & wire_nlO01il_dataout & wire_nlO010i_dataout & wire_nlO010i_dataout & wire_nlO010i_dataout & wire_nlO010i_dataout); + wire_nlO011O_sel <= ( nlOiO0i & nlOiO1O & nlOiO1l); + nlO011O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO011O_data, + o => wire_nlO011O_o, + sel => wire_nlO011O_sel + ); + wire_n0i0ll_data <= ( wire_n0ii1i_dataout & wire_nliii_w_lg_ni1iOl2019w); + wire_n0i0ll_sel <= ( n0i0iO & wire_nl01l_w_lg_n0i0iO2046w); + n0i0ll : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n0i0ll_data, + o => wire_n0i0ll_o, + sel => wire_n0i0ll_sel + ); + wire_n0i0lO_data <= ( wire_n0ii1l_dataout & ni1iOl & "0"); + wire_n0i0lO_sel <= ( n0i0iO & n0i0il & n0i0ii); + n0i0lO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0i0lO_data, + o => wire_n0i0lO_o, + sel => wire_n0i0lO_sel + ); + wire_n0i0Oi_data <= ( wire_n0ii1O_dataout & "0" & ni1iOl); + wire_n0i0Oi_sel <= ( n0i0iO & n0i0il & n0i0ii); + n0i0Oi : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0i0Oi_data, + o => wire_n0i0Oi_o, + sel => wire_n0i0Oi_sel + ); + wire_n0i0Ol_data <= ( wire_n0ii0i_dataout & wire_n0i0OO_dataout & wire_n0iiil_dataout); + wire_n0i0Ol_sel <= ( n0i0iO & n0i0il & n0i0ii); + n0i0Ol : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0i0Ol_data, + o => wire_n0i0Ol_o, + sel => wire_n0i0Ol_sel + ); + wire_n11il_data <= ( wire_n11Oi_dataout & wire_nliii_w_lg_nl0lO394w); + wire_n11il_sel <= ( n110O & wire_nl01l_w_lg_n110O421w); + n11il : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n11il_data, + o => wire_n11il_o, + sel => wire_n11il_sel + ); + wire_n11iO_data <= ( wire_n11Ol_dataout & nl0lO & "0"); + wire_n11iO_sel <= ( n110O & n110l & n110i); + n11iO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11iO_data, + o => wire_n11iO_o, + sel => wire_n11iO_sel + ); + wire_n11li_data <= ( wire_n11OO_dataout & "0" & nl0lO); + wire_n11li_sel <= ( n110O & n110l & n110i); + n11li : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11li_data, + o => wire_n11li_o, + sel => wire_n11li_sel + ); + wire_n11ll_data <= ( wire_n101i_dataout & wire_n11lO_dataout & wire_n100l_dataout); + wire_n11ll_sel <= ( n110O & n110l & n110i); + n11ll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11ll_data, + o => wire_n11ll_o, + sel => wire_n11ll_sel + ); + wire_n1l1il_data <= ( wire_n1l1Oi_dataout & wire_nliii_w_lg_n000ll2557w); + wire_n1l1il_sel <= ( n1l10O & wire_nl01l_w_lg_n1l10O2584w); + n1l1il : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n1l1il_data, + o => wire_n1l1il_o, + sel => wire_n1l1il_sel + ); + wire_n1l1iO_data <= ( wire_n1l1Ol_dataout & n000ll & "0"); + wire_n1l1iO_sel <= ( n1l10O & n1l10l & n1l10i); + n1l1iO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1l1iO_data, + o => wire_n1l1iO_o, + sel => wire_n1l1iO_sel + ); + wire_n1l1li_data <= ( wire_n1l1OO_dataout & "0" & n000ll); + wire_n1l1li_sel <= ( n1l10O & n1l10l & n1l10i); + n1l1li : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1l1li_data, + o => wire_n1l1li_o, + sel => wire_n1l1li_sel + ); + wire_n1l1ll_data <= ( wire_n1l01i_dataout & wire_n1l1lO_dataout & wire_n1l00l_dataout); + wire_n1l1ll_sel <= ( n1l10O & n1l10l & n1l10i); + n1l1ll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1l1ll_data, + o => wire_n1l1ll_o, + sel => wire_n1l1ll_sel + ); + wire_ni0iOl_data <= ( wire_ni0l0i_dataout & wire_nliii_w_lg_niOO1l1483w); + wire_ni0iOl_sel <= ( ni0ilO & wire_nl01l_w_lg_ni0ilO1510w); + ni0iOl : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_ni0iOl_data, + o => wire_ni0iOl_o, + sel => wire_ni0iOl_sel + ); + wire_ni0iOO_data <= ( wire_ni0l0l_dataout & niOO1l & "0"); + wire_ni0iOO_sel <= ( ni0ilO & ni0ill & ni0ili); + ni0iOO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni0iOO_data, + o => wire_ni0iOO_o, + sel => wire_ni0iOO_sel + ); + wire_ni0l1i_data <= ( wire_ni0l0O_dataout & "0" & niOO1l); + wire_ni0l1i_sel <= ( ni0ilO & ni0ill & ni0ili); + ni0l1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni0l1i_data, + o => wire_ni0l1i_o, + sel => wire_ni0l1i_sel + ); + wire_ni0l1l_data <= ( wire_ni0lii_dataout & wire_ni0l1O_dataout & wire_ni0lll_dataout); + wire_ni0l1l_sel <= ( ni0ilO & ni0ill & ni0ili); + ni0l1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni0l1l_data, + o => wire_ni0l1l_o, + sel => wire_ni0l1l_sel + ); + wire_nl1O0i_data <= ( wire_nl1OiO_dataout & "0" & nlO10l); + wire_nl1O0i_sel <= ( nl1lOO & nl1lOl & nl1lOi); + nl1O0i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1O0i_data, + o => wire_nl1O0i_o, + sel => wire_nl1O0i_sel + ); + wire_nl1O0l_data <= ( wire_nl1Oli_dataout & wire_nl1O0O_dataout & wire_nl1OOl_dataout); + wire_nl1O0l_sel <= ( nl1lOO & nl1lOl & nl1lOi); + nl1O0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1O0l_data, + o => wire_nl1O0l_o, + sel => wire_nl1O0l_sel + ); + wire_nl1O1l_data <= ( wire_nl1Oii_dataout & wire_nliii_w_lg_nlO10l946w); + wire_nl1O1l_sel <= ( nl1lOO & wire_nl01l_w_lg_nl1lOO973w); + nl1O1l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1O1l_data, + o => wire_nl1O1l_o, + sel => wire_nl1O1l_sel + ); + wire_nl1O1O_data <= ( wire_nl1Oil_dataout & nlO10l & "0"); + wire_nl1O1O_sel <= ( nl1lOO & nl1lOl & nl1lOi); + nl1O1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1O1O_data, + o => wire_nl1O1O_o, + sel => wire_nl1O1O_sel + ); + wire_nll10Ol_data <= ( wire_nll1i0i_dataout & wire_nliii_w_lg_nllll1l4168w); + wire_nll10Ol_sel <= ( nll10lO & wire_nl01l_w_lg_nll10lO4195w); + nll10Ol : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nll10Ol_data, + o => wire_nll10Ol_o, + sel => wire_nll10Ol_sel + ); + wire_nll10OO_data <= ( wire_nll1i0l_dataout & nllll1l & "0"); + wire_nll10OO_sel <= ( nll10lO & nll10ll & nll10li); + nll10OO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll10OO_data, + o => wire_nll10OO_o, + sel => wire_nll10OO_sel + ); + wire_nll1i1i_data <= ( wire_nll1i0O_dataout & "0" & nllll1l); + wire_nll1i1i_sel <= ( nll10lO & nll10ll & nll10li); + nll1i1i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll1i1i_data, + o => wire_nll1i1i_o, + sel => wire_nll1i1i_sel + ); + wire_nll1i1l_data <= ( wire_nll1iii_dataout & wire_nll1i1O_dataout & wire_nll1ill_dataout); + wire_nll1i1l_sel <= ( nll10lO & nll10ll & nll10li); + nll1i1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nll1i1l_data, + o => wire_nll1i1l_o, + sel => wire_nll1i1l_sel + ); + wire_nllOl0i_data <= ( wire_nllOliO_dataout & "0" & nlOiO0l); + wire_nllOl0i_sel <= ( nllOiOO & nllOiOl & nllOiOi); + nllOl0i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllOl0i_data, + o => wire_nllOl0i_o, + sel => wire_nllOl0i_sel + ); + wire_nllOl0l_data <= ( wire_nllOlli_dataout & wire_nllOl0O_dataout & wire_nllOlOl_dataout); + wire_nllOl0l_sel <= ( nllOiOO & nllOiOl & nllOiOi); + nllOl0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllOl0l_data, + o => wire_nllOl0l_o, + sel => wire_nllOl0l_sel + ); + wire_nllOl1l_data <= ( wire_nllOlii_dataout & wire_nliii_w_lg_nlOiO0l3631w); + wire_nllOl1l_sel <= ( nllOiOO & wire_nl01l_w_lg_nllOiOO3658w); + nllOl1l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nllOl1l_data, + o => wire_nllOl1l_o, + sel => wire_nllOl1l_sel + ); + wire_nllOl1O_data <= ( wire_nllOlil_dataout & nlOiO0l & "0"); + wire_nllOl1O_sel <= ( nllOiOO & nllOiOl & nllOiOi); + nllOl1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nllOl1O_data, + o => wire_nllOl1O_o, + sel => wire_nllOl1O_sel + ); + wire_nlOlO0l_data <= ( wire_nlOlOli_dataout & wire_nliii_w_lg_n1i1il3095w); + wire_nlOlO0l_sel <= ( nlOlO1O & wire_nl01l_w_lg_nlOlO1O3122w); + nlOlO0l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nlOlO0l_data, + o => wire_nlOlO0l_o, + sel => wire_nlOlO0l_sel + ); + wire_nlOlO0O_data <= ( wire_nlOlOll_dataout & n1i1il & "0"); + wire_nlOlO0O_sel <= ( nlOlO1O & nlOlO1l & nlOlO1i); + nlOlO0O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlOlO0O_data, + o => wire_nlOlO0O_o, + sel => wire_nlOlO0O_sel + ); + wire_nlOlOii_data <= ( wire_nlOlOlO_dataout & "0" & n1i1il); + wire_nlOlOii_sel <= ( nlOlO1O & nlOlO1l & nlOlO1i); + nlOlOii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlOlOii_data, + o => wire_nlOlOii_o, + sel => wire_nlOlOii_sel + ); + wire_nlOlOil_data <= ( wire_nlOlOOi_dataout & wire_nlOlOiO_dataout & wire_nlOO11l_dataout); + wire_nlOlOil_sel <= ( nlOlO1O & nlOlO1l & nlOlO1i); + nlOlOil : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlOlOil_data, + o => wire_nlOlOil_o, + sel => wire_nlOlOil_sel + ); + + END RTL; --cycloneiv_pciehip_iei_detect +--synopsys translate_on +--VALID FILE +--IP Functional Simulation Model +--VERSION_BEGIN 15.0 cbx_mgl 2015:04:22:18:06:50:SJ cbx_simgen 2015:04:22:18:04:08:SJ VERSION_END + + +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- You may only use these simulation model output files for simulation +-- purposes and expressly not for synthesis or any other purposes (in which +-- event Altera disclaims all warranties of any kind). + + +--synopsys translate_off + + LIBRARY sgate; + USE sgate.sgate_pack.all; + + LIBRARY cycloneiv_pcie_hip; + USE cycloneiv_pcie_hip.cycloneiv_pcie_hip_components.all; + +--synthesis_resources = lut 12672 mux21 54668 oper_add 301 oper_decoder 2 oper_less_than 177 oper_mux 15 oper_selector 311 cycloneiv_pciehip_pciexp_dcfiforam 7 cycloneiv_pciehip_pciexp_dcram_rtry 1 cycloneiv_pciehip_pciexp_dcram_rxvc 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY cycloneiv_pciehip_pciexp_top_hip IS + PORT + ( + adrd_rcv0 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adrd_rcv1 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adrd_rpl : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + adwr_rcv0 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adwr_rcv1 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adwr_rpl : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + clr_rxpath : OUT STD_LOGIC; + core_clk : IN STD_LOGIC; + core_clk_vc0 : OUT STD_LOGIC; + core_clk_vc1 : OUT STD_LOGIC; + core_crst : IN STD_LOGIC; + core_npor : IN STD_LOGIC; + core_rstn : IN STD_LOGIC; + core_srst : IN STD_LOGIC; + cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + cpl_pending : IN STD_LOGIC; + derr_rcv0 : IN STD_LOGIC; + derr_rcv1 : IN STD_LOGIC; + din_rcv0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + din_rcv1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + din_rpl : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + dl_ack_phypm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + dl_ack_req_upfc : OUT STD_LOGIC; + dl_ack_snd_upfc : OUT STD_LOGIC; + dl_aspm_cr0 : IN STD_LOGIC; + dl_comclk_reg : IN STD_LOGIC; + dl_ctrl_link2 : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + dl_current_deemp : OUT STD_LOGIC; + dl_current_speed : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + dl_data_upfc : IN STD_LOGIC_VECTOR (11 DOWNTO 0); + dl_dll_req : OUT STD_LOGIC; + dl_err_dll : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dl_err_phy : OUT STD_LOGIC; + dl_hdr_upfc : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + dl_inh_dllp : IN STD_LOGIC; + dl_link_auto_bdw_status : OUT STD_LOGIC; + dl_link_bdw_mng_status : OUT STD_LOGIC; + dl_ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dl_maxpload_dcr : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + dl_req_phycfg : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + dl_req_phypm : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + dl_req_upfc : IN STD_LOGIC; + dl_req_wake : IN STD_LOGIC; + dl_rpbuf_emp : OUT STD_LOGIC; + dl_rst_enter_comp_bit : OUT STD_LOGIC; + dl_rst_tx_margin_field : OUT STD_LOGIC; + dl_rx_ecrcchk : IN STD_LOGIC; + dl_rx_typ_pm : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + dl_rx_val_fc : OUT STD_LOGIC; + dl_rx_val_pm : OUT STD_LOGIC; + dl_snd_upfc : IN STD_LOGIC; + dl_tx_ack_pm : OUT STD_LOGIC; + dl_tx_req_pm : IN STD_LOGIC; + dl_tx_typ_pm : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + dl_txcfg_extsy : IN STD_LOGIC; + dl_typ_upfc : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + dl_up : OUT STD_LOGIC; + dl_vc_ctrl : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + dl_vc_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + dl_vcid_map : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + dl_vcid_upfc : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + dlup_exit : OUT STD_LOGIC; + dout_rcv0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + dout_rcv1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + dout_rpl : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + eidle_infer_sel : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + ev_128ns : OUT STD_LOGIC; + ev_1us : OUT STD_LOGIC; + hotrst_exit : OUT STD_LOGIC; + int_status : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + k_bar : IN STD_LOGIC_VECTOR (227 DOWNTO 0); + k_cnt : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + k_conf : IN STD_LOGIC_VECTOR (383 DOWNTO 0); + k_dev : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + k_gbl_hip : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + k_hip : IN STD_LOGIC_VECTOR (22 DOWNTO 0); + k_port : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + k_ptr0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0); + k_ptr1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0); + k_rtry : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + k_vc0 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc1 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc2 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc3 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc4 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc5 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc6 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc7 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + l2_exit : OUT STD_LOGIC; + lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + lane_reversal_enable : OUT STD_LOGIC; + link_up : OUT STD_LOGIC; + lmi_ack : OUT STD_LOGIC; + lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0); + lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + lmi_rden : IN STD_LOGIC; + lmi_wren : IN STD_LOGIC; + mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + phy_clk : IN STD_LOGIC; + phy_rstn : IN STD_LOGIC; + phy_srst : IN STD_LOGIC; + phystatus0 : IN STD_LOGIC; + phystatus1 : IN STD_LOGIC; + phystatus2 : IN STD_LOGIC; + phystatus3 : IN STD_LOGIC; + phystatus4 : IN STD_LOGIC; + phystatus5 : IN STD_LOGIC; + phystatus6 : IN STD_LOGIC; + phystatus7 : IN STD_LOGIC; + pld_clk : IN STD_LOGIC; + pld_rstn : IN STD_LOGIC; + pld_srst : IN STD_LOGIC; + powerdown0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown1 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown2 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown3 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown4 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown5 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown6 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown7 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + prstn : OUT STD_LOGIC; + rate : OUT STD_LOGIC; + reset_status : OUT STD_LOGIC; + rx_bar_dec_vc0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_bar_dec_vc1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc0_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc0_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc1_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc1_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_data_vc0_0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_data_vc0_1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_data_vc1_0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_data_vc1_1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_eop_vc0_0 : OUT STD_LOGIC; + rx_eop_vc0_1 : OUT STD_LOGIC; + rx_eop_vc1_0 : OUT STD_LOGIC; + rx_eop_vc1_1 : OUT STD_LOGIC; + rx_err_vc0 : OUT STD_LOGIC; + rx_err_vc1 : OUT STD_LOGIC; + rx_fifo_empty_vc0 : OUT STD_LOGIC; + rx_fifo_empty_vc1 : OUT STD_LOGIC; + rx_fifo_full_vc0 : OUT STD_LOGIC; + rx_fifo_full_vc1 : OUT STD_LOGIC; + rx_fifo_rdp0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_fifo_rdp1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_fifo_wrp0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_fifo_wrp1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_mask_vc0 : IN STD_LOGIC; + rx_mask_vc1 : IN STD_LOGIC; + rx_ready_vc0 : IN STD_LOGIC; + rx_ready_vc1 : IN STD_LOGIC; + rx_sop_vc0_0 : OUT STD_LOGIC; + rx_sop_vc0_1 : OUT STD_LOGIC; + rx_sop_vc1_0 : OUT STD_LOGIC; + rx_sop_vc1_1 : OUT STD_LOGIC; + rx_valid_vc0 : OUT STD_LOGIC; + rx_valid_vc1 : OUT STD_LOGIC; + rxdata0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata3 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata4 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata5 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata6 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata7 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdatak0 : IN STD_LOGIC; + rxdatak1 : IN STD_LOGIC; + rxdatak2 : IN STD_LOGIC; + rxdatak3 : IN STD_LOGIC; + rxdatak4 : IN STD_LOGIC; + rxdatak5 : IN STD_LOGIC; + rxdatak6 : IN STD_LOGIC; + rxdatak7 : IN STD_LOGIC; + rxelecidle0 : IN STD_LOGIC; + rxelecidle1 : IN STD_LOGIC; + rxelecidle2 : IN STD_LOGIC; + rxelecidle3 : IN STD_LOGIC; + rxelecidle4 : IN STD_LOGIC; + rxelecidle5 : IN STD_LOGIC; + rxelecidle6 : IN STD_LOGIC; + rxelecidle7 : IN STD_LOGIC; + rxpolarity0 : OUT STD_LOGIC; + rxpolarity1 : OUT STD_LOGIC; + rxpolarity2 : OUT STD_LOGIC; + rxpolarity3 : OUT STD_LOGIC; + rxpolarity4 : OUT STD_LOGIC; + rxpolarity5 : OUT STD_LOGIC; + rxpolarity6 : OUT STD_LOGIC; + rxpolarity7 : OUT STD_LOGIC; + rxstatus0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus1 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus2 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus3 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus4 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus5 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus6 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus7 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxvalid0 : IN STD_LOGIC; + rxvalid1 : IN STD_LOGIC; + rxvalid2 : IN STD_LOGIC; + rxvalid3 : IN STD_LOGIC; + rxvalid4 : IN STD_LOGIC; + rxvalid5 : IN STD_LOGIC; + rxvalid6 : IN STD_LOGIC; + rxvalid7 : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + serr_out : OUT STD_LOGIC; + successful_speed_negotiation_int : OUT STD_LOGIC; + swdn_in : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + swdn_wake : OUT STD_LOGIC; + swup_hotrst : OUT STD_LOGIC; + swup_in : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + test_in_hip : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + test_out_hip : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + tl_aer_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_app_inta_ack : OUT STD_LOGIC; + tl_app_inta_sts : IN STD_LOGIC; + tl_app_msi_ack : OUT STD_LOGIC; + tl_app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_app_msi_req : IN STD_LOGIC; + tl_app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + tl_cfg_ctl_wr : OUT STD_LOGIC; + tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0); + tl_cfg_sts_wr : OUT STD_LOGIC; + tl_hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_pm_auxpwr : IN STD_LOGIC; + tl_pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + tl_pm_event : IN STD_LOGIC; + tl_pme_to_cr : IN STD_LOGIC; + tl_pme_to_sr : OUT STD_LOGIC; + tl_slotclk_cfg : IN STD_LOGIC; + tx_cred_vc0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0); + tx_cred_vc1 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0); + tx_data_vc0_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_data_vc0_1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_data_vc1_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_data_vc1_1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_deemph : OUT STD_LOGIC; + tx_eop_vc0_0 : IN STD_LOGIC; + tx_eop_vc0_1 : IN STD_LOGIC; + tx_eop_vc1_0 : IN STD_LOGIC; + tx_eop_vc1_1 : IN STD_LOGIC; + tx_err_vc0 : IN STD_LOGIC; + tx_err_vc1 : IN STD_LOGIC; + tx_fifo_empty_vc0 : OUT STD_LOGIC; + tx_fifo_empty_vc1 : OUT STD_LOGIC; + tx_fifo_full_vc0 : OUT STD_LOGIC; + tx_fifo_full_vc1 : OUT STD_LOGIC; + tx_fifo_rdp_vc0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_fifo_rdp_vc1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_fifo_wrp_vc0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_fifo_wrp_vc1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_margin : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + tx_ready_vc0 : OUT STD_LOGIC; + tx_ready_vc1 : OUT STD_LOGIC; + tx_sop_vc0_0 : IN STD_LOGIC; + tx_sop_vc0_1 : IN STD_LOGIC; + tx_sop_vc1_0 : IN STD_LOGIC; + tx_sop_vc1_1 : IN STD_LOGIC; + tx_valid_vc0 : IN STD_LOGIC; + tx_valid_vc1 : IN STD_LOGIC; + txcompl0 : OUT STD_LOGIC; + txcompl1 : OUT STD_LOGIC; + txcompl2 : OUT STD_LOGIC; + txcompl3 : OUT STD_LOGIC; + txcompl4 : OUT STD_LOGIC; + txcompl5 : OUT STD_LOGIC; + txcompl6 : OUT STD_LOGIC; + txcompl7 : OUT STD_LOGIC; + txdata0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata3 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata4 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata5 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata6 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata7 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdatak0 : OUT STD_LOGIC; + txdatak1 : OUT STD_LOGIC; + txdatak2 : OUT STD_LOGIC; + txdatak3 : OUT STD_LOGIC; + txdatak4 : OUT STD_LOGIC; + txdatak5 : OUT STD_LOGIC; + txdatak6 : OUT STD_LOGIC; + txdatak7 : OUT STD_LOGIC; + txdetectrx0 : OUT STD_LOGIC; + txdetectrx1 : OUT STD_LOGIC; + txdetectrx2 : OUT STD_LOGIC; + txdetectrx3 : OUT STD_LOGIC; + txdetectrx4 : OUT STD_LOGIC; + txdetectrx5 : OUT STD_LOGIC; + txdetectrx6 : OUT STD_LOGIC; + txdetectrx7 : OUT STD_LOGIC; + txelecidle0 : OUT STD_LOGIC; + txelecidle1 : OUT STD_LOGIC; + txelecidle2 : OUT STD_LOGIC; + txelecidle3 : OUT STD_LOGIC; + txelecidle4 : OUT STD_LOGIC; + txelecidle5 : OUT STD_LOGIC; + txelecidle6 : OUT STD_LOGIC; + txelecidle7 : OUT STD_LOGIC; + urstn : OUT STD_LOGIC; + usrst : OUT STD_LOGIC; + wake_oen : OUT STD_LOGIC; + wren_rcv0 : OUT STD_LOGIC; + wren_rcv1 : OUT STD_LOGIC; + wren_rpl : OUT STD_LOGIC + ); + END cycloneiv_pciehip_pciexp_top_hip; + + ARCHITECTURE RTL OF cycloneiv_pciehip_pciexp_top_hip IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1; + SIGNAL niOO0011l71 : STD_LOGIC := '0'; + SIGNAL niOO0011l72 : STD_LOGIC := '0'; + SIGNAL niOO01O1l75 : STD_LOGIC := '0'; + SIGNAL niOO01O1l76 : STD_LOGIC := '0'; + SIGNAL niOO01O1O73 : STD_LOGIC := '0'; + SIGNAL niOO01O1O74 : STD_LOGIC := '0'; + SIGNAL niOO0ilil69 : STD_LOGIC := '0'; + SIGNAL niOO0ilil70 : STD_LOGIC := '0'; + SIGNAL niOO0iliO67 : STD_LOGIC := '0'; + SIGNAL niOO0iliO68 : STD_LOGIC := '0'; + SIGNAL niOO0illi65 : STD_LOGIC := '0'; + SIGNAL niOO0illi66 : STD_LOGIC := '0'; + SIGNAL niOO0iOiO63 : STD_LOGIC := '0'; + SIGNAL niOO0iOiO64 : STD_LOGIC := '0'; + SIGNAL niOO0iOli61 : STD_LOGIC := '0'; + SIGNAL niOO0iOli62 : STD_LOGIC := '0'; + SIGNAL niOO0l0ii51 : STD_LOGIC := '0'; + SIGNAL niOO0l0ii52 : STD_LOGIC := '0'; + SIGNAL niOO0l1ll59 : STD_LOGIC := '0'; + SIGNAL niOO0l1ll60 : STD_LOGIC := '0'; + SIGNAL niOO0l1lO57 : STD_LOGIC := '0'; + SIGNAL niOO0l1lO58 : STD_LOGIC := '0'; + SIGNAL niOO0l1Oi55 : STD_LOGIC := '0'; + SIGNAL niOO0l1Oi56 : STD_LOGIC := '0'; + SIGNAL niOO0l1Ol53 : STD_LOGIC := '0'; + SIGNAL niOO0l1Ol54 : STD_LOGIC := '0'; + SIGNAL niOO0ll0l49 : STD_LOGIC := '0'; + SIGNAL niOO0ll0l50 : STD_LOGIC := '0'; + SIGNAL niOO0ll0O47 : STD_LOGIC := '0'; + SIGNAL niOO0ll0O48 : STD_LOGIC := '0'; + SIGNAL niOO0llii45 : STD_LOGIC := '0'; + SIGNAL niOO0llii46 : STD_LOGIC := '0'; + SIGNAL niOO0llil43 : STD_LOGIC := '0'; + SIGNAL niOO0llil44 : STD_LOGIC := '0'; + SIGNAL niOO0llli41 : STD_LOGIC := '0'; + SIGNAL niOO0llli42 : STD_LOGIC := '0'; + SIGNAL niOO0llOl39 : STD_LOGIC := '0'; + SIGNAL niOO0llOl40 : STD_LOGIC := '0'; + SIGNAL wire_niOO0llOl40_w_lg_w_lg_q1262w1263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0llOl40_w_lg_q1262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0llOO37 : STD_LOGIC := '0'; + SIGNAL niOO0llOO38 : STD_LOGIC := '0'; + SIGNAL wire_niOO0llOO38_w_lg_w_lg_q1253w1254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0llOO38_w_lg_q1253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lO0i29 : STD_LOGIC := '0'; + SIGNAL niOO0lO0i30 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lO0i30_w_lg_w_lg_q1179w1180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lO0i30_w_lg_q1179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lO0l27 : STD_LOGIC := '0'; + SIGNAL niOO0lO0l28 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lO0l28_w_lg_w_lg_q1167w1168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lO0l28_w_lg_q1167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lO0O25 : STD_LOGIC := '0'; + SIGNAL niOO0lO0O26 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lO0O26_w_lg_w_lg_q1164w1165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lO0O26_w_lg_q1164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lO1i35 : STD_LOGIC := '0'; + SIGNAL niOO0lO1i36 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lO1i36_w_lg_w_lg_q1245w1246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lO1i36_w_lg_q1245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lO1l33 : STD_LOGIC := '0'; + SIGNAL niOO0lO1l34 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lO1l34_w_lg_w_lg_q1217w1218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lO1l34_w_lg_q1217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lO1O31 : STD_LOGIC := '0'; + SIGNAL niOO0lO1O32 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lO1O32_w_lg_w_lg_q1190w1191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lO1O32_w_lg_q1190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lOii23 : STD_LOGIC := '0'; + SIGNAL niOO0lOii24 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lOii24_w_lg_w_lg_q1146w1147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lOii24_w_lg_q1146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lOil21 : STD_LOGIC := '0'; + SIGNAL niOO0lOil22 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lOil22_w_lg_w_lg_q1136w1137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lOil22_w_lg_q1136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lOiO19 : STD_LOGIC := '0'; + SIGNAL niOO0lOiO20 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lOiO20_w_lg_w_lg_q1127w1128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lOiO20_w_lg_q1127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lOli17 : STD_LOGIC := '0'; + SIGNAL niOO0lOli18 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lOli18_w_lg_w_lg_q1120w1121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lOli18_w_lg_q1120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lOll15 : STD_LOGIC := '0'; + SIGNAL niOO0lOll16 : STD_LOGIC := '0'; + SIGNAL wire_niOO0lOll16_w_lg_w_lg_q1114w1115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOO0lOll16_w_lg_q1114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOO0lOOO13 : STD_LOGIC := '0'; + SIGNAL niOO0lOOO14 : STD_LOGIC := '0'; + SIGNAL niOO0O01i3 : STD_LOGIC := '0'; + SIGNAL niOO0O01i4 : STD_LOGIC := '0'; + SIGNAL niOO0O01O1 : STD_LOGIC := '0'; + SIGNAL niOO0O01O2 : STD_LOGIC := '0'; + SIGNAL niOO0O10i11 : STD_LOGIC := '0'; + SIGNAL niOO0O10i12 : STD_LOGIC := '0'; + SIGNAL niOO0O1ii10 : STD_LOGIC := '0'; + SIGNAL niOO0O1ii9 : STD_LOGIC := '0'; + SIGNAL niOO0O1iO7 : STD_LOGIC := '0'; + SIGNAL niOO0O1iO8 : STD_LOGIC := '0'; + SIGNAL niOO0O1Oi5 : STD_LOGIC := '0'; + SIGNAL niOO0O1Oi6 : STD_LOGIC := '0'; + SIGNAL niOO10Oli79 : STD_LOGIC := '0'; + SIGNAL niOO10Oli80 : STD_LOGIC := '0'; + SIGNAL niOO10Oll77 : STD_LOGIC := '0'; + SIGNAL niOO10Oll78 : STD_LOGIC := '0'; + SIGNAL n0OOOii : STD_LOGIC := '0'; + SIGNAL n1llOii : STD_LOGIC := '0'; + SIGNAL n1lO00i : STD_LOGIC := '0'; + SIGNAL n1lO01l : STD_LOGIC := '0'; + SIGNAL n1lO01O : STD_LOGIC := '0'; + SIGNAL n1lOi0i : STD_LOGIC := '0'; + SIGNAL n1lOiiO : STD_LOGIC := '0'; + SIGNAL n1lOili : STD_LOGIC := '0'; + SIGNAL n1lOill : STD_LOGIC := '0'; + SIGNAL n1lOilO : STD_LOGIC := '0'; + SIGNAL n1lOiOi : STD_LOGIC := '0'; + SIGNAL n1lOiOl : STD_LOGIC := '0'; + SIGNAL n1lOiOO : STD_LOGIC := '0'; + SIGNAL n1lOl0i : STD_LOGIC := '0'; + SIGNAL n1lOl0l : STD_LOGIC := '0'; + SIGNAL n1lOl0O : STD_LOGIC := '0'; + SIGNAL n1lOl1i : STD_LOGIC := '0'; + SIGNAL n1lOl1l : STD_LOGIC := '0'; + SIGNAL n1lOl1O : STD_LOGIC := '0'; + SIGNAL n1lOlii : STD_LOGIC := '0'; + SIGNAL n1lOlil : STD_LOGIC := '0'; + SIGNAL n1lOliO : STD_LOGIC := '0'; + SIGNAL n1lOlli : STD_LOGIC := '0'; + SIGNAL n1lOlll : STD_LOGIC := '0'; + SIGNAL n1lOllO : STD_LOGIC := '0'; + SIGNAL n1lOlOi : STD_LOGIC := '0'; + SIGNAL n1lOlOl : STD_LOGIC := '0'; + SIGNAL n1lOlOO : STD_LOGIC := '0'; + SIGNAL n1lOO1i : STD_LOGIC := '0'; + SIGNAL n1lOO1l : STD_LOGIC := '0'; + SIGNAL n1O0l0O : STD_LOGIC := '0'; + SIGNAL n1O0liO : STD_LOGIC := '0'; + SIGNAL n1O0O0i : STD_LOGIC := '0'; + SIGNAL n1O0O0l : STD_LOGIC := '0'; + SIGNAL n1O0O0O : STD_LOGIC := '0'; + SIGNAL n1O0O1i : STD_LOGIC := '0'; + SIGNAL n1O0O1l : STD_LOGIC := '0'; + SIGNAL n1O0O1O : STD_LOGIC := '0'; + SIGNAL n1O0Oii : STD_LOGIC := '0'; + SIGNAL n1O0Oil : STD_LOGIC := '0'; + SIGNAL n1O0OiO : STD_LOGIC := '0'; + SIGNAL n1O0Oli : STD_LOGIC := '0'; + SIGNAL n1O0Oll : STD_LOGIC := '0'; + SIGNAL n1O0OlO : STD_LOGIC := '0'; + SIGNAL n1O0OOi : STD_LOGIC := '0'; + SIGNAL n1O0OOl : STD_LOGIC := '0'; + SIGNAL n1O0OOO : STD_LOGIC := '0'; + SIGNAL n1Oi00i : STD_LOGIC := '0'; + SIGNAL n1Oi00l : STD_LOGIC := '0'; + SIGNAL n1Oi00O : STD_LOGIC := '0'; + SIGNAL n1Oi01i : STD_LOGIC := '0'; + SIGNAL n1Oi01l : STD_LOGIC := '0'; + SIGNAL n1Oi01O : STD_LOGIC := '0'; + SIGNAL n1Oi0ii : STD_LOGIC := '0'; + SIGNAL n1Oi0il : STD_LOGIC := '0'; + SIGNAL n1Oi0iO : STD_LOGIC := '0'; + SIGNAL n1Oi0li : STD_LOGIC := '0'; + SIGNAL n1Oi0ll : STD_LOGIC := '0'; + SIGNAL n1Oi0lO : STD_LOGIC := '0'; + SIGNAL n1Oi0Oi : STD_LOGIC := '0'; + SIGNAL n1Oi0Ol : STD_LOGIC := '0'; + SIGNAL n1Oi0OO : STD_LOGIC := '0'; + SIGNAL n1Oi10i : STD_LOGIC := '0'; + SIGNAL n1Oi10l : STD_LOGIC := '0'; + SIGNAL n1Oi10O : STD_LOGIC := '0'; + SIGNAL n1Oi11i : STD_LOGIC := '0'; + SIGNAL n1Oi11l : STD_LOGIC := '0'; + SIGNAL n1Oi11O : STD_LOGIC := '0'; + SIGNAL n1Oi1ii : STD_LOGIC := '0'; + SIGNAL n1Oi1il : STD_LOGIC := '0'; + SIGNAL n1Oi1iO : STD_LOGIC := '0'; + SIGNAL n1Oi1li : STD_LOGIC := '0'; + SIGNAL n1Oi1ll : STD_LOGIC := '0'; + SIGNAL n1Oi1lO : STD_LOGIC := '0'; + SIGNAL n1Oi1Oi : STD_LOGIC := '0'; + SIGNAL n1Oi1Ol : STD_LOGIC := '0'; + SIGNAL n1Oi1OO : STD_LOGIC := '0'; + SIGNAL n1Oii0i : STD_LOGIC := '0'; + SIGNAL n1Oii0l : STD_LOGIC := '0'; + SIGNAL n1Oii0O : STD_LOGIC := '0'; + SIGNAL n1Oii1i : STD_LOGIC := '0'; + SIGNAL n1Oii1l : STD_LOGIC := '0'; + SIGNAL n1Oii1O : STD_LOGIC := '0'; + SIGNAL n1Oiiii : STD_LOGIC := '0'; + SIGNAL n1Oiiil : STD_LOGIC := '0'; + SIGNAL n1OiiiO : STD_LOGIC := '0'; + SIGNAL n1Oiili : STD_LOGIC := '0'; + SIGNAL n1Oiill : STD_LOGIC := '0'; + SIGNAL n1OiilO : STD_LOGIC := '0'; + SIGNAL n1OiiOi : STD_LOGIC := '0'; + SIGNAL n1OiiOl : STD_LOGIC := '0'; + SIGNAL n1OiiOO : STD_LOGIC := '0'; + SIGNAL n1Oil0i : STD_LOGIC := '0'; + SIGNAL n1Oil0l : STD_LOGIC := '0'; + SIGNAL n1Oil0O : STD_LOGIC := '0'; + SIGNAL n1Oil1i : STD_LOGIC := '0'; + SIGNAL n1Oil1l : STD_LOGIC := '0'; + SIGNAL n1Oil1O : STD_LOGIC := '0'; + SIGNAL n1Oilii : STD_LOGIC := '0'; + SIGNAL n1Oilil : STD_LOGIC := '0'; + SIGNAL n1OiliO : STD_LOGIC := '0'; + SIGNAL n1Oilli : STD_LOGIC := '0'; + SIGNAL n1Oilll : STD_LOGIC := '0'; + SIGNAL n1OillO : STD_LOGIC := '0'; + SIGNAL n1OilOi : STD_LOGIC := '0'; + SIGNAL n1OilOl : STD_LOGIC := '0'; + SIGNAL n1OilOO : STD_LOGIC := '0'; + SIGNAL n1OiO0i : STD_LOGIC := '0'; + SIGNAL n1OiO0l : STD_LOGIC := '0'; + SIGNAL n1OiO0O : STD_LOGIC := '0'; + SIGNAL n1OiO1i : STD_LOGIC := '0'; + SIGNAL n1OiO1l : STD_LOGIC := '0'; + SIGNAL n1OiO1O : STD_LOGIC := '0'; + SIGNAL n1OiOii : STD_LOGIC := '0'; + SIGNAL n1OiOil : STD_LOGIC := '0'; + SIGNAL n1OiOiO : STD_LOGIC := '0'; + SIGNAL n1OiOli : STD_LOGIC := '0'; + SIGNAL n1OiOll : STD_LOGIC := '0'; + SIGNAL n1OiOlO : STD_LOGIC := '0'; + SIGNAL n1OiOOi : STD_LOGIC := '0'; + SIGNAL n1OiOOl : STD_LOGIC := '0'; + SIGNAL n1OiOOO : STD_LOGIC := '0'; + SIGNAL n1Ol00i : STD_LOGIC := '0'; + SIGNAL n1Ol00l : STD_LOGIC := '0'; + SIGNAL n1Ol00O : STD_LOGIC := '0'; + SIGNAL n1Ol01i : STD_LOGIC := '0'; + SIGNAL n1Ol01l : STD_LOGIC := '0'; + SIGNAL n1Ol01O : STD_LOGIC := '0'; + SIGNAL n1Ol0ii : STD_LOGIC := '0'; + SIGNAL n1Ol0il : STD_LOGIC := '0'; + SIGNAL n1Ol0iO : STD_LOGIC := '0'; + SIGNAL n1Ol0li : STD_LOGIC := '0'; + SIGNAL n1Ol0ll : STD_LOGIC := '0'; + SIGNAL n1Ol0lO : STD_LOGIC := '0'; + SIGNAL n1Ol0Oi : STD_LOGIC := '0'; + SIGNAL n1Ol0Ol : STD_LOGIC := '0'; + SIGNAL n1Ol0OO : STD_LOGIC := '0'; + SIGNAL n1Ol10i : STD_LOGIC := '0'; + SIGNAL n1Ol10l : STD_LOGIC := '0'; + SIGNAL n1Ol10O : STD_LOGIC := '0'; + SIGNAL n1Ol11i : STD_LOGIC := '0'; + SIGNAL n1Ol11l : STD_LOGIC := '0'; + SIGNAL n1Ol11O : STD_LOGIC := '0'; + SIGNAL n1Ol1ii : STD_LOGIC := '0'; + SIGNAL n1Ol1il : STD_LOGIC := '0'; + SIGNAL n1Ol1iO : STD_LOGIC := '0'; + SIGNAL n1Ol1li : STD_LOGIC := '0'; + SIGNAL n1Ol1ll : STD_LOGIC := '0'; + SIGNAL n1Ol1lO : STD_LOGIC := '0'; + SIGNAL n1Ol1Oi : STD_LOGIC := '0'; + SIGNAL n1Ol1Ol : STD_LOGIC := '0'; + SIGNAL n1Ol1OO : STD_LOGIC := '0'; + SIGNAL n1Oli0i : STD_LOGIC := '0'; + SIGNAL n1Oli0l : STD_LOGIC := '0'; + SIGNAL n1Oli0O : STD_LOGIC := '0'; + SIGNAL n1Oli1i : STD_LOGIC := '0'; + SIGNAL n1Oli1l : STD_LOGIC := '0'; + SIGNAL n1Oli1O : STD_LOGIC := '0'; + SIGNAL n1Oliii : STD_LOGIC := '0'; + SIGNAL n1Oliil : STD_LOGIC := '0'; + SIGNAL n1OliiO : STD_LOGIC := '0'; + SIGNAL n1Olili : STD_LOGIC := '0'; + SIGNAL n1Olill : STD_LOGIC := '0'; + SIGNAL n1OlilO : STD_LOGIC := '0'; + SIGNAL n1OliOi : STD_LOGIC := '0'; + SIGNAL n1OliOl : STD_LOGIC := '0'; + SIGNAL n1OliOO : STD_LOGIC := '0'; + SIGNAL n1Oll0i : STD_LOGIC := '0'; + SIGNAL n1Oll0l : STD_LOGIC := '0'; + SIGNAL n1Oll0O : STD_LOGIC := '0'; + SIGNAL n1Oll1i : STD_LOGIC := '0'; + SIGNAL n1Oll1l : STD_LOGIC := '0'; + SIGNAL n1Oll1O : STD_LOGIC := '0'; + SIGNAL n1Ollii : STD_LOGIC := '0'; + SIGNAL n1Ollil : STD_LOGIC := '0'; + SIGNAL n1OlliO : STD_LOGIC := '0'; + SIGNAL n1Ollli : STD_LOGIC := '0'; + SIGNAL n1Ollll : STD_LOGIC := '0'; + SIGNAL n1OlllO : STD_LOGIC := '0'; + SIGNAL n1OllOi : STD_LOGIC := '0'; + SIGNAL n1OllOl : STD_LOGIC := '0'; + SIGNAL n1OllOO : STD_LOGIC := '0'; + SIGNAL n1OlO0i : STD_LOGIC := '0'; + SIGNAL n1OlO0l : STD_LOGIC := '0'; + SIGNAL n1OlO0O : STD_LOGIC := '0'; + SIGNAL n1OlO1i : STD_LOGIC := '0'; + SIGNAL n1OlO1l : STD_LOGIC := '0'; + SIGNAL n1OlO1O : STD_LOGIC := '0'; + SIGNAL n1OlOii : STD_LOGIC := '0'; + SIGNAL n1OlOil : STD_LOGIC := '0'; + SIGNAL ni01lll : STD_LOGIC := '0'; + SIGNAL ni01llO : STD_LOGIC := '0'; + SIGNAL ni01lOl : STD_LOGIC := '0'; + SIGNAL ni10iii : STD_LOGIC := '0'; + SIGNAL ni10ilO : STD_LOGIC := '0'; + SIGNAL ni10iOi : STD_LOGIC := '0'; + SIGNAL ni10iOl : STD_LOGIC := '0'; + SIGNAL ni10iOO : STD_LOGIC := '0'; + SIGNAL ni10l0i : STD_LOGIC := '0'; + SIGNAL ni10l0l : STD_LOGIC := '0'; + SIGNAL ni10l0O : STD_LOGIC := '0'; + SIGNAL ni10l1i : STD_LOGIC := '0'; + SIGNAL ni10l1l : STD_LOGIC := '0'; + SIGNAL ni10l1O : STD_LOGIC := '0'; + SIGNAL ni10lii : STD_LOGIC := '0'; + SIGNAL ni10lil : STD_LOGIC := '0'; + SIGNAL ni10liO : STD_LOGIC := '0'; + SIGNAL ni10llO : STD_LOGIC := '0'; + SIGNAL ni10lOi : STD_LOGIC := '0'; + SIGNAL ni10O0i : STD_LOGIC := '0'; + SIGNAL ni10O0l : STD_LOGIC := '0'; + SIGNAL ni10O0O : STD_LOGIC := '0'; + SIGNAL ni10O1i : STD_LOGIC := '0'; + SIGNAL ni10O1l : STD_LOGIC := '0'; + SIGNAL ni10O1O : STD_LOGIC := '0'; + SIGNAL ni10Oii : STD_LOGIC := '0'; + SIGNAL ni1lOOl : STD_LOGIC := '0'; + SIGNAL wire_ni01lOi_PRN : STD_LOGIC; + SIGNAL wire_ni01lOi_w3816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_w_lg_w_lg_w_lg_n1lOlOl3806w3807w3810w3813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_w_lg_w_lg_n1lOlOl3806w3807w3810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_n1lO00i3832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_w_lg_n1lOlOl3806w3807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_w_lg_n1lOlOO3808w3809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_w_lg_n1lOO1i3811w3812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_w_lg_n1lOO1l3814w3815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_n1lOi0i3805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_n1lOO1l3771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_ni10l0l762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_ni10liO2719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_n1lOlOl3806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_n1lOlOO3808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_n1lOO1i3811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01lOi_w_lg_n1lOO1l3814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL ni10lli : STD_LOGIC := '0'; + SIGNAL ni10lll : STD_LOGIC := '0'; + SIGNAL ni10lOO : STD_LOGIC := '0'; + SIGNAL wire_ni10lOl_CLRN : STD_LOGIC; + SIGNAL wire_ni10lOl_PRN : STD_LOGIC; + SIGNAL n1lOO0l : STD_LOGIC := '0'; + SIGNAL n1lOO0O : STD_LOGIC := '0'; + SIGNAL n1lOO1O : STD_LOGIC := '0'; + SIGNAL n1lOOii : STD_LOGIC := '0'; + SIGNAL ni1100l : STD_LOGIC := '0'; + SIGNAL ni1100O : STD_LOGIC := '0'; + SIGNAL ni1101i : STD_LOGIC := '0'; + SIGNAL ni11llO : STD_LOGIC := '0'; + SIGNAL wire_ni11lll_PRN : STD_LOGIC; + SIGNAL n0OOOiO : STD_LOGIC := '0'; + SIGNAL n1llOiO : STD_LOGIC := '0'; + SIGNAL n1lO00l : STD_LOGIC := '0'; + SIGNAL n1lO00O : STD_LOGIC := '0'; + SIGNAL n1lO01i : STD_LOGIC := '0'; + SIGNAL n1lOO0i : STD_LOGIC := '0'; + SIGNAL ni11lli : STD_LOGIC := '0'; + SIGNAL ni11lOi : STD_LOGIC := '0'; + SIGNAL ni11lOl : STD_LOGIC := '0'; + SIGNAL ni11O1i : STD_LOGIC := '0'; + SIGNAL wire_ni11lOO_CLRN : STD_LOGIC; + SIGNAL wire_ni11lOO_PRN : STD_LOGIC; + SIGNAL n0Oli1i : STD_LOGIC := '0'; + SIGNAL n1O1lOO : STD_LOGIC := '0'; + SIGNAL n1O1O0i : STD_LOGIC := '0'; + SIGNAL n1O1O1i : STD_LOGIC := '0'; + SIGNAL ni1llil : STD_LOGIC := '0'; + SIGNAL wire_ni1llii_CLRN : STD_LOGIC; + SIGNAL wire_ni1llii_PRN : STD_LOGIC; + SIGNAL wire_ni1llii_w_lg_n0Oli1i3408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_n0Oli1i3428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_ni1llil2426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_ni1llil2568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_ni1llil2431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_w_lg_n0Oli1i3428w3431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_w_lg_ni1llil2426w2427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_n0Oli1i3312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1llii_w_lg_n0Oli1i3331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n0il00i : STD_LOGIC := '0'; + SIGNAL n0il00l : STD_LOGIC := '0'; + SIGNAL n0il00O : STD_LOGIC := '0'; + SIGNAL n0il01i : STD_LOGIC := '0'; + SIGNAL n0il01l : STD_LOGIC := '0'; + SIGNAL n0il01O : STD_LOGIC := '0'; + SIGNAL n0il0ii : STD_LOGIC := '0'; + SIGNAL n0il0il : STD_LOGIC := '0'; + SIGNAL n0il0iO : STD_LOGIC := '0'; + SIGNAL n0il0li : STD_LOGIC := '0'; + SIGNAL n0il0ll : STD_LOGIC := '0'; + SIGNAL n0il0lO : STD_LOGIC := '0'; + SIGNAL n0il0Oi : STD_LOGIC := '0'; + SIGNAL n0il0Ol : STD_LOGIC := '0'; + SIGNAL n0il0OO : STD_LOGIC := '0'; + SIGNAL n0il10O : STD_LOGIC := '0'; + SIGNAL n0il1ii : STD_LOGIC := '0'; + SIGNAL n0il1il : STD_LOGIC := '0'; + SIGNAL n0il1iO : STD_LOGIC := '0'; + SIGNAL n0il1li : STD_LOGIC := '0'; + SIGNAL n0il1ll : STD_LOGIC := '0'; + SIGNAL n0il1lO : STD_LOGIC := '0'; + SIGNAL n0il1Oi : STD_LOGIC := '0'; + SIGNAL n0il1Ol : STD_LOGIC := '0'; + SIGNAL n0il1OO : STD_LOGIC := '0'; + SIGNAL n0ili0i : STD_LOGIC := '0'; + SIGNAL n0ili0l : STD_LOGIC := '0'; + SIGNAL n0ili0O : STD_LOGIC := '0'; + SIGNAL n0ili1i : STD_LOGIC := '0'; + SIGNAL n0ili1l : STD_LOGIC := '0'; + SIGNAL n0ili1O : STD_LOGIC := '0'; + SIGNAL n0iliii : STD_LOGIC := '0'; + SIGNAL n0iliil : STD_LOGIC := '0'; + SIGNAL n0iliiO : STD_LOGIC := '0'; + SIGNAL n0ilili : STD_LOGIC := '0'; + SIGNAL n0ilill : STD_LOGIC := '0'; + SIGNAL n0ililO : STD_LOGIC := '0'; + SIGNAL n0iliOi : STD_LOGIC := '0'; + SIGNAL n0iliOl : STD_LOGIC := '0'; + SIGNAL n0iliOO : STD_LOGIC := '0'; + SIGNAL n0ill0i : STD_LOGIC := '0'; + SIGNAL n0ill0l : STD_LOGIC := '0'; + SIGNAL n0ill0O : STD_LOGIC := '0'; + SIGNAL n0ill1i : STD_LOGIC := '0'; + SIGNAL n0ill1l : STD_LOGIC := '0'; + SIGNAL n0ill1O : STD_LOGIC := '0'; + SIGNAL n0illii : STD_LOGIC := '0'; + SIGNAL n0illil : STD_LOGIC := '0'; + SIGNAL n0illiO : STD_LOGIC := '0'; + SIGNAL n0illli : STD_LOGIC := '0'; + SIGNAL n0illll : STD_LOGIC := '0'; + SIGNAL n0illlO : STD_LOGIC := '0'; + SIGNAL n0illOi : STD_LOGIC := '0'; + SIGNAL n0illOl : STD_LOGIC := '0'; + SIGNAL n0illOO : STD_LOGIC := '0'; + SIGNAL n0ilO0i : STD_LOGIC := '0'; + SIGNAL n0ilO0l : STD_LOGIC := '0'; + SIGNAL n0ilO0O : STD_LOGIC := '0'; + SIGNAL n0ilO1i : STD_LOGIC := '0'; + SIGNAL n0ilO1l : STD_LOGIC := '0'; + SIGNAL n0ilO1O : STD_LOGIC := '0'; + SIGNAL n0ilOii : STD_LOGIC := '0'; + SIGNAL n0ilOil : STD_LOGIC := '0'; + SIGNAL n0ilOiO : STD_LOGIC := '0'; + SIGNAL n0ilOli : STD_LOGIC := '0'; + SIGNAL n0ilOll : STD_LOGIC := '0'; + SIGNAL n0ilOlO : STD_LOGIC := '0'; + SIGNAL n0ilOOi : STD_LOGIC := '0'; + SIGNAL n0ilOOl : STD_LOGIC := '0'; + SIGNAL n0ilOOO : STD_LOGIC := '0'; + SIGNAL n0iO00i : STD_LOGIC := '0'; + SIGNAL n0iO00l : STD_LOGIC := '0'; + SIGNAL n0iO00O : STD_LOGIC := '0'; + SIGNAL n0iO01i : STD_LOGIC := '0'; + SIGNAL n0iO01l : STD_LOGIC := '0'; + SIGNAL n0iO01O : STD_LOGIC := '0'; + SIGNAL n0iO0ii : STD_LOGIC := '0'; + SIGNAL n0iO0il : STD_LOGIC := '0'; + SIGNAL n0iO0iO : STD_LOGIC := '0'; + SIGNAL n0iO0li : STD_LOGIC := '0'; + SIGNAL n0iO0ll : STD_LOGIC := '0'; + SIGNAL n0iO0lO : STD_LOGIC := '0'; + SIGNAL n0iO0Oi : STD_LOGIC := '0'; + SIGNAL n0iO0Ol : STD_LOGIC := '0'; + SIGNAL n0iO0OO : STD_LOGIC := '0'; + SIGNAL n0iO10i : STD_LOGIC := '0'; + SIGNAL n0iO10l : STD_LOGIC := '0'; + SIGNAL n0iO10O : STD_LOGIC := '0'; + SIGNAL n0iO11i : STD_LOGIC := '0'; + SIGNAL n0iO11l : STD_LOGIC := '0'; + SIGNAL n0iO11O : STD_LOGIC := '0'; + SIGNAL n0iO1ii : STD_LOGIC := '0'; + SIGNAL n0iO1il : STD_LOGIC := '0'; + SIGNAL n0iO1iO : STD_LOGIC := '0'; + SIGNAL n0iO1li : STD_LOGIC := '0'; + SIGNAL n0iO1ll : STD_LOGIC := '0'; + SIGNAL n0iO1lO : STD_LOGIC := '0'; + SIGNAL n0iO1Oi : STD_LOGIC := '0'; + SIGNAL n0iO1Ol : STD_LOGIC := '0'; + SIGNAL n0iO1OO : STD_LOGIC := '0'; + SIGNAL n0iOi0i : STD_LOGIC := '0'; + SIGNAL n0iOi0l : STD_LOGIC := '0'; + SIGNAL n0iOi0O : STD_LOGIC := '0'; + SIGNAL n0iOi1i : STD_LOGIC := '0'; + SIGNAL n0iOi1l : STD_LOGIC := '0'; + SIGNAL n0iOi1O : STD_LOGIC := '0'; + SIGNAL n0iOiii : STD_LOGIC := '0'; + SIGNAL n0iOiil : STD_LOGIC := '0'; + SIGNAL n0iOiiO : STD_LOGIC := '0'; + SIGNAL n0iOili : STD_LOGIC := '0'; + SIGNAL n0iOill : STD_LOGIC := '0'; + SIGNAL n0iOilO : STD_LOGIC := '0'; + SIGNAL n0iOiOi : STD_LOGIC := '0'; + SIGNAL n0iOiOl : STD_LOGIC := '0'; + SIGNAL n0iOiOO : STD_LOGIC := '0'; + SIGNAL n0iOl0i : STD_LOGIC := '0'; + SIGNAL n0iOl0l : STD_LOGIC := '0'; + SIGNAL n0iOl0O : STD_LOGIC := '0'; + SIGNAL n0iOl1i : STD_LOGIC := '0'; + SIGNAL n0iOl1l : STD_LOGIC := '0'; + SIGNAL n0iOl1O : STD_LOGIC := '0'; + SIGNAL n0iOlii : STD_LOGIC := '0'; + SIGNAL n0iOlil : STD_LOGIC := '0'; + SIGNAL n0iOliO : STD_LOGIC := '0'; + SIGNAL n0iOlli : STD_LOGIC := '0'; + SIGNAL n0iOlll : STD_LOGIC := '0'; + SIGNAL n0iOllO : STD_LOGIC := '0'; + SIGNAL n0iOlOi : STD_LOGIC := '0'; + SIGNAL n0iOlOl : STD_LOGIC := '0'; + SIGNAL n0iOlOO : STD_LOGIC := '0'; + SIGNAL n0iOO0i : STD_LOGIC := '0'; + SIGNAL n0iOO0l : STD_LOGIC := '0'; + SIGNAL n0iOO0O : STD_LOGIC := '0'; + SIGNAL n0iOO1i : STD_LOGIC := '0'; + SIGNAL n0iOO1l : STD_LOGIC := '0'; + SIGNAL n0iOO1O : STD_LOGIC := '0'; + SIGNAL n0iOOii : STD_LOGIC := '0'; + SIGNAL n0iOOil : STD_LOGIC := '0'; + SIGNAL n0iOOiO : STD_LOGIC := '0'; + SIGNAL n0iOOli : STD_LOGIC := '0'; + SIGNAL n0iOOll : STD_LOGIC := '0'; + SIGNAL n0iOOlO : STD_LOGIC := '0'; + SIGNAL n0iOOOi : STD_LOGIC := '0'; + SIGNAL n0iOOOl : STD_LOGIC := '0'; + SIGNAL n0iOOOO : STD_LOGIC := '0'; + SIGNAL n0l110i : STD_LOGIC := '0'; + SIGNAL n0l110l : STD_LOGIC := '0'; + SIGNAL n0l110O : STD_LOGIC := '0'; + SIGNAL n0l111i : STD_LOGIC := '0'; + SIGNAL n0l111l : STD_LOGIC := '0'; + SIGNAL n0l111O : STD_LOGIC := '0'; + SIGNAL n0l11ii : STD_LOGIC := '0'; + SIGNAL n0l11il : STD_LOGIC := '0'; + SIGNAL n0l11iO : STD_LOGIC := '0'; + SIGNAL n0l11li : STD_LOGIC := '0'; + SIGNAL n0l11ll : STD_LOGIC := '0'; + SIGNAL n0l11lO : STD_LOGIC := '0'; + SIGNAL n0Oi0il : STD_LOGIC := '0'; + SIGNAL n0Oi0iO : STD_LOGIC := '0'; + SIGNAL n0Oi0li : STD_LOGIC := '0'; + SIGNAL n0Oi0ll : STD_LOGIC := '0'; + SIGNAL n0Oi0lO : STD_LOGIC := '0'; + SIGNAL n0Oi0Oi : STD_LOGIC := '0'; + SIGNAL n0Oi0Ol : STD_LOGIC := '0'; + SIGNAL n0Oi0OO : STD_LOGIC := '0'; + SIGNAL n0Oii0i : STD_LOGIC := '0'; + SIGNAL n0Oii0l : STD_LOGIC := '0'; + SIGNAL n0Oii0O : STD_LOGIC := '0'; + SIGNAL n0Oii1i : STD_LOGIC := '0'; + SIGNAL n0Oii1l : STD_LOGIC := '0'; + SIGNAL n0Oii1O : STD_LOGIC := '0'; + SIGNAL n0Oiiii : STD_LOGIC := '0'; + SIGNAL n0Oiiil : STD_LOGIC := '0'; + SIGNAL n0OiiiO : STD_LOGIC := '0'; + SIGNAL n0Oiili : STD_LOGIC := '0'; + SIGNAL n0Oiill : STD_LOGIC := '0'; + SIGNAL n0OiOOi : STD_LOGIC := '0'; + SIGNAL n0OiOOl : STD_LOGIC := '0'; + SIGNAL n0OiOOO : STD_LOGIC := '0'; + SIGNAL n0Ol00i : STD_LOGIC := '0'; + SIGNAL n0Ol00l : STD_LOGIC := '0'; + SIGNAL n0Ol00O : STD_LOGIC := '0'; + SIGNAL n0Ol01i : STD_LOGIC := '0'; + SIGNAL n0Ol01l : STD_LOGIC := '0'; + SIGNAL n0Ol01O : STD_LOGIC := '0'; + SIGNAL n0Ol0ii : STD_LOGIC := '0'; + SIGNAL n0Ol0il : STD_LOGIC := '0'; + SIGNAL n0Ol0iO : STD_LOGIC := '0'; + SIGNAL n0Ol0li : STD_LOGIC := '0'; + SIGNAL n0Ol0ll : STD_LOGIC := '0'; + SIGNAL n0Ol0lO : STD_LOGIC := '0'; + SIGNAL n0Ol0Oi : STD_LOGIC := '0'; + SIGNAL n0Ol0Ol : STD_LOGIC := '0'; + SIGNAL n0Ol0OO : STD_LOGIC := '0'; + SIGNAL n0Ol10i : STD_LOGIC := '0'; + SIGNAL n0Ol10l : STD_LOGIC := '0'; + SIGNAL n0Ol10O : STD_LOGIC := '0'; + SIGNAL n0Ol11i : STD_LOGIC := '0'; + SIGNAL n0Ol11l : STD_LOGIC := '0'; + SIGNAL n0Ol11O : STD_LOGIC := '0'; + SIGNAL n0Ol1ii : STD_LOGIC := '0'; + SIGNAL n0Ol1il : STD_LOGIC := '0'; + SIGNAL n0Ol1iO : STD_LOGIC := '0'; + SIGNAL n0Ol1li : STD_LOGIC := '0'; + SIGNAL n0Ol1ll : STD_LOGIC := '0'; + SIGNAL n0Ol1lO : STD_LOGIC := '0'; + SIGNAL n0Ol1Oi : STD_LOGIC := '0'; + SIGNAL n0Ol1Ol : STD_LOGIC := '0'; + SIGNAL n0Ol1OO : STD_LOGIC := '0'; + SIGNAL n0OOOil : STD_LOGIC := '0'; + SIGNAL n1llOil : STD_LOGIC := '0'; + SIGNAL n1O1l0l : STD_LOGIC := '0'; + SIGNAL n1O1lli : STD_LOGIC := '0'; + SIGNAL n1O1lll : STD_LOGIC := '0'; + SIGNAL n1O1llO : STD_LOGIC := '0'; + SIGNAL n1O1lOi : STD_LOGIC := '0'; + SIGNAL n1O1lOl : STD_LOGIC := '0'; + SIGNAL n1O1O0l : STD_LOGIC := '0'; + SIGNAL n1O1O0O : STD_LOGIC := '0'; + SIGNAL n1O1O1l : STD_LOGIC := '0'; + SIGNAL n1O1O1O : STD_LOGIC := '0'; + SIGNAL n1O1Oii : STD_LOGIC := '0'; + SIGNAL n1O1Oil : STD_LOGIC := '0'; + SIGNAL n1O1OiO : STD_LOGIC := '0'; + SIGNAL n1O1Oli : STD_LOGIC := '0'; + SIGNAL n1O1Oll : STD_LOGIC := '0'; + SIGNAL ni1100i : STD_LOGIC := '0'; + SIGNAL ni1101l : STD_LOGIC := '0'; + SIGNAL ni1101O : STD_LOGIC := '0'; + SIGNAL ni11i0i : STD_LOGIC := '0'; + SIGNAL ni11iiO : STD_LOGIC := '0'; + SIGNAL ni11ili : STD_LOGIC := '0'; + SIGNAL ni11ill : STD_LOGIC := '0'; + SIGNAL ni11ilO : STD_LOGIC := '0'; + SIGNAL ni11iOi : STD_LOGIC := '0'; + SIGNAL ni11iOl : STD_LOGIC := '0'; + SIGNAL ni11iOO : STD_LOGIC := '0'; + SIGNAL ni11l0i : STD_LOGIC := '0'; + SIGNAL ni11l0l : STD_LOGIC := '0'; + SIGNAL ni11l0O : STD_LOGIC := '0'; + SIGNAL ni11l1i : STD_LOGIC := '0'; + SIGNAL ni11l1l : STD_LOGIC := '0'; + SIGNAL ni11l1O : STD_LOGIC := '0'; + SIGNAL ni11lii : STD_LOGIC := '0'; + SIGNAL ni11lil : STD_LOGIC := '0'; + SIGNAL ni11liO : STD_LOGIC := '0'; + SIGNAL ni1iO0i : STD_LOGIC := '0'; + SIGNAL ni1iOlO : STD_LOGIC := '0'; + SIGNAL ni1iOOi : STD_LOGIC := '0'; + SIGNAL ni1iOOl : STD_LOGIC := '0'; + SIGNAL ni1iOOO : STD_LOGIC := '0'; + SIGNAL ni1l11i : STD_LOGIC := '0'; + SIGNAL ni1l11l : STD_LOGIC := '0'; + SIGNAL ni1ll0l : STD_LOGIC := '0'; + SIGNAL ni1ll0O : STD_LOGIC := '0'; + SIGNAL ni1lliO : STD_LOGIC := '0'; + SIGNAL ni1llli : STD_LOGIC := '0'; + SIGNAL ni1llll : STD_LOGIC := '0'; + SIGNAL ni1lllO : STD_LOGIC := '0'; + SIGNAL ni1llOi : STD_LOGIC := '0'; + SIGNAL ni1llOl : STD_LOGIC := '0'; + SIGNAL ni1llOO : STD_LOGIC := '0'; + SIGNAL ni1lO0i : STD_LOGIC := '0'; + SIGNAL ni1lO0l : STD_LOGIC := '0'; + SIGNAL ni1lO0O : STD_LOGIC := '0'; + SIGNAL ni1lO1i : STD_LOGIC := '0'; + SIGNAL ni1lO1l : STD_LOGIC := '0'; + SIGNAL ni1lO1O : STD_LOGIC := '0'; + SIGNAL ni1lOii : STD_LOGIC := '0'; + SIGNAL ni1lOil : STD_LOGIC := '0'; + SIGNAL ni1lOiO : STD_LOGIC := '0'; + SIGNAL ni1lOli : STD_LOGIC := '0'; + SIGNAL ni1lOll : STD_LOGIC := '0'; + SIGNAL ni1lOOi : STD_LOGIC := '0'; + SIGNAL wire_ni1lOlO_CLRN : STD_LOGIC; + SIGNAL wire_ni1lOlO_PRN : STD_LOGIC; + SIGNAL wire_ni1lOlO_w2812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_w_lg_w_lg_ni11l0O2802w2803w2806w2809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_w_lg_n0Ol01l3235w3236w3237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol01i3231w3232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_ni1lllO2451w2454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_w_lg_ni11l0O2802w2803w2806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol01i3229w3411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol01l3235w3412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol01l3235w3236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol01O3238w3239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol01O3238w3399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol11i3240w3430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Ol11i3240w3391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_ni1lOOi2452w2562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0Oii0l3379w3380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Oii0O3381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Oii1O3342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Oiiii3341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0OiiiO3339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0OiOOl3227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol00i3334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol01i3231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol0OO3429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol0OO3414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol0OO3389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1100i2828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1ll0l2460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1ll0l2458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1ll0O2564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lllO2456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lllO2451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lOil2559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lOll2479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_n0OiOOl3227w3968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_ni11l0O2802w2803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_ni11lii2804w2805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_ni11lil2807w2808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_ni11liO2810w2811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Oiiii3421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0OiOOl3328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol00i3386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol01i3229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol01l3235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol01O3238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol0OO3319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol11i3240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol11l3329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1ii3625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1il3623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1iO3621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1li3619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1ll3617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1lO3615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1Oi3613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1Ol3611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol1OO3610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n1O1lli3233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n1O1lOl3726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni11i0i2801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni11liO2764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1iO0i2556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1iOlO2558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1iOOO2462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1l11i2560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1l11l2447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lliO2423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1llli2476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1llll2574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1llOl2608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1llOO2606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lO0i2598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lO0l2596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lO0O2594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lO1i2604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lO1l2602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lO1O2600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lOii2593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lOli2478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lOll2437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lOOi2452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_w_lg_n0Ol01i3229w3411w3413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_w_lg_n0Oii0l3379w3380w3382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_w_lg_ni1lOOi2452w2453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Oii0l3379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_n0Ol01i3228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1ll0l2534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni1lOOi2563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni11l0O2802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni11lii2804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni11lil2807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1lOlO_w_lg_ni11liO2810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO001ii : STD_LOGIC := '0'; + SIGNAL niO01OOl : STD_LOGIC := '0'; + SIGNAL wire_niO0010O_w_lg_niO01OOl8791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO001il : STD_LOGIC := '0'; + SIGNAL niO001ll : STD_LOGIC := '0'; + SIGNAL n000i00i : STD_LOGIC := '0'; + SIGNAL n000i01i : STD_LOGIC := '0'; + SIGNAL n000i01l : STD_LOGIC := '0'; + SIGNAL n000i01O : STD_LOGIC := '0'; + SIGNAL n000i10i : STD_LOGIC := '0'; + SIGNAL n000i10l : STD_LOGIC := '0'; + SIGNAL n000i10O : STD_LOGIC := '0'; + SIGNAL n000i1ii : STD_LOGIC := '0'; + SIGNAL n000i1il : STD_LOGIC := '0'; + SIGNAL n000i1iO : STD_LOGIC := '0'; + SIGNAL n000i1li : STD_LOGIC := '0'; + SIGNAL n000i1ll : STD_LOGIC := '0'; + SIGNAL n000i1lO : STD_LOGIC := '0'; + SIGNAL n000i1Oi : STD_LOGIC := '0'; + SIGNAL n000i1Ol : STD_LOGIC := '0'; + SIGNAL n000i1OO : STD_LOGIC := '0'; + SIGNAL n000lilO : STD_LOGIC := '0'; + SIGNAL n000llil : STD_LOGIC := '0'; + SIGNAL n000lliO : STD_LOGIC := '0'; + SIGNAL n000llli : STD_LOGIC := '0'; + SIGNAL n000llll : STD_LOGIC := '0'; + SIGNAL n000lllO : STD_LOGIC := '0'; + SIGNAL n000llOi : STD_LOGIC := '0'; + SIGNAL n000llOl : STD_LOGIC := '0'; + SIGNAL n000llOO : STD_LOGIC := '0'; + SIGNAL n000lO0i : STD_LOGIC := '0'; + SIGNAL n000lO0l : STD_LOGIC := '0'; + SIGNAL n000lO0O : STD_LOGIC := '0'; + SIGNAL n000lO1i : STD_LOGIC := '0'; + SIGNAL n000lO1l : STD_LOGIC := '0'; + SIGNAL n000lO1O : STD_LOGIC := '0'; + SIGNAL n000lOii : STD_LOGIC := '0'; + SIGNAL n000lOil : STD_LOGIC := '0'; + SIGNAL n00100ii : STD_LOGIC := '0'; + SIGNAL n00100il : STD_LOGIC := '0'; + SIGNAL n00100iO : STD_LOGIC := '0'; + SIGNAL n00100li : STD_LOGIC := '0'; + SIGNAL n0010ili : STD_LOGIC := '0'; + SIGNAL n0010ill : STD_LOGIC := '0'; + SIGNAL n0010ilO : STD_LOGIC := '0'; + SIGNAL n0010iOi : STD_LOGIC := '0'; + SIGNAL n0010iOl : STD_LOGIC := '0'; + SIGNAL n0010iOO : STD_LOGIC := '0'; + SIGNAL n0010l0i : STD_LOGIC := '0'; + SIGNAL n0010l1i : STD_LOGIC := '0'; + SIGNAL n0010l1l : STD_LOGIC := '0'; + SIGNAL n0010l1O : STD_LOGIC := '0'; + SIGNAL n001i10i : STD_LOGIC := '0'; + SIGNAL n001i10l : STD_LOGIC := '0'; + SIGNAL n001i10O : STD_LOGIC := '0'; + SIGNAL n001i11i : STD_LOGIC := '0'; + SIGNAL n001i11l : STD_LOGIC := '0'; + SIGNAL n001i11O : STD_LOGIC := '0'; + SIGNAL n001iilO : STD_LOGIC := '0'; + SIGNAL n001iiOi : STD_LOGIC := '0'; + SIGNAL n001iiOl : STD_LOGIC := '0'; + SIGNAL n001iiOO : STD_LOGIC := '0'; + SIGNAL n001il0i : STD_LOGIC := '0'; + SIGNAL n001il0l : STD_LOGIC := '0'; + SIGNAL n001il0O : STD_LOGIC := '0'; + SIGNAL n001il1i : STD_LOGIC := '0'; + SIGNAL n001il1l : STD_LOGIC := '0'; + SIGNAL n001il1O : STD_LOGIC := '0'; + SIGNAL n001ilii : STD_LOGIC := '0'; + SIGNAL n001ilil : STD_LOGIC := '0'; + SIGNAL n001iliO : STD_LOGIC := '0'; + SIGNAL n001illi : STD_LOGIC := '0'; + SIGNAL n001illl : STD_LOGIC := '0'; + SIGNAL n001illO : STD_LOGIC := '0'; + SIGNAL n001ilOi : STD_LOGIC := '0'; + SIGNAL n001ilOl : STD_LOGIC := '0'; + SIGNAL n001ilOO : STD_LOGIC := '0'; + SIGNAL n001iO0i : STD_LOGIC := '0'; + SIGNAL n001iO0l : STD_LOGIC := '0'; + SIGNAL n001iO0O : STD_LOGIC := '0'; + SIGNAL n001iO1i : STD_LOGIC := '0'; + SIGNAL n001iO1l : STD_LOGIC := '0'; + SIGNAL n001iO1O : STD_LOGIC := '0'; + SIGNAL n001iOii : STD_LOGIC := '0'; + SIGNAL n001ll1O : STD_LOGIC := '0'; + SIGNAL n00i100i : STD_LOGIC := '0'; + SIGNAL n00i100l : STD_LOGIC := '0'; + SIGNAL n00i100O : STD_LOGIC := '0'; + SIGNAL n00i101l : STD_LOGIC := '0'; + SIGNAL n00i101O : STD_LOGIC := '0'; + SIGNAL n00i10ii : STD_LOGIC := '0'; + SIGNAL n00i10il : STD_LOGIC := '0'; + SIGNAL n00i10iO : STD_LOGIC := '0'; + SIGNAL n00i10li : STD_LOGIC := '0'; + SIGNAL n00i10ll : STD_LOGIC := '0'; + SIGNAL n00i10lO : STD_LOGIC := '0'; + SIGNAL n00i10Oi : STD_LOGIC := '0'; + SIGNAL n00i10Ol : STD_LOGIC := '0'; + SIGNAL n00i10OO : STD_LOGIC := '0'; + SIGNAL n00i110O : STD_LOGIC := '0'; + SIGNAL n00i1i1i : STD_LOGIC := '0'; + SIGNAL n00iii0i : STD_LOGIC := '0'; + SIGNAL n00iii0l : STD_LOGIC := '0'; + SIGNAL n00iii1l : STD_LOGIC := '0'; + SIGNAL n00iii1O : STD_LOGIC := '0'; + SIGNAL n00iiiOi : STD_LOGIC := '0'; + SIGNAL n00iilii : STD_LOGIC := '0'; + SIGNAL n00iilil : STD_LOGIC := '0'; + SIGNAL n00iiliO : STD_LOGIC := '0'; + SIGNAL n00iilli : STD_LOGIC := '0'; + SIGNAL n00il1li : STD_LOGIC := '0'; + SIGNAL n00il1OO : STD_LOGIC := '0'; + SIGNAL n00ill0i : STD_LOGIC := '0'; + SIGNAL n00ill0l : STD_LOGIC := '0'; + SIGNAL n00ill0O : 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n0i0O00i : STD_LOGIC := '0'; + SIGNAL n0i0O00l : STD_LOGIC := '0'; + SIGNAL n0i0O00O : STD_LOGIC := '0'; + SIGNAL n0i0O01i : STD_LOGIC := '0'; + SIGNAL n0i0O01l : STD_LOGIC := '0'; + SIGNAL n0i0O01O : STD_LOGIC := '0'; + SIGNAL n0i0O0ii : STD_LOGIC := '0'; + SIGNAL n0i0O0il : STD_LOGIC := '0'; + SIGNAL n0i0O0iO : STD_LOGIC := '0'; + SIGNAL n0i0O0li : STD_LOGIC := '0'; + SIGNAL n0i0O0ll : STD_LOGIC := '0'; + SIGNAL n0i0O0lO : STD_LOGIC := '0'; + SIGNAL n0i0O0Oi : STD_LOGIC := '0'; + SIGNAL n0i0O0Ol : STD_LOGIC := '0'; + SIGNAL n0i0O0OO : STD_LOGIC := '0'; + SIGNAL n0i0O10l : STD_LOGIC := '0'; + SIGNAL n0i0O10O : STD_LOGIC := '0'; + SIGNAL n0i0O1ii : STD_LOGIC := '0'; + SIGNAL n0i0O1il : STD_LOGIC := '0'; + SIGNAL n0i0O1iO : STD_LOGIC := '0'; + SIGNAL n0i0O1li : STD_LOGIC := '0'; + SIGNAL n0i0O1ll : STD_LOGIC := '0'; + SIGNAL n0i0O1lO : STD_LOGIC := '0'; + SIGNAL n0i0O1Oi : STD_LOGIC := '0'; + SIGNAL n0i0O1Ol : STD_LOGIC := '0'; + SIGNAL n0i0O1OO : STD_LOGIC := '0'; + SIGNAL n0i0Oi0i : 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SIGNAL n0ii0O1O : STD_LOGIC := '0'; + SIGNAL n0ii0Oii : STD_LOGIC := '0'; + SIGNAL n0ii0Oil : STD_LOGIC := '0'; + SIGNAL n0ii0OiO : STD_LOGIC := '0'; + SIGNAL n0ii0Oli : STD_LOGIC := '0'; + SIGNAL n0ii0Oll : STD_LOGIC := '0'; + SIGNAL n0ii0OlO : STD_LOGIC := '0'; + SIGNAL n0iii0iO : STD_LOGIC := '0'; + SIGNAL n0iii0li : STD_LOGIC := '0'; + SIGNAL n0iii0ll : STD_LOGIC := '0'; + SIGNAL n0iii0lO : STD_LOGIC := '0'; + SIGNAL n0iii0Oi : STD_LOGIC := '0'; + SIGNAL n0iii0Ol : STD_LOGIC := '0'; + SIGNAL n0iiiO0l : STD_LOGIC := '0'; + SIGNAL n0iiiO0O : STD_LOGIC := '0'; + SIGNAL n0iiiOii : STD_LOGIC := '0'; + SIGNAL n0iiiOil : STD_LOGIC := '0'; + SIGNAL n0iiiOiO : STD_LOGIC := '0'; + SIGNAL n0iiiOli : STD_LOGIC := '0'; + SIGNAL n0iiiOll : STD_LOGIC := '0'; + SIGNAL n0iiiOlO : STD_LOGIC := '0'; + SIGNAL n0iiiOOi : STD_LOGIC := '0'; + SIGNAL n0iiiOOl : STD_LOGIC := '0'; + SIGNAL n0iiiOOO : STD_LOGIC := '0'; + SIGNAL n0iil10i : STD_LOGIC := '0'; + SIGNAL n0iil10l : STD_LOGIC := '0'; + SIGNAL n0iil10O : STD_LOGIC := '0'; + SIGNAL n0iil11i : STD_LOGIC := '0'; + SIGNAL n0iil11l : STD_LOGIC := '0'; + SIGNAL n0iil11O : STD_LOGIC := '0'; + SIGNAL n0iil1ii : STD_LOGIC := '0'; + SIGNAL n0iil1il : STD_LOGIC := '0'; + SIGNAL n0iil1iO : STD_LOGIC := '0'; + SIGNAL n0iil1li : STD_LOGIC := '0'; + SIGNAL n0iil1ll : STD_LOGIC := '0'; + SIGNAL n0iil1lO : STD_LOGIC := '0'; + SIGNAL n0iil1Oi : STD_LOGIC := '0'; + SIGNAL n0iil1Ol : STD_LOGIC := '0'; + SIGNAL n0iil1OO : STD_LOGIC := '0'; + SIGNAL n0iilOll : STD_LOGIC := '0'; + SIGNAL n0ili0lO : STD_LOGIC := '0'; + SIGNAL n0ili0Oi : STD_LOGIC := '0'; + SIGNAL n0ili0Ol : STD_LOGIC := '0'; + SIGNAL n0ili0OO : STD_LOGIC := '0'; + SIGNAL n0ilii0i : STD_LOGIC := '0'; + SIGNAL n0ilii0l : STD_LOGIC := '0'; + SIGNAL n0ilii0O : STD_LOGIC := '0'; + SIGNAL n0ilii1i : STD_LOGIC := '0'; + SIGNAL n0ilii1l : STD_LOGIC := '0'; + SIGNAL n0ilii1O : STD_LOGIC := '0'; + SIGNAL n0iliiii : STD_LOGIC := '0'; + SIGNAL n0iliiil : STD_LOGIC := '0'; + SIGNAL n0iliiiO : STD_LOGIC := '0'; + SIGNAL n0iliili : STD_LOGIC := '0'; + SIGNAL n0iliill : STD_LOGIC := '0'; + SIGNAL n0iliilO : STD_LOGIC := '0'; + SIGNAL n0illO0l : STD_LOGIC := '0'; + SIGNAL n0ilO01i : STD_LOGIC := '0'; + SIGNAL n0ilO10i : STD_LOGIC := '0'; + SIGNAL n0ilO10l : STD_LOGIC := '0'; + SIGNAL n0ilO10O : STD_LOGIC := '0'; + SIGNAL n0ilO11i : STD_LOGIC := '0'; + SIGNAL n0ilO11l : STD_LOGIC := '0'; + SIGNAL n0ilO11O : STD_LOGIC := '0'; + SIGNAL n0ilO1ii : STD_LOGIC := '0'; + SIGNAL n0ilO1il : STD_LOGIC := '0'; + SIGNAL n0ilO1iO : STD_LOGIC := '0'; + SIGNAL n0ilO1li : STD_LOGIC := '0'; + SIGNAL n0ilO1ll : STD_LOGIC := '0'; + SIGNAL n0ilO1lO : STD_LOGIC := '0'; + SIGNAL n0ilO1Oi : STD_LOGIC := '0'; + SIGNAL n0ilO1Ol : STD_LOGIC := '0'; + SIGNAL n0ilO1OO : STD_LOGIC := '0'; + SIGNAL n0iO10Ol : STD_LOGIC := '0'; + SIGNAL n0iO1ili : STD_LOGIC := '0'; + SIGNAL n0iO1ill : STD_LOGIC := '0'; + SIGNAL n0iO1ilO : STD_LOGIC := '0'; + SIGNAL n0iO1iOi : STD_LOGIC := '0'; + SIGNAL n0iO1iOl : STD_LOGIC := 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SIGNAL n0iOlOOl : STD_LOGIC := '0'; + SIGNAL n0iOlOOO : STD_LOGIC := '0'; + SIGNAL n0iOO00i : STD_LOGIC := '0'; + SIGNAL n0iOO00l : STD_LOGIC := '0'; + SIGNAL n0iOO00O : STD_LOGIC := '0'; + SIGNAL n0iOO01i : STD_LOGIC := '0'; + SIGNAL n0iOO01l : STD_LOGIC := '0'; + SIGNAL n0iOO01O : STD_LOGIC := '0'; + SIGNAL n0iOO0ii : STD_LOGIC := '0'; + SIGNAL n0iOO0il : STD_LOGIC := '0'; + SIGNAL n0iOO0iO : STD_LOGIC := '0'; + SIGNAL n0iOO0li : STD_LOGIC := '0'; + SIGNAL n0iOO0ll : STD_LOGIC := '0'; + SIGNAL n0iOO0lO : STD_LOGIC := '0'; + SIGNAL n0iOO0Oi : STD_LOGIC := '0'; + SIGNAL n0iOO0Ol : STD_LOGIC := '0'; + SIGNAL n0iOO0OO : STD_LOGIC := '0'; + SIGNAL n0iOO10i : STD_LOGIC := '0'; + SIGNAL n0iOO10l : STD_LOGIC := '0'; + SIGNAL n0iOO10O : STD_LOGIC := '0'; + SIGNAL n0iOO11i : STD_LOGIC := '0'; + SIGNAL n0iOO11l : STD_LOGIC := '0'; + SIGNAL n0iOO11O : STD_LOGIC := '0'; + SIGNAL n0iOO1ii : STD_LOGIC := '0'; + SIGNAL n0iOO1il : STD_LOGIC := '0'; + SIGNAL n0iOO1iO : STD_LOGIC := '0'; + SIGNAL n0iOO1li : STD_LOGIC := '0'; + SIGNAL n0iOO1ll : STD_LOGIC := '0'; + SIGNAL n0iOO1lO : STD_LOGIC := '0'; + SIGNAL n0iOO1Oi : STD_LOGIC := '0'; + SIGNAL n0iOO1Ol : STD_LOGIC := '0'; + SIGNAL n0iOO1OO : STD_LOGIC := '0'; + SIGNAL n0iOOi0i : STD_LOGIC := '0'; + SIGNAL n0iOOi0l : STD_LOGIC := '0'; + SIGNAL n0iOOi0O : STD_LOGIC := '0'; + SIGNAL n0iOOi1i : STD_LOGIC := '0'; + SIGNAL n0iOOi1l : STD_LOGIC := '0'; + SIGNAL n0iOOi1O : STD_LOGIC := '0'; + SIGNAL n0iOOiii : STD_LOGIC := '0'; + SIGNAL n0iOOiil : STD_LOGIC := '0'; + SIGNAL n0iOOiiO : STD_LOGIC := '0'; + SIGNAL n0l00iOO : STD_LOGIC := '0'; + SIGNAL n0l0111i : STD_LOGIC := '0'; + SIGNAL n0l0111l : STD_LOGIC := '0'; + SIGNAL n0l0111O : STD_LOGIC := '0'; + SIGNAL n0l01iiO : STD_LOGIC := '0'; + SIGNAL n0l01ili : STD_LOGIC := '0'; + SIGNAL n0l01ill : STD_LOGIC := '0'; + SIGNAL n0l01ilO : STD_LOGIC := '0'; + SIGNAL n0l01iOi : STD_LOGIC := '0'; + SIGNAL n0l01iOl : STD_LOGIC := '0'; + SIGNAL n0l01iOO : STD_LOGIC := '0'; + SIGNAL n0l01l0i : STD_LOGIC := '0'; + SIGNAL n0l01l0l : STD_LOGIC := '0'; + SIGNAL n0l01l0O : STD_LOGIC := '0'; + SIGNAL n0l01l1i : STD_LOGIC := '0'; + SIGNAL n0l01l1l : STD_LOGIC := '0'; + SIGNAL n0l01l1O : STD_LOGIC := '0'; + SIGNAL n0l01lii : STD_LOGIC := '0'; + SIGNAL n0l01lil : STD_LOGIC := '0'; + SIGNAL n0l01liO : STD_LOGIC := '0'; + SIGNAL n0l01lli : STD_LOGIC := '0'; + SIGNAL n0l01lll : STD_LOGIC := '0'; + SIGNAL n0l01llO : STD_LOGIC := '0'; + SIGNAL n0l01lOi : STD_LOGIC := '0'; + SIGNAL n0l01lOl : STD_LOGIC := '0'; + SIGNAL n0l01lOO : STD_LOGIC := '0'; + SIGNAL n0l01O0i : STD_LOGIC := '0'; + SIGNAL n0l01O1i : STD_LOGIC := '0'; + SIGNAL n0l01O1l : STD_LOGIC := '0'; + SIGNAL n0l01O1O : STD_LOGIC := '0'; + SIGNAL n0l10liO : STD_LOGIC := '0'; + SIGNAL n0l10lli : STD_LOGIC := '0'; + SIGNAL n0l10lll : STD_LOGIC := '0'; + SIGNAL n0l10llO : STD_LOGIC := '0'; + SIGNAL n0l10lOi : STD_LOGIC := '0'; + SIGNAL n0l10lOl : STD_LOGIC := '0'; + SIGNAL n0l10lOO : STD_LOGIC := '0'; + SIGNAL n0l10O0i : STD_LOGIC := '0'; + SIGNAL n0l10O0l : STD_LOGIC := '0'; + SIGNAL n0l10O0O : STD_LOGIC := '0'; + SIGNAL n0l10O1i : STD_LOGIC := '0'; + SIGNAL n0l10O1l : STD_LOGIC := '0'; + SIGNAL n0l10O1O : STD_LOGIC := '0'; + SIGNAL n0l10Oii : STD_LOGIC := '0'; + SIGNAL n0l10Oil : STD_LOGIC := '0'; + SIGNAL n0l10OiO : STD_LOGIC := '0'; + SIGNAL n0l10Oli : STD_LOGIC := '0'; + SIGNAL n0l10Oll : STD_LOGIC := '0'; + SIGNAL n0l10OlO : STD_LOGIC := '0'; + SIGNAL n0l10OOi : STD_LOGIC := '0'; + SIGNAL n0l10OOl : STD_LOGIC := '0'; + SIGNAL n0l10OOO : STD_LOGIC := '0'; + SIGNAL n0l1i00O : STD_LOGIC := '0'; + SIGNAL n0l1i01i : STD_LOGIC := '0'; + SIGNAL n0l1i10i : STD_LOGIC := '0'; + SIGNAL n0l1i10l : STD_LOGIC := '0'; + SIGNAL n0l1i10O : STD_LOGIC := '0'; + SIGNAL n0l1i11i : STD_LOGIC := '0'; + SIGNAL n0l1i11l : STD_LOGIC := '0'; + SIGNAL n0l1i11O : STD_LOGIC := '0'; + SIGNAL n0l1i1ii : STD_LOGIC := '0'; + SIGNAL n0l1i1il : STD_LOGIC := '0'; + SIGNAL n0l1i1iO : STD_LOGIC := '0'; + SIGNAL n0l1i1li : STD_LOGIC := '0'; + SIGNAL n0l1i1ll : STD_LOGIC := '0'; + SIGNAL n0l1i1lO : STD_LOGIC := '0'; + SIGNAL n0l1i1Oi : STD_LOGIC := '0'; + SIGNAL n0l1i1Ol : STD_LOGIC := '0'; + SIGNAL n0l1i1OO : STD_LOGIC := '0'; + SIGNAL n0l1O00i : STD_LOGIC := '0'; + SIGNAL n0l1O00l : STD_LOGIC := '0'; + SIGNAL n0l1O00O : STD_LOGIC := '0'; + SIGNAL n0l1O0ii : STD_LOGIC := '0'; + SIGNAL n0l1Oiii : STD_LOGIC := '0'; + SIGNAL n0l1Oiil : STD_LOGIC := '0'; + SIGNAL n0l1OiiO : STD_LOGIC := '0'; + SIGNAL n0l1Oili : STD_LOGIC := '0'; + SIGNAL n0l1Oill : STD_LOGIC := '0'; + SIGNAL n0l1OilO : STD_LOGIC := '0'; + SIGNAL n0l1OiOi : STD_LOGIC := '0'; + SIGNAL n0l1OiOl : STD_LOGIC := '0'; + SIGNAL n0l1OiOO : STD_LOGIC := '0'; + SIGNAL n0l1Ol1i : STD_LOGIC := '0'; + SIGNAL n0l1OOOi : STD_LOGIC := '0'; + SIGNAL n0l1OOOl : STD_LOGIC := '0'; + SIGNAL n0l1OOOO : STD_LOGIC := '0'; + SIGNAL n0li0iiO : STD_LOGIC := '0'; + SIGNAL n0li0l0l : STD_LOGIC := '0'; + SIGNAL n0li0l0O : STD_LOGIC := '0'; + SIGNAL n0li0lii : STD_LOGIC := '0'; + SIGNAL n0li0lil : STD_LOGIC := '0'; + SIGNAL n0li0liO : STD_LOGIC := '0'; + SIGNAL n0li0lli : STD_LOGIC := '0'; + SIGNAL n0li0lll : STD_LOGIC := '0'; + SIGNAL n0li0llO : STD_LOGIC := '0'; + SIGNAL n0li0lOi : STD_LOGIC := '0'; + SIGNAL n0li0lOl : STD_LOGIC := '0'; + SIGNAL n0li0lOO : STD_LOGIC := '0'; + SIGNAL n0li0O0i : STD_LOGIC := '0'; + SIGNAL n0li0O0l : STD_LOGIC := '0'; + SIGNAL n0li0O1i : STD_LOGIC := '0'; + SIGNAL n0li0O1l : STD_LOGIC := '0'; + SIGNAL n0li0O1O : STD_LOGIC := '0'; + SIGNAL n0li101i : STD_LOGIC := '0'; + SIGNAL n0li110i : STD_LOGIC := '0'; + SIGNAL n0li110l : STD_LOGIC := '0'; + SIGNAL n0li110O : STD_LOGIC := '0'; + SIGNAL n0li111i : STD_LOGIC := '0'; + SIGNAL n0li111l : STD_LOGIC := '0'; + SIGNAL n0li111O : STD_LOGIC := '0'; + SIGNAL n0li11ii : STD_LOGIC := '0'; + SIGNAL n0li11il : STD_LOGIC := '0'; + SIGNAL n0li11iO : STD_LOGIC := '0'; + SIGNAL n0li11li : STD_LOGIC := '0'; + SIGNAL n0li11ll : STD_LOGIC := '0'; + SIGNAL n0li11lO : STD_LOGIC := '0'; + SIGNAL n0li11Oi : STD_LOGIC := '0'; + SIGNAL n0li11Ol : STD_LOGIC := '0'; + SIGNAL n0li11OO : STD_LOGIC := '0'; + SIGNAL n0lil00i : STD_LOGIC := '0'; + SIGNAL n0lil00l : STD_LOGIC := '0'; + SIGNAL n0lil00O : STD_LOGIC := '0'; + SIGNAL n0lil01i : STD_LOGIC := '0'; + SIGNAL n0lil01l : STD_LOGIC := '0'; + SIGNAL n0lil01O : STD_LOGIC := '0'; + SIGNAL n0lil0ii : STD_LOGIC := '0'; + SIGNAL n0lil0il : STD_LOGIC := '0'; + SIGNAL n0lil0iO : STD_LOGIC := '0'; + SIGNAL n0lil0li : STD_LOGIC := '0'; + SIGNAL n0lil0ll : STD_LOGIC := '0'; + SIGNAL n0lil0lO : STD_LOGIC := '0'; + SIGNAL n0lil0Oi : STD_LOGIC := '0'; + SIGNAL n0lil11O : STD_LOGIC := '0'; + SIGNAL n0lil1Ol : STD_LOGIC := '0'; + SIGNAL n0lil1OO : STD_LOGIC := '0'; + SIGNAL n0ll01ii : STD_LOGIC := '0'; + SIGNAL n0ll01lO : STD_LOGIC := '0'; + SIGNAL n0ll0iOi : STD_LOGIC := '0'; + SIGNAL n0ll0iOl : STD_LOGIC := '0'; + SIGNAL n0ll0iOO : STD_LOGIC := '0'; + SIGNAL n0ll0l0i : STD_LOGIC := '0'; + SIGNAL n0ll0l0l : STD_LOGIC := '0'; + SIGNAL n0ll0l0O : STD_LOGIC := '0'; + SIGNAL n0ll0l1i : STD_LOGIC := '0'; + SIGNAL n0ll0l1l : STD_LOGIC := '0'; + SIGNAL n0ll0l1O : STD_LOGIC := '0'; + SIGNAL n0ll0lii : STD_LOGIC := '0'; + SIGNAL n0ll0lil : STD_LOGIC := '0'; + SIGNAL n0ll0liO : STD_LOGIC := '0'; + SIGNAL n0ll0lli : STD_LOGIC := '0'; + SIGNAL n0ll0lll : STD_LOGIC := '0'; + SIGNAL n0ll0llO : STD_LOGIC := '0'; + SIGNAL n0ll0lOi : STD_LOGIC := '0'; + SIGNAL n0ll0lOl : STD_LOGIC := '0'; + SIGNAL n0ll0lOO : STD_LOGIC := '0'; + SIGNAL n0ll0O0i : STD_LOGIC := '0'; + SIGNAL n0ll0O0l : STD_LOGIC := '0'; + SIGNAL n0ll0O0O : STD_LOGIC := '0'; + SIGNAL n0ll0O1i : STD_LOGIC := '0'; + SIGNAL n0ll0O1l : STD_LOGIC := '0'; + SIGNAL n0ll0O1O : STD_LOGIC := '0'; + SIGNAL n0ll0Oii : STD_LOGIC := '0'; + SIGNAL n0ll0Oil : STD_LOGIC := '0'; + SIGNAL n0ll0OiO : STD_LOGIC := '0'; + SIGNAL n0ll0Oli : STD_LOGIC := '0'; + SIGNAL n0ll0Oll : STD_LOGIC := '0'; + SIGNAL n0ll0OlO : STD_LOGIC := '0'; + SIGNAL n0ll0OOi : STD_LOGIC := '0'; + SIGNAL n0ll0OOl : STD_LOGIC := '0'; + SIGNAL n0ll0OOO : STD_LOGIC := '0'; + SIGNAL n0ll10Ol : STD_LOGIC := '0'; + SIGNAL n0ll10OO : STD_LOGIC := '0'; + SIGNAL n0ll1i1i : STD_LOGIC := '0'; + SIGNAL n0ll1i1l : STD_LOGIC := '0'; + SIGNAL n0ll1ili : STD_LOGIC := '0'; + SIGNAL n0ll1l0i : STD_LOGIC := '0'; + SIGNAL n0ll1l0l : STD_LOGIC := '0'; + SIGNAL n0ll1l0O : STD_LOGIC := '0'; + SIGNAL n0ll1lii : STD_LOGIC := '0'; + SIGNAL n0lli10i : STD_LOGIC := '0'; + SIGNAL n0lli10l : STD_LOGIC := '0'; + SIGNAL n0lli10O : STD_LOGIC := '0'; + SIGNAL n0lli11i : STD_LOGIC := '0'; + SIGNAL n0lli11l : STD_LOGIC := '0'; + SIGNAL n0lli11O : STD_LOGIC := '0'; + SIGNAL n0lli1ii : STD_LOGIC := '0'; + SIGNAL n0lli1il : STD_LOGIC := '0'; + SIGNAL n0lli1iO : STD_LOGIC := '0'; + SIGNAL n0lli1li : STD_LOGIC := '0'; + SIGNAL n0lli1ll : STD_LOGIC := '0'; + SIGNAL n0lli1lO : STD_LOGIC := '0'; + SIGNAL n0lli1Oi : STD_LOGIC := '0'; + SIGNAL n0llO0Oi : STD_LOGIC := '0'; + SIGNAL n0llO0Ol : STD_LOGIC := '0'; + SIGNAL n0llO0OO : STD_LOGIC := '0'; + SIGNAL n0llOi0i : STD_LOGIC := '0'; + SIGNAL n0llOi0l : STD_LOGIC := '0'; + SIGNAL n0llOi0O : STD_LOGIC := '0'; + SIGNAL n0llOi1i : STD_LOGIC := '0'; + SIGNAL n0llOi1l : STD_LOGIC := '0'; + SIGNAL n0llOi1O : STD_LOGIC := '0'; + SIGNAL n0llOiii : STD_LOGIC := '0'; + SIGNAL n0llOiil : STD_LOGIC := '0'; + SIGNAL n0llOiiO : STD_LOGIC := '0'; + SIGNAL n0llOili : STD_LOGIC := '0'; + SIGNAL n0llOill : STD_LOGIC := '0'; + SIGNAL n0llOilO : STD_LOGIC := '0'; + SIGNAL n0llOiOi : STD_LOGIC := '0'; + SIGNAL n0llOiOl : STD_LOGIC := '0'; + SIGNAL n0llOiOO : STD_LOGIC := '0'; + SIGNAL n0llOl0i : STD_LOGIC := '0'; + SIGNAL n0llOl0l : STD_LOGIC := '0'; + SIGNAL n0llOl0O : STD_LOGIC := '0'; + SIGNAL n0llOl1i : STD_LOGIC := '0'; + SIGNAL n0llOl1l : STD_LOGIC := '0'; + SIGNAL n0llOl1O : STD_LOGIC := '0'; + SIGNAL n0llOlii : STD_LOGIC := '0'; + SIGNAL n0llOlil : STD_LOGIC := '0'; + SIGNAL n0llOliO : STD_LOGIC := '0'; + SIGNAL n0llOlli : STD_LOGIC := '0'; + SIGNAL n0llOlll : STD_LOGIC := '0'; + SIGNAL n0llOllO : STD_LOGIC := '0'; + SIGNAL n0llOlOi : STD_LOGIC := '0'; + SIGNAL n0llOlOl : STD_LOGIC := '0'; + SIGNAL n0llOlOO : STD_LOGIC := '0'; + SIGNAL n0llOO0i : STD_LOGIC := '0'; + SIGNAL n0llOO0l : STD_LOGIC := '0'; + SIGNAL n0llOO1i : STD_LOGIC := '0'; + SIGNAL n0llOO1l : STD_LOGIC := '0'; + SIGNAL n0llOO1O : STD_LOGIC := '0'; + SIGNAL n0llOOli : STD_LOGIC := '0'; + SIGNAL n0lO0Oil : STD_LOGIC := '0'; + SIGNAL n0lO0OiO : STD_LOGIC := '0'; + SIGNAL n0lO0Oli : STD_LOGIC := '0'; + SIGNAL n0lO0Oll : STD_LOGIC := '0'; + SIGNAL n0lOi00i : STD_LOGIC := '0'; + SIGNAL n0lOi00l : STD_LOGIC := '0'; + SIGNAL n0lOi01i : STD_LOGIC := '0'; + SIGNAL n0lOi01l : STD_LOGIC := '0'; + SIGNAL n0lOi01O : STD_LOGIC := '0'; + SIGNAL n0lOi1ll : STD_LOGIC := '0'; + SIGNAL n0lOi1lO : STD_LOGIC := '0'; + SIGNAL n0lOi1Oi : STD_LOGIC := '0'; + SIGNAL n0lOi1Ol : STD_LOGIC := '0'; + SIGNAL n0lOi1OO : STD_LOGIC := '0'; + SIGNAL n0lOil0i : STD_LOGIC := '0'; + SIGNAL n0lOil0l : STD_LOGIC := '0'; + SIGNAL n0lOil0O : STD_LOGIC := '0'; + SIGNAL n0lOil1l : STD_LOGIC := '0'; + SIGNAL n0lOil1O : STD_LOGIC := '0'; + SIGNAL n0lOilii : STD_LOGIC := '0'; + SIGNAL n0lOl00i : STD_LOGIC := '0'; + SIGNAL n0lOl00l : STD_LOGIC := '0'; + SIGNAL n0lOl00O : STD_LOGIC := '0'; + SIGNAL n0lOl01i : STD_LOGIC := '0'; + SIGNAL n0lOl01l : STD_LOGIC := '0'; + SIGNAL n0lOl01O : STD_LOGIC := '0'; + SIGNAL n0lOl0ii : STD_LOGIC := '0'; + SIGNAL n0lOl0il : STD_LOGIC := '0'; + SIGNAL n0lOl0iO : STD_LOGIC := '0'; + SIGNAL n0lOl0li : STD_LOGIC := '0'; + SIGNAL n0lOl0ll : STD_LOGIC := '0'; + SIGNAL n0lOl0lO : STD_LOGIC := '0'; + SIGNAL n0lOl0Oi : STD_LOGIC := '0'; + SIGNAL n0lOl0Ol : STD_LOGIC := '0'; + SIGNAL n0lOl0OO : STD_LOGIC := '0'; + SIGNAL n0lOl1Oi : STD_LOGIC := '0'; + SIGNAL n0lOl1Ol : STD_LOGIC := '0'; + SIGNAL n0lOl1OO : STD_LOGIC := '0'; + SIGNAL n0lOli0i : STD_LOGIC := '0'; + SIGNAL n0lOli0l : STD_LOGIC := '0'; + SIGNAL n0lOli0O : STD_LOGIC := '0'; + SIGNAL n0lOli1i : STD_LOGIC := '0'; + SIGNAL n0lOli1l : STD_LOGIC := '0'; + SIGNAL n0lOli1O : STD_LOGIC := '0'; + SIGNAL n0lOliii : STD_LOGIC := '0'; + SIGNAL n0lOliil : STD_LOGIC := '0'; + SIGNAL n0lOO00i : STD_LOGIC := '0'; + SIGNAL n0O0011i : STD_LOGIC := '0'; + SIGNAL n0O0011l : STD_LOGIC := '0'; + SIGNAL n0O01lii : STD_LOGIC := '0'; + SIGNAL n0O01O0i : STD_LOGIC := '0'; + SIGNAL n0O01O0l : STD_LOGIC := '0'; + SIGNAL n0O01O0O : STD_LOGIC := '0'; + SIGNAL n0O01O1O : STD_LOGIC := '0'; + SIGNAL n0O01Oii : STD_LOGIC := '0'; + SIGNAL n0O01Oil : STD_LOGIC := '0'; + SIGNAL n0O01OiO : STD_LOGIC := '0'; + SIGNAL n0O01Oli : STD_LOGIC := '0'; + SIGNAL n0O01Oll : STD_LOGIC := '0'; + SIGNAL n0O01OlO : STD_LOGIC := '0'; + SIGNAL n0O01OOi : STD_LOGIC := '0'; + SIGNAL n0O01OOl : STD_LOGIC := '0'; + SIGNAL n0O01OOO : STD_LOGIC := '0'; + SIGNAL n0O0l0il : STD_LOGIC := '0'; + SIGNAL n0O0l0iO : STD_LOGIC := '0'; + SIGNAL n0O0l0li : STD_LOGIC := '0'; + SIGNAL n0O0l0ll : STD_LOGIC := '0'; + SIGNAL n0O0l10i : STD_LOGIC := '0'; + SIGNAL n0O0l10l : STD_LOGIC := '0'; + SIGNAL n0O0l10O : STD_LOGIC := '0'; + SIGNAL n0O0l11O : STD_LOGIC := '0'; + SIGNAL n0O0l1Ol : STD_LOGIC := '0'; + SIGNAL n0O0llll : STD_LOGIC := '0'; + SIGNAL n0O0lO1i : STD_LOGIC := '0'; + SIGNAL n0O0O00i : STD_LOGIC := '0'; + SIGNAL n0O0O00l : STD_LOGIC := '0'; + SIGNAL n0O0O00O : STD_LOGIC := '0'; + SIGNAL n0O0O01l : STD_LOGIC := '0'; + SIGNAL n0O0O01O : STD_LOGIC := '0'; + SIGNAL n0O0O0ii : STD_LOGIC := '0'; + SIGNAL n0O0O0il : STD_LOGIC := '0'; + SIGNAL n0O0O0iO : STD_LOGIC := '0'; + SIGNAL n0O0O0li : STD_LOGIC := '0'; + SIGNAL n0O0O0ll : STD_LOGIC := '0'; + SIGNAL n0O0O0lO : STD_LOGIC := '0'; + SIGNAL n0O0O0Oi : STD_LOGIC := '0'; + SIGNAL n0O0O0Ol : STD_LOGIC := '0'; + SIGNAL n0O0O0OO : STD_LOGIC := '0'; + SIGNAL n0O0Oi0i : STD_LOGIC := '0'; + SIGNAL n0O0Oi0l : STD_LOGIC := '0'; + SIGNAL n0O0Oi0O : STD_LOGIC := '0'; + SIGNAL n0O0Oi1i : STD_LOGIC := '0'; + SIGNAL n0O0Oi1l : STD_LOGIC := '0'; + SIGNAL n0O0Oi1O : STD_LOGIC := '0'; + SIGNAL n0O0Oiii : STD_LOGIC := '0'; + SIGNAL n0O0Oiil : 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n11Oi01O : STD_LOGIC := '0'; + SIGNAL n11Oi0ii : STD_LOGIC := '0'; + SIGNAL n11Oi10i : STD_LOGIC := '0'; + SIGNAL n11Oi10l : STD_LOGIC := '0'; + SIGNAL n11Oi10O : STD_LOGIC := '0'; + SIGNAL n11Oi11i : STD_LOGIC := '0'; + SIGNAL n11Oi11l : STD_LOGIC := '0'; + SIGNAL n11Oi11O : STD_LOGIC := '0'; + SIGNAL n11Oi1ii : STD_LOGIC := '0'; + SIGNAL n11Oi1il : STD_LOGIC := '0'; + SIGNAL n11Oi1iO : STD_LOGIC := '0'; + SIGNAL n11Oi1li : STD_LOGIC := '0'; + SIGNAL n11Oi1ll : STD_LOGIC := '0'; + SIGNAL n11Oi1lO : STD_LOGIC := '0'; + SIGNAL n11Oi1Oi : STD_LOGIC := '0'; + SIGNAL n11Oi1Ol : STD_LOGIC := '0'; + SIGNAL n11Oi1OO : STD_LOGIC := '0'; + SIGNAL n1iiii1i : STD_LOGIC := '0'; + SIGNAL n1iili0l : STD_LOGIC := '0'; + SIGNAL n1iili0O : STD_LOGIC := '0'; + SIGNAL n1iiliii : STD_LOGIC := '0'; + SIGNAL n1iiliil : STD_LOGIC := '0'; + SIGNAL n1iiliiO : STD_LOGIC := '0'; + SIGNAL n1iilili : STD_LOGIC := '0'; + SIGNAL n1iilill : STD_LOGIC := '0'; + SIGNAL n1iililO : STD_LOGIC := '0'; + SIGNAL n1iiliOi : STD_LOGIC := '0'; + SIGNAL n1iiliOl : STD_LOGIC := '0'; + SIGNAL n1iiliOO : STD_LOGIC := '0'; + SIGNAL n1iill0i : STD_LOGIC := '0'; + SIGNAL n1iill0l : STD_LOGIC := '0'; + SIGNAL n1iill0O : STD_LOGIC := '0'; + SIGNAL n1iill1i : STD_LOGIC := '0'; + SIGNAL n1iill1l : STD_LOGIC := '0'; + SIGNAL n1iill1O : STD_LOGIC := '0'; + SIGNAL n1iillii : STD_LOGIC := '0'; + SIGNAL n1iillil : STD_LOGIC := '0'; + SIGNAL n1iilliO : STD_LOGIC := '0'; + SIGNAL n1iillli : STD_LOGIC := '0'; + SIGNAL n1iiOlii : STD_LOGIC := '0'; + SIGNAL n1iiOlil : STD_LOGIC := '0'; + SIGNAL n1iiOliO : STD_LOGIC := '0'; + SIGNAL n1iiOlli : STD_LOGIC := '0'; + SIGNAL n1iiOlll : STD_LOGIC := '0'; + SIGNAL n1il100i : STD_LOGIC := '0'; + SIGNAL n1il100l : STD_LOGIC := '0'; + SIGNAL n1il100O : STD_LOGIC := '0'; + SIGNAL n1il101i : STD_LOGIC := '0'; + SIGNAL n1il101l : STD_LOGIC := '0'; + SIGNAL n1il101O : STD_LOGIC := '0'; + SIGNAL n1il10ii : STD_LOGIC := '0'; + SIGNAL n1il10il : STD_LOGIC := '0'; + SIGNAL n1il10iO : STD_LOGIC := '0'; + SIGNAL n1il10li : STD_LOGIC := '0'; + SIGNAL n1il10ll : STD_LOGIC := '0'; + SIGNAL n1il10lO : STD_LOGIC := '0'; + SIGNAL n1il10Oi : STD_LOGIC := '0'; + SIGNAL n1il10Ol : STD_LOGIC := '0'; + SIGNAL n1il10OO : STD_LOGIC := '0'; + SIGNAL n1il11il : STD_LOGIC := '0'; + SIGNAL n1il11li : STD_LOGIC := '0'; + SIGNAL n1il11ll : STD_LOGIC := '0'; + SIGNAL n1il11lO : STD_LOGIC := '0'; + SIGNAL n1il11Oi : STD_LOGIC := '0'; + SIGNAL n1il11OO : STD_LOGIC := '0'; + SIGNAL n1il1i0i : STD_LOGIC := '0'; + SIGNAL n1il1i0l : STD_LOGIC := '0'; + SIGNAL n1il1i1i : STD_LOGIC := '0'; + SIGNAL n1il1i1l : STD_LOGIC := '0'; + SIGNAL n1il1i1O : STD_LOGIC := '0'; + SIGNAL n1illOiO : STD_LOGIC := '0'; + SIGNAL n1ilOO0i : STD_LOGIC := '0'; + SIGNAL n1ilOO0l : STD_LOGIC := '0'; + SIGNAL n1ilOO0O : STD_LOGIC := '0'; + SIGNAL n1ilOO1i : STD_LOGIC := '0'; + SIGNAL n1ilOO1l : STD_LOGIC := '0'; + SIGNAL n1ilOO1O : STD_LOGIC := '0'; + SIGNAL n1ilOOii : STD_LOGIC := '0'; + SIGNAL n1ilOOil : STD_LOGIC := '0'; + SIGNAL n1ilOOiO : STD_LOGIC := '0'; + SIGNAL n1ilOOli : STD_LOGIC := '0'; + SIGNAL n1ilOOll : STD_LOGIC := '0'; + SIGNAL n1ilOOlO : STD_LOGIC := '0'; + SIGNAL n1ilOOOi : STD_LOGIC := '0'; + SIGNAL n1ilOOOl : STD_LOGIC := '0'; + SIGNAL n1ilOOOO : STD_LOGIC := '0'; + SIGNAL n1iO001i : STD_LOGIC := '0'; + SIGNAL n1iO001l : STD_LOGIC := '0'; + SIGNAL n1iO01Oi : STD_LOGIC := '0'; + SIGNAL n1iO01Ol : STD_LOGIC := '0'; + SIGNAL n1iO01OO : STD_LOGIC := '0'; + SIGNAL n1iO0ili : STD_LOGIC := '0'; + SIGNAL n1iO0ill : STD_LOGIC := '0'; + SIGNAL n1iO0ilO : STD_LOGIC := '0'; + SIGNAL n1iO0iOi : STD_LOGIC := '0'; + SIGNAL n1iO0iOl : STD_LOGIC := '0'; + SIGNAL n1iO0iOO : STD_LOGIC := '0'; + SIGNAL n1iO0l0i : STD_LOGIC := '0'; + SIGNAL n1iO0l0l : STD_LOGIC := '0'; + SIGNAL n1iO0l0O : STD_LOGIC := '0'; + SIGNAL n1iO0l1i : STD_LOGIC := '0'; + SIGNAL n1iO0l1l : STD_LOGIC := '0'; + SIGNAL n1iO0l1O : STD_LOGIC := '0'; + SIGNAL n1iO110i : STD_LOGIC := '0'; + SIGNAL n1iO110l : STD_LOGIC := '0'; + SIGNAL n1iO110O : STD_LOGIC := '0'; + SIGNAL n1iO111i : STD_LOGIC := '0'; + SIGNAL n1iO111l : STD_LOGIC := '0'; + SIGNAL n1iO111O : STD_LOGIC := '0'; + SIGNAL n1iO11ii : STD_LOGIC := '0'; + SIGNAL n1iO11il : STD_LOGIC := '0'; + SIGNAL n1iO11iO : STD_LOGIC := '0'; + SIGNAL n1iOl00i : STD_LOGIC := '0'; + SIGNAL n1iOl00l : STD_LOGIC := '0'; + SIGNAL n1iOl00O : STD_LOGIC := '0'; + SIGNAL n1iOl01i : STD_LOGIC := '0'; + SIGNAL n1iOl01l : STD_LOGIC := '0'; + SIGNAL n1iOl01O : STD_LOGIC := '0'; + SIGNAL n1iOl0ii : STD_LOGIC := '0'; + SIGNAL n1iOl0il : STD_LOGIC := '0'; + SIGNAL n1iOl0iO : STD_LOGIC := '0'; + SIGNAL n1iOl0li : STD_LOGIC := '0'; + SIGNAL n1iOl0ll : STD_LOGIC := '0'; + SIGNAL n1iOl0lO : STD_LOGIC := '0'; + SIGNAL n1iOl0Oi : STD_LOGIC := '0'; + SIGNAL n1iOl0Ol : STD_LOGIC := '0'; + SIGNAL n1iOl10i : STD_LOGIC := '0'; + SIGNAL n1iOl10l : STD_LOGIC := '0'; + SIGNAL n1iOl10O : STD_LOGIC := '0'; + SIGNAL n1iOl1ii : STD_LOGIC := '0'; + SIGNAL n1iOl1il : STD_LOGIC := '0'; + SIGNAL n1iOl1iO : STD_LOGIC := '0'; + SIGNAL n1iOl1li : STD_LOGIC := '0'; + SIGNAL n1iOl1ll : STD_LOGIC := '0'; + SIGNAL n1iOl1lO : STD_LOGIC := '0'; + SIGNAL n1iOl1Oi : STD_LOGIC := '0'; + SIGNAL n1iOl1Ol : STD_LOGIC := '0'; + SIGNAL n1iOl1OO : STD_LOGIC := '0'; + SIGNAL n1l0000i : STD_LOGIC := '0'; + SIGNAL n1l0000l : STD_LOGIC := '0'; + SIGNAL n1l0000O : STD_LOGIC := '0'; + SIGNAL n1l0001i : STD_LOGIC := '0'; + SIGNAL n1l0001l : STD_LOGIC := '0'; + SIGNAL n1l0001O : STD_LOGIC := '0'; + SIGNAL n1l000ii : STD_LOGIC := '0'; + SIGNAL n1l000il : STD_LOGIC := '0'; + SIGNAL n1l000iO : STD_LOGIC := '0'; + SIGNAL n1l000li : STD_LOGIC := '0'; + SIGNAL n1l000ll : STD_LOGIC := '0'; + SIGNAL n1l000lO : STD_LOGIC := '0'; + SIGNAL n1l000Oi : STD_LOGIC := '0'; + SIGNAL n1l000Ol : STD_LOGIC := '0'; + SIGNAL n1l000OO : STD_LOGIC := '0'; + SIGNAL n1l0010i : STD_LOGIC := '0'; + SIGNAL n1l0010l : STD_LOGIC := '0'; + SIGNAL n1l0010O : STD_LOGIC := '0'; + SIGNAL n1l0011l : STD_LOGIC := '0'; + SIGNAL n1l0011O : STD_LOGIC := '0'; + SIGNAL n1l001ii : STD_LOGIC := '0'; + SIGNAL n1l001il : STD_LOGIC := '0'; + SIGNAL n1l001iO : STD_LOGIC := '0'; + SIGNAL n1l001li : STD_LOGIC := '0'; + SIGNAL n1l001ll : STD_LOGIC := '0'; + SIGNAL n1l001lO : STD_LOGIC := '0'; + SIGNAL n1l001Oi : STD_LOGIC := '0'; + SIGNAL n1l001Ol : STD_LOGIC := '0'; + SIGNAL n1l001OO : STD_LOGIC := '0'; + SIGNAL n1l00i0i : STD_LOGIC := '0'; + SIGNAL n1l00i1i : STD_LOGIC := '0'; + SIGNAL n1l00i1l : STD_LOGIC := '0'; + SIGNAL n1l00i1O : STD_LOGIC := '0'; + SIGNAL n1l10iiO : STD_LOGIC := '0'; + SIGNAL n1l1100i : STD_LOGIC := '0'; + SIGNAL n1l1100l : STD_LOGIC := '0'; + SIGNAL n1l1100O : STD_LOGIC := '0'; + SIGNAL n1l1101i : STD_LOGIC := '0'; + SIGNAL n1l1101l : STD_LOGIC := '0'; + SIGNAL n1l1101O : STD_LOGIC := '0'; + SIGNAL n1l110ii : STD_LOGIC := '0'; + SIGNAL n1l110il : STD_LOGIC := '0'; + SIGNAL n1l110iO : STD_LOGIC := '0'; + SIGNAL n1l1O1il : STD_LOGIC := '0'; + SIGNAL n1l1O1iO : STD_LOGIC := '0'; + SIGNAL n1l1O1li : STD_LOGIC := '0'; + SIGNAL n1l1O1ll : STD_LOGIC := '0'; + SIGNAL n1l1O1lO : STD_LOGIC := '0'; + SIGNAL n1l1O1Oi : STD_LOGIC := '0'; + SIGNAL n1l1O1Ol : STD_LOGIC := '0'; + SIGNAL n1l1O1OO : STD_LOGIC := '0'; + SIGNAL n1l1Ol0l : STD_LOGIC := '0'; + SIGNAL n1l1Olll : STD_LOGIC := '0'; + SIGNAL n1l1OllO : STD_LOGIC := '0'; + SIGNAL n1l1OlOi : STD_LOGIC := '0'; + SIGNAL n1l1OlOl : STD_LOGIC := '0'; + SIGNAL n1l1OlOO : STD_LOGIC := '0'; + SIGNAL n1l1OO0i : STD_LOGIC := '0'; + SIGNAL n1l1OO0O : STD_LOGIC := '0'; + SIGNAL n1l1OO1i : STD_LOGIC := '0'; + SIGNAL n1l1OO1l : STD_LOGIC := '0'; + SIGNAL n1l1OO1O : STD_LOGIC := '0'; + SIGNAL n1l1OOii : STD_LOGIC := '0'; + SIGNAL n1l1OOiO : STD_LOGIC := '0'; + SIGNAL n1l1OOll : STD_LOGIC := '0'; + SIGNAL n1l1OOlO : STD_LOGIC := '0'; + SIGNAL n1l1OOOl : STD_LOGIC := '0'; + SIGNAL n1lil0Ol : STD_LOGIC := '0'; + SIGNAL n1lili0l : STD_LOGIC := '0'; + SIGNAL n1lilill : STD_LOGIC := '0'; + SIGNAL n1liliOi : STD_LOGIC := '0'; + SIGNAL n1liliOl : STD_LOGIC := '0'; + SIGNAL n1liliOO : STD_LOGIC := '0'; + SIGNAL n1lill0i : STD_LOGIC := '0'; + SIGNAL n1lill0l : STD_LOGIC := '0'; + SIGNAL n1lill0O : STD_LOGIC := '0'; + SIGNAL n1lill1i : STD_LOGIC := '0'; + SIGNAL n1lill1l : STD_LOGIC := '0'; + SIGNAL n1lill1O : STD_LOGIC := '0'; + SIGNAL n1lillii : STD_LOGIC := '0'; + SIGNAL n1lillil : STD_LOGIC := '0'; + SIGNAL n1lilliO : STD_LOGIC := '0'; + SIGNAL n1lillli : STD_LOGIC := '0'; + SIGNAL n1lillll : STD_LOGIC := '0'; + SIGNAL n1lilllO : STD_LOGIC := '0'; + SIGNAL n1lillOi : STD_LOGIC := '0'; + SIGNAL n1lillOl : STD_LOGIC := '0'; + SIGNAL n1lillOO : STD_LOGIC := '0'; + SIGNAL n1lilO0i : STD_LOGIC := '0'; + SIGNAL n1lilO0l : STD_LOGIC := '0'; + SIGNAL n1lilO1i : STD_LOGIC := '0'; + SIGNAL n1lilO1l : STD_LOGIC := '0'; + SIGNAL n1lilO1O : STD_LOGIC := '0'; + SIGNAL n1lilOii : STD_LOGIC := '0'; + SIGNAL n1lilOil : STD_LOGIC := '0'; + SIGNAL n1llO1Ol : STD_LOGIC := '0'; + SIGNAL n1lO0llO : STD_LOGIC := '0'; + SIGNAL n1lO0lOi : STD_LOGIC := '0'; + SIGNAL n1lO0lOl : STD_LOGIC := '0'; + SIGNAL n1lOi00i : STD_LOGIC := '0'; + SIGNAL n1lOi00l : STD_LOGIC := '0'; + SIGNAL n1lOi00O : STD_LOGIC := '0'; + SIGNAL n1lOi01i : STD_LOGIC := '0'; + SIGNAL n1lOi01l : STD_LOGIC := '0'; + SIGNAL n1lOi01O : STD_LOGIC := '0'; + SIGNAL n1lOi0il : STD_LOGIC := '0'; + SIGNAL n1lOi1lO : STD_LOGIC := '0'; + SIGNAL n1lOi1Oi : STD_LOGIC := '0'; + SIGNAL n1lOi1Ol : STD_LOGIC := '0'; + SIGNAL n1lOi1OO : STD_LOGIC := '0'; + SIGNAL n1lOO00i : STD_LOGIC := '0'; + SIGNAL n1lOO00l : STD_LOGIC := '0'; + SIGNAL n1lOO00O : STD_LOGIC := '0'; + SIGNAL n1lOO01i : STD_LOGIC := '0'; + SIGNAL n1lOO01l : STD_LOGIC := '0'; + SIGNAL n1lOO01O : STD_LOGIC := '0'; + SIGNAL n1lOO0ii : STD_LOGIC := '0'; + SIGNAL n1lOO0il : STD_LOGIC := '0'; + SIGNAL n1lOO0iO : STD_LOGIC := '0'; + SIGNAL n1lOO0li : STD_LOGIC := '0'; + SIGNAL n1lOO0ll : STD_LOGIC := '0'; + SIGNAL n1lOO0lO : STD_LOGIC := '0'; + SIGNAL n1lOO0Oi : STD_LOGIC := '0'; + SIGNAL n1lOO0Ol : STD_LOGIC := '0'; + SIGNAL n1lOO0OO : STD_LOGIC := '0'; + SIGNAL n1lOO10i : STD_LOGIC := '0'; + SIGNAL n1lOO10l : STD_LOGIC := '0'; + SIGNAL n1lOO10O : STD_LOGIC := '0'; + SIGNAL n1lOO11l : STD_LOGIC := '0'; + SIGNAL n1lOO11O : STD_LOGIC := '0'; + SIGNAL n1lOO1ii : STD_LOGIC := '0'; + SIGNAL n1lOO1il : STD_LOGIC := '0'; + SIGNAL n1lOO1iO : STD_LOGIC := '0'; + SIGNAL n1lOO1li : STD_LOGIC := '0'; + SIGNAL n1lOO1ll : STD_LOGIC := '0'; + SIGNAL n1lOO1lO : STD_LOGIC := '0'; + SIGNAL n1lOO1Oi : STD_LOGIC := '0'; + SIGNAL n1lOO1Ol : STD_LOGIC := '0'; + SIGNAL n1lOO1OO : STD_LOGIC := '0'; + SIGNAL n1lOOi0i : STD_LOGIC := '0'; + SIGNAL n1lOOi0l : STD_LOGIC := '0'; + SIGNAL n1lOOi0O : STD_LOGIC := '0'; + SIGNAL n1lOOi1i : STD_LOGIC := '0'; + SIGNAL n1lOOi1l : STD_LOGIC := '0'; + SIGNAL n1lOOi1O : STD_LOGIC := '0'; + SIGNAL n1lOOiii : STD_LOGIC := '0'; + SIGNAL n1lOOiil : STD_LOGIC := '0'; + SIGNAL n1lOOiiO : STD_LOGIC := '0'; + SIGNAL n1lOOili : STD_LOGIC := '0'; + SIGNAL n1lOOill : STD_LOGIC := '0'; + SIGNAL n1lOOilO : STD_LOGIC := '0'; + SIGNAL n1lOOiOi : STD_LOGIC := '0'; + SIGNAL n1lOOiOl : STD_LOGIC := '0'; + SIGNAL n1lOOiOO : STD_LOGIC := '0'; + SIGNAL n1lOOl0i : STD_LOGIC := '0'; + SIGNAL n1lOOl0l : STD_LOGIC := '0'; + SIGNAL n1lOOl0O : STD_LOGIC := '0'; + SIGNAL n1lOOl1i : STD_LOGIC := '0'; + SIGNAL n1lOOl1l : STD_LOGIC := '0'; + SIGNAL n1lOOl1O : STD_LOGIC := '0'; + SIGNAL n1lOOlii : STD_LOGIC := '0'; + SIGNAL n1lOOlil : STD_LOGIC := '0'; + SIGNAL n1lOOliO : STD_LOGIC := '0'; + SIGNAL n1lOOlli : STD_LOGIC := '0'; + SIGNAL n1lOOlll : STD_LOGIC := '0'; + SIGNAL n1lOOllO : STD_LOGIC := '0'; + SIGNAL n1lOOlOi : STD_LOGIC := '0'; + SIGNAL n1lOOlOl : STD_LOGIC := '0'; + SIGNAL n1lOOlOO : STD_LOGIC := '0'; + SIGNAL n1lOOO0i : STD_LOGIC := '0'; + SIGNAL n1lOOO0l : STD_LOGIC := '0'; + SIGNAL n1lOOO0O : STD_LOGIC := '0'; + SIGNAL n1lOOO1i : STD_LOGIC := '0'; + SIGNAL n1lOOO1l : STD_LOGIC := '0'; + SIGNAL n1lOOO1O : STD_LOGIC := '0'; + SIGNAL n1lOOOii : STD_LOGIC := '0'; + SIGNAL n1lOOOil : STD_LOGIC := '0'; + SIGNAL n1lOOOiO : STD_LOGIC := '0'; + SIGNAL n1lOOOli : STD_LOGIC := '0'; + SIGNAL n1lOOOll : STD_LOGIC := '0'; + SIGNAL n1lOOOlO : STD_LOGIC := '0'; + SIGNAL n1O01iOO : STD_LOGIC := '0'; + SIGNAL n1O01lll : STD_LOGIC := '0'; + SIGNAL n1O01llO : STD_LOGIC := '0'; + SIGNAL n1O01lOi : STD_LOGIC := '0'; + SIGNAL n1O01lOl : STD_LOGIC := '0'; + SIGNAL n1O01lOO : STD_LOGIC := '0'; + SIGNAL n1O01O0i : STD_LOGIC := '0'; + SIGNAL n1O01O0l : STD_LOGIC := '0'; + SIGNAL n1O01O0O : STD_LOGIC := '0'; + SIGNAL n1O01O1i : STD_LOGIC := '0'; + SIGNAL n1O01O1l : STD_LOGIC := '0'; + SIGNAL n1O01O1O : STD_LOGIC := '0'; + SIGNAL n1O01Oii : STD_LOGIC := '0'; + SIGNAL n1O01Oil : STD_LOGIC := '0'; + SIGNAL n1O01OiO : STD_LOGIC := '0'; + SIGNAL n1O01Oli : STD_LOGIC := '0'; + SIGNAL n1O01Oll : STD_LOGIC := '0'; + SIGNAL n1O0i00l : STD_LOGIC := '0'; + SIGNAL n1O0i00O : STD_LOGIC := '0'; + SIGNAL n1O0i0ii : STD_LOGIC := '0'; + SIGNAL n1O0i0il : STD_LOGIC := '0'; + SIGNAL n1O0i0iO : STD_LOGIC := '0'; + SIGNAL n1O0i0li : STD_LOGIC := '0'; + SIGNAL n1O0i0ll : STD_LOGIC := '0'; + SIGNAL n1O0i0lO : STD_LOGIC := '0'; + SIGNAL n1O0i0Oi : STD_LOGIC := '0'; + SIGNAL n1O0i0Ol : STD_LOGIC := '0'; + SIGNAL n1O0i0OO : STD_LOGIC := '0'; + SIGNAL n1O0i1iO : STD_LOGIC := '0'; + SIGNAL n1O0ii0i : STD_LOGIC := '0'; + SIGNAL n1O0ii1i : STD_LOGIC := '0'; + SIGNAL n1O0ii1l : STD_LOGIC := '0'; + SIGNAL n1O0ii1O : STD_LOGIC := '0'; + SIGNAL n1O0Oi0l : STD_LOGIC := '0'; + SIGNAL n1O0Oi0O : STD_LOGIC := '0'; + SIGNAL n1O0Oiii : STD_LOGIC := '0'; + SIGNAL n1O0Oiil : STD_LOGIC := '0'; + SIGNAL n1O0Ol1i : STD_LOGIC := '0'; + SIGNAL n1O0Olli : STD_LOGIC := '0'; + SIGNAL n1O0Olll : STD_LOGIC := '0'; + SIGNAL n1O0OllO : STD_LOGIC := '0'; + SIGNAL n1O0OlOi : STD_LOGIC := '0'; + SIGNAL n1Oi000i : STD_LOGIC := '0'; + SIGNAL n1Oi001i : STD_LOGIC := '0'; + SIGNAL n1Oi001l : STD_LOGIC := '0'; + SIGNAL n1Oi001O : STD_LOGIC := '0'; + SIGNAL n1Oi010i : STD_LOGIC := '0'; + SIGNAL n1Oi010l : STD_LOGIC := '0'; + SIGNAL n1Oi010O : STD_LOGIC := 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n1OiliOO : STD_LOGIC := '0'; + SIGNAL n1Oill0i : STD_LOGIC := '0'; + SIGNAL n1Oill0l : STD_LOGIC := '0'; + SIGNAL n1Oill0O : STD_LOGIC := '0'; + SIGNAL n1Oill1i : STD_LOGIC := '0'; + SIGNAL n1Oill1l : STD_LOGIC := '0'; + SIGNAL n1Oill1O : STD_LOGIC := '0'; + SIGNAL n1Oillii : STD_LOGIC := '0'; + SIGNAL n1Oillil : STD_LOGIC := '0'; + SIGNAL n1OilliO : STD_LOGIC := '0'; + SIGNAL n1Oillli : STD_LOGIC := '0'; + SIGNAL n1Oillll : STD_LOGIC := '0'; + SIGNAL n1OilllO : STD_LOGIC := '0'; + SIGNAL n1OillOi : STD_LOGIC := '0'; + SIGNAL n1OillOl : STD_LOGIC := '0'; + SIGNAL n1OillOO : STD_LOGIC := '0'; + SIGNAL n1OilO0i : STD_LOGIC := '0'; + SIGNAL n1OilO0l : STD_LOGIC := '0'; + SIGNAL n1OilO0O : STD_LOGIC := '0'; + SIGNAL n1OilO1i : STD_LOGIC := '0'; + SIGNAL n1OilO1l : STD_LOGIC := '0'; + SIGNAL n1OilO1O : STD_LOGIC := '0'; + SIGNAL n1OilOii : STD_LOGIC := '0'; + SIGNAL n1OilOil : STD_LOGIC := '0'; + SIGNAL n1OilOiO : STD_LOGIC := '0'; + SIGNAL n1OilOli : STD_LOGIC := '0'; + SIGNAL n1OilOll : STD_LOGIC := '0'; + SIGNAL n1OiO11i : STD_LOGIC := '0'; + SIGNAL n1Ol000i : STD_LOGIC := '0'; + SIGNAL n1Ol000l : STD_LOGIC := '0'; + SIGNAL n1Ol000O : STD_LOGIC := '0'; + SIGNAL n1Ol001l : STD_LOGIC := '0'; + SIGNAL n1Ol001O : STD_LOGIC := '0'; + SIGNAL n1Ol00ii : STD_LOGIC := '0'; + SIGNAL n1Ol00il : STD_LOGIC := '0'; + SIGNAL n1Ol00iO : STD_LOGIC := '0'; + SIGNAL n1Ol00li : STD_LOGIC := '0'; + SIGNAL n1Ol00ll : STD_LOGIC := '0'; + SIGNAL n1Ol011i : STD_LOGIC := '0'; + SIGNAL n1Ol011l : STD_LOGIC := '0'; + SIGNAL n1Ol0lil : STD_LOGIC := '0'; + SIGNAL n1Ol0liO : STD_LOGIC := '0'; + SIGNAL n1Ol0lli : STD_LOGIC := '0'; + SIGNAL n1Ol0lll : STD_LOGIC := '0'; + SIGNAL n1Ol0llO : STD_LOGIC := '0'; + SIGNAL n1Ol0lOi : STD_LOGIC := '0'; + SIGNAL n1Ol1OOl : STD_LOGIC := '0'; + SIGNAL n1Ol1OOO : STD_LOGIC := '0'; + SIGNAL n1Oli00i : STD_LOGIC := '0'; + SIGNAL n1Oli00l : STD_LOGIC := '0'; + SIGNAL n1Oli00O : STD_LOGIC := '0'; + SIGNAL n1Oli0ii : STD_LOGIC := '0'; + SIGNAL n1Oli0il : STD_LOGIC := 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n1OOliOi : STD_LOGIC := '0'; + SIGNAL n1OOliOl : STD_LOGIC := '0'; + SIGNAL n1OOliOO : STD_LOGIC := '0'; + SIGNAL n1OOOlOi : STD_LOGIC := '0'; + SIGNAL n1OOOOiO : STD_LOGIC := '0'; + SIGNAL n1OOOOli : STD_LOGIC := '0'; + SIGNAL n1OOOOll : STD_LOGIC := '0'; + SIGNAL n1OOOOlO : STD_LOGIC := '0'; + SIGNAL n1OOOOOi : STD_LOGIC := '0'; + SIGNAL n1OOOOOl : STD_LOGIC := '0'; + SIGNAL n1OOOOOO : STD_LOGIC := '0'; + SIGNAL ni00011i : STD_LOGIC := '0'; + SIGNAL ni000i0i : STD_LOGIC := '0'; + SIGNAL ni000i0l : STD_LOGIC := '0'; + SIGNAL ni000i0O : STD_LOGIC := '0'; + SIGNAL ni000i1O : STD_LOGIC := '0'; + SIGNAL ni000iii : STD_LOGIC := '0'; + SIGNAL ni000iil : STD_LOGIC := '0'; + SIGNAL ni000iiO : STD_LOGIC := '0'; + SIGNAL ni000ili : STD_LOGIC := '0'; + SIGNAL ni000ill : STD_LOGIC := '0'; + SIGNAL ni000OOi : STD_LOGIC := '0'; + SIGNAL ni000OOl : STD_LOGIC := '0'; + SIGNAL ni000OOO : STD_LOGIC := '0'; + SIGNAL ni0010Oi : STD_LOGIC := '0'; + SIGNAL ni0010Ol : STD_LOGIC := '0'; + SIGNAL ni0010OO : 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ni011lOl : STD_LOGIC := '0'; + SIGNAL ni01i00O : STD_LOGIC := '0'; + SIGNAL ni01i0ii : STD_LOGIC := '0'; + SIGNAL ni01i0il : STD_LOGIC := '0'; + SIGNAL ni01i0iO : STD_LOGIC := '0'; + SIGNAL ni01i0li : STD_LOGIC := '0'; + SIGNAL ni01i0ll : STD_LOGIC := '0'; + SIGNAL ni01i0lO : STD_LOGIC := '0'; + SIGNAL ni01i0Oi : STD_LOGIC := '0'; + SIGNAL ni01i0Ol : STD_LOGIC := '0'; + SIGNAL ni01iO0i : STD_LOGIC := '0'; + SIGNAL ni01iO0l : STD_LOGIC := '0'; + SIGNAL ni01iO0O : STD_LOGIC := '0'; + SIGNAL ni01iO1i : STD_LOGIC := '0'; + SIGNAL ni01iO1l : STD_LOGIC := '0'; + SIGNAL ni01iO1O : STD_LOGIC := '0'; + SIGNAL ni01iOii : STD_LOGIC := '0'; + SIGNAL ni01iOil : STD_LOGIC := '0'; + SIGNAL ni01iOiO : STD_LOGIC := '0'; + SIGNAL ni01l0ll : STD_LOGIC := '0'; + SIGNAL ni01l0lO : STD_LOGIC := '0'; + SIGNAL ni01l0Oi : STD_LOGIC := '0'; + SIGNAL ni01l0Ol : STD_LOGIC := '0'; + SIGNAL ni01l0OO : STD_LOGIC := '0'; + SIGNAL ni01li0i : STD_LOGIC := '0'; + SIGNAL ni01li1i : STD_LOGIC := '0'; + SIGNAL ni01li1l : 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'0'; + SIGNAL ni0i000O : STD_LOGIC := '0'; + SIGNAL ni0i001i : STD_LOGIC := '0'; + SIGNAL ni0i001l : STD_LOGIC := '0'; + SIGNAL ni0i001O : STD_LOGIC := '0'; + SIGNAL ni0i00ii : STD_LOGIC := '0'; + SIGNAL ni0i00il : STD_LOGIC := '0'; + SIGNAL ni0i00iO : STD_LOGIC := '0'; + SIGNAL ni0i00li : STD_LOGIC := '0'; + SIGNAL ni0i00ll : STD_LOGIC := '0'; + SIGNAL ni0i00lO : STD_LOGIC := '0'; + SIGNAL ni0i00Oi : STD_LOGIC := '0'; + SIGNAL ni0i00Ol : STD_LOGIC := '0'; + SIGNAL ni0i00OO : STD_LOGIC := '0'; + SIGNAL ni0i010i : STD_LOGIC := '0'; + SIGNAL ni0i010l : STD_LOGIC := '0'; + SIGNAL ni0i010O : STD_LOGIC := '0'; + SIGNAL ni0i011i : STD_LOGIC := '0'; + SIGNAL ni0i011l : STD_LOGIC := '0'; + SIGNAL ni0i011O : STD_LOGIC := '0'; + SIGNAL ni0i01ii : STD_LOGIC := '0'; + SIGNAL ni0i01il : STD_LOGIC := '0'; + SIGNAL ni0i01iO : STD_LOGIC := '0'; + SIGNAL ni0i01li : STD_LOGIC := '0'; + SIGNAL ni0i01ll : STD_LOGIC := '0'; + SIGNAL ni0i01lO : STD_LOGIC := '0'; + SIGNAL ni0i01Oi : STD_LOGIC := '0'; + SIGNAL ni0i01Ol : STD_LOGIC := '0'; + SIGNAL ni0i01OO : STD_LOGIC := '0'; + SIGNAL ni0i0i0i : STD_LOGIC := '0'; + SIGNAL ni0i0i0l : STD_LOGIC := '0'; + SIGNAL ni0i0i0O : STD_LOGIC := '0'; + SIGNAL ni0i0i1i : STD_LOGIC := '0'; + SIGNAL ni0i0i1l : STD_LOGIC := '0'; + SIGNAL ni0i0i1O : STD_LOGIC := '0'; + SIGNAL ni0i100i : STD_LOGIC := '0'; + SIGNAL ni0i100l : STD_LOGIC := '0'; + SIGNAL ni0i100O : STD_LOGIC := '0'; + SIGNAL ni0i101i : STD_LOGIC := '0'; + SIGNAL ni0i101l : STD_LOGIC := '0'; + SIGNAL ni0i101O : STD_LOGIC := '0'; + SIGNAL ni0i10ii : STD_LOGIC := '0'; + SIGNAL ni0i10il : STD_LOGIC := '0'; + SIGNAL ni0i10iO : STD_LOGIC := '0'; + SIGNAL ni0i10li : STD_LOGIC := '0'; + SIGNAL ni0i10ll : STD_LOGIC := '0'; + SIGNAL ni0i10lO : STD_LOGIC := '0'; + SIGNAL ni0i10Oi : STD_LOGIC := '0'; + SIGNAL ni0i10Ol : STD_LOGIC := '0'; + SIGNAL ni0i10OO : STD_LOGIC := '0'; + SIGNAL ni0i110i : STD_LOGIC := '0'; + SIGNAL ni0i110l : STD_LOGIC := '0'; + SIGNAL ni0i111l : STD_LOGIC := '0'; + SIGNAL ni0i111O : STD_LOGIC := '0'; + SIGNAL ni0i1i0i : STD_LOGIC := '0'; + SIGNAL ni0i1i0l : STD_LOGIC := '0'; + SIGNAL ni0i1i0O : STD_LOGIC := '0'; + SIGNAL ni0i1i1i : STD_LOGIC := '0'; + SIGNAL ni0i1i1l : STD_LOGIC := '0'; + SIGNAL ni0i1i1O : STD_LOGIC := '0'; + SIGNAL ni0i1iii : STD_LOGIC := '0'; + SIGNAL ni0i1iil : STD_LOGIC := '0'; + SIGNAL ni0i1iiO : STD_LOGIC := '0'; + SIGNAL ni0i1ili : STD_LOGIC := '0'; + SIGNAL ni0i1ill : STD_LOGIC := '0'; + SIGNAL ni0i1ilO : STD_LOGIC := '0'; + SIGNAL ni0i1iOi : STD_LOGIC := '0'; + SIGNAL ni0i1iOl : STD_LOGIC := '0'; + SIGNAL ni0i1iOO : STD_LOGIC := '0'; + SIGNAL ni0i1l0i : STD_LOGIC := '0'; + SIGNAL ni0i1l0l : STD_LOGIC := '0'; + SIGNAL ni0i1l0O : STD_LOGIC := '0'; + SIGNAL ni0i1l1i : STD_LOGIC := '0'; + SIGNAL ni0i1l1l : STD_LOGIC := '0'; + SIGNAL ni0i1l1O : STD_LOGIC := '0'; + SIGNAL ni0i1lii : STD_LOGIC := '0'; + SIGNAL ni0i1lil : STD_LOGIC := '0'; + SIGNAL ni0i1liO : STD_LOGIC := '0'; + SIGNAL ni0i1lli : STD_LOGIC := '0'; + SIGNAL ni0i1lll : STD_LOGIC := '0'; + SIGNAL ni0i1llO : STD_LOGIC := '0'; + SIGNAL ni0i1lOi : STD_LOGIC := '0'; + SIGNAL ni0i1lOl : STD_LOGIC := '0'; + SIGNAL ni0i1lOO : STD_LOGIC := '0'; + SIGNAL ni0i1O0i : STD_LOGIC := '0'; + SIGNAL ni0i1O0l : STD_LOGIC := '0'; + SIGNAL ni0i1O0O : STD_LOGIC := '0'; + SIGNAL ni0i1O1i : STD_LOGIC := '0'; + SIGNAL ni0i1O1l : STD_LOGIC := '0'; + SIGNAL ni0i1O1O : STD_LOGIC := '0'; + SIGNAL ni0i1Oii : STD_LOGIC := '0'; + SIGNAL ni0i1Oil : STD_LOGIC := '0'; + SIGNAL ni0i1OiO : STD_LOGIC := '0'; + SIGNAL ni0i1Oli : STD_LOGIC := '0'; + SIGNAL ni0i1Oll : STD_LOGIC := '0'; + SIGNAL ni0i1OlO : STD_LOGIC := '0'; + SIGNAL ni0i1OOi : STD_LOGIC := '0'; + SIGNAL ni0i1OOl : STD_LOGIC := '0'; + SIGNAL ni0i1OOO : STD_LOGIC := '0'; + SIGNAL ni1000lO : STD_LOGIC := '0'; + SIGNAL ni1000Oi : STD_LOGIC := '0'; + SIGNAL ni1000Ol : STD_LOGIC := '0'; + SIGNAL ni1000OO : STD_LOGIC := '0'; + SIGNAL ni100i0i : STD_LOGIC := '0'; + SIGNAL ni100i0l : STD_LOGIC := '0'; + SIGNAL ni100i0O : STD_LOGIC := '0'; + SIGNAL ni100i1i : STD_LOGIC := '0'; + SIGNAL ni100i1l : STD_LOGIC := '0'; + SIGNAL ni100i1O : STD_LOGIC := '0'; + SIGNAL ni100Oil : STD_LOGIC := '0'; + SIGNAL ni100OiO : STD_LOGIC := '0'; + SIGNAL ni100Oli : STD_LOGIC := '0'; + SIGNAL ni100Oll : STD_LOGIC := '0'; + SIGNAL ni100OlO : STD_LOGIC := '0'; + SIGNAL ni100OOi : STD_LOGIC := '0'; + SIGNAL ni100OOl : STD_LOGIC := '0'; + SIGNAL ni100OOO : STD_LOGIC := '0'; + SIGNAL ni101i0i : STD_LOGIC := '0'; + SIGNAL ni101i1i : STD_LOGIC := '0'; + SIGNAL ni101i1l : STD_LOGIC := '0'; + SIGNAL ni101i1O : STD_LOGIC := '0'; + SIGNAL ni101O0O : STD_LOGIC := '0'; + SIGNAL ni101Oii : STD_LOGIC := '0'; + SIGNAL ni101Oil : STD_LOGIC := '0'; + SIGNAL ni101OiO : STD_LOGIC := '0'; + SIGNAL ni101Oli : STD_LOGIC := '0'; + SIGNAL ni101Oll : STD_LOGIC := '0'; + SIGNAL ni101OlO : STD_LOGIC := '0'; + SIGNAL ni101OOi : STD_LOGIC := '0'; + SIGNAL ni101OOl : STD_LOGIC := '0'; + SIGNAL ni10i11i : STD_LOGIC := '0'; + SIGNAL ni10ii0i : STD_LOGIC := '0'; + SIGNAL ni10ii0l : STD_LOGIC := '0'; + SIGNAL ni10ii0O : STD_LOGIC := '0'; + SIGNAL ni10ii1O : STD_LOGIC := '0'; + SIGNAL ni10iiii : STD_LOGIC := '0'; + SIGNAL ni10iiil : STD_LOGIC := '0'; + SIGNAL ni10iiiO : STD_LOGIC := '0'; + SIGNAL ni10iili : STD_LOGIC := '0'; + SIGNAL ni10iill : STD_LOGIC := '0'; + SIGNAL ni10iOOi : STD_LOGIC := '0'; + SIGNAL ni10iOOl : STD_LOGIC := '0'; + SIGNAL ni10iOOO : STD_LOGIC := '0'; + SIGNAL ni10l10i : STD_LOGIC := '0'; + SIGNAL ni10l10l : STD_LOGIC := '0'; + SIGNAL ni10l10O : STD_LOGIC := '0'; + SIGNAL ni10l11i : STD_LOGIC := '0'; + SIGNAL ni10l11l : STD_LOGIC := '0'; + SIGNAL ni10l11O : STD_LOGIC := '0'; + SIGNAL ni10liil : STD_LOGIC := '0'; + SIGNAL ni10liiO : STD_LOGIC := '0'; + SIGNAL ni10lili : STD_LOGIC := '0'; + SIGNAL ni10lill : STD_LOGIC := '0'; + SIGNAL ni10lilO : STD_LOGIC := '0'; + SIGNAL ni10liOi : STD_LOGIC := '0'; + SIGNAL ni10liOl : STD_LOGIC := '0'; + SIGNAL ni10liOO : STD_LOGIC := '0'; + SIGNAL ni10ll1i : STD_LOGIC := '0'; + SIGNAL ni10O10i : STD_LOGIC := '0'; + SIGNAL ni10O10l : STD_LOGIC := '0'; + SIGNAL ni10O10O : STD_LOGIC := '0'; + SIGNAL ni10O11O : STD_LOGIC := '0'; + SIGNAL ni10O1ii : STD_LOGIC := '0'; + SIGNAL ni10O1il : STD_LOGIC := '0'; + SIGNAL ni10O1iO : STD_LOGIC := '0'; + SIGNAL ni10O1li : STD_LOGIC := '0'; + SIGNAL ni10O1ll : STD_LOGIC := '0'; + SIGNAL ni10OiOi : STD_LOGIC := '0'; + SIGNAL ni10OiOl : STD_LOGIC := '0'; + SIGNAL ni10OiOO : STD_LOGIC := '0'; + SIGNAL ni10Ol0i : STD_LOGIC := '0'; + SIGNAL ni10Ol0l : STD_LOGIC := '0'; + SIGNAL ni10Ol0O : STD_LOGIC := '0'; + SIGNAL ni10Ol1i : STD_LOGIC := '0'; + SIGNAL ni10Ol1l : STD_LOGIC := '0'; + SIGNAL ni10Ol1O : STD_LOGIC := '0'; + SIGNAL ni11000i : STD_LOGIC := '0'; + SIGNAL ni11000l : STD_LOGIC := '0'; + SIGNAL ni11000O : STD_LOGIC := '0'; + SIGNAL ni11001i : STD_LOGIC := '0'; + SIGNAL ni11001l : STD_LOGIC := '0'; + SIGNAL ni11001O : STD_LOGIC := '0'; + SIGNAL ni1100ii : STD_LOGIC := '0'; + SIGNAL ni1101Ol : STD_LOGIC := '0'; + SIGNAL ni1101OO : STD_LOGIC := '0'; + SIGNAL ni110l0l : STD_LOGIC := '0'; + SIGNAL ni110l0O : STD_LOGIC := '0'; + SIGNAL ni110lii : STD_LOGIC := '0'; + SIGNAL ni110lil : STD_LOGIC := '0'; + SIGNAL ni110liO : STD_LOGIC := '0'; + SIGNAL ni110lli : STD_LOGIC := '0'; + SIGNAL ni110lll : STD_LOGIC := '0'; + SIGNAL ni110llO : STD_LOGIC := '0'; + SIGNAL ni110lOi : STD_LOGIC := '0'; + SIGNAL ni110lOl : STD_LOGIC := '0'; + SIGNAL ni11100i : STD_LOGIC := '0'; + SIGNAL ni11100l : STD_LOGIC := '0'; + SIGNAL ni11100O : STD_LOGIC := '0'; + SIGNAL ni11101i : STD_LOGIC := '0'; + SIGNAL ni11101l : STD_LOGIC := '0'; + SIGNAL ni11101O : STD_LOGIC := '0'; + SIGNAL ni1110ii : STD_LOGIC := '0'; + SIGNAL ni1111Ol : STD_LOGIC := '0'; + SIGNAL ni1111OO : STD_LOGIC := '0'; + SIGNAL ni111liO : STD_LOGIC := '0'; + SIGNAL ni111lli : STD_LOGIC := '0'; + SIGNAL ni111lll : STD_LOGIC := '0'; + SIGNAL ni111llO : STD_LOGIC := '0'; + SIGNAL ni11i00i : STD_LOGIC := '0'; + SIGNAL ni11i00l : STD_LOGIC := '0'; + SIGNAL ni11i00O : STD_LOGIC := '0'; + SIGNAL ni11i01i : STD_LOGIC := '0'; + SIGNAL ni11i01l : STD_LOGIC := '0'; + SIGNAL ni11i01O : STD_LOGIC := '0'; + SIGNAL ni11i0ii : STD_LOGIC := '0'; + SIGNAL ni11i0il : STD_LOGIC := '0'; + SIGNAL ni11i0iO : STD_LOGIC := '0'; + SIGNAL ni11illl : STD_LOGIC := '0'; + SIGNAL ni11illO : STD_LOGIC := '0'; + SIGNAL ni11ilOi : STD_LOGIC := '0'; + SIGNAL ni11ilOl : STD_LOGIC := '0'; + SIGNAL ni11ilOO : STD_LOGIC := '0'; + SIGNAL ni11iO0i : STD_LOGIC := '0'; + SIGNAL ni11iO1i : STD_LOGIC := '0'; + SIGNAL ni11iO1l : STD_LOGIC := '0'; + SIGNAL ni11iO1O : STD_LOGIC := '0'; + SIGNAL ni11l00O : STD_LOGIC := '0'; + SIGNAL ni11l0ii : STD_LOGIC := '0'; + SIGNAL ni11l0il : STD_LOGIC := '0'; + SIGNAL ni11l0iO : STD_LOGIC := '0'; + SIGNAL ni11l0li : STD_LOGIC := '0'; + SIGNAL ni11l0ll : STD_LOGIC := '0'; + SIGNAL ni11l0lO : STD_LOGIC := '0'; + SIGNAL ni11l0Oi : STD_LOGIC := '0'; + SIGNAL ni11l0Ol : STD_LOGIC := '0'; + SIGNAL ni11lO0i : STD_LOGIC := '0'; + SIGNAL ni11lO0l : STD_LOGIC := '0'; + SIGNAL ni11lO0O : STD_LOGIC := '0'; + SIGNAL ni11lO1i : STD_LOGIC := '0'; + SIGNAL ni11lO1l : STD_LOGIC := '0'; + SIGNAL ni11lO1O : STD_LOGIC := '0'; + SIGNAL ni11lOii : STD_LOGIC := '0'; + SIGNAL ni11lOil : STD_LOGIC := '0'; + SIGNAL ni11lOiO : STD_LOGIC := '0'; + SIGNAL ni11O0ll : STD_LOGIC := '0'; + SIGNAL ni11O0lO : STD_LOGIC := '0'; + SIGNAL ni11O0Oi : STD_LOGIC := '0'; + SIGNAL ni11O0Ol : STD_LOGIC := '0'; + SIGNAL ni11O0OO : STD_LOGIC := '0'; + SIGNAL ni11Oi0i : STD_LOGIC := '0'; + SIGNAL ni11Oi1i : STD_LOGIC := '0'; + SIGNAL ni11Oi1l : STD_LOGIC := '0'; + SIGNAL ni11Oi1O : STD_LOGIC := '0'; + SIGNAL ni11OO0O : STD_LOGIC := '0'; + SIGNAL ni11OOii : STD_LOGIC := '0'; + SIGNAL ni11OOil : STD_LOGIC := '0'; + SIGNAL ni11OOiO : STD_LOGIC := '0'; + SIGNAL ni11OOli : STD_LOGIC := '0'; + SIGNAL ni11OOll : STD_LOGIC := '0'; + SIGNAL ni11OOlO : STD_LOGIC := '0'; + SIGNAL ni11OOOi : STD_LOGIC := '0'; + SIGNAL ni11OOOl : STD_LOGIC := '0'; + SIGNAL ni1i010i : STD_LOGIC := '0'; + SIGNAL ni1i010l : STD_LOGIC := '0'; + SIGNAL ni1i010O : STD_LOGIC := '0'; + SIGNAL ni1i01ii : STD_LOGIC := '0'; + SIGNAL ni1i01il : STD_LOGIC := '0'; + SIGNAL ni1i01iO : STD_LOGIC := '0'; + SIGNAL ni1i01li : STD_LOGIC := '0'; + SIGNAL ni1i01ll : STD_LOGIC := '0'; + SIGNAL ni1i01lO : STD_LOGIC := '0'; + SIGNAL ni1i01Oi : STD_LOGIC := '0'; + SIGNAL ni1i0iOO : STD_LOGIC := '0'; + SIGNAL ni1i0l0i : STD_LOGIC := '0'; + SIGNAL ni1i0l0l : STD_LOGIC := '0'; + SIGNAL ni1i0l0O : STD_LOGIC := '0'; + SIGNAL ni1i0l1i : STD_LOGIC := '0'; + SIGNAL ni1i0l1l : STD_LOGIC := '0'; + SIGNAL ni1i0l1O : STD_LOGIC := '0'; + SIGNAL ni1i0lii : STD_LOGIC := '0'; + SIGNAL ni1i0lil : STD_LOGIC := '0'; + SIGNAL ni1i11il : STD_LOGIC := '0'; + SIGNAL ni1i11iO : STD_LOGIC := '0'; + SIGNAL ni1i11li : STD_LOGIC := '0'; + SIGNAL ni1i11ll : STD_LOGIC := '0'; + SIGNAL ni1i1iOi : STD_LOGIC := '0'; + SIGNAL ni1i1iOl : STD_LOGIC := '0'; + SIGNAL ni1i1iOO : STD_LOGIC := '0'; + SIGNAL ni1i1l0i : STD_LOGIC := '0'; + SIGNAL ni1i1l0l : STD_LOGIC := '0'; + SIGNAL ni1i1l0O : STD_LOGIC := '0'; + SIGNAL ni1i1l1i : STD_LOGIC := '0'; + SIGNAL ni1i1l1l : STD_LOGIC := '0'; + SIGNAL ni1i1l1O : STD_LOGIC := '0'; + SIGNAL ni1ii01i : STD_LOGIC := '0'; + SIGNAL ni1ii01l : STD_LOGIC := '0'; + SIGNAL ni1ii01O : STD_LOGIC := '0'; + SIGNAL ni1ii1li : STD_LOGIC := '0'; + SIGNAL ni1ii1ll : STD_LOGIC := '0'; + SIGNAL ni1ii1lO : STD_LOGIC := '0'; + SIGNAL ni1ii1Oi : STD_LOGIC := '0'; + SIGNAL ni1ii1Ol : STD_LOGIC := '0'; + SIGNAL ni1ii1OO : STD_LOGIC := '0'; + SIGNAL ni1iil0l : STD_LOGIC := '0'; + SIGNAL ni1iil0O : STD_LOGIC := '0'; + SIGNAL ni1iilii : STD_LOGIC := '0'; + SIGNAL ni1iilil : STD_LOGIC := '0'; + SIGNAL ni1iiliO : STD_LOGIC := '0'; + SIGNAL ni1iilli : STD_LOGIC := '0'; + SIGNAL ni1iilll : STD_LOGIC := '0'; + SIGNAL ni1iillO : STD_LOGIC := '0'; + SIGNAL ni1iilOi : STD_LOGIC := '0'; + SIGNAL ni1il00i : STD_LOGIC := '0'; + SIGNAL ni1il00l : STD_LOGIC := '0'; + SIGNAL ni1il00O : STD_LOGIC := '0'; + SIGNAL ni1il01i : STD_LOGIC := '0'; + SIGNAL ni1il01l : STD_LOGIC := '0'; + SIGNAL ni1il01O : STD_LOGIC := '0'; + SIGNAL ni1il0ii : STD_LOGIC := '0'; + SIGNAL ni1il0il : STD_LOGIC := '0'; + SIGNAL ni1il1OO : STD_LOGIC := '0'; + SIGNAL ni1illli : STD_LOGIC := '0'; + SIGNAL ni1illll : STD_LOGIC := '0'; + SIGNAL ni1illlO : STD_LOGIC := '0'; + SIGNAL ni1illOi : STD_LOGIC := '0'; + SIGNAL ni1illOl : STD_LOGIC := '0'; + SIGNAL ni1illOO : STD_LOGIC := '0'; + SIGNAL ni1ilO1i : STD_LOGIC := '0'; + SIGNAL ni1ilO1l : STD_LOGIC := '0'; + SIGNAL ni1ilO1O : STD_LOGIC := '0'; + SIGNAL ni1iO00l : STD_LOGIC := '0'; + SIGNAL ni1iO00O : STD_LOGIC := '0'; + SIGNAL ni1iO0ii : STD_LOGIC := '0'; + SIGNAL ni1iO0il : STD_LOGIC := '0'; + SIGNAL ni1iO0iO : STD_LOGIC := '0'; + SIGNAL ni1iO0li : STD_LOGIC := '0'; + SIGNAL ni1iO0ll : STD_LOGIC := '0'; + SIGNAL ni1iO0lO : STD_LOGIC := '0'; + SIGNAL ni1iO0Oi : STD_LOGIC := '0'; + SIGNAL ni1iOlOO : STD_LOGIC := '0'; + SIGNAL ni1iOO1i : STD_LOGIC := '0'; + SIGNAL ni1iOO1l : STD_LOGIC := '0'; + SIGNAL ni1iOO1O : STD_LOGIC := '0'; + SIGNAL ni1l00ii : STD_LOGIC := '0'; + SIGNAL ni1l00il : STD_LOGIC := '0'; + SIGNAL ni1l00iO : STD_LOGIC := '0'; + SIGNAL ni1l00li : STD_LOGIC := '0'; + SIGNAL ni1l00ll : STD_LOGIC := '0'; + SIGNAL ni1l00lO : STD_LOGIC := '0'; + SIGNAL ni1l00Oi : STD_LOGIC := '0'; + SIGNAL ni1l00Ol : STD_LOGIC := '0'; + SIGNAL ni1l00OO : STD_LOGIC := '0'; + SIGNAL ni1l0O0i : STD_LOGIC := '0'; + SIGNAL ni1l0O0l : STD_LOGIC := '0'; + SIGNAL ni1l0O0O : STD_LOGIC := '0'; + SIGNAL ni1l0O1l : STD_LOGIC := '0'; + SIGNAL ni1l0O1O : STD_LOGIC := '0'; + SIGNAL ni1l0Oii : STD_LOGIC := '0'; + SIGNAL ni1l0Oil : STD_LOGIC := '0'; + SIGNAL ni1l0OiO : STD_LOGIC := '0'; + SIGNAL ni1l0Oli : STD_LOGIC := '0'; + SIGNAL ni1l100l : STD_LOGIC := '0'; + SIGNAL ni1l100O : STD_LOGIC := '0'; + SIGNAL ni1l10ii : STD_LOGIC := '0'; + SIGNAL ni1l10il : STD_LOGIC := '0'; + SIGNAL ni1l10iO : STD_LOGIC := '0'; + SIGNAL ni1l10li : STD_LOGIC := '0'; + SIGNAL ni1l10ll : STD_LOGIC := '0'; + SIGNAL ni1l10lO : STD_LOGIC := '0'; + SIGNAL ni1l10Oi : STD_LOGIC := '0'; + SIGNAL ni1l1lll : STD_LOGIC := '0'; + SIGNAL ni1l1llO : STD_LOGIC := '0'; + SIGNAL ni1l1lOi : STD_LOGIC := '0'; + SIGNAL ni1l1lOl : STD_LOGIC := '0'; + SIGNAL ni1l1lOO : STD_LOGIC := '0'; + SIGNAL ni1l1O0i : STD_LOGIC := '0'; + SIGNAL ni1l1O0l : STD_LOGIC := '0'; + SIGNAL ni1l1O1i : STD_LOGIC := '0'; + SIGNAL ni1l1O1l : STD_LOGIC := '0'; + SIGNAL ni1l1O1O : STD_LOGIC := '0'; + SIGNAL ni1li0lO : STD_LOGIC := '0'; + SIGNAL ni1li0Oi : STD_LOGIC := '0'; + SIGNAL ni1li0Ol : STD_LOGIC := '0'; + SIGNAL ni1li0OO : STD_LOGIC := '0'; + SIGNAL ni1lii0i : STD_LOGIC := '0'; + SIGNAL ni1lii0l : STD_LOGIC := '0'; + SIGNAL ni1lii1i : STD_LOGIC := '0'; + SIGNAL ni1lii1l : STD_LOGIC := '0'; + SIGNAL ni1lii1O : STD_LOGIC := '0'; + SIGNAL ni1liOii : STD_LOGIC := '0'; + SIGNAL ni1liOil : STD_LOGIC := '0'; + SIGNAL ni1liOiO : STD_LOGIC := '0'; + SIGNAL ni1liOli : STD_LOGIC := '0'; + SIGNAL ni1liOll : STD_LOGIC := '0'; + SIGNAL ni1liOlO : STD_LOGIC := '0'; + SIGNAL ni1liOOi : STD_LOGIC := '0'; + SIGNAL ni1liOOl : STD_LOGIC := '0'; + SIGNAL ni1liOOO : STD_LOGIC := '0'; + SIGNAL ni1lli0i : STD_LOGIC := '0'; + SIGNAL ni1lli0l : STD_LOGIC := '0'; + SIGNAL ni1lli0O : STD_LOGIC := '0'; + SIGNAL ni1lli1l : STD_LOGIC := '0'; + SIGNAL ni1lli1O : STD_LOGIC := '0'; + SIGNAL ni1lliii : STD_LOGIC := '0'; + SIGNAL ni1lliil : STD_LOGIC := '0'; + SIGNAL ni1lliiO : STD_LOGIC := '0'; + SIGNAL ni1llili : STD_LOGIC := '0'; + SIGNAL ni1llOlO : STD_LOGIC := '0'; + SIGNAL ni1llOOi : STD_LOGIC := '0'; + SIGNAL ni1llOOl : STD_LOGIC := '0'; + SIGNAL ni1llOOO : STD_LOGIC := '0'; + SIGNAL ni1lO10i : STD_LOGIC := '0'; + SIGNAL ni1lO10l : STD_LOGIC := '0'; + SIGNAL ni1lO11i : STD_LOGIC := '0'; + SIGNAL ni1lO11l : STD_LOGIC := '0'; + SIGNAL ni1lO11O : STD_LOGIC := '0'; + SIGNAL ni1lOiii : STD_LOGIC := '0'; + SIGNAL ni1lOiil : STD_LOGIC := '0'; + SIGNAL ni1lOiiO : STD_LOGIC := '0'; + SIGNAL ni1lOili : STD_LOGIC := '0'; + SIGNAL ni1lOOlO : STD_LOGIC := '0'; + SIGNAL ni1lOOOi : STD_LOGIC := '0'; + SIGNAL ni1lOOOl : STD_LOGIC := '0'; + SIGNAL ni1lOOOO : STD_LOGIC := '0'; + SIGNAL ni1O010i : STD_LOGIC := '0'; + SIGNAL ni1O010l : STD_LOGIC := '0'; + SIGNAL ni1O010O : STD_LOGIC := '0'; + SIGNAL ni1O011i : STD_LOGIC := '0'; + SIGNAL ni1O011l : STD_LOGIC := '0'; + SIGNAL ni1O011O : STD_LOGIC := '0'; + SIGNAL ni1O01ii : STD_LOGIC := '0'; + SIGNAL ni1O0iiO : STD_LOGIC := '0'; + SIGNAL ni1O0ili : STD_LOGIC := '0'; + SIGNAL ni1O0ill : STD_LOGIC := '0'; + SIGNAL ni1O0ilO : STD_LOGIC := '0'; + SIGNAL ni1O0iOi : STD_LOGIC := '0'; + SIGNAL ni1O0iOl : STD_LOGIC := '0'; + SIGNAL ni1O0iOO : STD_LOGIC := '0'; + SIGNAL ni1O0l1i : STD_LOGIC := '0'; + SIGNAL ni1O0l1l : STD_LOGIC := '0'; + SIGNAL ni1O110i : STD_LOGIC := '0'; + SIGNAL ni1O110l : STD_LOGIC := '0'; + SIGNAL ni1O111i : STD_LOGIC := '0'; + SIGNAL ni1O111l : STD_LOGIC := '0'; + SIGNAL ni1O111O : STD_LOGIC := '0'; + SIGNAL ni1O1i0i : STD_LOGIC := '0'; + SIGNAL ni1O1i0l : STD_LOGIC := '0'; + SIGNAL ni1O1i0O : STD_LOGIC := '0'; + SIGNAL ni1O1i1O : STD_LOGIC := '0'; + SIGNAL ni1O1iii : STD_LOGIC := '0'; + SIGNAL ni1O1iil : STD_LOGIC := '0'; + SIGNAL ni1O1iiO : STD_LOGIC := '0'; + SIGNAL ni1O1ili : STD_LOGIC := '0'; + SIGNAL ni1O1ill : STD_LOGIC := '0'; + SIGNAL ni1O1ilO : STD_LOGIC := '0'; + SIGNAL ni1O1OOl : STD_LOGIC := '0'; + SIGNAL ni1O1OOO : STD_LOGIC := '0'; + SIGNAL ni1Oi10i : STD_LOGIC := '0'; + SIGNAL ni1Oi10l : STD_LOGIC := '0'; + SIGNAL ni1Oi10O : STD_LOGIC := '0'; + SIGNAL ni1Oi1ii : STD_LOGIC := '0'; + SIGNAL ni1Oi1il : STD_LOGIC := '0'; + SIGNAL ni1Oi1iO : STD_LOGIC := '0'; + SIGNAL ni1Oi1li : STD_LOGIC := '0'; + SIGNAL ni1Oi1ll : STD_LOGIC := '0'; + SIGNAL ni1Oi1lO : STD_LOGIC := '0'; + SIGNAL ni1OiiOl : STD_LOGIC := '0'; + SIGNAL ni1OiiOO : STD_LOGIC := '0'; + SIGNAL ni1Oil0i : STD_LOGIC := '0'; + SIGNAL ni1Oil0l : STD_LOGIC := '0'; + SIGNAL ni1Oil0O : STD_LOGIC := '0'; + SIGNAL ni1Oil1i : STD_LOGIC := '0'; + SIGNAL ni1Oil1l : STD_LOGIC := '0'; + SIGNAL ni1Oil1O : STD_LOGIC := '0'; + SIGNAL ni1Oilii : STD_LOGIC := '0'; + SIGNAL ni1Ol01i : STD_LOGIC := '0'; + SIGNAL ni1Ol01l : STD_LOGIC := '0'; + SIGNAL ni1Ol1iO : STD_LOGIC := '0'; + SIGNAL ni1Ol1li : STD_LOGIC := '0'; + SIGNAL ni1Ol1ll : STD_LOGIC := '0'; + SIGNAL ni1Ol1lO : STD_LOGIC := '0'; + SIGNAL ni1Ol1Oi : STD_LOGIC := '0'; + SIGNAL ni1Ol1Ol : STD_LOGIC := '0'; + SIGNAL ni1Ol1OO : STD_LOGIC := '0'; + SIGNAL ni1Oll0i : STD_LOGIC := '0'; + SIGNAL ni1Oll0l : STD_LOGIC := '0'; + SIGNAL ni1Oll0O : STD_LOGIC := '0'; + SIGNAL ni1Ollii : STD_LOGIC := '0'; + SIGNAL ni1Ollil : STD_LOGIC := '0'; + SIGNAL ni1OlliO : STD_LOGIC := '0'; + SIGNAL ni1Ollli : STD_LOGIC := '0'; + SIGNAL ni1Ollll : STD_LOGIC := '0'; + SIGNAL ni1OlllO : STD_LOGIC := '0'; + SIGNAL ni1OO01i : STD_LOGIC := '0'; + SIGNAL ni1OO01l : STD_LOGIC := '0'; + SIGNAL ni1OO1Ol : STD_LOGIC := '0'; + SIGNAL ni1OO1OO : STD_LOGIC := '0'; + SIGNAL ni1OOl0i : STD_LOGIC := '0'; + SIGNAL ni1OOl0l : STD_LOGIC := '0'; + SIGNAL ni1OOl0O : STD_LOGIC := '0'; + SIGNAL ni1OOlii : STD_LOGIC := '0'; + SIGNAL ni1OOlil : STD_LOGIC := '0'; + SIGNAL ni1OOliO : STD_LOGIC := '0'; + SIGNAL ni1OOlli : STD_LOGIC := '0'; + SIGNAL ni1OOlll : STD_LOGIC := '0'; + SIGNAL ni1OOllO : STD_LOGIC := '0'; + SIGNAL nii0li1l : STD_LOGIC := '0'; + SIGNAL nii0lllO : STD_LOGIC := '0'; + SIGNAL nii0O1ii : STD_LOGIC := '0'; + SIGNAL nii0Oi1l : STD_LOGIC := '0'; + SIGNAL nii0OllO : STD_LOGIC := '0'; + SIGNAL niii00OO : STD_LOGIC := '0'; + SIGNAL niii0i1i : STD_LOGIC := '0'; + SIGNAL niii0i1l : STD_LOGIC := '0'; + SIGNAL niii0OOl : STD_LOGIC := '0'; + SIGNAL niii0OOO : STD_LOGIC := '0'; + SIGNAL niii11ii : STD_LOGIC := '0'; + SIGNAL niii1i1l : STD_LOGIC := '0'; + SIGNAL niii1llO : STD_LOGIC := '0'; + SIGNAL niii1O0l : STD_LOGIC := '0'; + SIGNAL niii1O0O : STD_LOGIC := '0'; + SIGNAL niii1Oii : STD_LOGIC := '0'; + SIGNAL niii1Oil : STD_LOGIC := '0'; + SIGNAL niii1OiO : STD_LOGIC := '0'; + SIGNAL niii1Oli : STD_LOGIC := '0'; + SIGNAL niii1Oll : STD_LOGIC := '0'; + SIGNAL niii1OlO : STD_LOGIC := '0'; + SIGNAL niiii00i : STD_LOGIC := '0'; + SIGNAL niiii00l : STD_LOGIC := '0'; + SIGNAL niiii00O : STD_LOGIC := '0'; + SIGNAL niiii01i : STD_LOGIC := '0'; + SIGNAL niiii01l : STD_LOGIC := '0'; + SIGNAL niiii01O : STD_LOGIC := '0'; + SIGNAL niiii0ii : STD_LOGIC := '0'; + SIGNAL niiii0il : STD_LOGIC := '0'; + SIGNAL niiii0iO : STD_LOGIC := '0'; + SIGNAL niiii0li : STD_LOGIC := '0'; + SIGNAL niiii0ll : STD_LOGIC := '0'; + SIGNAL niiii0lO : STD_LOGIC := '0'; + SIGNAL niiii0Oi : STD_LOGIC := '0'; + SIGNAL niiii0Ol : STD_LOGIC := '0'; + SIGNAL niiii0OO : STD_LOGIC := '0'; + SIGNAL niiii10i : STD_LOGIC := '0'; + SIGNAL niiii10l : STD_LOGIC := '0'; + SIGNAL niiii10O : STD_LOGIC := '0'; + SIGNAL niiii11i : STD_LOGIC := '0'; + SIGNAL niiii11l : STD_LOGIC := '0'; + SIGNAL niiii11O : STD_LOGIC := '0'; + SIGNAL niiii1ii : STD_LOGIC := '0'; + SIGNAL niiii1il : STD_LOGIC := '0'; + SIGNAL niiii1iO : STD_LOGIC := '0'; + SIGNAL niiii1li : STD_LOGIC := '0'; + SIGNAL niiii1ll : STD_LOGIC := '0'; + SIGNAL niiii1lO : STD_LOGIC := '0'; + SIGNAL niiii1Oi : STD_LOGIC := '0'; + SIGNAL niiii1Ol : STD_LOGIC := '0'; + SIGNAL niiii1OO : STD_LOGIC := '0'; + SIGNAL niiiii0i : STD_LOGIC := '0'; + SIGNAL niiiii0l : STD_LOGIC := '0'; + SIGNAL niiiii0O : STD_LOGIC := '0'; + SIGNAL niiiii1i : STD_LOGIC := '0'; + SIGNAL niiiii1l : STD_LOGIC := '0'; + SIGNAL niiiii1O : STD_LOGIC := '0'; + SIGNAL niiiiiii : STD_LOGIC := '0'; + SIGNAL niiiiiil : STD_LOGIC := '0'; + SIGNAL niiiiiiO : STD_LOGIC := '0'; + SIGNAL niiiiili : STD_LOGIC := '0'; + SIGNAL niiiiill : STD_LOGIC := '0'; + SIGNAL niiiiilO : STD_LOGIC := '0'; + SIGNAL niiiiiOi : STD_LOGIC := '0'; + SIGNAL niiiiiOl : STD_LOGIC := '0'; + SIGNAL niiiiiOO : STD_LOGIC := '0'; + SIGNAL niiiil0i : STD_LOGIC := '0'; + SIGNAL niiiil0l : STD_LOGIC := '0'; + SIGNAL niiiil0O : STD_LOGIC := '0'; + SIGNAL niiiil1i : STD_LOGIC := '0'; + SIGNAL niiiil1l : STD_LOGIC := '0'; + SIGNAL niiiil1O : STD_LOGIC := '0'; + SIGNAL niiiilii : STD_LOGIC := '0'; + SIGNAL niiiilil : STD_LOGIC := '0'; + SIGNAL niiiiliO : STD_LOGIC := '0'; + SIGNAL niiiilli : STD_LOGIC := '0'; + SIGNAL niiiilll : STD_LOGIC := '0'; + SIGNAL niiiillO : STD_LOGIC := '0'; + SIGNAL niiiilOi : STD_LOGIC := '0'; + SIGNAL niiiilOl : STD_LOGIC := '0'; + SIGNAL niiiilOO : STD_LOGIC := '0'; + SIGNAL niiiiO0i : STD_LOGIC := '0'; + SIGNAL niiiiO0l : STD_LOGIC := '0'; + SIGNAL niiiiO0O : STD_LOGIC := '0'; + SIGNAL niiiiO1i : STD_LOGIC := '0'; + SIGNAL niiiiO1l : STD_LOGIC := '0'; + SIGNAL niiiiO1O : STD_LOGIC := '0'; + SIGNAL niiiiOii : STD_LOGIC := '0'; + SIGNAL niiiiOil : STD_LOGIC := '0'; + SIGNAL niiiiOiO : STD_LOGIC := '0'; + SIGNAL niiiiOli : STD_LOGIC := '0'; + SIGNAL niiiiOll : STD_LOGIC := '0'; + SIGNAL niiiiOlO : STD_LOGIC := '0'; + SIGNAL niiiiOOi : STD_LOGIC := '0'; + SIGNAL niiiiOOl : STD_LOGIC := '0'; + SIGNAL niiiiOOO : STD_LOGIC := '0'; + SIGNAL niiil11i : STD_LOGIC := '0'; + SIGNAL niiil11l : STD_LOGIC := '0'; + SIGNAL niil00Ol : STD_LOGIC := '0'; + SIGNAL niil010i : STD_LOGIC := '0'; + SIGNAL niil010l : STD_LOGIC := '0'; + SIGNAL niil010O : STD_LOGIC := '0'; + SIGNAL niO010ii : STD_LOGIC := '0'; + SIGNAL niO010ll : STD_LOGIC := '0'; + SIGNAL niO011ii : STD_LOGIC := '0'; + SIGNAL niO011ll : STD_LOGIC := '0'; + SIGNAL niO01iii : STD_LOGIC := '0'; + SIGNAL niO01ilO : STD_LOGIC := '0'; + SIGNAL niO10OlO : STD_LOGIC := '0'; + SIGNAL niO10OOi : STD_LOGIC := '0'; + SIGNAL niO10OOl : STD_LOGIC := '0'; + SIGNAL niO10OOO : STD_LOGIC := '0'; + SIGNAL niO1i00i : STD_LOGIC := '0'; + SIGNAL niO1i00l : STD_LOGIC := '0'; + SIGNAL niO1i00O : STD_LOGIC := '0'; + SIGNAL niO1i01i : STD_LOGIC := '0'; + SIGNAL niO1i01l : STD_LOGIC := '0'; + SIGNAL niO1i01O : STD_LOGIC := '0'; + SIGNAL niO1i0ii : STD_LOGIC := '0'; + SIGNAL niO1i0il : STD_LOGIC := '0'; + SIGNAL niO1i0iO : STD_LOGIC := '0'; + SIGNAL niO1i0li : STD_LOGIC := '0'; + SIGNAL niO1i0ll : STD_LOGIC := '0'; + SIGNAL niO1i0lO : STD_LOGIC := '0'; + SIGNAL niO1i0Oi : STD_LOGIC := '0'; + SIGNAL niO1i0Ol : STD_LOGIC := '0'; + SIGNAL niO1i0OO : STD_LOGIC := '0'; + SIGNAL niO1i10i : STD_LOGIC := '0'; + SIGNAL niO1i10l : STD_LOGIC := '0'; + SIGNAL niO1i10O : STD_LOGIC := '0'; + SIGNAL niO1i11i : STD_LOGIC := '0'; + SIGNAL niO1i11l : STD_LOGIC := '0'; + SIGNAL niO1i11O : STD_LOGIC := '0'; + SIGNAL niO1i1ii : STD_LOGIC := '0'; + SIGNAL niO1i1il : STD_LOGIC := '0'; + SIGNAL niO1i1iO : STD_LOGIC := '0'; + SIGNAL niO1i1li : STD_LOGIC := '0'; + SIGNAL niO1i1ll : STD_LOGIC := '0'; + SIGNAL niO1i1lO : STD_LOGIC := '0'; + SIGNAL niO1i1Oi : STD_LOGIC := '0'; + SIGNAL niO1i1Ol : STD_LOGIC := '0'; + SIGNAL niO1i1OO : STD_LOGIC := '0'; + SIGNAL niO1ii0i : STD_LOGIC := '0'; + SIGNAL niO1ii0l : STD_LOGIC := '0'; + SIGNAL niO1ii0O : STD_LOGIC := '0'; + SIGNAL niO1ii1i : STD_LOGIC := '0'; + SIGNAL niO1ii1l : STD_LOGIC := '0'; + SIGNAL niO1ii1O : STD_LOGIC := '0'; + SIGNAL niO1iiii : STD_LOGIC := '0'; + SIGNAL niO1iiil : STD_LOGIC := '0'; + SIGNAL niO1iiiO : STD_LOGIC := '0'; + SIGNAL niO1iili : STD_LOGIC := '0'; + SIGNAL niO1iill : STD_LOGIC := '0'; + SIGNAL niO1iilO : STD_LOGIC := '0'; + SIGNAL niO1iiOi : STD_LOGIC := '0'; + SIGNAL niO1iiOl : STD_LOGIC := '0'; + SIGNAL niO1iiOO : STD_LOGIC := '0'; + SIGNAL niO1il0i : STD_LOGIC := '0'; + SIGNAL niO1il0l : STD_LOGIC := '0'; + SIGNAL niO1il0O : STD_LOGIC := '0'; + SIGNAL niO1il1i : STD_LOGIC := '0'; + SIGNAL niO1il1l : STD_LOGIC := '0'; + SIGNAL niO1il1O : STD_LOGIC := '0'; + SIGNAL niO1ilii : STD_LOGIC := '0'; + SIGNAL niO1ilil : STD_LOGIC := '0'; + SIGNAL niO1iliO : STD_LOGIC := '0'; + SIGNAL niO1illi : STD_LOGIC := '0'; + SIGNAL niO1illl : STD_LOGIC := '0'; + SIGNAL niO1illO : STD_LOGIC := '0'; + SIGNAL niO1ilOi : STD_LOGIC := '0'; + SIGNAL niO1ilOl : STD_LOGIC := '0'; + SIGNAL niO1ilOO : STD_LOGIC := '0'; + SIGNAL niO1iO0i : STD_LOGIC := '0'; + SIGNAL niO1iO0l : STD_LOGIC := '0'; + SIGNAL niO1iO0O : STD_LOGIC := '0'; + SIGNAL niO1iO1i : STD_LOGIC := '0'; + SIGNAL niO1iO1l : STD_LOGIC := '0'; + SIGNAL niO1iO1O : STD_LOGIC := '0'; + SIGNAL niO1iOii : STD_LOGIC := '0'; + SIGNAL niO1iOil : STD_LOGIC := '0'; + SIGNAL niO1iOiO : STD_LOGIC := '0'; + SIGNAL niO1iOli : STD_LOGIC := '0'; + SIGNAL niO1iOll : STD_LOGIC := '0'; + SIGNAL niO1iOlO : STD_LOGIC := '0'; + SIGNAL niO1iOOi : STD_LOGIC := '0'; + SIGNAL niO1iOOl : STD_LOGIC := '0'; + SIGNAL niO1iOOO : STD_LOGIC := '0'; + SIGNAL niO1l00i : STD_LOGIC := '0'; + SIGNAL niO1l00l : STD_LOGIC := '0'; + SIGNAL niO1l00O : STD_LOGIC := '0'; + SIGNAL niO1l01i : STD_LOGIC := '0'; + SIGNAL niO1l01l : STD_LOGIC := '0'; + SIGNAL niO1l01O : STD_LOGIC := '0'; + SIGNAL niO1l0ii : STD_LOGIC := '0'; + SIGNAL niO1l0il : STD_LOGIC := '0'; + SIGNAL niO1l0iO : STD_LOGIC := '0'; + SIGNAL niO1l0li : STD_LOGIC := '0'; + SIGNAL niO1l0ll : STD_LOGIC := '0'; + SIGNAL niO1l0lO : STD_LOGIC := '0'; + SIGNAL niO1l0Oi : STD_LOGIC := '0'; + SIGNAL niO1l0Ol : STD_LOGIC := '0'; + SIGNAL niO1l0OO : STD_LOGIC := '0'; + SIGNAL niO1l10i : STD_LOGIC := '0'; + SIGNAL niO1l10l : STD_LOGIC := '0'; + SIGNAL niO1l10O : STD_LOGIC := '0'; + SIGNAL niO1l11i : STD_LOGIC := '0'; + SIGNAL niO1l11l : STD_LOGIC := '0'; + SIGNAL niO1l11O : STD_LOGIC := '0'; + SIGNAL niO1l1ii : STD_LOGIC := '0'; + SIGNAL niO1l1il : STD_LOGIC := '0'; + SIGNAL niO1l1iO : STD_LOGIC := '0'; + SIGNAL niO1l1li : STD_LOGIC := '0'; + SIGNAL niO1l1ll : STD_LOGIC := '0'; + SIGNAL niO1l1lO : STD_LOGIC := '0'; + SIGNAL niO1l1Oi : STD_LOGIC := '0'; + SIGNAL niO1l1Ol : STD_LOGIC := '0'; + SIGNAL niO1l1OO : STD_LOGIC := '0'; + SIGNAL niO1li1i : STD_LOGIC := '0'; + SIGNAL niO1li1l : STD_LOGIC := '0'; + SIGNAL niO1OOlO : STD_LOGIC := '0'; + SIGNAL niOO0O0OO : STD_LOGIC := '0'; + SIGNAL niOO0Oi0i : STD_LOGIC := '0'; + SIGNAL niOO0Oi0l : STD_LOGIC := '0'; + SIGNAL niOO0Oi1i : STD_LOGIC := '0'; + SIGNAL niOO0Oi1l : STD_LOGIC := '0'; + SIGNAL niOO0Oi1O : STD_LOGIC := '0'; + SIGNAL niOO0Olii : STD_LOGIC := '0'; + SIGNAL niOO0OllO : STD_LOGIC := '0'; + SIGNAL niOO0OlOl : STD_LOGIC := '0'; + SIGNAL nlOi000li : STD_LOGIC := '0'; + SIGNAL nlOi0011i : STD_LOGIC := '0'; + SIGNAL nlOi001il : STD_LOGIC := '0'; + SIGNAL nlOi001ll : STD_LOGIC := '0'; + SIGNAL nlOi00i0l : STD_LOGIC := '0'; + SIGNAL nlOi00i1l : STD_LOGIC := '0'; + SIGNAL nlOi00iOO : STD_LOGIC := '0'; + SIGNAL nlOi00l0i : STD_LOGIC := '0'; + SIGNAL nlOi00liO : STD_LOGIC := '0'; + SIGNAL nlOi00lOi : STD_LOGIC := '0'; + SIGNAL nlOi00OOi : STD_LOGIC := '0'; + SIGNAL nlOi0i00l : STD_LOGIC := '0'; + SIGNAL nlOi0i10l : STD_LOGIC := '0'; + SIGNAL nlOi0i1il : STD_LOGIC := '0'; + SIGNAL nlOi0i1iO : STD_LOGIC := '0'; + SIGNAL nlOi0il0i : STD_LOGIC := '0'; + SIGNAL nlOi0il0l : STD_LOGIC := '0'; + SIGNAL nlOi0il0O : STD_LOGIC := '0'; + SIGNAL nlOi0il1O : STD_LOGIC := '0'; + SIGNAL nlOi0ilii : STD_LOGIC := '0'; + SIGNAL nlOi0ilil : STD_LOGIC := '0'; + SIGNAL nlOi0iliO : STD_LOGIC := '0'; + SIGNAL nlOi0illi : STD_LOGIC := '0'; + SIGNAL nlOi0illl : STD_LOGIC := '0'; + SIGNAL nlOi0illO : STD_LOGIC := '0'; + SIGNAL nlOi0ilOi : STD_LOGIC := '0'; + SIGNAL nlOi0l01l : STD_LOGIC := '0'; + SIGNAL nlOi0l1li : STD_LOGIC := '0'; + SIGNAL nlOi0l1OO : STD_LOGIC := '0'; + SIGNAL nlOi0lO0O : STD_LOGIC := '0'; + SIGNAL nlOi0lOOi : STD_LOGIC := '0'; + SIGNAL nlOi0O0il : STD_LOGIC := '0'; + SIGNAL nlOi0O0OO : STD_LOGIC := '0'; + SIGNAL nlOi0O10l : STD_LOGIC := '0'; + SIGNAL nlOi0O11O : STD_LOGIC := '0'; + SIGNAL nlOi0Oi1O : STD_LOGIC := '0'; + SIGNAL nlOi0Ol1l : STD_LOGIC := '0'; + SIGNAL nlOi0OliO : STD_LOGIC := '0'; + SIGNAL nlOi0OllO : STD_LOGIC := '0'; + SIGNAL nlOi0OOli : STD_LOGIC := '0'; + SIGNAL nlOi0OOOO : STD_LOGIC := '0'; + SIGNAL nlOii001O : STD_LOGIC := '0'; + SIGNAL nlOii01il : STD_LOGIC := '0'; + SIGNAL nlOii01OO : STD_LOGIC := '0'; + SIGNAL nlOii0i1l : STD_LOGIC := '0'; + SIGNAL nlOii0iiO : STD_LOGIC := '0'; + SIGNAL nlOii0ilO : STD_LOGIC := '0'; + SIGNAL nlOii0lii : STD_LOGIC := '0'; + SIGNAL nlOii0lll : STD_LOGIC := '0'; + SIGNAL nlOii0lOO : STD_LOGIC := '0'; + SIGNAL nlOii0O0i : STD_LOGIC := '0'; + SIGNAL nlOii0Oil : STD_LOGIC := '0'; + SIGNAL nlOii0OOi : STD_LOGIC := '0'; + SIGNAL nlOii100i : STD_LOGIC := '0'; + SIGNAL nlOii10il : STD_LOGIC := '0'; + SIGNAL nlOii10lO : STD_LOGIC := '0'; + SIGNAL nlOii111l : STD_LOGIC := '0'; + SIGNAL nlOii11OO : STD_LOGIC := '0'; + SIGNAL nlOii1i0l : STD_LOGIC := '0'; + SIGNAL nlOii1ilO : STD_LOGIC := '0'; + SIGNAL nlOii1iOO : STD_LOGIC := '0'; + SIGNAL nlOii1lOl : STD_LOGIC := '0'; + SIGNAL nlOii1O0O : STD_LOGIC := '0'; + SIGNAL nlOii1OiO : STD_LOGIC := '0'; + SIGNAL nlOiii01l : STD_LOGIC := '0'; + SIGNAL nlOiii0iO : STD_LOGIC := '0'; + SIGNAL nlOiii0lO : STD_LOGIC := '0'; + SIGNAL nlOiii10O : STD_LOGIC := '0'; + SIGNAL nlOiii11l : STD_LOGIC := '0'; + SIGNAL nlOiii1li : STD_LOGIC := '0'; + SIGNAL nlOiiiiOl : STD_LOGIC := '0'; + SIGNAL nlOiil01i : STD_LOGIC := '0'; + SIGNAL nlOiil0il : STD_LOGIC := '0'; + SIGNAL nlOiil0ll : STD_LOGIC := '0'; + SIGNAL nlOiil0lO : STD_LOGIC := '0'; + SIGNAL nlOiil0Oi : STD_LOGIC := '0'; + SIGNAL nlOiil0Ol : STD_LOGIC := '0'; + SIGNAL nlOiil0OO : STD_LOGIC := '0'; + SIGNAL nlOiili1i : STD_LOGIC := '0'; + SIGNAL nlOiili1l : STD_LOGIC := '0'; + SIGNAL nlOiili1O : STD_LOGIC := '0'; + SIGNAL nlOiiO11l : STD_LOGIC := '0'; + SIGNAL nlOiiO1iO : STD_LOGIC := '0'; + SIGNAL nlOiiO1lO : STD_LOGIC := '0'; + SIGNAL nlOiiO1Oi : STD_LOGIC := '0'; + SIGNAL nlOiiO1Ol : STD_LOGIC := '0'; + SIGNAL nlOiiO1OO : STD_LOGIC := '0'; + SIGNAL nlOiiOlll : STD_LOGIC := '0'; + SIGNAL nlOiiOO0O : STD_LOGIC := '0'; + SIGNAL nlOiiOO1O : STD_LOGIC := '0'; + SIGNAL nlOiiOOii : STD_LOGIC := '0'; + SIGNAL nlOiiOOil : STD_LOGIC := '0'; + SIGNAL nlOiiOOiO : STD_LOGIC := '0'; + SIGNAL nlOiiOOli : STD_LOGIC := '0'; + SIGNAL nlOil10iO : STD_LOGIC := '0'; + SIGNAL nlOil10li : STD_LOGIC := '0'; + SIGNAL nlOil10ll : STD_LOGIC := '0'; + SIGNAL nlOil10lO : STD_LOGIC := '0'; + SIGNAL nlOil10Oi : STD_LOGIC := '0'; + SIGNAL nlOil10Ol : STD_LOGIC := '0'; + SIGNAL nlOil10OO : STD_LOGIC := '0'; + SIGNAL nlOil1i1i : STD_LOGIC := '0'; + SIGNAL nlOili01i : STD_LOGIC := '0'; + SIGNAL nlOili10O : STD_LOGIC := '0'; + SIGNAL nlOili1Oi : STD_LOGIC := '0'; + SIGNAL nlOill00l : STD_LOGIC := '0'; + SIGNAL nlOill00O : STD_LOGIC := '0'; + SIGNAL nlOill01l : STD_LOGIC := '0'; + SIGNAL nlOill01O : STD_LOGIC := '0'; + SIGNAL nlOill0ii : STD_LOGIC := '0'; + SIGNAL nlOill0il : STD_LOGIC := '0'; + SIGNAL nlOill0iO : STD_LOGIC := '0'; + SIGNAL nlOill0li : STD_LOGIC := '0'; + SIGNAL nlOill0ll : STD_LOGIC := '0'; + SIGNAL nlOill0lO : STD_LOGIC := '0'; + SIGNAL nlOill0Oi : STD_LOGIC := '0'; + SIGNAL nlOill0Ol : STD_LOGIC := '0'; + SIGNAL nlOill0OO : STD_LOGIC := '0'; + SIGNAL nlOill11l : STD_LOGIC := '0'; + SIGNAL nlOill1ii : STD_LOGIC := '0'; + SIGNAL nlOill1il : STD_LOGIC := '0'; + SIGNAL nlOill1iO : STD_LOGIC := '0'; + SIGNAL nlOill1li : STD_LOGIC := '0'; + SIGNAL nlOill1ll : STD_LOGIC := '0'; + SIGNAL nlOill1lO : STD_LOGIC := '0'; + SIGNAL nlOill1Oi : STD_LOGIC := '0'; + SIGNAL nlOill1Ol : STD_LOGIC := '0'; + SIGNAL nlOilO00l : STD_LOGIC := '0'; + SIGNAL nlOilO0lO : STD_LOGIC := '0'; + SIGNAL nlOilO0OO : STD_LOGIC := '0'; + SIGNAL nlOilOiOl : STD_LOGIC := '0'; + SIGNAL nlOilOl0O : STD_LOGIC := '0'; + SIGNAL nlOilOliO : STD_LOGIC := '0'; + SIGNAL nlOilOOil : STD_LOGIC := '0'; + SIGNAL nlOilOOOO : STD_LOGIC := '0'; + SIGNAL nlOiO011i : STD_LOGIC := '0'; + SIGNAL nlOiO100i : STD_LOGIC := '0'; + SIGNAL nlOiO100l : STD_LOGIC := '0'; + SIGNAL nlOiO100O : STD_LOGIC := '0'; + SIGNAL nlOiO101i : STD_LOGIC := '0'; + SIGNAL nlOiO101l : STD_LOGIC := '0'; + SIGNAL nlOiO101O : STD_LOGIC := '0'; + SIGNAL nlOiO10ii : STD_LOGIC := '0'; + SIGNAL nlOiO10il : STD_LOGIC := '0'; + SIGNAL nlOiO10iO : STD_LOGIC := '0'; + SIGNAL nlOiO10li : STD_LOGIC := '0'; + SIGNAL nlOiO10ll : STD_LOGIC := '0'; + SIGNAL nlOiO10lO : STD_LOGIC := '0'; + SIGNAL nlOiO10Oi : STD_LOGIC := '0'; + SIGNAL nlOiO111O : STD_LOGIC := '0'; + SIGNAL nlOiO11OO : STD_LOGIC := '0'; + SIGNAL nlOiO1lOO : STD_LOGIC := '0'; + SIGNAL nlOiOi11l : STD_LOGIC := '0'; + SIGNAL nlOiOi11O : STD_LOGIC := '0'; + SIGNAL nlOiOl00i : STD_LOGIC := '0'; + SIGNAL nlOiOl00l : STD_LOGIC := '0'; + SIGNAL nlOiOl00O : STD_LOGIC := '0'; + SIGNAL nlOiOl01i : STD_LOGIC := '0'; + SIGNAL nlOiOl01l : STD_LOGIC := '0'; + SIGNAL nlOiOl01O : STD_LOGIC := '0'; + SIGNAL nlOiOl0ii : STD_LOGIC := '0'; + SIGNAL nlOiOl0il : STD_LOGIC := '0'; + SIGNAL nlOiOl0iO : STD_LOGIC := '0'; + SIGNAL nlOiOl0li : STD_LOGIC := '0'; + SIGNAL nlOiOl0ll : STD_LOGIC := '0'; + SIGNAL nlOiOl0lO : STD_LOGIC := '0'; + SIGNAL nlOiOl0Oi : STD_LOGIC := '0'; + SIGNAL nlOiOl0Ol : STD_LOGIC := '0'; + SIGNAL nlOiOl0OO : STD_LOGIC := '0'; + SIGNAL nlOiOl1Oi : STD_LOGIC := '0'; + SIGNAL nlOiOl1Ol : STD_LOGIC := '0'; + SIGNAL nlOiOl1OO : STD_LOGIC := '0'; + SIGNAL nlOiOli0i : STD_LOGIC := '0'; + SIGNAL nlOiOli0l : STD_LOGIC := '0'; + SIGNAL nlOiOli0O : STD_LOGIC := '0'; + SIGNAL nlOiOli1i : STD_LOGIC := '0'; + SIGNAL nlOiOli1l : STD_LOGIC := '0'; + SIGNAL nlOiOli1O : STD_LOGIC := '0'; + SIGNAL nlOiOliii : STD_LOGIC := '0'; + SIGNAL nlOiOliil : STD_LOGIC := '0'; + SIGNAL nlOiOliiO : STD_LOGIC := '0'; + SIGNAL nlOiOlili : STD_LOGIC := '0'; + SIGNAL nlOiOlill : STD_LOGIC := '0'; + SIGNAL nlOiOlilO : STD_LOGIC := '0'; + SIGNAL nlOiOliOi : STD_LOGIC := '0'; + SIGNAL nlOiOliOl : STD_LOGIC := '0'; + SIGNAL nlOiOliOO : STD_LOGIC := '0'; + SIGNAL nlOiOll0i : STD_LOGIC := '0'; + SIGNAL nlOiOll0l : STD_LOGIC := '0'; + SIGNAL nlOiOll0O : STD_LOGIC := '0'; + SIGNAL nlOiOll1i : STD_LOGIC := '0'; + SIGNAL nlOiOll1l : STD_LOGIC := '0'; + SIGNAL nlOiOll1O : STD_LOGIC := '0'; + SIGNAL nlOiOllii : STD_LOGIC := '0'; + SIGNAL nlOiOllil : STD_LOGIC := '0'; + SIGNAL nlOiOlliO : STD_LOGIC := '0'; + SIGNAL nlOiOllli : STD_LOGIC := '0'; + SIGNAL nlOiOllll : STD_LOGIC := '0'; + SIGNAL nlOiOlllO : STD_LOGIC := '0'; + SIGNAL nlOiOllOi : STD_LOGIC := '0'; + SIGNAL nlOiOllOl : STD_LOGIC := '0'; + SIGNAL nlOiOllOO : STD_LOGIC := '0'; + SIGNAL nlOiOlO0i : STD_LOGIC := '0'; + SIGNAL nlOiOlO0l : STD_LOGIC := '0'; + SIGNAL nlOiOlO0O : STD_LOGIC := '0'; + SIGNAL nlOiOlO1i : STD_LOGIC := '0'; + SIGNAL nlOiOlO1l : STD_LOGIC := '0'; + SIGNAL nlOiOlO1O : STD_LOGIC := '0'; + SIGNAL nlOiOlOii : STD_LOGIC := '0'; + SIGNAL nlOiOlOil : STD_LOGIC := '0'; + SIGNAL nlOiOlOiO : STD_LOGIC := '0'; + SIGNAL nlOiOlOli : STD_LOGIC := '0'; + SIGNAL nlOiOlOll : STD_LOGIC := '0'; + SIGNAL nlOiOlOlO : STD_LOGIC := '0'; + SIGNAL nlOiOlOOi : STD_LOGIC := '0'; + SIGNAL nlOiOlOOl : STD_LOGIC := '0'; + SIGNAL nlOiOlOOO : STD_LOGIC := '0'; + SIGNAL nlOiOO10i : STD_LOGIC := '0'; + SIGNAL nlOiOO10l : STD_LOGIC := '0'; + SIGNAL nlOiOO10O : STD_LOGIC := '0'; + SIGNAL nlOiOO11i : STD_LOGIC := '0'; + SIGNAL nlOiOO11l : STD_LOGIC := '0'; + SIGNAL nlOiOO11O : STD_LOGIC := '0'; + SIGNAL nlOiOO1ii : STD_LOGIC := '0'; + SIGNAL nlOiOO1il : STD_LOGIC := '0'; + SIGNAL nlOiOO1iO : STD_LOGIC := '0'; + SIGNAL nlOiOO1li : STD_LOGIC := '0'; + SIGNAL nlOiOO1ll : STD_LOGIC := '0'; + SIGNAL nlOliiO0i : STD_LOGIC := '0'; + SIGNAL nlOliiO0l : STD_LOGIC := '0'; + SIGNAL nlOliiO0O : STD_LOGIC := '0'; + SIGNAL nlOliiOii : STD_LOGIC := '0'; + SIGNAL nlOliiOil : STD_LOGIC := '0'; + SIGNAL nlOliiOiO : STD_LOGIC := '0'; + SIGNAL nlOliiOli : STD_LOGIC := '0'; + SIGNAL nlOliiOll : STD_LOGIC := '0'; + SIGNAL nlOliiOlO : STD_LOGIC := '0'; + SIGNAL nlOliiOOi : STD_LOGIC := '0'; + SIGNAL nlOliiOOl : STD_LOGIC := '0'; + SIGNAL nlOliiOOO : STD_LOGIC := '0'; + SIGNAL nlOlil10i : STD_LOGIC := '0'; + SIGNAL nlOlil10l : STD_LOGIC := '0'; + SIGNAL nlOlil11i : STD_LOGIC := '0'; + SIGNAL nlOlil11l : STD_LOGIC := '0'; + SIGNAL nlOlil11O : STD_LOGIC := '0'; + SIGNAL nlOliO00i : STD_LOGIC := '0'; + SIGNAL nlOliO00l : STD_LOGIC := '0'; + SIGNAL nlOliO01i : STD_LOGIC := '0'; + SIGNAL nlOliO01l : STD_LOGIC := '0'; + SIGNAL nlOliO0ii : STD_LOGIC := '0'; + SIGNAL nlOliO0il : STD_LOGIC := '0'; + SIGNAL nlOliO0li : STD_LOGIC := '0'; + SIGNAL nlOliO0ll : STD_LOGIC := '0'; + SIGNAL nlOliO10i : STD_LOGIC := '0'; + SIGNAL nlOliO10l : STD_LOGIC := '0'; + SIGNAL nlOliO11i : STD_LOGIC := '0'; + SIGNAL nlOliO11l : STD_LOGIC := '0'; + SIGNAL nlOliO1ii : STD_LOGIC := '0'; + SIGNAL nlOliO1il : STD_LOGIC := '0'; + SIGNAL nlOliO1li : STD_LOGIC := '0'; + SIGNAL nlOliO1ll : STD_LOGIC := '0'; + SIGNAL nlOliO1Oi : STD_LOGIC := '0'; + SIGNAL nlOliO1Ol : STD_LOGIC := '0'; + SIGNAL nlOll000i : STD_LOGIC := '0'; + SIGNAL nlOll000l : STD_LOGIC := '0'; + SIGNAL nlOll000O : STD_LOGIC := '0'; + SIGNAL nlOll001i : STD_LOGIC := '0'; + SIGNAL nlOll001l : STD_LOGIC := '0'; + SIGNAL nlOll001O : STD_LOGIC := '0'; + SIGNAL nlOll01iO : STD_LOGIC := '0'; + SIGNAL nlOll01li : STD_LOGIC := '0'; + SIGNAL nlOll01ll : STD_LOGIC := '0'; + SIGNAL nlOll01lO : STD_LOGIC := '0'; + SIGNAL nlOll01Oi : STD_LOGIC := '0'; + SIGNAL nlOll01Ol : STD_LOGIC := '0'; + SIGNAL nlOll01OO : STD_LOGIC := '0'; + SIGNAL nlOll0O0i : STD_LOGIC := '0'; + SIGNAL nlOll0O0l : STD_LOGIC := '0'; + SIGNAL nlOll0O0O : STD_LOGIC := '0'; + SIGNAL nlOllil0l : STD_LOGIC := '0'; + SIGNAL nlOllil0O : STD_LOGIC := '0'; + SIGNAL nlOllilii : STD_LOGIC := '0'; + SIGNAL nlOllilil : STD_LOGIC := '0'; + SIGNAL nlOlliliO : STD_LOGIC := '0'; + SIGNAL nlOllilli : STD_LOGIC := '0'; + SIGNAL nlOllilll : STD_LOGIC := '0'; + SIGNAL nlOllillO : STD_LOGIC := '0'; + SIGNAL nlOllilOi : STD_LOGIC := '0'; + SIGNAL nlOllilOl : STD_LOGIC := '0'; + SIGNAL nlOllilOO : STD_LOGIC := '0'; + SIGNAL nlOlliO0i : STD_LOGIC := '0'; + SIGNAL nlOlliO0l : STD_LOGIC := '0'; + SIGNAL nlOlliO0O : STD_LOGIC := '0'; + SIGNAL nlOlliO1i : STD_LOGIC := '0'; + SIGNAL nlOlliO1l : STD_LOGIC := '0'; + SIGNAL nlOlliO1O : STD_LOGIC := '0'; + SIGNAL nlOlliOii : STD_LOGIC := '0'; + SIGNAL nlOlliOil : STD_LOGIC := '0'; + SIGNAL nlOlliOiO : STD_LOGIC := '0'; + SIGNAL nlOlliOli : STD_LOGIC := '0'; + SIGNAL nlOlliOll : STD_LOGIC := '0'; + SIGNAL nlOlliOlO : STD_LOGIC := '0'; + SIGNAL nlOlliOOi : STD_LOGIC := '0'; + SIGNAL nlOlliOOl : STD_LOGIC := '0'; + SIGNAL nlOlliOOO : STD_LOGIC := '0'; + SIGNAL nlOllll0l : STD_LOGIC := '0'; + SIGNAL nlOllll0O : STD_LOGIC := '0'; + SIGNAL nlOllllil : STD_LOGIC := '0'; + SIGNAL nlOllO0iO : STD_LOGIC := '0'; + SIGNAL nlOllOliO : STD_LOGIC := '0'; + SIGNAL nlOllOlli : STD_LOGIC := '0'; + SIGNAL nlOllOlll : STD_LOGIC := '0'; + SIGNAL nlOllOllO : STD_LOGIC := '0'; + SIGNAL nlOllOlOi : STD_LOGIC := '0'; + SIGNAL nlOllOlOl : STD_LOGIC := '0'; + SIGNAL nlOllOlOO : STD_LOGIC := '0'; + SIGNAL nlOllOO1i : STD_LOGIC := '0'; + SIGNAL nlOlO010i : STD_LOGIC := '0'; + SIGNAL nlOlO010l : STD_LOGIC := '0'; + SIGNAL nlOlO011i : STD_LOGIC := '0'; + SIGNAL nlOlO011l : STD_LOGIC := '0'; + SIGNAL nlOlO011O : STD_LOGIC := '0'; + SIGNAL nlOlO0lOO : STD_LOGIC := '0'; + SIGNAL nlOlO10ii : STD_LOGIC := '0'; + SIGNAL nlOlO10il : STD_LOGIC := '0'; + SIGNAL nlOlO10iO : STD_LOGIC := '0'; + SIGNAL nlOlO1ilO : STD_LOGIC := '0'; + SIGNAL nlOlO1iOi : STD_LOGIC := '0'; + SIGNAL nlOlO1iOl : STD_LOGIC := '0'; + SIGNAL nlOlO1iOO : STD_LOGIC := '0'; + SIGNAL nlOlO1l0i : STD_LOGIC := '0'; + SIGNAL nlOlO1l1i : STD_LOGIC := '0'; + SIGNAL nlOlO1l1l : STD_LOGIC := '0'; + SIGNAL nlOlO1l1O : STD_LOGIC := '0'; + SIGNAL nlOlO1OOO : STD_LOGIC := '0'; + SIGNAL nlOlOi00i : STD_LOGIC := '0'; + SIGNAL nlOlOi00l : STD_LOGIC := '0'; + SIGNAL nlOlOi01i : STD_LOGIC := '0'; + SIGNAL nlOlOi01l : STD_LOGIC := '0'; + SIGNAL nlOlOi01O : STD_LOGIC := '0'; + SIGNAL nlOlOi1Oi : STD_LOGIC := '0'; + SIGNAL nlOlOi1Ol : STD_LOGIC := '0'; + SIGNAL nlOlOi1OO : STD_LOGIC := '0'; + SIGNAL nlOlOil0i : STD_LOGIC := '0'; + SIGNAL nlOlOil0l : STD_LOGIC := '0'; + SIGNAL nlOlOil0O : STD_LOGIC := '0'; + SIGNAL nlOlOil1i : STD_LOGIC := '0'; + SIGNAL nlOlOil1l : STD_LOGIC := '0'; + SIGNAL nlOlOil1O : STD_LOGIC := '0'; + SIGNAL nlOlOilii : STD_LOGIC := '0'; + SIGNAL nlOlOilil : STD_LOGIC := '0'; + SIGNAL nlOlOiliO : STD_LOGIC := '0'; + SIGNAL nlOlOilli : STD_LOGIC := '0'; + SIGNAL nlOlOillO : STD_LOGIC := '0'; + SIGNAL nlOlOilOi : STD_LOGIC := '0'; + SIGNAL nlOlOilOl : STD_LOGIC := '0'; + SIGNAL nlOlOiO1i : STD_LOGIC := '0'; + SIGNAL nlOlOiO1l : STD_LOGIC := '0'; + SIGNAL nlOlOiO1O : STD_LOGIC := '0'; + SIGNAL nlOO0000i : STD_LOGIC := '0'; + SIGNAL nlOO0000l : STD_LOGIC := '0'; + SIGNAL nlOO0000O : STD_LOGIC := '0'; + SIGNAL nlOO0001i : STD_LOGIC := '0'; + SIGNAL nlOO0001l : STD_LOGIC := '0'; + SIGNAL nlOO0001O : STD_LOGIC := '0'; + SIGNAL nlOO000ii : STD_LOGIC := '0'; + SIGNAL nlOO000il : STD_LOGIC := '0'; + SIGNAL nlOO000iO : STD_LOGIC := '0'; + SIGNAL nlOO000li : STD_LOGIC := '0'; + SIGNAL nlOO000ll : STD_LOGIC := '0'; + SIGNAL nlOO000lO : STD_LOGIC := '0'; + SIGNAL nlOO000Oi : STD_LOGIC := '0'; + SIGNAL nlOO000Ol : STD_LOGIC := '0'; + SIGNAL nlOO000OO : STD_LOGIC := '0'; + SIGNAL nlOO0010i : STD_LOGIC := '0'; + SIGNAL nlOO0010l : STD_LOGIC := '0'; + SIGNAL nlOO0010O : STD_LOGIC := '0'; + SIGNAL nlOO0011i : STD_LOGIC := '0'; + SIGNAL nlOO0011l : STD_LOGIC := '0'; + SIGNAL nlOO0011O : STD_LOGIC := '0'; + SIGNAL nlOO001ii : STD_LOGIC := '0'; + SIGNAL nlOO001il : STD_LOGIC := '0'; + SIGNAL nlOO001iO : STD_LOGIC := '0'; + SIGNAL nlOO001li : STD_LOGIC := '0'; + SIGNAL nlOO001ll : STD_LOGIC := '0'; + SIGNAL nlOO001lO : STD_LOGIC := '0'; + SIGNAL nlOO001Oi : STD_LOGIC := '0'; + SIGNAL nlOO001Ol : STD_LOGIC := '0'; + SIGNAL nlOO001OO : STD_LOGIC := '0'; + SIGNAL nlOO00i0i : STD_LOGIC := '0'; + SIGNAL nlOO00i0l : STD_LOGIC := '0'; + SIGNAL nlOO00i0O : STD_LOGIC := '0'; + SIGNAL nlOO00i1i : STD_LOGIC := '0'; + SIGNAL nlOO00i1l : STD_LOGIC := '0'; + SIGNAL nlOO00i1O : STD_LOGIC := '0'; + SIGNAL nlOO00iii : STD_LOGIC := '0'; + SIGNAL nlOO00iil : STD_LOGIC := '0'; + SIGNAL nlOO00iiO : STD_LOGIC := '0'; + SIGNAL nlOO00ili : STD_LOGIC := '0'; + SIGNAL nlOO00ill : STD_LOGIC := '0'; + SIGNAL nlOO00ilO : STD_LOGIC := '0'; + SIGNAL nlOO00iOi : STD_LOGIC := '0'; + SIGNAL nlOO00iOl : STD_LOGIC := '0'; + SIGNAL nlOO00iOO : STD_LOGIC := '0'; + SIGNAL nlOO00l0i : STD_LOGIC := '0'; + SIGNAL nlOO00l0l : STD_LOGIC := '0'; + SIGNAL nlOO00l0O : STD_LOGIC := '0'; + SIGNAL nlOO00l1i : STD_LOGIC := '0'; + SIGNAL nlOO00l1l : STD_LOGIC := '0'; + SIGNAL nlOO00l1O : STD_LOGIC := '0'; + SIGNAL nlOO00lii : STD_LOGIC := '0'; + SIGNAL nlOO00lil : STD_LOGIC := '0'; + SIGNAL nlOO00liO : STD_LOGIC := '0'; + SIGNAL nlOO00lli : STD_LOGIC := '0'; + SIGNAL nlOO00lll : STD_LOGIC := '0'; + SIGNAL nlOO00llO : STD_LOGIC := '0'; + SIGNAL nlOO00lOi : STD_LOGIC := '0'; + SIGNAL nlOO00lOl : STD_LOGIC := '0'; + SIGNAL nlOO00lOO : STD_LOGIC := '0'; + SIGNAL nlOO00O0i : STD_LOGIC := '0'; + SIGNAL nlOO00O0l : STD_LOGIC := '0'; + SIGNAL nlOO00O0O : STD_LOGIC := '0'; + SIGNAL nlOO00O1i : STD_LOGIC := '0'; + SIGNAL nlOO00O1l : STD_LOGIC := '0'; + SIGNAL nlOO00O1O : STD_LOGIC := '0'; + SIGNAL nlOO00Oii : STD_LOGIC := '0'; + SIGNAL nlOO00Oil : STD_LOGIC := '0'; + SIGNAL nlOO00OiO : STD_LOGIC := '0'; + SIGNAL nlOO00Oli : STD_LOGIC := '0'; + SIGNAL nlOO00Oll : STD_LOGIC := '0'; + SIGNAL nlOO00OlO : STD_LOGIC := '0'; + SIGNAL nlOO00OOi : STD_LOGIC := '0'; + SIGNAL nlOO00OOl : STD_LOGIC := '0'; + SIGNAL nlOO00OOO : STD_LOGIC := '0'; + SIGNAL nlOO0100l : STD_LOGIC := '0'; + SIGNAL nlOO0100O : STD_LOGIC := '0'; + SIGNAL nlOO010ii : STD_LOGIC := '0'; + SIGNAL nlOO010il : STD_LOGIC := '0'; + SIGNAL nlOO010iO : STD_LOGIC := '0'; + SIGNAL nlOO010li : STD_LOGIC := '0'; + SIGNAL nlOO010ll : STD_LOGIC := '0'; + SIGNAL nlOO010lO : STD_LOGIC := '0'; + SIGNAL nlOO010Oi : STD_LOGIC := '0'; + SIGNAL nlOO010Ol : STD_LOGIC := '0'; + SIGNAL nlOO010OO : STD_LOGIC := '0'; + SIGNAL nlOO01i0i : STD_LOGIC := '0'; + SIGNAL nlOO01i0l : STD_LOGIC := '0'; + SIGNAL nlOO01i0O : STD_LOGIC := '0'; + SIGNAL nlOO01i1i : STD_LOGIC := '0'; + SIGNAL nlOO01i1l : STD_LOGIC := '0'; + SIGNAL nlOO01i1O : STD_LOGIC := '0'; + SIGNAL nlOO01iii : STD_LOGIC := '0'; + SIGNAL nlOO01iil : STD_LOGIC := '0'; + SIGNAL nlOO01iiO : STD_LOGIC := '0'; + SIGNAL nlOO01ili : STD_LOGIC := '0'; + SIGNAL nlOO01ill : STD_LOGIC := '0'; + SIGNAL nlOO01ilO : STD_LOGIC := '0'; + SIGNAL nlOO01iOi : STD_LOGIC := '0'; + SIGNAL nlOO01iOl : STD_LOGIC := '0'; + SIGNAL nlOO01iOO : STD_LOGIC := '0'; + SIGNAL nlOO01l0i : STD_LOGIC := '0'; + SIGNAL nlOO01l0l : STD_LOGIC := '0'; + SIGNAL nlOO01l0O : STD_LOGIC := '0'; + SIGNAL nlOO01l1i : STD_LOGIC := '0'; + SIGNAL nlOO01l1l : STD_LOGIC := '0'; + SIGNAL nlOO01l1O : STD_LOGIC := '0'; + SIGNAL nlOO01lii : STD_LOGIC := '0'; + SIGNAL nlOO01lil : STD_LOGIC := '0'; + SIGNAL nlOO01liO : STD_LOGIC := '0'; + SIGNAL nlOO01lli : STD_LOGIC := '0'; + SIGNAL nlOO01lll : STD_LOGIC := '0'; + SIGNAL nlOO01llO : STD_LOGIC := '0'; + SIGNAL nlOO01lOi : STD_LOGIC := '0'; + SIGNAL nlOO01lOl : STD_LOGIC := '0'; + SIGNAL nlOO01lOO : STD_LOGIC := '0'; + SIGNAL nlOO01O0i : STD_LOGIC := '0'; + SIGNAL nlOO01O0l : STD_LOGIC := '0'; + SIGNAL nlOO01O0O : STD_LOGIC := '0'; + SIGNAL nlOO01O1i : STD_LOGIC := '0'; + SIGNAL nlOO01O1l : STD_LOGIC := '0'; + SIGNAL nlOO01O1O : STD_LOGIC := '0'; + SIGNAL nlOO01Oii : STD_LOGIC := '0'; + SIGNAL nlOO01Oil : STD_LOGIC := '0'; + SIGNAL nlOO01OiO : STD_LOGIC := '0'; + SIGNAL nlOO01Oli : STD_LOGIC := '0'; + SIGNAL nlOO01Oll : STD_LOGIC := '0'; + SIGNAL nlOO01OlO : STD_LOGIC := '0'; + SIGNAL nlOO01OOi : STD_LOGIC := '0'; + SIGNAL nlOO01OOl : STD_LOGIC := '0'; + SIGNAL nlOO01OOO : STD_LOGIC := '0'; + SIGNAL nlOO0i00i : STD_LOGIC := '0'; + SIGNAL nlOO0i00l : STD_LOGIC := '0'; + SIGNAL nlOO0i00O : STD_LOGIC := '0'; + SIGNAL nlOO0i01i : STD_LOGIC := '0'; + SIGNAL nlOO0i01l : STD_LOGIC := '0'; + SIGNAL nlOO0i01O : STD_LOGIC := '0'; + SIGNAL nlOO0i0ii : STD_LOGIC := '0'; + SIGNAL nlOO0i0il : STD_LOGIC := '0'; + SIGNAL nlOO0i0iO : STD_LOGIC := '0'; + SIGNAL nlOO0i0li : STD_LOGIC := '0'; + SIGNAL nlOO0i0ll : STD_LOGIC := '0'; + SIGNAL nlOO0i0lO : STD_LOGIC := '0'; + SIGNAL nlOO0i0Oi : STD_LOGIC := '0'; + SIGNAL nlOO0i0Ol : STD_LOGIC := '0'; + SIGNAL nlOO0i0OO : STD_LOGIC := '0'; + SIGNAL nlOO0i10i : STD_LOGIC := '0'; + SIGNAL nlOO0i10l : STD_LOGIC := '0'; + SIGNAL nlOO0i10O : STD_LOGIC := '0'; + SIGNAL nlOO0i11i : STD_LOGIC := '0'; + SIGNAL nlOO0i11l : STD_LOGIC := '0'; + SIGNAL nlOO0i11O : STD_LOGIC := '0'; + SIGNAL nlOO0i1ii : STD_LOGIC := '0'; + SIGNAL nlOO0i1il : STD_LOGIC := '0'; + SIGNAL nlOO0i1iO : STD_LOGIC := '0'; + SIGNAL nlOO0i1li : STD_LOGIC := '0'; + SIGNAL nlOO0i1ll : STD_LOGIC := '0'; + SIGNAL nlOO0i1lO : STD_LOGIC := '0'; + SIGNAL nlOO0i1Oi : STD_LOGIC := '0'; + SIGNAL nlOO0i1Ol : STD_LOGIC := '0'; + SIGNAL nlOO0i1OO : STD_LOGIC := '0'; + SIGNAL nlOO0ii0i : STD_LOGIC := '0'; + SIGNAL nlOO0ii0l : STD_LOGIC := '0'; + SIGNAL nlOO0ii0O : STD_LOGIC := '0'; + SIGNAL nlOO0ii1i : STD_LOGIC := '0'; + SIGNAL nlOO0ii1l : STD_LOGIC := '0'; + SIGNAL nlOO0ii1O : STD_LOGIC := '0'; + SIGNAL nlOO0iiii : STD_LOGIC := '0'; + SIGNAL nlOO0iiil : STD_LOGIC := '0'; + SIGNAL nlOO0iiiO : STD_LOGIC := '0'; + SIGNAL nlOO0iili : STD_LOGIC := '0'; + SIGNAL nlOO0iill : STD_LOGIC := '0'; + SIGNAL nlOO0iilO : STD_LOGIC := '0'; + SIGNAL nlOO0iiOi : STD_LOGIC := '0'; + SIGNAL nlOO0iiOl : STD_LOGIC := '0'; + SIGNAL nlOO0iiOO : STD_LOGIC := '0'; + SIGNAL nlOO0il0i : STD_LOGIC := '0'; + SIGNAL nlOO0il0l : STD_LOGIC := '0'; + SIGNAL nlOO0il0O : STD_LOGIC := '0'; + SIGNAL nlOO0il1i : STD_LOGIC := '0'; + SIGNAL nlOO0il1l : STD_LOGIC := '0'; + SIGNAL nlOO0il1O : STD_LOGIC := '0'; + SIGNAL nlOO0ilii : STD_LOGIC := '0'; + SIGNAL nlOO0ilil : STD_LOGIC := '0'; + SIGNAL nlOO0iliO : STD_LOGIC := '0'; + SIGNAL nlOO0illi : STD_LOGIC := '0'; + SIGNAL nlOO0illl : STD_LOGIC := '0'; + SIGNAL nlOO0illO : STD_LOGIC := '0'; + SIGNAL nlOO0ilOi : STD_LOGIC := '0'; + SIGNAL nlOO10Oli : STD_LOGIC := '0'; + SIGNAL nlOO1i10O : STD_LOGIC := '0'; + SIGNAL nlOO1i1ii : STD_LOGIC := '0'; + SIGNAL nlOO1i1il : STD_LOGIC := '0'; + SIGNAL nlOO1i1iO : STD_LOGIC := '0'; + SIGNAL nlOO1i1li : STD_LOGIC := '0'; + SIGNAL nlOO1i1ll : STD_LOGIC := '0'; + SIGNAL nlOO1i1lO : STD_LOGIC := '0'; + SIGNAL nlOO1i1Oi : STD_LOGIC := '0'; + SIGNAL nlOO1O10O : STD_LOGIC := '0'; + SIGNAL nlOO1O1ii : STD_LOGIC := '0'; + SIGNAL nlOO1O1il : STD_LOGIC := '0'; + SIGNAL nlOO1O1iO : STD_LOGIC := '0'; + SIGNAL nlOO1O1li : STD_LOGIC := '0'; + SIGNAL nlOO1O1ll : STD_LOGIC := '0'; + SIGNAL nlOO1O1lO : STD_LOGIC := '0'; + SIGNAL nlOO1O1Oi : STD_LOGIC := '0'; + SIGNAL nlOO1O1Ol : STD_LOGIC := '0'; + SIGNAL nlOO1O1OO : STD_LOGIC := '0'; + SIGNAL nlOOO0OlO : STD_LOGIC := '0'; + SIGNAL nlOOO0OOi : STD_LOGIC := '0'; + SIGNAL nlOOO0OOl : STD_LOGIC := '0'; + SIGNAL nlOOO0OOO : STD_LOGIC := '0'; + SIGNAL nlOOOi00i : STD_LOGIC := '0'; + SIGNAL nlOOOi00l : STD_LOGIC := '0'; + SIGNAL nlOOOi00O : STD_LOGIC := '0'; + SIGNAL nlOOOi01i : STD_LOGIC := '0'; + SIGNAL nlOOOi01l : STD_LOGIC := '0'; + SIGNAL nlOOOi01O : STD_LOGIC := '0'; + SIGNAL nlOOOi0ii : STD_LOGIC := '0'; + SIGNAL nlOOOi0il : STD_LOGIC := '0'; + SIGNAL nlOOOi0iO : STD_LOGIC := '0'; + SIGNAL nlOOOi0li : STD_LOGIC := '0'; + SIGNAL nlOOOi0ll : STD_LOGIC := '0'; + SIGNAL nlOOOi0lO : STD_LOGIC := '0'; + SIGNAL nlOOOi0Oi : STD_LOGIC := '0'; + SIGNAL nlOOOi0Ol : STD_LOGIC := '0'; + SIGNAL nlOOOi0OO : STD_LOGIC := '0'; + SIGNAL nlOOOi10i : STD_LOGIC := '0'; + SIGNAL nlOOOi10l : STD_LOGIC := '0'; + SIGNAL nlOOOi10O : STD_LOGIC := '0'; + SIGNAL nlOOOi11i : STD_LOGIC := '0'; + SIGNAL nlOOOi11l : STD_LOGIC := '0'; + SIGNAL nlOOOi11O : STD_LOGIC := '0'; + SIGNAL nlOOOi1ii : STD_LOGIC := '0'; + SIGNAL nlOOOi1il : STD_LOGIC := '0'; + SIGNAL nlOOOi1iO : STD_LOGIC := '0'; + SIGNAL nlOOOi1li : STD_LOGIC := '0'; + SIGNAL nlOOOi1ll : STD_LOGIC := '0'; + SIGNAL nlOOOi1lO : STD_LOGIC := '0'; + SIGNAL nlOOOi1Oi : STD_LOGIC := '0'; + SIGNAL nlOOOi1Ol : STD_LOGIC := '0'; + SIGNAL nlOOOi1OO : STD_LOGIC := '0'; + SIGNAL nlOOOii0i : STD_LOGIC := '0'; + SIGNAL nlOOOii0l : STD_LOGIC := '0'; + SIGNAL nlOOOii0O : STD_LOGIC := '0'; + SIGNAL nlOOOii1i : STD_LOGIC := '0'; + SIGNAL nlOOOii1l : STD_LOGIC := '0'; + SIGNAL nlOOOii1O : STD_LOGIC := '0'; + SIGNAL nlOOOiiii : STD_LOGIC := '0'; + SIGNAL nlOOOiiil : STD_LOGIC := '0'; + SIGNAL nlOOOiiiO : STD_LOGIC := '0'; + SIGNAL nlOOOiili : STD_LOGIC := '0'; + SIGNAL nlOOOiill : STD_LOGIC := '0'; + SIGNAL nlOOOiilO : STD_LOGIC := '0'; + SIGNAL nlOOOiiOi : STD_LOGIC := '0'; + SIGNAL nlOOOiiOl : STD_LOGIC := '0'; + SIGNAL nlOOOiiOO : STD_LOGIC := '0'; + SIGNAL nlOOOil0i : STD_LOGIC := '0'; + SIGNAL nlOOOil0l : STD_LOGIC := '0'; + SIGNAL nlOOOil0O : STD_LOGIC := '0'; + SIGNAL nlOOOil1i : STD_LOGIC := '0'; + SIGNAL nlOOOil1l : STD_LOGIC := '0'; + SIGNAL nlOOOil1O : STD_LOGIC := '0'; + SIGNAL nlOOOilii : STD_LOGIC := '0'; + SIGNAL nlOOOilil : STD_LOGIC := '0'; + SIGNAL nlOOOiliO : STD_LOGIC := '0'; + SIGNAL nlOOOilli : STD_LOGIC := '0'; + SIGNAL nlOOOilll : STD_LOGIC := '0'; + SIGNAL nlOOOillO : STD_LOGIC := '0'; + SIGNAL nlOOOilOi : STD_LOGIC := '0'; + SIGNAL nlOOOilOl : STD_LOGIC := '0'; + SIGNAL nlOOOilOO : STD_LOGIC := '0'; + SIGNAL nlOOOiO0i : STD_LOGIC := '0'; + SIGNAL nlOOOiO0l : STD_LOGIC := '0'; + SIGNAL nlOOOiO0O : STD_LOGIC := '0'; + SIGNAL nlOOOiO1i : STD_LOGIC := '0'; + SIGNAL nlOOOiO1l : STD_LOGIC := '0'; + SIGNAL nlOOOiO1O : STD_LOGIC := '0'; + SIGNAL nlOOOiOii : STD_LOGIC := '0'; + SIGNAL nlOOOiOil : STD_LOGIC := '0'; + SIGNAL nlOOOiOiO : STD_LOGIC := '0'; + SIGNAL nlOOOiOli : STD_LOGIC := '0'; + SIGNAL nlOOOiOll : STD_LOGIC := '0'; + SIGNAL nlOOOiOlO : STD_LOGIC := '0'; + SIGNAL nlOOOiOOi : STD_LOGIC := '0'; + SIGNAL nlOOOiOOl : STD_LOGIC := '0'; + SIGNAL nlOOOiOOO : STD_LOGIC := '0'; + SIGNAL nlOOOl00i : STD_LOGIC := '0'; + SIGNAL nlOOOl01i : STD_LOGIC := '0'; + SIGNAL nlOOOl01l : STD_LOGIC := '0'; + SIGNAL nlOOOl01O : STD_LOGIC := '0'; + SIGNAL nlOOOl10i : STD_LOGIC := '0'; + SIGNAL nlOOOl10l : STD_LOGIC := '0'; + SIGNAL nlOOOl10O : STD_LOGIC := '0'; + SIGNAL nlOOOl11i : STD_LOGIC := '0'; + SIGNAL nlOOOl11l : STD_LOGIC := '0'; + SIGNAL nlOOOl11O : STD_LOGIC := '0'; + SIGNAL nlOOOl1ii : STD_LOGIC := '0'; + SIGNAL nlOOOl1il : STD_LOGIC := '0'; + SIGNAL nlOOOl1iO : STD_LOGIC := '0'; + SIGNAL nlOOOl1li : STD_LOGIC := '0'; + SIGNAL nlOOOl1ll : STD_LOGIC := '0'; + SIGNAL nlOOOl1lO : STD_LOGIC := '0'; + SIGNAL nlOOOl1Oi : STD_LOGIC := '0'; + SIGNAL nlOOOl1Ol : STD_LOGIC := '0'; + SIGNAL nlOOOl1OO : STD_LOGIC := '0'; + SIGNAL wire_niO01ill_w_lg_w25198w25199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w25198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_w25193w25195w25196w25197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w25193w25195w25196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w25193w25195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w25193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_w25186w25188w25189w25191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_w19876w19877w19879w19880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w26895w26896w26908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w19898w19899w19900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w19887w19888w19889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10651w10652w10653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w16942w16943w16944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w16035w16036w16037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w17849w17850w17851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w15128w15129w15130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w14221w14222w14223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w13314w13315w13316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w12407w12408w12409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w19844w23519w23520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w25186w25188w25189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w19876w19877w19879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w18756w18757w18758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10502w10503w10504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10517w10518w10519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10525w10526w10527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10602w10603w10604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10617w10618w10619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10625w10626w10627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10552w10553w10554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10567w10568w10569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10575w10576w10577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10452w10453w10454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10467w10468w10469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10475w10476w10477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10402w10403w10404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10417w10418w10419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10425w10426w10427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10352w10353w10354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10367w10368w10369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10375w10376w10377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10302w10303w10304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10317w10318w10319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10325w10326w10327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10252w10253w10254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10267w10268w10269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w10275w10276w10277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w16931w16932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w16024w16025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w17838w17839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w15117w15118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w14210w14211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w13303w13304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w12396w12397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w26895w26896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w19898w19899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w19887w19888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w18745w18746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10651w10652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10640w10641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10491w10492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10511w10512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10591w10592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10611w10612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10541w10542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10561w10562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10441w10442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10461w10462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10391w10392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10411w10412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10341w10342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10361w10362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10291w10292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10311w10312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10241w10242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10261w10262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w15590w15593w15594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w17404w17407w17408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w16497w16500w16501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w14683w14686w14687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w13776w13779w13780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w12869w12872w12873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w11958w11961w11962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w18311w18314w18315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w16942w16943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w16035w16036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w17849w17850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w15128w15129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w14221w14222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w13314w13315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w12407w12408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w19844w23519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w25186w25188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w19876w19877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w18756w18757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10502w10503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10517w10518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10525w10526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10602w10603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10617w10618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10625w10626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10552w10553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10567w10568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10575w10576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10452w10453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10467w10468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10475w10476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10402w10403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10417w10418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10425w10426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10352w10353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10367w10368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10375w10376w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10302w10303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10317w10318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10325w10326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10252w10253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10267w10268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w10275w10276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w16931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w16024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w17838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w15117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w14210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w13303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w12396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w26895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w20897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w19898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w19887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w18745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w28257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w15590w15593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w17404w17407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w16497w16500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w14683w14686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w13776w13779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w12869w12872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w11958w11961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w18311w18314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w16942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w16238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w15331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w16035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w17145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w17849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w14424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w15128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w13517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w14221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w12610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w13314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w11699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w12407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w19844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w19926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w25186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w19876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w18052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w18756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w10275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n000i00i16928w16929w16930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00OOOil16021w16022w16023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01iOiOO17835w17836w17837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0iliilO15114w15115w15116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0li101i14207w14208w14209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0O1iO0l13300w13301w13302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0OO1iiO12393w12394w12395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1101liO26878w26879w26880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1iO0l0O20892w20893w20896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19894w19895w19897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19884w19885w19886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1OO0Oll18742w18743w18744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_ni11100O10647w10648w10650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_ni11100O10637w10638w10639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10488w10489w10490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10508w10509w10510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10588w10589w10590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10608w10609w10610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10538w10539w10540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10558w10559w10560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10438w10439w10440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10458w10459w10460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10388w10389w10390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10408w10409w10410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10338w10339w10340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10358w10359w10360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10288w10289w10290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10308w10309w10310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10238w10239w10240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10258w10259w10260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_nlOiO10ii28254w28255w28256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w15590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w17404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w16497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w14683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w13776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w12869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w11958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w18311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n000i00i16938w16939w16941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n001ilil16227w16229w16231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n001iliO16235w16236w16237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n001iliO16235w16653w16657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n001iO0l16165w16167w16168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00ilOOO21080w21082w21083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00O10lO15320w15322w15324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00O10Oi15328w15329w15330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00O10Oi15328w15746w15750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00O1iiO15258w15260w15261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00OOOil16031w16032w16034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n011llii21068w21070w21071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01i101i17072w17074w17075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01i110i17134w17136w17138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01i110l17142w17143w17144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01i110l17142w17560w17564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01iOiOO17845w17846w17848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01O00ll21074w21076w21077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0i00l0i21086w21088w21089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0iil11i14413w14415w14417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0iil11l14421w14422w14423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0iil11l14421w14839w14843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0iil1Oi14351w14353w14354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0iliilO15124w15125w15127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0iOO0il21092w21094w21095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0l13506w13508w13510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0O13514w13515w13516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0O13514w13932w13936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0l01O1l13444w13446w13447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0li101i14217w14218w14220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0ll0OlO21098w21100w21101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0iO12599w12601w12603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0li12607w12608w12609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0li12607w13025w13029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0lOli0O12537w12539w12540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0O0Ol1i21104w21106w21107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0O1iO0l13310w13311w13313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0Ol01li11625w11627w11628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOi11688w11690w11692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOl11696w11697w11698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOl11696w12117w12121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0OO1iiO12403w12404w12406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19850w19921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19841w19842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1iOl0Oi25180w25182w25184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19872w19873w19875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1lill0O19911w19913w19914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1Oi011O21063w21065w21066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1Oli0OO18041w18043w18045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1Olii1i18049w18050w18051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1Olii1i18049w18467w18471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1OliilO17979w17981w17982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1OO0Oll18752w18753w18755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10499w10501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10499w10516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10523w10524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10599w10601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10599w10616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10623w10624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10549w10551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10549w10566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10573w10574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10449w10451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10449w10466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10473w10474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10399w10401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10399w10416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10423w10424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10349w10351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10349w10366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10373w10374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10299w10301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10299w10316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10323w10324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10249w10251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10249w10266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10273w10274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_nlOO1O1Ol24778w24780w24781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n000i00i16928w16929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00OOOil16021w16022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01iOiOO17835w17836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0iliilO15114w15115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0li101i14207w14208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0O1iO0l13300w13301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0OO1iiO12393w12394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101liO26878w26879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11i111O19846w19924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11i111O19857w19858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1iO0l0O20892w20893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l001OO19894w19895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l001OO19884w19885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l00i1O19905w19906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l00i1O19783w19928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lill0O19918w19919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1OO0Oll18742w18743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni11100O10647w10648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni11100O10637w10638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii0iO10488w10489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii0iO10508w10509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii10O10588w10589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii10O10608w10609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii1OO10538w10539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii1OO10558w10559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiii1O10438w10439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiii1O10458w10459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiilO10388w10389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiilO10408w10409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiil0O10338w10339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiil0O10358w10359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiilOO10288w10289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiilOO10308w10309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOiO10238w10239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOiO10258w10259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOiO10ii28254w28255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n00l0lOl15587w15588w15589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0100i0O17401w17402w17403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n01OO1li16494w16495w16496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0i0Oi1O14680w14681w14682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0l1i1ii13773w13774w13775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0llOlll12866w12867w12868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n0Oii0OO11955w11956w11957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n1OilO1l18308w18309w18310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n000i00i16938w16939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n001ilil16227w16229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n001iliO16235w16236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n001iliO16235w16653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n001iO0l16165w16167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00ilOOO21080w21082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00O10lO15320w15322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00O1iiO15258w15260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00OOOil16031w16032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n011llii21068w21070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01i101i17072w17074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01i110i17134w17136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01i110l17142w17143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01i110l17142w17560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01iOiOO17845w17846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01O00ll21074w21076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0i00l0i21086w21088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0iil11i14413w14415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0iil11l14421w14422w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0iil11l14421w14839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0iil1Oi14351w14353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0iliilO15124w15125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0iOO0il21092w21094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0l01l0l13506w13508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0l01O1l13444w13446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0li101i14217w14218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0ll0OlO21098w21100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0lOl0iO12599w12601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0lOl0li12607w12608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0lOl0li12607w13025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0lOli0O12537w12539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0O0Ol1i21104w21106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0O1iO0l13310w13311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0Ol01li11625w11627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0Ol1OOi11688w11690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w11697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w12117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0OO1iiO12403w12404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l0i16090w26029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l0i16090w27837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l0l15183w26033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l0l15183w27841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l0O14276w26037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l0O14276w27845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l1l17904w26022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l1l17904w27830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l1O16997w26025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101l1O16997w27833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101lii13369w26041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101lii13369w27849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101lil12462w26045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101lil12462w27853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101liO11541w26049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1101liO11541w27857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11i111O19840w19850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11i111O19840w19841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11li10l21153w23483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11li10O21143w21144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0iOi21061w21062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0lii19984w19985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0llO24108w24114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11Oi1ll23889w23890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1iOl0Oi25180w25182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l0010O11542w11544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l0011O19569w19570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1l001OO19872w19873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lill0O19911w19913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1Oi011O21063w21065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1Oli0OO18041w18043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1OliilO17979w17981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1OO0Oll18752w18753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni00ll1i10876w10912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni01lOiO10957w10993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni0i0i0l10658w10659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni101i0i11362w11398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni111llO11443w11479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni1i11ll11281w11317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni1iOO1O11200w11236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni1lOili11119w11155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_ni1OO01l11038w11074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii0iO10498w10499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii0iO10498w10523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii10O10598w10599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii10O10598w10623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii1OO10548w10549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiii1OO10548w10573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiii1O10448w10449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiii1O10448w10473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiilO10398w10399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiilO10398w10423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiil0O10348w10349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiil0O10348w10373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiilOO10298w10299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiilOO10298w10323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOiO10248w10249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOiO10248w10273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niOO0O0OO19990w19991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOlOiliO21217w23459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOO0iilO20976w20977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOO1O1Ol24778w24780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i00i16928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0010ilO16620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001ilil16666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001iliO16660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00lO01i15713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O10lO15759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O10Oi15753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOOil16021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n010lOil17527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i110i17573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i110l17567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOiOO17835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ii0O0l14806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iil11i14852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iil11l14846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iliilO15114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01l0l13945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01l0O13939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l1OiiO13899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li101i14207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOi1Oi12992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOl0iO13038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOl0li13032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1iO0l13300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OiOO1l12081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol1OOi12130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol1OOl12124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO1iiO12393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l0i21078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l0l21084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l0O21090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l1l21067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l1O21072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101lii21096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101lil21102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101liO21108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101liO26878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1110Oii21207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1110OOO24680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11i111O19846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11i111O19857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li10i21129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li1il21048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0l1O23854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0llO23840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1O1O20986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il11ll21199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0l0O20892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl10i25220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l000Oi19865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001OO19894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001OO19884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l00i1O19905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l00i1O19783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OlOi18938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lill0O19918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lilO0l19585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Ol000i18434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oli0OO18480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Olii1i18474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0Oll18742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni00ll1i10915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni01lOiO10996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i0i0l10812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni101i0i11401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni11100O10647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni11100O10637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni111llO11482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1i11ll11320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1iOO1O11239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1lOili11158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1OO01l11077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0iO10488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0iO10508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii10O10588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii10O10608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1OO10538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1OO10558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiii1O10438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiii1O10458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiilO10388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiilO10408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiil0O10338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiil0O10358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiilOO10288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiilOO10308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOiO10238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOiO10258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0O0OO43259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Oi1l20951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiO10ii28254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO00i25139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO01i25119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO0ii25129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO10i25079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO11i25069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1ii25089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1li25099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1Oi25109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll0O0O24678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOilOl21225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOi10i24752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOi10i24679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl01i25090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl01l25080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl01O25070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1ll25130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1lO25140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1Oi25120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1Ol25110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1OO25100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00l0lOl15587w15588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n00l0Oil15591w15592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0100i0O17401w17402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0100iOO17405w17406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01OO00i16498w16499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n01OO1li16494w16495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0i0Oi1O14680w14681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0i0OilO14684w14685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0l1i01i13777w13778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0l1i1ii13773w13774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0llOlll12866w12867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0llOO0l12870w12871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0Oii0OO11955w11956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n0OiiiiO11959w11960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1OilO1l18308w18309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1OilOll18312w18313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO00i25133w25134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO00l25136w25137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO01i25113w25114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO01l25116w25117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO0ii25123w25124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO0il25126w25127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO10i25073w25074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO10l25076w25077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO11i25063w25064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO11l25066w25067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO1ii25083w25084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO1il25086w25087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO1li25093w25094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO1ll25096w25097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO1Oi25103w25104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOliO1Ol25106w25107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i00i16938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i01l16940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i01O16927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i10l16631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i10O16096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i1ii16175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i1il16104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i1lO16935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n000i1Oi16933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00100iO16371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0010iOl16382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0010iOO16387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001il0O16230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001ilii16228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001ilil16227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001iliO16235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001ilOi16166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001ilOO16173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n001iO0l16165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iiiOi15387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iilii15716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iilil15947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iiliO15946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00il1li26362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00ill1O27781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00illOi25306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00illOl27932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00ilOOl21081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00ilOOO21080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iO10i27391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iO10l27389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iO11i27700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iO11l27698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iO11O27696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00iO1OO26068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00l0i0l15572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00llOOi15464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00lO00i15480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00lO01O15475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O10li15323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O10ll15321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O10lO15320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O10Oi15328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O1i0i15266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O1i1l15259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00O1iiO15258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOliO15724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOlli15189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOlll15268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOllO15197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOO0O16033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOO1i16028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOO1l16026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOOii16020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00OOOil16031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01001lO17386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n010ll0l17278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n010lOli17289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n010lOll17294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011i00l17201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011i0Ol17530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011i0OO17761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011ii1i17760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011iO1l26358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011l0li27777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011li0l25302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011li0O27928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011ll0O21069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011llii21068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011llil27693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011lliO27691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011llli27689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011llll27347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011lllO27345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n011lOii26058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i101i17072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i110i17134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i110l17142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i111l17137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i111O17135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i11iO17073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01i11ll17080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOi0i17011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOi1i17538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOi1l17003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOi1O17082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOiil17842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOiiO17840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOiOi17847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOiOl17834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01iOiOO17845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01lOOiO16294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O00li21075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O00ll21074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O00OO27369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O01iO25304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O01li27930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O0i1i27367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O0ill26063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O110i16854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O110l16853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O111O16623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O1i0O26360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01O1OOl27779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01OlO1i16479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i000ii27783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i00i1l25308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i00i1O27934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i00l0i21086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i00l1O21087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i00lil27413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i00liO27411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i00O0i26073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i0101l14480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i010ll14809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i010lO15040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i010Oi15039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i01lOl26364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i0O1iO14665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ii0l1l14557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ii0Oii14568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ii0Oil14573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iiiOOl14416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iiiOOO14414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iil10O14352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iil11i14413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iil11l14421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iil1il14359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iil1Oi14351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ili0Oi14817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ili0Ol14282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ili0OO14361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ilii0l15121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ilii0O15119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ilii1i14290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iliili15126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iliill15113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iliilO15124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOiO0O13573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOiOOO13902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOl11i14133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOl11l14132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOli1O26366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOlOll27785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOO0ii21093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOO0il21092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOO0lO27436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOO0Oi27434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOO10O25310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOO1ii27936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0iOOiil26078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01l0i13507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01l0l13506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01l0O13514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01l1O13509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01lli13445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01llO13452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l01O1l13444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l10lOi13758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l1O00O13650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l1Oill13661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l1OilO13666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li101i14217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li110i13454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li110l13383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li111l13910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li111O13375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li11iO14214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li11li14212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li11Ol14219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0li11OO14206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll01ii26368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll0iOO27787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll0lli25312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll0lll27938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll0Oll21099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll0OlO21098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll1ili12666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll1l0i12995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll1l0l13226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0ll1l0O13225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lli11i27458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lli11l27456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lli1lO26083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0llOi1l12851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lO0Oli12743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOi01i12759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOi1OO12754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOl0ii12602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOl0il12600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOl0iO12599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOl0li12607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOl0Ol12538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOli0O12537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0lOli1i12545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0l0il12084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0l0iO12318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0l0li12317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0l1Ol11755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0llll26370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0O00i27789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0O0Ol25314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0O0OO27940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0OiOO21105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0Ol0i27703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0Ol0l27480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0Ol0O27478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0Ol1i21104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0Ol1l27707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0Ol1O27705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O0OO1i26088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1il0O13003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1ilii12468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1ilil12547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1iliO12476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1ilOi13307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1ilOl13305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1iO0i13299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1iO0l13310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0O1iO1O13312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Oii10O11940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OiOiOl11832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OiOO0i11843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OiOO0l11848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol010l11633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol011O11626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol01li11625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol1Oll11691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol1OlO11689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol1OOi11688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Ol1OOl11696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO10li12093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO10ll11555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO10lO11635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO10Oi11564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO1i1l12400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO1i1O12398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO1iii12405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO1iil12392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OO1iiO12403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OOOllO10656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101ili24106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101ill24107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101ilO27420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101iOl9948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101iOO9949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l0i16090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l0l15183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l0O14276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l1i11551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l1l17904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101l1O16997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101lii13369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101lil12462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101liO11541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1101lli18954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOii23546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOil26683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOiO26681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOli26679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOll26678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOlO23486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOOi19589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOOl19590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n110OOOO19843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1110O0O18762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1110Oii21198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1110Oli23547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i00i9978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i00l9976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i00O9974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i01i9990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i01l9986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i01O9984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i0ii9973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i0il23585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i10i12354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i10l23888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i10O9993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n111i1OO10028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11i111i19847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11i111l19781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11i111O19840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0Oii20659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0OiO23413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0Oli23446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0Oll26665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0OlO26663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0OOi26662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0OOl23442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11l0OOO26621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li10i21145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li10l21153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li10O21143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li11i26619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li11l26618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li1ii21150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11li1li9830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O000i26436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O000l26434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O000O26433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O001i26442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O001l26440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O001O26438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O00ll20660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O00OO21203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O011i25915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O01Ol26446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O01OO26444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0i1i20661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0i1O26590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0ill20641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0ilO21059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0iOi21061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0l1l24585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0l1O19986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0lii19984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0lil24584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0lli18955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0lll20250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0llO24108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0lOl24768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0O1O25056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0Oii24765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0OiO21115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0Oli21040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0Oll20924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0OlO19978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0OOi19979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1lil21210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1Oii20948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1OiO25928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1Oli25926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1Oll25924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1OlO25922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1OOi25920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1OOl25918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O1OOO25916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi01l24760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi0ii25477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi10i23897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi10l20175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi10O19980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1ii23487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1il19977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1ll23889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iili0l25475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iili0O25473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiliii25471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiliil25469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiliiO25467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iilili25465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iilill25463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iililO25461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiliOi25459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiliOl25457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiliOO25455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iill0i25447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iill0l25445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iill0O25443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iill1i25453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iill1l25451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iill1O25449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iillii25441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iillil25440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iillli25438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiOlii25436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiOlil25434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiOliO25432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iiOlli25431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il100i25425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il100l25423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il100O25421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il101l25429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il101O25427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10ii25419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10il25417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10iO25415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10li25413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10ll25411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10lO25409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10Oi25407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10Ol25405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il10OO25403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il11il20644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il11lO20653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il11Oi20651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il1i0i25395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il1i0l25394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il1i1i25401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il1i1l25399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1il1i1O25397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1illOiO26400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOO0i26392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOO0l26390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOO0O26388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOO1i26398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOO1l26396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOO1O26394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOii26387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOil20296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOli25329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOll25327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOlO25325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOOi25323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOOl25321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1ilOOOO25319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO001i25331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO001l25299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO01Oi25336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO01Ol25334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO01OO25332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0ili25297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0ill25295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0ilO25293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0iOi25291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0iOl25289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0iOO25287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0l0i25279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0l0l25278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0l1i25285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0l1l25283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO0l1O25281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO110i26674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO110l26672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO110O26670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO111i25317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO111l25316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO111O26676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO11ii26668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO11il26667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iO11iO25338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl00i25187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl00l25185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl00O25183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl01i25190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl0il25181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl0Oi25180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl1Ol25194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iOl1OO25192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l0001i11682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l000ll19831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l000lO19828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l000Oi19826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l000Ol19825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l000OO19823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l0010i11548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l0010l11543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l0010O11542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l0011l19903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l0011O19569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001ii19891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001il19881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001li19878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001lO19896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001Oi19874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001Ol19893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l001OO19872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l00i0i23478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l00i1i19784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l00i1l19819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l00i1O19818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l10iiO19988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1100i25172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1100l25170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1100O25168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1101i25178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1101l25176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1101O25174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l110ii25166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l110il25165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l110iO20000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OlOi18773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OO0i19949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OO0O19945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OO1i19975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OO1l19974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OO1O19951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OOii19943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OOiO19939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OOll19935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OOlO19933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1l1OOOl11561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lil0Ol23456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lilill18949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lill0l19912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lill0O19911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lill1l18967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lill1O19915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lillii18973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lilO0l19657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lO0lOi9962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lOi1lO18946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lOi1Oi18943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lOi1Ol18942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1O0Ol1i18108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1O0Olli18437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1O0Olll18668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1O0OllO18667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi001O26054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi010i27686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi010l27684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi010O27682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi011l21064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi011O21063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi01ii27325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi01il27323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi11Oi26357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi1l0O27776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi1O1i25301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oi1O1l27927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oiliil18293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Ol000O18196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Ol00ii18201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Ol011i18185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oli0Oi18044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oli0Ol18042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oli0OO18041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Olii0l17980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Olii1i18049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1Oliiii17987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OliilO17979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0llO18445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0lOi17910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0lOl17989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0lOO17918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0O0i18749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0O0l18747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0OiO18754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0Oli18741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OO0Oll18752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni00liOi10201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni00liOl10879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni00liOO10877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni00ll1i10876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni01lO0O10197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni01lOii10960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni01lOil10958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni01lOiO10957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i000i10691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i000l10689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i000O10687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i001i10697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i001l10695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i001O10693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00ii10685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00il10683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00iO10681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00li10679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00ll10677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00lO10675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00Oi10673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00Ol10671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i00OO10669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i010i10721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i010l10719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i010O10717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i011i10727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i011l10725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i011O10723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01ii10715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01il10713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01iO10711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01li10709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01ll10707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01lO10705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01Oi10703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01Ol10701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i01OO10699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i0i0i10663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i0i0l10658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i0i0O10123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i0i1i10667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i0i1l10666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i0i1O10661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1i0O10807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1iii10805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1iil10803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1iiO10801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1ili10799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1ill10797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1ilO10795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1iOi10794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1iOl10792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1iOO10790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1l0i10782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1l0l10780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1l0O10778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1l1i10788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1l1l10786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1l1O10784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1lii10776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1lil10774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1liO10772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1lli10770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1lll10768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1llO10765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1lOi10763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1lOl10761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1lOO10759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1O0i10751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1O0l10749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1O0O10747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1O1i10757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1O1l10755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1O1O10753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1Oii10745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1Oil10743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1OiO10741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1Oli10739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1Oll10737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1OlO10735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1OOi10733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1OOl10731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni0i1OOO10729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni101i0i11362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni101i1i10177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni101i1l11365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni101i1O11363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni11100l10646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni11101O10649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1111Ol10654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1111OO10642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni111liO10174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni111lli11446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni111lll11444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni111llO11443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1i11il10181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1i11iO11284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1i11li11282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1i11ll11281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1iOlOO10185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1iOO1i11203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1iOO1l11201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1iOO1O11200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1lOiii10189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1lOiil11122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1lOiiO11120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1lOili11119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1OO01i11039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1OO01l11038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1OO1Ol10193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_ni1OO1OO11041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nii0li1l10110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nii0lllO10097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nii0O1ii10084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nii0Oi1l10071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nii0OllO10058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niii0OOl10595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niii0OOO10593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niii11ii10045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niii1i1l10032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii00l10531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii01l10495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii01O10493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0ii10500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0il10487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0iO10498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0ll10445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0lO10443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii0Ol10481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii10i10600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii10l10587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii10O10598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii11l10631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1il10545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1iO10543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1ll10581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1Oi10550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1Ol10537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiii1OO10548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiii0l10395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiii0O10393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiii1i10450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiii1l10437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiii1O10448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiiil10431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiili10400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiill10387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiilO10398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiiOl10345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiiOO10343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiil0i10350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiil0l10337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiil0O10348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiil1l10381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiilil10295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiliO10293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiilll10331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiilOi10300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiilOl10287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiilOO10298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiO0l10281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiO1l10245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiO1O10243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOii10250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOil10237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOiO10248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOli10024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOll10022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOlO10020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOOi10018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOOl10016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiiiOOO10014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiil11i10012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niiil11l10010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niil010i18930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niil010O18772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niO010ll8775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niO011ll8784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niO01ilO8766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0O0OO19990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Oi0i20950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Oi0l21202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Oi1O20909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Olii20546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOi001il28841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOi00i1l28834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOi0i10l28824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOi0lOOi28776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOi0O0OO28765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOi0OliO28758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOi0OOli28755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOii01OO28730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOii0iiO28723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOii1ilO28744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOii1O0O28737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiii0iO28716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiil0il28687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiiO1iO28670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiiOO1O28650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOili1Oi28463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOill1Ol28335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOilO0lO28278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOilOl0O28271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOilOOOO28264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiO101i28260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiO101l28258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOiOO1ll28114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliiO0i21204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO0ll26842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll000i26820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll000l26819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll001i26826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll001l26824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll001O26822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll01iO26840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll01li26838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll01ll26836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll01lO26834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll01Oi26832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll01Ol26830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll01OO26828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll0O0i19983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOll0O0O21039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlliO1i27864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlliO1l27862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlliOlO27861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllll0l19981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllll0O19982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllO0iO17973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllOliO17066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllOlli16159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllOlll15252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllOllO14345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllOlOi13438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllOlOl12531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOllOlOO11619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlO010i8774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlO010l8783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlO011i8765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlO1l0i24728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOi00l27726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOil0i27714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOil0l27712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOil0O27710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOil1i27724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOil1l27722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOil1O27720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOilii27709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOiliO21217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOilli24721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOilOl24719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOlOiO1i24684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0000i26383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0000l26381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0000O26379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0001O26385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000ii26377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000il26375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000iO26373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000li26372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000ll25261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000lO25259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000Oi25257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000Ol25255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO000OO25253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00i0i26584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00i0l26582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00i0O26580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00i1i25251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00i1l25249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00i1O25248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00iii26578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00iil26576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00iiO26574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00ili26572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00ill26571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00ilO25943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00iOi25941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00iOl25939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00iOO25937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00l0i25930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00l0l26942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00l0O26940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00l1i25935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00l1l25933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00l1O25931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00lii26938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00lil26936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00liO26934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00lli26932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00lll26930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00llO26929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00O0O25882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00Oii25880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00Oil25878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00OiO25876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00Oli25874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00Oll25872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00OlO25870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00OOi25869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00OOl26461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO00OOO26459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0100l25731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0100O25729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010ii25727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010il25725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010iO25723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010li25721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010ll25720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010lO25794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010Oi25792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010Ol25790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO010OO25788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01i0i25781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01i1i25786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01i1l25784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01i1O25782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01iOi26143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01iOl26141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01iOO26139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01l0i26131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01l0l26130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01l0O25618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01l1i26137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01l1l26135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01l1O26133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01lii25616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01lil25614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01liO25612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01lli25610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01lll25608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01llO25606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO01lOi25605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i00i25238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i00l25236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i00O25234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i01i25244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i01l25242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i01O25240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0ii25233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0il26316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0iO26314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0li26312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0ll26310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0lO26308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0Oi26306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0Ol26304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i0OO26303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i10i26451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i10l26449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i10O26448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i11i26457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i11l26455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i11O26453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0i1OO25246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0iilO20976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0iiOi20978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0iiOl25834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0iiOO20980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0il0i20982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0il0l25276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0il0O25274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0il1i25831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0il1l25829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0il1O25827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0ilii25272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0ilil25270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0iliO25268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0illi25266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0illl25264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO0illO25263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1i1Oi27602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O10O27600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1ii27598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1il27596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1iO27594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1li27592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1ll27590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1lO27589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1Ol24778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1OO25733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiO0i25744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiO0l25742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiO0O25740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiO1l25748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiO1O25746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiOii25738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiOil25736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOiOiO25735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl00i21006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl01i24772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl01l24771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl01O24770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1ll24777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1lO24776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1Oi24775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1Ol24774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOOOl1OO24773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O1O1O20986w20987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i00i9978w10081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i00l9976w10094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i00O9974w10107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i01i9990w10042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i01l9986w10055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i01O9984w10068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i0ii9973w10120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n111i1OO10028w10029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOli10024w10122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOll10022w10109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOlO10020w10096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOOi10018w10083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOOl10016w10070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiiiOOO10014w10057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiil11i10012w10044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_niiil11l10010w10031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_w_lg_n11O0O0O22889w22890w22891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n11O0O0O22889w22890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lilO0l19027w19028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lOi01l18853w18854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lOi01O18871w18872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_n1lOi01O18792w18888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0iOl23838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0iOO23837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0l0l23097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11O0O0O22889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi01i24741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi10i24739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi11l24740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1ii24738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1il24747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1li24737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1ll24746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1lO24745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1Oi24744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1Ol24743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n11Oi1OO24742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1iilliO21209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lillOO19215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lilO0l19027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lilO0l18986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lOi01l18853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lOi01O18871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1lOi01O18792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Oi0i20918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Oi1l20901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_niOO0Oi1O20952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOO1O1Ol24590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOlO010i8774w8777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOlO010l8783w8786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_w_lg_nlOlO011i8765w8768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00l0lOl15587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n00l0Oil15591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0100i0O17401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0100iOO17405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01OO00i16498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n01OO1li16494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i0Oi1O14680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0i0OilO14684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l1i01i13777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0l1i1ii13773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0llOlll12866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0llOO0l12870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0Oii0OO11955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n0OiiiiO11959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OilO1l18308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_n1OilOll18312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO00i25133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO00l25136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO01i25113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO01l25116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO0ii25123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO0il25126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO10i25073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO10l25076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO11i25063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO11l25066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1ii25083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1il25086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1li25093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1ll25096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1Oi25103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01ill_w_lg_nlOliO1Ol25106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n001i1ii : STD_LOGIC := '0'; + SIGNAL n00il1ll : STD_LOGIC := '0'; + SIGNAL n00il1lO : STD_LOGIC := '0'; + SIGNAL n00il1Oi : STD_LOGIC := '0'; + SIGNAL n00il1Ol : STD_LOGIC := '0'; + SIGNAL n00l0OiO : STD_LOGIC := '0'; + SIGNAL n00l0Oli : STD_LOGIC := '0'; + SIGNAL n00l0Oll : STD_LOGIC := '0'; + SIGNAL n00l0OlO : STD_LOGIC := '0'; + SIGNAL n00lOlll : STD_LOGIC := '0'; + SIGNAL n0100l0i : STD_LOGIC := '0'; + SIGNAL n0100l1i : STD_LOGIC := '0'; + SIGNAL n0100l1l : STD_LOGIC := '0'; + SIGNAL n0100l1O : STD_LOGIC := '0'; + SIGNAL n010Oi1O : STD_LOGIC := '0'; + SIGNAL n011iO0i : STD_LOGIC := '0'; + SIGNAL n011iO0l : STD_LOGIC := '0'; + SIGNAL n011iO0O : STD_LOGIC := '0'; + SIGNAL n011iO1O : STD_LOGIC := '0'; + SIGNAL n01O1iii : STD_LOGIC := '0'; + SIGNAL n01O1iil : STD_LOGIC := '0'; + SIGNAL n01O1iiO : STD_LOGIC := '0'; + SIGNAL n01O1ili : STD_LOGIC := '0'; + SIGNAL n01OO00l : STD_LOGIC := '0'; + SIGNAL n01OO00O : STD_LOGIC := '0'; + SIGNAL n01OO0ii : STD_LOGIC := '0'; + SIGNAL n01OO0il : STD_LOGIC := '0'; + SIGNAL n0i01lOO : STD_LOGIC := '0'; + SIGNAL n0i01O1i : STD_LOGIC := '0'; + SIGNAL n0i01O1l : STD_LOGIC := '0'; + SIGNAL n0i01O1O : STD_LOGIC := '0'; + SIGNAL n0i0OiOi : STD_LOGIC := '0'; + SIGNAL n0i0OiOl : STD_LOGIC := '0'; + SIGNAL n0i0OiOO : STD_LOGIC := '0'; + SIGNAL n0i0Ol1i : STD_LOGIC := '0'; + SIGNAL n0iii0OO : STD_LOGIC := '0'; + SIGNAL n0iOli0i : STD_LOGIC := '0'; + SIGNAL n0iOli0l : STD_LOGIC := '0'; + SIGNAL n0iOli0O : STD_LOGIC := '0'; + SIGNAL n0iOliii : STD_LOGIC := '0'; + SIGNAL n0l0110i : STD_LOGIC := '0'; + SIGNAL n0l1i00i : STD_LOGIC := '0'; + SIGNAL n0l1i00l : STD_LOGIC := '0'; + SIGNAL n0l1i01l : STD_LOGIC := '0'; + SIGNAL n0l1i01O : STD_LOGIC := '0'; + SIGNAL n0ll01il : STD_LOGIC := '0'; + SIGNAL n0ll01iO : STD_LOGIC := '0'; + SIGNAL n0ll01li : STD_LOGIC := '0'; + SIGNAL n0ll01ll : STD_LOGIC := '0'; + SIGNAL n0llOO0O : STD_LOGIC := '0'; + SIGNAL n0llOOii : STD_LOGIC := '0'; + SIGNAL n0llOOil : STD_LOGIC := '0'; + SIGNAL n0llOOiO : STD_LOGIC := '0'; + SIGNAL n0lOilil : STD_LOGIC := '0'; + SIGNAL n0O0lllO : STD_LOGIC := '0'; + SIGNAL n0O0llOi : STD_LOGIC := '0'; + SIGNAL n0O0llOl : STD_LOGIC := '0'; + SIGNAL n0O0llOO : STD_LOGIC := '0'; + SIGNAL n0Oiiili : STD_LOGIC := '0'; + SIGNAL n0Oiiill : STD_LOGIC := '0'; + SIGNAL n0OiiilO : STD_LOGIC := '0'; + SIGNAL n0OiiiOi : STD_LOGIC := '0'; + SIGNAL n0Ol10lO : STD_LOGIC := '0'; + SIGNAL n11i110i : STD_LOGIC := '0'; + SIGNAL n11l0O0O : STD_LOGIC := '0'; + SIGNAL n11li1iO : STD_LOGIC := '0'; + SIGNAL n11O010l : STD_LOGIC := '0'; + SIGNAL n11O0i0l : STD_LOGIC := '0'; + SIGNAL n11O0i1l : STD_LOGIC := '0'; + SIGNAL n11O0iii : STD_LOGIC := '0'; + SIGNAL n11O0iiO : STD_LOGIC := '0'; + SIGNAL n11O0Oil : STD_LOGIC := '0'; + SIGNAL n11Oi00O : STD_LOGIC := '0'; + SIGNAL n1il11Ol : STD_LOGIC := '0'; + SIGNAL n1l1OO0l : STD_LOGIC := '0'; + SIGNAL n1l1OOil : STD_LOGIC := '0'; + SIGNAL n1l1OOli : STD_LOGIC := '0'; + SIGNAL n1l1OOOi : STD_LOGIC := '0'; + SIGNAL n1lililO : STD_LOGIC := '0'; + SIGNAL n1lilO0O : STD_LOGIC := '0'; + SIGNAL n1lOi0ii : STD_LOGIC := '0'; + SIGNAL n1Oi101i : STD_LOGIC := '0'; + SIGNAL n1Oi101l : STD_LOGIC := '0'; + SIGNAL n1Oi11Ol : STD_LOGIC := '0'; + SIGNAL n1Oi11OO : STD_LOGIC := '0'; + SIGNAL n1OilOlO : STD_LOGIC := '0'; + SIGNAL n1OilOOi : STD_LOGIC := '0'; + SIGNAL n1OilOOl : STD_LOGIC := '0'; + SIGNAL n1OilOOO : STD_LOGIC := '0'; + SIGNAL n1Ol0lOl : STD_LOGIC := '0'; + SIGNAL niO010lO : STD_LOGIC := '0'; + SIGNAL niO011lO : STD_LOGIC := '0'; + SIGNAL niO01iOl : STD_LOGIC := '0'; + SIGNAL nlOill00i : STD_LOGIC := '0'; + SIGNAL nlOill01i : STD_LOGIC := '0'; + SIGNAL nlOill1OO : STD_LOGIC := '0'; + SIGNAL nlOiO10Ol : STD_LOGIC := '0'; + SIGNAL nlOiOO1lO : STD_LOGIC := '0'; + SIGNAL nlOlil10O : STD_LOGIC := '0'; + SIGNAL nlOliO00O : STD_LOGIC := '0'; + SIGNAL nlOliO01O : STD_LOGIC := '0'; + SIGNAL nlOliO0iO : STD_LOGIC := '0'; + SIGNAL nlOliO10O : STD_LOGIC := '0'; + SIGNAL nlOliO11O : STD_LOGIC := '0'; + SIGNAL nlOliO1iO : STD_LOGIC := '0'; + SIGNAL nlOliO1lO : STD_LOGIC := '0'; + SIGNAL nlOliO1OO : STD_LOGIC := '0'; + SIGNAL nlOll0Oii : STD_LOGIC := '0'; + SIGNAL nlOllllii : STD_LOGIC := '0'; + SIGNAL nlOlOilll : STD_LOGIC := '0'; + SIGNAL nlOlOilOO : STD_LOGIC := '0'; + SIGNAL wire_niO01iOi_w19584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n00il1Ol15580w15581w15582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n00l0OlO15551w15553w15554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0100l0i17365w17367w17368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n011iO0O17394w17395w17396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n01O1ili16487w16488w16489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n01OO0il16458w16460w16461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0i01O1O14673w14674w14675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0i0Ol1i14644w14646w14647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0iOliii13766w13767w13768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0l1i00l13737w13739w13740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0ll01ll12859w12860w12861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0llOOiO12830w12832w12833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0O0llOO11948w11949w11950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n0OiiiOi11919w11921w11922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n1Oi101l18301w18302w18303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n1OilOOO18272w18274w18275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w25118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_n1lilO0O19581w19582w19583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n00il1Ol15580w15581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n00l0OlO15551w15553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n00l0OlO15551w15864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0100l0i17365w17367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0100l0i17365w17678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n011iO0O17394w17395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n01O1ili16487w16488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n01OO0il16458w16460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n01OO0il16458w16771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0i01O1O14673w14674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0i0Ol1i14644w14646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0i0Ol1i14644w14957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0iOliii13766w13767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0l1i00l13737w13739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0l1i00l13737w14050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0ll01ll12859w12860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0llOOiO12830w12832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0llOOiO12830w13143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0O0llOO11948w11949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0OiiiOi11919w11921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n0OiiiOi11919w12235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n1Oi101l18301w18302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n1OilOOO18272w18274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n1OilOOO18272w18585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOllllii23878w23879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOlil10O25061w25062w25065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO00O25121w25122w25125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO01O25131w25132w25135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO10O25081w25082w25085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO11O25071w25072w25075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1iO25091w25092w25095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1lO25101w25102w25105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1OO25111w25112w25115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n11Oi00O20642w20643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n11Oi00O20642w20646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n1lilO0O19581w19582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOiOO1lO28034w28035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00il1Ol15580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00l0OlO15551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0100l0i17365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n011iO0O17394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01O1ili16487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01OO0il16458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i01O1O14673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i0Ol1i14644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0iOliii13766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0l1i00l13737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0ll01ll12859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0llOOiO12830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0O0llOO11948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0OiiiOi11919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1Oi101l18301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1OilOOO18272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOllllii23878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOlil10O25061w25062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOliO00O25121w25122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOliO01O25131w25132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOliO10O25081w25082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOliO11O25071w25072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOliO1iO25091w25092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOliO1lO25101w25102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_nlOliO1OO25111w25112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00il1ll15944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00il1lO15942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00il1Oi15940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00il1Ol15939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00l0OiO15859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00l0Oli15552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00l0Oll15550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n00l0OlO15856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0100l0i17670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0100l1i17673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0100l1l17366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0100l1O17364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n011iO0i17756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n011iO0l17754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n011iO0O17753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n011iO1O17758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01O1iii16851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01O1iil16849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01O1iiO16847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01O1ili16846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01OO00l16766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01OO00O16459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01OO0ii16457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n01OO0il16763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i01lOO15037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i01O1i15035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i01O1l15033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i01O1O15032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i0OiOi14952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i0OiOl14645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i0OiOO14643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0i0Ol1i14949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0iOli0i14130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0iOli0l14128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0iOli0O14126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0iOliii14125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0l1i00i13736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0l1i00l14042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0l1i01l14045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0l1i01O13738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0ll01il13223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0ll01iO13221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0ll01li13219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0ll01ll13218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0llOO0O13138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0llOOii12831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0llOOil12829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0llOOiO13135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0O0lllO12315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0O0llOi12313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0O0llOl12311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0O0llOO12310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0Oiiili12230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0Oiiill11920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0OiiilO11918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n0OiiiOi12227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11li1iO9835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0i0l21009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0i1l26592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0iii26586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0iiO26588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11Oi00O20642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1il11Ol20649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1l1OO0l19947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1l1OOil19941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1l1OOli19937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1l1OOOi19932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1lilO0O19581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1Oi101i18661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1Oi101l18660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1Oi11Ol18665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1Oi11OO18663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1OilOlO18580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1OilOOi18273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1OilOOl18271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n1OilOOO18577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOiO10Ol28193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOiOO1lO28034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOllllii23948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOlOilOO24659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_w_lg_n11O0Oil21254w21255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0Oil23855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0Oil21467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0Oil21254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_n11O0Oil23836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOlil10O25061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOliO00O25121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOliO01O25131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOliO10O25081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOliO11O25071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOliO1iO25091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOliO1lO25101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01iOi_w_lg_nlOliO1OO25111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO01lii : STD_LOGIC := '0'; + SIGNAL niO01lli : STD_LOGIC := '0'; + SIGNAL n1iiOllO : STD_LOGIC := '0'; + SIGNAL niil01ii : STD_LOGIC := '0'; + SIGNAL niil01il : STD_LOGIC := '0'; + SIGNAL niil0iOO : STD_LOGIC := '0'; + SIGNAL niil0l0i : STD_LOGIC := '0'; + SIGNAL niil0l0l : STD_LOGIC := '0'; + SIGNAL niil0l1l : STD_LOGIC := '0'; + SIGNAL niil0l1O : STD_LOGIC := '0'; + SIGNAL niil0liO : STD_LOGIC := '0'; + SIGNAL niil0llO : STD_LOGIC := '0'; + SIGNAL niil0lOi : STD_LOGIC := '0'; + SIGNAL niil0lOl : STD_LOGIC := '0'; + SIGNAL niili1iO : STD_LOGIC := '0'; + SIGNAL niili1li : STD_LOGIC := '0'; + SIGNAL niili1ll : STD_LOGIC := '0'; + SIGNAL niili1lO : STD_LOGIC := '0'; + SIGNAL niili1Oi : STD_LOGIC := '0'; + SIGNAL niO0100i : STD_LOGIC := '0'; + SIGNAL niO0110i : STD_LOGIC := '0'; + SIGNAL niO01i0i : STD_LOGIC := '0'; + SIGNAL niO01lll : STD_LOGIC := '0'; + SIGNAL niO01lOi : STD_LOGIC := '0'; + SIGNAL niO110ii : STD_LOGIC := '0'; + SIGNAL niO110il : STD_LOGIC := '0'; + SIGNAL niO110iO : STD_LOGIC := '0'; + SIGNAL niO110li : STD_LOGIC := '0'; + SIGNAL niO110ll : STD_LOGIC := '0'; + SIGNAL niO1li0i : STD_LOGIC := '0'; + SIGNAL niO1li1O : STD_LOGIC := '0'; + SIGNAL niO1OOOi : STD_LOGIC := '0'; + SIGNAL niOO0Olli : STD_LOGIC := '0'; + SIGNAL nlOi0000O : STD_LOGIC := '0'; + SIGNAL nlOi00l0O : STD_LOGIC := '0'; + SIGNAL nlOi00l1l : STD_LOGIC := '0'; + SIGNAL nlOi00O0O : STD_LOGIC := '0'; + SIGNAL nlOi01OlO : STD_LOGIC := '0'; + SIGNAL nlOi0l1Oi : STD_LOGIC := '0'; + SIGNAL nlOi0O01O : STD_LOGIC := '0'; + SIGNAL nlOi0O11i : STD_LOGIC := '0'; + SIGNAL nlOi0OilO : STD_LOGIC := '0'; + SIGNAL nlOi0OOOi : STD_LOGIC := '0'; + SIGNAL nlOii00Oi : STD_LOGIC := '0'; + SIGNAL nlOii010i : STD_LOGIC := '0'; + SIGNAL nlOii0liO : STD_LOGIC := '0'; + SIGNAL nlOii0lOi : STD_LOGIC := '0'; + SIGNAL nlOii0O0O : STD_LOGIC := '0'; + SIGNAL nlOii0O1l : STD_LOGIC := '0'; + SIGNAL nlOii0Oli : STD_LOGIC := '0'; + SIGNAL nlOii100O : STD_LOGIC := '0'; + SIGNAL nlOii101l : STD_LOGIC := '0'; + SIGNAL nlOii10li : STD_LOGIC := '0'; + SIGNAL nlOii10Ol : STD_LOGIC := '0'; + SIGNAL nlOii1i1i : STD_LOGIC := '0'; + SIGNAL nlOii1lli : STD_LOGIC := '0'; + SIGNAL nlOiii1Oi : STD_LOGIC := '0'; + SIGNAL nlOiiiOlO : STD_LOGIC := '0'; + SIGNAL nlOiilO0O : STD_LOGIC := '0'; + SIGNAL nlOiiOiOi : STD_LOGIC := '0'; + SIGNAL nlOil101l : STD_LOGIC := '0'; + SIGNAL nlOil101O : STD_LOGIC := '0'; + SIGNAL nlOil10il : STD_LOGIC := '0'; + SIGNAL nlOil1i1O : STD_LOGIC := '0'; + SIGNAL nlOili11l : STD_LOGIC := '0'; + SIGNAL nlOilil0i : STD_LOGIC := '0'; + SIGNAL nlOilil0l : STD_LOGIC := '0'; + SIGNAL nlOilil1i : STD_LOGIC := '0'; + SIGNAL nlOilil1O : STD_LOGIC := '0'; + SIGNAL nlOilO01i : STD_LOGIC := '0'; + SIGNAL nlOilOili : STD_LOGIC := '0'; + SIGNAL nlOilOO0i : STD_LOGIC := '0'; + SIGNAL wire_niO01llO_CLRN : STD_LOGIC; + SIGNAL wire_niO01llO_w_lg_niil01ii23952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01llO_w_lg_niil01il23950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01llO_w_lg_niil0iOO23954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01llO_w_lg_niil0l0i23960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01llO_w_lg_niil0l0l23962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01llO_w_lg_niil0l1l23956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01llO_w_lg_niil0l1O23958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO01llO_w_lg_niil0liO23964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO01Oll : STD_LOGIC := '0'; + SIGNAL niO01OOi : STD_LOGIC := '0'; + SIGNAL wire_niO01OlO_PRN : STD_LOGIC; + SIGNAL n1l00il : STD_LOGIC := '0'; + SIGNAL n1lliil : STD_LOGIC := '0'; + SIGNAL n1lliiO : STD_LOGIC := '0'; + SIGNAL n1llili : STD_LOGIC := '0'; + SIGNAL ni0li0l : STD_LOGIC := '0'; + SIGNAL ni0li0O : STD_LOGIC := '0'; + SIGNAL ni0li1l : STD_LOGIC := '0'; + SIGNAL ni0liii : STD_LOGIC := '0'; + SIGNAL ni0liil : STD_LOGIC := '0'; + SIGNAL ni0liiO : STD_LOGIC := '0'; + SIGNAL ni0lili : STD_LOGIC := '0'; + SIGNAL ni0lill : STD_LOGIC := '0'; + SIGNAL ni0lilO : STD_LOGIC := '0'; + SIGNAL ni0O00i : STD_LOGIC := '0'; + SIGNAL ni0O00l : STD_LOGIC := '0'; + SIGNAL ni0O00O : STD_LOGIC := '0'; + SIGNAL ni0O01i : STD_LOGIC := '0'; + SIGNAL ni0O01l : STD_LOGIC := '0'; + SIGNAL ni0O01O : STD_LOGIC := '0'; + SIGNAL ni0O0ii : STD_LOGIC := '0'; + SIGNAL ni0O0il : STD_LOGIC := '0'; + SIGNAL ni0O0iO : STD_LOGIC := '0'; + SIGNAL ni0O0li : STD_LOGIC := '0'; + SIGNAL ni0O0ll : STD_LOGIC := '0'; + SIGNAL ni0O0lO : STD_LOGIC := '0'; + SIGNAL ni0O0Oi : STD_LOGIC := '0'; + SIGNAL ni0O0Ol : STD_LOGIC := '0'; + SIGNAL ni0O0OO : STD_LOGIC := '0'; + SIGNAL ni0O1li : STD_LOGIC := '0'; + SIGNAL ni0Oi0i : STD_LOGIC := '0'; + SIGNAL ni0Oi0l : STD_LOGIC := '0'; + SIGNAL ni0Oi0O : STD_LOGIC := '0'; + SIGNAL ni0Oi1i : STD_LOGIC := '0'; + SIGNAL ni0Oi1l : STD_LOGIC := '0'; + SIGNAL ni0Oi1O : STD_LOGIC := '0'; + SIGNAL ni0Oiii : STD_LOGIC := '0'; + SIGNAL ni0Oiil : STD_LOGIC := '0'; + SIGNAL ni0OiiO : STD_LOGIC := '0'; + SIGNAL ni0Oili : STD_LOGIC := '0'; + SIGNAL ni0Oill : STD_LOGIC := '0'; + SIGNAL ni0OilO : STD_LOGIC := '0'; + SIGNAL ni0OiOi : STD_LOGIC := '0'; + SIGNAL ni0OiOl : STD_LOGIC := '0'; + SIGNAL ni0OiOO : STD_LOGIC := '0'; + SIGNAL ni0Ol0i : STD_LOGIC := '0'; + SIGNAL ni0Ol0l : STD_LOGIC := '0'; + SIGNAL ni0Ol1i : STD_LOGIC := '0'; + SIGNAL ni0Ol1l : STD_LOGIC := '0'; + SIGNAL ni0Ol1O : STD_LOGIC := '0'; + SIGNAL niO010iO : STD_LOGIC := '0'; + SIGNAL niO010li : STD_LOGIC := '0'; + SIGNAL niO011iO : STD_LOGIC := '0'; + SIGNAL niO011li : STD_LOGIC := '0'; + SIGNAL niO01iiO : STD_LOGIC := '0'; + SIGNAL niO01ili : STD_LOGIC := '0'; + SIGNAL niOiil0i : STD_LOGIC := '0'; + SIGNAL niOiilll : STD_LOGIC := '0'; + SIGNAL niOiilOl : STD_LOGIC := '0'; + SIGNAL niOiilOO : STD_LOGIC := '0'; + SIGNAL niOiiO0i : STD_LOGIC := '0'; + SIGNAL niOiiO0l : STD_LOGIC := '0'; + SIGNAL niOiiO0O : STD_LOGIC := '0'; + SIGNAL niOiiO1i : STD_LOGIC := '0'; + SIGNAL niOiiO1l : STD_LOGIC := '0'; + SIGNAL niOiiO1O : STD_LOGIC := '0'; + SIGNAL niOiiOii : STD_LOGIC := '0'; + SIGNAL niOiiOil : STD_LOGIC := '0'; + SIGNAL niOiiOiO : STD_LOGIC := '0'; + SIGNAL niOiiOli : STD_LOGIC := '0'; + SIGNAL niOiiOll : STD_LOGIC := '0'; + SIGNAL niOiiOlO : STD_LOGIC := '0'; + SIGNAL niOiiOOi : STD_LOGIC := '0'; + SIGNAL niOiiOOl : STD_LOGIC := '0'; + SIGNAL niOiiOOO : STD_LOGIC := '0'; + SIGNAL niOil00i : STD_LOGIC := '0'; + SIGNAL niOil00l : STD_LOGIC := '0'; + SIGNAL niOil00O : STD_LOGIC := '0'; + SIGNAL niOil01i : STD_LOGIC := '0'; + SIGNAL niOil01l : STD_LOGIC := '0'; + SIGNAL niOil01O : STD_LOGIC := '0'; + SIGNAL niOil0ii : STD_LOGIC := '0'; + SIGNAL niOil0il : STD_LOGIC := '0'; + SIGNAL niOil0iO : STD_LOGIC := '0'; + SIGNAL niOil0li : STD_LOGIC := '0'; + SIGNAL niOil0ll : STD_LOGIC := '0'; + SIGNAL niOil0lO : STD_LOGIC := '0'; + SIGNAL niOil0Oi : STD_LOGIC := '0'; + SIGNAL niOil0Ol : STD_LOGIC := '0'; + SIGNAL niOil0OO : STD_LOGIC := '0'; + SIGNAL niOil10i : STD_LOGIC := '0'; + SIGNAL niOil10l : STD_LOGIC := '0'; + SIGNAL niOil10O : STD_LOGIC := '0'; + SIGNAL niOil11i : STD_LOGIC := '0'; + SIGNAL niOil11l : STD_LOGIC := '0'; + SIGNAL niOil11O : STD_LOGIC := '0'; + SIGNAL niOil1ii : STD_LOGIC := '0'; + SIGNAL niOil1il : STD_LOGIC := '0'; + SIGNAL niOil1iO : STD_LOGIC := '0'; + SIGNAL niOil1li : STD_LOGIC := '0'; + SIGNAL niOil1ll : STD_LOGIC := '0'; + SIGNAL niOil1lO : STD_LOGIC := '0'; + SIGNAL niOil1Oi : STD_LOGIC := '0'; + SIGNAL niOil1Ol : STD_LOGIC := '0'; + SIGNAL niOil1OO : STD_LOGIC := '0'; + SIGNAL niOiOii : STD_LOGIC := '0'; + SIGNAL niOiOlli : STD_LOGIC := '0'; + SIGNAL niOiOlll : STD_LOGIC := '0'; + SIGNAL niOiOllO : STD_LOGIC := '0'; + SIGNAL niOiOlOi : STD_LOGIC := '0'; + SIGNAL niOiOlOl : STD_LOGIC := '0'; + SIGNAL niOiOlOO : STD_LOGIC := '0'; + SIGNAL niOiOO0i : STD_LOGIC := '0'; + SIGNAL niOiOO0l : STD_LOGIC := '0'; + SIGNAL niOiOO0O : STD_LOGIC := '0'; + SIGNAL niOiOO1i : STD_LOGIC := '0'; + SIGNAL niOiOO1l : STD_LOGIC := '0'; + SIGNAL niOiOO1O : STD_LOGIC := '0'; + SIGNAL niOiOOii : STD_LOGIC := '0'; + SIGNAL niOiOOil : STD_LOGIC := '0'; + SIGNAL niOiOOiO : STD_LOGIC := '0'; + SIGNAL niOiOOli : STD_LOGIC := '0'; + SIGNAL niOiOOll : STD_LOGIC := '0'; + SIGNAL niOiOOlO : STD_LOGIC := '0'; + SIGNAL niOiOOOi : STD_LOGIC := '0'; + SIGNAL niOiOOOl : STD_LOGIC := '0'; + SIGNAL niOiOOOO : STD_LOGIC := '0'; + SIGNAL niOl100i : STD_LOGIC := '0'; + SIGNAL niOl100l : STD_LOGIC := '0'; + SIGNAL niOl100O : STD_LOGIC := '0'; + SIGNAL niOl101i : STD_LOGIC := '0'; + SIGNAL niOl101l : STD_LOGIC := '0'; + SIGNAL niOl101O : STD_LOGIC := '0'; + SIGNAL niOl10ii : STD_LOGIC := '0'; + SIGNAL niOl10il : STD_LOGIC := '0'; + SIGNAL niOl10iO : STD_LOGIC := '0'; + SIGNAL niOl10li : STD_LOGIC := '0'; + SIGNAL niOl10ll : STD_LOGIC := '0'; + SIGNAL niOl10lO : STD_LOGIC := '0'; + SIGNAL niOl10Oi : STD_LOGIC := '0'; + SIGNAL niOl110i : STD_LOGIC := '0'; + SIGNAL niOl110l : STD_LOGIC := '0'; + SIGNAL niOl110O : STD_LOGIC := '0'; + SIGNAL niOl111i : STD_LOGIC := '0'; + SIGNAL niOl111l : STD_LOGIC := '0'; + SIGNAL niOl111O : STD_LOGIC := '0'; + SIGNAL niOl11ii : STD_LOGIC := '0'; + SIGNAL niOl11il : STD_LOGIC := '0'; + SIGNAL niOl11iO : STD_LOGIC := '0'; + SIGNAL niOl11li : STD_LOGIC := '0'; + SIGNAL niOl11ll : STD_LOGIC := '0'; + SIGNAL niOl11lO : STD_LOGIC := '0'; + SIGNAL niOl11Oi : STD_LOGIC := '0'; + SIGNAL niOl11Ol : STD_LOGIC := '0'; + SIGNAL niOl11OO : STD_LOGIC := '0'; + SIGNAL niOlii1O : STD_LOGIC := '0'; + SIGNAL niOlOilO : STD_LOGIC := '0'; + SIGNAL niOlOl0i : STD_LOGIC := '0'; + SIGNAL niOlOlii : STD_LOGIC := '0'; + SIGNAL niOlOO0i : STD_LOGIC := '0'; + SIGNAL niOlOOll : STD_LOGIC := '0'; + SIGNAL niOlOOOl : STD_LOGIC := '0'; + SIGNAL niOO001l : STD_LOGIC := '0'; + SIGNAL niOO00iO : STD_LOGIC := '0'; + SIGNAL niOO00lO : STD_LOGIC := '0'; + SIGNAL niOO00O : STD_LOGIC := '0'; + SIGNAL niOO00Oi : STD_LOGIC := '0'; + SIGNAL niOO00Ol : STD_LOGIC := '0'; + SIGNAL niOO0ii : STD_LOGIC := '0'; + SIGNAL niOO0il : STD_LOGIC := '0'; + SIGNAL niOO0ill : STD_LOGIC := '0'; + SIGNAL niOO0iO : STD_LOGIC := '0'; + SIGNAL niOO0l0O : STD_LOGIC := '0'; + SIGNAL niOO0l1i : STD_LOGIC := '0'; + SIGNAL niOO0li : STD_LOGIC := '0'; + SIGNAL niOO0lil : STD_LOGIC := '0'; + SIGNAL niOO0ll : STD_LOGIC := '0'; + SIGNAL niOO0lO : STD_LOGIC := '0'; + SIGNAL niOO0Oi : STD_LOGIC := '0'; + SIGNAL niOO0OiO : STD_LOGIC := '0'; + SIGNAL niOO0Ol : STD_LOGIC := '0'; + SIGNAL niOO0Olil : STD_LOGIC := '0'; + SIGNAL niOO0OlOO : STD_LOGIC := '0'; + SIGNAL niOO0OO : STD_LOGIC := '0'; + SIGNAL niOO0OO0i : STD_LOGIC := '0'; + SIGNAL niOO0OO0l : STD_LOGIC := '0'; + SIGNAL niOO0OO0O : STD_LOGIC := '0'; + SIGNAL niOO0OO1O : STD_LOGIC := '0'; + SIGNAL niOO0OOii : STD_LOGIC := '0'; + SIGNAL niOO0OOil : STD_LOGIC := '0'; + SIGNAL niOO0OOiO : STD_LOGIC := '0'; + SIGNAL niOO0OOl : STD_LOGIC := '0'; + SIGNAL niOO100i : STD_LOGIC := '0'; + SIGNAL niOO10ii : STD_LOGIC := '0'; + SIGNAL niOO11lO : STD_LOGIC := '0'; + SIGNAL niOO1i0l : STD_LOGIC := '0'; + SIGNAL niOO1ilO : STD_LOGIC := '0'; + SIGNAL niOO1iOO : STD_LOGIC := '0'; + SIGNAL niOO1lOi : STD_LOGIC := '0'; + SIGNAL niOO1O0l : STD_LOGIC := '0'; + SIGNAL niOO1Oil : STD_LOGIC := '0'; + SIGNAL niOOi000i : STD_LOGIC := '0'; + SIGNAL niOOi000l : STD_LOGIC := '0'; + SIGNAL niOOi000O : STD_LOGIC := '0'; + SIGNAL niOOi001i : STD_LOGIC := '0'; + SIGNAL niOOi00ii : STD_LOGIC := '0'; + SIGNAL niOOi00il : STD_LOGIC := '0'; + SIGNAL niOOi00iO : STD_LOGIC := '0'; + SIGNAL niOOi00li : STD_LOGIC := '0'; + SIGNAL niOOi00ll : STD_LOGIC := '0'; + SIGNAL niOOi00lO : STD_LOGIC := '0'; + SIGNAL niOOi00Oi : STD_LOGIC := '0'; + SIGNAL niOOi00Ol : STD_LOGIC := '0'; + SIGNAL niOOi00OO : STD_LOGIC := '0'; + SIGNAL niOOi01iO : STD_LOGIC := '0'; + SIGNAL niOOi01l : STD_LOGIC := '0'; + SIGNAL niOOi0i : STD_LOGIC := '0'; + SIGNAL niOOi0i0i : STD_LOGIC := '0'; + SIGNAL niOOi0i0l : STD_LOGIC := '0'; + SIGNAL niOOi0i1i : STD_LOGIC := '0'; + SIGNAL niOOi0i1l : STD_LOGIC := '0'; + SIGNAL niOOi0i1O : STD_LOGIC := '0'; + SIGNAL niOOi0ii : STD_LOGIC := '0'; + SIGNAL niOOi0iO : STD_LOGIC := '0'; + SIGNAL niOOi0l : STD_LOGIC := '0'; + SIGNAL niOOi0O : STD_LOGIC := '0'; + SIGNAL niOOi11i : STD_LOGIC := '0'; + SIGNAL niOOi1i : STD_LOGIC := '0'; + SIGNAL niOOi1l : STD_LOGIC := '0'; + SIGNAL niOOi1O : STD_LOGIC := '0'; + SIGNAL niOOiii : STD_LOGIC := '0'; + SIGNAL niOOiil : STD_LOGIC := '0'; + SIGNAL niOOiiO : STD_LOGIC := '0'; + SIGNAL niOOili : STD_LOGIC := '0'; + SIGNAL niOOill : STD_LOGIC := '0'; + SIGNAL niOOilO : STD_LOGIC := '0'; + SIGNAL niOOiOi : STD_LOGIC := '0'; + SIGNAL niOOiOl : STD_LOGIC := '0'; + SIGNAL niOOiOO : STD_LOGIC := '0'; + SIGNAL niOOl00i : STD_LOGIC := '0'; + SIGNAL niOOl00l : STD_LOGIC := '0'; + SIGNAL niOOl00O : STD_LOGIC := '0'; + SIGNAL niOOl01i : STD_LOGIC := '0'; + SIGNAL niOOl0i : STD_LOGIC := '0'; + SIGNAL niOOl0ii : STD_LOGIC := '0'; + SIGNAL niOOl0il : STD_LOGIC := '0'; + SIGNAL niOOl0iO : STD_LOGIC := '0'; + SIGNAL niOOl0l : STD_LOGIC := '0'; + SIGNAL niOOl0li : STD_LOGIC := '0'; + SIGNAL niOOl0ll : STD_LOGIC := '0'; + SIGNAL niOOl0lO : STD_LOGIC := '0'; + SIGNAL niOOl0O : STD_LOGIC := '0'; + SIGNAL niOOl0Oi : STD_LOGIC := '0'; + SIGNAL niOOl0Ol : STD_LOGIC := '0'; + SIGNAL niOOl1i : STD_LOGIC := '0'; + SIGNAL niOOl1iO : STD_LOGIC := '0'; + SIGNAL niOOl1l : STD_LOGIC := '0'; + SIGNAL niOOl1O : STD_LOGIC := '0'; + SIGNAL niOOlii : STD_LOGIC := '0'; + SIGNAL niOOlil : STD_LOGIC := '0'; + SIGNAL niOOliO : STD_LOGIC := '0'; + SIGNAL niOOlli : STD_LOGIC := '0'; + SIGNAL niOOlll : STD_LOGIC := '0'; + SIGNAL niOOllO : STD_LOGIC := '0'; + SIGNAL niOOlO1i : STD_LOGIC := '0'; + SIGNAL niOOlOi : STD_LOGIC := '0'; + SIGNAL niOOlOil : STD_LOGIC := '0'; + SIGNAL niOOlOl : STD_LOGIC := '0'; + SIGNAL niOOlOll : STD_LOGIC := '0'; + SIGNAL niOOlOO : STD_LOGIC := '0'; + SIGNAL niOOO0i : STD_LOGIC := '0'; + SIGNAL niOOO0l : STD_LOGIC := '0'; + SIGNAL niOOO1i : STD_LOGIC := '0'; + SIGNAL niOOO1ii : STD_LOGIC := '0'; + SIGNAL niOOO1l : STD_LOGIC := '0'; + SIGNAL niOOO1lO : STD_LOGIC := '0'; + SIGNAL niOOO1O : STD_LOGIC := '0'; + SIGNAL niOOO1Ol : STD_LOGIC := '0'; + SIGNAL niOOOi1l : STD_LOGIC := '0'; + SIGNAL niOOOii : STD_LOGIC := '0'; + SIGNAL niOOOiiO : STD_LOGIC := '0'; + SIGNAL niOOOilO : STD_LOGIC := '0'; + SIGNAL niOOOl0O : STD_LOGIC := '0'; + SIGNAL niOOOliO : STD_LOGIC := '0'; + SIGNAL niOOOllO : STD_LOGIC := '0'; + SIGNAL niOOOlOO : STD_LOGIC := '0'; + SIGNAL niOOOO1O : STD_LOGIC := '0'; + SIGNAL niOOOOli : STD_LOGIC := '0'; + SIGNAL nl00li0i : STD_LOGIC := '0'; + SIGNAL nl00li0l : STD_LOGIC := '0'; + SIGNAL nl00li0O : STD_LOGIC := '0'; + SIGNAL nl00li1l : STD_LOGIC := '0'; + SIGNAL nl00li1O : STD_LOGIC := '0'; + SIGNAL nl00liii : STD_LOGIC := '0'; + SIGNAL nl00liil : STD_LOGIC := '0'; + SIGNAL nl00liiO : STD_LOGIC := '0'; + SIGNAL nl00lili : STD_LOGIC := '0'; + SIGNAL nl00lill : STD_LOGIC := '0'; + SIGNAL nl00lilO : STD_LOGIC := '0'; + SIGNAL nl00liOi : STD_LOGIC := '0'; + SIGNAL nl00liOl : STD_LOGIC := '0'; + SIGNAL nl00liOO : STD_LOGIC := '0'; + SIGNAL nl00ll0i : STD_LOGIC := '0'; + SIGNAL nl00ll0l : STD_LOGIC := '0'; + SIGNAL nl00ll0O : STD_LOGIC := '0'; + SIGNAL nl00ll1i : STD_LOGIC := '0'; + SIGNAL nl00ll1l : STD_LOGIC := '0'; + SIGNAL nl00ll1O : STD_LOGIC := '0'; + SIGNAL nl00llii : STD_LOGIC := '0'; + SIGNAL nl00llil : STD_LOGIC := '0'; + SIGNAL nl00lliO : STD_LOGIC := '0'; + SIGNAL nl00llli : STD_LOGIC := '0'; + SIGNAL nl00llll : STD_LOGIC := '0'; + SIGNAL nl00lllO : STD_LOGIC := '0'; + SIGNAL nl00llOi : STD_LOGIC := '0'; + SIGNAL nl00llOl : STD_LOGIC := '0'; + SIGNAL nl00llOO : STD_LOGIC := '0'; + SIGNAL nl00Ol1O : STD_LOGIC := '0'; + SIGNAL nl00Olil : STD_LOGIC := '0'; + SIGNAL nl00Olli : STD_LOGIC := '0'; + SIGNAL nl01010i : STD_LOGIC := '0'; + SIGNAL nl01010l : STD_LOGIC := '0'; + SIGNAL nl01010O : STD_LOGIC := '0'; + SIGNAL nl01011i : STD_LOGIC := '0'; + SIGNAL nl01011l : STD_LOGIC := '0'; + SIGNAL nl01011O : STD_LOGIC := '0'; + SIGNAL nl0101ii : STD_LOGIC := '0'; + SIGNAL nl0101il : STD_LOGIC := '0'; + SIGNAL nl0101iO : STD_LOGIC := '0'; + SIGNAL nl0101li : STD_LOGIC := '0'; + SIGNAL nl0101ll : STD_LOGIC := '0'; + SIGNAL nl0101lO : STD_LOGIC := '0'; + SIGNAL nl010OOl : STD_LOGIC := '0'; + SIGNAL nl011l0O : STD_LOGIC := '0'; + SIGNAL nl011lOi : STD_LOGIC := '0'; + SIGNAL nl011O0i : STD_LOGIC := '0'; + SIGNAL nl011O0l : STD_LOGIC := '0'; + SIGNAL nl011O0O : STD_LOGIC := '0'; + SIGNAL nl011O1i : STD_LOGIC := '0'; + SIGNAL nl011O1l : STD_LOGIC := '0'; + SIGNAL nl011O1O : STD_LOGIC := '0'; + SIGNAL nl011Oii : STD_LOGIC := '0'; + SIGNAL nl011Oil : STD_LOGIC := '0'; + SIGNAL nl011OiO : STD_LOGIC := '0'; + SIGNAL nl011Oli : STD_LOGIC := '0'; + SIGNAL nl011Oll : STD_LOGIC := '0'; + SIGNAL nl011OlO : STD_LOGIC := '0'; + SIGNAL nl011OOi : STD_LOGIC := '0'; + SIGNAL nl011OOl : STD_LOGIC := '0'; + SIGNAL nl011OOO : STD_LOGIC := '0'; + SIGNAL nl01i0ii : STD_LOGIC := '0'; + SIGNAL nl01i0lO : STD_LOGIC := '0'; + SIGNAL nl01i0Ol : STD_LOGIC := '0'; + SIGNAL nl01i10i : STD_LOGIC := '0'; + SIGNAL nl01i10O : STD_LOGIC := '0'; + SIGNAL nl01iiOi : STD_LOGIC := '0'; + SIGNAL nl01il1l : STD_LOGIC := '0'; + SIGNAL nl01illl : STD_LOGIC := '0'; + SIGNAL nl01li0i : STD_LOGIC := '0'; + SIGNAL nl01li0l : STD_LOGIC := '0'; + SIGNAL nl01li0O : STD_LOGIC := '0'; + SIGNAL nl01li1i : STD_LOGIC := '0'; + SIGNAL nl01li1l : STD_LOGIC := '0'; + SIGNAL nl01li1O : STD_LOGIC := '0'; + SIGNAL nl01liii : STD_LOGIC := '0'; + SIGNAL nl01liil : STD_LOGIC := '0'; + SIGNAL nl01liiO : STD_LOGIC := '0'; + SIGNAL nl01lili : STD_LOGIC := '0'; + SIGNAL nl01lill : STD_LOGIC := '0'; + SIGNAL nl01lilO : STD_LOGIC := '0'; + SIGNAL nl01liOi : STD_LOGIC := '0'; + SIGNAL nl01liOl : STD_LOGIC := '0'; + SIGNAL nl01liOO : STD_LOGIC := '0'; + SIGNAL nl01ll0i : STD_LOGIC := '0'; + SIGNAL nl01ll0l : STD_LOGIC := '0'; + SIGNAL nl01ll0O : STD_LOGIC := '0'; + SIGNAL nl01ll1i : STD_LOGIC := '0'; + SIGNAL nl01ll1l : STD_LOGIC := '0'; + SIGNAL nl01ll1O : STD_LOGIC := '0'; + SIGNAL nl01llii : STD_LOGIC := '0'; + SIGNAL nl01llil : STD_LOGIC := '0'; + SIGNAL nl01lliO : STD_LOGIC := '0'; + SIGNAL nl01llli : STD_LOGIC := '0'; + SIGNAL nl01llll : STD_LOGIC := '0'; + SIGNAL nl01lllO : STD_LOGIC := '0'; + SIGNAL nl01llOi : STD_LOGIC := '0'; + SIGNAL nl01llOl : STD_LOGIC := '0'; + SIGNAL nl01Ol1l : STD_LOGIC := '0'; + SIGNAL nl01Olii : STD_LOGIC := '0'; + SIGNAL nl01OliO : STD_LOGIC := '0'; + SIGNAL nl0il10l : STD_LOGIC := '0'; + SIGNAL nl0il10O : STD_LOGIC := '0'; + SIGNAL nl0il1ii : STD_LOGIC := '0'; + SIGNAL nl0il1il : STD_LOGIC := '0'; + SIGNAL nl0il1iO : STD_LOGIC := '0'; + SIGNAL nl0il1li : STD_LOGIC := '0'; + SIGNAL nl0iliii : STD_LOGIC := '0'; + SIGNAL nl0ilili : STD_LOGIC := '0'; + SIGNAL nl0ilill : STD_LOGIC := '0'; + SIGNAL nl0ililO : STD_LOGIC := '0'; + SIGNAL nl0iliOi : STD_LOGIC := '0'; + SIGNAL nl0iliOl : STD_LOGIC := '0'; + SIGNAL nl0iliOO : STD_LOGIC := '0'; + SIGNAL nl0ill0i : STD_LOGIC := '0'; + SIGNAL nl0ill0l : STD_LOGIC := '0'; + SIGNAL nl0ill0O : STD_LOGIC := '0'; + SIGNAL nl0ill1i : STD_LOGIC := '0'; + SIGNAL nl0ill1l : STD_LOGIC := '0'; + SIGNAL nl0ill1O : STD_LOGIC := '0'; + SIGNAL nl0illii : STD_LOGIC := '0'; + SIGNAL nl0illil : STD_LOGIC := '0'; + SIGNAL nl0illiO : STD_LOGIC := '0'; + SIGNAL nl0illli : STD_LOGIC := '0'; + SIGNAL nl0illll : STD_LOGIC := '0'; + SIGNAL nl0illlO : STD_LOGIC := '0'; + SIGNAL nl0illOi : STD_LOGIC := '0'; + SIGNAL nl0illOl : STD_LOGIC := '0'; + SIGNAL nl0iO0lO : STD_LOGIC := '0'; + SIGNAL nl0iO0Oi : STD_LOGIC := '0'; + SIGNAL nl0iO0Ol : STD_LOGIC := '0'; + SIGNAL nl0iO0OO : STD_LOGIC := '0'; + SIGNAL nl0iOi0i : STD_LOGIC := '0'; + SIGNAL nl0iOi0l : STD_LOGIC := '0'; + SIGNAL nl0iOi0O : STD_LOGIC := '0'; + SIGNAL nl0iOi1i : STD_LOGIC := '0'; + SIGNAL nl0iOi1l : STD_LOGIC := '0'; + SIGNAL nl0iOi1O : STD_LOGIC := '0'; + SIGNAL nl0iOiii : STD_LOGIC := '0'; + SIGNAL nl0iOiil : STD_LOGIC := '0'; + SIGNAL nl0iOiiO : STD_LOGIC := '0'; + SIGNAL nl0iOili : STD_LOGIC := '0'; + SIGNAL nl0iOill : STD_LOGIC := '0'; + SIGNAL nl0iOilO : STD_LOGIC := '0'; + SIGNAL nl0iOiOi : STD_LOGIC := '0'; + SIGNAL nl0iOiOl : STD_LOGIC := '0'; + SIGNAL nl0iOiOO : STD_LOGIC := '0'; + SIGNAL nl0iOl1i : STD_LOGIC := '0'; + SIGNAL nl0iOl1l : STD_LOGIC := '0'; + SIGNAL nl0iOl1O : STD_LOGIC := '0'; + SIGNAL nl0l0i0l : STD_LOGIC := '0'; + SIGNAL nl0l0i0O : STD_LOGIC := '0'; + SIGNAL nl0l0iii : STD_LOGIC := '0'; + SIGNAL nl0l0iil : STD_LOGIC := '0'; + SIGNAL nl0l0iiO : STD_LOGIC := '0'; + SIGNAL nl0l0ili : STD_LOGIC := '0'; + SIGNAL nl0l0OiO : STD_LOGIC := '0'; + SIGNAL nl0l0Oli : STD_LOGIC := '0'; + SIGNAL nl0l0Oll : STD_LOGIC := '0'; + SIGNAL nl0l0OlO : STD_LOGIC := '0'; + SIGNAL nl0l0OOi : STD_LOGIC := '0'; + SIGNAL nl0l0OOl : STD_LOGIC := '0'; + SIGNAL nl0l0OOO : STD_LOGIC := '0'; + SIGNAL nl0li10i : STD_LOGIC := '0'; + SIGNAL nl0li10l : STD_LOGIC := '0'; + SIGNAL nl0li10O : STD_LOGIC := '0'; + SIGNAL nl0li11i : STD_LOGIC := '0'; + SIGNAL nl0li11l : STD_LOGIC := '0'; + SIGNAL nl0li11O : STD_LOGIC := '0'; + SIGNAL nl0li1ii : STD_LOGIC := '0'; + SIGNAL nl0li1il : STD_LOGIC := '0'; + SIGNAL nl0li1iO : STD_LOGIC := '0'; + SIGNAL nl0li1li : STD_LOGIC := '0'; + SIGNAL nl0li1ll : STD_LOGIC := '0'; + SIGNAL nl0li1lO : STD_LOGIC := '0'; + SIGNAL nl0li1Oi : STD_LOGIC := '0'; + SIGNAL nl0lilll : STD_LOGIC := '0'; + SIGNAL nl0lillO : STD_LOGIC := '0'; + SIGNAL nl0lilOi : STD_LOGIC := '0'; + SIGNAL nl0lilOl : STD_LOGIC := '0'; + SIGNAL nl0lilOO : STD_LOGIC := '0'; + SIGNAL nl0liO0i : STD_LOGIC := '0'; + SIGNAL nl0liO0l : STD_LOGIC := '0'; + SIGNAL nl0liO0O : STD_LOGIC := '0'; + SIGNAL nl0liO1i : STD_LOGIC := '0'; + SIGNAL nl0liO1l : STD_LOGIC := '0'; + SIGNAL nl0liO1O : STD_LOGIC := '0'; + SIGNAL nl0liOii : STD_LOGIC := '0'; + SIGNAL nl0liOil : STD_LOGIC := '0'; + SIGNAL nl0liOiO : STD_LOGIC := '0'; + SIGNAL nl0liOli : STD_LOGIC := '0'; + SIGNAL nl0liOll : STD_LOGIC := '0'; + SIGNAL nl0liOlO : STD_LOGIC := '0'; + SIGNAL nl0liOOi : STD_LOGIC := '0'; + SIGNAL nl0liOOl : STD_LOGIC := '0'; + SIGNAL nl0liOOO : STD_LOGIC := '0'; + SIGNAL nl0ll11i : STD_LOGIC := '0'; + SIGNAL nl0ll11l : STD_LOGIC := '0'; + SIGNAL nl0lOOOi : STD_LOGIC := '0'; + SIGNAL nl0lOOOl : STD_LOGIC := '0'; + SIGNAL nl0lOOOO : STD_LOGIC := '0'; + SIGNAL nl0O100i : STD_LOGIC := '0'; + SIGNAL nl0O100l : STD_LOGIC := '0'; + SIGNAL nl0O100O : STD_LOGIC := '0'; + SIGNAL nl0O101i : STD_LOGIC := '0'; + SIGNAL nl0O101l : STD_LOGIC := '0'; + SIGNAL nl0O101O : STD_LOGIC := '0'; + SIGNAL nl0O10ii : STD_LOGIC := '0'; + SIGNAL nl0O10il : STD_LOGIC := '0'; + SIGNAL nl0O10iO : STD_LOGIC := '0'; + SIGNAL nl0O10li : STD_LOGIC := '0'; + SIGNAL nl0O10ll : STD_LOGIC := '0'; + SIGNAL nl0O10lO : STD_LOGIC := '0'; + SIGNAL nl0O10Oi : STD_LOGIC := '0'; + SIGNAL nl0O10Ol : STD_LOGIC := '0'; + SIGNAL nl0O10OO : STD_LOGIC := '0'; + SIGNAL nl0O110i : STD_LOGIC := '0'; + SIGNAL nl0O110l : STD_LOGIC := '0'; + SIGNAL nl0O110O : STD_LOGIC := '0'; + SIGNAL nl0O111i : STD_LOGIC := '0'; + SIGNAL nl0O111l : STD_LOGIC := '0'; + SIGNAL nl0O111O : STD_LOGIC := '0'; + SIGNAL nl0O11ii : STD_LOGIC := '0'; + SIGNAL nl0O11il : STD_LOGIC := '0'; + SIGNAL nl0O11iO : STD_LOGIC := '0'; + SIGNAL nl0O11li : STD_LOGIC := '0'; + SIGNAL nl0O11ll : STD_LOGIC := '0'; + SIGNAL nl0O11lO : STD_LOGIC := '0'; + SIGNAL nl0O11Oi : STD_LOGIC := '0'; + SIGNAL nl0O11Ol : STD_LOGIC := '0'; + SIGNAL nl0O11OO : STD_LOGIC := '0'; + SIGNAL nl0O1i0i : STD_LOGIC := '0'; + SIGNAL nl0O1i0l : STD_LOGIC := '0'; + SIGNAL nl0O1i0O : STD_LOGIC := '0'; + SIGNAL nl0O1i1i : STD_LOGIC := '0'; + SIGNAL nl0O1i1l : STD_LOGIC := '0'; + SIGNAL nl0O1i1O : STD_LOGIC := '0'; + SIGNAL nl0O1iii : STD_LOGIC := '0'; + SIGNAL nl0O1iil : STD_LOGIC := '0'; + SIGNAL nl0O1iiO : STD_LOGIC := '0'; + SIGNAL nl0O1ili : STD_LOGIC := '0'; + SIGNAL nl0O1ill : STD_LOGIC := '0'; + SIGNAL nl0O1ilO : STD_LOGIC := '0'; + SIGNAL nl0O1iOi : STD_LOGIC := '0'; + SIGNAL nl0O1iOl : STD_LOGIC := '0'; + SIGNAL nl0O1iOO : STD_LOGIC := '0'; + SIGNAL nl0O1l0i : STD_LOGIC := '0'; + SIGNAL nl0O1l0l : STD_LOGIC := '0'; + SIGNAL nl0O1l1i : STD_LOGIC := '0'; + SIGNAL nl0O1l1l : STD_LOGIC := '0'; + SIGNAL nl0O1l1O : STD_LOGIC := '0'; + SIGNAL nl0Ol0Ol : STD_LOGIC := '0'; + SIGNAL nl0Ol0OO : STD_LOGIC := '0'; + SIGNAL nl0Oli0i : STD_LOGIC := '0'; + SIGNAL nl0Oli0l : STD_LOGIC := '0'; + SIGNAL nl0Oli0O : STD_LOGIC := '0'; + SIGNAL nl0Oli1i : STD_LOGIC := '0'; + SIGNAL nl0Oli1l : STD_LOGIC := '0'; + SIGNAL nl0Oli1O : STD_LOGIC := '0'; + SIGNAL nl0Oliii : STD_LOGIC := '0'; + SIGNAL nl0Oliil : STD_LOGIC := '0'; + SIGNAL nl0OliiO : STD_LOGIC := '0'; + SIGNAL nl0OlO0O : STD_LOGIC := '0'; + SIGNAL nl0OlOll : STD_LOGIC := '0'; + SIGNAL nl0OlOOi : STD_LOGIC := '0'; + SIGNAL nl0OOl0i : STD_LOGIC := '0'; + SIGNAL nl0OOl0l : STD_LOGIC := '0'; + SIGNAL nl0OOl0O : STD_LOGIC := '0'; + SIGNAL nl0OOl1O : STD_LOGIC := '0'; + SIGNAL nl0OOO0i : STD_LOGIC := '0'; + SIGNAL nl0OOOiO : STD_LOGIC := '0'; + SIGNAL nl0OOOll : STD_LOGIC := '0'; + SIGNAL nl10001i : STD_LOGIC := '0'; + SIGNAL nl1000il : STD_LOGIC := '0'; + SIGNAL nl1000ll : STD_LOGIC := '0'; + SIGNAL nl1000lO : STD_LOGIC := '0'; + SIGNAL nl1000Oi : STD_LOGIC := '0'; + SIGNAL nl1000Ol : STD_LOGIC := '0'; + SIGNAL nl1000OO : STD_LOGIC := '0'; + SIGNAL nl100i0i : STD_LOGIC := '0'; + SIGNAL nl100i1i : STD_LOGIC := '0'; + SIGNAL nl100i1l : STD_LOGIC := '0'; + SIGNAL nl100i1O : STD_LOGIC := '0'; + SIGNAL nl10100O : STD_LOGIC := '0'; + SIGNAL nl10101O : STD_LOGIC := '0'; + SIGNAL nl1011ll : STD_LOGIC := '0'; + SIGNAL nl101i1l : STD_LOGIC := '0'; + SIGNAL nl101iii : STD_LOGIC := '0'; + SIGNAL nl101iiO : STD_LOGIC := '0'; + SIGNAL nl10i00i : STD_LOGIC := '0'; + SIGNAL nl10i01i : STD_LOGIC := '0'; + SIGNAL nl10i01l : STD_LOGIC := '0'; + SIGNAL nl10i01O : STD_LOGIC := '0'; + SIGNAL nl10i10l : STD_LOGIC := '0'; + SIGNAL nl10i1lO : STD_LOGIC := '0'; + SIGNAL nl10i1OO : STD_LOGIC := '0'; + SIGNAL nl10illO : STD_LOGIC := '0'; + SIGNAL nl10iO0i : STD_LOGIC := '0'; + SIGNAL nl10iOii : STD_LOGIC := '0'; + SIGNAL nl10iOil : STD_LOGIC := '0'; + SIGNAL nl10iOiO : STD_LOGIC := '0'; + SIGNAL nl10iOli : STD_LOGIC := '0'; + SIGNAL nl10iOll : STD_LOGIC := '0'; + SIGNAL nl10l01O : STD_LOGIC := '0'; + SIGNAL nl10l1lO : STD_LOGIC := '0'; + SIGNAL nl10l1OO : STD_LOGIC := '0'; + SIGNAL nl10llli : STD_LOGIC := '0'; + SIGNAL nl10lO0l : STD_LOGIC := '0'; + SIGNAL nl10lO0O : STD_LOGIC := '0'; + SIGNAL nl10lO1l : STD_LOGIC := '0'; + SIGNAL nl10lOii : STD_LOGIC := '0'; + SIGNAL nl10lOil : STD_LOGIC := '0'; + SIGNAL nl10lOiO : STD_LOGIC := '0'; + SIGNAL nl10lOli : STD_LOGIC := '0'; + SIGNAL nl10lOll : STD_LOGIC := '0'; + SIGNAL nl10lOlO : STD_LOGIC := '0'; + SIGNAL nl10O00O : STD_LOGIC := '0'; + SIGNAL nl10O01O : STD_LOGIC := '0'; + SIGNAL nl10O0iO : STD_LOGIC := '0'; + SIGNAL nl10O0lO : STD_LOGIC := '0'; + SIGNAL nl10O0OO : STD_LOGIC := '0'; + SIGNAL nl10Oi0O : STD_LOGIC := '0'; + SIGNAL nl10Oi1O : STD_LOGIC := '0'; + SIGNAL nl10OiiO : STD_LOGIC := '0'; + SIGNAL nl11000i : STD_LOGIC := '0'; + SIGNAL nl1100ii : STD_LOGIC := '0'; + SIGNAL nl1101lO : STD_LOGIC := '0'; + SIGNAL nl110i0l : STD_LOGIC := '0'; + SIGNAL nl110ilO : STD_LOGIC := '0'; + SIGNAL nl110iOO : STD_LOGIC := '0'; + SIGNAL nl110lOi : STD_LOGIC := '0'; + SIGNAL nl110O0l : STD_LOGIC := '0'; + SIGNAL nl110Oil : STD_LOGIC := '0'; + SIGNAL nl11101O : STD_LOGIC := '0'; + SIGNAL nl1110li : STD_LOGIC := '0'; + SIGNAL nl1110Oi : STD_LOGIC := '0'; + SIGNAL nl11110l : STD_LOGIC := '0'; + SIGNAL nl11111l : STD_LOGIC := '0'; + SIGNAL nl111ill : STD_LOGIC := '0'; + SIGNAL nl111l0O : STD_LOGIC := '0'; + SIGNAL nl111l1O : STD_LOGIC := '0'; + SIGNAL nl111O1O : STD_LOGIC := '0'; + SIGNAL nl111Oil : STD_LOGIC := '0'; + SIGNAL nl111Oli : STD_LOGIC := '0'; + SIGNAL nl11i01i : STD_LOGIC := '0'; + SIGNAL nl11i0Ol : STD_LOGIC := '0'; + SIGNAL nl11i10O : STD_LOGIC := '0'; + SIGNAL nl11i1Oi : STD_LOGIC := '0'; + SIGNAL nl11ii0O : STD_LOGIC := '0'; + SIGNAL nl11iiiO : STD_LOGIC := '0'; + SIGNAL nl11ilii : STD_LOGIC := '0'; + SIGNAL nl11ilOl : STD_LOGIC := '0'; + SIGNAL nl11iO1l : STD_LOGIC := '0'; + SIGNAL nl11iOOO : STD_LOGIC := '0'; + SIGNAL nl11l0ii : STD_LOGIC := '0'; + SIGNAL nl11l0lO : STD_LOGIC := '0'; + SIGNAL nl11l0Ol : STD_LOGIC := '0'; + SIGNAL nl11l1ii : STD_LOGIC := '0'; + SIGNAL nl11l1li : STD_LOGIC := '0'; + SIGNAL nl11liOO : STD_LOGIC := '0'; + SIGNAL nl11ll0l : STD_LOGIC := '0'; + SIGNAL nl11llii : STD_LOGIC := '0'; + SIGNAL nl11lOil : STD_LOGIC := '0'; + SIGNAL nl11lOOi : STD_LOGIC := '0'; + SIGNAL nl11lOOO : STD_LOGIC := '0'; + SIGNAL nl11O00O : STD_LOGIC := '0'; + SIGNAL nl11O01i : STD_LOGIC := '0'; + SIGNAL nl11O0il : STD_LOGIC := '0'; + SIGNAL nl11OiiO : STD_LOGIC := '0'; + SIGNAL nl11OiOl : STD_LOGIC := '0'; + SIGNAL nl11Ol1i : STD_LOGIC := '0'; + SIGNAL nl11OO0O : STD_LOGIC := '0'; + SIGNAL nl11OO1i : STD_LOGIC := '0'; + SIGNAL nl11OOil : STD_LOGIC := '0'; + SIGNAL nl1i010i : STD_LOGIC := '0'; + SIGNAL nl1i010l : STD_LOGIC := '0'; + SIGNAL nl1i010O : STD_LOGIC := '0'; + SIGNAL nl1i011i : STD_LOGIC := '0'; + SIGNAL nl1i011l : STD_LOGIC := '0'; + SIGNAL nl1i011O : STD_LOGIC := '0'; + SIGNAL nl1i01ii : STD_LOGIC := '0'; + SIGNAL nl1i01il : STD_LOGIC := '0'; + SIGNAL nl1i01iO : STD_LOGIC := '0'; + SIGNAL nl1i01li : STD_LOGIC := '0'; + SIGNAL nl1i01ll : STD_LOGIC := '0'; + SIGNAL nl1i01lO : STD_LOGIC := '0'; + SIGNAL nl1i01Oi : STD_LOGIC := '0'; + SIGNAL nl1i01Ol : STD_LOGIC := '0'; + SIGNAL nl1i01OO : STD_LOGIC := '0'; + SIGNAL nl1i1llO : STD_LOGIC := '0'; + SIGNAL nl1i1O0i : STD_LOGIC := '0'; + SIGNAL nl1i1Oii : STD_LOGIC := '0'; + SIGNAL nl1i1Oil : STD_LOGIC := '0'; + SIGNAL nl1i1OiO : STD_LOGIC := '0'; + SIGNAL nl1i1Oli : STD_LOGIC := '0'; + SIGNAL nl1i1Oll : STD_LOGIC := '0'; + SIGNAL nl1i1OlO : STD_LOGIC := '0'; + SIGNAL nl1i1OOi : STD_LOGIC := '0'; + SIGNAL nl1i1OOl : STD_LOGIC := '0'; + SIGNAL nl1i1OOO : STD_LOGIC := '0'; + SIGNAL nl1ii00i : STD_LOGIC := '0'; + SIGNAL nl1ii00l : STD_LOGIC := '0'; + SIGNAL nl1ii01O : STD_LOGIC := '0'; + SIGNAL nl1ii1il : STD_LOGIC := '0'; + SIGNAL nl1ii1OO : STD_LOGIC := '0'; + SIGNAL nl1iii0i : STD_LOGIC := '0'; + SIGNAL nl1iiiiO : STD_LOGIC := '0'; + SIGNAL nl1iiill : STD_LOGIC := '0'; + SIGNAL nl1iillO : STD_LOGIC := '0'; + SIGNAL nl1iiO0i : STD_LOGIC := '0'; + SIGNAL nl1iiO1l : STD_LOGIC := '0'; + SIGNAL nl1il00i : STD_LOGIC := '0'; + SIGNAL nl1il01l : STD_LOGIC := '0'; + SIGNAL nl1il10l : STD_LOGIC := '0'; + SIGNAL nl1il1lO : STD_LOGIC := '0'; + SIGNAL nl1iO00l : STD_LOGIC := '0'; + SIGNAL nl1iO0il : STD_LOGIC := '0'; + SIGNAL nl1iO0iO : STD_LOGIC := '0'; + SIGNAL nl1iO0li : STD_LOGIC := '0'; + SIGNAL nl1iO0ll : STD_LOGIC := '0'; + SIGNAL nl1iO0lO : STD_LOGIC := '0'; + SIGNAL nl1iO0Oi : STD_LOGIC := '0'; + SIGNAL nl1iO0Ol : STD_LOGIC := '0'; + SIGNAL nl1iO0OO : STD_LOGIC := '0'; + SIGNAL nl1iO1Oi : STD_LOGIC := '0'; + SIGNAL nl1iOi0i : STD_LOGIC := '0'; + SIGNAL nl1iOi0l : STD_LOGIC := '0'; + SIGNAL nl1iOi1i : STD_LOGIC := '0'; + SIGNAL nl1iOi1l : STD_LOGIC := '0'; + SIGNAL nl1iOi1O : STD_LOGIC := '0'; + SIGNAL nl1iOO0O : STD_LOGIC := '0'; + SIGNAL nl1iOOiO : STD_LOGIC := '0'; + SIGNAL nl1iOOlO : STD_LOGIC := '0'; + SIGNAL nl1l000l : STD_LOGIC := '0'; + SIGNAL nl1l00li : STD_LOGIC := '0'; + SIGNAL nl1l00lO : STD_LOGIC := '0'; + SIGNAL nl1l010i : STD_LOGIC := '0'; + SIGNAL nl1l011l : STD_LOGIC := '0'; + SIGNAL nl1l0iOi : STD_LOGIC := '0'; + SIGNAL nl1l0l0l : STD_LOGIC := '0'; + SIGNAL nl1l0l1O : STD_LOGIC := '0'; + SIGNAL nl1l0O1O : STD_LOGIC := '0'; + SIGNAL nl1l0Oii : STD_LOGIC := '0'; + SIGNAL nl1l0OOl : STD_LOGIC := '0'; + SIGNAL nl1l0OOO : STD_LOGIC := '0'; + SIGNAL nl1l10ll : STD_LOGIC := '0'; + SIGNAL nl1l111O : STD_LOGIC := '0'; + SIGNAL nl1l11il : STD_LOGIC := '0'; + SIGNAL nl1l11li : STD_LOGIC := '0'; + SIGNAL nl1l1i1i : STD_LOGIC := '0'; + SIGNAL nl1l1i1O : STD_LOGIC := '0'; + SIGNAL nl1l1l0i : STD_LOGIC := '0'; + SIGNAL nl1l1liO : STD_LOGIC := '0'; + SIGNAL nl1l1lll : STD_LOGIC := '0'; + SIGNAL nl1l1OlO : STD_LOGIC := '0'; + SIGNAL nl1li00i : STD_LOGIC := '0'; + SIGNAL nl1li01l : STD_LOGIC := '0'; + SIGNAL nl1li11i : STD_LOGIC := '0'; + SIGNAL nl1li1lO : STD_LOGIC := '0'; + SIGNAL nl1liiiO : STD_LOGIC := '0'; + SIGNAL nl1lil0i : STD_LOGIC := '0'; + SIGNAL nl1lil0l : STD_LOGIC := '0'; + SIGNAL nl1lil0O : STD_LOGIC := '0'; + SIGNAL nl1lil1O : STD_LOGIC := '0'; + SIGNAL nl1liO0i : STD_LOGIC := '0'; + SIGNAL nl1liOiO : STD_LOGIC := '0'; + SIGNAL nl1liOll : STD_LOGIC := '0'; + SIGNAL nl1ll00l : STD_LOGIC := '0'; + SIGNAL nl1ll0il : STD_LOGIC := '0'; + SIGNAL nl1ll0li : STD_LOGIC := '0'; + SIGNAL nl1llO1i : STD_LOGIC := '0'; + SIGNAL nl1llOil : STD_LOGIC := '0'; + SIGNAL nl1llOOi : STD_LOGIC := '0'; + SIGNAL nl1llOOO : STD_LOGIC := '0'; + SIGNAL nl1lO00l : STD_LOGIC := '0'; + SIGNAL nl1lO00O : STD_LOGIC := '0'; + SIGNAL nl1lO0ii : STD_LOGIC := '0'; + SIGNAL nl1lOi1O : STD_LOGIC := '0'; + SIGNAL nl1lOiil : STD_LOGIC := '0'; + SIGNAL nl1lOili : STD_LOGIC := '0'; + SIGNAL nl1O00ii : STD_LOGIC := '0'; + SIGNAL nl1O00li : STD_LOGIC := '0'; + SIGNAL nl1O01OO : STD_LOGIC := '0'; + SIGNAL nl1O0iil : STD_LOGIC := '0'; + SIGNAL nl1O0iOO : STD_LOGIC := '0'; + SIGNAL nl1O0l1O : STD_LOGIC := '0'; + SIGNAL nl1O0O1i : STD_LOGIC := '0'; + SIGNAL nl1O0Oil : STD_LOGIC := '0'; + SIGNAL nl1O0Oll : STD_LOGIC := '0'; + SIGNAL nl1O1i0O : STD_LOGIC := '0'; + SIGNAL nl1O1iOi : STD_LOGIC := '0'; + SIGNAL nl1O1l0i : STD_LOGIC := '0'; + SIGNAL nl1O1l1i : STD_LOGIC := '0'; + SIGNAL nl1O1l1l : STD_LOGIC := '0'; + SIGNAL nl1O1l1O : STD_LOGIC := '0'; + SIGNAL nl1O1O0l : STD_LOGIC := '0'; + SIGNAL nl1O1Oli : STD_LOGIC := '0'; + SIGNAL nl1O1OlO : STD_LOGIC := '0'; + SIGNAL nl1Oi00i : STD_LOGIC := '0'; + SIGNAL nl1Oi01i : STD_LOGIC := '0'; + SIGNAL nl1Oi0OO : STD_LOGIC := '0'; + SIGNAL nl1Oi1iO : STD_LOGIC := '0'; + SIGNAL nl1Oii0l : STD_LOGIC := '0'; + SIGNAL nl1Oiiii : STD_LOGIC := '0'; + SIGNAL nl1Oilil : STD_LOGIC := '0'; + SIGNAL nl1OilOi : STD_LOGIC := '0'; + SIGNAL nl1OilOO : STD_LOGIC := '0'; + SIGNAL nl1Ol0ll : STD_LOGIC := '0'; + SIGNAL nl1Ol11O : STD_LOGIC := '0'; + SIGNAL nl1Ol1li : STD_LOGIC := '0'; + SIGNAL nl1Ol1Oi : STD_LOGIC := '0'; + SIGNAL nl1Oli0O : STD_LOGIC := '0'; + SIGNAL nl1Oli1O : STD_LOGIC := '0'; + SIGNAL nl1Oll0i : STD_LOGIC := '0'; + SIGNAL nl1Ollll : STD_LOGIC := '0'; + SIGNAL nl1OllOl : STD_LOGIC := '0'; + SIGNAL nl1OlOlO : STD_LOGIC := '0'; + SIGNAL nl1OO10i : STD_LOGIC := '0'; + SIGNAL nl1OO1ii : STD_LOGIC := '0'; + SIGNAL nli0100i : STD_LOGIC := '0'; + SIGNAL nli0100l : STD_LOGIC := '0'; + SIGNAL nli0100O : STD_LOGIC := '0'; + SIGNAL nli0101i : STD_LOGIC := '0'; + SIGNAL nli0101l : STD_LOGIC := '0'; + SIGNAL nli0101O : STD_LOGIC := '0'; + SIGNAL nli010ii : STD_LOGIC := '0'; + SIGNAL nli010il : STD_LOGIC := '0'; + SIGNAL nli010iO : STD_LOGIC := '0'; + SIGNAL nli010li : STD_LOGIC := '0'; + SIGNAL nli010ll : STD_LOGIC := '0'; + SIGNAL nli010lO : STD_LOGIC := '0'; + SIGNAL nli010Oi : STD_LOGIC := '0'; + SIGNAL nli010Ol : STD_LOGIC := '0'; + SIGNAL nli010OO : STD_LOGIC := '0'; + SIGNAL nli0110i : STD_LOGIC := '0'; + SIGNAL nli0110l : STD_LOGIC := '0'; + SIGNAL nli0110O : STD_LOGIC := '0'; + SIGNAL nli0111i : STD_LOGIC := '0'; + SIGNAL nli0111l : STD_LOGIC := '0'; + SIGNAL nli0111O : STD_LOGIC := '0'; + SIGNAL nli011ii : STD_LOGIC := '0'; + SIGNAL nli011il : STD_LOGIC := '0'; + SIGNAL nli011iO : STD_LOGIC := '0'; + SIGNAL nli011li : STD_LOGIC := '0'; + SIGNAL nli011ll : STD_LOGIC := '0'; + SIGNAL nli011lO : STD_LOGIC := '0'; + SIGNAL nli011Oi : STD_LOGIC := '0'; + SIGNAL nli011Ol : STD_LOGIC := '0'; + SIGNAL nli011OO : STD_LOGIC := '0'; + SIGNAL nli01i0i : STD_LOGIC := '0'; + SIGNAL nli01i0l : STD_LOGIC := '0'; + SIGNAL nli01i0O : STD_LOGIC := '0'; + SIGNAL nli01i1i : STD_LOGIC := '0'; + SIGNAL nli01i1l : STD_LOGIC := '0'; + SIGNAL nli01i1O : STD_LOGIC := '0'; + SIGNAL nli01iii : STD_LOGIC := '0'; + SIGNAL nli01iil : STD_LOGIC := '0'; + SIGNAL nli01iiO : STD_LOGIC := '0'; + SIGNAL nli01ili : STD_LOGIC := '0'; + SIGNAL nli01ill : STD_LOGIC := '0'; + SIGNAL nli01ilO : STD_LOGIC := '0'; + SIGNAL nli01iOi : STD_LOGIC := '0'; + SIGNAL nli01iOl : STD_LOGIC := '0'; + SIGNAL nli1001i : STD_LOGIC := '0'; + SIGNAL nli1001l : STD_LOGIC := '0'; + SIGNAL nli1001O : STD_LOGIC := '0'; + SIGNAL nli1010i : STD_LOGIC := '0'; + SIGNAL nli1010l : STD_LOGIC := '0'; + SIGNAL nli1010O : STD_LOGIC := '0'; + SIGNAL nli1011i : STD_LOGIC := '0'; + SIGNAL nli1011l : STD_LOGIC := '0'; + SIGNAL nli1011O : STD_LOGIC := '0'; + SIGNAL nli101ii : STD_LOGIC := '0'; + SIGNAL nli101il : STD_LOGIC := '0'; + SIGNAL nli101iO : STD_LOGIC := '0'; + SIGNAL nli101li : STD_LOGIC := '0'; + SIGNAL nli101ll : STD_LOGIC := '0'; + SIGNAL nli101lO : STD_LOGIC := '0'; + SIGNAL nli101Oi : STD_LOGIC := '0'; + SIGNAL nli101Ol : STD_LOGIC := '0'; + SIGNAL nli101OO : STD_LOGIC := '0'; + SIGNAL nli1100l : STD_LOGIC := '0'; + SIGNAL nli110il : STD_LOGIC := '0'; + SIGNAL nli11l0i : STD_LOGIC := '0'; + SIGNAL nli11l0l : STD_LOGIC := '0'; + SIGNAL nli11l1O : STD_LOGIC := '0'; + SIGNAL nli11O0l : STD_LOGIC := '0'; + SIGNAL nli11Oli : STD_LOGIC := '0'; + SIGNAL nli11Oll : STD_LOGIC := '0'; + SIGNAL nli11OlO : STD_LOGIC := '0'; + SIGNAL nli11OOi : STD_LOGIC := '0'; + SIGNAL nli11OOl : STD_LOGIC := '0'; + SIGNAL nli11OOO : STD_LOGIC := '0'; + SIGNAL nli1l00i : STD_LOGIC := '0'; + SIGNAL nli1l0ii : STD_LOGIC := '0'; + SIGNAL nli1l0Ol : STD_LOGIC := '0'; + SIGNAL nli1l0OO : STD_LOGIC := '0'; + SIGNAL nli1li0i : STD_LOGIC := '0'; + SIGNAL nli1li0l : STD_LOGIC := '0'; + SIGNAL nli1li0O : STD_LOGIC := '0'; + SIGNAL nli1li1i : STD_LOGIC := '0'; + SIGNAL nli1li1l : STD_LOGIC := '0'; + SIGNAL nli1li1O : STD_LOGIC := '0'; + SIGNAL nli1liii : STD_LOGIC := '0'; + SIGNAL nli1liil : STD_LOGIC := '0'; + SIGNAL nli1liiO : STD_LOGIC := '0'; + SIGNAL nli1lili : STD_LOGIC := '0'; + SIGNAL nli1lill : STD_LOGIC := '0'; + SIGNAL nli1lilO : STD_LOGIC := '0'; + SIGNAL nli1liOi : STD_LOGIC := '0'; + SIGNAL nli1liOl : STD_LOGIC := '0'; + SIGNAL nli1liOO : STD_LOGIC := '0'; + SIGNAL nli1ll0i : STD_LOGIC := '0'; + SIGNAL nli1ll0l : STD_LOGIC := '0'; + SIGNAL nli1ll0O : STD_LOGIC := '0'; + SIGNAL nli1ll1i : STD_LOGIC := '0'; + SIGNAL nli1ll1l : STD_LOGIC := '0'; + SIGNAL nli1ll1O : STD_LOGIC := '0'; + SIGNAL nli1llii : STD_LOGIC := '0'; + SIGNAL nli1llil : STD_LOGIC := '0'; + SIGNAL nli1lliO : STD_LOGIC := '0'; + SIGNAL nli1llli : STD_LOGIC := '0'; + SIGNAL nli1llll : STD_LOGIC := '0'; + SIGNAL nli1lllO : STD_LOGIC := '0'; + SIGNAL nli1llOi : STD_LOGIC := '0'; + SIGNAL nli1llOl : STD_LOGIC := '0'; + SIGNAL nli1llOO : STD_LOGIC := '0'; + SIGNAL nli1lO0i : STD_LOGIC := '0'; + SIGNAL nli1lO0l : STD_LOGIC := '0'; + SIGNAL nli1lO0O : STD_LOGIC := '0'; + SIGNAL nli1lO1i : STD_LOGIC := '0'; + SIGNAL nli1lO1l : STD_LOGIC := '0'; + SIGNAL nli1lO1O : STD_LOGIC := '0'; + SIGNAL nli1lOii : STD_LOGIC := '0'; + SIGNAL nli1lOil : STD_LOGIC := '0'; + SIGNAL nli1lOiO : STD_LOGIC := '0'; + SIGNAL nli1lOli : STD_LOGIC := '0'; + SIGNAL nli1lOll : STD_LOGIC := '0'; + SIGNAL nli1lOlO : STD_LOGIC := '0'; + SIGNAL nli1lOOi : STD_LOGIC := '0'; + SIGNAL nli1lOOl : STD_LOGIC := '0'; + SIGNAL nli1lOOO : STD_LOGIC := '0'; + SIGNAL nli1O00i : STD_LOGIC := '0'; + SIGNAL nli1O00l : STD_LOGIC := '0'; + SIGNAL nli1O00O : STD_LOGIC := '0'; + SIGNAL nli1O01i : STD_LOGIC := '0'; + SIGNAL nli1O01l : STD_LOGIC := '0'; + SIGNAL nli1O01O : STD_LOGIC := '0'; + SIGNAL nli1O0ii : STD_LOGIC := '0'; + SIGNAL nli1O0il : STD_LOGIC := '0'; + SIGNAL nli1O0iO : STD_LOGIC := '0'; + SIGNAL nli1O0li : STD_LOGIC := '0'; + SIGNAL nli1O0ll : STD_LOGIC := '0'; + SIGNAL nli1O0lO : STD_LOGIC := '0'; + SIGNAL nli1O0Oi : STD_LOGIC := '0'; + SIGNAL nli1O0Ol : STD_LOGIC := '0'; + SIGNAL nli1O0OO : STD_LOGIC := '0'; + SIGNAL nli1O10i : STD_LOGIC := '0'; + SIGNAL nli1O10l : STD_LOGIC := '0'; + SIGNAL nli1O10O : STD_LOGIC := '0'; + SIGNAL nli1O11i : STD_LOGIC := '0'; + SIGNAL nli1O11l : STD_LOGIC := '0'; + SIGNAL nli1O11O : STD_LOGIC := '0'; + SIGNAL nli1O1ii : STD_LOGIC := '0'; + SIGNAL nli1O1il : STD_LOGIC := '0'; + SIGNAL nli1O1iO : STD_LOGIC := '0'; + SIGNAL nli1O1li : STD_LOGIC := '0'; + SIGNAL nli1O1ll : STD_LOGIC := '0'; + SIGNAL nli1O1lO : STD_LOGIC := '0'; + SIGNAL nli1O1Oi : STD_LOGIC := '0'; + SIGNAL nli1O1Ol : STD_LOGIC := '0'; + SIGNAL nli1O1OO : STD_LOGIC := '0'; + SIGNAL nli1Oi0i : STD_LOGIC := '0'; + SIGNAL nli1Oi0l : STD_LOGIC := '0'; + SIGNAL nli1Oi0O : STD_LOGIC := '0'; + SIGNAL nli1Oi1i : STD_LOGIC := '0'; + SIGNAL nli1Oi1l : STD_LOGIC := '0'; + SIGNAL nli1Oi1O : STD_LOGIC := '0'; + SIGNAL nli1Oiii : STD_LOGIC := '0'; + SIGNAL nli1Oiil : STD_LOGIC := '0'; + SIGNAL nli1OiiO : STD_LOGIC := '0'; + SIGNAL nli1Oili : STD_LOGIC := '0'; + SIGNAL nli1Oill : STD_LOGIC := '0'; + SIGNAL nli1OilO : STD_LOGIC := '0'; + SIGNAL nli1OiOi : STD_LOGIC := '0'; + SIGNAL nli1OiOl : STD_LOGIC := '0'; + SIGNAL nli1OiOO : STD_LOGIC := '0'; + SIGNAL nli1Ol0i : STD_LOGIC := '0'; + SIGNAL nli1Ol0l : STD_LOGIC := '0'; + SIGNAL nli1Ol0O : STD_LOGIC := '0'; + SIGNAL nli1Ol1i : STD_LOGIC := '0'; + SIGNAL nli1Ol1l : STD_LOGIC := '0'; + SIGNAL nli1Ol1O : STD_LOGIC := '0'; + SIGNAL nli1Olii : STD_LOGIC := '0'; + SIGNAL nli1Olil : STD_LOGIC := '0'; + SIGNAL nli1OliO : STD_LOGIC := '0'; + SIGNAL nli1Olli : STD_LOGIC := '0'; + SIGNAL nli1Olll : STD_LOGIC := '0'; + SIGNAL nli1OllO : STD_LOGIC := '0'; + SIGNAL nli1OlOi : STD_LOGIC := '0'; + SIGNAL nli1OlOl : STD_LOGIC := '0'; + SIGNAL nli1OlOO : STD_LOGIC := '0'; + SIGNAL nli1OO0i : STD_LOGIC := '0'; + SIGNAL nli1OO0l : STD_LOGIC := '0'; + SIGNAL nli1OO0O : STD_LOGIC := '0'; + SIGNAL nli1OO1i : STD_LOGIC := '0'; + SIGNAL nli1OO1l : STD_LOGIC := '0'; + SIGNAL nli1OO1O : STD_LOGIC := '0'; + SIGNAL nli1OOii : STD_LOGIC := '0'; + SIGNAL nli1OOil : STD_LOGIC := '0'; + SIGNAL nli1OOiO : STD_LOGIC := '0'; + SIGNAL nli1OOli : STD_LOGIC := '0'; + SIGNAL nli1OOll : STD_LOGIC := '0'; + SIGNAL nli1OOlO : STD_LOGIC := '0'; + SIGNAL nli1OOOi : STD_LOGIC := '0'; + SIGNAL nli1OOOl : STD_LOGIC := '0'; + SIGNAL nli1OOOO : STD_LOGIC := '0'; + SIGNAL nlll0lll : STD_LOGIC := '0'; + SIGNAL nllll0ll : STD_LOGIC := '0'; + SIGNAL nlllli0i : STD_LOGIC := '0'; + SIGNAL nlllli0l : STD_LOGIC := '0'; + SIGNAL nlllli0O : STD_LOGIC := '0'; + SIGNAL nlllli1i : STD_LOGIC := '0'; + SIGNAL nlllli1l : STD_LOGIC := '0'; + SIGNAL nlllli1O : STD_LOGIC := '0'; + SIGNAL nlllliii : STD_LOGIC := '0'; + SIGNAL nlllliil : STD_LOGIC := '0'; + SIGNAL nlllliiO : STD_LOGIC := '0'; + SIGNAL nllllili : STD_LOGIC := '0'; + SIGNAL nllllill : STD_LOGIC := '0'; + SIGNAL nllllilO : STD_LOGIC := '0'; + SIGNAL nlllliOi : STD_LOGIC := '0'; + SIGNAL nlllll0l : STD_LOGIC := '0'; + SIGNAL nlllll0O : STD_LOGIC := '0'; + SIGNAL nlllll1i : STD_LOGIC := '0'; + SIGNAL nlllll1l : STD_LOGIC := '0'; + SIGNAL nlllllii : STD_LOGIC := '0'; + SIGNAL nlllllil : STD_LOGIC := '0'; + SIGNAL nllllliO : STD_LOGIC := '0'; + SIGNAL nlllllli : STD_LOGIC := '0'; + SIGNAL nlllllll : STD_LOGIC := '0'; + SIGNAL wire_niOOO0O_CLRN : STD_LOGIC; + SIGNAL wire_niOOO0O_PRN : STD_LOGIC; + SIGNAL wire_niOOO0O_w6168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_w_lg_w_lg_w_lg_nli101OO6158w6159w6162w6165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_w_lg_w_lg_nli101OO6158w6159w6162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_w_lg_ni0O01O2320w2321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nli11l0l6184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_w_lg_nli1001i6160w6161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_w_lg_nli1001l6163w6164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_w_lg_nli1001O6166w6167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_w_lg_nli101OO6158w6159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_ni0O01O2320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_ni0O1li2322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOiilll8581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOlOl0i8541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOlOOll8534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOO00iO8496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOO0OlOO61845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOO100i8526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOO1ilO8518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOO1O0l8510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOOi001i61782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOOl01i8434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOOlOil8416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_niOOOiiO8402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl011lOi7598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0il1li6950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ilili6952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ilill6954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ililO6956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0iliOi6958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0iliOl6960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0iliOO6962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ill0i6970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ill0l6972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ill0O6916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ill1i6964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ill1l6966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ill1O6968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illii6918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illil6920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illiO6922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illli6924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illll6926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illlO6928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illOi6930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0illOl7062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0iO0lO6992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0ili6630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0OiO6632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0Oli6634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0Oll6636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0OlO6638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0OOi6640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0OOl6642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0l0OOO6644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li10i6652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li10l6596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li10O6598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li11i6646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li11l6648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li11O6650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li1ii6600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li1il6602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li1iO6604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li1li6606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li1ll6608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li1lO6610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0li1Oi6742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0lilll6672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0ll11l7200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0lOOOi7198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0lOOOl7196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0lOOOO7194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O100i7211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O100O7209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O101i7141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O101l7214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O101O7212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O10iO7177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O10li7175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O10ll7173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O10lO7171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O10Oi7169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O10Ol7167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O10OO7165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O110i7186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O110l7184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O110O7182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O111i7192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O111l7190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O111O7188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11ii7180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11il7179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11iO7154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11li7152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11ll7150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11lO7148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11Oi7146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11Ol7144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O11OO7142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1i0i7157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1i0l7156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1i0O7139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1i1i7163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1i1l7161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1i1O7159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1iii7137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1iil7135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1iiO7133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1ili7131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1ill7129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1ilO7127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1iOi7126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1iOl7207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1iOO7205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1l1i7204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl0O1l1O7202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1000il8223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl10101O8261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl10i1lO8203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl10iO0i8178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl10lO1l8144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11000i8359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl110ilO8351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl110O0l8343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1110li8382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11111l8390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl111l1O8374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl111O1O8370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11i1Oi8335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11ii0O8327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11ilOl8319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11l0ii8307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11l1ii8311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11liOO8300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11lOil8293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11O01i8286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl11OiiO8279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1i1O0i8059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1ii1OO8021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1iO00l7949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1O00ii7754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1O0iOO7746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1O0Oil7738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1O1iOi7772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1Oi01i7730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1Ol1li7708w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1Oli1O7700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1Ollll7692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nl1OO10i7684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nli1001O6123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nli11O0l6157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nlllliiO546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nlllliOi4573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nli1001i6160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nli1001l6163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nli1001O6166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niOOO0O_w_lg_nli101OO6158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1illl1i : STD_LOGIC := '0'; + SIGNAL n1illOil : STD_LOGIC := '0'; + SIGNAL n1l000i : STD_LOGIC := '0'; + SIGNAL n1l000l : STD_LOGIC := '0'; + SIGNAL n1l000O : STD_LOGIC := '0'; + SIGNAL n1l001i : STD_LOGIC := '0'; + SIGNAL n1l001l : STD_LOGIC := '0'; + SIGNAL n1l001O : STD_LOGIC := '0'; + SIGNAL n1l00ii : STD_LOGIC := '0'; + SIGNAL n1l010i : STD_LOGIC := '0'; + SIGNAL n1l010l : STD_LOGIC := '0'; + SIGNAL n1l010O : STD_LOGIC := '0'; + SIGNAL n1l011i : STD_LOGIC := '0'; + SIGNAL n1l011l : STD_LOGIC := '0'; + SIGNAL n1l01ii : STD_LOGIC := '0'; + SIGNAL n1l01il : STD_LOGIC := '0'; + SIGNAL n1l01iO : STD_LOGIC := '0'; + SIGNAL n1l01li : STD_LOGIC := '0'; + SIGNAL n1l01ll : STD_LOGIC := '0'; + SIGNAL n1l01lO : STD_LOGIC := '0'; + SIGNAL n1l01Oi : STD_LOGIC := '0'; + SIGNAL n1l01Ol : STD_LOGIC := '0'; + SIGNAL n1l01OO : STD_LOGIC := '0'; + SIGNAL ni0000i : STD_LOGIC := '0'; + SIGNAL ni0000l : STD_LOGIC := '0'; + SIGNAL ni0000O : STD_LOGIC := '0'; + SIGNAL ni0001i : STD_LOGIC := '0'; + SIGNAL ni0001l : STD_LOGIC := '0'; + SIGNAL ni0001O : STD_LOGIC := '0'; + SIGNAL ni000ii : STD_LOGIC := '0'; + SIGNAL ni000il : STD_LOGIC := '0'; + SIGNAL ni000iO : STD_LOGIC := '0'; + SIGNAL ni000li : STD_LOGIC := '0'; + SIGNAL ni000ll : STD_LOGIC := '0'; + SIGNAL ni000lO : STD_LOGIC := '0'; + SIGNAL ni000Oi : STD_LOGIC := '0'; + SIGNAL ni000Ol : STD_LOGIC := '0'; + SIGNAL ni000OO : STD_LOGIC := '0'; + SIGNAL ni001Ol : STD_LOGIC := '0'; + SIGNAL ni001OO : STD_LOGIC := '0'; + SIGNAL ni00i0i : STD_LOGIC := '0'; + SIGNAL ni00i0l : STD_LOGIC := '0'; + SIGNAL ni00i0O : STD_LOGIC := '0'; + SIGNAL ni00i1i : STD_LOGIC := '0'; + SIGNAL ni00i1l : STD_LOGIC := '0'; + SIGNAL ni00i1O : STD_LOGIC := '0'; + SIGNAL ni00iii : STD_LOGIC := '0'; + SIGNAL ni00iil : STD_LOGIC := '0'; + SIGNAL ni00iiO : STD_LOGIC := '0'; + SIGNAL ni00ili : STD_LOGIC := '0'; + SIGNAL ni00ill : STD_LOGIC := '0'; + SIGNAL ni00ilO : STD_LOGIC := '0'; + SIGNAL ni0i0OO : STD_LOGIC := '0'; + SIGNAL ni0l00i : STD_LOGIC := '0'; + SIGNAL ni0l00l : STD_LOGIC := '0'; + SIGNAL ni0l00O : STD_LOGIC := '0'; + SIGNAL ni0l0ii : STD_LOGIC := '0'; + SIGNAL ni0l0il : STD_LOGIC := '0'; + SIGNAL ni0liOi : STD_LOGIC := '0'; + SIGNAL ni0llil : STD_LOGIC := '0'; + SIGNAL ni0lliO : STD_LOGIC := '0'; + SIGNAL ni0llli : STD_LOGIC := '0'; + SIGNAL ni0llll : STD_LOGIC := '0'; + SIGNAL ni0lllO : STD_LOGIC := '0'; + SIGNAL ni0llOi : STD_LOGIC := '0'; + SIGNAL ni0llOl : STD_LOGIC := '0'; + SIGNAL ni0llOO : STD_LOGIC := '0'; + SIGNAL ni0lO1i : STD_LOGIC := '0'; + SIGNAL ni0lO1l : STD_LOGIC := '0'; + SIGNAL ni0O1iO : STD_LOGIC := '0'; + SIGNAL ni0Ol0O : STD_LOGIC := '0'; + SIGNAL nii000i : STD_LOGIC := '0'; + SIGNAL nii000l : STD_LOGIC := '0'; + SIGNAL nii000O : STD_LOGIC := '0'; + SIGNAL nii001i : STD_LOGIC := '0'; + SIGNAL nii001l : STD_LOGIC := '0'; + SIGNAL nii001O : STD_LOGIC := '0'; + SIGNAL nii00ii : STD_LOGIC := '0'; + SIGNAL nii00il : STD_LOGIC := '0'; + SIGNAL nii00iO : STD_LOGIC := '0'; + SIGNAL nii00li : STD_LOGIC := '0'; + SIGNAL nii00ll : STD_LOGIC := '0'; + SIGNAL nii00lO : STD_LOGIC := '0'; + SIGNAL nii00Oi : STD_LOGIC := '0'; + SIGNAL nii00Ol : STD_LOGIC := '0'; + SIGNAL nii00OO : STD_LOGIC := '0'; + SIGNAL nii010i : STD_LOGIC := '0'; + SIGNAL nii010l : STD_LOGIC := '0'; + SIGNAL nii010O : STD_LOGIC := '0'; + SIGNAL nii011i : STD_LOGIC := '0'; + SIGNAL nii011l : STD_LOGIC := '0'; + SIGNAL nii011O : STD_LOGIC := '0'; + SIGNAL nii01ii : STD_LOGIC := '0'; + SIGNAL nii01il : STD_LOGIC := '0'; + SIGNAL nii01iO : STD_LOGIC := '0'; + SIGNAL nii01li : STD_LOGIC := '0'; + SIGNAL nii01ll : STD_LOGIC := '0'; + SIGNAL nii01lO : STD_LOGIC := '0'; + SIGNAL nii01Oi : STD_LOGIC := '0'; + SIGNAL nii01Ol : STD_LOGIC := '0'; + SIGNAL nii01OO : STD_LOGIC := '0'; + SIGNAL nii0i0i : STD_LOGIC := '0'; + SIGNAL nii0i0l : STD_LOGIC := '0'; + SIGNAL nii0i0O : STD_LOGIC := '0'; + SIGNAL nii0i1i : STD_LOGIC := '0'; + SIGNAL nii0i1l : STD_LOGIC := '0'; + SIGNAL nii0i1O : STD_LOGIC := '0'; + SIGNAL nii0iii : STD_LOGIC := '0'; + SIGNAL nii0iil : STD_LOGIC := '0'; + SIGNAL nii0iiO : STD_LOGIC := '0'; + SIGNAL nii0ili : STD_LOGIC := '0'; + SIGNAL nii0ill : STD_LOGIC := '0'; + SIGNAL nii0ilO : STD_LOGIC := '0'; + SIGNAL nii0iOi : STD_LOGIC := '0'; + SIGNAL nii0iOl : STD_LOGIC := '0'; + SIGNAL nii0iOO : STD_LOGIC := '0'; + SIGNAL nii0l0i : STD_LOGIC := '0'; + SIGNAL nii0l0l : STD_LOGIC := '0'; + SIGNAL nii0l0O : STD_LOGIC := '0'; + SIGNAL nii0l1i : STD_LOGIC := '0'; + SIGNAL nii0l1l : STD_LOGIC := '0'; + SIGNAL nii0l1O : STD_LOGIC := '0'; + SIGNAL nii0lii : STD_LOGIC := '0'; + SIGNAL nii0lil : STD_LOGIC := '0'; + SIGNAL nii0liO : STD_LOGIC := '0'; + SIGNAL nii0lli : STD_LOGIC := '0'; + SIGNAL nii0lll : STD_LOGIC := '0'; + SIGNAL nii0llO : STD_LOGIC := '0'; + SIGNAL nii0lOi : STD_LOGIC := '0'; + SIGNAL nii0lOl : STD_LOGIC := '0'; + SIGNAL nii0lOO : STD_LOGIC := '0'; + SIGNAL nii0O0i : STD_LOGIC := '0'; + SIGNAL nii0O0l : STD_LOGIC := '0'; + SIGNAL nii0O0O : STD_LOGIC := '0'; + SIGNAL nii0O1i : STD_LOGIC := '0'; + SIGNAL nii0O1l : STD_LOGIC := '0'; + SIGNAL nii0O1O : STD_LOGIC := '0'; + SIGNAL nii0Oii : STD_LOGIC := '0'; + SIGNAL nii0Oil : STD_LOGIC := '0'; + SIGNAL nii0OiO : STD_LOGIC := '0'; + SIGNAL nii0Oli : STD_LOGIC := '0'; + SIGNAL nii0Oll : STD_LOGIC := '0'; + SIGNAL nii0OlO : STD_LOGIC := '0'; + SIGNAL nii0OOi : STD_LOGIC := '0'; + SIGNAL nii0OOl : STD_LOGIC := '0'; + SIGNAL nii0OOO : STD_LOGIC := '0'; + SIGNAL nii1l0l : STD_LOGIC := '0'; + SIGNAL nii1l0O : STD_LOGIC := '0'; + SIGNAL nii1lii : STD_LOGIC := '0'; + SIGNAL nii1lil : STD_LOGIC := '0'; + SIGNAL nii1liO : STD_LOGIC := '0'; + SIGNAL nii1lli : STD_LOGIC := '0'; + SIGNAL nii1lll : STD_LOGIC := '0'; + SIGNAL nii1llO : STD_LOGIC := '0'; + SIGNAL nii1lOi : STD_LOGIC := '0'; + SIGNAL nii1lOl : STD_LOGIC := '0'; + SIGNAL nii1lOO : STD_LOGIC := '0'; + SIGNAL nii1O0i : STD_LOGIC := '0'; + SIGNAL nii1O0l : STD_LOGIC := '0'; + SIGNAL nii1O0O : STD_LOGIC := '0'; + SIGNAL nii1O1i : STD_LOGIC := '0'; + SIGNAL nii1O1l : STD_LOGIC := '0'; + SIGNAL nii1O1O : STD_LOGIC := '0'; + SIGNAL nii1Oii : STD_LOGIC := '0'; + SIGNAL nii1Oil : STD_LOGIC := '0'; + SIGNAL nii1OiO : STD_LOGIC := '0'; + SIGNAL nii1Oli : STD_LOGIC := '0'; + SIGNAL nii1Oll : STD_LOGIC := '0'; + SIGNAL nii1OlO : STD_LOGIC := '0'; + SIGNAL nii1OOi : STD_LOGIC := '0'; + SIGNAL nii1OOl : STD_LOGIC := '0'; + SIGNAL nii1OOO : STD_LOGIC := '0'; + SIGNAL niii00i : STD_LOGIC := '0'; + SIGNAL niii00l : STD_LOGIC := '0'; + SIGNAL niii00O : STD_LOGIC := '0'; + SIGNAL niii01i : STD_LOGIC := '0'; + SIGNAL niii01l : STD_LOGIC := '0'; + SIGNAL niii01O : STD_LOGIC := '0'; + SIGNAL niii0ii : STD_LOGIC := '0'; + SIGNAL niii0il : STD_LOGIC := '0'; + SIGNAL niii0iO : STD_LOGIC := '0'; + SIGNAL niii0li : STD_LOGIC := '0'; + SIGNAL niii0ll : STD_LOGIC := '0'; + SIGNAL niii0lO : STD_LOGIC := '0'; + SIGNAL niii0Oi : STD_LOGIC := '0'; + SIGNAL niii0Ol : STD_LOGIC := '0'; + SIGNAL niii0OO : STD_LOGIC := '0'; + SIGNAL niii10i : STD_LOGIC := '0'; + SIGNAL niii10l : STD_LOGIC := '0'; + SIGNAL niii10O : STD_LOGIC := '0'; + SIGNAL niii11i : STD_LOGIC := '0'; + SIGNAL niii11l : STD_LOGIC := '0'; + SIGNAL niii11O : STD_LOGIC := '0'; + SIGNAL niii1ii : STD_LOGIC := '0'; + SIGNAL niii1il : STD_LOGIC := '0'; + SIGNAL niii1iO : STD_LOGIC := '0'; + SIGNAL niii1li : STD_LOGIC := '0'; + SIGNAL niii1ll : STD_LOGIC := '0'; + SIGNAL niii1lO : STD_LOGIC := '0'; + SIGNAL niii1Oi : STD_LOGIC := '0'; + SIGNAL niii1Ol : STD_LOGIC := '0'; + SIGNAL niii1OO : STD_LOGIC := '0'; + SIGNAL niiii0i : STD_LOGIC := '0'; + SIGNAL niiii0l : STD_LOGIC := '0'; + SIGNAL niiii0O : STD_LOGIC := '0'; + SIGNAL niiii1i : STD_LOGIC := '0'; + SIGNAL niiii1l : STD_LOGIC := '0'; + SIGNAL niiii1O : STD_LOGIC := '0'; + SIGNAL niiiiii : STD_LOGIC := '0'; + SIGNAL niiiiil : STD_LOGIC := '0'; + SIGNAL niiiiiO : STD_LOGIC := '0'; + SIGNAL niiiili : STD_LOGIC := '0'; + SIGNAL niiiill : STD_LOGIC := '0'; + SIGNAL niiiilO : STD_LOGIC := '0'; + SIGNAL niiiiOi : STD_LOGIC := '0'; + SIGNAL niiiiOl : STD_LOGIC := '0'; + SIGNAL niiiiOO : STD_LOGIC := '0'; + SIGNAL niiil0i : STD_LOGIC := '0'; + SIGNAL niiil0l : STD_LOGIC := '0'; + SIGNAL niiil0O : STD_LOGIC := '0'; + SIGNAL niiil1i : STD_LOGIC := '0'; + SIGNAL niiil1l : STD_LOGIC := '0'; + SIGNAL niiil1O : STD_LOGIC := '0'; + SIGNAL niiilii : STD_LOGIC := '0'; + SIGNAL niiilil : STD_LOGIC := '0'; + SIGNAL niiiliO : STD_LOGIC := '0'; + SIGNAL niiilli : STD_LOGIC := '0'; + SIGNAL niiilll : STD_LOGIC := '0'; + SIGNAL niiillO : STD_LOGIC := '0'; + SIGNAL niiilOi : STD_LOGIC := '0'; + SIGNAL niiilOl : STD_LOGIC := '0'; + SIGNAL niiilOO : STD_LOGIC := '0'; + SIGNAL niiiO0i : STD_LOGIC := '0'; + SIGNAL niiiO0l : STD_LOGIC := '0'; + SIGNAL niiiO0O : STD_LOGIC := '0'; + SIGNAL niiiO1i : STD_LOGIC := '0'; + SIGNAL niiiO1l : STD_LOGIC := '0'; + SIGNAL niiiO1O : STD_LOGIC := '0'; + SIGNAL niiiOii : STD_LOGIC := '0'; + SIGNAL niiiOil : STD_LOGIC := '0'; + SIGNAL niiiOiO : STD_LOGIC := '0'; + SIGNAL niiiOli : STD_LOGIC := '0'; + SIGNAL niiiOll : STD_LOGIC := '0'; + SIGNAL niiiOlO : STD_LOGIC := '0'; + SIGNAL niiiOOi : STD_LOGIC := '0'; + SIGNAL niiiOOl : STD_LOGIC := '0'; + SIGNAL niiiOOO : STD_LOGIC := '0'; + SIGNAL niO0000i : STD_LOGIC := '0'; + SIGNAL niO0000l : STD_LOGIC := '0'; + SIGNAL niO0000O : STD_LOGIC := '0'; + SIGNAL niO0001i : STD_LOGIC := '0'; + SIGNAL niO0001l : STD_LOGIC := '0'; + SIGNAL niO0001O : STD_LOGIC := '0'; + SIGNAL niO000ii : STD_LOGIC := '0'; + SIGNAL niO000il : STD_LOGIC := '0'; + SIGNAL niO000iO : STD_LOGIC := '0'; + SIGNAL niO000li : STD_LOGIC := '0'; + SIGNAL niO000ll : STD_LOGIC := '0'; + SIGNAL niO000lO : STD_LOGIC := '0'; + SIGNAL niO000Oi : STD_LOGIC := '0'; + SIGNAL niO000Ol : STD_LOGIC := '0'; + SIGNAL niO000OO : STD_LOGIC := '0'; + SIGNAL niO001Oi : STD_LOGIC := '0'; + SIGNAL niO001Ol : STD_LOGIC := '0'; + SIGNAL niO001OO : STD_LOGIC := '0'; + SIGNAL niO00i0i : STD_LOGIC := '0'; + SIGNAL niO00i0l : STD_LOGIC := '0'; + SIGNAL niO00i0O : STD_LOGIC := '0'; + SIGNAL niO00i1i : STD_LOGIC := '0'; + SIGNAL niO00i1l : STD_LOGIC := '0'; + SIGNAL niO00i1O : STD_LOGIC := '0'; + SIGNAL niO00iii : STD_LOGIC := '0'; + SIGNAL niO00iil : STD_LOGIC := '0'; + SIGNAL niO00iiO : STD_LOGIC := '0'; + SIGNAL niO00ili : STD_LOGIC := '0'; + SIGNAL niO00ill : STD_LOGIC := '0'; + SIGNAL niO00ilO : STD_LOGIC := '0'; + SIGNAL niO00iOi : STD_LOGIC := '0'; + SIGNAL niO00iOl : STD_LOGIC := '0'; + SIGNAL niO00iOO : STD_LOGIC := '0'; + SIGNAL niO00l0i : STD_LOGIC := '0'; + SIGNAL niO00l0l : STD_LOGIC := '0'; + SIGNAL niO00l0O : STD_LOGIC := '0'; + SIGNAL niO00l1i : STD_LOGIC := '0'; + SIGNAL niO00l1l : STD_LOGIC := '0'; + SIGNAL niO00l1O : STD_LOGIC := '0'; + SIGNAL niO00lii : STD_LOGIC := '0'; + SIGNAL niO00lil : STD_LOGIC := '0'; + SIGNAL niO00liO : STD_LOGIC := '0'; + SIGNAL niO00lli : STD_LOGIC := '0'; + SIGNAL niO00lll : STD_LOGIC := '0'; + SIGNAL niO00llO : STD_LOGIC := '0'; + SIGNAL niO00lOi : STD_LOGIC := '0'; + SIGNAL niO00lOl : STD_LOGIC := '0'; + SIGNAL niO00lOO : STD_LOGIC := '0'; + SIGNAL niO00O0i : STD_LOGIC := '0'; + SIGNAL niO00O0l : STD_LOGIC := '0'; + SIGNAL niO00O0O : STD_LOGIC := '0'; + SIGNAL niO00O1i : STD_LOGIC := '0'; + SIGNAL niO00O1l : STD_LOGIC := '0'; + SIGNAL niO00O1O : STD_LOGIC := '0'; + SIGNAL niO0l0li : STD_LOGIC := '0'; + SIGNAL niO0l0ll : STD_LOGIC := '0'; + SIGNAL niO0l0lO : STD_LOGIC := '0'; + SIGNAL niO0l0Oi : STD_LOGIC := '0'; + SIGNAL niO0liil : STD_LOGIC := '0'; + SIGNAL niO0liiO : STD_LOGIC := '0'; + SIGNAL niO0lili : STD_LOGIC := '0'; + SIGNAL niO0lill : STD_LOGIC := '0'; + SIGNAL niO0lilO : STD_LOGIC := '0'; + SIGNAL niO0liOi : STD_LOGIC := '0'; + SIGNAL niO0liOl : STD_LOGIC := '0'; + SIGNAL niO0liOO : STD_LOGIC := '0'; + SIGNAL niO0ll0i : STD_LOGIC := '0'; + SIGNAL niO0ll0l : STD_LOGIC := '0'; + SIGNAL niO0ll0O : STD_LOGIC := '0'; + SIGNAL niO0ll1i : STD_LOGIC := '0'; + SIGNAL niO0ll1l : STD_LOGIC := '0'; + SIGNAL niO0ll1O : STD_LOGIC := '0'; + SIGNAL niO0llii : STD_LOGIC := '0'; + SIGNAL niO0llil : STD_LOGIC := '0'; + SIGNAL niO0lliO : STD_LOGIC := '0'; + SIGNAL niO0llli : STD_LOGIC := '0'; + SIGNAL niO0llll : STD_LOGIC := '0'; + SIGNAL niO0lllO : STD_LOGIC := '0'; + SIGNAL niO0llOi : STD_LOGIC := '0'; + SIGNAL niO0llOl : STD_LOGIC := '0'; + SIGNAL niO0llOO : STD_LOGIC := '0'; + SIGNAL niO0lO0i : STD_LOGIC := '0'; + SIGNAL niO0lO0l : STD_LOGIC := '0'; + SIGNAL niO0lO0O : STD_LOGIC := '0'; + SIGNAL niO0lO1i : STD_LOGIC := '0'; + SIGNAL niO0lO1l : STD_LOGIC := '0'; + SIGNAL niO0lO1O : STD_LOGIC := '0'; + SIGNAL niO0lOii : STD_LOGIC := '0'; + SIGNAL niO0lOil : STD_LOGIC := '0'; + SIGNAL niO0lOiO : STD_LOGIC := '0'; + SIGNAL niO0lOli : STD_LOGIC := '0'; + SIGNAL niO0lOll : STD_LOGIC := '0'; + SIGNAL niO0lOlO : STD_LOGIC := '0'; + SIGNAL niO0lOOi : STD_LOGIC := '0'; + SIGNAL niO0lOOl : STD_LOGIC := '0'; + SIGNAL niO0OOOl : STD_LOGIC := '0'; + SIGNAL niO0OOOO : STD_LOGIC := '0'; + SIGNAL niOi000i : STD_LOGIC := '0'; + SIGNAL niOi000l : STD_LOGIC := '0'; + SIGNAL niOi000O : STD_LOGIC := '0'; + SIGNAL niOi001i : STD_LOGIC := '0'; + SIGNAL niOi001l : STD_LOGIC := '0'; + SIGNAL niOi001O : STD_LOGIC := '0'; + SIGNAL niOi00i : STD_LOGIC := '0'; + SIGNAL niOi00ii : STD_LOGIC := '0'; + SIGNAL niOi00il : STD_LOGIC := '0'; + SIGNAL niOi00iO : STD_LOGIC := '0'; + SIGNAL niOi00l : STD_LOGIC := '0'; + SIGNAL niOi00li : STD_LOGIC := '0'; + SIGNAL niOi00ll : STD_LOGIC := '0'; + SIGNAL niOi00lO : STD_LOGIC := '0'; + SIGNAL niOi00O : STD_LOGIC := '0'; + SIGNAL niOi00Oi : STD_LOGIC := '0'; + SIGNAL niOi010i : STD_LOGIC := '0'; + SIGNAL niOi010l : STD_LOGIC := '0'; + SIGNAL niOi010O : STD_LOGIC := '0'; + SIGNAL niOi011i : STD_LOGIC := '0'; + SIGNAL niOi011l : STD_LOGIC := '0'; + SIGNAL niOi011O : STD_LOGIC := '0'; + SIGNAL niOi01ii : STD_LOGIC := '0'; + SIGNAL niOi01il : STD_LOGIC := '0'; + SIGNAL niOi01iO : STD_LOGIC := '0'; + SIGNAL niOi01l : STD_LOGIC := '0'; + SIGNAL niOi01li : STD_LOGIC := '0'; + SIGNAL niOi01ll : STD_LOGIC := '0'; + SIGNAL niOi01lO : STD_LOGIC := '0'; + SIGNAL niOi01O : STD_LOGIC := '0'; + SIGNAL niOi01Oi : STD_LOGIC := '0'; + SIGNAL niOi01Ol : STD_LOGIC := '0'; + SIGNAL niOi01OO : STD_LOGIC := '0'; + SIGNAL niOi0ii : STD_LOGIC := '0'; + SIGNAL niOi0il : STD_LOGIC := '0'; + SIGNAL niOi0iO : STD_LOGIC := '0'; + SIGNAL niOi0li : STD_LOGIC := '0'; + SIGNAL niOi0ll : STD_LOGIC := '0'; + SIGNAL niOi0lO : STD_LOGIC := '0'; + SIGNAL niOi0Oi : STD_LOGIC := '0'; + SIGNAL niOi0Ol : STD_LOGIC := '0'; + SIGNAL niOi0OO : STD_LOGIC := '0'; + SIGNAL niOi111i : STD_LOGIC := '0'; + SIGNAL niOi111l : STD_LOGIC := '0'; + SIGNAL niOi1lOl : STD_LOGIC := '0'; + SIGNAL niOi1lOO : STD_LOGIC := '0'; + SIGNAL niOi1O0i : STD_LOGIC := '0'; + SIGNAL niOi1O0l : STD_LOGIC := '0'; + SIGNAL niOi1O0O : STD_LOGIC := '0'; + SIGNAL niOi1O1i : STD_LOGIC := '0'; + SIGNAL niOi1O1l : STD_LOGIC := '0'; + SIGNAL niOi1O1O : STD_LOGIC := '0'; + SIGNAL niOi1Oii : STD_LOGIC := '0'; + SIGNAL niOi1Oil : STD_LOGIC := '0'; + SIGNAL niOi1OiO : STD_LOGIC := '0'; + SIGNAL niOi1Oli : STD_LOGIC := '0'; + SIGNAL niOi1Oll : STD_LOGIC := '0'; + SIGNAL niOi1OlO : STD_LOGIC := '0'; + SIGNAL niOi1OOi : STD_LOGIC := '0'; + SIGNAL niOi1OOl : STD_LOGIC := '0'; + SIGNAL niOi1OOO : STD_LOGIC := '0'; + SIGNAL niOii0i : STD_LOGIC := '0'; + SIGNAL niOii0l : STD_LOGIC := '0'; + SIGNAL niOii0O : STD_LOGIC := '0'; + SIGNAL niOii1i : STD_LOGIC := '0'; + SIGNAL niOii1l : STD_LOGIC := '0'; + SIGNAL niOii1O : STD_LOGIC := '0'; + SIGNAL niOiiii : STD_LOGIC := '0'; + SIGNAL niOiiil : STD_LOGIC := '0'; + SIGNAL niOiiiO : STD_LOGIC := '0'; + SIGNAL niOiil1O : STD_LOGIC := '0'; + SIGNAL niOiili : STD_LOGIC := '0'; + SIGNAL niOiilil : STD_LOGIC := '0'; + SIGNAL niOiill : STD_LOGIC := '0'; + SIGNAL niOiilli : STD_LOGIC := '0'; + SIGNAL niOiilO : STD_LOGIC := '0'; + SIGNAL niOiiOi : STD_LOGIC := '0'; + SIGNAL niOiiOl : STD_LOGIC := '0'; + SIGNAL niOiiOO : STD_LOGIC := '0'; + SIGNAL niOil0i : STD_LOGIC := '0'; + SIGNAL niOil0l : STD_LOGIC := '0'; + SIGNAL niOil0O : STD_LOGIC := '0'; + SIGNAL niOil1i : STD_LOGIC := '0'; + SIGNAL niOil1l : STD_LOGIC := '0'; + SIGNAL niOil1O : STD_LOGIC := '0'; + SIGNAL niOilii : STD_LOGIC := '0'; + SIGNAL niOilil : STD_LOGIC := '0'; + SIGNAL niOiliO : STD_LOGIC := '0'; + SIGNAL niOilli : STD_LOGIC := '0'; + SIGNAL niOilll : STD_LOGIC := '0'; + SIGNAL niOillO : STD_LOGIC := '0'; + SIGNAL niOilOi : STD_LOGIC := '0'; + SIGNAL niOilOl : STD_LOGIC := '0'; + SIGNAL niOilOO : STD_LOGIC := '0'; + SIGNAL niOiO0i : STD_LOGIC := '0'; + SIGNAL niOiO0l : STD_LOGIC := '0'; + SIGNAL niOiO0O : STD_LOGIC := '0'; + SIGNAL niOiO1i : STD_LOGIC := '0'; + SIGNAL niOiO1l : STD_LOGIC := '0'; + SIGNAL niOiO1O : STD_LOGIC := '0'; + SIGNAL niOlii0l : STD_LOGIC := '0'; + SIGNAL niOlii0O : STD_LOGIC := '0'; + SIGNAL niOliiii : STD_LOGIC := '0'; + SIGNAL niOliiil : STD_LOGIC := '0'; + SIGNAL niOliiiO : STD_LOGIC := '0'; + SIGNAL niOliili : STD_LOGIC := '0'; + SIGNAL niOliill : STD_LOGIC := '0'; + SIGNAL niOliilO : STD_LOGIC := '0'; + SIGNAL niOliiOi : STD_LOGIC := '0'; + SIGNAL niOliiOl : STD_LOGIC := '0'; + SIGNAL niOliiOO : STD_LOGIC := '0'; + SIGNAL niOlil0i : STD_LOGIC := '0'; + SIGNAL niOlil0l : STD_LOGIC := '0'; + SIGNAL niOlil0O : STD_LOGIC := '0'; + SIGNAL niOlil1i : STD_LOGIC := '0'; + SIGNAL niOlil1l : STD_LOGIC := '0'; + SIGNAL niOlil1O : STD_LOGIC := '0'; + SIGNAL niOlilii : STD_LOGIC := '0'; + SIGNAL niOlilil : STD_LOGIC := '0'; + SIGNAL niOliliO : STD_LOGIC := '0'; + SIGNAL niOlilli : STD_LOGIC := '0'; + SIGNAL niOlilll : STD_LOGIC := '0'; + SIGNAL niOlillO : STD_LOGIC := '0'; + SIGNAL niOlilOi : STD_LOGIC := '0'; + SIGNAL niOlilOl : STD_LOGIC := '0'; + SIGNAL niOlilOO : STD_LOGIC := '0'; + SIGNAL niOliO0i : STD_LOGIC := '0'; + SIGNAL niOliO0l : STD_LOGIC := '0'; + SIGNAL niOliO0O : STD_LOGIC := '0'; + SIGNAL niOliO1i : STD_LOGIC := '0'; + SIGNAL niOliO1l : STD_LOGIC := '0'; + SIGNAL niOliO1O : STD_LOGIC := '0'; + SIGNAL niOliOii : STD_LOGIC := '0'; + SIGNAL niOliOil : STD_LOGIC := '0'; + SIGNAL niOliOiO : STD_LOGIC := '0'; + SIGNAL niOliOli : STD_LOGIC := '0'; + SIGNAL niOlOi0O : STD_LOGIC := '0'; + SIGNAL niOlOill : STD_LOGIC := '0'; + SIGNAL niOlOl1i : STD_LOGIC := '0'; + SIGNAL niOlOl1O : STD_LOGIC := '0'; + SIGNAL niOlOO1O : STD_LOGIC := '0'; + SIGNAL niOlOOil : STD_LOGIC := '0'; + SIGNAL niOlOOli : STD_LOGIC := '0'; + SIGNAL niOO000O : STD_LOGIC := '0'; + SIGNAL niOO001i : STD_LOGIC := '0'; + SIGNAL niOO00il : STD_LOGIC := '0'; + SIGNAL niOO010O : STD_LOGIC := '0'; + SIGNAL niOO01ii : STD_LOGIC := '0'; + SIGNAL niOO0ili : STD_LOGIC := '0'; + SIGNAL niOO0l1l : STD_LOGIC := '0'; + SIGNAL niOO0liO : STD_LOGIC := '0'; + SIGNAL niOO0llO : STD_LOGIC := '0'; + SIGNAL niOO0Oli : STD_LOGIC := '0'; + SIGNAL niOO101i : STD_LOGIC := '0'; + SIGNAL niOO101O : STD_LOGIC := '0'; + SIGNAL niOO11ll : STD_LOGIC := '0'; + SIGNAL niOO1i0i : STD_LOGIC := '0'; + SIGNAL niOO1iiO : STD_LOGIC := '0'; + SIGNAL niOO1ill : STD_LOGIC := '0'; + SIGNAL niOO1llO : STD_LOGIC := '0'; + SIGNAL niOO1O0i : STD_LOGIC := '0'; + SIGNAL niOO1O1l : STD_LOGIC := '0'; + SIGNAL niOOi01il : STD_LOGIC := '0'; + SIGNAL niOOi01O : STD_LOGIC := '0'; + SIGNAL niOOi01Oi : STD_LOGIC := '0'; + SIGNAL niOOi01OO : STD_LOGIC := '0'; + SIGNAL niOOi0li : STD_LOGIC := '0'; + SIGNAL niOOi0Oi : STD_LOGIC := '0'; + SIGNAL niOOi10l : STD_LOGIC := '0'; + SIGNAL niOOi11l : STD_LOGIC := '0'; + SIGNAL niOOi1i0i : STD_LOGIC := '0'; + SIGNAL niOOi1i0l : STD_LOGIC := '0'; + SIGNAL niOOi1i0O : STD_LOGIC := '0'; + SIGNAL niOOi1i1i : STD_LOGIC := '0'; + SIGNAL niOOi1i1l : STD_LOGIC := '0'; + SIGNAL niOOi1i1O : STD_LOGIC := '0'; + SIGNAL niOOi1iii : STD_LOGIC := '0'; + SIGNAL niOOi1iil : STD_LOGIC := '0'; + SIGNAL niOOi1iiO : STD_LOGIC := '0'; + SIGNAL niOOi1ili : STD_LOGIC := '0'; + SIGNAL niOOi1ill : STD_LOGIC := '0'; + SIGNAL niOOi1ilO : STD_LOGIC := '0'; + SIGNAL niOOi1iOi : STD_LOGIC := '0'; + SIGNAL niOOi1iOl : STD_LOGIC := '0'; + SIGNAL niOOi1iOO : STD_LOGIC := '0'; + SIGNAL niOOi1l1i : STD_LOGIC := '0'; + SIGNAL niOOil0i : STD_LOGIC := '0'; + SIGNAL niOOil0l : STD_LOGIC := '0'; + SIGNAL niOOil0O : STD_LOGIC := '0'; + SIGNAL niOOilii : STD_LOGIC := '0'; + SIGNAL niOOilil : STD_LOGIC := '0'; + SIGNAL niOOiliO : STD_LOGIC := '0'; + SIGNAL niOOilli : STD_LOGIC := '0'; + SIGNAL niOOilll : STD_LOGIC := '0'; + SIGNAL niOOillO : STD_LOGIC := '0'; + SIGNAL niOOilOi : STD_LOGIC := '0'; + SIGNAL niOOl1il : STD_LOGIC := '0'; + SIGNAL niOOl1Oi : STD_LOGIC := '0'; + SIGNAL niOOl1OO : STD_LOGIC := '0'; + SIGNAL niOOllOO : STD_LOGIC := '0'; + SIGNAL niOOlO0l : STD_LOGIC := '0'; + SIGNAL niOOlOii : STD_LOGIC := '0'; + SIGNAL niOOO01O : STD_LOGIC := '0'; + SIGNAL niOOO1il : STD_LOGIC := '0'; + SIGNAL niOOO1OO : STD_LOGIC := '0'; + SIGNAL niOOOi0O : STD_LOGIC := '0'; + SIGNAL niOOOi1i : STD_LOGIC := '0'; + SIGNAL niOOOiil : STD_LOGIC := '0'; + SIGNAL niOOOil : STD_LOGIC := '0'; + SIGNAL niOOOl0l : STD_LOGIC := '0'; + SIGNAL niOOOlil : STD_LOGIC := '0'; + SIGNAL niOOOlll : STD_LOGIC := '0'; + SIGNAL niOOOlOl : STD_LOGIC := '0'; + SIGNAL niOOOO1l : STD_LOGIC := '0'; + SIGNAL niOOOOiO : STD_LOGIC := '0'; + SIGNAL niOOOOOl : STD_LOGIC := '0'; + SIGNAL nl0000iO : STD_LOGIC := '0'; + SIGNAL nl0000li : STD_LOGIC := '0'; + SIGNAL nl0000ll : STD_LOGIC := '0'; + SIGNAL nl0000lO : STD_LOGIC := '0'; + SIGNAL nl0000Oi : STD_LOGIC := '0'; + SIGNAL nl0000Ol : STD_LOGIC := '0'; + SIGNAL nl0000OO : STD_LOGIC := '0'; + SIGNAL nl000i0i : STD_LOGIC := '0'; + SIGNAL nl000i0l : STD_LOGIC := '0'; + SIGNAL nl000i0O : STD_LOGIC := '0'; + SIGNAL nl000i1i : STD_LOGIC := '0'; + SIGNAL nl000i1l : STD_LOGIC := '0'; + SIGNAL nl000i1O : STD_LOGIC := '0'; + SIGNAL nl000iii : STD_LOGIC := '0'; + SIGNAL nl000iil : STD_LOGIC := '0'; + SIGNAL nl000iiO : STD_LOGIC := '0'; + SIGNAL nl000ili : STD_LOGIC := '0'; + SIGNAL nl000ill : STD_LOGIC := '0'; + SIGNAL nl000ilO : STD_LOGIC := '0'; + SIGNAL nl000iOi : STD_LOGIC := '0'; + SIGNAL nl000iOl : STD_LOGIC := '0'; + SIGNAL nl000iOO : STD_LOGIC := '0'; + SIGNAL nl000l0i : STD_LOGIC := '0'; + SIGNAL nl000l0l : STD_LOGIC := '0'; + SIGNAL nl000l0O : STD_LOGIC := '0'; + SIGNAL nl000l1i : STD_LOGIC := '0'; + SIGNAL nl000l1l : STD_LOGIC := '0'; + SIGNAL nl000l1O : STD_LOGIC := '0'; + SIGNAL nl000lii : STD_LOGIC := '0'; + SIGNAL nl000lil : STD_LOGIC := '0'; + SIGNAL nl000liO : STD_LOGIC := '0'; + SIGNAL nl000lli : STD_LOGIC := '0'; + SIGNAL nl000lll : STD_LOGIC := '0'; + SIGNAL nl000llO : STD_LOGIC := '0'; + SIGNAL nl000lOi : STD_LOGIC := '0'; + SIGNAL nl000lOl : STD_LOGIC := '0'; + SIGNAL nl000lOO : STD_LOGIC := '0'; + SIGNAL nl00100i : STD_LOGIC := '0'; + SIGNAL nl00101i : STD_LOGIC := '0'; + SIGNAL nl00101l : STD_LOGIC := '0'; + SIGNAL nl00101O : STD_LOGIC := '0'; + SIGNAL nl00110i : STD_LOGIC := '0'; + SIGNAL nl00110l : STD_LOGIC := '0'; + SIGNAL nl00110O : STD_LOGIC := '0'; + SIGNAL nl00111i : STD_LOGIC := '0'; + SIGNAL nl00111l : STD_LOGIC := '0'; + SIGNAL nl00111O : STD_LOGIC := '0'; + SIGNAL nl0011ii : STD_LOGIC := '0'; + SIGNAL nl0011il : STD_LOGIC := '0'; + SIGNAL nl0011iO : STD_LOGIC := '0'; + SIGNAL nl0011li : STD_LOGIC := '0'; + SIGNAL nl0011ll : STD_LOGIC := '0'; + SIGNAL nl0011lO : STD_LOGIC := '0'; + SIGNAL nl0011Oi : STD_LOGIC := '0'; + SIGNAL nl0011Ol : STD_LOGIC := '0'; + SIGNAL nl0011OO : STD_LOGIC := '0'; + SIGNAL nl00ilOO : STD_LOGIC := '0'; + SIGNAL nl00iO1i : STD_LOGIC := '0'; + SIGNAL nl00iO1l : STD_LOGIC := '0'; + SIGNAL nl00Ol0i : STD_LOGIC := '0'; + SIGNAL nl00Olll : STD_LOGIC := '0'; + SIGNAL nl00OlOl : STD_LOGIC := '0'; + SIGNAL nl00OlOO : STD_LOGIC := '0'; + SIGNAL nl00OO0i : STD_LOGIC := '0'; + SIGNAL nl00OO0l : STD_LOGIC := '0'; + SIGNAL nl00OO0O : STD_LOGIC := '0'; + SIGNAL nl00OO1i : STD_LOGIC := '0'; + SIGNAL nl00OO1l : STD_LOGIC := '0'; + SIGNAL nl00OO1O : STD_LOGIC := '0'; + SIGNAL nl00OOii : STD_LOGIC := '0'; + SIGNAL nl00OOil : STD_LOGIC := '0'; + SIGNAL nl00OOiO : STD_LOGIC := '0'; + SIGNAL nl00OOli : STD_LOGIC := '0'; + SIGNAL nl00OOll : STD_LOGIC := '0'; + SIGNAL nl00OOlO : STD_LOGIC := '0'; + SIGNAL nl00OOOi : STD_LOGIC := '0'; + SIGNAL nl00OOOl : STD_LOGIC := '0'; + SIGNAL nl00OOOO : STD_LOGIC := '0'; + SIGNAL nl010OOO : STD_LOGIC := '0'; + SIGNAL nl011l0l : STD_LOGIC := '0'; + SIGNAL nl011lli : STD_LOGIC := '0'; + SIGNAL nl011llO : STD_LOGIC := '0'; + SIGNAL nl01i0il : STD_LOGIC := '0'; + SIGNAL nl01i0OO : STD_LOGIC := '0'; + SIGNAL nl01i1ii : STD_LOGIC := '0'; + SIGNAL nl01i1li : STD_LOGIC := '0'; + SIGNAL nl01ii1O : STD_LOGIC := '0'; + SIGNAL nl01il1O : STD_LOGIC := '0'; + SIGNAL nl01illO : STD_LOGIC := '0'; + SIGNAL nl01ilOi : STD_LOGIC := '0'; + SIGNAL nl01Ol1O : STD_LOGIC := '0'; + SIGNAL nl01Olli : STD_LOGIC := '0'; + SIGNAL nl01OlOi : STD_LOGIC := '0'; + SIGNAL nl01OlOl : STD_LOGIC := '0'; + SIGNAL nl01OlOO : STD_LOGIC := '0'; + SIGNAL nl01OO0i : STD_LOGIC := '0'; + SIGNAL nl01OO0l : STD_LOGIC := '0'; + SIGNAL nl01OO0O : STD_LOGIC := '0'; + SIGNAL nl01OO1i : STD_LOGIC := '0'; + SIGNAL nl01OO1l : STD_LOGIC := '0'; + SIGNAL nl01OO1O : STD_LOGIC := '0'; + SIGNAL nl01OOii : STD_LOGIC := '0'; + SIGNAL nl01OOil : STD_LOGIC := '0'; + SIGNAL nl01OOiO : STD_LOGIC := '0'; + SIGNAL nl01OOli : STD_LOGIC := '0'; + SIGNAL nl01OOll : STD_LOGIC := '0'; + SIGNAL nl01OOlO : STD_LOGIC := '0'; + SIGNAL nl01OOOi : STD_LOGIC := '0'; + SIGNAL nl01OOOl : STD_LOGIC := '0'; + SIGNAL nl01OOOO : STD_LOGIC := '0'; + SIGNAL nl0i00li : STD_LOGIC := '0'; + SIGNAL nl0i00ll : STD_LOGIC := '0'; + SIGNAL nl0i00lO : STD_LOGIC := '0'; + SIGNAL nl0i00Oi : STD_LOGIC := '0'; + SIGNAL nl0i00Ol : STD_LOGIC := '0'; + SIGNAL nl0i00OO : STD_LOGIC := '0'; + SIGNAL nl0i0i0i : STD_LOGIC := '0'; + SIGNAL nl0i0i0l : STD_LOGIC := '0'; + SIGNAL nl0i0i0O : STD_LOGIC := '0'; + SIGNAL nl0i0i1i : STD_LOGIC := '0'; + SIGNAL nl0i0i1l : STD_LOGIC := '0'; + SIGNAL nl0i0i1O : STD_LOGIC := '0'; + SIGNAL nl0i0iii : STD_LOGIC := '0'; + SIGNAL nl0i0iil : STD_LOGIC := '0'; + SIGNAL nl0i0iiO : STD_LOGIC := '0'; + SIGNAL nl0i0ili : STD_LOGIC := '0'; + SIGNAL nl0i0ill : STD_LOGIC := '0'; + SIGNAL nl0i0ilO : STD_LOGIC := '0'; + SIGNAL nl0i0iOi : STD_LOGIC := '0'; + SIGNAL nl0i0iOl : STD_LOGIC := '0'; + SIGNAL nl0i0iOO : STD_LOGIC := '0'; + SIGNAL nl0i0l0i : STD_LOGIC := '0'; + SIGNAL nl0i0l0l : STD_LOGIC := '0'; + SIGNAL nl0i0l0O : STD_LOGIC := '0'; + SIGNAL nl0i0l1i : STD_LOGIC := '0'; + SIGNAL nl0i0l1l : STD_LOGIC := '0'; + SIGNAL nl0i0l1O : STD_LOGIC := '0'; + SIGNAL nl0i0lii : STD_LOGIC := '0'; + SIGNAL nl0i0lil : STD_LOGIC := '0'; + SIGNAL nl0i0liO : STD_LOGIC := '0'; + SIGNAL nl0i0lli : STD_LOGIC := '0'; + SIGNAL nl0i0lll : STD_LOGIC := '0'; + SIGNAL nl0i0llO : STD_LOGIC := '0'; + SIGNAL nl0i0lOi : STD_LOGIC := '0'; + SIGNAL nl0i0lOl : STD_LOGIC := '0'; + SIGNAL nl0i0lOO : STD_LOGIC := '0'; + SIGNAL nl0i0O1i : STD_LOGIC := '0'; + SIGNAL nl0i100i : STD_LOGIC := '0'; + SIGNAL nl0i100l : STD_LOGIC := '0'; + SIGNAL nl0i101i : STD_LOGIC := '0'; + SIGNAL nl0i101l : STD_LOGIC := '0'; + SIGNAL nl0i101O : STD_LOGIC := '0'; + SIGNAL nl0i110i : STD_LOGIC := '0'; + SIGNAL nl0i110l : STD_LOGIC := '0'; + SIGNAL nl0i110O : STD_LOGIC := '0'; + SIGNAL nl0i111i : STD_LOGIC := '0'; + SIGNAL nl0i111l : STD_LOGIC := '0'; + SIGNAL nl0i111O : STD_LOGIC := '0'; + SIGNAL nl0i11ii : STD_LOGIC := '0'; + SIGNAL nl0i11il : STD_LOGIC := '0'; + SIGNAL nl0i11iO : STD_LOGIC := '0'; + SIGNAL nl0i11li : STD_LOGIC := '0'; + SIGNAL nl0i11ll : STD_LOGIC := '0'; + SIGNAL nl0i11lO : STD_LOGIC := '0'; + SIGNAL nl0i11Oi : STD_LOGIC := '0'; + SIGNAL nl0i11Ol : STD_LOGIC := '0'; + SIGNAL nl0i11OO : STD_LOGIC := '0'; + SIGNAL nl0iiO1i : STD_LOGIC := '0'; + SIGNAL nl0iiO1l : STD_LOGIC := '0'; + SIGNAL nl0iiO1O : STD_LOGIC := '0'; + SIGNAL nl0O1l0O : STD_LOGIC := '0'; + SIGNAL nl0Oiili : STD_LOGIC := '0'; + SIGNAL nl0Oiill : STD_LOGIC := '0'; + SIGNAL nl0OiilO : STD_LOGIC := '0'; + SIGNAL nl0OiiOi : STD_LOGIC := '0'; + SIGNAL nl0OiiOl : STD_LOGIC := '0'; + SIGNAL nl0OiiOO : STD_LOGIC := '0'; + SIGNAL nl0Oil0i : STD_LOGIC := '0'; + SIGNAL nl0Oil0l : STD_LOGIC := '0'; + SIGNAL nl0Oil0O : STD_LOGIC := '0'; + SIGNAL nl0Oil1i : STD_LOGIC := '0'; + SIGNAL nl0Oil1l : STD_LOGIC := '0'; + SIGNAL nl0Oil1O : STD_LOGIC := '0'; + SIGNAL nl0Oilii : STD_LOGIC := '0'; + SIGNAL nl0Oilil : STD_LOGIC := '0'; + SIGNAL nl0OiliO : STD_LOGIC := '0'; + SIGNAL nl0Oilli : STD_LOGIC := '0'; + SIGNAL nl0Oilll : STD_LOGIC := '0'; + SIGNAL nl0OillO : STD_LOGIC := '0'; + SIGNAL nl0OilOi : STD_LOGIC := '0'; + SIGNAL nl0OilOl : STD_LOGIC := '0'; + SIGNAL nl0OilOO : STD_LOGIC := '0'; + SIGNAL nl0OiO0i : STD_LOGIC := '0'; + SIGNAL nl0OiO0l : STD_LOGIC := '0'; + SIGNAL nl0OiO0O : STD_LOGIC := '0'; + SIGNAL nl0OiO1i : STD_LOGIC := '0'; + SIGNAL nl0OiO1l : STD_LOGIC := '0'; + SIGNAL nl0OiO1O : STD_LOGIC := '0'; + SIGNAL nl0OlOii : STD_LOGIC := '0'; + SIGNAL nl0OlOOl : STD_LOGIC := '0'; + SIGNAL nl0OO10i : STD_LOGIC := '0'; + SIGNAL nl0OO10l : STD_LOGIC := '0'; + SIGNAL nl0OO10O : STD_LOGIC := '0'; + SIGNAL nl0OO11l : STD_LOGIC := '0'; + SIGNAL nl0OO11O : STD_LOGIC := '0'; + SIGNAL nl0OO1ii : STD_LOGIC := '0'; + SIGNAL nl0OO1il : STD_LOGIC := '0'; + SIGNAL nl0OO1iO : STD_LOGIC := '0'; + SIGNAL nl0OO1li : STD_LOGIC := '0'; + SIGNAL nl0OO1ll : STD_LOGIC := '0'; + SIGNAL nl0OO1lO : STD_LOGIC := '0'; + SIGNAL nl0OO1Oi : STD_LOGIC := '0'; + SIGNAL nl0OOO0l : STD_LOGIC := '0'; + SIGNAL nl0OOOlO : STD_LOGIC := '0'; + SIGNAL nl0OOOOO : STD_LOGIC := '0'; + SIGNAL nl10000l : STD_LOGIC := '0'; + SIGNAL nl1000ii : STD_LOGIC := '0'; + SIGNAL nl1000l : STD_LOGIC := '0'; + SIGNAL nl1001i : STD_LOGIC := '0'; + SIGNAL nl1001l : STD_LOGIC := '0'; + SIGNAL nl1001O : STD_LOGIC := '0'; + SIGNAL nl1001OO : STD_LOGIC := '0'; + SIGNAL nl100O0i : STD_LOGIC := '0'; + SIGNAL nl100O0l : STD_LOGIC := '0'; + SIGNAL nl100O0O : STD_LOGIC := '0'; + SIGNAL nl100O1O : STD_LOGIC := '0'; + SIGNAL nl10101l : STD_LOGIC := '0'; + SIGNAL nl1010i : STD_LOGIC := '0'; + SIGNAL nl1010l : STD_LOGIC := '0'; + SIGNAL nl1010O : STD_LOGIC := '0'; + SIGNAL nl1011i : STD_LOGIC := '0'; + SIGNAL nl1011l : STD_LOGIC := '0'; + SIGNAL nl1011li : STD_LOGIC := '0'; + SIGNAL nl1011O : STD_LOGIC := '0'; + SIGNAL nl1011OO : STD_LOGIC := '0'; + SIGNAL nl101i1O : STD_LOGIC := '0'; + SIGNAL nl101ii : STD_LOGIC := '0'; + SIGNAL nl101il : STD_LOGIC := '0'; + SIGNAL nl101ili : STD_LOGIC := '0'; + SIGNAL nl101iO : STD_LOGIC := '0'; + SIGNAL nl101iOi : STD_LOGIC := '0'; + SIGNAL nl101li : STD_LOGIC := '0'; + SIGNAL nl101ll : STD_LOGIC := '0'; + SIGNAL nl101lO : STD_LOGIC := '0'; + SIGNAL nl101O0i : STD_LOGIC := '0'; + SIGNAL nl101O0l : STD_LOGIC := '0'; + SIGNAL nl101O0O : STD_LOGIC := '0'; + SIGNAL nl101O1l : STD_LOGIC := '0'; + SIGNAL nl101O1O : STD_LOGIC := '0'; + SIGNAL nl101Oi : STD_LOGIC := '0'; + SIGNAL nl101Oii : STD_LOGIC := '0'; + SIGNAL nl101Oil : STD_LOGIC := '0'; + SIGNAL nl101OiO : STD_LOGIC := '0'; + SIGNAL nl101Ol : STD_LOGIC := '0'; + SIGNAL nl101OO : STD_LOGIC := '0'; + SIGNAL nl10i10i : STD_LOGIC := '0'; + SIGNAL nl10i1iO : STD_LOGIC := '0'; + SIGNAL nl10i1ll : STD_LOGIC := '0'; + SIGNAL nl10iili : STD_LOGIC := '0'; + SIGNAL nl10iill : STD_LOGIC := '0'; + SIGNAL nl10iilO : STD_LOGIC := '0'; + SIGNAL nl10iiOi : STD_LOGIC := '0'; + SIGNAL nl10illl : STD_LOGIC := '0'; + SIGNAL nl10iO1i : STD_LOGIC := '0'; + SIGNAL nl10iO1O : STD_LOGIC := '0'; + SIGNAL nl10l01l : STD_LOGIC := '0'; + SIGNAL nl10l0Ol : STD_LOGIC := '0'; + SIGNAL nl10l0OO : STD_LOGIC := '0'; + SIGNAL nl10l1ll : STD_LOGIC := '0'; + SIGNAL nl10l1Ol : STD_LOGIC := '0'; + SIGNAL nl10li0i : STD_LOGIC := '0'; + SIGNAL nl10li0l : STD_LOGIC := '0'; + SIGNAL nl10li1i : STD_LOGIC := '0'; + SIGNAL nl10li1l : STD_LOGIC := '0'; + SIGNAL nl10li1O : STD_LOGIC := '0'; + SIGNAL nl10lliO : STD_LOGIC := '0'; + SIGNAL nl10llOl : STD_LOGIC := '0'; + SIGNAL nl10lO1i : STD_LOGIC := '0'; + SIGNAL nl10O00i : STD_LOGIC := '0'; + SIGNAL nl10O0ii : STD_LOGIC := '0'; + SIGNAL nl10O0li : STD_LOGIC := '0'; + SIGNAL nl10O0Oi : STD_LOGIC := '0'; + SIGNAL nl10Oi0i : STD_LOGIC := '0'; + SIGNAL nl10Oi1i : STD_LOGIC := '0'; + SIGNAL nl10Oiii : STD_LOGIC := '0'; + SIGNAL nl10Oili : STD_LOGIC := '0'; + SIGNAL nl10OOii : STD_LOGIC := '0'; + SIGNAL nl10OOil : STD_LOGIC := '0'; + SIGNAL nl10OOiO : STD_LOGIC := '0'; + SIGNAL nl10OOli : STD_LOGIC := '0'; + SIGNAL nl10OOll : STD_LOGIC := '0'; + SIGNAL nl10OOlO : STD_LOGIC := '0'; + SIGNAL nl10OOOi : STD_LOGIC := '0'; + SIGNAL nl10OOOl : STD_LOGIC := '0'; + SIGNAL nl10OOOO : STD_LOGIC := '0'; + SIGNAL nl11001i : STD_LOGIC := '0'; + SIGNAL nl11001O : STD_LOGIC := '0'; + SIGNAL nl1101ll : STD_LOGIC := '0'; + SIGNAL nl110i0i : STD_LOGIC := '0'; + SIGNAL nl110iiO : STD_LOGIC := '0'; + SIGNAL nl110ill : STD_LOGIC := '0'; + SIGNAL nl110llO : STD_LOGIC := '0'; + SIGNAL nl110O0i : STD_LOGIC := '0'; + SIGNAL nl110O1l : STD_LOGIC := '0'; + SIGNAL nl11101l : STD_LOGIC := '0'; + SIGNAL nl1110ii : STD_LOGIC := '0'; + SIGNAL nl1110iO : STD_LOGIC := '0'; + SIGNAL nl11111i : STD_LOGIC := '0'; + SIGNAL nl111ili : STD_LOGIC := '0'; + SIGNAL nl111iOO : STD_LOGIC := '0'; + SIGNAL nl111l1l : STD_LOGIC := '0'; + SIGNAL nl111O0i : STD_LOGIC := '0'; + SIGNAL nl111Oll : STD_LOGIC := '0'; + SIGNAL nl111OOl : STD_LOGIC := '0'; + SIGNAL nl11i0Oi : STD_LOGIC := '0'; + SIGNAL nl11i10l : STD_LOGIC := '0'; + SIGNAL nl11i1li : STD_LOGIC := '0'; + SIGNAL nl11i1lO : STD_LOGIC := '0'; + SIGNAL nl11ii0l : STD_LOGIC := '0'; + SIGNAL nl11ii1O : STD_LOGIC := '0'; + SIGNAL nl11il0O : STD_LOGIC := '0'; + SIGNAL nl11illl : STD_LOGIC := '0'; + SIGNAL nl11ilO : STD_LOGIC := '0'; + SIGNAL nl11ilOi : STD_LOGIC := '0'; + SIGNAL nl11iOi : STD_LOGIC := '0'; + SIGNAL nl11iOl : STD_LOGIC := '0'; + SIGNAL nl11iOO : STD_LOGIC := '0'; + SIGNAL nl11iOOl : STD_LOGIC := '0'; + SIGNAL nl11l0i : STD_LOGIC := '0'; + SIGNAL nl11l0il : STD_LOGIC := '0'; + SIGNAL nl11l0l : STD_LOGIC := '0'; + SIGNAL nl11l0O : STD_LOGIC := '0'; + SIGNAL nl11l0OO : STD_LOGIC := '0'; + SIGNAL nl11l10i : STD_LOGIC := '0'; + SIGNAL nl11l10O : STD_LOGIC := '0'; + SIGNAL nl11l1i : STD_LOGIC := '0'; + SIGNAL nl11l1l : STD_LOGIC := '0'; + SIGNAL nl11l1O : STD_LOGIC := '0'; + SIGNAL nl11li1O : STD_LOGIC := '0'; + SIGNAL nl11lii : STD_LOGIC := '0'; + SIGNAL nl11lil : STD_LOGIC := '0'; + SIGNAL nl11liO : STD_LOGIC := '0'; + SIGNAL nl11ll1i : STD_LOGIC := '0'; + SIGNAL nl11lli : STD_LOGIC := '0'; + SIGNAL nl11llil : STD_LOGIC := '0'; + SIGNAL nl11lll : STD_LOGIC := '0'; + SIGNAL nl11llll : STD_LOGIC := '0'; + SIGNAL nl11lOiO : STD_LOGIC := '0'; + SIGNAL nl11lOl : STD_LOGIC := '0'; + SIGNAL nl11lOO : STD_LOGIC := '0'; + SIGNAL nl11O01l : STD_LOGIC := '0'; + SIGNAL nl11O0i : STD_LOGIC := '0'; + SIGNAL nl11O0iO : STD_LOGIC := '0'; + SIGNAL nl11O0l : STD_LOGIC := '0'; + SIGNAL nl11O0lO : STD_LOGIC := '0'; + SIGNAL nl11O0O : STD_LOGIC := '0'; + SIGNAL nl11O10i : STD_LOGIC := '0'; + SIGNAL nl11O11i : STD_LOGIC := '0'; + SIGNAL nl11O1i : STD_LOGIC := '0'; + SIGNAL nl11O1l : STD_LOGIC := '0'; + SIGNAL nl11O1O : STD_LOGIC := '0'; + SIGNAL nl11Oii : STD_LOGIC := '0'; + SIGNAL nl11Oil : STD_LOGIC := '0'; + SIGNAL nl11Oili : STD_LOGIC := '0'; + SIGNAL nl11OiO : STD_LOGIC := '0'; + SIGNAL nl11Ol0l : STD_LOGIC := '0'; + SIGNAL nl11Ol1l : STD_LOGIC := '0'; + SIGNAL nl11Oli : STD_LOGIC := '0'; + SIGNAL nl11Oll : STD_LOGIC := '0'; + SIGNAL nl11OlO : STD_LOGIC := '0'; + SIGNAL nl11OO1l : STD_LOGIC := '0'; + SIGNAL nl11OOi : STD_LOGIC := '0'; + SIGNAL nl11OOiO : STD_LOGIC := '0'; + SIGNAL nl11OOl : STD_LOGIC := '0'; + SIGNAL nl11OOlO : STD_LOGIC := '0'; + SIGNAL nl11OOO : STD_LOGIC := '0'; + SIGNAL nl1i0OlO : STD_LOGIC := '0'; + SIGNAL nl1i0OOi : STD_LOGIC := '0'; + SIGNAL nl1i110i : STD_LOGIC := '0'; + SIGNAL nl1i110l : STD_LOGIC := '0'; + SIGNAL nl1i110O : STD_LOGIC := '0'; + SIGNAL nl1i111i : STD_LOGIC := '0'; + SIGNAL nl1i111l : STD_LOGIC := '0'; + SIGNAL nl1i111O : STD_LOGIC := '0'; + SIGNAL nl1i11ii : STD_LOGIC := '0'; + SIGNAL nl1i11il : STD_LOGIC := '0'; + SIGNAL nl1i11iO : STD_LOGIC := '0'; + SIGNAL nl1i11li : STD_LOGIC := '0'; + SIGNAL nl1i11ll : STD_LOGIC := '0'; + SIGNAL nl1i11lO : STD_LOGIC := '0'; + SIGNAL nl1i1O1i : STD_LOGIC := '0'; + SIGNAL nl1i1O1O : STD_LOGIC := '0'; + SIGNAL nl1ii1ii : STD_LOGIC := '0'; + SIGNAL nl1ii1lO : STD_LOGIC := '0'; + SIGNAL nl1ii1Ol : STD_LOGIC := '0'; + SIGNAL nl1iii0l : STD_LOGIC := '0'; + SIGNAL nl1iiilO : STD_LOGIC := '0'; + SIGNAL nl1iiiOO : STD_LOGIC := '0'; + SIGNAL nl1iilOi : STD_LOGIC := '0'; + SIGNAL nl1iiO0l : STD_LOGIC := '0'; + SIGNAL nl1iiOil : STD_LOGIC := '0'; + SIGNAL nl1il00l : STD_LOGIC := '0'; + SIGNAL nl1il0il : STD_LOGIC := '0'; + SIGNAL nl1il0iO : STD_LOGIC := '0'; + SIGNAL nl1il1Oi : STD_LOGIC := '0'; + SIGNAL nl1ill0i : STD_LOGIC := '0'; + SIGNAL nl1ill0l : STD_LOGIC := '0'; + SIGNAL nl1ill0O : STD_LOGIC := '0'; + SIGNAL nl1ill1l : STD_LOGIC := '0'; + SIGNAL nl1ill1O : STD_LOGIC := '0'; + SIGNAL nl1illii : STD_LOGIC := '0'; + SIGNAL nl1illil : STD_LOGIC := '0'; + SIGNAL nl1illiO : STD_LOGIC := '0'; + SIGNAL nl1illli : STD_LOGIC := '0'; + SIGNAL nl1illll : STD_LOGIC := '0'; + SIGNAL nl1illlO : STD_LOGIC := '0'; + SIGNAL nl1illOi : STD_LOGIC := '0'; + SIGNAL nl1iO00i : STD_LOGIC := '0'; + SIGNAL nl1iO01l : STD_LOGIC := '0'; + SIGNAL nl1iO1lO : STD_LOGIC := '0'; + SIGNAL nl1iOOii : STD_LOGIC := '0'; + SIGNAL nl1iOOli : STD_LOGIC := '0'; + SIGNAL nl1iOOOi : STD_LOGIC := '0'; + SIGNAL nl1l000O : STD_LOGIC := '0'; + SIGNAL nl1l00Oi : STD_LOGIC := '0'; + SIGNAL nl1l010l : STD_LOGIC := '0'; + SIGNAL nl1l01il : STD_LOGIC := '0'; + SIGNAL nl1l0i1i : STD_LOGIC := '0'; + SIGNAL nl1l0iOl : STD_LOGIC := '0'; + SIGNAL nl1l0l0O : STD_LOGIC := '0'; + SIGNAL nl1l0liO : STD_LOGIC := '0'; + SIGNAL nl1l0O0i : STD_LOGIC := '0'; + SIGNAL nl1l0O0O : STD_LOGIC := '0'; + SIGNAL nl1l10lO : STD_LOGIC := '0'; + SIGNAL nl1l110i : STD_LOGIC := '0'; + SIGNAL nl1l11ll : STD_LOGIC := '0'; + SIGNAL nl1l11Ol : STD_LOGIC := '0'; + SIGNAL nl1l1i0i : STD_LOGIC := '0'; + SIGNAL nl1l1iii : STD_LOGIC := '0'; + SIGNAL nl1l1l0l : STD_LOGIC := '0'; + SIGNAL nl1l1llO : STD_LOGIC := '0'; + SIGNAL nl1l1lOO : STD_LOGIC := '0'; + SIGNAL nl1l1OOi : STD_LOGIC := '0'; + SIGNAL nl1li00l : STD_LOGIC := '0'; + SIGNAL nl1li0il : STD_LOGIC := '0'; + SIGNAL nl1li0iO : STD_LOGIC := '0'; + SIGNAL nl1li0li : STD_LOGIC := '0'; + SIGNAL nl1li0ll : STD_LOGIC := '0'; + SIGNAL nl1li1Oi : STD_LOGIC := '0'; + SIGNAL nl1liili : STD_LOGIC := '0'; + SIGNAL nl1liO0l : STD_LOGIC := '0'; + SIGNAL nl1liOlO : STD_LOGIC := '0'; + SIGNAL nl1liOOO : STD_LOGIC := '0'; + SIGNAL nl1ll00i : STD_LOGIC := '0'; + SIGNAL nl1ll0ii : STD_LOGIC := '0'; + SIGNAL nl1ll0ll : STD_LOGIC := '0'; + SIGNAL nl1ll0Ol : STD_LOGIC := '0'; + SIGNAL nl1ll0OO : STD_LOGIC := '0'; + SIGNAL nl1ll10i : STD_LOGIC := '0'; + SIGNAL nl1ll11i : STD_LOGIC := '0'; + SIGNAL nl1ll11l : STD_LOGIC := '0'; + SIGNAL nl1ll11O : STD_LOGIC := '0'; + SIGNAL nl1lli1i : STD_LOGIC := '0'; + SIGNAL nl1llilO : STD_LOGIC := '0'; + SIGNAL nl1lliOl : STD_LOGIC := '0'; + SIGNAL nl1lliOO : STD_LOGIC := '0'; + SIGNAL nl1lll1i : STD_LOGIC := '0'; + SIGNAL nl1llllO : STD_LOGIC := '0'; + SIGNAL nl1llOiO : STD_LOGIC := '0'; + SIGNAL nl1lO10i : STD_LOGIC := '0'; + SIGNAL nl1lO10l : STD_LOGIC := '0'; + SIGNAL nl1lO11i : STD_LOGIC := '0'; + SIGNAL nl1lOi0i : STD_LOGIC := '0'; + SIGNAL nl1lOill : STD_LOGIC := '0'; + SIGNAL nl1lOiOl : STD_LOGIC := '0'; + SIGNAL nl1lOiOO : STD_LOGIC := '0'; + SIGNAL nl1lOl1i : STD_LOGIC := '0'; + SIGNAL nl1lOl1l : STD_LOGIC := '0'; + SIGNAL nl1lOl1O : STD_LOGIC := '0'; + SIGNAL nl1lOO0i : STD_LOGIC := '0'; + SIGNAL nl1lOO0l : STD_LOGIC := '0'; + SIGNAL nl1lOO0O : STD_LOGIC := '0'; + SIGNAL nl1lOOii : STD_LOGIC := '0'; + SIGNAL nl1lOOil : STD_LOGIC := '0'; + SIGNAL nl1O000i : STD_LOGIC := '0'; + SIGNAL nl1O000O : STD_LOGIC := '0'; + SIGNAL nl1O011i : STD_LOGIC := '0'; + SIGNAL nl1O01Ol : STD_LOGIC := '0'; + SIGNAL nl1O0iii : STD_LOGIC := '0'; + SIGNAL nl1O0ilO : STD_LOGIC := '0'; + SIGNAL nl1O0iOl : STD_LOGIC := '0'; + SIGNAL nl1O0lOO : STD_LOGIC := '0'; + SIGNAL nl1O0O0l : STD_LOGIC := '0'; + SIGNAL nl1O0Oii : STD_LOGIC := '0'; + SIGNAL nl1O10ii : STD_LOGIC := '0'; + SIGNAL nl1O10il : STD_LOGIC := '0'; + SIGNAL nl1O10iO : STD_LOGIC := '0'; + SIGNAL nl1O110l : STD_LOGIC := '0'; + SIGNAL nl1O110O : STD_LOGIC := '0'; + SIGNAL nl1O11ii : STD_LOGIC := '0'; + SIGNAL nl1O1i0l : STD_LOGIC := '0'; + SIGNAL nl1O1ili : STD_LOGIC := '0'; + SIGNAL nl1O1ilO : STD_LOGIC := '0'; + SIGNAL nl1O1O0O : STD_LOGIC := '0'; + SIGNAL nl1O1OOi : STD_LOGIC := '0'; + SIGNAL nl1Oi1il : STD_LOGIC := '0'; + SIGNAL nl1Oi1Oi : STD_LOGIC := '0'; + SIGNAL nl1Oi1OO : STD_LOGIC := '0'; + SIGNAL nl1Oii1i : STD_LOGIC := '0'; + SIGNAL nl1Oiiil : STD_LOGIC := '0'; + SIGNAL nl1Oiill : STD_LOGIC := '0'; + SIGNAL nl1OiliO : STD_LOGIC := '0'; + SIGNAL nl1OiO0i : STD_LOGIC := '0'; + SIGNAL nl1OiO1i : STD_LOGIC := '0'; + SIGNAL nl1Ol0li : STD_LOGIC := '0'; + SIGNAL nl1Ol0OO : STD_LOGIC := '0'; + SIGNAL nl1Ol11l : STD_LOGIC := '0'; + SIGNAL nl1Ol1ii : STD_LOGIC := '0'; + SIGNAL nl1Ol1iO : STD_LOGIC := '0'; + SIGNAL nl1Oli1l : STD_LOGIC := '0'; + SIGNAL nl1Oll1O : STD_LOGIC := '0'; + SIGNAL nl1Ollil : STD_LOGIC := '0'; + SIGNAL nl1Ollli : STD_LOGIC := '0'; + SIGNAL nl1OlOll : STD_LOGIC := '0'; + SIGNAL nl1OO11i : STD_LOGIC := '0'; + SIGNAL nl1OO11O : STD_LOGIC := '0'; + SIGNAL nl1OOiOi : STD_LOGIC := '0'; + SIGNAL nl1OOiOl : STD_LOGIC := '0'; + SIGNAL nl1OOiOO : STD_LOGIC := '0'; + SIGNAL nl1OOl0i : STD_LOGIC := '0'; + SIGNAL nl1OOl0l : STD_LOGIC := '0'; + SIGNAL nl1OOl0O : STD_LOGIC := '0'; + SIGNAL nl1OOl1i : STD_LOGIC := '0'; + SIGNAL nl1OOl1l : STD_LOGIC := '0'; + SIGNAL nl1OOl1O : STD_LOGIC := '0'; + SIGNAL nl1OOlii : STD_LOGIC := '0'; + SIGNAL nl1OOlil : STD_LOGIC := '0'; + SIGNAL nl1OOliO : STD_LOGIC := '0'; + SIGNAL nl1OOlli : STD_LOGIC := '0'; + SIGNAL nl1OOlll : STD_LOGIC := '0'; + SIGNAL nl1OOllO : STD_LOGIC := '0'; + SIGNAL nl1OOlOi : STD_LOGIC := '0'; + SIGNAL nl1OOlOl : STD_LOGIC := '0'; + SIGNAL nl1OOlOO : STD_LOGIC := '0'; + SIGNAL nl1OOO0i : STD_LOGIC := '0'; + SIGNAL nl1OOO0l : STD_LOGIC := '0'; + SIGNAL nl1OOO0O : STD_LOGIC := '0'; + SIGNAL nl1OOO1i : STD_LOGIC := '0'; + SIGNAL nl1OOO1l : STD_LOGIC := '0'; + SIGNAL nl1OOO1O : STD_LOGIC := '0'; + SIGNAL nl1OOOii : STD_LOGIC := '0'; + SIGNAL nl1OOOil : STD_LOGIC := '0'; + SIGNAL nli01iOO : STD_LOGIC := '0'; + SIGNAL nli1100i : STD_LOGIC := '0'; + SIGNAL nli110iO : STD_LOGIC := '0'; + SIGNAL nli1110i : STD_LOGIC := '0'; + SIGNAL nli1111i : STD_LOGIC := '0'; + SIGNAL nli1111l : STD_LOGIC := '0'; + SIGNAL nli1111O : STD_LOGIC := '0'; + SIGNAL nli1i00i : STD_LOGIC := '0'; + SIGNAL nli1i00O : STD_LOGIC := '0'; + SIGNAL nli1i01O : STD_LOGIC := '0'; + SIGNAL nli1i0ii : STD_LOGIC := '0'; + SIGNAL nli1i0il : STD_LOGIC := '0'; + SIGNAL nli1i0iO : STD_LOGIC := '0'; + SIGNAL nli1i0li : STD_LOGIC := '0'; + SIGNAL nli1i0ll : STD_LOGIC := '0'; + SIGNAL nli1i0lO : STD_LOGIC := '0'; + SIGNAL nli1i10O : STD_LOGIC := '0'; + SIGNAL nli1i1ll : STD_LOGIC := '0'; + SIGNAL nli1i1lO : STD_LOGIC := '0'; + SIGNAL nli1i1Oi : STD_LOGIC := '0'; + SIGNAL nli1i1Ol : STD_LOGIC := '0'; + SIGNAL nli1i1OO : STD_LOGIC := '0'; + SIGNAL nlilli0Oi : STD_LOGIC := '0'; + SIGNAL nlilli0Ol : STD_LOGIC := '0'; + SIGNAL nlilli0OO : STD_LOGIC := '0'; + SIGNAL nlillii0i : STD_LOGIC := '0'; + SIGNAL nlillii0l : STD_LOGIC := '0'; + SIGNAL nlillii0O : STD_LOGIC := '0'; + SIGNAL nlillii1i : STD_LOGIC := '0'; + SIGNAL nlillii1l : STD_LOGIC := '0'; + SIGNAL nlillii1O : STD_LOGIC := '0'; + SIGNAL nlilliiii : STD_LOGIC := '0'; + SIGNAL nlilliiil : STD_LOGIC := '0'; + SIGNAL nlilliiiO : STD_LOGIC := '0'; + SIGNAL nlilliili : STD_LOGIC := '0'; + SIGNAL nlilliill : STD_LOGIC := '0'; + SIGNAL nlilliilO : STD_LOGIC := '0'; + SIGNAL nlilliiOi : STD_LOGIC := '0'; + SIGNAL nlilliiOl : STD_LOGIC := '0'; + SIGNAL nlilliiOO : STD_LOGIC := '0'; + SIGNAL nlillil1i : STD_LOGIC := '0'; + SIGNAL nlillil1l : STD_LOGIC := '0'; + SIGNAL nlillil1O : STD_LOGIC := '0'; + SIGNAL nlillO00i : STD_LOGIC := '0'; + SIGNAL nlillO00l : STD_LOGIC := '0'; + SIGNAL nlillO00O : STD_LOGIC := '0'; + SIGNAL nlillO01i : STD_LOGIC := '0'; + SIGNAL nlillO01l : STD_LOGIC := '0'; + SIGNAL nlillO01O : STD_LOGIC := '0'; + SIGNAL nlillO0ii : STD_LOGIC := '0'; + SIGNAL nlillO0il : STD_LOGIC := '0'; + SIGNAL nlillO0iO : STD_LOGIC := '0'; + SIGNAL nlillO0li : STD_LOGIC := '0'; + SIGNAL nlillO0ll : STD_LOGIC := '0'; + SIGNAL nlillO0lO : STD_LOGIC := '0'; + SIGNAL nlillO0Oi : STD_LOGIC := '0'; + SIGNAL nlillO0Ol : STD_LOGIC := '0'; + SIGNAL nlillO0OO : STD_LOGIC := '0'; + SIGNAL nlillO1Oi : STD_LOGIC := '0'; + SIGNAL nlillO1Ol : STD_LOGIC := '0'; + SIGNAL nlillO1OO : STD_LOGIC := '0'; + SIGNAL nlillOi0i : STD_LOGIC := '0'; + SIGNAL nlillOi0l : STD_LOGIC := '0'; + SIGNAL nlillOi0O : STD_LOGIC := '0'; + SIGNAL nlillOi1i : STD_LOGIC := '0'; + SIGNAL nlillOi1l : STD_LOGIC := '0'; + SIGNAL nlillOi1O : STD_LOGIC := '0'; + SIGNAL nlillOiii : STD_LOGIC := '0'; + SIGNAL nlillOiil : STD_LOGIC := '0'; + SIGNAL nlillOiiO : STD_LOGIC := '0'; + SIGNAL nlillOili : STD_LOGIC := '0'; + SIGNAL nlillOill : STD_LOGIC := '0'; + SIGNAL nlillOilO : STD_LOGIC := '0'; + SIGNAL nlillOiOi : STD_LOGIC := '0'; + SIGNAL nlillOiOl : STD_LOGIC := '0'; + SIGNAL nlillOiOO : STD_LOGIC := '0'; + SIGNAL nlillOl0i : STD_LOGIC := '0'; + SIGNAL nlillOl0l : STD_LOGIC := '0'; + SIGNAL nlillOl0O : STD_LOGIC := '0'; + SIGNAL nlillOl1i : STD_LOGIC := '0'; + SIGNAL nlillOl1l : STD_LOGIC := '0'; + SIGNAL nlillOl1O : STD_LOGIC := '0'; + SIGNAL nlillOlii : STD_LOGIC := '0'; + SIGNAL nlillOlil : STD_LOGIC := '0'; + SIGNAL nlillOliO : STD_LOGIC := '0'; + SIGNAL nlillOlli : STD_LOGIC := '0'; + SIGNAL nlillOlll : STD_LOGIC := '0'; + SIGNAL nlillOllO : STD_LOGIC := '0'; + SIGNAL nlillOlOl : STD_LOGIC := '0'; + SIGNAL nlilOilli : STD_LOGIC := '0'; + SIGNAL nlilOilll : STD_LOGIC := '0'; + SIGNAL nlilOillO : STD_LOGIC := '0'; + SIGNAL nlilOilOi : STD_LOGIC := '0'; + SIGNAL nlilOilOl : STD_LOGIC := '0'; + SIGNAL nlilOilOO : STD_LOGIC := '0'; + SIGNAL nlilOiO0i : STD_LOGIC := '0'; + SIGNAL nlilOiO0l : STD_LOGIC := '0'; + SIGNAL nlilOiO0O : STD_LOGIC := '0'; + SIGNAL nlilOiO1i : STD_LOGIC := '0'; + SIGNAL nlilOiO1l : STD_LOGIC := '0'; + SIGNAL nlilOiO1O : STD_LOGIC := '0'; + SIGNAL nlilOiOii : STD_LOGIC := '0'; + SIGNAL nlilOiOil : STD_LOGIC := '0'; + SIGNAL nlilOiOiO : STD_LOGIC := '0'; + SIGNAL nlilOiOli : STD_LOGIC := '0'; + SIGNAL nlilOiOll : STD_LOGIC := '0'; + SIGNAL nlilOiOlO : STD_LOGIC := '0'; + SIGNAL nlilOiOOi : STD_LOGIC := '0'; + SIGNAL nlilOiOOl : STD_LOGIC := '0'; + SIGNAL nlilOO0iO : STD_LOGIC := '0'; + SIGNAL nlilOO0li : STD_LOGIC := '0'; + SIGNAL nlilOO0ll : STD_LOGIC := '0'; + SIGNAL nliO0i0l : STD_LOGIC := '0'; + SIGNAL nliO0i0O : STD_LOGIC := '0'; + SIGNAL nliO0iii : STD_LOGIC := '0'; + SIGNAL nliO0iil : STD_LOGIC := '0'; + SIGNAL nliO0iiO : STD_LOGIC := '0'; + SIGNAL nliO0ili : STD_LOGIC := '0'; + SIGNAL nliO0ill : STD_LOGIC := '0'; + SIGNAL nliO0ilO : STD_LOGIC := '0'; + SIGNAL nliO0iOi : STD_LOGIC := '0'; + SIGNAL nliO0iOl : STD_LOGIC := '0'; + SIGNAL nliO0iOO : STD_LOGIC := '0'; + SIGNAL nliO0l0i : STD_LOGIC := '0'; + SIGNAL nliO0l0l : STD_LOGIC := '0'; + SIGNAL nliO0l0O : STD_LOGIC := '0'; + SIGNAL nliO0l1i : STD_LOGIC := '0'; + SIGNAL nliO0l1l : STD_LOGIC := '0'; + SIGNAL nliO0l1O : STD_LOGIC := '0'; + SIGNAL nliO0lii : STD_LOGIC := '0'; + SIGNAL nliO0lil : STD_LOGIC := '0'; + SIGNAL nliO0liO : STD_LOGIC := '0'; + SIGNAL nliO0lli : STD_LOGIC := '0'; + SIGNAL nliO0lll : STD_LOGIC := '0'; + SIGNAL nliO0llO : STD_LOGIC := '0'; + SIGNAL nliO0lOi : STD_LOGIC := '0'; + SIGNAL nliO0lOl : STD_LOGIC := '0'; + SIGNAL nliO0lOO : STD_LOGIC := '0'; + SIGNAL nliO0O0i : STD_LOGIC := '0'; + SIGNAL nliO0O0l : STD_LOGIC := '0'; + SIGNAL nliO0O0O : STD_LOGIC := '0'; + SIGNAL nliO0O1i : STD_LOGIC := '0'; + SIGNAL nliO0O1l : STD_LOGIC := '0'; + SIGNAL nliO0O1O : STD_LOGIC := '0'; + SIGNAL nliO0Oii : STD_LOGIC := '0'; + SIGNAL nliO0Oil : STD_LOGIC := '0'; + SIGNAL nliO0OiO : STD_LOGIC := '0'; + SIGNAL nliO0Oli : STD_LOGIC := '0'; + SIGNAL nliO0Oll : STD_LOGIC := '0'; + SIGNAL nliO0OlO : STD_LOGIC := '0'; + SIGNAL nliO0OOi : STD_LOGIC := '0'; + SIGNAL nliO0OOl : STD_LOGIC := '0'; + SIGNAL nliO0OOO : STD_LOGIC := '0'; + SIGNAL nliOi00i : STD_LOGIC := '0'; + SIGNAL nliOi00l : STD_LOGIC := '0'; + SIGNAL nliOi00O : STD_LOGIC := '0'; + SIGNAL nliOi01i : STD_LOGIC := '0'; + SIGNAL nliOi01l : STD_LOGIC := '0'; + SIGNAL nliOi01O : STD_LOGIC := '0'; + SIGNAL nliOi0ii : STD_LOGIC := '0'; + SIGNAL nliOi0il : STD_LOGIC := '0'; + SIGNAL nliOi0iO : STD_LOGIC := '0'; + SIGNAL nliOi0li : STD_LOGIC := '0'; + SIGNAL nliOi0ll : STD_LOGIC := '0'; + SIGNAL nliOi0lO : STD_LOGIC := '0'; + SIGNAL nliOi0Oi : STD_LOGIC := '0'; + SIGNAL nliOi0Ol : STD_LOGIC := '0'; + SIGNAL nliOi0OO : STD_LOGIC := '0'; + SIGNAL nliOi10i : STD_LOGIC := '0'; + SIGNAL nliOi10l : STD_LOGIC := '0'; + SIGNAL nliOi10O : STD_LOGIC := '0'; + SIGNAL nliOi11i : STD_LOGIC := '0'; + SIGNAL nliOi11l : STD_LOGIC := '0'; + SIGNAL nliOi11O : STD_LOGIC := '0'; + SIGNAL nliOi1ii : STD_LOGIC := '0'; + SIGNAL nliOi1il : STD_LOGIC := '0'; + SIGNAL nliOi1iO : STD_LOGIC := '0'; + SIGNAL nliOi1li : STD_LOGIC := '0'; + SIGNAL nliOi1ll : STD_LOGIC := '0'; + SIGNAL nliOi1lO : STD_LOGIC := '0'; + SIGNAL nliOi1Oi : STD_LOGIC := '0'; + SIGNAL nliOi1Ol : STD_LOGIC := '0'; + SIGNAL nliOi1OO : STD_LOGIC := '0'; + SIGNAL nliOii0i : STD_LOGIC := '0'; + SIGNAL nliOii0l : STD_LOGIC := '0'; + SIGNAL nliOii0O : STD_LOGIC := '0'; + SIGNAL nliOii1i : STD_LOGIC := '0'; + SIGNAL nliOii1l : STD_LOGIC := '0'; + SIGNAL nliOii1O : STD_LOGIC := '0'; + SIGNAL nliOiiii : STD_LOGIC := '0'; + SIGNAL nliOiiil : STD_LOGIC := '0'; + SIGNAL nliOiiiO : STD_LOGIC := '0'; + SIGNAL nliOiili : STD_LOGIC := '0'; + SIGNAL nliOiill : STD_LOGIC := '0'; + SIGNAL nliOiilO : STD_LOGIC := '0'; + SIGNAL nliOiiOi : STD_LOGIC := '0'; + SIGNAL nliOiiOl : STD_LOGIC := '0'; + SIGNAL nliOiiOO : STD_LOGIC := '0'; + SIGNAL nliOil0i : STD_LOGIC := '0'; + SIGNAL nliOil0l : STD_LOGIC := '0'; + SIGNAL nliOil0O : STD_LOGIC := '0'; + SIGNAL nliOil1i : STD_LOGIC := '0'; + SIGNAL nliOil1l : STD_LOGIC := '0'; + SIGNAL nliOil1O : STD_LOGIC := '0'; + SIGNAL nliOilii : STD_LOGIC := '0'; + SIGNAL nliOilil : STD_LOGIC := '0'; + SIGNAL nliOiliO : STD_LOGIC := '0'; + SIGNAL nliOilli : STD_LOGIC := '0'; + SIGNAL nliOilll : STD_LOGIC := '0'; + SIGNAL nliOillO : STD_LOGIC := '0'; + SIGNAL nliOilOi : STD_LOGIC := '0'; + SIGNAL nliOilOl : STD_LOGIC := '0'; + SIGNAL nliOilOO : STD_LOGIC := '0'; + SIGNAL nliOiO0i : STD_LOGIC := '0'; + SIGNAL nliOiO0l : STD_LOGIC := '0'; + SIGNAL nliOiO0O : STD_LOGIC := '0'; + SIGNAL nliOiO1i : STD_LOGIC := '0'; + SIGNAL nliOiO1l : STD_LOGIC := '0'; + SIGNAL nliOiO1O : STD_LOGIC := '0'; + SIGNAL nliOiOii : STD_LOGIC := '0'; + SIGNAL nliOiOil : STD_LOGIC := '0'; + SIGNAL nliOiOiO : STD_LOGIC := '0'; + SIGNAL nliOiOli : STD_LOGIC := '0'; + SIGNAL nliOiOll : STD_LOGIC := '0'; + SIGNAL nliOiOlO : STD_LOGIC := '0'; + SIGNAL nliOiOOi : STD_LOGIC := '0'; + SIGNAL nliOiOOl : STD_LOGIC := '0'; + SIGNAL nliOiOOO : STD_LOGIC := '0'; + SIGNAL nliOl00i : STD_LOGIC := '0'; + SIGNAL nliOl00l : STD_LOGIC := '0'; + SIGNAL nliOl00O : STD_LOGIC := '0'; + SIGNAL nliOl01i : STD_LOGIC := '0'; + SIGNAL nliOl01l : STD_LOGIC := '0'; + SIGNAL nliOl01O : STD_LOGIC := '0'; + SIGNAL nliOl0ii : STD_LOGIC := '0'; + SIGNAL nliOl0il : STD_LOGIC := '0'; + SIGNAL nliOl0iO : STD_LOGIC := '0'; + SIGNAL nliOl0li : STD_LOGIC := '0'; + SIGNAL nliOl0ll : STD_LOGIC := '0'; + SIGNAL nliOl0lO : STD_LOGIC := '0'; + SIGNAL nliOl0Oi : STD_LOGIC := '0'; + SIGNAL nliOl0Ol : STD_LOGIC := '0'; + SIGNAL nliOl0OO : STD_LOGIC := '0'; + SIGNAL nliOl10i : STD_LOGIC := '0'; + SIGNAL nliOl10l : STD_LOGIC := '0'; + SIGNAL nliOl10O : STD_LOGIC := '0'; + SIGNAL nliOl11i : STD_LOGIC := '0'; + SIGNAL nliOl11l : STD_LOGIC := '0'; + SIGNAL nliOl11O : STD_LOGIC := '0'; + SIGNAL nliOl1ii : STD_LOGIC := '0'; + SIGNAL nliOl1il : STD_LOGIC := '0'; + SIGNAL nliOl1iO : STD_LOGIC := '0'; + SIGNAL nliOl1li : STD_LOGIC := '0'; + SIGNAL nliOl1ll : STD_LOGIC := '0'; + SIGNAL nliOl1lO : STD_LOGIC := '0'; + SIGNAL nliOl1Oi : STD_LOGIC := '0'; + SIGNAL nliOl1Ol : STD_LOGIC := '0'; + SIGNAL nliOl1OO : STD_LOGIC := '0'; + SIGNAL nliOli0i : STD_LOGIC := '0'; + SIGNAL nliOli0l : STD_LOGIC := '0'; + SIGNAL nliOli0O : STD_LOGIC := '0'; + SIGNAL nliOli1i : STD_LOGIC := '0'; + SIGNAL nliOli1l : STD_LOGIC := '0'; + SIGNAL nliOli1O : STD_LOGIC := '0'; + SIGNAL nliOliii : STD_LOGIC := '0'; + SIGNAL nliOliil : STD_LOGIC := '0'; + SIGNAL nliOliiO : STD_LOGIC := '0'; + SIGNAL nliOlili : STD_LOGIC := '0'; + SIGNAL nliOlill : STD_LOGIC := '0'; + SIGNAL nll0i000i : STD_LOGIC := '0'; + SIGNAL nll0i000l : STD_LOGIC := '0'; + SIGNAL nll0i000O : STD_LOGIC := '0'; + SIGNAL nll0i001i : STD_LOGIC := '0'; + SIGNAL nll0i001l : STD_LOGIC := '0'; + SIGNAL nll0i001O : STD_LOGIC := '0'; + SIGNAL nll0i00ii : STD_LOGIC := '0'; + SIGNAL nll0i00il : STD_LOGIC := '0'; + SIGNAL nll0i00iO : STD_LOGIC := '0'; + SIGNAL nll0i00li : STD_LOGIC := '0'; + SIGNAL nll0i00ll : STD_LOGIC := '0'; + SIGNAL nll0i00lO : STD_LOGIC := '0'; + SIGNAL nll0i00Oi : STD_LOGIC := '0'; + SIGNAL nll0i00Ol : STD_LOGIC := '0'; + SIGNAL nll0i00OO : STD_LOGIC := '0'; + SIGNAL nll0i01Oi : STD_LOGIC := '0'; + SIGNAL nll0i01Ol : STD_LOGIC := '0'; + SIGNAL nll0i01OO : STD_LOGIC := '0'; + SIGNAL nll0i0i0i : STD_LOGIC := '0'; + SIGNAL nll0i0i0l : STD_LOGIC := '0'; + SIGNAL nll0i0i0O : STD_LOGIC := '0'; + SIGNAL nll0i0i1i : STD_LOGIC := '0'; + SIGNAL nll0i0i1l : STD_LOGIC := '0'; + SIGNAL nll0i0i1O : STD_LOGIC := '0'; + SIGNAL nll0i0iii : STD_LOGIC := '0'; + SIGNAL nll0i0iil : STD_LOGIC := '0'; + SIGNAL nll0i0iiO : STD_LOGIC := '0'; + SIGNAL nll0i0ili : STD_LOGIC := '0'; + SIGNAL nll0i0ill : STD_LOGIC := '0'; + SIGNAL nll0i0ilO : STD_LOGIC := '0'; + SIGNAL nll0i0iOi : STD_LOGIC := '0'; + SIGNAL nll0i0iOl : STD_LOGIC := '0'; + SIGNAL nll0i0iOO : STD_LOGIC := '0'; + SIGNAL nll0i0l0i : STD_LOGIC := '0'; + SIGNAL nll0i0l0l : STD_LOGIC := '0'; + SIGNAL nll0i0l0O : STD_LOGIC := '0'; + SIGNAL nll0i0l1i : STD_LOGIC := '0'; + SIGNAL nll0i0l1l : STD_LOGIC := '0'; + SIGNAL nll0i0l1O : STD_LOGIC := '0'; + SIGNAL nll0i0lii : STD_LOGIC := '0'; + SIGNAL nll0i0lil : STD_LOGIC := '0'; + SIGNAL nll0i0liO : STD_LOGIC := '0'; + SIGNAL nll0i0lli : STD_LOGIC := '0'; + SIGNAL nll0i0lll : STD_LOGIC := '0'; + SIGNAL nll0i0llO : STD_LOGIC := '0'; + SIGNAL nll0i0lOi : STD_LOGIC := '0'; + SIGNAL nll0i0lOl : STD_LOGIC := '0'; + SIGNAL nll0i0lOO : STD_LOGIC := '0'; + SIGNAL nll0i0O0i : STD_LOGIC := '0'; + SIGNAL nll0i0O0l : STD_LOGIC := '0'; + SIGNAL nll0i0O0O : STD_LOGIC := '0'; + SIGNAL nll0i0O1i : STD_LOGIC := '0'; + SIGNAL nll0i0O1l : STD_LOGIC := '0'; + SIGNAL nll0i0O1O : STD_LOGIC := '0'; + SIGNAL nll0i0Oii : STD_LOGIC := '0'; + SIGNAL nll0i0Oil : STD_LOGIC := '0'; + SIGNAL nll0i0OiO : STD_LOGIC := '0'; + SIGNAL nll0i0Oli : STD_LOGIC := '0'; + SIGNAL nll0i0Oll : STD_LOGIC := '0'; + SIGNAL nll0i0OlO : STD_LOGIC := '0'; + SIGNAL nll0i0OOi : STD_LOGIC := '0'; + SIGNAL nll0i0OOl : STD_LOGIC := '0'; + SIGNAL nll0i0OOO : STD_LOGIC := '0'; + SIGNAL nll0iO1lO : STD_LOGIC := '0'; + SIGNAL nll0liiOi : STD_LOGIC := '0'; + SIGNAL nll0liiOl : STD_LOGIC := '0'; + SIGNAL nll0liiOO : STD_LOGIC := '0'; + SIGNAL nll0lilil : STD_LOGIC := '0'; + SIGNAL nll0liOii : STD_LOGIC := '0'; + SIGNAL nll0liOil : STD_LOGIC := '0'; + SIGNAL nll0liOiO : STD_LOGIC := '0'; + SIGNAL nll0liOli : STD_LOGIC := '0'; + SIGNAL nll0liOll : STD_LOGIC := '0'; + SIGNAL nll0liOlO : STD_LOGIC := '0'; + SIGNAL nll0liOOi : STD_LOGIC := '0'; + SIGNAL nll0liOOl : STD_LOGIC := '0'; + SIGNAL nll0liOOO : STD_LOGIC := '0'; + SIGNAL nll0ll10i : STD_LOGIC := '0'; + SIGNAL nll0ll10l : STD_LOGIC := '0'; + SIGNAL nll0ll10O : STD_LOGIC := '0'; + SIGNAL nll0ll11i : STD_LOGIC := '0'; + SIGNAL nll0ll11l : STD_LOGIC := '0'; + SIGNAL nll0ll11O : STD_LOGIC := '0'; + SIGNAL nll0ll1ii : STD_LOGIC := '0'; + SIGNAL nll0ll1il : STD_LOGIC := '0'; + SIGNAL nll0ll1iO : STD_LOGIC := '0'; + SIGNAL nll0ll1li : STD_LOGIC := '0'; + SIGNAL nll0ll1ll : STD_LOGIC := '0'; + SIGNAL nll0ll1lO : STD_LOGIC := '0'; + SIGNAL nll0ll1Oi : STD_LOGIC := '0'; + SIGNAL nll0ll1Ol : STD_LOGIC := '0'; + SIGNAL nll0ll1OO : STD_LOGIC := '0'; + SIGNAL nll0lO01i : STD_LOGIC := '0'; + SIGNAL nll0lO0ii : STD_LOGIC := '0'; + SIGNAL nll0lO0il : STD_LOGIC := '0'; + SIGNAL nll0lO0iO : STD_LOGIC := '0'; + SIGNAL nll0lO0li : STD_LOGIC := '0'; + SIGNAL nll0lO0ll : STD_LOGIC := '0'; + SIGNAL nll0lO0lO : STD_LOGIC := '0'; + SIGNAL nll0lO0Oi : STD_LOGIC := '0'; + SIGNAL nll0lO0Ol : STD_LOGIC := '0'; + SIGNAL nll0lO0OO : STD_LOGIC := '0'; + SIGNAL nll0lOi1i : STD_LOGIC := '0'; + SIGNAL nll0lOi1l : STD_LOGIC := '0'; + SIGNAL nll0lOi1O : STD_LOGIC := '0'; + SIGNAL nll0O0i0i : STD_LOGIC := '0'; + SIGNAL nll0O0i0l : STD_LOGIC := '0'; + SIGNAL nll0O0i0O : STD_LOGIC := '0'; + SIGNAL nll0O0i1O : STD_LOGIC := '0'; + SIGNAL nll0O0iii : STD_LOGIC := '0'; + SIGNAL nll0O0iil : STD_LOGIC := '0'; + SIGNAL nll0O0iiO : STD_LOGIC := '0'; + SIGNAL nll0O0ili : STD_LOGIC := '0'; + SIGNAL nll0O0ill : STD_LOGIC := '0'; + SIGNAL nll0O0ilO : STD_LOGIC := '0'; + SIGNAL nll0O0iOi : STD_LOGIC := '0'; + SIGNAL nll0O0iOl : STD_LOGIC := '0'; + SIGNAL nll0O0iOO : STD_LOGIC := '0'; + SIGNAL nll0O0l0i : STD_LOGIC := '0'; + SIGNAL nll0O0l0l : STD_LOGIC := '0'; + SIGNAL nll0O0l0O : STD_LOGIC := '0'; + SIGNAL nll0O0l1i : STD_LOGIC := '0'; + SIGNAL nll0O0l1l : STD_LOGIC := '0'; + SIGNAL nll0O0l1O : STD_LOGIC := '0'; + SIGNAL nll0O0lii : STD_LOGIC := '0'; + SIGNAL nll0O0lil : STD_LOGIC := '0'; + SIGNAL nll0O0liO : STD_LOGIC := '0'; + SIGNAL nll0O0lli : STD_LOGIC := '0'; + SIGNAL nll0O0lll : STD_LOGIC := '0'; + SIGNAL nll0O0llO : STD_LOGIC := '0'; + SIGNAL nll0O0lO : STD_LOGIC := '0'; + SIGNAL nll0O0lOi : STD_LOGIC := '0'; + SIGNAL nll0O0lOl : STD_LOGIC := '0'; + SIGNAL nll0O0lOO : STD_LOGIC := '0'; + SIGNAL nll0O0O0i : STD_LOGIC := '0'; + SIGNAL nll0O0O0l : STD_LOGIC := '0'; + SIGNAL nll0O0O0O : STD_LOGIC := '0'; + SIGNAL nll0O0O1i : STD_LOGIC := '0'; + SIGNAL nll0O0O1l : STD_LOGIC := '0'; + SIGNAL nll0O0O1O : STD_LOGIC := '0'; + SIGNAL nll0O0Oi : STD_LOGIC := '0'; + SIGNAL nll0O0Oii : STD_LOGIC := '0'; + SIGNAL nll0O0Oil : STD_LOGIC := '0'; + SIGNAL nll0O0OiO : STD_LOGIC := '0'; + SIGNAL nll0O0Ol : STD_LOGIC := '0'; + SIGNAL nll0O0Oli : STD_LOGIC := '0'; + SIGNAL nll0O0Oll : STD_LOGIC := '0'; + SIGNAL nll0O0OlO : STD_LOGIC := '0'; + SIGNAL nll0O0OO : STD_LOGIC := '0'; + SIGNAL nll0O0OOi : STD_LOGIC := '0'; + SIGNAL nll0O0OOl : STD_LOGIC := '0'; + SIGNAL nll0O0OOO : STD_LOGIC := '0'; + SIGNAL nll0O100i : STD_LOGIC := '0'; + SIGNAL nll0O100l : STD_LOGIC := '0'; + SIGNAL nll0O100O : STD_LOGIC := '0'; + SIGNAL nll0O101i : STD_LOGIC := '0'; + SIGNAL nll0O101l : STD_LOGIC := '0'; + SIGNAL nll0O101O : STD_LOGIC := '0'; + SIGNAL nll0O10ii : STD_LOGIC := '0'; + SIGNAL nll0O10il : STD_LOGIC := '0'; + SIGNAL nll0O10iO : STD_LOGIC := '0'; + SIGNAL nll0O10li : STD_LOGIC := '0'; + SIGNAL nll0O10ll : STD_LOGIC := '0'; + SIGNAL nll0O10lO : STD_LOGIC := '0'; + SIGNAL nll0O10Oi : STD_LOGIC := '0'; + SIGNAL nll0O10Ol : STD_LOGIC := '0'; + SIGNAL nll0O10OO : STD_LOGIC := '0'; + SIGNAL nll0O11ii : STD_LOGIC := '0'; + SIGNAL nll0O11il : STD_LOGIC := '0'; + SIGNAL nll0O11iO : STD_LOGIC := '0'; + SIGNAL nll0O11li : STD_LOGIC := '0'; + SIGNAL nll0O11ll : STD_LOGIC := '0'; + SIGNAL nll0O11lO : STD_LOGIC := '0'; + SIGNAL nll0O11Oi : STD_LOGIC := '0'; + SIGNAL nll0O11Ol : STD_LOGIC := '0'; + SIGNAL nll0O11OO : STD_LOGIC := '0'; + SIGNAL nll0O1i1i : STD_LOGIC := '0'; + SIGNAL nll0O1i1l : STD_LOGIC := '0'; + SIGNAL nll0Oi00i : STD_LOGIC := '0'; + SIGNAL nll0Oi00l : STD_LOGIC := '0'; + SIGNAL nll0Oi00O : STD_LOGIC := '0'; + SIGNAL nll0Oi01i : STD_LOGIC := '0'; + SIGNAL nll0Oi01l : STD_LOGIC := '0'; + SIGNAL nll0Oi01O : STD_LOGIC := '0'; + SIGNAL nll0Oi0i : STD_LOGIC := '0'; + SIGNAL nll0Oi0ii : STD_LOGIC := '0'; + SIGNAL nll0Oi0il : STD_LOGIC := '0'; + SIGNAL nll0Oi0iO : STD_LOGIC := '0'; + SIGNAL nll0Oi0l : STD_LOGIC := '0'; + SIGNAL nll0Oi0li : STD_LOGIC := '0'; + SIGNAL nll0Oi0ll : STD_LOGIC := '0'; + SIGNAL nll0Oi0lO : STD_LOGIC := '0'; + SIGNAL nll0Oi0O : STD_LOGIC := '0'; + SIGNAL nll0Oi0Oi : STD_LOGIC := '0'; + SIGNAL nll0Oi0Ol : STD_LOGIC := '0'; + SIGNAL nll0Oi0OO : STD_LOGIC := '0'; + SIGNAL nll0Oi10i : STD_LOGIC := '0'; + SIGNAL nll0Oi10l : STD_LOGIC := '0'; + SIGNAL nll0Oi10O : STD_LOGIC := '0'; + SIGNAL nll0Oi11i : STD_LOGIC := '0'; + SIGNAL nll0Oi11l : STD_LOGIC := '0'; + SIGNAL nll0Oi11O : STD_LOGIC := '0'; + SIGNAL nll0Oi1i : STD_LOGIC := '0'; + SIGNAL nll0Oi1ii : STD_LOGIC := '0'; + SIGNAL nll0Oi1il : STD_LOGIC := '0'; + SIGNAL nll0Oi1iO : STD_LOGIC := '0'; + SIGNAL nll0Oi1l : STD_LOGIC := '0'; + SIGNAL nll0Oi1li : STD_LOGIC := '0'; + SIGNAL nll0Oi1ll : STD_LOGIC := '0'; + SIGNAL nll0Oi1lO : STD_LOGIC := '0'; + SIGNAL nll0Oi1O : STD_LOGIC := '0'; + SIGNAL nll0Oi1Oi : STD_LOGIC := '0'; + SIGNAL nll0Oi1Ol : STD_LOGIC := '0'; + SIGNAL nll0Oi1OO : STD_LOGIC := '0'; + SIGNAL nll0Oii0i : STD_LOGIC := '0'; + SIGNAL nll0Oii1i : STD_LOGIC := '0'; + SIGNAL nll0Oii1l : STD_LOGIC := '0'; + SIGNAL nll0Oii1O : STD_LOGIC := '0'; + SIGNAL nll0Oiii : STD_LOGIC := '0'; + SIGNAL nll0Oiil : STD_LOGIC := '0'; + SIGNAL nll0OiiO : STD_LOGIC := '0'; + SIGNAL nll0Oili : STD_LOGIC := '0'; + SIGNAL nll0OilO : STD_LOGIC := '0'; + SIGNAL nll0OiOi : STD_LOGIC := '0'; + SIGNAL nll0OiOl : STD_LOGIC := '0'; + SIGNAL nll0OiOO : STD_LOGIC := '0'; + SIGNAL nll0Ol0i : STD_LOGIC := '0'; + SIGNAL nll0Ol0l : STD_LOGIC := '0'; + SIGNAL nll0Ol1i : STD_LOGIC := '0'; + SIGNAL nll0Ol1l : STD_LOGIC := '0'; + SIGNAL nll0Ol1O : STD_LOGIC := '0'; + SIGNAL nll0OOOll : STD_LOGIC := '0'; + SIGNAL nll0OOOlO : STD_LOGIC := '0'; + SIGNAL nll0OOOOi : STD_LOGIC := '0'; + SIGNAL nll0OOOOl : STD_LOGIC := '0'; + SIGNAL nll100Oil : STD_LOGIC := '0'; + SIGNAL nll11lOli : STD_LOGIC := '0'; + SIGNAL nll11lOll : STD_LOGIC := '0'; + SIGNAL nll11lOlO : STD_LOGIC := '0'; + SIGNAL nll11lOOi : STD_LOGIC := '0'; + SIGNAL nll11lOOl : STD_LOGIC := '0'; + SIGNAL nll11lOOO : STD_LOGIC := '0'; + SIGNAL nll11O00i : STD_LOGIC := '0'; + SIGNAL nll11O00l : STD_LOGIC := '0'; + SIGNAL nll11O00O : STD_LOGIC := '0'; + SIGNAL nll11O01i : STD_LOGIC := '0'; + SIGNAL nll11O01l : STD_LOGIC := '0'; + SIGNAL nll11O01O : STD_LOGIC := '0'; + SIGNAL nll11O0ii : STD_LOGIC := '0'; + SIGNAL nll11O0il : STD_LOGIC := '0'; + SIGNAL nll11O0iO : STD_LOGIC := '0'; + SIGNAL nll11O0li : STD_LOGIC := '0'; + SIGNAL nll11O0ll : STD_LOGIC := '0'; + SIGNAL nll11O0lO : STD_LOGIC := '0'; + SIGNAL nll11O0Oi : STD_LOGIC := '0'; + SIGNAL nll11O0Ol : STD_LOGIC := '0'; + SIGNAL nll11O0OO : STD_LOGIC := '0'; + SIGNAL nll11O10i : STD_LOGIC := '0'; + SIGNAL nll11O10l : STD_LOGIC := '0'; + SIGNAL nll11O10O : STD_LOGIC := '0'; + SIGNAL nll11O11i : STD_LOGIC := '0'; + SIGNAL nll11O11l : STD_LOGIC := '0'; + SIGNAL nll11O11O : STD_LOGIC := '0'; + SIGNAL nll11O1ii : STD_LOGIC := '0'; + SIGNAL nll11O1il : STD_LOGIC := '0'; + SIGNAL nll11O1iO : STD_LOGIC := '0'; + SIGNAL nll11O1li : STD_LOGIC := '0'; + SIGNAL nll11O1ll : STD_LOGIC := '0'; + SIGNAL nll11O1lO : STD_LOGIC := '0'; + SIGNAL nll11O1Oi : STD_LOGIC := '0'; + SIGNAL nll11O1Ol : STD_LOGIC := '0'; + SIGNAL nll11O1OO : STD_LOGIC := '0'; + SIGNAL nll11Oi0i : STD_LOGIC := '0'; + SIGNAL nll11Oi0l : STD_LOGIC := '0'; + SIGNAL nll11Oi0O : STD_LOGIC := '0'; + SIGNAL nll11Oi1i : STD_LOGIC := '0'; + SIGNAL nll11Oi1l : STD_LOGIC := '0'; + SIGNAL nll11Oi1O : STD_LOGIC := '0'; + SIGNAL nll11Oiii : STD_LOGIC := '0'; + SIGNAL nll11Oiil : STD_LOGIC := '0'; + SIGNAL nll11OiiO : STD_LOGIC := '0'; + SIGNAL nll11Oili : STD_LOGIC := '0'; + SIGNAL nll11Oill : STD_LOGIC := '0'; + SIGNAL nll11OilO : STD_LOGIC := '0'; + SIGNAL nll11OiOi : STD_LOGIC := '0'; + SIGNAL nll11OiOl : STD_LOGIC := '0'; + SIGNAL nll11OiOO : STD_LOGIC := '0'; + SIGNAL nll11Ol0i : STD_LOGIC := '0'; + SIGNAL nll11Ol0l : STD_LOGIC := '0'; + SIGNAL nll11Ol0O : STD_LOGIC := '0'; + SIGNAL nll11Ol1i : STD_LOGIC := '0'; + SIGNAL nll11Ol1l : STD_LOGIC := '0'; + SIGNAL nll11Ol1O : STD_LOGIC := '0'; + SIGNAL nll11Olii : STD_LOGIC := '0'; + SIGNAL nll11Olil : STD_LOGIC := '0'; + SIGNAL nll11OliO : STD_LOGIC := '0'; + SIGNAL nll11Olli : STD_LOGIC := '0'; + SIGNAL nll11Olll : STD_LOGIC := '0'; + SIGNAL nll11OllO : STD_LOGIC := '0'; + SIGNAL nlli0i00i : STD_LOGIC := '0'; + SIGNAL nlli0i00l : STD_LOGIC := '0'; + SIGNAL nlli0i00O : STD_LOGIC := '0'; + SIGNAL nlli0i01i : STD_LOGIC := '0'; + SIGNAL nlli0i01l : STD_LOGIC := '0'; + SIGNAL nlli0i01O : STD_LOGIC := '0'; + SIGNAL nlli0i0ii : STD_LOGIC := '0'; + SIGNAL nlli0i0il : STD_LOGIC := '0'; + SIGNAL nlli0i0iO : STD_LOGIC := '0'; + SIGNAL nlli0i0li : STD_LOGIC := '0'; + SIGNAL nlli0i0ll : STD_LOGIC := '0'; + SIGNAL nlli0i0lO : STD_LOGIC := '0'; + SIGNAL nlli0i0Oi : STD_LOGIC := '0'; + SIGNAL nlli0i0Ol : STD_LOGIC := '0'; + SIGNAL nlli0i0OO : STD_LOGIC := '0'; + SIGNAL nlli0i1lO : STD_LOGIC := '0'; + SIGNAL nlli0i1Oi : STD_LOGIC := '0'; + SIGNAL nlli0i1Ol : STD_LOGIC := '0'; + SIGNAL nlli0i1OO : STD_LOGIC := '0'; + SIGNAL nlli0ii0i : STD_LOGIC := '0'; + SIGNAL nlli0ii0l : STD_LOGIC := '0'; + SIGNAL nlli0ii0O : STD_LOGIC := '0'; + SIGNAL nlli0ii1i : STD_LOGIC := '0'; + SIGNAL nlli0ii1l : STD_LOGIC := '0'; + SIGNAL nlli0ii1O : STD_LOGIC := '0'; + SIGNAL nlli0iiii : STD_LOGIC := '0'; + SIGNAL nlli0iiil : STD_LOGIC := '0'; + SIGNAL nlli0iiiO : STD_LOGIC := '0'; + SIGNAL nlli0iili : STD_LOGIC := '0'; + SIGNAL nlli0iill : STD_LOGIC := '0'; + SIGNAL nlli0iilO : STD_LOGIC := '0'; + SIGNAL nlli0iiOi : STD_LOGIC := '0'; + SIGNAL nlli0iiOl : STD_LOGIC := '0'; + SIGNAL nlli0iiOO : STD_LOGIC := '0'; + SIGNAL nlli0il0i : STD_LOGIC := '0'; + SIGNAL nlli0il0l : STD_LOGIC := '0'; + SIGNAL nlli0il0O : STD_LOGIC := '0'; + SIGNAL nlli0il1i : STD_LOGIC := '0'; + SIGNAL nlli0il1l : STD_LOGIC := '0'; + SIGNAL nlli0il1O : STD_LOGIC := '0'; + SIGNAL nlli0ilii : STD_LOGIC := '0'; + SIGNAL nlli0ilil : STD_LOGIC := '0'; + SIGNAL nlli0iliO : STD_LOGIC := '0'; + SIGNAL nlli0illi : STD_LOGIC := '0'; + SIGNAL nlli0illl : STD_LOGIC := '0'; + SIGNAL nlli0illO : STD_LOGIC := '0'; + SIGNAL nlli0ilOi : STD_LOGIC := '0'; + SIGNAL nlli0ilOl : STD_LOGIC := '0'; + SIGNAL nlli0ilOO : STD_LOGIC := '0'; + SIGNAL nlli0iO1i : STD_LOGIC := '0'; + SIGNAL nlli0iO1l : STD_LOGIC := '0'; + SIGNAL nlli0iO1O : STD_LOGIC := '0'; + SIGNAL nlli1010i : STD_LOGIC := '0'; + SIGNAL nlli1010l : STD_LOGIC := '0'; + SIGNAL nlli1010O : STD_LOGIC := '0'; + SIGNAL nlli1011i : STD_LOGIC := '0'; + SIGNAL nlli1011l : STD_LOGIC := '0'; + SIGNAL nlli1011O : STD_LOGIC := '0'; + SIGNAL nlli101ii : STD_LOGIC := '0'; + SIGNAL nlli101il : STD_LOGIC := '0'; + SIGNAL nlli101iO : STD_LOGIC := '0'; + SIGNAL nlli101li : STD_LOGIC := '0'; + SIGNAL nlli101ll : STD_LOGIC := '0'; + SIGNAL nlli1100O : STD_LOGIC := '0'; + SIGNAL nlli11i1l : STD_LOGIC := '0'; + SIGNAL nlli11lli : STD_LOGIC := '0'; + SIGNAL nlli11lll : STD_LOGIC := '0'; + SIGNAL nlli11llO : STD_LOGIC := '0'; + SIGNAL nlli11lOi : STD_LOGIC := '0'; + SIGNAL nlli11lOl : STD_LOGIC := '0'; + SIGNAL nlli11lOO : STD_LOGIC := '0'; + SIGNAL nlli11O0i : STD_LOGIC := '0'; + SIGNAL nlli11O0l : STD_LOGIC := '0'; + SIGNAL nlli11O0O : STD_LOGIC := '0'; + SIGNAL nlli11O1i : STD_LOGIC := '0'; + SIGNAL nlli11O1l : STD_LOGIC := '0'; + SIGNAL nlli11O1O : STD_LOGIC := '0'; + SIGNAL nlli11Oii : STD_LOGIC := '0'; + SIGNAL nlli11Oil : STD_LOGIC := '0'; + SIGNAL nlli11OiO : STD_LOGIC := '0'; + SIGNAL nlli11Oli : STD_LOGIC := '0'; + SIGNAL nlli11Oll : STD_LOGIC := '0'; + SIGNAL nlli11OlO : STD_LOGIC := '0'; + SIGNAL nlli11OOi : STD_LOGIC := '0'; + SIGNAL nlli11OOl : STD_LOGIC := '0'; + SIGNAL nlli11OOO : STD_LOGIC := '0'; + SIGNAL nlli1Oi0i : STD_LOGIC := '0'; + SIGNAL nlli1Oili : STD_LOGIC := '0'; + SIGNAL nlli1Oill : STD_LOGIC := '0'; + SIGNAL nlli1OilO : STD_LOGIC := '0'; + SIGNAL nlli1OiOi : STD_LOGIC := '0'; + SIGNAL nlli1OiOl : STD_LOGIC := '0'; + SIGNAL nlli1OiOO : STD_LOGIC := '0'; + SIGNAL nlli1Ol0i : STD_LOGIC := '0'; + SIGNAL nlli1Ol0l : STD_LOGIC := '0'; + SIGNAL nlli1Ol0O : STD_LOGIC := '0'; + SIGNAL nlli1Ol1i : STD_LOGIC := '0'; + SIGNAL nlli1Ol1l : STD_LOGIC := '0'; + SIGNAL nlli1Ol1O : STD_LOGIC := '0'; + SIGNAL nlli1Olii : STD_LOGIC := '0'; + SIGNAL nlli1Olil : STD_LOGIC := '0'; + SIGNAL nlli1OliO : STD_LOGIC := '0'; + SIGNAL nlli1Olli : STD_LOGIC := '0'; + SIGNAL nlli1Olll : STD_LOGIC := '0'; + SIGNAL nlli1OllO : STD_LOGIC := '0'; + SIGNAL nlli1OlOi : STD_LOGIC := '0'; + SIGNAL nlli1OlOl : STD_LOGIC := '0'; + SIGNAL nlli1OlOO : STD_LOGIC := '0'; + SIGNAL nlli1OO1i : STD_LOGIC := '0'; + SIGNAL nlli1OO1l : STD_LOGIC := '0'; + SIGNAL nllii0Oll : STD_LOGIC := '0'; + SIGNAL nllii0OlO : STD_LOGIC := '0'; + SIGNAL nlliii0Oi : STD_LOGIC := '0'; + SIGNAL nlliii0Ol : STD_LOGIC := '0'; + SIGNAL nlliii0OO : STD_LOGIC := '0'; + SIGNAL nlliiii0i : STD_LOGIC := '0'; + SIGNAL nlliiii0l : STD_LOGIC := '0'; + SIGNAL nlliiii0O : STD_LOGIC := '0'; + SIGNAL nlliiii1i : STD_LOGIC := '0'; + SIGNAL nlliiii1l : STD_LOGIC := '0'; + SIGNAL nlliiii1O : STD_LOGIC := '0'; + SIGNAL nlliiiiii : STD_LOGIC := '0'; + SIGNAL nlliiiiil : STD_LOGIC := '0'; + SIGNAL nlliiiiiO : STD_LOGIC := '0'; + SIGNAL nlliiiili : STD_LOGIC := '0'; + SIGNAL nlliiiill : STD_LOGIC := '0'; + SIGNAL nlliiiilO : STD_LOGIC := '0'; + SIGNAL nlliiiiOi : STD_LOGIC := '0'; + SIGNAL nlliiiiOl : STD_LOGIC := '0'; + SIGNAL nlliiiiOO : STD_LOGIC := '0'; + SIGNAL nlliiil0i : STD_LOGIC := '0'; + SIGNAL nlliiil0l : STD_LOGIC := '0'; + SIGNAL nlliiil0O : STD_LOGIC := '0'; + SIGNAL nlliiil1i : STD_LOGIC := '0'; + SIGNAL nlliiil1l : STD_LOGIC := '0'; + SIGNAL nlliiil1O : STD_LOGIC := '0'; + SIGNAL nlliiilii : STD_LOGIC := '0'; + SIGNAL nlliiilil : STD_LOGIC := '0'; + SIGNAL nlliiiliO : STD_LOGIC := '0'; + SIGNAL nlliiilli : STD_LOGIC := '0'; + SIGNAL nlliiilll : STD_LOGIC := '0'; + SIGNAL nlliiillO : STD_LOGIC := '0'; + SIGNAL nlliiilOi : STD_LOGIC := '0'; + SIGNAL nlliiilOl : STD_LOGIC := '0'; + SIGNAL nllili00i : STD_LOGIC := '0'; + SIGNAL nllili00l : STD_LOGIC := '0'; + SIGNAL nllili00O : STD_LOGIC := '0'; + SIGNAL nllili01i : STD_LOGIC := '0'; + SIGNAL nllili01l : STD_LOGIC := '0'; + SIGNAL nllili01O : STD_LOGIC := '0'; + SIGNAL nllili0ii : STD_LOGIC := '0'; + SIGNAL nllili0il : STD_LOGIC := '0'; + SIGNAL nllili0iO : STD_LOGIC := '0'; + SIGNAL nllili0li : STD_LOGIC := '0'; + SIGNAL nllili0ll : STD_LOGIC := '0'; + SIGNAL nllili0lO : STD_LOGIC := '0'; + SIGNAL nllili0Oi : STD_LOGIC := '0'; + SIGNAL nllili0Ol : STD_LOGIC := '0'; + SIGNAL nllili0OO : STD_LOGIC := '0'; + SIGNAL nllili10i : STD_LOGIC := '0'; + SIGNAL nllili10l : STD_LOGIC := '0'; + SIGNAL nllili10O : STD_LOGIC := '0'; + SIGNAL nllili11O : STD_LOGIC := '0'; + SIGNAL nllili1ii : STD_LOGIC := '0'; + SIGNAL nllili1il : STD_LOGIC := '0'; + SIGNAL nllili1iO : STD_LOGIC := '0'; + SIGNAL nllili1li : STD_LOGIC := '0'; + SIGNAL nllili1ll : STD_LOGIC := '0'; + SIGNAL nllili1lO : STD_LOGIC := '0'; + SIGNAL nllili1Oi : STD_LOGIC := '0'; + SIGNAL nllili1Ol : STD_LOGIC := '0'; + SIGNAL nllili1OO : STD_LOGIC := '0'; + SIGNAL nllilii0i : STD_LOGIC := '0'; + SIGNAL nllilii0l : STD_LOGIC := '0'; + SIGNAL nllilii0O : STD_LOGIC := '0'; + SIGNAL nllilii1i : STD_LOGIC := '0'; + SIGNAL nllilii1l : STD_LOGIC := '0'; + SIGNAL nllilii1O : STD_LOGIC := '0'; + SIGNAL nlliliiii : STD_LOGIC := '0'; + SIGNAL nlliliiil : STD_LOGIC := '0'; + SIGNAL nlliliiiO : STD_LOGIC := '0'; + SIGNAL nlliliili : STD_LOGIC := '0'; + SIGNAL nlliliill : STD_LOGIC := '0'; + SIGNAL nlliliilO : STD_LOGIC := '0'; + SIGNAL nlliliiOi : STD_LOGIC := '0'; + SIGNAL nlliliiOl : STD_LOGIC := '0'; + SIGNAL nlliliiOO : STD_LOGIC := '0'; + SIGNAL nllilil0i : STD_LOGIC := '0'; + SIGNAL nllilil0l : STD_LOGIC := '0'; + SIGNAL nllilil0O : STD_LOGIC := '0'; + SIGNAL nllilil1i : STD_LOGIC := '0'; + SIGNAL nllilil1l : STD_LOGIC := '0'; + SIGNAL nllilil1O : STD_LOGIC := '0'; + SIGNAL nllillOi : STD_LOGIC := '0'; + SIGNAL nllillOl : STD_LOGIC := '0'; + SIGNAL nllillOO : STD_LOGIC := '0'; + SIGNAL nllilO0i : STD_LOGIC := '0'; + SIGNAL nllilO0l : STD_LOGIC := '0'; + SIGNAL nllilO0O : STD_LOGIC := '0'; + SIGNAL nllilO1i : STD_LOGIC := '0'; + SIGNAL nllilO1l : STD_LOGIC := '0'; + SIGNAL nllilO1O : STD_LOGIC := '0'; + SIGNAL nllilOii : STD_LOGIC := '0'; + SIGNAL nllilOil : STD_LOGIC := '0'; + SIGNAL nllilOiO : STD_LOGIC := '0'; + SIGNAL nllilOli : STD_LOGIC := '0'; + SIGNAL nllilOll : STD_LOGIC := '0'; + SIGNAL nllilOlll : STD_LOGIC := '0'; + SIGNAL nllilOllO : STD_LOGIC := '0'; + SIGNAL nllilOlO : STD_LOGIC := '0'; + SIGNAL nllilOlOi : STD_LOGIC := '0'; + SIGNAL nllilOlOl : STD_LOGIC := '0'; + SIGNAL nllilOlOO : STD_LOGIC := '0'; + SIGNAL nllilOO0i : STD_LOGIC := '0'; + SIGNAL nllilOO0l : STD_LOGIC := '0'; + SIGNAL nllilOO0O : STD_LOGIC := '0'; + SIGNAL nllilOO1i : STD_LOGIC := '0'; + SIGNAL nllilOO1l : STD_LOGIC := '0'; + SIGNAL nllilOO1O : STD_LOGIC := '0'; + SIGNAL nllilOOi : STD_LOGIC := '0'; + SIGNAL nllilOOii : STD_LOGIC := '0'; + SIGNAL nllilOOil : STD_LOGIC := '0'; + SIGNAL nllilOOiO : STD_LOGIC := '0'; + SIGNAL nllilOOl : STD_LOGIC := '0'; + SIGNAL nllilOOli : STD_LOGIC := '0'; + SIGNAL nllilOOll : STD_LOGIC := '0'; + SIGNAL nllilOOlO : STD_LOGIC := '0'; + SIGNAL nllilOOO : STD_LOGIC := '0'; + SIGNAL nllilOOOi : STD_LOGIC := '0'; + SIGNAL nllilOOOl : STD_LOGIC := '0'; + SIGNAL nllilOOOO : STD_LOGIC := '0'; + SIGNAL nlliO01i : STD_LOGIC := '0'; + SIGNAL nlliO101i : STD_LOGIC := '0'; + SIGNAL nlliO10i : STD_LOGIC := '0'; + SIGNAL nlliO10l : STD_LOGIC := '0'; + SIGNAL nlliO10O : STD_LOGIC := '0'; + SIGNAL nlliO110i : STD_LOGIC := '0'; + SIGNAL nlliO110l : STD_LOGIC := '0'; + SIGNAL nlliO110O : STD_LOGIC := '0'; + SIGNAL nlliO111i : STD_LOGIC := '0'; + SIGNAL nlliO111l : STD_LOGIC := '0'; + SIGNAL nlliO111O : STD_LOGIC := '0'; + SIGNAL nlliO11i : STD_LOGIC := '0'; + SIGNAL nlliO11ii : STD_LOGIC := '0'; + SIGNAL nlliO11il : STD_LOGIC := '0'; + SIGNAL nlliO11iO : STD_LOGIC := '0'; + SIGNAL nlliO11l : STD_LOGIC := '0'; + SIGNAL nlliO11li : STD_LOGIC := '0'; + SIGNAL nlliO11ll : STD_LOGIC := '0'; + SIGNAL nlliO11lO : STD_LOGIC := '0'; + SIGNAL nlliO11O : STD_LOGIC := '0'; + SIGNAL nlliO11Oi : STD_LOGIC := '0'; + SIGNAL nlliO11Ol : STD_LOGIC := '0'; + SIGNAL nlliO11OO : STD_LOGIC := '0'; + SIGNAL nlliO1ii : STD_LOGIC := '0'; + SIGNAL nlliO1il : STD_LOGIC := '0'; + SIGNAL nlliO1iO : STD_LOGIC := '0'; + SIGNAL nlliO1li : STD_LOGIC := '0'; + SIGNAL nlliO1ll : STD_LOGIC := '0'; + SIGNAL nlliO1lO : STD_LOGIC := '0'; + SIGNAL nlliO1Oi : STD_LOGIC := '0'; + SIGNAL nlliO1Ol : STD_LOGIC := '0'; + SIGNAL nlliO1OO : STD_LOGIC := '0'; + SIGNAL nlliOl00i : STD_LOGIC := '0'; + SIGNAL nlliOl00l : STD_LOGIC := '0'; + SIGNAL nlliOl00O : STD_LOGIC := '0'; + SIGNAL nlliOl01i : STD_LOGIC := '0'; + SIGNAL nlliOl01l : STD_LOGIC := '0'; + SIGNAL nlliOl01O : STD_LOGIC := '0'; + SIGNAL nlliOl0ii : STD_LOGIC := '0'; + SIGNAL nlliOl0il : STD_LOGIC := '0'; + SIGNAL nlliOl0iO : STD_LOGIC := '0'; + SIGNAL nlliOl0li : STD_LOGIC := '0'; + SIGNAL nlliOl0ll : STD_LOGIC := '0'; + SIGNAL nlliOl0lO : STD_LOGIC := '0'; + SIGNAL nlliOl0Oi : STD_LOGIC := '0'; + SIGNAL nlliOl0Ol : STD_LOGIC := '0'; + SIGNAL nlliOl0OO : STD_LOGIC := '0'; + SIGNAL nlliOl10O : STD_LOGIC := '0'; + SIGNAL nlliOl11l : STD_LOGIC := '0'; + SIGNAL nlliOl1li : STD_LOGIC := '0'; + SIGNAL nlliOl1ll : STD_LOGIC := '0'; + SIGNAL nlliOl1lO : STD_LOGIC := '0'; + SIGNAL nlliOl1Oi : STD_LOGIC := '0'; + SIGNAL nlliOl1Ol : STD_LOGIC := '0'; + SIGNAL nlliOl1OO : STD_LOGIC := '0'; + SIGNAL nlliOli1i : STD_LOGIC := '0'; + SIGNAL nlliOli1l : STD_LOGIC := '0'; + SIGNAL nlliOOiOO : STD_LOGIC := '0'; + SIGNAL nlliOOl0i : STD_LOGIC := '0'; + SIGNAL nlliOOl0l : STD_LOGIC := '0'; + SIGNAL nlliOOl0O : STD_LOGIC := '0'; + SIGNAL nlliOOl1i : STD_LOGIC := '0'; + SIGNAL nlliOOl1l : STD_LOGIC := '0'; + SIGNAL nlliOOl1O : STD_LOGIC := '0'; + SIGNAL nlliOOlii : STD_LOGIC := '0'; + SIGNAL nlliOOlil : STD_LOGIC := '0'; + SIGNAL nlliOOliO : STD_LOGIC := '0'; + SIGNAL nlliOOlli : STD_LOGIC := '0'; + SIGNAL nlliOOlll : STD_LOGIC := '0'; + SIGNAL nlliOOllO : STD_LOGIC := '0'; + SIGNAL nlliOOlOi : STD_LOGIC := '0'; + SIGNAL nlliOOlOl : STD_LOGIC := '0'; + SIGNAL nlll000il : STD_LOGIC := '0'; + SIGNAL nlll000iO : STD_LOGIC := '0'; + SIGNAL nlll000li : STD_LOGIC := '0'; + SIGNAL nlll000ll : STD_LOGIC := '0'; + SIGNAL nlll000lO : STD_LOGIC := '0'; + SIGNAL nlll000Oi : STD_LOGIC := '0'; + SIGNAL nlll000Ol : STD_LOGIC := '0'; + SIGNAL nlll000OO : STD_LOGIC := '0'; + SIGNAL nlll00i0i : STD_LOGIC := '0'; + SIGNAL nlll00i0l : STD_LOGIC := '0'; + SIGNAL nlll00i0O : STD_LOGIC := '0'; + SIGNAL nlll00i1i : STD_LOGIC := '0'; + SIGNAL nlll00i1l : STD_LOGIC := '0'; + SIGNAL nlll00i1O : STD_LOGIC := '0'; + SIGNAL nlll00iii : STD_LOGIC := '0'; + SIGNAL nlll00iil : STD_LOGIC := '0'; + SIGNAL nlll00iiO : STD_LOGIC := '0'; + SIGNAL nlll00ili : STD_LOGIC := '0'; + SIGNAL nlll00ill : STD_LOGIC := '0'; + SIGNAL nlll00ilO : STD_LOGIC := '0'; + SIGNAL nlll00iOi : STD_LOGIC := '0'; + SIGNAL nlll00iOl : STD_LOGIC := '0'; + SIGNAL nlll00iOO : STD_LOGIC := '0'; + SIGNAL nlll00l1i : STD_LOGIC := '0'; + SIGNAL nlll0100i : STD_LOGIC := '0'; + SIGNAL nlll0100l : STD_LOGIC := '0'; + SIGNAL nlll0100O : STD_LOGIC := '0'; + SIGNAL nlll0101i : STD_LOGIC := '0'; + SIGNAL nlll0101l : STD_LOGIC := '0'; + SIGNAL nlll0101O : STD_LOGIC := '0'; + SIGNAL nlll010ii : STD_LOGIC := '0'; + SIGNAL nlll010il : STD_LOGIC := '0'; + SIGNAL nlll010iO : STD_LOGIC := '0'; + SIGNAL nlll010li : STD_LOGIC := '0'; + SIGNAL nlll010ll : STD_LOGIC := '0'; + SIGNAL nlll010lO : STD_LOGIC := '0'; + SIGNAL nlll010Oi : STD_LOGIC := '0'; + SIGNAL nlll010Ol : STD_LOGIC := '0'; + SIGNAL nlll010OO : STD_LOGIC := '0'; + SIGNAL nlll011OO : STD_LOGIC := '0'; + SIGNAL nlll01i1i : STD_LOGIC := '0'; + SIGNAL nlll0il1O : STD_LOGIC := '0'; + SIGNAL nlll0ilOl : STD_LOGIC := '0'; + SIGNAL nlll0ilOO : STD_LOGIC := '0'; + SIGNAL nlll0iO0i : STD_LOGIC := '0'; + SIGNAL nlll0iO0l : STD_LOGIC := '0'; + SIGNAL nlll0iO0O : STD_LOGIC := '0'; + SIGNAL nlll0iO1i : STD_LOGIC := '0'; + SIGNAL nlll0iO1l : STD_LOGIC := '0'; + SIGNAL nlll0iO1O : STD_LOGIC := '0'; + SIGNAL nlll0iOii : STD_LOGIC := '0'; + SIGNAL nlll0iOil : STD_LOGIC := '0'; + SIGNAL nlll0iOiO : STD_LOGIC := '0'; + SIGNAL nlll0iOli : STD_LOGIC := '0'; + SIGNAL nlll0iOll : STD_LOGIC := '0'; + SIGNAL nlll0iOlO : STD_LOGIC := '0'; + SIGNAL nlll0iOOi : STD_LOGIC := '0'; + SIGNAL nlll0iOOl : STD_LOGIC := '0'; + SIGNAL nlll0iOOO : STD_LOGIC := '0'; + SIGNAL nlll0llO : STD_LOGIC := '0'; + SIGNAL nlll11l0l : STD_LOGIC := '0'; + SIGNAL nlll11l0O : STD_LOGIC := '0'; + SIGNAL nlll11lii : STD_LOGIC := '0'; + SIGNAL nlll11lil : STD_LOGIC := '0'; + SIGNAL nlll11liO : STD_LOGIC := '0'; + SIGNAL nlll11lli : STD_LOGIC := '0'; + SIGNAL nlll11lll : STD_LOGIC := '0'; + SIGNAL nlll11llO : STD_LOGIC := '0'; + SIGNAL nlll11lOi : STD_LOGIC := '0'; + SIGNAL nlll11lOl : STD_LOGIC := '0'; + SIGNAL nlll11lOO : STD_LOGIC := '0'; + SIGNAL nlll11O1i : STD_LOGIC := '0'; + SIGNAL nlll11O1l : STD_LOGIC := '0'; + SIGNAL nlll1il0i : STD_LOGIC := '0'; + SIGNAL nlll1il0l : STD_LOGIC := '0'; + SIGNAL nlll1il0O : STD_LOGIC := '0'; + SIGNAL nlll1il1l : STD_LOGIC := '0'; + SIGNAL nlll1il1O : STD_LOGIC := '0'; + SIGNAL nlll1ilii : STD_LOGIC := '0'; + SIGNAL nlll1iliO : STD_LOGIC := '0'; + SIGNAL nlll1llOl : STD_LOGIC := '0'; + SIGNAL nlll1llOO : STD_LOGIC := '0'; + SIGNAL nlll1lO0i : STD_LOGIC := '0'; + SIGNAL nlll1lO0l : STD_LOGIC := '0'; + SIGNAL nlll1lO0O : STD_LOGIC := '0'; + SIGNAL nlll1lO1i : STD_LOGIC := '0'; + SIGNAL nlll1lO1l : STD_LOGIC := '0'; + SIGNAL nlll1lO1O : STD_LOGIC := '0'; + SIGNAL nlll1lOii : STD_LOGIC := '0'; + SIGNAL nlll1lOil : STD_LOGIC := '0'; + SIGNAL nlll1lOiO : STD_LOGIC := '0'; + SIGNAL nlll1lOli : STD_LOGIC := '0'; + SIGNAL nlll1lOll : STD_LOGIC := '0'; + SIGNAL nlll1lOlO : STD_LOGIC := '0'; + SIGNAL nlll1lOOi : STD_LOGIC := '0'; + SIGNAL nlll1lOOl : STD_LOGIC := '0'; + SIGNAL nlll1lOOO : STD_LOGIC := '0'; + SIGNAL nlll1OO0O : STD_LOGIC := '0'; + SIGNAL nlll1OOil : STD_LOGIC := '0'; + SIGNAL nllli0il : STD_LOGIC := '0'; + SIGNAL nllli0Oi : STD_LOGIC := '0'; + SIGNAL nllli0Ol : STD_LOGIC := '0'; + SIGNAL nllli0OO : STD_LOGIC := '0'; + SIGNAL nllli10O : STD_LOGIC := '0'; + SIGNAL nllli1ii : STD_LOGIC := '0'; + SIGNAL nllli1il : STD_LOGIC := '0'; + SIGNAL nlllii0i : STD_LOGIC := '0'; + SIGNAL nlllii0l : STD_LOGIC := '0'; + SIGNAL nlllii0O : STD_LOGIC := '0'; + SIGNAL nlllii1i : STD_LOGIC := '0'; + SIGNAL nlllii1l : STD_LOGIC := '0'; + SIGNAL nlllii1O : STD_LOGIC := '0'; + SIGNAL nllliiii : STD_LOGIC := '0'; + SIGNAL nllliiil : STD_LOGIC := '0'; + SIGNAL nllliiiO : STD_LOGIC := '0'; + SIGNAL nllliili : STD_LOGIC := '0'; + SIGNAL nllliill : STD_LOGIC := '0'; + SIGNAL nllliilO : STD_LOGIC := '0'; + SIGNAL nllliiOi : STD_LOGIC := '0'; + SIGNAL nlllOlll : STD_LOGIC := '0'; + SIGNAL nlllOllO : STD_LOGIC := '0'; + SIGNAL nlllOlOi : STD_LOGIC := '0'; + SIGNAL nlllOlOl : STD_LOGIC := '0'; + SIGNAL nlllOlOO : STD_LOGIC := '0'; + SIGNAL nlllOO0i : STD_LOGIC := '0'; + SIGNAL nlllOO0l : STD_LOGIC := '0'; + SIGNAL nlllOO0O : STD_LOGIC := '0'; + SIGNAL nlllOO1i : STD_LOGIC := '0'; + SIGNAL nlllOO1l : STD_LOGIC := '0'; + SIGNAL nlllOO1O : STD_LOGIC := '0'; + SIGNAL nlllOOii : STD_LOGIC := '0'; + SIGNAL nlllOOil : STD_LOGIC := '0'; + SIGNAL nlllOOiO : STD_LOGIC := '0'; + SIGNAL nlllOOli : STD_LOGIC := '0'; + SIGNAL nlllOOll : STD_LOGIC := '0'; + SIGNAL nlllOOlO : STD_LOGIC := '0'; + SIGNAL nlllOOOi : STD_LOGIC := '0'; + SIGNAL nlllOOOl : STD_LOGIC := '0'; + SIGNAL nlllOOOO : STD_LOGIC := '0'; + SIGNAL nllO000i : STD_LOGIC := '0'; + SIGNAL nllO000l : STD_LOGIC := '0'; + SIGNAL nllO000O : STD_LOGIC := '0'; + SIGNAL nllO001i : STD_LOGIC := '0'; + SIGNAL nllO001l : STD_LOGIC := '0'; + SIGNAL nllO001O : STD_LOGIC := '0'; + SIGNAL nllO00ii : STD_LOGIC := '0'; + SIGNAL nllO00il : STD_LOGIC := '0'; + SIGNAL nllO00iO : STD_LOGIC := '0'; + SIGNAL nllO00li : STD_LOGIC := '0'; + SIGNAL nllO00ll : STD_LOGIC := '0'; + SIGNAL nllO00lO : STD_LOGIC := '0'; + SIGNAL nllO00Oi : STD_LOGIC := '0'; + SIGNAL nllO00Ol : STD_LOGIC := '0'; + SIGNAL nllO00OO : STD_LOGIC := '0'; + SIGNAL nllO010i : STD_LOGIC := '0'; + SIGNAL nllO010l : STD_LOGIC := '0'; + SIGNAL nllO010O : STD_LOGIC := '0'; + SIGNAL nllO011i : STD_LOGIC := '0'; + SIGNAL nllO011l : STD_LOGIC := '0'; + SIGNAL nllO011O : STD_LOGIC := '0'; + SIGNAL nllO01ii : STD_LOGIC := '0'; + SIGNAL nllO01il : STD_LOGIC := '0'; + SIGNAL nllO01iO : STD_LOGIC := '0'; + SIGNAL nllO01li : STD_LOGIC := '0'; + SIGNAL nllO01ll : STD_LOGIC := '0'; + SIGNAL nllO01lO : STD_LOGIC := '0'; + SIGNAL nllO01Oi : STD_LOGIC := '0'; + SIGNAL nllO01Ol : STD_LOGIC := '0'; + SIGNAL nllO01OO : STD_LOGIC := '0'; + SIGNAL nllO0i0i : STD_LOGIC := '0'; + SIGNAL nllO0i0l : STD_LOGIC := '0'; + SIGNAL nllO0i0O : STD_LOGIC := '0'; + SIGNAL nllO0i1i : STD_LOGIC := '0'; + SIGNAL nllO0i1l : STD_LOGIC := '0'; + SIGNAL nllO0i1O : STD_LOGIC := '0'; + SIGNAL nllO100i : STD_LOGIC := '0'; + SIGNAL nllO100l : STD_LOGIC := '0'; + SIGNAL nllO100O : STD_LOGIC := '0'; + SIGNAL nllO101i : STD_LOGIC := '0'; + SIGNAL nllO101l : STD_LOGIC := '0'; + SIGNAL nllO101O : STD_LOGIC := '0'; + SIGNAL nllO10ii : STD_LOGIC := '0'; + SIGNAL nllO10il : STD_LOGIC := '0'; + SIGNAL nllO10iO : STD_LOGIC := '0'; + SIGNAL nllO10li : STD_LOGIC := '0'; + SIGNAL nllO10ll : STD_LOGIC := '0'; + SIGNAL nllO10lO : STD_LOGIC := '0'; + SIGNAL nllO10Oi : STD_LOGIC := '0'; + SIGNAL nllO10Ol : STD_LOGIC := '0'; + SIGNAL nllO10OO : STD_LOGIC := '0'; + SIGNAL nllO110i : STD_LOGIC := '0'; + SIGNAL nllO110l : STD_LOGIC := '0'; + SIGNAL nllO110O : STD_LOGIC := '0'; + SIGNAL nllO111i : STD_LOGIC := '0'; + SIGNAL nllO111l : STD_LOGIC := '0'; + SIGNAL nllO111O : STD_LOGIC := '0'; + SIGNAL nllO11ii : STD_LOGIC := '0'; + SIGNAL nllO11il : STD_LOGIC := '0'; + SIGNAL nllO11iO : STD_LOGIC := '0'; + SIGNAL nllO11li : STD_LOGIC := '0'; + SIGNAL nllO11ll : STD_LOGIC := '0'; + SIGNAL nllO11lO : STD_LOGIC := '0'; + SIGNAL nllO11Oi : STD_LOGIC := '0'; + SIGNAL nllO11Ol : STD_LOGIC := '0'; + SIGNAL nllO11OO : STD_LOGIC := '0'; + SIGNAL nllO1i0i : STD_LOGIC := '0'; + SIGNAL nllO1i0l : STD_LOGIC := '0'; + SIGNAL nllO1i0O : STD_LOGIC := '0'; + SIGNAL nllO1i1i : STD_LOGIC := '0'; + SIGNAL nllO1i1l : STD_LOGIC := '0'; + SIGNAL nllO1i1O : STD_LOGIC := '0'; + SIGNAL nllO1iii : STD_LOGIC := '0'; + SIGNAL nllO1iil : STD_LOGIC := '0'; + SIGNAL nllO1iiO : STD_LOGIC := '0'; + SIGNAL nllO1ili : STD_LOGIC := '0'; + SIGNAL nllO1ill : STD_LOGIC := '0'; + SIGNAL nllO1ilO : STD_LOGIC := '0'; + SIGNAL nllO1iOi : STD_LOGIC := '0'; + SIGNAL nllO1iOl : STD_LOGIC := '0'; + SIGNAL nllO1iOO : STD_LOGIC := '0'; + SIGNAL nllO1l0i : STD_LOGIC := '0'; + SIGNAL nllO1l0l : STD_LOGIC := '0'; + SIGNAL nllO1l0O : STD_LOGIC := '0'; + SIGNAL nllO1l1i : STD_LOGIC := '0'; + SIGNAL nllO1l1l : STD_LOGIC := '0'; + SIGNAL nllO1l1O : STD_LOGIC := '0'; + SIGNAL nllO1lii : STD_LOGIC := '0'; + SIGNAL nllO1lil : STD_LOGIC := '0'; + SIGNAL nllO1liO : STD_LOGIC := '0'; + SIGNAL nllO1lli : STD_LOGIC := '0'; + SIGNAL nllO1lll : STD_LOGIC := '0'; + SIGNAL nllO1llO : STD_LOGIC := '0'; + SIGNAL nllO1lOi : STD_LOGIC := '0'; + SIGNAL nllO1lOl : STD_LOGIC := '0'; + SIGNAL nllO1lOO : STD_LOGIC := '0'; + SIGNAL nllO1O0i : STD_LOGIC := '0'; + SIGNAL nllO1O0l : STD_LOGIC := '0'; + SIGNAL nllO1O0O : STD_LOGIC := '0'; + SIGNAL nllO1O1i : STD_LOGIC := '0'; + SIGNAL nllO1O1l : STD_LOGIC := '0'; + SIGNAL nllO1O1O : STD_LOGIC := '0'; + SIGNAL nllO1Oii : STD_LOGIC := '0'; + SIGNAL nllO1Oil : STD_LOGIC := '0'; + SIGNAL nllO1OiO : STD_LOGIC := '0'; + SIGNAL nllO1Oli : STD_LOGIC := '0'; + SIGNAL nllO1Oll : STD_LOGIC := '0'; + SIGNAL nllO1OlO : STD_LOGIC := '0'; + SIGNAL nllO1OOi : STD_LOGIC := '0'; + SIGNAL nllO1OOl : STD_LOGIC := '0'; + SIGNAL nllO1OOO : STD_LOGIC := '0'; + SIGNAL nllOil00i : STD_LOGIC := '0'; + SIGNAL nllOil00l : STD_LOGIC := '0'; + SIGNAL nllOil00O : STD_LOGIC := '0'; + SIGNAL nllOil01i : STD_LOGIC := '0'; + SIGNAL nllOil01l : STD_LOGIC := '0'; + SIGNAL nllOil01O : STD_LOGIC := '0'; + SIGNAL nllOil0ii : STD_LOGIC := '0'; + SIGNAL nllOil0il : STD_LOGIC := '0'; + SIGNAL nllOil0iO : STD_LOGIC := '0'; + SIGNAL nllOil0li : STD_LOGIC := '0'; + SIGNAL nllOil0ll : STD_LOGIC := '0'; + SIGNAL nllOil0lO : STD_LOGIC := '0'; + SIGNAL nllOil0Oi : STD_LOGIC := '0'; + SIGNAL nllOil0Ol : STD_LOGIC := '0'; + SIGNAL nllOil0OO : STD_LOGIC := '0'; + SIGNAL nllOil10O : STD_LOGIC := '0'; + SIGNAL nllOil1ii : STD_LOGIC := '0'; + SIGNAL nllOil1il : STD_LOGIC := '0'; + SIGNAL nllOil1iO : STD_LOGIC := '0'; + SIGNAL nllOil1li : STD_LOGIC := '0'; + SIGNAL nllOil1ll : STD_LOGIC := '0'; + SIGNAL nllOil1lO : STD_LOGIC := '0'; + SIGNAL nllOil1Oi : STD_LOGIC := '0'; + SIGNAL nllOil1Ol : STD_LOGIC := '0'; + SIGNAL nllOil1OO : STD_LOGIC := '0'; + SIGNAL nllOili0i : STD_LOGIC := '0'; + SIGNAL nllOili0l : STD_LOGIC := '0'; + SIGNAL nllOili0O : STD_LOGIC := '0'; + SIGNAL nllOili1i : STD_LOGIC := '0'; + SIGNAL nllOili1l : STD_LOGIC := '0'; + SIGNAL nllOili1O : STD_LOGIC := '0'; + SIGNAL nllOl11OO : STD_LOGIC := '0'; + SIGNAL nlO00lOiO : STD_LOGIC := '0'; + SIGNAL nlO00lOli : STD_LOGIC := '0'; + SIGNAL nlO00lOll : STD_LOGIC := '0'; + SIGNAL nlO00lOlO : STD_LOGIC := '0'; + SIGNAL nlO00lOOi : STD_LOGIC := '0'; + SIGNAL nlO00lOOl : STD_LOGIC := '0'; + SIGNAL nlO00lOOO : STD_LOGIC := '0'; + SIGNAL nlO00O11i : STD_LOGIC := '0'; + SIGNAL nlO00O11O : STD_LOGIC := '0'; + SIGNAL nlO0il00i : STD_LOGIC := '0'; + SIGNAL nlO0il00l : STD_LOGIC := '0'; + SIGNAL nlO0il00O : STD_LOGIC := '0'; + SIGNAL nlO0il01O : STD_LOGIC := '0'; + SIGNAL nlO0il0ii : STD_LOGIC := '0'; + SIGNAL nlO0il0il : STD_LOGIC := '0'; + SIGNAL nlO0il0iO : STD_LOGIC := '0'; + SIGNAL nlO0il0li : STD_LOGIC := '0'; + SIGNAL nlO0il0ll : STD_LOGIC := '0'; + SIGNAL nlO0il0lO : STD_LOGIC := '0'; + SIGNAL nlO0il0Oi : STD_LOGIC := '0'; + SIGNAL nlO0il0Ol : STD_LOGIC := '0'; + SIGNAL nlO0il0OO : STD_LOGIC := '0'; + SIGNAL nlO0ili0i : STD_LOGIC := '0'; + SIGNAL nlO0ili0l : STD_LOGIC := '0'; + SIGNAL nlO0ili0O : STD_LOGIC := '0'; + SIGNAL nlO0ili1i : STD_LOGIC := '0'; + SIGNAL nlO0ili1l : STD_LOGIC := '0'; + SIGNAL nlO0ili1O : STD_LOGIC := '0'; + SIGNAL nlO0iliii : STD_LOGIC := '0'; + SIGNAL nlO0iliil : STD_LOGIC := '0'; + SIGNAL nlO0iliiO : STD_LOGIC := '0'; + SIGNAL nlO0ilili : STD_LOGIC := '0'; + SIGNAL nlO0ilill : STD_LOGIC := '0'; + SIGNAL nlO0ililO : STD_LOGIC := '0'; + SIGNAL nlO0iliOi : STD_LOGIC := '0'; + SIGNAL nlO0iliOl : STD_LOGIC := '0'; + SIGNAL nlO0iliOO : STD_LOGIC := '0'; + SIGNAL nlO0ill0i : STD_LOGIC := '0'; + SIGNAL nlO0ill0l : STD_LOGIC := '0'; + SIGNAL nlO0ill0O : STD_LOGIC := '0'; + SIGNAL nlO0ill1i : STD_LOGIC := '0'; + SIGNAL nlO0ill1l : STD_LOGIC := '0'; + SIGNAL nlO0ill1O : STD_LOGIC := '0'; + SIGNAL nlO0illii : STD_LOGIC := '0'; + SIGNAL nlO0illil : STD_LOGIC := '0'; + SIGNAL nlO0illiO : STD_LOGIC := '0'; + SIGNAL nlO0illli : STD_LOGIC := '0'; + SIGNAL nlO0illll : STD_LOGIC := '0'; + SIGNAL nlO0illlO : STD_LOGIC := '0'; + SIGNAL nlO0illOi : STD_LOGIC := '0'; + SIGNAL nlO0illOl : STD_LOGIC := '0'; + SIGNAL nlO0illOO : STD_LOGIC := '0'; + SIGNAL nlO0ilO0i : STD_LOGIC := '0'; + SIGNAL nlO0ilO0l : STD_LOGIC := '0'; + SIGNAL nlO0ilO0O : STD_LOGIC := '0'; + SIGNAL nlO0ilO1i : STD_LOGIC := '0'; + SIGNAL nlO0ilO1l : STD_LOGIC := '0'; + SIGNAL nlO0ilO1O : STD_LOGIC := '0'; + SIGNAL nlO0ilOii : STD_LOGIC := '0'; + SIGNAL nlO0ilOil : STD_LOGIC := '0'; + SIGNAL nlO0ilOiO : STD_LOGIC := '0'; + SIGNAL nlO0ilOli : STD_LOGIC := '0'; + SIGNAL nlO0ilOll : STD_LOGIC := '0'; + SIGNAL nlO0ilOlO : STD_LOGIC := '0'; + SIGNAL nlO0ilOOi : STD_LOGIC := '0'; + SIGNAL nlO0ilOOl : STD_LOGIC := '0'; + SIGNAL nlO0ilOOO : STD_LOGIC := '0'; + SIGNAL nlO0iO00i : STD_LOGIC := '0'; + SIGNAL nlO0iO00l : STD_LOGIC := '0'; + SIGNAL nlO0iO00O : STD_LOGIC := '0'; + SIGNAL nlO0iO01i : STD_LOGIC := '0'; + SIGNAL nlO0iO01l : STD_LOGIC := '0'; + SIGNAL nlO0iO01O : STD_LOGIC := '0'; + SIGNAL nlO0iO0ii : STD_LOGIC := '0'; + SIGNAL nlO0iO0il : STD_LOGIC := '0'; + SIGNAL nlO0iO0iO : STD_LOGIC := '0'; + SIGNAL nlO0iO0li : STD_LOGIC := '0'; + SIGNAL nlO0iO0ll : STD_LOGIC := '0'; + SIGNAL nlO0iO0lO : STD_LOGIC := '0'; + SIGNAL nlO0iO0Oi : STD_LOGIC := '0'; + SIGNAL nlO0iO0Ol : STD_LOGIC := '0'; + SIGNAL nlO0iO0OO : STD_LOGIC := '0'; + SIGNAL nlO0iO10i : STD_LOGIC := '0'; + SIGNAL nlO0iO10l : STD_LOGIC := '0'; + SIGNAL nlO0iO10O : STD_LOGIC := '0'; + SIGNAL nlO0iO11i : STD_LOGIC := '0'; + SIGNAL nlO0iO11l : STD_LOGIC := '0'; + SIGNAL nlO0iO11O : STD_LOGIC := '0'; + SIGNAL nlO0iO1ii : STD_LOGIC := '0'; + SIGNAL nlO0iO1il : STD_LOGIC := '0'; + SIGNAL nlO0iO1iO : STD_LOGIC := '0'; + SIGNAL nlO0iO1li : STD_LOGIC := '0'; + SIGNAL nlO0iO1ll : STD_LOGIC := '0'; + SIGNAL nlO0iO1lO : STD_LOGIC := '0'; + SIGNAL nlO0iO1Oi : STD_LOGIC := '0'; + SIGNAL nlO0iO1Ol : STD_LOGIC := '0'; + SIGNAL nlO0iO1OO : STD_LOGIC := '0'; + SIGNAL nlO0iOi0i : STD_LOGIC := '0'; + SIGNAL nlO0iOi0l : STD_LOGIC := '0'; + SIGNAL nlO0iOi0O : STD_LOGIC := '0'; + SIGNAL nlO0iOi1i : STD_LOGIC := '0'; + SIGNAL nlO0iOi1l : STD_LOGIC := '0'; + SIGNAL nlO0iOi1O : STD_LOGIC := '0'; + SIGNAL nlO0iOiii : STD_LOGIC := '0'; + SIGNAL nlO0iOiil : STD_LOGIC := '0'; + SIGNAL nlO0iOiiO : STD_LOGIC := '0'; + SIGNAL nlO0iOili : STD_LOGIC := '0'; + SIGNAL nlO0iOill : STD_LOGIC := '0'; + SIGNAL nlO0iOilO : STD_LOGIC := '0'; + SIGNAL nlO0iOiOi : STD_LOGIC := '0'; + SIGNAL nlO0iOiOl : STD_LOGIC := '0'; + SIGNAL nlO0iOiOO : STD_LOGIC := '0'; + SIGNAL nlO0li0OO : STD_LOGIC := '0'; + SIGNAL nlO0lii0i : STD_LOGIC := '0'; + SIGNAL nlO0lii0l : STD_LOGIC := '0'; + SIGNAL nlO0lii0O : STD_LOGIC := '0'; + SIGNAL nlO0lii1i : STD_LOGIC := '0'; + SIGNAL nlO0lii1l : STD_LOGIC := '0'; + SIGNAL nlO0lii1O : STD_LOGIC := '0'; + SIGNAL nlO0liiii : STD_LOGIC := '0'; + SIGNAL nlO0liiil : STD_LOGIC := '0'; + SIGNAL nlO0liiiO : STD_LOGIC := '0'; + SIGNAL nlO0liili : STD_LOGIC := '0'; + SIGNAL nlO0liill : STD_LOGIC := '0'; + SIGNAL nlO0liilO : STD_LOGIC := '0'; + SIGNAL nlO0liiOi : STD_LOGIC := '0'; + SIGNAL nlO0liiOl : STD_LOGIC := '0'; + SIGNAL nlO0liiOO : STD_LOGIC := '0'; + SIGNAL nlO0lil0i : STD_LOGIC := '0'; + SIGNAL nlO0lil0l : STD_LOGIC := '0'; + SIGNAL nlO0lil0O : STD_LOGIC := '0'; + SIGNAL nlO0lil1i : STD_LOGIC := '0'; + SIGNAL nlO0lil1l : STD_LOGIC := '0'; + SIGNAL nlO0lil1O : STD_LOGIC := '0'; + SIGNAL nlO0lilii : STD_LOGIC := '0'; + SIGNAL nlO0lilil : STD_LOGIC := '0'; + SIGNAL nlO0liliO : STD_LOGIC := '0'; + SIGNAL nlO0lilli : STD_LOGIC := '0'; + SIGNAL nlO0lliO : STD_LOGIC := '0'; + SIGNAL nlO0llli : STD_LOGIC := '0'; + SIGNAL nlO0llll : STD_LOGIC := '0'; + SIGNAL nlO0llOi : STD_LOGIC := '0'; + SIGNAL nlO0Ol00l : STD_LOGIC := '0'; + SIGNAL nlO0Ol00O : STD_LOGIC := '0'; + SIGNAL nlO0Ol0ii : STD_LOGIC := '0'; + SIGNAL nlO0Ol0il : STD_LOGIC := '0'; + SIGNAL nlO0Ol0iO : STD_LOGIC := '0'; + SIGNAL nlO0Ol0li : STD_LOGIC := '0'; + SIGNAL nlO0Ol0ll : STD_LOGIC := '0'; + SIGNAL nlO0Ol0lO : STD_LOGIC := '0'; + SIGNAL nlO0Ol0Oi : STD_LOGIC := '0'; + SIGNAL nlO0Ol0Ol : STD_LOGIC := '0'; + SIGNAL nlO0Ol0OO : STD_LOGIC := '0'; + SIGNAL nlO0Oli0i : STD_LOGIC := '0'; + SIGNAL nlO0Oli0l : STD_LOGIC := '0'; + SIGNAL nlO0Oli0O : STD_LOGIC := '0'; + SIGNAL nlO0Oli1i : STD_LOGIC := '0'; + SIGNAL nlO0Oli1l : STD_LOGIC := '0'; + SIGNAL nlO0Oli1O : STD_LOGIC := '0'; + SIGNAL nlO0Oliii : STD_LOGIC := '0'; + SIGNAL nlO0Oliil : STD_LOGIC := '0'; + SIGNAL nlO0OliiO : STD_LOGIC := '0'; + SIGNAL nlO0Olili : STD_LOGIC := '0'; + SIGNAL nlO0Olill : STD_LOGIC := '0'; + SIGNAL nlO0OlilO : STD_LOGIC := '0'; + SIGNAL nlO0OliOi : STD_LOGIC := '0'; + SIGNAL nlO0OliOl : STD_LOGIC := '0'; + SIGNAL nlO0OliOO : STD_LOGIC := '0'; + SIGNAL nlO0Oll0i : STD_LOGIC := '0'; + SIGNAL nlO0Oll0l : STD_LOGIC := '0'; + SIGNAL nlO0Oll0O : STD_LOGIC := '0'; + SIGNAL nlO0Oll1i : STD_LOGIC := '0'; + SIGNAL nlO0Oll1l : STD_LOGIC := '0'; + SIGNAL nlO0Oll1O : STD_LOGIC := '0'; + SIGNAL nlO0Ollii : STD_LOGIC := '0'; + SIGNAL nlO0Ollil : STD_LOGIC := '0'; + SIGNAL nlO0OlliO : STD_LOGIC := '0'; + SIGNAL nlO0Ollli : STD_LOGIC := '0'; + SIGNAL nlO0Ollll : STD_LOGIC := '0'; + SIGNAL nlO0OlllO : STD_LOGIC := '0'; + SIGNAL nlO0OllOi : STD_LOGIC := '0'; + SIGNAL nlO0OllOl : STD_LOGIC := '0'; + SIGNAL nlO0OllOO : STD_LOGIC := '0'; + SIGNAL nlO0OlO0i : STD_LOGIC := '0'; + SIGNAL nlO0OlO0l : STD_LOGIC := '0'; + SIGNAL nlO0OlO0O : STD_LOGIC := '0'; + SIGNAL nlO0OlO1i : STD_LOGIC := '0'; + SIGNAL nlO0OlO1l : STD_LOGIC := '0'; + SIGNAL nlO0OlO1O : STD_LOGIC := '0'; + SIGNAL nlO0OlOii : STD_LOGIC := '0'; + SIGNAL nlO0OOOO : STD_LOGIC := '0'; + SIGNAL nlO1iiOi : STD_LOGIC := '0'; + SIGNAL nlO1lOi0O : STD_LOGIC := '0'; + SIGNAL nlO1lOiii : STD_LOGIC := '0'; + SIGNAL nlO1lOiil : STD_LOGIC := '0'; + SIGNAL nlO1lOiiO : STD_LOGIC := '0'; + SIGNAL nlO1lOili : STD_LOGIC := '0'; + SIGNAL nlO1lOill : STD_LOGIC := '0'; + SIGNAL nlO1lOilO : STD_LOGIC := '0'; + SIGNAL nlO1lOiOi : STD_LOGIC := '0'; + SIGNAL nlO1lOiOl : STD_LOGIC := '0'; + SIGNAL nlO1lOiOO : STD_LOGIC := '0'; + SIGNAL nlO1lOl0i : STD_LOGIC := '0'; + SIGNAL nlO1lOl0l : STD_LOGIC := '0'; + SIGNAL nlO1lOl0O : STD_LOGIC := '0'; + SIGNAL nlO1lOl1i : STD_LOGIC := '0'; + SIGNAL nlO1lOl1l : STD_LOGIC := '0'; + SIGNAL nlO1lOl1O : STD_LOGIC := '0'; + SIGNAL nlO1lOlii : STD_LOGIC := '0'; + SIGNAL nlO1lOlil : STD_LOGIC := '0'; + SIGNAL nlO1lOliO : STD_LOGIC := '0'; + SIGNAL nlO1lOlli : STD_LOGIC := '0'; + SIGNAL nlO1lOlll : STD_LOGIC := '0'; + SIGNAL nlO1lOllO : STD_LOGIC := '0'; + SIGNAL nlO1lOlOi : STD_LOGIC := '0'; + SIGNAL nlO1lOlOl : STD_LOGIC := '0'; + SIGNAL nlO1lOlOO : STD_LOGIC := '0'; + SIGNAL nlO1lOO0i : STD_LOGIC := '0'; + SIGNAL nlO1lOO0l : STD_LOGIC := '0'; + SIGNAL nlO1lOO0O : STD_LOGIC := '0'; + SIGNAL nlO1lOO1i : STD_LOGIC := '0'; + SIGNAL nlO1lOO1l : STD_LOGIC := '0'; + SIGNAL nlO1lOO1O : STD_LOGIC := '0'; + SIGNAL nlO1O0l1i : STD_LOGIC := '0'; + SIGNAL nlO1O0O0i : STD_LOGIC := '0'; + SIGNAL nlO1Oi00i : STD_LOGIC := '0'; + SIGNAL nlO1Oi00l : STD_LOGIC := '0'; + SIGNAL nlO1Oi00O : STD_LOGIC := '0'; + SIGNAL nlO1Oi01i : STD_LOGIC := '0'; + SIGNAL nlO1Oi01l : STD_LOGIC := '0'; + SIGNAL nlO1Oi01O : STD_LOGIC := '0'; + SIGNAL nlO1Oi0ii : STD_LOGIC := '0'; + SIGNAL nlO1Oi0il : STD_LOGIC := '0'; + SIGNAL nlO1Oi0iO : STD_LOGIC := '0'; + SIGNAL nlO1Oi0li : STD_LOGIC := '0'; + SIGNAL nlO1Oi0ll : STD_LOGIC := '0'; + SIGNAL nlO1Oi0lO : STD_LOGIC := '0'; + SIGNAL nlO1Oi0Oi : STD_LOGIC := '0'; + SIGNAL nlO1Oi0Ol : STD_LOGIC := '0'; + SIGNAL nlO1Oi0OO : STD_LOGIC := '0'; + SIGNAL nlO1Oi10i : STD_LOGIC := '0'; + SIGNAL nlO1Oi10l : STD_LOGIC := '0'; + SIGNAL nlO1Oi10O : STD_LOGIC := '0'; + SIGNAL nlO1Oi1ll : STD_LOGIC := '0'; + SIGNAL nlO1Oi1lO : STD_LOGIC := '0'; + SIGNAL nlO1Oi1Oi : STD_LOGIC := '0'; + SIGNAL nlO1Oi1Ol : STD_LOGIC := '0'; + SIGNAL nlO1Oi1OO : STD_LOGIC := '0'; + SIGNAL nlO1Oii0i : STD_LOGIC := '0'; + SIGNAL nlO1Oii0l : STD_LOGIC := '0'; + SIGNAL nlO1Oii0O : STD_LOGIC := '0'; + SIGNAL nlO1Oii1i : STD_LOGIC := '0'; + SIGNAL nlO1Oii1l : STD_LOGIC := '0'; + SIGNAL nlO1Oii1O : STD_LOGIC := '0'; + SIGNAL nlO1Oiiii : STD_LOGIC := '0'; + SIGNAL nlO1Oiiil : STD_LOGIC := '0'; + SIGNAL nlO1OiiiO : STD_LOGIC := '0'; + SIGNAL nlO1Oiili : STD_LOGIC := '0'; + SIGNAL nlO1Oiill : STD_LOGIC := '0'; + SIGNAL nlO1OiilO : STD_LOGIC := '0'; + SIGNAL nlO1OiiOi : STD_LOGIC := '0'; + SIGNAL nlO1OiiOl : STD_LOGIC := '0'; + SIGNAL nlO1OiiOO : STD_LOGIC := '0'; + SIGNAL nlO1Oil0i : STD_LOGIC := '0'; + SIGNAL nlO1Oil0l : STD_LOGIC := '0'; + SIGNAL nlO1Oil0O : STD_LOGIC := '0'; + SIGNAL nlO1Oil1i : STD_LOGIC := '0'; + SIGNAL nlO1Oil1l : STD_LOGIC := '0'; + SIGNAL nlO1Oil1O : STD_LOGIC := '0'; + SIGNAL nlO1Oilii : STD_LOGIC := '0'; + SIGNAL nlO1Oilil : STD_LOGIC := '0'; + SIGNAL nlO1OiliO : STD_LOGIC := '0'; + SIGNAL nlO1Oilli : STD_LOGIC := '0'; + SIGNAL nlO1Oilll : STD_LOGIC := '0'; + SIGNAL nlO1OillO : STD_LOGIC := '0'; + SIGNAL nlO1OilOi : STD_LOGIC := '0'; + SIGNAL nlO1OilOl : STD_LOGIC := '0'; + SIGNAL nlO1OilOO : STD_LOGIC := '0'; + SIGNAL nlO1OiO0i : STD_LOGIC := '0'; + SIGNAL nlO1OiO0l : STD_LOGIC := '0'; + SIGNAL nlO1OiO0O : STD_LOGIC := '0'; + SIGNAL nlO1OiO1i : STD_LOGIC := '0'; + SIGNAL nlO1OiO1l : STD_LOGIC := '0'; + SIGNAL nlO1OiO1O : STD_LOGIC := '0'; + SIGNAL nlO1OiOii : STD_LOGIC := '0'; + SIGNAL nlO1OiOil : STD_LOGIC := '0'; + SIGNAL nlO1OiOiO : STD_LOGIC := '0'; + SIGNAL nlO1OiOli : STD_LOGIC := '0'; + SIGNAL nlO1OiOll : STD_LOGIC := '0'; + SIGNAL nlO1OiOlO : STD_LOGIC := '0'; + SIGNAL nlO1OiOOi : STD_LOGIC := '0'; + SIGNAL nlO1OiOOl : STD_LOGIC := '0'; + SIGNAL nlO1OiOOO : STD_LOGIC := '0'; + SIGNAL nlO1Ol10i : STD_LOGIC := '0'; + SIGNAL nlO1Ol10l : STD_LOGIC := '0'; + SIGNAL nlO1Ol10O : STD_LOGIC := '0'; + SIGNAL nlO1Ol11i : STD_LOGIC := '0'; + SIGNAL nlO1Ol11l : STD_LOGIC := '0'; + SIGNAL nlO1Ol11O : STD_LOGIC := '0'; + SIGNAL nlO1Ol1ii : STD_LOGIC := '0'; + SIGNAL nlO1Ol1il : STD_LOGIC := '0'; + SIGNAL nlO1Ol1iO : STD_LOGIC := '0'; + SIGNAL nlO1Ol1li : STD_LOGIC := '0'; + SIGNAL nlOi000i : STD_LOGIC := '0'; + SIGNAL nlOi000iO : STD_LOGIC := '0'; + SIGNAL nlOi000l : STD_LOGIC := '0'; + SIGNAL nlOi000O : STD_LOGIC := '0'; + SIGNAL nlOi000Ol : STD_LOGIC := '0'; + SIGNAL nlOi0010l : STD_LOGIC := '0'; + SIGNAL nlOi001i : STD_LOGIC := '0'; + SIGNAL nlOi001ii : STD_LOGIC := '0'; + SIGNAL nlOi001l : STD_LOGIC := '0'; + SIGNAL nlOi001O : STD_LOGIC := '0'; + SIGNAL nlOi00i1i : STD_LOGIC := '0'; + SIGNAL nlOi00ii : STD_LOGIC := '0'; + SIGNAL nlOi00il : STD_LOGIC := '0'; + SIGNAL nlOi00iO : STD_LOGIC := '0'; + SIGNAL nlOi00l0l : STD_LOGIC := '0'; + SIGNAL nlOi00l1i : STD_LOGIC := '0'; + SIGNAL nlOi00li : STD_LOGIC := '0'; + SIGNAL nlOi00lil : STD_LOGIC := '0'; + SIGNAL nlOi00ll : STD_LOGIC := '0'; + SIGNAL nlOi00llO : STD_LOGIC := '0'; + SIGNAL nlOi00lO : STD_LOGIC := '0'; + SIGNAL nlOi00O0l : STD_LOGIC := '0'; + SIGNAL nlOi00Oi : STD_LOGIC := '0'; + SIGNAL nlOi00Ol : STD_LOGIC := '0'; + SIGNAL nlOi00OlO : STD_LOGIC := '0'; + SIGNAL nlOi00OO : STD_LOGIC := '0'; + SIGNAL nlOi010i : STD_LOGIC := '0'; + SIGNAL nlOi010l : STD_LOGIC := '0'; + SIGNAL nlOi010O : STD_LOGIC := '0'; + SIGNAL nlOi011i : STD_LOGIC := '0'; + SIGNAL nlOi011l : STD_LOGIC := '0'; + SIGNAL nlOi011O : STD_LOGIC := '0'; + SIGNAL nlOi01ii : STD_LOGIC := '0'; + SIGNAL nlOi01il : STD_LOGIC := '0'; + SIGNAL nlOi01iO : STD_LOGIC := '0'; + SIGNAL nlOi01li : STD_LOGIC := '0'; + SIGNAL nlOi01ll : STD_LOGIC := '0'; + SIGNAL nlOi01lO : STD_LOGIC := '0'; + SIGNAL nlOi01Oi : STD_LOGIC := '0'; + SIGNAL nlOi01Ol : STD_LOGIC := '0'; + SIGNAL nlOi01OO : STD_LOGIC := '0'; + SIGNAL nlOi01OOO : STD_LOGIC := '0'; + SIGNAL nlOi0i00i : STD_LOGIC := '0'; + SIGNAL nlOi0i0i : STD_LOGIC := '0'; + SIGNAL nlOi0i0l : STD_LOGIC := '0'; + SIGNAL nlOi0i0O : STD_LOGIC := '0'; + SIGNAL nlOi0i10i : STD_LOGIC := '0'; + SIGNAL nlOi0i11l : STD_LOGIC := '0'; + SIGNAL nlOi0i1i : STD_LOGIC := '0'; + SIGNAL nlOi0i1l : STD_LOGIC := '0'; + SIGNAL nlOi0i1O : STD_LOGIC := '0'; + SIGNAL nlOi0iii : STD_LOGIC := '0'; + SIGNAL nlOi0iil : STD_LOGIC := '0'; + SIGNAL nlOi0iiO : STD_LOGIC := '0'; + SIGNAL nlOi0ili : STD_LOGIC := '0'; + SIGNAL nlOi0ill : STD_LOGIC := '0'; + SIGNAL nlOi0ilO : STD_LOGIC := '0'; + SIGNAL nlOi0iOi : STD_LOGIC := '0'; + SIGNAL nlOi0iOl : STD_LOGIC := '0'; + SIGNAL nlOi0iOO : STD_LOGIC := '0'; + SIGNAL nlOi0l00O : STD_LOGIC := '0'; + SIGNAL nlOi0l01O : STD_LOGIC := '0'; + SIGNAL nlOi0l0i : STD_LOGIC := '0'; + SIGNAL nlOi0l0ii : STD_LOGIC := '0'; + SIGNAL nlOi0l0il : STD_LOGIC := '0'; + SIGNAL nlOi0l0iO : STD_LOGIC := '0'; + SIGNAL nlOi0l0l : STD_LOGIC := '0'; + SIGNAL nlOi0l0li : STD_LOGIC := '0'; + SIGNAL nlOi0l0ll : STD_LOGIC := '0'; + SIGNAL nlOi0l0lO : STD_LOGIC := '0'; + SIGNAL nlOi0l0O : STD_LOGIC := '0'; + SIGNAL nlOi0l0Oi : STD_LOGIC := '0'; + SIGNAL nlOi0l0Ol : STD_LOGIC := '0'; + SIGNAL nlOi0l0OO : STD_LOGIC := '0'; + SIGNAL nlOi0l1i : STD_LOGIC := '0'; + SIGNAL nlOi0l1l : STD_LOGIC := '0'; + SIGNAL nlOi0l1ll : STD_LOGIC := '0'; + SIGNAL nlOi0l1O : STD_LOGIC := '0'; + SIGNAL nlOi0li1i : STD_LOGIC := '0'; + SIGNAL nlOi0li1l : STD_LOGIC := '0'; + SIGNAL nlOi0li1O : STD_LOGIC := '0'; + SIGNAL nlOi0lii : STD_LOGIC := '0'; + SIGNAL nlOi0lil : STD_LOGIC := '0'; + SIGNAL nlOi0liO : STD_LOGIC := '0'; + SIGNAL nlOi0lli : STD_LOGIC := '0'; + SIGNAL nlOi0lll : STD_LOGIC := '0'; + SIGNAL nlOi0llO : STD_LOGIC := '0'; + SIGNAL nlOi0lO0l : STD_LOGIC := '0'; + SIGNAL nlOi0lOi : STD_LOGIC := '0'; + SIGNAL nlOi0lOl : STD_LOGIC := '0'; + SIGNAL nlOi0lOO : STD_LOGIC := '0'; + SIGNAL nlOi0lOOl : STD_LOGIC := '0'; + SIGNAL nlOi0O0i : STD_LOGIC := '0'; + SIGNAL nlOi0O0ii : STD_LOGIC := '0'; + SIGNAL nlOi0O0l : STD_LOGIC := '0'; + SIGNAL nlOi0O0lO : STD_LOGIC := '0'; + SIGNAL nlOi0O0O : STD_LOGIC := '0'; + SIGNAL nlOi0O0Ol : STD_LOGIC := '0'; + SIGNAL nlOi0O10O : STD_LOGIC := '0'; + SIGNAL nlOi0O1i : STD_LOGIC := '0'; + SIGNAL nlOi0O1iO : STD_LOGIC := '0'; + SIGNAL nlOi0O1l : STD_LOGIC := '0'; + SIGNAL nlOi0O1O : STD_LOGIC := '0'; + SIGNAL nlOi0Oii : STD_LOGIC := '0'; + SIGNAL nlOi0Oil : STD_LOGIC := '0'; + SIGNAL nlOi0OiO : STD_LOGIC := '0'; + SIGNAL nlOi0Ol0O : STD_LOGIC := '0'; + SIGNAL nlOi0Ol1i : STD_LOGIC := '0'; + SIGNAL nlOi0Oli : STD_LOGIC := '0'; + SIGNAL nlOi0Olil : STD_LOGIC := '0'; + SIGNAL nlOi0Oll : STD_LOGIC := '0'; + SIGNAL nlOi0OlO : STD_LOGIC := '0'; + SIGNAL nlOi0OOi : STD_LOGIC := '0'; + SIGNAL nlOi0OOl : STD_LOGIC := '0'; + SIGNAL nlOi0OOll : STD_LOGIC := '0'; + SIGNAL nlOi0OOO : STD_LOGIC := '0'; + SIGNAL nlOi100i : STD_LOGIC := '0'; + SIGNAL nlOi100l : STD_LOGIC := '0'; + SIGNAL nlOi100O : STD_LOGIC := '0'; + SIGNAL nlOi101i : STD_LOGIC := '0'; + SIGNAL nlOi101l : STD_LOGIC := '0'; + SIGNAL nlOi101O : STD_LOGIC := '0'; + SIGNAL nlOi10ii : STD_LOGIC := '0'; + SIGNAL nlOi10il : STD_LOGIC := '0'; + SIGNAL nlOi10iO : STD_LOGIC := '0'; + SIGNAL nlOi10li : STD_LOGIC := '0'; + SIGNAL nlOi10ll : STD_LOGIC := '0'; + SIGNAL nlOi10lO : STD_LOGIC := '0'; + SIGNAL nlOi10Oi : STD_LOGIC := '0'; + SIGNAL nlOi10Ol : STD_LOGIC := '0'; + SIGNAL nlOi10OO : STD_LOGIC := '0'; + SIGNAL nlOi110i : STD_LOGIC := '0'; + SIGNAL nlOi110l : STD_LOGIC := '0'; + SIGNAL nlOi110O : STD_LOGIC := '0'; + SIGNAL nlOi111i : STD_LOGIC := '0'; + SIGNAL nlOi111l : STD_LOGIC := '0'; + SIGNAL nlOi111O : STD_LOGIC := '0'; + SIGNAL nlOi11ii : STD_LOGIC := '0'; + SIGNAL nlOi11il : STD_LOGIC := '0'; + SIGNAL nlOi11iO : STD_LOGIC := '0'; + SIGNAL nlOi11li : STD_LOGIC := '0'; + SIGNAL nlOi11ll : STD_LOGIC := '0'; + SIGNAL nlOi11lO : STD_LOGIC := '0'; + SIGNAL nlOi11Oi : STD_LOGIC := '0'; + SIGNAL nlOi11Ol : STD_LOGIC := '0'; + SIGNAL nlOi11OO : STD_LOGIC := '0'; + SIGNAL nlOi1i0i : STD_LOGIC := '0'; + SIGNAL nlOi1i0l : STD_LOGIC := '0'; + SIGNAL nlOi1i0O : STD_LOGIC := '0'; + SIGNAL nlOi1i1i : STD_LOGIC := '0'; + SIGNAL nlOi1i1l : STD_LOGIC := '0'; + SIGNAL nlOi1i1O : STD_LOGIC := '0'; + SIGNAL nlOi1iii : STD_LOGIC := '0'; + SIGNAL nlOi1iil : STD_LOGIC := '0'; + SIGNAL nlOi1iiO : STD_LOGIC := '0'; + SIGNAL nlOi1ili : STD_LOGIC := '0'; + SIGNAL nlOi1ill : STD_LOGIC := '0'; + SIGNAL nlOi1ilO : STD_LOGIC := '0'; + SIGNAL nlOi1iOi : STD_LOGIC := '0'; + SIGNAL nlOi1iOl : STD_LOGIC := '0'; + SIGNAL nlOi1iOO : STD_LOGIC := '0'; + SIGNAL nlOi1l0i : STD_LOGIC := '0'; + SIGNAL nlOi1l0l : STD_LOGIC := '0'; + SIGNAL nlOi1l0O : STD_LOGIC := '0'; + SIGNAL nlOi1l1i : STD_LOGIC := '0'; + SIGNAL nlOi1l1l : STD_LOGIC := '0'; + SIGNAL nlOi1l1O : STD_LOGIC := '0'; + SIGNAL nlOi1lii : STD_LOGIC := '0'; + SIGNAL nlOi1lil : STD_LOGIC := '0'; + SIGNAL nlOi1liO : STD_LOGIC := '0'; + SIGNAL nlOi1lli : STD_LOGIC := '0'; + SIGNAL nlOi1lll : STD_LOGIC := '0'; + SIGNAL nlOi1llO : STD_LOGIC := '0'; + SIGNAL nlOi1lOi : STD_LOGIC := '0'; + SIGNAL nlOi1lOl : STD_LOGIC := '0'; + SIGNAL nlOi1lOO : STD_LOGIC := '0'; + SIGNAL nlOi1O0i : STD_LOGIC := '0'; + SIGNAL nlOi1O0l : STD_LOGIC := '0'; + SIGNAL nlOi1O0O : STD_LOGIC := '0'; + SIGNAL nlOi1O1i : STD_LOGIC := '0'; + SIGNAL nlOi1O1l : STD_LOGIC := '0'; + SIGNAL nlOi1O1O : STD_LOGIC := '0'; + SIGNAL nlOi1Oii : STD_LOGIC := '0'; + SIGNAL nlOi1Oil : STD_LOGIC := '0'; + SIGNAL nlOi1Oill : STD_LOGIC := '0'; + SIGNAL nlOi1OilO : STD_LOGIC := '0'; + SIGNAL nlOi1OiO : STD_LOGIC := '0'; + SIGNAL nlOi1OiOi : STD_LOGIC := '0'; + SIGNAL nlOi1OiOl : STD_LOGIC := '0'; + SIGNAL nlOi1OiOO : STD_LOGIC := '0'; + SIGNAL nlOi1Ol1i : STD_LOGIC := '0'; + SIGNAL nlOi1Ol1l : STD_LOGIC := '0'; + SIGNAL nlOi1Ol1O : STD_LOGIC := '0'; + SIGNAL nlOi1Oli : STD_LOGIC := '0'; + SIGNAL nlOi1Oll : STD_LOGIC := '0'; + SIGNAL nlOi1OlO : STD_LOGIC := '0'; + SIGNAL nlOi1OOi : STD_LOGIC := '0'; + SIGNAL nlOi1OOl : STD_LOGIC := '0'; + SIGNAL nlOi1OOO : STD_LOGIC := '0'; + SIGNAL nlOii00i : STD_LOGIC := '0'; + SIGNAL nlOii00l : STD_LOGIC := '0'; + SIGNAL nlOii00O : STD_LOGIC := '0'; + SIGNAL nlOii01i : STD_LOGIC := '0'; + SIGNAL nlOii01ii : STD_LOGIC := '0'; + SIGNAL nlOii01l : STD_LOGIC := '0'; + SIGNAL nlOii01lO : STD_LOGIC := '0'; + SIGNAL nlOii01O : STD_LOGIC := '0'; + SIGNAL nlOii01Ol : STD_LOGIC := '0'; + SIGNAL nlOii0i0O : STD_LOGIC := '0'; + SIGNAL nlOii0i1i : STD_LOGIC := '0'; + SIGNAL nlOii0ii : STD_LOGIC := '0'; + SIGNAL nlOii0iil : STD_LOGIC := '0'; + SIGNAL nlOii0il : STD_LOGIC := '0'; + SIGNAL nlOii0iO : STD_LOGIC := '0'; + SIGNAL nlOii0li : STD_LOGIC := '0'; + SIGNAL nlOii0lil : STD_LOGIC := '0'; + SIGNAL nlOii0ll : STD_LOGIC := '0'; + SIGNAL nlOii0llO : STD_LOGIC := '0'; + SIGNAL nlOii0lO : STD_LOGIC := '0'; + SIGNAL nlOii0O0l : STD_LOGIC := '0'; + SIGNAL nlOii0O1i : STD_LOGIC := '0'; + SIGNAL nlOii0Oi : STD_LOGIC := '0'; + SIGNAL nlOii0OiO : STD_LOGIC := '0'; + SIGNAL nlOii0Ol : STD_LOGIC := '0'; + SIGNAL nlOii0OlO : STD_LOGIC := '0'; + SIGNAL nlOii0OO : STD_LOGIC := '0'; + SIGNAL nlOii100l : STD_LOGIC := '0'; + SIGNAL nlOii101i : STD_LOGIC := '0'; + SIGNAL nlOii10i : STD_LOGIC := '0'; + SIGNAL nlOii10iO : STD_LOGIC := '0'; + SIGNAL nlOii10l : STD_LOGIC := '0'; + SIGNAL nlOii10O : STD_LOGIC := '0'; + SIGNAL nlOii10Oi : STD_LOGIC := '0'; + SIGNAL nlOii110O : STD_LOGIC := '0'; + SIGNAL nlOii111O : STD_LOGIC := '0'; + SIGNAL nlOii11i : STD_LOGIC := '0'; + SIGNAL nlOii11l : STD_LOGIC := '0'; + SIGNAL nlOii11O : STD_LOGIC := '0'; + SIGNAL nlOii1i0i : STD_LOGIC := '0'; + SIGNAL nlOii1ii : STD_LOGIC := '0'; + SIGNAL nlOii1iiO : STD_LOGIC := '0'; + SIGNAL nlOii1il : STD_LOGIC := '0'; + SIGNAL nlOii1ill : STD_LOGIC := '0'; + SIGNAL nlOii1iO : STD_LOGIC := '0'; + SIGNAL nlOii1li : STD_LOGIC := '0'; + SIGNAL nlOii1ll : STD_LOGIC := '0'; + SIGNAL nlOii1lO : STD_LOGIC := '0'; + SIGNAL nlOii1lOi : STD_LOGIC := '0'; + SIGNAL nlOii1O0l : STD_LOGIC := '0'; + SIGNAL nlOii1O1O : STD_LOGIC := '0'; + SIGNAL nlOii1Oi : STD_LOGIC := '0'; + SIGNAL nlOii1Ol : STD_LOGIC := '0'; + SIGNAL nlOii1OO : STD_LOGIC := '0'; + SIGNAL nlOiii00O : STD_LOGIC := '0'; + SIGNAL nlOiii01i : STD_LOGIC := '0'; + SIGNAL nlOiii0i : STD_LOGIC := '0'; + SIGNAL nlOiii0il : STD_LOGIC := '0'; + SIGNAL nlOiii0l : STD_LOGIC := '0'; + SIGNAL nlOiii0O : STD_LOGIC := '0'; + SIGNAL nlOiii10l : STD_LOGIC := '0'; + SIGNAL nlOiii11i : STD_LOGIC := '0'; + SIGNAL nlOiii1i : STD_LOGIC := '0'; + SIGNAL nlOiii1iO : STD_LOGIC := '0'; + SIGNAL nlOiii1l : STD_LOGIC := '0'; + SIGNAL nlOiii1O : STD_LOGIC := '0'; + SIGNAL nlOiiiii : STD_LOGIC := '0'; + SIGNAL nlOiiiiiO : STD_LOGIC := '0'; + SIGNAL nlOiiiil : STD_LOGIC := '0'; + SIGNAL nlOiiiill : STD_LOGIC := '0'; + SIGNAL nlOiiiiO : STD_LOGIC := '0'; + SIGNAL nlOiiiiOi : STD_LOGIC := '0'; + SIGNAL nlOiiili : STD_LOGIC := '0'; + SIGNAL nlOiiill : STD_LOGIC := '0'; + SIGNAL nlOiiilO : STD_LOGIC := '0'; + SIGNAL nlOiiiO0l : STD_LOGIC := '0'; + SIGNAL nlOiiiO0O : STD_LOGIC := '0'; + SIGNAL nlOiiiOi : STD_LOGIC := '0'; + SIGNAL nlOiiiOii : STD_LOGIC := '0'; + SIGNAL nlOiiiOil : STD_LOGIC := '0'; + SIGNAL nlOiiiOiO : STD_LOGIC := '0'; + SIGNAL nlOiiiOl : STD_LOGIC := '0'; + SIGNAL nlOiiiOli : STD_LOGIC := '0'; + SIGNAL nlOiiiOll : STD_LOGIC := '0'; + SIGNAL nlOiiiOO : STD_LOGIC := '0'; + SIGNAL nlOiil00l : STD_LOGIC := '0'; + SIGNAL nlOiil0i : STD_LOGIC := '0'; + SIGNAL nlOiil0ii : STD_LOGIC := '0'; + SIGNAL nlOiil0l : STD_LOGIC := '0'; + SIGNAL nlOiil0O : STD_LOGIC := '0'; + SIGNAL nlOiil1i : STD_LOGIC := '0'; + SIGNAL nlOiil1l : STD_LOGIC := '0'; + SIGNAL nlOiil1O : STD_LOGIC := '0'; + SIGNAL nlOiil1OO : STD_LOGIC := '0'; + SIGNAL nlOiilii : STD_LOGIC := '0'; + SIGNAL nlOiilil : STD_LOGIC := '0'; + SIGNAL nlOiiliO : STD_LOGIC := '0'; + SIGNAL nlOiilli : STD_LOGIC := '0'; + SIGNAL nlOiilll : STD_LOGIC := '0'; + SIGNAL nlOiillO : STD_LOGIC := '0'; + SIGNAL nlOiilO0i : STD_LOGIC := '0'; + SIGNAL nlOiilO0l : STD_LOGIC := '0'; + SIGNAL nlOiilO1O : STD_LOGIC := '0'; + SIGNAL nlOiilOi : STD_LOGIC := '0'; + SIGNAL nlOiilOl : STD_LOGIC := '0'; + SIGNAL nlOiilOO : STD_LOGIC := '0'; + SIGNAL nlOiiO0i : STD_LOGIC := '0'; + SIGNAL nlOiiO0l : STD_LOGIC := '0'; + SIGNAL nlOiiO0O : STD_LOGIC := '0'; + SIGNAL nlOiiO10O : STD_LOGIC := '0'; + SIGNAL nlOiiO11i : STD_LOGIC := '0'; + SIGNAL nlOiiO1i : STD_LOGIC := '0'; + SIGNAL nlOiiO1il : STD_LOGIC := '0'; + SIGNAL nlOiiO1l : STD_LOGIC := '0'; + SIGNAL nlOiiO1O : STD_LOGIC := '0'; + SIGNAL nlOiiOii : STD_LOGIC := '0'; + SIGNAL nlOiiOiiO : STD_LOGIC := '0'; + SIGNAL nlOiiOil : STD_LOGIC := '0'; + SIGNAL nlOiiOili : STD_LOGIC := '0'; + SIGNAL nlOiiOill : STD_LOGIC := '0'; + SIGNAL nlOiiOilO : STD_LOGIC := '0'; + SIGNAL nlOiiOiO : STD_LOGIC := '0'; + SIGNAL nlOiiOli : STD_LOGIC := '0'; + SIGNAL nlOiiOll : STD_LOGIC := '0'; + SIGNAL nlOiiOlli : STD_LOGIC := '0'; + SIGNAL nlOiiOlO : STD_LOGIC := '0'; + SIGNAL nlOiiOlOO : STD_LOGIC := '0'; + SIGNAL nlOiiOO1l : STD_LOGIC := '0'; + SIGNAL nlOiiOOi : STD_LOGIC := '0'; + SIGNAL nlOiiOOl : STD_LOGIC := '0'; + SIGNAL nlOiiOOO : STD_LOGIC := '0'; + SIGNAL nlOil001i : STD_LOGIC := '0'; + SIGNAL nlOil00i : STD_LOGIC := '0'; + SIGNAL nlOil00l : STD_LOGIC := '0'; + SIGNAL nlOil00O : STD_LOGIC := '0'; + SIGNAL nlOil010i : STD_LOGIC := '0'; + SIGNAL nlOil010O : STD_LOGIC := '0'; + SIGNAL nlOil011O : STD_LOGIC := '0'; + SIGNAL nlOil01i : STD_LOGIC := '0'; + SIGNAL nlOil01ii : STD_LOGIC := '0'; + SIGNAL nlOil01il : STD_LOGIC := '0'; + SIGNAL nlOil01iO : STD_LOGIC := '0'; + SIGNAL nlOil01l : STD_LOGIC := '0'; + SIGNAL nlOil01li : STD_LOGIC := '0'; + SIGNAL nlOil01ll : STD_LOGIC := '0'; + SIGNAL nlOil01lO : STD_LOGIC := '0'; + SIGNAL nlOil01O : STD_LOGIC := '0'; + SIGNAL nlOil01Oi : STD_LOGIC := '0'; + SIGNAL nlOil01Ol : STD_LOGIC := '0'; + SIGNAL nlOil01OO : STD_LOGIC := '0'; + SIGNAL nlOil0ii : STD_LOGIC := '0'; + SIGNAL nlOil0il : STD_LOGIC := '0'; + SIGNAL nlOil0iO : STD_LOGIC := '0'; + SIGNAL nlOil0li : STD_LOGIC := '0'; + SIGNAL nlOil0ll : STD_LOGIC := '0'; + SIGNAL nlOil0lO : STD_LOGIC := '0'; + SIGNAL nlOil0Oi : STD_LOGIC := '0'; + SIGNAL nlOil0Ol : STD_LOGIC := '0'; + SIGNAL nlOil0OO : STD_LOGIC := '0'; + SIGNAL nlOil10i : STD_LOGIC := '0'; + SIGNAL nlOil10l : STD_LOGIC := '0'; + SIGNAL nlOil10O : STD_LOGIC := '0'; + SIGNAL nlOil11i : STD_LOGIC := '0'; + SIGNAL nlOil11l : STD_LOGIC := '0'; + SIGNAL nlOil11O : STD_LOGIC := '0'; + SIGNAL nlOil1ii : STD_LOGIC := '0'; + SIGNAL nlOil1il : STD_LOGIC := '0'; + SIGNAL nlOil1iO : STD_LOGIC := '0'; + SIGNAL nlOil1li : STD_LOGIC := '0'; + SIGNAL nlOil1ll : STD_LOGIC := '0'; + SIGNAL nlOil1lO : STD_LOGIC := '0'; + SIGNAL nlOil1O1O : STD_LOGIC := '0'; + SIGNAL nlOil1Oi : STD_LOGIC := '0'; + SIGNAL nlOil1Oil : STD_LOGIC := '0'; + SIGNAL nlOil1OiO : STD_LOGIC := '0'; + SIGNAL nlOil1Ol : STD_LOGIC := '0'; + SIGNAL nlOil1Oli : STD_LOGIC := '0'; + SIGNAL nlOil1Oll : STD_LOGIC := '0'; + SIGNAL nlOil1OlO : STD_LOGIC := '0'; + SIGNAL nlOil1OO : STD_LOGIC := '0'; + SIGNAL nlOil1OOi : STD_LOGIC := '0'; + SIGNAL nlOil1OOl : STD_LOGIC := '0'; + SIGNAL nlOil1OOO : STD_LOGIC := '0'; + SIGNAL nlOili0i : STD_LOGIC := '0'; + SIGNAL nlOili0l : STD_LOGIC := '0'; + SIGNAL nlOili0O : STD_LOGIC := '0'; + SIGNAL nlOili10l : STD_LOGIC := '0'; + SIGNAL nlOili1i : STD_LOGIC := '0'; + SIGNAL nlOili1l : STD_LOGIC := '0'; + SIGNAL nlOili1li : STD_LOGIC := '0'; + SIGNAL nlOili1lO : STD_LOGIC := '0'; + SIGNAL nlOili1O : STD_LOGIC := '0'; + SIGNAL nlOiliii : STD_LOGIC := '0'; + SIGNAL nlOiliiil : STD_LOGIC := '0'; + SIGNAL nlOiliiiO : STD_LOGIC := '0'; + SIGNAL nlOiliili : STD_LOGIC := '0'; + SIGNAL nlOiliill : STD_LOGIC := '0'; + SIGNAL nlOiliilO : STD_LOGIC := '0'; + SIGNAL nlOiliiOi : STD_LOGIC := '0'; + SIGNAL nlOiliiOl : STD_LOGIC := '0'; + SIGNAL nlOiliiOO : STD_LOGIC := '0'; + SIGNAL nlOilO00i : STD_LOGIC := '0'; + SIGNAL nlOilO0iO : STD_LOGIC := '0'; + SIGNAL nlOilO0ll : STD_LOGIC := '0'; + SIGNAL nlOilOiOi : STD_LOGIC := '0'; + SIGNAL nlOilOl0l : STD_LOGIC := '0'; + SIGNAL nlOilOl1O : STD_LOGIC := '0'; + SIGNAL nlOilOOii : STD_LOGIC := '0'; + SIGNAL nlOilOOlO : STD_LOGIC := '0'; + SIGNAL nlOilOOOl : STD_LOGIC := '0'; + SIGNAL nlOl1i01l : STD_LOGIC := '0'; + SIGNAL nlOl1li0i : STD_LOGIC := '0'; + SIGNAL nlOl1li0l : STD_LOGIC := '0'; + SIGNAL wire_nl1000i_CLRN : STD_LOGIC; + SIGNAL wire_nl1000i_w_lg_w_lg_w29769w29771w29774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w2361w2363w2364w2365w2366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w2361w2371w2373w2375w2380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w36978w36979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w4436w4438w4440w4442w4446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w29769w29771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w2361w2363w2364w2365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w2361w2371w2373w2375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w2361w2371w2373w2383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w36978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w4436w4438w4440w4442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w29769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w2361w2363w2364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w2361w2371w2373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w36974w36975w36976w36977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w4436w4438w4440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w29761w29763w29765w29767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w2361w2363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w2361w2371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w36974w36975w36976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w4436w4438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w29761w29763w29765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w2361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w36974w36975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w4436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w36257w36258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w29761w29763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w29780w29785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_niOiO1i2353w2355w2357w2359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w36974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w4665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_n1l001l4428w4430w4432w4434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w59027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w59044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w59024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w59048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w9921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w9914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w9908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w36257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w29761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w29780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w60343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w59696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_niOiO1i2353w2355w2357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59038w59039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59031w59050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9896w9900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9890w9894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9882w9886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9873w9879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nll0Oii1l5332w5333w5334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlli1Ol0l36971w36972w36973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nllliili4655w4656w4659w4662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_n1l001l4428w4430w4432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nll0O0i0i36246w36247w36248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nll0O0i0O36253w36255w36256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nllilil0l35858w35860w36926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlliO11l5089w5106w5107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlO0liliO29755w29757w29759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlOi1Ol1O29650w29652w29779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlOiilii60339w60341w60342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlOil0OO59692w60307w60313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlOil0OO59692w59693w59695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlOili1l60355w60356w60357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_n1l01ii4073w4076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOiO1i2353w2355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0Oii1l5332w5333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0iO1i36270w36271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli1Ol0l36971w36972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlliliiOO35871w35872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlliO11i5102w5103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlOil0OO59701w59702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nllliili4655w4656w4659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_n1l000l4101w4316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_n1l001l4428w4430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niiiOOO2312w2313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOi01l2310w2311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi01il42910w42911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi01il42910w53644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi01il42910w53331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi01il42910w53329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i0i35846w35847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i1i44005w48206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1ill29013w29014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_niOOOil1058w1059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlilliiOi42828w42829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0O0i0i36246w36247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0O0i0O36253w36255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0O0iOl5342w5660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0O0iOl5342w5600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0Oi0iO5948w5954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0Oii1l5335w5338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0Oii1l5335w5336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0OilO5675w5676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w5678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w5659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w36235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllilil0l35858w35860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllilO1i5110w5747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllilO1i5110w5743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllilO1i5110w5706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllilOlOi35909w35910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlliO11i5100w5701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlliO11l5089w5726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlliO11l5089w5106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlliO11O5108w5714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlliO11O5108w5109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlO0liliO29755w29757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlOi1Ol1O29650w29652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlOiilii60339w60341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlOil0OO59692w60307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlOil0OO59692w59693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlOil11O59625w59627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlOili1l60355w60356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_n1l000l4315w4317w4318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlli0ilOO5658w35983w35984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nll0OiiO5649w5650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l000l4315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l000O4102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l001O4298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l011i4082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l011i4080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l011l4303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01ii4073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01ii4078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOiO1i2353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i0i35850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i0i35853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1iii34492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1ill29017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1l1i59030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOOil1061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOl0O9889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOl0O9872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilOO0li42249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iOi5672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iOl5613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iOl36239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iOl5601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi0iO5957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oii1l5332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oiii5609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oili5651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0OiOl5607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i01i36199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i01i36177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i01i36186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i01i36206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1Oi36217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1Oi36195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1Ol36209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1Ol36193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1OO36201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1OO36179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1OO36188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1OO36214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0iliO35933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0illi35932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ilOO35986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0iO1i36270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0iO1l36184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0iO1l36221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1Ol0l36971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliiilii42785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliliiOO35871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllillOl5686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllillOl5080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilO1i5749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOlOi35917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO01i5746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO01i5728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO01i5741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO01i5704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO10i5226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO11i5102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO11l5751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO11l5742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllli1il4681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1OiOl29018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil0OO59701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOili0l4040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlliliiOO35871w35872w35873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlOil11O59625w59627w59628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllillOl5080w6320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllliili4655w4656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllliill4657w4658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllliilO4660w4661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nllliiOi4663w4664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l000l4101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l000O4060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l001i4429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l001l4428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l00ii4074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l010i4042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l010l4099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l010O4314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01il4447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01iO4443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01li4441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01ll4439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01lO4437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01Oi4435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01Ol4433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l01OO4431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_ni001Ol2342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_ni00ilO2338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_ni0i0OO2344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_ni0l0il2336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_ni0lO1i2326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_ni0O1iO2324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niiiOOO2312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niO0l0li8755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niO0OOOl1060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOi01l2310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOil0l2369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOil0O2367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOilii2376w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOilil2374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOiliO2372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOilli2362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOilll2360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOillO2358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOilOi2356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOilOl2354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOilOO2352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOlOill8545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOO001i44257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOO010O44258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOO0ili46420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOO0liO8485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOO1i0i45522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi01il42910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi0li8471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi11l8478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i0i35846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i0O34491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i1i44005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i1l36191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i1O35849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1iii34557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1ili29016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1ill29013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1ilO59025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1iOi59019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1iOl59017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1iOO59015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1l1i59014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOil0i46311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOil0l46309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOil0O46308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOilii46307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOilil46306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOiliO46305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOilli46304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOilll46303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOillO46302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOilOi46364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOl1il46312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOllOO8420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOO1OO8409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOOi1i8406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOOil1058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOOOiO8394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl00ilOO7356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl00Olll7232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl01i0OO7558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl01i1ii7565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl01Olli7360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0iiO1i7228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0OiO0O6419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0OlOOl6384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0OO1li6393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0OO1ll6391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0OO1lO6389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0OO1Oi6388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl0OOOlO6364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl100O0i44666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl100O0l44665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl100O0O44664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl100O1O44667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1011li8265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl101ili8254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl10i10i44668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl10iili46322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl10iill46321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl10iilO46320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl10iiOi46319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl10illl46323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1101ll8363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl110i0i8355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl110llO8347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11101l8386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl111ili8378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl111Oll8366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11i0Oi8331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11i10l8339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11il0O8323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11ilO2143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11iOi2246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11iOl2239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11iOO2232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11iOOl8315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l0i2204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l0l2197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l0O2190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l0OO8303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l1i2225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l1l2218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l1O2211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11lii2183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11lil2176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11liO2169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11lli2162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11llil8296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11lll2155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11O0iO8282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11O11i8289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11Ol1l8275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11OOiO8268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1iiilO8010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1iiO0l8003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1il00l7993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1l00Oi7900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1l010l7907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1l0l0O7893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1l11ll7928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1l1i0i7921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1l1llO7914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1li00l7877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1liOlO7857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1lO11i7822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1lOill7802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1O01Ol7758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1O0iii7750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1O0lOO7742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1O110l7798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1O1OOi7761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1Oi1il7734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1Oiiil7722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1OiO1i7715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1Ol0li7704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1Ol11l7712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1Oll1O7696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1OlOll7688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1OOOii2349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl1OOOil2346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nli1100i54856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nli1i1ll5104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nli1i1OO6078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilli0Oi42220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilli0Ol42223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilli0OO42226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillii0i42247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillii1i42232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillii1l42235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillii1O42238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilliiOi42828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilliiOl42781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilliiOO42779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillil1i42778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOi0i9874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOi1O9876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOiiO42888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOili42886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOill42884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOilO42882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOiOi42880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOiOl42879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOl0i9881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOl0l9888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOl0O9902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOlii42167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOlil42168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlillOlli42169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilOO0iO5228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilOO0li42165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilOO0ll42166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i000i37581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i000l37585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i000O37589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i001i37569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i001l37573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i001O37577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00ii37593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00il37597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00iO37601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00li37605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00ll37609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00lO37613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00Oi37617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00Ol37621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i00OO37625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i01Oi37557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i01Ol37561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i01OO37565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0i0i37641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0i0l37645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0i0O37649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0i1i37629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0i1l37633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0i1O37637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0iii37653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0iil37657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0iiO37661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0ili37665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0ill37669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0ilO37673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0iOi37677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0iOl37427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0iOO37430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0l0i37446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0l0l37450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0l0O37454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0l1i37434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0l1l37438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0l1O37442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0lii37458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0lil37462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0liO37466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0lli37470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0lll37474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0llO37478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0lOi37482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0lOl37486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0lOO37490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0O0i37506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0O0l37510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0O0O37514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0O1i37494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0O1l37498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0O1O37502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0Oii37518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0Oil37522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0OiO37526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0Oli37530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0Oll37534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0OlO37538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0OOi37542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0OOl37546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0i0OOO37550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0iO1lO37554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0liiOi29692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0liiOl29690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0ll1OO36546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0lOi1l36419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0lOi1O36327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0i0i36246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0i0l36254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0i0O36253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iii37709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iil37707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iiO37705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0ili37704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0ill36243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0ilO36240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O0iOl5342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O101i36347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O101l36349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O10OO35783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11ii36329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11il36331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11iO36333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11li36335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11ll36337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11lO36339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11Oi36341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11Ol36343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O11OO36345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0O1i1i35781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi01l5329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi0ii5951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi0il5949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi0iO5948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi10i5975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi10l5973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi10O5971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi11O5977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi1ii5969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi1il5967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi1iO5965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi1li5963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oi1ll5962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oii0i36228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oii1i5265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oii1l5335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0OilO5675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0OOOll36490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0OOOOi36491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll100Oil36983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11lOli36986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11lOll36990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11lOlO36994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11lOOi36998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11lOOl37002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11lOOO37006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O00i37082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O00l37086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O00O37090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O01i37070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O01l37074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O01O37078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0ii37094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0il37098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0iO37102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0li37106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0ll37205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0lO37208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0Oi37212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0Ol37216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O0OO37220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O10i37022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O10l37026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O10O37030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O11i37010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O11l37014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O11O37018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1ii37034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1il37038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1iO37042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1li37046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1ll37050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1lO37054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1Oi37058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1Ol37062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11O1OO37066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oi0i37236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oi0l37240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oi0O37244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oi1i37224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oi1l37228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oi1O37232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oiii37248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oiil37252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11OiiO37256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oili37260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Oill37264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11OilO37268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11OiOi37272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11OiOl37276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11OiOO37280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Ol0i37296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Ol0l37300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Ol0O37304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Ol1i37284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Ol1l37288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Ol1O37292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Olii37308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Olil37312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11OliO37316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Olli37320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11Olll37324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll11OllO37328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i0li36947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i0ll36945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i0lO36943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i0Oi36941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i0Ol36939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i0OO36937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ii0i36930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ii1i36935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ii1l36933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ii1O36931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0illO35982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ilOi35930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ilOl36234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0ilOO5658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0iO1O35900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1100O36185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1Oili36980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1Ol0O36969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1Olii36966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1Olil36964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1OliO36962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1Olli36960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1Olll36958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1OllO36956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1OlOi36954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1OlOl36952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1OlOO36950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1OO1i36949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliiil0l34446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliiil0O42784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliiilii28850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliliiOi35868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliliiOl35866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliliiOO35864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilil0i35859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilil0l35858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilil1i35863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilil1l36927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilil1O35861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllillOl5218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilO1i5110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilO1l5219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOii5945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOil5943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOiO5941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOli5939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOll5937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOlO5935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOlOi35909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOOi5933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOOl5931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllilOOO5930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO01i5754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO10i5698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO11i5100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO11l5089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO11O5108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO1Oi5683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl00i35348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl00l35350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl00O35352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl01O35346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl0ii35354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl0il35356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl0iO35358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl10O28856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliOl11l35175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000il34361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000iO34363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000li34365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000ll34367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000lO34369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000Oi34371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000Ol34373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll000OO34375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00i0i35436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00i0l35438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00i0O35440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00i1i34377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00i1l34379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00i1O34381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00iii35442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll00iil35444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll0101l34625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll01i1i34359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll0il1O34569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll0iOOO34563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1il0l34166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1il1l34164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1il1O34165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1lOOO34167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1OO0O966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1OOil35170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllli0il4654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllliiOi4618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllO0i0l4357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllO0i0O4338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00lOiO29672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00lOli29673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00lOll29674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00lOlO28853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00lOOi28854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00lOOl28855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0il00i29492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0il01O29664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0iOiOO29413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0li0OO29490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lii0i29732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lii0l29730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lii0O29728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lii1i29421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lii1O29734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liiii29726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liiil29724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liiiO29722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liili29720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liill29718w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liilO29716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liiOi29715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liiOl29775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liiOO29772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lil0i29764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lil0l29762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lil0O29760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lil1i29770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lil1l29768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lil1O29766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lilii29758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lilil29756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0liliO29755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0lliO4409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0llOi4286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0OlOii28872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO0OOOO4297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOi0O29449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOiii29450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOiil29451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOiiO29452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOili29453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOill29454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOilO29455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOiOi29440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOiOl29441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOiOO29442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOl0i29446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOl0l29447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOl0O29432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOl1i29443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOl1l29444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOl1O29445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOlii29433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOlil29434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOliO29435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOlli29436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOlll29437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOllO29438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOlOi29439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOlOl29424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOlOO29425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOO0i29429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOO0l29430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOO0O29431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOO1i29426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOO1l29427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1lOO1O29428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1O0l1i29448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1Oi1ll28015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO1Ol1li29671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi0l01O28780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi0O0ii28769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi0O10O28772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi0Ol1i28762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1Oill29647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1OilO29645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1OiOi29643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1OiOl29642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1OiOO29159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1Ol1i29713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1Ol1l29651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1Ol1O29650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOii111O28751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOiiiOO60350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOiil0O60340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOiil1i60348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOiil1l60346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOiil1O60344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOiilii60339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil0ll60311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil0lO60309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil0Oi59694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil0Ol59700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil0OO59692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil10i60286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil10l60284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil10O60282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil11l59626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil11O59625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil1ii60280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil1il60278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil1iO60276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil1li60274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil1ll60273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil1O1O28018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOil1OOO28520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOili0i4039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOili0l4166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOili0O4300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOili1i59697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOili1l60355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOiliii4069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nll0Oii1l5332w5333w5334w5337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlliO11i5100w5701w5727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_w_lg_n1l000l4315w4317w4318w4319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nll0OiiO5649w5650w5652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_n1l000l4315w4317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0i01i36206w36210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0i1OO36214w36218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0illi35932w35934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_n1l00ii4074w4075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w35983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w5339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nliO0l1l5664w5665w5666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_w_lg_nlO00O11i29542w29563w29564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nliO0l1l5664w5665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0i01i35924w35925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0i1lO36211w36220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlli0i1OO35926w35927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlO00O11i29542w29543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_w_lg_nlO00O11i29542w29563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l00ii4302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_n1l011i4156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i1l36213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_niOOi1i1l36205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nl11l1O1558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlilOO0ll42241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nliO0l1l5664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0OiiO5649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oili5679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nll0Oili5471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i01i35924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1lO36211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli0i1OO35926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlli1OO1l36219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO11i5692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlliO1OO5141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1il0l34806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlll1ilii34837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00lOOl29539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlO00O11i29542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1OiOi29020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nlOi1Ol1l29021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllliili4655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllliill4657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllliilO4660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1000i_w_lg_nllliiOi4663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL n1illl0i : STD_LOGIC := '0'; + SIGNAL n1illl0l : STD_LOGIC := '0'; + SIGNAL n1illl0O : STD_LOGIC := '0'; + SIGNAL n1illl1O : STD_LOGIC := '0'; + SIGNAL n1illlii : STD_LOGIC := '0'; + SIGNAL n1illlil : STD_LOGIC := '0'; + SIGNAL n1illliO : STD_LOGIC := '0'; + SIGNAL n1illlli : STD_LOGIC := '0'; + SIGNAL n1illlll : STD_LOGIC := '0'; + SIGNAL n1illllO : STD_LOGIC := '0'; + SIGNAL n1illlOi : STD_LOGIC := '0'; + SIGNAL n1illlOl : STD_LOGIC := '0'; + SIGNAL n1illlOO : STD_LOGIC := '0'; + SIGNAL n1illO0i : STD_LOGIC := '0'; + SIGNAL n1illO0l : STD_LOGIC := '0'; + SIGNAL n1illO0O : STD_LOGIC := '0'; + SIGNAL n1illO1i : STD_LOGIC := '0'; + SIGNAL n1illO1l : STD_LOGIC := '0'; + SIGNAL n1illO1O : STD_LOGIC := '0'; + SIGNAL n1illOii : STD_LOGIC := '0'; + SIGNAL n1l011O : STD_LOGIC := '0'; + SIGNAL nil10lli : STD_LOGIC := '0'; + SIGNAL nil10lll : STD_LOGIC := '0'; + SIGNAL nil10llO : STD_LOGIC := '0'; + SIGNAL nil10lOi : STD_LOGIC := '0'; + SIGNAL nil10lOl : STD_LOGIC := '0'; + SIGNAL nil10lOO : STD_LOGIC := '0'; + SIGNAL nil10O0i : STD_LOGIC := '0'; + SIGNAL nil10O0l : STD_LOGIC := '0'; + SIGNAL nil10O0O : STD_LOGIC := '0'; + SIGNAL nil10O1i : STD_LOGIC := '0'; + SIGNAL nil10O1l : STD_LOGIC := '0'; + SIGNAL nil10O1O : STD_LOGIC := '0'; + SIGNAL nil10Oii : STD_LOGIC := '0'; + SIGNAL nil10Oil : STD_LOGIC := '0'; + SIGNAL nil10OiO : STD_LOGIC := '0'; + SIGNAL nil10Oli : STD_LOGIC := '0'; + SIGNAL nil10Oll : STD_LOGIC := '0'; + SIGNAL nil10OlO : STD_LOGIC := '0'; + SIGNAL nil10OOi : STD_LOGIC := '0'; + SIGNAL nil10OOl : STD_LOGIC := '0'; + SIGNAL nil10OOO : STD_LOGIC := '0'; + SIGNAL nil1100i : STD_LOGIC := '0'; + SIGNAL nil1100l : STD_LOGIC := '0'; + SIGNAL nil1100O : STD_LOGIC := '0'; + SIGNAL nil110ii : STD_LOGIC := '0'; + SIGNAL nil110il : STD_LOGIC := '0'; + SIGNAL nil110iO : STD_LOGIC := '0'; + SIGNAL nil110li : STD_LOGIC := '0'; + SIGNAL nil110ll : STD_LOGIC := '0'; + SIGNAL nil110lO : STD_LOGIC := '0'; + SIGNAL nil110Oi : STD_LOGIC := '0'; + SIGNAL nil110Ol : STD_LOGIC := '0'; + SIGNAL nil110OO : STD_LOGIC := '0'; + SIGNAL nil11i0i : STD_LOGIC := '0'; + SIGNAL nil11i0l : STD_LOGIC := '0'; + SIGNAL nil11i0O : STD_LOGIC := '0'; + SIGNAL nil11i1i : STD_LOGIC := '0'; + SIGNAL nil11i1l : STD_LOGIC := '0'; + SIGNAL nil11i1O : STD_LOGIC := '0'; + SIGNAL nil11iii : STD_LOGIC := '0'; + SIGNAL nil11iil : STD_LOGIC := '0'; + SIGNAL nil11iiO : STD_LOGIC := '0'; + SIGNAL nil1i10i : STD_LOGIC := '0'; + SIGNAL nil1i10l : STD_LOGIC := '0'; + SIGNAL nil1i11i : STD_LOGIC := '0'; + SIGNAL nil1i11l : STD_LOGIC := '0'; + SIGNAL nil1i11O : STD_LOGIC := '0'; + SIGNAL nl11lOi : STD_LOGIC := '0'; + SIGNAL nli1i00l : STD_LOGIC := '0'; + SIGNAL nli1i01i : STD_LOGIC := '0'; + SIGNAL nli1i01l : STD_LOGIC := '0'; + SIGNAL nlillOlOi : STD_LOGIC := '0'; + SIGNAL nlilOO0lO : STD_LOGIC := '0'; + SIGNAL nliOlilO : STD_LOGIC := '0'; + SIGNAL nll0Oill : STD_LOGIC := '0'; + SIGNAL nlliO01l : STD_LOGIC := '0'; + SIGNAL nlll1ilil : STD_LOGIC := '0'; + SIGNAL nlll1OOii : STD_LOGIC := '0'; + SIGNAL nlO00O11l : STD_LOGIC := '0'; + SIGNAL nlO0lllO : STD_LOGIC := '0'; + SIGNAL nlOil010l : STD_LOGIC := '0'; + SIGNAL nlOil011i : STD_LOGIC := '0'; + SIGNAL nlOil011l : STD_LOGIC := '0'; + SIGNAL wire_nl11llO_CLRN : STD_LOGIC; + SIGNAL wire_nl11llO_PRN : STD_LOGIC; + SIGNAL wire_nl11llO_w_lg_w_lg_nlll1OOii34722w34723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1l011O4051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1l011O4307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlliO01l5740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlliO01l5723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlll1OOii34722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illl0i25375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illl0l25373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illl0O25371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illl1O25377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illlii25369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illlil25367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illliO25365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illlli25363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illlll25361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illllO25359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illlOi25357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illlOl25355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illlOO25353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illO0i25345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illO0l25343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illO0O25341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illO1i25351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illO1l25349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illO1O25347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1illOii25340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_n1l011O4055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nl11lOi2148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlillOlOi42768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlll1ilil35500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlll1OOii34761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlO00O11l29156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlO0lllO4336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_n1l011O4051w4052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_nlliO01l5740w5745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w_lg_nlliO01l5740w5745w5748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nlliO01l5740w5745w5748w5752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w1088w1089w1090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w1074w1075w1076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w1088w1089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w1074w1075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w1088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w1074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nl11lOi1070w1085w1086w1087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nl11lOi1070w1071w1072w1073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w_lg_nl11lOi1070w1085w1086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w_lg_nl11lOi1070w1071w1072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_w_lg_nlll1ilil34878w34879w34880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_nl11lOi1070w1085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_nl11lOi1070w1071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_nlillOlOi42755w42756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_nlillOlOi42452w42453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_nlliO01l5221w5223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_w_lg_nlll1ilil34878w34879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nl11lOi1070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlillOlOi42755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlillOlOi42452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlliO01l5221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlliO01l5197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlliO01l5207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11llO_w_lg_nlll1ilil34878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nliii0O1l : STD_LOGIC := '0'; + SIGNAL nliii0OOi : STD_LOGIC := '0'; + SIGNAL nliii0OOl : STD_LOGIC := '0'; + SIGNAL nliii0OOO : STD_LOGIC := '0'; + SIGNAL nliiii00i : STD_LOGIC := '0'; + SIGNAL nliiii00l : STD_LOGIC := '0'; + SIGNAL nliiii00O : STD_LOGIC := '0'; + SIGNAL nliiii01i : STD_LOGIC := '0'; + SIGNAL nliiii01l : STD_LOGIC := '0'; + SIGNAL nliiii01O : STD_LOGIC := '0'; + SIGNAL nliiii0ii : STD_LOGIC := '0'; + SIGNAL nliiii0il : STD_LOGIC := '0'; + SIGNAL nliiii0iO : STD_LOGIC := '0'; + SIGNAL nliiii0li : STD_LOGIC := '0'; + SIGNAL nliiii0ll : STD_LOGIC := '0'; + SIGNAL nliiii0lO : STD_LOGIC := '0'; + SIGNAL nliiii0Oi : STD_LOGIC := '0'; + SIGNAL nliiii0Ol : STD_LOGIC := '0'; + SIGNAL nliiii0OO : STD_LOGIC := '0'; + SIGNAL nliiii10i : STD_LOGIC := '0'; + SIGNAL nliiii10l : STD_LOGIC := '0'; + SIGNAL nliiii10O : STD_LOGIC := '0'; + SIGNAL nliiii11i : STD_LOGIC := '0'; + SIGNAL nliiii11l : STD_LOGIC := '0'; + SIGNAL nliiii11O : STD_LOGIC := '0'; + SIGNAL nliiii1ii : STD_LOGIC := '0'; + SIGNAL nliiii1il : STD_LOGIC := '0'; + SIGNAL nliiii1iO : STD_LOGIC := '0'; + SIGNAL nliiii1li : STD_LOGIC := '0'; + SIGNAL nliiii1ll : STD_LOGIC := '0'; + SIGNAL nliiii1lO : STD_LOGIC := '0'; + SIGNAL nliiii1Oi : STD_LOGIC := '0'; + SIGNAL nliiii1Ol : STD_LOGIC := '0'; + SIGNAL nliiii1OO : STD_LOGIC := '0'; + SIGNAL nliiiii0i : STD_LOGIC := '0'; + SIGNAL nliiiii0l : STD_LOGIC := '0'; + SIGNAL nliiiii0O : STD_LOGIC := '0'; + SIGNAL nliiiii1i : STD_LOGIC := '0'; + SIGNAL nliiiii1l : STD_LOGIC := '0'; + SIGNAL nliiiii1O : STD_LOGIC := '0'; + SIGNAL nliiiiiii : STD_LOGIC := '0'; + SIGNAL nliiiiiil : STD_LOGIC := '0'; + SIGNAL nliiiiiiO : STD_LOGIC := '0'; + SIGNAL nliiiiili : STD_LOGIC := '0'; + SIGNAL nliiiiill : STD_LOGIC := '0'; + SIGNAL nliiiiilO : STD_LOGIC := '0'; + SIGNAL nliiiiiOi : STD_LOGIC := '0'; + SIGNAL nliiiiiOl : STD_LOGIC := '0'; + SIGNAL nliiiiiOO : STD_LOGIC := '0'; + SIGNAL nliiiil0i : STD_LOGIC := '0'; + SIGNAL nliiiil0l : STD_LOGIC := '0'; + SIGNAL nliiiil0O : STD_LOGIC := '0'; + SIGNAL nliiiil1i : STD_LOGIC := '0'; + SIGNAL nliiiil1l : STD_LOGIC := '0'; + SIGNAL nliiiil1O : STD_LOGIC := '0'; + SIGNAL nliiiilii : STD_LOGIC := '0'; + SIGNAL nliiiilil : STD_LOGIC := '0'; + SIGNAL nliiiiliO : STD_LOGIC := '0'; + SIGNAL nliiiilli : STD_LOGIC := '0'; + SIGNAL nliiiilll : STD_LOGIC := '0'; + SIGNAL nliiiillO : STD_LOGIC := '0'; + SIGNAL nliiiilOi : STD_LOGIC := '0'; + SIGNAL nliiiilOl : STD_LOGIC := '0'; + SIGNAL nliiiiO1i : STD_LOGIC := '0'; + SIGNAL wire_nliiiilOO_w_lg_nliii0O1l44660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliii0OOi44659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliii0OOl44658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliii0OOO44657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii00i44638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii00l44637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii00O44636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii01i44641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii01l44640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii01O44639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0ii44635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0il44634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0iO44633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0li44632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0ll44631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0lO44630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0Oi44629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0Ol44627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii0OO44626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii10i44653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii10l44652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii10O44651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii11i44656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii11l44655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii11O44654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1ii44650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1il44649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1iO44648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1li44647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1ll44646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1lO44645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1Oi44644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1Ol44643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiii1OO44642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiii0i44622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiii0l44621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiii0O44620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiii1i44625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiii1l44624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiii1O44623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiiii44619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiiil44618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiiiO44617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiili44616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiill44615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiilO44614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiiOi44613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiiOl44612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiiOO44611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiil0i44607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiil0l44606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiil0O44605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiil1i44610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiil1l44609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiil1O44608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiilii44604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiilil44603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiliO44602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiilli44601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiilll44600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiillO44599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiilOi44598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiilOl44597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiiilOO_w_lg_nliiiiO1i44596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nli11O01O : STD_LOGIC := '0'; + SIGNAL nli11O1OO : STD_LOGIC := '0'; + SIGNAL nliiO0i0l : STD_LOGIC := '0'; + SIGNAL nliiO0i0O : STD_LOGIC := '0'; + SIGNAL nliiO0ili : STD_LOGIC := '0'; + SIGNAL nliiO0ilO : STD_LOGIC := '0'; + SIGNAL nliiO0iOi : STD_LOGIC := '0'; + SIGNAL nliiO0iOO : STD_LOGIC := '0'; + SIGNAL nliiO10ii : STD_LOGIC := '0'; + SIGNAL wire_nliiO0iOl_w_lg_nliiO0i0l44503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO0iOl_w_lg_nliiO0i0O44504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO0iOl_w_lg_nliiO0ili44284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO0iOl_w_lg_nliiO0ilO44505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO0iOl_w_lg_nliiO0iOi44506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO0iOl_w_lg_nliiO0iOO44507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO0iOl_w_lg_nliiO10ii44514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl0ilOllO : STD_LOGIC := '0'; + SIGNAL nl0iO0Oii : STD_LOGIC := '0'; + SIGNAL nl0iO0Oil : STD_LOGIC := '0'; + SIGNAL nl0iO0OiO : STD_LOGIC := '0'; + SIGNAL nl0iO0Oli : STD_LOGIC := '0'; + SIGNAL nl0iO0Oll : STD_LOGIC := '0'; + SIGNAL nl0iO0OlO : STD_LOGIC := '0'; + SIGNAL nl0iO0OOi : STD_LOGIC := '0'; + SIGNAL nl0iO0OOl : STD_LOGIC := '0'; + SIGNAL nl0iO0OOO : STD_LOGIC := '0'; + SIGNAL nl0iOi11i : STD_LOGIC := '0'; + SIGNAL nl0iOi11l : STD_LOGIC := '0'; + SIGNAL nl0iOi11O : STD_LOGIC := '0'; + SIGNAL nli11ilOi : STD_LOGIC := '0'; + SIGNAL nli11l1ll : STD_LOGIC := '0'; + SIGNAL nli11l1lO : STD_LOGIC := '0'; + SIGNAL nli11li1i : STD_LOGIC := '0'; + SIGNAL nli11O00i : STD_LOGIC := '0'; + SIGNAL nli11O00l : STD_LOGIC := '0'; + SIGNAL nli11O00O : STD_LOGIC := '0'; + SIGNAL nli11O01i : STD_LOGIC := '0'; + SIGNAL nli11O01l : STD_LOGIC := '0'; + SIGNAL nli11O1il : STD_LOGIC := '0'; + SIGNAL nli11O1iO : STD_LOGIC := '0'; + SIGNAL nli11O1li : STD_LOGIC := '0'; + SIGNAL nli11O1ll : STD_LOGIC := '0'; + SIGNAL nli11O1lO : STD_LOGIC := '0'; + SIGNAL nli11O1Oi : STD_LOGIC := '0'; + SIGNAL nli11O1Ol : STD_LOGIC := '0'; + SIGNAL nli1ilO1O : STD_LOGIC := '0'; + SIGNAL nlii0OO0l : STD_LOGIC := '0'; + SIGNAL nlii0OO0O : STD_LOGIC := '0'; + SIGNAL nlii0OOii : STD_LOGIC := '0'; + SIGNAL nlii0OOil : STD_LOGIC := '0'; + SIGNAL nlii0OOiO : STD_LOGIC := '0'; + SIGNAL nlii0OOli : STD_LOGIC := '0'; + SIGNAL nlii0OOll : STD_LOGIC := '0'; + SIGNAL nlii0OOlO : STD_LOGIC := '0'; + SIGNAL nlii0OOOi : STD_LOGIC := '0'; + SIGNAL nlii0OOOl : STD_LOGIC := '0'; + SIGNAL nlii0OOOO : STD_LOGIC := '0'; + SIGNAL nlii1l1ll : STD_LOGIC := '0'; + SIGNAL nliii001i : STD_LOGIC := '0'; + SIGNAL nliii001l : STD_LOGIC := '0'; + SIGNAL nliii001O : STD_LOGIC := '0'; + SIGNAL nliii01Oi : STD_LOGIC := '0'; + SIGNAL nliii01Ol : STD_LOGIC := '0'; + SIGNAL nliii01OO : STD_LOGIC := '0'; + SIGNAL nliii100i : STD_LOGIC := '0'; + SIGNAL nliii100l : STD_LOGIC := '0'; + SIGNAL nliii100O : STD_LOGIC := '0'; + SIGNAL nliii101i : STD_LOGIC := '0'; + SIGNAL nliii101l : STD_LOGIC := '0'; + SIGNAL nliii101O : STD_LOGIC := '0'; + SIGNAL nliii110i : STD_LOGIC := '0'; + SIGNAL nliii110l : STD_LOGIC := '0'; + SIGNAL nliii110O : STD_LOGIC := '0'; + SIGNAL nliii111i : STD_LOGIC := '0'; + SIGNAL nliii111l : STD_LOGIC := '0'; + SIGNAL nliii111O : STD_LOGIC := '0'; + SIGNAL nliii11ii : STD_LOGIC := '0'; + SIGNAL nliii11il : STD_LOGIC := '0'; + SIGNAL nliii11iO : STD_LOGIC := '0'; + SIGNAL nliii11li : STD_LOGIC := '0'; + SIGNAL nliii11ll : STD_LOGIC := '0'; + SIGNAL nliii11lO : STD_LOGIC := '0'; + SIGNAL nliii11Oi : STD_LOGIC := '0'; + SIGNAL nliii11Ol : STD_LOGIC := '0'; + SIGNAL nliii11OO : STD_LOGIC := '0'; + SIGNAL nliiiiO0i : STD_LOGIC := '0'; + SIGNAL nliiiiO0l : STD_LOGIC := '0'; + SIGNAL nliiiiO0O : STD_LOGIC := '0'; + SIGNAL nliiiiO1l : STD_LOGIC := '0'; + SIGNAL nliiiiO1O : STD_LOGIC := '0'; + SIGNAL nliiiiOii : STD_LOGIC := '0'; + SIGNAL nliiiiOil : STD_LOGIC := '0'; + SIGNAL nliiiiOiO : STD_LOGIC := '0'; + SIGNAL nliiiiOli : STD_LOGIC := '0'; + SIGNAL nliiiiOll : STD_LOGIC := '0'; + SIGNAL nliiiiOlO : STD_LOGIC := '0'; + SIGNAL nliiiiOOi : STD_LOGIC := '0'; + SIGNAL nliiiiOOl : STD_LOGIC := '0'; + SIGNAL nliiiiOOO : STD_LOGIC := '0'; + SIGNAL nliiil00i : STD_LOGIC := '0'; + SIGNAL nliiil00l : STD_LOGIC := '0'; + SIGNAL nliiil00O : STD_LOGIC := '0'; + SIGNAL nliiil01i : STD_LOGIC := '0'; + SIGNAL nliiil01l : STD_LOGIC := '0'; + SIGNAL nliiil01O : STD_LOGIC := '0'; + SIGNAL nliiil0ii : STD_LOGIC := '0'; + SIGNAL nliiil0il : STD_LOGIC := '0'; + SIGNAL nliiil0iO : STD_LOGIC := '0'; + SIGNAL nliiil0li : STD_LOGIC := '0'; + SIGNAL nliiil0ll : STD_LOGIC := '0'; + SIGNAL nliiil0lO : STD_LOGIC := '0'; + SIGNAL nliiil0Oi : STD_LOGIC := '0'; + SIGNAL nliiil0Ol : STD_LOGIC := '0'; + SIGNAL nliiil0OO : STD_LOGIC := '0'; + SIGNAL nliiil10i : STD_LOGIC := '0'; + SIGNAL nliiil10l : STD_LOGIC := '0'; + SIGNAL nliiil10O : STD_LOGIC := '0'; + SIGNAL nliiil11i : STD_LOGIC := '0'; + SIGNAL nliiil11l : STD_LOGIC := '0'; + SIGNAL nliiil11O : STD_LOGIC := '0'; + SIGNAL nliiil1ii : STD_LOGIC := '0'; + SIGNAL nliiil1il : STD_LOGIC := '0'; + SIGNAL nliiil1iO : STD_LOGIC := '0'; + SIGNAL nliiil1li : STD_LOGIC := '0'; + SIGNAL nliiil1ll : STD_LOGIC := '0'; + SIGNAL nliiil1lO : STD_LOGIC := '0'; + SIGNAL nliiil1Oi : STD_LOGIC := '0'; + SIGNAL nliiil1Ol : STD_LOGIC := '0'; + SIGNAL nliiil1OO : STD_LOGIC := '0'; + SIGNAL nliiili0i : STD_LOGIC := '0'; + SIGNAL nliiili0l : STD_LOGIC := '0'; + SIGNAL nliiili0O : STD_LOGIC := '0'; + SIGNAL nliiili1i : STD_LOGIC := '0'; + SIGNAL nliiili1l : STD_LOGIC := '0'; + SIGNAL nliiili1O : STD_LOGIC := '0'; + SIGNAL nliiiliii : STD_LOGIC := '0'; + SIGNAL nliiiliil : STD_LOGIC := '0'; + SIGNAL nliiiliiO : STD_LOGIC := '0'; + SIGNAL nliiilili : STD_LOGIC := '0'; + SIGNAL nliiilill : STD_LOGIC := '0'; + SIGNAL nliiililO : STD_LOGIC := '0'; + SIGNAL nliiiliOi : STD_LOGIC := '0'; + SIGNAL nliiiliOl : STD_LOGIC := '0'; + SIGNAL nliiiliOO : STD_LOGIC := '0'; + SIGNAL nliiill0i : STD_LOGIC := '0'; + SIGNAL nliiill0l : STD_LOGIC := '0'; + SIGNAL nliiill0O : STD_LOGIC := '0'; + SIGNAL nliiill1i : STD_LOGIC := '0'; + SIGNAL nliiill1l : STD_LOGIC := '0'; + SIGNAL nliiill1O : STD_LOGIC := '0'; + SIGNAL nliiO011i : STD_LOGIC := '0'; + SIGNAL nliiO011l : STD_LOGIC := '0'; + SIGNAL nliiO0i0i : STD_LOGIC := '0'; + SIGNAL nliiO0iii : STD_LOGIC := '0'; + SIGNAL nliiO0iil : STD_LOGIC := '0'; + SIGNAL nliiO0iiO : STD_LOGIC := '0'; + SIGNAL nliiO0ill : STD_LOGIC := '0'; + SIGNAL nliiO0l1i : STD_LOGIC := '0'; + SIGNAL nliiO0O0O : STD_LOGIC := '0'; + SIGNAL nliiO0Oii : STD_LOGIC := '0'; + SIGNAL nliiO0Oil : STD_LOGIC := '0'; + SIGNAL nliiO0OiO : STD_LOGIC := '0'; + SIGNAL nliiO0Oli : STD_LOGIC := '0'; + SIGNAL nliiO0Oll : STD_LOGIC := '0'; + SIGNAL nliiO0OlO : STD_LOGIC := '0'; + SIGNAL nliiO0OOi : STD_LOGIC := '0'; + SIGNAL nliiO0OOl : STD_LOGIC := '0'; + SIGNAL nliiO0OOO : STD_LOGIC := '0'; + SIGNAL nliiO100i : STD_LOGIC := '0'; + SIGNAL nliiO100l : STD_LOGIC := '0'; + SIGNAL nliiO100O : STD_LOGIC := '0'; + SIGNAL nliiO101i : STD_LOGIC := '0'; + SIGNAL nliiO101l : STD_LOGIC := '0'; + SIGNAL nliiO101O : STD_LOGIC := '0'; + SIGNAL nliiO11OO : STD_LOGIC := '0'; + SIGNAL nliiO1l0l : STD_LOGIC := '0'; + SIGNAL nliiO1l0O : STD_LOGIC := '0'; + SIGNAL nliiO1lii : STD_LOGIC := '0'; + SIGNAL nliiO1lil : STD_LOGIC := '0'; + SIGNAL nliiO1liO : STD_LOGIC := '0'; + SIGNAL nliiO1lli : STD_LOGIC := '0'; + SIGNAL nliiO1OlO : STD_LOGIC := '0'; + SIGNAL nliiO1OOi : STD_LOGIC := '0'; + SIGNAL nliiO1OOl : STD_LOGIC := '0'; + SIGNAL nliiO1OOO : STD_LOGIC := '0'; + SIGNAL nliiOi11i : STD_LOGIC := '0'; + SIGNAL nliiOi11l : STD_LOGIC := '0'; + SIGNAL nliiOii0i : STD_LOGIC := '0'; + SIGNAL nliiOii0l : STD_LOGIC := '0'; + SIGNAL nliiOii0O : STD_LOGIC := '0'; + SIGNAL nliiOii1i : STD_LOGIC := '0'; + SIGNAL nliiOii1l : STD_LOGIC := '0'; + SIGNAL nliiOii1O : STD_LOGIC := '0'; + SIGNAL nliiOiiii : STD_LOGIC := '0'; + SIGNAL nliiOiiil : STD_LOGIC := '0'; + SIGNAL nliiOiiiO : STD_LOGIC := '0'; + SIGNAL nliiOiili : STD_LOGIC := '0'; + SIGNAL nliiOiill : STD_LOGIC := '0'; + SIGNAL nliiOiiOi : STD_LOGIC := '0'; + SIGNAL wire_nliiOiilO_w_lg_w_lg_nliiO0Oii44493w45047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_w_lg_nliiO0Oil44494w45046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_w_lg_nliiO0Oll44497w45043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_w_lg_nliiO0OOl44500w45040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11ilOi46310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11l1ll46317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11l1lO48215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11li1i46531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11O1il46532w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11O1iO46533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11O1li46536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11O1ll46535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11O1lO46534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli11O1Oi46539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nli1ilO1O46374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OO0l44688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OO0O44687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOii44686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOil44685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOiO44684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOli44683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOll44682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOlO44681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOOi44680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOOl44679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii0OOOO44678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nlii1l1ll44689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii001i44467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii001l44673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii001O44476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii01Oi44670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii01Ol44671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii01OO44672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii100i44691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii100l44690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii100O44669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii101i44694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii101l44693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii101O44692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii110i44674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii110l44705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii110O44704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii111i44677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii111l44676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii111O44675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11ii44703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11il44702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11iO44701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11li44700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11ll44699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11lO44698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11Oi44697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11Ol44696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliii11OO44695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiO0i44592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiO0l44591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiO0O44590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiO1l44594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiO1O44593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOii44589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOil44588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOiO44587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOli44586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOll44585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOlO44584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOOi44583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOOl44582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiiOOO44581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil00i44561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil00l44560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil00O44559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil01i44565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil01l44564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil01O44563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0ii44558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0il44557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0iO44556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0li44555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0ll44554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0lO44553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0Oi44552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0Ol44551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil0OO44550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil10i44577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil10l44576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil10O44575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil11i44580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil11l44579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil11O44578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1ii44574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1il44573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1iO44572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1li44571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1ll44570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1lO44569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1Oi44568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1Ol44567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiil1OO44566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiili0i44546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiili0l44545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiili0O44544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiili1i44549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiili1l44548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiili1O44547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiliii44543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiliil44542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiliiO44541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiilili44540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiilill44539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiililO44538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiliOi44537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiliOl44536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiiliOO44535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiill0i44531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiill0l44530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiill0O44520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiill1i44534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiill1l44533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiill1O44532w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO011i44513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO011l44316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0i0i44311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0iii44300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0iil44294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0iiO44289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0ill44279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0l1i44491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0O0O44492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0Oii44493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0Oil44494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0OiO44495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0Oli44496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0Oll44497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0OlO44498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0OOi44499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0OOl44500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO0OOO44501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO100i44525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO100l44524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO100O44367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO101i44528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO101l44527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO101O44526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO11OO44522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1l0l44515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1l0O44516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1lii44517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1lil44518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1liO44519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1lli44508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1OlO44509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1OOi44510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1OOl44511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiO1OOO44512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOi11i44502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOi11l44479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOii0i44483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOii0l44484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOii1i44480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOii1l44481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOii1O44482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOiiil44486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOiiiO44487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOiili44488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOiill44489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOiilO_w_lg_nliiOiiOi44490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl010Oi1i : STD_LOGIC := '0'; + SIGNAL nl10liOii : STD_LOGIC := '0'; + SIGNAL nl10lliii : STD_LOGIC := '0'; + SIGNAL nl10lliOl : STD_LOGIC := '0'; + SIGNAL nl111i1il : STD_LOGIC := '0'; + SIGNAL nl111iOiO : STD_LOGIC := '0'; + SIGNAL nl11OO0ii : STD_LOGIC := '0'; + SIGNAL nl11OOi1O : STD_LOGIC := '0'; + SIGNAL nl1l1iO0O : STD_LOGIC := '0'; + SIGNAL nl1l1iOll : STD_LOGIC := '0'; + SIGNAL nl1ll0iOO : STD_LOGIC := '0'; + SIGNAL nl1OilO0i : STD_LOGIC := '0'; + SIGNAL nl1OOii1O : STD_LOGIC := '0'; + SIGNAL nli1i010i : STD_LOGIC := '0'; + SIGNAL nli1i010l : STD_LOGIC := '0'; + SIGNAL nli1i010O : STD_LOGIC := '0'; + SIGNAL nli1i011l : STD_LOGIC := '0'; + SIGNAL nli1i011O : STD_LOGIC := '0'; + SIGNAL nli1i01ii : STD_LOGIC := '0'; + SIGNAL nli1i01il : STD_LOGIC := '0'; + SIGNAL nli1i01iO : STD_LOGIC := '0'; + SIGNAL nli1iOi0O : STD_LOGIC := '0'; + SIGNAL nli1iOiil : STD_LOGIC := '0'; + SIGNAL nli1iOiOi : STD_LOGIC := '0'; + SIGNAL nli1lilll : STD_LOGIC := '0'; + SIGNAL nli1lillO : STD_LOGIC := '0'; + SIGNAL nli1lilOi : STD_LOGIC := '0'; + SIGNAL nli1lilOl : STD_LOGIC := '0'; + SIGNAL nli1lilOO : STD_LOGIC := '0'; + SIGNAL nli1liO1i : STD_LOGIC := '0'; + SIGNAL nli1liO1l : STD_LOGIC := '0'; + SIGNAL nlil00ilO : STD_LOGIC := '0'; + SIGNAL nliliO10l : STD_LOGIC := '0'; + SIGNAL wire_nliliO10i_w_lg_w_lg_w_lg_w_lg_nl1OOii1O8962w8964w8965w8966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_w_lg_w_lg_nl1OOii1O8962w8964w8965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_w_lg_nl1OOii1O8962w8964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl1OilO0i56530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl1OOii1O8962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl10liOii43901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl111iOiO43397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl11OO0ii59868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl11OOi1O60227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl1ll0iOO55045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl1OilO0i55044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl1OOii1O54515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1iOi0O46371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1iOiil46373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1iOiOi46376w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1lilll47853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1lillO47852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1lilOi47851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1lilOl47850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1lilOO47849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1liO1i47848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nli1liO1l47847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_w_lg_nl10liOii43901w43902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_w_lg_nl1ll0iOO55586w55587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl1ll0iOO55831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO10i_w_lg_nl1ll0iOO55586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nl00l0O0i : STD_LOGIC := '0'; + SIGNAL nl00l0O0l : STD_LOGIC := '0'; + SIGNAL nl00l0O0O : STD_LOGIC := '0'; + SIGNAL nl00l0Oii : STD_LOGIC := '0'; + SIGNAL nl00l0Oil : STD_LOGIC := '0'; + SIGNAL nl00l0OiO : STD_LOGIC := '0'; + SIGNAL nl00l0Oli : STD_LOGIC := '0'; + SIGNAL nl00l0Oll : STD_LOGIC := '0'; + SIGNAL nl00l0OlO : STD_LOGIC := '0'; + SIGNAL nl00l0OOi : STD_LOGIC := '0'; + SIGNAL nl00l0OOl : STD_LOGIC := '0'; + SIGNAL nl00l0OOO : STD_LOGIC := '0'; + SIGNAL nl00l11il : STD_LOGIC := '0'; + SIGNAL nl00l11iO : STD_LOGIC := '0'; + SIGNAL nl00li00i : STD_LOGIC := '0'; + SIGNAL nl00li00l : STD_LOGIC := '0'; + SIGNAL nl00li00O : STD_LOGIC := '0'; + SIGNAL nl00li01i : STD_LOGIC := '0'; + SIGNAL nl00li01l : STD_LOGIC := '0'; + SIGNAL nl00li01O : STD_LOGIC := '0'; + SIGNAL nl00li0ii : STD_LOGIC := '0'; + SIGNAL nl00li0il : STD_LOGIC := '0'; + SIGNAL nl00li0iO : STD_LOGIC := '0'; + SIGNAL nl00li0li : STD_LOGIC := '0'; + SIGNAL nl00li0ll : STD_LOGIC := '0'; + SIGNAL nl00li0lO : STD_LOGIC := '0'; + SIGNAL nl00li0Oi : STD_LOGIC := '0'; + SIGNAL nl00li0Ol : STD_LOGIC := '0'; + SIGNAL nl00li0OO : STD_LOGIC := '0'; + SIGNAL nl00li10i : STD_LOGIC := '0'; + SIGNAL nl00li10l : STD_LOGIC := '0'; + SIGNAL nl00li10O : STD_LOGIC := '0'; + SIGNAL nl00li11i : STD_LOGIC := '0'; + SIGNAL nl00li11l : STD_LOGIC := '0'; + SIGNAL nl00li11O : STD_LOGIC := '0'; + SIGNAL nl00li1ii : STD_LOGIC := '0'; + SIGNAL nl00li1il : STD_LOGIC := '0'; + SIGNAL nl00li1iO : STD_LOGIC := '0'; + SIGNAL nl00li1li : STD_LOGIC := '0'; + SIGNAL nl00li1ll : STD_LOGIC := '0'; + SIGNAL nl00li1lO : STD_LOGIC := '0'; + SIGNAL nl00li1Oi : STD_LOGIC := '0'; + SIGNAL nl00li1Ol : STD_LOGIC := '0'; + SIGNAL nl00li1OO : STD_LOGIC := '0'; + SIGNAL nl00lii0i : STD_LOGIC := '0'; + SIGNAL nl00lii0l : STD_LOGIC := '0'; + SIGNAL nl00lii0O : STD_LOGIC := '0'; + SIGNAL nl00lii1i : STD_LOGIC := '0'; + SIGNAL nl00lii1l : STD_LOGIC := '0'; + SIGNAL nl00lii1O : STD_LOGIC := '0'; + SIGNAL nl00liiii : STD_LOGIC := '0'; + SIGNAL nl00liiil : STD_LOGIC := '0'; + SIGNAL nl00liiiO : STD_LOGIC := '0'; + SIGNAL nl00liili : STD_LOGIC := '0'; + SIGNAL nl00liill : STD_LOGIC := '0'; + SIGNAL nl00liilO : STD_LOGIC := '0'; + SIGNAL nl00liiOi : STD_LOGIC := '0'; + SIGNAL nl00liiOl : STD_LOGIC := '0'; + SIGNAL nl00liiOO : STD_LOGIC := '0'; + SIGNAL nl00lil0i : STD_LOGIC := '0'; + SIGNAL nl00lil0l : STD_LOGIC := '0'; + SIGNAL nl00lil0O : STD_LOGIC := '0'; + SIGNAL nl00lil1i : STD_LOGIC := '0'; + SIGNAL nl00lil1l : STD_LOGIC := '0'; + SIGNAL nl00lil1O : STD_LOGIC := '0'; + SIGNAL nl00lilii : STD_LOGIC := '0'; + SIGNAL nl00lilil : STD_LOGIC := '0'; + SIGNAL nl00liliO : STD_LOGIC := '0'; + SIGNAL nl00lilli : STD_LOGIC := '0'; + SIGNAL nl00lilll : STD_LOGIC := '0'; + SIGNAL nl00lillO : STD_LOGIC := '0'; + SIGNAL nl00lilOi : STD_LOGIC := '0'; + SIGNAL nl00lilOl : STD_LOGIC := '0'; + SIGNAL nl00lilOO : STD_LOGIC := '0'; + SIGNAL nl00liO0i : STD_LOGIC := '0'; + SIGNAL nl00liO0l : STD_LOGIC := '0'; + SIGNAL nl00liO0O : STD_LOGIC := '0'; + SIGNAL nl00liO1i : STD_LOGIC := '0'; + SIGNAL nl00liO1l : STD_LOGIC := '0'; + SIGNAL nl00liO1O : STD_LOGIC := '0'; + SIGNAL nl00liOii : STD_LOGIC := '0'; + SIGNAL nl00liOil : STD_LOGIC := '0'; + SIGNAL nl00liOiO : STD_LOGIC := '0'; + SIGNAL nl00liOli : STD_LOGIC := '0'; + SIGNAL nl00liOll : STD_LOGIC := '0'; + SIGNAL nl00liOlO : STD_LOGIC := '0'; + SIGNAL nl00liOOi : STD_LOGIC := '0'; + SIGNAL nl00liOOl : STD_LOGIC := '0'; + SIGNAL nl00liOOO : STD_LOGIC := '0'; + SIGNAL nl00ll00i : STD_LOGIC := '0'; + SIGNAL nl00ll00l : STD_LOGIC := '0'; + SIGNAL nl00ll00O : STD_LOGIC := '0'; + SIGNAL nl00ll01i : STD_LOGIC := '0'; + SIGNAL nl00ll01l : STD_LOGIC := '0'; + SIGNAL nl00ll01O : STD_LOGIC := '0'; + SIGNAL nl00ll0ii : STD_LOGIC := '0'; + SIGNAL nl00ll0il : STD_LOGIC := '0'; + SIGNAL nl00ll0iO : STD_LOGIC := '0'; + SIGNAL nl00ll0li : STD_LOGIC := '0'; + SIGNAL nl00ll0ll : STD_LOGIC := '0'; + SIGNAL nl00ll0lO : STD_LOGIC := '0'; + SIGNAL nl00ll0Oi : STD_LOGIC := '0'; + SIGNAL nl00ll0Ol : STD_LOGIC := '0'; + SIGNAL nl00ll0OO : STD_LOGIC := '0'; + SIGNAL nl00ll10i : STD_LOGIC := '0'; + SIGNAL nl00ll10l : STD_LOGIC := '0'; + SIGNAL nl00ll10O : STD_LOGIC := '0'; + SIGNAL nl00ll11i : STD_LOGIC := '0'; + SIGNAL nl00ll11l : STD_LOGIC := '0'; + SIGNAL nl00ll11O : STD_LOGIC := '0'; + SIGNAL nl00ll1ii : STD_LOGIC := '0'; + SIGNAL nl00ll1il : STD_LOGIC := '0'; + SIGNAL nl00ll1iO : STD_LOGIC := '0'; + SIGNAL nl00ll1li : STD_LOGIC := '0'; + SIGNAL nl00ll1ll : STD_LOGIC := '0'; + SIGNAL nl00ll1lO : STD_LOGIC := '0'; + SIGNAL nl00ll1Oi : STD_LOGIC := '0'; + SIGNAL nl00ll1Ol : STD_LOGIC := '0'; + SIGNAL nl00ll1OO : STD_LOGIC := '0'; + SIGNAL nl00lli0i : STD_LOGIC := '0'; + SIGNAL nl00lli0l : STD_LOGIC := '0'; + SIGNAL nl00lli0O : STD_LOGIC := '0'; + SIGNAL nl00lli1i : STD_LOGIC := '0'; + SIGNAL nl00lli1l : STD_LOGIC := '0'; + SIGNAL nl00lli1O : STD_LOGIC := '0'; + SIGNAL nl00lliii : STD_LOGIC := '0'; + SIGNAL nl00lliil : STD_LOGIC := '0'; + SIGNAL nl00lliiO : STD_LOGIC := '0'; + SIGNAL nl00llili : STD_LOGIC := '0'; + SIGNAL nl00llill : STD_LOGIC := '0'; + SIGNAL nl00llilO : STD_LOGIC := '0'; + SIGNAL nl00lliOi : STD_LOGIC := '0'; + SIGNAL nl00lliOl : STD_LOGIC := '0'; + SIGNAL nl00lliOO : STD_LOGIC := '0'; + SIGNAL nl00lll0i : STD_LOGIC := '0'; + SIGNAL nl00lll0l : STD_LOGIC := '0'; + SIGNAL nl00lll0O : STD_LOGIC := '0'; + SIGNAL nl00lll1i : STD_LOGIC := '0'; + SIGNAL nl00lll1l : STD_LOGIC := '0'; + SIGNAL nl00lll1O : STD_LOGIC := '0'; + SIGNAL nl00lllii : STD_LOGIC := '0'; + SIGNAL nl00lllil : STD_LOGIC := '0'; + SIGNAL nl010000i : STD_LOGIC := '0'; + SIGNAL nl010000l : STD_LOGIC := '0'; + SIGNAL nl010000O : STD_LOGIC := '0'; + SIGNAL nl010001i : STD_LOGIC := '0'; + SIGNAL nl010001l : STD_LOGIC := '0'; + SIGNAL nl010001O : STD_LOGIC := '0'; + SIGNAL nl01000ii : STD_LOGIC := '0'; + SIGNAL nl01000il : STD_LOGIC := '0'; + SIGNAL nl01000iO : STD_LOGIC := '0'; + SIGNAL nl01000li : STD_LOGIC := '0'; + SIGNAL nl01000ll : STD_LOGIC := '0'; + SIGNAL nl01000lO : STD_LOGIC := '0'; + SIGNAL nl01000Oi : STD_LOGIC := '0'; + SIGNAL nl01000Ol : STD_LOGIC := '0'; + SIGNAL nl01000OO : STD_LOGIC := '0'; + SIGNAL nl010010i : STD_LOGIC := '0'; + SIGNAL nl010010l : STD_LOGIC := '0'; + SIGNAL nl010010O : STD_LOGIC := '0'; + SIGNAL nl010011i : STD_LOGIC := '0'; + SIGNAL nl010011l : STD_LOGIC := '0'; + SIGNAL nl010011O : STD_LOGIC := '0'; + SIGNAL nl01001ii : STD_LOGIC := '0'; + SIGNAL nl01001il : STD_LOGIC := '0'; + SIGNAL nl01001iO : STD_LOGIC := '0'; + SIGNAL nl01001li : STD_LOGIC := '0'; + SIGNAL nl01001ll : STD_LOGIC := '0'; + SIGNAL nl01001lO : STD_LOGIC := '0'; + SIGNAL nl01001Oi : STD_LOGIC := '0'; + SIGNAL nl01001Ol : STD_LOGIC := '0'; + SIGNAL nl01001OO : STD_LOGIC := '0'; + SIGNAL nl0100i0i : STD_LOGIC := '0'; + SIGNAL nl0100i0l : STD_LOGIC := '0'; + SIGNAL nl0100i0O : STD_LOGIC := '0'; + SIGNAL nl0100i1i : STD_LOGIC := '0'; + SIGNAL nl0100i1l : STD_LOGIC := '0'; + SIGNAL nl0100i1O : STD_LOGIC := '0'; + SIGNAL nl0100iii : STD_LOGIC := '0'; + SIGNAL nl0100iil : STD_LOGIC := '0'; + SIGNAL nl0100iiO : STD_LOGIC := '0'; + SIGNAL nl0100ili : STD_LOGIC := '0'; + SIGNAL nl0100ill : STD_LOGIC := '0'; + SIGNAL nl0100ilO : STD_LOGIC := '0'; + SIGNAL nl0100iOi : STD_LOGIC := '0'; + SIGNAL nl0100iOl : STD_LOGIC := '0'; + SIGNAL nl0100iOO : STD_LOGIC := '0'; + SIGNAL nl0100l0i : STD_LOGIC := '0'; + SIGNAL nl0100l0l : STD_LOGIC := '0'; + SIGNAL nl0100l0O : STD_LOGIC := '0'; + SIGNAL nl0100l1i : STD_LOGIC := '0'; + SIGNAL nl0100l1l : STD_LOGIC := '0'; + SIGNAL nl0100l1O : STD_LOGIC := '0'; + SIGNAL nl0100lii : STD_LOGIC := '0'; + SIGNAL nl0100lil : STD_LOGIC := '0'; + SIGNAL nl0100liO : STD_LOGIC := '0'; + SIGNAL nl0100lli : STD_LOGIC := '0'; + SIGNAL nl0100lll : STD_LOGIC := '0'; + SIGNAL nl0100llO : STD_LOGIC := '0'; + SIGNAL nl0100lOi : STD_LOGIC := '0'; + SIGNAL nl0100lOl : STD_LOGIC := '0'; + SIGNAL nl0100lOO : STD_LOGIC := '0'; + SIGNAL nl0100O0i : STD_LOGIC := '0'; + SIGNAL nl0100O0l : STD_LOGIC := '0'; + SIGNAL nl0100O0O : STD_LOGIC := '0'; + SIGNAL nl0100O1i : STD_LOGIC := '0'; + SIGNAL nl0100O1l : STD_LOGIC := '0'; + SIGNAL nl0100O1O : STD_LOGIC := '0'; + SIGNAL nl0101lOl : STD_LOGIC := '0'; + SIGNAL nl0101lOO : STD_LOGIC := '0'; + SIGNAL nl0101O0i : STD_LOGIC := '0'; + SIGNAL nl0101O0l : STD_LOGIC := '0'; + SIGNAL nl0101O0O : STD_LOGIC := '0'; + SIGNAL nl0101O1i : STD_LOGIC := '0'; + SIGNAL nl0101O1l : STD_LOGIC := '0'; + SIGNAL nl0101O1O : STD_LOGIC := '0'; + SIGNAL nl0101Oii : STD_LOGIC := '0'; + SIGNAL nl0101Oil : STD_LOGIC := '0'; + SIGNAL nl0101OiO : STD_LOGIC := '0'; + SIGNAL nl0101Oli : STD_LOGIC := '0'; + SIGNAL nl0101Oll : STD_LOGIC := '0'; + SIGNAL nl0101OlO : STD_LOGIC := '0'; + SIGNAL nl0101OOi : STD_LOGIC := '0'; + SIGNAL nl0101OOl : STD_LOGIC := '0'; + SIGNAL nl0101OOO : STD_LOGIC := '0'; + SIGNAL nl010Olil : STD_LOGIC := '0'; + SIGNAL nl010OliO : STD_LOGIC := '0'; + SIGNAL nl010Olli : STD_LOGIC := '0'; + SIGNAL nl010Olll : STD_LOGIC := '0'; + SIGNAL nl010OllO : STD_LOGIC := '0'; + SIGNAL nl010OlOi : STD_LOGIC := '0'; + SIGNAL nl010OlOl : STD_LOGIC := '0'; + SIGNAL nl010OlOO : STD_LOGIC := '0'; + SIGNAL nl0111iil : STD_LOGIC := '0'; + SIGNAL nl0111iiO : STD_LOGIC := '0'; + SIGNAL nl0111ili : STD_LOGIC := '0'; + SIGNAL nl0111ill : STD_LOGIC := '0'; + SIGNAL nl0111ilO : STD_LOGIC := '0'; + SIGNAL nl0111iOi : STD_LOGIC := '0'; + SIGNAL nl0111iOl : STD_LOGIC := '0'; + SIGNAL nl0111iOO : STD_LOGIC := '0'; + SIGNAL nl0111l0i : STD_LOGIC := '0'; + SIGNAL nl0111l0l : STD_LOGIC := '0'; + SIGNAL nl0111l0O : STD_LOGIC := '0'; + SIGNAL nl0111l1i : STD_LOGIC := '0'; + SIGNAL nl0111l1l : STD_LOGIC := '0'; + SIGNAL nl0111l1O : STD_LOGIC := '0'; + SIGNAL nl0111lii : STD_LOGIC := '0'; + SIGNAL nl0111lil : STD_LOGIC := '0'; + SIGNAL nl0111liO : STD_LOGIC := '0'; + SIGNAL nl0111lli : STD_LOGIC := '0'; + SIGNAL nl0111lll : STD_LOGIC := '0'; + SIGNAL nl0111llO : STD_LOGIC := '0'; + SIGNAL nl0111lOi : STD_LOGIC := '0'; + SIGNAL nl0111lOl : STD_LOGIC := '0'; + SIGNAL nl0111lOO : STD_LOGIC := '0'; + SIGNAL nl0111O0i : STD_LOGIC := '0'; + SIGNAL nl0111O0l : STD_LOGIC := '0'; + SIGNAL nl0111O0O : STD_LOGIC := '0'; + SIGNAL nl0111O1i : STD_LOGIC := '0'; + SIGNAL nl0111O1l : STD_LOGIC := '0'; + SIGNAL nl0111O1O : STD_LOGIC := '0'; + SIGNAL nl0111Oii : STD_LOGIC := '0'; + SIGNAL nl0111Oil : STD_LOGIC := '0'; + SIGNAL nl0111OiO : STD_LOGIC := '0'; + SIGNAL nl0111Oli : STD_LOGIC := '0'; + SIGNAL nl0111Oll : STD_LOGIC := '0'; + SIGNAL nl0111OlO : STD_LOGIC := '0'; + SIGNAL nl011ilOl : STD_LOGIC := '0'; + SIGNAL nl011l0iO : STD_LOGIC := '0'; + SIGNAL nl011l0li : STD_LOGIC := '0'; + SIGNAL nl011l0ll : STD_LOGIC := '0'; + SIGNAL nl011l0lO : STD_LOGIC := '0'; + SIGNAL nl011l0Oi : STD_LOGIC := '0'; + SIGNAL nl011l0Ol : STD_LOGIC := '0'; + SIGNAL nl011l0OO : STD_LOGIC := '0'; + SIGNAL nl011l1ii : STD_LOGIC := '0'; + SIGNAL nl011l1il : STD_LOGIC := '0'; + SIGNAL nl011li0i : STD_LOGIC := '0'; + SIGNAL nl011li0l : STD_LOGIC := '0'; + SIGNAL nl011li0O : STD_LOGIC := '0'; + SIGNAL nl011li1i : STD_LOGIC := '0'; + SIGNAL nl011li1l : STD_LOGIC := '0'; + SIGNAL nl011li1O : STD_LOGIC := '0'; + SIGNAL nl011liii : STD_LOGIC := '0'; + SIGNAL nl011liil : STD_LOGIC := '0'; + SIGNAL nl011liiO : STD_LOGIC := '0'; + SIGNAL nl011lili : STD_LOGIC := '0'; + SIGNAL nl011lill : STD_LOGIC := '0'; + SIGNAL nl011lilO : STD_LOGIC := '0'; + SIGNAL nl011liOi : STD_LOGIC := '0'; + SIGNAL nl011liOl : STD_LOGIC := '0'; + SIGNAL nl011liOO : STD_LOGIC := '0'; + SIGNAL nl011ll0i : STD_LOGIC := '0'; + SIGNAL nl011ll1i : STD_LOGIC := '0'; + SIGNAL nl011ll1l : STD_LOGIC := '0'; + SIGNAL nl011ll1O : STD_LOGIC := '0'; + SIGNAL nl011OO1l : STD_LOGIC := '0'; + SIGNAL nl011OO1O : STD_LOGIC := '0'; + SIGNAL nl011OOlO : STD_LOGIC := '0'; + SIGNAL nl01i0O0O : STD_LOGIC := '0'; + SIGNAL nl01i0O1i : STD_LOGIC := '0'; + SIGNAL nl01i0Oii : STD_LOGIC := '0'; + SIGNAL nl01i0Oil : STD_LOGIC := '0'; + SIGNAL nl01i0OiO : STD_LOGIC := '0'; + SIGNAL nl01i0Oli : STD_LOGIC := '0'; + SIGNAL nl01i0Oll : STD_LOGIC := '0'; + SIGNAL nl01i0OlO : STD_LOGIC := '0'; + SIGNAL nl01i0OOi : STD_LOGIC := '0'; + SIGNAL nl01i0OOl : STD_LOGIC := '0'; + SIGNAL nl01i0OOO : STD_LOGIC := '0'; + SIGNAL nl01ii10i : STD_LOGIC := '0'; + SIGNAL nl01ii10l : STD_LOGIC := '0'; + SIGNAL nl01ii10O : STD_LOGIC := '0'; + SIGNAL nl01ii11i : STD_LOGIC := '0'; + SIGNAL nl01ii11l : STD_LOGIC := '0'; + SIGNAL nl01ii11O : STD_LOGIC := '0'; + SIGNAL nl01ii1ii : STD_LOGIC := '0'; + SIGNAL nl01ii1il : STD_LOGIC := '0'; + SIGNAL nl01ii1iO : STD_LOGIC := '0'; + SIGNAL nl01ii1li : STD_LOGIC := '0'; + SIGNAL nl01ii1ll : STD_LOGIC := '0'; + SIGNAL nl01ii1lO : STD_LOGIC := '0'; + SIGNAL nl01ii1Oi : STD_LOGIC := '0'; + SIGNAL nl01ii1Ol : STD_LOGIC := '0'; + SIGNAL nl01ii1OO : STD_LOGIC := '0'; + SIGNAL nl01l000i : STD_LOGIC := '0'; + SIGNAL nl01l000l : STD_LOGIC := '0'; + SIGNAL nl01l000O : STD_LOGIC := '0'; + SIGNAL nl01l001i : STD_LOGIC := '0'; + SIGNAL nl01l001l : STD_LOGIC := '0'; + SIGNAL nl01l001O : STD_LOGIC := '0'; + SIGNAL nl01l00ii : STD_LOGIC := '0'; + SIGNAL nl01l00il : STD_LOGIC := '0'; + SIGNAL nl01l00iO : STD_LOGIC := '0'; + SIGNAL nl01l00li : STD_LOGIC := '0'; + SIGNAL nl01l00ll : STD_LOGIC := '0'; + SIGNAL nl01l00lO : STD_LOGIC := '0'; + SIGNAL nl01l00Oi : STD_LOGIC := '0'; + SIGNAL nl01l00Ol : STD_LOGIC := '0'; + SIGNAL nl01l00OO : STD_LOGIC := '0'; + SIGNAL nl01l01ll : STD_LOGIC := '0'; + SIGNAL nl01l01lO : STD_LOGIC := '0'; + SIGNAL nl01l01Oi : STD_LOGIC := '0'; + SIGNAL nl01l01Ol : STD_LOGIC := '0'; + SIGNAL nl01l01OO : STD_LOGIC := '0'; + SIGNAL nl01l0i0i : STD_LOGIC := '0'; + SIGNAL nl01l0i0l : STD_LOGIC := '0'; + SIGNAL nl01l0i0O : STD_LOGIC := '0'; + SIGNAL nl01l0i1i : STD_LOGIC := '0'; + SIGNAL nl01l0i1l : STD_LOGIC := '0'; + SIGNAL nl01l0i1O : STD_LOGIC := '0'; + SIGNAL nl01l0iii : STD_LOGIC := '0'; + SIGNAL nl01l0iil : STD_LOGIC := '0'; + SIGNAL nl01l0iiO : STD_LOGIC := '0'; + SIGNAL nl01l0ili : STD_LOGIC := '0'; + SIGNAL nl01l0ill : STD_LOGIC := '0'; + SIGNAL nl01l0ilO : STD_LOGIC := '0'; + SIGNAL nl01l0iOi : STD_LOGIC := '0'; + SIGNAL nl01l0iOl : STD_LOGIC := '0'; + SIGNAL nl01l0iOO : STD_LOGIC := '0'; + SIGNAL nl01l0l0i : STD_LOGIC := '0'; + SIGNAL nl01l0l0l : STD_LOGIC := '0'; + SIGNAL nl01l0l0O : STD_LOGIC := '0'; + SIGNAL nl01l0l1i : STD_LOGIC := '0'; + SIGNAL nl01l0l1l : STD_LOGIC := '0'; + SIGNAL nl01l0l1O : STD_LOGIC := '0'; + SIGNAL nl01l0lii : STD_LOGIC := '0'; + SIGNAL nl01l0lil : STD_LOGIC := '0'; + SIGNAL nl01l0liO : STD_LOGIC := '0'; + SIGNAL nl01l0lli : STD_LOGIC := '0'; + SIGNAL nl01l0lll : STD_LOGIC := '0'; + SIGNAL nl01l0llO : STD_LOGIC := '0'; + SIGNAL nl01l0lOi : STD_LOGIC := '0'; + SIGNAL nl01l0lOl : STD_LOGIC := '0'; + SIGNAL nl01l0lOO : STD_LOGIC := '0'; + SIGNAL nl01l0O0i : STD_LOGIC := '0'; + SIGNAL nl01l0O1i : STD_LOGIC := '0'; + SIGNAL nl01l0O1l : STD_LOGIC := '0'; + SIGNAL nl01l0O1O : STD_LOGIC := '0'; + SIGNAL nl01lll0i : STD_LOGIC := '0'; + SIGNAL nl01lll0l : STD_LOGIC := '0'; + SIGNAL nl01lll0O : STD_LOGIC := '0'; + SIGNAL nl01lll1i : STD_LOGIC := '0'; + SIGNAL nl01lll1l : STD_LOGIC := '0'; + SIGNAL nl01lll1O : STD_LOGIC := '0'; + SIGNAL nl01lllii : STD_LOGIC := '0'; + SIGNAL nl01lllil : STD_LOGIC := '0'; + SIGNAL nl01llliO : STD_LOGIC := '0'; + SIGNAL nl01lllli : STD_LOGIC := '0'; + SIGNAL nl01lllll : STD_LOGIC := '0'; + SIGNAL nl01llllO : STD_LOGIC := '0'; + SIGNAL nl01lllOi : STD_LOGIC := '0'; + SIGNAL nl01lllOl : STD_LOGIC := '0'; + SIGNAL nl01lllOO : STD_LOGIC := '0'; + SIGNAL nl01lO0iO : STD_LOGIC := '0'; + SIGNAL nl01lO0li : STD_LOGIC := '0'; + SIGNAL nl01lO0ll : STD_LOGIC := '0'; + SIGNAL nl01lO0lO : STD_LOGIC := '0'; + SIGNAL nl01lO0Oi : STD_LOGIC := '0'; + SIGNAL nl01lO0Ol : STD_LOGIC := '0'; + SIGNAL nl01lO0OO : STD_LOGIC := '0'; + SIGNAL nl01lOi0i : STD_LOGIC := '0'; + SIGNAL nl01lOi0l : STD_LOGIC := '0'; + SIGNAL nl01lOi0O : STD_LOGIC := '0'; + SIGNAL nl01lOi1i : STD_LOGIC := '0'; + SIGNAL nl01lOi1l : STD_LOGIC := '0'; + SIGNAL nl01lOi1O : STD_LOGIC := '0'; + SIGNAL nl01lOiii : STD_LOGIC := '0'; + SIGNAL nl01lOiil : STD_LOGIC := '0'; + SIGNAL nl01lOiiO : STD_LOGIC := '0'; + SIGNAL nl01lOili : STD_LOGIC := '0'; + SIGNAL nl01lOill : STD_LOGIC := '0'; + SIGNAL nl01lOilO : STD_LOGIC := '0'; + SIGNAL nl01lOiOi : STD_LOGIC := '0'; + SIGNAL nl01lOiOl : STD_LOGIC := '0'; + SIGNAL nl01lOiOO : STD_LOGIC := '0'; + SIGNAL nl01lOl0i : STD_LOGIC := '0'; + SIGNAL nl01lOl0l : STD_LOGIC := '0'; + SIGNAL nl01lOl0O : STD_LOGIC := '0'; + SIGNAL nl01lOl1i : STD_LOGIC := '0'; + SIGNAL nl01lOl1l : STD_LOGIC := '0'; + SIGNAL nl01lOl1O : STD_LOGIC := '0'; + SIGNAL nl01lOlii : STD_LOGIC := '0'; + SIGNAL nl01lOlil : STD_LOGIC := '0'; + SIGNAL nl01lOliO : STD_LOGIC := '0'; + SIGNAL nl01lOlli : STD_LOGIC := '0'; + SIGNAL nl01lOlll : STD_LOGIC := '0'; + SIGNAL nl01lOllO : STD_LOGIC := '0'; + SIGNAL nl01lOlOi : STD_LOGIC := '0'; + SIGNAL nl01lOlOl : STD_LOGIC := '0'; + SIGNAL nl01lOlOO : STD_LOGIC := '0'; + SIGNAL nl01lOO0i : STD_LOGIC := '0'; + SIGNAL nl01lOO0l : STD_LOGIC := '0'; + SIGNAL nl01lOO0O : STD_LOGIC := '0'; + SIGNAL nl01lOO1i : STD_LOGIC := '0'; + SIGNAL nl01lOO1l : STD_LOGIC := '0'; + SIGNAL nl01lOO1O : STD_LOGIC := '0'; + SIGNAL nl01lOOii : STD_LOGIC := '0'; + SIGNAL nl01lOOil : STD_LOGIC := '0'; + SIGNAL nl01lOOiO : STD_LOGIC := '0'; + SIGNAL nl01lOOli : STD_LOGIC := '0'; + SIGNAL nl01lOOll : STD_LOGIC := '0'; + SIGNAL nl01lOOlO : STD_LOGIC := '0'; + SIGNAL nl01lOOOi : STD_LOGIC := '0'; + SIGNAL nl01lOOOl : STD_LOGIC := '0'; + SIGNAL nl01lOOOO : STD_LOGIC := '0'; + SIGNAL nl01O011i : STD_LOGIC := '0'; + SIGNAL nl01O011l : STD_LOGIC := '0'; + SIGNAL nl01O100i : STD_LOGIC := '0'; + SIGNAL nl01O100l : STD_LOGIC := '0'; + SIGNAL nl01O100O : STD_LOGIC := '0'; + SIGNAL nl01O101i : STD_LOGIC := '0'; + SIGNAL nl01O101l : STD_LOGIC := '0'; + SIGNAL nl01O101O : STD_LOGIC := '0'; + SIGNAL nl01O10ii : STD_LOGIC := '0'; + SIGNAL nl01O10il : STD_LOGIC := '0'; + SIGNAL nl01O10iO : STD_LOGIC := '0'; + SIGNAL nl01O10li : STD_LOGIC := '0'; + SIGNAL nl01O10ll : STD_LOGIC := '0'; + SIGNAL nl01O10lO : STD_LOGIC := '0'; + SIGNAL nl01O10Oi : STD_LOGIC := '0'; + SIGNAL nl01O10Ol : STD_LOGIC := '0'; + SIGNAL nl01O10OO : STD_LOGIC := '0'; + SIGNAL nl01O110i : STD_LOGIC := '0'; + SIGNAL nl01O110l : STD_LOGIC := '0'; + SIGNAL nl01O110O : STD_LOGIC := '0'; + SIGNAL nl01O111i : STD_LOGIC := '0'; + SIGNAL nl01O111l : STD_LOGIC := '0'; + SIGNAL nl01O111O : STD_LOGIC := '0'; + SIGNAL nl01O11ii : STD_LOGIC := '0'; + SIGNAL nl01O11il : STD_LOGIC := '0'; + SIGNAL nl01O11iO : STD_LOGIC := '0'; + SIGNAL nl01O11li : STD_LOGIC := '0'; + SIGNAL nl01O11ll : STD_LOGIC := '0'; + SIGNAL nl01O11lO : STD_LOGIC := '0'; + SIGNAL nl01O11Oi : STD_LOGIC := '0'; + SIGNAL nl01O11Ol : STD_LOGIC := '0'; + SIGNAL nl01O11OO : STD_LOGIC := '0'; + SIGNAL nl01O1i0i : STD_LOGIC := '0'; + SIGNAL nl01O1i0l : STD_LOGIC := '0'; + SIGNAL nl01O1i0O : STD_LOGIC := '0'; + SIGNAL nl01O1i1i : STD_LOGIC := '0'; + SIGNAL nl01O1i1l : STD_LOGIC := '0'; + SIGNAL nl01O1i1O : STD_LOGIC := '0'; + SIGNAL nl01O1iii : STD_LOGIC := '0'; + SIGNAL nl01O1iil : STD_LOGIC := '0'; + SIGNAL nl01O1iiO : STD_LOGIC := '0'; + SIGNAL nl01O1ili : STD_LOGIC := '0'; + SIGNAL nl01O1ill : STD_LOGIC := '0'; + SIGNAL nl01O1ilO : STD_LOGIC := '0'; + SIGNAL nl01O1iOi : STD_LOGIC := '0'; + SIGNAL nl01O1iOl : STD_LOGIC := '0'; + SIGNAL nl01O1iOO : STD_LOGIC := '0'; + SIGNAL nl01O1l0i : STD_LOGIC := '0'; + SIGNAL nl01O1l0l : STD_LOGIC := '0'; + SIGNAL nl01O1l0O : STD_LOGIC := '0'; + SIGNAL nl01O1l1i : STD_LOGIC := '0'; + SIGNAL nl01O1l1l : STD_LOGIC := '0'; + SIGNAL nl01O1l1O : STD_LOGIC := '0'; + SIGNAL nl01O1lii : STD_LOGIC := '0'; + SIGNAL nl01O1lil : STD_LOGIC := '0'; + SIGNAL nl01O1liO : STD_LOGIC := '0'; + SIGNAL nl01O1lli : STD_LOGIC := '0'; + SIGNAL nl01O1lll : STD_LOGIC := '0'; + SIGNAL nl01O1llO : STD_LOGIC := '0'; + SIGNAL nl01O1lOi : STD_LOGIC := '0'; + SIGNAL nl01O1lOl : STD_LOGIC := '0'; + SIGNAL nl01O1lOO : STD_LOGIC := '0'; + SIGNAL nl01O1O0i : STD_LOGIC := '0'; + SIGNAL nl01O1O0l : STD_LOGIC := '0'; + SIGNAL nl01O1O0O : STD_LOGIC := '0'; + SIGNAL nl01O1O1i : STD_LOGIC := '0'; + SIGNAL nl01O1O1l : STD_LOGIC := '0'; + SIGNAL nl01O1O1O : STD_LOGIC := '0'; + SIGNAL nl01O1Oii : STD_LOGIC := '0'; + SIGNAL nl01O1Oil : STD_LOGIC := '0'; + SIGNAL nl01O1OiO : STD_LOGIC := '0'; + SIGNAL nl01O1Oli : STD_LOGIC := '0'; + SIGNAL nl01O1Oll : STD_LOGIC := '0'; + SIGNAL nl01O1OlO : STD_LOGIC := '0'; + SIGNAL nl01O1OOi : STD_LOGIC := '0'; + SIGNAL nl01O1OOl : STD_LOGIC := '0'; + SIGNAL nl01O1OOO : STD_LOGIC := '0'; + SIGNAL nl0i0000i : STD_LOGIC := '0'; + SIGNAL nl0i0000l : STD_LOGIC := '0'; + SIGNAL nl0i0000O : STD_LOGIC := '0'; + SIGNAL nl0i0001i : STD_LOGIC := '0'; + SIGNAL nl0i0001l : STD_LOGIC := '0'; + SIGNAL nl0i0001O : STD_LOGIC := '0'; + SIGNAL nl0i000ii : STD_LOGIC := '0'; + SIGNAL nl0i000il : STD_LOGIC := '0'; + SIGNAL nl0i000iO : STD_LOGIC := '0'; + SIGNAL nl0i000li : STD_LOGIC := '0'; + SIGNAL nl0i000ll : STD_LOGIC := '0'; + SIGNAL nl0i000lO : STD_LOGIC := '0'; + SIGNAL nl0i000Oi : STD_LOGIC := '0'; + SIGNAL nl0i000Ol : STD_LOGIC := '0'; + SIGNAL nl0i000OO : STD_LOGIC := '0'; + SIGNAL nl0i0010i : STD_LOGIC := '0'; + SIGNAL nl0i0010l : STD_LOGIC := '0'; + SIGNAL nl0i0010O : STD_LOGIC := '0'; + SIGNAL nl0i0011i : STD_LOGIC := '0'; + SIGNAL nl0i0011l : STD_LOGIC := '0'; + SIGNAL nl0i0011O : STD_LOGIC := '0'; + SIGNAL nl0i001ii : STD_LOGIC := '0'; + SIGNAL nl0i001il : STD_LOGIC := '0'; + SIGNAL nl0i001iO : STD_LOGIC := '0'; + SIGNAL nl0i001li : STD_LOGIC := '0'; + SIGNAL nl0i001ll : STD_LOGIC := '0'; + SIGNAL nl0i001lO : STD_LOGIC := '0'; + SIGNAL nl0i001Oi : STD_LOGIC := '0'; + SIGNAL nl0i001Ol : STD_LOGIC := '0'; + SIGNAL nl0i001OO : STD_LOGIC := '0'; + SIGNAL nl0i00i0i : STD_LOGIC := '0'; + SIGNAL nl0i00i0l : STD_LOGIC := '0'; + SIGNAL nl0i00i0O : STD_LOGIC := '0'; + SIGNAL nl0i00i1i : STD_LOGIC := '0'; + SIGNAL nl0i00i1l : STD_LOGIC := '0'; + SIGNAL nl0i00i1O : STD_LOGIC := '0'; + SIGNAL nl0i00iii : STD_LOGIC := '0'; + SIGNAL nl0i00iil : STD_LOGIC := '0'; + SIGNAL nl0i00iiO : STD_LOGIC := '0'; + SIGNAL nl0i0100i : STD_LOGIC := '0'; + SIGNAL nl0i0100l : STD_LOGIC := '0'; + SIGNAL nl0i0100O : STD_LOGIC := '0'; + SIGNAL nl0i0101i : STD_LOGIC := '0'; + SIGNAL nl0i0101l : STD_LOGIC := '0'; + SIGNAL nl0i0101O : STD_LOGIC := '0'; + SIGNAL nl0i010ii : STD_LOGIC := '0'; + SIGNAL nl0i010il : STD_LOGIC := '0'; + SIGNAL nl0i010iO : STD_LOGIC := '0'; + SIGNAL nl0i010li : STD_LOGIC := '0'; + SIGNAL nl0i010ll : STD_LOGIC := '0'; + SIGNAL nl0i010lO : STD_LOGIC := '0'; + SIGNAL nl0i010Oi : STD_LOGIC := '0'; + SIGNAL nl0i010Ol : STD_LOGIC := '0'; + SIGNAL nl0i010OO : STD_LOGIC := '0'; + SIGNAL nl0i0110i : STD_LOGIC := '0'; + SIGNAL nl0i0110l : STD_LOGIC := '0'; + SIGNAL nl0i0110O : STD_LOGIC := '0'; + SIGNAL nl0i0111i : STD_LOGIC := '0'; + SIGNAL nl0i0111l : STD_LOGIC := '0'; + SIGNAL nl0i0111O : STD_LOGIC := '0'; + SIGNAL nl0i011ii : STD_LOGIC := '0'; + SIGNAL nl0i011il : STD_LOGIC := '0'; + SIGNAL nl0i011iO : STD_LOGIC := '0'; + SIGNAL nl0i011li : STD_LOGIC := '0'; + SIGNAL nl0i011ll : STD_LOGIC := '0'; + SIGNAL nl0i011lO : STD_LOGIC := '0'; + SIGNAL nl0i011Oi : STD_LOGIC := '0'; + SIGNAL nl0i011Ol : STD_LOGIC := '0'; + SIGNAL nl0i011OO : STD_LOGIC := '0'; + SIGNAL nl0i01i0i : STD_LOGIC := '0'; + SIGNAL nl0i01i0l : STD_LOGIC := '0'; + SIGNAL nl0i01i0O : STD_LOGIC := '0'; + SIGNAL nl0i01i1i : STD_LOGIC := '0'; + SIGNAL nl0i01i1l : STD_LOGIC := '0'; + SIGNAL nl0i01i1O : STD_LOGIC := '0'; + SIGNAL nl0i01iii : STD_LOGIC := '0'; + SIGNAL nl0i01iil : STD_LOGIC := '0'; + SIGNAL nl0i01iiO : STD_LOGIC := '0'; + SIGNAL nl0i01ili : STD_LOGIC := '0'; + SIGNAL nl0i01ill : STD_LOGIC := '0'; + SIGNAL nl0i01ilO : STD_LOGIC := '0'; + SIGNAL nl0i01iOi : STD_LOGIC := '0'; + SIGNAL nl0i01iOl : STD_LOGIC := '0'; + SIGNAL nl0i01iOO : STD_LOGIC := '0'; + SIGNAL nl0i01l0i : STD_LOGIC := '0'; + SIGNAL nl0i01l0l : STD_LOGIC := '0'; + SIGNAL nl0i01l0O : STD_LOGIC := '0'; + SIGNAL nl0i01l1i : STD_LOGIC := '0'; + SIGNAL nl0i01l1l : STD_LOGIC := '0'; + SIGNAL nl0i01l1O : STD_LOGIC := '0'; + SIGNAL nl0i01lii : STD_LOGIC := '0'; + SIGNAL nl0i01lil : STD_LOGIC := '0'; + SIGNAL nl0i01liO : STD_LOGIC := '0'; + SIGNAL nl0i01lli : STD_LOGIC := '0'; + SIGNAL nl0i01lll : STD_LOGIC := '0'; + SIGNAL nl0i01llO : STD_LOGIC := '0'; + SIGNAL nl0i01lOi : STD_LOGIC := '0'; + SIGNAL nl0i01lOl : STD_LOGIC := '0'; + SIGNAL nl0i01lOO : STD_LOGIC := '0'; + SIGNAL nl0i01O0i : STD_LOGIC := '0'; + SIGNAL nl0i01O0l : STD_LOGIC := '0'; + SIGNAL nl0i01O0O : STD_LOGIC := '0'; + SIGNAL nl0i01O1i : STD_LOGIC := '0'; + SIGNAL nl0i01O1l : STD_LOGIC := '0'; + SIGNAL nl0i01O1O : STD_LOGIC := '0'; + SIGNAL nl0i01Oii : STD_LOGIC := '0'; + SIGNAL nl0i01Oil : STD_LOGIC := '0'; + SIGNAL nl0i01OiO : STD_LOGIC := '0'; + SIGNAL nl0i01Oli : STD_LOGIC := '0'; + SIGNAL nl0i01Oll : STD_LOGIC := '0'; + SIGNAL nl0i01OlO : STD_LOGIC := '0'; + SIGNAL nl0i01OOi : STD_LOGIC := '0'; + SIGNAL nl0i01OOl : STD_LOGIC := '0'; + SIGNAL nl0i01OOO : STD_LOGIC := '0'; + SIGNAL nl0i1li0i : STD_LOGIC := '0'; + SIGNAL nl0i1li0l : STD_LOGIC := '0'; + SIGNAL nl0i1li0O : STD_LOGIC := '0'; + SIGNAL nl0i1li1O : STD_LOGIC := '0'; + SIGNAL nl0i1liii : STD_LOGIC := '0'; + SIGNAL nl0i1liil : STD_LOGIC := '0'; + SIGNAL nl0i1liiO : STD_LOGIC := '0'; + SIGNAL nl0i1lOOi : STD_LOGIC := '0'; + SIGNAL nl0i1lOOl : STD_LOGIC := '0'; + SIGNAL nl0i1lOOO : STD_LOGIC := '0'; + SIGNAL nl0i1O11i : STD_LOGIC := '0'; + SIGNAL nl0i1O1ii : STD_LOGIC := '0'; + SIGNAL nl0i1O1il : STD_LOGIC := '0'; + SIGNAL nl0i1O1iO : STD_LOGIC := '0'; + SIGNAL nl0i1O1li : STD_LOGIC := '0'; + SIGNAL nl0i1OiOi : STD_LOGIC := '0'; + SIGNAL nl0i1OiOl : STD_LOGIC := '0'; + SIGNAL nl0i1OiOO : STD_LOGIC := '0'; + SIGNAL nl0i1Ol0i : STD_LOGIC := '0'; + SIGNAL nl0i1Ol0l : STD_LOGIC := '0'; + SIGNAL nl0i1Ol0O : STD_LOGIC := '0'; + SIGNAL nl0i1Ol1i : STD_LOGIC := '0'; + SIGNAL nl0i1Ol1l : STD_LOGIC := '0'; + SIGNAL nl0i1Ol1O : STD_LOGIC := '0'; + SIGNAL nl0i1Olii : STD_LOGIC := '0'; + SIGNAL nl0i1Olil : STD_LOGIC := '0'; + SIGNAL nl0i1OliO : STD_LOGIC := '0'; + SIGNAL nl0i1Olli : STD_LOGIC := '0'; + SIGNAL nl0i1Olll : STD_LOGIC := '0'; + SIGNAL nl0i1OllO : STD_LOGIC := '0'; + SIGNAL nl0i1OlOi : STD_LOGIC := '0'; + SIGNAL nl0i1OlOl : STD_LOGIC := '0'; + SIGNAL nl0i1OlOO : STD_LOGIC := '0'; + SIGNAL nl0i1OO0i : STD_LOGIC := '0'; + SIGNAL nl0i1OO0l : STD_LOGIC := '0'; + SIGNAL nl0i1OO0O : STD_LOGIC := '0'; + SIGNAL nl0i1OO1i : STD_LOGIC := '0'; + SIGNAL nl0i1OO1l : STD_LOGIC := '0'; + SIGNAL nl0i1OO1O : STD_LOGIC := '0'; + SIGNAL nl0i1OOii : STD_LOGIC := '0'; + SIGNAL nl0i1OOil : STD_LOGIC := '0'; + SIGNAL nl0i1OOiO : STD_LOGIC := '0'; + SIGNAL nl0i1OOli : STD_LOGIC := '0'; + SIGNAL nl0i1OOll : STD_LOGIC := '0'; + SIGNAL nl0i1OOlO : STD_LOGIC := '0'; + SIGNAL nl0i1OOOi : STD_LOGIC := '0'; + SIGNAL nl0i1OOOl : STD_LOGIC := '0'; + SIGNAL nl0i1OOOO : STD_LOGIC := '0'; + SIGNAL nl0ili1ll : STD_LOGIC := '0'; + SIGNAL nl0illl0i : STD_LOGIC := '0'; + SIGNAL nl0illl0l : STD_LOGIC := '0'; + SIGNAL nl0illl0O : STD_LOGIC := '0'; + SIGNAL nl0illlii : STD_LOGIC := '0'; + SIGNAL nl0illlil : STD_LOGIC := '0'; + SIGNAL nl0illliO : STD_LOGIC := '0'; + SIGNAL nl0illlli : STD_LOGIC := '0'; + SIGNAL nl0illlll : STD_LOGIC := '0'; + SIGNAL nl0illllO : STD_LOGIC := '0'; + SIGNAL nl0ilOiOi : STD_LOGIC := '0'; + SIGNAL nl0ilOiOl : STD_LOGIC := '0'; + SIGNAL nl0ilOiOO : STD_LOGIC := '0'; + SIGNAL nl0ilOl0i : STD_LOGIC := '0'; + SIGNAL nl0ilOl0l : STD_LOGIC := '0'; + SIGNAL nl0ilOl0O : STD_LOGIC := '0'; + SIGNAL nl0ilOl1i : STD_LOGIC := '0'; + SIGNAL nl0ilOl1l : STD_LOGIC := '0'; + SIGNAL nl0ilOl1O : STD_LOGIC := '0'; + SIGNAL nl0ilOlii : STD_LOGIC := '0'; + SIGNAL nl0ilOlil : STD_LOGIC := '0'; + SIGNAL nl0ilOliO : STD_LOGIC := '0'; + SIGNAL nl0ilOlli : STD_LOGIC := '0'; + SIGNAL nl0ilOlll : STD_LOGIC := '0'; + SIGNAL nl0iOi10i : STD_LOGIC := '0'; + SIGNAL nl0iOiili : STD_LOGIC := '0'; + SIGNAL nl0iOiill : STD_LOGIC := '0'; + SIGNAL nl0iOiilO : STD_LOGIC := '0'; + SIGNAL nl0iOiiOi : STD_LOGIC := '0'; + SIGNAL nl0iOiiOl : STD_LOGIC := '0'; + SIGNAL nl0iOiiOO : STD_LOGIC := '0'; + SIGNAL nl0iOil0i : STD_LOGIC := '0'; + SIGNAL nl0iOil0l : STD_LOGIC := '0'; + SIGNAL nl0iOil0O : STD_LOGIC := '0'; + SIGNAL nl0iOil1i : STD_LOGIC := '0'; + SIGNAL nl0iOil1l : STD_LOGIC := '0'; + SIGNAL nl0iOil1O : STD_LOGIC := '0'; + SIGNAL nl0iOilii : STD_LOGIC := '0'; + SIGNAL nl0iOilil : STD_LOGIC := '0'; + SIGNAL nl0iOiliO : STD_LOGIC := '0'; + SIGNAL nl0iOilli : STD_LOGIC := '0'; + SIGNAL nl0iOilll : STD_LOGIC := '0'; + SIGNAL nl0iOillO : STD_LOGIC := '0'; + SIGNAL nl0iOilOi : STD_LOGIC := '0'; + SIGNAL nl0iOilOl : STD_LOGIC := '0'; + SIGNAL nl0iOilOO : STD_LOGIC := '0'; + SIGNAL nl0iOiO0i : STD_LOGIC := '0'; + SIGNAL nl0iOiO0l : STD_LOGIC := '0'; + SIGNAL nl0iOiO0O : STD_LOGIC := '0'; + SIGNAL nl0iOiO1i : STD_LOGIC := '0'; + SIGNAL nl0iOiO1l : STD_LOGIC := '0'; + SIGNAL nl0iOiO1O : STD_LOGIC := '0'; + SIGNAL nl0iOiOii : STD_LOGIC := '0'; + SIGNAL nl0iOiOil : STD_LOGIC := '0'; + SIGNAL nl0iOiOiO : STD_LOGIC := '0'; + SIGNAL nl0iOiOli : STD_LOGIC := '0'; + SIGNAL nl0iOiOll : STD_LOGIC := '0'; + SIGNAL nl0iOiOlO : STD_LOGIC := '0'; + SIGNAL nl0iOiOOi : STD_LOGIC := '0'; + SIGNAL nl0iOiOOl : STD_LOGIC := '0'; + SIGNAL nl0iOiOOO : STD_LOGIC := '0'; + SIGNAL nl0iOl10i : STD_LOGIC := '0'; + SIGNAL nl0iOl11i : STD_LOGIC := '0'; + SIGNAL nl0iOl11l : STD_LOGIC := '0'; + SIGNAL nl0iOl11O : STD_LOGIC := '0'; + SIGNAL nl0iOOO0i : STD_LOGIC := '0'; + SIGNAL nl0iOOO0l : STD_LOGIC := '0'; + SIGNAL nl0iOOO0O : STD_LOGIC := '0'; + SIGNAL nl0iOOO1l : STD_LOGIC := '0'; + SIGNAL nl0iOOO1O : STD_LOGIC := '0'; + SIGNAL nl0iOOOii : STD_LOGIC := '0'; + SIGNAL nl0iOOOil : STD_LOGIC := '0'; + SIGNAL nl0iOOOiO : STD_LOGIC := '0'; + SIGNAL nl0iOOOli : STD_LOGIC := '0'; + SIGNAL nl0iOOOll : STD_LOGIC := '0'; + SIGNAL nl0iOOOlO : STD_LOGIC := '0'; + SIGNAL nl0iOOOOi : STD_LOGIC := '0'; + SIGNAL nl0iOOOOl : STD_LOGIC := '0'; + SIGNAL nl0iOOOOO : STD_LOGIC := '0'; + SIGNAL nl0l000ll : STD_LOGIC := '0'; + SIGNAL nl0l001iO : STD_LOGIC := '0'; + SIGNAL nl0l001li : STD_LOGIC := '0'; + SIGNAL nl0l001ll : STD_LOGIC := '0'; + SIGNAL nl0l001lO : STD_LOGIC := '0'; + SIGNAL nl0l001Oi : STD_LOGIC := '0'; + SIGNAL nl0l001Ol : STD_LOGIC := '0'; + SIGNAL nl0l00iOl : STD_LOGIC := '0'; + SIGNAL nl0l00iOO : STD_LOGIC := '0'; + SIGNAL nl0l00l1i : STD_LOGIC := '0'; + SIGNAL nl0l00l1l : STD_LOGIC := '0'; + SIGNAL nl0l00l1O : STD_LOGIC := '0'; + SIGNAL nl0l0100i : STD_LOGIC := '0'; + SIGNAL nl0l0100l : STD_LOGIC := '0'; + SIGNAL nl0l0100O : STD_LOGIC := '0'; + SIGNAL nl0l0101l : STD_LOGIC := '0'; + SIGNAL nl0l0101O : STD_LOGIC := '0'; + SIGNAL nl0l010ii : STD_LOGIC := '0'; + SIGNAL nl0l010il : STD_LOGIC := '0'; + SIGNAL nl0l010iO : STD_LOGIC := '0'; + SIGNAL nl0l010li : STD_LOGIC := '0'; + SIGNAL nl0l010ll : STD_LOGIC := '0'; + SIGNAL nl0l010lO : STD_LOGIC := '0'; + SIGNAL nl0l010Oi : STD_LOGIC := '0'; + SIGNAL nl0l010Ol : STD_LOGIC := '0'; + SIGNAL nl0l010OO : STD_LOGIC := '0'; + SIGNAL nl0l01O1l : STD_LOGIC := '0'; + SIGNAL nl0l01O1O : STD_LOGIC := '0'; + SIGNAL nl0l0i00i : STD_LOGIC := '0'; + SIGNAL nl0l0i00l : STD_LOGIC := '0'; + SIGNAL nl0l0i00O : STD_LOGIC := '0'; + SIGNAL nl0l0i01i : STD_LOGIC := '0'; + SIGNAL nl0l0i01l : STD_LOGIC := '0'; + SIGNAL nl0l0i01O : STD_LOGIC := '0'; + SIGNAL nl0l0i0ii : STD_LOGIC := '0'; + SIGNAL nl0l0i0il : STD_LOGIC := '0'; + SIGNAL nl0l0i0iO : STD_LOGIC := '0'; + SIGNAL nl0l0i0li : STD_LOGIC := '0'; + SIGNAL nl0l0i0ll : STD_LOGIC := '0'; + SIGNAL nl0l0i1ii : STD_LOGIC := '0'; + SIGNAL nl0l0i1Oi : STD_LOGIC := '0'; + SIGNAL nl0l0i1Ol : STD_LOGIC := '0'; + SIGNAL nl0l0i1OO : STD_LOGIC := '0'; + SIGNAL nl0l0liiO : STD_LOGIC := '0'; + SIGNAL nl0l0lili : STD_LOGIC := '0'; + SIGNAL nl0l0lill : STD_LOGIC := '0'; + SIGNAL nl0l0lilO : STD_LOGIC := '0'; + SIGNAL nl0l0liOi : STD_LOGIC := '0'; + SIGNAL nl0l0liOl : STD_LOGIC := '0'; + SIGNAL nl0l0liOO : STD_LOGIC := '0'; + SIGNAL nl0l0ll0i : STD_LOGIC := '0'; + SIGNAL nl0l0ll0l : STD_LOGIC := '0'; + SIGNAL nl0l0ll0O : STD_LOGIC := '0'; + SIGNAL nl0l0ll1i : STD_LOGIC := '0'; + SIGNAL nl0l0ll1l : STD_LOGIC := '0'; + SIGNAL nl0l0ll1O : STD_LOGIC := '0'; + SIGNAL nl0l0llii : STD_LOGIC := '0'; + SIGNAL nl0l0llil : STD_LOGIC := '0'; + SIGNAL nl0l0lliO : STD_LOGIC := '0'; + SIGNAL nl0l0llli : STD_LOGIC := '0'; + SIGNAL nl0l0llll : STD_LOGIC := '0'; + SIGNAL nl0l0lllO : STD_LOGIC := '0'; + SIGNAL nl0l0llOi : STD_LOGIC := '0'; + SIGNAL nl0l0llOl : STD_LOGIC := '0'; + SIGNAL nl0l0llOO : STD_LOGIC := '0'; + SIGNAL nl0l0lO0i : STD_LOGIC := '0'; + SIGNAL nl0l0lO0l : STD_LOGIC := '0'; + SIGNAL nl0l0lO0O : STD_LOGIC := '0'; + SIGNAL nl0l0lO1i : STD_LOGIC := '0'; + SIGNAL nl0l0lO1l : STD_LOGIC := '0'; + SIGNAL nl0l0lO1O : STD_LOGIC := '0'; + SIGNAL nl0l0lOii : STD_LOGIC := '0'; + SIGNAL nl0l0lOil : STD_LOGIC := '0'; + SIGNAL nl0l0lOiO : STD_LOGIC := '0'; + SIGNAL nl0l0lOli : STD_LOGIC := '0'; + SIGNAL nl0l0lOll : STD_LOGIC := '0'; + SIGNAL nl0l0lOlO : STD_LOGIC := '0'; + SIGNAL nl0l0lOOi : STD_LOGIC := '0'; + SIGNAL nl0l0lOOl : STD_LOGIC := '0'; + SIGNAL nl0l0lOOO : STD_LOGIC := '0'; + SIGNAL nl0l0O00i : STD_LOGIC := '0'; + SIGNAL nl0l0O00l : STD_LOGIC := '0'; + SIGNAL nl0l0O00O : STD_LOGIC := '0'; + SIGNAL nl0l0O01i : STD_LOGIC := '0'; + SIGNAL nl0l0O01l : STD_LOGIC := '0'; + SIGNAL nl0l0O01O : STD_LOGIC := '0'; + SIGNAL nl0l0O0ii : STD_LOGIC := '0'; + SIGNAL nl0l0O0il : STD_LOGIC := '0'; + SIGNAL nl0l0O0iO : STD_LOGIC := '0'; + SIGNAL nl0l0O0li : STD_LOGIC := '0'; + SIGNAL nl0l0O0ll : STD_LOGIC := '0'; + SIGNAL nl0l0O0lO : STD_LOGIC := '0'; + SIGNAL nl0l0O0Oi : STD_LOGIC := '0'; + SIGNAL nl0l0O0Ol : STD_LOGIC := '0'; + SIGNAL nl0l0O0OO : STD_LOGIC := '0'; + SIGNAL nl0l0O10i : STD_LOGIC := '0'; + SIGNAL nl0l0O10l : STD_LOGIC := '0'; + SIGNAL nl0l0O10O : STD_LOGIC := '0'; + SIGNAL nl0l0O11i : STD_LOGIC := '0'; + SIGNAL nl0l0O11l : STD_LOGIC := '0'; + SIGNAL nl0l0O11O : STD_LOGIC := '0'; + SIGNAL nl0l0O1ii : STD_LOGIC := '0'; + SIGNAL nl0l0O1il : STD_LOGIC := '0'; + SIGNAL nl0l0O1iO : STD_LOGIC := '0'; + SIGNAL nl0l0O1li : STD_LOGIC := '0'; + SIGNAL nl0l0O1ll : STD_LOGIC := '0'; + SIGNAL nl0l0O1lO : STD_LOGIC := '0'; + SIGNAL nl0l0O1Oi : STD_LOGIC := '0'; + SIGNAL nl0l0O1Ol : STD_LOGIC := '0'; + SIGNAL nl0l0O1OO : STD_LOGIC := '0'; + SIGNAL nl0l0Oi0i : STD_LOGIC := '0'; + SIGNAL nl0l0Oi0l : STD_LOGIC := '0'; + SIGNAL nl0l0Oi0O : STD_LOGIC := '0'; + SIGNAL nl0l0Oi1i : STD_LOGIC := '0'; + SIGNAL nl0l0Oi1l : STD_LOGIC := '0'; + SIGNAL nl0l0Oi1O : STD_LOGIC := '0'; + SIGNAL nl0l0Oiii : STD_LOGIC := '0'; + SIGNAL nl0l0Oiil : STD_LOGIC := '0'; + SIGNAL nl0l0OiiO : STD_LOGIC := '0'; + SIGNAL nl0l0Oili : STD_LOGIC := '0'; + SIGNAL nl0l0Oill : STD_LOGIC := '0'; + SIGNAL nl0l0OilO : STD_LOGIC := '0'; + SIGNAL nl0l0OiOi : STD_LOGIC := '0'; + SIGNAL nl0l0OiOl : STD_LOGIC := '0'; + SIGNAL nl0l0OiOO : STD_LOGIC := '0'; + SIGNAL nl0l1010i : STD_LOGIC := '0'; + SIGNAL nl0l1010l : STD_LOGIC := '0'; + SIGNAL nl0l1010O : STD_LOGIC := '0'; + SIGNAL nl0l1011i : STD_LOGIC := '0'; + SIGNAL nl0l1011l : STD_LOGIC := '0'; + SIGNAL nl0l1011O : STD_LOGIC := '0'; + SIGNAL nl0l101ii : STD_LOGIC := '0'; + SIGNAL nl0l101il : STD_LOGIC := '0'; + SIGNAL nl0l1100i : STD_LOGIC := '0'; + SIGNAL nl0l1100l : STD_LOGIC := '0'; + SIGNAL nl0l1100O : STD_LOGIC := '0'; + SIGNAL nl0l1101i : STD_LOGIC := '0'; + SIGNAL nl0l1101l : STD_LOGIC := '0'; + SIGNAL nl0l1101O : STD_LOGIC := '0'; + SIGNAL nl0l110ii : STD_LOGIC := '0'; + SIGNAL nl0l110il : STD_LOGIC := '0'; + SIGNAL nl0l110iO : STD_LOGIC := '0'; + SIGNAL nl0l110li : STD_LOGIC := '0'; + SIGNAL nl0l110ll : STD_LOGIC := '0'; + SIGNAL nl0l110lO : STD_LOGIC := '0'; + SIGNAL nl0l110Oi : STD_LOGIC := '0'; + SIGNAL nl0l110Ol : STD_LOGIC := '0'; + SIGNAL nl0l110OO : STD_LOGIC := '0'; + SIGNAL nl0l1110i : STD_LOGIC := '0'; + SIGNAL nl0l1110l : STD_LOGIC := '0'; + SIGNAL nl0l1110O : STD_LOGIC := '0'; + SIGNAL nl0l1111i : STD_LOGIC := '0'; + SIGNAL nl0l1111l : STD_LOGIC := '0'; + SIGNAL nl0l1111O : STD_LOGIC := '0'; + SIGNAL nl0l111ii : STD_LOGIC := '0'; + SIGNAL nl0l111il : STD_LOGIC := '0'; + SIGNAL nl0l111iO : STD_LOGIC := '0'; + SIGNAL nl0l111li : STD_LOGIC := '0'; + SIGNAL nl0l111ll : STD_LOGIC := '0'; + SIGNAL nl0l111lO : STD_LOGIC := '0'; + SIGNAL nl0l111Oi : STD_LOGIC := '0'; + SIGNAL nl0l111Ol : STD_LOGIC := '0'; + SIGNAL nl0l111OO : STD_LOGIC := '0'; + SIGNAL nl0l11i0i : STD_LOGIC := '0'; + SIGNAL nl0l11i0l : STD_LOGIC := '0'; + SIGNAL nl0l11i0O : STD_LOGIC := '0'; + SIGNAL nl0l11i1i : STD_LOGIC := '0'; + SIGNAL nl0l11i1l : STD_LOGIC := '0'; + SIGNAL nl0l11i1O : STD_LOGIC := '0'; + SIGNAL nl0l11iii : STD_LOGIC := '0'; + SIGNAL nl0l11iil : STD_LOGIC := '0'; + SIGNAL nl0l11iiO : STD_LOGIC := '0'; + SIGNAL nl0l11ili : STD_LOGIC := '0'; + SIGNAL nl0l11ill : STD_LOGIC := '0'; + SIGNAL nl0l11ilO : STD_LOGIC := '0'; + SIGNAL nl0l11iOi : STD_LOGIC := '0'; + SIGNAL nl0l11iOl : STD_LOGIC := '0'; + SIGNAL nl0l11iOO : STD_LOGIC := '0'; + SIGNAL nl0l11l0i : STD_LOGIC := '0'; + SIGNAL nl0l11l0l : STD_LOGIC := '0'; + SIGNAL nl0l11l0O : STD_LOGIC := '0'; + SIGNAL nl0l11l1i : STD_LOGIC := '0'; + SIGNAL nl0l11l1l : STD_LOGIC := '0'; + SIGNAL nl0l11l1O : STD_LOGIC := '0'; + SIGNAL nl0l11lii : STD_LOGIC := '0'; + SIGNAL nl0l11lil : STD_LOGIC := '0'; + SIGNAL nl0l11liO : STD_LOGIC := '0'; + SIGNAL nl0l11lli : STD_LOGIC := '0'; + SIGNAL nl0l11lll : STD_LOGIC := '0'; + SIGNAL nl0l11llO : STD_LOGIC := '0'; + SIGNAL nl0l11lOi : STD_LOGIC := '0'; + SIGNAL nl0l11lOl : STD_LOGIC := '0'; + SIGNAL nl0l11lOO : STD_LOGIC := '0'; + SIGNAL nl0l11O0i : STD_LOGIC := '0'; + SIGNAL nl0l11O0l : STD_LOGIC := '0'; + SIGNAL nl0l11O0O : STD_LOGIC := '0'; + SIGNAL nl0l11O1i : STD_LOGIC := '0'; + SIGNAL nl0l11O1l : STD_LOGIC := '0'; + SIGNAL nl0l11O1O : STD_LOGIC := '0'; + SIGNAL nl0l11Oii : STD_LOGIC := '0'; + SIGNAL nl0l11Oil : STD_LOGIC := '0'; + SIGNAL nl0l11OiO : STD_LOGIC := '0'; + SIGNAL nl0l11Oli : STD_LOGIC := '0'; + SIGNAL nl0l11Oll : STD_LOGIC := '0'; + SIGNAL nl0l11OlO : STD_LOGIC := '0'; + SIGNAL nl0l11OOi : STD_LOGIC := '0'; + SIGNAL nl0l11OOl : STD_LOGIC := '0'; + SIGNAL nl0l11OOO : STD_LOGIC := '0'; + SIGNAL nl0lil00i : STD_LOGIC := '0'; + SIGNAL nl0lil00l : STD_LOGIC := '0'; + SIGNAL nl0lil00O : STD_LOGIC := '0'; + SIGNAL nl0lil0ii : STD_LOGIC := '0'; + SIGNAL nl0lil0il : STD_LOGIC := '0'; + SIGNAL nl0lil0iO : STD_LOGIC := '0'; + SIGNAL nl0lil0li : STD_LOGIC := '0'; + SIGNAL nl0lil0ll : STD_LOGIC := '0'; + SIGNAL nl0lil11i : STD_LOGIC := '0'; + SIGNAL nl0lil11l : STD_LOGIC := '0'; + SIGNAL nl0liliOO : STD_LOGIC := '0'; + SIGNAL nl0lill0i : STD_LOGIC := '0'; + SIGNAL nl0lill0l : STD_LOGIC := '0'; + SIGNAL nl0lill0O : STD_LOGIC := '0'; + SIGNAL nl0lill1i : STD_LOGIC := '0'; + SIGNAL nl0lill1l : STD_LOGIC := '0'; + SIGNAL nl0lill1O : STD_LOGIC := '0'; + SIGNAL nl0ll1O1l : STD_LOGIC := '0'; + SIGNAL nl0lliiiO : STD_LOGIC := '0'; + SIGNAL nl0llli0i : STD_LOGIC := '0'; + SIGNAL nl0llli0l : STD_LOGIC := '0'; + SIGNAL nl0llli0O : STD_LOGIC := '0'; + SIGNAL nl0llli1i : STD_LOGIC := '0'; + SIGNAL nl0llli1l : STD_LOGIC := '0'; + SIGNAL nl0llli1O : STD_LOGIC := '0'; + SIGNAL nl0llliii : STD_LOGIC := '0'; + SIGNAL nl0llliil : STD_LOGIC := '0'; + SIGNAL nl0llliiO : STD_LOGIC := '0'; + SIGNAL nl0lllili : STD_LOGIC := '0'; + SIGNAL nl0lllill : STD_LOGIC := '0'; + SIGNAL nl0lllilO : STD_LOGIC := '0'; + SIGNAL nl0llliOi : STD_LOGIC := '0'; + SIGNAL nl0llliOl : STD_LOGIC := '0'; + SIGNAL nl0llliOO : STD_LOGIC := '0'; + SIGNAL nl0llll0i : STD_LOGIC := '0'; + SIGNAL nl0llll0l : STD_LOGIC := '0'; + SIGNAL nl0llll0O : STD_LOGIC := '0'; + SIGNAL nl0llll1i : STD_LOGIC := '0'; + SIGNAL nl0llll1l : STD_LOGIC := '0'; + SIGNAL nl0llll1O : STD_LOGIC := '0'; + SIGNAL nl0llllii : STD_LOGIC := '0'; + SIGNAL nl0llllil : STD_LOGIC := '0'; + SIGNAL nl0lllliO : STD_LOGIC := '0'; + SIGNAL nl0llllli : STD_LOGIC := '0'; + SIGNAL nl0llllll : STD_LOGIC := '0'; + SIGNAL nl0lllllO : STD_LOGIC := '0'; + SIGNAL nl0llllOi : STD_LOGIC := '0'; + SIGNAL nl0llllOl : STD_LOGIC := '0'; + SIGNAL nl0llllOO : STD_LOGIC := '0'; + SIGNAL nl0lllO0i : STD_LOGIC := '0'; + SIGNAL nl0lllO0l : STD_LOGIC := '0'; + SIGNAL nl0lllO0O : STD_LOGIC := '0'; + SIGNAL nl0lllO1i : STD_LOGIC := '0'; + SIGNAL nl0lllO1l : STD_LOGIC := '0'; + SIGNAL nl0lllO1O : STD_LOGIC := '0'; + SIGNAL nl0lllOii : STD_LOGIC := '0'; + SIGNAL nl0lllOil : STD_LOGIC := '0'; + SIGNAL nl0lllOiO : STD_LOGIC := '0'; + SIGNAL nl0lllOli : STD_LOGIC := '0'; + SIGNAL nl0lllOll : STD_LOGIC := '0'; + SIGNAL nl0lllOlO : STD_LOGIC := '0'; + SIGNAL nl0lllOOi : STD_LOGIC := '0'; + SIGNAL nl0lllOOl : STD_LOGIC := '0'; + SIGNAL nl0lllOOO : STD_LOGIC := '0'; + SIGNAL nl0llO10i : STD_LOGIC := '0'; + SIGNAL nl0llO10l : STD_LOGIC := '0'; + SIGNAL nl0llO10O : STD_LOGIC := '0'; + SIGNAL nl0llO11i : STD_LOGIC := '0'; + SIGNAL nl0llO11l : STD_LOGIC := '0'; + SIGNAL nl0llO11O : STD_LOGIC := '0'; + SIGNAL nl0llO1ii : STD_LOGIC := '0'; + SIGNAL nl0llO1il : STD_LOGIC := '0'; + SIGNAL nl0llO1iO : STD_LOGIC := '0'; + SIGNAL nl0llO1li : STD_LOGIC := '0'; + SIGNAL nl0llO1ll : STD_LOGIC := '0'; + SIGNAL nl0llO1lO : STD_LOGIC := '0'; + SIGNAL nl0llO1Oi : STD_LOGIC := '0'; + SIGNAL nl0llO1Ol : STD_LOGIC := '0'; + SIGNAL nl0lOlill : STD_LOGIC := '0'; + SIGNAL nl0O0i10O : STD_LOGIC := '0'; + SIGNAL nl0O0llOi : STD_LOGIC := '0'; + SIGNAL nl0O10Oll : STD_LOGIC := '0'; + SIGNAL nl0O10OlO : STD_LOGIC := '0'; + SIGNAL nl0O10OOi : STD_LOGIC := '0'; + SIGNAL nl0O10OOl : STD_LOGIC := '0'; + SIGNAL nl0O10OOO : STD_LOGIC := '0'; + SIGNAL nl0O1101O : STD_LOGIC := '0'; + SIGNAL nl0O1i00i : STD_LOGIC := '0'; + SIGNAL nl0O1i00l : STD_LOGIC := '0'; + SIGNAL nl0O1i00O : STD_LOGIC := '0'; + SIGNAL nl0O1i01i : STD_LOGIC := '0'; + SIGNAL nl0O1i01l : STD_LOGIC := '0'; + SIGNAL nl0O1i01O : STD_LOGIC := '0'; + SIGNAL nl0O1i0ii : STD_LOGIC := '0'; + SIGNAL nl0O1i0il : STD_LOGIC := '0'; + SIGNAL nl0O1i0iO : STD_LOGIC := '0'; + SIGNAL nl0O1i0li : STD_LOGIC := '0'; + SIGNAL nl0O1i0ll : STD_LOGIC := '0'; + SIGNAL nl0O1i0lO : STD_LOGIC := '0'; + SIGNAL nl0O1i0Oi : STD_LOGIC := '0'; + SIGNAL nl0O1i0Ol : STD_LOGIC := '0'; + SIGNAL nl0O1i0OO : STD_LOGIC := '0'; + SIGNAL nl0O1i10i : STD_LOGIC := '0'; + SIGNAL nl0O1i10l : STD_LOGIC := '0'; + SIGNAL nl0O1i10O : STD_LOGIC := '0'; + SIGNAL nl0O1i11i : STD_LOGIC := '0'; + SIGNAL nl0O1i11l : STD_LOGIC := '0'; + SIGNAL nl0O1i11O : STD_LOGIC := '0'; + SIGNAL nl0O1i1ii : STD_LOGIC := '0'; + SIGNAL nl0O1i1il : STD_LOGIC := '0'; + SIGNAL nl0O1i1iO : STD_LOGIC := '0'; + SIGNAL nl0O1i1li : STD_LOGIC := '0'; + SIGNAL nl0O1i1ll : STD_LOGIC := '0'; + SIGNAL nl0O1i1lO : STD_LOGIC := '0'; + SIGNAL nl0O1i1Oi : STD_LOGIC := '0'; + SIGNAL nl0O1i1Ol : STD_LOGIC := '0'; + SIGNAL nl0O1i1OO : STD_LOGIC := '0'; + SIGNAL nl0O1ii0i : STD_LOGIC := '0'; + SIGNAL nl0O1ii0l : STD_LOGIC := '0'; + SIGNAL nl0O1ii0O : STD_LOGIC := '0'; + SIGNAL nl0O1ii1i : STD_LOGIC := '0'; + SIGNAL nl0O1ii1l : STD_LOGIC := '0'; + SIGNAL nl0O1ii1O : STD_LOGIC := '0'; + SIGNAL nl0O1iiii : STD_LOGIC := '0'; + SIGNAL nl0O1iiil : STD_LOGIC := '0'; + SIGNAL nl0O1iiiO : STD_LOGIC := '0'; + SIGNAL nl0O1iili : STD_LOGIC := '0'; + SIGNAL nl0O1iill : STD_LOGIC := '0'; + SIGNAL nl0O1iilO : STD_LOGIC := '0'; + SIGNAL nl0O1iiOi : STD_LOGIC := '0'; + SIGNAL nl0O1iiOl : STD_LOGIC := '0'; + SIGNAL nl0O1iiOO : STD_LOGIC := '0'; + SIGNAL nl0O1il0i : STD_LOGIC := '0'; + SIGNAL nl0O1il0l : STD_LOGIC := '0'; + SIGNAL nl0O1il0O : STD_LOGIC := '0'; + SIGNAL nl0O1il1i : STD_LOGIC := '0'; + SIGNAL nl0O1il1l : STD_LOGIC := '0'; + SIGNAL nl0O1il1O : STD_LOGIC := '0'; + SIGNAL nl0O1ilii : STD_LOGIC := '0'; + SIGNAL nl0O1ilil : STD_LOGIC := '0'; + SIGNAL nl0O1iliO : STD_LOGIC := '0'; + SIGNAL nl0Oi000i : STD_LOGIC := '0'; + SIGNAL nl0Oi001i : STD_LOGIC := '0'; + SIGNAL nl0Oi001l : STD_LOGIC := '0'; + SIGNAL nl0Oi001O : STD_LOGIC := '0'; + SIGNAL nl0Oi010i : STD_LOGIC := '0'; + SIGNAL nl0Oi010l : STD_LOGIC := '0'; + SIGNAL nl0Oi010O : STD_LOGIC := '0'; + SIGNAL nl0Oi011i : STD_LOGIC := '0'; + SIGNAL nl0Oi011l : STD_LOGIC := '0'; + SIGNAL nl0Oi011O : STD_LOGIC := '0'; + SIGNAL nl0Oi01ii : STD_LOGIC := '0'; + SIGNAL nl0Oi01il : STD_LOGIC := '0'; + SIGNAL nl0Oi01iO : STD_LOGIC := '0'; + SIGNAL nl0Oi01li : STD_LOGIC := '0'; + SIGNAL nl0Oi01ll : STD_LOGIC := '0'; + SIGNAL nl0Oi01lO : STD_LOGIC := '0'; + SIGNAL nl0Oi01Oi : STD_LOGIC := '0'; + SIGNAL nl0Oi01Ol : STD_LOGIC := '0'; + SIGNAL nl0Oi01OO : STD_LOGIC := '0'; + SIGNAL nl0Oi1i0O : STD_LOGIC := '0'; + SIGNAL nl0Oi1iii : STD_LOGIC := '0'; + SIGNAL nl0Oi1iil : STD_LOGIC := '0'; + SIGNAL nl0Oi1iiO : STD_LOGIC := '0'; + SIGNAL nl0Oi1ili : STD_LOGIC := '0'; + SIGNAL nl0Oi1ill : STD_LOGIC := '0'; + SIGNAL nl0Oi1ilO : STD_LOGIC := '0'; + SIGNAL nl0Oi1iOi : STD_LOGIC := '0'; + SIGNAL nl0Oi1iOl : STD_LOGIC := '0'; + SIGNAL nl0Oi1iOO : STD_LOGIC := '0'; + SIGNAL nl0Oi1l0i : STD_LOGIC := '0'; + SIGNAL nl0Oi1l0l : STD_LOGIC := '0'; + SIGNAL nl0Oi1l0O : STD_LOGIC := '0'; + SIGNAL nl0Oi1l1i : STD_LOGIC := '0'; + SIGNAL nl0Oi1l1l : STD_LOGIC := '0'; + SIGNAL nl0Oi1l1O : STD_LOGIC := '0'; + SIGNAL nl0Oi1lii : STD_LOGIC := '0'; + SIGNAL nl0Oi1lil : STD_LOGIC := '0'; + SIGNAL nl0Oi1liO : STD_LOGIC := '0'; + SIGNAL nl0Oi1lli : STD_LOGIC := '0'; + SIGNAL nl0Oi1lll : STD_LOGIC := '0'; + SIGNAL nl0Oi1llO : STD_LOGIC := '0'; + SIGNAL nl0Oi1lOi : STD_LOGIC := '0'; + SIGNAL nl0Oi1lOl : STD_LOGIC := '0'; + SIGNAL nl0Oi1lOO : STD_LOGIC := '0'; + SIGNAL nl0Oi1O0i : STD_LOGIC := '0'; + SIGNAL nl0Oi1O0l : STD_LOGIC := '0'; + SIGNAL nl0Oi1O0O : STD_LOGIC := '0'; + SIGNAL nl0Oi1O1i : STD_LOGIC := '0'; + SIGNAL nl0Oi1O1l : STD_LOGIC := '0'; + SIGNAL nl0Oi1O1O : STD_LOGIC := '0'; + SIGNAL nl0Oi1Oii : STD_LOGIC := '0'; + SIGNAL nl0Oi1Oil : STD_LOGIC := '0'; + SIGNAL nl0Oi1OiO : STD_LOGIC := '0'; + SIGNAL nl0Oi1Oli : STD_LOGIC := '0'; + SIGNAL nl0Oi1Oll : STD_LOGIC := '0'; + SIGNAL nl0Oi1OlO : STD_LOGIC := '0'; + SIGNAL nl0Oi1OOi : STD_LOGIC := '0'; + SIGNAL nl0Oi1OOl : STD_LOGIC := '0'; + SIGNAL nl0Oi1OOO : STD_LOGIC := '0'; + SIGNAL nl0OiO0li : STD_LOGIC := '0'; + SIGNAL nl0OiO1il : STD_LOGIC := '0'; + SIGNAL nl0OiO1iO : STD_LOGIC := '0'; + SIGNAL nl0OiO1li : STD_LOGIC := '0'; + SIGNAL nl0OiO1ll : STD_LOGIC := '0'; + SIGNAL nl0OiO1lO : STD_LOGIC := '0'; + SIGNAL nl0OiO1Oi : STD_LOGIC := '0'; + SIGNAL nl0OiOl0i : STD_LOGIC := '0'; + SIGNAL nl0OiOl0l : STD_LOGIC := '0'; + SIGNAL nl0OiOl0O : STD_LOGIC := '0'; + SIGNAL nl0OiOlii : STD_LOGIC := '0'; + SIGNAL nl0OiOlil : STD_LOGIC := '0'; + SIGNAL nl0Ol000i : STD_LOGIC := '0'; + SIGNAL nl0Ol000l : STD_LOGIC := '0'; + SIGNAL nl0Ol000O : STD_LOGIC := '0'; + SIGNAL nl0Ol001i : STD_LOGIC := '0'; + SIGNAL nl0Ol001l : STD_LOGIC := '0'; + SIGNAL nl0Ol001O : STD_LOGIC := '0'; + SIGNAL nl0Ol00ii : STD_LOGIC := '0'; + SIGNAL nl0Ol00il : STD_LOGIC := '0'; + SIGNAL nl0Ol00iO : STD_LOGIC := '0'; + SIGNAL nl0Ol00li : STD_LOGIC := '0'; + SIGNAL nl0Ol00ll : STD_LOGIC := '0'; + SIGNAL nl0Ol00lO : STD_LOGIC := '0'; + SIGNAL nl0Ol00Oi : STD_LOGIC := '0'; + SIGNAL nl0Ol00Ol : STD_LOGIC := '0'; + SIGNAL nl0Ol00OO : STD_LOGIC := '0'; + SIGNAL nl0Ol010i : STD_LOGIC := '0'; + SIGNAL nl0Ol010l : STD_LOGIC := '0'; + SIGNAL nl0Ol010O : STD_LOGIC := '0'; + SIGNAL nl0Ol011i : STD_LOGIC := '0'; + SIGNAL nl0Ol011l : STD_LOGIC := '0'; + SIGNAL nl0Ol011O : STD_LOGIC := '0'; + SIGNAL nl0Ol01ii : STD_LOGIC := '0'; + SIGNAL nl0Ol01il : STD_LOGIC := '0'; + SIGNAL nl0Ol01iO : STD_LOGIC := '0'; + SIGNAL nl0Ol01li : STD_LOGIC := '0'; + SIGNAL nl0Ol01ll : STD_LOGIC := '0'; + SIGNAL nl0Ol01lO : STD_LOGIC := '0'; + SIGNAL nl0Ol01Oi : STD_LOGIC := '0'; + SIGNAL nl0Ol01Ol : STD_LOGIC := '0'; + SIGNAL nl0Ol01OO : STD_LOGIC := '0'; + SIGNAL nl0Ol0i0i : STD_LOGIC := '0'; + SIGNAL nl0Ol0i0l : STD_LOGIC := '0'; + SIGNAL nl0Ol0i0O : STD_LOGIC := '0'; + SIGNAL nl0Ol0i1i : STD_LOGIC := '0'; + SIGNAL nl0Ol0i1l : STD_LOGIC := '0'; + SIGNAL nl0Ol0i1O : STD_LOGIC := '0'; + SIGNAL nl0Ol0iii : STD_LOGIC := '0'; + SIGNAL nl0Ol0iil : STD_LOGIC := '0'; + SIGNAL nl0Ol0iiO : STD_LOGIC := '0'; + SIGNAL nl0Ol0ili : STD_LOGIC := '0'; + SIGNAL nl0Ol0ill : STD_LOGIC := '0'; + SIGNAL nl0Ol0ilO : STD_LOGIC := '0'; + SIGNAL nl0Ol0iOi : STD_LOGIC := '0'; + SIGNAL nl0Ol0iOl : STD_LOGIC := '0'; + SIGNAL nl0Ol0iOO : STD_LOGIC := '0'; + SIGNAL nl0Ol0l0i : STD_LOGIC := '0'; + SIGNAL nl0Ol0l0l : STD_LOGIC := '0'; + SIGNAL nl0Ol0l0O : STD_LOGIC := '0'; + SIGNAL nl0Ol0l1i : STD_LOGIC := '0'; + SIGNAL nl0Ol0l1l : STD_LOGIC := '0'; + SIGNAL nl0Ol0l1O : STD_LOGIC := '0'; + SIGNAL nl0Ol0lii : STD_LOGIC := '0'; + SIGNAL nl0Ol0lil : STD_LOGIC := '0'; + SIGNAL nl0Ol0liO : STD_LOGIC := '0'; + SIGNAL nl0Ol0lli : STD_LOGIC := '0'; + SIGNAL nl0Ol0lll : STD_LOGIC := '0'; + SIGNAL nl0Ol0llO : STD_LOGIC := '0'; + SIGNAL nl0Ol0lOi : STD_LOGIC := '0'; + SIGNAL nl0Ol0lOl : STD_LOGIC := '0'; + SIGNAL nl0Ol0lOO : STD_LOGIC := '0'; + SIGNAL nl0Ol0O0i : STD_LOGIC := '0'; + SIGNAL nl0Ol0O0l : STD_LOGIC := '0'; + SIGNAL nl0Ol0O0O : STD_LOGIC := '0'; + SIGNAL nl0Ol0O1i : STD_LOGIC := '0'; + SIGNAL nl0Ol0O1l : STD_LOGIC := '0'; + SIGNAL nl0Ol0O1O : STD_LOGIC := '0'; + SIGNAL nl0Ol0Oii : STD_LOGIC := '0'; + SIGNAL nl0Ol0Oil : STD_LOGIC := '0'; + SIGNAL nl0Ol0OiO : STD_LOGIC := '0'; + SIGNAL nl0Ol0Oli : STD_LOGIC := '0'; + SIGNAL nl0Ol0Oll : STD_LOGIC := '0'; + SIGNAL nl0Ol1llO : STD_LOGIC := '0'; + SIGNAL nl0Ol1lOi : STD_LOGIC := '0'; + SIGNAL nl0Ol1lOl : STD_LOGIC := '0'; + SIGNAL nl0Ol1lOO : STD_LOGIC := '0'; + SIGNAL nl0Ol1O0i : STD_LOGIC := '0'; + SIGNAL nl0Ol1O0l : STD_LOGIC := '0'; + SIGNAL nl0Ol1O0O : STD_LOGIC := '0'; + SIGNAL nl0Ol1O1i : STD_LOGIC := '0'; + SIGNAL nl0Ol1O1l : STD_LOGIC := '0'; + SIGNAL nl0Ol1O1O : STD_LOGIC := '0'; + SIGNAL nl0Ol1Oii : STD_LOGIC := '0'; + SIGNAL nl0Ol1Oil : STD_LOGIC := '0'; + SIGNAL nl0Ol1OiO : STD_LOGIC := '0'; + SIGNAL nl0Ol1Oli : STD_LOGIC := '0'; + SIGNAL nl0Ol1Oll : STD_LOGIC := '0'; + SIGNAL nl0Ol1OlO : STD_LOGIC := '0'; + SIGNAL nl0Ol1OOi : STD_LOGIC := '0'; + SIGNAL nl0Ol1OOl : STD_LOGIC := '0'; + SIGNAL nl0Ol1OOO : STD_LOGIC := '0'; + SIGNAL nl0OO0Oii : STD_LOGIC := '0'; + SIGNAL nl0OO0Oil : STD_LOGIC := '0'; + SIGNAL nl0OO0OiO : STD_LOGIC := '0'; + SIGNAL nl0OO0Oli : STD_LOGIC := '0'; + SIGNAL nl0OO0Oll : STD_LOGIC := '0'; + SIGNAL nl0OO0OlO : STD_LOGIC := '0'; + SIGNAL nl0OO0OOi : STD_LOGIC := '0'; + SIGNAL nl0OO0OOl : STD_LOGIC := '0'; + SIGNAL nl0OO0OOO : STD_LOGIC := '0'; + SIGNAL nl0OO1iOO : STD_LOGIC := '0'; + SIGNAL nl0OO1l0i : STD_LOGIC := '0'; + SIGNAL nl0OO1l0l : STD_LOGIC := '0'; + SIGNAL nl0OO1l0O : STD_LOGIC := '0'; + SIGNAL nl0OO1l1i : STD_LOGIC := '0'; + SIGNAL nl0OO1l1l : STD_LOGIC := '0'; + SIGNAL nl0OO1l1O : STD_LOGIC := '0'; + SIGNAL nl0OO1lii : STD_LOGIC := '0'; + SIGNAL nl0OO1lil : STD_LOGIC := '0'; + SIGNAL nl0OO1liO : STD_LOGIC := '0'; + SIGNAL nl0OO1lli : STD_LOGIC := '0'; + SIGNAL nl0OO1lll : STD_LOGIC := '0'; + SIGNAL nl0OO1llO : STD_LOGIC := '0'; + SIGNAL nl0OO1lOi : STD_LOGIC := '0'; + SIGNAL nl0OO1lOl : STD_LOGIC := '0'; + SIGNAL nl0OO1lOO : STD_LOGIC := '0'; + SIGNAL nl0OO1O0i : STD_LOGIC := '0'; + SIGNAL nl0OO1O0l : STD_LOGIC := '0'; + SIGNAL nl0OO1O0O : STD_LOGIC := '0'; + SIGNAL nl0OO1O1i : STD_LOGIC := '0'; + SIGNAL nl0OO1O1l : STD_LOGIC := '0'; + SIGNAL nl0OO1O1O : STD_LOGIC := '0'; + SIGNAL nl0OO1Oii : STD_LOGIC := '0'; + SIGNAL nl0OO1Oil : STD_LOGIC := '0'; + SIGNAL nl0OOi00i : STD_LOGIC := '0'; + SIGNAL nl0OOi00l : STD_LOGIC := '0'; + SIGNAL nl0OOi00O : STD_LOGIC := '0'; + SIGNAL nl0OOi01i : STD_LOGIC := '0'; + SIGNAL nl0OOi01l : STD_LOGIC := '0'; + SIGNAL nl0OOi01O : STD_LOGIC := '0'; + SIGNAL nl0OOi0ii : STD_LOGIC := '0'; + SIGNAL nl0OOi0il : STD_LOGIC := '0'; + SIGNAL nl0OOi0iO : STD_LOGIC := '0'; + SIGNAL nl0OOi0li : STD_LOGIC := '0'; + SIGNAL nl0OOi0ll : STD_LOGIC := '0'; + SIGNAL nl0OOi0lO : STD_LOGIC := '0'; + SIGNAL nl0OOi0Oi : STD_LOGIC := '0'; + SIGNAL nl0OOi0Ol : STD_LOGIC := '0'; + SIGNAL nl0OOi0OO : STD_LOGIC := '0'; + SIGNAL nl0OOi10i : STD_LOGIC := '0'; + SIGNAL nl0OOi10l : STD_LOGIC := '0'; + SIGNAL nl0OOi10O : STD_LOGIC := '0'; + SIGNAL nl0OOi11i : STD_LOGIC := '0'; + SIGNAL nl0OOi11l : STD_LOGIC := '0'; + SIGNAL nl0OOi11O : STD_LOGIC := '0'; + SIGNAL nl0OOi1ii : STD_LOGIC := '0'; + SIGNAL nl0OOi1il : STD_LOGIC := '0'; + SIGNAL nl0OOi1iO : STD_LOGIC := '0'; + SIGNAL nl0OOi1li : STD_LOGIC := '0'; + SIGNAL nl0OOi1ll : STD_LOGIC := '0'; + SIGNAL nl0OOi1lO : STD_LOGIC := '0'; + SIGNAL nl0OOi1Oi : STD_LOGIC := '0'; + SIGNAL nl0OOi1Ol : STD_LOGIC := '0'; + SIGNAL nl0OOi1OO : STD_LOGIC := '0'; + SIGNAL nl0OOii1i : STD_LOGIC := '0'; + SIGNAL nl0OOO00i : STD_LOGIC := '0'; + SIGNAL nl0OOO00l : STD_LOGIC := '0'; + SIGNAL nl0OOO00O : STD_LOGIC := '0'; + SIGNAL nl0OOO01i : STD_LOGIC := '0'; + SIGNAL nl0OOO01l : STD_LOGIC := '0'; + SIGNAL nl0OOO01O : STD_LOGIC := '0'; + SIGNAL nl0OOO0ii : STD_LOGIC := '0'; + SIGNAL nl0OOO0il : STD_LOGIC := '0'; + SIGNAL nl0OOO0iO : STD_LOGIC := '0'; + SIGNAL nl0OOO10i : STD_LOGIC := '0'; + SIGNAL nl0OOO10l : STD_LOGIC := '0'; + SIGNAL nl0OOO10O : STD_LOGIC := '0'; + SIGNAL nl0OOO11l : STD_LOGIC := '0'; + SIGNAL nl0OOO11O : STD_LOGIC := '0'; + SIGNAL nl0OOO1ii : STD_LOGIC := '0'; + SIGNAL nl0OOO1il : STD_LOGIC := '0'; + SIGNAL nl0OOO1iO : STD_LOGIC := '0'; + SIGNAL nl0OOO1li : STD_LOGIC := '0'; + SIGNAL nl0OOO1ll : STD_LOGIC := '0'; + SIGNAL nl0OOO1lO : STD_LOGIC := '0'; + SIGNAL nl0OOO1Oi : STD_LOGIC := '0'; + SIGNAL nl0OOO1Ol : STD_LOGIC := '0'; + SIGNAL nl0OOO1OO : STD_LOGIC := '0'; + SIGNAL nl10ii0li : STD_LOGIC := '0'; + SIGNAL nl10ii0ll : STD_LOGIC := '0'; + SIGNAL nl10ilO0O : STD_LOGIC := '0'; + SIGNAL nl10ilOii : STD_LOGIC := '0'; + SIGNAL nl10ilOil : STD_LOGIC := '0'; + SIGNAL nl10ilOiO : STD_LOGIC := '0'; + SIGNAL nl10ilOli : STD_LOGIC := '0'; + SIGNAL nl10ilOll : STD_LOGIC := '0'; + SIGNAL nl10ilOlO : STD_LOGIC := '0'; + SIGNAL nl10ilOOi : STD_LOGIC := '0'; + SIGNAL nl10ilOOl : STD_LOGIC := '0'; + SIGNAL nl10iO1li : STD_LOGIC := '0'; + SIGNAL nl10iOO0i : STD_LOGIC := '0'; + SIGNAL nl10iOO0l : STD_LOGIC := '0'; + SIGNAL nl10iOO0O : STD_LOGIC := '0'; + SIGNAL nl10iOO1O : STD_LOGIC := '0'; + SIGNAL nl10iOOii : STD_LOGIC := '0'; + SIGNAL nl10iOOil : STD_LOGIC := '0'; + SIGNAL nl10iOOiO : STD_LOGIC := '0'; + SIGNAL nl10iOOli : STD_LOGIC := '0'; + SIGNAL nl10iOOll : STD_LOGIC := '0'; + SIGNAL nl10liO1l : STD_LOGIC := '0'; + SIGNAL nl10lli0O : STD_LOGIC := '0'; + SIGNAL nl10lliil : STD_LOGIC := '0'; + SIGNAL nl10lliiO : STD_LOGIC := '0'; + SIGNAL nl10llili : STD_LOGIC := '0'; + SIGNAL nl10llill : STD_LOGIC := '0'; + SIGNAL nl10llilO : STD_LOGIC := '0'; + SIGNAL nl10lliOi : STD_LOGIC := '0'; + SIGNAL nl10lliOO : STD_LOGIC := '0'; + SIGNAL nl10lll0i : STD_LOGIC := '0'; + SIGNAL nl10lll1i : STD_LOGIC := '0'; + SIGNAL nl10lll1l : STD_LOGIC := '0'; + SIGNAL nl10lll1O : STD_LOGIC := '0'; + SIGNAL nl10O000i : STD_LOGIC := '0'; + SIGNAL nl10O000l : STD_LOGIC := '0'; + SIGNAL nl10O000O : STD_LOGIC := '0'; + SIGNAL nl10O001i : STD_LOGIC := '0'; + SIGNAL nl10O001l : STD_LOGIC := '0'; + SIGNAL nl10O001O : STD_LOGIC := '0'; + SIGNAL nl10O00ii : STD_LOGIC := '0'; + SIGNAL nl10O00il : STD_LOGIC := '0'; + SIGNAL nl10O00iO : STD_LOGIC := '0'; + SIGNAL nl10O00li : STD_LOGIC := '0'; + SIGNAL nl10O00ll : STD_LOGIC := '0'; + SIGNAL nl10O00lO : STD_LOGIC := '0'; + SIGNAL nl10O00Oi : STD_LOGIC := '0'; + SIGNAL nl10O00Ol : STD_LOGIC := '0'; + SIGNAL nl10O00OO : STD_LOGIC := '0'; + SIGNAL nl10O01Ol : STD_LOGIC := '0'; + SIGNAL nl10O01OO : STD_LOGIC := '0'; + SIGNAL nl10O0i0i : STD_LOGIC := '0'; + SIGNAL nl10O0i0l : STD_LOGIC := '0'; + SIGNAL nl10O0i0O : STD_LOGIC := '0'; + SIGNAL nl10O0i1i : STD_LOGIC := '0'; + SIGNAL nl10O0i1l : STD_LOGIC := '0'; + SIGNAL nl10O0i1O : STD_LOGIC := '0'; + SIGNAL nl10O0iii : STD_LOGIC := '0'; + SIGNAL nl10O0iil : STD_LOGIC := '0'; + SIGNAL nl10O0iiO : STD_LOGIC := '0'; + SIGNAL nl10O0ili : STD_LOGIC := '0'; + SIGNAL nl10O0ill : STD_LOGIC := '0'; + SIGNAL nl10O0ilO : STD_LOGIC := '0'; + SIGNAL nl10O0iOi : STD_LOGIC := '0'; + SIGNAL nl10O0iOl : STD_LOGIC := '0'; + SIGNAL nl10O0iOO : STD_LOGIC := '0'; + SIGNAL nl10O0l0i : STD_LOGIC := '0'; + SIGNAL nl10O0l0l : STD_LOGIC := '0'; + SIGNAL nl10O0l0O : STD_LOGIC := '0'; + SIGNAL nl10O0l1i : STD_LOGIC := '0'; + SIGNAL nl10O0l1l : STD_LOGIC := '0'; + SIGNAL nl10O0l1O : STD_LOGIC := '0'; + SIGNAL nl10O0lii : STD_LOGIC := '0'; + SIGNAL nl10O0lil : STD_LOGIC := '0'; + SIGNAL nl10O0liO : STD_LOGIC := '0'; + SIGNAL nl10O0lli : STD_LOGIC := '0'; + SIGNAL nl10O0lll : STD_LOGIC := '0'; + SIGNAL nl10O0llO : STD_LOGIC := '0'; + SIGNAL nl10O0lOi : STD_LOGIC := '0'; + SIGNAL nl10O0lOl : STD_LOGIC := '0'; + SIGNAL nl10O0lOO : STD_LOGIC := '0'; + SIGNAL nl10O0O0i : STD_LOGIC := '0'; + SIGNAL nl10O0O0l : STD_LOGIC := '0'; + SIGNAL nl10O0O0O : STD_LOGIC := '0'; + SIGNAL nl10O0O1i : STD_LOGIC := '0'; + SIGNAL nl10O0O1l : STD_LOGIC := '0'; + SIGNAL nl10O0O1O : STD_LOGIC := '0'; + SIGNAL nl10O0Oii : STD_LOGIC := '0'; + SIGNAL nl10O0Oil : STD_LOGIC := '0'; + SIGNAL nl10O0OiO : STD_LOGIC := '0'; + SIGNAL nl10O0Oli : STD_LOGIC := '0'; + SIGNAL nl10O0Oll : STD_LOGIC := '0'; + SIGNAL nl10O0OlO : STD_LOGIC := '0'; + SIGNAL nl10O0OOi : STD_LOGIC := '0'; + SIGNAL nl10O100i : STD_LOGIC := '0'; + SIGNAL nl10O100l : STD_LOGIC := '0'; + SIGNAL nl10O101i : STD_LOGIC := '0'; + SIGNAL nl10O101l : STD_LOGIC := '0'; + SIGNAL nl10O101O : STD_LOGIC := '0'; + SIGNAL nl10O110O : STD_LOGIC := '0'; + SIGNAL nl10O11ii : STD_LOGIC := '0'; + SIGNAL nl10O11il : STD_LOGIC := '0'; + SIGNAL nl10O11iO : STD_LOGIC := '0'; + SIGNAL nl10O11li : STD_LOGIC := '0'; + SIGNAL nl10O11ll : STD_LOGIC := '0'; + SIGNAL nl10O11lO : STD_LOGIC := '0'; + SIGNAL nl10O11Oi : STD_LOGIC := '0'; + SIGNAL nl10O11Ol : STD_LOGIC := '0'; + SIGNAL nl10O11OO : STD_LOGIC := '0'; + SIGNAL nl110100i : STD_LOGIC := '0'; + SIGNAL nl110100l : STD_LOGIC := '0'; + SIGNAL nl110100O : STD_LOGIC := '0'; + SIGNAL nl110101i : STD_LOGIC := '0'; + SIGNAL nl110101l : STD_LOGIC := '0'; + SIGNAL nl110101O : STD_LOGIC := '0'; + SIGNAL nl11010ii : STD_LOGIC := '0'; + SIGNAL nl11010il : STD_LOGIC := '0'; + SIGNAL nl11010iO : STD_LOGIC := '0'; + SIGNAL nl11010li : STD_LOGIC := '0'; + SIGNAL nl11010ll : STD_LOGIC := '0'; + SIGNAL nl11010lO : STD_LOGIC := '0'; + SIGNAL nl11010Oi : STD_LOGIC := '0'; + SIGNAL nl11010Ol : STD_LOGIC := '0'; + SIGNAL nl11010OO : STD_LOGIC := '0'; + SIGNAL nl110110i : STD_LOGIC := '0'; + SIGNAL nl110110l : STD_LOGIC := '0'; + SIGNAL nl110110O : STD_LOGIC := '0'; + SIGNAL nl110111i : STD_LOGIC := '0'; + SIGNAL nl110111l : STD_LOGIC := '0'; + SIGNAL nl110111O : STD_LOGIC := '0'; + SIGNAL nl11011ii : STD_LOGIC := '0'; + SIGNAL nl11011il : STD_LOGIC := '0'; + SIGNAL nl11011iO : STD_LOGIC := '0'; + SIGNAL nl11011li : STD_LOGIC := '0'; + SIGNAL nl11011ll : STD_LOGIC := '0'; + SIGNAL nl11011lO : STD_LOGIC := '0'; + SIGNAL nl11011Oi : STD_LOGIC := '0'; + SIGNAL nl11011Ol : STD_LOGIC := '0'; + SIGNAL nl11011OO : STD_LOGIC := '0'; + SIGNAL nl1101i0i : STD_LOGIC := '0'; + SIGNAL nl1101i0l : STD_LOGIC := '0'; + SIGNAL nl1101i0O : STD_LOGIC := '0'; + SIGNAL nl1101i1i : STD_LOGIC := '0'; + SIGNAL nl1101i1l : STD_LOGIC := '0'; + SIGNAL nl1101i1O : STD_LOGIC := '0'; + SIGNAL nl1101iii : STD_LOGIC := '0'; + SIGNAL nl1101iil : STD_LOGIC := '0'; + SIGNAL nl1101iiO : STD_LOGIC := '0'; + SIGNAL nl1101ili : STD_LOGIC := '0'; + SIGNAL nl1101ill : STD_LOGIC := '0'; + SIGNAL nl1101ilO : STD_LOGIC := '0'; + SIGNAL nl1101iOi : STD_LOGIC := '0'; + SIGNAL nl1101iOl : STD_LOGIC := '0'; + SIGNAL nl1101iOO : STD_LOGIC := '0'; + SIGNAL nl1101l0i : STD_LOGIC := '0'; + SIGNAL nl1101l0l : STD_LOGIC := '0'; + SIGNAL nl1101l0O : STD_LOGIC := '0'; + SIGNAL nl1101l1i : STD_LOGIC := '0'; + SIGNAL nl1101l1l : STD_LOGIC := '0'; + SIGNAL nl1101l1O : STD_LOGIC := '0'; + SIGNAL nl110Oi0i : STD_LOGIC := '0'; + SIGNAL nl110Oi0l : STD_LOGIC := '0'; + SIGNAL nl110Oi0O : STD_LOGIC := '0'; + SIGNAL nl110Oi1l : STD_LOGIC := '0'; + SIGNAL nl110Oi1O : STD_LOGIC := '0'; + SIGNAL nl110Oiii : STD_LOGIC := '0'; + SIGNAL nl110Oiil : STD_LOGIC := '0'; + SIGNAL nl110OiiO : STD_LOGIC := '0'; + SIGNAL nl110Oili : STD_LOGIC := '0'; + SIGNAL nl110Oill : STD_LOGIC := '0'; + SIGNAL nl110OilO : STD_LOGIC := '0'; + SIGNAL nl110OiOi : STD_LOGIC := '0'; + SIGNAL nl110OiOl : STD_LOGIC := '0'; + SIGNAL nl110OiOO : STD_LOGIC := '0'; + SIGNAL nl110Ol0i : STD_LOGIC := '0'; + SIGNAL nl110Ol0l : STD_LOGIC := '0'; + SIGNAL nl110Ol0O : STD_LOGIC := '0'; + SIGNAL nl110Ol1i : STD_LOGIC := '0'; + SIGNAL nl110Ol1l : STD_LOGIC := '0'; + SIGNAL nl110Ol1O : STD_LOGIC := '0'; + SIGNAL nl110Olii : STD_LOGIC := '0'; + SIGNAL nl110Olil : STD_LOGIC := '0'; + SIGNAL nl110OliO : STD_LOGIC := '0'; + SIGNAL nl110Olli : STD_LOGIC := '0'; + SIGNAL nl110Olll : STD_LOGIC := '0'; + SIGNAL nl110OllO : STD_LOGIC := '0'; + SIGNAL nl110OlOi : STD_LOGIC := '0'; + SIGNAL nl110OlOl : STD_LOGIC := '0'; + SIGNAL nl110OlOO : STD_LOGIC := '0'; + SIGNAL nl110OO0i : STD_LOGIC := '0'; + SIGNAL nl110OO0l : STD_LOGIC := '0'; + SIGNAL nl110OO0O : STD_LOGIC := '0'; + SIGNAL nl110OO1i : STD_LOGIC := '0'; + SIGNAL nl110OO1l : STD_LOGIC := '0'; + SIGNAL nl110OO1O : STD_LOGIC := '0'; + SIGNAL nl110OOii : STD_LOGIC := '0'; + SIGNAL nl110OOil : STD_LOGIC := '0'; + SIGNAL nl110OOiO : STD_LOGIC := '0'; + SIGNAL nl110OOli : STD_LOGIC := '0'; + SIGNAL nl110OOll : STD_LOGIC := '0'; + SIGNAL nl110OOlO : STD_LOGIC := '0'; + SIGNAL nl110OOOi : STD_LOGIC := '0'; + SIGNAL nl110OOOl : STD_LOGIC := '0'; + SIGNAL nl110OOOO : STD_LOGIC := '0'; + SIGNAL nl11100iO : STD_LOGIC := '0'; + SIGNAL nl11100li : STD_LOGIC := '0'; + SIGNAL nl11100ll : STD_LOGIC := '0'; + SIGNAL nl11100lO : STD_LOGIC := '0'; + SIGNAL nl11100Oi : STD_LOGIC := '0'; + SIGNAL nl11100Ol : STD_LOGIC := '0'; + SIGNAL nl11100OO : STD_LOGIC := '0'; + SIGNAL nl11101il : STD_LOGIC := '0'; + SIGNAL nl1110i0i : STD_LOGIC := '0'; + SIGNAL nl1110i0l : STD_LOGIC := '0'; + SIGNAL nl1110i0O : STD_LOGIC := '0'; + SIGNAL nl1110i1i : STD_LOGIC := '0'; + SIGNAL nl1110i1l : STD_LOGIC := '0'; + SIGNAL nl1110i1O : STD_LOGIC := '0'; + SIGNAL nl1110iii : STD_LOGIC := '0'; + SIGNAL nl1110iil : STD_LOGIC := '0'; + SIGNAL nl1110iiO : STD_LOGIC := '0'; + SIGNAL nl1110ili : STD_LOGIC := '0'; + SIGNAL nl1110ill : STD_LOGIC := '0'; + SIGNAL nl1110ilO : STD_LOGIC := '0'; + SIGNAL nl1110iOi : STD_LOGIC := '0'; + SIGNAL nl1110iOl : STD_LOGIC := '0'; + SIGNAL nl1110iOO : STD_LOGIC := '0'; + SIGNAL nl1110l0i : STD_LOGIC := '0'; + SIGNAL nl1110l0l : STD_LOGIC := '0'; + SIGNAL nl1110l0O : STD_LOGIC := '0'; + SIGNAL nl1110l1i : STD_LOGIC := '0'; + SIGNAL nl1110l1l : STD_LOGIC := '0'; + SIGNAL nl1110l1O : STD_LOGIC := '0'; + SIGNAL nl1110lii : STD_LOGIC := '0'; + SIGNAL nl1110lil : STD_LOGIC := '0'; + SIGNAL nl1110liO : STD_LOGIC := '0'; + SIGNAL nl1110lli : STD_LOGIC := '0'; + SIGNAL nl1110lll : STD_LOGIC := '0'; + SIGNAL nl1110llO : STD_LOGIC := '0'; + SIGNAL nl1110lOi : STD_LOGIC := '0'; + SIGNAL nl1110lOl : STD_LOGIC := '0'; + SIGNAL nl1110lOO : STD_LOGIC := '0'; + SIGNAL nl1110O0i : STD_LOGIC := '0'; + SIGNAL nl1110O0l : STD_LOGIC := '0'; + SIGNAL nl1110O0O : STD_LOGIC := '0'; + SIGNAL nl1110O1i : STD_LOGIC := '0'; + SIGNAL nl1110O1l : STD_LOGIC := '0'; + SIGNAL nl1110O1O : STD_LOGIC := '0'; + SIGNAL nl1110Oii : STD_LOGIC := '0'; + SIGNAL nl1110Oil : STD_LOGIC := '0'; + SIGNAL nl1110OiO : STD_LOGIC := '0'; + SIGNAL nl1110Oli : STD_LOGIC := '0'; + SIGNAL nl1110Oll : STD_LOGIC := '0'; + SIGNAL nl1110OlO : STD_LOGIC := '0'; + SIGNAL nl1110OOi : STD_LOGIC := '0'; + SIGNAL nl1110OOl : STD_LOGIC := '0'; + SIGNAL nl1110OOO : STD_LOGIC := '0'; + SIGNAL nl111i10i : STD_LOGIC := '0'; + SIGNAL nl111i10l : STD_LOGIC := '0'; + SIGNAL nl111i10O : STD_LOGIC := '0'; + SIGNAL nl111i11i : STD_LOGIC := '0'; + SIGNAL nl111i11l : STD_LOGIC := '0'; + SIGNAL nl111i11O : STD_LOGIC := '0'; + SIGNAL nl111i1ii : STD_LOGIC := '0'; + SIGNAL nl111iOli : STD_LOGIC := '0'; + SIGNAL nl111l00i : STD_LOGIC := '0'; + SIGNAL nl111l00l : STD_LOGIC := '0'; + SIGNAL nl111l00O : STD_LOGIC := '0'; + SIGNAL nl111l01i : STD_LOGIC := '0'; + SIGNAL nl111l01l : STD_LOGIC := '0'; + SIGNAL nl111l01O : STD_LOGIC := '0'; + SIGNAL nl111l0ii : STD_LOGIC := '0'; + SIGNAL nl111l0il : STD_LOGIC := '0'; + SIGNAL nl111l0iO : STD_LOGIC := '0'; + SIGNAL nl111l0li : STD_LOGIC := '0'; + SIGNAL nl111l0ll : STD_LOGIC := '0'; + SIGNAL nl111l0lO : STD_LOGIC := '0'; + SIGNAL nl111l0Oi : STD_LOGIC := '0'; + SIGNAL nl111l0Ol : STD_LOGIC := '0'; + SIGNAL nl111l0OO : STD_LOGIC := '0'; + SIGNAL nl111l1lO : STD_LOGIC := '0'; + SIGNAL nl111l1Oi : STD_LOGIC := '0'; + SIGNAL nl111l1Ol : STD_LOGIC := '0'; + SIGNAL nl111l1OO : STD_LOGIC := '0'; + SIGNAL nl111li0i : STD_LOGIC := '0'; + SIGNAL nl111li0l : STD_LOGIC := '0'; + SIGNAL nl111li0O : STD_LOGIC := '0'; + SIGNAL nl111li1i : STD_LOGIC := '0'; + SIGNAL nl111li1l : STD_LOGIC := '0'; + SIGNAL nl111li1O : STD_LOGIC := '0'; + SIGNAL nl111liii : STD_LOGIC := '0'; + SIGNAL nl111liil : STD_LOGIC := '0'; + SIGNAL nl111liiO : STD_LOGIC := '0'; + SIGNAL nl111lili : STD_LOGIC := '0'; + SIGNAL nl111lill : STD_LOGIC := '0'; + SIGNAL nl111lilO : STD_LOGIC := '0'; + SIGNAL nl111liOi : STD_LOGIC := '0'; + SIGNAL nl111liOl : STD_LOGIC := '0'; + SIGNAL nl111liOO : STD_LOGIC := '0'; + SIGNAL nl111ll1i : STD_LOGIC := '0'; + SIGNAL nl111ll1l : STD_LOGIC := '0'; + SIGNAL nl111OO0i : STD_LOGIC := '0'; + SIGNAL nl111OO0l : STD_LOGIC := '0'; + SIGNAL nl111OO0O : STD_LOGIC := '0'; + SIGNAL nl111OO1i : STD_LOGIC := '0'; + SIGNAL nl111OO1l : STD_LOGIC := '0'; + SIGNAL nl111OO1O : STD_LOGIC := '0'; + SIGNAL nl111OOii : STD_LOGIC := '0'; + SIGNAL nl111OOil : STD_LOGIC := '0'; + SIGNAL nl111OOiO : STD_LOGIC := '0'; + SIGNAL nl111OOli : STD_LOGIC := '0'; + SIGNAL nl111OOll : STD_LOGIC := '0'; + SIGNAL nl111OOlO : STD_LOGIC := '0'; + SIGNAL nl111OOOi : STD_LOGIC := '0'; + SIGNAL nl111OOOl : STD_LOGIC := '0'; + SIGNAL nl111OOOO : STD_LOGIC := '0'; + SIGNAL nl11i110i : STD_LOGIC := '0'; + SIGNAL nl11i110l : STD_LOGIC := '0'; + SIGNAL nl11i110O : STD_LOGIC := '0'; + SIGNAL nl11i111i : STD_LOGIC := '0'; + SIGNAL nl11i111l : STD_LOGIC := '0'; + SIGNAL nl11i111O : STD_LOGIC := '0'; + SIGNAL nl11i11ii : STD_LOGIC := '0'; + SIGNAL nl11i11il : STD_LOGIC := '0'; + SIGNAL nl11i11iO : STD_LOGIC := '0'; + SIGNAL nl11i11li : STD_LOGIC := '0'; + SIGNAL nl11i11ll : STD_LOGIC := '0'; + SIGNAL nl11i11lO : STD_LOGIC := '0'; + SIGNAL nl11i11Oi : STD_LOGIC := '0'; + SIGNAL nl11i11Ol : STD_LOGIC := '0'; + SIGNAL nl11i11OO : STD_LOGIC := '0'; + SIGNAL nl11iiOOi : STD_LOGIC := '0'; + SIGNAL nl11iiOOl : STD_LOGIC := '0'; + SIGNAL nl11iiOOO : STD_LOGIC := '0'; + SIGNAL nl11il00i : STD_LOGIC := '0'; + SIGNAL nl11il00l : STD_LOGIC := '0'; + SIGNAL nl11il00O : STD_LOGIC := '0'; + SIGNAL nl11il01i : STD_LOGIC := '0'; + SIGNAL nl11il01l : STD_LOGIC := '0'; + SIGNAL nl11il01O : STD_LOGIC := '0'; + SIGNAL nl11il0ii : STD_LOGIC := '0'; + SIGNAL nl11il0il : STD_LOGIC := '0'; + SIGNAL nl11il0iO : STD_LOGIC := '0'; + SIGNAL nl11il0li : STD_LOGIC := '0'; + SIGNAL nl11il0ll : STD_LOGIC := '0'; + SIGNAL nl11il0lO : STD_LOGIC := '0'; + SIGNAL nl11il0Oi : STD_LOGIC := '0'; + SIGNAL nl11il0Ol : STD_LOGIC := '0'; + SIGNAL nl11il0OO : STD_LOGIC := '0'; + SIGNAL nl11il10i : STD_LOGIC := '0'; + SIGNAL nl11il10l : STD_LOGIC := '0'; + SIGNAL nl11il10O : STD_LOGIC := '0'; + SIGNAL nl11il11i : STD_LOGIC := '0'; + SIGNAL nl11il11l : STD_LOGIC := '0'; + SIGNAL nl11il11O : STD_LOGIC := '0'; + SIGNAL nl11il1ii : STD_LOGIC := '0'; + SIGNAL nl11il1il : STD_LOGIC := '0'; + SIGNAL nl11il1iO : STD_LOGIC := '0'; + SIGNAL nl11il1li : STD_LOGIC := '0'; + SIGNAL nl11il1ll : STD_LOGIC := '0'; + SIGNAL nl11il1lO : STD_LOGIC := '0'; + SIGNAL nl11il1Oi : STD_LOGIC := '0'; + SIGNAL nl11il1Ol : STD_LOGIC := '0'; + SIGNAL nl11il1OO : STD_LOGIC := '0'; + SIGNAL nl11ili0i : STD_LOGIC := '0'; + SIGNAL nl11ili0l : STD_LOGIC := '0'; + SIGNAL nl11ili0O : STD_LOGIC := '0'; + SIGNAL nl11ili1i : STD_LOGIC := '0'; + SIGNAL nl11ili1l : STD_LOGIC := '0'; + SIGNAL nl11ili1O : STD_LOGIC := '0'; + SIGNAL nl11iliii : STD_LOGIC := '0'; + SIGNAL nl11iliil : STD_LOGIC := '0'; + SIGNAL nl11iliiO : STD_LOGIC := '0'; + SIGNAL nl11ilili : STD_LOGIC := '0'; + SIGNAL nl11ilill : STD_LOGIC := '0'; + SIGNAL nl11ililO : STD_LOGIC := '0'; + SIGNAL nl11iliOi : STD_LOGIC := '0'; + SIGNAL nl11iliOl : STD_LOGIC := '0'; + SIGNAL nl11iliOO : STD_LOGIC := '0'; + SIGNAL nl11ill0i : STD_LOGIC := '0'; + SIGNAL nl11ill0l : STD_LOGIC := '0'; + SIGNAL nl11ill0O : STD_LOGIC := '0'; + SIGNAL nl11ill1i : STD_LOGIC := '0'; + SIGNAL nl11ill1l : STD_LOGIC := '0'; + SIGNAL nl11ill1O : STD_LOGIC := '0'; + SIGNAL nl11illii : STD_LOGIC := '0'; + SIGNAL nl11illil : STD_LOGIC := '0'; + SIGNAL nl11illiO : STD_LOGIC := '0'; + SIGNAL nl11illli : STD_LOGIC := '0'; + SIGNAL nl11illll : STD_LOGIC := '0'; + SIGNAL nl11illlO : STD_LOGIC := '0'; + SIGNAL nl11illOi : STD_LOGIC := '0'; + SIGNAL nl11illOl : STD_LOGIC := '0'; + SIGNAL nl11illOO : STD_LOGIC := '0'; + SIGNAL nl11ilO1i : STD_LOGIC := '0'; + SIGNAL nl11l000i : STD_LOGIC := '0'; + SIGNAL nl11l000l : STD_LOGIC := '0'; + SIGNAL nl11l000O : STD_LOGIC := '0'; + SIGNAL nl11l001i : STD_LOGIC := '0'; + SIGNAL nl11l001l : STD_LOGIC := '0'; + SIGNAL nl11l001O : STD_LOGIC := '0'; + SIGNAL nl11l00ii : STD_LOGIC := '0'; + SIGNAL nl11l00il : STD_LOGIC := '0'; + SIGNAL nl11l00iO : STD_LOGIC := '0'; + SIGNAL nl11l00li : STD_LOGIC := '0'; + SIGNAL nl11l00ll : STD_LOGIC := '0'; + SIGNAL nl11l00lO : STD_LOGIC := '0'; + SIGNAL nl11l00Oi : STD_LOGIC := '0'; + SIGNAL nl11l00Ol : STD_LOGIC := '0'; + SIGNAL nl11l00OO : STD_LOGIC := '0'; + SIGNAL nl11l010i : STD_LOGIC := '0'; + SIGNAL nl11l010l : STD_LOGIC := '0'; + SIGNAL nl11l010O : STD_LOGIC := '0'; + SIGNAL nl11l011i : STD_LOGIC := '0'; + SIGNAL nl11l011l : STD_LOGIC := '0'; + SIGNAL nl11l011O : STD_LOGIC := '0'; + SIGNAL nl11l01ii : STD_LOGIC := '0'; + SIGNAL nl11l01il : STD_LOGIC := '0'; + SIGNAL nl11l01iO : STD_LOGIC := '0'; + SIGNAL nl11l01li : STD_LOGIC := '0'; + SIGNAL nl11l01ll : STD_LOGIC := '0'; + SIGNAL nl11l01lO : STD_LOGIC := '0'; + SIGNAL nl11l01Oi : STD_LOGIC := '0'; + SIGNAL nl11l01Ol : STD_LOGIC := '0'; + SIGNAL nl11l01OO : STD_LOGIC := '0'; + SIGNAL nl11l0i1i : STD_LOGIC := '0'; + SIGNAL nl11l1ili : STD_LOGIC := '0'; + SIGNAL nl11l1iOi : STD_LOGIC := '0'; + SIGNAL nl11l1iOl : STD_LOGIC := '0'; + SIGNAL nl11l1iOO : STD_LOGIC := '0'; + SIGNAL nl11l1l0i : STD_LOGIC := '0'; + SIGNAL nl11l1l0l : STD_LOGIC := '0'; + SIGNAL nl11l1l0O : STD_LOGIC := '0'; + SIGNAL nl11l1l1i : STD_LOGIC := '0'; + SIGNAL nl11l1l1l : STD_LOGIC := '0'; + SIGNAL nl11l1l1O : STD_LOGIC := '0'; + SIGNAL nl11l1lii : STD_LOGIC := '0'; + SIGNAL nl11l1lil : STD_LOGIC := '0'; + SIGNAL nl11l1liO : STD_LOGIC := '0'; + SIGNAL nl11l1lli : STD_LOGIC := '0'; + SIGNAL nl11l1lll : STD_LOGIC := '0'; + SIGNAL nl11l1llO : STD_LOGIC := '0'; + SIGNAL nl11l1lOi : STD_LOGIC := '0'; + SIGNAL nl11l1lOl : STD_LOGIC := '0'; + SIGNAL nl11l1lOO : STD_LOGIC := '0'; + SIGNAL nl11l1O0i : STD_LOGIC := '0'; + SIGNAL nl11l1O0l : STD_LOGIC := '0'; + SIGNAL nl11l1O0O : STD_LOGIC := '0'; + SIGNAL nl11l1O1i : STD_LOGIC := '0'; + SIGNAL nl11l1O1l : STD_LOGIC := '0'; + SIGNAL nl11l1O1O : STD_LOGIC := '0'; + SIGNAL nl11l1Oii : STD_LOGIC := '0'; + SIGNAL nl11l1Oil : STD_LOGIC := '0'; + SIGNAL nl11l1OiO : STD_LOGIC := '0'; + SIGNAL nl11l1Oli : STD_LOGIC := '0'; + SIGNAL nl11l1Oll : STD_LOGIC := '0'; + SIGNAL nl11l1OlO : STD_LOGIC := '0'; + SIGNAL nl11l1OOi : STD_LOGIC := '0'; + SIGNAL nl11l1OOl : STD_LOGIC := '0'; + SIGNAL nl11l1OOO : STD_LOGIC := '0'; + SIGNAL nl11lO00i : STD_LOGIC := '0'; + SIGNAL nl11lO00l : STD_LOGIC := '0'; + SIGNAL nl11lO00O : STD_LOGIC := '0'; + SIGNAL nl11lO01i : STD_LOGIC := '0'; + SIGNAL nl11lO01l : STD_LOGIC := '0'; + SIGNAL nl11lO01O : STD_LOGIC := '0'; + SIGNAL nl11lO0ii : STD_LOGIC := '0'; + SIGNAL nl11lO0il : STD_LOGIC := '0'; + SIGNAL nl11lO0iO : STD_LOGIC := '0'; + SIGNAL nl11lO0li : STD_LOGIC := '0'; + SIGNAL nl11lO0ll : STD_LOGIC := '0'; + SIGNAL nl11lO0lO : STD_LOGIC := '0'; + SIGNAL nl11lO0Oi : STD_LOGIC := '0'; + SIGNAL nl11lO0Ol : STD_LOGIC := '0'; + SIGNAL nl11lO0OO : STD_LOGIC := '0'; + SIGNAL nl11lO10i : STD_LOGIC := '0'; + SIGNAL nl11lO10l : STD_LOGIC := '0'; + SIGNAL nl11lO10O : STD_LOGIC := '0'; + SIGNAL nl11lO11i : STD_LOGIC := '0'; + SIGNAL nl11lO11l : STD_LOGIC := '0'; + SIGNAL nl11lO11O : STD_LOGIC := '0'; + SIGNAL nl11lO1ii : STD_LOGIC := '0'; + SIGNAL nl11lO1il : STD_LOGIC := '0'; + SIGNAL nl11lO1iO : STD_LOGIC := '0'; + SIGNAL nl11lO1li : STD_LOGIC := '0'; + SIGNAL nl11lO1ll : STD_LOGIC := '0'; + SIGNAL nl11lO1lO : STD_LOGIC := '0'; + SIGNAL nl11lO1Oi : STD_LOGIC := '0'; + SIGNAL nl11lO1Ol : STD_LOGIC := '0'; + SIGNAL nl11lO1OO : STD_LOGIC := '0'; + SIGNAL nl11lOi0i : STD_LOGIC := '0'; + SIGNAL nl11lOi0l : STD_LOGIC := '0'; + SIGNAL nl11lOi0O : STD_LOGIC := '0'; + SIGNAL nl11lOi1i : STD_LOGIC := '0'; + SIGNAL nl11lOi1l : STD_LOGIC := '0'; + SIGNAL nl11lOi1O : STD_LOGIC := '0'; + SIGNAL nl11lOiii : STD_LOGIC := '0'; + SIGNAL nl11lOiil : STD_LOGIC := '0'; + SIGNAL nl11lOiiO : STD_LOGIC := '0'; + SIGNAL nl11lOili : STD_LOGIC := '0'; + SIGNAL nl11lOill : STD_LOGIC := '0'; + SIGNAL nl11lOilO : STD_LOGIC := '0'; + SIGNAL nl11lOiOi : STD_LOGIC := '0'; + SIGNAL nl11lOiOl : STD_LOGIC := '0'; + SIGNAL nl11lOiOO : STD_LOGIC := '0'; + SIGNAL nl11lOl0i : STD_LOGIC := '0'; + SIGNAL nl11lOl0l : STD_LOGIC := '0'; + SIGNAL nl11lOl0O : STD_LOGIC := '0'; + SIGNAL nl11lOl1i : STD_LOGIC := '0'; + SIGNAL nl11lOl1l : STD_LOGIC := '0'; + SIGNAL nl11lOl1O : STD_LOGIC := '0'; + SIGNAL nl11lOlii : STD_LOGIC := '0'; + SIGNAL nl11lOlil : STD_LOGIC := '0'; + SIGNAL nl11lOliO : STD_LOGIC := '0'; + SIGNAL nl11lOlli : STD_LOGIC := '0'; + SIGNAL nl11lOlll : STD_LOGIC := '0'; + SIGNAL nl11lOllO : STD_LOGIC := '0'; + SIGNAL nl11lOlOi : STD_LOGIC := '0'; + SIGNAL nl11lOlOl : STD_LOGIC := '0'; + SIGNAL nl11lOlOO : STD_LOGIC := '0'; + SIGNAL nl11lOO0i : STD_LOGIC := '0'; + SIGNAL nl11lOO1i : STD_LOGIC := '0'; + SIGNAL nl11lOO1l : STD_LOGIC := '0'; + SIGNAL nl11lOO1O : STD_LOGIC := '0'; + SIGNAL nl11Oii0i : STD_LOGIC := '0'; + SIGNAL nl11Oii0l : STD_LOGIC := '0'; + SIGNAL nl11Oii0O : STD_LOGIC := '0'; + SIGNAL nl11OiliO : STD_LOGIC := '0'; + SIGNAL nl11Oilli : STD_LOGIC := '0'; + SIGNAL nl11Oilll : STD_LOGIC := '0'; + SIGNAL nl11OillO : STD_LOGIC := '0'; + SIGNAL nl11OilOi : STD_LOGIC := '0'; + SIGNAL nl11OilOl : STD_LOGIC := '0'; + SIGNAL nl11OilOO : STD_LOGIC := '0'; + SIGNAL nl11OiO0i : STD_LOGIC := '0'; + SIGNAL nl11OiO0l : STD_LOGIC := '0'; + SIGNAL nl11OiO0O : STD_LOGIC := '0'; + SIGNAL nl11OiO1i : STD_LOGIC := '0'; + SIGNAL nl11OiO1l : STD_LOGIC := '0'; + SIGNAL nl11OiO1O : STD_LOGIC := '0'; + SIGNAL nl11OiOii : STD_LOGIC := '0'; + SIGNAL nl11OiOil : STD_LOGIC := '0'; + SIGNAL nl11OiOiO : STD_LOGIC := '0'; + SIGNAL nl11OiOli : STD_LOGIC := '0'; + SIGNAL nl11OiOll : STD_LOGIC := '0'; + SIGNAL nl11OiOlO : STD_LOGIC := '0'; + SIGNAL nl11OiOOi : STD_LOGIC := '0'; + SIGNAL nl11OiOOl : STD_LOGIC := '0'; + SIGNAL nl11OiOOO : STD_LOGIC := '0'; + SIGNAL nl11Ol11i : STD_LOGIC := '0'; + SIGNAL nl11OO00i : STD_LOGIC := '0'; + SIGNAL nl11OO00l : STD_LOGIC := '0'; + SIGNAL nl11OO00O : STD_LOGIC := '0'; + SIGNAL nl11OO0il : STD_LOGIC := '0'; + SIGNAL nl11OO0iO : STD_LOGIC := '0'; + SIGNAL nl11OO0li : STD_LOGIC := '0'; + SIGNAL nl11OO0ll : STD_LOGIC := '0'; + SIGNAL nl11OO0lO : STD_LOGIC := '0'; + SIGNAL nl11OO0Oi : STD_LOGIC := '0'; + SIGNAL nl11OO0Ol : STD_LOGIC := '0'; + SIGNAL nl11OO0OO : STD_LOGIC := '0'; + SIGNAL nl11OOi0i : STD_LOGIC := '0'; + SIGNAL nl11OOi0l : STD_LOGIC := '0'; + SIGNAL nl11OOi0O : STD_LOGIC := '0'; + SIGNAL nl11OOi1i : STD_LOGIC := '0'; + SIGNAL nl11OOi1l : STD_LOGIC := '0'; + SIGNAL nl11OOiii : STD_LOGIC := '0'; + SIGNAL nl11OOiil : STD_LOGIC := '0'; + SIGNAL nl11OOiiO : STD_LOGIC := '0'; + SIGNAL nl11OOili : STD_LOGIC := '0'; + SIGNAL nl11OOill : STD_LOGIC := '0'; + SIGNAL nl11OOilO : STD_LOGIC := '0'; + SIGNAL nl11OOiOi : STD_LOGIC := '0'; + SIGNAL nl11OOiOl : STD_LOGIC := '0'; + SIGNAL nl11OOiOO : STD_LOGIC := '0'; + SIGNAL nl11OOl0i : STD_LOGIC := '0'; + SIGNAL nl11OOl0l : STD_LOGIC := '0'; + SIGNAL nl11OOl0O : STD_LOGIC := '0'; + SIGNAL nl11OOl1i : STD_LOGIC := '0'; + SIGNAL nl11OOl1l : STD_LOGIC := '0'; + SIGNAL nl11OOl1O : STD_LOGIC := '0'; + SIGNAL nl11OOlii : STD_LOGIC := '0'; + SIGNAL nl11OOlil : STD_LOGIC := '0'; + SIGNAL nl11OOliO : STD_LOGIC := '0'; + SIGNAL nl11OOlli : STD_LOGIC := '0'; + SIGNAL nl11OOlll : STD_LOGIC := '0'; + SIGNAL nl11OOllO : STD_LOGIC := '0'; + SIGNAL nl11OOlOi : STD_LOGIC := '0'; + SIGNAL nl11OOlOl : STD_LOGIC := '0'; + SIGNAL nl11OOlOO : STD_LOGIC := '0'; + SIGNAL nl11OOO0i : STD_LOGIC := '0'; + SIGNAL nl11OOO0l : STD_LOGIC := '0'; + SIGNAL nl11OOO0O : STD_LOGIC := '0'; + SIGNAL nl11OOO1i : STD_LOGIC := '0'; + SIGNAL nl11OOO1l : STD_LOGIC := '0'; + SIGNAL nl11OOO1O : STD_LOGIC := '0'; + SIGNAL nl11OOOii : STD_LOGIC := '0'; + SIGNAL nl1i0100i : STD_LOGIC := '0'; + SIGNAL nl1i0100l : STD_LOGIC := '0'; + SIGNAL nl1i0100O : STD_LOGIC := '0'; + SIGNAL nl1i0101i : STD_LOGIC := '0'; + SIGNAL nl1i0101l : STD_LOGIC := '0'; + SIGNAL nl1i0101O : STD_LOGIC := '0'; + SIGNAL nl1i010ii : STD_LOGIC := '0'; + SIGNAL nl1i010il : STD_LOGIC := '0'; + SIGNAL nl1i010iO : STD_LOGIC := '0'; + SIGNAL nl1i0110i : STD_LOGIC := '0'; + SIGNAL nl1i0110l : STD_LOGIC := '0'; + SIGNAL nl1i0110O : STD_LOGIC := '0'; + SIGNAL nl1i0111i : STD_LOGIC := '0'; + SIGNAL nl1i0111l : STD_LOGIC := '0'; + SIGNAL nl1i0111O : STD_LOGIC := '0'; + SIGNAL nl1i011ii : STD_LOGIC := '0'; + SIGNAL nl1i011il : STD_LOGIC := '0'; + SIGNAL nl1i011iO : STD_LOGIC := '0'; + SIGNAL nl1i011li : STD_LOGIC := '0'; + SIGNAL nl1i011ll : STD_LOGIC := '0'; + SIGNAL nl1i011lO : STD_LOGIC := '0'; + SIGNAL nl1i011Oi : STD_LOGIC := '0'; + SIGNAL nl1i011Ol : STD_LOGIC := '0'; + SIGNAL nl1i011OO : STD_LOGIC := '0'; + SIGNAL nl1i1000i : STD_LOGIC := '0'; + SIGNAL nl1i1000l : STD_LOGIC := '0'; + SIGNAL nl1i1000O : STD_LOGIC := '0'; + SIGNAL nl1i1001i : STD_LOGIC := '0'; + SIGNAL nl1i1001l : STD_LOGIC := '0'; + SIGNAL nl1i1001O : STD_LOGIC := '0'; + SIGNAL nl1i100ii : STD_LOGIC := '0'; + SIGNAL nl1i100il : STD_LOGIC := '0'; + SIGNAL nl1i100iO : STD_LOGIC := '0'; + SIGNAL nl1i100li : STD_LOGIC := '0'; + SIGNAL nl1i100ll : STD_LOGIC := '0'; + SIGNAL nl1i100lO : STD_LOGIC := '0'; + SIGNAL nl1i100Oi : STD_LOGIC := '0'; + SIGNAL nl1i100Ol : STD_LOGIC := '0'; + SIGNAL nl1i100OO : STD_LOGIC := '0'; + SIGNAL nl1i1010i : STD_LOGIC := '0'; + SIGNAL nl1i1010l : STD_LOGIC := '0'; + SIGNAL nl1i1010O : STD_LOGIC := '0'; + SIGNAL nl1i1011i : STD_LOGIC := '0'; + SIGNAL nl1i1011l : STD_LOGIC := '0'; + SIGNAL nl1i1011O : STD_LOGIC := '0'; + SIGNAL nl1i101ii : STD_LOGIC := '0'; + SIGNAL nl1i101il : STD_LOGIC := '0'; + SIGNAL nl1i101iO : STD_LOGIC := '0'; + SIGNAL nl1i101li : STD_LOGIC := '0'; + SIGNAL nl1i101ll : STD_LOGIC := '0'; + SIGNAL nl1i101lO : STD_LOGIC := '0'; + SIGNAL nl1i101Oi : STD_LOGIC := '0'; + SIGNAL nl1i101Ol : STD_LOGIC := '0'; + SIGNAL nl1i101OO : STD_LOGIC := '0'; + SIGNAL nl1i10i0i : STD_LOGIC := '0'; + SIGNAL nl1i10i0l : STD_LOGIC := '0'; + SIGNAL nl1i10i0O : STD_LOGIC := '0'; + SIGNAL nl1i10i1i : STD_LOGIC := '0'; + SIGNAL nl1i10i1l : STD_LOGIC := '0'; + SIGNAL nl1i10i1O : STD_LOGIC := '0'; + SIGNAL nl1i10iii : STD_LOGIC := '0'; + SIGNAL nl1i10iil : STD_LOGIC := '0'; + SIGNAL nl1i10iiO : STD_LOGIC := '0'; + SIGNAL nl1i10ili : STD_LOGIC := '0'; + SIGNAL nl1i10ill : STD_LOGIC := '0'; + SIGNAL nl1i10ilO : STD_LOGIC := '0'; + SIGNAL nl1i10iOi : STD_LOGIC := '0'; + SIGNAL nl1i1101i : STD_LOGIC := '0'; + SIGNAL nl1i1101l : STD_LOGIC := '0'; + SIGNAL nl1i1101O : STD_LOGIC := '0'; + SIGNAL nl1i111Oi : STD_LOGIC := '0'; + SIGNAL nl1i111Ol : STD_LOGIC := '0'; + SIGNAL nl1i111OO : STD_LOGIC := '0'; + SIGNAL nl1i11lOl : STD_LOGIC := '0'; + SIGNAL nl1i11lOO : STD_LOGIC := '0'; + SIGNAL nl1i11O0i : STD_LOGIC := '0'; + SIGNAL nl1i11O0l : STD_LOGIC := '0'; + SIGNAL nl1i11O0O : STD_LOGIC := '0'; + SIGNAL nl1i11O1i : STD_LOGIC := '0'; + SIGNAL nl1i11O1l : STD_LOGIC := '0'; + SIGNAL nl1i11O1O : STD_LOGIC := '0'; + SIGNAL nl1i11Oii : STD_LOGIC := '0'; + SIGNAL nl1i11Oil : STD_LOGIC := '0'; + SIGNAL nl1i11OiO : STD_LOGIC := '0'; + SIGNAL nl1i11Oli : STD_LOGIC := '0'; + SIGNAL nl1i11Oll : STD_LOGIC := '0'; + SIGNAL nl1i11OlO : STD_LOGIC := '0'; + SIGNAL nl1i11OOi : STD_LOGIC := '0'; + SIGNAL nl1i11OOl : STD_LOGIC := '0'; + SIGNAL nl1i11OOO : STD_LOGIC := '0'; + SIGNAL nl1i1Oili : STD_LOGIC := '0'; + SIGNAL nl1i1Oill : STD_LOGIC := '0'; + SIGNAL nl1i1OilO : STD_LOGIC := '0'; + SIGNAL nl1i1OiOi : STD_LOGIC := '0'; + SIGNAL nl1i1OiOl : STD_LOGIC := '0'; + SIGNAL nl1i1OiOO : STD_LOGIC := '0'; + SIGNAL nl1i1Ol0i : STD_LOGIC := '0'; + SIGNAL nl1i1Ol0l : STD_LOGIC := '0'; + SIGNAL nl1i1Ol0O : STD_LOGIC := '0'; + SIGNAL nl1i1Ol1i : STD_LOGIC := '0'; + SIGNAL nl1i1Ol1l : STD_LOGIC := '0'; + SIGNAL nl1i1Ol1O : STD_LOGIC := '0'; + SIGNAL nl1i1Olii : STD_LOGIC := '0'; + SIGNAL nl1i1Olil : STD_LOGIC := '0'; + SIGNAL nl1i1OliO : STD_LOGIC := '0'; + SIGNAL nl1i1Olli : STD_LOGIC := '0'; + SIGNAL nl1i1Olll : STD_LOGIC := '0'; + SIGNAL nl1i1OllO : STD_LOGIC := '0'; + SIGNAL nl1i1OlOi : STD_LOGIC := '0'; + SIGNAL nl1i1OlOl : STD_LOGIC := '0'; + SIGNAL nl1i1OlOO : STD_LOGIC := '0'; + SIGNAL nl1i1OO0i : STD_LOGIC := '0'; + SIGNAL nl1i1OO0l : STD_LOGIC := '0'; + SIGNAL nl1i1OO0O : STD_LOGIC := '0'; + SIGNAL nl1i1OO1i : STD_LOGIC := '0'; + SIGNAL nl1i1OO1l : STD_LOGIC := '0'; + SIGNAL nl1i1OO1O : STD_LOGIC := '0'; + SIGNAL nl1i1OOii : STD_LOGIC := '0'; + SIGNAL nl1i1OOil : STD_LOGIC := '0'; + SIGNAL nl1i1OOiO : STD_LOGIC := '0'; + SIGNAL nl1i1OOli : STD_LOGIC := '0'; + SIGNAL nl1i1OOll : STD_LOGIC := '0'; + SIGNAL nl1i1OOlO : STD_LOGIC := '0'; + SIGNAL nl1i1OOOi : STD_LOGIC := '0'; + SIGNAL nl1i1OOOl : STD_LOGIC := '0'; + SIGNAL nl1i1OOOO : STD_LOGIC := '0'; + SIGNAL nl1iil0Ol : STD_LOGIC := '0'; + SIGNAL nl1iil10O : STD_LOGIC := '0'; + SIGNAL nl1iiO0li : STD_LOGIC := '0'; + SIGNAL nl1iiO0ll : STD_LOGIC := '0'; + SIGNAL nl1iiO0lO : STD_LOGIC := '0'; + SIGNAL nl1iiO0Oi : STD_LOGIC := '0'; + SIGNAL nl1iiO0Ol : STD_LOGIC := '0'; + SIGNAL nl1iiO0OO : STD_LOGIC := '0'; + SIGNAL nl1iiOi0i : STD_LOGIC := '0'; + SIGNAL nl1iiOi0l : STD_LOGIC := '0'; + SIGNAL nl1iiOi0O : STD_LOGIC := '0'; + SIGNAL nl1iiOi1i : STD_LOGIC := '0'; + SIGNAL nl1iiOi1l : STD_LOGIC := '0'; + SIGNAL nl1iiOi1O : STD_LOGIC := '0'; + SIGNAL nl1iiOiii : STD_LOGIC := '0'; + SIGNAL nl1il1i0i : STD_LOGIC := '0'; + SIGNAL nl1il1i0l : STD_LOGIC := '0'; + SIGNAL nl1il1i0O : STD_LOGIC := '0'; + SIGNAL nl1il1i1l : STD_LOGIC := '0'; + SIGNAL nl1il1i1O : STD_LOGIC := '0'; + SIGNAL nl1il1iii : STD_LOGIC := '0'; + SIGNAL nl1il1iil : STD_LOGIC := '0'; + SIGNAL nl1il1iiO : STD_LOGIC := '0'; + SIGNAL nl1il1ili : STD_LOGIC := '0'; + SIGNAL nl1il1ill : STD_LOGIC := '0'; + SIGNAL nl1il1ilO : STD_LOGIC := '0'; + SIGNAL nl1il1iOi : STD_LOGIC := '0'; + SIGNAL nl1il1iOl : STD_LOGIC := '0'; + SIGNAL nl1il1iOO : STD_LOGIC := '0'; + SIGNAL nl1l0000i : STD_LOGIC := '0'; + SIGNAL nl1l0000l : STD_LOGIC := '0'; + SIGNAL nl1l0000O : STD_LOGIC := '0'; + SIGNAL nl1l0001i : STD_LOGIC := '0'; + SIGNAL nl1l0001l : STD_LOGIC := '0'; + SIGNAL nl1l0001O : STD_LOGIC := '0'; + SIGNAL nl1l000ii : STD_LOGIC := '0'; + SIGNAL nl1l000il : STD_LOGIC := '0'; + SIGNAL nl1l000iO : STD_LOGIC := '0'; + SIGNAL nl1l000li : STD_LOGIC := '0'; + SIGNAL nl1l000ll : STD_LOGIC := '0'; + SIGNAL nl1l000lO : STD_LOGIC := '0'; + SIGNAL nl1l000Oi : STD_LOGIC := '0'; + SIGNAL nl1l000Ol : STD_LOGIC := '0'; + SIGNAL nl1l000OO : STD_LOGIC := '0'; + SIGNAL nl1l0010i : STD_LOGIC := '0'; + SIGNAL nl1l0010l : STD_LOGIC := '0'; + SIGNAL nl1l0010O : STD_LOGIC := '0'; + SIGNAL nl1l0011i : STD_LOGIC := '0'; + SIGNAL nl1l0011l : STD_LOGIC := '0'; + SIGNAL nl1l0011O : STD_LOGIC := '0'; + SIGNAL nl1l001ii : STD_LOGIC := '0'; + SIGNAL nl1l001il : STD_LOGIC := '0'; + SIGNAL nl1l001iO : STD_LOGIC := '0'; + SIGNAL nl1l001li : STD_LOGIC := '0'; + SIGNAL nl1l001ll : STD_LOGIC := '0'; + SIGNAL nl1l001lO : STD_LOGIC := '0'; + SIGNAL nl1l001Oi : STD_LOGIC := '0'; + SIGNAL nl1l001Ol : STD_LOGIC := '0'; + SIGNAL nl1l001OO : STD_LOGIC := '0'; + SIGNAL nl1l00i0i : STD_LOGIC := '0'; + SIGNAL nl1l00i0l : STD_LOGIC := '0'; + SIGNAL nl1l00i0O : STD_LOGIC := '0'; + SIGNAL nl1l00i1i : STD_LOGIC := '0'; + SIGNAL nl1l00i1l : STD_LOGIC := '0'; + SIGNAL nl1l00i1O : STD_LOGIC := '0'; + SIGNAL nl1l00iii : STD_LOGIC := '0'; + SIGNAL nl1l00iil : STD_LOGIC := '0'; + SIGNAL nl1l00iiO : STD_LOGIC := '0'; + SIGNAL nl1l00ili : STD_LOGIC := '0'; + SIGNAL nl1l00ill : STD_LOGIC := '0'; + SIGNAL nl1l00ilO : STD_LOGIC := '0'; + SIGNAL nl1l00iOi : STD_LOGIC := '0'; + SIGNAL nl1l00iOl : STD_LOGIC := '0'; + SIGNAL nl1l00iOO : STD_LOGIC := '0'; + SIGNAL nl1l00l0i : STD_LOGIC := '0'; + SIGNAL nl1l00l0l : STD_LOGIC := '0'; + SIGNAL nl1l00l0O : STD_LOGIC := '0'; + SIGNAL nl1l00l1i : STD_LOGIC := '0'; + SIGNAL nl1l00l1l : STD_LOGIC := '0'; + SIGNAL nl1l00l1O : STD_LOGIC := '0'; + SIGNAL nl1l00lii : STD_LOGIC := '0'; + SIGNAL nl1l00lil : STD_LOGIC := '0'; + SIGNAL nl1l00liO : STD_LOGIC := '0'; + SIGNAL nl1l00lli : STD_LOGIC := '0'; + SIGNAL nl1l00lll : STD_LOGIC := '0'; + SIGNAL nl1l00llO : STD_LOGIC := '0'; + SIGNAL nl1l00lOi : STD_LOGIC := '0'; + SIGNAL nl1l00lOl : STD_LOGIC := '0'; + SIGNAL nl1l00lOO : STD_LOGIC := '0'; + SIGNAL nl1l00O0i : STD_LOGIC := '0'; + SIGNAL nl1l00O0l : STD_LOGIC := '0'; + SIGNAL nl1l00O0O : STD_LOGIC := '0'; + SIGNAL nl1l00O1i : STD_LOGIC := '0'; + SIGNAL nl1l00O1l : STD_LOGIC := '0'; + SIGNAL nl1l00O1O : STD_LOGIC := '0'; + SIGNAL nl1l00Oii : STD_LOGIC := '0'; + SIGNAL nl1l00Oil : STD_LOGIC := '0'; + SIGNAL nl1l00OiO : STD_LOGIC := '0'; + SIGNAL nl1l00Oli : STD_LOGIC := '0'; + SIGNAL nl1l00Oll : STD_LOGIC := '0'; + SIGNAL nl1l00OlO : STD_LOGIC := '0'; + SIGNAL nl1l00OOi : STD_LOGIC := '0'; + SIGNAL nl1l00OOl : STD_LOGIC := '0'; + SIGNAL nl1l00OOO : STD_LOGIC := '0'; + SIGNAL nl1l0100i : STD_LOGIC := '0'; + SIGNAL nl1l0100l : STD_LOGIC := '0'; + SIGNAL nl1l0100O : STD_LOGIC := '0'; + SIGNAL nl1l0101i : STD_LOGIC := '0'; + SIGNAL nl1l0101l : STD_LOGIC := '0'; + SIGNAL nl1l0101O : STD_LOGIC := '0'; + SIGNAL nl1l010ii : STD_LOGIC := '0'; + SIGNAL nl1l010il : STD_LOGIC := '0'; + SIGNAL nl1l010iO : STD_LOGIC := '0'; + SIGNAL nl1l010li : STD_LOGIC := '0'; + SIGNAL nl1l010ll : STD_LOGIC := '0'; + SIGNAL nl1l010lO : STD_LOGIC := '0'; + SIGNAL nl1l010Oi : STD_LOGIC := '0'; + SIGNAL nl1l010Ol : STD_LOGIC := '0'; + SIGNAL nl1l010OO : STD_LOGIC := '0'; + SIGNAL nl1l0110i : STD_LOGIC := '0'; + SIGNAL nl1l0110l : STD_LOGIC := '0'; + SIGNAL nl1l0110O : STD_LOGIC := '0'; + SIGNAL nl1l0111i : STD_LOGIC := '0'; + SIGNAL nl1l0111l : STD_LOGIC := '0'; + SIGNAL nl1l0111O : STD_LOGIC := '0'; + SIGNAL nl1l011ii : STD_LOGIC := '0'; + SIGNAL nl1l011il : STD_LOGIC := '0'; + SIGNAL nl1l011iO : STD_LOGIC := '0'; + SIGNAL nl1l011li : STD_LOGIC := '0'; + SIGNAL nl1l011ll : STD_LOGIC := '0'; + SIGNAL nl1l011lO : STD_LOGIC := '0'; + SIGNAL nl1l011Oi : STD_LOGIC := '0'; + SIGNAL nl1l011Ol : STD_LOGIC := '0'; + SIGNAL nl1l011OO : STD_LOGIC := '0'; + SIGNAL nl1l01i0i : STD_LOGIC := '0'; + SIGNAL nl1l01i0l : STD_LOGIC := '0'; + SIGNAL nl1l01i0O : STD_LOGIC := '0'; + SIGNAL nl1l01i1i : STD_LOGIC := '0'; + SIGNAL nl1l01i1l : STD_LOGIC := '0'; + SIGNAL nl1l01i1O : STD_LOGIC := '0'; + SIGNAL nl1l01iii : STD_LOGIC := '0'; + SIGNAL nl1l01iil : STD_LOGIC := '0'; + SIGNAL nl1l01iiO : STD_LOGIC := '0'; + SIGNAL nl1l01ili : STD_LOGIC := '0'; + SIGNAL nl1l01ill : STD_LOGIC := '0'; + SIGNAL nl1l01ilO : STD_LOGIC := '0'; + SIGNAL nl1l01iOi : STD_LOGIC := '0'; + SIGNAL nl1l01iOl : STD_LOGIC := '0'; + SIGNAL nl1l01iOO : STD_LOGIC := '0'; + SIGNAL nl1l01l0i : STD_LOGIC := '0'; + SIGNAL nl1l01l0l : STD_LOGIC := '0'; + SIGNAL nl1l01l0O : STD_LOGIC := '0'; + SIGNAL nl1l01l1i : STD_LOGIC := '0'; + SIGNAL nl1l01l1l : STD_LOGIC := '0'; + SIGNAL nl1l01l1O : STD_LOGIC := '0'; + SIGNAL nl1l01lii : STD_LOGIC := '0'; + SIGNAL nl1l01lil : STD_LOGIC := '0'; + SIGNAL nl1l01liO : STD_LOGIC := '0'; + SIGNAL nl1l01lli : STD_LOGIC := '0'; + SIGNAL nl1l01lll : STD_LOGIC := '0'; + SIGNAL nl1l01llO : STD_LOGIC := '0'; + SIGNAL nl1l01lOi : STD_LOGIC := '0'; + SIGNAL nl1l01lOl : STD_LOGIC := '0'; + SIGNAL nl1l01lOO : STD_LOGIC := '0'; + SIGNAL nl1l01O0i : STD_LOGIC := '0'; + SIGNAL nl1l01O0l : STD_LOGIC := '0'; + SIGNAL nl1l01O0O : STD_LOGIC := '0'; + SIGNAL nl1l01O1i : STD_LOGIC := '0'; + SIGNAL nl1l01O1l : STD_LOGIC := '0'; + SIGNAL nl1l01O1O : STD_LOGIC := '0'; + SIGNAL nl1l01Oii : STD_LOGIC := '0'; + SIGNAL nl1l01Oil : STD_LOGIC := '0'; + SIGNAL nl1l01OiO : STD_LOGIC := '0'; + SIGNAL nl1l01Oli : STD_LOGIC := '0'; + SIGNAL nl1l01Oll : STD_LOGIC := '0'; + SIGNAL nl1l01OlO : STD_LOGIC := '0'; + SIGNAL nl1l01OOi : STD_LOGIC := '0'; + SIGNAL nl1l01OOl : STD_LOGIC := '0'; + SIGNAL nl1l01OOO : STD_LOGIC := '0'; + SIGNAL nl1l0i00i : STD_LOGIC := '0'; + SIGNAL nl1l0i00l : STD_LOGIC := '0'; + SIGNAL nl1l0i00O : STD_LOGIC := '0'; + SIGNAL nl1l0i01i : STD_LOGIC := '0'; + SIGNAL nl1l0i01l : STD_LOGIC := '0'; + SIGNAL nl1l0i01O : STD_LOGIC := '0'; + SIGNAL nl1l0i0ii : STD_LOGIC := '0'; + SIGNAL nl1l0i0il : STD_LOGIC := '0'; + SIGNAL nl1l0i0iO : STD_LOGIC := '0'; + SIGNAL nl1l0i0li : STD_LOGIC := '0'; + SIGNAL nl1l0i0ll : STD_LOGIC := '0'; + SIGNAL nl1l0i0lO : STD_LOGIC := '0'; + SIGNAL nl1l0i0Oi : STD_LOGIC := '0'; + SIGNAL nl1l0i0Ol : STD_LOGIC := '0'; + SIGNAL nl1l0i0OO : STD_LOGIC := '0'; + SIGNAL nl1l0i10i : STD_LOGIC := '0'; + SIGNAL nl1l0i10l : STD_LOGIC := '0'; + SIGNAL nl1l0i10O : STD_LOGIC := '0'; + SIGNAL nl1l0i11i : STD_LOGIC := '0'; + SIGNAL nl1l0i11l : STD_LOGIC := '0'; + SIGNAL nl1l0i11O : STD_LOGIC := '0'; + SIGNAL nl1l0i1ii : STD_LOGIC := '0'; + SIGNAL nl1l0i1il : STD_LOGIC := '0'; + SIGNAL nl1l0i1iO : STD_LOGIC := '0'; + SIGNAL nl1l0i1li : STD_LOGIC := '0'; + SIGNAL nl1l0i1ll : STD_LOGIC := '0'; + SIGNAL nl1l0i1lO : STD_LOGIC := '0'; + SIGNAL nl1l0i1Oi : STD_LOGIC := '0'; + SIGNAL nl1l0i1Ol : STD_LOGIC := '0'; + SIGNAL nl1l0i1OO : STD_LOGIC := '0'; + SIGNAL nl1l0ii0i : STD_LOGIC := '0'; + SIGNAL nl1l0ii0l : STD_LOGIC := '0'; + SIGNAL nl1l0ii0O : STD_LOGIC := '0'; + SIGNAL nl1l0ii1i : STD_LOGIC := '0'; + SIGNAL nl1l0ii1l : STD_LOGIC := '0'; + SIGNAL nl1l0ii1O : STD_LOGIC := '0'; + SIGNAL nl1l0iiii : STD_LOGIC := '0'; + SIGNAL nl1l0iiil : STD_LOGIC := '0'; + SIGNAL nl1l0iiiO : STD_LOGIC := '0'; + SIGNAL nl1l0iili : STD_LOGIC := '0'; + SIGNAL nl1l0iill : STD_LOGIC := '0'; + SIGNAL nl1l0iilO : STD_LOGIC := '0'; + SIGNAL nl1l0iiOi : STD_LOGIC := '0'; + SIGNAL nl1l0iiOl : STD_LOGIC := '0'; + SIGNAL nl1l0iiOO : STD_LOGIC := '0'; + SIGNAL nl1l0il0i : STD_LOGIC := '0'; + SIGNAL nl1l0il0l : STD_LOGIC := '0'; + SIGNAL nl1l0il0O : STD_LOGIC := '0'; + SIGNAL nl1l0il1i : STD_LOGIC := '0'; + SIGNAL nl1l0il1l : STD_LOGIC := '0'; + SIGNAL nl1l0il1O : STD_LOGIC := '0'; + SIGNAL nl1l0ilii : STD_LOGIC := '0'; + SIGNAL nl1l0ilil : STD_LOGIC := '0'; + SIGNAL nl1l0iliO : STD_LOGIC := '0'; + SIGNAL nl1l0illi : STD_LOGIC := '0'; + SIGNAL nl1l0illl : STD_LOGIC := '0'; + SIGNAL nl1l0illO : STD_LOGIC := '0'; + SIGNAL nl1l0ilOi : STD_LOGIC := '0'; + SIGNAL nl1l0ilOl : STD_LOGIC := '0'; + SIGNAL nl1l0ilOO : STD_LOGIC := '0'; + SIGNAL nl1l0iO0i : STD_LOGIC := '0'; + SIGNAL nl1l0iO0l : STD_LOGIC := '0'; + SIGNAL nl1l0iO0O : STD_LOGIC := '0'; + SIGNAL nl1l0iO1i : STD_LOGIC := '0'; + SIGNAL nl1l0iO1l : STD_LOGIC := '0'; + SIGNAL nl1l0iO1O : STD_LOGIC := '0'; + SIGNAL nl1l0iOii : STD_LOGIC := '0'; + SIGNAL nl1l0iOil : STD_LOGIC := '0'; + SIGNAL nl1l0iOiO : STD_LOGIC := '0'; + SIGNAL nl1l0iOli : STD_LOGIC := '0'; + SIGNAL nl1l0iOll : STD_LOGIC := '0'; + SIGNAL nl1l0iOlO : STD_LOGIC := '0'; + SIGNAL nl1l0iOOi : STD_LOGIC := '0'; + SIGNAL nl1l0iOOl : STD_LOGIC := '0'; + SIGNAL nl1l0iOOO : STD_LOGIC := '0'; + SIGNAL nl1l0l00i : STD_LOGIC := '0'; + SIGNAL nl1l0l00l : STD_LOGIC := '0'; + SIGNAL nl1l0l00O : STD_LOGIC := '0'; + SIGNAL nl1l0l01i : STD_LOGIC := '0'; + SIGNAL nl1l0l01l : STD_LOGIC := '0'; + SIGNAL nl1l0l01O : STD_LOGIC := '0'; + SIGNAL nl1l0l0ii : STD_LOGIC := '0'; + SIGNAL nl1l0l0il : STD_LOGIC := '0'; + SIGNAL nl1l0l0iO : STD_LOGIC := '0'; + SIGNAL nl1l0l0li : STD_LOGIC := '0'; + SIGNAL nl1l0l0ll : STD_LOGIC := '0'; + SIGNAL nl1l0l0lO : STD_LOGIC := '0'; + SIGNAL nl1l0l0Oi : STD_LOGIC := '0'; + SIGNAL nl1l0l0Ol : STD_LOGIC := '0'; + SIGNAL nl1l0l0OO : STD_LOGIC := '0'; + SIGNAL nl1l0l10i : STD_LOGIC := '0'; + SIGNAL nl1l0l10l : STD_LOGIC := '0'; + SIGNAL nl1l0l10O : STD_LOGIC := '0'; + SIGNAL nl1l0l11i : STD_LOGIC := '0'; + SIGNAL nl1l0l11l : STD_LOGIC := '0'; + SIGNAL nl1l0l11O : STD_LOGIC := '0'; + SIGNAL nl1l0l1ii : STD_LOGIC := '0'; + SIGNAL nl1l0l1il : STD_LOGIC := '0'; + SIGNAL nl1l0l1iO : STD_LOGIC := '0'; + SIGNAL nl1l0l1li : STD_LOGIC := '0'; + SIGNAL nl1l0l1ll : STD_LOGIC := '0'; + SIGNAL nl1l0l1lO : STD_LOGIC := '0'; + SIGNAL nl1l0l1Oi : STD_LOGIC := '0'; + SIGNAL nl1l0l1Ol : STD_LOGIC := '0'; + SIGNAL nl1l0l1OO : STD_LOGIC := '0'; + SIGNAL nl1l0li0i : STD_LOGIC := '0'; + SIGNAL nl1l0li0l : STD_LOGIC := '0'; + SIGNAL nl1l0li0O : STD_LOGIC := '0'; + SIGNAL nl1l0li1i : STD_LOGIC := '0'; + SIGNAL nl1l0li1l : STD_LOGIC := '0'; + SIGNAL nl1l0li1O : STD_LOGIC := '0'; + SIGNAL nl1l0liii : STD_LOGIC := '0'; + SIGNAL nl1l0liil : STD_LOGIC := '0'; + SIGNAL nl1l0liiO : STD_LOGIC := '0'; + SIGNAL nl1l0lili : STD_LOGIC := '0'; + SIGNAL nl1l0lill : STD_LOGIC := '0'; + SIGNAL nl1l0lilO : STD_LOGIC := '0'; + SIGNAL nl1l0liOi : STD_LOGIC := '0'; + SIGNAL nl1l0liOl : STD_LOGIC := '0'; + SIGNAL nl1l0liOO : STD_LOGIC := '0'; + SIGNAL nl1l0ll0i : STD_LOGIC := '0'; + SIGNAL nl1l0ll0l : STD_LOGIC := '0'; + SIGNAL nl1l0ll0O : STD_LOGIC := '0'; + SIGNAL nl1l0ll1i : STD_LOGIC := '0'; + SIGNAL nl1l0ll1l : STD_LOGIC := '0'; + SIGNAL nl1l0ll1O : STD_LOGIC := '0'; + SIGNAL nl1l0llii : STD_LOGIC := '0'; + SIGNAL nl1l0llil : STD_LOGIC := '0'; + SIGNAL nl1l0lliO : STD_LOGIC := '0'; + SIGNAL nl1l0llli : STD_LOGIC := '0'; + SIGNAL nl1l0llll : STD_LOGIC := '0'; + SIGNAL nl1l0lllO : STD_LOGIC := '0'; + SIGNAL nl1l0llOi : STD_LOGIC := '0'; + SIGNAL nl1l0llOl : STD_LOGIC := '0'; + SIGNAL nl1l0llOO : STD_LOGIC := '0'; + SIGNAL nl1l0lO0i : STD_LOGIC := '0'; + SIGNAL nl1l0lO0l : STD_LOGIC := '0'; + SIGNAL nl1l0lO0O : STD_LOGIC := '0'; + SIGNAL nl1l0lO1i : STD_LOGIC := '0'; + SIGNAL nl1l0lO1l : STD_LOGIC := '0'; + SIGNAL nl1l0lO1O : STD_LOGIC := '0'; + SIGNAL nl1l0lOii : STD_LOGIC := '0'; + SIGNAL nl1l0lOil : STD_LOGIC := '0'; + SIGNAL nl1l0lOiO : STD_LOGIC := '0'; + SIGNAL nl1l0lOli : STD_LOGIC := '0'; + SIGNAL nl1l1ilOO : STD_LOGIC := '0'; + SIGNAL nl1l1iO0i : STD_LOGIC := '0'; + SIGNAL nl1l1iO0l : STD_LOGIC := '0'; + SIGNAL nl1l1iO1i : STD_LOGIC := '0'; + SIGNAL nl1l1iO1l : STD_LOGIC := '0'; + SIGNAL nl1l1iO1O : STD_LOGIC := '0'; + SIGNAL nl1l1iOii : STD_LOGIC := '0'; + SIGNAL nl1l1iOil : STD_LOGIC := '0'; + SIGNAL nl1l1iOiO : STD_LOGIC := '0'; + SIGNAL nl1l1iOli : STD_LOGIC := '0'; + SIGNAL nl1l1iOlO : STD_LOGIC := '0'; + SIGNAL nl1l1iOOi : STD_LOGIC := '0'; + SIGNAL nl1l1iOOl : STD_LOGIC := '0'; + SIGNAL nl1l1iOOO : STD_LOGIC := '0'; + SIGNAL nl1l1l00i : STD_LOGIC := '0'; + SIGNAL nl1l1l00l : STD_LOGIC := '0'; + SIGNAL nl1l1l00O : STD_LOGIC := '0'; + SIGNAL nl1l1l01i : STD_LOGIC := '0'; + SIGNAL nl1l1l01l : STD_LOGIC := '0'; + SIGNAL nl1l1l01O : STD_LOGIC := '0'; + SIGNAL nl1l1l0ii : STD_LOGIC := '0'; + SIGNAL nl1l1l0il : STD_LOGIC := '0'; + SIGNAL nl1l1l0iO : STD_LOGIC := '0'; + SIGNAL nl1l1l0li : STD_LOGIC := '0'; + SIGNAL nl1l1l0ll : STD_LOGIC := '0'; + SIGNAL nl1l1l0lO : STD_LOGIC := '0'; + SIGNAL nl1l1l0Oi : STD_LOGIC := '0'; + SIGNAL nl1l1l0Ol : STD_LOGIC := '0'; + SIGNAL nl1l1l0OO : STD_LOGIC := '0'; + SIGNAL nl1l1l10i : STD_LOGIC := '0'; + SIGNAL nl1l1l10l : STD_LOGIC := '0'; + SIGNAL nl1l1l10O : STD_LOGIC := '0'; + SIGNAL nl1l1l11i : STD_LOGIC := '0'; + SIGNAL nl1l1l11l : STD_LOGIC := '0'; + SIGNAL nl1l1l11O : STD_LOGIC := '0'; + SIGNAL nl1l1l1ii : STD_LOGIC := '0'; + SIGNAL nl1l1l1il : STD_LOGIC := '0'; + SIGNAL nl1l1l1iO : STD_LOGIC := '0'; + SIGNAL nl1l1l1li : STD_LOGIC := '0'; + SIGNAL nl1l1l1ll : STD_LOGIC := '0'; + SIGNAL nl1l1l1lO : STD_LOGIC := '0'; + SIGNAL nl1l1l1Oi : STD_LOGIC := '0'; + SIGNAL nl1l1l1Ol : STD_LOGIC := '0'; + SIGNAL nl1l1l1OO : STD_LOGIC := '0'; + SIGNAL nl1l1li0i : STD_LOGIC := '0'; + SIGNAL nl1l1li0l : STD_LOGIC := '0'; + SIGNAL nl1l1li0O : STD_LOGIC := '0'; + SIGNAL nl1l1li1i : STD_LOGIC := '0'; + SIGNAL nl1l1li1l : STD_LOGIC := '0'; + SIGNAL nl1l1li1O : STD_LOGIC := '0'; + SIGNAL nl1l1liii : STD_LOGIC := '0'; + SIGNAL nl1l1liil : STD_LOGIC := '0'; + SIGNAL nl1l1liiO : STD_LOGIC := '0'; + SIGNAL nl1l1lili : STD_LOGIC := '0'; + SIGNAL nl1l1lill : STD_LOGIC := '0'; + SIGNAL nl1l1lilO : STD_LOGIC := '0'; + SIGNAL nl1l1liOi : STD_LOGIC := '0'; + SIGNAL nl1l1liOl : STD_LOGIC := '0'; + SIGNAL nl1l1liOO : STD_LOGIC := '0'; + SIGNAL nl1l1ll0i : STD_LOGIC := '0'; + SIGNAL nl1l1ll0l : STD_LOGIC := '0'; + SIGNAL nl1l1ll0O : STD_LOGIC := '0'; + SIGNAL nl1l1ll1i : STD_LOGIC := '0'; + SIGNAL nl1l1ll1l : STD_LOGIC := '0'; + SIGNAL nl1l1ll1O : STD_LOGIC := '0'; + SIGNAL nl1l1llii : STD_LOGIC := '0'; + SIGNAL nl1l1llil : STD_LOGIC := '0'; + SIGNAL nl1l1lliO : STD_LOGIC := '0'; + SIGNAL nl1l1llli : STD_LOGIC := '0'; + SIGNAL nl1l1llll : STD_LOGIC := '0'; + SIGNAL nl1l1lllO : STD_LOGIC := '0'; + SIGNAL nl1l1llOi : STD_LOGIC := '0'; + SIGNAL nl1l1llOl : STD_LOGIC := '0'; + SIGNAL nl1l1llOO : STD_LOGIC := '0'; + SIGNAL nl1l1lO0i : STD_LOGIC := '0'; + SIGNAL nl1l1lO0l : STD_LOGIC := '0'; + SIGNAL nl1l1lO0O : STD_LOGIC := '0'; + SIGNAL nl1l1lO1i : STD_LOGIC := '0'; + SIGNAL nl1l1lO1l : STD_LOGIC := '0'; + SIGNAL nl1l1lO1O : STD_LOGIC := '0'; + SIGNAL nl1l1lOii : STD_LOGIC := '0'; + SIGNAL nl1l1lOil : STD_LOGIC := '0'; + SIGNAL nl1l1lOiO : STD_LOGIC := '0'; + SIGNAL nl1l1lOli : STD_LOGIC := '0'; + SIGNAL nl1l1lOll : STD_LOGIC := '0'; + SIGNAL nl1l1lOlO : STD_LOGIC := '0'; + SIGNAL nl1l1lOOi : STD_LOGIC := '0'; + SIGNAL nl1l1lOOl : STD_LOGIC := '0'; + SIGNAL nl1l1lOOO : STD_LOGIC := '0'; + SIGNAL nl1l1O00i : STD_LOGIC := '0'; + SIGNAL nl1l1O00l : STD_LOGIC := '0'; + SIGNAL nl1l1O00O : STD_LOGIC := '0'; + SIGNAL nl1l1O01i : STD_LOGIC := '0'; + SIGNAL nl1l1O01l : STD_LOGIC := '0'; + SIGNAL nl1l1O01O : STD_LOGIC := '0'; + SIGNAL nl1l1O0ii : STD_LOGIC := '0'; + SIGNAL nl1l1O0il : STD_LOGIC := '0'; + SIGNAL nl1l1O0iO : STD_LOGIC := '0'; + SIGNAL nl1l1O0li : STD_LOGIC := '0'; + SIGNAL nl1l1O0ll : STD_LOGIC := '0'; + SIGNAL nl1l1O0lO : STD_LOGIC := '0'; + SIGNAL nl1l1O0Oi : STD_LOGIC := '0'; + SIGNAL nl1l1O0Ol : STD_LOGIC := '0'; + SIGNAL nl1l1O0OO : STD_LOGIC := '0'; + SIGNAL nl1l1O10i : STD_LOGIC := '0'; + SIGNAL nl1l1O10l : STD_LOGIC := '0'; + SIGNAL nl1l1O10O : STD_LOGIC := '0'; + SIGNAL nl1l1O11i : STD_LOGIC := '0'; + SIGNAL nl1l1O11l : STD_LOGIC := '0'; + SIGNAL nl1l1O11O : STD_LOGIC := '0'; + SIGNAL nl1l1O1ii : STD_LOGIC := '0'; + SIGNAL nl1l1O1il : STD_LOGIC := '0'; + SIGNAL nl1l1O1iO : STD_LOGIC := '0'; + SIGNAL nl1l1O1li : STD_LOGIC := '0'; + SIGNAL nl1l1O1ll : STD_LOGIC := '0'; + SIGNAL nl1l1O1lO : STD_LOGIC := '0'; + SIGNAL nl1l1O1Oi : STD_LOGIC := '0'; + SIGNAL nl1l1O1Ol : STD_LOGIC := '0'; + SIGNAL nl1l1O1OO : STD_LOGIC := '0'; + SIGNAL nl1l1Oi0i : STD_LOGIC := '0'; + SIGNAL nl1l1Oi0l : STD_LOGIC := '0'; + SIGNAL nl1l1Oi0O : STD_LOGIC := '0'; + SIGNAL nl1l1Oi1i : STD_LOGIC := '0'; + SIGNAL nl1l1Oi1l : STD_LOGIC := '0'; + SIGNAL nl1l1Oi1O : STD_LOGIC := '0'; + SIGNAL nl1l1Oiii : STD_LOGIC := '0'; + SIGNAL nl1l1Oiil : STD_LOGIC := '0'; + SIGNAL nl1l1OiiO : STD_LOGIC := '0'; + SIGNAL nl1l1Oili : STD_LOGIC := '0'; + SIGNAL nl1l1Oill : STD_LOGIC := '0'; + SIGNAL nl1l1OilO : STD_LOGIC := '0'; + SIGNAL nl1l1OiOi : STD_LOGIC := '0'; + SIGNAL nl1l1OiOl : STD_LOGIC := '0'; + SIGNAL nl1l1OiOO : STD_LOGIC := '0'; + SIGNAL nl1l1Ol0i : STD_LOGIC := '0'; + SIGNAL nl1l1Ol0l : STD_LOGIC := '0'; + SIGNAL nl1l1Ol0O : STD_LOGIC := '0'; + SIGNAL nl1l1Ol1i : STD_LOGIC := '0'; + SIGNAL nl1l1Ol1l : STD_LOGIC := '0'; + SIGNAL nl1l1Ol1O : STD_LOGIC := '0'; + SIGNAL nl1l1Olii : STD_LOGIC := '0'; + SIGNAL nl1l1Olil : STD_LOGIC := '0'; + SIGNAL nl1l1OliO : STD_LOGIC := '0'; + SIGNAL nl1l1Olli : STD_LOGIC := '0'; + SIGNAL nl1l1Olll : STD_LOGIC := '0'; + SIGNAL nl1l1OllO : STD_LOGIC := '0'; + SIGNAL nl1l1OlOi : STD_LOGIC := '0'; + SIGNAL nl1l1OlOl : STD_LOGIC := '0'; + SIGNAL nl1l1OlOO : STD_LOGIC := '0'; + SIGNAL nl1l1OO0i : STD_LOGIC := '0'; + SIGNAL nl1l1OO0l : STD_LOGIC := '0'; + SIGNAL nl1l1OO0O : STD_LOGIC := '0'; + SIGNAL nl1l1OO1i : STD_LOGIC := '0'; + SIGNAL nl1l1OO1l : STD_LOGIC := '0'; + SIGNAL nl1l1OO1O : STD_LOGIC := '0'; + SIGNAL nl1l1OOii : STD_LOGIC := '0'; + SIGNAL nl1l1OOil : STD_LOGIC := '0'; + SIGNAL nl1l1OOiO : STD_LOGIC := '0'; + SIGNAL nl1l1OOli : STD_LOGIC := '0'; + SIGNAL nl1l1OOll : STD_LOGIC := '0'; + SIGNAL nl1l1OOlO : STD_LOGIC := '0'; + SIGNAL nl1l1OOOi : STD_LOGIC := '0'; + SIGNAL nl1l1OOOl : STD_LOGIC := '0'; + SIGNAL nl1l1OOOO : STD_LOGIC := '0'; + SIGNAL nl1ll0iil : STD_LOGIC := '0'; + SIGNAL nl1ll0iiO : STD_LOGIC := '0'; + SIGNAL nl1ll0ili : STD_LOGIC := '0'; + SIGNAL nl1ll0ill : STD_LOGIC := '0'; + SIGNAL nl1ll0ilO : STD_LOGIC := '0'; + SIGNAL nl1ll0iOi : STD_LOGIC := '0'; + SIGNAL nl1ll0iOl : STD_LOGIC := '0'; + SIGNAL nl1ll0l0i : STD_LOGIC := '0'; + SIGNAL nl1ll0l0l : STD_LOGIC := '0'; + SIGNAL nl1ll0l0O : STD_LOGIC := '0'; + SIGNAL nl1ll0l1i : STD_LOGIC := '0'; + SIGNAL nl1ll0l1l : STD_LOGIC := '0'; + SIGNAL nl1ll0l1O : STD_LOGIC := '0'; + SIGNAL nl1ll0lii : STD_LOGIC := '0'; + SIGNAL nl1ll0lil : STD_LOGIC := '0'; + SIGNAL nl1ll0liO : STD_LOGIC := '0'; + SIGNAL nl1ll0lli : STD_LOGIC := '0'; + SIGNAL nl1ll0lll : STD_LOGIC := '0'; + SIGNAL nl1ll0llO : STD_LOGIC := '0'; + SIGNAL nl1ll0lOi : STD_LOGIC := '0'; + SIGNAL nl1ll0lOl : STD_LOGIC := '0'; + SIGNAL nl1ll0lOO : STD_LOGIC := '0'; + SIGNAL nl1lO1iiO : STD_LOGIC := '0'; + SIGNAL nl1lO1ilO : STD_LOGIC := '0'; + SIGNAL nl1O0000i : STD_LOGIC := '0'; + SIGNAL nl1O0000l : STD_LOGIC := '0'; + SIGNAL nl1O0000O : STD_LOGIC := '0'; + SIGNAL nl1O0001i : STD_LOGIC := '0'; + SIGNAL nl1O0001l : STD_LOGIC := '0'; + SIGNAL nl1O0001O : STD_LOGIC := '0'; + SIGNAL nl1O000ii : STD_LOGIC := '0'; + SIGNAL nl1O000il : STD_LOGIC := '0'; + SIGNAL nl1O000iO : STD_LOGIC := '0'; + SIGNAL nl1O000li : STD_LOGIC := '0'; + SIGNAL nl1O000ll : STD_LOGIC := '0'; + SIGNAL nl1O000lO : STD_LOGIC := '0'; + SIGNAL nl1O000Oi : STD_LOGIC := '0'; + SIGNAL nl1O000Ol : STD_LOGIC := '0'; + SIGNAL nl1O000OO : STD_LOGIC := '0'; + SIGNAL nl1O0010i : STD_LOGIC := '0'; + SIGNAL nl1O0010l : STD_LOGIC := '0'; + SIGNAL nl1O0010O : STD_LOGIC := '0'; + SIGNAL nl1O0011i : STD_LOGIC := '0'; + SIGNAL nl1O0011l : STD_LOGIC := '0'; + SIGNAL nl1O0011O : STD_LOGIC := '0'; + SIGNAL nl1O001ii : STD_LOGIC := '0'; + SIGNAL nl1O001il : STD_LOGIC := '0'; + SIGNAL nl1O001iO : STD_LOGIC := '0'; + SIGNAL nl1O001li : STD_LOGIC := '0'; + SIGNAL nl1O001ll : STD_LOGIC := '0'; + SIGNAL nl1O001lO : STD_LOGIC := '0'; + SIGNAL nl1O001Oi : STD_LOGIC := '0'; + SIGNAL nl1O001Ol : STD_LOGIC := '0'; + SIGNAL nl1O001OO : STD_LOGIC := '0'; + SIGNAL nl1O00i0i : STD_LOGIC := '0'; + SIGNAL nl1O00i0l : STD_LOGIC := '0'; + SIGNAL nl1O00i0O : STD_LOGIC := '0'; + SIGNAL nl1O00i1i : STD_LOGIC := '0'; + SIGNAL nl1O00i1l : STD_LOGIC := '0'; + SIGNAL nl1O00i1O : STD_LOGIC := '0'; + SIGNAL nl1O00iii : STD_LOGIC := '0'; + SIGNAL nl1O00iil : STD_LOGIC := '0'; + SIGNAL nl1O00iiO : STD_LOGIC := '0'; + SIGNAL nl1O00ili : STD_LOGIC := '0'; + SIGNAL nl1O00ill : STD_LOGIC := '0'; + SIGNAL nl1O00ilO : STD_LOGIC := '0'; + SIGNAL nl1O00iOi : STD_LOGIC := '0'; + SIGNAL nl1O00iOl : STD_LOGIC := '0'; + SIGNAL nl1O00iOO : STD_LOGIC := '0'; + SIGNAL nl1O00l0i : STD_LOGIC := '0'; + SIGNAL nl1O00l0l : STD_LOGIC := '0'; + SIGNAL nl1O00l0O : STD_LOGIC := '0'; + SIGNAL nl1O00l1i : STD_LOGIC := '0'; + SIGNAL nl1O00l1l : STD_LOGIC := '0'; + SIGNAL nl1O00l1O : STD_LOGIC := '0'; + SIGNAL nl1O00lii : STD_LOGIC := '0'; + SIGNAL nl1O00lil : STD_LOGIC := '0'; + SIGNAL nl1O00liO : STD_LOGIC := '0'; + SIGNAL nl1O00lli : STD_LOGIC := '0'; + SIGNAL nl1O00lll : STD_LOGIC := '0'; + SIGNAL nl1O00llO : STD_LOGIC := '0'; + SIGNAL nl1O00lOi : STD_LOGIC := '0'; + SIGNAL nl1O00lOl : STD_LOGIC := '0'; + SIGNAL nl1O00lOO : STD_LOGIC := '0'; + SIGNAL nl1O00O0i : STD_LOGIC := '0'; + SIGNAL nl1O00O0l : STD_LOGIC := '0'; + SIGNAL nl1O00O0O : STD_LOGIC := '0'; + SIGNAL nl1O00O1i : STD_LOGIC := '0'; + SIGNAL nl1O00O1l : STD_LOGIC := '0'; + SIGNAL nl1O00O1O : STD_LOGIC := '0'; + SIGNAL nl1O00Oii : STD_LOGIC := '0'; + SIGNAL nl1O00Oil : STD_LOGIC := '0'; + SIGNAL nl1O00OiO : STD_LOGIC := '0'; + SIGNAL nl1O00Oli : STD_LOGIC := '0'; + SIGNAL nl1O00Oll : STD_LOGIC := '0'; + SIGNAL nl1O00OlO : STD_LOGIC := '0'; + SIGNAL nl1O00OOi : STD_LOGIC := '0'; + SIGNAL nl1O00OOl : STD_LOGIC := '0'; + SIGNAL nl1O00OOO : STD_LOGIC := '0'; + SIGNAL nl1O0100i : STD_LOGIC := '0'; + SIGNAL nl1O0100l : STD_LOGIC := '0'; + SIGNAL nl1O0100O : STD_LOGIC := '0'; + SIGNAL nl1O0101i : STD_LOGIC := '0'; + SIGNAL nl1O0101l : STD_LOGIC := '0'; + SIGNAL nl1O0101O : STD_LOGIC := '0'; + SIGNAL nl1O010ii : STD_LOGIC := '0'; + SIGNAL nl1O010il : STD_LOGIC := '0'; + SIGNAL nl1O010iO : STD_LOGIC := '0'; + SIGNAL nl1O010li : STD_LOGIC := '0'; + SIGNAL nl1O010ll : STD_LOGIC := '0'; + SIGNAL nl1O010lO : STD_LOGIC := '0'; + SIGNAL nl1O010Oi : STD_LOGIC := '0'; + SIGNAL nl1O010Ol : STD_LOGIC := '0'; + SIGNAL nl1O010OO : STD_LOGIC := '0'; + SIGNAL nl1O0110i : STD_LOGIC := '0'; + SIGNAL nl1O0110l : STD_LOGIC := '0'; + SIGNAL nl1O0110O : STD_LOGIC := '0'; + SIGNAL nl1O0111i : STD_LOGIC := '0'; + SIGNAL nl1O0111l : STD_LOGIC := '0'; + SIGNAL nl1O0111O : STD_LOGIC := '0'; + SIGNAL nl1O011ii : STD_LOGIC := '0'; + SIGNAL nl1O011il : STD_LOGIC := '0'; + SIGNAL nl1O011iO : STD_LOGIC := '0'; + SIGNAL nl1O011li : STD_LOGIC := '0'; + SIGNAL nl1O011ll : STD_LOGIC := '0'; + SIGNAL nl1O011lO : STD_LOGIC := '0'; + SIGNAL nl1O011Oi : STD_LOGIC := '0'; + SIGNAL nl1O011Ol : STD_LOGIC := '0'; + SIGNAL nl1O011OO : STD_LOGIC := '0'; + SIGNAL nl1O01i0i : STD_LOGIC := '0'; + SIGNAL nl1O01i0l : STD_LOGIC := '0'; + SIGNAL nl1O01i0O : STD_LOGIC := '0'; + SIGNAL nl1O01i1i : STD_LOGIC := '0'; + SIGNAL nl1O01i1l : STD_LOGIC := '0'; + SIGNAL nl1O01i1O : STD_LOGIC := '0'; + SIGNAL nl1O01iii : STD_LOGIC := '0'; + SIGNAL nl1O01iil : STD_LOGIC := '0'; + SIGNAL nl1O01iiO : STD_LOGIC := '0'; + SIGNAL nl1O01ili : STD_LOGIC := '0'; + SIGNAL nl1O01ill : STD_LOGIC := '0'; + SIGNAL nl1O01ilO : STD_LOGIC := '0'; + SIGNAL nl1O01iOi : STD_LOGIC := '0'; + SIGNAL nl1O01iOl : STD_LOGIC := '0'; + SIGNAL nl1O01iOO : STD_LOGIC := '0'; + SIGNAL nl1O01l0i : STD_LOGIC := '0'; + SIGNAL nl1O01l0l : STD_LOGIC := '0'; + SIGNAL nl1O01l0O : STD_LOGIC := '0'; + SIGNAL nl1O01l1i : STD_LOGIC := '0'; + SIGNAL nl1O01l1l : STD_LOGIC := '0'; + SIGNAL nl1O01l1O : STD_LOGIC := '0'; + SIGNAL nl1O01lii : STD_LOGIC := '0'; + SIGNAL nl1O01lil : STD_LOGIC := '0'; + SIGNAL nl1O01liO : STD_LOGIC := '0'; + SIGNAL nl1O01lli : STD_LOGIC := '0'; + SIGNAL nl1O01lll : STD_LOGIC := '0'; + SIGNAL nl1O01llO : STD_LOGIC := '0'; + SIGNAL nl1O01lOi : STD_LOGIC := '0'; + SIGNAL nl1O01lOl : STD_LOGIC := '0'; + SIGNAL nl1O01lOO : STD_LOGIC := '0'; + SIGNAL nl1O01O0i : STD_LOGIC := '0'; + SIGNAL nl1O01O0l : STD_LOGIC := '0'; + SIGNAL nl1O01O0O : STD_LOGIC := '0'; + SIGNAL nl1O01O1i : STD_LOGIC := '0'; + SIGNAL nl1O01O1l : STD_LOGIC := '0'; + SIGNAL nl1O01O1O : STD_LOGIC := '0'; + SIGNAL nl1O01Oii : STD_LOGIC := '0'; + SIGNAL nl1O01Oil : STD_LOGIC := '0'; + SIGNAL nl1O01OiO : STD_LOGIC := '0'; + SIGNAL nl1O01Oli : STD_LOGIC := '0'; + SIGNAL nl1O01Oll : STD_LOGIC := '0'; + SIGNAL nl1O01OlO : STD_LOGIC := '0'; + SIGNAL nl1O01OOi : STD_LOGIC := '0'; + SIGNAL nl1O01OOl : STD_LOGIC := '0'; + SIGNAL nl1O01OOO : STD_LOGIC := '0'; + SIGNAL nl1O0i00i : STD_LOGIC := '0'; + SIGNAL nl1O0i00l : STD_LOGIC := '0'; + SIGNAL nl1O0i00O : STD_LOGIC := '0'; + SIGNAL nl1O0i01i : STD_LOGIC := '0'; + SIGNAL nl1O0i01l : STD_LOGIC := '0'; + SIGNAL nl1O0i01O : STD_LOGIC := '0'; + SIGNAL nl1O0i0ii : STD_LOGIC := '0'; + SIGNAL nl1O0i0il : STD_LOGIC := '0'; + SIGNAL nl1O0i0iO : STD_LOGIC := '0'; + SIGNAL nl1O0i0li : STD_LOGIC := '0'; + SIGNAL nl1O0i0ll : STD_LOGIC := '0'; + SIGNAL nl1O0i0lO : STD_LOGIC := '0'; + SIGNAL nl1O0i0Oi : STD_LOGIC := '0'; + SIGNAL nl1O0i0Ol : STD_LOGIC := '0'; + SIGNAL nl1O0i0OO : STD_LOGIC := '0'; + SIGNAL nl1O0i10i : STD_LOGIC := '0'; + SIGNAL nl1O0i10l : STD_LOGIC := '0'; + SIGNAL nl1O0i10O : STD_LOGIC := '0'; + SIGNAL nl1O0i11i : STD_LOGIC := '0'; + SIGNAL nl1O0i11l : STD_LOGIC := '0'; + SIGNAL nl1O0i11O : STD_LOGIC := '0'; + SIGNAL nl1O0i1ii : STD_LOGIC := '0'; + SIGNAL nl1O0i1il : STD_LOGIC := '0'; + SIGNAL nl1O0i1iO : STD_LOGIC := '0'; + SIGNAL nl1O0i1li : STD_LOGIC := '0'; + SIGNAL nl1O0i1ll : STD_LOGIC := '0'; + SIGNAL nl1O0i1lO : STD_LOGIC := '0'; + SIGNAL nl1O0i1Oi : STD_LOGIC := '0'; + SIGNAL nl1O0i1Ol : STD_LOGIC := '0'; + SIGNAL nl1O0i1OO : STD_LOGIC := '0'; + SIGNAL nl1O0ii0i : STD_LOGIC := '0'; + SIGNAL nl1O0ii0l : STD_LOGIC := '0'; + SIGNAL nl1O0ii0O : STD_LOGIC := '0'; + SIGNAL nl1O0ii1i : STD_LOGIC := '0'; + SIGNAL nl1O0ii1l : STD_LOGIC := '0'; + SIGNAL nl1O0ii1O : STD_LOGIC := '0'; + SIGNAL nl1O0iiii : STD_LOGIC := '0'; + SIGNAL nl1O1i0OO : STD_LOGIC := '0'; + SIGNAL nl1O1ii0i : STD_LOGIC := '0'; + SIGNAL nl1O1ii0l : STD_LOGIC := '0'; + SIGNAL nl1O1ii0O : STD_LOGIC := '0'; + SIGNAL nl1O1ii1i : STD_LOGIC := '0'; + SIGNAL nl1O1ii1l : STD_LOGIC := '0'; + SIGNAL nl1O1ii1O : STD_LOGIC := '0'; + SIGNAL nl1O1iiii : STD_LOGIC := '0'; + SIGNAL nl1O1iiil : STD_LOGIC := '0'; + SIGNAL nl1O1iiiO : STD_LOGIC := '0'; + SIGNAL nl1O1iili : STD_LOGIC := '0'; + SIGNAL nl1O1iill : STD_LOGIC := '0'; + SIGNAL nl1O1iilO : STD_LOGIC := '0'; + SIGNAL nl1O1iiOi : STD_LOGIC := '0'; + SIGNAL nl1O1iiOl : STD_LOGIC := '0'; + SIGNAL nl1O1iiOO : STD_LOGIC := '0'; + SIGNAL nl1O1il0i : STD_LOGIC := '0'; + SIGNAL nl1O1il0l : STD_LOGIC := '0'; + SIGNAL nl1O1il0O : STD_LOGIC := '0'; + SIGNAL nl1O1il1i : STD_LOGIC := '0'; + SIGNAL nl1O1il1l : STD_LOGIC := '0'; + SIGNAL nl1O1il1O : STD_LOGIC := '0'; + SIGNAL nl1O1ilii : STD_LOGIC := '0'; + SIGNAL nl1O1ilil : STD_LOGIC := '0'; + SIGNAL nl1O1iliO : STD_LOGIC := '0'; + SIGNAL nl1O1illi : STD_LOGIC := '0'; + SIGNAL nl1O1illl : STD_LOGIC := '0'; + SIGNAL nl1O1illO : STD_LOGIC := '0'; + SIGNAL nl1O1ilOi : STD_LOGIC := '0'; + SIGNAL nl1O1ilOl : STD_LOGIC := '0'; + SIGNAL nl1O1ilOO : STD_LOGIC := '0'; + SIGNAL nl1O1iO0i : STD_LOGIC := '0'; + SIGNAL nl1O1iO0l : STD_LOGIC := '0'; + SIGNAL nl1O1iO0O : STD_LOGIC := '0'; + SIGNAL nl1O1iO1i : STD_LOGIC := '0'; + SIGNAL nl1O1iO1l : STD_LOGIC := '0'; + SIGNAL nl1O1iO1O : STD_LOGIC := '0'; + SIGNAL nl1O1iOii : STD_LOGIC := '0'; + SIGNAL nl1O1iOil : STD_LOGIC := '0'; + SIGNAL nl1O1iOiO : STD_LOGIC := '0'; + SIGNAL nl1O1iOli : STD_LOGIC := '0'; + SIGNAL nl1O1iOll : STD_LOGIC := '0'; + SIGNAL nl1O1iOlO : STD_LOGIC := '0'; + SIGNAL nl1O1iOOi : STD_LOGIC := '0'; + SIGNAL nl1O1iOOl : STD_LOGIC := '0'; + SIGNAL nl1O1iOOO : STD_LOGIC := '0'; + SIGNAL nl1O1l00i : STD_LOGIC := '0'; + SIGNAL nl1O1l00l : STD_LOGIC := '0'; + SIGNAL nl1O1l00O : STD_LOGIC := '0'; + SIGNAL nl1O1l01i : STD_LOGIC := '0'; + SIGNAL nl1O1l01l : STD_LOGIC := '0'; + SIGNAL nl1O1l01O : STD_LOGIC := '0'; + SIGNAL nl1O1l0ii : STD_LOGIC := '0'; + SIGNAL nl1O1l0il : STD_LOGIC := '0'; + SIGNAL nl1O1l0iO : STD_LOGIC := '0'; + SIGNAL nl1O1l0li : STD_LOGIC := '0'; + SIGNAL nl1O1l0ll : STD_LOGIC := '0'; + SIGNAL nl1O1l0lO : STD_LOGIC := '0'; + SIGNAL nl1O1l0Oi : STD_LOGIC := '0'; + SIGNAL nl1O1l0Ol : STD_LOGIC := '0'; + SIGNAL nl1O1l0OO : STD_LOGIC := '0'; + SIGNAL nl1O1l10i : STD_LOGIC := '0'; + SIGNAL nl1O1l10l : STD_LOGIC := '0'; + SIGNAL nl1O1l10O : STD_LOGIC := '0'; + SIGNAL nl1O1l11i : STD_LOGIC := '0'; + SIGNAL nl1O1l11l : STD_LOGIC := '0'; + SIGNAL nl1O1l11O : STD_LOGIC := '0'; + SIGNAL nl1O1l1ii : STD_LOGIC := '0'; + SIGNAL nl1O1l1il : STD_LOGIC := '0'; + SIGNAL nl1O1l1iO : STD_LOGIC := '0'; + SIGNAL nl1O1l1li : STD_LOGIC := '0'; + SIGNAL nl1O1l1ll : STD_LOGIC := '0'; + SIGNAL nl1O1l1lO : STD_LOGIC := '0'; + SIGNAL nl1O1l1Oi : STD_LOGIC := '0'; + SIGNAL nl1O1l1Ol : STD_LOGIC := '0'; + SIGNAL nl1O1l1OO : STD_LOGIC := '0'; + SIGNAL nl1O1li0i : STD_LOGIC := '0'; + SIGNAL nl1O1li0l : STD_LOGIC := '0'; + SIGNAL nl1O1li0O : STD_LOGIC := '0'; + SIGNAL nl1O1li1i : STD_LOGIC := '0'; + SIGNAL nl1O1li1l : STD_LOGIC := '0'; + SIGNAL nl1O1li1O : STD_LOGIC := '0'; + SIGNAL nl1O1liii : STD_LOGIC := '0'; + SIGNAL nl1O1liil : STD_LOGIC := '0'; + SIGNAL nl1O1liiO : STD_LOGIC := '0'; + SIGNAL nl1O1lili : STD_LOGIC := '0'; + SIGNAL nl1O1lill : STD_LOGIC := '0'; + SIGNAL nl1O1lilO : STD_LOGIC := '0'; + SIGNAL nl1O1liOi : STD_LOGIC := '0'; + SIGNAL nl1O1liOl : STD_LOGIC := '0'; + SIGNAL nl1O1liOO : STD_LOGIC := '0'; + SIGNAL nl1O1ll0i : STD_LOGIC := '0'; + SIGNAL nl1O1ll0l : STD_LOGIC := '0'; + SIGNAL nl1O1ll0O : STD_LOGIC := '0'; + SIGNAL nl1O1ll1i : STD_LOGIC := '0'; + SIGNAL nl1O1ll1l : STD_LOGIC := '0'; + SIGNAL nl1O1ll1O : STD_LOGIC := '0'; + SIGNAL nl1O1llii : STD_LOGIC := '0'; + SIGNAL nl1O1llil : STD_LOGIC := '0'; + SIGNAL nl1O1lliO : STD_LOGIC := '0'; + SIGNAL nl1O1llli : STD_LOGIC := '0'; + SIGNAL nl1O1llll : STD_LOGIC := '0'; + SIGNAL nl1O1lllO : STD_LOGIC := '0'; + SIGNAL nl1O1llOi : STD_LOGIC := '0'; + SIGNAL nl1O1llOl : STD_LOGIC := '0'; + SIGNAL nl1O1llOO : STD_LOGIC := '0'; + SIGNAL nl1O1lO0i : STD_LOGIC := '0'; + SIGNAL nl1O1lO0l : STD_LOGIC := '0'; + SIGNAL nl1O1lO0O : STD_LOGIC := '0'; + SIGNAL nl1O1lO1i : STD_LOGIC := '0'; + SIGNAL nl1O1lO1l : STD_LOGIC := '0'; + SIGNAL nl1O1lO1O : STD_LOGIC := '0'; + SIGNAL nl1O1lOii : STD_LOGIC := '0'; + SIGNAL nl1O1lOil : STD_LOGIC := '0'; + SIGNAL nl1O1lOiO : STD_LOGIC := '0'; + SIGNAL nl1O1lOli : STD_LOGIC := '0'; + SIGNAL nl1O1lOll : STD_LOGIC := '0'; + SIGNAL nl1O1lOlO : STD_LOGIC := '0'; + SIGNAL nl1O1lOOi : STD_LOGIC := '0'; + SIGNAL nl1O1lOOl : STD_LOGIC := '0'; + SIGNAL nl1O1lOOO : STD_LOGIC := '0'; + SIGNAL nl1O1O00i : STD_LOGIC := '0'; + SIGNAL nl1O1O00l : STD_LOGIC := '0'; + SIGNAL nl1O1O00O : STD_LOGIC := '0'; + SIGNAL nl1O1O01i : STD_LOGIC := '0'; + SIGNAL nl1O1O01l : STD_LOGIC := '0'; + SIGNAL nl1O1O01O : STD_LOGIC := '0'; + SIGNAL nl1O1O0ii : STD_LOGIC := '0'; + SIGNAL nl1O1O0il : STD_LOGIC := '0'; + SIGNAL nl1O1O0iO : STD_LOGIC := '0'; + SIGNAL nl1O1O0li : STD_LOGIC := '0'; + SIGNAL nl1O1O0ll : STD_LOGIC := '0'; + SIGNAL nl1O1O0lO : STD_LOGIC := '0'; + SIGNAL nl1O1O0Oi : STD_LOGIC := '0'; + SIGNAL nl1O1O0Ol : STD_LOGIC := '0'; + SIGNAL nl1O1O0OO : STD_LOGIC := '0'; + SIGNAL nl1O1O10i : STD_LOGIC := '0'; + SIGNAL nl1O1O10l : STD_LOGIC := '0'; + SIGNAL nl1O1O10O : STD_LOGIC := '0'; + SIGNAL nl1O1O11i : STD_LOGIC := '0'; + SIGNAL nl1O1O11l : STD_LOGIC := '0'; + SIGNAL nl1O1O11O : STD_LOGIC := '0'; + SIGNAL nl1O1O1ii : STD_LOGIC := '0'; + SIGNAL nl1O1O1il : STD_LOGIC := '0'; + SIGNAL nl1O1O1iO : STD_LOGIC := '0'; + SIGNAL nl1O1O1li : STD_LOGIC := '0'; + SIGNAL nl1O1O1ll : STD_LOGIC := '0'; + SIGNAL nl1O1O1lO : STD_LOGIC := '0'; + SIGNAL nl1O1O1Oi : STD_LOGIC := '0'; + SIGNAL nl1O1O1Ol : STD_LOGIC := '0'; + SIGNAL nl1O1O1OO : STD_LOGIC := '0'; + SIGNAL nl1O1Oi0i : STD_LOGIC := '0'; + SIGNAL nl1O1Oi0l : STD_LOGIC := '0'; + SIGNAL nl1O1Oi0O : STD_LOGIC := '0'; + SIGNAL nl1O1Oi1i : STD_LOGIC := '0'; + SIGNAL nl1O1Oi1l : STD_LOGIC := '0'; + SIGNAL nl1O1Oi1O : STD_LOGIC := '0'; + SIGNAL nl1O1Oiii : STD_LOGIC := '0'; + SIGNAL nl1O1Oiil : STD_LOGIC := '0'; + SIGNAL nl1O1OiiO : STD_LOGIC := '0'; + SIGNAL nl1O1Oili : STD_LOGIC := '0'; + SIGNAL nl1O1Oill : STD_LOGIC := '0'; + SIGNAL nl1O1OilO : STD_LOGIC := '0'; + SIGNAL nl1O1OiOi : STD_LOGIC := '0'; + SIGNAL nl1O1OiOl : STD_LOGIC := '0'; + SIGNAL nl1O1OiOO : STD_LOGIC := '0'; + SIGNAL nl1O1Ol0i : STD_LOGIC := '0'; + SIGNAL nl1O1Ol0l : STD_LOGIC := '0'; + SIGNAL nl1O1Ol0O : STD_LOGIC := '0'; + SIGNAL nl1O1Ol1i : STD_LOGIC := '0'; + SIGNAL nl1O1Ol1l : STD_LOGIC := '0'; + SIGNAL nl1O1Ol1O : STD_LOGIC := '0'; + SIGNAL nl1O1Olii : STD_LOGIC := '0'; + SIGNAL nl1O1Olil : STD_LOGIC := '0'; + SIGNAL nl1O1OliO : STD_LOGIC := '0'; + SIGNAL nl1O1Olli : STD_LOGIC := '0'; + SIGNAL nl1O1Olll : STD_LOGIC := '0'; + SIGNAL nl1O1OllO : STD_LOGIC := '0'; + SIGNAL nl1O1OlOi : STD_LOGIC := '0'; + SIGNAL nl1O1OlOl : STD_LOGIC := '0'; + SIGNAL nl1O1OlOO : STD_LOGIC := '0'; + SIGNAL nl1O1OO0i : STD_LOGIC := '0'; + SIGNAL nl1O1OO0l : STD_LOGIC := '0'; + SIGNAL nl1O1OO0O : STD_LOGIC := '0'; + SIGNAL nl1O1OO1i : STD_LOGIC := '0'; + SIGNAL nl1O1OO1l : STD_LOGIC := '0'; + SIGNAL nl1O1OO1O : STD_LOGIC := '0'; + SIGNAL nl1O1OOii : STD_LOGIC := '0'; + SIGNAL nl1O1OOil : STD_LOGIC := '0'; + SIGNAL nl1O1OOiO : STD_LOGIC := '0'; + SIGNAL nl1O1OOli : STD_LOGIC := '0'; + SIGNAL nl1O1OOll : STD_LOGIC := '0'; + SIGNAL nl1O1OOlO : STD_LOGIC := '0'; + SIGNAL nl1O1OOOi : STD_LOGIC := '0'; + SIGNAL nl1O1OOOl : STD_LOGIC := '0'; + SIGNAL nl1O1OOOO : STD_LOGIC := '0'; + SIGNAL nl1Oill0l : STD_LOGIC := '0'; + SIGNAL nl1Oill0O : STD_LOGIC := '0'; + SIGNAL nl1Oillii : STD_LOGIC := '0'; + SIGNAL nl1Oillil : STD_LOGIC := '0'; + SIGNAL nl1OilliO : STD_LOGIC := '0'; + SIGNAL nl1Oillli : STD_LOGIC := '0'; + SIGNAL nl1Oillll : STD_LOGIC := '0'; + SIGNAL nl1OilllO : STD_LOGIC := '0'; + SIGNAL nl1OillOi : STD_LOGIC := '0'; + SIGNAL nl1OillOl : STD_LOGIC := '0'; + SIGNAL nl1OillOO : STD_LOGIC := '0'; + SIGNAL nl1OilO0l : STD_LOGIC := '0'; + SIGNAL nl1OilO0O : STD_LOGIC := '0'; + SIGNAL nl1OilO1i : STD_LOGIC := '0'; + SIGNAL nl1OilO1l : STD_LOGIC := '0'; + SIGNAL nl1OilO1O : STD_LOGIC := '0'; + SIGNAL nl1OilOii : STD_LOGIC := '0'; + SIGNAL nl1OilOil : STD_LOGIC := '0'; + SIGNAL nl1Ol011i : STD_LOGIC := '0'; + SIGNAL nl1Ol011l : STD_LOGIC := '0'; + SIGNAL nl1Ol011O : STD_LOGIC := '0'; + SIGNAL nl1Ol1l0i : STD_LOGIC := '0'; + SIGNAL nl1Ol1l0l : STD_LOGIC := '0'; + SIGNAL nl1Ol1l0O : STD_LOGIC := '0'; + SIGNAL nl1Ol1lii : STD_LOGIC := '0'; + SIGNAL nl1Ol1lil : STD_LOGIC := '0'; + SIGNAL nl1Ol1liO : STD_LOGIC := '0'; + SIGNAL nl1Ol1lli : STD_LOGIC := '0'; + SIGNAL nl1Ol1lll : STD_LOGIC := '0'; + SIGNAL nl1Ol1llO : STD_LOGIC := '0'; + SIGNAL nl1Ol1lOi : STD_LOGIC := '0'; + SIGNAL nl1Ol1lOl : STD_LOGIC := '0'; + SIGNAL nl1Ol1lOO : STD_LOGIC := '0'; + SIGNAL nl1Ol1O0i : STD_LOGIC := '0'; + SIGNAL nl1Ol1O0l : STD_LOGIC := '0'; + SIGNAL nl1Ol1O0O : STD_LOGIC := '0'; + SIGNAL nl1Ol1O1i : STD_LOGIC := '0'; + SIGNAL nl1Ol1O1l : STD_LOGIC := '0'; + SIGNAL nl1Ol1O1O : STD_LOGIC := '0'; + SIGNAL nl1Ol1Oii : STD_LOGIC := '0'; + SIGNAL nl1Ol1Oil : STD_LOGIC := '0'; + SIGNAL nl1Ol1OiO : STD_LOGIC := '0'; + SIGNAL nl1Ol1Oli : STD_LOGIC := '0'; + SIGNAL nl1Ol1Oll : STD_LOGIC := '0'; + SIGNAL nl1Ol1OlO : STD_LOGIC := '0'; + SIGNAL nl1Ol1OOi : STD_LOGIC := '0'; + SIGNAL nl1Ol1OOl : STD_LOGIC := '0'; + SIGNAL nl1Ol1OOO : STD_LOGIC := '0'; + SIGNAL nl1OllOOl : STD_LOGIC := '0'; + SIGNAL nl1OllOOO : STD_LOGIC := '0'; + SIGNAL nl1OlO11i : STD_LOGIC := '0'; + SIGNAL nl1OlO11l : STD_LOGIC := '0'; + SIGNAL nl1OlO11O : STD_LOGIC := '0'; + SIGNAL nl1OO010i : STD_LOGIC := '0'; + SIGNAL nl1OO010l : STD_LOGIC := '0'; + SIGNAL nl1OO010O : STD_LOGIC := '0'; + SIGNAL nl1OO011i : STD_LOGIC := '0'; + SIGNAL nl1OO011l : STD_LOGIC := '0'; + SIGNAL nl1OO011O : STD_LOGIC := '0'; + SIGNAL nl1OO1O0i : STD_LOGIC := '0'; + SIGNAL nl1OO1O0l : STD_LOGIC := '0'; + SIGNAL nl1OO1O0O : STD_LOGIC := '0'; + SIGNAL nl1OO1O1l : STD_LOGIC := '0'; + SIGNAL nl1OO1O1O : STD_LOGIC := '0'; + SIGNAL nl1OO1Oii : STD_LOGIC := '0'; + SIGNAL nl1OO1Oil : STD_LOGIC := '0'; + SIGNAL nl1OO1OiO : STD_LOGIC := '0'; + SIGNAL nl1OO1Oli : STD_LOGIC := '0'; + SIGNAL nl1OO1Oll : STD_LOGIC := '0'; + SIGNAL nl1OO1OlO : STD_LOGIC := '0'; + SIGNAL nl1OO1OOi : STD_LOGIC := '0'; + SIGNAL nl1OO1OOl : STD_LOGIC := '0'; + SIGNAL nl1OO1OOO : STD_LOGIC := '0'; + SIGNAL nl1OOi00i : STD_LOGIC := '0'; + SIGNAL nl1OOi00l : STD_LOGIC := '0'; + SIGNAL nl1OOi00O : STD_LOGIC := '0'; + SIGNAL nl1OOi01i : STD_LOGIC := '0'; + SIGNAL nl1OOi01l : STD_LOGIC := '0'; + SIGNAL nl1OOi01O : STD_LOGIC := '0'; + SIGNAL nl1OOi0ii : STD_LOGIC := '0'; + SIGNAL nl1OOi0il : STD_LOGIC := '0'; + SIGNAL nl1OOi0iO : STD_LOGIC := '0'; + SIGNAL nl1OOi0li : STD_LOGIC := '0'; + SIGNAL nl1OOi0ll : STD_LOGIC := '0'; + SIGNAL nl1OOi0lO : STD_LOGIC := '0'; + SIGNAL nl1OOi0Oi : STD_LOGIC := '0'; + SIGNAL nl1OOi0Ol : STD_LOGIC := '0'; + SIGNAL nl1OOi0OO : STD_LOGIC := '0'; + SIGNAL nl1OOi1lO : STD_LOGIC := '0'; + SIGNAL nl1OOi1Oi : STD_LOGIC := '0'; + SIGNAL nl1OOi1Ol : STD_LOGIC := '0'; + SIGNAL nl1OOi1OO : STD_LOGIC := '0'; + SIGNAL nl1OOii0i : STD_LOGIC := '0'; + SIGNAL nl1OOii0l : STD_LOGIC := '0'; + SIGNAL nl1OOii0O : STD_LOGIC := '0'; + SIGNAL nl1OOii1i : STD_LOGIC := '0'; + SIGNAL nl1OOii1l : STD_LOGIC := '0'; + SIGNAL nl1OOiiii : STD_LOGIC := '0'; + SIGNAL nl1OOiiil : STD_LOGIC := '0'; + SIGNAL nl1OOiiiO : STD_LOGIC := '0'; + SIGNAL nl1OOiili : STD_LOGIC := '0'; + SIGNAL nl1OOiill : STD_LOGIC := '0'; + SIGNAL nl1OOiilO : STD_LOGIC := '0'; + SIGNAL nl1OOiiOi : STD_LOGIC := '0'; + SIGNAL nl1OOiiOl : STD_LOGIC := '0'; + SIGNAL nl1OOiiOO : STD_LOGIC := '0'; + SIGNAL nl1OOil1i : STD_LOGIC := '0'; + SIGNAL nl1OOil1l : STD_LOGIC := '0'; + SIGNAL nl1OOil1O : STD_LOGIC := '0'; + SIGNAL nli0Oi0lO : STD_LOGIC := '0'; + SIGNAL nli0Oi0Ol : STD_LOGIC := '0'; + SIGNAL nli0Oi0OO : STD_LOGIC := '0'; + SIGNAL nli0Oiill : STD_LOGIC := '0'; + SIGNAL nli0OiilO : STD_LOGIC := '0'; + SIGNAL nli0OiiOi : STD_LOGIC := '0'; + SIGNAL nli0OOOlO : STD_LOGIC := '0'; + SIGNAL nli0OOOOi : STD_LOGIC := '0'; + SIGNAL nli0OOOOl : STD_LOGIC := '0'; + SIGNAL nli0OOOOO : STD_LOGIC := '0'; + SIGNAL nli10001i : STD_LOGIC := '0'; + SIGNAL nli10001l : STD_LOGIC := '0'; + SIGNAL nli10001O : STD_LOGIC := '0'; + SIGNAL nli10010i : STD_LOGIC := '0'; + SIGNAL nli10010l : STD_LOGIC := '0'; + SIGNAL nli10010O : STD_LOGIC := '0'; + SIGNAL nli10011i : STD_LOGIC := '0'; + SIGNAL nli10011l : STD_LOGIC := '0'; + SIGNAL nli10011O : STD_LOGIC := '0'; + SIGNAL nli1001ii : STD_LOGIC := '0'; + SIGNAL nli1001il : STD_LOGIC := '0'; + SIGNAL nli1001iO : STD_LOGIC := '0'; + SIGNAL nli1001li : STD_LOGIC := '0'; + SIGNAL nli1001ll : STD_LOGIC := '0'; + SIGNAL nli1001lO : STD_LOGIC := '0'; + SIGNAL nli1001Oi : STD_LOGIC := '0'; + SIGNAL nli1001Ol : STD_LOGIC := '0'; + SIGNAL nli1001OO : STD_LOGIC := '0'; + SIGNAL nli1010ll : STD_LOGIC := '0'; + SIGNAL nli1010lO : STD_LOGIC := '0'; + SIGNAL nli1010Oi : STD_LOGIC := '0'; + SIGNAL nli1010Ol : STD_LOGIC := '0'; + SIGNAL nli1010OO : STD_LOGIC := '0'; + SIGNAL nli101i0i : STD_LOGIC := '0'; + SIGNAL nli101i0l : STD_LOGIC := '0'; + SIGNAL nli101i0O : STD_LOGIC := '0'; + SIGNAL nli101i1i : STD_LOGIC := '0'; + SIGNAL nli101i1l : STD_LOGIC := '0'; + SIGNAL nli101i1O : STD_LOGIC := '0'; + SIGNAL nli101iii : STD_LOGIC := '0'; + SIGNAL nli101iil : STD_LOGIC := '0'; + SIGNAL nli101iiO : STD_LOGIC := '0'; + SIGNAL nli101ili : STD_LOGIC := '0'; + SIGNAL nli101ill : STD_LOGIC := '0'; + SIGNAL nli101ilO : STD_LOGIC := '0'; + SIGNAL nli101iOi : STD_LOGIC := '0'; + SIGNAL nli101iOl : STD_LOGIC := '0'; + SIGNAL nli101iOO : STD_LOGIC := '0'; + SIGNAL nli101l0i : STD_LOGIC := '0'; + SIGNAL nli101l0l : STD_LOGIC := '0'; + SIGNAL nli101l0O : STD_LOGIC := '0'; + SIGNAL nli101l1i : STD_LOGIC := '0'; + SIGNAL nli101l1l : STD_LOGIC := '0'; + SIGNAL nli101l1O : STD_LOGIC := '0'; + SIGNAL nli101lii : STD_LOGIC := '0'; + SIGNAL nli101lil : STD_LOGIC := '0'; + SIGNAL nli101liO : STD_LOGIC := '0'; + SIGNAL nli101lli : STD_LOGIC := '0'; + SIGNAL nli101lll : STD_LOGIC := '0'; + SIGNAL nli101llO : STD_LOGIC := '0'; + SIGNAL nli101lOi : STD_LOGIC := '0'; + SIGNAL nli101lOl : STD_LOGIC := '0'; + SIGNAL nli101lOO : STD_LOGIC := '0'; + SIGNAL nli101O0i : STD_LOGIC := '0'; + SIGNAL nli101O0l : STD_LOGIC := '0'; + SIGNAL nli101O0O : STD_LOGIC := '0'; + SIGNAL nli101O1i : STD_LOGIC := '0'; + SIGNAL nli101O1l : STD_LOGIC := '0'; + SIGNAL nli101O1O : STD_LOGIC := '0'; + SIGNAL nli101Oii : STD_LOGIC := '0'; + SIGNAL nli101Oil : STD_LOGIC := '0'; + SIGNAL nli101OiO : STD_LOGIC := '0'; + SIGNAL nli101Oli : STD_LOGIC := '0'; + SIGNAL nli101Oll : STD_LOGIC := '0'; + SIGNAL nli101OlO : STD_LOGIC := '0'; + SIGNAL nli101OOi : STD_LOGIC := '0'; + SIGNAL nli101OOl : STD_LOGIC := '0'; + SIGNAL nli101OOO : STD_LOGIC := '0'; + SIGNAL nli10Oiil : STD_LOGIC := '0'; + SIGNAL nli10OiiO : STD_LOGIC := '0'; + SIGNAL nli10Oili : STD_LOGIC := '0'; + SIGNAL nli10Oill : STD_LOGIC := '0'; + SIGNAL nli10Olil : STD_LOGIC := '0'; + SIGNAL nli10OliO : STD_LOGIC := '0'; + SIGNAL nli10Olli : STD_LOGIC := '0'; + SIGNAL nli10Olll : STD_LOGIC := '0'; + SIGNAL nli10OllO : STD_LOGIC := '0'; + SIGNAL nli10OlOi : STD_LOGIC := '0'; + SIGNAL nli10OlOl : STD_LOGIC := '0'; + SIGNAL nli10OlOO : STD_LOGIC := '0'; + SIGNAL nli10OO0i : STD_LOGIC := '0'; + SIGNAL nli10OO0l : STD_LOGIC := '0'; + SIGNAL nli10OO1i : STD_LOGIC := '0'; + SIGNAL nli10OO1l : STD_LOGIC := '0'; + SIGNAL nli10OO1O : STD_LOGIC := '0'; + SIGNAL nli11000i : STD_LOGIC := '0'; + SIGNAL nli11000l : STD_LOGIC := '0'; + SIGNAL nli11000O : STD_LOGIC := '0'; + SIGNAL nli11001i : STD_LOGIC := '0'; + SIGNAL nli11001l : STD_LOGIC := '0'; + SIGNAL nli11001O : STD_LOGIC := '0'; + SIGNAL nli1100ii : STD_LOGIC := '0'; + SIGNAL nli1100il : STD_LOGIC := '0'; + SIGNAL nli1100iO : STD_LOGIC := '0'; + SIGNAL nli11010i : STD_LOGIC := '0'; + SIGNAL nli11010l : STD_LOGIC := '0'; + SIGNAL nli11010O : STD_LOGIC := '0'; + SIGNAL nli1101ii : STD_LOGIC := '0'; + SIGNAL nli1101il : STD_LOGIC := '0'; + SIGNAL nli1101iO : STD_LOGIC := '0'; + SIGNAL nli1101li : STD_LOGIC := '0'; + SIGNAL nli1101ll : STD_LOGIC := '0'; + SIGNAL nli1101lO : STD_LOGIC := '0'; + SIGNAL nli1101Oi : STD_LOGIC := '0'; + SIGNAL nli1101Ol : STD_LOGIC := '0'; + SIGNAL nli1101OO : STD_LOGIC := '0'; + SIGNAL nli111i1l : STD_LOGIC := '0'; + SIGNAL nli11iiii : STD_LOGIC := '0'; + SIGNAL nli11iill : STD_LOGIC := '0'; + SIGNAL nli11ilil : STD_LOGIC := '0'; + SIGNAL nli11iliO : STD_LOGIC := '0'; + SIGNAL nli11illi : STD_LOGIC := '0'; + SIGNAL nli11illl : STD_LOGIC := '0'; + SIGNAL nli11illO : STD_LOGIC := '0'; + SIGNAL nli11l0Ol : STD_LOGIC := '0'; + SIGNAL nli11l0OO : STD_LOGIC := '0'; + SIGNAL nli11O0ii : STD_LOGIC := '0'; + SIGNAL nli11OiOl : STD_LOGIC := '0'; + SIGNAL nli11Ol0i : STD_LOGIC := '0'; + SIGNAL nli11Ol0l : STD_LOGIC := '0'; + SIGNAL nli11Ol0O : STD_LOGIC := '0'; + SIGNAL nli11Olii : STD_LOGIC := '0'; + SIGNAL nli11Olil : STD_LOGIC := '0'; + SIGNAL nli11OOll : STD_LOGIC := '0'; + SIGNAL nli11OOlO : STD_LOGIC := '0'; + SIGNAL nli11OOOi : STD_LOGIC := '0'; + SIGNAL nli11OOOl : STD_LOGIC := '0'; + SIGNAL nli11OOOO : STD_LOGIC := '0'; + SIGNAL nli1i001i : STD_LOGIC := '0'; + SIGNAL nli1i011i : STD_LOGIC := '0'; + SIGNAL nli1i01li : STD_LOGIC := '0'; + SIGNAL nli1i01ll : STD_LOGIC := '0'; + SIGNAL nli1i01lO : STD_LOGIC := '0'; + SIGNAL nli1i01Oi : STD_LOGIC := '0'; + SIGNAL nli1i01Ol : STD_LOGIC := '0'; + SIGNAL nli1i01OO : STD_LOGIC := '0'; + SIGNAL nli1i1OOi : STD_LOGIC := '0'; + SIGNAL nli1i1OOl : STD_LOGIC := '0'; + SIGNAL nli1i1OOO : STD_LOGIC := '0'; + SIGNAL nli1ii0li : STD_LOGIC := '0'; + SIGNAL nli1ii0ll : STD_LOGIC := '0'; + SIGNAL nli1iiiiO : STD_LOGIC := '0'; + SIGNAL nli1iiili : STD_LOGIC := '0'; + SIGNAL nli1iiill : STD_LOGIC := '0'; + SIGNAL nli1iiilO : STD_LOGIC := '0'; + SIGNAL nli1iiiOi : STD_LOGIC := '0'; + SIGNAL nli1iiiOl : STD_LOGIC := '0'; + SIGNAL nli1iiOlO : STD_LOGIC := '0'; + SIGNAL nli1iiOOi : STD_LOGIC := '0'; + SIGNAL nli1iiOOl : STD_LOGIC := '0'; + SIGNAL nli1iiOOO : STD_LOGIC := '0'; + SIGNAL nli1il10i : STD_LOGIC := '0'; + SIGNAL nli1il10l : STD_LOGIC := '0'; + SIGNAL nli1il10O : STD_LOGIC := '0'; + SIGNAL nli1il11i : STD_LOGIC := '0'; + SIGNAL nli1il11l : STD_LOGIC := '0'; + SIGNAL nli1il11O : STD_LOGIC := '0'; + SIGNAL nli1il1ii : STD_LOGIC := '0'; + SIGNAL nli1illiO : STD_LOGIC := '0'; + SIGNAL nli1illli : STD_LOGIC := '0'; + SIGNAL nli1illll : STD_LOGIC := '0'; + SIGNAL nli1illlO : STD_LOGIC := '0'; + SIGNAL nli1illOi : STD_LOGIC := '0'; + SIGNAL nli1illOl : STD_LOGIC := '0'; + SIGNAL nli1illOO : STD_LOGIC := '0'; + SIGNAL nli1ilO1i : STD_LOGIC := '0'; + SIGNAL nli1ilO1l : STD_LOGIC := '0'; + SIGNAL nli1iO0OO : STD_LOGIC := '0'; + SIGNAL nli1iOi0l : STD_LOGIC := '0'; + SIGNAL nli1iOiii : STD_LOGIC := '0'; + SIGNAL nli1iOiiO : STD_LOGIC := '0'; + SIGNAL nli1iOili : STD_LOGIC := '0'; + SIGNAL nli1iOill : STD_LOGIC := '0'; + SIGNAL nli1iOilO : STD_LOGIC := '0'; + SIGNAL nli1iOiOl : STD_LOGIC := '0'; + SIGNAL nli1iOiOO : STD_LOGIC := '0'; + SIGNAL nli1iOl1i : STD_LOGIC := '0'; + SIGNAL nli1iOl1l : STD_LOGIC := '0'; + SIGNAL nli1iOl1O : STD_LOGIC := '0'; + SIGNAL nli1l000i : STD_LOGIC := '0'; + SIGNAL nli1l000l : STD_LOGIC := '0'; + SIGNAL nli1l000O : STD_LOGIC := '0'; + SIGNAL nli1l001O : STD_LOGIC := '0'; + SIGNAL nli1l00ii : STD_LOGIC := '0'; + SIGNAL nli1l00il : STD_LOGIC := '0'; + SIGNAL nli1l00iO : STD_LOGIC := '0'; + SIGNAL nli1l00li : STD_LOGIC := '0'; + SIGNAL nli1l00ll : STD_LOGIC := '0'; + SIGNAL nli1l00lO : STD_LOGIC := '0'; + SIGNAL nli1l00Oi : STD_LOGIC := '0'; + SIGNAL nli1l00Ol : STD_LOGIC := '0'; + SIGNAL nli1l00OO : STD_LOGIC := '0'; + SIGNAL nli1l110O : STD_LOGIC := '0'; + SIGNAL nli1l11ii : STD_LOGIC := '0'; + SIGNAL nli1l11il : STD_LOGIC := '0'; + SIGNAL nli1l11iO : STD_LOGIC := '0'; + SIGNAL nli1l11li : STD_LOGIC := '0'; + SIGNAL nli1l11ll : STD_LOGIC := '0'; + SIGNAL nli1l11lO : STD_LOGIC := '0'; + SIGNAL nli1l11Oi : STD_LOGIC := '0'; + SIGNAL nli1l11Ol : STD_LOGIC := '0'; + SIGNAL nli1l1l0O : STD_LOGIC := '0'; + SIGNAL nli1l1lii : STD_LOGIC := '0'; + SIGNAL nli1l1lil : STD_LOGIC := '0'; + SIGNAL nli1l1liO : STD_LOGIC := '0'; + SIGNAL nli1l1lli : STD_LOGIC := '0'; + SIGNAL nli1l1lll : STD_LOGIC := '0'; + SIGNAL nli1l1llO : STD_LOGIC := '0'; + SIGNAL nli1l1lOi : STD_LOGIC := '0'; + SIGNAL nli1l1lOl : STD_LOGIC := '0'; + SIGNAL nli1l1lOO : STD_LOGIC := '0'; + SIGNAL nli1l1O0i : STD_LOGIC := '0'; + SIGNAL nli1l1O0l : STD_LOGIC := '0'; + SIGNAL nli1l1O0O : STD_LOGIC := '0'; + SIGNAL nli1l1O1i : STD_LOGIC := '0'; + SIGNAL nli1l1O1l : STD_LOGIC := '0'; + SIGNAL nli1l1O1O : STD_LOGIC := '0'; + SIGNAL nli1l1Oii : STD_LOGIC := '0'; + SIGNAL nli1l1Oil : STD_LOGIC := '0'; + SIGNAL nli1l1OiO : STD_LOGIC := '0'; + SIGNAL nli1l1Oli : STD_LOGIC := '0'; + SIGNAL nli1l1Oll : STD_LOGIC := '0'; + SIGNAL nli1lilli : STD_LOGIC := '0'; + SIGNAL nli1liO1O : STD_LOGIC := '0'; + SIGNAL nli1ll1ii : STD_LOGIC := '0'; + SIGNAL nli1ll1il : STD_LOGIC := '0'; + SIGNAL nli1ll1iO : STD_LOGIC := '0'; + SIGNAL nli1lliOO : STD_LOGIC := '0'; + SIGNAL nli1llOiO : STD_LOGIC := '0'; + SIGNAL nli1llOli : STD_LOGIC := '0'; + SIGNAL nli1llOll : STD_LOGIC := '0'; + SIGNAL nli1llOlO : STD_LOGIC := '0'; + SIGNAL nli1llOOi : STD_LOGIC := '0'; + SIGNAL nli1llOOl : STD_LOGIC := '0'; + SIGNAL nli1llOOO : STD_LOGIC := '0'; + SIGNAL nli1lO00i : STD_LOGIC := '0'; + SIGNAL nli1lO00l : STD_LOGIC := '0'; + SIGNAL nli1lO00O : STD_LOGIC := '0'; + SIGNAL nli1lO01i : STD_LOGIC := '0'; + SIGNAL nli1lO01l : STD_LOGIC := '0'; + SIGNAL nli1lO01O : STD_LOGIC := '0'; + SIGNAL nli1lO0ii : STD_LOGIC := '0'; + SIGNAL nli1lO0il : STD_LOGIC := '0'; + SIGNAL nli1lO0iO : STD_LOGIC := '0'; + SIGNAL nli1lO10i : STD_LOGIC := '0'; + SIGNAL nli1lO10l : STD_LOGIC := '0'; + SIGNAL nli1lO10O : STD_LOGIC := '0'; + SIGNAL nli1lO11i : STD_LOGIC := '0'; + SIGNAL nli1lO11l : STD_LOGIC := '0'; + SIGNAL nli1lO11O : STD_LOGIC := '0'; + SIGNAL nli1lO1ii : STD_LOGIC := '0'; + SIGNAL nli1lO1il : STD_LOGIC := '0'; + SIGNAL nli1lO1iO : STD_LOGIC := '0'; + SIGNAL nli1lO1li : STD_LOGIC := '0'; + SIGNAL nli1lO1ll : STD_LOGIC := '0'; + SIGNAL nli1lO1lO : STD_LOGIC := '0'; + SIGNAL nli1lO1Oi : STD_LOGIC := '0'; + SIGNAL nli1lO1Ol : STD_LOGIC := '0'; + SIGNAL nli1lO1OO : STD_LOGIC := '0'; + SIGNAL nlii10Oii : STD_LOGIC := '0'; + SIGNAL nlii10Oil : STD_LOGIC := '0'; + SIGNAL nlii10OiO : STD_LOGIC := '0'; + SIGNAL nlii10Oli : STD_LOGIC := '0'; + SIGNAL nlii10Oll : STD_LOGIC := '0'; + SIGNAL nlii10OlO : STD_LOGIC := '0'; + SIGNAL nlii10OOi : STD_LOGIC := '0'; + SIGNAL nlii10OOl : STD_LOGIC := '0'; + SIGNAL nlii10OOO : STD_LOGIC := '0'; + SIGNAL nlii1100i : STD_LOGIC := '0'; + SIGNAL nlii1100l : STD_LOGIC := '0'; + SIGNAL nlii1100O : STD_LOGIC := '0'; + SIGNAL nlii1101i : STD_LOGIC := '0'; + SIGNAL nlii1101l : STD_LOGIC := '0'; + SIGNAL nlii1101O : STD_LOGIC := '0'; + SIGNAL nlii110ii : STD_LOGIC := '0'; + SIGNAL nlii110il : STD_LOGIC := '0'; + SIGNAL nlii110iO : STD_LOGIC := '0'; + SIGNAL nlii110li : STD_LOGIC := '0'; + SIGNAL nlii110ll : STD_LOGIC := '0'; + SIGNAL nlii110lO : STD_LOGIC := '0'; + SIGNAL nlii110Oi : STD_LOGIC := '0'; + SIGNAL nlii110Ol : STD_LOGIC := '0'; + SIGNAL nlii110OO : STD_LOGIC := '0'; + SIGNAL nlii1110i : STD_LOGIC := '0'; + SIGNAL nlii1110l : STD_LOGIC := '0'; + SIGNAL nlii1110O : STD_LOGIC := '0'; + SIGNAL nlii1111i : STD_LOGIC := '0'; + SIGNAL nlii1111l : STD_LOGIC := '0'; + SIGNAL nlii1111O : STD_LOGIC := '0'; + SIGNAL nlii111ii : STD_LOGIC := '0'; + SIGNAL nlii111il : STD_LOGIC := '0'; + SIGNAL nlii111iO : STD_LOGIC := '0'; + SIGNAL nlii111li : STD_LOGIC := '0'; + SIGNAL nlii111ll : STD_LOGIC := '0'; + SIGNAL nlii111lO : STD_LOGIC := '0'; + SIGNAL nlii111Oi : STD_LOGIC := '0'; + SIGNAL nlii111Ol : STD_LOGIC := '0'; + SIGNAL nlii111OO : STD_LOGIC := '0'; + SIGNAL nlii11i0i : STD_LOGIC := '0'; + SIGNAL nlii11i0l : STD_LOGIC := '0'; + SIGNAL nlii11i0O : STD_LOGIC := '0'; + SIGNAL nlii11i1i : STD_LOGIC := '0'; + SIGNAL nlii11i1l : STD_LOGIC := '0'; + SIGNAL nlii11i1O : STD_LOGIC := '0'; + SIGNAL nlii11iii : STD_LOGIC := '0'; + SIGNAL nlii1i10i : STD_LOGIC := '0'; + SIGNAL nlii1i10l : STD_LOGIC := '0'; + SIGNAL nlii1i10O : STD_LOGIC := '0'; + SIGNAL nlii1i11i : STD_LOGIC := '0'; + SIGNAL nlii1i11l : STD_LOGIC := '0'; + SIGNAL nlii1i11O : STD_LOGIC := '0'; + SIGNAL nlii1i1ii : STD_LOGIC := '0'; + SIGNAL nlii1i1il : STD_LOGIC := '0'; + SIGNAL nlii1i1iO : STD_LOGIC := '0'; + SIGNAL nlii1i1li : STD_LOGIC := '0'; + SIGNAL nlii1illi : STD_LOGIC := '0'; + SIGNAL nlii1illl : STD_LOGIC := '0'; + SIGNAL nlii1illO : STD_LOGIC := '0'; + SIGNAL nlii1ilOi : STD_LOGIC := '0'; + SIGNAL nlii1ilOl : STD_LOGIC := '0'; + SIGNAL nlii1ilOO : STD_LOGIC := '0'; + SIGNAL nlii1iO0i : STD_LOGIC := '0'; + SIGNAL nlii1iO0l : STD_LOGIC := '0'; + SIGNAL nlii1iO0O : STD_LOGIC := '0'; + SIGNAL nlii1iO1i : STD_LOGIC := '0'; + SIGNAL nlii1iO1l : STD_LOGIC := '0'; + SIGNAL nlii1iO1O : STD_LOGIC := '0'; + SIGNAL nlii1iOii : STD_LOGIC := '0'; + SIGNAL nlii1iOil : STD_LOGIC := '0'; + SIGNAL nlii1iOiO : STD_LOGIC := '0'; + SIGNAL nlii1iOli : STD_LOGIC := '0'; + SIGNAL nlii1iOll : STD_LOGIC := '0'; + SIGNAL nlii1iOlO : STD_LOGIC := '0'; + SIGNAL nlii1iOOi : STD_LOGIC := '0'; + SIGNAL nlii1iOOl : STD_LOGIC := '0'; + SIGNAL nlii1iOOO : STD_LOGIC := '0'; + SIGNAL nlii1l10i : STD_LOGIC := '0'; + SIGNAL nlii1l10l : STD_LOGIC := '0'; + SIGNAL nlii1l10O : STD_LOGIC := '0'; + SIGNAL nlii1l11i : STD_LOGIC := '0'; + SIGNAL nlii1l11l : STD_LOGIC := '0'; + SIGNAL nlii1l11O : STD_LOGIC := '0'; + SIGNAL nlii1l1ii : STD_LOGIC := '0'; + SIGNAL nlii1l1il : STD_LOGIC := '0'; + SIGNAL nlii1l1iO : STD_LOGIC := '0'; + SIGNAL nlii1l1li : STD_LOGIC := '0'; + SIGNAL nliii000i : STD_LOGIC := '0'; + SIGNAL nliii0lOO : STD_LOGIC := '0'; + SIGNAL nliii0O1i : STD_LOGIC := '0'; + SIGNAL nliiOOiii : STD_LOGIC := '0'; + SIGNAL nliiOOiil : STD_LOGIC := '0'; + SIGNAL nliiOOiiO : STD_LOGIC := '0'; + SIGNAL nliiOOili : STD_LOGIC := '0'; + SIGNAL nliiOOill : STD_LOGIC := '0'; + SIGNAL nliiOOilO : STD_LOGIC := '0'; + SIGNAL nlil000Oi : STD_LOGIC := '0'; + SIGNAL nlil000Ol : STD_LOGIC := '0'; + SIGNAL nlil000OO : STD_LOGIC := '0'; + SIGNAL nlil00i0i : STD_LOGIC := '0'; + SIGNAL nlil00i0l : STD_LOGIC := '0'; + SIGNAL nlil00i0O : STD_LOGIC := '0'; + SIGNAL nlil00i1i : STD_LOGIC := '0'; + SIGNAL nlil00i1l : STD_LOGIC := '0'; + SIGNAL nlil00i1O : STD_LOGIC := '0'; + SIGNAL nlil00iii : STD_LOGIC := '0'; + SIGNAL nlil00iil : STD_LOGIC := '0'; + SIGNAL nlil00iiO : STD_LOGIC := '0'; + SIGNAL nlil00ili : STD_LOGIC := '0'; + SIGNAL nlil00ill : STD_LOGIC := '0'; + SIGNAL nlil0100i : STD_LOGIC := '0'; + SIGNAL nlil0100l : STD_LOGIC := '0'; + SIGNAL nlil0100O : STD_LOGIC := '0'; + SIGNAL nlil0101l : STD_LOGIC := '0'; + SIGNAL nlil0101O : STD_LOGIC := '0'; + SIGNAL nlil010ii : STD_LOGIC := '0'; + SIGNAL nlil010il : STD_LOGIC := '0'; + SIGNAL nlil010iO : STD_LOGIC := '0'; + SIGNAL nlil010li : STD_LOGIC := '0'; + SIGNAL nlil010ll : STD_LOGIC := '0'; + SIGNAL nlil010lO : STD_LOGIC := '0'; + SIGNAL nlil010Oi : STD_LOGIC := '0'; + SIGNAL nlil010Ol : STD_LOGIC := '0'; + SIGNAL nlil010OO : STD_LOGIC := '0'; + SIGNAL nlil01i0i : STD_LOGIC := '0'; + SIGNAL nlil01i0l : STD_LOGIC := '0'; + SIGNAL nlil01i1i : STD_LOGIC := '0'; + SIGNAL nlil01i1l : STD_LOGIC := '0'; + SIGNAL nlil01i1O : STD_LOGIC := '0'; + SIGNAL nlil1100i : STD_LOGIC := '0'; + SIGNAL nlil1100l : STD_LOGIC := '0'; + SIGNAL nlil1100O : STD_LOGIC := '0'; + SIGNAL nlil1101O : STD_LOGIC := '0'; + SIGNAL nlil110ii : STD_LOGIC := '0'; + SIGNAL nlil111Oi : STD_LOGIC := '0'; + SIGNAL nlil11l0i : STD_LOGIC := '0'; + SIGNAL nlil11lll : STD_LOGIC := '0'; + SIGNAL nlil11llO : STD_LOGIC := '0'; + SIGNAL nlil11lOi : STD_LOGIC := '0'; + SIGNAL nlil11lOl : STD_LOGIC := '0'; + SIGNAL nlil11lOO : STD_LOGIC := '0'; + SIGNAL nlil11O0i : STD_LOGIC := '0'; + SIGNAL nlil11O0l : STD_LOGIC := '0'; + SIGNAL nlil11O0O : STD_LOGIC := '0'; + SIGNAL nlil11O1i : STD_LOGIC := '0'; + SIGNAL nlil11O1l : STD_LOGIC := '0'; + SIGNAL nlil11O1O : STD_LOGIC := '0'; + SIGNAL nlil11Oii : STD_LOGIC := '0'; + SIGNAL nlil11Oil : STD_LOGIC := '0'; + SIGNAL nlil11OiO : STD_LOGIC := '0'; + SIGNAL nlil1i00i : STD_LOGIC := '0'; + SIGNAL nlil1i00l : STD_LOGIC := '0'; + SIGNAL nlil1i01i : STD_LOGIC := '0'; + SIGNAL nlil1i01l : STD_LOGIC := '0'; + SIGNAL nlil1i01O : STD_LOGIC := '0'; + SIGNAL nlil1i1OO : STD_LOGIC := '0'; + SIGNAL nlil1llOi : STD_LOGIC := '0'; + SIGNAL nlil1llOl : STD_LOGIC := '0'; + SIGNAL nlil1llOO : STD_LOGIC := '0'; + SIGNAL nlil1lO0i : STD_LOGIC := '0'; + SIGNAL nlil1lO0l : STD_LOGIC := '0'; + SIGNAL nlil1lO0O : STD_LOGIC := '0'; + SIGNAL nlil1lO1i : STD_LOGIC := '0'; + SIGNAL nlil1lO1l : STD_LOGIC := '0'; + SIGNAL nlil1lO1O : STD_LOGIC := '0'; + SIGNAL nlil1lOii : STD_LOGIC := '0'; + SIGNAL nlil1lOil : STD_LOGIC := '0'; + SIGNAL nlil1lOiO : STD_LOGIC := '0'; + SIGNAL nlil1lOli : STD_LOGIC := '0'; + SIGNAL nlil1OOiO : STD_LOGIC := '0'; + SIGNAL nlil1OOli : STD_LOGIC := '0'; + SIGNAL nlil1OOll : STD_LOGIC := '0'; + SIGNAL nlil1OOlO : STD_LOGIC := '0'; + SIGNAL nlilill1O : STD_LOGIC := '0'; + SIGNAL nlilillil : STD_LOGIC := '0'; + SIGNAL nlililliO : STD_LOGIC := '0'; + SIGNAL nlililOii : STD_LOGIC := '0'; + SIGNAL nlililOil : STD_LOGIC := '0'; + SIGNAL nlililOiO : STD_LOGIC := '0'; + SIGNAL nlililOli : STD_LOGIC := '0'; + SIGNAL nliliO10O : STD_LOGIC := '0'; + SIGNAL nliliO11i : STD_LOGIC := '0'; + SIGNAL nliliO11l : STD_LOGIC := '0'; + SIGNAL nliliO11O : STD_LOGIC := '0'; + SIGNAL nliliO1ii : STD_LOGIC := '0'; + SIGNAL nliliO1il : STD_LOGIC := '0'; + SIGNAL nliliO1iO : STD_LOGIC := '0'; + SIGNAL nliliO1li : STD_LOGIC := '0'; + SIGNAL nlill0lll : STD_LOGIC := '0'; + SIGNAL nlill0OlO : STD_LOGIC := '0'; + SIGNAL nlill1i0O : STD_LOGIC := '0'; + SIGNAL nlill1l0O : STD_LOGIC := '0'; + SIGNAL nlill1lii : STD_LOGIC := '0'; + SIGNAL nlill1lil : STD_LOGIC := '0'; + SIGNAL nlill1liO : STD_LOGIC := '0'; + SIGNAL nlill1lli : STD_LOGIC := '0'; + SIGNAL wire_nlill0Oll_w_lg_w_lg_w53924w53926w53930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w56923w56925w56926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w53924w53926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w56923w56925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w56923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_w53916w53918w53920w53922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_w56915w56917w56919w56921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w53916w53918w53920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w53515w53863w53864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w56915w56917w56919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w53916w53918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w53515w53863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w53515w53840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w53846w53847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w53748w53749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w56915w56917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w60217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w52435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w52442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w52450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w52457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w52490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w45159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w56915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w47757w47758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0iOO53517w53518w53519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53500w53501w53502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l1010l52106w52107w52108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l1010l52099w52100w52101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52460w52467w52471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52475w52478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52481w52484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0ili53910w53912w53914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0iOO53574w53575w53576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53504w53844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53504w53505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0i00i0l60213w60214w60216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11OOO52342w52344w52346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl111ll1i61431w61433w61435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lO1ii45155w45157w53747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lO1ii45155w45157w45158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOlOO44945w44946w52768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOlOO44945w44946w52772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOO1i45149w45150w45151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOO1l45164w45165w45166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl1iiO0li56217w56224w56225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl1ll0lll56909w56911w56913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl1OllOOO54880w54882w54884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nlii110Ol44999w45000w45001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nlii110Ol44999w45002w45003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w47757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0iOO53517w53518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53500w53501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0l0l53569w53570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0liO53449w53450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0liO53445w53446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0O1l47777w47778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0i00i0l60222w60223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l1010l52106w52107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l1010l52099w52100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52460w52467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1OilOii5684w5685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1OO010i54591w54592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nlii110Ol44995w45005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nlii110Ol45007w45010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl00lliOl54160w54166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl011ll1l54087w54088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l01Oi53740w53741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0ili53910w53912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0iOO53574w53575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0i000Ol59482w59488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0i00i0l60213w60214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOil0l44799w47578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOil0O47059w47236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOil0O47059w47060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiO1O47492w47505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w46925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l0Oill46193w51964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0l11OOO52342w52344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl111ll1i61431w61433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl11lO1ii45155w45157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl11lOlOO44945w44946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl11lOO1i45149w45150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl11lOO1l45164w45165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl11OiliO60228w60229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1iiO0li56217w56224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1ll0lll56909w56911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1ll0llO55838w55842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1Oillll55053w55054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1Ol1l0l55394w55395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1OllOOO54880w54882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1OOii1l8961w55191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli1illll47936w47937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli1illlO47940w47941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli1iOilO42904w42905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nlii110Ol44999w45000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nlii110Ol44999w45002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl0OiOl0i46167w47752w47753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl1ll0iiO55841w55843w55844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01ii1lO45016w45017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0llO53572w53594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0llO53591w53592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl00lliOl54169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl011l1ii52064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iOO53528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iOO53517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0l0i53500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0l0l53569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0liO53452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0liO53449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0liO53445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lll53411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0llO53420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOi53433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOi53417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOi53435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOl53382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0O1l47777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i000Ol59491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00i0l60222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46883w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili46774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiili47090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO47020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiilO46769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOil0i51895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOil1i48208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOil1O51899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiO0i46164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiOiO51898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiOli51901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiOll51904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiOOl51894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOl11O48207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l010lO43938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l1010l52106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l1010l52099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11Oli52460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11Oli52474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11OOO52492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiOl0l47740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1llO48605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10iO1li45042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO1OO44950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOlOO43386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO00i52073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO0li60204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO0lO60209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OOi0i59976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0ilO55830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0iOi56097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lOi56098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lOi55845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lOl5222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Oillll55051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilO0O56227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilO1i55216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilO1O55832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilOii5684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Ol1l0l55038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Ol1l0l55031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OO010i54591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10011i48078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli101ilO48090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli101lOl48084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OO0l48130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li48134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01ll48127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01lO48121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01Oi48118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01Ol48124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01OO48115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1il10l43971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOilO42900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOiOl45273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlii110Ol44995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlii110Ol45007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil00ill43937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil00ill43997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil01i0i43933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1100O44088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli1i011i48055w48056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl00llilO54163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl00lliOi54161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl00lliOl54160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0100llO59067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0100lOi56535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010Olil54111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010OliO54109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010Olli54107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010Olll54105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010OllO54103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010OlOi54101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010OlOl54099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl010OlOO54098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl011l1ii54095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl011ll1l54087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl011ll1O54081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl011OOlO54073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01i0O0O52922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01i0O1i52924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01i0Oii52921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01i0OOl52935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01i0OOO52934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii10i43330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii10l43328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii10O43326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii11i43336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii11l43334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii11O43332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii1ii43324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii1il43323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii1Oi44963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii1Ol52930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l00OO53931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l01ll53742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l01Oi53740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0i0i53921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0i0l53919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0i0O53917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0i1i53927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0i1l53925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0i1O53923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iii53915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iil53913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iiO53911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0ili53910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0ilO53520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iOi53523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iOl53527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0iOO53574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0l0i53503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0l0l44252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0l1i53845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0l1l53513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0l1O53508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lii53389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0liO44990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0O0i53186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i000lO59485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i000Oi59483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i000Ol59482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00i0i60221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00i0l60213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00i0O60218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00i1i60366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00i1l60364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00i1O60215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00iii61540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i00iiO52244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i1liii52277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0i1liil52078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0illl0l52598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0illl0O52596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0illlii52590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0illlil52588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0illliO52587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0illlli52592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0illllO52075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0ilOiOO52131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0ilOl1i52130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0ilOl1l52248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0ilOlll52123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOil0l44799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOil0O47059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOilli47862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiO1O47492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiOii46913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiOiO47246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOiOOl47245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOl10i52081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0iOl11l47151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l000ll45592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l001iO45593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l001li45594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l001ll45595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l001lO45596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l001Oi45597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l001Ol45599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l00iOl45600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l00iOO45601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l00l1i45602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l00l1l45603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l00l1O45604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0100i52257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0101l52252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0101O52251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l010OO52287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l01O1l52285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l01O1O52284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0i00O45598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0i0li51959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0liOi46237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0liOl46236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0liOO46235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0ll0i46231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0ll0l46230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0ll0O46229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0ll1i46234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0ll1l46233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0ll1O46232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0llii46228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0llil46227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lliO46224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0llli46223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0llll46222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lllO46221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0llOi46220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0llOl46219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0llOO46218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lO0i46214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lO0l46213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lO0O46212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lO1i46217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lO1l46216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lO1O46215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOii46211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOil46210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOiO46209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOli46208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOll46207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOlO46206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOOi46205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOOl46204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0lOOO46203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O00i46264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O00l46263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O00O46262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O01i46267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O01l46266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O01O46265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0ii46261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0il46260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0iO46259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0li46258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0ll46257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0lO46256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0Oi46255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0Ol46254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O0OO46253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O10i46199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O10l46198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O10O46197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O11i46202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O11l46201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O11O46200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1ii46196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1il46195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1iO46274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1li46273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1ll46272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1lO46271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1Oi46270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1Ol46269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0O1OO46268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oi0i46249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oi0l46248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oi0O46247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oi1i46252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oi1l46251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oi1O46250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oiii46246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oiil46245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0OiiO46244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oili46243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0Oill46193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0OilO46189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0OiOi46188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0OiOl46187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l0OiOO46545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l1011i52423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l1011l52421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l1011O52420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l101il52065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11O0O52432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11Oii52430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11Oil52428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11OiO52426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11Oli52425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11Oll52487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11OlO52347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11OOi52345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11OOl52343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0l11OOO52342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lil0ll45677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lil11i46544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0liliOO45676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lill0i45672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lill0l45671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lill0O45670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lill1i45675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lill1l45674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lill1O45673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0ll1O1l51277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lliiiO51476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llli0i51468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llli0l51466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llli0O51464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llli1i51474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llli1l51472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llli1O51470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llliii51462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llliil51460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llliiO51458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lllili51456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lllill51454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lllilO51452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llliOi51450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llliOl51448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llliOO51446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llll0i51438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llll0l51436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llll0O51434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llll1i51444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llll1l51442w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llll1O51440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llllii51432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llllil51430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lllliO51428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llllli51426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llllll51424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lllllO51422w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llllOi51420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llllOl51418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0llllOO51416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lllO1i51415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0lOlill50399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0O0i10O49514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiO0li45808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiO1il45809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiO1iO45810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiO1li45811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiO1ll45812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiO1lO45813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiO1Oi46166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiOl0i46167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiOl0l46168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiOl0O46169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiOlii46170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OiOlil48606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol000i45925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol000l45924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol000O45923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol001i45928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol001l45927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol001O45926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00ii45922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00il45921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00iO45920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00li45919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00ll45918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00lO46009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00Oi46008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00Ol46007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol00OO46006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol010i46021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol010l46020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol010O46019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol011i46024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol011l46023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol011O46022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01ii46018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01il46017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01iO46016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01li46015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01ll46014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01lO46013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01Oi46012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01Ol46011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol01OO45929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0i0i46002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0i0l46001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0i0O46000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0i1i46005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0i1l46004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0i1O46003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0iii45999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0iil45998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0iiO45997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0ili45996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0ill45995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0ilO45994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0iOi45993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0iOl45992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0iOO45991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0l0i45987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0l0l45986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0l0O45985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0l1i45990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0l1l45989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0l1O45988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0lii45984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0lil45983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0liO45982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0lli45981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0lll45980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0llO45979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0lOi45978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0lOl45943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0lOO45942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0O0i45938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0O0l45937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0O0O45936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0O1i45941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0O1l45940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0O1O45939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0Oii45935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0Oil45934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0OiO45933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0Oli45932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol0Oll45868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1lOi46042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1lOl46041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1lOO46040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1O0i46036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1O0l46035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1O0O46034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1O1i46039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1O1l46038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1O1O46037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1Oii46033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1Oil46032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1OiO46031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1Oli46030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1Oll46029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1OlO46028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1OOi46027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1OOl46026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0Ol1OOO46025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0Oii46122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0Oil46121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0OiO46120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0Oli46119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0Oll46118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0OlO46117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0OOi46116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0OOl46115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO0OOO46114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1iOO45867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1l0i45863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1l0l45862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1l0O45861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1l1i45866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1l1l45865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1l1O45864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1lii45860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1lil45859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1liO45858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1lli45857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1lll45880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1llO45879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1lOi45878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1lOl45877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1lOO45876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1O0i45872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1O0l45871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1O0O45870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1O1i45875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1O1l45874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1O1O45873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1Oii45869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OO1Oil46123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi00i46131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi00l46130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi00O46129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi01i46134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi01l46133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi01O46132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0ii46128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0il46127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0iO46126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0li46125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0ll46124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0lO45823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0Oi45822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0Ol45821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi0OO45820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi10i46110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi10l46109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi10O46108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi11i46113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi11l46112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi11O46111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1ii45817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1il45816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1iO45815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1li45814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1ll46139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1lO46138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1Oi46137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1Ol46136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOi1OO46135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOii1i45754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO00i45768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO00l45767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO00O45766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO01i45755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO01l45770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO01O45769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO0ii45765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO0il45764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO0iO45763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO10i45751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO10l45750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO10O45749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO11l45753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO11O45752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1ii45748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1il45747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1iO45762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1li45761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1ll45760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1lO45759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1Oi45758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1Ol45757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl0OOO1OO45756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10iO1li45504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10iOOli59405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10iOOll59408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10lliil8959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10lliiO58952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10llili58950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10llill58949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10lliOO54079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10lll1i58940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10lll1l58938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10lll1O58937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10O0OOi59149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11100iO61702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11100li61700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11100ll61698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11100lO61696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11100Oi61694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11100Ol61692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11100OO61690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11101il61704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110i0i61683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110i0l61642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110i0O61640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110i1i61688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110i1l61686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110i1O61684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110iii61638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110iil61636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110iiO61634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110ili61632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110ill61630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110ilO61629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110iOi61658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110iOl61656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110iOO61654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110l0i61646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110l0l61644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110l0O60380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110l1i61652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110l1l61650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110l1O61648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110lii60378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110lil60376w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110liO60375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110lli61627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110lll61625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110llO61623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110lOi61621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110lOl61619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110lOO61617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110O0i61679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110O0l61677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110O0O61675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110O1i61615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110O1l61614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110O1O61681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110Oii61673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110Oil61671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110OiO61669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110Oli61667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110Oll61665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110OlO61663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110OOi61661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110OOl61660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1110OOO61612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111i10i61604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111i10l61602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111i10O61600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111i11i61610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111i11l61608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111i11O61606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111i1ii61599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0il61452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0iO61450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0li61449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0ll61446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0lO61444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0Oi61443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0Ol61440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111l0OO61438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111li1i61437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111liOl61434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111liOO61432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111ll1i61431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111ll1l60372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111OO0i60384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111OO0l60385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111OO1i60373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111OO1l60374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111OO1O60383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO01i52765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO01l52763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO01O52762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO10l53746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO10O45156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO11l45162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO11O45160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO1ii45155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO1Oi44951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO1Ol44949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lO1OO44955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOlll45171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOllO45169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOlOi45152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOlOl43385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOlOO44945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOO1i45149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11lOO1l45164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11Oii0i60369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11Oii0l59845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OiliO60228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11Oilll60507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OillO60509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OilOi60511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OilOl60513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OilOO60515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OiO0i60523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OiO1i60517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OiO1l60519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OiO1O60521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OiOOl61552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OiOOO61551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11Ol11i59967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO00i59963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO00l60211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO00O59842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO0li59541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO0ll59542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO0lO59867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OOi0i59982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OOOii59718w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i010iO58944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1000i58138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1000l58140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1000O58142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1001i58132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1001l58134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1001O58136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100ii58144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100il58058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100iO58060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100li58062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100ll58064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100lO58066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100Oi58068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100Ol58070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i100OO58072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1010i58166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1010l58168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1010O58170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1011i58214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1011l58216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1011O58164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101ii58172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101il58174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101iO58176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101li58178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101ll58180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101lO58182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101Oi58184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101Ol58186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i101OO58130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10i0i58098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10i0l58100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10i0O58102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10i1i58092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10i1l58094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10i1O58096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10iii58104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10iil58106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10iiO58108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10ili58110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10ill58112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i10ilO58114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1101i59141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1101l59140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i1101O58236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i111Oi59147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i111Ol59145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i111OO59143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11lOl58238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11lOO58240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11O0i58248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11O0l58250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11O0O58252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11O1i58242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11O1l58244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11O1O58246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11Oii58254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11Oil58256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11OiO58258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11Oli58202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11Oll58204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11OlO58206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11OOi58208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11OOl58210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1i11OOO58212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1iil10O55851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1iiO0li56217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1iiO0ll57606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1iiO0lO57605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1iiOiii56091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1il1i1l56094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1il1i1O56135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1l1iOii55850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1l1iOil55849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0iiO55841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0ili55858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0ilO55035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0iOi54179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0iOl54180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0l0i56922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0l0l56920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0l0O56918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0l1i56927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0l1l56929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0l1O56924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lii56916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lil56914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0liO56912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lli56910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lll56909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0llO55838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lOi55058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0lOl5115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1lO1ilO56933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1O1i0OO56932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1O1ii1i56939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1O1ii1l56938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilliO55056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Oillli55050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Oillll55053w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilllO54891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OillOl54176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OillOO54177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilO0O54864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilO1i54178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilOii54862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilOil55037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Ol011O54883w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Ol1l0i55030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Ol1l0l55394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OllOOl54881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OllOOO54880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OlO11l54923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OO010i8963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OO010l54593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OOi01i54582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OOi01l54523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OOi1OO54545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OOii1l8961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli0Oi0Ol45090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli0Oiill45088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli0OOOOi44975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli0OOOOl44973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli0OOOOO44972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10001O46501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10011i48069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli101ilO48080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli101lOl48077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10Oiil46500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OiiO46499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10Oili46498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10Olil46477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OliO46478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10Olli46481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OllO46484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OlOi48046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OlOl46482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OlOO46479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OO0i48038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OO0l46486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OO1i46483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OO1l46480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10OO1O46485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11iiii44010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11iill46316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11ilil46315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11iliO46314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11illi46313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11illl44167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11illO44166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11l0OO48152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11O0ii46538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11OiOl46525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11Ol0i46529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11Ol0l46528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11Ol0O46527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11Olii46526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11Olil46520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11OOll46524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11OOlO46523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11OOOi46522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11OOOl46521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11OOOO48086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i011i46487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01li46492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01ll46493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01lO46494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01Oi46495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01Ol46496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i01OO46497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i1OOl48024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1ii0li47984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1ii0ll47970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iiiiO47976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iiili46418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iiill46417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iiOOl46426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iiOOO46427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1il10i46430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1il10l43974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1il10O43948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1il11i46428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1il11O46429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1illll47936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1illlO47940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1illOi47944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1illOl46365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1illOO46366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1ilO1i46367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1ilO1l46368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iO0OO46369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOi0l46372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOiii46370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOiiO46375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOili42902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOill42899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOilO42904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOiOl46377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOiOO46378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOl1i46379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOl1l46380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1iOl1O46332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l110O46331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11ii46340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11il46339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11iO46338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11li46337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11ll46336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11lO46335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11Oi46334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1l11Ol46333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1lilli47854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1liO1O47844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1ll1ii47843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1ll1il47842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1ll1iO47841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlii110lO44996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlii110Oi44994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlii110Ol44999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlii11i0O45506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliii000i44663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliii0lOO44662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliii0O1i44661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliiOOiii44117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliiOOill45520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil00i0l43345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil00i1i43347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil00iil43346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil0100i44132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil0100l44130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil0100O44128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil0101l44136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil0101O44134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010ii44127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010il44157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010iO44155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010li44153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010ll44151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010lO44149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010Oi44147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010Ol44145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil010OO44143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil01i0i43942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil01i1i44141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil01i1l44140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil01i1O43932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1100i44089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1100l44087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil11O1i44035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil11Oil44028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil11OiO43341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1i1OO43338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1llOi43939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1llOl43953w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1lOii52245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1lOil43935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1lOli44164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1OOiO44162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1OOli44160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1OOll44159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil1OOlO44138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlilillil43258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlililOli42942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliliO11i42940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliliO11l42939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nliliO1li42964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlill1i0O44980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlill1l0O44978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlill1lii44977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlill1lli45669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0llO53572w53594w53595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0lll53411w53412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0lOi53433w53434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl0OiOl0i46167w47752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1ll0iiO55841w55843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1OilOii54862w54863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lOi53433w53434w53436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w53422w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lil53414w53418w53421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lOi53324w53325w53326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_w_lg_nl1OilO1O55178w55179w55180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0lil53414w53418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0lOi53324w53325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl01l0lOO53327w53328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl10iO1li43256w43257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1OilO1O55178w55179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nl1OO010l54837w54838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_w_lg_nli11l0Ol51961w51962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01ii1lO45016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lii53416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lil53414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0liO53567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lli53568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0llO53439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0llO53572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0llO53591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOi53571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOi53324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOl53590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl01l0lOO53327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10iO1li43256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl10lliOO54083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111OO1l61530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl111OO1O61527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO0il60206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl11OO0OO60061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1ll0llO55563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OilO1O55178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1Ol1l0l55562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OlO11l55412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OlO11l55419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OO010l54837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nl1OOii1l54830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli11l0Ol51961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i011i48055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil00i0l43959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil00i0O43958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nlil01i1O43944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli10Olll48050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i011i48146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0Oll_w_lg_nli1i1OOl48133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL nlliOOlOO : STD_LOGIC := '0'; + SIGNAL nlliOOO0i : STD_LOGIC := '0'; + SIGNAL nlliOOO0l : STD_LOGIC := '0'; + SIGNAL nlliOOO0O : STD_LOGIC := '0'; + SIGNAL nlliOOO1i : STD_LOGIC := '0'; + SIGNAL nlliOOO1l : STD_LOGIC := '0'; + SIGNAL nlliOOO1O : STD_LOGIC := '0'; + SIGNAL nlliOOOii : STD_LOGIC := '0'; + SIGNAL nlliOOOil : STD_LOGIC := '0'; + SIGNAL nlliOOOiO : STD_LOGIC := '0'; + SIGNAL nlliOOOli : STD_LOGIC := '0'; + SIGNAL nlliOOOll : STD_LOGIC := '0'; + SIGNAL nlliOOOlO : STD_LOGIC := '0'; + SIGNAL nlliOOOOi : STD_LOGIC := '0'; + SIGNAL nlliOOOOl : STD_LOGIC := '0'; + SIGNAL nlliOOOOO : STD_LOGIC := '0'; + SIGNAL nlll1100i : STD_LOGIC := '0'; + SIGNAL nlll1100l : STD_LOGIC := '0'; + SIGNAL nlll1100O : STD_LOGIC := '0'; + SIGNAL nlll1101i : STD_LOGIC := '0'; + SIGNAL nlll1101l : STD_LOGIC := '0'; + SIGNAL nlll1101O : STD_LOGIC := '0'; + SIGNAL nlll110ii : STD_LOGIC := '0'; + SIGNAL nlll110il : STD_LOGIC := '0'; + SIGNAL nlll110iO : STD_LOGIC := '0'; + SIGNAL nlll110li : STD_LOGIC := '0'; + SIGNAL nlll110ll : STD_LOGIC := '0'; + SIGNAL nlll110lO : STD_LOGIC := '0'; + SIGNAL nlll110Oi : STD_LOGIC := '0'; + SIGNAL nlll110Ol : STD_LOGIC := '0'; + SIGNAL nlll110OO : STD_LOGIC := '0'; + SIGNAL nlll1110i : STD_LOGIC := '0'; + SIGNAL nlll1110l : STD_LOGIC := '0'; + SIGNAL nlll1110O : STD_LOGIC := '0'; + SIGNAL nlll1111i : STD_LOGIC := '0'; + SIGNAL nlll1111l : STD_LOGIC := '0'; + SIGNAL nlll1111O : STD_LOGIC := '0'; + SIGNAL nlll111ii : STD_LOGIC := '0'; + SIGNAL nlll111il : STD_LOGIC := '0'; + SIGNAL nlll111iO : STD_LOGIC := '0'; + SIGNAL nlll111li : STD_LOGIC := '0'; + SIGNAL nlll111ll : STD_LOGIC := '0'; + SIGNAL nlll111lO : STD_LOGIC := '0'; + SIGNAL nlll111Oi : STD_LOGIC := '0'; + SIGNAL nlll111Ol : STD_LOGIC := '0'; + SIGNAL nlll111OO : STD_LOGIC := '0'; + SIGNAL nlll11i0i : STD_LOGIC := '0'; + SIGNAL nlll11i0l : STD_LOGIC := '0'; + SIGNAL nlll11i0O : STD_LOGIC := '0'; + SIGNAL nlll11i1i : STD_LOGIC := '0'; + SIGNAL nlll11i1l : STD_LOGIC := '0'; + SIGNAL nlll11i1O : STD_LOGIC := '0'; + SIGNAL nlll11iii : STD_LOGIC := '0'; + SIGNAL nlll11iil : STD_LOGIC := '0'; + SIGNAL nlll11iiO : STD_LOGIC := '0'; + SIGNAL nlll11ili : STD_LOGIC := '0'; + SIGNAL nlll11ill : STD_LOGIC := '0'; + SIGNAL nlll11ilO : STD_LOGIC := '0'; + SIGNAL nlll11iOi : STD_LOGIC := '0'; + SIGNAL nlll11iOl : STD_LOGIC := '0'; + SIGNAL nlll11iOO : STD_LOGIC := '0'; + SIGNAL nlll11l0i : STD_LOGIC := '0'; + SIGNAL nlll11l1i : STD_LOGIC := '0'; + SIGNAL nlll11l1l : STD_LOGIC := '0'; + SIGNAL n1il1i0O : STD_LOGIC := '0'; + SIGNAL niO0111l : STD_LOGIC := '0'; + SIGNAL niO01O0i : STD_LOGIC := '0'; + SIGNAL niO01O1l : STD_LOGIC := '0'; + SIGNAL niO01Oii : STD_LOGIC := '0'; + SIGNAL niO01OiO : STD_LOGIC := '0'; + SIGNAL niO1OOOl : STD_LOGIC := '0'; + SIGNAL niO1OOOO : STD_LOGIC := '0'; + SIGNAL niOiil0O : STD_LOGIC := '0'; + SIGNAL niOlOiOl : STD_LOGIC := '0'; + SIGNAL niOlOO0O : STD_LOGIC := '0'; + SIGNAL niOO000i : STD_LOGIC := '0'; + SIGNAL niOO0ilO : STD_LOGIC := '0'; + SIGNAL niOO0iOi : STD_LOGIC := '0'; + SIGNAL niOO0O0O : STD_LOGIC := '0'; + SIGNAL niOO11Ol : STD_LOGIC := '0'; + SIGNAL niOO1iii : STD_LOGIC := '0'; + SIGNAL niOO1lOO : STD_LOGIC := '0'; + SIGNAL niOOi01ll : STD_LOGIC := '0'; + SIGNAL niOOi1Ol : STD_LOGIC := '0'; + SIGNAL niOOl1ll : STD_LOGIC := '0'; + SIGNAL niOOlO1O : STD_LOGIC := '0'; + SIGNAL niOOO10i : STD_LOGIC := '0'; + SIGNAL niOOOi0i : STD_LOGIC := '0'; + SIGNAL niOOOlii : STD_LOGIC := '0'; + SIGNAL niOOOlli : STD_LOGIC := '0'; + SIGNAL niOOOlOi : STD_LOGIC := '0'; + SIGNAL niOOOO0i : STD_LOGIC := '0'; + SIGNAL niOOOO1i : STD_LOGIC := '0'; + SIGNAL niOOOOlO : STD_LOGIC := '0'; + SIGNAL nl00lO1i : STD_LOGIC := '0'; + SIGNAL nl010Oll : STD_LOGIC := '0'; + SIGNAL nl011lil : STD_LOGIC := '0'; + SIGNAL nl01i00i : STD_LOGIC := '0'; + SIGNAL nl01llOO : STD_LOGIC := '0'; + SIGNAL nl0Olili : STD_LOGIC := '0'; + SIGNAL nl0OOlii : STD_LOGIC := '0'; + SIGNAL nl10001O : STD_LOGIC := '0'; + SIGNAL nl1010Ol : STD_LOGIC := '0'; + SIGNAL nl1011Oi : STD_LOGIC := '0'; + SIGNAL nl10i1ii : STD_LOGIC := '0'; + SIGNAL nl10ilOl : STD_LOGIC := '0'; + SIGNAL nl10l00i : STD_LOGIC := '0'; + SIGNAL nl10l01i : STD_LOGIC := '0'; + SIGNAL nl10l1Oi : STD_LOGIC := '0'; + SIGNAL nl10lllO : STD_LOGIC := '0'; + SIGNAL nl1101Ol : STD_LOGIC := '0'; + SIGNAL nl110iii : STD_LOGIC := '0'; + SIGNAL nl110lOO : STD_LOGIC := '0'; + SIGNAL nl11100l : STD_LOGIC := '0'; + SIGNAL nl111iOi : STD_LOGIC := '0'; + SIGNAL nl111lOl : STD_LOGIC := '0'; + SIGNAL nl11i1il : STD_LOGIC := '0'; + SIGNAL nl11ii1i : STD_LOGIC := '0'; + SIGNAL nl11iliO : STD_LOGIC := '0'; + SIGNAL nl11l01O : STD_LOGIC := '0'; + SIGNAL nl11l11l : STD_LOGIC := '0'; + SIGNAL nl11lill : STD_LOGIC := '0'; + SIGNAL nl11lO0i : STD_LOGIC := '0'; + SIGNAL nl11O1lO : STD_LOGIC := '0'; + SIGNAL nl11Oi0l : STD_LOGIC := '0'; + SIGNAL nl11OlOi : STD_LOGIC := '0'; + SIGNAL nl1i1lOl : STD_LOGIC := '0'; + SIGNAL nl1ii1li : STD_LOGIC := '0'; + SIGNAL nl1iii1i : STD_LOGIC := '0'; + SIGNAL nl1iiliO : STD_LOGIC := '0'; + SIGNAL nl1il10O : STD_LOGIC := '0'; + SIGNAL nl1iO1OO : STD_LOGIC := '0'; + SIGNAL nl1iOOOO : STD_LOGIC := '0'; + SIGNAL nl1l001l : STD_LOGIC := '0'; + SIGNAL nl1l0ili : STD_LOGIC := '0'; + SIGNAL nl1l0Oil : STD_LOGIC := '0'; + SIGNAL nl1l10il : STD_LOGIC := '0'; + SIGNAL nl1l1l1i : STD_LOGIC := '0'; + SIGNAL nl1l1OiO : STD_LOGIC := '0'; + SIGNAL nl1li11l : STD_LOGIC := '0'; + SIGNAL nl1lilii : STD_LOGIC := '0'; + SIGNAL nl1ll00O : STD_LOGIC := '0'; + SIGNAL nl1ll0iO : STD_LOGIC := '0'; + SIGNAL nl1llO1l : STD_LOGIC := '0'; + SIGNAL nl1lO0il : STD_LOGIC := '0'; + SIGNAL nl1O001l : STD_LOGIC := '0'; + SIGNAL nl1O0ili : STD_LOGIC := '0'; + SIGNAL nl1O0O1O : STD_LOGIC := '0'; + SIGNAL nl1O1iil : STD_LOGIC := '0'; + SIGNAL nl1O1O1l : STD_LOGIC := '0'; + SIGNAL nl1Oi0lO : STD_LOGIC := '0'; + SIGNAL nl1Oi1ll : STD_LOGIC := '0'; + SIGNAL nl1Oil0l : STD_LOGIC := '0'; + SIGNAL nl1Ol0Oi : STD_LOGIC := '0'; + SIGNAL nl1Ol10l : STD_LOGIC := '0'; + SIGNAL nl1Oll0O : STD_LOGIC := '0'; + SIGNAL nl1OlOOl : STD_LOGIC := '0'; + SIGNAL nli1000i : STD_LOGIC := '0'; + SIGNAL nli1000O : STD_LOGIC := '0'; + SIGNAL nli100ii : STD_LOGIC := '0'; + SIGNAL nli100il : STD_LOGIC := '0'; + SIGNAL nli1100O : STD_LOGIC := '0'; + SIGNAL nllli10l : STD_LOGIC := '0'; + SIGNAL nllli1iO : STD_LOGIC := '0'; + SIGNAL nllli1li : STD_LOGIC := '0'; + SIGNAL nlllil1i : STD_LOGIC := '0'; + SIGNAL nlOi000lO : STD_LOGIC := '0'; + SIGNAL nlOi0011O : STD_LOGIC := '0'; + SIGNAL nlOi00lli : STD_LOGIC := '0'; + SIGNAL nlOi00lOl : STD_LOGIC := '0'; + SIGNAL nlOi00OOO : STD_LOGIC := '0'; + SIGNAL nlOi0i00O : STD_LOGIC := '0'; + SIGNAL nlOi0ilOl : STD_LOGIC := '0'; + SIGNAL nlOi0lOii : STD_LOGIC := '0'; + SIGNAL nlOi0lOiO : STD_LOGIC := '0'; + SIGNAL nlOi0O0li : STD_LOGIC := '0'; + SIGNAL nlOi0Ol0i : STD_LOGIC := '0'; + SIGNAL nlOi0OO0O : STD_LOGIC := '0'; + SIGNAL nlOii01li : STD_LOGIC := '0'; + SIGNAL nlOii0i0i : STD_LOGIC := '0'; + SIGNAL nlOii0OOl : STD_LOGIC := '0'; + SIGNAL nlOii1iii : STD_LOGIC := '0'; + SIGNAL nlOii1O1i : STD_LOGIC := '0'; + SIGNAL nlOiii00i : STD_LOGIC := '0'; + SIGNAL nlOiii11O : STD_LOGIC := '0'; + SIGNAL nlOiii1ii : STD_LOGIC := '0'; + SIGNAL nlOiii1ll : STD_LOGIC := '0'; + SIGNAL nlOiiiili : STD_LOGIC := '0'; + SIGNAL nlOiil01O : STD_LOGIC := '0'; + SIGNAL nlOiiO10i : STD_LOGIC := '0'; + SIGNAL nlOiiOlOi : STD_LOGIC := '0'; + SIGNAL nlOil1i0i : STD_LOGIC := '0'; + SIGNAL nlOil1i0l : STD_LOGIC := '0'; + SIGNAL nlOil1i0O : STD_LOGIC := '0'; + SIGNAL nlOil1i1l : STD_LOGIC := '0'; + SIGNAL nlOili1il : STD_LOGIC := '0'; + SIGNAL nlOilii1i : STD_LOGIC := '0'; + SIGNAL nlOilii1l : STD_LOGIC := '0'; + SIGNAL nlOiliiii : STD_LOGIC := '0'; + SIGNAL nlOilil1l : STD_LOGIC := '0'; + SIGNAL nlOilO0ii : STD_LOGIC := '0'; + SIGNAL nlOilOl1i : STD_LOGIC := '0'; + SIGNAL nlOilOOli : STD_LOGIC := '0'; + SIGNAL wire_nllliiOO_w_lg_niO1OOOl8792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niO010il : STD_LOGIC := '0'; + SIGNAL niO0111i : STD_LOGIC := '0'; + SIGNAL niO0111O : STD_LOGIC := '0'; + SIGNAL niO011il : STD_LOGIC := '0'; + SIGNAL niO01iil : STD_LOGIC := '0'; + SIGNAL niO01lOl : STD_LOGIC := '0'; + SIGNAL niO01O1i : STD_LOGIC := '0'; + SIGNAL niOi00Ol : STD_LOGIC := '0'; + SIGNAL niOlOiii : STD_LOGIC := '0'; + SIGNAL niOlOlOO : STD_LOGIC := '0'; + SIGNAL niOO01il : STD_LOGIC := '0'; + SIGNAL niOO0l0i : STD_LOGIC := '0'; + SIGNAL niOO0Oi0O : STD_LOGIC := '0'; + SIGNAL niOO0OlO : STD_LOGIC := '0'; + SIGNAL niOO11il : STD_LOGIC := '0'; + SIGNAL niOO1i1i : STD_LOGIC := '0'; + SIGNAL niOO1liO : STD_LOGIC := '0'; + SIGNAL niOOi00l : STD_LOGIC := '0'; + SIGNAL niOOi1l1l : STD_LOGIC := '0'; + SIGNAL niOOilOl : STD_LOGIC := '0'; + SIGNAL niOOllll : STD_LOGIC := '0'; + SIGNAL niOOO0lO : STD_LOGIC := '0'; + SIGNAL niOOO1li : STD_LOGIC := '0'; + SIGNAL niOOOO0l : STD_LOGIC := '0'; + SIGNAL nl00Ol0O : STD_LOGIC := '0'; + SIGNAL nl01i0li : STD_LOGIC := '0'; + SIGNAL nl01i11l : STD_LOGIC := '0'; + SIGNAL nl01iiOl : STD_LOGIC := '0'; + SIGNAL nl01Ol0l : STD_LOGIC := '0'; + SIGNAL nl0OlOiO : STD_LOGIC := '0'; + SIGNAL nl0OOOii : STD_LOGIC := '0'; + SIGNAL nl100Oii : STD_LOGIC := '0'; + SIGNAL nl10110O : STD_LOGIC := '0'; + SIGNAL nl101i0l : STD_LOGIC := '0'; + SIGNAL nl101Oli : STD_LOGIC := '0'; + SIGNAL nl10iiOl : STD_LOGIC := '0'; + SIGNAL nl10li0O : STD_LOGIC := '0'; + SIGNAL nl10O00l : STD_LOGIC := '0'; + SIGNAL nl10O0il : STD_LOGIC := '0'; + SIGNAL nl10O0ll : STD_LOGIC := '0'; + SIGNAL nl10O0Ol : STD_LOGIC := '0'; + SIGNAL nl10Oi0l : STD_LOGIC := '0'; + SIGNAL nl10Oi1l : STD_LOGIC := '0'; + SIGNAL nl10Oiil : STD_LOGIC := '0'; + SIGNAL nl10Oill : STD_LOGIC := '0'; + SIGNAL nl1100OO : STD_LOGIC := '0'; + SIGNAL nl1101ii : STD_LOGIC := '0'; + SIGNAL nl110lil : STD_LOGIC := '0'; + SIGNAL nl1111Oi : STD_LOGIC := '0'; + SIGNAL nl111i0O : STD_LOGIC := '0'; + SIGNAL nl111O0O : STD_LOGIC := '0'; + SIGNAL nl11i0iO : STD_LOGIC := '0'; + SIGNAL nl11i11i : STD_LOGIC := '0'; + SIGNAL nl11il1l : STD_LOGIC := '0'; + SIGNAL nl11iOli : STD_LOGIC := '0'; + SIGNAL nl11l0li : STD_LOGIC := '0'; + SIGNAL nl11ll1O : STD_LOGIC := '0'; + SIGNAL nl11lOll : STD_LOGIC := '0'; + SIGNAL nl11O00i : STD_LOGIC := '0'; + SIGNAL nl11OilO : STD_LOGIC := '0'; + SIGNAL nl11OO0i : STD_LOGIC := '0'; + SIGNAL nl1i0OOl : STD_LOGIC := '0'; + SIGNAL nl1i11Oi : STD_LOGIC := '0'; + SIGNAL nl1iiiii : STD_LOGIC := '0'; + SIGNAL nl1iilOO : STD_LOGIC := '0'; + SIGNAL nl1il1OO : STD_LOGIC := '0'; + SIGNAL nl1illOl : STD_LOGIC := '0'; + SIGNAL nl1iOOil : STD_LOGIC := '0'; + SIGNAL nl1iOOll : STD_LOGIC := '0'; + SIGNAL nl1iOOOl : STD_LOGIC := '0'; + SIGNAL nl1l00il : STD_LOGIC := '0'; + SIGNAL nl1l0l1i : STD_LOGIC := '0'; + SIGNAL nl1l0O0l : STD_LOGIC := '0'; + SIGNAL nl1l10Ol : STD_LOGIC := '0'; + SIGNAL nl1l110O : STD_LOGIC := '0'; + SIGNAL nl1l1lii : STD_LOGIC := '0'; + SIGNAL nl1l1OOO : STD_LOGIC := '0'; + SIGNAL nl1li1OO : STD_LOGIC := '0'; + SIGNAL nl1liill : STD_LOGIC := '0'; + SIGNAL nl1liOii : STD_LOGIC := '0'; + SIGNAL nl1ll0lO : STD_LOGIC := '0'; + SIGNAL nl1llOll : STD_LOGIC := '0'; + SIGNAL nl1lOi0O : STD_LOGIC := '0'; + SIGNAL nl1O01li : STD_LOGIC := '0'; + SIGNAL nl1O0i1O : STD_LOGIC := '0'; + SIGNAL nl1O0lll : STD_LOGIC := '0'; + SIGNAL nl1O10li : STD_LOGIC := '0'; + SIGNAL nl1O1Oil : STD_LOGIC := '0'; + SIGNAL nl1Oi10i : STD_LOGIC := '0'; + SIGNAL nl1Oii1O : STD_LOGIC := '0'; + SIGNAL nl1Oilll : STD_LOGIC := '0'; + SIGNAL nl1OiOOi : STD_LOGIC := '0'; + SIGNAL nl1Ol00O : STD_LOGIC := '0'; + SIGNAL nl1OliOl : STD_LOGIC := '0'; + SIGNAL nl1OlOii : STD_LOGIC := '0'; + SIGNAL nl1OOOiO : STD_LOGIC := '0'; + SIGNAL nli1000l : STD_LOGIC := '0'; + SIGNAL nli110li : STD_LOGIC := '0'; + SIGNAL nli11l0O : STD_LOGIC := '0'; + SIGNAL nli11l1l : STD_LOGIC := '0'; + SIGNAL nli11lii : STD_LOGIC := '0'; + SIGNAL nlll0lOi : STD_LOGIC := '0'; + SIGNAL nllliiOl : STD_LOGIC := '0'; + SIGNAL nlllil0l : STD_LOGIC := '0'; + SIGNAL nlllil1l : STD_LOGIC := '0'; + SIGNAL nlllil1O : STD_LOGIC := '0'; + SIGNAL wire_nlllil0i_CLRN : STD_LOGIC; + SIGNAL wire_nlllil0i_PRN : STD_LOGIC; + SIGNAL niO0100O : STD_LOGIC := '0'; + SIGNAL niO0110O : STD_LOGIC := '0'; + SIGNAL niO01i0O : STD_LOGIC := '0'; + SIGNAL nlllliOl : STD_LOGIC := '0'; + SIGNAL nlllliOO : STD_LOGIC := '0'; + SIGNAL nlllll0i : STD_LOGIC := '0'; + SIGNAL wire_nlllll1O_CLRN : STD_LOGIC; + SIGNAL wire_n000000i_dataout : STD_LOGIC; + SIGNAL wire_n000000l_dataout : STD_LOGIC; + SIGNAL wire_n000000O_dataout : STD_LOGIC; + SIGNAL wire_n000001i_dataout : STD_LOGIC; + SIGNAL wire_n000001l_dataout : STD_LOGIC; + SIGNAL wire_n000001O_dataout : STD_LOGIC; + SIGNAL wire_n00000i_dataout : STD_LOGIC; + SIGNAL wire_n00000ii_dataout : STD_LOGIC; + SIGNAL wire_n00000il_dataout : STD_LOGIC; + SIGNAL wire_n00000iO_dataout : STD_LOGIC; + SIGNAL wire_n00000l_dataout : STD_LOGIC; + SIGNAL wire_n00000li_dataout : STD_LOGIC; + SIGNAL wire_n00000ll_dataout : STD_LOGIC; + SIGNAL wire_n00000lO_dataout : STD_LOGIC; + SIGNAL wire_n00000O_dataout : STD_LOGIC; + SIGNAL wire_n00000Oi_dataout : STD_LOGIC; + SIGNAL wire_n00000Ol_dataout : STD_LOGIC; + SIGNAL wire_n00000OO_dataout : STD_LOGIC; + SIGNAL wire_n000010i_dataout : STD_LOGIC; + SIGNAL wire_n000010l_dataout : STD_LOGIC; + SIGNAL wire_n000010O_dataout : STD_LOGIC; + SIGNAL wire_n000011i_dataout : STD_LOGIC; + SIGNAL wire_n000011l_dataout : STD_LOGIC; + SIGNAL wire_n000011O_dataout : STD_LOGIC; + SIGNAL wire_n00001i_dataout : STD_LOGIC; + SIGNAL wire_n00001ii_dataout : STD_LOGIC; + SIGNAL wire_n00001il_dataout : STD_LOGIC; + SIGNAL wire_n00001iO_dataout : STD_LOGIC; + SIGNAL wire_n00001l_dataout : STD_LOGIC; + SIGNAL wire_n00001li_dataout : STD_LOGIC; + SIGNAL wire_n00001ll_dataout : STD_LOGIC; + SIGNAL wire_n00001lO_dataout : STD_LOGIC; + SIGNAL wire_n00001O_dataout : STD_LOGIC; + SIGNAL wire_n00001Oi_dataout : STD_LOGIC; + SIGNAL wire_n00001Ol_dataout : STD_LOGIC; + SIGNAL wire_n00001OO_dataout : STD_LOGIC; + SIGNAL wire_n0000i0i_dataout : STD_LOGIC; + SIGNAL wire_n0000i0l_dataout : STD_LOGIC; + SIGNAL wire_n0000i0O_dataout : STD_LOGIC; + SIGNAL wire_n0000i1i_dataout : STD_LOGIC; + SIGNAL wire_n0000i1l_dataout : STD_LOGIC; + SIGNAL wire_n0000i1O_dataout : STD_LOGIC; + SIGNAL wire_n0000ii_dataout : STD_LOGIC; + SIGNAL wire_n0000iii_dataout : STD_LOGIC; + SIGNAL wire_n0000iil_dataout : STD_LOGIC; + SIGNAL wire_n0000il_dataout : STD_LOGIC; + SIGNAL wire_n0000iO_dataout : STD_LOGIC; + SIGNAL wire_n0000l0O_dataout : STD_LOGIC; + SIGNAL wire_n0000li_dataout : STD_LOGIC; + SIGNAL wire_n0000lii_dataout : STD_LOGIC; + SIGNAL wire_n0000lil_dataout : STD_LOGIC; + SIGNAL wire_n0000liO_dataout : STD_LOGIC; + SIGNAL wire_n0000ll_dataout : STD_LOGIC; + SIGNAL wire_n0000lli_dataout : STD_LOGIC; + SIGNAL wire_n0000lll_dataout : STD_LOGIC; + SIGNAL wire_n0000llO_dataout : STD_LOGIC; + SIGNAL wire_n0000lO_dataout : STD_LOGIC; + SIGNAL wire_n0000lOi_dataout : STD_LOGIC; + SIGNAL wire_n0000lOl_dataout : STD_LOGIC; + SIGNAL wire_n0000lOO_dataout : STD_LOGIC; + SIGNAL wire_n0000O0i_dataout : STD_LOGIC; + SIGNAL wire_n0000O0l_dataout : STD_LOGIC; + SIGNAL wire_n0000O0O_dataout : STD_LOGIC; + SIGNAL wire_n0000O1i_dataout : STD_LOGIC; + SIGNAL wire_n0000O1l_dataout : STD_LOGIC; + SIGNAL wire_n0000O1O_dataout : STD_LOGIC; + SIGNAL wire_n0000Oi_dataout : STD_LOGIC; + SIGNAL wire_n0000Oii_dataout : STD_LOGIC; + SIGNAL wire_n0000Oil_dataout : STD_LOGIC; + SIGNAL wire_n0000Ol_dataout : STD_LOGIC; + SIGNAL wire_n0000OO_dataout : STD_LOGIC; + SIGNAL wire_n0000OOl_dataout : STD_LOGIC; + SIGNAL wire_n0000OOO_dataout : STD_LOGIC; + SIGNAL wire_n000100i_dataout : STD_LOGIC; + SIGNAL wire_n000100l_dataout : STD_LOGIC; + SIGNAL wire_n000100O_dataout : STD_LOGIC; + SIGNAL wire_n000101i_dataout : STD_LOGIC; + SIGNAL wire_n000101l_dataout : STD_LOGIC; + SIGNAL wire_n000101O_dataout : STD_LOGIC; + SIGNAL wire_n00010i_dataout : STD_LOGIC; + SIGNAL wire_n00010ii_dataout : STD_LOGIC; + SIGNAL wire_n00010il_dataout : STD_LOGIC; + SIGNAL wire_n00010iO_dataout : STD_LOGIC; + SIGNAL wire_n00010l_dataout : STD_LOGIC; + SIGNAL wire_n00010O_dataout : STD_LOGIC; + SIGNAL wire_n000110i_dataout : STD_LOGIC; + SIGNAL wire_n000110l_dataout : STD_LOGIC; + SIGNAL wire_n000110O_dataout : STD_LOGIC; + SIGNAL wire_n000111i_dataout : STD_LOGIC; + SIGNAL wire_n000111l_dataout : STD_LOGIC; + SIGNAL wire_n000111O_dataout : STD_LOGIC; + SIGNAL wire_n00011ii_dataout : STD_LOGIC; + SIGNAL wire_n00011il_dataout : STD_LOGIC; + SIGNAL wire_n00011iO_dataout : STD_LOGIC; + SIGNAL wire_n00011li_dataout : STD_LOGIC; + SIGNAL wire_n00011ll_dataout : STD_LOGIC; + SIGNAL wire_n00011lO_dataout : STD_LOGIC; + SIGNAL wire_n00011Oi_dataout : STD_LOGIC; + SIGNAL wire_n00011Ol_dataout : STD_LOGIC; + SIGNAL wire_n00011OO_dataout : STD_LOGIC; + SIGNAL wire_n0001i0i_dataout : STD_LOGIC; + SIGNAL wire_n0001i0l_dataout : STD_LOGIC; + SIGNAL wire_n0001i0O_dataout : STD_LOGIC; + SIGNAL wire_n0001i1O_dataout : STD_LOGIC; + SIGNAL wire_n0001iii_dataout : STD_LOGIC; + SIGNAL wire_n0001iil_dataout : STD_LOGIC; + SIGNAL wire_n0001iiO_dataout : STD_LOGIC; + SIGNAL wire_n0001ili_dataout : STD_LOGIC; + SIGNAL wire_n0001ill_dataout : STD_LOGIC; + SIGNAL wire_n0001ilO_dataout : STD_LOGIC; + SIGNAL wire_n0001iO_dataout : STD_LOGIC; + SIGNAL wire_n0001iOi_dataout : STD_LOGIC; + SIGNAL wire_n0001iOl_dataout : STD_LOGIC; + SIGNAL wire_n0001iOO_dataout : STD_LOGIC; + SIGNAL wire_n0001l0i_dataout : STD_LOGIC; + SIGNAL wire_n0001l0l_dataout : STD_LOGIC; + SIGNAL wire_n0001l0O_dataout : STD_LOGIC; + SIGNAL wire_n0001l1i_dataout : STD_LOGIC; + SIGNAL wire_n0001l1l_dataout : STD_LOGIC; + SIGNAL wire_n0001l1O_dataout : STD_LOGIC; + SIGNAL wire_n0001li_dataout : STD_LOGIC; + SIGNAL wire_n0001lii_dataout : STD_LOGIC; + SIGNAL wire_n0001lil_dataout : STD_LOGIC; + SIGNAL wire_n0001liO_dataout : STD_LOGIC; + SIGNAL wire_n0001ll_dataout : STD_LOGIC; + SIGNAL wire_n0001lli_dataout : STD_LOGIC; + SIGNAL wire_n0001lll_dataout : STD_LOGIC; + SIGNAL wire_n0001llO_dataout : STD_LOGIC; + SIGNAL wire_n0001lO_dataout : STD_LOGIC; + SIGNAL wire_n0001lOi_dataout : STD_LOGIC; + SIGNAL wire_n0001lOl_dataout : STD_LOGIC; + SIGNAL wire_n0001lOO_dataout : STD_LOGIC; + SIGNAL wire_n0001O0i_dataout : STD_LOGIC; + SIGNAL wire_n0001O0l_dataout : STD_LOGIC; + SIGNAL wire_n0001O0O_dataout : STD_LOGIC; + SIGNAL wire_n0001O1i_dataout : STD_LOGIC; + SIGNAL wire_n0001O1l_dataout : STD_LOGIC; + SIGNAL wire_n0001O1O_dataout : STD_LOGIC; + SIGNAL wire_n0001Oi_dataout : STD_LOGIC; + SIGNAL wire_n0001Oii_dataout : STD_LOGIC; + SIGNAL wire_n0001Oil_dataout : STD_LOGIC; + SIGNAL wire_n0001OiO_dataout : STD_LOGIC; + SIGNAL wire_n0001Ol_dataout : STD_LOGIC; + SIGNAL wire_n0001Oli_dataout : STD_LOGIC; + SIGNAL wire_n0001Oll_dataout : STD_LOGIC; + SIGNAL wire_n0001OlO_dataout : STD_LOGIC; + SIGNAL wire_n0001OO_dataout : STD_LOGIC; + SIGNAL wire_n0001OOi_dataout : STD_LOGIC; + SIGNAL wire_n0001OOl_dataout : STD_LOGIC; + SIGNAL wire_n0001OOO_dataout : STD_LOGIC; + SIGNAL wire_n000i00l_dataout : STD_LOGIC; + SIGNAL wire_n000i00O_dataout : STD_LOGIC; + SIGNAL wire_n000i0i_dataout : STD_LOGIC; + SIGNAL wire_n000i0ii_dataout : STD_LOGIC; + SIGNAL wire_n000i0il_dataout : STD_LOGIC; + SIGNAL wire_n000i0iO_dataout : STD_LOGIC; + SIGNAL wire_n000i0l_dataout : STD_LOGIC; + SIGNAL wire_n000i0li_dataout : STD_LOGIC; + SIGNAL wire_n000i0ll_dataout : STD_LOGIC; + SIGNAL wire_n000i0lO_dataout : STD_LOGIC; + SIGNAL wire_n000i0O_dataout : STD_LOGIC; + SIGNAL wire_n000i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n000i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n000i0OO_dataout : STD_LOGIC; + SIGNAL wire_n000i1i_dataout : STD_LOGIC; + SIGNAL wire_n000i1l_dataout : STD_LOGIC; + SIGNAL wire_n000i1O_dataout : STD_LOGIC; + SIGNAL wire_n000ii0i_dataout : STD_LOGIC; + SIGNAL wire_n000ii0l_dataout : STD_LOGIC; + SIGNAL wire_n000ii0O_dataout : STD_LOGIC; + SIGNAL wire_n000ii1i_dataout : STD_LOGIC; + SIGNAL wire_n000ii1l_dataout : STD_LOGIC; + SIGNAL wire_n000ii1O_dataout : STD_LOGIC; + SIGNAL wire_n000iii_dataout : STD_LOGIC; + SIGNAL wire_n000iil_dataout : STD_LOGIC; + SIGNAL wire_n000iiO_dataout : STD_LOGIC; + SIGNAL wire_n000iiOi_dataout : STD_LOGIC; + SIGNAL wire_n000iiOl_dataout : STD_LOGIC; + SIGNAL wire_n000iiOO_dataout : STD_LOGIC; + SIGNAL wire_n000il0i_dataout : STD_LOGIC; + SIGNAL wire_n000il0l_dataout : STD_LOGIC; + SIGNAL wire_n000il0O_dataout : STD_LOGIC; + SIGNAL wire_n000il1i_dataout : STD_LOGIC; + SIGNAL wire_n000il1l_dataout : STD_LOGIC; + SIGNAL wire_n000il1O_dataout : STD_LOGIC; + SIGNAL wire_n000ili_dataout : STD_LOGIC; + SIGNAL wire_n000ilii_dataout : STD_LOGIC; + SIGNAL wire_n000ilil_dataout : STD_LOGIC; + SIGNAL wire_n000iliO_dataout : STD_LOGIC; + SIGNAL wire_n000ill_dataout : STD_LOGIC; + SIGNAL wire_n000illi_dataout : STD_LOGIC; + SIGNAL wire_n000illl_dataout : STD_LOGIC; + SIGNAL wire_n000illO_dataout : STD_LOGIC; + SIGNAL wire_n000ilO_dataout : STD_LOGIC; + SIGNAL wire_n000ilOi_dataout : STD_LOGIC; + SIGNAL wire_n000ilOl_dataout : STD_LOGIC; + SIGNAL wire_n000ilOO_dataout : STD_LOGIC; + SIGNAL wire_n000iO0i_dataout : STD_LOGIC; + SIGNAL wire_n000iO0l_dataout : STD_LOGIC; + SIGNAL wire_n000iO0O_dataout : STD_LOGIC; + SIGNAL wire_n000iO1i_dataout : STD_LOGIC; + SIGNAL wire_n000iO1l_dataout : STD_LOGIC; + SIGNAL wire_n000iO1O_dataout : STD_LOGIC; + SIGNAL wire_n000iOi_dataout : STD_LOGIC; + SIGNAL wire_n000iOii_dataout : STD_LOGIC; + SIGNAL wire_n000iOil_dataout : STD_LOGIC; + SIGNAL wire_n000iOiO_dataout : STD_LOGIC; + SIGNAL wire_n000iOl_dataout : STD_LOGIC; + SIGNAL wire_n000iOli_dataout : STD_LOGIC; + SIGNAL wire_n000iOll_dataout : STD_LOGIC; + SIGNAL wire_n000iOlO_dataout : STD_LOGIC; + SIGNAL wire_n000iOO_dataout : STD_LOGIC; + SIGNAL wire_n000iOOi_dataout : STD_LOGIC; + SIGNAL wire_n000l0i_dataout : STD_LOGIC; + SIGNAL wire_n000l0l_dataout : STD_LOGIC; + SIGNAL wire_n000l0O_dataout : STD_LOGIC; + SIGNAL wire_n000l10i_dataout : STD_LOGIC; + SIGNAL wire_n000l10l_dataout : STD_LOGIC; + SIGNAL wire_n000l10O_dataout : STD_LOGIC; + SIGNAL wire_n000l11i_dataout : STD_LOGIC; + SIGNAL wire_n000l11l_dataout : STD_LOGIC; + SIGNAL wire_n000l11O_dataout : STD_LOGIC; + SIGNAL wire_n000l1i_dataout : STD_LOGIC; + SIGNAL wire_n000l1l_dataout : STD_LOGIC; + SIGNAL wire_n000l1O_dataout : STD_LOGIC; + SIGNAL wire_n000li0l_dataout : STD_LOGIC; + SIGNAL wire_n000lii_dataout : STD_LOGIC; + SIGNAL wire_n000liil_dataout : STD_LOGIC; + SIGNAL wire_n000lil_dataout : STD_LOGIC; + SIGNAL wire_n000lili_dataout : STD_LOGIC; + SIGNAL wire_n000liO_dataout : STD_LOGIC; + SIGNAL wire_n000liOi_dataout : STD_LOGIC; + SIGNAL wire_n000liOO_dataout : STD_LOGIC; + SIGNAL wire_n000ll0i_dataout : STD_LOGIC; + SIGNAL wire_n000ll0O_dataout : STD_LOGIC; + SIGNAL wire_n000ll1l_dataout : STD_LOGIC; + SIGNAL wire_n000lli_dataout : STD_LOGIC; + SIGNAL wire_n000lll_dataout : STD_LOGIC; + SIGNAL wire_n000llO_dataout : STD_LOGIC; + SIGNAL wire_n000lOi_dataout : STD_LOGIC; + SIGNAL wire_n000lOiO_dataout : STD_LOGIC; + SIGNAL wire_n000lOl_dataout : STD_LOGIC; + SIGNAL wire_n000lOli_dataout : STD_LOGIC; + SIGNAL wire_n000lOll_dataout : STD_LOGIC; + SIGNAL wire_n000lOlO_dataout : STD_LOGIC; + SIGNAL wire_n000lOO_dataout : STD_LOGIC; + SIGNAL wire_n000lOOi_dataout : STD_LOGIC; + SIGNAL wire_n000lOOl_dataout : STD_LOGIC; + SIGNAL wire_n000lOOO_dataout : STD_LOGIC; + SIGNAL wire_n000O00i_dataout : STD_LOGIC; + SIGNAL wire_n000O00l_dataout : STD_LOGIC; + SIGNAL wire_n000O00O_dataout : STD_LOGIC; + SIGNAL wire_n000O01i_dataout : STD_LOGIC; + SIGNAL wire_n000O01l_dataout : STD_LOGIC; + SIGNAL wire_n000O01O_dataout : STD_LOGIC; + SIGNAL wire_n000O0i_dataout : STD_LOGIC; + SIGNAL wire_n000O0ii_dataout : STD_LOGIC; + SIGNAL wire_n000O0il_dataout : STD_LOGIC; + SIGNAL wire_n000O0iO_dataout : STD_LOGIC; + SIGNAL wire_n000O0l_dataout : STD_LOGIC; + SIGNAL wire_n000O0li_dataout : STD_LOGIC; + SIGNAL wire_n000O0ll_dataout : STD_LOGIC; + SIGNAL wire_n000O0lO_dataout : STD_LOGIC; + SIGNAL wire_n000O0O_dataout : STD_LOGIC; + SIGNAL wire_n000O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n000O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n000O0OO_dataout : STD_LOGIC; + SIGNAL wire_n000O10i_dataout : STD_LOGIC; + SIGNAL wire_n000O10l_dataout : STD_LOGIC; + SIGNAL wire_n000O10O_dataout : STD_LOGIC; + SIGNAL wire_n000O11i_dataout : STD_LOGIC; + SIGNAL wire_n000O11l_dataout : STD_LOGIC; + SIGNAL wire_n000O11O_dataout : STD_LOGIC; + SIGNAL wire_n000O1i_dataout : STD_LOGIC; + SIGNAL wire_n000O1ii_dataout : STD_LOGIC; + SIGNAL wire_n000O1il_dataout : STD_LOGIC; + SIGNAL wire_n000O1iO_dataout : STD_LOGIC; + SIGNAL wire_n000O1l_dataout : STD_LOGIC; + SIGNAL wire_n000O1li_dataout : STD_LOGIC; + SIGNAL wire_n000O1ll_dataout : STD_LOGIC; + SIGNAL wire_n000O1lO_dataout : STD_LOGIC; + SIGNAL wire_n000O1O_dataout : STD_LOGIC; + SIGNAL wire_n000O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n000O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n000O1OO_dataout : STD_LOGIC; + SIGNAL wire_n000Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n000Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n000Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n000Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n000Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n000Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n000Oii_dataout : STD_LOGIC; + SIGNAL wire_n000Oiii_dataout : STD_LOGIC; + SIGNAL wire_n000Oiil_dataout : STD_LOGIC; + SIGNAL wire_n000OiiO_dataout : STD_LOGIC; + SIGNAL wire_n000Oil_dataout : STD_LOGIC; + SIGNAL wire_n000Oili_dataout : STD_LOGIC; + SIGNAL wire_n000Oill_dataout : STD_LOGIC; + SIGNAL wire_n000OiO_dataout : STD_LOGIC; + SIGNAL wire_n000OiOi_dataout : STD_LOGIC; + SIGNAL wire_n000OiOl_dataout : STD_LOGIC; + SIGNAL wire_n000OiOO_dataout : STD_LOGIC; + SIGNAL wire_n000Oli_dataout : STD_LOGIC; + SIGNAL wire_n000Oll_dataout : STD_LOGIC; + SIGNAL wire_n000OlO_dataout : STD_LOGIC; + SIGNAL wire_n000OOi_dataout : STD_LOGIC; + SIGNAL wire_n000OOl_dataout : STD_LOGIC; + SIGNAL wire_n000OOO_dataout : STD_LOGIC; + SIGNAL wire_n000OOOl_dataout : STD_LOGIC; + SIGNAL wire_n000OOOl_w_lg_dataout15828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00100i_dataout : STD_LOGIC; + SIGNAL wire_n00100l_dataout : STD_LOGIC; + SIGNAL wire_n00100ll_dataout : STD_LOGIC; + SIGNAL wire_n00100lO_dataout : STD_LOGIC; + SIGNAL wire_n00100O_dataout : STD_LOGIC; + SIGNAL wire_n00100Oi_dataout : STD_LOGIC; + SIGNAL wire_n00100Ol_dataout : STD_LOGIC; + SIGNAL wire_n00100OO_dataout : STD_LOGIC; + SIGNAL wire_n00101i_dataout : STD_LOGIC; + SIGNAL wire_n00101l_dataout : STD_LOGIC; + SIGNAL wire_n00101O_dataout : STD_LOGIC; + SIGNAL wire_n0010i0i_dataout : STD_LOGIC; + SIGNAL wire_n0010i0l_dataout : STD_LOGIC; + SIGNAL wire_n0010i0O_dataout : STD_LOGIC; + SIGNAL wire_n0010i1i_dataout : STD_LOGIC; + SIGNAL wire_n0010i1l_dataout : STD_LOGIC; + SIGNAL wire_n0010i1O_dataout : STD_LOGIC; + SIGNAL wire_n0010ii_dataout : STD_LOGIC; + SIGNAL wire_n0010iii_dataout : STD_LOGIC; + SIGNAL wire_n0010il_dataout : STD_LOGIC; + SIGNAL wire_n0010iO_dataout : STD_LOGIC; + SIGNAL wire_n0010l0l_dataout : STD_LOGIC; + SIGNAL wire_n0010l0O_dataout : STD_LOGIC; + SIGNAL wire_n0010li_dataout : STD_LOGIC; + SIGNAL wire_n0010lii_dataout : STD_LOGIC; + SIGNAL wire_n0010lil_dataout : STD_LOGIC; + SIGNAL wire_n0010liO_dataout : STD_LOGIC; + SIGNAL wire_n0010ll_dataout : STD_LOGIC; + SIGNAL wire_n0010lli_dataout : STD_LOGIC; + SIGNAL wire_n0010lll_dataout : STD_LOGIC; + SIGNAL wire_n0010llO_dataout : STD_LOGIC; + SIGNAL wire_n0010lO_dataout : STD_LOGIC; + SIGNAL wire_n0010lOi_dataout : STD_LOGIC; + SIGNAL wire_n0010lOl_dataout : STD_LOGIC; + SIGNAL wire_n0010Oi_dataout : STD_LOGIC; + SIGNAL wire_n0010Ol_dataout : STD_LOGIC; + SIGNAL wire_n0010OO_dataout : STD_LOGIC; + SIGNAL wire_n00110i_dataout : STD_LOGIC; + SIGNAL wire_n00110l_dataout : STD_LOGIC; + SIGNAL wire_n00110li_dataout : STD_LOGIC; + SIGNAL wire_n00110ll_dataout : STD_LOGIC; + SIGNAL wire_n00110lO_dataout : STD_LOGIC; + SIGNAL wire_n00110O_dataout : STD_LOGIC; + SIGNAL wire_n00110Ol_dataout : STD_LOGIC; + SIGNAL wire_n00110OO_dataout : STD_LOGIC; + SIGNAL wire_n001110O_dataout : STD_LOGIC; + SIGNAL wire_n00111i_dataout : STD_LOGIC; + SIGNAL wire_n00111ii_dataout : STD_LOGIC; + SIGNAL wire_n00111il_dataout : STD_LOGIC; + SIGNAL wire_n00111iO_dataout : STD_LOGIC; + SIGNAL wire_n00111l_dataout : STD_LOGIC; + SIGNAL wire_n00111li_dataout : STD_LOGIC; + SIGNAL wire_n00111O_dataout : STD_LOGIC; + SIGNAL wire_n0011i0i_dataout : STD_LOGIC; + SIGNAL wire_n0011i0l_dataout : STD_LOGIC; + SIGNAL wire_n0011i0O_dataout : STD_LOGIC; + SIGNAL wire_n0011i1i_dataout : STD_LOGIC; + SIGNAL wire_n0011i1l_dataout : STD_LOGIC; + SIGNAL wire_n0011i1O_dataout : STD_LOGIC; + SIGNAL wire_n0011ii_dataout : STD_LOGIC; + SIGNAL wire_n0011iii_dataout : STD_LOGIC; + SIGNAL wire_n0011iil_dataout : STD_LOGIC; + SIGNAL wire_n0011iiO_dataout : STD_LOGIC; + SIGNAL wire_n0011il_dataout : STD_LOGIC; + SIGNAL wire_n0011ili_dataout : STD_LOGIC; + SIGNAL wire_n0011ill_dataout : STD_LOGIC; + SIGNAL wire_n0011ilO_dataout : STD_LOGIC; + SIGNAL wire_n0011iO_dataout : STD_LOGIC; + SIGNAL wire_n0011iOi_dataout : STD_LOGIC; + SIGNAL wire_n0011iOl_dataout : STD_LOGIC; + SIGNAL wire_n0011iOO_dataout : STD_LOGIC; + SIGNAL wire_n0011l0i_dataout : STD_LOGIC; + SIGNAL wire_n0011l0l_dataout : STD_LOGIC; + SIGNAL wire_n0011l0O_dataout : STD_LOGIC; + SIGNAL wire_n0011l1i_dataout : STD_LOGIC; + SIGNAL wire_n0011l1l_dataout : STD_LOGIC; + SIGNAL wire_n0011l1O_dataout : STD_LOGIC; + SIGNAL wire_n0011li_dataout : STD_LOGIC; + SIGNAL wire_n0011lii_dataout : STD_LOGIC; + SIGNAL wire_n0011lil_dataout : STD_LOGIC; + SIGNAL wire_n0011liO_dataout : STD_LOGIC; + SIGNAL wire_n0011ll_dataout : STD_LOGIC; + SIGNAL wire_n0011lli_dataout : STD_LOGIC; + SIGNAL wire_n0011lll_dataout : STD_LOGIC; + SIGNAL wire_n0011llO_dataout : STD_LOGIC; + SIGNAL wire_n0011lO_dataout : STD_LOGIC; + SIGNAL wire_n0011lOi_dataout : STD_LOGIC; + SIGNAL wire_n0011lOl_dataout : STD_LOGIC; + SIGNAL wire_n0011lOO_dataout : STD_LOGIC; + SIGNAL wire_n0011O0i_dataout : STD_LOGIC; + SIGNAL wire_n0011O0l_dataout : STD_LOGIC; + SIGNAL wire_n0011O0O_dataout : STD_LOGIC; + SIGNAL wire_n0011O1i_dataout : STD_LOGIC; + SIGNAL wire_n0011O1l_dataout : STD_LOGIC; + SIGNAL wire_n0011O1O_dataout : STD_LOGIC; + SIGNAL wire_n0011Oi_dataout : STD_LOGIC; + SIGNAL wire_n0011Oii_dataout : STD_LOGIC; + SIGNAL wire_n0011Oil_dataout : STD_LOGIC; + SIGNAL wire_n0011OiO_dataout : STD_LOGIC; + SIGNAL wire_n0011Ol_dataout : STD_LOGIC; + SIGNAL wire_n0011Oli_dataout : STD_LOGIC; + SIGNAL wire_n0011Oll_dataout : STD_LOGIC; + SIGNAL wire_n0011OlO_dataout : STD_LOGIC; + SIGNAL wire_n0011OO_dataout : STD_LOGIC; + SIGNAL wire_n0011OOi_dataout : STD_LOGIC; + SIGNAL wire_n001i00i_dataout : STD_LOGIC; + SIGNAL wire_n001i00l_dataout : STD_LOGIC; + SIGNAL wire_n001i00O_dataout : STD_LOGIC; + SIGNAL wire_n001i01i_dataout : STD_LOGIC; + SIGNAL wire_n001i01l_dataout : STD_LOGIC; + SIGNAL wire_n001i01O_dataout : STD_LOGIC; + SIGNAL wire_n001i0i_dataout : STD_LOGIC; + SIGNAL wire_n001i0ii_dataout : STD_LOGIC; + SIGNAL wire_n001i0il_dataout : STD_LOGIC; + SIGNAL wire_n001i0iO_dataout : STD_LOGIC; + SIGNAL wire_n001i0l_dataout : STD_LOGIC; + SIGNAL wire_n001i0li_dataout : STD_LOGIC; + SIGNAL wire_n001i0ll_dataout : STD_LOGIC; + SIGNAL wire_n001i0lO_dataout : STD_LOGIC; + SIGNAL wire_n001i0O_dataout : STD_LOGIC; + SIGNAL wire_n001i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n001i1i_dataout : STD_LOGIC; + SIGNAL wire_n001i1il_dataout : STD_LOGIC; + SIGNAL wire_n001i1iO_dataout : STD_LOGIC; + SIGNAL wire_n001i1l_dataout : STD_LOGIC; + SIGNAL wire_n001i1li_dataout : STD_LOGIC; + SIGNAL wire_n001i1ll_dataout : STD_LOGIC; + SIGNAL wire_n001i1lO_dataout : STD_LOGIC; + SIGNAL wire_n001i1O_dataout : STD_LOGIC; + SIGNAL wire_n001i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n001i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n001i1OO_dataout : STD_LOGIC; + SIGNAL wire_n001ii0i_dataout : STD_LOGIC; + SIGNAL wire_n001ii0i_w_lg_w_lg_w_lg_dataout16226w16232w16233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n001ii0i_w_lg_w_lg_dataout16226w16232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n001ii0i_w_lg_dataout16239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n001ii0i_w_lg_dataout16226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n001ii0l_dataout : STD_LOGIC; + SIGNAL wire_n001iii_dataout : STD_LOGIC; + SIGNAL wire_n001iiii_dataout : STD_LOGIC; + SIGNAL wire_n001iil_dataout : STD_LOGIC; + SIGNAL wire_n001iili_dataout : STD_LOGIC; + SIGNAL wire_n001iiO_dataout : STD_LOGIC; + SIGNAL wire_n001ili_dataout : STD_LOGIC; + SIGNAL wire_n001ill_dataout : STD_LOGIC; + SIGNAL wire_n001ilO_dataout : STD_LOGIC; + SIGNAL wire_n001iOi_dataout : STD_LOGIC; + SIGNAL wire_n001iOil_dataout : STD_LOGIC; + SIGNAL wire_n001iOiO_dataout : STD_LOGIC; + SIGNAL wire_n001iOl_dataout : STD_LOGIC; + SIGNAL wire_n001iOli_dataout : STD_LOGIC; + SIGNAL wire_n001iOll_dataout : STD_LOGIC; + SIGNAL wire_n001iOlO_dataout : STD_LOGIC; + SIGNAL wire_n001iOO_dataout : STD_LOGIC; + SIGNAL wire_n001iOOi_dataout : STD_LOGIC; + SIGNAL wire_n001iOOl_dataout : STD_LOGIC; + SIGNAL wire_n001iOOO_dataout : STD_LOGIC; + SIGNAL wire_n001l00i_dataout : STD_LOGIC; + SIGNAL wire_n001l00l_dataout : STD_LOGIC; + SIGNAL wire_n001l00O_dataout : STD_LOGIC; + SIGNAL wire_n001l01i_dataout : STD_LOGIC; + SIGNAL wire_n001l01l_dataout : STD_LOGIC; + SIGNAL wire_n001l01O_dataout : STD_LOGIC; + SIGNAL wire_n001l0i_dataout : STD_LOGIC; + SIGNAL wire_n001l0ii_dataout : STD_LOGIC; + SIGNAL wire_n001l0il_dataout : STD_LOGIC; + SIGNAL wire_n001l0iO_dataout : STD_LOGIC; + SIGNAL wire_n001l0l_dataout : STD_LOGIC; + SIGNAL wire_n001l0li_dataout : STD_LOGIC; + SIGNAL wire_n001l0ll_dataout : STD_LOGIC; + SIGNAL wire_n001l0lO_dataout : STD_LOGIC; + SIGNAL wire_n001l0O_dataout : STD_LOGIC; + SIGNAL wire_n001l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n001l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n001l0OO_dataout : STD_LOGIC; + SIGNAL wire_n001l10i_dataout : STD_LOGIC; + SIGNAL wire_n001l10l_dataout : STD_LOGIC; + SIGNAL wire_n001l10O_dataout : STD_LOGIC; + SIGNAL wire_n001l11i_dataout : STD_LOGIC; + SIGNAL wire_n001l11l_dataout : STD_LOGIC; + SIGNAL wire_n001l11O_dataout : STD_LOGIC; + SIGNAL wire_n001l1i_dataout : STD_LOGIC; + SIGNAL wire_n001l1ii_dataout : STD_LOGIC; + SIGNAL wire_n001l1il_dataout : STD_LOGIC; + SIGNAL wire_n001l1iO_dataout : STD_LOGIC; + SIGNAL wire_n001l1l_dataout : STD_LOGIC; + SIGNAL wire_n001l1li_dataout : STD_LOGIC; + SIGNAL wire_n001l1ll_dataout : STD_LOGIC; + SIGNAL wire_n001l1lO_dataout : STD_LOGIC; + SIGNAL wire_n001l1O_dataout : STD_LOGIC; + SIGNAL wire_n001l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n001l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n001l1OO_dataout : STD_LOGIC; + SIGNAL wire_n001li1i_dataout : STD_LOGIC; + SIGNAL wire_n001li1l_dataout : STD_LOGIC; + SIGNAL wire_n001li1O_dataout : STD_LOGIC; + SIGNAL wire_n001lii_dataout : STD_LOGIC; + SIGNAL wire_n001liil_dataout : STD_LOGIC; + SIGNAL wire_n001liiO_dataout : STD_LOGIC; + SIGNAL wire_n001lil_dataout : STD_LOGIC; + SIGNAL wire_n001liO_dataout : STD_LOGIC; + SIGNAL wire_n001liOi_dataout : STD_LOGIC; + SIGNAL wire_n001liOl_dataout : STD_LOGIC; + SIGNAL wire_n001liOO_dataout : STD_LOGIC; + SIGNAL wire_n001ll0i_dataout : STD_LOGIC; + SIGNAL wire_n001ll0l_dataout : STD_LOGIC; + SIGNAL wire_n001ll0O_dataout : STD_LOGIC; + SIGNAL wire_n001ll1i_dataout : STD_LOGIC; + SIGNAL wire_n001ll1l_dataout : STD_LOGIC; + SIGNAL wire_n001lli_dataout : STD_LOGIC; + SIGNAL wire_n001lll_dataout : STD_LOGIC; + SIGNAL wire_n001llO_dataout : STD_LOGIC; + SIGNAL wire_n001lO1i_dataout : STD_LOGIC; + SIGNAL wire_n001lO1l_dataout : STD_LOGIC; + SIGNAL wire_n001lOi_dataout : STD_LOGIC; + SIGNAL wire_n001lOii_dataout : STD_LOGIC; + SIGNAL wire_n001lOil_dataout : STD_LOGIC; + SIGNAL wire_n001lOiO_dataout : STD_LOGIC; + SIGNAL wire_n001lOl_dataout : STD_LOGIC; + SIGNAL wire_n001lOli_dataout : STD_LOGIC; + SIGNAL wire_n001lOll_dataout : STD_LOGIC; + SIGNAL wire_n001lOlO_dataout : STD_LOGIC; + SIGNAL wire_n001lOO_dataout : STD_LOGIC; + SIGNAL wire_n001lOOi_dataout : STD_LOGIC; + SIGNAL wire_n001lOOl_dataout : STD_LOGIC; + SIGNAL wire_n001lOOO_dataout : STD_LOGIC; + SIGNAL wire_n001O00i_dataout : STD_LOGIC; + SIGNAL wire_n001O00l_dataout : STD_LOGIC; + SIGNAL wire_n001O00O_dataout : STD_LOGIC; + SIGNAL wire_n001O01i_dataout : STD_LOGIC; + SIGNAL wire_n001O01l_dataout : STD_LOGIC; + SIGNAL wire_n001O01O_dataout : STD_LOGIC; + SIGNAL wire_n001O0i_dataout : STD_LOGIC; + SIGNAL wire_n001O0ii_dataout : STD_LOGIC; + SIGNAL wire_n001O0il_dataout : STD_LOGIC; + SIGNAL wire_n001O0iO_dataout : STD_LOGIC; + SIGNAL wire_n001O0l_dataout : STD_LOGIC; + SIGNAL wire_n001O0li_dataout : STD_LOGIC; + SIGNAL wire_n001O0ll_dataout : STD_LOGIC; + SIGNAL wire_n001O0lO_dataout : STD_LOGIC; + SIGNAL wire_n001O0O_dataout : STD_LOGIC; + SIGNAL wire_n001O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n001O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n001O0OO_dataout : STD_LOGIC; + SIGNAL wire_n001O10i_dataout : STD_LOGIC; + SIGNAL wire_n001O10l_dataout : STD_LOGIC; + SIGNAL wire_n001O10O_dataout : STD_LOGIC; + SIGNAL wire_n001O11i_dataout : STD_LOGIC; + SIGNAL wire_n001O11l_dataout : STD_LOGIC; + SIGNAL wire_n001O11O_dataout : STD_LOGIC; + SIGNAL wire_n001O1i_dataout : STD_LOGIC; + SIGNAL wire_n001O1ii_dataout : STD_LOGIC; + SIGNAL wire_n001O1il_dataout : STD_LOGIC; + SIGNAL wire_n001O1iO_dataout : STD_LOGIC; + SIGNAL wire_n001O1l_dataout : STD_LOGIC; + SIGNAL wire_n001O1li_dataout : STD_LOGIC; + SIGNAL wire_n001O1ll_dataout : STD_LOGIC; + SIGNAL wire_n001O1lO_dataout : STD_LOGIC; + SIGNAL wire_n001O1O_dataout : STD_LOGIC; + SIGNAL wire_n001O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n001O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n001O1OO_dataout : STD_LOGIC; + SIGNAL wire_n001Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n001Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n001Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n001Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n001Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n001Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n001Oii_dataout : STD_LOGIC; + SIGNAL wire_n001Oiii_dataout : STD_LOGIC; + SIGNAL wire_n001Oiil_dataout : STD_LOGIC; + SIGNAL wire_n001OiiO_dataout : STD_LOGIC; + SIGNAL wire_n001Oil_dataout : STD_LOGIC; + SIGNAL wire_n001Oili_dataout : STD_LOGIC; + SIGNAL wire_n001Oill_dataout : STD_LOGIC; + SIGNAL wire_n001OilO_dataout : STD_LOGIC; + SIGNAL wire_n001OiO_dataout : STD_LOGIC; + SIGNAL wire_n001OiOi_dataout : STD_LOGIC; + SIGNAL wire_n001OiOl_dataout : STD_LOGIC; + SIGNAL wire_n001OiOO_dataout : STD_LOGIC; + SIGNAL wire_n001Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n001Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n001Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n001Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n001Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n001Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n001Oli_dataout : STD_LOGIC; + SIGNAL wire_n001Olii_dataout : STD_LOGIC; + SIGNAL wire_n001Olil_dataout : STD_LOGIC; + SIGNAL wire_n001OliO_dataout : STD_LOGIC; + SIGNAL wire_n001Oll_dataout : STD_LOGIC; + SIGNAL wire_n001Olli_dataout : STD_LOGIC; + SIGNAL wire_n001Olll_dataout : STD_LOGIC; + SIGNAL wire_n001OllO_dataout : STD_LOGIC; + SIGNAL wire_n001OlO_dataout : STD_LOGIC; + SIGNAL wire_n001OlOi_dataout : STD_LOGIC; + SIGNAL wire_n001OlOl_dataout : STD_LOGIC; + SIGNAL wire_n001OlOO_dataout : STD_LOGIC; + SIGNAL wire_n001OO0i_dataout : STD_LOGIC; + SIGNAL wire_n001OO0l_dataout : STD_LOGIC; + SIGNAL wire_n001OO0O_dataout : STD_LOGIC; + SIGNAL wire_n001OO1i_dataout : STD_LOGIC; + SIGNAL wire_n001OO1l_dataout : STD_LOGIC; + SIGNAL wire_n001OO1O_dataout : STD_LOGIC; + SIGNAL wire_n001OOii_dataout : STD_LOGIC; + SIGNAL wire_n001OOil_dataout : STD_LOGIC; + SIGNAL wire_n001OOiO_dataout : STD_LOGIC; + SIGNAL wire_n001OOli_dataout : STD_LOGIC; + SIGNAL wire_n001OOll_dataout : STD_LOGIC; + SIGNAL wire_n001OOlO_dataout : STD_LOGIC; + SIGNAL wire_n001OOOi_dataout : STD_LOGIC; + SIGNAL wire_n001OOOl_dataout : STD_LOGIC; + SIGNAL wire_n001OOOO_dataout : STD_LOGIC; + SIGNAL wire_n00i00i_dataout : STD_LOGIC; + SIGNAL wire_n00i00l_dataout : STD_LOGIC; + SIGNAL wire_n00i00O_dataout : STD_LOGIC; + SIGNAL wire_n00i010i_dataout : STD_LOGIC; + SIGNAL wire_n00i011i_dataout : STD_LOGIC; + SIGNAL wire_n00i011l_dataout : STD_LOGIC; + SIGNAL wire_n00i011O_dataout : STD_LOGIC; + SIGNAL wire_n00i01i_dataout : STD_LOGIC; + SIGNAL wire_n00i01l_dataout : STD_LOGIC; + SIGNAL wire_n00i01O_dataout : STD_LOGIC; + SIGNAL wire_n00i0ii_dataout : STD_LOGIC; + SIGNAL wire_n00i0il_dataout : STD_LOGIC; + SIGNAL wire_n00i0iO_dataout : STD_LOGIC; + SIGNAL wire_n00i0li_dataout : STD_LOGIC; + SIGNAL wire_n00i0ll_dataout : STD_LOGIC; + SIGNAL wire_n00i0lO_dataout : STD_LOGIC; + SIGNAL wire_n00i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00i0OO_dataout : STD_LOGIC; + SIGNAL wire_n00i10i_dataout : STD_LOGIC; + SIGNAL wire_n00i10l_dataout : STD_LOGIC; + SIGNAL wire_n00i10O_dataout : STD_LOGIC; + SIGNAL wire_n00i110i_dataout : STD_LOGIC; + SIGNAL wire_n00i110i_w_lg_dataout15824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i111l_dataout : STD_LOGIC; + SIGNAL wire_n00i111l_w_lg_dataout15826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i11i_dataout : STD_LOGIC; + SIGNAL wire_n00i11ii_dataout : STD_LOGIC; + SIGNAL wire_n00i11ii_w_lg_dataout15822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i11iO_dataout : STD_LOGIC; + SIGNAL wire_n00i11iO_w_lg_dataout15820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i11l_dataout : STD_LOGIC; + SIGNAL wire_n00i11ll_dataout : STD_LOGIC; + SIGNAL wire_n00i11ll_w_lg_dataout15818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i11O_dataout : STD_LOGIC; + SIGNAL wire_n00i11Oi_dataout : STD_LOGIC; + SIGNAL wire_n00i11Oi_w_lg_dataout15816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i11OO_dataout : STD_LOGIC; + SIGNAL wire_n00i11OO_w_lg_dataout15814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00i1i0i_dataout : STD_LOGIC; + SIGNAL wire_n00i1i0l_dataout : STD_LOGIC; + SIGNAL wire_n00i1i0O_dataout : STD_LOGIC; + SIGNAL wire_n00i1i1l_dataout : STD_LOGIC; + SIGNAL wire_n00i1i1O_dataout : STD_LOGIC; + SIGNAL wire_n00i1ii_dataout : STD_LOGIC; + SIGNAL wire_n00i1iii_dataout : STD_LOGIC; + SIGNAL wire_n00i1iil_dataout : STD_LOGIC; + SIGNAL wire_n00i1iiO_dataout : STD_LOGIC; + SIGNAL wire_n00i1il_dataout : STD_LOGIC; + SIGNAL wire_n00i1ili_dataout : STD_LOGIC; + SIGNAL wire_n00i1ill_dataout : STD_LOGIC; + SIGNAL wire_n00i1ilO_dataout : STD_LOGIC; + SIGNAL wire_n00i1iO_dataout : STD_LOGIC; + SIGNAL wire_n00i1iOi_dataout : STD_LOGIC; + SIGNAL wire_n00i1iOl_dataout : STD_LOGIC; + SIGNAL wire_n00i1iOO_dataout : STD_LOGIC; + SIGNAL wire_n00i1l0i_dataout : STD_LOGIC; + SIGNAL wire_n00i1l0l_dataout : STD_LOGIC; + SIGNAL wire_n00i1l0O_dataout : STD_LOGIC; + SIGNAL wire_n00i1l1i_dataout : STD_LOGIC; + SIGNAL wire_n00i1l1l_dataout : STD_LOGIC; + SIGNAL wire_n00i1l1O_dataout : STD_LOGIC; + SIGNAL wire_n00i1li_dataout : STD_LOGIC; + SIGNAL wire_n00i1lii_dataout : STD_LOGIC; + SIGNAL wire_n00i1lil_dataout : STD_LOGIC; + SIGNAL wire_n00i1liO_dataout : STD_LOGIC; + SIGNAL wire_n00i1ll_dataout : STD_LOGIC; + SIGNAL wire_n00i1lli_dataout : STD_LOGIC; + SIGNAL wire_n00i1lll_dataout : STD_LOGIC; + SIGNAL wire_n00i1llO_dataout : STD_LOGIC; + SIGNAL wire_n00i1lO_dataout : STD_LOGIC; + SIGNAL wire_n00i1lOi_dataout : STD_LOGIC; + SIGNAL wire_n00i1lOl_dataout : STD_LOGIC; + SIGNAL wire_n00i1lOO_dataout : STD_LOGIC; + SIGNAL wire_n00i1O0i_dataout : STD_LOGIC; + SIGNAL wire_n00i1O0l_dataout : STD_LOGIC; + SIGNAL wire_n00i1O0O_dataout : STD_LOGIC; + SIGNAL wire_n00i1O1i_dataout : STD_LOGIC; + SIGNAL wire_n00i1O1l_dataout : STD_LOGIC; + SIGNAL wire_n00i1O1O_dataout : STD_LOGIC; + SIGNAL wire_n00i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n00i1Oii_dataout : STD_LOGIC; + SIGNAL wire_n00i1Oil_dataout : STD_LOGIC; + SIGNAL wire_n00i1OiO_dataout : STD_LOGIC; + SIGNAL wire_n00i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n00i1Oli_dataout : STD_LOGIC; + SIGNAL wire_n00i1Oll_dataout : STD_LOGIC; + SIGNAL wire_n00i1OlO_dataout : STD_LOGIC; + SIGNAL wire_n00i1OO_dataout : STD_LOGIC; + SIGNAL wire_n00i1OOi_dataout : STD_LOGIC; + SIGNAL wire_n00i1OOl_dataout : STD_LOGIC; + SIGNAL wire_n00i1OOO_dataout : STD_LOGIC; + SIGNAL wire_n00ii0i_dataout : STD_LOGIC; + SIGNAL wire_n00ii0il_dataout : STD_LOGIC; + SIGNAL wire_n00ii0iO_dataout : STD_LOGIC; + SIGNAL wire_n00ii0l_dataout : STD_LOGIC; + SIGNAL wire_n00ii0li_dataout : STD_LOGIC; + SIGNAL wire_n00ii0ll_dataout : STD_LOGIC; + SIGNAL wire_n00ii0lO_dataout : STD_LOGIC; + SIGNAL wire_n00ii0O_dataout : STD_LOGIC; + SIGNAL wire_n00ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00ii0OO_dataout : STD_LOGIC; + SIGNAL wire_n00ii1i_dataout : STD_LOGIC; + SIGNAL wire_n00ii1l_dataout : STD_LOGIC; + SIGNAL wire_n00ii1O_dataout : STD_LOGIC; + SIGNAL wire_n00iii0O_dataout : STD_LOGIC; + SIGNAL wire_n00iii1i_dataout : STD_LOGIC; + SIGNAL wire_n00iiii_dataout : STD_LOGIC; + SIGNAL wire_n00iiiii_dataout : STD_LOGIC; + SIGNAL wire_n00iiiil_dataout : STD_LOGIC; + SIGNAL wire_n00iiiiO_dataout : STD_LOGIC; + SIGNAL wire_n00iiil_dataout : STD_LOGIC; + SIGNAL wire_n00iiili_dataout : STD_LOGIC; + SIGNAL wire_n00iiill_dataout : STD_LOGIC; + SIGNAL wire_n00iiiO_dataout : STD_LOGIC; + SIGNAL wire_n00iiiOl_dataout : STD_LOGIC; + SIGNAL wire_n00iiiOO_dataout : STD_LOGIC; + SIGNAL wire_n00iil1i_dataout : STD_LOGIC; + SIGNAL wire_n00iili_dataout : STD_LOGIC; + SIGNAL wire_n00iill_dataout : STD_LOGIC; + SIGNAL wire_n00iilll_dataout : STD_LOGIC; + SIGNAL wire_n00iillO_dataout : STD_LOGIC; + SIGNAL wire_n00iilO_dataout : STD_LOGIC; + SIGNAL wire_n00iilOi_dataout : STD_LOGIC; + SIGNAL wire_n00iilOl_dataout : STD_LOGIC; + SIGNAL wire_n00iilOO_dataout : STD_LOGIC; + SIGNAL wire_n00iiO0i_dataout : STD_LOGIC; + SIGNAL wire_n00iiO0l_dataout : STD_LOGIC; + SIGNAL wire_n00iiO0O_dataout : STD_LOGIC; + SIGNAL wire_n00iiO1i_dataout : STD_LOGIC; + SIGNAL wire_n00iiO1l_dataout : STD_LOGIC; + SIGNAL wire_n00iiO1O_dataout : STD_LOGIC; + SIGNAL wire_n00iiOi_dataout : STD_LOGIC; + SIGNAL wire_n00iiOii_dataout : STD_LOGIC; + SIGNAL wire_n00iiOil_dataout : STD_LOGIC; + SIGNAL wire_n00iiOiO_dataout : STD_LOGIC; + SIGNAL wire_n00iiOl_dataout : STD_LOGIC; + SIGNAL wire_n00iiOli_dataout : STD_LOGIC; + SIGNAL wire_n00iiOO_dataout : STD_LOGIC; + SIGNAL wire_n00iiOOO_dataout : STD_LOGIC; + SIGNAL wire_n00il00i_dataout : STD_LOGIC; + SIGNAL wire_n00il00l_dataout : STD_LOGIC; + SIGNAL wire_n00il00O_dataout : STD_LOGIC; + SIGNAL wire_n00il01i_dataout : STD_LOGIC; + SIGNAL wire_n00il01l_dataout : STD_LOGIC; + SIGNAL wire_n00il01O_dataout : STD_LOGIC; + SIGNAL wire_n00il0i_dataout : STD_LOGIC; + SIGNAL wire_n00il0ii_dataout : STD_LOGIC; + SIGNAL wire_n00il0il_dataout : STD_LOGIC; + SIGNAL wire_n00il0iO_dataout : STD_LOGIC; + SIGNAL wire_n00il0l_dataout : STD_LOGIC; + SIGNAL wire_n00il0li_dataout : STD_LOGIC; + SIGNAL wire_n00il0ll_dataout : STD_LOGIC; + SIGNAL wire_n00il0lO_dataout : STD_LOGIC; + SIGNAL wire_n00il0O_dataout : STD_LOGIC; + SIGNAL wire_n00il0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00il0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00il0OO_dataout : STD_LOGIC; + SIGNAL wire_n00il10i_dataout : STD_LOGIC; + SIGNAL wire_n00il10l_dataout : STD_LOGIC; + SIGNAL wire_n00il10O_dataout : STD_LOGIC; + SIGNAL wire_n00il11i_dataout : STD_LOGIC; + SIGNAL wire_n00il11l_dataout : STD_LOGIC; + SIGNAL wire_n00il1i_dataout : STD_LOGIC; + SIGNAL wire_n00il1ii_dataout : STD_LOGIC; + SIGNAL wire_n00il1l_dataout : STD_LOGIC; + SIGNAL wire_n00il1O_dataout : STD_LOGIC; + SIGNAL wire_n00ili0i_dataout : STD_LOGIC; + SIGNAL wire_n00ili0l_dataout : STD_LOGIC; + SIGNAL wire_n00ili0O_dataout : STD_LOGIC; + SIGNAL wire_n00ili1i_dataout : STD_LOGIC; + SIGNAL wire_n00ili1l_dataout : STD_LOGIC; + SIGNAL wire_n00ili1O_dataout : STD_LOGIC; + SIGNAL wire_n00ilii_dataout : STD_LOGIC; + SIGNAL wire_n00iliii_dataout : STD_LOGIC; + SIGNAL wire_n00iliil_dataout : STD_LOGIC; + SIGNAL wire_n00iliiO_dataout : STD_LOGIC; + SIGNAL wire_n00ilil_dataout : STD_LOGIC; + SIGNAL wire_n00ilili_dataout : STD_LOGIC; + SIGNAL wire_n00iliO_dataout : STD_LOGIC; + SIGNAL wire_n00illi_dataout : STD_LOGIC; + SIGNAL wire_n00illl_dataout : STD_LOGIC; + SIGNAL wire_n00illO_dataout : STD_LOGIC; + SIGNAL wire_n00ilOi_dataout : STD_LOGIC; + SIGNAL wire_n00ilOl_dataout : STD_LOGIC; + SIGNAL wire_n00ilOO_dataout : STD_LOGIC; + SIGNAL wire_n00iO00i_dataout : STD_LOGIC; + SIGNAL wire_n00iO00l_dataout : STD_LOGIC; + SIGNAL wire_n00iO00O_dataout : STD_LOGIC; + SIGNAL wire_n00iO01l_dataout : STD_LOGIC; + SIGNAL wire_n00iO01O_dataout : STD_LOGIC; + SIGNAL wire_n00iO0i_dataout : STD_LOGIC; + SIGNAL wire_n00iO0ii_dataout : STD_LOGIC; + SIGNAL wire_n00iO0il_dataout : STD_LOGIC; + SIGNAL wire_n00iO0iO_dataout : STD_LOGIC; + SIGNAL wire_n00iO0l_dataout : STD_LOGIC; + SIGNAL wire_n00iO0li_dataout : STD_LOGIC; + SIGNAL wire_n00iO0ll_dataout : STD_LOGIC; + SIGNAL wire_n00iO0lO_dataout : STD_LOGIC; + SIGNAL wire_n00iO0O_dataout : STD_LOGIC; + SIGNAL wire_n00iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00iO0OO_dataout : STD_LOGIC; + SIGNAL wire_n00iO1i_dataout : STD_LOGIC; + SIGNAL wire_n00iO1l_dataout : STD_LOGIC; + SIGNAL wire_n00iO1O_dataout : STD_LOGIC; + SIGNAL wire_n00iOi0i_dataout : STD_LOGIC; + SIGNAL wire_n00iOi0l_dataout : STD_LOGIC; + SIGNAL wire_n00iOi0O_dataout : STD_LOGIC; + SIGNAL wire_n00iOi1i_dataout : STD_LOGIC; + SIGNAL wire_n00iOi1l_dataout : STD_LOGIC; + SIGNAL wire_n00iOi1O_dataout : STD_LOGIC; + SIGNAL wire_n00iOii_dataout : STD_LOGIC; + SIGNAL wire_n00iOiii_dataout : STD_LOGIC; + SIGNAL wire_n00iOiil_dataout : STD_LOGIC; + SIGNAL wire_n00iOiiO_dataout : STD_LOGIC; + SIGNAL wire_n00iOil_dataout : STD_LOGIC; + SIGNAL wire_n00iOili_dataout : STD_LOGIC; + SIGNAL wire_n00iOill_dataout : STD_LOGIC; + SIGNAL wire_n00iOilO_dataout : STD_LOGIC; + SIGNAL wire_n00iOiO_dataout : STD_LOGIC; + SIGNAL wire_n00iOiOi_dataout : STD_LOGIC; + SIGNAL wire_n00iOiOl_dataout : STD_LOGIC; + SIGNAL wire_n00iOiOO_dataout : STD_LOGIC; + SIGNAL wire_n00iOl0i_dataout : STD_LOGIC; + SIGNAL wire_n00iOl0l_dataout : STD_LOGIC; + SIGNAL wire_n00iOl0O_dataout : STD_LOGIC; + SIGNAL wire_n00iOl1i_dataout : STD_LOGIC; + SIGNAL wire_n00iOl1l_dataout : STD_LOGIC; + SIGNAL wire_n00iOl1O_dataout : STD_LOGIC; + SIGNAL wire_n00iOli_dataout : STD_LOGIC; + SIGNAL wire_n00iOlii_dataout : STD_LOGIC; + SIGNAL wire_n00iOlil_dataout : STD_LOGIC; + SIGNAL wire_n00iOliO_dataout : STD_LOGIC; + SIGNAL wire_n00iOll_dataout : STD_LOGIC; + SIGNAL wire_n00iOlli_dataout : STD_LOGIC; + SIGNAL wire_n00iOlll_dataout : STD_LOGIC; + SIGNAL wire_n00iOllO_dataout : STD_LOGIC; + SIGNAL wire_n00iOlO_dataout : STD_LOGIC; + SIGNAL wire_n00iOlOi_dataout : STD_LOGIC; + SIGNAL wire_n00iOlOl_dataout : STD_LOGIC; + SIGNAL wire_n00iOlOO_dataout : STD_LOGIC; + SIGNAL wire_n00iOO0i_dataout : STD_LOGIC; + SIGNAL wire_n00iOO0l_dataout : STD_LOGIC; + SIGNAL wire_n00iOO0O_dataout : STD_LOGIC; + SIGNAL wire_n00iOO1i_dataout : STD_LOGIC; + SIGNAL wire_n00iOO1l_dataout : STD_LOGIC; + SIGNAL wire_n00iOO1O_dataout : STD_LOGIC; + SIGNAL wire_n00iOOi_dataout : STD_LOGIC; + SIGNAL wire_n00iOOii_dataout : STD_LOGIC; + SIGNAL wire_n00iOOil_dataout : STD_LOGIC; + SIGNAL wire_n00iOOiO_dataout : STD_LOGIC; + SIGNAL wire_n00iOOl_dataout : STD_LOGIC; + SIGNAL wire_n00iOOli_dataout : STD_LOGIC; + SIGNAL wire_n00iOOll_dataout : STD_LOGIC; + SIGNAL wire_n00iOOlO_dataout : STD_LOGIC; + SIGNAL wire_n00iOOO_dataout : STD_LOGIC; + SIGNAL wire_n00iOOOi_dataout : STD_LOGIC; + SIGNAL wire_n00iOOOl_dataout : STD_LOGIC; + SIGNAL wire_n00iOOOO_dataout : STD_LOGIC; + SIGNAL wire_n00l00i_dataout : STD_LOGIC; + SIGNAL wire_n00l00l_dataout : STD_LOGIC; + SIGNAL wire_n00l00O_dataout : STD_LOGIC; + SIGNAL wire_n00l010i_dataout : STD_LOGIC; + SIGNAL wire_n00l010l_dataout : STD_LOGIC; + SIGNAL wire_n00l010O_dataout : STD_LOGIC; + SIGNAL wire_n00l011i_dataout : STD_LOGIC; + SIGNAL wire_n00l011l_dataout : STD_LOGIC; + SIGNAL wire_n00l011O_dataout : STD_LOGIC; + SIGNAL wire_n00l01i_dataout : STD_LOGIC; + SIGNAL wire_n00l01ii_dataout : STD_LOGIC; + SIGNAL wire_n00l01il_dataout : STD_LOGIC; + SIGNAL wire_n00l01iO_dataout : STD_LOGIC; + SIGNAL wire_n00l01l_dataout : STD_LOGIC; + SIGNAL wire_n00l01li_dataout : STD_LOGIC; + SIGNAL wire_n00l01ll_dataout : STD_LOGIC; + SIGNAL wire_n00l01lO_dataout : STD_LOGIC; + SIGNAL wire_n00l01O_dataout : STD_LOGIC; + SIGNAL wire_n00l01Oi_dataout : STD_LOGIC; + SIGNAL wire_n00l01Ol_dataout : STD_LOGIC; + SIGNAL wire_n00l0ii_dataout : STD_LOGIC; + SIGNAL wire_n00l0il_dataout : STD_LOGIC; + SIGNAL wire_n00l0iO_dataout : STD_LOGIC; + SIGNAL wire_n00l0li_dataout : STD_LOGIC; + SIGNAL wire_n00l0ll_dataout : STD_LOGIC; + SIGNAL wire_n00l0lO_dataout : STD_LOGIC; + SIGNAL wire_n00l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00l0OO_dataout : STD_LOGIC; + SIGNAL wire_n00l0OOl_dataout : STD_LOGIC; + SIGNAL wire_n00l0OOO_dataout : STD_LOGIC; + SIGNAL wire_n00l100i_dataout : STD_LOGIC; + SIGNAL wire_n00l100l_dataout : STD_LOGIC; + SIGNAL wire_n00l100O_dataout : STD_LOGIC; + SIGNAL wire_n00l101O_dataout : STD_LOGIC; + SIGNAL wire_n00l10i_dataout : STD_LOGIC; + SIGNAL wire_n00l10ii_dataout : STD_LOGIC; + SIGNAL wire_n00l10il_dataout : STD_LOGIC; + SIGNAL wire_n00l10iO_dataout : STD_LOGIC; + SIGNAL wire_n00l10l_dataout : STD_LOGIC; + SIGNAL wire_n00l10li_dataout : STD_LOGIC; + SIGNAL wire_n00l10ll_dataout : STD_LOGIC; + SIGNAL wire_n00l10lO_dataout : STD_LOGIC; + SIGNAL wire_n00l10O_dataout : STD_LOGIC; + SIGNAL wire_n00l10Oi_dataout : STD_LOGIC; + SIGNAL wire_n00l10Ol_dataout : STD_LOGIC; + SIGNAL wire_n00l10OO_dataout : STD_LOGIC; + SIGNAL wire_n00l110i_dataout : STD_LOGIC; + SIGNAL wire_n00l110l_dataout : STD_LOGIC; + SIGNAL wire_n00l110O_dataout : STD_LOGIC; + SIGNAL wire_n00l111i_dataout : STD_LOGIC; + SIGNAL wire_n00l111l_dataout : STD_LOGIC; + SIGNAL wire_n00l111O_dataout : STD_LOGIC; + SIGNAL wire_n00l11i_dataout : STD_LOGIC; + SIGNAL wire_n00l11ii_dataout : STD_LOGIC; + SIGNAL wire_n00l11il_dataout : STD_LOGIC; + SIGNAL wire_n00l11iO_dataout : STD_LOGIC; + SIGNAL wire_n00l11l_dataout : STD_LOGIC; + SIGNAL wire_n00l11li_dataout : STD_LOGIC; + SIGNAL wire_n00l11ll_dataout : STD_LOGIC; + SIGNAL wire_n00l11O_dataout : STD_LOGIC; + SIGNAL wire_n00l1i0i_dataout : STD_LOGIC; + SIGNAL wire_n00l1i0l_dataout : STD_LOGIC; + SIGNAL wire_n00l1i0O_dataout : STD_LOGIC; + SIGNAL wire_n00l1i1i_dataout : STD_LOGIC; + SIGNAL wire_n00l1i1l_dataout : STD_LOGIC; + SIGNAL wire_n00l1i1O_dataout : STD_LOGIC; + SIGNAL wire_n00l1ii_dataout : STD_LOGIC; + SIGNAL wire_n00l1iii_dataout : STD_LOGIC; + SIGNAL wire_n00l1iil_dataout : STD_LOGIC; + SIGNAL wire_n00l1iiO_dataout : STD_LOGIC; + SIGNAL wire_n00l1il_dataout : STD_LOGIC; + SIGNAL wire_n00l1ili_dataout : STD_LOGIC; + SIGNAL wire_n00l1ill_dataout : STD_LOGIC; + SIGNAL wire_n00l1ilO_dataout : STD_LOGIC; + SIGNAL wire_n00l1iO_dataout : STD_LOGIC; + SIGNAL wire_n00l1iOi_dataout : STD_LOGIC; + SIGNAL wire_n00l1iOl_dataout : STD_LOGIC; + SIGNAL wire_n00l1iOO_dataout : STD_LOGIC; + SIGNAL wire_n00l1l0i_dataout : STD_LOGIC; + SIGNAL wire_n00l1l0l_dataout : STD_LOGIC; + SIGNAL wire_n00l1l0O_dataout : STD_LOGIC; + SIGNAL wire_n00l1l1i_dataout : STD_LOGIC; + SIGNAL wire_n00l1l1l_dataout : STD_LOGIC; + SIGNAL wire_n00l1l1O_dataout : STD_LOGIC; + SIGNAL wire_n00l1li_dataout : STD_LOGIC; + SIGNAL wire_n00l1lii_dataout : STD_LOGIC; + SIGNAL wire_n00l1lil_dataout : STD_LOGIC; + SIGNAL wire_n00l1liO_dataout : STD_LOGIC; + SIGNAL wire_n00l1ll_dataout : STD_LOGIC; + SIGNAL wire_n00l1lli_dataout : STD_LOGIC; + SIGNAL wire_n00l1lll_dataout : STD_LOGIC; + SIGNAL wire_n00l1llO_dataout : STD_LOGIC; + SIGNAL wire_n00l1lO_dataout : STD_LOGIC; + SIGNAL wire_n00l1lOi_dataout : STD_LOGIC; + SIGNAL wire_n00l1lOl_dataout : STD_LOGIC; + SIGNAL wire_n00l1lOO_dataout : STD_LOGIC; + SIGNAL wire_n00l1O0i_dataout : STD_LOGIC; + SIGNAL wire_n00l1O0l_dataout : STD_LOGIC; + SIGNAL wire_n00l1O0O_dataout : STD_LOGIC; + SIGNAL wire_n00l1O1i_dataout : STD_LOGIC; + SIGNAL wire_n00l1O1l_dataout : STD_LOGIC; + SIGNAL wire_n00l1O1O_dataout : STD_LOGIC; + SIGNAL wire_n00l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n00l1Oii_dataout : STD_LOGIC; + SIGNAL wire_n00l1Oil_dataout : STD_LOGIC; + SIGNAL wire_n00l1OiO_dataout : STD_LOGIC; + SIGNAL wire_n00l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n00l1Oli_dataout : STD_LOGIC; + SIGNAL wire_n00l1Oll_dataout : STD_LOGIC; + SIGNAL wire_n00l1OlO_dataout : STD_LOGIC; + SIGNAL wire_n00l1OO_dataout : STD_LOGIC; + SIGNAL wire_n00l1OOi_dataout : STD_LOGIC; + SIGNAL wire_n00l1OOl_dataout : STD_LOGIC; + SIGNAL wire_n00l1OOO_dataout : STD_LOGIC; + SIGNAL wire_n00li00i_dataout : STD_LOGIC; + SIGNAL wire_n00li00l_dataout : STD_LOGIC; + SIGNAL wire_n00li00O_dataout : STD_LOGIC; + SIGNAL wire_n00li01i_dataout : STD_LOGIC; + SIGNAL wire_n00li01l_dataout : STD_LOGIC; + SIGNAL wire_n00li01O_dataout : STD_LOGIC; + SIGNAL wire_n00li0i_dataout : STD_LOGIC; + SIGNAL wire_n00li0ii_dataout : STD_LOGIC; + SIGNAL wire_n00li0il_dataout : STD_LOGIC; + SIGNAL wire_n00li0iO_dataout : STD_LOGIC; + SIGNAL wire_n00li0l_dataout : STD_LOGIC; + SIGNAL wire_n00li0li_dataout : STD_LOGIC; + SIGNAL wire_n00li0ll_dataout : STD_LOGIC; + SIGNAL wire_n00li0lO_dataout : STD_LOGIC; + SIGNAL wire_n00li0O_dataout : STD_LOGIC; + SIGNAL wire_n00li0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00li0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00li0OO_dataout : STD_LOGIC; + SIGNAL wire_n00li10i_dataout : STD_LOGIC; + SIGNAL wire_n00li10l_dataout : STD_LOGIC; + SIGNAL wire_n00li10O_dataout : STD_LOGIC; + SIGNAL wire_n00li11i_dataout : STD_LOGIC; + SIGNAL wire_n00li11l_dataout : STD_LOGIC; + SIGNAL wire_n00li11O_dataout : STD_LOGIC; + SIGNAL wire_n00li1i_dataout : STD_LOGIC; + SIGNAL wire_n00li1ii_dataout : STD_LOGIC; + SIGNAL wire_n00li1il_dataout : STD_LOGIC; + SIGNAL wire_n00li1iO_dataout : STD_LOGIC; + SIGNAL wire_n00li1l_dataout : STD_LOGIC; + SIGNAL wire_n00li1li_dataout : STD_LOGIC; + SIGNAL wire_n00li1ll_dataout : STD_LOGIC; + SIGNAL wire_n00li1lO_dataout : STD_LOGIC; + SIGNAL wire_n00li1O_dataout : STD_LOGIC; + SIGNAL wire_n00li1Oi_dataout : STD_LOGIC; + SIGNAL wire_n00li1Ol_dataout : STD_LOGIC; + SIGNAL wire_n00li1OO_dataout : STD_LOGIC; + SIGNAL wire_n00lii0i_dataout : STD_LOGIC; + SIGNAL wire_n00lii0l_dataout : STD_LOGIC; + SIGNAL wire_n00lii0O_dataout : STD_LOGIC; + SIGNAL wire_n00lii1i_dataout : STD_LOGIC; + SIGNAL wire_n00lii1l_dataout : STD_LOGIC; + SIGNAL wire_n00lii1O_dataout : STD_LOGIC; + SIGNAL wire_n00liii_dataout : STD_LOGIC; + SIGNAL wire_n00liiii_dataout : STD_LOGIC; + SIGNAL wire_n00liiil_dataout : STD_LOGIC; + SIGNAL wire_n00liiiO_dataout : STD_LOGIC; + SIGNAL wire_n00liil_dataout : STD_LOGIC; + SIGNAL wire_n00liili_dataout : STD_LOGIC; + SIGNAL wire_n00liill_dataout : STD_LOGIC; + SIGNAL wire_n00liiO_dataout : STD_LOGIC; + SIGNAL wire_n00lili_dataout : STD_LOGIC; + SIGNAL wire_n00lill_dataout : STD_LOGIC; + SIGNAL wire_n00lilli_dataout : STD_LOGIC; + SIGNAL wire_n00lilll_dataout : STD_LOGIC; + SIGNAL wire_n00lillO_dataout : STD_LOGIC; + SIGNAL wire_n00lilO_dataout : STD_LOGIC; + SIGNAL wire_n00lilOi_dataout : STD_LOGIC; + SIGNAL wire_n00lilOl_dataout : STD_LOGIC; + SIGNAL wire_n00liOi_dataout : STD_LOGIC; + SIGNAL wire_n00liOl_dataout : STD_LOGIC; + SIGNAL wire_n00liOO_dataout : STD_LOGIC; + SIGNAL wire_n00liOOl_dataout : STD_LOGIC; + SIGNAL wire_n00liOOO_dataout : STD_LOGIC; + SIGNAL wire_n00ll00i_dataout : STD_LOGIC; + SIGNAL wire_n00ll00l_dataout : STD_LOGIC; + SIGNAL wire_n00ll00O_dataout : STD_LOGIC; + SIGNAL wire_n00ll01i_dataout : STD_LOGIC; + SIGNAL wire_n00ll01l_dataout : STD_LOGIC; + SIGNAL wire_n00ll01O_dataout : STD_LOGIC; + SIGNAL wire_n00ll0i_dataout : STD_LOGIC; + SIGNAL wire_n00ll0ii_dataout : STD_LOGIC; + SIGNAL wire_n00ll0il_dataout : STD_LOGIC; + SIGNAL wire_n00ll0iO_dataout : STD_LOGIC; + SIGNAL wire_n00ll0l_dataout : STD_LOGIC; + SIGNAL wire_n00ll0li_dataout : STD_LOGIC; + SIGNAL wire_n00ll0ll_dataout : STD_LOGIC; + SIGNAL wire_n00ll0lO_dataout : STD_LOGIC; + SIGNAL wire_n00ll0O_dataout : STD_LOGIC; + SIGNAL wire_n00ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00ll0OO_dataout : STD_LOGIC; + SIGNAL wire_n00ll10i_dataout : STD_LOGIC; + SIGNAL wire_n00ll10l_dataout : STD_LOGIC; + SIGNAL wire_n00ll10O_dataout : STD_LOGIC; + SIGNAL wire_n00ll11i_dataout : STD_LOGIC; + SIGNAL wire_n00ll11O_dataout : STD_LOGIC; + SIGNAL wire_n00ll1i_dataout : STD_LOGIC; + SIGNAL wire_n00ll1ii_dataout : STD_LOGIC; + SIGNAL wire_n00ll1il_dataout : STD_LOGIC; + SIGNAL wire_n00ll1iO_dataout : STD_LOGIC; + SIGNAL wire_n00ll1l_dataout : STD_LOGIC; + SIGNAL wire_n00ll1li_dataout : STD_LOGIC; + SIGNAL wire_n00ll1ll_dataout : STD_LOGIC; + SIGNAL wire_n00ll1lO_dataout : STD_LOGIC; + SIGNAL wire_n00ll1O_dataout : STD_LOGIC; + SIGNAL wire_n00ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_n00ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n00ll1OO_dataout : STD_LOGIC; + SIGNAL wire_n00lli0i_dataout : STD_LOGIC; + SIGNAL wire_n00lli0l_dataout : STD_LOGIC; + SIGNAL wire_n00lli0O_dataout : STD_LOGIC; + SIGNAL wire_n00lli1i_dataout : STD_LOGIC; + SIGNAL wire_n00lli1l_dataout : STD_LOGIC; + SIGNAL wire_n00lli1O_dataout : STD_LOGIC; + SIGNAL wire_n00llii_dataout : STD_LOGIC; + SIGNAL wire_n00lliii_dataout : STD_LOGIC; + SIGNAL wire_n00lliil_dataout : STD_LOGIC; + SIGNAL wire_n00lliiO_dataout : STD_LOGIC; + SIGNAL wire_n00llil_dataout : STD_LOGIC; + SIGNAL wire_n00llili_dataout : STD_LOGIC; + SIGNAL wire_n00llill_dataout : STD_LOGIC; + SIGNAL wire_n00llilO_dataout : STD_LOGIC; + SIGNAL wire_n00lliO_dataout : STD_LOGIC; + SIGNAL wire_n00lliOi_dataout : STD_LOGIC; + SIGNAL wire_n00lliOl_dataout : STD_LOGIC; + SIGNAL wire_n00lliOO_dataout : STD_LOGIC; + SIGNAL wire_n00lll1i_dataout : STD_LOGIC; + SIGNAL wire_n00lll1l_dataout : STD_LOGIC; + SIGNAL wire_n00llli_dataout : STD_LOGIC; + SIGNAL wire_n00llll_dataout : STD_LOGIC; + SIGNAL wire_n00lllO_dataout : STD_LOGIC; + SIGNAL wire_n00llOi_dataout : STD_LOGIC; + SIGNAL wire_n00llOl_dataout : STD_LOGIC; + SIGNAL wire_n00llOO_dataout : STD_LOGIC; + SIGNAL wire_n00llOOO_dataout : STD_LOGIC; + SIGNAL wire_n00lO0i_dataout : STD_LOGIC; + SIGNAL wire_n00lO0iO_dataout : STD_LOGIC; + SIGNAL wire_n00lO0l_dataout : STD_LOGIC; + SIGNAL wire_n00lO0li_dataout : STD_LOGIC; + SIGNAL wire_n00lO0ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO0lO_dataout : STD_LOGIC; + SIGNAL wire_n00lO0O_dataout : STD_LOGIC; + SIGNAL wire_n00lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00lO0OO_dataout : STD_LOGIC; + SIGNAL wire_n00lO10i_dataout : STD_LOGIC; + SIGNAL wire_n00lO10l_dataout : STD_LOGIC; + SIGNAL wire_n00lO10O_dataout : STD_LOGIC; + SIGNAL wire_n00lO11i_dataout : STD_LOGIC; + SIGNAL wire_n00lO11l_dataout : STD_LOGIC; + SIGNAL wire_n00lO11O_dataout : STD_LOGIC; + SIGNAL wire_n00lO1i_dataout : STD_LOGIC; + SIGNAL wire_n00lO1ii_dataout : STD_LOGIC; + SIGNAL wire_n00lO1il_dataout : STD_LOGIC; + SIGNAL wire_n00lO1iO_dataout : STD_LOGIC; + SIGNAL wire_n00lO1l_dataout : STD_LOGIC; + SIGNAL wire_n00lO1li_dataout : STD_LOGIC; + SIGNAL wire_n00lO1ll_dataout : STD_LOGIC; + SIGNAL wire_n00lO1O_dataout : STD_LOGIC; + SIGNAL wire_n00lOi1i_dataout : STD_LOGIC; + SIGNAL wire_n00lOi1l_dataout : STD_LOGIC; + SIGNAL wire_n00lOi1O_dataout : STD_LOGIC; + SIGNAL wire_n00lOii_dataout : STD_LOGIC; + SIGNAL wire_n00lOil_dataout : STD_LOGIC; + SIGNAL wire_n00lOiO_dataout : STD_LOGIC; + SIGNAL wire_n00lOli_dataout : STD_LOGIC; + SIGNAL wire_n00lOll_dataout : STD_LOGIC; + SIGNAL wire_n00lOllO_dataout : STD_LOGIC; + SIGNAL wire_n00lOlO_dataout : STD_LOGIC; + SIGNAL wire_n00lOlOi_dataout : STD_LOGIC; + SIGNAL wire_n00lOlOl_dataout : STD_LOGIC; + SIGNAL wire_n00lOlOO_dataout : STD_LOGIC; + SIGNAL wire_n00lOO0i_dataout : STD_LOGIC; + SIGNAL wire_n00lOO0l_dataout : STD_LOGIC; + SIGNAL wire_n00lOO0O_dataout : STD_LOGIC; + SIGNAL wire_n00lOO1i_dataout : STD_LOGIC; + SIGNAL wire_n00lOO1l_dataout : STD_LOGIC; + SIGNAL wire_n00lOO1O_dataout : STD_LOGIC; + SIGNAL wire_n00lOOi_dataout : STD_LOGIC; + SIGNAL wire_n00lOOii_dataout : STD_LOGIC; + SIGNAL wire_n00lOOil_dataout : STD_LOGIC; + SIGNAL wire_n00lOOiO_dataout : STD_LOGIC; + SIGNAL wire_n00lOOl_dataout : STD_LOGIC; + SIGNAL wire_n00lOOli_dataout : STD_LOGIC; + SIGNAL wire_n00lOOll_dataout : STD_LOGIC; + SIGNAL wire_n00lOOlO_dataout : STD_LOGIC; + SIGNAL wire_n00lOOO_dataout : STD_LOGIC; + SIGNAL wire_n00lOOOi_dataout : STD_LOGIC; + SIGNAL wire_n00lOOOl_dataout : STD_LOGIC; + SIGNAL wire_n00lOOOO_dataout : STD_LOGIC; + SIGNAL wire_n00O000i_dataout : STD_LOGIC; + SIGNAL wire_n00O000l_dataout : STD_LOGIC; + SIGNAL wire_n00O000O_dataout : STD_LOGIC; + SIGNAL wire_n00O001l_dataout : STD_LOGIC; + SIGNAL wire_n00O001O_dataout : STD_LOGIC; + SIGNAL wire_n00O00i_dataout : STD_LOGIC; + SIGNAL wire_n00O00il_dataout : STD_LOGIC; + SIGNAL wire_n00O00iO_dataout : STD_LOGIC; + SIGNAL wire_n00O00l_dataout : STD_LOGIC; + SIGNAL wire_n00O00li_dataout : STD_LOGIC; + SIGNAL wire_n00O00O_dataout : STD_LOGIC; + SIGNAL wire_n00O010i_dataout : STD_LOGIC; + SIGNAL wire_n00O010l_dataout : STD_LOGIC; + SIGNAL wire_n00O010O_dataout : STD_LOGIC; + SIGNAL wire_n00O011i_dataout : STD_LOGIC; + SIGNAL wire_n00O011l_dataout : STD_LOGIC; + SIGNAL wire_n00O011O_dataout : STD_LOGIC; + SIGNAL wire_n00O01i_dataout : STD_LOGIC; + SIGNAL wire_n00O01ii_dataout : STD_LOGIC; + SIGNAL wire_n00O01l_dataout : STD_LOGIC; + SIGNAL wire_n00O01lO_dataout : STD_LOGIC; + SIGNAL wire_n00O01O_dataout : STD_LOGIC; + SIGNAL wire_n00O01Oi_dataout : STD_LOGIC; + SIGNAL wire_n00O0i0l_dataout : STD_LOGIC; + SIGNAL wire_n00O0i0O_dataout : STD_LOGIC; + SIGNAL wire_n00O0ii_dataout : STD_LOGIC; + SIGNAL wire_n00O0il_dataout : STD_LOGIC; + SIGNAL wire_n00O0ill_dataout : STD_LOGIC; + SIGNAL wire_n00O0ilO_dataout : STD_LOGIC; + SIGNAL wire_n00O0iO_dataout : STD_LOGIC; + SIGNAL wire_n00O0iOi_dataout : STD_LOGIC; + SIGNAL wire_n00O0iOl_dataout : STD_LOGIC; + SIGNAL wire_n00O0iOO_dataout : STD_LOGIC; + SIGNAL wire_n00O0l0i_dataout : STD_LOGIC; + SIGNAL wire_n00O0l0l_dataout : STD_LOGIC; + SIGNAL wire_n00O0l0O_dataout : STD_LOGIC; + SIGNAL wire_n00O0l1i_dataout : STD_LOGIC; + SIGNAL wire_n00O0l1l_dataout : STD_LOGIC; + SIGNAL wire_n00O0l1O_dataout : STD_LOGIC; + SIGNAL wire_n00O0li_dataout : STD_LOGIC; + SIGNAL wire_n00O0lii_dataout : STD_LOGIC; + SIGNAL wire_n00O0lil_dataout : STD_LOGIC; + SIGNAL wire_n00O0liO_dataout : STD_LOGIC; + SIGNAL wire_n00O0ll_dataout : STD_LOGIC; + SIGNAL wire_n00O0lli_dataout : STD_LOGIC; + SIGNAL wire_n00O0lll_dataout : STD_LOGIC; + SIGNAL wire_n00O0llO_dataout : STD_LOGIC; + SIGNAL wire_n00O0lO_dataout : STD_LOGIC; + SIGNAL wire_n00O0lOi_dataout : STD_LOGIC; + SIGNAL wire_n00O0lOl_dataout : STD_LOGIC; + SIGNAL wire_n00O0lOO_dataout : STD_LOGIC; + SIGNAL wire_n00O0O0i_dataout : STD_LOGIC; + SIGNAL wire_n00O0O0l_dataout : STD_LOGIC; + SIGNAL wire_n00O0O0O_dataout : STD_LOGIC; + SIGNAL wire_n00O0O1i_dataout : STD_LOGIC; + SIGNAL wire_n00O0O1l_dataout : STD_LOGIC; + SIGNAL wire_n00O0O1O_dataout : STD_LOGIC; + SIGNAL wire_n00O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00O0Oii_dataout : STD_LOGIC; + SIGNAL wire_n00O0Oil_dataout : STD_LOGIC; + SIGNAL wire_n00O0OiO_dataout : STD_LOGIC; + SIGNAL wire_n00O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00O0Oli_dataout : STD_LOGIC; + SIGNAL wire_n00O0Oll_dataout : STD_LOGIC; + SIGNAL wire_n00O0OlO_dataout : STD_LOGIC; + SIGNAL wire_n00O0OO_dataout : STD_LOGIC; + SIGNAL wire_n00O0OOi_dataout : STD_LOGIC; + SIGNAL wire_n00O0OOl_dataout : STD_LOGIC; + SIGNAL wire_n00O0OOO_dataout : STD_LOGIC; + SIGNAL wire_n00O10i_dataout : STD_LOGIC; + SIGNAL wire_n00O10l_dataout : STD_LOGIC; + SIGNAL wire_n00O10O_dataout : STD_LOGIC; + SIGNAL wire_n00O111i_dataout : STD_LOGIC; + SIGNAL wire_n00O111l_dataout : STD_LOGIC; + SIGNAL wire_n00O11i_dataout : STD_LOGIC; + SIGNAL wire_n00O11il_dataout : STD_LOGIC; + SIGNAL wire_n00O11il_w_lg_w_lg_w_lg_dataout15319w15325w15326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00O11il_w_lg_w_lg_dataout15319w15325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00O11il_w_lg_dataout15332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00O11il_w_lg_dataout15319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n00O11iO_dataout : STD_LOGIC; + SIGNAL wire_n00O11l_dataout : STD_LOGIC; + SIGNAL wire_n00O11ll_dataout : STD_LOGIC; + SIGNAL wire_n00O11O_dataout : STD_LOGIC; + SIGNAL wire_n00O11Ol_dataout : STD_LOGIC; + SIGNAL wire_n00O1ii_dataout : STD_LOGIC; + SIGNAL wire_n00O1il_dataout : STD_LOGIC; + SIGNAL wire_n00O1ilO_dataout : STD_LOGIC; + SIGNAL wire_n00O1iO_dataout : STD_LOGIC; + SIGNAL wire_n00O1iOi_dataout : STD_LOGIC; + SIGNAL wire_n00O1iOl_dataout : STD_LOGIC; + SIGNAL wire_n00O1iOO_dataout : STD_LOGIC; + SIGNAL wire_n00O1l0i_dataout : STD_LOGIC; + SIGNAL wire_n00O1l0l_dataout : STD_LOGIC; + SIGNAL wire_n00O1l0O_dataout : STD_LOGIC; + SIGNAL wire_n00O1l1i_dataout : STD_LOGIC; + SIGNAL wire_n00O1l1l_dataout : STD_LOGIC; + SIGNAL wire_n00O1l1O_dataout : STD_LOGIC; + SIGNAL wire_n00O1li_dataout : STD_LOGIC; + SIGNAL wire_n00O1lii_dataout : STD_LOGIC; + SIGNAL wire_n00O1lil_dataout : STD_LOGIC; + SIGNAL wire_n00O1liO_dataout : STD_LOGIC; + SIGNAL wire_n00O1ll_dataout : STD_LOGIC; + SIGNAL wire_n00O1lli_dataout : STD_LOGIC; + SIGNAL wire_n00O1lll_dataout : STD_LOGIC; + SIGNAL wire_n00O1llO_dataout : STD_LOGIC; + SIGNAL wire_n00O1lO_dataout : STD_LOGIC; + SIGNAL wire_n00O1lOi_dataout : STD_LOGIC; + SIGNAL wire_n00O1lOl_dataout : STD_LOGIC; + SIGNAL wire_n00O1lOO_dataout : STD_LOGIC; + SIGNAL wire_n00O1O0i_dataout : STD_LOGIC; + SIGNAL wire_n00O1O0l_dataout : STD_LOGIC; + SIGNAL wire_n00O1O0O_dataout : STD_LOGIC; + SIGNAL wire_n00O1O1i_dataout : STD_LOGIC; + SIGNAL wire_n00O1O1l_dataout : STD_LOGIC; + SIGNAL wire_n00O1O1O_dataout : STD_LOGIC; + SIGNAL wire_n00O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n00O1Oii_dataout : STD_LOGIC; + SIGNAL wire_n00O1Oil_dataout : STD_LOGIC; + SIGNAL wire_n00O1OiO_dataout : STD_LOGIC; + SIGNAL wire_n00O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n00O1Oli_dataout : STD_LOGIC; + SIGNAL wire_n00O1Oll_dataout : STD_LOGIC; + SIGNAL wire_n00O1OlO_dataout : STD_LOGIC; + SIGNAL wire_n00O1OO_dataout : STD_LOGIC; + SIGNAL wire_n00O1OOi_dataout : STD_LOGIC; + SIGNAL wire_n00O1OOl_dataout : STD_LOGIC; + SIGNAL wire_n00O1OOO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi00i_dataout : STD_LOGIC; + SIGNAL wire_n00Oi00l_dataout : STD_LOGIC; + SIGNAL wire_n00Oi00O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi01i_dataout : STD_LOGIC; + SIGNAL wire_n00Oi01l_dataout : STD_LOGIC; + SIGNAL wire_n00Oi01O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0il_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0li_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi10i_dataout : STD_LOGIC; + SIGNAL wire_n00Oi10l_dataout : STD_LOGIC; + SIGNAL wire_n00Oi10O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi11i_dataout : STD_LOGIC; + SIGNAL wire_n00Oi11l_dataout : STD_LOGIC; + SIGNAL wire_n00Oi11O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1il_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1li_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_n00Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_n00Oii0i_dataout : STD_LOGIC; + SIGNAL wire_n00Oii0l_dataout : STD_LOGIC; + SIGNAL wire_n00Oii0O_dataout : STD_LOGIC; + SIGNAL wire_n00Oii1i_dataout : STD_LOGIC; + SIGNAL wire_n00Oii1l_dataout : STD_LOGIC; + SIGNAL wire_n00Oii1O_dataout : STD_LOGIC; + SIGNAL wire_n00Oiii_dataout : STD_LOGIC; + SIGNAL wire_n00Oiiii_dataout : STD_LOGIC; + SIGNAL wire_n00Oiiil_dataout : STD_LOGIC; + SIGNAL wire_n00OiiiO_dataout : STD_LOGIC; + SIGNAL wire_n00Oiil_dataout : STD_LOGIC; + SIGNAL wire_n00Oiili_dataout : STD_LOGIC; + SIGNAL wire_n00Oiill_dataout : STD_LOGIC; + SIGNAL wire_n00OiilO_dataout : STD_LOGIC; + SIGNAL wire_n00OiiO_dataout : STD_LOGIC; + SIGNAL wire_n00OiiOi_dataout : STD_LOGIC; + SIGNAL wire_n00OiiOl_dataout : STD_LOGIC; + SIGNAL wire_n00OiiOO_dataout : STD_LOGIC; + SIGNAL wire_n00Oil0i_dataout : STD_LOGIC; + SIGNAL wire_n00Oil0l_dataout : STD_LOGIC; + SIGNAL wire_n00Oil0O_dataout : STD_LOGIC; + SIGNAL wire_n00Oil1i_dataout : STD_LOGIC; + SIGNAL wire_n00Oil1l_dataout : STD_LOGIC; + SIGNAL wire_n00Oil1O_dataout : STD_LOGIC; + SIGNAL wire_n00Oili_dataout : STD_LOGIC; + SIGNAL wire_n00Oilii_dataout : STD_LOGIC; + SIGNAL wire_n00Oilil_dataout : STD_LOGIC; + SIGNAL wire_n00OiliO_dataout : STD_LOGIC; + SIGNAL wire_n00Oill_dataout : STD_LOGIC; + SIGNAL wire_n00Oilli_dataout : STD_LOGIC; + SIGNAL wire_n00Oilll_dataout : STD_LOGIC; + SIGNAL wire_n00OillO_dataout : STD_LOGIC; + SIGNAL wire_n00OilO_dataout : STD_LOGIC; + SIGNAL wire_n00OilOi_dataout : STD_LOGIC; + SIGNAL wire_n00OilOl_dataout : STD_LOGIC; + SIGNAL wire_n00OilOO_dataout : STD_LOGIC; + SIGNAL wire_n00OiO0i_dataout : STD_LOGIC; + SIGNAL wire_n00OiO0l_dataout : STD_LOGIC; + SIGNAL wire_n00OiO0O_dataout : STD_LOGIC; + SIGNAL wire_n00OiO1i_dataout : STD_LOGIC; + SIGNAL wire_n00OiO1l_dataout : STD_LOGIC; + SIGNAL wire_n00OiO1O_dataout : STD_LOGIC; + SIGNAL wire_n00OiOi_dataout : STD_LOGIC; + SIGNAL wire_n00OiOii_dataout : STD_LOGIC; + SIGNAL wire_n00OiOil_dataout : STD_LOGIC; + SIGNAL wire_n00OiOiO_dataout : STD_LOGIC; + SIGNAL wire_n00OiOl_dataout : STD_LOGIC; + SIGNAL wire_n00OiOli_dataout : STD_LOGIC; + SIGNAL wire_n00OiOll_dataout : STD_LOGIC; + SIGNAL wire_n00OiOlO_dataout : STD_LOGIC; + SIGNAL wire_n00OiOO_dataout : STD_LOGIC; + SIGNAL wire_n00OiOOi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol00i_dataout : STD_LOGIC; + SIGNAL wire_n00Ol00l_dataout : STD_LOGIC; + SIGNAL wire_n00Ol00O_dataout : STD_LOGIC; + SIGNAL wire_n00Ol01i_dataout : STD_LOGIC; + SIGNAL wire_n00Ol01l_dataout : STD_LOGIC; + SIGNAL wire_n00Ol01O_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0il_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0li_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1il_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1li_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_n00Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_n00Oli0i_dataout : STD_LOGIC; + SIGNAL wire_n00Oli0l_dataout : STD_LOGIC; + SIGNAL wire_n00Oli0O_dataout : STD_LOGIC; + SIGNAL wire_n00Oli1i_dataout : STD_LOGIC; + SIGNAL wire_n00Oli1l_dataout : STD_LOGIC; + SIGNAL wire_n00Oli1O_dataout : STD_LOGIC; + SIGNAL wire_n00Olii_dataout : STD_LOGIC; + SIGNAL wire_n00Oliii_dataout : STD_LOGIC; + SIGNAL wire_n00Oliil_dataout : STD_LOGIC; + SIGNAL wire_n00OliiO_dataout : STD_LOGIC; + SIGNAL wire_n00Olil_dataout : STD_LOGIC; + SIGNAL wire_n00Olili_dataout : STD_LOGIC; + SIGNAL wire_n00Olill_dataout : STD_LOGIC; + SIGNAL wire_n00OlilO_dataout : STD_LOGIC; + SIGNAL wire_n00OliO_dataout : STD_LOGIC; + SIGNAL wire_n00OliOi_dataout : STD_LOGIC; + SIGNAL wire_n00OliOl_dataout : STD_LOGIC; + SIGNAL wire_n00OliOO_dataout : STD_LOGIC; + SIGNAL wire_n00Oll0i_dataout : STD_LOGIC; + SIGNAL wire_n00Oll0l_dataout : STD_LOGIC; + SIGNAL wire_n00Oll0O_dataout : STD_LOGIC; + SIGNAL wire_n00Oll1i_dataout : STD_LOGIC; + SIGNAL wire_n00Oll1l_dataout : STD_LOGIC; + SIGNAL wire_n00Oll1O_dataout : STD_LOGIC; + SIGNAL wire_n00Olli_dataout : STD_LOGIC; + SIGNAL wire_n00Ollii_dataout : STD_LOGIC; + SIGNAL wire_n00Ollil_dataout : STD_LOGIC; + SIGNAL wire_n00OlliO_dataout : STD_LOGIC; + SIGNAL wire_n00Olll_dataout : STD_LOGIC; + SIGNAL wire_n00Ollli_dataout : STD_LOGIC; + SIGNAL wire_n00Ollll_dataout : STD_LOGIC; + SIGNAL wire_n00OlllO_dataout : STD_LOGIC; + SIGNAL wire_n00OllO_dataout : STD_LOGIC; + SIGNAL wire_n00OllOi_dataout : STD_LOGIC; + SIGNAL wire_n00OllOl_dataout : STD_LOGIC; + SIGNAL wire_n00OllOO_dataout : STD_LOGIC; + SIGNAL wire_n00OlO0i_dataout : STD_LOGIC; + SIGNAL wire_n00OlO0l_dataout : STD_LOGIC; + SIGNAL wire_n00OlO0O_dataout : STD_LOGIC; + SIGNAL wire_n00OlO1i_dataout : STD_LOGIC; + SIGNAL wire_n00OlO1l_dataout : STD_LOGIC; + SIGNAL wire_n00OlO1O_dataout : STD_LOGIC; + SIGNAL wire_n00OlOi_dataout : STD_LOGIC; + SIGNAL wire_n00OlOii_dataout : STD_LOGIC; + SIGNAL wire_n00OlOil_dataout : STD_LOGIC; + SIGNAL wire_n00OlOiO_dataout : STD_LOGIC; + SIGNAL wire_n00OlOl_dataout : STD_LOGIC; + SIGNAL wire_n00OlOli_dataout : STD_LOGIC; + SIGNAL wire_n00OlOll_dataout : STD_LOGIC; + SIGNAL wire_n00OlOlO_dataout : STD_LOGIC; + SIGNAL wire_n00OlOO_dataout : STD_LOGIC; + SIGNAL wire_n00OlOOi_dataout : STD_LOGIC; + SIGNAL wire_n00OlOOl_dataout : STD_LOGIC; + SIGNAL wire_n00OlOOO_dataout : STD_LOGIC; + SIGNAL wire_n00OO0i_dataout : STD_LOGIC; + SIGNAL wire_n00OO0l_dataout : STD_LOGIC; + SIGNAL wire_n00OO0li_dataout : STD_LOGIC; + SIGNAL wire_n00OO0ll_dataout : STD_LOGIC; + SIGNAL wire_n00OO0lO_dataout : STD_LOGIC; + SIGNAL wire_n00OO0O_dataout : STD_LOGIC; + SIGNAL wire_n00OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n00OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n00OO0OO_dataout : STD_LOGIC; + SIGNAL wire_n00OO10i_dataout : STD_LOGIC; + SIGNAL wire_n00OO10l_dataout : STD_LOGIC; + SIGNAL wire_n00OO10O_dataout : STD_LOGIC; + SIGNAL wire_n00OO11i_dataout : STD_LOGIC; + SIGNAL wire_n00OO11l_dataout : STD_LOGIC; + SIGNAL wire_n00OO11O_dataout : STD_LOGIC; + SIGNAL wire_n00OO1i_dataout : STD_LOGIC; + SIGNAL wire_n00OO1ii_dataout : STD_LOGIC; + SIGNAL wire_n00OO1il_dataout : STD_LOGIC; + SIGNAL wire_n00OO1iO_dataout : STD_LOGIC; + SIGNAL wire_n00OO1l_dataout : STD_LOGIC; + SIGNAL wire_n00OO1li_dataout : STD_LOGIC; + SIGNAL wire_n00OO1ll_dataout : STD_LOGIC; + SIGNAL wire_n00OO1lO_dataout : STD_LOGIC; + SIGNAL wire_n00OO1O_dataout : STD_LOGIC; + SIGNAL wire_n00OOi0i_dataout : STD_LOGIC; + SIGNAL wire_n00OOi0l_dataout : STD_LOGIC; + SIGNAL wire_n00OOi0O_dataout : STD_LOGIC; + SIGNAL wire_n00OOi1i_dataout : STD_LOGIC; + SIGNAL wire_n00OOi1l_dataout : STD_LOGIC; + SIGNAL wire_n00OOi1O_dataout : STD_LOGIC; + SIGNAL wire_n00OOii_dataout : STD_LOGIC; + SIGNAL wire_n00OOiii_dataout : STD_LOGIC; + SIGNAL wire_n00OOiil_dataout : STD_LOGIC; + SIGNAL wire_n00OOiiO_dataout : STD_LOGIC; + SIGNAL wire_n00OOil_dataout : STD_LOGIC; + SIGNAL wire_n00OOili_dataout : STD_LOGIC; + SIGNAL wire_n00OOill_dataout : STD_LOGIC; + SIGNAL wire_n00OOilO_dataout : STD_LOGIC; + SIGNAL wire_n00OOiO_dataout : STD_LOGIC; + SIGNAL wire_n00OOl0i_dataout : STD_LOGIC; + SIGNAL wire_n00OOl1O_dataout : STD_LOGIC; + SIGNAL wire_n00OOli_dataout : STD_LOGIC; + SIGNAL wire_n00OOll_dataout : STD_LOGIC; + SIGNAL wire_n00OOlO_dataout : STD_LOGIC; + SIGNAL wire_n00OOOi_dataout : STD_LOGIC; + SIGNAL wire_n00OOOiO_dataout : STD_LOGIC; + SIGNAL wire_n00OOOl_dataout : STD_LOGIC; + SIGNAL wire_n00OOOli_dataout : STD_LOGIC; + SIGNAL wire_n00OOOll_dataout : STD_LOGIC; + SIGNAL wire_n00OOOlO_dataout : STD_LOGIC; + SIGNAL wire_n00OOOO_dataout : STD_LOGIC; + SIGNAL wire_n00OOOOi_dataout : STD_LOGIC; + SIGNAL wire_n00OOOOl_dataout : STD_LOGIC; + SIGNAL wire_n00OOOOO_dataout : STD_LOGIC; + SIGNAL wire_n01000i_dataout : STD_LOGIC; + SIGNAL wire_n01000l_dataout : STD_LOGIC; + SIGNAL wire_n01000O_dataout : STD_LOGIC; + SIGNAL wire_n01001i_dataout : STD_LOGIC; + SIGNAL wire_n01001l_dataout : STD_LOGIC; + SIGNAL wire_n01001O_dataout : STD_LOGIC; + SIGNAL wire_n0100ii_dataout : STD_LOGIC; + SIGNAL wire_n0100il_dataout : STD_LOGIC; + SIGNAL wire_n0100iO_dataout : STD_LOGIC; + SIGNAL wire_n0100l0O_dataout : STD_LOGIC; + SIGNAL wire_n0100li_dataout : STD_LOGIC; + SIGNAL wire_n0100lii_dataout : STD_LOGIC; + SIGNAL wire_n0100lil_dataout : STD_LOGIC; + SIGNAL wire_n0100liO_dataout : STD_LOGIC; + SIGNAL wire_n0100ll_dataout : STD_LOGIC; + SIGNAL wire_n0100lli_dataout : STD_LOGIC; + SIGNAL wire_n0100lll_dataout : STD_LOGIC; + SIGNAL wire_n0100llO_dataout : STD_LOGIC; + SIGNAL wire_n0100lO_dataout : STD_LOGIC; + SIGNAL wire_n0100lOi_dataout : STD_LOGIC; + SIGNAL wire_n0100lOl_dataout : STD_LOGIC; + SIGNAL wire_n0100lOO_dataout : STD_LOGIC; + SIGNAL wire_n0100O0i_dataout : STD_LOGIC; + SIGNAL wire_n0100O0l_dataout : STD_LOGIC; + SIGNAL wire_n0100O0O_dataout : STD_LOGIC; + SIGNAL wire_n0100O1i_dataout : STD_LOGIC; + SIGNAL wire_n0100O1l_dataout : STD_LOGIC; + SIGNAL wire_n0100O1O_dataout : STD_LOGIC; + SIGNAL wire_n0100Oi_dataout : STD_LOGIC; + SIGNAL wire_n0100Oii_dataout : STD_LOGIC; + SIGNAL wire_n0100Oil_dataout : STD_LOGIC; + SIGNAL wire_n0100OiO_dataout : STD_LOGIC; + SIGNAL wire_n0100Ol_dataout : STD_LOGIC; + SIGNAL wire_n0100Oli_dataout : STD_LOGIC; + SIGNAL wire_n0100Oll_dataout : STD_LOGIC; + SIGNAL wire_n0100OlO_dataout : STD_LOGIC; + SIGNAL wire_n0100OO_dataout : STD_LOGIC; + SIGNAL wire_n0100OOi_dataout : STD_LOGIC; + SIGNAL wire_n0100OOl_dataout : STD_LOGIC; + SIGNAL wire_n0100OOO_dataout : STD_LOGIC; + SIGNAL wire_n010100i_dataout : STD_LOGIC; + SIGNAL wire_n010100l_dataout : STD_LOGIC; + SIGNAL wire_n010100O_dataout : STD_LOGIC; + SIGNAL wire_n010101i_dataout : STD_LOGIC; + SIGNAL wire_n010101l_dataout : STD_LOGIC; + SIGNAL wire_n010101O_dataout : STD_LOGIC; + SIGNAL wire_n01010i_dataout : STD_LOGIC; + SIGNAL wire_n01010ii_dataout : STD_LOGIC; + SIGNAL wire_n01010il_dataout : STD_LOGIC; + SIGNAL wire_n01010iO_dataout : STD_LOGIC; + SIGNAL wire_n01010l_dataout : STD_LOGIC; + SIGNAL wire_n01010li_dataout : STD_LOGIC; + SIGNAL wire_n01010ll_dataout : STD_LOGIC; + SIGNAL wire_n01010lO_dataout : STD_LOGIC; + SIGNAL wire_n01010O_dataout : STD_LOGIC; + SIGNAL wire_n01010Oi_dataout : STD_LOGIC; + SIGNAL wire_n01010Ol_dataout : STD_LOGIC; + SIGNAL wire_n01010OO_dataout : STD_LOGIC; + SIGNAL wire_n010110i_dataout : STD_LOGIC; + SIGNAL wire_n010110l_dataout : STD_LOGIC; + SIGNAL wire_n010110O_dataout : STD_LOGIC; + SIGNAL wire_n010111i_dataout : STD_LOGIC; + SIGNAL wire_n010111l_dataout : STD_LOGIC; + SIGNAL wire_n010111O_dataout : STD_LOGIC; + SIGNAL wire_n01011i_dataout : STD_LOGIC; + SIGNAL wire_n01011ii_dataout : STD_LOGIC; + SIGNAL wire_n01011il_dataout : STD_LOGIC; + SIGNAL wire_n01011iO_dataout : STD_LOGIC; + SIGNAL wire_n01011l_dataout : STD_LOGIC; + SIGNAL wire_n01011li_dataout : STD_LOGIC; + SIGNAL wire_n01011ll_dataout : STD_LOGIC; + SIGNAL wire_n01011lO_dataout : STD_LOGIC; + SIGNAL wire_n01011O_dataout : STD_LOGIC; + SIGNAL wire_n01011Oi_dataout : STD_LOGIC; + SIGNAL wire_n01011Ol_dataout : STD_LOGIC; + SIGNAL wire_n01011OO_dataout : STD_LOGIC; + SIGNAL wire_n0101i0i_dataout : STD_LOGIC; + SIGNAL wire_n0101i0l_dataout : STD_LOGIC; + SIGNAL wire_n0101i0O_dataout : STD_LOGIC; + SIGNAL wire_n0101i1i_dataout : STD_LOGIC; + SIGNAL wire_n0101i1l_dataout : STD_LOGIC; + SIGNAL wire_n0101i1O_dataout : STD_LOGIC; + SIGNAL wire_n0101ii_dataout : STD_LOGIC; + SIGNAL wire_n0101iii_dataout : STD_LOGIC; + SIGNAL wire_n0101iil_dataout : STD_LOGIC; + SIGNAL wire_n0101iiO_dataout : STD_LOGIC; + SIGNAL wire_n0101il_dataout : STD_LOGIC; + SIGNAL wire_n0101ili_dataout : STD_LOGIC; + SIGNAL wire_n0101ill_dataout : STD_LOGIC; + SIGNAL wire_n0101ilO_dataout : STD_LOGIC; + SIGNAL wire_n0101iO_dataout : STD_LOGIC; + SIGNAL wire_n0101iOi_dataout : STD_LOGIC; + SIGNAL wire_n0101iOl_dataout : STD_LOGIC; + SIGNAL wire_n0101iOO_dataout : STD_LOGIC; + SIGNAL wire_n0101l0i_dataout : STD_LOGIC; + SIGNAL wire_n0101l0l_dataout : STD_LOGIC; + SIGNAL wire_n0101l0O_dataout : STD_LOGIC; + SIGNAL wire_n0101l1i_dataout : STD_LOGIC; + SIGNAL wire_n0101l1l_dataout : STD_LOGIC; + SIGNAL wire_n0101l1O_dataout : STD_LOGIC; + SIGNAL wire_n0101li_dataout : STD_LOGIC; + SIGNAL wire_n0101lii_dataout : STD_LOGIC; + SIGNAL wire_n0101lil_dataout : STD_LOGIC; + SIGNAL wire_n0101liO_dataout : STD_LOGIC; + SIGNAL wire_n0101ll_dataout : STD_LOGIC; + SIGNAL wire_n0101lli_dataout : STD_LOGIC; + SIGNAL wire_n0101lll_dataout : STD_LOGIC; + SIGNAL wire_n0101llO_dataout : STD_LOGIC; + SIGNAL wire_n0101lO_dataout : STD_LOGIC; + SIGNAL wire_n0101lOi_dataout : STD_LOGIC; + SIGNAL wire_n0101lOl_dataout : STD_LOGIC; + SIGNAL wire_n0101lOO_dataout : STD_LOGIC; + SIGNAL wire_n0101O0i_dataout : STD_LOGIC; + SIGNAL wire_n0101O0l_dataout : STD_LOGIC; + SIGNAL wire_n0101O0O_dataout : STD_LOGIC; + SIGNAL wire_n0101O1i_dataout : STD_LOGIC; + SIGNAL wire_n0101O1l_dataout : STD_LOGIC; + SIGNAL wire_n0101O1O_dataout : STD_LOGIC; + SIGNAL wire_n0101Oi_dataout : STD_LOGIC; + SIGNAL wire_n0101Ol_dataout : STD_LOGIC; + SIGNAL wire_n0101OO_dataout : STD_LOGIC; + SIGNAL wire_n010i01i_dataout : STD_LOGIC; + SIGNAL wire_n010i01l_dataout : STD_LOGIC; + SIGNAL wire_n010i01O_dataout : STD_LOGIC; + SIGNAL wire_n010i0i_dataout : STD_LOGIC; + SIGNAL wire_n010i0l_dataout : STD_LOGIC; + SIGNAL wire_n010i0O_dataout : STD_LOGIC; + SIGNAL wire_n010i10i_dataout : STD_LOGIC; + SIGNAL wire_n010i10l_dataout : STD_LOGIC; + SIGNAL wire_n010i10O_dataout : STD_LOGIC; + SIGNAL wire_n010i11i_dataout : STD_LOGIC; + SIGNAL wire_n010i11l_dataout : STD_LOGIC; + SIGNAL wire_n010i11O_dataout : STD_LOGIC; + SIGNAL wire_n010i1i_dataout : STD_LOGIC; + SIGNAL wire_n010i1ii_dataout : STD_LOGIC; + SIGNAL wire_n010i1il_dataout : STD_LOGIC; + SIGNAL wire_n010i1iO_dataout : STD_LOGIC; + SIGNAL wire_n010i1l_dataout : STD_LOGIC; + SIGNAL wire_n010i1li_dataout : STD_LOGIC; + SIGNAL wire_n010i1ll_dataout : STD_LOGIC; + SIGNAL wire_n010i1lO_dataout : STD_LOGIC; + SIGNAL wire_n010i1O_dataout : STD_LOGIC; + SIGNAL wire_n010i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n010i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n010i1OO_dataout : STD_LOGIC; + SIGNAL wire_n010ii0i_dataout : STD_LOGIC; + SIGNAL wire_n010ii0l_dataout : STD_LOGIC; + SIGNAL wire_n010ii0O_dataout : STD_LOGIC; + SIGNAL wire_n010ii1l_dataout : STD_LOGIC; + SIGNAL wire_n010ii1O_dataout : STD_LOGIC; + SIGNAL wire_n010iii_dataout : STD_LOGIC; + SIGNAL wire_n010iil_dataout : STD_LOGIC; + SIGNAL wire_n010iiO_dataout : STD_LOGIC; + SIGNAL wire_n010il0O_dataout : STD_LOGIC; + SIGNAL wire_n010ili_dataout : STD_LOGIC; + SIGNAL wire_n010ilii_dataout : STD_LOGIC; + SIGNAL wire_n010ilil_dataout : STD_LOGIC; + SIGNAL wire_n010ill_dataout : STD_LOGIC; + SIGNAL wire_n010illi_dataout : STD_LOGIC; + SIGNAL wire_n010illl_dataout : STD_LOGIC; + SIGNAL wire_n010illO_dataout : STD_LOGIC; + SIGNAL wire_n010ilO_dataout : STD_LOGIC; + SIGNAL wire_n010ilOi_dataout : STD_LOGIC; + SIGNAL wire_n010ilOl_dataout : STD_LOGIC; + SIGNAL wire_n010ilOO_dataout : STD_LOGIC; + SIGNAL wire_n010iO0i_dataout : STD_LOGIC; + SIGNAL wire_n010iO0l_dataout : STD_LOGIC; + SIGNAL wire_n010iO0O_dataout : STD_LOGIC; + SIGNAL wire_n010iO1i_dataout : STD_LOGIC; + SIGNAL wire_n010iO1l_dataout : STD_LOGIC; + SIGNAL wire_n010iO1O_dataout : STD_LOGIC; + SIGNAL wire_n010iOi_dataout : STD_LOGIC; + SIGNAL wire_n010iOii_dataout : STD_LOGIC; + SIGNAL wire_n010iOil_dataout : STD_LOGIC; + SIGNAL wire_n010iOiO_dataout : STD_LOGIC; + SIGNAL wire_n010iOl_dataout : STD_LOGIC; + SIGNAL wire_n010iOli_dataout : STD_LOGIC; + SIGNAL wire_n010iOll_dataout : STD_LOGIC; + SIGNAL wire_n010iOlO_dataout : STD_LOGIC; + SIGNAL wire_n010iOO_dataout : STD_LOGIC; + SIGNAL wire_n010iOOi_dataout : STD_LOGIC; + SIGNAL wire_n010iOOl_dataout : STD_LOGIC; + SIGNAL wire_n010iOOO_dataout : STD_LOGIC; + SIGNAL wire_n010l00i_dataout : STD_LOGIC; + SIGNAL wire_n010l00l_dataout : STD_LOGIC; + SIGNAL wire_n010l00O_dataout : STD_LOGIC; + SIGNAL wire_n010l01i_dataout : STD_LOGIC; + SIGNAL wire_n010l01l_dataout : STD_LOGIC; + SIGNAL wire_n010l01O_dataout : STD_LOGIC; + SIGNAL wire_n010l0i_dataout : STD_LOGIC; + SIGNAL wire_n010l0ii_dataout : STD_LOGIC; + SIGNAL wire_n010l0il_dataout : STD_LOGIC; + SIGNAL wire_n010l0iO_dataout : STD_LOGIC; + SIGNAL wire_n010l0l_dataout : STD_LOGIC; + SIGNAL wire_n010l0O_dataout : STD_LOGIC; + SIGNAL wire_n010l10i_dataout : STD_LOGIC; + SIGNAL wire_n010l10l_dataout : STD_LOGIC; + SIGNAL wire_n010l10O_dataout : STD_LOGIC; + SIGNAL wire_n010l11i_dataout : STD_LOGIC; + SIGNAL wire_n010l11l_dataout : STD_LOGIC; + SIGNAL wire_n010l11O_dataout : STD_LOGIC; + SIGNAL wire_n010l1i_dataout : STD_LOGIC; + SIGNAL wire_n010l1ii_dataout : STD_LOGIC; + SIGNAL wire_n010l1il_dataout : STD_LOGIC; + SIGNAL wire_n010l1iO_dataout : STD_LOGIC; + SIGNAL wire_n010l1l_dataout : STD_LOGIC; + SIGNAL wire_n010l1li_dataout : STD_LOGIC; + SIGNAL wire_n010l1ll_dataout : STD_LOGIC; + SIGNAL wire_n010l1lO_dataout : STD_LOGIC; + SIGNAL wire_n010l1O_dataout : STD_LOGIC; + SIGNAL wire_n010l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n010l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n010l1OO_dataout : STD_LOGIC; + SIGNAL wire_n010lii_dataout : STD_LOGIC; + SIGNAL wire_n010lil_dataout : STD_LOGIC; + SIGNAL wire_n010liO_dataout : STD_LOGIC; + SIGNAL wire_n010lli_dataout : STD_LOGIC; + SIGNAL wire_n010llii_dataout : STD_LOGIC; + SIGNAL wire_n010llil_dataout : STD_LOGIC; + SIGNAL wire_n010lliO_dataout : STD_LOGIC; + SIGNAL wire_n010lll_dataout : STD_LOGIC; + SIGNAL wire_n010llli_dataout : STD_LOGIC; + SIGNAL wire_n010llll_dataout : STD_LOGIC; + SIGNAL wire_n010lllO_dataout : STD_LOGIC; + SIGNAL wire_n010llO_dataout : STD_LOGIC; + SIGNAL wire_n010llOi_dataout : STD_LOGIC; + SIGNAL wire_n010llOl_dataout : STD_LOGIC; + SIGNAL wire_n010llOO_dataout : STD_LOGIC; + SIGNAL wire_n010lO1i_dataout : STD_LOGIC; + SIGNAL wire_n010lO1l_dataout : STD_LOGIC; + SIGNAL wire_n010lO1O_dataout : STD_LOGIC; + SIGNAL wire_n010lOi_dataout : STD_LOGIC; + SIGNAL wire_n010lOl_dataout : STD_LOGIC; + SIGNAL wire_n010lOO_dataout : STD_LOGIC; + SIGNAL wire_n010O0i_dataout : STD_LOGIC; + SIGNAL wire_n010O0l_dataout : STD_LOGIC; + SIGNAL wire_n010O0O_dataout : STD_LOGIC; + SIGNAL wire_n010O10i_dataout : STD_LOGIC; + SIGNAL wire_n010O10l_dataout : STD_LOGIC; + SIGNAL wire_n010O10O_dataout : STD_LOGIC; + SIGNAL wire_n010O11i_dataout : STD_LOGIC; + SIGNAL wire_n010O11l_dataout : STD_LOGIC; + SIGNAL wire_n010O11O_dataout : STD_LOGIC; + SIGNAL wire_n010O1i_dataout : STD_LOGIC; + SIGNAL wire_n010O1ii_dataout : STD_LOGIC; + SIGNAL wire_n010O1il_dataout : STD_LOGIC; + SIGNAL wire_n010O1iO_dataout : STD_LOGIC; + SIGNAL wire_n010O1l_dataout : STD_LOGIC; + SIGNAL wire_n010O1li_dataout : STD_LOGIC; + SIGNAL wire_n010O1O_dataout : STD_LOGIC; + SIGNAL wire_n010Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n010Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n010Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n010Oii_dataout : STD_LOGIC; + SIGNAL wire_n010Oiii_dataout : STD_LOGIC; + SIGNAL wire_n010Oiil_dataout : STD_LOGIC; + SIGNAL wire_n010OiiO_dataout : STD_LOGIC; + SIGNAL wire_n010Oil_dataout : STD_LOGIC; + SIGNAL wire_n010Oili_dataout : STD_LOGIC; + SIGNAL wire_n010Oill_dataout : STD_LOGIC; + SIGNAL wire_n010OilO_dataout : STD_LOGIC; + SIGNAL wire_n010OiO_dataout : STD_LOGIC; + SIGNAL wire_n010OiOi_dataout : STD_LOGIC; + SIGNAL wire_n010OiOl_dataout : STD_LOGIC; + SIGNAL wire_n010OiOO_dataout : STD_LOGIC; + SIGNAL wire_n010Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n010Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n010Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n010Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n010Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n010Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n010Oli_dataout : STD_LOGIC; + SIGNAL wire_n010Olii_dataout : STD_LOGIC; + SIGNAL wire_n010Olil_dataout : STD_LOGIC; + SIGNAL wire_n010OliO_dataout : STD_LOGIC; + SIGNAL wire_n010Oll_dataout : STD_LOGIC; + SIGNAL wire_n010OlO_dataout : STD_LOGIC; + SIGNAL wire_n010OlOO_dataout : STD_LOGIC; + SIGNAL wire_n010OlOO_w_lg_w_lg_w_lg_dataout17133w17139w17140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n010OlOO_w_lg_w_lg_dataout17133w17139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n010OlOO_w_lg_dataout17146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n010OlOO_w_lg_dataout17133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n010OO0O_dataout : STD_LOGIC; + SIGNAL wire_n010OO1i_dataout : STD_LOGIC; + SIGNAL wire_n010OO1O_dataout : STD_LOGIC; + SIGNAL wire_n010OOi_dataout : STD_LOGIC; + SIGNAL wire_n010OOl_dataout : STD_LOGIC; + SIGNAL wire_n010OOO_dataout : STD_LOGIC; + SIGNAL wire_n01100i_dataout : STD_LOGIC; + SIGNAL wire_n01100l_dataout : STD_LOGIC; + SIGNAL wire_n01100O_dataout : STD_LOGIC; + SIGNAL wire_n01101i_dataout : STD_LOGIC; + SIGNAL wire_n01101l_dataout : STD_LOGIC; + SIGNAL wire_n01101O_dataout : STD_LOGIC; + SIGNAL wire_n0110ii_dataout : STD_LOGIC; + SIGNAL wire_n0110il_dataout : STD_LOGIC; + SIGNAL wire_n0110iO_dataout : STD_LOGIC; + SIGNAL wire_n0110li_dataout : STD_LOGIC; + SIGNAL wire_n0110ll_dataout : STD_LOGIC; + SIGNAL wire_n0110lO_dataout : STD_LOGIC; + SIGNAL wire_n0110Oi_dataout : STD_LOGIC; + SIGNAL wire_n0110Ol_dataout : STD_LOGIC; + SIGNAL wire_n0110OO_dataout : STD_LOGIC; + SIGNAL wire_n0110OOO_dataout : STD_LOGIC; + SIGNAL wire_n011100i_dataout : STD_LOGIC; + SIGNAL wire_n011100l_dataout : STD_LOGIC; + SIGNAL wire_n011100O_dataout : STD_LOGIC; + SIGNAL wire_n011101i_dataout : STD_LOGIC; + SIGNAL wire_n011101l_dataout : STD_LOGIC; + SIGNAL wire_n011101O_dataout : STD_LOGIC; + SIGNAL wire_n01110i_dataout : STD_LOGIC; + SIGNAL wire_n01110ii_dataout : STD_LOGIC; + SIGNAL wire_n01110il_dataout : STD_LOGIC; + SIGNAL wire_n01110iO_dataout : STD_LOGIC; + SIGNAL wire_n01110l_dataout : STD_LOGIC; + SIGNAL wire_n01110li_dataout : STD_LOGIC; + SIGNAL wire_n01110ll_dataout : STD_LOGIC; + SIGNAL wire_n01110lO_dataout : STD_LOGIC; + SIGNAL wire_n01110O_dataout : STD_LOGIC; + SIGNAL wire_n01110Oi_dataout : STD_LOGIC; + SIGNAL wire_n01110Ol_dataout : STD_LOGIC; + SIGNAL wire_n01110OO_dataout : STD_LOGIC; + SIGNAL wire_n01111i_dataout : STD_LOGIC; + SIGNAL wire_n01111iO_dataout : STD_LOGIC; + SIGNAL wire_n01111l_dataout : STD_LOGIC; + SIGNAL wire_n01111li_dataout : STD_LOGIC; + SIGNAL wire_n01111ll_dataout : STD_LOGIC; + SIGNAL wire_n01111lO_dataout : STD_LOGIC; + SIGNAL wire_n01111O_dataout : STD_LOGIC; + SIGNAL wire_n01111Oi_dataout : STD_LOGIC; + SIGNAL wire_n01111Ol_dataout : STD_LOGIC; + SIGNAL wire_n01111OO_dataout : STD_LOGIC; + SIGNAL wire_n0111i0i_dataout : STD_LOGIC; + SIGNAL wire_n0111i0l_dataout : STD_LOGIC; + SIGNAL wire_n0111i0O_dataout : STD_LOGIC; + SIGNAL wire_n0111i1i_dataout : STD_LOGIC; + SIGNAL wire_n0111i1l_dataout : STD_LOGIC; + SIGNAL wire_n0111i1O_dataout : STD_LOGIC; + SIGNAL wire_n0111ii_dataout : STD_LOGIC; + SIGNAL wire_n0111iii_dataout : STD_LOGIC; + SIGNAL wire_n0111iil_dataout : STD_LOGIC; + SIGNAL wire_n0111iiO_dataout : STD_LOGIC; + SIGNAL wire_n0111il_dataout : STD_LOGIC; + SIGNAL wire_n0111ili_dataout : STD_LOGIC; + SIGNAL wire_n0111ill_dataout : STD_LOGIC; + SIGNAL wire_n0111ilO_dataout : STD_LOGIC; + SIGNAL wire_n0111iO_dataout : STD_LOGIC; + SIGNAL wire_n0111iOi_dataout : STD_LOGIC; + SIGNAL wire_n0111iOl_dataout : STD_LOGIC; + SIGNAL wire_n0111iOO_dataout : STD_LOGIC; + SIGNAL wire_n0111l0i_dataout : STD_LOGIC; + SIGNAL wire_n0111l0l_dataout : STD_LOGIC; + SIGNAL wire_n0111l0O_dataout : STD_LOGIC; + SIGNAL wire_n0111l1i_dataout : STD_LOGIC; + SIGNAL wire_n0111l1l_dataout : STD_LOGIC; + SIGNAL wire_n0111l1O_dataout : STD_LOGIC; + SIGNAL wire_n0111li_dataout : STD_LOGIC; + SIGNAL wire_n0111lii_dataout : STD_LOGIC; + SIGNAL wire_n0111lil_dataout : STD_LOGIC; + SIGNAL wire_n0111liO_dataout : STD_LOGIC; + SIGNAL wire_n0111ll_dataout : STD_LOGIC; + SIGNAL wire_n0111lli_dataout : STD_LOGIC; + SIGNAL wire_n0111lll_dataout : STD_LOGIC; + SIGNAL wire_n0111lO_dataout : STD_LOGIC; + SIGNAL wire_n0111Oi_dataout : STD_LOGIC; + SIGNAL wire_n0111Ol_dataout : STD_LOGIC; + SIGNAL wire_n0111OO_dataout : STD_LOGIC; + SIGNAL wire_n011i00O_dataout : STD_LOGIC; + SIGNAL wire_n011i01i_dataout : STD_LOGIC; + SIGNAL wire_n011i01l_dataout : STD_LOGIC; + SIGNAL wire_n011i01O_dataout : STD_LOGIC; + SIGNAL wire_n011i0i_dataout : STD_LOGIC; + SIGNAL wire_n011i0ii_dataout : STD_LOGIC; + SIGNAL wire_n011i0il_dataout : STD_LOGIC; + SIGNAL wire_n011i0l_dataout : STD_LOGIC; + SIGNAL wire_n011i0O_dataout : STD_LOGIC; + SIGNAL wire_n011i10i_dataout : STD_LOGIC; + SIGNAL wire_n011i10l_dataout : STD_LOGIC; + SIGNAL wire_n011i10O_dataout : STD_LOGIC; + SIGNAL wire_n011i11i_dataout : STD_LOGIC; + SIGNAL wire_n011i11l_dataout : STD_LOGIC; + SIGNAL wire_n011i11O_dataout : STD_LOGIC; + SIGNAL wire_n011i1i_dataout : STD_LOGIC; + SIGNAL wire_n011i1ii_dataout : STD_LOGIC; + SIGNAL wire_n011i1il_dataout : STD_LOGIC; + SIGNAL wire_n011i1l_dataout : STD_LOGIC; + SIGNAL wire_n011i1O_dataout : STD_LOGIC; + SIGNAL wire_n011i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n011i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n011i1OO_dataout : STD_LOGIC; + SIGNAL wire_n011ii0i_dataout : STD_LOGIC; + SIGNAL wire_n011ii0l_dataout : STD_LOGIC; + SIGNAL wire_n011ii0O_dataout : STD_LOGIC; + SIGNAL wire_n011ii1O_dataout : STD_LOGIC; + SIGNAL wire_n011iii_dataout : STD_LOGIC; + SIGNAL wire_n011iiii_dataout : STD_LOGIC; + SIGNAL wire_n011iiil_dataout : STD_LOGIC; + SIGNAL wire_n011iiiO_dataout : STD_LOGIC; + SIGNAL wire_n011iil_dataout : STD_LOGIC; + SIGNAL wire_n011iili_dataout : STD_LOGIC; + SIGNAL wire_n011iill_dataout : STD_LOGIC; + SIGNAL wire_n011iilO_dataout : STD_LOGIC; + SIGNAL wire_n011iiO_dataout : STD_LOGIC; + SIGNAL wire_n011iiOi_dataout : STD_LOGIC; + SIGNAL wire_n011iiOl_dataout : STD_LOGIC; + SIGNAL wire_n011iiOO_dataout : STD_LOGIC; + SIGNAL wire_n011il1i_dataout : STD_LOGIC; + SIGNAL wire_n011il1l_dataout : STD_LOGIC; + SIGNAL wire_n011ili_dataout : STD_LOGIC; + SIGNAL wire_n011ilii_dataout : STD_LOGIC; + SIGNAL wire_n011ilil_dataout : STD_LOGIC; + SIGNAL wire_n011iliO_dataout : STD_LOGIC; + SIGNAL wire_n011ill_dataout : STD_LOGIC; + SIGNAL wire_n011illl_dataout : STD_LOGIC; + SIGNAL wire_n011illO_dataout : STD_LOGIC; + SIGNAL wire_n011ilO_dataout : STD_LOGIC; + SIGNAL wire_n011ilOi_dataout : STD_LOGIC; + SIGNAL wire_n011ilOl_dataout : STD_LOGIC; + SIGNAL wire_n011iOi_dataout : STD_LOGIC; + SIGNAL wire_n011iOil_dataout : STD_LOGIC; + SIGNAL wire_n011iOiO_dataout : STD_LOGIC; + SIGNAL wire_n011iOl_dataout : STD_LOGIC; + SIGNAL wire_n011iOli_dataout : STD_LOGIC; + SIGNAL wire_n011iOll_dataout : STD_LOGIC; + SIGNAL wire_n011iOlO_dataout : STD_LOGIC; + SIGNAL wire_n011iOO_dataout : STD_LOGIC; + SIGNAL wire_n011iOOi_dataout : STD_LOGIC; + SIGNAL wire_n011iOOl_dataout : STD_LOGIC; + SIGNAL wire_n011iOOO_dataout : STD_LOGIC; + SIGNAL wire_n011l01i_dataout : STD_LOGIC; + SIGNAL wire_n011l01l_dataout : STD_LOGIC; + SIGNAL wire_n011l0i_dataout : STD_LOGIC; + SIGNAL wire_n011l0l_dataout : STD_LOGIC; + SIGNAL wire_n011l0O_dataout : STD_LOGIC; + SIGNAL wire_n011l10i_dataout : STD_LOGIC; + SIGNAL wire_n011l10l_dataout : STD_LOGIC; + SIGNAL wire_n011l10O_dataout : STD_LOGIC; + SIGNAL wire_n011l11i_dataout : STD_LOGIC; + SIGNAL wire_n011l11l_dataout : STD_LOGIC; + SIGNAL wire_n011l11O_dataout : STD_LOGIC; + SIGNAL wire_n011l1i_dataout : STD_LOGIC; + SIGNAL wire_n011l1ii_dataout : STD_LOGIC; + SIGNAL wire_n011l1il_dataout : STD_LOGIC; + SIGNAL wire_n011l1iO_dataout : STD_LOGIC; + SIGNAL wire_n011l1l_dataout : STD_LOGIC; + SIGNAL wire_n011l1li_dataout : STD_LOGIC; + SIGNAL wire_n011l1ll_dataout : STD_LOGIC; + SIGNAL wire_n011l1lO_dataout : STD_LOGIC; + SIGNAL wire_n011l1O_dataout : STD_LOGIC; + SIGNAL wire_n011l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n011l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n011l1OO_dataout : STD_LOGIC; + SIGNAL wire_n011lii_dataout : STD_LOGIC; + SIGNAL wire_n011lil_dataout : STD_LOGIC; + SIGNAL wire_n011liO_dataout : STD_LOGIC; + SIGNAL wire_n011lli_dataout : STD_LOGIC; + SIGNAL wire_n011lll_dataout : STD_LOGIC; + SIGNAL wire_n011llO_dataout : STD_LOGIC; + SIGNAL wire_n011lOi_dataout : STD_LOGIC; + SIGNAL wire_n011lOiO_dataout : STD_LOGIC; + SIGNAL wire_n011lOl_dataout : STD_LOGIC; + SIGNAL wire_n011lOli_dataout : STD_LOGIC; + SIGNAL wire_n011lOll_dataout : STD_LOGIC; + SIGNAL wire_n011lOlO_dataout : STD_LOGIC; + SIGNAL wire_n011lOO_dataout : STD_LOGIC; + SIGNAL wire_n011lOOi_dataout : STD_LOGIC; + SIGNAL wire_n011lOOl_dataout : STD_LOGIC; + SIGNAL wire_n011lOOO_dataout : STD_LOGIC; + SIGNAL wire_n011O00i_dataout : STD_LOGIC; + SIGNAL wire_n011O00l_dataout : STD_LOGIC; + SIGNAL wire_n011O00O_dataout : STD_LOGIC; + SIGNAL wire_n011O01i_dataout : STD_LOGIC; + SIGNAL wire_n011O01l_dataout : STD_LOGIC; + SIGNAL wire_n011O01O_dataout : STD_LOGIC; + SIGNAL wire_n011O0i_dataout : STD_LOGIC; + SIGNAL wire_n011O0ii_dataout : STD_LOGIC; + SIGNAL wire_n011O0il_dataout : STD_LOGIC; + SIGNAL wire_n011O0iO_dataout : STD_LOGIC; + SIGNAL wire_n011O0l_dataout : STD_LOGIC; + SIGNAL wire_n011O0li_dataout : STD_LOGIC; + SIGNAL wire_n011O0ll_dataout : STD_LOGIC; + SIGNAL wire_n011O0lO_dataout : STD_LOGIC; + SIGNAL wire_n011O0O_dataout : STD_LOGIC; + SIGNAL wire_n011O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n011O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n011O0OO_dataout : STD_LOGIC; + SIGNAL wire_n011O10i_dataout : STD_LOGIC; + SIGNAL wire_n011O10l_dataout : STD_LOGIC; + SIGNAL wire_n011O10O_dataout : STD_LOGIC; + SIGNAL wire_n011O11i_dataout : STD_LOGIC; + SIGNAL wire_n011O11l_dataout : STD_LOGIC; + SIGNAL wire_n011O11O_dataout : STD_LOGIC; + SIGNAL wire_n011O1i_dataout : STD_LOGIC; + SIGNAL wire_n011O1ii_dataout : STD_LOGIC; + SIGNAL wire_n011O1il_dataout : STD_LOGIC; + SIGNAL wire_n011O1iO_dataout : STD_LOGIC; + SIGNAL wire_n011O1l_dataout : STD_LOGIC; + SIGNAL wire_n011O1li_dataout : STD_LOGIC; + SIGNAL wire_n011O1ll_dataout : STD_LOGIC; + SIGNAL wire_n011O1lO_dataout : STD_LOGIC; + SIGNAL wire_n011O1O_dataout : STD_LOGIC; + SIGNAL wire_n011O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n011O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n011O1OO_dataout : STD_LOGIC; + SIGNAL wire_n011Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n011Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n011Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n011Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n011Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n011Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n011Oii_dataout : STD_LOGIC; + SIGNAL wire_n011Oiii_dataout : STD_LOGIC; + SIGNAL wire_n011Oiil_dataout : STD_LOGIC; + SIGNAL wire_n011OiiO_dataout : STD_LOGIC; + SIGNAL wire_n011Oil_dataout : STD_LOGIC; + SIGNAL wire_n011Oili_dataout : STD_LOGIC; + SIGNAL wire_n011Oill_dataout : STD_LOGIC; + SIGNAL wire_n011OilO_dataout : STD_LOGIC; + SIGNAL wire_n011OiO_dataout : STD_LOGIC; + SIGNAL wire_n011OiOi_dataout : STD_LOGIC; + SIGNAL wire_n011OiOl_dataout : STD_LOGIC; + SIGNAL wire_n011OiOO_dataout : STD_LOGIC; + SIGNAL wire_n011Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n011Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n011Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n011Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n011Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n011Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n011Oli_dataout : STD_LOGIC; + SIGNAL wire_n011Olii_dataout : STD_LOGIC; + SIGNAL wire_n011Olil_dataout : STD_LOGIC; + SIGNAL wire_n011OliO_dataout : STD_LOGIC; + SIGNAL wire_n011Oll_dataout : STD_LOGIC; + SIGNAL wire_n011Olli_dataout : STD_LOGIC; + SIGNAL wire_n011Olll_dataout : STD_LOGIC; + SIGNAL wire_n011OllO_dataout : STD_LOGIC; + SIGNAL wire_n011OlO_dataout : STD_LOGIC; + SIGNAL wire_n011OlOi_dataout : STD_LOGIC; + SIGNAL wire_n011OlOl_dataout : STD_LOGIC; + SIGNAL wire_n011OlOO_dataout : STD_LOGIC; + SIGNAL wire_n011OO1i_dataout : STD_LOGIC; + SIGNAL wire_n011OO1l_dataout : STD_LOGIC; + SIGNAL wire_n011OO1O_dataout : STD_LOGIC; + SIGNAL wire_n011OOi_dataout : STD_LOGIC; + SIGNAL wire_n011OOl_dataout : STD_LOGIC; + SIGNAL wire_n011OOli_dataout : STD_LOGIC; + SIGNAL wire_n011OOll_dataout : STD_LOGIC; + SIGNAL wire_n011OOlO_dataout : STD_LOGIC; + SIGNAL wire_n011OOO_dataout : STD_LOGIC; + SIGNAL wire_n011OOOi_dataout : STD_LOGIC; + SIGNAL wire_n011OOOl_dataout : STD_LOGIC; + SIGNAL wire_n011OOOO_dataout : STD_LOGIC; + SIGNAL wire_n01i000i_dataout : STD_LOGIC; + SIGNAL wire_n01i000l_dataout : STD_LOGIC; + SIGNAL wire_n01i000O_dataout : STD_LOGIC; + SIGNAL wire_n01i001O_dataout : STD_LOGIC; + SIGNAL wire_n01i00i_dataout : STD_LOGIC; + SIGNAL wire_n01i00ii_dataout : STD_LOGIC; + SIGNAL wire_n01i00il_dataout : STD_LOGIC; + SIGNAL wire_n01i00iO_dataout : STD_LOGIC; + SIGNAL wire_n01i00l_dataout : STD_LOGIC; + SIGNAL wire_n01i00li_dataout : STD_LOGIC; + SIGNAL wire_n01i00ll_dataout : STD_LOGIC; + SIGNAL wire_n01i00lO_dataout : STD_LOGIC; + SIGNAL wire_n01i00O_dataout : STD_LOGIC; + SIGNAL wire_n01i00Oi_dataout : STD_LOGIC; + SIGNAL wire_n01i00Ol_dataout : STD_LOGIC; + SIGNAL wire_n01i00OO_dataout : STD_LOGIC; + SIGNAL wire_n01i011i_dataout : STD_LOGIC; + SIGNAL wire_n01i011l_dataout : STD_LOGIC; + SIGNAL wire_n01i01i_dataout : STD_LOGIC; + SIGNAL wire_n01i01l_dataout : STD_LOGIC; + SIGNAL wire_n01i01lO_dataout : STD_LOGIC; + SIGNAL wire_n01i01O_dataout : STD_LOGIC; + SIGNAL wire_n01i01Oi_dataout : STD_LOGIC; + SIGNAL wire_n01i0i0i_dataout : STD_LOGIC; + SIGNAL wire_n01i0i0l_dataout : STD_LOGIC; + SIGNAL wire_n01i0i0O_dataout : STD_LOGIC; + SIGNAL wire_n01i0i1i_dataout : STD_LOGIC; + SIGNAL wire_n01i0i1l_dataout : STD_LOGIC; + SIGNAL wire_n01i0i1O_dataout : STD_LOGIC; + SIGNAL wire_n01i0ii_dataout : STD_LOGIC; + SIGNAL wire_n01i0iii_dataout : STD_LOGIC; + SIGNAL wire_n01i0iil_dataout : STD_LOGIC; + SIGNAL wire_n01i0iiO_dataout : STD_LOGIC; + SIGNAL wire_n01i0il_dataout : STD_LOGIC; + SIGNAL wire_n01i0ili_dataout : STD_LOGIC; + SIGNAL wire_n01i0ill_dataout : STD_LOGIC; + SIGNAL wire_n01i0ilO_dataout : STD_LOGIC; + SIGNAL wire_n01i0iO_dataout : STD_LOGIC; + SIGNAL wire_n01i0iOi_dataout : STD_LOGIC; + SIGNAL wire_n01i0iOl_dataout : STD_LOGIC; + SIGNAL wire_n01i0iOO_dataout : STD_LOGIC; + SIGNAL wire_n01i0l0i_dataout : STD_LOGIC; + SIGNAL wire_n01i0l0l_dataout : STD_LOGIC; + SIGNAL wire_n01i0l0O_dataout : STD_LOGIC; + SIGNAL wire_n01i0l1i_dataout : STD_LOGIC; + SIGNAL wire_n01i0l1l_dataout : STD_LOGIC; + SIGNAL wire_n01i0l1O_dataout : STD_LOGIC; + SIGNAL wire_n01i0li_dataout : STD_LOGIC; + SIGNAL wire_n01i0lii_dataout : STD_LOGIC; + SIGNAL wire_n01i0lil_dataout : STD_LOGIC; + SIGNAL wire_n01i0liO_dataout : STD_LOGIC; + SIGNAL wire_n01i0ll_dataout : STD_LOGIC; + SIGNAL wire_n01i0lli_dataout : STD_LOGIC; + SIGNAL wire_n01i0lll_dataout : STD_LOGIC; + SIGNAL wire_n01i0llO_dataout : STD_LOGIC; + SIGNAL wire_n01i0lO_dataout : STD_LOGIC; + SIGNAL wire_n01i0lOi_dataout : STD_LOGIC; + SIGNAL wire_n01i0lOl_dataout : STD_LOGIC; + SIGNAL wire_n01i0lOO_dataout : STD_LOGIC; + SIGNAL wire_n01i0O0i_dataout : STD_LOGIC; + SIGNAL wire_n01i0O0l_dataout : STD_LOGIC; + SIGNAL wire_n01i0O0O_dataout : STD_LOGIC; + SIGNAL wire_n01i0O1i_dataout : STD_LOGIC; + SIGNAL wire_n01i0O1l_dataout : STD_LOGIC; + SIGNAL wire_n01i0O1O_dataout : STD_LOGIC; + SIGNAL wire_n01i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01i0Oii_dataout : STD_LOGIC; + SIGNAL wire_n01i0Oil_dataout : STD_LOGIC; + SIGNAL wire_n01i0OiO_dataout : STD_LOGIC; + SIGNAL wire_n01i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01i0Oli_dataout : STD_LOGIC; + SIGNAL wire_n01i0Oll_dataout : STD_LOGIC; + SIGNAL wire_n01i0OlO_dataout : STD_LOGIC; + SIGNAL wire_n01i0OO_dataout : STD_LOGIC; + SIGNAL wire_n01i0OOi_dataout : STD_LOGIC; + SIGNAL wire_n01i0OOl_dataout : STD_LOGIC; + SIGNAL wire_n01i0OOO_dataout : STD_LOGIC; + SIGNAL wire_n01i100i_dataout : STD_LOGIC; + SIGNAL wire_n01i100l_dataout : STD_LOGIC; + SIGNAL wire_n01i100O_dataout : STD_LOGIC; + SIGNAL wire_n01i10i_dataout : STD_LOGIC; + SIGNAL wire_n01i10ii_dataout : STD_LOGIC; + SIGNAL wire_n01i10il_dataout : STD_LOGIC; + SIGNAL wire_n01i10iO_dataout : STD_LOGIC; + SIGNAL wire_n01i10l_dataout : STD_LOGIC; + SIGNAL wire_n01i10li_dataout : STD_LOGIC; + SIGNAL wire_n01i10ll_dataout : STD_LOGIC; + SIGNAL wire_n01i10lO_dataout : STD_LOGIC; + SIGNAL wire_n01i10O_dataout : STD_LOGIC; + SIGNAL wire_n01i10Oi_dataout : STD_LOGIC; + SIGNAL wire_n01i10Ol_dataout : STD_LOGIC; + SIGNAL wire_n01i10OO_dataout : STD_LOGIC; + SIGNAL wire_n01i11i_dataout : STD_LOGIC; + SIGNAL wire_n01i11l_dataout : STD_LOGIC; + SIGNAL wire_n01i11O_dataout : STD_LOGIC; + SIGNAL wire_n01i1i0i_dataout : STD_LOGIC; + SIGNAL wire_n01i1i0l_dataout : STD_LOGIC; + SIGNAL wire_n01i1i0O_dataout : STD_LOGIC; + SIGNAL wire_n01i1i1i_dataout : STD_LOGIC; + SIGNAL wire_n01i1i1l_dataout : STD_LOGIC; + SIGNAL wire_n01i1i1O_dataout : STD_LOGIC; + SIGNAL wire_n01i1ii_dataout : STD_LOGIC; + SIGNAL wire_n01i1iii_dataout : STD_LOGIC; + SIGNAL wire_n01i1iil_dataout : STD_LOGIC; + SIGNAL wire_n01i1iiO_dataout : STD_LOGIC; + SIGNAL wire_n01i1il_dataout : STD_LOGIC; + SIGNAL wire_n01i1ili_dataout : STD_LOGIC; + SIGNAL wire_n01i1ill_dataout : STD_LOGIC; + SIGNAL wire_n01i1ilO_dataout : STD_LOGIC; + SIGNAL wire_n01i1iO_dataout : STD_LOGIC; + SIGNAL wire_n01i1iOi_dataout : STD_LOGIC; + SIGNAL wire_n01i1iOl_dataout : STD_LOGIC; + SIGNAL wire_n01i1iOO_dataout : STD_LOGIC; + SIGNAL wire_n01i1l0i_dataout : STD_LOGIC; + SIGNAL wire_n01i1l0l_dataout : STD_LOGIC; + SIGNAL wire_n01i1l0O_dataout : STD_LOGIC; + SIGNAL wire_n01i1l1i_dataout : STD_LOGIC; + SIGNAL wire_n01i1l1l_dataout : STD_LOGIC; + SIGNAL wire_n01i1l1O_dataout : STD_LOGIC; + SIGNAL wire_n01i1li_dataout : STD_LOGIC; + SIGNAL wire_n01i1lii_dataout : STD_LOGIC; + SIGNAL wire_n01i1lil_dataout : STD_LOGIC; + SIGNAL wire_n01i1liO_dataout : STD_LOGIC; + SIGNAL wire_n01i1ll_dataout : STD_LOGIC; + SIGNAL wire_n01i1lli_dataout : STD_LOGIC; + SIGNAL wire_n01i1lll_dataout : STD_LOGIC; + SIGNAL wire_n01i1llO_dataout : STD_LOGIC; + SIGNAL wire_n01i1lO_dataout : STD_LOGIC; + SIGNAL wire_n01i1lOi_dataout : STD_LOGIC; + SIGNAL wire_n01i1lOl_dataout : STD_LOGIC; + SIGNAL wire_n01i1O0i_dataout : STD_LOGIC; + SIGNAL wire_n01i1O0l_dataout : STD_LOGIC; + SIGNAL wire_n01i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01i1OiO_dataout : STD_LOGIC; + SIGNAL wire_n01i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01i1Oli_dataout : STD_LOGIC; + SIGNAL wire_n01i1Oll_dataout : STD_LOGIC; + SIGNAL wire_n01i1OlO_dataout : STD_LOGIC; + SIGNAL wire_n01i1OO_dataout : STD_LOGIC; + SIGNAL wire_n01i1OOi_dataout : STD_LOGIC; + SIGNAL wire_n01i1OOO_dataout : STD_LOGIC; + SIGNAL wire_n01ii00i_dataout : STD_LOGIC; + SIGNAL wire_n01ii00l_dataout : STD_LOGIC; + SIGNAL wire_n01ii00O_dataout : STD_LOGIC; + SIGNAL wire_n01ii01i_dataout : STD_LOGIC; + SIGNAL wire_n01ii01l_dataout : STD_LOGIC; + SIGNAL wire_n01ii01O_dataout : STD_LOGIC; + SIGNAL wire_n01ii0i_dataout : STD_LOGIC; + SIGNAL wire_n01ii0ii_dataout : STD_LOGIC; + SIGNAL wire_n01ii0il_dataout : STD_LOGIC; + SIGNAL wire_n01ii0iO_dataout : STD_LOGIC; + SIGNAL wire_n01ii0l_dataout : STD_LOGIC; + SIGNAL wire_n01ii0li_dataout : STD_LOGIC; + SIGNAL wire_n01ii0ll_dataout : STD_LOGIC; + SIGNAL wire_n01ii0lO_dataout : STD_LOGIC; + SIGNAL wire_n01ii0O_dataout : STD_LOGIC; + SIGNAL wire_n01ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01ii0OO_dataout : STD_LOGIC; + SIGNAL wire_n01ii10i_dataout : STD_LOGIC; + SIGNAL wire_n01ii10l_dataout : STD_LOGIC; + SIGNAL wire_n01ii10O_dataout : STD_LOGIC; + SIGNAL wire_n01ii11i_dataout : STD_LOGIC; + SIGNAL wire_n01ii11l_dataout : STD_LOGIC; + SIGNAL wire_n01ii11O_dataout : STD_LOGIC; + SIGNAL wire_n01ii1i_dataout : STD_LOGIC; + SIGNAL wire_n01ii1ii_dataout : STD_LOGIC; + SIGNAL wire_n01ii1il_dataout : STD_LOGIC; + SIGNAL wire_n01ii1iO_dataout : STD_LOGIC; + SIGNAL wire_n01ii1l_dataout : STD_LOGIC; + SIGNAL wire_n01ii1li_dataout : STD_LOGIC; + SIGNAL wire_n01ii1ll_dataout : STD_LOGIC; + SIGNAL wire_n01ii1lO_dataout : STD_LOGIC; + SIGNAL wire_n01ii1O_dataout : STD_LOGIC; + SIGNAL wire_n01ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01ii1OO_dataout : STD_LOGIC; + SIGNAL wire_n01iii0i_dataout : STD_LOGIC; + SIGNAL wire_n01iii0l_dataout : STD_LOGIC; + SIGNAL wire_n01iii0O_dataout : STD_LOGIC; + SIGNAL wire_n01iii1i_dataout : STD_LOGIC; + SIGNAL wire_n01iii1l_dataout : STD_LOGIC; + SIGNAL wire_n01iii1O_dataout : STD_LOGIC; + SIGNAL wire_n01iiii_dataout : STD_LOGIC; + SIGNAL wire_n01iiiii_dataout : STD_LOGIC; + SIGNAL wire_n01iiiil_dataout : STD_LOGIC; + SIGNAL wire_n01iiiiO_dataout : STD_LOGIC; + SIGNAL wire_n01iiil_dataout : STD_LOGIC; + SIGNAL wire_n01iiili_dataout : STD_LOGIC; + SIGNAL wire_n01iiill_dataout : STD_LOGIC; + SIGNAL wire_n01iiilO_dataout : STD_LOGIC; + SIGNAL wire_n01iiiO_dataout : STD_LOGIC; + SIGNAL wire_n01iiiOi_dataout : STD_LOGIC; + SIGNAL wire_n01iiiOl_dataout : STD_LOGIC; + SIGNAL wire_n01iiiOO_dataout : STD_LOGIC; + SIGNAL wire_n01iil0i_dataout : STD_LOGIC; + SIGNAL wire_n01iil0l_dataout : STD_LOGIC; + SIGNAL wire_n01iil1i_dataout : STD_LOGIC; + SIGNAL wire_n01iil1l_dataout : STD_LOGIC; + SIGNAL wire_n01iil1O_dataout : STD_LOGIC; + SIGNAL wire_n01iili_dataout : STD_LOGIC; + SIGNAL wire_n01iill_dataout : STD_LOGIC; + SIGNAL wire_n01iilO_dataout : STD_LOGIC; + SIGNAL wire_n01iilOl_dataout : STD_LOGIC; + SIGNAL wire_n01iilOO_dataout : STD_LOGIC; + SIGNAL wire_n01iiO0i_dataout : STD_LOGIC; + SIGNAL wire_n01iiO0l_dataout : STD_LOGIC; + SIGNAL wire_n01iiO0O_dataout : STD_LOGIC; + SIGNAL wire_n01iiO1i_dataout : STD_LOGIC; + SIGNAL wire_n01iiO1l_dataout : STD_LOGIC; + SIGNAL wire_n01iiO1O_dataout : STD_LOGIC; + SIGNAL wire_n01iiOi_dataout : STD_LOGIC; + SIGNAL wire_n01iiOii_dataout : STD_LOGIC; + SIGNAL wire_n01iiOil_dataout : STD_LOGIC; + SIGNAL wire_n01iiOiO_dataout : STD_LOGIC; + SIGNAL wire_n01iiOl_dataout : STD_LOGIC; + SIGNAL wire_n01iiOli_dataout : STD_LOGIC; + SIGNAL wire_n01iiOll_dataout : STD_LOGIC; + SIGNAL wire_n01iiOlO_dataout : STD_LOGIC; + SIGNAL wire_n01iiOO_dataout : STD_LOGIC; + SIGNAL wire_n01iiOOi_dataout : STD_LOGIC; + SIGNAL wire_n01iiOOl_dataout : STD_LOGIC; + SIGNAL wire_n01iiOOO_dataout : STD_LOGIC; + SIGNAL wire_n01il00i_dataout : STD_LOGIC; + SIGNAL wire_n01il00l_dataout : STD_LOGIC; + SIGNAL wire_n01il00O_dataout : STD_LOGIC; + SIGNAL wire_n01il01i_dataout : STD_LOGIC; + SIGNAL wire_n01il01l_dataout : STD_LOGIC; + SIGNAL wire_n01il01O_dataout : STD_LOGIC; + SIGNAL wire_n01il0i_dataout : STD_LOGIC; + SIGNAL wire_n01il0ii_dataout : STD_LOGIC; + SIGNAL wire_n01il0il_dataout : STD_LOGIC; + SIGNAL wire_n01il0iO_dataout : STD_LOGIC; + SIGNAL wire_n01il0l_dataout : STD_LOGIC; + SIGNAL wire_n01il0li_dataout : STD_LOGIC; + SIGNAL wire_n01il0ll_dataout : STD_LOGIC; + SIGNAL wire_n01il0lO_dataout : STD_LOGIC; + SIGNAL wire_n01il0O_dataout : STD_LOGIC; + SIGNAL wire_n01il0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01il0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01il0OO_dataout : STD_LOGIC; + SIGNAL wire_n01il10i_dataout : STD_LOGIC; + SIGNAL wire_n01il10l_dataout : STD_LOGIC; + SIGNAL wire_n01il10O_dataout : STD_LOGIC; + SIGNAL wire_n01il11i_dataout : STD_LOGIC; + SIGNAL wire_n01il11l_dataout : STD_LOGIC; + SIGNAL wire_n01il11O_dataout : STD_LOGIC; + SIGNAL wire_n01il1i_dataout : STD_LOGIC; + SIGNAL wire_n01il1ii_dataout : STD_LOGIC; + SIGNAL wire_n01il1il_dataout : STD_LOGIC; + SIGNAL wire_n01il1iO_dataout : STD_LOGIC; + SIGNAL wire_n01il1l_dataout : STD_LOGIC; + SIGNAL wire_n01il1li_dataout : STD_LOGIC; + SIGNAL wire_n01il1ll_dataout : STD_LOGIC; + SIGNAL wire_n01il1lO_dataout : STD_LOGIC; + SIGNAL wire_n01il1O_dataout : STD_LOGIC; + SIGNAL wire_n01il1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01il1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01il1OO_dataout : STD_LOGIC; + SIGNAL wire_n01ili0i_dataout : STD_LOGIC; + SIGNAL wire_n01ili0l_dataout : STD_LOGIC; + SIGNAL wire_n01ili0O_dataout : STD_LOGIC; + SIGNAL wire_n01ili1i_dataout : STD_LOGIC; + SIGNAL wire_n01ili1l_dataout : STD_LOGIC; + SIGNAL wire_n01ili1O_dataout : STD_LOGIC; + SIGNAL wire_n01ilii_dataout : STD_LOGIC; + SIGNAL wire_n01iliii_dataout : STD_LOGIC; + SIGNAL wire_n01iliil_dataout : STD_LOGIC; + SIGNAL wire_n01iliiO_dataout : STD_LOGIC; + SIGNAL wire_n01ilil_dataout : STD_LOGIC; + SIGNAL wire_n01ilili_dataout : STD_LOGIC; + SIGNAL wire_n01ilill_dataout : STD_LOGIC; + SIGNAL wire_n01ililO_dataout : STD_LOGIC; + SIGNAL wire_n01iliO_dataout : STD_LOGIC; + SIGNAL wire_n01iliOi_dataout : STD_LOGIC; + SIGNAL wire_n01iliOl_dataout : STD_LOGIC; + SIGNAL wire_n01iliOO_dataout : STD_LOGIC; + SIGNAL wire_n01ill0i_dataout : STD_LOGIC; + SIGNAL wire_n01ill0l_dataout : STD_LOGIC; + SIGNAL wire_n01ill0O_dataout : STD_LOGIC; + SIGNAL wire_n01ill1i_dataout : STD_LOGIC; + SIGNAL wire_n01ill1l_dataout : STD_LOGIC; + SIGNAL wire_n01ill1O_dataout : STD_LOGIC; + SIGNAL wire_n01illi_dataout : STD_LOGIC; + SIGNAL wire_n01illii_dataout : STD_LOGIC; + SIGNAL wire_n01illil_dataout : STD_LOGIC; + SIGNAL wire_n01illiO_dataout : STD_LOGIC; + SIGNAL wire_n01illl_dataout : STD_LOGIC; + SIGNAL wire_n01illli_dataout : STD_LOGIC; + SIGNAL wire_n01illll_dataout : STD_LOGIC; + SIGNAL wire_n01illlO_dataout : STD_LOGIC; + SIGNAL wire_n01illO_dataout : STD_LOGIC; + SIGNAL wire_n01illOi_dataout : STD_LOGIC; + SIGNAL wire_n01illOl_dataout : STD_LOGIC; + SIGNAL wire_n01illOO_dataout : STD_LOGIC; + SIGNAL wire_n01ilO0i_dataout : STD_LOGIC; + SIGNAL wire_n01ilO1i_dataout : STD_LOGIC; + SIGNAL wire_n01ilO1l_dataout : STD_LOGIC; + SIGNAL wire_n01ilO1O_dataout : STD_LOGIC; + SIGNAL wire_n01ilOi_dataout : STD_LOGIC; + SIGNAL wire_n01ilOl_dataout : STD_LOGIC; + SIGNAL wire_n01ilOO_dataout : STD_LOGIC; + SIGNAL wire_n01iO00i_dataout : STD_LOGIC; + SIGNAL wire_n01iO01i_dataout : STD_LOGIC; + SIGNAL wire_n01iO01l_dataout : STD_LOGIC; + SIGNAL wire_n01iO01O_dataout : STD_LOGIC; + SIGNAL wire_n01iO0i_dataout : STD_LOGIC; + SIGNAL wire_n01iO0l_dataout : STD_LOGIC; + SIGNAL wire_n01iO0li_dataout : STD_LOGIC; + SIGNAL wire_n01iO0ll_dataout : STD_LOGIC; + SIGNAL wire_n01iO0O_dataout : STD_LOGIC; + SIGNAL wire_n01iO10i_dataout : STD_LOGIC; + SIGNAL wire_n01iO10l_dataout : STD_LOGIC; + SIGNAL wire_n01iO10O_dataout : STD_LOGIC; + SIGNAL wire_n01iO11l_dataout : STD_LOGIC; + SIGNAL wire_n01iO11O_dataout : STD_LOGIC; + SIGNAL wire_n01iO1i_dataout : STD_LOGIC; + SIGNAL wire_n01iO1ii_dataout : STD_LOGIC; + SIGNAL wire_n01iO1il_dataout : STD_LOGIC; + SIGNAL wire_n01iO1iO_dataout : STD_LOGIC; + SIGNAL wire_n01iO1l_dataout : STD_LOGIC; + SIGNAL wire_n01iO1li_dataout : STD_LOGIC; + SIGNAL wire_n01iO1ll_dataout : STD_LOGIC; + SIGNAL wire_n01iO1lO_dataout : STD_LOGIC; + SIGNAL wire_n01iO1O_dataout : STD_LOGIC; + SIGNAL wire_n01iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01iO1OO_dataout : STD_LOGIC; + SIGNAL wire_n01iOii_dataout : STD_LOGIC; + SIGNAL wire_n01iOil_dataout : STD_LOGIC; + SIGNAL wire_n01iOiO_dataout : STD_LOGIC; + SIGNAL wire_n01iOl0i_dataout : STD_LOGIC; + SIGNAL wire_n01iOl0l_dataout : STD_LOGIC; + SIGNAL wire_n01iOl0O_dataout : STD_LOGIC; + SIGNAL wire_n01iOl1i_dataout : STD_LOGIC; + SIGNAL wire_n01iOl1l_dataout : STD_LOGIC; + SIGNAL wire_n01iOl1O_dataout : STD_LOGIC; + SIGNAL wire_n01iOli_dataout : STD_LOGIC; + SIGNAL wire_n01iOlii_dataout : STD_LOGIC; + SIGNAL wire_n01iOlil_dataout : STD_LOGIC; + SIGNAL wire_n01iOliO_dataout : STD_LOGIC; + SIGNAL wire_n01iOll_dataout : STD_LOGIC; + SIGNAL wire_n01iOlli_dataout : STD_LOGIC; + SIGNAL wire_n01iOlll_dataout : STD_LOGIC; + SIGNAL wire_n01iOllO_dataout : STD_LOGIC; + SIGNAL wire_n01iOlO_dataout : STD_LOGIC; + SIGNAL wire_n01iOlOi_dataout : STD_LOGIC; + SIGNAL wire_n01iOlOl_dataout : STD_LOGIC; + SIGNAL wire_n01iOlOO_dataout : STD_LOGIC; + SIGNAL wire_n01iOO1i_dataout : STD_LOGIC; + SIGNAL wire_n01iOO1l_dataout : STD_LOGIC; + SIGNAL wire_n01iOOi_dataout : STD_LOGIC; + SIGNAL wire_n01iOOiO_dataout : STD_LOGIC; + SIGNAL wire_n01iOOl_dataout : STD_LOGIC; + SIGNAL wire_n01iOOli_dataout : STD_LOGIC; + SIGNAL wire_n01iOOll_dataout : STD_LOGIC; + SIGNAL wire_n01iOOlO_dataout : STD_LOGIC; + SIGNAL wire_n01iOOO_dataout : STD_LOGIC; + SIGNAL wire_n01iOOOi_dataout : STD_LOGIC; + SIGNAL wire_n01iOOOl_dataout : STD_LOGIC; + SIGNAL wire_n01iOOOO_dataout : STD_LOGIC; + SIGNAL wire_n01l000l_dataout : STD_LOGIC; + SIGNAL wire_n01l000O_dataout : STD_LOGIC; + SIGNAL wire_n01l00i_dataout : STD_LOGIC; + SIGNAL wire_n01l00ii_dataout : STD_LOGIC; + SIGNAL wire_n01l00il_dataout : STD_LOGIC; + SIGNAL wire_n01l00iO_dataout : STD_LOGIC; + SIGNAL wire_n01l00l_dataout : STD_LOGIC; + SIGNAL wire_n01l00li_dataout : STD_LOGIC; + SIGNAL wire_n01l00ll_dataout : STD_LOGIC; + SIGNAL wire_n01l00lO_dataout : STD_LOGIC; + SIGNAL wire_n01l00O_dataout : STD_LOGIC; + SIGNAL wire_n01l00Oi_dataout : STD_LOGIC; + SIGNAL wire_n01l00Ol_dataout : STD_LOGIC; + SIGNAL wire_n01l00OO_dataout : STD_LOGIC; + SIGNAL wire_n01l011l_dataout : STD_LOGIC; + SIGNAL wire_n01l01i_dataout : STD_LOGIC; + SIGNAL wire_n01l01l_dataout : STD_LOGIC; + SIGNAL wire_n01l01O_dataout : STD_LOGIC; + SIGNAL wire_n01l0i0i_dataout : STD_LOGIC; + SIGNAL wire_n01l0i0l_dataout : STD_LOGIC; + SIGNAL wire_n01l0i0O_dataout : STD_LOGIC; + SIGNAL wire_n01l0i1i_dataout : STD_LOGIC; + SIGNAL wire_n01l0i1l_dataout : STD_LOGIC; + SIGNAL wire_n01l0i1O_dataout : STD_LOGIC; + SIGNAL wire_n01l0ii_dataout : STD_LOGIC; + SIGNAL wire_n01l0iii_dataout : STD_LOGIC; + SIGNAL wire_n01l0iil_dataout : STD_LOGIC; + SIGNAL wire_n01l0iiO_dataout : STD_LOGIC; + SIGNAL wire_n01l0il_dataout : STD_LOGIC; + SIGNAL wire_n01l0ili_dataout : STD_LOGIC; + SIGNAL wire_n01l0ill_dataout : STD_LOGIC; + SIGNAL wire_n01l0ilO_dataout : STD_LOGIC; + SIGNAL wire_n01l0iO_dataout : STD_LOGIC; + SIGNAL wire_n01l0iOi_dataout : STD_LOGIC; + SIGNAL wire_n01l0iOl_dataout : STD_LOGIC; + SIGNAL wire_n01l0iOO_dataout : STD_LOGIC; + SIGNAL wire_n01l0l0i_dataout : STD_LOGIC; + SIGNAL wire_n01l0l0l_dataout : STD_LOGIC; + SIGNAL wire_n01l0l0O_dataout : STD_LOGIC; + SIGNAL wire_n01l0l1i_dataout : STD_LOGIC; + SIGNAL wire_n01l0l1l_dataout : STD_LOGIC; + SIGNAL wire_n01l0l1O_dataout : STD_LOGIC; + SIGNAL wire_n01l0li_dataout : STD_LOGIC; + SIGNAL wire_n01l0lii_dataout : STD_LOGIC; + SIGNAL wire_n01l0lil_dataout : STD_LOGIC; + SIGNAL wire_n01l0liO_dataout : STD_LOGIC; + SIGNAL wire_n01l0ll_dataout : STD_LOGIC; + SIGNAL wire_n01l0lli_dataout : STD_LOGIC; + SIGNAL wire_n01l0lll_dataout : STD_LOGIC; + SIGNAL wire_n01l0llO_dataout : STD_LOGIC; + SIGNAL wire_n01l0lO_dataout : STD_LOGIC; + SIGNAL wire_n01l0lOi_dataout : STD_LOGIC; + SIGNAL wire_n01l0lOl_dataout : STD_LOGIC; + SIGNAL wire_n01l0lOO_dataout : STD_LOGIC; + SIGNAL wire_n01l0O0i_dataout : STD_LOGIC; + SIGNAL wire_n01l0O0l_dataout : STD_LOGIC; + SIGNAL wire_n01l0O0O_dataout : STD_LOGIC; + SIGNAL wire_n01l0O1i_dataout : STD_LOGIC; + SIGNAL wire_n01l0O1l_dataout : STD_LOGIC; + SIGNAL wire_n01l0O1O_dataout : STD_LOGIC; + SIGNAL wire_n01l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01l0Oii_dataout : STD_LOGIC; + SIGNAL wire_n01l0OiO_dataout : STD_LOGIC; + SIGNAL wire_n01l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01l0Oli_dataout : STD_LOGIC; + SIGNAL wire_n01l0Oll_dataout : STD_LOGIC; + SIGNAL wire_n01l0OO_dataout : STD_LOGIC; + SIGNAL wire_n01l100i_dataout : STD_LOGIC; + SIGNAL wire_n01l100l_dataout : STD_LOGIC; + SIGNAL wire_n01l100O_dataout : STD_LOGIC; + SIGNAL wire_n01l101i_dataout : STD_LOGIC; + SIGNAL wire_n01l101l_dataout : STD_LOGIC; + SIGNAL wire_n01l101O_dataout : STD_LOGIC; + SIGNAL wire_n01l10i_dataout : STD_LOGIC; + SIGNAL wire_n01l10ii_dataout : STD_LOGIC; + SIGNAL wire_n01l10il_dataout : STD_LOGIC; + SIGNAL wire_n01l10iO_dataout : STD_LOGIC; + SIGNAL wire_n01l10l_dataout : STD_LOGIC; + SIGNAL wire_n01l10lO_dataout : STD_LOGIC; + SIGNAL wire_n01l10O_dataout : STD_LOGIC; + SIGNAL wire_n01l10Oi_dataout : STD_LOGIC; + SIGNAL wire_n01l10Ol_dataout : STD_LOGIC; + SIGNAL wire_n01l10OO_dataout : STD_LOGIC; + SIGNAL wire_n01l110i_dataout : STD_LOGIC; + SIGNAL wire_n01l110l_dataout : STD_LOGIC; + SIGNAL wire_n01l110O_dataout : STD_LOGIC; + SIGNAL wire_n01l111i_dataout : STD_LOGIC; + SIGNAL wire_n01l111l_dataout : STD_LOGIC; + SIGNAL wire_n01l111O_dataout : STD_LOGIC; + SIGNAL wire_n01l11i_dataout : STD_LOGIC; + SIGNAL wire_n01l11ii_dataout : STD_LOGIC; + SIGNAL wire_n01l11il_dataout : STD_LOGIC; + SIGNAL wire_n01l11iO_dataout : STD_LOGIC; + SIGNAL wire_n01l11l_dataout : STD_LOGIC; + SIGNAL wire_n01l11li_dataout : STD_LOGIC; + SIGNAL wire_n01l11ll_dataout : STD_LOGIC; + SIGNAL wire_n01l11lO_dataout : STD_LOGIC; + SIGNAL wire_n01l11O_dataout : STD_LOGIC; + SIGNAL wire_n01l11Oi_dataout : STD_LOGIC; + SIGNAL wire_n01l11Ol_dataout : STD_LOGIC; + SIGNAL wire_n01l11OO_dataout : STD_LOGIC; + SIGNAL wire_n01l1i1i_dataout : STD_LOGIC; + SIGNAL wire_n01l1i1l_dataout : STD_LOGIC; + SIGNAL wire_n01l1ii_dataout : STD_LOGIC; + SIGNAL wire_n01l1il_dataout : STD_LOGIC; + SIGNAL wire_n01l1iO_dataout : STD_LOGIC; + SIGNAL wire_n01l1li_dataout : STD_LOGIC; + SIGNAL wire_n01l1ll_dataout : STD_LOGIC; + SIGNAL wire_n01l1lO_dataout : STD_LOGIC; + SIGNAL wire_n01l1O0i_dataout : STD_LOGIC; + SIGNAL wire_n01l1O0O_dataout : STD_LOGIC; + SIGNAL wire_n01l1O1i_dataout : STD_LOGIC; + SIGNAL wire_n01l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01l1OiO_dataout : STD_LOGIC; + SIGNAL wire_n01l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01l1Oll_dataout : STD_LOGIC; + SIGNAL wire_n01l1OO_dataout : STD_LOGIC; + SIGNAL wire_n01l1OOi_dataout : STD_LOGIC; + SIGNAL wire_n01l1OOO_dataout : STD_LOGIC; + SIGNAL wire_n01li0i_dataout : STD_LOGIC; + SIGNAL wire_n01li0l_dataout : STD_LOGIC; + SIGNAL wire_n01li0li_dataout : STD_LOGIC; + SIGNAL wire_n01li0li_w_lg_dataout16735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01li0O_dataout : STD_LOGIC; + SIGNAL wire_n01li0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01li0Oi_w_lg_dataout16733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01li0OO_dataout : STD_LOGIC; + SIGNAL wire_n01li0OO_w_lg_dataout16731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01li1i_dataout : STD_LOGIC; + SIGNAL wire_n01li1l_dataout : STD_LOGIC; + SIGNAL wire_n01li1O_dataout : STD_LOGIC; + SIGNAL wire_n01lii0l_dataout : STD_LOGIC; + SIGNAL wire_n01lii0l_w_lg_dataout16727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01lii1O_dataout : STD_LOGIC; + SIGNAL wire_n01lii1O_w_lg_dataout16729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01liii_dataout : STD_LOGIC; + SIGNAL wire_n01liiii_dataout : STD_LOGIC; + SIGNAL wire_n01liiii_w_lg_dataout16725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01liiiO_dataout : STD_LOGIC; + SIGNAL wire_n01liiiO_w_lg_dataout16723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01liil_dataout : STD_LOGIC; + SIGNAL wire_n01liill_dataout : STD_LOGIC; + SIGNAL wire_n01liill_w_lg_dataout16721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n01liiO_dataout : STD_LOGIC; + SIGNAL wire_n01lili_dataout : STD_LOGIC; + SIGNAL wire_n01lill_dataout : STD_LOGIC; + SIGNAL wire_n01lilO_dataout : STD_LOGIC; + SIGNAL wire_n01lilOi_dataout : STD_LOGIC; + SIGNAL wire_n01lilOl_dataout : STD_LOGIC; + SIGNAL wire_n01lilOO_dataout : STD_LOGIC; + SIGNAL wire_n01liO0i_dataout : STD_LOGIC; + SIGNAL wire_n01liO0l_dataout : STD_LOGIC; + SIGNAL wire_n01liO0O_dataout : STD_LOGIC; + SIGNAL wire_n01liO1i_dataout : STD_LOGIC; + SIGNAL wire_n01liO1l_dataout : STD_LOGIC; + SIGNAL wire_n01liO1O_dataout : STD_LOGIC; + SIGNAL wire_n01liOi_dataout : STD_LOGIC; + SIGNAL wire_n01liOii_dataout : STD_LOGIC; + SIGNAL wire_n01liOil_dataout : STD_LOGIC; + SIGNAL wire_n01liOiO_dataout : STD_LOGIC; + SIGNAL wire_n01liOl_dataout : STD_LOGIC; + SIGNAL wire_n01liOli_dataout : STD_LOGIC; + SIGNAL wire_n01liOll_dataout : STD_LOGIC; + SIGNAL wire_n01liOlO_dataout : STD_LOGIC; + SIGNAL wire_n01liOO_dataout : STD_LOGIC; + SIGNAL wire_n01liOOi_dataout : STD_LOGIC; + SIGNAL wire_n01liOOl_dataout : STD_LOGIC; + SIGNAL wire_n01liOOO_dataout : STD_LOGIC; + SIGNAL wire_n01ll00i_dataout : STD_LOGIC; + SIGNAL wire_n01ll00l_dataout : STD_LOGIC; + SIGNAL wire_n01ll00O_dataout : STD_LOGIC; + SIGNAL wire_n01ll01i_dataout : STD_LOGIC; + SIGNAL wire_n01ll01l_dataout : STD_LOGIC; + SIGNAL wire_n01ll01O_dataout : STD_LOGIC; + SIGNAL wire_n01ll0i_dataout : STD_LOGIC; + SIGNAL wire_n01ll0ii_dataout : STD_LOGIC; + SIGNAL wire_n01ll0il_dataout : STD_LOGIC; + SIGNAL wire_n01ll0iO_dataout : STD_LOGIC; + SIGNAL wire_n01ll0l_dataout : STD_LOGIC; + SIGNAL wire_n01ll0li_dataout : STD_LOGIC; + SIGNAL wire_n01ll0ll_dataout : STD_LOGIC; + SIGNAL wire_n01ll0lO_dataout : STD_LOGIC; + SIGNAL wire_n01ll0O_dataout : STD_LOGIC; + SIGNAL wire_n01ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01ll0OO_dataout : STD_LOGIC; + SIGNAL wire_n01ll10i_dataout : STD_LOGIC; + SIGNAL wire_n01ll10l_dataout : STD_LOGIC; + SIGNAL wire_n01ll10O_dataout : STD_LOGIC; + SIGNAL wire_n01ll11i_dataout : STD_LOGIC; + SIGNAL wire_n01ll11l_dataout : STD_LOGIC; + SIGNAL wire_n01ll11O_dataout : STD_LOGIC; + SIGNAL wire_n01ll1i_dataout : STD_LOGIC; + SIGNAL wire_n01ll1ii_dataout : STD_LOGIC; + SIGNAL wire_n01ll1il_dataout : STD_LOGIC; + SIGNAL wire_n01ll1iO_dataout : STD_LOGIC; + SIGNAL wire_n01ll1l_dataout : STD_LOGIC; + SIGNAL wire_n01ll1li_dataout : STD_LOGIC; + SIGNAL wire_n01ll1ll_dataout : STD_LOGIC; + SIGNAL wire_n01ll1lO_dataout : STD_LOGIC; + SIGNAL wire_n01ll1O_dataout : STD_LOGIC; + SIGNAL wire_n01ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01ll1OO_dataout : STD_LOGIC; + SIGNAL wire_n01llii_dataout : STD_LOGIC; + SIGNAL wire_n01llil_dataout : STD_LOGIC; + SIGNAL wire_n01lliO_dataout : STD_LOGIC; + SIGNAL wire_n01llli_dataout : STD_LOGIC; + SIGNAL wire_n01llll_dataout : STD_LOGIC; + SIGNAL wire_n01lllO_dataout : STD_LOGIC; + SIGNAL wire_n01llOi_dataout : STD_LOGIC; + SIGNAL wire_n01llOl_dataout : STD_LOGIC; + SIGNAL wire_n01llOO_dataout : STD_LOGIC; + SIGNAL wire_n01lO0i_dataout : STD_LOGIC; + SIGNAL wire_n01lO0l_dataout : STD_LOGIC; + SIGNAL wire_n01lO0O_dataout : STD_LOGIC; + SIGNAL wire_n01lO1i_dataout : STD_LOGIC; + SIGNAL wire_n01lO1l_dataout : STD_LOGIC; + SIGNAL wire_n01lO1O_dataout : STD_LOGIC; + SIGNAL wire_n01lOii_dataout : STD_LOGIC; + SIGNAL wire_n01lOil_dataout : STD_LOGIC; + SIGNAL wire_n01lOiO_dataout : STD_LOGIC; + SIGNAL wire_n01lOl0i_dataout : STD_LOGIC; + SIGNAL wire_n01lOl0l_dataout : STD_LOGIC; + SIGNAL wire_n01lOl0O_dataout : STD_LOGIC; + SIGNAL wire_n01lOli_dataout : STD_LOGIC; + SIGNAL wire_n01lOlii_dataout : STD_LOGIC; + SIGNAL wire_n01lOlil_dataout : STD_LOGIC; + SIGNAL wire_n01lOliO_dataout : STD_LOGIC; + SIGNAL wire_n01lOll_dataout : STD_LOGIC; + SIGNAL wire_n01lOlli_dataout : STD_LOGIC; + SIGNAL wire_n01lOlll_dataout : STD_LOGIC; + SIGNAL wire_n01lOllO_dataout : STD_LOGIC; + SIGNAL wire_n01lOlO_dataout : STD_LOGIC; + SIGNAL wire_n01lOO0i_dataout : STD_LOGIC; + SIGNAL wire_n01lOO0l_dataout : STD_LOGIC; + SIGNAL wire_n01lOO0O_dataout : STD_LOGIC; + SIGNAL wire_n01lOO1l_dataout : STD_LOGIC; + SIGNAL wire_n01lOO1O_dataout : STD_LOGIC; + SIGNAL wire_n01lOOi_dataout : STD_LOGIC; + SIGNAL wire_n01lOOii_dataout : STD_LOGIC; + SIGNAL wire_n01lOOl_dataout : STD_LOGIC; + SIGNAL wire_n01lOOli_dataout : STD_LOGIC; + SIGNAL wire_n01lOOll_dataout : STD_LOGIC; + SIGNAL wire_n01lOOlO_dataout : STD_LOGIC; + SIGNAL wire_n01lOOO_dataout : STD_LOGIC; + SIGNAL wire_n01O00i_dataout : STD_LOGIC; + SIGNAL wire_n01O00l_dataout : STD_LOGIC; + SIGNAL wire_n01O00O_dataout : STD_LOGIC; + SIGNAL wire_n01O01i_dataout : STD_LOGIC; + SIGNAL wire_n01O01l_dataout : STD_LOGIC; + SIGNAL wire_n01O01O_dataout : STD_LOGIC; + SIGNAL wire_n01O0ii_dataout : STD_LOGIC; + SIGNAL wire_n01O0il_dataout : STD_LOGIC; + SIGNAL wire_n01O0iO_dataout : STD_LOGIC; + SIGNAL wire_n01O0iOi_dataout : STD_LOGIC; + SIGNAL wire_n01O0iOl_dataout : STD_LOGIC; + SIGNAL wire_n01O0iOO_dataout : STD_LOGIC; + SIGNAL wire_n01O0l0i_dataout : STD_LOGIC; + SIGNAL wire_n01O0l0l_dataout : STD_LOGIC; + SIGNAL wire_n01O0l0O_dataout : STD_LOGIC; + SIGNAL wire_n01O0l1i_dataout : STD_LOGIC; + SIGNAL wire_n01O0l1l_dataout : STD_LOGIC; + SIGNAL wire_n01O0l1O_dataout : STD_LOGIC; + SIGNAL wire_n01O0li_dataout : STD_LOGIC; + SIGNAL wire_n01O0lii_dataout : STD_LOGIC; + SIGNAL wire_n01O0lil_dataout : STD_LOGIC; + SIGNAL wire_n01O0liO_dataout : STD_LOGIC; + SIGNAL wire_n01O0ll_dataout : STD_LOGIC; + SIGNAL wire_n01O0lli_dataout : STD_LOGIC; + SIGNAL wire_n01O0lll_dataout : STD_LOGIC; + SIGNAL wire_n01O0llO_dataout : STD_LOGIC; + SIGNAL wire_n01O0lO_dataout : STD_LOGIC; + SIGNAL wire_n01O0lOi_dataout : STD_LOGIC; + SIGNAL wire_n01O0lOl_dataout : STD_LOGIC; + SIGNAL wire_n01O0lOO_dataout : STD_LOGIC; + SIGNAL wire_n01O0O0i_dataout : STD_LOGIC; + SIGNAL wire_n01O0O0l_dataout : STD_LOGIC; + SIGNAL wire_n01O0O0O_dataout : STD_LOGIC; + SIGNAL wire_n01O0O1i_dataout : STD_LOGIC; + SIGNAL wire_n01O0O1l_dataout : STD_LOGIC; + SIGNAL wire_n01O0O1O_dataout : STD_LOGIC; + SIGNAL wire_n01O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01O0Oii_dataout : STD_LOGIC; + SIGNAL wire_n01O0Oil_dataout : STD_LOGIC; + SIGNAL wire_n01O0OiO_dataout : STD_LOGIC; + SIGNAL wire_n01O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01O0Oli_dataout : STD_LOGIC; + SIGNAL wire_n01O0Oll_dataout : STD_LOGIC; + SIGNAL wire_n01O0OlO_dataout : STD_LOGIC; + SIGNAL wire_n01O0OO_dataout : STD_LOGIC; + SIGNAL wire_n01O0OOi_dataout : STD_LOGIC; + SIGNAL wire_n01O0OOl_dataout : STD_LOGIC; + SIGNAL wire_n01O0OOO_dataout : STD_LOGIC; + SIGNAL wire_n01O100i_dataout : STD_LOGIC; + SIGNAL wire_n01O100l_dataout : STD_LOGIC; + SIGNAL wire_n01O100O_dataout : STD_LOGIC; + SIGNAL wire_n01O101i_dataout : STD_LOGIC; + SIGNAL wire_n01O101l_dataout : STD_LOGIC; + SIGNAL wire_n01O101O_dataout : STD_LOGIC; + SIGNAL wire_n01O10i_dataout : STD_LOGIC; + SIGNAL wire_n01O10l_dataout : STD_LOGIC; + SIGNAL wire_n01O10ll_dataout : STD_LOGIC; + SIGNAL wire_n01O10lO_dataout : STD_LOGIC; + SIGNAL wire_n01O10O_dataout : STD_LOGIC; + SIGNAL wire_n01O10Oi_dataout : STD_LOGIC; + SIGNAL wire_n01O10OO_dataout : STD_LOGIC; + SIGNAL wire_n01O11i_dataout : STD_LOGIC; + SIGNAL wire_n01O11ii_dataout : STD_LOGIC; + SIGNAL wire_n01O11il_dataout : STD_LOGIC; + SIGNAL wire_n01O11iO_dataout : STD_LOGIC; + SIGNAL wire_n01O11l_dataout : STD_LOGIC; + SIGNAL wire_n01O11li_dataout : STD_LOGIC; + SIGNAL wire_n01O11ll_dataout : STD_LOGIC; + SIGNAL wire_n01O11lO_dataout : STD_LOGIC; + SIGNAL wire_n01O11O_dataout : STD_LOGIC; + SIGNAL wire_n01O11Oi_dataout : STD_LOGIC; + SIGNAL wire_n01O11Ol_dataout : STD_LOGIC; + SIGNAL wire_n01O11OO_dataout : STD_LOGIC; + SIGNAL wire_n01O1i1i_dataout : STD_LOGIC; + SIGNAL wire_n01O1i1l_dataout : STD_LOGIC; + SIGNAL wire_n01O1i1O_dataout : STD_LOGIC; + SIGNAL wire_n01O1ii_dataout : STD_LOGIC; + SIGNAL wire_n01O1il_dataout : STD_LOGIC; + SIGNAL wire_n01O1ilO_dataout : STD_LOGIC; + SIGNAL wire_n01O1iO_dataout : STD_LOGIC; + SIGNAL wire_n01O1iOi_dataout : STD_LOGIC; + SIGNAL wire_n01O1iOl_dataout : STD_LOGIC; + SIGNAL wire_n01O1iOO_dataout : STD_LOGIC; + SIGNAL wire_n01O1l0i_dataout : STD_LOGIC; + SIGNAL wire_n01O1l0l_dataout : STD_LOGIC; + SIGNAL wire_n01O1l0O_dataout : STD_LOGIC; + SIGNAL wire_n01O1l1i_dataout : STD_LOGIC; + SIGNAL wire_n01O1l1l_dataout : STD_LOGIC; + SIGNAL wire_n01O1l1O_dataout : STD_LOGIC; + SIGNAL wire_n01O1li_dataout : STD_LOGIC; + SIGNAL wire_n01O1lii_dataout : STD_LOGIC; + SIGNAL wire_n01O1lil_dataout : STD_LOGIC; + SIGNAL wire_n01O1liO_dataout : STD_LOGIC; + SIGNAL wire_n01O1ll_dataout : STD_LOGIC; + SIGNAL wire_n01O1lli_dataout : STD_LOGIC; + SIGNAL wire_n01O1lll_dataout : STD_LOGIC; + SIGNAL wire_n01O1llO_dataout : STD_LOGIC; + SIGNAL wire_n01O1lO_dataout : STD_LOGIC; + SIGNAL wire_n01O1lOi_dataout : STD_LOGIC; + SIGNAL wire_n01O1lOl_dataout : STD_LOGIC; + SIGNAL wire_n01O1lOO_dataout : STD_LOGIC; + SIGNAL wire_n01O1O0i_dataout : STD_LOGIC; + SIGNAL wire_n01O1O0l_dataout : STD_LOGIC; + SIGNAL wire_n01O1O0O_dataout : STD_LOGIC; + SIGNAL wire_n01O1O1i_dataout : STD_LOGIC; + SIGNAL wire_n01O1O1l_dataout : STD_LOGIC; + SIGNAL wire_n01O1O1O_dataout : STD_LOGIC; + SIGNAL wire_n01O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01O1OO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi00i_dataout : STD_LOGIC; + SIGNAL wire_n01Oi00l_dataout : STD_LOGIC; + SIGNAL wire_n01Oi00O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi01i_dataout : STD_LOGIC; + SIGNAL wire_n01Oi01l_dataout : STD_LOGIC; + SIGNAL wire_n01Oi01O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0il_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0li_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi10i_dataout : STD_LOGIC; + SIGNAL wire_n01Oi10l_dataout : STD_LOGIC; + SIGNAL wire_n01Oi10O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi11i_dataout : STD_LOGIC; + SIGNAL wire_n01Oi11l_dataout : STD_LOGIC; + SIGNAL wire_n01Oi11O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1il_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1li_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_n01Oii0i_dataout : STD_LOGIC; + SIGNAL wire_n01Oii0l_dataout : STD_LOGIC; + SIGNAL wire_n01Oii0O_dataout : STD_LOGIC; + SIGNAL wire_n01Oii1i_dataout : STD_LOGIC; + SIGNAL wire_n01Oii1l_dataout : STD_LOGIC; + SIGNAL wire_n01Oii1O_dataout : STD_LOGIC; + SIGNAL wire_n01Oiii_dataout : STD_LOGIC; + SIGNAL wire_n01Oiiii_dataout : STD_LOGIC; + SIGNAL wire_n01Oiil_dataout : STD_LOGIC; + SIGNAL wire_n01OiiO_dataout : STD_LOGIC; + SIGNAL wire_n01OiiOl_dataout : STD_LOGIC; + SIGNAL wire_n01OiiOO_dataout : STD_LOGIC; + SIGNAL wire_n01Oil0i_dataout : STD_LOGIC; + SIGNAL wire_n01Oil0l_dataout : STD_LOGIC; + SIGNAL wire_n01Oil0O_dataout : STD_LOGIC; + SIGNAL wire_n01Oil1i_dataout : STD_LOGIC; + SIGNAL wire_n01Oil1l_dataout : STD_LOGIC; + SIGNAL wire_n01Oil1O_dataout : STD_LOGIC; + SIGNAL wire_n01Oili_dataout : STD_LOGIC; + SIGNAL wire_n01Oilii_dataout : STD_LOGIC; + SIGNAL wire_n01Oilil_dataout : STD_LOGIC; + SIGNAL wire_n01OiliO_dataout : STD_LOGIC; + SIGNAL wire_n01Oill_dataout : STD_LOGIC; + SIGNAL wire_n01Oilli_dataout : STD_LOGIC; + SIGNAL wire_n01Oilll_dataout : STD_LOGIC; + SIGNAL wire_n01OillO_dataout : STD_LOGIC; + SIGNAL wire_n01OilO_dataout : STD_LOGIC; + SIGNAL wire_n01OilOi_dataout : STD_LOGIC; + SIGNAL wire_n01OilOl_dataout : STD_LOGIC; + SIGNAL wire_n01OilOO_dataout : STD_LOGIC; + SIGNAL wire_n01OiO0i_dataout : STD_LOGIC; + SIGNAL wire_n01OiO0l_dataout : STD_LOGIC; + SIGNAL wire_n01OiO0O_dataout : STD_LOGIC; + SIGNAL wire_n01OiO1i_dataout : STD_LOGIC; + SIGNAL wire_n01OiO1l_dataout : STD_LOGIC; + SIGNAL wire_n01OiO1O_dataout : STD_LOGIC; + SIGNAL wire_n01OiOi_dataout : STD_LOGIC; + SIGNAL wire_n01OiOii_dataout : STD_LOGIC; + SIGNAL wire_n01OiOil_dataout : STD_LOGIC; + SIGNAL wire_n01OiOiO_dataout : STD_LOGIC; + SIGNAL wire_n01OiOl_dataout : STD_LOGIC; + SIGNAL wire_n01OiOli_dataout : STD_LOGIC; + SIGNAL wire_n01OiOll_dataout : STD_LOGIC; + SIGNAL wire_n01OiOlO_dataout : STD_LOGIC; + SIGNAL wire_n01OiOO_dataout : STD_LOGIC; + SIGNAL wire_n01OiOOi_dataout : STD_LOGIC; + SIGNAL wire_n01OiOOl_dataout : STD_LOGIC; + SIGNAL wire_n01OiOOO_dataout : STD_LOGIC; + SIGNAL wire_n01Ol00i_dataout : STD_LOGIC; + SIGNAL wire_n01Ol00l_dataout : STD_LOGIC; + SIGNAL wire_n01Ol00O_dataout : STD_LOGIC; + SIGNAL wire_n01Ol01i_dataout : STD_LOGIC; + SIGNAL wire_n01Ol01l_dataout : STD_LOGIC; + SIGNAL wire_n01Ol01O_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0il_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0li_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_n01Ol10i_dataout : STD_LOGIC; + SIGNAL wire_n01Ol10l_dataout : STD_LOGIC; + SIGNAL wire_n01Ol10O_dataout : STD_LOGIC; + SIGNAL wire_n01Ol11i_dataout : STD_LOGIC; + SIGNAL wire_n01Ol11l_dataout : STD_LOGIC; + SIGNAL wire_n01Ol11O_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1il_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1li_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_n01Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_n01Oli0i_dataout : STD_LOGIC; + SIGNAL wire_n01Oli0l_dataout : STD_LOGIC; + SIGNAL wire_n01Oli0O_dataout : STD_LOGIC; + SIGNAL wire_n01Oli1i_dataout : STD_LOGIC; + SIGNAL wire_n01Oli1l_dataout : STD_LOGIC; + SIGNAL wire_n01Oli1O_dataout : STD_LOGIC; + SIGNAL wire_n01Olii_dataout : STD_LOGIC; + SIGNAL wire_n01Oliii_dataout : STD_LOGIC; + SIGNAL wire_n01Oliil_dataout : STD_LOGIC; + SIGNAL wire_n01OliiO_dataout : STD_LOGIC; + SIGNAL wire_n01Olil_dataout : STD_LOGIC; + SIGNAL wire_n01Olili_dataout : STD_LOGIC; + SIGNAL wire_n01OliO_dataout : STD_LOGIC; + SIGNAL wire_n01Olli_dataout : STD_LOGIC; + SIGNAL wire_n01Olll_dataout : STD_LOGIC; + SIGNAL wire_n01OllO_dataout : STD_LOGIC; + SIGNAL wire_n01OlOi_dataout : STD_LOGIC; + SIGNAL wire_n01OlOl_dataout : STD_LOGIC; + SIGNAL wire_n01OlOO_dataout : STD_LOGIC; + SIGNAL wire_n01OO0i_dataout : STD_LOGIC; + SIGNAL wire_n01OO0l_dataout : STD_LOGIC; + SIGNAL wire_n01OO0li_dataout : STD_LOGIC; + SIGNAL wire_n01OO0ll_dataout : STD_LOGIC; + SIGNAL wire_n01OO0lO_dataout : STD_LOGIC; + SIGNAL wire_n01OO0O_dataout : STD_LOGIC; + SIGNAL wire_n01OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n01OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n01OO0OO_dataout : STD_LOGIC; + SIGNAL wire_n01OO1i_dataout : STD_LOGIC; + SIGNAL wire_n01OO1l_dataout : STD_LOGIC; + SIGNAL wire_n01OO1O_dataout : STD_LOGIC; + SIGNAL wire_n01OOi0i_dataout : STD_LOGIC; + SIGNAL wire_n01OOi0l_dataout : STD_LOGIC; + SIGNAL wire_n01OOi0O_dataout : STD_LOGIC; + SIGNAL wire_n01OOi1i_dataout : STD_LOGIC; + SIGNAL wire_n01OOi1l_dataout : STD_LOGIC; + SIGNAL wire_n01OOi1O_dataout : STD_LOGIC; + SIGNAL wire_n01OOii_dataout : STD_LOGIC; + SIGNAL wire_n01OOiii_dataout : STD_LOGIC; + SIGNAL wire_n01OOiil_dataout : STD_LOGIC; + SIGNAL wire_n01OOiiO_dataout : STD_LOGIC; + SIGNAL wire_n01OOil_dataout : STD_LOGIC; + SIGNAL wire_n01OOili_dataout : STD_LOGIC; + SIGNAL wire_n01OOill_dataout : STD_LOGIC; + SIGNAL wire_n01OOilO_dataout : STD_LOGIC; + SIGNAL wire_n01OOiO_dataout : STD_LOGIC; + SIGNAL wire_n01OOiOi_dataout : STD_LOGIC; + SIGNAL wire_n01OOiOl_dataout : STD_LOGIC; + SIGNAL wire_n01OOiOO_dataout : STD_LOGIC; + SIGNAL wire_n01OOl0i_dataout : STD_LOGIC; + SIGNAL wire_n01OOl0l_dataout : STD_LOGIC; + SIGNAL wire_n01OOl0O_dataout : STD_LOGIC; + SIGNAL wire_n01OOl1i_dataout : STD_LOGIC; + SIGNAL wire_n01OOl1l_dataout : STD_LOGIC; + SIGNAL wire_n01OOl1O_dataout : STD_LOGIC; + SIGNAL wire_n01OOli_dataout : STD_LOGIC; + SIGNAL wire_n01OOlii_dataout : STD_LOGIC; + SIGNAL wire_n01OOlil_dataout : STD_LOGIC; + SIGNAL wire_n01OOliO_dataout : STD_LOGIC; + SIGNAL wire_n01OOll_dataout : STD_LOGIC; + SIGNAL wire_n01OOlli_dataout : STD_LOGIC; + SIGNAL wire_n01OOlll_dataout : STD_LOGIC; + SIGNAL wire_n01OOllO_dataout : STD_LOGIC; + SIGNAL wire_n01OOlO_dataout : STD_LOGIC; + SIGNAL wire_n01OOlOi_dataout : STD_LOGIC; + SIGNAL wire_n01OOlOl_dataout : STD_LOGIC; + SIGNAL wire_n01OOlOO_dataout : STD_LOGIC; + SIGNAL wire_n01OOO0i_dataout : STD_LOGIC; + SIGNAL wire_n01OOO0l_dataout : STD_LOGIC; + SIGNAL wire_n01OOO0O_dataout : STD_LOGIC; + SIGNAL wire_n01OOO1i_dataout : STD_LOGIC; + SIGNAL wire_n01OOO1l_dataout : STD_LOGIC; + SIGNAL wire_n01OOO1O_dataout : STD_LOGIC; + SIGNAL wire_n01OOOi_dataout : STD_LOGIC; + SIGNAL wire_n01OOOii_dataout : STD_LOGIC; + SIGNAL wire_n01OOOl_dataout : STD_LOGIC; + SIGNAL wire_n01OOOO_dataout : STD_LOGIC; + SIGNAL wire_n0i000i_dataout : STD_LOGIC; + SIGNAL wire_n0i000l_dataout : STD_LOGIC; + SIGNAL wire_n0i000O_dataout : STD_LOGIC; + SIGNAL wire_n0i0010i_dataout : STD_LOGIC; + SIGNAL wire_n0i0010l_dataout : STD_LOGIC; + SIGNAL wire_n0i0010O_dataout : STD_LOGIC; + SIGNAL wire_n0i0011i_dataout : STD_LOGIC; + SIGNAL wire_n0i0011l_dataout : STD_LOGIC; + SIGNAL wire_n0i0011O_dataout : STD_LOGIC; + SIGNAL wire_n0i001i_dataout : STD_LOGIC; + SIGNAL wire_n0i001ii_dataout : STD_LOGIC; + SIGNAL wire_n0i001il_dataout : STD_LOGIC; + SIGNAL wire_n0i001iO_dataout : STD_LOGIC; + SIGNAL wire_n0i001l_dataout : STD_LOGIC; + SIGNAL wire_n0i001li_dataout : STD_LOGIC; + SIGNAL wire_n0i001ll_dataout : STD_LOGIC; + SIGNAL wire_n0i001lO_dataout : STD_LOGIC; + SIGNAL wire_n0i001O_dataout : STD_LOGIC; + SIGNAL wire_n0i001Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i001Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i00ii_dataout : STD_LOGIC; + SIGNAL wire_n0i00il_dataout : STD_LOGIC; + SIGNAL wire_n0i00iO_dataout : STD_LOGIC; + SIGNAL wire_n0i00li_dataout : STD_LOGIC; + SIGNAL wire_n0i00ll_dataout : STD_LOGIC; + SIGNAL wire_n0i00lO_dataout : STD_LOGIC; + SIGNAL wire_n0i00O0O_dataout : STD_LOGIC; + SIGNAL wire_n0i00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i00Oii_dataout : STD_LOGIC; + SIGNAL wire_n0i00Oil_dataout : STD_LOGIC; + SIGNAL wire_n0i00OiO_dataout : STD_LOGIC; + SIGNAL wire_n0i00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i00Oli_dataout : STD_LOGIC; + SIGNAL wire_n0i00Oll_dataout : STD_LOGIC; + SIGNAL wire_n0i00OlO_dataout : STD_LOGIC; + SIGNAL wire_n0i00OO_dataout : STD_LOGIC; + SIGNAL wire_n0i00OOi_dataout : STD_LOGIC; + SIGNAL wire_n0i00OOl_dataout : STD_LOGIC; + SIGNAL wire_n0i00OOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0100i_dataout : STD_LOGIC; + SIGNAL wire_n0i0100l_dataout : STD_LOGIC; + SIGNAL wire_n0i0101O_dataout : STD_LOGIC; + SIGNAL wire_n0i010i_dataout : STD_LOGIC; + SIGNAL wire_n0i010l_dataout : STD_LOGIC; + SIGNAL wire_n0i010O_dataout : STD_LOGIC; + SIGNAL wire_n0i010OO_dataout : STD_LOGIC; + SIGNAL wire_n0i0110i_dataout : STD_LOGIC; + SIGNAL wire_n0i0110l_dataout : STD_LOGIC; + SIGNAL wire_n0i0111i_dataout : STD_LOGIC; + SIGNAL wire_n0i0111l_dataout : STD_LOGIC; + SIGNAL wire_n0i0111O_dataout : STD_LOGIC; + SIGNAL wire_n0i011i_dataout : STD_LOGIC; + SIGNAL wire_n0i011l_dataout : STD_LOGIC; + SIGNAL wire_n0i011li_dataout : STD_LOGIC; + SIGNAL wire_n0i011ll_dataout : STD_LOGIC; + SIGNAL wire_n0i011lO_dataout : STD_LOGIC; + SIGNAL wire_n0i011O_dataout : STD_LOGIC; + SIGNAL wire_n0i011Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i011Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i011OO_dataout : STD_LOGIC; + SIGNAL wire_n0i01i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i01i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i01i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i01i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i01i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i01i1O_dataout : STD_LOGIC; + SIGNAL wire_n0i01ii_dataout : STD_LOGIC; + SIGNAL wire_n0i01iii_dataout : STD_LOGIC; + SIGNAL wire_n0i01iil_dataout : STD_LOGIC; + SIGNAL wire_n0i01iiO_dataout : STD_LOGIC; + SIGNAL wire_n0i01il_dataout : STD_LOGIC; + SIGNAL wire_n0i01ili_dataout : STD_LOGIC; + SIGNAL wire_n0i01ill_dataout : STD_LOGIC; + SIGNAL wire_n0i01ilO_dataout : STD_LOGIC; + SIGNAL wire_n0i01iO_dataout : STD_LOGIC; + SIGNAL wire_n0i01iOi_dataout : STD_LOGIC; + SIGNAL wire_n0i01iOl_dataout : STD_LOGIC; + SIGNAL wire_n0i01l0i_dataout : STD_LOGIC; + SIGNAL wire_n0i01l0l_dataout : STD_LOGIC; + SIGNAL wire_n0i01l0O_dataout : STD_LOGIC; + SIGNAL wire_n0i01li_dataout : STD_LOGIC; + SIGNAL wire_n0i01lil_dataout : STD_LOGIC; + SIGNAL wire_n0i01liO_dataout : STD_LOGIC; + SIGNAL wire_n0i01ll_dataout : STD_LOGIC; + SIGNAL wire_n0i01lli_dataout : STD_LOGIC; + SIGNAL wire_n0i01lll_dataout : STD_LOGIC; + SIGNAL wire_n0i01lO_dataout : STD_LOGIC; + SIGNAL wire_n0i01O0l_dataout : STD_LOGIC; + SIGNAL wire_n0i01O0O_dataout : STD_LOGIC; + SIGNAL wire_n0i01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i01Oii_dataout : STD_LOGIC; + SIGNAL wire_n0i01Oil_dataout : STD_LOGIC; + SIGNAL wire_n0i01OiO_dataout : STD_LOGIC; + SIGNAL wire_n0i01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i01Oli_dataout : STD_LOGIC; + SIGNAL wire_n0i01Oll_dataout : STD_LOGIC; + SIGNAL wire_n0i01OlO_dataout : STD_LOGIC; + SIGNAL wire_n0i01OO_dataout : STD_LOGIC; + SIGNAL wire_n0i01OOi_dataout : STD_LOGIC; + SIGNAL wire_n0i01OOl_dataout : STD_LOGIC; + SIGNAL wire_n0i01OOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i00i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i00l_dataout : STD_LOGIC; + SIGNAL wire_n0i0i00O_dataout : STD_LOGIC; + SIGNAL wire_n0i0i01i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i01l_dataout : STD_LOGIC; + SIGNAL wire_n0i0i01O_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0ii_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0il_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0iO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0li_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0ll_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0lO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i0i0OO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i10i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i10l_dataout : STD_LOGIC; + SIGNAL wire_n0i0i10O_dataout : STD_LOGIC; + SIGNAL wire_n0i0i11i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i11l_dataout : STD_LOGIC; + SIGNAL wire_n0i0i11O_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1ii_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1il_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1iO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1li_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1ll_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1lO_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i0i1OO_dataout : STD_LOGIC; + SIGNAL wire_n0i0ii0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0ii0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0ii0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0ii1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0ii1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0ii1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0iiii_dataout : STD_LOGIC; + SIGNAL wire_n0i0iiil_dataout : STD_LOGIC; + SIGNAL wire_n0i0iiiO_dataout : STD_LOGIC; + SIGNAL wire_n0i0iil_dataout : STD_LOGIC; + SIGNAL wire_n0i0iili_dataout : STD_LOGIC; + SIGNAL wire_n0i0iill_dataout : STD_LOGIC; + SIGNAL wire_n0i0iilO_dataout : STD_LOGIC; + SIGNAL wire_n0i0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0i0iiOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0iiOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0iiOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0il0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0il0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0il0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0il1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0il1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0il1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0ili_dataout : STD_LOGIC; + SIGNAL wire_n0i0ilii_dataout : STD_LOGIC; + SIGNAL wire_n0i0ilil_dataout : STD_LOGIC; + SIGNAL wire_n0i0iliO_dataout : STD_LOGIC; + SIGNAL wire_n0i0ill_dataout : STD_LOGIC; + SIGNAL wire_n0i0illi_dataout : STD_LOGIC; + SIGNAL wire_n0i0illl_dataout : STD_LOGIC; + SIGNAL wire_n0i0illO_dataout : STD_LOGIC; + SIGNAL wire_n0i0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0i0ilOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0ilOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0ilOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOii_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOil_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOiO_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOli_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOll_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOlO_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0iOOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0l00i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l00l_dataout : STD_LOGIC; + SIGNAL wire_n0i0l00O_dataout : STD_LOGIC; + SIGNAL wire_n0i0l01i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l01l_dataout : STD_LOGIC; + SIGNAL wire_n0i0l01O_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0ii_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0il_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0iO_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0li_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0ll_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0lO_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i0l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0i0l10i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l10l_dataout : STD_LOGIC; + SIGNAL wire_n0i0l10O_dataout : STD_LOGIC; + SIGNAL wire_n0i0l11i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l11l_dataout : STD_LOGIC; + SIGNAL wire_n0i0l11O_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1il_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1iO_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1li_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1ll_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1lO_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i0l1OO_dataout : STD_LOGIC; + SIGNAL wire_n0i0li0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0li0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0li0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0li1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0li1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0li1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0lii_dataout : STD_LOGIC; + SIGNAL wire_n0i0liii_dataout : STD_LOGIC; + SIGNAL wire_n0i0liil_dataout : STD_LOGIC; + SIGNAL wire_n0i0liiO_dataout : STD_LOGIC; + SIGNAL wire_n0i0lil_dataout : STD_LOGIC; + SIGNAL wire_n0i0lili_dataout : STD_LOGIC; + SIGNAL wire_n0i0lill_dataout : STD_LOGIC; + SIGNAL wire_n0i0lilO_dataout : STD_LOGIC; + SIGNAL wire_n0i0liO_dataout : STD_LOGIC; + SIGNAL wire_n0i0liOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0liOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0liOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0ll0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0ll1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0lli_dataout : STD_LOGIC; + SIGNAL wire_n0i0llii_dataout : STD_LOGIC; + SIGNAL wire_n0i0llil_dataout : STD_LOGIC; + SIGNAL wire_n0i0lliO_dataout : STD_LOGIC; + SIGNAL wire_n0i0lll_dataout : STD_LOGIC; + SIGNAL wire_n0i0llli_dataout : STD_LOGIC; + SIGNAL wire_n0i0llll_dataout : STD_LOGIC; + SIGNAL wire_n0i0lllO_dataout : STD_LOGIC; + SIGNAL wire_n0i0llO_dataout : STD_LOGIC; + SIGNAL wire_n0i0llOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0llOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0llOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0lO1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0lO1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0i0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0i0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0i0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0i0Olii_dataout : STD_LOGIC; + SIGNAL wire_n0i0Olil_dataout : STD_LOGIC; + SIGNAL wire_n0i0OliO_dataout : STD_LOGIC; + SIGNAL wire_n0i0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0i0Olli_dataout : STD_LOGIC; + SIGNAL wire_n0i0Olll_dataout : STD_LOGIC; + SIGNAL wire_n0i0OllO_dataout : STD_LOGIC; + SIGNAL wire_n0i0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0i0OlOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0OlOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0OlOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0OO0i_dataout : STD_LOGIC; + SIGNAL wire_n0i0OO0l_dataout : STD_LOGIC; + SIGNAL wire_n0i0OO0O_dataout : STD_LOGIC; + SIGNAL wire_n0i0OO1i_dataout : STD_LOGIC; + SIGNAL wire_n0i0OO1l_dataout : STD_LOGIC; + SIGNAL wire_n0i0OO1O_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOii_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOil_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOiO_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOli_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOll_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOlO_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOO_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOOi_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOOl_dataout : STD_LOGIC; + SIGNAL wire_n0i0OOOO_dataout : STD_LOGIC; + SIGNAL wire_n0i1000i_dataout : STD_LOGIC; + SIGNAL wire_n0i1000O_dataout : STD_LOGIC; + SIGNAL wire_n0i1001l_dataout : STD_LOGIC; + SIGNAL wire_n0i100i_dataout : STD_LOGIC; + SIGNAL wire_n0i100il_dataout : STD_LOGIC; + SIGNAL wire_n0i100l_dataout : STD_LOGIC; + SIGNAL wire_n0i100li_dataout : STD_LOGIC; + SIGNAL wire_n0i100O_dataout : STD_LOGIC; + SIGNAL wire_n0i101i_dataout : STD_LOGIC; + SIGNAL wire_n0i101iO_dataout : STD_LOGIC; + SIGNAL wire_n0i101l_dataout : STD_LOGIC; + SIGNAL wire_n0i101lO_dataout : STD_LOGIC; + SIGNAL wire_n0i101O_dataout : STD_LOGIC; + SIGNAL wire_n0i101Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i10ii_dataout : STD_LOGIC; + SIGNAL wire_n0i10il_dataout : STD_LOGIC; + SIGNAL wire_n0i10iO_dataout : STD_LOGIC; + SIGNAL wire_n0i10iOi_dataout : STD_LOGIC; + SIGNAL wire_n0i10iOl_dataout : STD_LOGIC; + SIGNAL wire_n0i10iOO_dataout : STD_LOGIC; + SIGNAL wire_n0i10l0i_dataout : STD_LOGIC; + SIGNAL wire_n0i10l0l_dataout : STD_LOGIC; + SIGNAL wire_n0i10l0O_dataout : STD_LOGIC; + SIGNAL wire_n0i10l1i_dataout : STD_LOGIC; + SIGNAL wire_n0i10l1l_dataout : STD_LOGIC; + SIGNAL wire_n0i10l1O_dataout : STD_LOGIC; + SIGNAL wire_n0i10li_dataout : STD_LOGIC; + SIGNAL wire_n0i10lii_dataout : STD_LOGIC; + SIGNAL wire_n0i10lil_dataout : STD_LOGIC; + SIGNAL wire_n0i10liO_dataout : STD_LOGIC; + SIGNAL wire_n0i10ll_dataout : STD_LOGIC; + SIGNAL wire_n0i10lli_dataout : STD_LOGIC; + SIGNAL wire_n0i10lll_dataout : STD_LOGIC; + SIGNAL wire_n0i10llO_dataout : STD_LOGIC; + SIGNAL wire_n0i10lO_dataout : STD_LOGIC; + SIGNAL wire_n0i10lOi_dataout : STD_LOGIC; + SIGNAL wire_n0i10lOl_dataout : STD_LOGIC; + SIGNAL wire_n0i10lOO_dataout : STD_LOGIC; + SIGNAL wire_n0i10O0i_dataout : STD_LOGIC; + SIGNAL wire_n0i10O0l_dataout : STD_LOGIC; + SIGNAL wire_n0i10O0O_dataout : STD_LOGIC; + SIGNAL wire_n0i10O1i_dataout : STD_LOGIC; + SIGNAL wire_n0i10O1l_dataout : STD_LOGIC; + SIGNAL wire_n0i10O1O_dataout : STD_LOGIC; + SIGNAL wire_n0i10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i10Oii_dataout : STD_LOGIC; + SIGNAL wire_n0i10Oil_dataout : STD_LOGIC; + SIGNAL wire_n0i10OiO_dataout : STD_LOGIC; + SIGNAL wire_n0i10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i10Oli_dataout : STD_LOGIC; + SIGNAL wire_n0i10Oll_dataout : STD_LOGIC; + SIGNAL wire_n0i10OlO_dataout : STD_LOGIC; + SIGNAL wire_n0i10OO_dataout : STD_LOGIC; + SIGNAL wire_n0i10OOi_dataout : STD_LOGIC; + SIGNAL wire_n0i10OOl_dataout : STD_LOGIC; + SIGNAL wire_n0i10OOO_dataout : STD_LOGIC; + SIGNAL wire_n0i1100i_dataout : STD_LOGIC; + SIGNAL wire_n0i1100l_dataout : STD_LOGIC; + SIGNAL wire_n0i1100O_dataout : STD_LOGIC; + SIGNAL wire_n0i1101l_dataout : STD_LOGIC; + SIGNAL wire_n0i1101O_dataout : STD_LOGIC; + SIGNAL wire_n0i110i_dataout : STD_LOGIC; + SIGNAL wire_n0i110ii_dataout : STD_LOGIC; + SIGNAL wire_n0i110il_dataout : STD_LOGIC; + SIGNAL wire_n0i110iO_dataout : STD_LOGIC; + SIGNAL wire_n0i110l_dataout : STD_LOGIC; + SIGNAL wire_n0i110li_dataout : STD_LOGIC; + SIGNAL wire_n0i110ll_dataout : STD_LOGIC; + SIGNAL wire_n0i110lO_dataout : STD_LOGIC; + SIGNAL wire_n0i110O_dataout : STD_LOGIC; + SIGNAL wire_n0i110Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i110Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i110OO_dataout : STD_LOGIC; + SIGNAL wire_n0i1110i_dataout : STD_LOGIC; + SIGNAL wire_n0i1110l_dataout : STD_LOGIC; + SIGNAL wire_n0i1110O_dataout : STD_LOGIC; + SIGNAL wire_n0i1111i_dataout : STD_LOGIC; + SIGNAL wire_n0i1111l_dataout : STD_LOGIC; + SIGNAL wire_n0i1111O_dataout : STD_LOGIC; + SIGNAL wire_n0i111i_dataout : STD_LOGIC; + SIGNAL wire_n0i111ii_dataout : STD_LOGIC; + SIGNAL wire_n0i111il_dataout : STD_LOGIC; + SIGNAL wire_n0i111iO_dataout : STD_LOGIC; + SIGNAL wire_n0i111l_dataout : STD_LOGIC; + SIGNAL wire_n0i111li_dataout : STD_LOGIC; + SIGNAL wire_n0i111O_dataout : STD_LOGIC; + SIGNAL wire_n0i11i0i_dataout : STD_LOGIC; + SIGNAL wire_n0i11i0l_dataout : STD_LOGIC; + SIGNAL wire_n0i11i0O_dataout : STD_LOGIC; + SIGNAL wire_n0i11i1i_dataout : STD_LOGIC; + SIGNAL wire_n0i11i1l_dataout : STD_LOGIC; + SIGNAL wire_n0i11i1O_dataout : STD_LOGIC; + SIGNAL wire_n0i11ii_dataout : STD_LOGIC; + SIGNAL wire_n0i11iii_dataout : STD_LOGIC; + SIGNAL wire_n0i11iil_dataout : STD_LOGIC; + SIGNAL wire_n0i11iiO_dataout : STD_LOGIC; + SIGNAL wire_n0i11il_dataout : STD_LOGIC; + SIGNAL wire_n0i11ili_dataout : STD_LOGIC; + SIGNAL wire_n0i11ill_dataout : STD_LOGIC; + SIGNAL wire_n0i11ilO_dataout : STD_LOGIC; + SIGNAL wire_n0i11iO_dataout : STD_LOGIC; + SIGNAL wire_n0i11iOi_dataout : STD_LOGIC; + SIGNAL wire_n0i11iOl_dataout : STD_LOGIC; + SIGNAL wire_n0i11iOO_dataout : STD_LOGIC; + SIGNAL wire_n0i11l0l_dataout : STD_LOGIC; + SIGNAL wire_n0i11l0O_dataout : STD_LOGIC; + SIGNAL wire_n0i11l1i_dataout : STD_LOGIC; + SIGNAL wire_n0i11l1l_dataout : STD_LOGIC; + SIGNAL wire_n0i11li_dataout : STD_LOGIC; + SIGNAL wire_n0i11lii_dataout : STD_LOGIC; + SIGNAL wire_n0i11lil_dataout : STD_LOGIC; + SIGNAL wire_n0i11liO_dataout : STD_LOGIC; + SIGNAL wire_n0i11ll_dataout : STD_LOGIC; + SIGNAL wire_n0i11lli_dataout : STD_LOGIC; + SIGNAL wire_n0i11lO_dataout : STD_LOGIC; + SIGNAL wire_n0i11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i11Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i11OO_dataout : STD_LOGIC; + SIGNAL wire_n0i1i00i_dataout : STD_LOGIC; + SIGNAL wire_n0i1i01l_dataout : STD_LOGIC; + SIGNAL wire_n0i1i01O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i10i_dataout : STD_LOGIC; + SIGNAL wire_n0i1i10l_dataout : STD_LOGIC; + SIGNAL wire_n0i1i10O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i11i_dataout : STD_LOGIC; + SIGNAL wire_n0i1i11l_dataout : STD_LOGIC; + SIGNAL wire_n0i1i11O_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1ii_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1il_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1iO_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1li_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1ll_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1lO_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i1i1OO_dataout : STD_LOGIC; + SIGNAL wire_n0i1il0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1il0O_w_lg_dataout14919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1il1O_dataout : STD_LOGIC; + SIGNAL wire_n0i1il1O_w_lg_dataout14921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1ilil_dataout : STD_LOGIC; + SIGNAL wire_n0i1ilil_w_lg_dataout14917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1illl_dataout : STD_LOGIC; + SIGNAL wire_n0i1illl_w_lg_dataout14915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1ilOi_dataout : STD_LOGIC; + SIGNAL wire_n0i1ilOi_w_lg_dataout14913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1ilOO_dataout : STD_LOGIC; + SIGNAL wire_n0i1ilOO_w_lg_dataout14911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1iO0i_dataout : STD_LOGIC; + SIGNAL wire_n0i1iO0i_w_lg_dataout14907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1iO1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1iO1l_w_lg_dataout14909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0i1l00i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l00l_dataout : STD_LOGIC; + SIGNAL wire_n0i1l00O_dataout : STD_LOGIC; + SIGNAL wire_n0i1l01i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l01l_dataout : STD_LOGIC; + SIGNAL wire_n0i1l01O_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0i_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0il_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0l_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0li_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0lO_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i1l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0i1l10O_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1il_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1iO_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1li_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1ll_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1lO_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0i1l1OO_dataout : STD_LOGIC; + SIGNAL wire_n0i1li0i_dataout : STD_LOGIC; + SIGNAL wire_n0i1li0l_dataout : STD_LOGIC; + SIGNAL wire_n0i1li0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1li1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1li1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1li1O_dataout : STD_LOGIC; + SIGNAL wire_n0i1lii_dataout : STD_LOGIC; + SIGNAL wire_n0i1liii_dataout : STD_LOGIC; + SIGNAL wire_n0i1liil_dataout : STD_LOGIC; + SIGNAL wire_n0i1liiO_dataout : STD_LOGIC; + SIGNAL wire_n0i1lil_dataout : STD_LOGIC; + SIGNAL wire_n0i1lili_dataout : STD_LOGIC; + SIGNAL wire_n0i1lill_dataout : STD_LOGIC; + SIGNAL wire_n0i1lilO_dataout : STD_LOGIC; + SIGNAL wire_n0i1liO_dataout : STD_LOGIC; + SIGNAL wire_n0i1liOi_dataout : STD_LOGIC; + SIGNAL wire_n0i1liOl_dataout : STD_LOGIC; + SIGNAL wire_n0i1liOO_dataout : STD_LOGIC; + SIGNAL wire_n0i1ll0i_dataout : STD_LOGIC; + SIGNAL wire_n0i1ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0i1ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1ll1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0i1lli_dataout : STD_LOGIC; + SIGNAL wire_n0i1llii_dataout : STD_LOGIC; + SIGNAL wire_n0i1llil_dataout : STD_LOGIC; + SIGNAL wire_n0i1lll_dataout : STD_LOGIC; + SIGNAL wire_n0i1llO_dataout : STD_LOGIC; + SIGNAL wire_n0i1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0i1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0i1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0i1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0i1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0i1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0i1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0i1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0i1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0i1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0i1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0i1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0i1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0i1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0i1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0i1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0i1OOlO_dataout : STD_LOGIC; + SIGNAL wire_n0i1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0i1OOOi_dataout : STD_LOGIC; + SIGNAL wire_n0i1OOOl_dataout : STD_LOGIC; + SIGNAL wire_n0i1OOOO_dataout : STD_LOGIC; + SIGNAL wire_n0ii000i_dataout : STD_LOGIC; + SIGNAL wire_n0ii000l_dataout : STD_LOGIC; + SIGNAL wire_n0ii000O_dataout : STD_LOGIC; + SIGNAL wire_n0ii001i_dataout : STD_LOGIC; + SIGNAL wire_n0ii001l_dataout : STD_LOGIC; + SIGNAL wire_n0ii001O_dataout : STD_LOGIC; + SIGNAL wire_n0ii00i_dataout : STD_LOGIC; + SIGNAL wire_n0ii00l_dataout : STD_LOGIC; + SIGNAL wire_n0ii00O_dataout : STD_LOGIC; + SIGNAL wire_n0ii010i_dataout : STD_LOGIC; + SIGNAL wire_n0ii010l_dataout : STD_LOGIC; + SIGNAL wire_n0ii010O_dataout : STD_LOGIC; + SIGNAL wire_n0ii011i_dataout : STD_LOGIC; + SIGNAL wire_n0ii011l_dataout : STD_LOGIC; + SIGNAL wire_n0ii011O_dataout : STD_LOGIC; + SIGNAL wire_n0ii01i_dataout : STD_LOGIC; + SIGNAL wire_n0ii01ii_dataout : STD_LOGIC; + SIGNAL wire_n0ii01il_dataout : STD_LOGIC; + SIGNAL wire_n0ii01iO_dataout : STD_LOGIC; + SIGNAL wire_n0ii01l_dataout : STD_LOGIC; + SIGNAL wire_n0ii01li_dataout : STD_LOGIC; + SIGNAL wire_n0ii01ll_dataout : STD_LOGIC; + SIGNAL wire_n0ii01lO_dataout : STD_LOGIC; + SIGNAL wire_n0ii01O_dataout : STD_LOGIC; + SIGNAL wire_n0ii01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ii01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ii01OO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0ii_dataout : STD_LOGIC; + SIGNAL wire_n0ii0il_dataout : STD_LOGIC; + SIGNAL wire_n0ii0iO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0ii0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0ii0li_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lii_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lil_dataout : STD_LOGIC; + SIGNAL wire_n0ii0liO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0ll_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lli_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lll_dataout : STD_LOGIC; + SIGNAL wire_n0ii0llO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0ii0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ii0OO_dataout : STD_LOGIC; + SIGNAL wire_n0ii0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0ii0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0ii0OOO_dataout : STD_LOGIC; + SIGNAL wire_n0ii10i_dataout : STD_LOGIC; + SIGNAL wire_n0ii10l_dataout : STD_LOGIC; + SIGNAL wire_n0ii10O_dataout : STD_LOGIC; + SIGNAL wire_n0ii10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ii10OO_dataout : STD_LOGIC; + SIGNAL wire_n0ii110i_dataout : STD_LOGIC; + SIGNAL wire_n0ii110l_dataout : STD_LOGIC; + SIGNAL wire_n0ii110O_dataout : STD_LOGIC; + SIGNAL wire_n0ii111i_dataout : STD_LOGIC; + SIGNAL wire_n0ii111l_dataout : STD_LOGIC; + SIGNAL wire_n0ii111O_dataout : STD_LOGIC; + SIGNAL wire_n0ii11i_dataout : STD_LOGIC; + SIGNAL wire_n0ii11ii_dataout : STD_LOGIC; + SIGNAL wire_n0ii11il_dataout : STD_LOGIC; + SIGNAL wire_n0ii11iO_dataout : STD_LOGIC; + SIGNAL wire_n0ii11l_dataout : STD_LOGIC; + SIGNAL wire_n0ii11li_dataout : STD_LOGIC; + SIGNAL wire_n0ii11ll_dataout : STD_LOGIC; + SIGNAL wire_n0ii11lO_dataout : STD_LOGIC; + SIGNAL wire_n0ii11O_dataout : STD_LOGIC; + SIGNAL wire_n0ii11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ii11Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ii11OO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0ii1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0ii1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0ii1ii_dataout : STD_LOGIC; + SIGNAL wire_n0ii1il_dataout : STD_LOGIC; + SIGNAL wire_n0ii1iO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1l0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii1l0l_dataout : STD_LOGIC; + SIGNAL wire_n0ii1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0ii1li_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lii_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lil_dataout : STD_LOGIC; + SIGNAL wire_n0ii1liO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1ll_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lli_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lll_dataout : STD_LOGIC; + SIGNAL wire_n0ii1llO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0ii1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0ii1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0ii1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0ii1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0ii1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0ii1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ii1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0ii1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0ii1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ii1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0ii1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0ii1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1OO_dataout : STD_LOGIC; + SIGNAL wire_n0ii1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0ii1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0ii1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0iii0i_dataout : STD_LOGIC; + SIGNAL wire_n0iii0l_dataout : STD_LOGIC; + SIGNAL wire_n0iii0O_dataout : STD_LOGIC; + SIGNAL wire_n0iii10i_dataout : STD_LOGIC; + SIGNAL wire_n0iii10l_dataout : STD_LOGIC; + SIGNAL wire_n0iii10O_dataout : STD_LOGIC; + SIGNAL wire_n0iii11i_dataout : STD_LOGIC; + SIGNAL wire_n0iii11l_dataout : STD_LOGIC; + SIGNAL wire_n0iii11O_dataout : STD_LOGIC; + SIGNAL wire_n0iii1i_dataout : STD_LOGIC; + SIGNAL wire_n0iii1ii_dataout : STD_LOGIC; + SIGNAL wire_n0iii1l_dataout : STD_LOGIC; + SIGNAL wire_n0iii1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiii0i_dataout : STD_LOGIC; + SIGNAL wire_n0iiii0l_dataout : STD_LOGIC; + SIGNAL wire_n0iiii0O_dataout : STD_LOGIC; + SIGNAL wire_n0iiii1i_dataout : STD_LOGIC; + SIGNAL wire_n0iiii1l_dataout : STD_LOGIC; + SIGNAL wire_n0iiii1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiiii_dataout : STD_LOGIC; + SIGNAL wire_n0iiiiii_dataout : STD_LOGIC; + SIGNAL wire_n0iiiiil_dataout : STD_LOGIC; + SIGNAL wire_n0iiiiiO_dataout : STD_LOGIC; + SIGNAL wire_n0iiiil_dataout : STD_LOGIC; + SIGNAL wire_n0iiiili_dataout : STD_LOGIC; + SIGNAL wire_n0iiiill_dataout : STD_LOGIC; + SIGNAL wire_n0iiiilO_dataout : STD_LOGIC; + SIGNAL wire_n0iiiiO_dataout : STD_LOGIC; + SIGNAL wire_n0iiiiOi_dataout : STD_LOGIC; + SIGNAL wire_n0iiiiOl_dataout : STD_LOGIC; + SIGNAL wire_n0iiiiOO_dataout : STD_LOGIC; + SIGNAL wire_n0iiil0i_dataout : STD_LOGIC; + SIGNAL wire_n0iiil0l_dataout : STD_LOGIC; + SIGNAL wire_n0iiil0O_dataout : STD_LOGIC; + SIGNAL wire_n0iiil1i_dataout : STD_LOGIC; + SIGNAL wire_n0iiil1l_dataout : STD_LOGIC; + SIGNAL wire_n0iiil1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiili_dataout : STD_LOGIC; + SIGNAL wire_n0iiill_dataout : STD_LOGIC; + SIGNAL wire_n0iiillO_dataout : STD_LOGIC; + SIGNAL wire_n0iiillO_w_lg_w_lg_w_lg_dataout14412w14418w14419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iiillO_w_lg_w_lg_dataout14412w14418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iiillO_w_lg_dataout14425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iiillO_w_lg_dataout14412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iiilO_dataout : STD_LOGIC; + SIGNAL wire_n0iiilOi_dataout : STD_LOGIC; + SIGNAL wire_n0iiilOO_dataout : STD_LOGIC; + SIGNAL wire_n0iiiO1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiiOi_dataout : STD_LOGIC; + SIGNAL wire_n0iiiOl_dataout : STD_LOGIC; + SIGNAL wire_n0iiiOO_dataout : STD_LOGIC; + SIGNAL wire_n0iil00i_dataout : STD_LOGIC; + SIGNAL wire_n0iil00l_dataout : STD_LOGIC; + SIGNAL wire_n0iil00O_dataout : STD_LOGIC; + SIGNAL wire_n0iil01i_dataout : STD_LOGIC; + SIGNAL wire_n0iil01l_dataout : STD_LOGIC; + SIGNAL wire_n0iil01O_dataout : STD_LOGIC; + SIGNAL wire_n0iil0i_dataout : STD_LOGIC; + SIGNAL wire_n0iil0ii_dataout : STD_LOGIC; + SIGNAL wire_n0iil0il_dataout : STD_LOGIC; + SIGNAL wire_n0iil0iO_dataout : STD_LOGIC; + SIGNAL wire_n0iil0l_dataout : STD_LOGIC; + SIGNAL wire_n0iil0li_dataout : STD_LOGIC; + SIGNAL wire_n0iil0ll_dataout : STD_LOGIC; + SIGNAL wire_n0iil0lO_dataout : STD_LOGIC; + SIGNAL wire_n0iil0O_dataout : STD_LOGIC; + SIGNAL wire_n0iil0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0iil0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0iil0OO_dataout : STD_LOGIC; + SIGNAL wire_n0iil1i_dataout : STD_LOGIC; + SIGNAL wire_n0iil1l_dataout : STD_LOGIC; + SIGNAL wire_n0iil1O_dataout : STD_LOGIC; + SIGNAL wire_n0iili0i_dataout : STD_LOGIC; + SIGNAL wire_n0iili0l_dataout : STD_LOGIC; + SIGNAL wire_n0iili0O_dataout : STD_LOGIC; + SIGNAL wire_n0iili1i_dataout : STD_LOGIC; + SIGNAL wire_n0iili1l_dataout : STD_LOGIC; + SIGNAL wire_n0iili1O_dataout : STD_LOGIC; + SIGNAL wire_n0iilii_dataout : STD_LOGIC; + SIGNAL wire_n0iiliii_dataout : STD_LOGIC; + SIGNAL wire_n0iiliil_dataout : STD_LOGIC; + SIGNAL wire_n0iiliiO_dataout : STD_LOGIC; + SIGNAL wire_n0iilil_dataout : STD_LOGIC; + SIGNAL wire_n0iilili_dataout : STD_LOGIC; + SIGNAL wire_n0iilill_dataout : STD_LOGIC; + SIGNAL wire_n0iililO_dataout : STD_LOGIC; + SIGNAL wire_n0iiliO_dataout : STD_LOGIC; + SIGNAL wire_n0iiliOi_dataout : STD_LOGIC; + SIGNAL wire_n0iiliOl_dataout : STD_LOGIC; + SIGNAL wire_n0iiliOO_dataout : STD_LOGIC; + SIGNAL wire_n0iill0i_dataout : STD_LOGIC; + SIGNAL wire_n0iill0l_dataout : STD_LOGIC; + SIGNAL wire_n0iill0O_dataout : STD_LOGIC; + SIGNAL wire_n0iill1i_dataout : STD_LOGIC; + SIGNAL wire_n0iill1l_dataout : STD_LOGIC; + SIGNAL wire_n0iill1O_dataout : STD_LOGIC; + SIGNAL wire_n0iilli_dataout : STD_LOGIC; + SIGNAL wire_n0iillii_dataout : STD_LOGIC; + SIGNAL wire_n0iillil_dataout : STD_LOGIC; + SIGNAL wire_n0iilliO_dataout : STD_LOGIC; + SIGNAL wire_n0iilll_dataout : STD_LOGIC; + SIGNAL wire_n0iillli_dataout : STD_LOGIC; + SIGNAL wire_n0iillll_dataout : STD_LOGIC; + SIGNAL wire_n0iillO_dataout : STD_LOGIC; + SIGNAL wire_n0iilO0O_dataout : STD_LOGIC; + SIGNAL wire_n0iilO1i_dataout : STD_LOGIC; + SIGNAL wire_n0iilO1l_dataout : STD_LOGIC; + SIGNAL wire_n0iilOi_dataout : STD_LOGIC; + SIGNAL wire_n0iilOii_dataout : STD_LOGIC; + SIGNAL wire_n0iilOil_dataout : STD_LOGIC; + SIGNAL wire_n0iilOiO_dataout : STD_LOGIC; + SIGNAL wire_n0iilOli_dataout : STD_LOGIC; + SIGNAL wire_n0iilOlO_dataout : STD_LOGIC; + SIGNAL wire_n0iilOOi_dataout : STD_LOGIC; + SIGNAL wire_n0iilOOl_dataout : STD_LOGIC; + SIGNAL wire_n0iiO00i_dataout : STD_LOGIC; + SIGNAL wire_n0iiO00l_dataout : STD_LOGIC; + SIGNAL wire_n0iiO00O_dataout : STD_LOGIC; + SIGNAL wire_n0iiO01i_dataout : STD_LOGIC; + SIGNAL wire_n0iiO01l_dataout : STD_LOGIC; + SIGNAL wire_n0iiO01O_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0ii_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0il_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0iO_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0li_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0ll_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0lO_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0iiO0OO_dataout : STD_LOGIC; + SIGNAL wire_n0iiO1iO_dataout : STD_LOGIC; + SIGNAL wire_n0iiO1li_dataout : STD_LOGIC; + SIGNAL wire_n0iiO1OO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOi0i_dataout : STD_LOGIC; + SIGNAL wire_n0iiOi0l_dataout : STD_LOGIC; + SIGNAL wire_n0iiOi0O_dataout : STD_LOGIC; + SIGNAL wire_n0iiOi1i_dataout : STD_LOGIC; + SIGNAL wire_n0iiOi1l_dataout : STD_LOGIC; + SIGNAL wire_n0iiOi1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiOiii_dataout : STD_LOGIC; + SIGNAL wire_n0iiOiil_dataout : STD_LOGIC; + SIGNAL wire_n0iiOiiO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOili_dataout : STD_LOGIC; + SIGNAL wire_n0iiOill_dataout : STD_LOGIC; + SIGNAL wire_n0iiOilO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOiOi_dataout : STD_LOGIC; + SIGNAL wire_n0iiOiOl_dataout : STD_LOGIC; + SIGNAL wire_n0iiOiOO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOl0i_dataout : STD_LOGIC; + SIGNAL wire_n0iiOl0l_dataout : STD_LOGIC; + SIGNAL wire_n0iiOl0O_dataout : STD_LOGIC; + SIGNAL wire_n0iiOl1i_dataout : STD_LOGIC; + SIGNAL wire_n0iiOl1l_dataout : STD_LOGIC; + SIGNAL wire_n0iiOl1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiOlii_dataout : STD_LOGIC; + SIGNAL wire_n0iiOlil_dataout : STD_LOGIC; + SIGNAL wire_n0iiOliO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOlli_dataout : STD_LOGIC; + SIGNAL wire_n0iiOlll_dataout : STD_LOGIC; + SIGNAL wire_n0iiOllO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0iiOlOl_dataout : STD_LOGIC; + SIGNAL wire_n0iiOlOO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOO0i_dataout : STD_LOGIC; + SIGNAL wire_n0iiOO0l_dataout : STD_LOGIC; + SIGNAL wire_n0iiOO0O_dataout : STD_LOGIC; + SIGNAL wire_n0iiOO1i_dataout : STD_LOGIC; + SIGNAL wire_n0iiOO1l_dataout : STD_LOGIC; + SIGNAL wire_n0iiOO1O_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOii_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOil_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOiO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOli_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOll_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0iiOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0il000i_dataout : STD_LOGIC; + SIGNAL wire_n0il000l_dataout : STD_LOGIC; + SIGNAL wire_n0il000O_dataout : STD_LOGIC; + SIGNAL wire_n0il001i_dataout : STD_LOGIC; + SIGNAL wire_n0il001l_dataout : STD_LOGIC; + SIGNAL wire_n0il001O_dataout : STD_LOGIC; + SIGNAL wire_n0il00ii_dataout : STD_LOGIC; + SIGNAL wire_n0il00il_dataout : STD_LOGIC; + SIGNAL wire_n0il00iO_dataout : STD_LOGIC; + SIGNAL wire_n0il00li_dataout : STD_LOGIC; + SIGNAL wire_n0il00ll_dataout : STD_LOGIC; + SIGNAL wire_n0il00lO_dataout : STD_LOGIC; + SIGNAL wire_n0il00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0il00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0il00OO_dataout : STD_LOGIC; + SIGNAL wire_n0il010i_dataout : STD_LOGIC; + SIGNAL wire_n0il010l_dataout : STD_LOGIC; + SIGNAL wire_n0il010O_dataout : STD_LOGIC; + SIGNAL wire_n0il011i_dataout : STD_LOGIC; + SIGNAL wire_n0il011l_dataout : STD_LOGIC; + SIGNAL wire_n0il011O_dataout : STD_LOGIC; + SIGNAL wire_n0il01ii_dataout : STD_LOGIC; + SIGNAL wire_n0il01il_dataout : STD_LOGIC; + SIGNAL wire_n0il01iO_dataout : STD_LOGIC; + SIGNAL wire_n0il01li_dataout : STD_LOGIC; + SIGNAL wire_n0il01ll_dataout : STD_LOGIC; + SIGNAL wire_n0il01lO_dataout : STD_LOGIC; + SIGNAL wire_n0il01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0il01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0il01OO_dataout : STD_LOGIC; + SIGNAL wire_n0il0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0il0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0il0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0il0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0il0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0il0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0il0iii_dataout : STD_LOGIC; + SIGNAL wire_n0il0iil_dataout : STD_LOGIC; + SIGNAL wire_n0il0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0il0ili_dataout : STD_LOGIC; + SIGNAL wire_n0il0ill_dataout : STD_LOGIC; + SIGNAL wire_n0il0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0il0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0il0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0il0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0il0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0il0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0il0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0il0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0il0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0il0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0il0lii_dataout : STD_LOGIC; + SIGNAL wire_n0il0lil_dataout : STD_LOGIC; + SIGNAL wire_n0il0liO_dataout : STD_LOGIC; + SIGNAL wire_n0il0lli_dataout : STD_LOGIC; + SIGNAL wire_n0il0lll_dataout : STD_LOGIC; + SIGNAL wire_n0il0llO_dataout : STD_LOGIC; + SIGNAL wire_n0il0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0il0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0il0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0il0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0il0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0il0OOO_dataout : STD_LOGIC; + SIGNAL wire_n0il100i_dataout : STD_LOGIC; + SIGNAL wire_n0il100l_dataout : STD_LOGIC; + SIGNAL wire_n0il100O_dataout : STD_LOGIC; + SIGNAL wire_n0il101i_dataout : STD_LOGIC; + SIGNAL wire_n0il101l_dataout : STD_LOGIC; + SIGNAL wire_n0il101O_dataout : STD_LOGIC; + SIGNAL wire_n0il10ii_dataout : STD_LOGIC; + SIGNAL wire_n0il10il_dataout : STD_LOGIC; + SIGNAL wire_n0il10iO_dataout : STD_LOGIC; + SIGNAL wire_n0il10li_dataout : STD_LOGIC; + SIGNAL wire_n0il10ll_dataout : STD_LOGIC; + SIGNAL wire_n0il10lO_dataout : STD_LOGIC; + SIGNAL wire_n0il10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0il10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0il10OO_dataout : STD_LOGIC; + SIGNAL wire_n0il110i_dataout : STD_LOGIC; + SIGNAL wire_n0il110l_dataout : STD_LOGIC; + SIGNAL wire_n0il110O_dataout : STD_LOGIC; + SIGNAL wire_n0il111i_dataout : STD_LOGIC; + SIGNAL wire_n0il111l_dataout : STD_LOGIC; + SIGNAL wire_n0il111O_dataout : STD_LOGIC; + SIGNAL wire_n0il11ii_dataout : STD_LOGIC; + SIGNAL wire_n0il11il_dataout : STD_LOGIC; + SIGNAL wire_n0il11iO_dataout : STD_LOGIC; + SIGNAL wire_n0il11li_dataout : STD_LOGIC; + SIGNAL wire_n0il11ll_dataout : STD_LOGIC; + SIGNAL wire_n0il11lO_dataout : STD_LOGIC; + SIGNAL wire_n0il11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0il11Ol_dataout : STD_LOGIC; + SIGNAL wire_n0il11OO_dataout : STD_LOGIC; + SIGNAL wire_n0il1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0il1i0l_dataout : STD_LOGIC; + SIGNAL wire_n0il1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0il1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0il1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0il1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0il1iii_dataout : STD_LOGIC; + SIGNAL wire_n0il1iil_dataout : STD_LOGIC; + SIGNAL wire_n0il1iiO_dataout : STD_LOGIC; + SIGNAL wire_n0il1ili_dataout : STD_LOGIC; + SIGNAL wire_n0il1ill_dataout : STD_LOGIC; + SIGNAL wire_n0il1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0il1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0il1iOl_dataout : STD_LOGIC; + SIGNAL wire_n0il1iOO_dataout : STD_LOGIC; + SIGNAL wire_n0il1l1i_dataout : STD_LOGIC; + SIGNAL wire_n0il1l1l_dataout : STD_LOGIC; + SIGNAL wire_n0il1lll_dataout : STD_LOGIC; + SIGNAL wire_n0il1llO_dataout : STD_LOGIC; + SIGNAL wire_n0il1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0il1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0il1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0il1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0il1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0il1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0il1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0il1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0il1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0il1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0il1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0il1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0il1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0il1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0il1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0il1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0il1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0il1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0ili01i_dataout : STD_LOGIC; + SIGNAL wire_n0ili0ii_dataout : STD_LOGIC; + SIGNAL wire_n0ili0il_dataout : STD_LOGIC; + SIGNAL wire_n0ili10i_dataout : STD_LOGIC; + SIGNAL wire_n0ili10l_dataout : STD_LOGIC; + SIGNAL wire_n0ili10O_dataout : STD_LOGIC; + SIGNAL wire_n0ili11i_dataout : STD_LOGIC; + SIGNAL wire_n0ili11l_dataout : STD_LOGIC; + SIGNAL wire_n0ili11O_dataout : STD_LOGIC; + SIGNAL wire_n0ili1ii_dataout : STD_LOGIC; + SIGNAL wire_n0ili1il_dataout : STD_LOGIC; + SIGNAL wire_n0ili1iO_dataout : STD_LOGIC; + SIGNAL wire_n0ili1li_dataout : STD_LOGIC; + SIGNAL wire_n0ili1ll_dataout : STD_LOGIC; + SIGNAL wire_n0ili1lO_dataout : STD_LOGIC; + SIGNAL wire_n0ili1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ili1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ili1OO_dataout : STD_LOGIC; + SIGNAL wire_n0iliiOi_dataout : STD_LOGIC; + SIGNAL wire_n0iliiOl_dataout : STD_LOGIC; + SIGNAL wire_n0iliiOO_dataout : STD_LOGIC; + SIGNAL wire_n0ilil0i_dataout : STD_LOGIC; + SIGNAL wire_n0ilil0l_dataout : STD_LOGIC; + SIGNAL wire_n0ilil0O_dataout : STD_LOGIC; + SIGNAL wire_n0ilil1i_dataout : STD_LOGIC; + SIGNAL wire_n0ilil1l_dataout : STD_LOGIC; + SIGNAL wire_n0ilil1O_dataout : STD_LOGIC; + SIGNAL wire_n0ililii_dataout : STD_LOGIC; + SIGNAL wire_n0ililil_dataout : STD_LOGIC; + SIGNAL wire_n0ililiO_dataout : STD_LOGIC; + SIGNAL wire_n0ililli_dataout : STD_LOGIC; + SIGNAL wire_n0ililll_dataout : STD_LOGIC; + SIGNAL wire_n0ilillO_dataout : STD_LOGIC; + SIGNAL wire_n0ililOi_dataout : STD_LOGIC; + SIGNAL wire_n0ililOl_dataout : STD_LOGIC; + SIGNAL wire_n0iliO0O_dataout : STD_LOGIC; + SIGNAL wire_n0iliOii_dataout : STD_LOGIC; + SIGNAL wire_n0iliOil_dataout : STD_LOGIC; + SIGNAL wire_n0iliOiO_dataout : STD_LOGIC; + SIGNAL wire_n0iliOli_dataout : STD_LOGIC; + SIGNAL wire_n0iliOll_dataout : STD_LOGIC; + SIGNAL wire_n0iliOlO_dataout : STD_LOGIC; + SIGNAL wire_n0iliOOi_dataout : STD_LOGIC; + SIGNAL wire_n0iliOOl_dataout : STD_LOGIC; + SIGNAL wire_n0iliOOO_dataout : STD_LOGIC; + SIGNAL wire_n0ill00i_dataout : STD_LOGIC; + SIGNAL wire_n0ill00l_dataout : STD_LOGIC; + SIGNAL wire_n0ill00O_dataout : STD_LOGIC; + SIGNAL wire_n0ill01i_dataout : STD_LOGIC; + SIGNAL wire_n0ill01l_dataout : STD_LOGIC; + SIGNAL wire_n0ill01O_dataout : STD_LOGIC; + SIGNAL wire_n0ill0iO_dataout : STD_LOGIC; + SIGNAL wire_n0ill0li_dataout : STD_LOGIC; + SIGNAL wire_n0ill0ll_dataout : STD_LOGIC; + SIGNAL wire_n0ill0lO_dataout : STD_LOGIC; + SIGNAL wire_n0ill0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ill0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ill10i_dataout : STD_LOGIC; + SIGNAL wire_n0ill10l_dataout : STD_LOGIC; + SIGNAL wire_n0ill10O_dataout : STD_LOGIC; + SIGNAL wire_n0ill11i_dataout : STD_LOGIC; + SIGNAL wire_n0ill11l_dataout : STD_LOGIC; + SIGNAL wire_n0ill11O_dataout : STD_LOGIC; + SIGNAL wire_n0ill1ii_dataout : STD_LOGIC; + SIGNAL wire_n0ill1il_dataout : STD_LOGIC; + SIGNAL wire_n0ill1iO_dataout : STD_LOGIC; + SIGNAL wire_n0ill1li_dataout : STD_LOGIC; + SIGNAL wire_n0ill1ll_dataout : STD_LOGIC; + SIGNAL wire_n0ill1lO_dataout : STD_LOGIC; + SIGNAL wire_n0ill1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ill1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ill1OO_dataout : STD_LOGIC; + SIGNAL wire_n0illlOi_dataout : STD_LOGIC; + SIGNAL wire_n0illO0O_dataout : STD_LOGIC; + SIGNAL wire_n0illO1i_dataout : STD_LOGIC; + SIGNAL wire_n0illO1O_dataout : STD_LOGIC; + SIGNAL wire_n0illOil_dataout : STD_LOGIC; + SIGNAL wire_n0illOli_dataout : STD_LOGIC; + SIGNAL wire_n0illOlO_dataout : STD_LOGIC; + SIGNAL wire_n0illOOl_dataout : STD_LOGIC; + SIGNAL wire_n0ilO00i_dataout : STD_LOGIC; + SIGNAL wire_n0ilO00l_dataout : STD_LOGIC; + SIGNAL wire_n0ilO00O_dataout : STD_LOGIC; + SIGNAL wire_n0ilO01l_dataout : STD_LOGIC; + SIGNAL wire_n0ilO01O_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0ii_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0il_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0iO_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0li_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0ll_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0lO_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ilO0OO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOi0i_dataout : STD_LOGIC; + SIGNAL wire_n0ilOi0l_dataout : STD_LOGIC; + SIGNAL wire_n0ilOi0O_dataout : STD_LOGIC; + SIGNAL wire_n0ilOi1i_dataout : STD_LOGIC; + SIGNAL wire_n0ilOi1l_dataout : STD_LOGIC; + SIGNAL wire_n0ilOi1O_dataout : STD_LOGIC; + SIGNAL wire_n0ilOiii_dataout : STD_LOGIC; + SIGNAL wire_n0ilOiil_dataout : STD_LOGIC; + SIGNAL wire_n0ilOiiO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOili_dataout : STD_LOGIC; + SIGNAL wire_n0ilOill_dataout : STD_LOGIC; + SIGNAL wire_n0ilOilO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOiOi_dataout : STD_LOGIC; + SIGNAL wire_n0ilOiOl_dataout : STD_LOGIC; + SIGNAL wire_n0ilOiOO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOl0i_dataout : STD_LOGIC; + SIGNAL wire_n0ilOl0l_dataout : STD_LOGIC; + SIGNAL wire_n0ilOl0O_dataout : STD_LOGIC; + SIGNAL wire_n0ilOl1i_dataout : STD_LOGIC; + SIGNAL wire_n0ilOl1l_dataout : STD_LOGIC; + SIGNAL wire_n0ilOl1O_dataout : STD_LOGIC; + SIGNAL wire_n0ilOlii_dataout : STD_LOGIC; + SIGNAL wire_n0ilOlil_dataout : STD_LOGIC; + SIGNAL wire_n0ilOliO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOlli_dataout : STD_LOGIC; + SIGNAL wire_n0ilOlll_dataout : STD_LOGIC; + SIGNAL wire_n0ilOllO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0ilOlOl_dataout : STD_LOGIC; + SIGNAL wire_n0ilOlOO_dataout : STD_LOGIC; + SIGNAL wire_n0ilOO0i_dataout : STD_LOGIC; + SIGNAL wire_n0ilOO0O_dataout : STD_LOGIC; + SIGNAL wire_n0ilOO1i_dataout : STD_LOGIC; + SIGNAL wire_n0ilOO1l_dataout : STD_LOGIC; + SIGNAL wire_n0ilOO1O_dataout : STD_LOGIC; + SIGNAL wire_n0ilOOii_dataout : STD_LOGIC; + SIGNAL wire_n0ilOOil_dataout : STD_LOGIC; + SIGNAL wire_n0iO000i_dataout : STD_LOGIC; + SIGNAL wire_n0iO000l_dataout : STD_LOGIC; + SIGNAL wire_n0iO000O_dataout : STD_LOGIC; + SIGNAL wire_n0iO001i_dataout : STD_LOGIC; + SIGNAL wire_n0iO001l_dataout : STD_LOGIC; + SIGNAL wire_n0iO001O_dataout : STD_LOGIC; + SIGNAL wire_n0iO00ii_dataout : STD_LOGIC; + SIGNAL wire_n0iO00il_dataout : STD_LOGIC; + SIGNAL wire_n0iO00iO_dataout : STD_LOGIC; + SIGNAL wire_n0iO00li_dataout : STD_LOGIC; + SIGNAL wire_n0iO00ll_dataout : STD_LOGIC; + SIGNAL wire_n0iO00lO_dataout : STD_LOGIC; + SIGNAL wire_n0iO010i_dataout : STD_LOGIC; + SIGNAL wire_n0iO010l_dataout : STD_LOGIC; + SIGNAL wire_n0iO010O_dataout : STD_LOGIC; + SIGNAL wire_n0iO011i_dataout : STD_LOGIC; + SIGNAL wire_n0iO011l_dataout : STD_LOGIC; + SIGNAL wire_n0iO011O_dataout : STD_LOGIC; + SIGNAL wire_n0iO01ii_dataout : STD_LOGIC; + SIGNAL wire_n0iO01il_dataout : STD_LOGIC; + SIGNAL wire_n0iO01iO_dataout : STD_LOGIC; + SIGNAL wire_n0iO01li_dataout : STD_LOGIC; + SIGNAL wire_n0iO01ll_dataout : STD_LOGIC; + SIGNAL wire_n0iO01lO_dataout : STD_LOGIC; + SIGNAL wire_n0iO01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0iO01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0iO01OO_dataout : STD_LOGIC; + SIGNAL wire_n0iO10ii_dataout : STD_LOGIC; + SIGNAL wire_n0iO10ii_w_lg_dataout14014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO10li_dataout : STD_LOGIC; + SIGNAL wire_n0iO10li_w_lg_dataout14012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO10lO_dataout : STD_LOGIC; + SIGNAL wire_n0iO10lO_w_lg_dataout14010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO10OO_dataout : STD_LOGIC; + SIGNAL wire_n0iO10OO_w_lg_dataout14008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0iO1i0i_w_lg_dataout14004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0iO1i0O_w_lg_dataout14002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0iO1i1l_w_lg_dataout14006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO1iil_dataout : STD_LOGIC; + SIGNAL wire_n0iO1iil_w_lg_dataout14000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0iO1lli_dataout : STD_LOGIC; + SIGNAL wire_n0iO1lll_dataout : STD_LOGIC; + SIGNAL wire_n0iO1llO_dataout : STD_LOGIC; + SIGNAL wire_n0iO1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0iO1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0iO1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0iO1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0iO1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0iO1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0iO1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0iO1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0iO1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0iO1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0iO1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0iO1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0iO1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0iO1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0iO1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0iO1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0iO1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0iO1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0iOil0i_dataout : STD_LOGIC; + SIGNAL wire_n0iOil0l_dataout : STD_LOGIC; + SIGNAL wire_n0iOil0O_dataout : STD_LOGIC; + SIGNAL wire_n0iOil1i_dataout : STD_LOGIC; + SIGNAL wire_n0iOil1l_dataout : STD_LOGIC; + SIGNAL wire_n0iOil1O_dataout : STD_LOGIC; + SIGNAL wire_n0iOilii_dataout : STD_LOGIC; + SIGNAL wire_n0iOilil_dataout : STD_LOGIC; + SIGNAL wire_n0iOiliO_dataout : STD_LOGIC; + SIGNAL wire_n0iOilOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOilOO_dataout : STD_LOGIC; + SIGNAL wire_n0iOiO0i_dataout : STD_LOGIC; + SIGNAL wire_n0iOiO1i_dataout : STD_LOGIC; + SIGNAL wire_n0iOiO1l_dataout : STD_LOGIC; + SIGNAL wire_n0iOiO1O_dataout : STD_LOGIC; + SIGNAL wire_n0iOiOii_dataout : STD_LOGIC; + SIGNAL wire_n0iOiOil_dataout : STD_LOGIC; + SIGNAL wire_n0iOiOiO_dataout : STD_LOGIC; + SIGNAL wire_n0iOl01i_dataout : STD_LOGIC; + SIGNAL wire_n0iOl01l_dataout : STD_LOGIC; + SIGNAL wire_n0iOl01O_dataout : STD_LOGIC; + SIGNAL wire_n0iOl0il_dataout : STD_LOGIC; + SIGNAL wire_n0iOl0iO_dataout : STD_LOGIC; + SIGNAL wire_n0iOl0li_dataout : STD_LOGIC; + SIGNAL wire_n0iOl0lO_dataout : STD_LOGIC; + SIGNAL wire_n0iOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0iOl0OO_dataout : STD_LOGIC; + SIGNAL wire_n0iOl10i_dataout : STD_LOGIC; + SIGNAL wire_n0iOl10l_dataout : STD_LOGIC; + SIGNAL wire_n0iOl10O_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1ii_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1il_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1iO_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1li_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1ll_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1lO_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0iOl1OO_dataout : STD_LOGIC; + SIGNAL wire_n0iOliiO_dataout : STD_LOGIC; + SIGNAL wire_n0iOlili_dataout : STD_LOGIC; + SIGNAL wire_n0iOlill_dataout : STD_LOGIC; + SIGNAL wire_n0iOlilO_dataout : STD_LOGIC; + SIGNAL wire_n0iOliOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOliOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOliOO_dataout : STD_LOGIC; + SIGNAL wire_n0iOll0i_dataout : STD_LOGIC; + SIGNAL wire_n0iOll0l_dataout : STD_LOGIC; + SIGNAL wire_n0iOll0O_dataout : STD_LOGIC; + SIGNAL wire_n0iOll1i_dataout : STD_LOGIC; + SIGNAL wire_n0iOll1l_dataout : STD_LOGIC; + SIGNAL wire_n0iOll1O_dataout : STD_LOGIC; + SIGNAL wire_n0iOllii_dataout : STD_LOGIC; + SIGNAL wire_n0iOllil_dataout : STD_LOGIC; + SIGNAL wire_n0iOlliO_dataout : STD_LOGIC; + SIGNAL wire_n0iOllli_dataout : STD_LOGIC; + SIGNAL wire_n0iOllll_dataout : STD_LOGIC; + SIGNAL wire_n0iOlllO_dataout : STD_LOGIC; + SIGNAL wire_n0iOllOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOllOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOllOO_dataout : STD_LOGIC; + SIGNAL wire_n0iOlO1i_dataout : STD_LOGIC; + SIGNAL wire_n0iOlO1l_dataout : STD_LOGIC; + SIGNAL wire_n0iOlO1O_dataout : STD_LOGIC; + SIGNAL wire_n0iOOili_dataout : STD_LOGIC; + SIGNAL wire_n0iOOill_dataout : STD_LOGIC; + SIGNAL wire_n0iOOilO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOiOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOOiOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOOiOO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOl0i_dataout : STD_LOGIC; + SIGNAL wire_n0iOOl0l_dataout : STD_LOGIC; + SIGNAL wire_n0iOOl0O_dataout : STD_LOGIC; + SIGNAL wire_n0iOOl1i_dataout : STD_LOGIC; + SIGNAL wire_n0iOOl1l_dataout : STD_LOGIC; + SIGNAL wire_n0iOOl1O_dataout : STD_LOGIC; + SIGNAL wire_n0iOOlii_dataout : STD_LOGIC; + SIGNAL wire_n0iOOlil_dataout : STD_LOGIC; + SIGNAL wire_n0iOOliO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOlli_dataout : STD_LOGIC; + SIGNAL wire_n0iOOlll_dataout : STD_LOGIC; + SIGNAL wire_n0iOOllO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOOlOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOOlOO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOO0i_dataout : STD_LOGIC; + SIGNAL wire_n0iOOO0l_dataout : STD_LOGIC; + SIGNAL wire_n0iOOO0O_dataout : STD_LOGIC; + SIGNAL wire_n0iOOO1i_dataout : STD_LOGIC; + SIGNAL wire_n0iOOO1l_dataout : STD_LOGIC; + SIGNAL wire_n0iOOO1O_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOii_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOil_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOiO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOli_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOll_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0iOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0000i_dataout : STD_LOGIC; + SIGNAL wire_n0l0000l_dataout : STD_LOGIC; + SIGNAL wire_n0l0000O_dataout : STD_LOGIC; + SIGNAL wire_n0l0001i_dataout : STD_LOGIC; + SIGNAL wire_n0l0001l_dataout : STD_LOGIC; + SIGNAL wire_n0l0001O_dataout : STD_LOGIC; + SIGNAL wire_n0l000i_dataout : STD_LOGIC; + SIGNAL wire_n0l000ii_dataout : STD_LOGIC; + SIGNAL wire_n0l000il_dataout : STD_LOGIC; + SIGNAL wire_n0l000iO_dataout : STD_LOGIC; + SIGNAL wire_n0l000l_dataout : STD_LOGIC; + SIGNAL wire_n0l000li_dataout : STD_LOGIC; + SIGNAL wire_n0l000ll_dataout : STD_LOGIC; + SIGNAL wire_n0l000lO_dataout : STD_LOGIC; + SIGNAL wire_n0l000O_dataout : STD_LOGIC; + SIGNAL wire_n0l000Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l000Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l000OO_dataout : STD_LOGIC; + SIGNAL wire_n0l0010i_dataout : STD_LOGIC; + SIGNAL wire_n0l0010l_dataout : STD_LOGIC; + SIGNAL wire_n0l0010O_dataout : STD_LOGIC; + SIGNAL wire_n0l0011i_dataout : STD_LOGIC; + SIGNAL wire_n0l0011l_dataout : STD_LOGIC; + SIGNAL wire_n0l0011O_dataout : STD_LOGIC; + SIGNAL wire_n0l001i_dataout : STD_LOGIC; + SIGNAL wire_n0l001ii_dataout : STD_LOGIC; + SIGNAL wire_n0l001il_dataout : STD_LOGIC; + SIGNAL wire_n0l001iO_dataout : STD_LOGIC; + SIGNAL wire_n0l001l_dataout : STD_LOGIC; + SIGNAL wire_n0l001li_dataout : STD_LOGIC; + SIGNAL wire_n0l001ll_dataout : STD_LOGIC; + SIGNAL wire_n0l001lO_dataout : STD_LOGIC; + SIGNAL wire_n0l001O_dataout : STD_LOGIC; + SIGNAL wire_n0l001Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l001Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l001OO_dataout : STD_LOGIC; + SIGNAL wire_n0l00i0l_dataout : STD_LOGIC; + SIGNAL wire_n0l00i0O_dataout : STD_LOGIC; + SIGNAL wire_n0l00ii_dataout : STD_LOGIC; + SIGNAL wire_n0l00il_dataout : STD_LOGIC; + SIGNAL wire_n0l00ili_dataout : STD_LOGIC; + SIGNAL wire_n0l00ill_dataout : STD_LOGIC; + SIGNAL wire_n0l00ilO_dataout : STD_LOGIC; + SIGNAL wire_n0l00iO_dataout : STD_LOGIC; + SIGNAL wire_n0l00iOi_dataout : STD_LOGIC; + SIGNAL wire_n0l00iOl_dataout : STD_LOGIC; + SIGNAL wire_n0l00l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l00l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l00l1O_dataout : STD_LOGIC; + SIGNAL wire_n0l00li_dataout : STD_LOGIC; + SIGNAL wire_n0l00ll_dataout : STD_LOGIC; + SIGNAL wire_n0l00lO_dataout : STD_LOGIC; + SIGNAL wire_n0l00lOi_dataout : STD_LOGIC; + SIGNAL wire_n0l00lOl_dataout : STD_LOGIC; + SIGNAL wire_n0l00O0i_dataout : STD_LOGIC; + SIGNAL wire_n0l00O0l_dataout : STD_LOGIC; + SIGNAL wire_n0l00O0O_dataout : STD_LOGIC; + SIGNAL wire_n0l00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l00Oii_dataout : STD_LOGIC; + SIGNAL wire_n0l00Oil_dataout : STD_LOGIC; + SIGNAL wire_n0l00OiO_dataout : STD_LOGIC; + SIGNAL wire_n0l00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l00Oli_dataout : STD_LOGIC; + SIGNAL wire_n0l00Oll_dataout : STD_LOGIC; + SIGNAL wire_n0l00OlO_dataout : STD_LOGIC; + SIGNAL wire_n0l00OO_dataout : STD_LOGIC; + SIGNAL wire_n0l00OOi_dataout : STD_LOGIC; + SIGNAL wire_n0l00OOl_dataout : STD_LOGIC; + SIGNAL wire_n0l00OOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0100i_dataout : STD_LOGIC; + SIGNAL wire_n0l0100l_dataout : STD_LOGIC; + SIGNAL wire_n0l0100O_dataout : STD_LOGIC; + SIGNAL wire_n0l0101i_dataout : STD_LOGIC; + SIGNAL wire_n0l0101l_dataout : STD_LOGIC; + SIGNAL wire_n0l0101O_dataout : STD_LOGIC; + SIGNAL wire_n0l010i_dataout : STD_LOGIC; + SIGNAL wire_n0l010ii_dataout : STD_LOGIC; + SIGNAL wire_n0l010il_dataout : STD_LOGIC; + SIGNAL wire_n0l010iO_dataout : STD_LOGIC; + SIGNAL wire_n0l010l_dataout : STD_LOGIC; + SIGNAL wire_n0l010li_dataout : STD_LOGIC; + SIGNAL wire_n0l010O_dataout : STD_LOGIC; + SIGNAL wire_n0l0110l_dataout : STD_LOGIC; + SIGNAL wire_n0l0110O_dataout : STD_LOGIC; + SIGNAL wire_n0l011i_dataout : STD_LOGIC; + SIGNAL wire_n0l011ii_dataout : STD_LOGIC; + SIGNAL wire_n0l011il_dataout : STD_LOGIC; + SIGNAL wire_n0l011iO_dataout : STD_LOGIC; + SIGNAL wire_n0l011l_dataout : STD_LOGIC; + SIGNAL wire_n0l011li_dataout : STD_LOGIC; + SIGNAL wire_n0l011ll_dataout : STD_LOGIC; + SIGNAL wire_n0l011lO_dataout : STD_LOGIC; + SIGNAL wire_n0l011O_dataout : STD_LOGIC; + SIGNAL wire_n0l011Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l011Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l011OO_dataout : STD_LOGIC; + SIGNAL wire_n0l01i0i_dataout : STD_LOGIC; + SIGNAL wire_n0l01i1i_dataout : STD_LOGIC; + SIGNAL wire_n0l01i1i_w_lg_w_lg_w_lg_dataout13505w13511w13512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l01i1i_w_lg_w_lg_dataout13505w13511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l01i1i_w_lg_dataout13518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l01i1i_w_lg_dataout13505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0l01i1l_dataout : STD_LOGIC; + SIGNAL wire_n0l01ii_dataout : STD_LOGIC; + SIGNAL wire_n0l01iii_dataout : STD_LOGIC; + SIGNAL wire_n0l01il_dataout : STD_LOGIC; + SIGNAL wire_n0l01iO_dataout : STD_LOGIC; + SIGNAL wire_n0l01li_dataout : STD_LOGIC; + SIGNAL wire_n0l01ll_dataout : STD_LOGIC; + SIGNAL wire_n0l01lO_dataout : STD_LOGIC; + SIGNAL wire_n0l01O0l_dataout : STD_LOGIC; + SIGNAL wire_n0l01O0O_dataout : STD_LOGIC; + SIGNAL wire_n0l01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l01Oii_dataout : STD_LOGIC; + SIGNAL wire_n0l01Oil_dataout : STD_LOGIC; + SIGNAL wire_n0l01OiO_dataout : STD_LOGIC; + SIGNAL wire_n0l01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l01Oli_dataout : STD_LOGIC; + SIGNAL wire_n0l01Oll_dataout : STD_LOGIC; + SIGNAL wire_n0l01OlO_dataout : STD_LOGIC; + SIGNAL wire_n0l01OO_dataout : STD_LOGIC; + SIGNAL wire_n0l01OOi_dataout : STD_LOGIC; + SIGNAL wire_n0l01OOl_dataout : STD_LOGIC; + SIGNAL wire_n0l01OOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i00i_dataout : STD_LOGIC; + SIGNAL wire_n0l0i00l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i00O_dataout : STD_LOGIC; + SIGNAL wire_n0l0i01i_dataout : STD_LOGIC; + SIGNAL wire_n0l0i01l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i01O_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0ii_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0il_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0li_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0ll_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0lO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l0i0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i10i_dataout : STD_LOGIC; + SIGNAL wire_n0l0i10l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i10O_dataout : STD_LOGIC; + SIGNAL wire_n0l0i11i_dataout : STD_LOGIC; + SIGNAL wire_n0l0i11l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i11O_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1ii_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1il_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1iO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1li_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1ll_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1lO_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l0i1OO_dataout : STD_LOGIC; + SIGNAL wire_n0l0ii0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0ii0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0ii0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0ii1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0ii1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0ii1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0iii_dataout : STD_LOGIC; + SIGNAL wire_n0l0iiii_dataout : STD_LOGIC; + SIGNAL wire_n0l0iiil_dataout : STD_LOGIC; + SIGNAL wire_n0l0iiiO_dataout : STD_LOGIC; + SIGNAL wire_n0l0iil_dataout : STD_LOGIC; + SIGNAL wire_n0l0iili_dataout : STD_LOGIC; + SIGNAL wire_n0l0iill_dataout : STD_LOGIC; + SIGNAL wire_n0l0iilO_dataout : STD_LOGIC; + SIGNAL wire_n0l0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0l0iiOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0iiOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0iiOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0il0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0il0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0il0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0il1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0il1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0il1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0ili_dataout : STD_LOGIC; + SIGNAL wire_n0l0ilii_dataout : STD_LOGIC; + SIGNAL wire_n0l0ilil_dataout : STD_LOGIC; + SIGNAL wire_n0l0iliO_dataout : STD_LOGIC; + SIGNAL wire_n0l0ill_dataout : STD_LOGIC; + SIGNAL wire_n0l0illi_dataout : STD_LOGIC; + SIGNAL wire_n0l0illl_dataout : STD_LOGIC; + SIGNAL wire_n0l0illO_dataout : STD_LOGIC; + SIGNAL wire_n0l0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0l0ilOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0ilOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0ilOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0iO0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0iO0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0iO0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0iO1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0iO1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0iO1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOii_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOil_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOiO_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOli_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOll_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOlO_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0iOOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0l00i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l00l_dataout : STD_LOGIC; + SIGNAL wire_n0l0l00O_dataout : STD_LOGIC; + SIGNAL wire_n0l0l01i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l01l_dataout : STD_LOGIC; + SIGNAL wire_n0l0l01O_dataout : STD_LOGIC; + SIGNAL wire_n0l0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l0l10i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l10l_dataout : STD_LOGIC; + SIGNAL wire_n0l0l10O_dataout : STD_LOGIC; + SIGNAL wire_n0l0l11i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l11l_dataout : STD_LOGIC; + SIGNAL wire_n0l0l11O_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1il_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1iO_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1li_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1ll_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1lO_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l0l1OO_dataout : STD_LOGIC; + SIGNAL wire_n0l0li0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0li0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0li0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0li1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0li1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0li1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0lii_dataout : STD_LOGIC; + SIGNAL wire_n0l0liii_dataout : STD_LOGIC; + SIGNAL wire_n0l0liil_dataout : STD_LOGIC; + SIGNAL wire_n0l0liiO_dataout : STD_LOGIC; + SIGNAL wire_n0l0lil_dataout : STD_LOGIC; + SIGNAL wire_n0l0lili_dataout : STD_LOGIC; + SIGNAL wire_n0l0lill_dataout : STD_LOGIC; + SIGNAL wire_n0l0lilO_dataout : STD_LOGIC; + SIGNAL wire_n0l0liO_dataout : STD_LOGIC; + SIGNAL wire_n0l0liOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0liOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0liOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0ll0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0ll1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0lli_dataout : STD_LOGIC; + SIGNAL wire_n0l0llii_dataout : STD_LOGIC; + SIGNAL wire_n0l0llil_dataout : STD_LOGIC; + SIGNAL wire_n0l0lliO_dataout : STD_LOGIC; + SIGNAL wire_n0l0lll_dataout : STD_LOGIC; + SIGNAL wire_n0l0llli_dataout : STD_LOGIC; + SIGNAL wire_n0l0llll_dataout : STD_LOGIC; + SIGNAL wire_n0l0lllO_dataout : STD_LOGIC; + SIGNAL wire_n0l0llO_dataout : STD_LOGIC; + SIGNAL wire_n0l0llOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0llOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0llOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0lO0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0lO0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0lO0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0lO1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0lO1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOii_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOil_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOiO_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOli_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOll_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOlO_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0lOOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0O00i_dataout : STD_LOGIC; + SIGNAL wire_n0l0O00l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O00O_dataout : STD_LOGIC; + SIGNAL wire_n0l0O01i_dataout : STD_LOGIC; + SIGNAL wire_n0l0O01l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O01O_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0ii_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0il_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0li_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0ll_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0lO_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l0O0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l0O10i_dataout : STD_LOGIC; + SIGNAL wire_n0l0O10l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O10O_dataout : STD_LOGIC; + SIGNAL wire_n0l0O11i_dataout : STD_LOGIC; + SIGNAL wire_n0l0O11l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O11O_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1ii_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1il_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1iO_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1li_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1ll_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1lO_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l0O1OO_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0l0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0l0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n0l0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0l0Olii_dataout : STD_LOGIC; + SIGNAL wire_n0l0Olil_dataout : STD_LOGIC; + SIGNAL wire_n0l0OliO_dataout : STD_LOGIC; + SIGNAL wire_n0l0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0l0Olli_dataout : STD_LOGIC; + SIGNAL wire_n0l0Olll_dataout : STD_LOGIC; + SIGNAL wire_n0l0OllO_dataout : STD_LOGIC; + SIGNAL wire_n0l0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0l0OlOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0OlOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0OlOO_dataout : STD_LOGIC; + SIGNAL wire_n0l0OO0i_dataout : STD_LOGIC; + SIGNAL wire_n0l0OO0l_dataout : STD_LOGIC; + SIGNAL wire_n0l0OO1i_dataout : STD_LOGIC; + SIGNAL wire_n0l0OO1l_dataout : STD_LOGIC; + SIGNAL wire_n0l0OO1O_dataout : STD_LOGIC; + SIGNAL wire_n0l0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0l0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0l0OOll_dataout : STD_LOGIC; + SIGNAL wire_n0l0OOlO_dataout : STD_LOGIC; + SIGNAL wire_n0l0OOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1000i_dataout : STD_LOGIC; + SIGNAL wire_n0l1000l_dataout : STD_LOGIC; + SIGNAL wire_n0l1000O_dataout : STD_LOGIC; + SIGNAL wire_n0l1001i_dataout : STD_LOGIC; + SIGNAL wire_n0l1001l_dataout : STD_LOGIC; + SIGNAL wire_n0l1001O_dataout : STD_LOGIC; + SIGNAL wire_n0l100i_dataout : STD_LOGIC; + SIGNAL wire_n0l100ii_dataout : STD_LOGIC; + SIGNAL wire_n0l100il_dataout : STD_LOGIC; + SIGNAL wire_n0l100iO_dataout : STD_LOGIC; + SIGNAL wire_n0l100l_dataout : STD_LOGIC; + SIGNAL wire_n0l100li_dataout : STD_LOGIC; + SIGNAL wire_n0l100ll_dataout : STD_LOGIC; + SIGNAL wire_n0l100lO_dataout : STD_LOGIC; + SIGNAL wire_n0l100O_dataout : STD_LOGIC; + SIGNAL wire_n0l100Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l100Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l100OO_dataout : STD_LOGIC; + SIGNAL wire_n0l1010i_dataout : STD_LOGIC; + SIGNAL wire_n0l1010l_dataout : STD_LOGIC; + SIGNAL wire_n0l1010O_dataout : STD_LOGIC; + SIGNAL wire_n0l1011i_dataout : STD_LOGIC; + SIGNAL wire_n0l1011l_dataout : STD_LOGIC; + SIGNAL wire_n0l1011O_dataout : STD_LOGIC; + SIGNAL wire_n0l101i_dataout : STD_LOGIC; + SIGNAL wire_n0l101ii_dataout : STD_LOGIC; + SIGNAL wire_n0l101il_dataout : STD_LOGIC; + SIGNAL wire_n0l101iO_dataout : STD_LOGIC; + SIGNAL wire_n0l101l_dataout : STD_LOGIC; + SIGNAL wire_n0l101li_dataout : STD_LOGIC; + SIGNAL wire_n0l101ll_dataout : STD_LOGIC; + SIGNAL wire_n0l101lO_dataout : STD_LOGIC; + SIGNAL wire_n0l101O_dataout : STD_LOGIC; + SIGNAL wire_n0l101Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l101Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l101OO_dataout : STD_LOGIC; + SIGNAL wire_n0l10i0i_dataout : STD_LOGIC; + SIGNAL wire_n0l10i0l_dataout : STD_LOGIC; + SIGNAL wire_n0l10i0O_dataout : STD_LOGIC; + SIGNAL wire_n0l10i1i_dataout : STD_LOGIC; + SIGNAL wire_n0l10i1l_dataout : STD_LOGIC; + SIGNAL wire_n0l10i1O_dataout : STD_LOGIC; + SIGNAL wire_n0l10ii_dataout : STD_LOGIC; + SIGNAL wire_n0l10iii_dataout : STD_LOGIC; + SIGNAL wire_n0l10il_dataout : STD_LOGIC; + SIGNAL wire_n0l10iO_dataout : STD_LOGIC; + SIGNAL wire_n0l10li_dataout : STD_LOGIC; + SIGNAL wire_n0l10ll_dataout : STD_LOGIC; + SIGNAL wire_n0l10lO_dataout : STD_LOGIC; + SIGNAL wire_n0l10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l10OO_dataout : STD_LOGIC; + SIGNAL wire_n0l1100i_dataout : STD_LOGIC; + SIGNAL wire_n0l1100l_dataout : STD_LOGIC; + SIGNAL wire_n0l1100O_dataout : STD_LOGIC; + SIGNAL wire_n0l1101i_dataout : STD_LOGIC; + SIGNAL wire_n0l1101l_dataout : STD_LOGIC; + SIGNAL wire_n0l1101O_dataout : STD_LOGIC; + SIGNAL wire_n0l110ii_dataout : STD_LOGIC; + SIGNAL wire_n0l110il_dataout : STD_LOGIC; + SIGNAL wire_n0l110iO_dataout : STD_LOGIC; + SIGNAL wire_n0l110li_dataout : STD_LOGIC; + SIGNAL wire_n0l110ll_dataout : STD_LOGIC; + SIGNAL wire_n0l110lO_dataout : STD_LOGIC; + SIGNAL wire_n0l110Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l110Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l110OO_dataout : STD_LOGIC; + SIGNAL wire_n0l1110i_dataout : STD_LOGIC; + SIGNAL wire_n0l1110l_dataout : STD_LOGIC; + SIGNAL wire_n0l1110O_dataout : STD_LOGIC; + SIGNAL wire_n0l1111i_dataout : STD_LOGIC; + SIGNAL wire_n0l1111l_dataout : STD_LOGIC; + SIGNAL wire_n0l1111O_dataout : STD_LOGIC; + SIGNAL wire_n0l111ii_dataout : STD_LOGIC; + SIGNAL wire_n0l111il_dataout : STD_LOGIC; + SIGNAL wire_n0l111iO_dataout : STD_LOGIC; + SIGNAL wire_n0l111li_dataout : STD_LOGIC; + SIGNAL wire_n0l111ll_dataout : STD_LOGIC; + SIGNAL wire_n0l111lO_dataout : STD_LOGIC; + SIGNAL wire_n0l111Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l111Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l111OO_dataout : STD_LOGIC; + SIGNAL wire_n0l11i0i_dataout : STD_LOGIC; + SIGNAL wire_n0l11i1i_dataout : STD_LOGIC; + SIGNAL wire_n0l11i1l_dataout : STD_LOGIC; + SIGNAL wire_n0l11i1O_dataout : STD_LOGIC; + SIGNAL wire_n0l11ill_dataout : STD_LOGIC; + SIGNAL wire_n0l11ilO_dataout : STD_LOGIC; + SIGNAL wire_n0l11iOi_dataout : STD_LOGIC; + SIGNAL wire_n0l11iOl_dataout : STD_LOGIC; + SIGNAL wire_n0l11iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l11l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l11l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l11l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l11l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l11l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l11l1O_dataout : STD_LOGIC; + SIGNAL wire_n0l11lii_dataout : STD_LOGIC; + SIGNAL wire_n0l11lil_dataout : STD_LOGIC; + SIGNAL wire_n0l11liO_dataout : STD_LOGIC; + SIGNAL wire_n0l11lli_dataout : STD_LOGIC; + SIGNAL wire_n0l11lll_dataout : STD_LOGIC; + SIGNAL wire_n0l11llO_dataout : STD_LOGIC; + SIGNAL wire_n0l11lOi_dataout : STD_LOGIC; + SIGNAL wire_n0l11lOl_dataout : STD_LOGIC; + SIGNAL wire_n0l11lOO_dataout : STD_LOGIC; + SIGNAL wire_n0l11O0i_dataout : STD_LOGIC; + SIGNAL wire_n0l11O0l_dataout : STD_LOGIC; + SIGNAL wire_n0l11O0O_dataout : STD_LOGIC; + SIGNAL wire_n0l11O1i_dataout : STD_LOGIC; + SIGNAL wire_n0l11O1l_dataout : STD_LOGIC; + SIGNAL wire_n0l11O1O_dataout : STD_LOGIC; + SIGNAL wire_n0l11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l11Oii_dataout : STD_LOGIC; + SIGNAL wire_n0l11Oil_dataout : STD_LOGIC; + SIGNAL wire_n0l11OiO_dataout : STD_LOGIC; + SIGNAL wire_n0l11Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l11Oli_dataout : STD_LOGIC; + SIGNAL wire_n0l11Oll_dataout : STD_LOGIC; + SIGNAL wire_n0l11OlO_dataout : STD_LOGIC; + SIGNAL wire_n0l11OO_dataout : STD_LOGIC; + SIGNAL wire_n0l11OOi_dataout : STD_LOGIC; + SIGNAL wire_n0l11OOl_dataout : STD_LOGIC; + SIGNAL wire_n0l11OOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0ii_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0il_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0li_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0ll_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0lO_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l1i0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1ii1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1iii_dataout : STD_LOGIC; + SIGNAL wire_n0l1iiii_dataout : STD_LOGIC; + SIGNAL wire_n0l1iiil_dataout : STD_LOGIC; + SIGNAL wire_n0l1iiiO_dataout : STD_LOGIC; + SIGNAL wire_n0l1iil_dataout : STD_LOGIC; + SIGNAL wire_n0l1iili_dataout : STD_LOGIC; + SIGNAL wire_n0l1iill_dataout : STD_LOGIC; + SIGNAL wire_n0l1iilO_dataout : STD_LOGIC; + SIGNAL wire_n0l1iiO_dataout : STD_LOGIC; + SIGNAL wire_n0l1iiOi_dataout : STD_LOGIC; + SIGNAL wire_n0l1iiOl_dataout : STD_LOGIC; + SIGNAL wire_n0l1iiOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1il0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1il0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1il0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1il1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1il1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1il1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1ili_dataout : STD_LOGIC; + SIGNAL wire_n0l1ilii_dataout : STD_LOGIC; + SIGNAL wire_n0l1ilil_dataout : STD_LOGIC; + SIGNAL wire_n0l1iliO_dataout : STD_LOGIC; + SIGNAL wire_n0l1ill_dataout : STD_LOGIC; + SIGNAL wire_n0l1illi_dataout : STD_LOGIC; + SIGNAL wire_n0l1illl_dataout : STD_LOGIC; + SIGNAL wire_n0l1illO_dataout : STD_LOGIC; + SIGNAL wire_n0l1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0l1ilOi_dataout : STD_LOGIC; + SIGNAL wire_n0l1ilOl_dataout : STD_LOGIC; + SIGNAL wire_n0l1ilOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1iO0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1iO1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1iO1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1iO1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0l1iOl_dataout : STD_LOGIC; + SIGNAL wire_n0l1iOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0il_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0lO_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l1l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l1l10i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l10l_dataout : STD_LOGIC; + SIGNAL wire_n0l1l10O_dataout : STD_LOGIC; + SIGNAL wire_n0l1l11O_dataout : STD_LOGIC; + SIGNAL wire_n0l1l1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0l1l1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1li0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1li0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1li0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1li1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1li1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1li1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1lii_dataout : STD_LOGIC; + SIGNAL wire_n0l1liii_dataout : STD_LOGIC; + SIGNAL wire_n0l1liil_dataout : STD_LOGIC; + SIGNAL wire_n0l1liiO_dataout : STD_LOGIC; + SIGNAL wire_n0l1lil_dataout : STD_LOGIC; + SIGNAL wire_n0l1lili_dataout : STD_LOGIC; + SIGNAL wire_n0l1lill_dataout : STD_LOGIC; + SIGNAL wire_n0l1lilO_dataout : STD_LOGIC; + SIGNAL wire_n0l1liO_dataout : STD_LOGIC; + SIGNAL wire_n0l1liOi_dataout : STD_LOGIC; + SIGNAL wire_n0l1liOl_dataout : STD_LOGIC; + SIGNAL wire_n0l1liOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1ll0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1ll1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1lli_dataout : STD_LOGIC; + SIGNAL wire_n0l1llii_dataout : STD_LOGIC; + SIGNAL wire_n0l1llil_dataout : STD_LOGIC; + SIGNAL wire_n0l1lliO_dataout : STD_LOGIC; + SIGNAL wire_n0l1lll_dataout : STD_LOGIC; + SIGNAL wire_n0l1llli_dataout : STD_LOGIC; + SIGNAL wire_n0l1llll_dataout : STD_LOGIC; + SIGNAL wire_n0l1lllO_dataout : STD_LOGIC; + SIGNAL wire_n0l1llO_dataout : STD_LOGIC; + SIGNAL wire_n0l1llOi_dataout : STD_LOGIC; + SIGNAL wire_n0l1llOl_dataout : STD_LOGIC; + SIGNAL wire_n0l1llOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1lO0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1lO0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1lO0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1lO1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1lO1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1lO1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0l1lOii_dataout : STD_LOGIC; + SIGNAL wire_n0l1lOil_dataout : STD_LOGIC; + SIGNAL wire_n0l1lOiO_dataout : STD_LOGIC; + SIGNAL wire_n0l1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0l1lOli_dataout : STD_LOGIC; + SIGNAL wire_n0l1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0il_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0iO_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0li_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0ll_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0lO_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0l1O0OO_dataout : STD_LOGIC; + SIGNAL wire_n0l1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0l1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0l1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n0l1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n0l1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n0l1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n0l1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0l1Olii_dataout : STD_LOGIC; + SIGNAL wire_n0l1Olil_dataout : STD_LOGIC; + SIGNAL wire_n0l1OliO_dataout : STD_LOGIC; + SIGNAL wire_n0l1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0l1Olli_dataout : STD_LOGIC; + SIGNAL wire_n0l1Olll_dataout : STD_LOGIC; + SIGNAL wire_n0l1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0l1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0l1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0l1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0li00i_dataout : STD_LOGIC; + SIGNAL wire_n0li00l_dataout : STD_LOGIC; + SIGNAL wire_n0li00O_dataout : STD_LOGIC; + SIGNAL wire_n0li011i_dataout : STD_LOGIC; + SIGNAL wire_n0li011l_dataout : STD_LOGIC; + SIGNAL wire_n0li011O_dataout : STD_LOGIC; + SIGNAL wire_n0li01i_dataout : STD_LOGIC; + SIGNAL wire_n0li01l_dataout : STD_LOGIC; + SIGNAL wire_n0li01O_dataout : STD_LOGIC; + SIGNAL wire_n0li0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0li0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0li0ii_dataout : STD_LOGIC; + SIGNAL wire_n0li0iii_dataout : STD_LOGIC; + SIGNAL wire_n0li0il_dataout : STD_LOGIC; + SIGNAL wire_n0li0ili_dataout : STD_LOGIC; + SIGNAL wire_n0li0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0li0iO_dataout : STD_LOGIC; + SIGNAL wire_n0li0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0li0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0li0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0li0li_dataout : STD_LOGIC; + SIGNAL wire_n0li0ll_dataout : STD_LOGIC; + SIGNAL wire_n0li0lO_dataout : STD_LOGIC; + SIGNAL wire_n0li0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0li0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0li0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0li0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0li0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0li0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0li0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0li0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0li0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0li0OO_dataout : STD_LOGIC; + SIGNAL wire_n0li0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0li0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0li0OOO_dataout : STD_LOGIC; + SIGNAL wire_n0li100i_dataout : STD_LOGIC; + SIGNAL wire_n0li100l_dataout : STD_LOGIC; + SIGNAL wire_n0li100O_dataout : STD_LOGIC; + SIGNAL wire_n0li101l_dataout : STD_LOGIC; + SIGNAL wire_n0li101O_dataout : STD_LOGIC; + SIGNAL wire_n0li10i_dataout : STD_LOGIC; + SIGNAL wire_n0li10ii_dataout : STD_LOGIC; + SIGNAL wire_n0li10il_dataout : STD_LOGIC; + SIGNAL wire_n0li10iO_dataout : STD_LOGIC; + SIGNAL wire_n0li10l_dataout : STD_LOGIC; + SIGNAL wire_n0li10li_dataout : STD_LOGIC; + SIGNAL wire_n0li10ll_dataout : STD_LOGIC; + SIGNAL wire_n0li10lO_dataout : STD_LOGIC; + SIGNAL wire_n0li10O_dataout : STD_LOGIC; + SIGNAL wire_n0li10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0li10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0li10OO_dataout : STD_LOGIC; + SIGNAL wire_n0li11i_dataout : STD_LOGIC; + SIGNAL wire_n0li11l_dataout : STD_LOGIC; + SIGNAL wire_n0li11O_dataout : STD_LOGIC; + SIGNAL wire_n0li1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0li1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0li1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0li1ii_dataout : STD_LOGIC; + SIGNAL wire_n0li1il_dataout : STD_LOGIC; + SIGNAL wire_n0li1ili_dataout : STD_LOGIC; + SIGNAL wire_n0li1ill_dataout : STD_LOGIC; + SIGNAL wire_n0li1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0li1iO_dataout : STD_LOGIC; + SIGNAL wire_n0li1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0li1iOl_dataout : STD_LOGIC; + SIGNAL wire_n0li1iOO_dataout : STD_LOGIC; + SIGNAL wire_n0li1l0i_dataout : STD_LOGIC; + SIGNAL wire_n0li1l0l_dataout : STD_LOGIC; + SIGNAL wire_n0li1l0O_dataout : STD_LOGIC; + SIGNAL wire_n0li1l1i_dataout : STD_LOGIC; + SIGNAL wire_n0li1l1l_dataout : STD_LOGIC; + SIGNAL wire_n0li1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0li1li_dataout : STD_LOGIC; + SIGNAL wire_n0li1lii_dataout : STD_LOGIC; + SIGNAL wire_n0li1lil_dataout : STD_LOGIC; + SIGNAL wire_n0li1liO_dataout : STD_LOGIC; + SIGNAL wire_n0li1ll_dataout : STD_LOGIC; + SIGNAL wire_n0li1lli_dataout : STD_LOGIC; + SIGNAL wire_n0li1lll_dataout : STD_LOGIC; + SIGNAL wire_n0li1llO_dataout : STD_LOGIC; + SIGNAL wire_n0li1lO_dataout : STD_LOGIC; + SIGNAL wire_n0li1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0li1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0li1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0li1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0li1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0li1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0li1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0li1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0li1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0li1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0li1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0li1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0li1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0li1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0li1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0li1OO_dataout : STD_LOGIC; + SIGNAL wire_n0li1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0li1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0li1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0lii00i_dataout : STD_LOGIC; + SIGNAL wire_n0lii00l_dataout : STD_LOGIC; + SIGNAL wire_n0lii00O_dataout : STD_LOGIC; + SIGNAL wire_n0lii01i_dataout : STD_LOGIC; + SIGNAL wire_n0lii01l_dataout : STD_LOGIC; + SIGNAL wire_n0lii01O_dataout : STD_LOGIC; + SIGNAL wire_n0lii0i_dataout : STD_LOGIC; + SIGNAL wire_n0lii0ii_dataout : STD_LOGIC; + SIGNAL wire_n0lii0il_dataout : STD_LOGIC; + SIGNAL wire_n0lii0iO_dataout : STD_LOGIC; + SIGNAL wire_n0lii0l_dataout : STD_LOGIC; + SIGNAL wire_n0lii0li_dataout : STD_LOGIC; + SIGNAL wire_n0lii0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lii0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lii0O_dataout : STD_LOGIC; + SIGNAL wire_n0lii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lii0OO_dataout : STD_LOGIC; + SIGNAL wire_n0lii10i_dataout : STD_LOGIC; + SIGNAL wire_n0lii10l_dataout : STD_LOGIC; + SIGNAL wire_n0lii10O_dataout : STD_LOGIC; + SIGNAL wire_n0lii11i_dataout : STD_LOGIC; + SIGNAL wire_n0lii11l_dataout : STD_LOGIC; + SIGNAL wire_n0lii11O_dataout : STD_LOGIC; + SIGNAL wire_n0lii1i_dataout : STD_LOGIC; + SIGNAL wire_n0lii1ii_dataout : STD_LOGIC; + SIGNAL wire_n0lii1il_dataout : STD_LOGIC; + SIGNAL wire_n0lii1iO_dataout : STD_LOGIC; + SIGNAL wire_n0lii1l_dataout : STD_LOGIC; + SIGNAL wire_n0lii1li_dataout : STD_LOGIC; + SIGNAL wire_n0lii1ll_dataout : STD_LOGIC; + SIGNAL wire_n0lii1lO_dataout : STD_LOGIC; + SIGNAL wire_n0lii1O_dataout : STD_LOGIC; + SIGNAL wire_n0lii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lii1OO_dataout : STD_LOGIC; + SIGNAL wire_n0liii0i_dataout : STD_LOGIC; + SIGNAL wire_n0liii0l_dataout : STD_LOGIC; + SIGNAL wire_n0liii0O_dataout : STD_LOGIC; + SIGNAL wire_n0liii1i_dataout : STD_LOGIC; + SIGNAL wire_n0liii1l_dataout : STD_LOGIC; + SIGNAL wire_n0liii1O_dataout : STD_LOGIC; + SIGNAL wire_n0liiii_dataout : STD_LOGIC; + SIGNAL wire_n0liiiii_dataout : STD_LOGIC; + SIGNAL wire_n0liiiil_dataout : STD_LOGIC; + SIGNAL wire_n0liiil_dataout : STD_LOGIC; + SIGNAL wire_n0liiili_dataout : STD_LOGIC; + SIGNAL wire_n0liiill_dataout : STD_LOGIC; + SIGNAL wire_n0liiilO_dataout : STD_LOGIC; + SIGNAL wire_n0liiiO_dataout : STD_LOGIC; + SIGNAL wire_n0liili_dataout : STD_LOGIC; + SIGNAL wire_n0liill_dataout : STD_LOGIC; + SIGNAL wire_n0liilO_dataout : STD_LOGIC; + SIGNAL wire_n0liiOi_dataout : STD_LOGIC; + SIGNAL wire_n0liiOl_dataout : STD_LOGIC; + SIGNAL wire_n0liiOll_dataout : STD_LOGIC; + SIGNAL wire_n0liiOll_w_lg_dataout13107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0liiOO_dataout : STD_LOGIC; + SIGNAL wire_n0liiOOl_dataout : STD_LOGIC; + SIGNAL wire_n0liiOOl_w_lg_dataout13105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lil0i_dataout : STD_LOGIC; + SIGNAL wire_n0lil0l_dataout : STD_LOGIC; + SIGNAL wire_n0lil0O_dataout : STD_LOGIC; + SIGNAL wire_n0lil0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lil0OO_dataout : STD_LOGIC; + SIGNAL wire_n0lil10i_dataout : STD_LOGIC; + SIGNAL wire_n0lil10i_w_lg_dataout13101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lil10O_dataout : STD_LOGIC; + SIGNAL wire_n0lil10O_w_lg_dataout13099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lil11i_dataout : STD_LOGIC; + SIGNAL wire_n0lil11i_w_lg_dataout13103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lil1i_dataout : STD_LOGIC; + SIGNAL wire_n0lil1il_dataout : STD_LOGIC; + SIGNAL wire_n0lil1il_w_lg_dataout13097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lil1l_dataout : STD_LOGIC; + SIGNAL wire_n0lil1li_dataout : STD_LOGIC; + SIGNAL wire_n0lil1li_w_lg_dataout13095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lil1lO_dataout : STD_LOGIC; + SIGNAL wire_n0lil1lO_w_lg_dataout13093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lil1O_dataout : STD_LOGIC; + SIGNAL wire_n0lili0i_dataout : STD_LOGIC; + SIGNAL wire_n0lili0l_dataout : STD_LOGIC; + SIGNAL wire_n0lili0O_dataout : STD_LOGIC; + SIGNAL wire_n0lili1i_dataout : STD_LOGIC; + SIGNAL wire_n0lili1l_dataout : STD_LOGIC; + SIGNAL wire_n0lili1O_dataout : STD_LOGIC; + SIGNAL wire_n0lilii_dataout : STD_LOGIC; + SIGNAL wire_n0liliii_dataout : STD_LOGIC; + SIGNAL wire_n0liliil_dataout : STD_LOGIC; + SIGNAL wire_n0liliiO_dataout : STD_LOGIC; + SIGNAL wire_n0lilil_dataout : STD_LOGIC; + SIGNAL wire_n0lilili_dataout : STD_LOGIC; + SIGNAL wire_n0lilill_dataout : STD_LOGIC; + SIGNAL wire_n0lililO_dataout : STD_LOGIC; + SIGNAL wire_n0liliO_dataout : STD_LOGIC; + SIGNAL wire_n0liliOi_dataout : STD_LOGIC; + SIGNAL wire_n0liliOl_dataout : STD_LOGIC; + SIGNAL wire_n0liliOO_dataout : STD_LOGIC; + SIGNAL wire_n0lill0i_dataout : STD_LOGIC; + SIGNAL wire_n0lill0l_dataout : STD_LOGIC; + SIGNAL wire_n0lill0O_dataout : STD_LOGIC; + SIGNAL wire_n0lill1i_dataout : STD_LOGIC; + SIGNAL wire_n0lill1l_dataout : STD_LOGIC; + SIGNAL wire_n0lill1O_dataout : STD_LOGIC; + SIGNAL wire_n0lilli_dataout : STD_LOGIC; + SIGNAL wire_n0lillii_dataout : STD_LOGIC; + SIGNAL wire_n0lillil_dataout : STD_LOGIC; + SIGNAL wire_n0lilliO_dataout : STD_LOGIC; + SIGNAL wire_n0lilll_dataout : STD_LOGIC; + SIGNAL wire_n0lillli_dataout : STD_LOGIC; + SIGNAL wire_n0lillll_dataout : STD_LOGIC; + SIGNAL wire_n0lilllO_dataout : STD_LOGIC; + SIGNAL wire_n0lillO_dataout : STD_LOGIC; + SIGNAL wire_n0lillOi_dataout : STD_LOGIC; + SIGNAL wire_n0lillOl_dataout : STD_LOGIC; + SIGNAL wire_n0lillOO_dataout : STD_LOGIC; + SIGNAL wire_n0lilO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lilO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lilO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lilO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lilO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lilO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lilOi_dataout : STD_LOGIC; + SIGNAL wire_n0lilOii_dataout : STD_LOGIC; + SIGNAL wire_n0lilOil_dataout : STD_LOGIC; + SIGNAL wire_n0lilOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lilOl_dataout : STD_LOGIC; + SIGNAL wire_n0lilOli_dataout : STD_LOGIC; + SIGNAL wire_n0lilOll_dataout : STD_LOGIC; + SIGNAL wire_n0lilOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lilOO_dataout : STD_LOGIC; + SIGNAL wire_n0lilOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lilOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lilOOO_dataout : STD_LOGIC; + SIGNAL wire_n0liO0i_dataout : STD_LOGIC; + SIGNAL wire_n0liO0l_dataout : STD_LOGIC; + SIGNAL wire_n0liO0O_dataout : STD_LOGIC; + SIGNAL wire_n0liO11i_dataout : STD_LOGIC; + SIGNAL wire_n0liO1i_dataout : STD_LOGIC; + SIGNAL wire_n0liO1l_dataout : STD_LOGIC; + SIGNAL wire_n0liO1O_dataout : STD_LOGIC; + SIGNAL wire_n0liOii_dataout : STD_LOGIC; + SIGNAL wire_n0liOil_dataout : STD_LOGIC; + SIGNAL wire_n0liOiO_dataout : STD_LOGIC; + SIGNAL wire_n0liOli_dataout : STD_LOGIC; + SIGNAL wire_n0liOll_dataout : STD_LOGIC; + SIGNAL wire_n0liOlO_dataout : STD_LOGIC; + SIGNAL wire_n0liOOi_dataout : STD_LOGIC; + SIGNAL wire_n0liOOl_dataout : STD_LOGIC; + SIGNAL wire_n0liOOO_dataout : STD_LOGIC; + SIGNAL wire_n0ll000i_dataout : STD_LOGIC; + SIGNAL wire_n0ll000l_dataout : STD_LOGIC; + SIGNAL wire_n0ll000O_dataout : STD_LOGIC; + SIGNAL wire_n0ll001i_dataout : STD_LOGIC; + SIGNAL wire_n0ll001l_dataout : STD_LOGIC; + SIGNAL wire_n0ll001O_dataout : STD_LOGIC; + SIGNAL wire_n0ll00i_dataout : STD_LOGIC; + SIGNAL wire_n0ll00ii_dataout : STD_LOGIC; + SIGNAL wire_n0ll00il_dataout : STD_LOGIC; + SIGNAL wire_n0ll00iO_dataout : STD_LOGIC; + SIGNAL wire_n0ll00l_dataout : STD_LOGIC; + SIGNAL wire_n0ll00li_dataout : STD_LOGIC; + SIGNAL wire_n0ll00ll_dataout : STD_LOGIC; + SIGNAL wire_n0ll00lO_dataout : STD_LOGIC; + SIGNAL wire_n0ll00O_dataout : STD_LOGIC; + SIGNAL wire_n0ll00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ll00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ll00OO_dataout : STD_LOGIC; + SIGNAL wire_n0ll010i_dataout : STD_LOGIC; + SIGNAL wire_n0ll011i_dataout : STD_LOGIC; + SIGNAL wire_n0ll011l_dataout : STD_LOGIC; + SIGNAL wire_n0ll011O_dataout : STD_LOGIC; + SIGNAL wire_n0ll01i_dataout : STD_LOGIC; + SIGNAL wire_n0ll01l_dataout : STD_LOGIC; + SIGNAL wire_n0ll01O_dataout : STD_LOGIC; + SIGNAL wire_n0ll01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ll01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ll01OO_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0ll0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0ll0ii_dataout : STD_LOGIC; + SIGNAL wire_n0ll0iii_dataout : STD_LOGIC; + SIGNAL wire_n0ll0il_dataout : STD_LOGIC; + SIGNAL wire_n0ll0iO_dataout : STD_LOGIC; + SIGNAL wire_n0ll0li_dataout : STD_LOGIC; + SIGNAL wire_n0ll0ll_dataout : STD_LOGIC; + SIGNAL wire_n0ll0lO_dataout : STD_LOGIC; + SIGNAL wire_n0ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ll0OO_dataout : STD_LOGIC; + SIGNAL wire_n0ll100l_dataout : STD_LOGIC; + SIGNAL wire_n0ll100O_dataout : STD_LOGIC; + SIGNAL wire_n0ll10i_dataout : STD_LOGIC; + SIGNAL wire_n0ll10ii_dataout : STD_LOGIC; + SIGNAL wire_n0ll10il_dataout : STD_LOGIC; + SIGNAL wire_n0ll10iO_dataout : STD_LOGIC; + SIGNAL wire_n0ll10l_dataout : STD_LOGIC; + SIGNAL wire_n0ll10li_dataout : STD_LOGIC; + SIGNAL wire_n0ll10ll_dataout : STD_LOGIC; + SIGNAL wire_n0ll10lO_dataout : STD_LOGIC; + SIGNAL wire_n0ll10O_dataout : STD_LOGIC; + SIGNAL wire_n0ll10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ll11i_dataout : STD_LOGIC; + SIGNAL wire_n0ll11l_dataout : STD_LOGIC; + SIGNAL wire_n0ll11O_dataout : STD_LOGIC; + SIGNAL wire_n0ll1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0ll1i0l_dataout : STD_LOGIC; + SIGNAL wire_n0ll1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0ll1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0ll1ii_dataout : STD_LOGIC; + SIGNAL wire_n0ll1iii_dataout : STD_LOGIC; + SIGNAL wire_n0ll1iil_dataout : STD_LOGIC; + SIGNAL wire_n0ll1il_dataout : STD_LOGIC; + SIGNAL wire_n0ll1ill_dataout : STD_LOGIC; + SIGNAL wire_n0ll1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1iO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0ll1li_dataout : STD_LOGIC; + SIGNAL wire_n0ll1lil_dataout : STD_LOGIC; + SIGNAL wire_n0ll1liO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1ll_dataout : STD_LOGIC; + SIGNAL wire_n0ll1lli_dataout : STD_LOGIC; + SIGNAL wire_n0ll1lll_dataout : STD_LOGIC; + SIGNAL wire_n0ll1llO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1lO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0ll1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0ll1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0ll1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0ll1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0ll1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1OO_dataout : STD_LOGIC; + SIGNAL wire_n0ll1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0ll1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0lli00i_dataout : STD_LOGIC; + SIGNAL wire_n0lli00l_dataout : STD_LOGIC; + SIGNAL wire_n0lli00O_dataout : STD_LOGIC; + SIGNAL wire_n0lli01i_dataout : STD_LOGIC; + SIGNAL wire_n0lli01l_dataout : STD_LOGIC; + SIGNAL wire_n0lli01O_dataout : STD_LOGIC; + SIGNAL wire_n0lli0i_dataout : STD_LOGIC; + SIGNAL wire_n0lli0ii_dataout : STD_LOGIC; + SIGNAL wire_n0lli0il_dataout : STD_LOGIC; + SIGNAL wire_n0lli0iO_dataout : STD_LOGIC; + SIGNAL wire_n0lli0l_dataout : STD_LOGIC; + SIGNAL wire_n0lli0li_dataout : STD_LOGIC; + SIGNAL wire_n0lli0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lli0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lli0O_dataout : STD_LOGIC; + SIGNAL wire_n0lli0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lli0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lli0OO_dataout : STD_LOGIC; + SIGNAL wire_n0lli1i_dataout : STD_LOGIC; + SIGNAL wire_n0lli1l_dataout : STD_LOGIC; + SIGNAL wire_n0lli1O_dataout : STD_LOGIC; + SIGNAL wire_n0lli1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lli1OO_dataout : STD_LOGIC; + SIGNAL wire_n0llii0i_dataout : STD_LOGIC; + SIGNAL wire_n0llii0l_dataout : STD_LOGIC; + SIGNAL wire_n0llii0O_dataout : STD_LOGIC; + SIGNAL wire_n0llii1i_dataout : STD_LOGIC; + SIGNAL wire_n0llii1l_dataout : STD_LOGIC; + SIGNAL wire_n0llii1O_dataout : STD_LOGIC; + SIGNAL wire_n0lliii_dataout : STD_LOGIC; + SIGNAL wire_n0lliiii_dataout : STD_LOGIC; + SIGNAL wire_n0lliiil_dataout : STD_LOGIC; + SIGNAL wire_n0lliiiO_dataout : STD_LOGIC; + SIGNAL wire_n0lliil_dataout : STD_LOGIC; + SIGNAL wire_n0lliili_dataout : STD_LOGIC; + SIGNAL wire_n0lliill_dataout : STD_LOGIC; + SIGNAL wire_n0lliilO_dataout : STD_LOGIC; + SIGNAL wire_n0lliiO_dataout : STD_LOGIC; + SIGNAL wire_n0lliiOi_dataout : STD_LOGIC; + SIGNAL wire_n0lliiOl_dataout : STD_LOGIC; + SIGNAL wire_n0lliiOO_dataout : STD_LOGIC; + SIGNAL wire_n0llil0i_dataout : STD_LOGIC; + SIGNAL wire_n0llil0l_dataout : STD_LOGIC; + SIGNAL wire_n0llil0O_dataout : STD_LOGIC; + SIGNAL wire_n0llil1i_dataout : STD_LOGIC; + SIGNAL wire_n0llil1l_dataout : STD_LOGIC; + SIGNAL wire_n0llil1O_dataout : STD_LOGIC; + SIGNAL wire_n0llili_dataout : STD_LOGIC; + SIGNAL wire_n0llilii_dataout : STD_LOGIC; + SIGNAL wire_n0llilil_dataout : STD_LOGIC; + SIGNAL wire_n0lliliO_dataout : STD_LOGIC; + SIGNAL wire_n0llill_dataout : STD_LOGIC; + SIGNAL wire_n0llilli_dataout : STD_LOGIC; + SIGNAL wire_n0llilll_dataout : STD_LOGIC; + SIGNAL wire_n0llillO_dataout : STD_LOGIC; + SIGNAL wire_n0llilO_dataout : STD_LOGIC; + SIGNAL wire_n0llilOi_dataout : STD_LOGIC; + SIGNAL wire_n0llilOl_dataout : STD_LOGIC; + SIGNAL wire_n0llilOO_dataout : STD_LOGIC; + SIGNAL wire_n0lliO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lliO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lliO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lliO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lliO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lliO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lliOi_dataout : STD_LOGIC; + SIGNAL wire_n0lliOii_dataout : STD_LOGIC; + SIGNAL wire_n0lliOil_dataout : STD_LOGIC; + SIGNAL wire_n0lliOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lliOl_dataout : STD_LOGIC; + SIGNAL wire_n0lliOli_dataout : STD_LOGIC; + SIGNAL wire_n0lliOll_dataout : STD_LOGIC; + SIGNAL wire_n0lliOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lliOO_dataout : STD_LOGIC; + SIGNAL wire_n0lliOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lliOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lliOOO_dataout : STD_LOGIC; + SIGNAL wire_n0lll00i_dataout : STD_LOGIC; + SIGNAL wire_n0lll00l_dataout : STD_LOGIC; + SIGNAL wire_n0lll00O_dataout : STD_LOGIC; + SIGNAL wire_n0lll01i_dataout : STD_LOGIC; + SIGNAL wire_n0lll01l_dataout : STD_LOGIC; + SIGNAL wire_n0lll01O_dataout : STD_LOGIC; + SIGNAL wire_n0lll0i_dataout : STD_LOGIC; + SIGNAL wire_n0lll0ii_dataout : STD_LOGIC; + SIGNAL wire_n0lll0il_dataout : STD_LOGIC; + SIGNAL wire_n0lll0iO_dataout : STD_LOGIC; + SIGNAL wire_n0lll0l_dataout : STD_LOGIC; + SIGNAL wire_n0lll0li_dataout : STD_LOGIC; + SIGNAL wire_n0lll0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lll0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lll0O_dataout : STD_LOGIC; + SIGNAL wire_n0lll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lll0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lll0OO_dataout : STD_LOGIC; + SIGNAL wire_n0lll10i_dataout : STD_LOGIC; + SIGNAL wire_n0lll10l_dataout : STD_LOGIC; + SIGNAL wire_n0lll10O_dataout : STD_LOGIC; + SIGNAL wire_n0lll11i_dataout : STD_LOGIC; + SIGNAL wire_n0lll11l_dataout : STD_LOGIC; + SIGNAL wire_n0lll11O_dataout : STD_LOGIC; + SIGNAL wire_n0lll1i_dataout : STD_LOGIC; + SIGNAL wire_n0lll1ii_dataout : STD_LOGIC; + SIGNAL wire_n0lll1il_dataout : STD_LOGIC; + SIGNAL wire_n0lll1l_dataout : STD_LOGIC; + SIGNAL wire_n0lll1O_dataout : STD_LOGIC; + SIGNAL wire_n0lll1OO_dataout : STD_LOGIC; + SIGNAL wire_n0llli0i_dataout : STD_LOGIC; + SIGNAL wire_n0llli0l_dataout : STD_LOGIC; + SIGNAL wire_n0llli0O_dataout : STD_LOGIC; + SIGNAL wire_n0llli1i_dataout : STD_LOGIC; + SIGNAL wire_n0llli1l_dataout : STD_LOGIC; + SIGNAL wire_n0llli1O_dataout : STD_LOGIC; + SIGNAL wire_n0lllii_dataout : STD_LOGIC; + SIGNAL wire_n0llliii_dataout : STD_LOGIC; + SIGNAL wire_n0llliil_dataout : STD_LOGIC; + SIGNAL wire_n0llliiO_dataout : STD_LOGIC; + SIGNAL wire_n0lllil_dataout : STD_LOGIC; + SIGNAL wire_n0lllili_dataout : STD_LOGIC; + SIGNAL wire_n0lllill_dataout : STD_LOGIC; + SIGNAL wire_n0lllilO_dataout : STD_LOGIC; + SIGNAL wire_n0llliO_dataout : STD_LOGIC; + SIGNAL wire_n0llliOi_dataout : STD_LOGIC; + SIGNAL wire_n0llliOl_dataout : STD_LOGIC; + SIGNAL wire_n0llliOO_dataout : STD_LOGIC; + SIGNAL wire_n0llll0i_dataout : STD_LOGIC; + SIGNAL wire_n0llll0l_dataout : STD_LOGIC; + SIGNAL wire_n0llll0O_dataout : STD_LOGIC; + SIGNAL wire_n0llll1i_dataout : STD_LOGIC; + SIGNAL wire_n0llll1l_dataout : STD_LOGIC; + SIGNAL wire_n0llll1O_dataout : STD_LOGIC; + SIGNAL wire_n0lllli_dataout : STD_LOGIC; + SIGNAL wire_n0llllii_dataout : STD_LOGIC; + SIGNAL wire_n0llllil_dataout : STD_LOGIC; + SIGNAL wire_n0lllliO_dataout : STD_LOGIC; + SIGNAL wire_n0lllll_dataout : STD_LOGIC; + SIGNAL wire_n0llllli_dataout : STD_LOGIC; + SIGNAL wire_n0llllll_dataout : STD_LOGIC; + SIGNAL wire_n0lllllO_dataout : STD_LOGIC; + SIGNAL wire_n0llllO_dataout : STD_LOGIC; + SIGNAL wire_n0llllOi_dataout : STD_LOGIC; + SIGNAL wire_n0llllOl_dataout : STD_LOGIC; + SIGNAL wire_n0llllOO_dataout : STD_LOGIC; + SIGNAL wire_n0lllO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lllO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lllO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lllO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lllO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lllO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lllOi_dataout : STD_LOGIC; + SIGNAL wire_n0lllOii_dataout : STD_LOGIC; + SIGNAL wire_n0lllOil_dataout : STD_LOGIC; + SIGNAL wire_n0lllOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lllOl_dataout : STD_LOGIC; + SIGNAL wire_n0lllOli_dataout : STD_LOGIC; + SIGNAL wire_n0lllOll_dataout : STD_LOGIC; + SIGNAL wire_n0lllOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lllOO_dataout : STD_LOGIC; + SIGNAL wire_n0lllOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lllOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lllOOO_dataout : STD_LOGIC; + SIGNAL wire_n0llO0i_dataout : STD_LOGIC; + SIGNAL wire_n0llO0l_dataout : STD_LOGIC; + SIGNAL wire_n0llO0O_dataout : STD_LOGIC; + SIGNAL wire_n0llO10i_dataout : STD_LOGIC; + SIGNAL wire_n0llO10l_dataout : STD_LOGIC; + SIGNAL wire_n0llO10O_dataout : STD_LOGIC; + SIGNAL wire_n0llO11i_dataout : STD_LOGIC; + SIGNAL wire_n0llO11l_dataout : STD_LOGIC; + SIGNAL wire_n0llO11O_dataout : STD_LOGIC; + SIGNAL wire_n0llO1i_dataout : STD_LOGIC; + SIGNAL wire_n0llO1ii_dataout : STD_LOGIC; + SIGNAL wire_n0llO1il_dataout : STD_LOGIC; + SIGNAL wire_n0llO1iO_dataout : STD_LOGIC; + SIGNAL wire_n0llO1l_dataout : STD_LOGIC; + SIGNAL wire_n0llO1li_dataout : STD_LOGIC; + SIGNAL wire_n0llO1ll_dataout : STD_LOGIC; + SIGNAL wire_n0llO1O_dataout : STD_LOGIC; + SIGNAL wire_n0llOii_dataout : STD_LOGIC; + SIGNAL wire_n0llOil_dataout : STD_LOGIC; + SIGNAL wire_n0llOiO_dataout : STD_LOGIC; + SIGNAL wire_n0llOli_dataout : STD_LOGIC; + SIGNAL wire_n0llOll_dataout : STD_LOGIC; + SIGNAL wire_n0llOlO_dataout : STD_LOGIC; + SIGNAL wire_n0llOOi_dataout : STD_LOGIC; + SIGNAL wire_n0llOOl_dataout : STD_LOGIC; + SIGNAL wire_n0llOOll_dataout : STD_LOGIC; + SIGNAL wire_n0llOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0llOOO_dataout : STD_LOGIC; + SIGNAL wire_n0llOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0llOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0llOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0lO000i_dataout : STD_LOGIC; + SIGNAL wire_n0lO000l_dataout : STD_LOGIC; + SIGNAL wire_n0lO000O_dataout : STD_LOGIC; + SIGNAL wire_n0lO001i_dataout : STD_LOGIC; + SIGNAL wire_n0lO001l_dataout : STD_LOGIC; + SIGNAL wire_n0lO001O_dataout : STD_LOGIC; + SIGNAL wire_n0lO00i_dataout : STD_LOGIC; + SIGNAL wire_n0lO00ii_dataout : STD_LOGIC; + SIGNAL wire_n0lO00il_dataout : STD_LOGIC; + SIGNAL wire_n0lO00iO_dataout : STD_LOGIC; + SIGNAL wire_n0lO00l_dataout : STD_LOGIC; + SIGNAL wire_n0lO00li_dataout : STD_LOGIC; + SIGNAL wire_n0lO00ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO00lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO00O_dataout : STD_LOGIC; + SIGNAL wire_n0lO00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lO00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lO00OO_dataout : STD_LOGIC; + SIGNAL wire_n0lO010i_dataout : STD_LOGIC; + SIGNAL wire_n0lO010l_dataout : STD_LOGIC; + SIGNAL wire_n0lO010O_dataout : STD_LOGIC; + SIGNAL wire_n0lO011i_dataout : STD_LOGIC; + SIGNAL wire_n0lO011l_dataout : STD_LOGIC; + SIGNAL wire_n0lO011O_dataout : STD_LOGIC; + SIGNAL wire_n0lO01i_dataout : STD_LOGIC; + SIGNAL wire_n0lO01ii_dataout : STD_LOGIC; + SIGNAL wire_n0lO01il_dataout : STD_LOGIC; + SIGNAL wire_n0lO01iO_dataout : STD_LOGIC; + SIGNAL wire_n0lO01l_dataout : STD_LOGIC; + SIGNAL wire_n0lO01li_dataout : STD_LOGIC; + SIGNAL wire_n0lO01ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO01lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO01O_dataout : STD_LOGIC; + SIGNAL wire_n0lO01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lO01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lO01OO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0lO0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0lO0ii_dataout : STD_LOGIC; + SIGNAL wire_n0lO0iii_dataout : STD_LOGIC; + SIGNAL wire_n0lO0iil_dataout : STD_LOGIC; + SIGNAL wire_n0lO0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0il_dataout : STD_LOGIC; + SIGNAL wire_n0lO0ili_dataout : STD_LOGIC; + SIGNAL wire_n0lO0ill_dataout : STD_LOGIC; + SIGNAL wire_n0lO0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0iO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0lO0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0lO0li_dataout : STD_LOGIC; + SIGNAL wire_n0lO0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lO0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0OO_dataout : STD_LOGIC; + SIGNAL wire_n0lO0OOi_dataout : STD_LOGIC; + SIGNAL wire_n0lO0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0lO0OOO_dataout : STD_LOGIC; + SIGNAL wire_n0lO100i_dataout : STD_LOGIC; + SIGNAL wire_n0lO100l_dataout : STD_LOGIC; + SIGNAL wire_n0lO100O_dataout : STD_LOGIC; + SIGNAL wire_n0lO101i_dataout : STD_LOGIC; + SIGNAL wire_n0lO101l_dataout : STD_LOGIC; + SIGNAL wire_n0lO101O_dataout : STD_LOGIC; + SIGNAL wire_n0lO10i_dataout : STD_LOGIC; + SIGNAL wire_n0lO10ii_dataout : STD_LOGIC; + SIGNAL wire_n0lO10il_dataout : STD_LOGIC; + SIGNAL wire_n0lO10iO_dataout : STD_LOGIC; + SIGNAL wire_n0lO10l_dataout : STD_LOGIC; + SIGNAL wire_n0lO10li_dataout : STD_LOGIC; + SIGNAL wire_n0lO10ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO10lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO10O_dataout : STD_LOGIC; + SIGNAL wire_n0lO10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lO10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lO10OO_dataout : STD_LOGIC; + SIGNAL wire_n0lO110i_dataout : STD_LOGIC; + SIGNAL wire_n0lO110l_dataout : STD_LOGIC; + SIGNAL wire_n0lO110O_dataout : STD_LOGIC; + SIGNAL wire_n0lO111i_dataout : STD_LOGIC; + SIGNAL wire_n0lO111l_dataout : STD_LOGIC; + SIGNAL wire_n0lO111O_dataout : STD_LOGIC; + SIGNAL wire_n0lO11i_dataout : STD_LOGIC; + SIGNAL wire_n0lO11ii_dataout : STD_LOGIC; + SIGNAL wire_n0lO11il_dataout : STD_LOGIC; + SIGNAL wire_n0lO11iO_dataout : STD_LOGIC; + SIGNAL wire_n0lO11l_dataout : STD_LOGIC; + SIGNAL wire_n0lO11li_dataout : STD_LOGIC; + SIGNAL wire_n0lO11ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO11lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO11O_dataout : STD_LOGIC; + SIGNAL wire_n0lO11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lO11Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lO11OO_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i0l_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0lO1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0lO1ii_dataout : STD_LOGIC; + SIGNAL wire_n0lO1iii_dataout : STD_LOGIC; + SIGNAL wire_n0lO1iil_dataout : STD_LOGIC; + SIGNAL wire_n0lO1il_dataout : STD_LOGIC; + SIGNAL wire_n0lO1iO_dataout : STD_LOGIC; + SIGNAL wire_n0lO1li_dataout : STD_LOGIC; + SIGNAL wire_n0lO1lii_dataout : STD_LOGIC; + SIGNAL wire_n0lO1lil_dataout : STD_LOGIC; + SIGNAL wire_n0lO1liO_dataout : STD_LOGIC; + SIGNAL wire_n0lO1ll_dataout : STD_LOGIC; + SIGNAL wire_n0lO1lli_dataout : STD_LOGIC; + SIGNAL wire_n0lO1lll_dataout : STD_LOGIC; + SIGNAL wire_n0lO1lO_dataout : STD_LOGIC; + SIGNAL wire_n0lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lO1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0lO1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0lO1OO_dataout : STD_LOGIC; + SIGNAL wire_n0lO1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0lO1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi00O_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0ii_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0il_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0iO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0li_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0ll_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0lO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lOi0OO_dataout : STD_LOGIC; + SIGNAL wire_n0lOi10i_dataout : STD_LOGIC; + SIGNAL wire_n0lOi10l_dataout : STD_LOGIC; + SIGNAL wire_n0lOi10O_dataout : STD_LOGIC; + SIGNAL wire_n0lOi11i_dataout : STD_LOGIC; + SIGNAL wire_n0lOi11l_dataout : STD_LOGIC; + SIGNAL wire_n0lOi11O_dataout : STD_LOGIC; + SIGNAL wire_n0lOi1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOi1ii_dataout : STD_LOGIC; + SIGNAL wire_n0lOi1il_dataout : STD_LOGIC; + SIGNAL wire_n0lOi1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOi1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOiii_dataout : STD_LOGIC; + SIGNAL wire_n0lOiil_dataout : STD_LOGIC; + SIGNAL wire_n0lOiiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOili_dataout : STD_LOGIC; + SIGNAL wire_n0lOiliO_dataout : STD_LOGIC; + SIGNAL wire_n0lOill_dataout : STD_LOGIC; + SIGNAL wire_n0lOilli_dataout : STD_LOGIC; + SIGNAL wire_n0lOilll_dataout : STD_LOGIC; + SIGNAL wire_n0lOillO_dataout : STD_LOGIC; + SIGNAL wire_n0lOilO_dataout : STD_LOGIC; + SIGNAL wire_n0lOilOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOilOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOilOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOiO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOii_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOil_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOli_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOll_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOiOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOl0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOl0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOl0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOl10l_dataout : STD_LOGIC; + SIGNAL wire_n0lOl10l_w_lg_w_lg_w_lg_dataout12598w12604w12605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOl10l_w_lg_w_lg_dataout12598w12604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOl10l_w_lg_dataout12611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOl10l_w_lg_dataout12598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0lOl10O_dataout : STD_LOGIC; + SIGNAL wire_n0lOl1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOl1il_dataout : STD_LOGIC; + SIGNAL wire_n0lOl1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOl1ll_dataout : STD_LOGIC; + SIGNAL wire_n0lOl1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOlii_dataout : STD_LOGIC; + SIGNAL wire_n0lOliiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOlil_dataout : STD_LOGIC; + SIGNAL wire_n0lOlili_dataout : STD_LOGIC; + SIGNAL wire_n0lOlill_dataout : STD_LOGIC; + SIGNAL wire_n0lOlilO_dataout : STD_LOGIC; + SIGNAL wire_n0lOliO_dataout : STD_LOGIC; + SIGNAL wire_n0lOliOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOliOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOliOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOll0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOll0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOll0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOll1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOll1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOll1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOlli_dataout : STD_LOGIC; + SIGNAL wire_n0lOllii_dataout : STD_LOGIC; + SIGNAL wire_n0lOllil_dataout : STD_LOGIC; + SIGNAL wire_n0lOlliO_dataout : STD_LOGIC; + SIGNAL wire_n0lOlll_dataout : STD_LOGIC; + SIGNAL wire_n0lOllli_dataout : STD_LOGIC; + SIGNAL wire_n0lOllll_dataout : STD_LOGIC; + SIGNAL wire_n0lOlllO_dataout : STD_LOGIC; + SIGNAL wire_n0lOllO_dataout : STD_LOGIC; + SIGNAL wire_n0lOllOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOllOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOllOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOlO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOii_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOil_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOli_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOll_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOlOOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOO00l_dataout : STD_LOGIC; + SIGNAL wire_n0lOO00O_dataout : STD_LOGIC; + SIGNAL wire_n0lOO01i_dataout : STD_LOGIC; + SIGNAL wire_n0lOO01l_dataout : STD_LOGIC; + SIGNAL wire_n0lOO01O_dataout : STD_LOGIC; + SIGNAL wire_n0lOO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOO0ii_dataout : STD_LOGIC; + SIGNAL wire_n0lOO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOO10i_dataout : STD_LOGIC; + SIGNAL wire_n0lOO11i_dataout : STD_LOGIC; + SIGNAL wire_n0lOO11l_dataout : STD_LOGIC; + SIGNAL wire_n0lOO11O_dataout : STD_LOGIC; + SIGNAL wire_n0lOO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOO1iO_dataout : STD_LOGIC; + SIGNAL wire_n0lOO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOO1li_dataout : STD_LOGIC; + SIGNAL wire_n0lOO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0lOO1OO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOi1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOOi1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOOii_dataout : STD_LOGIC; + SIGNAL wire_n0lOOiil_dataout : STD_LOGIC; + SIGNAL wire_n0lOOiiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOil_dataout : STD_LOGIC; + SIGNAL wire_n0lOOili_dataout : STD_LOGIC; + SIGNAL wire_n0lOOill_dataout : STD_LOGIC; + SIGNAL wire_n0lOOilO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOiOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOOiOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOOiOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOOl1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOOli_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlii_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlil_dataout : STD_LOGIC; + SIGNAL wire_n0lOOliO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOll_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlli_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlll_dataout : STD_LOGIC; + SIGNAL wire_n0lOOllO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOOlOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO0i_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO0l_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO0O_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO1i_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO1l_dataout : STD_LOGIC; + SIGNAL wire_n0lOOO1O_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOii_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOil_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOiO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOli_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOll_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0lOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0000i_dataout : STD_LOGIC; + SIGNAL wire_n0O0000l_dataout : STD_LOGIC; + SIGNAL wire_n0O0000O_dataout : STD_LOGIC; + SIGNAL wire_n0O0001i_dataout : STD_LOGIC; + SIGNAL wire_n0O0001l_dataout : STD_LOGIC; + SIGNAL wire_n0O0001O_dataout : STD_LOGIC; + SIGNAL wire_n0O000i_dataout : STD_LOGIC; + SIGNAL wire_n0O000ii_dataout : STD_LOGIC; + SIGNAL wire_n0O000il_dataout : STD_LOGIC; + SIGNAL wire_n0O000iO_dataout : STD_LOGIC; + SIGNAL wire_n0O000l_dataout : STD_LOGIC; + SIGNAL wire_n0O000li_dataout : STD_LOGIC; + SIGNAL wire_n0O000ll_dataout : STD_LOGIC; + SIGNAL wire_n0O000lO_dataout : STD_LOGIC; + SIGNAL wire_n0O000O_dataout : STD_LOGIC; + SIGNAL wire_n0O000Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O000Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O000OO_dataout : STD_LOGIC; + SIGNAL wire_n0O0010i_dataout : STD_LOGIC; + SIGNAL wire_n0O0010l_dataout : STD_LOGIC; + SIGNAL wire_n0O0010O_dataout : STD_LOGIC; + SIGNAL wire_n0O0011O_dataout : STD_LOGIC; + SIGNAL wire_n0O001i_dataout : STD_LOGIC; + SIGNAL wire_n0O001ii_dataout : STD_LOGIC; + SIGNAL wire_n0O001il_dataout : STD_LOGIC; + SIGNAL wire_n0O001iO_dataout : STD_LOGIC; + SIGNAL wire_n0O001l_dataout : STD_LOGIC; + SIGNAL wire_n0O001li_dataout : STD_LOGIC; + SIGNAL wire_n0O001ll_dataout : STD_LOGIC; + SIGNAL wire_n0O001lO_dataout : STD_LOGIC; + SIGNAL wire_n0O001O_dataout : STD_LOGIC; + SIGNAL wire_n0O001Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O001Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O001OO_dataout : STD_LOGIC; + SIGNAL wire_n0O00i0i_dataout : STD_LOGIC; + SIGNAL wire_n0O00i0l_dataout : STD_LOGIC; + SIGNAL wire_n0O00i0O_dataout : STD_LOGIC; + SIGNAL wire_n0O00i1i_dataout : STD_LOGIC; + SIGNAL wire_n0O00i1l_dataout : STD_LOGIC; + SIGNAL wire_n0O00i1O_dataout : STD_LOGIC; + SIGNAL wire_n0O00ii_dataout : STD_LOGIC; + SIGNAL wire_n0O00iii_dataout : STD_LOGIC; + SIGNAL wire_n0O00iil_dataout : STD_LOGIC; + SIGNAL wire_n0O00iiO_dataout : STD_LOGIC; + SIGNAL wire_n0O00il_dataout : STD_LOGIC; + SIGNAL wire_n0O00ili_dataout : STD_LOGIC; + SIGNAL wire_n0O00ill_dataout : STD_LOGIC; + SIGNAL wire_n0O00ilO_dataout : STD_LOGIC; + SIGNAL wire_n0O00iO_dataout : STD_LOGIC; + SIGNAL wire_n0O00iOi_dataout : STD_LOGIC; + SIGNAL wire_n0O00iOl_dataout : STD_LOGIC; + SIGNAL wire_n0O00iOO_dataout : STD_LOGIC; + SIGNAL wire_n0O00l0i_dataout : STD_LOGIC; + SIGNAL wire_n0O00l0l_dataout : STD_LOGIC; + SIGNAL wire_n0O00l1i_dataout : STD_LOGIC; + SIGNAL wire_n0O00l1l_dataout : STD_LOGIC; + SIGNAL wire_n0O00l1O_dataout : STD_LOGIC; + SIGNAL wire_n0O00li_dataout : STD_LOGIC; + SIGNAL wire_n0O00ll_dataout : STD_LOGIC; + SIGNAL wire_n0O00lO_dataout : STD_LOGIC; + SIGNAL wire_n0O00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O00OO_dataout : STD_LOGIC; + SIGNAL wire_n0O0101i_dataout : STD_LOGIC; + SIGNAL wire_n0O010i_dataout : STD_LOGIC; + SIGNAL wire_n0O010l_dataout : STD_LOGIC; + SIGNAL wire_n0O010O_dataout : STD_LOGIC; + SIGNAL wire_n0O0110i_dataout : STD_LOGIC; + SIGNAL wire_n0O0110l_dataout : STD_LOGIC; + SIGNAL wire_n0O0110O_dataout : STD_LOGIC; + SIGNAL wire_n0O0111i_dataout : STD_LOGIC; + SIGNAL wire_n0O0111l_dataout : STD_LOGIC; + SIGNAL wire_n0O0111O_dataout : STD_LOGIC; + SIGNAL wire_n0O011i_dataout : STD_LOGIC; + SIGNAL wire_n0O011ii_dataout : STD_LOGIC; + SIGNAL wire_n0O011il_dataout : STD_LOGIC; + SIGNAL wire_n0O011iO_dataout : STD_LOGIC; + SIGNAL wire_n0O011l_dataout : STD_LOGIC; + SIGNAL wire_n0O011li_dataout : STD_LOGIC; + SIGNAL wire_n0O011ll_dataout : STD_LOGIC; + SIGNAL wire_n0O011lO_dataout : STD_LOGIC; + SIGNAL wire_n0O011O_dataout : STD_LOGIC; + SIGNAL wire_n0O011Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O011OO_dataout : STD_LOGIC; + SIGNAL wire_n0O01ii_dataout : STD_LOGIC; + SIGNAL wire_n0O01il_dataout : STD_LOGIC; + SIGNAL wire_n0O01iO_dataout : STD_LOGIC; + SIGNAL wire_n0O01iOO_dataout : STD_LOGIC; + SIGNAL wire_n0O01iOO_w_lg_dataout12199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01l0l_dataout : STD_LOGIC; + SIGNAL wire_n0O01l0l_w_lg_dataout12195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01l1O_dataout : STD_LOGIC; + SIGNAL wire_n0O01l1O_w_lg_dataout12197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01li_dataout : STD_LOGIC; + SIGNAL wire_n0O01lil_dataout : STD_LOGIC; + SIGNAL wire_n0O01lil_w_lg_dataout12193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01ll_dataout : STD_LOGIC; + SIGNAL wire_n0O01lli_dataout : STD_LOGIC; + SIGNAL wire_n0O01lli_w_lg_dataout12191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01llO_dataout : STD_LOGIC; + SIGNAL wire_n0O01llO_w_lg_dataout12189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01lO_dataout : STD_LOGIC; + SIGNAL wire_n0O01lOl_dataout : STD_LOGIC; + SIGNAL wire_n0O01lOl_w_lg_dataout12187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O01O1i_w_lg_dataout12185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0O01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O01OO_dataout : STD_LOGIC; + SIGNAL wire_n0O0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0O0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0O0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0O0iii_dataout : STD_LOGIC; + SIGNAL wire_n0O0iil_dataout : STD_LOGIC; + SIGNAL wire_n0O0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0O0ili_dataout : STD_LOGIC; + SIGNAL wire_n0O0ill_dataout : STD_LOGIC; + SIGNAL wire_n0O0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOiO_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOli_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOll_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOlO_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOOi_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOOl_dataout : STD_LOGIC; + SIGNAL wire_n0O0iOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0l01i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l01l_dataout : STD_LOGIC; + SIGNAL wire_n0O0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0l0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O0l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0O0l11i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l11l_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1il_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1iO_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1li_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1ll_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1lO_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0O0l1OO_dataout : STD_LOGIC; + SIGNAL wire_n0O0li0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0li0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0li0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0li1i_dataout : STD_LOGIC; + SIGNAL wire_n0O0li1l_dataout : STD_LOGIC; + SIGNAL wire_n0O0li1O_dataout : STD_LOGIC; + SIGNAL wire_n0O0lii_dataout : STD_LOGIC; + SIGNAL wire_n0O0liii_dataout : STD_LOGIC; + SIGNAL wire_n0O0liil_dataout : STD_LOGIC; + SIGNAL wire_n0O0liiO_dataout : STD_LOGIC; + SIGNAL wire_n0O0lil_dataout : STD_LOGIC; + SIGNAL wire_n0O0lili_dataout : STD_LOGIC; + SIGNAL wire_n0O0lill_dataout : STD_LOGIC; + SIGNAL wire_n0O0liO_dataout : STD_LOGIC; + SIGNAL wire_n0O0ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0ll1i_dataout : STD_LOGIC; + SIGNAL wire_n0O0ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0O0ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0O0lli_dataout : STD_LOGIC; + SIGNAL wire_n0O0llii_dataout : STD_LOGIC; + SIGNAL wire_n0O0llil_dataout : STD_LOGIC; + SIGNAL wire_n0O0lll_dataout : STD_LOGIC; + SIGNAL wire_n0O0llO_dataout : STD_LOGIC; + SIGNAL wire_n0O0lO0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0lO0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0lO0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n0O0lO1O_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOii_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOil_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOiO_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOli_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOll_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOlO_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOOi_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOOl_dataout : STD_LOGIC; + SIGNAL wire_n0O0lOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0O10i_dataout : STD_LOGIC; + SIGNAL wire_n0O0O10l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O10O_dataout : STD_LOGIC; + SIGNAL wire_n0O0O11i_dataout : STD_LOGIC; + SIGNAL wire_n0O0O11l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O11O_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1ii_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1il_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1iO_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1li_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1ll_dataout : STD_LOGIC; + SIGNAL wire_n0O0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0O0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0O0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0O0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0O0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0O0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0O0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0O0OO0i_dataout : STD_LOGIC; + SIGNAL wire_n0O0OO0l_dataout : STD_LOGIC; + SIGNAL wire_n0O0OO0O_dataout : STD_LOGIC; + SIGNAL wire_n0O0OO1O_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOii_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOil_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOiO_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOl_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOli_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOll_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOlO_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOO_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOOi_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOOl_dataout : STD_LOGIC; + SIGNAL wire_n0O0OOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1000i_dataout : STD_LOGIC; + SIGNAL wire_n0O1000l_dataout : STD_LOGIC; + SIGNAL wire_n0O1000O_dataout : STD_LOGIC; + SIGNAL wire_n0O1001i_dataout : STD_LOGIC; + SIGNAL wire_n0O1001l_dataout : STD_LOGIC; + SIGNAL wire_n0O1001O_dataout : STD_LOGIC; + SIGNAL wire_n0O100i_dataout : STD_LOGIC; + SIGNAL wire_n0O100ii_dataout : STD_LOGIC; + SIGNAL wire_n0O100il_dataout : STD_LOGIC; + SIGNAL wire_n0O100iO_dataout : STD_LOGIC; + SIGNAL wire_n0O100l_dataout : STD_LOGIC; + SIGNAL wire_n0O100li_dataout : STD_LOGIC; + SIGNAL wire_n0O100ll_dataout : STD_LOGIC; + SIGNAL wire_n0O100lO_dataout : STD_LOGIC; + SIGNAL wire_n0O100O_dataout : STD_LOGIC; + SIGNAL wire_n0O100Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O100Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O100OO_dataout : STD_LOGIC; + SIGNAL wire_n0O1010i_dataout : STD_LOGIC; + SIGNAL wire_n0O1010l_dataout : STD_LOGIC; + SIGNAL wire_n0O1010O_dataout : STD_LOGIC; + SIGNAL wire_n0O101i_dataout : STD_LOGIC; + SIGNAL wire_n0O101ii_dataout : STD_LOGIC; + SIGNAL wire_n0O101il_dataout : STD_LOGIC; + SIGNAL wire_n0O101iO_dataout : STD_LOGIC; + SIGNAL wire_n0O101l_dataout : STD_LOGIC; + SIGNAL wire_n0O101li_dataout : STD_LOGIC; + SIGNAL wire_n0O101ll_dataout : STD_LOGIC; + SIGNAL wire_n0O101lO_dataout : STD_LOGIC; + SIGNAL wire_n0O101O_dataout : STD_LOGIC; + SIGNAL wire_n0O101Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O101Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O101OO_dataout : STD_LOGIC; + SIGNAL wire_n0O10i0i_dataout : STD_LOGIC; + SIGNAL wire_n0O10i0l_dataout : STD_LOGIC; + SIGNAL wire_n0O10i0O_dataout : STD_LOGIC; + SIGNAL wire_n0O10i1i_dataout : STD_LOGIC; + SIGNAL wire_n0O10i1l_dataout : STD_LOGIC; + SIGNAL wire_n0O10i1O_dataout : STD_LOGIC; + SIGNAL wire_n0O10ii_dataout : STD_LOGIC; + SIGNAL wire_n0O10iii_dataout : STD_LOGIC; + SIGNAL wire_n0O10iil_dataout : STD_LOGIC; + SIGNAL wire_n0O10iiO_dataout : STD_LOGIC; + SIGNAL wire_n0O10il_dataout : STD_LOGIC; + SIGNAL wire_n0O10ili_dataout : STD_LOGIC; + SIGNAL wire_n0O10ill_dataout : STD_LOGIC; + SIGNAL wire_n0O10ilO_dataout : STD_LOGIC; + SIGNAL wire_n0O10iO_dataout : STD_LOGIC; + SIGNAL wire_n0O10iOi_dataout : STD_LOGIC; + SIGNAL wire_n0O10iOl_dataout : STD_LOGIC; + SIGNAL wire_n0O10iOO_dataout : STD_LOGIC; + SIGNAL wire_n0O10l0i_dataout : STD_LOGIC; + SIGNAL wire_n0O10l0l_dataout : STD_LOGIC; + SIGNAL wire_n0O10l0O_dataout : STD_LOGIC; + SIGNAL wire_n0O10l1i_dataout : STD_LOGIC; + SIGNAL wire_n0O10l1l_dataout : STD_LOGIC; + SIGNAL wire_n0O10l1O_dataout : STD_LOGIC; + SIGNAL wire_n0O10li_dataout : STD_LOGIC; + SIGNAL wire_n0O10lii_dataout : STD_LOGIC; + SIGNAL wire_n0O10lil_dataout : STD_LOGIC; + SIGNAL wire_n0O10liO_dataout : STD_LOGIC; + SIGNAL wire_n0O10ll_dataout : STD_LOGIC; + SIGNAL wire_n0O10lli_dataout : STD_LOGIC; + SIGNAL wire_n0O10lll_dataout : STD_LOGIC; + SIGNAL wire_n0O10llO_dataout : STD_LOGIC; + SIGNAL wire_n0O10lO_dataout : STD_LOGIC; + SIGNAL wire_n0O10lOi_dataout : STD_LOGIC; + SIGNAL wire_n0O10lOl_dataout : STD_LOGIC; + SIGNAL wire_n0O10lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O10O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O10O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O10O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O10O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O10O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O10O1O_dataout : STD_LOGIC; + SIGNAL wire_n0O10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O10Oii_dataout : STD_LOGIC; + SIGNAL wire_n0O10Oil_dataout : STD_LOGIC; + SIGNAL wire_n0O10OiO_dataout : STD_LOGIC; + SIGNAL wire_n0O10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O10Oli_dataout : STD_LOGIC; + SIGNAL wire_n0O10Oll_dataout : STD_LOGIC; + SIGNAL wire_n0O10OlO_dataout : STD_LOGIC; + SIGNAL wire_n0O10OO_dataout : STD_LOGIC; + SIGNAL wire_n0O10OOi_dataout : STD_LOGIC; + SIGNAL wire_n0O10OOl_dataout : STD_LOGIC; + SIGNAL wire_n0O10OOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1100i_dataout : STD_LOGIC; + SIGNAL wire_n0O1100l_dataout : STD_LOGIC; + SIGNAL wire_n0O1100O_dataout : STD_LOGIC; + SIGNAL wire_n0O1101i_dataout : STD_LOGIC; + SIGNAL wire_n0O1101l_dataout : STD_LOGIC; + SIGNAL wire_n0O1101O_dataout : STD_LOGIC; + SIGNAL wire_n0O110i_dataout : STD_LOGIC; + SIGNAL wire_n0O110ii_dataout : STD_LOGIC; + SIGNAL wire_n0O110il_dataout : STD_LOGIC; + SIGNAL wire_n0O110iO_dataout : STD_LOGIC; + SIGNAL wire_n0O110l_dataout : STD_LOGIC; + SIGNAL wire_n0O110li_dataout : STD_LOGIC; + SIGNAL wire_n0O110ll_dataout : STD_LOGIC; + SIGNAL wire_n0O110lO_dataout : STD_LOGIC; + SIGNAL wire_n0O110O_dataout : STD_LOGIC; + SIGNAL wire_n0O110Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O110Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O110OO_dataout : STD_LOGIC; + SIGNAL wire_n0O1110i_dataout : STD_LOGIC; + SIGNAL wire_n0O1110l_dataout : STD_LOGIC; + SIGNAL wire_n0O1110O_dataout : STD_LOGIC; + SIGNAL wire_n0O1111i_dataout : STD_LOGIC; + SIGNAL wire_n0O1111l_dataout : STD_LOGIC; + SIGNAL wire_n0O1111O_dataout : STD_LOGIC; + SIGNAL wire_n0O111i_dataout : STD_LOGIC; + SIGNAL wire_n0O111ii_dataout : STD_LOGIC; + SIGNAL wire_n0O111il_dataout : STD_LOGIC; + SIGNAL wire_n0O111iO_dataout : STD_LOGIC; + SIGNAL wire_n0O111l_dataout : STD_LOGIC; + SIGNAL wire_n0O111li_dataout : STD_LOGIC; + SIGNAL wire_n0O111ll_dataout : STD_LOGIC; + SIGNAL wire_n0O111lO_dataout : STD_LOGIC; + SIGNAL wire_n0O111O_dataout : STD_LOGIC; + SIGNAL wire_n0O111Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O111Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O111OO_dataout : STD_LOGIC; + SIGNAL wire_n0O11i0i_dataout : STD_LOGIC; + SIGNAL wire_n0O11i0l_dataout : STD_LOGIC; + SIGNAL wire_n0O11i0O_dataout : STD_LOGIC; + SIGNAL wire_n0O11i1i_dataout : STD_LOGIC; + SIGNAL wire_n0O11i1l_dataout : STD_LOGIC; + SIGNAL wire_n0O11i1O_dataout : STD_LOGIC; + SIGNAL wire_n0O11ii_dataout : STD_LOGIC; + SIGNAL wire_n0O11iii_dataout : STD_LOGIC; + SIGNAL wire_n0O11iil_dataout : STD_LOGIC; + SIGNAL wire_n0O11iiO_dataout : STD_LOGIC; + SIGNAL wire_n0O11il_dataout : STD_LOGIC; + SIGNAL wire_n0O11ili_dataout : STD_LOGIC; + SIGNAL wire_n0O11ill_dataout : STD_LOGIC; + SIGNAL wire_n0O11ilO_dataout : STD_LOGIC; + SIGNAL wire_n0O11iO_dataout : STD_LOGIC; + SIGNAL wire_n0O11iOi_dataout : STD_LOGIC; + SIGNAL wire_n0O11iOl_dataout : STD_LOGIC; + SIGNAL wire_n0O11iOO_dataout : STD_LOGIC; + SIGNAL wire_n0O11l0i_dataout : STD_LOGIC; + SIGNAL wire_n0O11l0l_dataout : STD_LOGIC; + SIGNAL wire_n0O11l0O_dataout : STD_LOGIC; + SIGNAL wire_n0O11l1i_dataout : STD_LOGIC; + SIGNAL wire_n0O11l1l_dataout : STD_LOGIC; + SIGNAL wire_n0O11l1O_dataout : STD_LOGIC; + SIGNAL wire_n0O11li_dataout : STD_LOGIC; + SIGNAL wire_n0O11lii_dataout : STD_LOGIC; + SIGNAL wire_n0O11lil_dataout : STD_LOGIC; + SIGNAL wire_n0O11liO_dataout : STD_LOGIC; + SIGNAL wire_n0O11ll_dataout : STD_LOGIC; + SIGNAL wire_n0O11lli_dataout : STD_LOGIC; + SIGNAL wire_n0O11lll_dataout : STD_LOGIC; + SIGNAL wire_n0O11llO_dataout : STD_LOGIC; + SIGNAL wire_n0O11lO_dataout : STD_LOGIC; + SIGNAL wire_n0O11lOi_dataout : STD_LOGIC; + SIGNAL wire_n0O11lOl_dataout : STD_LOGIC; + SIGNAL wire_n0O11lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O11O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O11O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O11O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O11O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O11O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O11O1O_dataout : STD_LOGIC; + SIGNAL wire_n0O11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O11Oii_dataout : STD_LOGIC; + SIGNAL wire_n0O11Oil_dataout : STD_LOGIC; + SIGNAL wire_n0O11OiO_dataout : STD_LOGIC; + SIGNAL wire_n0O11Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O11Oli_dataout : STD_LOGIC; + SIGNAL wire_n0O11OO_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0ii_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0il_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0iO_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0li_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0ll_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O1i0OO_dataout : STD_LOGIC; + SIGNAL wire_n0O1i10i_dataout : STD_LOGIC; + SIGNAL wire_n0O1i10l_dataout : STD_LOGIC; + SIGNAL wire_n0O1i10O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i11i_dataout : STD_LOGIC; + SIGNAL wire_n0O1i11l_dataout : STD_LOGIC; + SIGNAL wire_n0O1i11O_dataout : STD_LOGIC; + SIGNAL wire_n0O1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1i1ii_dataout : STD_LOGIC; + SIGNAL wire_n0O1i1il_dataout : STD_LOGIC; + SIGNAL wire_n0O1i1iO_dataout : STD_LOGIC; + SIGNAL wire_n0O1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1ii1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1iii_dataout : STD_LOGIC; + SIGNAL wire_n0O1iiii_dataout : STD_LOGIC; + SIGNAL wire_n0O1iiil_dataout : STD_LOGIC; + SIGNAL wire_n0O1iiiO_dataout : STD_LOGIC; + SIGNAL wire_n0O1iil_dataout : STD_LOGIC; + SIGNAL wire_n0O1iiO_dataout : STD_LOGIC; + SIGNAL wire_n0O1iiOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1il1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1ili_dataout : STD_LOGIC; + SIGNAL wire_n0O1ill_dataout : STD_LOGIC; + SIGNAL wire_n0O1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0O1iO0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOii_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOil_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOiO_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOli_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOll_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOlO_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1iOOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1l00i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l00l_dataout : STD_LOGIC; + SIGNAL wire_n0O1l00O_dataout : STD_LOGIC; + SIGNAL wire_n0O1l01i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l01l_dataout : STD_LOGIC; + SIGNAL wire_n0O1l01O_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0il_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0li_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0lO_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O1l0OO_dataout : STD_LOGIC; + SIGNAL wire_n0O1l10i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l10l_dataout : STD_LOGIC; + SIGNAL wire_n0O1l10O_dataout : STD_LOGIC; + SIGNAL wire_n0O1l11i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l11l_dataout : STD_LOGIC; + SIGNAL wire_n0O1l11O_dataout : STD_LOGIC; + SIGNAL wire_n0O1l1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n0O1l1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O1l1OO_dataout : STD_LOGIC; + SIGNAL wire_n0O1li0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1li0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1li0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1li1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1li1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1li1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1lii_dataout : STD_LOGIC; + SIGNAL wire_n0O1liii_dataout : STD_LOGIC; + SIGNAL wire_n0O1liil_dataout : STD_LOGIC; + SIGNAL wire_n0O1liiO_dataout : STD_LOGIC; + SIGNAL wire_n0O1lil_dataout : STD_LOGIC; + SIGNAL wire_n0O1lili_dataout : STD_LOGIC; + SIGNAL wire_n0O1lill_dataout : STD_LOGIC; + SIGNAL wire_n0O1lilO_dataout : STD_LOGIC; + SIGNAL wire_n0O1liO_dataout : STD_LOGIC; + SIGNAL wire_n0O1liOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1liOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1ll0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1ll0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1ll0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1ll1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1ll1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1lli_dataout : STD_LOGIC; + SIGNAL wire_n0O1llii_dataout : STD_LOGIC; + SIGNAL wire_n0O1lll_dataout : STD_LOGIC; + SIGNAL wire_n0O1llO_dataout : STD_LOGIC; + SIGNAL wire_n0O1lOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1lOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1O00l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O01i_dataout : STD_LOGIC; + SIGNAL wire_n0O1O01O_dataout : STD_LOGIC; + SIGNAL wire_n0O1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1O0ii_dataout : STD_LOGIC; + SIGNAL wire_n0O1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1O10O_dataout : STD_LOGIC; + SIGNAL wire_n0O1O1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1O1iO_dataout : STD_LOGIC; + SIGNAL wire_n0O1O1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1O1ll_dataout : STD_LOGIC; + SIGNAL wire_n0O1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oili_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oill_dataout : STD_LOGIC; + SIGNAL wire_n0O1OilO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OiOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1OiOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1OiOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0O1Olii_dataout : STD_LOGIC; + SIGNAL wire_n0O1Olil_dataout : STD_LOGIC; + SIGNAL wire_n0O1OliO_dataout : STD_LOGIC; + SIGNAL wire_n0O1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0O1Olli_dataout : STD_LOGIC; + SIGNAL wire_n0O1Olll_dataout : STD_LOGIC; + SIGNAL wire_n0O1OllO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OlOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1OlOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1OlOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO0i_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO0l_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO0O_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO1i_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO1l_dataout : STD_LOGIC; + SIGNAL wire_n0O1OO1O_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOii_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOil_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOiO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOli_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOll_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOlO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOOi_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOOl_dataout : STD_LOGIC; + SIGNAL wire_n0O1OOOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi000i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi000l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi000O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi001i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi001l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi001O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00il_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00li_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oi00OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi010i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi010l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi010O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi011i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi011l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi011O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01il_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01li_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oi01OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0iii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0iil_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0ili_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0ill_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0lii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0lil_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0liO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0lli_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0lll_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0llO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0Oi0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi100i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi100l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi100O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi101i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi101l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi101O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10il_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10li_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oi10OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi110i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi110l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi110O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi111i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi111l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi111O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11il_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11li_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oi11OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1i0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1iii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1iil_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1iiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1ili_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1ill_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1iOl_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1iOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1l0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1l0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1l0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1l1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1l1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1lii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1lil_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1liO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1lli_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1lll_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1llO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0Oi1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0OiiiOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oiil0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oiil0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oiil0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oiil1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oiil1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oiil1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oiilii_dataout : STD_LOGIC; + SIGNAL wire_n0Oiilil_dataout : STD_LOGIC; + SIGNAL wire_n0OiiliO_dataout : STD_LOGIC; + SIGNAL wire_n0Oiilli_dataout : STD_LOGIC; + SIGNAL wire_n0Oiilll_dataout : STD_LOGIC; + SIGNAL wire_n0OiillO_dataout : STD_LOGIC; + SIGNAL wire_n0OiilO_dataout : STD_LOGIC; + SIGNAL wire_n0OiilOi_dataout : STD_LOGIC; + SIGNAL wire_n0OiilOl_dataout : STD_LOGIC; + SIGNAL wire_n0OiilOO_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OiiO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOi_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOii_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOil_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOl_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOli_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOll_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOO_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OiiOOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oil0OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oil10i_dataout : STD_LOGIC; + SIGNAL wire_n0Oil10l_dataout : STD_LOGIC; + SIGNAL wire_n0Oil10O_dataout : STD_LOGIC; + SIGNAL wire_n0Oil11i_dataout : STD_LOGIC; + SIGNAL wire_n0Oil11l_dataout : STD_LOGIC; + SIGNAL wire_n0Oil11O_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1il_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1li_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oil1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oilii_dataout : STD_LOGIC; + SIGNAL wire_n0Oilil_dataout : STD_LOGIC; + SIGNAL wire_n0OiliO_dataout : STD_LOGIC; + SIGNAL wire_n0OiliOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oill0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oill0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oill0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oill1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oill1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oilli_dataout : STD_LOGIC; + SIGNAL wire_n0Oillii_dataout : STD_LOGIC; + SIGNAL wire_n0Oillil_dataout : STD_LOGIC; + SIGNAL wire_n0OilliO_dataout : STD_LOGIC; + SIGNAL wire_n0Oilll_dataout : STD_LOGIC; + SIGNAL wire_n0Oillli_dataout : STD_LOGIC; + SIGNAL wire_n0Oillll_dataout : STD_LOGIC; + SIGNAL wire_n0OilllO_dataout : STD_LOGIC; + SIGNAL wire_n0OillO_dataout : STD_LOGIC; + SIGNAL wire_n0OillOi_dataout : STD_LOGIC; + SIGNAL wire_n0OillOl_dataout : STD_LOGIC; + SIGNAL wire_n0OillOO_dataout : STD_LOGIC; + SIGNAL wire_n0OilO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OilO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OilO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OilO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OilO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OilO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OilOi_dataout : STD_LOGIC; + SIGNAL wire_n0OilOii_dataout : STD_LOGIC; + SIGNAL wire_n0OilOil_dataout : STD_LOGIC; + SIGNAL wire_n0OilOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OilOl_dataout : STD_LOGIC; + SIGNAL wire_n0OilOli_dataout : STD_LOGIC; + SIGNAL wire_n0OilOll_dataout : STD_LOGIC; + SIGNAL wire_n0OilOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OilOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OilOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OilOOO_dataout : STD_LOGIC; + SIGNAL wire_n0OiO01i_dataout : STD_LOGIC; + SIGNAL wire_n0OiO01l_dataout : STD_LOGIC; + SIGNAL wire_n0OiO01O_dataout : STD_LOGIC; + SIGNAL wire_n0OiO10i_dataout : STD_LOGIC; + SIGNAL wire_n0OiO10l_dataout : STD_LOGIC; + SIGNAL wire_n0OiO10O_dataout : STD_LOGIC; + SIGNAL wire_n0OiO11i_dataout : STD_LOGIC; + SIGNAL wire_n0OiO11l_dataout : STD_LOGIC; + SIGNAL wire_n0OiO11O_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1ii_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1il_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1iO_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1li_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1ll_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1lO_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OiO1OO_dataout : STD_LOGIC; + SIGNAL wire_n0OiOl0i_dataout : STD_LOGIC; + SIGNAL wire_n0OiOl0l_dataout : STD_LOGIC; + SIGNAL wire_n0OiOl0O_dataout : STD_LOGIC; + SIGNAL wire_n0OiOl1i_dataout : STD_LOGIC; + SIGNAL wire_n0OiOl1l_dataout : STD_LOGIC; + SIGNAL wire_n0OiOl1O_dataout : STD_LOGIC; + SIGNAL wire_n0OiOlii_dataout : STD_LOGIC; + SIGNAL wire_n0OiOlil_dataout : STD_LOGIC; + SIGNAL wire_n0OiOliO_dataout : STD_LOGIC; + SIGNAL wire_n0OiOlli_dataout : STD_LOGIC; + SIGNAL wire_n0OiOlll_dataout : STD_LOGIC; + SIGNAL wire_n0OiOllO_dataout : STD_LOGIC; + SIGNAL wire_n0OiOOli_dataout : STD_LOGIC; + SIGNAL wire_n0OiOOll_dataout : STD_LOGIC; + SIGNAL wire_n0OiOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OiOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OiOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OiOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol000i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol000l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol000O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol001i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol001l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol001O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00ii_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00il_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00iO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00li_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00ll_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00lO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Ol00OO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Ol01OO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0i0i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0i0l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0i0O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0i1i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0i1l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0i1O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0iii_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0iil_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0iiO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0ili_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0ill_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0ilO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0iOi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0iOl_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0iOO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0lii_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0lil_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0Ol0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0Ol10Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol10Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Ol10OO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol110i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol111i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol111l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol111O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1i0i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1i0l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1i0O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1i1i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1i1l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1i1O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1iii_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1iil_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1iiO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1ili_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1ill_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1iOl_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1iOO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1l1i_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1l1l_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1liO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1liO_w_lg_w_lg_w_lg_dataout11687w11693w11694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0Ol1liO_w_lg_w_lg_dataout11687w11693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0Ol1liO_w_lg_dataout11700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0Ol1liO_w_lg_dataout11687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0Ol1lli_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1llO_dataout : STD_LOGIC; + SIGNAL wire_n0Ol1lOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli00i_dataout : STD_LOGIC; + SIGNAL wire_n0Oli00l_dataout : STD_LOGIC; + SIGNAL wire_n0Oli00O_dataout : STD_LOGIC; + SIGNAL wire_n0Oli01i_dataout : STD_LOGIC; + SIGNAL wire_n0Oli01l_dataout : STD_LOGIC; + SIGNAL wire_n0Oli01O_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0il_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0li_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oli0OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli10O_dataout : STD_LOGIC; + SIGNAL wire_n0Oli1ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oli1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oli1lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oli1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oli1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oli1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oli1OO_dataout : STD_LOGIC; + SIGNAL wire_n0Olii0i_dataout : STD_LOGIC; + SIGNAL wire_n0Olii0l_dataout : STD_LOGIC; + SIGNAL wire_n0Olii0O_dataout : STD_LOGIC; + SIGNAL wire_n0Olii1i_dataout : STD_LOGIC; + SIGNAL wire_n0Olii1l_dataout : STD_LOGIC; + SIGNAL wire_n0Olii1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oliii_dataout : STD_LOGIC; + SIGNAL wire_n0Oliiii_dataout : STD_LOGIC; + SIGNAL wire_n0Oliiil_dataout : STD_LOGIC; + SIGNAL wire_n0OliiiO_dataout : STD_LOGIC; + SIGNAL wire_n0Oliil_dataout : STD_LOGIC; + SIGNAL wire_n0Oliili_dataout : STD_LOGIC; + SIGNAL wire_n0Oliill_dataout : STD_LOGIC; + SIGNAL wire_n0OliilO_dataout : STD_LOGIC; + SIGNAL wire_n0OliiO_dataout : STD_LOGIC; + SIGNAL wire_n0OliiOi_dataout : STD_LOGIC; + SIGNAL wire_n0OliiOl_dataout : STD_LOGIC; + SIGNAL wire_n0OliiOO_dataout : STD_LOGIC; + SIGNAL wire_n0Olil0i_dataout : STD_LOGIC; + SIGNAL wire_n0Olil0l_dataout : STD_LOGIC; + SIGNAL wire_n0Olil0O_dataout : STD_LOGIC; + SIGNAL wire_n0Olil1i_dataout : STD_LOGIC; + SIGNAL wire_n0Olil1l_dataout : STD_LOGIC; + SIGNAL wire_n0Olil1O_dataout : STD_LOGIC; + SIGNAL wire_n0Olili_dataout : STD_LOGIC; + SIGNAL wire_n0Olilii_dataout : STD_LOGIC; + SIGNAL wire_n0Olilil_dataout : STD_LOGIC; + SIGNAL wire_n0OliliO_dataout : STD_LOGIC; + SIGNAL wire_n0Olill_dataout : STD_LOGIC; + SIGNAL wire_n0Olilli_dataout : STD_LOGIC; + SIGNAL wire_n0Olilll_dataout : STD_LOGIC; + SIGNAL wire_n0OlillO_dataout : STD_LOGIC; + SIGNAL wire_n0OlilO_dataout : STD_LOGIC; + SIGNAL wire_n0OlilOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlilOl_dataout : STD_LOGIC; + SIGNAL wire_n0OlilOO_dataout : STD_LOGIC; + SIGNAL wire_n0OliO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OliO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OliO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OliO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OliO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OliO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OliOi_dataout : STD_LOGIC; + SIGNAL wire_n0OliOii_dataout : STD_LOGIC; + SIGNAL wire_n0OliOil_dataout : STD_LOGIC; + SIGNAL wire_n0OliOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OliOl_dataout : STD_LOGIC; + SIGNAL wire_n0OliOli_dataout : STD_LOGIC; + SIGNAL wire_n0OliOll_dataout : STD_LOGIC; + SIGNAL wire_n0OliOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OliOO_dataout : STD_LOGIC; + SIGNAL wire_n0OliOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OliOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OliOOO_dataout : STD_LOGIC; + SIGNAL wire_n0Oll00i_dataout : STD_LOGIC; + SIGNAL wire_n0Oll00l_dataout : STD_LOGIC; + SIGNAL wire_n0Oll00O_dataout : STD_LOGIC; + SIGNAL wire_n0Oll01i_dataout : STD_LOGIC; + SIGNAL wire_n0Oll01l_dataout : STD_LOGIC; + SIGNAL wire_n0Oll01O_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0i_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0il_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0l_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0li_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0O_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oll0OO_dataout : STD_LOGIC; + SIGNAL wire_n0Oll10i_dataout : STD_LOGIC; + SIGNAL wire_n0Oll10l_dataout : STD_LOGIC; + SIGNAL wire_n0Oll10O_dataout : STD_LOGIC; + SIGNAL wire_n0Oll11i_dataout : STD_LOGIC; + SIGNAL wire_n0Oll11l_dataout : STD_LOGIC; + SIGNAL wire_n0Oll11O_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1i_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1ii_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1il_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1iO_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1l_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1li_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1ll_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1lO_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1O_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0Oll1OO_dataout : STD_LOGIC; + SIGNAL wire_n0Olli0i_dataout : STD_LOGIC; + SIGNAL wire_n0Olli0l_dataout : STD_LOGIC; + SIGNAL wire_n0Olli0O_dataout : STD_LOGIC; + SIGNAL wire_n0Olli1i_dataout : STD_LOGIC; + SIGNAL wire_n0Olli1l_dataout : STD_LOGIC; + SIGNAL wire_n0Olli1O_dataout : STD_LOGIC; + SIGNAL wire_n0Ollii_dataout : STD_LOGIC; + SIGNAL wire_n0Olliii_dataout : STD_LOGIC; + SIGNAL wire_n0Olliil_dataout : STD_LOGIC; + SIGNAL wire_n0OlliiO_dataout : STD_LOGIC; + SIGNAL wire_n0Ollil_dataout : STD_LOGIC; + SIGNAL wire_n0Ollili_dataout : STD_LOGIC; + SIGNAL wire_n0Ollill_dataout : STD_LOGIC; + SIGNAL wire_n0OllilO_dataout : STD_LOGIC; + SIGNAL wire_n0OlliO_dataout : STD_LOGIC; + SIGNAL wire_n0OlliOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlliOl_dataout : STD_LOGIC; + SIGNAL wire_n0Ollli_dataout : STD_LOGIC; + SIGNAL wire_n0Olllil_dataout : STD_LOGIC; + SIGNAL wire_n0OllliO_dataout : STD_LOGIC; + SIGNAL wire_n0Ollll_dataout : STD_LOGIC; + SIGNAL wire_n0Olllli_dataout : STD_LOGIC; + SIGNAL wire_n0Olllll_dataout : STD_LOGIC; + SIGNAL wire_n0OllllO_dataout : STD_LOGIC; + SIGNAL wire_n0OlllO_dataout : STD_LOGIC; + SIGNAL wire_n0OlllOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlllOl_dataout : STD_LOGIC; + SIGNAL wire_n0OlllOO_dataout : STD_LOGIC; + SIGNAL wire_n0OllO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OllO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OllO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OllO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OllO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OllO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OllOi_dataout : STD_LOGIC; + SIGNAL wire_n0OllOii_dataout : STD_LOGIC; + SIGNAL wire_n0OllOil_dataout : STD_LOGIC; + SIGNAL wire_n0OllOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OllOl_dataout : STD_LOGIC; + SIGNAL wire_n0OllOli_dataout : STD_LOGIC; + SIGNAL wire_n0OllOll_dataout : STD_LOGIC; + SIGNAL wire_n0OllOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OllOO_dataout : STD_LOGIC; + SIGNAL wire_n0OllOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OllOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OllOOO_dataout : STD_LOGIC; + SIGNAL wire_n0OlO00i_dataout : STD_LOGIC; + SIGNAL wire_n0OlO00l_dataout : STD_LOGIC; + SIGNAL wire_n0OlO00O_dataout : STD_LOGIC; + SIGNAL wire_n0OlO01i_dataout : STD_LOGIC; + SIGNAL wire_n0OlO01l_dataout : STD_LOGIC; + SIGNAL wire_n0OlO01O_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0ii_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0il_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0iO_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0li_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0ll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0lO_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OlO0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OlO10i_dataout : STD_LOGIC; + SIGNAL wire_n0OlO10l_dataout : STD_LOGIC; + SIGNAL wire_n0OlO10O_dataout : STD_LOGIC; + SIGNAL wire_n0OlO11i_dataout : STD_LOGIC; + SIGNAL wire_n0OlO11l_dataout : STD_LOGIC; + SIGNAL wire_n0OlO11O_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1ii_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1il_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1iO_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1li_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1ll_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1lO_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OlO1OO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOi0i_dataout : STD_LOGIC; + SIGNAL wire_n0OlOi0l_dataout : STD_LOGIC; + SIGNAL wire_n0OlOi0O_dataout : STD_LOGIC; + SIGNAL wire_n0OlOi1i_dataout : STD_LOGIC; + SIGNAL wire_n0OlOi1l_dataout : STD_LOGIC; + SIGNAL wire_n0OlOi1O_dataout : STD_LOGIC; + SIGNAL wire_n0OlOii_dataout : STD_LOGIC; + SIGNAL wire_n0OlOiii_dataout : STD_LOGIC; + SIGNAL wire_n0OlOiil_dataout : STD_LOGIC; + SIGNAL wire_n0OlOiiO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOil_dataout : STD_LOGIC; + SIGNAL wire_n0OlOili_dataout : STD_LOGIC; + SIGNAL wire_n0OlOill_dataout : STD_LOGIC; + SIGNAL wire_n0OlOilO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOiOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlOiOl_dataout : STD_LOGIC; + SIGNAL wire_n0OlOiOO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOl0i_dataout : STD_LOGIC; + SIGNAL wire_n0OlOl0l_dataout : STD_LOGIC; + SIGNAL wire_n0OlOl0O_dataout : STD_LOGIC; + SIGNAL wire_n0OlOl1i_dataout : STD_LOGIC; + SIGNAL wire_n0OlOl1l_dataout : STD_LOGIC; + SIGNAL wire_n0OlOl1O_dataout : STD_LOGIC; + SIGNAL wire_n0OlOli_dataout : STD_LOGIC; + SIGNAL wire_n0OlOlii_dataout : STD_LOGIC; + SIGNAL wire_n0OlOlil_dataout : STD_LOGIC; + SIGNAL wire_n0OlOliO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOll_dataout : STD_LOGIC; + SIGNAL wire_n0OlOlli_dataout : STD_LOGIC; + SIGNAL wire_n0OlOlll_dataout : STD_LOGIC; + SIGNAL wire_n0OlOllO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOll_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOO_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OlOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0OO000O_dataout : STD_LOGIC; + SIGNAL wire_n0OO001i_dataout : STD_LOGIC; + SIGNAL wire_n0OO001l_dataout : STD_LOGIC; + SIGNAL wire_n0OO001O_dataout : STD_LOGIC; + SIGNAL wire_n0OO00i_dataout : STD_LOGIC; + SIGNAL wire_n0OO00ii_dataout : STD_LOGIC; + SIGNAL wire_n0OO00il_dataout : STD_LOGIC; + SIGNAL wire_n0OO00iO_dataout : STD_LOGIC; + SIGNAL wire_n0OO00l_dataout : STD_LOGIC; + SIGNAL wire_n0OO00li_dataout : STD_LOGIC; + SIGNAL wire_n0OO00ll_dataout : STD_LOGIC; + SIGNAL wire_n0OO00O_dataout : STD_LOGIC; + SIGNAL wire_n0OO010i_dataout : STD_LOGIC; + SIGNAL wire_n0OO010l_dataout : STD_LOGIC; + SIGNAL wire_n0OO010O_dataout : STD_LOGIC; + SIGNAL wire_n0OO011i_dataout : STD_LOGIC; + SIGNAL wire_n0OO011l_dataout : STD_LOGIC; + SIGNAL wire_n0OO011O_dataout : STD_LOGIC; + SIGNAL wire_n0OO01i_dataout : STD_LOGIC; + SIGNAL wire_n0OO01ii_dataout : STD_LOGIC; + SIGNAL wire_n0OO01il_dataout : STD_LOGIC; + SIGNAL wire_n0OO01iO_dataout : STD_LOGIC; + SIGNAL wire_n0OO01l_dataout : STD_LOGIC; + SIGNAL wire_n0OO01li_dataout : STD_LOGIC; + SIGNAL wire_n0OO01ll_dataout : STD_LOGIC; + SIGNAL wire_n0OO01lO_dataout : STD_LOGIC; + SIGNAL wire_n0OO01O_dataout : STD_LOGIC; + SIGNAL wire_n0OO01Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OO01Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OO01OO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0ii_dataout : STD_LOGIC; + SIGNAL wire_n0OO0il_dataout : STD_LOGIC; + SIGNAL wire_n0OO0iO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l0i_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l0l_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l0O_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l1i_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l1l_dataout : STD_LOGIC; + SIGNAL wire_n0OO0l1O_dataout : STD_LOGIC; + SIGNAL wire_n0OO0lii_dataout : STD_LOGIC; + SIGNAL wire_n0OO0lil_dataout : STD_LOGIC; + SIGNAL wire_n0OO0liO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0lli_dataout : STD_LOGIC; + SIGNAL wire_n0OO0lll_dataout : STD_LOGIC; + SIGNAL wire_n0OO0llO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0lOi_dataout : STD_LOGIC; + SIGNAL wire_n0OO0lOl_dataout : STD_LOGIC; + SIGNAL wire_n0OO0lOO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0O0i_dataout : STD_LOGIC; + SIGNAL wire_n0OO0O0l_dataout : STD_LOGIC; + SIGNAL wire_n0OO0O0O_dataout : STD_LOGIC; + SIGNAL wire_n0OO0O1i_dataout : STD_LOGIC; + SIGNAL wire_n0OO0O1l_dataout : STD_LOGIC; + SIGNAL wire_n0OO0O1O_dataout : STD_LOGIC; + SIGNAL wire_n0OO0Oii_dataout : STD_LOGIC; + SIGNAL wire_n0OO0Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OO0OiO_dataout : STD_LOGIC; + SIGNAL wire_n0OO0Oli_dataout : STD_LOGIC; + SIGNAL wire_n0OO0Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OO0OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OO100i_dataout : STD_LOGIC; + SIGNAL wire_n0OO100l_dataout : STD_LOGIC; + SIGNAL wire_n0OO10i_dataout : STD_LOGIC; + SIGNAL wire_n0OO10l_dataout : STD_LOGIC; + SIGNAL wire_n0OO10O_dataout : STD_LOGIC; + SIGNAL wire_n0OO110i_dataout : STD_LOGIC; + SIGNAL wire_n0OO110l_dataout : STD_LOGIC; + SIGNAL wire_n0OO110O_dataout : STD_LOGIC; + SIGNAL wire_n0OO111i_dataout : STD_LOGIC; + SIGNAL wire_n0OO111l_dataout : STD_LOGIC; + SIGNAL wire_n0OO111O_dataout : STD_LOGIC; + SIGNAL wire_n0OO11i_dataout : STD_LOGIC; + SIGNAL wire_n0OO11ii_dataout : STD_LOGIC; + SIGNAL wire_n0OO11il_dataout : STD_LOGIC; + SIGNAL wire_n0OO11iO_dataout : STD_LOGIC; + SIGNAL wire_n0OO11l_dataout : STD_LOGIC; + SIGNAL wire_n0OO11li_dataout : STD_LOGIC; + SIGNAL wire_n0OO11ll_dataout : STD_LOGIC; + SIGNAL wire_n0OO11lO_dataout : STD_LOGIC; + SIGNAL wire_n0OO11O_dataout : STD_LOGIC; + SIGNAL wire_n0OO11Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OO1ii_dataout : STD_LOGIC; + SIGNAL wire_n0OO1il_dataout : STD_LOGIC; + SIGNAL wire_n0OO1ili_dataout : STD_LOGIC; + SIGNAL wire_n0OO1ill_dataout : STD_LOGIC; + SIGNAL wire_n0OO1ilO_dataout : STD_LOGIC; + SIGNAL wire_n0OO1iO_dataout : STD_LOGIC; + SIGNAL wire_n0OO1iOi_dataout : STD_LOGIC; + SIGNAL wire_n0OO1iOl_dataout : STD_LOGIC; + SIGNAL wire_n0OO1iOO_dataout : STD_LOGIC; + SIGNAL wire_n0OO1l0i_dataout : STD_LOGIC; + SIGNAL wire_n0OO1l0l_dataout : STD_LOGIC; + SIGNAL wire_n0OO1l0O_dataout : STD_LOGIC; + SIGNAL wire_n0OO1l1i_dataout : STD_LOGIC; + SIGNAL wire_n0OO1l1l_dataout : STD_LOGIC; + SIGNAL wire_n0OO1l1O_dataout : STD_LOGIC; + SIGNAL wire_n0OO1li_dataout : STD_LOGIC; + SIGNAL wire_n0OO1lii_dataout : STD_LOGIC; + SIGNAL wire_n0OO1lil_dataout : STD_LOGIC; + SIGNAL wire_n0OO1liO_dataout : STD_LOGIC; + SIGNAL wire_n0OO1ll_dataout : STD_LOGIC; + SIGNAL wire_n0OO1lli_dataout : STD_LOGIC; + SIGNAL wire_n0OO1lll_dataout : STD_LOGIC; + SIGNAL wire_n0OO1lO_dataout : STD_LOGIC; + SIGNAL wire_n0OO1O0i_dataout : STD_LOGIC; + SIGNAL wire_n0OO1O0l_dataout : STD_LOGIC; + SIGNAL wire_n0OO1O0O_dataout : STD_LOGIC; + SIGNAL wire_n0OO1O1O_dataout : STD_LOGIC; + SIGNAL wire_n0OO1Oii_dataout : STD_LOGIC; + SIGNAL wire_n0OO1Oil_dataout : STD_LOGIC; + SIGNAL wire_n0OO1OiO_dataout : STD_LOGIC; + SIGNAL wire_n0OO1Oli_dataout : STD_LOGIC; + SIGNAL wire_n0OO1Oll_dataout : STD_LOGIC; + SIGNAL wire_n0OO1OlO_dataout : STD_LOGIC; + SIGNAL wire_n0OO1OOi_dataout : STD_LOGIC; + SIGNAL wire_n0OO1OOl_dataout : STD_LOGIC; + SIGNAL wire_n0OO1OOO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi00i_dataout : STD_LOGIC; + SIGNAL wire_n0OOi00l_dataout : STD_LOGIC; + SIGNAL wire_n0OOi00O_dataout : STD_LOGIC; + SIGNAL wire_n0OOi01i_dataout : STD_LOGIC; + SIGNAL wire_n0OOi01l_dataout : STD_LOGIC; + SIGNAL wire_n0OOi01O_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0ii_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0il_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0iO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0li_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0ll_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0lO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0O_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OOi0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1i_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1il_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1iO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1li_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1ll_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1lO_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OOi1OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOii0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOii1i_dataout : STD_LOGIC; + SIGNAL wire_n0OOii1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOii1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOiii_dataout : STD_LOGIC; + SIGNAL wire_n0OOiil_dataout : STD_LOGIC; + SIGNAL wire_n0OOiiO_dataout : STD_LOGIC; + SIGNAL wire_n0OOil0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOil0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOil0O_dataout : STD_LOGIC; + SIGNAL wire_n0OOil1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOili_dataout : STD_LOGIC; + SIGNAL wire_n0OOilii_dataout : STD_LOGIC; + SIGNAL wire_n0OOilil_dataout : STD_LOGIC; + SIGNAL wire_n0OOiliO_dataout : STD_LOGIC; + SIGNAL wire_n0OOilli_dataout : STD_LOGIC; + SIGNAL wire_n0OOilll_dataout : STD_LOGIC; + SIGNAL wire_n0OOillO_dataout : STD_LOGIC; + SIGNAL wire_n0OOilOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOilOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOilOO_dataout : STD_LOGIC; + SIGNAL wire_n0OOiO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOiO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOiO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OOiO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OOiO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOiO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOii_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOil_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOli_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOll_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOiOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOl00i_dataout : STD_LOGIC; + SIGNAL wire_n0OOl00l_dataout : STD_LOGIC; + SIGNAL wire_n0OOl00O_dataout : STD_LOGIC; + SIGNAL wire_n0OOl01i_dataout : STD_LOGIC; + SIGNAL wire_n0OOl01l_dataout : STD_LOGIC; + SIGNAL wire_n0OOl01O_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0ii_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0il_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0iO_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0li_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0ll_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0lO_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OOl0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OOl1OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOli0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOli0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOli0O_dataout : STD_LOGIC; + SIGNAL wire_n0OOli1i_dataout : STD_LOGIC; + SIGNAL wire_n0OOli1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOli1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOlii_dataout : STD_LOGIC; + SIGNAL wire_n0OOliii_dataout : STD_LOGIC; + SIGNAL wire_n0OOliil_dataout : STD_LOGIC; + SIGNAL wire_n0OOliiO_dataout : STD_LOGIC; + SIGNAL wire_n0OOlil_dataout : STD_LOGIC; + SIGNAL wire_n0OOliO_dataout : STD_LOGIC; + SIGNAL wire_n0OOllil_dataout : STD_LOGIC; + SIGNAL wire_n0OOlliO_dataout : STD_LOGIC; + SIGNAL wire_n0OOlll_dataout : STD_LOGIC; + SIGNAL wire_n0OOllli_dataout : STD_LOGIC; + SIGNAL wire_n0OOllll_dataout : STD_LOGIC; + SIGNAL wire_n0OOlllO_dataout : STD_LOGIC; + SIGNAL wire_n0OOllO_dataout : STD_LOGIC; + SIGNAL wire_n0OOllOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOllOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOllOO_dataout : STD_LOGIC; + SIGNAL wire_n0OOlO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOlO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOlO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OOlO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OOlO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOlO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOii_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOil_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOli_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOll_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOlOOO_dataout : STD_LOGIC; + SIGNAL wire_n0OOO00i_dataout : STD_LOGIC; + SIGNAL wire_n0OOO00l_dataout : STD_LOGIC; + SIGNAL wire_n0OOO00O_dataout : STD_LOGIC; + SIGNAL wire_n0OOO01O_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0ii_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0il_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0iO_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0li_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0ll_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0lO_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n0OOO0OO_dataout : STD_LOGIC; + SIGNAL wire_n0OOO10i_dataout : STD_LOGIC; + SIGNAL wire_n0OOO11i_dataout : STD_LOGIC; + SIGNAL wire_n0OOO11l_dataout : STD_LOGIC; + SIGNAL wire_n0OOO11O_dataout : STD_LOGIC; + SIGNAL wire_n0OOO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOOi0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOOi0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOOi0O_dataout : STD_LOGIC; + SIGNAL wire_n0OOOi1i_dataout : STD_LOGIC; + SIGNAL wire_n0OOOi1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOOi1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOOiii_dataout : STD_LOGIC; + SIGNAL wire_n0OOOiil_dataout : STD_LOGIC; + SIGNAL wire_n0OOOiiO_dataout : STD_LOGIC; + SIGNAL wire_n0OOOili_dataout : STD_LOGIC; + SIGNAL wire_n0OOOill_dataout : STD_LOGIC; + SIGNAL wire_n0OOOilO_dataout : STD_LOGIC; + SIGNAL wire_n0OOOiOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOOiOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOOlOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOOlOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOOlOO_dataout : STD_LOGIC; + SIGNAL wire_n0OOOO0i_dataout : STD_LOGIC; + SIGNAL wire_n0OOOO0l_dataout : STD_LOGIC; + SIGNAL wire_n0OOOO0O_dataout : STD_LOGIC; + SIGNAL wire_n0OOOO1i_dataout : STD_LOGIC; + SIGNAL wire_n0OOOO1l_dataout : STD_LOGIC; + SIGNAL wire_n0OOOO1O_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOii_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOil_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOiO_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOli_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOll_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOlO_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOOi_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOOl_dataout : STD_LOGIC; + SIGNAL wire_n0OOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n100000i_dataout : STD_LOGIC; + SIGNAL wire_n100000l_dataout : STD_LOGIC; + SIGNAL wire_n100000O_dataout : STD_LOGIC; + SIGNAL wire_n100001i_dataout : STD_LOGIC; + SIGNAL wire_n100001l_dataout : STD_LOGIC; + SIGNAL wire_n100001O_dataout : STD_LOGIC; + SIGNAL wire_n10000i_dataout : STD_LOGIC; + SIGNAL wire_n10000ii_dataout : STD_LOGIC; + SIGNAL wire_n10000il_dataout : STD_LOGIC; + SIGNAL wire_n10000l_dataout : STD_LOGIC; + SIGNAL wire_n10000O_dataout : STD_LOGIC; + SIGNAL wire_n100010i_dataout : STD_LOGIC; + SIGNAL wire_n100010l_dataout : STD_LOGIC; + SIGNAL wire_n100010O_dataout : STD_LOGIC; + SIGNAL wire_n100011i_dataout : STD_LOGIC; + SIGNAL wire_n100011l_dataout : STD_LOGIC; + SIGNAL wire_n100011O_dataout : STD_LOGIC; + SIGNAL wire_n10001i_dataout : STD_LOGIC; + SIGNAL wire_n10001ii_dataout : STD_LOGIC; + SIGNAL wire_n10001il_dataout : STD_LOGIC; + SIGNAL wire_n10001iO_dataout : STD_LOGIC; + SIGNAL wire_n10001l_dataout : STD_LOGIC; + SIGNAL wire_n10001li_dataout : STD_LOGIC; + SIGNAL wire_n10001ll_dataout : STD_LOGIC; + SIGNAL wire_n10001lO_dataout : STD_LOGIC; + SIGNAL wire_n10001O_dataout : STD_LOGIC; + SIGNAL wire_n10001Oi_dataout : STD_LOGIC; + SIGNAL wire_n10001Ol_dataout : STD_LOGIC; + SIGNAL wire_n10001OO_dataout : STD_LOGIC; + SIGNAL wire_n1000i0i_dataout : STD_LOGIC; + SIGNAL wire_n1000i0l_dataout : STD_LOGIC; + SIGNAL wire_n1000i0O_dataout : STD_LOGIC; + SIGNAL wire_n1000i1i_dataout : STD_LOGIC; + SIGNAL wire_n1000i1l_dataout : STD_LOGIC; + SIGNAL wire_n1000i1O_dataout : STD_LOGIC; + SIGNAL wire_n1000ii_dataout : STD_LOGIC; + SIGNAL wire_n1000iii_dataout : STD_LOGIC; + SIGNAL wire_n1000iil_dataout : STD_LOGIC; + SIGNAL wire_n1000iiO_dataout : STD_LOGIC; + SIGNAL wire_n1000il_dataout : STD_LOGIC; + SIGNAL wire_n1000ili_dataout : STD_LOGIC; + SIGNAL wire_n1000ill_dataout : STD_LOGIC; + SIGNAL wire_n1000ilO_dataout : STD_LOGIC; + SIGNAL wire_n1000iO_dataout : STD_LOGIC; + SIGNAL wire_n1000iOi_dataout : STD_LOGIC; + SIGNAL wire_n1000iOl_dataout : STD_LOGIC; + SIGNAL wire_n1000iOO_dataout : STD_LOGIC; + SIGNAL wire_n1000l0i_dataout : STD_LOGIC; + SIGNAL wire_n1000l0l_dataout : STD_LOGIC; + SIGNAL wire_n1000l0O_dataout : STD_LOGIC; + SIGNAL wire_n1000l1i_dataout : STD_LOGIC; + SIGNAL wire_n1000l1l_dataout : STD_LOGIC; + SIGNAL wire_n1000l1O_dataout : STD_LOGIC; + SIGNAL wire_n1000li_dataout : STD_LOGIC; + SIGNAL wire_n1000lii_dataout : STD_LOGIC; + SIGNAL wire_n1000lil_dataout : STD_LOGIC; + SIGNAL wire_n1000liO_dataout : STD_LOGIC; + SIGNAL wire_n1000lli_dataout : STD_LOGIC; + SIGNAL wire_n1000lll_dataout : STD_LOGIC; + SIGNAL wire_n1000llO_dataout : STD_LOGIC; + SIGNAL wire_n1000lOi_dataout : STD_LOGIC; + SIGNAL wire_n1000lOl_dataout : STD_LOGIC; + SIGNAL wire_n1000lOO_dataout : STD_LOGIC; + SIGNAL wire_n1000O0i_dataout : STD_LOGIC; + SIGNAL wire_n1000O0l_dataout : STD_LOGIC; + SIGNAL wire_n1000O0O_dataout : STD_LOGIC; + SIGNAL wire_n1000O1i_dataout : STD_LOGIC; + SIGNAL wire_n1000O1l_dataout : STD_LOGIC; + SIGNAL wire_n1000O1O_dataout : STD_LOGIC; + SIGNAL wire_n1000Oi_dataout : STD_LOGIC; + SIGNAL wire_n1000Oii_dataout : STD_LOGIC; + SIGNAL wire_n1000Oil_dataout : STD_LOGIC; + SIGNAL wire_n1000OiO_dataout : STD_LOGIC; + SIGNAL wire_n1000Ol_dataout : STD_LOGIC; + SIGNAL wire_n1000Oli_dataout : STD_LOGIC; + SIGNAL wire_n1000Oll_dataout : STD_LOGIC; + SIGNAL wire_n1000OlO_dataout : STD_LOGIC; + SIGNAL wire_n1000OO_dataout : STD_LOGIC; + SIGNAL wire_n1000OOi_dataout : STD_LOGIC; + SIGNAL wire_n1000OOl_dataout : STD_LOGIC; + SIGNAL wire_n1000OOO_dataout : STD_LOGIC; + SIGNAL wire_n100100i_dataout : STD_LOGIC; + SIGNAL wire_n100100l_dataout : STD_LOGIC; + SIGNAL wire_n100100O_dataout : STD_LOGIC; + SIGNAL wire_n100101i_dataout : STD_LOGIC; + SIGNAL wire_n100101l_dataout : STD_LOGIC; + SIGNAL wire_n100101O_dataout : STD_LOGIC; + SIGNAL wire_n10010i_dataout : STD_LOGIC; + SIGNAL wire_n10010ii_dataout : STD_LOGIC; + SIGNAL wire_n10010il_dataout : STD_LOGIC; + SIGNAL wire_n10010iO_dataout : STD_LOGIC; + SIGNAL wire_n10010l_dataout : STD_LOGIC; + SIGNAL wire_n10010li_dataout : STD_LOGIC; + SIGNAL wire_n10010ll_dataout : STD_LOGIC; + SIGNAL wire_n10010lO_dataout : STD_LOGIC; + SIGNAL wire_n10010O_dataout : STD_LOGIC; + SIGNAL wire_n10010Oi_dataout : STD_LOGIC; + SIGNAL wire_n10010Ol_dataout : STD_LOGIC; + SIGNAL wire_n10010OO_dataout : STD_LOGIC; + SIGNAL wire_n100110i_dataout : STD_LOGIC; + SIGNAL wire_n100110l_dataout : STD_LOGIC; + SIGNAL wire_n100110O_dataout : STD_LOGIC; + SIGNAL wire_n100111i_dataout : STD_LOGIC; + SIGNAL wire_n100111l_dataout : STD_LOGIC; + SIGNAL wire_n100111O_dataout : STD_LOGIC; + SIGNAL wire_n10011i_dataout : STD_LOGIC; + SIGNAL wire_n10011ii_dataout : STD_LOGIC; + SIGNAL wire_n10011il_dataout : STD_LOGIC; + SIGNAL wire_n10011iO_dataout : STD_LOGIC; + SIGNAL wire_n10011l_dataout : STD_LOGIC; + SIGNAL wire_n10011li_dataout : STD_LOGIC; + SIGNAL wire_n10011ll_dataout : STD_LOGIC; + SIGNAL wire_n10011lO_dataout : STD_LOGIC; + SIGNAL wire_n10011O_dataout : STD_LOGIC; + SIGNAL wire_n10011Oi_dataout : STD_LOGIC; + SIGNAL wire_n10011Ol_dataout : STD_LOGIC; + SIGNAL wire_n10011OO_dataout : STD_LOGIC; + SIGNAL wire_n1001i0i_dataout : STD_LOGIC; + SIGNAL wire_n1001i0l_dataout : STD_LOGIC; + SIGNAL wire_n1001i0O_dataout : STD_LOGIC; + SIGNAL wire_n1001i1i_dataout : STD_LOGIC; + SIGNAL wire_n1001i1l_dataout : STD_LOGIC; + SIGNAL wire_n1001i1O_dataout : STD_LOGIC; + SIGNAL wire_n1001ii_dataout : STD_LOGIC; + SIGNAL wire_n1001iii_dataout : STD_LOGIC; + SIGNAL wire_n1001iil_dataout : STD_LOGIC; + SIGNAL wire_n1001iiO_dataout : STD_LOGIC; + SIGNAL wire_n1001il_dataout : STD_LOGIC; + SIGNAL wire_n1001ili_dataout : STD_LOGIC; + SIGNAL wire_n1001ill_dataout : STD_LOGIC; + SIGNAL wire_n1001ilO_dataout : STD_LOGIC; + SIGNAL wire_n1001iO_dataout : STD_LOGIC; + SIGNAL wire_n1001iOi_dataout : STD_LOGIC; + SIGNAL wire_n1001iOl_dataout : STD_LOGIC; + SIGNAL wire_n1001iOO_dataout : STD_LOGIC; + SIGNAL wire_n1001l0i_dataout : STD_LOGIC; + SIGNAL wire_n1001l0l_dataout : STD_LOGIC; + SIGNAL wire_n1001l0O_dataout : STD_LOGIC; + SIGNAL wire_n1001l1i_dataout : STD_LOGIC; + SIGNAL wire_n1001l1l_dataout : STD_LOGIC; + SIGNAL wire_n1001l1O_dataout : STD_LOGIC; + SIGNAL wire_n1001li_dataout : STD_LOGIC; + SIGNAL wire_n1001lii_dataout : STD_LOGIC; + SIGNAL wire_n1001lil_dataout : STD_LOGIC; + SIGNAL wire_n1001liO_dataout : STD_LOGIC; + SIGNAL wire_n1001ll_dataout : STD_LOGIC; + SIGNAL wire_n1001lli_dataout : STD_LOGIC; + SIGNAL wire_n1001lll_dataout : STD_LOGIC; + SIGNAL wire_n1001llO_dataout : STD_LOGIC; + SIGNAL wire_n1001lO_dataout : STD_LOGIC; + SIGNAL wire_n1001lOi_dataout : STD_LOGIC; + SIGNAL wire_n1001lOl_dataout : STD_LOGIC; + SIGNAL wire_n1001lOO_dataout : STD_LOGIC; + SIGNAL wire_n1001O0i_dataout : STD_LOGIC; + SIGNAL wire_n1001O0l_dataout : STD_LOGIC; + SIGNAL wire_n1001O0O_dataout : STD_LOGIC; + SIGNAL wire_n1001O1i_dataout : STD_LOGIC; + SIGNAL wire_n1001O1l_dataout : STD_LOGIC; + SIGNAL wire_n1001O1O_dataout : STD_LOGIC; + SIGNAL wire_n1001Oi_dataout : STD_LOGIC; + SIGNAL wire_n1001Oii_dataout : STD_LOGIC; + SIGNAL wire_n1001Oil_dataout : STD_LOGIC; + SIGNAL wire_n1001OiO_dataout : STD_LOGIC; + SIGNAL wire_n1001Ol_dataout : STD_LOGIC; + SIGNAL wire_n1001Oli_dataout : STD_LOGIC; + SIGNAL wire_n1001OO_dataout : STD_LOGIC; + SIGNAL wire_n1001OOi_dataout : STD_LOGIC; + SIGNAL wire_n1001OOl_dataout : STD_LOGIC; + SIGNAL wire_n1001OOO_dataout : STD_LOGIC; + SIGNAL wire_n100i00i_dataout : STD_LOGIC; + SIGNAL wire_n100i00l_dataout : STD_LOGIC; + SIGNAL wire_n100i00O_dataout : STD_LOGIC; + SIGNAL wire_n100i01i_dataout : STD_LOGIC; + SIGNAL wire_n100i01l_dataout : STD_LOGIC; + SIGNAL wire_n100i01O_dataout : STD_LOGIC; + SIGNAL wire_n100i0i_dataout : STD_LOGIC; + SIGNAL wire_n100i0ii_dataout : STD_LOGIC; + SIGNAL wire_n100i0il_dataout : STD_LOGIC; + SIGNAL wire_n100i0iO_dataout : STD_LOGIC; + SIGNAL wire_n100i0l_dataout : STD_LOGIC; + SIGNAL wire_n100i0li_dataout : STD_LOGIC; + SIGNAL wire_n100i0ll_dataout : STD_LOGIC; + SIGNAL wire_n100i0lO_dataout : STD_LOGIC; + SIGNAL wire_n100i0O_dataout : STD_LOGIC; + SIGNAL wire_n100i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n100i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n100i0OO_dataout : STD_LOGIC; + SIGNAL wire_n100i10i_dataout : STD_LOGIC; + SIGNAL wire_n100i10l_dataout : STD_LOGIC; + SIGNAL wire_n100i10O_dataout : STD_LOGIC; + SIGNAL wire_n100i11i_dataout : STD_LOGIC; + SIGNAL wire_n100i11l_dataout : STD_LOGIC; + SIGNAL wire_n100i11O_dataout : STD_LOGIC; + SIGNAL wire_n100i1i_dataout : STD_LOGIC; + SIGNAL wire_n100i1ii_dataout : STD_LOGIC; + SIGNAL wire_n100i1il_dataout : STD_LOGIC; + SIGNAL wire_n100i1iO_dataout : STD_LOGIC; + SIGNAL wire_n100i1l_dataout : STD_LOGIC; + SIGNAL wire_n100i1li_dataout : STD_LOGIC; + SIGNAL wire_n100i1ll_dataout : STD_LOGIC; + SIGNAL wire_n100i1lO_dataout : STD_LOGIC; + SIGNAL wire_n100i1O_dataout : STD_LOGIC; + SIGNAL wire_n100i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n100i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n100i1OO_dataout : STD_LOGIC; + SIGNAL wire_n100ii1i_dataout : STD_LOGIC; + SIGNAL wire_n100iii_dataout : STD_LOGIC; + SIGNAL wire_n100iiil_dataout : STD_LOGIC; + SIGNAL wire_n100iiiO_dataout : STD_LOGIC; + SIGNAL wire_n100iil_dataout : STD_LOGIC; + SIGNAL wire_n100iili_dataout : STD_LOGIC; + SIGNAL wire_n100iill_dataout : STD_LOGIC; + SIGNAL wire_n100iilO_dataout : STD_LOGIC; + SIGNAL wire_n100iiO_dataout : STD_LOGIC; + SIGNAL wire_n100iiOi_dataout : STD_LOGIC; + SIGNAL wire_n100iiOl_dataout : STD_LOGIC; + SIGNAL wire_n100iiOO_dataout : STD_LOGIC; + SIGNAL wire_n100il0i_dataout : STD_LOGIC; + SIGNAL wire_n100il0l_dataout : STD_LOGIC; + SIGNAL wire_n100il0O_dataout : STD_LOGIC; + SIGNAL wire_n100il1i_dataout : STD_LOGIC; + SIGNAL wire_n100il1l_dataout : STD_LOGIC; + SIGNAL wire_n100il1O_dataout : STD_LOGIC; + SIGNAL wire_n100ili_dataout : STD_LOGIC; + SIGNAL wire_n100ilii_dataout : STD_LOGIC; + SIGNAL wire_n100ilil_dataout : STD_LOGIC; + SIGNAL wire_n100iliO_dataout : STD_LOGIC; + SIGNAL wire_n100ill_dataout : STD_LOGIC; + SIGNAL wire_n100illi_dataout : STD_LOGIC; + SIGNAL wire_n100illl_dataout : STD_LOGIC; + SIGNAL wire_n100illO_dataout : STD_LOGIC; + SIGNAL wire_n100ilO_dataout : STD_LOGIC; + SIGNAL wire_n100ilOi_dataout : STD_LOGIC; + SIGNAL wire_n100ilOl_dataout : STD_LOGIC; + SIGNAL wire_n100ilOO_dataout : STD_LOGIC; + SIGNAL wire_n100iO0i_dataout : STD_LOGIC; + SIGNAL wire_n100iO0l_dataout : STD_LOGIC; + SIGNAL wire_n100iO0O_dataout : STD_LOGIC; + SIGNAL wire_n100iO1i_dataout : STD_LOGIC; + SIGNAL wire_n100iO1l_dataout : STD_LOGIC; + SIGNAL wire_n100iO1O_dataout : STD_LOGIC; + SIGNAL wire_n100iOi_dataout : STD_LOGIC; + SIGNAL wire_n100iOii_dataout : STD_LOGIC; + SIGNAL wire_n100iOil_dataout : STD_LOGIC; + SIGNAL wire_n100iOiO_dataout : STD_LOGIC; + SIGNAL wire_n100iOl_dataout : STD_LOGIC; + SIGNAL wire_n100iOli_dataout : STD_LOGIC; + SIGNAL wire_n100iOll_dataout : STD_LOGIC; + SIGNAL wire_n100iOlO_dataout : STD_LOGIC; + SIGNAL wire_n100iOO_dataout : STD_LOGIC; + SIGNAL wire_n100iOOi_dataout : STD_LOGIC; + SIGNAL wire_n100iOOl_dataout : STD_LOGIC; + SIGNAL wire_n100iOOO_dataout : STD_LOGIC; + SIGNAL wire_n100l00i_dataout : STD_LOGIC; + SIGNAL wire_n100l00l_dataout : STD_LOGIC; + SIGNAL wire_n100l00O_dataout : STD_LOGIC; + SIGNAL wire_n100l01i_dataout : STD_LOGIC; + SIGNAL wire_n100l01l_dataout : STD_LOGIC; + SIGNAL wire_n100l01O_dataout : STD_LOGIC; + SIGNAL wire_n100l0i_dataout : STD_LOGIC; + SIGNAL wire_n100l0ii_dataout : STD_LOGIC; + SIGNAL wire_n100l0il_dataout : STD_LOGIC; + SIGNAL wire_n100l0iO_dataout : STD_LOGIC; + SIGNAL wire_n100l0l_dataout : STD_LOGIC; + SIGNAL wire_n100l0li_dataout : STD_LOGIC; + SIGNAL wire_n100l0ll_dataout : STD_LOGIC; + SIGNAL wire_n100l0lO_dataout : STD_LOGIC; + SIGNAL wire_n100l0O_dataout : STD_LOGIC; + SIGNAL wire_n100l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n100l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n100l0OO_dataout : STD_LOGIC; + SIGNAL wire_n100l10i_dataout : STD_LOGIC; + SIGNAL wire_n100l10l_dataout : STD_LOGIC; + SIGNAL wire_n100l10O_dataout : STD_LOGIC; + SIGNAL wire_n100l11i_dataout : STD_LOGIC; + SIGNAL wire_n100l11l_dataout : STD_LOGIC; + SIGNAL wire_n100l11O_dataout : STD_LOGIC; + SIGNAL wire_n100l1i_dataout : STD_LOGIC; + SIGNAL wire_n100l1ii_dataout : STD_LOGIC; + SIGNAL wire_n100l1il_dataout : STD_LOGIC; + SIGNAL wire_n100l1iO_dataout : STD_LOGIC; + SIGNAL wire_n100l1l_dataout : STD_LOGIC; + SIGNAL wire_n100l1li_dataout : STD_LOGIC; + SIGNAL wire_n100l1ll_dataout : STD_LOGIC; + SIGNAL wire_n100l1lO_dataout : STD_LOGIC; + SIGNAL wire_n100l1O_dataout : STD_LOGIC; + SIGNAL wire_n100l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n100l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n100l1OO_dataout : STD_LOGIC; + SIGNAL wire_n100li0i_dataout : STD_LOGIC; + SIGNAL wire_n100li0l_dataout : STD_LOGIC; + SIGNAL wire_n100li0O_dataout : STD_LOGIC; + SIGNAL wire_n100li1i_dataout : STD_LOGIC; + SIGNAL wire_n100li1l_dataout : STD_LOGIC; + SIGNAL wire_n100li1O_dataout : STD_LOGIC; + SIGNAL wire_n100lii_dataout : STD_LOGIC; + SIGNAL wire_n100liii_dataout : STD_LOGIC; + SIGNAL wire_n100liil_dataout : STD_LOGIC; + SIGNAL wire_n100liiO_dataout : STD_LOGIC; + SIGNAL wire_n100lil_dataout : STD_LOGIC; + SIGNAL wire_n100lili_dataout : STD_LOGIC; + SIGNAL wire_n100lill_dataout : STD_LOGIC; + SIGNAL wire_n100lilO_dataout : STD_LOGIC; + SIGNAL wire_n100liO_dataout : STD_LOGIC; + SIGNAL wire_n100liOi_dataout : STD_LOGIC; + SIGNAL wire_n100liOl_dataout : STD_LOGIC; + SIGNAL wire_n100liOO_dataout : STD_LOGIC; + SIGNAL wire_n100ll0i_dataout : STD_LOGIC; + SIGNAL wire_n100ll0l_dataout : STD_LOGIC; + SIGNAL wire_n100ll0O_dataout : STD_LOGIC; + SIGNAL wire_n100ll1i_dataout : STD_LOGIC; + SIGNAL wire_n100ll1l_dataout : STD_LOGIC; + SIGNAL wire_n100ll1O_dataout : STD_LOGIC; + SIGNAL wire_n100lli_dataout : STD_LOGIC; + SIGNAL wire_n100llii_dataout : STD_LOGIC; + SIGNAL wire_n100llil_dataout : STD_LOGIC; + SIGNAL wire_n100lliO_dataout : STD_LOGIC; + SIGNAL wire_n100lll_dataout : STD_LOGIC; + SIGNAL wire_n100llli_dataout : STD_LOGIC; + SIGNAL wire_n100llll_dataout : STD_LOGIC; + SIGNAL wire_n100lllO_dataout : STD_LOGIC; + SIGNAL wire_n100llO_dataout : STD_LOGIC; + SIGNAL wire_n100llOi_dataout : STD_LOGIC; + SIGNAL wire_n100llOl_dataout : STD_LOGIC; + SIGNAL wire_n100llOO_dataout : STD_LOGIC; + SIGNAL wire_n100lO0i_dataout : STD_LOGIC; + SIGNAL wire_n100lO0l_dataout : STD_LOGIC; + SIGNAL wire_n100lO0O_dataout : STD_LOGIC; + SIGNAL wire_n100lO1i_dataout : STD_LOGIC; + SIGNAL wire_n100lO1l_dataout : STD_LOGIC; + SIGNAL wire_n100lO1O_dataout : STD_LOGIC; + SIGNAL wire_n100lOi_dataout : STD_LOGIC; + SIGNAL wire_n100lOii_dataout : STD_LOGIC; + SIGNAL wire_n100lOil_dataout : STD_LOGIC; + SIGNAL wire_n100lOiO_dataout : STD_LOGIC; + SIGNAL wire_n100lOl_dataout : STD_LOGIC; + SIGNAL wire_n100lOli_dataout : STD_LOGIC; + SIGNAL wire_n100lOll_dataout : STD_LOGIC; + SIGNAL wire_n100lOlO_dataout : STD_LOGIC; + SIGNAL wire_n100lOO_dataout : STD_LOGIC; + SIGNAL wire_n100lOOi_dataout : STD_LOGIC; + SIGNAL wire_n100lOOl_dataout : STD_LOGIC; + SIGNAL wire_n100lOOO_dataout : STD_LOGIC; + SIGNAL wire_n100O00i_dataout : STD_LOGIC; + SIGNAL wire_n100O00l_dataout : STD_LOGIC; + SIGNAL wire_n100O00O_dataout : STD_LOGIC; + SIGNAL wire_n100O01i_dataout : STD_LOGIC; + SIGNAL wire_n100O01l_dataout : STD_LOGIC; + SIGNAL wire_n100O01O_dataout : STD_LOGIC; + SIGNAL wire_n100O0i_dataout : STD_LOGIC; + SIGNAL wire_n100O0ii_dataout : STD_LOGIC; + SIGNAL wire_n100O0il_dataout : STD_LOGIC; + SIGNAL wire_n100O0iO_dataout : STD_LOGIC; + SIGNAL wire_n100O0l_dataout : STD_LOGIC; + SIGNAL wire_n100O0li_dataout : STD_LOGIC; + SIGNAL wire_n100O0ll_dataout : STD_LOGIC; + SIGNAL wire_n100O0lO_dataout : STD_LOGIC; + SIGNAL wire_n100O0O_dataout : STD_LOGIC; + SIGNAL wire_n100O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n100O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n100O0OO_dataout : STD_LOGIC; + SIGNAL wire_n100O10i_dataout : STD_LOGIC; + SIGNAL wire_n100O10l_dataout : STD_LOGIC; + SIGNAL wire_n100O10O_dataout : STD_LOGIC; + SIGNAL wire_n100O11i_dataout : STD_LOGIC; + SIGNAL wire_n100O11l_dataout : STD_LOGIC; + SIGNAL wire_n100O11O_dataout : STD_LOGIC; + SIGNAL wire_n100O1i_dataout : STD_LOGIC; + SIGNAL wire_n100O1ii_dataout : STD_LOGIC; + SIGNAL wire_n100O1il_dataout : STD_LOGIC; + SIGNAL wire_n100O1iO_dataout : STD_LOGIC; + SIGNAL wire_n100O1l_dataout : STD_LOGIC; + SIGNAL wire_n100O1li_dataout : STD_LOGIC; + SIGNAL wire_n100O1ll_dataout : STD_LOGIC; + SIGNAL wire_n100O1lO_dataout : STD_LOGIC; + SIGNAL wire_n100O1O_dataout : STD_LOGIC; + SIGNAL wire_n100O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n100O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n100O1OO_dataout : STD_LOGIC; + SIGNAL wire_n100Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n100Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n100Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n100Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n100Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n100Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n100Oii_dataout : STD_LOGIC; + SIGNAL wire_n100Oiii_dataout : STD_LOGIC; + SIGNAL wire_n100Oiil_dataout : STD_LOGIC; + SIGNAL wire_n100OiiO_dataout : STD_LOGIC; + SIGNAL wire_n100Oil_dataout : STD_LOGIC; + SIGNAL wire_n100Oili_dataout : STD_LOGIC; + SIGNAL wire_n100Oill_dataout : STD_LOGIC; + SIGNAL wire_n100OilO_dataout : STD_LOGIC; + SIGNAL wire_n100OiO_dataout : STD_LOGIC; + SIGNAL wire_n100OiOi_dataout : STD_LOGIC; + SIGNAL wire_n100OiOl_dataout : STD_LOGIC; + SIGNAL wire_n100OiOO_dataout : STD_LOGIC; + SIGNAL wire_n100Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n100Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n100Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n100Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n100Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n100Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n100Oli_dataout : STD_LOGIC; + SIGNAL wire_n100Olii_dataout : STD_LOGIC; + SIGNAL wire_n100Olil_dataout : STD_LOGIC; + SIGNAL wire_n100OliO_dataout : STD_LOGIC; + SIGNAL wire_n100Oll_dataout : STD_LOGIC; + SIGNAL wire_n100Olli_dataout : STD_LOGIC; + SIGNAL wire_n100Olll_dataout : STD_LOGIC; + SIGNAL wire_n100OllO_dataout : STD_LOGIC; + SIGNAL wire_n100OlO_dataout : STD_LOGIC; + SIGNAL wire_n100OlOi_dataout : STD_LOGIC; + SIGNAL wire_n100OlOl_dataout : STD_LOGIC; + SIGNAL wire_n100OlOO_dataout : STD_LOGIC; + SIGNAL wire_n100OO0i_dataout : STD_LOGIC; + SIGNAL wire_n100OO0l_dataout : STD_LOGIC; + SIGNAL wire_n100OO0O_dataout : STD_LOGIC; + SIGNAL wire_n100OO1i_dataout : STD_LOGIC; + SIGNAL wire_n100OO1l_dataout : STD_LOGIC; + SIGNAL wire_n100OO1O_dataout : STD_LOGIC; + SIGNAL wire_n100OOi_dataout : STD_LOGIC; + SIGNAL wire_n100OOii_dataout : STD_LOGIC; + SIGNAL wire_n100OOil_dataout : STD_LOGIC; + SIGNAL wire_n100OOiO_dataout : STD_LOGIC; + SIGNAL wire_n100OOl_dataout : STD_LOGIC; + SIGNAL wire_n100OOli_dataout : STD_LOGIC; + SIGNAL wire_n100OOll_dataout : STD_LOGIC; + SIGNAL wire_n100OOlO_dataout : STD_LOGIC; + SIGNAL wire_n100OOO_dataout : STD_LOGIC; + SIGNAL wire_n100OOOi_dataout : STD_LOGIC; + SIGNAL wire_n100OOOl_dataout : STD_LOGIC; + SIGNAL wire_n100OOOO_dataout : STD_LOGIC; + SIGNAL wire_n101000i_dataout : STD_LOGIC; + SIGNAL wire_n101000l_dataout : STD_LOGIC; + SIGNAL wire_n101000O_dataout : STD_LOGIC; + SIGNAL wire_n101001i_dataout : STD_LOGIC; + SIGNAL wire_n101001l_dataout : STD_LOGIC; + SIGNAL wire_n101001O_dataout : STD_LOGIC; + SIGNAL wire_n10100i_dataout : STD_LOGIC; + SIGNAL wire_n10100ii_dataout : STD_LOGIC; + SIGNAL wire_n10100il_dataout : STD_LOGIC; + SIGNAL wire_n10100iO_dataout : STD_LOGIC; + SIGNAL wire_n10100l_dataout : STD_LOGIC; + SIGNAL wire_n10100li_dataout : STD_LOGIC; + SIGNAL wire_n10100ll_dataout : STD_LOGIC; + SIGNAL wire_n10100lO_dataout : STD_LOGIC; + SIGNAL wire_n10100O_dataout : STD_LOGIC; + SIGNAL wire_n10100Oi_dataout : STD_LOGIC; + SIGNAL wire_n10100Ol_dataout : STD_LOGIC; + SIGNAL wire_n10100OO_dataout : STD_LOGIC; + SIGNAL wire_n101010l_dataout : STD_LOGIC; + SIGNAL wire_n101010O_dataout : STD_LOGIC; + SIGNAL wire_n10101i_dataout : STD_LOGIC; + SIGNAL wire_n10101ii_dataout : STD_LOGIC; + SIGNAL wire_n10101il_dataout : STD_LOGIC; + SIGNAL wire_n10101iO_dataout : STD_LOGIC; + SIGNAL wire_n10101l_dataout : STD_LOGIC; + SIGNAL wire_n10101li_dataout : STD_LOGIC; + SIGNAL wire_n10101ll_dataout : STD_LOGIC; + SIGNAL wire_n10101lO_dataout : STD_LOGIC; + SIGNAL wire_n10101O_dataout : STD_LOGIC; + SIGNAL wire_n10101Oi_dataout : STD_LOGIC; + SIGNAL wire_n10101Ol_dataout : STD_LOGIC; + SIGNAL wire_n10101OO_dataout : STD_LOGIC; + SIGNAL wire_n1010i0i_dataout : STD_LOGIC; + SIGNAL wire_n1010i0l_dataout : STD_LOGIC; + SIGNAL wire_n1010i0O_dataout : STD_LOGIC; + SIGNAL wire_n1010i1i_dataout : STD_LOGIC; + SIGNAL wire_n1010i1l_dataout : STD_LOGIC; + SIGNAL wire_n1010i1O_dataout : STD_LOGIC; + SIGNAL wire_n1010ii_dataout : STD_LOGIC; + SIGNAL wire_n1010iii_dataout : STD_LOGIC; + SIGNAL wire_n1010iil_dataout : STD_LOGIC; + SIGNAL wire_n1010iiO_dataout : STD_LOGIC; + SIGNAL wire_n1010il_dataout : STD_LOGIC; + SIGNAL wire_n1010ili_dataout : STD_LOGIC; + SIGNAL wire_n1010ill_dataout : STD_LOGIC; + SIGNAL wire_n1010ilO_dataout : STD_LOGIC; + SIGNAL wire_n1010iO_dataout : STD_LOGIC; + SIGNAL wire_n1010iOi_dataout : STD_LOGIC; + SIGNAL wire_n1010iOl_dataout : STD_LOGIC; + SIGNAL wire_n1010iOO_dataout : STD_LOGIC; + SIGNAL wire_n1010l0i_dataout : STD_LOGIC; + SIGNAL wire_n1010l0l_dataout : STD_LOGIC; + SIGNAL wire_n1010l0O_dataout : STD_LOGIC; + SIGNAL wire_n1010l1i_dataout : STD_LOGIC; + SIGNAL wire_n1010l1l_dataout : STD_LOGIC; + SIGNAL wire_n1010l1O_dataout : STD_LOGIC; + SIGNAL wire_n1010li_dataout : STD_LOGIC; + SIGNAL wire_n1010lii_dataout : STD_LOGIC; + SIGNAL wire_n1010lil_dataout : STD_LOGIC; + SIGNAL wire_n1010liO_dataout : STD_LOGIC; + SIGNAL wire_n1010ll_dataout : STD_LOGIC; + SIGNAL wire_n1010lli_dataout : STD_LOGIC; + SIGNAL wire_n1010lO_dataout : STD_LOGIC; + SIGNAL wire_n1010lOl_dataout : STD_LOGIC; + SIGNAL wire_n1010lOO_dataout : STD_LOGIC; + SIGNAL wire_n1010O0i_dataout : STD_LOGIC; + SIGNAL wire_n1010O0l_dataout : STD_LOGIC; + SIGNAL wire_n1010O0O_dataout : STD_LOGIC; + SIGNAL wire_n1010O1i_dataout : STD_LOGIC; + SIGNAL wire_n1010O1l_dataout : STD_LOGIC; + SIGNAL wire_n1010O1O_dataout : STD_LOGIC; + SIGNAL wire_n1010Oi_dataout : STD_LOGIC; + SIGNAL wire_n1010Oii_dataout : STD_LOGIC; + SIGNAL wire_n1010Oil_dataout : STD_LOGIC; + SIGNAL wire_n1010OiO_dataout : STD_LOGIC; + SIGNAL wire_n1010Ol_dataout : STD_LOGIC; + SIGNAL wire_n1010Oli_dataout : STD_LOGIC; + SIGNAL wire_n1010Oll_dataout : STD_LOGIC; + SIGNAL wire_n1010OlO_dataout : STD_LOGIC; + SIGNAL wire_n1010OO_dataout : STD_LOGIC; + SIGNAL wire_n1010OOi_dataout : STD_LOGIC; + SIGNAL wire_n1010OOl_dataout : STD_LOGIC; + SIGNAL wire_n1010OOO_dataout : STD_LOGIC; + SIGNAL wire_n101100i_dataout : STD_LOGIC; + SIGNAL wire_n101100l_dataout : STD_LOGIC; + SIGNAL wire_n10110i_dataout : STD_LOGIC; + SIGNAL wire_n10110l_dataout : STD_LOGIC; + SIGNAL wire_n10110O_dataout : STD_LOGIC; + SIGNAL wire_n101110l_dataout : STD_LOGIC; + SIGNAL wire_n10111i_dataout : STD_LOGIC; + SIGNAL wire_n10111il_dataout : STD_LOGIC; + SIGNAL wire_n10111iO_dataout : STD_LOGIC; + SIGNAL wire_n10111l_dataout : STD_LOGIC; + SIGNAL wire_n10111O_dataout : STD_LOGIC; + SIGNAL wire_n1011ii_dataout : STD_LOGIC; + SIGNAL wire_n1011il_dataout : STD_LOGIC; + SIGNAL wire_n1011iO_dataout : STD_LOGIC; + SIGNAL wire_n1011li_dataout : STD_LOGIC; + SIGNAL wire_n1011ll_dataout : STD_LOGIC; + SIGNAL wire_n1011lO_dataout : STD_LOGIC; + SIGNAL wire_n1011Oi_dataout : STD_LOGIC; + SIGNAL wire_n1011Ol_dataout : STD_LOGIC; + SIGNAL wire_n1011OO_dataout : STD_LOGIC; + SIGNAL wire_n101i00i_dataout : STD_LOGIC; + SIGNAL wire_n101i00l_dataout : STD_LOGIC; + SIGNAL wire_n101i00O_dataout : STD_LOGIC; + SIGNAL wire_n101i01i_dataout : STD_LOGIC; + SIGNAL wire_n101i01l_dataout : STD_LOGIC; + SIGNAL wire_n101i01O_dataout : STD_LOGIC; + SIGNAL wire_n101i0i_dataout : STD_LOGIC; + SIGNAL wire_n101i0ii_dataout : STD_LOGIC; + SIGNAL wire_n101i0il_dataout : STD_LOGIC; + SIGNAL wire_n101i0iO_dataout : STD_LOGIC; + SIGNAL wire_n101i0l_dataout : STD_LOGIC; + SIGNAL wire_n101i0li_dataout : STD_LOGIC; + SIGNAL wire_n101i0ll_dataout : STD_LOGIC; + SIGNAL wire_n101i0lO_dataout : STD_LOGIC; + SIGNAL wire_n101i0O_dataout : STD_LOGIC; + SIGNAL wire_n101i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n101i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n101i0OO_dataout : STD_LOGIC; + SIGNAL wire_n101i10i_dataout : STD_LOGIC; + SIGNAL wire_n101i10l_dataout : STD_LOGIC; + SIGNAL wire_n101i10O_dataout : STD_LOGIC; + SIGNAL wire_n101i11i_dataout : STD_LOGIC; + SIGNAL wire_n101i11l_dataout : STD_LOGIC; + SIGNAL wire_n101i11O_dataout : STD_LOGIC; + SIGNAL wire_n101i1i_dataout : STD_LOGIC; + SIGNAL wire_n101i1ii_dataout : STD_LOGIC; + SIGNAL wire_n101i1il_dataout : STD_LOGIC; + SIGNAL wire_n101i1iO_dataout : STD_LOGIC; + SIGNAL wire_n101i1l_dataout : STD_LOGIC; + SIGNAL wire_n101i1li_dataout : STD_LOGIC; + SIGNAL wire_n101i1ll_dataout : STD_LOGIC; + SIGNAL wire_n101i1lO_dataout : STD_LOGIC; + SIGNAL wire_n101i1O_dataout : STD_LOGIC; + SIGNAL wire_n101i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n101i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n101i1OO_dataout : STD_LOGIC; + SIGNAL wire_n101ii0i_dataout : STD_LOGIC; + SIGNAL wire_n101ii0l_dataout : STD_LOGIC; + SIGNAL wire_n101ii0O_dataout : STD_LOGIC; + SIGNAL wire_n101ii1i_dataout : STD_LOGIC; + SIGNAL wire_n101ii1l_dataout : STD_LOGIC; + SIGNAL wire_n101ii1O_dataout : STD_LOGIC; + SIGNAL wire_n101iii_dataout : STD_LOGIC; + SIGNAL wire_n101iiii_dataout : STD_LOGIC; + SIGNAL wire_n101iiil_dataout : STD_LOGIC; + SIGNAL wire_n101iiiO_dataout : STD_LOGIC; + SIGNAL wire_n101iil_dataout : STD_LOGIC; + SIGNAL wire_n101iili_dataout : STD_LOGIC; + SIGNAL wire_n101iill_dataout : STD_LOGIC; + SIGNAL wire_n101iilO_dataout : STD_LOGIC; + SIGNAL wire_n101iiO_dataout : STD_LOGIC; + SIGNAL wire_n101iiOi_dataout : STD_LOGIC; + SIGNAL wire_n101iiOl_dataout : STD_LOGIC; + SIGNAL wire_n101iiOO_dataout : STD_LOGIC; + SIGNAL wire_n101il0i_dataout : STD_LOGIC; + SIGNAL wire_n101il0l_dataout : STD_LOGIC; + SIGNAL wire_n101il0O_dataout : STD_LOGIC; + SIGNAL wire_n101il1i_dataout : STD_LOGIC; + SIGNAL wire_n101il1l_dataout : STD_LOGIC; + SIGNAL wire_n101il1O_dataout : STD_LOGIC; + SIGNAL wire_n101ili_dataout : STD_LOGIC; + SIGNAL wire_n101ilii_dataout : STD_LOGIC; + SIGNAL wire_n101ilil_dataout : STD_LOGIC; + SIGNAL wire_n101iliO_dataout : STD_LOGIC; + SIGNAL wire_n101ill_dataout : STD_LOGIC; + SIGNAL wire_n101illi_dataout : STD_LOGIC; + SIGNAL wire_n101illl_dataout : STD_LOGIC; + SIGNAL wire_n101illO_dataout : STD_LOGIC; + SIGNAL wire_n101ilO_dataout : STD_LOGIC; + SIGNAL wire_n101ilOi_dataout : STD_LOGIC; + SIGNAL wire_n101iO0i_dataout : STD_LOGIC; + SIGNAL wire_n101iO0l_dataout : STD_LOGIC; + SIGNAL wire_n101iO0O_dataout : STD_LOGIC; + SIGNAL wire_n101iO1l_dataout : STD_LOGIC; + SIGNAL wire_n101iO1O_dataout : STD_LOGIC; + SIGNAL wire_n101iOi_dataout : STD_LOGIC; + SIGNAL wire_n101iOii_dataout : STD_LOGIC; + SIGNAL wire_n101iOil_dataout : STD_LOGIC; + SIGNAL wire_n101iOiO_dataout : STD_LOGIC; + SIGNAL wire_n101iOl_dataout : STD_LOGIC; + SIGNAL wire_n101iOli_dataout : STD_LOGIC; + SIGNAL wire_n101iOll_dataout : STD_LOGIC; + SIGNAL wire_n101iOlO_dataout : STD_LOGIC; + SIGNAL wire_n101iOO_dataout : STD_LOGIC; + SIGNAL wire_n101iOOi_dataout : STD_LOGIC; + SIGNAL wire_n101iOOl_dataout : STD_LOGIC; + SIGNAL wire_n101iOOO_dataout : STD_LOGIC; + SIGNAL wire_n101l00i_dataout : STD_LOGIC; + SIGNAL wire_n101l01O_dataout : STD_LOGIC; + SIGNAL wire_n101l0i_dataout : STD_LOGIC; + SIGNAL wire_n101l0il_dataout : STD_LOGIC; + SIGNAL wire_n101l0iO_dataout : STD_LOGIC; + SIGNAL wire_n101l0l_dataout : STD_LOGIC; + SIGNAL wire_n101l0li_dataout : STD_LOGIC; + SIGNAL wire_n101l0ll_dataout : STD_LOGIC; + SIGNAL wire_n101l0lO_dataout : STD_LOGIC; + SIGNAL wire_n101l0O_dataout : STD_LOGIC; + SIGNAL wire_n101l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n101l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n101l0OO_dataout : STD_LOGIC; + SIGNAL wire_n101l10i_dataout : STD_LOGIC; + SIGNAL wire_n101l10l_dataout : STD_LOGIC; + SIGNAL wire_n101l10O_dataout : STD_LOGIC; + SIGNAL wire_n101l11i_dataout : STD_LOGIC; + SIGNAL wire_n101l11l_dataout : STD_LOGIC; + SIGNAL wire_n101l11O_dataout : STD_LOGIC; + SIGNAL wire_n101l1i_dataout : STD_LOGIC; + SIGNAL wire_n101l1ii_dataout : STD_LOGIC; + SIGNAL wire_n101l1il_dataout : STD_LOGIC; + SIGNAL wire_n101l1iO_dataout : STD_LOGIC; + SIGNAL wire_n101l1l_dataout : STD_LOGIC; + SIGNAL wire_n101l1li_dataout : STD_LOGIC; + SIGNAL wire_n101l1ll_dataout : STD_LOGIC; + SIGNAL wire_n101l1lO_dataout : STD_LOGIC; + SIGNAL wire_n101l1O_dataout : STD_LOGIC; + SIGNAL wire_n101l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n101l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n101l1OO_dataout : STD_LOGIC; + SIGNAL wire_n101li0i_dataout : STD_LOGIC; + SIGNAL wire_n101li0l_dataout : STD_LOGIC; + SIGNAL wire_n101li0O_dataout : STD_LOGIC; + SIGNAL wire_n101li1i_dataout : STD_LOGIC; + SIGNAL wire_n101li1l_dataout : STD_LOGIC; + SIGNAL wire_n101li1O_dataout : STD_LOGIC; + SIGNAL wire_n101lii_dataout : STD_LOGIC; + SIGNAL wire_n101liii_dataout : STD_LOGIC; + SIGNAL wire_n101liil_dataout : STD_LOGIC; + SIGNAL wire_n101liiO_dataout : STD_LOGIC; + SIGNAL wire_n101lil_dataout : STD_LOGIC; + SIGNAL wire_n101lili_dataout : STD_LOGIC; + SIGNAL wire_n101lill_dataout : STD_LOGIC; + SIGNAL wire_n101lilO_dataout : STD_LOGIC; + SIGNAL wire_n101liO_dataout : STD_LOGIC; + SIGNAL wire_n101liOi_dataout : STD_LOGIC; + SIGNAL wire_n101liOl_dataout : STD_LOGIC; + SIGNAL wire_n101liOO_dataout : STD_LOGIC; + SIGNAL wire_n101ll0i_dataout : STD_LOGIC; + SIGNAL wire_n101ll0l_dataout : STD_LOGIC; + SIGNAL wire_n101ll0O_dataout : STD_LOGIC; + SIGNAL wire_n101ll1i_dataout : STD_LOGIC; + SIGNAL wire_n101ll1l_dataout : STD_LOGIC; + SIGNAL wire_n101ll1O_dataout : STD_LOGIC; + SIGNAL wire_n101lli_dataout : STD_LOGIC; + SIGNAL wire_n101llii_dataout : STD_LOGIC; + SIGNAL wire_n101llil_dataout : STD_LOGIC; + SIGNAL wire_n101lliO_dataout : STD_LOGIC; + SIGNAL wire_n101lll_dataout : STD_LOGIC; + SIGNAL wire_n101llli_dataout : STD_LOGIC; + SIGNAL wire_n101llll_dataout : STD_LOGIC; + SIGNAL wire_n101lllO_dataout : STD_LOGIC; + SIGNAL wire_n101llO_dataout : STD_LOGIC; + SIGNAL wire_n101llOi_dataout : STD_LOGIC; + SIGNAL wire_n101llOl_dataout : STD_LOGIC; + SIGNAL wire_n101llOO_dataout : STD_LOGIC; + SIGNAL wire_n101lO0i_dataout : STD_LOGIC; + SIGNAL wire_n101lO0l_dataout : STD_LOGIC; + SIGNAL wire_n101lO0O_dataout : STD_LOGIC; + SIGNAL wire_n101lO1i_dataout : STD_LOGIC; + SIGNAL wire_n101lO1l_dataout : STD_LOGIC; + SIGNAL wire_n101lO1O_dataout : STD_LOGIC; + SIGNAL wire_n101lOi_dataout : STD_LOGIC; + SIGNAL wire_n101lOii_dataout : STD_LOGIC; + SIGNAL wire_n101lOil_dataout : STD_LOGIC; + SIGNAL wire_n101lOiO_dataout : STD_LOGIC; + SIGNAL wire_n101lOl_dataout : STD_LOGIC; + SIGNAL wire_n101lOli_dataout : STD_LOGIC; + SIGNAL wire_n101lOll_dataout : STD_LOGIC; + SIGNAL wire_n101lOlO_dataout : STD_LOGIC; + SIGNAL wire_n101lOO_dataout : STD_LOGIC; + SIGNAL wire_n101lOOi_dataout : STD_LOGIC; + SIGNAL wire_n101lOOl_dataout : STD_LOGIC; + SIGNAL wire_n101lOOO_dataout : STD_LOGIC; + SIGNAL wire_n101O00i_dataout : STD_LOGIC; + SIGNAL wire_n101O00l_dataout : STD_LOGIC; + SIGNAL wire_n101O00O_dataout : STD_LOGIC; + SIGNAL wire_n101O01i_dataout : STD_LOGIC; + SIGNAL wire_n101O01l_dataout : STD_LOGIC; + SIGNAL wire_n101O01O_dataout : STD_LOGIC; + SIGNAL wire_n101O0i_dataout : STD_LOGIC; + SIGNAL wire_n101O0ii_dataout : STD_LOGIC; + SIGNAL wire_n101O0il_dataout : STD_LOGIC; + SIGNAL wire_n101O0l_dataout : STD_LOGIC; + SIGNAL wire_n101O0O_dataout : STD_LOGIC; + SIGNAL wire_n101O10i_dataout : STD_LOGIC; + SIGNAL wire_n101O10l_dataout : STD_LOGIC; + SIGNAL wire_n101O10O_dataout : STD_LOGIC; + SIGNAL wire_n101O11i_dataout : STD_LOGIC; + SIGNAL wire_n101O11l_dataout : STD_LOGIC; + SIGNAL wire_n101O11O_dataout : STD_LOGIC; + SIGNAL wire_n101O1i_dataout : STD_LOGIC; + SIGNAL wire_n101O1ii_dataout : STD_LOGIC; + SIGNAL wire_n101O1il_dataout : STD_LOGIC; + SIGNAL wire_n101O1iO_dataout : STD_LOGIC; + SIGNAL wire_n101O1l_dataout : STD_LOGIC; + SIGNAL wire_n101O1li_dataout : STD_LOGIC; + SIGNAL wire_n101O1ll_dataout : STD_LOGIC; + SIGNAL wire_n101O1lO_dataout : STD_LOGIC; + SIGNAL wire_n101O1O_dataout : STD_LOGIC; + SIGNAL wire_n101O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n101O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n101O1OO_dataout : STD_LOGIC; + SIGNAL wire_n101Oii_dataout : STD_LOGIC; + SIGNAL wire_n101Oil_dataout : STD_LOGIC; + SIGNAL wire_n101OilO_dataout : STD_LOGIC; + SIGNAL wire_n101OiO_dataout : STD_LOGIC; + SIGNAL wire_n101OiOi_dataout : STD_LOGIC; + SIGNAL wire_n101OiOl_dataout : STD_LOGIC; + SIGNAL wire_n101OiOO_dataout : STD_LOGIC; + SIGNAL wire_n101Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n101Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n101Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n101Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n101Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n101Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n101Oli_dataout : STD_LOGIC; + SIGNAL wire_n101Olii_dataout : STD_LOGIC; + SIGNAL wire_n101Olil_dataout : STD_LOGIC; + SIGNAL wire_n101OliO_dataout : STD_LOGIC; + SIGNAL wire_n101Oll_dataout : STD_LOGIC; + SIGNAL wire_n101Olli_dataout : STD_LOGIC; + SIGNAL wire_n101Olll_dataout : STD_LOGIC; + SIGNAL wire_n101OllO_dataout : STD_LOGIC; + SIGNAL wire_n101OlO_dataout : STD_LOGIC; + SIGNAL wire_n101OlOi_dataout : STD_LOGIC; + SIGNAL wire_n101OlOl_dataout : STD_LOGIC; + SIGNAL wire_n101OlOO_dataout : STD_LOGIC; + SIGNAL wire_n101OO0i_dataout : STD_LOGIC; + SIGNAL wire_n101OO0l_dataout : STD_LOGIC; + SIGNAL wire_n101OO0O_dataout : STD_LOGIC; + SIGNAL wire_n101OO1i_dataout : STD_LOGIC; + SIGNAL wire_n101OO1l_dataout : STD_LOGIC; + SIGNAL wire_n101OO1O_dataout : STD_LOGIC; + SIGNAL wire_n101OOi_dataout : STD_LOGIC; + SIGNAL wire_n101OOii_dataout : STD_LOGIC; + SIGNAL wire_n101OOil_dataout : STD_LOGIC; + SIGNAL wire_n101OOiO_dataout : STD_LOGIC; + SIGNAL wire_n101OOl_dataout : STD_LOGIC; + SIGNAL wire_n101OOli_dataout : STD_LOGIC; + SIGNAL wire_n101OOll_dataout : STD_LOGIC; + SIGNAL wire_n101OOlO_dataout : STD_LOGIC; + SIGNAL wire_n101OOO_dataout : STD_LOGIC; + SIGNAL wire_n101OOOi_dataout : STD_LOGIC; + SIGNAL wire_n101OOOl_dataout : STD_LOGIC; + SIGNAL wire_n101OOOO_dataout : STD_LOGIC; + SIGNAL wire_n10i000i_dataout : STD_LOGIC; + SIGNAL wire_n10i000l_dataout : STD_LOGIC; + SIGNAL wire_n10i000O_dataout : STD_LOGIC; + SIGNAL wire_n10i001i_dataout : STD_LOGIC; + SIGNAL wire_n10i001l_dataout : STD_LOGIC; + SIGNAL wire_n10i001O_dataout : STD_LOGIC; + SIGNAL wire_n10i00i_dataout : STD_LOGIC; + SIGNAL wire_n10i00ii_dataout : STD_LOGIC; + SIGNAL wire_n10i00il_dataout : STD_LOGIC; + SIGNAL wire_n10i00iO_dataout : STD_LOGIC; + SIGNAL wire_n10i00l_dataout : STD_LOGIC; + SIGNAL wire_n10i00li_dataout : STD_LOGIC; + SIGNAL wire_n10i00ll_dataout : STD_LOGIC; + SIGNAL wire_n10i00lO_dataout : STD_LOGIC; + SIGNAL wire_n10i00O_dataout : STD_LOGIC; + SIGNAL wire_n10i010i_dataout : STD_LOGIC; + SIGNAL wire_n10i010l_dataout : STD_LOGIC; + SIGNAL wire_n10i010O_dataout : STD_LOGIC; + SIGNAL wire_n10i011i_dataout : STD_LOGIC; + SIGNAL wire_n10i011l_dataout : STD_LOGIC; + SIGNAL wire_n10i011O_dataout : STD_LOGIC; + SIGNAL wire_n10i01i_dataout : STD_LOGIC; + SIGNAL wire_n10i01ii_dataout : STD_LOGIC; + SIGNAL wire_n10i01il_dataout : STD_LOGIC; + SIGNAL wire_n10i01iO_dataout : STD_LOGIC; + SIGNAL wire_n10i01l_dataout : STD_LOGIC; + SIGNAL wire_n10i01li_dataout : STD_LOGIC; + SIGNAL wire_n10i01ll_dataout : STD_LOGIC; + SIGNAL wire_n10i01lO_dataout : STD_LOGIC; + SIGNAL wire_n10i01O_dataout : STD_LOGIC; + SIGNAL wire_n10i01Oi_dataout : STD_LOGIC; + SIGNAL wire_n10i01Ol_dataout : STD_LOGIC; + SIGNAL wire_n10i01OO_dataout : STD_LOGIC; + SIGNAL wire_n10i0ii_dataout : STD_LOGIC; + SIGNAL wire_n10i0iiO_dataout : STD_LOGIC; + SIGNAL wire_n10i0il_dataout : STD_LOGIC; + SIGNAL wire_n10i0ili_dataout : STD_LOGIC; + SIGNAL wire_n10i0ill_dataout : STD_LOGIC; + SIGNAL wire_n10i0ilO_dataout : STD_LOGIC; + SIGNAL wire_n10i0iO_dataout : STD_LOGIC; + SIGNAL wire_n10i0iOi_dataout : STD_LOGIC; + SIGNAL wire_n10i0iOl_dataout : STD_LOGIC; + SIGNAL wire_n10i0iOO_dataout : STD_LOGIC; + SIGNAL wire_n10i0l0i_dataout : STD_LOGIC; + SIGNAL wire_n10i0l0l_dataout : STD_LOGIC; + SIGNAL wire_n10i0l0O_dataout : STD_LOGIC; + SIGNAL wire_n10i0l1i_dataout : STD_LOGIC; + SIGNAL wire_n10i0l1l_dataout : STD_LOGIC; + SIGNAL wire_n10i0l1O_dataout : STD_LOGIC; + SIGNAL wire_n10i0li_dataout : STD_LOGIC; + SIGNAL wire_n10i0lii_dataout : STD_LOGIC; + SIGNAL wire_n10i0lil_dataout : STD_LOGIC; + SIGNAL wire_n10i0liO_dataout : STD_LOGIC; + SIGNAL wire_n10i0ll_dataout : STD_LOGIC; + SIGNAL wire_n10i0lli_dataout : STD_LOGIC; + SIGNAL wire_n10i0lll_dataout : STD_LOGIC; + SIGNAL wire_n10i0llO_dataout : STD_LOGIC; + SIGNAL wire_n10i0lO_dataout : STD_LOGIC; + SIGNAL wire_n10i0lOi_dataout : STD_LOGIC; + SIGNAL wire_n10i0lOl_dataout : STD_LOGIC; + SIGNAL wire_n10i0lOO_dataout : STD_LOGIC; + SIGNAL wire_n10i0O0i_dataout : STD_LOGIC; + SIGNAL wire_n10i0O0l_dataout : STD_LOGIC; + SIGNAL wire_n10i0O0O_dataout : STD_LOGIC; + SIGNAL wire_n10i0O1i_dataout : STD_LOGIC; + SIGNAL wire_n10i0O1l_dataout : STD_LOGIC; + SIGNAL wire_n10i0O1O_dataout : STD_LOGIC; + SIGNAL wire_n10i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10i0Oii_dataout : STD_LOGIC; + SIGNAL wire_n10i0Oil_dataout : STD_LOGIC; + SIGNAL wire_n10i0OiO_dataout : STD_LOGIC; + SIGNAL wire_n10i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10i0Oli_dataout : STD_LOGIC; + SIGNAL wire_n10i0Oll_dataout : STD_LOGIC; + SIGNAL wire_n10i0OlO_dataout : STD_LOGIC; + SIGNAL wire_n10i0OO_dataout : STD_LOGIC; + SIGNAL wire_n10i0OOi_dataout : STD_LOGIC; + SIGNAL wire_n10i0OOl_dataout : STD_LOGIC; + SIGNAL wire_n10i0OOO_dataout : STD_LOGIC; + SIGNAL wire_n10i10i_dataout : STD_LOGIC; + SIGNAL wire_n10i10l_dataout : STD_LOGIC; + SIGNAL wire_n10i10O_dataout : STD_LOGIC; + SIGNAL wire_n10i110i_dataout : STD_LOGIC; + SIGNAL wire_n10i110l_dataout : STD_LOGIC; + SIGNAL wire_n10i110O_dataout : STD_LOGIC; + SIGNAL wire_n10i111i_dataout : STD_LOGIC; + SIGNAL wire_n10i111l_dataout : STD_LOGIC; + SIGNAL wire_n10i111O_dataout : STD_LOGIC; + SIGNAL wire_n10i11i_dataout : STD_LOGIC; + SIGNAL wire_n10i11ii_dataout : STD_LOGIC; + SIGNAL wire_n10i11il_dataout : STD_LOGIC; + SIGNAL wire_n10i11iO_dataout : STD_LOGIC; + SIGNAL wire_n10i11l_dataout : STD_LOGIC; + SIGNAL wire_n10i11li_dataout : STD_LOGIC; + SIGNAL wire_n10i11ll_dataout : STD_LOGIC; + SIGNAL wire_n10i11lO_dataout : STD_LOGIC; + SIGNAL wire_n10i11O_dataout : STD_LOGIC; + SIGNAL wire_n10i11Ol_dataout : STD_LOGIC; + SIGNAL wire_n10i1ii_dataout : STD_LOGIC; + SIGNAL wire_n10i1il_dataout : STD_LOGIC; + SIGNAL wire_n10i1iO_dataout : STD_LOGIC; + SIGNAL wire_n10i1li_dataout : STD_LOGIC; + SIGNAL wire_n10i1ll_dataout : STD_LOGIC; + SIGNAL wire_n10i1lO_dataout : STD_LOGIC; + SIGNAL wire_n10i1O0O_dataout : STD_LOGIC; + SIGNAL wire_n10i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10i1Oii_dataout : STD_LOGIC; + SIGNAL wire_n10i1Oil_dataout : STD_LOGIC; + SIGNAL wire_n10i1OiO_dataout : STD_LOGIC; + SIGNAL wire_n10i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10i1Oli_dataout : STD_LOGIC; + SIGNAL wire_n10i1Oll_dataout : STD_LOGIC; + SIGNAL wire_n10i1OlO_dataout : STD_LOGIC; + SIGNAL wire_n10i1OO_dataout : STD_LOGIC; + SIGNAL wire_n10i1OOi_dataout : STD_LOGIC; + SIGNAL wire_n10i1OOl_dataout : STD_LOGIC; + SIGNAL wire_n10i1OOO_dataout : STD_LOGIC; + SIGNAL wire_n10ii00i_dataout : STD_LOGIC; + SIGNAL wire_n10ii00l_dataout : STD_LOGIC; + SIGNAL wire_n10ii00O_dataout : STD_LOGIC; + SIGNAL wire_n10ii01i_dataout : STD_LOGIC; + SIGNAL wire_n10ii01l_dataout : STD_LOGIC; + SIGNAL wire_n10ii01O_dataout : STD_LOGIC; + SIGNAL wire_n10ii0i_dataout : STD_LOGIC; + SIGNAL wire_n10ii0ii_dataout : STD_LOGIC; + SIGNAL wire_n10ii0il_dataout : STD_LOGIC; + SIGNAL wire_n10ii0iO_dataout : STD_LOGIC; + SIGNAL wire_n10ii0l_dataout : STD_LOGIC; + SIGNAL wire_n10ii0li_dataout : STD_LOGIC; + SIGNAL wire_n10ii0ll_dataout : STD_LOGIC; + SIGNAL wire_n10ii0lO_dataout : STD_LOGIC; + SIGNAL wire_n10ii0O_dataout : STD_LOGIC; + SIGNAL wire_n10ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10ii0OO_dataout : STD_LOGIC; + SIGNAL wire_n10ii10i_dataout : STD_LOGIC; + SIGNAL wire_n10ii10l_dataout : STD_LOGIC; + SIGNAL wire_n10ii10O_dataout : STD_LOGIC; + SIGNAL wire_n10ii11i_dataout : STD_LOGIC; + SIGNAL wire_n10ii11l_dataout : STD_LOGIC; + SIGNAL wire_n10ii11O_dataout : STD_LOGIC; + SIGNAL wire_n10ii1i_dataout : STD_LOGIC; + SIGNAL wire_n10ii1ii_dataout : STD_LOGIC; + SIGNAL wire_n10ii1il_dataout : STD_LOGIC; + SIGNAL wire_n10ii1iO_dataout : STD_LOGIC; + SIGNAL wire_n10ii1l_dataout : STD_LOGIC; + SIGNAL wire_n10ii1li_dataout : STD_LOGIC; + SIGNAL wire_n10ii1ll_dataout : STD_LOGIC; + SIGNAL wire_n10ii1lO_dataout : STD_LOGIC; + SIGNAL wire_n10ii1O_dataout : STD_LOGIC; + SIGNAL wire_n10ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10ii1OO_dataout : STD_LOGIC; + SIGNAL wire_n10iii0i_dataout : STD_LOGIC; + SIGNAL wire_n10iii0l_dataout : STD_LOGIC; + SIGNAL wire_n10iii0O_dataout : STD_LOGIC; + SIGNAL wire_n10iii1i_dataout : STD_LOGIC; + SIGNAL wire_n10iii1l_dataout : STD_LOGIC; + SIGNAL wire_n10iii1O_dataout : STD_LOGIC; + SIGNAL wire_n10iiii_dataout : STD_LOGIC; + SIGNAL wire_n10iiiii_dataout : STD_LOGIC; + SIGNAL wire_n10iiiil_dataout : STD_LOGIC; + SIGNAL wire_n10iiiiO_dataout : STD_LOGIC; + SIGNAL wire_n10iiil_dataout : STD_LOGIC; + SIGNAL wire_n10iiili_dataout : STD_LOGIC; + SIGNAL wire_n10iiill_dataout : STD_LOGIC; + SIGNAL wire_n10iiilO_dataout : STD_LOGIC; + SIGNAL wire_n10iiiO_dataout : STD_LOGIC; + SIGNAL wire_n10iiiOi_dataout : STD_LOGIC; + SIGNAL wire_n10iiiOl_dataout : STD_LOGIC; + SIGNAL wire_n10iiiOO_dataout : STD_LOGIC; + SIGNAL wire_n10iil0i_dataout : STD_LOGIC; + SIGNAL wire_n10iil0l_dataout : STD_LOGIC; + SIGNAL wire_n10iil0O_dataout : STD_LOGIC; + SIGNAL wire_n10iil1i_dataout : STD_LOGIC; + SIGNAL wire_n10iil1l_dataout : STD_LOGIC; + SIGNAL wire_n10iil1O_dataout : STD_LOGIC; + SIGNAL wire_n10iili_dataout : STD_LOGIC; + SIGNAL wire_n10iilii_dataout : STD_LOGIC; + SIGNAL wire_n10iilil_dataout : STD_LOGIC; + SIGNAL wire_n10iiliO_dataout : STD_LOGIC; + SIGNAL wire_n10iill_dataout : STD_LOGIC; + SIGNAL wire_n10iilli_dataout : STD_LOGIC; + SIGNAL wire_n10iilll_dataout : STD_LOGIC; + SIGNAL wire_n10iillO_dataout : STD_LOGIC; + SIGNAL wire_n10iilO_dataout : STD_LOGIC; + SIGNAL wire_n10iilOi_dataout : STD_LOGIC; + SIGNAL wire_n10iilOl_dataout : STD_LOGIC; + SIGNAL wire_n10iilOO_dataout : STD_LOGIC; + SIGNAL wire_n10iiO0i_dataout : STD_LOGIC; + SIGNAL wire_n10iiO0l_dataout : STD_LOGIC; + SIGNAL wire_n10iiO0O_dataout : STD_LOGIC; + SIGNAL wire_n10iiO1i_dataout : STD_LOGIC; + SIGNAL wire_n10iiO1l_dataout : STD_LOGIC; + SIGNAL wire_n10iiO1O_dataout : STD_LOGIC; + SIGNAL wire_n10iiOi_dataout : STD_LOGIC; + SIGNAL wire_n10iiOii_dataout : STD_LOGIC; + SIGNAL wire_n10iiOil_dataout : STD_LOGIC; + SIGNAL wire_n10iiOiO_dataout : STD_LOGIC; + SIGNAL wire_n10iiOl_dataout : STD_LOGIC; + SIGNAL wire_n10iiOli_dataout : STD_LOGIC; + SIGNAL wire_n10iiOll_dataout : STD_LOGIC; + SIGNAL wire_n10iiOlO_dataout : STD_LOGIC; + SIGNAL wire_n10iiOO_dataout : STD_LOGIC; + SIGNAL wire_n10iiOOi_dataout : STD_LOGIC; + SIGNAL wire_n10iiOOl_dataout : STD_LOGIC; + SIGNAL wire_n10iiOOO_dataout : STD_LOGIC; + SIGNAL wire_n10il00i_dataout : STD_LOGIC; + SIGNAL wire_n10il00l_dataout : STD_LOGIC; + SIGNAL wire_n10il00O_dataout : STD_LOGIC; + SIGNAL wire_n10il01i_dataout : STD_LOGIC; + SIGNAL wire_n10il01l_dataout : STD_LOGIC; + SIGNAL wire_n10il01O_dataout : STD_LOGIC; + SIGNAL wire_n10il0i_dataout : STD_LOGIC; + SIGNAL wire_n10il0ii_dataout : STD_LOGIC; + SIGNAL wire_n10il0il_dataout : STD_LOGIC; + SIGNAL wire_n10il0iO_dataout : STD_LOGIC; + SIGNAL wire_n10il0l_dataout : STD_LOGIC; + SIGNAL wire_n10il0li_dataout : STD_LOGIC; + SIGNAL wire_n10il0ll_dataout : STD_LOGIC; + SIGNAL wire_n10il0lO_dataout : STD_LOGIC; + SIGNAL wire_n10il0O_dataout : STD_LOGIC; + SIGNAL wire_n10il0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10il0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10il0OO_dataout : STD_LOGIC; + SIGNAL wire_n10il10i_dataout : STD_LOGIC; + SIGNAL wire_n10il10l_dataout : STD_LOGIC; + SIGNAL wire_n10il10O_dataout : STD_LOGIC; + SIGNAL wire_n10il11i_dataout : STD_LOGIC; + SIGNAL wire_n10il11l_dataout : STD_LOGIC; + SIGNAL wire_n10il11O_dataout : STD_LOGIC; + SIGNAL wire_n10il1i_dataout : STD_LOGIC; + SIGNAL wire_n10il1ii_dataout : STD_LOGIC; + SIGNAL wire_n10il1il_dataout : STD_LOGIC; + SIGNAL wire_n10il1iO_dataout : STD_LOGIC; + SIGNAL wire_n10il1l_dataout : STD_LOGIC; + SIGNAL wire_n10il1li_dataout : STD_LOGIC; + SIGNAL wire_n10il1ll_dataout : STD_LOGIC; + SIGNAL wire_n10il1lO_dataout : STD_LOGIC; + SIGNAL wire_n10il1O_dataout : STD_LOGIC; + SIGNAL wire_n10il1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10il1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10il1OO_dataout : STD_LOGIC; + SIGNAL wire_n10ili0i_dataout : STD_LOGIC; + SIGNAL wire_n10ili0l_dataout : STD_LOGIC; + SIGNAL wire_n10ili0O_dataout : STD_LOGIC; + SIGNAL wire_n10ili1i_dataout : STD_LOGIC; + SIGNAL wire_n10ili1l_dataout : STD_LOGIC; + SIGNAL wire_n10ili1O_dataout : STD_LOGIC; + SIGNAL wire_n10ilii_dataout : STD_LOGIC; + SIGNAL wire_n10iliii_dataout : STD_LOGIC; + SIGNAL wire_n10iliil_dataout : STD_LOGIC; + SIGNAL wire_n10iliiO_dataout : STD_LOGIC; + SIGNAL wire_n10ilil_dataout : STD_LOGIC; + SIGNAL wire_n10ilili_dataout : STD_LOGIC; + SIGNAL wire_n10ilill_dataout : STD_LOGIC; + SIGNAL wire_n10ililO_dataout : STD_LOGIC; + SIGNAL wire_n10iliO_dataout : STD_LOGIC; + SIGNAL wire_n10iliOi_dataout : STD_LOGIC; + SIGNAL wire_n10iliOl_dataout : STD_LOGIC; + SIGNAL wire_n10iliOO_dataout : STD_LOGIC; + SIGNAL wire_n10ill1i_dataout : STD_LOGIC; + SIGNAL wire_n10ill1l_dataout : STD_LOGIC; + SIGNAL wire_n10illi_dataout : STD_LOGIC; + SIGNAL wire_n10illl_dataout : STD_LOGIC; + SIGNAL wire_n10illO_dataout : STD_LOGIC; + SIGNAL wire_n10ilOi_dataout : STD_LOGIC; + SIGNAL wire_n10ilOl_dataout : STD_LOGIC; + SIGNAL wire_n10ilOO_dataout : STD_LOGIC; + SIGNAL wire_n10iO00i_dataout : STD_LOGIC; + SIGNAL wire_n10iO00l_dataout : STD_LOGIC; + SIGNAL wire_n10iO00O_dataout : STD_LOGIC; + SIGNAL wire_n10iO01i_dataout : STD_LOGIC; + SIGNAL wire_n10iO01l_dataout : STD_LOGIC; + SIGNAL wire_n10iO01O_dataout : STD_LOGIC; + SIGNAL wire_n10iO0i_dataout : STD_LOGIC; + SIGNAL wire_n10iO0ii_dataout : STD_LOGIC; + SIGNAL wire_n10iO0il_dataout : STD_LOGIC; + SIGNAL wire_n10iO0iO_dataout : STD_LOGIC; + SIGNAL wire_n10iO0l_dataout : STD_LOGIC; + SIGNAL wire_n10iO0li_dataout : STD_LOGIC; + SIGNAL wire_n10iO0ll_dataout : STD_LOGIC; + SIGNAL wire_n10iO0lO_dataout : STD_LOGIC; + SIGNAL wire_n10iO0O_dataout : STD_LOGIC; + SIGNAL wire_n10iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10iO0OO_dataout : STD_LOGIC; + SIGNAL wire_n10iO10i_dataout : STD_LOGIC; + SIGNAL wire_n10iO10l_dataout : STD_LOGIC; + SIGNAL wire_n10iO10O_dataout : STD_LOGIC; + SIGNAL wire_n10iO11i_dataout : STD_LOGIC; + SIGNAL wire_n10iO11l_dataout : STD_LOGIC; + SIGNAL wire_n10iO11O_dataout : STD_LOGIC; + SIGNAL wire_n10iO1i_dataout : STD_LOGIC; + SIGNAL wire_n10iO1ii_dataout : STD_LOGIC; + SIGNAL wire_n10iO1il_dataout : STD_LOGIC; + SIGNAL wire_n10iO1iO_dataout : STD_LOGIC; + SIGNAL wire_n10iO1l_dataout : STD_LOGIC; + SIGNAL wire_n10iO1li_dataout : STD_LOGIC; + SIGNAL wire_n10iO1ll_dataout : STD_LOGIC; + SIGNAL wire_n10iO1lO_dataout : STD_LOGIC; + SIGNAL wire_n10iO1O_dataout : STD_LOGIC; + SIGNAL wire_n10iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10iO1OO_dataout : STD_LOGIC; + SIGNAL wire_n10iOi0i_dataout : STD_LOGIC; + SIGNAL wire_n10iOi0l_dataout : STD_LOGIC; + SIGNAL wire_n10iOi0O_dataout : STD_LOGIC; + SIGNAL wire_n10iOi1i_dataout : STD_LOGIC; + SIGNAL wire_n10iOi1l_dataout : STD_LOGIC; + SIGNAL wire_n10iOi1O_dataout : STD_LOGIC; + SIGNAL wire_n10iOii_dataout : STD_LOGIC; + SIGNAL wire_n10iOiii_dataout : STD_LOGIC; + SIGNAL wire_n10iOiil_dataout : STD_LOGIC; + SIGNAL wire_n10iOiiO_dataout : STD_LOGIC; + SIGNAL wire_n10iOil_dataout : STD_LOGIC; + SIGNAL wire_n10iOili_dataout : STD_LOGIC; + SIGNAL wire_n10iOill_dataout : STD_LOGIC; + SIGNAL wire_n10iOilO_dataout : STD_LOGIC; + SIGNAL wire_n10iOiO_dataout : STD_LOGIC; + SIGNAL wire_n10iOiOi_dataout : STD_LOGIC; + SIGNAL wire_n10iOiOl_dataout : STD_LOGIC; + SIGNAL wire_n10iOiOO_dataout : STD_LOGIC; + SIGNAL wire_n10iOl0i_dataout : STD_LOGIC; + SIGNAL wire_n10iOl0l_dataout : STD_LOGIC; + SIGNAL wire_n10iOl0O_dataout : STD_LOGIC; + SIGNAL wire_n10iOl1i_dataout : STD_LOGIC; + SIGNAL wire_n10iOl1l_dataout : STD_LOGIC; + SIGNAL wire_n10iOl1O_dataout : STD_LOGIC; + SIGNAL wire_n10iOli_dataout : STD_LOGIC; + SIGNAL wire_n10iOlii_dataout : STD_LOGIC; + SIGNAL wire_n10iOlil_dataout : STD_LOGIC; + SIGNAL wire_n10iOliO_dataout : STD_LOGIC; + SIGNAL wire_n10iOll_dataout : STD_LOGIC; + SIGNAL wire_n10iOlli_dataout : STD_LOGIC; + SIGNAL wire_n10iOlll_dataout : STD_LOGIC; + SIGNAL wire_n10iOllO_dataout : STD_LOGIC; + SIGNAL wire_n10iOlO_dataout : STD_LOGIC; + SIGNAL wire_n10iOlOi_dataout : STD_LOGIC; + SIGNAL wire_n10iOlOl_dataout : STD_LOGIC; + SIGNAL wire_n10iOlOO_dataout : STD_LOGIC; + SIGNAL wire_n10iOO0i_dataout : STD_LOGIC; + SIGNAL wire_n10iOO0l_dataout : STD_LOGIC; + SIGNAL wire_n10iOO0O_dataout : STD_LOGIC; + SIGNAL wire_n10iOO1i_dataout : STD_LOGIC; + SIGNAL wire_n10iOO1l_dataout : STD_LOGIC; + SIGNAL wire_n10iOO1O_dataout : STD_LOGIC; + SIGNAL wire_n10iOOi_dataout : STD_LOGIC; + SIGNAL wire_n10iOOii_dataout : STD_LOGIC; + SIGNAL wire_n10iOOil_dataout : STD_LOGIC; + SIGNAL wire_n10iOOiO_dataout : STD_LOGIC; + SIGNAL wire_n10iOOl_dataout : STD_LOGIC; + SIGNAL wire_n10iOOli_dataout : STD_LOGIC; + SIGNAL wire_n10iOOll_dataout : STD_LOGIC; + SIGNAL wire_n10iOOlO_dataout : STD_LOGIC; + SIGNAL wire_n10iOOO_dataout : STD_LOGIC; + SIGNAL wire_n10iOOOi_dataout : STD_LOGIC; + SIGNAL wire_n10iOOOl_dataout : STD_LOGIC; + SIGNAL wire_n10iOOOO_dataout : STD_LOGIC; + SIGNAL wire_n10l000i_dataout : STD_LOGIC; + SIGNAL wire_n10l000l_dataout : STD_LOGIC; + SIGNAL wire_n10l000O_dataout : STD_LOGIC; + SIGNAL wire_n10l001i_dataout : STD_LOGIC; + SIGNAL wire_n10l001l_dataout : STD_LOGIC; + SIGNAL wire_n10l001O_dataout : STD_LOGIC; + SIGNAL wire_n10l00i_dataout : STD_LOGIC; + SIGNAL wire_n10l00ii_dataout : STD_LOGIC; + SIGNAL wire_n10l00il_dataout : STD_LOGIC; + SIGNAL wire_n10l00iO_dataout : STD_LOGIC; + SIGNAL wire_n10l00l_dataout : STD_LOGIC; + SIGNAL wire_n10l00li_dataout : STD_LOGIC; + SIGNAL wire_n10l00ll_dataout : STD_LOGIC; + SIGNAL wire_n10l00lO_dataout : STD_LOGIC; + SIGNAL wire_n10l00O_dataout : STD_LOGIC; + SIGNAL wire_n10l00Oi_dataout : STD_LOGIC; + SIGNAL wire_n10l00Ol_dataout : STD_LOGIC; + SIGNAL wire_n10l00OO_dataout : STD_LOGIC; + SIGNAL wire_n10l010i_dataout : STD_LOGIC; + SIGNAL wire_n10l010l_dataout : STD_LOGIC; + SIGNAL wire_n10l010O_dataout : STD_LOGIC; + SIGNAL wire_n10l011i_dataout : STD_LOGIC; + SIGNAL wire_n10l011l_dataout : STD_LOGIC; + SIGNAL wire_n10l011O_dataout : STD_LOGIC; + SIGNAL wire_n10l01i_dataout : STD_LOGIC; + SIGNAL wire_n10l01ii_dataout : STD_LOGIC; + SIGNAL wire_n10l01il_dataout : STD_LOGIC; + SIGNAL wire_n10l01iO_dataout : STD_LOGIC; + SIGNAL wire_n10l01l_dataout : STD_LOGIC; + SIGNAL wire_n10l01li_dataout : STD_LOGIC; + SIGNAL wire_n10l01ll_dataout : STD_LOGIC; + SIGNAL wire_n10l01lO_dataout : STD_LOGIC; + SIGNAL wire_n10l01O_dataout : STD_LOGIC; + SIGNAL wire_n10l01Oi_dataout : STD_LOGIC; + SIGNAL wire_n10l01Ol_dataout : STD_LOGIC; + SIGNAL wire_n10l01OO_dataout : STD_LOGIC; + SIGNAL wire_n10l0i0i_dataout : STD_LOGIC; + SIGNAL wire_n10l0i0l_dataout : STD_LOGIC; + SIGNAL wire_n10l0i0O_dataout : STD_LOGIC; + SIGNAL wire_n10l0i1i_dataout : STD_LOGIC; + SIGNAL wire_n10l0i1l_dataout : STD_LOGIC; + SIGNAL wire_n10l0i1O_dataout : STD_LOGIC; + SIGNAL wire_n10l0ii_dataout : STD_LOGIC; + SIGNAL wire_n10l0iii_dataout : STD_LOGIC; + SIGNAL wire_n10l0iil_dataout : STD_LOGIC; + SIGNAL wire_n10l0iiO_dataout : STD_LOGIC; + SIGNAL wire_n10l0il_dataout : STD_LOGIC; + SIGNAL wire_n10l0ili_dataout : STD_LOGIC; + SIGNAL wire_n10l0ill_dataout : STD_LOGIC; + SIGNAL wire_n10l0ilO_dataout : STD_LOGIC; + SIGNAL wire_n10l0iO_dataout : STD_LOGIC; + SIGNAL wire_n10l0iOi_dataout : STD_LOGIC; + SIGNAL wire_n10l0iOl_dataout : STD_LOGIC; + SIGNAL wire_n10l0iOO_dataout : STD_LOGIC; + SIGNAL wire_n10l0l0i_dataout : STD_LOGIC; + SIGNAL wire_n10l0l0l_dataout : STD_LOGIC; + SIGNAL wire_n10l0l0O_dataout : STD_LOGIC; + SIGNAL wire_n10l0l1i_dataout : STD_LOGIC; + SIGNAL wire_n10l0l1l_dataout : STD_LOGIC; + SIGNAL wire_n10l0l1O_dataout : STD_LOGIC; + SIGNAL wire_n10l0li_dataout : STD_LOGIC; + SIGNAL wire_n10l0lii_dataout : STD_LOGIC; + SIGNAL wire_n10l0lil_dataout : STD_LOGIC; + SIGNAL wire_n10l0liO_dataout : STD_LOGIC; + SIGNAL wire_n10l0ll_dataout : STD_LOGIC; + SIGNAL wire_n10l0lli_dataout : STD_LOGIC; + SIGNAL wire_n10l0lll_dataout : STD_LOGIC; + SIGNAL wire_n10l0llO_dataout : STD_LOGIC; + SIGNAL wire_n10l0lO_dataout : STD_LOGIC; + SIGNAL wire_n10l0lOi_dataout : STD_LOGIC; + SIGNAL wire_n10l0lOl_dataout : STD_LOGIC; + SIGNAL wire_n10l0lOO_dataout : STD_LOGIC; + SIGNAL wire_n10l0O0i_dataout : STD_LOGIC; + SIGNAL wire_n10l0O0l_dataout : STD_LOGIC; + SIGNAL wire_n10l0O0O_dataout : STD_LOGIC; + SIGNAL wire_n10l0O1i_dataout : STD_LOGIC; + SIGNAL wire_n10l0O1l_dataout : STD_LOGIC; + SIGNAL wire_n10l0O1O_dataout : STD_LOGIC; + SIGNAL wire_n10l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10l0Oii_dataout : STD_LOGIC; + SIGNAL wire_n10l0Oil_dataout : STD_LOGIC; + SIGNAL wire_n10l0OiO_dataout : STD_LOGIC; + SIGNAL wire_n10l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10l0Oli_dataout : STD_LOGIC; + SIGNAL wire_n10l0Oll_dataout : STD_LOGIC; + SIGNAL wire_n10l0OlO_dataout : STD_LOGIC; + SIGNAL wire_n10l0OO_dataout : STD_LOGIC; + SIGNAL wire_n10l0OOi_dataout : STD_LOGIC; + SIGNAL wire_n10l0OOl_dataout : STD_LOGIC; + SIGNAL wire_n10l0OOO_dataout : STD_LOGIC; + SIGNAL wire_n10l10i_dataout : STD_LOGIC; + SIGNAL wire_n10l10l_dataout : STD_LOGIC; + SIGNAL wire_n10l10O_dataout : STD_LOGIC; + SIGNAL wire_n10l111i_dataout : STD_LOGIC; + SIGNAL wire_n10l111l_dataout : STD_LOGIC; + SIGNAL wire_n10l11i_dataout : STD_LOGIC; + SIGNAL wire_n10l11l_dataout : STD_LOGIC; + SIGNAL wire_n10l11O_dataout : STD_LOGIC; + SIGNAL wire_n10l1ii_dataout : STD_LOGIC; + SIGNAL wire_n10l1il_dataout : STD_LOGIC; + SIGNAL wire_n10l1iO_dataout : STD_LOGIC; + SIGNAL wire_n10l1l0i_dataout : STD_LOGIC; + SIGNAL wire_n10l1l0l_dataout : STD_LOGIC; + SIGNAL wire_n10l1l0O_dataout : STD_LOGIC; + SIGNAL wire_n10l1l1l_dataout : STD_LOGIC; + SIGNAL wire_n10l1li_dataout : STD_LOGIC; + SIGNAL wire_n10l1lii_dataout : STD_LOGIC; + SIGNAL wire_n10l1lil_dataout : STD_LOGIC; + SIGNAL wire_n10l1liO_dataout : STD_LOGIC; + SIGNAL wire_n10l1ll_dataout : STD_LOGIC; + SIGNAL wire_n10l1lli_dataout : STD_LOGIC; + SIGNAL wire_n10l1lll_dataout : STD_LOGIC; + SIGNAL wire_n10l1llO_dataout : STD_LOGIC; + SIGNAL wire_n10l1lO_dataout : STD_LOGIC; + SIGNAL wire_n10l1lOi_dataout : STD_LOGIC; + SIGNAL wire_n10l1lOl_dataout : STD_LOGIC; + SIGNAL wire_n10l1lOO_dataout : STD_LOGIC; + SIGNAL wire_n10l1O0i_dataout : STD_LOGIC; + SIGNAL wire_n10l1O0l_dataout : STD_LOGIC; + SIGNAL wire_n10l1O0O_dataout : STD_LOGIC; + SIGNAL wire_n10l1O1i_dataout : STD_LOGIC; + SIGNAL wire_n10l1O1l_dataout : STD_LOGIC; + SIGNAL wire_n10l1O1O_dataout : STD_LOGIC; + SIGNAL wire_n10l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10l1Oii_dataout : STD_LOGIC; + SIGNAL wire_n10l1Oil_dataout : STD_LOGIC; + SIGNAL wire_n10l1OiO_dataout : STD_LOGIC; + SIGNAL wire_n10l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10l1Oli_dataout : STD_LOGIC; + SIGNAL wire_n10l1Oll_dataout : STD_LOGIC; + SIGNAL wire_n10l1OlO_dataout : STD_LOGIC; + SIGNAL wire_n10l1OO_dataout : STD_LOGIC; + SIGNAL wire_n10l1OOi_dataout : STD_LOGIC; + SIGNAL wire_n10l1OOl_dataout : STD_LOGIC; + SIGNAL wire_n10l1OOO_dataout : STD_LOGIC; + SIGNAL wire_n10li00i_dataout : STD_LOGIC; + SIGNAL wire_n10li00l_dataout : STD_LOGIC; + SIGNAL wire_n10li00O_dataout : STD_LOGIC; + SIGNAL wire_n10li01i_dataout : STD_LOGIC; + SIGNAL wire_n10li01l_dataout : STD_LOGIC; + SIGNAL wire_n10li01O_dataout : STD_LOGIC; + SIGNAL wire_n10li0i_dataout : STD_LOGIC; + SIGNAL wire_n10li0ii_dataout : STD_LOGIC; + SIGNAL wire_n10li0il_dataout : STD_LOGIC; + SIGNAL wire_n10li0iO_dataout : STD_LOGIC; + SIGNAL wire_n10li0l_dataout : STD_LOGIC; + SIGNAL wire_n10li0li_dataout : STD_LOGIC; + SIGNAL wire_n10li0ll_dataout : STD_LOGIC; + SIGNAL wire_n10li0lO_dataout : STD_LOGIC; + SIGNAL wire_n10li0O_dataout : STD_LOGIC; + SIGNAL wire_n10li0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10li0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10li0OO_dataout : STD_LOGIC; + SIGNAL wire_n10li10i_dataout : STD_LOGIC; + SIGNAL wire_n10li10l_dataout : STD_LOGIC; + SIGNAL wire_n10li10O_dataout : STD_LOGIC; + SIGNAL wire_n10li11i_dataout : STD_LOGIC; + SIGNAL wire_n10li11l_dataout : STD_LOGIC; + SIGNAL wire_n10li11O_dataout : STD_LOGIC; + SIGNAL wire_n10li1i_dataout : STD_LOGIC; + SIGNAL wire_n10li1ii_dataout : STD_LOGIC; + SIGNAL wire_n10li1il_dataout : STD_LOGIC; + SIGNAL wire_n10li1iO_dataout : STD_LOGIC; + SIGNAL wire_n10li1l_dataout : STD_LOGIC; + SIGNAL wire_n10li1li_dataout : STD_LOGIC; + SIGNAL wire_n10li1ll_dataout : STD_LOGIC; + SIGNAL wire_n10li1lO_dataout : STD_LOGIC; + SIGNAL wire_n10li1O_dataout : STD_LOGIC; + SIGNAL wire_n10li1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10li1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10li1OO_dataout : STD_LOGIC; + SIGNAL wire_n10lii1i_dataout : STD_LOGIC; + SIGNAL wire_n10liii_dataout : STD_LOGIC; + SIGNAL wire_n10liil_dataout : STD_LOGIC; + SIGNAL wire_n10liiO_dataout : STD_LOGIC; + SIGNAL wire_n10lili_dataout : STD_LOGIC; + SIGNAL wire_n10lill_dataout : STD_LOGIC; + SIGNAL wire_n10lilO_dataout : STD_LOGIC; + SIGNAL wire_n10lilOO_dataout : STD_LOGIC; + SIGNAL wire_n10liO0i_dataout : STD_LOGIC; + SIGNAL wire_n10liO0l_dataout : STD_LOGIC; + SIGNAL wire_n10liO0O_dataout : STD_LOGIC; + SIGNAL wire_n10liO1i_dataout : STD_LOGIC; + SIGNAL wire_n10liO1l_dataout : STD_LOGIC; + SIGNAL wire_n10liOi_dataout : STD_LOGIC; + SIGNAL wire_n10liOii_dataout : STD_LOGIC; + SIGNAL wire_n10liOil_dataout : STD_LOGIC; + SIGNAL wire_n10liOiO_dataout : STD_LOGIC; + SIGNAL wire_n10liOl_dataout : STD_LOGIC; + SIGNAL wire_n10liOli_dataout : STD_LOGIC; + SIGNAL wire_n10liOll_dataout : STD_LOGIC; + SIGNAL wire_n10liOlO_dataout : STD_LOGIC; + SIGNAL wire_n10liOO_dataout : STD_LOGIC; + SIGNAL wire_n10liOOi_dataout : STD_LOGIC; + SIGNAL wire_n10liOOl_dataout : STD_LOGIC; + SIGNAL wire_n10liOOO_dataout : STD_LOGIC; + SIGNAL wire_n10ll00i_dataout : STD_LOGIC; + SIGNAL wire_n10ll00O_dataout : STD_LOGIC; + SIGNAL wire_n10ll01i_dataout : STD_LOGIC; + SIGNAL wire_n10ll01l_dataout : STD_LOGIC; + SIGNAL wire_n10ll01O_dataout : STD_LOGIC; + SIGNAL wire_n10ll0i_dataout : STD_LOGIC; + SIGNAL wire_n10ll0l_dataout : STD_LOGIC; + SIGNAL wire_n10ll0O_dataout : STD_LOGIC; + SIGNAL wire_n10ll10i_dataout : STD_LOGIC; + SIGNAL wire_n10ll10l_dataout : STD_LOGIC; + SIGNAL wire_n10ll10O_dataout : STD_LOGIC; + SIGNAL wire_n10ll11i_dataout : STD_LOGIC; + SIGNAL wire_n10ll11l_dataout : STD_LOGIC; + SIGNAL wire_n10ll11O_dataout : STD_LOGIC; + SIGNAL wire_n10ll1i_dataout : STD_LOGIC; + SIGNAL wire_n10ll1ii_dataout : STD_LOGIC; + SIGNAL wire_n10ll1il_dataout : STD_LOGIC; + SIGNAL wire_n10ll1iO_dataout : STD_LOGIC; + SIGNAL wire_n10ll1l_dataout : STD_LOGIC; + SIGNAL wire_n10ll1li_dataout : STD_LOGIC; + SIGNAL wire_n10ll1ll_dataout : STD_LOGIC; + SIGNAL wire_n10ll1lO_dataout : STD_LOGIC; + SIGNAL wire_n10ll1O_dataout : STD_LOGIC; + SIGNAL wire_n10ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10ll1OO_dataout : STD_LOGIC; + SIGNAL wire_n10lli0i_dataout : STD_LOGIC; + SIGNAL wire_n10lli0l_dataout : STD_LOGIC; + SIGNAL wire_n10lli0O_dataout : STD_LOGIC; + SIGNAL wire_n10lli1l_dataout : STD_LOGIC; + SIGNAL wire_n10lli1O_dataout : STD_LOGIC; + SIGNAL wire_n10llii_dataout : STD_LOGIC; + SIGNAL wire_n10lliii_dataout : STD_LOGIC; + SIGNAL wire_n10lliil_dataout : STD_LOGIC; + SIGNAL wire_n10lliiO_dataout : STD_LOGIC; + SIGNAL wire_n10llil_dataout : STD_LOGIC; + SIGNAL wire_n10llili_dataout : STD_LOGIC; + SIGNAL wire_n10llill_dataout : STD_LOGIC; + SIGNAL wire_n10llilO_dataout : STD_LOGIC; + SIGNAL wire_n10lliO_dataout : STD_LOGIC; + SIGNAL wire_n10lliOi_dataout : STD_LOGIC; + SIGNAL wire_n10lliOl_dataout : STD_LOGIC; + SIGNAL wire_n10lliOO_dataout : STD_LOGIC; + SIGNAL wire_n10lll0i_dataout : STD_LOGIC; + SIGNAL wire_n10lll0l_dataout : STD_LOGIC; + SIGNAL wire_n10lll0O_dataout : STD_LOGIC; + SIGNAL wire_n10lll1i_dataout : STD_LOGIC; + SIGNAL wire_n10lll1l_dataout : STD_LOGIC; + SIGNAL wire_n10lll1O_dataout : STD_LOGIC; + SIGNAL wire_n10llli_dataout : STD_LOGIC; + SIGNAL wire_n10lllii_dataout : STD_LOGIC; + SIGNAL wire_n10lllil_dataout : STD_LOGIC; + SIGNAL wire_n10llliO_dataout : STD_LOGIC; + SIGNAL wire_n10llll_dataout : STD_LOGIC; + SIGNAL wire_n10lllli_dataout : STD_LOGIC; + SIGNAL wire_n10lllll_dataout : STD_LOGIC; + SIGNAL wire_n10llllO_dataout : STD_LOGIC; + SIGNAL wire_n10lllO_dataout : STD_LOGIC; + SIGNAL wire_n10lllOi_dataout : STD_LOGIC; + SIGNAL wire_n10lllOl_dataout : STD_LOGIC; + SIGNAL wire_n10lllOO_dataout : STD_LOGIC; + SIGNAL wire_n10llO0i_dataout : STD_LOGIC; + SIGNAL wire_n10llO0l_dataout : STD_LOGIC; + SIGNAL wire_n10llO0O_dataout : STD_LOGIC; + SIGNAL wire_n10llO1i_dataout : STD_LOGIC; + SIGNAL wire_n10llO1l_dataout : STD_LOGIC; + SIGNAL wire_n10llO1O_dataout : STD_LOGIC; + SIGNAL wire_n10llOi_dataout : STD_LOGIC; + SIGNAL wire_n10llOii_dataout : STD_LOGIC; + SIGNAL wire_n10llOil_dataout : STD_LOGIC; + SIGNAL wire_n10llOiO_dataout : STD_LOGIC; + SIGNAL wire_n10llOl_dataout : STD_LOGIC; + SIGNAL wire_n10llOli_dataout : STD_LOGIC; + SIGNAL wire_n10llOll_dataout : STD_LOGIC; + SIGNAL wire_n10llOlO_dataout : STD_LOGIC; + SIGNAL wire_n10llOO_dataout : STD_LOGIC; + SIGNAL wire_n10llOOi_dataout : STD_LOGIC; + SIGNAL wire_n10llOOl_dataout : STD_LOGIC; + SIGNAL wire_n10llOOO_dataout : STD_LOGIC; + SIGNAL wire_n10lO00i_dataout : STD_LOGIC; + SIGNAL wire_n10lO00l_dataout : STD_LOGIC; + SIGNAL wire_n10lO00O_dataout : STD_LOGIC; + SIGNAL wire_n10lO01i_dataout : STD_LOGIC; + SIGNAL wire_n10lO01l_dataout : STD_LOGIC; + SIGNAL wire_n10lO01O_dataout : STD_LOGIC; + SIGNAL wire_n10lO0i_dataout : STD_LOGIC; + SIGNAL wire_n10lO0ii_dataout : STD_LOGIC; + SIGNAL wire_n10lO0il_dataout : STD_LOGIC; + SIGNAL wire_n10lO0iO_dataout : STD_LOGIC; + SIGNAL wire_n10lO0l_dataout : STD_LOGIC; + SIGNAL wire_n10lO0li_dataout : STD_LOGIC; + SIGNAL wire_n10lO0ll_dataout : STD_LOGIC; + SIGNAL wire_n10lO0lO_dataout : STD_LOGIC; + SIGNAL wire_n10lO0O_dataout : STD_LOGIC; + SIGNAL wire_n10lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10lO0OO_dataout : STD_LOGIC; + SIGNAL wire_n10lO10i_dataout : STD_LOGIC; + SIGNAL wire_n10lO10l_dataout : STD_LOGIC; + SIGNAL wire_n10lO10O_dataout : STD_LOGIC; + SIGNAL wire_n10lO11i_dataout : STD_LOGIC; + SIGNAL wire_n10lO11l_dataout : STD_LOGIC; + SIGNAL wire_n10lO11O_dataout : STD_LOGIC; + SIGNAL wire_n10lO1i_dataout : STD_LOGIC; + SIGNAL wire_n10lO1ii_dataout : STD_LOGIC; + SIGNAL wire_n10lO1il_dataout : STD_LOGIC; + SIGNAL wire_n10lO1iO_dataout : STD_LOGIC; + SIGNAL wire_n10lO1l_dataout : STD_LOGIC; + SIGNAL wire_n10lO1li_dataout : STD_LOGIC; + SIGNAL wire_n10lO1ll_dataout : STD_LOGIC; + SIGNAL wire_n10lO1lO_dataout : STD_LOGIC; + SIGNAL wire_n10lO1O_dataout : STD_LOGIC; + SIGNAL wire_n10lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10lO1OO_dataout : STD_LOGIC; + SIGNAL wire_n10lOi0i_dataout : STD_LOGIC; + SIGNAL wire_n10lOi0l_dataout : STD_LOGIC; + SIGNAL wire_n10lOi0O_dataout : STD_LOGIC; + SIGNAL wire_n10lOi1i_dataout : STD_LOGIC; + SIGNAL wire_n10lOi1l_dataout : STD_LOGIC; + SIGNAL wire_n10lOi1O_dataout : STD_LOGIC; + SIGNAL wire_n10lOii_dataout : STD_LOGIC; + SIGNAL wire_n10lOiii_dataout : STD_LOGIC; + SIGNAL wire_n10lOiil_dataout : STD_LOGIC; + SIGNAL wire_n10lOiiO_dataout : STD_LOGIC; + SIGNAL wire_n10lOil_dataout : STD_LOGIC; + SIGNAL wire_n10lOili_dataout : STD_LOGIC; + SIGNAL wire_n10lOill_dataout : STD_LOGIC; + SIGNAL wire_n10lOilO_dataout : STD_LOGIC; + SIGNAL wire_n10lOiO_dataout : STD_LOGIC; + SIGNAL wire_n10lOiOi_dataout : STD_LOGIC; + SIGNAL wire_n10lOiOl_dataout : STD_LOGIC; + SIGNAL wire_n10lOiOO_dataout : STD_LOGIC; + SIGNAL wire_n10lOl0i_dataout : STD_LOGIC; + SIGNAL wire_n10lOl0l_dataout : STD_LOGIC; + SIGNAL wire_n10lOl0O_dataout : STD_LOGIC; + SIGNAL wire_n10lOl1i_dataout : STD_LOGIC; + SIGNAL wire_n10lOl1l_dataout : STD_LOGIC; + SIGNAL wire_n10lOl1O_dataout : STD_LOGIC; + SIGNAL wire_n10lOli_dataout : STD_LOGIC; + SIGNAL wire_n10lOlii_dataout : STD_LOGIC; + SIGNAL wire_n10lOlil_dataout : STD_LOGIC; + SIGNAL wire_n10lOliO_dataout : STD_LOGIC; + SIGNAL wire_n10lOll_dataout : STD_LOGIC; + SIGNAL wire_n10lOlli_dataout : STD_LOGIC; + SIGNAL wire_n10lOlll_dataout : STD_LOGIC; + SIGNAL wire_n10lOllO_dataout : STD_LOGIC; + SIGNAL wire_n10lOlO_dataout : STD_LOGIC; + SIGNAL wire_n10lOlOi_dataout : STD_LOGIC; + SIGNAL wire_n10lOlOl_dataout : STD_LOGIC; + SIGNAL wire_n10lOlOO_dataout : STD_LOGIC; + SIGNAL wire_n10lOO0l_dataout : STD_LOGIC; + SIGNAL wire_n10lOO0O_dataout : STD_LOGIC; + SIGNAL wire_n10lOO1i_dataout : STD_LOGIC; + SIGNAL wire_n10lOO1l_dataout : STD_LOGIC; + SIGNAL wire_n10lOOi_dataout : STD_LOGIC; + SIGNAL wire_n10lOOii_dataout : STD_LOGIC; + SIGNAL wire_n10lOOil_dataout : STD_LOGIC; + SIGNAL wire_n10lOOiO_dataout : STD_LOGIC; + SIGNAL wire_n10lOOl_dataout : STD_LOGIC; + SIGNAL wire_n10lOOli_dataout : STD_LOGIC; + SIGNAL wire_n10lOOll_dataout : STD_LOGIC; + SIGNAL wire_n10lOOlO_dataout : STD_LOGIC; + SIGNAL wire_n10lOOO_dataout : STD_LOGIC; + SIGNAL wire_n10lOOOi_dataout : STD_LOGIC; + SIGNAL wire_n10lOOOl_dataout : STD_LOGIC; + SIGNAL wire_n10lOOOO_dataout : STD_LOGIC; + SIGNAL wire_n10O000i_dataout : STD_LOGIC; + SIGNAL wire_n10O000l_dataout : STD_LOGIC; + SIGNAL wire_n10O000O_dataout : STD_LOGIC; + SIGNAL wire_n10O001i_dataout : STD_LOGIC; + SIGNAL wire_n10O001l_dataout : STD_LOGIC; + SIGNAL wire_n10O001O_dataout : STD_LOGIC; + SIGNAL wire_n10O00i_dataout : STD_LOGIC; + SIGNAL wire_n10O00ii_dataout : STD_LOGIC; + SIGNAL wire_n10O00il_dataout : STD_LOGIC; + SIGNAL wire_n10O00iO_dataout : STD_LOGIC; + SIGNAL wire_n10O00l_dataout : STD_LOGIC; + SIGNAL wire_n10O00li_dataout : STD_LOGIC; + SIGNAL wire_n10O00ll_dataout : STD_LOGIC; + SIGNAL wire_n10O00lO_dataout : STD_LOGIC; + SIGNAL wire_n10O00O_dataout : STD_LOGIC; + SIGNAL wire_n10O00Oi_dataout : STD_LOGIC; + SIGNAL wire_n10O00Ol_dataout : STD_LOGIC; + SIGNAL wire_n10O00OO_dataout : STD_LOGIC; + SIGNAL wire_n10O010i_dataout : STD_LOGIC; + SIGNAL wire_n10O010l_dataout : STD_LOGIC; + SIGNAL wire_n10O010O_dataout : STD_LOGIC; + SIGNAL wire_n10O011i_dataout : STD_LOGIC; + SIGNAL wire_n10O011l_dataout : STD_LOGIC; + SIGNAL wire_n10O011O_dataout : STD_LOGIC; + SIGNAL wire_n10O01i_dataout : STD_LOGIC; + SIGNAL wire_n10O01ii_dataout : STD_LOGIC; + SIGNAL wire_n10O01il_dataout : STD_LOGIC; + SIGNAL wire_n10O01iO_dataout : STD_LOGIC; + SIGNAL wire_n10O01l_dataout : STD_LOGIC; + SIGNAL wire_n10O01li_dataout : STD_LOGIC; + SIGNAL wire_n10O01ll_dataout : STD_LOGIC; + SIGNAL wire_n10O01lO_dataout : STD_LOGIC; + SIGNAL wire_n10O01O_dataout : STD_LOGIC; + SIGNAL wire_n10O01Oi_dataout : STD_LOGIC; + SIGNAL wire_n10O01Ol_dataout : STD_LOGIC; + SIGNAL wire_n10O01OO_dataout : STD_LOGIC; + SIGNAL wire_n10O0i0i_dataout : STD_LOGIC; + SIGNAL wire_n10O0i0l_dataout : STD_LOGIC; + SIGNAL wire_n10O0i0O_dataout : STD_LOGIC; + SIGNAL wire_n10O0i1i_dataout : STD_LOGIC; + SIGNAL wire_n10O0i1l_dataout : STD_LOGIC; + SIGNAL wire_n10O0i1O_dataout : STD_LOGIC; + SIGNAL wire_n10O0ii_dataout : STD_LOGIC; + SIGNAL wire_n10O0iii_dataout : STD_LOGIC; + SIGNAL wire_n10O0iil_dataout : STD_LOGIC; + SIGNAL wire_n10O0iiO_dataout : STD_LOGIC; + SIGNAL wire_n10O0il_dataout : STD_LOGIC; + SIGNAL wire_n10O0ili_dataout : STD_LOGIC; + SIGNAL wire_n10O0ill_dataout : STD_LOGIC; + SIGNAL wire_n10O0ilO_dataout : STD_LOGIC; + SIGNAL wire_n10O0iO_dataout : STD_LOGIC; + SIGNAL wire_n10O0iOi_dataout : STD_LOGIC; + SIGNAL wire_n10O0iOl_dataout : STD_LOGIC; + SIGNAL wire_n10O0iOO_dataout : STD_LOGIC; + SIGNAL wire_n10O0l0i_dataout : STD_LOGIC; + SIGNAL wire_n10O0l0l_dataout : STD_LOGIC; + SIGNAL wire_n10O0l0O_dataout : STD_LOGIC; + SIGNAL wire_n10O0l1i_dataout : STD_LOGIC; + SIGNAL wire_n10O0l1l_dataout : STD_LOGIC; + SIGNAL wire_n10O0l1O_dataout : STD_LOGIC; + SIGNAL wire_n10O0li_dataout : STD_LOGIC; + SIGNAL wire_n10O0lii_dataout : STD_LOGIC; + SIGNAL wire_n10O0lil_dataout : STD_LOGIC; + SIGNAL wire_n10O0liO_dataout : STD_LOGIC; + SIGNAL wire_n10O0ll_dataout : STD_LOGIC; + SIGNAL wire_n10O0lli_dataout : STD_LOGIC; + SIGNAL wire_n10O0lll_dataout : STD_LOGIC; + SIGNAL wire_n10O0llO_dataout : STD_LOGIC; + SIGNAL wire_n10O0lO_dataout : STD_LOGIC; + SIGNAL wire_n10O0lOi_dataout : STD_LOGIC; + SIGNAL wire_n10O0lOl_dataout : STD_LOGIC; + SIGNAL wire_n10O0lOO_dataout : STD_LOGIC; + SIGNAL wire_n10O0O0i_dataout : STD_LOGIC; + SIGNAL wire_n10O0O0l_dataout : STD_LOGIC; + SIGNAL wire_n10O0O0O_dataout : STD_LOGIC; + SIGNAL wire_n10O0O1i_dataout : STD_LOGIC; + SIGNAL wire_n10O0O1l_dataout : STD_LOGIC; + SIGNAL wire_n10O0O1O_dataout : STD_LOGIC; + SIGNAL wire_n10O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10O0Oii_dataout : STD_LOGIC; + SIGNAL wire_n10O0Oil_dataout : STD_LOGIC; + SIGNAL wire_n10O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10O0OO_dataout : STD_LOGIC; + SIGNAL wire_n10O100i_dataout : STD_LOGIC; + SIGNAL wire_n10O100l_dataout : STD_LOGIC; + SIGNAL wire_n10O100O_dataout : STD_LOGIC; + SIGNAL wire_n10O101i_dataout : STD_LOGIC; + SIGNAL wire_n10O101l_dataout : STD_LOGIC; + SIGNAL wire_n10O101O_dataout : STD_LOGIC; + SIGNAL wire_n10O10i_dataout : STD_LOGIC; + SIGNAL wire_n10O10ii_dataout : STD_LOGIC; + SIGNAL wire_n10O10il_dataout : STD_LOGIC; + SIGNAL wire_n10O10iO_dataout : STD_LOGIC; + SIGNAL wire_n10O10l_dataout : STD_LOGIC; + SIGNAL wire_n10O10li_dataout : STD_LOGIC; + SIGNAL wire_n10O10ll_dataout : STD_LOGIC; + SIGNAL wire_n10O10lO_dataout : STD_LOGIC; + SIGNAL wire_n10O10O_dataout : STD_LOGIC; + SIGNAL wire_n10O10Oi_dataout : STD_LOGIC; + SIGNAL wire_n10O10Ol_dataout : STD_LOGIC; + SIGNAL wire_n10O10OO_dataout : STD_LOGIC; + SIGNAL wire_n10O110i_dataout : STD_LOGIC; + SIGNAL wire_n10O110l_dataout : STD_LOGIC; + SIGNAL wire_n10O110O_dataout : STD_LOGIC; + SIGNAL wire_n10O111i_dataout : STD_LOGIC; + SIGNAL wire_n10O111l_dataout : STD_LOGIC; + SIGNAL wire_n10O111O_dataout : STD_LOGIC; + SIGNAL wire_n10O11i_dataout : STD_LOGIC; + SIGNAL wire_n10O11ii_dataout : STD_LOGIC; + SIGNAL wire_n10O11il_dataout : STD_LOGIC; + SIGNAL wire_n10O11iO_dataout : STD_LOGIC; + SIGNAL wire_n10O11l_dataout : STD_LOGIC; + SIGNAL wire_n10O11li_dataout : STD_LOGIC; + SIGNAL wire_n10O11ll_dataout : STD_LOGIC; + SIGNAL wire_n10O11lO_dataout : STD_LOGIC; + SIGNAL wire_n10O11O_dataout : STD_LOGIC; + SIGNAL wire_n10O11Oi_dataout : STD_LOGIC; + SIGNAL wire_n10O11Ol_dataout : STD_LOGIC; + SIGNAL wire_n10O11OO_dataout : STD_LOGIC; + SIGNAL wire_n10O1i0i_dataout : STD_LOGIC; + SIGNAL wire_n10O1i0l_dataout : STD_LOGIC; + SIGNAL wire_n10O1i0O_dataout : STD_LOGIC; + SIGNAL wire_n10O1i1i_dataout : STD_LOGIC; + SIGNAL wire_n10O1i1l_dataout : STD_LOGIC; + SIGNAL wire_n10O1i1O_dataout : STD_LOGIC; + SIGNAL wire_n10O1ii_dataout : STD_LOGIC; + SIGNAL wire_n10O1iii_dataout : STD_LOGIC; + SIGNAL wire_n10O1iil_dataout : STD_LOGIC; + SIGNAL wire_n10O1iiO_dataout : STD_LOGIC; + SIGNAL wire_n10O1il_dataout : STD_LOGIC; + SIGNAL wire_n10O1ili_dataout : STD_LOGIC; + SIGNAL wire_n10O1ill_dataout : STD_LOGIC; + SIGNAL wire_n10O1ilO_dataout : STD_LOGIC; + SIGNAL wire_n10O1iO_dataout : STD_LOGIC; + SIGNAL wire_n10O1li_dataout : STD_LOGIC; + SIGNAL wire_n10O1ll_dataout : STD_LOGIC; + SIGNAL wire_n10O1lO_dataout : STD_LOGIC; + SIGNAL wire_n10O1O0i_dataout : STD_LOGIC; + SIGNAL wire_n10O1O0O_dataout : STD_LOGIC; + SIGNAL wire_n10O1O1i_dataout : STD_LOGIC; + SIGNAL wire_n10O1O1l_dataout : STD_LOGIC; + SIGNAL wire_n10O1O1O_dataout : STD_LOGIC; + SIGNAL wire_n10O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10O1Oii_dataout : STD_LOGIC; + SIGNAL wire_n10O1Oil_dataout : STD_LOGIC; + SIGNAL wire_n10O1OiO_dataout : STD_LOGIC; + SIGNAL wire_n10O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10O1Oli_dataout : STD_LOGIC; + SIGNAL wire_n10O1Oll_dataout : STD_LOGIC; + SIGNAL wire_n10O1OlO_dataout : STD_LOGIC; + SIGNAL wire_n10O1OO_dataout : STD_LOGIC; + SIGNAL wire_n10O1OOi_dataout : STD_LOGIC; + SIGNAL wire_n10O1OOl_dataout : STD_LOGIC; + SIGNAL wire_n10O1OOO_dataout : STD_LOGIC; + SIGNAL wire_n10Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n10Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n10Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n10Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n10Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n10Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n10Oii0i_dataout : STD_LOGIC; + SIGNAL wire_n10Oii0l_dataout : STD_LOGIC; + SIGNAL wire_n10Oii0O_dataout : STD_LOGIC; + SIGNAL wire_n10Oiii_dataout : STD_LOGIC; + SIGNAL wire_n10Oiiii_dataout : STD_LOGIC; + SIGNAL wire_n10Oiiil_dataout : STD_LOGIC; + SIGNAL wire_n10OiiiO_dataout : STD_LOGIC; + SIGNAL wire_n10Oiil_dataout : STD_LOGIC; + SIGNAL wire_n10Oiili_dataout : STD_LOGIC; + SIGNAL wire_n10Oiill_dataout : STD_LOGIC; + SIGNAL wire_n10OiilO_dataout : STD_LOGIC; + SIGNAL wire_n10OiiO_dataout : STD_LOGIC; + SIGNAL wire_n10OiiOi_dataout : STD_LOGIC; + SIGNAL wire_n10OiiOl_dataout : STD_LOGIC; + SIGNAL wire_n10OiiOO_dataout : STD_LOGIC; + SIGNAL wire_n10Oil0i_dataout : STD_LOGIC; + SIGNAL wire_n10Oil0l_dataout : STD_LOGIC; + SIGNAL wire_n10Oil0O_dataout : STD_LOGIC; + SIGNAL wire_n10Oil1i_dataout : STD_LOGIC; + SIGNAL wire_n10Oil1l_dataout : STD_LOGIC; + SIGNAL wire_n10Oil1O_dataout : STD_LOGIC; + SIGNAL wire_n10Oili_dataout : STD_LOGIC; + SIGNAL wire_n10Oilii_dataout : STD_LOGIC; + SIGNAL wire_n10Oilil_dataout : STD_LOGIC; + SIGNAL wire_n10OiliO_dataout : STD_LOGIC; + SIGNAL wire_n10Oill_dataout : STD_LOGIC; + SIGNAL wire_n10Oilli_dataout : STD_LOGIC; + SIGNAL wire_n10Oilll_dataout : STD_LOGIC; + SIGNAL wire_n10OillO_dataout : STD_LOGIC; + SIGNAL wire_n10OilO_dataout : STD_LOGIC; + SIGNAL wire_n10OilOi_dataout : STD_LOGIC; + SIGNAL wire_n10OilOl_dataout : STD_LOGIC; + SIGNAL wire_n10OilOO_dataout : STD_LOGIC; + SIGNAL wire_n10OiO0i_dataout : STD_LOGIC; + SIGNAL wire_n10OiO0l_dataout : STD_LOGIC; + SIGNAL wire_n10OiO0O_dataout : STD_LOGIC; + SIGNAL wire_n10OiO1i_dataout : STD_LOGIC; + SIGNAL wire_n10OiO1l_dataout : STD_LOGIC; + SIGNAL wire_n10OiO1O_dataout : STD_LOGIC; + SIGNAL wire_n10OiOi_dataout : STD_LOGIC; + SIGNAL wire_n10OiOii_dataout : STD_LOGIC; + SIGNAL wire_n10OiOil_dataout : STD_LOGIC; + SIGNAL wire_n10OiOiO_dataout : STD_LOGIC; + SIGNAL wire_n10OiOl_dataout : STD_LOGIC; + SIGNAL wire_n10OiOli_dataout : STD_LOGIC; + SIGNAL wire_n10OiOll_dataout : STD_LOGIC; + SIGNAL wire_n10OiOlO_dataout : STD_LOGIC; + SIGNAL wire_n10OiOO_dataout : STD_LOGIC; + SIGNAL wire_n10OiOOi_dataout : STD_LOGIC; + SIGNAL wire_n10OiOOl_dataout : STD_LOGIC; + SIGNAL wire_n10OiOOO_dataout : STD_LOGIC; + SIGNAL wire_n10Ol00i_dataout : STD_LOGIC; + SIGNAL wire_n10Ol00l_dataout : STD_LOGIC; + SIGNAL wire_n10Ol00O_dataout : STD_LOGIC; + SIGNAL wire_n10Ol01i_dataout : STD_LOGIC; + SIGNAL wire_n10Ol01l_dataout : STD_LOGIC; + SIGNAL wire_n10Ol01O_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0il_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0li_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_n10Ol10i_dataout : STD_LOGIC; + SIGNAL wire_n10Ol10l_dataout : STD_LOGIC; + SIGNAL wire_n10Ol10O_dataout : STD_LOGIC; + SIGNAL wire_n10Ol11i_dataout : STD_LOGIC; + SIGNAL wire_n10Ol11l_dataout : STD_LOGIC; + SIGNAL wire_n10Ol11O_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1il_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1li_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_n10Oli1i_dataout : STD_LOGIC; + SIGNAL wire_n10Oli1l_dataout : STD_LOGIC; + SIGNAL wire_n10Oli1O_dataout : STD_LOGIC; + SIGNAL wire_n10Olii_dataout : STD_LOGIC; + SIGNAL wire_n10Olil_dataout : STD_LOGIC; + SIGNAL wire_n10OliO_dataout : STD_LOGIC; + SIGNAL wire_n10Olli_dataout : STD_LOGIC; + SIGNAL wire_n10Olll_dataout : STD_LOGIC; + SIGNAL wire_n10Ollli_dataout : STD_LOGIC; + SIGNAL wire_n10Ollll_dataout : STD_LOGIC; + SIGNAL wire_n10OlllO_dataout : STD_LOGIC; + SIGNAL wire_n10OllO_dataout : STD_LOGIC; + SIGNAL wire_n10OllOi_dataout : STD_LOGIC; + SIGNAL wire_n10OllOl_dataout : STD_LOGIC; + SIGNAL wire_n10OllOO_dataout : STD_LOGIC; + SIGNAL wire_n10OlO0i_dataout : STD_LOGIC; + SIGNAL wire_n10OlO0l_dataout : STD_LOGIC; + SIGNAL wire_n10OlO0O_dataout : STD_LOGIC; + SIGNAL wire_n10OlO1i_dataout : STD_LOGIC; + SIGNAL wire_n10OlO1l_dataout : STD_LOGIC; + SIGNAL wire_n10OlO1O_dataout : STD_LOGIC; + SIGNAL wire_n10OlOi_dataout : STD_LOGIC; + SIGNAL wire_n10OlOii_dataout : STD_LOGIC; + SIGNAL wire_n10OlOil_dataout : STD_LOGIC; + SIGNAL wire_n10OlOiO_dataout : STD_LOGIC; + SIGNAL wire_n10OlOl_dataout : STD_LOGIC; + SIGNAL wire_n10OlOli_dataout : STD_LOGIC; + SIGNAL wire_n10OlOll_dataout : STD_LOGIC; + SIGNAL wire_n10OlOlO_dataout : STD_LOGIC; + SIGNAL wire_n10OlOO_dataout : STD_LOGIC; + SIGNAL wire_n10OlOOi_dataout : STD_LOGIC; + SIGNAL wire_n10OlOOl_dataout : STD_LOGIC; + SIGNAL wire_n10OlOOO_dataout : STD_LOGIC; + SIGNAL wire_n10OO00i_dataout : STD_LOGIC; + SIGNAL wire_n10OO00l_dataout : STD_LOGIC; + SIGNAL wire_n10OO00O_dataout : STD_LOGIC; + SIGNAL wire_n10OO01i_dataout : STD_LOGIC; + SIGNAL wire_n10OO01l_dataout : STD_LOGIC; + SIGNAL wire_n10OO01O_dataout : STD_LOGIC; + SIGNAL wire_n10OO0ii_dataout : STD_LOGIC; + SIGNAL wire_n10OO0il_dataout : STD_LOGIC; + SIGNAL wire_n10OO0iO_dataout : STD_LOGIC; + SIGNAL wire_n10OO0li_dataout : STD_LOGIC; + SIGNAL wire_n10OO0ll_dataout : STD_LOGIC; + SIGNAL wire_n10OO0lO_dataout : STD_LOGIC; + SIGNAL wire_n10OO0O_dataout : STD_LOGIC; + SIGNAL wire_n10OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n10OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n10OO0OO_dataout : STD_LOGIC; + SIGNAL wire_n10OO10i_dataout : STD_LOGIC; + SIGNAL wire_n10OO10l_dataout : STD_LOGIC; + SIGNAL wire_n10OO10O_dataout : STD_LOGIC; + SIGNAL wire_n10OO11i_dataout : STD_LOGIC; + SIGNAL wire_n10OO11l_dataout : STD_LOGIC; + SIGNAL wire_n10OO11O_dataout : STD_LOGIC; + SIGNAL wire_n10OO1i_dataout : STD_LOGIC; + SIGNAL wire_n10OO1ii_dataout : STD_LOGIC; + SIGNAL wire_n10OO1il_dataout : STD_LOGIC; + SIGNAL wire_n10OO1iO_dataout : STD_LOGIC; + SIGNAL wire_n10OO1li_dataout : STD_LOGIC; + SIGNAL wire_n10OO1ll_dataout : STD_LOGIC; + SIGNAL wire_n10OO1lO_dataout : STD_LOGIC; + SIGNAL wire_n10OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n10OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n10OO1OO_dataout : STD_LOGIC; + SIGNAL wire_n10OOi0i_dataout : STD_LOGIC; + SIGNAL wire_n10OOi0l_dataout : STD_LOGIC; + SIGNAL wire_n10OOi0O_dataout : STD_LOGIC; + SIGNAL wire_n10OOi1i_dataout : STD_LOGIC; + SIGNAL wire_n10OOi1l_dataout : STD_LOGIC; + SIGNAL wire_n10OOi1O_dataout : STD_LOGIC; + SIGNAL wire_n10OOii_dataout : STD_LOGIC; + SIGNAL wire_n10OOiii_dataout : STD_LOGIC; + SIGNAL wire_n10OOiil_dataout : STD_LOGIC; + SIGNAL wire_n10OOiiO_dataout : STD_LOGIC; + SIGNAL wire_n10OOil_dataout : STD_LOGIC; + SIGNAL wire_n10OOili_dataout : STD_LOGIC; + SIGNAL wire_n10OOill_dataout : STD_LOGIC; + SIGNAL wire_n10OOilO_dataout : STD_LOGIC; + SIGNAL wire_n10OOiO_dataout : STD_LOGIC; + SIGNAL wire_n10OOiOi_dataout : STD_LOGIC; + SIGNAL wire_n10OOiOl_dataout : STD_LOGIC; + SIGNAL wire_n10OOiOO_dataout : STD_LOGIC; + SIGNAL wire_n10OOl0i_dataout : STD_LOGIC; + SIGNAL wire_n10OOl0l_dataout : STD_LOGIC; + SIGNAL wire_n10OOl0O_dataout : STD_LOGIC; + SIGNAL wire_n10OOl1i_dataout : STD_LOGIC; + SIGNAL wire_n10OOl1l_dataout : STD_LOGIC; + SIGNAL wire_n10OOl1O_dataout : STD_LOGIC; + SIGNAL wire_n10OOli_dataout : STD_LOGIC; + SIGNAL wire_n10OOlii_dataout : STD_LOGIC; + SIGNAL wire_n10OOlil_dataout : STD_LOGIC; + SIGNAL wire_n10OOliO_dataout : STD_LOGIC; + SIGNAL wire_n10OOll_dataout : STD_LOGIC; + SIGNAL wire_n10OOlli_dataout : STD_LOGIC; + SIGNAL wire_n10OOlll_dataout : STD_LOGIC; + SIGNAL wire_n10OOllO_dataout : STD_LOGIC; + SIGNAL wire_n10OOlO_dataout : STD_LOGIC; + SIGNAL wire_n10OOlOi_dataout : STD_LOGIC; + SIGNAL wire_n10OOlOl_dataout : STD_LOGIC; + SIGNAL wire_n10OOlOO_dataout : STD_LOGIC; + SIGNAL wire_n10OOO0i_dataout : STD_LOGIC; + SIGNAL wire_n10OOO0l_dataout : STD_LOGIC; + SIGNAL wire_n10OOO0O_dataout : STD_LOGIC; + SIGNAL wire_n10OOO1i_dataout : STD_LOGIC; + SIGNAL wire_n10OOO1l_dataout : STD_LOGIC; + SIGNAL wire_n10OOO1O_dataout : STD_LOGIC; + SIGNAL wire_n10OOOi_dataout : STD_LOGIC; + SIGNAL wire_n10OOOii_dataout : STD_LOGIC; + SIGNAL wire_n10OOOil_dataout : STD_LOGIC; + SIGNAL wire_n10OOOiO_dataout : STD_LOGIC; + SIGNAL wire_n10OOOl_dataout : STD_LOGIC; + SIGNAL wire_n10OOOli_dataout : STD_LOGIC; + SIGNAL wire_n10OOOll_dataout : STD_LOGIC; + SIGNAL wire_n10OOOlO_dataout : STD_LOGIC; + SIGNAL wire_n10OOOO_dataout : STD_LOGIC; + SIGNAL wire_n10OOOOi_dataout : STD_LOGIC; + SIGNAL wire_n10OOOOl_dataout : STD_LOGIC; + SIGNAL wire_n10OOOOO_dataout : STD_LOGIC; + SIGNAL wire_n110000i_dataout : STD_LOGIC; + SIGNAL wire_n110000l_dataout : STD_LOGIC; + SIGNAL wire_n110000O_dataout : STD_LOGIC; + SIGNAL wire_n110001i_dataout : STD_LOGIC; + SIGNAL wire_n110001l_dataout : STD_LOGIC; + SIGNAL wire_n110001O_dataout : STD_LOGIC; + SIGNAL wire_n11000i_dataout : STD_LOGIC; + SIGNAL wire_n11000ii_dataout : STD_LOGIC; + SIGNAL wire_n11000il_dataout : STD_LOGIC; + SIGNAL wire_n11000iO_dataout : STD_LOGIC; + SIGNAL wire_n11000l_dataout : STD_LOGIC; + SIGNAL wire_n11000li_dataout : STD_LOGIC; + SIGNAL wire_n11000ll_dataout : STD_LOGIC; + SIGNAL wire_n11000lO_dataout : STD_LOGIC; + SIGNAL wire_n11000O_dataout : STD_LOGIC; + SIGNAL wire_n11000Oi_dataout : STD_LOGIC; + SIGNAL wire_n11000Ol_dataout : STD_LOGIC; + SIGNAL wire_n11000OO_dataout : STD_LOGIC; + SIGNAL wire_n110010i_dataout : STD_LOGIC; + SIGNAL wire_n110010l_dataout : STD_LOGIC; + SIGNAL wire_n110010O_dataout : STD_LOGIC; + SIGNAL wire_n110011i_dataout : STD_LOGIC; + SIGNAL wire_n110011l_dataout : STD_LOGIC; + SIGNAL wire_n110011O_dataout : STD_LOGIC; + SIGNAL wire_n11001i_dataout : STD_LOGIC; + SIGNAL wire_n11001ii_dataout : STD_LOGIC; + SIGNAL wire_n11001il_dataout : STD_LOGIC; + SIGNAL wire_n11001iO_dataout : STD_LOGIC; + SIGNAL wire_n11001l_dataout : STD_LOGIC; + SIGNAL wire_n11001li_dataout : STD_LOGIC; + SIGNAL wire_n11001ll_dataout : STD_LOGIC; + SIGNAL wire_n11001lO_dataout : STD_LOGIC; + SIGNAL wire_n11001O_dataout : STD_LOGIC; + SIGNAL wire_n11001Oi_dataout : STD_LOGIC; + SIGNAL wire_n11001Ol_dataout : STD_LOGIC; + SIGNAL wire_n11001OO_dataout : STD_LOGIC; + SIGNAL wire_n1100i0i_dataout : STD_LOGIC; + SIGNAL wire_n1100i0l_dataout : STD_LOGIC; + SIGNAL wire_n1100i0O_dataout : STD_LOGIC; + SIGNAL wire_n1100i1i_dataout : STD_LOGIC; + SIGNAL wire_n1100i1l_dataout : STD_LOGIC; + SIGNAL wire_n1100i1O_dataout : STD_LOGIC; + SIGNAL wire_n1100ii_dataout : STD_LOGIC; + SIGNAL wire_n1100iii_dataout : STD_LOGIC; + SIGNAL wire_n1100iil_dataout : STD_LOGIC; + SIGNAL wire_n1100iiO_dataout : STD_LOGIC; + SIGNAL wire_n1100il_dataout : STD_LOGIC; + SIGNAL wire_n1100ili_dataout : STD_LOGIC; + SIGNAL wire_n1100ill_dataout : STD_LOGIC; + SIGNAL wire_n1100ilO_dataout : STD_LOGIC; + SIGNAL wire_n1100iO_dataout : STD_LOGIC; + SIGNAL wire_n1100iOi_dataout : STD_LOGIC; + SIGNAL wire_n1100iOl_dataout : STD_LOGIC; + SIGNAL wire_n1100iOO_dataout : STD_LOGIC; + SIGNAL wire_n1100l0i_dataout : STD_LOGIC; + SIGNAL wire_n1100l0l_dataout : STD_LOGIC; + SIGNAL wire_n1100l0O_dataout : STD_LOGIC; + SIGNAL wire_n1100l1i_dataout : STD_LOGIC; + SIGNAL wire_n1100l1l_dataout : STD_LOGIC; + SIGNAL wire_n1100l1O_dataout : STD_LOGIC; + SIGNAL wire_n1100li_dataout : STD_LOGIC; + SIGNAL wire_n1100lii_dataout : STD_LOGIC; + SIGNAL wire_n1100lil_dataout : STD_LOGIC; + SIGNAL wire_n1100liO_dataout : STD_LOGIC; + SIGNAL wire_n1100ll_dataout : STD_LOGIC; + SIGNAL wire_n1100lli_dataout : STD_LOGIC; + SIGNAL wire_n1100lll_dataout : STD_LOGIC; + SIGNAL wire_n1100llO_dataout : STD_LOGIC; + SIGNAL wire_n1100lO_dataout : STD_LOGIC; + SIGNAL wire_n1100lOi_dataout : STD_LOGIC; + SIGNAL wire_n1100lOl_dataout : STD_LOGIC; + SIGNAL wire_n1100lOO_dataout : STD_LOGIC; + SIGNAL wire_n1100O0i_dataout : STD_LOGIC; + SIGNAL wire_n1100O0l_dataout : STD_LOGIC; + SIGNAL wire_n1100O0O_dataout : STD_LOGIC; + SIGNAL wire_n1100O1i_dataout : STD_LOGIC; + SIGNAL wire_n1100O1l_dataout : STD_LOGIC; + SIGNAL wire_n1100O1O_dataout : STD_LOGIC; + SIGNAL wire_n1100Oi_dataout : STD_LOGIC; + SIGNAL wire_n1100Oii_dataout : STD_LOGIC; + SIGNAL wire_n1100Oil_dataout : STD_LOGIC; + SIGNAL wire_n1100OiO_dataout : STD_LOGIC; + SIGNAL wire_n1100Ol_dataout : STD_LOGIC; + SIGNAL wire_n1100Oli_dataout : STD_LOGIC; + SIGNAL wire_n1100Oll_dataout : STD_LOGIC; + SIGNAL wire_n1100OlO_dataout : STD_LOGIC; + SIGNAL wire_n1100OO_dataout : STD_LOGIC; + SIGNAL wire_n1100OOi_dataout : STD_LOGIC; + SIGNAL wire_n1100OOl_dataout : STD_LOGIC; + SIGNAL wire_n1100OOO_dataout : STD_LOGIC; + SIGNAL wire_n11010i_dataout : STD_LOGIC; + SIGNAL wire_n11010l_dataout : STD_LOGIC; + SIGNAL wire_n11010O_dataout : STD_LOGIC; + SIGNAL wire_n11011i_dataout : STD_LOGIC; + SIGNAL wire_n11011ii_dataout : STD_LOGIC; + SIGNAL wire_n11011l_dataout : STD_LOGIC; + SIGNAL wire_n11011O_dataout : STD_LOGIC; + SIGNAL wire_n1101i0l_dataout : STD_LOGIC; + SIGNAL wire_n1101ii_dataout : STD_LOGIC; + SIGNAL wire_n1101il_dataout : STD_LOGIC; + SIGNAL wire_n1101iO_dataout : STD_LOGIC; + SIGNAL wire_n1101li_dataout : STD_LOGIC; + SIGNAL wire_n1101ll_dataout : STD_LOGIC; + SIGNAL wire_n1101lll_dataout : STD_LOGIC; + SIGNAL wire_n1101llO_dataout : STD_LOGIC; + SIGNAL wire_n1101lO_dataout : STD_LOGIC; + SIGNAL wire_n1101lOi_dataout : STD_LOGIC; + SIGNAL wire_n1101lOl_dataout : STD_LOGIC; + SIGNAL wire_n1101lOO_dataout : STD_LOGIC; + SIGNAL wire_n1101O0i_dataout : STD_LOGIC; + SIGNAL wire_n1101O0l_dataout : STD_LOGIC; + SIGNAL wire_n1101O0O_dataout : STD_LOGIC; + SIGNAL wire_n1101O1i_dataout : STD_LOGIC; + SIGNAL wire_n1101O1l_dataout : STD_LOGIC; + SIGNAL wire_n1101O1O_dataout : STD_LOGIC; + SIGNAL wire_n1101Oi_dataout : STD_LOGIC; + SIGNAL wire_n1101Oii_dataout : STD_LOGIC; + SIGNAL wire_n1101Oil_dataout : STD_LOGIC; + SIGNAL wire_n1101OiO_dataout : STD_LOGIC; + SIGNAL wire_n1101Ol_dataout : STD_LOGIC; + SIGNAL wire_n1101Oli_dataout : STD_LOGIC; + SIGNAL wire_n1101Oll_dataout : STD_LOGIC; + SIGNAL wire_n1101OlO_dataout : STD_LOGIC; + SIGNAL wire_n1101OO_dataout : STD_LOGIC; + SIGNAL wire_n1101OOi_dataout : STD_LOGIC; + SIGNAL wire_n1101OOl_dataout : STD_LOGIC; + SIGNAL wire_n1101OOO_dataout : STD_LOGIC; + SIGNAL wire_n110i00i_dataout : STD_LOGIC; + SIGNAL wire_n110i00l_dataout : STD_LOGIC; + SIGNAL wire_n110i00O_dataout : STD_LOGIC; + SIGNAL wire_n110i01i_dataout : STD_LOGIC; + SIGNAL wire_n110i01l_dataout : STD_LOGIC; + SIGNAL wire_n110i01O_dataout : STD_LOGIC; + SIGNAL wire_n110i0i_dataout : STD_LOGIC; + SIGNAL wire_n110i0ii_dataout : STD_LOGIC; + SIGNAL wire_n110i0il_dataout : STD_LOGIC; + SIGNAL wire_n110i0iO_dataout : STD_LOGIC; + SIGNAL wire_n110i0l_dataout : STD_LOGIC; + SIGNAL wire_n110i0li_dataout : STD_LOGIC; + SIGNAL wire_n110i0ll_dataout : STD_LOGIC; + SIGNAL wire_n110i0lO_dataout : STD_LOGIC; + SIGNAL wire_n110i0O_dataout : STD_LOGIC; + SIGNAL wire_n110i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n110i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n110i0OO_dataout : STD_LOGIC; + SIGNAL wire_n110i10i_dataout : STD_LOGIC; + SIGNAL wire_n110i10l_dataout : STD_LOGIC; + SIGNAL wire_n110i10O_dataout : STD_LOGIC; + SIGNAL wire_n110i11i_dataout : STD_LOGIC; + SIGNAL wire_n110i11l_dataout : STD_LOGIC; + SIGNAL wire_n110i11O_dataout : STD_LOGIC; + SIGNAL wire_n110i1i_dataout : STD_LOGIC; + SIGNAL wire_n110i1ii_dataout : STD_LOGIC; + SIGNAL wire_n110i1il_dataout : STD_LOGIC; + SIGNAL wire_n110i1iO_dataout : STD_LOGIC; + SIGNAL wire_n110i1l_dataout : STD_LOGIC; + SIGNAL wire_n110i1li_dataout : STD_LOGIC; + SIGNAL wire_n110i1ll_dataout : STD_LOGIC; + SIGNAL wire_n110i1lO_dataout : STD_LOGIC; + SIGNAL wire_n110i1O_dataout : STD_LOGIC; + SIGNAL wire_n110i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n110i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n110i1OO_dataout : STD_LOGIC; + SIGNAL wire_n110ii0i_dataout : STD_LOGIC; + SIGNAL wire_n110ii0l_dataout : STD_LOGIC; + SIGNAL wire_n110ii0O_dataout : STD_LOGIC; + SIGNAL wire_n110ii1i_dataout : STD_LOGIC; + SIGNAL wire_n110ii1l_dataout : STD_LOGIC; + SIGNAL wire_n110ii1O_dataout : STD_LOGIC; + SIGNAL wire_n110iii_dataout : STD_LOGIC; + SIGNAL wire_n110iiii_dataout : STD_LOGIC; + SIGNAL wire_n110iiil_dataout : STD_LOGIC; + SIGNAL wire_n110iiiO_dataout : STD_LOGIC; + SIGNAL wire_n110iil_dataout : STD_LOGIC; + SIGNAL wire_n110iili_dataout : STD_LOGIC; + SIGNAL wire_n110iill_dataout : STD_LOGIC; + SIGNAL wire_n110iilO_dataout : STD_LOGIC; + SIGNAL wire_n110iiO_dataout : STD_LOGIC; + SIGNAL wire_n110il0i_dataout : STD_LOGIC; + SIGNAL wire_n110il1l_dataout : STD_LOGIC; + SIGNAL wire_n110il1O_dataout : STD_LOGIC; + SIGNAL wire_n110ili_dataout : STD_LOGIC; + SIGNAL wire_n110ilil_dataout : STD_LOGIC; + SIGNAL wire_n110iliO_dataout : STD_LOGIC; + SIGNAL wire_n110ill_dataout : STD_LOGIC; + SIGNAL wire_n110illi_dataout : STD_LOGIC; + SIGNAL wire_n110illl_dataout : STD_LOGIC; + SIGNAL wire_n110illO_dataout : STD_LOGIC; + SIGNAL wire_n110ilO_dataout : STD_LOGIC; + SIGNAL wire_n110ilOi_dataout : STD_LOGIC; + SIGNAL wire_n110ilOl_dataout : STD_LOGIC; + SIGNAL wire_n110ilOO_dataout : STD_LOGIC; + SIGNAL wire_n110iO0i_dataout : STD_LOGIC; + SIGNAL wire_n110iO0l_dataout : STD_LOGIC; + SIGNAL wire_n110iO0O_dataout : STD_LOGIC; + SIGNAL wire_n110iO1i_dataout : STD_LOGIC; + SIGNAL wire_n110iO1l_dataout : STD_LOGIC; + SIGNAL wire_n110iO1O_dataout : STD_LOGIC; + SIGNAL wire_n110iOi_dataout : STD_LOGIC; + SIGNAL wire_n110iOii_dataout : STD_LOGIC; + SIGNAL wire_n110iOil_dataout : STD_LOGIC; + SIGNAL wire_n110iOiO_dataout : STD_LOGIC; + SIGNAL wire_n110iOl_dataout : STD_LOGIC; + SIGNAL wire_n110iOli_dataout : STD_LOGIC; + SIGNAL wire_n110iOll_dataout : STD_LOGIC; + SIGNAL wire_n110iOlO_dataout : STD_LOGIC; + SIGNAL wire_n110iOO_dataout : STD_LOGIC; + SIGNAL wire_n110iOOi_dataout : STD_LOGIC; + SIGNAL wire_n110iOOl_dataout : STD_LOGIC; + SIGNAL wire_n110iOOO_dataout : STD_LOGIC; + SIGNAL wire_n110l00i_dataout : STD_LOGIC; + SIGNAL wire_n110l00l_dataout : STD_LOGIC; + SIGNAL wire_n110l00O_dataout : STD_LOGIC; + SIGNAL wire_n110l01i_dataout : STD_LOGIC; + SIGNAL wire_n110l01l_dataout : STD_LOGIC; + SIGNAL wire_n110l01O_dataout : STD_LOGIC; + SIGNAL wire_n110l0i_dataout : STD_LOGIC; + SIGNAL wire_n110l0ii_dataout : STD_LOGIC; + SIGNAL wire_n110l0il_dataout : STD_LOGIC; + SIGNAL wire_n110l0iO_dataout : STD_LOGIC; + SIGNAL wire_n110l0l_dataout : STD_LOGIC; + SIGNAL wire_n110l0li_dataout : STD_LOGIC; + SIGNAL wire_n110l0ll_dataout : STD_LOGIC; + SIGNAL wire_n110l0lO_dataout : STD_LOGIC; + SIGNAL wire_n110l0O_dataout : STD_LOGIC; + SIGNAL wire_n110l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n110l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n110l0OO_dataout : STD_LOGIC; + SIGNAL wire_n110l11i_dataout : STD_LOGIC; + SIGNAL wire_n110l1i_dataout : STD_LOGIC; + SIGNAL wire_n110l1l_dataout : STD_LOGIC; + SIGNAL wire_n110l1lO_dataout : STD_LOGIC; + SIGNAL wire_n110l1O_dataout : STD_LOGIC; + SIGNAL wire_n110l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n110l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n110l1OO_dataout : STD_LOGIC; + SIGNAL wire_n110li0i_dataout : STD_LOGIC; + SIGNAL wire_n110li0l_dataout : STD_LOGIC; + SIGNAL wire_n110li0O_dataout : STD_LOGIC; + SIGNAL wire_n110li1i_dataout : STD_LOGIC; + SIGNAL wire_n110li1l_dataout : STD_LOGIC; + SIGNAL wire_n110li1O_dataout : STD_LOGIC; + SIGNAL wire_n110lii_dataout : STD_LOGIC; + SIGNAL wire_n110liii_dataout : STD_LOGIC; + SIGNAL wire_n110liil_dataout : STD_LOGIC; + SIGNAL wire_n110liiO_dataout : STD_LOGIC; + SIGNAL wire_n110lil_dataout : STD_LOGIC; + SIGNAL wire_n110lili_dataout : STD_LOGIC; + SIGNAL wire_n110lill_dataout : STD_LOGIC; + SIGNAL wire_n110lilO_dataout : STD_LOGIC; + SIGNAL wire_n110liO_dataout : STD_LOGIC; + SIGNAL wire_n110liOi_dataout : STD_LOGIC; + SIGNAL wire_n110liOl_dataout : STD_LOGIC; + SIGNAL wire_n110liOO_dataout : STD_LOGIC; + SIGNAL wire_n110ll0i_dataout : STD_LOGIC; + SIGNAL wire_n110ll0l_dataout : STD_LOGIC; + SIGNAL wire_n110ll0O_dataout : STD_LOGIC; + SIGNAL wire_n110ll1i_dataout : STD_LOGIC; + SIGNAL wire_n110ll1l_dataout : STD_LOGIC; + SIGNAL wire_n110ll1O_dataout : STD_LOGIC; + SIGNAL wire_n110lli_dataout : STD_LOGIC; + SIGNAL wire_n110llii_dataout : STD_LOGIC; + SIGNAL wire_n110llil_dataout : STD_LOGIC; + SIGNAL wire_n110lliO_dataout : STD_LOGIC; + SIGNAL wire_n110lll_dataout : STD_LOGIC; + SIGNAL wire_n110llli_dataout : STD_LOGIC; + SIGNAL wire_n110llll_dataout : STD_LOGIC; + SIGNAL wire_n110lllO_dataout : STD_LOGIC; + SIGNAL wire_n110llO_dataout : STD_LOGIC; + SIGNAL wire_n110llOi_dataout : STD_LOGIC; + SIGNAL wire_n110llOl_dataout : STD_LOGIC; + SIGNAL wire_n110llOO_dataout : STD_LOGIC; + SIGNAL wire_n110lO0i_dataout : STD_LOGIC; + SIGNAL wire_n110lO0l_dataout : STD_LOGIC; + SIGNAL wire_n110lO0O_dataout : STD_LOGIC; + SIGNAL wire_n110lO1i_dataout : STD_LOGIC; + SIGNAL wire_n110lO1l_dataout : STD_LOGIC; + SIGNAL wire_n110lO1O_dataout : STD_LOGIC; + SIGNAL wire_n110lOi_dataout : STD_LOGIC; + SIGNAL wire_n110lOii_dataout : STD_LOGIC; + SIGNAL wire_n110lOl_dataout : STD_LOGIC; + SIGNAL wire_n110lOO_dataout : STD_LOGIC; + SIGNAL wire_n110lOOi_dataout : STD_LOGIC; + SIGNAL wire_n110lOOl_dataout : STD_LOGIC; + SIGNAL wire_n110lOOO_dataout : STD_LOGIC; + SIGNAL wire_n110O00i_dataout : STD_LOGIC; + SIGNAL wire_n110O00l_dataout : STD_LOGIC; + SIGNAL wire_n110O00O_dataout : STD_LOGIC; + SIGNAL wire_n110O01i_dataout : STD_LOGIC; + SIGNAL wire_n110O01l_dataout : STD_LOGIC; + SIGNAL wire_n110O01O_dataout : STD_LOGIC; + SIGNAL wire_n110O0i_dataout : STD_LOGIC; + SIGNAL wire_n110O0ii_dataout : STD_LOGIC; + SIGNAL wire_n110O0il_dataout : STD_LOGIC; + SIGNAL wire_n110O0iO_dataout : STD_LOGIC; + SIGNAL wire_n110O0l_dataout : STD_LOGIC; + SIGNAL wire_n110O0li_dataout : STD_LOGIC; + SIGNAL wire_n110O0ll_dataout : STD_LOGIC; + SIGNAL wire_n110O0lO_dataout : STD_LOGIC; + SIGNAL wire_n110O0O_dataout : STD_LOGIC; + SIGNAL wire_n110O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n110O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n110O0OO_dataout : STD_LOGIC; + SIGNAL wire_n110O10i_dataout : STD_LOGIC; + SIGNAL wire_n110O10l_dataout : STD_LOGIC; + SIGNAL wire_n110O10O_dataout : STD_LOGIC; + SIGNAL wire_n110O11i_dataout : STD_LOGIC; + SIGNAL wire_n110O11l_dataout : STD_LOGIC; + SIGNAL wire_n110O11O_dataout : STD_LOGIC; + SIGNAL wire_n110O1i_dataout : STD_LOGIC; + SIGNAL wire_n110O1ii_dataout : STD_LOGIC; + SIGNAL wire_n110O1il_dataout : STD_LOGIC; + SIGNAL wire_n110O1iO_dataout : STD_LOGIC; + SIGNAL wire_n110O1l_dataout : STD_LOGIC; + SIGNAL wire_n110O1li_dataout : STD_LOGIC; + SIGNAL wire_n110O1ll_dataout : STD_LOGIC; + SIGNAL wire_n110O1lO_dataout : STD_LOGIC; + SIGNAL wire_n110O1O_dataout : STD_LOGIC; + SIGNAL wire_n110O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n110O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n110O1OO_dataout : STD_LOGIC; + SIGNAL wire_n110Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n110Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n110Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n110Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n110Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n110Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n110Oii_dataout : STD_LOGIC; + SIGNAL wire_n110Oiii_dataout : STD_LOGIC; + SIGNAL wire_n110Oiil_dataout : STD_LOGIC; + SIGNAL wire_n110OiiO_dataout : STD_LOGIC; + SIGNAL wire_n110Oil_dataout : STD_LOGIC; + SIGNAL wire_n110Oili_dataout : STD_LOGIC; + SIGNAL wire_n110Oill_dataout : STD_LOGIC; + SIGNAL wire_n110OilO_dataout : STD_LOGIC; + SIGNAL wire_n110OiO_dataout : STD_LOGIC; + SIGNAL wire_n110OiOi_dataout : STD_LOGIC; + SIGNAL wire_n110OiOl_dataout : STD_LOGIC; + SIGNAL wire_n110OiOO_dataout : STD_LOGIC; + SIGNAL wire_n110Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n110Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n110Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n110Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n110Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n110Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n110Oli_dataout : STD_LOGIC; + SIGNAL wire_n110Olii_dataout : STD_LOGIC; + SIGNAL wire_n110Olil_dataout : STD_LOGIC; + SIGNAL wire_n110Oll_dataout : STD_LOGIC; + SIGNAL wire_n110Olll_dataout : STD_LOGIC; + SIGNAL wire_n110OllO_dataout : STD_LOGIC; + SIGNAL wire_n110OlOi_dataout : STD_LOGIC; + SIGNAL wire_n110OlOl_dataout : STD_LOGIC; + SIGNAL wire_n110OlOO_dataout : STD_LOGIC; + SIGNAL wire_n110OO0O_dataout : STD_LOGIC; + SIGNAL wire_n110OO1i_dataout : STD_LOGIC; + SIGNAL wire_n110OO1l_dataout : STD_LOGIC; + SIGNAL wire_n110OO1O_dataout : STD_LOGIC; + SIGNAL wire_n110OOO_dataout : STD_LOGIC; + SIGNAL wire_n111000O_dataout : STD_LOGIC; + SIGNAL wire_n111001l_dataout : STD_LOGIC; + SIGNAL wire_n111001O_dataout : STD_LOGIC; + SIGNAL wire_n11100i_dataout : STD_LOGIC; + SIGNAL wire_n11100ii_dataout : STD_LOGIC; + SIGNAL wire_n11100l_dataout : STD_LOGIC; + SIGNAL wire_n11100li_dataout : STD_LOGIC; + SIGNAL wire_n11100ll_dataout : STD_LOGIC; + SIGNAL wire_n11100O_dataout : STD_LOGIC; + SIGNAL wire_n11100Ol_dataout : STD_LOGIC; + SIGNAL wire_n11100OO_dataout : STD_LOGIC; + SIGNAL wire_n11101i_dataout : STD_LOGIC; + SIGNAL wire_n11101il_dataout : STD_LOGIC; + SIGNAL wire_n11101iO_dataout : STD_LOGIC; + SIGNAL wire_n11101l_dataout : STD_LOGIC; + SIGNAL wire_n11101li_dataout : STD_LOGIC; + SIGNAL wire_n11101ll_dataout : STD_LOGIC; + SIGNAL wire_n11101lO_dataout : STD_LOGIC; + SIGNAL wire_n11101O_dataout : STD_LOGIC; + SIGNAL wire_n11101Oi_dataout : STD_LOGIC; + SIGNAL wire_n11101Ol_dataout : STD_LOGIC; + SIGNAL wire_n11101OO_dataout : STD_LOGIC; + SIGNAL wire_n1110i0i_dataout : STD_LOGIC; + SIGNAL wire_n1110i1O_dataout : STD_LOGIC; + SIGNAL wire_n1110ii_dataout : STD_LOGIC; + SIGNAL wire_n1110iii_dataout : STD_LOGIC; + SIGNAL wire_n1110iil_dataout : STD_LOGIC; + SIGNAL wire_n1110il_dataout : STD_LOGIC; + SIGNAL wire_n1110ill_dataout : STD_LOGIC; + SIGNAL wire_n1110ilO_dataout : STD_LOGIC; + SIGNAL wire_n1110iO_dataout : STD_LOGIC; + SIGNAL wire_n1110iOO_dataout : STD_LOGIC; + SIGNAL wire_n1110l0i_dataout : STD_LOGIC; + SIGNAL wire_n1110l0l_dataout : STD_LOGIC; + SIGNAL wire_n1110l0O_dataout : STD_LOGIC; + SIGNAL wire_n1110l1i_dataout : STD_LOGIC; + SIGNAL wire_n1110li_dataout : STD_LOGIC; + SIGNAL wire_n1110lii_dataout : STD_LOGIC; + SIGNAL wire_n1110lil_dataout : STD_LOGIC; + SIGNAL wire_n1110liO_dataout : STD_LOGIC; + SIGNAL wire_n1110ll_dataout : STD_LOGIC; + SIGNAL wire_n1110lli_dataout : STD_LOGIC; + SIGNAL wire_n1110lll_dataout : STD_LOGIC; + SIGNAL wire_n1110lO_dataout : STD_LOGIC; + SIGNAL wire_n1110Oi_dataout : STD_LOGIC; + SIGNAL wire_n1110Ol_dataout : STD_LOGIC; + SIGNAL wire_n1110OO_dataout : STD_LOGIC; + SIGNAL wire_n111100i_dataout : STD_LOGIC; + SIGNAL wire_n111100l_dataout : STD_LOGIC; + SIGNAL wire_n111100O_dataout : STD_LOGIC; + SIGNAL wire_n111101i_dataout : STD_LOGIC; + SIGNAL wire_n111101l_dataout : STD_LOGIC; + SIGNAL wire_n111101O_dataout : STD_LOGIC; + SIGNAL wire_n11110i_dataout : STD_LOGIC; + SIGNAL wire_n11110ii_dataout : STD_LOGIC; + SIGNAL wire_n11110il_dataout : STD_LOGIC; + SIGNAL wire_n11110iO_dataout : STD_LOGIC; + SIGNAL wire_n11110l_dataout : STD_LOGIC; + SIGNAL wire_n11110li_dataout : STD_LOGIC; + SIGNAL wire_n11110ll_dataout : STD_LOGIC; + SIGNAL wire_n11110O_dataout : STD_LOGIC; + SIGNAL wire_n111110i_dataout : STD_LOGIC; + SIGNAL wire_n111110l_dataout : STD_LOGIC; + SIGNAL wire_n111110O_dataout : STD_LOGIC; + SIGNAL wire_n111111i_dataout : STD_LOGIC; + SIGNAL wire_n111111l_dataout : STD_LOGIC; + SIGNAL wire_n111111O_dataout : STD_LOGIC; + SIGNAL wire_n11111i_dataout : STD_LOGIC; + SIGNAL wire_n11111ii_dataout : STD_LOGIC; + SIGNAL wire_n11111il_dataout : STD_LOGIC; + SIGNAL wire_n11111iO_dataout : STD_LOGIC; + SIGNAL wire_n11111l_dataout : STD_LOGIC; + SIGNAL wire_n11111li_dataout : STD_LOGIC; + SIGNAL wire_n11111ll_dataout : STD_LOGIC; + SIGNAL wire_n11111lO_dataout : STD_LOGIC; + SIGNAL wire_n11111O_dataout : STD_LOGIC; + SIGNAL wire_n11111Oi_dataout : STD_LOGIC; + SIGNAL wire_n11111Ol_dataout : STD_LOGIC; + SIGNAL wire_n11111OO_dataout : STD_LOGIC; + SIGNAL wire_n1111i0l_dataout : STD_LOGIC; + SIGNAL wire_n1111i0O_dataout : STD_LOGIC; + SIGNAL wire_n1111ii_dataout : STD_LOGIC; + SIGNAL wire_n1111iii_dataout : STD_LOGIC; + SIGNAL wire_n1111iil_dataout : STD_LOGIC; + SIGNAL wire_n1111iiO_dataout : STD_LOGIC; + SIGNAL wire_n1111il_dataout : STD_LOGIC; + SIGNAL wire_n1111ili_dataout : STD_LOGIC; + SIGNAL wire_n1111ill_dataout : STD_LOGIC; + SIGNAL wire_n1111ilO_dataout : STD_LOGIC; + SIGNAL wire_n1111iO_dataout : STD_LOGIC; + SIGNAL wire_n1111l0O_dataout : STD_LOGIC; + SIGNAL wire_n1111li_dataout : STD_LOGIC; + SIGNAL wire_n1111lii_dataout : STD_LOGIC; + SIGNAL wire_n1111lil_dataout : STD_LOGIC; + SIGNAL wire_n1111liO_dataout : STD_LOGIC; + SIGNAL wire_n1111ll_dataout : STD_LOGIC; + SIGNAL wire_n1111lli_dataout : STD_LOGIC; + SIGNAL wire_n1111lll_dataout : STD_LOGIC; + SIGNAL wire_n1111llO_dataout : STD_LOGIC; + SIGNAL wire_n1111lO_dataout : STD_LOGIC; + SIGNAL wire_n1111lOi_dataout : STD_LOGIC; + SIGNAL wire_n1111lOl_dataout : STD_LOGIC; + SIGNAL wire_n1111lOO_dataout : STD_LOGIC; + SIGNAL wire_n1111O0i_dataout : STD_LOGIC; + SIGNAL wire_n1111O0l_dataout : STD_LOGIC; + SIGNAL wire_n1111O0O_dataout : STD_LOGIC; + SIGNAL wire_n1111O1i_dataout : STD_LOGIC; + SIGNAL wire_n1111O1l_dataout : STD_LOGIC; + SIGNAL wire_n1111O1O_dataout : STD_LOGIC; + SIGNAL wire_n1111Oi_dataout : STD_LOGIC; + SIGNAL wire_n1111Ol_dataout : STD_LOGIC; + SIGNAL wire_n1111OO_dataout : STD_LOGIC; + SIGNAL wire_n111i0i_dataout : STD_LOGIC; + SIGNAL wire_n111i0iO_dataout : STD_LOGIC; + SIGNAL wire_n111i0l_dataout : STD_LOGIC; + SIGNAL wire_n111i0li_dataout : STD_LOGIC; + SIGNAL wire_n111i0ll_dataout : STD_LOGIC; + SIGNAL wire_n111i0lO_dataout : STD_LOGIC; + SIGNAL wire_n111i0O_dataout : STD_LOGIC; + SIGNAL wire_n111i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n111i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n111i0OO_dataout : STD_LOGIC; + SIGNAL wire_n111i1i_dataout : STD_LOGIC; + SIGNAL wire_n111i1l_dataout : STD_LOGIC; + SIGNAL wire_n111i1O_dataout : STD_LOGIC; + SIGNAL wire_n111ii0i_dataout : STD_LOGIC; + SIGNAL wire_n111ii0l_dataout : STD_LOGIC; + SIGNAL wire_n111ii0O_dataout : STD_LOGIC; + SIGNAL wire_n111ii1i_dataout : STD_LOGIC; + SIGNAL wire_n111ii1l_dataout : STD_LOGIC; + SIGNAL wire_n111ii1O_dataout : STD_LOGIC; + SIGNAL wire_n111iii_dataout : STD_LOGIC; + SIGNAL wire_n111iiii_dataout : STD_LOGIC; + SIGNAL wire_n111iiil_dataout : STD_LOGIC; + SIGNAL wire_n111iiiO_dataout : STD_LOGIC; + SIGNAL wire_n111iil_dataout : STD_LOGIC; + SIGNAL wire_n111iili_dataout : STD_LOGIC; + SIGNAL wire_n111iill_dataout : STD_LOGIC; + SIGNAL wire_n111iilO_dataout : STD_LOGIC; + SIGNAL wire_n111iiO_dataout : STD_LOGIC; + SIGNAL wire_n111iiOi_dataout : STD_LOGIC; + SIGNAL wire_n111iiOl_dataout : STD_LOGIC; + SIGNAL wire_n111iiOO_dataout : STD_LOGIC; + SIGNAL wire_n111il0i_dataout : STD_LOGIC; + SIGNAL wire_n111il0l_dataout : STD_LOGIC; + SIGNAL wire_n111il0O_dataout : STD_LOGIC; + SIGNAL wire_n111il1i_dataout : STD_LOGIC; + SIGNAL wire_n111il1l_dataout : STD_LOGIC; + SIGNAL wire_n111il1O_dataout : STD_LOGIC; + SIGNAL wire_n111ili_dataout : STD_LOGIC; + SIGNAL wire_n111ilii_dataout : STD_LOGIC; + SIGNAL wire_n111ilil_dataout : STD_LOGIC; + SIGNAL wire_n111iliO_dataout : STD_LOGIC; + SIGNAL wire_n111ill_dataout : STD_LOGIC; + SIGNAL wire_n111illi_dataout : STD_LOGIC; + SIGNAL wire_n111illl_dataout : STD_LOGIC; + SIGNAL wire_n111illO_dataout : STD_LOGIC; + SIGNAL wire_n111ilO_dataout : STD_LOGIC; + SIGNAL wire_n111ilOi_dataout : STD_LOGIC; + SIGNAL wire_n111ilOl_dataout : STD_LOGIC; + SIGNAL wire_n111iO1i_dataout : STD_LOGIC; + SIGNAL wire_n111iO1l_dataout : STD_LOGIC; + SIGNAL wire_n111iO1O_dataout : STD_LOGIC; + SIGNAL wire_n111iOi_dataout : STD_LOGIC; + SIGNAL wire_n111iOl_dataout : STD_LOGIC; + SIGNAL wire_n111iOO_dataout : STD_LOGIC; + SIGNAL wire_n111l01i_dataout : STD_LOGIC; + SIGNAL wire_n111l0i_dataout : STD_LOGIC; + SIGNAL wire_n111l0l_dataout : STD_LOGIC; + SIGNAL wire_n111l0O_dataout : STD_LOGIC; + SIGNAL wire_n111l11i_dataout : STD_LOGIC; + SIGNAL wire_n111l1i_dataout : STD_LOGIC; + SIGNAL wire_n111l1l_dataout : STD_LOGIC; + SIGNAL wire_n111l1ll_dataout : STD_LOGIC; + SIGNAL wire_n111l1lO_dataout : STD_LOGIC; + SIGNAL wire_n111l1O_dataout : STD_LOGIC; + SIGNAL wire_n111l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n111l1OO_dataout : STD_LOGIC; + SIGNAL wire_n111lii_dataout : STD_LOGIC; + SIGNAL wire_n111lil_dataout : STD_LOGIC; + SIGNAL wire_n111liO_dataout : STD_LOGIC; + SIGNAL wire_n111lli_dataout : STD_LOGIC; + SIGNAL wire_n111llii_dataout : STD_LOGIC; + SIGNAL wire_n111llil_dataout : STD_LOGIC; + SIGNAL wire_n111lliO_dataout : STD_LOGIC; + SIGNAL wire_n111lll_dataout : STD_LOGIC; + SIGNAL wire_n111llli_dataout : STD_LOGIC; + SIGNAL wire_n111llO_dataout : STD_LOGIC; + SIGNAL wire_n111lO0i_dataout : STD_LOGIC; + SIGNAL wire_n111lO0l_dataout : STD_LOGIC; + SIGNAL wire_n111lO0O_dataout : STD_LOGIC; + SIGNAL wire_n111lO1l_dataout : STD_LOGIC; + SIGNAL wire_n111lOi_dataout : STD_LOGIC; + SIGNAL wire_n111lOii_dataout : STD_LOGIC; + SIGNAL wire_n111lOil_dataout : STD_LOGIC; + SIGNAL wire_n111lOiO_dataout : STD_LOGIC; + SIGNAL wire_n111lOl_dataout : STD_LOGIC; + SIGNAL wire_n111lOli_dataout : STD_LOGIC; + SIGNAL wire_n111lOll_dataout : STD_LOGIC; + SIGNAL wire_n111lOlO_dataout : STD_LOGIC; + SIGNAL wire_n111lOO_dataout : STD_LOGIC; + SIGNAL wire_n111lOOi_dataout : STD_LOGIC; + SIGNAL wire_n111lOOl_dataout : STD_LOGIC; + SIGNAL wire_n111lOOO_dataout : STD_LOGIC; + SIGNAL wire_n111O00i_dataout : STD_LOGIC; + SIGNAL wire_n111O00l_dataout : STD_LOGIC; + SIGNAL wire_n111O00O_dataout : STD_LOGIC; + SIGNAL wire_n111O01i_dataout : STD_LOGIC; + SIGNAL wire_n111O01l_dataout : STD_LOGIC; + SIGNAL wire_n111O01O_dataout : STD_LOGIC; + SIGNAL wire_n111O0i_dataout : STD_LOGIC; + SIGNAL wire_n111O0ii_dataout : STD_LOGIC; + SIGNAL wire_n111O0il_dataout : STD_LOGIC; + SIGNAL wire_n111O0iO_dataout : STD_LOGIC; + SIGNAL wire_n111O0l_dataout : STD_LOGIC; + SIGNAL wire_n111O0li_dataout : STD_LOGIC; + SIGNAL wire_n111O0ll_dataout : STD_LOGIC; + SIGNAL wire_n111O0lO_dataout : STD_LOGIC; + SIGNAL wire_n111O0O_dataout : STD_LOGIC; + SIGNAL wire_n111O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n111O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n111O0OO_dataout : STD_LOGIC; + SIGNAL wire_n111O10i_dataout : STD_LOGIC; + SIGNAL wire_n111O10l_dataout : STD_LOGIC; + SIGNAL wire_n111O10O_dataout : STD_LOGIC; + SIGNAL wire_n111O11i_dataout : STD_LOGIC; + SIGNAL wire_n111O11l_dataout : STD_LOGIC; + SIGNAL wire_n111O11O_dataout : STD_LOGIC; + SIGNAL wire_n111O1i_dataout : STD_LOGIC; + SIGNAL wire_n111O1ii_dataout : STD_LOGIC; + SIGNAL wire_n111O1il_dataout : STD_LOGIC; + SIGNAL wire_n111O1iO_dataout : STD_LOGIC; + SIGNAL wire_n111O1l_dataout : STD_LOGIC; + SIGNAL wire_n111O1li_dataout : STD_LOGIC; + SIGNAL wire_n111O1ll_dataout : STD_LOGIC; + SIGNAL wire_n111O1lO_dataout : STD_LOGIC; + SIGNAL wire_n111O1O_dataout : STD_LOGIC; + SIGNAL wire_n111O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n111O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n111O1OO_dataout : STD_LOGIC; + SIGNAL wire_n111Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n111Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n111Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n111Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n111Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n111Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n111Oii_dataout : STD_LOGIC; + SIGNAL wire_n111Oiii_dataout : STD_LOGIC; + SIGNAL wire_n111Oiil_dataout : STD_LOGIC; + SIGNAL wire_n111OiiO_dataout : STD_LOGIC; + SIGNAL wire_n111Oil_dataout : STD_LOGIC; + SIGNAL wire_n111Oili_dataout : STD_LOGIC; + SIGNAL wire_n111Oill_dataout : STD_LOGIC; + SIGNAL wire_n111OilO_dataout : STD_LOGIC; + SIGNAL wire_n111OiO_dataout : STD_LOGIC; + SIGNAL wire_n111OiOi_dataout : STD_LOGIC; + SIGNAL wire_n111OiOl_dataout : STD_LOGIC; + SIGNAL wire_n111OiOO_dataout : STD_LOGIC; + SIGNAL wire_n111Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n111Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n111Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n111Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n111Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n111Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n111Oli_dataout : STD_LOGIC; + SIGNAL wire_n111Olii_dataout : STD_LOGIC; + SIGNAL wire_n111Oll_dataout : STD_LOGIC; + SIGNAL wire_n111OlO_dataout : STD_LOGIC; + SIGNAL wire_n111OlOO_dataout : STD_LOGIC; + SIGNAL wire_n111OO1i_dataout : STD_LOGIC; + SIGNAL wire_n111OOi_dataout : STD_LOGIC; + SIGNAL wire_n111OOl_dataout : STD_LOGIC; + SIGNAL wire_n111OOO_dataout : STD_LOGIC; + SIGNAL wire_n11i000i_dataout : STD_LOGIC; + SIGNAL wire_n11i000l_dataout : STD_LOGIC; + SIGNAL wire_n11i000O_dataout : STD_LOGIC; + SIGNAL wire_n11i001i_dataout : STD_LOGIC; + SIGNAL wire_n11i001l_dataout : STD_LOGIC; + SIGNAL wire_n11i001O_dataout : STD_LOGIC; + SIGNAL wire_n11i00i_dataout : STD_LOGIC; + SIGNAL wire_n11i00ii_dataout : STD_LOGIC; + SIGNAL wire_n11i00il_dataout : STD_LOGIC; + SIGNAL wire_n11i00iO_dataout : STD_LOGIC; + SIGNAL wire_n11i00l_dataout : STD_LOGIC; + SIGNAL wire_n11i00li_dataout : STD_LOGIC; + SIGNAL wire_n11i00ll_dataout : STD_LOGIC; + SIGNAL wire_n11i00lO_dataout : STD_LOGIC; + SIGNAL wire_n11i00O_dataout : STD_LOGIC; + SIGNAL wire_n11i00Oi_dataout : STD_LOGIC; + SIGNAL wire_n11i00Ol_dataout : STD_LOGIC; + SIGNAL wire_n11i00OO_dataout : STD_LOGIC; + SIGNAL wire_n11i010i_dataout : STD_LOGIC; + SIGNAL wire_n11i010l_dataout : STD_LOGIC; + SIGNAL wire_n11i010O_dataout : STD_LOGIC; + SIGNAL wire_n11i011i_dataout : STD_LOGIC; + SIGNAL wire_n11i011l_dataout : STD_LOGIC; + SIGNAL wire_n11i011O_dataout : STD_LOGIC; + SIGNAL wire_n11i01i_dataout : STD_LOGIC; + SIGNAL wire_n11i01ii_dataout : STD_LOGIC; + SIGNAL wire_n11i01il_dataout : STD_LOGIC; + SIGNAL wire_n11i01iO_dataout : STD_LOGIC; + SIGNAL wire_n11i01l_dataout : STD_LOGIC; + SIGNAL wire_n11i01li_dataout : STD_LOGIC; + SIGNAL wire_n11i01ll_dataout : STD_LOGIC; + SIGNAL wire_n11i01lO_dataout : STD_LOGIC; + SIGNAL wire_n11i01O_dataout : STD_LOGIC; + SIGNAL wire_n11i01Oi_dataout : STD_LOGIC; + SIGNAL wire_n11i01Ol_dataout : STD_LOGIC; + SIGNAL wire_n11i01OO_dataout : STD_LOGIC; + SIGNAL wire_n11i0i0i_dataout : STD_LOGIC; + SIGNAL wire_n11i0i0l_dataout : STD_LOGIC; + SIGNAL wire_n11i0i0O_dataout : STD_LOGIC; + SIGNAL wire_n11i0i1i_dataout : STD_LOGIC; + SIGNAL wire_n11i0i1l_dataout : STD_LOGIC; + SIGNAL wire_n11i0i1O_dataout : STD_LOGIC; + SIGNAL wire_n11i0ii_dataout : STD_LOGIC; + SIGNAL wire_n11i0iii_dataout : STD_LOGIC; + SIGNAL wire_n11i0iil_dataout : STD_LOGIC; + SIGNAL wire_n11i0iiO_dataout : STD_LOGIC; + SIGNAL wire_n11i0il_dataout : STD_LOGIC; + SIGNAL wire_n11i0ili_dataout : STD_LOGIC; + SIGNAL wire_n11i0ill_dataout : STD_LOGIC; + SIGNAL wire_n11i0ilO_dataout : STD_LOGIC; + SIGNAL wire_n11i0iO_dataout : STD_LOGIC; + SIGNAL wire_n11i0iOi_dataout : STD_LOGIC; + SIGNAL wire_n11i0iOl_dataout : STD_LOGIC; + SIGNAL wire_n11i0iOO_dataout : STD_LOGIC; + SIGNAL wire_n11i0l0i_dataout : STD_LOGIC; + SIGNAL wire_n11i0l0l_dataout : STD_LOGIC; + SIGNAL wire_n11i0l0O_dataout : STD_LOGIC; + SIGNAL wire_n11i0l1i_dataout : STD_LOGIC; + SIGNAL wire_n11i0l1l_dataout : STD_LOGIC; + SIGNAL wire_n11i0l1O_dataout : STD_LOGIC; + SIGNAL wire_n11i0li_dataout : STD_LOGIC; + SIGNAL wire_n11i0lii_dataout : STD_LOGIC; + SIGNAL wire_n11i0lil_dataout : STD_LOGIC; + SIGNAL wire_n11i0liO_dataout : STD_LOGIC; + SIGNAL wire_n11i0ll_dataout : STD_LOGIC; + SIGNAL wire_n11i0lli_dataout : STD_LOGIC; + SIGNAL wire_n11i0lll_dataout : STD_LOGIC; + SIGNAL wire_n11i0llO_dataout : STD_LOGIC; + SIGNAL wire_n11i0lO_dataout : STD_LOGIC; + SIGNAL wire_n11i0lOi_dataout : STD_LOGIC; + SIGNAL wire_n11i0lOl_dataout : STD_LOGIC; + SIGNAL wire_n11i0lOO_dataout : STD_LOGIC; + SIGNAL wire_n11i0O0i_dataout : STD_LOGIC; + SIGNAL wire_n11i0O0l_dataout : STD_LOGIC; + SIGNAL wire_n11i0O0O_dataout : STD_LOGIC; + SIGNAL wire_n11i0O1i_dataout : STD_LOGIC; + SIGNAL wire_n11i0O1l_dataout : STD_LOGIC; + SIGNAL wire_n11i0O1O_dataout : STD_LOGIC; + SIGNAL wire_n11i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11i0Oii_dataout : STD_LOGIC; + SIGNAL wire_n11i0Oil_dataout : STD_LOGIC; + SIGNAL wire_n11i0OiO_dataout : STD_LOGIC; + SIGNAL wire_n11i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11i0Oli_dataout : STD_LOGIC; + SIGNAL wire_n11i0Oll_dataout : STD_LOGIC; + SIGNAL wire_n11i0OlO_dataout : STD_LOGIC; + SIGNAL wire_n11i0OO_dataout : STD_LOGIC; + SIGNAL wire_n11i0OOi_dataout : STD_LOGIC; + SIGNAL wire_n11i0OOl_dataout : STD_LOGIC; + SIGNAL wire_n11i0OOO_dataout : STD_LOGIC; + SIGNAL wire_n11i100i_dataout : STD_LOGIC; + SIGNAL wire_n11i100l_dataout : STD_LOGIC; + SIGNAL wire_n11i100O_dataout : STD_LOGIC; + SIGNAL wire_n11i101i_dataout : STD_LOGIC; + SIGNAL wire_n11i101l_dataout : STD_LOGIC; + SIGNAL wire_n11i101O_dataout : STD_LOGIC; + SIGNAL wire_n11i10i_dataout : STD_LOGIC; + SIGNAL wire_n11i10ii_dataout : STD_LOGIC; + SIGNAL wire_n11i10l_dataout : STD_LOGIC; + SIGNAL wire_n11i10ll_dataout : STD_LOGIC; + SIGNAL wire_n11i10lO_dataout : STD_LOGIC; + SIGNAL wire_n11i10O_dataout : STD_LOGIC; + SIGNAL wire_n11i10OO_dataout : STD_LOGIC; + SIGNAL wire_n11i110l_dataout : STD_LOGIC; + SIGNAL wire_n11i110O_dataout : STD_LOGIC; + SIGNAL wire_n11i11i_dataout : STD_LOGIC; + SIGNAL wire_n11i11ii_dataout : STD_LOGIC; + SIGNAL wire_n11i11il_dataout : STD_LOGIC; + SIGNAL wire_n11i11iO_dataout : STD_LOGIC; + SIGNAL wire_n11i11l_dataout : STD_LOGIC; + SIGNAL wire_n11i11li_dataout : STD_LOGIC; + SIGNAL wire_n11i11ll_dataout : STD_LOGIC; + SIGNAL wire_n11i11lO_dataout : STD_LOGIC; + SIGNAL wire_n11i11O_dataout : STD_LOGIC; + SIGNAL wire_n11i11Oi_dataout : STD_LOGIC; + SIGNAL wire_n11i11Ol_dataout : STD_LOGIC; + SIGNAL wire_n11i11OO_dataout : STD_LOGIC; + SIGNAL wire_n11i1i1i_dataout : STD_LOGIC; + SIGNAL wire_n11i1i1l_dataout : STD_LOGIC; + SIGNAL wire_n11i1i1O_dataout : STD_LOGIC; + SIGNAL wire_n11i1ii_dataout : STD_LOGIC; + SIGNAL wire_n11i1iii_dataout : STD_LOGIC; + SIGNAL wire_n11i1iil_dataout : STD_LOGIC; + SIGNAL wire_n11i1iiO_dataout : STD_LOGIC; + SIGNAL wire_n11i1il_dataout : STD_LOGIC; + SIGNAL wire_n11i1ili_dataout : STD_LOGIC; + SIGNAL wire_n11i1ill_dataout : STD_LOGIC; + SIGNAL wire_n11i1ilO_dataout : STD_LOGIC; + SIGNAL wire_n11i1iO_dataout : STD_LOGIC; + SIGNAL wire_n11i1iOi_dataout : STD_LOGIC; + SIGNAL wire_n11i1iOl_dataout : STD_LOGIC; + SIGNAL wire_n11i1iOO_dataout : STD_LOGIC; + SIGNAL wire_n11i1l0i_dataout : STD_LOGIC; + SIGNAL wire_n11i1l0l_dataout : STD_LOGIC; + SIGNAL wire_n11i1l0O_dataout : STD_LOGIC; + SIGNAL wire_n11i1l1i_dataout : STD_LOGIC; + SIGNAL wire_n11i1l1l_dataout : STD_LOGIC; + SIGNAL wire_n11i1l1O_dataout : STD_LOGIC; + SIGNAL wire_n11i1li_dataout : STD_LOGIC; + SIGNAL wire_n11i1lii_dataout : STD_LOGIC; + SIGNAL wire_n11i1lil_dataout : STD_LOGIC; + SIGNAL wire_n11i1liO_dataout : STD_LOGIC; + SIGNAL wire_n11i1ll_dataout : STD_LOGIC; + SIGNAL wire_n11i1lli_dataout : STD_LOGIC; + SIGNAL wire_n11i1lll_dataout : STD_LOGIC; + SIGNAL wire_n11i1llO_dataout : STD_LOGIC; + SIGNAL wire_n11i1lO_dataout : STD_LOGIC; + SIGNAL wire_n11i1lOi_dataout : STD_LOGIC; + SIGNAL wire_n11i1lOl_dataout : STD_LOGIC; + SIGNAL wire_n11i1lOO_dataout : STD_LOGIC; + SIGNAL wire_n11i1O0i_dataout : STD_LOGIC; + SIGNAL wire_n11i1O0l_dataout : STD_LOGIC; + SIGNAL wire_n11i1O0O_dataout : STD_LOGIC; + SIGNAL wire_n11i1O1i_dataout : STD_LOGIC; + SIGNAL wire_n11i1O1l_dataout : STD_LOGIC; + SIGNAL wire_n11i1O1O_dataout : STD_LOGIC; + SIGNAL wire_n11i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11i1Oii_dataout : STD_LOGIC; + SIGNAL wire_n11i1Oil_dataout : STD_LOGIC; + SIGNAL wire_n11i1OiO_dataout : STD_LOGIC; + SIGNAL wire_n11i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11i1Oli_dataout : STD_LOGIC; + SIGNAL wire_n11i1Oll_dataout : STD_LOGIC; + SIGNAL wire_n11i1OlO_dataout : STD_LOGIC; + SIGNAL wire_n11i1OO_dataout : STD_LOGIC; + SIGNAL wire_n11i1OOi_dataout : STD_LOGIC; + SIGNAL wire_n11i1OOl_dataout : STD_LOGIC; + SIGNAL wire_n11i1OOO_dataout : STD_LOGIC; + SIGNAL wire_n11ii00i_dataout : STD_LOGIC; + SIGNAL wire_n11ii00l_dataout : STD_LOGIC; + SIGNAL wire_n11ii00O_dataout : STD_LOGIC; + SIGNAL wire_n11ii01i_dataout : STD_LOGIC; + SIGNAL wire_n11ii01l_dataout : STD_LOGIC; + SIGNAL wire_n11ii01O_dataout : STD_LOGIC; + SIGNAL wire_n11ii0i_dataout : STD_LOGIC; + SIGNAL wire_n11ii0ii_dataout : STD_LOGIC; + SIGNAL wire_n11ii0il_dataout : STD_LOGIC; + SIGNAL wire_n11ii0iO_dataout : STD_LOGIC; + SIGNAL wire_n11ii0l_dataout : STD_LOGIC; + SIGNAL wire_n11ii0li_dataout : STD_LOGIC; + SIGNAL wire_n11ii0ll_dataout : STD_LOGIC; + SIGNAL wire_n11ii0lO_dataout : STD_LOGIC; + SIGNAL wire_n11ii0O_dataout : STD_LOGIC; + SIGNAL wire_n11ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11ii0OO_dataout : STD_LOGIC; + SIGNAL wire_n11ii10i_dataout : STD_LOGIC; + SIGNAL wire_n11ii10l_dataout : STD_LOGIC; + SIGNAL wire_n11ii10O_dataout : STD_LOGIC; + SIGNAL wire_n11ii11i_dataout : STD_LOGIC; + SIGNAL wire_n11ii11l_dataout : STD_LOGIC; + SIGNAL wire_n11ii11O_dataout : STD_LOGIC; + SIGNAL wire_n11ii1i_dataout : STD_LOGIC; + SIGNAL wire_n11ii1ii_dataout : STD_LOGIC; + SIGNAL wire_n11ii1il_dataout : STD_LOGIC; + SIGNAL wire_n11ii1iO_dataout : STD_LOGIC; + SIGNAL wire_n11ii1l_dataout : STD_LOGIC; + SIGNAL wire_n11ii1li_dataout : STD_LOGIC; + SIGNAL wire_n11ii1ll_dataout : STD_LOGIC; + SIGNAL wire_n11ii1lO_dataout : STD_LOGIC; + SIGNAL wire_n11ii1O_dataout : STD_LOGIC; + SIGNAL wire_n11ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11ii1OO_dataout : STD_LOGIC; + SIGNAL wire_n11iii0i_dataout : STD_LOGIC; + SIGNAL wire_n11iii0l_dataout : STD_LOGIC; + SIGNAL wire_n11iii0O_dataout : STD_LOGIC; + SIGNAL wire_n11iii1i_dataout : STD_LOGIC; + SIGNAL wire_n11iii1l_dataout : STD_LOGIC; + SIGNAL wire_n11iii1O_dataout : STD_LOGIC; + SIGNAL wire_n11iiii_dataout : STD_LOGIC; + SIGNAL wire_n11iiiii_dataout : STD_LOGIC; + SIGNAL wire_n11iiiil_dataout : STD_LOGIC; + SIGNAL wire_n11iiiiO_dataout : STD_LOGIC; + SIGNAL wire_n11iiil_dataout : STD_LOGIC; + SIGNAL wire_n11iiili_dataout : STD_LOGIC; + SIGNAL wire_n11iiill_dataout : STD_LOGIC; + SIGNAL wire_n11iiilO_dataout : STD_LOGIC; + SIGNAL wire_n11iiiO_dataout : STD_LOGIC; + SIGNAL wire_n11iiiOi_dataout : STD_LOGIC; + SIGNAL wire_n11iiiOl_dataout : STD_LOGIC; + SIGNAL wire_n11iiiOO_dataout : STD_LOGIC; + SIGNAL wire_n11iil0i_dataout : STD_LOGIC; + SIGNAL wire_n11iil0l_dataout : STD_LOGIC; + SIGNAL wire_n11iil0O_dataout : STD_LOGIC; + SIGNAL wire_n11iil1i_dataout : STD_LOGIC; + SIGNAL wire_n11iil1l_dataout : STD_LOGIC; + SIGNAL wire_n11iil1O_dataout : STD_LOGIC; + SIGNAL wire_n11iili_dataout : STD_LOGIC; + SIGNAL wire_n11iilii_dataout : STD_LOGIC; + SIGNAL wire_n11iilil_dataout : STD_LOGIC; + SIGNAL wire_n11iiliO_dataout : STD_LOGIC; + SIGNAL wire_n11iill_dataout : STD_LOGIC; + SIGNAL wire_n11iilli_dataout : STD_LOGIC; + SIGNAL wire_n11iilll_dataout : STD_LOGIC; + SIGNAL wire_n11iillO_dataout : STD_LOGIC; + SIGNAL wire_n11iilO_dataout : STD_LOGIC; + SIGNAL wire_n11iilOi_dataout : STD_LOGIC; + SIGNAL wire_n11iilOl_dataout : STD_LOGIC; + SIGNAL wire_n11iilOO_dataout : STD_LOGIC; + SIGNAL wire_n11iiO0i_dataout : STD_LOGIC; + SIGNAL wire_n11iiO0l_dataout : STD_LOGIC; + SIGNAL wire_n11iiO0O_dataout : STD_LOGIC; + SIGNAL wire_n11iiO1i_dataout : STD_LOGIC; + SIGNAL wire_n11iiO1l_dataout : STD_LOGIC; + SIGNAL wire_n11iiO1O_dataout : STD_LOGIC; + SIGNAL wire_n11iiOi_dataout : STD_LOGIC; + SIGNAL wire_n11iiOii_dataout : STD_LOGIC; + SIGNAL wire_n11iiOil_dataout : STD_LOGIC; + SIGNAL wire_n11iiOiO_dataout : STD_LOGIC; + SIGNAL wire_n11iiOl_dataout : STD_LOGIC; + SIGNAL wire_n11iiOli_dataout : STD_LOGIC; + SIGNAL wire_n11iiOll_dataout : STD_LOGIC; + SIGNAL wire_n11iiOlO_dataout : STD_LOGIC; + SIGNAL wire_n11iiOO_dataout : STD_LOGIC; + SIGNAL wire_n11iiOOi_dataout : STD_LOGIC; + SIGNAL wire_n11iiOOl_dataout : STD_LOGIC; + SIGNAL wire_n11iiOOO_dataout : STD_LOGIC; + SIGNAL wire_n11il00i_dataout : STD_LOGIC; + SIGNAL wire_n11il00l_dataout : STD_LOGIC; + SIGNAL wire_n11il01i_dataout : STD_LOGIC; + SIGNAL wire_n11il01l_dataout : STD_LOGIC; + SIGNAL wire_n11il01O_dataout : STD_LOGIC; + SIGNAL wire_n11il0i_dataout : STD_LOGIC; + SIGNAL wire_n11il0l_dataout : STD_LOGIC; + SIGNAL wire_n11il0li_dataout : STD_LOGIC; + SIGNAL wire_n11il0ll_dataout : STD_LOGIC; + SIGNAL wire_n11il0lO_dataout : STD_LOGIC; + SIGNAL wire_n11il0O_dataout : STD_LOGIC; + SIGNAL wire_n11il10i_dataout : STD_LOGIC; + SIGNAL wire_n11il10l_dataout : STD_LOGIC; + SIGNAL wire_n11il10O_dataout : STD_LOGIC; + SIGNAL wire_n11il11i_dataout : STD_LOGIC; + SIGNAL wire_n11il11l_dataout : STD_LOGIC; + SIGNAL wire_n11il11O_dataout : STD_LOGIC; + SIGNAL wire_n11il1i_dataout : STD_LOGIC; + SIGNAL wire_n11il1ii_dataout : STD_LOGIC; + SIGNAL wire_n11il1il_dataout : STD_LOGIC; + SIGNAL wire_n11il1iO_dataout : STD_LOGIC; + SIGNAL wire_n11il1l_dataout : STD_LOGIC; + SIGNAL wire_n11il1li_dataout : STD_LOGIC; + SIGNAL wire_n11il1ll_dataout : STD_LOGIC; + SIGNAL wire_n11il1lO_dataout : STD_LOGIC; + SIGNAL wire_n11il1O_dataout : STD_LOGIC; + SIGNAL wire_n11il1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11il1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11il1OO_dataout : STD_LOGIC; + SIGNAL wire_n11ili0i_dataout : STD_LOGIC; + SIGNAL wire_n11ili0l_dataout : STD_LOGIC; + SIGNAL wire_n11ili0O_dataout : STD_LOGIC; + SIGNAL wire_n11ili1i_dataout : STD_LOGIC; + SIGNAL wire_n11ili1l_dataout : STD_LOGIC; + SIGNAL wire_n11ili1O_dataout : STD_LOGIC; + SIGNAL wire_n11ilii_dataout : STD_LOGIC; + SIGNAL wire_n11iliii_dataout : STD_LOGIC; + SIGNAL wire_n11iliil_dataout : STD_LOGIC; + SIGNAL wire_n11ilil_dataout : STD_LOGIC; + SIGNAL wire_n11ililO_dataout : STD_LOGIC; + SIGNAL wire_n11iliO_dataout : STD_LOGIC; + SIGNAL wire_n11iliOi_dataout : STD_LOGIC; + SIGNAL wire_n11iliOl_dataout : STD_LOGIC; + SIGNAL wire_n11iliOO_dataout : STD_LOGIC; + SIGNAL wire_n11ill0i_dataout : STD_LOGIC; + SIGNAL wire_n11ill0l_dataout : STD_LOGIC; + SIGNAL wire_n11ill0O_dataout : STD_LOGIC; + SIGNAL wire_n11ill1i_dataout : STD_LOGIC; + SIGNAL wire_n11ill1l_dataout : STD_LOGIC; + SIGNAL wire_n11ill1O_dataout : STD_LOGIC; + SIGNAL wire_n11illi_dataout : STD_LOGIC; + SIGNAL wire_n11illii_dataout : STD_LOGIC; + SIGNAL wire_n11illil_dataout : STD_LOGIC; + SIGNAL wire_n11illiO_dataout : STD_LOGIC; + SIGNAL wire_n11illl_dataout : STD_LOGIC; + SIGNAL wire_n11illli_dataout : STD_LOGIC; + SIGNAL wire_n11illll_dataout : STD_LOGIC; + SIGNAL wire_n11illlO_dataout : STD_LOGIC; + SIGNAL wire_n11illO_dataout : STD_LOGIC; + SIGNAL wire_n11illOi_dataout : STD_LOGIC; + SIGNAL wire_n11illOl_dataout : STD_LOGIC; + SIGNAL wire_n11illOO_dataout : STD_LOGIC; + SIGNAL wire_n11ilO0l_dataout : STD_LOGIC; + SIGNAL wire_n11ilO0O_dataout : STD_LOGIC; + SIGNAL wire_n11ilOi_dataout : STD_LOGIC; + SIGNAL wire_n11ilOii_dataout : STD_LOGIC; + SIGNAL wire_n11ilOil_dataout : STD_LOGIC; + SIGNAL wire_n11ilOiO_dataout : STD_LOGIC; + SIGNAL wire_n11ilOl_dataout : STD_LOGIC; + SIGNAL wire_n11ilOli_dataout : STD_LOGIC; + SIGNAL wire_n11ilOll_dataout : STD_LOGIC; + SIGNAL wire_n11ilOlO_dataout : STD_LOGIC; + SIGNAL wire_n11ilOO_dataout : STD_LOGIC; + SIGNAL wire_n11ilOOO_dataout : STD_LOGIC; + SIGNAL wire_n11iO00l_dataout : STD_LOGIC; + SIGNAL wire_n11iO00O_dataout : STD_LOGIC; + SIGNAL wire_n11iO0i_dataout : STD_LOGIC; + SIGNAL wire_n11iO0ii_dataout : STD_LOGIC; + SIGNAL wire_n11iO0il_dataout : STD_LOGIC; + SIGNAL wire_n11iO0iO_dataout : STD_LOGIC; + SIGNAL wire_n11iO0li_dataout : STD_LOGIC; + SIGNAL wire_n11iO0ll_dataout : STD_LOGIC; + SIGNAL wire_n11iO0lO_dataout : STD_LOGIC; + SIGNAL wire_n11iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11iO0OO_dataout : STD_LOGIC; + SIGNAL wire_n11iO10i_dataout : STD_LOGIC; + SIGNAL wire_n11iO10l_dataout : STD_LOGIC; + SIGNAL wire_n11iO10O_dataout : STD_LOGIC; + SIGNAL wire_n11iO11i_dataout : STD_LOGIC; + SIGNAL wire_n11iO11l_dataout : STD_LOGIC; + SIGNAL wire_n11iO11O_dataout : STD_LOGIC; + SIGNAL wire_n11iO1i_dataout : STD_LOGIC; + SIGNAL wire_n11iO1ii_dataout : STD_LOGIC; + SIGNAL wire_n11iO1il_dataout : STD_LOGIC; + SIGNAL wire_n11iO1iO_dataout : STD_LOGIC; + SIGNAL wire_n11iO1l_dataout : STD_LOGIC; + SIGNAL wire_n11iO1li_dataout : STD_LOGIC; + SIGNAL wire_n11iO1ll_dataout : STD_LOGIC; + SIGNAL wire_n11iO1lO_dataout : STD_LOGIC; + SIGNAL wire_n11iO1O_dataout : STD_LOGIC; + SIGNAL wire_n11iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11iO1OO_dataout : STD_LOGIC; + SIGNAL wire_n11iOi0i_dataout : STD_LOGIC; + SIGNAL wire_n11iOi0l_dataout : STD_LOGIC; + SIGNAL wire_n11iOi0O_dataout : STD_LOGIC; + SIGNAL wire_n11iOi1i_dataout : STD_LOGIC; + SIGNAL wire_n11iOi1l_dataout : STD_LOGIC; + SIGNAL wire_n11iOi1O_dataout : STD_LOGIC; + SIGNAL wire_n11iOii_dataout : STD_LOGIC; + SIGNAL wire_n11iOiii_dataout : STD_LOGIC; + SIGNAL wire_n11iOiil_dataout : STD_LOGIC; + SIGNAL wire_n11iOiiO_dataout : STD_LOGIC; + SIGNAL wire_n11iOil_dataout : STD_LOGIC; + SIGNAL wire_n11iOiO_dataout : STD_LOGIC; + SIGNAL wire_n11iOl0i_dataout : STD_LOGIC; + SIGNAL wire_n11iOl0l_dataout : STD_LOGIC; + SIGNAL wire_n11iOl0O_dataout : STD_LOGIC; + SIGNAL wire_n11iOl1i_dataout : STD_LOGIC; + SIGNAL wire_n11iOl1l_dataout : STD_LOGIC; + SIGNAL wire_n11iOl1O_dataout : STD_LOGIC; + SIGNAL wire_n11iOli_dataout : STD_LOGIC; + SIGNAL wire_n11iOlii_dataout : STD_LOGIC; + SIGNAL wire_n11iOlil_dataout : STD_LOGIC; + SIGNAL wire_n11iOliO_dataout : STD_LOGIC; + SIGNAL wire_n11iOll_dataout : STD_LOGIC; + SIGNAL wire_n11iOlO_dataout : STD_LOGIC; + SIGNAL wire_n11iOO0i_dataout : STD_LOGIC; + SIGNAL wire_n11iOO0l_dataout : STD_LOGIC; + SIGNAL wire_n11iOO0O_dataout : STD_LOGIC; + SIGNAL wire_n11iOO1l_dataout : STD_LOGIC; + SIGNAL wire_n11iOO1O_dataout : STD_LOGIC; + SIGNAL wire_n11iOOi_dataout : STD_LOGIC; + SIGNAL wire_n11iOOii_dataout : STD_LOGIC; + SIGNAL wire_n11iOOil_dataout : STD_LOGIC; + SIGNAL wire_n11iOOiO_dataout : STD_LOGIC; + SIGNAL wire_n11iOOl_dataout : STD_LOGIC; + SIGNAL wire_n11iOOli_dataout : STD_LOGIC; + SIGNAL wire_n11iOOll_dataout : STD_LOGIC; + SIGNAL wire_n11iOOlO_dataout : STD_LOGIC; + SIGNAL wire_n11iOOO_dataout : STD_LOGIC; + SIGNAL wire_n11iOOOi_dataout : STD_LOGIC; + SIGNAL wire_n11l000i_dataout : STD_LOGIC; + SIGNAL wire_n11l000l_dataout : STD_LOGIC; + SIGNAL wire_n11l000O_dataout : STD_LOGIC; + SIGNAL wire_n11l001i_dataout : STD_LOGIC; + SIGNAL wire_n11l001l_dataout : STD_LOGIC; + SIGNAL wire_n11l001O_dataout : STD_LOGIC; + SIGNAL wire_n11l00i_dataout : STD_LOGIC; + SIGNAL wire_n11l00ii_dataout : STD_LOGIC; + SIGNAL wire_n11l00il_dataout : STD_LOGIC; + SIGNAL wire_n11l00l_dataout : STD_LOGIC; + SIGNAL wire_n11l00O_dataout : STD_LOGIC; + SIGNAL wire_n11l00Oi_dataout : STD_LOGIC; + SIGNAL wire_n11l00OO_dataout : STD_LOGIC; + SIGNAL wire_n11l010i_dataout : STD_LOGIC; + SIGNAL wire_n11l010l_dataout : STD_LOGIC; + SIGNAL wire_n11l010O_dataout : STD_LOGIC; + SIGNAL wire_n11l011i_dataout : STD_LOGIC; + SIGNAL wire_n11l011l_dataout : STD_LOGIC; + SIGNAL wire_n11l011O_dataout : STD_LOGIC; + SIGNAL wire_n11l01i_dataout : STD_LOGIC; + SIGNAL wire_n11l01ii_dataout : STD_LOGIC; + SIGNAL wire_n11l01il_dataout : STD_LOGIC; + SIGNAL wire_n11l01iO_dataout : STD_LOGIC; + SIGNAL wire_n11l01l_dataout : STD_LOGIC; + SIGNAL wire_n11l01li_dataout : STD_LOGIC; + SIGNAL wire_n11l01ll_dataout : STD_LOGIC; + SIGNAL wire_n11l01lO_dataout : STD_LOGIC; + SIGNAL wire_n11l01O_dataout : STD_LOGIC; + SIGNAL wire_n11l01Oi_dataout : STD_LOGIC; + SIGNAL wire_n11l01Ol_dataout : STD_LOGIC; + SIGNAL wire_n11l01OO_dataout : STD_LOGIC; + SIGNAL wire_n11l0i0O_dataout : STD_LOGIC; + SIGNAL wire_n11l0i1i_dataout : STD_LOGIC; + SIGNAL wire_n11l0i1l_dataout : STD_LOGIC; + SIGNAL wire_n11l0i1O_dataout : STD_LOGIC; + SIGNAL wire_n11l0ii_dataout : STD_LOGIC; + SIGNAL wire_n11l0iii_dataout : STD_LOGIC; + SIGNAL wire_n11l0iil_dataout : STD_LOGIC; + SIGNAL wire_n11l0iiO_dataout : STD_LOGIC; + SIGNAL wire_n11l0il_dataout : STD_LOGIC; + SIGNAL wire_n11l0ili_dataout : STD_LOGIC; + SIGNAL wire_n11l0ill_dataout : STD_LOGIC; + SIGNAL wire_n11l0ilO_dataout : STD_LOGIC; + SIGNAL wire_n11l0iO_dataout : STD_LOGIC; + SIGNAL wire_n11l0iOi_dataout : STD_LOGIC; + SIGNAL wire_n11l0iOO_dataout : STD_LOGIC; + SIGNAL wire_n11l0l0i_dataout : STD_LOGIC; + SIGNAL wire_n11l0l0l_dataout : STD_LOGIC; + SIGNAL wire_n11l0l0O_dataout : STD_LOGIC; + SIGNAL wire_n11l0l1i_dataout : STD_LOGIC; + SIGNAL wire_n11l0l1l_dataout : STD_LOGIC; + SIGNAL wire_n11l0l1O_dataout : STD_LOGIC; + SIGNAL wire_n11l0li_dataout : STD_LOGIC; + SIGNAL wire_n11l0lii_dataout : STD_LOGIC; + SIGNAL wire_n11l0lil_dataout : STD_LOGIC; + SIGNAL wire_n11l0liO_dataout : STD_LOGIC; + SIGNAL wire_n11l0ll_dataout : STD_LOGIC; + SIGNAL wire_n11l0lli_dataout : STD_LOGIC; + SIGNAL wire_n11l0lll_dataout : STD_LOGIC; + SIGNAL wire_n11l0lO_dataout : STD_LOGIC; + SIGNAL wire_n11l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11l0OO_dataout : STD_LOGIC; + SIGNAL wire_n11l100i_dataout : STD_LOGIC; + SIGNAL wire_n11l100l_dataout : STD_LOGIC; + SIGNAL wire_n11l100O_dataout : STD_LOGIC; + SIGNAL wire_n11l101i_dataout : STD_LOGIC; + SIGNAL wire_n11l101l_dataout : STD_LOGIC; + SIGNAL wire_n11l101O_dataout : STD_LOGIC; + SIGNAL wire_n11l10i_dataout : STD_LOGIC; + SIGNAL wire_n11l10ii_dataout : STD_LOGIC; + SIGNAL wire_n11l10il_dataout : STD_LOGIC; + SIGNAL wire_n11l10iO_dataout : STD_LOGIC; + SIGNAL wire_n11l10l_dataout : STD_LOGIC; + SIGNAL wire_n11l10li_dataout : STD_LOGIC; + SIGNAL wire_n11l10ll_dataout : STD_LOGIC; + SIGNAL wire_n11l10lO_dataout : STD_LOGIC; + SIGNAL wire_n11l10O_dataout : STD_LOGIC; + SIGNAL wire_n11l10Oi_dataout : STD_LOGIC; + SIGNAL wire_n11l10Ol_dataout : STD_LOGIC; + SIGNAL wire_n11l10OO_dataout : STD_LOGIC; + SIGNAL wire_n11l110O_dataout : STD_LOGIC; + SIGNAL wire_n11l11i_dataout : STD_LOGIC; + SIGNAL wire_n11l11ii_dataout : STD_LOGIC; + SIGNAL wire_n11l11il_dataout : STD_LOGIC; + SIGNAL wire_n11l11iO_dataout : STD_LOGIC; + SIGNAL wire_n11l11l_dataout : STD_LOGIC; + SIGNAL wire_n11l11li_dataout : STD_LOGIC; + SIGNAL wire_n11l11ll_dataout : STD_LOGIC; + SIGNAL wire_n11l11lO_dataout : STD_LOGIC; + SIGNAL wire_n11l11O_dataout : STD_LOGIC; + SIGNAL wire_n11l11Oi_dataout : STD_LOGIC; + SIGNAL wire_n11l11Ol_dataout : STD_LOGIC; + SIGNAL wire_n11l11OO_dataout : STD_LOGIC; + SIGNAL wire_n11l1i1i_dataout : STD_LOGIC; + SIGNAL wire_n11l1i1l_dataout : STD_LOGIC; + SIGNAL wire_n11l1i1O_dataout : STD_LOGIC; + SIGNAL wire_n11l1ii_dataout : STD_LOGIC; + SIGNAL wire_n11l1iil_dataout : STD_LOGIC; + SIGNAL wire_n11l1iiO_dataout : STD_LOGIC; + SIGNAL wire_n11l1il_dataout : STD_LOGIC; + SIGNAL wire_n11l1ili_dataout : STD_LOGIC; + SIGNAL wire_n11l1ill_dataout : STD_LOGIC; + SIGNAL wire_n11l1iO_dataout : STD_LOGIC; + SIGNAL wire_n11l1iOl_dataout : STD_LOGIC; + SIGNAL wire_n11l1iOO_dataout : STD_LOGIC; + SIGNAL wire_n11l1l1i_dataout : STD_LOGIC; + SIGNAL wire_n11l1l1l_dataout : STD_LOGIC; + SIGNAL wire_n11l1li_dataout : STD_LOGIC; + SIGNAL wire_n11l1ll_dataout : STD_LOGIC; + SIGNAL wire_n11l1lll_dataout : STD_LOGIC; + SIGNAL wire_n11l1llO_dataout : STD_LOGIC; + SIGNAL wire_n11l1lO_dataout : STD_LOGIC; + SIGNAL wire_n11l1lOi_dataout : STD_LOGIC; + SIGNAL wire_n11l1lOl_dataout : STD_LOGIC; + SIGNAL wire_n11l1lOO_dataout : STD_LOGIC; + SIGNAL wire_n11l1O0i_dataout : STD_LOGIC; + SIGNAL wire_n11l1O0l_dataout : STD_LOGIC; + SIGNAL wire_n11l1O0O_dataout : STD_LOGIC; + SIGNAL wire_n11l1O1i_dataout : STD_LOGIC; + SIGNAL wire_n11l1O1O_dataout : STD_LOGIC; + SIGNAL wire_n11l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11l1Oii_dataout : STD_LOGIC; + SIGNAL wire_n11l1Oil_dataout : STD_LOGIC; + SIGNAL wire_n11l1OiO_dataout : STD_LOGIC; + SIGNAL wire_n11l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11l1Oli_dataout : STD_LOGIC; + SIGNAL wire_n11l1Oll_dataout : STD_LOGIC; + SIGNAL wire_n11l1OlO_dataout : STD_LOGIC; + SIGNAL wire_n11l1OO_dataout : STD_LOGIC; + SIGNAL wire_n11l1OOi_dataout : STD_LOGIC; + SIGNAL wire_n11l1OOl_dataout : STD_LOGIC; + SIGNAL wire_n11l1OOO_dataout : STD_LOGIC; + SIGNAL wire_n11li00i_dataout : STD_LOGIC; + SIGNAL wire_n11li00l_dataout : STD_LOGIC; + SIGNAL wire_n11li00O_dataout : STD_LOGIC; + SIGNAL wire_n11li01i_dataout : STD_LOGIC; + SIGNAL wire_n11li01l_dataout : STD_LOGIC; + SIGNAL wire_n11li01O_dataout : STD_LOGIC; + SIGNAL wire_n11li0i_dataout : STD_LOGIC; + SIGNAL wire_n11li0ii_dataout : STD_LOGIC; + SIGNAL wire_n11li0il_dataout : STD_LOGIC; + SIGNAL wire_n11li0iO_dataout : STD_LOGIC; + SIGNAL wire_n11li0l_dataout : STD_LOGIC; + SIGNAL wire_n11li0li_dataout : STD_LOGIC; + SIGNAL wire_n11li0ll_dataout : STD_LOGIC; + SIGNAL wire_n11li0lO_dataout : STD_LOGIC; + SIGNAL wire_n11li0O_dataout : STD_LOGIC; + SIGNAL wire_n11li0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11li0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11li0OO_dataout : STD_LOGIC; + SIGNAL wire_n11li1i_dataout : STD_LOGIC; + SIGNAL wire_n11li1l_dataout : STD_LOGIC; + SIGNAL wire_n11li1ll_dataout : STD_LOGIC; + SIGNAL wire_n11li1lO_dataout : STD_LOGIC; + SIGNAL wire_n11li1O_dataout : STD_LOGIC; + SIGNAL wire_n11li1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11li1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11li1OO_dataout : STD_LOGIC; + SIGNAL wire_n11lii0i_dataout : STD_LOGIC; + SIGNAL wire_n11lii0l_dataout : STD_LOGIC; + SIGNAL wire_n11lii0O_dataout : STD_LOGIC; + SIGNAL wire_n11lii1i_dataout : STD_LOGIC; + SIGNAL wire_n11lii1l_dataout : STD_LOGIC; + SIGNAL wire_n11lii1O_dataout : STD_LOGIC; + SIGNAL wire_n11liii_dataout : STD_LOGIC; + SIGNAL wire_n11liiii_dataout : STD_LOGIC; + SIGNAL wire_n11liiil_dataout : STD_LOGIC; + SIGNAL wire_n11liiiO_dataout : STD_LOGIC; + SIGNAL wire_n11liil_dataout : STD_LOGIC; + SIGNAL wire_n11liili_dataout : STD_LOGIC; + SIGNAL wire_n11liill_dataout : STD_LOGIC; + SIGNAL wire_n11liilO_dataout : STD_LOGIC; + SIGNAL wire_n11liiO_dataout : STD_LOGIC; + SIGNAL wire_n11liiOi_dataout : STD_LOGIC; + SIGNAL wire_n11liiOl_dataout : STD_LOGIC; + SIGNAL wire_n11liiOO_dataout : STD_LOGIC; + SIGNAL wire_n11lil0i_dataout : STD_LOGIC; + SIGNAL wire_n11lil0l_dataout : STD_LOGIC; + SIGNAL wire_n11lil0O_dataout : STD_LOGIC; + SIGNAL wire_n11lil1i_dataout : STD_LOGIC; + SIGNAL wire_n11lil1l_dataout : STD_LOGIC; + SIGNAL wire_n11lil1O_dataout : STD_LOGIC; + SIGNAL wire_n11lili_dataout : STD_LOGIC; + SIGNAL wire_n11lilii_dataout : STD_LOGIC; + SIGNAL wire_n11lilil_dataout : STD_LOGIC; + SIGNAL wire_n11liliO_dataout : STD_LOGIC; + SIGNAL wire_n11lill_dataout : STD_LOGIC; + SIGNAL wire_n11lilli_dataout : STD_LOGIC; + SIGNAL wire_n11lilll_dataout : STD_LOGIC; + SIGNAL wire_n11lillO_dataout : STD_LOGIC; + SIGNAL wire_n11lilO_dataout : STD_LOGIC; + SIGNAL wire_n11lilOi_dataout : STD_LOGIC; + SIGNAL wire_n11lilOl_dataout : STD_LOGIC; + SIGNAL wire_n11lilOO_dataout : STD_LOGIC; + SIGNAL wire_n11liO1i_dataout : STD_LOGIC; + SIGNAL wire_n11liO1l_dataout : STD_LOGIC; + SIGNAL wire_n11liOi_dataout : STD_LOGIC; + SIGNAL wire_n11liOl_dataout : STD_LOGIC; + SIGNAL wire_n11liOO_dataout : STD_LOGIC; + SIGNAL wire_n11ll01i_dataout : STD_LOGIC; + SIGNAL wire_n11ll01l_dataout : STD_LOGIC; + SIGNAL wire_n11ll0i_dataout : STD_LOGIC; + SIGNAL wire_n11ll0l_dataout : STD_LOGIC; + SIGNAL wire_n11ll0lO_dataout : STD_LOGIC; + SIGNAL wire_n11ll0O_dataout : STD_LOGIC; + SIGNAL wire_n11ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11ll0OO_dataout : STD_LOGIC; + SIGNAL wire_n11ll10l_dataout : STD_LOGIC; + SIGNAL wire_n11ll10O_dataout : STD_LOGIC; + SIGNAL wire_n11ll1i_dataout : STD_LOGIC; + SIGNAL wire_n11ll1ii_dataout : STD_LOGIC; + SIGNAL wire_n11ll1il_dataout : STD_LOGIC; + SIGNAL wire_n11ll1iO_dataout : STD_LOGIC; + SIGNAL wire_n11ll1l_dataout : STD_LOGIC; + SIGNAL wire_n11ll1li_dataout : STD_LOGIC; + SIGNAL wire_n11ll1ll_dataout : STD_LOGIC; + SIGNAL wire_n11ll1lO_dataout : STD_LOGIC; + SIGNAL wire_n11ll1O_dataout : STD_LOGIC; + SIGNAL wire_n11ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11ll1OO_dataout : STD_LOGIC; + SIGNAL wire_n11lli0i_dataout : STD_LOGIC; + SIGNAL wire_n11lli0l_dataout : STD_LOGIC; + SIGNAL wire_n11lli0O_dataout : STD_LOGIC; + SIGNAL wire_n11lli1i_dataout : STD_LOGIC; + SIGNAL wire_n11lli1l_dataout : STD_LOGIC; + SIGNAL wire_n11lli1O_dataout : STD_LOGIC; + SIGNAL wire_n11llii_dataout : STD_LOGIC; + SIGNAL wire_n11lliii_dataout : STD_LOGIC; + SIGNAL wire_n11lliil_dataout : STD_LOGIC; + SIGNAL wire_n11lliiO_dataout : STD_LOGIC; + SIGNAL wire_n11llil_dataout : STD_LOGIC; + SIGNAL wire_n11llili_dataout : STD_LOGIC; + SIGNAL wire_n11llill_dataout : STD_LOGIC; + SIGNAL wire_n11llilO_dataout : STD_LOGIC; + SIGNAL wire_n11lliO_dataout : STD_LOGIC; + SIGNAL wire_n11lliOi_dataout : STD_LOGIC; + SIGNAL wire_n11lliOl_dataout : STD_LOGIC; + SIGNAL wire_n11lliOO_dataout : STD_LOGIC; + SIGNAL wire_n11lll0i_dataout : STD_LOGIC; + SIGNAL wire_n11lll0l_dataout : STD_LOGIC; + SIGNAL wire_n11lll0O_dataout : STD_LOGIC; + SIGNAL wire_n11lll1i_dataout : STD_LOGIC; + SIGNAL wire_n11lll1l_dataout : STD_LOGIC; + SIGNAL wire_n11lll1O_dataout : STD_LOGIC; + SIGNAL wire_n11llli_dataout : STD_LOGIC; + SIGNAL wire_n11lllii_dataout : STD_LOGIC; + SIGNAL wire_n11lllil_dataout : STD_LOGIC; + SIGNAL wire_n11llliO_dataout : STD_LOGIC; + SIGNAL wire_n11llll_dataout : STD_LOGIC; + SIGNAL wire_n11lllli_dataout : STD_LOGIC; + SIGNAL wire_n11lllll_dataout : STD_LOGIC; + SIGNAL wire_n11llllO_dataout : STD_LOGIC; + SIGNAL wire_n11lllO_dataout : STD_LOGIC; + SIGNAL wire_n11lllOi_dataout : STD_LOGIC; + SIGNAL wire_n11lllOl_dataout : STD_LOGIC; + SIGNAL wire_n11lllOO_dataout : STD_LOGIC; + SIGNAL wire_n11llO0i_dataout : STD_LOGIC; + SIGNAL wire_n11llO1O_dataout : STD_LOGIC; + SIGNAL wire_n11llOi_dataout : STD_LOGIC; + SIGNAL wire_n11llOii_dataout : STD_LOGIC; + SIGNAL wire_n11llOil_dataout : STD_LOGIC; + SIGNAL wire_n11llOiO_dataout : STD_LOGIC; + SIGNAL wire_n11llOl_dataout : STD_LOGIC; + SIGNAL wire_n11llOli_dataout : STD_LOGIC; + SIGNAL wire_n11llOll_dataout : STD_LOGIC; + SIGNAL wire_n11llOlO_dataout : STD_LOGIC; + SIGNAL wire_n11llOO_dataout : STD_LOGIC; + SIGNAL wire_n11llOOi_dataout : STD_LOGIC; + SIGNAL wire_n11llOOl_dataout : STD_LOGIC; + SIGNAL wire_n11llOOO_dataout : STD_LOGIC; + SIGNAL wire_n11lO00i_dataout : STD_LOGIC; + SIGNAL wire_n11lO00l_dataout : STD_LOGIC; + SIGNAL wire_n11lO00O_dataout : STD_LOGIC; + SIGNAL wire_n11lO01i_dataout : STD_LOGIC; + SIGNAL wire_n11lO0i_dataout : STD_LOGIC; + SIGNAL wire_n11lO0ii_dataout : STD_LOGIC; + SIGNAL wire_n11lO0il_dataout : STD_LOGIC; + SIGNAL wire_n11lO0iO_dataout : STD_LOGIC; + SIGNAL wire_n11lO0l_dataout : STD_LOGIC; + SIGNAL wire_n11lO0li_dataout : STD_LOGIC; + SIGNAL wire_n11lO0ll_dataout : STD_LOGIC; + SIGNAL wire_n11lO0lO_dataout : STD_LOGIC; + SIGNAL wire_n11lO0O_dataout : STD_LOGIC; + SIGNAL wire_n11lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11lO0OO_dataout : STD_LOGIC; + SIGNAL wire_n11lO10i_dataout : STD_LOGIC; + SIGNAL wire_n11lO10l_dataout : STD_LOGIC; + SIGNAL wire_n11lO10O_dataout : STD_LOGIC; + SIGNAL wire_n11lO11i_dataout : STD_LOGIC; + SIGNAL wire_n11lO11l_dataout : STD_LOGIC; + SIGNAL wire_n11lO11O_dataout : STD_LOGIC; + SIGNAL wire_n11lO1i_dataout : STD_LOGIC; + SIGNAL wire_n11lO1ii_dataout : STD_LOGIC; + SIGNAL wire_n11lO1il_dataout : STD_LOGIC; + SIGNAL wire_n11lO1iO_dataout : STD_LOGIC; + SIGNAL wire_n11lO1l_dataout : STD_LOGIC; + SIGNAL wire_n11lO1li_dataout : STD_LOGIC; + SIGNAL wire_n11lO1ll_dataout : STD_LOGIC; + SIGNAL wire_n11lO1lO_dataout : STD_LOGIC; + SIGNAL wire_n11lO1O_dataout : STD_LOGIC; + SIGNAL wire_n11lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11lO1OO_dataout : STD_LOGIC; + SIGNAL wire_n11lOi0i_dataout : STD_LOGIC; + SIGNAL wire_n11lOi0l_dataout : STD_LOGIC; + SIGNAL wire_n11lOi1i_dataout : STD_LOGIC; + SIGNAL wire_n11lOi1l_dataout : STD_LOGIC; + SIGNAL wire_n11lOi1O_dataout : STD_LOGIC; + SIGNAL wire_n11lOii_dataout : STD_LOGIC; + SIGNAL wire_n11lOil_dataout : STD_LOGIC; + SIGNAL wire_n11lOiO_dataout : STD_LOGIC; + SIGNAL wire_n11lOl0O_dataout : STD_LOGIC; + SIGNAL wire_n11lOli_dataout : STD_LOGIC; + SIGNAL wire_n11lOll_dataout : STD_LOGIC; + SIGNAL wire_n11lOlO_dataout : STD_LOGIC; + SIGNAL wire_n11lOOi_dataout : STD_LOGIC; + SIGNAL wire_n11lOOii_dataout : STD_LOGIC; + SIGNAL wire_n11lOOl_dataout : STD_LOGIC; + SIGNAL wire_n11lOOO_dataout : STD_LOGIC; + SIGNAL wire_n11O00i_dataout : STD_LOGIC; + SIGNAL wire_n11O00l_dataout : STD_LOGIC; + SIGNAL wire_n11O00O_dataout : STD_LOGIC; + SIGNAL wire_n11O01i_dataout : STD_LOGIC; + SIGNAL wire_n11O01l_dataout : STD_LOGIC; + SIGNAL wire_n11O01O_dataout : STD_LOGIC; + SIGNAL wire_n11O0ii_dataout : STD_LOGIC; + SIGNAL wire_n11O0il_dataout : STD_LOGIC; + SIGNAL wire_n11O0iO_dataout : STD_LOGIC; + SIGNAL wire_n11O0li_dataout : STD_LOGIC; + SIGNAL wire_n11O0ll_dataout : STD_LOGIC; + SIGNAL wire_n11O0lO_dataout : STD_LOGIC; + SIGNAL wire_n11O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11O0OO_dataout : STD_LOGIC; + SIGNAL wire_n11O10i_dataout : STD_LOGIC; + SIGNAL wire_n11O10l_dataout : STD_LOGIC; + SIGNAL wire_n11O10O_dataout : STD_LOGIC; + SIGNAL wire_n11O11i_dataout : STD_LOGIC; + SIGNAL wire_n11O11il_dataout : STD_LOGIC; + SIGNAL wire_n11O11l_dataout : STD_LOGIC; + SIGNAL wire_n11O11O_dataout : STD_LOGIC; + SIGNAL wire_n11O1i0i_dataout : STD_LOGIC; + SIGNAL wire_n11O1i1l_dataout : STD_LOGIC; + SIGNAL wire_n11O1i1O_dataout : STD_LOGIC; + SIGNAL wire_n11O1ii_dataout : STD_LOGIC; + SIGNAL wire_n11O1il_dataout : STD_LOGIC; + SIGNAL wire_n11O1iO_dataout : STD_LOGIC; + SIGNAL wire_n11O1li_dataout : STD_LOGIC; + SIGNAL wire_n11O1liO_dataout : STD_LOGIC; + SIGNAL wire_n11O1ll_dataout : STD_LOGIC; + SIGNAL wire_n11O1lli_dataout : STD_LOGIC; + SIGNAL wire_n11O1lO_dataout : STD_LOGIC; + SIGNAL wire_n11O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11O1OO_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0il_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0li_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_n11Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n11Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n11Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n11Oii0i_dataout : STD_LOGIC; + SIGNAL wire_n11Oii0l_dataout : STD_LOGIC; + SIGNAL wire_n11Oii0O_dataout : STD_LOGIC; + SIGNAL wire_n11Oii1i_dataout : STD_LOGIC; + SIGNAL wire_n11Oii1l_dataout : STD_LOGIC; + SIGNAL wire_n11Oii1O_dataout : STD_LOGIC; + SIGNAL wire_n11Oiii_dataout : STD_LOGIC; + SIGNAL wire_n11Oiiii_dataout : STD_LOGIC; + SIGNAL wire_n11Oiiil_dataout : STD_LOGIC; + SIGNAL wire_n11OiiiO_dataout : STD_LOGIC; + SIGNAL wire_n11Oiil_dataout : STD_LOGIC; + SIGNAL wire_n11Oiili_dataout : STD_LOGIC; + SIGNAL wire_n11Oiill_dataout : STD_LOGIC; + SIGNAL wire_n11OiilO_dataout : STD_LOGIC; + SIGNAL wire_n11OiiO_dataout : STD_LOGIC; + SIGNAL wire_n11OiiOi_dataout : STD_LOGIC; + SIGNAL wire_n11OiiOl_dataout : STD_LOGIC; + SIGNAL wire_n11OiiOO_dataout : STD_LOGIC; + SIGNAL wire_n11Oil0i_dataout : STD_LOGIC; + SIGNAL wire_n11Oil0l_dataout : STD_LOGIC; + SIGNAL wire_n11Oil0O_dataout : STD_LOGIC; + SIGNAL wire_n11Oil1i_dataout : STD_LOGIC; + SIGNAL wire_n11Oil1l_dataout : STD_LOGIC; + SIGNAL wire_n11Oil1O_dataout : STD_LOGIC; + SIGNAL wire_n11Oili_dataout : STD_LOGIC; + SIGNAL wire_n11Oilii_dataout : STD_LOGIC; + SIGNAL wire_n11Oilil_dataout : STD_LOGIC; + SIGNAL wire_n11OiliO_dataout : STD_LOGIC; + SIGNAL wire_n11Oill_dataout : STD_LOGIC; + SIGNAL wire_n11Oilli_dataout : STD_LOGIC; + SIGNAL wire_n11Oilll_dataout : STD_LOGIC; + SIGNAL wire_n11OillO_dataout : STD_LOGIC; + SIGNAL wire_n11OilO_dataout : STD_LOGIC; + SIGNAL wire_n11OilOi_dataout : STD_LOGIC; + SIGNAL wire_n11OilOl_dataout : STD_LOGIC; + SIGNAL wire_n11OilOO_dataout : STD_LOGIC; + SIGNAL wire_n11OiO0i_dataout : STD_LOGIC; + SIGNAL wire_n11OiO0l_dataout : STD_LOGIC; + SIGNAL wire_n11OiO0O_dataout : STD_LOGIC; + SIGNAL wire_n11OiO1i_dataout : STD_LOGIC; + SIGNAL wire_n11OiO1l_dataout : STD_LOGIC; + SIGNAL wire_n11OiO1O_dataout : STD_LOGIC; + SIGNAL wire_n11OiOi_dataout : STD_LOGIC; + SIGNAL wire_n11OiOii_dataout : STD_LOGIC; + SIGNAL wire_n11OiOil_dataout : STD_LOGIC; + SIGNAL wire_n11OiOiO_dataout : STD_LOGIC; + SIGNAL wire_n11OiOl_dataout : STD_LOGIC; + SIGNAL wire_n11OiOli_dataout : STD_LOGIC; + SIGNAL wire_n11OiOll_dataout : STD_LOGIC; + SIGNAL wire_n11OiOlO_dataout : STD_LOGIC; + SIGNAL wire_n11OiOO_dataout : STD_LOGIC; + SIGNAL wire_n11OiOOi_dataout : STD_LOGIC; + SIGNAL wire_n11OiOOl_dataout : STD_LOGIC; + SIGNAL wire_n11OiOOO_dataout : STD_LOGIC; + SIGNAL wire_n11Ol00i_dataout : STD_LOGIC; + SIGNAL wire_n11Ol00l_dataout : STD_LOGIC; + SIGNAL wire_n11Ol00O_dataout : STD_LOGIC; + SIGNAL wire_n11Ol01i_dataout : STD_LOGIC; + SIGNAL wire_n11Ol01l_dataout : STD_LOGIC; + SIGNAL wire_n11Ol01O_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0il_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0li_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_n11Ol10i_dataout : STD_LOGIC; + SIGNAL wire_n11Ol10l_dataout : STD_LOGIC; + SIGNAL wire_n11Ol10O_dataout : STD_LOGIC; + SIGNAL wire_n11Ol11i_dataout : STD_LOGIC; + SIGNAL wire_n11Ol11l_dataout : STD_LOGIC; + SIGNAL wire_n11Ol11O_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1il_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1li_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_n11Oli0i_dataout : STD_LOGIC; + SIGNAL wire_n11Oli0l_dataout : STD_LOGIC; + SIGNAL wire_n11Oli0O_dataout : STD_LOGIC; + SIGNAL wire_n11Oli1i_dataout : STD_LOGIC; + SIGNAL wire_n11Oli1l_dataout : STD_LOGIC; + SIGNAL wire_n11Oli1O_dataout : STD_LOGIC; + SIGNAL wire_n11Olii_dataout : STD_LOGIC; + SIGNAL wire_n11Oliii_dataout : STD_LOGIC; + SIGNAL wire_n11Oliil_dataout : STD_LOGIC; + SIGNAL wire_n11OliiO_dataout : STD_LOGIC; + SIGNAL wire_n11Olil_dataout : STD_LOGIC; + SIGNAL wire_n11Olili_dataout : STD_LOGIC; + SIGNAL wire_n11Olill_dataout : STD_LOGIC; + SIGNAL wire_n11OlilO_dataout : STD_LOGIC; + SIGNAL wire_n11OliO_dataout : STD_LOGIC; + SIGNAL wire_n11OliOi_dataout : STD_LOGIC; + SIGNAL wire_n11OliOl_dataout : STD_LOGIC; + SIGNAL wire_n11OliOO_dataout : STD_LOGIC; + SIGNAL wire_n11Oll0i_dataout : STD_LOGIC; + SIGNAL wire_n11Oll0l_dataout : STD_LOGIC; + SIGNAL wire_n11Oll0O_dataout : STD_LOGIC; + SIGNAL wire_n11Oll1i_dataout : STD_LOGIC; + SIGNAL wire_n11Oll1l_dataout : STD_LOGIC; + SIGNAL wire_n11Oll1O_dataout : STD_LOGIC; + SIGNAL wire_n11Olli_dataout : STD_LOGIC; + SIGNAL wire_n11Ollii_dataout : STD_LOGIC; + SIGNAL wire_n11Ollil_dataout : STD_LOGIC; + SIGNAL wire_n11OlliO_dataout : STD_LOGIC; + SIGNAL wire_n11Olll_dataout : STD_LOGIC; + SIGNAL wire_n11Ollli_dataout : STD_LOGIC; + SIGNAL wire_n11Ollll_dataout : STD_LOGIC; + SIGNAL wire_n11OlllO_dataout : STD_LOGIC; + SIGNAL wire_n11OllO_dataout : STD_LOGIC; + SIGNAL wire_n11OllOi_dataout : STD_LOGIC; + SIGNAL wire_n11OllOl_dataout : STD_LOGIC; + SIGNAL wire_n11OllOO_dataout : STD_LOGIC; + SIGNAL wire_n11OlO0i_dataout : STD_LOGIC; + SIGNAL wire_n11OlO0l_dataout : STD_LOGIC; + SIGNAL wire_n11OlO0O_dataout : STD_LOGIC; + SIGNAL wire_n11OlO1i_dataout : STD_LOGIC; + SIGNAL wire_n11OlO1l_dataout : STD_LOGIC; + SIGNAL wire_n11OlO1O_dataout : STD_LOGIC; + SIGNAL wire_n11OlOi_dataout : STD_LOGIC; + SIGNAL wire_n11OlOii_dataout : STD_LOGIC; + SIGNAL wire_n11OlOil_dataout : STD_LOGIC; + SIGNAL wire_n11OlOiO_dataout : STD_LOGIC; + SIGNAL wire_n11OlOl_dataout : STD_LOGIC; + SIGNAL wire_n11OlOli_dataout : STD_LOGIC; + SIGNAL wire_n11OlOll_dataout : STD_LOGIC; + SIGNAL wire_n11OlOlO_dataout : STD_LOGIC; + SIGNAL wire_n11OlOO_dataout : STD_LOGIC; + SIGNAL wire_n11OlOOi_dataout : STD_LOGIC; + SIGNAL wire_n11OlOOl_dataout : STD_LOGIC; + SIGNAL wire_n11OlOOO_dataout : STD_LOGIC; + SIGNAL wire_n11OO00i_dataout : STD_LOGIC; + SIGNAL wire_n11OO00l_dataout : STD_LOGIC; + SIGNAL wire_n11OO00O_dataout : STD_LOGIC; + SIGNAL wire_n11OO01i_dataout : STD_LOGIC; + SIGNAL wire_n11OO01l_dataout : STD_LOGIC; + SIGNAL wire_n11OO01O_dataout : STD_LOGIC; + SIGNAL wire_n11OO0i_dataout : STD_LOGIC; + SIGNAL wire_n11OO0ii_dataout : STD_LOGIC; + SIGNAL wire_n11OO0il_dataout : STD_LOGIC; + SIGNAL wire_n11OO0iO_dataout : STD_LOGIC; + SIGNAL wire_n11OO0l_dataout : STD_LOGIC; + SIGNAL wire_n11OO0li_dataout : STD_LOGIC; + SIGNAL wire_n11OO0ll_dataout : STD_LOGIC; + SIGNAL wire_n11OO0lO_dataout : STD_LOGIC; + SIGNAL wire_n11OO0O_dataout : STD_LOGIC; + SIGNAL wire_n11OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n11OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n11OO0OO_dataout : STD_LOGIC; + SIGNAL wire_n11OO10i_dataout : STD_LOGIC; + SIGNAL wire_n11OO10l_dataout : STD_LOGIC; + SIGNAL wire_n11OO10O_dataout : STD_LOGIC; + SIGNAL wire_n11OO11i_dataout : STD_LOGIC; + SIGNAL wire_n11OO11l_dataout : STD_LOGIC; + SIGNAL wire_n11OO11O_dataout : STD_LOGIC; + SIGNAL wire_n11OO1i_dataout : STD_LOGIC; + SIGNAL wire_n11OO1ii_dataout : STD_LOGIC; + SIGNAL wire_n11OO1il_dataout : STD_LOGIC; + SIGNAL wire_n11OO1iO_dataout : STD_LOGIC; + SIGNAL wire_n11OO1l_dataout : STD_LOGIC; + SIGNAL wire_n11OO1li_dataout : STD_LOGIC; + SIGNAL wire_n11OO1ll_dataout : STD_LOGIC; + SIGNAL wire_n11OO1lO_dataout : STD_LOGIC; + SIGNAL wire_n11OO1O_dataout : STD_LOGIC; + SIGNAL wire_n11OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n11OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n11OO1OO_dataout : STD_LOGIC; + SIGNAL wire_n11OOi0i_dataout : STD_LOGIC; + SIGNAL wire_n11OOi0l_dataout : STD_LOGIC; + SIGNAL wire_n11OOi0O_dataout : STD_LOGIC; + SIGNAL wire_n11OOi1i_dataout : STD_LOGIC; + SIGNAL wire_n11OOi1l_dataout : STD_LOGIC; + SIGNAL wire_n11OOi1O_dataout : STD_LOGIC; + SIGNAL wire_n11OOii_dataout : STD_LOGIC; + SIGNAL wire_n11OOiii_dataout : STD_LOGIC; + SIGNAL wire_n11OOiil_dataout : STD_LOGIC; + SIGNAL wire_n11OOiiO_dataout : STD_LOGIC; + SIGNAL wire_n11OOil_dataout : STD_LOGIC; + SIGNAL wire_n11OOili_dataout : STD_LOGIC; + SIGNAL wire_n11OOill_dataout : STD_LOGIC; + SIGNAL wire_n11OOilO_dataout : STD_LOGIC; + SIGNAL wire_n11OOiO_dataout : STD_LOGIC; + SIGNAL wire_n11OOiOi_dataout : STD_LOGIC; + SIGNAL wire_n11OOiOl_dataout : STD_LOGIC; + SIGNAL wire_n11OOiOO_dataout : STD_LOGIC; + SIGNAL wire_n11OOl0i_dataout : STD_LOGIC; + SIGNAL wire_n11OOl0l_dataout : STD_LOGIC; + SIGNAL wire_n11OOl0O_dataout : STD_LOGIC; + SIGNAL wire_n11OOl1i_dataout : STD_LOGIC; + SIGNAL wire_n11OOl1l_dataout : STD_LOGIC; + SIGNAL wire_n11OOl1O_dataout : STD_LOGIC; + SIGNAL wire_n11OOli_dataout : STD_LOGIC; + SIGNAL wire_n11OOlii_dataout : STD_LOGIC; + SIGNAL wire_n11OOlil_dataout : STD_LOGIC; + SIGNAL wire_n11OOliO_dataout : STD_LOGIC; + SIGNAL wire_n11OOll_dataout : STD_LOGIC; + SIGNAL wire_n11OOlli_dataout : STD_LOGIC; + SIGNAL wire_n11OOlll_dataout : STD_LOGIC; + SIGNAL wire_n11OOllO_dataout : STD_LOGIC; + SIGNAL wire_n11OOlO_dataout : STD_LOGIC; + SIGNAL wire_n11OOlOi_dataout : STD_LOGIC; + SIGNAL wire_n11OOlOl_dataout : STD_LOGIC; + SIGNAL wire_n11OOlOO_dataout : STD_LOGIC; + SIGNAL wire_n11OOO0i_dataout : STD_LOGIC; + SIGNAL wire_n11OOO1i_dataout : STD_LOGIC; + SIGNAL wire_n11OOO1l_dataout : STD_LOGIC; + SIGNAL wire_n11OOO1O_dataout : STD_LOGIC; + SIGNAL wire_n11OOOi_dataout : STD_LOGIC; + SIGNAL wire_n11OOOl_dataout : STD_LOGIC; + SIGNAL wire_n11OOOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0000i_dataout : STD_LOGIC; + SIGNAL wire_n1i0000l_dataout : STD_LOGIC; + SIGNAL wire_n1i0000O_dataout : STD_LOGIC; + SIGNAL wire_n1i0001i_dataout : STD_LOGIC; + SIGNAL wire_n1i0001l_dataout : STD_LOGIC; + SIGNAL wire_n1i0001O_dataout : STD_LOGIC; + SIGNAL wire_n1i000i_dataout : STD_LOGIC; + SIGNAL wire_n1i000ii_dataout : STD_LOGIC; + SIGNAL wire_n1i000il_dataout : STD_LOGIC; + SIGNAL wire_n1i000iO_dataout : STD_LOGIC; + SIGNAL wire_n1i000l_dataout : STD_LOGIC; + SIGNAL wire_n1i000li_dataout : STD_LOGIC; + SIGNAL wire_n1i000ll_dataout : STD_LOGIC; + SIGNAL wire_n1i000lO_dataout : STD_LOGIC; + SIGNAL wire_n1i000O_dataout : STD_LOGIC; + SIGNAL wire_n1i000Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i000Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i000OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0010i_dataout : STD_LOGIC; + SIGNAL wire_n1i0010l_dataout : STD_LOGIC; + SIGNAL wire_n1i0011i_dataout : STD_LOGIC; + SIGNAL wire_n1i0011l_dataout : STD_LOGIC; + SIGNAL wire_n1i0011O_dataout : STD_LOGIC; + SIGNAL wire_n1i001i_dataout : STD_LOGIC; + SIGNAL wire_n1i001iO_dataout : STD_LOGIC; + SIGNAL wire_n1i001l_dataout : STD_LOGIC; + SIGNAL wire_n1i001li_dataout : STD_LOGIC; + SIGNAL wire_n1i001ll_dataout : STD_LOGIC; + SIGNAL wire_n1i001lO_dataout : STD_LOGIC; + SIGNAL wire_n1i001O_dataout : STD_LOGIC; + SIGNAL wire_n1i001Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i001Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i001OO_dataout : STD_LOGIC; + SIGNAL wire_n1i00i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i00i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i00i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i00i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i00i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i00i1O_dataout : STD_LOGIC; + SIGNAL wire_n1i00ii_dataout : STD_LOGIC; + SIGNAL wire_n1i00iii_dataout : STD_LOGIC; + SIGNAL wire_n1i00iil_dataout : STD_LOGIC; + SIGNAL wire_n1i00iiO_dataout : STD_LOGIC; + SIGNAL wire_n1i00il_dataout : STD_LOGIC; + SIGNAL wire_n1i00ili_dataout : STD_LOGIC; + SIGNAL wire_n1i00ill_dataout : STD_LOGIC; + SIGNAL wire_n1i00ilO_dataout : STD_LOGIC; + SIGNAL wire_n1i00iO_dataout : STD_LOGIC; + SIGNAL wire_n1i00iOi_dataout : STD_LOGIC; + SIGNAL wire_n1i00iOl_dataout : STD_LOGIC; + SIGNAL wire_n1i00iOO_dataout : STD_LOGIC; + SIGNAL wire_n1i00l0i_dataout : STD_LOGIC; + SIGNAL wire_n1i00l0l_dataout : STD_LOGIC; + SIGNAL wire_n1i00l0O_dataout : STD_LOGIC; + SIGNAL wire_n1i00l1i_dataout : STD_LOGIC; + SIGNAL wire_n1i00l1l_dataout : STD_LOGIC; + SIGNAL wire_n1i00l1O_dataout : STD_LOGIC; + SIGNAL wire_n1i00li_dataout : STD_LOGIC; + SIGNAL wire_n1i00lii_dataout : STD_LOGIC; + SIGNAL wire_n1i00lil_dataout : STD_LOGIC; + SIGNAL wire_n1i00liO_dataout : STD_LOGIC; + SIGNAL wire_n1i00ll_dataout : STD_LOGIC; + SIGNAL wire_n1i00lli_dataout : STD_LOGIC; + SIGNAL wire_n1i00lll_dataout : STD_LOGIC; + SIGNAL wire_n1i00llO_dataout : STD_LOGIC; + SIGNAL wire_n1i00lO_dataout : STD_LOGIC; + SIGNAL wire_n1i00lOi_dataout : STD_LOGIC; + SIGNAL wire_n1i00lOl_dataout : STD_LOGIC; + SIGNAL wire_n1i00lOO_dataout : STD_LOGIC; + SIGNAL wire_n1i00O0i_dataout : STD_LOGIC; + SIGNAL wire_n1i00O0l_dataout : STD_LOGIC; + SIGNAL wire_n1i00O0O_dataout : STD_LOGIC; + SIGNAL wire_n1i00O1i_dataout : STD_LOGIC; + SIGNAL wire_n1i00O1l_dataout : STD_LOGIC; + SIGNAL wire_n1i00O1O_dataout : STD_LOGIC; + SIGNAL wire_n1i00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i00Oii_dataout : STD_LOGIC; + SIGNAL wire_n1i00Oil_dataout : STD_LOGIC; + SIGNAL wire_n1i00OiO_dataout : STD_LOGIC; + SIGNAL wire_n1i00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i00Oli_dataout : STD_LOGIC; + SIGNAL wire_n1i00Oll_dataout : STD_LOGIC; + SIGNAL wire_n1i00OlO_dataout : STD_LOGIC; + SIGNAL wire_n1i00OO_dataout : STD_LOGIC; + SIGNAL wire_n1i00OOi_dataout : STD_LOGIC; + SIGNAL wire_n1i00OOl_dataout : STD_LOGIC; + SIGNAL wire_n1i00OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0100i_dataout : STD_LOGIC; + SIGNAL wire_n1i0100l_dataout : STD_LOGIC; + SIGNAL wire_n1i0100O_dataout : STD_LOGIC; + SIGNAL wire_n1i0101i_dataout : STD_LOGIC; + SIGNAL wire_n1i0101l_dataout : STD_LOGIC; + SIGNAL wire_n1i0101O_dataout : STD_LOGIC; + SIGNAL wire_n1i010i_dataout : STD_LOGIC; + SIGNAL wire_n1i010ii_dataout : STD_LOGIC; + SIGNAL wire_n1i010il_dataout : STD_LOGIC; + SIGNAL wire_n1i010iO_dataout : STD_LOGIC; + SIGNAL wire_n1i010l_dataout : STD_LOGIC; + SIGNAL wire_n1i010li_dataout : STD_LOGIC; + SIGNAL wire_n1i010ll_dataout : STD_LOGIC; + SIGNAL wire_n1i010lO_dataout : STD_LOGIC; + SIGNAL wire_n1i010O_dataout : STD_LOGIC; + SIGNAL wire_n1i010Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i010Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i010OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0110i_dataout : STD_LOGIC; + SIGNAL wire_n1i0110l_dataout : STD_LOGIC; + SIGNAL wire_n1i0110O_dataout : STD_LOGIC; + SIGNAL wire_n1i0111i_dataout : STD_LOGIC; + SIGNAL wire_n1i0111l_dataout : STD_LOGIC; + SIGNAL wire_n1i0111O_dataout : STD_LOGIC; + SIGNAL wire_n1i011i_dataout : STD_LOGIC; + SIGNAL wire_n1i011ii_dataout : STD_LOGIC; + SIGNAL wire_n1i011il_dataout : STD_LOGIC; + SIGNAL wire_n1i011iO_dataout : STD_LOGIC; + SIGNAL wire_n1i011l_dataout : STD_LOGIC; + SIGNAL wire_n1i011li_dataout : STD_LOGIC; + SIGNAL wire_n1i011ll_dataout : STD_LOGIC; + SIGNAL wire_n1i011lO_dataout : STD_LOGIC; + SIGNAL wire_n1i011O_dataout : STD_LOGIC; + SIGNAL wire_n1i011Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i011Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i011OO_dataout : STD_LOGIC; + SIGNAL wire_n1i01i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i01i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i01i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i01i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i01i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i01i1O_dataout : STD_LOGIC; + SIGNAL wire_n1i01ii_dataout : STD_LOGIC; + SIGNAL wire_n1i01iii_dataout : STD_LOGIC; + SIGNAL wire_n1i01iil_dataout : STD_LOGIC; + SIGNAL wire_n1i01iiO_dataout : STD_LOGIC; + SIGNAL wire_n1i01il_dataout : STD_LOGIC; + SIGNAL wire_n1i01ili_dataout : STD_LOGIC; + SIGNAL wire_n1i01ill_dataout : STD_LOGIC; + SIGNAL wire_n1i01ilO_dataout : STD_LOGIC; + SIGNAL wire_n1i01iO_dataout : STD_LOGIC; + SIGNAL wire_n1i01iOi_dataout : STD_LOGIC; + SIGNAL wire_n1i01iOl_dataout : STD_LOGIC; + SIGNAL wire_n1i01iOO_dataout : STD_LOGIC; + SIGNAL wire_n1i01l0l_dataout : STD_LOGIC; + SIGNAL wire_n1i01l1i_dataout : STD_LOGIC; + SIGNAL wire_n1i01l1l_dataout : STD_LOGIC; + SIGNAL wire_n1i01l1O_dataout : STD_LOGIC; + SIGNAL wire_n1i01li_dataout : STD_LOGIC; + SIGNAL wire_n1i01ll_dataout : STD_LOGIC; + SIGNAL wire_n1i01lO_dataout : STD_LOGIC; + SIGNAL wire_n1i01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i01OlO_dataout : STD_LOGIC; + SIGNAL wire_n1i01OO_dataout : STD_LOGIC; + SIGNAL wire_n1i01OOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0i00i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i00l_dataout : STD_LOGIC; + SIGNAL wire_n1i0i00O_dataout : STD_LOGIC; + SIGNAL wire_n1i0i01i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i01l_dataout : STD_LOGIC; + SIGNAL wire_n1i0i01O_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0ii_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0il_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0iO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0li_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0ll_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0lO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i0i0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i10i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i10l_dataout : STD_LOGIC; + SIGNAL wire_n1i0i10O_dataout : STD_LOGIC; + SIGNAL wire_n1i0i11i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i11l_dataout : STD_LOGIC; + SIGNAL wire_n1i0i11O_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1il_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1iO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1li_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1ll_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i0i1OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0ii1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0iii_dataout : STD_LOGIC; + SIGNAL wire_n1i0iiii_dataout : STD_LOGIC; + SIGNAL wire_n1i0iiil_dataout : STD_LOGIC; + SIGNAL wire_n1i0iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1i0iil_dataout : STD_LOGIC; + SIGNAL wire_n1i0iili_dataout : STD_LOGIC; + SIGNAL wire_n1i0iill_dataout : STD_LOGIC; + SIGNAL wire_n1i0iilO_dataout : STD_LOGIC; + SIGNAL wire_n1i0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1i0iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0il0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0il0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0il0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0il1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0il1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0il1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0ili_dataout : STD_LOGIC; + SIGNAL wire_n1i0ilii_dataout : STD_LOGIC; + SIGNAL wire_n1i0ilil_dataout : STD_LOGIC; + SIGNAL wire_n1i0iliO_dataout : STD_LOGIC; + SIGNAL wire_n1i0ill_dataout : STD_LOGIC; + SIGNAL wire_n1i0illi_dataout : STD_LOGIC; + SIGNAL wire_n1i0illl_dataout : STD_LOGIC; + SIGNAL wire_n1i0illO_dataout : STD_LOGIC; + SIGNAL wire_n1i0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1i0ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOii_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOil_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOli_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOll_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0l00i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l00l_dataout : STD_LOGIC; + SIGNAL wire_n1i0l00O_dataout : STD_LOGIC; + SIGNAL wire_n1i0l01i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l01l_dataout : STD_LOGIC; + SIGNAL wire_n1i0l01O_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0ii_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0il_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0iO_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0li_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0ll_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0lO_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i0l0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0l10i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l10l_dataout : STD_LOGIC; + SIGNAL wire_n1i0l10O_dataout : STD_LOGIC; + SIGNAL wire_n1i0l11i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l11l_dataout : STD_LOGIC; + SIGNAL wire_n1i0l11O_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1il_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1iO_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1li_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1ll_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i0l1OO_dataout : STD_LOGIC; + SIGNAL wire_n1i0li0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0li0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0li0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0li1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0li1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0li1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0lii_dataout : STD_LOGIC; + SIGNAL wire_n1i0liii_dataout : STD_LOGIC; + SIGNAL wire_n1i0liil_dataout : STD_LOGIC; + SIGNAL wire_n1i0liiO_dataout : STD_LOGIC; + SIGNAL wire_n1i0lil_dataout : STD_LOGIC; + SIGNAL wire_n1i0lili_dataout : STD_LOGIC; + SIGNAL wire_n1i0lill_dataout : STD_LOGIC; + SIGNAL wire_n1i0lilO_dataout : STD_LOGIC; + SIGNAL wire_n1i0liO_dataout : STD_LOGIC; + SIGNAL wire_n1i0liOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0liOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0liOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0ll1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0lli_dataout : STD_LOGIC; + SIGNAL wire_n1i0llii_dataout : STD_LOGIC; + SIGNAL wire_n1i0llil_dataout : STD_LOGIC; + SIGNAL wire_n1i0lliO_dataout : STD_LOGIC; + SIGNAL wire_n1i0lll_dataout : STD_LOGIC; + SIGNAL wire_n1i0llli_dataout : STD_LOGIC; + SIGNAL wire_n1i0llll_dataout : STD_LOGIC; + SIGNAL wire_n1i0lllO_dataout : STD_LOGIC; + SIGNAL wire_n1i0llO_dataout : STD_LOGIC; + SIGNAL wire_n1i0llOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0llOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0llOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0lO1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOii_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOil_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOiO_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOli_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOll_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOlO_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0lOOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1i0O11i_dataout : STD_LOGIC; + SIGNAL wire_n1i0O11l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O11O_dataout : STD_LOGIC; + SIGNAL wire_n1i0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1i0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1i0Oill_dataout : STD_LOGIC; + SIGNAL wire_n1i0OilO_dataout : STD_LOGIC; + SIGNAL wire_n1i0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1i0OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0OiOO_dataout : STD_LOGIC; + SIGNAL wire_n1i0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n1i0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n1i0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1i0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n1i0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1i0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1i0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1i0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1i0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1i0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1000i_dataout : STD_LOGIC; + SIGNAL wire_n1i1000l_dataout : STD_LOGIC; + SIGNAL wire_n1i1000O_dataout : STD_LOGIC; + SIGNAL wire_n1i1001i_dataout : STD_LOGIC; + SIGNAL wire_n1i1001l_dataout : STD_LOGIC; + SIGNAL wire_n1i1001O_dataout : STD_LOGIC; + SIGNAL wire_n1i100i_dataout : STD_LOGIC; + SIGNAL wire_n1i100ii_dataout : STD_LOGIC; + SIGNAL wire_n1i100il_dataout : STD_LOGIC; + SIGNAL wire_n1i100iO_dataout : STD_LOGIC; + SIGNAL wire_n1i100l_dataout : STD_LOGIC; + SIGNAL wire_n1i100li_dataout : STD_LOGIC; + SIGNAL wire_n1i100ll_dataout : STD_LOGIC; + SIGNAL wire_n1i100lO_dataout : STD_LOGIC; + SIGNAL wire_n1i100O_dataout : STD_LOGIC; + SIGNAL wire_n1i100Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i100Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i100OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1010i_dataout : STD_LOGIC; + SIGNAL wire_n1i1010l_dataout : STD_LOGIC; + SIGNAL wire_n1i1010O_dataout : STD_LOGIC; + SIGNAL wire_n1i1011i_dataout : STD_LOGIC; + SIGNAL wire_n1i1011l_dataout : STD_LOGIC; + SIGNAL wire_n1i1011O_dataout : STD_LOGIC; + SIGNAL wire_n1i101i_dataout : STD_LOGIC; + SIGNAL wire_n1i101ii_dataout : STD_LOGIC; + SIGNAL wire_n1i101il_dataout : STD_LOGIC; + SIGNAL wire_n1i101iO_dataout : STD_LOGIC; + SIGNAL wire_n1i101l_dataout : STD_LOGIC; + SIGNAL wire_n1i101li_dataout : STD_LOGIC; + SIGNAL wire_n1i101ll_dataout : STD_LOGIC; + SIGNAL wire_n1i101lO_dataout : STD_LOGIC; + SIGNAL wire_n1i101O_dataout : STD_LOGIC; + SIGNAL wire_n1i101Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i101Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i101OO_dataout : STD_LOGIC; + SIGNAL wire_n1i10i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i10i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i10i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i10i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i10i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i10i1O_dataout : STD_LOGIC; + SIGNAL wire_n1i10ii_dataout : STD_LOGIC; + SIGNAL wire_n1i10iii_dataout : STD_LOGIC; + SIGNAL wire_n1i10iil_dataout : STD_LOGIC; + SIGNAL wire_n1i10iiO_dataout : STD_LOGIC; + SIGNAL wire_n1i10il_dataout : STD_LOGIC; + SIGNAL wire_n1i10ili_dataout : STD_LOGIC; + SIGNAL wire_n1i10ill_dataout : STD_LOGIC; + SIGNAL wire_n1i10ilO_dataout : STD_LOGIC; + SIGNAL wire_n1i10iO_dataout : STD_LOGIC; + SIGNAL wire_n1i10iOi_dataout : STD_LOGIC; + SIGNAL wire_n1i10iOl_dataout : STD_LOGIC; + SIGNAL wire_n1i10iOO_dataout : STD_LOGIC; + SIGNAL wire_n1i10l0i_dataout : STD_LOGIC; + SIGNAL wire_n1i10l0l_dataout : STD_LOGIC; + SIGNAL wire_n1i10l0O_dataout : STD_LOGIC; + SIGNAL wire_n1i10l1i_dataout : STD_LOGIC; + SIGNAL wire_n1i10l1l_dataout : STD_LOGIC; + SIGNAL wire_n1i10l1O_dataout : STD_LOGIC; + SIGNAL wire_n1i10li_dataout : STD_LOGIC; + SIGNAL wire_n1i10lii_dataout : STD_LOGIC; + SIGNAL wire_n1i10lil_dataout : STD_LOGIC; + SIGNAL wire_n1i10liO_dataout : STD_LOGIC; + SIGNAL wire_n1i10ll_dataout : STD_LOGIC; + SIGNAL wire_n1i10lli_dataout : STD_LOGIC; + SIGNAL wire_n1i10lll_dataout : STD_LOGIC; + SIGNAL wire_n1i10llO_dataout : STD_LOGIC; + SIGNAL wire_n1i10lO_dataout : STD_LOGIC; + SIGNAL wire_n1i10lOi_dataout : STD_LOGIC; + SIGNAL wire_n1i10lOl_dataout : STD_LOGIC; + SIGNAL wire_n1i10lOO_dataout : STD_LOGIC; + SIGNAL wire_n1i10O0i_dataout : STD_LOGIC; + SIGNAL wire_n1i10O0l_dataout : STD_LOGIC; + SIGNAL wire_n1i10O0O_dataout : STD_LOGIC; + SIGNAL wire_n1i10O1i_dataout : STD_LOGIC; + SIGNAL wire_n1i10O1l_dataout : STD_LOGIC; + SIGNAL wire_n1i10O1O_dataout : STD_LOGIC; + SIGNAL wire_n1i10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i10Oii_dataout : STD_LOGIC; + SIGNAL wire_n1i10Oil_dataout : STD_LOGIC; + SIGNAL wire_n1i10OiO_dataout : STD_LOGIC; + SIGNAL wire_n1i10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i10Oli_dataout : STD_LOGIC; + SIGNAL wire_n1i10Oll_dataout : STD_LOGIC; + SIGNAL wire_n1i10OlO_dataout : STD_LOGIC; + SIGNAL wire_n1i10OO_dataout : STD_LOGIC; + SIGNAL wire_n1i10OOi_dataout : STD_LOGIC; + SIGNAL wire_n1i10OOl_dataout : STD_LOGIC; + SIGNAL wire_n1i10OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1100i_dataout : STD_LOGIC; + SIGNAL wire_n1i1100l_dataout : STD_LOGIC; + SIGNAL wire_n1i1101i_dataout : STD_LOGIC; + SIGNAL wire_n1i1101l_dataout : STD_LOGIC; + SIGNAL wire_n1i110i_dataout : STD_LOGIC; + SIGNAL wire_n1i110l_dataout : STD_LOGIC; + SIGNAL wire_n1i110O_dataout : STD_LOGIC; + SIGNAL wire_n1i1110i_dataout : STD_LOGIC; + SIGNAL wire_n1i1110l_dataout : STD_LOGIC; + SIGNAL wire_n1i1110O_dataout : STD_LOGIC; + SIGNAL wire_n1i1111i_dataout : STD_LOGIC; + SIGNAL wire_n1i1111l_dataout : STD_LOGIC; + SIGNAL wire_n1i1111O_dataout : STD_LOGIC; + SIGNAL wire_n1i111i_dataout : STD_LOGIC; + SIGNAL wire_n1i111ii_dataout : STD_LOGIC; + SIGNAL wire_n1i111il_dataout : STD_LOGIC; + SIGNAL wire_n1i111iO_dataout : STD_LOGIC; + SIGNAL wire_n1i111l_dataout : STD_LOGIC; + SIGNAL wire_n1i111li_dataout : STD_LOGIC; + SIGNAL wire_n1i111ll_dataout : STD_LOGIC; + SIGNAL wire_n1i111lO_dataout : STD_LOGIC; + SIGNAL wire_n1i111O_dataout : STD_LOGIC; + SIGNAL wire_n1i111Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i111Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i111OO_dataout : STD_LOGIC; + SIGNAL wire_n1i11i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i11i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i11i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i11i1O_dataout : STD_LOGIC; + SIGNAL wire_n1i11ii_dataout : STD_LOGIC; + SIGNAL wire_n1i11iii_dataout : STD_LOGIC; + SIGNAL wire_n1i11iil_dataout : STD_LOGIC; + SIGNAL wire_n1i11iiO_dataout : STD_LOGIC; + SIGNAL wire_n1i11il_dataout : STD_LOGIC; + SIGNAL wire_n1i11ili_dataout : STD_LOGIC; + SIGNAL wire_n1i11ill_dataout : STD_LOGIC; + SIGNAL wire_n1i11ilO_dataout : STD_LOGIC; + SIGNAL wire_n1i11iO_dataout : STD_LOGIC; + SIGNAL wire_n1i11iOi_dataout : STD_LOGIC; + SIGNAL wire_n1i11iOl_dataout : STD_LOGIC; + SIGNAL wire_n1i11iOO_dataout : STD_LOGIC; + SIGNAL wire_n1i11l0i_dataout : STD_LOGIC; + SIGNAL wire_n1i11l0l_dataout : STD_LOGIC; + SIGNAL wire_n1i11l0O_dataout : STD_LOGIC; + SIGNAL wire_n1i11l1i_dataout : STD_LOGIC; + SIGNAL wire_n1i11l1l_dataout : STD_LOGIC; + SIGNAL wire_n1i11l1O_dataout : STD_LOGIC; + SIGNAL wire_n1i11li_dataout : STD_LOGIC; + SIGNAL wire_n1i11lii_dataout : STD_LOGIC; + SIGNAL wire_n1i11lil_dataout : STD_LOGIC; + SIGNAL wire_n1i11liO_dataout : STD_LOGIC; + SIGNAL wire_n1i11ll_dataout : STD_LOGIC; + SIGNAL wire_n1i11lli_dataout : STD_LOGIC; + SIGNAL wire_n1i11lll_dataout : STD_LOGIC; + SIGNAL wire_n1i11llO_dataout : STD_LOGIC; + SIGNAL wire_n1i11lO_dataout : STD_LOGIC; + SIGNAL wire_n1i11lOi_dataout : STD_LOGIC; + SIGNAL wire_n1i11lOl_dataout : STD_LOGIC; + SIGNAL wire_n1i11O0i_dataout : STD_LOGIC; + SIGNAL wire_n1i11O0l_dataout : STD_LOGIC; + SIGNAL wire_n1i11O0O_dataout : STD_LOGIC; + SIGNAL wire_n1i11O1i_dataout : STD_LOGIC; + SIGNAL wire_n1i11O1l_dataout : STD_LOGIC; + SIGNAL wire_n1i11O1O_dataout : STD_LOGIC; + SIGNAL wire_n1i11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i11Oii_dataout : STD_LOGIC; + SIGNAL wire_n1i11Oil_dataout : STD_LOGIC; + SIGNAL wire_n1i11OiO_dataout : STD_LOGIC; + SIGNAL wire_n1i11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i11Oli_dataout : STD_LOGIC; + SIGNAL wire_n1i11Oll_dataout : STD_LOGIC; + SIGNAL wire_n1i11OlO_dataout : STD_LOGIC; + SIGNAL wire_n1i11OO_dataout : STD_LOGIC; + SIGNAL wire_n1i11OOi_dataout : STD_LOGIC; + SIGNAL wire_n1i11OOl_dataout : STD_LOGIC; + SIGNAL wire_n1i11OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1i00i_dataout : STD_LOGIC; + SIGNAL wire_n1i1i00l_dataout : STD_LOGIC; + SIGNAL wire_n1i1i00O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i01i_dataout : STD_LOGIC; + SIGNAL wire_n1i1i01l_dataout : STD_LOGIC; + SIGNAL wire_n1i1i01O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0il_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0li_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0ll_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0lO_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1i0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1i10i_dataout : STD_LOGIC; + SIGNAL wire_n1i1i10l_dataout : STD_LOGIC; + SIGNAL wire_n1i1i10O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i11i_dataout : STD_LOGIC; + SIGNAL wire_n1i1i11l_dataout : STD_LOGIC; + SIGNAL wire_n1i1i11O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1il_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1li_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1ll_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1i1OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1ii1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1iii_dataout : STD_LOGIC; + SIGNAL wire_n1i1iiii_dataout : STD_LOGIC; + SIGNAL wire_n1i1iiil_dataout : STD_LOGIC; + SIGNAL wire_n1i1iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1iil_dataout : STD_LOGIC; + SIGNAL wire_n1i1iili_dataout : STD_LOGIC; + SIGNAL wire_n1i1iill_dataout : STD_LOGIC; + SIGNAL wire_n1i1iilO_dataout : STD_LOGIC; + SIGNAL wire_n1i1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1il0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1il0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1il0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1il1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1il1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1il1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1ili_dataout : STD_LOGIC; + SIGNAL wire_n1i1ilii_dataout : STD_LOGIC; + SIGNAL wire_n1i1ilil_dataout : STD_LOGIC; + SIGNAL wire_n1i1iliO_dataout : STD_LOGIC; + SIGNAL wire_n1i1ill_dataout : STD_LOGIC; + SIGNAL wire_n1i1illi_dataout : STD_LOGIC; + SIGNAL wire_n1i1illl_dataout : STD_LOGIC; + SIGNAL wire_n1i1illO_dataout : STD_LOGIC; + SIGNAL wire_n1i1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1i1ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOii_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOil_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOli_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOll_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1l00i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l00l_dataout : STD_LOGIC; + SIGNAL wire_n1i1l00O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l01i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l01l_dataout : STD_LOGIC; + SIGNAL wire_n1i1l01O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0il_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0li_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0lO_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1l0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1l10i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l10l_dataout : STD_LOGIC; + SIGNAL wire_n1i1l10O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l11i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l11l_dataout : STD_LOGIC; + SIGNAL wire_n1i1l11O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1il_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1li_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1ll_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1l1OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1li0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1li0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1li0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1li1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1li1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1li1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1lii_dataout : STD_LOGIC; + SIGNAL wire_n1i1liii_dataout : STD_LOGIC; + SIGNAL wire_n1i1liil_dataout : STD_LOGIC; + SIGNAL wire_n1i1liiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1lil_dataout : STD_LOGIC; + SIGNAL wire_n1i1lili_dataout : STD_LOGIC; + SIGNAL wire_n1i1lill_dataout : STD_LOGIC; + SIGNAL wire_n1i1lilO_dataout : STD_LOGIC; + SIGNAL wire_n1i1liO_dataout : STD_LOGIC; + SIGNAL wire_n1i1liOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1liOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1liOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1ll1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1lli_dataout : STD_LOGIC; + SIGNAL wire_n1i1llii_dataout : STD_LOGIC; + SIGNAL wire_n1i1llil_dataout : STD_LOGIC; + SIGNAL wire_n1i1lliO_dataout : STD_LOGIC; + SIGNAL wire_n1i1lll_dataout : STD_LOGIC; + SIGNAL wire_n1i1llli_dataout : STD_LOGIC; + SIGNAL wire_n1i1llll_dataout : STD_LOGIC; + SIGNAL wire_n1i1lllO_dataout : STD_LOGIC; + SIGNAL wire_n1i1llO_dataout : STD_LOGIC; + SIGNAL wire_n1i1llOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1llOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1llOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1lO1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOii_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOil_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOli_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOll_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOlO_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1lOOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1O00i_dataout : STD_LOGIC; + SIGNAL wire_n1i1O00l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O00O_dataout : STD_LOGIC; + SIGNAL wire_n1i1O01i_dataout : STD_LOGIC; + SIGNAL wire_n1i1O01l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O01O_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0il_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1O0OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1O10i_dataout : STD_LOGIC; + SIGNAL wire_n1i1O10l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O10O_dataout : STD_LOGIC; + SIGNAL wire_n1i1O11i_dataout : STD_LOGIC; + SIGNAL wire_n1i1O11l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O11O_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1ii_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1il_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1iO_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1li_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1ll_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1lO_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1i1O1OO_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oiii_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oiil_dataout : STD_LOGIC; + SIGNAL wire_n1i1OiiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oili_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oill_dataout : STD_LOGIC; + SIGNAL wire_n1i1OilO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1OiOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1i1Olii_dataout : STD_LOGIC; + SIGNAL wire_n1i1Olil_dataout : STD_LOGIC; + SIGNAL wire_n1i1OliO_dataout : STD_LOGIC; + SIGNAL wire_n1i1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1i1Olli_dataout : STD_LOGIC; + SIGNAL wire_n1i1Olll_dataout : STD_LOGIC; + SIGNAL wire_n1i1OllO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OlOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1OlOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1OlOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO0i_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO0l_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO0O_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO1i_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO1l_dataout : STD_LOGIC; + SIGNAL wire_n1i1OO1O_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOii_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOil_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOiO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOli_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOll_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOlO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOOi_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOOl_dataout : STD_LOGIC; + SIGNAL wire_n1i1OOOO_dataout : STD_LOGIC; + SIGNAL wire_n1ii000i_dataout : STD_LOGIC; + SIGNAL wire_n1ii000l_dataout : STD_LOGIC; + SIGNAL wire_n1ii000O_dataout : STD_LOGIC; + SIGNAL wire_n1ii001i_dataout : STD_LOGIC; + SIGNAL wire_n1ii001l_dataout : STD_LOGIC; + SIGNAL wire_n1ii001O_dataout : STD_LOGIC; + SIGNAL wire_n1ii00i_dataout : STD_LOGIC; + SIGNAL wire_n1ii00ii_dataout : STD_LOGIC; + SIGNAL wire_n1ii00il_dataout : STD_LOGIC; + SIGNAL wire_n1ii00iO_dataout : STD_LOGIC; + SIGNAL wire_n1ii00l_dataout : STD_LOGIC; + SIGNAL wire_n1ii00li_dataout : STD_LOGIC; + SIGNAL wire_n1ii00ll_dataout : STD_LOGIC; + SIGNAL wire_n1ii00lO_dataout : STD_LOGIC; + SIGNAL wire_n1ii00O_dataout : STD_LOGIC; + SIGNAL wire_n1ii00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ii00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ii00OO_dataout : STD_LOGIC; + SIGNAL wire_n1ii010i_dataout : STD_LOGIC; + SIGNAL wire_n1ii010l_dataout : STD_LOGIC; + SIGNAL wire_n1ii010O_dataout : STD_LOGIC; + SIGNAL wire_n1ii011i_dataout : STD_LOGIC; + SIGNAL wire_n1ii011l_dataout : STD_LOGIC; + SIGNAL wire_n1ii011O_dataout : STD_LOGIC; + SIGNAL wire_n1ii01i_dataout : STD_LOGIC; + SIGNAL wire_n1ii01ii_dataout : STD_LOGIC; + SIGNAL wire_n1ii01il_dataout : STD_LOGIC; + SIGNAL wire_n1ii01iO_dataout : STD_LOGIC; + SIGNAL wire_n1ii01l_dataout : STD_LOGIC; + SIGNAL wire_n1ii01li_dataout : STD_LOGIC; + SIGNAL wire_n1ii01ll_dataout : STD_LOGIC; + SIGNAL wire_n1ii01lO_dataout : STD_LOGIC; + SIGNAL wire_n1ii01O_dataout : STD_LOGIC; + SIGNAL wire_n1ii01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ii01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ii01OO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii0ii_dataout : STD_LOGIC; + SIGNAL wire_n1ii0iii_dataout : STD_LOGIC; + SIGNAL wire_n1ii0iil_dataout : STD_LOGIC; + SIGNAL wire_n1ii0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0il_dataout : STD_LOGIC; + SIGNAL wire_n1ii0ili_dataout : STD_LOGIC; + SIGNAL wire_n1ii0ill_dataout : STD_LOGIC; + SIGNAL wire_n1ii0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0iO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1ii0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1ii0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l0i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l1l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0l1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii0li_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lii_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lil_dataout : STD_LOGIC; + SIGNAL wire_n1ii0liO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0ll_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lli_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lll_dataout : STD_LOGIC; + SIGNAL wire_n1ii0llO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1ii0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1ii0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ii0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1ii0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1ii0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ii0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1ii0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1ii0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0OO_dataout : STD_LOGIC; + SIGNAL wire_n1ii0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1ii0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1ii0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1ii10i_dataout : STD_LOGIC; + SIGNAL wire_n1ii10l_dataout : STD_LOGIC; + SIGNAL wire_n1ii10O_dataout : STD_LOGIC; + SIGNAL wire_n1ii11i_dataout : STD_LOGIC; + SIGNAL wire_n1ii11l_dataout : STD_LOGIC; + SIGNAL wire_n1ii11O_dataout : STD_LOGIC; + SIGNAL wire_n1ii1ii_dataout : STD_LOGIC; + SIGNAL wire_n1ii1il_dataout : STD_LOGIC; + SIGNAL wire_n1ii1iO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1ii1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii1li_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lii_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lil_dataout : STD_LOGIC; + SIGNAL wire_n1ii1liO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1ll_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lli_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lll_dataout : STD_LOGIC; + SIGNAL wire_n1ii1llO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1ii1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1ii1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ii1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1ii1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1ii1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ii1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1ii1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1ii1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1OO_dataout : STD_LOGIC; + SIGNAL wire_n1ii1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1ii1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1ii1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1iii00i_dataout : STD_LOGIC; + SIGNAL wire_n1iii00l_dataout : STD_LOGIC; + SIGNAL wire_n1iii00O_dataout : STD_LOGIC; + SIGNAL wire_n1iii01i_dataout : STD_LOGIC; + SIGNAL wire_n1iii01l_dataout : STD_LOGIC; + SIGNAL wire_n1iii01O_dataout : STD_LOGIC; + SIGNAL wire_n1iii0i_dataout : STD_LOGIC; + SIGNAL wire_n1iii0ii_dataout : STD_LOGIC; + SIGNAL wire_n1iii0il_dataout : STD_LOGIC; + SIGNAL wire_n1iii0iO_dataout : STD_LOGIC; + SIGNAL wire_n1iii0l_dataout : STD_LOGIC; + SIGNAL wire_n1iii0li_dataout : STD_LOGIC; + SIGNAL wire_n1iii0ll_dataout : STD_LOGIC; + SIGNAL wire_n1iii0lO_dataout : STD_LOGIC; + SIGNAL wire_n1iii0O_dataout : STD_LOGIC; + SIGNAL wire_n1iii10i_dataout : STD_LOGIC; + SIGNAL wire_n1iii10l_dataout : STD_LOGIC; + SIGNAL wire_n1iii10O_dataout : STD_LOGIC; + SIGNAL wire_n1iii11O_dataout : STD_LOGIC; + SIGNAL wire_n1iii1i_dataout : STD_LOGIC; + SIGNAL wire_n1iii1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iii1il_dataout : STD_LOGIC; + SIGNAL wire_n1iii1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iii1l_dataout : STD_LOGIC; + SIGNAL wire_n1iii1li_dataout : STD_LOGIC; + SIGNAL wire_n1iii1ll_dataout : STD_LOGIC; + SIGNAL wire_n1iii1lO_dataout : STD_LOGIC; + SIGNAL wire_n1iii1O_dataout : STD_LOGIC; + SIGNAL wire_n1iii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iii1OO_dataout : STD_LOGIC; + SIGNAL wire_n1iiii0O_dataout : STD_LOGIC; + SIGNAL wire_n1iiii1l_dataout : STD_LOGIC; + SIGNAL wire_n1iiiii_dataout : STD_LOGIC; + SIGNAL wire_n1iiiiii_dataout : STD_LOGIC; + SIGNAL wire_n1iiiiil_dataout : STD_LOGIC; + SIGNAL wire_n1iiiiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iiiil_dataout : STD_LOGIC; + SIGNAL wire_n1iiiili_dataout : STD_LOGIC; + SIGNAL wire_n1iiiill_dataout : STD_LOGIC; + SIGNAL wire_n1iiiilO_dataout : STD_LOGIC; + SIGNAL wire_n1iiiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iiiiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiili_dataout : STD_LOGIC; + SIGNAL wire_n1iiilii_dataout : STD_LOGIC; + SIGNAL wire_n1iiilil_dataout : STD_LOGIC; + SIGNAL wire_n1iiill_dataout : STD_LOGIC; + SIGNAL wire_n1iiilll_dataout : STD_LOGIC; + SIGNAL wire_n1iiillO_dataout : STD_LOGIC; + SIGNAL wire_n1iiilO_dataout : STD_LOGIC; + SIGNAL wire_n1iiilOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiilOO_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iiiO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOii_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOil_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOli_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOll_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOO_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiiOOO_dataout : STD_LOGIC; + SIGNAL wire_n1iil00i_dataout : STD_LOGIC; + SIGNAL wire_n1iil00l_dataout : STD_LOGIC; + SIGNAL wire_n1iil00O_dataout : STD_LOGIC; + SIGNAL wire_n1iil01i_dataout : STD_LOGIC; + SIGNAL wire_n1iil01l_dataout : STD_LOGIC; + SIGNAL wire_n1iil01O_dataout : STD_LOGIC; + SIGNAL wire_n1iil0i_dataout : STD_LOGIC; + SIGNAL wire_n1iil0ii_dataout : STD_LOGIC; + SIGNAL wire_n1iil0il_dataout : STD_LOGIC; + SIGNAL wire_n1iil0iO_dataout : STD_LOGIC; + SIGNAL wire_n1iil0l_dataout : STD_LOGIC; + SIGNAL wire_n1iil0li_dataout : STD_LOGIC; + SIGNAL wire_n1iil0ll_dataout : STD_LOGIC; + SIGNAL wire_n1iil0lO_dataout : STD_LOGIC; + SIGNAL wire_n1iil0O_dataout : STD_LOGIC; + SIGNAL wire_n1iil0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iil0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iil10i_dataout : STD_LOGIC; + SIGNAL wire_n1iil10l_dataout : STD_LOGIC; + SIGNAL wire_n1iil10O_dataout : STD_LOGIC; + SIGNAL wire_n1iil11i_dataout : STD_LOGIC; + SIGNAL wire_n1iil11l_dataout : STD_LOGIC; + SIGNAL wire_n1iil11O_dataout : STD_LOGIC; + SIGNAL wire_n1iil1i_dataout : STD_LOGIC; + SIGNAL wire_n1iil1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iil1il_dataout : STD_LOGIC; + SIGNAL wire_n1iil1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iil1l_dataout : STD_LOGIC; + SIGNAL wire_n1iil1li_dataout : STD_LOGIC; + SIGNAL wire_n1iil1ll_dataout : STD_LOGIC; + SIGNAL wire_n1iil1lO_dataout : STD_LOGIC; + SIGNAL wire_n1iil1O_dataout : STD_LOGIC; + SIGNAL wire_n1iil1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iil1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iil1OO_dataout : STD_LOGIC; + SIGNAL wire_n1iilii_dataout : STD_LOGIC; + SIGNAL wire_n1iilil_dataout : STD_LOGIC; + SIGNAL wire_n1iiliO_dataout : STD_LOGIC; + SIGNAL wire_n1iilli_dataout : STD_LOGIC; + SIGNAL wire_n1iilll_dataout : STD_LOGIC; + SIGNAL wire_n1iillll_dataout : STD_LOGIC; + SIGNAL wire_n1iilllO_dataout : STD_LOGIC; + SIGNAL wire_n1iillO_dataout : STD_LOGIC; + SIGNAL wire_n1iillOi_dataout : STD_LOGIC; + SIGNAL wire_n1iillOl_dataout : STD_LOGIC; + SIGNAL wire_n1iillOO_dataout : STD_LOGIC; + SIGNAL wire_n1iilO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iilO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iilO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iilO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iilO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iilO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iilOi_dataout : STD_LOGIC; + SIGNAL wire_n1iilOii_dataout : STD_LOGIC; + SIGNAL wire_n1iilOil_dataout : STD_LOGIC; + SIGNAL wire_n1iilOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iilOl_dataout : STD_LOGIC; + SIGNAL wire_n1iilOli_dataout : STD_LOGIC; + SIGNAL wire_n1iilOll_dataout : STD_LOGIC; + SIGNAL wire_n1iilOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iilOO_dataout : STD_LOGIC; + SIGNAL wire_n1iilOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iilOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iilOOO_dataout : STD_LOGIC; + SIGNAL wire_n1iiO00i_dataout : STD_LOGIC; + SIGNAL wire_n1iiO00l_dataout : STD_LOGIC; + SIGNAL wire_n1iiO00O_dataout : STD_LOGIC; + SIGNAL wire_n1iiO01i_dataout : STD_LOGIC; + SIGNAL wire_n1iiO01l_dataout : STD_LOGIC; + SIGNAL wire_n1iiO01O_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0il_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0li_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iiO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1iiO10i_dataout : STD_LOGIC; + SIGNAL wire_n1iiO10l_dataout : STD_LOGIC; + SIGNAL wire_n1iiO10O_dataout : STD_LOGIC; + SIGNAL wire_n1iiO11i_dataout : STD_LOGIC; + SIGNAL wire_n1iiO11l_dataout : STD_LOGIC; + SIGNAL wire_n1iiO11O_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1il_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1li_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iiO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1iiOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1iiOii_dataout : STD_LOGIC; + SIGNAL wire_n1iiOiii_dataout : STD_LOGIC; + SIGNAL wire_n1iiOiil_dataout : STD_LOGIC; + SIGNAL wire_n1iiOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOil_dataout : STD_LOGIC; + SIGNAL wire_n1iiOili_dataout : STD_LOGIC; + SIGNAL wire_n1iiOill_dataout : STD_LOGIC; + SIGNAL wire_n1iiOilO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiOiOO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOl0i_dataout : STD_LOGIC; + SIGNAL wire_n1iiOl1i_dataout : STD_LOGIC; + SIGNAL wire_n1iiOl1l_dataout : STD_LOGIC; + SIGNAL wire_n1iiOl1O_dataout : STD_LOGIC; + SIGNAL wire_n1iiOli_dataout : STD_LOGIC; + SIGNAL wire_n1iiOll_dataout : STD_LOGIC; + SIGNAL wire_n1iiOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iiOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOii_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOil_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOli_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOll_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOO_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iiOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1il000i_dataout : STD_LOGIC; + SIGNAL wire_n1il000l_dataout : STD_LOGIC; + SIGNAL wire_n1il000O_dataout : STD_LOGIC; + SIGNAL wire_n1il001i_dataout : STD_LOGIC; + SIGNAL wire_n1il001l_dataout : STD_LOGIC; + SIGNAL wire_n1il001O_dataout : STD_LOGIC; + SIGNAL wire_n1il00i_dataout : STD_LOGIC; + SIGNAL wire_n1il00ii_dataout : STD_LOGIC; + SIGNAL wire_n1il00il_dataout : STD_LOGIC; + SIGNAL wire_n1il00iO_dataout : STD_LOGIC; + SIGNAL wire_n1il00l_dataout : STD_LOGIC; + SIGNAL wire_n1il00li_dataout : STD_LOGIC; + SIGNAL wire_n1il00ll_dataout : STD_LOGIC; + SIGNAL wire_n1il00lO_dataout : STD_LOGIC; + SIGNAL wire_n1il00O_dataout : STD_LOGIC; + SIGNAL wire_n1il00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1il00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1il00OO_dataout : STD_LOGIC; + SIGNAL wire_n1il010i_dataout : STD_LOGIC; + SIGNAL wire_n1il010l_dataout : STD_LOGIC; + SIGNAL wire_n1il010O_dataout : STD_LOGIC; + SIGNAL wire_n1il011i_dataout : STD_LOGIC; + SIGNAL wire_n1il011l_dataout : STD_LOGIC; + SIGNAL wire_n1il011O_dataout : STD_LOGIC; + SIGNAL wire_n1il01i_dataout : STD_LOGIC; + SIGNAL wire_n1il01ii_dataout : STD_LOGIC; + SIGNAL wire_n1il01il_dataout : STD_LOGIC; + SIGNAL wire_n1il01iO_dataout : STD_LOGIC; + SIGNAL wire_n1il01l_dataout : STD_LOGIC; + SIGNAL wire_n1il01li_dataout : STD_LOGIC; + SIGNAL wire_n1il01ll_dataout : STD_LOGIC; + SIGNAL wire_n1il01lO_dataout : STD_LOGIC; + SIGNAL wire_n1il01O_dataout : STD_LOGIC; + SIGNAL wire_n1il01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1il01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1il01OO_dataout : STD_LOGIC; + SIGNAL wire_n1il0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1il0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1il0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1il0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1il0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1il0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1il0ii_dataout : STD_LOGIC; + SIGNAL wire_n1il0iii_dataout : STD_LOGIC; + SIGNAL wire_n1il0iil_dataout : STD_LOGIC; + SIGNAL wire_n1il0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1il0il_dataout : STD_LOGIC; + SIGNAL wire_n1il0ili_dataout : STD_LOGIC; + SIGNAL wire_n1il0ill_dataout : STD_LOGIC; + SIGNAL wire_n1il0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1il0iO_dataout : STD_LOGIC; + SIGNAL wire_n1il0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1il0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1il0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1il0liO_dataout : STD_LOGIC; + SIGNAL wire_n1il0ll_dataout : STD_LOGIC; + SIGNAL wire_n1il0lli_dataout : STD_LOGIC; + SIGNAL wire_n1il0lll_dataout : STD_LOGIC; + SIGNAL wire_n1il0llO_dataout : STD_LOGIC; + SIGNAL wire_n1il0lO_dataout : STD_LOGIC; + SIGNAL wire_n1il0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1il0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1il0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1il0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1il0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1il0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1il0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1il0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1il0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1il0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1il0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1il0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1il0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1il0OO_dataout : STD_LOGIC; + SIGNAL wire_n1il0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1il0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1il0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1il10i_dataout : STD_LOGIC; + SIGNAL wire_n1il10l_dataout : STD_LOGIC; + SIGNAL wire_n1il10O_dataout : STD_LOGIC; + SIGNAL wire_n1il110i_dataout : STD_LOGIC; + SIGNAL wire_n1il110l_dataout : STD_LOGIC; + SIGNAL wire_n1il110O_dataout : STD_LOGIC; + SIGNAL wire_n1il111i_dataout : STD_LOGIC; + SIGNAL wire_n1il111l_dataout : STD_LOGIC; + SIGNAL wire_n1il111O_dataout : STD_LOGIC; + SIGNAL wire_n1il11i_dataout : STD_LOGIC; + SIGNAL wire_n1il11iO_dataout : STD_LOGIC; + SIGNAL wire_n1il11l_dataout : STD_LOGIC; + SIGNAL wire_n1il11O_dataout : STD_LOGIC; + SIGNAL wire_n1il1ii_dataout : STD_LOGIC; + SIGNAL wire_n1il1iii_dataout : STD_LOGIC; + SIGNAL wire_n1il1iil_dataout : STD_LOGIC; + SIGNAL wire_n1il1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1il1il_dataout : STD_LOGIC; + SIGNAL wire_n1il1ili_dataout : STD_LOGIC; + SIGNAL wire_n1il1ill_dataout : STD_LOGIC; + SIGNAL wire_n1il1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1il1iO_dataout : STD_LOGIC; + SIGNAL wire_n1il1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1il1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1il1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1il1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1il1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1il1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1il1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1il1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1il1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1il1li_dataout : STD_LOGIC; + SIGNAL wire_n1il1lii_dataout : STD_LOGIC; + SIGNAL wire_n1il1lil_dataout : STD_LOGIC; + SIGNAL wire_n1il1liO_dataout : STD_LOGIC; + SIGNAL wire_n1il1ll_dataout : STD_LOGIC; + SIGNAL wire_n1il1lli_dataout : STD_LOGIC; + SIGNAL wire_n1il1lll_dataout : STD_LOGIC; + SIGNAL wire_n1il1llO_dataout : STD_LOGIC; + SIGNAL wire_n1il1lO_dataout : STD_LOGIC; + SIGNAL wire_n1il1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1il1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1il1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1il1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1il1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1il1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1il1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1il1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1il1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1il1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1il1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1il1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1il1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1il1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1il1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1il1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1il1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1il1OO_dataout : STD_LOGIC; + SIGNAL wire_n1il1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1il1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1il1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1ili00i_dataout : STD_LOGIC; + SIGNAL wire_n1ili00l_dataout : STD_LOGIC; + SIGNAL wire_n1ili00O_dataout : STD_LOGIC; + SIGNAL wire_n1ili01i_dataout : STD_LOGIC; + SIGNAL wire_n1ili01l_dataout : STD_LOGIC; + SIGNAL wire_n1ili01O_dataout : STD_LOGIC; + SIGNAL wire_n1ili0i_dataout : STD_LOGIC; + SIGNAL wire_n1ili0ii_dataout : STD_LOGIC; + SIGNAL wire_n1ili0il_dataout : STD_LOGIC; + SIGNAL wire_n1ili0iO_dataout : STD_LOGIC; + SIGNAL wire_n1ili0l_dataout : STD_LOGIC; + SIGNAL wire_n1ili0li_dataout : STD_LOGIC; + SIGNAL wire_n1ili0ll_dataout : STD_LOGIC; + SIGNAL wire_n1ili0lO_dataout : STD_LOGIC; + SIGNAL wire_n1ili0O_dataout : STD_LOGIC; + SIGNAL wire_n1ili0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ili0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ili0OO_dataout : STD_LOGIC; + SIGNAL wire_n1ili10i_dataout : STD_LOGIC; + SIGNAL wire_n1ili10l_dataout : STD_LOGIC; + SIGNAL wire_n1ili10O_dataout : STD_LOGIC; + SIGNAL wire_n1ili11i_dataout : STD_LOGIC; + SIGNAL wire_n1ili11l_dataout : STD_LOGIC; + SIGNAL wire_n1ili11O_dataout : STD_LOGIC; + SIGNAL wire_n1ili1i_dataout : STD_LOGIC; + SIGNAL wire_n1ili1ii_dataout : STD_LOGIC; + SIGNAL wire_n1ili1il_dataout : STD_LOGIC; + SIGNAL wire_n1ili1iO_dataout : STD_LOGIC; + SIGNAL wire_n1ili1l_dataout : STD_LOGIC; + SIGNAL wire_n1ili1li_dataout : STD_LOGIC; + SIGNAL wire_n1ili1ll_dataout : STD_LOGIC; + SIGNAL wire_n1ili1lO_dataout : STD_LOGIC; + SIGNAL wire_n1ili1O_dataout : STD_LOGIC; + SIGNAL wire_n1ili1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ili1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ili1OO_dataout : STD_LOGIC; + SIGNAL wire_n1ilii0i_dataout : STD_LOGIC; + SIGNAL wire_n1ilii0l_dataout : STD_LOGIC; + SIGNAL wire_n1ilii0O_dataout : STD_LOGIC; + SIGNAL wire_n1ilii1i_dataout : STD_LOGIC; + SIGNAL wire_n1ilii1l_dataout : STD_LOGIC; + SIGNAL wire_n1ilii1O_dataout : STD_LOGIC; + SIGNAL wire_n1iliii_dataout : STD_LOGIC; + SIGNAL wire_n1iliiii_dataout : STD_LOGIC; + SIGNAL wire_n1iliiil_dataout : STD_LOGIC; + SIGNAL wire_n1iliiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iliil_dataout : STD_LOGIC; + SIGNAL wire_n1iliili_dataout : STD_LOGIC; + SIGNAL wire_n1iliill_dataout : STD_LOGIC; + SIGNAL wire_n1iliilO_dataout : STD_LOGIC; + SIGNAL wire_n1iliiO_dataout : STD_LOGIC; + SIGNAL wire_n1iliiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iliiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iliiOO_dataout : STD_LOGIC; + SIGNAL wire_n1ilil0i_dataout : STD_LOGIC; + SIGNAL wire_n1ilil0l_dataout : STD_LOGIC; + SIGNAL wire_n1ilil0O_dataout : STD_LOGIC; + SIGNAL wire_n1ilil1i_dataout : STD_LOGIC; + SIGNAL wire_n1ilil1l_dataout : STD_LOGIC; + SIGNAL wire_n1ilil1O_dataout : STD_LOGIC; + SIGNAL wire_n1ilili_dataout : STD_LOGIC; + SIGNAL wire_n1ililii_dataout : STD_LOGIC; + SIGNAL wire_n1ililil_dataout : STD_LOGIC; + SIGNAL wire_n1ililiO_dataout : STD_LOGIC; + SIGNAL wire_n1ilill_dataout : STD_LOGIC; + SIGNAL wire_n1ililli_dataout : STD_LOGIC; + SIGNAL wire_n1ililll_dataout : STD_LOGIC; + SIGNAL wire_n1ilillO_dataout : STD_LOGIC; + SIGNAL wire_n1ililO_dataout : STD_LOGIC; + SIGNAL wire_n1ililOi_dataout : STD_LOGIC; + SIGNAL wire_n1ililOl_dataout : STD_LOGIC; + SIGNAL wire_n1ililOO_dataout : STD_LOGIC; + SIGNAL wire_n1iliO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iliO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iliO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iliO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iliO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iliO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iliOi_dataout : STD_LOGIC; + SIGNAL wire_n1iliOii_dataout : STD_LOGIC; + SIGNAL wire_n1iliOil_dataout : STD_LOGIC; + SIGNAL wire_n1iliOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iliOl_dataout : STD_LOGIC; + SIGNAL wire_n1iliOli_dataout : STD_LOGIC; + SIGNAL wire_n1iliOll_dataout : STD_LOGIC; + SIGNAL wire_n1iliOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iliOO_dataout : STD_LOGIC; + SIGNAL wire_n1iliOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iliOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iliOOO_dataout : STD_LOGIC; + SIGNAL wire_n1ill00i_dataout : STD_LOGIC; + SIGNAL wire_n1ill00l_dataout : STD_LOGIC; + SIGNAL wire_n1ill00O_dataout : STD_LOGIC; + SIGNAL wire_n1ill01i_dataout : STD_LOGIC; + SIGNAL wire_n1ill01l_dataout : STD_LOGIC; + SIGNAL wire_n1ill01O_dataout : STD_LOGIC; + SIGNAL wire_n1ill0i_dataout : STD_LOGIC; + SIGNAL wire_n1ill0ii_dataout : STD_LOGIC; + SIGNAL wire_n1ill0il_dataout : STD_LOGIC; + SIGNAL wire_n1ill0iO_dataout : STD_LOGIC; + SIGNAL wire_n1ill0l_dataout : STD_LOGIC; + SIGNAL wire_n1ill0li_dataout : STD_LOGIC; + SIGNAL wire_n1ill0ll_dataout : STD_LOGIC; + SIGNAL wire_n1ill0lO_dataout : STD_LOGIC; + SIGNAL wire_n1ill0O_dataout : STD_LOGIC; + SIGNAL wire_n1ill0OO_dataout : STD_LOGIC; + SIGNAL wire_n1ill10i_dataout : STD_LOGIC; + SIGNAL wire_n1ill10l_dataout : STD_LOGIC; + SIGNAL wire_n1ill10O_dataout : STD_LOGIC; + SIGNAL wire_n1ill11i_dataout : STD_LOGIC; + SIGNAL wire_n1ill11l_dataout : STD_LOGIC; + SIGNAL wire_n1ill11O_dataout : STD_LOGIC; + SIGNAL wire_n1ill1i_dataout : STD_LOGIC; + SIGNAL wire_n1ill1ii_dataout : STD_LOGIC; + SIGNAL wire_n1ill1il_dataout : STD_LOGIC; + SIGNAL wire_n1ill1iO_dataout : STD_LOGIC; + SIGNAL wire_n1ill1l_dataout : STD_LOGIC; + SIGNAL wire_n1ill1li_dataout : STD_LOGIC; + SIGNAL wire_n1ill1ll_dataout : STD_LOGIC; + SIGNAL wire_n1ill1lO_dataout : STD_LOGIC; + SIGNAL wire_n1ill1O_dataout : STD_LOGIC; + SIGNAL wire_n1ill1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ill1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ill1OO_dataout : STD_LOGIC; + SIGNAL wire_n1illii_dataout : STD_LOGIC; + SIGNAL wire_n1illil_dataout : STD_LOGIC; + SIGNAL wire_n1illili_dataout : STD_LOGIC; + SIGNAL wire_n1illill_dataout : STD_LOGIC; + SIGNAL wire_n1illilO_dataout : STD_LOGIC; + SIGNAL wire_n1illiO_dataout : STD_LOGIC; + SIGNAL wire_n1illiOi_dataout : STD_LOGIC; + SIGNAL wire_n1illiOl_dataout : STD_LOGIC; + SIGNAL wire_n1illiOO_dataout : STD_LOGIC; + SIGNAL wire_n1illl1l_dataout : STD_LOGIC; + SIGNAL wire_n1illli_dataout : STD_LOGIC; + SIGNAL wire_n1illll_dataout : STD_LOGIC; + SIGNAL wire_n1illlO_dataout : STD_LOGIC; + SIGNAL wire_n1illOi_dataout : STD_LOGIC; + SIGNAL wire_n1illOl_dataout : STD_LOGIC; + SIGNAL wire_n1illOli_dataout : STD_LOGIC; + SIGNAL wire_n1illOll_dataout : STD_LOGIC; + SIGNAL wire_n1illOlO_dataout : STD_LOGIC; + SIGNAL wire_n1illOO_dataout : STD_LOGIC; + SIGNAL wire_n1illOOi_dataout : STD_LOGIC; + SIGNAL wire_n1illOOl_dataout : STD_LOGIC; + SIGNAL wire_n1illOOO_dataout : STD_LOGIC; + SIGNAL wire_n1ilO00i_dataout : STD_LOGIC; + SIGNAL wire_n1ilO00l_dataout : STD_LOGIC; + SIGNAL wire_n1ilO00O_dataout : STD_LOGIC; + SIGNAL wire_n1ilO01i_dataout : STD_LOGIC; + SIGNAL wire_n1ilO01l_dataout : STD_LOGIC; + SIGNAL wire_n1ilO01O_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0i_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0il_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0l_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0li_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0O_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ilO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1ilO10i_dataout : STD_LOGIC; + SIGNAL wire_n1ilO10l_dataout : STD_LOGIC; + SIGNAL wire_n1ilO10O_dataout : STD_LOGIC; + SIGNAL wire_n1ilO11i_dataout : STD_LOGIC; + SIGNAL wire_n1ilO11l_dataout : STD_LOGIC; + SIGNAL wire_n1ilO11O_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1i_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1il_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1l_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1li_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1O_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ilO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1ilOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1ilOii_dataout : STD_LOGIC; + SIGNAL wire_n1ilOiii_dataout : STD_LOGIC; + SIGNAL wire_n1ilOiil_dataout : STD_LOGIC; + SIGNAL wire_n1ilOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOil_dataout : STD_LOGIC; + SIGNAL wire_n1ilOili_dataout : STD_LOGIC; + SIGNAL wire_n1ilOill_dataout : STD_LOGIC; + SIGNAL wire_n1ilOilO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOiO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1ilOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1ilOiOO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl0i_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl0l_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl0O_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl1i_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl1l_dataout : STD_LOGIC; + SIGNAL wire_n1ilOl1O_dataout : STD_LOGIC; + SIGNAL wire_n1ilOli_dataout : STD_LOGIC; + SIGNAL wire_n1ilOlii_dataout : STD_LOGIC; + SIGNAL wire_n1ilOlil_dataout : STD_LOGIC; + SIGNAL wire_n1ilOliO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOll_dataout : STD_LOGIC; + SIGNAL wire_n1ilOlli_dataout : STD_LOGIC; + SIGNAL wire_n1ilOlll_dataout : STD_LOGIC; + SIGNAL wire_n1ilOllO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOlO_dataout : STD_LOGIC; + SIGNAL wire_n1ilOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1ilOOi_dataout : STD_LOGIC; + SIGNAL wire_n1ilOOl_dataout : STD_LOGIC; + SIGNAL wire_n1ilOOO_dataout : STD_LOGIC; + SIGNAL wire_n1iO000i_dataout : STD_LOGIC; + SIGNAL wire_n1iO000l_dataout : STD_LOGIC; + SIGNAL wire_n1iO000O_dataout : STD_LOGIC; + SIGNAL wire_n1iO001O_dataout : STD_LOGIC; + SIGNAL wire_n1iO00i_dataout : STD_LOGIC; + SIGNAL wire_n1iO00ii_dataout : STD_LOGIC; + SIGNAL wire_n1iO00il_dataout : STD_LOGIC; + SIGNAL wire_n1iO00iO_dataout : STD_LOGIC; + SIGNAL wire_n1iO00l_dataout : STD_LOGIC; + SIGNAL wire_n1iO00li_dataout : STD_LOGIC; + SIGNAL wire_n1iO00ll_dataout : STD_LOGIC; + SIGNAL wire_n1iO00lO_dataout : STD_LOGIC; + SIGNAL wire_n1iO00O_dataout : STD_LOGIC; + SIGNAL wire_n1iO00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iO00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iO00OO_dataout : STD_LOGIC; + SIGNAL wire_n1iO011i_dataout : STD_LOGIC; + SIGNAL wire_n1iO01l_dataout : STD_LOGIC; + SIGNAL wire_n1iO01li_dataout : STD_LOGIC; + SIGNAL wire_n1iO01ll_dataout : STD_LOGIC; + SIGNAL wire_n1iO01lO_dataout : STD_LOGIC; + SIGNAL wire_n1iO01O_dataout : STD_LOGIC; + SIGNAL wire_n1iO0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1iO0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1iO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1iO0il_dataout : STD_LOGIC; + SIGNAL wire_n1iO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0li_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lii_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lil_dataout : STD_LOGIC; + SIGNAL wire_n1iO0liO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lli_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lll_dataout : STD_LOGIC; + SIGNAL wire_n1iO0llO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1iO0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1iO0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iO0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1iO0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1iO0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iO0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1iO0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1iO0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1iO0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1iO0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1iO0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1iO100i_dataout : STD_LOGIC; + SIGNAL wire_n1iO100l_dataout : STD_LOGIC; + SIGNAL wire_n1iO100O_dataout : STD_LOGIC; + SIGNAL wire_n1iO101i_dataout : STD_LOGIC; + SIGNAL wire_n1iO101l_dataout : STD_LOGIC; + SIGNAL wire_n1iO101O_dataout : STD_LOGIC; + SIGNAL wire_n1iO10i_dataout : STD_LOGIC; + SIGNAL wire_n1iO10ii_dataout : STD_LOGIC; + SIGNAL wire_n1iO10il_dataout : STD_LOGIC; + SIGNAL wire_n1iO10iO_dataout : STD_LOGIC; + SIGNAL wire_n1iO10l_dataout : STD_LOGIC; + SIGNAL wire_n1iO10li_dataout : STD_LOGIC; + SIGNAL wire_n1iO10ll_dataout : STD_LOGIC; + SIGNAL wire_n1iO10lO_dataout : STD_LOGIC; + SIGNAL wire_n1iO10O_dataout : STD_LOGIC; + SIGNAL wire_n1iO10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iO10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iO10OO_dataout : STD_LOGIC; + SIGNAL wire_n1iO11i_dataout : STD_LOGIC; + SIGNAL wire_n1iO11l_dataout : STD_LOGIC; + SIGNAL wire_n1iO11li_dataout : STD_LOGIC; + SIGNAL wire_n1iO11ll_dataout : STD_LOGIC; + SIGNAL wire_n1iO11lO_dataout : STD_LOGIC; + SIGNAL wire_n1iO11O_dataout : STD_LOGIC; + SIGNAL wire_n1iO11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iO11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iO11OO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1iO1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1iO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iO1iii_dataout : STD_LOGIC; + SIGNAL wire_n1iO1iil_dataout : STD_LOGIC; + SIGNAL wire_n1iO1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1il_dataout : STD_LOGIC; + SIGNAL wire_n1iO1ili_dataout : STD_LOGIC; + SIGNAL wire_n1iO1ill_dataout : STD_LOGIC; + SIGNAL wire_n1iO1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1iO1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1iO1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1iO1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1iO1li_dataout : STD_LOGIC; + SIGNAL wire_n1iO1lii_dataout : STD_LOGIC; + SIGNAL wire_n1iO1lil_dataout : STD_LOGIC; + SIGNAL wire_n1iO1liO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1iO1lli_dataout : STD_LOGIC; + SIGNAL wire_n1iO1lll_dataout : STD_LOGIC; + SIGNAL wire_n1iO1llO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iO1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iO1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1iO1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1iO1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1iO1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1iO1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1iO1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi00i_dataout : STD_LOGIC; + SIGNAL wire_n1iOi00l_dataout : STD_LOGIC; + SIGNAL wire_n1iOi00O_dataout : STD_LOGIC; + SIGNAL wire_n1iOi01i_dataout : STD_LOGIC; + SIGNAL wire_n1iOi01l_dataout : STD_LOGIC; + SIGNAL wire_n1iOi01O_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0ii_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0il_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0iO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0li_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0ll_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0lO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iOi0OO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi10i_dataout : STD_LOGIC; + SIGNAL wire_n1iOi10l_dataout : STD_LOGIC; + SIGNAL wire_n1iOi10O_dataout : STD_LOGIC; + SIGNAL wire_n1iOi11i_dataout : STD_LOGIC; + SIGNAL wire_n1iOi11l_dataout : STD_LOGIC; + SIGNAL wire_n1iOi11O_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1il_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1li_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1ll_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1lO_dataout : STD_LOGIC; + SIGNAL wire_n1iOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOii0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOii0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOii0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOii1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOii1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOii1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOiii_dataout : STD_LOGIC; + SIGNAL wire_n1iOiiii_dataout : STD_LOGIC; + SIGNAL wire_n1iOiiil_dataout : STD_LOGIC; + SIGNAL wire_n1iOiiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOiil_dataout : STD_LOGIC; + SIGNAL wire_n1iOiili_dataout : STD_LOGIC; + SIGNAL wire_n1iOiill_dataout : STD_LOGIC; + SIGNAL wire_n1iOiilO_dataout : STD_LOGIC; + SIGNAL wire_n1iOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOiiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOiiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOiiOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOil0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOil0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOil0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOil1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOil1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOil1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOili_dataout : STD_LOGIC; + SIGNAL wire_n1iOilii_dataout : STD_LOGIC; + SIGNAL wire_n1iOilil_dataout : STD_LOGIC; + SIGNAL wire_n1iOiliO_dataout : STD_LOGIC; + SIGNAL wire_n1iOill_dataout : STD_LOGIC; + SIGNAL wire_n1iOilli_dataout : STD_LOGIC; + SIGNAL wire_n1iOilll_dataout : STD_LOGIC; + SIGNAL wire_n1iOilO_dataout : STD_LOGIC; + SIGNAL wire_n1iOilOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOilOO_w_lg_dataout20251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1iOiO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOiO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOiO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOiO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOiO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOiO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOiOii_dataout : STD_LOGIC; + SIGNAL wire_n1iOiOil_dataout : STD_LOGIC; + SIGNAL wire_n1iOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOiOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOl0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOl0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOl0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOl0OO_dataout : STD_LOGIC; + SIGNAL wire_n1iOl1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOl1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOl1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOli0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOli0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOli0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOli1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOli1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOli1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOlii_dataout : STD_LOGIC; + SIGNAL wire_n1iOliii_dataout : STD_LOGIC; + SIGNAL wire_n1iOliil_dataout : STD_LOGIC; + SIGNAL wire_n1iOliiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOlil_dataout : STD_LOGIC; + SIGNAL wire_n1iOlili_dataout : STD_LOGIC; + SIGNAL wire_n1iOlill_dataout : STD_LOGIC; + SIGNAL wire_n1iOlilO_dataout : STD_LOGIC; + SIGNAL wire_n1iOliO_dataout : STD_LOGIC; + SIGNAL wire_n1iOliOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOliOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOliOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOll0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOll0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOll0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOll1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOll1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOll1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOlli_dataout : STD_LOGIC; + SIGNAL wire_n1iOllii_dataout : STD_LOGIC; + SIGNAL wire_n1iOllil_dataout : STD_LOGIC; + SIGNAL wire_n1iOlliO_dataout : STD_LOGIC; + SIGNAL wire_n1iOlll_dataout : STD_LOGIC; + SIGNAL wire_n1iOllli_dataout : STD_LOGIC; + SIGNAL wire_n1iOllll_dataout : STD_LOGIC; + SIGNAL wire_n1iOlllO_dataout : STD_LOGIC; + SIGNAL wire_n1iOllO_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOlO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOii_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOil_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOli_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOll_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOlOOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOO00i_dataout : STD_LOGIC; + SIGNAL wire_n1iOO00l_dataout : STD_LOGIC; + SIGNAL wire_n1iOO00O_dataout : STD_LOGIC; + SIGNAL wire_n1iOO01i_dataout : STD_LOGIC; + SIGNAL wire_n1iOO01l_dataout : STD_LOGIC; + SIGNAL wire_n1iOO01O_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0il_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0li_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iOO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1iOO10i_dataout : STD_LOGIC; + SIGNAL wire_n1iOO10l_dataout : STD_LOGIC; + SIGNAL wire_n1iOO10O_dataout : STD_LOGIC; + SIGNAL wire_n1iOO11i_dataout : STD_LOGIC; + SIGNAL wire_n1iOO11l_dataout : STD_LOGIC; + SIGNAL wire_n1iOO11O_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1il_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1iOO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOOii_dataout : STD_LOGIC; + SIGNAL wire_n1iOOiii_dataout : STD_LOGIC; + SIGNAL wire_n1iOOiil_dataout : STD_LOGIC; + SIGNAL wire_n1iOOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOil_dataout : STD_LOGIC; + SIGNAL wire_n1iOOili_dataout : STD_LOGIC; + SIGNAL wire_n1iOOill_dataout : STD_LOGIC; + SIGNAL wire_n1iOOilO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOOiOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOOl1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOOli_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlii_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlil_dataout : STD_LOGIC; + SIGNAL wire_n1iOOliO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOll_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlli_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlll_dataout : STD_LOGIC; + SIGNAL wire_n1iOOllO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO0i_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO0O_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1iOOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOii_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOli_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOll_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1iOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1l00i0l_dataout : STD_LOGIC; + SIGNAL wire_n1l00i0O_dataout : STD_LOGIC; + SIGNAL wire_n1l00iii_dataout : STD_LOGIC; + SIGNAL wire_n1l00iil_dataout : STD_LOGIC; + SIGNAL wire_n1l00iiO_dataout : STD_LOGIC; + SIGNAL wire_n1l00ili_dataout : STD_LOGIC; + SIGNAL wire_n1l00ill_dataout : STD_LOGIC; + SIGNAL wire_n1l00ilO_dataout : STD_LOGIC; + SIGNAL wire_n1l00iO_dataout : STD_LOGIC; + SIGNAL wire_n1l00iOi_dataout : STD_LOGIC; + SIGNAL wire_n1l00iOl_dataout : STD_LOGIC; + SIGNAL wire_n1l00iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l00l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l00l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l00l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l00l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l00l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l00l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l00li_dataout : STD_LOGIC; + SIGNAL wire_n1l00lii_dataout : STD_LOGIC; + SIGNAL wire_n1l00lil_dataout : STD_LOGIC; + SIGNAL wire_n1l00liO_dataout : STD_LOGIC; + SIGNAL wire_n1l00ll_dataout : STD_LOGIC; + SIGNAL wire_n1l00lli_dataout : STD_LOGIC; + SIGNAL wire_n1l00lll_dataout : STD_LOGIC; + SIGNAL wire_n1l00llO_dataout : STD_LOGIC; + SIGNAL wire_n1l00lO_dataout : STD_LOGIC; + SIGNAL wire_n1l00lOi_dataout : STD_LOGIC; + SIGNAL wire_n1l00lOl_dataout : STD_LOGIC; + SIGNAL wire_n1l00lOO_dataout : STD_LOGIC; + SIGNAL wire_n1l00O0i_dataout : STD_LOGIC; + SIGNAL wire_n1l00O0l_dataout : STD_LOGIC; + SIGNAL wire_n1l00O0O_dataout : STD_LOGIC; + SIGNAL wire_n1l00O1i_dataout : STD_LOGIC; + SIGNAL wire_n1l00O1l_dataout : STD_LOGIC; + SIGNAL wire_n1l00O1O_dataout : STD_LOGIC; + SIGNAL wire_n1l00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l00Oii_dataout : STD_LOGIC; + SIGNAL wire_n1l00Oil_dataout : STD_LOGIC; + SIGNAL wire_n1l00OiO_dataout : STD_LOGIC; + SIGNAL wire_n1l00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l00Oli_dataout : STD_LOGIC; + SIGNAL wire_n1l00Oll_dataout : STD_LOGIC; + SIGNAL wire_n1l00OlO_dataout : STD_LOGIC; + SIGNAL wire_n1l00OO_dataout : STD_LOGIC; + SIGNAL wire_n1l00OOi_dataout : STD_LOGIC; + SIGNAL wire_n1l00OOl_dataout : STD_LOGIC; + SIGNAL wire_n1l00OOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0100i_dataout : STD_LOGIC; + SIGNAL wire_n1l0100l_dataout : STD_LOGIC; + SIGNAL wire_n1l0101i_dataout : STD_LOGIC; + SIGNAL wire_n1l0101l_dataout : STD_LOGIC; + SIGNAL wire_n1l0101O_dataout : STD_LOGIC; + SIGNAL wire_n1l010il_dataout : STD_LOGIC; + SIGNAL wire_n1l010iO_dataout : STD_LOGIC; + SIGNAL wire_n1l010li_dataout : STD_LOGIC; + SIGNAL wire_n1l010ll_dataout : STD_LOGIC; + SIGNAL wire_n1l010lO_dataout : STD_LOGIC; + SIGNAL wire_n1l010Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0110i_dataout : STD_LOGIC; + SIGNAL wire_n1l0110l_dataout : STD_LOGIC; + SIGNAL wire_n1l0110O_dataout : STD_LOGIC; + SIGNAL wire_n1l0111i_dataout : STD_LOGIC; + SIGNAL wire_n1l0111l_dataout : STD_LOGIC; + SIGNAL wire_n1l0111O_dataout : STD_LOGIC; + SIGNAL wire_n1l011ii_dataout : STD_LOGIC; + SIGNAL wire_n1l011il_dataout : STD_LOGIC; + SIGNAL wire_n1l011iO_dataout : STD_LOGIC; + SIGNAL wire_n1l011li_dataout : STD_LOGIC; + SIGNAL wire_n1l011ll_dataout : STD_LOGIC; + SIGNAL wire_n1l011lO_dataout : STD_LOGIC; + SIGNAL wire_n1l011Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l011Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l011OO_dataout : STD_LOGIC; + SIGNAL wire_n1l01i0l_dataout : STD_LOGIC; + SIGNAL wire_n1l01i0O_dataout : STD_LOGIC; + SIGNAL wire_n1l01ili_dataout : STD_LOGIC; + SIGNAL wire_n1l01ill_dataout : STD_LOGIC; + SIGNAL wire_n1l01ilO_dataout : STD_LOGIC; + SIGNAL wire_n1l01iOi_dataout : STD_LOGIC; + SIGNAL wire_n1l01iOl_dataout : STD_LOGIC; + SIGNAL wire_n1l01iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l01l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l01l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l01l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l01l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l01lii_dataout : STD_LOGIC; + SIGNAL wire_n1l01lil_dataout : STD_LOGIC; + SIGNAL wire_n1l01liO_dataout : STD_LOGIC; + SIGNAL wire_n1l01lli_dataout : STD_LOGIC; + SIGNAL wire_n1l01lll_dataout : STD_LOGIC; + SIGNAL wire_n1l01llO_dataout : STD_LOGIC; + SIGNAL wire_n1l01lOi_dataout : STD_LOGIC; + SIGNAL wire_n1l01lOl_dataout : STD_LOGIC; + SIGNAL wire_n1l01lOO_dataout : STD_LOGIC; + SIGNAL wire_n1l01O0i_dataout : STD_LOGIC; + SIGNAL wire_n1l01O0l_dataout : STD_LOGIC; + SIGNAL wire_n1l01O0O_dataout : STD_LOGIC; + SIGNAL wire_n1l01O1l_dataout : STD_LOGIC; + SIGNAL wire_n1l01O1O_dataout : STD_LOGIC; + SIGNAL wire_n1l01Oii_dataout : STD_LOGIC; + SIGNAL wire_n1l01Oil_dataout : STD_LOGIC; + SIGNAL wire_n1l01OiO_dataout : STD_LOGIC; + SIGNAL wire_n1l01Oli_dataout : STD_LOGIC; + SIGNAL wire_n1l01Oll_dataout : STD_LOGIC; + SIGNAL wire_n1l01OlO_dataout : STD_LOGIC; + SIGNAL wire_n1l0i01i_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0lO_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0i0OO_dataout : STD_LOGIC; + SIGNAL wire_n1l0i10i_dataout : STD_LOGIC; + SIGNAL wire_n1l0i10l_dataout : STD_LOGIC; + SIGNAL wire_n1l0i10O_dataout : STD_LOGIC; + SIGNAL wire_n1l0i11i_dataout : STD_LOGIC; + SIGNAL wire_n1l0i11l_dataout : STD_LOGIC; + SIGNAL wire_n1l0i11O_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1il_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1li_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1ll_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0i1OO_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0ii1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0iii_dataout : STD_LOGIC; + SIGNAL wire_n1l0iiii_dataout : STD_LOGIC; + SIGNAL wire_n1l0iiil_dataout : STD_LOGIC; + SIGNAL wire_n1l0iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0iil_dataout : STD_LOGIC; + SIGNAL wire_n1l0iili_dataout : STD_LOGIC; + SIGNAL wire_n1l0iill_dataout : STD_LOGIC; + SIGNAL wire_n1l0iilO_dataout : STD_LOGIC; + SIGNAL wire_n1l0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0il0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0il0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0il0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0il1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0il1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0il1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0ili_dataout : STD_LOGIC; + SIGNAL wire_n1l0ilii_dataout : STD_LOGIC; + SIGNAL wire_n1l0ilil_dataout : STD_LOGIC; + SIGNAL wire_n1l0iliO_dataout : STD_LOGIC; + SIGNAL wire_n1l0ill_dataout : STD_LOGIC; + SIGNAL wire_n1l0illi_dataout : STD_LOGIC; + SIGNAL wire_n1l0illl_dataout : STD_LOGIC; + SIGNAL wire_n1l0illO_dataout : STD_LOGIC; + SIGNAL wire_n1l0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1l0ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOii_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOil_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOli_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOll_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0l00i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l00l_dataout : STD_LOGIC; + SIGNAL wire_n1l0l00O_dataout : STD_LOGIC; + SIGNAL wire_n1l0l01i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l01l_dataout : STD_LOGIC; + SIGNAL wire_n1l0l01O_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0ii_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0il_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0iO_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0li_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0lO_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0l0OO_dataout : STD_LOGIC; + SIGNAL wire_n1l0l10i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l10l_dataout : STD_LOGIC; + SIGNAL wire_n1l0l10O_dataout : STD_LOGIC; + SIGNAL wire_n1l0l11i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l11l_dataout : STD_LOGIC; + SIGNAL wire_n1l0l11O_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1il_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1li_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1ll_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0l1OO_dataout : STD_LOGIC; + SIGNAL wire_n1l0li0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0li0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0li0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0li1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0li1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0li1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0lii_dataout : STD_LOGIC; + SIGNAL wire_n1l0liii_dataout : STD_LOGIC; + SIGNAL wire_n1l0liil_dataout : STD_LOGIC; + SIGNAL wire_n1l0liiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0lil_dataout : STD_LOGIC; + SIGNAL wire_n1l0lili_dataout : STD_LOGIC; + SIGNAL wire_n1l0lill_dataout : STD_LOGIC; + SIGNAL wire_n1l0lilO_dataout : STD_LOGIC; + SIGNAL wire_n1l0liO_dataout : STD_LOGIC; + SIGNAL wire_n1l0liOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0liOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0liOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0ll1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0lli_dataout : STD_LOGIC; + SIGNAL wire_n1l0llii_dataout : STD_LOGIC; + SIGNAL wire_n1l0llil_dataout : STD_LOGIC; + SIGNAL wire_n1l0lliO_dataout : STD_LOGIC; + SIGNAL wire_n1l0lll_dataout : STD_LOGIC; + SIGNAL wire_n1l0llli_dataout : STD_LOGIC; + SIGNAL wire_n1l0llll_dataout : STD_LOGIC; + SIGNAL wire_n1l0lllO_dataout : STD_LOGIC; + SIGNAL wire_n1l0llO_dataout : STD_LOGIC; + SIGNAL wire_n1l0llOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0llOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0llOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0lO0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0lO0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0lO0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0lO1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0lO1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0lO1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOii_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOil_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOli_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOll_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOlO_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0lOOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0O00i_dataout : STD_LOGIC; + SIGNAL wire_n1l0O00l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O00O_dataout : STD_LOGIC; + SIGNAL wire_n1l0O01i_dataout : STD_LOGIC; + SIGNAL wire_n1l0O01l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O01O_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0ii_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0il_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0iO_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0li_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0lO_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0O0OO_dataout : STD_LOGIC; + SIGNAL wire_n1l0O10i_dataout : STD_LOGIC; + SIGNAL wire_n1l0O10l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O10O_dataout : STD_LOGIC; + SIGNAL wire_n1l0O11i_dataout : STD_LOGIC; + SIGNAL wire_n1l0O11l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O11O_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1ii_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1il_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1li_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1ll_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l0O1OO_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oiii_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oiil_dataout : STD_LOGIC; + SIGNAL wire_n1l0OiiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oili_dataout : STD_LOGIC; + SIGNAL wire_n1l0Oill_dataout : STD_LOGIC; + SIGNAL wire_n1l0OilO_dataout : STD_LOGIC; + SIGNAL wire_n1l0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0OiOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0Olii_dataout : STD_LOGIC; + SIGNAL wire_n1l0Olil_dataout : STD_LOGIC; + SIGNAL wire_n1l0OliO_dataout : STD_LOGIC; + SIGNAL wire_n1l0Olli_dataout : STD_LOGIC; + SIGNAL wire_n1l0Olll_dataout : STD_LOGIC; + SIGNAL wire_n1l0OllO_dataout : STD_LOGIC; + SIGNAL wire_n1l0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1l0OlOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0OlOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0OlOO_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO0i_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO0l_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO0O_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO1i_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO1l_dataout : STD_LOGIC; + SIGNAL wire_n1l0OO1O_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOii_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOil_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOiO_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOli_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOll_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOlO_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOOi_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOOl_dataout : STD_LOGIC; + SIGNAL wire_n1l0OOOO_dataout : STD_LOGIC; + SIGNAL wire_n1l100i_dataout : STD_LOGIC; + SIGNAL wire_n1l100l_dataout : STD_LOGIC; + SIGNAL wire_n1l100O_dataout : STD_LOGIC; + SIGNAL wire_n1l1010i_dataout : STD_LOGIC; + SIGNAL wire_n1l1010l_dataout : STD_LOGIC; + SIGNAL wire_n1l1010O_dataout : STD_LOGIC; + SIGNAL wire_n1l1011i_dataout : STD_LOGIC; + SIGNAL wire_n1l1011l_dataout : STD_LOGIC; + SIGNAL wire_n1l1011O_dataout : STD_LOGIC; + SIGNAL wire_n1l101i_dataout : STD_LOGIC; + SIGNAL wire_n1l101ii_dataout : STD_LOGIC; + SIGNAL wire_n1l101l_dataout : STD_LOGIC; + SIGNAL wire_n1l101O_dataout : STD_LOGIC; + SIGNAL wire_n1l10ii_dataout : STD_LOGIC; + SIGNAL wire_n1l10il_dataout : STD_LOGIC; + SIGNAL wire_n1l10ili_dataout : STD_LOGIC; + SIGNAL wire_n1l10ill_dataout : STD_LOGIC; + SIGNAL wire_n1l10ilO_dataout : STD_LOGIC; + SIGNAL wire_n1l10iO_dataout : STD_LOGIC; + SIGNAL wire_n1l10l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l10l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l10l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l10l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l10li_dataout : STD_LOGIC; + SIGNAL wire_n1l10ll_dataout : STD_LOGIC; + SIGNAL wire_n1l10lli_dataout : STD_LOGIC; + SIGNAL wire_n1l10lli_w_lg_dataout21212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l10lO_dataout : STD_LOGIC; + SIGNAL wire_n1l10lOl_dataout : STD_LOGIC; + SIGNAL wire_n1l10lOO_dataout : STD_LOGIC; + SIGNAL wire_n1l10O0i_dataout : STD_LOGIC; + SIGNAL wire_n1l10O0l_dataout : STD_LOGIC; + SIGNAL wire_n1l10O0O_dataout : STD_LOGIC; + SIGNAL wire_n1l10O1i_dataout : STD_LOGIC; + SIGNAL wire_n1l10O1l_dataout : STD_LOGIC; + SIGNAL wire_n1l10O1O_dataout : STD_LOGIC; + SIGNAL wire_n1l10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l10Oii_dataout : STD_LOGIC; + SIGNAL wire_n1l10Oil_dataout : STD_LOGIC; + SIGNAL wire_n1l10OiO_dataout : STD_LOGIC; + SIGNAL wire_n1l10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l10Oli_dataout : STD_LOGIC; + SIGNAL wire_n1l10Oll_dataout : STD_LOGIC; + SIGNAL wire_n1l10OlO_dataout : STD_LOGIC; + SIGNAL wire_n1l10OO_dataout : STD_LOGIC; + SIGNAL wire_n1l10OOi_dataout : STD_LOGIC; + SIGNAL wire_n1l10OOl_dataout : STD_LOGIC; + SIGNAL wire_n1l10OOO_dataout : STD_LOGIC; + SIGNAL wire_n1l110i_dataout : STD_LOGIC; + SIGNAL wire_n1l110l_dataout : STD_LOGIC; + SIGNAL wire_n1l110li_dataout : STD_LOGIC; + SIGNAL wire_n1l110ll_dataout : STD_LOGIC; + SIGNAL wire_n1l110lO_dataout : STD_LOGIC; + SIGNAL wire_n1l110O_dataout : STD_LOGIC; + SIGNAL wire_n1l110Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l110Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l110OO_dataout : STD_LOGIC; + SIGNAL wire_n1l1110i_dataout : STD_LOGIC; + SIGNAL wire_n1l1110l_dataout : STD_LOGIC; + SIGNAL wire_n1l1110O_dataout : STD_LOGIC; + SIGNAL wire_n1l1111i_dataout : STD_LOGIC; + SIGNAL wire_n1l1111l_dataout : STD_LOGIC; + SIGNAL wire_n1l1111O_dataout : STD_LOGIC; + SIGNAL wire_n1l111i_dataout : STD_LOGIC; + SIGNAL wire_n1l111ii_dataout : STD_LOGIC; + SIGNAL wire_n1l111il_dataout : STD_LOGIC; + SIGNAL wire_n1l111iO_dataout : STD_LOGIC; + SIGNAL wire_n1l111l_dataout : STD_LOGIC; + SIGNAL wire_n1l111li_dataout : STD_LOGIC; + SIGNAL wire_n1l111ll_dataout : STD_LOGIC; + SIGNAL wire_n1l111lO_dataout : STD_LOGIC; + SIGNAL wire_n1l111O_dataout : STD_LOGIC; + SIGNAL wire_n1l11i0i_dataout : STD_LOGIC; + SIGNAL wire_n1l11i0l_dataout : STD_LOGIC; + SIGNAL wire_n1l11i0O_dataout : STD_LOGIC; + SIGNAL wire_n1l11i1i_dataout : STD_LOGIC; + SIGNAL wire_n1l11i1l_dataout : STD_LOGIC; + SIGNAL wire_n1l11i1O_dataout : STD_LOGIC; + SIGNAL wire_n1l11ii_dataout : STD_LOGIC; + SIGNAL wire_n1l11il_dataout : STD_LOGIC; + SIGNAL wire_n1l11iO_dataout : STD_LOGIC; + SIGNAL wire_n1l11iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l11iOO_w_lg_w_lg_dataout25218w25219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l11iOO_w_lg_dataout25218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l11l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l11l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l11l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l11l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l11l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l11l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l11li_dataout : STD_LOGIC; + SIGNAL wire_n1l11lii_dataout : STD_LOGIC; + SIGNAL wire_n1l11lil_dataout : STD_LOGIC; + SIGNAL wire_n1l11liO_dataout : STD_LOGIC; + SIGNAL wire_n1l11ll_dataout : STD_LOGIC; + SIGNAL wire_n1l11lli_dataout : STD_LOGIC; + SIGNAL wire_n1l11lll_dataout : STD_LOGIC; + SIGNAL wire_n1l11llO_dataout : STD_LOGIC; + SIGNAL wire_n1l11lO_dataout : STD_LOGIC; + SIGNAL wire_n1l11lOi_dataout : STD_LOGIC; + SIGNAL wire_n1l11lOl_dataout : STD_LOGIC; + SIGNAL wire_n1l11lOO_dataout : STD_LOGIC; + SIGNAL wire_n1l11O0i_dataout : STD_LOGIC; + SIGNAL wire_n1l11O0l_dataout : STD_LOGIC; + SIGNAL wire_n1l11O0O_dataout : STD_LOGIC; + SIGNAL wire_n1l11O1i_dataout : STD_LOGIC; + SIGNAL wire_n1l11O1l_dataout : STD_LOGIC; + SIGNAL wire_n1l11O1O_dataout : STD_LOGIC; + SIGNAL wire_n1l11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l11Oii_dataout : STD_LOGIC; + SIGNAL wire_n1l11Oil_dataout : STD_LOGIC; + SIGNAL wire_n1l11OiO_dataout : STD_LOGIC; + SIGNAL wire_n1l11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l11Oli_dataout : STD_LOGIC; + SIGNAL wire_n1l11Oll_dataout : STD_LOGIC; + SIGNAL wire_n1l11OlO_dataout : STD_LOGIC; + SIGNAL wire_n1l11OO_dataout : STD_LOGIC; + SIGNAL wire_n1l11OOi_dataout : STD_LOGIC; + SIGNAL wire_n1l11OOl_dataout : STD_LOGIC; + SIGNAL wire_n1l11OOO_dataout : STD_LOGIC; + SIGNAL wire_n1l1i00i_dataout : STD_LOGIC; + SIGNAL wire_n1l1i00l_dataout : STD_LOGIC; + SIGNAL wire_n1l1i00O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i01i_dataout : STD_LOGIC; + SIGNAL wire_n1l1i01l_dataout : STD_LOGIC; + SIGNAL wire_n1l1i01O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0ii_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0il_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0iO_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0li_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0lO_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l1i0OO_dataout : STD_LOGIC; + SIGNAL wire_n1l1i10i_dataout : STD_LOGIC; + SIGNAL wire_n1l1i10l_dataout : STD_LOGIC; + SIGNAL wire_n1l1i10O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i11i_dataout : STD_LOGIC; + SIGNAL wire_n1l1i11l_dataout : STD_LOGIC; + SIGNAL wire_n1l1i11O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1il_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1li_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1ll_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l1i1OO_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii0i_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1ii1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1iii_dataout : STD_LOGIC; + SIGNAL wire_n1l1iiii_dataout : STD_LOGIC; + SIGNAL wire_n1l1iiil_dataout : STD_LOGIC; + SIGNAL wire_n1l1iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1l1iil_dataout : STD_LOGIC; + SIGNAL wire_n1l1iili_dataout : STD_LOGIC; + SIGNAL wire_n1l1iill_dataout : STD_LOGIC; + SIGNAL wire_n1l1iilO_dataout : STD_LOGIC; + SIGNAL wire_n1l1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1l1iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1l1iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1l1iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1l1il0i_dataout : STD_LOGIC; + SIGNAL wire_n1l1il0l_dataout : STD_LOGIC; + SIGNAL wire_n1l1il0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1il1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1il1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1il1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1ili_dataout : STD_LOGIC; + SIGNAL wire_n1l1ilii_dataout : STD_LOGIC; + SIGNAL wire_n1l1ilil_dataout : STD_LOGIC; + SIGNAL wire_n1l1iliO_dataout : STD_LOGIC; + SIGNAL wire_n1l1ill_dataout : STD_LOGIC; + SIGNAL wire_n1l1illi_dataout : STD_LOGIC; + SIGNAL wire_n1l1illl_dataout : STD_LOGIC; + SIGNAL wire_n1l1illO_dataout : STD_LOGIC; + SIGNAL wire_n1l1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1l1ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1l1ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1l1ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO0i_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO0l_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOii_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOil_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOli_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOll_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1l1iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1l1l00i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l00l_dataout : STD_LOGIC; + SIGNAL wire_n1l1l00O_dataout : STD_LOGIC; + SIGNAL wire_n1l1l01i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l01l_dataout : STD_LOGIC; + SIGNAL wire_n1l1l01O_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0il_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0li_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1l10i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l10l_dataout : STD_LOGIC; + SIGNAL wire_n1l1l10O_dataout : STD_LOGIC; + SIGNAL wire_n1l1l11i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l11l_dataout : STD_LOGIC; + SIGNAL wire_n1l1l11O_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1il_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1iO_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1li_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1ll_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l1l1OO_dataout : STD_LOGIC; + SIGNAL wire_n1l1lii_dataout : STD_LOGIC; + SIGNAL wire_n1l1lil_dataout : STD_LOGIC; + SIGNAL wire_n1l1liO_dataout : STD_LOGIC; + SIGNAL wire_n1l1lli_dataout : STD_LOGIC; + SIGNAL wire_n1l1lll_dataout : STD_LOGIC; + SIGNAL wire_n1l1llO_dataout : STD_LOGIC; + SIGNAL wire_n1l1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1l1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1l1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1l1O00i_dataout : STD_LOGIC; + SIGNAL wire_n1l1O00l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O00O_dataout : STD_LOGIC; + SIGNAL wire_n1l1O01i_dataout : STD_LOGIC; + SIGNAL wire_n1l1O01l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O01O_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0ii_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0il_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0iO_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0li_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0ll_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0lO_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1l1O0OO_dataout : STD_LOGIC; + SIGNAL wire_n1l1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oiii_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oiil_dataout : STD_LOGIC; + SIGNAL wire_n1l1OiiO_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oili_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oill_dataout : STD_LOGIC; + SIGNAL wire_n1l1OilO_dataout : STD_LOGIC; + SIGNAL wire_n1l1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1l1OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1l1OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1l1OiOO_dataout : STD_LOGIC; + SIGNAL wire_n1l1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n1l1Ol0O_w_lg_dataout18957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1Ol0O_w_lg_dataout18951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n1l1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1l1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1l1Olii_dataout : STD_LOGIC; + SIGNAL wire_n1l1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1l1OOOO_dataout : STD_LOGIC; + SIGNAL wire_n1li000i_dataout : STD_LOGIC; + SIGNAL wire_n1li000l_dataout : STD_LOGIC; + SIGNAL wire_n1li000O_dataout : STD_LOGIC; + SIGNAL wire_n1li001i_dataout : STD_LOGIC; + SIGNAL wire_n1li001l_dataout : STD_LOGIC; + SIGNAL wire_n1li001O_dataout : STD_LOGIC; + SIGNAL wire_n1li00i_dataout : STD_LOGIC; + SIGNAL wire_n1li00ii_dataout : STD_LOGIC; + SIGNAL wire_n1li00l_dataout : STD_LOGIC; + SIGNAL wire_n1li00lO_dataout : STD_LOGIC; + SIGNAL wire_n1li00O_dataout : STD_LOGIC; + SIGNAL wire_n1li00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1li00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1li00OO_dataout : STD_LOGIC; + SIGNAL wire_n1li010i_dataout : STD_LOGIC; + SIGNAL wire_n1li010l_dataout : STD_LOGIC; + SIGNAL wire_n1li010O_dataout : STD_LOGIC; + SIGNAL wire_n1li011i_dataout : STD_LOGIC; + SIGNAL wire_n1li011l_dataout : STD_LOGIC; + SIGNAL wire_n1li011O_dataout : STD_LOGIC; + SIGNAL wire_n1li01i_dataout : STD_LOGIC; + SIGNAL wire_n1li01ii_dataout : STD_LOGIC; + SIGNAL wire_n1li01il_dataout : STD_LOGIC; + SIGNAL wire_n1li01iO_dataout : STD_LOGIC; + SIGNAL wire_n1li01l_dataout : STD_LOGIC; + SIGNAL wire_n1li01li_dataout : STD_LOGIC; + SIGNAL wire_n1li01ll_dataout : STD_LOGIC; + SIGNAL wire_n1li01lO_dataout : STD_LOGIC; + SIGNAL wire_n1li01O_dataout : STD_LOGIC; + SIGNAL wire_n1li01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1li01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1li01OO_dataout : STD_LOGIC; + SIGNAL wire_n1li0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1li0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1li0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1li0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1li0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1li0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1li0ii_dataout : STD_LOGIC; + SIGNAL wire_n1li0iii_dataout : STD_LOGIC; + SIGNAL wire_n1li0iil_dataout : STD_LOGIC; + SIGNAL wire_n1li0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1li0il_dataout : STD_LOGIC; + SIGNAL wire_n1li0ili_dataout : STD_LOGIC; + SIGNAL wire_n1li0ill_dataout : STD_LOGIC; + SIGNAL wire_n1li0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1li0iO_dataout : STD_LOGIC; + SIGNAL wire_n1li0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1li0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1li0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1li0l0i_dataout : STD_LOGIC; + SIGNAL wire_n1li0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1li0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1li0l1i_dataout : STD_LOGIC; + SIGNAL wire_n1li0l1l_dataout : STD_LOGIC; + SIGNAL wire_n1li0l1O_dataout : STD_LOGIC; + SIGNAL wire_n1li0li_dataout : STD_LOGIC; + SIGNAL wire_n1li0lii_dataout : STD_LOGIC; + SIGNAL wire_n1li0lil_dataout : STD_LOGIC; + SIGNAL wire_n1li0liO_dataout : STD_LOGIC; + SIGNAL wire_n1li0ll_dataout : STD_LOGIC; + SIGNAL wire_n1li0lli_dataout : STD_LOGIC; + SIGNAL wire_n1li0lll_dataout : STD_LOGIC; + SIGNAL wire_n1li0llO_dataout : STD_LOGIC; + SIGNAL wire_n1li0lO_dataout : STD_LOGIC; + SIGNAL wire_n1li0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1li0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1li0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1li0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1li0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1li0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1li0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1li0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1li0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1li0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1li0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1li0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1li0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1li0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1li0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1li0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1li0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1li0OO_dataout : STD_LOGIC; + SIGNAL wire_n1li0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1li0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1li0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1li100i_dataout : STD_LOGIC; + SIGNAL wire_n1li100l_dataout : STD_LOGIC; + SIGNAL wire_n1li100O_dataout : STD_LOGIC; + SIGNAL wire_n1li101i_dataout : STD_LOGIC; + SIGNAL wire_n1li101l_dataout : STD_LOGIC; + SIGNAL wire_n1li101O_dataout : STD_LOGIC; + SIGNAL wire_n1li10i_dataout : STD_LOGIC; + SIGNAL wire_n1li10ii_dataout : STD_LOGIC; + SIGNAL wire_n1li10il_dataout : STD_LOGIC; + SIGNAL wire_n1li10iO_dataout : STD_LOGIC; + SIGNAL wire_n1li10l_dataout : STD_LOGIC; + SIGNAL wire_n1li10li_dataout : STD_LOGIC; + SIGNAL wire_n1li10ll_dataout : STD_LOGIC; + SIGNAL wire_n1li10lO_dataout : STD_LOGIC; + SIGNAL wire_n1li10O_dataout : STD_LOGIC; + SIGNAL wire_n1li10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1li10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1li10OO_dataout : STD_LOGIC; + SIGNAL wire_n1li110i_dataout : STD_LOGIC; + SIGNAL wire_n1li110l_dataout : STD_LOGIC; + SIGNAL wire_n1li110O_dataout : STD_LOGIC; + SIGNAL wire_n1li111i_dataout : STD_LOGIC; + SIGNAL wire_n1li111l_dataout : STD_LOGIC; + SIGNAL wire_n1li111O_dataout : STD_LOGIC; + SIGNAL wire_n1li11ii_dataout : STD_LOGIC; + SIGNAL wire_n1li11il_dataout : STD_LOGIC; + SIGNAL wire_n1li11iO_dataout : STD_LOGIC; + SIGNAL wire_n1li11l_dataout : STD_LOGIC; + SIGNAL wire_n1li11li_dataout : STD_LOGIC; + SIGNAL wire_n1li11ll_dataout : STD_LOGIC; + SIGNAL wire_n1li11lO_dataout : STD_LOGIC; + SIGNAL wire_n1li11O_dataout : STD_LOGIC; + SIGNAL wire_n1li11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1li11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1li11OO_dataout : STD_LOGIC; + SIGNAL wire_n1li1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1li1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1li1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1li1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1li1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1li1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1li1ii_dataout : STD_LOGIC; + SIGNAL wire_n1li1iii_dataout : STD_LOGIC; + SIGNAL wire_n1li1iil_dataout : STD_LOGIC; + SIGNAL wire_n1li1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1li1il_dataout : STD_LOGIC; + SIGNAL wire_n1li1ili_dataout : STD_LOGIC; + SIGNAL wire_n1li1ill_dataout : STD_LOGIC; + SIGNAL wire_n1li1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1li1iO_dataout : STD_LOGIC; + SIGNAL wire_n1li1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1li1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1li1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1li1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1li1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1li1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1li1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1li1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1li1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1li1li_dataout : STD_LOGIC; + SIGNAL wire_n1li1lii_dataout : STD_LOGIC; + SIGNAL wire_n1li1lil_dataout : STD_LOGIC; + SIGNAL wire_n1li1liO_dataout : STD_LOGIC; + SIGNAL wire_n1li1ll_dataout : STD_LOGIC; + SIGNAL wire_n1li1lli_dataout : STD_LOGIC; + SIGNAL wire_n1li1lll_dataout : STD_LOGIC; + SIGNAL wire_n1li1llO_dataout : STD_LOGIC; + SIGNAL wire_n1li1lO_dataout : STD_LOGIC; + SIGNAL wire_n1li1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1li1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1li1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1li1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1li1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1li1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1li1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1li1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1li1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1li1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1li1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1li1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1li1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1li1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1li1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1li1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1li1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1li1OO_dataout : STD_LOGIC; + SIGNAL wire_n1li1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1li1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1li1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1lii01i_dataout : STD_LOGIC; + SIGNAL wire_n1lii01l_dataout : STD_LOGIC; + SIGNAL wire_n1lii0ii_dataout : STD_LOGIC; + SIGNAL wire_n1lii0il_dataout : STD_LOGIC; + SIGNAL wire_n1lii0iO_dataout : STD_LOGIC; + SIGNAL wire_n1lii0li_dataout : STD_LOGIC; + SIGNAL wire_n1lii0lO_dataout : STD_LOGIC; + SIGNAL wire_n1lii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lii0OO_dataout : STD_LOGIC; + SIGNAL wire_n1lii10i_dataout : STD_LOGIC; + SIGNAL wire_n1lii11i_dataout : STD_LOGIC; + SIGNAL wire_n1lii11l_dataout : STD_LOGIC; + SIGNAL wire_n1lii11O_dataout : STD_LOGIC; + SIGNAL wire_n1lii1i_dataout : STD_LOGIC; + SIGNAL wire_n1lii1l_dataout : STD_LOGIC; + SIGNAL wire_n1lii1O_dataout : STD_LOGIC; + SIGNAL wire_n1liii0i_dataout : STD_LOGIC; + SIGNAL wire_n1liii0l_dataout : STD_LOGIC; + SIGNAL wire_n1liii0O_dataout : STD_LOGIC; + SIGNAL wire_n1liiiii_dataout : STD_LOGIC; + SIGNAL wire_n1liiiil_dataout : STD_LOGIC; + SIGNAL wire_n1liiiiO_dataout : STD_LOGIC; + SIGNAL wire_n1liiili_dataout : STD_LOGIC; + SIGNAL wire_n1liiill_dataout : STD_LOGIC; + SIGNAL wire_n1liiilO_dataout : STD_LOGIC; + SIGNAL wire_n1liiiOi_dataout : STD_LOGIC; + SIGNAL wire_n1liiiOl_dataout : STD_LOGIC; + SIGNAL wire_n1liiiOO_dataout : STD_LOGIC; + SIGNAL wire_n1liil0i_dataout : STD_LOGIC; + SIGNAL wire_n1liil0l_dataout : STD_LOGIC; + SIGNAL wire_n1liil0O_dataout : STD_LOGIC; + SIGNAL wire_n1liil1i_dataout : STD_LOGIC; + SIGNAL wire_n1liil1l_dataout : STD_LOGIC; + SIGNAL wire_n1liil1O_dataout : STD_LOGIC; + SIGNAL wire_n1liilii_dataout : STD_LOGIC; + SIGNAL wire_n1liilil_dataout : STD_LOGIC; + SIGNAL wire_n1liiliO_dataout : STD_LOGIC; + SIGNAL wire_n1liilli_dataout : STD_LOGIC; + SIGNAL wire_n1liilll_dataout : STD_LOGIC; + SIGNAL wire_n1liillO_dataout : STD_LOGIC; + SIGNAL wire_n1liilOi_dataout : STD_LOGIC; + SIGNAL wire_n1liilOl_dataout : STD_LOGIC; + SIGNAL wire_n1liilOO_dataout : STD_LOGIC; + SIGNAL wire_n1liiO0i_dataout : STD_LOGIC; + SIGNAL wire_n1liiO0l_dataout : STD_LOGIC; + SIGNAL wire_n1liiO0O_dataout : STD_LOGIC; + SIGNAL wire_n1liiO1i_dataout : STD_LOGIC; + SIGNAL wire_n1liiO1l_dataout : STD_LOGIC; + SIGNAL wire_n1liiO1O_dataout : STD_LOGIC; + SIGNAL wire_n1liiOii_dataout : STD_LOGIC; + SIGNAL wire_n1liiOil_dataout : STD_LOGIC; + SIGNAL wire_n1liiOiO_dataout : STD_LOGIC; + SIGNAL wire_n1liiOli_dataout : STD_LOGIC; + SIGNAL wire_n1liiOll_dataout : STD_LOGIC; + SIGNAL wire_n1liiOlO_dataout : STD_LOGIC; + SIGNAL wire_n1liiOOi_dataout : STD_LOGIC; + SIGNAL wire_n1liiOOl_dataout : STD_LOGIC; + SIGNAL wire_n1liiOOO_dataout : STD_LOGIC; + SIGNAL wire_n1lil00i_dataout : STD_LOGIC; + SIGNAL wire_n1lil00l_dataout : STD_LOGIC; + SIGNAL wire_n1lil00O_dataout : STD_LOGIC; + SIGNAL wire_n1lil01l_dataout : STD_LOGIC; + SIGNAL wire_n1lil01O_dataout : STD_LOGIC; + SIGNAL wire_n1lil0i_dataout : STD_LOGIC; + SIGNAL wire_n1lil0ii_dataout : STD_LOGIC; + SIGNAL wire_n1lil0il_dataout : STD_LOGIC; + SIGNAL wire_n1lil0iO_dataout : STD_LOGIC; + SIGNAL wire_n1lil0l_dataout : STD_LOGIC; + SIGNAL wire_n1lil0O_dataout : STD_LOGIC; + SIGNAL wire_n1lil0OO_dataout : STD_LOGIC; + SIGNAL wire_n1lil10i_dataout : STD_LOGIC; + SIGNAL wire_n1lil10l_dataout : STD_LOGIC; + SIGNAL wire_n1lil10O_dataout : STD_LOGIC; + SIGNAL wire_n1lil11i_dataout : STD_LOGIC; + SIGNAL wire_n1lil11l_dataout : STD_LOGIC; + SIGNAL wire_n1lil11O_dataout : STD_LOGIC; + SIGNAL wire_n1lil1i_dataout : STD_LOGIC; + SIGNAL wire_n1lil1ii_dataout : STD_LOGIC; + SIGNAL wire_n1lil1il_dataout : STD_LOGIC; + SIGNAL wire_n1lil1iO_dataout : STD_LOGIC; + SIGNAL wire_n1lil1l_dataout : STD_LOGIC; + SIGNAL wire_n1lil1li_dataout : STD_LOGIC; + SIGNAL wire_n1lil1O_dataout : STD_LOGIC; + SIGNAL wire_n1lili0O_dataout : STD_LOGIC; + SIGNAL wire_n1lili1i_dataout : STD_LOGIC; + SIGNAL wire_n1lili1l_dataout : STD_LOGIC; + SIGNAL wire_n1lili1O_dataout : STD_LOGIC; + SIGNAL wire_n1lilii_dataout : STD_LOGIC; + SIGNAL wire_n1liliii_dataout : STD_LOGIC; + SIGNAL wire_n1liliil_dataout : STD_LOGIC; + SIGNAL wire_n1lilil_dataout : STD_LOGIC; + SIGNAL wire_n1liliO_dataout : STD_LOGIC; + SIGNAL wire_n1lilli_dataout : STD_LOGIC; + SIGNAL wire_n1lilll_dataout : STD_LOGIC; + SIGNAL wire_n1lillO_dataout : STD_LOGIC; + SIGNAL wire_n1lilOi_dataout : STD_LOGIC; + SIGNAL wire_n1lilOiO_dataout : STD_LOGIC; + SIGNAL wire_n1lilOl_dataout : STD_LOGIC; + SIGNAL wire_n1lilOli_dataout : STD_LOGIC; + SIGNAL wire_n1lilOll_dataout : STD_LOGIC; + SIGNAL wire_n1lilOlO_dataout : STD_LOGIC; + SIGNAL wire_n1lilOO_dataout : STD_LOGIC; + SIGNAL wire_n1lilOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lilOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lilOOO_dataout : STD_LOGIC; + SIGNAL wire_n1liO00i_dataout : STD_LOGIC; + SIGNAL wire_n1liO00l_dataout : STD_LOGIC; + SIGNAL wire_n1liO00O_dataout : STD_LOGIC; + SIGNAL wire_n1liO01i_dataout : STD_LOGIC; + SIGNAL wire_n1liO01l_dataout : STD_LOGIC; + SIGNAL wire_n1liO01O_dataout : STD_LOGIC; + SIGNAL wire_n1liO0i_dataout : STD_LOGIC; + SIGNAL wire_n1liO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1liO0O_dataout : STD_LOGIC; + SIGNAL wire_n1liO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1liO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1liO10i_dataout : STD_LOGIC; + SIGNAL wire_n1liO10l_dataout : STD_LOGIC; + SIGNAL wire_n1liO10O_dataout : STD_LOGIC; + SIGNAL wire_n1liO11i_dataout : STD_LOGIC; + SIGNAL wire_n1liO11l_dataout : STD_LOGIC; + SIGNAL wire_n1liO11O_dataout : STD_LOGIC; + SIGNAL wire_n1liO1i_dataout : STD_LOGIC; + SIGNAL wire_n1liO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1liO1il_dataout : STD_LOGIC; + SIGNAL wire_n1liO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1liO1l_dataout : STD_LOGIC; + SIGNAL wire_n1liO1li_dataout : STD_LOGIC; + SIGNAL wire_n1liO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1liO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1liO1O_dataout : STD_LOGIC; + SIGNAL wire_n1liO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1liO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1liO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1liOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1liOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1liOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1liOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1liOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1liOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1liOii_dataout : STD_LOGIC; + SIGNAL wire_n1liOiii_dataout : STD_LOGIC; + SIGNAL wire_n1liOli_dataout : STD_LOGIC; + SIGNAL wire_n1liOli_w_lg_dataout4044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1liOll_dataout : STD_LOGIC; + SIGNAL wire_n1liOlO_dataout : STD_LOGIC; + SIGNAL wire_n1liOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1liOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1liOO0i_dataout : STD_LOGIC; + SIGNAL wire_n1liOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1liOO0O_dataout : STD_LOGIC; + SIGNAL wire_n1liOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1liOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1liOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1liOOi_dataout : STD_LOGIC; + SIGNAL wire_n1liOOii_dataout : STD_LOGIC; + SIGNAL wire_n1liOOil_dataout : STD_LOGIC; + SIGNAL wire_n1liOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1liOOl_dataout : STD_LOGIC; + SIGNAL wire_n1liOOli_dataout : STD_LOGIC; + SIGNAL wire_n1liOOll_dataout : STD_LOGIC; + SIGNAL wire_n1liOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1liOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1liOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1liOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1ll000i_dataout : STD_LOGIC; + SIGNAL wire_n1ll000l_dataout : STD_LOGIC; + SIGNAL wire_n1ll000O_dataout : STD_LOGIC; + SIGNAL wire_n1ll001i_dataout : STD_LOGIC; + SIGNAL wire_n1ll001l_dataout : STD_LOGIC; + SIGNAL wire_n1ll001O_dataout : STD_LOGIC; + SIGNAL wire_n1ll00ii_dataout : STD_LOGIC; + SIGNAL wire_n1ll00il_dataout : STD_LOGIC; + SIGNAL wire_n1ll00iO_dataout : STD_LOGIC; + SIGNAL wire_n1ll00l_dataout : STD_LOGIC; + SIGNAL wire_n1ll00li_dataout : STD_LOGIC; + SIGNAL wire_n1ll00ll_dataout : STD_LOGIC; + SIGNAL wire_n1ll00lO_dataout : STD_LOGIC; + SIGNAL wire_n1ll00O_dataout : STD_LOGIC; + SIGNAL wire_n1ll00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ll00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ll00OO_dataout : STD_LOGIC; + SIGNAL wire_n1ll011i_dataout : STD_LOGIC; + SIGNAL wire_n1ll01i_dataout : STD_LOGIC; + SIGNAL wire_n1ll01li_dataout : STD_LOGIC; + SIGNAL wire_n1ll01ll_dataout : STD_LOGIC; + SIGNAL wire_n1ll01lO_dataout : STD_LOGIC; + SIGNAL wire_n1ll01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ll01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ll01OO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1ll0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1ll0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1ll0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1ll0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1ll0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1ll0iii_dataout : STD_LOGIC; + SIGNAL wire_n1ll0iil_dataout : STD_LOGIC; + SIGNAL wire_n1ll0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0ili_dataout : STD_LOGIC; + SIGNAL wire_n1ll0ill_dataout : STD_LOGIC; + SIGNAL wire_n1ll0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1ll0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1ll0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0l0i_dataout : STD_LOGIC; + SIGNAL wire_n1ll0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1ll0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1ll0l1i_dataout : STD_LOGIC; + SIGNAL wire_n1ll0l1l_dataout : STD_LOGIC; + SIGNAL wire_n1ll0l1O_dataout : STD_LOGIC; + SIGNAL wire_n1ll0lii_dataout : STD_LOGIC; + SIGNAL wire_n1ll0lil_dataout : STD_LOGIC; + SIGNAL wire_n1ll0liO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0lli_dataout : STD_LOGIC; + SIGNAL wire_n1ll0lll_dataout : STD_LOGIC; + SIGNAL wire_n1ll0llO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1ll0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1ll0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1ll0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1ll0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1ll0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1ll0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1ll0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1ll0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1ll0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1ll0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1ll0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1ll0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1ll0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1ll0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1ll0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1ll100i_dataout : STD_LOGIC; + SIGNAL wire_n1ll100l_dataout : STD_LOGIC; + SIGNAL wire_n1ll100O_dataout : STD_LOGIC; + SIGNAL wire_n1ll101i_dataout : STD_LOGIC; + SIGNAL wire_n1ll101l_dataout : STD_LOGIC; + SIGNAL wire_n1ll101O_dataout : STD_LOGIC; + SIGNAL wire_n1ll10ii_dataout : STD_LOGIC; + SIGNAL wire_n1ll10il_dataout : STD_LOGIC; + SIGNAL wire_n1ll10iO_dataout : STD_LOGIC; + SIGNAL wire_n1ll10li_dataout : STD_LOGIC; + SIGNAL wire_n1ll10ll_dataout : STD_LOGIC; + SIGNAL wire_n1ll10lO_dataout : STD_LOGIC; + SIGNAL wire_n1ll10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ll10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ll10OO_dataout : STD_LOGIC; + SIGNAL wire_n1ll110i_dataout : STD_LOGIC; + SIGNAL wire_n1ll110l_dataout : STD_LOGIC; + SIGNAL wire_n1ll110O_dataout : STD_LOGIC; + SIGNAL wire_n1ll111i_dataout : STD_LOGIC; + SIGNAL wire_n1ll111l_dataout : STD_LOGIC; + SIGNAL wire_n1ll111O_dataout : STD_LOGIC; + SIGNAL wire_n1ll11ii_dataout : STD_LOGIC; + SIGNAL wire_n1ll11il_dataout : STD_LOGIC; + SIGNAL wire_n1ll11iO_dataout : STD_LOGIC; + SIGNAL wire_n1ll11li_dataout : STD_LOGIC; + SIGNAL wire_n1ll11ll_dataout : STD_LOGIC; + SIGNAL wire_n1ll11lO_dataout : STD_LOGIC; + SIGNAL wire_n1ll11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1ll11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ll11OO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1ll1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1ll1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1ll1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1ll1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1ll1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1ll1iii_dataout : STD_LOGIC; + SIGNAL wire_n1ll1iil_dataout : STD_LOGIC; + SIGNAL wire_n1ll1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1ili_dataout : STD_LOGIC; + SIGNAL wire_n1ll1ill_dataout : STD_LOGIC; + SIGNAL wire_n1ll1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1ll1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1ll1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1ll1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1ll1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1ll1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1ll1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1ll1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1ll1lii_dataout : STD_LOGIC; + SIGNAL wire_n1ll1lil_dataout : STD_LOGIC; + SIGNAL wire_n1ll1liO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1lli_dataout : STD_LOGIC; + SIGNAL wire_n1ll1lll_dataout : STD_LOGIC; + SIGNAL wire_n1ll1llO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1ll1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1ll1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1ll1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1ll1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1ll1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1ll1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1ll1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1ll1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1ll1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1ll1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1ll1Ol_w_lg_w_lg_dataout4106w4107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll1Ol_w_lg_w_lg_dataout4108w4109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll1Ol_w_lg_dataout4106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll1Ol_w_lg_dataout4108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1ll1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1ll1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1ll1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1OO_dataout : STD_LOGIC; + SIGNAL wire_n1ll1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1ll1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1ll1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1lli00i_dataout : STD_LOGIC; + SIGNAL wire_n1lli00l_dataout : STD_LOGIC; + SIGNAL wire_n1lli00O_dataout : STD_LOGIC; + SIGNAL wire_n1lli01i_dataout : STD_LOGIC; + SIGNAL wire_n1lli01l_dataout : STD_LOGIC; + SIGNAL wire_n1lli01O_dataout : STD_LOGIC; + SIGNAL wire_n1lli0ii_dataout : STD_LOGIC; + SIGNAL wire_n1lli0il_dataout : STD_LOGIC; + SIGNAL wire_n1lli0iO_dataout : STD_LOGIC; + SIGNAL wire_n1lli0li_dataout : STD_LOGIC; + SIGNAL wire_n1lli0ll_dataout : STD_LOGIC; + SIGNAL wire_n1lli0lO_dataout : STD_LOGIC; + SIGNAL wire_n1lli0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lli0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lli0OO_dataout : STD_LOGIC; + SIGNAL wire_n1lli10i_dataout : STD_LOGIC; + SIGNAL wire_n1lli10l_dataout : STD_LOGIC; + SIGNAL wire_n1lli10O_dataout : STD_LOGIC; + SIGNAL wire_n1lli11i_dataout : STD_LOGIC; + SIGNAL wire_n1lli11l_dataout : STD_LOGIC; + SIGNAL wire_n1lli11O_dataout : STD_LOGIC; + SIGNAL wire_n1lli1ii_dataout : STD_LOGIC; + SIGNAL wire_n1lli1il_dataout : STD_LOGIC; + SIGNAL wire_n1lli1iO_dataout : STD_LOGIC; + SIGNAL wire_n1lli1li_dataout : STD_LOGIC; + SIGNAL wire_n1lli1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lli1lO_dataout : STD_LOGIC; + SIGNAL wire_n1lli1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lli1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lli1OO_dataout : STD_LOGIC; + SIGNAL wire_n1llii0i_dataout : STD_LOGIC; + SIGNAL wire_n1llii0l_dataout : STD_LOGIC; + SIGNAL wire_n1llii0O_dataout : STD_LOGIC; + SIGNAL wire_n1llii1i_dataout : STD_LOGIC; + SIGNAL wire_n1llii1l_dataout : STD_LOGIC; + SIGNAL wire_n1llii1O_dataout : STD_LOGIC; + SIGNAL wire_n1lliiii_dataout : STD_LOGIC; + SIGNAL wire_n1lliiil_dataout : STD_LOGIC; + SIGNAL wire_n1lliiiO_dataout : STD_LOGIC; + SIGNAL wire_n1lliili_dataout : STD_LOGIC; + SIGNAL wire_n1lliill_dataout : STD_LOGIC; + SIGNAL wire_n1lliilO_dataout : STD_LOGIC; + SIGNAL wire_n1lliiOi_dataout : STD_LOGIC; + SIGNAL wire_n1lliiOl_dataout : STD_LOGIC; + SIGNAL wire_n1lliiOO_dataout : STD_LOGIC; + SIGNAL wire_n1llil0i_dataout : STD_LOGIC; + SIGNAL wire_n1llil0l_dataout : STD_LOGIC; + SIGNAL wire_n1llil0O_dataout : STD_LOGIC; + SIGNAL wire_n1llil1i_dataout : STD_LOGIC; + SIGNAL wire_n1llil1l_dataout : STD_LOGIC; + SIGNAL wire_n1llil1O_dataout : STD_LOGIC; + SIGNAL wire_n1llilii_dataout : STD_LOGIC; + SIGNAL wire_n1llilil_dataout : STD_LOGIC; + SIGNAL wire_n1lliliO_dataout : STD_LOGIC; + SIGNAL wire_n1llill_dataout : STD_LOGIC; + SIGNAL wire_n1llilli_dataout : STD_LOGIC; + SIGNAL wire_n1llilll_dataout : STD_LOGIC; + SIGNAL wire_n1llillO_dataout : STD_LOGIC; + SIGNAL wire_n1llilO_dataout : STD_LOGIC; + SIGNAL wire_n1llilOi_dataout : STD_LOGIC; + SIGNAL wire_n1llilOl_dataout : STD_LOGIC; + SIGNAL wire_n1llilOO_dataout : STD_LOGIC; + SIGNAL wire_n1lliO0i_dataout : STD_LOGIC; + SIGNAL wire_n1lliO0l_dataout : STD_LOGIC; + SIGNAL wire_n1lliO0O_dataout : STD_LOGIC; + SIGNAL wire_n1lliO1i_dataout : STD_LOGIC; + SIGNAL wire_n1lliO1l_dataout : STD_LOGIC; + SIGNAL wire_n1lliO1O_dataout : STD_LOGIC; + SIGNAL wire_n1lliOi_dataout : STD_LOGIC; + SIGNAL wire_n1lliOii_dataout : STD_LOGIC; + SIGNAL wire_n1lliOil_dataout : STD_LOGIC; + SIGNAL wire_n1lliOiO_dataout : STD_LOGIC; + SIGNAL wire_n1lliOl_dataout : STD_LOGIC; + SIGNAL wire_n1lliOli_dataout : STD_LOGIC; + SIGNAL wire_n1lliOll_dataout : STD_LOGIC; + SIGNAL wire_n1lliOlO_dataout : STD_LOGIC; + SIGNAL wire_n1lliOO_dataout : STD_LOGIC; + SIGNAL wire_n1lliOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lliOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lliOOO_dataout : STD_LOGIC; + SIGNAL wire_n1lll00i_dataout : STD_LOGIC; + SIGNAL wire_n1lll00l_dataout : STD_LOGIC; + SIGNAL wire_n1lll00O_dataout : STD_LOGIC; + SIGNAL wire_n1lll01i_dataout : STD_LOGIC; + SIGNAL wire_n1lll01l_dataout : STD_LOGIC; + SIGNAL wire_n1lll01O_dataout : STD_LOGIC; + SIGNAL wire_n1lll0ii_dataout : STD_LOGIC; + SIGNAL wire_n1lll0il_dataout : STD_LOGIC; + SIGNAL wire_n1lll0iO_dataout : STD_LOGIC; + SIGNAL wire_n1lll0li_dataout : STD_LOGIC; + SIGNAL wire_n1lll0ll_dataout : STD_LOGIC; + SIGNAL wire_n1lll0lO_dataout : STD_LOGIC; + SIGNAL wire_n1lll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lll0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lll0OO_dataout : STD_LOGIC; + SIGNAL wire_n1lll10i_dataout : STD_LOGIC; + SIGNAL wire_n1lll10l_dataout : STD_LOGIC; + SIGNAL wire_n1lll10O_dataout : STD_LOGIC; + SIGNAL wire_n1lll11i_dataout : STD_LOGIC; + SIGNAL wire_n1lll11l_dataout : STD_LOGIC; + SIGNAL wire_n1lll11O_dataout : STD_LOGIC; + SIGNAL wire_n1lll1i_dataout : STD_LOGIC; + SIGNAL wire_n1lll1ii_dataout : STD_LOGIC; + SIGNAL wire_n1lll1il_dataout : STD_LOGIC; + SIGNAL wire_n1lll1iO_dataout : STD_LOGIC; + SIGNAL wire_n1lll1l_dataout : STD_LOGIC; + SIGNAL wire_n1lll1li_dataout : STD_LOGIC; + SIGNAL wire_n1lll1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lll1lO_dataout : STD_LOGIC; + SIGNAL wire_n1lll1O_dataout : STD_LOGIC; + SIGNAL wire_n1lll1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lll1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lll1OO_dataout : STD_LOGIC; + SIGNAL wire_n1llli0i_dataout : STD_LOGIC; + SIGNAL wire_n1llli0l_dataout : STD_LOGIC; + SIGNAL wire_n1llli0O_dataout : STD_LOGIC; + SIGNAL wire_n1llli1i_dataout : STD_LOGIC; + SIGNAL wire_n1llli1l_dataout : STD_LOGIC; + SIGNAL wire_n1llli1O_dataout : STD_LOGIC; + SIGNAL wire_n1llliii_dataout : STD_LOGIC; + SIGNAL wire_n1llliil_dataout : STD_LOGIC; + SIGNAL wire_n1llliiO_dataout : STD_LOGIC; + SIGNAL wire_n1lllili_dataout : STD_LOGIC; + SIGNAL wire_n1lllill_dataout : STD_LOGIC; + SIGNAL wire_n1lllilO_dataout : STD_LOGIC; + SIGNAL wire_n1llliOi_dataout : STD_LOGIC; + SIGNAL wire_n1llliOl_dataout : STD_LOGIC; + SIGNAL wire_n1llll1O_dataout : STD_LOGIC; + SIGNAL wire_n1lllli_dataout : STD_LOGIC; + SIGNAL wire_n1lllll_dataout : STD_LOGIC; + SIGNAL wire_n1lllllO_dataout : STD_LOGIC; + SIGNAL wire_n1llllOi_dataout : STD_LOGIC; + SIGNAL wire_n1lllO0l_dataout : STD_LOGIC; + SIGNAL wire_n1lllO0O_dataout : STD_LOGIC; + SIGNAL wire_n1lllOi_dataout : STD_LOGIC; + SIGNAL wire_n1lllOii_dataout : STD_LOGIC; + SIGNAL wire_n1lllOil_dataout : STD_LOGIC; + SIGNAL wire_n1lllOiO_dataout : STD_LOGIC; + SIGNAL wire_n1lllOl_dataout : STD_LOGIC; + SIGNAL wire_n1lllOli_dataout : STD_LOGIC; + SIGNAL wire_n1lllOll_dataout : STD_LOGIC; + SIGNAL wire_n1lllOlO_dataout : STD_LOGIC; + SIGNAL wire_n1lllOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lllOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lllOOO_dataout : STD_LOGIC; + SIGNAL wire_n1llO00i_dataout : STD_LOGIC; + SIGNAL wire_n1llO00l_dataout : STD_LOGIC; + SIGNAL wire_n1llO00O_dataout : STD_LOGIC; + SIGNAL wire_n1llO01i_dataout : STD_LOGIC; + SIGNAL wire_n1llO01l_dataout : STD_LOGIC; + SIGNAL wire_n1llO01O_dataout : STD_LOGIC; + SIGNAL wire_n1llO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1llO0il_dataout : STD_LOGIC; + SIGNAL wire_n1llO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1llO0li_dataout : STD_LOGIC; + SIGNAL wire_n1llO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1llO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1llO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1llO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1llO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1llO10i_dataout : STD_LOGIC; + SIGNAL wire_n1llO10l_dataout : STD_LOGIC; + SIGNAL wire_n1llO10O_dataout : STD_LOGIC; + SIGNAL wire_n1llO11i_dataout : STD_LOGIC; + SIGNAL wire_n1llO11l_dataout : STD_LOGIC; + SIGNAL wire_n1llO11O_dataout : STD_LOGIC; + SIGNAL wire_n1llO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1llO1il_dataout : STD_LOGIC; + SIGNAL wire_n1llO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1llO1li_dataout : STD_LOGIC; + SIGNAL wire_n1llO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1llO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1llO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1llO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1llOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1llOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1llOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1llOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1llOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1llOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1llOiii_dataout : STD_LOGIC; + SIGNAL wire_n1llOiil_dataout : STD_LOGIC; + SIGNAL wire_n1llOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1llOili_dataout : STD_LOGIC; + SIGNAL wire_n1llOill_dataout : STD_LOGIC; + SIGNAL wire_n1llOilO_dataout : STD_LOGIC; + SIGNAL wire_n1llOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1llOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1llOiOO_dataout : STD_LOGIC; + SIGNAL wire_n1llOl0i_dataout : STD_LOGIC; + SIGNAL wire_n1llOl0l_dataout : STD_LOGIC; + SIGNAL wire_n1llOl0O_dataout : STD_LOGIC; + SIGNAL wire_n1llOl1i_dataout : STD_LOGIC; + SIGNAL wire_n1llOl1l_dataout : STD_LOGIC; + SIGNAL wire_n1llOl1O_dataout : STD_LOGIC; + SIGNAL wire_n1llOlii_dataout : STD_LOGIC; + SIGNAL wire_n1llOlil_dataout : STD_LOGIC; + SIGNAL wire_n1llOliO_dataout : STD_LOGIC; + SIGNAL wire_n1llOlli_dataout : STD_LOGIC; + SIGNAL wire_n1llOlll_dataout : STD_LOGIC; + SIGNAL wire_n1llOllO_dataout : STD_LOGIC; + SIGNAL wire_n1llOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1llOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1llOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1llOO0i_dataout : STD_LOGIC; + SIGNAL wire_n1llOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1llOO0O_dataout : STD_LOGIC; + SIGNAL wire_n1llOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1llOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1llOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1llOOii_dataout : STD_LOGIC; + SIGNAL wire_n1llOOil_dataout : STD_LOGIC; + SIGNAL wire_n1llOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1llOOli_dataout : STD_LOGIC; + SIGNAL wire_n1llOOll_dataout : STD_LOGIC; + SIGNAL wire_n1llOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1llOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1llOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1llOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO000i_dataout : STD_LOGIC; + SIGNAL wire_n1lO000l_dataout : STD_LOGIC; + SIGNAL wire_n1lO000O_dataout : STD_LOGIC; + SIGNAL wire_n1lO001i_dataout : STD_LOGIC; + SIGNAL wire_n1lO001l_dataout : STD_LOGIC; + SIGNAL wire_n1lO001O_dataout : STD_LOGIC; + SIGNAL wire_n1lO00ii_dataout : STD_LOGIC; + SIGNAL wire_n1lO00il_dataout : STD_LOGIC; + SIGNAL wire_n1lO00iO_dataout : STD_LOGIC; + SIGNAL wire_n1lO00li_dataout : STD_LOGIC; + SIGNAL wire_n1lO00ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO00lO_dataout : STD_LOGIC; + SIGNAL wire_n1lO00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lO00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lO00OO_dataout : STD_LOGIC; + SIGNAL wire_n1lO010i_dataout : STD_LOGIC; + SIGNAL wire_n1lO010l_dataout : STD_LOGIC; + SIGNAL wire_n1lO010O_dataout : STD_LOGIC; + SIGNAL wire_n1lO011i_dataout : STD_LOGIC; + SIGNAL wire_n1lO011l_dataout : STD_LOGIC; + SIGNAL wire_n1lO011O_dataout : STD_LOGIC; + SIGNAL wire_n1lO01ii_dataout : STD_LOGIC; + SIGNAL wire_n1lO01il_dataout : STD_LOGIC; + SIGNAL wire_n1lO01iO_dataout : STD_LOGIC; + SIGNAL wire_n1lO01li_dataout : STD_LOGIC; + SIGNAL wire_n1lO01ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO01lO_dataout : STD_LOGIC; + SIGNAL wire_n1lO01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lO01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lO01OO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1lO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1lO0iii_dataout : STD_LOGIC; + SIGNAL wire_n1lO0iil_dataout : STD_LOGIC; + SIGNAL wire_n1lO0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0il_dataout : STD_LOGIC; + SIGNAL wire_n1lO0ili_dataout : STD_LOGIC; + SIGNAL wire_n1lO0ill_dataout : STD_LOGIC; + SIGNAL wire_n1lO0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1lO0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1lO0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0l1O_dataout : STD_LOGIC; + SIGNAL wire_n1lO0lii_dataout : STD_LOGIC; + SIGNAL wire_n1lO0lil_dataout : STD_LOGIC; + SIGNAL wire_n1lO0liO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0lli_dataout : STD_LOGIC; + SIGNAL wire_n1lO0lll_dataout : STD_LOGIC; + SIGNAL wire_n1lO0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1lO0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1lO0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1lO0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lO0Ol_w_lg_dataout3833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO0Ol_w_lg_dataout3599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1lO0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1lO0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO100i_dataout : STD_LOGIC; + SIGNAL wire_n1lO100l_dataout : STD_LOGIC; + SIGNAL wire_n1lO100O_dataout : STD_LOGIC; + SIGNAL wire_n1lO101i_dataout : STD_LOGIC; + SIGNAL wire_n1lO101l_dataout : STD_LOGIC; + SIGNAL wire_n1lO101O_dataout : STD_LOGIC; + SIGNAL wire_n1lO10ii_dataout : STD_LOGIC; + SIGNAL wire_n1lO10il_dataout : STD_LOGIC; + SIGNAL wire_n1lO10iO_dataout : STD_LOGIC; + SIGNAL wire_n1lO10li_dataout : STD_LOGIC; + SIGNAL wire_n1lO10ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO10lO_dataout : STD_LOGIC; + SIGNAL wire_n1lO10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lO10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lO10OO_dataout : STD_LOGIC; + SIGNAL wire_n1lO110i_dataout : STD_LOGIC; + SIGNAL wire_n1lO110l_dataout : STD_LOGIC; + SIGNAL wire_n1lO110O_dataout : STD_LOGIC; + SIGNAL wire_n1lO111i_dataout : STD_LOGIC; + SIGNAL wire_n1lO111l_dataout : STD_LOGIC; + SIGNAL wire_n1lO111O_dataout : STD_LOGIC; + SIGNAL wire_n1lO11ii_dataout : STD_LOGIC; + SIGNAL wire_n1lO11il_dataout : STD_LOGIC; + SIGNAL wire_n1lO11iO_dataout : STD_LOGIC; + SIGNAL wire_n1lO11li_dataout : STD_LOGIC; + SIGNAL wire_n1lO11ll_dataout : STD_LOGIC; + SIGNAL wire_n1lO11lO_dataout : STD_LOGIC; + SIGNAL wire_n1lO11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lO11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lO11OO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1iii_dataout : STD_LOGIC; + SIGNAL wire_n1lO1iil_dataout : STD_LOGIC; + SIGNAL wire_n1lO1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1ili_dataout : STD_LOGIC; + SIGNAL wire_n1lO1ill_dataout : STD_LOGIC; + SIGNAL wire_n1lO1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1lO1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1lO1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1lii_dataout : STD_LOGIC; + SIGNAL wire_n1lO1lil_dataout : STD_LOGIC; + SIGNAL wire_n1lO1liO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1lli_dataout : STD_LOGIC; + SIGNAL wire_n1lO1lll_dataout : STD_LOGIC; + SIGNAL wire_n1lO1llO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1lO1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1lO1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1lO1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1lO1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1lO1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1lO1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1lO1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1lO1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1lO1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1lO1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1lO1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0iO_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0li_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0ll_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0lO_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lOi0OO_dataout : STD_LOGIC; + SIGNAL wire_n1lOi10l_dataout : STD_LOGIC; + SIGNAL wire_n1lOi10O_dataout : STD_LOGIC; + SIGNAL wire_n1lOi1ii_dataout : STD_LOGIC; + SIGNAL wire_n1lOi1il_dataout : STD_LOGIC; + SIGNAL wire_n1lOi1iO_dataout : STD_LOGIC; + SIGNAL wire_n1lOii0i_dataout : STD_LOGIC; + SIGNAL wire_n1lOii0l_dataout : STD_LOGIC; + SIGNAL wire_n1lOii0O_dataout : STD_LOGIC; + SIGNAL wire_n1lOii1i_dataout : STD_LOGIC; + SIGNAL wire_n1lOii1l_dataout : STD_LOGIC; + SIGNAL wire_n1lOii1O_dataout : STD_LOGIC; + SIGNAL wire_n1lOiii_dataout : STD_LOGIC; + SIGNAL wire_n1lOiiii_dataout : STD_LOGIC; + SIGNAL wire_n1lOiiil_dataout : STD_LOGIC; + SIGNAL wire_n1lOiiiO_dataout : STD_LOGIC; + SIGNAL wire_n1lOiil_dataout : STD_LOGIC; + SIGNAL wire_n1lOiili_dataout : STD_LOGIC; + SIGNAL wire_n1lOil0l_dataout : STD_LOGIC; + SIGNAL wire_n1lOil0O_dataout : STD_LOGIC; + SIGNAL wire_n1lOilii_dataout : STD_LOGIC; + SIGNAL wire_n1lOilil_dataout : STD_LOGIC; + SIGNAL wire_n1lOiliO_dataout : STD_LOGIC; + SIGNAL wire_n1lOilli_dataout : STD_LOGIC; + SIGNAL wire_n1lOilll_dataout : STD_LOGIC; + SIGNAL wire_n1lOillO_dataout : STD_LOGIC; + SIGNAL wire_n1lOilOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOilOO_dataout : STD_LOGIC; + SIGNAL wire_n1lOiO1i_dataout : STD_LOGIC; + SIGNAL wire_n1lOiO1l_dataout : STD_LOGIC; + SIGNAL wire_n1lOl00i_dataout : STD_LOGIC; + SIGNAL wire_n1lOl00l_dataout : STD_LOGIC; + SIGNAL wire_n1lOl00O_dataout : STD_LOGIC; + SIGNAL wire_n1lOl01i_dataout : STD_LOGIC; + SIGNAL wire_n1lOl01l_dataout : STD_LOGIC; + SIGNAL wire_n1lOl01O_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0ii_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0il_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0iO_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0li_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0ll_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0lO_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lOl0OO_dataout : STD_LOGIC; + SIGNAL wire_n1lOl10i_dataout : STD_LOGIC; + SIGNAL wire_n1lOl10l_dataout : STD_LOGIC; + SIGNAL wire_n1lOl10O_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1ii_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1il_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1iO_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1li_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1ll_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1lO_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1lOl1OO_dataout : STD_LOGIC; + SIGNAL wire_n1lOli0i_dataout : STD_LOGIC; + SIGNAL wire_n1lOli0l_dataout : STD_LOGIC; + SIGNAL wire_n1lOli0O_dataout : STD_LOGIC; + SIGNAL wire_n1lOli1i_dataout : STD_LOGIC; + SIGNAL wire_n1lOli1l_dataout : STD_LOGIC; + SIGNAL wire_n1lOli1O_dataout : STD_LOGIC; + SIGNAL wire_n1lOliii_dataout : STD_LOGIC; + SIGNAL wire_n1lOliil_dataout : STD_LOGIC; + SIGNAL wire_n1lOliiO_dataout : STD_LOGIC; + SIGNAL wire_n1lOlill_dataout : STD_LOGIC; + SIGNAL wire_n1lOlilO_dataout : STD_LOGIC; + SIGNAL wire_n1lOliOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOliOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOliOO_dataout : STD_LOGIC; + SIGNAL wire_n1lOll0i_dataout : STD_LOGIC; + SIGNAL wire_n1lOll0l_dataout : STD_LOGIC; + SIGNAL wire_n1lOll0O_dataout : STD_LOGIC; + SIGNAL wire_n1lOll1i_dataout : STD_LOGIC; + SIGNAL wire_n1lOll1l_dataout : STD_LOGIC; + SIGNAL wire_n1lOll1O_dataout : STD_LOGIC; + SIGNAL wire_n1lOllii_dataout : STD_LOGIC; + SIGNAL wire_n1lOllil_dataout : STD_LOGIC; + SIGNAL wire_n1lOlliO_dataout : STD_LOGIC; + SIGNAL wire_n1lOllli_dataout : STD_LOGIC; + SIGNAL wire_n1lOllll_dataout : STD_LOGIC; + SIGNAL wire_n1lOlllO_dataout : STD_LOGIC; + SIGNAL wire_n1lOllOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOllOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOllOO_dataout : STD_LOGIC; + SIGNAL wire_n1lOlO0i_dataout : STD_LOGIC; + SIGNAL wire_n1lOlO1i_dataout : STD_LOGIC; + SIGNAL wire_n1lOlO1l_dataout : STD_LOGIC; + SIGNAL wire_n1lOlO1O_dataout : STD_LOGIC; + SIGNAL wire_n1lOlOiO_dataout : STD_LOGIC; + SIGNAL wire_n1lOlOli_dataout : STD_LOGIC; + SIGNAL wire_n1lOlOll_dataout : STD_LOGIC; + SIGNAL wire_n1lOlOlO_dataout : STD_LOGIC; + SIGNAL wire_n1lOlOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOlOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOlOOO_dataout : STD_LOGIC; + SIGNAL wire_n1lOO11i_dataout : STD_LOGIC; + SIGNAL wire_n1lOOil_dataout : STD_LOGIC; + SIGNAL wire_n1lOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1lOOli_dataout : STD_LOGIC; + SIGNAL wire_n1lOOll_dataout : STD_LOGIC; + SIGNAL wire_n1lOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1lOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1lOOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1lOOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1lOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1O0000i_dataout : STD_LOGIC; + SIGNAL wire_n1O0000l_dataout : STD_LOGIC; + SIGNAL wire_n1O0000O_dataout : STD_LOGIC; + SIGNAL wire_n1O0001i_dataout : STD_LOGIC; + SIGNAL wire_n1O0001l_dataout : STD_LOGIC; + SIGNAL wire_n1O0001O_dataout : STD_LOGIC; + SIGNAL wire_n1O000ii_dataout : STD_LOGIC; + SIGNAL wire_n1O000il_dataout : STD_LOGIC; + SIGNAL wire_n1O000iO_dataout : STD_LOGIC; + SIGNAL wire_n1O000l_dataout : STD_LOGIC; + SIGNAL wire_n1O000li_dataout : STD_LOGIC; + SIGNAL wire_n1O000ll_dataout : STD_LOGIC; + SIGNAL wire_n1O000lO_dataout : STD_LOGIC; + SIGNAL wire_n1O000O_dataout : STD_LOGIC; + SIGNAL wire_n1O000Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O000Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O000OO_dataout : STD_LOGIC; + SIGNAL wire_n1O0010i_dataout : STD_LOGIC; + SIGNAL wire_n1O0010l_dataout : STD_LOGIC; + SIGNAL wire_n1O0010O_dataout : STD_LOGIC; + SIGNAL wire_n1O0011i_dataout : STD_LOGIC; + SIGNAL wire_n1O0011l_dataout : STD_LOGIC; + SIGNAL wire_n1O0011O_dataout : STD_LOGIC; + SIGNAL wire_n1O001ii_dataout : STD_LOGIC; + SIGNAL wire_n1O001il_dataout : STD_LOGIC; + SIGNAL wire_n1O001iO_dataout : STD_LOGIC; + SIGNAL wire_n1O001li_dataout : STD_LOGIC; + SIGNAL wire_n1O001ll_dataout : STD_LOGIC; + SIGNAL wire_n1O001lO_dataout : STD_LOGIC; + SIGNAL wire_n1O001Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O001Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O001OO_dataout : STD_LOGIC; + SIGNAL wire_n1O00i0i_dataout : STD_LOGIC; + SIGNAL wire_n1O00i0l_dataout : STD_LOGIC; + SIGNAL wire_n1O00i0O_dataout : STD_LOGIC; + SIGNAL wire_n1O00i1i_dataout : STD_LOGIC; + SIGNAL wire_n1O00i1l_dataout : STD_LOGIC; + SIGNAL wire_n1O00i1O_dataout : STD_LOGIC; + SIGNAL wire_n1O00ii_dataout : STD_LOGIC; + SIGNAL wire_n1O00iii_dataout : STD_LOGIC; + SIGNAL wire_n1O00iil_dataout : STD_LOGIC; + SIGNAL wire_n1O00iiO_dataout : STD_LOGIC; + SIGNAL wire_n1O00il_dataout : STD_LOGIC; + SIGNAL wire_n1O00ili_dataout : STD_LOGIC; + SIGNAL wire_n1O00ill_dataout : STD_LOGIC; + SIGNAL wire_n1O00ilO_dataout : STD_LOGIC; + SIGNAL wire_n1O00iO_dataout : STD_LOGIC; + SIGNAL wire_n1O00iOi_dataout : STD_LOGIC; + SIGNAL wire_n1O00iOl_dataout : STD_LOGIC; + SIGNAL wire_n1O00l1i_dataout : STD_LOGIC; + SIGNAL wire_n1O00l1l_dataout : STD_LOGIC; + SIGNAL wire_n1O00l1O_dataout : STD_LOGIC; + SIGNAL wire_n1O00li_dataout : STD_LOGIC; + SIGNAL wire_n1O00ll_dataout : STD_LOGIC; + SIGNAL wire_n1O00lO_dataout : STD_LOGIC; + SIGNAL wire_n1O00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O00OO_dataout : STD_LOGIC; + SIGNAL wire_n1O010i_dataout : STD_LOGIC; + SIGNAL wire_n1O010l_dataout : STD_LOGIC; + SIGNAL wire_n1O010O_dataout : STD_LOGIC; + SIGNAL wire_n1O0110i_dataout : STD_LOGIC; + SIGNAL wire_n1O0110l_dataout : STD_LOGIC; + SIGNAL wire_n1O0110O_dataout : STD_LOGIC; + SIGNAL wire_n1O0111i_dataout : STD_LOGIC; + SIGNAL wire_n1O0111l_dataout : STD_LOGIC; + SIGNAL wire_n1O0111O_dataout : STD_LOGIC; + SIGNAL wire_n1O011i_dataout : STD_LOGIC; + SIGNAL wire_n1O011ii_dataout : STD_LOGIC; + SIGNAL wire_n1O011il_dataout : STD_LOGIC; + SIGNAL wire_n1O011iO_dataout : STD_LOGIC; + SIGNAL wire_n1O011l_dataout : STD_LOGIC; + SIGNAL wire_n1O011li_dataout : STD_LOGIC; + SIGNAL wire_n1O011ll_dataout : STD_LOGIC; + SIGNAL wire_n1O011O_dataout : STD_LOGIC; + SIGNAL wire_n1O01ii_dataout : STD_LOGIC; + SIGNAL wire_n1O01iil_dataout : STD_LOGIC; + SIGNAL wire_n1O01il_dataout : STD_LOGIC; + SIGNAL wire_n1O01ill_dataout : STD_LOGIC; + SIGNAL wire_n1O01iO_dataout : STD_LOGIC; + SIGNAL wire_n1O01iOi_dataout : STD_LOGIC; + SIGNAL wire_n1O01l0l_dataout : STD_LOGIC; + SIGNAL wire_n1O01l1i_dataout : STD_LOGIC; + SIGNAL wire_n1O01l1O_dataout : STD_LOGIC; + SIGNAL wire_n1O01li_dataout : STD_LOGIC; + SIGNAL wire_n1O01lii_dataout : STD_LOGIC; + SIGNAL wire_n1O01liO_dataout : STD_LOGIC; + SIGNAL wire_n1O01ll_dataout : STD_LOGIC; + SIGNAL wire_n1O01lO_dataout : STD_LOGIC; + SIGNAL wire_n1O01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O01OlO_dataout : STD_LOGIC; + SIGNAL wire_n1O01OO_dataout : STD_LOGIC; + SIGNAL wire_n1O01OOi_dataout : STD_LOGIC; + SIGNAL wire_n1O01OOl_dataout : STD_LOGIC; + SIGNAL wire_n1O01OOO_dataout : STD_LOGIC; + SIGNAL wire_n1O0i01i_dataout : STD_LOGIC; + SIGNAL wire_n1O0i01i_w_lg_dataout18537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i01O_dataout : STD_LOGIC; + SIGNAL wire_n1O0i01O_w_lg_dataout18535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i10l_dataout : STD_LOGIC; + SIGNAL wire_n1O0i10l_w_lg_dataout18547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i11l_dataout : STD_LOGIC; + SIGNAL wire_n1O0i11l_w_lg_dataout18549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1O0i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1O0i1ii_w_lg_dataout18545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i1li_dataout : STD_LOGIC; + SIGNAL wire_n1O0i1li_w_lg_dataout18543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O0i1lO_w_lg_dataout18541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O0i1Ol_w_lg_dataout18539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1O0ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1O0iiii_dataout : STD_LOGIC; + SIGNAL wire_n1O0iiil_dataout : STD_LOGIC; + SIGNAL wire_n1O0iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1O0iili_dataout : STD_LOGIC; + SIGNAL wire_n1O0iill_dataout : STD_LOGIC; + SIGNAL wire_n1O0iilO_dataout : STD_LOGIC; + SIGNAL wire_n1O0iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1O0iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1O0iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1O0il0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0il0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0il0O_dataout : STD_LOGIC; + SIGNAL wire_n1O0il1i_dataout : STD_LOGIC; + SIGNAL wire_n1O0il1l_dataout : STD_LOGIC; + SIGNAL wire_n1O0il1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0ilii_dataout : STD_LOGIC; + SIGNAL wire_n1O0ilil_dataout : STD_LOGIC; + SIGNAL wire_n1O0iliO_dataout : STD_LOGIC; + SIGNAL wire_n1O0illi_dataout : STD_LOGIC; + SIGNAL wire_n1O0illl_dataout : STD_LOGIC; + SIGNAL wire_n1O0illO_dataout : STD_LOGIC; + SIGNAL wire_n1O0ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1O0ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1O0ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1O0iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOii_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOil_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOli_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOll_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1O0iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1O0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0l10i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l10l_dataout : STD_LOGIC; + SIGNAL wire_n1O0l10O_dataout : STD_LOGIC; + SIGNAL wire_n1O0l11i_dataout : STD_LOGIC; + SIGNAL wire_n1O0l11l_dataout : STD_LOGIC; + SIGNAL wire_n1O0l11O_dataout : STD_LOGIC; + SIGNAL wire_n1O0l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1O0lii_dataout : STD_LOGIC; + SIGNAL wire_n1O0lli_dataout : STD_LOGIC; + SIGNAL wire_n1O0lll_dataout : STD_LOGIC; + SIGNAL wire_n1O0llO_dataout : STD_LOGIC; + SIGNAL wire_n1O0O0ll_dataout : STD_LOGIC; + SIGNAL wire_n1O0O0lO_dataout : STD_LOGIC; + SIGNAL wire_n1O0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O0O0OO_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0OiiO_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oili_dataout : STD_LOGIC; + SIGNAL wire_n1O0Oill_dataout : STD_LOGIC; + SIGNAL wire_n1O0OilO_dataout : STD_LOGIC; + SIGNAL wire_n1O0OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1O0OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1O0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1O0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0OlOl_dataout : STD_LOGIC; + SIGNAL wire_n1O0OlOO_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO0i_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO0l_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO0O_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO1i_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO1l_dataout : STD_LOGIC; + SIGNAL wire_n1O0OO1O_dataout : STD_LOGIC; + SIGNAL wire_n1O0OOii_dataout : STD_LOGIC; + SIGNAL wire_n1O0OOil_dataout : STD_LOGIC; + SIGNAL wire_n1O0OOiO_dataout : STD_LOGIC; + SIGNAL wire_n1O0OOli_dataout : STD_LOGIC; + SIGNAL wire_n1O0OOll_dataout : STD_LOGIC; + SIGNAL wire_n1O0OOlO_dataout : STD_LOGIC; + SIGNAL wire_n1O0OOOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1000i_dataout : STD_LOGIC; + SIGNAL wire_n1O1000l_dataout : STD_LOGIC; + SIGNAL wire_n1O1000O_dataout : STD_LOGIC; + SIGNAL wire_n1O1001i_dataout : STD_LOGIC; + SIGNAL wire_n1O1001l_dataout : STD_LOGIC; + SIGNAL wire_n1O1001O_dataout : STD_LOGIC; + SIGNAL wire_n1O100ii_dataout : STD_LOGIC; + SIGNAL wire_n1O100il_dataout : STD_LOGIC; + SIGNAL wire_n1O100iO_dataout : STD_LOGIC; + SIGNAL wire_n1O100li_dataout : STD_LOGIC; + SIGNAL wire_n1O100ll_dataout : STD_LOGIC; + SIGNAL wire_n1O100lO_dataout : STD_LOGIC; + SIGNAL wire_n1O100Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O100Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O100OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1010i_dataout : STD_LOGIC; + SIGNAL wire_n1O1010l_dataout : STD_LOGIC; + SIGNAL wire_n1O1010O_dataout : STD_LOGIC; + SIGNAL wire_n1O1011i_dataout : STD_LOGIC; + SIGNAL wire_n1O1011l_dataout : STD_LOGIC; + SIGNAL wire_n1O1011O_dataout : STD_LOGIC; + SIGNAL wire_n1O101i_dataout : STD_LOGIC; + SIGNAL wire_n1O101ii_dataout : STD_LOGIC; + SIGNAL wire_n1O101il_dataout : STD_LOGIC; + SIGNAL wire_n1O101iO_dataout : STD_LOGIC; + SIGNAL wire_n1O101l_dataout : STD_LOGIC; + SIGNAL wire_n1O101li_dataout : STD_LOGIC; + SIGNAL wire_n1O101ll_dataout : STD_LOGIC; + SIGNAL wire_n1O101lO_dataout : STD_LOGIC; + SIGNAL wire_n1O101Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O101Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O101OO_dataout : STD_LOGIC; + SIGNAL wire_n1O10i0i_dataout : STD_LOGIC; + SIGNAL wire_n1O10i0l_dataout : STD_LOGIC; + SIGNAL wire_n1O10i0O_dataout : STD_LOGIC; + SIGNAL wire_n1O10i1i_dataout : STD_LOGIC; + SIGNAL wire_n1O10i1l_dataout : STD_LOGIC; + SIGNAL wire_n1O10i1O_dataout : STD_LOGIC; + SIGNAL wire_n1O10iii_dataout : STD_LOGIC; + SIGNAL wire_n1O10iil_dataout : STD_LOGIC; + SIGNAL wire_n1O10iiO_dataout : STD_LOGIC; + SIGNAL wire_n1O10ili_dataout : STD_LOGIC; + SIGNAL wire_n1O10ill_dataout : STD_LOGIC; + SIGNAL wire_n1O10ilO_dataout : STD_LOGIC; + SIGNAL wire_n1O10iOi_dataout : STD_LOGIC; + SIGNAL wire_n1O10iOl_dataout : STD_LOGIC; + SIGNAL wire_n1O10iOO_dataout : STD_LOGIC; + SIGNAL wire_n1O10l0i_dataout : STD_LOGIC; + SIGNAL wire_n1O10l0l_dataout : STD_LOGIC; + SIGNAL wire_n1O10l0O_dataout : STD_LOGIC; + SIGNAL wire_n1O10l1i_dataout : STD_LOGIC; + SIGNAL wire_n1O10l1l_dataout : STD_LOGIC; + SIGNAL wire_n1O10l1O_dataout : STD_LOGIC; + SIGNAL wire_n1O10lii_dataout : STD_LOGIC; + SIGNAL wire_n1O10lil_dataout : STD_LOGIC; + SIGNAL wire_n1O10liO_dataout : STD_LOGIC; + SIGNAL wire_n1O10lli_dataout : STD_LOGIC; + SIGNAL wire_n1O10lll_dataout : STD_LOGIC; + SIGNAL wire_n1O10llO_dataout : STD_LOGIC; + SIGNAL wire_n1O10lOi_dataout : STD_LOGIC; + SIGNAL wire_n1O10lOl_dataout : STD_LOGIC; + SIGNAL wire_n1O10lOO_dataout : STD_LOGIC; + SIGNAL wire_n1O10O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O10O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O10O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O10O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O10O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O10O1O_dataout : STD_LOGIC; + SIGNAL wire_n1O10Oii_dataout : STD_LOGIC; + SIGNAL wire_n1O10Oil_dataout : STD_LOGIC; + SIGNAL wire_n1O10OiO_dataout : STD_LOGIC; + SIGNAL wire_n1O10Oli_dataout : STD_LOGIC; + SIGNAL wire_n1O10Oll_dataout : STD_LOGIC; + SIGNAL wire_n1O10OlO_dataout : STD_LOGIC; + SIGNAL wire_n1O10OOi_dataout : STD_LOGIC; + SIGNAL wire_n1O10OOl_dataout : STD_LOGIC; + SIGNAL wire_n1O10OOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1100i_dataout : STD_LOGIC; + SIGNAL wire_n1O1100l_dataout : STD_LOGIC; + SIGNAL wire_n1O1100O_dataout : STD_LOGIC; + SIGNAL wire_n1O1101i_dataout : STD_LOGIC; + SIGNAL wire_n1O1101l_dataout : STD_LOGIC; + SIGNAL wire_n1O1101O_dataout : STD_LOGIC; + SIGNAL wire_n1O110i_dataout : STD_LOGIC; + SIGNAL wire_n1O110ii_dataout : STD_LOGIC; + SIGNAL wire_n1O110il_dataout : STD_LOGIC; + SIGNAL wire_n1O110iO_dataout : STD_LOGIC; + SIGNAL wire_n1O110l_dataout : STD_LOGIC; + SIGNAL wire_n1O110li_dataout : STD_LOGIC; + SIGNAL wire_n1O110ll_dataout : STD_LOGIC; + SIGNAL wire_n1O110lO_dataout : STD_LOGIC; + SIGNAL wire_n1O110O_dataout : STD_LOGIC; + SIGNAL wire_n1O110Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O110Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O110OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1110i_dataout : STD_LOGIC; + SIGNAL wire_n1O1110l_dataout : STD_LOGIC; + SIGNAL wire_n1O1110O_dataout : STD_LOGIC; + SIGNAL wire_n1O1111i_dataout : STD_LOGIC; + SIGNAL wire_n1O1111l_dataout : STD_LOGIC; + SIGNAL wire_n1O1111O_dataout : STD_LOGIC; + SIGNAL wire_n1O111i_dataout : STD_LOGIC; + SIGNAL wire_n1O111ii_dataout : STD_LOGIC; + SIGNAL wire_n1O111il_dataout : STD_LOGIC; + SIGNAL wire_n1O111iO_dataout : STD_LOGIC; + SIGNAL wire_n1O111l_dataout : STD_LOGIC; + SIGNAL wire_n1O111li_dataout : STD_LOGIC; + SIGNAL wire_n1O111ll_dataout : STD_LOGIC; + SIGNAL wire_n1O111lO_dataout : STD_LOGIC; + SIGNAL wire_n1O111O_dataout : STD_LOGIC; + SIGNAL wire_n1O111Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O111Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O111OO_dataout : STD_LOGIC; + SIGNAL wire_n1O11i0i_dataout : STD_LOGIC; + SIGNAL wire_n1O11i0l_dataout : STD_LOGIC; + SIGNAL wire_n1O11i0O_dataout : STD_LOGIC; + SIGNAL wire_n1O11i1i_dataout : STD_LOGIC; + SIGNAL wire_n1O11i1l_dataout : STD_LOGIC; + SIGNAL wire_n1O11i1O_dataout : STD_LOGIC; + SIGNAL wire_n1O11ii_dataout : STD_LOGIC; + SIGNAL wire_n1O11iii_dataout : STD_LOGIC; + SIGNAL wire_n1O11iil_dataout : STD_LOGIC; + SIGNAL wire_n1O11iiO_dataout : STD_LOGIC; + SIGNAL wire_n1O11il_dataout : STD_LOGIC; + SIGNAL wire_n1O11ili_dataout : STD_LOGIC; + SIGNAL wire_n1O11ill_dataout : STD_LOGIC; + SIGNAL wire_n1O11ilO_dataout : STD_LOGIC; + SIGNAL wire_n1O11iO_dataout : STD_LOGIC; + SIGNAL wire_n1O11iOi_dataout : STD_LOGIC; + SIGNAL wire_n1O11iOl_dataout : STD_LOGIC; + SIGNAL wire_n1O11iOO_dataout : STD_LOGIC; + SIGNAL wire_n1O11l0i_dataout : STD_LOGIC; + SIGNAL wire_n1O11l0l_dataout : STD_LOGIC; + SIGNAL wire_n1O11l0O_dataout : STD_LOGIC; + SIGNAL wire_n1O11l1i_dataout : STD_LOGIC; + SIGNAL wire_n1O11l1l_dataout : STD_LOGIC; + SIGNAL wire_n1O11l1O_dataout : STD_LOGIC; + SIGNAL wire_n1O11li_dataout : STD_LOGIC; + SIGNAL wire_n1O11lii_dataout : STD_LOGIC; + SIGNAL wire_n1O11lil_dataout : STD_LOGIC; + SIGNAL wire_n1O11liO_dataout : STD_LOGIC; + SIGNAL wire_n1O11ll_dataout : STD_LOGIC; + SIGNAL wire_n1O11lli_dataout : STD_LOGIC; + SIGNAL wire_n1O11lll_dataout : STD_LOGIC; + SIGNAL wire_n1O11llO_dataout : STD_LOGIC; + SIGNAL wire_n1O11lO_dataout : STD_LOGIC; + SIGNAL wire_n1O11lOi_dataout : STD_LOGIC; + SIGNAL wire_n1O11lOl_dataout : STD_LOGIC; + SIGNAL wire_n1O11lOO_dataout : STD_LOGIC; + SIGNAL wire_n1O11O0i_dataout : STD_LOGIC; + SIGNAL wire_n1O11O0l_dataout : STD_LOGIC; + SIGNAL wire_n1O11O0O_dataout : STD_LOGIC; + SIGNAL wire_n1O11O1i_dataout : STD_LOGIC; + SIGNAL wire_n1O11O1l_dataout : STD_LOGIC; + SIGNAL wire_n1O11O1O_dataout : STD_LOGIC; + SIGNAL wire_n1O11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O11Oii_dataout : STD_LOGIC; + SIGNAL wire_n1O11Oil_dataout : STD_LOGIC; + SIGNAL wire_n1O11OiO_dataout : STD_LOGIC; + SIGNAL wire_n1O11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O11Oli_dataout : STD_LOGIC; + SIGNAL wire_n1O11Oll_dataout : STD_LOGIC; + SIGNAL wire_n1O11OlO_dataout : STD_LOGIC; + SIGNAL wire_n1O11OO_dataout : STD_LOGIC; + SIGNAL wire_n1O11OOi_dataout : STD_LOGIC; + SIGNAL wire_n1O11OOl_dataout : STD_LOGIC; + SIGNAL wire_n1O11OOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1i00i_dataout : STD_LOGIC; + SIGNAL wire_n1O1i00l_dataout : STD_LOGIC; + SIGNAL wire_n1O1i00O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i01i_dataout : STD_LOGIC; + SIGNAL wire_n1O1i01l_dataout : STD_LOGIC; + SIGNAL wire_n1O1i01O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0il_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0li_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1i0OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1i10i_dataout : STD_LOGIC; + SIGNAL wire_n1O1i10l_dataout : STD_LOGIC; + SIGNAL wire_n1O1i10O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i11i_dataout : STD_LOGIC; + SIGNAL wire_n1O1i11l_dataout : STD_LOGIC; + SIGNAL wire_n1O1i11O_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1il_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1li_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1i1OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1ii1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1iiii_dataout : STD_LOGIC; + SIGNAL wire_n1O1iiil_dataout : STD_LOGIC; + SIGNAL wire_n1O1iiiO_dataout : STD_LOGIC; + SIGNAL wire_n1O1iili_dataout : STD_LOGIC; + SIGNAL wire_n1O1iill_dataout : STD_LOGIC; + SIGNAL wire_n1O1iilO_dataout : STD_LOGIC; + SIGNAL wire_n1O1iiOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1iiOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1iiOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1il0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1il0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1il0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1il1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1il1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1il1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1ilii_dataout : STD_LOGIC; + SIGNAL wire_n1O1ilil_dataout : STD_LOGIC; + SIGNAL wire_n1O1iliO_dataout : STD_LOGIC; + SIGNAL wire_n1O1illi_dataout : STD_LOGIC; + SIGNAL wire_n1O1illl_dataout : STD_LOGIC; + SIGNAL wire_n1O1illO_dataout : STD_LOGIC; + SIGNAL wire_n1O1ilOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1ilOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1ilOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1iO0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1iO1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1iO1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1iO1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOii_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOil_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOiO_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOli_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOll_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOlO_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1iOOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l00i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l00l_dataout : STD_LOGIC; + SIGNAL wire_n1O1l00O_dataout : STD_LOGIC; + SIGNAL wire_n1O1l01i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l01l_dataout : STD_LOGIC; + SIGNAL wire_n1O1l01O_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0il_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0li_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1l0OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l10i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l10l_dataout : STD_LOGIC; + SIGNAL wire_n1O1l10O_dataout : STD_LOGIC; + SIGNAL wire_n1O1l11i_dataout : STD_LOGIC; + SIGNAL wire_n1O1l11l_dataout : STD_LOGIC; + SIGNAL wire_n1O1l11O_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1il_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1li_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1l1OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1li0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1li0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1li0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1li1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1li1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1li1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1lii_dataout : STD_LOGIC; + SIGNAL wire_n1O1liii_dataout : STD_LOGIC; + SIGNAL wire_n1O1liil_dataout : STD_LOGIC; + SIGNAL wire_n1O1liiO_dataout : STD_LOGIC; + SIGNAL wire_n1O1lil_dataout : STD_LOGIC; + SIGNAL wire_n1O1lili_dataout : STD_LOGIC; + SIGNAL wire_n1O1lill_dataout : STD_LOGIC; + SIGNAL wire_n1O1lilO_dataout : STD_LOGIC; + SIGNAL wire_n1O1liO_dataout : STD_LOGIC; + SIGNAL wire_n1O1liOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1liOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1liOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1ll1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1llii_dataout : STD_LOGIC; + SIGNAL wire_n1O1llil_dataout : STD_LOGIC; + SIGNAL wire_n1O1lliO_dataout : STD_LOGIC; + SIGNAL wire_n1O1llli_dataout : STD_LOGIC; + SIGNAL wire_n1O1llll_dataout : STD_LOGIC; + SIGNAL wire_n1O1lllO_dataout : STD_LOGIC; + SIGNAL wire_n1O1llOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1llOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1llOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1lO1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOii_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOil_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOiO_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOli_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOll_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOlO_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1lOOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O00i_dataout : STD_LOGIC; + SIGNAL wire_n1O1O00l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O00O_dataout : STD_LOGIC; + SIGNAL wire_n1O1O01i_dataout : STD_LOGIC; + SIGNAL wire_n1O1O01l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O01O_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0il_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0li_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1O0OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O10i_dataout : STD_LOGIC; + SIGNAL wire_n1O1O10l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O10O_dataout : STD_LOGIC; + SIGNAL wire_n1O1O11i_dataout : STD_LOGIC; + SIGNAL wire_n1O1O11l_dataout : STD_LOGIC; + SIGNAL wire_n1O1O11O_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1ii_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1il_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1iO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1li_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1ll_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1lO_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1O1O1OO_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oiii_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oiil_dataout : STD_LOGIC; + SIGNAL wire_n1O1OiiO_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oili_dataout : STD_LOGIC; + SIGNAL wire_n1O1Oill_dataout : STD_LOGIC; + SIGNAL wire_n1O1OilO_dataout : STD_LOGIC; + SIGNAL wire_n1O1OiOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1OiOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1OiOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1Olii_dataout : STD_LOGIC; + SIGNAL wire_n1O1Olil_dataout : STD_LOGIC; + SIGNAL wire_n1O1OliO_dataout : STD_LOGIC; + SIGNAL wire_n1O1Olli_dataout : STD_LOGIC; + SIGNAL wire_n1O1Olll_dataout : STD_LOGIC; + SIGNAL wire_n1O1OllO_dataout : STD_LOGIC; + SIGNAL wire_n1O1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1O1OlOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1OlOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1OlOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO0i_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO0l_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO0O_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO1i_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO1l_dataout : STD_LOGIC; + SIGNAL wire_n1O1OO1O_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOii_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOil_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOiO_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOli_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOll_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOlO_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOOi_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOOl_dataout : STD_LOGIC; + SIGNAL wire_n1O1OOOO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi000l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi000O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00il_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00li_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00ll_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Oi00OO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0iii_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0iil_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0ili_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0ill_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0l0i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0l0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0l1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0l1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0l1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0lii_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0lil_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0liO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0lli_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0lll_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0llO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0lOi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0lOl_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1Oi0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi100i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi100l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi100O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10il_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10li_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10ll_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Oi10OO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi110i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi110l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi111O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi11ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oi11il_dataout : STD_LOGIC; + SIGNAL wire_n1Oi11iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi11li_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1iii_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1iil_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1ili_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1ill_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1Oi1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1Oii00O_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0il_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0li_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0ll_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Oii0OO_dataout : STD_LOGIC; + SIGNAL wire_n1Oii10i_dataout : STD_LOGIC; + SIGNAL wire_n1Oii10l_dataout : STD_LOGIC; + SIGNAL wire_n1Oii10O_dataout : STD_LOGIC; + SIGNAL wire_n1Oii11i_dataout : STD_LOGIC; + SIGNAL wire_n1Oii11l_dataout : STD_LOGIC; + SIGNAL wire_n1Oii11O_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1il_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1li_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1ll_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oii1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii0i_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oiii1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oiiiii_dataout : STD_LOGIC; + SIGNAL wire_n1Oiiiil_dataout : STD_LOGIC; + SIGNAL wire_n1OiiiiO_dataout : STD_LOGIC; + SIGNAL wire_n1Oiiili_dataout : STD_LOGIC; + SIGNAL wire_n1Oiiill_dataout : STD_LOGIC; + SIGNAL wire_n1OiiilO_dataout : STD_LOGIC; + SIGNAL wire_n1OiiiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiiiOl_dataout : STD_LOGIC; + SIGNAL wire_n1OiiiOO_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil0i_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil0l_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil0O_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil1i_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil1l_dataout : STD_LOGIC; + SIGNAL wire_n1Oiil1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oiilii_dataout : STD_LOGIC; + SIGNAL wire_n1Oiilil_dataout : STD_LOGIC; + SIGNAL wire_n1OiiliO_dataout : STD_LOGIC; + SIGNAL wire_n1Oiilli_dataout : STD_LOGIC; + SIGNAL wire_n1Oiilll_dataout : STD_LOGIC; + SIGNAL wire_n1OiillO_dataout : STD_LOGIC; + SIGNAL wire_n1OiilOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiilOl_dataout : STD_LOGIC; + SIGNAL wire_n1OiilOO_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OiiO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOii_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOil_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOli_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOll_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OiiOOO_dataout : STD_LOGIC; + SIGNAL wire_n1Oil01i_dataout : STD_LOGIC; + SIGNAL wire_n1Oil01l_dataout : STD_LOGIC; + SIGNAL wire_n1Oil10i_dataout : STD_LOGIC; + SIGNAL wire_n1Oil10l_dataout : STD_LOGIC; + SIGNAL wire_n1Oil10O_dataout : STD_LOGIC; + SIGNAL wire_n1Oil11i_dataout : STD_LOGIC; + SIGNAL wire_n1Oil11l_dataout : STD_LOGIC; + SIGNAL wire_n1Oil11O_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1il_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1li_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1ll_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Oil1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OiO00i_dataout : STD_LOGIC; + SIGNAL wire_n1OiO00l_dataout : STD_LOGIC; + SIGNAL wire_n1OiO00O_dataout : STD_LOGIC; + SIGNAL wire_n1OiO01i_dataout : STD_LOGIC; + SIGNAL wire_n1OiO01l_dataout : STD_LOGIC; + SIGNAL wire_n1OiO01O_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0il_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0li_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OiO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1OiO10i_dataout : STD_LOGIC; + SIGNAL wire_n1OiO10l_dataout : STD_LOGIC; + SIGNAL wire_n1OiO10O_dataout : STD_LOGIC; + SIGNAL wire_n1OiO11l_dataout : STD_LOGIC; + SIGNAL wire_n1OiO11O_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1il_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1li_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OiO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1OiOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1OiOiii_dataout : STD_LOGIC; + SIGNAL wire_n1OiOiil_dataout : STD_LOGIC; + SIGNAL wire_n1OiOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1OiOili_dataout : STD_LOGIC; + SIGNAL wire_n1OiOill_dataout : STD_LOGIC; + SIGNAL wire_n1OiOilO_dataout : STD_LOGIC; + SIGNAL wire_n1OiOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1OiOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1OiOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1OiOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1OiOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OiOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol00lO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol00OO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol010i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol010l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol010O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol011O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01ii_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01il_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01iO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01li_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01ll_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01lO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0lOO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O0i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O0l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O0O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O1i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O1l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0O1O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0Oii_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0Oil_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0OiO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0Oli_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0Oll_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1Ol0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol100i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol100l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol100O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol101i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol101l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol101O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10ii_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10il_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10iO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10li_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10ll_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10lO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol10OO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol110i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol110O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol111l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol111O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11ii_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11il_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11iO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11li_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11ll_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11lO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1Ol11OO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1iii_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1iil_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1ili_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1ill_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1Ol1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1Oli01l_dataout : STD_LOGIC; + SIGNAL wire_n1Oli10i_dataout : STD_LOGIC; + SIGNAL wire_n1Oli10l_dataout : STD_LOGIC; + SIGNAL wire_n1Oli11i_dataout : STD_LOGIC; + SIGNAL wire_n1Oli11l_dataout : STD_LOGIC; + SIGNAL wire_n1Oli11O_dataout : STD_LOGIC; + SIGNAL wire_n1Oli1ll_dataout : STD_LOGIC; + SIGNAL wire_n1Oli1ll_w_lg_w_lg_w_lg_dataout18040w18046w18047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oli1ll_w_lg_w_lg_dataout18040w18046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oli1ll_w_lg_dataout18053w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oli1ll_w_lg_dataout18040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1Oli1lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oli1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OliiOO_dataout : STD_LOGIC; + SIGNAL wire_n1Olil0i_dataout : STD_LOGIC; + SIGNAL wire_n1Olil0l_dataout : STD_LOGIC; + SIGNAL wire_n1Olil0O_dataout : STD_LOGIC; + SIGNAL wire_n1Olil1i_dataout : STD_LOGIC; + SIGNAL wire_n1Olil1l_dataout : STD_LOGIC; + SIGNAL wire_n1Olil1O_dataout : STD_LOGIC; + SIGNAL wire_n1Olilii_dataout : STD_LOGIC; + SIGNAL wire_n1Olilil_dataout : STD_LOGIC; + SIGNAL wire_n1OliliO_dataout : STD_LOGIC; + SIGNAL wire_n1Olilli_dataout : STD_LOGIC; + SIGNAL wire_n1Olilll_dataout : STD_LOGIC; + SIGNAL wire_n1OlillO_dataout : STD_LOGIC; + SIGNAL wire_n1OlilOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlilOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlilOO_dataout : STD_LOGIC; + SIGNAL wire_n1OliO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OliO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OliO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OliO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OliO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OliO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OliOii_dataout : STD_LOGIC; + SIGNAL wire_n1OliOil_dataout : STD_LOGIC; + SIGNAL wire_n1OliOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OliOli_dataout : STD_LOGIC; + SIGNAL wire_n1OliOll_dataout : STD_LOGIC; + SIGNAL wire_n1OliOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OliOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OliOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OliOOO_dataout : STD_LOGIC; + SIGNAL wire_n1Oll00l_dataout : STD_LOGIC; + SIGNAL wire_n1Oll00O_dataout : STD_LOGIC; + SIGNAL wire_n1Oll01i_dataout : STD_LOGIC; + SIGNAL wire_n1Oll0ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oll0il_dataout : STD_LOGIC; + SIGNAL wire_n1Oll0iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oll0ll_dataout : STD_LOGIC; + SIGNAL wire_n1Oll0lO_dataout : STD_LOGIC; + SIGNAL wire_n1Oll0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1Oll10i_dataout : STD_LOGIC; + SIGNAL wire_n1Oll10l_dataout : STD_LOGIC; + SIGNAL wire_n1Oll10O_dataout : STD_LOGIC; + SIGNAL wire_n1Oll11i_dataout : STD_LOGIC; + SIGNAL wire_n1Oll11l_dataout : STD_LOGIC; + SIGNAL wire_n1Oll11O_dataout : STD_LOGIC; + SIGNAL wire_n1Oll1ii_dataout : STD_LOGIC; + SIGNAL wire_n1Oll1il_dataout : STD_LOGIC; + SIGNAL wire_n1Oll1iO_dataout : STD_LOGIC; + SIGNAL wire_n1Oll1li_dataout : STD_LOGIC; + SIGNAL wire_n1Oll1OO_dataout : STD_LOGIC; + SIGNAL wire_n1Olliil_dataout : STD_LOGIC; + SIGNAL wire_n1OlliiO_dataout : STD_LOGIC; + SIGNAL wire_n1OlliOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlliOO_dataout : STD_LOGIC; + SIGNAL wire_n1Olll0i_dataout : STD_LOGIC; + SIGNAL wire_n1Olll0l_dataout : STD_LOGIC; + SIGNAL wire_n1Olll0O_dataout : STD_LOGIC; + SIGNAL wire_n1Olll1i_dataout : STD_LOGIC; + SIGNAL wire_n1Olll1l_dataout : STD_LOGIC; + SIGNAL wire_n1Olll1O_dataout : STD_LOGIC; + SIGNAL wire_n1Olllii_dataout : STD_LOGIC; + SIGNAL wire_n1Olllil_dataout : STD_LOGIC; + SIGNAL wire_n1OllliO_dataout : STD_LOGIC; + SIGNAL wire_n1Olllli_dataout : STD_LOGIC; + SIGNAL wire_n1Olllll_dataout : STD_LOGIC; + SIGNAL wire_n1OllllO_dataout : STD_LOGIC; + SIGNAL wire_n1OlllOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlllOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlllOO_dataout : STD_LOGIC; + SIGNAL wire_n1OllO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OllO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OllO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OllO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OllO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OllO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OllOii_dataout : STD_LOGIC; + SIGNAL wire_n1OllOil_dataout : STD_LOGIC; + SIGNAL wire_n1OllOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OllOli_dataout : STD_LOGIC; + SIGNAL wire_n1OllOll_dataout : STD_LOGIC; + SIGNAL wire_n1OllOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OllOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OllOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OllOOO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO00i_dataout : STD_LOGIC; + SIGNAL wire_n1OlO00l_dataout : STD_LOGIC; + SIGNAL wire_n1OlO00O_dataout : STD_LOGIC; + SIGNAL wire_n1OlO01i_dataout : STD_LOGIC; + SIGNAL wire_n1OlO01l_dataout : STD_LOGIC; + SIGNAL wire_n1OlO01O_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0il_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0li_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OlO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO10i_dataout : STD_LOGIC; + SIGNAL wire_n1OlO10l_dataout : STD_LOGIC; + SIGNAL wire_n1OlO10O_dataout : STD_LOGIC; + SIGNAL wire_n1OlO11i_dataout : STD_LOGIC; + SIGNAL wire_n1OlO11l_dataout : STD_LOGIC; + SIGNAL wire_n1OlO11O_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1il_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1li_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OlO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1OlOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1OlOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1OlOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1OlOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1OlOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiii_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiil_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOili_dataout : STD_LOGIC; + SIGNAL wire_n1OlOill_dataout : STD_LOGIC; + SIGNAL wire_n1OlOilO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlOiOO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOl0i_dataout : STD_LOGIC; + SIGNAL wire_n1OlOl0l_dataout : STD_LOGIC; + SIGNAL wire_n1OlOl0O_dataout : STD_LOGIC; + SIGNAL wire_n1OlOl1i_dataout : STD_LOGIC; + SIGNAL wire_n1OlOl1l_dataout : STD_LOGIC; + SIGNAL wire_n1OlOl1O_dataout : STD_LOGIC; + SIGNAL wire_n1OlOli_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlii_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlil_dataout : STD_LOGIC; + SIGNAL wire_n1OlOliO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOll_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlli_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlll_dataout : STD_LOGIC; + SIGNAL wire_n1OlOllO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OlOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOii_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOil_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOli_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOll_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOO_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OlOOOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO00i_dataout : STD_LOGIC; + SIGNAL wire_n1OO00l_dataout : STD_LOGIC; + SIGNAL wire_n1OO00O_dataout : STD_LOGIC; + SIGNAL wire_n1OO00Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OO00Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO00OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO010i_dataout : STD_LOGIC; + SIGNAL wire_n1OO010l_dataout : STD_LOGIC; + SIGNAL wire_n1OO010O_dataout : STD_LOGIC; + SIGNAL wire_n1OO011i_dataout : STD_LOGIC; + SIGNAL wire_n1OO011l_dataout : STD_LOGIC; + SIGNAL wire_n1OO011O_dataout : STD_LOGIC; + SIGNAL wire_n1OO01i_dataout : STD_LOGIC; + SIGNAL wire_n1OO01ii_dataout : STD_LOGIC; + SIGNAL wire_n1OO01il_dataout : STD_LOGIC; + SIGNAL wire_n1OO01iO_dataout : STD_LOGIC; + SIGNAL wire_n1OO01l_dataout : STD_LOGIC; + SIGNAL wire_n1OO01li_dataout : STD_LOGIC; + SIGNAL wire_n1OO01ll_dataout : STD_LOGIC; + SIGNAL wire_n1OO01lO_dataout : STD_LOGIC; + SIGNAL wire_n1OO01O_dataout : STD_LOGIC; + SIGNAL wire_n1OO01Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OO01Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO01OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i0i_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i0l_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i0O_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i1i_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i1l_dataout : STD_LOGIC; + SIGNAL wire_n1OO0i1O_dataout : STD_LOGIC; + SIGNAL wire_n1OO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1OO0iii_dataout : STD_LOGIC; + SIGNAL wire_n1OO0iil_dataout : STD_LOGIC; + SIGNAL wire_n1OO0iiO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0il_dataout : STD_LOGIC; + SIGNAL wire_n1OO0ili_dataout : STD_LOGIC; + SIGNAL wire_n1OO0ill_dataout : STD_LOGIC; + SIGNAL wire_n1OO0ilO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0iO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0iOi_dataout : STD_LOGIC; + SIGNAL wire_n1OO0iOl_dataout : STD_LOGIC; + SIGNAL wire_n1OO0iOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0l0O_dataout : STD_LOGIC; + SIGNAL wire_n1OO0li_dataout : STD_LOGIC; + SIGNAL wire_n1OO0lii_dataout : STD_LOGIC; + SIGNAL wire_n1OO0ll_dataout : STD_LOGIC; + SIGNAL wire_n1OO0lO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO0OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO0OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OO0OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OO0OOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO100i_dataout : STD_LOGIC; + SIGNAL wire_n1OO100l_dataout : STD_LOGIC; + SIGNAL wire_n1OO100O_dataout : STD_LOGIC; + SIGNAL wire_n1OO101i_dataout : STD_LOGIC; + SIGNAL wire_n1OO101l_dataout : STD_LOGIC; + SIGNAL wire_n1OO101O_dataout : STD_LOGIC; + SIGNAL wire_n1OO10i_dataout : STD_LOGIC; + SIGNAL wire_n1OO10ii_dataout : STD_LOGIC; + SIGNAL wire_n1OO10il_dataout : STD_LOGIC; + SIGNAL wire_n1OO10iO_dataout : STD_LOGIC; + SIGNAL wire_n1OO10l_dataout : STD_LOGIC; + SIGNAL wire_n1OO10li_dataout : STD_LOGIC; + SIGNAL wire_n1OO10ll_dataout : STD_LOGIC; + SIGNAL wire_n1OO10lO_dataout : STD_LOGIC; + SIGNAL wire_n1OO10O_dataout : STD_LOGIC; + SIGNAL wire_n1OO10Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OO10Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO10OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO111i_dataout : STD_LOGIC; + SIGNAL wire_n1OO11i_dataout : STD_LOGIC; + SIGNAL wire_n1OO11l_dataout : STD_LOGIC; + SIGNAL wire_n1OO11li_dataout : STD_LOGIC; + SIGNAL wire_n1OO11ll_dataout : STD_LOGIC; + SIGNAL wire_n1OO11lO_dataout : STD_LOGIC; + SIGNAL wire_n1OO11O_dataout : STD_LOGIC; + SIGNAL wire_n1OO11Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OO11Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO11OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i0i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i0l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i0O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i1i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i1l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1i1O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1OO1iii_dataout : STD_LOGIC; + SIGNAL wire_n1OO1iil_dataout : STD_LOGIC; + SIGNAL wire_n1OO1iiO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1il_dataout : STD_LOGIC; + SIGNAL wire_n1OO1ili_dataout : STD_LOGIC; + SIGNAL wire_n1OO1ill_dataout : STD_LOGIC; + SIGNAL wire_n1OO1ilO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1iOi_dataout : STD_LOGIC; + SIGNAL wire_n1OO1iOl_dataout : STD_LOGIC; + SIGNAL wire_n1OO1iOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l0i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l0l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l0O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l1i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l1l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1l1O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1li_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lii_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lil_dataout : STD_LOGIC; + SIGNAL wire_n1OO1liO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lli_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lll_dataout : STD_LOGIC; + SIGNAL wire_n1OO1llO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lOi_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lOl_dataout : STD_LOGIC; + SIGNAL wire_n1OO1lOO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O0i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O0l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O0O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O1i_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O1l_dataout : STD_LOGIC; + SIGNAL wire_n1OO1O1O_dataout : STD_LOGIC; + SIGNAL wire_n1OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OO1Oii_dataout : STD_LOGIC; + SIGNAL wire_n1OO1Oil_dataout : STD_LOGIC; + SIGNAL wire_n1OO1OiO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OO1Oli_dataout : STD_LOGIC; + SIGNAL wire_n1OO1Oll_dataout : STD_LOGIC; + SIGNAL wire_n1OO1OlO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OO1OOi_dataout : STD_LOGIC; + SIGNAL wire_n1OO1OOl_dataout : STD_LOGIC; + SIGNAL wire_n1OO1OOO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi00l_dataout : STD_LOGIC; + SIGNAL wire_n1OOi00O_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0i_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0ii_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0il_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0iO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0li_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0ll_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0lO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0O_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OOi0OO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi10i_dataout : STD_LOGIC; + SIGNAL wire_n1OOi10l_dataout : STD_LOGIC; + SIGNAL wire_n1OOi10O_dataout : STD_LOGIC; + SIGNAL wire_n1OOi11i_dataout : STD_LOGIC; + SIGNAL wire_n1OOi11l_dataout : STD_LOGIC; + SIGNAL wire_n1OOi11O_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1ii_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1il_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1iO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1l_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1li_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1ll_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1lO_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OOii0i_dataout : STD_LOGIC; + SIGNAL wire_n1OOii0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOii0O_dataout : STD_LOGIC; + SIGNAL wire_n1OOii1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOii1l_dataout : STD_LOGIC; + SIGNAL wire_n1OOii1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOiii_dataout : STD_LOGIC; + SIGNAL wire_n1OOiiii_dataout : STD_LOGIC; + SIGNAL wire_n1OOiiil_dataout : STD_LOGIC; + SIGNAL wire_n1OOiiiO_dataout : STD_LOGIC; + SIGNAL wire_n1OOiil_dataout : STD_LOGIC; + SIGNAL wire_n1OOiili_dataout : STD_LOGIC; + SIGNAL wire_n1OOiill_dataout : STD_LOGIC; + SIGNAL wire_n1OOiilO_dataout : STD_LOGIC; + SIGNAL wire_n1OOiiO_dataout : STD_LOGIC; + SIGNAL wire_n1OOiiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOiiOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOiiOO_dataout : STD_LOGIC; + SIGNAL wire_n1OOil0i_dataout : STD_LOGIC; + SIGNAL wire_n1OOil0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOil1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOil1l_dataout : STD_LOGIC; + SIGNAL wire_n1OOil1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOili_dataout : STD_LOGIC; + SIGNAL wire_n1OOilil_dataout : STD_LOGIC; + SIGNAL wire_n1OOiliO_dataout : STD_LOGIC; + SIGNAL wire_n1OOill_dataout : STD_LOGIC; + SIGNAL wire_n1OOilli_dataout : STD_LOGIC; + SIGNAL wire_n1OOilll_dataout : STD_LOGIC; + SIGNAL wire_n1OOillO_dataout : STD_LOGIC; + SIGNAL wire_n1OOilO_dataout : STD_LOGIC; + SIGNAL wire_n1OOilOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOiOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOiOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOiOO_dataout : STD_LOGIC; + SIGNAL wire_n1OOl00l_dataout : STD_LOGIC; + SIGNAL wire_n1OOl01l_dataout : STD_LOGIC; + SIGNAL wire_n1OOl0i_dataout : STD_LOGIC; + SIGNAL wire_n1OOl0ii_dataout : STD_LOGIC; + SIGNAL wire_n1OOl0iO_dataout : STD_LOGIC; + SIGNAL wire_n1OOl0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOl0ll_dataout : STD_LOGIC; + SIGNAL wire_n1OOl0O_dataout : STD_LOGIC; + SIGNAL wire_n1OOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OOl1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOl1l_dataout : STD_LOGIC; + SIGNAL wire_n1OOl1lO_dataout : STD_LOGIC; + SIGNAL wire_n1OOl1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOl1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OOlii_dataout : STD_LOGIC; + SIGNAL wire_n1OOlil_dataout : STD_LOGIC; + SIGNAL wire_n1OOliO_dataout : STD_LOGIC; + SIGNAL wire_n1OOll0i_dataout : STD_LOGIC; + SIGNAL wire_n1OOll0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOll0O_dataout : STD_LOGIC; + SIGNAL wire_n1OOll1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOll1l_dataout : STD_LOGIC; + SIGNAL wire_n1OOll1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOlli_dataout : STD_LOGIC; + SIGNAL wire_n1OOllii_dataout : STD_LOGIC; + SIGNAL wire_n1OOllil_dataout : STD_LOGIC; + SIGNAL wire_n1OOlliO_dataout : STD_LOGIC; + SIGNAL wire_n1OOlll_dataout : STD_LOGIC; + SIGNAL wire_n1OOllli_dataout : STD_LOGIC; + SIGNAL wire_n1OOllll_dataout : STD_LOGIC; + SIGNAL wire_n1OOlllO_dataout : STD_LOGIC; + SIGNAL wire_n1OOllO_dataout : STD_LOGIC; + SIGNAL wire_n1OOllOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOllOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOllOO_dataout : STD_LOGIC; + SIGNAL wire_n1OOlO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OOlO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOlO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OOlO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOlO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OOlO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOii_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOil_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOli_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOll_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOO_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOlOOO_dataout : STD_LOGIC; + SIGNAL wire_n1OOO00l_dataout : STD_LOGIC; + SIGNAL wire_n1OOO00O_dataout : STD_LOGIC; + SIGNAL wire_n1OOO01i_dataout : STD_LOGIC; + SIGNAL wire_n1OOO01l_dataout : STD_LOGIC; + SIGNAL wire_n1OOO01O_dataout : STD_LOGIC; + SIGNAL wire_n1OOO0i_dataout : STD_LOGIC; + SIGNAL wire_n1OOO0ii_dataout : STD_LOGIC; + SIGNAL wire_n1OOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOO0O_dataout : STD_LOGIC; + SIGNAL wire_n1OOO10i_dataout : STD_LOGIC; + SIGNAL wire_n1OOO10l_dataout : STD_LOGIC; + SIGNAL wire_n1OOO10O_dataout : STD_LOGIC; + SIGNAL wire_n1OOO11i_dataout : STD_LOGIC; + SIGNAL wire_n1OOO11l_dataout : STD_LOGIC; + SIGNAL wire_n1OOO11O_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1ii_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1il_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1iO_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1l_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1li_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1ll_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1lO_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_n1OOO1OO_dataout : STD_LOGIC; + SIGNAL wire_n1OOOii_dataout : STD_LOGIC; + SIGNAL wire_n1OOOil_dataout : STD_LOGIC; + SIGNAL wire_n1OOOiO_dataout : STD_LOGIC; + SIGNAL wire_n1OOOl0O_dataout : STD_LOGIC; + SIGNAL wire_n1OOOl0O_w_lg_dataout17642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOli_dataout : STD_LOGIC; + SIGNAL wire_n1OOOliO_dataout : STD_LOGIC; + SIGNAL wire_n1OOOliO_w_lg_dataout17640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOll_dataout : STD_LOGIC; + SIGNAL wire_n1OOOlll_dataout : STD_LOGIC; + SIGNAL wire_n1OOOlll_w_lg_dataout17638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOlO_dataout : STD_LOGIC; + SIGNAL wire_n1OOOlOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOOlOl_w_lg_dataout17636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOO0l_dataout : STD_LOGIC; + SIGNAL wire_n1OOOO0l_w_lg_dataout17630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOO1i_dataout : STD_LOGIC; + SIGNAL wire_n1OOOO1i_w_lg_dataout17634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOO1O_dataout : STD_LOGIC; + SIGNAL wire_n1OOOO1O_w_lg_dataout17632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOOi_dataout : STD_LOGIC; + SIGNAL wire_n1OOOOii_dataout : STD_LOGIC; + SIGNAL wire_n1OOOOii_w_lg_dataout17628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1OOOOl_dataout : STD_LOGIC; + SIGNAL wire_n1OOOOO_dataout : STD_LOGIC; + SIGNAL wire_ni00000i_dataout : STD_LOGIC; + SIGNAL wire_ni00000l_dataout : STD_LOGIC; + SIGNAL wire_ni00000O_dataout : STD_LOGIC; + SIGNAL wire_ni00001i_dataout : STD_LOGIC; + SIGNAL wire_ni00001l_dataout : STD_LOGIC; + SIGNAL wire_ni00001O_dataout : STD_LOGIC; + SIGNAL wire_ni0000ii_dataout : STD_LOGIC; + SIGNAL wire_ni0000il_dataout : STD_LOGIC; + SIGNAL wire_ni0000iO_dataout : STD_LOGIC; + SIGNAL wire_ni0000li_dataout : STD_LOGIC; + SIGNAL wire_ni0000ll_dataout : STD_LOGIC; + SIGNAL wire_ni0000lO_dataout : STD_LOGIC; + SIGNAL wire_ni0000Oi_dataout : STD_LOGIC; + SIGNAL wire_ni00010i_dataout : STD_LOGIC; + SIGNAL wire_ni00010l_dataout : STD_LOGIC; + SIGNAL wire_ni00010O_dataout : STD_LOGIC; + SIGNAL wire_ni00011l_dataout : STD_LOGIC; + SIGNAL wire_ni00011O_dataout : STD_LOGIC; + SIGNAL wire_ni0001ii_dataout : STD_LOGIC; + SIGNAL wire_ni0001il_dataout : STD_LOGIC; + SIGNAL wire_ni0001iO_dataout : STD_LOGIC; + SIGNAL wire_ni0001li_dataout : STD_LOGIC; + SIGNAL wire_ni0001ll_dataout : STD_LOGIC; + SIGNAL wire_ni0001lO_dataout : STD_LOGIC; + SIGNAL wire_ni0001Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0001Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0001OO_dataout : STD_LOGIC; + SIGNAL wire_ni000ilO_dataout : STD_LOGIC; + SIGNAL wire_ni000iOi_dataout : STD_LOGIC; + SIGNAL wire_ni000iOl_dataout : STD_LOGIC; + SIGNAL wire_ni000iOO_dataout : STD_LOGIC; + SIGNAL wire_ni000l0i_dataout : STD_LOGIC; + SIGNAL wire_ni000l0l_dataout : STD_LOGIC; + SIGNAL wire_ni000l0O_dataout : STD_LOGIC; + SIGNAL wire_ni000l1i_dataout : STD_LOGIC; + SIGNAL wire_ni000l1l_dataout : STD_LOGIC; + SIGNAL wire_ni000l1O_dataout : STD_LOGIC; + SIGNAL wire_ni000lii_dataout : STD_LOGIC; + SIGNAL wire_ni000lil_dataout : STD_LOGIC; + SIGNAL wire_ni000liO_dataout : STD_LOGIC; + SIGNAL wire_ni000lli_dataout : STD_LOGIC; + SIGNAL wire_ni000lll_dataout : STD_LOGIC; + SIGNAL wire_ni000llO_dataout : STD_LOGIC; + SIGNAL wire_ni000lOi_dataout : STD_LOGIC; + SIGNAL wire_ni000lOl_dataout : STD_LOGIC; + SIGNAL wire_ni000lOO_dataout : STD_LOGIC; + SIGNAL wire_ni000O0i_dataout : STD_LOGIC; + SIGNAL wire_ni000O0l_dataout : STD_LOGIC; + SIGNAL wire_ni000O0O_dataout : STD_LOGIC; + SIGNAL wire_ni000O1i_dataout : STD_LOGIC; + SIGNAL wire_ni000O1l_dataout : STD_LOGIC; + SIGNAL wire_ni000O1O_dataout : STD_LOGIC; + SIGNAL wire_ni000Oii_dataout : STD_LOGIC; + SIGNAL wire_ni000Oil_dataout : STD_LOGIC; + SIGNAL wire_ni00100i_dataout : STD_LOGIC; + SIGNAL wire_ni00100l_dataout : STD_LOGIC; + SIGNAL wire_ni00100O_dataout : STD_LOGIC; + SIGNAL wire_ni00101i_dataout : STD_LOGIC; + SIGNAL wire_ni00101l_dataout : STD_LOGIC; + SIGNAL wire_ni00101O_dataout : STD_LOGIC; + SIGNAL wire_ni0010ii_dataout : STD_LOGIC; + SIGNAL wire_ni0010il_dataout : STD_LOGIC; + SIGNAL wire_ni00110i_dataout : STD_LOGIC; + SIGNAL wire_ni00110l_dataout : STD_LOGIC; + SIGNAL wire_ni00110O_dataout : STD_LOGIC; + SIGNAL wire_ni00111i_dataout : STD_LOGIC; + SIGNAL wire_ni00111l_dataout : STD_LOGIC; + SIGNAL wire_ni00111O_dataout : STD_LOGIC; + SIGNAL wire_ni0011ii_dataout : STD_LOGIC; + SIGNAL wire_ni0011il_dataout : STD_LOGIC; + SIGNAL wire_ni0011iO_dataout : STD_LOGIC; + SIGNAL wire_ni0011l_dataout : STD_LOGIC; + SIGNAL wire_ni0011li_dataout : STD_LOGIC; + SIGNAL wire_ni0011ll_dataout : STD_LOGIC; + SIGNAL wire_ni0011lO_dataout : STD_LOGIC; + SIGNAL wire_ni0011O_dataout : STD_LOGIC; + SIGNAL wire_ni0011Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0011Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0011OO_dataout : STD_LOGIC; + SIGNAL wire_ni001iii_dataout : STD_LOGIC; + SIGNAL wire_ni001iil_dataout : STD_LOGIC; + SIGNAL wire_ni001iiO_dataout : STD_LOGIC; + SIGNAL wire_ni001ili_dataout : STD_LOGIC; + SIGNAL wire_ni001ill_dataout : STD_LOGIC; + SIGNAL wire_ni001ilO_dataout : STD_LOGIC; + SIGNAL wire_ni001iOi_dataout : STD_LOGIC; + SIGNAL wire_ni001iOl_dataout : STD_LOGIC; + SIGNAL wire_ni001iOO_dataout : STD_LOGIC; + SIGNAL wire_ni001l0i_dataout : STD_LOGIC; + SIGNAL wire_ni001l0l_dataout : STD_LOGIC; + SIGNAL wire_ni001l0O_dataout : STD_LOGIC; + SIGNAL wire_ni001l1i_dataout : STD_LOGIC; + SIGNAL wire_ni001l1l_dataout : STD_LOGIC; + SIGNAL wire_ni001l1O_dataout : STD_LOGIC; + SIGNAL wire_ni001lii_dataout : STD_LOGIC; + SIGNAL wire_ni001lil_dataout : STD_LOGIC; + SIGNAL wire_ni001liO_dataout : STD_LOGIC; + SIGNAL wire_ni001lli_dataout : STD_LOGIC; + SIGNAL wire_ni001lll_dataout : STD_LOGIC; + SIGNAL wire_ni001llO_dataout : STD_LOGIC; + SIGNAL wire_ni001lOi_dataout : STD_LOGIC; + SIGNAL wire_ni001lOl_dataout : STD_LOGIC; + SIGNAL wire_ni001lOO_dataout : STD_LOGIC; + SIGNAL wire_ni001O1i_dataout : STD_LOGIC; + SIGNAL wire_ni001O1l_dataout : STD_LOGIC; + SIGNAL wire_ni001O1O_dataout : STD_LOGIC; + SIGNAL wire_ni00i00i_dataout : STD_LOGIC; + SIGNAL wire_ni00i00l_dataout : STD_LOGIC; + SIGNAL wire_ni00i00O_dataout : STD_LOGIC; + SIGNAL wire_ni00i01i_dataout : STD_LOGIC; + SIGNAL wire_ni00i01l_dataout : STD_LOGIC; + SIGNAL wire_ni00i01O_dataout : STD_LOGIC; + SIGNAL wire_ni00i0ii_dataout : STD_LOGIC; + SIGNAL wire_ni00i0il_dataout : STD_LOGIC; + SIGNAL wire_ni00i0iO_dataout : STD_LOGIC; + SIGNAL wire_ni00i0li_dataout : STD_LOGIC; + SIGNAL wire_ni00i0ll_dataout : STD_LOGIC; + SIGNAL wire_ni00i0lO_dataout : STD_LOGIC; + SIGNAL wire_ni00i0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni00i0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni00i0OO_dataout : STD_LOGIC; + SIGNAL wire_ni00i1ii_dataout : STD_LOGIC; + SIGNAL wire_ni00i1il_dataout : STD_LOGIC; + SIGNAL wire_ni00i1iO_dataout : STD_LOGIC; + SIGNAL wire_ni00i1li_dataout : STD_LOGIC; + SIGNAL wire_ni00i1ll_dataout : STD_LOGIC; + SIGNAL wire_ni00i1lO_dataout : STD_LOGIC; + SIGNAL wire_ni00i1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni00i1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni00i1OO_dataout : STD_LOGIC; + SIGNAL wire_ni00ii1i_dataout : STD_LOGIC; + SIGNAL wire_ni00ii1l_dataout : STD_LOGIC; + SIGNAL wire_ni00ii1O_dataout : STD_LOGIC; + SIGNAL wire_ni00il0i_dataout : STD_LOGIC; + SIGNAL wire_ni00il0l_dataout : STD_LOGIC; + SIGNAL wire_ni00il0O_dataout : STD_LOGIC; + SIGNAL wire_ni00il1l_dataout : STD_LOGIC; + SIGNAL wire_ni00il1O_dataout : STD_LOGIC; + SIGNAL wire_ni00ilii_dataout : STD_LOGIC; + SIGNAL wire_ni00ilil_dataout : STD_LOGIC; + SIGNAL wire_ni00iliO_dataout : STD_LOGIC; + SIGNAL wire_ni00illi_dataout : STD_LOGIC; + SIGNAL wire_ni00illl_dataout : STD_LOGIC; + SIGNAL wire_ni00illO_dataout : STD_LOGIC; + SIGNAL wire_ni00ilOi_dataout : STD_LOGIC; + SIGNAL wire_ni00ilOl_dataout : STD_LOGIC; + SIGNAL wire_ni00ilOO_dataout : STD_LOGIC; + SIGNAL wire_ni00iO0i_dataout : STD_LOGIC; + SIGNAL wire_ni00iO0l_dataout : STD_LOGIC; + SIGNAL wire_ni00iO0O_dataout : STD_LOGIC; + SIGNAL wire_ni00iO1i_dataout : STD_LOGIC; + SIGNAL wire_ni00iO1l_dataout : STD_LOGIC; + SIGNAL wire_ni00iO1O_dataout : STD_LOGIC; + SIGNAL wire_ni00iOi_dataout : STD_LOGIC; + SIGNAL wire_ni00iOii_dataout : STD_LOGIC; + SIGNAL wire_ni00iOil_dataout : STD_LOGIC; + SIGNAL wire_ni00iOiO_dataout : STD_LOGIC; + SIGNAL wire_ni00iOl_dataout : STD_LOGIC; + SIGNAL wire_ni00iOli_dataout : STD_LOGIC; + SIGNAL wire_ni00iOll_dataout : STD_LOGIC; + SIGNAL wire_ni00iOlO_dataout : STD_LOGIC; + SIGNAL wire_ni00iOO_dataout : STD_LOGIC; + SIGNAL wire_ni00iOOi_dataout : STD_LOGIC; + SIGNAL wire_ni00l00i_dataout : STD_LOGIC; + SIGNAL wire_ni00l00l_dataout : STD_LOGIC; + SIGNAL wire_ni00l00O_dataout : STD_LOGIC; + SIGNAL wire_ni00l01i_dataout : STD_LOGIC; + SIGNAL wire_ni00l01l_dataout : STD_LOGIC; + SIGNAL wire_ni00l01O_dataout : STD_LOGIC; + SIGNAL wire_ni00l0i_dataout : STD_LOGIC; + SIGNAL wire_ni00l0ii_dataout : STD_LOGIC; + SIGNAL wire_ni00l0il_dataout : STD_LOGIC; + SIGNAL wire_ni00l0iO_dataout : STD_LOGIC; + SIGNAL wire_ni00l0l_dataout : STD_LOGIC; + SIGNAL wire_ni00l0li_dataout : STD_LOGIC; + SIGNAL wire_ni00l0ll_dataout : STD_LOGIC; + SIGNAL wire_ni00l0lO_dataout : STD_LOGIC; + SIGNAL wire_ni00l0O_dataout : STD_LOGIC; + SIGNAL wire_ni00l0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni00l0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni00l0OO_dataout : STD_LOGIC; + SIGNAL wire_ni00l1i_dataout : STD_LOGIC; + SIGNAL wire_ni00l1l_dataout : STD_LOGIC; + SIGNAL wire_ni00l1lO_dataout : STD_LOGIC; + SIGNAL wire_ni00l1O_dataout : STD_LOGIC; + SIGNAL wire_ni00l1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni00l1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni00l1OO_dataout : STD_LOGIC; + SIGNAL wire_ni00li0i_dataout : STD_LOGIC; + SIGNAL wire_ni00li0l_dataout : STD_LOGIC; + SIGNAL wire_ni00li0O_dataout : STD_LOGIC; + SIGNAL wire_ni00li1i_dataout : STD_LOGIC; + SIGNAL wire_ni00li1l_dataout : STD_LOGIC; + SIGNAL wire_ni00li1O_dataout : STD_LOGIC; + SIGNAL wire_ni00lii_dataout : STD_LOGIC; + SIGNAL wire_ni00liii_dataout : STD_LOGIC; + SIGNAL wire_ni00liil_dataout : STD_LOGIC; + SIGNAL wire_ni00lil_dataout : STD_LOGIC; + SIGNAL wire_ni00liO_dataout : STD_LOGIC; + SIGNAL wire_ni00ll0i_dataout : STD_LOGIC; + SIGNAL wire_ni00ll0l_dataout : STD_LOGIC; + SIGNAL wire_ni00ll0O_dataout : STD_LOGIC; + SIGNAL wire_ni00ll1l_dataout : STD_LOGIC; + SIGNAL wire_ni00ll1O_dataout : STD_LOGIC; + SIGNAL wire_ni00lli_dataout : STD_LOGIC; + SIGNAL wire_ni00lliO_dataout : STD_LOGIC; + SIGNAL wire_ni00lll_dataout : STD_LOGIC; + SIGNAL wire_ni00llli_dataout : STD_LOGIC; + SIGNAL wire_ni00llll_dataout : STD_LOGIC; + SIGNAL wire_ni00lllO_dataout : STD_LOGIC; + SIGNAL wire_ni00llO_dataout : STD_LOGIC; + SIGNAL wire_ni00llOi_dataout : STD_LOGIC; + SIGNAL wire_ni00llOl_dataout : STD_LOGIC; + SIGNAL wire_ni00llOO_dataout : STD_LOGIC; + SIGNAL wire_ni00lO0i_dataout : STD_LOGIC; + SIGNAL wire_ni00lO0l_dataout : STD_LOGIC; + SIGNAL wire_ni00lO1i_dataout : STD_LOGIC; + SIGNAL wire_ni00lO1l_dataout : STD_LOGIC; + SIGNAL wire_ni00lO1O_dataout : STD_LOGIC; + SIGNAL wire_ni00lOi_dataout : STD_LOGIC; + SIGNAL wire_ni00lOl_dataout : STD_LOGIC; + SIGNAL wire_ni00lOO_dataout : STD_LOGIC; + SIGNAL wire_ni00O0i_dataout : STD_LOGIC; + SIGNAL wire_ni00O0l_dataout : STD_LOGIC; + SIGNAL wire_ni00O0O_dataout : STD_LOGIC; + SIGNAL wire_ni00O1i_dataout : STD_LOGIC; + SIGNAL wire_ni00O1l_dataout : STD_LOGIC; + SIGNAL wire_ni00O1O_dataout : STD_LOGIC; + SIGNAL wire_ni00Oii_dataout : STD_LOGIC; + SIGNAL wire_ni00Oil_dataout : STD_LOGIC; + SIGNAL wire_ni00OiO_dataout : STD_LOGIC; + SIGNAL wire_ni00Oli_dataout : STD_LOGIC; + SIGNAL wire_ni00Oll_dataout : STD_LOGIC; + SIGNAL wire_ni00OlO_dataout : STD_LOGIC; + SIGNAL wire_ni00OOi_dataout : STD_LOGIC; + SIGNAL wire_ni00OOl_dataout : STD_LOGIC; + SIGNAL wire_ni00OOO_dataout : STD_LOGIC; + SIGNAL wire_ni0100li_dataout : STD_LOGIC; + SIGNAL wire_ni0100ll_dataout : STD_LOGIC; + SIGNAL wire_ni0100lO_dataout : STD_LOGIC; + SIGNAL wire_ni0100Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0100Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0100OO_dataout : STD_LOGIC; + SIGNAL wire_ni01010i_dataout : STD_LOGIC; + SIGNAL wire_ni01010l_dataout : STD_LOGIC; + SIGNAL wire_ni01010O_dataout : STD_LOGIC; + SIGNAL wire_ni01011i_dataout : STD_LOGIC; + SIGNAL wire_ni01011l_dataout : STD_LOGIC; + SIGNAL wire_ni01011O_dataout : STD_LOGIC; + SIGNAL wire_ni0101i_dataout : STD_LOGIC; + SIGNAL wire_ni0101ii_dataout : STD_LOGIC; + SIGNAL wire_ni0101il_dataout : STD_LOGIC; + SIGNAL wire_ni0101iO_dataout : STD_LOGIC; + SIGNAL wire_ni0101l_dataout : STD_LOGIC; + SIGNAL wire_ni0101li_dataout : STD_LOGIC; + SIGNAL wire_ni0101ll_dataout : STD_LOGIC; + SIGNAL wire_ni0101O_dataout : STD_LOGIC; + SIGNAL wire_ni010i0i_dataout : STD_LOGIC; + SIGNAL wire_ni010i0l_dataout : STD_LOGIC; + SIGNAL wire_ni010i0O_dataout : STD_LOGIC; + SIGNAL wire_ni010i1i_dataout : STD_LOGIC; + SIGNAL wire_ni010i1l_dataout : STD_LOGIC; + SIGNAL wire_ni010i1O_dataout : STD_LOGIC; + SIGNAL wire_ni010ii_dataout : STD_LOGIC; + SIGNAL wire_ni010ii_w_lg_dataout2517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni010iii_dataout : STD_LOGIC; + SIGNAL wire_ni010iil_dataout : STD_LOGIC; + SIGNAL wire_ni010iiO_dataout : STD_LOGIC; + SIGNAL wire_ni010il_dataout : STD_LOGIC; + SIGNAL wire_ni010ili_dataout : STD_LOGIC; + SIGNAL wire_ni010ill_dataout : STD_LOGIC; + SIGNAL wire_ni010ilO_dataout : STD_LOGIC; + SIGNAL wire_ni010iO_dataout : STD_LOGIC; + SIGNAL wire_ni010iOi_dataout : STD_LOGIC; + SIGNAL wire_ni010iOl_dataout : STD_LOGIC; + SIGNAL wire_ni010iOO_dataout : STD_LOGIC; + SIGNAL wire_ni010l0i_dataout : STD_LOGIC; + SIGNAL wire_ni010l0l_dataout : STD_LOGIC; + SIGNAL wire_ni010l0O_dataout : STD_LOGIC; + SIGNAL wire_ni010l1i_dataout : STD_LOGIC; + SIGNAL wire_ni010l1l_dataout : STD_LOGIC; + SIGNAL wire_ni010l1O_dataout : STD_LOGIC; + SIGNAL wire_ni010li_dataout : STD_LOGIC; + SIGNAL wire_ni010ll_dataout : STD_LOGIC; + SIGNAL wire_ni010O0l_dataout : STD_LOGIC; + SIGNAL wire_ni010O0O_dataout : STD_LOGIC; + SIGNAL wire_ni010Oii_dataout : STD_LOGIC; + SIGNAL wire_ni010Oil_dataout : STD_LOGIC; + SIGNAL wire_ni010OiO_dataout : STD_LOGIC; + SIGNAL wire_ni010Oli_dataout : STD_LOGIC; + SIGNAL wire_ni010Oll_dataout : STD_LOGIC; + SIGNAL wire_ni010OlO_dataout : STD_LOGIC; + SIGNAL wire_ni010OOi_dataout : STD_LOGIC; + SIGNAL wire_ni010OOl_dataout : STD_LOGIC; + SIGNAL wire_ni010OOO_dataout : STD_LOGIC; + SIGNAL wire_ni01100l_dataout : STD_LOGIC; + SIGNAL wire_ni01100O_dataout : STD_LOGIC; + SIGNAL wire_ni0110i_dataout : STD_LOGIC; + SIGNAL wire_ni0110ii_dataout : STD_LOGIC; + SIGNAL wire_ni0110il_dataout : STD_LOGIC; + SIGNAL wire_ni0110iO_dataout : STD_LOGIC; + SIGNAL wire_ni0110l_dataout : STD_LOGIC; + SIGNAL wire_ni0110li_dataout : STD_LOGIC; + SIGNAL wire_ni0110ll_dataout : STD_LOGIC; + SIGNAL wire_ni0110lO_dataout : STD_LOGIC; + SIGNAL wire_ni0110O_dataout : STD_LOGIC; + SIGNAL wire_ni0110Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0110Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0110OO_dataout : STD_LOGIC; + SIGNAL wire_ni01110i_dataout : STD_LOGIC; + SIGNAL wire_ni01110l_dataout : STD_LOGIC; + SIGNAL wire_ni01110O_dataout : STD_LOGIC; + SIGNAL wire_ni01111i_dataout : STD_LOGIC; + SIGNAL wire_ni01111l_dataout : STD_LOGIC; + SIGNAL wire_ni01111O_dataout : STD_LOGIC; + SIGNAL wire_ni0111i_dataout : STD_LOGIC; + SIGNAL wire_ni0111ii_dataout : STD_LOGIC; + SIGNAL wire_ni0111il_dataout : STD_LOGIC; + SIGNAL wire_ni0111iO_dataout : STD_LOGIC; + SIGNAL wire_ni0111l_dataout : STD_LOGIC; + SIGNAL wire_ni0111O_dataout : STD_LOGIC; + SIGNAL wire_ni011i0i_dataout : STD_LOGIC; + SIGNAL wire_ni011i0l_dataout : STD_LOGIC; + SIGNAL wire_ni011i0O_dataout : STD_LOGIC; + SIGNAL wire_ni011i1i_dataout : STD_LOGIC; + SIGNAL wire_ni011i1l_dataout : STD_LOGIC; + SIGNAL wire_ni011i1O_dataout : STD_LOGIC; + SIGNAL wire_ni011ii_dataout : STD_LOGIC; + SIGNAL wire_ni011iii_dataout : STD_LOGIC; + SIGNAL wire_ni011iil_dataout : STD_LOGIC; + SIGNAL wire_ni011iiO_dataout : STD_LOGIC; + SIGNAL wire_ni011il_dataout : STD_LOGIC; + SIGNAL wire_ni011ili_dataout : STD_LOGIC; + SIGNAL wire_ni011ill_dataout : STD_LOGIC; + SIGNAL wire_ni011ilO_dataout : STD_LOGIC; + SIGNAL wire_ni011iO_dataout : STD_LOGIC; + SIGNAL wire_ni011iOi_dataout : STD_LOGIC; + SIGNAL wire_ni011iOl_dataout : STD_LOGIC; + SIGNAL wire_ni011iOO_dataout : STD_LOGIC; + SIGNAL wire_ni011l1i_dataout : STD_LOGIC; + SIGNAL wire_ni011li_dataout : STD_LOGIC; + SIGNAL wire_ni011ll_dataout : STD_LOGIC; + SIGNAL wire_ni011lO_dataout : STD_LOGIC; + SIGNAL wire_ni011lOO_dataout : STD_LOGIC; + SIGNAL wire_ni011O0i_dataout : STD_LOGIC; + SIGNAL wire_ni011O0l_dataout : STD_LOGIC; + SIGNAL wire_ni011O0O_dataout : STD_LOGIC; + SIGNAL wire_ni011O1i_dataout : STD_LOGIC; + SIGNAL wire_ni011O1l_dataout : STD_LOGIC; + SIGNAL wire_ni011O1O_dataout : STD_LOGIC; + SIGNAL wire_ni011Oi_dataout : STD_LOGIC; + SIGNAL wire_ni011Oii_dataout : STD_LOGIC; + SIGNAL wire_ni011Oil_dataout : STD_LOGIC; + SIGNAL wire_ni011OiO_dataout : STD_LOGIC; + SIGNAL wire_ni011Ol_dataout : STD_LOGIC; + SIGNAL wire_ni011Oli_dataout : STD_LOGIC; + SIGNAL wire_ni011Oll_dataout : STD_LOGIC; + SIGNAL wire_ni011OlO_dataout : STD_LOGIC; + SIGNAL wire_ni011OO_dataout : STD_LOGIC; + SIGNAL wire_ni011OOi_dataout : STD_LOGIC; + SIGNAL wire_ni011OOl_dataout : STD_LOGIC; + SIGNAL wire_ni011OOO_dataout : STD_LOGIC; + SIGNAL wire_ni01i01i_dataout : STD_LOGIC; + SIGNAL wire_ni01i0OO_dataout : STD_LOGIC; + SIGNAL wire_ni01i10i_dataout : STD_LOGIC; + SIGNAL wire_ni01i10l_dataout : STD_LOGIC; + SIGNAL wire_ni01i10O_dataout : STD_LOGIC; + SIGNAL wire_ni01i11i_dataout : STD_LOGIC; + SIGNAL wire_ni01i11l_dataout : STD_LOGIC; + SIGNAL wire_ni01i11O_dataout : STD_LOGIC; + SIGNAL wire_ni01i1ii_dataout : STD_LOGIC; + SIGNAL wire_ni01i1il_dataout : STD_LOGIC; + SIGNAL wire_ni01i1iO_dataout : STD_LOGIC; + SIGNAL wire_ni01i1li_dataout : STD_LOGIC; + SIGNAL wire_ni01i1ll_dataout : STD_LOGIC; + SIGNAL wire_ni01i1lO_dataout : STD_LOGIC; + SIGNAL wire_ni01i1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni01i1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni01i1OO_dataout : STD_LOGIC; + SIGNAL wire_ni01ii0i_dataout : STD_LOGIC; + SIGNAL wire_ni01ii0l_dataout : STD_LOGIC; + SIGNAL wire_ni01ii0O_dataout : STD_LOGIC; + SIGNAL wire_ni01ii1i_dataout : STD_LOGIC; + SIGNAL wire_ni01ii1l_dataout : STD_LOGIC; + SIGNAL wire_ni01ii1O_dataout : STD_LOGIC; + SIGNAL wire_ni01iiii_dataout : STD_LOGIC; + SIGNAL wire_ni01iiil_dataout : STD_LOGIC; + SIGNAL wire_ni01iiiO_dataout : STD_LOGIC; + SIGNAL wire_ni01iili_dataout : STD_LOGIC; + SIGNAL wire_ni01iill_dataout : STD_LOGIC; + SIGNAL wire_ni01iilO_dataout : STD_LOGIC; + SIGNAL wire_ni01iiOi_dataout : STD_LOGIC; + SIGNAL wire_ni01iiOl_dataout : STD_LOGIC; + SIGNAL wire_ni01iiOO_dataout : STD_LOGIC; + SIGNAL wire_ni01il0i_dataout : STD_LOGIC; + SIGNAL wire_ni01il0l_dataout : STD_LOGIC; + SIGNAL wire_ni01il0O_dataout : STD_LOGIC; + SIGNAL wire_ni01il1i_dataout : STD_LOGIC; + SIGNAL wire_ni01il1l_dataout : STD_LOGIC; + SIGNAL wire_ni01il1O_dataout : STD_LOGIC; + SIGNAL wire_ni01ilii_dataout : STD_LOGIC; + SIGNAL wire_ni01ilil_dataout : STD_LOGIC; + SIGNAL wire_ni01iliO_dataout : STD_LOGIC; + SIGNAL wire_ni01ill_dataout : STD_LOGIC; + SIGNAL wire_ni01ill_w_lg_w_lg_dataout2483w2484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01ill_w_lg_w_lg_dataout2485w2486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01ill_w_lg_dataout2483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01ill_w_lg_dataout2485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni01illi_dataout : STD_LOGIC; + SIGNAL wire_ni01illl_dataout : STD_LOGIC; + SIGNAL wire_ni01ilO_dataout : STD_LOGIC; + SIGNAL wire_ni01iOi_dataout : STD_LOGIC; + SIGNAL wire_ni01iOli_dataout : STD_LOGIC; + SIGNAL wire_ni01iOll_dataout : STD_LOGIC; + SIGNAL wire_ni01iOlO_dataout : STD_LOGIC; + SIGNAL wire_ni01iOOi_dataout : STD_LOGIC; + SIGNAL wire_ni01iOOl_dataout : STD_LOGIC; + SIGNAL wire_ni01iOOO_dataout : STD_LOGIC; + SIGNAL wire_ni01l00i_dataout : STD_LOGIC; + SIGNAL wire_ni01l00l_dataout : STD_LOGIC; + SIGNAL wire_ni01l00O_dataout : STD_LOGIC; + SIGNAL wire_ni01l01i_dataout : STD_LOGIC; + SIGNAL wire_ni01l01l_dataout : STD_LOGIC; + SIGNAL wire_ni01l01O_dataout : STD_LOGIC; + SIGNAL wire_ni01l10i_dataout : STD_LOGIC; + SIGNAL wire_ni01l10l_dataout : STD_LOGIC; + SIGNAL wire_ni01l10O_dataout : STD_LOGIC; + SIGNAL wire_ni01l11i_dataout : STD_LOGIC; + SIGNAL wire_ni01l11l_dataout : STD_LOGIC; + SIGNAL wire_ni01l11O_dataout : STD_LOGIC; + SIGNAL wire_ni01l1ii_dataout : STD_LOGIC; + SIGNAL wire_ni01l1il_dataout : STD_LOGIC; + SIGNAL wire_ni01l1iO_dataout : STD_LOGIC; + SIGNAL wire_ni01l1l_dataout : STD_LOGIC; + SIGNAL wire_ni01l1li_dataout : STD_LOGIC; + SIGNAL wire_ni01l1ll_dataout : STD_LOGIC; + SIGNAL wire_ni01l1lO_dataout : STD_LOGIC; + SIGNAL wire_ni01l1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni01l1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni01l1OO_dataout : STD_LOGIC; + SIGNAL wire_ni01li0l_dataout : STD_LOGIC; + SIGNAL wire_ni01li0O_dataout : STD_LOGIC; + SIGNAL wire_ni01liii_dataout : STD_LOGIC; + SIGNAL wire_ni01liil_dataout : STD_LOGIC; + SIGNAL wire_ni01liiO_dataout : STD_LOGIC; + SIGNAL wire_ni01lili_dataout : STD_LOGIC; + SIGNAL wire_ni01lill_dataout : STD_LOGIC; + SIGNAL wire_ni01lilO_dataout : STD_LOGIC; + SIGNAL wire_ni01liOi_dataout : STD_LOGIC; + SIGNAL wire_ni01liOl_dataout : STD_LOGIC; + SIGNAL wire_ni01liOO_dataout : STD_LOGIC; + SIGNAL wire_ni01ll0i_dataout : STD_LOGIC; + SIGNAL wire_ni01ll0l_dataout : STD_LOGIC; + SIGNAL wire_ni01ll0O_dataout : STD_LOGIC; + SIGNAL wire_ni01ll1i_dataout : STD_LOGIC; + SIGNAL wire_ni01ll1l_dataout : STD_LOGIC; + SIGNAL wire_ni01ll1O_dataout : STD_LOGIC; + SIGNAL wire_ni01llii_dataout : STD_LOGIC; + SIGNAL wire_ni01llil_dataout : STD_LOGIC; + SIGNAL wire_ni01lliO_dataout : STD_LOGIC; + SIGNAL wire_ni01llli_dataout : STD_LOGIC; + SIGNAL wire_ni01llll_dataout : STD_LOGIC; + SIGNAL wire_ni01lllO_dataout : STD_LOGIC; + SIGNAL wire_ni01llOi_dataout : STD_LOGIC; + SIGNAL wire_ni01llOl_dataout : STD_LOGIC; + SIGNAL wire_ni01llOO_dataout : STD_LOGIC; + SIGNAL wire_ni01lO1i_dataout : STD_LOGIC; + SIGNAL wire_ni01lOli_dataout : STD_LOGIC; + SIGNAL wire_ni01lOll_dataout : STD_LOGIC; + SIGNAL wire_ni01lOlO_dataout : STD_LOGIC; + SIGNAL wire_ni01lOO_dataout : STD_LOGIC; + SIGNAL wire_ni01lOOi_dataout : STD_LOGIC; + SIGNAL wire_ni01lOOl_dataout : STD_LOGIC; + SIGNAL wire_ni01O0i_dataout : STD_LOGIC; + SIGNAL wire_ni01O0l_dataout : STD_LOGIC; + SIGNAL wire_ni01O0O_dataout : STD_LOGIC; + SIGNAL wire_ni01O10i_dataout : STD_LOGIC; + SIGNAL wire_ni01O10l_dataout : STD_LOGIC; + SIGNAL wire_ni01O10O_dataout : STD_LOGIC; + SIGNAL wire_ni01O11l_dataout : STD_LOGIC; + SIGNAL wire_ni01O11O_dataout : STD_LOGIC; + SIGNAL wire_ni01O1i_dataout : STD_LOGIC; + SIGNAL wire_ni01O1ii_dataout : STD_LOGIC; + SIGNAL wire_ni01O1il_dataout : STD_LOGIC; + SIGNAL wire_ni01O1iO_dataout : STD_LOGIC; + SIGNAL wire_ni01O1l_dataout : STD_LOGIC; + SIGNAL wire_ni01O1li_dataout : STD_LOGIC; + SIGNAL wire_ni01O1ll_dataout : STD_LOGIC; + SIGNAL wire_ni01O1lO_dataout : STD_LOGIC; + SIGNAL wire_ni01O1O_dataout : STD_LOGIC; + SIGNAL wire_ni01O1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni01Oi0l_dataout : STD_LOGIC; + SIGNAL wire_ni01Oi0O_dataout : STD_LOGIC; + SIGNAL wire_ni01Oii_dataout : STD_LOGIC; + SIGNAL wire_ni01Oiii_dataout : STD_LOGIC; + SIGNAL wire_ni01Oiil_dataout : STD_LOGIC; + SIGNAL wire_ni01OiiO_dataout : STD_LOGIC; + SIGNAL wire_ni01Oili_dataout : STD_LOGIC; + SIGNAL wire_ni01Oill_dataout : STD_LOGIC; + SIGNAL wire_ni01OilO_dataout : STD_LOGIC; + SIGNAL wire_ni01OiOi_dataout : STD_LOGIC; + SIGNAL wire_ni01OiOl_dataout : STD_LOGIC; + SIGNAL wire_ni01OiOO_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol0i_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol0l_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol0O_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol1i_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol1l_dataout : STD_LOGIC; + SIGNAL wire_ni01Ol1O_dataout : STD_LOGIC; + SIGNAL wire_ni01Olii_dataout : STD_LOGIC; + SIGNAL wire_ni01Olil_dataout : STD_LOGIC; + SIGNAL wire_ni01OliO_dataout : STD_LOGIC; + SIGNAL wire_ni01Olli_dataout : STD_LOGIC; + SIGNAL wire_ni01Olll_dataout : STD_LOGIC; + SIGNAL wire_ni01OllO_dataout : STD_LOGIC; + SIGNAL wire_ni01OlOi_dataout : STD_LOGIC; + SIGNAL wire_ni01OlOl_dataout : STD_LOGIC; + SIGNAL wire_ni01OlOO_dataout : STD_LOGIC; + SIGNAL wire_ni01OO1i_dataout : STD_LOGIC; + SIGNAL wire_ni01OOl_dataout : STD_LOGIC; + SIGNAL wire_ni01OOlO_dataout : STD_LOGIC; + SIGNAL wire_ni01OOO_dataout : STD_LOGIC; + SIGNAL wire_ni01OOOi_dataout : STD_LOGIC; + SIGNAL wire_ni01OOOl_dataout : STD_LOGIC; + SIGNAL wire_ni01OOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0i00i_dataout : STD_LOGIC; + SIGNAL wire_ni0i00l_dataout : STD_LOGIC; + SIGNAL wire_ni0i00O_dataout : STD_LOGIC; + SIGNAL wire_ni0i01i_dataout : STD_LOGIC; + SIGNAL wire_ni0i01l_dataout : STD_LOGIC; + SIGNAL wire_ni0i01O_dataout : STD_LOGIC; + SIGNAL wire_ni0i0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0i0iii_dataout : STD_LOGIC; + SIGNAL wire_ni0i0iil_dataout : STD_LOGIC; + SIGNAL wire_ni0i0iiO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0il_dataout : STD_LOGIC; + SIGNAL wire_ni0i0ili_dataout : STD_LOGIC; + SIGNAL wire_ni0i0ill_dataout : STD_LOGIC; + SIGNAL wire_ni0i0ilO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0iOi_dataout : STD_LOGIC; + SIGNAL wire_ni0i0iOl_dataout : STD_LOGIC; + SIGNAL wire_ni0i0iOO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l0i_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l0O_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l1i_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l1l_dataout : STD_LOGIC; + SIGNAL wire_ni0i0l1O_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lii_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lil_dataout : STD_LOGIC; + SIGNAL wire_ni0i0liO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lli_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lll_dataout : STD_LOGIC; + SIGNAL wire_ni0i0llO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lOi_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0i0lOO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0O0i_dataout : STD_LOGIC; + SIGNAL wire_ni0i0O0l_dataout : STD_LOGIC; + SIGNAL wire_ni0i0O0O_dataout : STD_LOGIC; + SIGNAL wire_ni0i0O1i_dataout : STD_LOGIC; + SIGNAL wire_ni0i0O1l_dataout : STD_LOGIC; + SIGNAL wire_ni0i0O1O_dataout : STD_LOGIC; + SIGNAL wire_ni0i0Oii_dataout : STD_LOGIC; + SIGNAL wire_ni0i0Oil_dataout : STD_LOGIC; + SIGNAL wire_ni0i0OiO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0Oli_dataout : STD_LOGIC; + SIGNAL wire_ni0i0Oll_dataout : STD_LOGIC; + SIGNAL wire_ni0i0OlO_dataout : STD_LOGIC; + SIGNAL wire_ni0i0OOi_dataout : STD_LOGIC; + SIGNAL wire_ni0i0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni0i0OOO_dataout : STD_LOGIC; + SIGNAL wire_ni0i10i_dataout : STD_LOGIC; + SIGNAL wire_ni0i10l_dataout : STD_LOGIC; + SIGNAL wire_ni0i10O_dataout : STD_LOGIC; + SIGNAL wire_ni0i110O_dataout : STD_LOGIC; + SIGNAL wire_ni0i11i_dataout : STD_LOGIC; + SIGNAL wire_ni0i11ii_dataout : STD_LOGIC; + SIGNAL wire_ni0i11il_dataout : STD_LOGIC; + SIGNAL wire_ni0i11iO_dataout : STD_LOGIC; + SIGNAL wire_ni0i11l_dataout : STD_LOGIC; + SIGNAL wire_ni0i11lO_dataout : STD_LOGIC; + SIGNAL wire_ni0i11O_dataout : STD_LOGIC; + SIGNAL wire_ni0i11Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0i1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0i1il_dataout : STD_LOGIC; + SIGNAL wire_ni0i1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0i1li_dataout : STD_LOGIC; + SIGNAL wire_ni0i1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0i1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0i1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0ii00i_dataout : STD_LOGIC; + SIGNAL wire_ni0ii00l_dataout : STD_LOGIC; + SIGNAL wire_ni0ii00O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii01i_dataout : STD_LOGIC; + SIGNAL wire_ni0ii01l_dataout : STD_LOGIC; + SIGNAL wire_ni0ii01O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0i_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0il_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0l_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0li_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0ii0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0ii10i_dataout : STD_LOGIC; + SIGNAL wire_ni0ii10l_dataout : STD_LOGIC; + SIGNAL wire_ni0ii10O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii11i_dataout : STD_LOGIC; + SIGNAL wire_ni0ii11l_dataout : STD_LOGIC; + SIGNAL wire_ni0ii11O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1i_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1il_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1l_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1li_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1O_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0ii1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0iii0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iii0l_dataout : STD_LOGIC; + SIGNAL wire_ni0iii0O_dataout : STD_LOGIC; + SIGNAL wire_ni0iii1i_dataout : STD_LOGIC; + SIGNAL wire_ni0iii1l_dataout : STD_LOGIC; + SIGNAL wire_ni0iii1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iiii_dataout : STD_LOGIC; + SIGNAL wire_ni0iiiii_dataout : STD_LOGIC; + SIGNAL wire_ni0iiiil_dataout : STD_LOGIC; + SIGNAL wire_ni0iiiiO_dataout : STD_LOGIC; + SIGNAL wire_ni0iiil_dataout : STD_LOGIC; + SIGNAL wire_ni0iiili_dataout : STD_LOGIC; + SIGNAL wire_ni0iiill_dataout : STD_LOGIC; + SIGNAL wire_ni0iiilO_dataout : STD_LOGIC; + SIGNAL wire_ni0iiiO_dataout : STD_LOGIC; + SIGNAL wire_ni0iiiOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iiiOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iiiOO_dataout : STD_LOGIC; + SIGNAL wire_ni0iil0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iil0l_dataout : STD_LOGIC; + SIGNAL wire_ni0iil0O_dataout : STD_LOGIC; + SIGNAL wire_ni0iil1i_dataout : STD_LOGIC; + SIGNAL wire_ni0iil1l_dataout : STD_LOGIC; + SIGNAL wire_ni0iil1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iili_dataout : STD_LOGIC; + SIGNAL wire_ni0iilii_dataout : STD_LOGIC; + SIGNAL wire_ni0iilil_dataout : STD_LOGIC; + SIGNAL wire_ni0iiliO_dataout : STD_LOGIC; + SIGNAL wire_ni0iill_dataout : STD_LOGIC; + SIGNAL wire_ni0iilli_dataout : STD_LOGIC; + SIGNAL wire_ni0iilll_dataout : STD_LOGIC; + SIGNAL wire_ni0iillO_dataout : STD_LOGIC; + SIGNAL wire_ni0iilO_dataout : STD_LOGIC; + SIGNAL wire_ni0iilOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iilOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iilOO_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0iiO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOii_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOil_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOli_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOll_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOO_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iiOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0il00i_dataout : STD_LOGIC; + SIGNAL wire_ni0il00l_dataout : STD_LOGIC; + SIGNAL wire_ni0il00O_dataout : STD_LOGIC; + SIGNAL wire_ni0il01i_dataout : STD_LOGIC; + SIGNAL wire_ni0il01l_dataout : STD_LOGIC; + SIGNAL wire_ni0il01O_dataout : STD_LOGIC; + SIGNAL wire_ni0il0i_dataout : STD_LOGIC; + SIGNAL wire_ni0il0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0il0il_dataout : STD_LOGIC; + SIGNAL wire_ni0il0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0il0l_dataout : STD_LOGIC; + SIGNAL wire_ni0il0li_dataout : STD_LOGIC; + SIGNAL wire_ni0il0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0il0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0il0O_dataout : STD_LOGIC; + SIGNAL wire_ni0il0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0il0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0il0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0il10i_dataout : STD_LOGIC; + SIGNAL wire_ni0il10l_dataout : STD_LOGIC; + SIGNAL wire_ni0il10O_dataout : STD_LOGIC; + SIGNAL wire_ni0il11i_dataout : STD_LOGIC; + SIGNAL wire_ni0il11l_dataout : STD_LOGIC; + SIGNAL wire_ni0il11O_dataout : STD_LOGIC; + SIGNAL wire_ni0il1i_dataout : STD_LOGIC; + SIGNAL wire_ni0il1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0il1il_dataout : STD_LOGIC; + SIGNAL wire_ni0il1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0il1l_dataout : STD_LOGIC; + SIGNAL wire_ni0il1li_dataout : STD_LOGIC; + SIGNAL wire_ni0il1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0il1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0il1O_dataout : STD_LOGIC; + SIGNAL wire_ni0il1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0il1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0il1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0ili0i_dataout : STD_LOGIC; + SIGNAL wire_ni0ili0l_dataout : STD_LOGIC; + SIGNAL wire_ni0ili0O_dataout : STD_LOGIC; + SIGNAL wire_ni0ili1i_dataout : STD_LOGIC; + SIGNAL wire_ni0ili1l_dataout : STD_LOGIC; + SIGNAL wire_ni0ili1O_dataout : STD_LOGIC; + SIGNAL wire_ni0ilii_dataout : STD_LOGIC; + SIGNAL wire_ni0iliii_dataout : STD_LOGIC; + SIGNAL wire_ni0iliil_dataout : STD_LOGIC; + SIGNAL wire_ni0iliiO_dataout : STD_LOGIC; + SIGNAL wire_ni0ilil_dataout : STD_LOGIC; + SIGNAL wire_ni0ilili_dataout : STD_LOGIC; + SIGNAL wire_ni0ilill_dataout : STD_LOGIC; + SIGNAL wire_ni0ililO_dataout : STD_LOGIC; + SIGNAL wire_ni0iliO_dataout : STD_LOGIC; + SIGNAL wire_ni0iliOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iliOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iliOO_dataout : STD_LOGIC; + SIGNAL wire_ni0ill0i_dataout : STD_LOGIC; + SIGNAL wire_ni0ill0l_dataout : STD_LOGIC; + SIGNAL wire_ni0ill0O_dataout : STD_LOGIC; + SIGNAL wire_ni0ill1i_dataout : STD_LOGIC; + SIGNAL wire_ni0ill1l_dataout : STD_LOGIC; + SIGNAL wire_ni0ill1O_dataout : STD_LOGIC; + SIGNAL wire_ni0illi_dataout : STD_LOGIC; + SIGNAL wire_ni0illii_dataout : STD_LOGIC; + SIGNAL wire_ni0illil_dataout : STD_LOGIC; + SIGNAL wire_ni0illiO_dataout : STD_LOGIC; + SIGNAL wire_ni0illl_dataout : STD_LOGIC; + SIGNAL wire_ni0illli_dataout : STD_LOGIC; + SIGNAL wire_ni0illll_dataout : STD_LOGIC; + SIGNAL wire_ni0illlO_dataout : STD_LOGIC; + SIGNAL wire_ni0illO_dataout : STD_LOGIC; + SIGNAL wire_ni0illOi_dataout : STD_LOGIC; + SIGNAL wire_ni0illOl_dataout : STD_LOGIC; + SIGNAL wire_ni0illOO_dataout : STD_LOGIC; + SIGNAL wire_ni0ilO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0ilO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0ilO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0ilO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0ilO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0ilO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOii_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOil_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOl_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOli_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOll_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOO_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0ilOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0iO00i_dataout : STD_LOGIC; + SIGNAL wire_ni0iO00l_dataout : STD_LOGIC; + SIGNAL wire_ni0iO00O_dataout : STD_LOGIC; + SIGNAL wire_ni0iO01i_dataout : STD_LOGIC; + SIGNAL wire_ni0iO01l_dataout : STD_LOGIC; + SIGNAL wire_ni0iO01O_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0il_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0li_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0iO0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0iO10i_dataout : STD_LOGIC; + SIGNAL wire_ni0iO10l_dataout : STD_LOGIC; + SIGNAL wire_ni0iO10O_dataout : STD_LOGIC; + SIGNAL wire_ni0iO11i_dataout : STD_LOGIC; + SIGNAL wire_ni0iO11l_dataout : STD_LOGIC; + SIGNAL wire_ni0iO11O_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1il_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1li_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0iO1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOi0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iOi0l_dataout : STD_LOGIC; + SIGNAL wire_ni0iOi0O_dataout : STD_LOGIC; + SIGNAL wire_ni0iOi1i_dataout : STD_LOGIC; + SIGNAL wire_ni0iOi1l_dataout : STD_LOGIC; + SIGNAL wire_ni0iOi1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iOii_dataout : STD_LOGIC; + SIGNAL wire_ni0iOiii_dataout : STD_LOGIC; + SIGNAL wire_ni0iOiil_dataout : STD_LOGIC; + SIGNAL wire_ni0iOiiO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOil_dataout : STD_LOGIC; + SIGNAL wire_ni0iOili_dataout : STD_LOGIC; + SIGNAL wire_ni0iOill_dataout : STD_LOGIC; + SIGNAL wire_ni0iOilO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOiOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iOiOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iOiOO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl0l_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl0O_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl1i_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl1l_dataout : STD_LOGIC; + SIGNAL wire_ni0iOl1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iOli_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlii_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlil_dataout : STD_LOGIC; + SIGNAL wire_ni0iOliO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOll_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlli_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlll_dataout : STD_LOGIC; + SIGNAL wire_ni0iOllO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iOlOO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0iOO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOii_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOil_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOli_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOll_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0iOOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l000i_dataout : STD_LOGIC; + SIGNAL wire_ni0l000l_dataout : STD_LOGIC; + SIGNAL wire_ni0l000O_dataout : STD_LOGIC; + SIGNAL wire_ni0l001i_dataout : STD_LOGIC; + SIGNAL wire_ni0l001l_dataout : STD_LOGIC; + SIGNAL wire_ni0l001O_dataout : STD_LOGIC; + SIGNAL wire_ni0l00ii_dataout : STD_LOGIC; + SIGNAL wire_ni0l00il_dataout : STD_LOGIC; + SIGNAL wire_ni0l00iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l00li_dataout : STD_LOGIC; + SIGNAL wire_ni0l00ll_dataout : STD_LOGIC; + SIGNAL wire_ni0l00lO_dataout : STD_LOGIC; + SIGNAL wire_ni0l00Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0l00Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0l00OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l010i_dataout : STD_LOGIC; + SIGNAL wire_ni0l010l_dataout : STD_LOGIC; + SIGNAL wire_ni0l010O_dataout : STD_LOGIC; + SIGNAL wire_ni0l011i_dataout : STD_LOGIC; + SIGNAL wire_ni0l011l_dataout : STD_LOGIC; + SIGNAL wire_ni0l011O_dataout : STD_LOGIC; + SIGNAL wire_ni0l01i_dataout : STD_LOGIC; + SIGNAL wire_ni0l01ii_dataout : STD_LOGIC; + SIGNAL wire_ni0l01il_dataout : STD_LOGIC; + SIGNAL wire_ni0l01iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l01li_dataout : STD_LOGIC; + SIGNAL wire_ni0l01ll_dataout : STD_LOGIC; + SIGNAL wire_ni0l01lO_dataout : STD_LOGIC; + SIGNAL wire_ni0l01O_dataout : STD_LOGIC; + SIGNAL wire_ni0l01Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0l01Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0l01OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i1i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i1l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0i1O_dataout : STD_LOGIC; + SIGNAL wire_ni0l0iii_dataout : STD_LOGIC; + SIGNAL wire_ni0l0iil_dataout : STD_LOGIC; + SIGNAL wire_ni0l0iiO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0ili_dataout : STD_LOGIC; + SIGNAL wire_ni0l0ill_dataout : STD_LOGIC; + SIGNAL wire_ni0l0ilO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0iOi_dataout : STD_LOGIC; + SIGNAL wire_ni0l0iOl_dataout : STD_LOGIC; + SIGNAL wire_ni0l0iOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l1i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l1l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0l1O_dataout : STD_LOGIC; + SIGNAL wire_ni0l0li_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lii_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lil_dataout : STD_LOGIC; + SIGNAL wire_ni0l0liO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lli_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lll_dataout : STD_LOGIC; + SIGNAL wire_ni0l0llO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lOi_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0l0lOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O1i_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O1l_dataout : STD_LOGIC; + SIGNAL wire_ni0l0O1O_dataout : STD_LOGIC; + SIGNAL wire_ni0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0l0Oii_dataout : STD_LOGIC; + SIGNAL wire_ni0l0Oil_dataout : STD_LOGIC; + SIGNAL wire_ni0l0OiO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0l0Oli_dataout : STD_LOGIC; + SIGNAL wire_ni0l0Oll_dataout : STD_LOGIC; + SIGNAL wire_ni0l0OlO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l0OOi_dataout : STD_LOGIC; + SIGNAL wire_ni0l0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni0l0OOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l100i_dataout : STD_LOGIC; + SIGNAL wire_ni0l100l_dataout : STD_LOGIC; + SIGNAL wire_ni0l100O_dataout : STD_LOGIC; + SIGNAL wire_ni0l101i_dataout : STD_LOGIC; + SIGNAL wire_ni0l101l_dataout : STD_LOGIC; + SIGNAL wire_ni0l101O_dataout : STD_LOGIC; + SIGNAL wire_ni0l10i_dataout : STD_LOGIC; + SIGNAL wire_ni0l10ii_dataout : STD_LOGIC; + SIGNAL wire_ni0l10il_dataout : STD_LOGIC; + SIGNAL wire_ni0l10iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l10l_dataout : STD_LOGIC; + SIGNAL wire_ni0l10li_dataout : STD_LOGIC; + SIGNAL wire_ni0l10ll_dataout : STD_LOGIC; + SIGNAL wire_ni0l10lO_dataout : STD_LOGIC; + SIGNAL wire_ni0l10O_dataout : STD_LOGIC; + SIGNAL wire_ni0l10Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0l10Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0l10OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l110i_dataout : STD_LOGIC; + SIGNAL wire_ni0l110l_dataout : STD_LOGIC; + SIGNAL wire_ni0l110O_dataout : STD_LOGIC; + SIGNAL wire_ni0l111i_dataout : STD_LOGIC; + SIGNAL wire_ni0l111l_dataout : STD_LOGIC; + SIGNAL wire_ni0l111O_dataout : STD_LOGIC; + SIGNAL wire_ni0l11i_dataout : STD_LOGIC; + SIGNAL wire_ni0l11ii_dataout : STD_LOGIC; + SIGNAL wire_ni0l11il_dataout : STD_LOGIC; + SIGNAL wire_ni0l11iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l11l_dataout : STD_LOGIC; + SIGNAL wire_ni0l11li_dataout : STD_LOGIC; + SIGNAL wire_ni0l11ll_dataout : STD_LOGIC; + SIGNAL wire_ni0l11lO_dataout : STD_LOGIC; + SIGNAL wire_ni0l11O_dataout : STD_LOGIC; + SIGNAL wire_ni0l11Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0l11Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0l11OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i1i_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i1l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1i1O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0l1iii_dataout : STD_LOGIC; + SIGNAL wire_ni0l1iil_dataout : STD_LOGIC; + SIGNAL wire_ni0l1iiO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1il_dataout : STD_LOGIC; + SIGNAL wire_ni0l1ili_dataout : STD_LOGIC; + SIGNAL wire_ni0l1ill_dataout : STD_LOGIC; + SIGNAL wire_ni0l1ilO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1iOi_dataout : STD_LOGIC; + SIGNAL wire_ni0l1iOl_dataout : STD_LOGIC; + SIGNAL wire_ni0l1iOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1l0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l1l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1l0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1l1i_dataout : STD_LOGIC; + SIGNAL wire_ni0l1l1l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1l1O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1li_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lii_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lil_dataout : STD_LOGIC; + SIGNAL wire_ni0l1liO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lli_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lll_dataout : STD_LOGIC; + SIGNAL wire_ni0l1llO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lOi_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0l1lOO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O0i_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O0l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O0O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O1i_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O1l_dataout : STD_LOGIC; + SIGNAL wire_ni0l1O1O_dataout : STD_LOGIC; + SIGNAL wire_ni0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0l1Oii_dataout : STD_LOGIC; + SIGNAL wire_ni0l1Oil_dataout : STD_LOGIC; + SIGNAL wire_ni0l1OiO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1Oli_dataout : STD_LOGIC; + SIGNAL wire_ni0l1Oll_dataout : STD_LOGIC; + SIGNAL wire_ni0l1OlO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0l1OOi_dataout : STD_LOGIC; + SIGNAL wire_ni0l1OOl_dataout : STD_LOGIC; + SIGNAL wire_ni0l1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni0li00i_dataout : STD_LOGIC; + SIGNAL wire_ni0li00l_dataout : STD_LOGIC; + SIGNAL wire_ni0li00O_dataout : STD_LOGIC; + SIGNAL wire_ni0li01i_dataout : STD_LOGIC; + SIGNAL wire_ni0li01l_dataout : STD_LOGIC; + SIGNAL wire_ni0li01O_dataout : STD_LOGIC; + SIGNAL wire_ni0li0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0li0il_dataout : STD_LOGIC; + SIGNAL wire_ni0li0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0li0li_dataout : STD_LOGIC; + SIGNAL wire_ni0li0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0li0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0li0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0li0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0li0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0li10i_dataout : STD_LOGIC; + SIGNAL wire_ni0li10l_dataout : STD_LOGIC; + SIGNAL wire_ni0li10O_dataout : STD_LOGIC; + SIGNAL wire_ni0li11i_dataout : STD_LOGIC; + SIGNAL wire_ni0li11l_dataout : STD_LOGIC; + SIGNAL wire_ni0li11O_dataout : STD_LOGIC; + SIGNAL wire_ni0li1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0li1il_dataout : STD_LOGIC; + SIGNAL wire_ni0li1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0li1li_dataout : STD_LOGIC; + SIGNAL wire_ni0li1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0li1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0li1O_dataout : STD_LOGIC; + SIGNAL wire_ni0li1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0li1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0li1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0lii0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lii0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lii0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lii1i_dataout : STD_LOGIC; + SIGNAL wire_ni0lii1l_dataout : STD_LOGIC; + SIGNAL wire_ni0lii1O_dataout : STD_LOGIC; + SIGNAL wire_ni0liiii_dataout : STD_LOGIC; + SIGNAL wire_ni0liiil_dataout : STD_LOGIC; + SIGNAL wire_ni0liiiO_dataout : STD_LOGIC; + SIGNAL wire_ni0liili_dataout : STD_LOGIC; + SIGNAL wire_ni0liill_dataout : STD_LOGIC; + SIGNAL wire_ni0liilO_dataout : STD_LOGIC; + SIGNAL wire_ni0liiOi_dataout : STD_LOGIC; + SIGNAL wire_ni0liiOl_dataout : STD_LOGIC; + SIGNAL wire_ni0liiOO_dataout : STD_LOGIC; + SIGNAL wire_ni0lil0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lil0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lil0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lil1i_dataout : STD_LOGIC; + SIGNAL wire_ni0lil1l_dataout : STD_LOGIC; + SIGNAL wire_ni0lil1O_dataout : STD_LOGIC; + SIGNAL wire_ni0lilii_dataout : STD_LOGIC; + SIGNAL wire_ni0lilil_dataout : STD_LOGIC; + SIGNAL wire_ni0liliO_dataout : STD_LOGIC; + SIGNAL wire_ni0lilli_dataout : STD_LOGIC; + SIGNAL wire_ni0lilll_dataout : STD_LOGIC; + SIGNAL wire_ni0lillO_dataout : STD_LOGIC; + SIGNAL wire_ni0lilOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lilOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lilOO_dataout : STD_LOGIC; + SIGNAL wire_ni0liOl_dataout : STD_LOGIC; + SIGNAL wire_ni0liOO_dataout : STD_LOGIC; + SIGNAL wire_ni0liOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0liOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0ll00i_dataout : STD_LOGIC; + SIGNAL wire_ni0ll00l_dataout : STD_LOGIC; + SIGNAL wire_ni0ll00O_dataout : STD_LOGIC; + SIGNAL wire_ni0ll01i_dataout : STD_LOGIC; + SIGNAL wire_ni0ll01l_dataout : STD_LOGIC; + SIGNAL wire_ni0ll01O_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0i_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0il_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0l_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0li_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0O_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0ll0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0ll10i_dataout : STD_LOGIC; + SIGNAL wire_ni0ll10l_dataout : STD_LOGIC; + SIGNAL wire_ni0ll10O_dataout : STD_LOGIC; + SIGNAL wire_ni0ll11i_dataout : STD_LOGIC; + SIGNAL wire_ni0ll11l_dataout : STD_LOGIC; + SIGNAL wire_ni0ll11O_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1i_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1il_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1l_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1li_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1O_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0ll1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0lli0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lli0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lli0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lli1i_dataout : STD_LOGIC; + SIGNAL wire_ni0lli1l_dataout : STD_LOGIC; + SIGNAL wire_ni0lli1O_dataout : STD_LOGIC; + SIGNAL wire_ni0llii_dataout : STD_LOGIC; + SIGNAL wire_ni0lliii_dataout : STD_LOGIC; + SIGNAL wire_ni0lliil_dataout : STD_LOGIC; + SIGNAL wire_ni0lliiO_dataout : STD_LOGIC; + SIGNAL wire_ni0llili_dataout : STD_LOGIC; + SIGNAL wire_ni0llill_dataout : STD_LOGIC; + SIGNAL wire_ni0llilO_dataout : STD_LOGIC; + SIGNAL wire_ni0lliOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lliOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lliOO_dataout : STD_LOGIC; + SIGNAL wire_ni0lll0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lll0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lll0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lll1i_dataout : STD_LOGIC; + SIGNAL wire_ni0lll1l_dataout : STD_LOGIC; + SIGNAL wire_ni0lll1O_dataout : STD_LOGIC; + SIGNAL wire_ni0lllii_dataout : STD_LOGIC; + SIGNAL wire_ni0lllil_dataout : STD_LOGIC; + SIGNAL wire_ni0llliO_dataout : STD_LOGIC; + SIGNAL wire_ni0lllli_dataout : STD_LOGIC; + SIGNAL wire_ni0lllll_dataout : STD_LOGIC; + SIGNAL wire_ni0llllO_dataout : STD_LOGIC; + SIGNAL wire_ni0lllOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lllOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lllOO_dataout : STD_LOGIC; + SIGNAL wire_ni0llO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0llO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0llO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0llO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0llO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0llO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0llOii_dataout : STD_LOGIC; + SIGNAL wire_ni0llOil_dataout : STD_LOGIC; + SIGNAL wire_ni0llOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0llOli_dataout : STD_LOGIC; + SIGNAL wire_ni0llOll_dataout : STD_LOGIC; + SIGNAL wire_ni0llOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0llOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0llOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0llOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO00i_dataout : STD_LOGIC; + SIGNAL wire_ni0lO00l_dataout : STD_LOGIC; + SIGNAL wire_ni0lO00O_dataout : STD_LOGIC; + SIGNAL wire_ni0lO01i_dataout : STD_LOGIC; + SIGNAL wire_ni0lO01l_dataout : STD_LOGIC; + SIGNAL wire_ni0lO01O_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0il_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0li_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0lO0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO10i_dataout : STD_LOGIC; + SIGNAL wire_ni0lO10l_dataout : STD_LOGIC; + SIGNAL wire_ni0lO10O_dataout : STD_LOGIC; + SIGNAL wire_ni0lO11i_dataout : STD_LOGIC; + SIGNAL wire_ni0lO11l_dataout : STD_LOGIC; + SIGNAL wire_ni0lO11O_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1il_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1li_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0lO1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOi0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lOi0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lOi0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lOi1i_dataout : STD_LOGIC; + SIGNAL wire_ni0lOi1l_dataout : STD_LOGIC; + SIGNAL wire_ni0lOi1O_dataout : STD_LOGIC; + SIGNAL wire_ni0lOii_dataout : STD_LOGIC; + SIGNAL wire_ni0lOiii_dataout : STD_LOGIC; + SIGNAL wire_ni0lOiil_dataout : STD_LOGIC; + SIGNAL wire_ni0lOiiO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOil_dataout : STD_LOGIC; + SIGNAL wire_ni0lOili_dataout : STD_LOGIC; + SIGNAL wire_ni0lOill_dataout : STD_LOGIC; + SIGNAL wire_ni0lOilO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOiOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lOiOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lOiOO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl1i_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl1l_dataout : STD_LOGIC; + SIGNAL wire_ni0lOl1O_dataout : STD_LOGIC; + SIGNAL wire_ni0lOli_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlii_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlil_dataout : STD_LOGIC; + SIGNAL wire_ni0lOliO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOll_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlli_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlll_dataout : STD_LOGIC; + SIGNAL wire_ni0lOllO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lOlOO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0lOO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOii_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOil_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOli_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOll_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0lOOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O000i_dataout : STD_LOGIC; + SIGNAL wire_ni0O000l_dataout : STD_LOGIC; + SIGNAL wire_ni0O000O_dataout : STD_LOGIC; + SIGNAL wire_ni0O001i_dataout : STD_LOGIC; + SIGNAL wire_ni0O001l_dataout : STD_LOGIC; + SIGNAL wire_ni0O001O_dataout : STD_LOGIC; + SIGNAL wire_ni0O00ii_dataout : STD_LOGIC; + SIGNAL wire_ni0O00il_dataout : STD_LOGIC; + SIGNAL wire_ni0O00iO_dataout : STD_LOGIC; + SIGNAL wire_ni0O00li_dataout : STD_LOGIC; + SIGNAL wire_ni0O00ll_dataout : STD_LOGIC; + SIGNAL wire_ni0O00lO_dataout : STD_LOGIC; + SIGNAL wire_ni0O00Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0O00Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0O00OO_dataout : STD_LOGIC; + SIGNAL wire_ni0O010i_dataout : STD_LOGIC; + SIGNAL wire_ni0O010l_dataout : STD_LOGIC; + SIGNAL wire_ni0O010O_dataout : STD_LOGIC; + SIGNAL wire_ni0O011i_dataout : STD_LOGIC; + SIGNAL wire_ni0O011l_dataout : STD_LOGIC; + SIGNAL wire_ni0O011O_dataout : STD_LOGIC; + SIGNAL wire_ni0O01ii_dataout : STD_LOGIC; + SIGNAL wire_ni0O01il_dataout : STD_LOGIC; + SIGNAL wire_ni0O01iO_dataout : STD_LOGIC; + SIGNAL wire_ni0O01li_dataout : STD_LOGIC; + SIGNAL wire_ni0O01ll_dataout : STD_LOGIC; + SIGNAL wire_ni0O01lO_dataout : STD_LOGIC; + SIGNAL wire_ni0O01Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0O01Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0O01OO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0i0i_dataout : STD_LOGIC; + SIGNAL wire_ni0O0i0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O0i0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O0i1i_dataout : STD_LOGIC; + SIGNAL wire_ni0O0i1l_dataout : STD_LOGIC; + SIGNAL wire_ni0O0i1O_dataout : STD_LOGIC; + SIGNAL wire_ni0O0iii_dataout : STD_LOGIC; + SIGNAL wire_ni0O0iil_dataout : STD_LOGIC; + SIGNAL wire_ni0O0iiO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0ili_dataout : STD_LOGIC; + SIGNAL wire_ni0O0ill_dataout : STD_LOGIC; + SIGNAL wire_ni0O0ilO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0iOi_dataout : STD_LOGIC; + SIGNAL wire_ni0O0iOl_dataout : STD_LOGIC; + SIGNAL wire_ni0O0iOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0l0i_dataout : STD_LOGIC; + SIGNAL wire_ni0O0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O0l0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O0l1i_dataout : STD_LOGIC; + SIGNAL wire_ni0O0l1l_dataout : STD_LOGIC; + SIGNAL wire_ni0O0l1O_dataout : STD_LOGIC; + SIGNAL wire_ni0O0lii_dataout : STD_LOGIC; + SIGNAL wire_ni0O0lil_dataout : STD_LOGIC; + SIGNAL wire_ni0O0liO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0lli_dataout : STD_LOGIC; + SIGNAL wire_ni0O0lll_dataout : STD_LOGIC; + SIGNAL wire_ni0O0llO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0lOi_dataout : STD_LOGIC; + SIGNAL wire_ni0O0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0O0lOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0O0i_dataout : STD_LOGIC; + SIGNAL wire_ni0O0O0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O0O0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O0O1i_dataout : STD_LOGIC; + SIGNAL wire_ni0O0O1l_dataout : STD_LOGIC; + SIGNAL wire_ni0O0O1O_dataout : STD_LOGIC; + SIGNAL wire_ni0O0Oii_dataout : STD_LOGIC; + SIGNAL wire_ni0O0Oil_dataout : STD_LOGIC; + SIGNAL wire_ni0O0OiO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0Oli_dataout : STD_LOGIC; + SIGNAL wire_ni0O0Oll_dataout : STD_LOGIC; + SIGNAL wire_ni0O0OlO_dataout : STD_LOGIC; + SIGNAL wire_ni0O0OOi_dataout : STD_LOGIC; + SIGNAL wire_ni0O0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni0O0OOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O100i_dataout : STD_LOGIC; + SIGNAL wire_ni0O100l_dataout : STD_LOGIC; + SIGNAL wire_ni0O100O_dataout : STD_LOGIC; + SIGNAL wire_ni0O101i_dataout : STD_LOGIC; + SIGNAL wire_ni0O101l_dataout : STD_LOGIC; + SIGNAL wire_ni0O101O_dataout : STD_LOGIC; + SIGNAL wire_ni0O10i_dataout : STD_LOGIC; + SIGNAL wire_ni0O10ii_dataout : STD_LOGIC; + SIGNAL wire_ni0O10il_dataout : STD_LOGIC; + SIGNAL wire_ni0O10iO_dataout : STD_LOGIC; + SIGNAL wire_ni0O10l_dataout : STD_LOGIC; + SIGNAL wire_ni0O10li_dataout : STD_LOGIC; + SIGNAL wire_ni0O10ll_dataout : STD_LOGIC; + SIGNAL wire_ni0O10lO_dataout : STD_LOGIC; + SIGNAL wire_ni0O10O_dataout : STD_LOGIC; + SIGNAL wire_ni0O10Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0O10Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0O10OO_dataout : STD_LOGIC; + SIGNAL wire_ni0O110i_dataout : STD_LOGIC; + SIGNAL wire_ni0O110l_dataout : STD_LOGIC; + SIGNAL wire_ni0O110O_dataout : STD_LOGIC; + SIGNAL wire_ni0O111i_dataout : STD_LOGIC; + SIGNAL wire_ni0O111l_dataout : STD_LOGIC; + SIGNAL wire_ni0O111O_dataout : STD_LOGIC; + SIGNAL wire_ni0O11i_dataout : STD_LOGIC; + SIGNAL wire_ni0O11ii_dataout : STD_LOGIC; + SIGNAL wire_ni0O11il_dataout : STD_LOGIC; + SIGNAL wire_ni0O11iO_dataout : STD_LOGIC; + SIGNAL wire_ni0O11l_dataout : STD_LOGIC; + SIGNAL wire_ni0O11li_dataout : STD_LOGIC; + SIGNAL wire_ni0O11ll_dataout : STD_LOGIC; + SIGNAL wire_ni0O11lO_dataout : STD_LOGIC; + SIGNAL wire_ni0O11O_dataout : STD_LOGIC; + SIGNAL wire_ni0O11Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0O11Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0O11OO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1i0i_dataout : STD_LOGIC; + SIGNAL wire_ni0O1i0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O1i0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O1i1i_dataout : STD_LOGIC; + SIGNAL wire_ni0O1i1l_dataout : STD_LOGIC; + SIGNAL wire_ni0O1i1O_dataout : STD_LOGIC; + SIGNAL wire_ni0O1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0O1iii_dataout : STD_LOGIC; + SIGNAL wire_ni0O1iil_dataout : STD_LOGIC; + SIGNAL wire_ni0O1iiO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1ili_dataout : STD_LOGIC; + SIGNAL wire_ni0O1ill_dataout : STD_LOGIC; + SIGNAL wire_ni0O1ilO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1iOi_dataout : STD_LOGIC; + SIGNAL wire_ni0O1iOl_dataout : STD_LOGIC; + SIGNAL wire_ni0O1iOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1l0i_dataout : STD_LOGIC; + SIGNAL wire_ni0O1l0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O1l0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O1l1i_dataout : STD_LOGIC; + SIGNAL wire_ni0O1l1l_dataout : STD_LOGIC; + SIGNAL wire_ni0O1l1O_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lii_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lil_dataout : STD_LOGIC; + SIGNAL wire_ni0O1liO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lli_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lll_dataout : STD_LOGIC; + SIGNAL wire_ni0O1llO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lOi_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lOl_dataout : STD_LOGIC; + SIGNAL wire_ni0O1lOO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1O0i_dataout : STD_LOGIC; + SIGNAL wire_ni0O1O0l_dataout : STD_LOGIC; + SIGNAL wire_ni0O1O0O_dataout : STD_LOGIC; + SIGNAL wire_ni0O1O1i_dataout : STD_LOGIC; + SIGNAL wire_ni0O1O1l_dataout : STD_LOGIC; + SIGNAL wire_ni0O1O1O_dataout : STD_LOGIC; + SIGNAL wire_ni0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0O1Oii_dataout : STD_LOGIC; + SIGNAL wire_ni0O1Oil_dataout : STD_LOGIC; + SIGNAL wire_ni0O1OiO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0O1Oli_dataout : STD_LOGIC; + SIGNAL wire_ni0O1Oll_dataout : STD_LOGIC; + SIGNAL wire_ni0O1OlO_dataout : STD_LOGIC; + SIGNAL wire_ni0O1OOi_dataout : STD_LOGIC; + SIGNAL wire_ni0O1OOl_dataout : STD_LOGIC; + SIGNAL wire_ni0O1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi00i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi00l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi00O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi01i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi01l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi01O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0il_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0li_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi10i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi10l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi10O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi11i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi11l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi11O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1il_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1li_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oii0i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oii0l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oii0O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oii1i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oii1l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oii1O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oiiii_dataout : STD_LOGIC; + SIGNAL wire_ni0Oiiil_dataout : STD_LOGIC; + SIGNAL wire_ni0OiiiO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oiili_dataout : STD_LOGIC; + SIGNAL wire_ni0Oiill_dataout : STD_LOGIC; + SIGNAL wire_ni0OiilO_dataout : STD_LOGIC; + SIGNAL wire_ni0OiiOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OiiOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OiiOO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oil0i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oil0l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oil0O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oil1i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oil1l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oil1O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oilii_dataout : STD_LOGIC; + SIGNAL wire_ni0Oilil_dataout : STD_LOGIC; + SIGNAL wire_ni0OiliO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oilli_dataout : STD_LOGIC; + SIGNAL wire_ni0Oilll_dataout : STD_LOGIC; + SIGNAL wire_ni0OillO_dataout : STD_LOGIC; + SIGNAL wire_ni0OilOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OilOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OilOO_dataout : STD_LOGIC; + SIGNAL wire_ni0OiO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0OiO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0OiO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0OiO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0OiO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0OiO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOii_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOil_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOli_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOll_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OiOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol00i_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol00l_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol00O_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol01i_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol01l_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol01O_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0il_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0li_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol10i_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol10l_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol10O_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol11i_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol11l_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol11O_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1il_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1li_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli0i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli0l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli0O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli1i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli1l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oli1O_dataout : STD_LOGIC; + SIGNAL wire_ni0Olii_dataout : STD_LOGIC; + SIGNAL wire_ni0Oliii_dataout : STD_LOGIC; + SIGNAL wire_ni0Oliil_dataout : STD_LOGIC; + SIGNAL wire_ni0OliiO_dataout : STD_LOGIC; + SIGNAL wire_ni0Olil_dataout : STD_LOGIC; + SIGNAL wire_ni0Olili_dataout : STD_LOGIC; + SIGNAL wire_ni0Olill_dataout : STD_LOGIC; + SIGNAL wire_ni0OlilO_dataout : STD_LOGIC; + SIGNAL wire_ni0OliO_dataout : STD_LOGIC; + SIGNAL wire_ni0OliOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OliOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OliOO_dataout : STD_LOGIC; + SIGNAL wire_ni0Oll0i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oll0l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oll0O_dataout : STD_LOGIC; + SIGNAL wire_ni0Oll1i_dataout : STD_LOGIC; + SIGNAL wire_ni0Oll1l_dataout : STD_LOGIC; + SIGNAL wire_ni0Oll1O_dataout : STD_LOGIC; + SIGNAL wire_ni0Olli_dataout : STD_LOGIC; + SIGNAL wire_ni0Ollii_dataout : STD_LOGIC; + SIGNAL wire_ni0Ollil_dataout : STD_LOGIC; + SIGNAL wire_ni0OlliO_dataout : STD_LOGIC; + SIGNAL wire_ni0Olll_dataout : STD_LOGIC; + SIGNAL wire_ni0Ollli_dataout : STD_LOGIC; + SIGNAL wire_ni0Ollll_dataout : STD_LOGIC; + SIGNAL wire_ni0OlllO_dataout : STD_LOGIC; + SIGNAL wire_ni0OllO_dataout : STD_LOGIC; + SIGNAL wire_ni0OllOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OllOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OllOO_dataout : STD_LOGIC; + SIGNAL wire_ni0OlO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0OlO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0OlO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0OlO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0OlO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0OlO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOii_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOil_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOli_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOll_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOO_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OlOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0OO00i_dataout : STD_LOGIC; + SIGNAL wire_ni0OO00l_dataout : STD_LOGIC; + SIGNAL wire_ni0OO00O_dataout : STD_LOGIC; + SIGNAL wire_ni0OO01i_dataout : STD_LOGIC; + SIGNAL wire_ni0OO01l_dataout : STD_LOGIC; + SIGNAL wire_ni0OO01O_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0ii_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0il_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0iO_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0li_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0ll_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0lO_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0OO0OO_dataout : STD_LOGIC; + SIGNAL wire_ni0OO10i_dataout : STD_LOGIC; + SIGNAL wire_ni0OO10l_dataout : STD_LOGIC; + SIGNAL wire_ni0OO10O_dataout : STD_LOGIC; + SIGNAL wire_ni0OO11i_dataout : STD_LOGIC; + SIGNAL wire_ni0OO11l_dataout : STD_LOGIC; + SIGNAL wire_ni0OO11O_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1ii_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1il_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1iO_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1li_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1ll_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1lO_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni0OO1OO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOi0i_dataout : STD_LOGIC; + SIGNAL wire_ni0OOi0l_dataout : STD_LOGIC; + SIGNAL wire_ni0OOi0O_dataout : STD_LOGIC; + SIGNAL wire_ni0OOi1i_dataout : STD_LOGIC; + SIGNAL wire_ni0OOi1l_dataout : STD_LOGIC; + SIGNAL wire_ni0OOi1O_dataout : STD_LOGIC; + SIGNAL wire_ni0OOii_dataout : STD_LOGIC; + SIGNAL wire_ni0OOiii_dataout : STD_LOGIC; + SIGNAL wire_ni0OOiil_dataout : STD_LOGIC; + SIGNAL wire_ni0OOiiO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOil_dataout : STD_LOGIC; + SIGNAL wire_ni0OOili_dataout : STD_LOGIC; + SIGNAL wire_ni0OOill_dataout : STD_LOGIC; + SIGNAL wire_ni0OOilO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOiOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OOiOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OOiOO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl0i_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl0l_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl0O_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl1i_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl1l_dataout : STD_LOGIC; + SIGNAL wire_ni0OOl1O_dataout : STD_LOGIC; + SIGNAL wire_ni0OOli_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlii_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlil_dataout : STD_LOGIC; + SIGNAL wire_ni0OOliO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOll_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlli_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlll_dataout : STD_LOGIC; + SIGNAL wire_ni0OOllO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OOlOO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOO0i_dataout : STD_LOGIC; + SIGNAL wire_ni0OOO0l_dataout : STD_LOGIC; + SIGNAL wire_ni0OOO0O_dataout : STD_LOGIC; + SIGNAL wire_ni0OOO1i_dataout : STD_LOGIC; + SIGNAL wire_ni0OOO1l_dataout : STD_LOGIC; + SIGNAL wire_ni0OOO1O_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOii_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOil_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOiO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOli_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOll_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOlO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOO_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOOi_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOOl_dataout : STD_LOGIC; + SIGNAL wire_ni0OOOOO_dataout : STD_LOGIC; + SIGNAL wire_ni10000i_dataout : STD_LOGIC; + SIGNAL wire_ni10000l_dataout : STD_LOGIC; + SIGNAL wire_ni10000O_dataout : STD_LOGIC; + SIGNAL wire_ni10001i_dataout : STD_LOGIC; + SIGNAL wire_ni10001l_dataout : STD_LOGIC; + SIGNAL wire_ni10001O_dataout : STD_LOGIC; + SIGNAL wire_ni1000ii_dataout : STD_LOGIC; + SIGNAL wire_ni1000il_dataout : STD_LOGIC; + SIGNAL wire_ni1000iO_dataout : STD_LOGIC; + SIGNAL wire_ni1000li_dataout : STD_LOGIC; + SIGNAL wire_ni1000ll_dataout : STD_LOGIC; + SIGNAL wire_ni10010i_dataout : STD_LOGIC; + SIGNAL wire_ni10010l_dataout : STD_LOGIC; + SIGNAL wire_ni10010O_dataout : STD_LOGIC; + SIGNAL wire_ni10011i_dataout : STD_LOGIC; + SIGNAL wire_ni10011l_dataout : STD_LOGIC; + SIGNAL wire_ni10011O_dataout : STD_LOGIC; + SIGNAL wire_ni1001ii_dataout : STD_LOGIC; + SIGNAL wire_ni1001il_dataout : STD_LOGIC; + SIGNAL wire_ni1001iO_dataout : STD_LOGIC; + SIGNAL wire_ni1001li_dataout : STD_LOGIC; + SIGNAL wire_ni1001ll_dataout : STD_LOGIC; + SIGNAL wire_ni1001lO_dataout : STD_LOGIC; + SIGNAL wire_ni1001Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1001Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1001OO_dataout : STD_LOGIC; + SIGNAL wire_ni100iii_dataout : STD_LOGIC; + SIGNAL wire_ni100iil_dataout : STD_LOGIC; + SIGNAL wire_ni100iiO_dataout : STD_LOGIC; + SIGNAL wire_ni100ili_dataout : STD_LOGIC; + SIGNAL wire_ni100ill_dataout : STD_LOGIC; + SIGNAL wire_ni100ilO_dataout : STD_LOGIC; + SIGNAL wire_ni100iOi_dataout : STD_LOGIC; + SIGNAL wire_ni100iOl_dataout : STD_LOGIC; + SIGNAL wire_ni100iOO_dataout : STD_LOGIC; + SIGNAL wire_ni100l0i_dataout : STD_LOGIC; + SIGNAL wire_ni100l0l_dataout : STD_LOGIC; + SIGNAL wire_ni100l0O_dataout : STD_LOGIC; + SIGNAL wire_ni100l1i_dataout : STD_LOGIC; + SIGNAL wire_ni100l1l_dataout : STD_LOGIC; + SIGNAL wire_ni100l1O_dataout : STD_LOGIC; + SIGNAL wire_ni100lii_dataout : STD_LOGIC; + SIGNAL wire_ni100lil_dataout : STD_LOGIC; + SIGNAL wire_ni100liO_dataout : STD_LOGIC; + SIGNAL wire_ni100lli_dataout : STD_LOGIC; + SIGNAL wire_ni100lll_dataout : STD_LOGIC; + SIGNAL wire_ni100llO_dataout : STD_LOGIC; + SIGNAL wire_ni100lOi_dataout : STD_LOGIC; + SIGNAL wire_ni100lOl_dataout : STD_LOGIC; + SIGNAL wire_ni100lOO_dataout : STD_LOGIC; + SIGNAL wire_ni100O1i_dataout : STD_LOGIC; + SIGNAL wire_ni100O1l_dataout : STD_LOGIC; + SIGNAL wire_ni100O1O_dataout : STD_LOGIC; + SIGNAL wire_ni10100i_dataout : STD_LOGIC; + SIGNAL wire_ni10100l_dataout : STD_LOGIC; + SIGNAL wire_ni10100O_dataout : STD_LOGIC; + SIGNAL wire_ni10101i_dataout : STD_LOGIC; + SIGNAL wire_ni10101l_dataout : STD_LOGIC; + SIGNAL wire_ni10101O_dataout : STD_LOGIC; + SIGNAL wire_ni1010i_dataout : STD_LOGIC; + SIGNAL wire_ni1010ii_dataout : STD_LOGIC; + SIGNAL wire_ni1010il_dataout : STD_LOGIC; + SIGNAL wire_ni1010iO_dataout : STD_LOGIC; + SIGNAL wire_ni1010li_dataout : STD_LOGIC; + SIGNAL wire_ni1010ll_dataout : STD_LOGIC; + SIGNAL wire_ni10110i_dataout : STD_LOGIC; + SIGNAL wire_ni10110l_dataout : STD_LOGIC; + SIGNAL wire_ni10110O_dataout : STD_LOGIC; + SIGNAL wire_ni10111i_dataout : STD_LOGIC; + SIGNAL wire_ni10111l_dataout : STD_LOGIC; + SIGNAL wire_ni10111O_dataout : STD_LOGIC; + SIGNAL wire_ni1011i_dataout : STD_LOGIC; + SIGNAL wire_ni1011ii_dataout : STD_LOGIC; + SIGNAL wire_ni1011il_dataout : STD_LOGIC; + SIGNAL wire_ni1011iO_dataout : STD_LOGIC; + SIGNAL wire_ni1011l_dataout : STD_LOGIC; + SIGNAL wire_ni1011li_dataout : STD_LOGIC; + SIGNAL wire_ni1011ll_dataout : STD_LOGIC; + SIGNAL wire_ni1011lO_dataout : STD_LOGIC; + SIGNAL wire_ni1011O_dataout : STD_LOGIC; + SIGNAL wire_ni1011Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1011Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1011OO_dataout : STD_LOGIC; + SIGNAL wire_ni101i0l_dataout : STD_LOGIC; + SIGNAL wire_ni101i0O_dataout : STD_LOGIC; + SIGNAL wire_ni101iii_dataout : STD_LOGIC; + SIGNAL wire_ni101iil_dataout : STD_LOGIC; + SIGNAL wire_ni101iiO_dataout : STD_LOGIC; + SIGNAL wire_ni101ilO_dataout : STD_LOGIC; + SIGNAL wire_ni101iOi_dataout : STD_LOGIC; + SIGNAL wire_ni101iOl_dataout : STD_LOGIC; + SIGNAL wire_ni101iOO_dataout : STD_LOGIC; + SIGNAL wire_ni101l0i_dataout : STD_LOGIC; + SIGNAL wire_ni101l0l_dataout : STD_LOGIC; + SIGNAL wire_ni101l0O_dataout : STD_LOGIC; + SIGNAL wire_ni101l1i_dataout : STD_LOGIC; + SIGNAL wire_ni101l1l_dataout : STD_LOGIC; + SIGNAL wire_ni101l1O_dataout : STD_LOGIC; + SIGNAL wire_ni101lii_dataout : STD_LOGIC; + SIGNAL wire_ni101lil_dataout : STD_LOGIC; + SIGNAL wire_ni101OOO_dataout : STD_LOGIC; + SIGNAL wire_ni10i00i_dataout : STD_LOGIC; + SIGNAL wire_ni10i00l_dataout : STD_LOGIC; + SIGNAL wire_ni10i00O_dataout : STD_LOGIC; + SIGNAL wire_ni10i01i_dataout : STD_LOGIC; + SIGNAL wire_ni10i01l_dataout : STD_LOGIC; + SIGNAL wire_ni10i01O_dataout : STD_LOGIC; + SIGNAL wire_ni10i0ii_dataout : STD_LOGIC; + SIGNAL wire_ni10i0il_dataout : STD_LOGIC; + SIGNAL wire_ni10i0iO_dataout : STD_LOGIC; + SIGNAL wire_ni10i0li_dataout : STD_LOGIC; + SIGNAL wire_ni10i0ll_dataout : STD_LOGIC; + SIGNAL wire_ni10i0lO_dataout : STD_LOGIC; + SIGNAL wire_ni10i0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni10i10i_dataout : STD_LOGIC; + SIGNAL wire_ni10i10l_dataout : STD_LOGIC; + SIGNAL wire_ni10i10O_dataout : STD_LOGIC; + SIGNAL wire_ni10i11l_dataout : STD_LOGIC; + SIGNAL wire_ni10i11O_dataout : STD_LOGIC; + SIGNAL wire_ni10i1ii_dataout : STD_LOGIC; + SIGNAL wire_ni10i1il_dataout : STD_LOGIC; + SIGNAL wire_ni10i1iO_dataout : STD_LOGIC; + SIGNAL wire_ni10i1li_dataout : STD_LOGIC; + SIGNAL wire_ni10i1ll_dataout : STD_LOGIC; + SIGNAL wire_ni10i1lO_dataout : STD_LOGIC; + SIGNAL wire_ni10i1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni10i1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni10i1OO_dataout : STD_LOGIC; + SIGNAL wire_ni10iil_dataout : STD_LOGIC; + SIGNAL wire_ni10iilO_dataout : STD_LOGIC; + SIGNAL wire_ni10iiO_dataout : STD_LOGIC; + SIGNAL wire_ni10iiOi_dataout : STD_LOGIC; + SIGNAL wire_ni10iiOl_dataout : STD_LOGIC; + SIGNAL wire_ni10iiOO_dataout : STD_LOGIC; + SIGNAL wire_ni10il0i_dataout : STD_LOGIC; + SIGNAL wire_ni10il0l_dataout : STD_LOGIC; + SIGNAL wire_ni10il0O_dataout : STD_LOGIC; + SIGNAL wire_ni10il1i_dataout : STD_LOGIC; + SIGNAL wire_ni10il1l_dataout : STD_LOGIC; + SIGNAL wire_ni10il1O_dataout : STD_LOGIC; + SIGNAL wire_ni10ili_dataout : STD_LOGIC; + SIGNAL wire_ni10ilii_dataout : STD_LOGIC; + SIGNAL wire_ni10ilil_dataout : STD_LOGIC; + SIGNAL wire_ni10iliO_dataout : STD_LOGIC; + SIGNAL wire_ni10ill_dataout : STD_LOGIC; + SIGNAL wire_ni10illi_dataout : STD_LOGIC; + SIGNAL wire_ni10illl_dataout : STD_LOGIC; + SIGNAL wire_ni10illO_dataout : STD_LOGIC; + SIGNAL wire_ni10ilOi_dataout : STD_LOGIC; + SIGNAL wire_ni10ilOl_dataout : STD_LOGIC; + SIGNAL wire_ni10ilOO_dataout : STD_LOGIC; + SIGNAL wire_ni10iO0i_dataout : STD_LOGIC; + SIGNAL wire_ni10iO0l_dataout : STD_LOGIC; + SIGNAL wire_ni10iO0O_dataout : STD_LOGIC; + SIGNAL wire_ni10iO1i_dataout : STD_LOGIC; + SIGNAL wire_ni10iO1l_dataout : STD_LOGIC; + SIGNAL wire_ni10iO1O_dataout : STD_LOGIC; + SIGNAL wire_ni10iOii_dataout : STD_LOGIC; + SIGNAL wire_ni10iOil_dataout : STD_LOGIC; + SIGNAL wire_ni10l00i_dataout : STD_LOGIC; + SIGNAL wire_ni10l00l_dataout : STD_LOGIC; + SIGNAL wire_ni10l00O_dataout : STD_LOGIC; + SIGNAL wire_ni10l01i_dataout : STD_LOGIC; + SIGNAL wire_ni10l01l_dataout : STD_LOGIC; + SIGNAL wire_ni10l01O_dataout : STD_LOGIC; + SIGNAL wire_ni10l0ii_dataout : STD_LOGIC; + SIGNAL wire_ni10l0il_dataout : STD_LOGIC; + SIGNAL wire_ni10l0iO_dataout : STD_LOGIC; + SIGNAL wire_ni10l0li_dataout : STD_LOGIC; + SIGNAL wire_ni10l0ll_dataout : STD_LOGIC; + SIGNAL wire_ni10l0lO_dataout : STD_LOGIC; + SIGNAL wire_ni10l0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni10l0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni10l0OO_dataout : STD_LOGIC; + SIGNAL wire_ni10l1ii_dataout : STD_LOGIC; + SIGNAL wire_ni10l1il_dataout : STD_LOGIC; + SIGNAL wire_ni10l1iO_dataout : STD_LOGIC; + SIGNAL wire_ni10l1li_dataout : STD_LOGIC; + SIGNAL wire_ni10l1ll_dataout : STD_LOGIC; + SIGNAL wire_ni10l1lO_dataout : STD_LOGIC; + SIGNAL wire_ni10l1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni10l1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni10l1OO_dataout : STD_LOGIC; + SIGNAL wire_ni10li1i_dataout : STD_LOGIC; + SIGNAL wire_ni10li1l_dataout : STD_LOGIC; + SIGNAL wire_ni10li1O_dataout : STD_LOGIC; + SIGNAL wire_ni10ll0i_dataout : STD_LOGIC; + SIGNAL wire_ni10ll0l_dataout : STD_LOGIC; + SIGNAL wire_ni10ll0O_dataout : STD_LOGIC; + SIGNAL wire_ni10ll1l_dataout : STD_LOGIC; + SIGNAL wire_ni10ll1O_dataout : STD_LOGIC; + SIGNAL wire_ni10llii_dataout : STD_LOGIC; + SIGNAL wire_ni10llil_dataout : STD_LOGIC; + SIGNAL wire_ni10lliO_dataout : STD_LOGIC; + SIGNAL wire_ni10llli_dataout : STD_LOGIC; + SIGNAL wire_ni10llll_dataout : STD_LOGIC; + SIGNAL wire_ni10lllO_dataout : STD_LOGIC; + SIGNAL wire_ni10llOi_dataout : STD_LOGIC; + SIGNAL wire_ni10llOl_dataout : STD_LOGIC; + SIGNAL wire_ni10llOO_dataout : STD_LOGIC; + SIGNAL wire_ni10lO0i_dataout : STD_LOGIC; + SIGNAL wire_ni10lO0l_dataout : STD_LOGIC; + SIGNAL wire_ni10lO0O_dataout : STD_LOGIC; + SIGNAL wire_ni10lO1i_dataout : STD_LOGIC; + SIGNAL wire_ni10lO1l_dataout : STD_LOGIC; + SIGNAL wire_ni10lO1O_dataout : STD_LOGIC; + SIGNAL wire_ni10lOii_dataout : STD_LOGIC; + SIGNAL wire_ni10lOil_dataout : STD_LOGIC; + SIGNAL wire_ni10lOiO_dataout : STD_LOGIC; + SIGNAL wire_ni10lOli_dataout : STD_LOGIC; + SIGNAL wire_ni10lOll_dataout : STD_LOGIC; + SIGNAL wire_ni10lOlO_dataout : STD_LOGIC; + SIGNAL wire_ni10lOOi_dataout : STD_LOGIC; + SIGNAL wire_ni10O00i_dataout : STD_LOGIC; + SIGNAL wire_ni10O00l_dataout : STD_LOGIC; + SIGNAL wire_ni10O00O_dataout : STD_LOGIC; + SIGNAL wire_ni10O01i_dataout : STD_LOGIC; + SIGNAL wire_ni10O01l_dataout : STD_LOGIC; + SIGNAL wire_ni10O01O_dataout : STD_LOGIC; + SIGNAL wire_ni10O0ii_dataout : STD_LOGIC; + SIGNAL wire_ni10O0il_dataout : STD_LOGIC; + SIGNAL wire_ni10O0iO_dataout : STD_LOGIC; + SIGNAL wire_ni10O0li_dataout : STD_LOGIC; + SIGNAL wire_ni10O0ll_dataout : STD_LOGIC; + SIGNAL wire_ni10O0lO_dataout : STD_LOGIC; + SIGNAL wire_ni10O0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni10O0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni10O0OO_dataout : STD_LOGIC; + SIGNAL wire_ni10O1lO_dataout : STD_LOGIC; + SIGNAL wire_ni10O1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni10O1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni10O1OO_dataout : STD_LOGIC; + SIGNAL wire_ni10Oi0i_dataout : STD_LOGIC; + SIGNAL wire_ni10Oi0l_dataout : STD_LOGIC; + SIGNAL wire_ni10Oi0O_dataout : STD_LOGIC; + SIGNAL wire_ni10Oi1i_dataout : STD_LOGIC; + SIGNAL wire_ni10Oi1l_dataout : STD_LOGIC; + SIGNAL wire_ni10Oi1O_dataout : STD_LOGIC; + SIGNAL wire_ni10Oiii_dataout : STD_LOGIC; + SIGNAL wire_ni10Oiil_dataout : STD_LOGIC; + SIGNAL wire_ni10Oil_dataout : STD_LOGIC; + SIGNAL wire_ni10OiO_dataout : STD_LOGIC; + SIGNAL wire_ni10Oli_dataout : STD_LOGIC; + SIGNAL wire_ni10Olii_dataout : STD_LOGIC; + SIGNAL wire_ni10Olil_dataout : STD_LOGIC; + SIGNAL wire_ni10OliO_dataout : STD_LOGIC; + SIGNAL wire_ni10Oll_dataout : STD_LOGIC; + SIGNAL wire_ni10Olli_dataout : STD_LOGIC; + SIGNAL wire_ni10Olll_dataout : STD_LOGIC; + SIGNAL wire_ni10OllO_dataout : STD_LOGIC; + SIGNAL wire_ni10OlO_dataout : STD_LOGIC; + SIGNAL wire_ni10OlOi_dataout : STD_LOGIC; + SIGNAL wire_ni10OlOl_dataout : STD_LOGIC; + SIGNAL wire_ni10OlOO_dataout : STD_LOGIC; + SIGNAL wire_ni10OO0i_dataout : STD_LOGIC; + SIGNAL wire_ni10OO0l_dataout : STD_LOGIC; + SIGNAL wire_ni10OO0O_dataout : STD_LOGIC; + SIGNAL wire_ni10OO1i_dataout : STD_LOGIC; + SIGNAL wire_ni10OO1l_dataout : STD_LOGIC; + SIGNAL wire_ni10OO1O_dataout : STD_LOGIC; + SIGNAL wire_ni10OOi_dataout : STD_LOGIC; + SIGNAL wire_ni10OOii_dataout : STD_LOGIC; + SIGNAL wire_ni10OOil_dataout : STD_LOGIC; + SIGNAL wire_ni10OOiO_dataout : STD_LOGIC; + SIGNAL wire_ni10OOl_dataout : STD_LOGIC; + SIGNAL wire_ni10OOli_dataout : STD_LOGIC; + SIGNAL wire_ni10OOll_dataout : STD_LOGIC; + SIGNAL wire_ni10OOlO_dataout : STD_LOGIC; + SIGNAL wire_ni10OOO_dataout : STD_LOGIC; + SIGNAL wire_ni10OOOi_dataout : STD_LOGIC; + SIGNAL wire_ni10OOOl_dataout : STD_LOGIC; + SIGNAL wire_ni10OOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1100il_dataout : STD_LOGIC; + SIGNAL wire_ni1100iO_dataout : STD_LOGIC; + SIGNAL wire_ni1100li_dataout : STD_LOGIC; + SIGNAL wire_ni1100ll_dataout : STD_LOGIC; + SIGNAL wire_ni1100lO_dataout : STD_LOGIC; + SIGNAL wire_ni1100Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1100Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1100OO_dataout : STD_LOGIC; + SIGNAL wire_ni11011i_dataout : STD_LOGIC; + SIGNAL wire_ni110i0i_dataout : STD_LOGIC; + SIGNAL wire_ni110i0l_dataout : STD_LOGIC; + SIGNAL wire_ni110i0O_dataout : STD_LOGIC; + SIGNAL wire_ni110i1i_dataout : STD_LOGIC; + SIGNAL wire_ni110i1l_dataout : STD_LOGIC; + SIGNAL wire_ni110i1O_dataout : STD_LOGIC; + SIGNAL wire_ni110ii_dataout : STD_LOGIC; + SIGNAL wire_ni110iii_dataout : STD_LOGIC; + SIGNAL wire_ni110iil_dataout : STD_LOGIC; + SIGNAL wire_ni110iiO_dataout : STD_LOGIC; + SIGNAL wire_ni110il_dataout : STD_LOGIC; + SIGNAL wire_ni110ili_dataout : STD_LOGIC; + SIGNAL wire_ni110ill_dataout : STD_LOGIC; + SIGNAL wire_ni110ilO_dataout : STD_LOGIC; + SIGNAL wire_ni110iO_dataout : STD_LOGIC; + SIGNAL wire_ni110iOi_dataout : STD_LOGIC; + SIGNAL wire_ni110iOl_dataout : STD_LOGIC; + SIGNAL wire_ni110iOO_dataout : STD_LOGIC; + SIGNAL wire_ni110l0i_dataout : STD_LOGIC; + SIGNAL wire_ni110l1i_dataout : STD_LOGIC; + SIGNAL wire_ni110l1l_dataout : STD_LOGIC; + SIGNAL wire_ni110l1O_dataout : STD_LOGIC; + SIGNAL wire_ni110lOO_dataout : STD_LOGIC; + SIGNAL wire_ni110O0i_dataout : STD_LOGIC; + SIGNAL wire_ni110O0l_dataout : STD_LOGIC; + SIGNAL wire_ni110O0O_dataout : STD_LOGIC; + SIGNAL wire_ni110O1i_dataout : STD_LOGIC; + SIGNAL wire_ni110O1l_dataout : STD_LOGIC; + SIGNAL wire_ni110O1O_dataout : STD_LOGIC; + SIGNAL wire_ni110Oii_dataout : STD_LOGIC; + SIGNAL wire_ni110Oil_dataout : STD_LOGIC; + SIGNAL wire_ni110OiO_dataout : STD_LOGIC; + SIGNAL wire_ni110Ol_dataout : STD_LOGIC; + SIGNAL wire_ni110Ol_w_lg_dataout2829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni110Ol_w_lg_dataout2425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni110Oli_dataout : STD_LOGIC; + SIGNAL wire_ni110Oll_dataout : STD_LOGIC; + SIGNAL wire_ni110OlO_dataout : STD_LOGIC; + SIGNAL wire_ni110OOi_dataout : STD_LOGIC; + SIGNAL wire_ni110OOl_dataout : STD_LOGIC; + SIGNAL wire_ni110OOO_dataout : STD_LOGIC; + SIGNAL wire_ni1110il_dataout : STD_LOGIC; + SIGNAL wire_ni1110iO_dataout : STD_LOGIC; + SIGNAL wire_ni1110li_dataout : STD_LOGIC; + SIGNAL wire_ni1110ll_dataout : STD_LOGIC; + SIGNAL wire_ni1110lO_dataout : STD_LOGIC; + SIGNAL wire_ni1110Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1110Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1110OO_dataout : STD_LOGIC; + SIGNAL wire_ni11110i_dataout : STD_LOGIC; + SIGNAL wire_ni11110l_dataout : STD_LOGIC; + SIGNAL wire_ni11110O_dataout : STD_LOGIC; + SIGNAL wire_ni11111i_dataout : STD_LOGIC; + SIGNAL wire_ni11111l_dataout : STD_LOGIC; + SIGNAL wire_ni11111O_dataout : STD_LOGIC; + SIGNAL wire_ni1111ii_dataout : STD_LOGIC; + SIGNAL wire_ni1111il_dataout : STD_LOGIC; + SIGNAL wire_ni1111iO_dataout : STD_LOGIC; + SIGNAL wire_ni111i0i_dataout : STD_LOGIC; + SIGNAL wire_ni111i0l_dataout : STD_LOGIC; + SIGNAL wire_ni111i0O_dataout : STD_LOGIC; + SIGNAL wire_ni111i1i_dataout : STD_LOGIC; + SIGNAL wire_ni111i1l_dataout : STD_LOGIC; + SIGNAL wire_ni111i1O_dataout : STD_LOGIC; + SIGNAL wire_ni111iii_dataout : STD_LOGIC; + SIGNAL wire_ni111iil_dataout : STD_LOGIC; + SIGNAL wire_ni111iiO_dataout : STD_LOGIC; + SIGNAL wire_ni111ili_dataout : STD_LOGIC; + SIGNAL wire_ni111ill_dataout : STD_LOGIC; + SIGNAL wire_ni111ilO_dataout : STD_LOGIC; + SIGNAL wire_ni111iOi_dataout : STD_LOGIC; + SIGNAL wire_ni111iOl_dataout : STD_LOGIC; + SIGNAL wire_ni111iOO_dataout : STD_LOGIC; + SIGNAL wire_ni111l0i_dataout : STD_LOGIC; + SIGNAL wire_ni111l1i_dataout : STD_LOGIC; + SIGNAL wire_ni111l1l_dataout : STD_LOGIC; + SIGNAL wire_ni111l1O_dataout : STD_LOGIC; + SIGNAL wire_ni111lOi_dataout : STD_LOGIC; + SIGNAL wire_ni111lOl_dataout : STD_LOGIC; + SIGNAL wire_ni111lOO_dataout : STD_LOGIC; + SIGNAL wire_ni111O0l_dataout : STD_LOGIC; + SIGNAL wire_ni111O0O_dataout : STD_LOGIC; + SIGNAL wire_ni111O1i_dataout : STD_LOGIC; + SIGNAL wire_ni111O1l_dataout : STD_LOGIC; + SIGNAL wire_ni111Oii_dataout : STD_LOGIC; + SIGNAL wire_ni111Oil_dataout : STD_LOGIC; + SIGNAL wire_ni111OiO_dataout : STD_LOGIC; + SIGNAL wire_ni111Oli_dataout : STD_LOGIC; + SIGNAL wire_ni111Oll_dataout : STD_LOGIC; + SIGNAL wire_ni111OlO_dataout : STD_LOGIC; + SIGNAL wire_ni111OOi_dataout : STD_LOGIC; + SIGNAL wire_ni111OOl_dataout : STD_LOGIC; + SIGNAL wire_ni111OOO_dataout : STD_LOGIC; + SIGNAL wire_ni11i0l_dataout : STD_LOGIC; + SIGNAL wire_ni11i0li_dataout : STD_LOGIC; + SIGNAL wire_ni11i0ll_dataout : STD_LOGIC; + SIGNAL wire_ni11i0lO_dataout : STD_LOGIC; + SIGNAL wire_ni11i0O_dataout : STD_LOGIC; + SIGNAL wire_ni11i0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni11i0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni11i0OO_dataout : STD_LOGIC; + SIGNAL wire_ni11i10i_dataout : STD_LOGIC; + SIGNAL wire_ni11i10l_dataout : STD_LOGIC; + SIGNAL wire_ni11i10O_dataout : STD_LOGIC; + SIGNAL wire_ni11i11i_dataout : STD_LOGIC; + SIGNAL wire_ni11i11l_dataout : STD_LOGIC; + SIGNAL wire_ni11i11O_dataout : STD_LOGIC; + SIGNAL wire_ni11i1ii_dataout : STD_LOGIC; + SIGNAL wire_ni11i1il_dataout : STD_LOGIC; + SIGNAL wire_ni11i1iO_dataout : STD_LOGIC; + SIGNAL wire_ni11i1li_dataout : STD_LOGIC; + SIGNAL wire_ni11i1ll_dataout : STD_LOGIC; + SIGNAL wire_ni11ii0i_dataout : STD_LOGIC; + SIGNAL wire_ni11ii0l_dataout : STD_LOGIC; + SIGNAL wire_ni11ii0O_dataout : STD_LOGIC; + SIGNAL wire_ni11ii1i_dataout : STD_LOGIC; + SIGNAL wire_ni11ii1l_dataout : STD_LOGIC; + SIGNAL wire_ni11ii1O_dataout : STD_LOGIC; + SIGNAL wire_ni11iii_dataout : STD_LOGIC; + SIGNAL wire_ni11iiii_dataout : STD_LOGIC; + SIGNAL wire_ni11iiil_dataout : STD_LOGIC; + SIGNAL wire_ni11iiiO_dataout : STD_LOGIC; + SIGNAL wire_ni11iil_dataout : STD_LOGIC; + SIGNAL wire_ni11iili_dataout : STD_LOGIC; + SIGNAL wire_ni11iill_dataout : STD_LOGIC; + SIGNAL wire_ni11iilO_dataout : STD_LOGIC; + SIGNAL wire_ni11iiOi_dataout : STD_LOGIC; + SIGNAL wire_ni11iiOl_dataout : STD_LOGIC; + SIGNAL wire_ni11iiOO_dataout : STD_LOGIC; + SIGNAL wire_ni11il0i_dataout : STD_LOGIC; + SIGNAL wire_ni11il0l_dataout : STD_LOGIC; + SIGNAL wire_ni11il0O_dataout : STD_LOGIC; + SIGNAL wire_ni11il1i_dataout : STD_LOGIC; + SIGNAL wire_ni11il1l_dataout : STD_LOGIC; + SIGNAL wire_ni11il1O_dataout : STD_LOGIC; + SIGNAL wire_ni11iO0l_dataout : STD_LOGIC; + SIGNAL wire_ni11iO0O_dataout : STD_LOGIC; + SIGNAL wire_ni11iOii_dataout : STD_LOGIC; + SIGNAL wire_ni11iOil_dataout : STD_LOGIC; + SIGNAL wire_ni11iOiO_dataout : STD_LOGIC; + SIGNAL wire_ni11iOli_dataout : STD_LOGIC; + SIGNAL wire_ni11iOll_dataout : STD_LOGIC; + SIGNAL wire_ni11iOlO_dataout : STD_LOGIC; + SIGNAL wire_ni11iOOi_dataout : STD_LOGIC; + SIGNAL wire_ni11iOOl_dataout : STD_LOGIC; + SIGNAL wire_ni11iOOO_dataout : STD_LOGIC; + SIGNAL wire_ni11l01i_dataout : STD_LOGIC; + SIGNAL wire_ni11l0OO_dataout : STD_LOGIC; + SIGNAL wire_ni11l10i_dataout : STD_LOGIC; + SIGNAL wire_ni11l10l_dataout : STD_LOGIC; + SIGNAL wire_ni11l10O_dataout : STD_LOGIC; + SIGNAL wire_ni11l11i_dataout : STD_LOGIC; + SIGNAL wire_ni11l11l_dataout : STD_LOGIC; + SIGNAL wire_ni11l11O_dataout : STD_LOGIC; + SIGNAL wire_ni11l1ii_dataout : STD_LOGIC; + SIGNAL wire_ni11l1il_dataout : STD_LOGIC; + SIGNAL wire_ni11l1iO_dataout : STD_LOGIC; + SIGNAL wire_ni11l1li_dataout : STD_LOGIC; + SIGNAL wire_ni11l1ll_dataout : STD_LOGIC; + SIGNAL wire_ni11l1lO_dataout : STD_LOGIC; + SIGNAL wire_ni11l1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni11l1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni11l1OO_dataout : STD_LOGIC; + SIGNAL wire_ni11li0i_dataout : STD_LOGIC; + SIGNAL wire_ni11li0l_dataout : STD_LOGIC; + SIGNAL wire_ni11li0O_dataout : STD_LOGIC; + SIGNAL wire_ni11li1i_dataout : STD_LOGIC; + SIGNAL wire_ni11li1l_dataout : STD_LOGIC; + SIGNAL wire_ni11li1O_dataout : STD_LOGIC; + SIGNAL wire_ni11liii_dataout : STD_LOGIC; + SIGNAL wire_ni11liil_dataout : STD_LOGIC; + SIGNAL wire_ni11liiO_dataout : STD_LOGIC; + SIGNAL wire_ni11lili_dataout : STD_LOGIC; + SIGNAL wire_ni11lill_dataout : STD_LOGIC; + SIGNAL wire_ni11lilO_dataout : STD_LOGIC; + SIGNAL wire_ni11liOi_dataout : STD_LOGIC; + SIGNAL wire_ni11liOl_dataout : STD_LOGIC; + SIGNAL wire_ni11liOO_dataout : STD_LOGIC; + SIGNAL wire_ni11ll0i_dataout : STD_LOGIC; + SIGNAL wire_ni11ll0l_dataout : STD_LOGIC; + SIGNAL wire_ni11ll0O_dataout : STD_LOGIC; + SIGNAL wire_ni11ll1i_dataout : STD_LOGIC; + SIGNAL wire_ni11ll1l_dataout : STD_LOGIC; + SIGNAL wire_ni11ll1O_dataout : STD_LOGIC; + SIGNAL wire_ni11llii_dataout : STD_LOGIC; + SIGNAL wire_ni11llil_dataout : STD_LOGIC; + SIGNAL wire_ni11lliO_dataout : STD_LOGIC; + SIGNAL wire_ni11llli_dataout : STD_LOGIC; + SIGNAL wire_ni11llll_dataout : STD_LOGIC; + SIGNAL wire_ni11lOli_dataout : STD_LOGIC; + SIGNAL wire_ni11lOll_dataout : STD_LOGIC; + SIGNAL wire_ni11lOlO_dataout : STD_LOGIC; + SIGNAL wire_ni11lOOi_dataout : STD_LOGIC; + SIGNAL wire_ni11lOOl_dataout : STD_LOGIC; + SIGNAL wire_ni11lOOO_dataout : STD_LOGIC; + SIGNAL wire_ni11O00i_dataout : STD_LOGIC; + SIGNAL wire_ni11O00l_dataout : STD_LOGIC; + SIGNAL wire_ni11O00O_dataout : STD_LOGIC; + SIGNAL wire_ni11O01i_dataout : STD_LOGIC; + SIGNAL wire_ni11O01l_dataout : STD_LOGIC; + SIGNAL wire_ni11O01O_dataout : STD_LOGIC; + SIGNAL wire_ni11O0i_dataout : STD_LOGIC; + SIGNAL wire_ni11O0l_dataout : STD_LOGIC; + SIGNAL wire_ni11O0O_dataout : STD_LOGIC; + SIGNAL wire_ni11O10i_dataout : STD_LOGIC; + SIGNAL wire_ni11O10l_dataout : STD_LOGIC; + SIGNAL wire_ni11O10O_dataout : STD_LOGIC; + SIGNAL wire_ni11O11i_dataout : STD_LOGIC; + SIGNAL wire_ni11O11l_dataout : STD_LOGIC; + SIGNAL wire_ni11O11O_dataout : STD_LOGIC; + SIGNAL wire_ni11O1ii_dataout : STD_LOGIC; + SIGNAL wire_ni11O1il_dataout : STD_LOGIC; + SIGNAL wire_ni11O1iO_dataout : STD_LOGIC; + SIGNAL wire_ni11O1l_dataout : STD_LOGIC; + SIGNAL wire_ni11O1li_dataout : STD_LOGIC; + SIGNAL wire_ni11O1ll_dataout : STD_LOGIC; + SIGNAL wire_ni11O1lO_dataout : STD_LOGIC; + SIGNAL wire_ni11O1O_dataout : STD_LOGIC; + SIGNAL wire_ni11O1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni11O1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni11O1OO_dataout : STD_LOGIC; + SIGNAL wire_ni11Oi0l_dataout : STD_LOGIC; + SIGNAL wire_ni11Oi0O_dataout : STD_LOGIC; + SIGNAL wire_ni11Oii_dataout : STD_LOGIC; + SIGNAL wire_ni11Oiii_dataout : STD_LOGIC; + SIGNAL wire_ni11Oiil_dataout : STD_LOGIC; + SIGNAL wire_ni11OiiO_dataout : STD_LOGIC; + SIGNAL wire_ni11Oil_dataout : STD_LOGIC; + SIGNAL wire_ni11Oili_dataout : STD_LOGIC; + SIGNAL wire_ni11Oill_dataout : STD_LOGIC; + SIGNAL wire_ni11OilO_dataout : STD_LOGIC; + SIGNAL wire_ni11OiO_dataout : STD_LOGIC; + SIGNAL wire_ni11OiOi_dataout : STD_LOGIC; + SIGNAL wire_ni11OiOl_dataout : STD_LOGIC; + SIGNAL wire_ni11OiOO_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol0i_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol0l_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol0O_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol1i_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol1l_dataout : STD_LOGIC; + SIGNAL wire_ni11Ol1O_dataout : STD_LOGIC; + SIGNAL wire_ni11Oli_dataout : STD_LOGIC; + SIGNAL wire_ni11Olii_dataout : STD_LOGIC; + SIGNAL wire_ni11Olil_dataout : STD_LOGIC; + SIGNAL wire_ni11OliO_dataout : STD_LOGIC; + SIGNAL wire_ni11Oll_dataout : STD_LOGIC; + SIGNAL wire_ni11Olli_dataout : STD_LOGIC; + SIGNAL wire_ni11Olll_dataout : STD_LOGIC; + SIGNAL wire_ni11OllO_dataout : STD_LOGIC; + SIGNAL wire_ni11OlO_dataout : STD_LOGIC; + SIGNAL wire_ni11OlOi_dataout : STD_LOGIC; + SIGNAL wire_ni11OlOl_dataout : STD_LOGIC; + SIGNAL wire_ni11OlOO_dataout : STD_LOGIC; + SIGNAL wire_ni11OO1i_dataout : STD_LOGIC; + SIGNAL wire_ni11OOi_dataout : STD_LOGIC; + SIGNAL wire_ni11OOl_dataout : STD_LOGIC; + SIGNAL wire_ni11OOO_dataout : STD_LOGIC; + SIGNAL wire_ni11OOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1i000i_dataout : STD_LOGIC; + SIGNAL wire_ni1i000l_dataout : STD_LOGIC; + SIGNAL wire_ni1i000O_dataout : STD_LOGIC; + SIGNAL wire_ni1i001i_dataout : STD_LOGIC; + SIGNAL wire_ni1i001l_dataout : STD_LOGIC; + SIGNAL wire_ni1i001O_dataout : STD_LOGIC; + SIGNAL wire_ni1i00i_dataout : STD_LOGIC; + SIGNAL wire_ni1i00ii_dataout : STD_LOGIC; + SIGNAL wire_ni1i00il_dataout : STD_LOGIC; + SIGNAL wire_ni1i00iO_dataout : STD_LOGIC; + SIGNAL wire_ni1i00li_dataout : STD_LOGIC; + SIGNAL wire_ni1i00ll_dataout : STD_LOGIC; + SIGNAL wire_ni1i00lO_dataout : STD_LOGIC; + SIGNAL wire_ni1i00Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1i00Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1i00OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i011i_dataout : STD_LOGIC; + SIGNAL wire_ni1i011l_dataout : STD_LOGIC; + SIGNAL wire_ni1i011O_dataout : STD_LOGIC; + SIGNAL wire_ni1i01i_dataout : STD_LOGIC; + SIGNAL wire_ni1i01l_dataout : STD_LOGIC; + SIGNAL wire_ni1i01O_dataout : STD_LOGIC; + SIGNAL wire_ni1i01Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1i01OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i0i_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i0l_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i1i_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i1l_dataout : STD_LOGIC; + SIGNAL wire_ni1i0i1O_dataout : STD_LOGIC; + SIGNAL wire_ni1i0iii_dataout : STD_LOGIC; + SIGNAL wire_ni1i0iil_dataout : STD_LOGIC; + SIGNAL wire_ni1i0iiO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0ili_dataout : STD_LOGIC; + SIGNAL wire_ni1i0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0li_dataout : STD_LOGIC; + SIGNAL wire_ni1i0liO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1i0lli_dataout : STD_LOGIC; + SIGNAL wire_ni1i0lll_dataout : STD_LOGIC; + SIGNAL wire_ni1i0llO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0lOi_dataout : STD_LOGIC; + SIGNAL wire_ni1i0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni1i0lOO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O0i_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O0l_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O1i_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O1l_dataout : STD_LOGIC; + SIGNAL wire_ni1i0O1O_dataout : STD_LOGIC; + SIGNAL wire_ni1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1i0Oii_dataout : STD_LOGIC; + SIGNAL wire_ni1i0Oil_dataout : STD_LOGIC; + SIGNAL wire_ni1i0OiO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1i0Oli_dataout : STD_LOGIC; + SIGNAL wire_ni1i0Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1i0OlO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i0OOi_dataout : STD_LOGIC; + SIGNAL wire_ni1i0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni1i0OOO_dataout : STD_LOGIC; + SIGNAL wire_ni1i100i_dataout : STD_LOGIC; + SIGNAL wire_ni1i100l_dataout : STD_LOGIC; + SIGNAL wire_ni1i100O_dataout : STD_LOGIC; + SIGNAL wire_ni1i101i_dataout : STD_LOGIC; + SIGNAL wire_ni1i10i_dataout : STD_LOGIC; + SIGNAL wire_ni1i10ii_dataout : STD_LOGIC; + SIGNAL wire_ni1i10il_dataout : STD_LOGIC; + SIGNAL wire_ni1i10iO_dataout : STD_LOGIC; + SIGNAL wire_ni1i10l_dataout : STD_LOGIC; + SIGNAL wire_ni1i10li_dataout : STD_LOGIC; + SIGNAL wire_ni1i10ll_dataout : STD_LOGIC; + SIGNAL wire_ni1i10lO_dataout : STD_LOGIC; + SIGNAL wire_ni1i10O_dataout : STD_LOGIC; + SIGNAL wire_ni1i10Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1i10Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1i10OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i111i_dataout : STD_LOGIC; + SIGNAL wire_ni1i111l_dataout : STD_LOGIC; + SIGNAL wire_ni1i111O_dataout : STD_LOGIC; + SIGNAL wire_ni1i11i_dataout : STD_LOGIC; + SIGNAL wire_ni1i11l_dataout : STD_LOGIC; + SIGNAL wire_ni1i11lO_dataout : STD_LOGIC; + SIGNAL wire_ni1i11O_dataout : STD_LOGIC; + SIGNAL wire_ni1i11Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1i11Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1i11OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1i1il_dataout : STD_LOGIC; + SIGNAL wire_ni1i1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1li_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lii_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lil_dataout : STD_LOGIC; + SIGNAL wire_ni1i1liO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lli_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lll_dataout : STD_LOGIC; + SIGNAL wire_ni1i1llO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lOi_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lOl_dataout : STD_LOGIC; + SIGNAL wire_ni1i1lOO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O0i_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O0l_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O0O_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O1i_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O1l_dataout : STD_LOGIC; + SIGNAL wire_ni1i1O1O_dataout : STD_LOGIC; + SIGNAL wire_ni1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1i1Oii_dataout : STD_LOGIC; + SIGNAL wire_ni1i1Oil_dataout : STD_LOGIC; + SIGNAL wire_ni1i1OiO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1i1Oli_dataout : STD_LOGIC; + SIGNAL wire_ni1i1Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1i1OlO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1i1OOi_dataout : STD_LOGIC; + SIGNAL wire_ni1i1OOl_dataout : STD_LOGIC; + SIGNAL wire_ni1i1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni1ii00i_dataout : STD_LOGIC; + SIGNAL wire_ni1ii00l_dataout : STD_LOGIC; + SIGNAL wire_ni1ii00O_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0i_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0il_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0l_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0li_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1ii0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1ii10i_dataout : STD_LOGIC; + SIGNAL wire_ni1ii10l_dataout : STD_LOGIC; + SIGNAL wire_ni1ii11i_dataout : STD_LOGIC; + SIGNAL wire_ni1ii11l_dataout : STD_LOGIC; + SIGNAL wire_ni1ii11O_dataout : STD_LOGIC; + SIGNAL wire_ni1ii1i_dataout : STD_LOGIC; + SIGNAL wire_ni1ii1l_dataout : STD_LOGIC; + SIGNAL wire_ni1ii1O_dataout : STD_LOGIC; + SIGNAL wire_ni1iii0i_dataout : STD_LOGIC; + SIGNAL wire_ni1iii0l_dataout : STD_LOGIC; + SIGNAL wire_ni1iii0O_dataout : STD_LOGIC; + SIGNAL wire_ni1iii1i_dataout : STD_LOGIC; + SIGNAL wire_ni1iii1l_dataout : STD_LOGIC; + SIGNAL wire_ni1iii1O_dataout : STD_LOGIC; + SIGNAL wire_ni1iiiii_dataout : STD_LOGIC; + SIGNAL wire_ni1iiiil_dataout : STD_LOGIC; + SIGNAL wire_ni1iiiiO_dataout : STD_LOGIC; + SIGNAL wire_ni1iiili_dataout : STD_LOGIC; + SIGNAL wire_ni1iiill_dataout : STD_LOGIC; + SIGNAL wire_ni1iiilO_dataout : STD_LOGIC; + SIGNAL wire_ni1iiiOi_dataout : STD_LOGIC; + SIGNAL wire_ni1iiiOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iiiOO_dataout : STD_LOGIC; + SIGNAL wire_ni1iilOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iilOO_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO0i_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1iiO1O_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOii_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOil_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOiO_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOli_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOll_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOlO_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOOi_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iiOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1il0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1il0li_dataout : STD_LOGIC; + SIGNAL wire_ni1il0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1il0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1il0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1il0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1il0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1il10i_dataout : STD_LOGIC; + SIGNAL wire_ni1il10l_dataout : STD_LOGIC; + SIGNAL wire_ni1il10O_dataout : STD_LOGIC; + SIGNAL wire_ni1il11i_dataout : STD_LOGIC; + SIGNAL wire_ni1il11l_dataout : STD_LOGIC; + SIGNAL wire_ni1il11O_dataout : STD_LOGIC; + SIGNAL wire_ni1il1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1il1il_dataout : STD_LOGIC; + SIGNAL wire_ni1il1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1il1li_dataout : STD_LOGIC; + SIGNAL wire_ni1ili0i_dataout : STD_LOGIC; + SIGNAL wire_ni1ili0l_dataout : STD_LOGIC; + SIGNAL wire_ni1ili0O_dataout : STD_LOGIC; + SIGNAL wire_ni1ili1i_dataout : STD_LOGIC; + SIGNAL wire_ni1ili1l_dataout : STD_LOGIC; + SIGNAL wire_ni1ili1O_dataout : STD_LOGIC; + SIGNAL wire_ni1iliii_dataout : STD_LOGIC; + SIGNAL wire_ni1iliil_dataout : STD_LOGIC; + SIGNAL wire_ni1iliiO_dataout : STD_LOGIC; + SIGNAL wire_ni1ilili_dataout : STD_LOGIC; + SIGNAL wire_ni1ilill_dataout : STD_LOGIC; + SIGNAL wire_ni1ililO_dataout : STD_LOGIC; + SIGNAL wire_ni1iliOi_dataout : STD_LOGIC; + SIGNAL wire_ni1iliOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iliOO_dataout : STD_LOGIC; + SIGNAL wire_ni1ill0i_dataout : STD_LOGIC; + SIGNAL wire_ni1ill0l_dataout : STD_LOGIC; + SIGNAL wire_ni1ill1i_dataout : STD_LOGIC; + SIGNAL wire_ni1ill1l_dataout : STD_LOGIC; + SIGNAL wire_ni1ill1O_dataout : STD_LOGIC; + SIGNAL wire_ni1ilO0i_dataout : STD_LOGIC; + SIGNAL wire_ni1ilO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1ilO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOii_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOil_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOiO_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOl_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOl_w_lg_dataout2737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1ilOl_w_lg_dataout2826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_ni1ilOli_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOll_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOlO_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOO_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOOi_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOOl_dataout : STD_LOGIC; + SIGNAL wire_ni1ilOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1iO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1iO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1iO0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1iO10i_dataout : STD_LOGIC; + SIGNAL wire_ni1iO10l_dataout : STD_LOGIC; + SIGNAL wire_ni1iO10O_dataout : STD_LOGIC; + SIGNAL wire_ni1iO11i_dataout : STD_LOGIC; + SIGNAL wire_ni1iO11l_dataout : STD_LOGIC; + SIGNAL wire_ni1iO11O_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1il_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1li_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1O_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1iO1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi0i_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi0l_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi0O_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi1i_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi1l_dataout : STD_LOGIC; + SIGNAL wire_ni1iOi1O_dataout : STD_LOGIC; + SIGNAL wire_ni1iOiii_dataout : STD_LOGIC; + SIGNAL wire_ni1iOiil_dataout : STD_LOGIC; + SIGNAL wire_ni1iOiiO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOili_dataout : STD_LOGIC; + SIGNAL wire_ni1iOill_dataout : STD_LOGIC; + SIGNAL wire_ni1iOilO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOiOi_dataout : STD_LOGIC; + SIGNAL wire_ni1iOiOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iOiOO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl0i_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl0l_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl0O_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl1i_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl1l_dataout : STD_LOGIC; + SIGNAL wire_ni1iOl1O_dataout : STD_LOGIC; + SIGNAL wire_ni1iOlii_dataout : STD_LOGIC; + SIGNAL wire_ni1iOlil_dataout : STD_LOGIC; + SIGNAL wire_ni1iOliO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOlli_dataout : STD_LOGIC; + SIGNAL wire_ni1iOO0i_dataout : STD_LOGIC; + SIGNAL wire_ni1iOO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1iOO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1iOOii_dataout : STD_LOGIC; + SIGNAL wire_ni1iOOil_dataout : STD_LOGIC; + SIGNAL wire_ni1iOOll_dataout : STD_LOGIC; + SIGNAL wire_ni1iOOlO_dataout : STD_LOGIC; + SIGNAL wire_ni1iOOOi_dataout : STD_LOGIC; + SIGNAL wire_ni1iOOOl_dataout : STD_LOGIC; + SIGNAL wire_ni1iOOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1l001i_dataout : STD_LOGIC; + SIGNAL wire_ni1l001l_dataout : STD_LOGIC; + SIGNAL wire_ni1l010i_dataout : STD_LOGIC; + SIGNAL wire_ni1l010l_dataout : STD_LOGIC; + SIGNAL wire_ni1l010O_dataout : STD_LOGIC; + SIGNAL wire_ni1l011i_dataout : STD_LOGIC; + SIGNAL wire_ni1l011l_dataout : STD_LOGIC; + SIGNAL wire_ni1l011O_dataout : STD_LOGIC; + SIGNAL wire_ni1l01ii_dataout : STD_LOGIC; + SIGNAL wire_ni1l01il_dataout : STD_LOGIC; + SIGNAL wire_ni1l01iO_dataout : STD_LOGIC; + SIGNAL wire_ni1l01li_dataout : STD_LOGIC; + SIGNAL wire_ni1l01ll_dataout : STD_LOGIC; + SIGNAL wire_ni1l01lO_dataout : STD_LOGIC; + SIGNAL wire_ni1l01Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1l01Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1l01OO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i0i_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i0l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0i1O_dataout : STD_LOGIC; + SIGNAL wire_ni1l0iii_dataout : STD_LOGIC; + SIGNAL wire_ni1l0iil_dataout : STD_LOGIC; + SIGNAL wire_ni1l0iiO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0ili_dataout : STD_LOGIC; + SIGNAL wire_ni1l0ill_dataout : STD_LOGIC; + SIGNAL wire_ni1l0ilO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0iOi_dataout : STD_LOGIC; + SIGNAL wire_ni1l0iOl_dataout : STD_LOGIC; + SIGNAL wire_ni1l0iOO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l0i_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l0l1O_dataout : STD_LOGIC; + SIGNAL wire_ni1l0li_dataout : STD_LOGIC; + SIGNAL wire_ni1l0lii_dataout : STD_LOGIC; + SIGNAL wire_ni1l0lil_dataout : STD_LOGIC; + SIGNAL wire_ni1l0liO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1l0lli_dataout : STD_LOGIC; + SIGNAL wire_ni1l0lll_dataout : STD_LOGIC; + SIGNAL wire_ni1l0llO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1l0Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1l0OlO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1l0OOi_dataout : STD_LOGIC; + SIGNAL wire_ni1l0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni1l0OOO_dataout : STD_LOGIC; + SIGNAL wire_ni1l10i_dataout : STD_LOGIC; + SIGNAL wire_ni1l10l_dataout : STD_LOGIC; + SIGNAL wire_ni1l10O_dataout : STD_LOGIC; + SIGNAL wire_ni1l10Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1l10OO_dataout : STD_LOGIC; + SIGNAL wire_ni1l110i_dataout : STD_LOGIC; + SIGNAL wire_ni1l110l_dataout : STD_LOGIC; + SIGNAL wire_ni1l110O_dataout : STD_LOGIC; + SIGNAL wire_ni1l111i_dataout : STD_LOGIC; + SIGNAL wire_ni1l111l_dataout : STD_LOGIC; + SIGNAL wire_ni1l111O_dataout : STD_LOGIC; + SIGNAL wire_ni1l11ii_dataout : STD_LOGIC; + SIGNAL wire_ni1l11O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i0i_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i0l_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l1i1O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1l1iii_dataout : STD_LOGIC; + SIGNAL wire_ni1l1iil_dataout : STD_LOGIC; + SIGNAL wire_ni1l1iiO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1il_dataout : STD_LOGIC; + SIGNAL wire_ni1l1ili_dataout : STD_LOGIC; + SIGNAL wire_ni1l1ill_dataout : STD_LOGIC; + SIGNAL wire_ni1l1ilO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1iOi_dataout : STD_LOGIC; + SIGNAL wire_ni1l1iOl_dataout : STD_LOGIC; + SIGNAL wire_ni1l1iOO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l0i_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l0l_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l1i_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l1l_dataout : STD_LOGIC; + SIGNAL wire_ni1l1l1O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1li_dataout : STD_LOGIC; + SIGNAL wire_ni1l1lii_dataout : STD_LOGIC; + SIGNAL wire_ni1l1lil_dataout : STD_LOGIC; + SIGNAL wire_ni1l1liO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1l1lli_dataout : STD_LOGIC; + SIGNAL wire_ni1l1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1O0O_dataout : STD_LOGIC; + SIGNAL wire_ni1l1Oii_dataout : STD_LOGIC; + SIGNAL wire_ni1l1Oil_dataout : STD_LOGIC; + SIGNAL wire_ni1l1OiO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1Oli_dataout : STD_LOGIC; + SIGNAL wire_ni1l1Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1l1OlO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1l1OOi_dataout : STD_LOGIC; + SIGNAL wire_ni1l1OOl_dataout : STD_LOGIC; + SIGNAL wire_ni1l1OOO_dataout : STD_LOGIC; + SIGNAL wire_ni1li00i_dataout : STD_LOGIC; + SIGNAL wire_ni1li00l_dataout : STD_LOGIC; + SIGNAL wire_ni1li00O_dataout : STD_LOGIC; + SIGNAL wire_ni1li01i_dataout : STD_LOGIC; + SIGNAL wire_ni1li01l_dataout : STD_LOGIC; + SIGNAL wire_ni1li01O_dataout : STD_LOGIC; + SIGNAL wire_ni1li0i_dataout : STD_LOGIC; + SIGNAL wire_ni1li0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1li0l_dataout : STD_LOGIC; + SIGNAL wire_ni1li0O_dataout : STD_LOGIC; + SIGNAL wire_ni1li10i_dataout : STD_LOGIC; + SIGNAL wire_ni1li10l_dataout : STD_LOGIC; + SIGNAL wire_ni1li10O_dataout : STD_LOGIC; + SIGNAL wire_ni1li11i_dataout : STD_LOGIC; + SIGNAL wire_ni1li11l_dataout : STD_LOGIC; + SIGNAL wire_ni1li11O_dataout : STD_LOGIC; + SIGNAL wire_ni1li1i_dataout : STD_LOGIC; + SIGNAL wire_ni1li1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1li1il_dataout : STD_LOGIC; + SIGNAL wire_ni1li1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1li1li_dataout : STD_LOGIC; + SIGNAL wire_ni1li1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1li1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1li1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1li1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1li1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1lii0O_dataout : STD_LOGIC; + SIGNAL wire_ni1liii_dataout : STD_LOGIC; + SIGNAL wire_ni1liiii_dataout : STD_LOGIC; + SIGNAL wire_ni1liiil_dataout : STD_LOGIC; + SIGNAL wire_ni1liiiO_dataout : STD_LOGIC; + SIGNAL wire_ni1liil_dataout : STD_LOGIC; + SIGNAL wire_ni1liili_dataout : STD_LOGIC; + SIGNAL wire_ni1liill_dataout : STD_LOGIC; + SIGNAL wire_ni1liilO_dataout : STD_LOGIC; + SIGNAL wire_ni1liiO_dataout : STD_LOGIC; + SIGNAL wire_ni1liiOi_dataout : STD_LOGIC; + SIGNAL wire_ni1liiOl_dataout : STD_LOGIC; + SIGNAL wire_ni1liiOO_dataout : STD_LOGIC; + SIGNAL wire_ni1lil0i_dataout : STD_LOGIC; + SIGNAL wire_ni1lil0l_dataout : STD_LOGIC; + SIGNAL wire_ni1lil0O_dataout : STD_LOGIC; + SIGNAL wire_ni1lil1i_dataout : STD_LOGIC; + SIGNAL wire_ni1lil1l_dataout : STD_LOGIC; + SIGNAL wire_ni1lil1O_dataout : STD_LOGIC; + SIGNAL wire_ni1lili_dataout : STD_LOGIC; + SIGNAL wire_ni1lilii_dataout : STD_LOGIC; + SIGNAL wire_ni1lilil_dataout : STD_LOGIC; + SIGNAL wire_ni1liliO_dataout : STD_LOGIC; + SIGNAL wire_ni1lill_dataout : STD_LOGIC; + SIGNAL wire_ni1lilli_dataout : STD_LOGIC; + SIGNAL wire_ni1lilll_dataout : STD_LOGIC; + SIGNAL wire_ni1lillO_dataout : STD_LOGIC; + SIGNAL wire_ni1lilO_dataout : STD_LOGIC; + SIGNAL wire_ni1lilOi_dataout : STD_LOGIC; + SIGNAL wire_ni1lilOl_dataout : STD_LOGIC; + SIGNAL wire_ni1lilOO_dataout : STD_LOGIC; + SIGNAL wire_ni1liO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1liO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1liOi_dataout : STD_LOGIC; + SIGNAL wire_ni1liOl_dataout : STD_LOGIC; + SIGNAL wire_ni1liOO_dataout : STD_LOGIC; + SIGNAL wire_ni1ll00i_dataout : STD_LOGIC; + SIGNAL wire_ni1ll00l_dataout : STD_LOGIC; + SIGNAL wire_ni1ll00O_dataout : STD_LOGIC; + SIGNAL wire_ni1ll01i_dataout : STD_LOGIC; + SIGNAL wire_ni1ll01l_dataout : STD_LOGIC; + SIGNAL wire_ni1ll01O_dataout : STD_LOGIC; + SIGNAL wire_ni1ll0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1ll0il_dataout : STD_LOGIC; + SIGNAL wire_ni1ll0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1ll0li_dataout : STD_LOGIC; + SIGNAL wire_ni1ll0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1ll0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1ll10i_dataout : STD_LOGIC; + SIGNAL wire_ni1ll10l_dataout : STD_LOGIC; + SIGNAL wire_ni1ll10O_dataout : STD_LOGIC; + SIGNAL wire_ni1ll11i_dataout : STD_LOGIC; + SIGNAL wire_ni1ll11l_dataout : STD_LOGIC; + SIGNAL wire_ni1ll11O_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1i_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1il_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1li_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1ll1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1llill_dataout : STD_LOGIC; + SIGNAL wire_ni1llilO_dataout : STD_LOGIC; + SIGNAL wire_ni1lliOi_dataout : STD_LOGIC; + SIGNAL wire_ni1lliOl_dataout : STD_LOGIC; + SIGNAL wire_ni1lliOO_dataout : STD_LOGIC; + SIGNAL wire_ni1lll0i_dataout : STD_LOGIC; + SIGNAL wire_ni1lll0l_dataout : STD_LOGIC; + SIGNAL wire_ni1lll0O_dataout : STD_LOGIC; + SIGNAL wire_ni1lll1i_dataout : STD_LOGIC; + SIGNAL wire_ni1lll1l_dataout : STD_LOGIC; + SIGNAL wire_ni1lll1O_dataout : STD_LOGIC; + SIGNAL wire_ni1lllii_dataout : STD_LOGIC; + SIGNAL wire_ni1lllil_dataout : STD_LOGIC; + SIGNAL wire_ni1llliO_dataout : STD_LOGIC; + SIGNAL wire_ni1lllli_dataout : STD_LOGIC; + SIGNAL wire_ni1lllll_dataout : STD_LOGIC; + SIGNAL wire_ni1llllO_dataout : STD_LOGIC; + SIGNAL wire_ni1lllOi_dataout : STD_LOGIC; + SIGNAL wire_ni1lllOl_dataout : STD_LOGIC; + SIGNAL wire_ni1lllOO_dataout : STD_LOGIC; + SIGNAL wire_ni1llO0i_dataout : STD_LOGIC; + SIGNAL wire_ni1llO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1llO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1llO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1llO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1llO1O_dataout : STD_LOGIC; + SIGNAL wire_ni1llOii_dataout : STD_LOGIC; + SIGNAL wire_ni1lO00i_dataout : STD_LOGIC; + SIGNAL wire_ni1lO00l_dataout : STD_LOGIC; + SIGNAL wire_ni1lO00O_dataout : STD_LOGIC; + SIGNAL wire_ni1lO01i_dataout : STD_LOGIC; + SIGNAL wire_ni1lO01l_dataout : STD_LOGIC; + SIGNAL wire_ni1lO01O_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0il_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0li_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1lO0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1lO10O_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1il_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1li_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1lO1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1lOi1i_dataout : STD_LOGIC; + SIGNAL wire_ni1lOi1l_dataout : STD_LOGIC; + SIGNAL wire_ni1lOill_dataout : STD_LOGIC; + SIGNAL wire_ni1lOilO_dataout : STD_LOGIC; + SIGNAL wire_ni1lOiOi_dataout : STD_LOGIC; + SIGNAL wire_ni1lOiOl_dataout : STD_LOGIC; + SIGNAL wire_ni1lOiOO_dataout : STD_LOGIC; + SIGNAL wire_ni1lOl0i_dataout : STD_LOGIC; + SIGNAL wire_ni1lOl0l_dataout : STD_LOGIC; + SIGNAL wire_ni1lOl0O_dataout : STD_LOGIC; + SIGNAL wire_ni1lOl1O_dataout : STD_LOGIC; + SIGNAL wire_ni1lOlii_dataout : STD_LOGIC; + SIGNAL wire_ni1lOlil_dataout : STD_LOGIC; + SIGNAL wire_ni1lOliO_dataout : STD_LOGIC; + SIGNAL wire_ni1lOlli_dataout : STD_LOGIC; + SIGNAL wire_ni1lOlll_dataout : STD_LOGIC; + SIGNAL wire_ni1lOllO_dataout : STD_LOGIC; + SIGNAL wire_ni1lOlOi_dataout : STD_LOGIC; + SIGNAL wire_ni1lOlOl_dataout : STD_LOGIC; + SIGNAL wire_ni1lOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1O000i_dataout : STD_LOGIC; + SIGNAL wire_ni1O000l_dataout : STD_LOGIC; + SIGNAL wire_ni1O000O_dataout : STD_LOGIC; + SIGNAL wire_ni1O001i_dataout : STD_LOGIC; + SIGNAL wire_ni1O001l_dataout : STD_LOGIC; + SIGNAL wire_ni1O001O_dataout : STD_LOGIC; + SIGNAL wire_ni1O00i_dataout : STD_LOGIC; + SIGNAL wire_ni1O00ii_dataout : STD_LOGIC; + SIGNAL wire_ni1O00il_dataout : STD_LOGIC; + SIGNAL wire_ni1O00iO_dataout : STD_LOGIC; + SIGNAL wire_ni1O00l_dataout : STD_LOGIC; + SIGNAL wire_ni1O00li_dataout : STD_LOGIC; + SIGNAL wire_ni1O00ll_dataout : STD_LOGIC; + SIGNAL wire_ni1O00lO_dataout : STD_LOGIC; + SIGNAL wire_ni1O00O_dataout : STD_LOGIC; + SIGNAL wire_ni1O00Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1O00Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1O00OO_dataout : STD_LOGIC; + SIGNAL wire_ni1O01i_dataout : STD_LOGIC; + SIGNAL wire_ni1O01il_dataout : STD_LOGIC; + SIGNAL wire_ni1O01iO_dataout : STD_LOGIC; + SIGNAL wire_ni1O01l_dataout : STD_LOGIC; + SIGNAL wire_ni1O01li_dataout : STD_LOGIC; + SIGNAL wire_ni1O01ll_dataout : STD_LOGIC; + SIGNAL wire_ni1O01lO_dataout : STD_LOGIC; + SIGNAL wire_ni1O01O_dataout : STD_LOGIC; + SIGNAL wire_ni1O01Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1O01Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1O01OO_dataout : STD_LOGIC; + SIGNAL wire_ni1O0i0i_dataout : STD_LOGIC; + SIGNAL wire_ni1O0i1i_dataout : STD_LOGIC; + SIGNAL wire_ni1O0i1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O0i1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1O0il_dataout : STD_LOGIC; + SIGNAL wire_ni1O0l0i_dataout : STD_LOGIC; + SIGNAL wire_ni1O0l0l_dataout : STD_LOGIC; + SIGNAL wire_ni1O0l0O_dataout : STD_LOGIC; + SIGNAL wire_ni1O0l1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O0lii_dataout : STD_LOGIC; + SIGNAL wire_ni1O0lil_dataout : STD_LOGIC; + SIGNAL wire_ni1O0liO_dataout : STD_LOGIC; + SIGNAL wire_ni1O0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1O0lli_dataout : STD_LOGIC; + SIGNAL wire_ni1O0lll_dataout : STD_LOGIC; + SIGNAL wire_ni1O0llO_dataout : STD_LOGIC; + SIGNAL wire_ni1O0lOi_dataout : STD_LOGIC; + SIGNAL wire_ni1O0lOl_dataout : STD_LOGIC; + SIGNAL wire_ni1O0lOO_dataout : STD_LOGIC; + SIGNAL wire_ni1O0O0i_dataout : STD_LOGIC; + SIGNAL wire_ni1O0O0l_dataout : STD_LOGIC; + SIGNAL wire_ni1O0O0O_dataout : STD_LOGIC; + SIGNAL wire_ni1O0O1i_dataout : STD_LOGIC; + SIGNAL wire_ni1O0O1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O0O1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O0Oii_dataout : STD_LOGIC; + SIGNAL wire_ni1O0Oil_dataout : STD_LOGIC; + SIGNAL wire_ni1O0OiO_dataout : STD_LOGIC; + SIGNAL wire_ni1O0Oli_dataout : STD_LOGIC; + SIGNAL wire_ni1O0Oll_dataout : STD_LOGIC; + SIGNAL wire_ni1O0OlO_dataout : STD_LOGIC; + SIGNAL wire_ni1O0OOi_dataout : STD_LOGIC; + SIGNAL wire_ni1O0OOl_dataout : STD_LOGIC; + SIGNAL wire_ni1O100i_dataout : STD_LOGIC; + SIGNAL wire_ni1O100l_dataout : STD_LOGIC; + SIGNAL wire_ni1O100O_dataout : STD_LOGIC; + SIGNAL wire_ni1O101i_dataout : STD_LOGIC; + SIGNAL wire_ni1O101l_dataout : STD_LOGIC; + SIGNAL wire_ni1O101O_dataout : STD_LOGIC; + SIGNAL wire_ni1O10i_dataout : STD_LOGIC; + SIGNAL wire_ni1O10ii_dataout : STD_LOGIC; + SIGNAL wire_ni1O10il_dataout : STD_LOGIC; + SIGNAL wire_ni1O10iO_dataout : STD_LOGIC; + SIGNAL wire_ni1O10l_dataout : STD_LOGIC; + SIGNAL wire_ni1O10li_dataout : STD_LOGIC; + SIGNAL wire_ni1O10ll_dataout : STD_LOGIC; + SIGNAL wire_ni1O10lO_dataout : STD_LOGIC; + SIGNAL wire_ni1O10O_dataout : STD_LOGIC; + SIGNAL wire_ni1O10Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1O10Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1O10OO_dataout : STD_LOGIC; + SIGNAL wire_ni1O110O_dataout : STD_LOGIC; + SIGNAL wire_ni1O11i_dataout : STD_LOGIC; + SIGNAL wire_ni1O11ii_dataout : STD_LOGIC; + SIGNAL wire_ni1O11il_dataout : STD_LOGIC; + SIGNAL wire_ni1O11iO_dataout : STD_LOGIC; + SIGNAL wire_ni1O11l_dataout : STD_LOGIC; + SIGNAL wire_ni1O11li_dataout : STD_LOGIC; + SIGNAL wire_ni1O11ll_dataout : STD_LOGIC; + SIGNAL wire_ni1O11lO_dataout : STD_LOGIC; + SIGNAL wire_ni1O11O_dataout : STD_LOGIC; + SIGNAL wire_ni1O11Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1O11Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1O11OO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1i1i_dataout : STD_LOGIC; + SIGNAL wire_ni1O1i1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1O1il_dataout : STD_LOGIC; + SIGNAL wire_ni1O1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1iOi_dataout : STD_LOGIC; + SIGNAL wire_ni1O1iOl_dataout : STD_LOGIC; + SIGNAL wire_ni1O1iOO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l0i_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l0l_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l0O_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l1i_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O1l1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O1li_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lii_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lil_dataout : STD_LOGIC; + SIGNAL wire_ni1O1liO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1ll_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lli_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lll_dataout : STD_LOGIC; + SIGNAL wire_ni1O1llO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lOi_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lOl_dataout : STD_LOGIC; + SIGNAL wire_ni1O1lOO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1O0i_dataout : STD_LOGIC; + SIGNAL wire_ni1O1O0l_dataout : STD_LOGIC; + SIGNAL wire_ni1O1O0O_dataout : STD_LOGIC; + SIGNAL wire_ni1O1O1i_dataout : STD_LOGIC; + SIGNAL wire_ni1O1O1l_dataout : STD_LOGIC; + SIGNAL wire_ni1O1O1O_dataout : STD_LOGIC; + SIGNAL wire_ni1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1O1Oii_dataout : STD_LOGIC; + SIGNAL wire_ni1O1Oil_dataout : STD_LOGIC; + SIGNAL wire_ni1O1OiO_dataout : STD_LOGIC; + SIGNAL wire_ni1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1O1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi00i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi00l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi00O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi01i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi01l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi01O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0il_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0li_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii0i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii0l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii0O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii1i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii1l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oii1O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oiii_dataout : STD_LOGIC; + SIGNAL wire_ni1Oiiii_dataout : STD_LOGIC; + SIGNAL wire_ni1Oiiil_dataout : STD_LOGIC; + SIGNAL wire_ni1OiiiO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oiil_dataout : STD_LOGIC; + SIGNAL wire_ni1OiiO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oili_dataout : STD_LOGIC; + SIGNAL wire_ni1Oilil_dataout : STD_LOGIC; + SIGNAL wire_ni1OiliO_dataout : STD_LOGIC; + SIGNAL wire_ni1Oill_dataout : STD_LOGIC; + SIGNAL wire_ni1Oilli_dataout : STD_LOGIC; + SIGNAL wire_ni1Oilll_dataout : STD_LOGIC; + SIGNAL wire_ni1OillO_dataout : STD_LOGIC; + SIGNAL wire_ni1OilO_dataout : STD_LOGIC; + SIGNAL wire_ni1OilOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OilOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OilOO_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO0i_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1OiO1O_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOii_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOil_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOiO_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOli_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOll_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOlO_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOO_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OiOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol00i_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol00l_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol00O_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol01O_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0il_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0li_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol10i_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol11i_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol11l_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol11O_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_ni1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli0i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli0l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli0O_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli1i_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli1l_dataout : STD_LOGIC; + SIGNAL wire_ni1Oli1O_dataout : STD_LOGIC; + SIGNAL wire_ni1Olii_dataout : STD_LOGIC; + SIGNAL wire_ni1Oliii_dataout : STD_LOGIC; + SIGNAL wire_ni1Oliil_dataout : STD_LOGIC; + SIGNAL wire_ni1OliiO_dataout : STD_LOGIC; + SIGNAL wire_ni1Olil_dataout : STD_LOGIC; + SIGNAL wire_ni1Olili_dataout : STD_LOGIC; + SIGNAL wire_ni1Olill_dataout : STD_LOGIC; + SIGNAL wire_ni1OlilO_dataout : STD_LOGIC; + SIGNAL wire_ni1OliO_dataout : STD_LOGIC; + SIGNAL wire_ni1OliOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OliOl_dataout : STD_LOGIC; + SIGNAL wire_ni1Olli_dataout : STD_LOGIC; + SIGNAL wire_ni1Olll_dataout : STD_LOGIC; + SIGNAL wire_ni1OllO_dataout : STD_LOGIC; + SIGNAL wire_ni1OllOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OllOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OllOO_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO0i_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1OlO1O_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOii_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOil_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOiO_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOli_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOll_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOlO_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOO_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OlOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1OO00i_dataout : STD_LOGIC; + SIGNAL wire_ni1OO00l_dataout : STD_LOGIC; + SIGNAL wire_ni1OO00O_dataout : STD_LOGIC; + SIGNAL wire_ni1OO01O_dataout : STD_LOGIC; + SIGNAL wire_ni1OO0ii_dataout : STD_LOGIC; + SIGNAL wire_ni1OO0li_dataout : STD_LOGIC; + SIGNAL wire_ni1OO0ll_dataout : STD_LOGIC; + SIGNAL wire_ni1OO0lO_dataout : STD_LOGIC; + SIGNAL wire_ni1OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_ni1OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_ni1OO0OO_dataout : STD_LOGIC; + SIGNAL wire_ni1OO10i_dataout : STD_LOGIC; + SIGNAL wire_ni1OO10l_dataout : STD_LOGIC; + SIGNAL wire_ni1OO10O_dataout : STD_LOGIC; + SIGNAL wire_ni1OO11i_dataout : STD_LOGIC; + SIGNAL wire_ni1OO11l_dataout : STD_LOGIC; + SIGNAL wire_ni1OO11O_dataout : STD_LOGIC; + SIGNAL wire_ni1OO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1OO1ii_dataout : STD_LOGIC; + SIGNAL wire_ni1OO1il_dataout : STD_LOGIC; + SIGNAL wire_ni1OO1iO_dataout : STD_LOGIC; + SIGNAL wire_ni1OO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1OOi0i_dataout : STD_LOGIC; + SIGNAL wire_ni1OOi0l_dataout : STD_LOGIC; + SIGNAL wire_ni1OOi0O_dataout : STD_LOGIC; + SIGNAL wire_ni1OOi1i_dataout : STD_LOGIC; + SIGNAL wire_ni1OOi1l_dataout : STD_LOGIC; + SIGNAL wire_ni1OOi1O_dataout : STD_LOGIC; + SIGNAL wire_ni1OOlOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OOlOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OOlOO_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO0i_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO0l_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO0O_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO1i_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO1l_dataout : STD_LOGIC; + SIGNAL wire_ni1OOO1O_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOii_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOil_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOiO_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOli_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOll_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOlO_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOO_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOOi_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOOl_dataout : STD_LOGIC; + SIGNAL wire_ni1OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nii0000i_dataout : STD_LOGIC; + SIGNAL wire_nii0000l_dataout : STD_LOGIC; + SIGNAL wire_nii0000O_dataout : STD_LOGIC; + SIGNAL wire_nii0001i_dataout : STD_LOGIC; + SIGNAL wire_nii0001l_dataout : STD_LOGIC; + SIGNAL wire_nii0001O_dataout : STD_LOGIC; + SIGNAL wire_nii000ii_dataout : STD_LOGIC; + SIGNAL wire_nii000il_dataout : STD_LOGIC; + SIGNAL wire_nii000iO_dataout : STD_LOGIC; + SIGNAL wire_nii000li_dataout : STD_LOGIC; + SIGNAL wire_nii000ll_dataout : STD_LOGIC; + SIGNAL wire_nii000lO_dataout : STD_LOGIC; + SIGNAL wire_nii000Oi_dataout : STD_LOGIC; + SIGNAL wire_nii000Ol_dataout : STD_LOGIC; + SIGNAL wire_nii000OO_dataout : STD_LOGIC; + SIGNAL wire_nii0010i_dataout : STD_LOGIC; + SIGNAL wire_nii0010l_dataout : STD_LOGIC; + SIGNAL wire_nii0010O_dataout : STD_LOGIC; + SIGNAL wire_nii0011i_dataout : STD_LOGIC; + SIGNAL wire_nii0011l_dataout : STD_LOGIC; + SIGNAL wire_nii0011O_dataout : STD_LOGIC; + SIGNAL wire_nii001ii_dataout : STD_LOGIC; + SIGNAL wire_nii001il_dataout : STD_LOGIC; + SIGNAL wire_nii001iO_dataout : STD_LOGIC; + SIGNAL wire_nii001li_dataout : STD_LOGIC; + SIGNAL wire_nii001ll_dataout : STD_LOGIC; + SIGNAL wire_nii001lO_dataout : STD_LOGIC; + SIGNAL wire_nii001Oi_dataout : STD_LOGIC; + SIGNAL wire_nii001Ol_dataout : STD_LOGIC; + SIGNAL wire_nii001OO_dataout : STD_LOGIC; + SIGNAL wire_nii00i0i_dataout : STD_LOGIC; + SIGNAL wire_nii00i0l_dataout : STD_LOGIC; + SIGNAL wire_nii00i0O_dataout : STD_LOGIC; + SIGNAL wire_nii00i1i_dataout : STD_LOGIC; + SIGNAL wire_nii00i1l_dataout : STD_LOGIC; + SIGNAL wire_nii00i1O_dataout : STD_LOGIC; + SIGNAL wire_nii00iii_dataout : STD_LOGIC; + SIGNAL wire_nii00iil_dataout : STD_LOGIC; + SIGNAL wire_nii00iiO_dataout : STD_LOGIC; + SIGNAL wire_nii00ili_dataout : STD_LOGIC; + SIGNAL wire_nii00ill_dataout : STD_LOGIC; + SIGNAL wire_nii00ilO_dataout : STD_LOGIC; + SIGNAL wire_nii00iOi_dataout : STD_LOGIC; + SIGNAL wire_nii00iOl_dataout : STD_LOGIC; + SIGNAL wire_nii00iOO_dataout : STD_LOGIC; + SIGNAL wire_nii00l0i_dataout : STD_LOGIC; + SIGNAL wire_nii00l0l_dataout : STD_LOGIC; + SIGNAL wire_nii00l0O_dataout : STD_LOGIC; + SIGNAL wire_nii00l1i_dataout : STD_LOGIC; + SIGNAL wire_nii00l1l_dataout : STD_LOGIC; + SIGNAL wire_nii00l1O_dataout : STD_LOGIC; + SIGNAL wire_nii00lii_dataout : STD_LOGIC; + SIGNAL wire_nii00lil_dataout : STD_LOGIC; + SIGNAL wire_nii00liO_dataout : STD_LOGIC; + SIGNAL wire_nii00lli_dataout : STD_LOGIC; + SIGNAL wire_nii00lll_dataout : STD_LOGIC; + SIGNAL wire_nii00llO_dataout : STD_LOGIC; + SIGNAL wire_nii00lOi_dataout : STD_LOGIC; + SIGNAL wire_nii00lOl_dataout : STD_LOGIC; + SIGNAL wire_nii00lOO_dataout : STD_LOGIC; + SIGNAL wire_nii00O0i_dataout : STD_LOGIC; + SIGNAL wire_nii00O0l_dataout : STD_LOGIC; + SIGNAL wire_nii00O0O_dataout : STD_LOGIC; + SIGNAL wire_nii00O1i_dataout : STD_LOGIC; + SIGNAL wire_nii00O1l_dataout : STD_LOGIC; + SIGNAL wire_nii00O1O_dataout : STD_LOGIC; + SIGNAL wire_nii00Oii_dataout : STD_LOGIC; + SIGNAL wire_nii00Oil_dataout : STD_LOGIC; + SIGNAL wire_nii00OiO_dataout : STD_LOGIC; + SIGNAL wire_nii00Oli_dataout : STD_LOGIC; + SIGNAL wire_nii00Oll_dataout : STD_LOGIC; + SIGNAL wire_nii00OlO_dataout : STD_LOGIC; + SIGNAL wire_nii00OOi_dataout : STD_LOGIC; + SIGNAL wire_nii00OOl_dataout : STD_LOGIC; + SIGNAL wire_nii00OOO_dataout : STD_LOGIC; + SIGNAL wire_nii0100i_dataout : STD_LOGIC; + SIGNAL wire_nii0100l_dataout : STD_LOGIC; + SIGNAL wire_nii0100O_dataout : STD_LOGIC; + SIGNAL wire_nii0101i_dataout : STD_LOGIC; + SIGNAL wire_nii0101l_dataout : STD_LOGIC; + SIGNAL wire_nii0101O_dataout : STD_LOGIC; + SIGNAL wire_nii010ii_dataout : STD_LOGIC; + SIGNAL wire_nii010il_dataout : STD_LOGIC; + SIGNAL wire_nii010iO_dataout : STD_LOGIC; + SIGNAL wire_nii010li_dataout : STD_LOGIC; + SIGNAL wire_nii010ll_dataout : STD_LOGIC; + SIGNAL wire_nii010lO_dataout : STD_LOGIC; + SIGNAL wire_nii010Oi_dataout : STD_LOGIC; + SIGNAL wire_nii010Ol_dataout : STD_LOGIC; + SIGNAL wire_nii010OO_dataout : STD_LOGIC; + SIGNAL wire_nii0110i_dataout : STD_LOGIC; + SIGNAL wire_nii0110l_dataout : STD_LOGIC; + SIGNAL wire_nii0110O_dataout : STD_LOGIC; + SIGNAL wire_nii0111i_dataout : STD_LOGIC; + SIGNAL wire_nii0111l_dataout : STD_LOGIC; + SIGNAL wire_nii0111O_dataout : STD_LOGIC; + SIGNAL wire_nii011ii_dataout : STD_LOGIC; + SIGNAL wire_nii011il_dataout : STD_LOGIC; + SIGNAL wire_nii011iO_dataout : STD_LOGIC; + SIGNAL wire_nii011li_dataout : STD_LOGIC; + SIGNAL wire_nii011ll_dataout : STD_LOGIC; + SIGNAL wire_nii011lO_dataout : STD_LOGIC; + SIGNAL wire_nii011Oi_dataout : STD_LOGIC; + SIGNAL wire_nii011Ol_dataout : STD_LOGIC; + SIGNAL wire_nii011OO_dataout : STD_LOGIC; + SIGNAL wire_nii01i0i_dataout : STD_LOGIC; + SIGNAL wire_nii01i0l_dataout : STD_LOGIC; + SIGNAL wire_nii01i0O_dataout : STD_LOGIC; + SIGNAL wire_nii01i1i_dataout : STD_LOGIC; + SIGNAL wire_nii01i1l_dataout : STD_LOGIC; + SIGNAL wire_nii01i1O_dataout : STD_LOGIC; + SIGNAL wire_nii01iii_dataout : STD_LOGIC; + SIGNAL wire_nii01iil_dataout : STD_LOGIC; + SIGNAL wire_nii01iiO_dataout : STD_LOGIC; + SIGNAL wire_nii01ili_dataout : STD_LOGIC; + SIGNAL wire_nii01ill_dataout : STD_LOGIC; + SIGNAL wire_nii01ilO_dataout : STD_LOGIC; + SIGNAL wire_nii01iOi_dataout : STD_LOGIC; + SIGNAL wire_nii01iOl_dataout : STD_LOGIC; + SIGNAL wire_nii01iOO_dataout : STD_LOGIC; + SIGNAL wire_nii01l0i_dataout : STD_LOGIC; + SIGNAL wire_nii01l0l_dataout : STD_LOGIC; + SIGNAL wire_nii01l0O_dataout : STD_LOGIC; + SIGNAL wire_nii01l1i_dataout : STD_LOGIC; + SIGNAL wire_nii01l1l_dataout : STD_LOGIC; + SIGNAL wire_nii01l1O_dataout : STD_LOGIC; + SIGNAL wire_nii01lii_dataout : STD_LOGIC; + SIGNAL wire_nii01lil_dataout : STD_LOGIC; + SIGNAL wire_nii01liO_dataout : STD_LOGIC; + SIGNAL wire_nii01lli_dataout : STD_LOGIC; + SIGNAL wire_nii01lll_dataout : STD_LOGIC; + SIGNAL wire_nii01llO_dataout : STD_LOGIC; + SIGNAL wire_nii01lOi_dataout : STD_LOGIC; + SIGNAL wire_nii01lOl_dataout : STD_LOGIC; + SIGNAL wire_nii01lOO_dataout : STD_LOGIC; + SIGNAL wire_nii01O0i_dataout : STD_LOGIC; + SIGNAL wire_nii01O0l_dataout : STD_LOGIC; + SIGNAL wire_nii01O0O_dataout : STD_LOGIC; + SIGNAL wire_nii01O1i_dataout : STD_LOGIC; + SIGNAL wire_nii01O1l_dataout : STD_LOGIC; + SIGNAL wire_nii01O1O_dataout : STD_LOGIC; + SIGNAL wire_nii01Oii_dataout : STD_LOGIC; + SIGNAL wire_nii01Oil_dataout : STD_LOGIC; + SIGNAL wire_nii01OiO_dataout : STD_LOGIC; + SIGNAL wire_nii01Oli_dataout : STD_LOGIC; + SIGNAL wire_nii01Oll_dataout : STD_LOGIC; + SIGNAL wire_nii01OlO_dataout : STD_LOGIC; + SIGNAL wire_nii01OOi_dataout : STD_LOGIC; + SIGNAL wire_nii01OOl_dataout : STD_LOGIC; + SIGNAL wire_nii01OOO_dataout : STD_LOGIC; + SIGNAL wire_nii0i00i_dataout : STD_LOGIC; + SIGNAL wire_nii0i00l_dataout : STD_LOGIC; + SIGNAL wire_nii0i00O_dataout : STD_LOGIC; + SIGNAL wire_nii0i01i_dataout : STD_LOGIC; + SIGNAL wire_nii0i01l_dataout : STD_LOGIC; + SIGNAL wire_nii0i01O_dataout : STD_LOGIC; + SIGNAL wire_nii0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nii0i0il_dataout : STD_LOGIC; + SIGNAL wire_nii0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nii0i0li_dataout : STD_LOGIC; + SIGNAL wire_nii0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nii0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nii0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nii0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nii0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nii0i10i_dataout : STD_LOGIC; + SIGNAL wire_nii0i10l_dataout : STD_LOGIC; + SIGNAL wire_nii0i10O_dataout : STD_LOGIC; + SIGNAL wire_nii0i11i_dataout : STD_LOGIC; + SIGNAL wire_nii0i11l_dataout : STD_LOGIC; + SIGNAL wire_nii0i11O_dataout : STD_LOGIC; + SIGNAL wire_nii0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nii0i1il_dataout : STD_LOGIC; + SIGNAL wire_nii0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nii0i1li_dataout : STD_LOGIC; + SIGNAL wire_nii0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nii0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nii0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nii0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nii0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nii0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nii0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nii0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nii0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nii0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nii0iiii_dataout : STD_LOGIC; + SIGNAL wire_nii0iiil_dataout : STD_LOGIC; + SIGNAL wire_nii0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nii0iili_dataout : STD_LOGIC; + SIGNAL wire_nii0iill_dataout : STD_LOGIC; + SIGNAL wire_nii0iilO_dataout : STD_LOGIC; + SIGNAL wire_nii0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nii0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nii0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nii0il0i_dataout : STD_LOGIC; + SIGNAL wire_nii0il0l_dataout : STD_LOGIC; + SIGNAL wire_nii0il0O_dataout : STD_LOGIC; + SIGNAL wire_nii0il1i_dataout : STD_LOGIC; + SIGNAL wire_nii0il1l_dataout : STD_LOGIC; + SIGNAL wire_nii0il1O_dataout : STD_LOGIC; + SIGNAL wire_nii0ilii_dataout : STD_LOGIC; + SIGNAL wire_nii0ilil_dataout : STD_LOGIC; + SIGNAL wire_nii0iliO_dataout : STD_LOGIC; + SIGNAL wire_nii0illi_dataout : STD_LOGIC; + SIGNAL wire_nii0illl_dataout : STD_LOGIC; + SIGNAL wire_nii0illO_dataout : STD_LOGIC; + SIGNAL wire_nii0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nii0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nii0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nii0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nii0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nii0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nii0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nii0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nii0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nii0iOii_dataout : STD_LOGIC; + SIGNAL wire_nii0iOil_dataout : STD_LOGIC; + SIGNAL wire_nii0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nii0iOli_dataout : STD_LOGIC; + SIGNAL wire_nii0iOll_dataout : STD_LOGIC; + SIGNAL wire_nii0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nii0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nii0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nii0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nii0l00i_dataout : STD_LOGIC; + SIGNAL wire_nii0l00l_dataout : STD_LOGIC; + SIGNAL wire_nii0l00O_dataout : STD_LOGIC; + SIGNAL wire_nii0l01i_dataout : STD_LOGIC; + SIGNAL wire_nii0l01l_dataout : STD_LOGIC; + SIGNAL wire_nii0l01O_dataout : STD_LOGIC; + SIGNAL wire_nii0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nii0l0il_dataout : STD_LOGIC; + SIGNAL wire_nii0l10i_dataout : STD_LOGIC; + SIGNAL wire_nii0l10l_dataout : STD_LOGIC; + SIGNAL wire_nii0l10O_dataout : STD_LOGIC; + SIGNAL wire_nii0l11i_dataout : STD_LOGIC; + SIGNAL wire_nii0l11l_dataout : STD_LOGIC; + SIGNAL wire_nii0l11O_dataout : STD_LOGIC; + SIGNAL wire_nii0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nii0l1il_dataout : STD_LOGIC; + SIGNAL wire_nii0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nii0l1li_dataout : STD_LOGIC; + SIGNAL wire_nii0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nii0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nii0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nii0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nii0li0i_dataout : STD_LOGIC; + SIGNAL wire_nii0li0l_dataout : STD_LOGIC; + SIGNAL wire_nii0li1O_dataout : STD_LOGIC; + SIGNAL wire_nii0lili_dataout : STD_LOGIC; + SIGNAL wire_nii0lill_dataout : STD_LOGIC; + SIGNAL wire_nii0lilO_dataout : STD_LOGIC; + SIGNAL wire_nii0liOi_dataout : STD_LOGIC; + SIGNAL wire_nii0liOl_dataout : STD_LOGIC; + SIGNAL wire_nii0liOO_dataout : STD_LOGIC; + SIGNAL wire_nii0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nii0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nii0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nii0llOi_dataout : STD_LOGIC; + SIGNAL wire_nii0llOl_dataout : STD_LOGIC; + SIGNAL wire_nii0llOO_dataout : STD_LOGIC; + SIGNAL wire_nii0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nii0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nii0lOii_dataout : STD_LOGIC; + SIGNAL wire_nii0lOil_dataout : STD_LOGIC; + SIGNAL wire_nii0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nii0lOli_dataout : STD_LOGIC; + SIGNAL wire_nii0lOll_dataout : STD_LOGIC; + SIGNAL wire_nii0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nii0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nii0O00i_dataout : STD_LOGIC; + SIGNAL wire_nii0O00l_dataout : STD_LOGIC; + SIGNAL wire_nii0O00O_dataout : STD_LOGIC; + SIGNAL wire_nii0O01i_dataout : STD_LOGIC; + SIGNAL wire_nii0O01l_dataout : STD_LOGIC; + SIGNAL wire_nii0O01O_dataout : STD_LOGIC; + SIGNAL wire_nii0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nii0O0il_dataout : STD_LOGIC; + SIGNAL wire_nii0O1il_dataout : STD_LOGIC; + SIGNAL wire_nii0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nii0O1li_dataout : STD_LOGIC; + SIGNAL wire_nii0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nii0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nii0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nii0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nii0Oili_dataout : STD_LOGIC; + SIGNAL wire_nii0Oill_dataout : STD_LOGIC; + SIGNAL wire_nii0OilO_dataout : STD_LOGIC; + SIGNAL wire_nii0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nii0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nii0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nii0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nii0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nii0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nii0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nii0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nii0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nii0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nii0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nii0OOii_dataout : STD_LOGIC; + SIGNAL wire_nii0OOil_dataout : STD_LOGIC; + SIGNAL wire_nii0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nii0OOli_dataout : STD_LOGIC; + SIGNAL wire_nii0OOll_dataout : STD_LOGIC; + SIGNAL wire_nii0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nii0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nii1000i_dataout : STD_LOGIC; + SIGNAL wire_nii1000l_dataout : STD_LOGIC; + SIGNAL wire_nii1000O_dataout : STD_LOGIC; + SIGNAL wire_nii1001i_dataout : STD_LOGIC; + SIGNAL wire_nii1001l_dataout : STD_LOGIC; + SIGNAL wire_nii1001O_dataout : STD_LOGIC; + SIGNAL wire_nii100i_dataout : STD_LOGIC; + SIGNAL wire_nii100ii_dataout : STD_LOGIC; + SIGNAL wire_nii100il_dataout : STD_LOGIC; + SIGNAL wire_nii100iO_dataout : STD_LOGIC; + SIGNAL wire_nii100l_dataout : STD_LOGIC; + SIGNAL wire_nii100li_dataout : STD_LOGIC; + SIGNAL wire_nii100ll_dataout : STD_LOGIC; + SIGNAL wire_nii100lO_dataout : STD_LOGIC; + SIGNAL wire_nii100O_dataout : STD_LOGIC; + SIGNAL wire_nii100Oi_dataout : STD_LOGIC; + SIGNAL wire_nii100Ol_dataout : STD_LOGIC; + SIGNAL wire_nii100OO_dataout : STD_LOGIC; + SIGNAL wire_nii1010i_dataout : STD_LOGIC; + SIGNAL wire_nii1010l_dataout : STD_LOGIC; + SIGNAL wire_nii1010O_dataout : STD_LOGIC; + SIGNAL wire_nii1011i_dataout : STD_LOGIC; + SIGNAL wire_nii1011l_dataout : STD_LOGIC; + SIGNAL wire_nii1011O_dataout : STD_LOGIC; + SIGNAL wire_nii101i_dataout : STD_LOGIC; + SIGNAL wire_nii101ii_dataout : STD_LOGIC; + SIGNAL wire_nii101il_dataout : STD_LOGIC; + SIGNAL wire_nii101iO_dataout : STD_LOGIC; + SIGNAL wire_nii101l_dataout : STD_LOGIC; + SIGNAL wire_nii101li_dataout : STD_LOGIC; + SIGNAL wire_nii101ll_dataout : STD_LOGIC; + SIGNAL wire_nii101lO_dataout : STD_LOGIC; + SIGNAL wire_nii101O_dataout : STD_LOGIC; + SIGNAL wire_nii101Oi_dataout : STD_LOGIC; + SIGNAL wire_nii101Ol_dataout : STD_LOGIC; + SIGNAL wire_nii101OO_dataout : STD_LOGIC; + SIGNAL wire_nii10i0i_dataout : STD_LOGIC; + SIGNAL wire_nii10i0l_dataout : STD_LOGIC; + SIGNAL wire_nii10i0O_dataout : STD_LOGIC; + SIGNAL wire_nii10i1i_dataout : STD_LOGIC; + SIGNAL wire_nii10i1l_dataout : STD_LOGIC; + SIGNAL wire_nii10i1O_dataout : STD_LOGIC; + SIGNAL wire_nii10ii_dataout : STD_LOGIC; + SIGNAL wire_nii10iii_dataout : STD_LOGIC; + SIGNAL wire_nii10iil_dataout : STD_LOGIC; + SIGNAL wire_nii10iiO_dataout : STD_LOGIC; + SIGNAL wire_nii10il_dataout : STD_LOGIC; + SIGNAL wire_nii10ili_dataout : STD_LOGIC; + SIGNAL wire_nii10ill_dataout : STD_LOGIC; + SIGNAL wire_nii10ilO_dataout : STD_LOGIC; + SIGNAL wire_nii10iO_dataout : STD_LOGIC; + SIGNAL wire_nii10iOi_dataout : STD_LOGIC; + SIGNAL wire_nii10iOl_dataout : STD_LOGIC; + SIGNAL wire_nii10iOO_dataout : STD_LOGIC; + SIGNAL wire_nii10l0i_dataout : STD_LOGIC; + SIGNAL wire_nii10l0l_dataout : STD_LOGIC; + SIGNAL wire_nii10l0O_dataout : STD_LOGIC; + SIGNAL wire_nii10l1i_dataout : STD_LOGIC; + SIGNAL wire_nii10l1l_dataout : STD_LOGIC; + SIGNAL wire_nii10l1O_dataout : STD_LOGIC; + SIGNAL wire_nii10li_dataout : STD_LOGIC; + SIGNAL wire_nii10lii_dataout : STD_LOGIC; + SIGNAL wire_nii10lil_dataout : STD_LOGIC; + SIGNAL wire_nii10liO_dataout : STD_LOGIC; + SIGNAL wire_nii10ll_dataout : STD_LOGIC; + SIGNAL wire_nii10lli_dataout : STD_LOGIC; + SIGNAL wire_nii10lll_dataout : STD_LOGIC; + SIGNAL wire_nii10llO_dataout : STD_LOGIC; + SIGNAL wire_nii10lO_dataout : STD_LOGIC; + SIGNAL wire_nii10lOi_dataout : STD_LOGIC; + SIGNAL wire_nii10lOl_dataout : STD_LOGIC; + SIGNAL wire_nii10lOO_dataout : STD_LOGIC; + SIGNAL wire_nii10O0i_dataout : STD_LOGIC; + SIGNAL wire_nii10O0l_dataout : STD_LOGIC; + SIGNAL wire_nii10O0O_dataout : STD_LOGIC; + SIGNAL wire_nii10O1i_dataout : STD_LOGIC; + SIGNAL wire_nii10O1l_dataout : STD_LOGIC; + SIGNAL wire_nii10O1O_dataout : STD_LOGIC; + SIGNAL wire_nii10Oi_dataout : STD_LOGIC; + SIGNAL wire_nii10Oii_dataout : STD_LOGIC; + SIGNAL wire_nii10Oil_dataout : STD_LOGIC; + SIGNAL wire_nii10OiO_dataout : STD_LOGIC; + SIGNAL wire_nii10Ol_dataout : STD_LOGIC; + SIGNAL wire_nii10Oli_dataout : STD_LOGIC; + SIGNAL wire_nii10Oll_dataout : STD_LOGIC; + SIGNAL wire_nii10OlO_dataout : STD_LOGIC; + SIGNAL wire_nii10OO_dataout : STD_LOGIC; + SIGNAL wire_nii10OOi_dataout : STD_LOGIC; + SIGNAL wire_nii10OOl_dataout : STD_LOGIC; + SIGNAL wire_nii10OOO_dataout : STD_LOGIC; + SIGNAL wire_nii1100i_dataout : STD_LOGIC; + SIGNAL wire_nii1100l_dataout : STD_LOGIC; + SIGNAL wire_nii1100O_dataout : STD_LOGIC; + SIGNAL wire_nii1101i_dataout : STD_LOGIC; + SIGNAL wire_nii1101l_dataout : STD_LOGIC; + SIGNAL wire_nii1101O_dataout : STD_LOGIC; + SIGNAL wire_nii110i_dataout : STD_LOGIC; + SIGNAL wire_nii110ii_dataout : STD_LOGIC; + SIGNAL wire_nii110il_dataout : STD_LOGIC; + SIGNAL wire_nii110iO_dataout : STD_LOGIC; + SIGNAL wire_nii110l_dataout : STD_LOGIC; + SIGNAL wire_nii110li_dataout : STD_LOGIC; + SIGNAL wire_nii110ll_dataout : STD_LOGIC; + SIGNAL wire_nii110lO_dataout : STD_LOGIC; + SIGNAL wire_nii110O_dataout : STD_LOGIC; + SIGNAL wire_nii110Oi_dataout : STD_LOGIC; + SIGNAL wire_nii110Ol_dataout : STD_LOGIC; + SIGNAL wire_nii110OO_dataout : STD_LOGIC; + SIGNAL wire_nii1110i_dataout : STD_LOGIC; + SIGNAL wire_nii1110l_dataout : STD_LOGIC; + SIGNAL wire_nii1110O_dataout : STD_LOGIC; + SIGNAL wire_nii1111i_dataout : STD_LOGIC; + SIGNAL wire_nii1111l_dataout : STD_LOGIC; + SIGNAL wire_nii1111O_dataout : STD_LOGIC; + SIGNAL wire_nii111i_dataout : STD_LOGIC; + SIGNAL wire_nii111ii_dataout : STD_LOGIC; + SIGNAL wire_nii111il_dataout : STD_LOGIC; + SIGNAL wire_nii111iO_dataout : STD_LOGIC; + SIGNAL wire_nii111l_dataout : STD_LOGIC; + SIGNAL wire_nii111li_dataout : STD_LOGIC; + SIGNAL wire_nii111ll_dataout : STD_LOGIC; + SIGNAL wire_nii111lO_dataout : STD_LOGIC; + SIGNAL wire_nii111O_dataout : STD_LOGIC; + SIGNAL wire_nii111Oi_dataout : STD_LOGIC; + SIGNAL wire_nii111Ol_dataout : STD_LOGIC; + SIGNAL wire_nii111OO_dataout : STD_LOGIC; + SIGNAL wire_nii11i0i_dataout : STD_LOGIC; + SIGNAL wire_nii11i0l_dataout : STD_LOGIC; + SIGNAL wire_nii11i0O_dataout : STD_LOGIC; + SIGNAL wire_nii11i1i_dataout : STD_LOGIC; + SIGNAL wire_nii11i1l_dataout : STD_LOGIC; + SIGNAL wire_nii11i1O_dataout : STD_LOGIC; + SIGNAL wire_nii11ii_dataout : STD_LOGIC; + SIGNAL wire_nii11iii_dataout : STD_LOGIC; + SIGNAL wire_nii11iil_dataout : STD_LOGIC; + SIGNAL wire_nii11iiO_dataout : STD_LOGIC; + SIGNAL wire_nii11il_dataout : STD_LOGIC; + SIGNAL wire_nii11ili_dataout : STD_LOGIC; + SIGNAL wire_nii11ill_dataout : STD_LOGIC; + SIGNAL wire_nii11ilO_dataout : STD_LOGIC; + SIGNAL wire_nii11iO_dataout : STD_LOGIC; + SIGNAL wire_nii11iOi_dataout : STD_LOGIC; + SIGNAL wire_nii11iOl_dataout : STD_LOGIC; + SIGNAL wire_nii11iOO_dataout : STD_LOGIC; + SIGNAL wire_nii11l0i_dataout : STD_LOGIC; + SIGNAL wire_nii11l0l_dataout : STD_LOGIC; + SIGNAL wire_nii11l0O_dataout : STD_LOGIC; + SIGNAL wire_nii11l1i_dataout : STD_LOGIC; + SIGNAL wire_nii11l1l_dataout : STD_LOGIC; + SIGNAL wire_nii11l1O_dataout : STD_LOGIC; + SIGNAL wire_nii11li_dataout : STD_LOGIC; + SIGNAL wire_nii11lii_dataout : STD_LOGIC; + SIGNAL wire_nii11lil_dataout : STD_LOGIC; + SIGNAL wire_nii11liO_dataout : STD_LOGIC; + SIGNAL wire_nii11ll_dataout : STD_LOGIC; + SIGNAL wire_nii11lli_dataout : STD_LOGIC; + SIGNAL wire_nii11lll_dataout : STD_LOGIC; + SIGNAL wire_nii11llO_dataout : STD_LOGIC; + SIGNAL wire_nii11lO_dataout : STD_LOGIC; + SIGNAL wire_nii11lOi_dataout : STD_LOGIC; + SIGNAL wire_nii11lOl_dataout : STD_LOGIC; + SIGNAL wire_nii11lOO_dataout : STD_LOGIC; + SIGNAL wire_nii11O0i_dataout : STD_LOGIC; + SIGNAL wire_nii11O0l_dataout : STD_LOGIC; + SIGNAL wire_nii11O0O_dataout : STD_LOGIC; + SIGNAL wire_nii11O1i_dataout : STD_LOGIC; + SIGNAL wire_nii11O1l_dataout : STD_LOGIC; + SIGNAL wire_nii11O1O_dataout : STD_LOGIC; + SIGNAL wire_nii11Oi_dataout : STD_LOGIC; + SIGNAL wire_nii11Oii_dataout : STD_LOGIC; + SIGNAL wire_nii11Oil_dataout : STD_LOGIC; + SIGNAL wire_nii11OiO_dataout : STD_LOGIC; + SIGNAL wire_nii11Ol_dataout : STD_LOGIC; + SIGNAL wire_nii11Oli_dataout : STD_LOGIC; + SIGNAL wire_nii11Oll_dataout : STD_LOGIC; + SIGNAL wire_nii11OlO_dataout : STD_LOGIC; + SIGNAL wire_nii11OO_dataout : STD_LOGIC; + SIGNAL wire_nii11OOi_dataout : STD_LOGIC; + SIGNAL wire_nii11OOl_dataout : STD_LOGIC; + SIGNAL wire_nii11OOO_dataout : STD_LOGIC; + SIGNAL wire_nii1i00i_dataout : STD_LOGIC; + SIGNAL wire_nii1i00l_dataout : STD_LOGIC; + SIGNAL wire_nii1i00O_dataout : STD_LOGIC; + SIGNAL wire_nii1i01i_dataout : STD_LOGIC; + SIGNAL wire_nii1i01l_dataout : STD_LOGIC; + SIGNAL wire_nii1i01O_dataout : STD_LOGIC; + SIGNAL wire_nii1i0i_dataout : STD_LOGIC; + SIGNAL wire_nii1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nii1i0il_dataout : STD_LOGIC; + SIGNAL wire_nii1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nii1i0l_dataout : STD_LOGIC; + SIGNAL wire_nii1i0li_dataout : STD_LOGIC; + SIGNAL wire_nii1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nii1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nii1i0O_dataout : STD_LOGIC; + SIGNAL wire_nii1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nii1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nii1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nii1i10i_dataout : STD_LOGIC; + SIGNAL wire_nii1i10l_dataout : STD_LOGIC; + SIGNAL wire_nii1i10O_dataout : STD_LOGIC; + SIGNAL wire_nii1i11i_dataout : STD_LOGIC; + SIGNAL wire_nii1i11l_dataout : STD_LOGIC; + SIGNAL wire_nii1i11O_dataout : STD_LOGIC; + SIGNAL wire_nii1i1i_dataout : STD_LOGIC; + SIGNAL wire_nii1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nii1i1il_dataout : STD_LOGIC; + SIGNAL wire_nii1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nii1i1l_dataout : STD_LOGIC; + SIGNAL wire_nii1i1li_dataout : STD_LOGIC; + SIGNAL wire_nii1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nii1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nii1i1O_dataout : STD_LOGIC; + SIGNAL wire_nii1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nii1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nii1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nii1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nii1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nii1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nii1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nii1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nii1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nii1iii_dataout : STD_LOGIC; + SIGNAL wire_nii1iiii_dataout : STD_LOGIC; + SIGNAL wire_nii1iiil_dataout : STD_LOGIC; + SIGNAL wire_nii1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nii1iil_dataout : STD_LOGIC; + SIGNAL wire_nii1iili_dataout : STD_LOGIC; + SIGNAL wire_nii1iill_dataout : STD_LOGIC; + SIGNAL wire_nii1iilO_dataout : STD_LOGIC; + SIGNAL wire_nii1iiO_dataout : STD_LOGIC; + SIGNAL wire_nii1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nii1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nii1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nii1il0i_dataout : STD_LOGIC; + SIGNAL wire_nii1il0l_dataout : STD_LOGIC; + SIGNAL wire_nii1il0O_dataout : STD_LOGIC; + SIGNAL wire_nii1il1i_dataout : STD_LOGIC; + SIGNAL wire_nii1il1l_dataout : STD_LOGIC; + SIGNAL wire_nii1il1O_dataout : STD_LOGIC; + SIGNAL wire_nii1ili_dataout : STD_LOGIC; + SIGNAL wire_nii1ilii_dataout : STD_LOGIC; + SIGNAL wire_nii1ilil_dataout : STD_LOGIC; + SIGNAL wire_nii1iliO_dataout : STD_LOGIC; + SIGNAL wire_nii1ill_dataout : STD_LOGIC; + SIGNAL wire_nii1illi_dataout : STD_LOGIC; + SIGNAL wire_nii1illl_dataout : STD_LOGIC; + SIGNAL wire_nii1illO_dataout : STD_LOGIC; + SIGNAL wire_nii1ilO_dataout : STD_LOGIC; + SIGNAL wire_nii1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nii1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nii1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nii1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nii1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nii1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nii1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nii1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nii1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nii1iOi_dataout : STD_LOGIC; + SIGNAL wire_nii1iOii_dataout : STD_LOGIC; + SIGNAL wire_nii1iOil_dataout : STD_LOGIC; + SIGNAL wire_nii1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nii1iOl_dataout : STD_LOGIC; + SIGNAL wire_nii1iOli_dataout : STD_LOGIC; + SIGNAL wire_nii1iOll_dataout : STD_LOGIC; + SIGNAL wire_nii1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nii1iOO_dataout : STD_LOGIC; + SIGNAL wire_nii1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nii1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nii1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nii1l00i_dataout : STD_LOGIC; + SIGNAL wire_nii1l01i_dataout : STD_LOGIC; + SIGNAL wire_nii1l01l_dataout : STD_LOGIC; + SIGNAL wire_nii1l01O_dataout : STD_LOGIC; + SIGNAL wire_nii1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nii1l0il_dataout : STD_LOGIC; + SIGNAL wire_nii1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nii1l0li_dataout : STD_LOGIC; + SIGNAL wire_nii1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nii1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nii1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nii1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nii1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nii1l10i_dataout : STD_LOGIC; + SIGNAL wire_nii1l10l_dataout : STD_LOGIC; + SIGNAL wire_nii1l10O_dataout : STD_LOGIC; + SIGNAL wire_nii1l11i_dataout : STD_LOGIC; + SIGNAL wire_nii1l11l_dataout : STD_LOGIC; + SIGNAL wire_nii1l11O_dataout : STD_LOGIC; + SIGNAL wire_nii1l1i_dataout : STD_LOGIC; + SIGNAL wire_nii1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nii1l1il_dataout : STD_LOGIC; + SIGNAL wire_nii1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nii1l1li_dataout : STD_LOGIC; + SIGNAL wire_nii1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nii1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nii1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nii1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nii1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nii1li0i_dataout : STD_LOGIC; + SIGNAL wire_nii1li0l_dataout : STD_LOGIC; + SIGNAL wire_nii1li0O_dataout : STD_LOGIC; + SIGNAL wire_nii1li1i_dataout : STD_LOGIC; + SIGNAL wire_nii1li1l_dataout : STD_LOGIC; + SIGNAL wire_nii1li1O_dataout : STD_LOGIC; + SIGNAL wire_nii1liii_dataout : STD_LOGIC; + SIGNAL wire_nii1liil_dataout : STD_LOGIC; + SIGNAL wire_nii1liiO_dataout : STD_LOGIC; + SIGNAL wire_nii1lili_dataout : STD_LOGIC; + SIGNAL wire_nii1lill_dataout : STD_LOGIC; + SIGNAL wire_nii1lilO_dataout : STD_LOGIC; + SIGNAL wire_nii1liOi_dataout : STD_LOGIC; + SIGNAL wire_nii1liOl_dataout : STD_LOGIC; + SIGNAL wire_nii1liOO_dataout : STD_LOGIC; + SIGNAL wire_nii1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nii1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nii1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nii1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nii1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nii1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nii1llii_dataout : STD_LOGIC; + SIGNAL wire_nii1llil_dataout : STD_LOGIC; + SIGNAL wire_nii1lliO_dataout : STD_LOGIC; + SIGNAL wire_nii1llli_dataout : STD_LOGIC; + SIGNAL wire_nii1llll_dataout : STD_LOGIC; + SIGNAL wire_nii1lllO_dataout : STD_LOGIC; + SIGNAL wire_nii1llOi_dataout : STD_LOGIC; + SIGNAL wire_nii1llOl_dataout : STD_LOGIC; + SIGNAL wire_nii1llOO_dataout : STD_LOGIC; + SIGNAL wire_nii1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nii1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nii1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nii1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nii1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nii1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nii1lOii_dataout : STD_LOGIC; + SIGNAL wire_nii1lOil_dataout : STD_LOGIC; + SIGNAL wire_nii1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nii1lOli_dataout : STD_LOGIC; + SIGNAL wire_nii1lOll_dataout : STD_LOGIC; + SIGNAL wire_nii1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nii1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nii1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nii1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nii1O00i_dataout : STD_LOGIC; + SIGNAL wire_nii1O00l_dataout : STD_LOGIC; + SIGNAL wire_nii1O00O_dataout : STD_LOGIC; + SIGNAL wire_nii1O01i_dataout : STD_LOGIC; + SIGNAL wire_nii1O01l_dataout : STD_LOGIC; + SIGNAL wire_nii1O01O_dataout : STD_LOGIC; + SIGNAL wire_nii1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nii1O0il_dataout : STD_LOGIC; + SIGNAL wire_nii1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nii1O0li_dataout : STD_LOGIC; + SIGNAL wire_nii1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nii1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nii1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nii1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nii1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nii1O10i_dataout : STD_LOGIC; + SIGNAL wire_nii1O10l_dataout : STD_LOGIC; + SIGNAL wire_nii1O10O_dataout : STD_LOGIC; + SIGNAL wire_nii1O11i_dataout : STD_LOGIC; + SIGNAL wire_nii1O11l_dataout : STD_LOGIC; + SIGNAL wire_nii1O11O_dataout : STD_LOGIC; + SIGNAL wire_nii1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nii1O1il_dataout : STD_LOGIC; + SIGNAL wire_nii1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nii1O1li_dataout : STD_LOGIC; + SIGNAL wire_nii1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nii1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nii1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nii1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nii1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nii1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nii1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nii1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nii1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nii1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nii1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nii1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nii1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nii1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nii1Oili_dataout : STD_LOGIC; + SIGNAL wire_nii1Oill_dataout : STD_LOGIC; + SIGNAL wire_nii1OilO_dataout : STD_LOGIC; + SIGNAL wire_nii1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nii1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nii1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nii1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nii1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nii1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nii1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nii1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nii1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nii1Olii_dataout : STD_LOGIC; + SIGNAL wire_nii1Olil_dataout : STD_LOGIC; + SIGNAL wire_nii1OliO_dataout : STD_LOGIC; + SIGNAL wire_nii1Olli_dataout : STD_LOGIC; + SIGNAL wire_nii1Olll_dataout : STD_LOGIC; + SIGNAL wire_nii1OllO_dataout : STD_LOGIC; + SIGNAL wire_nii1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nii1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nii1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nii1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nii1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nii1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nii1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nii1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nii1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nii1OOii_dataout : STD_LOGIC; + SIGNAL wire_nii1OOil_dataout : STD_LOGIC; + SIGNAL wire_nii1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nii1OOli_dataout : STD_LOGIC; + SIGNAL wire_nii1OOll_dataout : STD_LOGIC; + SIGNAL wire_nii1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nii1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nii1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nii1OOOO_dataout : STD_LOGIC; + SIGNAL wire_niii000i_dataout : STD_LOGIC; + SIGNAL wire_niii000l_dataout : STD_LOGIC; + SIGNAL wire_niii001i_dataout : STD_LOGIC; + SIGNAL wire_niii001O_dataout : STD_LOGIC; + SIGNAL wire_niii00ii_dataout : STD_LOGIC; + SIGNAL wire_niii00il_dataout : STD_LOGIC; + SIGNAL wire_niii00iO_dataout : STD_LOGIC; + SIGNAL wire_niii00ll_dataout : STD_LOGIC; + SIGNAL wire_niii00lO_dataout : STD_LOGIC; + SIGNAL wire_niii00Oi_dataout : STD_LOGIC; + SIGNAL wire_niii010i_dataout : STD_LOGIC; + SIGNAL wire_niii010O_dataout : STD_LOGIC; + SIGNAL wire_niii011l_dataout : STD_LOGIC; + SIGNAL wire_niii011O_dataout : STD_LOGIC; + SIGNAL wire_niii01ii_dataout : STD_LOGIC; + SIGNAL wire_niii01il_dataout : STD_LOGIC; + SIGNAL wire_niii01li_dataout : STD_LOGIC; + SIGNAL wire_niii01ll_dataout : STD_LOGIC; + SIGNAL wire_niii01lO_dataout : STD_LOGIC; + SIGNAL wire_niii01Ol_dataout : STD_LOGIC; + SIGNAL wire_niii01OO_dataout : STD_LOGIC; + SIGNAL wire_niii0i0i_dataout : STD_LOGIC; + SIGNAL wire_niii0i0l_dataout : STD_LOGIC; + SIGNAL wire_niii0i0O_dataout : STD_LOGIC; + SIGNAL wire_niii0i1O_dataout : STD_LOGIC; + SIGNAL wire_niii0iii_dataout : STD_LOGIC; + SIGNAL wire_niii0iil_dataout : STD_LOGIC; + SIGNAL wire_niii0l0l_dataout : STD_LOGIC; + SIGNAL wire_niii0l0O_dataout : STD_LOGIC; + SIGNAL wire_niii0lii_dataout : STD_LOGIC; + SIGNAL wire_niii0lil_dataout : STD_LOGIC; + SIGNAL wire_niii0liO_dataout : STD_LOGIC; + SIGNAL wire_niii0lli_dataout : STD_LOGIC; + SIGNAL wire_niii0lll_dataout : STD_LOGIC; + SIGNAL wire_niii0llO_dataout : STD_LOGIC; + SIGNAL wire_niii0lOi_dataout : STD_LOGIC; + SIGNAL wire_niii0lOl_dataout : STD_LOGIC; + SIGNAL wire_niii0lOO_dataout : STD_LOGIC; + SIGNAL wire_niii0O0i_dataout : STD_LOGIC; + SIGNAL wire_niii0O0l_dataout : STD_LOGIC; + SIGNAL wire_niii0O0O_dataout : STD_LOGIC; + SIGNAL wire_niii0O1i_dataout : STD_LOGIC; + SIGNAL wire_niii0O1l_dataout : STD_LOGIC; + SIGNAL wire_niii0O1O_dataout : STD_LOGIC; + SIGNAL wire_niii0Oii_dataout : STD_LOGIC; + SIGNAL wire_niii0Oil_dataout : STD_LOGIC; + SIGNAL wire_niii0OiO_dataout : STD_LOGIC; + SIGNAL wire_niii0Oli_dataout : STD_LOGIC; + SIGNAL wire_niii0Oll_dataout : STD_LOGIC; + SIGNAL wire_niii0OlO_dataout : STD_LOGIC; + SIGNAL wire_niii0OOi_dataout : STD_LOGIC; + SIGNAL wire_niii100i_dataout : STD_LOGIC; + SIGNAL wire_niii100l_dataout : STD_LOGIC; + SIGNAL wire_niii100O_dataout : STD_LOGIC; + SIGNAL wire_niii101i_dataout : STD_LOGIC; + SIGNAL wire_niii101l_dataout : STD_LOGIC; + SIGNAL wire_niii101O_dataout : STD_LOGIC; + SIGNAL wire_niii10ii_dataout : STD_LOGIC; + SIGNAL wire_niii10il_dataout : STD_LOGIC; + SIGNAL wire_niii11il_dataout : STD_LOGIC; + SIGNAL wire_niii11iO_dataout : STD_LOGIC; + SIGNAL wire_niii11li_dataout : STD_LOGIC; + SIGNAL wire_niii11OO_dataout : STD_LOGIC; + SIGNAL wire_niii1i0i_dataout : STD_LOGIC; + SIGNAL wire_niii1i0l_dataout : STD_LOGIC; + SIGNAL wire_niii1i1O_dataout : STD_LOGIC; + SIGNAL wire_niii1ili_dataout : STD_LOGIC; + SIGNAL wire_niii1ill_dataout : STD_LOGIC; + SIGNAL wire_niii1ilO_dataout : STD_LOGIC; + SIGNAL wire_niii1iOi_dataout : STD_LOGIC; + SIGNAL wire_niii1iOl_dataout : STD_LOGIC; + SIGNAL wire_niii1iOO_dataout : STD_LOGIC; + SIGNAL wire_niii1l1i_dataout : STD_LOGIC; + SIGNAL wire_niii1l1l_dataout : STD_LOGIC; + SIGNAL wire_niii1l1O_dataout : STD_LOGIC; + SIGNAL wire_niii1lOi_dataout : STD_LOGIC; + SIGNAL wire_niii1lOl_dataout : STD_LOGIC; + SIGNAL wire_niii1lOO_dataout : STD_LOGIC; + SIGNAL wire_niii1OOi_dataout : STD_LOGIC; + SIGNAL wire_niii1OOl_dataout : STD_LOGIC; + SIGNAL wire_niii1OOO_dataout : STD_LOGIC; + SIGNAL wire_niiil00i_dataout : STD_LOGIC; + SIGNAL wire_niiil00l_dataout : STD_LOGIC; + SIGNAL wire_niiil00O_dataout : STD_LOGIC; + SIGNAL wire_niiil01i_dataout : STD_LOGIC; + SIGNAL wire_niiil01l_dataout : STD_LOGIC; + SIGNAL wire_niiil01O_dataout : STD_LOGIC; + SIGNAL wire_niiil0ii_dataout : STD_LOGIC; + SIGNAL wire_niiil0il_dataout : STD_LOGIC; + SIGNAL wire_niiil0iO_dataout : STD_LOGIC; + SIGNAL wire_niiil0li_dataout : STD_LOGIC; + SIGNAL wire_niiil0ll_dataout : STD_LOGIC; + SIGNAL wire_niiil0lO_dataout : STD_LOGIC; + SIGNAL wire_niiil0Oi_dataout : STD_LOGIC; + SIGNAL wire_niiil0Ol_dataout : STD_LOGIC; + SIGNAL wire_niiil0OO_dataout : STD_LOGIC; + SIGNAL wire_niiil10i_dataout : STD_LOGIC; + SIGNAL wire_niiil10l_dataout : STD_LOGIC; + SIGNAL wire_niiil10O_dataout : STD_LOGIC; + SIGNAL wire_niiil11O_dataout : STD_LOGIC; + SIGNAL wire_niiil1ii_dataout : STD_LOGIC; + SIGNAL wire_niiil1il_dataout : STD_LOGIC; + SIGNAL wire_niiil1iO_dataout : STD_LOGIC; + SIGNAL wire_niiil1li_dataout : STD_LOGIC; + SIGNAL wire_niiil1ll_dataout : STD_LOGIC; + SIGNAL wire_niiil1lO_dataout : STD_LOGIC; + SIGNAL wire_niiil1Oi_dataout : STD_LOGIC; + SIGNAL wire_niiil1Ol_dataout : STD_LOGIC; + SIGNAL wire_niiil1OO_dataout : STD_LOGIC; + SIGNAL wire_niiili0i_dataout : STD_LOGIC; + SIGNAL wire_niiili0l_dataout : STD_LOGIC; + SIGNAL wire_niiili0O_dataout : STD_LOGIC; + SIGNAL wire_niiili1i_dataout : STD_LOGIC; + SIGNAL wire_niiili1l_dataout : STD_LOGIC; + SIGNAL wire_niiili1O_dataout : STD_LOGIC; + SIGNAL wire_niiiliii_dataout : STD_LOGIC; + SIGNAL wire_niiiliil_dataout : STD_LOGIC; + SIGNAL wire_niiiliiO_dataout : STD_LOGIC; + SIGNAL wire_niiilili_dataout : STD_LOGIC; + SIGNAL wire_niiilill_dataout : STD_LOGIC; + SIGNAL wire_niiililO_dataout : STD_LOGIC; + SIGNAL wire_niiiliOi_dataout : STD_LOGIC; + SIGNAL wire_niiiliOl_dataout : STD_LOGIC; + SIGNAL wire_niiiliOO_dataout : STD_LOGIC; + SIGNAL wire_niiill0i_dataout : STD_LOGIC; + SIGNAL wire_niiill0l_dataout : STD_LOGIC; + SIGNAL wire_niiill0O_dataout : STD_LOGIC; + SIGNAL wire_niiill1i_dataout : STD_LOGIC; + SIGNAL wire_niiill1l_dataout : STD_LOGIC; + SIGNAL wire_niiill1O_dataout : STD_LOGIC; + SIGNAL wire_niiillii_dataout : STD_LOGIC; + SIGNAL wire_niiillil_dataout : STD_LOGIC; + SIGNAL wire_niiilliO_dataout : STD_LOGIC; + SIGNAL wire_niiillli_dataout : STD_LOGIC; + SIGNAL wire_niiillll_dataout : STD_LOGIC; + SIGNAL wire_niiilllO_dataout : STD_LOGIC; + SIGNAL wire_niiillOi_dataout : STD_LOGIC; + SIGNAL wire_niiillOl_dataout : STD_LOGIC; + SIGNAL wire_niiillOO_dataout : STD_LOGIC; + SIGNAL wire_niiilO0i_dataout : STD_LOGIC; + SIGNAL wire_niiilO0l_dataout : STD_LOGIC; + SIGNAL wire_niiilO0O_dataout : STD_LOGIC; + SIGNAL wire_niiilO1i_dataout : STD_LOGIC; + SIGNAL wire_niiilO1l_dataout : STD_LOGIC; + SIGNAL wire_niiilO1O_dataout : STD_LOGIC; + SIGNAL wire_niiilOii_dataout : STD_LOGIC; + SIGNAL wire_niiilOil_dataout : STD_LOGIC; + SIGNAL wire_niiilOiO_dataout : STD_LOGIC; + SIGNAL wire_niiilOli_dataout : STD_LOGIC; + SIGNAL wire_niiilOll_dataout : STD_LOGIC; + SIGNAL wire_niiilOlO_dataout : STD_LOGIC; + SIGNAL wire_niiilOOi_dataout : STD_LOGIC; + SIGNAL wire_niiilOOl_dataout : STD_LOGIC; + SIGNAL wire_niiilOOO_dataout : STD_LOGIC; + SIGNAL wire_niiiO00i_dataout : STD_LOGIC; + SIGNAL wire_niiiO00l_dataout : STD_LOGIC; + SIGNAL wire_niiiO00O_dataout : STD_LOGIC; + SIGNAL wire_niiiO01i_dataout : STD_LOGIC; + SIGNAL wire_niiiO01l_dataout : STD_LOGIC; + SIGNAL wire_niiiO01O_dataout : STD_LOGIC; + SIGNAL wire_niiiO0ii_dataout : STD_LOGIC; + SIGNAL wire_niiiO0il_dataout : STD_LOGIC; + SIGNAL wire_niiiO0iO_dataout : STD_LOGIC; + SIGNAL wire_niiiO0li_dataout : STD_LOGIC; + SIGNAL wire_niiiO0ll_dataout : STD_LOGIC; + SIGNAL wire_niiiO0lO_dataout : STD_LOGIC; + SIGNAL wire_niiiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niiiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niiiO0OO_dataout : STD_LOGIC; + SIGNAL wire_niiiO10i_dataout : STD_LOGIC; + SIGNAL wire_niiiO10l_dataout : STD_LOGIC; + SIGNAL wire_niiiO10O_dataout : STD_LOGIC; + SIGNAL wire_niiiO11i_dataout : STD_LOGIC; + SIGNAL wire_niiiO11l_dataout : STD_LOGIC; + SIGNAL wire_niiiO11O_dataout : STD_LOGIC; + SIGNAL wire_niiiO1ii_dataout : STD_LOGIC; + SIGNAL wire_niiiO1il_dataout : STD_LOGIC; + SIGNAL wire_niiiO1iO_dataout : STD_LOGIC; + SIGNAL wire_niiiO1li_dataout : STD_LOGIC; + SIGNAL wire_niiiO1ll_dataout : STD_LOGIC; + SIGNAL wire_niiiO1lO_dataout : STD_LOGIC; + SIGNAL wire_niiiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niiiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niiiO1OO_dataout : STD_LOGIC; + SIGNAL wire_niiiOi0i_dataout : STD_LOGIC; + SIGNAL wire_niiiOi0l_dataout : STD_LOGIC; + SIGNAL wire_niiiOi0O_dataout : STD_LOGIC; + SIGNAL wire_niiiOi1i_dataout : STD_LOGIC; + SIGNAL wire_niiiOi1l_dataout : STD_LOGIC; + SIGNAL wire_niiiOi1O_dataout : STD_LOGIC; + SIGNAL wire_niiiOiii_dataout : STD_LOGIC; + SIGNAL wire_niiiOiil_dataout : STD_LOGIC; + SIGNAL wire_niiiOiiO_dataout : STD_LOGIC; + SIGNAL wire_niiiOili_dataout : STD_LOGIC; + SIGNAL wire_niiiOill_dataout : STD_LOGIC; + SIGNAL wire_niiiOilO_dataout : STD_LOGIC; + SIGNAL wire_niiiOiOi_dataout : STD_LOGIC; + SIGNAL wire_niiiOiOl_dataout : STD_LOGIC; + SIGNAL wire_niiiOiOO_dataout : STD_LOGIC; + SIGNAL wire_niiiOl0i_dataout : STD_LOGIC; + SIGNAL wire_niiiOl0l_dataout : STD_LOGIC; + SIGNAL wire_niiiOl0O_dataout : STD_LOGIC; + SIGNAL wire_niiiOl1i_dataout : STD_LOGIC; + SIGNAL wire_niiiOl1l_dataout : STD_LOGIC; + SIGNAL wire_niiiOl1O_dataout : STD_LOGIC; + SIGNAL wire_niiiOlii_dataout : STD_LOGIC; + SIGNAL wire_niiiOlil_dataout : STD_LOGIC; + SIGNAL wire_niiiOliO_dataout : STD_LOGIC; + SIGNAL wire_niiiOlli_dataout : STD_LOGIC; + SIGNAL wire_niiiOlll_dataout : STD_LOGIC; + SIGNAL wire_niiiOllO_dataout : STD_LOGIC; + SIGNAL wire_niiiOlOi_dataout : STD_LOGIC; + SIGNAL wire_niiiOlOl_dataout : STD_LOGIC; + SIGNAL wire_niiiOlOO_dataout : STD_LOGIC; + SIGNAL wire_niiiOO0i_dataout : STD_LOGIC; + SIGNAL wire_niiiOO0l_dataout : STD_LOGIC; + SIGNAL wire_niiiOO0O_dataout : STD_LOGIC; + SIGNAL wire_niiiOO1i_dataout : STD_LOGIC; + SIGNAL wire_niiiOO1l_dataout : STD_LOGIC; + SIGNAL wire_niiiOO1O_dataout : STD_LOGIC; + SIGNAL wire_niiiOOii_dataout : STD_LOGIC; + SIGNAL wire_niiiOOil_dataout : STD_LOGIC; + SIGNAL wire_niiiOOiO_dataout : STD_LOGIC; + SIGNAL wire_niiiOOli_dataout : STD_LOGIC; + SIGNAL wire_niiiOOll_dataout : STD_LOGIC; + SIGNAL wire_niiiOOlO_dataout : STD_LOGIC; + SIGNAL wire_niiiOOOi_dataout : STD_LOGIC; + SIGNAL wire_niiiOOOl_dataout : STD_LOGIC; + SIGNAL wire_niiiOOOO_dataout : STD_LOGIC; + SIGNAL wire_niil000i_dataout : STD_LOGIC; + SIGNAL wire_niil000l_dataout : STD_LOGIC; + SIGNAL wire_niil000O_dataout : STD_LOGIC; + SIGNAL wire_niil001i_dataout : STD_LOGIC; + SIGNAL wire_niil001l_dataout : STD_LOGIC; + SIGNAL wire_niil001O_dataout : STD_LOGIC; + SIGNAL wire_niil00i_dataout : STD_LOGIC; + SIGNAL wire_niil00ii_dataout : STD_LOGIC; + SIGNAL wire_niil00il_dataout : STD_LOGIC; + SIGNAL wire_niil00iO_dataout : STD_LOGIC; + SIGNAL wire_niil00l_dataout : STD_LOGIC; + SIGNAL wire_niil00li_dataout : STD_LOGIC; + SIGNAL wire_niil00ll_dataout : STD_LOGIC; + SIGNAL wire_niil00lO_dataout : STD_LOGIC; + SIGNAL wire_niil00O_dataout : STD_LOGIC; + SIGNAL wire_niil00Oi_dataout : STD_LOGIC; + SIGNAL wire_niil01i_dataout : STD_LOGIC; + SIGNAL wire_niil01iO_dataout : STD_LOGIC; + SIGNAL wire_niil01l_dataout : STD_LOGIC; + SIGNAL wire_niil01li_dataout : STD_LOGIC; + SIGNAL wire_niil01ll_dataout : STD_LOGIC; + SIGNAL wire_niil01lO_dataout : STD_LOGIC; + SIGNAL wire_niil01O_dataout : STD_LOGIC; + SIGNAL wire_niil01Oi_dataout : STD_LOGIC; + SIGNAL wire_niil01Ol_dataout : STD_LOGIC; + SIGNAL wire_niil01OO_dataout : STD_LOGIC; + SIGNAL wire_niil0i0i_dataout : STD_LOGIC; + SIGNAL wire_niil0i0l_dataout : STD_LOGIC; + SIGNAL wire_niil0i0O_dataout : STD_LOGIC; + SIGNAL wire_niil0i1l_dataout : STD_LOGIC; + SIGNAL wire_niil0i1l_w_lg_w_lg_dataout9952w9953w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niil0i1l_w_lg_dataout9952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niil0i1l_w_lg_w_lg_w_lg_dataout9952w9953w9956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niil0i1O_dataout : STD_LOGIC; + SIGNAL wire_niil0ii_dataout : STD_LOGIC; + SIGNAL wire_niil0iiO_dataout : STD_LOGIC; + SIGNAL wire_niil0il_dataout : STD_LOGIC; + SIGNAL wire_niil0ili_dataout : STD_LOGIC; + SIGNAL wire_niil0ill_dataout : STD_LOGIC; + SIGNAL wire_niil0ilO_dataout : STD_LOGIC; + SIGNAL wire_niil0iO_dataout : STD_LOGIC; + SIGNAL wire_niil0iOi_dataout : STD_LOGIC; + SIGNAL wire_niil0iOl_dataout : STD_LOGIC; + SIGNAL wire_niil0l0O_dataout : STD_LOGIC; + SIGNAL wire_niil0l1i_dataout : STD_LOGIC; + SIGNAL wire_niil0li_dataout : STD_LOGIC; + SIGNAL wire_niil0ll_dataout : STD_LOGIC; + SIGNAL wire_niil0lO_dataout : STD_LOGIC; + SIGNAL wire_niil0lOO_dataout : STD_LOGIC; + SIGNAL wire_niil0O0i_dataout : STD_LOGIC; + SIGNAL wire_niil0O0l_dataout : STD_LOGIC; + SIGNAL wire_niil0O0O_dataout : STD_LOGIC; + SIGNAL wire_niil0O1i_dataout : STD_LOGIC; + SIGNAL wire_niil0O1l_dataout : STD_LOGIC; + SIGNAL wire_niil0O1O_dataout : STD_LOGIC; + SIGNAL wire_niil0Oi_dataout : STD_LOGIC; + SIGNAL wire_niil0Oii_dataout : STD_LOGIC; + SIGNAL wire_niil0Oil_dataout : STD_LOGIC; + SIGNAL wire_niil0OiO_dataout : STD_LOGIC; + SIGNAL wire_niil0Ol_dataout : STD_LOGIC; + SIGNAL wire_niil0Oli_dataout : STD_LOGIC; + SIGNAL wire_niil0Oll_dataout : STD_LOGIC; + SIGNAL wire_niil0OlO_dataout : STD_LOGIC; + SIGNAL wire_niil0OO_dataout : STD_LOGIC; + SIGNAL wire_niil0OOi_dataout : STD_LOGIC; + SIGNAL wire_niil0OOl_dataout : STD_LOGIC; + SIGNAL wire_niil0OOO_dataout : STD_LOGIC; + SIGNAL wire_niil100i_dataout : STD_LOGIC; + SIGNAL wire_niil100l_dataout : STD_LOGIC; + SIGNAL wire_niil100O_dataout : STD_LOGIC; + SIGNAL wire_niil101i_dataout : STD_LOGIC; + SIGNAL wire_niil101l_dataout : STD_LOGIC; + SIGNAL wire_niil101O_dataout : STD_LOGIC; + SIGNAL wire_niil10i_dataout : STD_LOGIC; + SIGNAL wire_niil10ii_dataout : STD_LOGIC; + SIGNAL wire_niil10il_dataout : STD_LOGIC; + SIGNAL wire_niil10iO_dataout : STD_LOGIC; + SIGNAL wire_niil10l_dataout : STD_LOGIC; + SIGNAL wire_niil10li_dataout : STD_LOGIC; + SIGNAL wire_niil10ll_dataout : STD_LOGIC; + SIGNAL wire_niil10lO_dataout : STD_LOGIC; + SIGNAL wire_niil10O_dataout : STD_LOGIC; + SIGNAL wire_niil10Oi_dataout : STD_LOGIC; + SIGNAL wire_niil10Ol_dataout : STD_LOGIC; + SIGNAL wire_niil10OO_dataout : STD_LOGIC; + SIGNAL wire_niil110i_dataout : STD_LOGIC; + SIGNAL wire_niil110l_dataout : STD_LOGIC; + SIGNAL wire_niil110O_dataout : STD_LOGIC; + SIGNAL wire_niil111i_dataout : STD_LOGIC; + SIGNAL wire_niil111l_dataout : STD_LOGIC; + SIGNAL wire_niil111O_dataout : STD_LOGIC; + SIGNAL wire_niil11i_dataout : STD_LOGIC; + SIGNAL wire_niil11ii_dataout : STD_LOGIC; + SIGNAL wire_niil11il_dataout : STD_LOGIC; + SIGNAL wire_niil11iO_dataout : STD_LOGIC; + SIGNAL wire_niil11l_dataout : STD_LOGIC; + SIGNAL wire_niil11li_dataout : STD_LOGIC; + SIGNAL wire_niil11ll_dataout : STD_LOGIC; + SIGNAL wire_niil11lO_dataout : STD_LOGIC; + SIGNAL wire_niil11O_dataout : STD_LOGIC; + SIGNAL wire_niil11Oi_dataout : STD_LOGIC; + SIGNAL wire_niil11Ol_dataout : STD_LOGIC; + SIGNAL wire_niil11OO_dataout : STD_LOGIC; + SIGNAL wire_niil1i0i_dataout : STD_LOGIC; + SIGNAL wire_niil1i0l_dataout : STD_LOGIC; + SIGNAL wire_niil1i0O_dataout : STD_LOGIC; + SIGNAL wire_niil1i1i_dataout : STD_LOGIC; + SIGNAL wire_niil1i1l_dataout : STD_LOGIC; + SIGNAL wire_niil1i1O_dataout : STD_LOGIC; + SIGNAL wire_niil1ii_dataout : STD_LOGIC; + SIGNAL wire_niil1iii_dataout : STD_LOGIC; + SIGNAL wire_niil1iil_dataout : STD_LOGIC; + SIGNAL wire_niil1iiO_dataout : STD_LOGIC; + SIGNAL wire_niil1il_dataout : STD_LOGIC; + SIGNAL wire_niil1ili_dataout : STD_LOGIC; + SIGNAL wire_niil1ill_dataout : STD_LOGIC; + SIGNAL wire_niil1ilO_dataout : STD_LOGIC; + SIGNAL wire_niil1iO_dataout : STD_LOGIC; + SIGNAL wire_niil1iOi_dataout : STD_LOGIC; + SIGNAL wire_niil1iOl_dataout : STD_LOGIC; + SIGNAL wire_niil1iOO_dataout : STD_LOGIC; + SIGNAL wire_niil1l0i_dataout : STD_LOGIC; + SIGNAL wire_niil1l0l_dataout : STD_LOGIC; + SIGNAL wire_niil1l0O_dataout : STD_LOGIC; + SIGNAL wire_niil1l1i_dataout : STD_LOGIC; + SIGNAL wire_niil1l1l_dataout : STD_LOGIC; + SIGNAL wire_niil1l1O_dataout : STD_LOGIC; + SIGNAL wire_niil1li_dataout : STD_LOGIC; + SIGNAL wire_niil1lii_dataout : STD_LOGIC; + SIGNAL wire_niil1lil_dataout : STD_LOGIC; + SIGNAL wire_niil1liO_dataout : STD_LOGIC; + SIGNAL wire_niil1ll_dataout : STD_LOGIC; + SIGNAL wire_niil1lli_dataout : STD_LOGIC; + SIGNAL wire_niil1lll_dataout : STD_LOGIC; + SIGNAL wire_niil1llO_dataout : STD_LOGIC; + SIGNAL wire_niil1lO_dataout : STD_LOGIC; + SIGNAL wire_niil1lOi_dataout : STD_LOGIC; + SIGNAL wire_niil1lOl_dataout : STD_LOGIC; + SIGNAL wire_niil1lOO_dataout : STD_LOGIC; + SIGNAL wire_niil1O0i_dataout : STD_LOGIC; + SIGNAL wire_niil1O0l_dataout : STD_LOGIC; + SIGNAL wire_niil1O0O_dataout : STD_LOGIC; + SIGNAL wire_niil1O1i_dataout : STD_LOGIC; + SIGNAL wire_niil1O1l_dataout : STD_LOGIC; + SIGNAL wire_niil1O1O_dataout : STD_LOGIC; + SIGNAL wire_niil1Oi_dataout : STD_LOGIC; + SIGNAL wire_niil1Oii_dataout : STD_LOGIC; + SIGNAL wire_niil1Oil_dataout : STD_LOGIC; + SIGNAL wire_niil1OiO_dataout : STD_LOGIC; + SIGNAL wire_niil1Ol_dataout : STD_LOGIC; + SIGNAL wire_niil1Oli_dataout : STD_LOGIC; + SIGNAL wire_niil1Oll_dataout : STD_LOGIC; + SIGNAL wire_niil1OlO_dataout : STD_LOGIC; + SIGNAL wire_niil1OO_dataout : STD_LOGIC; + SIGNAL wire_niili00i_dataout : STD_LOGIC; + SIGNAL wire_niili00l_dataout : STD_LOGIC; + SIGNAL wire_niili00O_dataout : STD_LOGIC; + SIGNAL wire_niili01i_dataout : STD_LOGIC; + SIGNAL wire_niili01l_dataout : STD_LOGIC; + SIGNAL wire_niili01O_dataout : STD_LOGIC; + SIGNAL wire_niili0i_dataout : STD_LOGIC; + SIGNAL wire_niili0ii_dataout : STD_LOGIC; + SIGNAL wire_niili0il_dataout : STD_LOGIC; + SIGNAL wire_niili0iO_dataout : STD_LOGIC; + SIGNAL wire_niili0l_dataout : STD_LOGIC; + SIGNAL wire_niili0li_dataout : STD_LOGIC; + SIGNAL wire_niili0ll_dataout : STD_LOGIC; + SIGNAL wire_niili0lO_dataout : STD_LOGIC; + SIGNAL wire_niili0O_dataout : STD_LOGIC; + SIGNAL wire_niili0Oi_dataout : STD_LOGIC; + SIGNAL wire_niili0Ol_dataout : STD_LOGIC; + SIGNAL wire_niili0OO_dataout : STD_LOGIC; + SIGNAL wire_niili10i_dataout : STD_LOGIC; + SIGNAL wire_niili10l_dataout : STD_LOGIC; + SIGNAL wire_niili10O_dataout : STD_LOGIC; + SIGNAL wire_niili11i_dataout : STD_LOGIC; + SIGNAL wire_niili11l_dataout : STD_LOGIC; + SIGNAL wire_niili11O_dataout : STD_LOGIC; + SIGNAL wire_niili1i_dataout : STD_LOGIC; + SIGNAL wire_niili1ii_dataout : STD_LOGIC; + SIGNAL wire_niili1il_dataout : STD_LOGIC; + SIGNAL wire_niili1l_dataout : STD_LOGIC; + SIGNAL wire_niili1O_dataout : STD_LOGIC; + SIGNAL wire_niili1Ol_dataout : STD_LOGIC; + SIGNAL wire_niili1OO_dataout : STD_LOGIC; + SIGNAL wire_niilii0i_dataout : STD_LOGIC; + SIGNAL wire_niilii0l_dataout : STD_LOGIC; + SIGNAL wire_niilii0O_dataout : STD_LOGIC; + SIGNAL wire_niilii1i_dataout : STD_LOGIC; + SIGNAL wire_niilii1l_dataout : STD_LOGIC; + SIGNAL wire_niilii1O_dataout : STD_LOGIC; + SIGNAL wire_niiliii_dataout : STD_LOGIC; + SIGNAL wire_niiliiii_dataout : STD_LOGIC; + SIGNAL wire_niiliiil_dataout : STD_LOGIC; + SIGNAL wire_niiliiiO_dataout : STD_LOGIC; + SIGNAL wire_niiliil_dataout : STD_LOGIC; + SIGNAL wire_niiliili_dataout : STD_LOGIC; + SIGNAL wire_niiliill_dataout : STD_LOGIC; + SIGNAL wire_niiliilO_dataout : STD_LOGIC; + SIGNAL wire_niiliiO_dataout : STD_LOGIC; + SIGNAL wire_niiliiOi_dataout : STD_LOGIC; + SIGNAL wire_niiliiOl_dataout : STD_LOGIC; + SIGNAL wire_niiliiOO_dataout : STD_LOGIC; + SIGNAL wire_niilil1i_dataout : STD_LOGIC; + SIGNAL wire_niilil1l_dataout : STD_LOGIC; + SIGNAL wire_niilili_dataout : STD_LOGIC; + SIGNAL wire_niilill_dataout : STD_LOGIC; + SIGNAL wire_niililO_dataout : STD_LOGIC; + SIGNAL wire_niiliOi_dataout : STD_LOGIC; + SIGNAL wire_niiliOl_dataout : STD_LOGIC; + SIGNAL wire_niiliOO_dataout : STD_LOGIC; + SIGNAL wire_niill0i_dataout : STD_LOGIC; + SIGNAL wire_niill0l_dataout : STD_LOGIC; + SIGNAL wire_niill0O_dataout : STD_LOGIC; + SIGNAL wire_niill1i_dataout : STD_LOGIC; + SIGNAL wire_niill1l_dataout : STD_LOGIC; + SIGNAL wire_niill1O_dataout : STD_LOGIC; + SIGNAL wire_niillii_dataout : STD_LOGIC; + SIGNAL wire_niillil_dataout : STD_LOGIC; + SIGNAL wire_niilliO_dataout : STD_LOGIC; + SIGNAL wire_niilliOl_dataout : STD_LOGIC; + SIGNAL wire_niilliOO_dataout : STD_LOGIC; + SIGNAL wire_niilll0i_dataout : STD_LOGIC; + SIGNAL wire_niilll0l_dataout : STD_LOGIC; + SIGNAL wire_niilll0O_dataout : STD_LOGIC; + SIGNAL wire_niilll1i_dataout : STD_LOGIC; + SIGNAL wire_niilll1l_dataout : STD_LOGIC; + SIGNAL wire_niilll1O_dataout : STD_LOGIC; + SIGNAL wire_niillli_dataout : STD_LOGIC; + SIGNAL wire_niilllii_dataout : STD_LOGIC; + SIGNAL wire_niilllil_dataout : STD_LOGIC; + SIGNAL wire_niillliO_dataout : STD_LOGIC; + SIGNAL wire_niillll_dataout : STD_LOGIC; + SIGNAL wire_niilllli_dataout : STD_LOGIC; + SIGNAL wire_niilllll_dataout : STD_LOGIC; + SIGNAL wire_niillllO_dataout : STD_LOGIC; + SIGNAL wire_niilllO_dataout : STD_LOGIC; + SIGNAL wire_niilllOi_dataout : STD_LOGIC; + SIGNAL wire_niilllOl_dataout : STD_LOGIC; + SIGNAL wire_niilllOO_dataout : STD_LOGIC; + SIGNAL wire_niillO0i_dataout : STD_LOGIC; + SIGNAL wire_niillO0l_dataout : STD_LOGIC; + SIGNAL wire_niillO0O_dataout : STD_LOGIC; + SIGNAL wire_niillO1i_dataout : STD_LOGIC; + SIGNAL wire_niillO1l_dataout : STD_LOGIC; + SIGNAL wire_niillO1O_dataout : STD_LOGIC; + SIGNAL wire_niillOi_dataout : STD_LOGIC; + SIGNAL wire_niillOii_dataout : STD_LOGIC; + SIGNAL wire_niillOl_dataout : STD_LOGIC; + SIGNAL wire_niillOll_dataout : STD_LOGIC; + SIGNAL wire_niillOlO_dataout : STD_LOGIC; + SIGNAL wire_niillOO_dataout : STD_LOGIC; + SIGNAL wire_niillOOi_dataout : STD_LOGIC; + SIGNAL wire_niillOOl_dataout : STD_LOGIC; + SIGNAL wire_niillOOO_dataout : STD_LOGIC; + SIGNAL wire_niilO00i_dataout : STD_LOGIC; + SIGNAL wire_niilO00l_dataout : STD_LOGIC; + SIGNAL wire_niilO00O_dataout : STD_LOGIC; + SIGNAL wire_niilO01i_dataout : STD_LOGIC; + SIGNAL wire_niilO01l_dataout : STD_LOGIC; + SIGNAL wire_niilO01O_dataout : STD_LOGIC; + SIGNAL wire_niilO0i_dataout : STD_LOGIC; + SIGNAL wire_niilO0ii_dataout : STD_LOGIC; + SIGNAL wire_niilO0il_dataout : STD_LOGIC; + SIGNAL wire_niilO0iO_dataout : STD_LOGIC; + SIGNAL wire_niilO0l_dataout : STD_LOGIC; + SIGNAL wire_niilO0li_dataout : STD_LOGIC; + SIGNAL wire_niilO0ll_dataout : STD_LOGIC; + SIGNAL wire_niilO0lO_dataout : STD_LOGIC; + SIGNAL wire_niilO0O_dataout : STD_LOGIC; + SIGNAL wire_niilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niilO0OO_dataout : STD_LOGIC; + SIGNAL wire_niilO10i_dataout : STD_LOGIC; + SIGNAL wire_niilO10l_dataout : STD_LOGIC; + SIGNAL wire_niilO10O_dataout : STD_LOGIC; + SIGNAL wire_niilO11i_dataout : STD_LOGIC; + SIGNAL wire_niilO11l_dataout : STD_LOGIC; + SIGNAL wire_niilO11O_dataout : STD_LOGIC; + SIGNAL wire_niilO1i_dataout : STD_LOGIC; + SIGNAL wire_niilO1ii_dataout : STD_LOGIC; + SIGNAL wire_niilO1iO_dataout : STD_LOGIC; + SIGNAL wire_niilO1l_dataout : STD_LOGIC; + SIGNAL wire_niilO1li_dataout : STD_LOGIC; + SIGNAL wire_niilO1ll_dataout : STD_LOGIC; + SIGNAL wire_niilO1lO_dataout : STD_LOGIC; + SIGNAL wire_niilO1O_dataout : STD_LOGIC; + SIGNAL wire_niilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niilO1OO_dataout : STD_LOGIC; + SIGNAL wire_niilOi0i_dataout : STD_LOGIC; + SIGNAL wire_niilOi0l_dataout : STD_LOGIC; + SIGNAL wire_niilOi0O_dataout : STD_LOGIC; + SIGNAL wire_niilOi1i_dataout : STD_LOGIC; + SIGNAL wire_niilOi1l_dataout : STD_LOGIC; + SIGNAL wire_niilOi1O_dataout : STD_LOGIC; + SIGNAL wire_niilOii_dataout : STD_LOGIC; + SIGNAL wire_niilOiii_dataout : STD_LOGIC; + SIGNAL wire_niilOiil_dataout : STD_LOGIC; + SIGNAL wire_niilOiiO_dataout : STD_LOGIC; + SIGNAL wire_niilOil_dataout : STD_LOGIC; + SIGNAL wire_niilOili_dataout : STD_LOGIC; + SIGNAL wire_niilOill_dataout : STD_LOGIC; + SIGNAL wire_niilOilO_dataout : STD_LOGIC; + SIGNAL wire_niilOiO_dataout : STD_LOGIC; + SIGNAL wire_niilOiOi_dataout : STD_LOGIC; + SIGNAL wire_niilOiOl_dataout : STD_LOGIC; + SIGNAL wire_niilOiOO_dataout : STD_LOGIC; + SIGNAL wire_niilOl0i_dataout : STD_LOGIC; + SIGNAL wire_niilOl0l_dataout : STD_LOGIC; + SIGNAL wire_niilOl0O_dataout : STD_LOGIC; + SIGNAL wire_niilOl1i_dataout : STD_LOGIC; + SIGNAL wire_niilOl1l_dataout : STD_LOGIC; + SIGNAL wire_niilOl1O_dataout : STD_LOGIC; + SIGNAL wire_niilOli_dataout : STD_LOGIC; + SIGNAL wire_niilOlii_dataout : STD_LOGIC; + SIGNAL wire_niilOlil_dataout : STD_LOGIC; + SIGNAL wire_niilOliO_dataout : STD_LOGIC; + SIGNAL wire_niilOll_dataout : STD_LOGIC; + SIGNAL wire_niilOlli_dataout : STD_LOGIC; + SIGNAL wire_niilOlll_dataout : STD_LOGIC; + SIGNAL wire_niilOllO_dataout : STD_LOGIC; + SIGNAL wire_niilOlO_dataout : STD_LOGIC; + SIGNAL wire_niilOlOi_dataout : STD_LOGIC; + SIGNAL wire_niilOlOl_dataout : STD_LOGIC; + SIGNAL wire_niilOlOO_dataout : STD_LOGIC; + SIGNAL wire_niilOO0i_dataout : STD_LOGIC; + SIGNAL wire_niilOO0l_dataout : STD_LOGIC; + SIGNAL wire_niilOO0O_dataout : STD_LOGIC; + SIGNAL wire_niilOO1i_dataout : STD_LOGIC; + SIGNAL wire_niilOO1l_dataout : STD_LOGIC; + SIGNAL wire_niilOO1O_dataout : STD_LOGIC; + SIGNAL wire_niilOOi_dataout : STD_LOGIC; + SIGNAL wire_niilOOii_dataout : STD_LOGIC; + SIGNAL wire_niilOOil_dataout : STD_LOGIC; + SIGNAL wire_niilOOiO_dataout : STD_LOGIC; + SIGNAL wire_niilOOl_dataout : STD_LOGIC; + SIGNAL wire_niilOOli_dataout : STD_LOGIC; + SIGNAL wire_niilOOll_dataout : STD_LOGIC; + SIGNAL wire_niilOOlO_dataout : STD_LOGIC; + SIGNAL wire_niilOOO_dataout : STD_LOGIC; + SIGNAL wire_niilOOOi_dataout : STD_LOGIC; + SIGNAL wire_niilOOOl_dataout : STD_LOGIC; + SIGNAL wire_niilOOOO_dataout : STD_LOGIC; + SIGNAL wire_niiO000i_dataout : STD_LOGIC; + SIGNAL wire_niiO000l_dataout : STD_LOGIC; + SIGNAL wire_niiO000O_dataout : STD_LOGIC; + SIGNAL wire_niiO001i_dataout : STD_LOGIC; + SIGNAL wire_niiO001l_dataout : STD_LOGIC; + SIGNAL wire_niiO001O_dataout : STD_LOGIC; + SIGNAL wire_niiO00i_dataout : STD_LOGIC; + SIGNAL wire_niiO00ii_dataout : STD_LOGIC; + SIGNAL wire_niiO00il_dataout : STD_LOGIC; + SIGNAL wire_niiO00iO_dataout : STD_LOGIC; + SIGNAL wire_niiO00l_dataout : STD_LOGIC; + SIGNAL wire_niiO00li_dataout : STD_LOGIC; + SIGNAL wire_niiO00ll_dataout : STD_LOGIC; + SIGNAL wire_niiO00lO_dataout : STD_LOGIC; + SIGNAL wire_niiO00O_dataout : STD_LOGIC; + SIGNAL wire_niiO00Oi_dataout : STD_LOGIC; + SIGNAL wire_niiO00Ol_dataout : STD_LOGIC; + SIGNAL wire_niiO00OO_dataout : STD_LOGIC; + SIGNAL wire_niiO010i_dataout : STD_LOGIC; + SIGNAL wire_niiO010l_dataout : STD_LOGIC; + SIGNAL wire_niiO010O_dataout : STD_LOGIC; + SIGNAL wire_niiO011i_dataout : STD_LOGIC; + SIGNAL wire_niiO011l_dataout : STD_LOGIC; + SIGNAL wire_niiO011O_dataout : STD_LOGIC; + SIGNAL wire_niiO01i_dataout : STD_LOGIC; + SIGNAL wire_niiO01ii_dataout : STD_LOGIC; + SIGNAL wire_niiO01il_dataout : STD_LOGIC; + SIGNAL wire_niiO01iO_dataout : STD_LOGIC; + SIGNAL wire_niiO01l_dataout : STD_LOGIC; + SIGNAL wire_niiO01li_dataout : STD_LOGIC; + SIGNAL wire_niiO01ll_dataout : STD_LOGIC; + SIGNAL wire_niiO01lO_dataout : STD_LOGIC; + SIGNAL wire_niiO01O_dataout : STD_LOGIC; + SIGNAL wire_niiO01Oi_dataout : STD_LOGIC; + SIGNAL wire_niiO01Ol_dataout : STD_LOGIC; + SIGNAL wire_niiO01OO_dataout : STD_LOGIC; + SIGNAL wire_niiO0i0i_dataout : STD_LOGIC; + SIGNAL wire_niiO0i0l_dataout : STD_LOGIC; + SIGNAL wire_niiO0i0O_dataout : STD_LOGIC; + SIGNAL wire_niiO0i1i_dataout : STD_LOGIC; + SIGNAL wire_niiO0i1l_dataout : STD_LOGIC; + SIGNAL wire_niiO0i1O_dataout : STD_LOGIC; + SIGNAL wire_niiO0ii_dataout : STD_LOGIC; + SIGNAL wire_niiO0iii_dataout : STD_LOGIC; + SIGNAL wire_niiO0iil_dataout : STD_LOGIC; + SIGNAL wire_niiO0iiO_dataout : STD_LOGIC; + SIGNAL wire_niiO0il_dataout : STD_LOGIC; + SIGNAL wire_niiO0ili_dataout : STD_LOGIC; + SIGNAL wire_niiO0ill_dataout : STD_LOGIC; + SIGNAL wire_niiO0ilO_dataout : STD_LOGIC; + SIGNAL wire_niiO0iO_dataout : STD_LOGIC; + SIGNAL wire_niiO0iOi_dataout : STD_LOGIC; + SIGNAL wire_niiO0iOl_dataout : STD_LOGIC; + SIGNAL wire_niiO0iOO_dataout : STD_LOGIC; + SIGNAL wire_niiO0l0i_dataout : STD_LOGIC; + SIGNAL wire_niiO0l0l_dataout : STD_LOGIC; + SIGNAL wire_niiO0l0O_dataout : STD_LOGIC; + SIGNAL wire_niiO0l1i_dataout : STD_LOGIC; + SIGNAL wire_niiO0l1l_dataout : STD_LOGIC; + SIGNAL wire_niiO0l1O_dataout : STD_LOGIC; + SIGNAL wire_niiO0li_dataout : STD_LOGIC; + SIGNAL wire_niiO0lii_dataout : STD_LOGIC; + SIGNAL wire_niiO0lil_dataout : STD_LOGIC; + SIGNAL wire_niiO0liO_dataout : STD_LOGIC; + SIGNAL wire_niiO0ll_dataout : STD_LOGIC; + SIGNAL wire_niiO0lli_dataout : STD_LOGIC; + SIGNAL wire_niiO0lll_dataout : STD_LOGIC; + SIGNAL wire_niiO0llO_dataout : STD_LOGIC; + SIGNAL wire_niiO0lO_dataout : STD_LOGIC; + SIGNAL wire_niiO0lOi_dataout : STD_LOGIC; + SIGNAL wire_niiO0lOl_dataout : STD_LOGIC; + SIGNAL wire_niiO0lOO_dataout : STD_LOGIC; + SIGNAL wire_niiO0O0i_dataout : STD_LOGIC; + SIGNAL wire_niiO0O0l_dataout : STD_LOGIC; + SIGNAL wire_niiO0O0O_dataout : STD_LOGIC; + SIGNAL wire_niiO0O1i_dataout : STD_LOGIC; + SIGNAL wire_niiO0O1l_dataout : STD_LOGIC; + SIGNAL wire_niiO0O1O_dataout : STD_LOGIC; + SIGNAL wire_niiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niiO0Oii_dataout : STD_LOGIC; + SIGNAL wire_niiO0Oil_dataout : STD_LOGIC; + SIGNAL wire_niiO0OiO_dataout : STD_LOGIC; + SIGNAL wire_niiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niiO0Oli_dataout : STD_LOGIC; + SIGNAL wire_niiO0Oll_dataout : STD_LOGIC; + SIGNAL wire_niiO0OlO_dataout : STD_LOGIC; + SIGNAL wire_niiO0OO_dataout : STD_LOGIC; + SIGNAL wire_niiO0OOi_dataout : STD_LOGIC; + SIGNAL wire_niiO0OOl_dataout : STD_LOGIC; + SIGNAL wire_niiO0OOO_dataout : STD_LOGIC; + SIGNAL wire_niiO100i_dataout : STD_LOGIC; + SIGNAL wire_niiO100l_dataout : STD_LOGIC; + SIGNAL wire_niiO100O_dataout : STD_LOGIC; + SIGNAL wire_niiO101i_dataout : STD_LOGIC; + SIGNAL wire_niiO101l_dataout : STD_LOGIC; + SIGNAL wire_niiO101O_dataout : STD_LOGIC; + SIGNAL wire_niiO10i_dataout : STD_LOGIC; + SIGNAL wire_niiO10ii_dataout : STD_LOGIC; + SIGNAL wire_niiO10il_dataout : STD_LOGIC; + SIGNAL wire_niiO10iO_dataout : STD_LOGIC; + SIGNAL wire_niiO10l_dataout : STD_LOGIC; + SIGNAL wire_niiO10li_dataout : STD_LOGIC; + SIGNAL wire_niiO10ll_dataout : STD_LOGIC; + SIGNAL wire_niiO10lO_dataout : STD_LOGIC; + SIGNAL wire_niiO10O_dataout : STD_LOGIC; + SIGNAL wire_niiO10Oi_dataout : STD_LOGIC; + SIGNAL wire_niiO10Ol_dataout : STD_LOGIC; + SIGNAL wire_niiO10OO_dataout : STD_LOGIC; + SIGNAL wire_niiO110i_dataout : STD_LOGIC; + SIGNAL wire_niiO110l_dataout : STD_LOGIC; + SIGNAL wire_niiO110O_dataout : STD_LOGIC; + SIGNAL wire_niiO111i_dataout : STD_LOGIC; + SIGNAL wire_niiO111l_dataout : STD_LOGIC; + SIGNAL wire_niiO111O_dataout : STD_LOGIC; + SIGNAL wire_niiO11i_dataout : STD_LOGIC; + SIGNAL wire_niiO11ii_dataout : STD_LOGIC; + SIGNAL wire_niiO11il_dataout : STD_LOGIC; + SIGNAL wire_niiO11iO_dataout : STD_LOGIC; + SIGNAL wire_niiO11l_dataout : STD_LOGIC; + SIGNAL wire_niiO11li_dataout : STD_LOGIC; + SIGNAL wire_niiO11ll_dataout : STD_LOGIC; + SIGNAL wire_niiO11lO_dataout : STD_LOGIC; + SIGNAL wire_niiO11O_dataout : STD_LOGIC; + SIGNAL wire_niiO11Oi_dataout : STD_LOGIC; + SIGNAL wire_niiO11Ol_dataout : STD_LOGIC; + SIGNAL wire_niiO11OO_dataout : STD_LOGIC; + SIGNAL wire_niiO1i0i_dataout : STD_LOGIC; + SIGNAL wire_niiO1i0l_dataout : STD_LOGIC; + SIGNAL wire_niiO1i0O_dataout : STD_LOGIC; + SIGNAL wire_niiO1i1i_dataout : STD_LOGIC; + SIGNAL wire_niiO1i1l_dataout : STD_LOGIC; + SIGNAL wire_niiO1i1O_dataout : STD_LOGIC; + SIGNAL wire_niiO1ii_dataout : STD_LOGIC; + SIGNAL wire_niiO1iii_dataout : STD_LOGIC; + SIGNAL wire_niiO1iil_dataout : STD_LOGIC; + SIGNAL wire_niiO1iiO_dataout : STD_LOGIC; + SIGNAL wire_niiO1il_dataout : STD_LOGIC; + SIGNAL wire_niiO1ili_dataout : STD_LOGIC; + SIGNAL wire_niiO1ill_dataout : STD_LOGIC; + SIGNAL wire_niiO1ilO_dataout : STD_LOGIC; + SIGNAL wire_niiO1iO_dataout : STD_LOGIC; + SIGNAL wire_niiO1iOi_dataout : STD_LOGIC; + SIGNAL wire_niiO1iOl_dataout : STD_LOGIC; + SIGNAL wire_niiO1iOO_dataout : STD_LOGIC; + SIGNAL wire_niiO1l0i_dataout : STD_LOGIC; + SIGNAL wire_niiO1l0l_dataout : STD_LOGIC; + SIGNAL wire_niiO1l0O_dataout : STD_LOGIC; + SIGNAL wire_niiO1l1i_dataout : STD_LOGIC; + SIGNAL wire_niiO1l1l_dataout : STD_LOGIC; + SIGNAL wire_niiO1l1O_dataout : STD_LOGIC; + SIGNAL wire_niiO1li_dataout : STD_LOGIC; + SIGNAL wire_niiO1lii_dataout : STD_LOGIC; + SIGNAL wire_niiO1lil_dataout : STD_LOGIC; + SIGNAL wire_niiO1liO_dataout : STD_LOGIC; + SIGNAL wire_niiO1ll_dataout : STD_LOGIC; + SIGNAL wire_niiO1lli_dataout : STD_LOGIC; + SIGNAL wire_niiO1lll_dataout : STD_LOGIC; + SIGNAL wire_niiO1llO_dataout : STD_LOGIC; + SIGNAL wire_niiO1lO_dataout : STD_LOGIC; + SIGNAL wire_niiO1lOi_dataout : STD_LOGIC; + SIGNAL wire_niiO1lOl_dataout : STD_LOGIC; + SIGNAL wire_niiO1lOO_dataout : STD_LOGIC; + SIGNAL wire_niiO1O0i_dataout : STD_LOGIC; + SIGNAL wire_niiO1O0l_dataout : STD_LOGIC; + SIGNAL wire_niiO1O0O_dataout : STD_LOGIC; + SIGNAL wire_niiO1O1i_dataout : STD_LOGIC; + SIGNAL wire_niiO1O1l_dataout : STD_LOGIC; + SIGNAL wire_niiO1O1O_dataout : STD_LOGIC; + SIGNAL wire_niiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niiO1Oii_dataout : STD_LOGIC; + SIGNAL wire_niiO1Oil_dataout : STD_LOGIC; + SIGNAL wire_niiO1OiO_dataout : STD_LOGIC; + SIGNAL wire_niiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niiO1Oli_dataout : STD_LOGIC; + SIGNAL wire_niiO1Oll_dataout : STD_LOGIC; + SIGNAL wire_niiO1OlO_dataout : STD_LOGIC; + SIGNAL wire_niiO1OO_dataout : STD_LOGIC; + SIGNAL wire_niiO1OOi_dataout : STD_LOGIC; + SIGNAL wire_niiO1OOl_dataout : STD_LOGIC; + SIGNAL wire_niiO1OOO_dataout : STD_LOGIC; + SIGNAL wire_niiOi00i_dataout : STD_LOGIC; + SIGNAL wire_niiOi00l_dataout : STD_LOGIC; + SIGNAL wire_niiOi00O_dataout : STD_LOGIC; + SIGNAL wire_niiOi01i_dataout : STD_LOGIC; + SIGNAL wire_niiOi01l_dataout : STD_LOGIC; + SIGNAL wire_niiOi01O_dataout : STD_LOGIC; + SIGNAL wire_niiOi0i_dataout : STD_LOGIC; + SIGNAL wire_niiOi0ii_dataout : STD_LOGIC; + SIGNAL wire_niiOi0il_dataout : STD_LOGIC; + SIGNAL wire_niiOi0iO_dataout : STD_LOGIC; + SIGNAL wire_niiOi0l_dataout : STD_LOGIC; + SIGNAL wire_niiOi0li_dataout : STD_LOGIC; + SIGNAL wire_niiOi0ll_dataout : STD_LOGIC; + SIGNAL wire_niiOi0lO_dataout : STD_LOGIC; + SIGNAL wire_niiOi0O_dataout : STD_LOGIC; + SIGNAL wire_niiOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_niiOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_niiOi0OO_dataout : STD_LOGIC; + SIGNAL wire_niiOi10i_dataout : STD_LOGIC; + SIGNAL wire_niiOi10l_dataout : STD_LOGIC; + SIGNAL wire_niiOi10O_dataout : STD_LOGIC; + SIGNAL wire_niiOi11i_dataout : STD_LOGIC; + SIGNAL wire_niiOi11l_dataout : STD_LOGIC; + SIGNAL wire_niiOi11O_dataout : STD_LOGIC; + SIGNAL wire_niiOi1i_dataout : STD_LOGIC; + SIGNAL wire_niiOi1ii_dataout : STD_LOGIC; + SIGNAL wire_niiOi1il_dataout : STD_LOGIC; + SIGNAL wire_niiOi1iO_dataout : STD_LOGIC; + SIGNAL wire_niiOi1l_dataout : STD_LOGIC; + SIGNAL wire_niiOi1li_dataout : STD_LOGIC; + SIGNAL wire_niiOi1ll_dataout : STD_LOGIC; + SIGNAL wire_niiOi1lO_dataout : STD_LOGIC; + SIGNAL wire_niiOi1O_dataout : STD_LOGIC; + SIGNAL wire_niiOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_niiOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_niiOi1OO_dataout : STD_LOGIC; + SIGNAL wire_niiOii0i_dataout : STD_LOGIC; + SIGNAL wire_niiOii0l_dataout : STD_LOGIC; + SIGNAL wire_niiOii0O_dataout : STD_LOGIC; + SIGNAL wire_niiOii1i_dataout : STD_LOGIC; + SIGNAL wire_niiOii1l_dataout : STD_LOGIC; + SIGNAL wire_niiOii1O_dataout : STD_LOGIC; + SIGNAL wire_niiOiii_dataout : STD_LOGIC; + SIGNAL wire_niiOiiii_dataout : STD_LOGIC; + SIGNAL wire_niiOiiil_dataout : STD_LOGIC; + SIGNAL wire_niiOiiiO_dataout : STD_LOGIC; + SIGNAL wire_niiOiil_dataout : STD_LOGIC; + SIGNAL wire_niiOiili_dataout : STD_LOGIC; + SIGNAL wire_niiOiill_dataout : STD_LOGIC; + SIGNAL wire_niiOiilO_dataout : STD_LOGIC; + SIGNAL wire_niiOiiO_dataout : STD_LOGIC; + SIGNAL wire_niiOiiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOiiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOiiOO_dataout : STD_LOGIC; + SIGNAL wire_niiOil0i_dataout : STD_LOGIC; + SIGNAL wire_niiOil0l_dataout : STD_LOGIC; + SIGNAL wire_niiOil0O_dataout : STD_LOGIC; + SIGNAL wire_niiOil1i_dataout : STD_LOGIC; + SIGNAL wire_niiOil1l_dataout : STD_LOGIC; + SIGNAL wire_niiOil1O_dataout : STD_LOGIC; + SIGNAL wire_niiOili_dataout : STD_LOGIC; + SIGNAL wire_niiOilii_dataout : STD_LOGIC; + SIGNAL wire_niiOilil_dataout : STD_LOGIC; + SIGNAL wire_niiOiliO_dataout : STD_LOGIC; + SIGNAL wire_niiOill_dataout : STD_LOGIC; + SIGNAL wire_niiOilli_dataout : STD_LOGIC; + SIGNAL wire_niiOilll_dataout : STD_LOGIC; + SIGNAL wire_niiOillO_dataout : STD_LOGIC; + SIGNAL wire_niiOilO_dataout : STD_LOGIC; + SIGNAL wire_niiOilOi_dataout : STD_LOGIC; + SIGNAL wire_niiOilOl_dataout : STD_LOGIC; + SIGNAL wire_niiOilOO_dataout : STD_LOGIC; + SIGNAL wire_niiOiO0i_dataout : STD_LOGIC; + SIGNAL wire_niiOiO0l_dataout : STD_LOGIC; + SIGNAL wire_niiOiO0O_dataout : STD_LOGIC; + SIGNAL wire_niiOiO1i_dataout : STD_LOGIC; + SIGNAL wire_niiOiO1l_dataout : STD_LOGIC; + SIGNAL wire_niiOiO1O_dataout : STD_LOGIC; + SIGNAL wire_niiOiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOiOii_dataout : STD_LOGIC; + SIGNAL wire_niiOiOil_dataout : STD_LOGIC; + SIGNAL wire_niiOiOiO_dataout : STD_LOGIC; + SIGNAL wire_niiOiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOiOli_dataout : STD_LOGIC; + SIGNAL wire_niiOiOll_dataout : STD_LOGIC; + SIGNAL wire_niiOiOlO_dataout : STD_LOGIC; + SIGNAL wire_niiOiOO_dataout : STD_LOGIC; + SIGNAL wire_niiOiOOi_dataout : STD_LOGIC; + SIGNAL wire_niiOiOOl_dataout : STD_LOGIC; + SIGNAL wire_niiOiOOO_dataout : STD_LOGIC; + SIGNAL wire_niiOl00i_dataout : STD_LOGIC; + SIGNAL wire_niiOl00l_dataout : STD_LOGIC; + SIGNAL wire_niiOl00O_dataout : STD_LOGIC; + SIGNAL wire_niiOl01i_dataout : STD_LOGIC; + SIGNAL wire_niiOl01l_dataout : STD_LOGIC; + SIGNAL wire_niiOl01O_dataout : STD_LOGIC; + SIGNAL wire_niiOl0i_dataout : STD_LOGIC; + SIGNAL wire_niiOl0ii_dataout : STD_LOGIC; + SIGNAL wire_niiOl0il_dataout : STD_LOGIC; + SIGNAL wire_niiOl0iO_dataout : STD_LOGIC; + SIGNAL wire_niiOl0l_dataout : STD_LOGIC; + SIGNAL wire_niiOl0li_dataout : STD_LOGIC; + SIGNAL wire_niiOl0ll_dataout : STD_LOGIC; + SIGNAL wire_niiOl0lO_dataout : STD_LOGIC; + SIGNAL wire_niiOl0O_dataout : STD_LOGIC; + SIGNAL wire_niiOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_niiOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_niiOl0OO_dataout : STD_LOGIC; + SIGNAL wire_niiOl10i_dataout : STD_LOGIC; + SIGNAL wire_niiOl10l_dataout : STD_LOGIC; + SIGNAL wire_niiOl10O_dataout : STD_LOGIC; + SIGNAL wire_niiOl11i_dataout : STD_LOGIC; + SIGNAL wire_niiOl11l_dataout : STD_LOGIC; + SIGNAL wire_niiOl11O_dataout : STD_LOGIC; + SIGNAL wire_niiOl1i_dataout : STD_LOGIC; + SIGNAL wire_niiOl1ii_dataout : STD_LOGIC; + SIGNAL wire_niiOl1il_dataout : STD_LOGIC; + SIGNAL wire_niiOl1iO_dataout : STD_LOGIC; + SIGNAL wire_niiOl1l_dataout : STD_LOGIC; + SIGNAL wire_niiOl1li_dataout : STD_LOGIC; + SIGNAL wire_niiOl1ll_dataout : STD_LOGIC; + SIGNAL wire_niiOl1lO_dataout : STD_LOGIC; + SIGNAL wire_niiOl1O_dataout : STD_LOGIC; + SIGNAL wire_niiOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_niiOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_niiOl1OO_dataout : STD_LOGIC; + SIGNAL wire_niiOli0i_dataout : STD_LOGIC; + SIGNAL wire_niiOli0l_dataout : STD_LOGIC; + SIGNAL wire_niiOli0O_dataout : STD_LOGIC; + SIGNAL wire_niiOli1i_dataout : STD_LOGIC; + SIGNAL wire_niiOli1l_dataout : STD_LOGIC; + SIGNAL wire_niiOli1O_dataout : STD_LOGIC; + SIGNAL wire_niiOlii_dataout : STD_LOGIC; + SIGNAL wire_niiOliii_dataout : STD_LOGIC; + SIGNAL wire_niiOliil_dataout : STD_LOGIC; + SIGNAL wire_niiOliiO_dataout : STD_LOGIC; + SIGNAL wire_niiOlil_dataout : STD_LOGIC; + SIGNAL wire_niiOlili_dataout : STD_LOGIC; + SIGNAL wire_niiOlill_dataout : STD_LOGIC; + SIGNAL wire_niiOlilO_dataout : STD_LOGIC; + SIGNAL wire_niiOliO_dataout : STD_LOGIC; + SIGNAL wire_niiOliOi_dataout : STD_LOGIC; + SIGNAL wire_niiOliOl_dataout : STD_LOGIC; + SIGNAL wire_niiOliOO_dataout : STD_LOGIC; + SIGNAL wire_niiOll0i_dataout : STD_LOGIC; + SIGNAL wire_niiOll0l_dataout : STD_LOGIC; + SIGNAL wire_niiOll0O_dataout : STD_LOGIC; + SIGNAL wire_niiOll1i_dataout : STD_LOGIC; + SIGNAL wire_niiOll1l_dataout : STD_LOGIC; + SIGNAL wire_niiOll1O_dataout : STD_LOGIC; + SIGNAL wire_niiOlli_dataout : STD_LOGIC; + SIGNAL wire_niiOllii_dataout : STD_LOGIC; + SIGNAL wire_niiOllil_dataout : STD_LOGIC; + SIGNAL wire_niiOlliO_dataout : STD_LOGIC; + SIGNAL wire_niiOlll_dataout : STD_LOGIC; + SIGNAL wire_niiOllli_dataout : STD_LOGIC; + SIGNAL wire_niiOllll_dataout : STD_LOGIC; + SIGNAL wire_niiOlllO_dataout : STD_LOGIC; + SIGNAL wire_niiOllO_dataout : STD_LOGIC; + SIGNAL wire_niiOllOi_dataout : STD_LOGIC; + SIGNAL wire_niiOllOl_dataout : STD_LOGIC; + SIGNAL wire_niiOllOO_dataout : STD_LOGIC; + SIGNAL wire_niiOlO0i_dataout : STD_LOGIC; + SIGNAL wire_niiOlO0l_dataout : STD_LOGIC; + SIGNAL wire_niiOlO0O_dataout : STD_LOGIC; + SIGNAL wire_niiOlO1i_dataout : STD_LOGIC; + SIGNAL wire_niiOlO1l_dataout : STD_LOGIC; + SIGNAL wire_niiOlO1O_dataout : STD_LOGIC; + SIGNAL wire_niiOlOi_dataout : STD_LOGIC; + SIGNAL wire_niiOlOii_dataout : STD_LOGIC; + SIGNAL wire_niiOlOil_dataout : STD_LOGIC; + SIGNAL wire_niiOlOiO_dataout : STD_LOGIC; + SIGNAL wire_niiOlOl_dataout : STD_LOGIC; + SIGNAL wire_niiOlOli_dataout : STD_LOGIC; + SIGNAL wire_niiOlOll_dataout : STD_LOGIC; + SIGNAL wire_niiOlOlO_dataout : STD_LOGIC; + SIGNAL wire_niiOlOO_dataout : STD_LOGIC; + SIGNAL wire_niiOlOOi_dataout : STD_LOGIC; + SIGNAL wire_niiOlOOl_dataout : STD_LOGIC; + SIGNAL wire_niiOlOOO_dataout : STD_LOGIC; + SIGNAL wire_niiOO00i_dataout : STD_LOGIC; + SIGNAL wire_niiOO00l_dataout : STD_LOGIC; + SIGNAL wire_niiOO00O_dataout : STD_LOGIC; + SIGNAL wire_niiOO01i_dataout : STD_LOGIC; + SIGNAL wire_niiOO01l_dataout : STD_LOGIC; + SIGNAL wire_niiOO01O_dataout : STD_LOGIC; + SIGNAL wire_niiOO0i_dataout : STD_LOGIC; + SIGNAL wire_niiOO0ii_dataout : STD_LOGIC; + SIGNAL wire_niiOO0il_dataout : STD_LOGIC; + SIGNAL wire_niiOO0iO_dataout : STD_LOGIC; + SIGNAL wire_niiOO0l_dataout : STD_LOGIC; + SIGNAL wire_niiOO0li_dataout : STD_LOGIC; + SIGNAL wire_niiOO0ll_dataout : STD_LOGIC; + SIGNAL wire_niiOO0lO_dataout : STD_LOGIC; + SIGNAL wire_niiOO0O_dataout : STD_LOGIC; + SIGNAL wire_niiOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niiOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niiOO0OO_dataout : STD_LOGIC; + SIGNAL wire_niiOO10i_dataout : STD_LOGIC; + SIGNAL wire_niiOO10l_dataout : STD_LOGIC; + SIGNAL wire_niiOO10O_dataout : STD_LOGIC; + SIGNAL wire_niiOO11i_dataout : STD_LOGIC; + SIGNAL wire_niiOO11l_dataout : STD_LOGIC; + SIGNAL wire_niiOO11O_dataout : STD_LOGIC; + SIGNAL wire_niiOO1i_dataout : STD_LOGIC; + SIGNAL wire_niiOO1ii_dataout : STD_LOGIC; + SIGNAL wire_niiOO1il_dataout : STD_LOGIC; + SIGNAL wire_niiOO1iO_dataout : STD_LOGIC; + SIGNAL wire_niiOO1l_dataout : STD_LOGIC; + SIGNAL wire_niiOO1li_dataout : STD_LOGIC; + SIGNAL wire_niiOO1ll_dataout : STD_LOGIC; + SIGNAL wire_niiOO1lO_dataout : STD_LOGIC; + SIGNAL wire_niiOO1O_dataout : STD_LOGIC; + SIGNAL wire_niiOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niiOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niiOO1OO_dataout : STD_LOGIC; + SIGNAL wire_niiOOi0i_dataout : STD_LOGIC; + SIGNAL wire_niiOOi0l_dataout : STD_LOGIC; + SIGNAL wire_niiOOi0O_dataout : STD_LOGIC; + SIGNAL wire_niiOOi1i_dataout : STD_LOGIC; + SIGNAL wire_niiOOi1l_dataout : STD_LOGIC; + SIGNAL wire_niiOOi1O_dataout : STD_LOGIC; + SIGNAL wire_niiOOii_dataout : STD_LOGIC; + SIGNAL wire_niiOOiii_dataout : STD_LOGIC; + SIGNAL wire_niiOOiil_dataout : STD_LOGIC; + SIGNAL wire_niiOOiiO_dataout : STD_LOGIC; + SIGNAL wire_niiOOil_dataout : STD_LOGIC; + SIGNAL wire_niiOOili_dataout : STD_LOGIC; + SIGNAL wire_niiOOill_dataout : STD_LOGIC; + SIGNAL wire_niiOOilO_dataout : STD_LOGIC; + SIGNAL wire_niiOOiO_dataout : STD_LOGIC; + SIGNAL wire_niiOOiOi_dataout : STD_LOGIC; + SIGNAL wire_niiOOiOl_dataout : STD_LOGIC; + SIGNAL wire_niiOOiOO_dataout : STD_LOGIC; + SIGNAL wire_niiOOl0i_dataout : STD_LOGIC; + SIGNAL wire_niiOOl0l_dataout : STD_LOGIC; + SIGNAL wire_niiOOl0O_dataout : STD_LOGIC; + SIGNAL wire_niiOOl1i_dataout : STD_LOGIC; + SIGNAL wire_niiOOl1l_dataout : STD_LOGIC; + SIGNAL wire_niiOOl1O_dataout : STD_LOGIC; + SIGNAL wire_niiOOli_dataout : STD_LOGIC; + SIGNAL wire_niiOOlii_dataout : STD_LOGIC; + SIGNAL wire_niiOOlil_dataout : STD_LOGIC; + SIGNAL wire_niiOOliO_dataout : STD_LOGIC; + SIGNAL wire_niiOOll_dataout : STD_LOGIC; + SIGNAL wire_niiOOlli_dataout : STD_LOGIC; + SIGNAL wire_niiOOlll_dataout : STD_LOGIC; + SIGNAL wire_niiOOllO_dataout : STD_LOGIC; + SIGNAL wire_niiOOlO_dataout : STD_LOGIC; + SIGNAL wire_niiOOlOi_dataout : STD_LOGIC; + SIGNAL wire_niiOOlOl_dataout : STD_LOGIC; + SIGNAL wire_niiOOlOO_dataout : STD_LOGIC; + SIGNAL wire_niiOOO0i_dataout : STD_LOGIC; + SIGNAL wire_niiOOO0l_dataout : STD_LOGIC; + SIGNAL wire_niiOOO0O_dataout : STD_LOGIC; + SIGNAL wire_niiOOO1i_dataout : STD_LOGIC; + SIGNAL wire_niiOOO1l_dataout : STD_LOGIC; + SIGNAL wire_niiOOO1O_dataout : STD_LOGIC; + SIGNAL wire_niiOOOi_dataout : STD_LOGIC; + SIGNAL wire_niiOOOii_dataout : STD_LOGIC; + SIGNAL wire_niiOOOil_dataout : STD_LOGIC; + SIGNAL wire_niiOOOiO_dataout : STD_LOGIC; + SIGNAL wire_niiOOOl_dataout : STD_LOGIC; + SIGNAL wire_niiOOOli_dataout : STD_LOGIC; + SIGNAL wire_niiOOOll_dataout : STD_LOGIC; + SIGNAL wire_niiOOOlO_dataout : STD_LOGIC; + SIGNAL wire_niiOOOO_dataout : STD_LOGIC; + SIGNAL wire_niiOOOOi_dataout : STD_LOGIC; + SIGNAL wire_niiOOOOl_dataout : STD_LOGIC; + SIGNAL wire_niiOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nil0000i_dataout : STD_LOGIC; + SIGNAL wire_nil0000l_dataout : STD_LOGIC; + SIGNAL wire_nil0000O_dataout : STD_LOGIC; + SIGNAL wire_nil0001i_dataout : STD_LOGIC; + SIGNAL wire_nil0001l_dataout : STD_LOGIC; + SIGNAL wire_nil0001O_dataout : STD_LOGIC; + SIGNAL wire_nil000i_dataout : STD_LOGIC; + SIGNAL wire_nil000ii_dataout : STD_LOGIC; + SIGNAL wire_nil000il_dataout : STD_LOGIC; + SIGNAL wire_nil000iO_dataout : STD_LOGIC; + SIGNAL wire_nil000l_dataout : STD_LOGIC; + SIGNAL wire_nil000li_dataout : STD_LOGIC; + SIGNAL wire_nil000ll_dataout : STD_LOGIC; + SIGNAL wire_nil000lO_dataout : STD_LOGIC; + SIGNAL wire_nil000O_dataout : STD_LOGIC; + SIGNAL wire_nil000Oi_dataout : STD_LOGIC; + SIGNAL wire_nil000Ol_dataout : STD_LOGIC; + SIGNAL wire_nil000OO_dataout : STD_LOGIC; + SIGNAL wire_nil0010i_dataout : STD_LOGIC; + SIGNAL wire_nil0010l_dataout : STD_LOGIC; + SIGNAL wire_nil0010O_dataout : STD_LOGIC; + SIGNAL wire_nil0011i_dataout : STD_LOGIC; + SIGNAL wire_nil0011l_dataout : STD_LOGIC; + SIGNAL wire_nil0011O_dataout : STD_LOGIC; + SIGNAL wire_nil001i_dataout : STD_LOGIC; + SIGNAL wire_nil001ii_dataout : STD_LOGIC; + SIGNAL wire_nil001il_dataout : STD_LOGIC; + SIGNAL wire_nil001iO_dataout : STD_LOGIC; + SIGNAL wire_nil001l_dataout : STD_LOGIC; + SIGNAL wire_nil001li_dataout : STD_LOGIC; + SIGNAL wire_nil001ll_dataout : STD_LOGIC; + SIGNAL wire_nil001lO_dataout : STD_LOGIC; + SIGNAL wire_nil001O_dataout : STD_LOGIC; + SIGNAL wire_nil001Oi_dataout : STD_LOGIC; + SIGNAL wire_nil001Ol_dataout : STD_LOGIC; + SIGNAL wire_nil001OO_dataout : STD_LOGIC; + SIGNAL wire_nil00i0i_dataout : STD_LOGIC; + SIGNAL wire_nil00i0l_dataout : STD_LOGIC; + SIGNAL wire_nil00i0O_dataout : STD_LOGIC; + SIGNAL wire_nil00i1i_dataout : STD_LOGIC; + SIGNAL wire_nil00i1l_dataout : STD_LOGIC; + SIGNAL wire_nil00i1O_dataout : STD_LOGIC; + SIGNAL wire_nil00ii_dataout : STD_LOGIC; + SIGNAL wire_nil00iii_dataout : STD_LOGIC; + SIGNAL wire_nil00iil_dataout : STD_LOGIC; + SIGNAL wire_nil00iiO_dataout : STD_LOGIC; + SIGNAL wire_nil00il_dataout : STD_LOGIC; + SIGNAL wire_nil00ili_dataout : STD_LOGIC; + SIGNAL wire_nil00ill_dataout : STD_LOGIC; + SIGNAL wire_nil00ilO_dataout : STD_LOGIC; + SIGNAL wire_nil00iO_dataout : STD_LOGIC; + SIGNAL wire_nil00iOi_dataout : STD_LOGIC; + SIGNAL wire_nil00iOl_dataout : STD_LOGIC; + SIGNAL wire_nil00iOO_dataout : STD_LOGIC; + SIGNAL wire_nil00l0i_dataout : STD_LOGIC; + SIGNAL wire_nil00l0l_dataout : STD_LOGIC; + SIGNAL wire_nil00l0O_dataout : STD_LOGIC; + SIGNAL wire_nil00l1i_dataout : STD_LOGIC; + SIGNAL wire_nil00l1l_dataout : STD_LOGIC; + SIGNAL wire_nil00l1O_dataout : STD_LOGIC; + SIGNAL wire_nil00li_dataout : STD_LOGIC; + SIGNAL wire_nil00lii_dataout : STD_LOGIC; + SIGNAL wire_nil00lil_dataout : STD_LOGIC; + SIGNAL wire_nil00liO_dataout : STD_LOGIC; + SIGNAL wire_nil00ll_dataout : STD_LOGIC; + SIGNAL wire_nil00lli_dataout : STD_LOGIC; + SIGNAL wire_nil00lll_dataout : STD_LOGIC; + SIGNAL wire_nil00llO_dataout : STD_LOGIC; + SIGNAL wire_nil00lO_dataout : STD_LOGIC; + SIGNAL wire_nil00lOi_dataout : STD_LOGIC; + SIGNAL wire_nil00lOl_dataout : STD_LOGIC; + SIGNAL wire_nil00lOO_dataout : STD_LOGIC; + SIGNAL wire_nil00O0i_dataout : STD_LOGIC; + SIGNAL wire_nil00O0l_dataout : STD_LOGIC; + SIGNAL wire_nil00O0O_dataout : STD_LOGIC; + SIGNAL wire_nil00O1i_dataout : STD_LOGIC; + SIGNAL wire_nil00O1l_dataout : STD_LOGIC; + SIGNAL wire_nil00O1O_dataout : STD_LOGIC; + SIGNAL wire_nil00Oi_dataout : STD_LOGIC; + SIGNAL wire_nil00Oii_dataout : STD_LOGIC; + SIGNAL wire_nil00Oil_dataout : STD_LOGIC; + SIGNAL wire_nil00OiO_dataout : STD_LOGIC; + SIGNAL wire_nil00Ol_dataout : STD_LOGIC; + SIGNAL wire_nil00Oli_dataout : STD_LOGIC; + SIGNAL wire_nil00Oll_dataout : STD_LOGIC; + SIGNAL wire_nil00OlO_dataout : STD_LOGIC; + SIGNAL wire_nil00OO_dataout : STD_LOGIC; + SIGNAL wire_nil00OOi_dataout : STD_LOGIC; + SIGNAL wire_nil00OOl_dataout : STD_LOGIC; + SIGNAL wire_nil00OOO_dataout : STD_LOGIC; + SIGNAL wire_nil0100i_dataout : STD_LOGIC; + SIGNAL wire_nil0100l_dataout : STD_LOGIC; + SIGNAL wire_nil0100O_dataout : STD_LOGIC; + SIGNAL wire_nil0101i_dataout : STD_LOGIC; + SIGNAL wire_nil0101l_dataout : STD_LOGIC; + SIGNAL wire_nil0101O_dataout : STD_LOGIC; + SIGNAL wire_nil010i_dataout : STD_LOGIC; + SIGNAL wire_nil010ii_dataout : STD_LOGIC; + SIGNAL wire_nil010il_dataout : STD_LOGIC; + SIGNAL wire_nil010iO_dataout : STD_LOGIC; + SIGNAL wire_nil010l_dataout : STD_LOGIC; + SIGNAL wire_nil010li_dataout : STD_LOGIC; + SIGNAL wire_nil010ll_dataout : STD_LOGIC; + SIGNAL wire_nil010lO_dataout : STD_LOGIC; + SIGNAL wire_nil010O_dataout : STD_LOGIC; + SIGNAL wire_nil010Oi_dataout : STD_LOGIC; + SIGNAL wire_nil010Ol_dataout : STD_LOGIC; + SIGNAL wire_nil010OO_dataout : STD_LOGIC; + SIGNAL wire_nil0110i_dataout : STD_LOGIC; + SIGNAL wire_nil0110l_dataout : STD_LOGIC; + SIGNAL wire_nil0110O_dataout : STD_LOGIC; + SIGNAL wire_nil0111i_dataout : STD_LOGIC; + SIGNAL wire_nil0111l_dataout : STD_LOGIC; + SIGNAL wire_nil0111O_dataout : STD_LOGIC; + SIGNAL wire_nil011i_dataout : STD_LOGIC; + SIGNAL wire_nil011ii_dataout : STD_LOGIC; + SIGNAL wire_nil011il_dataout : STD_LOGIC; + SIGNAL wire_nil011iO_dataout : STD_LOGIC; + SIGNAL wire_nil011l_dataout : STD_LOGIC; + SIGNAL wire_nil011li_dataout : STD_LOGIC; + SIGNAL wire_nil011ll_dataout : STD_LOGIC; + SIGNAL wire_nil011lO_dataout : STD_LOGIC; + SIGNAL wire_nil011O_dataout : STD_LOGIC; + SIGNAL wire_nil011Oi_dataout : STD_LOGIC; + SIGNAL wire_nil011Ol_dataout : STD_LOGIC; + SIGNAL wire_nil011OO_dataout : STD_LOGIC; + SIGNAL wire_nil01i0i_dataout : STD_LOGIC; + SIGNAL wire_nil01i0l_dataout : STD_LOGIC; + SIGNAL wire_nil01i0O_dataout : STD_LOGIC; + SIGNAL wire_nil01i1i_dataout : STD_LOGIC; + SIGNAL wire_nil01i1l_dataout : STD_LOGIC; + SIGNAL wire_nil01i1O_dataout : STD_LOGIC; + SIGNAL wire_nil01ii_dataout : STD_LOGIC; + SIGNAL wire_nil01iii_dataout : STD_LOGIC; + SIGNAL wire_nil01iil_dataout : STD_LOGIC; + SIGNAL wire_nil01iiO_dataout : STD_LOGIC; + SIGNAL wire_nil01il_dataout : STD_LOGIC; + SIGNAL wire_nil01ili_dataout : STD_LOGIC; + SIGNAL wire_nil01ill_dataout : STD_LOGIC; + SIGNAL wire_nil01ilO_dataout : STD_LOGIC; + SIGNAL wire_nil01iO_dataout : STD_LOGIC; + SIGNAL wire_nil01iOi_dataout : STD_LOGIC; + SIGNAL wire_nil01iOl_dataout : STD_LOGIC; + SIGNAL wire_nil01iOO_dataout : STD_LOGIC; + SIGNAL wire_nil01l0i_dataout : STD_LOGIC; + SIGNAL wire_nil01l0l_dataout : STD_LOGIC; + SIGNAL wire_nil01l0O_dataout : STD_LOGIC; + SIGNAL wire_nil01l1i_dataout : STD_LOGIC; + SIGNAL wire_nil01l1l_dataout : STD_LOGIC; + SIGNAL wire_nil01l1O_dataout : STD_LOGIC; + SIGNAL wire_nil01li_dataout : STD_LOGIC; + SIGNAL wire_nil01lii_dataout : STD_LOGIC; + SIGNAL wire_nil01lil_dataout : STD_LOGIC; + SIGNAL wire_nil01liO_dataout : STD_LOGIC; + SIGNAL wire_nil01ll_dataout : STD_LOGIC; + SIGNAL wire_nil01lli_dataout : STD_LOGIC; + SIGNAL wire_nil01lll_dataout : STD_LOGIC; + SIGNAL wire_nil01llO_dataout : STD_LOGIC; + SIGNAL wire_nil01lO_dataout : STD_LOGIC; + SIGNAL wire_nil01lOi_dataout : STD_LOGIC; + SIGNAL wire_nil01lOl_dataout : STD_LOGIC; + SIGNAL wire_nil01lOO_dataout : STD_LOGIC; + SIGNAL wire_nil01O0i_dataout : STD_LOGIC; + SIGNAL wire_nil01O0l_dataout : STD_LOGIC; + SIGNAL wire_nil01O0O_dataout : STD_LOGIC; + SIGNAL wire_nil01O1i_dataout : STD_LOGIC; + SIGNAL wire_nil01O1l_dataout : STD_LOGIC; + SIGNAL wire_nil01O1O_dataout : STD_LOGIC; + SIGNAL wire_nil01Oi_dataout : STD_LOGIC; + SIGNAL wire_nil01Oii_dataout : STD_LOGIC; + SIGNAL wire_nil01Oil_dataout : STD_LOGIC; + SIGNAL wire_nil01OiO_dataout : STD_LOGIC; + SIGNAL wire_nil01Ol_dataout : STD_LOGIC; + SIGNAL wire_nil01Oli_dataout : STD_LOGIC; + SIGNAL wire_nil01Oll_dataout : STD_LOGIC; + SIGNAL wire_nil01OlO_dataout : STD_LOGIC; + SIGNAL wire_nil01OO_dataout : STD_LOGIC; + SIGNAL wire_nil01OOi_dataout : STD_LOGIC; + SIGNAL wire_nil01OOl_dataout : STD_LOGIC; + SIGNAL wire_nil01OOO_dataout : STD_LOGIC; + SIGNAL wire_nil0i00i_dataout : STD_LOGIC; + SIGNAL wire_nil0i00l_dataout : STD_LOGIC; + SIGNAL wire_nil0i00O_dataout : STD_LOGIC; + SIGNAL wire_nil0i01i_dataout : STD_LOGIC; + SIGNAL wire_nil0i01l_dataout : STD_LOGIC; + SIGNAL wire_nil0i01O_dataout : STD_LOGIC; + SIGNAL wire_nil0i0i_dataout : STD_LOGIC; + SIGNAL wire_nil0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nil0i0il_dataout : STD_LOGIC; + SIGNAL wire_nil0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nil0i0l_dataout : STD_LOGIC; + SIGNAL wire_nil0i0li_dataout : STD_LOGIC; + SIGNAL wire_nil0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nil0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nil0i0O_dataout : STD_LOGIC; + SIGNAL wire_nil0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nil0i10i_dataout : STD_LOGIC; + SIGNAL wire_nil0i10l_dataout : STD_LOGIC; + SIGNAL wire_nil0i10O_dataout : STD_LOGIC; + SIGNAL wire_nil0i11i_dataout : STD_LOGIC; + SIGNAL wire_nil0i11l_dataout : STD_LOGIC; + SIGNAL wire_nil0i11O_dataout : STD_LOGIC; + SIGNAL wire_nil0i1i_dataout : STD_LOGIC; + SIGNAL wire_nil0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nil0i1il_dataout : STD_LOGIC; + SIGNAL wire_nil0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nil0i1l_dataout : STD_LOGIC; + SIGNAL wire_nil0i1li_dataout : STD_LOGIC; + SIGNAL wire_nil0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nil0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nil0i1O_dataout : STD_LOGIC; + SIGNAL wire_nil0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nil0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nil0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nil0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nil0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nil0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nil0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nil0iii_dataout : STD_LOGIC; + SIGNAL wire_nil0iiii_dataout : STD_LOGIC; + SIGNAL wire_nil0iiil_dataout : STD_LOGIC; + SIGNAL wire_nil0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nil0iil_dataout : STD_LOGIC; + SIGNAL wire_nil0iili_dataout : STD_LOGIC; + SIGNAL wire_nil0iill_dataout : STD_LOGIC; + SIGNAL wire_nil0iilO_dataout : STD_LOGIC; + SIGNAL wire_nil0iiO_dataout : STD_LOGIC; + SIGNAL wire_nil0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nil0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nil0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nil0il0i_dataout : STD_LOGIC; + SIGNAL wire_nil0il0l_dataout : STD_LOGIC; + SIGNAL wire_nil0il0O_dataout : STD_LOGIC; + SIGNAL wire_nil0il1i_dataout : STD_LOGIC; + SIGNAL wire_nil0il1l_dataout : STD_LOGIC; + SIGNAL wire_nil0il1O_dataout : STD_LOGIC; + SIGNAL wire_nil0ili_dataout : STD_LOGIC; + SIGNAL wire_nil0ilii_dataout : STD_LOGIC; + SIGNAL wire_nil0ilil_dataout : STD_LOGIC; + SIGNAL wire_nil0iliO_dataout : STD_LOGIC; + SIGNAL wire_nil0ill_dataout : STD_LOGIC; + SIGNAL wire_nil0illi_dataout : STD_LOGIC; + SIGNAL wire_nil0illl_dataout : STD_LOGIC; + SIGNAL wire_nil0illO_dataout : STD_LOGIC; + SIGNAL wire_nil0ilO_dataout : STD_LOGIC; + SIGNAL wire_nil0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nil0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nil0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nil0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nil0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nil0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nil0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nil0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nil0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nil0iOi_dataout : STD_LOGIC; + SIGNAL wire_nil0iOii_dataout : STD_LOGIC; + SIGNAL wire_nil0iOil_dataout : STD_LOGIC; + SIGNAL wire_nil0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nil0iOl_dataout : STD_LOGIC; + SIGNAL wire_nil0iOli_dataout : STD_LOGIC; + SIGNAL wire_nil0iOll_dataout : STD_LOGIC; + SIGNAL wire_nil0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nil0iOO_dataout : STD_LOGIC; + SIGNAL wire_nil0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nil0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nil0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nil0l00i_dataout : STD_LOGIC; + SIGNAL wire_nil0l00l_dataout : STD_LOGIC; + SIGNAL wire_nil0l00O_dataout : STD_LOGIC; + SIGNAL wire_nil0l01i_dataout : STD_LOGIC; + SIGNAL wire_nil0l01l_dataout : STD_LOGIC; + SIGNAL wire_nil0l01O_dataout : STD_LOGIC; + SIGNAL wire_nil0l0i_dataout : STD_LOGIC; + SIGNAL wire_nil0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nil0l0il_dataout : STD_LOGIC; + SIGNAL wire_nil0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nil0l0l_dataout : STD_LOGIC; + SIGNAL wire_nil0l0li_dataout : STD_LOGIC; + SIGNAL wire_nil0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nil0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nil0l0O_dataout : STD_LOGIC; + SIGNAL wire_nil0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nil0l10i_dataout : STD_LOGIC; + SIGNAL wire_nil0l10l_dataout : STD_LOGIC; + SIGNAL wire_nil0l10O_dataout : STD_LOGIC; + SIGNAL wire_nil0l11i_dataout : STD_LOGIC; + SIGNAL wire_nil0l11l_dataout : STD_LOGIC; + SIGNAL wire_nil0l11O_dataout : STD_LOGIC; + SIGNAL wire_nil0l1i_dataout : STD_LOGIC; + SIGNAL wire_nil0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nil0l1il_dataout : STD_LOGIC; + SIGNAL wire_nil0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nil0l1l_dataout : STD_LOGIC; + SIGNAL wire_nil0l1li_dataout : STD_LOGIC; + SIGNAL wire_nil0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nil0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nil0l1O_dataout : STD_LOGIC; + SIGNAL wire_nil0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nil0li0i_dataout : STD_LOGIC; + SIGNAL wire_nil0li0l_dataout : STD_LOGIC; + SIGNAL wire_nil0li0O_dataout : STD_LOGIC; + SIGNAL wire_nil0li1i_dataout : STD_LOGIC; + SIGNAL wire_nil0li1l_dataout : STD_LOGIC; + SIGNAL wire_nil0li1O_dataout : STD_LOGIC; + SIGNAL wire_nil0lii_dataout : STD_LOGIC; + SIGNAL wire_nil0liii_dataout : STD_LOGIC; + SIGNAL wire_nil0liil_dataout : STD_LOGIC; + SIGNAL wire_nil0liiO_dataout : STD_LOGIC; + SIGNAL wire_nil0lil_dataout : STD_LOGIC; + SIGNAL wire_nil0lili_dataout : STD_LOGIC; + SIGNAL wire_nil0lill_dataout : STD_LOGIC; + SIGNAL wire_nil0lilO_dataout : STD_LOGIC; + SIGNAL wire_nil0liO_dataout : STD_LOGIC; + SIGNAL wire_nil0liOi_dataout : STD_LOGIC; + SIGNAL wire_nil0liOl_dataout : STD_LOGIC; + SIGNAL wire_nil0liOO_dataout : STD_LOGIC; + SIGNAL wire_nil0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nil0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nil0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nil0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nil0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nil0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nil0lli_dataout : STD_LOGIC; + SIGNAL wire_nil0llii_dataout : STD_LOGIC; + SIGNAL wire_nil0llil_dataout : STD_LOGIC; + SIGNAL wire_nil0lliO_dataout : STD_LOGIC; + SIGNAL wire_nil0lll_dataout : STD_LOGIC; + SIGNAL wire_nil0llli_dataout : STD_LOGIC; + SIGNAL wire_nil0llll_dataout : STD_LOGIC; + SIGNAL wire_nil0lllO_dataout : STD_LOGIC; + SIGNAL wire_nil0llO_dataout : STD_LOGIC; + SIGNAL wire_nil0llOi_dataout : STD_LOGIC; + SIGNAL wire_nil0llOl_dataout : STD_LOGIC; + SIGNAL wire_nil0llOO_dataout : STD_LOGIC; + SIGNAL wire_nil0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nil0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nil0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nil0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nil0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nil0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nil0lOi_dataout : STD_LOGIC; + SIGNAL wire_nil0lOii_dataout : STD_LOGIC; + SIGNAL wire_nil0lOil_dataout : STD_LOGIC; + SIGNAL wire_nil0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nil0lOl_dataout : STD_LOGIC; + SIGNAL wire_nil0lOli_dataout : STD_LOGIC; + SIGNAL wire_nil0lOll_dataout : STD_LOGIC; + SIGNAL wire_nil0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nil0lOO_dataout : STD_LOGIC; + SIGNAL wire_nil0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nil0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nil0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nil0O00i_dataout : STD_LOGIC; + SIGNAL wire_nil0O00l_dataout : STD_LOGIC; + SIGNAL wire_nil0O00O_dataout : STD_LOGIC; + SIGNAL wire_nil0O01i_dataout : STD_LOGIC; + SIGNAL wire_nil0O01l_dataout : STD_LOGIC; + SIGNAL wire_nil0O01O_dataout : STD_LOGIC; + SIGNAL wire_nil0O0i_dataout : STD_LOGIC; + SIGNAL wire_nil0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nil0O0il_dataout : STD_LOGIC; + SIGNAL wire_nil0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nil0O0l_dataout : STD_LOGIC; + SIGNAL wire_nil0O0li_dataout : STD_LOGIC; + SIGNAL wire_nil0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nil0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nil0O0O_dataout : STD_LOGIC; + SIGNAL wire_nil0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0O10i_dataout : STD_LOGIC; + SIGNAL wire_nil0O10l_dataout : STD_LOGIC; + SIGNAL wire_nil0O10O_dataout : STD_LOGIC; + SIGNAL wire_nil0O11i_dataout : STD_LOGIC; + SIGNAL wire_nil0O11l_dataout : STD_LOGIC; + SIGNAL wire_nil0O11O_dataout : STD_LOGIC; + SIGNAL wire_nil0O1i_dataout : STD_LOGIC; + SIGNAL wire_nil0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nil0O1il_dataout : STD_LOGIC; + SIGNAL wire_nil0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nil0O1l_dataout : STD_LOGIC; + SIGNAL wire_nil0O1li_dataout : STD_LOGIC; + SIGNAL wire_nil0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nil0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nil0O1O_dataout : STD_LOGIC; + SIGNAL wire_nil0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nil0Oii_dataout : STD_LOGIC; + SIGNAL wire_nil0Oil_dataout : STD_LOGIC; + SIGNAL wire_nil0OiO_dataout : STD_LOGIC; + SIGNAL wire_nil0Oli_dataout : STD_LOGIC; + SIGNAL wire_nil0Oll_dataout : STD_LOGIC; + SIGNAL wire_nil0OlO_dataout : STD_LOGIC; + SIGNAL wire_nil0OOi_dataout : STD_LOGIC; + SIGNAL wire_nil0OOl_dataout : STD_LOGIC; + SIGNAL wire_nil0OOO_dataout : STD_LOGIC; + SIGNAL wire_nil1000i_dataout : STD_LOGIC; + SIGNAL wire_nil1000l_dataout : STD_LOGIC; + SIGNAL wire_nil1000O_dataout : STD_LOGIC; + SIGNAL wire_nil1001i_dataout : STD_LOGIC; + SIGNAL wire_nil1001l_dataout : STD_LOGIC; + SIGNAL wire_nil1001O_dataout : STD_LOGIC; + SIGNAL wire_nil100i_dataout : STD_LOGIC; + SIGNAL wire_nil100ii_dataout : STD_LOGIC; + SIGNAL wire_nil100il_dataout : STD_LOGIC; + SIGNAL wire_nil100iO_dataout : STD_LOGIC; + SIGNAL wire_nil100l_dataout : STD_LOGIC; + SIGNAL wire_nil100O_dataout : STD_LOGIC; + SIGNAL wire_nil100Oi_dataout : STD_LOGIC; + SIGNAL wire_nil100Ol_dataout : STD_LOGIC; + SIGNAL wire_nil100OO_dataout : STD_LOGIC; + SIGNAL wire_nil1010i_dataout : STD_LOGIC; + SIGNAL wire_nil1010l_dataout : STD_LOGIC; + SIGNAL wire_nil1010O_dataout : STD_LOGIC; + SIGNAL wire_nil1011i_dataout : STD_LOGIC; + SIGNAL wire_nil1011l_dataout : STD_LOGIC; + SIGNAL wire_nil1011O_dataout : STD_LOGIC; + SIGNAL wire_nil101i_dataout : STD_LOGIC; + SIGNAL wire_nil101ii_dataout : STD_LOGIC; + SIGNAL wire_nil101il_dataout : STD_LOGIC; + SIGNAL wire_nil101iO_dataout : STD_LOGIC; + SIGNAL wire_nil101l_dataout : STD_LOGIC; + SIGNAL wire_nil101li_dataout : STD_LOGIC; + SIGNAL wire_nil101ll_dataout : STD_LOGIC; + SIGNAL wire_nil101lO_dataout : STD_LOGIC; + SIGNAL wire_nil101O_dataout : STD_LOGIC; + SIGNAL wire_nil101Oi_dataout : STD_LOGIC; + SIGNAL wire_nil101Ol_dataout : STD_LOGIC; + SIGNAL wire_nil101OO_dataout : STD_LOGIC; + SIGNAL wire_nil10i0i_dataout : STD_LOGIC; + SIGNAL wire_nil10i0l_dataout : STD_LOGIC; + SIGNAL wire_nil10i0O_dataout : STD_LOGIC; + SIGNAL wire_nil10i1i_dataout : STD_LOGIC; + SIGNAL wire_nil10i1l_dataout : STD_LOGIC; + SIGNAL wire_nil10i1O_dataout : STD_LOGIC; + SIGNAL wire_nil10ii_dataout : STD_LOGIC; + SIGNAL wire_nil10iii_dataout : STD_LOGIC; + SIGNAL wire_nil10iil_dataout : STD_LOGIC; + SIGNAL wire_nil10iiO_dataout : STD_LOGIC; + SIGNAL wire_nil10il_dataout : STD_LOGIC; + SIGNAL wire_nil10ili_dataout : STD_LOGIC; + SIGNAL wire_nil10ill_dataout : STD_LOGIC; + SIGNAL wire_nil10ilO_dataout : STD_LOGIC; + SIGNAL wire_nil10iO_dataout : STD_LOGIC; + SIGNAL wire_nil10iOi_dataout : STD_LOGIC; + SIGNAL wire_nil10iOl_dataout : STD_LOGIC; + SIGNAL wire_nil10iOO_dataout : STD_LOGIC; + SIGNAL wire_nil10l0i_dataout : STD_LOGIC; + SIGNAL wire_nil10l0l_dataout : STD_LOGIC; + SIGNAL wire_nil10l0O_dataout : STD_LOGIC; + SIGNAL wire_nil10l1i_dataout : STD_LOGIC; + SIGNAL wire_nil10l1l_dataout : STD_LOGIC; + SIGNAL wire_nil10l1O_dataout : STD_LOGIC; + SIGNAL wire_nil10li_dataout : STD_LOGIC; + SIGNAL wire_nil10lii_dataout : STD_LOGIC; + SIGNAL wire_nil10lil_dataout : STD_LOGIC; + SIGNAL wire_nil10ll_dataout : STD_LOGIC; + SIGNAL wire_nil10lO_dataout : STD_LOGIC; + SIGNAL wire_nil10Oi_dataout : STD_LOGIC; + SIGNAL wire_nil10Ol_dataout : STD_LOGIC; + SIGNAL wire_nil10OO_dataout : STD_LOGIC; + SIGNAL wire_nil1101i_dataout : STD_LOGIC; + SIGNAL wire_nil1101l_dataout : STD_LOGIC; + SIGNAL wire_nil1101O_dataout : STD_LOGIC; + SIGNAL wire_nil110i_dataout : STD_LOGIC; + SIGNAL wire_nil110l_dataout : STD_LOGIC; + SIGNAL wire_nil110O_dataout : STD_LOGIC; + SIGNAL wire_nil1110i_dataout : STD_LOGIC; + SIGNAL wire_nil1110l_dataout : STD_LOGIC; + SIGNAL wire_nil1110O_dataout : STD_LOGIC; + SIGNAL wire_nil1111i_dataout : STD_LOGIC; + SIGNAL wire_nil1111l_dataout : STD_LOGIC; + SIGNAL wire_nil1111O_dataout : STD_LOGIC; + SIGNAL wire_nil111i_dataout : STD_LOGIC; + SIGNAL wire_nil111ii_dataout : STD_LOGIC; + SIGNAL wire_nil111il_dataout : STD_LOGIC; + SIGNAL wire_nil111iO_dataout : STD_LOGIC; + SIGNAL wire_nil111l_dataout : STD_LOGIC; + SIGNAL wire_nil111li_dataout : STD_LOGIC; + SIGNAL wire_nil111ll_dataout : STD_LOGIC; + SIGNAL wire_nil111lO_dataout : STD_LOGIC; + SIGNAL wire_nil111O_dataout : STD_LOGIC; + SIGNAL wire_nil111Oi_dataout : STD_LOGIC; + SIGNAL wire_nil111Ol_dataout : STD_LOGIC; + SIGNAL wire_nil111OO_dataout : STD_LOGIC; + SIGNAL wire_nil11ii_dataout : STD_LOGIC; + SIGNAL wire_nil11il_dataout : STD_LOGIC; + SIGNAL wire_nil11ili_dataout : STD_LOGIC; + SIGNAL wire_nil11ill_dataout : STD_LOGIC; + SIGNAL wire_nil11ilO_dataout : STD_LOGIC; + SIGNAL wire_nil11iO_dataout : STD_LOGIC; + SIGNAL wire_nil11iOi_dataout : STD_LOGIC; + SIGNAL wire_nil11iOl_dataout : STD_LOGIC; + SIGNAL wire_nil11iOO_dataout : STD_LOGIC; + SIGNAL wire_nil11l0i_dataout : STD_LOGIC; + SIGNAL wire_nil11l0l_dataout : STD_LOGIC; + SIGNAL wire_nil11l0O_dataout : STD_LOGIC; + SIGNAL wire_nil11l1i_dataout : STD_LOGIC; + SIGNAL wire_nil11l1l_dataout : STD_LOGIC; + SIGNAL wire_nil11l1O_dataout : STD_LOGIC; + SIGNAL wire_nil11li_dataout : STD_LOGIC; + SIGNAL wire_nil11lii_dataout : STD_LOGIC; + SIGNAL wire_nil11lil_dataout : STD_LOGIC; + SIGNAL wire_nil11liO_dataout : STD_LOGIC; + SIGNAL wire_nil11ll_dataout : STD_LOGIC; + SIGNAL wire_nil11lli_dataout : STD_LOGIC; + SIGNAL wire_nil11lll_dataout : STD_LOGIC; + SIGNAL wire_nil11llO_dataout : STD_LOGIC; + SIGNAL wire_nil11lO_dataout : STD_LOGIC; + SIGNAL wire_nil11lOi_dataout : STD_LOGIC; + SIGNAL wire_nil11lOl_dataout : STD_LOGIC; + SIGNAL wire_nil11lOO_dataout : STD_LOGIC; + SIGNAL wire_nil11O0i_dataout : STD_LOGIC; + SIGNAL wire_nil11O0l_dataout : STD_LOGIC; + SIGNAL wire_nil11O0O_dataout : STD_LOGIC; + SIGNAL wire_nil11O1i_dataout : STD_LOGIC; + SIGNAL wire_nil11O1l_dataout : STD_LOGIC; + SIGNAL wire_nil11O1O_dataout : STD_LOGIC; + SIGNAL wire_nil11Oi_dataout : STD_LOGIC; + SIGNAL wire_nil11Oii_dataout : STD_LOGIC; + SIGNAL wire_nil11Oil_dataout : STD_LOGIC; + SIGNAL wire_nil11OiO_dataout : STD_LOGIC; + SIGNAL wire_nil11Ol_dataout : STD_LOGIC; + SIGNAL wire_nil11Oli_dataout : STD_LOGIC; + SIGNAL wire_nil11Oll_dataout : STD_LOGIC; + SIGNAL wire_nil11OlO_dataout : STD_LOGIC; + SIGNAL wire_nil11OO_dataout : STD_LOGIC; + SIGNAL wire_nil11OOi_dataout : STD_LOGIC; + SIGNAL wire_nil11OOl_dataout : STD_LOGIC; + SIGNAL wire_nil11OOO_dataout : STD_LOGIC; + SIGNAL wire_nil1i00i_dataout : STD_LOGIC; + SIGNAL wire_nil1i00l_dataout : STD_LOGIC; + SIGNAL wire_nil1i00O_dataout : STD_LOGIC; + SIGNAL wire_nil1i01i_dataout : STD_LOGIC; + SIGNAL wire_nil1i01l_dataout : STD_LOGIC; + SIGNAL wire_nil1i01O_dataout : STD_LOGIC; + SIGNAL wire_nil1i0i_dataout : STD_LOGIC; + SIGNAL wire_nil1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nil1i0il_dataout : STD_LOGIC; + SIGNAL wire_nil1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nil1i0l_dataout : STD_LOGIC; + SIGNAL wire_nil1i0li_dataout : STD_LOGIC; + SIGNAL wire_nil1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nil1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nil1i0O_dataout : STD_LOGIC; + SIGNAL wire_nil1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nil1i10O_dataout : STD_LOGIC; + SIGNAL wire_nil1i1i_dataout : STD_LOGIC; + SIGNAL wire_nil1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nil1i1il_dataout : STD_LOGIC; + SIGNAL wire_nil1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nil1i1l_dataout : STD_LOGIC; + SIGNAL wire_nil1i1li_dataout : STD_LOGIC; + SIGNAL wire_nil1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nil1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nil1i1O_dataout : STD_LOGIC; + SIGNAL wire_nil1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nil1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nil1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nil1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nil1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nil1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nil1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nil1iii_dataout : STD_LOGIC; + SIGNAL wire_nil1iiii_dataout : STD_LOGIC; + SIGNAL wire_nil1iiil_dataout : STD_LOGIC; + SIGNAL wire_nil1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nil1iil_dataout : STD_LOGIC; + SIGNAL wire_nil1iili_dataout : STD_LOGIC; + SIGNAL wire_nil1iill_dataout : STD_LOGIC; + SIGNAL wire_nil1iilO_dataout : STD_LOGIC; + SIGNAL wire_nil1iiO_dataout : STD_LOGIC; + SIGNAL wire_nil1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nil1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nil1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nil1il0i_dataout : STD_LOGIC; + SIGNAL wire_nil1il0l_dataout : STD_LOGIC; + SIGNAL wire_nil1il0O_dataout : STD_LOGIC; + SIGNAL wire_nil1il1i_dataout : STD_LOGIC; + SIGNAL wire_nil1il1l_dataout : STD_LOGIC; + SIGNAL wire_nil1il1O_dataout : STD_LOGIC; + SIGNAL wire_nil1ili_dataout : STD_LOGIC; + SIGNAL wire_nil1ilii_dataout : STD_LOGIC; + SIGNAL wire_nil1ilil_dataout : STD_LOGIC; + SIGNAL wire_nil1iliO_dataout : STD_LOGIC; + SIGNAL wire_nil1ill_dataout : STD_LOGIC; + SIGNAL wire_nil1illi_dataout : STD_LOGIC; + SIGNAL wire_nil1illl_dataout : STD_LOGIC; + SIGNAL wire_nil1illO_dataout : STD_LOGIC; + SIGNAL wire_nil1ilO_dataout : STD_LOGIC; + SIGNAL wire_nil1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nil1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nil1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nil1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nil1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nil1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nil1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nil1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nil1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nil1iOi_dataout : STD_LOGIC; + SIGNAL wire_nil1iOii_dataout : STD_LOGIC; + SIGNAL wire_nil1iOil_dataout : STD_LOGIC; + SIGNAL wire_nil1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nil1iOl_dataout : STD_LOGIC; + SIGNAL wire_nil1iOli_dataout : STD_LOGIC; + SIGNAL wire_nil1iOll_dataout : STD_LOGIC; + SIGNAL wire_nil1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nil1iOO_dataout : STD_LOGIC; + SIGNAL wire_nil1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nil1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nil1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nil1l00i_dataout : STD_LOGIC; + SIGNAL wire_nil1l00l_dataout : STD_LOGIC; + SIGNAL wire_nil1l00O_dataout : STD_LOGIC; + SIGNAL wire_nil1l01i_dataout : STD_LOGIC; + SIGNAL wire_nil1l01l_dataout : STD_LOGIC; + SIGNAL wire_nil1l01O_dataout : STD_LOGIC; + SIGNAL wire_nil1l0i_dataout : STD_LOGIC; + SIGNAL wire_nil1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nil1l0il_dataout : STD_LOGIC; + SIGNAL wire_nil1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nil1l0l_dataout : STD_LOGIC; + SIGNAL wire_nil1l0li_dataout : STD_LOGIC; + SIGNAL wire_nil1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nil1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nil1l0O_dataout : STD_LOGIC; + SIGNAL wire_nil1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nil1l10i_dataout : STD_LOGIC; + SIGNAL wire_nil1l10l_dataout : STD_LOGIC; + SIGNAL wire_nil1l10O_dataout : STD_LOGIC; + SIGNAL wire_nil1l11i_dataout : STD_LOGIC; + SIGNAL wire_nil1l11l_dataout : STD_LOGIC; + SIGNAL wire_nil1l11O_dataout : STD_LOGIC; + SIGNAL wire_nil1l1i_dataout : STD_LOGIC; + SIGNAL wire_nil1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nil1l1il_dataout : STD_LOGIC; + SIGNAL wire_nil1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nil1l1l_dataout : STD_LOGIC; + SIGNAL wire_nil1l1li_dataout : STD_LOGIC; + SIGNAL wire_nil1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nil1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nil1l1O_dataout : STD_LOGIC; + SIGNAL wire_nil1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nil1li0i_dataout : STD_LOGIC; + SIGNAL wire_nil1li0l_dataout : STD_LOGIC; + SIGNAL wire_nil1li0O_dataout : STD_LOGIC; + SIGNAL wire_nil1li1i_dataout : STD_LOGIC; + SIGNAL wire_nil1li1l_dataout : STD_LOGIC; + SIGNAL wire_nil1li1O_dataout : STD_LOGIC; + SIGNAL wire_nil1lii_dataout : STD_LOGIC; + SIGNAL wire_nil1liii_dataout : STD_LOGIC; + SIGNAL wire_nil1liil_dataout : STD_LOGIC; + SIGNAL wire_nil1liiO_dataout : STD_LOGIC; + SIGNAL wire_nil1lil_dataout : STD_LOGIC; + SIGNAL wire_nil1lili_dataout : STD_LOGIC; + SIGNAL wire_nil1lill_dataout : STD_LOGIC; + SIGNAL wire_nil1lilO_dataout : STD_LOGIC; + SIGNAL wire_nil1liO_dataout : STD_LOGIC; + SIGNAL wire_nil1liOi_dataout : STD_LOGIC; + SIGNAL wire_nil1liOl_dataout : STD_LOGIC; + SIGNAL wire_nil1liOO_dataout : STD_LOGIC; + SIGNAL wire_nil1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nil1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nil1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nil1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nil1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nil1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nil1lli_dataout : STD_LOGIC; + SIGNAL wire_nil1llii_dataout : STD_LOGIC; + SIGNAL wire_nil1llil_dataout : STD_LOGIC; + SIGNAL wire_nil1lliO_dataout : STD_LOGIC; + SIGNAL wire_nil1lll_dataout : STD_LOGIC; + SIGNAL wire_nil1llli_dataout : STD_LOGIC; + SIGNAL wire_nil1llll_dataout : STD_LOGIC; + SIGNAL wire_nil1lllO_dataout : STD_LOGIC; + SIGNAL wire_nil1llO_dataout : STD_LOGIC; + SIGNAL wire_nil1llOi_dataout : STD_LOGIC; + SIGNAL wire_nil1llOl_dataout : STD_LOGIC; + SIGNAL wire_nil1llOO_dataout : STD_LOGIC; + SIGNAL wire_nil1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nil1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nil1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nil1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nil1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nil1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nil1lOi_dataout : STD_LOGIC; + SIGNAL wire_nil1lOii_dataout : STD_LOGIC; + SIGNAL wire_nil1lOil_dataout : STD_LOGIC; + SIGNAL wire_nil1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nil1lOl_dataout : STD_LOGIC; + SIGNAL wire_nil1lOli_dataout : STD_LOGIC; + SIGNAL wire_nil1lOll_dataout : STD_LOGIC; + SIGNAL wire_nil1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nil1lOO_dataout : STD_LOGIC; + SIGNAL wire_nil1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nil1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nil1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nil1O00i_dataout : STD_LOGIC; + SIGNAL wire_nil1O00l_dataout : STD_LOGIC; + SIGNAL wire_nil1O00O_dataout : STD_LOGIC; + SIGNAL wire_nil1O01i_dataout : STD_LOGIC; + SIGNAL wire_nil1O01l_dataout : STD_LOGIC; + SIGNAL wire_nil1O01O_dataout : STD_LOGIC; + SIGNAL wire_nil1O0i_dataout : STD_LOGIC; + SIGNAL wire_nil1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nil1O0il_dataout : STD_LOGIC; + SIGNAL wire_nil1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nil1O0l_dataout : STD_LOGIC; + SIGNAL wire_nil1O0li_dataout : STD_LOGIC; + SIGNAL wire_nil1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nil1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nil1O0O_dataout : STD_LOGIC; + SIGNAL wire_nil1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nil1O10i_dataout : STD_LOGIC; + SIGNAL wire_nil1O10l_dataout : STD_LOGIC; + SIGNAL wire_nil1O10O_dataout : STD_LOGIC; + SIGNAL wire_nil1O11i_dataout : STD_LOGIC; + SIGNAL wire_nil1O11l_dataout : STD_LOGIC; + SIGNAL wire_nil1O11O_dataout : STD_LOGIC; + SIGNAL wire_nil1O1i_dataout : STD_LOGIC; + SIGNAL wire_nil1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nil1O1il_dataout : STD_LOGIC; + SIGNAL wire_nil1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nil1O1l_dataout : STD_LOGIC; + SIGNAL wire_nil1O1li_dataout : STD_LOGIC; + SIGNAL wire_nil1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nil1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nil1O1O_dataout : STD_LOGIC; + SIGNAL wire_nil1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nil1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nil1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nil1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nil1Oii_dataout : STD_LOGIC; + SIGNAL wire_nil1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nil1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nil1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nil1Oil_dataout : STD_LOGIC; + SIGNAL wire_nil1Oili_dataout : STD_LOGIC; + SIGNAL wire_nil1Oill_dataout : STD_LOGIC; + SIGNAL wire_nil1OilO_dataout : STD_LOGIC; + SIGNAL wire_nil1OiO_dataout : STD_LOGIC; + SIGNAL wire_nil1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nil1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nil1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nil1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nil1Oli_dataout : STD_LOGIC; + SIGNAL wire_nil1Olii_dataout : STD_LOGIC; + SIGNAL wire_nil1Olil_dataout : STD_LOGIC; + SIGNAL wire_nil1OliO_dataout : STD_LOGIC; + SIGNAL wire_nil1Oll_dataout : STD_LOGIC; + SIGNAL wire_nil1Olli_dataout : STD_LOGIC; + SIGNAL wire_nil1Olll_dataout : STD_LOGIC; + SIGNAL wire_nil1OllO_dataout : STD_LOGIC; + SIGNAL wire_nil1OlO_dataout : STD_LOGIC; + SIGNAL wire_nil1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nil1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nil1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nil1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nil1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nil1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nil1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nil1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nil1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nil1OOi_dataout : STD_LOGIC; + SIGNAL wire_nil1OOii_dataout : STD_LOGIC; + SIGNAL wire_nil1OOil_dataout : STD_LOGIC; + SIGNAL wire_nil1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nil1OOl_dataout : STD_LOGIC; + SIGNAL wire_nil1OOli_dataout : STD_LOGIC; + SIGNAL wire_nil1OOll_dataout : STD_LOGIC; + SIGNAL wire_nil1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nil1OOO_dataout : STD_LOGIC; + SIGNAL wire_nil1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nil1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nil1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nili000i_dataout : STD_LOGIC; + SIGNAL wire_nili000l_dataout : STD_LOGIC; + SIGNAL wire_nili000O_dataout : STD_LOGIC; + SIGNAL wire_nili001i_dataout : STD_LOGIC; + SIGNAL wire_nili001l_dataout : STD_LOGIC; + SIGNAL wire_nili001O_dataout : STD_LOGIC; + SIGNAL wire_nili00i_dataout : STD_LOGIC; + SIGNAL wire_nili00ii_dataout : STD_LOGIC; + SIGNAL wire_nili00il_dataout : STD_LOGIC; + SIGNAL wire_nili00iO_dataout : STD_LOGIC; + SIGNAL wire_nili00l_dataout : STD_LOGIC; + SIGNAL wire_nili00li_dataout : STD_LOGIC; + SIGNAL wire_nili00ll_dataout : STD_LOGIC; + SIGNAL wire_nili00lO_dataout : STD_LOGIC; + SIGNAL wire_nili00O_dataout : STD_LOGIC; + SIGNAL wire_nili00Oi_dataout : STD_LOGIC; + SIGNAL wire_nili00Ol_dataout : STD_LOGIC; + SIGNAL wire_nili00OO_dataout : STD_LOGIC; + SIGNAL wire_nili010i_dataout : STD_LOGIC; + SIGNAL wire_nili010l_dataout : STD_LOGIC; + SIGNAL wire_nili010O_dataout : STD_LOGIC; + SIGNAL wire_nili011i_dataout : STD_LOGIC; + SIGNAL wire_nili011l_dataout : STD_LOGIC; + SIGNAL wire_nili011O_dataout : STD_LOGIC; + SIGNAL wire_nili01i_dataout : STD_LOGIC; + SIGNAL wire_nili01ii_dataout : STD_LOGIC; + SIGNAL wire_nili01il_dataout : STD_LOGIC; + SIGNAL wire_nili01iO_dataout : STD_LOGIC; + SIGNAL wire_nili01l_dataout : STD_LOGIC; + SIGNAL wire_nili01li_dataout : STD_LOGIC; + SIGNAL wire_nili01ll_dataout : STD_LOGIC; + SIGNAL wire_nili01lO_dataout : STD_LOGIC; + SIGNAL wire_nili01O_dataout : STD_LOGIC; + SIGNAL wire_nili01Oi_dataout : STD_LOGIC; + SIGNAL wire_nili01Ol_dataout : STD_LOGIC; + SIGNAL wire_nili01OO_dataout : STD_LOGIC; + SIGNAL wire_nili0i0i_dataout : STD_LOGIC; + SIGNAL wire_nili0i0l_dataout : STD_LOGIC; + SIGNAL wire_nili0i0O_dataout : STD_LOGIC; + SIGNAL wire_nili0i1i_dataout : STD_LOGIC; + SIGNAL wire_nili0i1l_dataout : STD_LOGIC; + SIGNAL wire_nili0i1O_dataout : STD_LOGIC; + SIGNAL wire_nili0ii_dataout : STD_LOGIC; + SIGNAL wire_nili0iii_dataout : STD_LOGIC; + SIGNAL wire_nili0iil_dataout : STD_LOGIC; + SIGNAL wire_nili0iiO_dataout : STD_LOGIC; + SIGNAL wire_nili0il_dataout : STD_LOGIC; + SIGNAL wire_nili0ili_dataout : STD_LOGIC; + SIGNAL wire_nili0ill_dataout : STD_LOGIC; + SIGNAL wire_nili0ilO_dataout : STD_LOGIC; + SIGNAL wire_nili0iO_dataout : STD_LOGIC; + SIGNAL wire_nili0iOi_dataout : STD_LOGIC; + SIGNAL wire_nili0iOl_dataout : STD_LOGIC; + SIGNAL wire_nili0iOO_dataout : STD_LOGIC; + SIGNAL wire_nili0l0i_dataout : STD_LOGIC; + SIGNAL wire_nili0l0l_dataout : STD_LOGIC; + SIGNAL wire_nili0l0O_dataout : STD_LOGIC; + SIGNAL wire_nili0l1i_dataout : STD_LOGIC; + SIGNAL wire_nili0l1l_dataout : STD_LOGIC; + SIGNAL wire_nili0l1O_dataout : STD_LOGIC; + SIGNAL wire_nili0li_dataout : STD_LOGIC; + SIGNAL wire_nili0lii_dataout : STD_LOGIC; + SIGNAL wire_nili0lil_dataout : STD_LOGIC; + SIGNAL wire_nili0liO_dataout : STD_LOGIC; + SIGNAL wire_nili0ll_dataout : STD_LOGIC; + SIGNAL wire_nili0lli_dataout : STD_LOGIC; + SIGNAL wire_nili0lll_dataout : STD_LOGIC; + SIGNAL wire_nili0llO_dataout : STD_LOGIC; + SIGNAL wire_nili0lO_dataout : STD_LOGIC; + SIGNAL wire_nili0lOi_dataout : STD_LOGIC; + SIGNAL wire_nili0lOl_dataout : STD_LOGIC; + SIGNAL wire_nili0lOO_dataout : STD_LOGIC; + SIGNAL wire_nili0O0i_dataout : STD_LOGIC; + SIGNAL wire_nili0O0l_dataout : STD_LOGIC; + SIGNAL wire_nili0O0O_dataout : STD_LOGIC; + SIGNAL wire_nili0O1i_dataout : STD_LOGIC; + SIGNAL wire_nili0O1l_dataout : STD_LOGIC; + SIGNAL wire_nili0O1O_dataout : STD_LOGIC; + SIGNAL wire_nili0Oi_dataout : STD_LOGIC; + SIGNAL wire_nili0Oii_dataout : STD_LOGIC; + SIGNAL wire_nili0Oil_dataout : STD_LOGIC; + SIGNAL wire_nili0OiO_dataout : STD_LOGIC; + SIGNAL wire_nili0Ol_dataout : STD_LOGIC; + SIGNAL wire_nili0Oli_dataout : STD_LOGIC; + SIGNAL wire_nili0Oll_dataout : STD_LOGIC; + SIGNAL wire_nili0OlO_dataout : STD_LOGIC; + SIGNAL wire_nili0OO_dataout : STD_LOGIC; + SIGNAL wire_nili0OOi_dataout : STD_LOGIC; + SIGNAL wire_nili0OOl_dataout : STD_LOGIC; + SIGNAL wire_nili0OOO_dataout : STD_LOGIC; + SIGNAL wire_nili10i_dataout : STD_LOGIC; + SIGNAL wire_nili10l_dataout : STD_LOGIC; + SIGNAL wire_nili10O_dataout : STD_LOGIC; + SIGNAL wire_nili11i_dataout : STD_LOGIC; + SIGNAL wire_nili11l_dataout : STD_LOGIC; + SIGNAL wire_nili11O_dataout : STD_LOGIC; + SIGNAL wire_nili1ii_dataout : STD_LOGIC; + SIGNAL wire_nili1il_dataout : STD_LOGIC; + SIGNAL wire_nili1iO_dataout : STD_LOGIC; + SIGNAL wire_nili1l0i_dataout : STD_LOGIC; + SIGNAL wire_nili1l0l_dataout : STD_LOGIC; + SIGNAL wire_nili1l0O_dataout : STD_LOGIC; + SIGNAL wire_nili1l1O_dataout : STD_LOGIC; + SIGNAL wire_nili1li_dataout : STD_LOGIC; + SIGNAL wire_nili1lii_dataout : STD_LOGIC; + SIGNAL wire_nili1lil_dataout : STD_LOGIC; + SIGNAL wire_nili1liO_dataout : STD_LOGIC; + SIGNAL wire_nili1ll_dataout : STD_LOGIC; + SIGNAL wire_nili1lli_dataout : STD_LOGIC; + SIGNAL wire_nili1lll_dataout : STD_LOGIC; + SIGNAL wire_nili1llO_dataout : STD_LOGIC; + SIGNAL wire_nili1lO_dataout : STD_LOGIC; + SIGNAL wire_nili1lOi_dataout : STD_LOGIC; + SIGNAL wire_nili1lOl_dataout : STD_LOGIC; + SIGNAL wire_nili1lOO_dataout : STD_LOGIC; + SIGNAL wire_nili1O0i_dataout : STD_LOGIC; + SIGNAL wire_nili1O0l_dataout : STD_LOGIC; + SIGNAL wire_nili1O0O_dataout : STD_LOGIC; + SIGNAL wire_nili1O1i_dataout : STD_LOGIC; + SIGNAL wire_nili1O1l_dataout : STD_LOGIC; + SIGNAL wire_nili1O1O_dataout : STD_LOGIC; + SIGNAL wire_nili1Oi_dataout : STD_LOGIC; + SIGNAL wire_nili1Oii_dataout : STD_LOGIC; + SIGNAL wire_nili1Oil_dataout : STD_LOGIC; + SIGNAL wire_nili1OiO_dataout : STD_LOGIC; + SIGNAL wire_nili1Ol_dataout : STD_LOGIC; + SIGNAL wire_nili1Oli_dataout : STD_LOGIC; + SIGNAL wire_nili1Oll_dataout : STD_LOGIC; + SIGNAL wire_nili1OlO_dataout : STD_LOGIC; + SIGNAL wire_nili1OO_dataout : STD_LOGIC; + SIGNAL wire_nili1OOi_dataout : STD_LOGIC; + SIGNAL wire_nili1OOl_dataout : STD_LOGIC; + SIGNAL wire_nili1OOO_dataout : STD_LOGIC; + SIGNAL wire_nilii00i_dataout : STD_LOGIC; + SIGNAL wire_nilii00l_dataout : STD_LOGIC; + SIGNAL wire_nilii00O_dataout : STD_LOGIC; + SIGNAL wire_nilii01i_dataout : STD_LOGIC; + SIGNAL wire_nilii01l_dataout : STD_LOGIC; + SIGNAL wire_nilii01O_dataout : STD_LOGIC; + SIGNAL wire_nilii0i_dataout : STD_LOGIC; + SIGNAL wire_nilii0ii_dataout : STD_LOGIC; + SIGNAL wire_nilii0il_dataout : STD_LOGIC; + SIGNAL wire_nilii0iO_dataout : STD_LOGIC; + SIGNAL wire_nilii0l_dataout : STD_LOGIC; + SIGNAL wire_nilii0li_dataout : STD_LOGIC; + SIGNAL wire_nilii0ll_dataout : STD_LOGIC; + SIGNAL wire_nilii0lO_dataout : STD_LOGIC; + SIGNAL wire_nilii0O_dataout : STD_LOGIC; + SIGNAL wire_nilii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilii0OO_dataout : STD_LOGIC; + SIGNAL wire_nilii10i_dataout : STD_LOGIC; + SIGNAL wire_nilii10l_dataout : STD_LOGIC; + SIGNAL wire_nilii10O_dataout : STD_LOGIC; + SIGNAL wire_nilii11i_dataout : STD_LOGIC; + SIGNAL wire_nilii11l_dataout : STD_LOGIC; + SIGNAL wire_nilii11O_dataout : STD_LOGIC; + SIGNAL wire_nilii1i_dataout : STD_LOGIC; + SIGNAL wire_nilii1ii_dataout : STD_LOGIC; + SIGNAL wire_nilii1il_dataout : STD_LOGIC; + SIGNAL wire_nilii1iO_dataout : STD_LOGIC; + SIGNAL wire_nilii1l_dataout : STD_LOGIC; + SIGNAL wire_nilii1li_dataout : STD_LOGIC; + SIGNAL wire_nilii1ll_dataout : STD_LOGIC; + SIGNAL wire_nilii1lO_dataout : STD_LOGIC; + SIGNAL wire_nilii1O_dataout : STD_LOGIC; + SIGNAL wire_nilii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nilii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nilii1OO_dataout : STD_LOGIC; + SIGNAL wire_niliii0i_dataout : STD_LOGIC; + SIGNAL wire_niliii0l_dataout : STD_LOGIC; + SIGNAL wire_niliii0O_dataout : STD_LOGIC; + SIGNAL wire_niliii1i_dataout : STD_LOGIC; + SIGNAL wire_niliii1l_dataout : STD_LOGIC; + SIGNAL wire_niliii1O_dataout : STD_LOGIC; + SIGNAL wire_niliiii_dataout : STD_LOGIC; + SIGNAL wire_niliiiii_dataout : STD_LOGIC; + SIGNAL wire_niliiiil_dataout : STD_LOGIC; + SIGNAL wire_niliiiiO_dataout : STD_LOGIC; + SIGNAL wire_niliiil_dataout : STD_LOGIC; + SIGNAL wire_niliiili_dataout : STD_LOGIC; + SIGNAL wire_niliiill_dataout : STD_LOGIC; + SIGNAL wire_niliiilO_dataout : STD_LOGIC; + SIGNAL wire_niliiiO_dataout : STD_LOGIC; + SIGNAL wire_niliiiOi_dataout : STD_LOGIC; + SIGNAL wire_niliiiOl_dataout : STD_LOGIC; + SIGNAL wire_niliiiOO_dataout : STD_LOGIC; + SIGNAL wire_niliil0i_dataout : STD_LOGIC; + SIGNAL wire_niliil0l_dataout : STD_LOGIC; + SIGNAL wire_niliil0O_dataout : STD_LOGIC; + SIGNAL wire_niliil1i_dataout : STD_LOGIC; + SIGNAL wire_niliil1l_dataout : STD_LOGIC; + SIGNAL wire_niliil1O_dataout : STD_LOGIC; + SIGNAL wire_niliili_dataout : STD_LOGIC; + SIGNAL wire_niliilii_dataout : STD_LOGIC; + SIGNAL wire_niliilil_dataout : STD_LOGIC; + SIGNAL wire_niliiliO_dataout : STD_LOGIC; + SIGNAL wire_niliill_dataout : STD_LOGIC; + SIGNAL wire_niliilli_dataout : STD_LOGIC; + SIGNAL wire_niliilll_dataout : STD_LOGIC; + SIGNAL wire_niliillO_dataout : STD_LOGIC; + SIGNAL wire_niliilO_dataout : STD_LOGIC; + SIGNAL wire_niliilOi_dataout : STD_LOGIC; + SIGNAL wire_niliilOl_dataout : STD_LOGIC; + SIGNAL wire_niliilOO_dataout : STD_LOGIC; + SIGNAL wire_niliiO0i_dataout : STD_LOGIC; + SIGNAL wire_niliiO0l_dataout : STD_LOGIC; + SIGNAL wire_niliiO0O_dataout : STD_LOGIC; + SIGNAL wire_niliiO1i_dataout : STD_LOGIC; + SIGNAL wire_niliiO1l_dataout : STD_LOGIC; + SIGNAL wire_niliiO1O_dataout : STD_LOGIC; + SIGNAL wire_niliiOi_dataout : STD_LOGIC; + SIGNAL wire_niliiOii_dataout : STD_LOGIC; + SIGNAL wire_niliiOil_dataout : STD_LOGIC; + SIGNAL wire_niliiOiO_dataout : STD_LOGIC; + SIGNAL wire_niliiOl_dataout : STD_LOGIC; + SIGNAL wire_niliiOli_dataout : STD_LOGIC; + SIGNAL wire_niliiOll_dataout : STD_LOGIC; + SIGNAL wire_niliiOlO_dataout : STD_LOGIC; + SIGNAL wire_niliiOO_dataout : STD_LOGIC; + SIGNAL wire_niliiOOi_dataout : STD_LOGIC; + SIGNAL wire_niliiOOl_dataout : STD_LOGIC; + SIGNAL wire_niliiOOO_dataout : STD_LOGIC; + SIGNAL wire_nilil00i_dataout : STD_LOGIC; + SIGNAL wire_nilil00l_dataout : STD_LOGIC; + SIGNAL wire_nilil00O_dataout : STD_LOGIC; + SIGNAL wire_nilil01i_dataout : STD_LOGIC; + SIGNAL wire_nilil01l_dataout : STD_LOGIC; + SIGNAL wire_nilil01O_dataout : STD_LOGIC; + SIGNAL wire_nilil0i_dataout : STD_LOGIC; + SIGNAL wire_nilil0ii_dataout : STD_LOGIC; + SIGNAL wire_nilil0il_dataout : STD_LOGIC; + SIGNAL wire_nilil0iO_dataout : STD_LOGIC; + SIGNAL wire_nilil0l_dataout : STD_LOGIC; + SIGNAL wire_nilil0li_dataout : STD_LOGIC; + SIGNAL wire_nilil0ll_dataout : STD_LOGIC; + SIGNAL wire_nilil0lO_dataout : STD_LOGIC; + SIGNAL wire_nilil0O_dataout : STD_LOGIC; + SIGNAL wire_nilil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilil0OO_dataout : STD_LOGIC; + SIGNAL wire_nilil10i_dataout : STD_LOGIC; + SIGNAL wire_nilil10l_dataout : STD_LOGIC; + SIGNAL wire_nilil10O_dataout : STD_LOGIC; + SIGNAL wire_nilil11i_dataout : STD_LOGIC; + SIGNAL wire_nilil11l_dataout : STD_LOGIC; + SIGNAL wire_nilil11O_dataout : STD_LOGIC; + SIGNAL wire_nilil1i_dataout : STD_LOGIC; + SIGNAL wire_nilil1ii_dataout : STD_LOGIC; + SIGNAL wire_nilil1il_dataout : STD_LOGIC; + SIGNAL wire_nilil1iO_dataout : STD_LOGIC; + SIGNAL wire_nilil1l_dataout : STD_LOGIC; + SIGNAL wire_nilil1li_dataout : STD_LOGIC; + SIGNAL wire_nilil1ll_dataout : STD_LOGIC; + SIGNAL wire_nilil1lO_dataout : STD_LOGIC; + SIGNAL wire_nilil1O_dataout : STD_LOGIC; + SIGNAL wire_nilil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nilil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nilil1OO_dataout : STD_LOGIC; + SIGNAL wire_nilili0i_dataout : STD_LOGIC; + SIGNAL wire_nilili0l_dataout : STD_LOGIC; + SIGNAL wire_nilili0O_dataout : STD_LOGIC; + SIGNAL wire_nilili1i_dataout : STD_LOGIC; + SIGNAL wire_nilili1l_dataout : STD_LOGIC; + SIGNAL wire_nilili1O_dataout : STD_LOGIC; + SIGNAL wire_nililii_dataout : STD_LOGIC; + SIGNAL wire_nililiii_dataout : STD_LOGIC; + SIGNAL wire_nililiil_dataout : STD_LOGIC; + SIGNAL wire_nililiiO_dataout : STD_LOGIC; + SIGNAL wire_nililil_dataout : STD_LOGIC; + SIGNAL wire_nililili_dataout : STD_LOGIC; + SIGNAL wire_nililill_dataout : STD_LOGIC; + SIGNAL wire_nilililO_dataout : STD_LOGIC; + SIGNAL wire_nililiO_dataout : STD_LOGIC; + SIGNAL wire_nililiOi_dataout : STD_LOGIC; + SIGNAL wire_nililiOl_dataout : STD_LOGIC; + SIGNAL wire_nililiOO_dataout : STD_LOGIC; + SIGNAL wire_nilill0i_dataout : STD_LOGIC; + SIGNAL wire_nilill0l_dataout : STD_LOGIC; + SIGNAL wire_nilill0O_dataout : STD_LOGIC; + SIGNAL wire_nilill1i_dataout : STD_LOGIC; + SIGNAL wire_nilill1l_dataout : STD_LOGIC; + SIGNAL wire_nilill1O_dataout : STD_LOGIC; + SIGNAL wire_nililli_dataout : STD_LOGIC; + SIGNAL wire_nilillii_dataout : STD_LOGIC; + SIGNAL wire_nilillil_dataout : STD_LOGIC; + SIGNAL wire_nililliO_dataout : STD_LOGIC; + SIGNAL wire_nililll_dataout : STD_LOGIC; + SIGNAL wire_nilillli_dataout : STD_LOGIC; + SIGNAL wire_nilillll_dataout : STD_LOGIC; + SIGNAL wire_nililllO_dataout : STD_LOGIC; + SIGNAL wire_nilillO_dataout : STD_LOGIC; + SIGNAL wire_nilillOi_dataout : STD_LOGIC; + SIGNAL wire_nilillOl_dataout : STD_LOGIC; + SIGNAL wire_nilillOO_dataout : STD_LOGIC; + SIGNAL wire_nililO0i_dataout : STD_LOGIC; + SIGNAL wire_nililO0l_dataout : STD_LOGIC; + SIGNAL wire_nililO0O_dataout : STD_LOGIC; + SIGNAL wire_nililO1i_dataout : STD_LOGIC; + SIGNAL wire_nililO1l_dataout : STD_LOGIC; + SIGNAL wire_nililO1O_dataout : STD_LOGIC; + SIGNAL wire_nililOi_dataout : STD_LOGIC; + SIGNAL wire_nililOii_dataout : STD_LOGIC; + SIGNAL wire_nililOil_dataout : STD_LOGIC; + SIGNAL wire_nililOiO_dataout : STD_LOGIC; + SIGNAL wire_nililOl_dataout : STD_LOGIC; + SIGNAL wire_nililOli_dataout : STD_LOGIC; + SIGNAL wire_nililOll_dataout : STD_LOGIC; + SIGNAL wire_nililOlO_dataout : STD_LOGIC; + SIGNAL wire_nililOO_dataout : STD_LOGIC; + SIGNAL wire_nililOOi_dataout : STD_LOGIC; + SIGNAL wire_nililOOl_dataout : STD_LOGIC; + SIGNAL wire_nililOOO_dataout : STD_LOGIC; + SIGNAL wire_niliO00i_dataout : STD_LOGIC; + SIGNAL wire_niliO00l_dataout : STD_LOGIC; + SIGNAL wire_niliO00O_dataout : STD_LOGIC; + SIGNAL wire_niliO01i_dataout : STD_LOGIC; + SIGNAL wire_niliO01l_dataout : STD_LOGIC; + SIGNAL wire_niliO01O_dataout : STD_LOGIC; + SIGNAL wire_niliO0i_dataout : STD_LOGIC; + SIGNAL wire_niliO0ii_dataout : STD_LOGIC; + SIGNAL wire_niliO0il_dataout : STD_LOGIC; + SIGNAL wire_niliO0iO_dataout : STD_LOGIC; + SIGNAL wire_niliO0l_dataout : STD_LOGIC; + SIGNAL wire_niliO0li_dataout : STD_LOGIC; + SIGNAL wire_niliO0ll_dataout : STD_LOGIC; + SIGNAL wire_niliO0lO_dataout : STD_LOGIC; + SIGNAL wire_niliO0O_dataout : STD_LOGIC; + SIGNAL wire_niliO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niliO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niliO0OO_dataout : STD_LOGIC; + SIGNAL wire_niliO10i_dataout : STD_LOGIC; + SIGNAL wire_niliO10l_dataout : STD_LOGIC; + SIGNAL wire_niliO10O_dataout : STD_LOGIC; + SIGNAL wire_niliO11i_dataout : STD_LOGIC; + SIGNAL wire_niliO11l_dataout : STD_LOGIC; + SIGNAL wire_niliO11O_dataout : STD_LOGIC; + SIGNAL wire_niliO1i_dataout : STD_LOGIC; + SIGNAL wire_niliO1ii_dataout : STD_LOGIC; + SIGNAL wire_niliO1il_dataout : STD_LOGIC; + SIGNAL wire_niliO1iO_dataout : STD_LOGIC; + SIGNAL wire_niliO1l_dataout : STD_LOGIC; + SIGNAL wire_niliO1li_dataout : STD_LOGIC; + SIGNAL wire_niliO1ll_dataout : STD_LOGIC; + SIGNAL wire_niliO1lO_dataout : STD_LOGIC; + SIGNAL wire_niliO1O_dataout : STD_LOGIC; + SIGNAL wire_niliO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niliO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niliO1OO_dataout : STD_LOGIC; + SIGNAL wire_niliOi0i_dataout : STD_LOGIC; + SIGNAL wire_niliOi0l_dataout : STD_LOGIC; + SIGNAL wire_niliOi0O_dataout : STD_LOGIC; + SIGNAL wire_niliOi1i_dataout : STD_LOGIC; + SIGNAL wire_niliOi1l_dataout : STD_LOGIC; + SIGNAL wire_niliOi1O_dataout : STD_LOGIC; + SIGNAL wire_niliOii_dataout : STD_LOGIC; + SIGNAL wire_niliOiii_dataout : STD_LOGIC; + SIGNAL wire_niliOiil_dataout : STD_LOGIC; + SIGNAL wire_niliOiiO_dataout : STD_LOGIC; + SIGNAL wire_niliOil_dataout : STD_LOGIC; + SIGNAL wire_niliOili_dataout : STD_LOGIC; + SIGNAL wire_niliOill_dataout : STD_LOGIC; + SIGNAL wire_niliOilO_dataout : STD_LOGIC; + SIGNAL wire_niliOiO_dataout : STD_LOGIC; + SIGNAL wire_niliOiOi_dataout : STD_LOGIC; + SIGNAL wire_niliOiOl_dataout : STD_LOGIC; + SIGNAL wire_niliOiOO_dataout : STD_LOGIC; + SIGNAL wire_niliOl0i_dataout : STD_LOGIC; + SIGNAL wire_niliOl0l_dataout : STD_LOGIC; + SIGNAL wire_niliOl0O_dataout : STD_LOGIC; + SIGNAL wire_niliOl1i_dataout : STD_LOGIC; + SIGNAL wire_niliOl1l_dataout : STD_LOGIC; + SIGNAL wire_niliOl1O_dataout : STD_LOGIC; + SIGNAL wire_niliOli_dataout : STD_LOGIC; + SIGNAL wire_niliOlii_dataout : STD_LOGIC; + SIGNAL wire_niliOlil_dataout : STD_LOGIC; + SIGNAL wire_niliOliO_dataout : STD_LOGIC; + SIGNAL wire_niliOll_dataout : STD_LOGIC; + SIGNAL wire_niliOlli_dataout : STD_LOGIC; + SIGNAL wire_niliOlll_dataout : STD_LOGIC; + SIGNAL wire_niliOllO_dataout : STD_LOGIC; + SIGNAL wire_niliOlO_dataout : STD_LOGIC; + SIGNAL wire_niliOlOi_dataout : STD_LOGIC; + SIGNAL wire_niliOlOl_dataout : STD_LOGIC; + SIGNAL wire_niliOlOO_dataout : STD_LOGIC; + SIGNAL wire_niliOO0i_dataout : STD_LOGIC; + SIGNAL wire_niliOO0l_dataout : STD_LOGIC; + SIGNAL wire_niliOO0O_dataout : STD_LOGIC; + SIGNAL wire_niliOO1i_dataout : STD_LOGIC; + SIGNAL wire_niliOO1l_dataout : STD_LOGIC; + SIGNAL wire_niliOO1O_dataout : STD_LOGIC; + SIGNAL wire_niliOOi_dataout : STD_LOGIC; + SIGNAL wire_niliOOii_dataout : STD_LOGIC; + SIGNAL wire_niliOOil_dataout : STD_LOGIC; + SIGNAL wire_niliOOiO_dataout : STD_LOGIC; + SIGNAL wire_niliOOl_dataout : STD_LOGIC; + SIGNAL wire_niliOOli_dataout : STD_LOGIC; + SIGNAL wire_niliOOll_dataout : STD_LOGIC; + SIGNAL wire_niliOOlO_dataout : STD_LOGIC; + SIGNAL wire_niliOOO_dataout : STD_LOGIC; + SIGNAL wire_niliOOOi_dataout : STD_LOGIC; + SIGNAL wire_niliOOOl_dataout : STD_LOGIC; + SIGNAL wire_niliOOOO_dataout : STD_LOGIC; + SIGNAL wire_nill000i_dataout : STD_LOGIC; + SIGNAL wire_nill000l_dataout : STD_LOGIC; + SIGNAL wire_nill000O_dataout : STD_LOGIC; + SIGNAL wire_nill001i_dataout : STD_LOGIC; + SIGNAL wire_nill001l_dataout : STD_LOGIC; + SIGNAL wire_nill001O_dataout : STD_LOGIC; + SIGNAL wire_nill00i_dataout : STD_LOGIC; + SIGNAL wire_nill00ii_dataout : STD_LOGIC; + SIGNAL wire_nill00il_dataout : STD_LOGIC; + SIGNAL wire_nill00iO_dataout : STD_LOGIC; + SIGNAL wire_nill00l_dataout : STD_LOGIC; + SIGNAL wire_nill00li_dataout : STD_LOGIC; + SIGNAL wire_nill00ll_dataout : STD_LOGIC; + SIGNAL wire_nill00lO_dataout : STD_LOGIC; + SIGNAL wire_nill00O_dataout : STD_LOGIC; + SIGNAL wire_nill00Oi_dataout : STD_LOGIC; + SIGNAL wire_nill00Ol_dataout : STD_LOGIC; + SIGNAL wire_nill00OO_dataout : STD_LOGIC; + SIGNAL wire_nill010i_dataout : STD_LOGIC; + SIGNAL wire_nill010l_dataout : STD_LOGIC; + SIGNAL wire_nill010O_dataout : STD_LOGIC; + SIGNAL wire_nill011i_dataout : STD_LOGIC; + SIGNAL wire_nill011l_dataout : STD_LOGIC; + SIGNAL wire_nill011O_dataout : STD_LOGIC; + SIGNAL wire_nill01i_dataout : STD_LOGIC; + SIGNAL wire_nill01ii_dataout : STD_LOGIC; + SIGNAL wire_nill01il_dataout : STD_LOGIC; + SIGNAL wire_nill01iO_dataout : STD_LOGIC; + SIGNAL wire_nill01l_dataout : STD_LOGIC; + SIGNAL wire_nill01li_dataout : STD_LOGIC; + SIGNAL wire_nill01ll_dataout : STD_LOGIC; + SIGNAL wire_nill01lO_dataout : STD_LOGIC; + SIGNAL wire_nill01O_dataout : STD_LOGIC; + SIGNAL wire_nill01Oi_dataout : STD_LOGIC; + SIGNAL wire_nill01Ol_dataout : STD_LOGIC; + SIGNAL wire_nill01OO_dataout : STD_LOGIC; + SIGNAL wire_nill0i0i_dataout : STD_LOGIC; + SIGNAL wire_nill0i0l_dataout : STD_LOGIC; + SIGNAL wire_nill0i0O_dataout : STD_LOGIC; + SIGNAL wire_nill0i1i_dataout : STD_LOGIC; + SIGNAL wire_nill0i1l_dataout : STD_LOGIC; + SIGNAL wire_nill0i1O_dataout : STD_LOGIC; + SIGNAL wire_nill0ii_dataout : STD_LOGIC; + SIGNAL wire_nill0iii_dataout : STD_LOGIC; + SIGNAL wire_nill0iil_dataout : STD_LOGIC; + SIGNAL wire_nill0iiO_dataout : STD_LOGIC; + SIGNAL wire_nill0il_dataout : STD_LOGIC; + SIGNAL wire_nill0ili_dataout : STD_LOGIC; + SIGNAL wire_nill0ill_dataout : STD_LOGIC; + SIGNAL wire_nill0ilO_dataout : STD_LOGIC; + SIGNAL wire_nill0iO_dataout : STD_LOGIC; + SIGNAL wire_nill0iOi_dataout : STD_LOGIC; + SIGNAL wire_nill0iOl_dataout : STD_LOGIC; + SIGNAL wire_nill0iOO_dataout : STD_LOGIC; + SIGNAL wire_nill0l0i_dataout : STD_LOGIC; + SIGNAL wire_nill0l0l_dataout : STD_LOGIC; + SIGNAL wire_nill0l0O_dataout : STD_LOGIC; + SIGNAL wire_nill0l1i_dataout : STD_LOGIC; + SIGNAL wire_nill0l1l_dataout : STD_LOGIC; + SIGNAL wire_nill0l1O_dataout : STD_LOGIC; + SIGNAL wire_nill0li_dataout : STD_LOGIC; + SIGNAL wire_nill0lii_dataout : STD_LOGIC; + SIGNAL wire_nill0lil_dataout : STD_LOGIC; + SIGNAL wire_nill0liO_dataout : STD_LOGIC; + SIGNAL wire_nill0ll_dataout : STD_LOGIC; + SIGNAL wire_nill0lli_dataout : STD_LOGIC; + SIGNAL wire_nill0lll_dataout : STD_LOGIC; + SIGNAL wire_nill0llO_dataout : STD_LOGIC; + SIGNAL wire_nill0lO_dataout : STD_LOGIC; + SIGNAL wire_nill0lOi_dataout : STD_LOGIC; + SIGNAL wire_nill0lOl_dataout : STD_LOGIC; + SIGNAL wire_nill0lOO_dataout : STD_LOGIC; + SIGNAL wire_nill0O0i_dataout : STD_LOGIC; + SIGNAL wire_nill0O0l_dataout : STD_LOGIC; + SIGNAL wire_nill0O0O_dataout : STD_LOGIC; + SIGNAL wire_nill0O1i_dataout : STD_LOGIC; + SIGNAL wire_nill0O1l_dataout : STD_LOGIC; + SIGNAL wire_nill0O1O_dataout : STD_LOGIC; + SIGNAL wire_nill0Oi_dataout : STD_LOGIC; + SIGNAL wire_nill0Oii_dataout : STD_LOGIC; + SIGNAL wire_nill0Oil_dataout : STD_LOGIC; + SIGNAL wire_nill0OiO_dataout : STD_LOGIC; + SIGNAL wire_nill0Ol_dataout : STD_LOGIC; + SIGNAL wire_nill0Oli_dataout : STD_LOGIC; + SIGNAL wire_nill0Oll_dataout : STD_LOGIC; + SIGNAL wire_nill0OlO_dataout : STD_LOGIC; + SIGNAL wire_nill0OO_dataout : STD_LOGIC; + SIGNAL wire_nill0OOi_dataout : STD_LOGIC; + SIGNAL wire_nill0OOl_dataout : STD_LOGIC; + SIGNAL wire_nill0OOO_dataout : STD_LOGIC; + SIGNAL wire_nill100i_dataout : STD_LOGIC; + SIGNAL wire_nill100l_dataout : STD_LOGIC; + SIGNAL wire_nill100O_dataout : STD_LOGIC; + SIGNAL wire_nill101i_dataout : STD_LOGIC; + SIGNAL wire_nill101l_dataout : STD_LOGIC; + SIGNAL wire_nill101O_dataout : STD_LOGIC; + SIGNAL wire_nill10i_dataout : STD_LOGIC; + SIGNAL wire_nill10ii_dataout : STD_LOGIC; + SIGNAL wire_nill10il_dataout : STD_LOGIC; + SIGNAL wire_nill10iO_dataout : STD_LOGIC; + SIGNAL wire_nill10l_dataout : STD_LOGIC; + SIGNAL wire_nill10li_dataout : STD_LOGIC; + SIGNAL wire_nill10ll_dataout : STD_LOGIC; + SIGNAL wire_nill10lO_dataout : STD_LOGIC; + SIGNAL wire_nill10O_dataout : STD_LOGIC; + SIGNAL wire_nill10Oi_dataout : STD_LOGIC; + SIGNAL wire_nill10Ol_dataout : STD_LOGIC; + SIGNAL wire_nill10OO_dataout : STD_LOGIC; + SIGNAL wire_nill110i_dataout : STD_LOGIC; + SIGNAL wire_nill110l_dataout : STD_LOGIC; + SIGNAL wire_nill110O_dataout : STD_LOGIC; + SIGNAL wire_nill111i_dataout : STD_LOGIC; + SIGNAL wire_nill111l_dataout : STD_LOGIC; + SIGNAL wire_nill111O_dataout : STD_LOGIC; + SIGNAL wire_nill11i_dataout : STD_LOGIC; + SIGNAL wire_nill11ii_dataout : STD_LOGIC; + SIGNAL wire_nill11il_dataout : STD_LOGIC; + SIGNAL wire_nill11iO_dataout : STD_LOGIC; + SIGNAL wire_nill11l_dataout : STD_LOGIC; + SIGNAL wire_nill11li_dataout : STD_LOGIC; + SIGNAL wire_nill11ll_dataout : STD_LOGIC; + SIGNAL wire_nill11lO_dataout : STD_LOGIC; + SIGNAL wire_nill11O_dataout : STD_LOGIC; + SIGNAL wire_nill11Oi_dataout : STD_LOGIC; + SIGNAL wire_nill11Ol_dataout : STD_LOGIC; + SIGNAL wire_nill11OO_dataout : STD_LOGIC; + SIGNAL wire_nill1i0i_dataout : STD_LOGIC; + SIGNAL wire_nill1i0l_dataout : STD_LOGIC; + SIGNAL wire_nill1i0O_dataout : STD_LOGIC; + SIGNAL wire_nill1i1i_dataout : STD_LOGIC; + SIGNAL wire_nill1i1l_dataout : STD_LOGIC; + SIGNAL wire_nill1i1O_dataout : STD_LOGIC; + SIGNAL wire_nill1ii_dataout : STD_LOGIC; + SIGNAL wire_nill1iii_dataout : STD_LOGIC; + SIGNAL wire_nill1iil_dataout : STD_LOGIC; + SIGNAL wire_nill1iiO_dataout : STD_LOGIC; + SIGNAL wire_nill1il_dataout : STD_LOGIC; + SIGNAL wire_nill1ili_dataout : STD_LOGIC; + SIGNAL wire_nill1ill_dataout : STD_LOGIC; + SIGNAL wire_nill1ilO_dataout : STD_LOGIC; + SIGNAL wire_nill1iO_dataout : STD_LOGIC; + SIGNAL wire_nill1iOi_dataout : STD_LOGIC; + SIGNAL wire_nill1iOl_dataout : STD_LOGIC; + SIGNAL wire_nill1iOO_dataout : STD_LOGIC; + SIGNAL wire_nill1l0i_dataout : STD_LOGIC; + SIGNAL wire_nill1l0l_dataout : STD_LOGIC; + SIGNAL wire_nill1l0O_dataout : STD_LOGIC; + SIGNAL wire_nill1l1i_dataout : STD_LOGIC; + SIGNAL wire_nill1l1l_dataout : STD_LOGIC; + SIGNAL wire_nill1l1O_dataout : STD_LOGIC; + SIGNAL wire_nill1li_dataout : STD_LOGIC; + SIGNAL wire_nill1lii_dataout : STD_LOGIC; + SIGNAL wire_nill1lil_dataout : STD_LOGIC; + SIGNAL wire_nill1liO_dataout : STD_LOGIC; + SIGNAL wire_nill1ll_dataout : STD_LOGIC; + SIGNAL wire_nill1lli_dataout : STD_LOGIC; + SIGNAL wire_nill1lll_dataout : STD_LOGIC; + SIGNAL wire_nill1llO_dataout : STD_LOGIC; + SIGNAL wire_nill1lO_dataout : STD_LOGIC; + SIGNAL wire_nill1lOi_dataout : STD_LOGIC; + SIGNAL wire_nill1lOl_dataout : STD_LOGIC; + SIGNAL wire_nill1lOO_dataout : STD_LOGIC; + SIGNAL wire_nill1O0i_dataout : STD_LOGIC; + SIGNAL wire_nill1O0l_dataout : STD_LOGIC; + SIGNAL wire_nill1O0O_dataout : STD_LOGIC; + SIGNAL wire_nill1O1i_dataout : STD_LOGIC; + SIGNAL wire_nill1O1l_dataout : STD_LOGIC; + SIGNAL wire_nill1O1O_dataout : STD_LOGIC; + SIGNAL wire_nill1Oi_dataout : STD_LOGIC; + SIGNAL wire_nill1Oii_dataout : STD_LOGIC; + SIGNAL wire_nill1Oil_dataout : STD_LOGIC; + SIGNAL wire_nill1OiO_dataout : STD_LOGIC; + SIGNAL wire_nill1Ol_dataout : STD_LOGIC; + SIGNAL wire_nill1Oli_dataout : STD_LOGIC; + SIGNAL wire_nill1Oll_dataout : STD_LOGIC; + SIGNAL wire_nill1OlO_dataout : STD_LOGIC; + SIGNAL wire_nill1OO_dataout : STD_LOGIC; + SIGNAL wire_nill1OOi_dataout : STD_LOGIC; + SIGNAL wire_nill1OOl_dataout : STD_LOGIC; + SIGNAL wire_nill1OOO_dataout : STD_LOGIC; + SIGNAL wire_nilli00i_dataout : STD_LOGIC; + SIGNAL wire_nilli00l_dataout : STD_LOGIC; + SIGNAL wire_nilli00O_dataout : STD_LOGIC; + SIGNAL wire_nilli01i_dataout : STD_LOGIC; + SIGNAL wire_nilli01l_dataout : STD_LOGIC; + SIGNAL wire_nilli01O_dataout : STD_LOGIC; + SIGNAL wire_nilli0i_dataout : STD_LOGIC; + SIGNAL wire_nilli0ii_dataout : STD_LOGIC; + SIGNAL wire_nilli0il_dataout : STD_LOGIC; + SIGNAL wire_nilli0iO_dataout : STD_LOGIC; + SIGNAL wire_nilli0l_dataout : STD_LOGIC; + SIGNAL wire_nilli0li_dataout : STD_LOGIC; + SIGNAL wire_nilli0ll_dataout : STD_LOGIC; + SIGNAL wire_nilli0lO_dataout : STD_LOGIC; + SIGNAL wire_nilli0O_dataout : STD_LOGIC; + SIGNAL wire_nilli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilli0OO_dataout : STD_LOGIC; + SIGNAL wire_nilli10i_dataout : STD_LOGIC; + SIGNAL wire_nilli10l_dataout : STD_LOGIC; + SIGNAL wire_nilli10O_dataout : STD_LOGIC; + SIGNAL wire_nilli11i_dataout : STD_LOGIC; + SIGNAL wire_nilli11l_dataout : STD_LOGIC; + SIGNAL wire_nilli11O_dataout : STD_LOGIC; + SIGNAL wire_nilli1i_dataout : STD_LOGIC; + SIGNAL wire_nilli1ii_dataout : STD_LOGIC; + SIGNAL wire_nilli1il_dataout : STD_LOGIC; + SIGNAL wire_nilli1iO_dataout : STD_LOGIC; + SIGNAL wire_nilli1l_dataout : STD_LOGIC; + SIGNAL wire_nilli1li_dataout : STD_LOGIC; + SIGNAL wire_nilli1ll_dataout : STD_LOGIC; + SIGNAL wire_nilli1lO_dataout : STD_LOGIC; + SIGNAL wire_nilli1O_dataout : STD_LOGIC; + SIGNAL wire_nilli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nilli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nilli1OO_dataout : STD_LOGIC; + SIGNAL wire_nillii0i_dataout : STD_LOGIC; + SIGNAL wire_nillii0l_dataout : STD_LOGIC; + SIGNAL wire_nillii0O_dataout : STD_LOGIC; + SIGNAL wire_nillii1i_dataout : STD_LOGIC; + SIGNAL wire_nillii1l_dataout : STD_LOGIC; + SIGNAL wire_nillii1O_dataout : STD_LOGIC; + SIGNAL wire_nilliii_dataout : STD_LOGIC; + SIGNAL wire_nilliiii_dataout : STD_LOGIC; + SIGNAL wire_nilliiil_dataout : STD_LOGIC; + SIGNAL wire_nilliiiO_dataout : STD_LOGIC; + SIGNAL wire_nilliil_dataout : STD_LOGIC; + SIGNAL wire_nilliili_dataout : STD_LOGIC; + SIGNAL wire_nilliill_dataout : STD_LOGIC; + SIGNAL wire_nilliilO_dataout : STD_LOGIC; + SIGNAL wire_nilliiO_dataout : STD_LOGIC; + SIGNAL wire_nilliiOi_dataout : STD_LOGIC; + SIGNAL wire_nilliiOl_dataout : STD_LOGIC; + SIGNAL wire_nilliiOO_dataout : STD_LOGIC; + SIGNAL wire_nillil0i_dataout : STD_LOGIC; + SIGNAL wire_nillil0l_dataout : STD_LOGIC; + SIGNAL wire_nillil0O_dataout : STD_LOGIC; + SIGNAL wire_nillil1i_dataout : STD_LOGIC; + SIGNAL wire_nillil1l_dataout : STD_LOGIC; + SIGNAL wire_nillil1O_dataout : STD_LOGIC; + SIGNAL wire_nillili_dataout : STD_LOGIC; + SIGNAL wire_nillilii_dataout : STD_LOGIC; + SIGNAL wire_nillilil_dataout : STD_LOGIC; + SIGNAL wire_nilliliO_dataout : STD_LOGIC; + SIGNAL wire_nillill_dataout : STD_LOGIC; + SIGNAL wire_nillilli_dataout : STD_LOGIC; + SIGNAL wire_nillilll_dataout : STD_LOGIC; + SIGNAL wire_nillillO_dataout : STD_LOGIC; + SIGNAL wire_nillilO_dataout : STD_LOGIC; + SIGNAL wire_nillilOi_dataout : STD_LOGIC; + SIGNAL wire_nillilOl_dataout : STD_LOGIC; + SIGNAL wire_nillilOO_dataout : STD_LOGIC; + SIGNAL wire_nilliO0l_dataout : STD_LOGIC; + SIGNAL wire_nilliO0O_dataout : STD_LOGIC; + SIGNAL wire_nilliO1i_dataout : STD_LOGIC; + SIGNAL wire_nilliO1l_dataout : STD_LOGIC; + SIGNAL wire_nilliO1O_dataout : STD_LOGIC; + SIGNAL wire_nilliOi_dataout : STD_LOGIC; + SIGNAL wire_nilliOii_dataout : STD_LOGIC; + SIGNAL wire_nilliOil_dataout : STD_LOGIC; + SIGNAL wire_nilliOiO_dataout : STD_LOGIC; + SIGNAL wire_nilliOl_dataout : STD_LOGIC; + SIGNAL wire_nilliOli_dataout : STD_LOGIC; + SIGNAL wire_nilliOll_dataout : STD_LOGIC; + SIGNAL wire_nilliOlO_dataout : STD_LOGIC; + SIGNAL wire_nilliOO_dataout : STD_LOGIC; + SIGNAL wire_nilliOOi_dataout : STD_LOGIC; + SIGNAL wire_nilliOOl_dataout : STD_LOGIC; + SIGNAL wire_nilliOOO_dataout : STD_LOGIC; + SIGNAL wire_nilll00i_dataout : STD_LOGIC; + SIGNAL wire_nilll00l_dataout : STD_LOGIC; + SIGNAL wire_nilll00O_dataout : STD_LOGIC; + SIGNAL wire_nilll0i_dataout : STD_LOGIC; + SIGNAL wire_nilll0ii_dataout : STD_LOGIC; + SIGNAL wire_nilll0il_dataout : STD_LOGIC; + SIGNAL wire_nilll0iO_dataout : STD_LOGIC; + SIGNAL wire_nilll0l_dataout : STD_LOGIC; + SIGNAL wire_nilll0li_dataout : STD_LOGIC; + SIGNAL wire_nilll0ll_dataout : STD_LOGIC; + SIGNAL wire_nilll0lO_dataout : STD_LOGIC; + SIGNAL wire_nilll0O_dataout : STD_LOGIC; + SIGNAL wire_nilll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilll0OO_dataout : STD_LOGIC; + SIGNAL wire_nilll10i_dataout : STD_LOGIC; + SIGNAL wire_nilll10l_dataout : STD_LOGIC; + SIGNAL wire_nilll10O_dataout : STD_LOGIC; + SIGNAL wire_nilll11i_dataout : STD_LOGIC; + SIGNAL wire_nilll11l_dataout : STD_LOGIC; + SIGNAL wire_nilll11O_dataout : STD_LOGIC; + SIGNAL wire_nilll1i_dataout : STD_LOGIC; + SIGNAL wire_nilll1ii_dataout : STD_LOGIC; + SIGNAL wire_nilll1il_dataout : STD_LOGIC; + SIGNAL wire_nilll1iO_dataout : STD_LOGIC; + SIGNAL wire_nilll1l_dataout : STD_LOGIC; + SIGNAL wire_nilll1li_dataout : STD_LOGIC; + SIGNAL wire_nilll1ll_dataout : STD_LOGIC; + SIGNAL wire_nilll1lO_dataout : STD_LOGIC; + SIGNAL wire_nilll1O_dataout : STD_LOGIC; + SIGNAL wire_nilll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nillli0i_dataout : STD_LOGIC; + SIGNAL wire_nillli0l_dataout : STD_LOGIC; + SIGNAL wire_nillli0O_dataout : STD_LOGIC; + SIGNAL wire_nillli1i_dataout : STD_LOGIC; + SIGNAL wire_nillli1l_dataout : STD_LOGIC; + SIGNAL wire_nillli1O_dataout : STD_LOGIC; + SIGNAL wire_nilllii_dataout : STD_LOGIC; + SIGNAL wire_nillliii_dataout : STD_LOGIC; + SIGNAL wire_nillliil_dataout : STD_LOGIC; + SIGNAL wire_nillliiO_dataout : STD_LOGIC; + SIGNAL wire_nilllil_dataout : STD_LOGIC; + SIGNAL wire_nilllili_dataout : STD_LOGIC; + SIGNAL wire_nilllill_dataout : STD_LOGIC; + SIGNAL wire_nilllilO_dataout : STD_LOGIC; + SIGNAL wire_nillliO_dataout : STD_LOGIC; + SIGNAL wire_nillliOi_dataout : STD_LOGIC; + SIGNAL wire_nillliOl_dataout : STD_LOGIC; + SIGNAL wire_nillliOO_dataout : STD_LOGIC; + SIGNAL wire_nillll0i_dataout : STD_LOGIC; + SIGNAL wire_nillll0l_dataout : STD_LOGIC; + SIGNAL wire_nillll0O_dataout : STD_LOGIC; + SIGNAL wire_nillll1i_dataout : STD_LOGIC; + SIGNAL wire_nillll1l_dataout : STD_LOGIC; + SIGNAL wire_nillll1O_dataout : STD_LOGIC; + SIGNAL wire_nilllli_dataout : STD_LOGIC; + SIGNAL wire_nillllii_dataout : STD_LOGIC; + SIGNAL wire_nillllil_dataout : STD_LOGIC; + SIGNAL wire_nilllliO_dataout : STD_LOGIC; + SIGNAL wire_nilllll_dataout : STD_LOGIC; + SIGNAL wire_nillllli_dataout : STD_LOGIC; + SIGNAL wire_nillllll_dataout : STD_LOGIC; + SIGNAL wire_nilllllO_dataout : STD_LOGIC; + SIGNAL wire_nillllO_dataout : STD_LOGIC; + SIGNAL wire_nillllOi_dataout : STD_LOGIC; + SIGNAL wire_nillllOl_dataout : STD_LOGIC; + SIGNAL wire_nillllOO_dataout : STD_LOGIC; + SIGNAL wire_nilllO0i_dataout : STD_LOGIC; + SIGNAL wire_nilllO0l_dataout : STD_LOGIC; + SIGNAL wire_nilllO0O_dataout : STD_LOGIC; + SIGNAL wire_nilllO1i_dataout : STD_LOGIC; + SIGNAL wire_nilllO1l_dataout : STD_LOGIC; + SIGNAL wire_nilllO1O_dataout : STD_LOGIC; + SIGNAL wire_nilllOi_dataout : STD_LOGIC; + SIGNAL wire_nilllOii_dataout : STD_LOGIC; + SIGNAL wire_nilllOil_dataout : STD_LOGIC; + SIGNAL wire_nilllOiO_dataout : STD_LOGIC; + SIGNAL wire_nilllOl_dataout : STD_LOGIC; + SIGNAL wire_nilllOli_dataout : STD_LOGIC; + SIGNAL wire_nilllOll_dataout : STD_LOGIC; + SIGNAL wire_nilllOlO_dataout : STD_LOGIC; + SIGNAL wire_nilllOO_dataout : STD_LOGIC; + SIGNAL wire_nilllOOi_dataout : STD_LOGIC; + SIGNAL wire_nilllOOl_dataout : STD_LOGIC; + SIGNAL wire_nilllOOO_dataout : STD_LOGIC; + SIGNAL wire_nillO00i_dataout : STD_LOGIC; + SIGNAL wire_nillO00l_dataout : STD_LOGIC; + SIGNAL wire_nillO00O_dataout : STD_LOGIC; + SIGNAL wire_nillO01i_dataout : STD_LOGIC; + SIGNAL wire_nillO01l_dataout : STD_LOGIC; + SIGNAL wire_nillO01O_dataout : STD_LOGIC; + SIGNAL wire_nillO0i_dataout : STD_LOGIC; + SIGNAL wire_nillO0ii_dataout : STD_LOGIC; + SIGNAL wire_nillO0il_dataout : STD_LOGIC; + SIGNAL wire_nillO0iO_dataout : STD_LOGIC; + SIGNAL wire_nillO0l_dataout : STD_LOGIC; + SIGNAL wire_nillO0li_dataout : STD_LOGIC; + SIGNAL wire_nillO0ll_dataout : STD_LOGIC; + SIGNAL wire_nillO0lO_dataout : STD_LOGIC; + SIGNAL wire_nillO0O_dataout : STD_LOGIC; + SIGNAL wire_nillO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nillO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nillO0OO_dataout : STD_LOGIC; + SIGNAL wire_nillO10i_dataout : STD_LOGIC; + SIGNAL wire_nillO10l_dataout : STD_LOGIC; + SIGNAL wire_nillO10O_dataout : STD_LOGIC; + SIGNAL wire_nillO11i_dataout : STD_LOGIC; + SIGNAL wire_nillO11l_dataout : STD_LOGIC; + SIGNAL wire_nillO11O_dataout : STD_LOGIC; + SIGNAL wire_nillO1i_dataout : STD_LOGIC; + SIGNAL wire_nillO1ii_dataout : STD_LOGIC; + SIGNAL wire_nillO1il_dataout : STD_LOGIC; + SIGNAL wire_nillO1iO_dataout : STD_LOGIC; + SIGNAL wire_nillO1l_dataout : STD_LOGIC; + SIGNAL wire_nillO1li_dataout : STD_LOGIC; + SIGNAL wire_nillO1ll_dataout : STD_LOGIC; + SIGNAL wire_nillO1lO_dataout : STD_LOGIC; + SIGNAL wire_nillO1O_dataout : STD_LOGIC; + SIGNAL wire_nillO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nillO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nillO1OO_dataout : STD_LOGIC; + SIGNAL wire_nillOi0i_dataout : STD_LOGIC; + SIGNAL wire_nillOi0l_dataout : STD_LOGIC; + SIGNAL wire_nillOi0O_dataout : STD_LOGIC; + SIGNAL wire_nillOi1i_dataout : STD_LOGIC; + SIGNAL wire_nillOi1l_dataout : STD_LOGIC; + SIGNAL wire_nillOi1O_dataout : STD_LOGIC; + SIGNAL wire_nillOii_dataout : STD_LOGIC; + SIGNAL wire_nillOiii_dataout : STD_LOGIC; + SIGNAL wire_nillOiil_dataout : STD_LOGIC; + SIGNAL wire_nillOiiO_dataout : STD_LOGIC; + SIGNAL wire_nillOil_dataout : STD_LOGIC; + SIGNAL wire_nillOili_dataout : STD_LOGIC; + SIGNAL wire_nillOill_dataout : STD_LOGIC; + SIGNAL wire_nillOilO_dataout : STD_LOGIC; + SIGNAL wire_nillOiO_dataout : STD_LOGIC; + SIGNAL wire_nillOiOi_dataout : STD_LOGIC; + SIGNAL wire_nillOiOl_dataout : STD_LOGIC; + SIGNAL wire_nillOiOO_dataout : STD_LOGIC; + SIGNAL wire_nillOl0i_dataout : STD_LOGIC; + SIGNAL wire_nillOl0l_dataout : STD_LOGIC; + SIGNAL wire_nillOl0O_dataout : STD_LOGIC; + SIGNAL wire_nillOl1i_dataout : STD_LOGIC; + SIGNAL wire_nillOl1l_dataout : STD_LOGIC; + SIGNAL wire_nillOl1O_dataout : STD_LOGIC; + SIGNAL wire_nillOli_dataout : STD_LOGIC; + SIGNAL wire_nillOlii_dataout : STD_LOGIC; + SIGNAL wire_nillOlil_dataout : STD_LOGIC; + SIGNAL wire_nillOliO_dataout : STD_LOGIC; + SIGNAL wire_nillOll_dataout : STD_LOGIC; + SIGNAL wire_nillOlli_dataout : STD_LOGIC; + SIGNAL wire_nillOlll_dataout : STD_LOGIC; + SIGNAL wire_nillOllO_dataout : STD_LOGIC; + SIGNAL wire_nillOlO_dataout : STD_LOGIC; + SIGNAL wire_nillOlOi_dataout : STD_LOGIC; + SIGNAL wire_nillOlOl_dataout : STD_LOGIC; + SIGNAL wire_nillOlOO_dataout : STD_LOGIC; + SIGNAL wire_nillOO0i_dataout : STD_LOGIC; + SIGNAL wire_nillOO0l_dataout : STD_LOGIC; + SIGNAL wire_nillOO0O_dataout : STD_LOGIC; + SIGNAL wire_nillOO1i_dataout : STD_LOGIC; + SIGNAL wire_nillOO1l_dataout : STD_LOGIC; + SIGNAL wire_nillOO1O_dataout : STD_LOGIC; + SIGNAL wire_nillOOi_dataout : STD_LOGIC; + SIGNAL wire_nillOOii_dataout : STD_LOGIC; + SIGNAL wire_nillOOil_dataout : STD_LOGIC; + SIGNAL wire_nillOOiO_dataout : STD_LOGIC; + SIGNAL wire_nillOOl_dataout : STD_LOGIC; + SIGNAL wire_nillOOli_dataout : STD_LOGIC; + SIGNAL wire_nillOOll_dataout : STD_LOGIC; + SIGNAL wire_nillOOlO_dataout : STD_LOGIC; + SIGNAL wire_nillOOO_dataout : STD_LOGIC; + SIGNAL wire_nillOOOi_dataout : STD_LOGIC; + SIGNAL wire_nillOOOl_dataout : STD_LOGIC; + SIGNAL wire_nillOOOO_dataout : STD_LOGIC; + SIGNAL wire_nilO000i_dataout : STD_LOGIC; + SIGNAL wire_nilO000l_dataout : STD_LOGIC; + SIGNAL wire_nilO000O_dataout : STD_LOGIC; + SIGNAL wire_nilO001i_dataout : STD_LOGIC; + SIGNAL wire_nilO001l_dataout : STD_LOGIC; + SIGNAL wire_nilO001O_dataout : STD_LOGIC; + SIGNAL wire_nilO00i_dataout : STD_LOGIC; + SIGNAL wire_nilO00ii_dataout : STD_LOGIC; + SIGNAL wire_nilO00il_dataout : STD_LOGIC; + SIGNAL wire_nilO00iO_dataout : STD_LOGIC; + SIGNAL wire_nilO00l_dataout : STD_LOGIC; + SIGNAL wire_nilO00li_dataout : STD_LOGIC; + SIGNAL wire_nilO00ll_dataout : STD_LOGIC; + SIGNAL wire_nilO00lO_dataout : STD_LOGIC; + SIGNAL wire_nilO00O_dataout : STD_LOGIC; + SIGNAL wire_nilO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nilO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nilO00OO_dataout : STD_LOGIC; + SIGNAL wire_nilO010i_dataout : STD_LOGIC; + SIGNAL wire_nilO010i_w_lg_w_lg_dataout25163w53440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010i_w_lg_dataout25163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010l_dataout : STD_LOGIC; + SIGNAL wire_nilO010l_w_lg_dataout8971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_dataout : STD_LOGIC; + SIGNAL wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w43350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_w_lg_w_lg_dataout8973w8974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_w_lg_w_lg_dataout8976w8977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_w_lg_w_lg_dataout8970w8972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_w_lg_dataout8973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_w_lg_dataout8976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_w_lg_dataout8970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w54849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO011i_dataout : STD_LOGIC; + SIGNAL wire_nilO011l_dataout : STD_LOGIC; + SIGNAL wire_nilO011l_w_lg_dataout43407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO011O_dataout : STD_LOGIC; + SIGNAL wire_nilO01i_dataout : STD_LOGIC; + SIGNAL wire_nilO01ii_dataout : STD_LOGIC; + SIGNAL wire_nilO01il_dataout : STD_LOGIC; + SIGNAL wire_nilO01iO_dataout : STD_LOGIC; + SIGNAL wire_nilO01l_dataout : STD_LOGIC; + SIGNAL wire_nilO01ll_dataout : STD_LOGIC; + SIGNAL wire_nilO01lO_dataout : STD_LOGIC; + SIGNAL wire_nilO01O_dataout : STD_LOGIC; + SIGNAL wire_nilO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nilO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nilO01OO_dataout : STD_LOGIC; + SIGNAL wire_nilO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nilO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nilO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nilO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nilO0ii_dataout : STD_LOGIC; + SIGNAL wire_nilO0iii_dataout : STD_LOGIC; + SIGNAL wire_nilO0iil_dataout : STD_LOGIC; + SIGNAL wire_nilO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nilO0il_dataout : STD_LOGIC; + SIGNAL wire_nilO0ili_dataout : STD_LOGIC; + SIGNAL wire_nilO0ill_dataout : STD_LOGIC; + SIGNAL wire_nilO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nilO0iO_dataout : STD_LOGIC; + SIGNAL wire_nilO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nilO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nilO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nilO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nilO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nilO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nilO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nilO0li_dataout : STD_LOGIC; + SIGNAL wire_nilO0lii_dataout : STD_LOGIC; + SIGNAL wire_nilO0lil_dataout : STD_LOGIC; + SIGNAL wire_nilO0liO_dataout : STD_LOGIC; + SIGNAL wire_nilO0ll_dataout : STD_LOGIC; + SIGNAL wire_nilO0lli_dataout : STD_LOGIC; + SIGNAL wire_nilO0lll_dataout : STD_LOGIC; + SIGNAL wire_nilO0llO_dataout : STD_LOGIC; + SIGNAL wire_nilO0lO_dataout : STD_LOGIC; + SIGNAL wire_nilO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nilO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nilO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nilO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nilO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nilO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nilO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nilO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nilO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nilO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nilO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nilO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nilO0OO_dataout : STD_LOGIC; + SIGNAL wire_nilO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nilO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nilO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nilO0OOO_w_lg_w_lg_dataout34724w34725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO0OOO_w_lg_dataout34724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilO100i_dataout : STD_LOGIC; + SIGNAL wire_nilO100l_dataout : STD_LOGIC; + SIGNAL wire_nilO100O_dataout : STD_LOGIC; + SIGNAL wire_nilO101i_dataout : STD_LOGIC; + SIGNAL wire_nilO101l_dataout : STD_LOGIC; + SIGNAL wire_nilO101O_dataout : STD_LOGIC; + SIGNAL wire_nilO10i_dataout : STD_LOGIC; + SIGNAL wire_nilO10ii_dataout : STD_LOGIC; + SIGNAL wire_nilO10il_dataout : STD_LOGIC; + SIGNAL wire_nilO10iO_dataout : STD_LOGIC; + SIGNAL wire_nilO10l_dataout : STD_LOGIC; + SIGNAL wire_nilO10li_dataout : STD_LOGIC; + SIGNAL wire_nilO10ll_dataout : STD_LOGIC; + SIGNAL wire_nilO10lO_dataout : STD_LOGIC; + SIGNAL wire_nilO10O_dataout : STD_LOGIC; + SIGNAL wire_nilO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nilO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nilO10OO_dataout : STD_LOGIC; + SIGNAL wire_nilO110i_dataout : STD_LOGIC; + SIGNAL wire_nilO110l_dataout : STD_LOGIC; + SIGNAL wire_nilO110O_dataout : STD_LOGIC; + SIGNAL wire_nilO111i_dataout : STD_LOGIC; + SIGNAL wire_nilO111l_dataout : STD_LOGIC; + SIGNAL wire_nilO111O_dataout : STD_LOGIC; + SIGNAL wire_nilO11i_dataout : STD_LOGIC; + SIGNAL wire_nilO11ii_dataout : STD_LOGIC; + SIGNAL wire_nilO11il_dataout : STD_LOGIC; + SIGNAL wire_nilO11iO_dataout : STD_LOGIC; + SIGNAL wire_nilO11l_dataout : STD_LOGIC; + SIGNAL wire_nilO11li_dataout : STD_LOGIC; + SIGNAL wire_nilO11ll_dataout : STD_LOGIC; + SIGNAL wire_nilO11lO_dataout : STD_LOGIC; + SIGNAL wire_nilO11O_dataout : STD_LOGIC; + SIGNAL wire_nilO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nilO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nilO11OO_dataout : STD_LOGIC; + SIGNAL wire_nilO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nilO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nilO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nilO1ii_dataout : STD_LOGIC; + SIGNAL wire_nilO1iii_dataout : STD_LOGIC; + SIGNAL wire_nilO1iil_dataout : STD_LOGIC; + SIGNAL wire_nilO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nilO1il_dataout : STD_LOGIC; + SIGNAL wire_nilO1ili_dataout : STD_LOGIC; + SIGNAL wire_nilO1ill_dataout : STD_LOGIC; + SIGNAL wire_nilO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nilO1iO_dataout : STD_LOGIC; + SIGNAL wire_nilO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nilO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nilO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nilO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nilO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nilO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nilO1li_dataout : STD_LOGIC; + SIGNAL wire_nilO1lii_dataout : STD_LOGIC; + SIGNAL wire_nilO1lil_dataout : STD_LOGIC; + SIGNAL wire_nilO1liO_dataout : STD_LOGIC; + SIGNAL wire_nilO1ll_dataout : STD_LOGIC; + SIGNAL wire_nilO1lli_dataout : STD_LOGIC; + SIGNAL wire_nilO1lll_dataout : STD_LOGIC; + SIGNAL wire_nilO1llO_dataout : STD_LOGIC; + SIGNAL wire_nilO1lO_dataout : STD_LOGIC; + SIGNAL wire_nilO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nilO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nilO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nilO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nilO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nilO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nilO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nilO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nilO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nilO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nilO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nilO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nilO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nilO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nilO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nilO1OO_dataout : STD_LOGIC; + SIGNAL wire_nilO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nilO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nilO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nilOi00i_dataout : STD_LOGIC; + SIGNAL wire_nilOi00i_w_lg_dataout54077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi00l_dataout : STD_LOGIC; + SIGNAL wire_nilOi00O_dataout : STD_LOGIC; + SIGNAL wire_nilOi00O_w_lg_w_lg_dataout45023w52928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi00O_w_lg_dataout45023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi01i_dataout : STD_LOGIC; + SIGNAL wire_nilOi01l_dataout : STD_LOGIC; + SIGNAL wire_nilOi01O_dataout : STD_LOGIC; + SIGNAL wire_nilOi0i_dataout : STD_LOGIC; + SIGNAL wire_nilOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nilOi0ii_w_lg_w_lg_w_lg_dataout52927w52932w52933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0ii_w_lg_w_lg_dataout52927w52932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0ii_w_lg_dataout52927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0il_dataout : STD_LOGIC; + SIGNAL wire_nilOi0il_w_lg_w_lg_w_lg_dataout44964w52929w52931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0il_w_lg_w_lg_dataout44964w52929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0il_w_lg_w_lg_dataout44964w44965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0il_w_lg_dataout44964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nilOi0iO_w_lg_dataout42932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0l_dataout : STD_LOGIC; + SIGNAL wire_nilOi0li_dataout : STD_LOGIC; + SIGNAL wire_nilOi0li_w_lg_dataout42931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0li_w_lg_dataout54063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nilOi0ll_w_lg_dataout54064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nilOi0lO_w_lg_dataout53094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0O_dataout : STD_LOGIC; + SIGNAL wire_nilOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilOi0Oi_w_lg_dataout53096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilOi0Ol_w_lg_dataout45180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nilOi0OO_w_lg_dataout45178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi10i_dataout : STD_LOGIC; + SIGNAL wire_nilOi10l_dataout : STD_LOGIC; + SIGNAL wire_nilOi10O_dataout : STD_LOGIC; + SIGNAL wire_nilOi11i_dataout : STD_LOGIC; + SIGNAL wire_nilOi11i_w_lg_dataout59400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi11l_dataout : STD_LOGIC; + SIGNAL wire_nilOi11l_w_lg_w_lg_w_lg_dataout43384w43387w43388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi11l_w_lg_w_lg_dataout43384w43387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi11l_w_lg_dataout43384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOi11O_dataout : STD_LOGIC; + SIGNAL wire_nilOi1i_dataout : STD_LOGIC; + SIGNAL wire_nilOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nilOi1il_dataout : STD_LOGIC; + SIGNAL wire_nilOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nilOi1l_dataout : STD_LOGIC; + SIGNAL wire_nilOi1li_dataout : STD_LOGIC; + SIGNAL wire_nilOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nilOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nilOi1O_dataout : STD_LOGIC; + SIGNAL wire_nilOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nilOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nilOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nilOii0i_dataout : STD_LOGIC; + SIGNAL wire_nilOii0i_w_lg_w_lg_w53765w53766w53767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w_lg_w53887w53888w53895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w53765w53766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w53765w53770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w53887w53888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w53887w53901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w53765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w45177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w53887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w53877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w53764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w45176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w53875w53876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w_lg_dataout45173w45175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_w_lg_dataout45173w53875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0i_w_lg_dataout45173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0l_dataout : STD_LOGIC; + SIGNAL wire_nilOii0l_w_lg_dataout53106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii0O_dataout : STD_LOGIC; + SIGNAL wire_nilOii0O_w_lg_dataout53108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii1i_dataout : STD_LOGIC; + SIGNAL wire_nilOii1i_w_lg_dataout53100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii1l_dataout : STD_LOGIC; + SIGNAL wire_nilOii1l_w_lg_dataout53102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOii1O_dataout : STD_LOGIC; + SIGNAL wire_nilOii1O_w_lg_dataout45174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiii_dataout : STD_LOGIC; + SIGNAL wire_nilOiiii_dataout : STD_LOGIC; + SIGNAL wire_nilOiiii_w_lg_dataout53110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiiil_dataout : STD_LOGIC; + SIGNAL wire_nilOiiil_w_lg_dataout53112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nilOiiiO_w_lg_dataout53114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiil_dataout : STD_LOGIC; + SIGNAL wire_nilOiili_dataout : STD_LOGIC; + SIGNAL wire_nilOiili_w_lg_dataout53908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiill_dataout : STD_LOGIC; + SIGNAL wire_nilOiill_w_lg_dataout53906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiilO_dataout : STD_LOGIC; + SIGNAL wire_nilOiilO_w_lg_dataout53905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiiO_dataout : STD_LOGIC; + SIGNAL wire_nilOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nilOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nilOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nilOil0i_dataout : STD_LOGIC; + SIGNAL wire_nilOil0l_dataout : STD_LOGIC; + SIGNAL wire_nilOil0O_dataout : STD_LOGIC; + SIGNAL wire_nilOil1i_dataout : STD_LOGIC; + SIGNAL wire_nilOil1l_dataout : STD_LOGIC; + SIGNAL wire_nilOil1O_dataout : STD_LOGIC; + SIGNAL wire_nilOili_dataout : STD_LOGIC; + SIGNAL wire_nilOilii_dataout : STD_LOGIC; + SIGNAL wire_nilOilil_dataout : STD_LOGIC; + SIGNAL wire_nilOiliO_dataout : STD_LOGIC; + SIGNAL wire_nilOill_dataout : STD_LOGIC; + SIGNAL wire_nilOilli_dataout : STD_LOGIC; + SIGNAL wire_nilOilll_dataout : STD_LOGIC; + SIGNAL wire_nilOillO_dataout : STD_LOGIC; + SIGNAL wire_nilOilO_dataout : STD_LOGIC; + SIGNAL wire_nilOilOi_dataout : STD_LOGIC; + SIGNAL wire_nilOilOl_dataout : STD_LOGIC; + SIGNAL wire_nilOilOl_w_lg_dataout53154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOilOO_dataout : STD_LOGIC; + SIGNAL wire_nilOilOO_w_lg_dataout53156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nilOiO0i_w_lg_dataout53730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nilOiO0l_w_lg_dataout53728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nilOiO0O_w_lg_dataout53726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nilOiO1i_w_lg_dataout53736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nilOiO1l_w_lg_dataout53734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOiO1O_w_lg_dataout53732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOi_dataout : STD_LOGIC; + SIGNAL wire_nilOiOii_dataout : STD_LOGIC; + SIGNAL wire_nilOiOii_w_lg_dataout53724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOil_dataout : STD_LOGIC; + SIGNAL wire_nilOiOil_w_lg_dataout53723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOiOiO_w_lg_dataout49194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOl_dataout : STD_LOGIC; + SIGNAL wire_nilOiOli_dataout : STD_LOGIC; + SIGNAL wire_nilOiOli_w_lg_dataout49192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOll_dataout : STD_LOGIC; + SIGNAL wire_nilOiOll_w_lg_dataout49190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOiOlO_w_lg_w_lg_dataout49188w53619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOlO_w_lg_w_lg_w_lg_dataout49188w53619w53620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOlO_w_lg_dataout49188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOO_dataout : STD_LOGIC; + SIGNAL wire_nilOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOiOOi_w_lg_dataout49186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOiOOl_w_lg_dataout49185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nilOiOOO_w_lg_dataout49183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl00i_dataout : STD_LOGIC; + SIGNAL wire_nilOl00i_w_lg_dataout42840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl00l_dataout : STD_LOGIC; + SIGNAL wire_nilOl00l_w_lg_dataout61592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl00O_dataout : STD_LOGIC; + SIGNAL wire_nilOl00O_w_lg_dataout61590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01i_dataout : STD_LOGIC; + SIGNAL wire_nilOl01i_w42839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01i_w_lg_w_lg_w_lg_dataout42832w42833w42836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01i_w_lg_w_lg_dataout42832w42833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01i_w_lg_dataout42832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01l_dataout : STD_LOGIC; + SIGNAL wire_nilOl01l_w_lg_w_lg_dataout42834w42835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01l_w_lg_dataout42834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01O_dataout : STD_LOGIC; + SIGNAL wire_nilOl01O_w_lg_w_lg_dataout42837w42838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl01O_w_lg_dataout42837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0i_dataout : STD_LOGIC; + SIGNAL wire_nilOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nilOl0ii_w_lg_dataout61588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0il_dataout : STD_LOGIC; + SIGNAL wire_nilOl0il_w_lg_dataout61586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nilOl0iO_w_lg_dataout61584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0l_dataout : STD_LOGIC; + SIGNAL wire_nilOl0li_dataout : STD_LOGIC; + SIGNAL wire_nilOl0li_w_lg_dataout61582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nilOl0ll_w_lg_dataout61580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nilOl0lO_w_lg_dataout61578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0O_dataout : STD_LOGIC; + SIGNAL wire_nilOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilOl0Oi_w_lg_dataout61576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilOl0Ol_w_lg_dataout61574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nilOl0OO_w_lg_dataout61572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl10i_dataout : STD_LOGIC; + SIGNAL wire_nilOl10i_w_lg_dataout49172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl10l_dataout : STD_LOGIC; + SIGNAL wire_nilOl10l_w_lg_dataout49170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl10O_dataout : STD_LOGIC; + SIGNAL wire_nilOl10O_w_lg_w_lg_dataout49168w54114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl10O_w_lg_dataout54117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl10O_w_lg_dataout49168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl11i_dataout : STD_LOGIC; + SIGNAL wire_nilOl11i_w_lg_dataout49181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl11l_dataout : STD_LOGIC; + SIGNAL wire_nilOl11l_w_lg_dataout49175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl11O_dataout : STD_LOGIC; + SIGNAL wire_nilOl11O_w_lg_dataout49178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1i_dataout : STD_LOGIC; + SIGNAL wire_nilOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nilOl1ii_w_lg_dataout49166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1il_dataout : STD_LOGIC; + SIGNAL wire_nilOl1il_w_lg_dataout43280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nilOl1iO_w_lg_dataout43278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1l_dataout : STD_LOGIC; + SIGNAL wire_nilOl1li_dataout : STD_LOGIC; + SIGNAL wire_nilOl1li_w_lg_dataout43291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nilOl1ll_w_lg_dataout43266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nilOl1lO_w53755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w44969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w44967w44968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w_lg_w_lg_dataout43274w53200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w_lg_w_lg_dataout43274w44967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w_lg_dataout53761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1lO_w_lg_dataout43274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1O_dataout : STD_LOGIC; + SIGNAL wire_nilOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nilOl1Oi_w_lg_w_lg_w53632w53637w53638w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_w_lg_dataout53615w53616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_dataout53937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_dataout43272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_w_lg_dataout43272w53625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_w_lg_w_lg_dataout43272w53625w53630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w53632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_w53632w53637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_dataout53615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Oi_w_lg_dataout53622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nilOl1Ol_w_lg_w_lg_w_lg_dataout53633w53635w53636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_w_lg_w_lg_dataout43262w45182w45183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_w_lg_dataout53633w53635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_w_lg_dataout43262w45182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_w_lg_dataout43262w53611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_w_lg_dataout43262w53631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_dataout53614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_dataout53633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1Ol_w_lg_dataout43262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nilOl1OO_w_lg_w49173w49174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w49173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_w43303w49167w49169w49171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w43303w49167w49169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w43303w49167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w43303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43276w43301w43302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43276w43301w43311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43296w43297w43298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_w43284w43285w43313w43321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_w43284w43290w43292w43293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w43275w43276w43301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w43275w43276w43277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w43275w43296w43297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w43284w43285w43313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w43284w43285w43286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w43284w43290w43292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w43275w43276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w43275w43296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w43284w43285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w43284w43290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w43275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w43265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w43284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w43270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43268w43283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43268w43269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_dataout43261w43263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_w_lg_dataout43261w43268w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOl1OO_w_lg_dataout43261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOli0i_dataout : STD_LOGIC; + SIGNAL wire_nilOli0i_w_lg_dataout61565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOli0l_dataout : STD_LOGIC; + SIGNAL wire_nilOli0l_w_lg_dataout61563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOli0O_dataout : STD_LOGIC; + SIGNAL wire_nilOli0O_w_lg_dataout61561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOli1i_dataout : STD_LOGIC; + SIGNAL wire_nilOli1i_w_lg_dataout61571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOli1l_dataout : STD_LOGIC; + SIGNAL wire_nilOli1l_w_lg_dataout61569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOli1O_dataout : STD_LOGIC; + SIGNAL wire_nilOli1O_w_lg_dataout61567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOlii_dataout : STD_LOGIC; + SIGNAL wire_nilOliii_dataout : STD_LOGIC; + SIGNAL wire_nilOliii_w_lg_dataout61559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOliil_dataout : STD_LOGIC; + SIGNAL wire_nilOliil_w_lg_dataout61557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOliiO_dataout : STD_LOGIC; + SIGNAL wire_nilOliiO_w_lg_dataout61556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOlil_dataout : STD_LOGIC; + SIGNAL wire_nilOlili_dataout : STD_LOGIC; + SIGNAL wire_nilOlili_w_lg_dataout42893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOlill_dataout : STD_LOGIC; + SIGNAL wire_nilOlill_w_lg_dataout42891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOlilO_dataout : STD_LOGIC; + SIGNAL wire_nilOlilO_w_lg_dataout42890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOliO_dataout : STD_LOGIC; + SIGNAL wire_nilOliOi_dataout : STD_LOGIC; + SIGNAL wire_nilOliOi_w_lg_dataout61595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOliOl_dataout : STD_LOGIC; + SIGNAL wire_nilOliOl_w_lg_dataout61594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOliOO_dataout : STD_LOGIC; + SIGNAL wire_nilOll0i_dataout : STD_LOGIC; + SIGNAL wire_nilOll0i_w_lg_w_lg_dataout9845w9846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOll0i_w_lg_dataout9842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOll0i_w_lg_dataout9845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOll0l_dataout : STD_LOGIC; + SIGNAL wire_nilOll0l_w_lg_dataout54086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOll0O_dataout : STD_LOGIC; + SIGNAL wire_nilOll1i_dataout : STD_LOGIC; + SIGNAL wire_nilOll1l_dataout : STD_LOGIC; + SIGNAL wire_nilOll1l_w_lg_dataout9843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOll1O_dataout : STD_LOGIC; + SIGNAL wire_nilOll1O_w_lg_dataout9841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOlli_dataout : STD_LOGIC; + SIGNAL wire_nilOllii_dataout : STD_LOGIC; + SIGNAL wire_nilOllil_dataout : STD_LOGIC; + SIGNAL wire_nilOlliO_dataout : STD_LOGIC; + SIGNAL wire_nilOlll_dataout : STD_LOGIC; + SIGNAL wire_nilOllli_dataout : STD_LOGIC; + SIGNAL wire_nilOllll_dataout : STD_LOGIC; + SIGNAL wire_nilOlllO_dataout : STD_LOGIC; + SIGNAL wire_nilOllO_dataout : STD_LOGIC; + SIGNAL wire_nilOllOi_dataout : STD_LOGIC; + SIGNAL wire_nilOllOl_dataout : STD_LOGIC; + SIGNAL wire_nilOllOO_dataout : STD_LOGIC; + SIGNAL wire_nilOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nilOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nilOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nilOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nilOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nilOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOlOi_dataout : STD_LOGIC; + SIGNAL wire_nilOlOii_dataout : STD_LOGIC; + SIGNAL wire_nilOlOil_dataout : STD_LOGIC; + SIGNAL wire_nilOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOlOl_dataout : STD_LOGIC; + SIGNAL wire_nilOlOli_dataout : STD_LOGIC; + SIGNAL wire_nilOlOll_dataout : STD_LOGIC; + SIGNAL wire_nilOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOlOO_dataout : STD_LOGIC; + SIGNAL wire_nilOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nilOO00i_dataout : STD_LOGIC; + SIGNAL wire_nilOO00l_dataout : STD_LOGIC; + SIGNAL wire_nilOO00O_dataout : STD_LOGIC; + SIGNAL wire_nilOO00O_w_lg_dataout47986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO01i_dataout : STD_LOGIC; + SIGNAL wire_nilOO01i_w_lg_dataout9215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO01l_dataout : STD_LOGIC; + SIGNAL wire_nilOO01l_w_lg_dataout295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO01O_dataout : STD_LOGIC; + SIGNAL wire_nilOO01O_w_lg_dataout60235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0i_dataout : STD_LOGIC; + SIGNAL wire_nilOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nilOO0ii_w_lg_dataout44003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0ii_w_lg_dataout43998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0ii_w_lg_dataout43403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0il_dataout : STD_LOGIC; + SIGNAL wire_nilOO0il_w_lg_dataout44112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nilOO0l_dataout : STD_LOGIC; + SIGNAL wire_nilOO0li_dataout : STD_LOGIC; + SIGNAL wire_nilOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nilOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nilOO0O_dataout : STD_LOGIC; + SIGNAL wire_nilOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nilOO0Oi_w_lg_w_lg_w_lg_dataout29675w29678w29679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0Oi_w_lg_w_lg_dataout29675w29678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0Oi_w_lg_dataout29675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nilOO0Ol_w_lg_dataout43358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nilOO0OO_w_lg_dataout43356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO10i_dataout : STD_LOGIC; + SIGNAL wire_nilOO10l_dataout : STD_LOGIC; + SIGNAL wire_nilOO10O_dataout : STD_LOGIC; + SIGNAL wire_nilOO11i_dataout : STD_LOGIC; + SIGNAL wire_nilOO11i_w_lg_dataout29686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO11l_dataout : STD_LOGIC; + SIGNAL wire_nilOO11l_w_lg_dataout29684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO11O_dataout : STD_LOGIC; + SIGNAL wire_nilOO1i_dataout : STD_LOGIC; + SIGNAL wire_nilOO1il_dataout : STD_LOGIC; + SIGNAL wire_nilOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nilOO1l_dataout : STD_LOGIC; + SIGNAL wire_nilOO1li_dataout : STD_LOGIC; + SIGNAL wire_nilOO1li_w_lg_dataout43976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nilOO1ll_w_lg_dataout43968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nilOO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nilOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nilOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nilOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nilOOi0i_w_lg_dataout44011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nilOOi0l_w_lg_dataout43900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nilOOi0O_w_lg_dataout45195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nilOOi1i_w_lg_dataout43363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOi1i_w_lg_dataout43355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nilOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nilOOi1O_w_lg_w_lg_dataout29676w29677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOi1O_w_lg_dataout29667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOi1O_w_lg_dataout29676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOii_dataout : STD_LOGIC; + SIGNAL wire_nilOOiii_dataout : STD_LOGIC; + SIGNAL wire_nilOOiii_w_lg_dataout45038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOiii_w_lg_dataout45502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOiil_dataout : STD_LOGIC; + SIGNAL wire_nilOOiil_w_lg_dataout45193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nilOOiiO_w_lg_dataout45191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOil_dataout : STD_LOGIC; + SIGNAL wire_nilOOili_dataout : STD_LOGIC; + SIGNAL wire_nilOOili_w_lg_dataout45189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOill_dataout : STD_LOGIC; + SIGNAL wire_nilOOill_w_lg_dataout45188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOill_w_lg_dataout43255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOilO_dataout : STD_LOGIC; + SIGNAL wire_nilOOilO_w_lg_dataout45039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOilO_w_lg_dataout45501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nilOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nilOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nilOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nilOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nilOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nilOOli_dataout : STD_LOGIC; + SIGNAL wire_nilOOlii_dataout : STD_LOGIC; + SIGNAL wire_nilOOlil_dataout : STD_LOGIC; + SIGNAL wire_nilOOliO_dataout : STD_LOGIC; + SIGNAL wire_nilOOll_dataout : STD_LOGIC; + SIGNAL wire_nilOOlli_dataout : STD_LOGIC; + SIGNAL wire_nilOOlll_dataout : STD_LOGIC; + SIGNAL wire_nilOOllO_dataout : STD_LOGIC; + SIGNAL wire_nilOOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nilOOO0i_w_lg_dataout60194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOO0i_w_lg_dataout54084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOO0i_w_lg_w_lg_dataout54084w54085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOO0i_w_lg_dataout47830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nilOOO0l_w_lg_dataout59507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nilOOO0O_w_lg_dataout59505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nilOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nilOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nilOOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOOii_dataout : STD_LOGIC; + SIGNAL wire_nilOOOii_w_lg_dataout59503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOil_dataout : STD_LOGIC; + SIGNAL wire_nilOOOil_w_lg_dataout59501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nilOOOiO_w_lg_dataout59499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOOli_dataout : STD_LOGIC; + SIGNAL wire_nilOOOli_w_lg_dataout59497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOll_dataout : STD_LOGIC; + SIGNAL wire_nilOOOll_w_lg_dataout59496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nilOOOlO_w_lg_dataout42845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nilOOOOi_w_lg_dataout42849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nilOOOOl_w_lg_dataout42853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nilOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nilOOOOO_w_lg_dataout42857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO000i_dataout : STD_LOGIC; + SIGNAL wire_niO000l_dataout : STD_LOGIC; + SIGNAL wire_niO000O_dataout : STD_LOGIC; + SIGNAL wire_niO0010l_dataout : STD_LOGIC; + SIGNAL wire_niO0011l_dataout : STD_LOGIC; + SIGNAL wire_niO0011O_dataout : STD_LOGIC; + SIGNAL wire_niO001i_dataout : STD_LOGIC; + SIGNAL wire_niO001iO_dataout : STD_LOGIC; + SIGNAL wire_niO001l_dataout : STD_LOGIC; + SIGNAL wire_niO001O_dataout : STD_LOGIC; + SIGNAL wire_niO00ii_dataout : STD_LOGIC; + SIGNAL wire_niO00il_dataout : STD_LOGIC; + SIGNAL wire_niO00iO_dataout : STD_LOGIC; + SIGNAL wire_niO00li_dataout : STD_LOGIC; + SIGNAL wire_niO00ll_dataout : STD_LOGIC; + SIGNAL wire_niO00lO_dataout : STD_LOGIC; + SIGNAL wire_niO00Oi_dataout : STD_LOGIC; + SIGNAL wire_niO00Oii_dataout : STD_LOGIC; + SIGNAL wire_niO00Oil_dataout : STD_LOGIC; + SIGNAL wire_niO00OiO_dataout : STD_LOGIC; + SIGNAL wire_niO00Ol_dataout : STD_LOGIC; + SIGNAL wire_niO00Oli_dataout : STD_LOGIC; + SIGNAL wire_niO00Oll_dataout : STD_LOGIC; + SIGNAL wire_niO00OlO_dataout : STD_LOGIC; + SIGNAL wire_niO00OO_dataout : STD_LOGIC; + SIGNAL wire_niO00OOi_dataout : STD_LOGIC; + SIGNAL wire_niO00OOl_dataout : STD_LOGIC; + SIGNAL wire_niO00OOO_dataout : STD_LOGIC; + SIGNAL wire_niO0101l_dataout : STD_LOGIC; + SIGNAL wire_niO010i_dataout : STD_LOGIC; + SIGNAL wire_niO010l_dataout : STD_LOGIC; + SIGNAL wire_niO010O_dataout : STD_LOGIC; + SIGNAL wire_niO010Oi_dataout : STD_LOGIC; + SIGNAL wire_niO011i_dataout : STD_LOGIC; + SIGNAL wire_niO011l_dataout : STD_LOGIC; + SIGNAL wire_niO011O_dataout : STD_LOGIC; + SIGNAL wire_niO011Oi_dataout : STD_LOGIC; + SIGNAL wire_niO01i1l_dataout : STD_LOGIC; + SIGNAL wire_niO01ii_dataout : STD_LOGIC; + SIGNAL wire_niO01il_dataout : STD_LOGIC; + SIGNAL wire_niO01iO_dataout : STD_LOGIC; + SIGNAL wire_niO01iOO_dataout : STD_LOGIC; + SIGNAL wire_niO01l0i_dataout : STD_LOGIC; + SIGNAL wire_niO01l0O_dataout : STD_LOGIC; + SIGNAL wire_niO01li_dataout : STD_LOGIC; + SIGNAL wire_niO01lil_dataout : STD_LOGIC; + SIGNAL wire_niO01ll_dataout : STD_LOGIC; + SIGNAL wire_niO01lO_dataout : STD_LOGIC; + SIGNAL wire_niO01lOO_dataout : STD_LOGIC; + SIGNAL wire_niO01O0O_dataout : STD_LOGIC; + SIGNAL wire_niO01Oi_dataout : STD_LOGIC; + SIGNAL wire_niO01Oil_dataout : STD_LOGIC; + SIGNAL wire_niO01Ol_dataout : STD_LOGIC; + SIGNAL wire_niO01Oli_dataout : STD_LOGIC; + SIGNAL wire_niO01OO_dataout : STD_LOGIC; + SIGNAL wire_niO01OOO_dataout : STD_LOGIC; + SIGNAL wire_niO0i00i_dataout : STD_LOGIC; + SIGNAL wire_niO0i00l_dataout : STD_LOGIC; + SIGNAL wire_niO0i00O_dataout : STD_LOGIC; + SIGNAL wire_niO0i01i_dataout : STD_LOGIC; + SIGNAL wire_niO0i01l_dataout : STD_LOGIC; + SIGNAL wire_niO0i01O_dataout : STD_LOGIC; + SIGNAL wire_niO0i0i_dataout : STD_LOGIC; + SIGNAL wire_niO0i0ii_dataout : STD_LOGIC; + SIGNAL wire_niO0i0il_dataout : STD_LOGIC; + SIGNAL wire_niO0i0iO_dataout : STD_LOGIC; + SIGNAL wire_niO0i0l_dataout : STD_LOGIC; + SIGNAL wire_niO0i0li_dataout : STD_LOGIC; + SIGNAL wire_niO0i0ll_dataout : STD_LOGIC; + SIGNAL wire_niO0i0lO_dataout : STD_LOGIC; + SIGNAL wire_niO0i0O_dataout : STD_LOGIC; + SIGNAL wire_niO0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0i0OO_dataout : STD_LOGIC; + SIGNAL wire_niO0i10i_dataout : STD_LOGIC; + SIGNAL wire_niO0i10l_dataout : STD_LOGIC; + SIGNAL wire_niO0i10O_dataout : STD_LOGIC; + SIGNAL wire_niO0i11i_dataout : STD_LOGIC; + SIGNAL wire_niO0i11l_dataout : STD_LOGIC; + SIGNAL wire_niO0i11O_dataout : STD_LOGIC; + SIGNAL wire_niO0i1i_dataout : STD_LOGIC; + SIGNAL wire_niO0i1ii_dataout : STD_LOGIC; + SIGNAL wire_niO0i1il_dataout : STD_LOGIC; + SIGNAL wire_niO0i1iO_dataout : STD_LOGIC; + SIGNAL wire_niO0i1l_dataout : STD_LOGIC; + SIGNAL wire_niO0i1li_dataout : STD_LOGIC; + SIGNAL wire_niO0i1ll_dataout : STD_LOGIC; + SIGNAL wire_niO0i1lO_dataout : STD_LOGIC; + SIGNAL wire_niO0i1O_dataout : STD_LOGIC; + SIGNAL wire_niO0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0i1OO_dataout : STD_LOGIC; + SIGNAL wire_niO0ii0i_dataout : STD_LOGIC; + SIGNAL wire_niO0ii0l_dataout : STD_LOGIC; + SIGNAL wire_niO0ii0O_dataout : STD_LOGIC; + SIGNAL wire_niO0ii1i_dataout : STD_LOGIC; + SIGNAL wire_niO0ii1l_dataout : STD_LOGIC; + SIGNAL wire_niO0ii1O_dataout : STD_LOGIC; + SIGNAL wire_niO0iii_dataout : STD_LOGIC; + SIGNAL wire_niO0iiii_dataout : STD_LOGIC; + SIGNAL wire_niO0iiil_dataout : STD_LOGIC; + SIGNAL wire_niO0iiiO_dataout : STD_LOGIC; + SIGNAL wire_niO0iil_dataout : STD_LOGIC; + SIGNAL wire_niO0iili_dataout : STD_LOGIC; + SIGNAL wire_niO0iill_dataout : STD_LOGIC; + SIGNAL wire_niO0iilO_dataout : STD_LOGIC; + SIGNAL wire_niO0iiO_dataout : STD_LOGIC; + SIGNAL wire_niO0iiOi_dataout : STD_LOGIC; + SIGNAL wire_niO0iiOl_dataout : STD_LOGIC; + SIGNAL wire_niO0iiOO_dataout : STD_LOGIC; + SIGNAL wire_niO0il0i_dataout : STD_LOGIC; + SIGNAL wire_niO0il0l_dataout : STD_LOGIC; + SIGNAL wire_niO0il0O_dataout : STD_LOGIC; + SIGNAL wire_niO0il1i_dataout : STD_LOGIC; + SIGNAL wire_niO0il1l_dataout : STD_LOGIC; + SIGNAL wire_niO0il1O_dataout : STD_LOGIC; + SIGNAL wire_niO0ili_dataout : STD_LOGIC; + SIGNAL wire_niO0ilii_dataout : STD_LOGIC; + SIGNAL wire_niO0ilil_dataout : STD_LOGIC; + SIGNAL wire_niO0iliO_dataout : STD_LOGIC; + SIGNAL wire_niO0ill_dataout : STD_LOGIC; + SIGNAL wire_niO0illi_dataout : STD_LOGIC; + SIGNAL wire_niO0illl_dataout : STD_LOGIC; + SIGNAL wire_niO0illO_dataout : STD_LOGIC; + SIGNAL wire_niO0ilO_dataout : STD_LOGIC; + SIGNAL wire_niO0ilOi_dataout : STD_LOGIC; + SIGNAL wire_niO0ilOl_dataout : STD_LOGIC; + SIGNAL wire_niO0ilOO_dataout : STD_LOGIC; + SIGNAL wire_niO0iO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0iO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0iO0O_dataout : STD_LOGIC; + SIGNAL wire_niO0iO1i_dataout : STD_LOGIC; + SIGNAL wire_niO0iO1l_dataout : STD_LOGIC; + SIGNAL wire_niO0iO1O_dataout : STD_LOGIC; + SIGNAL wire_niO0iOi_dataout : STD_LOGIC; + SIGNAL wire_niO0iOii_dataout : STD_LOGIC; + SIGNAL wire_niO0iOil_dataout : STD_LOGIC; + SIGNAL wire_niO0iOiO_dataout : STD_LOGIC; + SIGNAL wire_niO0iOl_dataout : STD_LOGIC; + SIGNAL wire_niO0iOli_dataout : STD_LOGIC; + SIGNAL wire_niO0iOll_dataout : STD_LOGIC; + SIGNAL wire_niO0iOlO_dataout : STD_LOGIC; + SIGNAL wire_niO0iOO_dataout : STD_LOGIC; + SIGNAL wire_niO0iOOi_dataout : STD_LOGIC; + SIGNAL wire_niO0iOOl_dataout : STD_LOGIC; + SIGNAL wire_niO0iOOO_dataout : STD_LOGIC; + SIGNAL wire_niO0l00i_dataout : STD_LOGIC; + SIGNAL wire_niO0l00l_dataout : STD_LOGIC; + SIGNAL wire_niO0l00O_dataout : STD_LOGIC; + SIGNAL wire_niO0l01i_dataout : STD_LOGIC; + SIGNAL wire_niO0l01l_dataout : STD_LOGIC; + SIGNAL wire_niO0l01O_dataout : STD_LOGIC; + SIGNAL wire_niO0l0i_dataout : STD_LOGIC; + SIGNAL wire_niO0l0ii_dataout : STD_LOGIC; + SIGNAL wire_niO0l0il_dataout : STD_LOGIC; + SIGNAL wire_niO0l0iO_dataout : STD_LOGIC; + SIGNAL wire_niO0l0l_dataout : STD_LOGIC; + SIGNAL wire_niO0l0O_dataout : STD_LOGIC; + SIGNAL wire_niO0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0l0OO_dataout : STD_LOGIC; + SIGNAL wire_niO0l10i_dataout : STD_LOGIC; + SIGNAL wire_niO0l10l_dataout : STD_LOGIC; + SIGNAL wire_niO0l10O_dataout : STD_LOGIC; + SIGNAL wire_niO0l11i_dataout : STD_LOGIC; + SIGNAL wire_niO0l11l_dataout : STD_LOGIC; + SIGNAL wire_niO0l11O_dataout : STD_LOGIC; + SIGNAL wire_niO0l1i_dataout : STD_LOGIC; + SIGNAL wire_niO0l1ii_dataout : STD_LOGIC; + SIGNAL wire_niO0l1il_dataout : STD_LOGIC; + SIGNAL wire_niO0l1iO_dataout : STD_LOGIC; + SIGNAL wire_niO0l1l_dataout : STD_LOGIC; + SIGNAL wire_niO0l1li_dataout : STD_LOGIC; + SIGNAL wire_niO0l1ll_dataout : STD_LOGIC; + SIGNAL wire_niO0l1lO_dataout : STD_LOGIC; + SIGNAL wire_niO0l1O_dataout : STD_LOGIC; + SIGNAL wire_niO0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0l1OO_dataout : STD_LOGIC; + SIGNAL wire_niO0li0i_dataout : STD_LOGIC; + SIGNAL wire_niO0li0l_dataout : STD_LOGIC; + SIGNAL wire_niO0li1i_dataout : STD_LOGIC; + SIGNAL wire_niO0li1l_dataout : STD_LOGIC; + SIGNAL wire_niO0li1O_dataout : STD_LOGIC; + SIGNAL wire_niO0lii_dataout : STD_LOGIC; + SIGNAL wire_niO0lil_dataout : STD_LOGIC; + SIGNAL wire_niO0liO_dataout : STD_LOGIC; + SIGNAL wire_niO0lli_dataout : STD_LOGIC; + SIGNAL wire_niO0lll_dataout : STD_LOGIC; + SIGNAL wire_niO0llO_dataout : STD_LOGIC; + SIGNAL wire_niO0lOi_dataout : STD_LOGIC; + SIGNAL wire_niO0lOl_dataout : STD_LOGIC; + SIGNAL wire_niO0lOO_dataout : STD_LOGIC; + SIGNAL wire_niO0lOOO_dataout : STD_LOGIC; + SIGNAL wire_niO0O00i_dataout : STD_LOGIC; + SIGNAL wire_niO0O00l_dataout : STD_LOGIC; + SIGNAL wire_niO0O00O_dataout : STD_LOGIC; + SIGNAL wire_niO0O01i_dataout : STD_LOGIC; + SIGNAL wire_niO0O01l_dataout : STD_LOGIC; + SIGNAL wire_niO0O01O_dataout : STD_LOGIC; + SIGNAL wire_niO0O0i_dataout : STD_LOGIC; + SIGNAL wire_niO0O0ii_dataout : STD_LOGIC; + SIGNAL wire_niO0O0il_dataout : STD_LOGIC; + SIGNAL wire_niO0O0iO_dataout : STD_LOGIC; + SIGNAL wire_niO0O0l_dataout : STD_LOGIC; + SIGNAL wire_niO0O0li_dataout : STD_LOGIC; + SIGNAL wire_niO0O0ll_dataout : STD_LOGIC; + SIGNAL wire_niO0O0lO_dataout : STD_LOGIC; + SIGNAL wire_niO0O0O_dataout : STD_LOGIC; + SIGNAL wire_niO0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0O0OO_dataout : STD_LOGIC; + SIGNAL wire_niO0O10i_dataout : STD_LOGIC; + SIGNAL wire_niO0O10l_dataout : STD_LOGIC; + SIGNAL wire_niO0O10O_dataout : STD_LOGIC; + SIGNAL wire_niO0O11i_dataout : STD_LOGIC; + SIGNAL wire_niO0O11l_dataout : STD_LOGIC; + SIGNAL wire_niO0O11O_dataout : STD_LOGIC; + SIGNAL wire_niO0O1i_dataout : STD_LOGIC; + SIGNAL wire_niO0O1ii_dataout : STD_LOGIC; + SIGNAL wire_niO0O1il_dataout : STD_LOGIC; + SIGNAL wire_niO0O1iO_dataout : STD_LOGIC; + SIGNAL wire_niO0O1l_dataout : STD_LOGIC; + SIGNAL wire_niO0O1li_dataout : STD_LOGIC; + SIGNAL wire_niO0O1ll_dataout : STD_LOGIC; + SIGNAL wire_niO0O1lO_dataout : STD_LOGIC; + SIGNAL wire_niO0O1O_dataout : STD_LOGIC; + SIGNAL wire_niO0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO0O1OO_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_niO0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_niO0Oii_dataout : STD_LOGIC; + SIGNAL wire_niO0Oiii_dataout : STD_LOGIC; + SIGNAL wire_niO0Oiil_dataout : STD_LOGIC; + SIGNAL wire_niO0OiiO_dataout : STD_LOGIC; + SIGNAL wire_niO0Oil_dataout : STD_LOGIC; + SIGNAL wire_niO0Oili_dataout : STD_LOGIC; + SIGNAL wire_niO0Oill_dataout : STD_LOGIC; + SIGNAL wire_niO0OilO_dataout : STD_LOGIC; + SIGNAL wire_niO0OiO_dataout : STD_LOGIC; + SIGNAL wire_niO0OiOi_dataout : STD_LOGIC; + SIGNAL wire_niO0OiOl_dataout : STD_LOGIC; + SIGNAL wire_niO0OiOO_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_niO0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_niO0Oli_dataout : STD_LOGIC; + SIGNAL wire_niO0Olii_dataout : STD_LOGIC; + SIGNAL wire_niO0Olil_dataout : STD_LOGIC; + SIGNAL wire_niO0OliO_dataout : STD_LOGIC; + SIGNAL wire_niO0Oll_dataout : STD_LOGIC; + SIGNAL wire_niO0Olli_dataout : STD_LOGIC; + SIGNAL wire_niO0Olll_dataout : STD_LOGIC; + SIGNAL wire_niO0OllO_dataout : STD_LOGIC; + SIGNAL wire_niO0OlO_dataout : STD_LOGIC; + SIGNAL wire_niO0OlOi_dataout : STD_LOGIC; + SIGNAL wire_niO0OlOl_dataout : STD_LOGIC; + SIGNAL wire_niO0OlOO_dataout : STD_LOGIC; + SIGNAL wire_niO0OO0i_dataout : STD_LOGIC; + SIGNAL wire_niO0OO0l_dataout : STD_LOGIC; + SIGNAL wire_niO0OO0O_dataout : STD_LOGIC; + SIGNAL wire_niO0OO1i_dataout : STD_LOGIC; + SIGNAL wire_niO0OO1l_dataout : STD_LOGIC; + SIGNAL wire_niO0OO1O_dataout : STD_LOGIC; + SIGNAL wire_niO0OOi_dataout : STD_LOGIC; + SIGNAL wire_niO0OOii_dataout : STD_LOGIC; + SIGNAL wire_niO0OOil_dataout : STD_LOGIC; + SIGNAL wire_niO0OOiO_dataout : STD_LOGIC; + SIGNAL wire_niO0OOl_dataout : STD_LOGIC; + SIGNAL wire_niO0OOli_dataout : STD_LOGIC; + SIGNAL wire_niO0OOll_dataout : STD_LOGIC; + SIGNAL wire_niO0OOlO_dataout : STD_LOGIC; + SIGNAL wire_niO0OOO_dataout : STD_LOGIC; + SIGNAL wire_niO0OOOi_dataout : STD_LOGIC; + SIGNAL wire_niO1000i_dataout : STD_LOGIC; + SIGNAL wire_niO1000i_w_lg_dataout15784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1000l_dataout : STD_LOGIC; + SIGNAL wire_niO1000l_w_lg_dataout15782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1000O_dataout : STD_LOGIC; + SIGNAL wire_niO1000O_w_lg_dataout15830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1001i_dataout : STD_LOGIC; + SIGNAL wire_niO1001i_w_lg_dataout19798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1001l_dataout : STD_LOGIC; + SIGNAL wire_niO1001l_w_lg_dataout27506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1001O_dataout : STD_LOGIC; + SIGNAL wire_niO1001O_w_lg_dataout15432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100i_dataout : STD_LOGIC; + SIGNAL wire_niO100ii_dataout : STD_LOGIC; + SIGNAL wire_niO100ii_w_lg_dataout15808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100il_dataout : STD_LOGIC; + SIGNAL wire_niO100il_w_lg_dataout15841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100iO_dataout : STD_LOGIC; + SIGNAL wire_niO100iO_w_lg_dataout15797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100l_dataout : STD_LOGIC; + SIGNAL wire_niO100li_dataout : STD_LOGIC; + SIGNAL wire_niO100li_w_lg_dataout15776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_dataout : STD_LOGIC; + SIGNAL wire_niO100ll_w15851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_w15835w15836w15837w15838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_w15842w15848w15849w15850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_w15842w15843w15844w15845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w15835w15836w15837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w15780w15831w15832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w15799w15800w15801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w15842w15848w15849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w15842w15843w15844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w15790w15791w15792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15835w15836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15780w15831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15780w15781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15934w15935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15799w15800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15842w15848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15842w15843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w15790w15791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w15835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w15780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w15934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w15799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w15842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w15790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_dataout15777w15778w15779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_dataout15805w15806w15807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15796w15798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15788w15840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15788w15789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_dataout15777w15778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_dataout15805w15806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_dataout15787w15796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_w_lg_dataout15787w15788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_dataout15777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_dataout15805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100ll_w_lg_dataout15787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100lO_dataout : STD_LOGIC; + SIGNAL wire_niO100lO_w_lg_dataout16298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100O_dataout : STD_LOGIC; + SIGNAL wire_niO100Oi_dataout : STD_LOGIC; + SIGNAL wire_niO100Oi_w_lg_dataout16296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100Ol_dataout : STD_LOGIC; + SIGNAL wire_niO100Ol_w_lg_w_lg_w_lg_dataout16630w23925w23926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100Ol_w_lg_w_lg_dataout16300w16301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100Ol_w_lg_w_lg_dataout16630w23925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100Ol_w_lg_dataout16297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100Ol_w_lg_dataout16300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100Ol_w_lg_dataout16630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO100OO_dataout : STD_LOGIC; + SIGNAL wire_niO1010i_dataout : STD_LOGIC; + SIGNAL wire_niO1010i_w_lg_dataout14877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1010l_dataout : STD_LOGIC; + SIGNAL wire_niO1010l_w_lg_dataout14875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1010O_dataout : STD_LOGIC; + SIGNAL wire_niO1010O_w_lg_dataout14923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1011i_dataout : STD_LOGIC; + SIGNAL wire_niO1011i_w_lg_dataout19802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1011l_dataout : STD_LOGIC; + SIGNAL wire_niO1011l_w_lg_dataout27511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1011O_dataout : STD_LOGIC; + SIGNAL wire_niO1011O_w_lg_dataout14525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101i_dataout : STD_LOGIC; + SIGNAL wire_niO101ii_dataout : STD_LOGIC; + SIGNAL wire_niO101ii_w_lg_dataout14901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101il_dataout : STD_LOGIC; + SIGNAL wire_niO101il_w_lg_dataout14934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101iO_dataout : STD_LOGIC; + SIGNAL wire_niO101iO_w_lg_dataout14890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101l_dataout : STD_LOGIC; + SIGNAL wire_niO101li_dataout : STD_LOGIC; + SIGNAL wire_niO101li_w_lg_dataout14869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_dataout : STD_LOGIC; + SIGNAL wire_niO101ll_w14944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_w14928w14929w14930w14931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_w14935w14941w14942w14943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_w14935w14936w14937w14938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w14928w14929w14930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w14873w14924w14925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w14892w14893w14894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w14935w14941w14942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w14935w14936w14937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w14883w14884w14885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w14928w14929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w14873w14924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w14873w14874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w15027w15028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w14892w14893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w14935w14941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w14935w14936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w14883w14884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w14928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w14873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w15027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w14892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w14935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w14883w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_dataout14870w14871w14872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_dataout14898w14899w14900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14889w14891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14881w14933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14881w14882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_dataout14870w14871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_dataout14898w14899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_dataout14880w14889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_w_lg_dataout14880w14881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_dataout14870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_dataout14898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101ll_w_lg_dataout14880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101lO_dataout : STD_LOGIC; + SIGNAL wire_niO101lO_w_lg_dataout15391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101O_dataout : STD_LOGIC; + SIGNAL wire_niO101Oi_dataout : STD_LOGIC; + SIGNAL wire_niO101Oi_w_lg_dataout15389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101Ol_dataout : STD_LOGIC; + SIGNAL wire_niO101Ol_w_lg_w_lg_w_lg_dataout15723w23929w23930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101Ol_w_lg_w_lg_dataout15393w15394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101Ol_w_lg_w_lg_dataout15723w23929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101Ol_w_lg_dataout15390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101Ol_w_lg_dataout15393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101Ol_w_lg_dataout15723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO101OO_dataout : STD_LOGIC; + SIGNAL wire_niO10i0i_dataout : STD_LOGIC; + SIGNAL wire_niO10i0i_w_lg_dataout16691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10i0l_dataout : STD_LOGIC; + SIGNAL wire_niO10i0l_w_lg_dataout16689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10i0O_dataout : STD_LOGIC; + SIGNAL wire_niO10i0O_w_lg_dataout16737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10i1i_dataout : STD_LOGIC; + SIGNAL wire_niO10i1i_w_lg_dataout19794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10i1l_dataout : STD_LOGIC; + SIGNAL wire_niO10i1l_w_lg_dataout27501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10i1O_dataout : STD_LOGIC; + SIGNAL wire_niO10i1O_w_lg_dataout16339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ii_dataout : STD_LOGIC; + SIGNAL wire_niO10iii_dataout : STD_LOGIC; + SIGNAL wire_niO10iii_w_lg_dataout16715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iil_dataout : STD_LOGIC; + SIGNAL wire_niO10iil_w_lg_dataout16748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iiO_dataout : STD_LOGIC; + SIGNAL wire_niO10iiO_w_lg_dataout16704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10il_dataout : STD_LOGIC; + SIGNAL wire_niO10ili_dataout : STD_LOGIC; + SIGNAL wire_niO10ili_w_lg_dataout16683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_dataout : STD_LOGIC; + SIGNAL wire_niO10ill_w16758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_w16742w16743w16744w16745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_w16749w16755w16756w16757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_w16749w16750w16751w16752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w16742w16743w16744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w16687w16738w16739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w16706w16707w16708w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w16749w16755w16756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w16749w16750w16751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w16697w16698w16699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16742w16743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16687w16738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16687w16688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16841w16842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16706w16707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16749w16755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16749w16750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w16697w16698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w16742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w16687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w16841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w16706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w16749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w16697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_dataout16684w16685w16686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_dataout16712w16713w16714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16703w16705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16695w16747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16695w16696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_dataout16684w16685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_dataout16712w16713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_dataout16694w16703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_w_lg_dataout16694w16695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_dataout16684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_dataout16712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ill_w_lg_dataout16694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ilO_dataout : STD_LOGIC; + SIGNAL wire_niO10ilO_w_lg_dataout17205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iO_dataout : STD_LOGIC; + SIGNAL wire_niO10iOi_dataout : STD_LOGIC; + SIGNAL wire_niO10iOi_w_lg_dataout17203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iOl_dataout : STD_LOGIC; + SIGNAL wire_niO10iOl_w_lg_w_lg_w_lg_dataout17537w23921w23922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iOl_w_lg_w_lg_dataout17207w17208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iOl_w_lg_w_lg_dataout17537w23921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iOl_w_lg_dataout17204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iOl_w_lg_dataout17207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iOl_w_lg_dataout17537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10iOO_dataout : STD_LOGIC; + SIGNAL wire_niO10l0i_dataout : STD_LOGIC; + SIGNAL wire_niO10l0i_w_lg_dataout17598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10l0l_dataout : STD_LOGIC; + SIGNAL wire_niO10l0l_w_lg_dataout17596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10l0O_dataout : STD_LOGIC; + SIGNAL wire_niO10l0O_w_lg_dataout17644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10l1i_dataout : STD_LOGIC; + SIGNAL wire_niO10l1i_w_lg_dataout19790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10l1l_dataout : STD_LOGIC; + SIGNAL wire_niO10l1l_w_lg_dataout27496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10l1O_dataout : STD_LOGIC; + SIGNAL wire_niO10l1O_w_lg_dataout17246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10li_dataout : STD_LOGIC; + SIGNAL wire_niO10lii_dataout : STD_LOGIC; + SIGNAL wire_niO10lii_w_lg_dataout17622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lil_dataout : STD_LOGIC; + SIGNAL wire_niO10lil_w_lg_dataout17655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10liO_dataout : STD_LOGIC; + SIGNAL wire_niO10liO_w_lg_dataout17611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10ll_dataout : STD_LOGIC; + SIGNAL wire_niO10lli_dataout : STD_LOGIC; + SIGNAL wire_niO10lli_w_lg_dataout17590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_dataout : STD_LOGIC; + SIGNAL wire_niO10lll_w17665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_w17649w17650w17651w17652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_w17656w17662w17663w17664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_w17656w17657w17658w17659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w17649w17650w17651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w17594w17645w17646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w17613w17614w17615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w17656w17662w17663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w17656w17657w17658w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w17604w17605w17606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17649w17650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17594w17645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17594w17595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17748w17749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17613w17614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17656w17662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17656w17657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w17604w17605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w17649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w17594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w17748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w17613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w17656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w17604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_dataout17591w17592w17593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_dataout17619w17620w17621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17610w17612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17602w17654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17602w17603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_dataout17591w17592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_dataout17619w17620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_dataout17601w17610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_w_lg_dataout17601w17602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_dataout17591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_dataout17619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lll_w_lg_dataout17601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10llO_dataout : STD_LOGIC; + SIGNAL wire_niO10llO_w_lg_dataout18112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lO_dataout : STD_LOGIC; + SIGNAL wire_niO10lOi_dataout : STD_LOGIC; + SIGNAL wire_niO10lOi_w_lg_dataout18110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lOl_dataout : STD_LOGIC; + SIGNAL wire_niO10lOl_w_lg_w_lg_w_lg_dataout18444w23917w23918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lOl_w_lg_w_lg_dataout18114w18115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lOl_w_lg_w_lg_dataout18444w23917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lOl_w_lg_dataout18111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lOl_w_lg_dataout18114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lOl_w_lg_dataout18444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10lOO_dataout : STD_LOGIC; + SIGNAL wire_niO10O0i_dataout : STD_LOGIC; + SIGNAL wire_niO10O0i_w_lg_dataout18505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10O0l_dataout : STD_LOGIC; + SIGNAL wire_niO10O0l_w_lg_dataout18503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10O0O_dataout : STD_LOGIC; + SIGNAL wire_niO10O0O_w_lg_dataout18551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10O1i_dataout : STD_LOGIC; + SIGNAL wire_niO10O1i_w_lg_dataout19787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10O1l_dataout : STD_LOGIC; + SIGNAL wire_niO10O1l_w_lg_dataout27492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10O1O_dataout : STD_LOGIC; + SIGNAL wire_niO10O1O_w_lg_dataout18153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oi_dataout : STD_LOGIC; + SIGNAL wire_niO10Oii_dataout : STD_LOGIC; + SIGNAL wire_niO10Oii_w_lg_dataout18529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oil_dataout : STD_LOGIC; + SIGNAL wire_niO10Oil_w_lg_dataout18562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10OiO_dataout : STD_LOGIC; + SIGNAL wire_niO10OiO_w_lg_dataout18518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Ol_dataout : STD_LOGIC; + SIGNAL wire_niO10Oli_dataout : STD_LOGIC; + SIGNAL wire_niO10Oli_w_lg_dataout18497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_dataout : STD_LOGIC; + SIGNAL wire_niO10Oll_w18572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_w18556w18557w18558w18559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_w18563w18569w18570w18571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_w18563w18564w18565w18566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w18556w18557w18558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w18501w18552w18553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w18520w18521w18522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w18563w18569w18570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w18563w18564w18565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w18511w18512w18513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18556w18557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18501w18552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18501w18502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18655w18656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18520w18521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18563w18569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18563w18564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w18511w18512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w18556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w18501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w18655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w18520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w18563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w18511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_dataout18498w18499w18500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_dataout18526w18527w18528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18517w18519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18509w18561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18509w18510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_dataout18498w18499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_dataout18526w18527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_dataout18508w18517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_w_lg_dataout18508w18509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_dataout18498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_dataout18526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10Oll_w_lg_dataout18508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO10OO_dataout : STD_LOGIC; + SIGNAL wire_niO1100i_dataout : STD_LOGIC; + SIGNAL wire_niO1100l_dataout : STD_LOGIC; + SIGNAL wire_niO1100O_dataout : STD_LOGIC; + SIGNAL wire_niO1101i_dataout : STD_LOGIC; + SIGNAL wire_niO1101l_dataout : STD_LOGIC; + SIGNAL wire_niO1101O_dataout : STD_LOGIC; + SIGNAL wire_niO110i_dataout : STD_LOGIC; + SIGNAL wire_niO110l_dataout : STD_LOGIC; + SIGNAL wire_niO110lO_dataout : STD_LOGIC; + SIGNAL wire_niO110lO_w_lg_dataout11759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110O_dataout : STD_LOGIC; + SIGNAL wire_niO110Oi_dataout : STD_LOGIC; + SIGNAL wire_niO110Oi_w_lg_dataout11757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110Ol_dataout : STD_LOGIC; + SIGNAL wire_niO110Ol_w_lg_w_lg_w_lg_dataout12091w23945w23946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110Ol_w_lg_w_lg_dataout11761w11762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110Ol_w_lg_w_lg_dataout12091w23945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110Ol_w_lg_dataout11758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110Ol_w_lg_dataout11761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110Ol_w_lg_dataout12091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO110OO_dataout : STD_LOGIC; + SIGNAL wire_niO1110i_dataout : STD_LOGIC; + SIGNAL wire_niO1110i_w_lg_dataout42248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1110i_w_lg_dataout42873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1110l_dataout : STD_LOGIC; + SIGNAL wire_niO1110l_w_lg_dataout44125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1110O_dataout : STD_LOGIC; + SIGNAL wire_niO1110O_w_lg_dataout36183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1111i_dataout : STD_LOGIC; + SIGNAL wire_niO1111i_w_lg_dataout42861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1111l_dataout : STD_LOGIC; + SIGNAL wire_niO1111l_w_lg_dataout42865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO1111O_dataout : STD_LOGIC; + SIGNAL wire_niO1111O_w_lg_dataout42869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO111i_dataout : STD_LOGIC; + SIGNAL wire_niO111ii_dataout : STD_LOGIC; + SIGNAL wire_niO111ii_w_lg_dataout8980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO111il_dataout : STD_LOGIC; + SIGNAL wire_niO111il_w_lg_dataout9224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO111iO_dataout : STD_LOGIC; + SIGNAL wire_niO111l_dataout : STD_LOGIC; + SIGNAL wire_niO111li_dataout : STD_LOGIC; + SIGNAL wire_niO111ll_dataout : STD_LOGIC; + SIGNAL wire_niO111lO_dataout : STD_LOGIC; + SIGNAL wire_niO111O_dataout : STD_LOGIC; + SIGNAL wire_niO111Oi_dataout : STD_LOGIC; + SIGNAL wire_niO111Ol_dataout : STD_LOGIC; + SIGNAL wire_niO111OO_dataout : STD_LOGIC; + SIGNAL wire_niO11i0i_dataout : STD_LOGIC; + SIGNAL wire_niO11i0i_w_lg_dataout12155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11i0l_dataout : STD_LOGIC; + SIGNAL wire_niO11i0l_w_lg_dataout12153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11i0O_dataout : STD_LOGIC; + SIGNAL wire_niO11i0O_w_lg_dataout12201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11i1i_dataout : STD_LOGIC; + SIGNAL wire_niO11i1i_w_lg_dataout19814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11i1l_dataout : STD_LOGIC; + SIGNAL wire_niO11i1l_w_lg_dataout27526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11i1O_dataout : STD_LOGIC; + SIGNAL wire_niO11i1O_w_lg_dataout11800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ii_dataout : STD_LOGIC; + SIGNAL wire_niO11iii_dataout : STD_LOGIC; + SIGNAL wire_niO11iii_w_lg_dataout12179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iil_dataout : STD_LOGIC; + SIGNAL wire_niO11iil_w_lg_dataout12212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iiO_dataout : STD_LOGIC; + SIGNAL wire_niO11iiO_w_lg_dataout12168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11il_dataout : STD_LOGIC; + SIGNAL wire_niO11ili_dataout : STD_LOGIC; + SIGNAL wire_niO11ili_w_lg_dataout12147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_dataout : STD_LOGIC; + SIGNAL wire_niO11ill_w12222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_w12206w12207w12208w12209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_w12213w12219w12220w12221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_w12213w12214w12215w12216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w12206w12207w12208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w12151w12202w12203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w12170w12171w12172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w12213w12219w12220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w12213w12214w12215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w12161w12162w12163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12206w12207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12151w12202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12151w12152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12305w12306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12170w12171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12213w12219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12213w12214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w12161w12162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w12206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w12151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w12305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w12170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w12213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w12161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_dataout12148w12149w12150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_dataout12176w12177w12178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12167w12169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12159w12211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12159w12160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_dataout12148w12149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_dataout12176w12177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_dataout12158w12167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_w_lg_dataout12158w12159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_dataout12148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_dataout12176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ill_w_lg_dataout12158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ilO_dataout : STD_LOGIC; + SIGNAL wire_niO11ilO_w_lg_dataout12670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iO_dataout : STD_LOGIC; + SIGNAL wire_niO11iOi_dataout : STD_LOGIC; + SIGNAL wire_niO11iOi_w_lg_dataout12668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iOl_dataout : STD_LOGIC; + SIGNAL wire_niO11iOl_w_lg_w_lg_w_lg_dataout13002w23941w23942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iOl_w_lg_w_lg_dataout12672w12673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iOl_w_lg_w_lg_dataout13002w23941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iOl_w_lg_dataout12669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iOl_w_lg_dataout12672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iOl_w_lg_dataout13002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11iOO_dataout : STD_LOGIC; + SIGNAL wire_niO11l0i_dataout : STD_LOGIC; + SIGNAL wire_niO11l0i_w_lg_dataout13063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11l0l_dataout : STD_LOGIC; + SIGNAL wire_niO11l0l_w_lg_dataout13061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11l0O_dataout : STD_LOGIC; + SIGNAL wire_niO11l0O_w_lg_dataout13109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11l1i_dataout : STD_LOGIC; + SIGNAL wire_niO11l1i_w_lg_dataout19810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11l1l_dataout : STD_LOGIC; + SIGNAL wire_niO11l1l_w_lg_dataout27521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11l1O_dataout : STD_LOGIC; + SIGNAL wire_niO11l1O_w_lg_dataout12711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11li_dataout : STD_LOGIC; + SIGNAL wire_niO11lii_dataout : STD_LOGIC; + SIGNAL wire_niO11lii_w_lg_dataout13087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lil_dataout : STD_LOGIC; + SIGNAL wire_niO11lil_w_lg_dataout13120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11liO_dataout : STD_LOGIC; + SIGNAL wire_niO11liO_w_lg_dataout13076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11ll_dataout : STD_LOGIC; + SIGNAL wire_niO11lli_dataout : STD_LOGIC; + SIGNAL wire_niO11lli_w_lg_dataout13055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_dataout : STD_LOGIC; + SIGNAL wire_niO11lll_w13130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_w13114w13115w13116w13117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_w13121w13127w13128w13129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_w13121w13122w13123w13124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w13114w13115w13116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w13059w13110w13111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w13078w13079w13080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w13121w13127w13128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w13121w13122w13123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w13069w13070w13071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13114w13115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13059w13110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13059w13060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13213w13214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13078w13079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13121w13127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13121w13122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w13069w13070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w13114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w13059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w13213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w13078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w13121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w13069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_dataout13056w13057w13058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_dataout13084w13085w13086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13075w13077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13067w13119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13067w13068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_dataout13056w13057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_dataout13084w13085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_dataout13066w13075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_w_lg_dataout13066w13067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_dataout13056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_dataout13084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lll_w_lg_dataout13066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11llO_dataout : STD_LOGIC; + SIGNAL wire_niO11llO_w_lg_dataout13577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lO_dataout : STD_LOGIC; + SIGNAL wire_niO11lOi_dataout : STD_LOGIC; + SIGNAL wire_niO11lOi_w_lg_dataout13575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lOl_dataout : STD_LOGIC; + SIGNAL wire_niO11lOl_w_lg_w_lg_w_lg_dataout13909w23937w23938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lOl_w_lg_w_lg_dataout13579w13580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lOl_w_lg_w_lg_dataout13909w23937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lOl_w_lg_dataout13576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lOl_w_lg_dataout13579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lOl_w_lg_dataout13909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11lOO_dataout : STD_LOGIC; + SIGNAL wire_niO11O0i_dataout : STD_LOGIC; + SIGNAL wire_niO11O0i_w_lg_dataout13970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11O0l_dataout : STD_LOGIC; + SIGNAL wire_niO11O0l_w_lg_dataout13968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11O0O_dataout : STD_LOGIC; + SIGNAL wire_niO11O0O_w_lg_dataout14016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11O1i_dataout : STD_LOGIC; + SIGNAL wire_niO11O1i_w_lg_dataout19806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11O1l_dataout : STD_LOGIC; + SIGNAL wire_niO11O1l_w_lg_dataout27516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11O1O_dataout : STD_LOGIC; + SIGNAL wire_niO11O1O_w_lg_dataout13618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oi_dataout : STD_LOGIC; + SIGNAL wire_niO11Oii_dataout : STD_LOGIC; + SIGNAL wire_niO11Oii_w_lg_dataout13994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oil_dataout : STD_LOGIC; + SIGNAL wire_niO11Oil_w_lg_dataout14027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OiO_dataout : STD_LOGIC; + SIGNAL wire_niO11OiO_w_lg_dataout13983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Ol_dataout : STD_LOGIC; + SIGNAL wire_niO11Oli_dataout : STD_LOGIC; + SIGNAL wire_niO11Oli_w_lg_dataout13962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_dataout : STD_LOGIC; + SIGNAL wire_niO11Oll_w14037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_w14021w14022w14023w14024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_w14028w14034w14035w14036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_w14028w14029w14030w14031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w14021w14022w14023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w13966w14017w14018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w13985w13986w13987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w14028w14034w14035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w14028w14029w14030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w13976w13977w13978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w14021w14022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w13966w14017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w13966w13967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w14120w14121w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w13985w13986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w14028w14034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w14028w14029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w13976w13977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w14021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w13966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w14120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w13985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w14028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w13976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_dataout13963w13964w13965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_dataout13991w13992w13993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13982w13984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13974w14026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13974w13975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_dataout13963w13964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_dataout13991w13992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_dataout13973w13982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_w_lg_dataout13973w13974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_dataout13963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_dataout13991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11Oll_w_lg_dataout13973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OlO_dataout : STD_LOGIC; + SIGNAL wire_niO11OlO_w_lg_dataout14484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OO_dataout : STD_LOGIC; + SIGNAL wire_niO11OOi_dataout : STD_LOGIC; + SIGNAL wire_niO11OOi_w_lg_dataout14482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OOl_dataout : STD_LOGIC; + SIGNAL wire_niO11OOl_w_lg_w_lg_w_lg_dataout14816w23933w23934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OOl_w_lg_w_lg_dataout14486w14487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OOl_w_lg_w_lg_dataout14816w23933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OOl_w_lg_dataout14483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OOl_w_lg_dataout14486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OOl_w_lg_dataout14816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_niO11OOO_dataout : STD_LOGIC; + SIGNAL wire_niO1i0i_dataout : STD_LOGIC; + SIGNAL wire_niO1i0l_dataout : STD_LOGIC; + SIGNAL wire_niO1i0O_dataout : STD_LOGIC; + SIGNAL wire_niO1i1i_dataout : STD_LOGIC; + SIGNAL wire_niO1i1l_dataout : STD_LOGIC; + SIGNAL wire_niO1i1O_dataout : STD_LOGIC; + SIGNAL wire_niO1iii_dataout : STD_LOGIC; + SIGNAL wire_niO1iil_dataout : STD_LOGIC; + SIGNAL wire_niO1iiO_dataout : STD_LOGIC; + SIGNAL wire_niO1ili_dataout : STD_LOGIC; + SIGNAL wire_niO1ill_dataout : STD_LOGIC; + SIGNAL wire_niO1ilO_dataout : STD_LOGIC; + SIGNAL wire_niO1iOi_dataout : STD_LOGIC; + SIGNAL wire_niO1iOl_dataout : STD_LOGIC; + SIGNAL wire_niO1iOO_dataout : STD_LOGIC; + SIGNAL wire_niO1l0i_dataout : STD_LOGIC; + SIGNAL wire_niO1l0l_dataout : STD_LOGIC; + SIGNAL wire_niO1l0O_dataout : STD_LOGIC; + SIGNAL wire_niO1l1i_dataout : STD_LOGIC; + SIGNAL wire_niO1l1l_dataout : STD_LOGIC; + SIGNAL wire_niO1l1O_dataout : STD_LOGIC; + SIGNAL wire_niO1li0l_dataout : STD_LOGIC; + SIGNAL wire_niO1li0O_dataout : STD_LOGIC; + SIGNAL wire_niO1lii_dataout : STD_LOGIC; + SIGNAL wire_niO1liii_dataout : STD_LOGIC; + SIGNAL wire_niO1liil_dataout : STD_LOGIC; + SIGNAL wire_niO1liiO_dataout : STD_LOGIC; + SIGNAL wire_niO1lil_dataout : STD_LOGIC; + SIGNAL wire_niO1lili_dataout : STD_LOGIC; + SIGNAL wire_niO1lill_dataout : STD_LOGIC; + SIGNAL wire_niO1lilO_dataout : STD_LOGIC; + SIGNAL wire_niO1liO_dataout : STD_LOGIC; + SIGNAL wire_niO1liOi_dataout : STD_LOGIC; + SIGNAL wire_niO1liOl_dataout : STD_LOGIC; + SIGNAL wire_niO1liOO_dataout : STD_LOGIC; + SIGNAL wire_niO1ll0i_dataout : STD_LOGIC; + SIGNAL wire_niO1ll0l_dataout : STD_LOGIC; + SIGNAL wire_niO1ll0O_dataout : STD_LOGIC; + SIGNAL wire_niO1ll1i_dataout : STD_LOGIC; + SIGNAL wire_niO1ll1l_dataout : STD_LOGIC; + SIGNAL wire_niO1ll1O_dataout : STD_LOGIC; + SIGNAL wire_niO1lli_dataout : STD_LOGIC; + SIGNAL wire_niO1llii_dataout : STD_LOGIC; + SIGNAL wire_niO1llil_dataout : STD_LOGIC; + SIGNAL wire_niO1lliO_dataout : STD_LOGIC; + SIGNAL wire_niO1lll_dataout : STD_LOGIC; + SIGNAL wire_niO1llli_dataout : STD_LOGIC; + SIGNAL wire_niO1llll_dataout : STD_LOGIC; + SIGNAL wire_niO1lllO_dataout : STD_LOGIC; + SIGNAL wire_niO1llO_dataout : STD_LOGIC; + SIGNAL wire_niO1llOi_dataout : STD_LOGIC; + SIGNAL wire_niO1llOl_dataout : STD_LOGIC; + SIGNAL wire_niO1llOO_dataout : STD_LOGIC; + SIGNAL wire_niO1lO0i_dataout : STD_LOGIC; + SIGNAL wire_niO1lO0l_dataout : STD_LOGIC; + SIGNAL wire_niO1lO0O_dataout : STD_LOGIC; + SIGNAL wire_niO1lO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1lO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1lO1O_dataout : STD_LOGIC; + SIGNAL wire_niO1lOi_dataout : STD_LOGIC; + SIGNAL wire_niO1lOii_dataout : STD_LOGIC; + SIGNAL wire_niO1lOil_dataout : STD_LOGIC; + SIGNAL wire_niO1lOiO_dataout : STD_LOGIC; + SIGNAL wire_niO1lOl_dataout : STD_LOGIC; + SIGNAL wire_niO1lOli_dataout : STD_LOGIC; + SIGNAL wire_niO1lOll_dataout : STD_LOGIC; + SIGNAL wire_niO1lOlO_dataout : STD_LOGIC; + SIGNAL wire_niO1lOO_dataout : STD_LOGIC; + SIGNAL wire_niO1lOOi_dataout : STD_LOGIC; + SIGNAL wire_niO1lOOl_dataout : STD_LOGIC; + SIGNAL wire_niO1lOOO_dataout : STD_LOGIC; + SIGNAL wire_niO1O00i_dataout : STD_LOGIC; + SIGNAL wire_niO1O00l_dataout : STD_LOGIC; + SIGNAL wire_niO1O00O_dataout : STD_LOGIC; + SIGNAL wire_niO1O01i_dataout : STD_LOGIC; + SIGNAL wire_niO1O01l_dataout : STD_LOGIC; + SIGNAL wire_niO1O01O_dataout : STD_LOGIC; + SIGNAL wire_niO1O0i_dataout : STD_LOGIC; + SIGNAL wire_niO1O0ii_dataout : STD_LOGIC; + SIGNAL wire_niO1O0il_dataout : STD_LOGIC; + SIGNAL wire_niO1O0iO_dataout : STD_LOGIC; + SIGNAL wire_niO1O0l_dataout : STD_LOGIC; + SIGNAL wire_niO1O0li_dataout : STD_LOGIC; + SIGNAL wire_niO1O0ll_dataout : STD_LOGIC; + SIGNAL wire_niO1O0lO_dataout : STD_LOGIC; + SIGNAL wire_niO1O0O_dataout : STD_LOGIC; + SIGNAL wire_niO1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_niO1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_niO1O0OO_dataout : STD_LOGIC; + SIGNAL wire_niO1O10i_dataout : STD_LOGIC; + SIGNAL wire_niO1O10l_dataout : STD_LOGIC; + SIGNAL wire_niO1O10O_dataout : STD_LOGIC; + SIGNAL wire_niO1O11i_dataout : STD_LOGIC; + SIGNAL wire_niO1O11l_dataout : STD_LOGIC; + SIGNAL wire_niO1O11O_dataout : STD_LOGIC; + SIGNAL wire_niO1O1i_dataout : STD_LOGIC; + SIGNAL wire_niO1O1ii_dataout : STD_LOGIC; + SIGNAL wire_niO1O1il_dataout : STD_LOGIC; + SIGNAL wire_niO1O1iO_dataout : STD_LOGIC; + SIGNAL wire_niO1O1l_dataout : STD_LOGIC; + SIGNAL wire_niO1O1li_dataout : STD_LOGIC; + SIGNAL wire_niO1O1ll_dataout : STD_LOGIC; + SIGNAL wire_niO1O1lO_dataout : STD_LOGIC; + SIGNAL wire_niO1O1O_dataout : STD_LOGIC; + SIGNAL wire_niO1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_niO1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_niO1O1OO_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_niO1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_niO1Oii_dataout : STD_LOGIC; + SIGNAL wire_niO1Oiii_dataout : STD_LOGIC; + SIGNAL wire_niO1Oiil_dataout : STD_LOGIC; + SIGNAL wire_niO1OiiO_dataout : STD_LOGIC; + SIGNAL wire_niO1Oil_dataout : STD_LOGIC; + SIGNAL wire_niO1Oili_dataout : STD_LOGIC; + SIGNAL wire_niO1Oill_dataout : STD_LOGIC; + SIGNAL wire_niO1OilO_dataout : STD_LOGIC; + SIGNAL wire_niO1OiO_dataout : STD_LOGIC; + SIGNAL wire_niO1OiOi_dataout : STD_LOGIC; + SIGNAL wire_niO1OiOl_dataout : STD_LOGIC; + SIGNAL wire_niO1OiOO_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_niO1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_niO1Oli_dataout : STD_LOGIC; + SIGNAL wire_niO1Olii_dataout : STD_LOGIC; + SIGNAL wire_niO1Olil_dataout : STD_LOGIC; + SIGNAL wire_niO1OliO_dataout : STD_LOGIC; + SIGNAL wire_niO1Oll_dataout : STD_LOGIC; + SIGNAL wire_niO1Olli_dataout : STD_LOGIC; + SIGNAL wire_niO1Olll_dataout : STD_LOGIC; + SIGNAL wire_niO1OllO_dataout : STD_LOGIC; + SIGNAL wire_niO1OlO_dataout : STD_LOGIC; + SIGNAL wire_niO1OlOi_dataout : STD_LOGIC; + SIGNAL wire_niO1OlOl_dataout : STD_LOGIC; + SIGNAL wire_niO1OlOO_dataout : STD_LOGIC; + SIGNAL wire_niO1OO0i_dataout : STD_LOGIC; + SIGNAL wire_niO1OO0l_dataout : STD_LOGIC; + SIGNAL wire_niO1OO0O_dataout : STD_LOGIC; + SIGNAL wire_niO1OO1i_dataout : STD_LOGIC; + SIGNAL wire_niO1OO1l_dataout : STD_LOGIC; + SIGNAL wire_niO1OO1O_dataout : STD_LOGIC; + SIGNAL wire_niO1OOi_dataout : STD_LOGIC; + SIGNAL wire_niO1OOii_dataout : STD_LOGIC; + SIGNAL wire_niO1OOil_dataout : STD_LOGIC; + SIGNAL wire_niO1OOiO_dataout : STD_LOGIC; + SIGNAL wire_niO1OOl_dataout : STD_LOGIC; + SIGNAL wire_niO1OOli_dataout : STD_LOGIC; + SIGNAL wire_niO1OOll_dataout : STD_LOGIC; + SIGNAL wire_niO1OOO_dataout : STD_LOGIC; + SIGNAL wire_niOi00OO_dataout : STD_LOGIC; + SIGNAL wire_niOi0i0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0i0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0i0O_dataout : STD_LOGIC; + SIGNAL wire_niOi0i1i_dataout : STD_LOGIC; + SIGNAL wire_niOi0i1l_dataout : STD_LOGIC; + SIGNAL wire_niOi0i1O_dataout : STD_LOGIC; + SIGNAL wire_niOi0iii_dataout : STD_LOGIC; + SIGNAL wire_niOi0iil_dataout : STD_LOGIC; + SIGNAL wire_niOi0iiO_dataout : STD_LOGIC; + SIGNAL wire_niOi0ili_dataout : STD_LOGIC; + SIGNAL wire_niOi0ill_dataout : STD_LOGIC; + SIGNAL wire_niOi0ilO_dataout : STD_LOGIC; + SIGNAL wire_niOi0iOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0iOl_dataout : STD_LOGIC; + SIGNAL wire_niOi0iOO_dataout : STD_LOGIC; + SIGNAL wire_niOi0l0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0l0O_dataout : STD_LOGIC; + SIGNAL wire_niOi0l1i_dataout : STD_LOGIC; + SIGNAL wire_niOi0l1l_dataout : STD_LOGIC; + SIGNAL wire_niOi0l1O_dataout : STD_LOGIC; + SIGNAL wire_niOi0lii_dataout : STD_LOGIC; + SIGNAL wire_niOi0lil_dataout : STD_LOGIC; + SIGNAL wire_niOi0liO_dataout : STD_LOGIC; + SIGNAL wire_niOi0lli_dataout : STD_LOGIC; + SIGNAL wire_niOi0lll_dataout : STD_LOGIC; + SIGNAL wire_niOi0llO_dataout : STD_LOGIC; + SIGNAL wire_niOi0lOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0lOl_dataout : STD_LOGIC; + SIGNAL wire_niOi0lOO_dataout : STD_LOGIC; + SIGNAL wire_niOi0O0i_dataout : STD_LOGIC; + SIGNAL wire_niOi0O0l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O0O_dataout : STD_LOGIC; + SIGNAL wire_niOi0O1i_dataout : STD_LOGIC; + SIGNAL wire_niOi0O1l_dataout : STD_LOGIC; + SIGNAL wire_niOi0O1O_dataout : STD_LOGIC; + SIGNAL wire_niOi0Oii_dataout : STD_LOGIC; + SIGNAL wire_niOi0Oil_dataout : STD_LOGIC; + SIGNAL wire_niOi0OiO_dataout : STD_LOGIC; + SIGNAL wire_niOi0Oli_dataout : STD_LOGIC; + SIGNAL wire_niOi0Oll_dataout : STD_LOGIC; + SIGNAL wire_niOi0OlO_dataout : STD_LOGIC; + SIGNAL wire_niOi0OOi_dataout : STD_LOGIC; + SIGNAL wire_niOi0OOl_dataout : STD_LOGIC; + SIGNAL wire_niOi0OOO_dataout : STD_LOGIC; + SIGNAL wire_niOi10i_dataout : STD_LOGIC; + SIGNAL wire_niOi10l_dataout : STD_LOGIC; + SIGNAL wire_niOi10O_dataout : STD_LOGIC; + SIGNAL wire_niOi110i_dataout : STD_LOGIC; + SIGNAL wire_niOi110l_dataout : STD_LOGIC; + SIGNAL wire_niOi110O_dataout : STD_LOGIC; + SIGNAL wire_niOi111O_dataout : STD_LOGIC; + SIGNAL wire_niOi11i_dataout : STD_LOGIC; + SIGNAL wire_niOi11ii_dataout : STD_LOGIC; + SIGNAL wire_niOi11il_dataout : STD_LOGIC; + SIGNAL wire_niOi11iO_dataout : STD_LOGIC; + SIGNAL wire_niOi11l_dataout : STD_LOGIC; + SIGNAL wire_niOi11O_dataout : STD_LOGIC; + SIGNAL wire_niOi1ii_dataout : STD_LOGIC; + SIGNAL wire_niOi1il_dataout : STD_LOGIC; + SIGNAL wire_niOi1iO_dataout : STD_LOGIC; + SIGNAL wire_niOi1li_dataout : STD_LOGIC; + SIGNAL wire_niOi1ll_dataout : STD_LOGIC; + SIGNAL wire_niOi1lO_dataout : STD_LOGIC; + SIGNAL wire_niOii00i_dataout : STD_LOGIC; + SIGNAL wire_niOii00l_dataout : STD_LOGIC; + SIGNAL wire_niOii00O_dataout : STD_LOGIC; + SIGNAL wire_niOii01i_dataout : STD_LOGIC; + SIGNAL wire_niOii01l_dataout : STD_LOGIC; + SIGNAL wire_niOii01O_dataout : STD_LOGIC; + SIGNAL wire_niOii0ii_dataout : STD_LOGIC; + SIGNAL wire_niOii0il_dataout : STD_LOGIC; + SIGNAL wire_niOii0iO_dataout : STD_LOGIC; + SIGNAL wire_niOii0li_dataout : STD_LOGIC; + SIGNAL wire_niOii0ll_dataout : STD_LOGIC; + SIGNAL wire_niOii0lO_dataout : STD_LOGIC; + SIGNAL wire_niOii0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOii0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOii0OO_dataout : STD_LOGIC; + SIGNAL wire_niOii10i_dataout : STD_LOGIC; + SIGNAL wire_niOii10l_dataout : STD_LOGIC; + SIGNAL wire_niOii10O_dataout : STD_LOGIC; + SIGNAL wire_niOii11i_dataout : STD_LOGIC; + SIGNAL wire_niOii11l_dataout : STD_LOGIC; + SIGNAL wire_niOii11O_dataout : STD_LOGIC; + SIGNAL wire_niOii1ii_dataout : STD_LOGIC; + SIGNAL wire_niOii1il_dataout : STD_LOGIC; + SIGNAL wire_niOii1iO_dataout : STD_LOGIC; + SIGNAL wire_niOii1li_dataout : STD_LOGIC; + SIGNAL wire_niOii1ll_dataout : STD_LOGIC; + SIGNAL wire_niOii1lO_dataout : STD_LOGIC; + SIGNAL wire_niOii1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOii1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOii1OO_dataout : STD_LOGIC; + SIGNAL wire_niOiii0i_dataout : STD_LOGIC; + SIGNAL wire_niOiii0l_dataout : STD_LOGIC; + SIGNAL wire_niOiii0O_dataout : STD_LOGIC; + SIGNAL wire_niOiii1i_dataout : STD_LOGIC; + SIGNAL wire_niOiii1l_dataout : STD_LOGIC; + SIGNAL wire_niOiii1O_dataout : STD_LOGIC; + SIGNAL wire_niOiiiii_dataout : STD_LOGIC; + SIGNAL wire_niOiiiil_dataout : STD_LOGIC; + SIGNAL wire_niOiiiiO_dataout : STD_LOGIC; + SIGNAL wire_niOiiili_dataout : STD_LOGIC; + SIGNAL wire_niOiiill_dataout : STD_LOGIC; + SIGNAL wire_niOiiilO_dataout : STD_LOGIC; + SIGNAL wire_niOiiiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiiiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiiiOO_dataout : STD_LOGIC; + SIGNAL wire_niOiil0l_dataout : STD_LOGIC; + SIGNAL wire_niOiil1i_dataout : STD_LOGIC; + SIGNAL wire_niOiilii_dataout : STD_LOGIC; + SIGNAL wire_niOiiliO_dataout : STD_LOGIC; + SIGNAL wire_niOiillO_dataout : STD_LOGIC; + SIGNAL wire_niOiilOi_dataout : STD_LOGIC; + SIGNAL wire_niOili0i_dataout : STD_LOGIC; + SIGNAL wire_niOili0l_dataout : STD_LOGIC; + SIGNAL wire_niOili0O_dataout : STD_LOGIC; + SIGNAL wire_niOili1i_dataout : STD_LOGIC; + SIGNAL wire_niOili1l_dataout : STD_LOGIC; + SIGNAL wire_niOili1O_dataout : STD_LOGIC; + SIGNAL wire_niOiliii_dataout : STD_LOGIC; + SIGNAL wire_niOiliil_dataout : STD_LOGIC; + SIGNAL wire_niOiliiO_dataout : STD_LOGIC; + SIGNAL wire_niOilili_dataout : STD_LOGIC; + SIGNAL wire_niOilill_dataout : STD_LOGIC; + SIGNAL wire_niOililO_dataout : STD_LOGIC; + SIGNAL wire_niOiliOi_dataout : STD_LOGIC; + SIGNAL wire_niOiliOl_dataout : STD_LOGIC; + SIGNAL wire_niOiliOO_dataout : STD_LOGIC; + SIGNAL wire_niOill0i_dataout : STD_LOGIC; + SIGNAL wire_niOill0l_dataout : STD_LOGIC; + SIGNAL wire_niOill0O_dataout : STD_LOGIC; + SIGNAL wire_niOill1i_dataout : STD_LOGIC; + SIGNAL wire_niOill1l_dataout : STD_LOGIC; + SIGNAL wire_niOill1O_dataout : STD_LOGIC; + SIGNAL wire_niOillii_dataout : STD_LOGIC; + SIGNAL wire_niOillil_dataout : STD_LOGIC; + SIGNAL wire_niOilliO_dataout : STD_LOGIC; + SIGNAL wire_niOillli_dataout : STD_LOGIC; + SIGNAL wire_niOillll_dataout : STD_LOGIC; + SIGNAL wire_niOilllO_dataout : STD_LOGIC; + SIGNAL wire_niOillOi_dataout : STD_LOGIC; + SIGNAL wire_niOillOl_dataout : STD_LOGIC; + SIGNAL wire_niOillOO_dataout : STD_LOGIC; + SIGNAL wire_niOilO0i_dataout : STD_LOGIC; + SIGNAL wire_niOilO0l_dataout : STD_LOGIC; + SIGNAL wire_niOilO0O_dataout : STD_LOGIC; + SIGNAL wire_niOilO1i_dataout : STD_LOGIC; + SIGNAL wire_niOilO1l_dataout : STD_LOGIC; + SIGNAL wire_niOilO1O_dataout : STD_LOGIC; + SIGNAL wire_niOilOii_dataout : STD_LOGIC; + SIGNAL wire_niOilOil_dataout : STD_LOGIC; + SIGNAL wire_niOilOiO_dataout : STD_LOGIC; + SIGNAL wire_niOilOli_dataout : STD_LOGIC; + SIGNAL wire_niOilOll_dataout : STD_LOGIC; + SIGNAL wire_niOilOlO_dataout : STD_LOGIC; + SIGNAL wire_niOilOOi_dataout : STD_LOGIC; + SIGNAL wire_niOilOOl_dataout : STD_LOGIC; + SIGNAL wire_niOilOOO_dataout : STD_LOGIC; + SIGNAL wire_niOiO00i_dataout : STD_LOGIC; + SIGNAL wire_niOiO00l_dataout : STD_LOGIC; + SIGNAL wire_niOiO00O_dataout : STD_LOGIC; + SIGNAL wire_niOiO01i_dataout : STD_LOGIC; + SIGNAL wire_niOiO01l_dataout : STD_LOGIC; + SIGNAL wire_niOiO01O_dataout : STD_LOGIC; + SIGNAL wire_niOiO0ii_dataout : STD_LOGIC; + SIGNAL wire_niOiO0il_dataout : STD_LOGIC; + SIGNAL wire_niOiO0iO_dataout : STD_LOGIC; + SIGNAL wire_niOiO0li_dataout : STD_LOGIC; + SIGNAL wire_niOiO0ll_dataout : STD_LOGIC; + SIGNAL wire_niOiO0lO_dataout : STD_LOGIC; + SIGNAL wire_niOiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOiO0OO_dataout : STD_LOGIC; + SIGNAL wire_niOiO10i_dataout : STD_LOGIC; + SIGNAL wire_niOiO10O_dataout : STD_LOGIC; + SIGNAL wire_niOiO11i_dataout : STD_LOGIC; + SIGNAL wire_niOiO11l_dataout : STD_LOGIC; + SIGNAL wire_niOiO11O_dataout : STD_LOGIC; + SIGNAL wire_niOiO1ii_dataout : STD_LOGIC; + SIGNAL wire_niOiO1il_dataout : STD_LOGIC; + SIGNAL wire_niOiO1iO_dataout : STD_LOGIC; + SIGNAL wire_niOiO1li_dataout : STD_LOGIC; + SIGNAL wire_niOiO1ll_dataout : STD_LOGIC; + SIGNAL wire_niOiO1lO_dataout : STD_LOGIC; + SIGNAL wire_niOiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOiO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOiOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOiOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOiOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOiOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOiOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOiOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOiOiii_dataout : STD_LOGIC; + SIGNAL wire_niOiOiil_dataout : STD_LOGIC; + SIGNAL wire_niOiOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOiOil_dataout : STD_LOGIC; + SIGNAL wire_niOiOili_dataout : STD_LOGIC; + SIGNAL wire_niOiOill_dataout : STD_LOGIC; + SIGNAL wire_niOiOilO_dataout : STD_LOGIC; + SIGNAL wire_niOiOiO_dataout : STD_LOGIC; + SIGNAL wire_niOiOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOiOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOiOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOiOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOiOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOiOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOiOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOiOli_dataout : STD_LOGIC; + SIGNAL wire_niOiOlii_dataout : STD_LOGIC; + SIGNAL wire_niOiOll_dataout : STD_LOGIC; + SIGNAL wire_niOiOlO_dataout : STD_LOGIC; + SIGNAL wire_niOiOOi_dataout : STD_LOGIC; + SIGNAL wire_niOiOOl_dataout : STD_LOGIC; + SIGNAL wire_niOiOOO_dataout : STD_LOGIC; + SIGNAL wire_niOl000i_dataout : STD_LOGIC; + SIGNAL wire_niOl000l_dataout : STD_LOGIC; + SIGNAL wire_niOl000O_dataout : STD_LOGIC; + SIGNAL wire_niOl001i_dataout : STD_LOGIC; + SIGNAL wire_niOl001l_dataout : STD_LOGIC; + SIGNAL wire_niOl001O_dataout : STD_LOGIC; + SIGNAL wire_niOl00i_dataout : STD_LOGIC; + SIGNAL wire_niOl00ii_dataout : STD_LOGIC; + SIGNAL wire_niOl00il_dataout : STD_LOGIC; + SIGNAL wire_niOl00iO_dataout : STD_LOGIC; + SIGNAL wire_niOl00l_dataout : STD_LOGIC; + SIGNAL wire_niOl00li_dataout : STD_LOGIC; + SIGNAL wire_niOl00ll_dataout : STD_LOGIC; + SIGNAL wire_niOl00lO_dataout : STD_LOGIC; + SIGNAL wire_niOl00O_dataout : STD_LOGIC; + SIGNAL wire_niOl00Oi_dataout : STD_LOGIC; + SIGNAL wire_niOl00Ol_dataout : STD_LOGIC; + SIGNAL wire_niOl00OO_dataout : STD_LOGIC; + SIGNAL wire_niOl010i_dataout : STD_LOGIC; + SIGNAL wire_niOl010l_dataout : STD_LOGIC; + SIGNAL wire_niOl010O_dataout : STD_LOGIC; + SIGNAL wire_niOl011i_dataout : STD_LOGIC; + SIGNAL wire_niOl011l_dataout : STD_LOGIC; + SIGNAL wire_niOl011O_dataout : STD_LOGIC; + SIGNAL wire_niOl01i_dataout : STD_LOGIC; + SIGNAL wire_niOl01ii_dataout : STD_LOGIC; + SIGNAL wire_niOl01il_dataout : STD_LOGIC; + SIGNAL wire_niOl01iO_dataout : STD_LOGIC; + SIGNAL wire_niOl01l_dataout : STD_LOGIC; + SIGNAL wire_niOl01li_dataout : STD_LOGIC; + SIGNAL wire_niOl01ll_dataout : STD_LOGIC; + SIGNAL wire_niOl01lO_dataout : STD_LOGIC; + SIGNAL wire_niOl01O_dataout : STD_LOGIC; + SIGNAL wire_niOl01Oi_dataout : STD_LOGIC; + SIGNAL wire_niOl01Ol_dataout : STD_LOGIC; + SIGNAL wire_niOl01OO_dataout : STD_LOGIC; + SIGNAL wire_niOl0i0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0i0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0i0O_dataout : STD_LOGIC; + SIGNAL wire_niOl0i1i_dataout : STD_LOGIC; + SIGNAL wire_niOl0i1l_dataout : STD_LOGIC; + SIGNAL wire_niOl0i1O_dataout : STD_LOGIC; + SIGNAL wire_niOl0ii_dataout : STD_LOGIC; + SIGNAL wire_niOl0iii_dataout : STD_LOGIC; + SIGNAL wire_niOl0iil_dataout : STD_LOGIC; + SIGNAL wire_niOl0iiO_dataout : STD_LOGIC; + SIGNAL wire_niOl0il_dataout : STD_LOGIC; + SIGNAL wire_niOl0ili_dataout : STD_LOGIC; + SIGNAL wire_niOl0ill_dataout : STD_LOGIC; + SIGNAL wire_niOl0ilO_dataout : STD_LOGIC; + SIGNAL wire_niOl0iO_dataout : STD_LOGIC; + SIGNAL wire_niOl0iOi_dataout : STD_LOGIC; + SIGNAL wire_niOl0iOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0iOO_dataout : STD_LOGIC; + SIGNAL wire_niOl0l0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0l0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0l0O_dataout : STD_LOGIC; + SIGNAL wire_niOl0l1i_dataout : STD_LOGIC; + SIGNAL wire_niOl0l1l_dataout : STD_LOGIC; + SIGNAL wire_niOl0l1O_dataout : STD_LOGIC; + SIGNAL wire_niOl0li_dataout : STD_LOGIC; + SIGNAL wire_niOl0lii_dataout : STD_LOGIC; + SIGNAL wire_niOl0lil_dataout : STD_LOGIC; + SIGNAL wire_niOl0liO_dataout : STD_LOGIC; + SIGNAL wire_niOl0ll_dataout : STD_LOGIC; + SIGNAL wire_niOl0lli_dataout : STD_LOGIC; + SIGNAL wire_niOl0lll_dataout : STD_LOGIC; + SIGNAL wire_niOl0llO_dataout : STD_LOGIC; + SIGNAL wire_niOl0lO_dataout : STD_LOGIC; + SIGNAL wire_niOl0lOi_dataout : STD_LOGIC; + SIGNAL wire_niOl0lOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0lOO_dataout : STD_LOGIC; + SIGNAL wire_niOl0O0i_dataout : STD_LOGIC; + SIGNAL wire_niOl0O0l_dataout : STD_LOGIC; + SIGNAL wire_niOl0O0O_dataout : STD_LOGIC; + SIGNAL wire_niOl0O1i_dataout : STD_LOGIC; + SIGNAL wire_niOl0O1l_dataout : STD_LOGIC; + SIGNAL wire_niOl0O1O_dataout : STD_LOGIC; + SIGNAL wire_niOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOl0Oii_dataout : STD_LOGIC; + SIGNAL wire_niOl0Oil_dataout : STD_LOGIC; + SIGNAL wire_niOl0OiO_dataout : STD_LOGIC; + SIGNAL wire_niOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOl0Oli_dataout : STD_LOGIC; + SIGNAL wire_niOl0Oll_dataout : STD_LOGIC; + SIGNAL wire_niOl0OlO_dataout : STD_LOGIC; + SIGNAL wire_niOl0OO_dataout : STD_LOGIC; + SIGNAL wire_niOl0OOi_dataout : STD_LOGIC; + SIGNAL wire_niOl0OOl_dataout : STD_LOGIC; + SIGNAL wire_niOl0OOO_dataout : STD_LOGIC; + SIGNAL wire_niOl10i_dataout : STD_LOGIC; + SIGNAL wire_niOl10l_dataout : STD_LOGIC; + SIGNAL wire_niOl10O_dataout : STD_LOGIC; + SIGNAL wire_niOl10Ol_dataout : STD_LOGIC; + SIGNAL wire_niOl10OO_dataout : STD_LOGIC; + SIGNAL wire_niOl11i_dataout : STD_LOGIC; + SIGNAL wire_niOl11l_dataout : STD_LOGIC; + SIGNAL wire_niOl11O_dataout : STD_LOGIC; + SIGNAL wire_niOl1i0i_dataout : STD_LOGIC; + SIGNAL wire_niOl1i0l_dataout : STD_LOGIC; + SIGNAL wire_niOl1i0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1i1i_dataout : STD_LOGIC; + SIGNAL wire_niOl1i1l_dataout : STD_LOGIC; + SIGNAL wire_niOl1i1O_dataout : STD_LOGIC; + SIGNAL wire_niOl1ii_dataout : STD_LOGIC; + SIGNAL wire_niOl1iii_dataout : STD_LOGIC; + SIGNAL wire_niOl1iil_dataout : STD_LOGIC; + SIGNAL wire_niOl1iiO_dataout : STD_LOGIC; + SIGNAL wire_niOl1il_dataout : STD_LOGIC; + SIGNAL wire_niOl1ili_dataout : STD_LOGIC; + SIGNAL wire_niOl1ill_dataout : STD_LOGIC; + SIGNAL wire_niOl1ilO_dataout : STD_LOGIC; + SIGNAL wire_niOl1iO_dataout : STD_LOGIC; + SIGNAL wire_niOl1iOi_dataout : STD_LOGIC; + SIGNAL wire_niOl1iOl_dataout : STD_LOGIC; + SIGNAL wire_niOl1iOO_dataout : STD_LOGIC; + SIGNAL wire_niOl1l0i_dataout : STD_LOGIC; + SIGNAL wire_niOl1l0l_dataout : STD_LOGIC; + SIGNAL wire_niOl1l0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1l1i_dataout : STD_LOGIC; + SIGNAL wire_niOl1l1l_dataout : STD_LOGIC; + SIGNAL wire_niOl1l1O_dataout : STD_LOGIC; + SIGNAL wire_niOl1li_dataout : STD_LOGIC; + SIGNAL wire_niOl1lii_dataout : STD_LOGIC; + SIGNAL wire_niOl1lil_dataout : STD_LOGIC; + SIGNAL wire_niOl1liO_dataout : STD_LOGIC; + SIGNAL wire_niOl1ll_dataout : STD_LOGIC; + SIGNAL wire_niOl1lli_dataout : STD_LOGIC; + SIGNAL wire_niOl1lll_dataout : STD_LOGIC; + SIGNAL wire_niOl1llO_dataout : STD_LOGIC; + SIGNAL wire_niOl1lO_dataout : STD_LOGIC; + SIGNAL wire_niOl1lOi_dataout : STD_LOGIC; + SIGNAL wire_niOl1lOl_dataout : STD_LOGIC; + SIGNAL wire_niOl1lOO_dataout : STD_LOGIC; + SIGNAL wire_niOl1O0i_dataout : STD_LOGIC; + SIGNAL wire_niOl1O0l_dataout : STD_LOGIC; + SIGNAL wire_niOl1O0O_dataout : STD_LOGIC; + SIGNAL wire_niOl1O1i_dataout : STD_LOGIC; + SIGNAL wire_niOl1O1l_dataout : STD_LOGIC; + SIGNAL wire_niOl1O1O_dataout : STD_LOGIC; + SIGNAL wire_niOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOl1Oii_dataout : STD_LOGIC; + SIGNAL wire_niOl1Oil_dataout : STD_LOGIC; + SIGNAL wire_niOl1OiO_dataout : STD_LOGIC; + SIGNAL wire_niOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOl1Oli_dataout : STD_LOGIC; + SIGNAL wire_niOl1Oll_dataout : STD_LOGIC; + SIGNAL wire_niOl1OlO_dataout : STD_LOGIC; + SIGNAL wire_niOl1OO_dataout : STD_LOGIC; + SIGNAL wire_niOl1OOi_dataout : STD_LOGIC; + SIGNAL wire_niOl1OOl_dataout : STD_LOGIC; + SIGNAL wire_niOl1OOO_dataout : STD_LOGIC; + SIGNAL wire_niOli00i_dataout : STD_LOGIC; + SIGNAL wire_niOli00l_dataout : STD_LOGIC; + SIGNAL wire_niOli00O_dataout : STD_LOGIC; + SIGNAL wire_niOli01i_dataout : STD_LOGIC; + SIGNAL wire_niOli01l_dataout : STD_LOGIC; + SIGNAL wire_niOli01O_dataout : STD_LOGIC; + SIGNAL wire_niOli0i_dataout : STD_LOGIC; + SIGNAL wire_niOli0ii_dataout : STD_LOGIC; + SIGNAL wire_niOli0il_dataout : STD_LOGIC; + SIGNAL wire_niOli0iO_dataout : STD_LOGIC; + SIGNAL wire_niOli0l_dataout : STD_LOGIC; + SIGNAL wire_niOli0li_dataout : STD_LOGIC; + SIGNAL wire_niOli0ll_dataout : STD_LOGIC; + SIGNAL wire_niOli0lO_dataout : STD_LOGIC; + SIGNAL wire_niOli0O_dataout : STD_LOGIC; + SIGNAL wire_niOli0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOli0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOli0OO_dataout : STD_LOGIC; + SIGNAL wire_niOli10i_dataout : STD_LOGIC; + SIGNAL wire_niOli10l_dataout : STD_LOGIC; + SIGNAL wire_niOli10O_dataout : STD_LOGIC; + SIGNAL wire_niOli11i_dataout : STD_LOGIC; + SIGNAL wire_niOli11l_dataout : STD_LOGIC; + SIGNAL wire_niOli11O_dataout : STD_LOGIC; + SIGNAL wire_niOli1i_dataout : STD_LOGIC; + SIGNAL wire_niOli1ii_dataout : STD_LOGIC; + SIGNAL wire_niOli1il_dataout : STD_LOGIC; + SIGNAL wire_niOli1iO_dataout : STD_LOGIC; + SIGNAL wire_niOli1l_dataout : STD_LOGIC; + SIGNAL wire_niOli1li_dataout : STD_LOGIC; + SIGNAL wire_niOli1ll_dataout : STD_LOGIC; + SIGNAL wire_niOli1lO_dataout : STD_LOGIC; + SIGNAL wire_niOli1O_dataout : STD_LOGIC; + SIGNAL wire_niOli1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOli1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOli1OO_dataout : STD_LOGIC; + SIGNAL wire_niOlii1i_dataout : STD_LOGIC; + SIGNAL wire_niOliii_dataout : STD_LOGIC; + SIGNAL wire_niOliil_dataout : STD_LOGIC; + SIGNAL wire_niOliiO_dataout : STD_LOGIC; + SIGNAL wire_niOlili_dataout : STD_LOGIC; + SIGNAL wire_niOlill_dataout : STD_LOGIC; + SIGNAL wire_niOlilO_dataout : STD_LOGIC; + SIGNAL wire_niOliOi_dataout : STD_LOGIC; + SIGNAL wire_niOliOl_dataout : STD_LOGIC; + SIGNAL wire_niOliOll_dataout : STD_LOGIC; + SIGNAL wire_niOliOlO_dataout : STD_LOGIC; + SIGNAL wire_niOliOO_dataout : STD_LOGIC; + SIGNAL wire_niOliOOi_dataout : STD_LOGIC; + SIGNAL wire_niOliOOl_dataout : STD_LOGIC; + SIGNAL wire_niOliOOO_dataout : STD_LOGIC; + SIGNAL wire_niOll00i_dataout : STD_LOGIC; + SIGNAL wire_niOll00l_dataout : STD_LOGIC; + SIGNAL wire_niOll00O_dataout : STD_LOGIC; + SIGNAL wire_niOll01i_dataout : STD_LOGIC; + SIGNAL wire_niOll01l_dataout : STD_LOGIC; + SIGNAL wire_niOll01O_dataout : STD_LOGIC; + SIGNAL wire_niOll0i_dataout : STD_LOGIC; + SIGNAL wire_niOll0ii_dataout : STD_LOGIC; + SIGNAL wire_niOll0il_dataout : STD_LOGIC; + SIGNAL wire_niOll0iO_dataout : STD_LOGIC; + SIGNAL wire_niOll0l_dataout : STD_LOGIC; + SIGNAL wire_niOll0li_dataout : STD_LOGIC; + SIGNAL wire_niOll0ll_dataout : STD_LOGIC; + SIGNAL wire_niOll0lO_dataout : STD_LOGIC; + SIGNAL wire_niOll0O_dataout : STD_LOGIC; + SIGNAL wire_niOll0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOll0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOll0OO_dataout : STD_LOGIC; + SIGNAL wire_niOll10i_dataout : STD_LOGIC; + SIGNAL wire_niOll10l_dataout : STD_LOGIC; + SIGNAL wire_niOll10O_dataout : STD_LOGIC; + SIGNAL wire_niOll11i_dataout : STD_LOGIC; + SIGNAL wire_niOll11l_dataout : STD_LOGIC; + SIGNAL wire_niOll11O_dataout : STD_LOGIC; + SIGNAL wire_niOll1i_dataout : STD_LOGIC; + SIGNAL wire_niOll1ii_dataout : STD_LOGIC; + SIGNAL wire_niOll1il_dataout : STD_LOGIC; + SIGNAL wire_niOll1iO_dataout : STD_LOGIC; + SIGNAL wire_niOll1l_dataout : STD_LOGIC; + SIGNAL wire_niOll1li_dataout : STD_LOGIC; + SIGNAL wire_niOll1ll_dataout : STD_LOGIC; + SIGNAL wire_niOll1lO_dataout : STD_LOGIC; + SIGNAL wire_niOll1O_dataout : STD_LOGIC; + SIGNAL wire_niOll1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOll1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOll1OO_dataout : STD_LOGIC; + SIGNAL wire_niOlli0i_dataout : STD_LOGIC; + SIGNAL wire_niOlli0l_dataout : STD_LOGIC; + SIGNAL wire_niOlli0O_dataout : STD_LOGIC; + SIGNAL wire_niOlli1i_dataout : STD_LOGIC; + SIGNAL wire_niOlli1l_dataout : STD_LOGIC; + SIGNAL wire_niOlli1O_dataout : STD_LOGIC; + SIGNAL wire_niOllii_dataout : STD_LOGIC; + SIGNAL wire_niOlliii_dataout : STD_LOGIC; + SIGNAL wire_niOlliil_dataout : STD_LOGIC; + SIGNAL wire_niOlliiO_dataout : STD_LOGIC; + SIGNAL wire_niOllil_dataout : STD_LOGIC; + SIGNAL wire_niOllili_dataout : STD_LOGIC; + SIGNAL wire_niOllill_dataout : STD_LOGIC; + SIGNAL wire_niOllilO_dataout : STD_LOGIC; + SIGNAL wire_niOlliO_dataout : STD_LOGIC; + SIGNAL wire_niOlliOi_dataout : STD_LOGIC; + SIGNAL wire_niOlliOl_dataout : STD_LOGIC; + SIGNAL wire_niOlliOO_dataout : STD_LOGIC; + SIGNAL wire_niOlll0i_dataout : STD_LOGIC; + SIGNAL wire_niOlll0l_dataout : STD_LOGIC; + SIGNAL wire_niOlll0O_dataout : STD_LOGIC; + SIGNAL wire_niOlll1i_dataout : STD_LOGIC; + SIGNAL wire_niOlll1l_dataout : STD_LOGIC; + SIGNAL wire_niOlll1O_dataout : STD_LOGIC; + SIGNAL wire_niOllli_dataout : STD_LOGIC; + SIGNAL wire_niOlllii_dataout : STD_LOGIC; + SIGNAL wire_niOlllil_dataout : STD_LOGIC; + SIGNAL wire_niOllliO_dataout : STD_LOGIC; + SIGNAL wire_niOllll_dataout : STD_LOGIC; + SIGNAL wire_niOlllli_dataout : STD_LOGIC; + SIGNAL wire_niOlllll_dataout : STD_LOGIC; + SIGNAL wire_niOllllO_dataout : STD_LOGIC; + SIGNAL wire_niOlllO_dataout : STD_LOGIC; + SIGNAL wire_niOlllOi_dataout : STD_LOGIC; + SIGNAL wire_niOlllOl_dataout : STD_LOGIC; + SIGNAL wire_niOlllOO_dataout : STD_LOGIC; + SIGNAL wire_niOllO0i_dataout : STD_LOGIC; + SIGNAL wire_niOllO0l_dataout : STD_LOGIC; + SIGNAL wire_niOllO0O_dataout : STD_LOGIC; + SIGNAL wire_niOllO1i_dataout : STD_LOGIC; + SIGNAL wire_niOllO1l_dataout : STD_LOGIC; + SIGNAL wire_niOllO1O_dataout : STD_LOGIC; + SIGNAL wire_niOllOi_dataout : STD_LOGIC; + SIGNAL wire_niOllOii_dataout : STD_LOGIC; + SIGNAL wire_niOllOil_dataout : STD_LOGIC; + SIGNAL wire_niOllOiO_dataout : STD_LOGIC; + SIGNAL wire_niOllOl_dataout : STD_LOGIC; + SIGNAL wire_niOllOli_dataout : STD_LOGIC; + SIGNAL wire_niOllOll_dataout : STD_LOGIC; + SIGNAL wire_niOllOlO_dataout : STD_LOGIC; + SIGNAL wire_niOllOO_dataout : STD_LOGIC; + SIGNAL wire_niOllOOi_dataout : STD_LOGIC; + SIGNAL wire_niOllOOl_dataout : STD_LOGIC; + SIGNAL wire_niOllOOO_dataout : STD_LOGIC; + SIGNAL wire_niOlO00i_dataout : STD_LOGIC; + SIGNAL wire_niOlO00l_dataout : STD_LOGIC; + SIGNAL wire_niOlO00O_dataout : STD_LOGIC; + SIGNAL wire_niOlO01i_dataout : STD_LOGIC; + SIGNAL wire_niOlO01l_dataout : STD_LOGIC; + SIGNAL wire_niOlO01O_dataout : STD_LOGIC; + SIGNAL wire_niOlO0i_dataout : STD_LOGIC; + SIGNAL wire_niOlO0ii_dataout : STD_LOGIC; + SIGNAL wire_niOlO0il_dataout : STD_LOGIC; + SIGNAL wire_niOlO0iO_dataout : STD_LOGIC; + SIGNAL wire_niOlO0l_dataout : STD_LOGIC; + SIGNAL wire_niOlO0li_dataout : STD_LOGIC; + SIGNAL wire_niOlO0ll_dataout : STD_LOGIC; + SIGNAL wire_niOlO0lO_dataout : STD_LOGIC; + SIGNAL wire_niOlO0O_dataout : STD_LOGIC; + SIGNAL wire_niOlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOlO0OO_dataout : STD_LOGIC; + SIGNAL wire_niOlO10i_dataout : STD_LOGIC; + SIGNAL wire_niOlO10l_dataout : STD_LOGIC; + SIGNAL wire_niOlO10O_dataout : STD_LOGIC; + SIGNAL wire_niOlO11i_dataout : STD_LOGIC; + SIGNAL wire_niOlO11l_dataout : STD_LOGIC; + SIGNAL wire_niOlO11O_dataout : STD_LOGIC; + SIGNAL wire_niOlO1i_dataout : STD_LOGIC; + SIGNAL wire_niOlO1ii_dataout : STD_LOGIC; + SIGNAL wire_niOlO1il_dataout : STD_LOGIC; + SIGNAL wire_niOlO1iO_dataout : STD_LOGIC; + SIGNAL wire_niOlO1l_dataout : STD_LOGIC; + SIGNAL wire_niOlO1li_dataout : STD_LOGIC; + SIGNAL wire_niOlO1ll_dataout : STD_LOGIC; + SIGNAL wire_niOlO1lO_dataout : STD_LOGIC; + SIGNAL wire_niOlO1O_dataout : STD_LOGIC; + SIGNAL wire_niOlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOlO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOlOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOlOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOlOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOlOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOlOii_dataout : STD_LOGIC; + SIGNAL wire_niOlOiil_dataout : STD_LOGIC; + SIGNAL wire_niOlOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOlOil_dataout : STD_LOGIC; + SIGNAL wire_niOlOiO_dataout : STD_LOGIC; + SIGNAL wire_niOlOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOlOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOlOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOlOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOlOli_dataout : STD_LOGIC; + SIGNAL wire_niOlOlil_dataout : STD_LOGIC; + SIGNAL wire_niOlOliO_dataout : STD_LOGIC; + SIGNAL wire_niOlOll_dataout : STD_LOGIC; + SIGNAL wire_niOlOlli_dataout : STD_LOGIC; + SIGNAL wire_niOlOlO_dataout : STD_LOGIC; + SIGNAL wire_niOlOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOO0l_dataout : STD_LOGIC; + SIGNAL wire_niOlOO1i_dataout : STD_LOGIC; + SIGNAL wire_niOlOOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOOii_dataout : STD_LOGIC; + SIGNAL wire_niOlOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOlOOl_dataout : STD_LOGIC; + SIGNAL wire_niOlOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOlOOO_dataout : STD_LOGIC; + SIGNAL wire_niOlOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOlOOOO_dataout : STD_LOGIC; + SIGNAL wire_niOO000l_dataout : STD_LOGIC; + SIGNAL wire_niOO001O_dataout : STD_LOGIC; + SIGNAL wire_niOO00ii_dataout : STD_LOGIC; + SIGNAL wire_niOO00li_dataout : STD_LOGIC; + SIGNAL wire_niOO00ll_dataout : STD_LOGIC; + SIGNAL wire_niOO00OO_dataout : STD_LOGIC; + SIGNAL wire_niOO01i_dataout : STD_LOGIC; + SIGNAL wire_niOO01iO_dataout : STD_LOGIC; + SIGNAL wire_niOO01l_dataout : STD_LOGIC; + SIGNAL wire_niOO01li_dataout : STD_LOGIC; + SIGNAL wire_niOO01ll_dataout : STD_LOGIC; + SIGNAL wire_niOO01lO_dataout : STD_LOGIC; + SIGNAL wire_niOO01Oi_dataout : STD_LOGIC; + SIGNAL wire_niOO01Ol_dataout : STD_LOGIC; + SIGNAL wire_niOO0i0i_dataout : STD_LOGIC; + SIGNAL wire_niOO0i0O_dataout : STD_LOGIC; + SIGNAL wire_niOO0i1i_dataout : STD_LOGIC; + SIGNAL wire_niOO0i1l_dataout : STD_LOGIC; + SIGNAL wire_niOO0i1O_dataout : STD_LOGIC; + SIGNAL wire_niOO0iii_dataout : STD_LOGIC; + SIGNAL wire_niOO0iil_dataout : STD_LOGIC; + SIGNAL wire_niOO0iOl_dataout : STD_LOGIC; + SIGNAL wire_niOO0l0l_dataout : STD_LOGIC; + SIGNAL wire_niOO0l1O_dataout : STD_LOGIC; + SIGNAL wire_niOO0lii_dataout : STD_LOGIC; + SIGNAL wire_niOO0lli_dataout : STD_LOGIC; + SIGNAL wire_niOO0lll_dataout : STD_LOGIC; + SIGNAL wire_niOO0lOi_dataout : STD_LOGIC; + SIGNAL wire_niOO0lOl_dataout : STD_LOGIC; + SIGNAL wire_niOO0lOO_dataout : STD_LOGIC; + SIGNAL wire_niOO0O0i_dataout : STD_LOGIC; + SIGNAL wire_niOO0Oii_dataout : STD_LOGIC; + SIGNAL wire_niOO0Oiii_dataout : STD_LOGIC; + SIGNAL wire_niOO0Oiil_dataout : STD_LOGIC; + SIGNAL wire_niOO0OiiO_dataout : STD_LOGIC; + SIGNAL wire_niOO0Oili_dataout : STD_LOGIC; + SIGNAL wire_niOO0Oill_dataout : STD_LOGIC; + SIGNAL wire_niOO0OilO_dataout : STD_LOGIC; + SIGNAL wire_niOO0OiOi_dataout : STD_LOGIC; + SIGNAL wire_niOO0OiOl_dataout : STD_LOGIC; + SIGNAL wire_niOO0OiOO_dataout : STD_LOGIC; + SIGNAL wire_niOO0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_niOO0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_niOO0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_niOO0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_niOO0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_niOO0OliO_dataout : STD_LOGIC; + SIGNAL wire_niOO0Oll_dataout : STD_LOGIC; + SIGNAL wire_niOO0Olll_dataout : STD_LOGIC; + SIGNAL wire_niOO0OlOi_dataout : STD_LOGIC; + SIGNAL wire_niOO0OO1i_dataout : STD_LOGIC; + SIGNAL wire_niOO0OO1l_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOi_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOli_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOll_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOlO_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOO_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOOi_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOOl_dataout : STD_LOGIC; + SIGNAL wire_niOO0OOOO_dataout : STD_LOGIC; + SIGNAL wire_niOO100l_dataout : STD_LOGIC; + SIGNAL wire_niOO100O_dataout : STD_LOGIC; + SIGNAL wire_niOO101l_dataout : STD_LOGIC; + SIGNAL wire_niOO10i_dataout : STD_LOGIC; + SIGNAL wire_niOO10il_dataout : STD_LOGIC; + SIGNAL wire_niOO10iO_dataout : STD_LOGIC; + SIGNAL wire_niOO10l_dataout : STD_LOGIC; + SIGNAL wire_niOO10li_dataout : STD_LOGIC; + SIGNAL wire_niOO10O_dataout : STD_LOGIC; + SIGNAL wire_niOO10Ol_dataout : STD_LOGIC; + SIGNAL wire_niOO110O_dataout : STD_LOGIC; + SIGNAL wire_niOO111i_dataout : STD_LOGIC; + SIGNAL wire_niOO111l_dataout : STD_LOGIC; + SIGNAL wire_niOO11i_dataout : STD_LOGIC; + SIGNAL wire_niOO11iO_dataout : STD_LOGIC; + SIGNAL wire_niOO11l_dataout : STD_LOGIC; + SIGNAL wire_niOO11O_dataout : STD_LOGIC; + SIGNAL wire_niOO11Oi_dataout : STD_LOGIC; + SIGNAL wire_niOO11OO_dataout : STD_LOGIC; + SIGNAL wire_niOO1i0O_dataout : STD_LOGIC; + SIGNAL wire_niOO1i1l_dataout : STD_LOGIC; + SIGNAL wire_niOO1ii_dataout : STD_LOGIC; + SIGNAL wire_niOO1iil_dataout : STD_LOGIC; + SIGNAL wire_niOO1il_dataout : STD_LOGIC; + SIGNAL wire_niOO1ili_dataout : STD_LOGIC; + SIGNAL wire_niOO1iO_dataout : STD_LOGIC; + SIGNAL wire_niOO1iOi_dataout : STD_LOGIC; + SIGNAL wire_niOO1iOl_dataout : STD_LOGIC; + SIGNAL wire_niOO1l1i_dataout : STD_LOGIC; + SIGNAL wire_niOO1l1l_dataout : STD_LOGIC; + SIGNAL wire_niOO1l1O_dataout : STD_LOGIC; + SIGNAL wire_niOO1li_dataout : STD_LOGIC; + SIGNAL wire_niOO1lii_dataout : STD_LOGIC; + SIGNAL wire_niOO1ll_dataout : STD_LOGIC; + SIGNAL wire_niOO1lli_dataout : STD_LOGIC; + SIGNAL wire_niOO1lO_dataout : STD_LOGIC; + SIGNAL wire_niOO1lOl_dataout : STD_LOGIC; + SIGNAL wire_niOO1O0O_dataout : STD_LOGIC; + SIGNAL wire_niOO1O1i_dataout : STD_LOGIC; + SIGNAL wire_niOO1O1O_dataout : STD_LOGIC; + SIGNAL wire_niOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOO1Oii_dataout : STD_LOGIC; + SIGNAL wire_niOO1OiO_dataout : STD_LOGIC; + SIGNAL wire_niOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOO1Oli_dataout : STD_LOGIC; + SIGNAL wire_niOO1Oll_dataout : STD_LOGIC; + SIGNAL wire_niOO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOO1OOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi001l_dataout : STD_LOGIC; + SIGNAL wire_niOOi001O_dataout : STD_LOGIC; + SIGNAL wire_niOOi00i_dataout : STD_LOGIC; + SIGNAL wire_niOOi00O_dataout : STD_LOGIC; + SIGNAL wire_niOOi010i_dataout : STD_LOGIC; + SIGNAL wire_niOOi010l_dataout : STD_LOGIC; + SIGNAL wire_niOOi010O_dataout : STD_LOGIC; + SIGNAL wire_niOOi011i_dataout : STD_LOGIC; + SIGNAL wire_niOOi011l_dataout : STD_LOGIC; + SIGNAL wire_niOOi011O_dataout : STD_LOGIC; + SIGNAL wire_niOOi01li_dataout : STD_LOGIC; + SIGNAL wire_niOOi01lO_dataout : STD_LOGIC; + SIGNAL wire_niOOi01Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOi0i0O_dataout : STD_LOGIC; + SIGNAL wire_niOOi0iii_dataout : STD_LOGIC; + SIGNAL wire_niOOi0iil_dataout : STD_LOGIC; + SIGNAL wire_niOOi0iiO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0il_dataout : STD_LOGIC; + SIGNAL wire_niOOi0ili_dataout : STD_LOGIC; + SIGNAL wire_niOOi0ill_dataout : STD_LOGIC; + SIGNAL wire_niOOi0ilO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0iOi_dataout : STD_LOGIC; + SIGNAL wire_niOOi0iOl_dataout : STD_LOGIC; + SIGNAL wire_niOOi0iOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0l0i_dataout : STD_LOGIC; + SIGNAL wire_niOOi0l0l_dataout : STD_LOGIC; + SIGNAL wire_niOOi0l0O_dataout : STD_LOGIC; + SIGNAL wire_niOOi0l1i_dataout : STD_LOGIC; + SIGNAL wire_niOOi0l1l_dataout : STD_LOGIC; + SIGNAL wire_niOOi0l1O_dataout : STD_LOGIC; + SIGNAL wire_niOOi0lii_dataout : STD_LOGIC; + SIGNAL wire_niOOi0lil_dataout : STD_LOGIC; + SIGNAL wire_niOOi0liO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOi0lll_dataout : STD_LOGIC; + SIGNAL wire_niOOi0llO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0lOi_dataout : STD_LOGIC; + SIGNAL wire_niOOi0lOl_dataout : STD_LOGIC; + SIGNAL wire_niOOi0lOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0O0i_dataout : STD_LOGIC; + SIGNAL wire_niOOi0O0l_dataout : STD_LOGIC; + SIGNAL wire_niOOi0O0O_dataout : STD_LOGIC; + SIGNAL wire_niOOi0O1i_dataout : STD_LOGIC; + SIGNAL wire_niOOi0O1l_dataout : STD_LOGIC; + SIGNAL wire_niOOi0O1O_dataout : STD_LOGIC; + SIGNAL wire_niOOi0Oii_dataout : STD_LOGIC; + SIGNAL wire_niOOi0Oil_dataout : STD_LOGIC; + SIGNAL wire_niOOi0OiO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOi0Oli_dataout : STD_LOGIC; + SIGNAL wire_niOOi0Oll_dataout : STD_LOGIC; + SIGNAL wire_niOOi0OlO_dataout : STD_LOGIC; + SIGNAL wire_niOOi0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOi10i_dataout : STD_LOGIC; + SIGNAL wire_niOOi10O_dataout : STD_LOGIC; + SIGNAL wire_niOOi110l_dataout : STD_LOGIC; + SIGNAL wire_niOOi110O_dataout : STD_LOGIC; + SIGNAL wire_niOOi111i_dataout : STD_LOGIC; + SIGNAL wire_niOOi111l_dataout : STD_LOGIC; + SIGNAL wire_niOOi111O_dataout : STD_LOGIC; + SIGNAL wire_niOOi11ii_dataout : STD_LOGIC; + SIGNAL wire_niOOi11il_dataout : STD_LOGIC; + SIGNAL wire_niOOi11iO_dataout : STD_LOGIC; + SIGNAL wire_niOOi11li_dataout : STD_LOGIC; + SIGNAL wire_niOOi11ll_dataout : STD_LOGIC; + SIGNAL wire_niOOi11O_dataout : STD_LOGIC; + SIGNAL wire_niOOi1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOi1il_dataout : STD_LOGIC; + SIGNAL wire_niOOi1l0i_dataout : STD_LOGIC; + SIGNAL wire_niOOi1l0l_dataout : STD_LOGIC; + SIGNAL wire_niOOi1l0O_dataout : STD_LOGIC; + SIGNAL wire_niOOi1l1O_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lii_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lil_dataout : STD_LOGIC; + SIGNAL wire_niOOi1liO_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lli_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lll_dataout : STD_LOGIC; + SIGNAL wire_niOOi1llO_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lOi_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lOl_dataout : STD_LOGIC; + SIGNAL wire_niOOi1lOO_dataout : STD_LOGIC; + SIGNAL wire_niOOi1O0i_dataout : STD_LOGIC; + SIGNAL wire_niOOi1O0l_dataout : STD_LOGIC; + SIGNAL wire_niOOi1O0O_dataout : STD_LOGIC; + SIGNAL wire_niOOi1O1i_dataout : STD_LOGIC; + SIGNAL wire_niOOi1O1l_dataout : STD_LOGIC; + SIGNAL wire_niOOi1O1O_dataout : STD_LOGIC; + SIGNAL wire_niOOi1Oii_dataout : STD_LOGIC; + SIGNAL wire_niOOi1Oil_dataout : STD_LOGIC; + SIGNAL wire_niOOi1OiO_dataout : STD_LOGIC; + SIGNAL wire_niOOi1Oli_dataout : STD_LOGIC; + SIGNAL wire_niOOi1Oll_dataout : STD_LOGIC; + SIGNAL wire_niOOi1OlO_dataout : STD_LOGIC; + SIGNAL wire_niOOi1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOi1OOi_dataout : STD_LOGIC; + SIGNAL wire_niOOi1OOl_dataout : STD_LOGIC; + SIGNAL wire_niOOi1OOO_dataout : STD_LOGIC; + SIGNAL wire_niOOii00i_dataout : STD_LOGIC; + SIGNAL wire_niOOii00l_dataout : STD_LOGIC; + SIGNAL wire_niOOii00O_dataout : STD_LOGIC; + SIGNAL wire_niOOii01l_dataout : STD_LOGIC; + SIGNAL wire_niOOii01O_dataout : STD_LOGIC; + SIGNAL wire_niOOii0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOii0il_dataout : STD_LOGIC; + SIGNAL wire_niOOii0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOii0l_dataout : STD_LOGIC; + SIGNAL wire_niOOii0li_dataout : STD_LOGIC; + SIGNAL wire_niOOii0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOii0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOii0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOii0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOii0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOii1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiii0i_dataout : STD_LOGIC; + SIGNAL wire_niOOiii0l_dataout : STD_LOGIC; + SIGNAL wire_niOOiii0O_dataout : STD_LOGIC; + SIGNAL wire_niOOiii1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiii1l_dataout : STD_LOGIC; + SIGNAL wire_niOOiii1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiiiii_dataout : STD_LOGIC; + SIGNAL wire_niOOiiiil_dataout : STD_LOGIC; + SIGNAL wire_niOOiiiiO_dataout : STD_LOGIC; + SIGNAL wire_niOOiiili_dataout : STD_LOGIC; + SIGNAL wire_niOOiiill_dataout : STD_LOGIC; + SIGNAL wire_niOOiiilO_dataout : STD_LOGIC; + SIGNAL wire_niOOiiiOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiiiOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiiiOO_dataout : STD_LOGIC; + SIGNAL wire_niOOiil0i_dataout : STD_LOGIC; + SIGNAL wire_niOOiil0l_dataout : STD_LOGIC; + SIGNAL wire_niOOiil0O_dataout : STD_LOGIC; + SIGNAL wire_niOOiil1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiil1l_dataout : STD_LOGIC; + SIGNAL wire_niOOiil1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiilii_dataout : STD_LOGIC; + SIGNAL wire_niOOiilil_dataout : STD_LOGIC; + SIGNAL wire_niOOiiliO_dataout : STD_LOGIC; + SIGNAL wire_niOOiilli_dataout : STD_LOGIC; + SIGNAL wire_niOOiilll_dataout : STD_LOGIC; + SIGNAL wire_niOOiillO_dataout : STD_LOGIC; + SIGNAL wire_niOOiilOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiilOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiilOO_dataout : STD_LOGIC; + SIGNAL wire_niOOiiO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOiiO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOiiO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOiiO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiiO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOiiO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOii_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOil_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOli_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOll_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiiOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOil00i_dataout : STD_LOGIC; + SIGNAL wire_niOOil00l_dataout : STD_LOGIC; + SIGNAL wire_niOOil00O_dataout : STD_LOGIC; + SIGNAL wire_niOOil01i_dataout : STD_LOGIC; + SIGNAL wire_niOOil01l_dataout : STD_LOGIC; + SIGNAL wire_niOOil01O_dataout : STD_LOGIC; + SIGNAL wire_niOOil0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOil0il_dataout : STD_LOGIC; + SIGNAL wire_niOOil0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOil0li_dataout : STD_LOGIC; + SIGNAL wire_niOOil0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOil0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOil0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOil0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOil0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOil10i_dataout : STD_LOGIC; + SIGNAL wire_niOOil10l_dataout : STD_LOGIC; + SIGNAL wire_niOOil10O_dataout : STD_LOGIC; + SIGNAL wire_niOOil11i_dataout : STD_LOGIC; + SIGNAL wire_niOOil11l_dataout : STD_LOGIC; + SIGNAL wire_niOOil11O_dataout : STD_LOGIC; + SIGNAL wire_niOOil1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOil1il_dataout : STD_LOGIC; + SIGNAL wire_niOOil1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOil1li_dataout : STD_LOGIC; + SIGNAL wire_niOOil1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOil1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOil1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOil1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOil1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOili0i_dataout : STD_LOGIC; + SIGNAL wire_niOOili0l_dataout : STD_LOGIC; + SIGNAL wire_niOOili0O_dataout : STD_LOGIC; + SIGNAL wire_niOOili1i_dataout : STD_LOGIC; + SIGNAL wire_niOOili1l_dataout : STD_LOGIC; + SIGNAL wire_niOOili1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiliii_dataout : STD_LOGIC; + SIGNAL wire_niOOiliil_dataout : STD_LOGIC; + SIGNAL wire_niOOiliiO_dataout : STD_LOGIC; + SIGNAL wire_niOOilili_dataout : STD_LOGIC; + SIGNAL wire_niOOilill_dataout : STD_LOGIC; + SIGNAL wire_niOOililO_dataout : STD_LOGIC; + SIGNAL wire_niOOiliOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiliOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiliOO_dataout : STD_LOGIC; + SIGNAL wire_niOOill0i_dataout : STD_LOGIC; + SIGNAL wire_niOOill0l_dataout : STD_LOGIC; + SIGNAL wire_niOOill0O_dataout : STD_LOGIC; + SIGNAL wire_niOOill1i_dataout : STD_LOGIC; + SIGNAL wire_niOOill1l_dataout : STD_LOGIC; + SIGNAL wire_niOOill1O_dataout : STD_LOGIC; + SIGNAL wire_niOOillii_dataout : STD_LOGIC; + SIGNAL wire_niOOillil_dataout : STD_LOGIC; + SIGNAL wire_niOOilliO_dataout : STD_LOGIC; + SIGNAL wire_niOOillli_dataout : STD_LOGIC; + SIGNAL wire_niOOillll_dataout : STD_LOGIC; + SIGNAL wire_niOOilllO_dataout : STD_LOGIC; + SIGNAL wire_niOOillOi_dataout : STD_LOGIC; + SIGNAL wire_niOOillOl_dataout : STD_LOGIC; + SIGNAL wire_niOOillOO_dataout : STD_LOGIC; + SIGNAL wire_niOOilO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOilO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOilO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOilO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOilO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOilO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOilOii_dataout : STD_LOGIC; + SIGNAL wire_niOOilOil_dataout : STD_LOGIC; + SIGNAL wire_niOOilOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOilOli_dataout : STD_LOGIC; + SIGNAL wire_niOOilOll_dataout : STD_LOGIC; + SIGNAL wire_niOOilOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOilOO_dataout : STD_LOGIC; + SIGNAL wire_niOOilOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOilOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOilOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOiO00i_dataout : STD_LOGIC; + SIGNAL wire_niOOiO00l_dataout : STD_LOGIC; + SIGNAL wire_niOOiO00O_dataout : STD_LOGIC; + SIGNAL wire_niOOiO01i_dataout : STD_LOGIC; + SIGNAL wire_niOOiO01l_dataout : STD_LOGIC; + SIGNAL wire_niOOiO01O_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0il_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0li_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOiO0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOiO10i_dataout : STD_LOGIC; + SIGNAL wire_niOOiO10l_dataout : STD_LOGIC; + SIGNAL wire_niOOiO10O_dataout : STD_LOGIC; + SIGNAL wire_niOOiO11i_dataout : STD_LOGIC; + SIGNAL wire_niOOiO11l_dataout : STD_LOGIC; + SIGNAL wire_niOOiO11O_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1il_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1li_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOiO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOOiOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOOiOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOOiOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOOiOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiOii_dataout : STD_LOGIC; + SIGNAL wire_niOOiOiii_dataout : STD_LOGIC; + SIGNAL wire_niOOiOiil_dataout : STD_LOGIC; + SIGNAL wire_niOOiOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOil_dataout : STD_LOGIC; + SIGNAL wire_niOOiOili_dataout : STD_LOGIC; + SIGNAL wire_niOOiOill_dataout : STD_LOGIC; + SIGNAL wire_niOOiOilO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOOiOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOOiOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOOiOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOOiOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiOli_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlii_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlil_dataout : STD_LOGIC; + SIGNAL wire_niOOiOliO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOll_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlli_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlll_dataout : STD_LOGIC; + SIGNAL wire_niOOiOllO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiOlOO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOiOO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOiOO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOiOO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOiOO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOiOO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOii_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOil_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOli_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOiOOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOl000i_dataout : STD_LOGIC; + SIGNAL wire_niOOl000l_dataout : STD_LOGIC; + SIGNAL wire_niOOl000O_dataout : STD_LOGIC; + SIGNAL wire_niOOl001i_dataout : STD_LOGIC; + SIGNAL wire_niOOl001l_dataout : STD_LOGIC; + SIGNAL wire_niOOl001O_dataout : STD_LOGIC; + SIGNAL wire_niOOl00ii_dataout : STD_LOGIC; + SIGNAL wire_niOOl00il_dataout : STD_LOGIC; + SIGNAL wire_niOOl00iO_dataout : STD_LOGIC; + SIGNAL wire_niOOl00li_dataout : STD_LOGIC; + SIGNAL wire_niOOl00ll_dataout : STD_LOGIC; + SIGNAL wire_niOOl00lO_dataout : STD_LOGIC; + SIGNAL wire_niOOl00Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOl00Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOl00OO_dataout : STD_LOGIC; + SIGNAL wire_niOOl010i_dataout : STD_LOGIC; + SIGNAL wire_niOOl010l_dataout : STD_LOGIC; + SIGNAL wire_niOOl010O_dataout : STD_LOGIC; + SIGNAL wire_niOOl011i_dataout : STD_LOGIC; + SIGNAL wire_niOOl011l_dataout : STD_LOGIC; + SIGNAL wire_niOOl011O_dataout : STD_LOGIC; + SIGNAL wire_niOOl01ii_dataout : STD_LOGIC; + SIGNAL wire_niOOl01il_dataout : STD_LOGIC; + SIGNAL wire_niOOl01iO_dataout : STD_LOGIC; + SIGNAL wire_niOOl01l_dataout : STD_LOGIC; + SIGNAL wire_niOOl01li_dataout : STD_LOGIC; + SIGNAL wire_niOOl01ll_dataout : STD_LOGIC; + SIGNAL wire_niOOl01lO_dataout : STD_LOGIC; + SIGNAL wire_niOOl01O_dataout : STD_LOGIC; + SIGNAL wire_niOOl01Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOl01Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOl01OO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0i0i_dataout : STD_LOGIC; + SIGNAL wire_niOOl0i0l_dataout : STD_LOGIC; + SIGNAL wire_niOOl0i0O_dataout : STD_LOGIC; + SIGNAL wire_niOOl0i1i_dataout : STD_LOGIC; + SIGNAL wire_niOOl0i1l_dataout : STD_LOGIC; + SIGNAL wire_niOOl0i1O_dataout : STD_LOGIC; + SIGNAL wire_niOOl0iii_dataout : STD_LOGIC; + SIGNAL wire_niOOl0iil_dataout : STD_LOGIC; + SIGNAL wire_niOOl0iiO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0ili_dataout : STD_LOGIC; + SIGNAL wire_niOOl0ill_dataout : STD_LOGIC; + SIGNAL wire_niOOl0ilO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0iOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl0iOl_dataout : STD_LOGIC; + SIGNAL wire_niOOl0iOO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0l0i_dataout : STD_LOGIC; + SIGNAL wire_niOOl0l0l_dataout : STD_LOGIC; + SIGNAL wire_niOOl0l0O_dataout : STD_LOGIC; + SIGNAL wire_niOOl0l1i_dataout : STD_LOGIC; + SIGNAL wire_niOOl0l1l_dataout : STD_LOGIC; + SIGNAL wire_niOOl0l1O_dataout : STD_LOGIC; + SIGNAL wire_niOOl0lii_dataout : STD_LOGIC; + SIGNAL wire_niOOl0lil_dataout : STD_LOGIC; + SIGNAL wire_niOOl0liO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0lli_dataout : STD_LOGIC; + SIGNAL wire_niOOl0lll_dataout : STD_LOGIC; + SIGNAL wire_niOOl0llO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0lOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl0lOl_dataout : STD_LOGIC; + SIGNAL wire_niOOl0lOO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0O0i_dataout : STD_LOGIC; + SIGNAL wire_niOOl0O0l_dataout : STD_LOGIC; + SIGNAL wire_niOOl0O0O_dataout : STD_LOGIC; + SIGNAL wire_niOOl0O1i_dataout : STD_LOGIC; + SIGNAL wire_niOOl0O1l_dataout : STD_LOGIC; + SIGNAL wire_niOOl0O1O_dataout : STD_LOGIC; + SIGNAL wire_niOOl0Oii_dataout : STD_LOGIC; + SIGNAL wire_niOOl0Oil_dataout : STD_LOGIC; + SIGNAL wire_niOOl0OiO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0Oli_dataout : STD_LOGIC; + SIGNAL wire_niOOl0Oll_dataout : STD_LOGIC; + SIGNAL wire_niOOl0OlO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOl0OOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl0OOl_dataout : STD_LOGIC; + SIGNAL wire_niOOl0OOO_dataout : STD_LOGIC; + SIGNAL wire_niOOl100i_dataout : STD_LOGIC; + SIGNAL wire_niOOl100l_dataout : STD_LOGIC; + SIGNAL wire_niOOl100O_dataout : STD_LOGIC; + SIGNAL wire_niOOl101i_dataout : STD_LOGIC; + SIGNAL wire_niOOl101l_dataout : STD_LOGIC; + SIGNAL wire_niOOl101O_dataout : STD_LOGIC; + SIGNAL wire_niOOl10i_dataout : STD_LOGIC; + SIGNAL wire_niOOl10ii_dataout : STD_LOGIC; + SIGNAL wire_niOOl10il_dataout : STD_LOGIC; + SIGNAL wire_niOOl10iO_dataout : STD_LOGIC; + SIGNAL wire_niOOl10l_dataout : STD_LOGIC; + SIGNAL wire_niOOl10li_dataout : STD_LOGIC; + SIGNAL wire_niOOl10ll_dataout : STD_LOGIC; + SIGNAL wire_niOOl10lO_dataout : STD_LOGIC; + SIGNAL wire_niOOl10O_dataout : STD_LOGIC; + SIGNAL wire_niOOl10Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOl10Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOl10OO_dataout : STD_LOGIC; + SIGNAL wire_niOOl110i_dataout : STD_LOGIC; + SIGNAL wire_niOOl110l_dataout : STD_LOGIC; + SIGNAL wire_niOOl110O_dataout : STD_LOGIC; + SIGNAL wire_niOOl111i_dataout : STD_LOGIC; + SIGNAL wire_niOOl111l_dataout : STD_LOGIC; + SIGNAL wire_niOOl111O_dataout : STD_LOGIC; + SIGNAL wire_niOOl11i_dataout : STD_LOGIC; + SIGNAL wire_niOOl11ii_dataout : STD_LOGIC; + SIGNAL wire_niOOl11il_dataout : STD_LOGIC; + SIGNAL wire_niOOl11iO_dataout : STD_LOGIC; + SIGNAL wire_niOOl11l_dataout : STD_LOGIC; + SIGNAL wire_niOOl11li_dataout : STD_LOGIC; + SIGNAL wire_niOOl11ll_dataout : STD_LOGIC; + SIGNAL wire_niOOl11lO_dataout : STD_LOGIC; + SIGNAL wire_niOOl11O_dataout : STD_LOGIC; + SIGNAL wire_niOOl11Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOl11Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOl11OO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1i0i_dataout : STD_LOGIC; + SIGNAL wire_niOOl1i0l_dataout : STD_LOGIC; + SIGNAL wire_niOOl1i0O_dataout : STD_LOGIC; + SIGNAL wire_niOOl1i1i_dataout : STD_LOGIC; + SIGNAL wire_niOOl1i1l_dataout : STD_LOGIC; + SIGNAL wire_niOOl1i1O_dataout : STD_LOGIC; + SIGNAL wire_niOOl1iii_dataout : STD_LOGIC; + SIGNAL wire_niOOl1iil_dataout : STD_LOGIC; + SIGNAL wire_niOOl1iiO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1ili_dataout : STD_LOGIC; + SIGNAL wire_niOOl1ill_dataout : STD_LOGIC; + SIGNAL wire_niOOl1ilO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1iOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl1iOl_dataout : STD_LOGIC; + SIGNAL wire_niOOl1iOO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1l0i_dataout : STD_LOGIC; + SIGNAL wire_niOOl1l0l_dataout : STD_LOGIC; + SIGNAL wire_niOOl1l0O_dataout : STD_LOGIC; + SIGNAL wire_niOOl1l1i_dataout : STD_LOGIC; + SIGNAL wire_niOOl1l1l_dataout : STD_LOGIC; + SIGNAL wire_niOOl1l1O_dataout : STD_LOGIC; + SIGNAL wire_niOOl1li_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lii_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lil_dataout : STD_LOGIC; + SIGNAL wire_niOOl1liO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lli_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lll_dataout : STD_LOGIC; + SIGNAL wire_niOOl1llO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lOl_dataout : STD_LOGIC; + SIGNAL wire_niOOl1lOO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1O0i_dataout : STD_LOGIC; + SIGNAL wire_niOOl1O0l_dataout : STD_LOGIC; + SIGNAL wire_niOOl1O0O_dataout : STD_LOGIC; + SIGNAL wire_niOOl1O1i_dataout : STD_LOGIC; + SIGNAL wire_niOOl1O1l_dataout : STD_LOGIC; + SIGNAL wire_niOOl1O1O_dataout : STD_LOGIC; + SIGNAL wire_niOOl1Oii_dataout : STD_LOGIC; + SIGNAL wire_niOOl1Oil_dataout : STD_LOGIC; + SIGNAL wire_niOOl1OiO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOl1Oli_dataout : STD_LOGIC; + SIGNAL wire_niOOl1Oll_dataout : STD_LOGIC; + SIGNAL wire_niOOl1OlO_dataout : STD_LOGIC; + SIGNAL wire_niOOl1OOi_dataout : STD_LOGIC; + SIGNAL wire_niOOl1OOl_dataout : STD_LOGIC; + SIGNAL wire_niOOl1OOO_dataout : STD_LOGIC; + SIGNAL wire_niOOli00i_dataout : STD_LOGIC; + SIGNAL wire_niOOli00l_dataout : STD_LOGIC; + SIGNAL wire_niOOli00O_dataout : STD_LOGIC; + SIGNAL wire_niOOli01i_dataout : STD_LOGIC; + SIGNAL wire_niOOli01l_dataout : STD_LOGIC; + SIGNAL wire_niOOli01O_dataout : STD_LOGIC; + SIGNAL wire_niOOli0i_dataout : STD_LOGIC; + SIGNAL wire_niOOli0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOli0il_dataout : STD_LOGIC; + SIGNAL wire_niOOli0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOli0l_dataout : STD_LOGIC; + SIGNAL wire_niOOli0li_dataout : STD_LOGIC; + SIGNAL wire_niOOli0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOli0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOli0O_dataout : STD_LOGIC; + SIGNAL wire_niOOli0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOli0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOli0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOli10i_dataout : STD_LOGIC; + SIGNAL wire_niOOli10l_dataout : STD_LOGIC; + SIGNAL wire_niOOli10O_dataout : STD_LOGIC; + SIGNAL wire_niOOli11i_dataout : STD_LOGIC; + SIGNAL wire_niOOli11l_dataout : STD_LOGIC; + SIGNAL wire_niOOli11O_dataout : STD_LOGIC; + SIGNAL wire_niOOli1i_dataout : STD_LOGIC; + SIGNAL wire_niOOli1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOli1il_dataout : STD_LOGIC; + SIGNAL wire_niOOli1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOli1l_dataout : STD_LOGIC; + SIGNAL wire_niOOli1li_dataout : STD_LOGIC; + SIGNAL wire_niOOli1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOli1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOli1O_dataout : STD_LOGIC; + SIGNAL wire_niOOli1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOli1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOli1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOlii0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlii0l_dataout : STD_LOGIC; + SIGNAL wire_niOOlii0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlii1i_dataout : STD_LOGIC; + SIGNAL wire_niOOlii1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlii1O_dataout : STD_LOGIC; + SIGNAL wire_niOOliii_dataout : STD_LOGIC; + SIGNAL wire_niOOliiii_dataout : STD_LOGIC; + SIGNAL wire_niOOliiil_dataout : STD_LOGIC; + SIGNAL wire_niOOliiiO_dataout : STD_LOGIC; + SIGNAL wire_niOOliil_dataout : STD_LOGIC; + SIGNAL wire_niOOliili_dataout : STD_LOGIC; + SIGNAL wire_niOOliill_dataout : STD_LOGIC; + SIGNAL wire_niOOliilO_dataout : STD_LOGIC; + SIGNAL wire_niOOliiO_dataout : STD_LOGIC; + SIGNAL wire_niOOliiOi_dataout : STD_LOGIC; + SIGNAL wire_niOOliiOl_dataout : STD_LOGIC; + SIGNAL wire_niOOliiOO_dataout : STD_LOGIC; + SIGNAL wire_niOOlil0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlil0l_dataout : STD_LOGIC; + SIGNAL wire_niOOlil0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlil1i_dataout : STD_LOGIC; + SIGNAL wire_niOOlil1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlil1O_dataout : STD_LOGIC; + SIGNAL wire_niOOlili_dataout : STD_LOGIC; + SIGNAL wire_niOOlilii_dataout : STD_LOGIC; + SIGNAL wire_niOOlilil_dataout : STD_LOGIC; + SIGNAL wire_niOOliliO_dataout : STD_LOGIC; + SIGNAL wire_niOOlill_dataout : STD_LOGIC; + SIGNAL wire_niOOlilli_dataout : STD_LOGIC; + SIGNAL wire_niOOlilll_dataout : STD_LOGIC; + SIGNAL wire_niOOlillO_dataout : STD_LOGIC; + SIGNAL wire_niOOlilO_dataout : STD_LOGIC; + SIGNAL wire_niOOlilOi_dataout : STD_LOGIC; + SIGNAL wire_niOOlilOl_dataout : STD_LOGIC; + SIGNAL wire_niOOlilOO_dataout : STD_LOGIC; + SIGNAL wire_niOOliO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOliO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOliO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOliO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOliO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOliO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOliOii_dataout : STD_LOGIC; + SIGNAL wire_niOOliOil_dataout : STD_LOGIC; + SIGNAL wire_niOOliOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOliOl_dataout : STD_LOGIC; + SIGNAL wire_niOOliOli_dataout : STD_LOGIC; + SIGNAL wire_niOOliOll_dataout : STD_LOGIC; + SIGNAL wire_niOOliOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOliOO_dataout : STD_LOGIC; + SIGNAL wire_niOOliOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOliOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOliOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOll00i_dataout : STD_LOGIC; + SIGNAL wire_niOOll00l_dataout : STD_LOGIC; + SIGNAL wire_niOOll00O_dataout : STD_LOGIC; + SIGNAL wire_niOOll01i_dataout : STD_LOGIC; + SIGNAL wire_niOOll01l_dataout : STD_LOGIC; + SIGNAL wire_niOOll01O_dataout : STD_LOGIC; + SIGNAL wire_niOOll0i_dataout : STD_LOGIC; + SIGNAL wire_niOOll0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOll0il_dataout : STD_LOGIC; + SIGNAL wire_niOOll0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOll0l_dataout : STD_LOGIC; + SIGNAL wire_niOOll0li_dataout : STD_LOGIC; + SIGNAL wire_niOOll0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOll0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOll0O_dataout : STD_LOGIC; + SIGNAL wire_niOOll0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOll0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOll0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOll10i_dataout : STD_LOGIC; + SIGNAL wire_niOOll10l_dataout : STD_LOGIC; + SIGNAL wire_niOOll10O_dataout : STD_LOGIC; + SIGNAL wire_niOOll11i_dataout : STD_LOGIC; + SIGNAL wire_niOOll11l_dataout : STD_LOGIC; + SIGNAL wire_niOOll11O_dataout : STD_LOGIC; + SIGNAL wire_niOOll1i_dataout : STD_LOGIC; + SIGNAL wire_niOOll1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOll1il_dataout : STD_LOGIC; + SIGNAL wire_niOOll1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOll1l_dataout : STD_LOGIC; + SIGNAL wire_niOOll1li_dataout : STD_LOGIC; + SIGNAL wire_niOOll1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOll1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOll1O_dataout : STD_LOGIC; + SIGNAL wire_niOOll1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOll1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOll1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOlli0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlli0l_dataout : STD_LOGIC; + SIGNAL wire_niOOlli0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlli1i_dataout : STD_LOGIC; + SIGNAL wire_niOOlli1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlli1O_dataout : STD_LOGIC; + SIGNAL wire_niOOllii_dataout : STD_LOGIC; + SIGNAL wire_niOOlliii_dataout : STD_LOGIC; + SIGNAL wire_niOOlliil_dataout : STD_LOGIC; + SIGNAL wire_niOOlliiO_dataout : STD_LOGIC; + SIGNAL wire_niOOllil_dataout : STD_LOGIC; + SIGNAL wire_niOOllili_dataout : STD_LOGIC; + SIGNAL wire_niOOllill_dataout : STD_LOGIC; + SIGNAL wire_niOOllilO_dataout : STD_LOGIC; + SIGNAL wire_niOOlliO_dataout : STD_LOGIC; + SIGNAL wire_niOOlliOi_dataout : STD_LOGIC; + SIGNAL wire_niOOlliOl_dataout : STD_LOGIC; + SIGNAL wire_niOOlliOO_dataout : STD_LOGIC; + SIGNAL wire_niOOlll0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlll0l_dataout : STD_LOGIC; + SIGNAL wire_niOOlll0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlll1i_dataout : STD_LOGIC; + SIGNAL wire_niOOlll1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlll1O_dataout : STD_LOGIC; + SIGNAL wire_niOOlllii_dataout : STD_LOGIC; + SIGNAL wire_niOOlllil_dataout : STD_LOGIC; + SIGNAL wire_niOOllliO_dataout : STD_LOGIC; + SIGNAL wire_niOOlllli_dataout : STD_LOGIC; + SIGNAL wire_niOOlllll_dataout : STD_LOGIC; + SIGNAL wire_niOOllllO_dataout : STD_LOGIC; + SIGNAL wire_niOOlllO_dataout : STD_LOGIC; + SIGNAL wire_niOOlllOi_dataout : STD_LOGIC; + SIGNAL wire_niOOlllOl_dataout : STD_LOGIC; + SIGNAL wire_niOOlllOO_dataout : STD_LOGIC; + SIGNAL wire_niOOllO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOllO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOllO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOllO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOllO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOllO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOllOi_dataout : STD_LOGIC; + SIGNAL wire_niOOllOii_dataout : STD_LOGIC; + SIGNAL wire_niOOllOil_dataout : STD_LOGIC; + SIGNAL wire_niOOllOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOllOli_dataout : STD_LOGIC; + SIGNAL wire_niOOllOll_dataout : STD_LOGIC; + SIGNAL wire_niOOllOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOllOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOllOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOllOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOlO00i_dataout : STD_LOGIC; + SIGNAL wire_niOOlO00l_dataout : STD_LOGIC; + SIGNAL wire_niOOlO00O_dataout : STD_LOGIC; + SIGNAL wire_niOOlO01i_dataout : STD_LOGIC; + SIGNAL wire_niOOlO01l_dataout : STD_LOGIC; + SIGNAL wire_niOOlO01O_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0il_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0li_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOlO0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOlO10i_dataout : STD_LOGIC; + SIGNAL wire_niOOlO10l_dataout : STD_LOGIC; + SIGNAL wire_niOOlO10O_dataout : STD_LOGIC; + SIGNAL wire_niOOlO11i_dataout : STD_LOGIC; + SIGNAL wire_niOOlO11l_dataout : STD_LOGIC; + SIGNAL wire_niOOlO11O_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1il_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1li_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOlO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOOlOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOOlOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOOlOiii_dataout : STD_LOGIC; + SIGNAL wire_niOOlOiil_dataout : STD_LOGIC; + SIGNAL wire_niOOlOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOili_dataout : STD_LOGIC; + SIGNAL wire_niOOlOill_dataout : STD_LOGIC; + SIGNAL wire_niOOlOilO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOOlOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOOlOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOOlOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOOlOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOOlOli_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlii_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlil_dataout : STD_LOGIC; + SIGNAL wire_niOOlOliO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlli_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlll_dataout : STD_LOGIC; + SIGNAL wire_niOOlOllO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlOl_dataout : STD_LOGIC; + SIGNAL wire_niOOlOlOO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOlOO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOlOO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOlOO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOlOO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOlOO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOii_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOil_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOli_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOlOOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOO000i_dataout : STD_LOGIC; + SIGNAL wire_niOOO000l_dataout : STD_LOGIC; + SIGNAL wire_niOOO000O_dataout : STD_LOGIC; + SIGNAL wire_niOOO001i_dataout : STD_LOGIC; + SIGNAL wire_niOOO001l_dataout : STD_LOGIC; + SIGNAL wire_niOOO001O_dataout : STD_LOGIC; + SIGNAL wire_niOOO00i_dataout : STD_LOGIC; + SIGNAL wire_niOOO00ii_dataout : STD_LOGIC; + SIGNAL wire_niOOO00il_dataout : STD_LOGIC; + SIGNAL wire_niOOO00iO_dataout : STD_LOGIC; + SIGNAL wire_niOOO00l_dataout : STD_LOGIC; + SIGNAL wire_niOOO00li_dataout : STD_LOGIC; + SIGNAL wire_niOOO00ll_dataout : STD_LOGIC; + SIGNAL wire_niOOO00lO_dataout : STD_LOGIC; + SIGNAL wire_niOOO00O_dataout : STD_LOGIC; + SIGNAL wire_niOOO00Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOO00Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOO00OO_dataout : STD_LOGIC; + SIGNAL wire_niOOO010i_dataout : STD_LOGIC; + SIGNAL wire_niOOO010l_dataout : STD_LOGIC; + SIGNAL wire_niOOO010O_dataout : STD_LOGIC; + SIGNAL wire_niOOO011i_dataout : STD_LOGIC; + SIGNAL wire_niOOO011l_dataout : STD_LOGIC; + SIGNAL wire_niOOO011O_dataout : STD_LOGIC; + SIGNAL wire_niOOO01i_dataout : STD_LOGIC; + SIGNAL wire_niOOO01ii_dataout : STD_LOGIC; + SIGNAL wire_niOOO01il_dataout : STD_LOGIC; + SIGNAL wire_niOOO01iO_dataout : STD_LOGIC; + SIGNAL wire_niOOO01l_dataout : STD_LOGIC; + SIGNAL wire_niOOO01li_dataout : STD_LOGIC; + SIGNAL wire_niOOO01ll_dataout : STD_LOGIC; + SIGNAL wire_niOOO01lO_dataout : STD_LOGIC; + SIGNAL wire_niOOO01Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOO01Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOO01OO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0i0i_dataout : STD_LOGIC; + SIGNAL wire_niOOO0i0l_dataout : STD_LOGIC; + SIGNAL wire_niOOO0i0O_dataout : STD_LOGIC; + SIGNAL wire_niOOO0i1i_dataout : STD_LOGIC; + SIGNAL wire_niOOO0i1l_dataout : STD_LOGIC; + SIGNAL wire_niOOO0i1O_dataout : STD_LOGIC; + SIGNAL wire_niOOO0iii_dataout : STD_LOGIC; + SIGNAL wire_niOOO0iil_dataout : STD_LOGIC; + SIGNAL wire_niOOO0iiO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0ili_dataout : STD_LOGIC; + SIGNAL wire_niOOO0ill_dataout : STD_LOGIC; + SIGNAL wire_niOOO0ilO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0iOi_dataout : STD_LOGIC; + SIGNAL wire_niOOO0iOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO0iOO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0l0i_dataout : STD_LOGIC; + SIGNAL wire_niOOO0l0l_dataout : STD_LOGIC; + SIGNAL wire_niOOO0l0O_dataout : STD_LOGIC; + SIGNAL wire_niOOO0l1i_dataout : STD_LOGIC; + SIGNAL wire_niOOO0l1l_dataout : STD_LOGIC; + SIGNAL wire_niOOO0l1O_dataout : STD_LOGIC; + SIGNAL wire_niOOO0li_dataout : STD_LOGIC; + SIGNAL wire_niOOO0lii_dataout : STD_LOGIC; + SIGNAL wire_niOOO0lil_dataout : STD_LOGIC; + SIGNAL wire_niOOO0liO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0lli_dataout : STD_LOGIC; + SIGNAL wire_niOOO0lll_dataout : STD_LOGIC; + SIGNAL wire_niOOO0llO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0lOi_dataout : STD_LOGIC; + SIGNAL wire_niOOO0lOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO0lOO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0O0i_dataout : STD_LOGIC; + SIGNAL wire_niOOO0O0l_dataout : STD_LOGIC; + SIGNAL wire_niOOO0O0O_dataout : STD_LOGIC; + SIGNAL wire_niOOO0O1i_dataout : STD_LOGIC; + SIGNAL wire_niOOO0O1l_dataout : STD_LOGIC; + SIGNAL wire_niOOO0O1O_dataout : STD_LOGIC; + SIGNAL wire_niOOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOO0Oii_dataout : STD_LOGIC; + SIGNAL wire_niOOO0Oil_dataout : STD_LOGIC; + SIGNAL wire_niOOO0OiO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOO0Oli_dataout : STD_LOGIC; + SIGNAL wire_niOOO0Oll_dataout : STD_LOGIC; + SIGNAL wire_niOOO0OlO_dataout : STD_LOGIC; + SIGNAL wire_niOOO0OOi_dataout : STD_LOGIC; + SIGNAL wire_niOOO0OOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO0OOO_dataout : STD_LOGIC; + SIGNAL wire_niOOO100i_dataout : STD_LOGIC; + SIGNAL wire_niOOO100l_dataout : STD_LOGIC; + SIGNAL wire_niOOO100O_dataout : STD_LOGIC; + SIGNAL wire_niOOO101i_dataout : STD_LOGIC; + SIGNAL wire_niOOO101l_dataout : STD_LOGIC; + SIGNAL wire_niOOO101O_dataout : STD_LOGIC; + SIGNAL wire_niOOO10ii_dataout : STD_LOGIC; + SIGNAL wire_niOOO10il_dataout : STD_LOGIC; + SIGNAL wire_niOOO10iO_dataout : STD_LOGIC; + SIGNAL wire_niOOO10l_dataout : STD_LOGIC; + SIGNAL wire_niOOO10li_dataout : STD_LOGIC; + SIGNAL wire_niOOO10ll_dataout : STD_LOGIC; + SIGNAL wire_niOOO10lO_dataout : STD_LOGIC; + SIGNAL wire_niOOO10Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOO10Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOO10OO_dataout : STD_LOGIC; + SIGNAL wire_niOOO110i_dataout : STD_LOGIC; + SIGNAL wire_niOOO110l_dataout : STD_LOGIC; + SIGNAL wire_niOOO110O_dataout : STD_LOGIC; + SIGNAL wire_niOOO111i_dataout : STD_LOGIC; + SIGNAL wire_niOOO111l_dataout : STD_LOGIC; + SIGNAL wire_niOOO111O_dataout : STD_LOGIC; + SIGNAL wire_niOOO11ii_dataout : STD_LOGIC; + SIGNAL wire_niOOO11il_dataout : STD_LOGIC; + SIGNAL wire_niOOO11iO_dataout : STD_LOGIC; + SIGNAL wire_niOOO11l_dataout : STD_LOGIC; + SIGNAL wire_niOOO11li_dataout : STD_LOGIC; + SIGNAL wire_niOOO11ll_dataout : STD_LOGIC; + SIGNAL wire_niOOO11lO_dataout : STD_LOGIC; + SIGNAL wire_niOOO11Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOO11Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOO11OO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1i0i_dataout : STD_LOGIC; + SIGNAL wire_niOOO1i0l_dataout : STD_LOGIC; + SIGNAL wire_niOOO1i0O_dataout : STD_LOGIC; + SIGNAL wire_niOOO1i1i_dataout : STD_LOGIC; + SIGNAL wire_niOOO1i1l_dataout : STD_LOGIC; + SIGNAL wire_niOOO1i1O_dataout : STD_LOGIC; + SIGNAL wire_niOOO1iii_dataout : STD_LOGIC; + SIGNAL wire_niOOO1iil_dataout : STD_LOGIC; + SIGNAL wire_niOOO1iiO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1ili_dataout : STD_LOGIC; + SIGNAL wire_niOOO1ill_dataout : STD_LOGIC; + SIGNAL wire_niOOO1ilO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1iOi_dataout : STD_LOGIC; + SIGNAL wire_niOOO1iOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO1iOO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1l0i_dataout : STD_LOGIC; + SIGNAL wire_niOOO1l0l_dataout : STD_LOGIC; + SIGNAL wire_niOOO1l0O_dataout : STD_LOGIC; + SIGNAL wire_niOOO1l1i_dataout : STD_LOGIC; + SIGNAL wire_niOOO1l1l_dataout : STD_LOGIC; + SIGNAL wire_niOOO1l1O_dataout : STD_LOGIC; + SIGNAL wire_niOOO1lii_dataout : STD_LOGIC; + SIGNAL wire_niOOO1lil_dataout : STD_LOGIC; + SIGNAL wire_niOOO1liO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOO1lli_dataout : STD_LOGIC; + SIGNAL wire_niOOO1lll_dataout : STD_LOGIC; + SIGNAL wire_niOOO1llO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1lOi_dataout : STD_LOGIC; + SIGNAL wire_niOOO1lOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO1lOO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1O0i_dataout : STD_LOGIC; + SIGNAL wire_niOOO1O0l_dataout : STD_LOGIC; + SIGNAL wire_niOOO1O0O_dataout : STD_LOGIC; + SIGNAL wire_niOOO1O1i_dataout : STD_LOGIC; + SIGNAL wire_niOOO1O1l_dataout : STD_LOGIC; + SIGNAL wire_niOOO1O1O_dataout : STD_LOGIC; + SIGNAL wire_niOOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOO1Oii_dataout : STD_LOGIC; + SIGNAL wire_niOOO1Oil_dataout : STD_LOGIC; + SIGNAL wire_niOOO1OiO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1Oli_dataout : STD_LOGIC; + SIGNAL wire_niOOO1Oll_dataout : STD_LOGIC; + SIGNAL wire_niOOO1OlO_dataout : STD_LOGIC; + SIGNAL wire_niOOO1OOi_dataout : STD_LOGIC; + SIGNAL wire_niOOO1OOl_dataout : STD_LOGIC; + SIGNAL wire_niOOO1OOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi00i_dataout : STD_LOGIC; + SIGNAL wire_niOOOi00l_dataout : STD_LOGIC; + SIGNAL wire_niOOOi00O_dataout : STD_LOGIC; + SIGNAL wire_niOOOi01i_dataout : STD_LOGIC; + SIGNAL wire_niOOOi01l_dataout : STD_LOGIC; + SIGNAL wire_niOOOi01O_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0il_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0li_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOOi0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi10i_dataout : STD_LOGIC; + SIGNAL wire_niOOOi10l_dataout : STD_LOGIC; + SIGNAL wire_niOOOi10O_dataout : STD_LOGIC; + SIGNAL wire_niOOOi11i_dataout : STD_LOGIC; + SIGNAL wire_niOOOi11l_dataout : STD_LOGIC; + SIGNAL wire_niOOOi11O_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1il_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1li_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOOi1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOOii0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOii0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOii0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOii1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOii1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOii1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOiii_dataout : STD_LOGIC; + SIGNAL wire_niOOOiiii_dataout : STD_LOGIC; + SIGNAL wire_niOOOiiil_dataout : STD_LOGIC; + SIGNAL wire_niOOOiiiO_dataout : STD_LOGIC; + SIGNAL wire_niOOOiili_dataout : STD_LOGIC; + SIGNAL wire_niOOOiill_dataout : STD_LOGIC; + SIGNAL wire_niOOOiilO_dataout : STD_LOGIC; + SIGNAL wire_niOOOiiOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOiiOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOiiOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOil0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOil0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOil0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOil1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOil1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOil1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOili_dataout : STD_LOGIC; + SIGNAL wire_niOOOilii_dataout : STD_LOGIC; + SIGNAL wire_niOOOilil_dataout : STD_LOGIC; + SIGNAL wire_niOOOiliO_dataout : STD_LOGIC; + SIGNAL wire_niOOOill_dataout : STD_LOGIC; + SIGNAL wire_niOOOilli_dataout : STD_LOGIC; + SIGNAL wire_niOOOilll_dataout : STD_LOGIC; + SIGNAL wire_niOOOillO_dataout : STD_LOGIC; + SIGNAL wire_niOOOilOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOilOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOilOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOOiO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOiO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOiO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOiO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOiO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOiO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOii_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOil_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOli_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOll_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOiOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOl00i_dataout : STD_LOGIC; + SIGNAL wire_niOOOl00l_dataout : STD_LOGIC; + SIGNAL wire_niOOOl00O_dataout : STD_LOGIC; + SIGNAL wire_niOOOl01i_dataout : STD_LOGIC; + SIGNAL wire_niOOOl01l_dataout : STD_LOGIC; + SIGNAL wire_niOOOl01O_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0il_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0li_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOOl0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOOl10i_dataout : STD_LOGIC; + SIGNAL wire_niOOOl10l_dataout : STD_LOGIC; + SIGNAL wire_niOOOl10O_dataout : STD_LOGIC; + SIGNAL wire_niOOOl11i_dataout : STD_LOGIC; + SIGNAL wire_niOOOl11l_dataout : STD_LOGIC; + SIGNAL wire_niOOOl11O_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1il_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1li_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOOl1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOOli_dataout : STD_LOGIC; + SIGNAL wire_niOOOli0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOli0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOli0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOli1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOli1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOli1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOliii_dataout : STD_LOGIC; + SIGNAL wire_niOOOliil_dataout : STD_LOGIC; + SIGNAL wire_niOOOliiO_dataout : STD_LOGIC; + SIGNAL wire_niOOOlili_dataout : STD_LOGIC; + SIGNAL wire_niOOOlill_dataout : STD_LOGIC; + SIGNAL wire_niOOOlilO_dataout : STD_LOGIC; + SIGNAL wire_niOOOliOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOliOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOliOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOOll0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOll0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOll0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOll1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOll1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOll1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOllii_dataout : STD_LOGIC; + SIGNAL wire_niOOOllil_dataout : STD_LOGIC; + SIGNAL wire_niOOOlliO_dataout : STD_LOGIC; + SIGNAL wire_niOOOllli_dataout : STD_LOGIC; + SIGNAL wire_niOOOllll_dataout : STD_LOGIC; + SIGNAL wire_niOOOlllO_dataout : STD_LOGIC; + SIGNAL wire_niOOOllOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOllOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOllOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOOlO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOlO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOlO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOlO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOlO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOlO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOii_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOil_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOli_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOll_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOlOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOO00i_dataout : STD_LOGIC; + SIGNAL wire_niOOOO00l_dataout : STD_LOGIC; + SIGNAL wire_niOOOO00O_dataout : STD_LOGIC; + SIGNAL wire_niOOOO01i_dataout : STD_LOGIC; + SIGNAL wire_niOOOO01l_dataout : STD_LOGIC; + SIGNAL wire_niOOOO01O_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0ii_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0il_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0iO_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0li_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0ll_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0lO_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOOO0OO_dataout : STD_LOGIC; + SIGNAL wire_niOOOO10i_dataout : STD_LOGIC; + SIGNAL wire_niOOOO10l_dataout : STD_LOGIC; + SIGNAL wire_niOOOO10O_dataout : STD_LOGIC; + SIGNAL wire_niOOOO11i_dataout : STD_LOGIC; + SIGNAL wire_niOOOO11l_dataout : STD_LOGIC; + SIGNAL wire_niOOOO11O_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1ii_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1il_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1iO_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1li_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1ll_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1lO_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_niOOOO1OO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOOi0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOOi0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOOi0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOOi1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOOi1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOOi1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOOii_dataout : STD_LOGIC; + SIGNAL wire_niOOOOiii_dataout : STD_LOGIC; + SIGNAL wire_niOOOOiil_dataout : STD_LOGIC; + SIGNAL wire_niOOOOiiO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOili_dataout : STD_LOGIC; + SIGNAL wire_niOOOOill_dataout : STD_LOGIC; + SIGNAL wire_niOOOOilO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOiOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOOiOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOOiOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOOl0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOOl0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOOl0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOOl1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOOl1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOOl1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOOlii_dataout : STD_LOGIC; + SIGNAL wire_niOOOOlil_dataout : STD_LOGIC; + SIGNAL wire_niOOOOliO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOOOlli_dataout : STD_LOGIC; + SIGNAL wire_niOOOOlll_dataout : STD_LOGIC; + SIGNAL wire_niOOOOllO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOlOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOOlOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOOlOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOO0i_dataout : STD_LOGIC; + SIGNAL wire_niOOOOO0l_dataout : STD_LOGIC; + SIGNAL wire_niOOOOO0O_dataout : STD_LOGIC; + SIGNAL wire_niOOOOO1i_dataout : STD_LOGIC; + SIGNAL wire_niOOOOO1l_dataout : STD_LOGIC; + SIGNAL wire_niOOOOO1O_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOii_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOil_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOiO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOli_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOll_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOlO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOO_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOOi_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOOl_dataout : STD_LOGIC; + SIGNAL wire_niOOOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl000000i_dataout : STD_LOGIC; + SIGNAL wire_nl000000l_dataout : STD_LOGIC; + SIGNAL wire_nl000000O_dataout : STD_LOGIC; + SIGNAL wire_nl000001i_dataout : STD_LOGIC; + SIGNAL wire_nl000001l_dataout : STD_LOGIC; + SIGNAL wire_nl000001O_dataout : STD_LOGIC; + SIGNAL wire_nl00000i_dataout : STD_LOGIC; + SIGNAL wire_nl00000ii_dataout : STD_LOGIC; + SIGNAL wire_nl00000il_dataout : STD_LOGIC; + SIGNAL wire_nl00000iO_dataout : STD_LOGIC; + SIGNAL wire_nl00000l_dataout : STD_LOGIC; + SIGNAL wire_nl00000li_dataout : STD_LOGIC; + SIGNAL wire_nl00000ll_dataout : STD_LOGIC; + SIGNAL wire_nl00000lO_dataout : STD_LOGIC; + SIGNAL wire_nl00000O_dataout : STD_LOGIC; + SIGNAL wire_nl00000Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00000Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00000OO_dataout : STD_LOGIC; + SIGNAL wire_nl000010i_dataout : STD_LOGIC; + SIGNAL wire_nl000010l_dataout : STD_LOGIC; + SIGNAL wire_nl000010O_dataout : STD_LOGIC; + SIGNAL wire_nl000011i_dataout : STD_LOGIC; + SIGNAL wire_nl000011l_dataout : STD_LOGIC; + SIGNAL wire_nl000011O_dataout : STD_LOGIC; + SIGNAL wire_nl00001i_dataout : STD_LOGIC; + SIGNAL wire_nl00001ii_dataout : STD_LOGIC; + SIGNAL wire_nl00001il_dataout : STD_LOGIC; + SIGNAL wire_nl00001iO_dataout : STD_LOGIC; + SIGNAL wire_nl00001l_dataout : STD_LOGIC; + SIGNAL wire_nl00001li_dataout : STD_LOGIC; + SIGNAL wire_nl00001ll_dataout : STD_LOGIC; + SIGNAL wire_nl00001lO_dataout : STD_LOGIC; + SIGNAL wire_nl00001O_dataout : STD_LOGIC; + SIGNAL wire_nl00001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00001Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00001OO_dataout : STD_LOGIC; + SIGNAL wire_nl0000i_dataout : STD_LOGIC; + SIGNAL wire_nl0000i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0000i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0000i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0000i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0000i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0000i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0000iii_dataout : STD_LOGIC; + SIGNAL wire_nl0000iil_dataout : STD_LOGIC; + SIGNAL wire_nl0000iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0000ili_dataout : STD_LOGIC; + SIGNAL wire_nl0000ill_dataout : STD_LOGIC; + SIGNAL wire_nl0000ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0000iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0000iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0000iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0000l_dataout : STD_LOGIC; + SIGNAL wire_nl0000l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0000l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0000l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0000l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0000l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0000l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0000lii_dataout : STD_LOGIC; + SIGNAL wire_nl0000lil_dataout : STD_LOGIC; + SIGNAL wire_nl0000liO_dataout : STD_LOGIC; + SIGNAL wire_nl0000lli_dataout : STD_LOGIC; + SIGNAL wire_nl0000lll_dataout : STD_LOGIC; + SIGNAL wire_nl0000llO_dataout : STD_LOGIC; + SIGNAL wire_nl0000lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0000lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0000lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0000O_dataout : STD_LOGIC; + SIGNAL wire_nl0000O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0000O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0000O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0000O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0000O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0000O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0000Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0000Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0000OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0000Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0000Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0000OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0000OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0000OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0000OOO_dataout : STD_LOGIC; + SIGNAL wire_nl000100i_dataout : STD_LOGIC; + SIGNAL wire_nl000100l_dataout : STD_LOGIC; + SIGNAL wire_nl000100O_dataout : STD_LOGIC; + SIGNAL wire_nl000101i_dataout : STD_LOGIC; + SIGNAL wire_nl000101l_dataout : STD_LOGIC; + SIGNAL wire_nl000101O_dataout : STD_LOGIC; + SIGNAL wire_nl00010i_dataout : STD_LOGIC; + SIGNAL wire_nl00010ii_dataout : STD_LOGIC; + SIGNAL wire_nl00010il_dataout : STD_LOGIC; + SIGNAL wire_nl00010iO_dataout : STD_LOGIC; + SIGNAL wire_nl00010l_dataout : STD_LOGIC; + SIGNAL wire_nl00010li_dataout : STD_LOGIC; + SIGNAL wire_nl00010ll_dataout : STD_LOGIC; + SIGNAL wire_nl00010lO_dataout : STD_LOGIC; + SIGNAL wire_nl00010O_dataout : STD_LOGIC; + SIGNAL wire_nl00010Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00010Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00010OO_dataout : STD_LOGIC; + SIGNAL wire_nl000110i_dataout : STD_LOGIC; + SIGNAL wire_nl000110l_dataout : STD_LOGIC; + SIGNAL wire_nl000110O_dataout : STD_LOGIC; + SIGNAL wire_nl000111i_dataout : STD_LOGIC; + SIGNAL wire_nl000111l_dataout : STD_LOGIC; + SIGNAL wire_nl000111O_dataout : STD_LOGIC; + SIGNAL wire_nl00011i_dataout : STD_LOGIC; + SIGNAL wire_nl00011ii_dataout : STD_LOGIC; + SIGNAL wire_nl00011il_dataout : STD_LOGIC; + SIGNAL wire_nl00011iO_dataout : STD_LOGIC; + SIGNAL wire_nl00011l_dataout : STD_LOGIC; + SIGNAL wire_nl00011li_dataout : STD_LOGIC; + SIGNAL wire_nl00011ll_dataout : STD_LOGIC; + SIGNAL wire_nl00011lO_dataout : STD_LOGIC; + SIGNAL wire_nl00011O_dataout : STD_LOGIC; + SIGNAL wire_nl00011Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00011Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00011OO_dataout : STD_LOGIC; + SIGNAL wire_nl0001i_dataout : STD_LOGIC; + SIGNAL wire_nl0001i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0001i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0001i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0001i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0001i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0001i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0001ii_dataout : STD_LOGIC; + SIGNAL wire_nl0001iii_dataout : STD_LOGIC; + SIGNAL wire_nl0001iil_dataout : STD_LOGIC; + SIGNAL wire_nl0001iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0001il_dataout : STD_LOGIC; + SIGNAL wire_nl0001ili_dataout : STD_LOGIC; + SIGNAL wire_nl0001ill_dataout : STD_LOGIC; + SIGNAL wire_nl0001ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0001iO_dataout : STD_LOGIC; + SIGNAL wire_nl0001iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0001iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0001iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0001l_dataout : STD_LOGIC; + SIGNAL wire_nl0001l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0001l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0001l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0001l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0001l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0001l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0001li_dataout : STD_LOGIC; + SIGNAL wire_nl0001lii_dataout : STD_LOGIC; + SIGNAL wire_nl0001lil_dataout : STD_LOGIC; + SIGNAL wire_nl0001liO_dataout : STD_LOGIC; + SIGNAL wire_nl0001ll_dataout : STD_LOGIC; + SIGNAL wire_nl0001lli_dataout : STD_LOGIC; + SIGNAL wire_nl0001lll_dataout : STD_LOGIC; + SIGNAL wire_nl0001llO_dataout : STD_LOGIC; + SIGNAL wire_nl0001lO_dataout : STD_LOGIC; + SIGNAL wire_nl0001lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0001lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0001lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0001O_dataout : STD_LOGIC; + SIGNAL wire_nl0001O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0001O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0001O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0001O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0001O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0001O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0001Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0001Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0001OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0001Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0001Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0001Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0001OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0001OO_dataout : STD_LOGIC; + SIGNAL wire_nl0001OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0001OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0001OOO_dataout : STD_LOGIC; + SIGNAL wire_nl000i00i_dataout : STD_LOGIC; + SIGNAL wire_nl000i00l_dataout : STD_LOGIC; + SIGNAL wire_nl000i00O_dataout : STD_LOGIC; + SIGNAL wire_nl000i01i_dataout : STD_LOGIC; + SIGNAL wire_nl000i01l_dataout : STD_LOGIC; + SIGNAL wire_nl000i01O_dataout : STD_LOGIC; + SIGNAL wire_nl000i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl000i0il_dataout : STD_LOGIC; + SIGNAL wire_nl000i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl000i0li_dataout : STD_LOGIC; + SIGNAL wire_nl000i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl000i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl000i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl000i10i_dataout : STD_LOGIC; + SIGNAL wire_nl000i10l_dataout : STD_LOGIC; + SIGNAL wire_nl000i10O_dataout : STD_LOGIC; + SIGNAL wire_nl000i11i_dataout : STD_LOGIC; + SIGNAL wire_nl000i11l_dataout : STD_LOGIC; + SIGNAL wire_nl000i11O_dataout : STD_LOGIC; + SIGNAL wire_nl000i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl000i1il_dataout : STD_LOGIC; + SIGNAL wire_nl000i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl000i1li_dataout : STD_LOGIC; + SIGNAL wire_nl000i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl000i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl000i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl000ii_dataout : STD_LOGIC; + SIGNAL wire_nl000ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl000ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl000ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl000ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl000ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl000ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl000iiii_dataout : STD_LOGIC; + SIGNAL wire_nl000iiil_dataout : STD_LOGIC; + SIGNAL wire_nl000iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl000iili_dataout : STD_LOGIC; + SIGNAL wire_nl000iill_dataout : STD_LOGIC; + SIGNAL wire_nl000iilO_dataout : STD_LOGIC; + SIGNAL wire_nl000iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl000iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl000iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl000il_dataout : STD_LOGIC; + SIGNAL wire_nl000il0i_dataout : STD_LOGIC; + SIGNAL wire_nl000il0l_dataout : STD_LOGIC; + SIGNAL wire_nl000il0O_dataout : STD_LOGIC; + SIGNAL wire_nl000il1i_dataout : STD_LOGIC; + SIGNAL wire_nl000il1l_dataout : STD_LOGIC; + SIGNAL wire_nl000il1O_dataout : STD_LOGIC; + SIGNAL wire_nl000ilii_dataout : STD_LOGIC; + SIGNAL wire_nl000ilil_dataout : STD_LOGIC; + SIGNAL wire_nl000iliO_dataout : STD_LOGIC; + SIGNAL wire_nl000illi_dataout : STD_LOGIC; + SIGNAL wire_nl000illl_dataout : STD_LOGIC; + SIGNAL wire_nl000illO_dataout : STD_LOGIC; + SIGNAL wire_nl000ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl000ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl000ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl000iO_dataout : STD_LOGIC; + SIGNAL wire_nl000iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl000iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl000iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl000iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl000iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl000iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl000iOii_dataout : STD_LOGIC; + SIGNAL wire_nl000iOil_dataout : STD_LOGIC; + SIGNAL wire_nl000iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl000iOli_dataout : STD_LOGIC; + SIGNAL wire_nl000iOll_dataout : STD_LOGIC; + SIGNAL wire_nl000iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl000iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl000iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl000iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl000l00i_dataout : STD_LOGIC; + SIGNAL wire_nl000l00l_dataout : STD_LOGIC; + SIGNAL wire_nl000l00O_dataout : STD_LOGIC; + SIGNAL wire_nl000l01i_dataout : STD_LOGIC; + SIGNAL wire_nl000l01l_dataout : STD_LOGIC; + SIGNAL wire_nl000l01O_dataout : STD_LOGIC; + SIGNAL wire_nl000l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl000l0il_dataout : STD_LOGIC; + SIGNAL wire_nl000l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl000l0li_dataout : STD_LOGIC; + SIGNAL wire_nl000l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl000l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl000l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl000l10i_dataout : STD_LOGIC; + SIGNAL wire_nl000l10l_dataout : STD_LOGIC; + SIGNAL wire_nl000l10O_dataout : STD_LOGIC; + SIGNAL wire_nl000l11i_dataout : STD_LOGIC; + SIGNAL wire_nl000l11l_dataout : STD_LOGIC; + SIGNAL wire_nl000l11O_dataout : STD_LOGIC; + SIGNAL wire_nl000l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl000l1il_dataout : STD_LOGIC; + SIGNAL wire_nl000l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl000l1li_dataout : STD_LOGIC; + SIGNAL wire_nl000l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl000l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl000l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl000li_dataout : STD_LOGIC; + SIGNAL wire_nl000li0i_dataout : STD_LOGIC; + SIGNAL wire_nl000li0l_dataout : STD_LOGIC; + SIGNAL wire_nl000li0O_dataout : STD_LOGIC; + SIGNAL wire_nl000li1i_dataout : STD_LOGIC; + SIGNAL wire_nl000li1l_dataout : STD_LOGIC; + SIGNAL wire_nl000li1O_dataout : STD_LOGIC; + SIGNAL wire_nl000liii_dataout : STD_LOGIC; + SIGNAL wire_nl000liil_dataout : STD_LOGIC; + SIGNAL wire_nl000liiO_dataout : STD_LOGIC; + SIGNAL wire_nl000lili_dataout : STD_LOGIC; + SIGNAL wire_nl000lill_dataout : STD_LOGIC; + SIGNAL wire_nl000lilO_dataout : STD_LOGIC; + SIGNAL wire_nl000liOi_dataout : STD_LOGIC; + SIGNAL wire_nl000liOl_dataout : STD_LOGIC; + SIGNAL wire_nl000liOO_dataout : STD_LOGIC; + SIGNAL wire_nl000ll_dataout : STD_LOGIC; + SIGNAL wire_nl000ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl000ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl000ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl000ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl000ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl000ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl000llii_dataout : STD_LOGIC; + SIGNAL wire_nl000llil_dataout : STD_LOGIC; + SIGNAL wire_nl000lliO_dataout : STD_LOGIC; + SIGNAL wire_nl000llli_dataout : STD_LOGIC; + SIGNAL wire_nl000llll_dataout : STD_LOGIC; + SIGNAL wire_nl000lllO_dataout : STD_LOGIC; + SIGNAL wire_nl000llOi_dataout : STD_LOGIC; + SIGNAL wire_nl000llOl_dataout : STD_LOGIC; + SIGNAL wire_nl000llOO_dataout : STD_LOGIC; + SIGNAL wire_nl000lO_dataout : STD_LOGIC; + SIGNAL wire_nl000lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl000lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl000lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl000lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl000lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl000lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl000lOii_dataout : STD_LOGIC; + SIGNAL wire_nl000lOil_dataout : STD_LOGIC; + SIGNAL wire_nl000lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl000lOli_dataout : STD_LOGIC; + SIGNAL wire_nl000lOll_dataout : STD_LOGIC; + SIGNAL wire_nl000lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl000lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl000lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl000lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl000O00i_dataout : STD_LOGIC; + SIGNAL wire_nl000O00l_dataout : STD_LOGIC; + SIGNAL wire_nl000O00O_dataout : STD_LOGIC; + SIGNAL wire_nl000O01i_dataout : STD_LOGIC; + SIGNAL wire_nl000O01l_dataout : STD_LOGIC; + SIGNAL wire_nl000O01O_dataout : STD_LOGIC; + SIGNAL wire_nl000O0i_dataout : STD_LOGIC; + SIGNAL wire_nl000O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl000O0il_dataout : STD_LOGIC; + SIGNAL wire_nl000O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl000O0l_dataout : STD_LOGIC; + SIGNAL wire_nl000O0li_dataout : STD_LOGIC; + SIGNAL wire_nl000O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl000O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl000O0O_dataout : STD_LOGIC; + SIGNAL wire_nl000O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl000O10i_dataout : STD_LOGIC; + SIGNAL wire_nl000O10l_dataout : STD_LOGIC; + SIGNAL wire_nl000O10O_dataout : STD_LOGIC; + SIGNAL wire_nl000O11i_dataout : STD_LOGIC; + SIGNAL wire_nl000O11l_dataout : STD_LOGIC; + SIGNAL wire_nl000O11O_dataout : STD_LOGIC; + SIGNAL wire_nl000O1i_dataout : STD_LOGIC; + SIGNAL wire_nl000O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl000O1il_dataout : STD_LOGIC; + SIGNAL wire_nl000O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl000O1l_dataout : STD_LOGIC; + SIGNAL wire_nl000O1li_dataout : STD_LOGIC; + SIGNAL wire_nl000O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl000O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl000O1O_dataout : STD_LOGIC; + SIGNAL wire_nl000O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl000Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl000Oii_dataout : STD_LOGIC; + SIGNAL wire_nl000Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl000Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl000OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl000Oil_dataout : STD_LOGIC; + SIGNAL wire_nl000Oili_dataout : STD_LOGIC; + SIGNAL wire_nl000Oill_dataout : STD_LOGIC; + SIGNAL wire_nl000OilO_dataout : STD_LOGIC; + SIGNAL wire_nl000OiO_dataout : STD_LOGIC; + SIGNAL wire_nl000OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl000OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl000OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl000Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl000Oli_dataout : STD_LOGIC; + SIGNAL wire_nl000Olii_dataout : STD_LOGIC; + SIGNAL wire_nl000Olil_dataout : STD_LOGIC; + SIGNAL wire_nl000OliO_dataout : STD_LOGIC; + SIGNAL wire_nl000Oll_dataout : STD_LOGIC; + SIGNAL wire_nl000Olli_dataout : STD_LOGIC; + SIGNAL wire_nl000Olll_dataout : STD_LOGIC; + SIGNAL wire_nl000OllO_dataout : STD_LOGIC; + SIGNAL wire_nl000OlO_dataout : STD_LOGIC; + SIGNAL wire_nl000OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl000OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl000OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl000OO_dataout : STD_LOGIC; + SIGNAL wire_nl000OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl000OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl000OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl000OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl000OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl000OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl000OOi_dataout : STD_LOGIC; + SIGNAL wire_nl000OOii_dataout : STD_LOGIC; + SIGNAL wire_nl000OOil_dataout : STD_LOGIC; + SIGNAL wire_nl000OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl000OOl_dataout : STD_LOGIC; + SIGNAL wire_nl000OOli_dataout : STD_LOGIC; + SIGNAL wire_nl000OOll_dataout : STD_LOGIC; + SIGNAL wire_nl000OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl000OOO_dataout : STD_LOGIC; + SIGNAL wire_nl000OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl000OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl000OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl001000i_dataout : STD_LOGIC; + SIGNAL wire_nl001000O_dataout : STD_LOGIC; + SIGNAL wire_nl001001i_dataout : STD_LOGIC; + SIGNAL wire_nl001001O_dataout : STD_LOGIC; + SIGNAL wire_nl00100ii_dataout : STD_LOGIC; + SIGNAL wire_nl00100iO_dataout : STD_LOGIC; + SIGNAL wire_nl00100l_dataout : STD_LOGIC; + SIGNAL wire_nl00100li_dataout : STD_LOGIC; + SIGNAL wire_nl00100lO_dataout : STD_LOGIC; + SIGNAL wire_nl00100O_dataout : STD_LOGIC; + SIGNAL wire_nl00100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00100OO_dataout : STD_LOGIC; + SIGNAL wire_nl001010i_dataout : STD_LOGIC; + SIGNAL wire_nl001010l_dataout : STD_LOGIC; + SIGNAL wire_nl001010O_dataout : STD_LOGIC; + SIGNAL wire_nl001011i_dataout : STD_LOGIC; + SIGNAL wire_nl001011l_dataout : STD_LOGIC; + SIGNAL wire_nl001011O_dataout : STD_LOGIC; + SIGNAL wire_nl00101ii_dataout : STD_LOGIC; + SIGNAL wire_nl00101il_dataout : STD_LOGIC; + SIGNAL wire_nl00101iO_dataout : STD_LOGIC; + SIGNAL wire_nl00101li_dataout : STD_LOGIC; + SIGNAL wire_nl00101ll_dataout : STD_LOGIC; + SIGNAL wire_nl00101lO_dataout : STD_LOGIC; + SIGNAL wire_nl00101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00101OO_dataout : STD_LOGIC; + SIGNAL wire_nl0010i_dataout : STD_LOGIC; + SIGNAL wire_nl0010i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0010i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0010i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0010i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0010ii_dataout : STD_LOGIC; + SIGNAL wire_nl0010iii_dataout : STD_LOGIC; + SIGNAL wire_nl0010iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0010il_dataout : STD_LOGIC; + SIGNAL wire_nl0010ili_dataout : STD_LOGIC; + SIGNAL wire_nl0010ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0010iO_dataout : STD_LOGIC; + SIGNAL wire_nl0010iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0010iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0010l_dataout : STD_LOGIC; + SIGNAL wire_nl0010l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0010l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0010l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0010l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0010li_dataout : STD_LOGIC; + SIGNAL wire_nl0010lii_dataout : STD_LOGIC; + SIGNAL wire_nl0010liO_dataout : STD_LOGIC; + SIGNAL wire_nl0010ll_dataout : STD_LOGIC; + SIGNAL wire_nl0010lli_dataout : STD_LOGIC; + SIGNAL wire_nl0010llO_dataout : STD_LOGIC; + SIGNAL wire_nl0010lO_dataout : STD_LOGIC; + SIGNAL wire_nl0010lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0010lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0010O_dataout : STD_LOGIC; + SIGNAL wire_nl0010O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0010O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0010O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0010O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0010Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0010Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0010OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0010Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0010Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0010OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0010OO_dataout : STD_LOGIC; + SIGNAL wire_nl0010OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0010OOO_dataout : STD_LOGIC; + SIGNAL wire_nl001100i_dataout : STD_LOGIC; + SIGNAL wire_nl001100l_dataout : STD_LOGIC; + SIGNAL wire_nl001100O_dataout : STD_LOGIC; + SIGNAL wire_nl001101i_dataout : STD_LOGIC; + SIGNAL wire_nl001101l_dataout : STD_LOGIC; + SIGNAL wire_nl001101O_dataout : STD_LOGIC; + SIGNAL wire_nl00110ii_dataout : STD_LOGIC; + SIGNAL wire_nl00110il_dataout : STD_LOGIC; + SIGNAL wire_nl00110iO_dataout : STD_LOGIC; + SIGNAL wire_nl00110li_dataout : STD_LOGIC; + SIGNAL wire_nl00110ll_dataout : STD_LOGIC; + SIGNAL wire_nl00110lO_dataout : STD_LOGIC; + SIGNAL wire_nl00110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00110OO_dataout : STD_LOGIC; + SIGNAL wire_nl001110i_dataout : STD_LOGIC; + SIGNAL wire_nl001110l_dataout : STD_LOGIC; + SIGNAL wire_nl001110O_dataout : STD_LOGIC; + SIGNAL wire_nl001111i_dataout : STD_LOGIC; + SIGNAL wire_nl001111l_dataout : STD_LOGIC; + SIGNAL wire_nl001111O_dataout : STD_LOGIC; + SIGNAL wire_nl00111ii_dataout : STD_LOGIC; + SIGNAL wire_nl00111il_dataout : STD_LOGIC; + SIGNAL wire_nl00111iO_dataout : STD_LOGIC; + SIGNAL wire_nl00111li_dataout : STD_LOGIC; + SIGNAL wire_nl00111ll_dataout : STD_LOGIC; + SIGNAL wire_nl00111lO_dataout : STD_LOGIC; + SIGNAL wire_nl00111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00111OO_dataout : STD_LOGIC; + SIGNAL wire_nl0011i_dataout : STD_LOGIC; + SIGNAL wire_nl0011i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0011i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0011i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0011i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0011i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0011i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0011iii_dataout : STD_LOGIC; + SIGNAL wire_nl0011iil_dataout : STD_LOGIC; + SIGNAL wire_nl0011iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0011ili_dataout : STD_LOGIC; + SIGNAL wire_nl0011ill_dataout : STD_LOGIC; + SIGNAL wire_nl0011ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0011iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0011iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0011iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0011l_dataout : STD_LOGIC; + SIGNAL wire_nl0011l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0011l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0011l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0011l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0011l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0011l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0011lii_dataout : STD_LOGIC; + SIGNAL wire_nl0011lil_dataout : STD_LOGIC; + SIGNAL wire_nl0011liO_dataout : STD_LOGIC; + SIGNAL wire_nl0011lli_dataout : STD_LOGIC; + SIGNAL wire_nl0011lll_dataout : STD_LOGIC; + SIGNAL wire_nl0011llO_dataout : STD_LOGIC; + SIGNAL wire_nl0011lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0011lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0011lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0011O_dataout : STD_LOGIC; + SIGNAL wire_nl0011O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0011O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0011O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0011O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0011O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0011O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0011Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0011Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0011OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0011Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0011Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0011OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0011OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0011OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0011OOO_dataout : STD_LOGIC; + SIGNAL wire_nl001i00i_dataout : STD_LOGIC; + SIGNAL wire_nl001i00O_dataout : STD_LOGIC; + SIGNAL wire_nl001i01i_dataout : STD_LOGIC; + SIGNAL wire_nl001i01O_dataout : STD_LOGIC; + SIGNAL wire_nl001i0i_dataout : STD_LOGIC; + SIGNAL wire_nl001i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl001i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl001i0l_dataout : STD_LOGIC; + SIGNAL wire_nl001i0li_dataout : STD_LOGIC; + SIGNAL wire_nl001i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl001i0O_dataout : STD_LOGIC; + SIGNAL wire_nl001i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl001i10i_dataout : STD_LOGIC; + SIGNAL wire_nl001i10O_dataout : STD_LOGIC; + SIGNAL wire_nl001i11i_dataout : STD_LOGIC; + SIGNAL wire_nl001i11O_dataout : STD_LOGIC; + SIGNAL wire_nl001i1i_dataout : STD_LOGIC; + SIGNAL wire_nl001i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl001i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl001i1l_dataout : STD_LOGIC; + SIGNAL wire_nl001i1li_dataout : STD_LOGIC; + SIGNAL wire_nl001i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl001i1O_dataout : STD_LOGIC; + SIGNAL wire_nl001i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl001ii_dataout : STD_LOGIC; + SIGNAL wire_nl001ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl001ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl001ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl001ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl001iii_dataout : STD_LOGIC; + SIGNAL wire_nl001iiii_dataout : STD_LOGIC; + SIGNAL wire_nl001iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl001iil_dataout : STD_LOGIC; + SIGNAL wire_nl001iili_dataout : STD_LOGIC; + SIGNAL wire_nl001iilO_dataout : STD_LOGIC; + SIGNAL wire_nl001iiO_dataout : STD_LOGIC; + SIGNAL wire_nl001iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl001iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl001il_dataout : STD_LOGIC; + SIGNAL wire_nl001il0i_dataout : STD_LOGIC; + SIGNAL wire_nl001il0O_dataout : STD_LOGIC; + SIGNAL wire_nl001il1i_dataout : STD_LOGIC; + SIGNAL wire_nl001il1O_dataout : STD_LOGIC; + SIGNAL wire_nl001ili_dataout : STD_LOGIC; + SIGNAL wire_nl001ilii_dataout : STD_LOGIC; + SIGNAL wire_nl001iliO_dataout : STD_LOGIC; + SIGNAL wire_nl001ill_dataout : STD_LOGIC; + SIGNAL wire_nl001illi_dataout : STD_LOGIC; + SIGNAL wire_nl001illO_dataout : STD_LOGIC; + SIGNAL wire_nl001ilO_dataout : STD_LOGIC; + SIGNAL wire_nl001ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl001ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl001iO_dataout : STD_LOGIC; + SIGNAL wire_nl001iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl001iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl001iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl001iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl001iOi_dataout : STD_LOGIC; + SIGNAL wire_nl001iOii_dataout : STD_LOGIC; + SIGNAL wire_nl001iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl001iOl_dataout : STD_LOGIC; + SIGNAL wire_nl001iOli_dataout : STD_LOGIC; + SIGNAL wire_nl001iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl001iOO_dataout : STD_LOGIC; + SIGNAL wire_nl001iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl001iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl001l00i_dataout : STD_LOGIC; + SIGNAL wire_nl001l00O_dataout : STD_LOGIC; + SIGNAL wire_nl001l01i_dataout : STD_LOGIC; + SIGNAL wire_nl001l01O_dataout : STD_LOGIC; + SIGNAL wire_nl001l0i_dataout : STD_LOGIC; + SIGNAL wire_nl001l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl001l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl001l0l_dataout : STD_LOGIC; + SIGNAL wire_nl001l0li_dataout : STD_LOGIC; + SIGNAL wire_nl001l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl001l0O_dataout : STD_LOGIC; + SIGNAL wire_nl001l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl001l10i_dataout : STD_LOGIC; + SIGNAL wire_nl001l10O_dataout : STD_LOGIC; + SIGNAL wire_nl001l11i_dataout : STD_LOGIC; + SIGNAL wire_nl001l11O_dataout : STD_LOGIC; + SIGNAL wire_nl001l1i_dataout : STD_LOGIC; + SIGNAL wire_nl001l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl001l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl001l1l_dataout : STD_LOGIC; + SIGNAL wire_nl001l1li_dataout : STD_LOGIC; + SIGNAL wire_nl001l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl001l1O_dataout : STD_LOGIC; + SIGNAL wire_nl001l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl001li_dataout : STD_LOGIC; + SIGNAL wire_nl001li0i_dataout : STD_LOGIC; + SIGNAL wire_nl001li0O_dataout : STD_LOGIC; + SIGNAL wire_nl001li1i_dataout : STD_LOGIC; + SIGNAL wire_nl001li1O_dataout : STD_LOGIC; + SIGNAL wire_nl001lii_dataout : STD_LOGIC; + SIGNAL wire_nl001liii_dataout : STD_LOGIC; + SIGNAL wire_nl001liiO_dataout : STD_LOGIC; + SIGNAL wire_nl001lil_dataout : STD_LOGIC; + SIGNAL wire_nl001lili_dataout : STD_LOGIC; + SIGNAL wire_nl001lilO_dataout : STD_LOGIC; + SIGNAL wire_nl001liO_dataout : STD_LOGIC; + SIGNAL wire_nl001liOi_dataout : STD_LOGIC; + SIGNAL wire_nl001liOO_dataout : STD_LOGIC; + SIGNAL wire_nl001ll_dataout : STD_LOGIC; + SIGNAL wire_nl001ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl001ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl001ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl001ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl001lli_dataout : STD_LOGIC; + SIGNAL wire_nl001llii_dataout : STD_LOGIC; + SIGNAL wire_nl001lll_dataout : STD_LOGIC; + SIGNAL wire_nl001llO_dataout : STD_LOGIC; + SIGNAL wire_nl001lO_dataout : STD_LOGIC; + SIGNAL wire_nl001lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl001lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl001lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl001lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl001lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl001lOi_dataout : STD_LOGIC; + SIGNAL wire_nl001lOii_dataout : STD_LOGIC; + SIGNAL wire_nl001lOil_dataout : STD_LOGIC; + SIGNAL wire_nl001lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl001lOli_dataout : STD_LOGIC; + SIGNAL wire_nl001lOll_dataout : STD_LOGIC; + SIGNAL wire_nl001lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl001lOO_dataout : STD_LOGIC; + SIGNAL wire_nl001lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl001lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl001lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl001O00i_dataout : STD_LOGIC; + SIGNAL wire_nl001O00l_dataout : STD_LOGIC; + SIGNAL wire_nl001O00O_dataout : STD_LOGIC; + SIGNAL wire_nl001O01i_dataout : STD_LOGIC; + SIGNAL wire_nl001O01l_dataout : STD_LOGIC; + SIGNAL wire_nl001O01O_dataout : STD_LOGIC; + SIGNAL wire_nl001O0i_dataout : STD_LOGIC; + SIGNAL wire_nl001O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl001O0il_dataout : STD_LOGIC; + SIGNAL wire_nl001O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl001O0l_dataout : STD_LOGIC; + SIGNAL wire_nl001O0li_dataout : STD_LOGIC; + SIGNAL wire_nl001O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl001O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl001O0O_dataout : STD_LOGIC; + SIGNAL wire_nl001O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl001O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl001O10i_dataout : STD_LOGIC; + SIGNAL wire_nl001O10l_dataout : STD_LOGIC; + SIGNAL wire_nl001O10O_dataout : STD_LOGIC; + SIGNAL wire_nl001O11i_dataout : STD_LOGIC; + SIGNAL wire_nl001O11l_dataout : STD_LOGIC; + SIGNAL wire_nl001O11O_dataout : STD_LOGIC; + SIGNAL wire_nl001O1i_dataout : STD_LOGIC; + SIGNAL wire_nl001O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl001O1il_dataout : STD_LOGIC; + SIGNAL wire_nl001O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl001O1l_dataout : STD_LOGIC; + SIGNAL wire_nl001O1li_dataout : STD_LOGIC; + SIGNAL wire_nl001O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl001O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl001O1O_dataout : STD_LOGIC; + SIGNAL wire_nl001O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl001O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl001Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl001Oii_dataout : STD_LOGIC; + SIGNAL wire_nl001Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl001Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl001OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl001Oil_dataout : STD_LOGIC; + SIGNAL wire_nl001Oili_dataout : STD_LOGIC; + SIGNAL wire_nl001Oill_dataout : STD_LOGIC; + SIGNAL wire_nl001OilO_dataout : STD_LOGIC; + SIGNAL wire_nl001OiO_dataout : STD_LOGIC; + SIGNAL wire_nl001OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl001OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl001OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl001Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl001Oli_dataout : STD_LOGIC; + SIGNAL wire_nl001Olii_dataout : STD_LOGIC; + SIGNAL wire_nl001Olil_dataout : STD_LOGIC; + SIGNAL wire_nl001OliO_dataout : STD_LOGIC; + SIGNAL wire_nl001Oll_dataout : STD_LOGIC; + SIGNAL wire_nl001Olli_dataout : STD_LOGIC; + SIGNAL wire_nl001Olll_dataout : STD_LOGIC; + SIGNAL wire_nl001OllO_dataout : STD_LOGIC; + SIGNAL wire_nl001OlO_dataout : STD_LOGIC; + SIGNAL wire_nl001OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl001OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl001OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl001OO_dataout : STD_LOGIC; + SIGNAL wire_nl001OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl001OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl001OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl001OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl001OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl001OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl001OOi_dataout : STD_LOGIC; + SIGNAL wire_nl001OOii_dataout : STD_LOGIC; + SIGNAL wire_nl001OOil_dataout : STD_LOGIC; + SIGNAL wire_nl001OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl001OOl_dataout : STD_LOGIC; + SIGNAL wire_nl001OOli_dataout : STD_LOGIC; + SIGNAL wire_nl001OOll_dataout : STD_LOGIC; + SIGNAL wire_nl001OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl001OOO_dataout : STD_LOGIC; + SIGNAL wire_nl001OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl001OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl001OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00i000i_dataout : STD_LOGIC; + SIGNAL wire_nl00i000l_dataout : STD_LOGIC; + SIGNAL wire_nl00i001i_dataout : STD_LOGIC; + SIGNAL wire_nl00i001l_dataout : STD_LOGIC; + SIGNAL wire_nl00i00i_dataout : STD_LOGIC; + SIGNAL wire_nl00i00ii_dataout : STD_LOGIC; + SIGNAL wire_nl00i00il_dataout : STD_LOGIC; + SIGNAL wire_nl00i00l_dataout : STD_LOGIC; + SIGNAL wire_nl00i00li_dataout : STD_LOGIC; + SIGNAL wire_nl00i00ll_dataout : STD_LOGIC; + SIGNAL wire_nl00i00O_dataout : STD_LOGIC; + SIGNAL wire_nl00i00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00i00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00i010i_dataout : STD_LOGIC; + SIGNAL wire_nl00i010l_dataout : STD_LOGIC; + SIGNAL wire_nl00i011i_dataout : STD_LOGIC; + SIGNAL wire_nl00i011l_dataout : STD_LOGIC; + SIGNAL wire_nl00i01i_dataout : STD_LOGIC; + SIGNAL wire_nl00i01ii_dataout : STD_LOGIC; + SIGNAL wire_nl00i01il_dataout : STD_LOGIC; + SIGNAL wire_nl00i01l_dataout : STD_LOGIC; + SIGNAL wire_nl00i01li_dataout : STD_LOGIC; + SIGNAL wire_nl00i01ll_dataout : STD_LOGIC; + SIGNAL wire_nl00i01O_dataout : STD_LOGIC; + SIGNAL wire_nl00i01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00i01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00i0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00i0iii_dataout : STD_LOGIC; + SIGNAL wire_nl00i0iil_dataout : STD_LOGIC; + SIGNAL wire_nl00i0il_dataout : STD_LOGIC; + SIGNAL wire_nl00i0ili_dataout : STD_LOGIC; + SIGNAL wire_nl00i0ill_dataout : STD_LOGIC; + SIGNAL wire_nl00i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00i0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl00i0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl00i0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0li_dataout : STD_LOGIC; + SIGNAL wire_nl00i0lii_dataout : STD_LOGIC; + SIGNAL wire_nl00i0lil_dataout : STD_LOGIC; + SIGNAL wire_nl00i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00i0lli_dataout : STD_LOGIC; + SIGNAL wire_nl00i0lll_dataout : STD_LOGIC; + SIGNAL wire_nl00i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00i0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl00i0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl00i0O_dataout : STD_LOGIC; + SIGNAL wire_nl00i0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00i0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl00i0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl00i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00i0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl00i0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl00i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00i0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl00i0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl00i100i_dataout : STD_LOGIC; + SIGNAL wire_nl00i100l_dataout : STD_LOGIC; + SIGNAL wire_nl00i100O_dataout : STD_LOGIC; + SIGNAL wire_nl00i101i_dataout : STD_LOGIC; + SIGNAL wire_nl00i101l_dataout : STD_LOGIC; + SIGNAL wire_nl00i101O_dataout : STD_LOGIC; + SIGNAL wire_nl00i10i_dataout : STD_LOGIC; + SIGNAL wire_nl00i10ii_dataout : STD_LOGIC; + SIGNAL wire_nl00i10il_dataout : STD_LOGIC; + SIGNAL wire_nl00i10iO_dataout : STD_LOGIC; + SIGNAL wire_nl00i10l_dataout : STD_LOGIC; + SIGNAL wire_nl00i10li_dataout : STD_LOGIC; + SIGNAL wire_nl00i10ll_dataout : STD_LOGIC; + SIGNAL wire_nl00i10lO_dataout : STD_LOGIC; + SIGNAL wire_nl00i10O_dataout : STD_LOGIC; + SIGNAL wire_nl00i10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00i10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00i10OO_dataout : STD_LOGIC; + SIGNAL wire_nl00i110i_dataout : STD_LOGIC; + SIGNAL wire_nl00i110l_dataout : STD_LOGIC; + SIGNAL wire_nl00i110O_dataout : STD_LOGIC; + SIGNAL wire_nl00i111i_dataout : STD_LOGIC; + SIGNAL wire_nl00i111l_dataout : STD_LOGIC; + SIGNAL wire_nl00i111O_dataout : STD_LOGIC; + SIGNAL wire_nl00i11i_dataout : STD_LOGIC; + SIGNAL wire_nl00i11ii_dataout : STD_LOGIC; + SIGNAL wire_nl00i11il_dataout : STD_LOGIC; + SIGNAL wire_nl00i11iO_dataout : STD_LOGIC; + SIGNAL wire_nl00i11l_dataout : STD_LOGIC; + SIGNAL wire_nl00i11li_dataout : STD_LOGIC; + SIGNAL wire_nl00i11ll_dataout : STD_LOGIC; + SIGNAL wire_nl00i11lO_dataout : STD_LOGIC; + SIGNAL wire_nl00i11O_dataout : STD_LOGIC; + SIGNAL wire_nl00i11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00i11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00i11OO_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl00i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00i1iii_dataout : STD_LOGIC; + SIGNAL wire_nl00i1iil_dataout : STD_LOGIC; + SIGNAL wire_nl00i1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl00i1il_dataout : STD_LOGIC; + SIGNAL wire_nl00i1ili_dataout : STD_LOGIC; + SIGNAL wire_nl00i1ill_dataout : STD_LOGIC; + SIGNAL wire_nl00i1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl00i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl00i1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl00i1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl00i1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl00i1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl00i1li_dataout : STD_LOGIC; + SIGNAL wire_nl00i1lii_dataout : STD_LOGIC; + SIGNAL wire_nl00i1lil_dataout : STD_LOGIC; + SIGNAL wire_nl00i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00i1lli_dataout : STD_LOGIC; + SIGNAL wire_nl00i1lll_dataout : STD_LOGIC; + SIGNAL wire_nl00i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl00i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl00i1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl00i1O_dataout : STD_LOGIC; + SIGNAL wire_nl00i1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl00i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl00i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00i1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl00i1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl00i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00i1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl00i1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl00i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl00i1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl00i1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl00ii00i_dataout : STD_LOGIC; + SIGNAL wire_nl00ii00l_dataout : STD_LOGIC; + SIGNAL wire_nl00ii01i_dataout : STD_LOGIC; + SIGNAL wire_nl00ii01l_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0il_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0li_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00ii10i_dataout : STD_LOGIC; + SIGNAL wire_nl00ii10l_dataout : STD_LOGIC; + SIGNAL wire_nl00ii11i_dataout : STD_LOGIC; + SIGNAL wire_nl00ii11l_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1il_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1li_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00iii_dataout : STD_LOGIC; + SIGNAL wire_nl00iii0i_dataout : STD_LOGIC; + SIGNAL wire_nl00iii0l_dataout : STD_LOGIC; + SIGNAL wire_nl00iii1i_dataout : STD_LOGIC; + SIGNAL wire_nl00iii1l_dataout : STD_LOGIC; + SIGNAL wire_nl00iiii_dataout : STD_LOGIC; + SIGNAL wire_nl00iiiii_dataout : STD_LOGIC; + SIGNAL wire_nl00iiiil_dataout : STD_LOGIC; + SIGNAL wire_nl00iiil_dataout : STD_LOGIC; + SIGNAL wire_nl00iiili_dataout : STD_LOGIC; + SIGNAL wire_nl00iiill_dataout : STD_LOGIC; + SIGNAL wire_nl00iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl00iiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl00iil_dataout : STD_LOGIC; + SIGNAL wire_nl00iil0i_dataout : STD_LOGIC; + SIGNAL wire_nl00iil0l_dataout : STD_LOGIC; + SIGNAL wire_nl00iil1i_dataout : STD_LOGIC; + SIGNAL wire_nl00iil1l_dataout : STD_LOGIC; + SIGNAL wire_nl00iili_dataout : STD_LOGIC; + SIGNAL wire_nl00iilii_dataout : STD_LOGIC; + SIGNAL wire_nl00iilil_dataout : STD_LOGIC; + SIGNAL wire_nl00iill_dataout : STD_LOGIC; + SIGNAL wire_nl00iilli_dataout : STD_LOGIC; + SIGNAL wire_nl00iilll_dataout : STD_LOGIC; + SIGNAL wire_nl00iilO_dataout : STD_LOGIC; + SIGNAL wire_nl00iilOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iilOl_dataout : STD_LOGIC; + SIGNAL wire_nl00iiO_dataout : STD_LOGIC; + SIGNAL wire_nl00iiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00iiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00iiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00iiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOii_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOil_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOli_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOll_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00il00i_dataout : STD_LOGIC; + SIGNAL wire_nl00il00l_dataout : STD_LOGIC; + SIGNAL wire_nl00il00O_dataout : STD_LOGIC; + SIGNAL wire_nl00il0i_dataout : STD_LOGIC; + SIGNAL wire_nl00il0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00il0il_dataout : STD_LOGIC; + SIGNAL wire_nl00il0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00il0l_dataout : STD_LOGIC; + SIGNAL wire_nl00il0li_dataout : STD_LOGIC; + SIGNAL wire_nl00il0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00il0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00il0O_dataout : STD_LOGIC; + SIGNAL wire_nl00il0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00il0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00il0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00il10i_dataout : STD_LOGIC; + SIGNAL wire_nl00il10l_dataout : STD_LOGIC; + SIGNAL wire_nl00il11i_dataout : STD_LOGIC; + SIGNAL wire_nl00il11l_dataout : STD_LOGIC; + SIGNAL wire_nl00il1i_dataout : STD_LOGIC; + SIGNAL wire_nl00il1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00il1il_dataout : STD_LOGIC; + SIGNAL wire_nl00il1l_dataout : STD_LOGIC; + SIGNAL wire_nl00il1li_dataout : STD_LOGIC; + SIGNAL wire_nl00il1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00il1O_dataout : STD_LOGIC; + SIGNAL wire_nl00il1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00ili_dataout : STD_LOGIC; + SIGNAL wire_nl00ili0i_dataout : STD_LOGIC; + SIGNAL wire_nl00ili0l_dataout : STD_LOGIC; + SIGNAL wire_nl00ili0O_dataout : STD_LOGIC; + SIGNAL wire_nl00ili1i_dataout : STD_LOGIC; + SIGNAL wire_nl00ili1l_dataout : STD_LOGIC; + SIGNAL wire_nl00ili1O_dataout : STD_LOGIC; + SIGNAL wire_nl00ilii_dataout : STD_LOGIC; + SIGNAL wire_nl00iliii_dataout : STD_LOGIC; + SIGNAL wire_nl00iliil_dataout : STD_LOGIC; + SIGNAL wire_nl00iliiO_dataout : STD_LOGIC; + SIGNAL wire_nl00ilil_dataout : STD_LOGIC; + SIGNAL wire_nl00ilili_dataout : STD_LOGIC; + SIGNAL wire_nl00ilill_dataout : STD_LOGIC; + SIGNAL wire_nl00ililO_dataout : STD_LOGIC; + SIGNAL wire_nl00iliO_dataout : STD_LOGIC; + SIGNAL wire_nl00iliOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iliOl_dataout : STD_LOGIC; + SIGNAL wire_nl00iliOO_dataout : STD_LOGIC; + SIGNAL wire_nl00ill_dataout : STD_LOGIC; + SIGNAL wire_nl00ill0i_dataout : STD_LOGIC; + SIGNAL wire_nl00ill0l_dataout : STD_LOGIC; + SIGNAL wire_nl00ill0O_dataout : STD_LOGIC; + SIGNAL wire_nl00ill1i_dataout : STD_LOGIC; + SIGNAL wire_nl00ill1l_dataout : STD_LOGIC; + SIGNAL wire_nl00ill1O_dataout : STD_LOGIC; + SIGNAL wire_nl00illi_dataout : STD_LOGIC; + SIGNAL wire_nl00illii_dataout : STD_LOGIC; + SIGNAL wire_nl00illil_dataout : STD_LOGIC; + SIGNAL wire_nl00illiO_dataout : STD_LOGIC; + SIGNAL wire_nl00illl_dataout : STD_LOGIC; + SIGNAL wire_nl00illli_dataout : STD_LOGIC; + SIGNAL wire_nl00illll_dataout : STD_LOGIC; + SIGNAL wire_nl00illlO_dataout : STD_LOGIC; + SIGNAL wire_nl00illO_dataout : STD_LOGIC; + SIGNAL wire_nl00illOi_dataout : STD_LOGIC; + SIGNAL wire_nl00illOl_dataout : STD_LOGIC; + SIGNAL wire_nl00illOO_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00ilO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOii_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOil_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOli_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOll_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOlO_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00iO00i_dataout : STD_LOGIC; + SIGNAL wire_nl00iO00l_dataout : STD_LOGIC; + SIGNAL wire_nl00iO00O_dataout : STD_LOGIC; + SIGNAL wire_nl00iO01i_dataout : STD_LOGIC; + SIGNAL wire_nl00iO01l_dataout : STD_LOGIC; + SIGNAL wire_nl00iO01O_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0il_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0li_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00iO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00iO10i_dataout : STD_LOGIC; + SIGNAL wire_nl00iO10l_dataout : STD_LOGIC; + SIGNAL wire_nl00iO10O_dataout : STD_LOGIC; + SIGNAL wire_nl00iO11i_dataout : STD_LOGIC; + SIGNAL wire_nl00iO11l_dataout : STD_LOGIC; + SIGNAL wire_nl00iO11O_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1il_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1li_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00iO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl00iOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl00iOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl00iOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl00iOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl00iOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl00iOii_dataout : STD_LOGIC; + SIGNAL wire_nl00iOiii_dataout : STD_LOGIC; + SIGNAL wire_nl00iOiil_dataout : STD_LOGIC; + SIGNAL wire_nl00iOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOili_dataout : STD_LOGIC; + SIGNAL wire_nl00iOill_dataout : STD_LOGIC; + SIGNAL wire_nl00iOilO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl00iOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl00iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl00iOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl00iOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl00iOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl00iOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl00iOlii_dataout : STD_LOGIC; + SIGNAL wire_nl00iOlil_dataout : STD_LOGIC; + SIGNAL wire_nl00iOliO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOlli_dataout : STD_LOGIC; + SIGNAL wire_nl00iOlll_dataout : STD_LOGIC; + SIGNAL wire_nl00iOllO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl00iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl00iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00iOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00iOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00iOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00iOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00iOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00iOOii_dataout : STD_LOGIC; + SIGNAL wire_nl00iOOil_dataout : STD_LOGIC; + SIGNAL wire_nl00iOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00iOOli_dataout : STD_LOGIC; + SIGNAL wire_nl00iOOll_dataout : STD_LOGIC; + SIGNAL wire_nl00l0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl00l111i_dataout : STD_LOGIC; + SIGNAL wire_nl00l111i_w_lg_dataout53192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00l111l_dataout : STD_LOGIC; + SIGNAL wire_nl00l111l_w_lg_w_lg_dataout53191w53193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00l111l_w_lg_dataout53191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00l11li_dataout : STD_LOGIC; + SIGNAL wire_nl00l11ll_dataout : STD_LOGIC; + SIGNAL wire_nl00l11lO_dataout : STD_LOGIC; + SIGNAL wire_nl00l11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00l11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00l11OO_dataout : STD_LOGIC; + SIGNAL wire_nl00llliO_dataout : STD_LOGIC; + SIGNAL wire_nl00lllli_dataout : STD_LOGIC; + SIGNAL wire_nl00lllll_dataout : STD_LOGIC; + SIGNAL wire_nl00llllO_dataout : STD_LOGIC; + SIGNAL wire_nl00lllOi_dataout : STD_LOGIC; + SIGNAL wire_nl00lllOl_dataout : STD_LOGIC; + SIGNAL wire_nl00lllOO_dataout : STD_LOGIC; + SIGNAL wire_nl00llO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00llO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00llO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00llO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00llO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00llO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00llOii_dataout : STD_LOGIC; + SIGNAL wire_nl00llOil_dataout : STD_LOGIC; + SIGNAL wire_nl00llOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00llOli_dataout : STD_LOGIC; + SIGNAL wire_nl00llOll_dataout : STD_LOGIC; + SIGNAL wire_nl00llOlO_dataout : STD_LOGIC; + SIGNAL wire_nl00llOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00llOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00llOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00lO00i_dataout : STD_LOGIC; + SIGNAL wire_nl00lO00l_dataout : STD_LOGIC; + SIGNAL wire_nl00lO00O_dataout : STD_LOGIC; + SIGNAL wire_nl00lO01i_dataout : STD_LOGIC; + SIGNAL wire_nl00lO01l_dataout : STD_LOGIC; + SIGNAL wire_nl00lO01O_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0il_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0li_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00lO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00lO10i_dataout : STD_LOGIC; + SIGNAL wire_nl00lO10l_dataout : STD_LOGIC; + SIGNAL wire_nl00lO10O_dataout : STD_LOGIC; + SIGNAL wire_nl00lO11i_dataout : STD_LOGIC; + SIGNAL wire_nl00lO11l_dataout : STD_LOGIC; + SIGNAL wire_nl00lO11O_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1il_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1li_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00lO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl00lOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl00lOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl00lOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl00lOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl00lOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl00lOii_dataout : STD_LOGIC; + SIGNAL wire_nl00lOiii_dataout : STD_LOGIC; + SIGNAL wire_nl00lOiil_dataout : STD_LOGIC; + SIGNAL wire_nl00lOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOil_dataout : STD_LOGIC; + SIGNAL wire_nl00lOili_dataout : STD_LOGIC; + SIGNAL wire_nl00lOill_dataout : STD_LOGIC; + SIGNAL wire_nl00lOilO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl00lOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl00lOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl00lOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl00lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl00lOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl00lOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl00lOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl00lOli_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlii_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlil_dataout : STD_LOGIC; + SIGNAL wire_nl00lOliO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOll_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlli_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlll_dataout : STD_LOGIC; + SIGNAL wire_nl00lOllO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl00lOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00lOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00lOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00lOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00lOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00lOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOii_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOil_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOli_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOll_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00lOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00O000i_dataout : STD_LOGIC; + SIGNAL wire_nl00O000l_dataout : STD_LOGIC; + SIGNAL wire_nl00O000O_dataout : STD_LOGIC; + SIGNAL wire_nl00O001i_dataout : STD_LOGIC; + SIGNAL wire_nl00O001l_dataout : STD_LOGIC; + SIGNAL wire_nl00O001O_dataout : STD_LOGIC; + SIGNAL wire_nl00O00i_dataout : STD_LOGIC; + SIGNAL wire_nl00O00ii_dataout : STD_LOGIC; + SIGNAL wire_nl00O00il_dataout : STD_LOGIC; + SIGNAL wire_nl00O00iO_dataout : STD_LOGIC; + SIGNAL wire_nl00O00l_dataout : STD_LOGIC; + SIGNAL wire_nl00O00li_dataout : STD_LOGIC; + SIGNAL wire_nl00O00ll_dataout : STD_LOGIC; + SIGNAL wire_nl00O00lO_dataout : STD_LOGIC; + SIGNAL wire_nl00O00O_dataout : STD_LOGIC; + SIGNAL wire_nl00O00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00O00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00O00OO_dataout : STD_LOGIC; + SIGNAL wire_nl00O010i_dataout : STD_LOGIC; + SIGNAL wire_nl00O010l_dataout : STD_LOGIC; + SIGNAL wire_nl00O010O_dataout : STD_LOGIC; + SIGNAL wire_nl00O011i_dataout : STD_LOGIC; + SIGNAL wire_nl00O011l_dataout : STD_LOGIC; + SIGNAL wire_nl00O011O_dataout : STD_LOGIC; + SIGNAL wire_nl00O01i_dataout : STD_LOGIC; + SIGNAL wire_nl00O01ii_dataout : STD_LOGIC; + SIGNAL wire_nl00O01il_dataout : STD_LOGIC; + SIGNAL wire_nl00O01iO_dataout : STD_LOGIC; + SIGNAL wire_nl00O01l_dataout : STD_LOGIC; + SIGNAL wire_nl00O01li_dataout : STD_LOGIC; + SIGNAL wire_nl00O01ll_dataout : STD_LOGIC; + SIGNAL wire_nl00O01lO_dataout : STD_LOGIC; + SIGNAL wire_nl00O01O_dataout : STD_LOGIC; + SIGNAL wire_nl00O01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00O01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00O01OO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl00O0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl00O0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl00O0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl00O0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl00O0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl00O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00O0iii_dataout : STD_LOGIC; + SIGNAL wire_nl00O0iil_dataout : STD_LOGIC; + SIGNAL wire_nl00O0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0il_dataout : STD_LOGIC; + SIGNAL wire_nl00O0ili_dataout : STD_LOGIC; + SIGNAL wire_nl00O0ill_dataout : STD_LOGIC; + SIGNAL wire_nl00O0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl00O0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl00O0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl00O0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl00O0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl00O0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl00O0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl00O0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl00O0li_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lii_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lil_dataout : STD_LOGIC; + SIGNAL wire_nl00O0liO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lli_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lll_dataout : STD_LOGIC; + SIGNAL wire_nl00O0llO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl00O0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl00O0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl00O0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl00O0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl00O0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl00O0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl00O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00O0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl00O0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl00O0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00O0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl00O0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl00O0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00O0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl00O0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl00O0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl00O100i_dataout : STD_LOGIC; + SIGNAL wire_nl00O100l_dataout : STD_LOGIC; + SIGNAL wire_nl00O100O_dataout : STD_LOGIC; + SIGNAL wire_nl00O101i_dataout : STD_LOGIC; + SIGNAL wire_nl00O101l_dataout : STD_LOGIC; + SIGNAL wire_nl00O101O_dataout : STD_LOGIC; + SIGNAL wire_nl00O10i_dataout : STD_LOGIC; + SIGNAL wire_nl00O10ii_dataout : STD_LOGIC; + SIGNAL wire_nl00O10il_dataout : STD_LOGIC; + SIGNAL wire_nl00O10iO_dataout : STD_LOGIC; + SIGNAL wire_nl00O10l_dataout : STD_LOGIC; + SIGNAL wire_nl00O10li_dataout : STD_LOGIC; + SIGNAL wire_nl00O10ll_dataout : STD_LOGIC; + SIGNAL wire_nl00O10lO_dataout : STD_LOGIC; + SIGNAL wire_nl00O10O_dataout : STD_LOGIC; + SIGNAL wire_nl00O10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00O10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00O10OO_dataout : STD_LOGIC; + SIGNAL wire_nl00O110i_dataout : STD_LOGIC; + SIGNAL wire_nl00O110l_dataout : STD_LOGIC; + SIGNAL wire_nl00O110O_dataout : STD_LOGIC; + SIGNAL wire_nl00O111i_dataout : STD_LOGIC; + SIGNAL wire_nl00O111l_dataout : STD_LOGIC; + SIGNAL wire_nl00O111O_dataout : STD_LOGIC; + SIGNAL wire_nl00O11i_dataout : STD_LOGIC; + SIGNAL wire_nl00O11ii_dataout : STD_LOGIC; + SIGNAL wire_nl00O11il_dataout : STD_LOGIC; + SIGNAL wire_nl00O11iO_dataout : STD_LOGIC; + SIGNAL wire_nl00O11l_dataout : STD_LOGIC; + SIGNAL wire_nl00O11li_dataout : STD_LOGIC; + SIGNAL wire_nl00O11ll_dataout : STD_LOGIC; + SIGNAL wire_nl00O11lO_dataout : STD_LOGIC; + SIGNAL wire_nl00O11O_dataout : STD_LOGIC; + SIGNAL wire_nl00O11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00O11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00O11OO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl00O1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl00O1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl00O1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl00O1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl00O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl00O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00O1iii_dataout : STD_LOGIC; + SIGNAL wire_nl00O1iil_dataout : STD_LOGIC; + SIGNAL wire_nl00O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1il_dataout : STD_LOGIC; + SIGNAL wire_nl00O1ili_dataout : STD_LOGIC; + SIGNAL wire_nl00O1ill_dataout : STD_LOGIC; + SIGNAL wire_nl00O1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl00O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl00O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl00O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl00O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl00O1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl00O1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl00O1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl00O1li_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lii_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lil_dataout : STD_LOGIC; + SIGNAL wire_nl00O1liO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lli_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lll_dataout : STD_LOGIC; + SIGNAL wire_nl00O1llO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl00O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl00O1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl00O1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl00O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl00O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl00O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl00O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl00O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl00O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl00O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl00O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl00O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl00O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl00O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi00i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi00l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi00O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi01i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi01l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi01O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0il_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0li_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi10i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi10l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi10O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi11i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi11l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi11O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1il_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1li_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oii0i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oii0l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oii1i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oii1l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oii1O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl00Oiiii_dataout : STD_LOGIC; + SIGNAL wire_nl00Oiiil_dataout : STD_LOGIC; + SIGNAL wire_nl00OiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl00Oiili_dataout : STD_LOGIC; + SIGNAL wire_nl00Oiill_dataout : STD_LOGIC; + SIGNAL wire_nl00OiilO_dataout : STD_LOGIC; + SIGNAL wire_nl00OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl00OiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oil0i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oil0l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oil0O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oil1i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oil1l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oil1O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oili_dataout : STD_LOGIC; + SIGNAL wire_nl00Oilii_dataout : STD_LOGIC; + SIGNAL wire_nl00Oilil_dataout : STD_LOGIC; + SIGNAL wire_nl00OiliO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oill_dataout : STD_LOGIC; + SIGNAL wire_nl00Oilli_dataout : STD_LOGIC; + SIGNAL wire_nl00Oilll_dataout : STD_LOGIC; + SIGNAL wire_nl00OillO_dataout : STD_LOGIC; + SIGNAL wire_nl00OilO_dataout : STD_LOGIC; + SIGNAL wire_nl00OilOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OilOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OilOO_dataout : STD_LOGIC; + SIGNAL wire_nl00OiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00OiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00OiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00OiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00OiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00OiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOii_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOil_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOli_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOll_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol00l_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol00O_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0il_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0li_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol10l_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol10O_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol11i_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1li_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oli0i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oli0O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oli1i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oli1l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oli1O_dataout : STD_LOGIC; + SIGNAL wire_nl00Olii_dataout : STD_LOGIC; + SIGNAL wire_nl00Oliii_dataout : STD_LOGIC; + SIGNAL wire_nl00Oliil_dataout : STD_LOGIC; + SIGNAL wire_nl00OliiO_dataout : STD_LOGIC; + SIGNAL wire_nl00Olili_dataout : STD_LOGIC; + SIGNAL wire_nl00Olill_dataout : STD_LOGIC; + SIGNAL wire_nl00OlilO_dataout : STD_LOGIC; + SIGNAL wire_nl00OliO_dataout : STD_LOGIC; + SIGNAL wire_nl00OliOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OliOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OliOO_dataout : STD_LOGIC; + SIGNAL wire_nl00Oll0i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oll0l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oll0O_dataout : STD_LOGIC; + SIGNAL wire_nl00Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nl00Oll1l_dataout : STD_LOGIC; + SIGNAL wire_nl00Oll1O_dataout : STD_LOGIC; + SIGNAL wire_nl00Ollii_dataout : STD_LOGIC; + SIGNAL wire_nl00Ollil_dataout : STD_LOGIC; + SIGNAL wire_nl00OlliO_dataout : STD_LOGIC; + SIGNAL wire_nl00Ollli_dataout : STD_LOGIC; + SIGNAL wire_nl00Ollll_dataout : STD_LOGIC; + SIGNAL wire_nl00OlllO_dataout : STD_LOGIC; + SIGNAL wire_nl00OllO_dataout : STD_LOGIC; + SIGNAL wire_nl00OllOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OllOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OllOO_dataout : STD_LOGIC; + SIGNAL wire_nl00OlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00OlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00OlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00OlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00OlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00OlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOii_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOil_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOli_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOll_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl00OO00i_dataout : STD_LOGIC; + SIGNAL wire_nl00OO00l_dataout : STD_LOGIC; + SIGNAL wire_nl00OO00O_dataout : STD_LOGIC; + SIGNAL wire_nl00OO01i_dataout : STD_LOGIC; + SIGNAL wire_nl00OO01l_dataout : STD_LOGIC; + SIGNAL wire_nl00OO01O_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0il_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0li_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00OO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl00OO10i_dataout : STD_LOGIC; + SIGNAL wire_nl00OO10l_dataout : STD_LOGIC; + SIGNAL wire_nl00OO10O_dataout : STD_LOGIC; + SIGNAL wire_nl00OO11i_dataout : STD_LOGIC; + SIGNAL wire_nl00OO11l_dataout : STD_LOGIC; + SIGNAL wire_nl00OO11O_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1il_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1li_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl00OO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl00OOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl00OOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl00OOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl00OOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl00OOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl00OOiii_dataout : STD_LOGIC; + SIGNAL wire_nl00OOiil_dataout : STD_LOGIC; + SIGNAL wire_nl00OOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOili_dataout : STD_LOGIC; + SIGNAL wire_nl00OOill_dataout : STD_LOGIC; + SIGNAL wire_nl00OOilO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl00OOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl00OOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl00OOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl00OOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl00OOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl00OOlii_dataout : STD_LOGIC; + SIGNAL wire_nl00OOlil_dataout : STD_LOGIC; + SIGNAL wire_nl00OOliO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOlli_dataout : STD_LOGIC; + SIGNAL wire_nl00OOlll_dataout : STD_LOGIC; + SIGNAL wire_nl00OOllO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl00OOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl00OOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl00OOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl00OOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl00OOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOii_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOil_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOli_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOll_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl00OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01000i_dataout : STD_LOGIC; + SIGNAL wire_nl01000l_dataout : STD_LOGIC; + SIGNAL wire_nl01000O_dataout : STD_LOGIC; + SIGNAL wire_nl01001i_dataout : STD_LOGIC; + SIGNAL wire_nl01001l_dataout : STD_LOGIC; + SIGNAL wire_nl01001O_dataout : STD_LOGIC; + SIGNAL wire_nl0100i_dataout : STD_LOGIC; + SIGNAL wire_nl0100ii_dataout : STD_LOGIC; + SIGNAL wire_nl0100il_dataout : STD_LOGIC; + SIGNAL wire_nl0100iO_dataout : STD_LOGIC; + SIGNAL wire_nl0100l_dataout : STD_LOGIC; + SIGNAL wire_nl0100li_dataout : STD_LOGIC; + SIGNAL wire_nl0100ll_dataout : STD_LOGIC; + SIGNAL wire_nl0100lO_dataout : STD_LOGIC; + SIGNAL wire_nl0100O_dataout : STD_LOGIC; + SIGNAL wire_nl0100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0100Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0100Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0100OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0100Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0100Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0100OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0100OO_dataout : STD_LOGIC; + SIGNAL wire_nl0100OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0100OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0100OOO_dataout : STD_LOGIC; + SIGNAL wire_nl010100i_dataout : STD_LOGIC; + SIGNAL wire_nl010100l_dataout : STD_LOGIC; + SIGNAL wire_nl010100O_dataout : STD_LOGIC; + SIGNAL wire_nl010101i_dataout : STD_LOGIC; + SIGNAL wire_nl010101l_dataout : STD_LOGIC; + SIGNAL wire_nl010101O_dataout : STD_LOGIC; + SIGNAL wire_nl01010ii_dataout : STD_LOGIC; + SIGNAL wire_nl01010il_dataout : STD_LOGIC; + SIGNAL wire_nl01010iO_dataout : STD_LOGIC; + SIGNAL wire_nl01010li_dataout : STD_LOGIC; + SIGNAL wire_nl01010ll_dataout : STD_LOGIC; + SIGNAL wire_nl01010lO_dataout : STD_LOGIC; + SIGNAL wire_nl01010Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01010Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01010OO_dataout : STD_LOGIC; + SIGNAL wire_nl010110i_dataout : STD_LOGIC; + SIGNAL wire_nl010110O_dataout : STD_LOGIC; + SIGNAL wire_nl010111i_dataout : STD_LOGIC; + SIGNAL wire_nl010111l_dataout : STD_LOGIC; + SIGNAL wire_nl010111O_dataout : STD_LOGIC; + SIGNAL wire_nl01011ii_dataout : STD_LOGIC; + SIGNAL wire_nl01011il_dataout : STD_LOGIC; + SIGNAL wire_nl01011iO_dataout : STD_LOGIC; + SIGNAL wire_nl01011li_dataout : STD_LOGIC; + SIGNAL wire_nl01011ll_dataout : STD_LOGIC; + SIGNAL wire_nl01011lO_dataout : STD_LOGIC; + SIGNAL wire_nl01011Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01011Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01011OO_dataout : STD_LOGIC; + SIGNAL wire_nl0101i_dataout : STD_LOGIC; + SIGNAL wire_nl0101i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0101i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0101i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0101i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0101iii_dataout : STD_LOGIC; + SIGNAL wire_nl0101iil_dataout : STD_LOGIC; + SIGNAL wire_nl0101iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0101ili_dataout : STD_LOGIC; + SIGNAL wire_nl0101ill_dataout : STD_LOGIC; + SIGNAL wire_nl0101ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0101iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0101iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0101iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0101l_dataout : STD_LOGIC; + SIGNAL wire_nl0101l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0101l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0101l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0101l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0101l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0101l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0101lll_dataout : STD_LOGIC; + SIGNAL wire_nl0101lll_w_lg_dataout59086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0101llO_dataout : STD_LOGIC; + SIGNAL wire_nl0101llO_w_lg_dataout59085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0101O_dataout : STD_LOGIC; + SIGNAL wire_nl0101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0101OO_dataout : STD_LOGIC; + SIGNAL wire_nl010i00i_dataout : STD_LOGIC; + SIGNAL wire_nl010i00l_dataout : STD_LOGIC; + SIGNAL wire_nl010i00O_dataout : STD_LOGIC; + SIGNAL wire_nl010i01i_dataout : STD_LOGIC; + SIGNAL wire_nl010i01l_dataout : STD_LOGIC; + SIGNAL wire_nl010i01O_dataout : STD_LOGIC; + SIGNAL wire_nl010i0i_dataout : STD_LOGIC; + SIGNAL wire_nl010i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl010i0il_dataout : STD_LOGIC; + SIGNAL wire_nl010i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl010i0l_dataout : STD_LOGIC; + SIGNAL wire_nl010i0li_dataout : STD_LOGIC; + SIGNAL wire_nl010i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl010i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl010i0O_dataout : STD_LOGIC; + SIGNAL wire_nl010i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl010i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl010i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl010i10i_dataout : STD_LOGIC; + SIGNAL wire_nl010i10l_dataout : STD_LOGIC; + SIGNAL wire_nl010i10O_dataout : STD_LOGIC; + SIGNAL wire_nl010i11i_dataout : STD_LOGIC; + SIGNAL wire_nl010i11l_dataout : STD_LOGIC; + SIGNAL wire_nl010i11O_dataout : STD_LOGIC; + SIGNAL wire_nl010i1i_dataout : STD_LOGIC; + SIGNAL wire_nl010i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl010i1il_dataout : STD_LOGIC; + SIGNAL wire_nl010i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl010i1l_dataout : STD_LOGIC; + SIGNAL wire_nl010i1li_dataout : STD_LOGIC; + SIGNAL wire_nl010i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl010i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl010i1O_dataout : STD_LOGIC; + SIGNAL wire_nl010i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl010i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl010i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl010ii_dataout : STD_LOGIC; + SIGNAL wire_nl010ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl010ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl010ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl010ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl010ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl010ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl010iii_dataout : STD_LOGIC; + SIGNAL wire_nl010iiii_dataout : STD_LOGIC; + SIGNAL wire_nl010iiil_dataout : STD_LOGIC; + SIGNAL wire_nl010iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl010iil_dataout : STD_LOGIC; + SIGNAL wire_nl010iili_dataout : STD_LOGIC; + SIGNAL wire_nl010iill_dataout : STD_LOGIC; + SIGNAL wire_nl010iilO_dataout : STD_LOGIC; + SIGNAL wire_nl010iiO_dataout : STD_LOGIC; + SIGNAL wire_nl010iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl010iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl010iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl010il_dataout : STD_LOGIC; + SIGNAL wire_nl010il0i_dataout : STD_LOGIC; + SIGNAL wire_nl010il0l_dataout : STD_LOGIC; + SIGNAL wire_nl010il0O_dataout : STD_LOGIC; + SIGNAL wire_nl010il1i_dataout : STD_LOGIC; + SIGNAL wire_nl010il1l_dataout : STD_LOGIC; + SIGNAL wire_nl010il1O_dataout : STD_LOGIC; + SIGNAL wire_nl010ili_dataout : STD_LOGIC; + SIGNAL wire_nl010ilii_dataout : STD_LOGIC; + SIGNAL wire_nl010ilil_dataout : STD_LOGIC; + SIGNAL wire_nl010iliO_dataout : STD_LOGIC; + SIGNAL wire_nl010ill_dataout : STD_LOGIC; + SIGNAL wire_nl010illi_dataout : STD_LOGIC; + SIGNAL wire_nl010illl_dataout : STD_LOGIC; + SIGNAL wire_nl010illO_dataout : STD_LOGIC; + SIGNAL wire_nl010ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl010ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl010ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl010iO_dataout : STD_LOGIC; + SIGNAL wire_nl010iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl010iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl010iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl010iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl010iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl010iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl010iOi_dataout : STD_LOGIC; + SIGNAL wire_nl010iOii_dataout : STD_LOGIC; + SIGNAL wire_nl010iOil_dataout : STD_LOGIC; + SIGNAL wire_nl010iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl010iOl_dataout : STD_LOGIC; + SIGNAL wire_nl010iOli_dataout : STD_LOGIC; + SIGNAL wire_nl010iOll_dataout : STD_LOGIC; + SIGNAL wire_nl010iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl010iOO_dataout : STD_LOGIC; + SIGNAL wire_nl010iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl010iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl010iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl010l00i_dataout : STD_LOGIC; + SIGNAL wire_nl010l00l_dataout : STD_LOGIC; + SIGNAL wire_nl010l00O_dataout : STD_LOGIC; + SIGNAL wire_nl010l01i_dataout : STD_LOGIC; + SIGNAL wire_nl010l01l_dataout : STD_LOGIC; + SIGNAL wire_nl010l01O_dataout : STD_LOGIC; + SIGNAL wire_nl010l0i_dataout : STD_LOGIC; + SIGNAL wire_nl010l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl010l0il_dataout : STD_LOGIC; + SIGNAL wire_nl010l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl010l0l_dataout : STD_LOGIC; + SIGNAL wire_nl010l0li_dataout : STD_LOGIC; + SIGNAL wire_nl010l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl010l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl010l0O_dataout : STD_LOGIC; + SIGNAL wire_nl010l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl010l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl010l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl010l10i_dataout : STD_LOGIC; + SIGNAL wire_nl010l10l_dataout : STD_LOGIC; + SIGNAL wire_nl010l10O_dataout : STD_LOGIC; + SIGNAL wire_nl010l11i_dataout : STD_LOGIC; + SIGNAL wire_nl010l11l_dataout : STD_LOGIC; + SIGNAL wire_nl010l11O_dataout : STD_LOGIC; + SIGNAL wire_nl010l1i_dataout : STD_LOGIC; + SIGNAL wire_nl010l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl010l1il_dataout : STD_LOGIC; + SIGNAL wire_nl010l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl010l1l_dataout : STD_LOGIC; + SIGNAL wire_nl010l1li_dataout : STD_LOGIC; + SIGNAL wire_nl010l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl010l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl010l1O_dataout : STD_LOGIC; + SIGNAL wire_nl010l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl010l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl010l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl010li_dataout : STD_LOGIC; + SIGNAL wire_nl010li0i_dataout : STD_LOGIC; + SIGNAL wire_nl010li0l_dataout : STD_LOGIC; + SIGNAL wire_nl010li0O_dataout : STD_LOGIC; + SIGNAL wire_nl010li1i_dataout : STD_LOGIC; + SIGNAL wire_nl010li1l_dataout : STD_LOGIC; + SIGNAL wire_nl010li1O_dataout : STD_LOGIC; + SIGNAL wire_nl010lii_dataout : STD_LOGIC; + SIGNAL wire_nl010liii_dataout : STD_LOGIC; + SIGNAL wire_nl010liil_dataout : STD_LOGIC; + SIGNAL wire_nl010liiO_dataout : STD_LOGIC; + SIGNAL wire_nl010lil_dataout : STD_LOGIC; + SIGNAL wire_nl010lili_dataout : STD_LOGIC; + SIGNAL wire_nl010lill_dataout : STD_LOGIC; + SIGNAL wire_nl010lilO_dataout : STD_LOGIC; + SIGNAL wire_nl010liO_dataout : STD_LOGIC; + SIGNAL wire_nl010liOi_dataout : STD_LOGIC; + SIGNAL wire_nl010liOl_dataout : STD_LOGIC; + SIGNAL wire_nl010liOO_dataout : STD_LOGIC; + SIGNAL wire_nl010ll_dataout : STD_LOGIC; + SIGNAL wire_nl010ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl010ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl010ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl010ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl010ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl010ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl010lli_dataout : STD_LOGIC; + SIGNAL wire_nl010llii_dataout : STD_LOGIC; + SIGNAL wire_nl010llil_dataout : STD_LOGIC; + SIGNAL wire_nl010lliO_dataout : STD_LOGIC; + SIGNAL wire_nl010lll_dataout : STD_LOGIC; + SIGNAL wire_nl010llli_dataout : STD_LOGIC; + SIGNAL wire_nl010llll_dataout : STD_LOGIC; + SIGNAL wire_nl010lllO_dataout : STD_LOGIC; + SIGNAL wire_nl010llO_dataout : STD_LOGIC; + SIGNAL wire_nl010llOi_dataout : STD_LOGIC; + SIGNAL wire_nl010llOl_dataout : STD_LOGIC; + SIGNAL wire_nl010llOO_dataout : STD_LOGIC; + SIGNAL wire_nl010lO_dataout : STD_LOGIC; + SIGNAL wire_nl010lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl010lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl010lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl010lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl010lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl010lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl010lOi_dataout : STD_LOGIC; + SIGNAL wire_nl010lOii_dataout : STD_LOGIC; + SIGNAL wire_nl010lOil_dataout : STD_LOGIC; + SIGNAL wire_nl010lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl010lOl_dataout : STD_LOGIC; + SIGNAL wire_nl010lOli_dataout : STD_LOGIC; + SIGNAL wire_nl010lOll_dataout : STD_LOGIC; + SIGNAL wire_nl010lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl010lOO_dataout : STD_LOGIC; + SIGNAL wire_nl010lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl010lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl010lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl010O00i_dataout : STD_LOGIC; + SIGNAL wire_nl010O00l_dataout : STD_LOGIC; + SIGNAL wire_nl010O01i_dataout : STD_LOGIC; + SIGNAL wire_nl010O01l_dataout : STD_LOGIC; + SIGNAL wire_nl010O0i_dataout : STD_LOGIC; + SIGNAL wire_nl010O0l_dataout : STD_LOGIC; + SIGNAL wire_nl010O0O_dataout : STD_LOGIC; + SIGNAL wire_nl010O10i_dataout : STD_LOGIC; + SIGNAL wire_nl010O10l_dataout : STD_LOGIC; + SIGNAL wire_nl010O10O_dataout : STD_LOGIC; + SIGNAL wire_nl010O11i_dataout : STD_LOGIC; + SIGNAL wire_nl010O11l_dataout : STD_LOGIC; + SIGNAL wire_nl010O11O_dataout : STD_LOGIC; + SIGNAL wire_nl010O11O_w_lg_dataout54062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010O1i_dataout : STD_LOGIC; + SIGNAL wire_nl010O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl010O1il_dataout : STD_LOGIC; + SIGNAL wire_nl010O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl010O1l_dataout : STD_LOGIC; + SIGNAL wire_nl010O1li_dataout : STD_LOGIC; + SIGNAL wire_nl010O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl010O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl010O1O_dataout : STD_LOGIC; + SIGNAL wire_nl010O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl010O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl010O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl010Oi_dataout : STD_LOGIC; + SIGNAL wire_nl010Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl010Oi0i_w_lg_w_lg_dataout54122w54133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010Oi0i_w_lg_dataout54142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010Oi0i_w_lg_dataout54122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl010Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl010Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl010Oi1l_w_lg_dataout54125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl010Oi1O_w_lg_dataout54123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl010Oii_dataout : STD_LOGIC; + SIGNAL wire_nl010Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl010Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl010OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl010Oil_dataout : STD_LOGIC; + SIGNAL wire_nl010Oili_dataout : STD_LOGIC; + SIGNAL wire_nl010Oill_dataout : STD_LOGIC; + SIGNAL wire_nl010OilO_dataout : STD_LOGIC; + SIGNAL wire_nl010OiO_dataout : STD_LOGIC; + SIGNAL wire_nl010OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl010OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl010OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl010Ol_dataout : STD_LOGIC; + SIGNAL wire_nl010Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl010Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl010Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl010Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl010Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl010Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl010Olii_dataout : STD_LOGIC; + SIGNAL wire_nl010OlO_dataout : STD_LOGIC; + SIGNAL wire_nl010OO_dataout : STD_LOGIC; + SIGNAL wire_nl010OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl010OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl010OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl010OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl010OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl010OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl010OOii_dataout : STD_LOGIC; + SIGNAL wire_nl010OOil_dataout : STD_LOGIC; + SIGNAL wire_nl010OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl010OOli_dataout : STD_LOGIC; + SIGNAL wire_nl010OOll_dataout : STD_LOGIC; + SIGNAL wire_nl010OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl010OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl010OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl010OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl011000i_dataout : STD_LOGIC; + SIGNAL wire_nl011000l_dataout : STD_LOGIC; + SIGNAL wire_nl011000O_dataout : STD_LOGIC; + SIGNAL wire_nl011001i_dataout : STD_LOGIC; + SIGNAL wire_nl011001l_dataout : STD_LOGIC; + SIGNAL wire_nl011001O_dataout : STD_LOGIC; + SIGNAL wire_nl01100i_dataout : STD_LOGIC; + SIGNAL wire_nl01100ii_dataout : STD_LOGIC; + SIGNAL wire_nl01100il_dataout : STD_LOGIC; + SIGNAL wire_nl01100iO_dataout : STD_LOGIC; + SIGNAL wire_nl01100l_dataout : STD_LOGIC; + SIGNAL wire_nl01100li_dataout : STD_LOGIC; + SIGNAL wire_nl01100ll_dataout : STD_LOGIC; + SIGNAL wire_nl01100lO_dataout : STD_LOGIC; + SIGNAL wire_nl01100O_dataout : STD_LOGIC; + SIGNAL wire_nl01100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01100OO_dataout : STD_LOGIC; + SIGNAL wire_nl011010i_dataout : STD_LOGIC; + SIGNAL wire_nl011010l_dataout : STD_LOGIC; + SIGNAL wire_nl011010O_dataout : STD_LOGIC; + SIGNAL wire_nl011011i_dataout : STD_LOGIC; + SIGNAL wire_nl011011l_dataout : STD_LOGIC; + SIGNAL wire_nl011011O_dataout : STD_LOGIC; + SIGNAL wire_nl01101i_dataout : STD_LOGIC; + SIGNAL wire_nl01101ii_dataout : STD_LOGIC; + SIGNAL wire_nl01101il_dataout : STD_LOGIC; + SIGNAL wire_nl01101iO_dataout : STD_LOGIC; + SIGNAL wire_nl01101l_dataout : STD_LOGIC; + SIGNAL wire_nl01101li_dataout : STD_LOGIC; + SIGNAL wire_nl01101ll_dataout : STD_LOGIC; + SIGNAL wire_nl01101lO_dataout : STD_LOGIC; + SIGNAL wire_nl01101O_dataout : STD_LOGIC; + SIGNAL wire_nl01101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01101OO_dataout : STD_LOGIC; + SIGNAL wire_nl0110i_dataout : STD_LOGIC; + SIGNAL wire_nl0110i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0110i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0110i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0110i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0110i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0110i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0110ii_dataout : STD_LOGIC; + SIGNAL wire_nl0110iii_dataout : STD_LOGIC; + SIGNAL wire_nl0110iil_dataout : STD_LOGIC; + SIGNAL wire_nl0110iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0110il_dataout : STD_LOGIC; + SIGNAL wire_nl0110ili_dataout : STD_LOGIC; + SIGNAL wire_nl0110ill_dataout : STD_LOGIC; + SIGNAL wire_nl0110ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0110iO_dataout : STD_LOGIC; + SIGNAL wire_nl0110iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0110iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0110iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0110l_dataout : STD_LOGIC; + SIGNAL wire_nl0110l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0110l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0110l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0110l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0110l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0110l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0110li_dataout : STD_LOGIC; + SIGNAL wire_nl0110ll_dataout : STD_LOGIC; + SIGNAL wire_nl0110lli_dataout : STD_LOGIC; + SIGNAL wire_nl0110lll_dataout : STD_LOGIC; + SIGNAL wire_nl0110llO_dataout : STD_LOGIC; + SIGNAL wire_nl0110lO_dataout : STD_LOGIC; + SIGNAL wire_nl0110lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0110lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0110lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0110O_dataout : STD_LOGIC; + SIGNAL wire_nl0110O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0110O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0110O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0110O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0110O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0110O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0110Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0110Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0110OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0110Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0110Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0110OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0110OO_dataout : STD_LOGIC; + SIGNAL wire_nl011100i_dataout : STD_LOGIC; + SIGNAL wire_nl011100l_dataout : STD_LOGIC; + SIGNAL wire_nl011100O_dataout : STD_LOGIC; + SIGNAL wire_nl011101i_dataout : STD_LOGIC; + SIGNAL wire_nl011101l_dataout : STD_LOGIC; + SIGNAL wire_nl011101O_dataout : STD_LOGIC; + SIGNAL wire_nl01110i_dataout : STD_LOGIC; + SIGNAL wire_nl01110ii_dataout : STD_LOGIC; + SIGNAL wire_nl01110il_dataout : STD_LOGIC; + SIGNAL wire_nl01110iO_dataout : STD_LOGIC; + SIGNAL wire_nl01110l_dataout : STD_LOGIC; + SIGNAL wire_nl01110O_dataout : STD_LOGIC; + SIGNAL wire_nl01110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01110OO_dataout : STD_LOGIC; + SIGNAL wire_nl011110i_dataout : STD_LOGIC; + SIGNAL wire_nl011110l_dataout : STD_LOGIC; + SIGNAL wire_nl011110O_dataout : STD_LOGIC; + SIGNAL wire_nl01111i_dataout : STD_LOGIC; + SIGNAL wire_nl01111ii_dataout : STD_LOGIC; + SIGNAL wire_nl01111il_dataout : STD_LOGIC; + SIGNAL wire_nl01111iO_dataout : STD_LOGIC; + SIGNAL wire_nl01111l_dataout : STD_LOGIC; + SIGNAL wire_nl01111li_dataout : STD_LOGIC; + SIGNAL wire_nl01111ll_dataout : STD_LOGIC; + SIGNAL wire_nl01111lO_dataout : STD_LOGIC; + SIGNAL wire_nl01111O_dataout : STD_LOGIC; + SIGNAL wire_nl01111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01111OO_dataout : STD_LOGIC; + SIGNAL wire_nl0111i_dataout : STD_LOGIC; + SIGNAL wire_nl0111i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0111i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0111i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0111i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0111i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0111i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0111ii_dataout : STD_LOGIC; + SIGNAL wire_nl0111il_dataout : STD_LOGIC; + SIGNAL wire_nl0111iO_dataout : STD_LOGIC; + SIGNAL wire_nl0111l_dataout : STD_LOGIC; + SIGNAL wire_nl0111li_dataout : STD_LOGIC; + SIGNAL wire_nl0111ll_dataout : STD_LOGIC; + SIGNAL wire_nl0111lO_dataout : STD_LOGIC; + SIGNAL wire_nl0111O_dataout : STD_LOGIC; + SIGNAL wire_nl0111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0111OO_dataout : STD_LOGIC; + SIGNAL wire_nl0111OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0111OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0111OOO_dataout : STD_LOGIC; + SIGNAL wire_nl011i00i_dataout : STD_LOGIC; + SIGNAL wire_nl011i00l_dataout : STD_LOGIC; + SIGNAL wire_nl011i01i_dataout : STD_LOGIC; + SIGNAL wire_nl011i01l_dataout : STD_LOGIC; + SIGNAL wire_nl011i01O_dataout : STD_LOGIC; + SIGNAL wire_nl011i0i_dataout : STD_LOGIC; + SIGNAL wire_nl011i0l_dataout : STD_LOGIC; + SIGNAL wire_nl011i0O_dataout : STD_LOGIC; + SIGNAL wire_nl011i10O_dataout : STD_LOGIC; + SIGNAL wire_nl011i1i_dataout : STD_LOGIC; + SIGNAL wire_nl011i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl011i1il_dataout : STD_LOGIC; + SIGNAL wire_nl011i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl011i1l_dataout : STD_LOGIC; + SIGNAL wire_nl011i1li_dataout : STD_LOGIC; + SIGNAL wire_nl011i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl011i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl011i1O_dataout : STD_LOGIC; + SIGNAL wire_nl011i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl011i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl011i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl011ii_dataout : STD_LOGIC; + SIGNAL wire_nl011iii_dataout : STD_LOGIC; + SIGNAL wire_nl011iil_dataout : STD_LOGIC; + SIGNAL wire_nl011iiO_dataout : STD_LOGIC; + SIGNAL wire_nl011il_dataout : STD_LOGIC; + SIGNAL wire_nl011ili_dataout : STD_LOGIC; + SIGNAL wire_nl011ill_dataout : STD_LOGIC; + SIGNAL wire_nl011ilO_dataout : STD_LOGIC; + SIGNAL wire_nl011iO_dataout : STD_LOGIC; + SIGNAL wire_nl011iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl011iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl011iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl011iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl011iO1i_w_lg_dataout54846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl011iO1l_w_lg_dataout54844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl011iO1O_w54848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011iO1O_w_lg_w_lg_w_lg_dataout54843w54845w54847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011iO1O_w_lg_w_lg_dataout54843w54845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011iO1O_w_lg_dataout54843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011iOi_dataout : STD_LOGIC; + SIGNAL wire_nl011iOii_dataout : STD_LOGIC; + SIGNAL wire_nl011iOil_dataout : STD_LOGIC; + SIGNAL wire_nl011iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl011iOl_dataout : STD_LOGIC; + SIGNAL wire_nl011iOli_dataout : STD_LOGIC; + SIGNAL wire_nl011iOll_dataout : STD_LOGIC; + SIGNAL wire_nl011iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl011iOO_dataout : STD_LOGIC; + SIGNAL wire_nl011iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl011iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl011iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl011l0il_dataout : STD_LOGIC; + SIGNAL wire_nl011l0il_w_lg_dataout58915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011l10i_dataout : STD_LOGIC; + SIGNAL wire_nl011l10l_dataout : STD_LOGIC; + SIGNAL wire_nl011l10O_dataout : STD_LOGIC; + SIGNAL wire_nl011l11i_dataout : STD_LOGIC; + SIGNAL wire_nl011l11l_dataout : STD_LOGIC; + SIGNAL wire_nl011l11O_dataout : STD_LOGIC; + SIGNAL wire_nl011l1i_dataout : STD_LOGIC; + SIGNAL wire_nl011l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl011l1l_dataout : STD_LOGIC; + SIGNAL wire_nl011l1li_dataout : STD_LOGIC; + SIGNAL wire_nl011l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl011l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl011l1O_dataout : STD_LOGIC; + SIGNAL wire_nl011l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl011l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl011li_dataout : STD_LOGIC; + SIGNAL wire_nl011lii_dataout : STD_LOGIC; + SIGNAL wire_nl011liO_dataout : STD_LOGIC; + SIGNAL wire_nl011ll_dataout : STD_LOGIC; + SIGNAL wire_nl011ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl011ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl011llii_dataout : STD_LOGIC; + SIGNAL wire_nl011llil_dataout : STD_LOGIC; + SIGNAL wire_nl011lliO_dataout : STD_LOGIC; + SIGNAL wire_nl011lll_dataout : STD_LOGIC; + SIGNAL wire_nl011llli_dataout : STD_LOGIC; + SIGNAL wire_nl011llll_dataout : STD_LOGIC; + SIGNAL wire_nl011lllO_dataout : STD_LOGIC; + SIGNAL wire_nl011llOi_dataout : STD_LOGIC; + SIGNAL wire_nl011llOl_dataout : STD_LOGIC; + SIGNAL wire_nl011llOO_dataout : STD_LOGIC; + SIGNAL wire_nl011lO_dataout : STD_LOGIC; + SIGNAL wire_nl011lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl011lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl011lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl011lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl011lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl011lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl011lOii_dataout : STD_LOGIC; + SIGNAL wire_nl011lOil_dataout : STD_LOGIC; + SIGNAL wire_nl011lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl011lOl_dataout : STD_LOGIC; + SIGNAL wire_nl011lOli_dataout : STD_LOGIC; + SIGNAL wire_nl011lOll_dataout : STD_LOGIC; + SIGNAL wire_nl011lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl011lOO_dataout : STD_LOGIC; + SIGNAL wire_nl011lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl011lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl011lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl011O00i_dataout : STD_LOGIC; + SIGNAL wire_nl011O00l_dataout : STD_LOGIC; + SIGNAL wire_nl011O00O_dataout : STD_LOGIC; + SIGNAL wire_nl011O01i_dataout : STD_LOGIC; + SIGNAL wire_nl011O01l_dataout : STD_LOGIC; + SIGNAL wire_nl011O01O_dataout : STD_LOGIC; + SIGNAL wire_nl011O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl011O0il_dataout : STD_LOGIC; + SIGNAL wire_nl011O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl011O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl011O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl011O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl011O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl011O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl011O10i_dataout : STD_LOGIC; + SIGNAL wire_nl011O10l_dataout : STD_LOGIC; + SIGNAL wire_nl011O10O_dataout : STD_LOGIC; + SIGNAL wire_nl011O11i_dataout : STD_LOGIC; + SIGNAL wire_nl011O11l_dataout : STD_LOGIC; + SIGNAL wire_nl011O11O_dataout : STD_LOGIC; + SIGNAL wire_nl011O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl011O1il_dataout : STD_LOGIC; + SIGNAL wire_nl011O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl011O1li_dataout : STD_LOGIC; + SIGNAL wire_nl011O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl011O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl011O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl011O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl011O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl011Oi_dataout : STD_LOGIC; + SIGNAL wire_nl011Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl011OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl011OilO_dataout : STD_LOGIC; + SIGNAL wire_nl011OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl011Ol_dataout : STD_LOGIC; + SIGNAL wire_nl011Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl011Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl011Ol0l_w_lg_dataout55199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl011Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl011Ol1l_w_lg_w_lg_dataout54516w54517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011Ol1l_w_lg_dataout54829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011Ol1l_w_lg_dataout54183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011Ol1l_w_lg_dataout54516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl011Ol1O_w_lg_dataout54215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011Ol1O_w_lg_dataout8960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011Olil_dataout : STD_LOGIC; + SIGNAL wire_nl011OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl011OlOO_w_lg_dataout8890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011OO_dataout : STD_LOGIC; + SIGNAL wire_nl011OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl011OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl011OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl011OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl011OO1i_w_lg_dataout54065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl011OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl011OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl011OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01i00l_dataout : STD_LOGIC; + SIGNAL wire_nl01i01l_dataout : STD_LOGIC; + SIGNAL wire_nl01i0i_dataout : STD_LOGIC; + SIGNAL wire_nl01i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01i0l_dataout : STD_LOGIC; + SIGNAL wire_nl01i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01i0O_dataout : STD_LOGIC; + SIGNAL wire_nl01i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01i100i_dataout : STD_LOGIC; + SIGNAL wire_nl01i100l_dataout : STD_LOGIC; + SIGNAL wire_nl01i100O_dataout : STD_LOGIC; + SIGNAL wire_nl01i101l_dataout : STD_LOGIC; + SIGNAL wire_nl01i101O_dataout : STD_LOGIC; + SIGNAL wire_nl01i10ii_dataout : STD_LOGIC; + SIGNAL wire_nl01i10il_dataout : STD_LOGIC; + SIGNAL wire_nl01i10iO_dataout : STD_LOGIC; + SIGNAL wire_nl01i10l_dataout : STD_LOGIC; + SIGNAL wire_nl01i110i_dataout : STD_LOGIC; + SIGNAL wire_nl01i110l_dataout : STD_LOGIC; + SIGNAL wire_nl01i110O_dataout : STD_LOGIC; + SIGNAL wire_nl01i111i_dataout : STD_LOGIC; + SIGNAL wire_nl01i111l_dataout : STD_LOGIC; + SIGNAL wire_nl01i111O_dataout : STD_LOGIC; + SIGNAL wire_nl01i11i_dataout : STD_LOGIC; + SIGNAL wire_nl01i11ii_dataout : STD_LOGIC; + SIGNAL wire_nl01i11il_dataout : STD_LOGIC; + SIGNAL wire_nl01i11iO_dataout : STD_LOGIC; + SIGNAL wire_nl01i11li_dataout : STD_LOGIC; + SIGNAL wire_nl01i11ll_dataout : STD_LOGIC; + SIGNAL wire_nl01i11lO_dataout : STD_LOGIC; + SIGNAL wire_nl01i11O_dataout : STD_LOGIC; + SIGNAL wire_nl01i1i_dataout : STD_LOGIC; + SIGNAL wire_nl01i1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl01i1il_dataout : STD_LOGIC; + SIGNAL wire_nl01i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01i1l_dataout : STD_LOGIC; + SIGNAL wire_nl01i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01i1O_dataout : STD_LOGIC; + SIGNAL wire_nl01i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01ii00i_dataout : STD_LOGIC; + SIGNAL wire_nl01ii00l_dataout : STD_LOGIC; + SIGNAL wire_nl01ii00O_dataout : STD_LOGIC; + SIGNAL wire_nl01ii01i_dataout : STD_LOGIC; + SIGNAL wire_nl01ii01l_dataout : STD_LOGIC; + SIGNAL wire_nl01ii01O_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0il_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0li_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01ii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl01ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl01ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl01iii_dataout : STD_LOGIC; + SIGNAL wire_nl01iii0i_dataout : STD_LOGIC; + SIGNAL wire_nl01iii0l_dataout : STD_LOGIC; + SIGNAL wire_nl01iii0O_dataout : STD_LOGIC; + SIGNAL wire_nl01iii1i_dataout : STD_LOGIC; + SIGNAL wire_nl01iii1l_dataout : STD_LOGIC; + SIGNAL wire_nl01iii1O_dataout : STD_LOGIC; + SIGNAL wire_nl01iiiii_dataout : STD_LOGIC; + SIGNAL wire_nl01iiiil_dataout : STD_LOGIC; + SIGNAL wire_nl01iiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl01iiili_dataout : STD_LOGIC; + SIGNAL wire_nl01iiill_dataout : STD_LOGIC; + SIGNAL wire_nl01iiilO_dataout : STD_LOGIC; + SIGNAL wire_nl01iiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl01iiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl01iiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl01iil_dataout : STD_LOGIC; + SIGNAL wire_nl01iil0i_dataout : STD_LOGIC; + SIGNAL wire_nl01iil0l_dataout : STD_LOGIC; + SIGNAL wire_nl01iil0O_dataout : STD_LOGIC; + SIGNAL wire_nl01iil1i_dataout : STD_LOGIC; + SIGNAL wire_nl01iil1l_dataout : STD_LOGIC; + SIGNAL wire_nl01iil1O_dataout : STD_LOGIC; + SIGNAL wire_nl01iili_dataout : STD_LOGIC; + SIGNAL wire_nl01iilii_dataout : STD_LOGIC; + SIGNAL wire_nl01iilil_dataout : STD_LOGIC; + SIGNAL wire_nl01iiliO_dataout : STD_LOGIC; + SIGNAL wire_nl01iilli_dataout : STD_LOGIC; + SIGNAL wire_nl01iilll_dataout : STD_LOGIC; + SIGNAL wire_nl01iillO_dataout : STD_LOGIC; + SIGNAL wire_nl01iilOi_dataout : STD_LOGIC; + SIGNAL wire_nl01iilOl_dataout : STD_LOGIC; + SIGNAL wire_nl01iilOO_dataout : STD_LOGIC; + SIGNAL wire_nl01iiO_dataout : STD_LOGIC; + SIGNAL wire_nl01iiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01iiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01iiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl01iiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01iiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01iiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01iiOii_dataout : STD_LOGIC; + SIGNAL wire_nl01iiOil_dataout : STD_LOGIC; + SIGNAL wire_nl01iiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl01iiOli_dataout : STD_LOGIC; + SIGNAL wire_nl01iiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01il00l_dataout : STD_LOGIC; + SIGNAL wire_nl01il00O_dataout : STD_LOGIC; + SIGNAL wire_nl01il0i_dataout : STD_LOGIC; + SIGNAL wire_nl01il0ii_dataout : STD_LOGIC; + SIGNAL wire_nl01il0il_dataout : STD_LOGIC; + SIGNAL wire_nl01il0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01il0l_dataout : STD_LOGIC; + SIGNAL wire_nl01il0li_dataout : STD_LOGIC; + SIGNAL wire_nl01il0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01il0lO_dataout : STD_LOGIC; + SIGNAL wire_nl01il0O_dataout : STD_LOGIC; + SIGNAL wire_nl01il0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01il0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01il0OO_dataout : STD_LOGIC; + SIGNAL wire_nl01il11i_dataout : STD_LOGIC; + SIGNAL wire_nl01il11l_dataout : STD_LOGIC; + SIGNAL wire_nl01il1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01ili_dataout : STD_LOGIC; + SIGNAL wire_nl01ili1i_dataout : STD_LOGIC; + SIGNAL wire_nl01ili1l_dataout : STD_LOGIC; + SIGNAL wire_nl01ili1O_dataout : STD_LOGIC; + SIGNAL wire_nl01ilii_dataout : STD_LOGIC; + SIGNAL wire_nl01ilil_dataout : STD_LOGIC; + SIGNAL wire_nl01iliO_dataout : STD_LOGIC; + SIGNAL wire_nl01ill_dataout : STD_LOGIC; + SIGNAL wire_nl01ilO_dataout : STD_LOGIC; + SIGNAL wire_nl01ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl01ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl01iO00i_dataout : STD_LOGIC; + SIGNAL wire_nl01iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01iOi_dataout : STD_LOGIC; + SIGNAL wire_nl01iOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl01iOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl01iOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl01iOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl01iOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl01iOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl01iOii_dataout : STD_LOGIC; + SIGNAL wire_nl01iOl_dataout : STD_LOGIC; + SIGNAL wire_nl01iOO_dataout : STD_LOGIC; + SIGNAL wire_nl01l010i_dataout : STD_LOGIC; + SIGNAL wire_nl01l010l_dataout : STD_LOGIC; + SIGNAL wire_nl01l010O_dataout : STD_LOGIC; + SIGNAL wire_nl01l011i_dataout : STD_LOGIC; + SIGNAL wire_nl01l011l_dataout : STD_LOGIC; + SIGNAL wire_nl01l011O_dataout : STD_LOGIC; + SIGNAL wire_nl01l01ii_dataout : STD_LOGIC; + SIGNAL wire_nl01l01il_dataout : STD_LOGIC; + SIGNAL wire_nl01l01iO_dataout : STD_LOGIC; + SIGNAL wire_nl01l01iO_w_lg_dataout53565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l0i_dataout : STD_LOGIC; + SIGNAL wire_nl01l0l_dataout : STD_LOGIC; + SIGNAL wire_nl01l0O_dataout : STD_LOGIC; + SIGNAL wire_nl01l0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl01l0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl01l0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl01l0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl01l0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl01l0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl01l0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl01l0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl01l0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl01l0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl01l0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl01l1i_dataout : STD_LOGIC; + SIGNAL wire_nl01l1l_dataout : STD_LOGIC; + SIGNAL wire_nl01l1liO_dataout : STD_LOGIC; + SIGNAL wire_nl01l1lli_dataout : STD_LOGIC; + SIGNAL wire_nl01l1lll_dataout : STD_LOGIC; + SIGNAL wire_nl01l1O_dataout : STD_LOGIC; + SIGNAL wire_nl01l1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl01l1OOl_w_lg_w_lg_dataout53587w53588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l1OOl_w_lg_dataout53587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl01li00i_dataout : STD_LOGIC; + SIGNAL wire_nl01li00l_dataout : STD_LOGIC; + SIGNAL wire_nl01li00O_dataout : STD_LOGIC; + SIGNAL wire_nl01li01i_dataout : STD_LOGIC; + SIGNAL wire_nl01li01l_dataout : STD_LOGIC; + SIGNAL wire_nl01li01O_dataout : STD_LOGIC; + SIGNAL wire_nl01li0ii_dataout : STD_LOGIC; + SIGNAL wire_nl01li0il_dataout : STD_LOGIC; + SIGNAL wire_nl01li0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01li0li_dataout : STD_LOGIC; + SIGNAL wire_nl01li0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01li0lO_dataout : STD_LOGIC; + SIGNAL wire_nl01li0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01li0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01li0OO_dataout : STD_LOGIC; + SIGNAL wire_nl01li10i_dataout : STD_LOGIC; + SIGNAL wire_nl01li10l_dataout : STD_LOGIC; + SIGNAL wire_nl01li10O_dataout : STD_LOGIC; + SIGNAL wire_nl01li11i_dataout : STD_LOGIC; + SIGNAL wire_nl01li11l_dataout : STD_LOGIC; + SIGNAL wire_nl01li11O_dataout : STD_LOGIC; + SIGNAL wire_nl01li1ii_dataout : STD_LOGIC; + SIGNAL wire_nl01li1il_dataout : STD_LOGIC; + SIGNAL wire_nl01li1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01li1li_dataout : STD_LOGIC; + SIGNAL wire_nl01li1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01li1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01li1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01li1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01li1OO_dataout : STD_LOGIC; + SIGNAL wire_nl01lii_dataout : STD_LOGIC; + SIGNAL wire_nl01lii0i_dataout : STD_LOGIC; + SIGNAL wire_nl01lii0l_dataout : STD_LOGIC; + SIGNAL wire_nl01lii0O_dataout : STD_LOGIC; + SIGNAL wire_nl01lii1i_dataout : STD_LOGIC; + SIGNAL wire_nl01lii1l_dataout : STD_LOGIC; + SIGNAL wire_nl01lii1O_dataout : STD_LOGIC; + SIGNAL wire_nl01liiii_dataout : STD_LOGIC; + SIGNAL wire_nl01liiil_dataout : STD_LOGIC; + SIGNAL wire_nl01liiiO_dataout : STD_LOGIC; + SIGNAL wire_nl01liili_dataout : STD_LOGIC; + SIGNAL wire_nl01liill_dataout : STD_LOGIC; + SIGNAL wire_nl01liilO_dataout : STD_LOGIC; + SIGNAL wire_nl01liiOi_dataout : STD_LOGIC; + SIGNAL wire_nl01liiOl_dataout : STD_LOGIC; + SIGNAL wire_nl01liiOO_dataout : STD_LOGIC; + SIGNAL wire_nl01lil_dataout : STD_LOGIC; + SIGNAL wire_nl01lil0i_dataout : STD_LOGIC; + SIGNAL wire_nl01lil0l_dataout : STD_LOGIC; + SIGNAL wire_nl01lil0O_dataout : STD_LOGIC; + SIGNAL wire_nl01lil1i_dataout : STD_LOGIC; + SIGNAL wire_nl01lil1l_dataout : STD_LOGIC; + SIGNAL wire_nl01lil1O_dataout : STD_LOGIC; + SIGNAL wire_nl01lilii_dataout : STD_LOGIC; + SIGNAL wire_nl01lilil_dataout : STD_LOGIC; + SIGNAL wire_nl01liliO_dataout : STD_LOGIC; + SIGNAL wire_nl01lilli_dataout : STD_LOGIC; + SIGNAL wire_nl01lilll_dataout : STD_LOGIC; + SIGNAL wire_nl01lillO_dataout : STD_LOGIC; + SIGNAL wire_nl01lilOi_dataout : STD_LOGIC; + SIGNAL wire_nl01lilOl_dataout : STD_LOGIC; + SIGNAL wire_nl01lilOO_dataout : STD_LOGIC; + SIGNAL wire_nl01liO_dataout : STD_LOGIC; + SIGNAL wire_nl01liO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01liO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01liO0O_dataout : STD_LOGIC; + SIGNAL wire_nl01liO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01liO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01liO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01liOii_dataout : STD_LOGIC; + SIGNAL wire_nl01liOil_dataout : STD_LOGIC; + SIGNAL wire_nl01liOiO_dataout : STD_LOGIC; + SIGNAL wire_nl01liOli_dataout : STD_LOGIC; + SIGNAL wire_nl01liOll_dataout : STD_LOGIC; + SIGNAL wire_nl01liOlO_dataout : STD_LOGIC; + SIGNAL wire_nl01liOOi_dataout : STD_LOGIC; + SIGNAL wire_nl01liOOl_dataout : STD_LOGIC; + SIGNAL wire_nl01liOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01ll00i_dataout : STD_LOGIC; + SIGNAL wire_nl01ll00l_dataout : STD_LOGIC; + SIGNAL wire_nl01ll01i_dataout : STD_LOGIC; + SIGNAL wire_nl01ll01l_dataout : STD_LOGIC; + SIGNAL wire_nl01ll01O_dataout : STD_LOGIC; + SIGNAL wire_nl01ll10i_dataout : STD_LOGIC; + SIGNAL wire_nl01ll10l_dataout : STD_LOGIC; + SIGNAL wire_nl01ll10O_dataout : STD_LOGIC; + SIGNAL wire_nl01ll11i_dataout : STD_LOGIC; + SIGNAL wire_nl01ll11l_dataout : STD_LOGIC; + SIGNAL wire_nl01ll11O_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1il_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1li_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01ll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl01lli_dataout : STD_LOGIC; + SIGNAL wire_nl01lli1l_dataout : STD_LOGIC; + SIGNAL wire_nl01lli1O_dataout : STD_LOGIC; + SIGNAL wire_nl01lll_dataout : STD_LOGIC; + SIGNAL wire_nl01llO_dataout : STD_LOGIC; + SIGNAL wire_nl01llO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01llO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01llO0O_dataout : STD_LOGIC; + SIGNAL wire_nl01llO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01llO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01llO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01llOii_dataout : STD_LOGIC; + SIGNAL wire_nl01llOil_dataout : STD_LOGIC; + SIGNAL wire_nl01llOiO_dataout : STD_LOGIC; + SIGNAL wire_nl01llOli_dataout : STD_LOGIC; + SIGNAL wire_nl01llOll_dataout : STD_LOGIC; + SIGNAL wire_nl01llOlO_dataout : STD_LOGIC; + SIGNAL wire_nl01llOOi_dataout : STD_LOGIC; + SIGNAL wire_nl01llOOl_dataout : STD_LOGIC; + SIGNAL wire_nl01llOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01lO00i_dataout : STD_LOGIC; + SIGNAL wire_nl01lO00l_dataout : STD_LOGIC; + SIGNAL wire_nl01lO00O_dataout : STD_LOGIC; + SIGNAL wire_nl01lO01i_dataout : STD_LOGIC; + SIGNAL wire_nl01lO01l_dataout : STD_LOGIC; + SIGNAL wire_nl01lO01O_dataout : STD_LOGIC; + SIGNAL wire_nl01lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl01lO11i_dataout : STD_LOGIC; + SIGNAL wire_nl01lO11l_dataout : STD_LOGIC; + SIGNAL wire_nl01lO11O_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1il_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1li_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01lO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl01lOi_dataout : STD_LOGIC; + SIGNAL wire_nl01lOii_dataout : STD_LOGIC; + SIGNAL wire_nl01lOil_dataout : STD_LOGIC; + SIGNAL wire_nl01lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl01lOl_dataout : STD_LOGIC; + SIGNAL wire_nl01lOli_dataout : STD_LOGIC; + SIGNAL wire_nl01lOll_dataout : STD_LOGIC; + SIGNAL wire_nl01lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl01lOO_dataout : STD_LOGIC; + SIGNAL wire_nl01lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl01lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl01lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01O000i_dataout : STD_LOGIC; + SIGNAL wire_nl01O000l_dataout : STD_LOGIC; + SIGNAL wire_nl01O000O_dataout : STD_LOGIC; + SIGNAL wire_nl01O001i_dataout : STD_LOGIC; + SIGNAL wire_nl01O001l_dataout : STD_LOGIC; + SIGNAL wire_nl01O001O_dataout : STD_LOGIC; + SIGNAL wire_nl01O00i_dataout : STD_LOGIC; + SIGNAL wire_nl01O00ii_dataout : STD_LOGIC; + SIGNAL wire_nl01O00il_dataout : STD_LOGIC; + SIGNAL wire_nl01O00iO_dataout : STD_LOGIC; + SIGNAL wire_nl01O00l_dataout : STD_LOGIC; + SIGNAL wire_nl01O00li_dataout : STD_LOGIC; + SIGNAL wire_nl01O00ll_dataout : STD_LOGIC; + SIGNAL wire_nl01O00lO_dataout : STD_LOGIC; + SIGNAL wire_nl01O00O_dataout : STD_LOGIC; + SIGNAL wire_nl01O00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01O00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01O00OO_dataout : STD_LOGIC; + SIGNAL wire_nl01O010i_dataout : STD_LOGIC; + SIGNAL wire_nl01O010l_dataout : STD_LOGIC; + SIGNAL wire_nl01O010O_dataout : STD_LOGIC; + SIGNAL wire_nl01O011O_dataout : STD_LOGIC; + SIGNAL wire_nl01O01i_dataout : STD_LOGIC; + SIGNAL wire_nl01O01ii_dataout : STD_LOGIC; + SIGNAL wire_nl01O01il_dataout : STD_LOGIC; + SIGNAL wire_nl01O01iO_dataout : STD_LOGIC; + SIGNAL wire_nl01O01l_dataout : STD_LOGIC; + SIGNAL wire_nl01O01li_dataout : STD_LOGIC; + SIGNAL wire_nl01O01ll_dataout : STD_LOGIC; + SIGNAL wire_nl01O01lO_dataout : STD_LOGIC; + SIGNAL wire_nl01O01O_dataout : STD_LOGIC; + SIGNAL wire_nl01O01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01O01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01O01OO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl01O0iii_dataout : STD_LOGIC; + SIGNAL wire_nl01O0iil_dataout : STD_LOGIC; + SIGNAL wire_nl01O0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0il_dataout : STD_LOGIC; + SIGNAL wire_nl01O0ili_dataout : STD_LOGIC; + SIGNAL wire_nl01O0ill_dataout : STD_LOGIC; + SIGNAL wire_nl01O0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl01O0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl01O0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0li_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lii_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lil_dataout : STD_LOGIC; + SIGNAL wire_nl01O0liO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lli_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lll_dataout : STD_LOGIC; + SIGNAL wire_nl01O0llO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl01O0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl01O0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl01O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01O0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl01O0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl01O0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01O0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl01O0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl01O0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl01O0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl01O0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl01O0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl01O10i_dataout : STD_LOGIC; + SIGNAL wire_nl01O10l_dataout : STD_LOGIC; + SIGNAL wire_nl01O10O_dataout : STD_LOGIC; + SIGNAL wire_nl01O11i_dataout : STD_LOGIC; + SIGNAL wire_nl01O11l_dataout : STD_LOGIC; + SIGNAL wire_nl01O11O_dataout : STD_LOGIC; + SIGNAL wire_nl01O1i_dataout : STD_LOGIC; + SIGNAL wire_nl01O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl01O1il_dataout : STD_LOGIC; + SIGNAL wire_nl01O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01O1l_dataout : STD_LOGIC; + SIGNAL wire_nl01O1li_dataout : STD_LOGIC; + SIGNAL wire_nl01O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01O1O_dataout : STD_LOGIC; + SIGNAL wire_nl01O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi00i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi00l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi00O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi01i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi01l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi01O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0il_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0li_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi10i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi10l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi10O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi11i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi11l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi11O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1il_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1li_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oii0i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oii0l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oii1i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oii1l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oii1O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oiiii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oiiil_dataout : STD_LOGIC; + SIGNAL wire_nl01OiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl01Oiili_dataout : STD_LOGIC; + SIGNAL wire_nl01Oiill_dataout : STD_LOGIC; + SIGNAL wire_nl01OiilO_dataout : STD_LOGIC; + SIGNAL wire_nl01OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl01OiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil0i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil0l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil0O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil1i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil1l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oil1O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oili_dataout : STD_LOGIC; + SIGNAL wire_nl01Oilii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oilil_dataout : STD_LOGIC; + SIGNAL wire_nl01OiliO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oill_dataout : STD_LOGIC; + SIGNAL wire_nl01Oilli_dataout : STD_LOGIC; + SIGNAL wire_nl01Oilll_dataout : STD_LOGIC; + SIGNAL wire_nl01OillO_dataout : STD_LOGIC; + SIGNAL wire_nl01OilO_dataout : STD_LOGIC; + SIGNAL wire_nl01OilOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OilOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OilOO_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01OiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOii_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOil_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOli_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOll_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol00l_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol00O_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0il_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0li_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol10l_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol10O_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol11i_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1li_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli0i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli0O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli1i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli1l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oli1O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oliii_dataout : STD_LOGIC; + SIGNAL wire_nl01Oliil_dataout : STD_LOGIC; + SIGNAL wire_nl01OliiO_dataout : STD_LOGIC; + SIGNAL wire_nl01Olil_dataout : STD_LOGIC; + SIGNAL wire_nl01Olili_dataout : STD_LOGIC; + SIGNAL wire_nl01Olill_dataout : STD_LOGIC; + SIGNAL wire_nl01OlilO_dataout : STD_LOGIC; + SIGNAL wire_nl01OliOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OliOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OliOO_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll0i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll0l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll0O_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll1l_dataout : STD_LOGIC; + SIGNAL wire_nl01Oll1O_dataout : STD_LOGIC; + SIGNAL wire_nl01Ollii_dataout : STD_LOGIC; + SIGNAL wire_nl01Ollil_dataout : STD_LOGIC; + SIGNAL wire_nl01OlliO_dataout : STD_LOGIC; + SIGNAL wire_nl01Olll_dataout : STD_LOGIC; + SIGNAL wire_nl01Ollli_dataout : STD_LOGIC; + SIGNAL wire_nl01Ollll_dataout : STD_LOGIC; + SIGNAL wire_nl01OlllO_dataout : STD_LOGIC; + SIGNAL wire_nl01OllO_dataout : STD_LOGIC; + SIGNAL wire_nl01OllOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OllOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OllOO_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01OlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOii_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOil_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOli_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOll_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl01OO00i_dataout : STD_LOGIC; + SIGNAL wire_nl01OO00l_dataout : STD_LOGIC; + SIGNAL wire_nl01OO00O_dataout : STD_LOGIC; + SIGNAL wire_nl01OO01i_dataout : STD_LOGIC; + SIGNAL wire_nl01OO01l_dataout : STD_LOGIC; + SIGNAL wire_nl01OO01O_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0il_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0li_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01OO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl01OO10i_dataout : STD_LOGIC; + SIGNAL wire_nl01OO10l_dataout : STD_LOGIC; + SIGNAL wire_nl01OO10O_dataout : STD_LOGIC; + SIGNAL wire_nl01OO11i_dataout : STD_LOGIC; + SIGNAL wire_nl01OO11l_dataout : STD_LOGIC; + SIGNAL wire_nl01OO11O_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1il_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1li_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl01OO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl01OOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl01OOiii_dataout : STD_LOGIC; + SIGNAL wire_nl01OOiil_dataout : STD_LOGIC; + SIGNAL wire_nl01OOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOili_dataout : STD_LOGIC; + SIGNAL wire_nl01OOill_dataout : STD_LOGIC; + SIGNAL wire_nl01OOilO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl01OOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl01OOlii_dataout : STD_LOGIC; + SIGNAL wire_nl01OOlil_dataout : STD_LOGIC; + SIGNAL wire_nl01OOliO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOlli_dataout : STD_LOGIC; + SIGNAL wire_nl01OOlll_dataout : STD_LOGIC; + SIGNAL wire_nl01OOllO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl01OOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOii_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOil_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOli_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOll_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl01OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i000i_dataout : STD_LOGIC; + SIGNAL wire_nl0i000l_dataout : STD_LOGIC; + SIGNAL wire_nl0i000O_dataout : STD_LOGIC; + SIGNAL wire_nl0i001i_dataout : STD_LOGIC; + SIGNAL wire_nl0i001l_dataout : STD_LOGIC; + SIGNAL wire_nl0i001O_dataout : STD_LOGIC; + SIGNAL wire_nl0i00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i00ili_dataout : STD_LOGIC; + SIGNAL wire_nl0i00ill_dataout : STD_LOGIC; + SIGNAL wire_nl0i00ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i00iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i00iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i00iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i00l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i00l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i00l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i00l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i00l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i00l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i00lii_dataout : STD_LOGIC; + SIGNAL wire_nl0i00lil_dataout : STD_LOGIC; + SIGNAL wire_nl0i00liO_dataout : STD_LOGIC; + SIGNAL wire_nl0i00lli_dataout : STD_LOGIC; + SIGNAL wire_nl0i00lll_dataout : STD_LOGIC; + SIGNAL wire_nl0i00llO_dataout : STD_LOGIC; + SIGNAL wire_nl0i00lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i00lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i00lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i00O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i00O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i00O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i00O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i00O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i00O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i00Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0i00Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0i00OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i00Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0i00Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0i00OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i00OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i00OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i00OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i010i_dataout : STD_LOGIC; + SIGNAL wire_nl0i010l_dataout : STD_LOGIC; + SIGNAL wire_nl0i010O_dataout : STD_LOGIC; + SIGNAL wire_nl0i011i_dataout : STD_LOGIC; + SIGNAL wire_nl0i011l_dataout : STD_LOGIC; + SIGNAL wire_nl0i011O_dataout : STD_LOGIC; + SIGNAL wire_nl0i01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i01il_dataout : STD_LOGIC; + SIGNAL wire_nl0i01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i01li_dataout : STD_LOGIC; + SIGNAL wire_nl0i01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i00i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i00l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i00O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i01i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i01l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0il_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0li_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i10i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i10l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i10O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i11i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i11l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i11O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1il_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1li_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iiii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iiil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iili_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iill_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0il0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0il0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0il0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0il1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0il1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0il1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ilii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ilil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iliO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0illi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0illl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0illO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOli_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l00i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l00l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l00O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l01i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l01l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0il_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0li_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l10i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l10l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l10O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l11i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l11l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l11O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1il_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1li_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0li0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0li0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0li0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0li1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0li1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0li1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0liii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0liil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0liiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lili_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lill_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0liOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0liOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0liOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0llii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0llil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lliO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0llli_dataout : STD_LOGIC; + SIGNAL wire_nl0i0llll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lllO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0llOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0llOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0llOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOli_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O00i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O00l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O00O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O01i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O01l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0il_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0li_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O10i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O10l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O10O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O11i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O11l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O11O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1il_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1li_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oili_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oill_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Olii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Olil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OliO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Olli_dataout : STD_LOGIC; + SIGNAL wire_nl0i0Olll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OllO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOii_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOil_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOli_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOll_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1000i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1000l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1000O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1001i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1001l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1001O_dataout : STD_LOGIC; + SIGNAL wire_nl0i100ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i100il_dataout : STD_LOGIC; + SIGNAL wire_nl0i100iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i100li_dataout : STD_LOGIC; + SIGNAL wire_nl0i100ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i100lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i100O_dataout : STD_LOGIC; + SIGNAL wire_nl0i100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i100OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1010i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1010l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1010O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1011i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1011l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1011O_dataout : STD_LOGIC; + SIGNAL wire_nl0i101ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i101il_dataout : STD_LOGIC; + SIGNAL wire_nl0i101iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i101li_dataout : STD_LOGIC; + SIGNAL wire_nl0i101ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i101lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i101OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i10i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i10i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i10i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i10i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i10i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i10iii_dataout : STD_LOGIC; + SIGNAL wire_nl0i10iil_dataout : STD_LOGIC; + SIGNAL wire_nl0i10iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10il_dataout : STD_LOGIC; + SIGNAL wire_nl0i10ili_dataout : STD_LOGIC; + SIGNAL wire_nl0i10ill_dataout : STD_LOGIC; + SIGNAL wire_nl0i10ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i10iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i10iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i10l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i10l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i10l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i10l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i10l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i10li_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lii_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lil_dataout : STD_LOGIC; + SIGNAL wire_nl0i10liO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lli_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lll_dataout : STD_LOGIC; + SIGNAL wire_nl0i10llO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i10lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i10O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i10O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i10O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i10O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i10O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i10Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0i10Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0i10OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i10Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0i10Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0i10OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i10OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i10OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i10OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1100i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1100l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1100O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1101i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1101l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1101O_dataout : STD_LOGIC; + SIGNAL wire_nl0i110ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i110il_dataout : STD_LOGIC; + SIGNAL wire_nl0i110iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i110li_dataout : STD_LOGIC; + SIGNAL wire_nl0i110ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i110lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i110OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1110i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1110l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1110O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1111i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1111l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1111O_dataout : STD_LOGIC; + SIGNAL wire_nl0i111ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i111il_dataout : STD_LOGIC; + SIGNAL wire_nl0i111iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i111li_dataout : STD_LOGIC; + SIGNAL wire_nl0i111ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i111lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i111OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i11i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i11i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i11i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i11i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i11i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i11iii_dataout : STD_LOGIC; + SIGNAL wire_nl0i11iil_dataout : STD_LOGIC; + SIGNAL wire_nl0i11iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11ili_dataout : STD_LOGIC; + SIGNAL wire_nl0i11ill_dataout : STD_LOGIC; + SIGNAL wire_nl0i11ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i11iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i11iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i11l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i11l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i11l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i11l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i11l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i11lii_dataout : STD_LOGIC; + SIGNAL wire_nl0i11lil_dataout : STD_LOGIC; + SIGNAL wire_nl0i11liO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11lli_dataout : STD_LOGIC; + SIGNAL wire_nl0i11lll_dataout : STD_LOGIC; + SIGNAL wire_nl0i11llO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i11lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i11lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i11O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i11O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i11O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i11O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i11O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i11Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0i11Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0i11OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0i11Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0i11OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i11OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i11OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i11OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i00i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i00l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i00O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i01i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i01l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0il_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0li_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i10i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i10l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i10O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i11i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i11l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i11O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1il_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1li_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iiii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iiil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iili_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iill_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1il0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1il0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1il0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1il1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1il1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1il1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ilii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ilil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iliO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0i1illi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1illl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1illO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOli_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l00i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l00l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l00O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l01i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l01l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0il_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0li_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l10i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l10l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l10O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l11i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l11l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l11O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1il_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1li_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1li1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lili_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lill_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lilO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1liOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1liOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1liOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lliO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llli_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lllO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1llOO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOil_w_lg_dataout52607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0i1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOiO_w_lg_dataout52605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0i1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOli_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOli_w_lg_dataout52603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0i1lOll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOll_w_lg_dataout52601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0i1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1lOlO_w_lg_dataout52600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0i1O00i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O00l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O01i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O01l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O01O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O0li_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O10i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O10l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O11l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O11O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0i1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0i1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0i1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0i1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0i1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0i1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0i1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii000i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii000l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii000O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii001i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii001l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii001O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00il_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00li_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ii00OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii010i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii010l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii010O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii011i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii011l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii011O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01il_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01li_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ii01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0il_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0li_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ii0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii100i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii100l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii100O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii101i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii101l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii101O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10il_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10li_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ii10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii110i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii110l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii110O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii111i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii111l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii111O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11il_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11li_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ii11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1iii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1il_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1li_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ii1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iii00i_dataout : STD_LOGIC; + SIGNAL wire_nl0iii00l_dataout : STD_LOGIC; + SIGNAL wire_nl0iii00O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii01i_dataout : STD_LOGIC; + SIGNAL wire_nl0iii01l_dataout : STD_LOGIC; + SIGNAL wire_nl0iii01O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0li_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iii10i_dataout : STD_LOGIC; + SIGNAL wire_nl0iii10l_dataout : STD_LOGIC; + SIGNAL wire_nl0iii10O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii11i_dataout : STD_LOGIC; + SIGNAL wire_nl0iii11l_dataout : STD_LOGIC; + SIGNAL wire_nl0iii11O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1il_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1li_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iii1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiiii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiiil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiili_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiill_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiil0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiil1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiili_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiliO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiill_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilli_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilll_dataout : STD_LOGIC; + SIGNAL wire_nl0iiillO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOli_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOll_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iil00i_dataout : STD_LOGIC; + SIGNAL wire_nl0iil00l_dataout : STD_LOGIC; + SIGNAL wire_nl0iil00O_dataout : STD_LOGIC; + SIGNAL wire_nl0iil01i_dataout : STD_LOGIC; + SIGNAL wire_nl0iil01l_dataout : STD_LOGIC; + SIGNAL wire_nl0iil01O_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0li_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iil0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iil10i_dataout : STD_LOGIC; + SIGNAL wire_nl0iil10l_dataout : STD_LOGIC; + SIGNAL wire_nl0iil10O_dataout : STD_LOGIC; + SIGNAL wire_nl0iil11i_dataout : STD_LOGIC; + SIGNAL wire_nl0iil11l_dataout : STD_LOGIC; + SIGNAL wire_nl0iil11O_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1il_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1li_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iil1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iili0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iili0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iili0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iili1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iili1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iili1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iilii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiliii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiliil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiliiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iilil_dataout : STD_LOGIC; + SIGNAL wire_nl0iilili_dataout : STD_LOGIC; + SIGNAL wire_nl0iilill_dataout : STD_LOGIC; + SIGNAL wire_nl0iililO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiliO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiliOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiliOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiliOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iill0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iill0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iill0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iill1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iill1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iill1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iilli_dataout : STD_LOGIC; + SIGNAL wire_nl0iillii_dataout : STD_LOGIC; + SIGNAL wire_nl0iillil_dataout : STD_LOGIC; + SIGNAL wire_nl0iilliO_dataout : STD_LOGIC; + SIGNAL wire_nl0iilll_dataout : STD_LOGIC; + SIGNAL wire_nl0iillli_dataout : STD_LOGIC; + SIGNAL wire_nl0iillll_dataout : STD_LOGIC; + SIGNAL wire_nl0iilllO_dataout : STD_LOGIC; + SIGNAL wire_nl0iillO_dataout : STD_LOGIC; + SIGNAL wire_nl0iillOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iillOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iillOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iilO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iilO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iilO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iilO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iilO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iilO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOii_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOli_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOll_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO10i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO10l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO10O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO11i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO11l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO11O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1il_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1li_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOiil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOili_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOill_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOlii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOlil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOllO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOii_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOli_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOll_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0il000i_dataout : STD_LOGIC; + SIGNAL wire_nl0il000l_dataout : STD_LOGIC; + SIGNAL wire_nl0il000O_dataout : STD_LOGIC; + SIGNAL wire_nl0il001i_dataout : STD_LOGIC; + SIGNAL wire_nl0il001l_dataout : STD_LOGIC; + SIGNAL wire_nl0il001O_dataout : STD_LOGIC; + SIGNAL wire_nl0il00i_dataout : STD_LOGIC; + SIGNAL wire_nl0il00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0il00l_dataout : STD_LOGIC; + SIGNAL wire_nl0il00li_dataout : STD_LOGIC; + SIGNAL wire_nl0il00ll_dataout : STD_LOGIC; + SIGNAL wire_nl0il00lO_dataout : STD_LOGIC; + SIGNAL wire_nl0il00O_dataout : STD_LOGIC; + SIGNAL wire_nl0il00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0il00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0il00OO_dataout : STD_LOGIC; + SIGNAL wire_nl0il010i_dataout : STD_LOGIC; + SIGNAL wire_nl0il010l_dataout : STD_LOGIC; + SIGNAL wire_nl0il010O_dataout : STD_LOGIC; + SIGNAL wire_nl0il011i_dataout : STD_LOGIC; + SIGNAL wire_nl0il011l_dataout : STD_LOGIC; + SIGNAL wire_nl0il011O_dataout : STD_LOGIC; + SIGNAL wire_nl0il01i_dataout : STD_LOGIC; + SIGNAL wire_nl0il01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il01il_dataout : STD_LOGIC; + SIGNAL wire_nl0il01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0il01l_dataout : STD_LOGIC; + SIGNAL wire_nl0il01li_dataout : STD_LOGIC; + SIGNAL wire_nl0il01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0il01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0il01O_dataout : STD_LOGIC; + SIGNAL wire_nl0il01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0il01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0il01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0il0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0il0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0il0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0il0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0il0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0il0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0il0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0il0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0il0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0il0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0il0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0il0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0il0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0il0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0il0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0il0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0il0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0il0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0il0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0il0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0il0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0il0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0il0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0il0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0il0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0il0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0il0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0il0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0il0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0il0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0il0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0il0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0il0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0il0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0il0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0il100i_dataout : STD_LOGIC; + SIGNAL wire_nl0il100l_dataout : STD_LOGIC; + SIGNAL wire_nl0il100O_dataout : STD_LOGIC; + SIGNAL wire_nl0il101i_dataout : STD_LOGIC; + SIGNAL wire_nl0il101l_dataout : STD_LOGIC; + SIGNAL wire_nl0il101O_dataout : STD_LOGIC; + SIGNAL wire_nl0il10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il10il_dataout : STD_LOGIC; + SIGNAL wire_nl0il10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0il10li_dataout : STD_LOGIC; + SIGNAL wire_nl0il10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0il10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0il10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0il10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0il10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0il110i_dataout : STD_LOGIC; + SIGNAL wire_nl0il110l_dataout : STD_LOGIC; + SIGNAL wire_nl0il110O_dataout : STD_LOGIC; + SIGNAL wire_nl0il111i_dataout : STD_LOGIC; + SIGNAL wire_nl0il111l_dataout : STD_LOGIC; + SIGNAL wire_nl0il111O_dataout : STD_LOGIC; + SIGNAL wire_nl0il11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0il11il_dataout : STD_LOGIC; + SIGNAL wire_nl0il11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0il11li_dataout : STD_LOGIC; + SIGNAL wire_nl0il11ll_dataout : STD_LOGIC; + SIGNAL wire_nl0il11lO_dataout : STD_LOGIC; + SIGNAL wire_nl0il11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0il11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0il11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0il1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0il1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0il1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0il1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0il1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0il1iii_dataout : STD_LOGIC; + SIGNAL wire_nl0il1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0il1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0il1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0il1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0il1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0il1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0il1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0il1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0il1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0il1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0il1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0il1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0il1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0il1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0il1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0il1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0il1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0il1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0il1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0il1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0il1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0il1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0il1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0il1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0il1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0il1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0il1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0il1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0il1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ili00l_dataout : STD_LOGIC; + SIGNAL wire_nl0ili00O_dataout : STD_LOGIC; + SIGNAL wire_nl0ili01l_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0il_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0li_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ili0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ili10i_dataout : STD_LOGIC; + SIGNAL wire_nl0ili10l_dataout : STD_LOGIC; + SIGNAL wire_nl0ili10O_dataout : STD_LOGIC; + SIGNAL wire_nl0ili11i_dataout : STD_LOGIC; + SIGNAL wire_nl0ili11l_dataout : STD_LOGIC; + SIGNAL wire_nl0ili11O_dataout : STD_LOGIC; + SIGNAL wire_nl0ili1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ili1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ili1il_dataout : STD_LOGIC; + SIGNAL wire_nl0ili1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ili1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ili1li_dataout : STD_LOGIC; + SIGNAL wire_nl0ili1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iliiii_dataout : STD_LOGIC; + SIGNAL wire_nl0iliiil_dataout : STD_LOGIC; + SIGNAL wire_nl0iliiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iliili_dataout : STD_LOGIC; + SIGNAL wire_nl0iliill_dataout : STD_LOGIC; + SIGNAL wire_nl0iliilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iliiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iliiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iliiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilil0O_w_lg_dataout52199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ilil1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ililii_dataout : STD_LOGIC; + SIGNAL wire_nl0ililii_w_lg_dataout52201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ililil_dataout : STD_LOGIC; + SIGNAL wire_nl0ililil_w_lg_dataout52203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ililiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ililli_dataout : STD_LOGIC; + SIGNAL wire_nl0ililll_dataout : STD_LOGIC; + SIGNAL wire_nl0ilillO_dataout : STD_LOGIC; + SIGNAL wire_nl0ililOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ililOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ililOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iliO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iliO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iliO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iliO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iliO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iliO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOii_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOli_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOll_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iliOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ill10i_dataout : STD_LOGIC; + SIGNAL wire_nl0ill10l_dataout : STD_LOGIC; + SIGNAL wire_nl0ill10O_dataout : STD_LOGIC; + SIGNAL wire_nl0ill11i_dataout : STD_LOGIC; + SIGNAL wire_nl0ill11l_dataout : STD_LOGIC; + SIGNAL wire_nl0ill11O_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1il_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1li_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ill1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0illi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0illi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0illi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0illi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0illi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0illi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0illiii_dataout : STD_LOGIC; + SIGNAL wire_nl0illiil_dataout : STD_LOGIC; + SIGNAL wire_nl0illiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0illiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0illl1i_dataout : STD_LOGIC; + SIGNAL wire_nl0illl1l_dataout : STD_LOGIC; + SIGNAL wire_nl0illl1O_dataout : STD_LOGIC; + SIGNAL wire_nl0illlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0illlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0illlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0illO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0illO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0illO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0illO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0illO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0illO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0illOii_dataout : STD_LOGIC; + SIGNAL wire_nl0illOil_dataout : STD_LOGIC; + SIGNAL wire_nl0illOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0illOli_dataout : STD_LOGIC; + SIGNAL wire_nl0illOll_dataout : STD_LOGIC; + SIGNAL wire_nl0illOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0illOO_dataout : STD_LOGIC; + SIGNAL wire_nl0illOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0illOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0illOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO10i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO10l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO10O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO11i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO11l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO11O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1il_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1li_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ilO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOi0i_w_lg_dataout52528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ilOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOi0l_w_lg_dataout52526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ilOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOi0O_w_lg_dataout52524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ilOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOii_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOiii_w_lg_dataout52522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ilOiil_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOiil_w_lg_dataout52520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ilOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOiiO_w_lg_dataout52518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0ilOil_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOli_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOll_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOii_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOil_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOli_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOll_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0ilOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO000i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO001i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO001l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO001O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iO010i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO010l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO010O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO011i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO011l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO011O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01li_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iO01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO100i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO100l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO100O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO101i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO101l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO101O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10li_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iO10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO110i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO110l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO110O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO111i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO111l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO111O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11li_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iO11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1iii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1il_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1li_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi00i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi00l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi00O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi01i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi01l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi01O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0li_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi10l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi10O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1il_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1li_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOiiii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOiiil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl00i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl00l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl00O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl01i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl01l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl01O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl10l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl10O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1il_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1li_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOli0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOli0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOli0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOli1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOli1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOli1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOliii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOliil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOliiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlili_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlill_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOliOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOliOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOliOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlliO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllli_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlllO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOllOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOli_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO10i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO10l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO10O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO11i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO11l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO11O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1il_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1li_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0iOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOiil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOil_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOili_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOill_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOilO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOli_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOll_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0iOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0000i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0000l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0000O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0001i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0001l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0001O_dataout : STD_LOGIC; + SIGNAL wire_nl0l000i_dataout : STD_LOGIC; + SIGNAL wire_nl0l000ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l000l_dataout : STD_LOGIC; + SIGNAL wire_nl0l000lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l000O_dataout : STD_LOGIC; + SIGNAL wire_nl0l000Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l001i_dataout : STD_LOGIC; + SIGNAL wire_nl0l001l_dataout : STD_LOGIC; + SIGNAL wire_nl0l001O_dataout : STD_LOGIC; + SIGNAL wire_nl0l001OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l00i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l00i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l00i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l00i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l00iii_dataout : STD_LOGIC; + SIGNAL wire_nl0l00iil_dataout : STD_LOGIC; + SIGNAL wire_nl0l00il_dataout : STD_LOGIC; + SIGNAL wire_nl0l00ili_dataout : STD_LOGIC; + SIGNAL wire_nl0l00ill_dataout : STD_LOGIC; + SIGNAL wire_nl0l00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l00l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l00l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l00l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l00li_dataout : STD_LOGIC; + SIGNAL wire_nl0l00lii_dataout : STD_LOGIC; + SIGNAL wire_nl0l00lil_dataout : STD_LOGIC; + SIGNAL wire_nl0l00liO_dataout : STD_LOGIC; + SIGNAL wire_nl0l00lli_dataout : STD_LOGIC; + SIGNAL wire_nl0l00lll_dataout : STD_LOGIC; + SIGNAL wire_nl0l00lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l00lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l00lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l00O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l010l_dataout : STD_LOGIC; + SIGNAL wire_nl0l010O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0110i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0110l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0110O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0111i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0111i_w_lg_dataout52336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0111l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0111l_w52414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0111l_w_lg_w_lg_w_lg_dataout52335w52337w52339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0111l_w_lg_w_lg_dataout52335w52337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0111l_w_lg_dataout52416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0111l_w_lg_dataout52335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0111O_dataout : STD_LOGIC; + SIGNAL wire_nl0l011ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l011il_dataout : STD_LOGIC; + SIGNAL wire_nl0l011iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l011li_dataout : STD_LOGIC; + SIGNAL wire_nl0l011ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l011lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l011Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l011Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l011OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l01i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l01i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l01i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l01i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l01i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l01i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l01iii_dataout : STD_LOGIC; + SIGNAL wire_nl0l01iil_dataout : STD_LOGIC; + SIGNAL wire_nl0l01iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l01il_dataout : STD_LOGIC; + SIGNAL wire_nl0l01ili_dataout : STD_LOGIC; + SIGNAL wire_nl0l01ill_dataout : STD_LOGIC; + SIGNAL wire_nl0l01ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l01iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l01iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l01l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l01li_dataout : STD_LOGIC; + SIGNAL wire_nl0l01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l01O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l01O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l01O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l01Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0l01Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0l01OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l01Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0l01Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0l01OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i10l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i10O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i1il_dataout : STD_LOGIC; + SIGNAL wire_nl0l0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iiii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iiil_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iili_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iill_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0il0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0il0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0il0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0il1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0il1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ilii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ilil_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iliO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0l0illi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0illl_dataout : STD_LOGIC; + SIGNAL wire_nl0l0illO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOil_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOli_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOll_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l00i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l00l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l01i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l01l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l01O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l0Ol_w_lg_dataout46163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l0OO_w_lg_dataout46242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0l10i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l10l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l10O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l11i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l11l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l11O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1il_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1li_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0li0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0li0i_w_lg_dataout46240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0li0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0li0O_w_lg_dataout46239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0li1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0li1l_w_lg_dataout46241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0liil_dataout : STD_LOGIC; + SIGNAL wire_nl0l0liil_w_lg_dataout46238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Olii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Olil_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OliO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Olli_dataout : STD_LOGIC; + SIGNAL wire_nl0l0Olll_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OllO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOii_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOil_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOli_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOll_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1000i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1000l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1000O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1001i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1001l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1001O_dataout : STD_LOGIC; + SIGNAL wire_nl0l100i_dataout : STD_LOGIC; + SIGNAL wire_nl0l100ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l100il_dataout : STD_LOGIC; + SIGNAL wire_nl0l100iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l100l_dataout : STD_LOGIC; + SIGNAL wire_nl0l100li_dataout : STD_LOGIC; + SIGNAL wire_nl0l100ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l100lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l100O_dataout : STD_LOGIC; + SIGNAL wire_nl0l100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l100OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l101i_dataout : STD_LOGIC; + SIGNAL wire_nl0l101iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l101l_dataout : STD_LOGIC; + SIGNAL wire_nl0l101li_dataout : STD_LOGIC; + SIGNAL wire_nl0l101ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l101lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l101O_dataout : STD_LOGIC; + SIGNAL wire_nl0l101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l101OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l10i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l10i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l10i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l10i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l10i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l10iii_dataout : STD_LOGIC; + SIGNAL wire_nl0l10iil_dataout : STD_LOGIC; + SIGNAL wire_nl0l10iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10il_dataout : STD_LOGIC; + SIGNAL wire_nl0l10ili_dataout : STD_LOGIC; + SIGNAL wire_nl0l10ill_dataout : STD_LOGIC; + SIGNAL wire_nl0l10ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l10iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l10iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l10l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l10l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l10l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l10l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l10l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l10li_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lii_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lil_dataout : STD_LOGIC; + SIGNAL wire_nl0l10liO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lli_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lll_dataout : STD_LOGIC; + SIGNAL wire_nl0l10llO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l10lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l10O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l10O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l10O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l10O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l10O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l10Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0l10Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0l10OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l10Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0l10Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0l10OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l10OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l10OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l10OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l110i_dataout : STD_LOGIC; + SIGNAL wire_nl0l110l_dataout : STD_LOGIC; + SIGNAL wire_nl0l110O_dataout : STD_LOGIC; + SIGNAL wire_nl0l111i_dataout : STD_LOGIC; + SIGNAL wire_nl0l111l_dataout : STD_LOGIC; + SIGNAL wire_nl0l111O_dataout : STD_LOGIC; + SIGNAL wire_nl0l11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l11il_dataout : STD_LOGIC; + SIGNAL wire_nl0l11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l11li_dataout : STD_LOGIC; + SIGNAL wire_nl0l11ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l11lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i00i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i00l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i00O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i01i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i01l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i01O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0il_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0li_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i10i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i10l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i10O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i11i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i11l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i11O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1il_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1li_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iiii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iiil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iili_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iill_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1il0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1il0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1il0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1il1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1il1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1il1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ilii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ilil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iliO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0l1illi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1illl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1illO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOli_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l00i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l00l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l00O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l01i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l01l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l01O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0il_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0li_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l10i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l10l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l10O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l11i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l11l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l11O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1il_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1li0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1li0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1li0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1li1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1li1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1li1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1liii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1liil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1liiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lili_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lill_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1liOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1liOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1liOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lliO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llli_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lllO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1llOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lO1l_w_lg_dataout48198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lO1O_w_lg_w_lg_dataout48195w48196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1lO1O_w_lg_dataout48199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1lO1O_w_lg_dataout48195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOli_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O01i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O01l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O01O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O0OO_w_lg_dataout52093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1O10i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O10l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O10O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O11i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O11l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O11O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1il_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1li_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0l1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oi1i_w_lg_dataout52091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oili_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oill_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OilO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Olii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Olil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OliO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Olli_dataout : STD_LOGIC; + SIGNAL wire_nl0l1Olll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OllO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOii_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOil_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOil_w_lg_dataout52356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOiO_w_lg_dataout52354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOli_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOli_w_lg_dataout52352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOll_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOll_w_lg_dataout52350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOlO_w52359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w52366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w52374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w52381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52384w52391w52395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52399w52402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52405w52408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_dataout52384w52391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_dataout52384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_dataout52398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOlO_w_lg_dataout52349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOOi_w_lg_dataout52411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOOl_w_lg_dataout52340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0l1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0l1OOOO_w_lg_dataout52338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0li000i_dataout : STD_LOGIC; + SIGNAL wire_nl0li000l_dataout : STD_LOGIC; + SIGNAL wire_nl0li000O_dataout : STD_LOGIC; + SIGNAL wire_nl0li001i_dataout : STD_LOGIC; + SIGNAL wire_nl0li001l_dataout : STD_LOGIC; + SIGNAL wire_nl0li001O_dataout : STD_LOGIC; + SIGNAL wire_nl0li00i_dataout : STD_LOGIC; + SIGNAL wire_nl0li00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0li00il_dataout : STD_LOGIC; + SIGNAL wire_nl0li00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0li00l_dataout : STD_LOGIC; + SIGNAL wire_nl0li00li_dataout : STD_LOGIC; + SIGNAL wire_nl0li00ll_dataout : STD_LOGIC; + SIGNAL wire_nl0li00lO_dataout : STD_LOGIC; + SIGNAL wire_nl0li00O_dataout : STD_LOGIC; + SIGNAL wire_nl0li00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0li00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0li00OO_dataout : STD_LOGIC; + SIGNAL wire_nl0li010i_dataout : STD_LOGIC; + SIGNAL wire_nl0li010l_dataout : STD_LOGIC; + SIGNAL wire_nl0li010O_dataout : STD_LOGIC; + SIGNAL wire_nl0li011i_dataout : STD_LOGIC; + SIGNAL wire_nl0li011l_dataout : STD_LOGIC; + SIGNAL wire_nl0li011O_dataout : STD_LOGIC; + SIGNAL wire_nl0li01i_dataout : STD_LOGIC; + SIGNAL wire_nl0li01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0li01il_dataout : STD_LOGIC; + SIGNAL wire_nl0li01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0li01l_dataout : STD_LOGIC; + SIGNAL wire_nl0li01O_dataout : STD_LOGIC; + SIGNAL wire_nl0li01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0li0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0li0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0li0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0li0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0li0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0li0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0li0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0li0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0li0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0il_dataout : STD_LOGIC; + SIGNAL wire_nl0li0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0li0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0li0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0li0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0li0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0li0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0li0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0li0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0li0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0li0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0li0li_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0li0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0li0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0li0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0li0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0li0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0li0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0li0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0li0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0li0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0li0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0li0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0li0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0li0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0li0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0li0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0li0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0li0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0li0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0li100i_dataout : STD_LOGIC; + SIGNAL wire_nl0li100l_dataout : STD_LOGIC; + SIGNAL wire_nl0li100O_dataout : STD_LOGIC; + SIGNAL wire_nl0li101i_dataout : STD_LOGIC; + SIGNAL wire_nl0li101l_dataout : STD_LOGIC; + SIGNAL wire_nl0li101O_dataout : STD_LOGIC; + SIGNAL wire_nl0li10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0li10il_dataout : STD_LOGIC; + SIGNAL wire_nl0li10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0li10li_dataout : STD_LOGIC; + SIGNAL wire_nl0li10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0li10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0li10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0li10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0li10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0li110i_dataout : STD_LOGIC; + SIGNAL wire_nl0li110l_dataout : STD_LOGIC; + SIGNAL wire_nl0li110O_dataout : STD_LOGIC; + SIGNAL wire_nl0li111i_dataout : STD_LOGIC; + SIGNAL wire_nl0li111l_dataout : STD_LOGIC; + SIGNAL wire_nl0li111O_dataout : STD_LOGIC; + SIGNAL wire_nl0li11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0li11il_dataout : STD_LOGIC; + SIGNAL wire_nl0li11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0li11li_dataout : STD_LOGIC; + SIGNAL wire_nl0li11ll_dataout : STD_LOGIC; + SIGNAL wire_nl0li11lO_dataout : STD_LOGIC; + SIGNAL wire_nl0li11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0li11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0li11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0li1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0li1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0li1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0li1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0li1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0li1iii_dataout : STD_LOGIC; + SIGNAL wire_nl0li1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0li1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0li1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0li1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0li1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0li1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0li1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0li1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0li1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0li1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0li1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0li1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0li1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0li1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0li1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0li1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0li1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0li1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0li1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0li1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0li1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0li1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0li1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0li1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0li1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0li1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0li1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0li1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0li1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0li1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0li1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0li1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lii00i_dataout : STD_LOGIC; + SIGNAL wire_nl0lii00l_dataout : STD_LOGIC; + SIGNAL wire_nl0lii00O_dataout : STD_LOGIC; + SIGNAL wire_nl0lii01i_dataout : STD_LOGIC; + SIGNAL wire_nl0lii01l_dataout : STD_LOGIC; + SIGNAL wire_nl0lii01O_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0il_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0li_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lii11i_dataout : STD_LOGIC; + SIGNAL wire_nl0lii11l_dataout : STD_LOGIC; + SIGNAL wire_nl0lii11O_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1il_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1li_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lii1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0liii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0liii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0liii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0liii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0liii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0liii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0liiii_dataout : STD_LOGIC; + SIGNAL wire_nl0liiiii_dataout : STD_LOGIC; + SIGNAL wire_nl0liiiil_dataout : STD_LOGIC; + SIGNAL wire_nl0liiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0liiil_dataout : STD_LOGIC; + SIGNAL wire_nl0liiili_dataout : STD_LOGIC; + SIGNAL wire_nl0liiill_dataout : STD_LOGIC; + SIGNAL wire_nl0liiilO_dataout : STD_LOGIC; + SIGNAL wire_nl0liiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0liiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0liiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0liiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0liil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0liil0l_dataout : STD_LOGIC; + SIGNAL wire_nl0liil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0liil1i_dataout : STD_LOGIC; + SIGNAL wire_nl0liil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0liil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0liili_dataout : STD_LOGIC; + SIGNAL wire_nl0liilii_dataout : STD_LOGIC; + SIGNAL wire_nl0liilil_dataout : STD_LOGIC; + SIGNAL wire_nl0liiliO_dataout : STD_LOGIC; + SIGNAL wire_nl0liill_dataout : STD_LOGIC; + SIGNAL wire_nl0liilli_dataout : STD_LOGIC; + SIGNAL wire_nl0liilll_dataout : STD_LOGIC; + SIGNAL wire_nl0liillO_dataout : STD_LOGIC; + SIGNAL wire_nl0liilO_dataout : STD_LOGIC; + SIGNAL wire_nl0liilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0liilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0liilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0liiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0liiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0liiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0liiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0liiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0liiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0liiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0liiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0liiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0liiOli_dataout : STD_LOGIC; + SIGNAL wire_nl0liiOll_dataout : STD_LOGIC; + SIGNAL wire_nl0liiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0liiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lil01i_dataout : STD_LOGIC; + SIGNAL wire_nl0lil01i_w_lg_dataout46179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lil01l_dataout : STD_LOGIC; + SIGNAL wire_nl0lil01l_w_lg_dataout46178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lil01O_dataout : STD_LOGIC; + SIGNAL wire_nl0lil01O_w_lg_dataout46177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lil0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lil0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lil0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lil10i_dataout : STD_LOGIC; + SIGNAL wire_nl0lil10l_dataout : STD_LOGIC; + SIGNAL wire_nl0lil10O_dataout : STD_LOGIC; + SIGNAL wire_nl0lil11O_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1ll_w_lg_dataout46184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lil1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1lO_w_lg_dataout46183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1Oi_w_lg_dataout46182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1Ol_w_lg_dataout46181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lil1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lil1OO_w_lg_dataout46180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lili0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lili0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lili0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lili1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lili1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lili1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lilii_dataout : STD_LOGIC; + SIGNAL wire_nl0liliii_dataout : STD_LOGIC; + SIGNAL wire_nl0liliil_dataout : STD_LOGIC; + SIGNAL wire_nl0liliiO_dataout : STD_LOGIC; + SIGNAL wire_nl0lilil_dataout : STD_LOGIC; + SIGNAL wire_nl0lilili_dataout : STD_LOGIC; + SIGNAL wire_nl0lilill_dataout : STD_LOGIC; + SIGNAL wire_nl0lililO_dataout : STD_LOGIC; + SIGNAL wire_nl0liliO_dataout : STD_LOGIC; + SIGNAL wire_nl0lillii_dataout : STD_LOGIC; + SIGNAL wire_nl0lillil_dataout : STD_LOGIC; + SIGNAL wire_nl0lilliO_dataout : STD_LOGIC; + SIGNAL wire_nl0lillli_dataout : STD_LOGIC; + SIGNAL wire_nl0lillll_dataout : STD_LOGIC; + SIGNAL wire_nl0lilllO_dataout : STD_LOGIC; + SIGNAL wire_nl0lillOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lillOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lillOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lilO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lilO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lilO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lilO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lilO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lilO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lilOii_dataout : STD_LOGIC; + SIGNAL wire_nl0ll00i_dataout : STD_LOGIC; + SIGNAL wire_nl0ll00l_dataout : STD_LOGIC; + SIGNAL wire_nl0ll00O_dataout : STD_LOGIC; + SIGNAL wire_nl0ll01i_dataout : STD_LOGIC; + SIGNAL wire_nl0ll01l_dataout : STD_LOGIC; + SIGNAL wire_nl0ll01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ll01O_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0il_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0li_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ll0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll10i_dataout : STD_LOGIC; + SIGNAL wire_nl0ll10l_dataout : STD_LOGIC; + SIGNAL wire_nl0ll10O_dataout : STD_LOGIC; + SIGNAL wire_nl0ll11O_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1il_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1li_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0ll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lli0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lli0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lli0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lli1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lli1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lli1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lliii_dataout : STD_LOGIC; + SIGNAL wire_nl0lliil_dataout : STD_LOGIC; + SIGNAL wire_nl0lliili_dataout : STD_LOGIC; + SIGNAL wire_nl0lliilO_dataout : STD_LOGIC; + SIGNAL wire_nl0lliilO_w_lg_dataout45745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lliiO_dataout : STD_LOGIC; + SIGNAL wire_nl0lliiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lliiOi_w_lg_dataout45744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lliiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lliiOl_w_lg_dataout45743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0lliiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lliiOO_w_lg_dataout45742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0llili_dataout : STD_LOGIC; + SIGNAL wire_nl0llill_dataout : STD_LOGIC; + SIGNAL wire_nl0llilO_dataout : STD_LOGIC; + SIGNAL wire_nl0lliOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lliOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lliOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lllii_dataout : STD_LOGIC; + SIGNAL wire_nl0lllil_dataout : STD_LOGIC; + SIGNAL wire_nl0llliO_dataout : STD_LOGIC; + SIGNAL wire_nl0lllli_dataout : STD_LOGIC; + SIGNAL wire_nl0lllll_dataout : STD_LOGIC; + SIGNAL wire_nl0llllO_dataout : STD_LOGIC; + SIGNAL wire_nl0lllOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lllOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lllOO_dataout : STD_LOGIC; + SIGNAL wire_nl0llO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0llO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0llO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0llO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0llO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0llO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0llO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0llO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0llO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0llO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0llO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0llOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0llOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0llOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0llOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0llOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0llOii_dataout : STD_LOGIC; + SIGNAL wire_nl0llOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0llOiil_dataout : STD_LOGIC; + SIGNAL wire_nl0llOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOil_dataout : STD_LOGIC; + SIGNAL wire_nl0llOili_dataout : STD_LOGIC; + SIGNAL wire_nl0llOill_dataout : STD_LOGIC; + SIGNAL wire_nl0llOilO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0llOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0llOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0llOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0llOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0llOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl0llOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl0llOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl0llOli_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlii_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlil_dataout : STD_LOGIC; + SIGNAL wire_nl0llOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOll_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0llOllO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0llOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0llOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0llOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0llOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0llOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0llOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOii_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOil_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOli_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOll_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0llOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO000i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO000l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO000O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO001i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO001l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO001O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00il_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00li_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lO00OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO010i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO010l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO010O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO011i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO011l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO011O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01il_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01li_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lO01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lO100i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO100l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO100O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO101i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO101l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO101O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10il_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10li_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lO10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO110i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO110l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO110O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO111i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO111l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO111O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11il_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11li_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lO11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1il_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1li_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOili_dataout : STD_LOGIC; + SIGNAL wire_nl0lOill_dataout : STD_LOGIC; + SIGNAL wire_nl0lOilO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl0lOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl0lOlii_dataout : STD_LOGIC; + SIGNAL wire_nl0lOlil_dataout : STD_LOGIC; + SIGNAL wire_nl0lOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0lOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0lOllO_dataout : STD_LOGIC; + SIGNAL wire_nl0lOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0lOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0lOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0lOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O000i_dataout : STD_LOGIC; + SIGNAL wire_nl0O000l_dataout : STD_LOGIC; + SIGNAL wire_nl0O000O_dataout : STD_LOGIC; + SIGNAL wire_nl0O001i_dataout : STD_LOGIC; + SIGNAL wire_nl0O001l_dataout : STD_LOGIC; + SIGNAL wire_nl0O001O_dataout : STD_LOGIC; + SIGNAL wire_nl0O00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O00il_dataout : STD_LOGIC; + SIGNAL wire_nl0O00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O00li_dataout : STD_LOGIC; + SIGNAL wire_nl0O00ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O00lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O00OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O010i_dataout : STD_LOGIC; + SIGNAL wire_nl0O010l_dataout : STD_LOGIC; + SIGNAL wire_nl0O010O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0110i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0110l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0110O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0111i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0111l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0111O_dataout : STD_LOGIC; + SIGNAL wire_nl0O011i_dataout : STD_LOGIC; + SIGNAL wire_nl0O011ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O011il_dataout : STD_LOGIC; + SIGNAL wire_nl0O011iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O011l_dataout : STD_LOGIC; + SIGNAL wire_nl0O011li_dataout : STD_LOGIC; + SIGNAL wire_nl0O011ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O011O_dataout : STD_LOGIC; + SIGNAL wire_nl0O01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O01il_dataout : STD_LOGIC; + SIGNAL wire_nl0O01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O01li_dataout : STD_LOGIC; + SIGNAL wire_nl0O01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0O0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0O0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0O0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0O0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0O0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0O0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0llOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lO0i_w_lg_dataout45973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lO0l_w_lg_dataout45972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lO1l_w_lg_dataout45975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lO1O_w_lg_dataout45974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Ol0O_w_lg_dataout49705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Olii_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Olii_w_lg_dataout49703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0Olil_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Olil_w_lg_dataout49701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OliO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OliO_w_lg_dataout49699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Olli_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Olli_w_lg_dataout49697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0Olll_dataout : STD_LOGIC; + SIGNAL wire_nl0O0Olll_w_lg_dataout49695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OllO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OllO_w_lg_dataout49693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OlOi_w_lg_dataout49691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OlOl_w_lg_dataout49689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OlOO_w_lg_dataout49687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OO0i_w_lg_dataout49679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OO0l_w_lg_dataout49677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OO0O_w_lg_dataout49675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OO1i_w_lg_dataout49685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OO1l_w_lg_dataout49683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OO1O_w_lg_dataout49681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOii_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOii_w_lg_dataout49673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOil_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOil_w_lg_dataout49671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOiO_w_lg_dataout49669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOli_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOli_w_lg_dataout49667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOll_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOll_w_lg_dataout49665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOlO_w_lg_dataout49663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOOi_w_lg_dataout49661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOOl_w_lg_dataout49659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O0OOOO_w_lg_dataout49657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O1000i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1000i_w_lg_dataout50573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O1000l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1000l_w_lg_dataout50571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O1000O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1000O_w_lg_dataout50569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O1001i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1001i_w_lg_dataout50579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O1001l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1001l_w_lg_dataout50577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O1001O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1001O_w_lg_dataout50575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O100ii_w_lg_dataout50567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100il_dataout : STD_LOGIC; + SIGNAL wire_nl0O100il_w_lg_dataout50565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O100iO_w_lg_dataout50563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100li_dataout : STD_LOGIC; + SIGNAL wire_nl0O100li_w_lg_dataout50561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O100ll_w_lg_dataout50559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O100lO_w_lg_dataout50557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O100Oi_w_lg_dataout50555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O100Ol_w_lg_dataout50553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O100OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O100OO_w_lg_dataout50551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O101ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O101ll_w_lg_dataout50589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O101lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O101lO_w_lg_dataout50587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O101Oi_w_lg_dataout50585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O101Ol_w_lg_dataout50583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O101OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O101OO_w_lg_dataout50581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O10i0i_w_lg_dataout50543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O10i0l_w_lg_dataout50541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O10i0O_w_lg_dataout50539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O10i1i_w_lg_dataout50549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O10i1l_w_lg_dataout50547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O10i1O_w_lg_dataout50545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10iii_dataout : STD_LOGIC; + SIGNAL wire_nl0O10iii_w_lg_dataout50537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10iil_dataout : STD_LOGIC; + SIGNAL wire_nl0O10iil_w_lg_dataout50535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O10iiO_w_lg_dataout50533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10ili_dataout : STD_LOGIC; + SIGNAL wire_nl0O10ili_w_lg_dataout50531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10ill_dataout : STD_LOGIC; + SIGNAL wire_nl0O10ill_w_lg_dataout50529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0O10ilO_w_lg_dataout50528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O10iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O10iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O10iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O10l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O10l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O10l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O10l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O10l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O10l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O10lii_dataout : STD_LOGIC; + SIGNAL wire_nl0O10lil_dataout : STD_LOGIC; + SIGNAL wire_nl0O10liO_dataout : STD_LOGIC; + SIGNAL wire_nl0O10lli_dataout : STD_LOGIC; + SIGNAL wire_nl0O10lll_dataout : STD_LOGIC; + SIGNAL wire_nl0O10llO_dataout : STD_LOGIC; + SIGNAL wire_nl0O10lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O10lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O10lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O10O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O10O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O10O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O10O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O10O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O10O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O10Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0O10Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0O10OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O10Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1100i_dataout : STD_LOGIC; + SIGNAL wire_nl0O110ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O110ii_w_lg_dataout45855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O110il_dataout : STD_LOGIC; + SIGNAL wire_nl0O110il_w_lg_dataout45854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O110iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O110iO_w_lg_dataout45853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O110li_dataout : STD_LOGIC; + SIGNAL wire_nl0O110li_w_lg_dataout45852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0O1illi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1illl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1illO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l00i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l00l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l00O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l01i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l01l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l01O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0il_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0li_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l10i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l10l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l10O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l11i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l11l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l11O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1il_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1li_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1li0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1li0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1li0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1li1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1li1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1li1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1liii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1liil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1liiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lili_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lill_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lilO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1liO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1liOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1liOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1liOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lliO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lllO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1llOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O00i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O00l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O00O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O01i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O01l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O01O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0il_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0li_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O10i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O10l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O10O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O11O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1il_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1li_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0O1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oili_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oill_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OilO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Olii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Olil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OliO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Olli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1Olll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OllO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOii_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOil_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOli_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOll_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0O1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi000l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi000O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi00OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi01i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi01l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi01O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi100i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi100l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi100O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi101i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi101l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi101O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi110i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi110i_w_lg_dataout49649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi110l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi110l_w_lg_dataout49647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi110O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi110O_w_lg_dataout49645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi111i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi111i_w_lg_dataout49655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi111l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi111l_w_lg_dataout49653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi111O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi111O_w_lg_dataout49651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi11i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11ii_w_lg_dataout49644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Oi11il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii00i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii00l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii00O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii01i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii01l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii01O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii10i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii10l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii10O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii11i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii11l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii11O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oii1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiiiii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiiiil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiiili_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiil0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiil1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiilii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiilil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiliO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiilli_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiilll_dataout : STD_LOGIC; + SIGNAL wire_nl0OiillO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OiilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OiilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil00i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil00l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil00O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil01i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil01l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil01O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil10i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil10l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil10O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil11i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil11l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil11O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oil1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oili0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oili0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oili0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oili1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oili1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oili1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiliii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oiliil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiliiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oilili_dataout : STD_LOGIC; + SIGNAL wire_nl0Oilill_dataout : STD_LOGIC; + SIGNAL wire_nl0OililO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiliOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OiliOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OiliOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oill0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oill0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oill0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oill1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oill1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oill1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOili_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOill_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOllO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol10l_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol10O_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol11i_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1li_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli00i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli00l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli00O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli01i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli01l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli01O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli10i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli10l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli10O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli11i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli11l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli11O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oli1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Olii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Olii1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oliiii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oliiil_dataout : STD_LOGIC; + SIGNAL wire_nl0OliiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oliili_dataout : STD_LOGIC; + SIGNAL wire_nl0Oliill_dataout : STD_LOGIC; + SIGNAL wire_nl0OliilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OliiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OliiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OliiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Olil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olil0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Olil1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Olilii_dataout : STD_LOGIC; + SIGNAL wire_nl0Olilil_dataout : STD_LOGIC; + SIGNAL wire_nl0OliliO_dataout : STD_LOGIC; + SIGNAL wire_nl0Olill_dataout : STD_LOGIC; + SIGNAL wire_nl0Olilli_dataout : STD_LOGIC; + SIGNAL wire_nl0Olilll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlillO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OlilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OlilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OliO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OliO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OliO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OliO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OliO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OliO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OliOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll00i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll00l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll00O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll01i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll01l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll01O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll10i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll10l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll10O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll11i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll11l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll11O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1il_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1li_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0Oll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0Olli0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olli0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olli0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Olli1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olli1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olli1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Ollii_dataout : STD_LOGIC; + SIGNAL wire_nl0Olliii_dataout : STD_LOGIC; + SIGNAL wire_nl0Olliil_dataout : STD_LOGIC; + SIGNAL wire_nl0OlliiO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ollil_dataout : STD_LOGIC; + SIGNAL wire_nl0Ollili_dataout : STD_LOGIC; + SIGNAL wire_nl0Ollill_dataout : STD_LOGIC; + SIGNAL wire_nl0OllilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlliO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlliOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OlliOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OlliOO_dataout : STD_LOGIC; + SIGNAL wire_nl0Olll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0Olll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0Olll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0Olll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0Ollli_dataout : STD_LOGIC; + SIGNAL wire_nl0Olllii_dataout : STD_LOGIC; + SIGNAL wire_nl0Olllil_dataout : STD_LOGIC; + SIGNAL wire_nl0OllliO_dataout : STD_LOGIC; + SIGNAL wire_nl0Ollll_dataout : STD_LOGIC; + SIGNAL wire_nl0Olllli_dataout : STD_LOGIC; + SIGNAL wire_nl0Olllll_dataout : STD_LOGIC; + SIGNAL wire_nl0OllllO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlllO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlllOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OlllOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OlllOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OllO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OllO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OllO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OllO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OllO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OllO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OllOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO10i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO10l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO10O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO11l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO11O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1il_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1li_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOiil_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOili_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOill_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlii_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlil_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOllO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OlOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO000i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO000l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO000O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO001i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO001l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO001O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00il_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00li_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO00OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO010i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO010l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO010O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO011i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO011l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO011O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01il_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01li_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO01OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0iii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0iil_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0il_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0ili_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0ill_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lil_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0liO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lli_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lll_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0llO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO100O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO101i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO101l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10il_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10li_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO10OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO110i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO110l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO110O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO111i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO111l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO111O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11il_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11li_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO11OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1iii_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1iil_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1ili_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1ill_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOii0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOii0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOii0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOii1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOii1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiiii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiiil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiili_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiill_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOil0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOil0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOil0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOil1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOil1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOil1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOili_dataout : STD_LOGIC; + SIGNAL wire_nl0OOilii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOilil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiliO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOilli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOilll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOillO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOilOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOilOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOilOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl00i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl00l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl00O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl01i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl01l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl01O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl0il_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl0li_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl10i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl10l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl10O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl11i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl11l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl11O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1il_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1li_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOli0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOli0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOli1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOli1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlili_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlill_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOliOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOliOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOliOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOll0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOll0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOll0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOll1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOll1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOll1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlliO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlllO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOllOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO0li_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOiii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOiil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOili_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOill_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOilO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOlii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOlil_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOliO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOlli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOlll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOii_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOli_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOll_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl0OOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl100000i_dataout : STD_LOGIC; + SIGNAL wire_nl100000l_dataout : STD_LOGIC; + SIGNAL wire_nl100000O_dataout : STD_LOGIC; + SIGNAL wire_nl100001i_dataout : STD_LOGIC; + SIGNAL wire_nl100001l_dataout : STD_LOGIC; + SIGNAL wire_nl100001O_dataout : STD_LOGIC; + SIGNAL wire_nl10000i_dataout : STD_LOGIC; + SIGNAL wire_nl10000ii_dataout : STD_LOGIC; + SIGNAL wire_nl10000il_dataout : STD_LOGIC; + SIGNAL wire_nl10000iO_dataout : STD_LOGIC; + SIGNAL wire_nl10000li_dataout : STD_LOGIC; + SIGNAL wire_nl10000ll_dataout : STD_LOGIC; + SIGNAL wire_nl10000lO_dataout : STD_LOGIC; + SIGNAL wire_nl10000O_dataout : STD_LOGIC; + SIGNAL wire_nl10000Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10000Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10000OO_dataout : STD_LOGIC; + SIGNAL wire_nl100010i_dataout : STD_LOGIC; + SIGNAL wire_nl100010l_dataout : STD_LOGIC; + SIGNAL wire_nl100010O_dataout : STD_LOGIC; + SIGNAL wire_nl100011i_dataout : STD_LOGIC; + SIGNAL wire_nl100011l_dataout : STD_LOGIC; + SIGNAL wire_nl100011O_dataout : STD_LOGIC; + SIGNAL wire_nl10001ii_dataout : STD_LOGIC; + SIGNAL wire_nl10001il_dataout : STD_LOGIC; + SIGNAL wire_nl10001iO_dataout : STD_LOGIC; + SIGNAL wire_nl10001l_dataout : STD_LOGIC; + SIGNAL wire_nl10001li_dataout : STD_LOGIC; + SIGNAL wire_nl10001ll_dataout : STD_LOGIC; + SIGNAL wire_nl10001lO_dataout : STD_LOGIC; + SIGNAL wire_nl10001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10001Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10001OO_dataout : STD_LOGIC; + SIGNAL wire_nl1000i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1000i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1000i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1000i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1000i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1000i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1000iii_dataout : STD_LOGIC; + SIGNAL wire_nl1000iil_dataout : STD_LOGIC; + SIGNAL wire_nl1000iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1000ili_dataout : STD_LOGIC; + SIGNAL wire_nl1000ill_dataout : STD_LOGIC; + SIGNAL wire_nl1000ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1000iO_dataout : STD_LOGIC; + SIGNAL wire_nl1000iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1000iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1000iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1000l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1000l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1000l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1000l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1000l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1000l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1000li_dataout : STD_LOGIC; + SIGNAL wire_nl1000lii_dataout : STD_LOGIC; + SIGNAL wire_nl1000lil_dataout : STD_LOGIC; + SIGNAL wire_nl1000liO_dataout : STD_LOGIC; + SIGNAL wire_nl1000lli_dataout : STD_LOGIC; + SIGNAL wire_nl1000lll_dataout : STD_LOGIC; + SIGNAL wire_nl1000llO_dataout : STD_LOGIC; + SIGNAL wire_nl1000lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1000lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1000lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1000O_dataout : STD_LOGIC; + SIGNAL wire_nl1000O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1000O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1000O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1000O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1000O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1000O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1000Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1000Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1000OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1000Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1000Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1000OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1000OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1000OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1000OOO_dataout : STD_LOGIC; + SIGNAL wire_nl100100i_dataout : STD_LOGIC; + SIGNAL wire_nl100100l_dataout : STD_LOGIC; + SIGNAL wire_nl100100O_dataout : STD_LOGIC; + SIGNAL wire_nl100101i_dataout : STD_LOGIC; + SIGNAL wire_nl100101l_dataout : STD_LOGIC; + SIGNAL wire_nl100101O_dataout : STD_LOGIC; + SIGNAL wire_nl10010i_dataout : STD_LOGIC; + SIGNAL wire_nl10010ii_dataout : STD_LOGIC; + SIGNAL wire_nl10010il_dataout : STD_LOGIC; + SIGNAL wire_nl10010iO_dataout : STD_LOGIC; + SIGNAL wire_nl10010l_dataout : STD_LOGIC; + SIGNAL wire_nl10010li_dataout : STD_LOGIC; + SIGNAL wire_nl10010ll_dataout : STD_LOGIC; + SIGNAL wire_nl10010lO_dataout : STD_LOGIC; + SIGNAL wire_nl10010O_dataout : STD_LOGIC; + SIGNAL wire_nl10010Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10010Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10010OO_dataout : STD_LOGIC; + SIGNAL wire_nl100110i_dataout : STD_LOGIC; + SIGNAL wire_nl100110l_dataout : STD_LOGIC; + SIGNAL wire_nl100110O_dataout : STD_LOGIC; + SIGNAL wire_nl100111i_dataout : STD_LOGIC; + SIGNAL wire_nl100111l_dataout : STD_LOGIC; + SIGNAL wire_nl100111O_dataout : STD_LOGIC; + SIGNAL wire_nl10011i_dataout : STD_LOGIC; + SIGNAL wire_nl10011ii_dataout : STD_LOGIC; + SIGNAL wire_nl10011il_dataout : STD_LOGIC; + SIGNAL wire_nl10011iO_dataout : STD_LOGIC; + SIGNAL wire_nl10011l_dataout : STD_LOGIC; + SIGNAL wire_nl10011li_dataout : STD_LOGIC; + SIGNAL wire_nl10011ll_dataout : STD_LOGIC; + SIGNAL wire_nl10011lO_dataout : STD_LOGIC; + SIGNAL wire_nl10011O_dataout : STD_LOGIC; + SIGNAL wire_nl10011Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10011Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10011OO_dataout : STD_LOGIC; + SIGNAL wire_nl1001i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1001i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1001i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1001i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1001i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1001i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1001ii_dataout : STD_LOGIC; + SIGNAL wire_nl1001iii_dataout : STD_LOGIC; + SIGNAL wire_nl1001iil_dataout : STD_LOGIC; + SIGNAL wire_nl1001iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1001il_dataout : STD_LOGIC; + SIGNAL wire_nl1001ili_dataout : STD_LOGIC; + SIGNAL wire_nl1001ill_dataout : STD_LOGIC; + SIGNAL wire_nl1001ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1001iO_dataout : STD_LOGIC; + SIGNAL wire_nl1001iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1001iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1001iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1001l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1001l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1001l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1001l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1001l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1001l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1001li_dataout : STD_LOGIC; + SIGNAL wire_nl1001lii_dataout : STD_LOGIC; + SIGNAL wire_nl1001lil_dataout : STD_LOGIC; + SIGNAL wire_nl1001liO_dataout : STD_LOGIC; + SIGNAL wire_nl1001ll_dataout : STD_LOGIC; + SIGNAL wire_nl1001lli_dataout : STD_LOGIC; + SIGNAL wire_nl1001lll_dataout : STD_LOGIC; + SIGNAL wire_nl1001llO_dataout : STD_LOGIC; + SIGNAL wire_nl1001lO_dataout : STD_LOGIC; + SIGNAL wire_nl1001lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1001lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1001lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1001O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1001O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1001O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1001O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1001O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1001O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1001Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1001Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1001OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1001Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1001Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1001OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1001OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1001OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1001OOO_dataout : STD_LOGIC; + SIGNAL wire_nl100i00i_dataout : STD_LOGIC; + SIGNAL wire_nl100i00l_dataout : STD_LOGIC; + SIGNAL wire_nl100i00O_dataout : STD_LOGIC; + SIGNAL wire_nl100i01i_dataout : STD_LOGIC; + SIGNAL wire_nl100i01l_dataout : STD_LOGIC; + SIGNAL wire_nl100i01O_dataout : STD_LOGIC; + SIGNAL wire_nl100i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl100i0il_dataout : STD_LOGIC; + SIGNAL wire_nl100i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl100i0l_dataout : STD_LOGIC; + SIGNAL wire_nl100i0li_dataout : STD_LOGIC; + SIGNAL wire_nl100i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl100i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl100i0O_dataout : STD_LOGIC; + SIGNAL wire_nl100i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl100i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl100i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl100i10i_dataout : STD_LOGIC; + SIGNAL wire_nl100i10l_dataout : STD_LOGIC; + SIGNAL wire_nl100i10O_dataout : STD_LOGIC; + SIGNAL wire_nl100i11i_dataout : STD_LOGIC; + SIGNAL wire_nl100i11l_dataout : STD_LOGIC; + SIGNAL wire_nl100i11O_dataout : STD_LOGIC; + SIGNAL wire_nl100i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl100i1il_dataout : STD_LOGIC; + SIGNAL wire_nl100i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl100i1li_dataout : STD_LOGIC; + SIGNAL wire_nl100i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl100i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl100i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl100i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl100i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl100ii_dataout : STD_LOGIC; + SIGNAL wire_nl100ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl100ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl100ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl100ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl100ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl100ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl100iii_dataout : STD_LOGIC; + SIGNAL wire_nl100iiii_dataout : STD_LOGIC; + SIGNAL wire_nl100iiil_dataout : STD_LOGIC; + SIGNAL wire_nl100iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl100iil_dataout : STD_LOGIC; + SIGNAL wire_nl100iili_dataout : STD_LOGIC; + SIGNAL wire_nl100iill_dataout : STD_LOGIC; + SIGNAL wire_nl100iilO_dataout : STD_LOGIC; + SIGNAL wire_nl100iiO_dataout : STD_LOGIC; + SIGNAL wire_nl100iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl100iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl100iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl100il_dataout : STD_LOGIC; + SIGNAL wire_nl100il0i_dataout : STD_LOGIC; + SIGNAL wire_nl100il0l_dataout : STD_LOGIC; + SIGNAL wire_nl100il0O_dataout : STD_LOGIC; + SIGNAL wire_nl100il1i_dataout : STD_LOGIC; + SIGNAL wire_nl100il1l_dataout : STD_LOGIC; + SIGNAL wire_nl100il1O_dataout : STD_LOGIC; + SIGNAL wire_nl100ili_dataout : STD_LOGIC; + SIGNAL wire_nl100ilii_dataout : STD_LOGIC; + SIGNAL wire_nl100ilil_dataout : STD_LOGIC; + SIGNAL wire_nl100iliO_dataout : STD_LOGIC; + SIGNAL wire_nl100ill_dataout : STD_LOGIC; + SIGNAL wire_nl100illi_dataout : STD_LOGIC; + SIGNAL wire_nl100illl_dataout : STD_LOGIC; + SIGNAL wire_nl100illO_dataout : STD_LOGIC; + SIGNAL wire_nl100ilO_dataout : STD_LOGIC; + SIGNAL wire_nl100ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl100ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl100ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl100iO_dataout : STD_LOGIC; + SIGNAL wire_nl100iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl100iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl100iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl100iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl100iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl100iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl100iOi_dataout : STD_LOGIC; + SIGNAL wire_nl100iOii_dataout : STD_LOGIC; + SIGNAL wire_nl100iOil_dataout : STD_LOGIC; + SIGNAL wire_nl100iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl100iOl_dataout : STD_LOGIC; + SIGNAL wire_nl100iOli_dataout : STD_LOGIC; + SIGNAL wire_nl100iOll_dataout : STD_LOGIC; + SIGNAL wire_nl100iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl100iOO_dataout : STD_LOGIC; + SIGNAL wire_nl100iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl100iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl100iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl100l00i_dataout : STD_LOGIC; + SIGNAL wire_nl100l00l_dataout : STD_LOGIC; + SIGNAL wire_nl100l00O_dataout : STD_LOGIC; + SIGNAL wire_nl100l01i_dataout : STD_LOGIC; + SIGNAL wire_nl100l01l_dataout : STD_LOGIC; + SIGNAL wire_nl100l01O_dataout : STD_LOGIC; + SIGNAL wire_nl100l0i_dataout : STD_LOGIC; + SIGNAL wire_nl100l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl100l0il_dataout : STD_LOGIC; + SIGNAL wire_nl100l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl100l0l_dataout : STD_LOGIC; + SIGNAL wire_nl100l0li_dataout : STD_LOGIC; + SIGNAL wire_nl100l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl100l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl100l0O_dataout : STD_LOGIC; + SIGNAL wire_nl100l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl100l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl100l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl100l10i_dataout : STD_LOGIC; + SIGNAL wire_nl100l10l_dataout : STD_LOGIC; + SIGNAL wire_nl100l10O_dataout : STD_LOGIC; + SIGNAL wire_nl100l11i_dataout : STD_LOGIC; + SIGNAL wire_nl100l11l_dataout : STD_LOGIC; + SIGNAL wire_nl100l11O_dataout : STD_LOGIC; + SIGNAL wire_nl100l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl100l1il_dataout : STD_LOGIC; + SIGNAL wire_nl100l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl100l1l_dataout : STD_LOGIC; + SIGNAL wire_nl100l1li_dataout : STD_LOGIC; + SIGNAL wire_nl100l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl100l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl100l1O_dataout : STD_LOGIC; + SIGNAL wire_nl100l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl100l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl100l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl100li_dataout : STD_LOGIC; + SIGNAL wire_nl100li0i_dataout : STD_LOGIC; + SIGNAL wire_nl100li0l_dataout : STD_LOGIC; + SIGNAL wire_nl100li0O_dataout : STD_LOGIC; + SIGNAL wire_nl100li1i_dataout : STD_LOGIC; + SIGNAL wire_nl100li1l_dataout : STD_LOGIC; + SIGNAL wire_nl100li1O_dataout : STD_LOGIC; + SIGNAL wire_nl100lii_dataout : STD_LOGIC; + SIGNAL wire_nl100liii_dataout : STD_LOGIC; + SIGNAL wire_nl100liil_dataout : STD_LOGIC; + SIGNAL wire_nl100liiO_dataout : STD_LOGIC; + SIGNAL wire_nl100lil_dataout : STD_LOGIC; + SIGNAL wire_nl100lili_dataout : STD_LOGIC; + SIGNAL wire_nl100lill_dataout : STD_LOGIC; + SIGNAL wire_nl100lilO_dataout : STD_LOGIC; + SIGNAL wire_nl100liO_dataout : STD_LOGIC; + SIGNAL wire_nl100liOi_dataout : STD_LOGIC; + SIGNAL wire_nl100liOl_dataout : STD_LOGIC; + SIGNAL wire_nl100liOO_dataout : STD_LOGIC; + SIGNAL wire_nl100ll_dataout : STD_LOGIC; + SIGNAL wire_nl100ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl100ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl100ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl100ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl100ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl100ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl100lli_dataout : STD_LOGIC; + SIGNAL wire_nl100llii_dataout : STD_LOGIC; + SIGNAL wire_nl100llil_dataout : STD_LOGIC; + SIGNAL wire_nl100lliO_dataout : STD_LOGIC; + SIGNAL wire_nl100llli_dataout : STD_LOGIC; + SIGNAL wire_nl100llll_dataout : STD_LOGIC; + SIGNAL wire_nl100lllO_dataout : STD_LOGIC; + SIGNAL wire_nl100llOi_dataout : STD_LOGIC; + SIGNAL wire_nl100llOl_dataout : STD_LOGIC; + SIGNAL wire_nl100llOO_dataout : STD_LOGIC; + SIGNAL wire_nl100lO_dataout : STD_LOGIC; + SIGNAL wire_nl100lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl100lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl100lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl100lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl100lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl100lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl100lOii_dataout : STD_LOGIC; + SIGNAL wire_nl100lOil_dataout : STD_LOGIC; + SIGNAL wire_nl100lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl100lOli_dataout : STD_LOGIC; + SIGNAL wire_nl100lOll_dataout : STD_LOGIC; + SIGNAL wire_nl100lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl100lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl100lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl100lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl100O00i_dataout : STD_LOGIC; + SIGNAL wire_nl100O00l_dataout : STD_LOGIC; + SIGNAL wire_nl100O00O_dataout : STD_LOGIC; + SIGNAL wire_nl100O01i_dataout : STD_LOGIC; + SIGNAL wire_nl100O01l_dataout : STD_LOGIC; + SIGNAL wire_nl100O01O_dataout : STD_LOGIC; + SIGNAL wire_nl100O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl100O0il_dataout : STD_LOGIC; + SIGNAL wire_nl100O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl100O0li_dataout : STD_LOGIC; + SIGNAL wire_nl100O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl100O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl100O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl100O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl100O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl100O10i_dataout : STD_LOGIC; + SIGNAL wire_nl100O10l_dataout : STD_LOGIC; + SIGNAL wire_nl100O10O_dataout : STD_LOGIC; + SIGNAL wire_nl100O11i_dataout : STD_LOGIC; + SIGNAL wire_nl100O11l_dataout : STD_LOGIC; + SIGNAL wire_nl100O11O_dataout : STD_LOGIC; + SIGNAL wire_nl100O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl100O1il_dataout : STD_LOGIC; + SIGNAL wire_nl100O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl100O1li_dataout : STD_LOGIC; + SIGNAL wire_nl100O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl100O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl100O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl100O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl100O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl100Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl100Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl100Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl100Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl100Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl100Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl100Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl100Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl100OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl100Oil_dataout : STD_LOGIC; + SIGNAL wire_nl100Oili_dataout : STD_LOGIC; + SIGNAL wire_nl100Oill_dataout : STD_LOGIC; + SIGNAL wire_nl100OilO_dataout : STD_LOGIC; + SIGNAL wire_nl100OiO_dataout : STD_LOGIC; + SIGNAL wire_nl100OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl100OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl100OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl100Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl100Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl100Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl100Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl100Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl100Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl100Oli_dataout : STD_LOGIC; + SIGNAL wire_nl100Olii_dataout : STD_LOGIC; + SIGNAL wire_nl100Olil_dataout : STD_LOGIC; + SIGNAL wire_nl100OliO_dataout : STD_LOGIC; + SIGNAL wire_nl100Oll_dataout : STD_LOGIC; + SIGNAL wire_nl100Olli_dataout : STD_LOGIC; + SIGNAL wire_nl100Olll_dataout : STD_LOGIC; + SIGNAL wire_nl100OllO_dataout : STD_LOGIC; + SIGNAL wire_nl100OlO_dataout : STD_LOGIC; + SIGNAL wire_nl100OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl100OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl100OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl100OO_dataout : STD_LOGIC; + SIGNAL wire_nl100OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl100OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl100OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl100OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl100OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl100OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl100OOi_dataout : STD_LOGIC; + SIGNAL wire_nl100OOii_dataout : STD_LOGIC; + SIGNAL wire_nl100OOil_dataout : STD_LOGIC; + SIGNAL wire_nl100OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl100OOl_dataout : STD_LOGIC; + SIGNAL wire_nl100OOli_dataout : STD_LOGIC; + SIGNAL wire_nl100OOll_dataout : STD_LOGIC; + SIGNAL wire_nl100OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl100OOO_dataout : STD_LOGIC; + SIGNAL wire_nl100OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl100OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl100OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl101000i_dataout : STD_LOGIC; + SIGNAL wire_nl101000l_dataout : STD_LOGIC; + SIGNAL wire_nl101000O_dataout : STD_LOGIC; + SIGNAL wire_nl101001i_dataout : STD_LOGIC; + SIGNAL wire_nl101001O_dataout : STD_LOGIC; + SIGNAL wire_nl10100i_dataout : STD_LOGIC; + SIGNAL wire_nl10100ii_dataout : STD_LOGIC; + SIGNAL wire_nl10100il_dataout : STD_LOGIC; + SIGNAL wire_nl10100iO_dataout : STD_LOGIC; + SIGNAL wire_nl10100l_dataout : STD_LOGIC; + SIGNAL wire_nl10100li_dataout : STD_LOGIC; + SIGNAL wire_nl10100ll_dataout : STD_LOGIC; + SIGNAL wire_nl101010i_dataout : STD_LOGIC; + SIGNAL wire_nl101010l_dataout : STD_LOGIC; + SIGNAL wire_nl101010O_dataout : STD_LOGIC; + SIGNAL wire_nl101011i_dataout : STD_LOGIC; + SIGNAL wire_nl101011l_dataout : STD_LOGIC; + SIGNAL wire_nl101011O_dataout : STD_LOGIC; + SIGNAL wire_nl10101i_dataout : STD_LOGIC; + SIGNAL wire_nl10101ii_dataout : STD_LOGIC; + SIGNAL wire_nl10101il_dataout : STD_LOGIC; + SIGNAL wire_nl10101li_dataout : STD_LOGIC; + SIGNAL wire_nl10101ll_dataout : STD_LOGIC; + SIGNAL wire_nl10101lO_dataout : STD_LOGIC; + SIGNAL wire_nl10101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10101OO_dataout : STD_LOGIC; + SIGNAL wire_nl1010i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1010i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1010i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1010i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1010i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1010ii_dataout : STD_LOGIC; + SIGNAL wire_nl1010iii_dataout : STD_LOGIC; + SIGNAL wire_nl1010iil_dataout : STD_LOGIC; + SIGNAL wire_nl1010iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1010il_dataout : STD_LOGIC; + SIGNAL wire_nl1010ili_dataout : STD_LOGIC; + SIGNAL wire_nl1010ill_dataout : STD_LOGIC; + SIGNAL wire_nl1010ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1010iO_dataout : STD_LOGIC; + SIGNAL wire_nl1010iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1010iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1010iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1010l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1010l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1010l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1010l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1010l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1010l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1010lii_dataout : STD_LOGIC; + SIGNAL wire_nl1010lil_dataout : STD_LOGIC; + SIGNAL wire_nl1010liO_dataout : STD_LOGIC; + SIGNAL wire_nl1010lli_dataout : STD_LOGIC; + SIGNAL wire_nl1010lll_dataout : STD_LOGIC; + SIGNAL wire_nl1010llO_dataout : STD_LOGIC; + SIGNAL wire_nl1010lO_dataout : STD_LOGIC; + SIGNAL wire_nl1010lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1010lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1010lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1010O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1010O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1010O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1010O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1010O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1010O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1010Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1010Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1010OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1010Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1010Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1010OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1010OO_dataout : STD_LOGIC; + SIGNAL wire_nl1010OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1010OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1010OOO_dataout : STD_LOGIC; + SIGNAL wire_nl101100i_dataout : STD_LOGIC; + SIGNAL wire_nl101100l_dataout : STD_LOGIC; + SIGNAL wire_nl101100O_dataout : STD_LOGIC; + SIGNAL wire_nl101101i_dataout : STD_LOGIC; + SIGNAL wire_nl101101l_dataout : STD_LOGIC; + SIGNAL wire_nl101101O_dataout : STD_LOGIC; + SIGNAL wire_nl10110i_dataout : STD_LOGIC; + SIGNAL wire_nl10110ii_dataout : STD_LOGIC; + SIGNAL wire_nl10110il_dataout : STD_LOGIC; + SIGNAL wire_nl10110iO_dataout : STD_LOGIC; + SIGNAL wire_nl10110li_dataout : STD_LOGIC; + SIGNAL wire_nl10110ll_dataout : STD_LOGIC; + SIGNAL wire_nl10110lO_dataout : STD_LOGIC; + SIGNAL wire_nl10110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10110OO_dataout : STD_LOGIC; + SIGNAL wire_nl101110i_dataout : STD_LOGIC; + SIGNAL wire_nl101110l_dataout : STD_LOGIC; + SIGNAL wire_nl101110O_dataout : STD_LOGIC; + SIGNAL wire_nl101111i_dataout : STD_LOGIC; + SIGNAL wire_nl101111l_dataout : STD_LOGIC; + SIGNAL wire_nl101111O_dataout : STD_LOGIC; + SIGNAL wire_nl10111ii_dataout : STD_LOGIC; + SIGNAL wire_nl10111il_dataout : STD_LOGIC; + SIGNAL wire_nl10111iO_dataout : STD_LOGIC; + SIGNAL wire_nl10111li_dataout : STD_LOGIC; + SIGNAL wire_nl10111ll_dataout : STD_LOGIC; + SIGNAL wire_nl10111lO_dataout : STD_LOGIC; + SIGNAL wire_nl10111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10111OO_dataout : STD_LOGIC; + SIGNAL wire_nl1011i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1011i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1011i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1011i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1011i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1011i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1011ii_dataout : STD_LOGIC; + SIGNAL wire_nl1011iii_dataout : STD_LOGIC; + SIGNAL wire_nl1011iil_dataout : STD_LOGIC; + SIGNAL wire_nl1011iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1011il_dataout : STD_LOGIC; + SIGNAL wire_nl1011ili_dataout : STD_LOGIC; + SIGNAL wire_nl1011ill_dataout : STD_LOGIC; + SIGNAL wire_nl1011lO_dataout : STD_LOGIC; + SIGNAL wire_nl1011lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1011O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1011O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1011O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1011O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1011O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1011Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1011Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1011OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1011Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1011Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1011Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1011OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1011OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1011OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1011OOO_dataout : STD_LOGIC; + SIGNAL wire_nl101i00i_dataout : STD_LOGIC; + SIGNAL wire_nl101i01O_dataout : STD_LOGIC; + SIGNAL wire_nl101i0i_dataout : STD_LOGIC; + SIGNAL wire_nl101i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl101i0O_dataout : STD_LOGIC; + SIGNAL wire_nl101i10i_dataout : STD_LOGIC; + SIGNAL wire_nl101i11l_dataout : STD_LOGIC; + SIGNAL wire_nl101i11O_dataout : STD_LOGIC; + SIGNAL wire_nl101i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl101i1il_dataout : STD_LOGIC; + SIGNAL wire_nl101i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl101i1li_dataout : STD_LOGIC; + SIGNAL wire_nl101i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl101i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl101ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl101ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl101iiii_dataout : STD_LOGIC; + SIGNAL wire_nl101iiil_dataout : STD_LOGIC; + SIGNAL wire_nl101iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl101iil_dataout : STD_LOGIC; + SIGNAL wire_nl101iili_dataout : STD_LOGIC; + SIGNAL wire_nl101iill_dataout : STD_LOGIC; + SIGNAL wire_nl101iilO_dataout : STD_LOGIC; + SIGNAL wire_nl101iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl101iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl101iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl101il0i_dataout : STD_LOGIC; + SIGNAL wire_nl101il0l_dataout : STD_LOGIC; + SIGNAL wire_nl101il0O_dataout : STD_LOGIC; + SIGNAL wire_nl101il1i_dataout : STD_LOGIC; + SIGNAL wire_nl101il1l_dataout : STD_LOGIC; + SIGNAL wire_nl101il1O_dataout : STD_LOGIC; + SIGNAL wire_nl101ilii_dataout : STD_LOGIC; + SIGNAL wire_nl101ilil_dataout : STD_LOGIC; + SIGNAL wire_nl101iliO_dataout : STD_LOGIC; + SIGNAL wire_nl101ill_dataout : STD_LOGIC; + SIGNAL wire_nl101illi_dataout : STD_LOGIC; + SIGNAL wire_nl101illl_dataout : STD_LOGIC; + SIGNAL wire_nl101illO_dataout : STD_LOGIC; + SIGNAL wire_nl101ilO_dataout : STD_LOGIC; + SIGNAL wire_nl101ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl101ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl101ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl101iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl101iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl101iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl101iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl101iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl101iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl101iOii_dataout : STD_LOGIC; + SIGNAL wire_nl101iOil_dataout : STD_LOGIC; + SIGNAL wire_nl101iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl101iOl_dataout : STD_LOGIC; + SIGNAL wire_nl101iOli_dataout : STD_LOGIC; + SIGNAL wire_nl101iOll_dataout : STD_LOGIC; + SIGNAL wire_nl101iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl101iOO_dataout : STD_LOGIC; + SIGNAL wire_nl101iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl101iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl101iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl101l00i_dataout : STD_LOGIC; + SIGNAL wire_nl101l00l_dataout : STD_LOGIC; + SIGNAL wire_nl101l00O_dataout : STD_LOGIC; + SIGNAL wire_nl101l01i_dataout : STD_LOGIC; + SIGNAL wire_nl101l01l_dataout : STD_LOGIC; + SIGNAL wire_nl101l01O_dataout : STD_LOGIC; + SIGNAL wire_nl101l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl101l0il_dataout : STD_LOGIC; + SIGNAL wire_nl101l0l_dataout : STD_LOGIC; + SIGNAL wire_nl101l0li_dataout : STD_LOGIC; + SIGNAL wire_nl101l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl101l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl101l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl101l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl101l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl101l10i_dataout : STD_LOGIC; + SIGNAL wire_nl101l10l_dataout : STD_LOGIC; + SIGNAL wire_nl101l10O_dataout : STD_LOGIC; + SIGNAL wire_nl101l11i_dataout : STD_LOGIC; + SIGNAL wire_nl101l11l_dataout : STD_LOGIC; + SIGNAL wire_nl101l11O_dataout : STD_LOGIC; + SIGNAL wire_nl101l1i_dataout : STD_LOGIC; + SIGNAL wire_nl101l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl101l1il_dataout : STD_LOGIC; + SIGNAL wire_nl101l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl101l1li_dataout : STD_LOGIC; + SIGNAL wire_nl101l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl101l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl101l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl101l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl101l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl101li0i_dataout : STD_LOGIC; + SIGNAL wire_nl101li0l_dataout : STD_LOGIC; + SIGNAL wire_nl101li0O_dataout : STD_LOGIC; + SIGNAL wire_nl101li1i_dataout : STD_LOGIC; + SIGNAL wire_nl101li1l_dataout : STD_LOGIC; + SIGNAL wire_nl101li1O_dataout : STD_LOGIC; + SIGNAL wire_nl101liii_dataout : STD_LOGIC; + SIGNAL wire_nl101liil_dataout : STD_LOGIC; + SIGNAL wire_nl101liiO_dataout : STD_LOGIC; + SIGNAL wire_nl101lili_dataout : STD_LOGIC; + SIGNAL wire_nl101lill_dataout : STD_LOGIC; + SIGNAL wire_nl101lilO_dataout : STD_LOGIC; + SIGNAL wire_nl101liOi_dataout : STD_LOGIC; + SIGNAL wire_nl101liOl_dataout : STD_LOGIC; + SIGNAL wire_nl101liOO_dataout : STD_LOGIC; + SIGNAL wire_nl101ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl101ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl101ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl101ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl101ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl101ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl101llii_dataout : STD_LOGIC; + SIGNAL wire_nl101llil_dataout : STD_LOGIC; + SIGNAL wire_nl101lliO_dataout : STD_LOGIC; + SIGNAL wire_nl101llli_dataout : STD_LOGIC; + SIGNAL wire_nl101llll_dataout : STD_LOGIC; + SIGNAL wire_nl101lllO_dataout : STD_LOGIC; + SIGNAL wire_nl101llOi_dataout : STD_LOGIC; + SIGNAL wire_nl101llOl_dataout : STD_LOGIC; + SIGNAL wire_nl101llOO_dataout : STD_LOGIC; + SIGNAL wire_nl101lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl101lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl101lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl101lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl101lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl101lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl101lOii_dataout : STD_LOGIC; + SIGNAL wire_nl101lOil_dataout : STD_LOGIC; + SIGNAL wire_nl101lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl101lOli_dataout : STD_LOGIC; + SIGNAL wire_nl101lOll_dataout : STD_LOGIC; + SIGNAL wire_nl101lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl101lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl101lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl101lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl101O10i_dataout : STD_LOGIC; + SIGNAL wire_nl101O10l_dataout : STD_LOGIC; + SIGNAL wire_nl101O10O_dataout : STD_LOGIC; + SIGNAL wire_nl101O11i_dataout : STD_LOGIC; + SIGNAL wire_nl101O11l_dataout : STD_LOGIC; + SIGNAL wire_nl101O11O_dataout : STD_LOGIC; + SIGNAL wire_nl101O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl101O1il_dataout : STD_LOGIC; + SIGNAL wire_nl101O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl101O1li_dataout : STD_LOGIC; + SIGNAL wire_nl101O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl101O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl101O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl101Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl101Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl101Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl101Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl101Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl101OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl101Oili_dataout : STD_LOGIC; + SIGNAL wire_nl101Oill_dataout : STD_LOGIC; + SIGNAL wire_nl101OilO_dataout : STD_LOGIC; + SIGNAL wire_nl101OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl101OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl101OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl101Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl101Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl101Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl101Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl101Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl101Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl101Olii_dataout : STD_LOGIC; + SIGNAL wire_nl101Olil_dataout : STD_LOGIC; + SIGNAL wire_nl101OliO_dataout : STD_LOGIC; + SIGNAL wire_nl101Oll_dataout : STD_LOGIC; + SIGNAL wire_nl101Olli_dataout : STD_LOGIC; + SIGNAL wire_nl101Olll_dataout : STD_LOGIC; + SIGNAL wire_nl101OllO_dataout : STD_LOGIC; + SIGNAL wire_nl101OlO_dataout : STD_LOGIC; + SIGNAL wire_nl101OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl101OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl101OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl101OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl101OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl101OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl101OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl101OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl101OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl101OOi_dataout : STD_LOGIC; + SIGNAL wire_nl101OOii_dataout : STD_LOGIC; + SIGNAL wire_nl101OOil_dataout : STD_LOGIC; + SIGNAL wire_nl101OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl101OOl_dataout : STD_LOGIC; + SIGNAL wire_nl101OOli_dataout : STD_LOGIC; + SIGNAL wire_nl101OOll_dataout : STD_LOGIC; + SIGNAL wire_nl101OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl101OOO_dataout : STD_LOGIC; + SIGNAL wire_nl101OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl101OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl101OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10i000i_dataout : STD_LOGIC; + SIGNAL wire_nl10i000l_dataout : STD_LOGIC; + SIGNAL wire_nl10i000O_dataout : STD_LOGIC; + SIGNAL wire_nl10i001i_dataout : STD_LOGIC; + SIGNAL wire_nl10i001l_dataout : STD_LOGIC; + SIGNAL wire_nl10i001O_dataout : STD_LOGIC; + SIGNAL wire_nl10i00ii_dataout : STD_LOGIC; + SIGNAL wire_nl10i00il_dataout : STD_LOGIC; + SIGNAL wire_nl10i00iO_dataout : STD_LOGIC; + SIGNAL wire_nl10i00l_dataout : STD_LOGIC; + SIGNAL wire_nl10i00li_dataout : STD_LOGIC; + SIGNAL wire_nl10i00ll_dataout : STD_LOGIC; + SIGNAL wire_nl10i00lO_dataout : STD_LOGIC; + SIGNAL wire_nl10i00O_dataout : STD_LOGIC; + SIGNAL wire_nl10i00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10i00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10i00OO_dataout : STD_LOGIC; + SIGNAL wire_nl10i010i_dataout : STD_LOGIC; + SIGNAL wire_nl10i010l_dataout : STD_LOGIC; + SIGNAL wire_nl10i010O_dataout : STD_LOGIC; + SIGNAL wire_nl10i011i_dataout : STD_LOGIC; + SIGNAL wire_nl10i011l_dataout : STD_LOGIC; + SIGNAL wire_nl10i011O_dataout : STD_LOGIC; + SIGNAL wire_nl10i01ii_dataout : STD_LOGIC; + SIGNAL wire_nl10i01il_dataout : STD_LOGIC; + SIGNAL wire_nl10i01iO_dataout : STD_LOGIC; + SIGNAL wire_nl10i01li_dataout : STD_LOGIC; + SIGNAL wire_nl10i01ll_dataout : STD_LOGIC; + SIGNAL wire_nl10i01lO_dataout : STD_LOGIC; + SIGNAL wire_nl10i01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10i01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10i01OO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0i_dataout : STD_LOGIC; + SIGNAL wire_nl10i0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl10i0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl10i0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl10i0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl10i0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl10i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10i0iii_dataout : STD_LOGIC; + SIGNAL wire_nl10i0iil_dataout : STD_LOGIC; + SIGNAL wire_nl10i0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0il_dataout : STD_LOGIC; + SIGNAL wire_nl10i0ili_dataout : STD_LOGIC; + SIGNAL wire_nl10i0ill_dataout : STD_LOGIC; + SIGNAL wire_nl10i0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl10i0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl10i0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0l_dataout : STD_LOGIC; + SIGNAL wire_nl10i0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl10i0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl10i0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl10i0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl10i0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl10i0li_dataout : STD_LOGIC; + SIGNAL wire_nl10i0lii_dataout : STD_LOGIC; + SIGNAL wire_nl10i0lil_dataout : STD_LOGIC; + SIGNAL wire_nl10i0liO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10i0lli_dataout : STD_LOGIC; + SIGNAL wire_nl10i0lll_dataout : STD_LOGIC; + SIGNAL wire_nl10i0llO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl10i0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl10i0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl10i0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl10i0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl10i0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl10i0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl10i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10i0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl10i0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl10i0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10i0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl10i0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl10i0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10i0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl10i0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl10i0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl10i100i_dataout : STD_LOGIC; + SIGNAL wire_nl10i100l_dataout : STD_LOGIC; + SIGNAL wire_nl10i100O_dataout : STD_LOGIC; + SIGNAL wire_nl10i101i_dataout : STD_LOGIC; + SIGNAL wire_nl10i101l_dataout : STD_LOGIC; + SIGNAL wire_nl10i101O_dataout : STD_LOGIC; + SIGNAL wire_nl10i10ii_dataout : STD_LOGIC; + SIGNAL wire_nl10i10il_dataout : STD_LOGIC; + SIGNAL wire_nl10i10iO_dataout : STD_LOGIC; + SIGNAL wire_nl10i10li_dataout : STD_LOGIC; + SIGNAL wire_nl10i10ll_dataout : STD_LOGIC; + SIGNAL wire_nl10i10lO_dataout : STD_LOGIC; + SIGNAL wire_nl10i10O_dataout : STD_LOGIC; + SIGNAL wire_nl10i10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10i10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10i10OO_dataout : STD_LOGIC; + SIGNAL wire_nl10i110i_dataout : STD_LOGIC; + SIGNAL wire_nl10i110l_dataout : STD_LOGIC; + SIGNAL wire_nl10i110O_dataout : STD_LOGIC; + SIGNAL wire_nl10i111i_dataout : STD_LOGIC; + SIGNAL wire_nl10i111l_dataout : STD_LOGIC; + SIGNAL wire_nl10i111O_dataout : STD_LOGIC; + SIGNAL wire_nl10i11i_dataout : STD_LOGIC; + SIGNAL wire_nl10i11ii_dataout : STD_LOGIC; + SIGNAL wire_nl10i11il_dataout : STD_LOGIC; + SIGNAL wire_nl10i11iO_dataout : STD_LOGIC; + SIGNAL wire_nl10i11l_dataout : STD_LOGIC; + SIGNAL wire_nl10i11li_dataout : STD_LOGIC; + SIGNAL wire_nl10i11ll_dataout : STD_LOGIC; + SIGNAL wire_nl10i11lO_dataout : STD_LOGIC; + SIGNAL wire_nl10i11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10i11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10i11OO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1i_dataout : STD_LOGIC; + SIGNAL wire_nl10i1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl10i1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl10i1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl10i1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl10i1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl10i1iii_dataout : STD_LOGIC; + SIGNAL wire_nl10i1iil_dataout : STD_LOGIC; + SIGNAL wire_nl10i1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1il_dataout : STD_LOGIC; + SIGNAL wire_nl10i1ili_dataout : STD_LOGIC; + SIGNAL wire_nl10i1ill_dataout : STD_LOGIC; + SIGNAL wire_nl10i1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl10i1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl10i1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1l_dataout : STD_LOGIC; + SIGNAL wire_nl10i1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl10i1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl10i1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl10i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl10i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl10i1li_dataout : STD_LOGIC; + SIGNAL wire_nl10i1lii_dataout : STD_LOGIC; + SIGNAL wire_nl10i1lil_dataout : STD_LOGIC; + SIGNAL wire_nl10i1liO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1lli_dataout : STD_LOGIC; + SIGNAL wire_nl10i1lll_dataout : STD_LOGIC; + SIGNAL wire_nl10i1llO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl10i1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl10i1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1O_dataout : STD_LOGIC; + SIGNAL wire_nl10i1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl10i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl10i1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl10i1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl10i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl10i1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl10i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10i1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl10i1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl10i1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10i1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl10i1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl10i1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl10i1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl10i1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl10i1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl10ii01O_dataout : STD_LOGIC; + SIGNAL wire_nl10ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl10ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10ii10i_dataout : STD_LOGIC; + SIGNAL wire_nl10ii10l_dataout : STD_LOGIC; + SIGNAL wire_nl10ii10O_dataout : STD_LOGIC; + SIGNAL wire_nl10ii11i_dataout : STD_LOGIC; + SIGNAL wire_nl10ii11l_dataout : STD_LOGIC; + SIGNAL wire_nl10ii11O_dataout : STD_LOGIC; + SIGNAL wire_nl10ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl10ii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10ii1il_dataout : STD_LOGIC; + SIGNAL wire_nl10ii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl10ii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10ii1lO_w_lg_dataout59872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10ii1lO_w_lg_dataout59873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iii_dataout : STD_LOGIC; + SIGNAL wire_nl10iii1i_dataout : STD_LOGIC; + SIGNAL wire_nl10iii1l_dataout : STD_LOGIC; + SIGNAL wire_nl10iil_dataout : STD_LOGIC; + SIGNAL wire_nl10iil1O_dataout : STD_LOGIC; + SIGNAL wire_nl10iil1O_w_lg_dataout61537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iilli_dataout : STD_LOGIC; + SIGNAL wire_nl10iilli_w_lg_dataout61528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iilll_dataout : STD_LOGIC; + SIGNAL wire_nl10iillO_dataout : STD_LOGIC; + SIGNAL wire_nl10iilOi_dataout : STD_LOGIC; + SIGNAL wire_nl10iilOl_dataout : STD_LOGIC; + SIGNAL wire_nl10iilOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iiO_dataout : STD_LOGIC; + SIGNAL wire_nl10iiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl10iiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl10iiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl10iiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl10iiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl10iiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOii_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOil_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOli_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOOl_w_lg_w_lg_dataout59597w59874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iiOOl_w_lg_dataout59870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iiOOl_w_lg_dataout59597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iiOOO_w_lg_w_lg_dataout59596w59598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iiOOO_w_lg_w_lg_w_lg_dataout59596w59598w59599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iiOOO_w_lg_dataout59596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il00i_dataout : STD_LOGIC; + SIGNAL wire_nl10il00l_dataout : STD_LOGIC; + SIGNAL wire_nl10il00O_dataout : STD_LOGIC; + SIGNAL wire_nl10il01i_dataout : STD_LOGIC; + SIGNAL wire_nl10il01l_dataout : STD_LOGIC; + SIGNAL wire_nl10il01O_dataout : STD_LOGIC; + SIGNAL wire_nl10il0i_dataout : STD_LOGIC; + SIGNAL wire_nl10il0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10il0il_dataout : STD_LOGIC; + SIGNAL wire_nl10il0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10il0l_dataout : STD_LOGIC; + SIGNAL wire_nl10il0li_dataout : STD_LOGIC; + SIGNAL wire_nl10il0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10il0lO_dataout : STD_LOGIC; + SIGNAL wire_nl10il0O_dataout : STD_LOGIC; + SIGNAL wire_nl10il0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10il0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10il0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10il10i_dataout : STD_LOGIC; + SIGNAL wire_nl10il10i_w_lg_dataout60297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il10l_dataout : STD_LOGIC; + SIGNAL wire_nl10il10l_w_lg_dataout60295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il10O_dataout : STD_LOGIC; + SIGNAL wire_nl10il10O_w_lg_dataout60293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il11i_dataout : STD_LOGIC; + SIGNAL wire_nl10il11i_w_lg_dataout60303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il11l_dataout : STD_LOGIC; + SIGNAL wire_nl10il11l_w_lg_dataout60301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il11O_dataout : STD_LOGIC; + SIGNAL wire_nl10il11O_w_lg_dataout60299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il1i_dataout : STD_LOGIC; + SIGNAL wire_nl10il1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10il1ii_w_lg_dataout60291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il1il_dataout : STD_LOGIC; + SIGNAL wire_nl10il1il_w_lg_dataout60290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10il1l_dataout : STD_LOGIC; + SIGNAL wire_nl10il1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10il1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10il1O_dataout : STD_LOGIC; + SIGNAL wire_nl10il1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10il1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10ili_dataout : STD_LOGIC; + SIGNAL wire_nl10ili0i_dataout : STD_LOGIC; + SIGNAL wire_nl10ili0l_dataout : STD_LOGIC; + SIGNAL wire_nl10ili0O_dataout : STD_LOGIC; + SIGNAL wire_nl10ili1i_dataout : STD_LOGIC; + SIGNAL wire_nl10ili1l_dataout : STD_LOGIC; + SIGNAL wire_nl10ili1O_dataout : STD_LOGIC; + SIGNAL wire_nl10ilii_dataout : STD_LOGIC; + SIGNAL wire_nl10iliii_dataout : STD_LOGIC; + SIGNAL wire_nl10iliil_dataout : STD_LOGIC; + SIGNAL wire_nl10ilil_dataout : STD_LOGIC; + SIGNAL wire_nl10iliO_dataout : STD_LOGIC; + SIGNAL wire_nl10ill_dataout : STD_LOGIC; + SIGNAL wire_nl10ilO_dataout : STD_LOGIC; + SIGNAL wire_nl10ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl10ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl10ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iO00i_dataout : STD_LOGIC; + SIGNAL wire_nl10iO00l_dataout : STD_LOGIC; + SIGNAL wire_nl10iO00O_dataout : STD_LOGIC; + SIGNAL wire_nl10iO01i_dataout : STD_LOGIC; + SIGNAL wire_nl10iO01l_dataout : STD_LOGIC; + SIGNAL wire_nl10iO01O_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0il_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0li_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10iO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10iO10i_dataout : STD_LOGIC; + SIGNAL wire_nl10iO10l_dataout : STD_LOGIC; + SIGNAL wire_nl10iO10O_dataout : STD_LOGIC; + SIGNAL wire_nl10iO11i_dataout : STD_LOGIC; + SIGNAL wire_nl10iO11l_dataout : STD_LOGIC; + SIGNAL wire_nl10iO11O_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1il_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10iO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOi_dataout : STD_LOGIC; + SIGNAL wire_nl10iOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl10iOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl10iOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl10iOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl10iOili_dataout : STD_LOGIC; + SIGNAL wire_nl10iOili_w_lg_dataout59417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iOill_dataout : STD_LOGIC; + SIGNAL wire_nl10iOill_w_lg_dataout59415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iOilO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOilO_w_lg_dataout59414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10iOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl10iOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl10iOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOl_dataout : STD_LOGIC; + SIGNAL wire_nl10iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl10iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl10iOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl10iOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl10iOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl10iOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlii_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlil_dataout : STD_LOGIC; + SIGNAL wire_nl10iOliO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlli_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlll_dataout : STD_LOGIC; + SIGNAL wire_nl10iOllO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl10iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10iOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10iOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10iOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10iOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10l0i_dataout : STD_LOGIC; + SIGNAL wire_nl10l0l_dataout : STD_LOGIC; + SIGNAL wire_nl10l0O_dataout : STD_LOGIC; + SIGNAL wire_nl10l100i_dataout : STD_LOGIC; + SIGNAL wire_nl10l100l_dataout : STD_LOGIC; + SIGNAL wire_nl10l100O_dataout : STD_LOGIC; + SIGNAL wire_nl10l101i_dataout : STD_LOGIC; + SIGNAL wire_nl10l101l_dataout : STD_LOGIC; + SIGNAL wire_nl10l101O_dataout : STD_LOGIC; + SIGNAL wire_nl10l10ii_dataout : STD_LOGIC; + SIGNAL wire_nl10l10il_dataout : STD_LOGIC; + SIGNAL wire_nl10l10iO_dataout : STD_LOGIC; + SIGNAL wire_nl10l10l_dataout : STD_LOGIC; + SIGNAL wire_nl10l10li_dataout : STD_LOGIC; + SIGNAL wire_nl10l10ll_dataout : STD_LOGIC; + SIGNAL wire_nl10l10lO_dataout : STD_LOGIC; + SIGNAL wire_nl10l10O_dataout : STD_LOGIC; + SIGNAL wire_nl10l10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10l10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10l10OO_dataout : STD_LOGIC; + SIGNAL wire_nl10l110i_dataout : STD_LOGIC; + SIGNAL wire_nl10l110l_dataout : STD_LOGIC; + SIGNAL wire_nl10l110O_dataout : STD_LOGIC; + SIGNAL wire_nl10l111i_dataout : STD_LOGIC; + SIGNAL wire_nl10l111l_dataout : STD_LOGIC; + SIGNAL wire_nl10l111O_dataout : STD_LOGIC; + SIGNAL wire_nl10l11i_dataout : STD_LOGIC; + SIGNAL wire_nl10l11ii_dataout : STD_LOGIC; + SIGNAL wire_nl10l11il_dataout : STD_LOGIC; + SIGNAL wire_nl10l11iO_dataout : STD_LOGIC; + SIGNAL wire_nl10l11l_dataout : STD_LOGIC; + SIGNAL wire_nl10l11li_dataout : STD_LOGIC; + SIGNAL wire_nl10l11ll_dataout : STD_LOGIC; + SIGNAL wire_nl10l11lO_dataout : STD_LOGIC; + SIGNAL wire_nl10l11O_dataout : STD_LOGIC; + SIGNAL wire_nl10l11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10l11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10l11OO_dataout : STD_LOGIC; + SIGNAL wire_nl10l1i_dataout : STD_LOGIC; + SIGNAL wire_nl10l1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl10l1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl10l1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl10l1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl10l1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl10l1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl10l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10l1iii_dataout : STD_LOGIC; + SIGNAL wire_nl10l1iil_dataout : STD_LOGIC; + SIGNAL wire_nl10l1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl10l1il_dataout : STD_LOGIC; + SIGNAL wire_nl10l1ili_dataout : STD_LOGIC; + SIGNAL wire_nl10l1ill_dataout : STD_LOGIC; + SIGNAL wire_nl10l1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl10l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10l1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl10l1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl10l1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl10l1l_dataout : STD_LOGIC; + SIGNAL wire_nl10l1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl10l1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl10l1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl10l1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl10l1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl10l1lii_dataout : STD_LOGIC; + SIGNAL wire_nl10l1lli_dataout : STD_LOGIC; + SIGNAL wire_nl10l1lll_dataout : STD_LOGIC; + SIGNAL wire_nl10l1O_dataout : STD_LOGIC; + SIGNAL wire_nl10lii_dataout : STD_LOGIC; + SIGNAL wire_nl10liii_dataout : STD_LOGIC; + SIGNAL wire_nl10liil_dataout : STD_LOGIC; + SIGNAL wire_nl10liiO_dataout : STD_LOGIC; + SIGNAL wire_nl10lil_dataout : STD_LOGIC; + SIGNAL wire_nl10lili_dataout : STD_LOGIC; + SIGNAL wire_nl10lill_dataout : STD_LOGIC; + SIGNAL wire_nl10lilO_dataout : STD_LOGIC; + SIGNAL wire_nl10liO_dataout : STD_LOGIC; + SIGNAL wire_nl10liO0i_dataout : STD_LOGIC; + SIGNAL wire_nl10liO1O_dataout : STD_LOGIC; + SIGNAL wire_nl10liOi_dataout : STD_LOGIC; + SIGNAL wire_nl10liOil_dataout : STD_LOGIC; + SIGNAL wire_nl10liOiO_dataout : STD_LOGIC; + SIGNAL wire_nl10liOl_dataout : STD_LOGIC; + SIGNAL wire_nl10liOli_dataout : STD_LOGIC; + SIGNAL wire_nl10liOll_dataout : STD_LOGIC; + SIGNAL wire_nl10liOlO_dataout : STD_LOGIC; + SIGNAL wire_nl10liOO_dataout : STD_LOGIC; + SIGNAL wire_nl10liOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10liOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10liOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10ll00i_dataout : STD_LOGIC; + SIGNAL wire_nl10ll00l_dataout : STD_LOGIC; + SIGNAL wire_nl10ll00O_dataout : STD_LOGIC; + SIGNAL wire_nl10ll01i_dataout : STD_LOGIC; + SIGNAL wire_nl10ll01l_dataout : STD_LOGIC; + SIGNAL wire_nl10ll01O_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0il_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0li_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0lO_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10ll0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10ll10i_dataout : STD_LOGIC; + SIGNAL wire_nl10ll10l_dataout : STD_LOGIC; + SIGNAL wire_nl10ll10O_dataout : STD_LOGIC; + SIGNAL wire_nl10ll11i_dataout : STD_LOGIC; + SIGNAL wire_nl10ll11l_dataout : STD_LOGIC; + SIGNAL wire_nl10ll11O_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1il_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1li_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10ll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10lli_dataout : STD_LOGIC; + SIGNAL wire_nl10lli0i_dataout : STD_LOGIC; + SIGNAL wire_nl10lli0i_w_lg_dataout58914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lli0l_dataout : STD_LOGIC; + SIGNAL wire_nl10lli1i_dataout : STD_LOGIC; + SIGNAL wire_nl10lli1l_dataout : STD_LOGIC; + SIGNAL wire_nl10lli1O_dataout : STD_LOGIC; + SIGNAL wire_nl10llii_dataout : STD_LOGIC; + SIGNAL wire_nl10lll_dataout : STD_LOGIC; + SIGNAL wire_nl10lll0l_dataout : STD_LOGIC; + SIGNAL wire_nl10lll0O_dataout : STD_LOGIC; + SIGNAL wire_nl10lllii_dataout : STD_LOGIC; + SIGNAL wire_nl10lllil_dataout : STD_LOGIC; + SIGNAL wire_nl10llliO_dataout : STD_LOGIC; + SIGNAL wire_nl10llll_dataout : STD_LOGIC; + SIGNAL wire_nl10lllli_dataout : STD_LOGIC; + SIGNAL wire_nl10lllll_dataout : STD_LOGIC; + SIGNAL wire_nl10llllO_dataout : STD_LOGIC; + SIGNAL wire_nl10lllOi_dataout : STD_LOGIC; + SIGNAL wire_nl10lllOl_dataout : STD_LOGIC; + SIGNAL wire_nl10lllOO_dataout : STD_LOGIC; + SIGNAL wire_nl10llO_dataout : STD_LOGIC; + SIGNAL wire_nl10llO0i_dataout : STD_LOGIC; + SIGNAL wire_nl10llO0l_dataout : STD_LOGIC; + SIGNAL wire_nl10llO0O_dataout : STD_LOGIC; + SIGNAL wire_nl10llO1i_dataout : STD_LOGIC; + SIGNAL wire_nl10llO1l_dataout : STD_LOGIC; + SIGNAL wire_nl10llO1O_dataout : STD_LOGIC; + SIGNAL wire_nl10llOi_dataout : STD_LOGIC; + SIGNAL wire_nl10llOii_dataout : STD_LOGIC; + SIGNAL wire_nl10llOil_dataout : STD_LOGIC; + SIGNAL wire_nl10llOiO_dataout : STD_LOGIC; + SIGNAL wire_nl10llOli_dataout : STD_LOGIC; + SIGNAL wire_nl10llOO_dataout : STD_LOGIC; + SIGNAL wire_nl10llOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10llOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10llOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10lO00i_dataout : STD_LOGIC; + SIGNAL wire_nl10lO00l_dataout : STD_LOGIC; + SIGNAL wire_nl10lO00O_dataout : STD_LOGIC; + SIGNAL wire_nl10lO01i_dataout : STD_LOGIC; + SIGNAL wire_nl10lO01l_dataout : STD_LOGIC; + SIGNAL wire_nl10lO01O_dataout : STD_LOGIC; + SIGNAL wire_nl10lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl10lO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10lO0il_dataout : STD_LOGIC; + SIGNAL wire_nl10lO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10lO0li_dataout : STD_LOGIC; + SIGNAL wire_nl10lO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10lO10i_dataout : STD_LOGIC; + SIGNAL wire_nl10lO10l_dataout : STD_LOGIC; + SIGNAL wire_nl10lO10O_dataout : STD_LOGIC; + SIGNAL wire_nl10lO11i_dataout : STD_LOGIC; + SIGNAL wire_nl10lO11l_dataout : STD_LOGIC; + SIGNAL wire_nl10lO11O_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1il_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1li_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10lO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10lOi_dataout : STD_LOGIC; + SIGNAL wire_nl10lOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl10lOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl10lOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl10lOill_dataout : STD_LOGIC; + SIGNAL wire_nl10lOilO_dataout : STD_LOGIC; + SIGNAL wire_nl10lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl10lOl_dataout : STD_LOGIC; + SIGNAL wire_nl10lOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl10lOl0l_w_lg_dataout58922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl10lOl0O_w_lg_dataout58919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lOlii_dataout : STD_LOGIC; + SIGNAL wire_nl10lOlii_w_lg_dataout58916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lOlil_dataout : STD_LOGIC; + SIGNAL wire_nl10lOliO_dataout : STD_LOGIC; + SIGNAL wire_nl10lOO_dataout : STD_LOGIC; + SIGNAL wire_nl10lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10O010i_dataout : STD_LOGIC; + SIGNAL wire_nl10O010l_dataout : STD_LOGIC; + SIGNAL wire_nl10O010O_dataout : STD_LOGIC; + SIGNAL wire_nl10O011i_dataout : STD_LOGIC; + SIGNAL wire_nl10O011O_dataout : STD_LOGIC; + SIGNAL wire_nl10O01i_dataout : STD_LOGIC; + SIGNAL wire_nl10O01ii_dataout : STD_LOGIC; + SIGNAL wire_nl10O01il_dataout : STD_LOGIC; + SIGNAL wire_nl10O01iO_dataout : STD_LOGIC; + SIGNAL wire_nl10O01li_dataout : STD_LOGIC; + SIGNAL wire_nl10O01ll_dataout : STD_LOGIC; + SIGNAL wire_nl10O01lO_dataout : STD_LOGIC; + SIGNAL wire_nl10O0i_dataout : STD_LOGIC; + SIGNAL wire_nl10O0l_dataout : STD_LOGIC; + SIGNAL wire_nl10O0O_dataout : STD_LOGIC; + SIGNAL wire_nl10O0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl10O0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl10O100O_dataout : STD_LOGIC; + SIGNAL wire_nl10O10i_dataout : STD_LOGIC; + SIGNAL wire_nl10O10ii_dataout : STD_LOGIC; + SIGNAL wire_nl10O10il_dataout : STD_LOGIC; + SIGNAL wire_nl10O10iO_dataout : STD_LOGIC; + SIGNAL wire_nl10O10l_dataout : STD_LOGIC; + SIGNAL wire_nl10O10li_dataout : STD_LOGIC; + SIGNAL wire_nl10O10ll_dataout : STD_LOGIC; + SIGNAL wire_nl10O10lO_dataout : STD_LOGIC; + SIGNAL wire_nl10O10O_dataout : STD_LOGIC; + SIGNAL wire_nl10O10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10O10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10O10OO_dataout : STD_LOGIC; + SIGNAL wire_nl10O11i_dataout : STD_LOGIC; + SIGNAL wire_nl10O11l_dataout : STD_LOGIC; + SIGNAL wire_nl10O11O_dataout : STD_LOGIC; + SIGNAL wire_nl10O1i_dataout : STD_LOGIC; + SIGNAL wire_nl10O1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl10O1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl10O1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl10O1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl10O1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl10O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl10O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10O1iii_dataout : STD_LOGIC; + SIGNAL wire_nl10O1iil_dataout : STD_LOGIC; + SIGNAL wire_nl10O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1ili_dataout : STD_LOGIC; + SIGNAL wire_nl10O1ill_dataout : STD_LOGIC; + SIGNAL wire_nl10O1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl10O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl10O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1l_dataout : STD_LOGIC; + SIGNAL wire_nl10O1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl10O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl10O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl10O1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl10O1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl10O1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl10O1li_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lii_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lil_dataout : STD_LOGIC; + SIGNAL wire_nl10O1liO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lli_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lll_dataout : STD_LOGIC; + SIGNAL wire_nl10O1llO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl10O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1O_dataout : STD_LOGIC; + SIGNAL wire_nl10O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl10O1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl10O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl10O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl10O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl10O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl10O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl10O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl10O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl10O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl10O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl10O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi00i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi00l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi00O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi01i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi01l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi01O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0il_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0li_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi10i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi10l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi10O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi11i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi11l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi11O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1il_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1li_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oii_dataout : STD_LOGIC; + SIGNAL wire_nl10Oii0i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oii0l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oii1i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oii1l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oii1O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oiiii_dataout : STD_LOGIC; + SIGNAL wire_nl10Oiiil_dataout : STD_LOGIC; + SIGNAL wire_nl10OiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oiili_dataout : STD_LOGIC; + SIGNAL wire_nl10Oiill_dataout : STD_LOGIC; + SIGNAL wire_nl10OiilO_dataout : STD_LOGIC; + SIGNAL wire_nl10OiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oil_dataout : STD_LOGIC; + SIGNAL wire_nl10Oil0i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oil0l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oil0O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oil1i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oil1l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oil1O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oilii_dataout : STD_LOGIC; + SIGNAL wire_nl10Oilil_dataout : STD_LOGIC; + SIGNAL wire_nl10OiliO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oilli_dataout : STD_LOGIC; + SIGNAL wire_nl10Oilll_dataout : STD_LOGIC; + SIGNAL wire_nl10OillO_dataout : STD_LOGIC; + SIGNAL wire_nl10OilOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OilOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OilOO_dataout : STD_LOGIC; + SIGNAL wire_nl10OiO_dataout : STD_LOGIC; + SIGNAL wire_nl10OiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl10OiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl10OiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl10OiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl10OiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl10OiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOii_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOil_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOli_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOll_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol00l_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol00O_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0il_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0li_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol10l_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol10O_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol11i_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1li_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oli_dataout : STD_LOGIC; + SIGNAL wire_nl10Oli0i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oli0O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oli1i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oli1l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oli1O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oliii_dataout : STD_LOGIC; + SIGNAL wire_nl10Oliil_dataout : STD_LOGIC; + SIGNAL wire_nl10OliiO_dataout : STD_LOGIC; + SIGNAL wire_nl10Olili_dataout : STD_LOGIC; + SIGNAL wire_nl10Olill_dataout : STD_LOGIC; + SIGNAL wire_nl10OlilO_dataout : STD_LOGIC; + SIGNAL wire_nl10OliOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OliOO_dataout : STD_LOGIC; + SIGNAL wire_nl10Oll_dataout : STD_LOGIC; + SIGNAL wire_nl10Oll0i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oll0l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oll0O_dataout : STD_LOGIC; + SIGNAL wire_nl10Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nl10Oll1l_dataout : STD_LOGIC; + SIGNAL wire_nl10Oll1O_dataout : STD_LOGIC; + SIGNAL wire_nl10Ollii_dataout : STD_LOGIC; + SIGNAL wire_nl10Ollil_dataout : STD_LOGIC; + SIGNAL wire_nl10OlliO_dataout : STD_LOGIC; + SIGNAL wire_nl10Ollli_dataout : STD_LOGIC; + SIGNAL wire_nl10Ollll_dataout : STD_LOGIC; + SIGNAL wire_nl10OlllO_dataout : STD_LOGIC; + SIGNAL wire_nl10OllOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OllOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OllOO_dataout : STD_LOGIC; + SIGNAL wire_nl10OlO_dataout : STD_LOGIC; + SIGNAL wire_nl10OlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl10OlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl10OlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl10OlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl10OlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl10OlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOii_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOil_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOli_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOll_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl10OO00i_dataout : STD_LOGIC; + SIGNAL wire_nl10OO00l_dataout : STD_LOGIC; + SIGNAL wire_nl10OO00O_dataout : STD_LOGIC; + SIGNAL wire_nl10OO01i_dataout : STD_LOGIC; + SIGNAL wire_nl10OO01l_dataout : STD_LOGIC; + SIGNAL wire_nl10OO01O_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0il_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0li_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10OO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl10OO10i_dataout : STD_LOGIC; + SIGNAL wire_nl10OO10l_dataout : STD_LOGIC; + SIGNAL wire_nl10OO10O_dataout : STD_LOGIC; + SIGNAL wire_nl10OO11i_dataout : STD_LOGIC; + SIGNAL wire_nl10OO11l_dataout : STD_LOGIC; + SIGNAL wire_nl10OO11O_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1il_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1li_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl10OO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl10OOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl10OOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl10OOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl10OOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl10OOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl10OOiii_dataout : STD_LOGIC; + SIGNAL wire_nl10OOiil_dataout : STD_LOGIC; + SIGNAL wire_nl10OOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOili_dataout : STD_LOGIC; + SIGNAL wire_nl10OOill_dataout : STD_LOGIC; + SIGNAL wire_nl10OOilO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl10OOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl10OOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl10OOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl10OOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl10OOlii_dataout : STD_LOGIC; + SIGNAL wire_nl10OOlil_dataout : STD_LOGIC; + SIGNAL wire_nl10OOliO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOlli_dataout : STD_LOGIC; + SIGNAL wire_nl10OOlll_dataout : STD_LOGIC; + SIGNAL wire_nl10OOllO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl10OOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl10OOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl10OOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl10OOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl10OOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOii_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOil_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOli_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOll_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl10OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl110000i_dataout : STD_LOGIC; + SIGNAL wire_nl110000l_dataout : STD_LOGIC; + SIGNAL wire_nl110000O_dataout : STD_LOGIC; + SIGNAL wire_nl110001i_dataout : STD_LOGIC; + SIGNAL wire_nl110001l_dataout : STD_LOGIC; + SIGNAL wire_nl110001O_dataout : STD_LOGIC; + SIGNAL wire_nl11000ii_dataout : STD_LOGIC; + SIGNAL wire_nl11000il_dataout : STD_LOGIC; + SIGNAL wire_nl11000iO_dataout : STD_LOGIC; + SIGNAL wire_nl11000l_dataout : STD_LOGIC; + SIGNAL wire_nl11000li_dataout : STD_LOGIC; + SIGNAL wire_nl11000ll_dataout : STD_LOGIC; + SIGNAL wire_nl11000lO_dataout : STD_LOGIC; + SIGNAL wire_nl11000O_dataout : STD_LOGIC; + SIGNAL wire_nl11000Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11000Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11000OO_dataout : STD_LOGIC; + SIGNAL wire_nl110010i_dataout : STD_LOGIC; + SIGNAL wire_nl110010l_dataout : STD_LOGIC; + SIGNAL wire_nl110010O_dataout : STD_LOGIC; + SIGNAL wire_nl110011i_dataout : STD_LOGIC; + SIGNAL wire_nl110011l_dataout : STD_LOGIC; + SIGNAL wire_nl110011O_dataout : STD_LOGIC; + SIGNAL wire_nl11001ii_dataout : STD_LOGIC; + SIGNAL wire_nl11001il_dataout : STD_LOGIC; + SIGNAL wire_nl11001iO_dataout : STD_LOGIC; + SIGNAL wire_nl11001l_dataout : STD_LOGIC; + SIGNAL wire_nl11001li_dataout : STD_LOGIC; + SIGNAL wire_nl11001ll_dataout : STD_LOGIC; + SIGNAL wire_nl11001lO_dataout : STD_LOGIC; + SIGNAL wire_nl11001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11001Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11001OO_dataout : STD_LOGIC; + SIGNAL wire_nl1100i_dataout : STD_LOGIC; + SIGNAL wire_nl1100i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1100i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1100i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1100i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1100i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1100i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1100iii_dataout : STD_LOGIC; + SIGNAL wire_nl1100iil_dataout : STD_LOGIC; + SIGNAL wire_nl1100iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1100il_dataout : STD_LOGIC; + SIGNAL wire_nl1100ili_dataout : STD_LOGIC; + SIGNAL wire_nl1100ill_dataout : STD_LOGIC; + SIGNAL wire_nl1100ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1100iO_dataout : STD_LOGIC; + SIGNAL wire_nl1100iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1100iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1100iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1100l_dataout : STD_LOGIC; + SIGNAL wire_nl1100l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1100l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1100l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1100l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1100l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1100l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1100li_dataout : STD_LOGIC; + SIGNAL wire_nl1100lii_dataout : STD_LOGIC; + SIGNAL wire_nl1100lil_dataout : STD_LOGIC; + SIGNAL wire_nl1100liO_dataout : STD_LOGIC; + SIGNAL wire_nl1100lll_dataout : STD_LOGIC; + SIGNAL wire_nl1100llO_dataout : STD_LOGIC; + SIGNAL wire_nl1100lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1100lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1100lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1100O_dataout : STD_LOGIC; + SIGNAL wire_nl1100O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1100O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1100O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1100O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1100O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1100O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1100Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1100Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1100OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1100Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1100Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1100OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1100OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1100OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1100OOO_dataout : STD_LOGIC; + SIGNAL wire_nl11010l_dataout : STD_LOGIC; + SIGNAL wire_nl11011i_dataout : STD_LOGIC; + SIGNAL wire_nl11011l_dataout : STD_LOGIC; + SIGNAL wire_nl1101i_dataout : STD_LOGIC; + SIGNAL wire_nl1101il_dataout : STD_LOGIC; + SIGNAL wire_nl1101iO_dataout : STD_LOGIC; + SIGNAL wire_nl1101l_dataout : STD_LOGIC; + SIGNAL wire_nl1101lii_dataout : STD_LOGIC; + SIGNAL wire_nl1101lil_dataout : STD_LOGIC; + SIGNAL wire_nl1101liO_dataout : STD_LOGIC; + SIGNAL wire_nl1101lli_dataout : STD_LOGIC; + SIGNAL wire_nl1101lll_dataout : STD_LOGIC; + SIGNAL wire_nl1101llO_dataout : STD_LOGIC; + SIGNAL wire_nl1101lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1101lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1101lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1101O_dataout : STD_LOGIC; + SIGNAL wire_nl1101O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1101O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1101O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1101O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1101O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1101O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1101Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1101Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1101OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1101Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1101Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1101OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1101OO_dataout : STD_LOGIC; + SIGNAL wire_nl1101OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1101OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1101OOO_dataout : STD_LOGIC; + SIGNAL wire_nl110i00i_dataout : STD_LOGIC; + SIGNAL wire_nl110i00l_dataout : STD_LOGIC; + SIGNAL wire_nl110i00O_dataout : STD_LOGIC; + SIGNAL wire_nl110i01i_dataout : STD_LOGIC; + SIGNAL wire_nl110i01l_dataout : STD_LOGIC; + SIGNAL wire_nl110i01O_dataout : STD_LOGIC; + SIGNAL wire_nl110i0il_dataout : STD_LOGIC; + SIGNAL wire_nl110i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl110i0li_dataout : STD_LOGIC; + SIGNAL wire_nl110i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl110i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl110i0O_dataout : STD_LOGIC; + SIGNAL wire_nl110i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl110i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl110i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl110i10i_dataout : STD_LOGIC; + SIGNAL wire_nl110i10l_dataout : STD_LOGIC; + SIGNAL wire_nl110i10O_dataout : STD_LOGIC; + SIGNAL wire_nl110i11l_dataout : STD_LOGIC; + SIGNAL wire_nl110i11O_dataout : STD_LOGIC; + SIGNAL wire_nl110i1i_dataout : STD_LOGIC; + SIGNAL wire_nl110i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl110i1il_dataout : STD_LOGIC; + SIGNAL wire_nl110i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl110i1l_dataout : STD_LOGIC; + SIGNAL wire_nl110i1li_dataout : STD_LOGIC; + SIGNAL wire_nl110i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl110i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl110i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl110i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl110i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl110ii_dataout : STD_LOGIC; + SIGNAL wire_nl110ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl110ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl110ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl110ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl110ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl110iiii_dataout : STD_LOGIC; + SIGNAL wire_nl110iiil_dataout : STD_LOGIC; + SIGNAL wire_nl110iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl110iil_dataout : STD_LOGIC; + SIGNAL wire_nl110iili_dataout : STD_LOGIC; + SIGNAL wire_nl110iill_dataout : STD_LOGIC; + SIGNAL wire_nl110iilO_dataout : STD_LOGIC; + SIGNAL wire_nl110iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl110iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl110iiOl_w_lg_dataout61343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl110iiOO_w_lg_dataout61345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110il_dataout : STD_LOGIC; + SIGNAL wire_nl110il0i_dataout : STD_LOGIC; + SIGNAL wire_nl110il0i_w_lg_dataout61353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110il0l_dataout : STD_LOGIC; + SIGNAL wire_nl110il0l_w_lg_dataout61355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110il0O_dataout : STD_LOGIC; + SIGNAL wire_nl110il0O_w_lg_dataout61357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110il1i_dataout : STD_LOGIC; + SIGNAL wire_nl110il1i_w_lg_dataout61347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110il1l_dataout : STD_LOGIC; + SIGNAL wire_nl110il1l_w_lg_dataout61349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110il1O_dataout : STD_LOGIC; + SIGNAL wire_nl110il1O_w_lg_dataout61351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110ili_dataout : STD_LOGIC; + SIGNAL wire_nl110ilii_dataout : STD_LOGIC; + SIGNAL wire_nl110ilii_w_lg_dataout61359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110ilil_dataout : STD_LOGIC; + SIGNAL wire_nl110ilil_w_lg_dataout61361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110iliO_dataout : STD_LOGIC; + SIGNAL wire_nl110iliO_w_lg_dataout61363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110illi_dataout : STD_LOGIC; + SIGNAL wire_nl110illi_w_lg_dataout61365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110illl_dataout : STD_LOGIC; + SIGNAL wire_nl110illO_dataout : STD_LOGIC; + SIGNAL wire_nl110ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl110ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl110ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl110iO_dataout : STD_LOGIC; + SIGNAL wire_nl110iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl110iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl110iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl110iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl110iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl110iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl110iOi_dataout : STD_LOGIC; + SIGNAL wire_nl110iOii_dataout : STD_LOGIC; + SIGNAL wire_nl110iOl_dataout : STD_LOGIC; + SIGNAL wire_nl110iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl110iOlO_w_lg_dataout61198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl110iOOi_w_lg_dataout61200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl110iOOl_w_lg_dataout61202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl110iOOO_w_lg_dataout61204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l00i_dataout : STD_LOGIC; + SIGNAL wire_nl110l00i_w_lg_dataout61091w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l00l_dataout : STD_LOGIC; + SIGNAL wire_nl110l00l_w_lg_dataout61093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l00O_dataout : STD_LOGIC; + SIGNAL wire_nl110l00O_w_lg_dataout61095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l01i_dataout : STD_LOGIC; + SIGNAL wire_nl110l01i_w_lg_dataout61085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l01l_dataout : STD_LOGIC; + SIGNAL wire_nl110l01l_w_lg_dataout61087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l01O_dataout : STD_LOGIC; + SIGNAL wire_nl110l01O_w_lg_dataout61089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl110l0ii_w_lg_dataout61097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l0il_dataout : STD_LOGIC; + SIGNAL wire_nl110l0il_w_lg_dataout61099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl110l0iO_w_lg_dataout61101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l0li_dataout : STD_LOGIC; + SIGNAL wire_nl110l0li_w_lg_dataout61103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl110l0ll_w_lg_dataout61105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl110l0O_dataout : STD_LOGIC; + SIGNAL wire_nl110l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl110l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl110l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl110l10i_dataout : STD_LOGIC; + SIGNAL wire_nl110l10i_w_lg_dataout61212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l10l_dataout : STD_LOGIC; + SIGNAL wire_nl110l10O_dataout : STD_LOGIC; + SIGNAL wire_nl110l11i_dataout : STD_LOGIC; + SIGNAL wire_nl110l11i_w_lg_dataout61206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l11l_dataout : STD_LOGIC; + SIGNAL wire_nl110l11l_w_lg_dataout61208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l11O_dataout : STD_LOGIC; + SIGNAL wire_nl110l11O_w_lg_dataout61210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110l1i_dataout : STD_LOGIC; + SIGNAL wire_nl110l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl110l1il_dataout : STD_LOGIC; + SIGNAL wire_nl110l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl110l1l_dataout : STD_LOGIC; + SIGNAL wire_nl110l1li_dataout : STD_LOGIC; + SIGNAL wire_nl110l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl110l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl110l1O_dataout : STD_LOGIC; + SIGNAL wire_nl110l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl110l1OO_w_lg_dataout61083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110li_dataout : STD_LOGIC; + SIGNAL wire_nl110li0i_dataout : STD_LOGIC; + SIGNAL wire_nl110li0l_dataout : STD_LOGIC; + SIGNAL wire_nl110li0O_dataout : STD_LOGIC; + SIGNAL wire_nl110li1i_dataout : STD_LOGIC; + SIGNAL wire_nl110li1l_dataout : STD_LOGIC; + SIGNAL wire_nl110li1O_dataout : STD_LOGIC; + SIGNAL wire_nl110liii_dataout : STD_LOGIC; + SIGNAL wire_nl110liil_dataout : STD_LOGIC; + SIGNAL wire_nl110liO_dataout : STD_LOGIC; + SIGNAL wire_nl110liOi_dataout : STD_LOGIC; + SIGNAL wire_nl110liOi_w_lg_dataout60992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110liOl_dataout : STD_LOGIC; + SIGNAL wire_nl110liOl_w_lg_dataout60994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110liOO_dataout : STD_LOGIC; + SIGNAL wire_nl110liOO_w_lg_dataout60996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110ll_dataout : STD_LOGIC; + SIGNAL wire_nl110ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl110ll0i_w_lg_dataout61004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl110ll0l_w_lg_dataout61006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl110ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl110ll1i_w_lg_dataout60998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl110ll1l_w_lg_dataout61000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl110ll1O_w_lg_dataout61002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lli_dataout : STD_LOGIC; + SIGNAL wire_nl110llii_dataout : STD_LOGIC; + SIGNAL wire_nl110llil_dataout : STD_LOGIC; + SIGNAL wire_nl110lliO_dataout : STD_LOGIC; + SIGNAL wire_nl110llli_dataout : STD_LOGIC; + SIGNAL wire_nl110llll_dataout : STD_LOGIC; + SIGNAL wire_nl110lllO_dataout : STD_LOGIC; + SIGNAL wire_nl110llOi_dataout : STD_LOGIC; + SIGNAL wire_nl110lO_dataout : STD_LOGIC; + SIGNAL wire_nl110lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl110lO0i_w_lg_dataout61307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl110lO0l_w_lg_dataout61309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl110lO0O_w_lg_dataout61311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl110lO1i_w_lg_dataout61301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl110lO1l_w_lg_dataout61303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl110lO1O_w_lg_dataout61305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lOii_dataout : STD_LOGIC; + SIGNAL wire_nl110lOii_w_lg_dataout61313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lOil_dataout : STD_LOGIC; + SIGNAL wire_nl110lOil_w_lg_dataout61315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl110lOiO_w_lg_dataout61317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lOl_dataout : STD_LOGIC; + SIGNAL wire_nl110lOli_dataout : STD_LOGIC; + SIGNAL wire_nl110lOli_w_lg_dataout61319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lOll_dataout : STD_LOGIC; + SIGNAL wire_nl110lOll_w_lg_dataout61321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl110lOlO_w_lg_dataout61323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl110lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl110lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl110O00i_dataout : STD_LOGIC; + SIGNAL wire_nl110O00i_w_lg_dataout60903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O00l_dataout : STD_LOGIC; + SIGNAL wire_nl110O00l_w_lg_dataout60905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O00O_dataout : STD_LOGIC; + SIGNAL wire_nl110O00O_w_lg_dataout60907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O01i_dataout : STD_LOGIC; + SIGNAL wire_nl110O01i_w_lg_dataout60897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O01l_dataout : STD_LOGIC; + SIGNAL wire_nl110O01l_w_lg_dataout60899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O01O_dataout : STD_LOGIC; + SIGNAL wire_nl110O01O_w_lg_dataout60901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl110O0il_dataout : STD_LOGIC; + SIGNAL wire_nl110O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl110O0li_dataout : STD_LOGIC; + SIGNAL wire_nl110O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl110O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl110O0O_dataout : STD_LOGIC; + SIGNAL wire_nl110O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl110O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl110O10i_dataout : STD_LOGIC; + SIGNAL wire_nl110O10l_dataout : STD_LOGIC; + SIGNAL wire_nl110O10O_dataout : STD_LOGIC; + SIGNAL wire_nl110O11i_dataout : STD_LOGIC; + SIGNAL wire_nl110O11l_dataout : STD_LOGIC; + SIGNAL wire_nl110O11O_dataout : STD_LOGIC; + SIGNAL wire_nl110O1i_dataout : STD_LOGIC; + SIGNAL wire_nl110O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl110O1il_dataout : STD_LOGIC; + SIGNAL wire_nl110O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl110O1O_dataout : STD_LOGIC; + SIGNAL wire_nl110O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl110O1Ol_w_lg_dataout60893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl110O1OO_w_lg_dataout60895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl110Oii_dataout : STD_LOGIC; + SIGNAL wire_nl110OiO_dataout : STD_LOGIC; + SIGNAL wire_nl110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl110Oli_dataout : STD_LOGIC; + SIGNAL wire_nl110Oll_dataout : STD_LOGIC; + SIGNAL wire_nl110OO_dataout : STD_LOGIC; + SIGNAL wire_nl110OOl_dataout : STD_LOGIC; + SIGNAL wire_nl11100i_dataout : STD_LOGIC; + SIGNAL wire_nl11100O_dataout : STD_LOGIC; + SIGNAL wire_nl111011l_dataout : STD_LOGIC; + SIGNAL wire_nl11101li_dataout : STD_LOGIC; + SIGNAL wire_nl11101ll_dataout : STD_LOGIC; + SIGNAL wire_nl1110i_dataout : STD_LOGIC; + SIGNAL wire_nl1110il_dataout : STD_LOGIC; + SIGNAL wire_nl1110l_dataout : STD_LOGIC; + SIGNAL wire_nl1110ll_dataout : STD_LOGIC; + SIGNAL wire_nl1110lO_dataout : STD_LOGIC; + SIGNAL wire_nl1110O_dataout : STD_LOGIC; + SIGNAL wire_nl1110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1110OO_dataout : STD_LOGIC; + SIGNAL wire_nl111100i_dataout : STD_LOGIC; + SIGNAL wire_nl111100l_dataout : STD_LOGIC; + SIGNAL wire_nl111100O_dataout : STD_LOGIC; + SIGNAL wire_nl111101i_dataout : STD_LOGIC; + SIGNAL wire_nl111101l_dataout : STD_LOGIC; + SIGNAL wire_nl111101O_dataout : STD_LOGIC; + SIGNAL wire_nl11110i_dataout : STD_LOGIC; + SIGNAL wire_nl11110ii_dataout : STD_LOGIC; + SIGNAL wire_nl11110il_dataout : STD_LOGIC; + SIGNAL wire_nl11110iO_dataout : STD_LOGIC; + SIGNAL wire_nl11110li_dataout : STD_LOGIC; + SIGNAL wire_nl11110ll_dataout : STD_LOGIC; + SIGNAL wire_nl11110lO_dataout : STD_LOGIC; + SIGNAL wire_nl11110O_dataout : STD_LOGIC; + SIGNAL wire_nl11110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11110OO_dataout : STD_LOGIC; + SIGNAL wire_nl111110i_dataout : STD_LOGIC; + SIGNAL wire_nl111110l_dataout : STD_LOGIC; + SIGNAL wire_nl111110O_dataout : STD_LOGIC; + SIGNAL wire_nl111111i_dataout : STD_LOGIC; + SIGNAL wire_nl111111l_dataout : STD_LOGIC; + SIGNAL wire_nl111111O_dataout : STD_LOGIC; + SIGNAL wire_nl11111ii_dataout : STD_LOGIC; + SIGNAL wire_nl11111il_dataout : STD_LOGIC; + SIGNAL wire_nl11111iO_dataout : STD_LOGIC; + SIGNAL wire_nl11111li_dataout : STD_LOGIC; + SIGNAL wire_nl11111ll_dataout : STD_LOGIC; + SIGNAL wire_nl11111lO_dataout : STD_LOGIC; + SIGNAL wire_nl11111O_dataout : STD_LOGIC; + SIGNAL wire_nl11111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11111OO_dataout : STD_LOGIC; + SIGNAL wire_nl1111i_dataout : STD_LOGIC; + SIGNAL wire_nl1111i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1111i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1111i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1111i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1111i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1111i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1111ii_dataout : STD_LOGIC; + SIGNAL wire_nl1111iii_dataout : STD_LOGIC; + SIGNAL wire_nl1111iil_dataout : STD_LOGIC; + SIGNAL wire_nl1111iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1111il_dataout : STD_LOGIC; + SIGNAL wire_nl1111ili_dataout : STD_LOGIC; + SIGNAL wire_nl1111ill_dataout : STD_LOGIC; + SIGNAL wire_nl1111ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1111iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1111iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1111iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1111l_dataout : STD_LOGIC; + SIGNAL wire_nl1111l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1111l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1111l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1111l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1111l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1111l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1111lii_dataout : STD_LOGIC; + SIGNAL wire_nl1111lil_dataout : STD_LOGIC; + SIGNAL wire_nl1111liO_dataout : STD_LOGIC; + SIGNAL wire_nl1111ll_dataout : STD_LOGIC; + SIGNAL wire_nl1111O_dataout : STD_LOGIC; + SIGNAL wire_nl1111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1111OO_dataout : STD_LOGIC; + SIGNAL wire_nl111i00i_dataout : STD_LOGIC; + SIGNAL wire_nl111i00l_dataout : STD_LOGIC; + SIGNAL wire_nl111i00O_dataout : STD_LOGIC; + SIGNAL wire_nl111i01i_dataout : STD_LOGIC; + SIGNAL wire_nl111i01l_dataout : STD_LOGIC; + SIGNAL wire_nl111i01O_dataout : STD_LOGIC; + SIGNAL wire_nl111i0i_dataout : STD_LOGIC; + SIGNAL wire_nl111i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl111i0il_dataout : STD_LOGIC; + SIGNAL wire_nl111i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl111i0li_dataout : STD_LOGIC; + SIGNAL wire_nl111i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl111i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl111i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl111i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl111i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl111i1i_dataout : STD_LOGIC; + SIGNAL wire_nl111i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl111i1li_dataout : STD_LOGIC; + SIGNAL wire_nl111i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl111i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl111i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl111i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl111i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl111ii_dataout : STD_LOGIC; + SIGNAL wire_nl111ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl111ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl111ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl111ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl111ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl111ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl111iii_dataout : STD_LOGIC; + SIGNAL wire_nl111iiii_dataout : STD_LOGIC; + SIGNAL wire_nl111iiil_dataout : STD_LOGIC; + SIGNAL wire_nl111iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl111iil_dataout : STD_LOGIC; + SIGNAL wire_nl111iili_dataout : STD_LOGIC; + SIGNAL wire_nl111iill_dataout : STD_LOGIC; + SIGNAL wire_nl111iilO_dataout : STD_LOGIC; + SIGNAL wire_nl111iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl111iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl111iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl111il_dataout : STD_LOGIC; + SIGNAL wire_nl111il0i_dataout : STD_LOGIC; + SIGNAL wire_nl111il0l_dataout : STD_LOGIC; + SIGNAL wire_nl111il0O_dataout : STD_LOGIC; + SIGNAL wire_nl111il1i_dataout : STD_LOGIC; + SIGNAL wire_nl111il1l_dataout : STD_LOGIC; + SIGNAL wire_nl111il1O_dataout : STD_LOGIC; + SIGNAL wire_nl111ilii_dataout : STD_LOGIC; + SIGNAL wire_nl111ilil_dataout : STD_LOGIC; + SIGNAL wire_nl111iliO_dataout : STD_LOGIC; + SIGNAL wire_nl111illi_dataout : STD_LOGIC; + SIGNAL wire_nl111illl_dataout : STD_LOGIC; + SIGNAL wire_nl111illO_dataout : STD_LOGIC; + SIGNAL wire_nl111ilO_dataout : STD_LOGIC; + SIGNAL wire_nl111ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl111ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl111ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl111iO_dataout : STD_LOGIC; + SIGNAL wire_nl111iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl111iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl111iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl111iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl111iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl111iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl111iOii_dataout : STD_LOGIC; + SIGNAL wire_nl111iOil_dataout : STD_LOGIC; + SIGNAL wire_nl111iOl_dataout : STD_LOGIC; + SIGNAL wire_nl111iOll_dataout : STD_LOGIC; + SIGNAL wire_nl111iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl111l0i_dataout : STD_LOGIC; + SIGNAL wire_nl111l0l_dataout : STD_LOGIC; + SIGNAL wire_nl111l1i_dataout : STD_LOGIC; + SIGNAL wire_nl111li_dataout : STD_LOGIC; + SIGNAL wire_nl111lii_dataout : STD_LOGIC; + SIGNAL wire_nl111lil_dataout : STD_LOGIC; + SIGNAL wire_nl111liO_dataout : STD_LOGIC; + SIGNAL wire_nl111ll_dataout : STD_LOGIC; + SIGNAL wire_nl111ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl111ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl111ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl111ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl111llii_dataout : STD_LOGIC; + SIGNAL wire_nl111llil_dataout : STD_LOGIC; + SIGNAL wire_nl111lliO_dataout : STD_LOGIC; + SIGNAL wire_nl111llli_dataout : STD_LOGIC; + SIGNAL wire_nl111llll_dataout : STD_LOGIC; + SIGNAL wire_nl111lllO_dataout : STD_LOGIC; + SIGNAL wire_nl111llO_dataout : STD_LOGIC; + SIGNAL wire_nl111llOi_dataout : STD_LOGIC; + SIGNAL wire_nl111llOl_dataout : STD_LOGIC; + SIGNAL wire_nl111llOO_dataout : STD_LOGIC; + SIGNAL wire_nl111lO_dataout : STD_LOGIC; + SIGNAL wire_nl111lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl111lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl111lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl111lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl111lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl111lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl111lOii_dataout : STD_LOGIC; + SIGNAL wire_nl111lOil_dataout : STD_LOGIC; + SIGNAL wire_nl111lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl111lOli_dataout : STD_LOGIC; + SIGNAL wire_nl111lOll_dataout : STD_LOGIC; + SIGNAL wire_nl111lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl111lOO_dataout : STD_LOGIC; + SIGNAL wire_nl111lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl111lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl111lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl111O00i_dataout : STD_LOGIC; + SIGNAL wire_nl111O00l_dataout : STD_LOGIC; + SIGNAL wire_nl111O00O_dataout : STD_LOGIC; + SIGNAL wire_nl111O01i_dataout : STD_LOGIC; + SIGNAL wire_nl111O01l_dataout : STD_LOGIC; + SIGNAL wire_nl111O01O_dataout : STD_LOGIC; + SIGNAL wire_nl111O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl111O0il_dataout : STD_LOGIC; + SIGNAL wire_nl111O0l_dataout : STD_LOGIC; + SIGNAL wire_nl111O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl111O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl111O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl111O10i_dataout : STD_LOGIC; + SIGNAL wire_nl111O10l_dataout : STD_LOGIC; + SIGNAL wire_nl111O10O_dataout : STD_LOGIC; + SIGNAL wire_nl111O11i_dataout : STD_LOGIC; + SIGNAL wire_nl111O11l_dataout : STD_LOGIC; + SIGNAL wire_nl111O11O_dataout : STD_LOGIC; + SIGNAL wire_nl111O1i_dataout : STD_LOGIC; + SIGNAL wire_nl111O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl111O1il_dataout : STD_LOGIC; + SIGNAL wire_nl111O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl111O1li_dataout : STD_LOGIC; + SIGNAL wire_nl111O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl111O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl111O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl111O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl111O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl111Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl111Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl111Oii_dataout : STD_LOGIC; + SIGNAL wire_nl111Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl111OilO_dataout : STD_LOGIC; + SIGNAL wire_nl111OiO_dataout : STD_LOGIC; + SIGNAL wire_nl111OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl111OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl111OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl111Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl111Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl111Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl111Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl111Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl111Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl111Olii_dataout : STD_LOGIC; + SIGNAL wire_nl111Olil_dataout : STD_LOGIC; + SIGNAL wire_nl111OliO_dataout : STD_LOGIC; + SIGNAL wire_nl111Olli_dataout : STD_LOGIC; + SIGNAL wire_nl111Olll_dataout : STD_LOGIC; + SIGNAL wire_nl111OlO_dataout : STD_LOGIC; + SIGNAL wire_nl111OO_dataout : STD_LOGIC; + SIGNAL wire_nl111OOi_dataout : STD_LOGIC; + SIGNAL wire_nl111OOO_dataout : STD_LOGIC; + SIGNAL wire_nl11i000i_dataout : STD_LOGIC; + SIGNAL wire_nl11i000l_dataout : STD_LOGIC; + SIGNAL wire_nl11i000O_dataout : STD_LOGIC; + SIGNAL wire_nl11i001i_dataout : STD_LOGIC; + SIGNAL wire_nl11i001l_dataout : STD_LOGIC; + SIGNAL wire_nl11i001O_dataout : STD_LOGIC; + SIGNAL wire_nl11i00i_dataout : STD_LOGIC; + SIGNAL wire_nl11i00ii_dataout : STD_LOGIC; + SIGNAL wire_nl11i00il_dataout : STD_LOGIC; + SIGNAL wire_nl11i00iO_dataout : STD_LOGIC; + SIGNAL wire_nl11i00li_dataout : STD_LOGIC; + SIGNAL wire_nl11i00ll_dataout : STD_LOGIC; + SIGNAL wire_nl11i00lO_dataout : STD_LOGIC; + SIGNAL wire_nl11i00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11i00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11i00OO_dataout : STD_LOGIC; + SIGNAL wire_nl11i010i_dataout : STD_LOGIC; + SIGNAL wire_nl11i010l_dataout : STD_LOGIC; + SIGNAL wire_nl11i010O_dataout : STD_LOGIC; + SIGNAL wire_nl11i011i_dataout : STD_LOGIC; + SIGNAL wire_nl11i011l_dataout : STD_LOGIC; + SIGNAL wire_nl11i011O_dataout : STD_LOGIC; + SIGNAL wire_nl11i01ii_dataout : STD_LOGIC; + SIGNAL wire_nl11i01il_dataout : STD_LOGIC; + SIGNAL wire_nl11i01iO_dataout : STD_LOGIC; + SIGNAL wire_nl11i01l_dataout : STD_LOGIC; + SIGNAL wire_nl11i01li_dataout : STD_LOGIC; + SIGNAL wire_nl11i01ll_dataout : STD_LOGIC; + SIGNAL wire_nl11i01lO_dataout : STD_LOGIC; + SIGNAL wire_nl11i01O_dataout : STD_LOGIC; + SIGNAL wire_nl11i01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11i01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11i01OO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0i_dataout : STD_LOGIC; + SIGNAL wire_nl11i0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl11i0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl11i0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl11i0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl11i0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl11i0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl11i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl11i0iii_dataout : STD_LOGIC; + SIGNAL wire_nl11i0iil_dataout : STD_LOGIC; + SIGNAL wire_nl11i0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0ili_dataout : STD_LOGIC; + SIGNAL wire_nl11i0ill_dataout : STD_LOGIC; + SIGNAL wire_nl11i0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl11i0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl11i0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0l_dataout : STD_LOGIC; + SIGNAL wire_nl11i0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl11i0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl11i0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl11i0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl11i0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl11i0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl11i0li_dataout : STD_LOGIC; + SIGNAL wire_nl11i0lii_dataout : STD_LOGIC; + SIGNAL wire_nl11i0lil_dataout : STD_LOGIC; + SIGNAL wire_nl11i0liO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11i0lli_dataout : STD_LOGIC; + SIGNAL wire_nl11i0lll_dataout : STD_LOGIC; + SIGNAL wire_nl11i0llO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl11i0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl11i0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0O_dataout : STD_LOGIC; + SIGNAL wire_nl11i0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl11i0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl11i0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl11i0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl11i0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl11i0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl11i0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl11i0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl11i0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl11i0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl11i0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11i0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl11i0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl11i0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl11i100i_dataout : STD_LOGIC; + SIGNAL wire_nl11i100l_dataout : STD_LOGIC; + SIGNAL wire_nl11i100O_dataout : STD_LOGIC; + SIGNAL wire_nl11i101i_dataout : STD_LOGIC; + SIGNAL wire_nl11i101l_dataout : STD_LOGIC; + SIGNAL wire_nl11i101O_dataout : STD_LOGIC; + SIGNAL wire_nl11i10ii_dataout : STD_LOGIC; + SIGNAL wire_nl11i10il_dataout : STD_LOGIC; + SIGNAL wire_nl11i10iO_dataout : STD_LOGIC; + SIGNAL wire_nl11i10li_dataout : STD_LOGIC; + SIGNAL wire_nl11i10ll_dataout : STD_LOGIC; + SIGNAL wire_nl11i10lO_dataout : STD_LOGIC; + SIGNAL wire_nl11i10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11i10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11i10OO_dataout : STD_LOGIC; + SIGNAL wire_nl11i11l_dataout : STD_LOGIC; + SIGNAL wire_nl11i11O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1i_dataout : STD_LOGIC; + SIGNAL wire_nl11i1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl11i1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl11i1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl11i1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl11i1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11i1iii_dataout : STD_LOGIC; + SIGNAL wire_nl11i1iil_dataout : STD_LOGIC; + SIGNAL wire_nl11i1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1ili_dataout : STD_LOGIC; + SIGNAL wire_nl11i1ill_dataout : STD_LOGIC; + SIGNAL wire_nl11i1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl11i1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl11i1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1l_dataout : STD_LOGIC; + SIGNAL wire_nl11i1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl11i1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl11i1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl11i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl11i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1lii_dataout : STD_LOGIC; + SIGNAL wire_nl11i1lil_dataout : STD_LOGIC; + SIGNAL wire_nl11i1liO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11i1lli_dataout : STD_LOGIC; + SIGNAL wire_nl11i1lll_dataout : STD_LOGIC; + SIGNAL wire_nl11i1llO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl11i1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl11i1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl11i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl11i1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl11i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl11i1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl11i1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl11i1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl11i1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11i1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl11i1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl11i1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl11i1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl11i1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl11i1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl11ii00i_dataout : STD_LOGIC; + SIGNAL wire_nl11ii00l_dataout : STD_LOGIC; + SIGNAL wire_nl11ii00O_dataout : STD_LOGIC; + SIGNAL wire_nl11ii01i_dataout : STD_LOGIC; + SIGNAL wire_nl11ii01l_dataout : STD_LOGIC; + SIGNAL wire_nl11ii01O_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0il_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0li_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11ii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11ii10i_dataout : STD_LOGIC; + SIGNAL wire_nl11ii10l_dataout : STD_LOGIC; + SIGNAL wire_nl11ii10O_dataout : STD_LOGIC; + SIGNAL wire_nl11ii11i_dataout : STD_LOGIC; + SIGNAL wire_nl11ii11l_dataout : STD_LOGIC; + SIGNAL wire_nl11ii11O_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1il_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1li_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11ii1OO_dataout : STD_LOGIC; + SIGNAL wire_nl11iii_dataout : STD_LOGIC; + SIGNAL wire_nl11iii0i_dataout : STD_LOGIC; + SIGNAL wire_nl11iii0l_dataout : STD_LOGIC; + SIGNAL wire_nl11iii0O_dataout : STD_LOGIC; + SIGNAL wire_nl11iii1i_dataout : STD_LOGIC; + SIGNAL wire_nl11iii1l_dataout : STD_LOGIC; + SIGNAL wire_nl11iii1O_dataout : STD_LOGIC; + SIGNAL wire_nl11iiii_dataout : STD_LOGIC; + SIGNAL wire_nl11iiiii_dataout : STD_LOGIC; + SIGNAL wire_nl11iiiil_dataout : STD_LOGIC; + SIGNAL wire_nl11iiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl11iiil_dataout : STD_LOGIC; + SIGNAL wire_nl11iiili_dataout : STD_LOGIC; + SIGNAL wire_nl11iiill_dataout : STD_LOGIC; + SIGNAL wire_nl11iiilO_dataout : STD_LOGIC; + SIGNAL wire_nl11iil_dataout : STD_LOGIC; + SIGNAL wire_nl11iili_dataout : STD_LOGIC; + SIGNAL wire_nl11iill_dataout : STD_LOGIC; + SIGNAL wire_nl11iilO_dataout : STD_LOGIC; + SIGNAL wire_nl11iiO_dataout : STD_LOGIC; + SIGNAL wire_nl11iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl11il0i_dataout : STD_LOGIC; + SIGNAL wire_nl11il1O_dataout : STD_LOGIC; + SIGNAL wire_nl11ili_dataout : STD_LOGIC; + SIGNAL wire_nl11ilil_dataout : STD_LOGIC; + SIGNAL wire_nl11illi_dataout : STD_LOGIC; + SIGNAL wire_nl11illO_dataout : STD_LOGIC; + SIGNAL wire_nl11ilO0i_dataout : STD_LOGIC; + SIGNAL wire_nl11ilO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11ilO0O_dataout : STD_LOGIC; + SIGNAL wire_nl11ilO1l_dataout : STD_LOGIC; + SIGNAL wire_nl11ilO1O_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOii_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOil_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOli_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOll_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl11iO00i_dataout : STD_LOGIC; + SIGNAL wire_nl11iO00l_dataout : STD_LOGIC; + SIGNAL wire_nl11iO00O_dataout : STD_LOGIC; + SIGNAL wire_nl11iO01i_dataout : STD_LOGIC; + SIGNAL wire_nl11iO01l_dataout : STD_LOGIC; + SIGNAL wire_nl11iO01O_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0il_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0li_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11iO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11iO10i_dataout : STD_LOGIC; + SIGNAL wire_nl11iO10l_dataout : STD_LOGIC; + SIGNAL wire_nl11iO10O_dataout : STD_LOGIC; + SIGNAL wire_nl11iO11i_dataout : STD_LOGIC; + SIGNAL wire_nl11iO11l_dataout : STD_LOGIC; + SIGNAL wire_nl11iO11O_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1il_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1li_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11iO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl11iOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl11iOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl11iOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl11iOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl11iOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl11iOiii_dataout : STD_LOGIC; + SIGNAL wire_nl11iOiil_dataout : STD_LOGIC; + SIGNAL wire_nl11iOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOil_dataout : STD_LOGIC; + SIGNAL wire_nl11iOili_dataout : STD_LOGIC; + SIGNAL wire_nl11iOill_dataout : STD_LOGIC; + SIGNAL wire_nl11iOilO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl11iOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl11iOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl11iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl11iOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl11iOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl11iOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl11iOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlii_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlil_dataout : STD_LOGIC; + SIGNAL wire_nl11iOliO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOll_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlli_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlll_dataout : STD_LOGIC; + SIGNAL wire_nl11iOllO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl11iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl11iOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11iOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl11iOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl11iOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl11iOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOii_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOil_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOli_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOll_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11iOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl11l00i_dataout : STD_LOGIC; + SIGNAL wire_nl11l00l_dataout : STD_LOGIC; + SIGNAL wire_nl11l01i_dataout : STD_LOGIC; + SIGNAL wire_nl11l0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl11l0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl11l0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl11l0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl11l0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl11l0iii_dataout : STD_LOGIC; + SIGNAL wire_nl11l0iil_dataout : STD_LOGIC; + SIGNAL wire_nl11l0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0ili_dataout : STD_LOGIC; + SIGNAL wire_nl11l0ill_dataout : STD_LOGIC; + SIGNAL wire_nl11l0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl11l0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl11l0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl11l0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl11l0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl11l0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl11l0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl11l0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl11l0lii_dataout : STD_LOGIC; + SIGNAL wire_nl11l0lil_dataout : STD_LOGIC; + SIGNAL wire_nl11l0liO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11l0lli_dataout : STD_LOGIC; + SIGNAL wire_nl11l0lll_dataout : STD_LOGIC; + SIGNAL wire_nl11l0llO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl11l0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl11l0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl11l0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl11l0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl11l0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl11l0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl11l0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl11l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11l0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl11l0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl11l0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl11l0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl11l0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl11l0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl11l0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl11l0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl11l100i_dataout : STD_LOGIC; + SIGNAL wire_nl11l100l_dataout : STD_LOGIC; + SIGNAL wire_nl11l100O_dataout : STD_LOGIC; + SIGNAL wire_nl11l101i_dataout : STD_LOGIC; + SIGNAL wire_nl11l101l_dataout : STD_LOGIC; + SIGNAL wire_nl11l101O_dataout : STD_LOGIC; + SIGNAL wire_nl11l10ii_dataout : STD_LOGIC; + SIGNAL wire_nl11l10il_dataout : STD_LOGIC; + SIGNAL wire_nl11l10iO_dataout : STD_LOGIC; + SIGNAL wire_nl11l10l_dataout : STD_LOGIC; + SIGNAL wire_nl11l10li_dataout : STD_LOGIC; + SIGNAL wire_nl11l10ll_dataout : STD_LOGIC; + SIGNAL wire_nl11l10lO_dataout : STD_LOGIC; + SIGNAL wire_nl11l10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11l10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11l10OO_dataout : STD_LOGIC; + SIGNAL wire_nl11l110i_dataout : STD_LOGIC; + SIGNAL wire_nl11l110l_dataout : STD_LOGIC; + SIGNAL wire_nl11l110O_dataout : STD_LOGIC; + SIGNAL wire_nl11l111i_dataout : STD_LOGIC; + SIGNAL wire_nl11l111l_dataout : STD_LOGIC; + SIGNAL wire_nl11l111O_dataout : STD_LOGIC; + SIGNAL wire_nl11l11i_dataout : STD_LOGIC; + SIGNAL wire_nl11l11ii_dataout : STD_LOGIC; + SIGNAL wire_nl11l11il_dataout : STD_LOGIC; + SIGNAL wire_nl11l11iO_dataout : STD_LOGIC; + SIGNAL wire_nl11l11li_dataout : STD_LOGIC; + SIGNAL wire_nl11l11ll_dataout : STD_LOGIC; + SIGNAL wire_nl11l11lO_dataout : STD_LOGIC; + SIGNAL wire_nl11l11O_dataout : STD_LOGIC; + SIGNAL wire_nl11l11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11l11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11l11OO_dataout : STD_LOGIC; + SIGNAL wire_nl11l1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl11l1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl11l1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl11l1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl11l1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl11l1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl11l1iii_dataout : STD_LOGIC; + SIGNAL wire_nl11l1iil_dataout : STD_LOGIC; + SIGNAL wire_nl11l1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl11l1il_dataout : STD_LOGIC; + SIGNAL wire_nl11l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl11l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11li00i_dataout : STD_LOGIC; + SIGNAL wire_nl11li00l_dataout : STD_LOGIC; + SIGNAL wire_nl11li00O_dataout : STD_LOGIC; + SIGNAL wire_nl11li01i_dataout : STD_LOGIC; + SIGNAL wire_nl11li01l_dataout : STD_LOGIC; + SIGNAL wire_nl11li01O_dataout : STD_LOGIC; + SIGNAL wire_nl11li0i_dataout : STD_LOGIC; + SIGNAL wire_nl11li0ii_dataout : STD_LOGIC; + SIGNAL wire_nl11li0il_dataout : STD_LOGIC; + SIGNAL wire_nl11li0iO_dataout : STD_LOGIC; + SIGNAL wire_nl11li0l_dataout : STD_LOGIC; + SIGNAL wire_nl11li0li_dataout : STD_LOGIC; + SIGNAL wire_nl11li0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11li0lO_dataout : STD_LOGIC; + SIGNAL wire_nl11li0O_dataout : STD_LOGIC; + SIGNAL wire_nl11li0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11li0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11li0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11li10i_dataout : STD_LOGIC; + SIGNAL wire_nl11li10l_dataout : STD_LOGIC; + SIGNAL wire_nl11li10O_dataout : STD_LOGIC; + SIGNAL wire_nl11li11i_dataout : STD_LOGIC; + SIGNAL wire_nl11li11l_dataout : STD_LOGIC; + SIGNAL wire_nl11li11O_dataout : STD_LOGIC; + SIGNAL wire_nl11li1i_dataout : STD_LOGIC; + SIGNAL wire_nl11li1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11li1il_dataout : STD_LOGIC; + SIGNAL wire_nl11li1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11li1l_dataout : STD_LOGIC; + SIGNAL wire_nl11li1li_dataout : STD_LOGIC; + SIGNAL wire_nl11li1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11li1lO_dataout : STD_LOGIC; + SIGNAL wire_nl11li1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11li1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11li1OO_dataout : STD_LOGIC; + SIGNAL wire_nl11lii0i_dataout : STD_LOGIC; + SIGNAL wire_nl11lii0l_dataout : STD_LOGIC; + SIGNAL wire_nl11lii0O_dataout : STD_LOGIC; + SIGNAL wire_nl11lii1i_dataout : STD_LOGIC; + SIGNAL wire_nl11lii1l_dataout : STD_LOGIC; + SIGNAL wire_nl11lii1O_dataout : STD_LOGIC; + SIGNAL wire_nl11liiii_dataout : STD_LOGIC; + SIGNAL wire_nl11liiil_dataout : STD_LOGIC; + SIGNAL wire_nl11liiiO_dataout : STD_LOGIC; + SIGNAL wire_nl11liili_dataout : STD_LOGIC; + SIGNAL wire_nl11liill_dataout : STD_LOGIC; + SIGNAL wire_nl11liilO_dataout : STD_LOGIC; + SIGNAL wire_nl11liiO_dataout : STD_LOGIC; + SIGNAL wire_nl11liiOi_dataout : STD_LOGIC; + SIGNAL wire_nl11liiOl_dataout : STD_LOGIC; + SIGNAL wire_nl11liiOO_dataout : STD_LOGIC; + SIGNAL wire_nl11lil0i_dataout : STD_LOGIC; + SIGNAL wire_nl11lil0l_dataout : STD_LOGIC; + SIGNAL wire_nl11lil0O_dataout : STD_LOGIC; + SIGNAL wire_nl11lil1i_dataout : STD_LOGIC; + SIGNAL wire_nl11lil1l_dataout : STD_LOGIC; + SIGNAL wire_nl11lil1O_dataout : STD_LOGIC; + SIGNAL wire_nl11lilii_dataout : STD_LOGIC; + SIGNAL wire_nl11lilil_dataout : STD_LOGIC; + SIGNAL wire_nl11liliO_dataout : STD_LOGIC; + SIGNAL wire_nl11lilli_dataout : STD_LOGIC; + SIGNAL wire_nl11lilll_dataout : STD_LOGIC; + SIGNAL wire_nl11lillO_dataout : STD_LOGIC; + SIGNAL wire_nl11lilO_dataout : STD_LOGIC; + SIGNAL wire_nl11lilOi_dataout : STD_LOGIC; + SIGNAL wire_nl11lilOl_dataout : STD_LOGIC; + SIGNAL wire_nl11lilOO_dataout : STD_LOGIC; + SIGNAL wire_nl11liO0i_dataout : STD_LOGIC; + SIGNAL wire_nl11liO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11liO0O_dataout : STD_LOGIC; + SIGNAL wire_nl11liO1i_dataout : STD_LOGIC; + SIGNAL wire_nl11liO1l_dataout : STD_LOGIC; + SIGNAL wire_nl11liO1O_dataout : STD_LOGIC; + SIGNAL wire_nl11liOi_dataout : STD_LOGIC; + SIGNAL wire_nl11liOii_dataout : STD_LOGIC; + SIGNAL wire_nl11liOil_dataout : STD_LOGIC; + SIGNAL wire_nl11liOiO_dataout : STD_LOGIC; + SIGNAL wire_nl11liOli_dataout : STD_LOGIC; + SIGNAL wire_nl11liOll_dataout : STD_LOGIC; + SIGNAL wire_nl11liOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11liOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11liOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11liOOO_dataout : STD_LOGIC; + SIGNAL wire_nl11ll00i_dataout : STD_LOGIC; + SIGNAL wire_nl11ll00l_dataout : STD_LOGIC; + SIGNAL wire_nl11ll00O_dataout : STD_LOGIC; + SIGNAL wire_nl11ll01i_dataout : STD_LOGIC; + SIGNAL wire_nl11ll01l_dataout : STD_LOGIC; + SIGNAL wire_nl11ll01O_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0ii_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0il_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0iO_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0li_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0lO_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11ll0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11ll10i_dataout : STD_LOGIC; + SIGNAL wire_nl11ll10l_dataout : STD_LOGIC; + SIGNAL wire_nl11ll10O_dataout : STD_LOGIC; + SIGNAL wire_nl11ll11i_dataout : STD_LOGIC; + SIGNAL wire_nl11ll11l_dataout : STD_LOGIC; + SIGNAL wire_nl11ll11O_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1il_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1li_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1lO_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11ll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl11lli0i_dataout : STD_LOGIC; + SIGNAL wire_nl11lli0l_dataout : STD_LOGIC; + SIGNAL wire_nl11lli0O_dataout : STD_LOGIC; + SIGNAL wire_nl11lli1i_dataout : STD_LOGIC; + SIGNAL wire_nl11lli1l_dataout : STD_LOGIC; + SIGNAL wire_nl11lli1O_dataout : STD_LOGIC; + SIGNAL wire_nl11lliii_dataout : STD_LOGIC; + SIGNAL wire_nl11lliil_dataout : STD_LOGIC; + SIGNAL wire_nl11lliiO_dataout : STD_LOGIC; + SIGNAL wire_nl11llili_dataout : STD_LOGIC; + SIGNAL wire_nl11llill_dataout : STD_LOGIC; + SIGNAL wire_nl11llilO_dataout : STD_LOGIC; + SIGNAL wire_nl11lliO_dataout : STD_LOGIC; + SIGNAL wire_nl11lliOi_dataout : STD_LOGIC; + SIGNAL wire_nl11lliOl_dataout : STD_LOGIC; + SIGNAL wire_nl11lliOO_dataout : STD_LOGIC; + SIGNAL wire_nl11lll0i_dataout : STD_LOGIC; + SIGNAL wire_nl11lll0l_dataout : STD_LOGIC; + SIGNAL wire_nl11lll0O_dataout : STD_LOGIC; + SIGNAL wire_nl11lll1i_dataout : STD_LOGIC; + SIGNAL wire_nl11lll1l_dataout : STD_LOGIC; + SIGNAL wire_nl11lll1O_dataout : STD_LOGIC; + SIGNAL wire_nl11llli_dataout : STD_LOGIC; + SIGNAL wire_nl11lllii_dataout : STD_LOGIC; + SIGNAL wire_nl11lllil_dataout : STD_LOGIC; + SIGNAL wire_nl11llliO_dataout : STD_LOGIC; + SIGNAL wire_nl11lllli_dataout : STD_LOGIC; + SIGNAL wire_nl11lllll_dataout : STD_LOGIC; + SIGNAL wire_nl11llllO_dataout : STD_LOGIC; + SIGNAL wire_nl11lllO_dataout : STD_LOGIC; + SIGNAL wire_nl11lllOi_dataout : STD_LOGIC; + SIGNAL wire_nl11lllOl_dataout : STD_LOGIC; + SIGNAL wire_nl11lllOO_dataout : STD_LOGIC; + SIGNAL wire_nl11llO0i_dataout : STD_LOGIC; + SIGNAL wire_nl11llO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11llO0O_dataout : STD_LOGIC; + SIGNAL wire_nl11llO1i_dataout : STD_LOGIC; + SIGNAL wire_nl11llO1l_dataout : STD_LOGIC; + SIGNAL wire_nl11llO1O_dataout : STD_LOGIC; + SIGNAL wire_nl11llOi_dataout : STD_LOGIC; + SIGNAL wire_nl11llOii_dataout : STD_LOGIC; + SIGNAL wire_nl11llOil_dataout : STD_LOGIC; + SIGNAL wire_nl11llOiO_dataout : STD_LOGIC; + SIGNAL wire_nl11llOl_dataout : STD_LOGIC; + SIGNAL wire_nl11llOli_dataout : STD_LOGIC; + SIGNAL wire_nl11llOll_dataout : STD_LOGIC; + SIGNAL wire_nl11llOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11llOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl11lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl11lOli_dataout : STD_LOGIC; + SIGNAL wire_nl11lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11lOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11lOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOii_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOil_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOli_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOll_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11lOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl11O000i_dataout : STD_LOGIC; + SIGNAL wire_nl11O000l_dataout : STD_LOGIC; + SIGNAL wire_nl11O000O_dataout : STD_LOGIC; + SIGNAL wire_nl11O001i_dataout : STD_LOGIC; + SIGNAL wire_nl11O001l_dataout : STD_LOGIC; + SIGNAL wire_nl11O001O_dataout : STD_LOGIC; + SIGNAL wire_nl11O00ii_dataout : STD_LOGIC; + SIGNAL wire_nl11O00il_dataout : STD_LOGIC; + SIGNAL wire_nl11O00iO_dataout : STD_LOGIC; + SIGNAL wire_nl11O00l_dataout : STD_LOGIC; + SIGNAL wire_nl11O00li_dataout : STD_LOGIC; + SIGNAL wire_nl11O00ll_dataout : STD_LOGIC; + SIGNAL wire_nl11O00lO_dataout : STD_LOGIC; + SIGNAL wire_nl11O00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11O00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11O00OO_dataout : STD_LOGIC; + SIGNAL wire_nl11O010i_dataout : STD_LOGIC; + SIGNAL wire_nl11O010l_dataout : STD_LOGIC; + SIGNAL wire_nl11O010O_dataout : STD_LOGIC; + SIGNAL wire_nl11O011i_dataout : STD_LOGIC; + SIGNAL wire_nl11O011l_dataout : STD_LOGIC; + SIGNAL wire_nl11O011O_dataout : STD_LOGIC; + SIGNAL wire_nl11O01ii_dataout : STD_LOGIC; + SIGNAL wire_nl11O01il_dataout : STD_LOGIC; + SIGNAL wire_nl11O01iO_dataout : STD_LOGIC; + SIGNAL wire_nl11O01li_dataout : STD_LOGIC; + SIGNAL wire_nl11O01ll_dataout : STD_LOGIC; + SIGNAL wire_nl11O01lO_dataout : STD_LOGIC; + SIGNAL wire_nl11O01O_dataout : STD_LOGIC; + SIGNAL wire_nl11O01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11O01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11O01OO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl11O0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl11O0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl11O0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl11O0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl11O0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl11O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl11O0iii_dataout : STD_LOGIC; + SIGNAL wire_nl11O0iil_dataout : STD_LOGIC; + SIGNAL wire_nl11O0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0ili_dataout : STD_LOGIC; + SIGNAL wire_nl11O0ill_dataout : STD_LOGIC; + SIGNAL wire_nl11O0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl11O0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl11O0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl11O0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl11O0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl11O0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl11O0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl11O0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl11O0li_dataout : STD_LOGIC; + SIGNAL wire_nl11O0lii_dataout : STD_LOGIC; + SIGNAL wire_nl11O0lil_dataout : STD_LOGIC; + SIGNAL wire_nl11O0liO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11O0lli_dataout : STD_LOGIC; + SIGNAL wire_nl11O0lll_dataout : STD_LOGIC; + SIGNAL wire_nl11O0llO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl11O0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl11O0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl11O0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl11O0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl11O0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl11O0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl11O0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl11O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11O0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl11O0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl11O0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11O0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl11O0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl11O0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11O0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl11O0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl11O0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl11O100i_dataout : STD_LOGIC; + SIGNAL wire_nl11O100l_dataout : STD_LOGIC; + SIGNAL wire_nl11O100O_dataout : STD_LOGIC; + SIGNAL wire_nl11O101i_dataout : STD_LOGIC; + SIGNAL wire_nl11O101l_dataout : STD_LOGIC; + SIGNAL wire_nl11O101O_dataout : STD_LOGIC; + SIGNAL wire_nl11O10ii_dataout : STD_LOGIC; + SIGNAL wire_nl11O10il_dataout : STD_LOGIC; + SIGNAL wire_nl11O10iO_dataout : STD_LOGIC; + SIGNAL wire_nl11O10l_dataout : STD_LOGIC; + SIGNAL wire_nl11O10li_dataout : STD_LOGIC; + SIGNAL wire_nl11O10ll_dataout : STD_LOGIC; + SIGNAL wire_nl11O10lO_dataout : STD_LOGIC; + SIGNAL wire_nl11O10O_dataout : STD_LOGIC; + SIGNAL wire_nl11O10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11O10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11O10OO_dataout : STD_LOGIC; + SIGNAL wire_nl11O110i_dataout : STD_LOGIC; + SIGNAL wire_nl11O110l_dataout : STD_LOGIC; + SIGNAL wire_nl11O110O_dataout : STD_LOGIC; + SIGNAL wire_nl11O111i_dataout : STD_LOGIC; + SIGNAL wire_nl11O111l_dataout : STD_LOGIC; + SIGNAL wire_nl11O111O_dataout : STD_LOGIC; + SIGNAL wire_nl11O11ii_dataout : STD_LOGIC; + SIGNAL wire_nl11O11il_dataout : STD_LOGIC; + SIGNAL wire_nl11O11iO_dataout : STD_LOGIC; + SIGNAL wire_nl11O11l_dataout : STD_LOGIC; + SIGNAL wire_nl11O11li_dataout : STD_LOGIC; + SIGNAL wire_nl11O11ll_dataout : STD_LOGIC; + SIGNAL wire_nl11O11lO_dataout : STD_LOGIC; + SIGNAL wire_nl11O11O_dataout : STD_LOGIC; + SIGNAL wire_nl11O11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11O11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11O11OO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl11O1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl11O1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl11O1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl11O1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl11O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl11O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11O1iii_dataout : STD_LOGIC; + SIGNAL wire_nl11O1iil_dataout : STD_LOGIC; + SIGNAL wire_nl11O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1ili_dataout : STD_LOGIC; + SIGNAL wire_nl11O1ill_dataout : STD_LOGIC; + SIGNAL wire_nl11O1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl11O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl11O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl11O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl11O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl11O1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl11O1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl11O1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl11O1li_dataout : STD_LOGIC; + SIGNAL wire_nl11O1lii_dataout : STD_LOGIC; + SIGNAL wire_nl11O1lil_dataout : STD_LOGIC; + SIGNAL wire_nl11O1liO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1lli_dataout : STD_LOGIC; + SIGNAL wire_nl11O1lll_dataout : STD_LOGIC; + SIGNAL wire_nl11O1llO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl11O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl11O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl11O1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl11O1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl11O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl11O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl11O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl11O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl11O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl11O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl11O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl11O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl11O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl11O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl11O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi00i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi00l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi00O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi01i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi01l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi01O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0il_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0li_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi10i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi10l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi10O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi11i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi11l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi11O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1il_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1li_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oii1i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl11Oiiii_dataout : STD_LOGIC; + SIGNAL wire_nl11Oiiil_dataout : STD_LOGIC; + SIGNAL wire_nl11OiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oiili_dataout : STD_LOGIC; + SIGNAL wire_nl11Oiill_dataout : STD_LOGIC; + SIGNAL wire_nl11OiilO_dataout : STD_LOGIC; + SIGNAL wire_nl11OiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl11OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl11OiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oil0l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oil0O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oilii_dataout : STD_LOGIC; + SIGNAL wire_nl11Oilii_w_lg_dataout59843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11Oill_dataout : STD_LOGIC; + SIGNAL wire_nl11OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl11OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol00l_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol00O_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol0il_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol0li_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol10l_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol10O_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1li_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl11Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oli0i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oli0O_dataout : STD_LOGIC; + SIGNAL wire_nl11Olii_dataout : STD_LOGIC; + SIGNAL wire_nl11Oliii_dataout : STD_LOGIC; + SIGNAL wire_nl11Oliil_dataout : STD_LOGIC; + SIGNAL wire_nl11OliiO_dataout : STD_LOGIC; + SIGNAL wire_nl11Olil_dataout : STD_LOGIC; + SIGNAL wire_nl11Olili_dataout : STD_LOGIC; + SIGNAL wire_nl11Olill_dataout : STD_LOGIC; + SIGNAL wire_nl11OlilO_dataout : STD_LOGIC; + SIGNAL wire_nl11OliOi_dataout : STD_LOGIC; + SIGNAL wire_nl11OliOl_dataout : STD_LOGIC; + SIGNAL wire_nl11OliOO_dataout : STD_LOGIC; + SIGNAL wire_nl11Oll0i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oll0l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oll0O_dataout : STD_LOGIC; + SIGNAL wire_nl11Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nl11Oll1l_dataout : STD_LOGIC; + SIGNAL wire_nl11Oll1O_dataout : STD_LOGIC; + SIGNAL wire_nl11Ollii_dataout : STD_LOGIC; + SIGNAL wire_nl11Ollil_dataout : STD_LOGIC; + SIGNAL wire_nl11OlliO_dataout : STD_LOGIC; + SIGNAL wire_nl11Olll_dataout : STD_LOGIC; + SIGNAL wire_nl11Ollli_dataout : STD_LOGIC; + SIGNAL wire_nl11Ollll_dataout : STD_LOGIC; + SIGNAL wire_nl11OlllO_dataout : STD_LOGIC; + SIGNAL wire_nl11OllOi_dataout : STD_LOGIC; + SIGNAL wire_nl11OllOl_dataout : STD_LOGIC; + SIGNAL wire_nl11OllOO_dataout : STD_LOGIC; + SIGNAL wire_nl11OlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl11OlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11OlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl11OlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl11OlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl11OlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOii_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOil_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOli_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOll_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11OlOOl_w_lg_dataout61549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl11OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl11OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl11OOii_dataout : STD_LOGIC; + SIGNAL wire_nl11OOli_dataout : STD_LOGIC; + SIGNAL wire_nl11OOll_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOil_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOli_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOll_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl11OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0000i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0000l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0000O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0001i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0001l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0001O_dataout : STD_LOGIC; + SIGNAL wire_nl1i000i_dataout : STD_LOGIC; + SIGNAL wire_nl1i000ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i000il_dataout : STD_LOGIC; + SIGNAL wire_nl1i000iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i000l_dataout : STD_LOGIC; + SIGNAL wire_nl1i000li_dataout : STD_LOGIC; + SIGNAL wire_nl1i000ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i000lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i000O_dataout : STD_LOGIC; + SIGNAL wire_nl1i000Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i000Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i000OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0010i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0010l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0010O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0011i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0011l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0011O_dataout : STD_LOGIC; + SIGNAL wire_nl1i001i_dataout : STD_LOGIC; + SIGNAL wire_nl1i001ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i001il_dataout : STD_LOGIC; + SIGNAL wire_nl1i001iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i001l_dataout : STD_LOGIC; + SIGNAL wire_nl1i001li_dataout : STD_LOGIC; + SIGNAL wire_nl1i001ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i001lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i001O_dataout : STD_LOGIC; + SIGNAL wire_nl1i001Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i001Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i001OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i00i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i00i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i00i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i00i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i00i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i00iii_dataout : STD_LOGIC; + SIGNAL wire_nl1i00iil_dataout : STD_LOGIC; + SIGNAL wire_nl1i00iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00il_dataout : STD_LOGIC; + SIGNAL wire_nl1i00ili_dataout : STD_LOGIC; + SIGNAL wire_nl1i00ill_dataout : STD_LOGIC; + SIGNAL wire_nl1i00ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i00iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i00iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i00l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i00l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i00l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i00l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i00l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i00li_dataout : STD_LOGIC; + SIGNAL wire_nl1i00lii_dataout : STD_LOGIC; + SIGNAL wire_nl1i00lil_dataout : STD_LOGIC; + SIGNAL wire_nl1i00liO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i00lll_dataout : STD_LOGIC; + SIGNAL wire_nl1i00llO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i00lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i00lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i00O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i00O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i00O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i00O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i00O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i00Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1i00Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1i00OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i00Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1i00Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1i00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i00OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i00OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i010li_dataout : STD_LOGIC; + SIGNAL wire_nl1i010ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i010lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i010Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i010Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i010OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i01i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i01i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i01i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i01i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i01i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i01iii_dataout : STD_LOGIC; + SIGNAL wire_nl1i01iil_dataout : STD_LOGIC; + SIGNAL wire_nl1i01iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01ili_dataout : STD_LOGIC; + SIGNAL wire_nl1i01ill_dataout : STD_LOGIC; + SIGNAL wire_nl1i01ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i01iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i01iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i01l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i01l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i01l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i01l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i01l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i01lii_dataout : STD_LOGIC; + SIGNAL wire_nl1i01lil_dataout : STD_LOGIC; + SIGNAL wire_nl1i01liO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01lli_dataout : STD_LOGIC; + SIGNAL wire_nl1i01lll_dataout : STD_LOGIC; + SIGNAL wire_nl1i01llO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i01lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i01lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i01O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i01O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i01O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i01O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i01O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i01Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1i01Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1i01OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1i01Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1i01OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1i01OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i01OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i01OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i00i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i00l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i00O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i01i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i01l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i01O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0il_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0li_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i10i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i10l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i10O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i11i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i11l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1il_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1li_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iiii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iiil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iili_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iill_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0il0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0il0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0il0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0il1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0il1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0il1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ili_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ilii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1i0illi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0illl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0illO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOli_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l00i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l00l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l00O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l01i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l01l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l01O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0li_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l11i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l11l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1il_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1li_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0li0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0li0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0li0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0li1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0li1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0li1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0liii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0liil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0liiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lili_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lill_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0liOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0liOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0liOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lliO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0llli_dataout : STD_LOGIC; + SIGNAL wire_nl1i0llll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lllO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0llOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0llOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0llOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lOii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lOil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O00i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O00l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O00O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O01i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O01l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O01O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O0il_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O10i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O10l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O10O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O11i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O11l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1il_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1li_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oili_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Oill_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Olil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OliO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Olli_dataout : STD_LOGIC; + SIGNAL wire_nl1i0Olll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OllO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOii_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOil_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOli_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOll_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i100i_dataout : STD_LOGIC; + SIGNAL wire_nl1i100l_dataout : STD_LOGIC; + SIGNAL wire_nl1i100O_dataout : STD_LOGIC; + SIGNAL wire_nl1i101i_dataout : STD_LOGIC; + SIGNAL wire_nl1i101l_dataout : STD_LOGIC; + SIGNAL wire_nl1i101O_dataout : STD_LOGIC; + SIGNAL wire_nl1i10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i10il_dataout : STD_LOGIC; + SIGNAL wire_nl1i10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i10iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i10l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i10l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i10l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i10l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i10l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i10li_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lii_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lil_dataout : STD_LOGIC; + SIGNAL wire_nl1i10liO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lli_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lll_dataout : STD_LOGIC; + SIGNAL wire_nl1i10llO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i10lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i10O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i10O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i10O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i10O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i10O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i10Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1i10Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1i10OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i10Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1i10Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1i10OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i10OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i10OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i10OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1100i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1100l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1100O_dataout : STD_LOGIC; + SIGNAL wire_nl1i110ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i110il_dataout : STD_LOGIC; + SIGNAL wire_nl1i110iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1110i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1110l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1110O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1111i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1111l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1111O_dataout : STD_LOGIC; + SIGNAL wire_nl1i111ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i111il_dataout : STD_LOGIC; + SIGNAL wire_nl1i111iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i111li_dataout : STD_LOGIC; + SIGNAL wire_nl1i111ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i00i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i00l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i00O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i01i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i01l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i01O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0il_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0li_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i10i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i10l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i10O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i11i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i11l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1il_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1li_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iiii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iiil_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iili_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iill_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1il0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1il0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1il0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1il1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1il1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1il1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ilii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ilil_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iliO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1i1illi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1illl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1illO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOil_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOli_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l00i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l00l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l00O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l01l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l01O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0il_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0li_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l10i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l10l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l10O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l11i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l11l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1il_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1li_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i1li0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1li0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1li0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1li1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1li1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1li1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1liii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1liil_dataout : STD_LOGIC; + SIGNAL wire_nl1i1liiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lili_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lill_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lilO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1liOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1liOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1liOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1i1llii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lliO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1llli_dataout : STD_LOGIC; + SIGNAL wire_nl1i1llll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lllO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1llOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1llOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1llOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOil_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1i1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O00i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O00l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O01i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O01l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O01O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0il_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0li_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O10i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O10l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O10O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O11i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O11l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O11O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1il_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1li_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1i1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl1i1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl1ii00O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii01i_dataout : STD_LOGIC; + SIGNAL wire_nl1ii01l_dataout : STD_LOGIC; + SIGNAL wire_nl1ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ii0il_dataout : STD_LOGIC; + SIGNAL wire_nl1ii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ii0li_dataout : STD_LOGIC; + SIGNAL wire_nl1ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ii100i_dataout : STD_LOGIC; + SIGNAL wire_nl1ii100l_dataout : STD_LOGIC; + SIGNAL wire_nl1ii100O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii101i_dataout : STD_LOGIC; + SIGNAL wire_nl1ii101l_dataout : STD_LOGIC; + SIGNAL wire_nl1ii101O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii10i_dataout : STD_LOGIC; + SIGNAL wire_nl1ii10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ii10il_dataout : STD_LOGIC; + SIGNAL wire_nl1ii10l_dataout : STD_LOGIC; + SIGNAL wire_nl1ii111i_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11i_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11il_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11l_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11li_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11O_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ii11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1ii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iiiil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiili_dataout : STD_LOGIC; + SIGNAL wire_nl1iiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iil00i_dataout : STD_LOGIC; + SIGNAL wire_nl1iil00l_dataout : STD_LOGIC; + SIGNAL wire_nl1iil00O_dataout : STD_LOGIC; + SIGNAL wire_nl1iil01i_dataout : STD_LOGIC; + SIGNAL wire_nl1iil01l_dataout : STD_LOGIC; + SIGNAL wire_nl1iil01O_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0il_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0li_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iil0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iil10i_dataout : STD_LOGIC; + SIGNAL wire_nl1iil10l_dataout : STD_LOGIC; + SIGNAL wire_nl1iil11i_dataout : STD_LOGIC; + SIGNAL wire_nl1iil11l_dataout : STD_LOGIC; + SIGNAL wire_nl1iil11O_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1li_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iil1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iili0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iili0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iili1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iili1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iilii_dataout : STD_LOGIC; + SIGNAL wire_nl1iiliOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iiliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iill0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iill0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iill0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iill1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iill1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iill1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iilli_dataout : STD_LOGIC; + SIGNAL wire_nl1iillii_dataout : STD_LOGIC; + SIGNAL wire_nl1iillil_dataout : STD_LOGIC; + SIGNAL wire_nl1iilliO_dataout : STD_LOGIC; + SIGNAL wire_nl1iillli_dataout : STD_LOGIC; + SIGNAL wire_nl1iillll_dataout : STD_LOGIC; + SIGNAL wire_nl1iilllO_dataout : STD_LOGIC; + SIGNAL wire_nl1iillOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iillOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iillOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iilO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iilO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iilO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iilO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iilO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iilO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO00i_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO00O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOili_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOill_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1il000O_dataout : STD_LOGIC; + SIGNAL wire_nl1il001i_dataout : STD_LOGIC; + SIGNAL wire_nl1il00il_dataout : STD_LOGIC; + SIGNAL wire_nl1il00li_dataout : STD_LOGIC; + SIGNAL wire_nl1il00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1il00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1il00O_dataout : STD_LOGIC; + SIGNAL wire_nl1il00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1il010i_dataout : STD_LOGIC; + SIGNAL wire_nl1il010l_dataout : STD_LOGIC; + SIGNAL wire_nl1il010O_dataout : STD_LOGIC; + SIGNAL wire_nl1il011i_dataout : STD_LOGIC; + SIGNAL wire_nl1il011l_dataout : STD_LOGIC; + SIGNAL wire_nl1il011O_dataout : STD_LOGIC; + SIGNAL wire_nl1il01i_dataout : STD_LOGIC; + SIGNAL wire_nl1il01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il01il_dataout : STD_LOGIC; + SIGNAL wire_nl1il01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1il01li_dataout : STD_LOGIC; + SIGNAL wire_nl1il01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1il01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1il01O_dataout : STD_LOGIC; + SIGNAL wire_nl1il01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1il01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1il01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1il0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1il0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1il0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1il0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il0iii_dataout : STD_LOGIC; + SIGNAL wire_nl1il0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1il0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1il0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1il0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1il0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1il0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1il0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1il0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1il0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1il0li_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1il0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1il0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1il0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1il0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1il0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1il0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1il0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1il0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1il0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1il0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1il0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1il0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1il0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1il0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1il0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1il0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1il0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1il100i_dataout : STD_LOGIC; + SIGNAL wire_nl1il100l_dataout : STD_LOGIC; + SIGNAL wire_nl1il100O_dataout : STD_LOGIC; + SIGNAL wire_nl1il101i_dataout : STD_LOGIC; + SIGNAL wire_nl1il101l_dataout : STD_LOGIC; + SIGNAL wire_nl1il101O_dataout : STD_LOGIC; + SIGNAL wire_nl1il10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il10il_dataout : STD_LOGIC; + SIGNAL wire_nl1il10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1il10li_dataout : STD_LOGIC; + SIGNAL wire_nl1il10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1il111i_dataout : STD_LOGIC; + SIGNAL wire_nl1il111l_dataout : STD_LOGIC; + SIGNAL wire_nl1il111O_dataout : STD_LOGIC; + SIGNAL wire_nl1il11il_dataout : STD_LOGIC; + SIGNAL wire_nl1il11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1il11li_dataout : STD_LOGIC; + SIGNAL wire_nl1il11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1il11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1il11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1il11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1il11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1il1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1il1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1il1il_dataout : STD_LOGIC; + SIGNAL wire_nl1il1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1il1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1il1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1il1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1il1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1il1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1il1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1il1li_dataout : STD_LOGIC; + SIGNAL wire_nl1il1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1il1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1il1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1il1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1il1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1il1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1il1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1il1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1il1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1il1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1il1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1il1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1il1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1il1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1il1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1il1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1il1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1il1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1il1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1il1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1il1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1il1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1il1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1il1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ili00i_dataout : STD_LOGIC; + SIGNAL wire_nl1ili01i_dataout : STD_LOGIC; + SIGNAL wire_nl1ili01l_dataout : STD_LOGIC; + SIGNAL wire_nl1ili01O_dataout : STD_LOGIC; + SIGNAL wire_nl1ili10i_dataout : STD_LOGIC; + SIGNAL wire_nl1ili10l_dataout : STD_LOGIC; + SIGNAL wire_nl1ili10O_dataout : STD_LOGIC; + SIGNAL wire_nl1ili11i_dataout : STD_LOGIC; + SIGNAL wire_nl1ili11l_dataout : STD_LOGIC; + SIGNAL wire_nl1ili11O_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1li_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ili1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iliilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iliiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iliiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iliiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilil0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilil0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilil1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilil1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ililii_dataout : STD_LOGIC; + SIGNAL wire_nl1ililil_dataout : STD_LOGIC; + SIGNAL wire_nl1ililiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ililli_dataout : STD_LOGIC; + SIGNAL wire_nl1ililll_dataout : STD_LOGIC; + SIGNAL wire_nl1ilillO_dataout : STD_LOGIC; + SIGNAL wire_nl1ililOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ililOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ililOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iliO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iliO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iliO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iliO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iliO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iliO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iliOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ill00i_dataout : STD_LOGIC; + SIGNAL wire_nl1ill00l_dataout : STD_LOGIC; + SIGNAL wire_nl1ill00O_dataout : STD_LOGIC; + SIGNAL wire_nl1ill01i_dataout : STD_LOGIC; + SIGNAL wire_nl1ill01l_dataout : STD_LOGIC; + SIGNAL wire_nl1ill01O_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0il_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0li_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ill0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1ill10i_dataout : STD_LOGIC; + SIGNAL wire_nl1ill10l_dataout : STD_LOGIC; + SIGNAL wire_nl1ill10O_dataout : STD_LOGIC; + SIGNAL wire_nl1ill11i_dataout : STD_LOGIC; + SIGNAL wire_nl1ill11l_dataout : STD_LOGIC; + SIGNAL wire_nl1ill11O_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1il_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1li_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ill1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1illi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1illi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1illi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1illi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1illi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1illi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1illiii_dataout : STD_LOGIC; + SIGNAL wire_nl1illiil_dataout : STD_LOGIC; + SIGNAL wire_nl1illiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1illili_dataout : STD_LOGIC; + SIGNAL wire_nl1illill_dataout : STD_LOGIC; + SIGNAL wire_nl1illilO_dataout : STD_LOGIC; + SIGNAL wire_nl1illiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1illiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1illiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1illl_dataout : STD_LOGIC; + SIGNAL wire_nl1illl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1illl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1illl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1illl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1illl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1illl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1illlii_dataout : STD_LOGIC; + SIGNAL wire_nl1illlil_dataout : STD_LOGIC; + SIGNAL wire_nl1illliO_dataout : STD_LOGIC; + SIGNAL wire_nl1illlli_dataout : STD_LOGIC; + SIGNAL wire_nl1illlll_dataout : STD_LOGIC; + SIGNAL wire_nl1illllO_dataout : STD_LOGIC; + SIGNAL wire_nl1illlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1illlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1illlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1illO_dataout : STD_LOGIC; + SIGNAL wire_nl1illO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1illO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1illO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1illO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1illO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1illO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1illOii_dataout : STD_LOGIC; + SIGNAL wire_nl1illOil_dataout : STD_LOGIC; + SIGNAL wire_nl1illOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1illOli_dataout : STD_LOGIC; + SIGNAL wire_nl1illOll_dataout : STD_LOGIC; + SIGNAL wire_nl1illOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1illOO_dataout : STD_LOGIC; + SIGNAL wire_nl1illOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1illOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1illOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO00i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO00l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO00O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO01l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO01O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0il_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0li_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ilO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOii_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOil_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOili_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOill_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOli_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOll_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ilOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO000i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO000l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO000O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO001i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO001l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO001O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00li_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iO00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO010i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO010l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO010O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO011i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO011l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO011O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01li_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iO01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0iii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0ili_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO100i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO100l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO100O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO101i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO101l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO101O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10li_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iO10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO110i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO110l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO110O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO111i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO111l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO111O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11li_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iO11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi00i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi00l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi00O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi01i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi01l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi01O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0il_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0li_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi10i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi10l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi10O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi11i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi11l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi11O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1li_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiiii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiiil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiili_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiill_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOili_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiliO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOill_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOillO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl00i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl00l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl00O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl01i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl01l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl01O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0il_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0li_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl10i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl10l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl10O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl11i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl11l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOli1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOliii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOliil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlili_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlill_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOliOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOliOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlliO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlllO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOllOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO00i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO00l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO00O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO01l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO01O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0il_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0li_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1iOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOili_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOill_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1iOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l001O_dataout : STD_LOGIC; + SIGNAL wire_nl1l00i_dataout : STD_LOGIC; + SIGNAL wire_nl1l00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l00l_dataout : STD_LOGIC; + SIGNAL wire_nl1l00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l00O_dataout : STD_LOGIC; + SIGNAL wire_nl1l00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l010O_dataout : STD_LOGIC; + SIGNAL wire_nl1l011i_dataout : STD_LOGIC; + SIGNAL wire_nl1l011O_dataout : STD_LOGIC; + SIGNAL wire_nl1l01i_dataout : STD_LOGIC; + SIGNAL wire_nl1l01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l01l_dataout : STD_LOGIC; + SIGNAL wire_nl1l01li_dataout : STD_LOGIC; + SIGNAL wire_nl1l01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l01O_dataout : STD_LOGIC; + SIGNAL wire_nl1l01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1l0il_dataout : STD_LOGIC; + SIGNAL wire_nl1l0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0li_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lOll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O00i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O00l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O00O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O01i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O01l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O01O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0il_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0li_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O10i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O10l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O10O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O11i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O11l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O11O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1il_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1li_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oili_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Oill_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OilO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Olii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Olil_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OliO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Olli_dataout : STD_LOGIC; + SIGNAL wire_nl1l0Olll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OllO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOii_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOil_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOli_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOll_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1000i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1000l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1000O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1001i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1001l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1001O_dataout : STD_LOGIC; + SIGNAL wire_nl1l100ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l100il_dataout : STD_LOGIC; + SIGNAL wire_nl1l100iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l100li_dataout : STD_LOGIC; + SIGNAL wire_nl1l100ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l100lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l100O_dataout : STD_LOGIC; + SIGNAL wire_nl1l100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l100OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1010i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1010l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1010O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1011i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1011l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1011O_dataout : STD_LOGIC; + SIGNAL wire_nl1l101i_dataout : STD_LOGIC; + SIGNAL wire_nl1l101ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l101il_dataout : STD_LOGIC; + SIGNAL wire_nl1l101iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l101l_dataout : STD_LOGIC; + SIGNAL wire_nl1l101li_dataout : STD_LOGIC; + SIGNAL wire_nl1l101ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l101lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l101OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l10iii_dataout : STD_LOGIC; + SIGNAL wire_nl1l10iil_dataout : STD_LOGIC; + SIGNAL wire_nl1l10iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10ili_dataout : STD_LOGIC; + SIGNAL wire_nl1l10ill_dataout : STD_LOGIC; + SIGNAL wire_nl1l10ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l10iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l10iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l10lii_dataout : STD_LOGIC; + SIGNAL wire_nl1l10lil_dataout : STD_LOGIC; + SIGNAL wire_nl1l10liO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10lli_dataout : STD_LOGIC; + SIGNAL wire_nl1l10lll_dataout : STD_LOGIC; + SIGNAL wire_nl1l10llO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l10lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l10lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l10O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l10Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1l10Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1l10OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1l10Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1l10OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l10OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l10OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l10OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1100i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1100l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1100O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1101i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1101l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1101O_dataout : STD_LOGIC; + SIGNAL wire_nl1l110ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l110il_dataout : STD_LOGIC; + SIGNAL wire_nl1l110iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l110l_dataout : STD_LOGIC; + SIGNAL wire_nl1l110li_dataout : STD_LOGIC; + SIGNAL wire_nl1l110ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l110lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l110OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1110i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1110l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1110O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1111i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1111l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1111O_dataout : STD_LOGIC; + SIGNAL wire_nl1l111i_dataout : STD_LOGIC; + SIGNAL wire_nl1l111ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l111il_dataout : STD_LOGIC; + SIGNAL wire_nl1l111iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l111li_dataout : STD_LOGIC; + SIGNAL wire_nl1l111ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l111lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l111OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l11iii_dataout : STD_LOGIC; + SIGNAL wire_nl1l11iil_dataout : STD_LOGIC; + SIGNAL wire_nl1l11iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11ili_dataout : STD_LOGIC; + SIGNAL wire_nl1l11ill_dataout : STD_LOGIC; + SIGNAL wire_nl1l11ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l11iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l11iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lii_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lil_dataout : STD_LOGIC; + SIGNAL wire_nl1l11liO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lli_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lll_dataout : STD_LOGIC; + SIGNAL wire_nl1l11llO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l11lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l11O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l11Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1l11Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1l11OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1l11Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1l11OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l11OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l11OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l11OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i00i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i00l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i00O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i01i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i01l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i01O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0il_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0li_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i10i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i10l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i10O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i11i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i11l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i11O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1il_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1li_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1l1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iiii_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iiil_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iili_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iill_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iilO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il0i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il0l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1il1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ilii_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ilil_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iliO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1illi_dataout : STD_LOGIC; + SIGNAL wire_nl1l1illl_dataout : STD_LOGIC; + SIGNAL wire_nl1l1illO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1li_dataout : STD_LOGIC; + SIGNAL wire_nl1l1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1l1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1l1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1l1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1l1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1l1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1l1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1l1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1li000i_dataout : STD_LOGIC; + SIGNAL wire_nl1li000l_dataout : STD_LOGIC; + SIGNAL wire_nl1li000O_dataout : STD_LOGIC; + SIGNAL wire_nl1li001i_dataout : STD_LOGIC; + SIGNAL wire_nl1li001l_dataout : STD_LOGIC; + SIGNAL wire_nl1li001O_dataout : STD_LOGIC; + SIGNAL wire_nl1li00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1li00il_dataout : STD_LOGIC; + SIGNAL wire_nl1li00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1li00li_dataout : STD_LOGIC; + SIGNAL wire_nl1li00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1li00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1li00O_dataout : STD_LOGIC; + SIGNAL wire_nl1li00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1li00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1li00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1li010i_dataout : STD_LOGIC; + SIGNAL wire_nl1li010l_dataout : STD_LOGIC; + SIGNAL wire_nl1li010O_dataout : STD_LOGIC; + SIGNAL wire_nl1li011i_dataout : STD_LOGIC; + SIGNAL wire_nl1li011l_dataout : STD_LOGIC; + SIGNAL wire_nl1li011O_dataout : STD_LOGIC; + SIGNAL wire_nl1li01i_dataout : STD_LOGIC; + SIGNAL wire_nl1li01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1li01il_dataout : STD_LOGIC; + SIGNAL wire_nl1li01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1li01li_dataout : STD_LOGIC; + SIGNAL wire_nl1li01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1li01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1li01O_dataout : STD_LOGIC; + SIGNAL wire_nl1li01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1li01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1li01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1li0iii_dataout : STD_LOGIC; + SIGNAL wire_nl1li0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1li0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0ili_dataout : STD_LOGIC; + SIGNAL wire_nl1li0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1li0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1li0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1li0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1li0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1li0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1li0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1li0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1li0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1li0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1li0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1li0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1li0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1li0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1li0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1li0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1li100i_dataout : STD_LOGIC; + SIGNAL wire_nl1li100l_dataout : STD_LOGIC; + SIGNAL wire_nl1li100O_dataout : STD_LOGIC; + SIGNAL wire_nl1li101i_dataout : STD_LOGIC; + SIGNAL wire_nl1li101l_dataout : STD_LOGIC; + SIGNAL wire_nl1li101O_dataout : STD_LOGIC; + SIGNAL wire_nl1li10i_dataout : STD_LOGIC; + SIGNAL wire_nl1li10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1li10il_dataout : STD_LOGIC; + SIGNAL wire_nl1li10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1li10l_dataout : STD_LOGIC; + SIGNAL wire_nl1li10li_dataout : STD_LOGIC; + SIGNAL wire_nl1li10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1li10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1li10O_dataout : STD_LOGIC; + SIGNAL wire_nl1li10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1li10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1li10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1li110i_dataout : STD_LOGIC; + SIGNAL wire_nl1li110l_dataout : STD_LOGIC; + SIGNAL wire_nl1li110O_dataout : STD_LOGIC; + SIGNAL wire_nl1li111i_dataout : STD_LOGIC; + SIGNAL wire_nl1li111l_dataout : STD_LOGIC; + SIGNAL wire_nl1li111O_dataout : STD_LOGIC; + SIGNAL wire_nl1li11ii_dataout : STD_LOGIC; + SIGNAL wire_nl1li11il_dataout : STD_LOGIC; + SIGNAL wire_nl1li11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1li11li_dataout : STD_LOGIC; + SIGNAL wire_nl1li11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1li11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1li11O_dataout : STD_LOGIC; + SIGNAL wire_nl1li11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1li11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1li11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1li1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1li1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1li1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1il_dataout : STD_LOGIC; + SIGNAL wire_nl1li1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1li1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1li1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1li1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1li1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1li_dataout : STD_LOGIC; + SIGNAL wire_nl1li1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1li1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1li1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1li1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1li1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1li1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1li1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1li1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1li1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1li1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1li1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1li1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1li1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1li1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1li1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1li1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1li1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lii00i_dataout : STD_LOGIC; + SIGNAL wire_nl1lii00l_dataout : STD_LOGIC; + SIGNAL wire_nl1lii00O_dataout : STD_LOGIC; + SIGNAL wire_nl1lii01i_dataout : STD_LOGIC; + SIGNAL wire_nl1lii01l_dataout : STD_LOGIC; + SIGNAL wire_nl1lii01O_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0il_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0li_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lii10i_dataout : STD_LOGIC; + SIGNAL wire_nl1lii10l_dataout : STD_LOGIC; + SIGNAL wire_nl1lii10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lii11i_dataout : STD_LOGIC; + SIGNAL wire_nl1lii11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lii11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1li_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lii1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1liii_dataout : STD_LOGIC; + SIGNAL wire_nl1liii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1liii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1liii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1liii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1liii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1liii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1liiii_dataout : STD_LOGIC; + SIGNAL wire_nl1liiiii_dataout : STD_LOGIC; + SIGNAL wire_nl1liiiil_dataout : STD_LOGIC; + SIGNAL wire_nl1liiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1liiili_dataout : STD_LOGIC; + SIGNAL wire_nl1liiill_dataout : STD_LOGIC; + SIGNAL wire_nl1liiilO_dataout : STD_LOGIC; + SIGNAL wire_nl1liiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1liil_dataout : STD_LOGIC; + SIGNAL wire_nl1liil0i_dataout : STD_LOGIC; + SIGNAL wire_nl1liil0l_dataout : STD_LOGIC; + SIGNAL wire_nl1liil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1liil1i_dataout : STD_LOGIC; + SIGNAL wire_nl1liil1l_dataout : STD_LOGIC; + SIGNAL wire_nl1liil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1liilii_dataout : STD_LOGIC; + SIGNAL wire_nl1liilil_dataout : STD_LOGIC; + SIGNAL wire_nl1liiliO_dataout : STD_LOGIC; + SIGNAL wire_nl1liilli_dataout : STD_LOGIC; + SIGNAL wire_nl1liilll_dataout : STD_LOGIC; + SIGNAL wire_nl1liillO_dataout : STD_LOGIC; + SIGNAL wire_nl1liilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1liiO_dataout : STD_LOGIC; + SIGNAL wire_nl1liiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1liiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1liiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1liiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1liiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1liiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOii_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOil_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOli_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOll_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lil00i_dataout : STD_LOGIC; + SIGNAL wire_nl1lil00l_dataout : STD_LOGIC; + SIGNAL wire_nl1lil00O_dataout : STD_LOGIC; + SIGNAL wire_nl1lil01i_dataout : STD_LOGIC; + SIGNAL wire_nl1lil01l_dataout : STD_LOGIC; + SIGNAL wire_nl1lil01O_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0il_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0li_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lil0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lil10i_dataout : STD_LOGIC; + SIGNAL wire_nl1lil10l_dataout : STD_LOGIC; + SIGNAL wire_nl1lil10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lil11i_dataout : STD_LOGIC; + SIGNAL wire_nl1lil11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lil11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1li_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lil1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lili_dataout : STD_LOGIC; + SIGNAL wire_nl1lili0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lili0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lili0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lili1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lili1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lili1O_dataout : STD_LOGIC; + SIGNAL wire_nl1liliii_dataout : STD_LOGIC; + SIGNAL wire_nl1liliil_dataout : STD_LOGIC; + SIGNAL wire_nl1liliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lilil_dataout : STD_LOGIC; + SIGNAL wire_nl1lilili_dataout : STD_LOGIC; + SIGNAL wire_nl1lilill_dataout : STD_LOGIC; + SIGNAL wire_nl1lililO_dataout : STD_LOGIC; + SIGNAL wire_nl1liliO_dataout : STD_LOGIC; + SIGNAL wire_nl1liliOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liliOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lill_dataout : STD_LOGIC; + SIGNAL wire_nl1lill0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lill0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lill0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lill1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lill1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lill1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lilli_dataout : STD_LOGIC; + SIGNAL wire_nl1lillii_dataout : STD_LOGIC; + SIGNAL wire_nl1lillil_dataout : STD_LOGIC; + SIGNAL wire_nl1lilliO_dataout : STD_LOGIC; + SIGNAL wire_nl1lilll_dataout : STD_LOGIC; + SIGNAL wire_nl1lillli_dataout : STD_LOGIC; + SIGNAL wire_nl1lillO_dataout : STD_LOGIC; + SIGNAL wire_nl1lilO_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOii_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOil_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1liO00i_dataout : STD_LOGIC; + SIGNAL wire_nl1liO00l_dataout : STD_LOGIC; + SIGNAL wire_nl1liO00O_dataout : STD_LOGIC; + SIGNAL wire_nl1liO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1liO01l_dataout : STD_LOGIC; + SIGNAL wire_nl1liO01O_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0il_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0li_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1liO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1liO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1liO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1liO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1liO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1liO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1liO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1liO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1liOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1liOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1liOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1liOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1liOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1liOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1liOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1liOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOil_dataout : STD_LOGIC; + SIGNAL wire_nl1liOili_dataout : STD_LOGIC; + SIGNAL wire_nl1liOill_dataout : STD_LOGIC; + SIGNAL wire_nl1liOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1liOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1liOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1liOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1liOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1liOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1liOli_dataout : STD_LOGIC; + SIGNAL wire_nl1liOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1liOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1liOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1liOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1liOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1liOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1liOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1liOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1liOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1liOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1liOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll010i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll010l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll010O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll011i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll011l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll011O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll01i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll01l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ll0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll100i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll100l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll100O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll101i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll101l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll101O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10il_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10li_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ll10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll110i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll110l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll110O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll111i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll111l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll111O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11il_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11li_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ll11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1il_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1li_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1ll1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lli00l_dataout : STD_LOGIC; + SIGNAL wire_nl1lli00O_dataout : STD_LOGIC; + SIGNAL wire_nl1lli01i_dataout : STD_LOGIC; + SIGNAL wire_nl1lli01l_dataout : STD_LOGIC; + SIGNAL wire_nl1lli0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lli0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lli0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lli0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lli10i_dataout : STD_LOGIC; + SIGNAL wire_nl1lli10l_dataout : STD_LOGIC; + SIGNAL wire_nl1lli10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lli11i_dataout : STD_LOGIC; + SIGNAL wire_nl1lli11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lli11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lli1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lli1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lli1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lli1O_dataout : STD_LOGIC; + SIGNAL wire_nl1llii_dataout : STD_LOGIC; + SIGNAL wire_nl1lliii_dataout : STD_LOGIC; + SIGNAL wire_nl1lliil_dataout : STD_LOGIC; + SIGNAL wire_nl1lliill_dataout : STD_LOGIC; + SIGNAL wire_nl1lliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1llil_dataout : STD_LOGIC; + SIGNAL wire_nl1lliO_dataout : STD_LOGIC; + SIGNAL wire_nl1lliO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOii_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOil_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lliOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lll00i_dataout : STD_LOGIC; + SIGNAL wire_nl1lll00l_dataout : STD_LOGIC; + SIGNAL wire_nl1lll00O_dataout : STD_LOGIC; + SIGNAL wire_nl1lll01i_dataout : STD_LOGIC; + SIGNAL wire_nl1lll01l_dataout : STD_LOGIC; + SIGNAL wire_nl1lll01O_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0il_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0li_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lll0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lll10i_dataout : STD_LOGIC; + SIGNAL wire_nl1lll10l_dataout : STD_LOGIC; + SIGNAL wire_nl1lll10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lll11i_dataout : STD_LOGIC; + SIGNAL wire_nl1lll11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lll11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1li_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1llli_dataout : STD_LOGIC; + SIGNAL wire_nl1llli0i_dataout : STD_LOGIC; + SIGNAL wire_nl1llli0l_dataout : STD_LOGIC; + SIGNAL wire_nl1llli0O_dataout : STD_LOGIC; + SIGNAL wire_nl1llli1i_dataout : STD_LOGIC; + SIGNAL wire_nl1llli1l_dataout : STD_LOGIC; + SIGNAL wire_nl1llli1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lllii_dataout : STD_LOGIC; + SIGNAL wire_nl1llliii_dataout : STD_LOGIC; + SIGNAL wire_nl1llliil_dataout : STD_LOGIC; + SIGNAL wire_nl1llliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lllil_dataout : STD_LOGIC; + SIGNAL wire_nl1lllili_dataout : STD_LOGIC; + SIGNAL wire_nl1lllill_dataout : STD_LOGIC; + SIGNAL wire_nl1lllilO_dataout : STD_LOGIC; + SIGNAL wire_nl1llliO_dataout : STD_LOGIC; + SIGNAL wire_nl1llliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1llll_dataout : STD_LOGIC; + SIGNAL wire_nl1llll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1llll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1llll0O_dataout : STD_LOGIC; + SIGNAL wire_nl1llll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1llll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1llll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1llllOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lllO_dataout : STD_LOGIC; + SIGNAL wire_nl1lllO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lllO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lllO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lllO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lllO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lllO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOii_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOil_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lllOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1llO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1llO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1llO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1llO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1llO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1llO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1llO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1llO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1llO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1llO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1llOi_dataout : STD_LOGIC; + SIGNAL wire_nl1llOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1llOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1llOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1llOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1llOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1llOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1llOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1llOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1llOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1llOili_dataout : STD_LOGIC; + SIGNAL wire_nl1llOill_dataout : STD_LOGIC; + SIGNAL wire_nl1llOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1llOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1llOl_dataout : STD_LOGIC; + SIGNAL wire_nl1llOli_dataout : STD_LOGIC; + SIGNAL wire_nl1llOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1llOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1llOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1llOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1llOO_dataout : STD_LOGIC; + SIGNAL wire_nl1llOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1llOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1llOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1llOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1llOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1llOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1llOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO000i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO000l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO000O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO001i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO001l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO001O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00il_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00li_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lO00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO010i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO010l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO010O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO011i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO011l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO011O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01il_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01li_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lO01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w56945w56951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w55288w55289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0i0i_w_lg_w_lg_dataout55287w56945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0i0i_w_lg_w_lg_dataout55287w55288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0i0i_w_lg_dataout55287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i1i_w_lg_dataout56948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i1l_w_lg_dataout56946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0i1O_w_lg_dataout56944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lO0iii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0ili_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0li_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO100i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO100l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO100O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO101i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO101l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO101O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10il_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10li_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lO10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO110i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO111i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO111l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO111O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11li_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lO11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi00i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi00l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi00O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi01i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi01l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi01O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0il_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0li_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi10i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi10l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi11i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1li_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiiii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiiil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiili_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiill_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiilO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOil0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOil0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOil1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOil1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiliO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOillO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl00i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl00l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl00O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl01i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl01l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl01O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0il_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0li_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl10i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl10l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl11i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOli0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOli0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOli0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOli1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOli1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOli1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOliii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOliil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlili_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlill_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlilO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOliOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOliOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOll0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlliO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlllO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOllOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO00i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO00l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO00O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO01l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO01O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0il_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0li_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO10i_w_lg_dataout52155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO10l_w_lg_dataout52147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO10O_w52150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO10O_w_lg_w_lg_w_lg_dataout52141w52148w52149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO10O_w_lg_w_lg_w_lg_dataout52141w52142w52151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO10O_w_lg_w_lg_dataout52141w52148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO10O_w_lg_w_lg_dataout52141w52142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO10O_w_lg_dataout52141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO11O_w_lg_dataout52144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1ii_w_lg_dataout52322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1il_w_lg_dataout52291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1iO_w_lg_dataout52298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1li_w_lg_w_lg_w52301w52318w52319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w52301w52318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w52301w52302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w52323w52324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w52301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w52309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w52323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w52293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52299w52300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52299w52308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52290w52292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w_lg_dataout52289w52299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_w_lg_dataout52289w52290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1li_w_lg_dataout52289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1ll_w_lg_dataout56970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1lO_w_lg_dataout56968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1Oi_w_lg_dataout56966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1lOO1Ol_w_lg_dataout56965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOi0l_w_lg_w_lg_dataout52550w55799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOi0l_w_lg_dataout55804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOi0l_w_lg_dataout52550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOi0O_w_lg_dataout52548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiii_w_lg_dataout52546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiil_w_lg_dataout52544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiiO_w_lg_dataout52542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOili_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOili_w_lg_dataout52540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOill_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOill_w_lg_dataout52538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOilO_w_lg_dataout52536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiOi_w_lg_dataout52534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiOl_w_lg_w_lg_w52547w52549w52552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_w52547w52549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_w52547w56985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w52547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_w_lg_w_lg_w52539w52541w52543w52545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_w_lg_w52539w52541w52543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_w52539w52541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w52539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_w_lg_w_lg_dataout52533w52535w52537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_w_lg_dataout52533w52535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOl_w_lg_dataout52533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOiOO_w_lg_dataout56960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOl0i_w_lg_dataout52050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl0l_w_lg_dataout55800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl0l_w_lg_dataout55805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl0l_w_lg_dataout54725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOl1i_w_lg_dataout56962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlOi_w_lg_dataout55789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOlOi_w_lg_dataout55410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOlOi_w_lg_dataout55417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlOl_w_lg_dataout52282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOlOO_w_lg_dataout52012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_w_lg_w_lg_dataout5075w52330w52331w52332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_w_lg_dataout5075w52330w52331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_dataout5075w52330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_dataout5075w5688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_dataout56210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_dataout55790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_dataout5075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0i_w_lg_dataout5689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout54760w56981w56982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout52008w56221w56222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_dataout54760w56981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_dataout52008w54761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_dataout52008w55818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_dataout52008w52009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_dataout52008w56221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_dataout54760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_dataout52008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout52008w52009w52010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOO1i_w_lg_dataout5085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOO1l_w_lg_dataout5083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOO1O_w_lg_w_lg_w_lg_w_lg_dataout5082w5084w5086w52281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_w_lg_w_lg_w_lg_dataout5082w56204w56205w56206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w5086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w52011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w56204w56205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_w_lg_dataout5082w5084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_w_lg_dataout5082w56204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_dataout56209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOO1O_w_lg_dataout5082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1lOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1lOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O000l_dataout : STD_LOGIC; + SIGNAL wire_nl1O001i_dataout : STD_LOGIC; + SIGNAL wire_nl1O001O_dataout : STD_LOGIC; + SIGNAL wire_nl1O00i_dataout : STD_LOGIC; + SIGNAL wire_nl1O00il_dataout : STD_LOGIC; + SIGNAL wire_nl1O00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O00l_dataout : STD_LOGIC; + SIGNAL wire_nl1O00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O00O_dataout : STD_LOGIC; + SIGNAL wire_nl1O00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O010i_dataout : STD_LOGIC; + SIGNAL wire_nl1O011l_dataout : STD_LOGIC; + SIGNAL wire_nl1O011O_dataout : STD_LOGIC; + SIGNAL wire_nl1O01i_dataout : STD_LOGIC; + SIGNAL wire_nl1O01il_dataout : STD_LOGIC; + SIGNAL wire_nl1O01l_dataout : STD_LOGIC; + SIGNAL wire_nl1O01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O01O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iiil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iili_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iill_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iilO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0il1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ilii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ilil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iliO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1O0illi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0illl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0illO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOli_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l00i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l00l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l00O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l01i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l01l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l01O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0il_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0li_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l10i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l10l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l10O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l11i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l11l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l11O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1il_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1li_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0li1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0liii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0liil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0liiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lili_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lill_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lilO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0liOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0liOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0liOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lliO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llli_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lllO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0llOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOli_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O00i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O00l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O00O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O01i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O01l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O01O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0il_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0li_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O10i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O10l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O10O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O11i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O11l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O11O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1il_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1li_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oili_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oill_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OilO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Olii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Olil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OliO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Olli_dataout : STD_LOGIC; + SIGNAL wire_nl1O0Olll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OllO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOii_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOil_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOli_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOll_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1000i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1000l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1000O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1001i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1001l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1001O_dataout : STD_LOGIC; + SIGNAL wire_nl1O100ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O100il_dataout : STD_LOGIC; + SIGNAL wire_nl1O100iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O100li_dataout : STD_LOGIC; + SIGNAL wire_nl1O100ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O100lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O100Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O100Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O100OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1010i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1010l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1010O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1011i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1011l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1011O_dataout : STD_LOGIC; + SIGNAL wire_nl1O101ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O101il_dataout : STD_LOGIC; + SIGNAL wire_nl1O101iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O101li_dataout : STD_LOGIC; + SIGNAL wire_nl1O101ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O101lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O101Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O101Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O101OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10i_dataout : STD_LOGIC; + SIGNAL wire_nl1O10i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O10i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O10i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O10i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O10i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O10i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O10iii_dataout : STD_LOGIC; + SIGNAL wire_nl1O10iil_dataout : STD_LOGIC; + SIGNAL wire_nl1O10iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10ili_dataout : STD_LOGIC; + SIGNAL wire_nl1O10ill_dataout : STD_LOGIC; + SIGNAL wire_nl1O10ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O10iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O10iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10l_dataout : STD_LOGIC; + SIGNAL wire_nl1O10l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O10l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O10l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O10l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O10l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O10l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lii_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lil_dataout : STD_LOGIC; + SIGNAL wire_nl1O10liO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lli_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lll_dataout : STD_LOGIC; + SIGNAL wire_nl1O10llO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O10lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10O_dataout : STD_LOGIC; + SIGNAL wire_nl1O10O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O10O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O10O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O10O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O10O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O10O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O10Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1O10Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1O10OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O10Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1O10Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1O10OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O10OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O10OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O10OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1100i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1100l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1100O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1101i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1101l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1101O_dataout : STD_LOGIC; + SIGNAL wire_nl1O110ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O110il_dataout : STD_LOGIC; + SIGNAL wire_nl1O110iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O110li_dataout : STD_LOGIC; + SIGNAL wire_nl1O110ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O110lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O110Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O110Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O110OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1110i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1110l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1110O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1111i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1111l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1111O_dataout : STD_LOGIC; + SIGNAL wire_nl1O111i_dataout : STD_LOGIC; + SIGNAL wire_nl1O111ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O111il_dataout : STD_LOGIC; + SIGNAL wire_nl1O111iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O111l_dataout : STD_LOGIC; + SIGNAL wire_nl1O111li_dataout : STD_LOGIC; + SIGNAL wire_nl1O111ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O111lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O111O_dataout : STD_LOGIC; + SIGNAL wire_nl1O111Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O111Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O111OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11i_dataout : STD_LOGIC; + SIGNAL wire_nl1O11i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O11i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O11i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O11i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O11i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O11i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O11iii_dataout : STD_LOGIC; + SIGNAL wire_nl1O11iil_dataout : STD_LOGIC; + SIGNAL wire_nl1O11iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11il_dataout : STD_LOGIC; + SIGNAL wire_nl1O11ili_dataout : STD_LOGIC; + SIGNAL wire_nl1O11ill_dataout : STD_LOGIC; + SIGNAL wire_nl1O11ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O11iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O11iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11l_dataout : STD_LOGIC; + SIGNAL wire_nl1O11l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O11l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O11l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O11l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O11l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O11l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O11li_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lii_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lil_dataout : STD_LOGIC; + SIGNAL wire_nl1O11liO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lli_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lll_dataout : STD_LOGIC; + SIGNAL wire_nl1O11llO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O11lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11O_dataout : STD_LOGIC; + SIGNAL wire_nl1O11O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1O11O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O11O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O11O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O11O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O11O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O11Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1O11Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1O11OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O11Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1O11Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1O11OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O11OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O11OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O11OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i00i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i00l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i00O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i01i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i01l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i01O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0il_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0li_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i10i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i10l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i10O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i11i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i11l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i11O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1il_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1li_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1O1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1il_dataout : STD_LOGIC; + SIGNAL wire_nl1O1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1li_dataout : STD_LOGIC; + SIGNAL wire_nl1O1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1O1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1O1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1O1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1O1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi000i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi000l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi000O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi001i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi001l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi001O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi010i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi010l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi010O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi011i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi011l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi011O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0iii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0ili_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi100i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi100l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi100O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi101i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi101l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi101O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi110i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi110l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi110O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi111i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi111l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi111O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1liO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1llO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Oi1OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii00i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii00l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii00O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii01i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii01l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii01O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii10i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii10l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii10O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii11i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii11l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii11O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oii1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiiiii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiiiil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiiili_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiiill_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiil0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiil0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiil1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiil1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiili_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiilii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiilil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiliO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiilli_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiilll_dataout : STD_LOGIC; + SIGNAL wire_nl1OiillO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil00i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil00l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil00O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil01i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil01l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil01O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil10i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil10l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil10O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil11i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil11l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil11O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oil1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oili_dataout : STD_LOGIC; + SIGNAL wire_nl1Oili0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oili0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oili0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oili1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oili1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oili1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiliii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oiliil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oilili_dataout : STD_LOGIC; + SIGNAL wire_nl1Oilill_dataout : STD_LOGIC; + SIGNAL wire_nl1OililO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiliOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiliOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oill_dataout : STD_LOGIC; + SIGNAL wire_nl1Oill0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oill1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oill1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oill1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oilli_dataout : STD_LOGIC; + SIGNAL wire_nl1OillO_dataout : STD_LOGIC; + SIGNAL wire_nl1OilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OilOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO0li_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO11O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol000i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol000l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol000O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol001i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol001l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol001O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00il_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00li_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol010i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol010l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol010O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01il_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01li_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0il_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0liO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0llO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0lOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0lOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0lOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0O0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0O0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0O0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0O1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0O1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0O1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0Oii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0Oil_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0OiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0Oli_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0Oll_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0OlO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0OOi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0OOl_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol0OOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol100i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol100l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol100O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol101i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol101O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10il_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10li_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol110i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol110l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol110O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol111i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol111l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol111O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11il_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11li_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1iii_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1iil_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1ili_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1ill_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1ill_w_lg_dataout55398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1Ol1ill_w_lg_dataout54875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli00i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli00l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli00O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli01i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli01l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli01O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli10i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli10l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli10O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli11i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli11l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli11O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oli1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Olii_dataout : STD_LOGIC; + SIGNAL wire_nl1Olii0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olii0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Olii0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Olii1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olii1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Olii1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oliii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oliiii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oliiil_dataout : STD_LOGIC; + SIGNAL wire_nl1OliiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oliil_dataout : STD_LOGIC; + SIGNAL wire_nl1Oliili_dataout : STD_LOGIC; + SIGNAL wire_nl1Oliill_dataout : STD_LOGIC; + SIGNAL wire_nl1OliilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OliiOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OliiOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OliiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Olil_dataout : STD_LOGIC; + SIGNAL wire_nl1Olil0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olil0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Olil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Olil1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olil1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Olil1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Olilii_dataout : STD_LOGIC; + SIGNAL wire_nl1Olilil_dataout : STD_LOGIC; + SIGNAL wire_nl1OliliO_dataout : STD_LOGIC; + SIGNAL wire_nl1Olilli_dataout : STD_LOGIC; + SIGNAL wire_nl1Olilll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlillO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OliO_dataout : STD_LOGIC; + SIGNAL wire_nl1OliO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OliO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OliO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OliO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OliO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OliOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll00i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll00l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll00O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll01i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll01l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll01O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll10i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll10l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll10O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll11i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll11l_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll11O_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1il_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1li_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1Oll1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1Olli_dataout : STD_LOGIC; + SIGNAL wire_nl1Olli0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olli0l_dataout : STD_LOGIC; + SIGNAL wire_nl1Olli0O_dataout : STD_LOGIC; + SIGNAL wire_nl1Olli1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olli1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Olli1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Ollii_dataout : STD_LOGIC; + SIGNAL wire_nl1Olliii_dataout : STD_LOGIC; + SIGNAL wire_nl1Olliil_dataout : STD_LOGIC; + SIGNAL wire_nl1OlliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1Ollili_dataout : STD_LOGIC; + SIGNAL wire_nl1Ollill_dataout : STD_LOGIC; + SIGNAL wire_nl1OllilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlliO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlliOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OlliOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OlliOO_dataout : STD_LOGIC; + SIGNAL wire_nl1Olll_dataout : STD_LOGIC; + SIGNAL wire_nl1Olll0i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1Olll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1Olll1O_dataout : STD_LOGIC; + SIGNAL wire_nl1Olllii_dataout : STD_LOGIC; + SIGNAL wire_nl1Olllil_dataout : STD_LOGIC; + SIGNAL wire_nl1OllliO_dataout : STD_LOGIC; + SIGNAL wire_nl1Olllli_dataout : STD_LOGIC; + SIGNAL wire_nl1Olllll_dataout : STD_LOGIC; + SIGNAL wire_nl1OllllO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlllO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlllOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OlllOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OlllOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OllO_dataout : STD_LOGIC; + SIGNAL wire_nl1OllO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OllO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OllO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OllO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OllOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OllOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OllOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OllOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OllOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OllOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OllOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO01l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOi1l_w_lg_dataout55402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1OlOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOiOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOl1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OlOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO000i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO000l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO000O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO001i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO001l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO001O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00il_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00li_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO00OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01il_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01li_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO01OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0iii_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0iil_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0ili_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0ill_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0lii_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0lil_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0lli_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0lll_dataout : STD_LOGIC; + SIGNAL wire_nl1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO100i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO100l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO100O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO101i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO101l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO101O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10il_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10li_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO10OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO110i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO110l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO110O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO111i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO111l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO111O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11il_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11li_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OO11OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi10i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi10i_w_lg_dataout56727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1OOi10l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi10l_w_lg_dataout56726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1OOi11l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOi11O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOil0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOil0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOil0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOilii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOilil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiliO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOilli_dataout : STD_LOGIC; + SIGNAL wire_nl1OOilll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOillO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOilOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOilOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOilOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl00i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl00l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl00O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl01i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl01l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl01O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0il_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0li_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl10i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl10l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl10O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl11i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl11l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl11O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1il_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1li_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOli0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOli0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOli0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOli1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOli1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOli1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOliii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOliil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOliiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlili_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlill_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOliOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOliOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOll1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOll1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOllli_dataout : STD_LOGIC; + SIGNAL wire_nl1OOllll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOllOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOllOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO00i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO00l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO00O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO01i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO01l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO01O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO0li_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO10i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO10l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO10O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO11i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1il_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1li_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nl1OOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOiii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOiil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOili_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOill_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOilO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOliO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlli_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOllO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOii_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOil_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOli_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOll_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nl1OOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0000i_dataout : STD_LOGIC; + SIGNAL wire_nli0000l_dataout : STD_LOGIC; + SIGNAL wire_nli0000O_dataout : STD_LOGIC; + SIGNAL wire_nli0001i_dataout : STD_LOGIC; + SIGNAL wire_nli0001l_dataout : STD_LOGIC; + SIGNAL wire_nli0001O_dataout : STD_LOGIC; + SIGNAL wire_nli000ii_dataout : STD_LOGIC; + SIGNAL wire_nli000il_dataout : STD_LOGIC; + SIGNAL wire_nli000iO_dataout : STD_LOGIC; + SIGNAL wire_nli000li_dataout : STD_LOGIC; + SIGNAL wire_nli000ll_dataout : STD_LOGIC; + SIGNAL wire_nli000lO_dataout : STD_LOGIC; + SIGNAL wire_nli000Oi_dataout : STD_LOGIC; + SIGNAL wire_nli000Ol_dataout : STD_LOGIC; + SIGNAL wire_nli000Oli_dataout : STD_LOGIC; + SIGNAL wire_nli000Oli_w_lg_dataout47728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000Oli_w_lg_w_lg_dataout47728w47729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000Oll_dataout : STD_LOGIC; + SIGNAL wire_nli000Oll_w_lg_dataout47689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000Oll_w_lg_w_lg_dataout47689w47690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OlO_dataout : STD_LOGIC; + SIGNAL wire_nli000OlO_w_lg_dataout47655w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OlO_w_lg_w_lg_dataout47655w47656w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OO_dataout : STD_LOGIC; + SIGNAL wire_nli000OOi_dataout : STD_LOGIC; + SIGNAL wire_nli000OOi_w_lg_dataout47621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OOi_w_lg_w_lg_dataout47621w47622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OOl_dataout : STD_LOGIC; + SIGNAL wire_nli000OOl_w_lg_dataout47587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OOl_w_lg_w_lg_dataout47587w47588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OOO_dataout : STD_LOGIC; + SIGNAL wire_nli000OOO_w_lg_dataout47553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli000OOO_w_lg_w_lg_dataout47553w47554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0010i_dataout : STD_LOGIC; + SIGNAL wire_nli0010l_dataout : STD_LOGIC; + SIGNAL wire_nli0010O_dataout : STD_LOGIC; + SIGNAL wire_nli0011i_dataout : STD_LOGIC; + SIGNAL wire_nli0011l_dataout : STD_LOGIC; + SIGNAL wire_nli0011O_dataout : STD_LOGIC; + SIGNAL wire_nli001ii_dataout : STD_LOGIC; + SIGNAL wire_nli001il_dataout : STD_LOGIC; + SIGNAL wire_nli001iO_dataout : STD_LOGIC; + SIGNAL wire_nli001li_dataout : STD_LOGIC; + SIGNAL wire_nli001ll_dataout : STD_LOGIC; + SIGNAL wire_nli001lO_dataout : STD_LOGIC; + SIGNAL wire_nli001Oi_dataout : STD_LOGIC; + SIGNAL wire_nli001Ol_dataout : STD_LOGIC; + SIGNAL wire_nli001OO_dataout : STD_LOGIC; + SIGNAL wire_nli00i00i_dataout : STD_LOGIC; + SIGNAL wire_nli00i00i_w_lg_dataout46968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i00i_w_lg_w_lg_dataout46968w46969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i00l_dataout : STD_LOGIC; + SIGNAL wire_nli00i00l_w_lg_dataout46938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i00l_w_lg_w_lg_dataout46938w46939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i00O_dataout : STD_LOGIC; + SIGNAL wire_nli00i00O_w_lg_dataout46909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i00O_w_lg_w_lg_dataout46909w46910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i01i_dataout : STD_LOGIC; + SIGNAL wire_nli00i01i_w_lg_dataout47055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i01i_w_lg_w_lg_dataout47055w47056w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i01l_dataout : STD_LOGIC; + SIGNAL wire_nli00i01l_w_lg_dataout47025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i01l_w_lg_w_lg_dataout47025w47026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i01O_dataout : STD_LOGIC; + SIGNAL wire_nli00i01O_w_lg_dataout46996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i01O_w_lg_w_lg_dataout46996w46997w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0i_dataout : STD_LOGIC; + SIGNAL wire_nli00i0ii_dataout : STD_LOGIC; + SIGNAL wire_nli00i0ii_w_lg_dataout46881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0ii_w_lg_w_lg_dataout46881w46882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0il_dataout : STD_LOGIC; + SIGNAL wire_nli00i0il_w_lg_dataout46853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0il_w_lg_w_lg_dataout46853w46854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0iO_dataout : STD_LOGIC; + SIGNAL wire_nli00i0iO_w_lg_dataout46826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0iO_w_lg_w_lg_dataout46826w46827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0l_dataout : STD_LOGIC; + SIGNAL wire_nli00i0li_dataout : STD_LOGIC; + SIGNAL wire_nli00i0li_w_lg_dataout46799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0li_w_lg_w_lg_dataout46799w46800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0ll_dataout : STD_LOGIC; + SIGNAL wire_nli00i0ll_w_lg_dataout46772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0ll_w_lg_w_lg_dataout46772w46773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0lO_dataout : STD_LOGIC; + SIGNAL wire_nli00i0lO_w_lg_dataout47727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0O_dataout : STD_LOGIC; + SIGNAL wire_nli00i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli00i0Oi_w_lg_dataout47654w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli00i0Ol_w_lg_dataout47620w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0OO_dataout : STD_LOGIC; + SIGNAL wire_nli00i0OO_w_lg_dataout47714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i0OO_w_lg_w_lg_dataout47714w47715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i10i_dataout : STD_LOGIC; + SIGNAL wire_nli00i10i_w_lg_dataout47426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i10i_w_lg_w_lg_dataout47426w47427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i10l_dataout : STD_LOGIC; + SIGNAL wire_nli00i10l_w_lg_dataout47397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i10l_w_lg_w_lg_dataout47397w47398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i10O_dataout : STD_LOGIC; + SIGNAL wire_nli00i10O_w_lg_dataout47366w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i10O_w_lg_w_lg_dataout47366w47367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i11i_dataout : STD_LOGIC; + SIGNAL wire_nli00i11i_w_lg_dataout47522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i11i_w_lg_w_lg_dataout47522w47523w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i11l_dataout : STD_LOGIC; + SIGNAL wire_nli00i11l_w_lg_dataout47488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i11l_w_lg_w_lg_dataout47488w47489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i11O_dataout : STD_LOGIC; + SIGNAL wire_nli00i11O_w_lg_dataout47458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i11O_w_lg_w_lg_dataout47458w47459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1i_dataout : STD_LOGIC; + SIGNAL wire_nli00i1ii_dataout : STD_LOGIC; + SIGNAL wire_nli00i1ii_w_lg_dataout47335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1ii_w_lg_w_lg_dataout47335w47336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1il_dataout : STD_LOGIC; + SIGNAL wire_nli00i1il_w_lg_dataout47304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1il_w_lg_w_lg_dataout47304w47305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1iO_dataout : STD_LOGIC; + SIGNAL wire_nli00i1iO_w_lg_dataout47274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1iO_w_lg_w_lg_dataout47274w47275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1l_dataout : STD_LOGIC; + SIGNAL wire_nli00i1li_dataout : STD_LOGIC; + SIGNAL wire_nli00i1li_w_lg_dataout47241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1li_w_lg_w_lg_dataout47241w47242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1ll_dataout : STD_LOGIC; + SIGNAL wire_nli00i1ll_w_lg_dataout47212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1ll_w_lg_w_lg_dataout47212w47213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1lO_dataout : STD_LOGIC; + SIGNAL wire_nli00i1lO_w_lg_dataout47179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1lO_w_lg_w_lg_dataout47179w47180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1O_dataout : STD_LOGIC; + SIGNAL wire_nli00i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli00i1Oi_w_lg_dataout47147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1Oi_w_lg_w_lg_dataout47147w47148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli00i1Ol_w_lg_dataout47119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1Ol_w_lg_w_lg_dataout47119w47120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1OO_dataout : STD_LOGIC; + SIGNAL wire_nli00i1OO_w_lg_dataout47088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00i1OO_w_lg_w_lg_dataout47088w47089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii0i_dataout : STD_LOGIC; + SIGNAL wire_nli00ii0i_w_lg_dataout47575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii0i_w_lg_w_lg_dataout47575w47576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii0l_dataout : STD_LOGIC; + SIGNAL wire_nli00ii0l_w_lg_dataout47544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii0l_w_lg_w_lg_dataout47544w47545w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii0O_dataout : STD_LOGIC; + SIGNAL wire_nli00ii0O_w_lg_dataout47512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii0O_w_lg_w_lg_dataout47512w47513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii1i_dataout : STD_LOGIC; + SIGNAL wire_nli00ii1i_w_lg_dataout47676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii1i_w_lg_w_lg_dataout47676w47677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii1l_dataout : STD_LOGIC; + SIGNAL wire_nli00ii1l_w_lg_dataout47643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii1l_w_lg_w_lg_dataout47643w47644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii1O_dataout : STD_LOGIC; + SIGNAL wire_nli00ii1O_w_lg_dataout47609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ii1O_w_lg_w_lg_dataout47609w47610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iii_dataout : STD_LOGIC; + SIGNAL wire_nli00iiii_dataout : STD_LOGIC; + SIGNAL wire_nli00iiii_w_lg_dataout47478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiii_w_lg_w_lg_dataout47478w47479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiil_dataout : STD_LOGIC; + SIGNAL wire_nli00iiil_w_lg_dataout47448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiil_w_lg_w_lg_dataout47448w47449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiiO_dataout : STD_LOGIC; + SIGNAL wire_nli00iiiO_w_lg_dataout47417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiiO_w_lg_w_lg_dataout47417w47418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iil_dataout : STD_LOGIC; + SIGNAL wire_nli00iili_dataout : STD_LOGIC; + SIGNAL wire_nli00iili_w_lg_dataout47387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iili_w_lg_w_lg_dataout47387w47388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iill_dataout : STD_LOGIC; + SIGNAL wire_nli00iill_w_lg_dataout47357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iill_w_lg_w_lg_dataout47357w47358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iilO_dataout : STD_LOGIC; + SIGNAL wire_nli00iilO_w_lg_dataout47326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iilO_w_lg_w_lg_dataout47326w47327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiO_dataout : STD_LOGIC; + SIGNAL wire_nli00iiOi_dataout : STD_LOGIC; + SIGNAL wire_nli00iiOi_w_lg_dataout47297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiOi_w_lg_w_lg_dataout47297w47298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiOl_dataout : STD_LOGIC; + SIGNAL wire_nli00iiOl_w_lg_dataout47266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiOl_w_lg_w_lg_dataout47266w47267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiOO_dataout : STD_LOGIC; + SIGNAL wire_nli00iiOO_w_lg_dataout47233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iiOO_w_lg_w_lg_dataout47233w47234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il0i_dataout : STD_LOGIC; + SIGNAL wire_nli00il0i_w_lg_dataout47111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il0i_w_lg_w_lg_dataout47111w47112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il0l_dataout : STD_LOGIC; + SIGNAL wire_nli00il0l_w_lg_dataout47079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il0l_w_lg_w_lg_dataout47079w47080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il0O_dataout : STD_LOGIC; + SIGNAL wire_nli00il0O_w_lg_dataout47046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il0O_w_lg_w_lg_dataout47046w47047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il1i_dataout : STD_LOGIC; + SIGNAL wire_nli00il1i_w_lg_dataout47202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il1i_w_lg_w_lg_dataout47202w47203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il1l_dataout : STD_LOGIC; + SIGNAL wire_nli00il1l_w_lg_dataout47170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il1l_w_lg_w_lg_dataout47170w47171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il1O_dataout : STD_LOGIC; + SIGNAL wire_nli00il1O_w_lg_dataout47139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00il1O_w_lg_w_lg_dataout47139w47140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ili_dataout : STD_LOGIC; + SIGNAL wire_nli00ilii_dataout : STD_LOGIC; + SIGNAL wire_nli00ilii_w_lg_dataout47018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilii_w_lg_w_lg_dataout47018w47019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilil_dataout : STD_LOGIC; + SIGNAL wire_nli00ilil_w_lg_dataout46990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilil_w_lg_w_lg_dataout46990w46991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iliO_dataout : STD_LOGIC; + SIGNAL wire_nli00iliO_w_lg_dataout46961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iliO_w_lg_w_lg_dataout46961w46962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ill_dataout : STD_LOGIC; + SIGNAL wire_nli00illi_dataout : STD_LOGIC; + SIGNAL wire_nli00illi_w_lg_dataout46932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00illi_w_lg_w_lg_dataout46932w46933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00illl_dataout : STD_LOGIC; + SIGNAL wire_nli00illl_w_lg_dataout46902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00illl_w_lg_w_lg_dataout46902w46903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00illO_dataout : STD_LOGIC; + SIGNAL wire_nli00illO_w_lg_dataout46874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00illO_w_lg_w_lg_dataout46874w46875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilO_dataout : STD_LOGIC; + SIGNAL wire_nli00ilOi_dataout : STD_LOGIC; + SIGNAL wire_nli00ilOi_w_lg_dataout46847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilOi_w_lg_w_lg_dataout46847w46848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilOl_dataout : STD_LOGIC; + SIGNAL wire_nli00ilOl_w_lg_dataout46820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilOl_w_lg_w_lg_dataout46820w46821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilOO_dataout : STD_LOGIC; + SIGNAL wire_nli00ilOO_w_lg_dataout46794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ilOO_w_lg_w_lg_dataout46794w46795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iO0i_dataout : STD_LOGIC; + SIGNAL wire_nli00iO0i_w_lg_dataout47642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iO0l_dataout : STD_LOGIC; + SIGNAL wire_nli00iO0l_w_lg_dataout47608w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iO0O_dataout : STD_LOGIC; + SIGNAL wire_nli00iO0O_w_lg_dataout47574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iO1i_dataout : STD_LOGIC; + SIGNAL wire_nli00iO1i_w_lg_dataout46767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iO1i_w_lg_w_lg_dataout46767w46768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iO1l_dataout : STD_LOGIC; + SIGNAL wire_nli00iO1l_w_lg_dataout47713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iO1O_dataout : STD_LOGIC; + SIGNAL wire_nli00iO1O_w_lg_dataout47675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOi_dataout : STD_LOGIC; + SIGNAL wire_nli00iOii_dataout : STD_LOGIC; + SIGNAL wire_nli00iOii_w_lg_dataout47543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOil_dataout : STD_LOGIC; + SIGNAL wire_nli00iOil_w_lg_dataout47511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOiO_dataout : STD_LOGIC; + SIGNAL wire_nli00iOiO_w_lg_dataout47477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOl_dataout : STD_LOGIC; + SIGNAL wire_nli00iOli_dataout : STD_LOGIC; + SIGNAL wire_nli00iOli_w_lg_dataout47447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOll_dataout : STD_LOGIC; + SIGNAL wire_nli00iOll_w_lg_dataout47416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOlO_dataout : STD_LOGIC; + SIGNAL wire_nli00iOlO_w_lg_dataout47386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOO_dataout : STD_LOGIC; + SIGNAL wire_nli00iOOi_dataout : STD_LOGIC; + SIGNAL wire_nli00iOOi_w_lg_dataout47356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOOl_dataout : STD_LOGIC; + SIGNAL wire_nli00iOOl_w_lg_dataout47325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00iOOO_dataout : STD_LOGIC; + SIGNAL wire_nli00iOOO_w_lg_dataout47296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l00i_dataout : STD_LOGIC; + SIGNAL wire_nli00l00i_w_lg_dataout47200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l00l_dataout : STD_LOGIC; + SIGNAL wire_nli00l00l_w_lg_dataout47168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l00O_dataout : STD_LOGIC; + SIGNAL wire_nli00l00O_w_lg_dataout47137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l01i_dataout : STD_LOGIC; + SIGNAL wire_nli00l01i_w_lg_dataout46819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l01l_dataout : STD_LOGIC; + SIGNAL wire_nli00l01l_w_lg_dataout46793w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l01O_dataout : STD_LOGIC; + SIGNAL wire_nli00l01O_w_lg_dataout46766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0i_dataout : STD_LOGIC; + SIGNAL wire_nli00l0ii_dataout : STD_LOGIC; + SIGNAL wire_nli00l0ii_w_lg_dataout47109w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0il_dataout : STD_LOGIC; + SIGNAL wire_nli00l0il_w_lg_dataout47077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0iO_dataout : STD_LOGIC; + SIGNAL wire_nli00l0iO_w_lg_dataout47044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0l_dataout : STD_LOGIC; + SIGNAL wire_nli00l0li_dataout : STD_LOGIC; + SIGNAL wire_nli00l0li_w_lg_dataout47016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0ll_dataout : STD_LOGIC; + SIGNAL wire_nli00l0ll_w_lg_dataout46988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0lO_dataout : STD_LOGIC; + SIGNAL wire_nli00l0lO_w_lg_dataout46959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0O_dataout : STD_LOGIC; + SIGNAL wire_nli00l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli00l0Oi_w_lg_dataout46930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli00l0Ol_w_lg_dataout46900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l0OO_dataout : STD_LOGIC; + SIGNAL wire_nli00l0OO_w_lg_dataout46792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l10i_dataout : STD_LOGIC; + SIGNAL wire_nli00l10i_w_lg_dataout47169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l10l_dataout : STD_LOGIC; + SIGNAL wire_nli00l10l_w_lg_dataout47138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l10O_dataout : STD_LOGIC; + SIGNAL wire_nli00l10O_w_lg_dataout47110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l11i_dataout : STD_LOGIC; + SIGNAL wire_nli00l11i_w_lg_dataout47265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l11l_dataout : STD_LOGIC; + SIGNAL wire_nli00l11l_w_lg_dataout47232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l11O_dataout : STD_LOGIC; + SIGNAL wire_nli00l11O_w_lg_dataout47201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1i_dataout : STD_LOGIC; + SIGNAL wire_nli00l1ii_dataout : STD_LOGIC; + SIGNAL wire_nli00l1ii_w_lg_dataout47078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1il_dataout : STD_LOGIC; + SIGNAL wire_nli00l1il_w_lg_dataout47045w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1iO_dataout : STD_LOGIC; + SIGNAL wire_nli00l1iO_w_lg_dataout47017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1l_dataout : STD_LOGIC; + SIGNAL wire_nli00l1li_dataout : STD_LOGIC; + SIGNAL wire_nli00l1li_w_lg_dataout46989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1ll_dataout : STD_LOGIC; + SIGNAL wire_nli00l1ll_w_lg_dataout46960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1lO_dataout : STD_LOGIC; + SIGNAL wire_nli00l1lO_w_lg_dataout46931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1O_dataout : STD_LOGIC; + SIGNAL wire_nli00l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli00l1Oi_w_lg_dataout46901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli00l1Ol_w_lg_dataout46873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00l1OO_dataout : STD_LOGIC; + SIGNAL wire_nli00l1OO_w_lg_dataout46846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00li0i_dataout : STD_LOGIC; + SIGNAL wire_nli00li0i_w_lg_dataout47653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00li0l_dataout : STD_LOGIC; + SIGNAL wire_nli00li0l_w_lg_dataout47619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00li0O_dataout : STD_LOGIC; + SIGNAL wire_nli00li0O_w_lg_dataout47586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00li1i_dataout : STD_LOGIC; + SIGNAL wire_nli00li1i_w_lg_dataout46765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00li1l_dataout : STD_LOGIC; + SIGNAL wire_nli00li1l_w_lg_dataout47726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00li1O_dataout : STD_LOGIC; + SIGNAL wire_nli00li1O_w_lg_dataout47688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lii_dataout : STD_LOGIC; + SIGNAL wire_nli00liii_dataout : STD_LOGIC; + SIGNAL wire_nli00liii_w_lg_dataout47552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00liil_dataout : STD_LOGIC; + SIGNAL wire_nli00liil_w_lg_dataout47521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00liiO_dataout : STD_LOGIC; + SIGNAL wire_nli00liiO_w_lg_dataout47487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lil_dataout : STD_LOGIC; + SIGNAL wire_nli00lili_dataout : STD_LOGIC; + SIGNAL wire_nli00lili_w_lg_dataout47457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lill_dataout : STD_LOGIC; + SIGNAL wire_nli00lill_w_lg_dataout47425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lilO_dataout : STD_LOGIC; + SIGNAL wire_nli00lilO_w_lg_dataout47396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00liO_dataout : STD_LOGIC; + SIGNAL wire_nli00liOi_dataout : STD_LOGIC; + SIGNAL wire_nli00liOi_w_lg_dataout47365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00liOl_dataout : STD_LOGIC; + SIGNAL wire_nli00liOl_w_lg_dataout47334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00liOO_dataout : STD_LOGIC; + SIGNAL wire_nli00liOO_w_lg_dataout47211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ll0i_dataout : STD_LOGIC; + SIGNAL wire_nli00ll0i_w_lg_dataout47618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ll0l_dataout : STD_LOGIC; + SIGNAL wire_nli00ll0l_w_lg_dataout47585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ll0O_dataout : STD_LOGIC; + SIGNAL wire_nli00ll0O_w_lg_dataout47724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ll1i_dataout : STD_LOGIC; + SIGNAL wire_nli00ll1i_w_lg_dataout47725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ll1l_dataout : STD_LOGIC; + SIGNAL wire_nli00ll1l_w_lg_dataout47687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00ll1O_dataout : STD_LOGIC; + SIGNAL wire_nli00ll1O_w_lg_dataout47652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lli_dataout : STD_LOGIC; + SIGNAL wire_nli00llii_dataout : STD_LOGIC; + SIGNAL wire_nli00llii_w_lg_dataout47686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00llil_dataout : STD_LOGIC; + SIGNAL wire_nli00llil_w_lg_dataout47651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lliO_dataout : STD_LOGIC; + SIGNAL wire_nli00lliO_w_lg_dataout47617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lll_dataout : STD_LOGIC; + SIGNAL wire_nli00llli_dataout : STD_LOGIC; + SIGNAL wire_nli00llli_w_lg_dataout47584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00llll_dataout : STD_LOGIC; + SIGNAL wire_nli00llll_w_lg_dataout47723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lllO_dataout : STD_LOGIC; + SIGNAL wire_nli00lllO_w_lg_dataout47685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00llO_dataout : STD_LOGIC; + SIGNAL wire_nli00llOi_dataout : STD_LOGIC; + SIGNAL wire_nli00llOi_w_lg_dataout47650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00llOl_dataout : STD_LOGIC; + SIGNAL wire_nli00llOl_w_lg_dataout47616w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00llOO_dataout : STD_LOGIC; + SIGNAL wire_nli00llOO_w_lg_dataout47583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lO0i_dataout : STD_LOGIC; + SIGNAL wire_nli00lO0i_w_lg_dataout47456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lO0l_dataout : STD_LOGIC; + SIGNAL wire_nli00lO0l_w_lg_dataout47424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lO0O_dataout : STD_LOGIC; + SIGNAL wire_nli00lO0O_w_lg_dataout47395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lO1i_dataout : STD_LOGIC; + SIGNAL wire_nli00lO1i_w_lg_dataout47551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lO1l_dataout : STD_LOGIC; + SIGNAL wire_nli00lO1l_w_lg_dataout47520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lO1O_dataout : STD_LOGIC; + SIGNAL wire_nli00lO1O_w_lg_dataout47486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOi_dataout : STD_LOGIC; + SIGNAL wire_nli00lOii_dataout : STD_LOGIC; + SIGNAL wire_nli00lOii_w_lg_dataout47364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOil_dataout : STD_LOGIC; + SIGNAL wire_nli00lOil_w_lg_dataout47333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOiO_dataout : STD_LOGIC; + SIGNAL wire_nli00lOiO_w_lg_dataout47303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOl_dataout : STD_LOGIC; + SIGNAL wire_nli00lOli_dataout : STD_LOGIC; + SIGNAL wire_nli00lOli_w_lg_dataout47273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOll_dataout : STD_LOGIC; + SIGNAL wire_nli00lOll_w_lg_dataout47240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOlO_dataout : STD_LOGIC; + SIGNAL wire_nli00lOlO_w_lg_dataout47210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOO_dataout : STD_LOGIC; + SIGNAL wire_nli00lOOi_dataout : STD_LOGIC; + SIGNAL wire_nli00lOOi_w_lg_dataout47178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOOl_dataout : STD_LOGIC; + SIGNAL wire_nli00lOOl_w_lg_dataout47722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00lOOO_dataout : STD_LOGIC; + SIGNAL wire_nli00lOOO_w_lg_dataout47684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O00i_dataout : STD_LOGIC; + SIGNAL wire_nli00O00i_w_lg_dataout47087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O00l_dataout : STD_LOGIC; + SIGNAL wire_nli00O00l_w_lg_dataout47054w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O00O_dataout : STD_LOGIC; + SIGNAL wire_nli00O00O_w_lg_dataout47024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O01i_dataout : STD_LOGIC; + SIGNAL wire_nli00O01i_w_lg_dataout47177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O01l_dataout : STD_LOGIC; + SIGNAL wire_nli00O01l_w_lg_dataout47146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O01O_dataout : STD_LOGIC; + SIGNAL wire_nli00O01O_w_lg_dataout47118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0i_dataout : STD_LOGIC; + SIGNAL wire_nli00O0ii_dataout : STD_LOGIC; + SIGNAL wire_nli00O0ii_w_lg_dataout46995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0il_dataout : STD_LOGIC; + SIGNAL wire_nli00O0il_w_lg_dataout46967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0iO_dataout : STD_LOGIC; + SIGNAL wire_nli00O0iO_w_lg_dataout47720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0l_dataout : STD_LOGIC; + SIGNAL wire_nli00O0li_dataout : STD_LOGIC; + SIGNAL wire_nli00O0li_w_lg_dataout47682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0ll_dataout : STD_LOGIC; + SIGNAL wire_nli00O0ll_w_lg_dataout47647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0lO_dataout : STD_LOGIC; + SIGNAL wire_nli00O0lO_w_lg_dataout47613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0O_dataout : STD_LOGIC; + SIGNAL wire_nli00O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli00O0Oi_w_lg_dataout47581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli00O0Ol_w_lg_dataout47549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O0OO_dataout : STD_LOGIC; + SIGNAL wire_nli00O0OO_w_lg_dataout47518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O10i_dataout : STD_LOGIC; + SIGNAL wire_nli00O10i_w_lg_dataout47683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O10l_dataout : STD_LOGIC; + SIGNAL wire_nli00O10l_w_lg_dataout47648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O10O_dataout : STD_LOGIC; + SIGNAL wire_nli00O10O_w_lg_dataout47614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O11i_dataout : STD_LOGIC; + SIGNAL wire_nli00O11i_w_lg_dataout47649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O11l_dataout : STD_LOGIC; + SIGNAL wire_nli00O11l_w_lg_dataout47615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O11O_dataout : STD_LOGIC; + SIGNAL wire_nli00O11O_w_lg_dataout47721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1i_dataout : STD_LOGIC; + SIGNAL wire_nli00O1ii_dataout : STD_LOGIC; + SIGNAL wire_nli00O1ii_w_lg_dataout47582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1il_dataout : STD_LOGIC; + SIGNAL wire_nli00O1il_w_lg_dataout47550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1iO_dataout : STD_LOGIC; + SIGNAL wire_nli00O1iO_w_lg_dataout47519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1l_dataout : STD_LOGIC; + SIGNAL wire_nli00O1li_dataout : STD_LOGIC; + SIGNAL wire_nli00O1li_w_lg_dataout47485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1ll_dataout : STD_LOGIC; + SIGNAL wire_nli00O1ll_w_lg_dataout47455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1lO_dataout : STD_LOGIC; + SIGNAL wire_nli00O1lO_w_lg_dataout47423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1O_dataout : STD_LOGIC; + SIGNAL wire_nli00O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli00O1Oi_w_lg_dataout47394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli00O1Ol_w_lg_dataout47332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00O1OO_dataout : STD_LOGIC; + SIGNAL wire_nli00O1OO_w_lg_dataout47209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nli00Oi0i_w_lg_dataout47393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nli00Oi0l_w_lg_dataout47363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nli00Oi0O_w_lg_dataout47331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nli00Oi1i_w_lg_dataout47484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nli00Oi1l_w_lg_dataout47454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nli00Oi1O_w_lg_dataout47422w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oii_dataout : STD_LOGIC; + SIGNAL wire_nli00Oiii_dataout : STD_LOGIC; + SIGNAL wire_nli00Oiii_w_lg_dataout47302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oiil_dataout : STD_LOGIC; + SIGNAL wire_nli00Oiil_w_lg_dataout47272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OiiO_dataout : STD_LOGIC; + SIGNAL wire_nli00OiiO_w_lg_dataout47239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oil_dataout : STD_LOGIC; + SIGNAL wire_nli00Oili_dataout : STD_LOGIC; + SIGNAL wire_nli00Oili_w_lg_dataout47208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oill_dataout : STD_LOGIC; + SIGNAL wire_nli00Oill_w_lg_dataout47176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OilO_dataout : STD_LOGIC; + SIGNAL wire_nli00OilO_w_lg_dataout47145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OiO_dataout : STD_LOGIC; + SIGNAL wire_nli00OiOi_dataout : STD_LOGIC; + SIGNAL wire_nli00OiOi_w_lg_dataout47117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OiOl_dataout : STD_LOGIC; + SIGNAL wire_nli00OiOl_w_lg_dataout47086w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OiOO_dataout : STD_LOGIC; + SIGNAL wire_nli00OiOO_w_lg_dataout47053w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nli00Ol0i_w_lg_dataout46937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nli00Ol0l_w_lg_dataout46908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nli00Ol0O_w_lg_dataout46880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nli00Ol1i_w_lg_dataout47023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nli00Ol1l_w_lg_dataout46994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nli00Ol1O_w_lg_dataout46966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oli_dataout : STD_LOGIC; + SIGNAL wire_nli00Olii_dataout : STD_LOGIC; + SIGNAL wire_nli00Olii_w_lg_dataout46852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Olil_dataout : STD_LOGIC; + SIGNAL wire_nli00Olil_w_lg_dataout46825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OliO_dataout : STD_LOGIC; + SIGNAL wire_nli00OliO_w_lg_dataout46798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Oll_dataout : STD_LOGIC; + SIGNAL wire_nli00Olli_dataout : STD_LOGIC; + SIGNAL wire_nli00Olli_w_lg_dataout46771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00Olll_dataout : STD_LOGIC; + SIGNAL wire_nli00Olll_w_lg_dataout47719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OllO_dataout : STD_LOGIC; + SIGNAL wire_nli00OllO_w_lg_dataout47681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OlO_dataout : STD_LOGIC; + SIGNAL wire_nli00OlOi_dataout : STD_LOGIC; + SIGNAL wire_nli00OlOl_dataout : STD_LOGIC; + SIGNAL wire_nli00OlOl_w_lg_dataout47580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OlOO_dataout : STD_LOGIC; + SIGNAL wire_nli00OlOO_w_lg_dataout47517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OO0i_dataout : STD_LOGIC; + SIGNAL wire_nli00OO0i_w_lg_dataout47392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OO0l_dataout : STD_LOGIC; + SIGNAL wire_nli00OO0l_w_lg_dataout47362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OO0O_dataout : STD_LOGIC; + SIGNAL wire_nli00OO0O_w_lg_dataout47207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OO1i_dataout : STD_LOGIC; + SIGNAL wire_nli00OO1i_w_lg_dataout47483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OO1l_dataout : STD_LOGIC; + SIGNAL wire_nli00OO1l_w_lg_dataout47453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OO1O_dataout : STD_LOGIC; + SIGNAL wire_nli00OO1O_w_lg_dataout47421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOi_dataout : STD_LOGIC; + SIGNAL wire_nli00OOii_dataout : STD_LOGIC; + SIGNAL wire_nli00OOii_w_lg_dataout47175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOil_dataout : STD_LOGIC; + SIGNAL wire_nli00OOil_w_lg_dataout47085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOiO_dataout : STD_LOGIC; + SIGNAL wire_nli00OOiO_w_lg_dataout47052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOl_dataout : STD_LOGIC; + SIGNAL wire_nli00OOli_dataout : STD_LOGIC; + SIGNAL wire_nli00OOli_w_lg_dataout47022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOll_dataout : STD_LOGIC; + SIGNAL wire_nli00OOlO_dataout : STD_LOGIC; + SIGNAL wire_nli00OOlO_w_lg_dataout46907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOO_dataout : STD_LOGIC; + SIGNAL wire_nli00OOOi_dataout : STD_LOGIC; + SIGNAL wire_nli00OOOi_w_lg_dataout46879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOOl_dataout : STD_LOGIC; + SIGNAL wire_nli00OOOl_w_lg_dataout46851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli00OOOO_dataout : STD_LOGIC; + SIGNAL wire_nli00OOOO_w_lg_dataout46824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli01l0i_dataout : STD_LOGIC; + SIGNAL wire_nli01l0l_dataout : STD_LOGIC; + SIGNAL wire_nli01l0O_dataout : STD_LOGIC; + SIGNAL wire_nli01l1i_dataout : STD_LOGIC; + SIGNAL wire_nli01l1l_dataout : STD_LOGIC; + SIGNAL wire_nli01l1O_dataout : STD_LOGIC; + SIGNAL wire_nli01lii_dataout : STD_LOGIC; + SIGNAL wire_nli01lil_dataout : STD_LOGIC; + SIGNAL wire_nli01liO_dataout : STD_LOGIC; + SIGNAL wire_nli01lli_dataout : STD_LOGIC; + SIGNAL wire_nli01lll_dataout : STD_LOGIC; + SIGNAL wire_nli01llO_dataout : STD_LOGIC; + SIGNAL wire_nli01lOi_dataout : STD_LOGIC; + SIGNAL wire_nli01lOl_dataout : STD_LOGIC; + SIGNAL wire_nli01lOO_dataout : STD_LOGIC; + SIGNAL wire_nli01O0i_dataout : STD_LOGIC; + SIGNAL wire_nli01O0l_dataout : STD_LOGIC; + SIGNAL wire_nli01O0O_dataout : STD_LOGIC; + SIGNAL wire_nli01O1i_dataout : STD_LOGIC; + SIGNAL wire_nli01O1l_dataout : STD_LOGIC; + SIGNAL wire_nli01O1O_dataout : STD_LOGIC; + SIGNAL wire_nli01Oii_dataout : STD_LOGIC; + SIGNAL wire_nli01Oil_dataout : STD_LOGIC; + SIGNAL wire_nli01OiO_dataout : STD_LOGIC; + SIGNAL wire_nli01Oli_dataout : STD_LOGIC; + SIGNAL wire_nli01Oll_dataout : STD_LOGIC; + SIGNAL wire_nli01OlO_dataout : STD_LOGIC; + SIGNAL wire_nli01OOi_dataout : STD_LOGIC; + SIGNAL wire_nli01OOl_dataout : STD_LOGIC; + SIGNAL wire_nli01OOO_dataout : STD_LOGIC; + SIGNAL wire_nli0i000i_dataout : STD_LOGIC; + SIGNAL wire_nli0i000i_w_lg_dataout47415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i000l_dataout : STD_LOGIC; + SIGNAL wire_nli0i000l_w_lg_dataout47385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i000O_dataout : STD_LOGIC; + SIGNAL wire_nli0i000O_w_lg_dataout47354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i001i_dataout : STD_LOGIC; + SIGNAL wire_nli0i001i_w_lg_dataout47674w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i001l_dataout : STD_LOGIC; + SIGNAL wire_nli0i001l_w_lg_dataout47607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i001O_dataout : STD_LOGIC; + SIGNAL wire_nli0i001O_w_lg_dataout47446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00i_dataout : STD_LOGIC; + SIGNAL wire_nli0i00ii_dataout : STD_LOGIC; + SIGNAL wire_nli0i00ii_w_lg_dataout47323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00il_dataout : STD_LOGIC; + SIGNAL wire_nli0i00il_w_lg_dataout47294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00iO_dataout : STD_LOGIC; + SIGNAL wire_nli0i00iO_w_lg_dataout47263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00l_dataout : STD_LOGIC; + SIGNAL wire_nli0i00li_dataout : STD_LOGIC; + SIGNAL wire_nli0i00li_w_lg_dataout47231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00ll_dataout : STD_LOGIC; + SIGNAL wire_nli0i00ll_w_lg_dataout46958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00lO_dataout : STD_LOGIC; + SIGNAL wire_nli0i00lO_w_lg_dataout46929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00O_dataout : STD_LOGIC; + SIGNAL wire_nli0i00Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0i00Oi_w_lg_dataout46899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0i00Ol_w_lg_dataout46872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i00OO_dataout : STD_LOGIC; + SIGNAL wire_nli0i00OO_w_lg_dataout46845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i010i_dataout : STD_LOGIC; + SIGNAL wire_nli0i010i_w_lg_dataout47142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i010l_dataout : STD_LOGIC; + SIGNAL wire_nli0i010l_w_lg_dataout47114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i010O_dataout : STD_LOGIC; + SIGNAL wire_nli0i010O_w_lg_dataout47082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i011i_dataout : STD_LOGIC; + SIGNAL wire_nli0i011l_dataout : STD_LOGIC; + SIGNAL wire_nli0i011l_w_lg_dataout47205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i011O_dataout : STD_LOGIC; + SIGNAL wire_nli0i011O_w_lg_dataout47173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01i_dataout : STD_LOGIC; + SIGNAL wire_nli0i01ii_dataout : STD_LOGIC; + SIGNAL wire_nli0i01ii_w_lg_dataout47049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01il_dataout : STD_LOGIC; + SIGNAL wire_nli0i01il_w_lg_dataout47021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01iO_dataout : STD_LOGIC; + SIGNAL wire_nli0i01iO_w_lg_dataout46964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01l_dataout : STD_LOGIC; + SIGNAL wire_nli0i01li_dataout : STD_LOGIC; + SIGNAL wire_nli0i01li_w_lg_dataout46935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01ll_dataout : STD_LOGIC; + SIGNAL wire_nli0i01ll_w_lg_dataout46905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01lO_dataout : STD_LOGIC; + SIGNAL wire_nli0i01lO_w_lg_dataout46877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01O_dataout : STD_LOGIC; + SIGNAL wire_nli0i01Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0i01Oi_w_lg_dataout46850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0i01Ol_w_lg_dataout46823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i01OO_dataout : STD_LOGIC; + SIGNAL wire_nli0i01OO_w_lg_dataout47711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0i0i_dataout : STD_LOGIC; + SIGNAL wire_nli0i0i0i_w_lg_dataout47108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0i0l_dataout : STD_LOGIC; + SIGNAL wire_nli0i0i0l_w_lg_dataout47076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0i0O_dataout : STD_LOGIC; + SIGNAL wire_nli0i0i0O_w_lg_dataout47043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0i1i_dataout : STD_LOGIC; + SIGNAL wire_nli0i0i1i_w_lg_dataout46818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0i1l_dataout : STD_LOGIC; + SIGNAL wire_nli0i0i1l_w_lg_dataout46791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0i1O_dataout : STD_LOGIC; + SIGNAL wire_nli0i0i1O_w_lg_dataout46764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iii_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iii_w_lg_dataout47015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0iil_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iil_w_lg_dataout46987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0iiO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iiO_w_lg_dataout46957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0il_dataout : STD_LOGIC; + SIGNAL wire_nli0i0ili_dataout : STD_LOGIC; + SIGNAL wire_nli0i0ili_w_lg_dataout46928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0ill_dataout : STD_LOGIC; + SIGNAL wire_nli0i0ill_w_lg_dataout46898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0ilO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0ilO_w_lg_dataout46871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iOi_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iOi_w_lg_dataout46844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0iOl_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iOl_w_lg_dataout46817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0iOO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0iOO_w_lg_dataout46790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0l0i_dataout : STD_LOGIC; + SIGNAL wire_nli0i0l0i_w_lg_dataout47641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0l0l_dataout : STD_LOGIC; + SIGNAL wire_nli0i0l0l_w_lg_dataout47606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0l0O_dataout : STD_LOGIC; + SIGNAL wire_nli0i0l0O_w_lg_dataout47572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0l1i_dataout : STD_LOGIC; + SIGNAL wire_nli0i0l1i_w_lg_dataout46763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0l1l_dataout : STD_LOGIC; + SIGNAL wire_nli0i0l1l_w_lg_dataout47709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0l1O_dataout : STD_LOGIC; + SIGNAL wire_nli0i0l1O_w_lg_dataout47673w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0li_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lii_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lii_w_lg_dataout47542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0lil_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lil_w_lg_dataout47510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0liO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0liO_w_lg_dataout47476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lli_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lli_w_lg_dataout47445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0lll_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lll_w_lg_dataout47414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0llO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0llO_w_lg_dataout47384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lOi_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lOi_w_lg_dataout47353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0lOl_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lOl_w_lg_dataout47322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0lOO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0lOO_w_lg_dataout47293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0O0i_dataout : STD_LOGIC; + SIGNAL wire_nli0i0O0i_w_lg_dataout47708w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0O0l_dataout : STD_LOGIC; + SIGNAL wire_nli0i0O0l_w_lg_dataout47672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0O0O_dataout : STD_LOGIC; + SIGNAL wire_nli0i0O0O_w_lg_dataout47640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0O1i_dataout : STD_LOGIC; + SIGNAL wire_nli0i0O1i_w_lg_dataout47262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0O1l_dataout : STD_LOGIC; + SIGNAL wire_nli0i0O1l_w_lg_dataout47229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0i0Oii_dataout : STD_LOGIC; + SIGNAL wire_nli0i0Oii_w_lg_dataout47605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0Oil_dataout : STD_LOGIC; + SIGNAL wire_nli0i0Oil_w_lg_dataout47571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0OiO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0OiO_w_lg_dataout47541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0i0Oli_dataout : STD_LOGIC; + SIGNAL wire_nli0i0Oli_w_lg_dataout47509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0Oll_dataout : STD_LOGIC; + SIGNAL wire_nli0i0Oll_w_lg_dataout47475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0OlO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0OlO_w_lg_dataout47444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0OOi_dataout : STD_LOGIC; + SIGNAL wire_nli0i0OOi_w_lg_dataout47413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0OOl_dataout : STD_LOGIC; + SIGNAL wire_nli0i0OOl_w_lg_dataout47383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i0OOO_dataout : STD_LOGIC; + SIGNAL wire_nli0i0OOO_w_lg_dataout47352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i100i_dataout : STD_LOGIC; + SIGNAL wire_nli0i100i_w_lg_dataout47144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i100l_dataout : STD_LOGIC; + SIGNAL wire_nli0i100l_w_lg_dataout47116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i100O_dataout : STD_LOGIC; + SIGNAL wire_nli0i100O_w_lg_dataout47084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i101i_dataout : STD_LOGIC; + SIGNAL wire_nli0i101i_w_lg_dataout47238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i101l_dataout : STD_LOGIC; + SIGNAL wire_nli0i101l_w_lg_dataout47206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i101O_dataout : STD_LOGIC; + SIGNAL wire_nli0i101O_w_lg_dataout47174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i10i_dataout : STD_LOGIC; + SIGNAL wire_nli0i10ii_dataout : STD_LOGIC; + SIGNAL wire_nli0i10ii_w_lg_dataout47051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i10il_dataout : STD_LOGIC; + SIGNAL wire_nli0i10il_w_lg_dataout46965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i10iO_dataout : STD_LOGIC; + SIGNAL wire_nli0i10iO_w_lg_dataout46936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i10l_dataout : STD_LOGIC; + SIGNAL wire_nli0i10li_dataout : STD_LOGIC; + SIGNAL wire_nli0i10li_w_lg_dataout46906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i10ll_dataout : STD_LOGIC; + SIGNAL wire_nli0i10ll_w_lg_dataout46878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i10lO_dataout : STD_LOGIC; + SIGNAL wire_nli0i10O_dataout : STD_LOGIC; + SIGNAL wire_nli0i10Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0i10Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0i10Ol_w_lg_dataout46797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i10OO_dataout : STD_LOGIC; + SIGNAL wire_nli0i10OO_w_lg_dataout46770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i110i_dataout : STD_LOGIC; + SIGNAL wire_nli0i110i_w_lg_dataout47680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i110l_dataout : STD_LOGIC; + SIGNAL wire_nli0i110l_w_lg_dataout47579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i110O_dataout : STD_LOGIC; + SIGNAL wire_nli0i110O_w_lg_dataout47548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i111i_dataout : STD_LOGIC; + SIGNAL wire_nli0i111l_dataout : STD_LOGIC; + SIGNAL wire_nli0i111O_dataout : STD_LOGIC; + SIGNAL wire_nli0i111O_w_lg_dataout47718w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11i_dataout : STD_LOGIC; + SIGNAL wire_nli0i11ii_dataout : STD_LOGIC; + SIGNAL wire_nli0i11ii_w_lg_dataout47516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11il_dataout : STD_LOGIC; + SIGNAL wire_nli0i11il_w_lg_dataout47482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11iO_dataout : STD_LOGIC; + SIGNAL wire_nli0i11iO_w_lg_dataout47452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11l_dataout : STD_LOGIC; + SIGNAL wire_nli0i11li_dataout : STD_LOGIC; + SIGNAL wire_nli0i11ll_dataout : STD_LOGIC; + SIGNAL wire_nli0i11ll_w_lg_dataout47391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11lO_dataout : STD_LOGIC; + SIGNAL wire_nli0i11lO_w_lg_dataout47361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11O_dataout : STD_LOGIC; + SIGNAL wire_nli0i11Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0i11Oi_w_lg_dataout47330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0i11Ol_w_lg_dataout47301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i11OO_dataout : STD_LOGIC; + SIGNAL wire_nli0i11OO_w_lg_dataout47271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1i0i_dataout : STD_LOGIC; + SIGNAL wire_nli0i1i0i_w_lg_dataout47612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1i0l_dataout : STD_LOGIC; + SIGNAL wire_nli0i1i0O_dataout : STD_LOGIC; + SIGNAL wire_nli0i1i1i_dataout : STD_LOGIC; + SIGNAL wire_nli0i1i1l_dataout : STD_LOGIC; + SIGNAL wire_nli0i1i1O_dataout : STD_LOGIC; + SIGNAL wire_nli0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iii_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iil_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iiO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1il_dataout : STD_LOGIC; + SIGNAL wire_nli0i1ili_dataout : STD_LOGIC; + SIGNAL wire_nli0i1ill_dataout : STD_LOGIC; + SIGNAL wire_nli0i1ilO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iOi_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iOl_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iOl_w_lg_dataout47270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1iOO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1iOO_w_lg_dataout47237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1l0i_dataout : STD_LOGIC; + SIGNAL wire_nli0i1l0i_w_lg_dataout47115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1l0l_dataout : STD_LOGIC; + SIGNAL wire_nli0i1l0l_w_lg_dataout47083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1l0O_dataout : STD_LOGIC; + SIGNAL wire_nli0i1l0O_w_lg_dataout47050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1l1i_dataout : STD_LOGIC; + SIGNAL wire_nli0i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nli0i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nli0i1l1O_w_lg_dataout47143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1li_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lii_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lii_w_lg_dataout47717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1lil_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lil_w_lg_dataout47679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1liO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1liO_w_lg_dataout47646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lli_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lli_w_lg_dataout47547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1lll_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lll_w_lg_dataout47515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1llO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1llO_w_lg_dataout47481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lOi_w_lg_dataout47451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1lOl_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lOl_w_lg_dataout47420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1lOO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1lOO_w_lg_dataout47390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1O0i_dataout : STD_LOGIC; + SIGNAL wire_nli0i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nli0i1O0O_dataout : STD_LOGIC; + SIGNAL wire_nli0i1O1i_dataout : STD_LOGIC; + SIGNAL wire_nli0i1O1i_w_lg_dataout47360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nli0i1O1l_w_lg_dataout47329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1O1O_dataout : STD_LOGIC; + SIGNAL wire_nli0i1O1O_w_lg_dataout47300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0i1Oii_dataout : STD_LOGIC; + SIGNAL wire_nli0i1Oil_dataout : STD_LOGIC; + SIGNAL wire_nli0i1OiO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0i1Oli_dataout : STD_LOGIC; + SIGNAL wire_nli0i1Oli_w_lg_dataout46993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0i1Oll_dataout : STD_LOGIC; + SIGNAL wire_nli0i1OlO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1OOi_dataout : STD_LOGIC; + SIGNAL wire_nli0i1OOl_dataout : STD_LOGIC; + SIGNAL wire_nli0i1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli0i1OOO_w_lg_dataout47269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii00i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii00i_w_lg_dataout46789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii00l_dataout : STD_LOGIC; + SIGNAL wire_nli0ii00l_w_lg_dataout46762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii00O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii01i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii01i_w_lg_dataout46870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii01l_dataout : STD_LOGIC; + SIGNAL wire_nli0ii01l_w_lg_dataout46843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii01O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii01O_w_lg_dataout46816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0il_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0ii0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0ii10i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii10i_w_lg_dataout47228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii10l_dataout : STD_LOGIC; + SIGNAL wire_nli0ii10l_w_lg_dataout47198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii10O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii10O_w_lg_dataout47166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii11i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii11i_w_lg_dataout47321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii11l_dataout : STD_LOGIC; + SIGNAL wire_nli0ii11l_w_lg_dataout47292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii11O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii11O_w_lg_dataout47261w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1ii_w_lg_dataout47136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1il_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1il_w_lg_dataout47107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1iO_w_lg_dataout47075w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1li_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1li_w_lg_dataout47042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1ll_w_lg_dataout47014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1lO_w_lg_dataout46986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1Oi_w_lg_dataout46956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1Ol_w_lg_dataout46927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ii1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0ii1OO_w_lg_dataout46897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iii0i_dataout : STD_LOGIC; + SIGNAL wire_nli0iii0l_dataout : STD_LOGIC; + SIGNAL wire_nli0iii0O_dataout : STD_LOGIC; + SIGNAL wire_nli0iii1i_dataout : STD_LOGIC; + SIGNAL wire_nli0iii1l_dataout : STD_LOGIC; + SIGNAL wire_nli0iii1O_dataout : STD_LOGIC; + SIGNAL wire_nli0iiii_dataout : STD_LOGIC; + SIGNAL wire_nli0iiiiO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiiiO_w_lg_dataout47639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiil_dataout : STD_LOGIC; + SIGNAL wire_nli0iiili_dataout : STD_LOGIC; + SIGNAL wire_nli0iiili_w_lg_dataout47604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiill_dataout : STD_LOGIC; + SIGNAL wire_nli0iiill_w_lg_dataout47570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiilO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiilO_w_lg_dataout47540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiiOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iiiOi_w_lg_dataout47508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiiOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iiiOl_w_lg_dataout47474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiiOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiiOO_w_lg_dataout47443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iil0i_dataout : STD_LOGIC; + SIGNAL wire_nli0iil0i_w_lg_dataout47320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iil0l_dataout : STD_LOGIC; + SIGNAL wire_nli0iil0l_w_lg_dataout47291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iil0O_dataout : STD_LOGIC; + SIGNAL wire_nli0iil0O_w_lg_dataout47260w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iil1i_dataout : STD_LOGIC; + SIGNAL wire_nli0iil1i_w_lg_dataout47412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iil1l_dataout : STD_LOGIC; + SIGNAL wire_nli0iil1l_w_lg_dataout47382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iil1O_dataout : STD_LOGIC; + SIGNAL wire_nli0iil1O_w_lg_dataout47351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iili_dataout : STD_LOGIC; + SIGNAL wire_nli0iilii_dataout : STD_LOGIC; + SIGNAL wire_nli0iilii_w_lg_dataout47227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iilil_dataout : STD_LOGIC; + SIGNAL wire_nli0iilil_w_lg_dataout47197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiliO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiliO_w_lg_dataout47165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iill_dataout : STD_LOGIC; + SIGNAL wire_nli0iilli_dataout : STD_LOGIC; + SIGNAL wire_nli0iilli_w_lg_dataout47135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iilll_dataout : STD_LOGIC; + SIGNAL wire_nli0iilll_w_lg_dataout47106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iillO_dataout : STD_LOGIC; + SIGNAL wire_nli0iillO_w_lg_dataout47074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iilO_dataout : STD_LOGIC; + SIGNAL wire_nli0iilOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iilOi_w_lg_dataout47041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iilOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iilOl_w_lg_dataout47013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iilOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iilOO_w_lg_dataout46985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0iiO0i_w_lg_dataout46869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0iiO0l_w_lg_dataout46842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0iiO0O_w_lg_dataout46815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0iiO1i_w_lg_dataout46955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0iiO1l_w_lg_dataout46926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0iiO1O_w_lg_dataout46896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOii_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOii_w_lg_dataout46788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOil_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOil_w_lg_dataout46761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOiO_w_lg_dataout47319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOli_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOli_w_lg_dataout47196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOll_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOll_w_lg_dataout47164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOlO_w_lg_dataout47134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOOi_w_lg_dataout47105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOOl_w_lg_dataout47073w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iiOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iiOOO_w_lg_dataout47040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il00i_dataout : STD_LOGIC; + SIGNAL wire_nli0il00i_w_lg_dataout47011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il00l_dataout : STD_LOGIC; + SIGNAL wire_nli0il00O_dataout : STD_LOGIC; + SIGNAL wire_nli0il01i_dataout : STD_LOGIC; + SIGNAL wire_nli0il01i_w_lg_dataout47163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il01l_dataout : STD_LOGIC; + SIGNAL wire_nli0il01l_w_lg_dataout47104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il01O_dataout : STD_LOGIC; + SIGNAL wire_nli0il01O_w_lg_dataout47072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il0i_dataout : STD_LOGIC; + SIGNAL wire_nli0il0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0il0il_dataout : STD_LOGIC; + SIGNAL wire_nli0il0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0il0l_dataout : STD_LOGIC; + SIGNAL wire_nli0il0li_dataout : STD_LOGIC; + SIGNAL wire_nli0il0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0il0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0il0O_dataout : STD_LOGIC; + SIGNAL wire_nli0il0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0il0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0il0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0il10i_dataout : STD_LOGIC; + SIGNAL wire_nli0il10i_w_lg_dataout47706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il10l_dataout : STD_LOGIC; + SIGNAL wire_nli0il10l_w_lg_dataout47671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il10O_dataout : STD_LOGIC; + SIGNAL wire_nli0il10O_w_lg_dataout47637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il11i_dataout : STD_LOGIC; + SIGNAL wire_nli0il11i_w_lg_dataout47012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il11l_dataout : STD_LOGIC; + SIGNAL wire_nli0il11l_w_lg_dataout46984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il11O_dataout : STD_LOGIC; + SIGNAL wire_nli0il11O_w_lg_dataout46954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1i_dataout : STD_LOGIC; + SIGNAL wire_nli0il1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0il1ii_w_lg_dataout47603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1il_dataout : STD_LOGIC; + SIGNAL wire_nli0il1il_w_lg_dataout47569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0il1iO_w_lg_dataout47538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1l_dataout : STD_LOGIC; + SIGNAL wire_nli0il1li_dataout : STD_LOGIC; + SIGNAL wire_nli0il1li_w_lg_dataout47506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0il1ll_w_lg_dataout47473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0il1lO_w_lg_dataout47441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1O_dataout : STD_LOGIC; + SIGNAL wire_nli0il1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0il1Oi_w_lg_dataout47411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0il1Ol_w_lg_dataout47381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0il1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0il1OO_w_lg_dataout47195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ili0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ili0l_dataout : STD_LOGIC; + SIGNAL wire_nli0ili1i_dataout : STD_LOGIC; + SIGNAL wire_nli0ili1l_dataout : STD_LOGIC; + SIGNAL wire_nli0ili1O_dataout : STD_LOGIC; + SIGNAL wire_nli0ilii_dataout : STD_LOGIC; + SIGNAL wire_nli0iliii_dataout : STD_LOGIC; + SIGNAL wire_nli0iliii_w_lg_dataout47705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iliil_dataout : STD_LOGIC; + SIGNAL wire_nli0iliil_w_lg_dataout47349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iliiO_dataout : STD_LOGIC; + SIGNAL wire_nli0iliiO_w_lg_dataout47318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilil_dataout : STD_LOGIC; + SIGNAL wire_nli0ilili_dataout : STD_LOGIC; + SIGNAL wire_nli0ilili_w_lg_dataout47288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilill_dataout : STD_LOGIC; + SIGNAL wire_nli0ilill_w_lg_dataout47257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ililO_dataout : STD_LOGIC; + SIGNAL wire_nli0ililO_w_lg_dataout47226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iliO_dataout : STD_LOGIC; + SIGNAL wire_nli0iliOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iliOi_w_lg_dataout47194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iliOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iliOl_w_lg_dataout47162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iliOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iliOO_w_lg_dataout47133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ill0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ill0i_w_lg_dataout47010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ill0l_dataout : STD_LOGIC; + SIGNAL wire_nli0ill0l_w_lg_dataout46983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ill0O_dataout : STD_LOGIC; + SIGNAL wire_nli0ill0O_w_lg_dataout46953w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ill1i_dataout : STD_LOGIC; + SIGNAL wire_nli0ill1i_w_lg_dataout47103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ill1l_dataout : STD_LOGIC; + SIGNAL wire_nli0ill1l_w_lg_dataout47071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ill1O_dataout : STD_LOGIC; + SIGNAL wire_nli0ill1O_w_lg_dataout47039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illi_dataout : STD_LOGIC; + SIGNAL wire_nli0illii_dataout : STD_LOGIC; + SIGNAL wire_nli0illii_w_lg_dataout46924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illil_dataout : STD_LOGIC; + SIGNAL wire_nli0illil_w_lg_dataout46895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illiO_dataout : STD_LOGIC; + SIGNAL wire_nli0illiO_w_lg_dataout46868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illl_dataout : STD_LOGIC; + SIGNAL wire_nli0illli_dataout : STD_LOGIC; + SIGNAL wire_nli0illli_w_lg_dataout46841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illll_dataout : STD_LOGIC; + SIGNAL wire_nli0illll_w_lg_dataout46814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illlO_dataout : STD_LOGIC; + SIGNAL wire_nli0illlO_w_lg_dataout46787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illO_dataout : STD_LOGIC; + SIGNAL wire_nli0illOi_dataout : STD_LOGIC; + SIGNAL wire_nli0illOi_w_lg_dataout46760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0illOO_dataout : STD_LOGIC; + SIGNAL wire_nli0illOO_w_lg_dataout47602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ilO0i_w_lg_dataout47670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0ilO0l_w_lg_dataout47636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0ilO0O_w_lg_dataout47601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0ilO1i_w_lg_dataout47568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0ilO1l_w_lg_dataout47537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0ilO1O_w_lg_dataout47704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOii_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOii_w_lg_dataout47567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOil_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOil_w_lg_dataout47536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOiO_w_lg_dataout47504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOli_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOli_w_lg_dataout47472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOll_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOll_w_lg_dataout47440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOlO_w_lg_dataout47410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOOi_w_lg_dataout47380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOOl_w_lg_dataout47348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0ilOOO_w_lg_dataout47317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO00i_dataout : STD_LOGIC; + SIGNAL wire_nli0iO00i_w_lg_dataout46759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO00l_dataout : STD_LOGIC; + SIGNAL wire_nli0iO00O_dataout : STD_LOGIC; + SIGNAL wire_nli0iO01i_dataout : STD_LOGIC; + SIGNAL wire_nli0iO01i_w_lg_dataout46840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO01l_dataout : STD_LOGIC; + SIGNAL wire_nli0iO01l_w_lg_dataout46813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO01O_dataout : STD_LOGIC; + SIGNAL wire_nli0iO01O_w_lg_dataout46786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0il_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0li_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0iO0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0iO10i_dataout : STD_LOGIC; + SIGNAL wire_nli0iO10i_w_lg_dataout47193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO10l_dataout : STD_LOGIC; + SIGNAL wire_nli0iO10l_w_lg_dataout47161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO10O_dataout : STD_LOGIC; + SIGNAL wire_nli0iO10O_w_lg_dataout47132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO11i_dataout : STD_LOGIC; + SIGNAL wire_nli0iO11i_w_lg_dataout47287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO11l_dataout : STD_LOGIC; + SIGNAL wire_nli0iO11l_w_lg_dataout47256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO11O_dataout : STD_LOGIC; + SIGNAL wire_nli0iO11O_w_lg_dataout47225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1ii_w_lg_dataout47102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1il_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1il_w_lg_dataout47070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1iO_w_lg_dataout47038w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1li_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1li_w_lg_dataout47009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1ll_w_lg_dataout46982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1lO_w_lg_dataout46952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1Oi_w_lg_dataout46923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1Ol_w_lg_dataout46894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iO1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0iO1OO_w_lg_dataout46867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOi0i_dataout : STD_LOGIC; + SIGNAL wire_nli0iOi0l_dataout : STD_LOGIC; + SIGNAL wire_nli0iOi0O_dataout : STD_LOGIC; + SIGNAL wire_nli0iOi1i_dataout : STD_LOGIC; + SIGNAL wire_nli0iOi1l_dataout : STD_LOGIC; + SIGNAL wire_nli0iOi1O_dataout : STD_LOGIC; + SIGNAL wire_nli0iOii_dataout : STD_LOGIC; + SIGNAL wire_nli0iOiii_dataout : STD_LOGIC; + SIGNAL wire_nli0iOiil_dataout : STD_LOGIC; + SIGNAL wire_nli0iOiiO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOil_dataout : STD_LOGIC; + SIGNAL wire_nli0iOili_dataout : STD_LOGIC; + SIGNAL wire_nli0iOill_dataout : STD_LOGIC; + SIGNAL wire_nli0iOilO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOiOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iOiOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iOiOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nli0iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nli0iOl0O_dataout : STD_LOGIC; + SIGNAL wire_nli0iOl1i_dataout : STD_LOGIC; + SIGNAL wire_nli0iOl1l_dataout : STD_LOGIC; + SIGNAL wire_nli0iOl1O_dataout : STD_LOGIC; + SIGNAL wire_nli0iOli_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlil_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlil_w_lg_dataout47703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOliO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOliO_w_lg_dataout47669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOll_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlli_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlli_w_lg_dataout47635w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOlll_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlll_w_lg_dataout47600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOllO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOllO_w_lg_dataout47566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlOi_w_lg_dataout47535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlOl_w_lg_dataout47503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOlOO_w_lg_dataout47471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0iOO0i_w_lg_dataout47347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0iOO0l_w_lg_dataout47316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0iOO0O_w_lg_dataout47286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0iOO1i_w_lg_dataout47439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0iOO1l_w_lg_dataout47409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0iOO1O_w_lg_dataout47379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOii_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOii_w_lg_dataout47255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOil_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOil_w_lg_dataout47224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOiO_w_lg_dataout47192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOli_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOli_w_lg_dataout47160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOll_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOll_w_lg_dataout47131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOlO_w_lg_dataout47101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOOi_w_lg_dataout47069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOOl_w_lg_dataout47037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0iOOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0iOOOO_w_lg_dataout47008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l000i_dataout : STD_LOGIC; + SIGNAL wire_nli0l000i_w_lg_dataout47129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l000l_dataout : STD_LOGIC; + SIGNAL wire_nli0l000l_w_lg_dataout47099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l000O_dataout : STD_LOGIC; + SIGNAL wire_nli0l000O_w_lg_dataout47067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l001i_dataout : STD_LOGIC; + SIGNAL wire_nli0l001i_w_lg_dataout47222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l001l_dataout : STD_LOGIC; + SIGNAL wire_nli0l001l_w_lg_dataout47190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l001O_dataout : STD_LOGIC; + SIGNAL wire_nli0l001O_w_lg_dataout47158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00i_dataout : STD_LOGIC; + SIGNAL wire_nli0l00ii_dataout : STD_LOGIC; + SIGNAL wire_nli0l00ii_w_lg_dataout47035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00il_dataout : STD_LOGIC; + SIGNAL wire_nli0l00il_w_lg_dataout47006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l00iO_w_lg_dataout46979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00l_dataout : STD_LOGIC; + SIGNAL wire_nli0l00li_dataout : STD_LOGIC; + SIGNAL wire_nli0l00li_w_lg_dataout46949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00ll_dataout : STD_LOGIC; + SIGNAL wire_nli0l00ll_w_lg_dataout46920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00lO_dataout : STD_LOGIC; + SIGNAL wire_nli0l00lO_w_lg_dataout46891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00O_dataout : STD_LOGIC; + SIGNAL wire_nli0l00Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0l00Oi_w_lg_dataout46864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0l00Ol_w_lg_dataout46837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l00OO_dataout : STD_LOGIC; + SIGNAL wire_nli0l00OO_w_lg_dataout46810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l010i_dataout : STD_LOGIC; + SIGNAL wire_nli0l010i_w_lg_dataout47598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l010l_dataout : STD_LOGIC; + SIGNAL wire_nli0l010l_w_lg_dataout47564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l010O_dataout : STD_LOGIC; + SIGNAL wire_nli0l010O_w_lg_dataout47533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l011i_dataout : STD_LOGIC; + SIGNAL wire_nli0l011i_w_lg_dataout47701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l011l_dataout : STD_LOGIC; + SIGNAL wire_nli0l011l_w_lg_dataout47667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l011O_dataout : STD_LOGIC; + SIGNAL wire_nli0l011O_w_lg_dataout47633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01i_dataout : STD_LOGIC; + SIGNAL wire_nli0l01ii_dataout : STD_LOGIC; + SIGNAL wire_nli0l01ii_w_lg_dataout47501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01il_dataout : STD_LOGIC; + SIGNAL wire_nli0l01il_w_lg_dataout47469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l01iO_w_lg_dataout47437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01l_dataout : STD_LOGIC; + SIGNAL wire_nli0l01li_dataout : STD_LOGIC; + SIGNAL wire_nli0l01li_w_lg_dataout47407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01ll_dataout : STD_LOGIC; + SIGNAL wire_nli0l01ll_w_lg_dataout47377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01lO_dataout : STD_LOGIC; + SIGNAL wire_nli0l01lO_w_lg_dataout47345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01O_dataout : STD_LOGIC; + SIGNAL wire_nli0l01Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0l01Oi_w_lg_dataout47314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0l01Ol_w_lg_dataout47284w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l01OO_dataout : STD_LOGIC; + SIGNAL wire_nli0l01OO_w_lg_dataout47253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0i0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l0i0l_dataout : STD_LOGIC; + SIGNAL wire_nli0l0i0O_dataout : STD_LOGIC; + SIGNAL wire_nli0l0i1i_dataout : STD_LOGIC; + SIGNAL wire_nli0l0i1i_w_lg_dataout46783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0i1l_dataout : STD_LOGIC; + SIGNAL wire_nli0l0i1l_w_lg_dataout46756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0i1O_dataout : STD_LOGIC; + SIGNAL wire_nli0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0l0iii_dataout : STD_LOGIC; + SIGNAL wire_nli0l0iil_dataout : STD_LOGIC; + SIGNAL wire_nli0l0iiO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0il_dataout : STD_LOGIC; + SIGNAL wire_nli0l0ili_dataout : STD_LOGIC; + SIGNAL wire_nli0l0ill_dataout : STD_LOGIC; + SIGNAL wire_nli0l0ilO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0iOi_dataout : STD_LOGIC; + SIGNAL wire_nli0l0iOl_dataout : STD_LOGIC; + SIGNAL wire_nli0l0iOO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0l0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l0l0l_dataout : STD_LOGIC; + SIGNAL wire_nli0l0l0O_dataout : STD_LOGIC; + SIGNAL wire_nli0l0l1i_dataout : STD_LOGIC; + SIGNAL wire_nli0l0l1l_dataout : STD_LOGIC; + SIGNAL wire_nli0l0l1O_dataout : STD_LOGIC; + SIGNAL wire_nli0l0li_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lii_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lil_dataout : STD_LOGIC; + SIGNAL wire_nli0l0liO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lli_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lll_dataout : STD_LOGIC; + SIGNAL wire_nli0l0llO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lOi_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lOO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0lOO_w_lg_dataout47700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0O0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l0O0i_w_lg_dataout47563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0O0l_dataout : STD_LOGIC; + SIGNAL wire_nli0l0O0l_w_lg_dataout47532w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0O0O_dataout : STD_LOGIC; + SIGNAL wire_nli0l0O0O_w_lg_dataout47500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0O1i_dataout : STD_LOGIC; + SIGNAL wire_nli0l0O1i_w_lg_dataout47666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0O1l_dataout : STD_LOGIC; + SIGNAL wire_nli0l0O1l_w_lg_dataout47632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0O1O_dataout : STD_LOGIC; + SIGNAL wire_nli0l0O1O_w_lg_dataout47597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0l0Oii_dataout : STD_LOGIC; + SIGNAL wire_nli0l0Oii_w_lg_dataout47468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0Oil_dataout : STD_LOGIC; + SIGNAL wire_nli0l0Oil_w_lg_dataout47436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0OiO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0OiO_w_lg_dataout47406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0l0Oli_dataout : STD_LOGIC; + SIGNAL wire_nli0l0Oli_w_lg_dataout47376w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0Oll_dataout : STD_LOGIC; + SIGNAL wire_nli0l0Oll_w_lg_dataout47344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0OlO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0OlO_w_lg_dataout47313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0OOi_dataout : STD_LOGIC; + SIGNAL wire_nli0l0OOi_w_lg_dataout47283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0OOl_dataout : STD_LOGIC; + SIGNAL wire_nli0l0OOl_w_lg_dataout47252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l0OOO_dataout : STD_LOGIC; + SIGNAL wire_nli0l0OOO_w_lg_dataout47221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l100i_dataout : STD_LOGIC; + SIGNAL wire_nli0l100l_dataout : STD_LOGIC; + SIGNAL wire_nli0l100O_dataout : STD_LOGIC; + SIGNAL wire_nli0l101i_dataout : STD_LOGIC; + SIGNAL wire_nli0l101l_dataout : STD_LOGIC; + SIGNAL wire_nli0l101O_dataout : STD_LOGIC; + SIGNAL wire_nli0l10i_dataout : STD_LOGIC; + SIGNAL wire_nli0l10ii_dataout : STD_LOGIC; + SIGNAL wire_nli0l10il_dataout : STD_LOGIC; + SIGNAL wire_nli0l10iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l10l_dataout : STD_LOGIC; + SIGNAL wire_nli0l10li_dataout : STD_LOGIC; + SIGNAL wire_nli0l10ll_dataout : STD_LOGIC; + SIGNAL wire_nli0l10lO_dataout : STD_LOGIC; + SIGNAL wire_nli0l10O_dataout : STD_LOGIC; + SIGNAL wire_nli0l10Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0l10Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0l10OO_dataout : STD_LOGIC; + SIGNAL wire_nli0l110i_dataout : STD_LOGIC; + SIGNAL wire_nli0l110i_w_lg_dataout46893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l110l_dataout : STD_LOGIC; + SIGNAL wire_nli0l110l_w_lg_dataout46866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l110O_dataout : STD_LOGIC; + SIGNAL wire_nli0l110O_w_lg_dataout46839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l111i_dataout : STD_LOGIC; + SIGNAL wire_nli0l111i_w_lg_dataout46981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l111l_dataout : STD_LOGIC; + SIGNAL wire_nli0l111l_w_lg_dataout46951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l111O_dataout : STD_LOGIC; + SIGNAL wire_nli0l111O_w_lg_dataout46922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l11i_dataout : STD_LOGIC; + SIGNAL wire_nli0l11ii_dataout : STD_LOGIC; + SIGNAL wire_nli0l11ii_w_lg_dataout46812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l11il_dataout : STD_LOGIC; + SIGNAL wire_nli0l11il_w_lg_dataout46785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l11iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l11iO_w_lg_dataout46758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l11l_dataout : STD_LOGIC; + SIGNAL wire_nli0l11li_dataout : STD_LOGIC; + SIGNAL wire_nli0l11ll_dataout : STD_LOGIC; + SIGNAL wire_nli0l11lO_dataout : STD_LOGIC; + SIGNAL wire_nli0l11O_dataout : STD_LOGIC; + SIGNAL wire_nli0l11Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0l11Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0l11OO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1i0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l1i0l_dataout : STD_LOGIC; + SIGNAL wire_nli0l1i0O_dataout : STD_LOGIC; + SIGNAL wire_nli0l1i1i_dataout : STD_LOGIC; + SIGNAL wire_nli0l1i1l_dataout : STD_LOGIC; + SIGNAL wire_nli0l1i1O_dataout : STD_LOGIC; + SIGNAL wire_nli0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iii_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iil_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iiO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1il_dataout : STD_LOGIC; + SIGNAL wire_nli0l1ili_dataout : STD_LOGIC; + SIGNAL wire_nli0l1ill_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iOi_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iOi_w_lg_dataout47702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1iOl_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iOl_w_lg_dataout47668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1iOO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1iOO_w_lg_dataout47634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1l0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l1l0i_w_lg_dataout47502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1l0l_dataout : STD_LOGIC; + SIGNAL wire_nli0l1l0l_w_lg_dataout47470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1l0O_dataout : STD_LOGIC; + SIGNAL wire_nli0l1l0O_w_lg_dataout47438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1l1i_dataout : STD_LOGIC; + SIGNAL wire_nli0l1l1i_w_lg_dataout47599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1l1l_dataout : STD_LOGIC; + SIGNAL wire_nli0l1l1l_w_lg_dataout47565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1l1O_dataout : STD_LOGIC; + SIGNAL wire_nli0l1l1O_w_lg_dataout47534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1li_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lii_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lii_w_lg_dataout47408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1lil_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lil_w_lg_dataout47378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1liO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1liO_w_lg_dataout47346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lli_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lli_w_lg_dataout47315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1lll_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lll_w_lg_dataout47285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1llO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1llO_w_lg_dataout47254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lOi_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lOi_w_lg_dataout47223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1lOl_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lOl_w_lg_dataout47191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1lOO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1lOO_w_lg_dataout47159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1O0i_dataout : STD_LOGIC; + SIGNAL wire_nli0l1O0i_w_lg_dataout47036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1O0l_dataout : STD_LOGIC; + SIGNAL wire_nli0l1O0l_w_lg_dataout47007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1O0O_dataout : STD_LOGIC; + SIGNAL wire_nli0l1O0O_w_lg_dataout46980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1O1i_dataout : STD_LOGIC; + SIGNAL wire_nli0l1O1i_w_lg_dataout47130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1O1l_dataout : STD_LOGIC; + SIGNAL wire_nli0l1O1l_w_lg_dataout47100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1O1O_dataout : STD_LOGIC; + SIGNAL wire_nli0l1O1O_w_lg_dataout47068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0l1Oii_dataout : STD_LOGIC; + SIGNAL wire_nli0l1Oii_w_lg_dataout46950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1Oil_dataout : STD_LOGIC; + SIGNAL wire_nli0l1Oil_w_lg_dataout46921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1OiO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1OiO_w_lg_dataout46892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0l1Oli_dataout : STD_LOGIC; + SIGNAL wire_nli0l1Oli_w_lg_dataout46865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1Oll_dataout : STD_LOGIC; + SIGNAL wire_nli0l1Oll_w_lg_dataout46838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1OlO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1OlO_w_lg_dataout46811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0l1OOi_dataout : STD_LOGIC; + SIGNAL wire_nli0l1OOi_w_lg_dataout46784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0l1OOl_dataout : STD_LOGIC; + SIGNAL wire_nli0l1OOl_w_lg_dataout46757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li00i_dataout : STD_LOGIC; + SIGNAL wire_nli0li00l_dataout : STD_LOGIC; + SIGNAL wire_nli0li00O_dataout : STD_LOGIC; + SIGNAL wire_nli0li01i_dataout : STD_LOGIC; + SIGNAL wire_nli0li01i_w_lg_dataout46755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li01l_dataout : STD_LOGIC; + SIGNAL wire_nli0li01O_dataout : STD_LOGIC; + SIGNAL wire_nli0li0i_dataout : STD_LOGIC; + SIGNAL wire_nli0li0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0li0il_dataout : STD_LOGIC; + SIGNAL wire_nli0li0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0li0l_dataout : STD_LOGIC; + SIGNAL wire_nli0li0li_dataout : STD_LOGIC; + SIGNAL wire_nli0li0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0li0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0li0O_dataout : STD_LOGIC; + SIGNAL wire_nli0li0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0li0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0li0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0li10i_dataout : STD_LOGIC; + SIGNAL wire_nli0li10i_w_lg_dataout47098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li10l_dataout : STD_LOGIC; + SIGNAL wire_nli0li10l_w_lg_dataout47066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li10O_dataout : STD_LOGIC; + SIGNAL wire_nli0li10O_w_lg_dataout47034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li11i_dataout : STD_LOGIC; + SIGNAL wire_nli0li11i_w_lg_dataout47189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li11l_dataout : STD_LOGIC; + SIGNAL wire_nli0li11l_w_lg_dataout47157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li11O_dataout : STD_LOGIC; + SIGNAL wire_nli0li11O_w_lg_dataout47128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1i_dataout : STD_LOGIC; + SIGNAL wire_nli0li1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0li1ii_w_lg_dataout47005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1il_dataout : STD_LOGIC; + SIGNAL wire_nli0li1il_w_lg_dataout46978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0li1iO_w_lg_dataout46948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1l_dataout : STD_LOGIC; + SIGNAL wire_nli0li1li_dataout : STD_LOGIC; + SIGNAL wire_nli0li1li_w_lg_dataout46919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0li1ll_w_lg_dataout46890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0li1lO_w_lg_dataout46863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1O_dataout : STD_LOGIC; + SIGNAL wire_nli0li1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0li1Oi_w_lg_dataout46836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0li1Ol_w_lg_dataout46809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0li1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0li1OO_w_lg_dataout46782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lii0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lii0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lii0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lii1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lii1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lii1O_dataout : STD_LOGIC; + SIGNAL wire_nli0liii_dataout : STD_LOGIC; + SIGNAL wire_nli0liiii_dataout : STD_LOGIC; + SIGNAL wire_nli0liiil_dataout : STD_LOGIC; + SIGNAL wire_nli0liiiO_dataout : STD_LOGIC; + SIGNAL wire_nli0liil_dataout : STD_LOGIC; + SIGNAL wire_nli0liili_dataout : STD_LOGIC; + SIGNAL wire_nli0liilO_dataout : STD_LOGIC; + SIGNAL wire_nli0liilO_w_lg_dataout47699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liiO_dataout : STD_LOGIC; + SIGNAL wire_nli0liiOi_dataout : STD_LOGIC; + SIGNAL wire_nli0liiOi_w_lg_dataout47665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liiOl_dataout : STD_LOGIC; + SIGNAL wire_nli0liiOl_w_lg_dataout47631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liiOO_dataout : STD_LOGIC; + SIGNAL wire_nli0liiOO_w_lg_dataout47596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lil0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lil0i_w_lg_dataout47467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lil0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lil0l_w_lg_dataout47435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lil0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lil0O_w_lg_dataout47405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lil1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lil1i_w_lg_dataout47562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lil1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lil1l_w_lg_dataout47531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lil1O_dataout : STD_LOGIC; + SIGNAL wire_nli0lil1O_w_lg_dataout47499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lili_dataout : STD_LOGIC; + SIGNAL wire_nli0lilii_dataout : STD_LOGIC; + SIGNAL wire_nli0lilii_w_lg_dataout47375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lilil_dataout : STD_LOGIC; + SIGNAL wire_nli0lilil_w_lg_dataout47343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liliO_dataout : STD_LOGIC; + SIGNAL wire_nli0liliO_w_lg_dataout47312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lill_dataout : STD_LOGIC; + SIGNAL wire_nli0lilli_dataout : STD_LOGIC; + SIGNAL wire_nli0lilli_w_lg_dataout47282w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lilll_dataout : STD_LOGIC; + SIGNAL wire_nli0lilll_w_lg_dataout47251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lillO_dataout : STD_LOGIC; + SIGNAL wire_nli0lillO_w_lg_dataout47220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lilO_dataout : STD_LOGIC; + SIGNAL wire_nli0lilOi_dataout : STD_LOGIC; + SIGNAL wire_nli0lilOi_w_lg_dataout47188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lilOl_dataout : STD_LOGIC; + SIGNAL wire_nli0lilOl_w_lg_dataout47156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lilOO_dataout : STD_LOGIC; + SIGNAL wire_nli0lilOO_w_lg_dataout47127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0liO0i_w_lg_dataout47004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0liO0l_w_lg_dataout46977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0liO0O_w_lg_dataout46947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0liO1i_w_lg_dataout47097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0liO1l_w_lg_dataout47065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0liO1O_w_lg_dataout47033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOi_dataout : STD_LOGIC; + SIGNAL wire_nli0liOii_dataout : STD_LOGIC; + SIGNAL wire_nli0liOii_w_lg_dataout46918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOil_dataout : STD_LOGIC; + SIGNAL wire_nli0liOil_w_lg_dataout46889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0liOiO_w_lg_dataout46862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOl_dataout : STD_LOGIC; + SIGNAL wire_nli0liOli_dataout : STD_LOGIC; + SIGNAL wire_nli0liOli_w_lg_dataout46835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOll_dataout : STD_LOGIC; + SIGNAL wire_nli0liOll_w_lg_dataout46808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0liOlO_w_lg_dataout46781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOO_dataout : STD_LOGIC; + SIGNAL wire_nli0liOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0liOOi_w_lg_dataout46754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0liOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0liOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0ll00i_dataout : STD_LOGIC; + SIGNAL wire_nli0ll00i_w_lg_dataout47595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll00l_dataout : STD_LOGIC; + SIGNAL wire_nli0ll00l_w_lg_dataout47561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll00O_dataout : STD_LOGIC; + SIGNAL wire_nli0ll00O_w_lg_dataout47530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll01i_dataout : STD_LOGIC; + SIGNAL wire_nli0ll01i_w_lg_dataout47698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll01l_dataout : STD_LOGIC; + SIGNAL wire_nli0ll01l_w_lg_dataout47664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll01O_dataout : STD_LOGIC; + SIGNAL wire_nli0ll01O_w_lg_dataout47630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0ii_w_lg_dataout47498w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0il_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0il_w_lg_dataout47466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0iO_w_lg_dataout47434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0li_w_lg_dataout47404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0ll_w_lg_dataout47374w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0lO_w_lg_dataout47342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0Oi_w_lg_dataout47311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0Ol_w_lg_dataout47281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0ll0OO_w_lg_dataout47250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0ll10i_dataout : STD_LOGIC; + SIGNAL wire_nli0ll10l_dataout : STD_LOGIC; + SIGNAL wire_nli0ll10O_dataout : STD_LOGIC; + SIGNAL wire_nli0ll11i_dataout : STD_LOGIC; + SIGNAL wire_nli0ll11l_dataout : STD_LOGIC; + SIGNAL wire_nli0ll11O_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1il_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1li_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0lli0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lli0i_w_lg_dataout47126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lli0l_w_lg_dataout47096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lli0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lli0O_w_lg_dataout47064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lli1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lli1i_w_lg_dataout47219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lli1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lli1l_w_lg_dataout47187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lli1O_dataout : STD_LOGIC; + SIGNAL wire_nli0lli1O_w_lg_dataout47155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0llii_dataout : STD_LOGIC; + SIGNAL wire_nli0lliii_dataout : STD_LOGIC; + SIGNAL wire_nli0lliii_w_lg_dataout47032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lliil_dataout : STD_LOGIC; + SIGNAL wire_nli0lliil_w_lg_dataout47003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lliiO_dataout : STD_LOGIC; + SIGNAL wire_nli0lliiO_w_lg_dataout46976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0llil_dataout : STD_LOGIC; + SIGNAL wire_nli0llili_dataout : STD_LOGIC; + SIGNAL wire_nli0llili_w_lg_dataout46946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0llill_dataout : STD_LOGIC; + SIGNAL wire_nli0llill_w_lg_dataout46917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0llilO_dataout : STD_LOGIC; + SIGNAL wire_nli0llilO_w_lg_dataout46888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lliO_dataout : STD_LOGIC; + SIGNAL wire_nli0lliOi_dataout : STD_LOGIC; + SIGNAL wire_nli0lliOi_w_lg_dataout46861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lliOl_dataout : STD_LOGIC; + SIGNAL wire_nli0lliOl_w_lg_dataout46834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lliOO_dataout : STD_LOGIC; + SIGNAL wire_nli0lliOO_w_lg_dataout46807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lll0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lll0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lll0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lll1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lll1i_w_lg_dataout46780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lll1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lll1l_w_lg_dataout46753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lll1O_dataout : STD_LOGIC; + SIGNAL wire_nli0llli_dataout : STD_LOGIC; + SIGNAL wire_nli0lllii_dataout : STD_LOGIC; + SIGNAL wire_nli0lllil_dataout : STD_LOGIC; + SIGNAL wire_nli0llliO_dataout : STD_LOGIC; + SIGNAL wire_nli0llll_dataout : STD_LOGIC; + SIGNAL wire_nli0lllli_dataout : STD_LOGIC; + SIGNAL wire_nli0lllll_dataout : STD_LOGIC; + SIGNAL wire_nli0llllO_dataout : STD_LOGIC; + SIGNAL wire_nli0lllO_dataout : STD_LOGIC; + SIGNAL wire_nli0lllOi_dataout : STD_LOGIC; + SIGNAL wire_nli0lllOl_dataout : STD_LOGIC; + SIGNAL wire_nli0lllOO_dataout : STD_LOGIC; + SIGNAL wire_nli0llO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0llO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0llO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0llO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0llO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0llO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0llOi_dataout : STD_LOGIC; + SIGNAL wire_nli0llOii_dataout : STD_LOGIC; + SIGNAL wire_nli0llOil_dataout : STD_LOGIC; + SIGNAL wire_nli0llOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0llOl_dataout : STD_LOGIC; + SIGNAL wire_nli0llOli_dataout : STD_LOGIC; + SIGNAL wire_nli0llOll_dataout : STD_LOGIC; + SIGNAL wire_nli0llOO_dataout : STD_LOGIC; + SIGNAL wire_nli0llOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0llOOi_w_lg_dataout47697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0llOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0llOOl_w_lg_dataout47663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0llOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0llOOO_w_lg_dataout47629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO00i_dataout : STD_LOGIC; + SIGNAL wire_nli0lO00i_w_lg_dataout47031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO00l_dataout : STD_LOGIC; + SIGNAL wire_nli0lO00l_w_lg_dataout47002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO00O_dataout : STD_LOGIC; + SIGNAL wire_nli0lO00O_w_lg_dataout46975w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO01i_dataout : STD_LOGIC; + SIGNAL wire_nli0lO01i_w_lg_dataout47125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO01l_dataout : STD_LOGIC; + SIGNAL wire_nli0lO01l_w_lg_dataout47095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO01O_dataout : STD_LOGIC; + SIGNAL wire_nli0lO01O_w_lg_dataout47063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0ii_w_lg_dataout46945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0il_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0il_w_lg_dataout46916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0iO_w_lg_dataout46887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0li_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0li_w_lg_dataout46860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0ll_w_lg_dataout46833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0lO_w_lg_dataout46806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0Oi_w_lg_dataout46779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0Ol_w_lg_dataout46752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0lO0OO_w_lg_dataout47696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO10i_dataout : STD_LOGIC; + SIGNAL wire_nli0lO10i_w_lg_dataout47497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO10l_dataout : STD_LOGIC; + SIGNAL wire_nli0lO10l_w_lg_dataout47465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO10O_dataout : STD_LOGIC; + SIGNAL wire_nli0lO10O_w_lg_dataout47433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO11i_dataout : STD_LOGIC; + SIGNAL wire_nli0lO11i_w_lg_dataout47594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO11l_dataout : STD_LOGIC; + SIGNAL wire_nli0lO11l_w_lg_dataout47560w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO11O_dataout : STD_LOGIC; + SIGNAL wire_nli0lO11O_w_lg_dataout47529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1ii_w_lg_dataout47403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1il_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1il_w_lg_dataout47373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1iO_w_lg_dataout47341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1li_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1li_w_lg_dataout47310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1ll_w_lg_dataout47280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1lO_w_lg_dataout47249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1Oi_w_lg_dataout47218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1Ol_w_lg_dataout47186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lO1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0lO1OO_w_lg_dataout47154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOi0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lOi0i_w_lg_dataout47559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOi0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lOi0l_w_lg_dataout47528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOi0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lOi0O_w_lg_dataout47496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOi1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lOi1i_w_lg_dataout47662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOi1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lOi1l_w_lg_dataout47628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOi1O_dataout : STD_LOGIC; + SIGNAL wire_nli0lOi1O_w_lg_dataout47593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOii_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiii_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiii_w_lg_dataout47464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOiil_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiil_w_lg_dataout47432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOiiO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiiO_w_lg_dataout47402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOil_dataout : STD_LOGIC; + SIGNAL wire_nli0lOili_dataout : STD_LOGIC; + SIGNAL wire_nli0lOili_w_lg_dataout47372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOill_dataout : STD_LOGIC; + SIGNAL wire_nli0lOill_w_lg_dataout47340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOilO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOilO_w_lg_dataout47309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiOi_w_lg_dataout47279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOiOl_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiOl_w_lg_dataout47248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOiOO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOiOO_w_lg_dataout47217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOl0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lOl0i_w_lg_dataout47094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOl0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lOl0l_w_lg_dataout47062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lOl0O_w_lg_dataout47030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOl1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lOl1i_w_lg_dataout47185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOl1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lOl1l_w_lg_dataout47153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOl1O_dataout : STD_LOGIC; + SIGNAL wire_nli0lOl1O_w_lg_dataout47124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOli_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlii_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlii_w_lg_dataout47001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOlil_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlil_w_lg_dataout46974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOliO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOliO_w_lg_dataout46944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOll_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlli_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlli_w_lg_dataout46915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOlll_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlll_w_lg_dataout46886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOllO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOllO_w_lg_dataout46859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlOi_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlOi_w_lg_dataout46832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOlOl_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlOl_w_lg_dataout46805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOlOO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOlOO_w_lg_dataout46778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0lOO0i_w_lg_dataout47627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0lOO0l_w_lg_dataout47592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0lOO0O_w_lg_dataout47558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0lOO1i_w_lg_dataout46751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0lOO1l_w_lg_dataout47695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0lOO1O_w_lg_dataout47661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOii_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOii_w_lg_dataout47527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOil_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOil_w_lg_dataout47495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOiO_w_lg_dataout47463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOli_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOli_w_lg_dataout47184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOll_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOll_w_lg_dataout46973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOlO_w_lg_dataout47694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOOi_w_lg_dataout47660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0lOOOl_w_lg_dataout47626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0lOOOO_dataout : STD_LOGIC; + SIGNAL wire_nli0O00i_dataout : STD_LOGIC; + SIGNAL wire_nli0O00l_dataout : STD_LOGIC; + SIGNAL wire_nli0O00O_dataout : STD_LOGIC; + SIGNAL wire_nli0O010i_dataout : STD_LOGIC; + SIGNAL wire_nli0O011i_dataout : STD_LOGIC; + SIGNAL wire_nli0O011l_dataout : STD_LOGIC; + SIGNAL wire_nli0O011O_dataout : STD_LOGIC; + SIGNAL wire_nli0O01i_dataout : STD_LOGIC; + SIGNAL wire_nli0O01l_dataout : STD_LOGIC; + SIGNAL wire_nli0O01O_dataout : STD_LOGIC; + SIGNAL wire_nli0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nli0O0il_dataout : STD_LOGIC; + SIGNAL wire_nli0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nli0O0li_dataout : STD_LOGIC; + SIGNAL wire_nli0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0O100i_dataout : STD_LOGIC; + SIGNAL wire_nli0O100l_dataout : STD_LOGIC; + SIGNAL wire_nli0O100O_dataout : STD_LOGIC; + SIGNAL wire_nli0O100O_w_lg_dataout46943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O101i_dataout : STD_LOGIC; + SIGNAL wire_nli0O101i_w_lg_dataout47093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O101l_dataout : STD_LOGIC; + SIGNAL wire_nli0O101l_w_lg_dataout47061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O101O_dataout : STD_LOGIC; + SIGNAL wire_nli0O10i_dataout : STD_LOGIC; + SIGNAL wire_nli0O10ii_dataout : STD_LOGIC; + SIGNAL wire_nli0O10il_dataout : STD_LOGIC; + SIGNAL wire_nli0O10iO_dataout : STD_LOGIC; + SIGNAL wire_nli0O10iO_w_lg_dataout46858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O10l_dataout : STD_LOGIC; + SIGNAL wire_nli0O10li_dataout : STD_LOGIC; + SIGNAL wire_nli0O10li_w_lg_dataout46831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O10ll_dataout : STD_LOGIC; + SIGNAL wire_nli0O10ll_w_lg_dataout46804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O10lO_dataout : STD_LOGIC; + SIGNAL wire_nli0O10lO_w_lg_dataout46777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O10O_dataout : STD_LOGIC; + SIGNAL wire_nli0O10Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0O10Oi_w_lg_dataout46750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O10Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0O10OO_dataout : STD_LOGIC; + SIGNAL wire_nli0O110i_dataout : STD_LOGIC; + SIGNAL wire_nli0O110l_dataout : STD_LOGIC; + SIGNAL wire_nli0O110l_w_lg_dataout47431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O110O_dataout : STD_LOGIC; + SIGNAL wire_nli0O111i_dataout : STD_LOGIC; + SIGNAL wire_nli0O111l_dataout : STD_LOGIC; + SIGNAL wire_nli0O111O_dataout : STD_LOGIC; + SIGNAL wire_nli0O111O_w_lg_dataout47494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O11i_dataout : STD_LOGIC; + SIGNAL wire_nli0O11ii_dataout : STD_LOGIC; + SIGNAL wire_nli0O11ii_w_lg_dataout47371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O11il_dataout : STD_LOGIC; + SIGNAL wire_nli0O11iO_dataout : STD_LOGIC; + SIGNAL wire_nli0O11l_dataout : STD_LOGIC; + SIGNAL wire_nli0O11li_dataout : STD_LOGIC; + SIGNAL wire_nli0O11ll_dataout : STD_LOGIC; + SIGNAL wire_nli0O11lO_dataout : STD_LOGIC; + SIGNAL wire_nli0O11O_dataout : STD_LOGIC; + SIGNAL wire_nli0O11Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0O11Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0O11OO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1i0i_dataout : STD_LOGIC; + SIGNAL wire_nli0O1i0l_dataout : STD_LOGIC; + SIGNAL wire_nli0O1i0O_dataout : STD_LOGIC; + SIGNAL wire_nli0O1i1i_dataout : STD_LOGIC; + SIGNAL wire_nli0O1i1l_dataout : STD_LOGIC; + SIGNAL wire_nli0O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nli0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nli0O1iii_dataout : STD_LOGIC; + SIGNAL wire_nli0O1iil_dataout : STD_LOGIC; + SIGNAL wire_nli0O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1il_dataout : STD_LOGIC; + SIGNAL wire_nli0O1ili_dataout : STD_LOGIC; + SIGNAL wire_nli0O1ill_dataout : STD_LOGIC; + SIGNAL wire_nli0O1ilO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1ilO_w_lg_dataout47693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1iOi_dataout : STD_LOGIC; + SIGNAL wire_nli0O1iOi_w_lg_dataout47659w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nli0O1iOl_w_lg_dataout47625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1iOO_w_lg_dataout47591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1l0i_dataout : STD_LOGIC; + SIGNAL wire_nli0O1l0i_w_lg_dataout47462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nli0O1l0l_w_lg_dataout47430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nli0O1l0O_w_lg_dataout47401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1l1i_dataout : STD_LOGIC; + SIGNAL wire_nli0O1l1i_w_lg_dataout47557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1l1l_dataout : STD_LOGIC; + SIGNAL wire_nli0O1l1l_w_lg_dataout47526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1l1O_dataout : STD_LOGIC; + SIGNAL wire_nli0O1l1O_w_lg_dataout47493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1li_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lii_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lii_w_lg_dataout47370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1lil_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lil_w_lg_dataout47339w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1liO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1liO_w_lg_dataout47308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lli_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lli_w_lg_dataout47278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1lll_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lll_w_lg_dataout47247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1llO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1llO_w_lg_dataout47216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lOi_w_lg_dataout47183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lOl_w_lg_dataout47152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1lOO_w_lg_dataout47123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nli0O1O0i_w_lg_dataout47000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1O0l_dataout : STD_LOGIC; + SIGNAL wire_nli0O1O0l_w_lg_dataout46972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1O0O_dataout : STD_LOGIC; + SIGNAL wire_nli0O1O0O_w_lg_dataout46942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nli0O1O1i_w_lg_dataout47092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nli0O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nli0O1O1O_w_lg_dataout47029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nli0O1Oii_w_lg_dataout46914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nli0O1Oil_w_lg_dataout46885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1OiO_w_lg_dataout46857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nli0O1Oli_w_lg_dataout46830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nli0O1Oll_w_lg_dataout46803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1OlO_w_lg_dataout46776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nli0O1OOi_w_lg_dataout46749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nli0O1OOl_w_lg_dataout47765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OOl_w_lg_dataout47761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli0O1OOO_w_lg_dataout47749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OOO_w_lg_dataout47737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0O1OOO_w_lg_dataout47743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nli0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oii0l_dataout : STD_LOGIC; + SIGNAL wire_nli0Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oii1i_dataout : STD_LOGIC; + SIGNAL wire_nli0Oii1l_dataout : STD_LOGIC; + SIGNAL wire_nli0Oii1O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nli0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nli0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nli0OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nli0OiiOO_dataout : STD_LOGIC; + SIGNAL wire_nli0Oil1i_dataout : STD_LOGIC; + SIGNAL wire_nli0Oili_dataout : STD_LOGIC; + SIGNAL wire_nli0Oill_dataout : STD_LOGIC; + SIGNAL wire_nli0OilO_dataout : STD_LOGIC; + SIGNAL wire_nli0OilOi_dataout : STD_LOGIC; + SIGNAL wire_nli0OilOl_dataout : STD_LOGIC; + SIGNAL wire_nli0OilOO_dataout : STD_LOGIC; + SIGNAL wire_nli0OiO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0OiO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0OiO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0OiO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0OiO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOli_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOll_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol00l_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol00O_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0li_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nli0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nli0Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nli0Oli1i_dataout : STD_LOGIC; + SIGNAL wire_nli0Oli1l_dataout : STD_LOGIC; + SIGNAL wire_nli0Olii_dataout : STD_LOGIC; + SIGNAL wire_nli0Olil_dataout : STD_LOGIC; + SIGNAL wire_nli0OliO_dataout : STD_LOGIC; + SIGNAL wire_nli0Olli_dataout : STD_LOGIC; + SIGNAL wire_nli0Olll_dataout : STD_LOGIC; + SIGNAL wire_nli0OllO_dataout : STD_LOGIC; + SIGNAL wire_nli0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nli0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nli0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nli0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nli0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nli0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nli0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nli0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nli0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nli0OOii_dataout : STD_LOGIC; + SIGNAL wire_nli0OOil_dataout : STD_LOGIC; + SIGNAL wire_nli0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nli0OOli_dataout : STD_LOGIC; + SIGNAL wire_nli0OOlii_dataout : STD_LOGIC; + SIGNAL wire_nli0OOll_dataout : STD_LOGIC; + SIGNAL wire_nli0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nli0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nli0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nli0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nli10000i_dataout : STD_LOGIC; + SIGNAL wire_nli10000l_dataout : STD_LOGIC; + SIGNAL wire_nli10000O_dataout : STD_LOGIC; + SIGNAL wire_nli1000ii_dataout : STD_LOGIC; + SIGNAL wire_nli1000il_dataout : STD_LOGIC; + SIGNAL wire_nli1000iO_dataout : STD_LOGIC; + SIGNAL wire_nli1000li_dataout : STD_LOGIC; + SIGNAL wire_nli1000ll_dataout : STD_LOGIC; + SIGNAL wire_nli1000lO_dataout : STD_LOGIC; + SIGNAL wire_nli1000Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1000Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1000OO_dataout : STD_LOGIC; + SIGNAL wire_nli100i0i_dataout : STD_LOGIC; + SIGNAL wire_nli100i0l_dataout : STD_LOGIC; + SIGNAL wire_nli100i0O_dataout : STD_LOGIC; + SIGNAL wire_nli100i1i_dataout : STD_LOGIC; + SIGNAL wire_nli100i1l_dataout : STD_LOGIC; + SIGNAL wire_nli100i1O_dataout : STD_LOGIC; + SIGNAL wire_nli100iii_dataout : STD_LOGIC; + SIGNAL wire_nli100iil_dataout : STD_LOGIC; + SIGNAL wire_nli100iiO_dataout : STD_LOGIC; + SIGNAL wire_nli100ili_dataout : STD_LOGIC; + SIGNAL wire_nli100ill_dataout : STD_LOGIC; + SIGNAL wire_nli100ilO_dataout : STD_LOGIC; + SIGNAL wire_nli100iO_dataout : STD_LOGIC; + SIGNAL wire_nli100iOi_dataout : STD_LOGIC; + SIGNAL wire_nli100iOl_dataout : STD_LOGIC; + SIGNAL wire_nli100iOO_dataout : STD_LOGIC; + SIGNAL wire_nli100l0i_dataout : STD_LOGIC; + SIGNAL wire_nli100l0l_dataout : STD_LOGIC; + SIGNAL wire_nli100l0O_dataout : STD_LOGIC; + SIGNAL wire_nli100l1i_dataout : STD_LOGIC; + SIGNAL wire_nli100l1l_dataout : STD_LOGIC; + SIGNAL wire_nli100l1O_dataout : STD_LOGIC; + SIGNAL wire_nli100li_dataout : STD_LOGIC; + SIGNAL wire_nli100lii_dataout : STD_LOGIC; + SIGNAL wire_nli100lil_dataout : STD_LOGIC; + SIGNAL wire_nli100liO_dataout : STD_LOGIC; + SIGNAL wire_nli100ll_dataout : STD_LOGIC; + SIGNAL wire_nli100lli_dataout : STD_LOGIC; + SIGNAL wire_nli100lll_dataout : STD_LOGIC; + SIGNAL wire_nli100llO_dataout : STD_LOGIC; + SIGNAL wire_nli100lO_dataout : STD_LOGIC; + SIGNAL wire_nli100lOi_dataout : STD_LOGIC; + SIGNAL wire_nli100lOl_dataout : STD_LOGIC; + SIGNAL wire_nli100lOO_dataout : STD_LOGIC; + SIGNAL wire_nli100O0i_dataout : STD_LOGIC; + SIGNAL wire_nli100O0l_dataout : STD_LOGIC; + SIGNAL wire_nli100O0O_dataout : STD_LOGIC; + SIGNAL wire_nli100O1i_dataout : STD_LOGIC; + SIGNAL wire_nli100O1l_dataout : STD_LOGIC; + SIGNAL wire_nli100O1O_dataout : STD_LOGIC; + SIGNAL wire_nli100Oi_dataout : STD_LOGIC; + SIGNAL wire_nli100Oii_dataout : STD_LOGIC; + SIGNAL wire_nli100Oil_dataout : STD_LOGIC; + SIGNAL wire_nli100OiO_dataout : STD_LOGIC; + SIGNAL wire_nli100Ol_dataout : STD_LOGIC; + SIGNAL wire_nli100Oli_dataout : STD_LOGIC; + SIGNAL wire_nli100Oll_dataout : STD_LOGIC; + SIGNAL wire_nli100OlO_dataout : STD_LOGIC; + SIGNAL wire_nli100OO_dataout : STD_LOGIC; + SIGNAL wire_nli100OOi_dataout : STD_LOGIC; + SIGNAL wire_nli100OOl_dataout : STD_LOGIC; + SIGNAL wire_nli100OOO_dataout : STD_LOGIC; + SIGNAL wire_nli10100i_dataout : STD_LOGIC; + SIGNAL wire_nli10100i_w_lg_dataout46507w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10100l_dataout : STD_LOGIC; + SIGNAL wire_nli10100l_w_lg_dataout46506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10100O_dataout : STD_LOGIC; + SIGNAL wire_nli10100O_w_lg_dataout46505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10101i_dataout : STD_LOGIC; + SIGNAL wire_nli10101i_w_lg_dataout46510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10101l_dataout : STD_LOGIC; + SIGNAL wire_nli10101l_w_lg_dataout46509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10101O_dataout : STD_LOGIC; + SIGNAL wire_nli10101O_w_lg_dataout46508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1010ii_dataout : STD_LOGIC; + SIGNAL wire_nli1010ii_w_lg_dataout46504w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10110i_dataout : STD_LOGIC; + SIGNAL wire_nli10110l_dataout : STD_LOGIC; + SIGNAL wire_nli10110O_dataout : STD_LOGIC; + SIGNAL wire_nli10110O_w_lg_dataout46503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10111i_dataout : STD_LOGIC; + SIGNAL wire_nli10111l_dataout : STD_LOGIC; + SIGNAL wire_nli10111O_dataout : STD_LOGIC; + SIGNAL wire_nli1011ii_dataout : STD_LOGIC; + SIGNAL wire_nli1011ii_w_lg_dataout46519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011il_dataout : STD_LOGIC; + SIGNAL wire_nli1011il_w_lg_dataout46518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011iO_dataout : STD_LOGIC; + SIGNAL wire_nli1011iO_w_lg_dataout46517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011li_dataout : STD_LOGIC; + SIGNAL wire_nli1011li_w_lg_dataout46516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011ll_dataout : STD_LOGIC; + SIGNAL wire_nli1011ll_w_lg_dataout46515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011lO_dataout : STD_LOGIC; + SIGNAL wire_nli1011lO_w_lg_dataout46514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1011Oi_w_lg_dataout46513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1011Ol_w_lg_dataout46512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1011OO_dataout : STD_LOGIC; + SIGNAL wire_nli1011OO_w_lg_dataout46511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli10i00i_dataout : STD_LOGIC; + SIGNAL wire_nli10i00l_dataout : STD_LOGIC; + SIGNAL wire_nli10i00O_dataout : STD_LOGIC; + SIGNAL wire_nli10i01i_dataout : STD_LOGIC; + SIGNAL wire_nli10i01l_dataout : STD_LOGIC; + SIGNAL wire_nli10i01O_dataout : STD_LOGIC; + SIGNAL wire_nli10i0i_dataout : STD_LOGIC; + SIGNAL wire_nli10i0ii_dataout : STD_LOGIC; + SIGNAL wire_nli10i0il_dataout : STD_LOGIC; + SIGNAL wire_nli10i0iO_dataout : STD_LOGIC; + SIGNAL wire_nli10i0l_dataout : STD_LOGIC; + SIGNAL wire_nli10i0li_dataout : STD_LOGIC; + SIGNAL wire_nli10i0ll_dataout : STD_LOGIC; + SIGNAL wire_nli10i0lO_dataout : STD_LOGIC; + SIGNAL wire_nli10i0O_dataout : STD_LOGIC; + SIGNAL wire_nli10i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli10i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli10i0OO_dataout : STD_LOGIC; + SIGNAL wire_nli10i10i_dataout : STD_LOGIC; + SIGNAL wire_nli10i10l_dataout : STD_LOGIC; + SIGNAL wire_nli10i10O_dataout : STD_LOGIC; + SIGNAL wire_nli10i11i_dataout : STD_LOGIC; + SIGNAL wire_nli10i11l_dataout : STD_LOGIC; + SIGNAL wire_nli10i11O_dataout : STD_LOGIC; + SIGNAL wire_nli10i1i_dataout : STD_LOGIC; + SIGNAL wire_nli10i1ii_dataout : STD_LOGIC; + SIGNAL wire_nli10i1il_dataout : STD_LOGIC; + SIGNAL wire_nli10i1iO_dataout : STD_LOGIC; + SIGNAL wire_nli10i1l_dataout : STD_LOGIC; + SIGNAL wire_nli10i1li_dataout : STD_LOGIC; + SIGNAL wire_nli10i1ll_dataout : STD_LOGIC; + SIGNAL wire_nli10i1lO_dataout : STD_LOGIC; + SIGNAL wire_nli10i1O_dataout : STD_LOGIC; + SIGNAL wire_nli10i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli10i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli10i1OO_dataout : STD_LOGIC; + SIGNAL wire_nli10ii0i_dataout : STD_LOGIC; + SIGNAL wire_nli10ii0l_dataout : STD_LOGIC; + SIGNAL wire_nli10ii0O_dataout : STD_LOGIC; + SIGNAL wire_nli10ii1i_dataout : STD_LOGIC; + SIGNAL wire_nli10ii1l_dataout : STD_LOGIC; + SIGNAL wire_nli10ii1O_dataout : STD_LOGIC; + SIGNAL wire_nli10iii_dataout : STD_LOGIC; + SIGNAL wire_nli10iiii_dataout : STD_LOGIC; + SIGNAL wire_nli10iiil_dataout : STD_LOGIC; + SIGNAL wire_nli10iiiO_dataout : STD_LOGIC; + SIGNAL wire_nli10iil_dataout : STD_LOGIC; + SIGNAL wire_nli10iili_dataout : STD_LOGIC; + SIGNAL wire_nli10iill_dataout : STD_LOGIC; + SIGNAL wire_nli10iilO_dataout : STD_LOGIC; + SIGNAL wire_nli10iiO_dataout : STD_LOGIC; + SIGNAL wire_nli10iiOi_dataout : STD_LOGIC; + SIGNAL wire_nli10iiOl_dataout : STD_LOGIC; + SIGNAL wire_nli10iiOO_dataout : STD_LOGIC; + SIGNAL wire_nli10il0l_dataout : STD_LOGIC; + SIGNAL wire_nli10il0O_dataout : STD_LOGIC; + SIGNAL wire_nli10ili_dataout : STD_LOGIC; + SIGNAL wire_nli10ilii_dataout : STD_LOGIC; + SIGNAL wire_nli10ilil_dataout : STD_LOGIC; + SIGNAL wire_nli10iliO_dataout : STD_LOGIC; + SIGNAL wire_nli10ill_dataout : STD_LOGIC; + SIGNAL wire_nli10illi_dataout : STD_LOGIC; + SIGNAL wire_nli10illl_dataout : STD_LOGIC; + SIGNAL wire_nli10illO_dataout : STD_LOGIC; + SIGNAL wire_nli10ilO_dataout : STD_LOGIC; + SIGNAL wire_nli10ilOi_dataout : STD_LOGIC; + SIGNAL wire_nli10ilOl_dataout : STD_LOGIC; + SIGNAL wire_nli10ilOO_dataout : STD_LOGIC; + SIGNAL wire_nli10iO0i_dataout : STD_LOGIC; + SIGNAL wire_nli10iO0l_dataout : STD_LOGIC; + SIGNAL wire_nli10iO0O_dataout : STD_LOGIC; + SIGNAL wire_nli10iO1i_dataout : STD_LOGIC; + SIGNAL wire_nli10iO1l_dataout : STD_LOGIC; + SIGNAL wire_nli10iO1O_dataout : STD_LOGIC; + SIGNAL wire_nli10iOi_dataout : STD_LOGIC; + SIGNAL wire_nli10iOii_dataout : STD_LOGIC; + SIGNAL wire_nli10iOil_dataout : STD_LOGIC; + SIGNAL wire_nli10iOiO_dataout : STD_LOGIC; + SIGNAL wire_nli10iOl_dataout : STD_LOGIC; + SIGNAL wire_nli10iOli_dataout : STD_LOGIC; + SIGNAL wire_nli10iOll_dataout : STD_LOGIC; + SIGNAL wire_nli10iOlO_dataout : STD_LOGIC; + SIGNAL wire_nli10iOO_dataout : STD_LOGIC; + SIGNAL wire_nli10iOOi_dataout : STD_LOGIC; + SIGNAL wire_nli10iOOl_dataout : STD_LOGIC; + SIGNAL wire_nli10iOOO_dataout : STD_LOGIC; + SIGNAL wire_nli10l00i_dataout : STD_LOGIC; + SIGNAL wire_nli10l00l_dataout : STD_LOGIC; + SIGNAL wire_nli10l00O_dataout : STD_LOGIC; + SIGNAL wire_nli10l01i_dataout : STD_LOGIC; + SIGNAL wire_nli10l01l_dataout : STD_LOGIC; + SIGNAL wire_nli10l01O_dataout : STD_LOGIC; + SIGNAL wire_nli10l0ii_dataout : STD_LOGIC; + SIGNAL wire_nli10l0il_dataout : STD_LOGIC; + SIGNAL wire_nli10l0iO_dataout : STD_LOGIC; + SIGNAL wire_nli10l0li_dataout : STD_LOGIC; + SIGNAL wire_nli10l0ll_dataout : STD_LOGIC; + SIGNAL wire_nli10l0lO_dataout : STD_LOGIC; + SIGNAL wire_nli10l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli10l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli10l0OO_dataout : STD_LOGIC; + SIGNAL wire_nli10l10i_dataout : STD_LOGIC; + SIGNAL wire_nli10l10l_dataout : STD_LOGIC; + SIGNAL wire_nli10l10O_dataout : STD_LOGIC; + SIGNAL wire_nli10l11i_dataout : STD_LOGIC; + SIGNAL wire_nli10l11l_dataout : STD_LOGIC; + SIGNAL wire_nli10l11O_dataout : STD_LOGIC; + SIGNAL wire_nli10l1i_dataout : STD_LOGIC; + SIGNAL wire_nli10l1ii_dataout : STD_LOGIC; + SIGNAL wire_nli10l1il_dataout : STD_LOGIC; + SIGNAL wire_nli10l1l_dataout : STD_LOGIC; + SIGNAL wire_nli10l1O_dataout : STD_LOGIC; + SIGNAL wire_nli10l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli10l1OO_dataout : STD_LOGIC; + SIGNAL wire_nli10li0i_dataout : STD_LOGIC; + SIGNAL wire_nli10li0l_dataout : STD_LOGIC; + SIGNAL wire_nli10li0O_dataout : STD_LOGIC; + SIGNAL wire_nli10li1i_dataout : STD_LOGIC; + SIGNAL wire_nli10li1l_dataout : STD_LOGIC; + SIGNAL wire_nli10li1O_dataout : STD_LOGIC; + SIGNAL wire_nli10liii_dataout : STD_LOGIC; + SIGNAL wire_nli10liil_dataout : STD_LOGIC; + SIGNAL wire_nli10liiO_dataout : STD_LOGIC; + SIGNAL wire_nli10lili_dataout : STD_LOGIC; + SIGNAL wire_nli10lill_dataout : STD_LOGIC; + SIGNAL wire_nli10lilO_dataout : STD_LOGIC; + SIGNAL wire_nli10liOi_dataout : STD_LOGIC; + SIGNAL wire_nli10liOl_dataout : STD_LOGIC; + SIGNAL wire_nli10liOO_dataout : STD_LOGIC; + SIGNAL wire_nli10ll1i_dataout : STD_LOGIC; + SIGNAL wire_nli10ll1l_dataout : STD_LOGIC; + SIGNAL wire_nli10llil_dataout : STD_LOGIC; + SIGNAL wire_nli10lliO_dataout : STD_LOGIC; + SIGNAL wire_nli10llli_dataout : STD_LOGIC; + SIGNAL wire_nli10llll_dataout : STD_LOGIC; + SIGNAL wire_nli10lllO_dataout : STD_LOGIC; + SIGNAL wire_nli10llOi_dataout : STD_LOGIC; + SIGNAL wire_nli10llOl_dataout : STD_LOGIC; + SIGNAL wire_nli10llOO_dataout : STD_LOGIC; + SIGNAL wire_nli10lO0i_dataout : STD_LOGIC; + SIGNAL wire_nli10lO0l_dataout : STD_LOGIC; + SIGNAL wire_nli10lO0O_dataout : STD_LOGIC; + SIGNAL wire_nli10lO1i_dataout : STD_LOGIC; + SIGNAL wire_nli10lO1l_dataout : STD_LOGIC; + SIGNAL wire_nli10lO1O_dataout : STD_LOGIC; + SIGNAL wire_nli10lOii_dataout : STD_LOGIC; + SIGNAL wire_nli10lOil_dataout : STD_LOGIC; + SIGNAL wire_nli10lOiO_dataout : STD_LOGIC; + SIGNAL wire_nli10lOli_dataout : STD_LOGIC; + SIGNAL wire_nli10lOll_dataout : STD_LOGIC; + SIGNAL wire_nli10lOlO_dataout : STD_LOGIC; + SIGNAL wire_nli10lOOi_dataout : STD_LOGIC; + SIGNAL wire_nli10lOOl_dataout : STD_LOGIC; + SIGNAL wire_nli10lOOO_dataout : STD_LOGIC; + SIGNAL wire_nli10O00i_dataout : STD_LOGIC; + SIGNAL wire_nli10O00l_dataout : STD_LOGIC; + SIGNAL wire_nli10O00O_dataout : STD_LOGIC; + SIGNAL wire_nli10O01i_dataout : STD_LOGIC; + SIGNAL wire_nli10O01l_dataout : STD_LOGIC; + SIGNAL wire_nli10O01O_dataout : STD_LOGIC; + SIGNAL wire_nli10O0ii_dataout : STD_LOGIC; + SIGNAL wire_nli10O0il_dataout : STD_LOGIC; + SIGNAL wire_nli10O0iO_dataout : STD_LOGIC; + SIGNAL wire_nli10O0li_dataout : STD_LOGIC; + SIGNAL wire_nli10O0ll_dataout : STD_LOGIC; + SIGNAL wire_nli10O0lO_dataout : STD_LOGIC; + SIGNAL wire_nli10O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli10O10i_dataout : STD_LOGIC; + SIGNAL wire_nli10O10l_dataout : STD_LOGIC; + SIGNAL wire_nli10O10O_dataout : STD_LOGIC; + SIGNAL wire_nli10O11i_dataout : STD_LOGIC; + SIGNAL wire_nli10O11l_dataout : STD_LOGIC; + SIGNAL wire_nli10O11O_dataout : STD_LOGIC; + SIGNAL wire_nli10O1ii_dataout : STD_LOGIC; + SIGNAL wire_nli10O1il_dataout : STD_LOGIC; + SIGNAL wire_nli10O1iO_dataout : STD_LOGIC; + SIGNAL wire_nli10O1li_dataout : STD_LOGIC; + SIGNAL wire_nli10O1ll_dataout : STD_LOGIC; + SIGNAL wire_nli10O1lO_dataout : STD_LOGIC; + SIGNAL wire_nli10O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli10O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli10O1OO_dataout : STD_LOGIC; + SIGNAL wire_nli10OilO_dataout : STD_LOGIC; + SIGNAL wire_nli10OiOi_dataout : STD_LOGIC; + SIGNAL wire_nli10OiOl_dataout : STD_LOGIC; + SIGNAL wire_nli10OiOO_dataout : STD_LOGIC; + SIGNAL wire_nli10Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nli10Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nli10Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nli10Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nli10OO0O_dataout : STD_LOGIC; + SIGNAL wire_nli10OOii_dataout : STD_LOGIC; + SIGNAL wire_nli10OOil_dataout : STD_LOGIC; + SIGNAL wire_nli10OOiO_dataout : STD_LOGIC; + SIGNAL wire_nli10OOli_dataout : STD_LOGIC; + SIGNAL wire_nli10OOll_dataout : STD_LOGIC; + SIGNAL wire_nli10OOlO_dataout : STD_LOGIC; + SIGNAL wire_nli10OOOi_dataout : STD_LOGIC; + SIGNAL wire_nli10OOOl_dataout : STD_LOGIC; + SIGNAL wire_nli10OOOO_dataout : STD_LOGIC; + SIGNAL wire_nli1100li_dataout : STD_LOGIC; + SIGNAL wire_nli1100ll_dataout : STD_LOGIC; + SIGNAL wire_nli1100lO_dataout : STD_LOGIC; + SIGNAL wire_nli1100Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1100Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1100OO_dataout : STD_LOGIC; + SIGNAL wire_nli1101i_dataout : STD_LOGIC; + SIGNAL wire_nli1101l_dataout : STD_LOGIC; + SIGNAL wire_nli110i0i_dataout : STD_LOGIC; + SIGNAL wire_nli110i0l_dataout : STD_LOGIC; + SIGNAL wire_nli110i0O_dataout : STD_LOGIC; + SIGNAL wire_nli110i1i_dataout : STD_LOGIC; + SIGNAL wire_nli110i1l_dataout : STD_LOGIC; + SIGNAL wire_nli110i1O_dataout : STD_LOGIC; + SIGNAL wire_nli110iii_dataout : STD_LOGIC; + SIGNAL wire_nli110iil_dataout : STD_LOGIC; + SIGNAL wire_nli110iiO_dataout : STD_LOGIC; + SIGNAL wire_nli110ili_dataout : STD_LOGIC; + SIGNAL wire_nli110ill_dataout : STD_LOGIC; + SIGNAL wire_nli110ilO_dataout : STD_LOGIC; + SIGNAL wire_nli110iOi_dataout : STD_LOGIC; + SIGNAL wire_nli110iOl_dataout : STD_LOGIC; + SIGNAL wire_nli110iOO_dataout : STD_LOGIC; + SIGNAL wire_nli110l0i_dataout : STD_LOGIC; + SIGNAL wire_nli110l0l_dataout : STD_LOGIC; + SIGNAL wire_nli110l0O_dataout : STD_LOGIC; + SIGNAL wire_nli110l1i_dataout : STD_LOGIC; + SIGNAL wire_nli110l1l_dataout : STD_LOGIC; + SIGNAL wire_nli110l1O_dataout : STD_LOGIC; + SIGNAL wire_nli110lii_dataout : STD_LOGIC; + SIGNAL wire_nli110lil_dataout : STD_LOGIC; + SIGNAL wire_nli110liO_dataout : STD_LOGIC; + SIGNAL wire_nli110lli_dataout : STD_LOGIC; + SIGNAL wire_nli110lll_dataout : STD_LOGIC; + SIGNAL wire_nli110llO_dataout : STD_LOGIC; + SIGNAL wire_nli110lOi_dataout : STD_LOGIC; + SIGNAL wire_nli110lOl_dataout : STD_LOGIC; + SIGNAL wire_nli110lOO_dataout : STD_LOGIC; + SIGNAL wire_nli110O0i_dataout : STD_LOGIC; + SIGNAL wire_nli110O0l_dataout : STD_LOGIC; + SIGNAL wire_nli110O0O_dataout : STD_LOGIC; + SIGNAL wire_nli110O1i_dataout : STD_LOGIC; + SIGNAL wire_nli110O1l_dataout : STD_LOGIC; + SIGNAL wire_nli110O1O_dataout : STD_LOGIC; + SIGNAL wire_nli110Oii_dataout : STD_LOGIC; + SIGNAL wire_nli110Oil_dataout : STD_LOGIC; + SIGNAL wire_nli110OiO_dataout : STD_LOGIC; + SIGNAL wire_nli110Oli_dataout : STD_LOGIC; + SIGNAL wire_nli110Oll_dataout : STD_LOGIC; + SIGNAL wire_nli110OlO_dataout : STD_LOGIC; + SIGNAL wire_nli110OOi_dataout : STD_LOGIC; + SIGNAL wire_nli110OOl_dataout : STD_LOGIC; + SIGNAL wire_nli110OOO_dataout : STD_LOGIC; + SIGNAL wire_nli1110l_dataout : STD_LOGIC; + SIGNAL wire_nli1110O_dataout : STD_LOGIC; + SIGNAL wire_nli11111i_dataout : STD_LOGIC; + SIGNAL wire_nli111ii_dataout : STD_LOGIC; + SIGNAL wire_nli111il_dataout : STD_LOGIC; + SIGNAL wire_nli111iO_dataout : STD_LOGIC; + SIGNAL wire_nli111li_dataout : STD_LOGIC; + SIGNAL wire_nli111ll_dataout : STD_LOGIC; + SIGNAL wire_nli111Oi_dataout : STD_LOGIC; + SIGNAL wire_nli111Ol_dataout : STD_LOGIC; + SIGNAL wire_nli111OO_dataout : STD_LOGIC; + SIGNAL wire_nli11i10i_dataout : STD_LOGIC; + SIGNAL wire_nli11i10l_dataout : STD_LOGIC; + SIGNAL wire_nli11i10O_dataout : STD_LOGIC; + SIGNAL wire_nli11i11i_dataout : STD_LOGIC; + SIGNAL wire_nli11i11l_dataout : STD_LOGIC; + SIGNAL wire_nli11i11O_dataout : STD_LOGIC; + SIGNAL wire_nli11i1ii_dataout : STD_LOGIC; + SIGNAL wire_nli11i1il_dataout : STD_LOGIC; + SIGNAL wire_nli11i1iO_dataout : STD_LOGIC; + SIGNAL wire_nli11i1li_dataout : STD_LOGIC; + SIGNAL wire_nli11i1ll_dataout : STD_LOGIC; + SIGNAL wire_nli11i1lO_dataout : STD_LOGIC; + SIGNAL wire_nli11i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli11i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli11i1OO_dataout : STD_LOGIC; + SIGNAL wire_nli11iilO_dataout : STD_LOGIC; + SIGNAL wire_nli11iiOi_dataout : STD_LOGIC; + SIGNAL wire_nli11iiOl_dataout : STD_LOGIC; + SIGNAL wire_nli11ilOl_dataout : STD_LOGIC; + SIGNAL wire_nli11ilOO_dataout : STD_LOGIC; + SIGNAL wire_nli11iO0i_dataout : STD_LOGIC; + SIGNAL wire_nli11iO0l_dataout : STD_LOGIC; + SIGNAL wire_nli11iO0O_dataout : STD_LOGIC; + SIGNAL wire_nli11iO1i_dataout : STD_LOGIC; + SIGNAL wire_nli11iO1l_dataout : STD_LOGIC; + SIGNAL wire_nli11iO1O_dataout : STD_LOGIC; + SIGNAL wire_nli11iOii_dataout : STD_LOGIC; + SIGNAL wire_nli11iOil_dataout : STD_LOGIC; + SIGNAL wire_nli11iOiO_dataout : STD_LOGIC; + SIGNAL wire_nli11iOli_dataout : STD_LOGIC; + SIGNAL wire_nli11iOOl_dataout : STD_LOGIC; + SIGNAL wire_nli11iOOO_dataout : STD_LOGIC; + SIGNAL wire_nli11l01O_dataout : STD_LOGIC; + SIGNAL wire_nli11l0lO_dataout : STD_LOGIC; + SIGNAL wire_nli11l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli11l10i_dataout : STD_LOGIC; + SIGNAL wire_nli11l10l_dataout : STD_LOGIC; + SIGNAL wire_nli11l10O_dataout : STD_LOGIC; + SIGNAL wire_nli11l1ii_dataout : STD_LOGIC; + SIGNAL wire_nli11l1il_dataout : STD_LOGIC; + SIGNAL wire_nli11l1iO_dataout : STD_LOGIC; + SIGNAL wire_nli11l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli11l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli11li0i_dataout : STD_LOGIC; + SIGNAL wire_nli11li0l_dataout : STD_LOGIC; + SIGNAL wire_nli11li1l_dataout : STD_LOGIC; + SIGNAL wire_nli11li1O_dataout : STD_LOGIC; + SIGNAL wire_nli11liiO_dataout : STD_LOGIC; + SIGNAL wire_nli11lil_dataout : STD_LOGIC; + SIGNAL wire_nli11liO_dataout : STD_LOGIC; + SIGNAL wire_nli11lli_dataout : STD_LOGIC; + SIGNAL wire_nli11lOO_dataout : STD_LOGIC; + SIGNAL wire_nli11lOO_w_lg_dataout6185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli11lOO_w_lg_dataout5921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli11O0il_dataout : STD_LOGIC; + SIGNAL wire_nli11O0iO_dataout : STD_LOGIC; + SIGNAL wire_nli11O0li_dataout : STD_LOGIC; + SIGNAL wire_nli11O0ll_dataout : STD_LOGIC; + SIGNAL wire_nli11O0lO_dataout : STD_LOGIC; + SIGNAL wire_nli11O0O_dataout : STD_LOGIC; + SIGNAL wire_nli11O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli11O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli11O0OO_dataout : STD_LOGIC; + SIGNAL wire_nli11O10i_dataout : STD_LOGIC; + SIGNAL wire_nli11O10i_w_lg_dataout46540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli11O10O_dataout : STD_LOGIC; + SIGNAL wire_nli11O10O_w_lg_dataout46537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli11O11i_dataout : STD_LOGIC; + SIGNAL wire_nli11O11i_w_lg_dataout46543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli11O11l_dataout : STD_LOGIC; + SIGNAL wire_nli11O11l_w_lg_dataout46542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli11O11O_dataout : STD_LOGIC; + SIGNAL wire_nli11O11O_w_lg_dataout46541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli11Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nli11Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nli11Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nli11Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nli11Oii_dataout : STD_LOGIC; + SIGNAL wire_nli11Oiii_dataout : STD_LOGIC; + SIGNAL wire_nli11Oiil_dataout : STD_LOGIC; + SIGNAL wire_nli11OiiO_dataout : STD_LOGIC; + SIGNAL wire_nli11Oil_dataout : STD_LOGIC; + SIGNAL wire_nli11Oili_dataout : STD_LOGIC; + SIGNAL wire_nli11Oill_dataout : STD_LOGIC; + SIGNAL wire_nli11OilO_dataout : STD_LOGIC; + SIGNAL wire_nli11OiO_dataout : STD_LOGIC; + SIGNAL wire_nli11OiOi_dataout : STD_LOGIC; + SIGNAL wire_nli11OiOO_dataout : STD_LOGIC; + SIGNAL wire_nli11Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nli11OliO_dataout : STD_LOGIC; + SIGNAL wire_nli11Olli_dataout : STD_LOGIC; + SIGNAL wire_nli11Olll_dataout : STD_LOGIC; + SIGNAL wire_nli11OllO_dataout : STD_LOGIC; + SIGNAL wire_nli11OlOi_dataout : STD_LOGIC; + SIGNAL wire_nli11OlOl_dataout : STD_LOGIC; + SIGNAL wire_nli11OO0i_dataout : STD_LOGIC; + SIGNAL wire_nli11OO0l_dataout : STD_LOGIC; + SIGNAL wire_nli11OO0O_dataout : STD_LOGIC; + SIGNAL wire_nli11OO1O_dataout : STD_LOGIC; + SIGNAL wire_nli11OOii_dataout : STD_LOGIC; + SIGNAL wire_nli11OOil_dataout : STD_LOGIC; + SIGNAL wire_nli11OOiO_dataout : STD_LOGIC; + SIGNAL wire_nli11OOli_dataout : STD_LOGIC; + SIGNAL wire_nli1i000i_dataout : STD_LOGIC; + SIGNAL wire_nli1i000l_dataout : STD_LOGIC; + SIGNAL wire_nli1i000O_dataout : STD_LOGIC; + SIGNAL wire_nli1i001l_dataout : STD_LOGIC; + SIGNAL wire_nli1i001O_dataout : STD_LOGIC; + SIGNAL wire_nli1i00ii_dataout : STD_LOGIC; + SIGNAL wire_nli1i00il_dataout : STD_LOGIC; + SIGNAL wire_nli1i00iO_dataout : STD_LOGIC; + SIGNAL wire_nli1i00li_dataout : STD_LOGIC; + SIGNAL wire_nli1i00ll_dataout : STD_LOGIC; + SIGNAL wire_nli1i00lO_dataout : STD_LOGIC; + SIGNAL wire_nli1i00Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1i00Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1i00OO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0i0i_dataout : STD_LOGIC; + SIGNAL wire_nli1i0i0l_dataout : STD_LOGIC; + SIGNAL wire_nli1i0i0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i0i1i_dataout : STD_LOGIC; + SIGNAL wire_nli1i0i1l_dataout : STD_LOGIC; + SIGNAL wire_nli1i0i1O_dataout : STD_LOGIC; + SIGNAL wire_nli1i0iii_dataout : STD_LOGIC; + SIGNAL wire_nli1i0iil_dataout : STD_LOGIC; + SIGNAL wire_nli1i0iiO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0ili_dataout : STD_LOGIC; + SIGNAL wire_nli1i0ill_dataout : STD_LOGIC; + SIGNAL wire_nli1i0ilO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0iOi_dataout : STD_LOGIC; + SIGNAL wire_nli1i0iOl_dataout : STD_LOGIC; + SIGNAL wire_nli1i0iOO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0l0i_dataout : STD_LOGIC; + SIGNAL wire_nli1i0l0l_dataout : STD_LOGIC; + SIGNAL wire_nli1i0l0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i0l1i_dataout : STD_LOGIC; + SIGNAL wire_nli1i0l1l_dataout : STD_LOGIC; + SIGNAL wire_nli1i0l1O_dataout : STD_LOGIC; + SIGNAL wire_nli1i0lii_dataout : STD_LOGIC; + SIGNAL wire_nli1i0lil_dataout : STD_LOGIC; + SIGNAL wire_nli1i0liO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0lli_dataout : STD_LOGIC; + SIGNAL wire_nli1i0lOi_dataout : STD_LOGIC; + SIGNAL wire_nli1i0O1i_dataout : STD_LOGIC; + SIGNAL wire_nli1i0O1l_dataout : STD_LOGIC; + SIGNAL wire_nli1i0O1O_dataout : STD_LOGIC; + SIGNAL wire_nli1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1i0Oii_dataout : STD_LOGIC; + SIGNAL wire_nli1i0Oil_dataout : STD_LOGIC; + SIGNAL wire_nli1i0OiO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1i0Oli_dataout : STD_LOGIC; + SIGNAL wire_nli1i0Oll_dataout : STD_LOGIC; + SIGNAL wire_nli1i0OlO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nli1i0OOi_dataout : STD_LOGIC; + SIGNAL wire_nli1i0OOl_dataout : STD_LOGIC; + SIGNAL wire_nli1i100l_dataout : STD_LOGIC; + SIGNAL wire_nli1i100O_dataout : STD_LOGIC; + SIGNAL wire_nli1i10ii_dataout : STD_LOGIC; + SIGNAL wire_nli1i10il_dataout : STD_LOGIC; + SIGNAL wire_nli1i110i_dataout : STD_LOGIC; + SIGNAL wire_nli1i110l_dataout : STD_LOGIC; + SIGNAL wire_nli1i110O_dataout : STD_LOGIC; + SIGNAL wire_nli1i111i_dataout : STD_LOGIC; + SIGNAL wire_nli1i111l_dataout : STD_LOGIC; + SIGNAL wire_nli1i111O_dataout : STD_LOGIC; + SIGNAL wire_nli1i11ii_dataout : STD_LOGIC; + SIGNAL wire_nli1i11il_dataout : STD_LOGIC; + SIGNAL wire_nli1i11iO_dataout : STD_LOGIC; + SIGNAL wire_nli1i11li_dataout : STD_LOGIC; + SIGNAL wire_nli1i11ll_dataout : STD_LOGIC; + SIGNAL wire_nli1i11lO_dataout : STD_LOGIC; + SIGNAL wire_nli1i11Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1i11Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1i11OO_dataout : STD_LOGIC; + SIGNAL wire_nli1i1i0i_dataout : STD_LOGIC; + SIGNAL wire_nli1i1i0l_dataout : STD_LOGIC; + SIGNAL wire_nli1i1i0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nli1i1iii_dataout : STD_LOGIC; + SIGNAL wire_nli1i1iil_dataout : STD_LOGIC; + SIGNAL wire_nli1i1il_dataout : STD_LOGIC; + SIGNAL wire_nli1i1ill_dataout : STD_LOGIC; + SIGNAL wire_nli1i1ilO_dataout : STD_LOGIC; + SIGNAL wire_nli1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nli1i1iOi_dataout : STD_LOGIC; + SIGNAL wire_nli1i1iOl_dataout : STD_LOGIC; + SIGNAL wire_nli1i1l0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nli1i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nli1i1li_dataout : STD_LOGIC; + SIGNAL wire_nli1i1lii_dataout : STD_LOGIC; + SIGNAL wire_nli1i1lil_dataout : STD_LOGIC; + SIGNAL wire_nli1i1llO_dataout : STD_LOGIC; + SIGNAL wire_nli1i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nli1i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nli1i1O0O_dataout : STD_LOGIC; + SIGNAL wire_nli1i1O1i_dataout : STD_LOGIC; + SIGNAL wire_nli1i1O1i_w_lg_dataout46489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1O1i_w_lg_w_lg_dataout48141w48143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1O1i_w_lg_dataout48141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nli1i1O1l_w_lg_dataout46488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1O1l_w_lg_dataout48142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1OiO_dataout : STD_LOGIC; + SIGNAL wire_nli1i1OiO_w_lg_dataout46491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1OiO_w_lg_w_lg_dataout48136w48138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1OiO_w_lg_dataout48136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1Oli_dataout : STD_LOGIC; + SIGNAL wire_nli1i1Oli_w_lg_dataout46490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1i1Oli_w_lg_dataout48137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii00i_dataout : STD_LOGIC; + SIGNAL wire_nli1ii00i_w_lg_dataout46465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii00l_dataout : STD_LOGIC; + SIGNAL wire_nli1ii00l_w_lg_dataout46464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii00O_dataout : STD_LOGIC; + SIGNAL wire_nli1ii00O_w_lg_dataout46463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii01i_dataout : STD_LOGIC; + SIGNAL wire_nli1ii01i_w_lg_dataout46468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii01l_dataout : STD_LOGIC; + SIGNAL wire_nli1ii01l_w_lg_dataout46467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii01O_dataout : STD_LOGIC; + SIGNAL wire_nli1ii01O_w_lg_dataout46466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0ii_w_lg_dataout46462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii0il_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0il_w_lg_dataout46461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii0iO_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0iO_w_lg_dataout46460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1ii0OO_dataout : STD_LOGIC; + SIGNAL wire_nli1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nli1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nli1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nli1ii1OO_dataout : STD_LOGIC; + SIGNAL wire_nli1ii1OO_w_lg_dataout46469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iii0O_dataout : STD_LOGIC; + SIGNAL wire_nli1iii0O_w_lg_dataout46419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iii1i_dataout : STD_LOGIC; + SIGNAL wire_nli1iii1l_dataout : STD_LOGIC; + SIGNAL wire_nli1iiii_dataout : STD_LOGIC; + SIGNAL wire_nli1iiiii_dataout : STD_LOGIC; + SIGNAL wire_nli1iiiii_w_lg_dataout46421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iiiil_dataout : STD_LOGIC; + SIGNAL wire_nli1iiiil_w_lg_dataout46422w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iiil_dataout : STD_LOGIC; + SIGNAL wire_nli1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nli1iiiOO_dataout : STD_LOGIC; + SIGNAL wire_nli1iil0i_dataout : STD_LOGIC; + SIGNAL wire_nli1iil0l_dataout : STD_LOGIC; + SIGNAL wire_nli1iil0O_dataout : STD_LOGIC; + SIGNAL wire_nli1iil1i_dataout : STD_LOGIC; + SIGNAL wire_nli1iil1l_dataout : STD_LOGIC; + SIGNAL wire_nli1iil1O_dataout : STD_LOGIC; + SIGNAL wire_nli1iili_dataout : STD_LOGIC; + SIGNAL wire_nli1iilii_dataout : STD_LOGIC; + SIGNAL wire_nli1iilil_dataout : STD_LOGIC; + SIGNAL wire_nli1iill_dataout : STD_LOGIC; + SIGNAL wire_nli1iilO_dataout : STD_LOGIC; + SIGNAL wire_nli1iilOl_dataout : STD_LOGIC; + SIGNAL wire_nli1iilOO_dataout : STD_LOGIC; + SIGNAL wire_nli1iiO1i_dataout : STD_LOGIC; + SIGNAL wire_nli1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nli1iiOil_dataout : STD_LOGIC; + SIGNAL wire_nli1iiOiO_dataout : STD_LOGIC; + SIGNAL wire_nli1iiOiO_w_lg_dataout46423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nli1iiOli_dataout : STD_LOGIC; + SIGNAL wire_nli1iiOli_w_lg_dataout46424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iiOll_dataout : STD_LOGIC; + SIGNAL wire_nli1iiOll_w_lg_dataout46425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nli1il00i_dataout : STD_LOGIC; + SIGNAL wire_nli1il00l_dataout : STD_LOGIC; + SIGNAL wire_nli1il01i_dataout : STD_LOGIC; + SIGNAL wire_nli1il01l_dataout : STD_LOGIC; + SIGNAL wire_nli1il01O_dataout : STD_LOGIC; + SIGNAL wire_nli1il0ii_dataout : STD_LOGIC; + SIGNAL wire_nli1il0il_dataout : STD_LOGIC; + SIGNAL wire_nli1il0iO_dataout : STD_LOGIC; + SIGNAL wire_nli1il0lO_dataout : STD_LOGIC; + SIGNAL wire_nli1il0O_dataout : STD_LOGIC; + SIGNAL wire_nli1il1i_dataout : STD_LOGIC; + SIGNAL wire_nli1il1il_dataout : STD_LOGIC; + SIGNAL wire_nli1il1iO_dataout : STD_LOGIC; + SIGNAL wire_nli1il1li_dataout : STD_LOGIC; + SIGNAL wire_nli1il1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1il1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1il1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1il1OO_dataout : STD_LOGIC; + SIGNAL wire_nli1ili0i_dataout : STD_LOGIC; + SIGNAL wire_nli1ili1i_dataout : STD_LOGIC; + SIGNAL wire_nli1ili1l_dataout : STD_LOGIC; + SIGNAL wire_nli1ili1O_dataout : STD_LOGIC; + SIGNAL wire_nli1ilii_dataout : STD_LOGIC; + SIGNAL wire_nli1iliii_dataout : STD_LOGIC; + SIGNAL wire_nli1iliil_dataout : STD_LOGIC; + SIGNAL wire_nli1iliiO_dataout : STD_LOGIC; + SIGNAL wire_nli1ilil_dataout : STD_LOGIC; + SIGNAL wire_nli1ilili_dataout : STD_LOGIC; + SIGNAL wire_nli1ilill_dataout : STD_LOGIC; + SIGNAL wire_nli1ililO_dataout : STD_LOGIC; + SIGNAL wire_nli1iliO_dataout : STD_LOGIC; + SIGNAL wire_nli1iliOl_dataout : STD_LOGIC; + SIGNAL wire_nli1iliOl_w_lg_dataout46389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1iliOO_dataout : STD_LOGIC; + SIGNAL wire_nli1ill0i_dataout : STD_LOGIC; + SIGNAL wire_nli1ill0i_w_lg_dataout46400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ill0l_dataout : STD_LOGIC; + SIGNAL wire_nli1ill0l_w_lg_dataout46399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ill0O_dataout : STD_LOGIC; + SIGNAL wire_nli1ill0O_w_lg_dataout46398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ill1i_dataout : STD_LOGIC; + SIGNAL wire_nli1ill1i_w_lg_dataout46397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ill1l_dataout : STD_LOGIC; + SIGNAL wire_nli1ill1l_w_lg_dataout46396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ill1O_dataout : STD_LOGIC; + SIGNAL wire_nli1ill1O_w_lg_dataout46395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1illi_dataout : STD_LOGIC; + SIGNAL wire_nli1illii_dataout : STD_LOGIC; + SIGNAL wire_nli1illii_w_lg_dataout46416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1illil_dataout : STD_LOGIC; + SIGNAL wire_nli1illil_w_lg_dataout46415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1illl_dataout : STD_LOGIC; + SIGNAL wire_nli1illO_dataout : STD_LOGIC; + SIGNAL wire_nli1ilO0i_dataout : STD_LOGIC; + SIGNAL wire_nli1ilO0l_dataout : STD_LOGIC; + SIGNAL wire_nli1ilO0O_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOii_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOil_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOiO_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOli_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOll_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nli1ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nli1iO00O_dataout : STD_LOGIC; + SIGNAL wire_nli1iO01i_dataout : STD_LOGIC; + SIGNAL wire_nli1iO01l_dataout : STD_LOGIC; + SIGNAL wire_nli1iO0ii_dataout : STD_LOGIC; + SIGNAL wire_nli1iO0iO_dataout : STD_LOGIC; + SIGNAL wire_nli1iO0li_dataout : STD_LOGIC; + SIGNAL wire_nli1iO0lO_dataout : STD_LOGIC; + SIGNAL wire_nli1iO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1iO10O_dataout : STD_LOGIC; + SIGNAL wire_nli1iO11i_dataout : STD_LOGIC; + SIGNAL wire_nli1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nli1iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nli1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nli1iO1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1iO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1iO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1iO1OO_dataout : STD_LOGIC; + SIGNAL wire_nli1iOi1i_dataout : STD_LOGIC; + SIGNAL wire_nli1iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nli1iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nli1iOl0O_dataout : STD_LOGIC; + SIGNAL wire_nli1iOlii_dataout : STD_LOGIC; + SIGNAL wire_nli1iOlil_dataout : STD_LOGIC; + SIGNAL wire_nli1iOliO_dataout : STD_LOGIC; + SIGNAL wire_nli1iOlli_dataout : STD_LOGIC; + SIGNAL wire_nli1iOlll_dataout : STD_LOGIC; + SIGNAL wire_nli1iOllO_dataout : STD_LOGIC; + SIGNAL wire_nli1iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nli1iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nli1iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nli1iOO0i_dataout : STD_LOGIC; + SIGNAL wire_nli1iOO0O_dataout : STD_LOGIC; + SIGNAL wire_nli1iOO1i_dataout : STD_LOGIC; + SIGNAL wire_nli1iOO1l_dataout : STD_LOGIC; + SIGNAL wire_nli1iOO1O_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOii_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOil_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOiO_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOli_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOll_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOlO_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOOi_dataout : STD_LOGIC; + SIGNAL wire_nli1iOOOl_dataout : STD_LOGIC; + SIGNAL wire_nli1l001i_dataout : STD_LOGIC; + SIGNAL wire_nli1l001l_dataout : STD_LOGIC; + SIGNAL wire_nli1l00l_dataout : STD_LOGIC; + SIGNAL wire_nli1l010i_dataout : STD_LOGIC; + SIGNAL wire_nli1l010l_dataout : STD_LOGIC; + SIGNAL wire_nli1l010O_dataout : STD_LOGIC; + SIGNAL wire_nli1l011i_dataout : STD_LOGIC; + SIGNAL wire_nli1l011l_dataout : STD_LOGIC; + SIGNAL wire_nli1l011O_dataout : STD_LOGIC; + SIGNAL wire_nli1l01ii_dataout : STD_LOGIC; + SIGNAL wire_nli1l01il_dataout : STD_LOGIC; + SIGNAL wire_nli1l01iO_dataout : STD_LOGIC; + SIGNAL wire_nli1l01li_dataout : STD_LOGIC; + SIGNAL wire_nli1l01ll_dataout : STD_LOGIC; + SIGNAL wire_nli1l01lO_dataout : STD_LOGIC; + SIGNAL wire_nli1l01O_dataout : STD_LOGIC; + SIGNAL wire_nli1l01Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1l01Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1l01OO_dataout : STD_LOGIC; + SIGNAL wire_nli1l0i0i_dataout : STD_LOGIC; + SIGNAL wire_nli1l0i0l_dataout : STD_LOGIC; + SIGNAL wire_nli1l0i0O_dataout : STD_LOGIC; + SIGNAL wire_nli1l0i1i_dataout : STD_LOGIC; + SIGNAL wire_nli1l0i1l_dataout : STD_LOGIC; + SIGNAL wire_nli1l0i1O_dataout : STD_LOGIC; + SIGNAL wire_nli1l0iii_dataout : STD_LOGIC; + SIGNAL wire_nli1l0iil_dataout : STD_LOGIC; + SIGNAL wire_nli1l0iiO_dataout : STD_LOGIC; + SIGNAL wire_nli1l0il_dataout : STD_LOGIC; + SIGNAL wire_nli1l0ili_dataout : STD_LOGIC; + SIGNAL wire_nli1l0ill_dataout : STD_LOGIC; + SIGNAL wire_nli1l0ilO_dataout : STD_LOGIC; + SIGNAL wire_nli1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nli1l0iOi_dataout : STD_LOGIC; + SIGNAL wire_nli1l0li_dataout : STD_LOGIC; + SIGNAL wire_nli1l100i_dataout : STD_LOGIC; + SIGNAL wire_nli1l100l_dataout : STD_LOGIC; + SIGNAL wire_nli1l100O_dataout : STD_LOGIC; + SIGNAL wire_nli1l101i_dataout : STD_LOGIC; + SIGNAL wire_nli1l101l_dataout : STD_LOGIC; + SIGNAL wire_nli1l101O_dataout : STD_LOGIC; + SIGNAL wire_nli1l10ii_dataout : STD_LOGIC; + SIGNAL wire_nli1l10il_dataout : STD_LOGIC; + SIGNAL wire_nli1l10iO_dataout : STD_LOGIC; + SIGNAL wire_nli1l10li_dataout : STD_LOGIC; + SIGNAL wire_nli1l10ll_dataout : STD_LOGIC; + SIGNAL wire_nli1l10lO_dataout : STD_LOGIC; + SIGNAL wire_nli1l10Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1l10Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1l10OO_dataout : STD_LOGIC; + SIGNAL wire_nli1l110i_dataout : STD_LOGIC; + SIGNAL wire_nli1l110l_dataout : STD_LOGIC; + SIGNAL wire_nli1l111i_dataout : STD_LOGIC; + SIGNAL wire_nli1l111l_dataout : STD_LOGIC; + SIGNAL wire_nli1l111O_dataout : STD_LOGIC; + SIGNAL wire_nli1l11OO_dataout : STD_LOGIC; + SIGNAL wire_nli1l1i0i_dataout : STD_LOGIC; + SIGNAL wire_nli1l1i1i_dataout : STD_LOGIC; + SIGNAL wire_nli1l1i1l_dataout : STD_LOGIC; + SIGNAL wire_nli1l1i1O_dataout : STD_LOGIC; + SIGNAL wire_nli1l1iiO_dataout : STD_LOGIC; + SIGNAL wire_nli1l1iiO_w_lg_dataout46328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1l1ili_dataout : STD_LOGIC; + SIGNAL wire_nli1l1ili_w_lg_dataout46327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1l1ill_dataout : STD_LOGIC; + SIGNAL wire_nli1l1ill_w_lg_dataout46326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1l1ilO_dataout : STD_LOGIC; + SIGNAL wire_nli1l1ilO_w_lg_w_lg_w_lg_dataout46325w48154w48155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1l1ilO_w_lg_w_lg_dataout46325w48154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1l1ilO_w_lg_dataout46325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1l1OlO_dataout : STD_LOGIC; + SIGNAL wire_nli1l1OOi_dataout : STD_LOGIC; + SIGNAL wire_nli1l1OOl_dataout : STD_LOGIC; + SIGNAL wire_nli1l1OOO_dataout : STD_LOGIC; + SIGNAL wire_nli1li00i_dataout : STD_LOGIC; + SIGNAL wire_nli1li00l_dataout : STD_LOGIC; + SIGNAL wire_nli1li00O_dataout : STD_LOGIC; + SIGNAL wire_nli1li01i_dataout : STD_LOGIC; + SIGNAL wire_nli1li01l_dataout : STD_LOGIC; + SIGNAL wire_nli1li01O_dataout : STD_LOGIC; + SIGNAL wire_nli1li0ii_dataout : STD_LOGIC; + SIGNAL wire_nli1li0il_dataout : STD_LOGIC; + SIGNAL wire_nli1li0iO_dataout : STD_LOGIC; + SIGNAL wire_nli1li0iO_w_lg_dataout47868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1li0li_dataout : STD_LOGIC; + SIGNAL wire_nli1li0ll_dataout : STD_LOGIC; + SIGNAL wire_nli1li0lO_dataout : STD_LOGIC; + SIGNAL wire_nli1li0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1li0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1li0OO_dataout : STD_LOGIC; + SIGNAL wire_nli1li1li_dataout : STD_LOGIC; + SIGNAL wire_nli1li1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1li1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1li1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1li1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1li1OO_dataout : STD_LOGIC; + SIGNAL wire_nli1lii0i_dataout : STD_LOGIC; + SIGNAL wire_nli1lii0l_dataout : STD_LOGIC; + SIGNAL wire_nli1lii0O_dataout : STD_LOGIC; + SIGNAL wire_nli1lii1i_dataout : STD_LOGIC; + SIGNAL wire_nli1lii1i_w_lg_dataout47882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lii1l_dataout : STD_LOGIC; + SIGNAL wire_nli1lii1O_dataout : STD_LOGIC; + SIGNAL wire_nli1liiii_dataout : STD_LOGIC; + SIGNAL wire_nli1liiil_dataout : STD_LOGIC; + SIGNAL wire_nli1liiiO_dataout : STD_LOGIC; + SIGNAL wire_nli1liili_dataout : STD_LOGIC; + SIGNAL wire_nli1liill_dataout : STD_LOGIC; + SIGNAL wire_nli1liilO_dataout : STD_LOGIC; + SIGNAL wire_nli1liilO_w_lg_dataout47866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1liiOi_dataout : STD_LOGIC; + SIGNAL wire_nli1liiOl_dataout : STD_LOGIC; + SIGNAL wire_nli1liiOO_dataout : STD_LOGIC; + SIGNAL wire_nli1lil0i_dataout : STD_LOGIC; + SIGNAL wire_nli1lil0i_w_lg_dataout47860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lil0l_dataout : STD_LOGIC; + SIGNAL wire_nli1lil0l_w_lg_dataout47859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lil0O_dataout : STD_LOGIC; + SIGNAL wire_nli1lil0O_w_lg_dataout47858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lil1i_dataout : STD_LOGIC; + SIGNAL wire_nli1lil1l_dataout : STD_LOGIC; + SIGNAL wire_nli1lil1l_w_lg_dataout47861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lilii_dataout : STD_LOGIC; + SIGNAL wire_nli1lilii_w_lg_dataout47857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lilil_dataout : STD_LOGIC; + SIGNAL wire_nli1lilil_w_lg_dataout47856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1liliO_dataout : STD_LOGIC; + SIGNAL wire_nli1liliO_w_lg_dataout47855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1liO0i_dataout : STD_LOGIC; + SIGNAL wire_nli1liO0l_dataout : STD_LOGIC; + SIGNAL wire_nli1liO0O_dataout : STD_LOGIC; + SIGNAL wire_nli1liOii_dataout : STD_LOGIC; + SIGNAL wire_nli1liOil_dataout : STD_LOGIC; + SIGNAL wire_nli1liOiO_dataout : STD_LOGIC; + SIGNAL wire_nli1liOli_dataout : STD_LOGIC; + SIGNAL wire_nli1liOll_dataout : STD_LOGIC; + SIGNAL wire_nli1liOlO_dataout : STD_LOGIC; + SIGNAL wire_nli1liOOi_dataout : STD_LOGIC; + SIGNAL wire_nli1liOOl_dataout : STD_LOGIC; + SIGNAL wire_nli1liOOO_dataout : STD_LOGIC; + SIGNAL wire_nli1ll01i_dataout : STD_LOGIC; + SIGNAL wire_nli1ll01l_dataout : STD_LOGIC; + SIGNAL wire_nli1ll0OO_dataout : STD_LOGIC; + SIGNAL wire_nli1ll0OO_w_lg_dataout53423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ll10O_dataout : STD_LOGIC; + SIGNAL wire_nli1ll10O_w_lg_dataout47845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1ll11i_dataout : STD_LOGIC; + SIGNAL wire_nli1ll11l_dataout : STD_LOGIC; + SIGNAL wire_nli1ll11O_dataout : STD_LOGIC; + SIGNAL wire_nli1ll1li_dataout : STD_LOGIC; + SIGNAL wire_nli1ll1ll_dataout : STD_LOGIC; + SIGNAL wire_nli1ll1lO_dataout : STD_LOGIC; + SIGNAL wire_nli1ll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1ll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1ll1OO_dataout : STD_LOGIC; + SIGNAL wire_nli1lli0i_dataout : STD_LOGIC; + SIGNAL wire_nli1lli0i_w_lg_dataout53447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lli0l_dataout : STD_LOGIC; + SIGNAL wire_nli1lli0l_w_lg_dataout53381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lli0O_dataout : STD_LOGIC; + SIGNAL wire_nli1lli0O_w_lg_dataout53379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lli1i_dataout : STD_LOGIC; + SIGNAL wire_nli1lli1i_w_lg_w_lg_dataout53427w53428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lli1i_w_lg_dataout53427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lli1l_dataout : STD_LOGIC; + SIGNAL wire_nli1lli1l_w_lg_dataout53836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lli1O_dataout : STD_LOGIC; + SIGNAL wire_nli1lli1O_w_lg_dataout53834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lliii_dataout : STD_LOGIC; + SIGNAL wire_nli1lliii_w_lg_dataout53377w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nli1lliil_dataout : STD_LOGIC; + SIGNAL wire_nli1lliiO_dataout : STD_LOGIC; + SIGNAL wire_nli1llili_dataout : STD_LOGIC; + SIGNAL wire_nli1llill_dataout : STD_LOGIC; + SIGNAL wire_nli1llilO_dataout : STD_LOGIC; + SIGNAL wire_nli1lll0i_dataout : STD_LOGIC; + SIGNAL wire_nli1lll1l_dataout : STD_LOGIC; + SIGNAL wire_nli1lll1O_dataout : STD_LOGIC; + SIGNAL wire_nli1lllii_dataout : STD_LOGIC; + SIGNAL wire_nli1lllil_dataout : STD_LOGIC; + SIGNAL wire_nli1llliO_dataout : STD_LOGIC; + SIGNAL wire_nli1lO0li_dataout : STD_LOGIC; + SIGNAL wire_nli1lO0ll_dataout : STD_LOGIC; + SIGNAL wire_nli1lO0lO_dataout : STD_LOGIC; + SIGNAL wire_nli1lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nli1lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nli1lO0OO_dataout : STD_LOGIC; + SIGNAL wire_nli1lOi0i_dataout : STD_LOGIC; + SIGNAL wire_nli1lOi0l_dataout : STD_LOGIC; + SIGNAL wire_nli1lOi0O_dataout : STD_LOGIC; + SIGNAL wire_nli1lOi1i_dataout : STD_LOGIC; + SIGNAL wire_nli1lOi1l_dataout : STD_LOGIC; + SIGNAL wire_nli1lOi1O_dataout : STD_LOGIC; + SIGNAL wire_nli1lOiii_dataout : STD_LOGIC; + SIGNAL wire_nli1lOiil_dataout : STD_LOGIC; + SIGNAL wire_nli1lOiiO_dataout : STD_LOGIC; + SIGNAL wire_nli1lOili_dataout : STD_LOGIC; + SIGNAL wire_nli1lOill_dataout : STD_LOGIC; + SIGNAL wire_nli1lOilO_dataout : STD_LOGIC; + SIGNAL wire_nli1lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nli1lOiOl_dataout : STD_LOGIC; + SIGNAL wire_nli1lOiOO_dataout : STD_LOGIC; + SIGNAL wire_nli1lOl0i_dataout : STD_LOGIC; + SIGNAL wire_nli1lOl0l_dataout : STD_LOGIC; + SIGNAL wire_nli1lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nli1lOl1i_dataout : STD_LOGIC; + SIGNAL wire_nli1lOl1l_dataout : STD_LOGIC; + SIGNAL wire_nli1lOl1O_dataout : STD_LOGIC; + SIGNAL wire_nli1lOlii_dataout : STD_LOGIC; + SIGNAL wire_nli1lOlil_dataout : STD_LOGIC; + SIGNAL wire_nli1lOliO_dataout : STD_LOGIC; + SIGNAL wire_nli1lOlli_dataout : STD_LOGIC; + SIGNAL wire_nli1lOlll_dataout : STD_LOGIC; + SIGNAL wire_nlii000i_dataout : STD_LOGIC; + SIGNAL wire_nlii000l_dataout : STD_LOGIC; + SIGNAL wire_nlii000O_dataout : STD_LOGIC; + SIGNAL wire_nlii001i_dataout : STD_LOGIC; + SIGNAL wire_nlii001l_dataout : STD_LOGIC; + SIGNAL wire_nlii001O_dataout : STD_LOGIC; + SIGNAL wire_nlii00ii_dataout : STD_LOGIC; + SIGNAL wire_nlii00il_dataout : STD_LOGIC; + SIGNAL wire_nlii00iO_dataout : STD_LOGIC; + SIGNAL wire_nlii00li_dataout : STD_LOGIC; + SIGNAL wire_nlii00liO_dataout : STD_LOGIC; + SIGNAL wire_nlii00ll_dataout : STD_LOGIC; + SIGNAL wire_nlii00lli_dataout : STD_LOGIC; + SIGNAL wire_nlii00lll_dataout : STD_LOGIC; + SIGNAL wire_nlii00llO_dataout : STD_LOGIC; + SIGNAL wire_nlii00lO_dataout : STD_LOGIC; + SIGNAL wire_nlii00lOi_dataout : STD_LOGIC; + SIGNAL wire_nlii00lOl_dataout : STD_LOGIC; + SIGNAL wire_nlii00lOO_dataout : STD_LOGIC; + SIGNAL wire_nlii00O0i_dataout : STD_LOGIC; + SIGNAL wire_nlii00O0l_dataout : STD_LOGIC; + SIGNAL wire_nlii00O0O_dataout : STD_LOGIC; + SIGNAL wire_nlii00O1i_dataout : STD_LOGIC; + SIGNAL wire_nlii00O1l_dataout : STD_LOGIC; + SIGNAL wire_nlii00O1O_dataout : STD_LOGIC; + SIGNAL wire_nlii00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii00Oii_dataout : STD_LOGIC; + SIGNAL wire_nlii00Oil_dataout : STD_LOGIC; + SIGNAL wire_nlii00OiO_dataout : STD_LOGIC; + SIGNAL wire_nlii00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii00Oli_dataout : STD_LOGIC; + SIGNAL wire_nlii00Oll_dataout : STD_LOGIC; + SIGNAL wire_nlii00OlO_dataout : STD_LOGIC; + SIGNAL wire_nlii00OO_dataout : STD_LOGIC; + SIGNAL wire_nlii00OOi_dataout : STD_LOGIC; + SIGNAL wire_nlii00OOl_dataout : STD_LOGIC; + SIGNAL wire_nlii00OOO_dataout : STD_LOGIC; + SIGNAL wire_nlii010i_dataout : STD_LOGIC; + SIGNAL wire_nlii010l_dataout : STD_LOGIC; + SIGNAL wire_nlii010O_dataout : STD_LOGIC; + SIGNAL wire_nlii011i_dataout : STD_LOGIC; + SIGNAL wire_nlii011l_dataout : STD_LOGIC; + SIGNAL wire_nlii011O_dataout : STD_LOGIC; + SIGNAL wire_nlii01ii_dataout : STD_LOGIC; + SIGNAL wire_nlii01il_dataout : STD_LOGIC; + SIGNAL wire_nlii01iO_dataout : STD_LOGIC; + SIGNAL wire_nlii01li_dataout : STD_LOGIC; + SIGNAL wire_nlii01ll_dataout : STD_LOGIC; + SIGNAL wire_nlii01lO_dataout : STD_LOGIC; + SIGNAL wire_nlii01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii01OO_dataout : STD_LOGIC; + SIGNAL wire_nlii0i00i_dataout : STD_LOGIC; + SIGNAL wire_nlii0i00l_dataout : STD_LOGIC; + SIGNAL wire_nlii0i00O_dataout : STD_LOGIC; + SIGNAL wire_nlii0i01i_dataout : STD_LOGIC; + SIGNAL wire_nlii0i01l_dataout : STD_LOGIC; + SIGNAL wire_nlii0i01O_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0il_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0li_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlii0i10i_dataout : STD_LOGIC; + SIGNAL wire_nlii0i10l_dataout : STD_LOGIC; + SIGNAL wire_nlii0i10O_dataout : STD_LOGIC; + SIGNAL wire_nlii0i11i_dataout : STD_LOGIC; + SIGNAL wire_nlii0i11l_dataout : STD_LOGIC; + SIGNAL wire_nlii0i11O_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1il_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1li_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0iii_dataout : STD_LOGIC; + SIGNAL wire_nlii0iiii_dataout : STD_LOGIC; + SIGNAL wire_nlii0iiil_dataout : STD_LOGIC; + SIGNAL wire_nlii0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlii0iil_dataout : STD_LOGIC; + SIGNAL wire_nlii0iili_dataout : STD_LOGIC; + SIGNAL wire_nlii0iill_dataout : STD_LOGIC; + SIGNAL wire_nlii0iilO_dataout : STD_LOGIC; + SIGNAL wire_nlii0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlii0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0il0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0il0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0il0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0il1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0il1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0il1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0ili_dataout : STD_LOGIC; + SIGNAL wire_nlii0ilii_dataout : STD_LOGIC; + SIGNAL wire_nlii0ilil_dataout : STD_LOGIC; + SIGNAL wire_nlii0iliO_dataout : STD_LOGIC; + SIGNAL wire_nlii0ill_dataout : STD_LOGIC; + SIGNAL wire_nlii0illi_dataout : STD_LOGIC; + SIGNAL wire_nlii0illl_dataout : STD_LOGIC; + SIGNAL wire_nlii0illO_dataout : STD_LOGIC; + SIGNAL wire_nlii0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlii0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOii_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOil_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOli_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOll_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0l00i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l00l_dataout : STD_LOGIC; + SIGNAL wire_nlii0l00O_dataout : STD_LOGIC; + SIGNAL wire_nlii0l01l_dataout : STD_LOGIC; + SIGNAL wire_nlii0l01O_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0il_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0li_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlii0l10i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l10l_dataout : STD_LOGIC; + SIGNAL wire_nlii0l10O_dataout : STD_LOGIC; + SIGNAL wire_nlii0l11i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l11l_dataout : STD_LOGIC; + SIGNAL wire_nlii0l11O_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1il_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1li_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii0li0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0li0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0li0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0li1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0li1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0li1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0lii_dataout : STD_LOGIC; + SIGNAL wire_nlii0liii_dataout : STD_LOGIC; + SIGNAL wire_nlii0liil_dataout : STD_LOGIC; + SIGNAL wire_nlii0liiO_dataout : STD_LOGIC; + SIGNAL wire_nlii0lil_dataout : STD_LOGIC; + SIGNAL wire_nlii0lili_dataout : STD_LOGIC; + SIGNAL wire_nlii0lill_dataout : STD_LOGIC; + SIGNAL wire_nlii0lilO_dataout : STD_LOGIC; + SIGNAL wire_nlii0liO_dataout : STD_LOGIC; + SIGNAL wire_nlii0liOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0liOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0liOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0lli_dataout : STD_LOGIC; + SIGNAL wire_nlii0llii_dataout : STD_LOGIC; + SIGNAL wire_nlii0llil_dataout : STD_LOGIC; + SIGNAL wire_nlii0lliO_dataout : STD_LOGIC; + SIGNAL wire_nlii0lll_dataout : STD_LOGIC; + SIGNAL wire_nlii0llli_dataout : STD_LOGIC; + SIGNAL wire_nlii0llll_dataout : STD_LOGIC; + SIGNAL wire_nlii0lllO_dataout : STD_LOGIC; + SIGNAL wire_nlii0llO_dataout : STD_LOGIC; + SIGNAL wire_nlii0llOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0llOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0llOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOii_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOil_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOli_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOll_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0O00i_dataout : STD_LOGIC; + SIGNAL wire_nlii0O00l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O00O_dataout : STD_LOGIC; + SIGNAL wire_nlii0O01i_dataout : STD_LOGIC; + SIGNAL wire_nlii0O01l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O01O_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0il_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0li_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlii0O10i_dataout : STD_LOGIC; + SIGNAL wire_nlii0O10l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O10O_dataout : STD_LOGIC; + SIGNAL wire_nlii0O11i_dataout : STD_LOGIC; + SIGNAL wire_nlii0O11l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O11O_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1il_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1li_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlii0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oili_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oill_dataout : STD_LOGIC; + SIGNAL wire_nlii0OilO_dataout : STD_LOGIC; + SIGNAL wire_nlii0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlii0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlii0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlii0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlii0Olii_dataout : STD_LOGIC; + SIGNAL wire_nlii0Olil_dataout : STD_LOGIC; + SIGNAL wire_nlii0OliO_dataout : STD_LOGIC; + SIGNAL wire_nlii0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlii0Olli_dataout : STD_LOGIC; + SIGNAL wire_nlii0Olll_dataout : STD_LOGIC; + SIGNAL wire_nlii0OllO_dataout : STD_LOGIC; + SIGNAL wire_nlii0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlii0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlii0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlii0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlii0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlii0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlii0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlii0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlii0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlii100i_dataout : STD_LOGIC; + SIGNAL wire_nlii100iO_dataout : STD_LOGIC; + SIGNAL wire_nlii100l_dataout : STD_LOGIC; + SIGNAL wire_nlii100li_dataout : STD_LOGIC; + SIGNAL wire_nlii100ll_dataout : STD_LOGIC; + SIGNAL wire_nlii100lO_dataout : STD_LOGIC; + SIGNAL wire_nlii100O_dataout : STD_LOGIC; + SIGNAL wire_nlii100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii1010i_dataout : STD_LOGIC; + SIGNAL wire_nlii1010l_dataout : STD_LOGIC; + SIGNAL wire_nlii1011i_dataout : STD_LOGIC; + SIGNAL wire_nlii1011l_dataout : STD_LOGIC; + SIGNAL wire_nlii1011O_dataout : STD_LOGIC; + SIGNAL wire_nlii101i_dataout : STD_LOGIC; + SIGNAL wire_nlii101ii_dataout : STD_LOGIC; + SIGNAL wire_nlii101il_dataout : STD_LOGIC; + SIGNAL wire_nlii101l_dataout : STD_LOGIC; + SIGNAL wire_nlii101O_dataout : STD_LOGIC; + SIGNAL wire_nlii10i0i_dataout : STD_LOGIC; + SIGNAL wire_nlii10i0l_dataout : STD_LOGIC; + SIGNAL wire_nlii10i0O_dataout : STD_LOGIC; + SIGNAL wire_nlii10i1i_dataout : STD_LOGIC; + SIGNAL wire_nlii10i1l_dataout : STD_LOGIC; + SIGNAL wire_nlii10i1O_dataout : STD_LOGIC; + SIGNAL wire_nlii10ii_dataout : STD_LOGIC; + SIGNAL wire_nlii10iii_dataout : STD_LOGIC; + SIGNAL wire_nlii10iil_dataout : STD_LOGIC; + SIGNAL wire_nlii10iiO_dataout : STD_LOGIC; + SIGNAL wire_nlii10il_dataout : STD_LOGIC; + SIGNAL wire_nlii10ili_dataout : STD_LOGIC; + SIGNAL wire_nlii10ill_dataout : STD_LOGIC; + SIGNAL wire_nlii10ilO_dataout : STD_LOGIC; + SIGNAL wire_nlii10iO_dataout : STD_LOGIC; + SIGNAL wire_nlii10iOi_dataout : STD_LOGIC; + SIGNAL wire_nlii10iOl_dataout : STD_LOGIC; + SIGNAL wire_nlii10iOO_dataout : STD_LOGIC; + SIGNAL wire_nlii10l0i_dataout : STD_LOGIC; + SIGNAL wire_nlii10l0l_dataout : STD_LOGIC; + SIGNAL wire_nlii10l0O_dataout : STD_LOGIC; + SIGNAL wire_nlii10l1i_dataout : STD_LOGIC; + SIGNAL wire_nlii10l1O_dataout : STD_LOGIC; + SIGNAL wire_nlii10li_dataout : STD_LOGIC; + SIGNAL wire_nlii10lii_dataout : STD_LOGIC; + SIGNAL wire_nlii10lil_dataout : STD_LOGIC; + SIGNAL wire_nlii10liO_dataout : STD_LOGIC; + SIGNAL wire_nlii10ll_dataout : STD_LOGIC; + SIGNAL wire_nlii10lli_dataout : STD_LOGIC; + SIGNAL wire_nlii10lll_dataout : STD_LOGIC; + SIGNAL wire_nlii10llO_dataout : STD_LOGIC; + SIGNAL wire_nlii10lO_dataout : STD_LOGIC; + SIGNAL wire_nlii10lOi_dataout : STD_LOGIC; + SIGNAL wire_nlii10lOl_dataout : STD_LOGIC; + SIGNAL wire_nlii10lOO_dataout : STD_LOGIC; + SIGNAL wire_nlii10O1i_dataout : STD_LOGIC; + SIGNAL wire_nlii10O1l_dataout : STD_LOGIC; + SIGNAL wire_nlii10O1O_dataout : STD_LOGIC; + SIGNAL wire_nlii10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii10OO_dataout : STD_LOGIC; + SIGNAL wire_nlii110i_dataout : STD_LOGIC; + SIGNAL wire_nlii110l_dataout : STD_LOGIC; + SIGNAL wire_nlii110O_dataout : STD_LOGIC; + SIGNAL wire_nlii111i_dataout : STD_LOGIC; + SIGNAL wire_nlii111l_dataout : STD_LOGIC; + SIGNAL wire_nlii111O_dataout : STD_LOGIC; + SIGNAL wire_nlii11ii_dataout : STD_LOGIC; + SIGNAL wire_nlii11iil_dataout : STD_LOGIC; + SIGNAL wire_nlii11iiO_dataout : STD_LOGIC; + SIGNAL wire_nlii11il_dataout : STD_LOGIC; + SIGNAL wire_nlii11ili_dataout : STD_LOGIC; + SIGNAL wire_nlii11ill_dataout : STD_LOGIC; + SIGNAL wire_nlii11ilO_dataout : STD_LOGIC; + SIGNAL wire_nlii11iO_dataout : STD_LOGIC; + SIGNAL wire_nlii11iOi_dataout : STD_LOGIC; + SIGNAL wire_nlii11iOl_dataout : STD_LOGIC; + SIGNAL wire_nlii11iOO_dataout : STD_LOGIC; + SIGNAL wire_nlii11l0i_dataout : STD_LOGIC; + SIGNAL wire_nlii11l0l_dataout : STD_LOGIC; + SIGNAL wire_nlii11l0O_dataout : STD_LOGIC; + SIGNAL wire_nlii11l1i_dataout : STD_LOGIC; + SIGNAL wire_nlii11l1l_dataout : STD_LOGIC; + SIGNAL wire_nlii11l1O_dataout : STD_LOGIC; + SIGNAL wire_nlii11li_dataout : STD_LOGIC; + SIGNAL wire_nlii11lii_dataout : STD_LOGIC; + SIGNAL wire_nlii11lil_dataout : STD_LOGIC; + SIGNAL wire_nlii11liO_dataout : STD_LOGIC; + SIGNAL wire_nlii11ll_dataout : STD_LOGIC; + SIGNAL wire_nlii11lli_dataout : STD_LOGIC; + SIGNAL wire_nlii11lll_dataout : STD_LOGIC; + SIGNAL wire_nlii11llO_dataout : STD_LOGIC; + SIGNAL wire_nlii11lO_dataout : STD_LOGIC; + SIGNAL wire_nlii11lOi_dataout : STD_LOGIC; + SIGNAL wire_nlii11lOl_dataout : STD_LOGIC; + SIGNAL wire_nlii11lOO_dataout : STD_LOGIC; + SIGNAL wire_nlii11O0i_dataout : STD_LOGIC; + SIGNAL wire_nlii11O0l_dataout : STD_LOGIC; + SIGNAL wire_nlii11O0O_dataout : STD_LOGIC; + SIGNAL wire_nlii11O1i_dataout : STD_LOGIC; + SIGNAL wire_nlii11O1l_dataout : STD_LOGIC; + SIGNAL wire_nlii11O1O_dataout : STD_LOGIC; + SIGNAL wire_nlii11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii11Oii_dataout : STD_LOGIC; + SIGNAL wire_nlii11Oil_dataout : STD_LOGIC; + SIGNAL wire_nlii11OiO_dataout : STD_LOGIC; + SIGNAL wire_nlii11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii11Oli_dataout : STD_LOGIC; + SIGNAL wire_nlii11Oll_dataout : STD_LOGIC; + SIGNAL wire_nlii11OlO_dataout : STD_LOGIC; + SIGNAL wire_nlii11OO_dataout : STD_LOGIC; + SIGNAL wire_nlii11OOi_dataout : STD_LOGIC; + SIGNAL wire_nlii11OOl_dataout : STD_LOGIC; + SIGNAL wire_nlii11OOO_dataout : STD_LOGIC; + SIGNAL wire_nlii1i00i_dataout : STD_LOGIC; + SIGNAL wire_nlii1i00l_dataout : STD_LOGIC; + SIGNAL wire_nlii1i00O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i01i_dataout : STD_LOGIC; + SIGNAL wire_nlii1i01l_dataout : STD_LOGIC; + SIGNAL wire_nlii1i01O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0il_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0li_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii1iii_dataout : STD_LOGIC; + SIGNAL wire_nlii1iiii_dataout : STD_LOGIC; + SIGNAL wire_nlii1iiil_dataout : STD_LOGIC; + SIGNAL wire_nlii1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlii1iil_dataout : STD_LOGIC; + SIGNAL wire_nlii1iili_dataout : STD_LOGIC; + SIGNAL wire_nlii1iill_dataout : STD_LOGIC; + SIGNAL wire_nlii1iilO_dataout : STD_LOGIC; + SIGNAL wire_nlii1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlii1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlii1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlii1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlii1il0i_dataout : STD_LOGIC; + SIGNAL wire_nlii1il1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1il1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1il1O_dataout : STD_LOGIC; + SIGNAL wire_nlii1ili_dataout : STD_LOGIC; + SIGNAL wire_nlii1ill_dataout : STD_LOGIC; + SIGNAL wire_nlii1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlii1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlii1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlii1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlii1l00i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l00l_dataout : STD_LOGIC; + SIGNAL wire_nlii1l00O_dataout : STD_LOGIC; + SIGNAL wire_nlii1l01i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l01l_dataout : STD_LOGIC; + SIGNAL wire_nlii1l01O_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0il_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0li_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlii1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlii1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlii1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlii1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlii1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlii1li0i_dataout : STD_LOGIC; + SIGNAL wire_nlii1li0l_dataout : STD_LOGIC; + SIGNAL wire_nlii1li0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1li1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1li1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1li1O_dataout : STD_LOGIC; + SIGNAL wire_nlii1lii_dataout : STD_LOGIC; + SIGNAL wire_nlii1liii_dataout : STD_LOGIC; + SIGNAL wire_nlii1liil_dataout : STD_LOGIC; + SIGNAL wire_nlii1liiO_dataout : STD_LOGIC; + SIGNAL wire_nlii1lil_dataout : STD_LOGIC; + SIGNAL wire_nlii1lili_dataout : STD_LOGIC; + SIGNAL wire_nlii1lill_dataout : STD_LOGIC; + SIGNAL wire_nlii1lilO_dataout : STD_LOGIC; + SIGNAL wire_nlii1liO_dataout : STD_LOGIC; + SIGNAL wire_nlii1liOi_dataout : STD_LOGIC; + SIGNAL wire_nlii1liOl_dataout : STD_LOGIC; + SIGNAL wire_nlii1liOO_dataout : STD_LOGIC; + SIGNAL wire_nlii1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlii1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlii1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlii1lli_dataout : STD_LOGIC; + SIGNAL wire_nlii1llii_dataout : STD_LOGIC; + SIGNAL wire_nlii1llil_dataout : STD_LOGIC; + SIGNAL wire_nlii1lliO_dataout : STD_LOGIC; + SIGNAL wire_nlii1lll_dataout : STD_LOGIC; + SIGNAL wire_nlii1llli_dataout : STD_LOGIC; + SIGNAL wire_nlii1llll_dataout : STD_LOGIC; + SIGNAL wire_nlii1lllO_dataout : STD_LOGIC; + SIGNAL wire_nlii1llO_dataout : STD_LOGIC; + SIGNAL wire_nlii1llOi_dataout : STD_LOGIC; + SIGNAL wire_nlii1llOl_dataout : STD_LOGIC; + SIGNAL wire_nlii1llOO_dataout : STD_LOGIC; + SIGNAL wire_nlii1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlii1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlii1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOii_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOil_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOli_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOll_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlii1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlii1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlii1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlii1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlii1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlii1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlii1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlii1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlii1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlii1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlii1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlii1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlii1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlii1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlii1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlii1OOO_dataout : STD_LOGIC; + SIGNAL wire_nliii000l_dataout : STD_LOGIC; + SIGNAL wire_nliii000O_dataout : STD_LOGIC; + SIGNAL wire_nliii00i_dataout : STD_LOGIC; + SIGNAL wire_nliii00iO_dataout : STD_LOGIC; + SIGNAL wire_nliii00l_dataout : STD_LOGIC; + SIGNAL wire_nliii00li_dataout : STD_LOGIC; + SIGNAL wire_nliii00O_dataout : STD_LOGIC; + SIGNAL wire_nliii00Ol_dataout : STD_LOGIC; + SIGNAL wire_nliii00OO_dataout : STD_LOGIC; + SIGNAL wire_nliii010i_dataout : STD_LOGIC; + SIGNAL wire_nliii010l_dataout : STD_LOGIC; + SIGNAL wire_nliii010O_dataout : STD_LOGIC; + SIGNAL wire_nliii011i_dataout : STD_LOGIC; + SIGNAL wire_nliii011l_dataout : STD_LOGIC; + SIGNAL wire_nliii011O_dataout : STD_LOGIC; + SIGNAL wire_nliii01i_dataout : STD_LOGIC; + SIGNAL wire_nliii01ii_dataout : STD_LOGIC; + SIGNAL wire_nliii01il_dataout : STD_LOGIC; + SIGNAL wire_nliii01iO_dataout : STD_LOGIC; + SIGNAL wire_nliii01l_dataout : STD_LOGIC; + SIGNAL wire_nliii01li_dataout : STD_LOGIC; + SIGNAL wire_nliii01ll_dataout : STD_LOGIC; + SIGNAL wire_nliii01O_dataout : STD_LOGIC; + SIGNAL wire_nliii0i0l_dataout : STD_LOGIC; + SIGNAL wire_nliii0i0O_dataout : STD_LOGIC; + SIGNAL wire_nliii0ii_dataout : STD_LOGIC; + SIGNAL wire_nliii0il_dataout : STD_LOGIC; + SIGNAL wire_nliii0ili_dataout : STD_LOGIC; + SIGNAL wire_nliii0ill_dataout : STD_LOGIC; + SIGNAL wire_nliii0iO_dataout : STD_LOGIC; + SIGNAL wire_nliii0l1l_dataout : STD_LOGIC; + SIGNAL wire_nliii0l1O_dataout : STD_LOGIC; + SIGNAL wire_nliii0li_dataout : STD_LOGIC; + SIGNAL wire_nliii0lii_dataout : STD_LOGIC; + SIGNAL wire_nliii0lil_dataout : STD_LOGIC; + SIGNAL wire_nliii0ll_dataout : STD_LOGIC; + SIGNAL wire_nliii0lO_dataout : STD_LOGIC; + SIGNAL wire_nliii0O0i_dataout : STD_LOGIC; + SIGNAL wire_nliii0O0l_dataout : STD_LOGIC; + SIGNAL wire_nliii0O0O_dataout : STD_LOGIC; + SIGNAL wire_nliii0O1O_dataout : STD_LOGIC; + SIGNAL wire_nliii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliii0Oii_dataout : STD_LOGIC; + SIGNAL wire_nliii0Oil_dataout : STD_LOGIC; + SIGNAL wire_nliii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliii0OO_dataout : STD_LOGIC; + SIGNAL wire_nliii10i_dataout : STD_LOGIC; + SIGNAL wire_nliii10ii_dataout : STD_LOGIC; + SIGNAL wire_nliii10il_dataout : STD_LOGIC; + SIGNAL wire_nliii10iO_dataout : STD_LOGIC; + SIGNAL wire_nliii10l_dataout : STD_LOGIC; + SIGNAL wire_nliii10li_dataout : STD_LOGIC; + SIGNAL wire_nliii10ll_dataout : STD_LOGIC; + SIGNAL wire_nliii10lO_dataout : STD_LOGIC; + SIGNAL wire_nliii10O_dataout : STD_LOGIC; + SIGNAL wire_nliii10Oi_dataout : STD_LOGIC; + SIGNAL wire_nliii10Ol_dataout : STD_LOGIC; + SIGNAL wire_nliii10OO_dataout : STD_LOGIC; + SIGNAL wire_nliii11i_dataout : STD_LOGIC; + SIGNAL wire_nliii11l_dataout : STD_LOGIC; + SIGNAL wire_nliii11O_dataout : STD_LOGIC; + SIGNAL wire_nliii1i0i_dataout : STD_LOGIC; + SIGNAL wire_nliii1i0l_dataout : STD_LOGIC; + SIGNAL wire_nliii1i0O_dataout : STD_LOGIC; + SIGNAL wire_nliii1i1i_dataout : STD_LOGIC; + SIGNAL wire_nliii1i1l_dataout : STD_LOGIC; + SIGNAL wire_nliii1i1O_dataout : STD_LOGIC; + SIGNAL wire_nliii1ii_dataout : STD_LOGIC; + SIGNAL wire_nliii1iii_dataout : STD_LOGIC; + SIGNAL wire_nliii1iil_dataout : STD_LOGIC; + SIGNAL wire_nliii1iiO_dataout : STD_LOGIC; + SIGNAL wire_nliii1il_dataout : STD_LOGIC; + SIGNAL wire_nliii1ili_dataout : STD_LOGIC; + SIGNAL wire_nliii1ill_dataout : STD_LOGIC; + SIGNAL wire_nliii1ilO_dataout : STD_LOGIC; + SIGNAL wire_nliii1iO_dataout : STD_LOGIC; + SIGNAL wire_nliii1iOi_dataout : STD_LOGIC; + SIGNAL wire_nliii1iOl_dataout : STD_LOGIC; + SIGNAL wire_nliii1iOO_dataout : STD_LOGIC; + SIGNAL wire_nliii1l0i_dataout : STD_LOGIC; + SIGNAL wire_nliii1l0l_dataout : STD_LOGIC; + SIGNAL wire_nliii1l0O_dataout : STD_LOGIC; + SIGNAL wire_nliii1l1i_dataout : STD_LOGIC; + SIGNAL wire_nliii1l1l_dataout : STD_LOGIC; + SIGNAL wire_nliii1l1O_dataout : STD_LOGIC; + SIGNAL wire_nliii1li_dataout : STD_LOGIC; + SIGNAL wire_nliii1lii_dataout : STD_LOGIC; + SIGNAL wire_nliii1lil_dataout : STD_LOGIC; + SIGNAL wire_nliii1ll_dataout : STD_LOGIC; + SIGNAL wire_nliii1lli_dataout : STD_LOGIC; + SIGNAL wire_nliii1lll_dataout : STD_LOGIC; + SIGNAL wire_nliii1llO_dataout : STD_LOGIC; + SIGNAL wire_nliii1lO_dataout : STD_LOGIC; + SIGNAL wire_nliii1lOi_dataout : STD_LOGIC; + SIGNAL wire_nliii1lOl_dataout : STD_LOGIC; + SIGNAL wire_nliii1lOO_dataout : STD_LOGIC; + SIGNAL wire_nliii1O0i_dataout : STD_LOGIC; + SIGNAL wire_nliii1O0l_dataout : STD_LOGIC; + SIGNAL wire_nliii1O0O_dataout : STD_LOGIC; + SIGNAL wire_nliii1O1i_dataout : STD_LOGIC; + SIGNAL wire_nliii1O1l_dataout : STD_LOGIC; + SIGNAL wire_nliii1O1O_dataout : STD_LOGIC; + SIGNAL wire_nliii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliii1Oii_dataout : STD_LOGIC; + SIGNAL wire_nliii1Oil_dataout : STD_LOGIC; + SIGNAL wire_nliii1OiO_dataout : STD_LOGIC; + SIGNAL wire_nliii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliii1Oli_dataout : STD_LOGIC; + SIGNAL wire_nliii1Oll_dataout : STD_LOGIC; + SIGNAL wire_nliii1OlO_dataout : STD_LOGIC; + SIGNAL wire_nliii1OO_dataout : STD_LOGIC; + SIGNAL wire_nliii1OOi_dataout : STD_LOGIC; + SIGNAL wire_nliii1OOl_dataout : STD_LOGIC; + SIGNAL wire_nliii1OOO_dataout : STD_LOGIC; + SIGNAL wire_nliiii0i_dataout : STD_LOGIC; + SIGNAL wire_nliiii0l_dataout : STD_LOGIC; + SIGNAL wire_nliiii0O_dataout : STD_LOGIC; + SIGNAL wire_nliiii1i_dataout : STD_LOGIC; + SIGNAL wire_nliiii1l_dataout : STD_LOGIC; + SIGNAL wire_nliiii1O_dataout : STD_LOGIC; + SIGNAL wire_nliiiiii_dataout : STD_LOGIC; + SIGNAL wire_nliiiiil_dataout : STD_LOGIC; + SIGNAL wire_nliiiiiO_dataout : STD_LOGIC; + SIGNAL wire_nliiiili_dataout : STD_LOGIC; + SIGNAL wire_nliiiill_dataout : STD_LOGIC; + SIGNAL wire_nliiiilO_dataout : STD_LOGIC; + SIGNAL wire_nliiiiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiiiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiiiOO_dataout : STD_LOGIC; + SIGNAL wire_nliiil0i_dataout : STD_LOGIC; + SIGNAL wire_nliiil0l_dataout : STD_LOGIC; + SIGNAL wire_nliiil0O_dataout : STD_LOGIC; + SIGNAL wire_nliiil1i_dataout : STD_LOGIC; + SIGNAL wire_nliiil1l_dataout : STD_LOGIC; + SIGNAL wire_nliiil1O_dataout : STD_LOGIC; + SIGNAL wire_nliiilii_dataout : STD_LOGIC; + SIGNAL wire_nliiilil_dataout : STD_LOGIC; + SIGNAL wire_nliiiliO_dataout : STD_LOGIC; + SIGNAL wire_nliiilli_dataout : STD_LOGIC; + SIGNAL wire_nliiillii_dataout : STD_LOGIC; + SIGNAL wire_nliiillil_dataout : STD_LOGIC; + SIGNAL wire_nliiilliO_dataout : STD_LOGIC; + SIGNAL wire_nliiilll_dataout : STD_LOGIC; + SIGNAL wire_nliiillli_dataout : STD_LOGIC; + SIGNAL wire_nliiillll_dataout : STD_LOGIC; + SIGNAL wire_nliiilllO_dataout : STD_LOGIC; + SIGNAL wire_nliiillO_dataout : STD_LOGIC; + SIGNAL wire_nliiillOi_dataout : STD_LOGIC; + SIGNAL wire_nliiillOl_dataout : STD_LOGIC; + SIGNAL wire_nliiillOO_dataout : STD_LOGIC; + SIGNAL wire_nliiilO0i_dataout : STD_LOGIC; + SIGNAL wire_nliiilO0l_dataout : STD_LOGIC; + SIGNAL wire_nliiilO0O_dataout : STD_LOGIC; + SIGNAL wire_nliiilO1i_dataout : STD_LOGIC; + SIGNAL wire_nliiilO1l_dataout : STD_LOGIC; + SIGNAL wire_nliiilO1O_dataout : STD_LOGIC; + SIGNAL wire_nliiilOii_dataout : STD_LOGIC; + SIGNAL wire_nliiilOil_dataout : STD_LOGIC; + SIGNAL wire_nliiilOiO_dataout : STD_LOGIC; + SIGNAL wire_nliiilOl_dataout : STD_LOGIC; + SIGNAL wire_nliiilOli_dataout : STD_LOGIC; + SIGNAL wire_nliiilOll_dataout : STD_LOGIC; + SIGNAL wire_nliiilOlO_dataout : STD_LOGIC; + SIGNAL wire_nliiilOO_dataout : STD_LOGIC; + SIGNAL wire_nliiilOOi_dataout : STD_LOGIC; + SIGNAL wire_nliiilOOl_dataout : STD_LOGIC; + SIGNAL wire_nliiilOOO_dataout : STD_LOGIC; + SIGNAL wire_nliiiO00i_dataout : STD_LOGIC; + SIGNAL wire_nliiiO00l_dataout : STD_LOGIC; + SIGNAL wire_nliiiO00O_dataout : STD_LOGIC; + SIGNAL wire_nliiiO01i_dataout : STD_LOGIC; + SIGNAL wire_nliiiO01l_dataout : STD_LOGIC; + SIGNAL wire_nliiiO01O_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0i_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0ii_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0il_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0l_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0li_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0ll_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0lO_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0O_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliiiO0OO_dataout : STD_LOGIC; + SIGNAL wire_nliiiO10i_dataout : STD_LOGIC; + SIGNAL wire_nliiiO10l_dataout : STD_LOGIC; + SIGNAL wire_nliiiO10O_dataout : STD_LOGIC; + SIGNAL wire_nliiiO11i_dataout : STD_LOGIC; + SIGNAL wire_nliiiO11l_dataout : STD_LOGIC; + SIGNAL wire_nliiiO11O_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1i_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1ii_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1il_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1iO_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1l_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1li_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1ll_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1lO_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1O_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliiiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOi0i_dataout : STD_LOGIC; + SIGNAL wire_nliiiOi0l_dataout : STD_LOGIC; + SIGNAL wire_nliiiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nliiiOi1i_dataout : STD_LOGIC; + SIGNAL wire_nliiiOi1l_dataout : STD_LOGIC; + SIGNAL wire_nliiiOi1O_dataout : STD_LOGIC; + SIGNAL wire_nliiiOii_dataout : STD_LOGIC; + SIGNAL wire_nliiiOiii_dataout : STD_LOGIC; + SIGNAL wire_nliiiOiil_dataout : STD_LOGIC; + SIGNAL wire_nliiiOiiO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOil_dataout : STD_LOGIC; + SIGNAL wire_nliiiOili_dataout : STD_LOGIC; + SIGNAL wire_nliiiOill_dataout : STD_LOGIC; + SIGNAL wire_nliiiOilO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOiO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nliiiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nliiiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nliiiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nliiiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nliiiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nliiiOli_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlii_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlil_dataout : STD_LOGIC; + SIGNAL wire_nliiiOliO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOll_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlli_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlll_dataout : STD_LOGIC; + SIGNAL wire_nliiiOllO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nliiiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nliiiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nliiiOO0O_dataout : STD_LOGIC; + SIGNAL wire_nliiiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nliiiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nliiiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOii_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOil_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOiO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOli_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOll_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nliiiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nliil000i_dataout : STD_LOGIC; + SIGNAL wire_nliil000l_dataout : STD_LOGIC; + SIGNAL wire_nliil000O_dataout : STD_LOGIC; + SIGNAL wire_nliil001i_dataout : STD_LOGIC; + SIGNAL wire_nliil001l_dataout : STD_LOGIC; + SIGNAL wire_nliil001O_dataout : STD_LOGIC; + SIGNAL wire_nliil00i_dataout : STD_LOGIC; + SIGNAL wire_nliil00ii_dataout : STD_LOGIC; + SIGNAL wire_nliil00il_dataout : STD_LOGIC; + SIGNAL wire_nliil00iO_dataout : STD_LOGIC; + SIGNAL wire_nliil00l_dataout : STD_LOGIC; + SIGNAL wire_nliil00li_dataout : STD_LOGIC; + SIGNAL wire_nliil00ll_dataout : STD_LOGIC; + SIGNAL wire_nliil00lO_dataout : STD_LOGIC; + SIGNAL wire_nliil00O_dataout : STD_LOGIC; + SIGNAL wire_nliil00Oi_dataout : STD_LOGIC; + SIGNAL wire_nliil00Ol_dataout : STD_LOGIC; + SIGNAL wire_nliil00OO_dataout : STD_LOGIC; + SIGNAL wire_nliil010i_dataout : STD_LOGIC; + SIGNAL wire_nliil010l_dataout : STD_LOGIC; + SIGNAL wire_nliil010O_dataout : STD_LOGIC; + SIGNAL wire_nliil011i_dataout : STD_LOGIC; + SIGNAL wire_nliil011l_dataout : STD_LOGIC; + SIGNAL wire_nliil011O_dataout : STD_LOGIC; + SIGNAL wire_nliil01i_dataout : STD_LOGIC; + SIGNAL wire_nliil01ii_dataout : STD_LOGIC; + SIGNAL wire_nliil01il_dataout : STD_LOGIC; + SIGNAL wire_nliil01iO_dataout : STD_LOGIC; + SIGNAL wire_nliil01l_dataout : STD_LOGIC; + SIGNAL wire_nliil01li_dataout : STD_LOGIC; + SIGNAL wire_nliil01ll_dataout : STD_LOGIC; + SIGNAL wire_nliil01lO_dataout : STD_LOGIC; + SIGNAL wire_nliil01O_dataout : STD_LOGIC; + SIGNAL wire_nliil01Oi_dataout : STD_LOGIC; + SIGNAL wire_nliil01Ol_dataout : STD_LOGIC; + SIGNAL wire_nliil01OO_dataout : STD_LOGIC; + SIGNAL wire_nliil0i0i_dataout : STD_LOGIC; + SIGNAL wire_nliil0i0l_dataout : STD_LOGIC; + SIGNAL wire_nliil0i0O_dataout : STD_LOGIC; + SIGNAL wire_nliil0i1i_dataout : STD_LOGIC; + SIGNAL wire_nliil0i1l_dataout : STD_LOGIC; + SIGNAL wire_nliil0i1O_dataout : STD_LOGIC; + SIGNAL wire_nliil0ii_dataout : STD_LOGIC; + SIGNAL wire_nliil0iii_dataout : STD_LOGIC; + SIGNAL wire_nliil0iil_dataout : STD_LOGIC; + SIGNAL wire_nliil0iiO_dataout : STD_LOGIC; + SIGNAL wire_nliil0il_dataout : STD_LOGIC; + SIGNAL wire_nliil0ili_dataout : STD_LOGIC; + SIGNAL wire_nliil0ill_dataout : STD_LOGIC; + SIGNAL wire_nliil0ilO_dataout : STD_LOGIC; + SIGNAL wire_nliil0iO_dataout : STD_LOGIC; + SIGNAL wire_nliil0iOi_dataout : STD_LOGIC; + SIGNAL wire_nliil0iOl_dataout : STD_LOGIC; + SIGNAL wire_nliil0iOO_dataout : STD_LOGIC; + SIGNAL wire_nliil0l0i_dataout : STD_LOGIC; + SIGNAL wire_nliil0l0l_dataout : STD_LOGIC; + SIGNAL wire_nliil0l0O_dataout : STD_LOGIC; + SIGNAL wire_nliil0l1i_dataout : STD_LOGIC; + SIGNAL wire_nliil0l1l_dataout : STD_LOGIC; + SIGNAL wire_nliil0l1O_dataout : STD_LOGIC; + SIGNAL wire_nliil0li_dataout : STD_LOGIC; + SIGNAL wire_nliil0lii_dataout : STD_LOGIC; + SIGNAL wire_nliil0lil_dataout : STD_LOGIC; + SIGNAL wire_nliil0liO_dataout : STD_LOGIC; + SIGNAL wire_nliil0ll_dataout : STD_LOGIC; + SIGNAL wire_nliil0lli_dataout : STD_LOGIC; + SIGNAL wire_nliil0lll_dataout : STD_LOGIC; + SIGNAL wire_nliil0llO_dataout : STD_LOGIC; + SIGNAL wire_nliil0lO_dataout : STD_LOGIC; + SIGNAL wire_nliil0lOi_dataout : STD_LOGIC; + SIGNAL wire_nliil0lOl_dataout : STD_LOGIC; + SIGNAL wire_nliil0lOO_dataout : STD_LOGIC; + SIGNAL wire_nliil0O0i_dataout : STD_LOGIC; + SIGNAL wire_nliil0O0l_dataout : STD_LOGIC; + SIGNAL wire_nliil0O0O_dataout : STD_LOGIC; + SIGNAL wire_nliil0O1i_dataout : STD_LOGIC; + SIGNAL wire_nliil0O1l_dataout : STD_LOGIC; + SIGNAL wire_nliil0O1O_dataout : STD_LOGIC; + SIGNAL wire_nliil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliil0Oii_dataout : STD_LOGIC; + SIGNAL wire_nliil0Oil_dataout : STD_LOGIC; + SIGNAL wire_nliil0OiO_dataout : STD_LOGIC; + SIGNAL wire_nliil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliil0Oli_dataout : STD_LOGIC; + SIGNAL wire_nliil0Oll_dataout : STD_LOGIC; + SIGNAL wire_nliil0OlO_dataout : STD_LOGIC; + SIGNAL wire_nliil0OO_dataout : STD_LOGIC; + SIGNAL wire_nliil0OOi_dataout : STD_LOGIC; + SIGNAL wire_nliil0OOl_dataout : STD_LOGIC; + SIGNAL wire_nliil0OOO_dataout : STD_LOGIC; + SIGNAL wire_nliil100i_dataout : STD_LOGIC; + SIGNAL wire_nliil100l_dataout : STD_LOGIC; + SIGNAL wire_nliil100O_dataout : STD_LOGIC; + SIGNAL wire_nliil101i_dataout : STD_LOGIC; + SIGNAL wire_nliil101l_dataout : STD_LOGIC; + SIGNAL wire_nliil101O_dataout : STD_LOGIC; + SIGNAL wire_nliil10i_dataout : STD_LOGIC; + SIGNAL wire_nliil10ii_dataout : STD_LOGIC; + SIGNAL wire_nliil10il_dataout : STD_LOGIC; + SIGNAL wire_nliil10iO_dataout : STD_LOGIC; + SIGNAL wire_nliil10l_dataout : STD_LOGIC; + SIGNAL wire_nliil10li_dataout : STD_LOGIC; + SIGNAL wire_nliil10ll_dataout : STD_LOGIC; + SIGNAL wire_nliil10lO_dataout : STD_LOGIC; + SIGNAL wire_nliil10O_dataout : STD_LOGIC; + SIGNAL wire_nliil10Oi_dataout : STD_LOGIC; + SIGNAL wire_nliil10Ol_dataout : STD_LOGIC; + SIGNAL wire_nliil10OO_dataout : STD_LOGIC; + SIGNAL wire_nliil110i_dataout : STD_LOGIC; + SIGNAL wire_nliil110l_dataout : STD_LOGIC; + SIGNAL wire_nliil110O_dataout : STD_LOGIC; + SIGNAL wire_nliil111i_dataout : STD_LOGIC; + SIGNAL wire_nliil111l_dataout : STD_LOGIC; + SIGNAL wire_nliil111O_dataout : STD_LOGIC; + SIGNAL wire_nliil11i_dataout : STD_LOGIC; + SIGNAL wire_nliil11ii_dataout : STD_LOGIC; + SIGNAL wire_nliil11il_dataout : STD_LOGIC; + SIGNAL wire_nliil11iO_dataout : STD_LOGIC; + SIGNAL wire_nliil11l_dataout : STD_LOGIC; + SIGNAL wire_nliil11li_dataout : STD_LOGIC; + SIGNAL wire_nliil11ll_dataout : STD_LOGIC; + SIGNAL wire_nliil11lO_dataout : STD_LOGIC; + SIGNAL wire_nliil11O_dataout : STD_LOGIC; + SIGNAL wire_nliil11Oi_dataout : STD_LOGIC; + SIGNAL wire_nliil11Ol_dataout : STD_LOGIC; + SIGNAL wire_nliil11OO_dataout : STD_LOGIC; + SIGNAL wire_nliil1i0i_dataout : STD_LOGIC; + SIGNAL wire_nliil1i0l_dataout : STD_LOGIC; + SIGNAL wire_nliil1i0O_dataout : STD_LOGIC; + SIGNAL wire_nliil1i1i_dataout : STD_LOGIC; + SIGNAL wire_nliil1i1l_dataout : STD_LOGIC; + SIGNAL wire_nliil1i1O_dataout : STD_LOGIC; + SIGNAL wire_nliil1ii_dataout : STD_LOGIC; + SIGNAL wire_nliil1iii_dataout : STD_LOGIC; + SIGNAL wire_nliil1iil_dataout : STD_LOGIC; + SIGNAL wire_nliil1iiO_dataout : STD_LOGIC; + SIGNAL wire_nliil1il_dataout : STD_LOGIC; + SIGNAL wire_nliil1ili_dataout : STD_LOGIC; + SIGNAL wire_nliil1ill_dataout : STD_LOGIC; + SIGNAL wire_nliil1ilO_dataout : STD_LOGIC; + SIGNAL wire_nliil1iO_dataout : STD_LOGIC; + SIGNAL wire_nliil1iOi_dataout : STD_LOGIC; + SIGNAL wire_nliil1iOl_dataout : STD_LOGIC; + SIGNAL wire_nliil1iOO_dataout : STD_LOGIC; + SIGNAL wire_nliil1l0i_dataout : STD_LOGIC; + SIGNAL wire_nliil1l0l_dataout : STD_LOGIC; + SIGNAL wire_nliil1l0O_dataout : STD_LOGIC; + SIGNAL wire_nliil1l1i_dataout : STD_LOGIC; + SIGNAL wire_nliil1l1l_dataout : STD_LOGIC; + SIGNAL wire_nliil1l1O_dataout : STD_LOGIC; + SIGNAL wire_nliil1li_dataout : STD_LOGIC; + SIGNAL wire_nliil1lii_dataout : STD_LOGIC; + SIGNAL wire_nliil1lil_dataout : STD_LOGIC; + SIGNAL wire_nliil1liO_dataout : STD_LOGIC; + SIGNAL wire_nliil1ll_dataout : STD_LOGIC; + SIGNAL wire_nliil1lli_dataout : STD_LOGIC; + SIGNAL wire_nliil1lll_dataout : STD_LOGIC; + SIGNAL wire_nliil1llO_dataout : STD_LOGIC; + SIGNAL wire_nliil1lO_dataout : STD_LOGIC; + SIGNAL wire_nliil1lOi_dataout : STD_LOGIC; + SIGNAL wire_nliil1lOl_dataout : STD_LOGIC; + SIGNAL wire_nliil1lOO_dataout : STD_LOGIC; + SIGNAL wire_nliil1O0i_dataout : STD_LOGIC; + SIGNAL wire_nliil1O0l_dataout : STD_LOGIC; + SIGNAL wire_nliil1O0O_dataout : STD_LOGIC; + SIGNAL wire_nliil1O1i_dataout : STD_LOGIC; + SIGNAL wire_nliil1O1l_dataout : STD_LOGIC; + SIGNAL wire_nliil1O1O_dataout : STD_LOGIC; + SIGNAL wire_nliil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliil1Oii_dataout : STD_LOGIC; + SIGNAL wire_nliil1Oil_dataout : STD_LOGIC; + SIGNAL wire_nliil1OiO_dataout : STD_LOGIC; + SIGNAL wire_nliil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliil1Oli_dataout : STD_LOGIC; + SIGNAL wire_nliil1Oll_dataout : STD_LOGIC; + SIGNAL wire_nliil1OlO_dataout : STD_LOGIC; + SIGNAL wire_nliil1OO_dataout : STD_LOGIC; + SIGNAL wire_nliil1OOi_dataout : STD_LOGIC; + SIGNAL wire_nliil1OOl_dataout : STD_LOGIC; + SIGNAL wire_nliil1OOO_dataout : STD_LOGIC; + SIGNAL wire_nliili00i_dataout : STD_LOGIC; + SIGNAL wire_nliili00l_dataout : STD_LOGIC; + SIGNAL wire_nliili00O_dataout : STD_LOGIC; + SIGNAL wire_nliili01i_dataout : STD_LOGIC; + SIGNAL wire_nliili01l_dataout : STD_LOGIC; + SIGNAL wire_nliili01O_dataout : STD_LOGIC; + SIGNAL wire_nliili0ii_dataout : STD_LOGIC; + SIGNAL wire_nliili0il_dataout : STD_LOGIC; + SIGNAL wire_nliili0iO_dataout : STD_LOGIC; + SIGNAL wire_nliili0li_dataout : STD_LOGIC; + SIGNAL wire_nliili0ll_dataout : STD_LOGIC; + SIGNAL wire_nliili0lO_dataout : STD_LOGIC; + SIGNAL wire_nliili0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliili0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliili0OO_dataout : STD_LOGIC; + SIGNAL wire_nliili10i_dataout : STD_LOGIC; + SIGNAL wire_nliili10l_dataout : STD_LOGIC; + SIGNAL wire_nliili10O_dataout : STD_LOGIC; + SIGNAL wire_nliili11i_dataout : STD_LOGIC; + SIGNAL wire_nliili11l_dataout : STD_LOGIC; + SIGNAL wire_nliili11O_dataout : STD_LOGIC; + SIGNAL wire_nliili1i_dataout : STD_LOGIC; + SIGNAL wire_nliili1ii_dataout : STD_LOGIC; + SIGNAL wire_nliili1il_dataout : STD_LOGIC; + SIGNAL wire_nliili1iO_dataout : STD_LOGIC; + SIGNAL wire_nliili1li_dataout : STD_LOGIC; + SIGNAL wire_nliili1ll_dataout : STD_LOGIC; + SIGNAL wire_nliili1lO_dataout : STD_LOGIC; + SIGNAL wire_nliili1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliili1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliili1OO_dataout : STD_LOGIC; + SIGNAL wire_nliilii0i_dataout : STD_LOGIC; + SIGNAL wire_nliilii0l_dataout : STD_LOGIC; + SIGNAL wire_nliilii0O_dataout : STD_LOGIC; + SIGNAL wire_nliilii1i_dataout : STD_LOGIC; + SIGNAL wire_nliilii1l_dataout : STD_LOGIC; + SIGNAL wire_nliilii1O_dataout : STD_LOGIC; + SIGNAL wire_nliiliiii_dataout : STD_LOGIC; + SIGNAL wire_nliiliiil_dataout : STD_LOGIC; + SIGNAL wire_nliiliiiO_dataout : STD_LOGIC; + SIGNAL wire_nliiliil_dataout : STD_LOGIC; + SIGNAL wire_nliiliill_dataout : STD_LOGIC; + SIGNAL wire_nliiliilO_dataout : STD_LOGIC; + SIGNAL wire_nliiliiO_dataout : STD_LOGIC; + SIGNAL wire_nliiliiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiliiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiliiOO_dataout : STD_LOGIC; + SIGNAL wire_nliilil0i_dataout : STD_LOGIC; + SIGNAL wire_nliilil0l_dataout : STD_LOGIC; + SIGNAL wire_nliilil0O_dataout : STD_LOGIC; + SIGNAL wire_nliilil1i_dataout : STD_LOGIC; + SIGNAL wire_nliilil1l_dataout : STD_LOGIC; + SIGNAL wire_nliilil1O_dataout : STD_LOGIC; + SIGNAL wire_nliilili_dataout : STD_LOGIC; + SIGNAL wire_nliililii_dataout : STD_LOGIC; + SIGNAL wire_nliililil_dataout : STD_LOGIC; + SIGNAL wire_nliililiO_dataout : STD_LOGIC; + SIGNAL wire_nliilill_dataout : STD_LOGIC; + SIGNAL wire_nliililli_dataout : STD_LOGIC; + SIGNAL wire_nliililll_dataout : STD_LOGIC; + SIGNAL wire_nliilillO_dataout : STD_LOGIC; + SIGNAL wire_nliililOi_dataout : STD_LOGIC; + SIGNAL wire_nliililOl_dataout : STD_LOGIC; + SIGNAL wire_nliililOO_dataout : STD_LOGIC; + SIGNAL wire_nliiliO0i_dataout : STD_LOGIC; + SIGNAL wire_nliiliO0l_dataout : STD_LOGIC; + SIGNAL wire_nliiliO0O_dataout : STD_LOGIC; + SIGNAL wire_nliiliO1i_dataout : STD_LOGIC; + SIGNAL wire_nliiliO1l_dataout : STD_LOGIC; + SIGNAL wire_nliiliO1O_dataout : STD_LOGIC; + SIGNAL wire_nliiliOii_dataout : STD_LOGIC; + SIGNAL wire_nliiliOil_dataout : STD_LOGIC; + SIGNAL wire_nliiliOiO_dataout : STD_LOGIC; + SIGNAL wire_nliiliOl_dataout : STD_LOGIC; + SIGNAL wire_nliiliOli_dataout : STD_LOGIC; + SIGNAL wire_nliiliOll_dataout : STD_LOGIC; + SIGNAL wire_nliiliOlO_dataout : STD_LOGIC; + SIGNAL wire_nliiliOO_dataout : STD_LOGIC; + SIGNAL wire_nliiliOOi_dataout : STD_LOGIC; + SIGNAL wire_nliiliOOl_dataout : STD_LOGIC; + SIGNAL wire_nliiliOOO_dataout : STD_LOGIC; + SIGNAL wire_nliill00i_dataout : STD_LOGIC; + SIGNAL wire_nliill00l_dataout : STD_LOGIC; + SIGNAL wire_nliill00O_dataout : STD_LOGIC; + SIGNAL wire_nliill01i_dataout : STD_LOGIC; + SIGNAL wire_nliill01l_dataout : STD_LOGIC; + SIGNAL wire_nliill01O_dataout : STD_LOGIC; + SIGNAL wire_nliill0i_dataout : STD_LOGIC; + SIGNAL wire_nliill0ii_dataout : STD_LOGIC; + SIGNAL wire_nliill0il_dataout : STD_LOGIC; + SIGNAL wire_nliill0iO_dataout : STD_LOGIC; + SIGNAL wire_nliill0l_dataout : STD_LOGIC; + SIGNAL wire_nliill0li_dataout : STD_LOGIC; + SIGNAL wire_nliill0ll_dataout : STD_LOGIC; + SIGNAL wire_nliill0lO_dataout : STD_LOGIC; + SIGNAL wire_nliill0O_dataout : STD_LOGIC; + SIGNAL wire_nliill0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliill0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliill0OO_dataout : STD_LOGIC; + SIGNAL wire_nliill10i_dataout : STD_LOGIC; + SIGNAL wire_nliill10l_dataout : STD_LOGIC; + SIGNAL wire_nliill10O_dataout : STD_LOGIC; + SIGNAL wire_nliill11i_dataout : STD_LOGIC; + SIGNAL wire_nliill11l_dataout : STD_LOGIC; + SIGNAL wire_nliill11O_dataout : STD_LOGIC; + SIGNAL wire_nliill1i_dataout : STD_LOGIC; + SIGNAL wire_nliill1ii_dataout : STD_LOGIC; + SIGNAL wire_nliill1il_dataout : STD_LOGIC; + SIGNAL wire_nliill1iO_dataout : STD_LOGIC; + SIGNAL wire_nliill1l_dataout : STD_LOGIC; + SIGNAL wire_nliill1li_dataout : STD_LOGIC; + SIGNAL wire_nliill1ll_dataout : STD_LOGIC; + SIGNAL wire_nliill1lO_dataout : STD_LOGIC; + SIGNAL wire_nliill1O_dataout : STD_LOGIC; + SIGNAL wire_nliill1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliill1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliill1OO_dataout : STD_LOGIC; + SIGNAL wire_nliilli0i_dataout : STD_LOGIC; + SIGNAL wire_nliilli0l_dataout : STD_LOGIC; + SIGNAL wire_nliilli0O_dataout : STD_LOGIC; + SIGNAL wire_nliilli1i_dataout : STD_LOGIC; + SIGNAL wire_nliilli1l_dataout : STD_LOGIC; + SIGNAL wire_nliilli1O_dataout : STD_LOGIC; + SIGNAL wire_nliillii_dataout : STD_LOGIC; + SIGNAL wire_nliilliii_dataout : STD_LOGIC; + SIGNAL wire_nliilliil_dataout : STD_LOGIC; + SIGNAL wire_nliilliiO_dataout : STD_LOGIC; + SIGNAL wire_nliillil_dataout : STD_LOGIC; + SIGNAL wire_nliillili_dataout : STD_LOGIC; + SIGNAL wire_nliillill_dataout : STD_LOGIC; + SIGNAL wire_nliillilO_dataout : STD_LOGIC; + SIGNAL wire_nliilliO_dataout : STD_LOGIC; + SIGNAL wire_nliilliOi_dataout : STD_LOGIC; + SIGNAL wire_nliilliOl_dataout : STD_LOGIC; + SIGNAL wire_nliilliOO_dataout : STD_LOGIC; + SIGNAL wire_nliilll0i_dataout : STD_LOGIC; + SIGNAL wire_nliilll0l_dataout : STD_LOGIC; + SIGNAL wire_nliilll0O_dataout : STD_LOGIC; + SIGNAL wire_nliilll1i_dataout : STD_LOGIC; + SIGNAL wire_nliilll1l_dataout : STD_LOGIC; + SIGNAL wire_nliilll1O_dataout : STD_LOGIC; + SIGNAL wire_nliillli_dataout : STD_LOGIC; + SIGNAL wire_nliilllii_dataout : STD_LOGIC; + SIGNAL wire_nliilllil_dataout : STD_LOGIC; + SIGNAL wire_nliillliO_dataout : STD_LOGIC; + SIGNAL wire_nliillll_dataout : STD_LOGIC; + SIGNAL wire_nliilllli_dataout : STD_LOGIC; + SIGNAL wire_nliilllll_dataout : STD_LOGIC; + SIGNAL wire_nliillllO_dataout : STD_LOGIC; + SIGNAL wire_nliilllO_dataout : STD_LOGIC; + SIGNAL wire_nliilllOi_dataout : STD_LOGIC; + SIGNAL wire_nliilllOl_dataout : STD_LOGIC; + SIGNAL wire_nliilllOO_dataout : STD_LOGIC; + SIGNAL wire_nliillO0i_dataout : STD_LOGIC; + SIGNAL wire_nliillO0l_dataout : STD_LOGIC; + SIGNAL wire_nliillO0O_dataout : STD_LOGIC; + SIGNAL wire_nliillO1i_dataout : STD_LOGIC; + SIGNAL wire_nliillO1l_dataout : STD_LOGIC; + SIGNAL wire_nliillO1O_dataout : STD_LOGIC; + SIGNAL wire_nliillOi_dataout : STD_LOGIC; + SIGNAL wire_nliillOii_dataout : STD_LOGIC; + SIGNAL wire_nliillOil_dataout : STD_LOGIC; + SIGNAL wire_nliillOiO_dataout : STD_LOGIC; + SIGNAL wire_nliillOl_dataout : STD_LOGIC; + SIGNAL wire_nliillOli_dataout : STD_LOGIC; + SIGNAL wire_nliillOll_dataout : STD_LOGIC; + SIGNAL wire_nliillOlO_dataout : STD_LOGIC; + SIGNAL wire_nliillOO_dataout : STD_LOGIC; + SIGNAL wire_nliillOOi_dataout : STD_LOGIC; + SIGNAL wire_nliillOOl_dataout : STD_LOGIC; + SIGNAL wire_nliillOOO_dataout : STD_LOGIC; + SIGNAL wire_nliilO00i_dataout : STD_LOGIC; + SIGNAL wire_nliilO00l_dataout : STD_LOGIC; + SIGNAL wire_nliilO00O_dataout : STD_LOGIC; + SIGNAL wire_nliilO01i_dataout : STD_LOGIC; + SIGNAL wire_nliilO01l_dataout : STD_LOGIC; + SIGNAL wire_nliilO01O_dataout : STD_LOGIC; + SIGNAL wire_nliilO0i_dataout : STD_LOGIC; + SIGNAL wire_nliilO0ii_dataout : STD_LOGIC; + SIGNAL wire_nliilO0il_dataout : STD_LOGIC; + SIGNAL wire_nliilO0iO_dataout : STD_LOGIC; + SIGNAL wire_nliilO0l_dataout : STD_LOGIC; + SIGNAL wire_nliilO0li_dataout : STD_LOGIC; + SIGNAL wire_nliilO0ll_dataout : STD_LOGIC; + SIGNAL wire_nliilO0lO_dataout : STD_LOGIC; + SIGNAL wire_nliilO0O_dataout : STD_LOGIC; + SIGNAL wire_nliilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliilO0OO_dataout : STD_LOGIC; + SIGNAL wire_nliilO10i_dataout : STD_LOGIC; + SIGNAL wire_nliilO10l_dataout : STD_LOGIC; + SIGNAL wire_nliilO10O_dataout : STD_LOGIC; + SIGNAL wire_nliilO11i_dataout : STD_LOGIC; + SIGNAL wire_nliilO11l_dataout : STD_LOGIC; + SIGNAL wire_nliilO11O_dataout : STD_LOGIC; + SIGNAL wire_nliilO1i_dataout : STD_LOGIC; + SIGNAL wire_nliilO1ii_dataout : STD_LOGIC; + SIGNAL wire_nliilO1il_dataout : STD_LOGIC; + SIGNAL wire_nliilO1iO_dataout : STD_LOGIC; + SIGNAL wire_nliilO1l_dataout : STD_LOGIC; + SIGNAL wire_nliilO1li_dataout : STD_LOGIC; + SIGNAL wire_nliilO1ll_dataout : STD_LOGIC; + SIGNAL wire_nliilO1lO_dataout : STD_LOGIC; + SIGNAL wire_nliilO1O_dataout : STD_LOGIC; + SIGNAL wire_nliilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliilO1OO_dataout : STD_LOGIC; + SIGNAL wire_nliilOi0i_dataout : STD_LOGIC; + SIGNAL wire_nliilOi0l_dataout : STD_LOGIC; + SIGNAL wire_nliilOi0O_dataout : STD_LOGIC; + SIGNAL wire_nliilOi1i_dataout : STD_LOGIC; + SIGNAL wire_nliilOi1l_dataout : STD_LOGIC; + SIGNAL wire_nliilOi1O_dataout : STD_LOGIC; + SIGNAL wire_nliilOii_dataout : STD_LOGIC; + SIGNAL wire_nliilOiii_dataout : STD_LOGIC; + SIGNAL wire_nliilOiil_dataout : STD_LOGIC; + SIGNAL wire_nliilOiiO_dataout : STD_LOGIC; + SIGNAL wire_nliilOil_dataout : STD_LOGIC; + SIGNAL wire_nliilOili_dataout : STD_LOGIC; + SIGNAL wire_nliilOill_dataout : STD_LOGIC; + SIGNAL wire_nliilOilO_dataout : STD_LOGIC; + SIGNAL wire_nliilOiO_dataout : STD_LOGIC; + SIGNAL wire_nliilOiOi_dataout : STD_LOGIC; + SIGNAL wire_nliilOiOl_dataout : STD_LOGIC; + SIGNAL wire_nliilOiOO_dataout : STD_LOGIC; + SIGNAL wire_nliilOl0i_dataout : STD_LOGIC; + SIGNAL wire_nliilOl0l_dataout : STD_LOGIC; + SIGNAL wire_nliilOl1i_dataout : STD_LOGIC; + SIGNAL wire_nliilOl1l_dataout : STD_LOGIC; + SIGNAL wire_nliilOl1O_dataout : STD_LOGIC; + SIGNAL wire_nliilOli_dataout : STD_LOGIC; + SIGNAL wire_nliilOlil_dataout : STD_LOGIC; + SIGNAL wire_nliilOliO_dataout : STD_LOGIC; + SIGNAL wire_nliilOll_dataout : STD_LOGIC; + SIGNAL wire_nliilOlli_dataout : STD_LOGIC; + SIGNAL wire_nliilOlll_dataout : STD_LOGIC; + SIGNAL wire_nliilOllO_dataout : STD_LOGIC; + SIGNAL wire_nliilOlO_dataout : STD_LOGIC; + SIGNAL wire_nliilOlOi_dataout : STD_LOGIC; + SIGNAL wire_nliilOlOl_dataout : STD_LOGIC; + SIGNAL wire_nliilOlOO_dataout : STD_LOGIC; + SIGNAL wire_nliilOO0i_dataout : STD_LOGIC; + SIGNAL wire_nliilOO0l_dataout : STD_LOGIC; + SIGNAL wire_nliilOO0O_dataout : STD_LOGIC; + SIGNAL wire_nliilOO1i_dataout : STD_LOGIC; + SIGNAL wire_nliilOO1l_dataout : STD_LOGIC; + SIGNAL wire_nliilOO1O_dataout : STD_LOGIC; + SIGNAL wire_nliilOOi_dataout : STD_LOGIC; + SIGNAL wire_nliilOOii_dataout : STD_LOGIC; + SIGNAL wire_nliilOOil_dataout : STD_LOGIC; + SIGNAL wire_nliilOOiO_dataout : STD_LOGIC; + SIGNAL wire_nliilOOl_dataout : STD_LOGIC; + SIGNAL wire_nliilOOli_dataout : STD_LOGIC; + SIGNAL wire_nliilOOll_dataout : STD_LOGIC; + SIGNAL wire_nliilOOlO_dataout : STD_LOGIC; + SIGNAL wire_nliilOOO_dataout : STD_LOGIC; + SIGNAL wire_nliilOOOi_dataout : STD_LOGIC; + SIGNAL wire_nliilOOOl_dataout : STD_LOGIC; + SIGNAL wire_nliilOOOO_dataout : STD_LOGIC; + SIGNAL wire_nliiO000l_dataout : STD_LOGIC; + SIGNAL wire_nliiO000O_dataout : STD_LOGIC; + SIGNAL wire_nliiO001i_dataout : STD_LOGIC; + SIGNAL wire_nliiO001l_dataout : STD_LOGIC; + SIGNAL wire_nliiO00i_dataout : STD_LOGIC; + SIGNAL wire_nliiO00iO_dataout : STD_LOGIC; + SIGNAL wire_nliiO00l_dataout : STD_LOGIC; + SIGNAL wire_nliiO00li_dataout : STD_LOGIC; + SIGNAL wire_nliiO00O_dataout : STD_LOGIC; + SIGNAL wire_nliiO010i_dataout : STD_LOGIC; + SIGNAL wire_nliiO011O_dataout : STD_LOGIC; + SIGNAL wire_nliiO01i_dataout : STD_LOGIC; + SIGNAL wire_nliiO01ii_dataout : STD_LOGIC; + SIGNAL wire_nliiO01il_dataout : STD_LOGIC; + SIGNAL wire_nliiO01l_dataout : STD_LOGIC; + SIGNAL wire_nliiO01ll_dataout : STD_LOGIC; + SIGNAL wire_nliiO01lO_dataout : STD_LOGIC; + SIGNAL wire_nliiO01O_dataout : STD_LOGIC; + SIGNAL wire_nliiO0ii_dataout : STD_LOGIC; + SIGNAL wire_nliiO0il_dataout : STD_LOGIC; + SIGNAL wire_nliiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nliiO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nliiO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nliiO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nliiO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nliiO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nliiO0li_dataout : STD_LOGIC; + SIGNAL wire_nliiO0lil_dataout : STD_LOGIC; + SIGNAL wire_nliiO0liO_dataout : STD_LOGIC; + SIGNAL wire_nliiO0ll_dataout : STD_LOGIC; + SIGNAL wire_nliiO0lli_dataout : STD_LOGIC; + SIGNAL wire_nliiO0lll_dataout : STD_LOGIC; + SIGNAL wire_nliiO0lO_dataout : STD_LOGIC; + SIGNAL wire_nliiO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nliiO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nliiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliiO0OO_dataout : STD_LOGIC; + SIGNAL wire_nliiO10i_dataout : STD_LOGIC; + SIGNAL wire_nliiO10il_dataout : STD_LOGIC; + SIGNAL wire_nliiO10l_dataout : STD_LOGIC; + SIGNAL wire_nliiO10O_dataout : STD_LOGIC; + SIGNAL wire_nliiO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nliiO110i_dataout : STD_LOGIC; + SIGNAL wire_nliiO110l_dataout : STD_LOGIC; + SIGNAL wire_nliiO110O_dataout : STD_LOGIC; + SIGNAL wire_nliiO111i_dataout : STD_LOGIC; + SIGNAL wire_nliiO111l_dataout : STD_LOGIC; + SIGNAL wire_nliiO111O_dataout : STD_LOGIC; + SIGNAL wire_nliiO11i_dataout : STD_LOGIC; + SIGNAL wire_nliiO11ii_dataout : STD_LOGIC; + SIGNAL wire_nliiO11il_dataout : STD_LOGIC; + SIGNAL wire_nliiO11iO_dataout : STD_LOGIC; + SIGNAL wire_nliiO11l_dataout : STD_LOGIC; + SIGNAL wire_nliiO11li_dataout : STD_LOGIC; + SIGNAL wire_nliiO11ll_dataout : STD_LOGIC; + SIGNAL wire_nliiO11lO_dataout : STD_LOGIC; + SIGNAL wire_nliiO11O_dataout : STD_LOGIC; + SIGNAL wire_nliiO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nliiO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nliiO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nliiO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nliiO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nliiO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nliiO1ii_dataout : STD_LOGIC; + SIGNAL wire_nliiO1iii_dataout : STD_LOGIC; + SIGNAL wire_nliiO1iil_dataout : STD_LOGIC; + SIGNAL wire_nliiO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nliiO1il_dataout : STD_LOGIC; + SIGNAL wire_nliiO1ili_dataout : STD_LOGIC; + SIGNAL wire_nliiO1ill_dataout : STD_LOGIC; + SIGNAL wire_nliiO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nliiO1iO_dataout : STD_LOGIC; + SIGNAL wire_nliiO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nliiO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nliiO1li_dataout : STD_LOGIC; + SIGNAL wire_nliiO1ll_dataout : STD_LOGIC; + SIGNAL wire_nliiO1lll_dataout : STD_LOGIC; + SIGNAL wire_nliiO1llO_dataout : STD_LOGIC; + SIGNAL wire_nliiO1lO_dataout : STD_LOGIC; + SIGNAL wire_nliiO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nliiO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nliiO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nliiO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nliiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nliiOi0i_dataout : STD_LOGIC; + SIGNAL wire_nliiOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nliiOi0l_dataout : STD_LOGIC; + SIGNAL wire_nliiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nliiOi10i_dataout : STD_LOGIC; + SIGNAL wire_nliiOi10l_dataout : STD_LOGIC; + SIGNAL wire_nliiOi10O_dataout : STD_LOGIC; + SIGNAL wire_nliiOi11O_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1i_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1l_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1li_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1O_dataout : STD_LOGIC; + SIGNAL wire_nliiOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliiOiii_dataout : STD_LOGIC; + SIGNAL wire_nliiOiil_dataout : STD_LOGIC; + SIGNAL wire_nliiOiiO_dataout : STD_LOGIC; + SIGNAL wire_nliiOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nliiOil0l_dataout : STD_LOGIC; + SIGNAL wire_nliiOil0O_dataout : STD_LOGIC; + SIGNAL wire_nliiOili_dataout : STD_LOGIC; + SIGNAL wire_nliiOill_dataout : STD_LOGIC; + SIGNAL wire_nliiOillO_dataout : STD_LOGIC; + SIGNAL wire_nliiOilO_dataout : STD_LOGIC; + SIGNAL wire_nliiOilOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nliiOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nliiOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nliiOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nliiOiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nliiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nliiOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOl01l_dataout : STD_LOGIC; + SIGNAL wire_nliiOl01O_dataout : STD_LOGIC; + SIGNAL wire_nliiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nliiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nliiOl0li_dataout : STD_LOGIC; + SIGNAL wire_nliiOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nliiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nliiOl10i_dataout : STD_LOGIC; + SIGNAL wire_nliiOl10l_dataout : STD_LOGIC; + SIGNAL wire_nliiOl10O_dataout : STD_LOGIC; + SIGNAL wire_nliiOl11O_dataout : STD_LOGIC; + SIGNAL wire_nliiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nliiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nliiOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nliiOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nliiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nliiOli0i_dataout : STD_LOGIC; + SIGNAL wire_nliiOli1O_dataout : STD_LOGIC; + SIGNAL wire_nliiOlii_dataout : STD_LOGIC; + SIGNAL wire_nliiOliii_dataout : STD_LOGIC; + SIGNAL wire_nliiOlil_dataout : STD_LOGIC; + SIGNAL wire_nliiOliO_dataout : STD_LOGIC; + SIGNAL wire_nliiOliOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOliOi_w_lg_w_lg_dataout44320w45270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOliOi_w_lg_w_lg_w_lg_dataout44320w45270w45271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOliOi_w_lg_dataout44320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiOliOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOlli_dataout : STD_LOGIC; + SIGNAL wire_nliiOlll_dataout : STD_LOGIC; + SIGNAL wire_nliiOllO_dataout : STD_LOGIC; + SIGNAL wire_nliiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nliiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nliiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nliiOO0O_dataout : STD_LOGIC; + SIGNAL wire_nliiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nliiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nliiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nliiOOii_dataout : STD_LOGIC; + SIGNAL wire_nliiOOil_dataout : STD_LOGIC; + SIGNAL wire_nliiOOiO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nliiOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nliiOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nliiOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nliiOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nliiOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nliiOOli_dataout : STD_LOGIC; + SIGNAL wire_nliiOOlii_dataout : STD_LOGIC; + SIGNAL wire_nliiOOlil_dataout : STD_LOGIC; + SIGNAL wire_nliiOOliO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOll_dataout : STD_LOGIC; + SIGNAL wire_nliiOOlli_dataout : STD_LOGIC; + SIGNAL wire_nliiOOlll_dataout : STD_LOGIC; + SIGNAL wire_nliiOOllO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nliiOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOli_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOll_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nliiOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0000l_dataout : STD_LOGIC; + SIGNAL wire_nlil0000O_dataout : STD_LOGIC; + SIGNAL wire_nlil000i_dataout : STD_LOGIC; + SIGNAL wire_nlil000l_dataout : STD_LOGIC; + SIGNAL wire_nlil000ll_dataout : STD_LOGIC; + SIGNAL wire_nlil000lO_dataout : STD_LOGIC; + SIGNAL wire_nlil000O_dataout : STD_LOGIC; + SIGNAL wire_nlil0010i_dataout : STD_LOGIC; + SIGNAL wire_nlil0010l_dataout : STD_LOGIC; + SIGNAL wire_nlil0010O_dataout : STD_LOGIC; + SIGNAL wire_nlil0011i_dataout : STD_LOGIC; + SIGNAL wire_nlil0011l_dataout : STD_LOGIC; + SIGNAL wire_nlil0011O_dataout : STD_LOGIC; + SIGNAL wire_nlil001i_dataout : STD_LOGIC; + SIGNAL wire_nlil001ii_dataout : STD_LOGIC; + SIGNAL wire_nlil001il_dataout : STD_LOGIC; + SIGNAL wire_nlil001iO_dataout : STD_LOGIC; + SIGNAL wire_nlil001l_dataout : STD_LOGIC; + SIGNAL wire_nlil001li_dataout : STD_LOGIC; + SIGNAL wire_nlil001ll_dataout : STD_LOGIC; + SIGNAL wire_nlil001lO_dataout : STD_LOGIC; + SIGNAL wire_nlil001O_dataout : STD_LOGIC; + SIGNAL wire_nlil001Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil001Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil001OO_dataout : STD_LOGIC; + SIGNAL wire_nlil00ii_dataout : STD_LOGIC; + SIGNAL wire_nlil00il_dataout : STD_LOGIC; + SIGNAL wire_nlil00iO_dataout : STD_LOGIC; + SIGNAL wire_nlil00iOi_dataout : STD_LOGIC; + SIGNAL wire_nlil00iOl_dataout : STD_LOGIC; + SIGNAL wire_nlil00iOO_dataout : STD_LOGIC; + SIGNAL wire_nlil00l0i_dataout : STD_LOGIC; + SIGNAL wire_nlil00l0l_dataout : STD_LOGIC; + SIGNAL wire_nlil00l0O_dataout : STD_LOGIC; + SIGNAL wire_nlil00l1i_dataout : STD_LOGIC; + SIGNAL wire_nlil00l1l_dataout : STD_LOGIC; + SIGNAL wire_nlil00l1O_dataout : STD_LOGIC; + SIGNAL wire_nlil00li_dataout : STD_LOGIC; + SIGNAL wire_nlil00lii_dataout : STD_LOGIC; + SIGNAL wire_nlil00lil_dataout : STD_LOGIC; + SIGNAL wire_nlil00liO_dataout : STD_LOGIC; + SIGNAL wire_nlil00ll_dataout : STD_LOGIC; + SIGNAL wire_nlil00lli_dataout : STD_LOGIC; + SIGNAL wire_nlil00lll_dataout : STD_LOGIC; + SIGNAL wire_nlil00llO_dataout : STD_LOGIC; + SIGNAL wire_nlil00lO_dataout : STD_LOGIC; + SIGNAL wire_nlil00lOi_dataout : STD_LOGIC; + SIGNAL wire_nlil00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil00OO_dataout : STD_LOGIC; + SIGNAL wire_nlil010i_dataout : STD_LOGIC; + SIGNAL wire_nlil010l_dataout : STD_LOGIC; + SIGNAL wire_nlil010O_dataout : STD_LOGIC; + SIGNAL wire_nlil0110i_dataout : STD_LOGIC; + SIGNAL wire_nlil0110l_dataout : STD_LOGIC; + SIGNAL wire_nlil0110O_dataout : STD_LOGIC; + SIGNAL wire_nlil0111i_dataout : STD_LOGIC; + SIGNAL wire_nlil0111l_dataout : STD_LOGIC; + SIGNAL wire_nlil0111O_dataout : STD_LOGIC; + SIGNAL wire_nlil011i_dataout : STD_LOGIC; + SIGNAL wire_nlil011ii_dataout : STD_LOGIC; + SIGNAL wire_nlil011il_dataout : STD_LOGIC; + SIGNAL wire_nlil011iO_dataout : STD_LOGIC; + SIGNAL wire_nlil011l_dataout : STD_LOGIC; + SIGNAL wire_nlil011O_dataout : STD_LOGIC; + SIGNAL wire_nlil01i0O_dataout : STD_LOGIC; + SIGNAL wire_nlil01ii_dataout : STD_LOGIC; + SIGNAL wire_nlil01iii_dataout : STD_LOGIC; + SIGNAL wire_nlil01iil_dataout : STD_LOGIC; + SIGNAL wire_nlil01iiO_dataout : STD_LOGIC; + SIGNAL wire_nlil01il_dataout : STD_LOGIC; + SIGNAL wire_nlil01ili_dataout : STD_LOGIC; + SIGNAL wire_nlil01ill_dataout : STD_LOGIC; + SIGNAL wire_nlil01ilO_dataout : STD_LOGIC; + SIGNAL wire_nlil01iO_dataout : STD_LOGIC; + SIGNAL wire_nlil01iOi_dataout : STD_LOGIC; + SIGNAL wire_nlil01iOl_dataout : STD_LOGIC; + SIGNAL wire_nlil01iOO_dataout : STD_LOGIC; + SIGNAL wire_nlil01l0i_dataout : STD_LOGIC; + SIGNAL wire_nlil01l0l_dataout : STD_LOGIC; + SIGNAL wire_nlil01l0O_dataout : STD_LOGIC; + SIGNAL wire_nlil01l1i_dataout : STD_LOGIC; + SIGNAL wire_nlil01l1l_dataout : STD_LOGIC; + SIGNAL wire_nlil01l1O_dataout : STD_LOGIC; + SIGNAL wire_nlil01li_dataout : STD_LOGIC; + SIGNAL wire_nlil01lii_dataout : STD_LOGIC; + SIGNAL wire_nlil01lil_dataout : STD_LOGIC; + SIGNAL wire_nlil01liO_dataout : STD_LOGIC; + SIGNAL wire_nlil01ll_dataout : STD_LOGIC; + SIGNAL wire_nlil01lli_dataout : STD_LOGIC; + SIGNAL wire_nlil01lll_dataout : STD_LOGIC; + SIGNAL wire_nlil01llO_dataout : STD_LOGIC; + SIGNAL wire_nlil01lO_dataout : STD_LOGIC; + SIGNAL wire_nlil01lOi_dataout : STD_LOGIC; + SIGNAL wire_nlil01lOl_dataout : STD_LOGIC; + SIGNAL wire_nlil01lOO_dataout : STD_LOGIC; + SIGNAL wire_nlil01O0i_dataout : STD_LOGIC; + SIGNAL wire_nlil01O0l_dataout : STD_LOGIC; + SIGNAL wire_nlil01O0O_dataout : STD_LOGIC; + SIGNAL wire_nlil01O1i_dataout : STD_LOGIC; + SIGNAL wire_nlil01O1l_dataout : STD_LOGIC; + SIGNAL wire_nlil01O1O_dataout : STD_LOGIC; + SIGNAL wire_nlil01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil01Oii_dataout : STD_LOGIC; + SIGNAL wire_nlil01Oil_dataout : STD_LOGIC; + SIGNAL wire_nlil01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil01Oll_dataout : STD_LOGIC; + SIGNAL wire_nlil01OlO_dataout : STD_LOGIC; + SIGNAL wire_nlil01OO_dataout : STD_LOGIC; + SIGNAL wire_nlil01OOi_dataout : STD_LOGIC; + SIGNAL wire_nlil01OOl_dataout : STD_LOGIC; + SIGNAL wire_nlil01OOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0i00i_dataout : STD_LOGIC; + SIGNAL wire_nlil0i00l_dataout : STD_LOGIC; + SIGNAL wire_nlil0i00O_dataout : STD_LOGIC; + SIGNAL wire_nlil0i01i_dataout : STD_LOGIC; + SIGNAL wire_nlil0i01l_dataout : STD_LOGIC; + SIGNAL wire_nlil0i01O_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0il_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0li_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlil0i10i_dataout : STD_LOGIC; + SIGNAL wire_nlil0i10l_dataout : STD_LOGIC; + SIGNAL wire_nlil0i10O_dataout : STD_LOGIC; + SIGNAL wire_nlil0i11l_dataout : STD_LOGIC; + SIGNAL wire_nlil0i11O_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1il_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1li_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlil0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0iii_dataout : STD_LOGIC; + SIGNAL wire_nlil0iiii_dataout : STD_LOGIC; + SIGNAL wire_nlil0iiil_dataout : STD_LOGIC; + SIGNAL wire_nlil0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0iil_dataout : STD_LOGIC; + SIGNAL wire_nlil0iili_dataout : STD_LOGIC; + SIGNAL wire_nlil0iill_dataout : STD_LOGIC; + SIGNAL wire_nlil0iilO_dataout : STD_LOGIC; + SIGNAL wire_nlil0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0il0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0il0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0il0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0il1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0il1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0il1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0ili_dataout : STD_LOGIC; + SIGNAL wire_nlil0ilii_dataout : STD_LOGIC; + SIGNAL wire_nlil0ilil_dataout : STD_LOGIC; + SIGNAL wire_nlil0iliO_dataout : STD_LOGIC; + SIGNAL wire_nlil0ill_dataout : STD_LOGIC; + SIGNAL wire_nlil0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlil0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOii_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOil_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOli_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOll_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0l00i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l00l_dataout : STD_LOGIC; + SIGNAL wire_nlil0l00O_dataout : STD_LOGIC; + SIGNAL wire_nlil0l01i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l01l_dataout : STD_LOGIC; + SIGNAL wire_nlil0l01O_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0li_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlil0l10i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l10l_dataout : STD_LOGIC; + SIGNAL wire_nlil0l10O_dataout : STD_LOGIC; + SIGNAL wire_nlil0l11i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l11l_dataout : STD_LOGIC; + SIGNAL wire_nlil0l11O_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1il_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1li_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlil0li0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0li0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0li0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0li1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0li1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0li1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0lii_dataout : STD_LOGIC; + SIGNAL wire_nlil0liii_dataout : STD_LOGIC; + SIGNAL wire_nlil0liil_dataout : STD_LOGIC; + SIGNAL wire_nlil0liiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0lil_dataout : STD_LOGIC; + SIGNAL wire_nlil0lili_dataout : STD_LOGIC; + SIGNAL wire_nlil0lill_dataout : STD_LOGIC; + SIGNAL wire_nlil0lilO_dataout : STD_LOGIC; + SIGNAL wire_nlil0liO_dataout : STD_LOGIC; + SIGNAL wire_nlil0liOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0liOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0liOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0lli_dataout : STD_LOGIC; + SIGNAL wire_nlil0llii_dataout : STD_LOGIC; + SIGNAL wire_nlil0llil_dataout : STD_LOGIC; + SIGNAL wire_nlil0lliO_dataout : STD_LOGIC; + SIGNAL wire_nlil0lll_dataout : STD_LOGIC; + SIGNAL wire_nlil0llli_dataout : STD_LOGIC; + SIGNAL wire_nlil0llll_dataout : STD_LOGIC; + SIGNAL wire_nlil0lllO_dataout : STD_LOGIC; + SIGNAL wire_nlil0llO_dataout : STD_LOGIC; + SIGNAL wire_nlil0llOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0llOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0llOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOii_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOil_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOli_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOll_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0O00i_dataout : STD_LOGIC; + SIGNAL wire_nlil0O00l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O00O_dataout : STD_LOGIC; + SIGNAL wire_nlil0O01i_dataout : STD_LOGIC; + SIGNAL wire_nlil0O01l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0il_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0li_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlil0O10i_dataout : STD_LOGIC; + SIGNAL wire_nlil0O10l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O10O_dataout : STD_LOGIC; + SIGNAL wire_nlil0O11i_dataout : STD_LOGIC; + SIGNAL wire_nlil0O11l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O11O_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1il_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1li_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlil0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oili_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oill_dataout : STD_LOGIC; + SIGNAL wire_nlil0OilO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlil0Olii_dataout : STD_LOGIC; + SIGNAL wire_nlil0Olil_dataout : STD_LOGIC; + SIGNAL wire_nlil0OliO_dataout : STD_LOGIC; + SIGNAL wire_nlil0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlil0Olli_dataout : STD_LOGIC; + SIGNAL wire_nlil0Olll_dataout : STD_LOGIC; + SIGNAL wire_nlil0OllO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlil0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlil0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlil0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlil0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlil0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOii_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOil_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOli_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOll_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlil0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1000i_dataout : STD_LOGIC; + SIGNAL wire_nlil1000l_dataout : STD_LOGIC; + SIGNAL wire_nlil1000O_dataout : STD_LOGIC; + SIGNAL wire_nlil1001i_dataout : STD_LOGIC; + SIGNAL wire_nlil1001l_dataout : STD_LOGIC; + SIGNAL wire_nlil1001O_dataout : STD_LOGIC; + SIGNAL wire_nlil100i_dataout : STD_LOGIC; + SIGNAL wire_nlil100ii_dataout : STD_LOGIC; + SIGNAL wire_nlil100il_dataout : STD_LOGIC; + SIGNAL wire_nlil100iO_dataout : STD_LOGIC; + SIGNAL wire_nlil100l_dataout : STD_LOGIC; + SIGNAL wire_nlil100li_dataout : STD_LOGIC; + SIGNAL wire_nlil100lO_dataout : STD_LOGIC; + SIGNAL wire_nlil100O_dataout : STD_LOGIC; + SIGNAL wire_nlil100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil100Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil100OO_dataout : STD_LOGIC; + SIGNAL wire_nlil1010i_dataout : STD_LOGIC; + SIGNAL wire_nlil1010l_dataout : STD_LOGIC; + SIGNAL wire_nlil1010O_dataout : STD_LOGIC; + SIGNAL wire_nlil1011i_dataout : STD_LOGIC; + SIGNAL wire_nlil1011l_dataout : STD_LOGIC; + SIGNAL wire_nlil1011O_dataout : STD_LOGIC; + SIGNAL wire_nlil101i_dataout : STD_LOGIC; + SIGNAL wire_nlil101ii_dataout : STD_LOGIC; + SIGNAL wire_nlil101il_dataout : STD_LOGIC; + SIGNAL wire_nlil101iO_dataout : STD_LOGIC; + SIGNAL wire_nlil101l_dataout : STD_LOGIC; + SIGNAL wire_nlil101li_dataout : STD_LOGIC; + SIGNAL wire_nlil101ll_dataout : STD_LOGIC; + SIGNAL wire_nlil101lO_dataout : STD_LOGIC; + SIGNAL wire_nlil101O_dataout : STD_LOGIC; + SIGNAL wire_nlil101Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil101Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil101OO_dataout : STD_LOGIC; + SIGNAL wire_nlil10i0i_dataout : STD_LOGIC; + SIGNAL wire_nlil10i0l_dataout : STD_LOGIC; + SIGNAL wire_nlil10i0O_dataout : STD_LOGIC; + SIGNAL wire_nlil10i1i_dataout : STD_LOGIC; + SIGNAL wire_nlil10i1l_dataout : STD_LOGIC; + SIGNAL wire_nlil10i1O_dataout : STD_LOGIC; + SIGNAL wire_nlil10ii_dataout : STD_LOGIC; + SIGNAL wire_nlil10iii_dataout : STD_LOGIC; + SIGNAL wire_nlil10iil_dataout : STD_LOGIC; + SIGNAL wire_nlil10iiO_dataout : STD_LOGIC; + SIGNAL wire_nlil10il_dataout : STD_LOGIC; + SIGNAL wire_nlil10ili_dataout : STD_LOGIC; + SIGNAL wire_nlil10ill_dataout : STD_LOGIC; + SIGNAL wire_nlil10ilO_dataout : STD_LOGIC; + SIGNAL wire_nlil10iO_dataout : STD_LOGIC; + SIGNAL wire_nlil10iOi_dataout : STD_LOGIC; + SIGNAL wire_nlil10l0i_dataout : STD_LOGIC; + SIGNAL wire_nlil10l0l_dataout : STD_LOGIC; + SIGNAL wire_nlil10l1O_dataout : STD_LOGIC; + SIGNAL wire_nlil10li_dataout : STD_LOGIC; + SIGNAL wire_nlil10lil_dataout : STD_LOGIC; + SIGNAL wire_nlil10liO_dataout : STD_LOGIC; + SIGNAL wire_nlil10ll_dataout : STD_LOGIC; + SIGNAL wire_nlil10lli_dataout : STD_LOGIC; + SIGNAL wire_nlil10lO_dataout : STD_LOGIC; + SIGNAL wire_nlil10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil10OO_dataout : STD_LOGIC; + SIGNAL wire_nlil10OOO_dataout : STD_LOGIC; + SIGNAL wire_nlil10OOO_w_lg_dataout44032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlil110i_dataout : STD_LOGIC; + SIGNAL wire_nlil110il_dataout : STD_LOGIC; + SIGNAL wire_nlil110iO_dataout : STD_LOGIC; + SIGNAL wire_nlil110l_dataout : STD_LOGIC; + SIGNAL wire_nlil110li_dataout : STD_LOGIC; + SIGNAL wire_nlil110ll_dataout : STD_LOGIC; + SIGNAL wire_nlil110lO_dataout : STD_LOGIC; + SIGNAL wire_nlil110O_dataout : STD_LOGIC; + SIGNAL wire_nlil110Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil110Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil110OO_dataout : STD_LOGIC; + SIGNAL wire_nlil1110i_dataout : STD_LOGIC; + SIGNAL wire_nlil1110l_dataout : STD_LOGIC; + SIGNAL wire_nlil1110O_dataout : STD_LOGIC; + SIGNAL wire_nlil1111i_dataout : STD_LOGIC; + SIGNAL wire_nlil1111l_dataout : STD_LOGIC; + SIGNAL wire_nlil1111O_dataout : STD_LOGIC; + SIGNAL wire_nlil111i_dataout : STD_LOGIC; + SIGNAL wire_nlil111ii_dataout : STD_LOGIC; + SIGNAL wire_nlil111iO_dataout : STD_LOGIC; + SIGNAL wire_nlil111l_dataout : STD_LOGIC; + SIGNAL wire_nlil111ll_dataout : STD_LOGIC; + SIGNAL wire_nlil111lO_dataout : STD_LOGIC; + SIGNAL wire_nlil111O_dataout : STD_LOGIC; + SIGNAL wire_nlil111Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil111OO_dataout : STD_LOGIC; + SIGNAL wire_nlil11i0i_dataout : STD_LOGIC; + SIGNAL wire_nlil11i0l_dataout : STD_LOGIC; + SIGNAL wire_nlil11i0O_dataout : STD_LOGIC; + SIGNAL wire_nlil11i1i_dataout : STD_LOGIC; + SIGNAL wire_nlil11i1l_dataout : STD_LOGIC; + SIGNAL wire_nlil11i1O_dataout : STD_LOGIC; + SIGNAL wire_nlil11ii_dataout : STD_LOGIC; + SIGNAL wire_nlil11iii_dataout : STD_LOGIC; + SIGNAL wire_nlil11iil_dataout : STD_LOGIC; + SIGNAL wire_nlil11iiO_dataout : STD_LOGIC; + SIGNAL wire_nlil11il_dataout : STD_LOGIC; + SIGNAL wire_nlil11ili_dataout : STD_LOGIC; + SIGNAL wire_nlil11ill_dataout : STD_LOGIC; + SIGNAL wire_nlil11ilO_dataout : STD_LOGIC; + SIGNAL wire_nlil11iO_dataout : STD_LOGIC; + SIGNAL wire_nlil11iOi_dataout : STD_LOGIC; + SIGNAL wire_nlil11iOl_dataout : STD_LOGIC; + SIGNAL wire_nlil11iOO_dataout : STD_LOGIC; + SIGNAL wire_nlil11l0l_dataout : STD_LOGIC; + SIGNAL wire_nlil11l0O_dataout : STD_LOGIC; + SIGNAL wire_nlil11li_dataout : STD_LOGIC; + SIGNAL wire_nlil11lii_dataout : STD_LOGIC; + SIGNAL wire_nlil11lil_dataout : STD_LOGIC; + SIGNAL wire_nlil11ll_dataout : STD_LOGIC; + SIGNAL wire_nlil11lO_dataout : STD_LOGIC; + SIGNAL wire_nlil11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil11Oli_dataout : STD_LOGIC; + SIGNAL wire_nlil11Oll_dataout : STD_LOGIC; + SIGNAL wire_nlil11OlO_dataout : STD_LOGIC; + SIGNAL wire_nlil11OO_dataout : STD_LOGIC; + SIGNAL wire_nlil11OOi_dataout : STD_LOGIC; + SIGNAL wire_nlil11OOl_dataout : STD_LOGIC; + SIGNAL wire_nlil11OOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1i00O_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0il_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0li_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlil1i10l_dataout : STD_LOGIC; + SIGNAL wire_nlil1i10l_w_lg_dataout44029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlil1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlil1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1iii_dataout : STD_LOGIC; + SIGNAL wire_nlil1iiii_dataout : STD_LOGIC; + SIGNAL wire_nlil1iiil_dataout : STD_LOGIC; + SIGNAL wire_nlil1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlil1iil_dataout : STD_LOGIC; + SIGNAL wire_nlil1iili_dataout : STD_LOGIC; + SIGNAL wire_nlil1iill_dataout : STD_LOGIC; + SIGNAL wire_nlil1iilO_dataout : STD_LOGIC; + SIGNAL wire_nlil1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlil1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1il0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1il0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1il0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1il1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1il1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1il1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1ili_dataout : STD_LOGIC; + SIGNAL wire_nlil1ilii_dataout : STD_LOGIC; + SIGNAL wire_nlil1ilil_dataout : STD_LOGIC; + SIGNAL wire_nlil1iliO_dataout : STD_LOGIC; + SIGNAL wire_nlil1ill_dataout : STD_LOGIC; + SIGNAL wire_nlil1illi_dataout : STD_LOGIC; + SIGNAL wire_nlil1illl_dataout : STD_LOGIC; + SIGNAL wire_nlil1illO_dataout : STD_LOGIC; + SIGNAL wire_nlil1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlil1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOll_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1l00i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l00l_dataout : STD_LOGIC; + SIGNAL wire_nlil1l00O_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0il_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0li_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlil1l10i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l10l_dataout : STD_LOGIC; + SIGNAL wire_nlil1l10O_dataout : STD_LOGIC; + SIGNAL wire_nlil1l11i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l11l_dataout : STD_LOGIC; + SIGNAL wire_nlil1l11O_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1il_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1li_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlil1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1li0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1li0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1li0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1li1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1li1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1li1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1lii_dataout : STD_LOGIC; + SIGNAL wire_nlil1lil_dataout : STD_LOGIC; + SIGNAL wire_nlil1lilO_dataout : STD_LOGIC; + SIGNAL wire_nlil1liO_dataout : STD_LOGIC; + SIGNAL wire_nlil1liOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1liOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1liOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1lli_dataout : STD_LOGIC; + SIGNAL wire_nlil1llii_dataout : STD_LOGIC; + SIGNAL wire_nlil1llil_dataout : STD_LOGIC; + SIGNAL wire_nlil1lliO_dataout : STD_LOGIC; + SIGNAL wire_nlil1lll_dataout : STD_LOGIC; + SIGNAL wire_nlil1llli_dataout : STD_LOGIC; + SIGNAL wire_nlil1llO_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOll_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1O00i_dataout : STD_LOGIC; + SIGNAL wire_nlil1O00l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O00O_dataout : STD_LOGIC; + SIGNAL wire_nlil1O01l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O01O_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0il_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0li_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlil1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlil1O10i_dataout : STD_LOGIC; + SIGNAL wire_nlil1O10l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O10O_dataout : STD_LOGIC; + SIGNAL wire_nlil1O11i_dataout : STD_LOGIC; + SIGNAL wire_nlil1O11l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O11O_dataout : STD_LOGIC; + SIGNAL wire_nlil1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlil1O1il_dataout : STD_LOGIC; + SIGNAL wire_nlil1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlil1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oili_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oill_dataout : STD_LOGIC; + SIGNAL wire_nlil1OilO_dataout : STD_LOGIC; + SIGNAL wire_nlil1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlil1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlil1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlil1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlil1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlil1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlil1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlil1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlil1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlil1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlil1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlil1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlili000i_dataout : STD_LOGIC; + SIGNAL wire_nlili000l_dataout : STD_LOGIC; + SIGNAL wire_nlili000O_dataout : STD_LOGIC; + SIGNAL wire_nlili001i_dataout : STD_LOGIC; + SIGNAL wire_nlili001l_dataout : STD_LOGIC; + SIGNAL wire_nlili001O_dataout : STD_LOGIC; + SIGNAL wire_nlili00i_dataout : STD_LOGIC; + SIGNAL wire_nlili00ii_dataout : STD_LOGIC; + SIGNAL wire_nlili00l_dataout : STD_LOGIC; + SIGNAL wire_nlili00lO_dataout : STD_LOGIC; + SIGNAL wire_nlili00O_dataout : STD_LOGIC; + SIGNAL wire_nlili00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlili00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlili00OO_dataout : STD_LOGIC; + SIGNAL wire_nlili010i_dataout : STD_LOGIC; + SIGNAL wire_nlili010l_dataout : STD_LOGIC; + SIGNAL wire_nlili010O_dataout : STD_LOGIC; + SIGNAL wire_nlili011i_dataout : STD_LOGIC; + SIGNAL wire_nlili011l_dataout : STD_LOGIC; + SIGNAL wire_nlili011O_dataout : STD_LOGIC; + SIGNAL wire_nlili01i_dataout : STD_LOGIC; + SIGNAL wire_nlili01ii_dataout : STD_LOGIC; + SIGNAL wire_nlili01il_dataout : STD_LOGIC; + SIGNAL wire_nlili01iO_dataout : STD_LOGIC; + SIGNAL wire_nlili01l_dataout : STD_LOGIC; + SIGNAL wire_nlili01li_dataout : STD_LOGIC; + SIGNAL wire_nlili01ll_dataout : STD_LOGIC; + SIGNAL wire_nlili01lO_dataout : STD_LOGIC; + SIGNAL wire_nlili01O_dataout : STD_LOGIC; + SIGNAL wire_nlili01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlili01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlili01OO_dataout : STD_LOGIC; + SIGNAL wire_nlili0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlili0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlili0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlili0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlili0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlili0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlili0ii_dataout : STD_LOGIC; + SIGNAL wire_nlili0iii_dataout : STD_LOGIC; + SIGNAL wire_nlili0iil_dataout : STD_LOGIC; + SIGNAL wire_nlili0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlili0il_dataout : STD_LOGIC; + SIGNAL wire_nlili0ili_dataout : STD_LOGIC; + SIGNAL wire_nlili0ill_dataout : STD_LOGIC; + SIGNAL wire_nlili0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlili0iO_dataout : STD_LOGIC; + SIGNAL wire_nlili0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlili0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlili0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlili0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlili0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlili0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlili0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlili0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlili0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlili0li_dataout : STD_LOGIC; + SIGNAL wire_nlili0lii_dataout : STD_LOGIC; + SIGNAL wire_nlili0lil_dataout : STD_LOGIC; + SIGNAL wire_nlili0liO_dataout : STD_LOGIC; + SIGNAL wire_nlili0ll_dataout : STD_LOGIC; + SIGNAL wire_nlili0lli_dataout : STD_LOGIC; + SIGNAL wire_nlili0lll_dataout : STD_LOGIC; + SIGNAL wire_nlili0llO_dataout : STD_LOGIC; + SIGNAL wire_nlili0lO_dataout : STD_LOGIC; + SIGNAL wire_nlili0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlili0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlili0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlili0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlili0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlili0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlili0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlili0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlili0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlili0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlili0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlili0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlili0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlili0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlili0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlili0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlili0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlili0OO_dataout : STD_LOGIC; + SIGNAL wire_nlili0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlili0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlili0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlili100i_dataout : STD_LOGIC; + SIGNAL wire_nlili100l_dataout : STD_LOGIC; + SIGNAL wire_nlili100O_dataout : STD_LOGIC; + SIGNAL wire_nlili101i_dataout : STD_LOGIC; + SIGNAL wire_nlili101l_dataout : STD_LOGIC; + SIGNAL wire_nlili101O_dataout : STD_LOGIC; + SIGNAL wire_nlili10i_dataout : STD_LOGIC; + SIGNAL wire_nlili10ii_dataout : STD_LOGIC; + SIGNAL wire_nlili10il_dataout : STD_LOGIC; + SIGNAL wire_nlili10iO_dataout : STD_LOGIC; + SIGNAL wire_nlili10l_dataout : STD_LOGIC; + SIGNAL wire_nlili10li_dataout : STD_LOGIC; + SIGNAL wire_nlili10ll_dataout : STD_LOGIC; + SIGNAL wire_nlili10lO_dataout : STD_LOGIC; + SIGNAL wire_nlili10O_dataout : STD_LOGIC; + SIGNAL wire_nlili10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlili10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlili10OO_dataout : STD_LOGIC; + SIGNAL wire_nlili110i_dataout : STD_LOGIC; + SIGNAL wire_nlili110l_dataout : STD_LOGIC; + SIGNAL wire_nlili110O_dataout : STD_LOGIC; + SIGNAL wire_nlili11i_dataout : STD_LOGIC; + SIGNAL wire_nlili11ii_dataout : STD_LOGIC; + SIGNAL wire_nlili11il_dataout : STD_LOGIC; + SIGNAL wire_nlili11iO_dataout : STD_LOGIC; + SIGNAL wire_nlili11l_dataout : STD_LOGIC; + SIGNAL wire_nlili11li_dataout : STD_LOGIC; + SIGNAL wire_nlili11ll_dataout : STD_LOGIC; + SIGNAL wire_nlili11lO_dataout : STD_LOGIC; + SIGNAL wire_nlili11O_dataout : STD_LOGIC; + SIGNAL wire_nlili11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlili11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlili11OO_dataout : STD_LOGIC; + SIGNAL wire_nlili1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlili1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlili1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlili1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlili1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlili1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlili1ii_dataout : STD_LOGIC; + SIGNAL wire_nlili1iii_dataout : STD_LOGIC; + SIGNAL wire_nlili1iil_dataout : STD_LOGIC; + SIGNAL wire_nlili1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlili1il_dataout : STD_LOGIC; + SIGNAL wire_nlili1ili_dataout : STD_LOGIC; + SIGNAL wire_nlili1ill_dataout : STD_LOGIC; + SIGNAL wire_nlili1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlili1iO_dataout : STD_LOGIC; + SIGNAL wire_nlili1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlili1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlili1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlili1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlili1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlili1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlili1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlili1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlili1li_dataout : STD_LOGIC; + SIGNAL wire_nlili1lii_dataout : STD_LOGIC; + SIGNAL wire_nlili1lil_dataout : STD_LOGIC; + SIGNAL wire_nlili1liO_dataout : STD_LOGIC; + SIGNAL wire_nlili1ll_dataout : STD_LOGIC; + SIGNAL wire_nlili1lli_dataout : STD_LOGIC; + SIGNAL wire_nlili1lll_dataout : STD_LOGIC; + SIGNAL wire_nlili1llO_dataout : STD_LOGIC; + SIGNAL wire_nlili1lO_dataout : STD_LOGIC; + SIGNAL wire_nlili1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlili1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlili1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlili1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlili1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlili1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlili1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlili1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlili1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlili1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlili1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlili1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlili1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlili1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlili1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlili1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlili1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlili1OO_dataout : STD_LOGIC; + SIGNAL wire_nlili1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlili1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlili1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlilii00i_dataout : STD_LOGIC; + SIGNAL wire_nlilii00l_dataout : STD_LOGIC; + SIGNAL wire_nlilii00O_dataout : STD_LOGIC; + SIGNAL wire_nlilii01i_dataout : STD_LOGIC; + SIGNAL wire_nlilii01l_dataout : STD_LOGIC; + SIGNAL wire_nlilii01O_dataout : STD_LOGIC; + SIGNAL wire_nlilii0i_dataout : STD_LOGIC; + SIGNAL wire_nlilii0ii_dataout : STD_LOGIC; + SIGNAL wire_nlilii0il_dataout : STD_LOGIC; + SIGNAL wire_nlilii0iO_dataout : STD_LOGIC; + SIGNAL wire_nlilii0l_dataout : STD_LOGIC; + SIGNAL wire_nlilii0li_dataout : STD_LOGIC; + SIGNAL wire_nlilii0ll_dataout : STD_LOGIC; + SIGNAL wire_nlilii0lO_dataout : STD_LOGIC; + SIGNAL wire_nlilii0O_dataout : STD_LOGIC; + SIGNAL wire_nlilii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilii0OO_dataout : STD_LOGIC; + SIGNAL wire_nlilii10i_dataout : STD_LOGIC; + SIGNAL wire_nlilii10l_dataout : STD_LOGIC; + SIGNAL wire_nlilii10O_dataout : STD_LOGIC; + SIGNAL wire_nlilii11i_dataout : STD_LOGIC; + SIGNAL wire_nlilii11l_dataout : STD_LOGIC; + SIGNAL wire_nlilii11O_dataout : STD_LOGIC; + SIGNAL wire_nlilii1i_dataout : STD_LOGIC; + SIGNAL wire_nlilii1ii_dataout : STD_LOGIC; + SIGNAL wire_nlilii1il_dataout : STD_LOGIC; + SIGNAL wire_nlilii1iO_dataout : STD_LOGIC; + SIGNAL wire_nlilii1l_dataout : STD_LOGIC; + SIGNAL wire_nlilii1li_dataout : STD_LOGIC; + SIGNAL wire_nlilii1ll_dataout : STD_LOGIC; + SIGNAL wire_nlilii1lO_dataout : STD_LOGIC; + SIGNAL wire_nlilii1O_dataout : STD_LOGIC; + SIGNAL wire_nlilii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilii1OO_dataout : STD_LOGIC; + SIGNAL wire_nliliii0i_dataout : STD_LOGIC; + SIGNAL wire_nliliii1i_dataout : STD_LOGIC; + SIGNAL wire_nliliii1l_dataout : STD_LOGIC; + SIGNAL wire_nliliii1O_dataout : STD_LOGIC; + SIGNAL wire_nliliiii_dataout : STD_LOGIC; + SIGNAL wire_nliliiil_dataout : STD_LOGIC; + SIGNAL wire_nliliiiO_dataout : STD_LOGIC; + SIGNAL wire_nliliili_dataout : STD_LOGIC; + SIGNAL wire_nliliill_dataout : STD_LOGIC; + SIGNAL wire_nliliilll_dataout : STD_LOGIC; + SIGNAL wire_nliliilO_dataout : STD_LOGIC; + SIGNAL wire_nliliilOi_dataout : STD_LOGIC; + SIGNAL wire_nliliilOi_w_lg_dataout43982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliilOl_dataout : STD_LOGIC; + SIGNAL wire_nliliilOl_w_lg_dataout43980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliilOO_dataout : STD_LOGIC; + SIGNAL wire_nliliilOO_w_lg_dataout48202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliiO0i_dataout : STD_LOGIC; + SIGNAL wire_nliliiO0l_dataout : STD_LOGIC; + SIGNAL wire_nliliiO0O_dataout : STD_LOGIC; + SIGNAL wire_nliliiO1i_dataout : STD_LOGIC; + SIGNAL wire_nliliiO1i_w48213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliiO1i_w_lg_w_lg_w_lg_dataout48201w48203w48212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliiO1i_w_lg_w_lg_w_lg_dataout48201w48203w48204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliiO1i_w_lg_w_lg_dataout48201w48203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliiO1i_w_lg_dataout48219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliiO1i_w_lg_dataout48201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliiO1l_dataout : STD_LOGIC; + SIGNAL wire_nliliiO1O_dataout : STD_LOGIC; + SIGNAL wire_nliliiOi_dataout : STD_LOGIC; + SIGNAL wire_nliliiOii_dataout : STD_LOGIC; + SIGNAL wire_nliliiOil_dataout : STD_LOGIC; + SIGNAL wire_nliliiOiO_dataout : STD_LOGIC; + SIGNAL wire_nliliiOl_dataout : STD_LOGIC; + SIGNAL wire_nliliiOli_dataout : STD_LOGIC; + SIGNAL wire_nliliiOll_dataout : STD_LOGIC; + SIGNAL wire_nliliiOlO_dataout : STD_LOGIC; + SIGNAL wire_nliliiOO_dataout : STD_LOGIC; + SIGNAL wire_nliliiOOi_dataout : STD_LOGIC; + SIGNAL wire_nliliiOOl_dataout : STD_LOGIC; + SIGNAL wire_nliliiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlilil00i_dataout : STD_LOGIC; + SIGNAL wire_nlilil00l_dataout : STD_LOGIC; + SIGNAL wire_nlilil00O_dataout : STD_LOGIC; + SIGNAL wire_nlilil01i_dataout : STD_LOGIC; + SIGNAL wire_nlilil01l_dataout : STD_LOGIC; + SIGNAL wire_nlilil01O_dataout : STD_LOGIC; + SIGNAL wire_nlilil0i_dataout : STD_LOGIC; + SIGNAL wire_nlilil0ii_dataout : STD_LOGIC; + SIGNAL wire_nlilil0il_dataout : STD_LOGIC; + SIGNAL wire_nlilil0l_dataout : STD_LOGIC; + SIGNAL wire_nlilil0O_dataout : STD_LOGIC; + SIGNAL wire_nlilil10i_dataout : STD_LOGIC; + SIGNAL wire_nlilil10l_dataout : STD_LOGIC; + SIGNAL wire_nlilil10O_dataout : STD_LOGIC; + SIGNAL wire_nlilil11i_dataout : STD_LOGIC; + SIGNAL wire_nlilil11l_dataout : STD_LOGIC; + SIGNAL wire_nlilil11O_dataout : STD_LOGIC; + SIGNAL wire_nlilil1i_dataout : STD_LOGIC; + SIGNAL wire_nlilil1ii_dataout : STD_LOGIC; + SIGNAL wire_nlilil1il_dataout : STD_LOGIC; + SIGNAL wire_nlilil1iO_dataout : STD_LOGIC; + SIGNAL wire_nlilil1l_dataout : STD_LOGIC; + SIGNAL wire_nlilil1li_dataout : STD_LOGIC; + SIGNAL wire_nlilil1ll_dataout : STD_LOGIC; + SIGNAL wire_nlilil1lO_dataout : STD_LOGIC; + SIGNAL wire_nlilil1O_dataout : STD_LOGIC; + SIGNAL wire_nlilil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilil1OO_dataout : STD_LOGIC; + SIGNAL wire_nlililii_dataout : STD_LOGIC; + SIGNAL wire_nlililil_dataout : STD_LOGIC; + SIGNAL wire_nlililiO_dataout : STD_LOGIC; + SIGNAL wire_nlilill0i_dataout : STD_LOGIC; + SIGNAL wire_nlilill0l_dataout : STD_LOGIC; + SIGNAL wire_nlilill0O_dataout : STD_LOGIC; + SIGNAL wire_nlililli_dataout : STD_LOGIC; + SIGNAL wire_nlilillii_dataout : STD_LOGIC; + SIGNAL wire_nlililll_dataout : STD_LOGIC; + SIGNAL wire_nlilillli_dataout : STD_LOGIC; + SIGNAL wire_nlilillll_dataout : STD_LOGIC; + SIGNAL wire_nlililllO_dataout : STD_LOGIC; + SIGNAL wire_nlilillO_dataout : STD_LOGIC; + SIGNAL wire_nlilillOi_dataout : STD_LOGIC; + SIGNAL wire_nlilillOl_dataout : STD_LOGIC; + SIGNAL wire_nlilillOO_dataout : STD_LOGIC; + SIGNAL wire_nlililO1i_dataout : STD_LOGIC; + SIGNAL wire_nlililOi_dataout : STD_LOGIC; + SIGNAL wire_nlililOl_dataout : STD_LOGIC; + SIGNAL wire_nlililOll_dataout : STD_LOGIC; + SIGNAL wire_nlililOlO_dataout : STD_LOGIC; + SIGNAL wire_nlililOO_dataout : STD_LOGIC; + SIGNAL wire_nlililOOi_dataout : STD_LOGIC; + SIGNAL wire_nlililOOl_dataout : STD_LOGIC; + SIGNAL wire_nlililOOl_w_lg_dataout43903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliO00i_dataout : STD_LOGIC; + SIGNAL wire_nliliO00l_dataout : STD_LOGIC; + SIGNAL wire_nliliO00O_dataout : STD_LOGIC; + SIGNAL wire_nliliO01i_dataout : STD_LOGIC; + SIGNAL wire_nliliO01l_dataout : STD_LOGIC; + SIGNAL wire_nliliO01O_dataout : STD_LOGIC; + SIGNAL wire_nliliO0i_dataout : STD_LOGIC; + SIGNAL wire_nliliO0ii_dataout : STD_LOGIC; + SIGNAL wire_nliliO0il_dataout : STD_LOGIC; + SIGNAL wire_nliliO0iO_dataout : STD_LOGIC; + SIGNAL wire_nliliO0l_dataout : STD_LOGIC; + SIGNAL wire_nliliO0li_dataout : STD_LOGIC; + SIGNAL wire_nliliO0ll_dataout : STD_LOGIC; + SIGNAL wire_nliliO0lO_dataout : STD_LOGIC; + SIGNAL wire_nliliO0O_dataout : STD_LOGIC; + SIGNAL wire_nliliO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliliO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliliO0OO_dataout : STD_LOGIC; + SIGNAL wire_nliliO1i_dataout : STD_LOGIC; + SIGNAL wire_nliliO1l_dataout : STD_LOGIC; + SIGNAL wire_nliliO1ll_dataout : STD_LOGIC; + SIGNAL wire_nliliO1lO_dataout : STD_LOGIC; + SIGNAL wire_nliliO1O_dataout : STD_LOGIC; + SIGNAL wire_nliliO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliliO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliliO1OO_dataout : STD_LOGIC; + SIGNAL wire_nliliOi0i_dataout : STD_LOGIC; + SIGNAL wire_nliliOi0l_dataout : STD_LOGIC; + SIGNAL wire_nliliOi0O_dataout : STD_LOGIC; + SIGNAL wire_nliliOi1i_dataout : STD_LOGIC; + SIGNAL wire_nliliOi1l_dataout : STD_LOGIC; + SIGNAL wire_nliliOi1O_dataout : STD_LOGIC; + SIGNAL wire_nliliOii_dataout : STD_LOGIC; + SIGNAL wire_nliliOiii_dataout : STD_LOGIC; + SIGNAL wire_nliliOiiO_dataout : STD_LOGIC; + SIGNAL wire_nliliOil_dataout : STD_LOGIC; + SIGNAL wire_nliliOili_dataout : STD_LOGIC; + SIGNAL wire_nliliOill_dataout : STD_LOGIC; + SIGNAL wire_nliliOilO_dataout : STD_LOGIC; + SIGNAL wire_nliliOiO_dataout : STD_LOGIC; + SIGNAL wire_nliliOiOi_dataout : STD_LOGIC; + SIGNAL wire_nliliOiOl_dataout : STD_LOGIC; + SIGNAL wire_nliliOiOO_dataout : STD_LOGIC; + SIGNAL wire_nliliOl0i_dataout : STD_LOGIC; + SIGNAL wire_nliliOl0l_dataout : STD_LOGIC; + SIGNAL wire_nliliOl0O_dataout : STD_LOGIC; + SIGNAL wire_nliliOl1i_dataout : STD_LOGIC; + SIGNAL wire_nliliOl1l_dataout : STD_LOGIC; + SIGNAL wire_nliliOl1O_dataout : STD_LOGIC; + SIGNAL wire_nliliOli_dataout : STD_LOGIC; + SIGNAL wire_nliliOlii_dataout : STD_LOGIC; + SIGNAL wire_nliliOlil_dataout : STD_LOGIC; + SIGNAL wire_nliliOliO_dataout : STD_LOGIC; + SIGNAL wire_nliliOll_dataout : STD_LOGIC; + SIGNAL wire_nliliOlO_dataout : STD_LOGIC; + SIGNAL wire_nliliOlOi_dataout : STD_LOGIC; + SIGNAL wire_nliliOlOl_dataout : STD_LOGIC; + SIGNAL wire_nliliOlOO_dataout : STD_LOGIC; + SIGNAL wire_nliliOO0i_dataout : STD_LOGIC; + SIGNAL wire_nliliOO0i_w_lg_dataout43231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliliOO1i_dataout : STD_LOGIC; + SIGNAL wire_nliliOO1l_dataout : STD_LOGIC; + SIGNAL wire_nliliOO1O_dataout : STD_LOGIC; + SIGNAL wire_nliliOOi_dataout : STD_LOGIC; + SIGNAL wire_nliliOOil_dataout : STD_LOGIC; + SIGNAL wire_nliliOOiO_dataout : STD_LOGIC; + SIGNAL wire_nliliOOl_dataout : STD_LOGIC; + SIGNAL wire_nliliOOli_dataout : STD_LOGIC; + SIGNAL wire_nliliOOll_dataout : STD_LOGIC; + SIGNAL wire_nliliOOlO_dataout : STD_LOGIC; + SIGNAL wire_nliliOOO_dataout : STD_LOGIC; + SIGNAL wire_nliliOOOi_dataout : STD_LOGIC; + SIGNAL wire_nliliOOOl_dataout : STD_LOGIC; + SIGNAL wire_nliliOOOl_w_lg_dataout43190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill00i_dataout : STD_LOGIC; + SIGNAL wire_nlill00l_dataout : STD_LOGIC; + SIGNAL wire_nlill00O_dataout : STD_LOGIC; + SIGNAL wire_nlill00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlill011i_dataout : STD_LOGIC; + SIGNAL wire_nlill011l_dataout : STD_LOGIC; + SIGNAL wire_nlill01i_dataout : STD_LOGIC; + SIGNAL wire_nlill01il_dataout : STD_LOGIC; + SIGNAL wire_nlill01iO_dataout : STD_LOGIC; + SIGNAL wire_nlill01l_dataout : STD_LOGIC; + SIGNAL wire_nlill01O_dataout : STD_LOGIC; + SIGNAL wire_nlill0ii_dataout : STD_LOGIC; + SIGNAL wire_nlill0il_dataout : STD_LOGIC; + SIGNAL wire_nlill0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlill0iO_dataout : STD_LOGIC; + SIGNAL wire_nlill0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlill0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlill0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlill0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlill0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlill0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlill0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlill0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlill0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlill0li_dataout : STD_LOGIC; + SIGNAL wire_nlill0lii_dataout : STD_LOGIC; + SIGNAL wire_nlill0lil_dataout : STD_LOGIC; + SIGNAL wire_nlill0liO_dataout : STD_LOGIC; + SIGNAL wire_nlill0ll_dataout : STD_LOGIC; + SIGNAL wire_nlill0lli_dataout : STD_LOGIC; + SIGNAL wire_nlill0llO_dataout : STD_LOGIC; + SIGNAL wire_nlill0llO_w_lg_dataout59397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0lO_dataout : STD_LOGIC; + SIGNAL wire_nlill0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlill0lOi_w_lg_dataout59395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlill0lOl_w_lg_dataout59394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlill0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlill0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlill0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlill0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlill0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlill0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlill0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlill0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlill0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlill0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlill0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlill0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlill0OO_dataout : STD_LOGIC; + SIGNAL wire_nlill0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlill0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlill100i_dataout : STD_LOGIC; + SIGNAL wire_nlill100i_w_lg_dataout43113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill101i_dataout : STD_LOGIC; + SIGNAL wire_nlill101l_dataout : STD_LOGIC; + SIGNAL wire_nlill101O_dataout : STD_LOGIC; + SIGNAL wire_nlill10i_dataout : STD_LOGIC; + SIGNAL wire_nlill10il_dataout : STD_LOGIC; + SIGNAL wire_nlill10iO_dataout : STD_LOGIC; + SIGNAL wire_nlill10l_dataout : STD_LOGIC; + SIGNAL wire_nlill10li_dataout : STD_LOGIC; + SIGNAL wire_nlill10ll_dataout : STD_LOGIC; + SIGNAL wire_nlill10lO_dataout : STD_LOGIC; + SIGNAL wire_nlill10O_dataout : STD_LOGIC; + SIGNAL wire_nlill10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlill10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlill10Ol_w_lg_dataout43082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill110i_dataout : STD_LOGIC; + SIGNAL wire_nlill110l_dataout : STD_LOGIC; + SIGNAL wire_nlill110O_dataout : STD_LOGIC; + SIGNAL wire_nlill111O_dataout : STD_LOGIC; + SIGNAL wire_nlill11i_dataout : STD_LOGIC; + SIGNAL wire_nlill11ii_dataout : STD_LOGIC; + SIGNAL wire_nlill11il_dataout : STD_LOGIC; + SIGNAL wire_nlill11iO_dataout : STD_LOGIC; + SIGNAL wire_nlill11iO_w_lg_dataout43154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill11l_dataout : STD_LOGIC; + SIGNAL wire_nlill11O_dataout : STD_LOGIC; + SIGNAL wire_nlill11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlill11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlill11OO_dataout : STD_LOGIC; + SIGNAL wire_nlill1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlill1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlill1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlill1ii_dataout : STD_LOGIC; + SIGNAL wire_nlill1iii_dataout : STD_LOGIC; + SIGNAL wire_nlill1iil_dataout : STD_LOGIC; + SIGNAL wire_nlill1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlill1il_dataout : STD_LOGIC; + SIGNAL wire_nlill1ili_dataout : STD_LOGIC; + SIGNAL wire_nlill1ili_w_lg_dataout43041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill1iO_dataout : STD_LOGIC; + SIGNAL wire_nlill1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlill1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlill1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlill1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlill1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlill1l1l_w_lg_dataout43005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlill1li_dataout : STD_LOGIC; + SIGNAL wire_nlill1ll_dataout : STD_LOGIC; + SIGNAL wire_nlill1lll_dataout : STD_LOGIC; + SIGNAL wire_nlill1llO_dataout : STD_LOGIC; + SIGNAL wire_nlill1lO_dataout : STD_LOGIC; + SIGNAL wire_nlill1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlill1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlill1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlill1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlill1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlill1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlill1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlill1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlill1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlill1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlill1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlill1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlill1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlill1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlill1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlill1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlill1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlill1OO_dataout : STD_LOGIC; + SIGNAL wire_nlill1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlill1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlill1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlilli0i_dataout : STD_LOGIC; + SIGNAL wire_nlilli0l_dataout : STD_LOGIC; + SIGNAL wire_nlilli0O_dataout : STD_LOGIC; + SIGNAL wire_nlilli1i_dataout : STD_LOGIC; + SIGNAL wire_nlilli1l_dataout : STD_LOGIC; + SIGNAL wire_nlilli1O_dataout : STD_LOGIC; + SIGNAL wire_nlilliii_dataout : STD_LOGIC; + SIGNAL wire_nlilliil_dataout : STD_LOGIC; + SIGNAL wire_nlilliiO_dataout : STD_LOGIC; + SIGNAL wire_nlillil0i_dataout : STD_LOGIC; + SIGNAL wire_nlillil0l_dataout : STD_LOGIC; + SIGNAL wire_nlillil0O_dataout : STD_LOGIC; + SIGNAL wire_nlillili_dataout : STD_LOGIC; + SIGNAL wire_nlillilii_dataout : STD_LOGIC; + SIGNAL wire_nlillilil_dataout : STD_LOGIC; + SIGNAL wire_nlilliliO_dataout : STD_LOGIC; + SIGNAL wire_nlillill_dataout : STD_LOGIC; + SIGNAL wire_nlillilli_dataout : STD_LOGIC; + SIGNAL wire_nlillilll_dataout : STD_LOGIC; + SIGNAL wire_nlillillO_dataout : STD_LOGIC; + SIGNAL wire_nlillilO_dataout : STD_LOGIC; + SIGNAL wire_nlillilOi_dataout : STD_LOGIC; + SIGNAL wire_nlillilOl_dataout : STD_LOGIC; + SIGNAL wire_nlillilOO_dataout : STD_LOGIC; + SIGNAL wire_nlilliO0i_dataout : STD_LOGIC; + SIGNAL wire_nlilliO0l_dataout : STD_LOGIC; + SIGNAL wire_nlilliO0O_dataout : STD_LOGIC; + SIGNAL wire_nlilliO1i_dataout : STD_LOGIC; + SIGNAL wire_nlilliO1l_dataout : STD_LOGIC; + SIGNAL wire_nlilliO1O_dataout : STD_LOGIC; + SIGNAL wire_nlilliOi_dataout : STD_LOGIC; + SIGNAL wire_nlilliOii_dataout : STD_LOGIC; + SIGNAL wire_nlilliOil_dataout : STD_LOGIC; + SIGNAL wire_nlilliOiO_dataout : STD_LOGIC; + SIGNAL wire_nlilliOl_dataout : STD_LOGIC; + SIGNAL wire_nlilliOli_dataout : STD_LOGIC; + SIGNAL wire_nlilliOO_dataout : STD_LOGIC; + SIGNAL wire_nlilliOOi_dataout : STD_LOGIC; + SIGNAL wire_nlilliOOl_dataout : STD_LOGIC; + SIGNAL wire_nlilll00i_dataout : STD_LOGIC; + SIGNAL wire_nlilll00l_dataout : STD_LOGIC; + SIGNAL wire_nlilll01i_dataout : STD_LOGIC; + SIGNAL wire_nlilll0i_dataout : STD_LOGIC; + SIGNAL wire_nlilll0ii_dataout : STD_LOGIC; + SIGNAL wire_nlilll0il_dataout : STD_LOGIC; + SIGNAL wire_nlilll0l_dataout : STD_LOGIC; + SIGNAL wire_nlilll0ll_dataout : STD_LOGIC; + SIGNAL wire_nlilll0lO_dataout : STD_LOGIC; + SIGNAL wire_nlilll0O_dataout : STD_LOGIC; + SIGNAL wire_nlilll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilll0OO_dataout : STD_LOGIC; + SIGNAL wire_nlilll10l_dataout : STD_LOGIC; + SIGNAL wire_nlilll10O_dataout : STD_LOGIC; + SIGNAL wire_nlilll11i_dataout : STD_LOGIC; + SIGNAL wire_nlilll11l_dataout : STD_LOGIC; + SIGNAL wire_nlilll1i_dataout : STD_LOGIC; + SIGNAL wire_nlilll1il_dataout : STD_LOGIC; + SIGNAL wire_nlilll1iO_dataout : STD_LOGIC; + SIGNAL wire_nlilll1l_dataout : STD_LOGIC; + SIGNAL wire_nlilll1lO_dataout : STD_LOGIC; + SIGNAL wire_nlilll1O_dataout : STD_LOGIC; + SIGNAL wire_nlilll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlillli0i_dataout : STD_LOGIC; + SIGNAL wire_nlillli0O_dataout : STD_LOGIC; + SIGNAL wire_nlillli1O_dataout : STD_LOGIC; + SIGNAL wire_nlilllii_dataout : STD_LOGIC; + SIGNAL wire_nlillliii_dataout : STD_LOGIC; + SIGNAL wire_nlilllil_dataout : STD_LOGIC; + SIGNAL wire_nlilllili_dataout : STD_LOGIC; + SIGNAL wire_nlilllill_dataout : STD_LOGIC; + SIGNAL wire_nlillliO_dataout : STD_LOGIC; + SIGNAL wire_nlillliOi_dataout : STD_LOGIC; + SIGNAL wire_nlillliOl_dataout : STD_LOGIC; + SIGNAL wire_nlillll0l_dataout : STD_LOGIC; + SIGNAL wire_nlillll0O_dataout : STD_LOGIC; + SIGNAL wire_nlillll1l_dataout : STD_LOGIC; + SIGNAL wire_nlillll1O_dataout : STD_LOGIC; + SIGNAL wire_nlillllii_dataout : STD_LOGIC; + SIGNAL wire_nlilllO1i_dataout : STD_LOGIC; + SIGNAL wire_nlilllO1l_dataout : STD_LOGIC; + SIGNAL wire_nlilllOli_dataout : STD_LOGIC; + SIGNAL wire_nlilllOll_dataout : STD_LOGIC; + SIGNAL wire_nlilllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlillO11i_dataout : STD_LOGIC; + SIGNAL wire_nlillO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlillO1iO_w_lg_dataout29688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlillOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlillOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlillOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlillOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlillOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlillOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlillOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlillOOii_dataout : STD_LOGIC; + SIGNAL wire_nlillOOil_dataout : STD_LOGIC; + SIGNAL wire_nlillOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlillOOl_dataout : STD_LOGIC; + SIGNAL wire_nlillOOli_dataout : STD_LOGIC; + SIGNAL wire_nlillOOll_dataout : STD_LOGIC; + SIGNAL wire_nlillOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlillOOO_dataout : STD_LOGIC; + SIGNAL wire_nlillOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlillOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlillOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlilO000i_dataout : STD_LOGIC; + SIGNAL wire_nlilO000l_dataout : STD_LOGIC; + SIGNAL wire_nlilO000O_dataout : STD_LOGIC; + SIGNAL wire_nlilO001i_dataout : STD_LOGIC; + SIGNAL wire_nlilO001l_dataout : STD_LOGIC; + SIGNAL wire_nlilO001O_dataout : STD_LOGIC; + SIGNAL wire_nlilO00i_dataout : STD_LOGIC; + SIGNAL wire_nlilO00ii_dataout : STD_LOGIC; + SIGNAL wire_nlilO00il_dataout : STD_LOGIC; + SIGNAL wire_nlilO00iO_dataout : STD_LOGIC; + SIGNAL wire_nlilO00l_dataout : STD_LOGIC; + SIGNAL wire_nlilO00li_dataout : STD_LOGIC; + SIGNAL wire_nlilO00ll_dataout : STD_LOGIC; + SIGNAL wire_nlilO00lO_dataout : STD_LOGIC; + SIGNAL wire_nlilO00O_dataout : STD_LOGIC; + SIGNAL wire_nlilO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilO00OO_dataout : STD_LOGIC; + SIGNAL wire_nlilO010i_dataout : STD_LOGIC; + SIGNAL wire_nlilO010l_dataout : STD_LOGIC; + SIGNAL wire_nlilO010O_dataout : STD_LOGIC; + SIGNAL wire_nlilO011i_dataout : STD_LOGIC; + SIGNAL wire_nlilO011l_dataout : STD_LOGIC; + SIGNAL wire_nlilO011O_dataout : STD_LOGIC; + SIGNAL wire_nlilO01i_dataout : STD_LOGIC; + SIGNAL wire_nlilO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlilO01il_dataout : STD_LOGIC; + SIGNAL wire_nlilO01iO_dataout : STD_LOGIC; + SIGNAL wire_nlilO01l_dataout : STD_LOGIC; + SIGNAL wire_nlilO01li_dataout : STD_LOGIC; + SIGNAL wire_nlilO01ll_dataout : STD_LOGIC; + SIGNAL wire_nlilO01lO_dataout : STD_LOGIC; + SIGNAL wire_nlilO01O_dataout : STD_LOGIC; + SIGNAL wire_nlilO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilO01OO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlilO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlilO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlilO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlilO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlilO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlilO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlilO0iii_dataout : STD_LOGIC; + SIGNAL wire_nlilO0iil_dataout : STD_LOGIC; + SIGNAL wire_nlilO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0il_dataout : STD_LOGIC; + SIGNAL wire_nlilO0ili_dataout : STD_LOGIC; + SIGNAL wire_nlilO0ill_dataout : STD_LOGIC; + SIGNAL wire_nlilO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlilO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlilO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlilO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlilO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlilO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlilO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlilO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlilO0li_dataout : STD_LOGIC; + SIGNAL wire_nlilO0lii_dataout : STD_LOGIC; + SIGNAL wire_nlilO0lil_dataout : STD_LOGIC; + SIGNAL wire_nlilO0liO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlilO0lli_dataout : STD_LOGIC; + SIGNAL wire_nlilO0lll_dataout : STD_LOGIC; + SIGNAL wire_nlilO0llO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlilO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlilO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlilO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlilO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlilO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlilO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlilO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlilO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlilO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlilO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlilO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlilO100i_dataout : STD_LOGIC; + SIGNAL wire_nlilO100l_dataout : STD_LOGIC; + SIGNAL wire_nlilO100O_dataout : STD_LOGIC; + SIGNAL wire_nlilO101i_dataout : STD_LOGIC; + SIGNAL wire_nlilO101l_dataout : STD_LOGIC; + SIGNAL wire_nlilO101O_dataout : STD_LOGIC; + SIGNAL wire_nlilO10i_dataout : STD_LOGIC; + SIGNAL wire_nlilO10ii_dataout : STD_LOGIC; + SIGNAL wire_nlilO10il_dataout : STD_LOGIC; + SIGNAL wire_nlilO10iO_dataout : STD_LOGIC; + SIGNAL wire_nlilO10l_dataout : STD_LOGIC; + SIGNAL wire_nlilO10li_dataout : STD_LOGIC; + SIGNAL wire_nlilO10ll_dataout : STD_LOGIC; + SIGNAL wire_nlilO10lO_dataout : STD_LOGIC; + SIGNAL wire_nlilO10O_dataout : STD_LOGIC; + SIGNAL wire_nlilO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilO10OO_dataout : STD_LOGIC; + SIGNAL wire_nlilO110i_dataout : STD_LOGIC; + SIGNAL wire_nlilO110l_dataout : STD_LOGIC; + SIGNAL wire_nlilO110O_dataout : STD_LOGIC; + SIGNAL wire_nlilO111i_dataout : STD_LOGIC; + SIGNAL wire_nlilO111l_dataout : STD_LOGIC; + SIGNAL wire_nlilO111O_dataout : STD_LOGIC; + SIGNAL wire_nlilO11i_dataout : STD_LOGIC; + SIGNAL wire_nlilO11ii_dataout : STD_LOGIC; + SIGNAL wire_nlilO11il_dataout : STD_LOGIC; + SIGNAL wire_nlilO11iO_dataout : STD_LOGIC; + SIGNAL wire_nlilO11l_dataout : STD_LOGIC; + SIGNAL wire_nlilO11li_dataout : STD_LOGIC; + SIGNAL wire_nlilO11ll_dataout : STD_LOGIC; + SIGNAL wire_nlilO11lO_dataout : STD_LOGIC; + SIGNAL wire_nlilO11O_dataout : STD_LOGIC; + SIGNAL wire_nlilO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilO11OO_dataout : STD_LOGIC; + SIGNAL wire_nlilO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlilO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlilO1il_dataout : STD_LOGIC; + SIGNAL wire_nlilO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlilO1li_dataout : STD_LOGIC; + SIGNAL wire_nlilO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlilO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlilO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlilO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlilO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlilO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi00i_dataout : STD_LOGIC; + SIGNAL wire_nlilOi00l_dataout : STD_LOGIC; + SIGNAL wire_nlilOi00O_dataout : STD_LOGIC; + SIGNAL wire_nlilOi01i_dataout : STD_LOGIC; + SIGNAL wire_nlilOi01l_dataout : STD_LOGIC; + SIGNAL wire_nlilOi01O_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0il_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi10i_dataout : STD_LOGIC; + SIGNAL wire_nlilOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlilOi10O_dataout : STD_LOGIC; + SIGNAL wire_nlilOi11i_dataout : STD_LOGIC; + SIGNAL wire_nlilOi11l_dataout : STD_LOGIC; + SIGNAL wire_nlilOi11O_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1il_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlilOii0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOii0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOii0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOii1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOii1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOii1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOiii_dataout : STD_LOGIC; + SIGNAL wire_nlilOiiii_dataout : STD_LOGIC; + SIGNAL wire_nlilOiiil_dataout : STD_LOGIC; + SIGNAL wire_nlilOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlilOiil_dataout : STD_LOGIC; + SIGNAL wire_nlilOiili_dataout : STD_LOGIC; + SIGNAL wire_nlilOiill_dataout : STD_LOGIC; + SIGNAL wire_nlilOiilO_dataout : STD_LOGIC; + SIGNAL wire_nlilOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlilOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOil0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOil0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOil0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOil1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOil1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOil1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOili_dataout : STD_LOGIC; + SIGNAL wire_nlilOill_dataout : STD_LOGIC; + SIGNAL wire_nlilOilO_dataout : STD_LOGIC; + SIGNAL wire_nlilOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOl00i_dataout : STD_LOGIC; + SIGNAL wire_nlilOl00l_dataout : STD_LOGIC; + SIGNAL wire_nlilOl00O_dataout : STD_LOGIC; + SIGNAL wire_nlilOl01i_dataout : STD_LOGIC; + SIGNAL wire_nlilOl01l_dataout : STD_LOGIC; + SIGNAL wire_nlilOl01O_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0il_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0li_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nlilOl10i_dataout : STD_LOGIC; + SIGNAL wire_nlilOl10l_dataout : STD_LOGIC; + SIGNAL wire_nlilOl10O_dataout : STD_LOGIC; + SIGNAL wire_nlilOl11i_dataout : STD_LOGIC; + SIGNAL wire_nlilOl11l_dataout : STD_LOGIC; + SIGNAL wire_nlilOl11O_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1il_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1li_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nlilOli0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOli0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOli0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOli1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOli1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOli1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOlii_dataout : STD_LOGIC; + SIGNAL wire_nlilOliii_dataout : STD_LOGIC; + SIGNAL wire_nlilOliil_dataout : STD_LOGIC; + SIGNAL wire_nlilOliiO_dataout : STD_LOGIC; + SIGNAL wire_nlilOlil_dataout : STD_LOGIC; + SIGNAL wire_nlilOliO_dataout : STD_LOGIC; + SIGNAL wire_nlilOlli_dataout : STD_LOGIC; + SIGNAL wire_nlilOlll_dataout : STD_LOGIC; + SIGNAL wire_nlilOllO_dataout : STD_LOGIC; + SIGNAL wire_nlilOllOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOllOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOllOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOii_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOil_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlilOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlilOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlilOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlilOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlilOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlilOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0il_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlilOO10i_dataout : STD_LOGIC; + SIGNAL wire_nlilOO10l_dataout : STD_LOGIC; + SIGNAL wire_nlilOO10O_dataout : STD_LOGIC; + SIGNAL wire_nlilOO11O_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1il_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1li_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlilOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOOii_dataout : STD_LOGIC; + SIGNAL wire_nlilOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlilOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOil_dataout : STD_LOGIC; + SIGNAL wire_nlilOOili_dataout : STD_LOGIC; + SIGNAL wire_nlilOOill_dataout : STD_LOGIC; + SIGNAL wire_nlilOOilO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOOli_dataout : STD_LOGIC; + SIGNAL wire_nlilOOlii_dataout : STD_LOGIC; + SIGNAL wire_nlilOOlil_dataout : STD_LOGIC; + SIGNAL wire_nlilOOliO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOll_dataout : STD_LOGIC; + SIGNAL wire_nlilOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlilOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlilOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlilOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlilOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlilOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOli_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOll_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlilOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nliO010i_dataout : STD_LOGIC; + SIGNAL wire_nliO010l_dataout : STD_LOGIC; + SIGNAL wire_nliO010O_dataout : STD_LOGIC; + SIGNAL wire_nliO011i_dataout : STD_LOGIC; + SIGNAL wire_nliO011l_dataout : STD_LOGIC; + SIGNAL wire_nliO011O_dataout : STD_LOGIC; + SIGNAL wire_nliO01ii_dataout : STD_LOGIC; + SIGNAL wire_nliO01il_dataout : STD_LOGIC; + SIGNAL wire_nliO01iO_dataout : STD_LOGIC; + SIGNAL wire_nliO100i_dataout : STD_LOGIC; + SIGNAL wire_nliO100l_dataout : STD_LOGIC; + SIGNAL wire_nliO100O_dataout : STD_LOGIC; + SIGNAL wire_nliO101i_dataout : STD_LOGIC; + SIGNAL wire_nliO101l_dataout : STD_LOGIC; + SIGNAL wire_nliO101O_dataout : STD_LOGIC; + SIGNAL wire_nliO10ii_dataout : STD_LOGIC; + SIGNAL wire_nliO10il_dataout : STD_LOGIC; + SIGNAL wire_nliO10iO_dataout : STD_LOGIC; + SIGNAL wire_nliO10li_dataout : STD_LOGIC; + SIGNAL wire_nliO10ll_dataout : STD_LOGIC; + SIGNAL wire_nliO10lO_dataout : STD_LOGIC; + SIGNAL wire_nliO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nliO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nliO10OO_dataout : STD_LOGIC; + SIGNAL wire_nliO110i_dataout : STD_LOGIC; + SIGNAL wire_nliO110l_dataout : STD_LOGIC; + SIGNAL wire_nliO110O_dataout : STD_LOGIC; + SIGNAL wire_nliO1111i_dataout : STD_LOGIC; + SIGNAL wire_nliO1111l_dataout : STD_LOGIC; + SIGNAL wire_nliO111i_dataout : STD_LOGIC; + SIGNAL wire_nliO111l_dataout : STD_LOGIC; + SIGNAL wire_nliO111O_dataout : STD_LOGIC; + SIGNAL wire_nliO11ii_dataout : STD_LOGIC; + SIGNAL wire_nliO11il_dataout : STD_LOGIC; + SIGNAL wire_nliO11iO_dataout : STD_LOGIC; + SIGNAL wire_nliO11li_dataout : STD_LOGIC; + SIGNAL wire_nliO11ll_dataout : STD_LOGIC; + SIGNAL wire_nliO11lO_dataout : STD_LOGIC; + SIGNAL wire_nliO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nliO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nliO11OO_dataout : STD_LOGIC; + SIGNAL wire_nliO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nliO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nliO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nliO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nliO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nliO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nliO1iii_dataout : STD_LOGIC; + SIGNAL wire_nliO1iil_dataout : STD_LOGIC; + SIGNAL wire_nliO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nliO1ili_dataout : STD_LOGIC; + SIGNAL wire_nliO1ill_dataout : STD_LOGIC; + SIGNAL wire_nliO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nliO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nliO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nliO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nliO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nliO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nliO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nliO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nliO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nliO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nliO1lii_dataout : STD_LOGIC; + SIGNAL wire_nliO1lil_dataout : STD_LOGIC; + SIGNAL wire_nliO1liO_dataout : STD_LOGIC; + SIGNAL wire_nliO1lli_dataout : STD_LOGIC; + SIGNAL wire_nliO1lll_dataout : STD_LOGIC; + SIGNAL wire_nliO1llO_dataout : STD_LOGIC; + SIGNAL wire_nliO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nliO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nliO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nliO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nliO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nliO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nliO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nliO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nliO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nliO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nliO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nliO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nliO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nliO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nliO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nliO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nliO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nliO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nliOliOi_dataout : STD_LOGIC; + SIGNAL wire_nliOliOl_dataout : STD_LOGIC; + SIGNAL wire_nliOliOO_dataout : STD_LOGIC; + SIGNAL wire_nliOll0i_dataout : STD_LOGIC; + SIGNAL wire_nliOll0l_dataout : STD_LOGIC; + SIGNAL wire_nliOll0O_dataout : STD_LOGIC; + SIGNAL wire_nliOll1i_dataout : STD_LOGIC; + SIGNAL wire_nliOll1l_dataout : STD_LOGIC; + SIGNAL wire_nliOll1O_dataout : STD_LOGIC; + SIGNAL wire_nliOllii_dataout : STD_LOGIC; + SIGNAL wire_nliOllil_dataout : STD_LOGIC; + SIGNAL wire_nliOlliO_dataout : STD_LOGIC; + SIGNAL wire_nliOllli_dataout : STD_LOGIC; + SIGNAL wire_nliOllll_dataout : STD_LOGIC; + SIGNAL wire_nliOlllO_dataout : STD_LOGIC; + SIGNAL wire_nliOllOi_dataout : STD_LOGIC; + SIGNAL wire_nliOllOl_dataout : STD_LOGIC; + SIGNAL wire_nliOllOO_dataout : STD_LOGIC; + SIGNAL wire_nliOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nliOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nliOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nliOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nliOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nliOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nliOlOii_dataout : STD_LOGIC; + SIGNAL wire_nliOlOil_dataout : STD_LOGIC; + SIGNAL wire_nliOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nliOlOli_dataout : STD_LOGIC; + SIGNAL wire_nliOlOll_dataout : STD_LOGIC; + SIGNAL wire_nliOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nliOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nliOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nliOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nliOO00i_dataout : STD_LOGIC; + SIGNAL wire_nliOO00l_dataout : STD_LOGIC; + SIGNAL wire_nliOO00O_dataout : STD_LOGIC; + SIGNAL wire_nliOO01i_dataout : STD_LOGIC; + SIGNAL wire_nliOO01l_dataout : STD_LOGIC; + SIGNAL wire_nliOO01O_dataout : STD_LOGIC; + SIGNAL wire_nliOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nliOO0il_dataout : STD_LOGIC; + SIGNAL wire_nliOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nliOO0li_dataout : STD_LOGIC; + SIGNAL wire_nliOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nliOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nliOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nliOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nliOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nliOO10i_dataout : STD_LOGIC; + SIGNAL wire_nliOO10l_dataout : STD_LOGIC; + SIGNAL wire_nliOO10O_dataout : STD_LOGIC; + SIGNAL wire_nliOO11i_dataout : STD_LOGIC; + SIGNAL wire_nliOO11l_dataout : STD_LOGIC; + SIGNAL wire_nliOO11O_dataout : STD_LOGIC; + SIGNAL wire_nliOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nliOO1il_dataout : STD_LOGIC; + SIGNAL wire_nliOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nliOO1li_dataout : STD_LOGIC; + SIGNAL wire_nliOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nliOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nliOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nliOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nliOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nliOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nliOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nliOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nliOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nliOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nliOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nliOOiii_dataout : STD_LOGIC; + SIGNAL wire_nliOOiil_dataout : STD_LOGIC; + SIGNAL wire_nliOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nliOOili_dataout : STD_LOGIC; + SIGNAL wire_nliOOill_dataout : STD_LOGIC; + SIGNAL wire_nliOOilO_dataout : STD_LOGIC; + SIGNAL wire_nliOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nliOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nliOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nliOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nliOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nliOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nliOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nliOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nliOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nliOOlii_dataout : STD_LOGIC; + SIGNAL wire_nliOOlil_dataout : STD_LOGIC; + SIGNAL wire_nliOOliO_dataout : STD_LOGIC; + SIGNAL wire_nliOOlli_dataout : STD_LOGIC; + SIGNAL wire_nliOOlll_dataout : STD_LOGIC; + SIGNAL wire_nliOOllO_dataout : STD_LOGIC; + SIGNAL wire_nliOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nliOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nliOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nliOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nliOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nliOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nliOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nliOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nliOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nliOOOii_dataout : STD_LOGIC; + SIGNAL wire_nliOOOil_dataout : STD_LOGIC; + SIGNAL wire_nliOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nliOOOli_dataout : STD_LOGIC; + SIGNAL wire_nliOOOll_dataout : STD_LOGIC; + SIGNAL wire_nliOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nliOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nliOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nliOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0000i_dataout : STD_LOGIC; + SIGNAL wire_nll0000l_dataout : STD_LOGIC; + SIGNAL wire_nll0000O_dataout : STD_LOGIC; + SIGNAL wire_nll0001i_dataout : STD_LOGIC; + SIGNAL wire_nll0001l_dataout : STD_LOGIC; + SIGNAL wire_nll0001O_dataout : STD_LOGIC; + SIGNAL wire_nll000ii_dataout : STD_LOGIC; + SIGNAL wire_nll000il_dataout : STD_LOGIC; + SIGNAL wire_nll000iO_dataout : STD_LOGIC; + SIGNAL wire_nll000li_dataout : STD_LOGIC; + SIGNAL wire_nll000ll_dataout : STD_LOGIC; + SIGNAL wire_nll000lO_dataout : STD_LOGIC; + SIGNAL wire_nll000Oi_dataout : STD_LOGIC; + SIGNAL wire_nll000Ol_dataout : STD_LOGIC; + SIGNAL wire_nll000OO_dataout : STD_LOGIC; + SIGNAL wire_nll0010i_dataout : STD_LOGIC; + SIGNAL wire_nll0010l_dataout : STD_LOGIC; + SIGNAL wire_nll0010O_dataout : STD_LOGIC; + SIGNAL wire_nll0011i_dataout : STD_LOGIC; + SIGNAL wire_nll0011l_dataout : STD_LOGIC; + SIGNAL wire_nll0011O_dataout : STD_LOGIC; + SIGNAL wire_nll001ii_dataout : STD_LOGIC; + SIGNAL wire_nll001il_dataout : STD_LOGIC; + SIGNAL wire_nll001iO_dataout : STD_LOGIC; + SIGNAL wire_nll001li_dataout : STD_LOGIC; + SIGNAL wire_nll001ll_dataout : STD_LOGIC; + SIGNAL wire_nll001lO_dataout : STD_LOGIC; + SIGNAL wire_nll001Oi_dataout : STD_LOGIC; + SIGNAL wire_nll001Ol_dataout : STD_LOGIC; + SIGNAL wire_nll001OO_dataout : STD_LOGIC; + SIGNAL wire_nll00i0i_dataout : STD_LOGIC; + SIGNAL wire_nll00i0l_dataout : STD_LOGIC; + SIGNAL wire_nll00i0O_dataout : STD_LOGIC; + SIGNAL wire_nll00i1i_dataout : STD_LOGIC; + SIGNAL wire_nll00i1l_dataout : STD_LOGIC; + SIGNAL wire_nll00i1O_dataout : STD_LOGIC; + SIGNAL wire_nll00iii_dataout : STD_LOGIC; + SIGNAL wire_nll00iil_dataout : STD_LOGIC; + SIGNAL wire_nll00iiO_dataout : STD_LOGIC; + SIGNAL wire_nll00ili_dataout : STD_LOGIC; + SIGNAL wire_nll00ill_dataout : STD_LOGIC; + SIGNAL wire_nll00ilO_dataout : STD_LOGIC; + SIGNAL wire_nll00iOi_dataout : STD_LOGIC; + SIGNAL wire_nll00iOl_dataout : STD_LOGIC; + SIGNAL wire_nll00iOO_dataout : STD_LOGIC; + SIGNAL wire_nll00l0i_dataout : STD_LOGIC; + SIGNAL wire_nll00l0l_dataout : STD_LOGIC; + SIGNAL wire_nll00l0O_dataout : STD_LOGIC; + SIGNAL wire_nll00l1i_dataout : STD_LOGIC; + SIGNAL wire_nll00l1l_dataout : STD_LOGIC; + SIGNAL wire_nll00l1O_dataout : STD_LOGIC; + SIGNAL wire_nll00lii_dataout : STD_LOGIC; + SIGNAL wire_nll00lil_dataout : STD_LOGIC; + SIGNAL wire_nll00liO_dataout : STD_LOGIC; + SIGNAL wire_nll00lli_dataout : STD_LOGIC; + SIGNAL wire_nll00lll_dataout : STD_LOGIC; + SIGNAL wire_nll00llO_dataout : STD_LOGIC; + SIGNAL wire_nll00lOi_dataout : STD_LOGIC; + SIGNAL wire_nll00lOl_dataout : STD_LOGIC; + SIGNAL wire_nll00lOO_dataout : STD_LOGIC; + SIGNAL wire_nll00O0i_dataout : STD_LOGIC; + SIGNAL wire_nll00O0l_dataout : STD_LOGIC; + SIGNAL wire_nll00O0O_dataout : STD_LOGIC; + SIGNAL wire_nll00O1i_dataout : STD_LOGIC; + SIGNAL wire_nll00O1l_dataout : STD_LOGIC; + SIGNAL wire_nll00O1O_dataout : STD_LOGIC; + SIGNAL wire_nll00Oii_dataout : STD_LOGIC; + SIGNAL wire_nll00Oil_dataout : STD_LOGIC; + SIGNAL wire_nll00OiO_dataout : STD_LOGIC; + SIGNAL wire_nll00Oli_dataout : STD_LOGIC; + SIGNAL wire_nll00Oll_dataout : STD_LOGIC; + SIGNAL wire_nll00OlO_dataout : STD_LOGIC; + SIGNAL wire_nll00OOi_dataout : STD_LOGIC; + SIGNAL wire_nll00OOl_dataout : STD_LOGIC; + SIGNAL wire_nll00OOO_dataout : STD_LOGIC; + SIGNAL wire_nll0100i_dataout : STD_LOGIC; + SIGNAL wire_nll0100l_dataout : STD_LOGIC; + SIGNAL wire_nll0100O_dataout : STD_LOGIC; + SIGNAL wire_nll0101i_dataout : STD_LOGIC; + SIGNAL wire_nll0101l_dataout : STD_LOGIC; + SIGNAL wire_nll0101O_dataout : STD_LOGIC; + SIGNAL wire_nll010ii_dataout : STD_LOGIC; + SIGNAL wire_nll010il_dataout : STD_LOGIC; + SIGNAL wire_nll010iO_dataout : STD_LOGIC; + SIGNAL wire_nll010li_dataout : STD_LOGIC; + SIGNAL wire_nll010ll_dataout : STD_LOGIC; + SIGNAL wire_nll010lO_dataout : STD_LOGIC; + SIGNAL wire_nll010Oi_dataout : STD_LOGIC; + SIGNAL wire_nll010Ol_dataout : STD_LOGIC; + SIGNAL wire_nll010OO_dataout : STD_LOGIC; + SIGNAL wire_nll0110i_dataout : STD_LOGIC; + SIGNAL wire_nll0110l_dataout : STD_LOGIC; + SIGNAL wire_nll0110O_dataout : STD_LOGIC; + SIGNAL wire_nll0111i_dataout : STD_LOGIC; + SIGNAL wire_nll0111l_dataout : STD_LOGIC; + SIGNAL wire_nll0111O_dataout : STD_LOGIC; + SIGNAL wire_nll011ii_dataout : STD_LOGIC; + SIGNAL wire_nll011il_dataout : STD_LOGIC; + SIGNAL wire_nll011iO_dataout : STD_LOGIC; + SIGNAL wire_nll011li_dataout : STD_LOGIC; + SIGNAL wire_nll011ll_dataout : STD_LOGIC; + SIGNAL wire_nll011lO_dataout : STD_LOGIC; + SIGNAL wire_nll011Oi_dataout : STD_LOGIC; + SIGNAL wire_nll011Ol_dataout : STD_LOGIC; + SIGNAL wire_nll011OO_dataout : STD_LOGIC; + SIGNAL wire_nll01i0i_dataout : STD_LOGIC; + SIGNAL wire_nll01i0l_dataout : STD_LOGIC; + SIGNAL wire_nll01i0O_dataout : STD_LOGIC; + SIGNAL wire_nll01i1i_dataout : STD_LOGIC; + SIGNAL wire_nll01i1l_dataout : STD_LOGIC; + SIGNAL wire_nll01i1O_dataout : STD_LOGIC; + SIGNAL wire_nll01iii_dataout : STD_LOGIC; + SIGNAL wire_nll01iil_dataout : STD_LOGIC; + SIGNAL wire_nll01iiO_dataout : STD_LOGIC; + SIGNAL wire_nll01ili_dataout : STD_LOGIC; + SIGNAL wire_nll01ill_dataout : STD_LOGIC; + SIGNAL wire_nll01ilO_dataout : STD_LOGIC; + SIGNAL wire_nll01iOi_dataout : STD_LOGIC; + SIGNAL wire_nll01iOl_dataout : STD_LOGIC; + SIGNAL wire_nll01iOO_dataout : STD_LOGIC; + SIGNAL wire_nll01l0i_dataout : STD_LOGIC; + SIGNAL wire_nll01l0l_dataout : STD_LOGIC; + SIGNAL wire_nll01l0O_dataout : STD_LOGIC; + SIGNAL wire_nll01l1i_dataout : STD_LOGIC; + SIGNAL wire_nll01l1l_dataout : STD_LOGIC; + SIGNAL wire_nll01l1O_dataout : STD_LOGIC; + SIGNAL wire_nll01lii_dataout : STD_LOGIC; + SIGNAL wire_nll01lil_dataout : STD_LOGIC; + SIGNAL wire_nll01liO_dataout : STD_LOGIC; + SIGNAL wire_nll01lli_dataout : STD_LOGIC; + SIGNAL wire_nll01lll_dataout : STD_LOGIC; + SIGNAL wire_nll01llO_dataout : STD_LOGIC; + SIGNAL wire_nll01lOi_dataout : STD_LOGIC; + SIGNAL wire_nll01lOl_dataout : STD_LOGIC; + SIGNAL wire_nll01lOO_dataout : STD_LOGIC; + SIGNAL wire_nll01O0i_dataout : STD_LOGIC; + SIGNAL wire_nll01O0l_dataout : STD_LOGIC; + SIGNAL wire_nll01O0O_dataout : STD_LOGIC; + SIGNAL wire_nll01O1i_dataout : STD_LOGIC; + SIGNAL wire_nll01O1l_dataout : STD_LOGIC; + SIGNAL wire_nll01O1O_dataout : STD_LOGIC; + SIGNAL wire_nll01Oii_dataout : STD_LOGIC; + SIGNAL wire_nll01Oil_dataout : STD_LOGIC; + SIGNAL wire_nll01OiO_dataout : STD_LOGIC; + SIGNAL wire_nll01Oli_dataout : STD_LOGIC; + SIGNAL wire_nll01Oll_dataout : STD_LOGIC; + SIGNAL wire_nll01OlO_dataout : STD_LOGIC; + SIGNAL wire_nll01OOi_dataout : STD_LOGIC; + SIGNAL wire_nll01OOl_dataout : STD_LOGIC; + SIGNAL wire_nll01OOO_dataout : STD_LOGIC; + SIGNAL wire_nll0i00i_dataout : STD_LOGIC; + SIGNAL wire_nll0i00l_dataout : STD_LOGIC; + SIGNAL wire_nll0i00O_dataout : STD_LOGIC; + SIGNAL wire_nll0i01i_dataout : STD_LOGIC; + SIGNAL wire_nll0i01l_dataout : STD_LOGIC; + SIGNAL wire_nll0i01O_dataout : STD_LOGIC; + SIGNAL wire_nll0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0i0il_dataout : STD_LOGIC; + SIGNAL wire_nll0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0i0li_dataout : STD_LOGIC; + SIGNAL wire_nll0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nll0i10i_dataout : STD_LOGIC; + SIGNAL wire_nll0i10l_dataout : STD_LOGIC; + SIGNAL wire_nll0i10O_dataout : STD_LOGIC; + SIGNAL wire_nll0i11i_dataout : STD_LOGIC; + SIGNAL wire_nll0i11l_dataout : STD_LOGIC; + SIGNAL wire_nll0i11O_dataout : STD_LOGIC; + SIGNAL wire_nll0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nll0i1il_dataout : STD_LOGIC; + SIGNAL wire_nll0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nll0i1li_dataout : STD_LOGIC; + SIGNAL wire_nll0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nll0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nll0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nll0ii00i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii00l_dataout : STD_LOGIC; + SIGNAL wire_nll0ii00O_dataout : STD_LOGIC; + SIGNAL wire_nll0ii01i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii01l_dataout : STD_LOGIC; + SIGNAL wire_nll0ii01O_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0il_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0li_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0ii0OO_dataout : STD_LOGIC; + SIGNAL wire_nll0ii10i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii10l_dataout : STD_LOGIC; + SIGNAL wire_nll0ii10O_dataout : STD_LOGIC; + SIGNAL wire_nll0ii11i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii11l_dataout : STD_LOGIC; + SIGNAL wire_nll0ii11O_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1ii_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1il_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1iO_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1li_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1ll_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1lO_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0ii1OO_dataout : STD_LOGIC; + SIGNAL wire_nll0iii0i_dataout : STD_LOGIC; + SIGNAL wire_nll0iii0l_dataout : STD_LOGIC; + SIGNAL wire_nll0iii0O_dataout : STD_LOGIC; + SIGNAL wire_nll0iii1i_dataout : STD_LOGIC; + SIGNAL wire_nll0iii1l_dataout : STD_LOGIC; + SIGNAL wire_nll0iii1O_dataout : STD_LOGIC; + SIGNAL wire_nll0iiii_dataout : STD_LOGIC; + SIGNAL wire_nll0iiiii_dataout : STD_LOGIC; + SIGNAL wire_nll0iiiil_dataout : STD_LOGIC; + SIGNAL wire_nll0iiiiO_dataout : STD_LOGIC; + SIGNAL wire_nll0iiil_dataout : STD_LOGIC; + SIGNAL wire_nll0iiili_dataout : STD_LOGIC; + SIGNAL wire_nll0iiill_dataout : STD_LOGIC; + SIGNAL wire_nll0iiilO_dataout : STD_LOGIC; + SIGNAL wire_nll0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nll0iiiOi_dataout : STD_LOGIC; + SIGNAL wire_nll0iiiOl_dataout : STD_LOGIC; + SIGNAL wire_nll0iiiOO_dataout : STD_LOGIC; + SIGNAL wire_nll0iil0i_dataout : STD_LOGIC; + SIGNAL wire_nll0iil0l_dataout : STD_LOGIC; + SIGNAL wire_nll0iil0O_dataout : STD_LOGIC; + SIGNAL wire_nll0iil1i_dataout : STD_LOGIC; + SIGNAL wire_nll0iil1l_dataout : STD_LOGIC; + SIGNAL wire_nll0iil1O_dataout : STD_LOGIC; + SIGNAL wire_nll0iili_dataout : STD_LOGIC; + SIGNAL wire_nll0iilii_dataout : STD_LOGIC; + SIGNAL wire_nll0iilil_dataout : STD_LOGIC; + SIGNAL wire_nll0iiliO_dataout : STD_LOGIC; + SIGNAL wire_nll0iill_dataout : STD_LOGIC; + SIGNAL wire_nll0iilli_dataout : STD_LOGIC; + SIGNAL wire_nll0iilll_dataout : STD_LOGIC; + SIGNAL wire_nll0iillO_dataout : STD_LOGIC; + SIGNAL wire_nll0iilO_dataout : STD_LOGIC; + SIGNAL wire_nll0iilOi_dataout : STD_LOGIC; + SIGNAL wire_nll0iilOl_dataout : STD_LOGIC; + SIGNAL wire_nll0iilOO_dataout : STD_LOGIC; + SIGNAL wire_nll0iiO0i_dataout : STD_LOGIC; + SIGNAL wire_nll0iiO0l_dataout : STD_LOGIC; + SIGNAL wire_nll0iiO0O_dataout : STD_LOGIC; + SIGNAL wire_nll0iiO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0iiO1l_dataout : STD_LOGIC; + SIGNAL wire_nll0iiO1O_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOii_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOil_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOiO_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOli_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOll_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOOi_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOOl_dataout : STD_LOGIC; + SIGNAL wire_nll0iiOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0il00i_dataout : STD_LOGIC; + SIGNAL wire_nll0il00l_dataout : STD_LOGIC; + SIGNAL wire_nll0il00O_dataout : STD_LOGIC; + SIGNAL wire_nll0il01i_dataout : STD_LOGIC; + SIGNAL wire_nll0il01l_dataout : STD_LOGIC; + SIGNAL wire_nll0il01O_dataout : STD_LOGIC; + SIGNAL wire_nll0il0i_dataout : STD_LOGIC; + SIGNAL wire_nll0il0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0il0il_dataout : STD_LOGIC; + SIGNAL wire_nll0il0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0il0l_dataout : STD_LOGIC; + SIGNAL wire_nll0il0li_dataout : STD_LOGIC; + SIGNAL wire_nll0il0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0il0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0il0O_dataout : STD_LOGIC; + SIGNAL wire_nll0il0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0il0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0il0OO_dataout : STD_LOGIC; + SIGNAL wire_nll0il10i_dataout : STD_LOGIC; + SIGNAL wire_nll0il10l_dataout : STD_LOGIC; + SIGNAL wire_nll0il10O_dataout : STD_LOGIC; + SIGNAL wire_nll0il11i_dataout : STD_LOGIC; + SIGNAL wire_nll0il11l_dataout : STD_LOGIC; + SIGNAL wire_nll0il11O_dataout : STD_LOGIC; + SIGNAL wire_nll0il1i_dataout : STD_LOGIC; + SIGNAL wire_nll0il1ii_dataout : STD_LOGIC; + SIGNAL wire_nll0il1il_dataout : STD_LOGIC; + SIGNAL wire_nll0il1iO_dataout : STD_LOGIC; + SIGNAL wire_nll0il1l_dataout : STD_LOGIC; + SIGNAL wire_nll0il1li_dataout : STD_LOGIC; + SIGNAL wire_nll0il1ll_dataout : STD_LOGIC; + SIGNAL wire_nll0il1lO_dataout : STD_LOGIC; + SIGNAL wire_nll0il1O_dataout : STD_LOGIC; + SIGNAL wire_nll0il1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0il1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0il1OO_dataout : STD_LOGIC; + SIGNAL wire_nll0ili0i_dataout : STD_LOGIC; + SIGNAL wire_nll0ili0l_dataout : STD_LOGIC; + SIGNAL wire_nll0ili0O_dataout : STD_LOGIC; + SIGNAL wire_nll0ili1i_dataout : STD_LOGIC; + SIGNAL wire_nll0ili1l_dataout : STD_LOGIC; + SIGNAL wire_nll0ili1O_dataout : STD_LOGIC; + SIGNAL wire_nll0ilii_dataout : STD_LOGIC; + SIGNAL wire_nll0iliii_dataout : STD_LOGIC; + SIGNAL wire_nll0iliil_dataout : STD_LOGIC; + SIGNAL wire_nll0iliiO_dataout : STD_LOGIC; + SIGNAL wire_nll0ilil_dataout : STD_LOGIC; + SIGNAL wire_nll0ilili_dataout : STD_LOGIC; + SIGNAL wire_nll0ilill_dataout : STD_LOGIC; + SIGNAL wire_nll0ililO_dataout : STD_LOGIC; + SIGNAL wire_nll0iliO_dataout : STD_LOGIC; + SIGNAL wire_nll0iliOi_dataout : STD_LOGIC; + SIGNAL wire_nll0iliOl_dataout : STD_LOGIC; + SIGNAL wire_nll0iliOO_dataout : STD_LOGIC; + SIGNAL wire_nll0ill0i_dataout : STD_LOGIC; + SIGNAL wire_nll0ill0l_dataout : STD_LOGIC; + SIGNAL wire_nll0ill0O_dataout : STD_LOGIC; + SIGNAL wire_nll0ill1i_dataout : STD_LOGIC; + SIGNAL wire_nll0ill1l_dataout : STD_LOGIC; + SIGNAL wire_nll0ill1O_dataout : STD_LOGIC; + SIGNAL wire_nll0illi_dataout : STD_LOGIC; + SIGNAL wire_nll0illii_dataout : STD_LOGIC; + SIGNAL wire_nll0illil_dataout : STD_LOGIC; + SIGNAL wire_nll0illiO_dataout : STD_LOGIC; + SIGNAL wire_nll0illl_dataout : STD_LOGIC; + SIGNAL wire_nll0illli_dataout : STD_LOGIC; + SIGNAL wire_nll0illll_dataout : STD_LOGIC; + SIGNAL wire_nll0illlO_dataout : STD_LOGIC; + SIGNAL wire_nll0illO_dataout : STD_LOGIC; + SIGNAL wire_nll0illOi_dataout : STD_LOGIC; + SIGNAL wire_nll0illOl_dataout : STD_LOGIC; + SIGNAL wire_nll0illOO_dataout : STD_LOGIC; + SIGNAL wire_nll0ilO0i_dataout : STD_LOGIC; + SIGNAL wire_nll0ilO0l_dataout : STD_LOGIC; + SIGNAL wire_nll0ilO0O_dataout : STD_LOGIC; + SIGNAL wire_nll0ilO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0ilO1l_dataout : STD_LOGIC; + SIGNAL wire_nll0ilO1O_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOii_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOil_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOiO_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOli_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOll_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOOi_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOOl_dataout : STD_LOGIC; + SIGNAL wire_nll0ilOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nll0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nll0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nll0iO10i_dataout : STD_LOGIC; + SIGNAL wire_nll0iO10l_dataout : STD_LOGIC; + SIGNAL wire_nll0iO10O_dataout : STD_LOGIC; + SIGNAL wire_nll0iO11i_dataout : STD_LOGIC; + SIGNAL wire_nll0iO11l_dataout : STD_LOGIC; + SIGNAL wire_nll0iO11O_dataout : STD_LOGIC; + SIGNAL wire_nll0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0iO1ii_dataout : STD_LOGIC; + SIGNAL wire_nll0iO1il_dataout : STD_LOGIC; + SIGNAL wire_nll0iO1iO_dataout : STD_LOGIC; + SIGNAL wire_nll0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nll0iO1li_dataout : STD_LOGIC; + SIGNAL wire_nll0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nll0iOii_dataout : STD_LOGIC; + SIGNAL wire_nll0iOil_dataout : STD_LOGIC; + SIGNAL wire_nll0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nll0iOli_dataout : STD_LOGIC; + SIGNAL wire_nll0iOll_dataout : STD_LOGIC; + SIGNAL wire_nll0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nll0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nll0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0l00i_dataout : STD_LOGIC; + SIGNAL wire_nll0l00l_dataout : STD_LOGIC; + SIGNAL wire_nll0l00O_dataout : STD_LOGIC; + SIGNAL wire_nll0l01i_dataout : STD_LOGIC; + SIGNAL wire_nll0l01l_dataout : STD_LOGIC; + SIGNAL wire_nll0l01O_dataout : STD_LOGIC; + SIGNAL wire_nll0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0l0il_dataout : STD_LOGIC; + SIGNAL wire_nll0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0l0li_dataout : STD_LOGIC; + SIGNAL wire_nll0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nll0l10i_dataout : STD_LOGIC; + SIGNAL wire_nll0l10l_dataout : STD_LOGIC; + SIGNAL wire_nll0l10O_dataout : STD_LOGIC; + SIGNAL wire_nll0l11i_dataout : STD_LOGIC; + SIGNAL wire_nll0l11l_dataout : STD_LOGIC; + SIGNAL wire_nll0l11O_dataout : STD_LOGIC; + SIGNAL wire_nll0l1li_dataout : STD_LOGIC; + SIGNAL wire_nll0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nll0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nll0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nll0li0i_dataout : STD_LOGIC; + SIGNAL wire_nll0li0l_dataout : STD_LOGIC; + SIGNAL wire_nll0li0O_dataout : STD_LOGIC; + SIGNAL wire_nll0li1i_dataout : STD_LOGIC; + SIGNAL wire_nll0li1l_dataout : STD_LOGIC; + SIGNAL wire_nll0li1O_dataout : STD_LOGIC; + SIGNAL wire_nll0liii_dataout : STD_LOGIC; + SIGNAL wire_nll0liil_dataout : STD_LOGIC; + SIGNAL wire_nll0liiO_dataout : STD_LOGIC; + SIGNAL wire_nll0lil0i_dataout : STD_LOGIC; + SIGNAL wire_nll0lil0l_dataout : STD_LOGIC; + SIGNAL wire_nll0lil1i_dataout : STD_LOGIC; + SIGNAL wire_nll0lil1l_dataout : STD_LOGIC; + SIGNAL wire_nll0lil1O_dataout : STD_LOGIC; + SIGNAL wire_nll0lili_dataout : STD_LOGIC; + SIGNAL wire_nll0liliO_dataout : STD_LOGIC; + SIGNAL wire_nll0lill_dataout : STD_LOGIC; + SIGNAL wire_nll0lilli_dataout : STD_LOGIC; + SIGNAL wire_nll0lilll_dataout : STD_LOGIC; + SIGNAL wire_nll0lillO_dataout : STD_LOGIC; + SIGNAL wire_nll0lilO_dataout : STD_LOGIC; + SIGNAL wire_nll0lilOi_dataout : STD_LOGIC; + SIGNAL wire_nll0lilOl_dataout : STD_LOGIC; + SIGNAL wire_nll0lilOO_dataout : STD_LOGIC; + SIGNAL wire_nll0liO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0liOi_dataout : STD_LOGIC; + SIGNAL wire_nll0liOl_dataout : STD_LOGIC; + SIGNAL wire_nll0ll00i_dataout : STD_LOGIC; + SIGNAL wire_nll0ll00l_dataout : STD_LOGIC; + SIGNAL wire_nll0ll00O_dataout : STD_LOGIC; + SIGNAL wire_nll0ll01i_dataout : STD_LOGIC; + SIGNAL wire_nll0ll01l_dataout : STD_LOGIC; + SIGNAL wire_nll0ll01O_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0il_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0li_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0ll0OO_dataout : STD_LOGIC; + SIGNAL wire_nll0lli0i_dataout : STD_LOGIC; + SIGNAL wire_nll0lli0l_dataout : STD_LOGIC; + SIGNAL wire_nll0lli0O_dataout : STD_LOGIC; + SIGNAL wire_nll0lli1i_dataout : STD_LOGIC; + SIGNAL wire_nll0lli1l_dataout : STD_LOGIC; + SIGNAL wire_nll0lli1O_dataout : STD_LOGIC; + SIGNAL wire_nll0lliii_dataout : STD_LOGIC; + SIGNAL wire_nll0lliil_dataout : STD_LOGIC; + SIGNAL wire_nll0lliiO_dataout : STD_LOGIC; + SIGNAL wire_nll0llili_dataout : STD_LOGIC; + SIGNAL wire_nll0llill_dataout : STD_LOGIC; + SIGNAL wire_nll0llilO_dataout : STD_LOGIC; + SIGNAL wire_nll0lliOi_dataout : STD_LOGIC; + SIGNAL wire_nll0lliOl_dataout : STD_LOGIC; + SIGNAL wire_nll0lliOO_dataout : STD_LOGIC; + SIGNAL wire_nll0lll0i_dataout : STD_LOGIC; + SIGNAL wire_nll0lll0l_dataout : STD_LOGIC; + SIGNAL wire_nll0lll0O_dataout : STD_LOGIC; + SIGNAL wire_nll0lll1i_dataout : STD_LOGIC; + SIGNAL wire_nll0lll1l_dataout : STD_LOGIC; + SIGNAL wire_nll0lll1O_dataout : STD_LOGIC; + SIGNAL wire_nll0lllii_dataout : STD_LOGIC; + SIGNAL wire_nll0lllil_dataout : STD_LOGIC; + SIGNAL wire_nll0llliO_dataout : STD_LOGIC; + SIGNAL wire_nll0lllli_dataout : STD_LOGIC; + SIGNAL wire_nll0lllll_dataout : STD_LOGIC; + SIGNAL wire_nll0llllO_dataout : STD_LOGIC; + SIGNAL wire_nll0lllOi_dataout : STD_LOGIC; + SIGNAL wire_nll0lllOl_dataout : STD_LOGIC; + SIGNAL wire_nll0lllOO_dataout : STD_LOGIC; + SIGNAL wire_nll0llO0i_dataout : STD_LOGIC; + SIGNAL wire_nll0llO0l_dataout : STD_LOGIC; + SIGNAL wire_nll0llO0O_dataout : STD_LOGIC; + SIGNAL wire_nll0llO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0llO1l_dataout : STD_LOGIC; + SIGNAL wire_nll0llO1O_dataout : STD_LOGIC; + SIGNAL wire_nll0llOii_dataout : STD_LOGIC; + SIGNAL wire_nll0llOil_dataout : STD_LOGIC; + SIGNAL wire_nll0llOiO_dataout : STD_LOGIC; + SIGNAL wire_nll0llOli_dataout : STD_LOGIC; + SIGNAL wire_nll0llOll_dataout : STD_LOGIC; + SIGNAL wire_nll0llOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0llOOi_dataout : STD_LOGIC; + SIGNAL wire_nll0llOOl_dataout : STD_LOGIC; + SIGNAL wire_nll0llOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0lO00i_dataout : STD_LOGIC; + SIGNAL wire_nll0lO01l_dataout : STD_LOGIC; + SIGNAL wire_nll0lO01O_dataout : STD_LOGIC; + SIGNAL wire_nll0lO10i_dataout : STD_LOGIC; + SIGNAL wire_nll0lO10l_dataout : STD_LOGIC; + SIGNAL wire_nll0lO10O_dataout : STD_LOGIC; + SIGNAL wire_nll0lO11i_dataout : STD_LOGIC; + SIGNAL wire_nll0lO11l_dataout : STD_LOGIC; + SIGNAL wire_nll0lO11O_dataout : STD_LOGIC; + SIGNAL wire_nll0lO1ii_dataout : STD_LOGIC; + SIGNAL wire_nll0lO1il_dataout : STD_LOGIC; + SIGNAL wire_nll0lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nll0lO1li_dataout : STD_LOGIC; + SIGNAL wire_nll0lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nll0lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nll0lOi0i_dataout : STD_LOGIC; + SIGNAL wire_nll0lOi0l_dataout : STD_LOGIC; + SIGNAL wire_nll0lOi0O_dataout : STD_LOGIC; + SIGNAL wire_nll0lOiii_dataout : STD_LOGIC; + SIGNAL wire_nll0lOiil_dataout : STD_LOGIC; + SIGNAL wire_nll0lOiiO_dataout : STD_LOGIC; + SIGNAL wire_nll0lOili_dataout : STD_LOGIC; + SIGNAL wire_nll0lOill_dataout : STD_LOGIC; + SIGNAL wire_nll0lOilO_dataout : STD_LOGIC; + SIGNAL wire_nll0lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nll0lOiOl_dataout : STD_LOGIC; + SIGNAL wire_nll0lOiOO_dataout : STD_LOGIC; + SIGNAL wire_nll0lOl0i_dataout : STD_LOGIC; + SIGNAL wire_nll0lOl0l_dataout : STD_LOGIC; + SIGNAL wire_nll0lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nll0lOl1O_dataout : STD_LOGIC; + SIGNAL wire_nll0lOlii_dataout : STD_LOGIC; + SIGNAL wire_nll0lOlil_dataout : STD_LOGIC; + SIGNAL wire_nll0lOliO_dataout : STD_LOGIC; + SIGNAL wire_nll0lOlli_dataout : STD_LOGIC; + SIGNAL wire_nll0lOlll_dataout : STD_LOGIC; + SIGNAL wire_nll0lOllO_dataout : STD_LOGIC; + SIGNAL wire_nll0lOlOi_dataout : STD_LOGIC; + SIGNAL wire_nll0lOlOl_dataout : STD_LOGIC; + SIGNAL wire_nll0lOlOO_dataout : STD_LOGIC; + SIGNAL wire_nll0lOO0i_dataout : STD_LOGIC; + SIGNAL wire_nll0lOO0l_dataout : STD_LOGIC; + SIGNAL wire_nll0lOO0O_dataout : STD_LOGIC; + SIGNAL wire_nll0lOO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0lOO1l_dataout : STD_LOGIC; + SIGNAL wire_nll0lOO1O_dataout : STD_LOGIC; + SIGNAL wire_nll0lOOii_dataout : STD_LOGIC; + SIGNAL wire_nll0lOOll_dataout : STD_LOGIC; + SIGNAL wire_nll0lOOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0O000i_dataout : STD_LOGIC; + SIGNAL wire_nll0O000l_dataout : STD_LOGIC; + SIGNAL wire_nll0O000O_dataout : STD_LOGIC; + SIGNAL wire_nll0O001i_dataout : STD_LOGIC; + SIGNAL wire_nll0O001l_dataout : STD_LOGIC; + SIGNAL wire_nll0O001O_dataout : STD_LOGIC; + SIGNAL wire_nll0O00ii_dataout : STD_LOGIC; + SIGNAL wire_nll0O00il_dataout : STD_LOGIC; + SIGNAL wire_nll0O00iO_dataout : STD_LOGIC; + SIGNAL wire_nll0O00li_dataout : STD_LOGIC; + SIGNAL wire_nll0O010i_dataout : STD_LOGIC; + SIGNAL wire_nll0O010l_dataout : STD_LOGIC; + SIGNAL wire_nll0O010O_dataout : STD_LOGIC; + SIGNAL wire_nll0O011i_dataout : STD_LOGIC; + SIGNAL wire_nll0O011l_dataout : STD_LOGIC; + SIGNAL wire_nll0O011O_dataout : STD_LOGIC; + SIGNAL wire_nll0O01ii_dataout : STD_LOGIC; + SIGNAL wire_nll0O01il_dataout : STD_LOGIC; + SIGNAL wire_nll0O01iO_dataout : STD_LOGIC; + SIGNAL wire_nll0O01li_dataout : STD_LOGIC; + SIGNAL wire_nll0O01ll_dataout : STD_LOGIC; + SIGNAL wire_nll0O01lO_dataout : STD_LOGIC; + SIGNAL wire_nll0O01Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0O01Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0O01OO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1i0i_dataout : STD_LOGIC; + SIGNAL wire_nll0O1i0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O1i0O_dataout : STD_LOGIC; + SIGNAL wire_nll0O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nll0O1iii_dataout : STD_LOGIC; + SIGNAL wire_nll0O1iil_dataout : STD_LOGIC; + SIGNAL wire_nll0O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1ili_dataout : STD_LOGIC; + SIGNAL wire_nll0O1ill_dataout : STD_LOGIC; + SIGNAL wire_nll0O1ilO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1iOi_dataout : STD_LOGIC; + SIGNAL wire_nll0O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nll0O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1l0i_dataout : STD_LOGIC; + SIGNAL wire_nll0O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nll0O1l1i_dataout : STD_LOGIC; + SIGNAL wire_nll0O1l1l_dataout : STD_LOGIC; + SIGNAL wire_nll0O1l1O_dataout : STD_LOGIC; + SIGNAL wire_nll0O1lii_dataout : STD_LOGIC; + SIGNAL wire_nll0O1lil_dataout : STD_LOGIC; + SIGNAL wire_nll0O1liO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1lli_dataout : STD_LOGIC; + SIGNAL wire_nll0O1lll_dataout : STD_LOGIC; + SIGNAL wire_nll0O1llO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nll0O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nll0O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nll0O1O0l_dataout : STD_LOGIC; + SIGNAL wire_nll0O1O0O_dataout : STD_LOGIC; + SIGNAL wire_nll0O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nll0O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nll0O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nll0O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nll0O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nll0O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nll0O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nll0O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nll0O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nll0O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nll0O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nll0Oii0l_dataout : STD_LOGIC; + SIGNAL wire_nll0Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oiiii_dataout : STD_LOGIC; + SIGNAL wire_nll0Oiiil_dataout : STD_LOGIC; + SIGNAL wire_nll0OiiiO_dataout : STD_LOGIC; + SIGNAL wire_nll0Oiili_dataout : STD_LOGIC; + SIGNAL wire_nll0Oiill_dataout : STD_LOGIC; + SIGNAL wire_nll0OiilO_dataout : STD_LOGIC; + SIGNAL wire_nll0OiiOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OiiOO_dataout : STD_LOGIC; + SIGNAL wire_nll0Oil0i_dataout : STD_LOGIC; + SIGNAL wire_nll0Oil0l_dataout : STD_LOGIC; + SIGNAL wire_nll0Oil0O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oil1i_dataout : STD_LOGIC; + SIGNAL wire_nll0Oil1l_dataout : STD_LOGIC; + SIGNAL wire_nll0Oil1O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oilii_dataout : STD_LOGIC; + SIGNAL wire_nll0Oilil_dataout : STD_LOGIC; + SIGNAL wire_nll0OiliO_dataout : STD_LOGIC; + SIGNAL wire_nll0Oilli_dataout : STD_LOGIC; + SIGNAL wire_nll0Oilll_dataout : STD_LOGIC; + SIGNAL wire_nll0OillO_dataout : STD_LOGIC; + SIGNAL wire_nll0OilOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OilOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OilOO_dataout : STD_LOGIC; + SIGNAL wire_nll0OiO0i_dataout : STD_LOGIC; + SIGNAL wire_nll0OiO0l_dataout : STD_LOGIC; + SIGNAL wire_nll0OiO0O_dataout : STD_LOGIC; + SIGNAL wire_nll0OiO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0OiO1l_dataout : STD_LOGIC; + SIGNAL wire_nll0OiO1O_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOii_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOil_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOiO_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOli_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOll_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OiOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol00l_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol00O_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0il_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0li_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol10l_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol10O_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol11i_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1ii_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1li_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nll0Oli0i_dataout : STD_LOGIC; + SIGNAL wire_nll0Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nll0Oli0O_dataout : STD_LOGIC; + SIGNAL wire_nll0Oli1i_dataout : STD_LOGIC; + SIGNAL wire_nll0Oli1l_dataout : STD_LOGIC; + SIGNAL wire_nll0Oli1O_dataout : STD_LOGIC; + SIGNAL wire_nll0Olii_dataout : STD_LOGIC; + SIGNAL wire_nll0Oliii_dataout : STD_LOGIC; + SIGNAL wire_nll0Oliil_dataout : STD_LOGIC; + SIGNAL wire_nll0Olil_dataout : STD_LOGIC; + SIGNAL wire_nll0Olili_dataout : STD_LOGIC; + SIGNAL wire_nll0Olill_dataout : STD_LOGIC; + SIGNAL wire_nll0OlilO_dataout : STD_LOGIC; + SIGNAL wire_nll0OliO_dataout : STD_LOGIC; + SIGNAL wire_nll0OliOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OliOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OliOO_dataout : STD_LOGIC; + SIGNAL wire_nll0Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nll0Olli_dataout : STD_LOGIC; + SIGNAL wire_nll0Olll_dataout : STD_LOGIC; + SIGNAL wire_nll0OllO_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOli_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOll_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0OO00i_dataout : STD_LOGIC; + SIGNAL wire_nll0OO00l_dataout : STD_LOGIC; + SIGNAL wire_nll0OO00O_dataout : STD_LOGIC; + SIGNAL wire_nll0OO01i_dataout : STD_LOGIC; + SIGNAL wire_nll0OO01l_dataout : STD_LOGIC; + SIGNAL wire_nll0OO01O_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0ii_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0il_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0iO_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0li_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0ll_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0lO_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0OO0OO_dataout : STD_LOGIC; + SIGNAL wire_nll0OO10i_dataout : STD_LOGIC; + SIGNAL wire_nll0OO10l_dataout : STD_LOGIC; + SIGNAL wire_nll0OO10O_dataout : STD_LOGIC; + SIGNAL wire_nll0OO11i_dataout : STD_LOGIC; + SIGNAL wire_nll0OO11l_dataout : STD_LOGIC; + SIGNAL wire_nll0OO11O_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1ii_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1il_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1iO_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1li_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1ll_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1lO_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll0OO1OO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOi0i_dataout : STD_LOGIC; + SIGNAL wire_nll0OOi0l_dataout : STD_LOGIC; + SIGNAL wire_nll0OOi0O_dataout : STD_LOGIC; + SIGNAL wire_nll0OOi1i_dataout : STD_LOGIC; + SIGNAL wire_nll0OOi1l_dataout : STD_LOGIC; + SIGNAL wire_nll0OOi1O_dataout : STD_LOGIC; + SIGNAL wire_nll0OOii_dataout : STD_LOGIC; + SIGNAL wire_nll0OOiii_dataout : STD_LOGIC; + SIGNAL wire_nll0OOiil_dataout : STD_LOGIC; + SIGNAL wire_nll0OOiiO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOil_dataout : STD_LOGIC; + SIGNAL wire_nll0OOili_dataout : STD_LOGIC; + SIGNAL wire_nll0OOill_dataout : STD_LOGIC; + SIGNAL wire_nll0OOilO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOiOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OOiOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OOiOO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOl0i_dataout : STD_LOGIC; + SIGNAL wire_nll0OOl0l_dataout : STD_LOGIC; + SIGNAL wire_nll0OOl0O_dataout : STD_LOGIC; + SIGNAL wire_nll0OOl1i_dataout : STD_LOGIC; + SIGNAL wire_nll0OOl1l_dataout : STD_LOGIC; + SIGNAL wire_nll0OOl1O_dataout : STD_LOGIC; + SIGNAL wire_nll0OOli_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlii_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlil_dataout : STD_LOGIC; + SIGNAL wire_nll0OOliO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOll_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlli_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlll_dataout : STD_LOGIC; + SIGNAL wire_nll0OOllO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OOlOO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nll0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nll0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nll0OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nll10000i_dataout : STD_LOGIC; + SIGNAL wire_nll10000l_dataout : STD_LOGIC; + SIGNAL wire_nll10000O_dataout : STD_LOGIC; + SIGNAL wire_nll10001i_dataout : STD_LOGIC; + SIGNAL wire_nll10001l_dataout : STD_LOGIC; + SIGNAL wire_nll10001O_dataout : STD_LOGIC; + SIGNAL wire_nll1000i_dataout : STD_LOGIC; + SIGNAL wire_nll1000ii_dataout : STD_LOGIC; + SIGNAL wire_nll1000il_dataout : STD_LOGIC; + SIGNAL wire_nll1000iO_dataout : STD_LOGIC; + SIGNAL wire_nll1000l_dataout : STD_LOGIC; + SIGNAL wire_nll1000li_dataout : STD_LOGIC; + SIGNAL wire_nll1000ll_dataout : STD_LOGIC; + SIGNAL wire_nll1000lO_dataout : STD_LOGIC; + SIGNAL wire_nll1000O_dataout : STD_LOGIC; + SIGNAL wire_nll1000Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1000Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1000OO_dataout : STD_LOGIC; + SIGNAL wire_nll10010i_dataout : STD_LOGIC; + SIGNAL wire_nll10010l_dataout : STD_LOGIC; + SIGNAL wire_nll10010O_dataout : STD_LOGIC; + SIGNAL wire_nll10011i_dataout : STD_LOGIC; + SIGNAL wire_nll10011l_dataout : STD_LOGIC; + SIGNAL wire_nll10011O_dataout : STD_LOGIC; + SIGNAL wire_nll1001i_dataout : STD_LOGIC; + SIGNAL wire_nll1001ii_dataout : STD_LOGIC; + SIGNAL wire_nll1001il_dataout : STD_LOGIC; + SIGNAL wire_nll1001iO_dataout : STD_LOGIC; + SIGNAL wire_nll1001l_dataout : STD_LOGIC; + SIGNAL wire_nll1001li_dataout : STD_LOGIC; + SIGNAL wire_nll1001ll_dataout : STD_LOGIC; + SIGNAL wire_nll1001lO_dataout : STD_LOGIC; + SIGNAL wire_nll1001O_dataout : STD_LOGIC; + SIGNAL wire_nll1001Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1001Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1001OO_dataout : STD_LOGIC; + SIGNAL wire_nll100i0i_dataout : STD_LOGIC; + SIGNAL wire_nll100i0l_dataout : STD_LOGIC; + SIGNAL wire_nll100i0O_dataout : STD_LOGIC; + SIGNAL wire_nll100i1i_dataout : STD_LOGIC; + SIGNAL wire_nll100i1l_dataout : STD_LOGIC; + SIGNAL wire_nll100i1O_dataout : STD_LOGIC; + SIGNAL wire_nll100ii_dataout : STD_LOGIC; + SIGNAL wire_nll100iii_dataout : STD_LOGIC; + SIGNAL wire_nll100iil_dataout : STD_LOGIC; + SIGNAL wire_nll100iiO_dataout : STD_LOGIC; + SIGNAL wire_nll100il_dataout : STD_LOGIC; + SIGNAL wire_nll100ili_dataout : STD_LOGIC; + SIGNAL wire_nll100ill_dataout : STD_LOGIC; + SIGNAL wire_nll100ilO_dataout : STD_LOGIC; + SIGNAL wire_nll100iO_dataout : STD_LOGIC; + SIGNAL wire_nll100iOi_dataout : STD_LOGIC; + SIGNAL wire_nll100iOl_dataout : STD_LOGIC; + SIGNAL wire_nll100iOO_dataout : STD_LOGIC; + SIGNAL wire_nll100l0i_dataout : STD_LOGIC; + SIGNAL wire_nll100l0l_dataout : STD_LOGIC; + SIGNAL wire_nll100l0O_dataout : STD_LOGIC; + SIGNAL wire_nll100l1i_dataout : STD_LOGIC; + SIGNAL wire_nll100l1l_dataout : STD_LOGIC; + SIGNAL wire_nll100l1O_dataout : STD_LOGIC; + SIGNAL wire_nll100li_dataout : STD_LOGIC; + SIGNAL wire_nll100lii_dataout : STD_LOGIC; + SIGNAL wire_nll100lil_dataout : STD_LOGIC; + SIGNAL wire_nll100liO_dataout : STD_LOGIC; + SIGNAL wire_nll100ll_dataout : STD_LOGIC; + SIGNAL wire_nll100lli_dataout : STD_LOGIC; + SIGNAL wire_nll100lll_dataout : STD_LOGIC; + SIGNAL wire_nll100llO_dataout : STD_LOGIC; + SIGNAL wire_nll100lO_dataout : STD_LOGIC; + SIGNAL wire_nll100lOi_dataout : STD_LOGIC; + SIGNAL wire_nll100lOl_dataout : STD_LOGIC; + SIGNAL wire_nll100lOO_dataout : STD_LOGIC; + SIGNAL wire_nll100O0i_dataout : STD_LOGIC; + SIGNAL wire_nll100O0l_dataout : STD_LOGIC; + SIGNAL wire_nll100O0O_dataout : STD_LOGIC; + SIGNAL wire_nll100O1i_dataout : STD_LOGIC; + SIGNAL wire_nll100O1l_dataout : STD_LOGIC; + SIGNAL wire_nll100O1O_dataout : STD_LOGIC; + SIGNAL wire_nll100Oi_dataout : STD_LOGIC; + SIGNAL wire_nll100Oii_dataout : STD_LOGIC; + SIGNAL wire_nll100Ol_dataout : STD_LOGIC; + SIGNAL wire_nll100OO_dataout : STD_LOGIC; + SIGNAL wire_nll10100i_dataout : STD_LOGIC; + SIGNAL wire_nll10100l_dataout : STD_LOGIC; + SIGNAL wire_nll10100O_dataout : STD_LOGIC; + SIGNAL wire_nll10101i_dataout : STD_LOGIC; + SIGNAL wire_nll10101l_dataout : STD_LOGIC; + SIGNAL wire_nll10101O_dataout : STD_LOGIC; + SIGNAL wire_nll1010i_dataout : STD_LOGIC; + SIGNAL wire_nll1010ii_dataout : STD_LOGIC; + SIGNAL wire_nll1010il_dataout : STD_LOGIC; + SIGNAL wire_nll1010iO_dataout : STD_LOGIC; + SIGNAL wire_nll1010l_dataout : STD_LOGIC; + SIGNAL wire_nll1010li_dataout : STD_LOGIC; + SIGNAL wire_nll1010ll_dataout : STD_LOGIC; + SIGNAL wire_nll1010lO_dataout : STD_LOGIC; + SIGNAL wire_nll1010O_dataout : STD_LOGIC; + SIGNAL wire_nll1010Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1010Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1010OO_dataout : STD_LOGIC; + SIGNAL wire_nll10110i_dataout : STD_LOGIC; + SIGNAL wire_nll10110l_dataout : STD_LOGIC; + SIGNAL wire_nll10110O_dataout : STD_LOGIC; + SIGNAL wire_nll10111i_dataout : STD_LOGIC; + SIGNAL wire_nll10111l_dataout : STD_LOGIC; + SIGNAL wire_nll10111O_dataout : STD_LOGIC; + SIGNAL wire_nll1011i_dataout : STD_LOGIC; + SIGNAL wire_nll1011ii_dataout : STD_LOGIC; + SIGNAL wire_nll1011il_dataout : STD_LOGIC; + SIGNAL wire_nll1011iO_dataout : STD_LOGIC; + SIGNAL wire_nll1011l_dataout : STD_LOGIC; + SIGNAL wire_nll1011li_dataout : STD_LOGIC; + SIGNAL wire_nll1011ll_dataout : STD_LOGIC; + SIGNAL wire_nll1011lO_dataout : STD_LOGIC; + SIGNAL wire_nll1011O_dataout : STD_LOGIC; + SIGNAL wire_nll1011Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1011Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1011OO_dataout : STD_LOGIC; + SIGNAL wire_nll101i0i_dataout : STD_LOGIC; + SIGNAL wire_nll101i0l_dataout : STD_LOGIC; + SIGNAL wire_nll101i0O_dataout : STD_LOGIC; + SIGNAL wire_nll101i1i_dataout : STD_LOGIC; + SIGNAL wire_nll101i1l_dataout : STD_LOGIC; + SIGNAL wire_nll101i1O_dataout : STD_LOGIC; + SIGNAL wire_nll101ii_dataout : STD_LOGIC; + SIGNAL wire_nll101iii_dataout : STD_LOGIC; + SIGNAL wire_nll101iil_dataout : STD_LOGIC; + SIGNAL wire_nll101iiO_dataout : STD_LOGIC; + SIGNAL wire_nll101il_dataout : STD_LOGIC; + SIGNAL wire_nll101ili_dataout : STD_LOGIC; + SIGNAL wire_nll101ill_dataout : STD_LOGIC; + SIGNAL wire_nll101ilO_dataout : STD_LOGIC; + SIGNAL wire_nll101iO_dataout : STD_LOGIC; + SIGNAL wire_nll101iOi_dataout : STD_LOGIC; + SIGNAL wire_nll101iOl_dataout : STD_LOGIC; + SIGNAL wire_nll101iOO_dataout : STD_LOGIC; + SIGNAL wire_nll101l0i_dataout : STD_LOGIC; + SIGNAL wire_nll101l0l_dataout : STD_LOGIC; + SIGNAL wire_nll101l0O_dataout : STD_LOGIC; + SIGNAL wire_nll101l1i_dataout : STD_LOGIC; + SIGNAL wire_nll101l1l_dataout : STD_LOGIC; + SIGNAL wire_nll101l1O_dataout : STD_LOGIC; + SIGNAL wire_nll101li_dataout : STD_LOGIC; + SIGNAL wire_nll101lii_dataout : STD_LOGIC; + SIGNAL wire_nll101lil_dataout : STD_LOGIC; + SIGNAL wire_nll101liO_dataout : STD_LOGIC; + SIGNAL wire_nll101ll_dataout : STD_LOGIC; + SIGNAL wire_nll101lli_dataout : STD_LOGIC; + SIGNAL wire_nll101lll_dataout : STD_LOGIC; + SIGNAL wire_nll101llO_dataout : STD_LOGIC; + SIGNAL wire_nll101lO_dataout : STD_LOGIC; + SIGNAL wire_nll101lOi_dataout : STD_LOGIC; + SIGNAL wire_nll101lOl_dataout : STD_LOGIC; + SIGNAL wire_nll101lOO_dataout : STD_LOGIC; + SIGNAL wire_nll101O0i_dataout : STD_LOGIC; + SIGNAL wire_nll101O0l_dataout : STD_LOGIC; + SIGNAL wire_nll101O0O_dataout : STD_LOGIC; + SIGNAL wire_nll101O1i_dataout : STD_LOGIC; + SIGNAL wire_nll101O1l_dataout : STD_LOGIC; + SIGNAL wire_nll101O1O_dataout : STD_LOGIC; + SIGNAL wire_nll101Oi_dataout : STD_LOGIC; + SIGNAL wire_nll101Oii_dataout : STD_LOGIC; + SIGNAL wire_nll101Oil_dataout : STD_LOGIC; + SIGNAL wire_nll101OiO_dataout : STD_LOGIC; + SIGNAL wire_nll101Ol_dataout : STD_LOGIC; + SIGNAL wire_nll101Oli_dataout : STD_LOGIC; + SIGNAL wire_nll101Oll_dataout : STD_LOGIC; + SIGNAL wire_nll101OlO_dataout : STD_LOGIC; + SIGNAL wire_nll101OO_dataout : STD_LOGIC; + SIGNAL wire_nll101OOi_dataout : STD_LOGIC; + SIGNAL wire_nll101OOl_dataout : STD_LOGIC; + SIGNAL wire_nll101OOO_dataout : STD_LOGIC; + SIGNAL wire_nll10i0i_dataout : STD_LOGIC; + SIGNAL wire_nll10i0l_dataout : STD_LOGIC; + SIGNAL wire_nll10i0O_dataout : STD_LOGIC; + SIGNAL wire_nll10i1i_dataout : STD_LOGIC; + SIGNAL wire_nll10i1l_dataout : STD_LOGIC; + SIGNAL wire_nll10i1O_dataout : STD_LOGIC; + SIGNAL wire_nll10iii_dataout : STD_LOGIC; + SIGNAL wire_nll10iil_dataout : STD_LOGIC; + SIGNAL wire_nll10iiO_dataout : STD_LOGIC; + SIGNAL wire_nll10ili_dataout : STD_LOGIC; + SIGNAL wire_nll10ill_dataout : STD_LOGIC; + SIGNAL wire_nll10ilO_dataout : STD_LOGIC; + SIGNAL wire_nll10iOi_dataout : STD_LOGIC; + SIGNAL wire_nll10iOl_dataout : STD_LOGIC; + SIGNAL wire_nll10iOO_dataout : STD_LOGIC; + SIGNAL wire_nll10l0i_dataout : STD_LOGIC; + SIGNAL wire_nll10l0l_dataout : STD_LOGIC; + SIGNAL wire_nll10l0O_dataout : STD_LOGIC; + SIGNAL wire_nll10l1i_dataout : STD_LOGIC; + SIGNAL wire_nll10l1l_dataout : STD_LOGIC; + SIGNAL wire_nll10l1O_dataout : STD_LOGIC; + SIGNAL wire_nll10lii_dataout : STD_LOGIC; + SIGNAL wire_nll10lil_dataout : STD_LOGIC; + SIGNAL wire_nll10liO_dataout : STD_LOGIC; + SIGNAL wire_nll10lli_dataout : STD_LOGIC; + SIGNAL wire_nll10lll_dataout : STD_LOGIC; + SIGNAL wire_nll10llO_dataout : STD_LOGIC; + SIGNAL wire_nll10lOi_dataout : STD_LOGIC; + SIGNAL wire_nll10lOl_dataout : STD_LOGIC; + SIGNAL wire_nll10lOO_dataout : STD_LOGIC; + SIGNAL wire_nll10O0i_dataout : STD_LOGIC; + SIGNAL wire_nll10O0l_dataout : STD_LOGIC; + SIGNAL wire_nll10O0O_dataout : STD_LOGIC; + SIGNAL wire_nll10O1i_dataout : STD_LOGIC; + SIGNAL wire_nll10O1l_dataout : STD_LOGIC; + SIGNAL wire_nll10O1O_dataout : STD_LOGIC; + SIGNAL wire_nll10Oii_dataout : STD_LOGIC; + SIGNAL wire_nll10Oil_dataout : STD_LOGIC; + SIGNAL wire_nll10OiO_dataout : STD_LOGIC; + SIGNAL wire_nll10Oli_dataout : STD_LOGIC; + SIGNAL wire_nll10Oll_dataout : STD_LOGIC; + SIGNAL wire_nll10OlO_dataout : STD_LOGIC; + SIGNAL wire_nll10OOi_dataout : STD_LOGIC; + SIGNAL wire_nll10OOl_dataout : STD_LOGIC; + SIGNAL wire_nll10OOO_dataout : STD_LOGIC; + SIGNAL wire_nll1100i_dataout : STD_LOGIC; + SIGNAL wire_nll1100l_dataout : STD_LOGIC; + SIGNAL wire_nll1100O_dataout : STD_LOGIC; + SIGNAL wire_nll1101i_dataout : STD_LOGIC; + SIGNAL wire_nll1101l_dataout : STD_LOGIC; + SIGNAL wire_nll1101O_dataout : STD_LOGIC; + SIGNAL wire_nll110ii_dataout : STD_LOGIC; + SIGNAL wire_nll110il_dataout : STD_LOGIC; + SIGNAL wire_nll110iO_dataout : STD_LOGIC; + SIGNAL wire_nll110li_dataout : STD_LOGIC; + SIGNAL wire_nll110ll_dataout : STD_LOGIC; + SIGNAL wire_nll110lO_dataout : STD_LOGIC; + SIGNAL wire_nll110Oi_dataout : STD_LOGIC; + SIGNAL wire_nll110Ol_dataout : STD_LOGIC; + SIGNAL wire_nll110OO_dataout : STD_LOGIC; + SIGNAL wire_nll1110i_dataout : STD_LOGIC; + SIGNAL wire_nll1110l_dataout : STD_LOGIC; + SIGNAL wire_nll1110O_dataout : STD_LOGIC; + SIGNAL wire_nll1111i_dataout : STD_LOGIC; + SIGNAL wire_nll1111l_dataout : STD_LOGIC; + SIGNAL wire_nll1111O_dataout : STD_LOGIC; + SIGNAL wire_nll111ii_dataout : STD_LOGIC; + SIGNAL wire_nll111il_dataout : STD_LOGIC; + SIGNAL wire_nll111iO_dataout : STD_LOGIC; + SIGNAL wire_nll111li_dataout : STD_LOGIC; + SIGNAL wire_nll111ll_dataout : STD_LOGIC; + SIGNAL wire_nll111lO_dataout : STD_LOGIC; + SIGNAL wire_nll111Oi_dataout : STD_LOGIC; + SIGNAL wire_nll111Ol_dataout : STD_LOGIC; + SIGNAL wire_nll111OO_dataout : STD_LOGIC; + SIGNAL wire_nll11i0i_dataout : STD_LOGIC; + SIGNAL wire_nll11i0l_dataout : STD_LOGIC; + SIGNAL wire_nll11i0O_dataout : STD_LOGIC; + SIGNAL wire_nll11i1i_dataout : STD_LOGIC; + SIGNAL wire_nll11i1l_dataout : STD_LOGIC; + SIGNAL wire_nll11i1O_dataout : STD_LOGIC; + SIGNAL wire_nll11iii_dataout : STD_LOGIC; + SIGNAL wire_nll11iil_dataout : STD_LOGIC; + SIGNAL wire_nll11iiO_dataout : STD_LOGIC; + SIGNAL wire_nll11ili_dataout : STD_LOGIC; + SIGNAL wire_nll11ill_dataout : STD_LOGIC; + SIGNAL wire_nll11ilO_dataout : STD_LOGIC; + SIGNAL wire_nll11iOi_dataout : STD_LOGIC; + SIGNAL wire_nll11iOl_dataout : STD_LOGIC; + SIGNAL wire_nll11iOO_dataout : STD_LOGIC; + SIGNAL wire_nll11l0i_dataout : STD_LOGIC; + SIGNAL wire_nll11l0l_dataout : STD_LOGIC; + SIGNAL wire_nll11l0O_dataout : STD_LOGIC; + SIGNAL wire_nll11l1i_dataout : STD_LOGIC; + SIGNAL wire_nll11l1l_dataout : STD_LOGIC; + SIGNAL wire_nll11l1O_dataout : STD_LOGIC; + SIGNAL wire_nll11lii_dataout : STD_LOGIC; + SIGNAL wire_nll11lil_dataout : STD_LOGIC; + SIGNAL wire_nll11liO_dataout : STD_LOGIC; + SIGNAL wire_nll11lli_dataout : STD_LOGIC; + SIGNAL wire_nll11lll_dataout : STD_LOGIC; + SIGNAL wire_nll11llO_dataout : STD_LOGIC; + SIGNAL wire_nll11lOi_dataout : STD_LOGIC; + SIGNAL wire_nll11lOl_dataout : STD_LOGIC; + SIGNAL wire_nll11lOO_dataout : STD_LOGIC; + SIGNAL wire_nll11O0i_dataout : STD_LOGIC; + SIGNAL wire_nll11O0l_dataout : STD_LOGIC; + SIGNAL wire_nll11O0O_dataout : STD_LOGIC; + SIGNAL wire_nll11O1i_dataout : STD_LOGIC; + SIGNAL wire_nll11O1l_dataout : STD_LOGIC; + SIGNAL wire_nll11O1O_dataout : STD_LOGIC; + SIGNAL wire_nll11Oii_dataout : STD_LOGIC; + SIGNAL wire_nll11Oil_dataout : STD_LOGIC; + SIGNAL wire_nll11OiO_dataout : STD_LOGIC; + SIGNAL wire_nll11Oli_dataout : STD_LOGIC; + SIGNAL wire_nll11Oll_dataout : STD_LOGIC; + SIGNAL wire_nll11OlO_dataout : STD_LOGIC; + SIGNAL wire_nll11OlOi_dataout : STD_LOGIC; + SIGNAL wire_nll11OlOl_dataout : STD_LOGIC; + SIGNAL wire_nll11OlOO_dataout : STD_LOGIC; + SIGNAL wire_nll11OO0i_dataout : STD_LOGIC; + SIGNAL wire_nll11OO0l_dataout : STD_LOGIC; + SIGNAL wire_nll11OO0O_dataout : STD_LOGIC; + SIGNAL wire_nll11OO1i_dataout : STD_LOGIC; + SIGNAL wire_nll11OO1l_dataout : STD_LOGIC; + SIGNAL wire_nll11OO1O_dataout : STD_LOGIC; + SIGNAL wire_nll11OOi_dataout : STD_LOGIC; + SIGNAL wire_nll11OOii_dataout : STD_LOGIC; + SIGNAL wire_nll11OOil_dataout : STD_LOGIC; + SIGNAL wire_nll11OOiO_dataout : STD_LOGIC; + SIGNAL wire_nll11OOl_dataout : STD_LOGIC; + SIGNAL wire_nll11OOli_dataout : STD_LOGIC; + SIGNAL wire_nll11OOll_dataout : STD_LOGIC; + SIGNAL wire_nll11OOlO_dataout : STD_LOGIC; + SIGNAL wire_nll11OOO_dataout : STD_LOGIC; + SIGNAL wire_nll11OOOi_dataout : STD_LOGIC; + SIGNAL wire_nll11OOOl_dataout : STD_LOGIC; + SIGNAL wire_nll11OOOO_dataout : STD_LOGIC; + SIGNAL wire_nll1i00i_dataout : STD_LOGIC; + SIGNAL wire_nll1i00l_dataout : STD_LOGIC; + SIGNAL wire_nll1i00O_dataout : STD_LOGIC; + SIGNAL wire_nll1i01i_dataout : STD_LOGIC; + SIGNAL wire_nll1i01l_dataout : STD_LOGIC; + SIGNAL wire_nll1i01O_dataout : STD_LOGIC; + SIGNAL wire_nll1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nll1i0il_dataout : STD_LOGIC; + SIGNAL wire_nll1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nll1i0li_dataout : STD_LOGIC; + SIGNAL wire_nll1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nll1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nll1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nll1i10i_dataout : STD_LOGIC; + SIGNAL wire_nll1i10l_dataout : STD_LOGIC; + SIGNAL wire_nll1i10O_dataout : STD_LOGIC; + SIGNAL wire_nll1i11i_dataout : STD_LOGIC; + SIGNAL wire_nll1i11l_dataout : STD_LOGIC; + SIGNAL wire_nll1i11O_dataout : STD_LOGIC; + SIGNAL wire_nll1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1i1il_dataout : STD_LOGIC; + SIGNAL wire_nll1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1i1li_dataout : STD_LOGIC; + SIGNAL wire_nll1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nll1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nll1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nll1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nll1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nll1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nll1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nll1iiii_dataout : STD_LOGIC; + SIGNAL wire_nll1iiil_dataout : STD_LOGIC; + SIGNAL wire_nll1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nll1iili_dataout : STD_LOGIC; + SIGNAL wire_nll1iill_dataout : STD_LOGIC; + SIGNAL wire_nll1iilO_dataout : STD_LOGIC; + SIGNAL wire_nll1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nll1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nll1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nll1il0i_dataout : STD_LOGIC; + SIGNAL wire_nll1il0l_dataout : STD_LOGIC; + SIGNAL wire_nll1il0O_dataout : STD_LOGIC; + SIGNAL wire_nll1il1i_dataout : STD_LOGIC; + SIGNAL wire_nll1il1l_dataout : STD_LOGIC; + SIGNAL wire_nll1il1O_dataout : STD_LOGIC; + SIGNAL wire_nll1ilii_dataout : STD_LOGIC; + SIGNAL wire_nll1ilil_dataout : STD_LOGIC; + SIGNAL wire_nll1iliO_dataout : STD_LOGIC; + SIGNAL wire_nll1illi_dataout : STD_LOGIC; + SIGNAL wire_nll1illl_dataout : STD_LOGIC; + SIGNAL wire_nll1illO_dataout : STD_LOGIC; + SIGNAL wire_nll1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nll1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nll1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nll1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nll1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nll1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nll1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nll1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nll1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nll1iOii_dataout : STD_LOGIC; + SIGNAL wire_nll1iOil_dataout : STD_LOGIC; + SIGNAL wire_nll1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nll1iOli_dataout : STD_LOGIC; + SIGNAL wire_nll1iOll_dataout : STD_LOGIC; + SIGNAL wire_nll1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nll1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nll1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nll1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nll1l00i_dataout : STD_LOGIC; + SIGNAL wire_nll1l00l_dataout : STD_LOGIC; + SIGNAL wire_nll1l00O_dataout : STD_LOGIC; + SIGNAL wire_nll1l01i_dataout : STD_LOGIC; + SIGNAL wire_nll1l01l_dataout : STD_LOGIC; + SIGNAL wire_nll1l01O_dataout : STD_LOGIC; + SIGNAL wire_nll1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nll1l0il_dataout : STD_LOGIC; + SIGNAL wire_nll1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nll1l0li_dataout : STD_LOGIC; + SIGNAL wire_nll1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nll1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nll1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nll1l10i_dataout : STD_LOGIC; + SIGNAL wire_nll1l10l_dataout : STD_LOGIC; + SIGNAL wire_nll1l10O_dataout : STD_LOGIC; + SIGNAL wire_nll1l11i_dataout : STD_LOGIC; + SIGNAL wire_nll1l11l_dataout : STD_LOGIC; + SIGNAL wire_nll1l11O_dataout : STD_LOGIC; + SIGNAL wire_nll1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1l1il_dataout : STD_LOGIC; + SIGNAL wire_nll1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1l1li_dataout : STD_LOGIC; + SIGNAL wire_nll1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nll1li0i_dataout : STD_LOGIC; + SIGNAL wire_nll1li0l_dataout : STD_LOGIC; + SIGNAL wire_nll1li0O_dataout : STD_LOGIC; + SIGNAL wire_nll1li1i_dataout : STD_LOGIC; + SIGNAL wire_nll1li1l_dataout : STD_LOGIC; + SIGNAL wire_nll1li1O_dataout : STD_LOGIC; + SIGNAL wire_nll1liii_dataout : STD_LOGIC; + SIGNAL wire_nll1liil_dataout : STD_LOGIC; + SIGNAL wire_nll1liiO_dataout : STD_LOGIC; + SIGNAL wire_nll1lili_dataout : STD_LOGIC; + SIGNAL wire_nll1lill_dataout : STD_LOGIC; + SIGNAL wire_nll1lilO_dataout : STD_LOGIC; + SIGNAL wire_nll1liOi_dataout : STD_LOGIC; + SIGNAL wire_nll1liOl_dataout : STD_LOGIC; + SIGNAL wire_nll1liOO_dataout : STD_LOGIC; + SIGNAL wire_nll1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nll1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nll1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nll1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nll1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nll1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nll1llii_dataout : STD_LOGIC; + SIGNAL wire_nll1llil_dataout : STD_LOGIC; + SIGNAL wire_nll1lliO_dataout : STD_LOGIC; + SIGNAL wire_nll1llli_dataout : STD_LOGIC; + SIGNAL wire_nll1llll_dataout : STD_LOGIC; + SIGNAL wire_nll1lllO_dataout : STD_LOGIC; + SIGNAL wire_nll1llOi_dataout : STD_LOGIC; + SIGNAL wire_nll1llOl_dataout : STD_LOGIC; + SIGNAL wire_nll1llOO_dataout : STD_LOGIC; + SIGNAL wire_nll1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nll1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nll1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nll1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nll1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nll1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nll1lOii_dataout : STD_LOGIC; + SIGNAL wire_nll1lOil_dataout : STD_LOGIC; + SIGNAL wire_nll1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nll1lOli_dataout : STD_LOGIC; + SIGNAL wire_nll1lOll_dataout : STD_LOGIC; + SIGNAL wire_nll1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nll1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nll1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nll1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nll1O00i_dataout : STD_LOGIC; + SIGNAL wire_nll1O00l_dataout : STD_LOGIC; + SIGNAL wire_nll1O00O_dataout : STD_LOGIC; + SIGNAL wire_nll1O01i_dataout : STD_LOGIC; + SIGNAL wire_nll1O01l_dataout : STD_LOGIC; + SIGNAL wire_nll1O01O_dataout : STD_LOGIC; + SIGNAL wire_nll1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nll1O0il_dataout : STD_LOGIC; + SIGNAL wire_nll1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nll1O0li_dataout : STD_LOGIC; + SIGNAL wire_nll1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nll1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nll1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nll1O10i_dataout : STD_LOGIC; + SIGNAL wire_nll1O10l_dataout : STD_LOGIC; + SIGNAL wire_nll1O10O_dataout : STD_LOGIC; + SIGNAL wire_nll1O11i_dataout : STD_LOGIC; + SIGNAL wire_nll1O11l_dataout : STD_LOGIC; + SIGNAL wire_nll1O11O_dataout : STD_LOGIC; + SIGNAL wire_nll1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nll1O1il_dataout : STD_LOGIC; + SIGNAL wire_nll1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nll1O1li_dataout : STD_LOGIC; + SIGNAL wire_nll1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nll1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nll1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nll1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nll1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nll1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nll1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nll1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nll1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nll1Oili_dataout : STD_LOGIC; + SIGNAL wire_nll1Oill_dataout : STD_LOGIC; + SIGNAL wire_nll1OilO_dataout : STD_LOGIC; + SIGNAL wire_nll1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nll1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nll1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nll1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nll1Olii_dataout : STD_LOGIC; + SIGNAL wire_nll1Olil_dataout : STD_LOGIC; + SIGNAL wire_nll1OliO_dataout : STD_LOGIC; + SIGNAL wire_nll1Olli_dataout : STD_LOGIC; + SIGNAL wire_nll1Olll_dataout : STD_LOGIC; + SIGNAL wire_nll1OllO_dataout : STD_LOGIC; + SIGNAL wire_nll1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nll1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nll1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nll1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nll1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nll1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nll1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nll1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nll1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nll1OOii_dataout : STD_LOGIC; + SIGNAL wire_nll1OOil_dataout : STD_LOGIC; + SIGNAL wire_nll1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nll1OOli_dataout : STD_LOGIC; + SIGNAL wire_nll1OOll_dataout : STD_LOGIC; + SIGNAL wire_nll1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nll1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nll1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nll1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0000i_dataout : STD_LOGIC; + SIGNAL wire_nlli0000l_dataout : STD_LOGIC; + SIGNAL wire_nlli0000O_dataout : STD_LOGIC; + SIGNAL wire_nlli0001i_dataout : STD_LOGIC; + SIGNAL wire_nlli0001l_dataout : STD_LOGIC; + SIGNAL wire_nlli0001O_dataout : STD_LOGIC; + SIGNAL wire_nlli000i_dataout : STD_LOGIC; + SIGNAL wire_nlli000ii_dataout : STD_LOGIC; + SIGNAL wire_nlli000il_dataout : STD_LOGIC; + SIGNAL wire_nlli000iO_dataout : STD_LOGIC; + SIGNAL wire_nlli000l_dataout : STD_LOGIC; + SIGNAL wire_nlli000li_dataout : STD_LOGIC; + SIGNAL wire_nlli000ll_dataout : STD_LOGIC; + SIGNAL wire_nlli000lO_dataout : STD_LOGIC; + SIGNAL wire_nlli000O_dataout : STD_LOGIC; + SIGNAL wire_nlli000Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli000Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli000OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0010i_dataout : STD_LOGIC; + SIGNAL wire_nlli0010l_dataout : STD_LOGIC; + SIGNAL wire_nlli0010O_dataout : STD_LOGIC; + SIGNAL wire_nlli0011i_dataout : STD_LOGIC; + SIGNAL wire_nlli0011l_dataout : STD_LOGIC; + SIGNAL wire_nlli0011O_dataout : STD_LOGIC; + SIGNAL wire_nlli001i_dataout : STD_LOGIC; + SIGNAL wire_nlli001ii_dataout : STD_LOGIC; + SIGNAL wire_nlli001il_dataout : STD_LOGIC; + SIGNAL wire_nlli001iO_dataout : STD_LOGIC; + SIGNAL wire_nlli001l_dataout : STD_LOGIC; + SIGNAL wire_nlli001li_dataout : STD_LOGIC; + SIGNAL wire_nlli001ll_dataout : STD_LOGIC; + SIGNAL wire_nlli001lO_dataout : STD_LOGIC; + SIGNAL wire_nlli001O_dataout : STD_LOGIC; + SIGNAL wire_nlli001Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli001Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli001OO_dataout : STD_LOGIC; + SIGNAL wire_nlli00i0i_dataout : STD_LOGIC; + SIGNAL wire_nlli00i0l_dataout : STD_LOGIC; + SIGNAL wire_nlli00i0O_dataout : STD_LOGIC; + SIGNAL wire_nlli00i1i_dataout : STD_LOGIC; + SIGNAL wire_nlli00i1l_dataout : STD_LOGIC; + SIGNAL wire_nlli00i1O_dataout : STD_LOGIC; + SIGNAL wire_nlli00ii_dataout : STD_LOGIC; + SIGNAL wire_nlli00iii_dataout : STD_LOGIC; + SIGNAL wire_nlli00iil_dataout : STD_LOGIC; + SIGNAL wire_nlli00iiO_dataout : STD_LOGIC; + SIGNAL wire_nlli00il_dataout : STD_LOGIC; + SIGNAL wire_nlli00ili_dataout : STD_LOGIC; + SIGNAL wire_nlli00ill_dataout : STD_LOGIC; + SIGNAL wire_nlli00ilO_dataout : STD_LOGIC; + SIGNAL wire_nlli00iO_dataout : STD_LOGIC; + SIGNAL wire_nlli00iOi_dataout : STD_LOGIC; + SIGNAL wire_nlli00iOl_dataout : STD_LOGIC; + SIGNAL wire_nlli00iOO_dataout : STD_LOGIC; + SIGNAL wire_nlli00l0i_dataout : STD_LOGIC; + SIGNAL wire_nlli00l0l_dataout : STD_LOGIC; + SIGNAL wire_nlli00l0O_dataout : STD_LOGIC; + SIGNAL wire_nlli00l1i_dataout : STD_LOGIC; + SIGNAL wire_nlli00l1l_dataout : STD_LOGIC; + SIGNAL wire_nlli00l1O_dataout : STD_LOGIC; + SIGNAL wire_nlli00li_dataout : STD_LOGIC; + SIGNAL wire_nlli00ll_dataout : STD_LOGIC; + SIGNAL wire_nlli00lO_dataout : STD_LOGIC; + SIGNAL wire_nlli00lOO_dataout : STD_LOGIC; + SIGNAL wire_nlli00O0i_dataout : STD_LOGIC; + SIGNAL wire_nlli00O0l_dataout : STD_LOGIC; + SIGNAL wire_nlli00O0O_dataout : STD_LOGIC; + SIGNAL wire_nlli00O1i_dataout : STD_LOGIC; + SIGNAL wire_nlli00O1l_dataout : STD_LOGIC; + SIGNAL wire_nlli00O1O_dataout : STD_LOGIC; + SIGNAL wire_nlli00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli00Oii_dataout : STD_LOGIC; + SIGNAL wire_nlli00Oil_dataout : STD_LOGIC; + SIGNAL wire_nlli00OiO_dataout : STD_LOGIC; + SIGNAL wire_nlli00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli00Oli_dataout : STD_LOGIC; + SIGNAL wire_nlli00OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0100i_dataout : STD_LOGIC; + SIGNAL wire_nlli0100l_dataout : STD_LOGIC; + SIGNAL wire_nlli0100O_dataout : STD_LOGIC; + SIGNAL wire_nlli0101i_dataout : STD_LOGIC; + SIGNAL wire_nlli0101l_dataout : STD_LOGIC; + SIGNAL wire_nlli0101O_dataout : STD_LOGIC; + SIGNAL wire_nlli010i_dataout : STD_LOGIC; + SIGNAL wire_nlli010ii_dataout : STD_LOGIC; + SIGNAL wire_nlli010il_dataout : STD_LOGIC; + SIGNAL wire_nlli010iO_dataout : STD_LOGIC; + SIGNAL wire_nlli010l_dataout : STD_LOGIC; + SIGNAL wire_nlli010li_dataout : STD_LOGIC; + SIGNAL wire_nlli010ll_dataout : STD_LOGIC; + SIGNAL wire_nlli010lO_dataout : STD_LOGIC; + SIGNAL wire_nlli010O_dataout : STD_LOGIC; + SIGNAL wire_nlli010Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli010Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli010OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0110i_dataout : STD_LOGIC; + SIGNAL wire_nlli0110l_dataout : STD_LOGIC; + SIGNAL wire_nlli0110O_dataout : STD_LOGIC; + SIGNAL wire_nlli0111i_dataout : STD_LOGIC; + SIGNAL wire_nlli0111l_dataout : STD_LOGIC; + SIGNAL wire_nlli0111O_dataout : STD_LOGIC; + SIGNAL wire_nlli011i_dataout : STD_LOGIC; + SIGNAL wire_nlli011ii_dataout : STD_LOGIC; + SIGNAL wire_nlli011il_dataout : STD_LOGIC; + SIGNAL wire_nlli011iO_dataout : STD_LOGIC; + SIGNAL wire_nlli011l_dataout : STD_LOGIC; + SIGNAL wire_nlli011li_dataout : STD_LOGIC; + SIGNAL wire_nlli011ll_dataout : STD_LOGIC; + SIGNAL wire_nlli011lO_dataout : STD_LOGIC; + SIGNAL wire_nlli011O_dataout : STD_LOGIC; + SIGNAL wire_nlli011Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli011Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli011OO_dataout : STD_LOGIC; + SIGNAL wire_nlli01i0i_dataout : STD_LOGIC; + SIGNAL wire_nlli01i0l_dataout : STD_LOGIC; + SIGNAL wire_nlli01i0O_dataout : STD_LOGIC; + SIGNAL wire_nlli01i1i_dataout : STD_LOGIC; + SIGNAL wire_nlli01i1l_dataout : STD_LOGIC; + SIGNAL wire_nlli01i1O_dataout : STD_LOGIC; + SIGNAL wire_nlli01ii_dataout : STD_LOGIC; + SIGNAL wire_nlli01iii_dataout : STD_LOGIC; + SIGNAL wire_nlli01iil_dataout : STD_LOGIC; + SIGNAL wire_nlli01iiO_dataout : STD_LOGIC; + SIGNAL wire_nlli01il_dataout : STD_LOGIC; + SIGNAL wire_nlli01ili_dataout : STD_LOGIC; + SIGNAL wire_nlli01ill_dataout : STD_LOGIC; + SIGNAL wire_nlli01ilO_dataout : STD_LOGIC; + SIGNAL wire_nlli01iO_dataout : STD_LOGIC; + SIGNAL wire_nlli01iOi_dataout : STD_LOGIC; + SIGNAL wire_nlli01iOl_dataout : STD_LOGIC; + SIGNAL wire_nlli01iOO_dataout : STD_LOGIC; + SIGNAL wire_nlli01l0i_dataout : STD_LOGIC; + SIGNAL wire_nlli01l0l_dataout : STD_LOGIC; + SIGNAL wire_nlli01l0O_dataout : STD_LOGIC; + SIGNAL wire_nlli01l1i_dataout : STD_LOGIC; + SIGNAL wire_nlli01l1O_dataout : STD_LOGIC; + SIGNAL wire_nlli01li_dataout : STD_LOGIC; + SIGNAL wire_nlli01lii_dataout : STD_LOGIC; + SIGNAL wire_nlli01lil_dataout : STD_LOGIC; + SIGNAL wire_nlli01liO_dataout : STD_LOGIC; + SIGNAL wire_nlli01ll_dataout : STD_LOGIC; + SIGNAL wire_nlli01lli_dataout : STD_LOGIC; + SIGNAL wire_nlli01lll_dataout : STD_LOGIC; + SIGNAL wire_nlli01llO_dataout : STD_LOGIC; + SIGNAL wire_nlli01lO_dataout : STD_LOGIC; + SIGNAL wire_nlli01lOi_dataout : STD_LOGIC; + SIGNAL wire_nlli01lOl_dataout : STD_LOGIC; + SIGNAL wire_nlli01lOO_dataout : STD_LOGIC; + SIGNAL wire_nlli01O0i_dataout : STD_LOGIC; + SIGNAL wire_nlli01O0l_dataout : STD_LOGIC; + SIGNAL wire_nlli01O0O_dataout : STD_LOGIC; + SIGNAL wire_nlli01O1i_dataout : STD_LOGIC; + SIGNAL wire_nlli01O1l_dataout : STD_LOGIC; + SIGNAL wire_nlli01O1O_dataout : STD_LOGIC; + SIGNAL wire_nlli01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli01Oii_dataout : STD_LOGIC; + SIGNAL wire_nlli01Oil_dataout : STD_LOGIC; + SIGNAL wire_nlli01OiO_dataout : STD_LOGIC; + SIGNAL wire_nlli01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli01OO_dataout : STD_LOGIC; + SIGNAL wire_nlli01OOi_dataout : STD_LOGIC; + SIGNAL wire_nlli01OOl_dataout : STD_LOGIC; + SIGNAL wire_nlli01OOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0i10i_dataout : STD_LOGIC; + SIGNAL wire_nlli0i10l_dataout : STD_LOGIC; + SIGNAL wire_nlli0i10O_dataout : STD_LOGIC; + SIGNAL wire_nlli0i11l_dataout : STD_LOGIC; + SIGNAL wire_nlli0i11O_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1il_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1li_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlli0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0iii_dataout : STD_LOGIC; + SIGNAL wire_nlli0iil_dataout : STD_LOGIC; + SIGNAL wire_nlli0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlli0ili_dataout : STD_LOGIC; + SIGNAL wire_nlli0ill_dataout : STD_LOGIC; + SIGNAL wire_nlli0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlli0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOii_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOil_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOli_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOll_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0l00i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l00l_dataout : STD_LOGIC; + SIGNAL wire_nlli0l00O_dataout : STD_LOGIC; + SIGNAL wire_nlli0l01i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l01l_dataout : STD_LOGIC; + SIGNAL wire_nlli0l01O_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0il_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0li_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0l10i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l10l_dataout : STD_LOGIC; + SIGNAL wire_nlli0l10O_dataout : STD_LOGIC; + SIGNAL wire_nlli0l11i_dataout : STD_LOGIC; + SIGNAL wire_nlli0l11l_dataout : STD_LOGIC; + SIGNAL wire_nlli0l11O_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1il_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1li_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0li0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0li0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0li0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0li1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0li1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0li1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0lii_dataout : STD_LOGIC; + SIGNAL wire_nlli0liii_dataout : STD_LOGIC; + SIGNAL wire_nlli0liil_dataout : STD_LOGIC; + SIGNAL wire_nlli0liiO_dataout : STD_LOGIC; + SIGNAL wire_nlli0lil_dataout : STD_LOGIC; + SIGNAL wire_nlli0lili_dataout : STD_LOGIC; + SIGNAL wire_nlli0lill_dataout : STD_LOGIC; + SIGNAL wire_nlli0lilO_dataout : STD_LOGIC; + SIGNAL wire_nlli0liO_dataout : STD_LOGIC; + SIGNAL wire_nlli0liOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0liOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0liOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0lli_dataout : STD_LOGIC; + SIGNAL wire_nlli0llii_dataout : STD_LOGIC; + SIGNAL wire_nlli0llil_dataout : STD_LOGIC; + SIGNAL wire_nlli0lliO_dataout : STD_LOGIC; + SIGNAL wire_nlli0lll_dataout : STD_LOGIC; + SIGNAL wire_nlli0llli_dataout : STD_LOGIC; + SIGNAL wire_nlli0llll_dataout : STD_LOGIC; + SIGNAL wire_nlli0lllO_dataout : STD_LOGIC; + SIGNAL wire_nlli0llO_dataout : STD_LOGIC; + SIGNAL wire_nlli0llOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0llOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0llOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOii_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOil_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOli_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOll_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0O00i_dataout : STD_LOGIC; + SIGNAL wire_nlli0O00l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O00O_dataout : STD_LOGIC; + SIGNAL wire_nlli0O01i_dataout : STD_LOGIC; + SIGNAL wire_nlli0O01l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O01O_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0il_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0li_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0O10i_dataout : STD_LOGIC; + SIGNAL wire_nlli0O10l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O10O_dataout : STD_LOGIC; + SIGNAL wire_nlli0O11i_dataout : STD_LOGIC; + SIGNAL wire_nlli0O11l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O11O_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1il_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1li_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlli0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oili_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oill_dataout : STD_LOGIC; + SIGNAL wire_nlli0OilO_dataout : STD_LOGIC; + SIGNAL wire_nlli0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlli0Olii_dataout : STD_LOGIC; + SIGNAL wire_nlli0Olil_dataout : STD_LOGIC; + SIGNAL wire_nlli0OliO_dataout : STD_LOGIC; + SIGNAL wire_nlli0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlli0Olli_dataout : STD_LOGIC; + SIGNAL wire_nlli0Olll_dataout : STD_LOGIC; + SIGNAL wire_nlli0OllO_dataout : STD_LOGIC; + SIGNAL wire_nlli0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlli0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlli0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlli0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlli0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlli0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlli0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOii_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOil_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOli_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOll_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlli0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlli1000i_dataout : STD_LOGIC; + SIGNAL wire_nlli1000l_dataout : STD_LOGIC; + SIGNAL wire_nlli1000O_dataout : STD_LOGIC; + SIGNAL wire_nlli1001i_dataout : STD_LOGIC; + SIGNAL wire_nlli1001l_dataout : STD_LOGIC; + SIGNAL wire_nlli1001O_dataout : STD_LOGIC; + SIGNAL wire_nlli100i_dataout : STD_LOGIC; + SIGNAL wire_nlli100ii_dataout : STD_LOGIC; + SIGNAL wire_nlli100il_dataout : STD_LOGIC; + SIGNAL wire_nlli100iO_dataout : STD_LOGIC; + SIGNAL wire_nlli100l_dataout : STD_LOGIC; + SIGNAL wire_nlli100li_dataout : STD_LOGIC; + SIGNAL wire_nlli100ll_dataout : STD_LOGIC; + SIGNAL wire_nlli100lO_dataout : STD_LOGIC; + SIGNAL wire_nlli100O_dataout : STD_LOGIC; + SIGNAL wire_nlli100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli100Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli100OO_dataout : STD_LOGIC; + SIGNAL wire_nlli101i_dataout : STD_LOGIC; + SIGNAL wire_nlli101l_dataout : STD_LOGIC; + SIGNAL wire_nlli101lO_dataout : STD_LOGIC; + SIGNAL wire_nlli101O_dataout : STD_LOGIC; + SIGNAL wire_nlli101Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli101Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli101OO_dataout : STD_LOGIC; + SIGNAL wire_nlli10i0i_dataout : STD_LOGIC; + SIGNAL wire_nlli10i0l_dataout : STD_LOGIC; + SIGNAL wire_nlli10i0O_dataout : STD_LOGIC; + SIGNAL wire_nlli10i1i_dataout : STD_LOGIC; + SIGNAL wire_nlli10i1l_dataout : STD_LOGIC; + SIGNAL wire_nlli10i1O_dataout : STD_LOGIC; + SIGNAL wire_nlli10ii_dataout : STD_LOGIC; + SIGNAL wire_nlli10iii_dataout : STD_LOGIC; + SIGNAL wire_nlli10iil_dataout : STD_LOGIC; + SIGNAL wire_nlli10iiO_dataout : STD_LOGIC; + SIGNAL wire_nlli10il_dataout : STD_LOGIC; + SIGNAL wire_nlli10ili_dataout : STD_LOGIC; + SIGNAL wire_nlli10ill_dataout : STD_LOGIC; + SIGNAL wire_nlli10ilO_dataout : STD_LOGIC; + SIGNAL wire_nlli10iO_dataout : STD_LOGIC; + SIGNAL wire_nlli10iOi_dataout : STD_LOGIC; + SIGNAL wire_nlli10iOl_dataout : STD_LOGIC; + SIGNAL wire_nlli10iOO_dataout : STD_LOGIC; + SIGNAL wire_nlli10l0i_dataout : STD_LOGIC; + SIGNAL wire_nlli10l0l_dataout : STD_LOGIC; + SIGNAL wire_nlli10l0O_dataout : STD_LOGIC; + SIGNAL wire_nlli10l1i_dataout : STD_LOGIC; + SIGNAL wire_nlli10l1l_dataout : STD_LOGIC; + SIGNAL wire_nlli10l1O_dataout : STD_LOGIC; + SIGNAL wire_nlli10lii_dataout : STD_LOGIC; + SIGNAL wire_nlli10lil_dataout : STD_LOGIC; + SIGNAL wire_nlli10liO_dataout : STD_LOGIC; + SIGNAL wire_nlli10lli_dataout : STD_LOGIC; + SIGNAL wire_nlli10lll_dataout : STD_LOGIC; + SIGNAL wire_nlli10llO_dataout : STD_LOGIC; + SIGNAL wire_nlli10lOi_dataout : STD_LOGIC; + SIGNAL wire_nlli10lOl_dataout : STD_LOGIC; + SIGNAL wire_nlli10lOO_dataout : STD_LOGIC; + SIGNAL wire_nlli10O0i_dataout : STD_LOGIC; + SIGNAL wire_nlli10O0l_dataout : STD_LOGIC; + SIGNAL wire_nlli10O0O_dataout : STD_LOGIC; + SIGNAL wire_nlli10O1i_dataout : STD_LOGIC; + SIGNAL wire_nlli10O1l_dataout : STD_LOGIC; + SIGNAL wire_nlli10O1O_dataout : STD_LOGIC; + SIGNAL wire_nlli10Oii_dataout : STD_LOGIC; + SIGNAL wire_nlli10Oil_dataout : STD_LOGIC; + SIGNAL wire_nlli10OiO_dataout : STD_LOGIC; + SIGNAL wire_nlli10Oli_dataout : STD_LOGIC; + SIGNAL wire_nlli10Oll_dataout : STD_LOGIC; + SIGNAL wire_nlli10OlO_dataout : STD_LOGIC; + SIGNAL wire_nlli10OOi_dataout : STD_LOGIC; + SIGNAL wire_nlli10OOl_dataout : STD_LOGIC; + SIGNAL wire_nlli10OOO_dataout : STD_LOGIC; + SIGNAL wire_nlli110i_dataout : STD_LOGIC; + SIGNAL wire_nlli110ii_dataout : STD_LOGIC; + SIGNAL wire_nlli110il_dataout : STD_LOGIC; + SIGNAL wire_nlli110iO_dataout : STD_LOGIC; + SIGNAL wire_nlli110l_dataout : STD_LOGIC; + SIGNAL wire_nlli110O_dataout : STD_LOGIC; + SIGNAL wire_nlli1110i_dataout : STD_LOGIC; + SIGNAL wire_nlli1110l_dataout : STD_LOGIC; + SIGNAL wire_nlli1110O_dataout : STD_LOGIC; + SIGNAL wire_nlli1111i_dataout : STD_LOGIC; + SIGNAL wire_nlli1111l_dataout : STD_LOGIC; + SIGNAL wire_nlli1111O_dataout : STD_LOGIC; + SIGNAL wire_nlli111i_dataout : STD_LOGIC; + SIGNAL wire_nlli111ii_dataout : STD_LOGIC; + SIGNAL wire_nlli111il_dataout : STD_LOGIC; + SIGNAL wire_nlli111iO_dataout : STD_LOGIC; + SIGNAL wire_nlli111l_dataout : STD_LOGIC; + SIGNAL wire_nlli111li_dataout : STD_LOGIC; + SIGNAL wire_nlli111ll_dataout : STD_LOGIC; + SIGNAL wire_nlli111O_dataout : STD_LOGIC; + SIGNAL wire_nlli11i0i_dataout : STD_LOGIC; + SIGNAL wire_nlli11i1O_dataout : STD_LOGIC; + SIGNAL wire_nlli11ii_dataout : STD_LOGIC; + SIGNAL wire_nlli11il_dataout : STD_LOGIC; + SIGNAL wire_nlli11iO_dataout : STD_LOGIC; + SIGNAL wire_nlli11li_dataout : STD_LOGIC; + SIGNAL wire_nlli11ll_dataout : STD_LOGIC; + SIGNAL wire_nlli11lO_dataout : STD_LOGIC; + SIGNAL wire_nlli11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlli11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlli11OO_dataout : STD_LOGIC; + SIGNAL wire_nlli1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlli1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlli1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlli1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlli1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlli1lii_dataout : STD_LOGIC; + SIGNAL wire_nlli1lil_dataout : STD_LOGIC; + SIGNAL wire_nlli1liO_dataout : STD_LOGIC; + SIGNAL wire_nlli1lli_dataout : STD_LOGIC; + SIGNAL wire_nlli1lll_dataout : STD_LOGIC; + SIGNAL wire_nlli1llO_dataout : STD_LOGIC; + SIGNAL wire_nlli1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlli1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlli1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlli1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlli1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlli1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlli1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlli1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlli1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlli1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlli1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlli1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlli1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlli1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlli1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlli1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlli1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlli1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlli1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlli1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlli1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOii_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOil_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOli_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOll_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlli1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nllii000i_dataout : STD_LOGIC; + SIGNAL wire_nllii000l_dataout : STD_LOGIC; + SIGNAL wire_nllii000O_dataout : STD_LOGIC; + SIGNAL wire_nllii001i_dataout : STD_LOGIC; + SIGNAL wire_nllii001l_dataout : STD_LOGIC; + SIGNAL wire_nllii001O_dataout : STD_LOGIC; + SIGNAL wire_nllii00i_dataout : STD_LOGIC; + SIGNAL wire_nllii00ii_dataout : STD_LOGIC; + SIGNAL wire_nllii00il_dataout : STD_LOGIC; + SIGNAL wire_nllii00iO_dataout : STD_LOGIC; + SIGNAL wire_nllii00l_dataout : STD_LOGIC; + SIGNAL wire_nllii00li_dataout : STD_LOGIC; + SIGNAL wire_nllii00ll_dataout : STD_LOGIC; + SIGNAL wire_nllii00lO_dataout : STD_LOGIC; + SIGNAL wire_nllii00O_dataout : STD_LOGIC; + SIGNAL wire_nllii00Oi_dataout : STD_LOGIC; + SIGNAL wire_nllii00Ol_dataout : STD_LOGIC; + SIGNAL wire_nllii00OO_dataout : STD_LOGIC; + SIGNAL wire_nllii010i_dataout : STD_LOGIC; + SIGNAL wire_nllii010l_dataout : STD_LOGIC; + SIGNAL wire_nllii010O_dataout : STD_LOGIC; + SIGNAL wire_nllii011i_dataout : STD_LOGIC; + SIGNAL wire_nllii011l_dataout : STD_LOGIC; + SIGNAL wire_nllii011O_dataout : STD_LOGIC; + SIGNAL wire_nllii01i_dataout : STD_LOGIC; + SIGNAL wire_nllii01ii_dataout : STD_LOGIC; + SIGNAL wire_nllii01il_dataout : STD_LOGIC; + SIGNAL wire_nllii01iO_dataout : STD_LOGIC; + SIGNAL wire_nllii01l_dataout : STD_LOGIC; + SIGNAL wire_nllii01li_dataout : STD_LOGIC; + SIGNAL wire_nllii01ll_dataout : STD_LOGIC; + SIGNAL wire_nllii01lO_dataout : STD_LOGIC; + SIGNAL wire_nllii01O_dataout : STD_LOGIC; + SIGNAL wire_nllii01Oi_dataout : STD_LOGIC; + SIGNAL wire_nllii01Ol_dataout : STD_LOGIC; + SIGNAL wire_nllii01OO_dataout : STD_LOGIC; + SIGNAL wire_nllii0i0i_dataout : STD_LOGIC; + SIGNAL wire_nllii0i0l_dataout : STD_LOGIC; + SIGNAL wire_nllii0i0O_dataout : STD_LOGIC; + SIGNAL wire_nllii0i1i_dataout : STD_LOGIC; + SIGNAL wire_nllii0i1l_dataout : STD_LOGIC; + SIGNAL wire_nllii0i1O_dataout : STD_LOGIC; + SIGNAL wire_nllii0ii_dataout : STD_LOGIC; + SIGNAL wire_nllii0iii_dataout : STD_LOGIC; + SIGNAL wire_nllii0iil_dataout : STD_LOGIC; + SIGNAL wire_nllii0iiO_dataout : STD_LOGIC; + SIGNAL wire_nllii0il_dataout : STD_LOGIC; + SIGNAL wire_nllii0ili_dataout : STD_LOGIC; + SIGNAL wire_nllii0ill_dataout : STD_LOGIC; + SIGNAL wire_nllii0ilO_dataout : STD_LOGIC; + SIGNAL wire_nllii0iO_dataout : STD_LOGIC; + SIGNAL wire_nllii0iOi_dataout : STD_LOGIC; + SIGNAL wire_nllii0iOl_dataout : STD_LOGIC; + SIGNAL wire_nllii0iOO_dataout : STD_LOGIC; + SIGNAL wire_nllii0l0i_dataout : STD_LOGIC; + SIGNAL wire_nllii0l0l_dataout : STD_LOGIC; + SIGNAL wire_nllii0l0O_dataout : STD_LOGIC; + SIGNAL wire_nllii0l1i_dataout : STD_LOGIC; + SIGNAL wire_nllii0l1l_dataout : STD_LOGIC; + SIGNAL wire_nllii0l1O_dataout : STD_LOGIC; + SIGNAL wire_nllii0li_dataout : STD_LOGIC; + SIGNAL wire_nllii0lii_dataout : STD_LOGIC; + SIGNAL wire_nllii0lil_dataout : STD_LOGIC; + SIGNAL wire_nllii0liO_dataout : STD_LOGIC; + SIGNAL wire_nllii0ll_dataout : STD_LOGIC; + SIGNAL wire_nllii0lli_dataout : STD_LOGIC; + SIGNAL wire_nllii0lll_dataout : STD_LOGIC; + SIGNAL wire_nllii0llO_dataout : STD_LOGIC; + SIGNAL wire_nllii0lO_dataout : STD_LOGIC; + SIGNAL wire_nllii0lOi_dataout : STD_LOGIC; + SIGNAL wire_nllii0lOl_dataout : STD_LOGIC; + SIGNAL wire_nllii0lOO_dataout : STD_LOGIC; + SIGNAL wire_nllii0O0i_dataout : STD_LOGIC; + SIGNAL wire_nllii0O0l_dataout : STD_LOGIC; + SIGNAL wire_nllii0O0O_dataout : STD_LOGIC; + SIGNAL wire_nllii0O1i_dataout : STD_LOGIC; + SIGNAL wire_nllii0O1l_dataout : STD_LOGIC; + SIGNAL wire_nllii0O1O_dataout : STD_LOGIC; + SIGNAL wire_nllii0Oii_dataout : STD_LOGIC; + SIGNAL wire_nllii0Oil_dataout : STD_LOGIC; + SIGNAL wire_nllii0OOi_dataout : STD_LOGIC; + SIGNAL wire_nllii0OOl_dataout : STD_LOGIC; + SIGNAL wire_nllii100i_dataout : STD_LOGIC; + SIGNAL wire_nllii100l_dataout : STD_LOGIC; + SIGNAL wire_nllii100O_dataout : STD_LOGIC; + SIGNAL wire_nllii101i_dataout : STD_LOGIC; + SIGNAL wire_nllii101l_dataout : STD_LOGIC; + SIGNAL wire_nllii101O_dataout : STD_LOGIC; + SIGNAL wire_nllii10i_dataout : STD_LOGIC; + SIGNAL wire_nllii10ii_dataout : STD_LOGIC; + SIGNAL wire_nllii10il_dataout : STD_LOGIC; + SIGNAL wire_nllii10iO_dataout : STD_LOGIC; + SIGNAL wire_nllii10l_dataout : STD_LOGIC; + SIGNAL wire_nllii10li_dataout : STD_LOGIC; + SIGNAL wire_nllii10ll_dataout : STD_LOGIC; + SIGNAL wire_nllii10lO_dataout : STD_LOGIC; + SIGNAL wire_nllii10O_dataout : STD_LOGIC; + SIGNAL wire_nllii10Oi_dataout : STD_LOGIC; + SIGNAL wire_nllii10Ol_dataout : STD_LOGIC; + SIGNAL wire_nllii10OO_dataout : STD_LOGIC; + SIGNAL wire_nllii110i_dataout : STD_LOGIC; + SIGNAL wire_nllii110l_dataout : STD_LOGIC; + SIGNAL wire_nllii110O_dataout : STD_LOGIC; + SIGNAL wire_nllii111i_dataout : STD_LOGIC; + SIGNAL wire_nllii111l_dataout : STD_LOGIC; + SIGNAL wire_nllii111O_dataout : STD_LOGIC; + SIGNAL wire_nllii11i_dataout : STD_LOGIC; + SIGNAL wire_nllii11ii_dataout : STD_LOGIC; + SIGNAL wire_nllii11il_dataout : STD_LOGIC; + SIGNAL wire_nllii11iO_dataout : STD_LOGIC; + SIGNAL wire_nllii11l_dataout : STD_LOGIC; + SIGNAL wire_nllii11li_dataout : STD_LOGIC; + SIGNAL wire_nllii11ll_dataout : STD_LOGIC; + SIGNAL wire_nllii11lO_dataout : STD_LOGIC; + SIGNAL wire_nllii11O_dataout : STD_LOGIC; + SIGNAL wire_nllii11Oi_dataout : STD_LOGIC; + SIGNAL wire_nllii11Ol_dataout : STD_LOGIC; + SIGNAL wire_nllii1i0i_dataout : STD_LOGIC; + SIGNAL wire_nllii1i0l_dataout : STD_LOGIC; + SIGNAL wire_nllii1i0O_dataout : STD_LOGIC; + SIGNAL wire_nllii1i1i_dataout : STD_LOGIC; + SIGNAL wire_nllii1i1l_dataout : STD_LOGIC; + SIGNAL wire_nllii1i1O_dataout : STD_LOGIC; + SIGNAL wire_nllii1ii_dataout : STD_LOGIC; + SIGNAL wire_nllii1iii_dataout : STD_LOGIC; + SIGNAL wire_nllii1iil_dataout : STD_LOGIC; + SIGNAL wire_nllii1iiO_dataout : STD_LOGIC; + SIGNAL wire_nllii1il_dataout : STD_LOGIC; + SIGNAL wire_nllii1ili_dataout : STD_LOGIC; + SIGNAL wire_nllii1ill_dataout : STD_LOGIC; + SIGNAL wire_nllii1ilO_dataout : STD_LOGIC; + SIGNAL wire_nllii1iO_dataout : STD_LOGIC; + SIGNAL wire_nllii1iOi_dataout : STD_LOGIC; + SIGNAL wire_nllii1iOl_dataout : STD_LOGIC; + SIGNAL wire_nllii1iOO_dataout : STD_LOGIC; + SIGNAL wire_nllii1l0i_dataout : STD_LOGIC; + SIGNAL wire_nllii1l0l_dataout : STD_LOGIC; + SIGNAL wire_nllii1l0O_dataout : STD_LOGIC; + SIGNAL wire_nllii1l1i_dataout : STD_LOGIC; + SIGNAL wire_nllii1l1l_dataout : STD_LOGIC; + SIGNAL wire_nllii1l1O_dataout : STD_LOGIC; + SIGNAL wire_nllii1li_dataout : STD_LOGIC; + SIGNAL wire_nllii1lii_dataout : STD_LOGIC; + SIGNAL wire_nllii1lil_dataout : STD_LOGIC; + SIGNAL wire_nllii1liO_dataout : STD_LOGIC; + SIGNAL wire_nllii1ll_dataout : STD_LOGIC; + SIGNAL wire_nllii1lli_dataout : STD_LOGIC; + SIGNAL wire_nllii1lll_dataout : STD_LOGIC; + SIGNAL wire_nllii1llO_dataout : STD_LOGIC; + SIGNAL wire_nllii1lO_dataout : STD_LOGIC; + SIGNAL wire_nllii1O0i_dataout : STD_LOGIC; + SIGNAL wire_nllii1O0l_dataout : STD_LOGIC; + SIGNAL wire_nllii1O0O_dataout : STD_LOGIC; + SIGNAL wire_nllii1O1O_dataout : STD_LOGIC; + SIGNAL wire_nllii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllii1Oii_dataout : STD_LOGIC; + SIGNAL wire_nllii1Oil_dataout : STD_LOGIC; + SIGNAL wire_nllii1OiO_dataout : STD_LOGIC; + SIGNAL wire_nllii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllii1Oli_dataout : STD_LOGIC; + SIGNAL wire_nllii1Oll_dataout : STD_LOGIC; + SIGNAL wire_nllii1OlO_dataout : STD_LOGIC; + SIGNAL wire_nllii1OO_dataout : STD_LOGIC; + SIGNAL wire_nllii1OOi_dataout : STD_LOGIC; + SIGNAL wire_nllii1OOl_dataout : STD_LOGIC; + SIGNAL wire_nllii1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlliii00O_dataout : STD_LOGIC; + SIGNAL wire_nlliii0ii_dataout : STD_LOGIC; + SIGNAL wire_nlliiiil_dataout : STD_LOGIC; + SIGNAL wire_nlliiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlliiilOO_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlliiiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOii_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOil_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOli_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOll_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOlO_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlliiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlliil00i_dataout : STD_LOGIC; + SIGNAL wire_nlliil01i_dataout : STD_LOGIC; + SIGNAL wire_nlliil01l_dataout : STD_LOGIC; + SIGNAL wire_nlliil01O_dataout : STD_LOGIC; + SIGNAL wire_nlliil0i_dataout : STD_LOGIC; + SIGNAL wire_nlliil0l_dataout : STD_LOGIC; + SIGNAL wire_nlliil0O_dataout : STD_LOGIC; + SIGNAL wire_nlliil10i_dataout : STD_LOGIC; + SIGNAL wire_nlliil10l_dataout : STD_LOGIC; + SIGNAL wire_nlliil10O_dataout : STD_LOGIC; + SIGNAL wire_nlliil11i_dataout : STD_LOGIC; + SIGNAL wire_nlliil11l_dataout : STD_LOGIC; + SIGNAL wire_nlliil11O_dataout : STD_LOGIC; + SIGNAL wire_nlliil1i_dataout : STD_LOGIC; + SIGNAL wire_nlliil1ii_dataout : STD_LOGIC; + SIGNAL wire_nlliil1il_dataout : STD_LOGIC; + SIGNAL wire_nlliil1iO_dataout : STD_LOGIC; + SIGNAL wire_nlliil1l_dataout : STD_LOGIC; + SIGNAL wire_nlliil1li_dataout : STD_LOGIC; + SIGNAL wire_nlliil1ll_dataout : STD_LOGIC; + SIGNAL wire_nlliil1lO_dataout : STD_LOGIC; + SIGNAL wire_nlliil1O_dataout : STD_LOGIC; + SIGNAL wire_nlliil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlliil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlliil1OO_dataout : STD_LOGIC; + SIGNAL wire_nlliilii_dataout : STD_LOGIC; + SIGNAL wire_nlliilil_dataout : STD_LOGIC; + SIGNAL wire_nlliiliO_dataout : STD_LOGIC; + SIGNAL wire_nlliilli_dataout : STD_LOGIC; + SIGNAL wire_nlliilll_dataout : STD_LOGIC; + SIGNAL wire_nlliillO_dataout : STD_LOGIC; + SIGNAL wire_nlliilOi_dataout : STD_LOGIC; + SIGNAL wire_nlliilOl_dataout : STD_LOGIC; + SIGNAL wire_nlliilOO_dataout : STD_LOGIC; + SIGNAL wire_nlliiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlliiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlliiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlliiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlliiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlliiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlliiOii_dataout : STD_LOGIC; + SIGNAL wire_nlliiOil_dataout : STD_LOGIC; + SIGNAL wire_nlliiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlliiOli_dataout : STD_LOGIC; + SIGNAL wire_nlliiOll_dataout : STD_LOGIC; + SIGNAL wire_nlliiOlO_dataout : STD_LOGIC; + SIGNAL wire_nllil00i_dataout : STD_LOGIC; + SIGNAL wire_nllil00l_dataout : STD_LOGIC; + SIGNAL wire_nllil00O_dataout : STD_LOGIC; + SIGNAL wire_nllil01i_dataout : STD_LOGIC; + SIGNAL wire_nllil01l_dataout : STD_LOGIC; + SIGNAL wire_nllil01O_dataout : STD_LOGIC; + SIGNAL wire_nllil0ii_dataout : STD_LOGIC; + SIGNAL wire_nllil0il_dataout : STD_LOGIC; + SIGNAL wire_nllil0iO_dataout : STD_LOGIC; + SIGNAL wire_nllil0lO_dataout : STD_LOGIC; + SIGNAL wire_nllil0lO_w_lg_dataout8888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllil10i_dataout : STD_LOGIC; + SIGNAL wire_nllil10l_dataout : STD_LOGIC; + SIGNAL wire_nllil10O_dataout : STD_LOGIC; + SIGNAL wire_nllil1ii_dataout : STD_LOGIC; + SIGNAL wire_nllil1il_dataout : STD_LOGIC; + SIGNAL wire_nllil1iO_dataout : STD_LOGIC; + SIGNAL wire_nllil1li_dataout : STD_LOGIC; + SIGNAL wire_nllil1ll_dataout : STD_LOGIC; + SIGNAL wire_nllil1lO_dataout : STD_LOGIC; + SIGNAL wire_nllil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllil1OO_dataout : STD_LOGIC; + SIGNAL wire_nllililii_dataout : STD_LOGIC; + SIGNAL wire_nllililil_dataout : STD_LOGIC; + SIGNAL wire_nllililiO_dataout : STD_LOGIC; + SIGNAL wire_nllililli_dataout : STD_LOGIC; + SIGNAL wire_nllililll_dataout : STD_LOGIC; + SIGNAL wire_nllilillO_dataout : STD_LOGIC; + SIGNAL wire_nllililOi_dataout : STD_LOGIC; + SIGNAL wire_nllililOl_dataout : STD_LOGIC; + SIGNAL wire_nllililOO_dataout : STD_LOGIC; + SIGNAL wire_nlliliO0i_dataout : STD_LOGIC; + SIGNAL wire_nlliliO0l_dataout : STD_LOGIC; + SIGNAL wire_nlliliO0O_dataout : STD_LOGIC; + SIGNAL wire_nlliliO1i_dataout : STD_LOGIC; + SIGNAL wire_nlliliO1l_dataout : STD_LOGIC; + SIGNAL wire_nlliliO1O_dataout : STD_LOGIC; + SIGNAL wire_nlliliOii_dataout : STD_LOGIC; + SIGNAL wire_nlliliOil_dataout : STD_LOGIC; + SIGNAL wire_nlliliOiO_dataout : STD_LOGIC; + SIGNAL wire_nlliliOli_dataout : STD_LOGIC; + SIGNAL wire_nlliliOll_dataout : STD_LOGIC; + SIGNAL wire_nlliliOlO_dataout : STD_LOGIC; + SIGNAL wire_nlliliOOi_dataout : STD_LOGIC; + SIGNAL wire_nlliliOOl_dataout : STD_LOGIC; + SIGNAL wire_nlliliOOO_dataout : STD_LOGIC; + SIGNAL wire_nllill00i_dataout : STD_LOGIC; + SIGNAL wire_nllill00l_dataout : STD_LOGIC; + SIGNAL wire_nllill00O_dataout : STD_LOGIC; + SIGNAL wire_nllill01i_dataout : STD_LOGIC; + SIGNAL wire_nllill01l_dataout : STD_LOGIC; + SIGNAL wire_nllill01O_dataout : STD_LOGIC; + SIGNAL wire_nllill0ii_dataout : STD_LOGIC; + SIGNAL wire_nllill0il_dataout : STD_LOGIC; + SIGNAL wire_nllill0iO_dataout : STD_LOGIC; + SIGNAL wire_nllill0li_dataout : STD_LOGIC; + SIGNAL wire_nllill10i_dataout : STD_LOGIC; + SIGNAL wire_nllill10l_dataout : STD_LOGIC; + SIGNAL wire_nllill10O_dataout : STD_LOGIC; + SIGNAL wire_nllill11i_dataout : STD_LOGIC; + SIGNAL wire_nllill11l_dataout : STD_LOGIC; + SIGNAL wire_nllill11O_dataout : STD_LOGIC; + SIGNAL wire_nllill1ii_dataout : STD_LOGIC; + SIGNAL wire_nllill1il_dataout : STD_LOGIC; + SIGNAL wire_nllill1iO_dataout : STD_LOGIC; + SIGNAL wire_nllill1li_dataout : STD_LOGIC; + SIGNAL wire_nllill1ll_dataout : STD_LOGIC; + SIGNAL wire_nllill1lO_dataout : STD_LOGIC; + SIGNAL wire_nllill1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllill1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllill1OO_dataout : STD_LOGIC; + SIGNAL wire_nllilli0l_dataout : STD_LOGIC; + SIGNAL wire_nllilli0O_dataout : STD_LOGIC; + SIGNAL wire_nllilliii_dataout : STD_LOGIC; + SIGNAL wire_nllilliil_dataout : STD_LOGIC; + SIGNAL wire_nllilliiO_dataout : STD_LOGIC; + SIGNAL wire_nllillil_dataout : STD_LOGIC; + SIGNAL wire_nllillil_w_lg_dataout55059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllillili_dataout : STD_LOGIC; + SIGNAL wire_nllillill_dataout : STD_LOGIC; + SIGNAL wire_nllillilO_dataout : STD_LOGIC; + SIGNAL wire_nllilliO_dataout : STD_LOGIC; + SIGNAL wire_nllilliOi_dataout : STD_LOGIC; + SIGNAL wire_nllilliOl_dataout : STD_LOGIC; + SIGNAL wire_nllilliOO_dataout : STD_LOGIC; + SIGNAL wire_nllilll0i_dataout : STD_LOGIC; + SIGNAL wire_nllilll0l_dataout : STD_LOGIC; + SIGNAL wire_nllilll0O_dataout : STD_LOGIC; + SIGNAL wire_nllilll1i_dataout : STD_LOGIC; + SIGNAL wire_nllilll1l_dataout : STD_LOGIC; + SIGNAL wire_nllilll1O_dataout : STD_LOGIC; + SIGNAL wire_nllilllii_dataout : STD_LOGIC; + SIGNAL wire_nllilllil_dataout : STD_LOGIC; + SIGNAL wire_nllillliO_dataout : STD_LOGIC; + SIGNAL wire_nllilllli_dataout : STD_LOGIC; + SIGNAL wire_nllilllll_dataout : STD_LOGIC; + SIGNAL wire_nllillllO_dataout : STD_LOGIC; + SIGNAL wire_nllilllOi_dataout : STD_LOGIC; + SIGNAL wire_nllilllOl_dataout : STD_LOGIC; + SIGNAL wire_nllilllOO_dataout : STD_LOGIC; + SIGNAL wire_nllillO0i_dataout : STD_LOGIC; + SIGNAL wire_nllillO0l_dataout : STD_LOGIC; + SIGNAL wire_nllillO0O_dataout : STD_LOGIC; + SIGNAL wire_nllillO1i_dataout : STD_LOGIC; + SIGNAL wire_nllillO1l_dataout : STD_LOGIC; + SIGNAL wire_nllillO1O_dataout : STD_LOGIC; + SIGNAL wire_nllillOii_dataout : STD_LOGIC; + SIGNAL wire_nllillOil_dataout : STD_LOGIC; + SIGNAL wire_nllillOiO_dataout : STD_LOGIC; + SIGNAL wire_nllillOli_dataout : STD_LOGIC; + SIGNAL wire_nllillOll_dataout : STD_LOGIC; + SIGNAL wire_nllillOlO_dataout : STD_LOGIC; + SIGNAL wire_nllillOOi_dataout : STD_LOGIC; + SIGNAL wire_nllillOOl_dataout : STD_LOGIC; + SIGNAL wire_nllillOOO_dataout : STD_LOGIC; + SIGNAL wire_nllilO00i_dataout : STD_LOGIC; + SIGNAL wire_nllilO00l_dataout : STD_LOGIC; + SIGNAL wire_nllilO00O_dataout : STD_LOGIC; + SIGNAL wire_nllilO01i_dataout : STD_LOGIC; + SIGNAL wire_nllilO01l_dataout : STD_LOGIC; + SIGNAL wire_nllilO01O_dataout : STD_LOGIC; + SIGNAL wire_nllilO0ii_dataout : STD_LOGIC; + SIGNAL wire_nllilO0il_dataout : STD_LOGIC; + SIGNAL wire_nllilO0iO_dataout : STD_LOGIC; + SIGNAL wire_nllilO0li_dataout : STD_LOGIC; + SIGNAL wire_nllilO0ll_dataout : STD_LOGIC; + SIGNAL wire_nllilO0lO_dataout : STD_LOGIC; + SIGNAL wire_nllilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nllilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nllilO0OO_dataout : STD_LOGIC; + SIGNAL wire_nllilO10i_dataout : STD_LOGIC; + SIGNAL wire_nllilO10l_dataout : STD_LOGIC; + SIGNAL wire_nllilO10O_dataout : STD_LOGIC; + SIGNAL wire_nllilO11i_dataout : STD_LOGIC; + SIGNAL wire_nllilO11l_dataout : STD_LOGIC; + SIGNAL wire_nllilO11O_dataout : STD_LOGIC; + SIGNAL wire_nllilO1ii_dataout : STD_LOGIC; + SIGNAL wire_nllilO1il_dataout : STD_LOGIC; + SIGNAL wire_nllilO1iO_dataout : STD_LOGIC; + SIGNAL wire_nllilO1li_dataout : STD_LOGIC; + SIGNAL wire_nllilO1ll_dataout : STD_LOGIC; + SIGNAL wire_nllilO1lO_dataout : STD_LOGIC; + SIGNAL wire_nllilO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllilO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllilO1OO_dataout : STD_LOGIC; + SIGNAL wire_nllilOi0i_dataout : STD_LOGIC; + SIGNAL wire_nllilOi0l_dataout : STD_LOGIC; + SIGNAL wire_nllilOi0O_dataout : STD_LOGIC; + SIGNAL wire_nllilOi1i_dataout : STD_LOGIC; + SIGNAL wire_nllilOi1l_dataout : STD_LOGIC; + SIGNAL wire_nllilOi1O_dataout : STD_LOGIC; + SIGNAL wire_nllilOiii_dataout : STD_LOGIC; + SIGNAL wire_nllilOiil_dataout : STD_LOGIC; + SIGNAL wire_nllilOiiO_dataout : STD_LOGIC; + SIGNAL wire_nllilOili_dataout : STD_LOGIC; + SIGNAL wire_nllilOill_dataout : STD_LOGIC; + SIGNAL wire_nllilOilO_dataout : STD_LOGIC; + SIGNAL wire_nllilOiOi_dataout : STD_LOGIC; + SIGNAL wire_nllilOiOl_dataout : STD_LOGIC; + SIGNAL wire_nllilOiOO_dataout : STD_LOGIC; + SIGNAL wire_nllilOl0i_dataout : STD_LOGIC; + SIGNAL wire_nllilOl0l_dataout : STD_LOGIC; + SIGNAL wire_nllilOl0O_dataout : STD_LOGIC; + SIGNAL wire_nllilOl1i_dataout : STD_LOGIC; + SIGNAL wire_nllilOl1l_dataout : STD_LOGIC; + SIGNAL wire_nllilOl1O_dataout : STD_LOGIC; + SIGNAL wire_nllilOlii_dataout : STD_LOGIC; + SIGNAL wire_nllilOlil_dataout : STD_LOGIC; + SIGNAL wire_nllilOliO_dataout : STD_LOGIC; + SIGNAL wire_nllilOlli_dataout : STD_LOGIC; + SIGNAL wire_nlliO00i_dataout : STD_LOGIC; + SIGNAL wire_nlliO00l_dataout : STD_LOGIC; + SIGNAL wire_nlliO00O_dataout : STD_LOGIC; + SIGNAL wire_nlliO010i_dataout : STD_LOGIC; + SIGNAL wire_nlliO010l_dataout : STD_LOGIC; + SIGNAL wire_nlliO010O_dataout : STD_LOGIC; + SIGNAL wire_nlliO011i_dataout : STD_LOGIC; + SIGNAL wire_nlliO011l_dataout : STD_LOGIC; + SIGNAL wire_nlliO011O_dataout : STD_LOGIC; + SIGNAL wire_nlliO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlliO01il_dataout : STD_LOGIC; + SIGNAL wire_nlliO01iO_dataout : STD_LOGIC; + SIGNAL wire_nlliO01li_dataout : STD_LOGIC; + SIGNAL wire_nlliO01ll_dataout : STD_LOGIC; + SIGNAL wire_nlliO01lO_dataout : STD_LOGIC; + SIGNAL wire_nlliO01O_dataout : STD_LOGIC; + SIGNAL wire_nlliO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlliO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlliO01OO_dataout : STD_LOGIC; + SIGNAL wire_nlliO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlliO0il_dataout : STD_LOGIC; + SIGNAL wire_nlliO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlliO0li_dataout : STD_LOGIC; + SIGNAL wire_nlliO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlliO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlliO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlliO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlliO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlliO100i_dataout : STD_LOGIC; + SIGNAL wire_nlliO100l_dataout : STD_LOGIC; + SIGNAL wire_nlliO100O_dataout : STD_LOGIC; + SIGNAL wire_nlliO101l_dataout : STD_LOGIC; + SIGNAL wire_nlliO101O_dataout : STD_LOGIC; + SIGNAL wire_nlliO10ii_dataout : STD_LOGIC; + SIGNAL wire_nlliO10il_dataout : STD_LOGIC; + SIGNAL wire_nlliO10iO_dataout : STD_LOGIC; + SIGNAL wire_nlliO10li_dataout : STD_LOGIC; + SIGNAL wire_nlliO10ll_dataout : STD_LOGIC; + SIGNAL wire_nlliO10lO_dataout : STD_LOGIC; + SIGNAL wire_nlliO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlliO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlliO10OO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlliO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlliO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlliO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlliO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1ili_dataout : STD_LOGIC; + SIGNAL wire_nlliO1ill_dataout : STD_LOGIC; + SIGNAL wire_nlliO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlliO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlliO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlliO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlliO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlliO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlliO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlliO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlliO1lii_dataout : STD_LOGIC; + SIGNAL wire_nlliO1lil_dataout : STD_LOGIC; + SIGNAL wire_nlliO1liO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1lli_dataout : STD_LOGIC; + SIGNAL wire_nlliO1lll_dataout : STD_LOGIC; + SIGNAL wire_nlliO1llO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlliO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlliO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlliO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlliO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlliO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlliO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlliO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlliO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlliO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlliO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlliO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlliO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlliO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlliO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlliO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlliOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlliOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlliOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlliOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlliOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlliOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOiii_dataout : STD_LOGIC; + SIGNAL wire_nlliOiil_dataout : STD_LOGIC; + SIGNAL wire_nlliOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlliOili_dataout : STD_LOGIC; + SIGNAL wire_nlliOill_dataout : STD_LOGIC; + SIGNAL wire_nlliOilO_dataout : STD_LOGIC; + SIGNAL wire_nlliOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlliOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlliOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlliOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlliOl11O_dataout : STD_LOGIC; + SIGNAL wire_nlliOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlliOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlliOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOli0i_dataout : STD_LOGIC; + SIGNAL wire_nlliOli0l_dataout : STD_LOGIC; + SIGNAL wire_nlliOli0O_dataout : STD_LOGIC; + SIGNAL wire_nlliOli1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOlii_dataout : STD_LOGIC; + SIGNAL wire_nlliOliii_dataout : STD_LOGIC; + SIGNAL wire_nlliOliil_dataout : STD_LOGIC; + SIGNAL wire_nlliOliiO_dataout : STD_LOGIC; + SIGNAL wire_nlliOlil_dataout : STD_LOGIC; + SIGNAL wire_nlliOlili_dataout : STD_LOGIC; + SIGNAL wire_nlliOlill_dataout : STD_LOGIC; + SIGNAL wire_nlliOlilO_dataout : STD_LOGIC; + SIGNAL wire_nlliOliO_dataout : STD_LOGIC; + SIGNAL wire_nlliOliOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOliOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOliOO_dataout : STD_LOGIC; + SIGNAL wire_nlliOll0i_dataout : STD_LOGIC; + SIGNAL wire_nlliOll0l_dataout : STD_LOGIC; + SIGNAL wire_nlliOll0O_dataout : STD_LOGIC; + SIGNAL wire_nlliOll1i_dataout : STD_LOGIC; + SIGNAL wire_nlliOll1l_dataout : STD_LOGIC; + SIGNAL wire_nlliOll1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOlli_dataout : STD_LOGIC; + SIGNAL wire_nlliOllii_dataout : STD_LOGIC; + SIGNAL wire_nlliOllil_dataout : STD_LOGIC; + SIGNAL wire_nlliOlliO_dataout : STD_LOGIC; + SIGNAL wire_nlliOlll_dataout : STD_LOGIC; + SIGNAL wire_nlliOllli_dataout : STD_LOGIC; + SIGNAL wire_nlliOllll_dataout : STD_LOGIC; + SIGNAL wire_nlliOlllO_dataout : STD_LOGIC; + SIGNAL wire_nlliOllO_dataout : STD_LOGIC; + SIGNAL wire_nlliOllOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOllOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOllOO_dataout : STD_LOGIC; + SIGNAL wire_nlliOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlliOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlliOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlliOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlliOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlliOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOii_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOil_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlliOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlliOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlliOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlliOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlliOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlliOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlliOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0li_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlliOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlliOO10i_dataout : STD_LOGIC; + SIGNAL wire_nlliOO10l_dataout : STD_LOGIC; + SIGNAL wire_nlliOO10O_dataout : STD_LOGIC; + SIGNAL wire_nlliOO11i_dataout : STD_LOGIC; + SIGNAL wire_nlliOO11l_dataout : STD_LOGIC; + SIGNAL wire_nlliOO11O_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1li_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlliOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlliOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlliOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlliOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlliOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlliOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlliOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlliOOii_dataout : STD_LOGIC; + SIGNAL wire_nlliOOiii_dataout : STD_LOGIC; + SIGNAL wire_nlliOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlliOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlliOOil_dataout : STD_LOGIC; + SIGNAL wire_nlliOOili_dataout : STD_LOGIC; + SIGNAL wire_nlliOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlliOOli_dataout : STD_LOGIC; + SIGNAL wire_nlliOOll_dataout : STD_LOGIC; + SIGNAL wire_nlliOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlliOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlliOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlliOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0000i_dataout : STD_LOGIC; + SIGNAL wire_nlll0000l_dataout : STD_LOGIC; + SIGNAL wire_nlll0000O_dataout : STD_LOGIC; + SIGNAL wire_nlll0010i_dataout : STD_LOGIC; + SIGNAL wire_nlll0011i_dataout : STD_LOGIC; + SIGNAL wire_nlll0011l_dataout : STD_LOGIC; + SIGNAL wire_nlll0011O_dataout : STD_LOGIC; + SIGNAL wire_nlll001ll_dataout : STD_LOGIC; + SIGNAL wire_nlll001lO_dataout : STD_LOGIC; + SIGNAL wire_nlll00iO_dataout : STD_LOGIC; + SIGNAL wire_nlll00l0i_dataout : STD_LOGIC; + SIGNAL wire_nlll00l0l_dataout : STD_LOGIC; + SIGNAL wire_nlll00l0O_dataout : STD_LOGIC; + SIGNAL wire_nlll00l1l_dataout : STD_LOGIC; + SIGNAL wire_nlll00l1O_dataout : STD_LOGIC; + SIGNAL wire_nlll00li_dataout : STD_LOGIC; + SIGNAL wire_nlll00lii_dataout : STD_LOGIC; + SIGNAL wire_nlll00lil_dataout : STD_LOGIC; + SIGNAL wire_nlll00liO_dataout : STD_LOGIC; + SIGNAL wire_nlll00ll_dataout : STD_LOGIC; + SIGNAL wire_nlll00lli_dataout : STD_LOGIC; + SIGNAL wire_nlll00lll_dataout : STD_LOGIC; + SIGNAL wire_nlll00llO_dataout : STD_LOGIC; + SIGNAL wire_nlll00lO_dataout : STD_LOGIC; + SIGNAL wire_nlll00lOi_dataout : STD_LOGIC; + SIGNAL wire_nlll00lOl_dataout : STD_LOGIC; + SIGNAL wire_nlll00lOO_dataout : STD_LOGIC; + SIGNAL wire_nlll00O0i_dataout : STD_LOGIC; + SIGNAL wire_nlll00O0l_dataout : STD_LOGIC; + SIGNAL wire_nlll00O0O_dataout : STD_LOGIC; + SIGNAL wire_nlll00O1i_dataout : STD_LOGIC; + SIGNAL wire_nlll00O1l_dataout : STD_LOGIC; + SIGNAL wire_nlll00O1O_dataout : STD_LOGIC; + SIGNAL wire_nlll00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll00Oii_dataout : STD_LOGIC; + SIGNAL wire_nlll00Oil_dataout : STD_LOGIC; + SIGNAL wire_nlll00OiO_dataout : STD_LOGIC; + SIGNAL wire_nlll00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll00Oli_dataout : STD_LOGIC; + SIGNAL wire_nlll00Oll_dataout : STD_LOGIC; + SIGNAL wire_nlll00OlO_dataout : STD_LOGIC; + SIGNAL wire_nlll00OO_dataout : STD_LOGIC; + SIGNAL wire_nlll00OOi_dataout : STD_LOGIC; + SIGNAL wire_nlll00OOl_dataout : STD_LOGIC; + SIGNAL wire_nlll00OOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0110i_dataout : STD_LOGIC; + SIGNAL wire_nlll0110l_dataout : STD_LOGIC; + SIGNAL wire_nlll0111i_dataout : STD_LOGIC; + SIGNAL wire_nlll0111l_dataout : STD_LOGIC; + SIGNAL wire_nlll0111O_dataout : STD_LOGIC; + SIGNAL wire_nlll011ii_dataout : STD_LOGIC; + SIGNAL wire_nlll011il_dataout : STD_LOGIC; + SIGNAL wire_nlll011iO_dataout : STD_LOGIC; + SIGNAL wire_nlll011li_dataout : STD_LOGIC; + SIGNAL wire_nlll011ll_dataout : STD_LOGIC; + SIGNAL wire_nlll011lO_dataout : STD_LOGIC; + SIGNAL wire_nlll01i0i_dataout : STD_LOGIC; + SIGNAL wire_nlll01i0l_dataout : STD_LOGIC; + SIGNAL wire_nlll01i0O_dataout : STD_LOGIC; + SIGNAL wire_nlll01i1l_dataout : STD_LOGIC; + SIGNAL wire_nlll01i1O_dataout : STD_LOGIC; + SIGNAL wire_nlll01iii_dataout : STD_LOGIC; + SIGNAL wire_nlll01iil_dataout : STD_LOGIC; + SIGNAL wire_nlll01iiO_dataout : STD_LOGIC; + SIGNAL wire_nlll01ili_dataout : STD_LOGIC; + SIGNAL wire_nlll01ill_dataout : STD_LOGIC; + SIGNAL wire_nlll01ilO_dataout : STD_LOGIC; + SIGNAL wire_nlll01iOi_dataout : STD_LOGIC; + SIGNAL wire_nlll01iOl_dataout : STD_LOGIC; + SIGNAL wire_nlll01iOO_dataout : STD_LOGIC; + SIGNAL wire_nlll01l0i_dataout : STD_LOGIC; + SIGNAL wire_nlll01l0l_dataout : STD_LOGIC; + SIGNAL wire_nlll01l1i_dataout : STD_LOGIC; + SIGNAL wire_nlll01l1l_dataout : STD_LOGIC; + SIGNAL wire_nlll01l1O_dataout : STD_LOGIC; + SIGNAL wire_nlll01lii_dataout : STD_LOGIC; + SIGNAL wire_nlll01lil_dataout : STD_LOGIC; + SIGNAL wire_nlll01liO_dataout : STD_LOGIC; + SIGNAL wire_nlll01ll_dataout : STD_LOGIC; + SIGNAL wire_nlll01lli_dataout : STD_LOGIC; + SIGNAL wire_nlll01lO_dataout : STD_LOGIC; + SIGNAL wire_nlll01lOi_dataout : STD_LOGIC; + SIGNAL wire_nlll01lOO_dataout : STD_LOGIC; + SIGNAL wire_nlll01O0i_dataout : STD_LOGIC; + SIGNAL wire_nlll01O0l_dataout : STD_LOGIC; + SIGNAL wire_nlll01O0O_dataout : STD_LOGIC; + SIGNAL wire_nlll01O1i_dataout : STD_LOGIC; + SIGNAL wire_nlll01O1l_dataout : STD_LOGIC; + SIGNAL wire_nlll01O1O_dataout : STD_LOGIC; + SIGNAL wire_nlll01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll01Oii_dataout : STD_LOGIC; + SIGNAL wire_nlll01Oil_dataout : STD_LOGIC; + SIGNAL wire_nlll01OiO_dataout : STD_LOGIC; + SIGNAL wire_nlll01Oli_dataout : STD_LOGIC; + SIGNAL wire_nlll01Oll_dataout : STD_LOGIC; + SIGNAL wire_nlll01OlO_dataout : STD_LOGIC; + SIGNAL wire_nlll01OOi_dataout : STD_LOGIC; + SIGNAL wire_nlll01OOl_dataout : STD_LOGIC; + SIGNAL wire_nlll01OOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0i00i_dataout : STD_LOGIC; + SIGNAL wire_nlll0i00l_dataout : STD_LOGIC; + SIGNAL wire_nlll0i00O_dataout : STD_LOGIC; + SIGNAL wire_nlll0i01i_dataout : STD_LOGIC; + SIGNAL wire_nlll0i01l_dataout : STD_LOGIC; + SIGNAL wire_nlll0i01O_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0il_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0li_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlll0i10i_dataout : STD_LOGIC; + SIGNAL wire_nlll0i10l_dataout : STD_LOGIC; + SIGNAL wire_nlll0i10O_dataout : STD_LOGIC; + SIGNAL wire_nlll0i11i_dataout : STD_LOGIC; + SIGNAL wire_nlll0i11l_dataout : STD_LOGIC; + SIGNAL wire_nlll0i11O_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1il_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1li_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlll0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlll0iii_dataout : STD_LOGIC; + SIGNAL wire_nlll0iiii_dataout : STD_LOGIC; + SIGNAL wire_nlll0iiil_dataout : STD_LOGIC; + SIGNAL wire_nlll0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlll0iil_dataout : STD_LOGIC; + SIGNAL wire_nlll0iili_dataout : STD_LOGIC; + SIGNAL wire_nlll0iill_dataout : STD_LOGIC; + SIGNAL wire_nlll0iilO_dataout : STD_LOGIC; + SIGNAL wire_nlll0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlll0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlll0il0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0il0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0il0O_dataout : STD_LOGIC; + SIGNAL wire_nlll0ili_dataout : STD_LOGIC; + SIGNAL wire_nlll0ilii_dataout : STD_LOGIC; + SIGNAL wire_nlll0ill_dataout : STD_LOGIC; + SIGNAL wire_nlll0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlll0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlll0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlll0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0l00l_dataout : STD_LOGIC; + SIGNAL wire_nlll0l00O_dataout : STD_LOGIC; + SIGNAL wire_nlll0l01i_dataout : STD_LOGIC; + SIGNAL wire_nlll0l01l_dataout : STD_LOGIC; + SIGNAL wire_nlll0l01O_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0il_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0li_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlll0l10i_dataout : STD_LOGIC; + SIGNAL wire_nlll0l10l_dataout : STD_LOGIC; + SIGNAL wire_nlll0l10O_dataout : STD_LOGIC; + SIGNAL wire_nlll0l11i_dataout : STD_LOGIC; + SIGNAL wire_nlll0l11l_dataout : STD_LOGIC; + SIGNAL wire_nlll0l11O_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1il_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1li_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlll0li0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0li0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0li1i_dataout : STD_LOGIC; + SIGNAL wire_nlll0li1l_dataout : STD_LOGIC; + SIGNAL wire_nlll0li1O_dataout : STD_LOGIC; + SIGNAL wire_nlll0lii_dataout : STD_LOGIC; + SIGNAL wire_nlll0liii_dataout : STD_LOGIC; + SIGNAL wire_nlll0liii_w_lg_dataout34277w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liil_dataout : STD_LOGIC; + SIGNAL wire_nlll0liil_w_lg_dataout34279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liiO_dataout : STD_LOGIC; + SIGNAL wire_nlll0liiO_w_lg_dataout34281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lili_dataout : STD_LOGIC; + SIGNAL wire_nlll0lili_w_lg_dataout34283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lill_dataout : STD_LOGIC; + SIGNAL wire_nlll0lill_w_lg_dataout34285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lilO_dataout : STD_LOGIC; + SIGNAL wire_nlll0lilO_w_lg_dataout34287w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liO_dataout : STD_LOGIC; + SIGNAL wire_nlll0liO_w_lg_w_lg_dataout5087w5088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liO_w_lg_dataout5744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liO_w_lg_dataout5750w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liO_w_lg_dataout5087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liOi_dataout : STD_LOGIC; + SIGNAL wire_nlll0liOi_w_lg_dataout34289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liOl_dataout : STD_LOGIC; + SIGNAL wire_nlll0liOl_w_lg_dataout34291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0liOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0liOO_w_lg_dataout34293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll1i_w_lg_dataout34295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll1l_w_lg_dataout34297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlll0ll1O_w_lg_dataout34299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0llii_dataout : STD_LOGIC; + SIGNAL wire_nlll0llil_dataout : STD_LOGIC; + SIGNAL wire_nlll0lliO_dataout : STD_LOGIC; + SIGNAL wire_nlll0llli_dataout : STD_LOGIC; + SIGNAL wire_nlll0llll_dataout : STD_LOGIC; + SIGNAL wire_nlll0lllO_dataout : STD_LOGIC; + SIGNAL wire_nlll0llOi_dataout : STD_LOGIC; + SIGNAL wire_nlll0llOl_dataout : STD_LOGIC; + SIGNAL wire_nlll0llOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0lOll_dataout : STD_LOGIC; + SIGNAL wire_nlll0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlll0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlll0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlll0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlll0O10i_dataout : STD_LOGIC; + SIGNAL wire_nlll0O10l_dataout : STD_LOGIC; + SIGNAL wire_nlll0O10O_dataout : STD_LOGIC; + SIGNAL wire_nlll0O11i_dataout : STD_LOGIC; + SIGNAL wire_nlll0O11l_dataout : STD_LOGIC; + SIGNAL wire_nlll0O11O_dataout : STD_LOGIC; + SIGNAL wire_nlll0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlll0O1il_dataout : STD_LOGIC; + SIGNAL wire_nlll0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlll0O1li_dataout : STD_LOGIC; + SIGNAL wire_nlll0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1000i_dataout : STD_LOGIC; + SIGNAL wire_nlll1000l_dataout : STD_LOGIC; + SIGNAL wire_nlll1000O_dataout : STD_LOGIC; + SIGNAL wire_nlll1001i_dataout : STD_LOGIC; + SIGNAL wire_nlll1001l_dataout : STD_LOGIC; + SIGNAL wire_nlll1001O_dataout : STD_LOGIC; + SIGNAL wire_nlll100i_dataout : STD_LOGIC; + SIGNAL wire_nlll100ii_dataout : STD_LOGIC; + SIGNAL wire_nlll100il_dataout : STD_LOGIC; + SIGNAL wire_nlll100iO_dataout : STD_LOGIC; + SIGNAL wire_nlll100l_dataout : STD_LOGIC; + SIGNAL wire_nlll100li_dataout : STD_LOGIC; + SIGNAL wire_nlll100ll_dataout : STD_LOGIC; + SIGNAL wire_nlll100lO_dataout : STD_LOGIC; + SIGNAL wire_nlll100O_dataout : STD_LOGIC; + SIGNAL wire_nlll100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll100Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll100OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1010i_dataout : STD_LOGIC; + SIGNAL wire_nlll1010l_dataout : STD_LOGIC; + SIGNAL wire_nlll1010O_dataout : STD_LOGIC; + SIGNAL wire_nlll1011i_dataout : STD_LOGIC; + SIGNAL wire_nlll1011l_dataout : STD_LOGIC; + SIGNAL wire_nlll1011O_dataout : STD_LOGIC; + SIGNAL wire_nlll101ii_dataout : STD_LOGIC; + SIGNAL wire_nlll101il_dataout : STD_LOGIC; + SIGNAL wire_nlll101iO_dataout : STD_LOGIC; + SIGNAL wire_nlll101li_dataout : STD_LOGIC; + SIGNAL wire_nlll101ll_dataout : STD_LOGIC; + SIGNAL wire_nlll101lO_dataout : STD_LOGIC; + SIGNAL wire_nlll101Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll101Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll101OO_dataout : STD_LOGIC; + SIGNAL wire_nlll10i0i_dataout : STD_LOGIC; + SIGNAL wire_nlll10i0l_dataout : STD_LOGIC; + SIGNAL wire_nlll10i0O_dataout : STD_LOGIC; + SIGNAL wire_nlll10i1i_dataout : STD_LOGIC; + SIGNAL wire_nlll10i1l_dataout : STD_LOGIC; + SIGNAL wire_nlll10i1O_dataout : STD_LOGIC; + SIGNAL wire_nlll10ii_dataout : STD_LOGIC; + SIGNAL wire_nlll10iii_dataout : STD_LOGIC; + SIGNAL wire_nlll10iil_dataout : STD_LOGIC; + SIGNAL wire_nlll10iiO_dataout : STD_LOGIC; + SIGNAL wire_nlll10il_dataout : STD_LOGIC; + SIGNAL wire_nlll10ili_dataout : STD_LOGIC; + SIGNAL wire_nlll10ill_dataout : STD_LOGIC; + SIGNAL wire_nlll10ilO_dataout : STD_LOGIC; + SIGNAL wire_nlll10iO_dataout : STD_LOGIC; + SIGNAL wire_nlll10iOi_dataout : STD_LOGIC; + SIGNAL wire_nlll10iOl_dataout : STD_LOGIC; + SIGNAL wire_nlll10iOO_dataout : STD_LOGIC; + SIGNAL wire_nlll10l0i_dataout : STD_LOGIC; + SIGNAL wire_nlll10l0l_dataout : STD_LOGIC; + SIGNAL wire_nlll10l0O_dataout : STD_LOGIC; + SIGNAL wire_nlll10l1i_dataout : STD_LOGIC; + SIGNAL wire_nlll10l1l_dataout : STD_LOGIC; + SIGNAL wire_nlll10l1O_dataout : STD_LOGIC; + SIGNAL wire_nlll10li_dataout : STD_LOGIC; + SIGNAL wire_nlll10lii_dataout : STD_LOGIC; + SIGNAL wire_nlll10lil_dataout : STD_LOGIC; + SIGNAL wire_nlll10liO_dataout : STD_LOGIC; + SIGNAL wire_nlll10ll_dataout : STD_LOGIC; + SIGNAL wire_nlll10lli_dataout : STD_LOGIC; + SIGNAL wire_nlll10lll_dataout : STD_LOGIC; + SIGNAL wire_nlll10llO_dataout : STD_LOGIC; + SIGNAL wire_nlll10lO_dataout : STD_LOGIC; + SIGNAL wire_nlll10lOi_dataout : STD_LOGIC; + SIGNAL wire_nlll10lOl_dataout : STD_LOGIC; + SIGNAL wire_nlll10lOO_dataout : STD_LOGIC; + SIGNAL wire_nlll10O0i_dataout : STD_LOGIC; + SIGNAL wire_nlll10O0l_dataout : STD_LOGIC; + SIGNAL wire_nlll10O0O_dataout : STD_LOGIC; + SIGNAL wire_nlll10O1i_dataout : STD_LOGIC; + SIGNAL wire_nlll10O1l_dataout : STD_LOGIC; + SIGNAL wire_nlll10O1O_dataout : STD_LOGIC; + SIGNAL wire_nlll10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll10Oii_dataout : STD_LOGIC; + SIGNAL wire_nlll10Oil_dataout : STD_LOGIC; + SIGNAL wire_nlll10OiO_dataout : STD_LOGIC; + SIGNAL wire_nlll10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll10Oli_dataout : STD_LOGIC; + SIGNAL wire_nlll10Oll_dataout : STD_LOGIC; + SIGNAL wire_nlll10OO_dataout : STD_LOGIC; + SIGNAL wire_nlll10OOl_dataout : STD_LOGIC; + SIGNAL wire_nlll10OOO_dataout : STD_LOGIC; + SIGNAL wire_nlll110i_dataout : STD_LOGIC; + SIGNAL wire_nlll110l_dataout : STD_LOGIC; + SIGNAL wire_nlll110O_dataout : STD_LOGIC; + SIGNAL wire_nlll111i_dataout : STD_LOGIC; + SIGNAL wire_nlll111l_dataout : STD_LOGIC; + SIGNAL wire_nlll111O_dataout : STD_LOGIC; + SIGNAL wire_nlll11ii_dataout : STD_LOGIC; + SIGNAL wire_nlll11il_dataout : STD_LOGIC; + SIGNAL wire_nlll11iO_dataout : STD_LOGIC; + SIGNAL wire_nlll11li_dataout : STD_LOGIC; + SIGNAL wire_nlll11ll_dataout : STD_LOGIC; + SIGNAL wire_nlll11lO_dataout : STD_LOGIC; + SIGNAL wire_nlll11O0i_dataout : STD_LOGIC; + SIGNAL wire_nlll11O0l_dataout : STD_LOGIC; + SIGNAL wire_nlll11O0O_dataout : STD_LOGIC; + SIGNAL wire_nlll11O1O_dataout : STD_LOGIC; + SIGNAL wire_nlll11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll11Oii_dataout : STD_LOGIC; + SIGNAL wire_nlll11Oil_dataout : STD_LOGIC; + SIGNAL wire_nlll11OiO_dataout : STD_LOGIC; + SIGNAL wire_nlll11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll11Oli_dataout : STD_LOGIC; + SIGNAL wire_nlll11Oll_dataout : STD_LOGIC; + SIGNAL wire_nlll11OlO_dataout : STD_LOGIC; + SIGNAL wire_nlll11OOi_dataout : STD_LOGIC; + SIGNAL wire_nlll11OOl_dataout : STD_LOGIC; + SIGNAL wire_nlll11OOO_dataout : STD_LOGIC; + SIGNAL wire_nlll1i00i_dataout : STD_LOGIC; + SIGNAL wire_nlll1i00l_dataout : STD_LOGIC; + SIGNAL wire_nlll1i00O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i01i_dataout : STD_LOGIC; + SIGNAL wire_nlll1i01l_dataout : STD_LOGIC; + SIGNAL wire_nlll1i01O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0il_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0li_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1i10i_dataout : STD_LOGIC; + SIGNAL wire_nlll1i10l_dataout : STD_LOGIC; + SIGNAL wire_nlll1i10O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i11i_dataout : STD_LOGIC; + SIGNAL wire_nlll1i11l_dataout : STD_LOGIC; + SIGNAL wire_nlll1i11O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1il_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1li_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlll1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlll1iii_dataout : STD_LOGIC; + SIGNAL wire_nlll1iiii_dataout : STD_LOGIC; + SIGNAL wire_nlll1iiil_dataout : STD_LOGIC; + SIGNAL wire_nlll1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlll1iil_dataout : STD_LOGIC; + SIGNAL wire_nlll1iili_dataout : STD_LOGIC; + SIGNAL wire_nlll1iill_dataout : STD_LOGIC; + SIGNAL wire_nlll1iilO_dataout : STD_LOGIC; + SIGNAL wire_nlll1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlll1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlll1ili_dataout : STD_LOGIC; + SIGNAL wire_nlll1ill_dataout : STD_LOGIC; + SIGNAL wire_nlll1illi_dataout : STD_LOGIC; + SIGNAL wire_nlll1illl_dataout : STD_LOGIC; + SIGNAL wire_nlll1illO_dataout : STD_LOGIC; + SIGNAL wire_nlll1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlll1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlll1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlll1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlll1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlll1l00i_dataout : STD_LOGIC; + SIGNAL wire_nlll1l00l_dataout : STD_LOGIC; + SIGNAL wire_nlll1l00O_dataout : STD_LOGIC; + SIGNAL wire_nlll1l01i_dataout : STD_LOGIC; + SIGNAL wire_nlll1l01O_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0il_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0li_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1l10i_dataout : STD_LOGIC; + SIGNAL wire_nlll1l10l_dataout : STD_LOGIC; + SIGNAL wire_nlll1l10O_dataout : STD_LOGIC; + SIGNAL wire_nlll1l11i_dataout : STD_LOGIC; + SIGNAL wire_nlll1l11l_dataout : STD_LOGIC; + SIGNAL wire_nlll1l11O_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1il_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1li_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1li0i_dataout : STD_LOGIC; + SIGNAL wire_nlll1li0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1li0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1li1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1li1O_dataout : STD_LOGIC; + SIGNAL wire_nlll1lii_dataout : STD_LOGIC; + SIGNAL wire_nlll1liii_dataout : STD_LOGIC; + SIGNAL wire_nlll1liil_dataout : STD_LOGIC; + SIGNAL wire_nlll1liiO_dataout : STD_LOGIC; + SIGNAL wire_nlll1lil_dataout : STD_LOGIC; + SIGNAL wire_nlll1lili_dataout : STD_LOGIC; + SIGNAL wire_nlll1lill_dataout : STD_LOGIC; + SIGNAL wire_nlll1lilO_dataout : STD_LOGIC; + SIGNAL wire_nlll1liO_dataout : STD_LOGIC; + SIGNAL wire_nlll1liOi_dataout : STD_LOGIC; + SIGNAL wire_nlll1liOl_dataout : STD_LOGIC; + SIGNAL wire_nlll1liOO_dataout : STD_LOGIC; + SIGNAL wire_nlll1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1lli_dataout : STD_LOGIC; + SIGNAL wire_nlll1llii_dataout : STD_LOGIC; + SIGNAL wire_nlll1llil_dataout : STD_LOGIC; + SIGNAL wire_nlll1lliO_dataout : STD_LOGIC; + SIGNAL wire_nlll1lll_dataout : STD_LOGIC; + SIGNAL wire_nlll1llli_dataout : STD_LOGIC; + SIGNAL wire_nlll1llll_dataout : STD_LOGIC; + SIGNAL wire_nlll1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlll1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlll1O00i_dataout : STD_LOGIC; + SIGNAL wire_nlll1O00l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O00O_dataout : STD_LOGIC; + SIGNAL wire_nlll1O01i_dataout : STD_LOGIC; + SIGNAL wire_nlll1O01l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O01O_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0il_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0li_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1O10i_dataout : STD_LOGIC; + SIGNAL wire_nlll1O10l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O10O_dataout : STD_LOGIC; + SIGNAL wire_nlll1O11i_dataout : STD_LOGIC; + SIGNAL wire_nlll1O11l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O11O_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1il_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1li_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlll1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlll1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oili_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oill_dataout : STD_LOGIC; + SIGNAL wire_nlll1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlll1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlll1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlll1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlll1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlll1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlll1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlll1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlll1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlll1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlll1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlll1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlll1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlll1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlll1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlll1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlll1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlll1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlll1OOli_dataout : STD_LOGIC; + SIGNAL wire_nlll1OOll_dataout : STD_LOGIC; + SIGNAL wire_nlll1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nllli01O_dataout : STD_LOGIC; + SIGNAL wire_nllli01O_w_lg_dataout4682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllli01O_w_lg_dataout4050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nllli0iO_dataout : STD_LOGIC; + SIGNAL wire_nllli0li_dataout : STD_LOGIC; + SIGNAL wire_nllli0ll_dataout : STD_LOGIC; + SIGNAL wire_nllli0lO_dataout : STD_LOGIC; + SIGNAL wire_nllli1ll_dataout : STD_LOGIC; + SIGNAL wire_nllli1lO_dataout : STD_LOGIC; + SIGNAL wire_nllli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlllil0O_dataout : STD_LOGIC; + SIGNAL wire_nlllilii_dataout : STD_LOGIC; + SIGNAL wire_nlllilil_dataout : STD_LOGIC; + SIGNAL wire_nllliliO_dataout : STD_LOGIC; + SIGNAL wire_nlllilli_dataout : STD_LOGIC; + SIGNAL wire_nlllilll_dataout : STD_LOGIC; + SIGNAL wire_nlllillO_dataout : STD_LOGIC; + SIGNAL wire_nlllilOi_dataout : STD_LOGIC; + SIGNAL wire_nlllilOl_dataout : STD_LOGIC; + SIGNAL wire_nlllilOO_dataout : STD_LOGIC; + SIGNAL wire_nllliO0i_dataout : STD_LOGIC; + SIGNAL wire_nllliO0l_dataout : STD_LOGIC; + SIGNAL wire_nllliO0O_dataout : STD_LOGIC; + SIGNAL wire_nllliO1i_dataout : STD_LOGIC; + SIGNAL wire_nllliO1l_dataout : STD_LOGIC; + SIGNAL wire_nllliO1O_dataout : STD_LOGIC; + SIGNAL wire_nllliOii_dataout : STD_LOGIC; + SIGNAL wire_nllliOil_dataout : STD_LOGIC; + SIGNAL wire_nllll0lO_dataout : STD_LOGIC; + SIGNAL wire_nllll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nllll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nllll0OO_dataout : STD_LOGIC; + SIGNAL wire_nllllllO_dataout : STD_LOGIC; + SIGNAL wire_nlllllOi_dataout : STD_LOGIC; + SIGNAL wire_nlllllOl_dataout : STD_LOGIC; + SIGNAL wire_nlllllOO_dataout : STD_LOGIC; + SIGNAL wire_nllllO0i_dataout : STD_LOGIC; + SIGNAL wire_nllllO0l_dataout : STD_LOGIC; + SIGNAL wire_nllllO0O_dataout : STD_LOGIC; + SIGNAL wire_nllllO1i_dataout : STD_LOGIC; + SIGNAL wire_nllllO1l_dataout : STD_LOGIC; + SIGNAL wire_nllllO1O_dataout : STD_LOGIC; + SIGNAL wire_nllllOii_dataout : STD_LOGIC; + SIGNAL wire_nllllOil_dataout : STD_LOGIC; + SIGNAL wire_nllllOiO_dataout : STD_LOGIC; + SIGNAL wire_nllllOli_dataout : STD_LOGIC; + SIGNAL wire_nllllOll_dataout : STD_LOGIC; + SIGNAL wire_nllllOlO_dataout : STD_LOGIC; + SIGNAL wire_nllllOOi_dataout : STD_LOGIC; + SIGNAL wire_nllllOOl_dataout : STD_LOGIC; + SIGNAL wire_nllllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlllO00i_dataout : STD_LOGIC; + SIGNAL wire_nlllO00l_dataout : STD_LOGIC; + SIGNAL wire_nlllO00O_dataout : STD_LOGIC; + SIGNAL wire_nlllO01i_dataout : STD_LOGIC; + SIGNAL wire_nlllO01l_dataout : STD_LOGIC; + SIGNAL wire_nlllO01O_dataout : STD_LOGIC; + SIGNAL wire_nlllO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlllO0il_dataout : STD_LOGIC; + SIGNAL wire_nlllO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlllO10i_dataout : STD_LOGIC; + SIGNAL wire_nlllO10l_dataout : STD_LOGIC; + SIGNAL wire_nlllO10O_dataout : STD_LOGIC; + SIGNAL wire_nlllO11i_dataout : STD_LOGIC; + SIGNAL wire_nlllO11l_dataout : STD_LOGIC; + SIGNAL wire_nlllO11O_dataout : STD_LOGIC; + SIGNAL wire_nlllO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlllO1il_dataout : STD_LOGIC; + SIGNAL wire_nlllO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlllO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlllO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlllOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlllOl0O_w_lg_dataout4591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlllOl0O_w_lg_dataout4679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlllOlii_dataout : STD_LOGIC; + SIGNAL wire_nlllOlil_dataout : STD_LOGIC; + SIGNAL wire_nlllOliO_dataout : STD_LOGIC; + SIGNAL wire_nlllOlli_dataout : STD_LOGIC; + SIGNAL wire_nllO0iii_dataout : STD_LOGIC; + SIGNAL wire_nllO0iil_dataout : STD_LOGIC; + SIGNAL wire_nllO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nllO0ili_dataout : STD_LOGIC; + SIGNAL wire_nllO0ill_dataout : STD_LOGIC; + SIGNAL wire_nllO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nllO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nllO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nllO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nllO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nllO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nllO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nllO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nllO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nllO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nllO0lii_dataout : STD_LOGIC; + SIGNAL wire_nllO0lil_dataout : STD_LOGIC; + SIGNAL wire_nllO0liO_dataout : STD_LOGIC; + SIGNAL wire_nllO0lli_dataout : STD_LOGIC; + SIGNAL wire_nllO0lll_dataout : STD_LOGIC; + SIGNAL wire_nllO0llO_dataout : STD_LOGIC; + SIGNAL wire_nllO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nllO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nllO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nllO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nllO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nllO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nllO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nllO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nllO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nllO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nllO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nllO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nllO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nllO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nllO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nllO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nllO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nllO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nllOi00i_dataout : STD_LOGIC; + SIGNAL wire_nllOi00l_dataout : STD_LOGIC; + SIGNAL wire_nllOi00O_dataout : STD_LOGIC; + SIGNAL wire_nllOi01i_dataout : STD_LOGIC; + SIGNAL wire_nllOi01l_dataout : STD_LOGIC; + SIGNAL wire_nllOi01O_dataout : STD_LOGIC; + SIGNAL wire_nllOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nllOi0il_dataout : STD_LOGIC; + SIGNAL wire_nllOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nllOi0li_dataout : STD_LOGIC; + SIGNAL wire_nllOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nllOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nllOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nllOi10i_dataout : STD_LOGIC; + SIGNAL wire_nllOi10l_dataout : STD_LOGIC; + SIGNAL wire_nllOi10O_dataout : STD_LOGIC; + SIGNAL wire_nllOi11i_dataout : STD_LOGIC; + SIGNAL wire_nllOi11l_dataout : STD_LOGIC; + SIGNAL wire_nllOi11O_dataout : STD_LOGIC; + SIGNAL wire_nllOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nllOi1il_dataout : STD_LOGIC; + SIGNAL wire_nllOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nllOi1li_dataout : STD_LOGIC; + SIGNAL wire_nllOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nllOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nllOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nllOii0i_dataout : STD_LOGIC; + SIGNAL wire_nllOii0l_dataout : STD_LOGIC; + SIGNAL wire_nllOii0O_dataout : STD_LOGIC; + SIGNAL wire_nllOii1i_dataout : STD_LOGIC; + SIGNAL wire_nllOii1l_dataout : STD_LOGIC; + SIGNAL wire_nllOii1O_dataout : STD_LOGIC; + SIGNAL wire_nllOiiii_dataout : STD_LOGIC; + SIGNAL wire_nllOiiil_dataout : STD_LOGIC; + SIGNAL wire_nllOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nllOiili_dataout : STD_LOGIC; + SIGNAL wire_nllOiill_dataout : STD_LOGIC; + SIGNAL wire_nllOiilO_dataout : STD_LOGIC; + SIGNAL wire_nllOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nllOil0i_dataout : STD_LOGIC; + SIGNAL wire_nllOil0l_dataout : STD_LOGIC; + SIGNAL wire_nllOil0O_dataout : STD_LOGIC; + SIGNAL wire_nllOil1i_dataout : STD_LOGIC; + SIGNAL wire_nllOil1l_dataout : STD_LOGIC; + SIGNAL wire_nllOil1O_dataout : STD_LOGIC; + SIGNAL wire_nllOilii_dataout : STD_LOGIC; + SIGNAL wire_nllOiliii_dataout : STD_LOGIC; + SIGNAL wire_nllOiliil_dataout : STD_LOGIC; + SIGNAL wire_nllOiliiO_dataout : STD_LOGIC; + SIGNAL wire_nllOilil_dataout : STD_LOGIC; + SIGNAL wire_nllOilili_dataout : STD_LOGIC; + SIGNAL wire_nllOilill_dataout : STD_LOGIC; + SIGNAL wire_nllOililO_dataout : STD_LOGIC; + SIGNAL wire_nllOiliO_dataout : STD_LOGIC; + SIGNAL wire_nllOiliOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiliOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiliOO_dataout : STD_LOGIC; + SIGNAL wire_nllOill0i_dataout : STD_LOGIC; + SIGNAL wire_nllOill0l_dataout : STD_LOGIC; + SIGNAL wire_nllOill0O_dataout : STD_LOGIC; + SIGNAL wire_nllOill1i_dataout : STD_LOGIC; + SIGNAL wire_nllOill1l_dataout : STD_LOGIC; + SIGNAL wire_nllOill1O_dataout : STD_LOGIC; + SIGNAL wire_nllOilli_dataout : STD_LOGIC; + SIGNAL wire_nllOillii_dataout : STD_LOGIC; + SIGNAL wire_nllOillil_dataout : STD_LOGIC; + SIGNAL wire_nllOilliO_dataout : STD_LOGIC; + SIGNAL wire_nllOilll_dataout : STD_LOGIC; + SIGNAL wire_nllOillli_dataout : STD_LOGIC; + SIGNAL wire_nllOillll_dataout : STD_LOGIC; + SIGNAL wire_nllOilllO_dataout : STD_LOGIC; + SIGNAL wire_nllOillO_dataout : STD_LOGIC; + SIGNAL wire_nllOillOi_dataout : STD_LOGIC; + SIGNAL wire_nllOillOl_dataout : STD_LOGIC; + SIGNAL wire_nllOillOO_dataout : STD_LOGIC; + SIGNAL wire_nllOilO0i_dataout : STD_LOGIC; + SIGNAL wire_nllOilO0l_dataout : STD_LOGIC; + SIGNAL wire_nllOilO0O_dataout : STD_LOGIC; + SIGNAL wire_nllOilO1i_dataout : STD_LOGIC; + SIGNAL wire_nllOilO1l_dataout : STD_LOGIC; + SIGNAL wire_nllOilO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOilOi_dataout : STD_LOGIC; + SIGNAL wire_nllOilOii_dataout : STD_LOGIC; + SIGNAL wire_nllOilOil_dataout : STD_LOGIC; + SIGNAL wire_nllOilOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOilOl_dataout : STD_LOGIC; + SIGNAL wire_nllOilOli_dataout : STD_LOGIC; + SIGNAL wire_nllOilOll_dataout : STD_LOGIC; + SIGNAL wire_nllOilOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOilOO_dataout : STD_LOGIC; + SIGNAL wire_nllOilOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOilOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOilOOO_dataout : STD_LOGIC; + SIGNAL wire_nllOiO00i_dataout : STD_LOGIC; + SIGNAL wire_nllOiO00l_dataout : STD_LOGIC; + SIGNAL wire_nllOiO00O_dataout : STD_LOGIC; + SIGNAL wire_nllOiO01i_dataout : STD_LOGIC; + SIGNAL wire_nllOiO01l_dataout : STD_LOGIC; + SIGNAL wire_nllOiO01O_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0ii_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0il_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0li_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0ll_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0lO_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOiO0OO_dataout : STD_LOGIC; + SIGNAL wire_nllOiO10i_dataout : STD_LOGIC; + SIGNAL wire_nllOiO10l_dataout : STD_LOGIC; + SIGNAL wire_nllOiO10O_dataout : STD_LOGIC; + SIGNAL wire_nllOiO11i_dataout : STD_LOGIC; + SIGNAL wire_nllOiO11l_dataout : STD_LOGIC; + SIGNAL wire_nllOiO11O_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1ii_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1il_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1iO_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1li_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1ll_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1lO_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi0i_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi0l_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi1i_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi1l_dataout : STD_LOGIC; + SIGNAL wire_nllOiOi1O_dataout : STD_LOGIC; + SIGNAL wire_nllOiOii_dataout : STD_LOGIC; + SIGNAL wire_nllOiOiii_dataout : STD_LOGIC; + SIGNAL wire_nllOiOiil_dataout : STD_LOGIC; + SIGNAL wire_nllOiOiiO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOil_dataout : STD_LOGIC; + SIGNAL wire_nllOiOili_dataout : STD_LOGIC; + SIGNAL wire_nllOiOill_dataout : STD_LOGIC; + SIGNAL wire_nllOiOilO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOiOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nllOiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nllOiOli_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlii_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlil_dataout : STD_LOGIC; + SIGNAL wire_nllOiOliO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOll_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlli_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlll_dataout : STD_LOGIC; + SIGNAL wire_nllOiOllO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO0O_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nllOiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOii_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOil_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOli_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOll_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nllOl00i_dataout : STD_LOGIC; + SIGNAL wire_nllOl00l_dataout : STD_LOGIC; + SIGNAL wire_nllOl00O_dataout : STD_LOGIC; + SIGNAL wire_nllOl01i_dataout : STD_LOGIC; + SIGNAL wire_nllOl01l_dataout : STD_LOGIC; + SIGNAL wire_nllOl01O_dataout : STD_LOGIC; + SIGNAL wire_nllOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nllOl0il_dataout : STD_LOGIC; + SIGNAL wire_nllOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nllOl0li_dataout : STD_LOGIC; + SIGNAL wire_nllOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nllOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nllOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nllOl10i_dataout : STD_LOGIC; + SIGNAL wire_nllOl10l_dataout : STD_LOGIC; + SIGNAL wire_nllOl10O_dataout : STD_LOGIC; + SIGNAL wire_nllOl110i_dataout : STD_LOGIC; + SIGNAL wire_nllOl110l_dataout : STD_LOGIC; + SIGNAL wire_nllOl110O_dataout : STD_LOGIC; + SIGNAL wire_nllOl111i_dataout : STD_LOGIC; + SIGNAL wire_nllOl111l_dataout : STD_LOGIC; + SIGNAL wire_nllOl111O_dataout : STD_LOGIC; + SIGNAL wire_nllOl11i_dataout : STD_LOGIC; + SIGNAL wire_nllOl11ii_dataout : STD_LOGIC; + SIGNAL wire_nllOl11il_dataout : STD_LOGIC; + SIGNAL wire_nllOl11iO_dataout : STD_LOGIC; + SIGNAL wire_nllOl11l_dataout : STD_LOGIC; + SIGNAL wire_nllOl11li_dataout : STD_LOGIC; + SIGNAL wire_nllOl11ll_dataout : STD_LOGIC; + SIGNAL wire_nllOl11lO_dataout : STD_LOGIC; + SIGNAL wire_nllOl11O_dataout : STD_LOGIC; + SIGNAL wire_nllOl11Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOl11Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nllOl1il_dataout : STD_LOGIC; + SIGNAL wire_nllOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nllOl1li_dataout : STD_LOGIC; + SIGNAL wire_nllOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nllOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nllOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nllOli0i_dataout : STD_LOGIC; + SIGNAL wire_nllOli0l_dataout : STD_LOGIC; + SIGNAL wire_nllOli0O_dataout : STD_LOGIC; + SIGNAL wire_nllOli1i_dataout : STD_LOGIC; + SIGNAL wire_nllOli1l_dataout : STD_LOGIC; + SIGNAL wire_nllOli1O_dataout : STD_LOGIC; + SIGNAL wire_nllOliii_dataout : STD_LOGIC; + SIGNAL wire_nllOliil_dataout : STD_LOGIC; + SIGNAL wire_nllOliiO_dataout : STD_LOGIC; + SIGNAL wire_nllOlili_dataout : STD_LOGIC; + SIGNAL wire_nllOlill_dataout : STD_LOGIC; + SIGNAL wire_nllOlilO_dataout : STD_LOGIC; + SIGNAL wire_nllOliOi_dataout : STD_LOGIC; + SIGNAL wire_nllOliOl_dataout : STD_LOGIC; + SIGNAL wire_nllOliOO_dataout : STD_LOGIC; + SIGNAL wire_nllOll0i_dataout : STD_LOGIC; + SIGNAL wire_nllOll0l_dataout : STD_LOGIC; + SIGNAL wire_nllOll0O_dataout : STD_LOGIC; + SIGNAL wire_nllOll1i_dataout : STD_LOGIC; + SIGNAL wire_nllOll1l_dataout : STD_LOGIC; + SIGNAL wire_nllOll1O_dataout : STD_LOGIC; + SIGNAL wire_nllOllii_dataout : STD_LOGIC; + SIGNAL wire_nllOllil_dataout : STD_LOGIC; + SIGNAL wire_nllOlliO_dataout : STD_LOGIC; + SIGNAL wire_nllOllli_dataout : STD_LOGIC; + SIGNAL wire_nllOllll_dataout : STD_LOGIC; + SIGNAL wire_nllOlllO_dataout : STD_LOGIC; + SIGNAL wire_nllOllOi_dataout : STD_LOGIC; + SIGNAL wire_nllOllOl_dataout : STD_LOGIC; + SIGNAL wire_nllOllOO_dataout : STD_LOGIC; + SIGNAL wire_nllOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nllOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nllOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nllOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nllOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nllOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOlOii_dataout : STD_LOGIC; + SIGNAL wire_nllOlOil_dataout : STD_LOGIC; + SIGNAL wire_nllOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOlOli_dataout : STD_LOGIC; + SIGNAL wire_nllOlOll_dataout : STD_LOGIC; + SIGNAL wire_nllOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nllOO00i_dataout : STD_LOGIC; + SIGNAL wire_nllOO00l_dataout : STD_LOGIC; + SIGNAL wire_nllOO00O_dataout : STD_LOGIC; + SIGNAL wire_nllOO01i_dataout : STD_LOGIC; + SIGNAL wire_nllOO01l_dataout : STD_LOGIC; + SIGNAL wire_nllOO01O_dataout : STD_LOGIC; + SIGNAL wire_nllOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nllOO0il_dataout : STD_LOGIC; + SIGNAL wire_nllOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nllOO0li_dataout : STD_LOGIC; + SIGNAL wire_nllOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nllOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nllOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nllOO10i_dataout : STD_LOGIC; + SIGNAL wire_nllOO10l_dataout : STD_LOGIC; + SIGNAL wire_nllOO10O_dataout : STD_LOGIC; + SIGNAL wire_nllOO11i_dataout : STD_LOGIC; + SIGNAL wire_nllOO11l_dataout : STD_LOGIC; + SIGNAL wire_nllOO11O_dataout : STD_LOGIC; + SIGNAL wire_nllOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nllOO1il_dataout : STD_LOGIC; + SIGNAL wire_nllOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nllOO1li_dataout : STD_LOGIC; + SIGNAL wire_nllOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nllOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nllOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nllOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nllOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nllOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nllOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nllOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nllOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nllOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nllOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nllOOiii_dataout : STD_LOGIC; + SIGNAL wire_nllOOiil_dataout : STD_LOGIC; + SIGNAL wire_nllOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nllOOili_dataout : STD_LOGIC; + SIGNAL wire_nllOOill_dataout : STD_LOGIC; + SIGNAL wire_nllOOilO_dataout : STD_LOGIC; + SIGNAL wire_nllOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nllOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nllOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nllOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nllOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nllOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nllOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nllOOlii_dataout : STD_LOGIC; + SIGNAL wire_nllOOlil_dataout : STD_LOGIC; + SIGNAL wire_nllOOliO_dataout : STD_LOGIC; + SIGNAL wire_nllOOlli_dataout : STD_LOGIC; + SIGNAL wire_nllOOlll_dataout : STD_LOGIC; + SIGNAL wire_nllOOllO_dataout : STD_LOGIC; + SIGNAL wire_nllOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nllOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nllOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nllOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nllOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nllOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nllOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nllOOOii_dataout : STD_LOGIC; + SIGNAL wire_nllOOOil_dataout : STD_LOGIC; + SIGNAL wire_nllOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nllOOOli_dataout : STD_LOGIC; + SIGNAL wire_nllOOOll_dataout : STD_LOGIC; + SIGNAL wire_nllOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nllOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nllOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nllOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00000i_dataout : STD_LOGIC; + SIGNAL wire_nlO00000l_dataout : STD_LOGIC; + SIGNAL wire_nlO00000O_dataout : STD_LOGIC; + SIGNAL wire_nlO00001i_dataout : STD_LOGIC; + SIGNAL wire_nlO00001l_dataout : STD_LOGIC; + SIGNAL wire_nlO00001O_dataout : STD_LOGIC; + SIGNAL wire_nlO0000i_dataout : STD_LOGIC; + SIGNAL wire_nlO0000ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0000il_dataout : STD_LOGIC; + SIGNAL wire_nlO0000iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0000l_dataout : STD_LOGIC; + SIGNAL wire_nlO0000li_dataout : STD_LOGIC; + SIGNAL wire_nlO0000ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0000lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0000O_dataout : STD_LOGIC; + SIGNAL wire_nlO0000Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0000Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0000OO_dataout : STD_LOGIC; + SIGNAL wire_nlO00010i_dataout : STD_LOGIC; + SIGNAL wire_nlO00010l_dataout : STD_LOGIC; + SIGNAL wire_nlO00010O_dataout : STD_LOGIC; + SIGNAL wire_nlO00011i_dataout : STD_LOGIC; + SIGNAL wire_nlO00011l_dataout : STD_LOGIC; + SIGNAL wire_nlO00011O_dataout : STD_LOGIC; + SIGNAL wire_nlO0001i_dataout : STD_LOGIC; + SIGNAL wire_nlO0001ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0001il_dataout : STD_LOGIC; + SIGNAL wire_nlO0001iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0001l_dataout : STD_LOGIC; + SIGNAL wire_nlO0001li_dataout : STD_LOGIC; + SIGNAL wire_nlO0001ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0001lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0001O_dataout : STD_LOGIC; + SIGNAL wire_nlO0001Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0001Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0001OO_dataout : STD_LOGIC; + SIGNAL wire_nlO000i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO000i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO000i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO000i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO000i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO000i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO000ii_dataout : STD_LOGIC; + SIGNAL wire_nlO000iii_dataout : STD_LOGIC; + SIGNAL wire_nlO000iil_dataout : STD_LOGIC; + SIGNAL wire_nlO000iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO000il_dataout : STD_LOGIC; + SIGNAL wire_nlO000ili_dataout : STD_LOGIC; + SIGNAL wire_nlO000ill_dataout : STD_LOGIC; + SIGNAL wire_nlO000ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO000iO_dataout : STD_LOGIC; + SIGNAL wire_nlO000iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO000iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO000iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO000l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO000l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO000l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO000l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO000l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO000l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO000li_dataout : STD_LOGIC; + SIGNAL wire_nlO000lii_dataout : STD_LOGIC; + SIGNAL wire_nlO000lil_dataout : STD_LOGIC; + SIGNAL wire_nlO000liO_dataout : STD_LOGIC; + SIGNAL wire_nlO000ll_dataout : STD_LOGIC; + SIGNAL wire_nlO000lli_dataout : STD_LOGIC; + SIGNAL wire_nlO000lll_dataout : STD_LOGIC; + SIGNAL wire_nlO000llO_dataout : STD_LOGIC; + SIGNAL wire_nlO000lO_dataout : STD_LOGIC; + SIGNAL wire_nlO000lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO000lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO000lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO000O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO000O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO000O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO000O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO000O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO000O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO000Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO000Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO000Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO000OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO000Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO000Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO000Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO000OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO000OO_dataout : STD_LOGIC; + SIGNAL wire_nlO000OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO000OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO000OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00100i_dataout : STD_LOGIC; + SIGNAL wire_nlO00100l_dataout : STD_LOGIC; + SIGNAL wire_nlO00100O_dataout : STD_LOGIC; + SIGNAL wire_nlO00101i_dataout : STD_LOGIC; + SIGNAL wire_nlO00101l_dataout : STD_LOGIC; + SIGNAL wire_nlO00101O_dataout : STD_LOGIC; + SIGNAL wire_nlO0010i_dataout : STD_LOGIC; + SIGNAL wire_nlO0010ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0010il_dataout : STD_LOGIC; + SIGNAL wire_nlO0010iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0010l_dataout : STD_LOGIC; + SIGNAL wire_nlO0010li_dataout : STD_LOGIC; + SIGNAL wire_nlO0010ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0010lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0010O_dataout : STD_LOGIC; + SIGNAL wire_nlO0010Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0010Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0010OO_dataout : STD_LOGIC; + SIGNAL wire_nlO00110i_dataout : STD_LOGIC; + SIGNAL wire_nlO00110l_dataout : STD_LOGIC; + SIGNAL wire_nlO00110O_dataout : STD_LOGIC; + SIGNAL wire_nlO00111i_dataout : STD_LOGIC; + SIGNAL wire_nlO00111l_dataout : STD_LOGIC; + SIGNAL wire_nlO00111O_dataout : STD_LOGIC; + SIGNAL wire_nlO0011i_dataout : STD_LOGIC; + SIGNAL wire_nlO0011ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0011il_dataout : STD_LOGIC; + SIGNAL wire_nlO0011iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0011l_dataout : STD_LOGIC; + SIGNAL wire_nlO0011li_dataout : STD_LOGIC; + SIGNAL wire_nlO0011ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0011lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0011O_dataout : STD_LOGIC; + SIGNAL wire_nlO0011Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0011Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0011OO_dataout : STD_LOGIC; + SIGNAL wire_nlO001i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO001i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO001i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO001i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO001i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO001i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO001ii_dataout : STD_LOGIC; + SIGNAL wire_nlO001iii_dataout : STD_LOGIC; + SIGNAL wire_nlO001iil_dataout : STD_LOGIC; + SIGNAL wire_nlO001iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO001il_dataout : STD_LOGIC; + SIGNAL wire_nlO001ili_dataout : STD_LOGIC; + SIGNAL wire_nlO001ill_dataout : STD_LOGIC; + SIGNAL wire_nlO001ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO001iO_dataout : STD_LOGIC; + SIGNAL wire_nlO001iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO001iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO001iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO001l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO001l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO001l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO001l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO001l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO001l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO001li_dataout : STD_LOGIC; + SIGNAL wire_nlO001lii_dataout : STD_LOGIC; + SIGNAL wire_nlO001lil_dataout : STD_LOGIC; + SIGNAL wire_nlO001liO_dataout : STD_LOGIC; + SIGNAL wire_nlO001ll_dataout : STD_LOGIC; + SIGNAL wire_nlO001lli_dataout : STD_LOGIC; + SIGNAL wire_nlO001lll_dataout : STD_LOGIC; + SIGNAL wire_nlO001llO_dataout : STD_LOGIC; + SIGNAL wire_nlO001lO_dataout : STD_LOGIC; + SIGNAL wire_nlO001lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO001lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO001lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO001O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO001O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO001O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO001O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO001O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO001O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO001Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO001Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO001Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO001OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO001Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO001Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO001Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO001OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO001OO_dataout : STD_LOGIC; + SIGNAL wire_nlO001OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO001OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO001OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i00i_dataout : STD_LOGIC; + SIGNAL wire_nlO00i00l_dataout : STD_LOGIC; + SIGNAL wire_nlO00i00O_dataout : STD_LOGIC; + SIGNAL wire_nlO00i01i_dataout : STD_LOGIC; + SIGNAL wire_nlO00i01l_dataout : STD_LOGIC; + SIGNAL wire_nlO00i01O_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0il_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0li_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO00i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i10i_dataout : STD_LOGIC; + SIGNAL wire_nlO00i10l_dataout : STD_LOGIC; + SIGNAL wire_nlO00i10O_dataout : STD_LOGIC; + SIGNAL wire_nlO00i11i_dataout : STD_LOGIC; + SIGNAL wire_nlO00i11l_dataout : STD_LOGIC; + SIGNAL wire_nlO00i11O_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1il_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1li_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO00i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO00ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00iii_dataout : STD_LOGIC; + SIGNAL wire_nlO00iiii_dataout : STD_LOGIC; + SIGNAL wire_nlO00iiil_dataout : STD_LOGIC; + SIGNAL wire_nlO00iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO00iil_dataout : STD_LOGIC; + SIGNAL wire_nlO00iili_dataout : STD_LOGIC; + SIGNAL wire_nlO00iill_dataout : STD_LOGIC; + SIGNAL wire_nlO00iilO_dataout : STD_LOGIC; + SIGNAL wire_nlO00iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO00iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00il0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00il0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00il0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00il1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00il1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00il1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00ili_dataout : STD_LOGIC; + SIGNAL wire_nlO00ilii_dataout : STD_LOGIC; + SIGNAL wire_nlO00ilil_dataout : STD_LOGIC; + SIGNAL wire_nlO00iliO_dataout : STD_LOGIC; + SIGNAL wire_nlO00ill_dataout : STD_LOGIC; + SIGNAL wire_nlO00illi_dataout : STD_LOGIC; + SIGNAL wire_nlO00illl_dataout : STD_LOGIC; + SIGNAL wire_nlO00illO_dataout : STD_LOGIC; + SIGNAL wire_nlO00ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO00ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOii_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOil_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOli_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOll_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00l00i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l00l_dataout : STD_LOGIC; + SIGNAL wire_nlO00l00O_dataout : STD_LOGIC; + SIGNAL wire_nlO00l01i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l01l_dataout : STD_LOGIC; + SIGNAL wire_nlO00l01O_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0il_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0li_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO00l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO00l10i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l10l_dataout : STD_LOGIC; + SIGNAL wire_nlO00l10O_dataout : STD_LOGIC; + SIGNAL wire_nlO00l11i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l11l_dataout : STD_LOGIC; + SIGNAL wire_nlO00l11O_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1il_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1li_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO00l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO00li0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00li0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00li0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00li1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00li1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00li1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00lii_dataout : STD_LOGIC; + SIGNAL wire_nlO00liii_dataout : STD_LOGIC; + SIGNAL wire_nlO00liil_dataout : STD_LOGIC; + SIGNAL wire_nlO00liiO_dataout : STD_LOGIC; + SIGNAL wire_nlO00lil_dataout : STD_LOGIC; + SIGNAL wire_nlO00lili_dataout : STD_LOGIC; + SIGNAL wire_nlO00lill_dataout : STD_LOGIC; + SIGNAL wire_nlO00lilO_dataout : STD_LOGIC; + SIGNAL wire_nlO00liO_dataout : STD_LOGIC; + SIGNAL wire_nlO00liOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00liOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00liOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00lli_dataout : STD_LOGIC; + SIGNAL wire_nlO00llii_dataout : STD_LOGIC; + SIGNAL wire_nlO00llil_dataout : STD_LOGIC; + SIGNAL wire_nlO00lliO_dataout : STD_LOGIC; + SIGNAL wire_nlO00lll_dataout : STD_LOGIC; + SIGNAL wire_nlO00llli_dataout : STD_LOGIC; + SIGNAL wire_nlO00llll_dataout : STD_LOGIC; + SIGNAL wire_nlO00lllO_dataout : STD_LOGIC; + SIGNAL wire_nlO00llO_dataout : STD_LOGIC; + SIGNAL wire_nlO00llOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00llOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00llOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00O00i_dataout : STD_LOGIC; + SIGNAL wire_nlO00O00l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O00O_dataout : STD_LOGIC; + SIGNAL wire_nlO00O01i_dataout : STD_LOGIC; + SIGNAL wire_nlO00O01l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O01O_dataout : STD_LOGIC; + SIGNAL wire_nlO00O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO00O0il_dataout : STD_LOGIC; + SIGNAL wire_nlO00O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO00O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00O10i_dataout : STD_LOGIC; + SIGNAL wire_nlO00O10l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O10O_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1il_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1li_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO00O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO00Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO00OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO00Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO00Oili_dataout : STD_LOGIC; + SIGNAL wire_nlO00Oill_dataout : STD_LOGIC; + SIGNAL wire_nlO00OilO_dataout : STD_LOGIC; + SIGNAL wire_nlO00OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO00OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlO00Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlO00Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlO00Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO00Olii_dataout : STD_LOGIC; + SIGNAL wire_nlO00Olil_dataout : STD_LOGIC; + SIGNAL wire_nlO00OliO_dataout : STD_LOGIC; + SIGNAL wire_nlO00Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO00Olli_dataout : STD_LOGIC; + SIGNAL wire_nlO00Olll_dataout : STD_LOGIC; + SIGNAL wire_nlO00OllO_dataout : STD_LOGIC; + SIGNAL wire_nlO00OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO00OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO00OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO00OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOil_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO00OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01000i_dataout : STD_LOGIC; + SIGNAL wire_nlO01000l_dataout : STD_LOGIC; + SIGNAL wire_nlO01000O_dataout : STD_LOGIC; + SIGNAL wire_nlO01001i_dataout : STD_LOGIC; + SIGNAL wire_nlO01001l_dataout : STD_LOGIC; + SIGNAL wire_nlO01001O_dataout : STD_LOGIC; + SIGNAL wire_nlO0100i_dataout : STD_LOGIC; + SIGNAL wire_nlO0100ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0100il_dataout : STD_LOGIC; + SIGNAL wire_nlO0100iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0100l_dataout : STD_LOGIC; + SIGNAL wire_nlO0100li_dataout : STD_LOGIC; + SIGNAL wire_nlO0100ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0100lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0100O_dataout : STD_LOGIC; + SIGNAL wire_nlO0100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0100Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0100OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01010i_dataout : STD_LOGIC; + SIGNAL wire_nlO01010l_dataout : STD_LOGIC; + SIGNAL wire_nlO01010O_dataout : STD_LOGIC; + SIGNAL wire_nlO01011i_dataout : STD_LOGIC; + SIGNAL wire_nlO01011l_dataout : STD_LOGIC; + SIGNAL wire_nlO01011O_dataout : STD_LOGIC; + SIGNAL wire_nlO0101i_dataout : STD_LOGIC; + SIGNAL wire_nlO0101ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0101il_dataout : STD_LOGIC; + SIGNAL wire_nlO0101iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0101l_dataout : STD_LOGIC; + SIGNAL wire_nlO0101li_dataout : STD_LOGIC; + SIGNAL wire_nlO0101ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0101lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0101O_dataout : STD_LOGIC; + SIGNAL wire_nlO0101Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0101Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0101OO_dataout : STD_LOGIC; + SIGNAL wire_nlO010i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO010i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO010i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO010i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO010i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO010i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO010ii_dataout : STD_LOGIC; + SIGNAL wire_nlO010iii_dataout : STD_LOGIC; + SIGNAL wire_nlO010iil_dataout : STD_LOGIC; + SIGNAL wire_nlO010iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO010il_dataout : STD_LOGIC; + SIGNAL wire_nlO010ili_dataout : STD_LOGIC; + SIGNAL wire_nlO010ill_dataout : STD_LOGIC; + SIGNAL wire_nlO010ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO010iO_dataout : STD_LOGIC; + SIGNAL wire_nlO010iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO010iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO010iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO010l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO010l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO010l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO010l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO010l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO010l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO010li_dataout : STD_LOGIC; + SIGNAL wire_nlO010lii_dataout : STD_LOGIC; + SIGNAL wire_nlO010lil_dataout : STD_LOGIC; + SIGNAL wire_nlO010liO_dataout : STD_LOGIC; + SIGNAL wire_nlO010ll_dataout : STD_LOGIC; + SIGNAL wire_nlO010lli_dataout : STD_LOGIC; + SIGNAL wire_nlO010lll_dataout : STD_LOGIC; + SIGNAL wire_nlO010llO_dataout : STD_LOGIC; + SIGNAL wire_nlO010lO_dataout : STD_LOGIC; + SIGNAL wire_nlO010lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO010lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO010lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO010O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO010O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO010O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO010O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO010O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO010O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO010Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO010Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO010Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO010OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO010Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO010Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO010Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO010OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO010OO_dataout : STD_LOGIC; + SIGNAL wire_nlO010OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO010OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO010OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01100i_dataout : STD_LOGIC; + SIGNAL wire_nlO01100l_dataout : STD_LOGIC; + SIGNAL wire_nlO01100O_dataout : STD_LOGIC; + SIGNAL wire_nlO01101l_dataout : STD_LOGIC; + SIGNAL wire_nlO01101O_dataout : STD_LOGIC; + SIGNAL wire_nlO0110i_dataout : STD_LOGIC; + SIGNAL wire_nlO0110ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0110il_dataout : STD_LOGIC; + SIGNAL wire_nlO0110iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0110l_dataout : STD_LOGIC; + SIGNAL wire_nlO0110li_dataout : STD_LOGIC; + SIGNAL wire_nlO0110ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0110lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0110O_dataout : STD_LOGIC; + SIGNAL wire_nlO0110Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0110Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0110OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01110i_dataout : STD_LOGIC; + SIGNAL wire_nlO01110l_dataout : STD_LOGIC; + SIGNAL wire_nlO01110O_dataout : STD_LOGIC; + SIGNAL wire_nlO01111i_dataout : STD_LOGIC; + SIGNAL wire_nlO01111l_dataout : STD_LOGIC; + SIGNAL wire_nlO01111O_dataout : STD_LOGIC; + SIGNAL wire_nlO0111i_dataout : STD_LOGIC; + SIGNAL wire_nlO0111ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0111il_dataout : STD_LOGIC; + SIGNAL wire_nlO0111iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0111l_dataout : STD_LOGIC; + SIGNAL wire_nlO0111li_dataout : STD_LOGIC; + SIGNAL wire_nlO0111ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0111lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0111O_dataout : STD_LOGIC; + SIGNAL wire_nlO011i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO011i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO011i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO011i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO011i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO011i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO011ii_dataout : STD_LOGIC; + SIGNAL wire_nlO011iii_dataout : STD_LOGIC; + SIGNAL wire_nlO011iil_dataout : STD_LOGIC; + SIGNAL wire_nlO011iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO011il_dataout : STD_LOGIC; + SIGNAL wire_nlO011ili_dataout : STD_LOGIC; + SIGNAL wire_nlO011ill_dataout : STD_LOGIC; + SIGNAL wire_nlO011ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO011iO_dataout : STD_LOGIC; + SIGNAL wire_nlO011iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO011iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO011iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO011l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO011l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO011l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO011l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO011l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO011l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO011li_dataout : STD_LOGIC; + SIGNAL wire_nlO011lii_dataout : STD_LOGIC; + SIGNAL wire_nlO011lil_dataout : STD_LOGIC; + SIGNAL wire_nlO011liO_dataout : STD_LOGIC; + SIGNAL wire_nlO011ll_dataout : STD_LOGIC; + SIGNAL wire_nlO011lli_dataout : STD_LOGIC; + SIGNAL wire_nlO011lll_dataout : STD_LOGIC; + SIGNAL wire_nlO011llO_dataout : STD_LOGIC; + SIGNAL wire_nlO011lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO011lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO011lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO011O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO011O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO011O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO011O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO011O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO011O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO011Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO011Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO011OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO011Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO011Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO011Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO011OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO011OO_dataout : STD_LOGIC; + SIGNAL wire_nlO011OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO011OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO011OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01i00i_dataout : STD_LOGIC; + SIGNAL wire_nlO01i00l_dataout : STD_LOGIC; + SIGNAL wire_nlO01i00O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i01i_dataout : STD_LOGIC; + SIGNAL wire_nlO01i01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01i01O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0il_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0li_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO01i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01i10i_dataout : STD_LOGIC; + SIGNAL wire_nlO01i10l_dataout : STD_LOGIC; + SIGNAL wire_nlO01i10O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i11i_dataout : STD_LOGIC; + SIGNAL wire_nlO01i11l_dataout : STD_LOGIC; + SIGNAL wire_nlO01i11O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1il_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1li_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO01i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01iii_dataout : STD_LOGIC; + SIGNAL wire_nlO01iiii_dataout : STD_LOGIC; + SIGNAL wire_nlO01iiil_dataout : STD_LOGIC; + SIGNAL wire_nlO01iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01iil_dataout : STD_LOGIC; + SIGNAL wire_nlO01iili_dataout : STD_LOGIC; + SIGNAL wire_nlO01iill_dataout : STD_LOGIC; + SIGNAL wire_nlO01iilO_dataout : STD_LOGIC; + SIGNAL wire_nlO01iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01il0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01il0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01il0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01il1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01il1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01il1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01ili_dataout : STD_LOGIC; + SIGNAL wire_nlO01ilii_dataout : STD_LOGIC; + SIGNAL wire_nlO01ilil_dataout : STD_LOGIC; + SIGNAL wire_nlO01iliO_dataout : STD_LOGIC; + SIGNAL wire_nlO01ill_dataout : STD_LOGIC; + SIGNAL wire_nlO01illi_dataout : STD_LOGIC; + SIGNAL wire_nlO01illl_dataout : STD_LOGIC; + SIGNAL wire_nlO01illO_dataout : STD_LOGIC; + SIGNAL wire_nlO01ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO01ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOii_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOil_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOli_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOll_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01l00i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l00l_dataout : STD_LOGIC; + SIGNAL wire_nlO01l00O_dataout : STD_LOGIC; + SIGNAL wire_nlO01l01i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01l01O_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0il_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0li_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO01l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01l10i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l10l_dataout : STD_LOGIC; + SIGNAL wire_nlO01l10O_dataout : STD_LOGIC; + SIGNAL wire_nlO01l11i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l11l_dataout : STD_LOGIC; + SIGNAL wire_nlO01l11O_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1il_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1li_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO01l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01li0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01li0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01li0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01li1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01li1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01li1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01lii_dataout : STD_LOGIC; + SIGNAL wire_nlO01liii_dataout : STD_LOGIC; + SIGNAL wire_nlO01liil_dataout : STD_LOGIC; + SIGNAL wire_nlO01liiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01lil_dataout : STD_LOGIC; + SIGNAL wire_nlO01lili_dataout : STD_LOGIC; + SIGNAL wire_nlO01lill_dataout : STD_LOGIC; + SIGNAL wire_nlO01lilO_dataout : STD_LOGIC; + SIGNAL wire_nlO01liO_dataout : STD_LOGIC; + SIGNAL wire_nlO01liOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01liOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01liOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01lli_dataout : STD_LOGIC; + SIGNAL wire_nlO01llii_dataout : STD_LOGIC; + SIGNAL wire_nlO01llil_dataout : STD_LOGIC; + SIGNAL wire_nlO01lliO_dataout : STD_LOGIC; + SIGNAL wire_nlO01lll_dataout : STD_LOGIC; + SIGNAL wire_nlO01llli_dataout : STD_LOGIC; + SIGNAL wire_nlO01llll_dataout : STD_LOGIC; + SIGNAL wire_nlO01lllO_dataout : STD_LOGIC; + SIGNAL wire_nlO01llO_dataout : STD_LOGIC; + SIGNAL wire_nlO01llOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01llOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01llOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOii_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOil_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOli_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOll_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01O00i_dataout : STD_LOGIC; + SIGNAL wire_nlO01O00l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O00O_dataout : STD_LOGIC; + SIGNAL wire_nlO01O01i_dataout : STD_LOGIC; + SIGNAL wire_nlO01O01l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O01O_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0il_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0li_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO01O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01O10i_dataout : STD_LOGIC; + SIGNAL wire_nlO01O10l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O10O_dataout : STD_LOGIC; + SIGNAL wire_nlO01O11i_dataout : STD_LOGIC; + SIGNAL wire_nlO01O11l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O11O_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1il_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1li_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO01O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlO01OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oili_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oill_dataout : STD_LOGIC; + SIGNAL wire_nlO01OilO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO01Olii_dataout : STD_LOGIC; + SIGNAL wire_nlO01Olil_dataout : STD_LOGIC; + SIGNAL wire_nlO01OliO_dataout : STD_LOGIC; + SIGNAL wire_nlO01Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO01Olli_dataout : STD_LOGIC; + SIGNAL wire_nlO01Olll_dataout : STD_LOGIC; + SIGNAL wire_nlO01OllO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO01OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO01OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO01OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO01OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO01OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOii_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOil_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOli_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOll_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO01OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i000i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i000l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i000O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i001i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i001l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i001O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00il_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00li_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0i00OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i010i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i010l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i010O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i011i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i011l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01il_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01li_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0i01OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i10l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i10O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i111i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i111l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i111O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lii_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lil_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1liO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lli_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lll_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1llO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0i1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iiii_dataout : STD_LOGIC; + SIGNAL wire_nlO0iiil_dataout : STD_LOGIC; + SIGNAL wire_nlO0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iili_dataout : STD_LOGIC; + SIGNAL wire_nlO0iill_dataout : STD_LOGIC; + SIGNAL wire_nlO0iilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0il0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0il0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0il0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0il1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0il1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0il1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ilii_dataout : STD_LOGIC; + SIGNAL wire_nlO0ilil_dataout : STD_LOGIC; + SIGNAL wire_nlO0iliO_dataout : STD_LOGIC; + SIGNAL wire_nlO0illi_dataout : STD_LOGIC; + SIGNAL wire_nlO0illl_dataout : STD_LOGIC; + SIGNAL wire_nlO0illO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlii_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlil_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOliO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlli_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlll_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOllO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0iOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l000i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l000l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l000O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l001i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l001l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l001O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00il_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00li_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0l00OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l010i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l010l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l010O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l011i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l011l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l011O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01il_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01li_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0l01OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0iii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0iil_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0ili_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0ill_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lil_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0liO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lli_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0llO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0l0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l100i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l100l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l100O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l101i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l101l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l101O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10il_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10li_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0l10OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l110i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l110l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l110O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l111i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l111l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l111O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11il_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11li_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0l11OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1iii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1iil_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1ili_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1ill_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lil_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1liO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lli_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1llO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0l1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0li00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0li00l_dataout : STD_LOGIC; + SIGNAL wire_nlO0li00O_dataout : STD_LOGIC; + SIGNAL wire_nlO0li01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0li01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0li01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0li0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0li10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0li10l_dataout : STD_LOGIC; + SIGNAL wire_nlO0li10O_dataout : STD_LOGIC; + SIGNAL wire_nlO0li11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0li11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0li11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0li1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0liii_dataout : STD_LOGIC; + SIGNAL wire_nlO0liil_dataout : STD_LOGIC; + SIGNAL wire_nlO0liiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lili_dataout : STD_LOGIC; + SIGNAL wire_nlO0lill_dataout : STD_LOGIC; + SIGNAL wire_nlO0lilll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lillO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lilOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lilOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lilOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0liO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0liO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0liO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0liO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0liO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0liO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0liOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll00l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll00O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll10l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll10O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0ll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lli1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lliii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lliil_dataout : STD_LOGIC; + SIGNAL wire_nlO0lliiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0llili_dataout : STD_LOGIC; + SIGNAL wire_nlO0llill_dataout : STD_LOGIC; + SIGNAL wire_nlO0llilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lliOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lliOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lliOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lll0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lll0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lll0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lll1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lll1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lllii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lllil_dataout : STD_LOGIC; + SIGNAL wire_nlO0llliO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lllli_dataout : STD_LOGIC; + SIGNAL wire_nlO0lllll_dataout : STD_LOGIC; + SIGNAL wire_nlO0llllO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lllOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lllOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0llO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0llOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0lO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOiii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOiil_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOili_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOill_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOlii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOlil_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOliO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOlli_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOlll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOllO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0lOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O000l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O000O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O000O_w_lg_dataout28852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O001i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O001l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O001O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0O00OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O010i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O011i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O011O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01li_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0O01OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0iii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0iil_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0ili_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0ill_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lil_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0liO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lli_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0llO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lOi_w_lg_dataout29753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lOl_w_lg_dataout29751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0lOO_w_lg_dataout29749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O0i_w_lg_dataout29741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O0l_w_lg_dataout29739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O0O_w_lg_dataout29737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O1i_w_lg_dataout29747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O1l_w_lg_dataout29745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0O1O_w_lg_dataout29743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0Oii_w_lg_dataout29736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0OOi_w_lg_dataout29186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0OOi_w_lg_w_lg_dataout29186w29291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0O0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0O0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O100i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O100l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O100O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O101i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O101l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O101O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10il_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10li_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0O10OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O110i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O110l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O110O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O111i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O111l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O111O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11il_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11li_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0O11OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1iii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1iil_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1ili_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1ill_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lil_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1liO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lli_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1llO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi00l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi00O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi10l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi10O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1lO_w_lg_dataout29185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oii1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oiiii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oiiil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oiili_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oiill_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oil1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oilii_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oilil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiliO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oill_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oill_w_lg_w_lg_dataout4340w4341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oill_w_lg_w_lg_dataout4340w4343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oill_w_lg_dataout4340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0Oilli_dataout : STD_LOGIC; + SIGNAL wire_nlO0Oilll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OillO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OilOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OilOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OilOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0Olll_dataout : STD_LOGIC; + SIGNAL wire_nlO0Olll_w_lg_dataout59543w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlO0OllO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO00i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO00l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO00O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO01O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0il_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0li_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO11l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO0OO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOiii_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOiil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOili_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOill_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOilO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOlii_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOlil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOliO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOlli_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOlll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOllO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOii_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOil_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOli_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOll_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO0OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1000i_dataout : STD_LOGIC; + SIGNAL wire_nlO1000l_dataout : STD_LOGIC; + SIGNAL wire_nlO1000O_dataout : STD_LOGIC; + SIGNAL wire_nlO1001i_dataout : STD_LOGIC; + SIGNAL wire_nlO1001l_dataout : STD_LOGIC; + SIGNAL wire_nlO1001O_dataout : STD_LOGIC; + SIGNAL wire_nlO100ii_dataout : STD_LOGIC; + SIGNAL wire_nlO100il_dataout : STD_LOGIC; + SIGNAL wire_nlO100iO_dataout : STD_LOGIC; + SIGNAL wire_nlO100li_dataout : STD_LOGIC; + SIGNAL wire_nlO100ll_dataout : STD_LOGIC; + SIGNAL wire_nlO100lO_dataout : STD_LOGIC; + SIGNAL wire_nlO100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO100Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO100OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1010i_dataout : STD_LOGIC; + SIGNAL wire_nlO1010l_dataout : STD_LOGIC; + SIGNAL wire_nlO1010O_dataout : STD_LOGIC; + SIGNAL wire_nlO1011i_dataout : STD_LOGIC; + SIGNAL wire_nlO1011l_dataout : STD_LOGIC; + SIGNAL wire_nlO1011O_dataout : STD_LOGIC; + SIGNAL wire_nlO101ii_dataout : STD_LOGIC; + SIGNAL wire_nlO101il_dataout : STD_LOGIC; + SIGNAL wire_nlO101iO_dataout : STD_LOGIC; + SIGNAL wire_nlO101li_dataout : STD_LOGIC; + SIGNAL wire_nlO101ll_dataout : STD_LOGIC; + SIGNAL wire_nlO101lO_dataout : STD_LOGIC; + SIGNAL wire_nlO101Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO101Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO101OO_dataout : STD_LOGIC; + SIGNAL wire_nlO10i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO10i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO10i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO10i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO10i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO10i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO10iii_dataout : STD_LOGIC; + SIGNAL wire_nlO10iil_dataout : STD_LOGIC; + SIGNAL wire_nlO10iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO10ili_dataout : STD_LOGIC; + SIGNAL wire_nlO10ill_dataout : STD_LOGIC; + SIGNAL wire_nlO10ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO10iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO10iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO10iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO10l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO10l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO10l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO10l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO10l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO10l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO10lii_dataout : STD_LOGIC; + SIGNAL wire_nlO10lil_dataout : STD_LOGIC; + SIGNAL wire_nlO10liO_dataout : STD_LOGIC; + SIGNAL wire_nlO10lli_dataout : STD_LOGIC; + SIGNAL wire_nlO10lll_dataout : STD_LOGIC; + SIGNAL wire_nlO10llO_dataout : STD_LOGIC; + SIGNAL wire_nlO10lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO10lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO10lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO10O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO10O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO10O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO10O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO10O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO10Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO10Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO10OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO10Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO10Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO10OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO10OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO10OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO10OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1100i_dataout : STD_LOGIC; + SIGNAL wire_nlO1100l_dataout : STD_LOGIC; + SIGNAL wire_nlO1100O_dataout : STD_LOGIC; + SIGNAL wire_nlO1101i_dataout : STD_LOGIC; + SIGNAL wire_nlO1101l_dataout : STD_LOGIC; + SIGNAL wire_nlO1101O_dataout : STD_LOGIC; + SIGNAL wire_nlO110ii_dataout : STD_LOGIC; + SIGNAL wire_nlO110il_dataout : STD_LOGIC; + SIGNAL wire_nlO110iO_dataout : STD_LOGIC; + SIGNAL wire_nlO110li_dataout : STD_LOGIC; + SIGNAL wire_nlO110ll_dataout : STD_LOGIC; + SIGNAL wire_nlO110lO_dataout : STD_LOGIC; + SIGNAL wire_nlO110Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO110Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO110OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1110i_dataout : STD_LOGIC; + SIGNAL wire_nlO1110l_dataout : STD_LOGIC; + SIGNAL wire_nlO1110O_dataout : STD_LOGIC; + SIGNAL wire_nlO1111i_dataout : STD_LOGIC; + SIGNAL wire_nlO1111l_dataout : STD_LOGIC; + SIGNAL wire_nlO1111O_dataout : STD_LOGIC; + SIGNAL wire_nlO111ii_dataout : STD_LOGIC; + SIGNAL wire_nlO111il_dataout : STD_LOGIC; + SIGNAL wire_nlO111iO_dataout : STD_LOGIC; + SIGNAL wire_nlO111li_dataout : STD_LOGIC; + SIGNAL wire_nlO111ll_dataout : STD_LOGIC; + SIGNAL wire_nlO111lO_dataout : STD_LOGIC; + SIGNAL wire_nlO111Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO111Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO111OO_dataout : STD_LOGIC; + SIGNAL wire_nlO11i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO11i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO11i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO11i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO11i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO11i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO11iii_dataout : STD_LOGIC; + SIGNAL wire_nlO11iil_dataout : STD_LOGIC; + SIGNAL wire_nlO11iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO11ili_dataout : STD_LOGIC; + SIGNAL wire_nlO11ill_dataout : STD_LOGIC; + SIGNAL wire_nlO11ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO11iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO11iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO11iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO11l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO11l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO11l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO11l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO11l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO11l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO11lii_dataout : STD_LOGIC; + SIGNAL wire_nlO11lil_dataout : STD_LOGIC; + SIGNAL wire_nlO11liO_dataout : STD_LOGIC; + SIGNAL wire_nlO11lli_dataout : STD_LOGIC; + SIGNAL wire_nlO11lll_dataout : STD_LOGIC; + SIGNAL wire_nlO11llO_dataout : STD_LOGIC; + SIGNAL wire_nlO11lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO11lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO11lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO11O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO11O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO11O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO11O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO11O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO11O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO11Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO11Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO11OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO11Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO11Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO11OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO11OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO11OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO11OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i00i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i00l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i00O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i01i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i01l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i01O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0il_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0li_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i10i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i10l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i10O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i11i_dataout : STD_LOGIC; + SIGNAL wire_nlO1i11l_dataout : STD_LOGIC; + SIGNAL wire_nlO1i11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiii_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiil_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1iili_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1il0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1il0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1il0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1il1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1il1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1il1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1ilii_dataout : STD_LOGIC; + SIGNAL wire_nlO1ilil_dataout : STD_LOGIC; + SIGNAL wire_nlO1iliO_dataout : STD_LOGIC; + SIGNAL wire_nlO1illi_dataout : STD_LOGIC; + SIGNAL wire_nlO1illl_dataout : STD_LOGIC; + SIGNAL wire_nlO1illO_dataout : STD_LOGIC; + SIGNAL wire_nlO1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOii_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOil_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOli_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOll_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l00i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l00l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l00O_dataout : STD_LOGIC; + SIGNAL wire_nlO1l01i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l01l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l01O_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0il_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0li_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l10i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l10l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l10O_dataout : STD_LOGIC; + SIGNAL wire_nlO1l11i_dataout : STD_LOGIC; + SIGNAL wire_nlO1l11l_dataout : STD_LOGIC; + SIGNAL wire_nlO1l11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1li0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1li0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1li0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1li1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1li1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1li1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1liii_dataout : STD_LOGIC; + SIGNAL wire_nlO1liil_dataout : STD_LOGIC; + SIGNAL wire_nlO1liiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lili_dataout : STD_LOGIC; + SIGNAL wire_nlO1lill_dataout : STD_LOGIC; + SIGNAL wire_nlO1lilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1liOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1liOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1liOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1llii_dataout : STD_LOGIC; + SIGNAL wire_nlO1llil_dataout : STD_LOGIC; + SIGNAL wire_nlO1lliO_dataout : STD_LOGIC; + SIGNAL wire_nlO1llli_dataout : STD_LOGIC; + SIGNAL wire_nlO1llll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lllO_dataout : STD_LOGIC; + SIGNAL wire_nlO1llOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1llOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1llOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOii_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOil_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOli_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOii_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOil_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOli_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOll_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1lOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O000i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O000l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O000O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O001i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O001l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O001O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00il_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00li_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1O00OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O010i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O010l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O010O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O011i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O011l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O011O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01il_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01li_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1O01OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0iii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0iil_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0il_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0ili_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0ill_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0li_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O100i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O100l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O100O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O101i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O101l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O101O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10il_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10li_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1O10OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O110i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O110l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O110O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O111i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O111l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O111O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11il_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11li_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1O11OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1iii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1iil_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1ili_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1ill_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lil_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1liO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lli_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1llO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1O1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oili_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oill_dataout : STD_LOGIC; + SIGNAL wire_nlO1OilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol00i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol00l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol00O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol01i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol01l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol01O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0il_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0li_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ol1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oli0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oli0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oli0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oli1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oli1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oli1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Olii_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oliii_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oliil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OliiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Olil_dataout : STD_LOGIC; + SIGNAL wire_nlO1Olili_dataout : STD_LOGIC; + SIGNAL wire_nlO1Olill_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OliO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OliOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OliOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OliOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1Oll1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1Olli_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ollii_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ollil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlliO_dataout : STD_LOGIC; + SIGNAL wire_nlO1Olll_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ollli_dataout : STD_LOGIC; + SIGNAL wire_nlO1Ollll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlllO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OllO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OllOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OllOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OllOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOii_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOli_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO00i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO00l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO00O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO01i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO01l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO01O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0il_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0li_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO10i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO10l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO10O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO11i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO11l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO11O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1il_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1li_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlO1OO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOii_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOiii_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOiil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOili_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOill_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOilO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOli_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlii_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOliO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlli_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOllO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOii_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOil_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOli_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOll_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlO1OOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0000l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0001O_dataout : STD_LOGIC; + SIGNAL wire_nlOi000ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi000ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi000Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi000OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0010i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0010O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0011l_dataout : STD_LOGIC; + SIGNAL wire_nlOi001iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi001li_dataout : STD_LOGIC; + SIGNAL wire_nlOi001lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi001Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi001Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi00i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi00i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi00i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi00iii_dataout : STD_LOGIC; + SIGNAL wire_nlOi00iil_dataout : STD_LOGIC; + SIGNAL wire_nlOi00ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOi00iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi00l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi00l1O_w_lg_w_lg_dataout21012w21013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi00l1O_w_lg_dataout21012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi00lii_dataout : STD_LOGIC; + SIGNAL wire_nlOi00lll_dataout : STD_LOGIC; + SIGNAL wire_nlOi00O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi00O0i_w_lg_dataout9865w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi00O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi00O1O_w_lg_dataout9870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi00Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOi00Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOi00OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi00Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOi00OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi0100i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0100l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0100O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0101i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0101l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0101O_dataout : STD_LOGIC; + SIGNAL wire_nlOi010li_dataout : STD_LOGIC; + SIGNAL wire_nlOi010li_w_lg_dataout29711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi010ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi010ll_w_lg_dataout29709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi010lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi010lO_w_lg_dataout29707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi010Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi010Oi_w_lg_dataout29705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi010Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi010Ol_w_lg_dataout29703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi010OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi010OO_w_lg_dataout29701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0110i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0110l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0110O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0111i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0111l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0111O_dataout : STD_LOGIC; + SIGNAL wire_nlOi011ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi011il_dataout : STD_LOGIC; + SIGNAL wire_nlOi011iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi011li_dataout : STD_LOGIC; + SIGNAL wire_nlOi011ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi011lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi011Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi011Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi011OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i1i_w_lg_dataout29699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi01i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi01i1l_w_lg_dataout29698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi01i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi01iii_dataout : STD_LOGIC; + SIGNAL wire_nlOi01iil_dataout : STD_LOGIC; + SIGNAL wire_nlOi01iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi01ili_dataout : STD_LOGIC; + SIGNAL wire_nlOi01ill_dataout : STD_LOGIC; + SIGNAL wire_nlOi01ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOi01iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi01lii_dataout : STD_LOGIC; + SIGNAL wire_nlOi01lil_dataout : STD_LOGIC; + SIGNAL wire_nlOi01liO_dataout : STD_LOGIC; + SIGNAL wire_nlOi01lli_dataout : STD_LOGIC; + SIGNAL wire_nlOi01lll_dataout : STD_LOGIC; + SIGNAL wire_nlOi01llO_dataout : STD_LOGIC; + SIGNAL wire_nlOi01lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi01lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi01lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O0i_w_lg_dataout29166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi01O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi01O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi01Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOi01Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOi01OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i01i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i01O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i01O_w_lg_dataout46530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0i10O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i11i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i11O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i1li_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ii0O_w_lg_dataout9020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iiii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iiil_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iiil_w_lg_dataout9017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iiiO_w_lg_w_lg_w_lg_w_lg_dataout9016w9018w9019w9021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iiiO_w_lg_w_lg_w_lg_dataout9016w9018w9019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iiiO_w_lg_w_lg_dataout9016w9018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iiiO_w_lg_dataout9016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iili_w_lg_w_lg_w_lg_dataout20928w20937w20938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_w_lg_w_lg_w_lg_dataout20928w20939w20940w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_w_lg_w_lg_dataout20928w20937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_w_lg_w_lg_dataout20928w20939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_w_lg_dataout20928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_w20941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_w_lg_w20941w20942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iili_w_lg_w_lg_w20941w20942w20943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0iill_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iilO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0il1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0il1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOil_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOli_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l00i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l01i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l10i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l10l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l10O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l11i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l11l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l11O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l1il_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi0li0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0li0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0li0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0liii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0liil_dataout : STD_LOGIC; + SIGNAL wire_nlOi0liiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lili_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lill_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lilO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0liOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0liOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi0liOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0llii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0llil_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lliO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0llli_dataout : STD_LOGIC; + SIGNAL wire_nlOi0llll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lllO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0llOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0llOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi0llOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lO0i_w_lg_dataout28858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lOil_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lOli_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lOll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O00i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O01l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O10i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O11l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O1il_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O1li_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Oill_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Olii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Olli_dataout : STD_LOGIC; + SIGNAL wire_nlOi0Olll_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OO0l_w_lg_dataout20783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OOii_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OOil_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOi0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi1110i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1110l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1110O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1111i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1111l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1111O_dataout : STD_LOGIC; + SIGNAL wire_nlOi111ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi111il_dataout : STD_LOGIC; + SIGNAL wire_nlOi111iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi111li_dataout : STD_LOGIC; + SIGNAL wire_nlOi111ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi111lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi111Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l00i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l00l_w_lg_dataout29032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1l00O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l01i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l01i_w_lg_dataout29031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1l01l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l01O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0il_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0li_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0li_w_lg_dataout29029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0lO_w_lg_dataout29030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li0i_w_lg_dataout29028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1li0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li1i_w_lg_dataout29026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1li1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1li1O_w_lg_dataout29027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1liii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1liil_dataout : STD_LOGIC; + SIGNAL wire_nlOi1liiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lili_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lill_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lill_w_lg_dataout29025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1lilO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1liOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1liOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi1liOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1llii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1llil_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lliO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1llli_dataout : STD_LOGIC; + SIGNAL wire_nlOi1llll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lllO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1llOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1llOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi1llOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOil_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOli_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O00i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O00l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O00O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O01i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O01l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O01O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O10i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O10l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O10O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O11i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O11l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O11O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1il_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1li_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOi1O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oi0i_w_lg_dataout28866w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oi0l_w_lg_dataout28864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oiii_w_lg_dataout28862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Oiil_w_lg_dataout28860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOi1Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Olii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Olil_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OliO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Olli_dataout : STD_LOGIC; + SIGNAL wire_nlOi1Olll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OllO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOii_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOil_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOli_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOll_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOi1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOii000i_dataout : STD_LOGIC; + SIGNAL wire_nlOii000l_dataout : STD_LOGIC; + SIGNAL wire_nlOii000O_dataout : STD_LOGIC; + SIGNAL wire_nlOii001i_dataout : STD_LOGIC; + SIGNAL wire_nlOii001l_dataout : STD_LOGIC; + SIGNAL wire_nlOii00li_dataout : STD_LOGIC; + SIGNAL wire_nlOii00lO_dataout : STD_LOGIC; + SIGNAL wire_nlOii00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOii010l_dataout : STD_LOGIC; + SIGNAL wire_nlOii011i_dataout : STD_LOGIC; + SIGNAL wire_nlOii011O_dataout : STD_LOGIC; + SIGNAL wire_nlOii01iO_dataout : STD_LOGIC; + SIGNAL wire_nlOii01ll_dataout : STD_LOGIC; + SIGNAL wire_nlOii01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOii0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOii0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOii0iii_dataout : STD_LOGIC; + SIGNAL wire_nlOii0ili_dataout : STD_LOGIC; + SIGNAL wire_nlOii0ill_dataout : STD_LOGIC; + SIGNAL wire_nlOii0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOii0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOii0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOii0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOii0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOii0l0O_w_lg_w_lg_dataout21190w24751w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0l0O_w_lg_dataout21190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0l0O_w_lg_dataout23875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOii0lli_w_lg_dataout25161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOii0lOl_w_lg_dataout24922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0lOl_w_lg_dataout23877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOii0O1O_w_lg_dataout9833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOii0Oii_w26816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_w_lg_w_lg_w26809w26811w26813w26815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_w_lg_w26809w26811w26813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_w26809w26811w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w26809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_w_lg_w_lg_dataout21042w26805w26807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_w_lg_dataout21042w26805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_w_lg_w_lg_dataout21042w21043w21044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_dataout21042w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oii_w_lg_w_lg_dataout21042w21043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOii0Oll_w_lg_dataout42177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOii0OOO_w_lg_dataout34636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii101O_dataout : STD_LOGIC; + SIGNAL wire_nlOii101O_w_lg_w_lg_dataout20780w20781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii101O_w_lg_dataout20779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii101O_w_lg_dataout20780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii10ii_dataout : STD_LOGIC; + SIGNAL wire_nlOii10ii_w_lg_w_lg_dataout23869w23871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii10ii_w_lg_dataout23869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii10ii_w_lg_dataout23472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOii10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOii10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOii110i_dataout : STD_LOGIC; + SIGNAL wire_nlOii110l_dataout : STD_LOGIC; + SIGNAL wire_nlOii111i_dataout : STD_LOGIC; + SIGNAL wire_nlOii11ii_dataout : STD_LOGIC; + SIGNAL wire_nlOii11il_dataout : STD_LOGIC; + SIGNAL wire_nlOii11iO_dataout : STD_LOGIC; + SIGNAL wire_nlOii11lO_dataout : STD_LOGIC; + SIGNAL wire_nlOii11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOii1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOii1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOii1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOii1ili_dataout : STD_LOGIC; + SIGNAL wire_nlOii1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOii1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOii1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOii1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOii1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOii1lii_dataout : STD_LOGIC; + SIGNAL wire_nlOii1liO_dataout : STD_LOGIC; + SIGNAL wire_nlOii1lll_dataout : STD_LOGIC; + SIGNAL wire_nlOii1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOii1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOii1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOii1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOii1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOii1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOii1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOii1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiii00l_dataout : STD_LOGIC; + SIGNAL wire_nlOiii01O_dataout : STD_LOGIC; + SIGNAL wire_nlOiii0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiii0li_dataout : STD_LOGIC; + SIGNAL wire_nlOiii0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiii0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiii10i_dataout : STD_LOGIC; + SIGNAL wire_nlOiii10i_w_lg_dataout42170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiii1il_dataout : STD_LOGIC; + SIGNAL wire_nlOiii1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiiii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiillO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiiilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiil00i_dataout : STD_LOGIC; + SIGNAL wire_nlOiil00O_dataout : STD_LOGIC; + SIGNAL wire_nlOiil01l_dataout : STD_LOGIC; + SIGNAL wire_nlOiil0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiil0li_dataout : STD_LOGIC; + SIGNAL wire_nlOiil10i_dataout : STD_LOGIC; + SIGNAL wire_nlOiil10l_dataout : STD_LOGIC; + SIGNAL wire_nlOiil10O_dataout : STD_LOGIC; + SIGNAL wire_nlOiil11i_dataout : STD_LOGIC; + SIGNAL wire_nlOiil11l_dataout : STD_LOGIC; + SIGNAL wire_nlOiil11O_dataout : STD_LOGIC; + SIGNAL wire_nlOiil1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiil1il_dataout : STD_LOGIC; + SIGNAL wire_nlOiil1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiil1li_dataout : STD_LOGIC; + SIGNAL wire_nlOiil1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiil1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiili0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiili0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiili0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiliii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiliil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiilili_dataout : STD_LOGIC; + SIGNAL wire_nlOiilill_dataout : STD_LOGIC; + SIGNAL wire_nlOiililO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiiliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiill0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiill0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiill0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiill1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiill1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiill1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiillii_dataout : STD_LOGIC; + SIGNAL wire_nlOiillOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiillOl_w_lg_dataout9855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiillOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiillOO_w_lg_dataout9853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiilO1i_w_lg_dataout9851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiilO1l_w_lg_w_lg_w_lg_w_lg_dataout9857w9858w9868w9869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1l_w_lg_w_lg_dataout9857w9858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1l_w_lg_w_lg_dataout9857w9862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1l_w_lg_dataout9852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilO1l_w_lg_dataout9857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiilOii_dataout : STD_LOGIC; + SIGNAL wire_nlOiilOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiilOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiilOli_dataout : STD_LOGIC; + SIGNAL wire_nlOiilOll_dataout : STD_LOGIC; + SIGNAL wire_nlOiilOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiilOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiilOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOiiO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOil000i_dataout : STD_LOGIC; + SIGNAL wire_nlOil000l_dataout : STD_LOGIC; + SIGNAL wire_nlOil000O_dataout : STD_LOGIC; + SIGNAL wire_nlOil001l_dataout : STD_LOGIC; + SIGNAL wire_nlOil001O_dataout : STD_LOGIC; + SIGNAL wire_nlOil00ii_dataout : STD_LOGIC; + SIGNAL wire_nlOil00il_dataout : STD_LOGIC; + SIGNAL wire_nlOil00iO_dataout : STD_LOGIC; + SIGNAL wire_nlOil00li_dataout : STD_LOGIC; + SIGNAL wire_nlOil00ll_dataout : STD_LOGIC; + SIGNAL wire_nlOil00lO_dataout : STD_LOGIC; + SIGNAL wire_nlOil00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOil00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOil00OO_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOil0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOil0iii_dataout : STD_LOGIC; + SIGNAL wire_nlOil0iil_dataout : STD_LOGIC; + SIGNAL wire_nlOil0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOil0ili_dataout : STD_LOGIC; + SIGNAL wire_nlOil0ill_dataout : STD_LOGIC; + SIGNAL wire_nlOil0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOil0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOil0lii_dataout : STD_LOGIC; + SIGNAL wire_nlOil0lil_dataout : STD_LOGIC; + SIGNAL wire_nlOil0liO_dataout : STD_LOGIC; + SIGNAL wire_nlOil0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOil0lll_dataout : STD_LOGIC; + SIGNAL wire_nlOil0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOil0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOil0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOil0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOil0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOil100i_dataout : STD_LOGIC; + SIGNAL wire_nlOil100l_dataout : STD_LOGIC; + SIGNAL wire_nlOil100O_dataout : STD_LOGIC; + SIGNAL wire_nlOil10ii_dataout : STD_LOGIC; + SIGNAL wire_nlOil110i_dataout : STD_LOGIC; + SIGNAL wire_nlOil110l_dataout : STD_LOGIC; + SIGNAL wire_nlOil110O_dataout : STD_LOGIC; + SIGNAL wire_nlOil111i_dataout : STD_LOGIC; + SIGNAL wire_nlOil111l_dataout : STD_LOGIC; + SIGNAL wire_nlOil11ii_dataout : STD_LOGIC; + SIGNAL wire_nlOil11il_dataout : STD_LOGIC; + SIGNAL wire_nlOil1iii_dataout : STD_LOGIC; + SIGNAL wire_nlOil1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOil1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOil1ili_dataout : STD_LOGIC; + SIGNAL wire_nlOil1ill_dataout : STD_LOGIC; + SIGNAL wire_nlOil1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOil1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOil1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOil1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOil1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOil1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOil1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOili00i_dataout : STD_LOGIC; + SIGNAL wire_nlOili01l_dataout : STD_LOGIC; + SIGNAL wire_nlOili01O_dataout : STD_LOGIC; + SIGNAL wire_nlOili0il_dataout : STD_LOGIC; + SIGNAL wire_nlOili11i_dataout : STD_LOGIC; + SIGNAL wire_nlOili11O_dataout : STD_LOGIC; + SIGNAL wire_nlOili1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOili1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOili1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOili1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOili1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOilii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOilii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOilii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOilii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiliil_dataout : STD_LOGIC; + SIGNAL wire_nlOiliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOilil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOilili_dataout : STD_LOGIC; + SIGNAL wire_nlOililii_dataout : STD_LOGIC; + SIGNAL wire_nlOililil_dataout : STD_LOGIC; + SIGNAL wire_nlOililiO_dataout : STD_LOGIC; + SIGNAL wire_nlOilill_dataout : STD_LOGIC; + SIGNAL wire_nlOililli_dataout : STD_LOGIC; + SIGNAL wire_nlOililll_dataout : STD_LOGIC; + SIGNAL wire_nlOilillO_dataout : STD_LOGIC; + SIGNAL wire_nlOililO_dataout : STD_LOGIC; + SIGNAL wire_nlOililOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOill0i_dataout : STD_LOGIC; + SIGNAL wire_nlOill0l_dataout : STD_LOGIC; + SIGNAL wire_nlOill0O_dataout : STD_LOGIC; + SIGNAL wire_nlOill10i_dataout : STD_LOGIC; + SIGNAL wire_nlOill10l_dataout : STD_LOGIC; + SIGNAL wire_nlOill10O_dataout : STD_LOGIC; + SIGNAL wire_nlOill11O_dataout : STD_LOGIC; + SIGNAL wire_nlOill1i_dataout : STD_LOGIC; + SIGNAL wire_nlOill1l_dataout : STD_LOGIC; + SIGNAL wire_nlOill1O_dataout : STD_LOGIC; + SIGNAL wire_nlOilli0i_dataout : STD_LOGIC; + SIGNAL wire_nlOilli0l_dataout : STD_LOGIC; + SIGNAL wire_nlOilli0O_dataout : STD_LOGIC; + SIGNAL wire_nlOilli1i_dataout : STD_LOGIC; + SIGNAL wire_nlOilli1l_dataout : STD_LOGIC; + SIGNAL wire_nlOilli1O_dataout : STD_LOGIC; + SIGNAL wire_nlOillii_dataout : STD_LOGIC; + SIGNAL wire_nlOilliii_dataout : STD_LOGIC; + SIGNAL wire_nlOilliil_dataout : STD_LOGIC; + SIGNAL wire_nlOilliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOillil_dataout : STD_LOGIC; + SIGNAL wire_nlOillili_dataout : STD_LOGIC; + SIGNAL wire_nlOillill_dataout : STD_LOGIC; + SIGNAL wire_nlOillilO_dataout : STD_LOGIC; + SIGNAL wire_nlOilliO_dataout : STD_LOGIC; + SIGNAL wire_nlOilliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOilliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOilliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOilll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOilll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOilll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOilll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOilll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOilll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOillli_dataout : STD_LOGIC; + SIGNAL wire_nlOilllii_dataout : STD_LOGIC; + SIGNAL wire_nlOilllil_dataout : STD_LOGIC; + SIGNAL wire_nlOillliO_dataout : STD_LOGIC; + SIGNAL wire_nlOillll_dataout : STD_LOGIC; + SIGNAL wire_nlOilllli_dataout : STD_LOGIC; + SIGNAL wire_nlOilllO_dataout : STD_LOGIC; + SIGNAL wire_nlOillO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOillO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOillO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOillOi_dataout : STD_LOGIC; + SIGNAL wire_nlOillOii_dataout : STD_LOGIC; + SIGNAL wire_nlOillOil_dataout : STD_LOGIC; + SIGNAL wire_nlOillOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOillOl_dataout : STD_LOGIC; + SIGNAL wire_nlOillOli_dataout : STD_LOGIC; + SIGNAL wire_nlOillOll_dataout : STD_LOGIC; + SIGNAL wire_nlOillOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOillOO_dataout : STD_LOGIC; + SIGNAL wire_nlOillOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOillOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOillOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOilO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOilO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOilO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOilO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOilO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOilO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOilO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOilO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOilO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOilO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOilO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOilO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOilO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOilOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOilOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOilOii_dataout : STD_LOGIC; + SIGNAL wire_nlOilOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOilOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOil_dataout : STD_LOGIC; + SIGNAL wire_nlOilOill_dataout : STD_LOGIC; + SIGNAL wire_nlOilOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOilOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOilOli_dataout : STD_LOGIC; + SIGNAL wire_nlOilOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOilOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOilOll_dataout : STD_LOGIC; + SIGNAL wire_nlOilOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOilOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOilOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOilOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOilOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOilOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOilOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOilOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOilOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOilOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO000i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO000i_w_lg_w_lg_w36605w36606w36610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO000i_w_lg_w36605w36606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO000i_w36605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO000i_w_lg_w_lg_w_lg_dataout36602w36603w36604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO000i_w_lg_w_lg_dataout36602w36603w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO000i_w_lg_dataout36602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO000l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO000O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO001i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO001l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO001O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00il_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00li_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiO00OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO010i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO010l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO010O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO011l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO011O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01il_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01li_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01lO_w_lg_dataout36611w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01Oi_w_lg_dataout36607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiO01OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0i0O_w_lg_dataout36600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iii_w_lg_dataout36598w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iil_w_lg_dataout36587w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0ili_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0ill_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0ill_w_lg_dataout36593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iOi_w_lg_w_lg_w36595w36596w36597w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w_lg_w36595w36596w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w36586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w36595w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w_lg_w_lg_w_lg_dataout36583w36584w36585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w_lg_w_lg_w_lg_dataout36591w36592w36594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w_lg_w_lg_dataout36583w36584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w_lg_w_lg_dataout36591w36592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w_lg_dataout36583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOi_w_lg_dataout36591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iOl_w_lg_dataout36581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0iOO_w_lg_dataout36577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0l0O_w_lg_w_lg_w36575w36576w36580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0l0O_w_lg_w36575w36576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0l0O_w36575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0l0O_w_lg_w_lg_w_lg_dataout36572w36573w36574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0l0O_w_lg_w_lg_dataout36572w36573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0l0O_w_lg_dataout36572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0liO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0Oil_w_lg_dataout36570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0OiO_w_lg_dataout36568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0Oli_w_lg_dataout36557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0OOi_w_lg_dataout36563w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO0OOO_w_lg_w_lg_w36565w36566w36567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w_lg_w36565w36566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w36556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w36565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w_lg_w_lg_w_lg_dataout36553w36554w36555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w_lg_w_lg_w_lg_dataout36561w36562w36564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w_lg_w_lg_dataout36553w36554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w_lg_w_lg_dataout36561w36562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w_lg_dataout36553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO0OOO_w_lg_dataout36561w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiO10i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO10O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO110i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO110l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO110O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO111i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO111l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO11li_dataout : STD_LOGIC; + SIGNAL wire_nlOiO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1ili_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1ill_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1lii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1lil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1liO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1lli_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1lll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1llO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi00i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi00l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi00O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi01i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi01l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi01O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0il_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi10i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi11i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi11i_w_lg_dataout36238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1ll_w_lg_w_lg_dataout18936w18937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiOi1ll_w_lg_dataout18936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiili_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiill_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOil0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOil0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOil1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOili_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiliO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOill_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilli_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOillO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOli_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl10i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl10l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl10O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl11i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl11l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl11O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1il_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1li_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1ll_w_lg_dataout18919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOl1lO_w_lg_dataout18765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOiOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOiOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOili_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOill_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOiOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl000i_dataout : STD_LOGIC; + SIGNAL wire_nlOl000l_dataout : STD_LOGIC; + SIGNAL wire_nlOl000O_dataout : STD_LOGIC; + SIGNAL wire_nlOl001i_dataout : STD_LOGIC; + SIGNAL wire_nlOl001l_dataout : STD_LOGIC; + SIGNAL wire_nlOl001O_dataout : STD_LOGIC; + SIGNAL wire_nlOl00ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl00il_dataout : STD_LOGIC; + SIGNAL wire_nlOl00iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl00li_dataout : STD_LOGIC; + SIGNAL wire_nlOl00ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl00lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl00OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl010i_dataout : STD_LOGIC; + SIGNAL wire_nlOl010l_dataout : STD_LOGIC; + SIGNAL wire_nlOl010O_dataout : STD_LOGIC; + SIGNAL wire_nlOl011i_dataout : STD_LOGIC; + SIGNAL wire_nlOl011l_dataout : STD_LOGIC; + SIGNAL wire_nlOl011O_dataout : STD_LOGIC; + SIGNAL wire_nlOl01ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl01il_dataout : STD_LOGIC; + SIGNAL wire_nlOl01iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl01li_dataout : STD_LOGIC; + SIGNAL wire_nlOl01ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl01lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl01OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl0iii_dataout : STD_LOGIC; + SIGNAL wire_nlOl0iil_dataout : STD_LOGIC; + SIGNAL wire_nlOl0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0ili_dataout : STD_LOGIC; + SIGNAL wire_nlOl0ill_dataout : STD_LOGIC; + SIGNAL wire_nlOl0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lii_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lil_dataout : STD_LOGIC; + SIGNAL wire_nlOl0liO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lll_dataout : STD_LOGIC; + SIGNAL wire_nlOl0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOl0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOl0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOl0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOl0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOl0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1000i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1000l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1000O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1001i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1001l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1001O_dataout : STD_LOGIC; + SIGNAL wire_nlOl100i_dataout : STD_LOGIC; + SIGNAL wire_nlOl100ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl100il_dataout : STD_LOGIC; + SIGNAL wire_nlOl100iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl100l_dataout : STD_LOGIC; + SIGNAL wire_nlOl100li_dataout : STD_LOGIC; + SIGNAL wire_nlOl100ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl100lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl100O_dataout : STD_LOGIC; + SIGNAL wire_nlOl100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl100Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl100OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1010i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1010l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1010O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1011i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1011l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1011O_dataout : STD_LOGIC; + SIGNAL wire_nlOl101i_dataout : STD_LOGIC; + SIGNAL wire_nlOl101ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl101il_dataout : STD_LOGIC; + SIGNAL wire_nlOl101iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl101l_dataout : STD_LOGIC; + SIGNAL wire_nlOl101li_dataout : STD_LOGIC; + SIGNAL wire_nlOl101ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl101lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl101O_dataout : STD_LOGIC; + SIGNAL wire_nlOl101Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl101Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl101OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl10i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl10i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl10i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl10i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl10i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl10ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl10iii_dataout : STD_LOGIC; + SIGNAL wire_nlOl10iil_dataout : STD_LOGIC; + SIGNAL wire_nlOl10iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10il_dataout : STD_LOGIC; + SIGNAL wire_nlOl10ili_dataout : STD_LOGIC; + SIGNAL wire_nlOl10ill_dataout : STD_LOGIC; + SIGNAL wire_nlOl10ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl10iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl10iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl10l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl10l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl10l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl10l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl10l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl10li_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lii_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lil_dataout : STD_LOGIC; + SIGNAL wire_nlOl10liO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lli_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lll_dataout : STD_LOGIC; + SIGNAL wire_nlOl10llO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl10lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl10O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl10O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl10O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl10O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl10O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl10Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOl10Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOl10OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl10Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOl10Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOl10OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl10OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl10OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl10OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1100i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1100l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1100O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1101i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1101l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1101O_dataout : STD_LOGIC; + SIGNAL wire_nlOl110i_dataout : STD_LOGIC; + SIGNAL wire_nlOl110ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl110il_dataout : STD_LOGIC; + SIGNAL wire_nlOl110iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl110l_dataout : STD_LOGIC; + SIGNAL wire_nlOl110li_dataout : STD_LOGIC; + SIGNAL wire_nlOl110ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl110lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl110O_dataout : STD_LOGIC; + SIGNAL wire_nlOl110Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl110Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl110OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1110i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1110l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1110O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1111i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1111l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1111O_dataout : STD_LOGIC; + SIGNAL wire_nlOl111i_dataout : STD_LOGIC; + SIGNAL wire_nlOl111ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl111il_dataout : STD_LOGIC; + SIGNAL wire_nlOl111iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl111l_dataout : STD_LOGIC; + SIGNAL wire_nlOl111li_dataout : STD_LOGIC; + SIGNAL wire_nlOl111ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl111lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl111O_dataout : STD_LOGIC; + SIGNAL wire_nlOl111Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl111Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl111OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl11i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl11i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl11i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl11i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl11i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl11ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl11iii_dataout : STD_LOGIC; + SIGNAL wire_nlOl11iil_dataout : STD_LOGIC; + SIGNAL wire_nlOl11iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11il_dataout : STD_LOGIC; + SIGNAL wire_nlOl11ili_dataout : STD_LOGIC; + SIGNAL wire_nlOl11ill_dataout : STD_LOGIC; + SIGNAL wire_nlOl11ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl11iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl11iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl11l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl11li_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lii_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lil_dataout : STD_LOGIC; + SIGNAL wire_nlOl11liO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lli_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lll_dataout : STD_LOGIC; + SIGNAL wire_nlOl11llO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl11lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl11O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl11O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl11O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl11O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl11O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl11Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOl11Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOl11OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl11Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOl11Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOl11OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl11OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl11OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl11OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i00i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i00l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i00O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i01O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0il_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0li_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i10i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i10l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i10O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i11i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i11l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i11O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1il_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1li_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iiii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iiil_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iili_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iill_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iilO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1il0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1il0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1il0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1il1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1il1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1il1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ili_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ilii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ilil_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iliO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ill_dataout : STD_LOGIC; + SIGNAL wire_nlOl1illi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1illl_dataout : STD_LOGIC; + SIGNAL wire_nlOl1illO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOil_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOli_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl1iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l01i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l01l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l01O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l0il_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l0Ol_w_lg_dataout4337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl1l0Ol_w_lg_dataout4348w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l0OO_w_lg_dataout28027w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOl1l10i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l10l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l10O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l11i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l11l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l11O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1il_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1li_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOl1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1li0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1li1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1li1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1liii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1liil_dataout : STD_LOGIC; + SIGNAL wire_nlOl1liiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lil_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lili_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lill_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lilO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1liO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lli_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1llO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOl1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOl1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOl1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOl1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOl1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOl1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOl1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOl1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOl1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOli0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOli10i_dataout : STD_LOGIC; + SIGNAL wire_nlOli10l_dataout : STD_LOGIC; + SIGNAL wire_nlOli10O_dataout : STD_LOGIC; + SIGNAL wire_nlOli11i_dataout : STD_LOGIC; + SIGNAL wire_nlOli11l_dataout : STD_LOGIC; + SIGNAL wire_nlOli11O_dataout : STD_LOGIC; + SIGNAL wire_nlOli1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOliiii_dataout : STD_LOGIC; + SIGNAL wire_nlOliiil_dataout : STD_LOGIC; + SIGNAL wire_nlOliiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOliili_dataout : STD_LOGIC; + SIGNAL wire_nlOliill_dataout : STD_LOGIC; + SIGNAL wire_nlOliilO_dataout : STD_LOGIC; + SIGNAL wire_nlOliiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOliiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOliiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlil00i_dataout : STD_LOGIC; + SIGNAL wire_nlOlil00l_dataout : STD_LOGIC; + SIGNAL wire_nlOlil00O_dataout : STD_LOGIC; + SIGNAL wire_nlOlil01i_dataout : STD_LOGIC; + SIGNAL wire_nlOlil01l_dataout : STD_LOGIC; + SIGNAL wire_nlOlil01O_dataout : STD_LOGIC; + SIGNAL wire_nlOlil0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlil0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlil0il_dataout : STD_LOGIC; + SIGNAL wire_nlOlil0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlil0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1il_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1li_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlil1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlilii_dataout : STD_LOGIC; + SIGNAL wire_nlOlilil_dataout : STD_LOGIC; + SIGNAL wire_nlOliliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlilli_dataout : STD_LOGIC; + SIGNAL wire_nlOlilll_dataout : STD_LOGIC; + SIGNAL wire_nlOlilllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlillO_dataout : STD_LOGIC; + SIGNAL wire_nlOlillOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlillOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlillOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlilO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlilO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlilO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlilO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlilO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOil_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlilOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOliO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOliO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOliO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOliO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOliO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOliO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOliO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOliO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOliO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOliO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOliOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOliOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOliOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOliOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOliOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOliOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOliOii_dataout : STD_LOGIC; + SIGNAL wire_nlOliOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOliOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOliOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOil_dataout : STD_LOGIC; + SIGNAL wire_nlOliOili_dataout : STD_LOGIC; + SIGNAL wire_nlOliOill_dataout : STD_LOGIC; + SIGNAL wire_nlOliOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOliOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOliOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOliOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOliOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOliOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOliOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOliOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOliOli_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOliOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOll_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOliOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOliOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOliOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOliOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOliOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOliOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOliOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOliOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOll00i_dataout : STD_LOGIC; + SIGNAL wire_nlOll00ii_dataout : STD_LOGIC; + SIGNAL wire_nlOll00il_dataout : STD_LOGIC; + SIGNAL wire_nlOll00iO_dataout : STD_LOGIC; + SIGNAL wire_nlOll00l_dataout : STD_LOGIC; + SIGNAL wire_nlOll00li_dataout : STD_LOGIC; + SIGNAL wire_nlOll00ll_dataout : STD_LOGIC; + SIGNAL wire_nlOll00lO_dataout : STD_LOGIC; + SIGNAL wire_nlOll00O_dataout : STD_LOGIC; + SIGNAL wire_nlOll00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOll00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOll00OO_dataout : STD_LOGIC; + SIGNAL wire_nlOll010i_dataout : STD_LOGIC; + SIGNAL wire_nlOll011l_dataout : STD_LOGIC; + SIGNAL wire_nlOll011O_dataout : STD_LOGIC; + SIGNAL wire_nlOll01i_dataout : STD_LOGIC; + SIGNAL wire_nlOll01l_dataout : STD_LOGIC; + SIGNAL wire_nlOll01O_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOll0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOll0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOll0iii_dataout : STD_LOGIC; + SIGNAL wire_nlOll0iil_dataout : STD_LOGIC; + SIGNAL wire_nlOll0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0il_dataout : STD_LOGIC; + SIGNAL wire_nlOll0ili_dataout : STD_LOGIC; + SIGNAL wire_nlOll0ill_dataout : STD_LOGIC; + SIGNAL wire_nlOll0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOll0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOll0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOll0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOll0li_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lii_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lil_dataout : STD_LOGIC; + SIGNAL wire_nlOll0liO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lll_dataout : STD_LOGIC; + SIGNAL wire_nlOll0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOll0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOll0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOll0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOll0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOll0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOll0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOll0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOll100i_dataout : STD_LOGIC; + SIGNAL wire_nlOll100l_dataout : STD_LOGIC; + SIGNAL wire_nlOll100O_dataout : STD_LOGIC; + SIGNAL wire_nlOll101i_dataout : STD_LOGIC; + SIGNAL wire_nlOll101l_dataout : STD_LOGIC; + SIGNAL wire_nlOll101O_dataout : STD_LOGIC; + SIGNAL wire_nlOll10i_dataout : STD_LOGIC; + SIGNAL wire_nlOll10ii_dataout : STD_LOGIC; + SIGNAL wire_nlOll10il_dataout : STD_LOGIC; + SIGNAL wire_nlOll10iO_dataout : STD_LOGIC; + SIGNAL wire_nlOll10l_dataout : STD_LOGIC; + SIGNAL wire_nlOll10li_dataout : STD_LOGIC; + SIGNAL wire_nlOll10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOll10lO_dataout : STD_LOGIC; + SIGNAL wire_nlOll10O_dataout : STD_LOGIC; + SIGNAL wire_nlOll10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOll10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOll10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOll110i_dataout : STD_LOGIC; + SIGNAL wire_nlOll110l_dataout : STD_LOGIC; + SIGNAL wire_nlOll110O_dataout : STD_LOGIC; + SIGNAL wire_nlOll111i_dataout : STD_LOGIC; + SIGNAL wire_nlOll111l_dataout : STD_LOGIC; + SIGNAL wire_nlOll111O_dataout : STD_LOGIC; + SIGNAL wire_nlOll11i_dataout : STD_LOGIC; + SIGNAL wire_nlOll11ii_dataout : STD_LOGIC; + SIGNAL wire_nlOll11il_dataout : STD_LOGIC; + SIGNAL wire_nlOll11iO_dataout : STD_LOGIC; + SIGNAL wire_nlOll11l_dataout : STD_LOGIC; + SIGNAL wire_nlOll11li_dataout : STD_LOGIC; + SIGNAL wire_nlOll11ll_dataout : STD_LOGIC; + SIGNAL wire_nlOll11lO_dataout : STD_LOGIC; + SIGNAL wire_nlOll11O_dataout : STD_LOGIC; + SIGNAL wire_nlOll11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOll11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOll11OO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOll1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOll1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1il_dataout : STD_LOGIC; + SIGNAL wire_nlOll1ill_dataout : STD_LOGIC; + SIGNAL wire_nlOll1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOll1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOll1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOll1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOll1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOll1li_dataout : STD_LOGIC; + SIGNAL wire_nlOll1lil_dataout : STD_LOGIC; + SIGNAL wire_nlOll1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOll1lli_dataout : STD_LOGIC; + SIGNAL wire_nlOll1lll_dataout : STD_LOGIC; + SIGNAL wire_nlOll1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOll1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOll1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOll1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOll1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOll1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOll1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOll1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOll1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOll1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOll1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlli00i_dataout : STD_LOGIC; + SIGNAL wire_nlOlli01i_dataout : STD_LOGIC; + SIGNAL wire_nlOlli01l_dataout : STD_LOGIC; + SIGNAL wire_nlOlli01O_dataout : STD_LOGIC; + SIGNAL wire_nlOlli0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlli0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlli0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlli0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlli0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlli10i_dataout : STD_LOGIC; + SIGNAL wire_nlOlli10l_dataout : STD_LOGIC; + SIGNAL wire_nlOlli10O_dataout : STD_LOGIC; + SIGNAL wire_nlOlli11O_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1li_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlli1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOllii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOllii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOllii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlliii_dataout : STD_LOGIC; + SIGNAL wire_nlOlliiii_dataout : STD_LOGIC; + SIGNAL wire_nlOlliiil_dataout : STD_LOGIC; + SIGNAL wire_nlOlliiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlliil_dataout : STD_LOGIC; + SIGNAL wire_nlOlliili_dataout : STD_LOGIC; + SIGNAL wire_nlOlliill_dataout : STD_LOGIC; + SIGNAL wire_nlOlliilO_dataout : STD_LOGIC; + SIGNAL wire_nlOlliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlliiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlliiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlliiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOllil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOllili_dataout : STD_LOGIC; + SIGNAL wire_nlOllill_dataout : STD_LOGIC; + SIGNAL wire_nlOllilO_dataout : STD_LOGIC; + SIGNAL wire_nlOlliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlll00i_dataout : STD_LOGIC; + SIGNAL wire_nlOlll00l_dataout : STD_LOGIC; + SIGNAL wire_nlOlll00O_dataout : STD_LOGIC; + SIGNAL wire_nlOlll01i_dataout : STD_LOGIC; + SIGNAL wire_nlOlll01l_dataout : STD_LOGIC; + SIGNAL wire_nlOlll01O_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0il_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0li_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlll0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlll10i_dataout : STD_LOGIC; + SIGNAL wire_nlOlll10l_dataout : STD_LOGIC; + SIGNAL wire_nlOlll10O_dataout : STD_LOGIC; + SIGNAL wire_nlOlll11i_dataout : STD_LOGIC; + SIGNAL wire_nlOlll11l_dataout : STD_LOGIC; + SIGNAL wire_nlOlll11O_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1il_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1li_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlll1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOllli0l_dataout : STD_LOGIC; + SIGNAL wire_nlOllli0O_dataout : STD_LOGIC; + SIGNAL wire_nlOllli1i_dataout : STD_LOGIC; + SIGNAL wire_nlOllli1l_dataout : STD_LOGIC; + SIGNAL wire_nlOllli1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlllii_dataout : STD_LOGIC; + SIGNAL wire_nlOllliii_dataout : STD_LOGIC; + SIGNAL wire_nlOllliil_dataout : STD_LOGIC; + SIGNAL wire_nlOllliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlllil_dataout : STD_LOGIC; + SIGNAL wire_nlOlllili_dataout : STD_LOGIC; + SIGNAL wire_nlOlllill_dataout : STD_LOGIC; + SIGNAL wire_nlOlllilO_dataout : STD_LOGIC; + SIGNAL wire_nlOllliO_dataout : STD_LOGIC; + SIGNAL wire_nlOllliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOllliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOllliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOllll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOllll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOllll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlllli_dataout : STD_LOGIC; + SIGNAL wire_nlOlllliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlllll_dataout : STD_LOGIC; + SIGNAL wire_nlOllllli_dataout : STD_LOGIC; + SIGNAL wire_nlOllllll_dataout : STD_LOGIC; + SIGNAL wire_nlOlllllO_dataout : STD_LOGIC; + SIGNAL wire_nlOllllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlllO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlllO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlllO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlllO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlllO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOil_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlllOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOllO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOllO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOllO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOllO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOllO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOllO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOllO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOllO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOllO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOii_dataout : STD_LOGIC; + SIGNAL wire_nlOllOil_dataout : STD_LOGIC; + SIGNAL wire_nlOllOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOli_dataout : STD_LOGIC; + SIGNAL wire_nlOllOll_dataout : STD_LOGIC; + SIGNAL wire_nlOllOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOllOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOllOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOllOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOllOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOllOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO001i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO001l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO00ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO00il_dataout : STD_LOGIC; + SIGNAL wire_nlOlO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlO00OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO010O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01il_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01li_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlO01OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0Oii_w_lg_dataout21224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO101i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO101l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO101O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10li_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlO10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO110i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO110l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO110O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO111i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO111l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO111O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11il_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11li_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlO11OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lil_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1liO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lli_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1llO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi00O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0il_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi10l_w_lg_dataout26817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi10O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi10O_w_lg_dataout26844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1ii_w_lg_dataout26814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi1il_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1il_w_lg_dataout26812w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1iO_w_lg_dataout26810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1li_w_lg_dataout26808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1ll_w_lg_dataout26806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOi1lO_w_lg_dataout26804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOlOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOili_dataout : STD_LOGIC; + SIGNAL wire_nlOlOill_dataout : STD_LOGIC; + SIGNAL wire_nlOlOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl00i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl00l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl00O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl01i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl01l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl01O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0il_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0li_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl10i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl10l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl10O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl11i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl11l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl11O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl1il_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOli1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOliii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOliil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlili_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlill_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlilO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOllOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO10i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO10O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOlOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOili_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOill_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOlOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO000i_dataout : STD_LOGIC; + SIGNAL wire_nlOO000l_dataout : STD_LOGIC; + SIGNAL wire_nlOO000O_dataout : STD_LOGIC; + SIGNAL wire_nlOO001i_dataout : STD_LOGIC; + SIGNAL wire_nlOO001l_dataout : STD_LOGIC; + SIGNAL wire_nlOO001O_dataout : STD_LOGIC; + SIGNAL wire_nlOO00ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO00il_dataout : STD_LOGIC; + SIGNAL wire_nlOO00iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO00li_dataout : STD_LOGIC; + SIGNAL wire_nlOO00ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO00lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO00Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO00Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO00OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0101i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0101l_dataout : STD_LOGIC; + SIGNAL wire_nlOO010i_dataout : STD_LOGIC; + SIGNAL wire_nlOO010l_dataout : STD_LOGIC; + SIGNAL wire_nlOO010O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0110i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0110l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0110O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0111i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0111l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0111O_dataout : STD_LOGIC; + SIGNAL wire_nlOO011i_dataout : STD_LOGIC; + SIGNAL wire_nlOO011ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO011il_dataout : STD_LOGIC; + SIGNAL wire_nlOO011iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO011l_dataout : STD_LOGIC; + SIGNAL wire_nlOO011li_dataout : STD_LOGIC; + SIGNAL wire_nlOO011ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO011lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO011O_dataout : STD_LOGIC; + SIGNAL wire_nlOO011Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO011Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO011OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO01il_dataout : STD_LOGIC; + SIGNAL wire_nlOO01iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO01li_dataout : STD_LOGIC; + SIGNAL wire_nlOO01ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO01lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO01OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ili_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ill_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOli_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0iOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l00i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l00l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l00O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l01i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l01l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l01O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0il_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0li_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l10i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l10l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l10O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l11i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l11l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l11O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1il_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1li_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO0l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0li1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0liii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0liil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0liiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lili_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lill_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0liO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0liOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0liOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0liOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lliO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llli_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lllO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0llOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOli_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O00i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O00l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O00O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O01i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O01l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O01O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0il_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0li_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O10i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O10l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O10O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O11i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O11l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O11O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1il_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1li_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO0O1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oili_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oill_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Ol1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Olii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Olil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OliO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Olli_dataout : STD_LOGIC; + SIGNAL wire_nlOO0Olll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OllO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOii_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOil_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOli_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOll_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO0OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1000i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1000l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1000O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1001i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1001l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1001O_dataout : STD_LOGIC; + SIGNAL wire_nlOO100i_dataout : STD_LOGIC; + SIGNAL wire_nlOO100ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO100il_dataout : STD_LOGIC; + SIGNAL wire_nlOO100iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO100l_dataout : STD_LOGIC; + SIGNAL wire_nlOO100li_dataout : STD_LOGIC; + SIGNAL wire_nlOO100ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO100lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO100O_dataout : STD_LOGIC; + SIGNAL wire_nlOO100Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO100Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO100OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1010i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1010l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1010O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1011i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1011l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1011O_dataout : STD_LOGIC; + SIGNAL wire_nlOO101i_dataout : STD_LOGIC; + SIGNAL wire_nlOO101ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO101il_dataout : STD_LOGIC; + SIGNAL wire_nlOO101iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO101l_dataout : STD_LOGIC; + SIGNAL wire_nlOO101li_dataout : STD_LOGIC; + SIGNAL wire_nlOO101ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO101lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO101O_dataout : STD_LOGIC; + SIGNAL wire_nlOO101Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO101Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO101OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO10ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO10iii_dataout : STD_LOGIC; + SIGNAL wire_nlOO10iil_dataout : STD_LOGIC; + SIGNAL wire_nlOO10iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10il_dataout : STD_LOGIC; + SIGNAL wire_nlOO10ili_dataout : STD_LOGIC; + SIGNAL wire_nlOO10ill_dataout : STD_LOGIC; + SIGNAL wire_nlOO10ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO10iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO10iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO10li_dataout : STD_LOGIC; + SIGNAL wire_nlOO10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO10lli_dataout : STD_LOGIC; + SIGNAL wire_nlOO10lll_dataout : STD_LOGIC; + SIGNAL wire_nlOO10llO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO10lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO10lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO10O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO10Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOO10Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO10Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOO10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO10OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO10OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO10OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1100i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1100l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1100O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1101i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1101l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1101O_dataout : STD_LOGIC; + SIGNAL wire_nlOO110i_dataout : STD_LOGIC; + SIGNAL wire_nlOO110ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO110il_dataout : STD_LOGIC; + SIGNAL wire_nlOO110iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO110l_dataout : STD_LOGIC; + SIGNAL wire_nlOO110li_dataout : STD_LOGIC; + SIGNAL wire_nlOO110ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO110lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO110O_dataout : STD_LOGIC; + SIGNAL wire_nlOO110Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO110Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO110OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1110i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1110l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1110O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1111l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1111O_dataout : STD_LOGIC; + SIGNAL wire_nlOO111i_dataout : STD_LOGIC; + SIGNAL wire_nlOO111ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO111il_dataout : STD_LOGIC; + SIGNAL wire_nlOO111iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO111l_dataout : STD_LOGIC; + SIGNAL wire_nlOO111O_dataout : STD_LOGIC; + SIGNAL wire_nlOO111Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO111Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO111OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO11iii_dataout : STD_LOGIC; + SIGNAL wire_nlOO11iil_dataout : STD_LOGIC; + SIGNAL wire_nlOO11il_dataout : STD_LOGIC; + SIGNAL wire_nlOO11ill_dataout : STD_LOGIC; + SIGNAL wire_nlOO11ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO11iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO11iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11li_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lii_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lil_dataout : STD_LOGIC; + SIGNAL wire_nlOO11liO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lli_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lll_dataout : STD_LOGIC; + SIGNAL wire_nlOO11llO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO11lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO11O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO11Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOO11Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOO11OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO11Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOO11Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOO11OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO11OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i00i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i00l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i00O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i01i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i01l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i01O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0il_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0li_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i10i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i10l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i11i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i11l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i11O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO1i1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iiii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iiil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iili_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iill_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1il1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ili_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ilii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ilil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iliO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ill_dataout : STD_LOGIC; + SIGNAL wire_nlOO1illi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1illl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1illO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO0i_w_lg_dataout24105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1iO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO0l_w_lg_dataout26694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1iO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iO1O_w_lg_dataout24104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iOii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iOil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l00i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l00l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l00O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l01i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l01l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l01O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0il_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0li_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l10O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1ii_w_lg_dataout24112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1il_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1iO_w_lg_dataout24024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1li_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1li_w_lg_dataout24007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1ll_w_lg_dataout27120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1lO_w_lg_dataout27118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1Oi_w_lg_dataout27125w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1Ol_w_lg_dataout27123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1l1OO_w_lg_w_lg_dataout27122w27128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1l1OO_w_lg_dataout27122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOO1li0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1li0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1li0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1li1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1li1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1li1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1liii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1liil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1liiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lili_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lill_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1liO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1liOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1liOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1liOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1ll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lli_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lliO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llli_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lllO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1llOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOli_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1lOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O00i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O00l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O00O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O01i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O01l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O01O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0il_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0li_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O11i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O11l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O11O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oiii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oiil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oili_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oill_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OilO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Olli_dataout : STD_LOGIC; + SIGNAL wire_nlOO1Olll_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OllO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOii_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOil_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOli_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOO1OOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi00i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi00l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi00O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi010i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi010l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi010O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi011i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi011l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi011O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01il_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01li_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi01O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0iii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0iil_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0il_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0ili_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0ill_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0li_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lil_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0liO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOi0OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi100i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi100l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi100O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi101i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi101l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi101O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10il_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10li_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOi10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi110i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi110l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi110O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi111i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi111l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi111O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11il_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11li_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOi11OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1iii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1il_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1ili_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1ill_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1iOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1li_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lil_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1liO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lli_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1llO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOi1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOii00i_dataout : STD_LOGIC; + SIGNAL wire_nlOOii00l_dataout : STD_LOGIC; + SIGNAL wire_nlOOii00O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii01i_dataout : STD_LOGIC; + SIGNAL wire_nlOOii01l_dataout : STD_LOGIC; + SIGNAL wire_nlOOii01O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0il_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0li_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOii0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOii10i_dataout : STD_LOGIC; + SIGNAL wire_nlOOii10l_dataout : STD_LOGIC; + SIGNAL wire_nlOOii10O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii11i_dataout : STD_LOGIC; + SIGNAL wire_nlOOii11l_dataout : STD_LOGIC; + SIGNAL wire_nlOOii11O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1il_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1li_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOii1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiii1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiiii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiiil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiili_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiill_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiil1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiili_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiliO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiill_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilli_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilll_dataout : STD_LOGIC; + SIGNAL wire_nlOOiillO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOil00i_dataout : STD_LOGIC; + SIGNAL wire_nlOOil00l_dataout : STD_LOGIC; + SIGNAL wire_nlOOil00O_dataout : STD_LOGIC; + SIGNAL wire_nlOOil01i_dataout : STD_LOGIC; + SIGNAL wire_nlOOil01l_dataout : STD_LOGIC; + SIGNAL wire_nlOOil01O_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0il_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0li_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOil0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOil10i_dataout : STD_LOGIC; + SIGNAL wire_nlOOil10l_dataout : STD_LOGIC; + SIGNAL wire_nlOOil10O_dataout : STD_LOGIC; + SIGNAL wire_nlOOil11i_dataout : STD_LOGIC; + SIGNAL wire_nlOOil11l_dataout : STD_LOGIC; + SIGNAL wire_nlOOil11O_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1il_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1li_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOil1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOilii_dataout : STD_LOGIC; + SIGNAL wire_nlOOilil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiliO_dataout : STD_LOGIC; + SIGNAL wire_nlOOilli_dataout : STD_LOGIC; + SIGNAL wire_nlOOilll_dataout : STD_LOGIC; + SIGNAL wire_nlOOillO_dataout : STD_LOGIC; + SIGNAL wire_nlOOilOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOilOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOilOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOiO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOiOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl00i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl00l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl00O_dataout : STD_LOGIC; + SIGNAL wire_nlOOl01i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl01l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl01O_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0il_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0li_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10li_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10O_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOl10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11il_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11li_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11O_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOl11OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1il_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1iOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1iOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1li_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOl1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOli0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOli0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOli0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOli1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOli1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOli1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOliii_dataout : STD_LOGIC; + SIGNAL wire_nlOOliil_dataout : STD_LOGIC; + SIGNAL wire_nlOOliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlili_dataout : STD_LOGIC; + SIGNAL wire_nlOOlill_dataout : STD_LOGIC; + SIGNAL wire_nlOOlilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOllii_dataout : STD_LOGIC; + SIGNAL wire_nlOOllil_dataout : STD_LOGIC; + SIGNAL wire_nlOOlliO_dataout : STD_LOGIC; + SIGNAL wire_nlOOllli_dataout : STD_LOGIC; + SIGNAL wire_nlOOllll_dataout : STD_LOGIC; + SIGNAL wire_nlOOlllO_dataout : STD_LOGIC; + SIGNAL wire_nlOOllOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOllOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOllOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO010i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO010l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO010O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO011i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO011l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO011O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01il_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01li_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOO01OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l0O_w_lg_dataout24214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0l1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0l1O_w_lg_dataout24218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lii_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lil_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0liO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0liO_w_lg_dataout24210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lli_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lll_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0llO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0llO_w_lg_dataout24206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0lOO_w_lg_dataout24202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O0O_w_lg_dataout24194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0O1O_w_lg_dataout24198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0OiO_w_lg_dataout24190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10il_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10li_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOO10OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1i1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1iii_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1iil_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1iiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1ili_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1ill_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1ilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1lOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1lOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1O1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1Oii_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1Oil_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1OiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1Oli_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1Oll_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1OlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1OOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1OOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOO1OOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOili_dataout : STD_LOGIC; + SIGNAL wire_nlOOOill_dataout : STD_LOGIC; + SIGNAL wire_nlOOOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl00l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl00O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0il_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0li_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOli1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOliii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOliil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOliiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlili_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlill_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOliO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOliOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOliOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOliOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOll1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlliO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlllO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOllOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOlOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO00i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO00l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO00O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO01i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO01l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO01O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0il_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0li_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO0OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO10i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO10l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO10O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO11i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO11l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO11O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1ii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1il_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1iO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1li_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1ll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1lO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1Oi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1Ol_dataout : STD_LOGIC; + SIGNAL wire_nlOOOO1OO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOi1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOiii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOiil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOiiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOili_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOill_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOilO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOiOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOiOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOiOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOl1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOlii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO0i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO0l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO0O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO1i_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO1l_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOO1O_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOii_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOil_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOiO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOli_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOll_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOlO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOO_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOOi_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOOl_dataout : STD_LOGIC; + SIGNAL wire_nlOOOOOOO_dataout : STD_LOGIC; + SIGNAL wire_n0000OiO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0000OiO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_gnd : STD_LOGIC; + SIGNAL wire_n0000OiO_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n000l1il_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n000l1il_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n000l1il_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0010iil_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0010iil_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0010iil_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0011OOl_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0011OOl_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0011OOl_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n001i0Ol_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001i0Ol_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001i0Ol_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001li0i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001li0i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n001li0i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n00il11O_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n00il11O_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n00il11O_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n00ililO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00ililO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00ililO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00l11lO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n00l11lO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n00l11lO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n00lll1O_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00lll1O_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00lll1O_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n00lO1lO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00lO1lO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00lO1lO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00O01il_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n00O01il_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n00O01il_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n00O111O_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n00O111O_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n00O111O_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n00OOiOi_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00OOiOi_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00OOiOi_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n010l0li_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n010l0li_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n010l0li_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n010lO0i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010lO0i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010lO0i_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010Olli_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n010Olli_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n010Olli_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n011illi_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n011illi_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n011illi_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n011l00i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011l00i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011l00i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n011OO0i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n011OO0i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n011OO0i_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n01i1lOO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n01i1lOO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n01i1lOO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n01iO00l_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iO00l_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iO00l_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01l1i0i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n01l1i0i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n01l1i0i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n01O10Ol_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n01O10Ol_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n01O10Ol_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n01O1Oil_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n01O1Oil_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n01O1Oil_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n01Oiiil_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n01Oiiil_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n01Oiiil_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0i0001i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i0001i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i0001i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0i01lii_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0i01lii_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0i01lii_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0i0iO1i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0i0iO1i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0i0iO1i_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0i11llO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0i11llO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0i11llO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0ii00ii_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ii00ii_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ii00ii_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ii0O1i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii0O1i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii0O1i_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0iiilii_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0iiilii_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0iiilii_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0iilllO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0iilllO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0iilllO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0ili01l_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0ili01l_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0ili01l_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0illi1i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0illi1i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0illi1i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0iOl0ll_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0iOl0ll_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0iOl0ll_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0iOlO0l_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iOlO0l_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0iOlO0l_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0l00i1i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0l00i1i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0l00i1i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0l010ll_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0l010ll_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0l010ll_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0l0OO0O_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0OO0O_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0OO0O_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l11i0l_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0l11i0l_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0l11i0l_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0l1lOll_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0l1lOll_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0l1lOll_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0l1Oi0l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l1Oi0l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l1Oi0l_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0li010l_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0li010l_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0li010l_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0ll0iiO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ll0iiO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ll0iiO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0ll1OOO_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0ll1OOO_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0ll1OOO_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0lll1iO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0lll1iO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0lll1iO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0lO0iOO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0lO0iOO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0lO0iOO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0lOi1iO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lOi1iO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lOi1iO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lOiOOO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0lOiOOO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0lOiOOO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0lOO10l_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0lOO10l_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0lOO10l_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0O0ll0i_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0O0ll0i_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0O0ll0i_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0O0O1Oi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0O0O1Oi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0O0O1Oi_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0O1iili_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1iili_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1iili_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1lliO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0O1lliO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0O1lliO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0Oi1lOi_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0Oi1lOi_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0Oi1lOi_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n0OiO00i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0OiO00i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0OiO00i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n0OiOlOi_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OiOlOi_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OiOlOi_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Ol0liO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0Ol0liO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0Ol0liO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0Ol1l0i_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0Ol1l0i_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0Ol1l0i_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0OO00Oi_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0OO00Oi_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0OO00Oi_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n0OO11Ol_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0OO11Ol_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0OO11Ol_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n110100O_a : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_n110100O_b : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_n110100O_o : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_n11010li_a : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_n11010li_b : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_n11010li_o : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_n11ilO1i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11ilO1i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11ilO1i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n11ll01O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n11ll01O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n11ll01O_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1iiOl0l_a : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1iiOl0l_b : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1iiOl0l_o : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1il11ii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1il11ii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1il11ii_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1ill0Oi_a : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_n1ill0Oi_b : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_n1ill0Oi_o : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_n1ilOlOl_a : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1ilOlOl_b : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1ilOlOl_o : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1ilOlOO_a : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1ilOlOO_b : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1ilOlOO_o : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_n1iO0i1O_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1iO0i1O_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1iO0i1O_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1iO1lOl_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1iO1lOl_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1iO1lOl_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1iOi1Oi_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_n1iOi1Oi_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_n1iOi1Oi_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_n1iOO1li_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1iOO1li_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1iOO1li_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1iOOOil_a : STD_LOGIC_VECTOR (18 DOWNTO 0); + SIGNAL wire_n1iOOOil_b : STD_LOGIC_VECTOR (18 DOWNTO 0); + SIGNAL wire_n1iOOOil_o : STD_LOGIC_VECTOR (18 DOWNTO 0); + SIGNAL wire_n1l010Ol_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l010Ol_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l010Ol_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l01i1l_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1l01i1l_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1l01i1l_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1l01iii_a : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l01iii_b : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l01iii_o : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1l01O1i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1l01O1i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1l01O1i_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1l1Ol1O_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1l1Ol1O_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1l1Ol1O_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1lii0ll_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1lii0ll_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1lii0ll_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1lil0li_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lil0li_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lil0li_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lil1ll_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lil1ll_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lil1ll_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lil1lO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lil1lO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lil1lO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOilOl_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOilOl_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1lOilOl_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O100i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O100i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O100i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O1iOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O1iOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1O1iOi_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oi110O_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1Oi110O_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1Oi110O_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1Oi1iOO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oi1iOO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oi1iOO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oii1OO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oii1OO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Oii1OO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1Ol01OO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Ol01OO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Ol01OO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Ol1l0O_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Ol1l0O_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Ol1l0O_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1Oli10O_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Oli10O_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Oli10O_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Oll1ll_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Oll1ll_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1Oll1ll_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1OO0l1i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO0l1i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO0l1i_o : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OOilOO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1OOilOO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1OOilOO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_ni00lO0O_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni00lO0O_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni00lO0O_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni00lOil_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni00lOil_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni00lOil_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni01O01i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni01O01i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni01O01i_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni01O1Ol_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni01O1Ol_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni01O1Ol_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni100OO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni100OO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni100OO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1010O_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1010O_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni1010O_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_ni101liO_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni101liO_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni101liO_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni101lll_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni101lll_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni101lll_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni11010i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni11010i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni11010i_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni11011l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni11011l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni11011l_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1i1i1i_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1i1i1i_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1i1i1i_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1i1i1O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1i1i1O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1i1i1O_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1l11il_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1l11il_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1l11il_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1l11li_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1l11li_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1l11li_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1lOlOO_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1lOlOO_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1lOlOO_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1lOO1l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1lOO1l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1lOO1l_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1OOiii_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1OOiii_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1OOiii_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1OOiiO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1OOiiO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1OOiiO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii1l00l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii1l00l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nii1l00l_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_niii0iiO_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niii0iiO_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niii0iiO_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil100li_a : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nil100li_b : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nil100li_o : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nil100ll_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nil100ll_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nil100ll_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nil100lO_a : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nil100lO_b : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nil100lO_o : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nil10liO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nil10liO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nil10liO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_niO0li0O_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO0li0O_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niO0li0O_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOi11li_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOi11li_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOi11li_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOlii1l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOlii1l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOlii1l_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOlOi0l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOlOi0l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_niOlOi0l_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl00iOil_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl00iOil_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl00iOil_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01i10li_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01i10li_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01i10li_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01i11Oi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl01i11Oi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl01i11Oi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl01illi_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01illi_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01illi_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01iO0O_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01iO0O_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01iO0O_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01l1lii_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl01l1lii_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl01l1lii_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl01l1lii_w_o_range53564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01l1lil_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl01l1lil_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl01l1lil_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl01lliOO_a : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl01lliOO_b : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl01lliOO_o : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl01lO0ii_a : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl01lO0ii_b : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl01lO0ii_o : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl0iiOiO_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0iiOiO_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0iiOiO_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0iliil_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl0iliil_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl0iliil_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl0iliiO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl0iliiO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl0iliiO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl0ilil0l_a : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl0ilil0l_b : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl0ilil0l_o : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl0iO01l_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0iO01l_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0iO01l_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0iO0ll_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0iO0ll_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0iO0ll_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0l01l1i_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0l01l1i_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0l01l1i_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl0l0Oii_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl0l0Oii_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl0l0Oii_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl0l0Oil_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl0l0Oil_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl0l0Oil_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl0lil1i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0lil1i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0lil1i_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0lilli_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0lilli_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0lilli_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl101i0li_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl101i0li_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl101i0li_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl10iiOll_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl10iiOll_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl10iiOll_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl10iiOlO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10iiOlO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10iiOlO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10iiOOi_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10iiOOi_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10iiOOi_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10il1iO_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl10il1iO_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl10il1iO_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl10iOi0l_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10iOi0l_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10iOi0l_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl10lOO1l_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10lOO1l_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10lOO1l_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10lOOli_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10lOOli_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10lOOli_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10O011l_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O011l_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O011l_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O01Oi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O01Oi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O01Oi_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O111l_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10O111l_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10O111l_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl10O1O0O_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O1O0O_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O1O0O_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl110iOil_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110iOil_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110iOil_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110iOli_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110iOli_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110iOli_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110l1Oi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110l1Oi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110l1Oi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110l1Ol_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110l1Ol_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110l1Ol_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110liiO_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110liiO_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110liiO_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110lill_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110lill_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110lill_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110llOl_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110llOl_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110llOl_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110llOO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110llOO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110llOO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110O0OO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110O0OO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110O0OO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl110O1li_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110O1li_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110O1li_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl110O1lO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110O1lO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110O1lO_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl110Oi1i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110Oi1i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl110Oi1i_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl111l1li_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111l1li_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111l1li_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111l1ll_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111l1ll_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111l1ll_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111O0iO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111O0iO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111O0iO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111O0lO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111O0lO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111O0lO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111Oi0i_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111Oi0i_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111Oi0i_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl111Oi1i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111Oi1i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111Oi1i_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111Oiil_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111Oiil_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111Oiil_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111Oill_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111Oill_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111Oill_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111OllO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111OllO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111OllO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl111OlOO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111OlOO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl111OlOO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl11Oil1i_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl11Oil1i_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl11Oil1i_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl11Oil1O_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl11Oil1O_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl11Oil1O_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1i00lli_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i00lli_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i00lli_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i00OlO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i00OlO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i00OlO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0ii0l_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0ii0l_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0ii0l_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0ilil_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0ilil_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0ilil_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0l0il_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0l0il_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0l0il_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0l10i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0l10i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0l10i_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0ll0O_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0ll0O_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0ll0O_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0ll1O_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i0ll1O_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i0ll1O_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i0lOli_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i0lOli_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i0lOli_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i0lOOi_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0lOOi_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0lOOi_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0O0li_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i0O0li_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i0O0li_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i0O0Oi_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0O0Oi_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0O0Oi_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i0Ol0l_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0Ol0l_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0Ol0l_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i0Ol1l_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i0Ol1l_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i0Ol1l_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11lil_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11lil_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11lil_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11liO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11liO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11liO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11lli_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11lli_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11lli_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11lll_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11lll_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11lll_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11llO_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11llO_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11llO_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1i11lOi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11lOi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i11lOi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1i1iOOi_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1iOOi_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1iOOi_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1l1OO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1l1OO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1l1OO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1llil_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1llil_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1llil_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1lOli_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1lOli_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1lOli_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1O00O_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1O00O_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1O00O_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i1OiiO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1OiiO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1i1OiiO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1ii10iO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1ii10iO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1ii10iO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1ii10lO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1ii10lO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1ii10lO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1ii110l_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ii110l_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ii110l_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ii111l_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii111l_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii111l_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1iiO10l_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1iiO10l_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1iiO10l_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1iiO11l_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1iiO11l_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1iiO11l_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1iiO11O_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiO11O_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiO11O_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiO1ii_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiO1ii_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiO1ii_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1il10lO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il10lO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il10lO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1iliill_w_lg_w_o_range56062w56066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1iliill_w_lg_w_o_range56060w56980w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1iliill_w_lg_w_o_range56060w56061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1iliill_w_lg_w_o_range56062w56063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1iliill_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1iliill_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1iliill_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1iliill_w_o_range56060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1iliill_w_o_range56062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1llill_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llill_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llill_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llliOi_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1llliOi_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1llliOi_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1lllll_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lllll_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1lllll_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1llO1ii_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1llO1ii_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1llO1ii_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1lO110l_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1lO110l_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1lO110l_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1lO11ii_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1lO11ii_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1lO11ii_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1O101i_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O101i_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1O101i_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1OlilOO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OlilOO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OlilOO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1i1O_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1i1O_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1i1O_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1ili_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1ili_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1ili_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1lOl_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OO1lOl_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OO1lOl_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OO1lOO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1lOO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1lOO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OO1O1i_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OO1O1i_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OO1O1i_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OOlOii_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1OOlOii_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1OOlOii_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1OOlOOO_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1OOlOOO_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1OOlOOO_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1OOO0ii_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1OOO0ii_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1OOO0ii_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1OOO0il_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OOO0il_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OOO0il_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1OOO0iO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOO0iO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOO0iO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOiOi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOiOi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOiOi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOOOl_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOOOl_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOOOl_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nli10l0l_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli10l0l_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli10l0l_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli10OOl_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli10OOl_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nli10OOl_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil0001i_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlil0001i_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlil0001i_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlil011li_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil011li_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil011li_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil01OiO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlil01OiO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlil01OiO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlil100ll_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil100ll_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil100ll_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil10iOl_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil10iOl_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil10iOl_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil11l1i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlil11l1i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlil11l1i_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliliOllO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliliOllO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliliOllO_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nliliOOii_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliliOOii_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliliOOii_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill10ii_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill10ii_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill10ii_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill111l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill111l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill111l_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill11lO_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlill11lO_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlill11lO_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlill1i1l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill1i1l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill1i1l_o : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill1iOi_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill1iOi_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlill1iOi_o : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlilOilii_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilOilii_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilOilii_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nll0lO1Oi_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nll0lO1Oi_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nll0lO1Oi_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nll0lOOil_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nll0lOOil_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nll0lOOil_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nll0O00lO_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nll0O00lO_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nll0O00lO_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlli00lii_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli00lii_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli00lii_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli00liO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlli00liO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlli00liO_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlli00Oll_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli00Oll_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli00Oll_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli01l1l_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli01l1l_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli01l1l_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlli01Oll_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlli01Oll_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlli01Oll_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlli0l1i_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlli0l1i_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlli0l1i_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlliiOOi_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlliiOOi_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlliiOOi_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlliiOOO_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlliiOOO_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlliiOOO_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlliOl1ii_a : STD_LOGIC_VECTOR (32 DOWNTO 0); + SIGNAL wire_nlliOl1ii_b : STD_LOGIC_VECTOR (32 DOWNTO 0); + SIGNAL wire_nlliOl1ii_o : STD_LOGIC_VECTOR (32 DOWNTO 0); + SIGNAL wire_nlliOl1il_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlliOl1il_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlliOl1il_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlliOl1iO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOl1iO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOl1iO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOlOlO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOlOlO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOlOlO_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOlOOi_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOlOOi_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOlOOi_o : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nlliOO1il_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlliOO1il_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlliOO1il_o : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlll0010l_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlll0010l_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlll0010l_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlll01lll_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlll01lll_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlll01lll_o : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nlll0iiOl_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0iiOl_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0iiOl_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0lO1i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0lO1i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0lO1i_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0lO1O_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlll0lO1O_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlll0lO1O_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlll0lOil_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlll0lOil_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlll0lOil_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlll0lOiO_a : STD_LOGIC_VECTOR (32 DOWNTO 0); + SIGNAL wire_nlll0lOiO_b : STD_LOGIC_VECTOR (32 DOWNTO 0); + SIGNAL wire_nlll0lOiO_o : STD_LOGIC_VECTOR (32 DOWNTO 0); + SIGNAL wire_nlll0lOli_a : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nlll0lOli_b : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nlll0lOli_o : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nlll10OlO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll10OlO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll10OlO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll10OOi_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll10OOi_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll10OOi_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll1i1ii_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll1i1ii_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll1i1ii_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll1iiOl_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll1iiOl_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll1iiOl_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll1iiOO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll1iiOO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll1iiOO_o : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll1Olii_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll1Olii_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlll1Olii_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nllliOli_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllliOli_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllliOli_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllll00i_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllll00i_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nllll00i_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlO0lll1O_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lll1O_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lll1O_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lO00i_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlO0lO00i_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlO0lO00i_o : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nlO0lO0il_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lO0il_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lO0il_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lOl0i_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lOl0i_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0lOl0i_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0O11iO_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0O11iO_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlO0O11iO_o : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlOil0ilO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOil0ilO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOil0ilO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOilllll_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOilllll_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOilllll_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOiO1OiO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOiO1OiO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOiO1OiO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOiO1OOO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOiO1OOO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOiO1OOO_o : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOll0O1i_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlOll0O1i_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlOll0O1i_o : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlOllli0i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOllli0i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOllli0i_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOllll0i_a : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nlOllll0i_b : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nlOllll0i_o : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nlOlOOOiO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOlOOOiO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOlOOOiO_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOO1OOll_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOO1OOll_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlOO1OOll_o : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl001lliO_i : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl001lliO_o : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL wire_nl00il01i_i : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl00il01i_o : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL wire_n0000Oll_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0000Oll_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_vcc : STD_LOGIC; + SIGNAL wire_n0000Oll_o : STD_LOGIC; + SIGNAL wire_n00010ll_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00010ll_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00010ll_o : STD_LOGIC; + SIGNAL wire_n00010OO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00010OO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00010OO_o : STD_LOGIC; + SIGNAL wire_n000l1ii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n000l1ii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n000l1ii_o : STD_LOGIC; + SIGNAL wire_n001101l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n001101l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n001101l_o : STD_LOGIC; + SIGNAL wire_n00110Oi_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00110Oi_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00110Oi_o : STD_LOGIC; + SIGNAL wire_n00liiOO_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n00liiOO_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n00liiOO_o : STD_LOGIC; + SIGNAL wire_n00liO0O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00liO0O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00liO0O_o : STD_LOGIC; + SIGNAL wire_n00ll11l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00ll11l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n00ll11l_o : STD_LOGIC; + SIGNAL wire_n00OiOOO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00OiOOO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00OiOOO_o : STD_LOGIC; + SIGNAL wire_n00Ol10i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00Ol10i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00Ol10i_o : STD_LOGIC; + SIGNAL wire_n00OOiOO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00OOiOO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n00OOiOO_o : STD_LOGIC; + SIGNAL wire_n010i0ii_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n010i0ii_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n010i0ii_o : STD_LOGIC; + SIGNAL wire_n010iiOi_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010iiOi_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010iiOi_o : STD_LOGIC; + SIGNAL wire_n010iliO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010iliO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n010iliO_o : STD_LOGIC; + SIGNAL wire_n01iilii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iilii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iilii_o : STD_LOGIC; + SIGNAL wire_n01iilll_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iilll_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iilll_o : STD_LOGIC; + SIGNAL wire_n01iO0ii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iO0ii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01iO0ii_o : STD_LOGIC; + SIGNAL wire_n01l1i1O_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01l1i1O_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n01l1i1O_o : STD_LOGIC; + SIGNAL wire_n01OOOll_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n01OOOll_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n01OOOll_o : STD_LOGIC; + SIGNAL wire_n0i11lll_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0i11lll_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0i11lll_o : STD_LOGIC; + SIGNAL wire_n0ii100i_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0ii100i_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0ii100i_o : STD_LOGIC; + SIGNAL wire_n0ii1ili_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii1ili_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii1ili_o : STD_LOGIC; + SIGNAL wire_n0ii1l0O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii1l0O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0ii1l0O_o : STD_LOGIC; + SIGNAL wire_n0il1l0i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0il1l0i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0il1l0i_o : STD_LOGIC; + SIGNAL wire_n0il1lil_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0il1lil_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0il1lil_o : STD_LOGIC; + SIGNAL wire_n0ili00i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0ili00i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0ili00i_o : STD_LOGIC; + SIGNAL wire_n0ill0OO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0ill0OO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0ill0OO_o : STD_LOGIC; + SIGNAL wire_n0l0l0il_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0l0il_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0l0il_o : STD_LOGIC; + SIGNAL wire_n0l0l0lO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0l0lO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0l0lO_o : STD_LOGIC; + SIGNAL wire_n0l0OOil_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0OOil_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0l0OOil_o : STD_LOGIC; + SIGNAL wire_n0l1iOil_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0l1iOil_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0l1iOil_o : STD_LOGIC; + SIGNAL wire_n0l1l0li_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l1l0li_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l1l0li_o : STD_LOGIC; + SIGNAL wire_n0l1l1Ol_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l1l1Ol_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0l1l1Ol_o : STD_LOGIC; + SIGNAL wire_n0li010i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0li010i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0li010i_o : STD_LOGIC; + SIGNAL wire_n0lO1ilO_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0lO1ilO_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0lO1ilO_o : STD_LOGIC; + SIGNAL wire_n0lO1O1O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lO1O1O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lO1O1O_o : STD_LOGIC; + SIGNAL wire_n0lO1OOl_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lO1OOl_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0lO1OOl_o : STD_LOGIC; + SIGNAL wire_n0O1011i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1011i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1011i_o : STD_LOGIC; + SIGNAL wire_n0O11OlO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O11OlO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O11OlO_o : STD_LOGIC; + SIGNAL wire_n0O1iilO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1iilO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1iilO_o : STD_LOGIC; + SIGNAL wire_n0O1llil_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1llil_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0O1llil_o : STD_LOGIC; + SIGNAL wire_n0Oi1lO_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_n0Oi1lO_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_n0Oi1lO_o : STD_LOGIC; + SIGNAL wire_n0Oil01i_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0Oil01i_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0Oil01i_o : STD_LOGIC; + SIGNAL wire_n0Oiliii_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oiliii_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oiliii_o : STD_LOGIC; + SIGNAL wire_n0Oill1O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oill1O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0Oill1O_o : STD_LOGIC; + SIGNAL wire_n0Olll0l_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0Olll0l_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0Olll0l_o : STD_LOGIC; + SIGNAL wire_n0Olll1i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0Olll1i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0Olll1i_o : STD_LOGIC; + SIGNAL wire_n0OO00lO_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0OO00lO_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0OO00lO_o : STD_LOGIC; + SIGNAL wire_n0OO101i_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0OO101i_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n0OO101i_o : STD_LOGIC; + SIGNAL wire_n10ilOOl_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10ilOOl_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10ilOOl_o : STD_LOGIC; + SIGNAL wire_n10l1i1i_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n10l1i1i_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n10l1i1i_o : STD_LOGIC; + SIGNAL wire_n10lil0l_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n10lil0l_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n10lil0l_o : STD_LOGIC; + SIGNAL wire_n110100l_w_lg_w_lg_o24931w24932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n110100l_w_lg_w_lg_o23825w23826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n110100l_w_lg_o24931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n110100l_w_lg_o23825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n110100l_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_n110100l_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_n110100l_o : STD_LOGIC; + SIGNAL wire_n11010iO_w_lg_w_lg_o23823w23824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11010iO_w_lg_w_lg_o24929w24930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11010iO_w_lg_o23823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11010iO_w_lg_o24929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n11010iO_a : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_n11010iO_b : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_n11010iO_o : STD_LOGIC; + SIGNAL wire_n11O100l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O100l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O100l_o : STD_LOGIC; + SIGNAL wire_n11O101l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O101l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O101l_o : STD_LOGIC; + SIGNAL wire_n11O10il_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O10il_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O10il_o : STD_LOGIC; + SIGNAL wire_n11O10ll_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O10ll_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O10ll_o : STD_LOGIC; + SIGNAL wire_n11O10Ol_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O10Ol_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O10Ol_o : STD_LOGIC; + SIGNAL wire_n11O11ll_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O11ll_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O11ll_o : STD_LOGIC; + SIGNAL wire_n11O11Ol_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O11Ol_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O11Ol_o : STD_LOGIC; + SIGNAL wire_n11O1i1i_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O1i1i_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11O1i1i_o : STD_LOGIC; + SIGNAL wire_n1l1Ol0i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1l1Ol0i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1l1Ol0i_o : STD_LOGIC; + SIGNAL wire_n1O000i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O000i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O000i_o : STD_LOGIC; + SIGNAL wire_n1O001i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O001i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O001i_o : STD_LOGIC; + SIGNAL wire_n1O101O_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O101O_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1O101O_o : STD_LOGIC; + SIGNAL wire_n1OiOl1O_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1OiOl1O_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n1OiOl1O_o : STD_LOGIC; + SIGNAL wire_n1OiOOiO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OiOOiO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1OiOOiO_o : STD_LOGIC; + SIGNAL wire_n1Ol110l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Ol110l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1Ol110l_o : STD_LOGIC; + SIGNAL wire_n1OO0l1O_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO0l1O_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO0l1O_o : STD_LOGIC; + SIGNAL wire_n1OO111O_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO111O_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO111O_o : STD_LOGIC; + SIGNAL wire_n1OO11ii_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO11ii_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OO11ii_o : STD_LOGIC; + SIGNAL wire_n1OOilOl_a : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OOilOl_b : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1OOilOl_o : STD_LOGIC; + SIGNAL wire_ni1010l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1010l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1010l_o : STD_LOGIC; + SIGNAL wire_ni1i00l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1i00l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1i00l_o : STD_LOGIC; + SIGNAL wire_ni1i0il_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1i0il_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1i0il_o : STD_LOGIC; + SIGNAL wire_nil0Olil_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0Olil_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0Olil_o : STD_LOGIC; + SIGNAL wire_nil0OO1O_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0OO1O_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nil0OO1O_o : STD_LOGIC; + SIGNAL wire_nili10lO_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nili10lO_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nili10lO_o : STD_LOGIC; + SIGNAL wire_nili111i_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nili111i_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nili111i_o : STD_LOGIC; + SIGNAL wire_nili11Ol_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nili11Ol_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nili11Ol_o : STD_LOGIC; + SIGNAL wire_nl00il01l_w_lg_o52792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl00il01l_a : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl00il01l_b : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl00il01l_o : STD_LOGIC; + SIGNAL wire_nl01i10lO_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl01i10lO_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl01i10lO_o : STD_LOGIC; + SIGNAL wire_nl01il01i_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl01il01i_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl01il01i_o : STD_LOGIC; + SIGNAL wire_nl01illOl_w_lg_o53585w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01illOl_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl01illOl_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl01illOl_o : STD_LOGIC; + SIGNAL wire_nl01iOO1i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01iOO1i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01iOO1i_o : STD_LOGIC; + SIGNAL wire_nl01iOO1l_w_lg_o53419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl01iOO1l_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01iOO1l_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl01iOO1l_o : STD_LOGIC; + SIGNAL wire_nl0il0iO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0il0iO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0il0iO_o : STD_LOGIC; + SIGNAL wire_nl0il0ll_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0il0ll_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0il0ll_o : STD_LOGIC; + SIGNAL wire_nl0ili0i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0ili0i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0ili0i_o : STD_LOGIC; + SIGNAL wire_nl0ili0O_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0ili0O_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0ili0O_o : STD_LOGIC; + SIGNAL wire_nl0l0li0l_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0li0l_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0li0l_o : STD_LOGIC; + SIGNAL wire_nl0l0li1i_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0li1i_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0li1i_o : STD_LOGIC; + SIGNAL wire_nl0l0li1O_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0li1O_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0li1O_o : STD_LOGIC; + SIGNAL wire_nl0l0liii_a : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0liii_b : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl0l0liii_o : STD_LOGIC; + SIGNAL wire_nl0l0liO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0l0liO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0l0liO_o : STD_LOGIC; + SIGNAL wire_nl0l0lll_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0l0lll_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0l0lll_o : STD_LOGIC; + SIGNAL wire_nl0l0O0i_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0l0O0i_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0l0O0i_o : STD_LOGIC; + SIGNAL wire_nl0l0O0O_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0l0O0O_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0l0O0O_o : STD_LOGIC; + SIGNAL wire_nl0ll0lli_a : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0ll0lli_b : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0ll0lli_o : STD_LOGIC; + SIGNAL wire_nl0lli1li_a : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0lli1li_b : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0lli1li_o : STD_LOGIC; + SIGNAL wire_nl0lOOi0i_a : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0lOOi0i_b : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0lOOi0i_o : STD_LOGIC; + SIGNAL wire_nl0lOOO0i_a : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0lOOO0i_b : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0lOOO0i_o : STD_LOGIC; + SIGNAL wire_nl0O0iOOl_a : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0O0iOOl_b : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0O0iOOl_o : STD_LOGIC; + SIGNAL wire_nl0O0l0Ol_a : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0O0l0Ol_b : STD_LOGIC_VECTOR (27 DOWNTO 0); + SIGNAL wire_nl0O0l0Ol_o : STD_LOGIC; + SIGNAL wire_nl0Ol10ii_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10ii_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10ii_o : STD_LOGIC; + SIGNAL wire_nl0Ol10il_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10il_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10il_o : STD_LOGIC; + SIGNAL wire_nl0Ol10li_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10li_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10li_o : STD_LOGIC; + SIGNAL wire_nl0Ol10lO_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10lO_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0Ol10lO_o : STD_LOGIC; + SIGNAL wire_nl0Ol1i0i_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i0i_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i0i_o : STD_LOGIC; + SIGNAL wire_nl0Ol1i0l_w_lg_o47754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1i0l_w_lg_w_lg_o47754w47756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1i0l_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i0l_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i0l_o : STD_LOGIC; + SIGNAL wire_nl0Ol1i1i_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i1i_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i1i_o : STD_LOGIC; + SIGNAL wire_nl0Ol1i1l_w_lg_o47755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1i1l_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i1l_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl0Ol1i1l_o : STD_LOGIC; + SIGNAL wire_nl0Ol1iiO_a : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nl0Ol1iiO_b : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nl0Ol1iiO_o : STD_LOGIC; + SIGNAL wire_nl0Ol1ill_a : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nl0Ol1ill_b : STD_LOGIC_VECTOR (19 DOWNTO 0); + SIGNAL wire_nl0Ol1ill_o : STD_LOGIC; + SIGNAL wire_nl0Ol1iOl_a : STD_LOGIC_VECTOR (43 DOWNTO 0); + SIGNAL wire_nl0Ol1iOl_b : STD_LOGIC_VECTOR (43 DOWNTO 0); + SIGNAL wire_nl0Ol1iOl_o : STD_LOGIC; + SIGNAL wire_nl0Ol1l0l_w_lg_o48607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1l0l_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1l0l_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1l0l_o : STD_LOGIC; + SIGNAL wire_nl0Ol1l1i_a : STD_LOGIC_VECTOR (43 DOWNTO 0); + SIGNAL wire_nl0Ol1l1i_b : STD_LOGIC_VECTOR (43 DOWNTO 0); + SIGNAL wire_nl0Ol1l1i_o : STD_LOGIC; + SIGNAL wire_nl0Ol1lil_w_lg_o48604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl0Ol1lil_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1lil_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1lil_o : STD_LOGIC; + SIGNAL wire_nl0Ol1lli_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1lli_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1lli_o : STD_LOGIC; + SIGNAL wire_nl0Ol1lll_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1lll_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl0Ol1lll_o : STD_LOGIC; + SIGNAL wire_nl101i0iO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl101i0iO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl101i0iO_o : STD_LOGIC; + SIGNAL wire_nl101O0OO_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl101O0OO_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl101O0OO_o : STD_LOGIC; + SIGNAL wire_nl101Oi1i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl101Oi1i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl101Oi1i_o : STD_LOGIC; + SIGNAL wire_nl101Oi1O_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl101Oi1O_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl101Oi1O_o : STD_LOGIC; + SIGNAL wire_nl10lOO0l_w_lg_o58909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lOO0l_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10lOO0l_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10lOO0l_o : STD_LOGIC; + SIGNAL wire_nl10lOO1i_w_lg_o58910w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lOO1i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl10lOO1i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl10lOO1i_o : STD_LOGIC; + SIGNAL wire_nl10lOOiO_w_lg_o58802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lOOiO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl10lOOiO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl10lOOiO_o : STD_LOGIC; + SIGNAL wire_nl10lOOOi_w_lg_o58801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10lOOOi_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10lOOOi_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10lOOOi_o : STD_LOGIC; + SIGNAL wire_nl10O110l_w_lg_o58694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10O110l_a : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O110l_b : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl10O110l_o : STD_LOGIC; + SIGNAL wire_nl10O111i_w_lg_o58696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl10O111i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl10O111i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl10O111i_o : STD_LOGIC; + SIGNAL wire_nl111000l_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111000l_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111000l_o : STD_LOGIC; + SIGNAL wire_nl111001i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111001i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111001i_o : STD_LOGIC; + SIGNAL wire_nl111l10i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111l10i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111l10i_o : STD_LOGIC; + SIGNAL wire_nl111l1iO_w_lg_o61436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl111l1iO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111l1iO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111l1iO_o : STD_LOGIC; + SIGNAL wire_nl111O0ll_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl111O0ll_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl111O0ll_o : STD_LOGIC; + SIGNAL wire_nl111Oi1O_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111Oi1O_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl111Oi1O_o : STD_LOGIC; + SIGNAL wire_nl111Oili_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl111Oili_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl111Oili_o : STD_LOGIC; + SIGNAL wire_nl111OlOl_a : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl111OlOl_b : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl111OlOl_o : STD_LOGIC; + SIGNAL wire_nl1i110lO_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i110lO_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i110lO_o : STD_LOGIC; + SIGNAL wire_nl1i11i1O_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11i1O_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11i1O_o : STD_LOGIC; + SIGNAL wire_nl1i11iil_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11iil_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11iil_o : STD_LOGIC; + SIGNAL wire_nl1i11iOi_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11iOi_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11iOi_o : STD_LOGIC; + SIGNAL wire_nl1i11l0O_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11l0O_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11l0O_o : STD_LOGIC; + SIGNAL wire_nl1i11l1O_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11l1O_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1i11l1O_o : STD_LOGIC; + SIGNAL wire_nl1iililO_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iililO_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iililO_o : STD_LOGIC; + SIGNAL wire_nl1iiliOi_w_lg_o56528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1iiliOi_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1iiliOi_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1iiliOi_o : STD_LOGIC; + SIGNAL wire_nl1il001O_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1il001O_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1il001O_o : STD_LOGIC; + SIGNAL wire_nl1il10OO_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1il10OO_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1il10OO_o : STD_LOGIC; + SIGNAL wire_nl1ili00O_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1ili00O_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nl1ili00O_o : STD_LOGIC; + SIGNAL wire_nl1ili0li_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ili0li_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ili0li_o : STD_LOGIC; + SIGNAL wire_nl1ili0Oi_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ili0Oi_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ili0Oi_o : STD_LOGIC; + SIGNAL wire_nl1ilii1i_w_lg_o56077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ilii1i_w_lg_w_lg_o56077w56078w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nl1ilii1i_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ilii1i_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nl1ilii1i_o : STD_LOGIC; + SIGNAL wire_nl1llO1li_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1llO1li_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1llO1li_o : STD_LOGIC; + SIGNAL wire_nl1Ol0lii_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1Ol0lii_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1Ol0lii_o : STD_LOGIC; + SIGNAL wire_nl1OlilOl_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OlilOl_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OlilOl_o : STD_LOGIC; + SIGNAL wire_nl1Olll0l_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1Olll0l_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1Olll0l_o : STD_LOGIC; + SIGNAL wire_nl1OOi11i_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOi11i_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOi11i_o : STD_LOGIC; + SIGNAL wire_nl1OOOiOO_a : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOiOO_b : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1OOOiOO_o : STD_LOGIC; + SIGNAL wire_nli10l0i_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli10l0i_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli10l0i_o : STD_LOGIC; + SIGNAL wire_nli111i1i_a : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_nli111i1i_b : STD_LOGIC_VECTOR (20 DOWNTO 0); + SIGNAL wire_nli111i1i_o : STD_LOGIC; + SIGNAL wire_nli1il0l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli1il0l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli1il0l_o : STD_LOGIC; + SIGNAL wire_nli1il1l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli1il1l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli1il1l_o : STD_LOGIC; + SIGNAL wire_nll0lOl1l_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nll0lOl1l_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nll0lOl1l_o : STD_LOGIC; + SIGNAL wire_nll0O00ll_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nll0O00ll_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nll0O00ll_o : STD_LOGIC; + SIGNAL wire_nll0O0i1i_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nll0O0i1i_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nll0O0i1i_o : STD_LOGIC; + SIGNAL wire_nll0O1il_a : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nll0O1il_b : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_nll0O1il_o : STD_LOGIC; + SIGNAL wire_nlliOlOOl_a : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlliOlOOl_b : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlliOlOOl_o : STD_LOGIC; + SIGNAL wire_nlll0lOii_a : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0lOii_b : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlll0lOii_o : STD_LOGIC; + SIGNAL wire_nllliOiO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllliOiO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nllliOiO_o : STD_LOGIC; + SIGNAL wire_nlllO1iO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1iO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1iO_o : STD_LOGIC; + SIGNAL wire_nlllO1lO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1lO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlllO1lO_o : STD_LOGIC; + SIGNAL wire_nlOi1O0ll_a : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlOi1O0ll_b : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nlOi1O0ll_o : STD_LOGIC; + SIGNAL wire_nlOil0iOi_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOil0iOi_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOil0iOi_o : STD_LOGIC; + SIGNAL wire_nlOillllO_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOillllO_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOillllO_o : STD_LOGIC; + SIGNAL wire_nlOl1ll1l_a : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOl1ll1l_b : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOl1ll1l_o : STD_LOGIC; + SIGNAL wire_nl00l110i_data : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL wire_nl00l110i_o : STD_LOGIC; + SIGNAL wire_nl00l110i_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl00l111O_data : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL wire_nl00l111O_o : STD_LOGIC; + SIGNAL wire_nl00l111O_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl0l01OOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl0l01OOi_o : STD_LOGIC; + SIGNAL wire_nl0l01OOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliiO1l1i_w_lg_o44431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nliiO1l1i_data : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL wire_nliiO1l1i_o : STD_LOGIC; + SIGNAL wire_nliiO1l1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nliliOiil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nliliOiil_o : STD_LOGIC; + SIGNAL wire_nliliOiil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliliOlll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nliliOlll_o : STD_LOGIC; + SIGNAL wire_nliliOlll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nliliOO0O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nliliOO0O_o : STD_LOGIC; + SIGNAL wire_nliliOO0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill100O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlill100O_o : STD_LOGIC; + SIGNAL wire_nlill100O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill111i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlill111i_o : STD_LOGIC; + SIGNAL wire_nlill111i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill11ll_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlill11ll_o : STD_LOGIC; + SIGNAL wire_nlill11ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill1i1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlill1i1i_o : STD_LOGIC; + SIGNAL wire_nlill1i1i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill1ilO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlill1ilO_o : STD_LOGIC; + SIGNAL wire_nlill1ilO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlill1l0i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlill1l0i_o : STD_LOGIC; + SIGNAL wire_nlill1l0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlillllOO_w_lg_o42294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlillllOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlillllOO_o : STD_LOGIC; + SIGNAL wire_nlillllOO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilllOiO_w_lg_o42807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlilllOiO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlilllOiO_o : STD_LOGIC; + SIGNAL wire_nlilllOiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0OO0li_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0li_o : STD_LOGIC; + SIGNAL wire_n0OO0li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0ll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0ll_o : STD_LOGIC; + SIGNAL wire_n0OO0ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0lO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0lO_o : STD_LOGIC; + SIGNAL wire_n0OO0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0Oi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0Oi_o : STD_LOGIC; + SIGNAL wire_n0OO0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0Ol_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0Ol_o : STD_LOGIC; + SIGNAL wire_n0OO0Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0OO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO0OO_o : STD_LOGIC; + SIGNAL wire_n0OO0OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OO1Oi_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0OO1Oi_o : STD_LOGIC; + SIGNAL wire_n0OO1Oi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_n0OO1Ol_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n0OO1Ol_o : STD_LOGIC; + SIGNAL wire_n0OO1Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n101011i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n101011i_o : STD_LOGIC; + SIGNAL wire_n101011i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n101011l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n101011l_o : STD_LOGIC; + SIGNAL wire_n101011l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n101100O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n101100O_o : STD_LOGIC; + SIGNAL wire_n101100O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n101101i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n101101i_o : STD_LOGIC; + SIGNAL wire_n101101i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n101101l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n101101l_o : STD_LOGIC; + SIGNAL wire_n101101l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n10110ii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10110ii_o : STD_LOGIC; + SIGNAL wire_n10110ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10110iO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n10110iO_o : STD_LOGIC; + SIGNAL wire_n10110iO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n10110lO_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n10110lO_o : STD_LOGIC; + SIGNAL wire_n10110lO_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n10110Oi_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n10110Oi_o : STD_LOGIC; + SIGNAL wire_n10110Oi_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n10110Ol_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n10110Ol_o : STD_LOGIC; + SIGNAL wire_n10110Ol_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n10110OO_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n10110OO_o : STD_LOGIC; + SIGNAL wire_n10110OO_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n101110O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n101110O_o : STD_LOGIC; + SIGNAL wire_n101110O_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n101111l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n101111l_o : STD_LOGIC; + SIGNAL wire_n101111l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10111li_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10111li_o : STD_LOGIC; + SIGNAL wire_n10111li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10111lO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10111lO_o : STD_LOGIC; + SIGNAL wire_n10111lO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n10111Ol_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10111Ol_o : STD_LOGIC; + SIGNAL wire_n10111Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n10111OO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n10111OO_o : STD_LOGIC; + SIGNAL wire_n10111OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1011i0i_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i0i_o : STD_LOGIC; + SIGNAL wire_n1011i0i_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i0l_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i0l_o : STD_LOGIC; + SIGNAL wire_n1011i0l_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i0O_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i0O_o : STD_LOGIC; + SIGNAL wire_n1011i0O_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i1i_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i1i_o : STD_LOGIC; + SIGNAL wire_n1011i1i_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i1l_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i1l_o : STD_LOGIC; + SIGNAL wire_n1011i1l_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i1O_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011i1O_o : STD_LOGIC; + SIGNAL wire_n1011i1O_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iii_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iii_o : STD_LOGIC; + SIGNAL wire_n1011iii_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iil_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iil_o : STD_LOGIC; + SIGNAL wire_n1011iil_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iiO_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iiO_o : STD_LOGIC; + SIGNAL wire_n1011iiO_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011ili_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011ili_o : STD_LOGIC; + SIGNAL wire_n1011ili_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011ill_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011ill_o : STD_LOGIC; + SIGNAL wire_n1011ill_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011ilO_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011ilO_o : STD_LOGIC; + SIGNAL wire_n1011ilO_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iOi_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iOi_o : STD_LOGIC; + SIGNAL wire_n1011iOi_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iOl_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iOl_o : STD_LOGIC; + SIGNAL wire_n1011iOl_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iOO_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011iOO_o : STD_LOGIC; + SIGNAL wire_n1011iOO_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l0i_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l0i_o : STD_LOGIC; + SIGNAL wire_n1011l0i_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l0l_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l0l_o : STD_LOGIC; + SIGNAL wire_n1011l0l_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l0O_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l0O_o : STD_LOGIC; + SIGNAL wire_n1011l0O_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l1i_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l1i_o : STD_LOGIC; + SIGNAL wire_n1011l1i_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l1l_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l1l_o : STD_LOGIC; + SIGNAL wire_n1011l1l_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l1O_data : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011l1O_o : STD_LOGIC; + SIGNAL wire_n1011l1O_sel : STD_LOGIC_VECTOR (24 DOWNTO 0); + SIGNAL wire_n1011lii_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1011lii_o : STD_LOGIC; + SIGNAL wire_n1011lii_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1011liO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011liO_o : STD_LOGIC; + SIGNAL wire_n1011liO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011lli_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011lli_o : STD_LOGIC; + SIGNAL wire_n1011lli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011llO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1011llO_o : STD_LOGIC; + SIGNAL wire_n1011llO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1011lOl_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1011lOl_o : STD_LOGIC; + SIGNAL wire_n1011lOl_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1011O0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011O0i_o : STD_LOGIC; + SIGNAL wire_n1011O0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011O0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011O0l_o : STD_LOGIC; + SIGNAL wire_n1011O0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011O1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011O1l_o : STD_LOGIC; + SIGNAL wire_n1011O1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011O1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011O1O_o : STD_LOGIC; + SIGNAL wire_n1011O1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011Oii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011Oii_o : STD_LOGIC; + SIGNAL wire_n1011Oii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011OiO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011OiO_o : STD_LOGIC; + SIGNAL wire_n1011OiO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011Oli_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1011Oli_o : STD_LOGIC; + SIGNAL wire_n1011Oli_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1011OlO_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1011OlO_o : STD_LOGIC; + SIGNAL wire_n1011OlO_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1011OOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1011OOl_o : STD_LOGIC; + SIGNAL wire_n1011OOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOO0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n11OOO0l_o : STD_LOGIC; + SIGNAL wire_n11OOO0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n11OOOii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOii_o : STD_LOGIC; + SIGNAL wire_n11OOOii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOil_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOil_o : STD_LOGIC; + SIGNAL wire_n11OOOil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOli_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOli_o : STD_LOGIC; + SIGNAL wire_n11OOOli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOll_o : STD_LOGIC; + SIGNAL wire_n11OOOll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n11OOOOi_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n11OOOOi_o : STD_LOGIC; + SIGNAL wire_n11OOOOi_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n11OOOOO_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n11OOOOO_o : STD_LOGIC; + SIGNAL wire_n11OOOOO_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_n1l0Oli_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l0Oli_o : STD_LOGIC; + SIGNAL wire_n1l0Oli_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1l0OOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1l0OOi_o : STD_LOGIC; + SIGNAL wire_n1l0OOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1l0OOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1l0OOl_o : STD_LOGIC; + SIGNAL wire_n1l0OOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1l0OOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1l0OOO_o : STD_LOGIC; + SIGNAL wire_n1l0OOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1li11i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1li11i_o : STD_LOGIC; + SIGNAL wire_n1li11i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1liO0il_data : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_n1liO0il_o : STD_LOGIC; + SIGNAL wire_n1liO0il_sel : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL wire_n1liO0ll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1liO0ll_o : STD_LOGIC; + SIGNAL wire_n1liO0ll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1liO0lO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1liO0lO_o : STD_LOGIC; + SIGNAL wire_n1liO0lO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1liOiil_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1liOiil_o : STD_LOGIC; + SIGNAL wire_n1liOiil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_n1liOili_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOili_o : STD_LOGIC; + SIGNAL wire_n1liOili_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOill_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOill_o : STD_LOGIC; + SIGNAL wire_n1liOill_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOilO_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOilO_o : STD_LOGIC; + SIGNAL wire_n1liOilO_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOiOi_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOiOi_o : STD_LOGIC; + SIGNAL wire_n1liOiOi_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOiOl_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOiOl_o : STD_LOGIC; + SIGNAL wire_n1liOiOl_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOiOO_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOiOO_o : STD_LOGIC; + SIGNAL wire_n1liOiOO_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOl0i_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOl0i_o : STD_LOGIC; + SIGNAL wire_n1liOl0i_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOl0l_data : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_n1liOl0l_o : STD_LOGIC; + SIGNAL wire_n1liOl0l_sel : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_n1liOl0O_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOl0O_o : STD_LOGIC; + SIGNAL wire_n1liOl0O_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOl1O_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOl1O_o : STD_LOGIC; + SIGNAL wire_n1liOl1O_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOlii_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOlii_o : STD_LOGIC; + SIGNAL wire_n1liOlii_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOlil_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOlil_o : STD_LOGIC; + SIGNAL wire_n1liOlil_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOliO_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOliO_o : STD_LOGIC; + SIGNAL wire_n1liOliO_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_n1liOlll_data : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_n1liOlll_o : STD_LOGIC; + SIGNAL wire_n1liOlll_sel : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_n1lOiO0O_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiO0O_o : STD_LOGIC; + SIGNAL wire_n1lOiO0O_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiOil_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiOil_o : STD_LOGIC; + SIGNAL wire_n1lOiOil_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiOli_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiOli_o : STD_LOGIC; + SIGNAL wire_n1lOiOli_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiOlO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiOlO_o : STD_LOGIC; + SIGNAL wire_n1lOiOlO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOiOOi_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lOiOOi_o : STD_LOGIC; + SIGNAL wire_n1lOiOOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lOiOOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lOiOOl_o : STD_LOGIC; + SIGNAL wire_n1lOiOOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_n1lOl11i_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOl11i_o : STD_LOGIC; + SIGNAL wire_n1lOl11i_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_n1lOl11O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_n1lOl11O_o : STD_LOGIC; + SIGNAL wire_n1lOl11O_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_ni1O0iO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1O0iO_o : STD_LOGIC; + SIGNAL wire_ni1O0iO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_ni1O0lO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1O0lO_o : STD_LOGIC; + SIGNAL wire_ni1O0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1O0Oi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1O0Oi_o : STD_LOGIC; + SIGNAL wire_ni1O0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1O0Ol_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1O0Ol_o : STD_LOGIC; + SIGNAL wire_ni1O0Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1O0OO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_ni1O0OO_o : STD_LOGIC; + SIGNAL wire_ni1O0OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1011ilO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1011ilO_o : STD_LOGIC; + SIGNAL wire_nl1011ilO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1011iOl_data : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1011iOl_o : STD_LOGIC; + SIGNAL wire_nl1011iOl_sel : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1011iOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1011iOO_o : STD_LOGIC; + SIGNAL wire_nl1011iOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1011l0i_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011l0i_o : STD_LOGIC; + SIGNAL wire_nl1011l0i_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011l0l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1011l0l_o : STD_LOGIC; + SIGNAL wire_nl1011l0l_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1011l0O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1011l0O_o : STD_LOGIC; + SIGNAL wire_nl1011l0O_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1011l1l_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1011l1l_o : STD_LOGIC; + SIGNAL wire_nl1011l1l_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1011lil_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1011lil_o : STD_LOGIC; + SIGNAL wire_nl1011lil_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1011lli_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011lli_o : STD_LOGIC; + SIGNAL wire_nl1011lli_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011lll_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011lll_o : STD_LOGIC; + SIGNAL wire_nl1011lll_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011llO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011llO_o : STD_LOGIC; + SIGNAL wire_nl1011llO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1011lOl_data : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl1011lOl_o : STD_LOGIC; + SIGNAL wire_nl1011lOl_sel : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_nl10OOl_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl10OOl_o : STD_LOGIC; + SIGNAL wire_nl10OOl_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl10OOO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl10OOO_o : STD_LOGIC; + SIGNAL wire_nl10OOO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i00i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i00i_o : STD_LOGIC; + SIGNAL wire_nl1i00i_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i00l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i00l_o : STD_LOGIC; + SIGNAL wire_nl1i00l_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i00O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i00O_o : STD_LOGIC; + SIGNAL wire_nl1i00O_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i01i_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i01i_o : STD_LOGIC; + SIGNAL wire_nl1i01i_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i01l_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i01l_o : STD_LOGIC; + SIGNAL wire_nl1i01l_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i01O_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i01O_o : STD_LOGIC; + SIGNAL wire_nl1i01O_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0ii_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0ii_o : STD_LOGIC; + SIGNAL wire_nl1i0ii_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0il_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0il_o : STD_LOGIC; + SIGNAL wire_nl1i0il_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0iO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0iO_o : STD_LOGIC; + SIGNAL wire_nl1i0iO_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0li_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0li_o : STD_LOGIC; + SIGNAL wire_nl1i0li_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0ll_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0ll_o : STD_LOGIC; + SIGNAL wire_nl1i0ll_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i0lO_data : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nl1i0lO_o : STD_LOGIC; + SIGNAL wire_nl1i0lO_sel : STD_LOGIC_VECTOR (14 DOWNTO 0); + SIGNAL wire_nl1i0Ol_data : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl1i0Ol_o : STD_LOGIC; + SIGNAL wire_nl1i0Ol_sel : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl1i0OO_data : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl1i0OO_o : STD_LOGIC; + SIGNAL wire_nl1i0OO_sel : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl1i10i_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i10i_o : STD_LOGIC; + SIGNAL wire_nl1i10i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i10l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i10l_o : STD_LOGIC; + SIGNAL wire_nl1i10l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i10O_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i10O_o : STD_LOGIC; + SIGNAL wire_nl1i10O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i11i_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i11i_o : STD_LOGIC; + SIGNAL wire_nl1i11i_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i11l_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i11l_o : STD_LOGIC; + SIGNAL wire_nl1i11l_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i11O_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i11O_o : STD_LOGIC; + SIGNAL wire_nl1i11O_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1ii_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1ii_o : STD_LOGIC; + SIGNAL wire_nl1i1ii_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1il_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1il_o : STD_LOGIC; + SIGNAL wire_nl1i1il_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1iO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1iO_o : STD_LOGIC; + SIGNAL wire_nl1i1iO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1li_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1li_o : STD_LOGIC; + SIGNAL wire_nl1i1li_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1ll_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1ll_o : STD_LOGIC; + SIGNAL wire_nl1i1ll_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1lO_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1lO_o : STD_LOGIC; + SIGNAL wire_nl1i1lO_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1Oi_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1Oi_o : STD_LOGIC; + SIGNAL wire_nl1i1Oi_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1Ol_data : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1Ol_o : STD_LOGIC; + SIGNAL wire_nl1i1Ol_sel : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl1i1OO_data : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1i1OO_o : STD_LOGIC; + SIGNAL wire_nl1i1OO_sel : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL wire_nl1ii0i_data : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii0i_o : STD_LOGIC; + SIGNAL wire_nl1ii0i_sel : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii0l_data : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii0l_o : STD_LOGIC; + SIGNAL wire_nl1ii0l_sel : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii0O_data : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii0O_o : STD_LOGIC; + SIGNAL wire_nl1ii0O_sel : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii1i_data : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl1ii1i_o : STD_LOGIC; + SIGNAL wire_nl1ii1i_sel : STD_LOGIC_VECTOR (13 DOWNTO 0); + SIGNAL wire_nl1ii1O_data : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii1O_o : STD_LOGIC; + SIGNAL wire_nl1ii1O_sel : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1iiil_data : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiil_o : STD_LOGIC; + SIGNAL wire_nl1iiil_sel : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiiO_data : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiiO_o : STD_LOGIC; + SIGNAL wire_nl1iiiO_sel : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iili_data : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iili_o : STD_LOGIC; + SIGNAL wire_nl1iili_sel : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iill_data : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iill_o : STD_LOGIC; + SIGNAL wire_nl1iill_sel : STD_LOGIC_VECTOR (10 DOWNTO 0); + SIGNAL wire_nl1iiOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1iiOi_o : STD_LOGIC; + SIGNAL wire_nl1iiOi_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1iiOl_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1iiOl_o : STD_LOGIC; + SIGNAL wire_nl1iiOl_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1iiOO_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1iiOO_o : STD_LOGIC; + SIGNAL wire_nl1iiOO_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il0i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il0i_o : STD_LOGIC; + SIGNAL wire_nl1il0i_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il0l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il0l_o : STD_LOGIC; + SIGNAL wire_nl1il0l_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il1i_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il1i_o : STD_LOGIC; + SIGNAL wire_nl1il1i_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il1l_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il1l_o : STD_LOGIC; + SIGNAL wire_nl1il1l_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il1O_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1il1O_o : STD_LOGIC; + SIGNAL wire_nl1il1O_sel : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nl1lliiOO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1lliiOO_o : STD_LOGIC; + SIGNAL wire_nl1lliiOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil0i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil0i_o : STD_LOGIC; + SIGNAL wire_nl1llil0i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil0l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil0l_o : STD_LOGIC; + SIGNAL wire_nl1llil0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llil0O_o : STD_LOGIC; + SIGNAL wire_nl1llil0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llil1i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil1i_o : STD_LOGIC; + SIGNAL wire_nl1llil1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil1l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil1l_o : STD_LOGIC; + SIGNAL wire_nl1llil1l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil1O_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llil1O_o : STD_LOGIC; + SIGNAL wire_nl1llil1O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1llilii_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilii_o : STD_LOGIC; + SIGNAL wire_nl1llilii_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilil_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilil_o : STD_LOGIC; + SIGNAL wire_nl1llilil_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lliliO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lliliO_o : STD_LOGIC; + SIGNAL wire_nl1lliliO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilli_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilli_o : STD_LOGIC; + SIGNAL wire_nl1llilli_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilll_o : STD_LOGIC; + SIGNAL wire_nl1llilll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llillO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llillO_o : STD_LOGIC; + SIGNAL wire_nl1llillO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilOi_o : STD_LOGIC; + SIGNAL wire_nl1llilOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilOl_o : STD_LOGIC; + SIGNAL wire_nl1llilOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1llilOO_o : STD_LOGIC; + SIGNAL wire_nl1llilOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lliO0l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1lliO0l_o : STD_LOGIC; + SIGNAL wire_nl1lliO0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1lliO1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lliO1i_o : STD_LOGIC; + SIGNAL wire_nl1lliO1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl1lliO1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1lliO1O_o : STD_LOGIC; + SIGNAL wire_nl1lliO1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1OiOi1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1OiOi1O_o : STD_LOGIC; + SIGNAL wire_nl1OiOi1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nl1OiOiii_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOiii_o : STD_LOGIC; + SIGNAL wire_nl1OiOiii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOiil_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOiil_o : STD_LOGIC; + SIGNAL wire_nl1OiOiil_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOili_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOili_o : STD_LOGIC; + SIGNAL wire_nl1OiOili_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOill_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOill_o : STD_LOGIC; + SIGNAL wire_nl1OiOill_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOilO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOilO_o : STD_LOGIC; + SIGNAL wire_nl1OiOilO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOiOi_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1OiOiOi_o : STD_LOGIC; + SIGNAL wire_nl1OiOiOi_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1OiOiOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOiOl_o : STD_LOGIC; + SIGNAL wire_nl1OiOiOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1OiOiOO_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nl1OiOiOO_o : STD_LOGIC; + SIGNAL wire_nl1OiOiOO_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nli11iOll_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli11iOll_o : STD_LOGIC; + SIGNAL wire_nli11iOll_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli11iOlO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nli11iOlO_o : STD_LOGIC; + SIGNAL wire_nli11iOlO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlil00lOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil00lOl_o : STD_LOGIC; + SIGNAL wire_nlil00lOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil00O0i_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00O0i_o : STD_LOGIC; + SIGNAL wire_nlil00O0i_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00O0l_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00O0l_o : STD_LOGIC; + SIGNAL wire_nlil00O0l_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00O0O_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00O0O_o : STD_LOGIC; + SIGNAL wire_nlil00O0O_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00O1i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil00O1i_o : STD_LOGIC; + SIGNAL wire_nlil00O1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlil00O1O_data : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlil00O1O_o : STD_LOGIC; + SIGNAL wire_nlil00O1O_sel : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlil00Oii_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00Oii_o : STD_LOGIC; + SIGNAL wire_nlil00Oii_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00Oil_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00Oil_o : STD_LOGIC; + SIGNAL wire_nlil00Oil_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OiO_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OiO_o : STD_LOGIC; + SIGNAL wire_nlil00OiO_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00Oli_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00Oli_o : STD_LOGIC; + SIGNAL wire_nlil00Oli_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00Oll_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00Oll_o : STD_LOGIC; + SIGNAL wire_nlil00Oll_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OlO_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OlO_o : STD_LOGIC; + SIGNAL wire_nlil00OlO_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OOi_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OOi_o : STD_LOGIC; + SIGNAL wire_nlil00OOi_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OOl_data : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlil00OOl_o : STD_LOGIC; + SIGNAL wire_nlil00OOl_sel : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nlil00OOO_data : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlil00OOO_o : STD_LOGIC; + SIGNAL wire_nlil00OOO_sel : STD_LOGIC_VECTOR (11 DOWNTO 0); + SIGNAL wire_nlilO1i0i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1i0i_o : STD_LOGIC; + SIGNAL wire_nlilO1i0i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1i0l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1i0l_o : STD_LOGIC; + SIGNAL wire_nlilO1i0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1i1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlilO1i1l_o : STD_LOGIC; + SIGNAL wire_nlilO1i1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlilO1iii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilO1iii_o : STD_LOGIC; + SIGNAL wire_nlilO1iii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilO1iil_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilO1iil_o : STD_LOGIC; + SIGNAL wire_nlilO1iil_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilO1ill_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1ill_o : STD_LOGIC; + SIGNAL wire_nlilO1ill_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1ilO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1ilO_o : STD_LOGIC; + SIGNAL wire_nlilO1ilO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1iOi_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1iOi_o : STD_LOGIC; + SIGNAL wire_nlilO1iOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1iOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1iOl_o : STD_LOGIC; + SIGNAL wire_nlilO1iOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1iOO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1iOO_o : STD_LOGIC; + SIGNAL wire_nlilO1iOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l0i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l0i_o : STD_LOGIC; + SIGNAL wire_nlilO1l0i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l0l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l0l_o : STD_LOGIC; + SIGNAL wire_nlilO1l0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l0O_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l0O_o : STD_LOGIC; + SIGNAL wire_nlilO1l0O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l1i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l1i_o : STD_LOGIC; + SIGNAL wire_nlilO1l1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l1l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l1l_o : STD_LOGIC; + SIGNAL wire_nlilO1l1l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l1O_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1l1O_o : STD_LOGIC; + SIGNAL wire_nlilO1l1O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lii_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lii_o : STD_LOGIC; + SIGNAL wire_nlilO1lii_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lil_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lil_o : STD_LOGIC; + SIGNAL wire_nlilO1lil_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1liO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1liO_o : STD_LOGIC; + SIGNAL wire_nlilO1liO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lli_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lli_o : STD_LOGIC; + SIGNAL wire_nlilO1lli_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lll_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lll_o : STD_LOGIC; + SIGNAL wire_nlilO1lll_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1llO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1llO_o : STD_LOGIC; + SIGNAL wire_nlilO1llO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lOi_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lOi_o : STD_LOGIC; + SIGNAL wire_nlilO1lOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lOl_o : STD_LOGIC; + SIGNAL wire_nlilO1lOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lOO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1lOO_o : STD_LOGIC; + SIGNAL wire_nlilO1lOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1O0i_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1O0i_o : STD_LOGIC; + SIGNAL wire_nlilO1O0i_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1O0l_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1O0l_o : STD_LOGIC; + SIGNAL wire_nlilO1O0l_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1O0O_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1O0O_o : STD_LOGIC; + SIGNAL wire_nlilO1O0O_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1O1i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1O1i_o : STD_LOGIC; + SIGNAL wire_nlilO1O1i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlilO1O1O_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1O1O_o : STD_LOGIC; + SIGNAL wire_nlilO1O1O_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1Oii_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1Oii_o : STD_LOGIC; + SIGNAL wire_nlilO1Oii_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1Oil_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1Oil_o : STD_LOGIC; + SIGNAL wire_nlilO1Oil_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1OiO_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1OiO_o : STD_LOGIC; + SIGNAL wire_nlilO1OiO_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlilO1Oli_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1Oli_o : STD_LOGIC; + SIGNAL wire_nlilO1Oli_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1Oll_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilO1Oll_o : STD_LOGIC; + SIGNAL wire_nlilO1Oll_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlilOOi0i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOi0i_o : STD_LOGIC; + SIGNAL wire_nlilOOi0i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOi0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOi0l_o : STD_LOGIC; + SIGNAL wire_nlilOOi0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOi0O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOi0O_o : STD_LOGIC; + SIGNAL wire_nlilOOi0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOi1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOi1O_o : STD_LOGIC; + SIGNAL wire_nlilOOi1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOiii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlilOOiii_o : STD_LOGIC; + SIGNAL wire_nlilOOiii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlli10li_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10li_o : STD_LOGIC; + SIGNAL wire_nlli10li_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10ll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10ll_o : STD_LOGIC; + SIGNAL wire_nlli10ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10lO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10lO_o : STD_LOGIC; + SIGNAL wire_nlli10lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10Oi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10Oi_o : STD_LOGIC; + SIGNAL wire_nlli10Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10Ol_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10Ol_o : STD_LOGIC; + SIGNAL wire_nlli10Ol_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10OO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli10OO_o : STD_LOGIC; + SIGNAL wire_nlli10OO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i0i_o : STD_LOGIC; + SIGNAL wire_nlli1i0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i0l_o : STD_LOGIC; + SIGNAL wire_nlli1i0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i0O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i0O_o : STD_LOGIC; + SIGNAL wire_nlli1i0O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i1i_o : STD_LOGIC; + SIGNAL wire_nlli1i1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i1l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i1l_o : STD_LOGIC; + SIGNAL wire_nlli1i1l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1i1O_o : STD_LOGIC; + SIGNAL wire_nlli1i1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlli1iii_o : STD_LOGIC; + SIGNAL wire_nlli1iii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlli1iiO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iiO_o : STD_LOGIC; + SIGNAL wire_nlli1iiO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1ili_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1ili_o : STD_LOGIC; + SIGNAL wire_nlli1ili_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1ill_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1ill_o : STD_LOGIC; + SIGNAL wire_nlli1ill_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1ilO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1ilO_o : STD_LOGIC; + SIGNAL wire_nlli1ilO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iOi_o : STD_LOGIC; + SIGNAL wire_nlli1iOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iOl_o : STD_LOGIC; + SIGNAL wire_nlli1iOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1iOO_o : STD_LOGIC; + SIGNAL wire_nlli1iOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1l1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlli1l1i_o : STD_LOGIC; + SIGNAL wire_nlli1l1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll101l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll101l_o : STD_LOGIC; + SIGNAL wire_nlll101l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll11OO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll11OO_o : STD_LOGIC; + SIGNAL wire_nlll11OO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1iO0l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iO0l_o : STD_LOGIC; + SIGNAL wire_nlll1iO0l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iO0O_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iO0O_o : STD_LOGIC; + SIGNAL wire_nlll1iO0O_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iO1O_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iO1O_o : STD_LOGIC; + SIGNAL wire_nlll1iO1O_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iOi_o : STD_LOGIC; + SIGNAL wire_nlll1iOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iOii_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlll1iOii_o : STD_LOGIC; + SIGNAL wire_nlll1iOii_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlll1iOiO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iOiO_o : STD_LOGIC; + SIGNAL wire_nlll1iOiO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iOl_o : STD_LOGIC; + SIGNAL wire_nlll1iOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iOli_data : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlll1iOli_o : STD_LOGIC; + SIGNAL wire_nlll1iOli_sel : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_nlll1iOlO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iOlO_o : STD_LOGIC; + SIGNAL wire_nlll1iOlO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlll1iOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iOO_o : STD_LOGIC; + SIGNAL wire_nlll1iOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1iOOl_data : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlll1iOOl_o : STD_LOGIC; + SIGNAL wire_nlll1iOOl_sel : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nlll1l0i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1l0i_o : STD_LOGIC; + SIGNAL wire_nlll1l0i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1l0l_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1l0l_o : STD_LOGIC; + SIGNAL wire_nlll1l0l_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1l1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1l1i_o : STD_LOGIC; + SIGNAL wire_nlll1l1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll1l1l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1l1l_o : STD_LOGIC; + SIGNAL wire_nlll1l1l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1OOlO_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1OOlO_o : STD_LOGIC; + SIGNAL wire_nlll1OOlO_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1OOOi_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1OOOi_o : STD_LOGIC; + SIGNAL wire_nlll1OOOi_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1OOOl_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlll1OOOl_o : STD_LOGIC; + SIGNAL wire_nlll1OOOl_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00O0li_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00O0li_o : STD_LOGIC; + SIGNAL wire_nlO00O0li_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00O0ll_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00O0ll_o : STD_LOGIC; + SIGNAL wire_nlO00O0ll_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00O0lO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00O0lO_o : STD_LOGIC; + SIGNAL wire_nlO00O0lO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00O0Oi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00O0Oi_o : STD_LOGIC; + SIGNAL wire_nlO00O0Oi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00O0Ol_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00O0Ol_o : STD_LOGIC; + SIGNAL wire_nlO00O0Ol_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Oi0l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Oi0l_o : STD_LOGIC; + SIGNAL wire_nlO00Oi0l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Oi0O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Oi0O_o : STD_LOGIC; + SIGNAL wire_nlO00Oi0O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Oi1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00Oi1i_o : STD_LOGIC; + SIGNAL wire_nlO00Oi1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlO00Oi1O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO00Oi1O_o : STD_LOGIC; + SIGNAL wire_nlO00Oi1O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O10i_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O10i_o : STD_LOGIC; + SIGNAL wire_nlO0O10i_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O10l_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O10l_o : STD_LOGIC; + SIGNAL wire_nlO0O10l_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O10O_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O10O_o : STD_LOGIC; + SIGNAL wire_nlO0O10O_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O1ii_data : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlO0O1ii_o : STD_LOGIC; + SIGNAL wire_nlO0O1ii_sel : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_nlOll0OOi_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOll0OOi_o : STD_LOGIC; + SIGNAL wire_nlOll0OOi_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOll0OOl_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOll0OOl_o : STD_LOGIC; + SIGNAL wire_nlOll0OOl_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOll0OOO_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOll0OOO_o : STD_LOGIC; + SIGNAL wire_nlOll0OOO_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOlli11i_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOlli11i_o : STD_LOGIC; + SIGNAL wire_nlOlli11i_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOlli11l_data : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOlli11l_o : STD_LOGIC; + SIGNAL wire_nlOlli11l_sel : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlOllllOi_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOllllOi_o : STD_LOGIC; + SIGNAL wire_nlOllllOi_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOllllOl_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOllllOl_o : STD_LOGIC; + SIGNAL wire_nlOllllOl_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOllllOO_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOllllOO_o : STD_LOGIC; + SIGNAL wire_nlOllllOO_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOlllO1i_data : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOlllO1i_o : STD_LOGIC; + SIGNAL wire_nlOlllO1i_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOO0O_w_lg_w_q_range2464w2565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0OOO0O_data : STD_LOGIC_VECTOR (132 DOWNTO 0); + SIGNAL wire_n0OOO0O_q : STD_LOGIC_VECTOR (132 DOWNTO 0); + SIGNAL wire_n0OOO0O_rdaddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOO0O_wraddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n0OOO0O_w_q_range2445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0OOO0O_w_q_range2448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n0OOO0O_w_q_range2464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_n1llO0O_data : STD_LOGIC_VECTOR (157 DOWNTO 0); + SIGNAL wire_n1llO0O_q : STD_LOGIC_VECTOR (157 DOWNTO 0); + SIGNAL wire_n1llO0O_rdaddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_n1llO0O_wraddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nl01iilO_data : STD_LOGIC_VECTOR (53 DOWNTO 0); + SIGNAL wire_nl01iilO_q : STD_LOGIC_VECTOR (53 DOWNTO 0); + SIGNAL wire_nl01iilO_rdaddress : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nl01iilO_wraddress : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_nli110ii_data : STD_LOGIC_VECTOR (157 DOWNTO 0); + SIGNAL wire_nli110ii_q : STD_LOGIC_VECTOR (157 DOWNTO 0); + SIGNAL wire_nli110ii_rdaddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nli110ii_wraddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll0lli_w_lg_w_q_range4070w4398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_lg_w_q_range4231w4450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_lg_w_q_range4359w4397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_lg_w_q_range4229w4449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_lg_w_q_range4087w4304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_lg_w_lg_w_q_range4070w4398w4399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_data : STD_LOGIC_VECTOR (132 DOWNTO 0); + SIGNAL wire_nlll0lli_q : STD_LOGIC_VECTOR (132 DOWNTO 0); + SIGNAL wire_nlll0lli_rdaddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll0lli_wraddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlll0lli_w_q_range4067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_q_range4070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_q_range4359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_q_range4231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_q_range4229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlll0lli_w_q_range4087w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_nlOil11li_data : STD_LOGIC_VECTOR (75 DOWNTO 0); + SIGNAL wire_nlOil11li_q : STD_LOGIC_VECTOR (75 DOWNTO 0); + SIGNAL wire_nlOil11li_rdaddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOil11li_wraddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOili0li_data : STD_LOGIC_VECTOR (73 DOWNTO 0); + SIGNAL wire_nlOili0li_q : STD_LOGIC_VECTOR (73 DOWNTO 0); + SIGNAL wire_nlOili0li_rdaddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlOili0li_wraddress : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL wire_nlliO0lOi_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlliO0lOi_q : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_nlliO0lOi_rdaddress : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nlliO0lOi_wraddress : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_nl1ii10OO_data : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii10OO_q : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL wire_nl1ii10OO_rdaddress : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_nl1ii10OO_wraddress : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w20922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w4020w4021w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2402w2403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOl0l01i20919w20920w20921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOl0l1OO20911w20912w20913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOi0010l53612w53627w53629w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOiOilil35819w35821w35822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOiOilli35807w35809w35810w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOiOiO0l35813w35815w35816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOiOiOii35801w35803w35804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlii0iO18300w18304w18305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOliliil17393w17397w17398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOliOlii16486w16490w16491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOll1O0O15579w15583w15584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlli10l14672w14676w14677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlll00i13765w13769w13770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOllOi1O12858w12862w12863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlO1l1l11947w11951w11952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOO10l1i20908w21151w21152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOO10lOO8902w23242w23243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_k_hip_range2413w2429w5669w5670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w4018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w4020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w2402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi011ii54835w54836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1i10O59849w59850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOii1OOl52070w52071w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOii1OOl52076w52077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiiO0Ol47768w47769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiO1lii42830w42831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOi10l36263w36264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0l01i20919w20920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0l1OO20911w20912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_tx_valid_vc04031w4033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_tx_valid_vc12414w2416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_conf_range29168w29169w29170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range55029w55032w55033w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_hip_range2413w5661w5662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_hip_range2413w3330w3332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_hip_range2413w5220w5224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_hip_range2413w5663w5667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi0010l53612w53627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi001iO53573w53578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi001iO53573w53579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi0lOOi53212w53213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1i1Ol60233w60234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1OllO54888w56529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOii1liO52084w52085w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiiO0il47745w47748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiiO0Ol47734w47764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiiO0Ol47734w47747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiiO0Ol47734w47736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOilllOl44309w44310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOilllOl44309w45114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOilOO1i43375w43401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOilOO1i43375w43962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOilil35819w35821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOilli35807w35809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOiO0l35813w35815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOiO1l35899w35901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOiOii35801w35803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0l0Ol24321w24322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0li0O24326w24327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0li1i20883w20886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0li1i20883w24187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0liil20875w20878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0liil20875w24182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0liOi24331w24332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0liOO20867w20870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0liOO20867w24177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0ll0l24336w24337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0llii20859w20862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0llii20859w24172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0lllO24341w24342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0llOl20851w20854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0llOl20851w24167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0lO0i24346w24347w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0lO0O20843w20846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0lO0O20843w24162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0lOll24351w24352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0lOOi20835w20838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0lOOi20835w24157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0O10l20827w20830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0O10l20827w24152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0O11O24356w24357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0Oi1i23454w23455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0Oiii20898w20915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0Oiii20898w20899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0Ol0i21223w23872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl10ilO28539w28540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOli101i20192w23502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOli101l20190w20191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlii0iO18300w18304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliiiOO18267w18279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliilii18159w18433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliilii18159w18435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliilii18159w18297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliliil17393w17397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlillOl17360w17372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlilO0O17252w17526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlilO0O17252w17528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlilO0O17252w17390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliOlii16486w16490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliOOOi16453w16465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll000i15438w15712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll000i15438w15714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll000i15438w15576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll01lO15546w15558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll110l16345w16619w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll110l16345w16621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll110l16345w16483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll1O0O15579w15583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlli0ll14639w14651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlli10l14672w14676w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllii1O14531w14805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllii1O14531w14807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllii1O14531w14669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlll00i13765w13769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlllili13732w13744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllll1l13624w13898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllll1l13624w13900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllll1l13624w13762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOi1O12858w12862w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOliO12825w12837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOO1i12717w12991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOO1i12717w12993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOO1i12717w12855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO011i11806w12080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO011i11806w12082w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO011i11806w11944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO1l1l11947w11951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO1O0i20967w23870w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO1OiO11914w11926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11221w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w11047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOl0Ol10165w10897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOllll10854w10874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOlO0l10935w10955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOlOOl11016w11036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOO01l11178w11198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOO0ll11259w11279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOO1il11097w11117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOOi0l11340w11360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOOiOl11421w11441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlOOO1O9954w9955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO000ll4352w29665w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO00llO4046w4048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO10l1i20908w21151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO10lOO8902w21166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO10lOO8902w21191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO10lOO8902w23242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO10lOO8902w23489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO1iiiO8535w8537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO1iili8527w8529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO1iill8519w8521w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO1iilO8511w8513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range45712w45713w51280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range45915w45916w49517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range45913w45914w49643w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range47787w47788w47789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range45710w45711w51414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range51119w51288w51289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range45805w45806w50402w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range45803w45804w50527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range47798w47799w47800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_conf_range1869w46186w46226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_conf_range9950w9951w9959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_gbl_hip_range23582w23583w23584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_hip_range2413w2429w5669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_tx_data_vc0_0_range4011w4012w4015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_tx_data_vc0_0_range4008w4009w4010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_tx_data_vc0_0_range4005w4006w4007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_tx_data_vc1_0_range2393w2394w2397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_tx_data_vc1_0_range2390w2391w2392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_tx_data_vc1_0_range2387w2388w2389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w20916w20917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w54874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOliii0l18289w18291w18292w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlill0i17382w17384w17385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOliOO1O16475w16477w16478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOll011l15568w15570w15571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlli01i14661w14663w14664w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlll0OO13754w13756w13757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOllOiOl12847w12849w12850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlO1lOi11936w11938w11939w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOO01lll5093w5094w5095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_niOO00l0i4100w4103w4104w4105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_niOO0l01l2477w2480w2481w2482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi00OOO53184w53185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1Olii54871w54872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiiO00O47759w47760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiiO0lO47741w47742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOilOO0l44001w44002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOli11il20299w20300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO01llO5097w5098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi001iO53582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00i0l53401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00iii53398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00iiO53395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00l1i53429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00l1l53424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00Oli53183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00Oll53194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0110l54839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi011ii54835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01i0l55508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01i0l54727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01i0l55397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOii53437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOOi53215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOOi53624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10lOl59875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10lOl59871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10O0O59712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10Oil59710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i10O59849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1ii0l58908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1iiiO58800w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1iiOi58693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O11O55414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1Ol1O54885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1OliO55198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1OlOi55403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1l0i52104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1liO52092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1OiO52069w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1OOl52070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1OOl52076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiili0O48151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiill0O48070w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiillil48057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO0Ol47768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOi1l48051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili01O51907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili0ii48150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilliOl45266w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilliOO45272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilll0i44317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilll0i44301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilll0i44295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilll0i44285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilll0i44280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilllOi53566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilllOl45264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilO0iO43943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOlOO43941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOO1i43390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOO1i43936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOO1i43987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO0Oll36547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1lii42830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi10l36263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOii0l35874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiiil35854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiiiO35851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiili35848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOilii35902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiliO35911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO1l35907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiOli36492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01l0i23892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0i0OO21015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l01i20919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0Ol24258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0Ol20884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0Ol24185w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0OO24219w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0OO24259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0OO20885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0OO24186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l1OO20911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li0O24254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li0O20876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li0O24180w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li1l20887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li1l24188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liii24215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liii24255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liii20877w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liii24181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liiO20879w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liiO24183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOi24250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOi20868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOi24175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOl24211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOl24251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOl20869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOl24176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0l24246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0l20860w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0l24170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0O24207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0O24247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0O20861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0O24171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll1i20871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll1i24178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llil20863w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llil24173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lllO24242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lllO20852w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lllO24165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOi24203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOi24243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOi20853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOi24166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOO20855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOO24168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0i24238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0i20844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0i24160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0l24199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0l24239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0l20845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0l24161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOii20847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOii24163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOll24234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOll20836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOll24155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOlO24195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOlO24235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOlO20837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOlO24156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOOl20839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOOl24158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10i24191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10i24231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10i20829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10i24151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10O20831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10O24153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O11O24230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O11O20828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O11O24150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Ol0l24924w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10O0i28350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11OOi29015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1Olli24923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1Olli24779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0i1O19683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli101i21149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1iOl21214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliii0l18289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliii1l18290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliil0l18156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlill0i17382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlill1i17383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlilO0i17249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOlOO16476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOO1O16475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll001l15435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll011l15568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll111O16342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1OOl15569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli01i14661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli1Oi14662w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllii1i14528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll0lO13755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll0OO13754w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllliOO13621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOill12848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOiOl12847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOlOl12714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1lli11937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1lOi11936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1OOl11803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOOlOl21014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO000ll4355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO000Ol4401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00i1O4326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00ill4320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00ill4312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00l0i4100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00lli4305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00lll4327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00llO4041w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01i1O5602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01lll5093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01lll5096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1OO3744w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l00O2566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l01l2477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOl56228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOO21168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOO9957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOO23473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OO1l6096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_valid_vc04037w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_valid_vc04031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_valid_vc12420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_valid_vc12414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_ni00O11O10767w10769w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_nl0liO1Oi51818w51819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_nl0lO0Oii50931w50932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_nl0O01i1l50047w50048w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8533w8538w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8525w8530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8517w8522w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8509w8514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45712w51281w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47794w47796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45915w49518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range49299w49515w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47787w51990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47787w47790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47783w47785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47776w47779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range48482w48483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range48482w48878w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45818w48487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range48494w48495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range48494w48609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45930w48491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range51061w51278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range51119w51982w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range51119w51290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range51117w51286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45805w50403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range50184w50400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47798w51986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47798w47801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46288w48197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46286w48200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range44263w44363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range44263w44327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range44263w44368w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range44263w44430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range44115w44116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range43970w43999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range43970w43972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range44000w44004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range47998w47999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range48000w48001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range48002w48003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range48004w48005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range48006w48007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range48008w48009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range48010w48011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range48012w48013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range29168w29457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range29168w29169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range1869w51903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range1869w46275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46162w51908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46162w51900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46162w51902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46162w51905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46162w51958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46175w51978w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46194w51896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range24588w24591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range24588w24630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_dev_range52044w52499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range28022w28028w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range28022w28025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range28020w28029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range54181w54184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range54181w54216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range54181w54586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range54181w54855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range55029w55039w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range55029w55032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range25479w25493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range2434w35935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range2434w59722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range1050w3435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range9015w9022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w6169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4666w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4077w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4049w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5661w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3409w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4081w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4079w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2457w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5610w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w6420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5653w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w4400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w3338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5604w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w5606w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_mode_range8895w9840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_test_in_hip_range61746w61749w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_test_in_hip_range61715w61726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w4018w4019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w2400w2401w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w51989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w51981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w51985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOilllOl45264w45265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOil0lil51645w51646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOil11lO49874w49875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOil1Oli50758w50759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl10l1O28513w28514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl10O0l28328w28329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0001l53584w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi000li53454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi000lO53415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0010i53645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0010l53612w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi001il53581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi001iO53573w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi001li54067w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi001OO53534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00lii53229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00lil53626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00liO53634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00O0i53602w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00O0l53601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00O0O53607w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00O1O53628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00Oii53609w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00Oil53600w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00Oli53198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00OOO53182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0101i54853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0110O54834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi011Oi54831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi011OO54520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01i0l54724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01i0O54209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01i1l54196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01l1l54090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01lli54052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01lll54217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi01Oll54001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0i11l53116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lO0O52760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOil52614w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOli53605w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOll53190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOOi53212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOOl53453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O00i52177w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O01i52553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O01l52176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O11i52280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O11l52275w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O1ii52250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O1iO52247w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O1ll52243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0O1lO52249w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0Oi0O52137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0Oi1l52159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0Oiii52517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0Oili52124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0Oill52127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0OilO52128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0Olii52139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0OliO52105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0Olli52103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10i1i61548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10i1l60239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10iil60170w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10iiO60253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10ill59981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10iOi60173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10iOO59973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10l0i60003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10l0O60193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10lOl59979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10lOO59856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10O0i59855w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10OlO61533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11ilO61846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11iOi61838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11iOO61783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11l1i61765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11O0l61544w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11O0O61539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11Oii61529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11Oil61526w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11Oli61464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi11OlO61462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i00l59715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i00O59724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i0Oi58933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i0Ol58929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i0OO58925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i10O59857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i1Ol60233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i1OO60237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1ii0i58907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1ii1O58911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1iiii58803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1iiil58799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1iill58695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1iilO58692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1illO57815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1ilOl57737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1li1l56196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1ll1i56068w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1llll55853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1lO0l55827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1lO0O55569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1lOil55566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1lOll55514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O0li55222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O0Oi55215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O0Ol55208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O0OO55207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O11i55413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1O1li56089w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1Oi0O55062w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1Oi1O55066w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1Oiil55040w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1Ol0i55828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1Ol1i54886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1OllO54888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1OlOi56853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1OOOi54859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1OOOl54858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii000i53801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii01il51966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii0lil51127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii0liO51285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii0O0O53809w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1liO52084w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1Oll52063w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1OOi52160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1OOl52072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOii1OOO52111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiii0ii50248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiii0i53818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiiO0l49363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiil0iO48178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiliOi48102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiilO1i48030w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiilOlO47917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO00O47763w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO0ii47746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO0il47745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO0Oi47735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO0Ol47734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO10O47795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO11l47838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO11O47846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO1li47784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOi0i46473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOi0l46472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOi0O46459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOi1i46476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOi1l46475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOi1O46474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOiii46324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOiOi46161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOiOl46160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOiOO46159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOl0i46155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOl0l46154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOl0O46153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOl1i46158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOl1l46157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOl1O46156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOlii46152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOlil46151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOliO46150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOlli46149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOlll46148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOllO46147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOlOi46146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOlOl46145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOlOO46144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOO0i46140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOO1i46143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOO1l46142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOO1O46141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOil45971w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOiO45970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOli45969w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOll45968w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOlO45967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOOi45966w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOOl45965w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiOOOO45964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil000i45784w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil000l45783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil000O45782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil001i45787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil001l45786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil001O45785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00ii45781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00il45780w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00iO45779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00li45778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00ll45777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00lO45776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00Oi45775w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00Ol45774w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil00OO45773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil010l45798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil010O45797w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil011i45826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil011l45825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil011O45824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01ii45796w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01il45795w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01iO45794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01li45793w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01ll45792w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01lO45791w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01Oi45790w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01Ol45789w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil01OO45788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0i0i45741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0i0l45740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0i0O45739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0i1i45772w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0i1l45771w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0iii45738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0iil45737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0iiO45736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0ili45735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0ill45734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0ilO45733w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0iOi45732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0iOl45731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0iOO45730w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0l0i45726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0l0l45725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0l0O45724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0l1i45729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0l1l45728w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0l1O45727w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lii45723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lil45722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0liO45721w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lli45720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lll45719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0llO45718w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lOi45717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lOl45716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lOO45715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0O0i45703w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0O0l45702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0O0O45701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0O1i45714w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0O1l45705w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0O1O45704w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0Oii45700w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0Oil45699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0OiO45698w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0Oli45697w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0Oll45696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0OlO45695w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0OOi45694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0OOl45693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0OOO45692w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil100i45945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil100l45944w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil101i45948w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil101l45947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil101O45946w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10ii45908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10il45907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10iO45906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10li45905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10ll45904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10lO45903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10Oi45902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10Ol45901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil10OO45900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil110i45960w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil110l45959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil110O45958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil111i45963w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil111l45962w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil111O45961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11ii45957w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11il45956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11iO45955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11li45954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11ll45953w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11lO45952w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11Oi45951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11Ol45950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11OO45949w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1i0i45896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1i0l45895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1i0O45894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1i1i45899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1i1l45898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1i1O45897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1iii45893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1iil45892w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1iiO45891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1ili45890w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1ill45889w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1ilO45888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1iOi45887w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1iOl45886w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1iOO45885w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1l0i45881w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1l0O45851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1l1i45884w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1l1l45883w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1l1O45882w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1lii45850w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1lil45849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1liO45848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1lli45847w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1lll45846w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1llO45845w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1lOi45844w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1lOl45843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1lOO45842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1O0i45838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1O0l45837w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1O0O45836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1O1i45841w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1O1l45840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1O1O45839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1Oii45835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1Oil45834w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1OiO45833w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1Oli45832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1Oll45831w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1OlO45830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1OOi45829w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1OOl45828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1OOO45827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili00i47932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili00l47930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili00O47928w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili01i45527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili0ii45092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili0iO53400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili0li53397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili0ll53394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili0Ol45064w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili10i45688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili10l45687w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili10O45686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili11i45691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili11l45690w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili11O45689w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1ii45685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1il45684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1iO45683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1li45682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1ll45681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1lO45680w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1Oi45679w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1Ol45678w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOili1OO45976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiliiOl45052w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiliiOO45050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilil0i45036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilil0O45034w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilil1O45126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill00i45131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill00l45129w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill00O45127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill01i45137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill01l45135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill01O45133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill0iO44369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill0Ol45197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill0OO44360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill1ll45147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill1lO45145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill1Oi45143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill1Ol45141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOill1OO45139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilli0i45236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilli0l45240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilll0O44332w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilll1i44485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilllii44330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilllil44328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOillliO44326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilllOl44309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilllOO44447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOillO0i46470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOillO0l46471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOillOil44080w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOillOiO44057w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilO0ii43817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilO11i52530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOi1l43406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOi1O43404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOl1l43927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOlii43399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOlli43955w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOlll44007w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOlOi44008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOlOl44009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOlOO43389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOO1i43375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO10Oi42898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO110i42934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO111l42937w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1i0i42896w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1i1l42897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1lOO42299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1O1l42254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1Oii42231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1OiO42230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1Oli42229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1OOl42297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi00i36176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi01O36178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi0li35985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi1li36212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi1ll36204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi1lO36222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi1Oi36215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi1Ol36207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOi1OO36187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOii0O35888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOilii35903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOilil35819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiliO35913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOilli35807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOillO35820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOilOl35808w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO0l35813w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO1i35814w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO1l35899w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO1O35802w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiOii35801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOl1ii34770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOli1i34556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOOiil29534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0011O23416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00iiO23552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00iOl21215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00iOO21213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00l0O23857w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00lil21194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00lli21189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00lOi21181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00lOO21178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00O0i26921w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00O0l26919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00O0O26917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00O1i26927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00O1l26925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00O1O26923w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00Oii26915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00Oil26914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00OiO21167w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl00Oll21164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0100O23590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl010ii23580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl010il23577w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl010iO23581w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl010li23576w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl011Oi23591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01l0l23485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01lii23553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01lli23469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01lll23467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01O0O23447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01Oii23445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01OiO23443w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01Oli23441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl01Oll23438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0i01l21114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0i0li21031w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0i10l21148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0i1ii21161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ii0O21003w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0iill20999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0iiOi20998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0il0i20989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0il1l20993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0il1O20991w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0iO0O20959w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0iOlO20945w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0iOOO20933w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l00O20903w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l01l20907w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l01O20906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0il20914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0li20891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0lO20888w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0Oi26105w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0Ol24321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l0OO24320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l10O23466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l11i20932w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l1iO23508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0l1OO20936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li0i20880w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li0l26103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li0O24326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0li1i20883w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liii24325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liil20875w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lill20872w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lilO26101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOi24331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOl24330w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0liOO20867w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0i26099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0l24336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll0O24335w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ll1O20864w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llii20859w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llli20856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llll26097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lllO24341w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOi24340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0llOl20851w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0i24346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0l24345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO0O20843w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO1l20848w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lO1O26095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOiO20840w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOli26093w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOll24351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOlO24350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0lOOi20835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O00i25976w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O00l23564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O00O23565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O01i25981w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O01l25979w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O01O25977w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O0ii23566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O0il23567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O0iO23568w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O0li23569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O0ll23570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O0lO23571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O0Oi20806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10i24355w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O10l20827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O11i20832w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O11l26092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O11O24356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O1lO25989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O1Oi25987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O1Ol25985w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O1OO25983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Oi1i23454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Oiii20898w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Ol0i21223w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Ol0l24926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Ol0O20757w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Ol1l20786w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Ol1O20785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Olil20684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OO0l20555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OO0O25392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OO1O20640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOii25390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOil25388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOiO25386w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOli25384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOll25382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOlO25380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOOi25379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0OOOl20506w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1000l28781w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1000O28779w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1001i28835w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1001O28823w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100ii28773w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100il28766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100iO28759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100li28752w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100ll28745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100lO28738w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100Oi28731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100Ol28724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl100OO28717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1010l29171w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1011O28876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl101ii28869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl101il28868w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl101iO29694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl101lO29696w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl101OO28842w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10i0l28669w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10i1l28688w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10i1O28686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10iii28651w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10iil28649w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10ill28541w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10ilO28539w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10iOl28534w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10l0i28518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10l1l28529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10l1O28516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10lii28478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10lil28482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10liO28475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10lli28474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10lll28464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10lOl28356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10lOO28354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10O0i28344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10O0l28331w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10O0O28333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10O1l28349w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10OiO28293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10Oli28297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10Oll28290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10OlO28289w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10OOi28279w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10OOl28272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10OOO28265w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1100i29483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1100l29482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1100O29481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1101i29486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1101l29485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1101O29484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110ii29480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110il29479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110iO29478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110li29477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110ll29476w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110lO29475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110Oi29474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110Ol29473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl110OO29472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl111Oi29489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl111Ol29488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl111OO29487w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11i0i29468w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11i0l29467w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11i0O29466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11i1i29471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11i1l29470w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11i1O29469w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11iii29465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11iil29464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11iiO29463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11ili29462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11ill29461w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11ilO29460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11iOi29459w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11iOl29458w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11l1i29456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11l1O32019w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11lll29365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl11OOl34628w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i01O24999w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i0OO24782w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i11O28120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i1ii28036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i1li25150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i1ll25149w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i1Oi25148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1i1OO25058w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1il1l24681w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1iOli24631w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1iOOi24593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1iOOl24592w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l00i24425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l00l24429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l00O24433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l01l24417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l01O24421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l0ii24437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l0il24441w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l0iO24445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1l11i24589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lO0l24102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lO0O24100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOii24098w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOil24096w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOiO24094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOli24092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOll24090w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOlO24088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOOi26657w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOOl26652w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1lOOO26647w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O00i23992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O00l23990w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O00O23988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O01l23996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O01O23994w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O0ii23986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O0il23984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O0iO23983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O10i26627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O10l26623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O11i26642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O11l26637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1O11O26632w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1OliO23853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl1OOli23839w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli000i19580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli01il19578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli01iO19565w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli01OO19562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0i1O19660w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0iil18989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0ill19512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0iOi19465w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0l0i19564w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0l0O18972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0llO18964w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0lOl18958w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0lOO18956w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0O1i19670w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0O1l19558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0O1O18941w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli0OlO18770w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli101i20192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli101l20190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli101O20189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli10il21112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli10Ol20065w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli111l20301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli11iO20255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli11ll20252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli11Ol20248w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1iiO20055w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1iOl20954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1iOO20777w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1l1i20778w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1l1O19995w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1lli19684w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1lOl19682w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1lOO19594w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1O0O19579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1OiO23494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii00l18351w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii01l18354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii0iO18300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii0Oi18229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii11i18931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii1Oi18396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliiiil18296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliiiOO18267w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliil0l18160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliil1i18278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliil1O18295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliilii18159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliilli18117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlil0lO17489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlil1li17913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlil1ll18059w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlil1lO17908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlil1Oi17916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlili0i17444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlili1i17447w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliliil17393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlililO17322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlillii17389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlillOl17360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlillOO17371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlilO0i17253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlilO0O17252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlilO1l17388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlilOiO17210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliO0iO17006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliO0li17152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliO0ll17001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliO0lO17009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOill16582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOiOO16540w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOl1O16537w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOlii16486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOlll16415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOO0O16482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOOOi16453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOOOl16464w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll000i15438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll001l15439w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll00ii15396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll010l15575w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll01lO15546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll01Oi15557w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll01OO15574w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll0lii15192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll0lil15338w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll0liO15187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll0lli15195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll0OiO14768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll0OOi14726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll110l16345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll111i16481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll111O16346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll11il16303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1iil16099w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1iiO16245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1ili16094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1ill16102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1lli15675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1lOl15633w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1O0O15579w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1O1l15630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1Oli15508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli00i14668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli0ll14639w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli0lO14650w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli0Ol14667w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli10l14672w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli11i14723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli1iO14601w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllii0O14489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllii1i14532w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllii1O14531w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlliO0O14285w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlliOii14431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlliOil14280w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlliOiO14288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll00i13765w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll0il13694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll1il13861w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll1lO13819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll1OO13816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllli1O13761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlllili13732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlllill13743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllliOi13760w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllliOO13625w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllll0l13582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllll1l13624w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllO0ii12954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllO0ll12912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllO0Ol12909w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllO10l13378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllO10O13524w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllO1ii13373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllO1il13381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOi1O12858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOiii12787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOl1l12854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOliO12825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOlli12836w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOllO12853w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOlOl12718w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOO0i12675w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOO1i12717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO010i11764w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO011i11806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0i0i11558w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0i0l11706w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0i0O11553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0iii11562w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0liO11440w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO0Oll11359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO100i12471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO100l12617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO100O12466w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO10ii12474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1i0O12043w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1ili12001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1iOi11998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1l0O11876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1l1l11947w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1O0i20967w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1O1i11943w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1OiO11914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1Oli11925w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1OlO11942w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1OOl11807w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOi0OO11197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOi1Oi11278w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOil1l11116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOiO0i11035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOl0il10873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOl0Ol10165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOl10O10954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOli0i10824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOli0l10822w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOli0O10820w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOli1l10828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOli1O10826w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOliii10818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOliil10816w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOliiO10815w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOll0l10155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOll1i10154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOll1O10153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOllll10854w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOlO0l10935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOlOOl11016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOO01l11178w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOO0ll11259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOO1il11097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOOi0l11340w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOOiOl11421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOOO1l9961w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlOOO1O9954w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO000ll4352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO000Oi4345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0010l4569w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0011i4578w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0011O4571w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO001ii4567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO001iO4486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO001li4490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO001ll4483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO001lO4482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00llO4046w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00lOO4032w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00O0l4023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00Oii3766w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00Oil3768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00OOl3742w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00OOO3743w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO010iO5648w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01i1l5387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01l0l5119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01lii5127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01liO5159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01lli5092w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01lOi5719w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01lOl5214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01O0i4613w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01O0l4615w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01Oll4589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01OlO4590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01OOl4583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i10i3731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i10l3724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i11l3736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1ii3722w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1iO3720w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1ll3640w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1lO3644w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1Oi3637w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1Ol3636w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0i1OO3830w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iiOi3378w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iiOO3252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0il0i3404w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0il0l3327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0il1O3274w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0illl2759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0illO2761w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iO0i2736w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iO0O2729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iO1O2735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iOil2724w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iOll2717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iOOi2715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0iOOO2713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l0li2415w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l0OO2405w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l10i2627w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l10l2626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l11l2630w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0l11O2634w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0lOOi2256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0lOOl2255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0O11l2254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0O11O2253w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0O1ll4426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0O1lO2591w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10ilO9183w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10iOi9182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10iOl9024w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10iOO9023w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10l1i20908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lii45508w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lil45510w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10liO45516w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lll45518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10llO45512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOi45514w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOO8902w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10O0i59411w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10O0O43993w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10O1l8900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10Oii8785w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10Oil8776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10OiO8767w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10OOi46502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1i11l8582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1i11O8580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iiil8542w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iiiO8535w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iili8527w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iill8519w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iilO8511w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iiOl8493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iiOO8486w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1il0i8435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1il0l8423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1il0O8417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1il1i8479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1il1l8472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ilii8410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ilil8403w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iliO8391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1illi8383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1illl8375w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1illO8367w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ilOi8360w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ilOl8352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ilOO8344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iO0i8312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iO0l8304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iO0O8297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iO1i8336w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iO1l8328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iO1O8320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOii8290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOil8283w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOiO8276w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOli8269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOll8262w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOlO8255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOOl8224w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1iOOO8222w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l00l7950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l00O7936w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l01i8004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l01O7992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l0ii7929w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l0il7922w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l0iO7915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l0li7908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l0ll7901w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l0Oi7894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l0OO7876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l10l8179w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l10O8173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l11l8204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l11O8198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l1il8145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l1iO8136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l1ll8060w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l1lO8035w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l1Ol8018w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1l1OO8011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1li0i35176w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1li1l7858w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1li1O7856w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1liiO7821w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lill7803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lilO7801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ll0i7747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ll0l7739w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ll0O7731w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ll1i7768w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ll1l7762w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1ll1O7755w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1llii7723w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1llil7716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lliO7709w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1llli7701w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1llll7693w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lllO7685w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1llOl7599w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1llOO7572w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lO0O7361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lO1i7566w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lO1l7559w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lOii7359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lOli7233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1lOll7231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Oi0i6385w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Oi0l6383w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Oiii6365w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Oiil6359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OiiO6118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Oili6120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Ol0i6088w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Ol0O6083w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Ol1i6094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Ol1l6095w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Olii6076w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OliO6074w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1Olll6072w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OlOi5992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OlOl5996w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OlOO5989w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OO1i5988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO1OO1l6182w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_eop_vc0_04425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_eop_vc1_02590w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_err_vc04036w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_err_vc12419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_sop_vc0_04025w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_sop_vc0_14026w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_sop_vc1_02407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_tx_sop_vc1_12408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45712w45713w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45915w45916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45913w45914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47787w47788w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45710w45711w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45818w45819w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45930w45931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range51119w51288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45805w45806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45803w45804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range47798w47799w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range44263w44264w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range1869w46186w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range46173w46174w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_conf_range9950w9951w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_dev_range52047w52497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range25481w25482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range1050w1051w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range23582w23583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_hip_range2413w2429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_mode_range8897w9838w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_test_in_hip_range61747w61748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_test_in_hip_range61717w61725w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc0_0_range4011w4012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc0_0_range4013w4014w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc0_0_range4016w4017w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc0_0_range4008w4009w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc0_0_range4005w4006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc1_0_range2393w2394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc1_0_range2395w2396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc1_0_range2398w2399w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc1_0_range2390w2391w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_tx_data_vc1_0_range2387w2388w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w20916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w35817w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w35805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_k_hip_range2413w5661w5662w5668w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOi001iO53573w53578w53580w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOl0Oiii20898w20899w20900w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOl0Ol0i21223w23872w23873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOi1Olii54871w54872w54873w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOilii35902w35908w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliii0l18289w18291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliil0l18156w18157w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlill0i17382w17384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlilO0i17249w17250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliOO1O16475w16477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll001l15435w15436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll011l15568w15570w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll111O16342w16343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlli01i14661w14663w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllii1i14528w14529w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlll0OO13754w13756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllliOO13621w13622w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOiOl12847w12849w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOlOl12714w12715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO1lOi11936w11938w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO1OOl11803w11804w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO00l0i4100w4103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO00lli4305w4306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO01lll5093w5094w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO0l00O2566w2567w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOO0l01l2477w2480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_conf_range1869w46275w51906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi000lO53415w53448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi0010i53645w53646w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi0010l53612w53621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1ii1O58911w58926w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1iiii58803w58930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1iill58695w58934w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOilOi1O43404w43986w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOilii35903w35906w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiOiliO35913w35916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0Ol0l24926w24927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOli0iil18989w19425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_conf_range44263w44264w44269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_hip_range2413w2429w3333w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_hip_range2413w2429w5225w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w35817w35818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w35805w35806w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w5671w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w53583w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOiOilii35902w35908w35912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOliil0l18156w18157w18158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlilO0i17249w17250w17251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOll001l15435w15436w15437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOll111O16342w16343w16344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOllii1i14528w14529w14530w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOllliOO13621w13622w13623w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOllOlOl12714w12715w12716w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOlO1OOl11803w11804w11805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOO00l0i4100w4103w4104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOO0l01l2477w2480w2481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOi1ii1O58911w58926w58927w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOi1iiii58803w58930w58931w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOi1iill58695w58934w58935w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOli0iil18989w19425w19426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w44270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w53583w53586w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w35918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w44270w44271w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w53583w53586w53589w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w44270w44271w44272w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w53583w53586w53589w53593w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w42915w42916w42917w42918w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w42915w42916w42917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w42915w42916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w42915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w42246w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOiO10il42912w42913w42914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOiO1Oii42243w42244w42245w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_niOl0ilOl20972w20973w20974w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi00Oii53617w53618w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi10l0O60203w60205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOi1i01O59406w59407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiil0Ol48209w48210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiO10il42912w42913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOiO1Oii42243w42244w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0ilOl20972w20973w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0O1iO20894w20895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOl0O1li20824w20825w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlii0lO18269w18270w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlilill17362w17363w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOliOlli16455w16456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOll1OiO15548w15549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlli1il14641w14642w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlll0ii13734w13735w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOllOi0O12827w12828w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_niOlO1l0l11916w11917w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_k_bar_range45805w51984w51987w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00O1i53214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00Oii53617w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi00OOO53184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi0lOii53444w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi10l0O60203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1i01O59406w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1Olii54871w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOi1OO1i54726w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiil0Ol48209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO00O47759w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiiO0lO47741w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOilOO0l44001w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO10il42912w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1lOl42295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1O0O42242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiO1Oii42243w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOil0l35920w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOil0O35919w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOilOO35904w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO0i35905w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO0O35915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOiO1l35914w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOiOl0li34626w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0il0O20992w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0ilOl20972w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O1iO20894w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0O1li20824w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl0Ol0l23874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli11il20299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOli1OiO23876w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlii0lO18269w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlilill17362w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOliOlli16455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOll1OiO15548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlli1il14641w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlll0ii13734w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOllOi0O12827w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOlO1l0l11916w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00iii4313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO00lll4047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO010li5677w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01lil5707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO01llO5097w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO0il1l3392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOO23891w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOO10lOO23893w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45712w51983w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45915w51988w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_bar_range45805w51984w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range1050w3226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_k_gbl_hip_range23582w23621w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil0lil51645w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil11lO49874w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOil1Oli50758w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10l0l28505w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10l1O28513w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10O0l28328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_niOl10Oii28320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8533w8536w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8525w8528w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8517w8520w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_cpl_err_range8509w8512w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phycfg_range7707w7710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phycfg_range7699w7702w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phycfg_range7691w7694w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phycfg_range7683w7686w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phypm_range7753w7756w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phypm_range7745w7748w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phypm_range7737w7740w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_dl_req_phypm_range7729w7732w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swdn_in_range8389w8392w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swdn_in_range8381w8384w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swdn_in_range8373w8376w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swup_in_range8358w8361w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swup_in_range8350w8353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swup_in_range8342w8345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swup_in_range8334w8337w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swup_in_range8326w8329w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swup_in_range8318w8321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_swup_in_range8310w8313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL niOi0000i : STD_LOGIC; + SIGNAL niOi0000l : STD_LOGIC; + SIGNAL niOi0000O : STD_LOGIC; + SIGNAL niOi0001i : STD_LOGIC; + SIGNAL niOi0001l : STD_LOGIC; + SIGNAL niOi0001O : STD_LOGIC; + SIGNAL niOi000ii : STD_LOGIC; + SIGNAL niOi000il : STD_LOGIC; + SIGNAL niOi000iO : STD_LOGIC; + SIGNAL niOi000li : STD_LOGIC; + SIGNAL niOi000ll : STD_LOGIC; + SIGNAL niOi000lO : STD_LOGIC; + SIGNAL niOi000Oi : STD_LOGIC; + SIGNAL niOi000Ol : STD_LOGIC; + SIGNAL niOi000OO : STD_LOGIC; + SIGNAL niOi0010i : STD_LOGIC; + SIGNAL niOi0010l : STD_LOGIC; + SIGNAL niOi0010O : STD_LOGIC; + SIGNAL niOi0011i : STD_LOGIC; + SIGNAL niOi0011l : STD_LOGIC; + SIGNAL niOi0011O : STD_LOGIC; + SIGNAL niOi001ii : STD_LOGIC; + SIGNAL niOi001il : STD_LOGIC; + SIGNAL niOi001iO : STD_LOGIC; + SIGNAL niOi001li : STD_LOGIC; + SIGNAL niOi001ll : STD_LOGIC; + SIGNAL niOi001lO : STD_LOGIC; + SIGNAL niOi001Oi : STD_LOGIC; + SIGNAL niOi001Ol : STD_LOGIC; + SIGNAL niOi001OO : STD_LOGIC; + SIGNAL niOi00i0i : STD_LOGIC; + SIGNAL niOi00i0l : STD_LOGIC; + SIGNAL niOi00i0O : STD_LOGIC; + SIGNAL niOi00i1i : STD_LOGIC; + SIGNAL niOi00i1l : STD_LOGIC; + SIGNAL niOi00i1O : STD_LOGIC; + SIGNAL niOi00iii : STD_LOGIC; + SIGNAL niOi00iil : STD_LOGIC; + SIGNAL niOi00iiO : STD_LOGIC; + SIGNAL niOi00ili : STD_LOGIC; + SIGNAL niOi00ill : STD_LOGIC; + SIGNAL niOi00ilO : STD_LOGIC; + SIGNAL niOi00iOi : STD_LOGIC; + SIGNAL niOi00iOl : STD_LOGIC; + SIGNAL niOi00iOO : STD_LOGIC; + SIGNAL niOi00l0i : STD_LOGIC; + SIGNAL niOi00l0l : STD_LOGIC; + SIGNAL niOi00l0O : STD_LOGIC; + SIGNAL niOi00l1i : STD_LOGIC; + SIGNAL niOi00l1l : STD_LOGIC; + SIGNAL niOi00l1O : STD_LOGIC; + SIGNAL niOi00lii : STD_LOGIC; + SIGNAL niOi00lil : STD_LOGIC; + SIGNAL niOi00liO : STD_LOGIC; + SIGNAL niOi00lli : STD_LOGIC; + SIGNAL niOi00lll : STD_LOGIC; + SIGNAL niOi00llO : STD_LOGIC; + SIGNAL niOi00lOi : STD_LOGIC; + SIGNAL niOi00lOl : STD_LOGIC; + SIGNAL niOi00lOO : STD_LOGIC; + SIGNAL niOi00O0i : STD_LOGIC; + SIGNAL niOi00O0l : STD_LOGIC; + SIGNAL niOi00O0O : STD_LOGIC; + SIGNAL niOi00O1i : STD_LOGIC; + SIGNAL niOi00O1l : STD_LOGIC; + SIGNAL niOi00O1O : STD_LOGIC; + SIGNAL niOi00Oii : STD_LOGIC; + SIGNAL niOi00Oil : STD_LOGIC; + SIGNAL niOi00OiO : STD_LOGIC; + SIGNAL niOi00Oli : STD_LOGIC; + SIGNAL niOi00Oll : STD_LOGIC; + SIGNAL niOi00OlO : STD_LOGIC; + SIGNAL niOi00OOi : STD_LOGIC; + SIGNAL niOi00OOl : STD_LOGIC; + SIGNAL niOi00OOO : STD_LOGIC; + SIGNAL niOi0100i : STD_LOGIC; + SIGNAL niOi0100l : STD_LOGIC; + SIGNAL niOi0100O : STD_LOGIC; + SIGNAL niOi0101i : STD_LOGIC; + SIGNAL niOi0101l : STD_LOGIC; + SIGNAL niOi0101O : STD_LOGIC; + SIGNAL niOi010ii : STD_LOGIC; + SIGNAL niOi010il : STD_LOGIC; + SIGNAL niOi010iO : STD_LOGIC; + SIGNAL niOi010li : STD_LOGIC; + SIGNAL niOi010ll : STD_LOGIC; + SIGNAL niOi010lO : STD_LOGIC; + SIGNAL niOi010Oi : STD_LOGIC; + SIGNAL niOi010Ol : STD_LOGIC; + SIGNAL niOi010OO : STD_LOGIC; + SIGNAL niOi0110i : STD_LOGIC; + SIGNAL niOi0110l : STD_LOGIC; + SIGNAL niOi0110O : STD_LOGIC; + SIGNAL niOi0111i : STD_LOGIC; + SIGNAL niOi0111l : STD_LOGIC; + SIGNAL niOi0111O : STD_LOGIC; + SIGNAL niOi011ii : STD_LOGIC; + SIGNAL niOi011il : STD_LOGIC; + SIGNAL niOi011iO : STD_LOGIC; + SIGNAL niOi011li : STD_LOGIC; + SIGNAL niOi011ll : STD_LOGIC; + SIGNAL niOi011lO : STD_LOGIC; + SIGNAL niOi011Oi : STD_LOGIC; + SIGNAL niOi011Ol : STD_LOGIC; + SIGNAL niOi011OO : STD_LOGIC; + SIGNAL niOi01i0i : STD_LOGIC; + SIGNAL niOi01i0l : STD_LOGIC; + SIGNAL niOi01i0O : STD_LOGIC; + SIGNAL niOi01i1i : STD_LOGIC; + SIGNAL niOi01i1l : STD_LOGIC; + SIGNAL niOi01i1O : STD_LOGIC; + SIGNAL niOi01iii : STD_LOGIC; + SIGNAL niOi01iil : STD_LOGIC; + SIGNAL niOi01iiO : STD_LOGIC; + SIGNAL niOi01ili : STD_LOGIC; + SIGNAL niOi01ill : STD_LOGIC; + SIGNAL niOi01ilO : STD_LOGIC; + SIGNAL niOi01iOi : STD_LOGIC; + SIGNAL niOi01iOl : STD_LOGIC; + SIGNAL niOi01iOO : STD_LOGIC; + SIGNAL niOi01l0i : STD_LOGIC; + SIGNAL niOi01l0l : STD_LOGIC; + SIGNAL niOi01l0O : STD_LOGIC; + SIGNAL niOi01l1i : STD_LOGIC; + SIGNAL niOi01l1l : STD_LOGIC; + SIGNAL niOi01l1O : STD_LOGIC; + SIGNAL niOi01lii : STD_LOGIC; + SIGNAL niOi01lil : STD_LOGIC; + SIGNAL niOi01liO : STD_LOGIC; + SIGNAL niOi01lli : STD_LOGIC; + SIGNAL niOi01lll : STD_LOGIC; + SIGNAL niOi01llO : STD_LOGIC; + SIGNAL niOi01lOi : STD_LOGIC; + SIGNAL niOi01lOl : STD_LOGIC; + SIGNAL niOi01lOO : STD_LOGIC; + SIGNAL niOi01O0i : STD_LOGIC; + SIGNAL niOi01O0l : STD_LOGIC; + SIGNAL niOi01O0O : STD_LOGIC; + SIGNAL niOi01O1i : STD_LOGIC; + SIGNAL niOi01O1l : STD_LOGIC; + SIGNAL niOi01O1O : STD_LOGIC; + SIGNAL niOi01Oii : STD_LOGIC; + SIGNAL niOi01Oil : STD_LOGIC; + SIGNAL niOi01OiO : STD_LOGIC; + SIGNAL niOi01Oli : STD_LOGIC; + SIGNAL niOi01Oll : STD_LOGIC; + SIGNAL niOi01OlO : STD_LOGIC; + SIGNAL niOi01OOi : STD_LOGIC; + SIGNAL niOi01OOl : STD_LOGIC; + SIGNAL niOi01OOO : STD_LOGIC; + SIGNAL niOi0i00i : STD_LOGIC; + SIGNAL niOi0i00l : STD_LOGIC; + SIGNAL niOi0i00O : STD_LOGIC; + SIGNAL niOi0i01i : STD_LOGIC; + SIGNAL niOi0i01l : STD_LOGIC; + SIGNAL niOi0i01O : STD_LOGIC; + SIGNAL niOi0i0ii : STD_LOGIC; + SIGNAL niOi0i0il : STD_LOGIC; + SIGNAL niOi0i0iO : STD_LOGIC; + SIGNAL niOi0i0li : STD_LOGIC; + SIGNAL niOi0i0ll : STD_LOGIC; + SIGNAL niOi0i0lO : STD_LOGIC; + SIGNAL niOi0i0Oi : STD_LOGIC; + SIGNAL niOi0i0Ol : STD_LOGIC; + SIGNAL niOi0i0OO : STD_LOGIC; + SIGNAL niOi0i10i : STD_LOGIC; + SIGNAL niOi0i10l : STD_LOGIC; + SIGNAL niOi0i10O : STD_LOGIC; + SIGNAL niOi0i11i : STD_LOGIC; + SIGNAL niOi0i11l : STD_LOGIC; + SIGNAL niOi0i11O : STD_LOGIC; + SIGNAL niOi0i1ii : STD_LOGIC; + SIGNAL niOi0i1il : STD_LOGIC; + SIGNAL niOi0i1iO : STD_LOGIC; + SIGNAL niOi0i1li : STD_LOGIC; + SIGNAL niOi0i1ll : STD_LOGIC; + SIGNAL niOi0i1lO : STD_LOGIC; + SIGNAL niOi0i1Oi : STD_LOGIC; + SIGNAL niOi0i1Ol : STD_LOGIC; + SIGNAL niOi0i1OO : STD_LOGIC; + SIGNAL niOi0ii0i : STD_LOGIC; + SIGNAL niOi0ii0l : STD_LOGIC; + SIGNAL niOi0ii0O : STD_LOGIC; + SIGNAL niOi0ii1i : STD_LOGIC; + SIGNAL niOi0ii1l : STD_LOGIC; + SIGNAL niOi0ii1O : STD_LOGIC; + SIGNAL niOi0iiii : STD_LOGIC; + SIGNAL niOi0iiil : STD_LOGIC; + SIGNAL niOi0iiiO : STD_LOGIC; + SIGNAL niOi0iili : STD_LOGIC; + SIGNAL niOi0iill : STD_LOGIC; + SIGNAL niOi0iilO : STD_LOGIC; + SIGNAL niOi0iiOi : STD_LOGIC; + SIGNAL niOi0iiOl : STD_LOGIC; + SIGNAL niOi0iiOO : STD_LOGIC; + SIGNAL niOi0il0i : STD_LOGIC; + SIGNAL niOi0il0l : STD_LOGIC; + SIGNAL niOi0il0O : STD_LOGIC; + SIGNAL niOi0il1i : STD_LOGIC; + SIGNAL niOi0il1l : STD_LOGIC; + SIGNAL niOi0il1O : STD_LOGIC; + SIGNAL niOi0ilii : STD_LOGIC; + SIGNAL niOi0ilil : STD_LOGIC; + SIGNAL niOi0iliO : STD_LOGIC; + SIGNAL niOi0illi : STD_LOGIC; + SIGNAL niOi0illl : STD_LOGIC; + SIGNAL niOi0illO : STD_LOGIC; + SIGNAL niOi0ilOi : STD_LOGIC; + SIGNAL niOi0ilOl : STD_LOGIC; + SIGNAL niOi0ilOO : STD_LOGIC; + SIGNAL niOi0iO0i : STD_LOGIC; + SIGNAL niOi0iO0l : STD_LOGIC; + SIGNAL niOi0iO0O : STD_LOGIC; + SIGNAL niOi0iO1i : STD_LOGIC; + SIGNAL niOi0iO1l : STD_LOGIC; + SIGNAL niOi0iO1O : STD_LOGIC; + SIGNAL niOi0iOii : STD_LOGIC; + SIGNAL niOi0iOil : STD_LOGIC; + SIGNAL niOi0iOiO : STD_LOGIC; + SIGNAL niOi0iOli : STD_LOGIC; + SIGNAL niOi0iOll : STD_LOGIC; + SIGNAL niOi0iOlO : STD_LOGIC; + SIGNAL niOi0iOOi : STD_LOGIC; + SIGNAL niOi0iOOl : STD_LOGIC; + SIGNAL niOi0iOOO : STD_LOGIC; + SIGNAL niOi0l00i : STD_LOGIC; + SIGNAL niOi0l00l : STD_LOGIC; + SIGNAL niOi0l00O : STD_LOGIC; + SIGNAL niOi0l01i : STD_LOGIC; + SIGNAL niOi0l01l : STD_LOGIC; + SIGNAL niOi0l01O : STD_LOGIC; + SIGNAL niOi0l0ii : STD_LOGIC; + SIGNAL niOi0l0il : STD_LOGIC; + SIGNAL niOi0l0iO : STD_LOGIC; + SIGNAL niOi0l0li : STD_LOGIC; + SIGNAL niOi0l0ll : STD_LOGIC; + SIGNAL niOi0l0lO : STD_LOGIC; + SIGNAL niOi0l0Oi : STD_LOGIC; + SIGNAL niOi0l0Ol : STD_LOGIC; + SIGNAL niOi0l0OO : STD_LOGIC; + SIGNAL niOi0l10i : STD_LOGIC; + SIGNAL niOi0l10l : STD_LOGIC; + SIGNAL niOi0l10O : STD_LOGIC; + SIGNAL niOi0l11i : STD_LOGIC; + SIGNAL niOi0l11l : STD_LOGIC; + SIGNAL niOi0l11O : STD_LOGIC; + SIGNAL niOi0l1ii : STD_LOGIC; + SIGNAL niOi0l1il : STD_LOGIC; + SIGNAL niOi0l1iO : STD_LOGIC; + SIGNAL niOi0l1li : STD_LOGIC; + SIGNAL niOi0l1ll : STD_LOGIC; + SIGNAL niOi0l1lO : STD_LOGIC; + SIGNAL niOi0l1Oi : STD_LOGIC; + SIGNAL niOi0l1Ol : STD_LOGIC; + SIGNAL niOi0l1OO : STD_LOGIC; + SIGNAL niOi0li0i : STD_LOGIC; + SIGNAL niOi0li0l : STD_LOGIC; + SIGNAL niOi0li0O : STD_LOGIC; + SIGNAL niOi0li1i : STD_LOGIC; + SIGNAL niOi0li1l : STD_LOGIC; + SIGNAL niOi0li1O : STD_LOGIC; + SIGNAL niOi0liii : STD_LOGIC; + SIGNAL niOi0liil : STD_LOGIC; + SIGNAL niOi0liiO : STD_LOGIC; + SIGNAL niOi0lili : STD_LOGIC; + SIGNAL niOi0lill : STD_LOGIC; + SIGNAL niOi0lilO : STD_LOGIC; + SIGNAL niOi0liOi : STD_LOGIC; + SIGNAL niOi0liOl : STD_LOGIC; + SIGNAL niOi0liOO : STD_LOGIC; + SIGNAL niOi0ll0i : STD_LOGIC; + SIGNAL niOi0ll0l : STD_LOGIC; + SIGNAL niOi0ll0O : STD_LOGIC; + SIGNAL niOi0ll1i : STD_LOGIC; + SIGNAL niOi0ll1l : STD_LOGIC; + SIGNAL niOi0ll1O : STD_LOGIC; + SIGNAL niOi0llii : STD_LOGIC; + SIGNAL niOi0llil : STD_LOGIC; + SIGNAL niOi0lliO : STD_LOGIC; + SIGNAL niOi0llli : STD_LOGIC; + SIGNAL niOi0llll : STD_LOGIC; + SIGNAL niOi0lllO : STD_LOGIC; + SIGNAL niOi0llOi : STD_LOGIC; + SIGNAL niOi0llOl : STD_LOGIC; + SIGNAL niOi0llOO : STD_LOGIC; + SIGNAL niOi0lO0i : STD_LOGIC; + SIGNAL niOi0lO0l : STD_LOGIC; + SIGNAL niOi0lO0O : STD_LOGIC; + SIGNAL niOi0lO1i : STD_LOGIC; + SIGNAL niOi0lO1l : STD_LOGIC; + SIGNAL niOi0lO1O : STD_LOGIC; + SIGNAL niOi0lOii : STD_LOGIC; + SIGNAL niOi0lOil : STD_LOGIC; + SIGNAL niOi0lOiO : STD_LOGIC; + SIGNAL niOi0lOli : STD_LOGIC; + SIGNAL niOi0lOll : STD_LOGIC; + SIGNAL niOi0lOlO : STD_LOGIC; + SIGNAL niOi0lOOi : STD_LOGIC; + SIGNAL niOi0lOOl : STD_LOGIC; + SIGNAL niOi0lOOO : STD_LOGIC; + SIGNAL niOi0O00i : STD_LOGIC; + SIGNAL niOi0O00l : STD_LOGIC; + SIGNAL niOi0O00O : STD_LOGIC; + SIGNAL niOi0O01i : STD_LOGIC; + SIGNAL niOi0O01l : STD_LOGIC; + SIGNAL niOi0O01O : STD_LOGIC; + SIGNAL niOi0O0ii : STD_LOGIC; + SIGNAL niOi0O0il : STD_LOGIC; + SIGNAL niOi0O0iO : STD_LOGIC; + SIGNAL niOi0O0li : STD_LOGIC; + SIGNAL niOi0O0ll : STD_LOGIC; + SIGNAL niOi0O0lO : STD_LOGIC; + SIGNAL niOi0O0Oi : STD_LOGIC; + SIGNAL niOi0O0Ol : STD_LOGIC; + SIGNAL niOi0O0OO : STD_LOGIC; + SIGNAL niOi0O10i : STD_LOGIC; + SIGNAL niOi0O10l : STD_LOGIC; + SIGNAL niOi0O10O : STD_LOGIC; + SIGNAL niOi0O11i : STD_LOGIC; + SIGNAL niOi0O11l : STD_LOGIC; + SIGNAL niOi0O11O : STD_LOGIC; + SIGNAL niOi0O1ii : STD_LOGIC; + SIGNAL niOi0O1il : STD_LOGIC; + SIGNAL niOi0O1iO : STD_LOGIC; + SIGNAL niOi0O1li : STD_LOGIC; + SIGNAL niOi0O1ll : STD_LOGIC; + SIGNAL niOi0O1lO : STD_LOGIC; + SIGNAL niOi0O1Oi : STD_LOGIC; + SIGNAL niOi0O1Ol : STD_LOGIC; + SIGNAL niOi0O1OO : STD_LOGIC; + SIGNAL niOi0Oi0i : STD_LOGIC; + SIGNAL niOi0Oi0l : STD_LOGIC; + SIGNAL niOi0Oi0O : STD_LOGIC; + SIGNAL niOi0Oi1i : STD_LOGIC; + SIGNAL niOi0Oi1l : STD_LOGIC; + SIGNAL niOi0Oi1O : STD_LOGIC; + SIGNAL niOi0Oiii : STD_LOGIC; + SIGNAL niOi0Oiil : STD_LOGIC; + SIGNAL niOi0OiiO : STD_LOGIC; + SIGNAL niOi0Oili : STD_LOGIC; + SIGNAL niOi0Oill : STD_LOGIC; + SIGNAL niOi0OilO : STD_LOGIC; + SIGNAL niOi0OiOi : STD_LOGIC; + SIGNAL niOi0OiOl : STD_LOGIC; + SIGNAL niOi0OiOO : STD_LOGIC; + SIGNAL niOi0Ol0i : STD_LOGIC; + SIGNAL niOi0Ol0l : STD_LOGIC; + SIGNAL niOi0Ol0O : STD_LOGIC; + SIGNAL niOi0Ol1i : STD_LOGIC; + SIGNAL niOi0Ol1l : STD_LOGIC; + SIGNAL niOi0Ol1O : STD_LOGIC; + SIGNAL niOi0Olii : STD_LOGIC; + SIGNAL niOi0Olil : STD_LOGIC; + SIGNAL niOi0OliO : STD_LOGIC; + SIGNAL niOi0Olli : STD_LOGIC; + SIGNAL niOi0Olll : STD_LOGIC; + SIGNAL niOi0OllO : STD_LOGIC; + SIGNAL niOi0OlOi : STD_LOGIC; + SIGNAL niOi0OlOl : STD_LOGIC; + SIGNAL niOi0OlOO : STD_LOGIC; + SIGNAL niOi0OO0i : STD_LOGIC; + SIGNAL niOi0OO0l : STD_LOGIC; + SIGNAL niOi0OO0O : STD_LOGIC; + SIGNAL niOi0OO1i : STD_LOGIC; + SIGNAL niOi0OO1l : STD_LOGIC; + SIGNAL niOi0OO1O : STD_LOGIC; + SIGNAL niOi0OOii : STD_LOGIC; + SIGNAL niOi0OOil : STD_LOGIC; + SIGNAL niOi0OOiO : STD_LOGIC; + SIGNAL niOi0OOli : STD_LOGIC; + SIGNAL niOi0OOll : STD_LOGIC; + SIGNAL niOi0OOlO : STD_LOGIC; + SIGNAL niOi0OOOi : STD_LOGIC; + SIGNAL niOi0OOOl : STD_LOGIC; + SIGNAL niOi0OOOO : STD_LOGIC; + SIGNAL niOi1000i : STD_LOGIC; + SIGNAL niOi1000l : STD_LOGIC; + SIGNAL niOi1000O : STD_LOGIC; + SIGNAL niOi1001i : STD_LOGIC; + SIGNAL niOi1001l : STD_LOGIC; + SIGNAL niOi1001O : STD_LOGIC; + SIGNAL niOi100ii : STD_LOGIC; + SIGNAL niOi100il : STD_LOGIC; + SIGNAL niOi100iO : STD_LOGIC; + SIGNAL niOi100li : STD_LOGIC; + SIGNAL niOi100ll : STD_LOGIC; + SIGNAL niOi100lO : STD_LOGIC; + SIGNAL niOi100Oi : STD_LOGIC; + SIGNAL niOi100Ol : STD_LOGIC; + SIGNAL niOi100OO : STD_LOGIC; + SIGNAL niOi1010i : STD_LOGIC; + SIGNAL niOi1010l : STD_LOGIC; + SIGNAL niOi1010O : STD_LOGIC; + SIGNAL niOi1011i : STD_LOGIC; + SIGNAL niOi1011l : STD_LOGIC; + SIGNAL niOi1011O : STD_LOGIC; + SIGNAL niOi101ii : STD_LOGIC; + SIGNAL niOi101il : STD_LOGIC; + SIGNAL niOi101iO : STD_LOGIC; + SIGNAL niOi101li : STD_LOGIC; + SIGNAL niOi101ll : STD_LOGIC; + SIGNAL niOi101lO : STD_LOGIC; + SIGNAL niOi101Oi : STD_LOGIC; + SIGNAL niOi101Ol : STD_LOGIC; + SIGNAL niOi101OO : STD_LOGIC; + SIGNAL niOi10i0i : STD_LOGIC; + SIGNAL niOi10i0l : STD_LOGIC; + SIGNAL niOi10i0O : STD_LOGIC; + SIGNAL niOi10i1i : STD_LOGIC; + SIGNAL niOi10i1l : STD_LOGIC; + SIGNAL niOi10i1O : STD_LOGIC; + SIGNAL niOi10iii : STD_LOGIC; + SIGNAL niOi10iil : STD_LOGIC; + SIGNAL niOi10iiO : STD_LOGIC; + SIGNAL niOi10ili : STD_LOGIC; + SIGNAL niOi10ill : STD_LOGIC; + SIGNAL niOi10ilO : STD_LOGIC; + SIGNAL niOi10iOi : STD_LOGIC; + SIGNAL niOi10iOl : STD_LOGIC; + SIGNAL niOi10iOO : STD_LOGIC; + SIGNAL niOi10l0i : STD_LOGIC; + SIGNAL niOi10l0l : STD_LOGIC; + SIGNAL niOi10l0O : STD_LOGIC; + SIGNAL niOi10l1i : STD_LOGIC; + SIGNAL niOi10l1l : STD_LOGIC; + SIGNAL niOi10l1O : STD_LOGIC; + SIGNAL niOi10lii : STD_LOGIC; + SIGNAL niOi10lil : STD_LOGIC; + SIGNAL niOi10liO : STD_LOGIC; + SIGNAL niOi10lli : STD_LOGIC; + SIGNAL niOi10lll : STD_LOGIC; + SIGNAL niOi10llO : STD_LOGIC; + SIGNAL niOi10lOi : STD_LOGIC; + SIGNAL niOi10lOl : STD_LOGIC; + SIGNAL niOi10lOO : STD_LOGIC; + SIGNAL niOi10O0i : STD_LOGIC; + SIGNAL niOi10O0l : STD_LOGIC; + SIGNAL niOi10O0O : STD_LOGIC; + SIGNAL niOi10O1i : STD_LOGIC; + SIGNAL niOi10O1l : STD_LOGIC; + SIGNAL niOi10O1O : STD_LOGIC; + SIGNAL niOi10Oii : STD_LOGIC; + SIGNAL niOi10Oil : STD_LOGIC; + SIGNAL niOi10OiO : STD_LOGIC; + SIGNAL niOi10Oli : STD_LOGIC; + SIGNAL niOi10Oll : STD_LOGIC; + SIGNAL niOi10OlO : STD_LOGIC; + SIGNAL niOi10OOi : STD_LOGIC; + SIGNAL niOi10OOl : STD_LOGIC; + SIGNAL niOi10OOO : STD_LOGIC; + SIGNAL niOi11ill : STD_LOGIC; + SIGNAL niOi11ilO : STD_LOGIC; + SIGNAL niOi11iOi : STD_LOGIC; + SIGNAL niOi11iOl : STD_LOGIC; + SIGNAL niOi11iOO : STD_LOGIC; + SIGNAL niOi11l0i : STD_LOGIC; + SIGNAL niOi11l0l : STD_LOGIC; + SIGNAL niOi11l0O : STD_LOGIC; + SIGNAL niOi11l1i : STD_LOGIC; + SIGNAL niOi11l1l : STD_LOGIC; + SIGNAL niOi11l1O : STD_LOGIC; + SIGNAL niOi11lii : STD_LOGIC; + SIGNAL niOi11lil : STD_LOGIC; + SIGNAL niOi11liO : STD_LOGIC; + SIGNAL niOi11lli : STD_LOGIC; + SIGNAL niOi11lll : STD_LOGIC; + SIGNAL niOi11llO : STD_LOGIC; + SIGNAL niOi11lOi : STD_LOGIC; + SIGNAL niOi11lOl : STD_LOGIC; + SIGNAL niOi11lOO : STD_LOGIC; + SIGNAL niOi11O0i : STD_LOGIC; + SIGNAL niOi11O0l : STD_LOGIC; + SIGNAL niOi11O0O : STD_LOGIC; + SIGNAL niOi11O1i : STD_LOGIC; + SIGNAL niOi11O1l : STD_LOGIC; + SIGNAL niOi11O1O : STD_LOGIC; + SIGNAL niOi11Oii : STD_LOGIC; + SIGNAL niOi11Oil : STD_LOGIC; + SIGNAL niOi11OiO : STD_LOGIC; + SIGNAL niOi11Oli : STD_LOGIC; + SIGNAL niOi11Oll : STD_LOGIC; + SIGNAL niOi11OlO : STD_LOGIC; + SIGNAL niOi11OOi : STD_LOGIC; + SIGNAL niOi11OOl : STD_LOGIC; + SIGNAL niOi11OOO : STD_LOGIC; + SIGNAL niOi1i00i : STD_LOGIC; + SIGNAL niOi1i00l : STD_LOGIC; + SIGNAL niOi1i00O : STD_LOGIC; + SIGNAL niOi1i01i : STD_LOGIC; + SIGNAL niOi1i01l : STD_LOGIC; + SIGNAL niOi1i01O : STD_LOGIC; + SIGNAL niOi1i0ii : STD_LOGIC; + SIGNAL niOi1i0il : STD_LOGIC; + SIGNAL niOi1i0iO : STD_LOGIC; + SIGNAL niOi1i0li : STD_LOGIC; + SIGNAL niOi1i0ll : STD_LOGIC; + SIGNAL niOi1i0lO : STD_LOGIC; + SIGNAL niOi1i0Oi : STD_LOGIC; + SIGNAL niOi1i0Ol : STD_LOGIC; + SIGNAL niOi1i0OO : STD_LOGIC; + SIGNAL niOi1i10i : STD_LOGIC; + SIGNAL niOi1i10l : STD_LOGIC; + SIGNAL niOi1i10O : STD_LOGIC; + SIGNAL niOi1i11i : STD_LOGIC; + SIGNAL niOi1i11l : STD_LOGIC; + SIGNAL niOi1i11O : STD_LOGIC; + SIGNAL niOi1i1ii : STD_LOGIC; + SIGNAL niOi1i1il : STD_LOGIC; + SIGNAL niOi1i1iO : STD_LOGIC; + SIGNAL niOi1i1li : STD_LOGIC; + SIGNAL niOi1i1ll : STD_LOGIC; + SIGNAL niOi1i1lO : STD_LOGIC; + SIGNAL niOi1i1Oi : STD_LOGIC; + SIGNAL niOi1i1Ol : STD_LOGIC; + SIGNAL niOi1i1OO : STD_LOGIC; + SIGNAL niOi1ii0i : STD_LOGIC; + SIGNAL niOi1ii0l : STD_LOGIC; + SIGNAL niOi1ii0O : STD_LOGIC; + SIGNAL niOi1ii1i : STD_LOGIC; + SIGNAL niOi1ii1l : STD_LOGIC; + SIGNAL niOi1ii1O : STD_LOGIC; + SIGNAL niOi1iiii : STD_LOGIC; + SIGNAL niOi1iiil : STD_LOGIC; + SIGNAL niOi1iiiO : STD_LOGIC; + SIGNAL niOi1iili : STD_LOGIC; + SIGNAL niOi1iill : STD_LOGIC; + SIGNAL niOi1iilO : STD_LOGIC; + SIGNAL niOi1iiOi : STD_LOGIC; + SIGNAL niOi1iiOl : STD_LOGIC; + SIGNAL niOi1iiOO : STD_LOGIC; + SIGNAL niOi1il0i : STD_LOGIC; + SIGNAL niOi1il0l : STD_LOGIC; + SIGNAL niOi1il0O : STD_LOGIC; + SIGNAL niOi1il1i : STD_LOGIC; + SIGNAL niOi1il1l : STD_LOGIC; + SIGNAL niOi1il1O : STD_LOGIC; + SIGNAL niOi1ilii : STD_LOGIC; + SIGNAL niOi1ilil : STD_LOGIC; + SIGNAL niOi1iliO : STD_LOGIC; + SIGNAL niOi1illi : STD_LOGIC; + SIGNAL niOi1illl : STD_LOGIC; + SIGNAL niOi1illO : STD_LOGIC; + SIGNAL niOi1ilOi : STD_LOGIC; + SIGNAL niOi1ilOl : STD_LOGIC; + SIGNAL niOi1ilOO : STD_LOGIC; + SIGNAL niOi1iO0i : STD_LOGIC; + SIGNAL niOi1iO0l : STD_LOGIC; + SIGNAL niOi1iO0O : STD_LOGIC; + SIGNAL niOi1iO1i : STD_LOGIC; + SIGNAL niOi1iO1l : STD_LOGIC; + SIGNAL niOi1iO1O : STD_LOGIC; + SIGNAL niOi1iOii : STD_LOGIC; + SIGNAL niOi1iOil : STD_LOGIC; + SIGNAL niOi1iOiO : STD_LOGIC; + SIGNAL niOi1iOli : STD_LOGIC; + SIGNAL niOi1iOll : STD_LOGIC; + SIGNAL niOi1iOlO : STD_LOGIC; + SIGNAL niOi1iOOi : STD_LOGIC; + SIGNAL niOi1iOOl : STD_LOGIC; + SIGNAL niOi1iOOO : STD_LOGIC; + SIGNAL niOi1l00i : STD_LOGIC; + SIGNAL niOi1l00l : STD_LOGIC; + SIGNAL niOi1l00O : STD_LOGIC; + SIGNAL niOi1l01i : STD_LOGIC; + SIGNAL niOi1l01l : STD_LOGIC; + SIGNAL niOi1l01O : STD_LOGIC; + SIGNAL niOi1l0ii : STD_LOGIC; + SIGNAL niOi1l0il : STD_LOGIC; + SIGNAL niOi1l0iO : STD_LOGIC; + SIGNAL niOi1l0li : STD_LOGIC; + SIGNAL niOi1l0ll : STD_LOGIC; + SIGNAL niOi1l0lO : STD_LOGIC; + SIGNAL niOi1l0Oi : STD_LOGIC; + SIGNAL niOi1l0Ol : STD_LOGIC; + SIGNAL niOi1l0OO : STD_LOGIC; + SIGNAL niOi1l10i : STD_LOGIC; + SIGNAL niOi1l10l : STD_LOGIC; + SIGNAL niOi1l10O : STD_LOGIC; + SIGNAL niOi1l11i : STD_LOGIC; + SIGNAL niOi1l11l : STD_LOGIC; + SIGNAL niOi1l11O : STD_LOGIC; + SIGNAL niOi1l1ii : STD_LOGIC; + SIGNAL niOi1l1il : STD_LOGIC; + SIGNAL niOi1l1iO : STD_LOGIC; + SIGNAL niOi1l1li : STD_LOGIC; + SIGNAL niOi1l1ll : STD_LOGIC; + SIGNAL niOi1l1lO : STD_LOGIC; + SIGNAL niOi1l1Oi : STD_LOGIC; + SIGNAL niOi1l1Ol : STD_LOGIC; + SIGNAL niOi1l1OO : STD_LOGIC; + SIGNAL niOi1li0i : STD_LOGIC; + SIGNAL niOi1li0l : STD_LOGIC; + SIGNAL niOi1li0O : STD_LOGIC; + SIGNAL niOi1li1i : STD_LOGIC; + SIGNAL niOi1li1l : STD_LOGIC; + SIGNAL niOi1li1O : STD_LOGIC; + SIGNAL niOi1liii : STD_LOGIC; + SIGNAL niOi1liil : STD_LOGIC; + SIGNAL niOi1liiO : STD_LOGIC; + SIGNAL niOi1lili : STD_LOGIC; + SIGNAL niOi1lill : STD_LOGIC; + SIGNAL niOi1lilO : STD_LOGIC; + SIGNAL niOi1liOi : STD_LOGIC; + SIGNAL niOi1liOl : STD_LOGIC; + SIGNAL niOi1liOO : STD_LOGIC; + SIGNAL niOi1ll0i : STD_LOGIC; + SIGNAL niOi1ll0l : STD_LOGIC; + SIGNAL niOi1ll0O : STD_LOGIC; + SIGNAL niOi1ll1i : STD_LOGIC; + SIGNAL niOi1ll1l : STD_LOGIC; + SIGNAL niOi1ll1O : STD_LOGIC; + SIGNAL niOi1llii : STD_LOGIC; + SIGNAL niOi1llil : STD_LOGIC; + SIGNAL niOi1lliO : STD_LOGIC; + SIGNAL niOi1llli : STD_LOGIC; + SIGNAL niOi1llll : STD_LOGIC; + SIGNAL niOi1lllO : STD_LOGIC; + SIGNAL niOi1llOi : STD_LOGIC; + SIGNAL niOi1llOl : STD_LOGIC; + SIGNAL niOi1llOO : STD_LOGIC; + SIGNAL niOi1lO0i : STD_LOGIC; + SIGNAL niOi1lO0l : STD_LOGIC; + SIGNAL niOi1lO0O : STD_LOGIC; + SIGNAL niOi1lO1i : STD_LOGIC; + SIGNAL niOi1lO1l : STD_LOGIC; + SIGNAL niOi1lO1O : STD_LOGIC; + SIGNAL niOi1lOii : STD_LOGIC; + SIGNAL niOi1lOil : STD_LOGIC; + SIGNAL niOi1lOiO : STD_LOGIC; + SIGNAL niOi1lOli : STD_LOGIC; + SIGNAL niOi1lOll : STD_LOGIC; + SIGNAL niOi1lOlO : STD_LOGIC; + SIGNAL niOi1lOOi : STD_LOGIC; + SIGNAL niOi1lOOl : STD_LOGIC; + SIGNAL niOi1lOOO : STD_LOGIC; + SIGNAL niOi1O00i : STD_LOGIC; + SIGNAL niOi1O00l : STD_LOGIC; + SIGNAL niOi1O00O : STD_LOGIC; + SIGNAL niOi1O01i : STD_LOGIC; + SIGNAL niOi1O01l : STD_LOGIC; + SIGNAL niOi1O01O : STD_LOGIC; + SIGNAL niOi1O0ii : STD_LOGIC; + SIGNAL niOi1O0il : STD_LOGIC; + SIGNAL niOi1O0iO : STD_LOGIC; + SIGNAL niOi1O0li : STD_LOGIC; + SIGNAL niOi1O0ll : STD_LOGIC; + SIGNAL niOi1O0lO : STD_LOGIC; + SIGNAL niOi1O0Oi : STD_LOGIC; + SIGNAL niOi1O0Ol : STD_LOGIC; + SIGNAL niOi1O0OO : STD_LOGIC; + SIGNAL niOi1O10i : STD_LOGIC; + SIGNAL niOi1O10l : STD_LOGIC; + SIGNAL niOi1O10O : STD_LOGIC; + SIGNAL niOi1O11i : STD_LOGIC; + SIGNAL niOi1O11l : STD_LOGIC; + SIGNAL niOi1O11O : STD_LOGIC; + SIGNAL niOi1O1ii : STD_LOGIC; + SIGNAL niOi1O1il : STD_LOGIC; + SIGNAL niOi1O1iO : STD_LOGIC; + SIGNAL niOi1O1li : STD_LOGIC; + SIGNAL niOi1O1ll : STD_LOGIC; + SIGNAL niOi1O1lO : STD_LOGIC; + SIGNAL niOi1O1Oi : STD_LOGIC; + SIGNAL niOi1O1Ol : STD_LOGIC; + SIGNAL niOi1O1OO : STD_LOGIC; + SIGNAL niOi1Oi0i : STD_LOGIC; + SIGNAL niOi1Oi0l : STD_LOGIC; + SIGNAL niOi1Oi0O : STD_LOGIC; + SIGNAL niOi1Oi1i : STD_LOGIC; + SIGNAL niOi1Oi1l : STD_LOGIC; + SIGNAL niOi1Oi1O : STD_LOGIC; + SIGNAL niOi1Oiii : STD_LOGIC; + SIGNAL niOi1Oiil : STD_LOGIC; + SIGNAL niOi1OiiO : STD_LOGIC; + SIGNAL niOi1Oili : STD_LOGIC; + SIGNAL niOi1Oill : STD_LOGIC; + SIGNAL niOi1OilO : STD_LOGIC; + SIGNAL niOi1OiOi : STD_LOGIC; + SIGNAL niOi1OiOl : STD_LOGIC; + SIGNAL niOi1OiOO : STD_LOGIC; + SIGNAL niOi1Ol0i : STD_LOGIC; + SIGNAL niOi1Ol0l : STD_LOGIC; + SIGNAL niOi1Ol0O : STD_LOGIC; + SIGNAL niOi1Ol1i : STD_LOGIC; + SIGNAL niOi1Ol1l : STD_LOGIC; + SIGNAL niOi1Ol1O : STD_LOGIC; + SIGNAL niOi1Olii : STD_LOGIC; + SIGNAL niOi1Olil : STD_LOGIC; + SIGNAL niOi1OliO : STD_LOGIC; + SIGNAL niOi1Olli : STD_LOGIC; + SIGNAL niOi1Olll : STD_LOGIC; + SIGNAL niOi1OllO : STD_LOGIC; + SIGNAL niOi1OlOi : STD_LOGIC; + SIGNAL niOi1OlOl : STD_LOGIC; + SIGNAL niOi1OlOO : STD_LOGIC; + SIGNAL niOi1OO0i : STD_LOGIC; + SIGNAL niOi1OO0l : STD_LOGIC; + SIGNAL niOi1OO0O : STD_LOGIC; + SIGNAL niOi1OO1i : STD_LOGIC; + SIGNAL niOi1OO1l : STD_LOGIC; + SIGNAL niOi1OO1O : STD_LOGIC; + SIGNAL niOi1OOii : STD_LOGIC; + SIGNAL niOi1OOil : STD_LOGIC; + SIGNAL niOi1OOiO : STD_LOGIC; + SIGNAL niOi1OOli : STD_LOGIC; + SIGNAL niOi1OOll : STD_LOGIC; + SIGNAL niOi1OOlO : STD_LOGIC; + SIGNAL niOi1OOOi : STD_LOGIC; + SIGNAL niOi1OOOl : STD_LOGIC; + SIGNAL niOi1OOOO : STD_LOGIC; + SIGNAL niOii000i : STD_LOGIC; + SIGNAL niOii000l : STD_LOGIC; + SIGNAL niOii000O : STD_LOGIC; + SIGNAL niOii001i : STD_LOGIC; + SIGNAL niOii001l : STD_LOGIC; + SIGNAL niOii001O : STD_LOGIC; + SIGNAL niOii00ii : STD_LOGIC; + SIGNAL niOii00il : STD_LOGIC; + SIGNAL niOii00iO : STD_LOGIC; + SIGNAL niOii00li : STD_LOGIC; + SIGNAL niOii00ll : STD_LOGIC; + SIGNAL niOii00lO : STD_LOGIC; + SIGNAL niOii00Oi : STD_LOGIC; + SIGNAL niOii00Ol : STD_LOGIC; + SIGNAL niOii00OO : STD_LOGIC; + SIGNAL niOii010i : STD_LOGIC; + SIGNAL niOii010l : STD_LOGIC; + SIGNAL niOii010O : STD_LOGIC; + SIGNAL niOii011i : STD_LOGIC; + SIGNAL niOii011l : STD_LOGIC; + SIGNAL niOii011O : STD_LOGIC; + SIGNAL niOii01ii : STD_LOGIC; + SIGNAL niOii01il : STD_LOGIC; + SIGNAL niOii01iO : STD_LOGIC; + SIGNAL niOii01li : STD_LOGIC; + SIGNAL niOii01ll : STD_LOGIC; + SIGNAL niOii01lO : STD_LOGIC; + SIGNAL niOii01Oi : STD_LOGIC; + SIGNAL niOii01Ol : STD_LOGIC; + SIGNAL niOii01OO : STD_LOGIC; + SIGNAL niOii0i0i : STD_LOGIC; + SIGNAL niOii0i0l : STD_LOGIC; + SIGNAL niOii0i0O : STD_LOGIC; + SIGNAL niOii0i1i : STD_LOGIC; + SIGNAL niOii0i1l : STD_LOGIC; + SIGNAL niOii0i1O : STD_LOGIC; + SIGNAL niOii0iii : STD_LOGIC; + SIGNAL niOii0iil : STD_LOGIC; + SIGNAL niOii0iiO : STD_LOGIC; + SIGNAL niOii0ili : STD_LOGIC; + SIGNAL niOii0ill : STD_LOGIC; + SIGNAL niOii0ilO : STD_LOGIC; + SIGNAL niOii0iOi : STD_LOGIC; + SIGNAL niOii0iOl : STD_LOGIC; + SIGNAL niOii0iOO : STD_LOGIC; + SIGNAL niOii0l0i : STD_LOGIC; + SIGNAL niOii0l0l : STD_LOGIC; + SIGNAL niOii0l0O : STD_LOGIC; + SIGNAL niOii0l1i : STD_LOGIC; + SIGNAL niOii0l1l : STD_LOGIC; + SIGNAL niOii0l1O : STD_LOGIC; + SIGNAL niOii0lii : STD_LOGIC; + SIGNAL niOii0lil : STD_LOGIC; + SIGNAL niOii0liO : STD_LOGIC; + SIGNAL niOii0lli : STD_LOGIC; + SIGNAL niOii0lll : STD_LOGIC; + SIGNAL niOii0llO : STD_LOGIC; + SIGNAL niOii0lOi : STD_LOGIC; + SIGNAL niOii0lOl : STD_LOGIC; + SIGNAL niOii0lOO : STD_LOGIC; + SIGNAL niOii0O0i : STD_LOGIC; + SIGNAL niOii0O0l : STD_LOGIC; + SIGNAL niOii0O0O : STD_LOGIC; + SIGNAL niOii0O1i : STD_LOGIC; + SIGNAL niOii0O1l : STD_LOGIC; + SIGNAL niOii0O1O : STD_LOGIC; + SIGNAL niOii0Oii : STD_LOGIC; + SIGNAL niOii0Oil : STD_LOGIC; + SIGNAL niOii0OiO : STD_LOGIC; + SIGNAL niOii0Oli : STD_LOGIC; + SIGNAL niOii0Oll : STD_LOGIC; + SIGNAL niOii0OlO : STD_LOGIC; + SIGNAL niOii0OOi : STD_LOGIC; + SIGNAL niOii0OOl : STD_LOGIC; + SIGNAL niOii0OOO : STD_LOGIC; + SIGNAL niOii100i : STD_LOGIC; + SIGNAL niOii100l : STD_LOGIC; + SIGNAL niOii100O : STD_LOGIC; + SIGNAL niOii101i : STD_LOGIC; + SIGNAL niOii101l : STD_LOGIC; + SIGNAL niOii101O : STD_LOGIC; + SIGNAL niOii10ii : STD_LOGIC; + SIGNAL niOii10il : STD_LOGIC; + SIGNAL niOii10iO : STD_LOGIC; + SIGNAL niOii10li : STD_LOGIC; + SIGNAL niOii10ll : STD_LOGIC; + SIGNAL niOii10lO : STD_LOGIC; + SIGNAL niOii10Oi : STD_LOGIC; + SIGNAL niOii10Ol : STD_LOGIC; + SIGNAL niOii10OO : STD_LOGIC; + SIGNAL niOii110i : STD_LOGIC; + SIGNAL niOii110l : STD_LOGIC; + SIGNAL niOii110O : STD_LOGIC; + SIGNAL niOii111i : STD_LOGIC; + SIGNAL niOii111l : STD_LOGIC; + SIGNAL niOii111O : STD_LOGIC; + SIGNAL niOii11ii : STD_LOGIC; + SIGNAL niOii11il : STD_LOGIC; + SIGNAL niOii11iO : STD_LOGIC; + SIGNAL niOii11li : STD_LOGIC; + SIGNAL niOii11ll : STD_LOGIC; + SIGNAL niOii11lO : STD_LOGIC; + SIGNAL niOii11Oi : STD_LOGIC; + SIGNAL niOii11Ol : STD_LOGIC; + SIGNAL niOii11OO : STD_LOGIC; + SIGNAL niOii1i0i : STD_LOGIC; + SIGNAL niOii1i0l : STD_LOGIC; + SIGNAL niOii1i0O : STD_LOGIC; + SIGNAL niOii1i1i : STD_LOGIC; + SIGNAL niOii1i1l : STD_LOGIC; + SIGNAL niOii1i1O : STD_LOGIC; + SIGNAL niOii1iii : STD_LOGIC; + SIGNAL niOii1iil : STD_LOGIC; + SIGNAL niOii1iiO : STD_LOGIC; + SIGNAL niOii1ili : STD_LOGIC; + SIGNAL niOii1ill : STD_LOGIC; + SIGNAL niOii1ilO : STD_LOGIC; + SIGNAL niOii1iOi : STD_LOGIC; + SIGNAL niOii1iOl : STD_LOGIC; + SIGNAL niOii1iOO : STD_LOGIC; + SIGNAL niOii1l0i : STD_LOGIC; + SIGNAL niOii1l0l : STD_LOGIC; + SIGNAL niOii1l0O : STD_LOGIC; + SIGNAL niOii1l1i : STD_LOGIC; + SIGNAL niOii1l1l : STD_LOGIC; + SIGNAL niOii1l1O : STD_LOGIC; + SIGNAL niOii1lii : STD_LOGIC; + SIGNAL niOii1lil : STD_LOGIC; + SIGNAL niOii1liO : STD_LOGIC; + SIGNAL niOii1lli : STD_LOGIC; + SIGNAL niOii1lll : STD_LOGIC; + SIGNAL niOii1llO : STD_LOGIC; + SIGNAL niOii1lOi : STD_LOGIC; + SIGNAL niOii1lOl : STD_LOGIC; + SIGNAL niOii1lOO : STD_LOGIC; + SIGNAL niOii1O0i : STD_LOGIC; + SIGNAL niOii1O0l : STD_LOGIC; + SIGNAL niOii1O0O : STD_LOGIC; + SIGNAL niOii1O1i : STD_LOGIC; + SIGNAL niOii1O1l : STD_LOGIC; + SIGNAL niOii1O1O : STD_LOGIC; + SIGNAL niOii1Oii : STD_LOGIC; + SIGNAL niOii1Oil : STD_LOGIC; + SIGNAL niOii1OiO : STD_LOGIC; + SIGNAL niOii1Oli : STD_LOGIC; + SIGNAL niOii1Oll : STD_LOGIC; + SIGNAL niOii1OlO : STD_LOGIC; + SIGNAL niOii1OOi : STD_LOGIC; + SIGNAL niOii1OOl : STD_LOGIC; + SIGNAL niOii1OOO : STD_LOGIC; + SIGNAL niOiii00i : STD_LOGIC; + SIGNAL niOiii00l : STD_LOGIC; + SIGNAL niOiii00O : STD_LOGIC; + SIGNAL niOiii01i : STD_LOGIC; + SIGNAL niOiii01l : STD_LOGIC; + SIGNAL niOiii01O : STD_LOGIC; + SIGNAL niOiii0ii : STD_LOGIC; + SIGNAL niOiii0il : STD_LOGIC; + SIGNAL niOiii0iO : STD_LOGIC; + SIGNAL niOiii0li : STD_LOGIC; + SIGNAL niOiii0ll : STD_LOGIC; + SIGNAL niOiii0lO : STD_LOGIC; + SIGNAL niOiii0Oi : STD_LOGIC; + SIGNAL niOiii0Ol : STD_LOGIC; + SIGNAL niOiii0OO : STD_LOGIC; + SIGNAL niOiii10i : STD_LOGIC; + SIGNAL niOiii10l : STD_LOGIC; + SIGNAL niOiii10O : STD_LOGIC; + SIGNAL niOiii11i : STD_LOGIC; + SIGNAL niOiii11l : STD_LOGIC; + SIGNAL niOiii11O : STD_LOGIC; + SIGNAL niOiii1ii : STD_LOGIC; + SIGNAL niOiii1il : STD_LOGIC; + SIGNAL niOiii1iO : STD_LOGIC; + SIGNAL niOiii1li : STD_LOGIC; + SIGNAL niOiii1ll : STD_LOGIC; + SIGNAL niOiii1lO : STD_LOGIC; + SIGNAL niOiii1Oi : STD_LOGIC; + SIGNAL niOiii1Ol : STD_LOGIC; + SIGNAL niOiii1OO : STD_LOGIC; + SIGNAL niOiiii0i : STD_LOGIC; + SIGNAL niOiiii0l : STD_LOGIC; + SIGNAL niOiiii0O : STD_LOGIC; + SIGNAL niOiiii1i : STD_LOGIC; + SIGNAL niOiiii1l : STD_LOGIC; + SIGNAL niOiiii1O : STD_LOGIC; + SIGNAL niOiiiiii : STD_LOGIC; + SIGNAL niOiiiiil : STD_LOGIC; + SIGNAL niOiiiiiO : STD_LOGIC; + SIGNAL niOiiiili : STD_LOGIC; + SIGNAL niOiiiill : STD_LOGIC; + SIGNAL niOiiiilO : STD_LOGIC; + SIGNAL niOiiiiOi : STD_LOGIC; + SIGNAL niOiiiiOl : STD_LOGIC; + SIGNAL niOiiiiOO : STD_LOGIC; + SIGNAL niOiiil0i : STD_LOGIC; + SIGNAL niOiiil0l : STD_LOGIC; + SIGNAL niOiiil0O : STD_LOGIC; + SIGNAL niOiiil1i : STD_LOGIC; + SIGNAL niOiiil1l : STD_LOGIC; + SIGNAL niOiiil1O : STD_LOGIC; + SIGNAL niOiiilii : STD_LOGIC; + SIGNAL niOiiilil : STD_LOGIC; + SIGNAL niOiiiliO : STD_LOGIC; + SIGNAL niOiiilli : STD_LOGIC; + SIGNAL niOiiilll : STD_LOGIC; + SIGNAL niOiiillO : STD_LOGIC; + SIGNAL niOiiilOi : STD_LOGIC; + SIGNAL niOiiilOl : STD_LOGIC; + SIGNAL niOiiilOO : STD_LOGIC; + SIGNAL niOiiiO0i : STD_LOGIC; + SIGNAL niOiiiO0l : STD_LOGIC; + SIGNAL niOiiiO0O : STD_LOGIC; + SIGNAL niOiiiO1i : STD_LOGIC; + SIGNAL niOiiiO1l : STD_LOGIC; + SIGNAL niOiiiO1O : STD_LOGIC; + SIGNAL niOiiiOii : STD_LOGIC; + SIGNAL niOiiiOil : STD_LOGIC; + SIGNAL niOiiiOiO : STD_LOGIC; + SIGNAL niOiiiOli : STD_LOGIC; + SIGNAL niOiiiOll : STD_LOGIC; + SIGNAL niOiiiOlO : STD_LOGIC; + SIGNAL niOiiiOOi : STD_LOGIC; + SIGNAL niOiiiOOl : STD_LOGIC; + SIGNAL niOiiiOOO : STD_LOGIC; + SIGNAL niOiil00i : STD_LOGIC; + SIGNAL niOiil00l : STD_LOGIC; + SIGNAL niOiil00O : STD_LOGIC; + SIGNAL niOiil01i : STD_LOGIC; + SIGNAL niOiil01l : STD_LOGIC; + SIGNAL niOiil01O : STD_LOGIC; + SIGNAL niOiil0ii : STD_LOGIC; + SIGNAL niOiil0il : STD_LOGIC; + SIGNAL niOiil0iO : STD_LOGIC; + SIGNAL niOiil0li : STD_LOGIC; + SIGNAL niOiil0ll : STD_LOGIC; + SIGNAL niOiil0lO : STD_LOGIC; + SIGNAL niOiil0Oi : STD_LOGIC; + SIGNAL niOiil0Ol : STD_LOGIC; + SIGNAL niOiil0OO : STD_LOGIC; + SIGNAL niOiil10i : STD_LOGIC; + SIGNAL niOiil10l : STD_LOGIC; + SIGNAL niOiil10O : STD_LOGIC; + SIGNAL niOiil11i : STD_LOGIC; + SIGNAL niOiil11l : STD_LOGIC; + SIGNAL niOiil11O : STD_LOGIC; + SIGNAL niOiil1ii : STD_LOGIC; + SIGNAL niOiil1il : STD_LOGIC; + SIGNAL niOiil1iO : STD_LOGIC; + SIGNAL niOiil1li : STD_LOGIC; + SIGNAL niOiil1ll : STD_LOGIC; + SIGNAL niOiil1lO : STD_LOGIC; + SIGNAL niOiil1Oi : STD_LOGIC; + SIGNAL niOiil1Ol : STD_LOGIC; + SIGNAL niOiil1OO : STD_LOGIC; + SIGNAL niOiili0i : STD_LOGIC; + SIGNAL niOiili0l : STD_LOGIC; + SIGNAL niOiili0O : STD_LOGIC; + SIGNAL niOiili1i : STD_LOGIC; + SIGNAL niOiili1l : STD_LOGIC; + SIGNAL niOiili1O : STD_LOGIC; + SIGNAL niOiiliii : STD_LOGIC; + SIGNAL niOiiliil : STD_LOGIC; + SIGNAL niOiiliiO : STD_LOGIC; + SIGNAL niOiilili : STD_LOGIC; + SIGNAL niOiilill : STD_LOGIC; + SIGNAL niOiililO : STD_LOGIC; + SIGNAL niOiiliOi : STD_LOGIC; + SIGNAL niOiiliOl : STD_LOGIC; + SIGNAL niOiiliOO : STD_LOGIC; + SIGNAL niOiill0i : STD_LOGIC; + SIGNAL niOiill0l : STD_LOGIC; + SIGNAL niOiill0O : STD_LOGIC; + SIGNAL niOiill1i : STD_LOGIC; + SIGNAL niOiill1l : STD_LOGIC; + SIGNAL niOiill1O : STD_LOGIC; + SIGNAL niOiillii : STD_LOGIC; + SIGNAL niOiillil : STD_LOGIC; + SIGNAL niOiilliO : STD_LOGIC; + SIGNAL niOiillli : STD_LOGIC; + SIGNAL niOiillll : STD_LOGIC; + SIGNAL niOiilllO : STD_LOGIC; + SIGNAL niOiillOi : STD_LOGIC; + SIGNAL niOiillOl : STD_LOGIC; + SIGNAL niOiillOO : STD_LOGIC; + SIGNAL niOiilO0i : STD_LOGIC; + SIGNAL niOiilO0l : STD_LOGIC; + SIGNAL niOiilO0O : STD_LOGIC; + SIGNAL niOiilO1i : STD_LOGIC; + SIGNAL niOiilO1l : STD_LOGIC; + SIGNAL niOiilO1O : STD_LOGIC; + SIGNAL niOiilOii : STD_LOGIC; + SIGNAL niOiilOil : STD_LOGIC; + SIGNAL niOiilOiO : STD_LOGIC; + SIGNAL niOiilOli : STD_LOGIC; + SIGNAL niOiilOll : STD_LOGIC; + SIGNAL niOiilOlO : STD_LOGIC; + SIGNAL niOiilOOi : STD_LOGIC; + SIGNAL niOiilOOl : STD_LOGIC; + SIGNAL niOiilOOO : STD_LOGIC; + SIGNAL niOiiO00i : STD_LOGIC; + SIGNAL niOiiO00l : STD_LOGIC; + SIGNAL niOiiO00O : STD_LOGIC; + SIGNAL niOiiO01i : STD_LOGIC; + SIGNAL niOiiO01l : STD_LOGIC; + SIGNAL niOiiO01O : STD_LOGIC; + SIGNAL niOiiO0ii : STD_LOGIC; + SIGNAL niOiiO0il : STD_LOGIC; + SIGNAL niOiiO0iO : STD_LOGIC; + SIGNAL niOiiO0li : STD_LOGIC; + SIGNAL niOiiO0ll : STD_LOGIC; + SIGNAL niOiiO0lO : STD_LOGIC; + SIGNAL niOiiO0Oi : STD_LOGIC; + SIGNAL niOiiO0Ol : STD_LOGIC; + SIGNAL niOiiO0OO : STD_LOGIC; + SIGNAL niOiiO10i : STD_LOGIC; + SIGNAL niOiiO10l : STD_LOGIC; + SIGNAL niOiiO10O : STD_LOGIC; + SIGNAL niOiiO11i : STD_LOGIC; + SIGNAL niOiiO11l : STD_LOGIC; + SIGNAL niOiiO11O : STD_LOGIC; + SIGNAL niOiiO1ii : STD_LOGIC; + SIGNAL niOiiO1il : STD_LOGIC; + SIGNAL niOiiO1iO : STD_LOGIC; + SIGNAL niOiiO1li : STD_LOGIC; + SIGNAL niOiiO1ll : STD_LOGIC; + SIGNAL niOiiO1lO : STD_LOGIC; + SIGNAL niOiiO1Oi : STD_LOGIC; + SIGNAL niOiiO1Ol : STD_LOGIC; + SIGNAL niOiiO1OO : STD_LOGIC; + SIGNAL niOiiOi0i : STD_LOGIC; + SIGNAL niOiiOi0l : STD_LOGIC; + SIGNAL niOiiOi0O : STD_LOGIC; + SIGNAL niOiiOi1i : STD_LOGIC; + SIGNAL niOiiOi1l : STD_LOGIC; + SIGNAL niOiiOi1O : STD_LOGIC; + SIGNAL niOiiOiii : STD_LOGIC; + SIGNAL niOiiOiil : STD_LOGIC; + SIGNAL niOiiOiiO : STD_LOGIC; + SIGNAL niOiiOili : STD_LOGIC; + SIGNAL niOiiOill : STD_LOGIC; + SIGNAL niOiiOilO : STD_LOGIC; + SIGNAL niOiiOiOi : STD_LOGIC; + SIGNAL niOiiOiOl : STD_LOGIC; + SIGNAL niOiiOiOO : STD_LOGIC; + SIGNAL niOiiOl0i : STD_LOGIC; + SIGNAL niOiiOl0l : STD_LOGIC; + SIGNAL niOiiOl0O : STD_LOGIC; + SIGNAL niOiiOl1i : STD_LOGIC; + SIGNAL niOiiOl1l : STD_LOGIC; + SIGNAL niOiiOl1O : STD_LOGIC; + SIGNAL niOiiOlii : STD_LOGIC; + SIGNAL niOiiOlil : STD_LOGIC; + SIGNAL niOiiOliO : STD_LOGIC; + SIGNAL niOiiOlli : STD_LOGIC; + SIGNAL niOiiOlll : STD_LOGIC; + SIGNAL niOiiOllO : STD_LOGIC; + SIGNAL niOiiOlOi : STD_LOGIC; + SIGNAL niOiiOlOl : STD_LOGIC; + SIGNAL niOiiOlOO : STD_LOGIC; + SIGNAL niOiiOO0i : STD_LOGIC; + SIGNAL niOiiOO0l : STD_LOGIC; + SIGNAL niOiiOO0O : STD_LOGIC; + SIGNAL niOiiOO1i : STD_LOGIC; + SIGNAL niOiiOO1l : STD_LOGIC; + SIGNAL niOiiOO1O : STD_LOGIC; + SIGNAL niOiiOOii : STD_LOGIC; + SIGNAL niOiiOOil : STD_LOGIC; + SIGNAL niOiiOOiO : STD_LOGIC; + SIGNAL niOiiOOli : STD_LOGIC; + SIGNAL niOiiOOll : STD_LOGIC; + SIGNAL niOiiOOlO : STD_LOGIC; + SIGNAL niOiiOOOi : STD_LOGIC; + SIGNAL niOiiOOOl : STD_LOGIC; + SIGNAL niOiiOOOO : STD_LOGIC; + SIGNAL niOil000i : STD_LOGIC; + SIGNAL niOil000l : STD_LOGIC; + SIGNAL niOil000O : STD_LOGIC; + SIGNAL niOil001i : STD_LOGIC; + SIGNAL niOil001l : STD_LOGIC; + SIGNAL niOil001O : STD_LOGIC; + SIGNAL niOil00ii : STD_LOGIC; + SIGNAL niOil00il : STD_LOGIC; + SIGNAL niOil00iO : STD_LOGIC; + SIGNAL niOil00li : STD_LOGIC; + SIGNAL niOil00ll : STD_LOGIC; + SIGNAL niOil00lO : STD_LOGIC; + SIGNAL niOil00Oi : STD_LOGIC; + SIGNAL niOil00Ol : STD_LOGIC; + SIGNAL niOil00OO : STD_LOGIC; + SIGNAL niOil010i : STD_LOGIC; + SIGNAL niOil010l : STD_LOGIC; + SIGNAL niOil010O : STD_LOGIC; + SIGNAL niOil011i : STD_LOGIC; + SIGNAL niOil011l : STD_LOGIC; + SIGNAL niOil011O : STD_LOGIC; + SIGNAL niOil01ii : STD_LOGIC; + SIGNAL niOil01il : STD_LOGIC; + SIGNAL niOil01iO : STD_LOGIC; + SIGNAL niOil01li : STD_LOGIC; + SIGNAL niOil01ll : STD_LOGIC; + SIGNAL niOil01lO : STD_LOGIC; + SIGNAL niOil01Oi : STD_LOGIC; + SIGNAL niOil01Ol : STD_LOGIC; + SIGNAL niOil01OO : STD_LOGIC; + SIGNAL niOil0i0i : STD_LOGIC; + SIGNAL niOil0i0l : STD_LOGIC; + SIGNAL niOil0i0O : STD_LOGIC; + SIGNAL niOil0i1i : STD_LOGIC; + SIGNAL niOil0i1l : STD_LOGIC; + SIGNAL niOil0i1O : STD_LOGIC; + SIGNAL niOil0iii : STD_LOGIC; + SIGNAL niOil0iil : STD_LOGIC; + SIGNAL niOil0iiO : STD_LOGIC; + SIGNAL niOil0ili : STD_LOGIC; + SIGNAL niOil0ill : STD_LOGIC; + SIGNAL niOil0ilO : STD_LOGIC; + SIGNAL niOil0iOi : STD_LOGIC; + SIGNAL niOil0iOl : STD_LOGIC; + SIGNAL niOil0iOO : STD_LOGIC; + SIGNAL niOil0l0i : STD_LOGIC; + SIGNAL niOil0l0l : STD_LOGIC; + SIGNAL niOil0l0O : STD_LOGIC; + SIGNAL niOil0l1i : STD_LOGIC; + SIGNAL niOil0l1l : STD_LOGIC; + SIGNAL niOil0l1O : STD_LOGIC; + SIGNAL niOil0lii : STD_LOGIC; + SIGNAL niOil0lil : STD_LOGIC; + SIGNAL niOil0liO : STD_LOGIC; + SIGNAL niOil0lli : STD_LOGIC; + SIGNAL niOil0lll : STD_LOGIC; + SIGNAL niOil0llO : STD_LOGIC; + SIGNAL niOil0lOi : STD_LOGIC; + SIGNAL niOil0lOl : STD_LOGIC; + SIGNAL niOil0lOO : STD_LOGIC; + SIGNAL niOil0O0i : STD_LOGIC; + SIGNAL niOil0O0l : STD_LOGIC; + SIGNAL niOil0O0O : STD_LOGIC; + SIGNAL niOil0O1i : STD_LOGIC; + SIGNAL niOil0O1l : STD_LOGIC; + SIGNAL niOil0O1O : STD_LOGIC; + SIGNAL niOil0Oii : STD_LOGIC; + SIGNAL niOil0Oil : STD_LOGIC; + SIGNAL niOil0OiO : STD_LOGIC; + SIGNAL niOil0Oli : STD_LOGIC; + SIGNAL niOil0Oll : STD_LOGIC; + SIGNAL niOil0OlO : STD_LOGIC; + SIGNAL niOil0OOi : STD_LOGIC; + SIGNAL niOil0OOl : STD_LOGIC; + SIGNAL niOil0OOO : STD_LOGIC; + SIGNAL niOil100i : STD_LOGIC; + SIGNAL niOil100l : STD_LOGIC; + SIGNAL niOil100O : STD_LOGIC; + SIGNAL niOil101i : STD_LOGIC; + SIGNAL niOil101l : STD_LOGIC; + SIGNAL niOil101O : STD_LOGIC; + SIGNAL niOil10ii : STD_LOGIC; + SIGNAL niOil10il : STD_LOGIC; + SIGNAL niOil10iO : STD_LOGIC; + SIGNAL niOil10li : STD_LOGIC; + SIGNAL niOil10ll : STD_LOGIC; + SIGNAL niOil10lO : STD_LOGIC; + SIGNAL niOil10Oi : STD_LOGIC; + SIGNAL niOil10Ol : STD_LOGIC; + SIGNAL niOil10OO : STD_LOGIC; + SIGNAL niOil110i : STD_LOGIC; + SIGNAL niOil110l : STD_LOGIC; + SIGNAL niOil110O : STD_LOGIC; + SIGNAL niOil111i : STD_LOGIC; + SIGNAL niOil111l : STD_LOGIC; + SIGNAL niOil111O : STD_LOGIC; + SIGNAL niOil11ii : STD_LOGIC; + SIGNAL niOil11il : STD_LOGIC; + SIGNAL niOil11iO : STD_LOGIC; + SIGNAL niOil11li : STD_LOGIC; + SIGNAL niOil11ll : STD_LOGIC; + SIGNAL niOil11lO : STD_LOGIC; + SIGNAL niOil11Oi : STD_LOGIC; + SIGNAL niOil11Ol : STD_LOGIC; + SIGNAL niOil11OO : STD_LOGIC; + SIGNAL niOil1i0i : STD_LOGIC; + SIGNAL niOil1i0l : STD_LOGIC; + SIGNAL niOil1i0O : STD_LOGIC; + SIGNAL niOil1i1i : STD_LOGIC; + SIGNAL niOil1i1l : STD_LOGIC; + SIGNAL niOil1i1O : STD_LOGIC; + SIGNAL niOil1iii : STD_LOGIC; + SIGNAL niOil1iil : STD_LOGIC; + SIGNAL niOil1iiO : STD_LOGIC; + SIGNAL niOil1ili : STD_LOGIC; + SIGNAL niOil1ill : STD_LOGIC; + SIGNAL niOil1ilO : STD_LOGIC; + SIGNAL niOil1iOi : STD_LOGIC; + SIGNAL niOil1iOl : STD_LOGIC; + SIGNAL niOil1iOO : STD_LOGIC; + SIGNAL niOil1l0i : STD_LOGIC; + SIGNAL niOil1l0l : STD_LOGIC; + SIGNAL niOil1l0O : STD_LOGIC; + SIGNAL niOil1l1i : STD_LOGIC; + SIGNAL niOil1l1l : STD_LOGIC; + SIGNAL niOil1l1O : STD_LOGIC; + SIGNAL niOil1lii : STD_LOGIC; + SIGNAL niOil1lil : STD_LOGIC; + SIGNAL niOil1liO : STD_LOGIC; + SIGNAL niOil1lli : STD_LOGIC; + SIGNAL niOil1lll : STD_LOGIC; + SIGNAL niOil1llO : STD_LOGIC; + SIGNAL niOil1lOi : STD_LOGIC; + SIGNAL niOil1lOl : STD_LOGIC; + SIGNAL niOil1lOO : STD_LOGIC; + SIGNAL niOil1O0i : STD_LOGIC; + SIGNAL niOil1O0l : STD_LOGIC; + SIGNAL niOil1O0O : STD_LOGIC; + SIGNAL niOil1O1i : STD_LOGIC; + SIGNAL niOil1O1l : STD_LOGIC; + SIGNAL niOil1O1O : STD_LOGIC; + SIGNAL niOil1Oii : STD_LOGIC; + SIGNAL niOil1Oil : STD_LOGIC; + SIGNAL niOil1OiO : STD_LOGIC; + SIGNAL niOil1Oli : STD_LOGIC; + SIGNAL niOil1Oll : STD_LOGIC; + SIGNAL niOil1OlO : STD_LOGIC; + SIGNAL niOil1OOi : STD_LOGIC; + SIGNAL niOil1OOl : STD_LOGIC; + SIGNAL niOil1OOO : STD_LOGIC; + SIGNAL niOili00i : STD_LOGIC; + SIGNAL niOili00l : STD_LOGIC; + SIGNAL niOili00O : STD_LOGIC; + SIGNAL niOili01i : STD_LOGIC; + SIGNAL niOili01l : STD_LOGIC; + SIGNAL niOili01O : STD_LOGIC; + SIGNAL niOili0ii : STD_LOGIC; + SIGNAL niOili0il : STD_LOGIC; + SIGNAL niOili0iO : STD_LOGIC; + SIGNAL niOili0li : STD_LOGIC; + SIGNAL niOili0ll : STD_LOGIC; + SIGNAL niOili0lO : STD_LOGIC; + SIGNAL niOili0Oi : STD_LOGIC; + SIGNAL niOili0Ol : STD_LOGIC; + SIGNAL niOili0OO : STD_LOGIC; + SIGNAL niOili10i : STD_LOGIC; + SIGNAL niOili10l : STD_LOGIC; + SIGNAL niOili10O : STD_LOGIC; + SIGNAL niOili11i : STD_LOGIC; + SIGNAL niOili11l : STD_LOGIC; + SIGNAL niOili11O : STD_LOGIC; + SIGNAL niOili1ii : STD_LOGIC; + SIGNAL niOili1il : STD_LOGIC; + SIGNAL niOili1iO : STD_LOGIC; + SIGNAL niOili1li : STD_LOGIC; + SIGNAL niOili1ll : STD_LOGIC; + SIGNAL niOili1lO : STD_LOGIC; + SIGNAL niOili1Oi : STD_LOGIC; + SIGNAL niOili1Ol : STD_LOGIC; + SIGNAL niOili1OO : STD_LOGIC; + SIGNAL niOilii0i : STD_LOGIC; + SIGNAL niOilii0l : STD_LOGIC; + SIGNAL niOilii0O : STD_LOGIC; + SIGNAL niOilii1i : STD_LOGIC; + SIGNAL niOilii1l : STD_LOGIC; + SIGNAL niOilii1O : STD_LOGIC; + SIGNAL niOiliiii : STD_LOGIC; + SIGNAL niOiliiil : STD_LOGIC; + SIGNAL niOiliiiO : STD_LOGIC; + SIGNAL niOiliili : STD_LOGIC; + SIGNAL niOiliill : STD_LOGIC; + SIGNAL niOiliilO : STD_LOGIC; + SIGNAL niOiliiOi : STD_LOGIC; + SIGNAL niOiliiOl : STD_LOGIC; + SIGNAL niOiliiOO : STD_LOGIC; + SIGNAL niOilil0i : STD_LOGIC; + SIGNAL niOilil0l : STD_LOGIC; + SIGNAL niOilil0O : STD_LOGIC; + SIGNAL niOilil1i : STD_LOGIC; + SIGNAL niOilil1l : STD_LOGIC; + SIGNAL niOilil1O : STD_LOGIC; + SIGNAL niOililii : STD_LOGIC; + SIGNAL niOililil : STD_LOGIC; + SIGNAL niOililiO : STD_LOGIC; + SIGNAL niOililli : STD_LOGIC; + SIGNAL niOililll : STD_LOGIC; + SIGNAL niOilillO : STD_LOGIC; + SIGNAL niOililOi : STD_LOGIC; + SIGNAL niOililOl : STD_LOGIC; + SIGNAL niOililOO : STD_LOGIC; + SIGNAL niOiliO0i : STD_LOGIC; + SIGNAL niOiliO0l : STD_LOGIC; + SIGNAL niOiliO0O : STD_LOGIC; + SIGNAL niOiliO1i : STD_LOGIC; + SIGNAL niOiliO1l : STD_LOGIC; + SIGNAL niOiliO1O : STD_LOGIC; + SIGNAL niOiliOii : STD_LOGIC; + SIGNAL niOiliOil : STD_LOGIC; + SIGNAL niOiliOiO : STD_LOGIC; + SIGNAL niOiliOli : STD_LOGIC; + SIGNAL niOiliOll : STD_LOGIC; + SIGNAL niOiliOlO : STD_LOGIC; + SIGNAL niOiliOOi : STD_LOGIC; + SIGNAL niOiliOOl : STD_LOGIC; + SIGNAL niOiliOOO : STD_LOGIC; + SIGNAL niOill00i : STD_LOGIC; + SIGNAL niOill00l : STD_LOGIC; + SIGNAL niOill00O : STD_LOGIC; + SIGNAL niOill01i : STD_LOGIC; + SIGNAL niOill01l : STD_LOGIC; + SIGNAL niOill01O : STD_LOGIC; + SIGNAL niOill0ii : STD_LOGIC; + SIGNAL niOill0il : STD_LOGIC; + SIGNAL niOill0iO : STD_LOGIC; + SIGNAL niOill0li : STD_LOGIC; + SIGNAL niOill0ll : STD_LOGIC; + SIGNAL niOill0lO : STD_LOGIC; + SIGNAL niOill0Oi : STD_LOGIC; + SIGNAL niOill0Ol : STD_LOGIC; + SIGNAL niOill0OO : STD_LOGIC; + SIGNAL niOill10i : STD_LOGIC; + SIGNAL niOill10l : STD_LOGIC; + SIGNAL niOill10O : STD_LOGIC; + SIGNAL niOill11i : STD_LOGIC; + SIGNAL niOill11l : STD_LOGIC; + SIGNAL niOill11O : STD_LOGIC; + SIGNAL niOill1ii : STD_LOGIC; + SIGNAL niOill1il : STD_LOGIC; + SIGNAL niOill1iO : STD_LOGIC; + SIGNAL niOill1li : STD_LOGIC; + SIGNAL niOill1ll : STD_LOGIC; + SIGNAL niOill1lO : STD_LOGIC; + SIGNAL niOill1Oi : STD_LOGIC; + SIGNAL niOill1Ol : STD_LOGIC; + SIGNAL niOill1OO : STD_LOGIC; + SIGNAL niOilli0i : STD_LOGIC; + SIGNAL niOilli0l : STD_LOGIC; + SIGNAL niOilli0O : STD_LOGIC; + SIGNAL niOilli1i : STD_LOGIC; + SIGNAL niOilli1l : STD_LOGIC; + SIGNAL niOilli1O : STD_LOGIC; + SIGNAL niOilliii : STD_LOGIC; + SIGNAL niOilliil : STD_LOGIC; + SIGNAL niOilliiO : STD_LOGIC; + SIGNAL niOillili : STD_LOGIC; + SIGNAL niOillill : STD_LOGIC; + SIGNAL niOillilO : STD_LOGIC; + SIGNAL niOilliOi : STD_LOGIC; + SIGNAL niOilliOl : STD_LOGIC; + SIGNAL niOilliOO : STD_LOGIC; + SIGNAL niOilll0i : STD_LOGIC; + SIGNAL niOilll0l : STD_LOGIC; + SIGNAL niOilll0O : STD_LOGIC; + SIGNAL niOilll1i : STD_LOGIC; + SIGNAL niOilll1l : STD_LOGIC; + SIGNAL niOilll1O : STD_LOGIC; + SIGNAL niOilllii : STD_LOGIC; + SIGNAL niOilllil : STD_LOGIC; + SIGNAL niOillliO : STD_LOGIC; + SIGNAL niOilllli : STD_LOGIC; + SIGNAL niOilllll : STD_LOGIC; + SIGNAL niOillllO : STD_LOGIC; + SIGNAL niOilllOi : STD_LOGIC; + SIGNAL niOilllOl : STD_LOGIC; + SIGNAL niOilllOO : STD_LOGIC; + SIGNAL niOillO0i : STD_LOGIC; + SIGNAL niOillO0l : STD_LOGIC; + SIGNAL niOillO0O : STD_LOGIC; + SIGNAL niOillO1i : STD_LOGIC; + SIGNAL niOillO1l : STD_LOGIC; + SIGNAL niOillO1O : STD_LOGIC; + SIGNAL niOillOii : STD_LOGIC; + SIGNAL niOillOil : STD_LOGIC; + SIGNAL niOillOiO : STD_LOGIC; + SIGNAL niOillOli : STD_LOGIC; + SIGNAL niOillOll : STD_LOGIC; + SIGNAL niOillOlO : STD_LOGIC; + SIGNAL niOillOOi : STD_LOGIC; + SIGNAL niOillOOl : STD_LOGIC; + SIGNAL niOillOOO : STD_LOGIC; + SIGNAL niOilO00i : STD_LOGIC; + SIGNAL niOilO00l : STD_LOGIC; + SIGNAL niOilO00O : STD_LOGIC; + SIGNAL niOilO01i : STD_LOGIC; + SIGNAL niOilO01l : STD_LOGIC; + SIGNAL niOilO01O : STD_LOGIC; + SIGNAL niOilO0ii : STD_LOGIC; + SIGNAL niOilO0il : STD_LOGIC; + SIGNAL niOilO0iO : STD_LOGIC; + SIGNAL niOilO0li : STD_LOGIC; + SIGNAL niOilO0ll : STD_LOGIC; + SIGNAL niOilO0lO : STD_LOGIC; + SIGNAL niOilO0Oi : STD_LOGIC; + SIGNAL niOilO0Ol : STD_LOGIC; + SIGNAL niOilO0OO : STD_LOGIC; + SIGNAL niOilO10i : STD_LOGIC; + SIGNAL niOilO10l : STD_LOGIC; + SIGNAL niOilO10O : STD_LOGIC; + SIGNAL niOilO11i : STD_LOGIC; + SIGNAL niOilO11l : STD_LOGIC; + SIGNAL niOilO11O : STD_LOGIC; + SIGNAL niOilO1ii : STD_LOGIC; + SIGNAL niOilO1il : STD_LOGIC; + SIGNAL niOilO1iO : STD_LOGIC; + SIGNAL niOilO1li : STD_LOGIC; + SIGNAL niOilO1ll : STD_LOGIC; + SIGNAL niOilO1lO : STD_LOGIC; + SIGNAL niOilO1Oi : STD_LOGIC; + SIGNAL niOilO1Ol : STD_LOGIC; + SIGNAL niOilO1OO : STD_LOGIC; + SIGNAL niOilOi0i : STD_LOGIC; + SIGNAL niOilOi0l : STD_LOGIC; + SIGNAL niOilOi0O : STD_LOGIC; + SIGNAL niOilOi1i : STD_LOGIC; + SIGNAL niOilOi1l : STD_LOGIC; + SIGNAL niOilOi1O : STD_LOGIC; + SIGNAL niOilOiii : STD_LOGIC; + SIGNAL niOilOiil : STD_LOGIC; + SIGNAL niOilOiiO : STD_LOGIC; + SIGNAL niOilOili : STD_LOGIC; + SIGNAL niOilOill : STD_LOGIC; + SIGNAL niOilOilO : STD_LOGIC; + SIGNAL niOilOiOi : STD_LOGIC; + SIGNAL niOilOiOl : STD_LOGIC; + SIGNAL niOilOiOO : STD_LOGIC; + SIGNAL niOilOl0i : STD_LOGIC; + SIGNAL niOilOl0l : STD_LOGIC; + SIGNAL niOilOl0O : STD_LOGIC; + SIGNAL niOilOl1i : STD_LOGIC; + SIGNAL niOilOl1l : STD_LOGIC; + SIGNAL niOilOl1O : STD_LOGIC; + SIGNAL niOilOlii : STD_LOGIC; + SIGNAL niOilOlil : STD_LOGIC; + SIGNAL niOilOliO : STD_LOGIC; + SIGNAL niOilOlli : STD_LOGIC; + SIGNAL niOilOlll : STD_LOGIC; + SIGNAL niOilOllO : STD_LOGIC; + SIGNAL niOilOlOi : STD_LOGIC; + SIGNAL niOilOlOl : STD_LOGIC; + SIGNAL niOilOlOO : STD_LOGIC; + SIGNAL niOilOO0i : STD_LOGIC; + SIGNAL niOilOO0l : STD_LOGIC; + SIGNAL niOilOO0O : STD_LOGIC; + SIGNAL niOilOO1i : STD_LOGIC; + SIGNAL niOilOO1l : STD_LOGIC; + SIGNAL niOilOO1O : STD_LOGIC; + SIGNAL niOilOOii : STD_LOGIC; + SIGNAL niOilOOil : STD_LOGIC; + SIGNAL niOilOOiO : STD_LOGIC; + SIGNAL niOilOOli : STD_LOGIC; + SIGNAL niOilOOll : STD_LOGIC; + SIGNAL niOilOOlO : STD_LOGIC; + SIGNAL niOilOOOi : STD_LOGIC; + SIGNAL niOilOOOl : STD_LOGIC; + SIGNAL niOilOOOO : STD_LOGIC; + SIGNAL niOiO000i : STD_LOGIC; + SIGNAL niOiO000l : STD_LOGIC; + SIGNAL niOiO000O : STD_LOGIC; + SIGNAL niOiO001i : STD_LOGIC; + SIGNAL niOiO001l : STD_LOGIC; + SIGNAL niOiO001O : STD_LOGIC; + SIGNAL niOiO00ii : STD_LOGIC; + SIGNAL niOiO00il : STD_LOGIC; + SIGNAL niOiO00iO : STD_LOGIC; + SIGNAL niOiO00li : STD_LOGIC; + SIGNAL niOiO00ll : STD_LOGIC; + SIGNAL niOiO00lO : STD_LOGIC; + SIGNAL niOiO00Oi : STD_LOGIC; + SIGNAL niOiO00Ol : STD_LOGIC; + SIGNAL niOiO00OO : STD_LOGIC; + SIGNAL niOiO010i : STD_LOGIC; + SIGNAL niOiO010l : STD_LOGIC; + SIGNAL niOiO010O : STD_LOGIC; + SIGNAL niOiO011i : STD_LOGIC; + SIGNAL niOiO011l : STD_LOGIC; + SIGNAL niOiO011O : STD_LOGIC; + SIGNAL niOiO01ii : STD_LOGIC; + SIGNAL niOiO01il : STD_LOGIC; + SIGNAL niOiO01iO : STD_LOGIC; + SIGNAL niOiO01li : STD_LOGIC; + SIGNAL niOiO01ll : STD_LOGIC; + SIGNAL niOiO01lO : STD_LOGIC; + SIGNAL niOiO01Oi : STD_LOGIC; + SIGNAL niOiO01Ol : STD_LOGIC; + SIGNAL niOiO01OO : STD_LOGIC; + SIGNAL niOiO0i0i : STD_LOGIC; + SIGNAL niOiO0i0l : STD_LOGIC; + SIGNAL niOiO0i0O : STD_LOGIC; + SIGNAL niOiO0i1i : STD_LOGIC; + SIGNAL niOiO0i1l : STD_LOGIC; + SIGNAL niOiO0i1O : STD_LOGIC; + SIGNAL niOiO0iii : STD_LOGIC; + SIGNAL niOiO0iil : STD_LOGIC; + SIGNAL niOiO0iiO : STD_LOGIC; + SIGNAL niOiO0ili : STD_LOGIC; + SIGNAL niOiO0ill : STD_LOGIC; + SIGNAL niOiO0ilO : STD_LOGIC; + SIGNAL niOiO0iOi : STD_LOGIC; + SIGNAL niOiO0iOl : STD_LOGIC; + SIGNAL niOiO0iOO : STD_LOGIC; + SIGNAL niOiO0l0i : STD_LOGIC; + SIGNAL niOiO0l0l : STD_LOGIC; + SIGNAL niOiO0l0O : STD_LOGIC; + SIGNAL niOiO0l1i : STD_LOGIC; + SIGNAL niOiO0l1l : STD_LOGIC; + SIGNAL niOiO0l1O : STD_LOGIC; + SIGNAL niOiO0lii : STD_LOGIC; + SIGNAL niOiO0lil : STD_LOGIC; + SIGNAL niOiO0liO : STD_LOGIC; + SIGNAL niOiO0lli : STD_LOGIC; + SIGNAL niOiO0lll : STD_LOGIC; + SIGNAL niOiO0llO : STD_LOGIC; + SIGNAL niOiO0lOi : STD_LOGIC; + SIGNAL niOiO0lOl : STD_LOGIC; + SIGNAL niOiO0lOO : STD_LOGIC; + SIGNAL niOiO0O0i : STD_LOGIC; + SIGNAL niOiO0O0l : STD_LOGIC; + SIGNAL niOiO0O0O : STD_LOGIC; + SIGNAL niOiO0O1i : STD_LOGIC; + SIGNAL niOiO0O1l : STD_LOGIC; + SIGNAL niOiO0O1O : STD_LOGIC; + SIGNAL niOiO0Oii : STD_LOGIC; + SIGNAL niOiO0Oil : STD_LOGIC; + SIGNAL niOiO0OiO : STD_LOGIC; + SIGNAL niOiO0Oli : STD_LOGIC; + SIGNAL niOiO0Oll : STD_LOGIC; + SIGNAL niOiO0OlO : STD_LOGIC; + SIGNAL niOiO0OOi : STD_LOGIC; + SIGNAL niOiO0OOl : STD_LOGIC; + SIGNAL niOiO0OOO : STD_LOGIC; + SIGNAL niOiO100i : STD_LOGIC; + SIGNAL niOiO100l : STD_LOGIC; + SIGNAL niOiO100O : STD_LOGIC; + SIGNAL niOiO101i : STD_LOGIC; + SIGNAL niOiO101l : STD_LOGIC; + SIGNAL niOiO101O : STD_LOGIC; + SIGNAL niOiO10ii : STD_LOGIC; + SIGNAL niOiO10il : STD_LOGIC; + SIGNAL niOiO10iO : STD_LOGIC; + SIGNAL niOiO10li : STD_LOGIC; + SIGNAL niOiO10ll : STD_LOGIC; + SIGNAL niOiO10lO : STD_LOGIC; + SIGNAL niOiO10Oi : STD_LOGIC; + SIGNAL niOiO10Ol : STD_LOGIC; + SIGNAL niOiO10OO : STD_LOGIC; + SIGNAL niOiO110i : STD_LOGIC; + SIGNAL niOiO110l : STD_LOGIC; + SIGNAL niOiO110O : STD_LOGIC; + SIGNAL niOiO111i : STD_LOGIC; + SIGNAL niOiO111l : STD_LOGIC; + SIGNAL niOiO111O : STD_LOGIC; + SIGNAL niOiO11ii : STD_LOGIC; + SIGNAL niOiO11il : STD_LOGIC; + SIGNAL niOiO11iO : STD_LOGIC; + SIGNAL niOiO11li : STD_LOGIC; + SIGNAL niOiO11ll : STD_LOGIC; + SIGNAL niOiO11lO : STD_LOGIC; + SIGNAL niOiO11Oi : STD_LOGIC; + SIGNAL niOiO11Ol : STD_LOGIC; + SIGNAL niOiO11OO : STD_LOGIC; + SIGNAL niOiO1i0i : STD_LOGIC; + SIGNAL niOiO1i0l : STD_LOGIC; + SIGNAL niOiO1i0O : STD_LOGIC; + SIGNAL niOiO1i1i : STD_LOGIC; + SIGNAL niOiO1i1l : STD_LOGIC; + SIGNAL niOiO1i1O : STD_LOGIC; + SIGNAL niOiO1iii : STD_LOGIC; + SIGNAL niOiO1iil : STD_LOGIC; + SIGNAL niOiO1iiO : STD_LOGIC; + SIGNAL niOiO1ili : STD_LOGIC; + SIGNAL niOiO1ill : STD_LOGIC; + SIGNAL niOiO1ilO : STD_LOGIC; + SIGNAL niOiO1iOi : STD_LOGIC; + SIGNAL niOiO1iOl : STD_LOGIC; + SIGNAL niOiO1iOO : STD_LOGIC; + SIGNAL niOiO1l0i : STD_LOGIC; + SIGNAL niOiO1l0l : STD_LOGIC; + SIGNAL niOiO1l0O : STD_LOGIC; + SIGNAL niOiO1l1i : STD_LOGIC; + SIGNAL niOiO1l1l : STD_LOGIC; + SIGNAL niOiO1l1O : STD_LOGIC; + SIGNAL niOiO1lii : STD_LOGIC; + SIGNAL niOiO1lil : STD_LOGIC; + SIGNAL niOiO1liO : STD_LOGIC; + SIGNAL niOiO1lli : STD_LOGIC; + SIGNAL niOiO1lll : STD_LOGIC; + SIGNAL niOiO1llO : STD_LOGIC; + SIGNAL niOiO1lOi : STD_LOGIC; + SIGNAL niOiO1lOl : STD_LOGIC; + SIGNAL niOiO1lOO : STD_LOGIC; + SIGNAL niOiO1O0i : STD_LOGIC; + SIGNAL niOiO1O0l : STD_LOGIC; + SIGNAL niOiO1O0O : STD_LOGIC; + SIGNAL niOiO1O1i : STD_LOGIC; + SIGNAL niOiO1O1l : STD_LOGIC; + SIGNAL niOiO1O1O : STD_LOGIC; + SIGNAL niOiO1Oii : STD_LOGIC; + SIGNAL niOiO1Oil : STD_LOGIC; + SIGNAL niOiO1OiO : STD_LOGIC; + SIGNAL niOiO1Oli : STD_LOGIC; + SIGNAL niOiO1Oll : STD_LOGIC; + SIGNAL niOiO1OlO : STD_LOGIC; + SIGNAL niOiO1OOi : STD_LOGIC; + SIGNAL niOiO1OOl : STD_LOGIC; + SIGNAL niOiO1OOO : STD_LOGIC; + SIGNAL niOiOi00i : STD_LOGIC; + SIGNAL niOiOi00l : STD_LOGIC; + SIGNAL niOiOi00O : STD_LOGIC; + SIGNAL niOiOi01i : STD_LOGIC; + SIGNAL niOiOi01l : STD_LOGIC; + SIGNAL niOiOi01O : STD_LOGIC; + SIGNAL niOiOi0ii : STD_LOGIC; + SIGNAL niOiOi0il : STD_LOGIC; + SIGNAL niOiOi0iO : STD_LOGIC; + SIGNAL niOiOi0li : STD_LOGIC; + SIGNAL niOiOi0ll : STD_LOGIC; + SIGNAL niOiOi0lO : STD_LOGIC; + SIGNAL niOiOi0Oi : STD_LOGIC; + SIGNAL niOiOi0Ol : STD_LOGIC; + SIGNAL niOiOi0OO : STD_LOGIC; + SIGNAL niOiOi10i : STD_LOGIC; + SIGNAL niOiOi10l : STD_LOGIC; + SIGNAL niOiOi10O : STD_LOGIC; + SIGNAL niOiOi11i : STD_LOGIC; + SIGNAL niOiOi11l : STD_LOGIC; + SIGNAL niOiOi11O : STD_LOGIC; + SIGNAL niOiOi1ii : STD_LOGIC; + SIGNAL niOiOi1il : STD_LOGIC; + SIGNAL niOiOi1iO : STD_LOGIC; + SIGNAL niOiOi1li : STD_LOGIC; + SIGNAL niOiOi1ll : STD_LOGIC; + SIGNAL niOiOi1lO : STD_LOGIC; + SIGNAL niOiOi1Oi : STD_LOGIC; + SIGNAL niOiOi1Ol : STD_LOGIC; + SIGNAL niOiOi1OO : STD_LOGIC; + SIGNAL niOiOii0i : STD_LOGIC; + SIGNAL niOiOii0l : STD_LOGIC; + SIGNAL niOiOii0O : STD_LOGIC; + SIGNAL niOiOii1i : STD_LOGIC; + SIGNAL niOiOii1l : STD_LOGIC; + SIGNAL niOiOii1O : STD_LOGIC; + SIGNAL niOiOiiii : STD_LOGIC; + SIGNAL niOiOiiil : STD_LOGIC; + SIGNAL niOiOiiiO : STD_LOGIC; + SIGNAL niOiOiili : STD_LOGIC; + SIGNAL niOiOiill : STD_LOGIC; + SIGNAL niOiOiilO : STD_LOGIC; + SIGNAL niOiOiiOi : STD_LOGIC; + SIGNAL niOiOiiOl : STD_LOGIC; + SIGNAL niOiOiiOO : STD_LOGIC; + SIGNAL niOiOil0i : STD_LOGIC; + SIGNAL niOiOil0l : STD_LOGIC; + SIGNAL niOiOil0O : STD_LOGIC; + SIGNAL niOiOil1i : STD_LOGIC; + SIGNAL niOiOil1l : STD_LOGIC; + SIGNAL niOiOil1O : STD_LOGIC; + SIGNAL niOiOilii : STD_LOGIC; + SIGNAL niOiOilil : STD_LOGIC; + SIGNAL niOiOiliO : STD_LOGIC; + SIGNAL niOiOilli : STD_LOGIC; + SIGNAL niOiOilll : STD_LOGIC; + SIGNAL niOiOillO : STD_LOGIC; + SIGNAL niOiOilOi : STD_LOGIC; + SIGNAL niOiOilOl : STD_LOGIC; + SIGNAL niOiOilOO : STD_LOGIC; + SIGNAL niOiOiO0i : STD_LOGIC; + SIGNAL niOiOiO0l : STD_LOGIC; + SIGNAL niOiOiO0O : STD_LOGIC; + SIGNAL niOiOiO1i : STD_LOGIC; + SIGNAL niOiOiO1l : STD_LOGIC; + SIGNAL niOiOiO1O : STD_LOGIC; + SIGNAL niOiOiOii : STD_LOGIC; + SIGNAL niOiOiOil : STD_LOGIC; + SIGNAL niOiOiOiO : STD_LOGIC; + SIGNAL niOiOiOli : STD_LOGIC; + SIGNAL niOiOiOll : STD_LOGIC; + SIGNAL niOiOiOlO : STD_LOGIC; + SIGNAL niOiOiOOi : STD_LOGIC; + SIGNAL niOiOiOOl : STD_LOGIC; + SIGNAL niOiOiOOO : STD_LOGIC; + SIGNAL niOiOl00i : STD_LOGIC; + SIGNAL niOiOl00l : STD_LOGIC; + SIGNAL niOiOl00O : STD_LOGIC; + SIGNAL niOiOl01i : STD_LOGIC; + SIGNAL niOiOl01l : STD_LOGIC; + SIGNAL niOiOl01O : STD_LOGIC; + SIGNAL niOiOl0ii : STD_LOGIC; + SIGNAL niOiOl0il : STD_LOGIC; + SIGNAL niOiOl0iO : STD_LOGIC; + SIGNAL niOiOl0li : STD_LOGIC; + SIGNAL niOiOl0ll : STD_LOGIC; + SIGNAL niOiOl0lO : STD_LOGIC; + SIGNAL niOiOl0Oi : STD_LOGIC; + SIGNAL niOiOl0Ol : STD_LOGIC; + SIGNAL niOiOl0OO : STD_LOGIC; + SIGNAL niOiOl10i : STD_LOGIC; + SIGNAL niOiOl10l : STD_LOGIC; + SIGNAL niOiOl10O : STD_LOGIC; + SIGNAL niOiOl11i : STD_LOGIC; + SIGNAL niOiOl11l : STD_LOGIC; + SIGNAL niOiOl11O : STD_LOGIC; + SIGNAL niOiOl1ii : STD_LOGIC; + SIGNAL niOiOl1il : STD_LOGIC; + SIGNAL niOiOl1iO : STD_LOGIC; + SIGNAL niOiOl1li : STD_LOGIC; + SIGNAL niOiOl1ll : STD_LOGIC; + SIGNAL niOiOl1lO : STD_LOGIC; + SIGNAL niOiOl1Oi : STD_LOGIC; + SIGNAL niOiOl1Ol : STD_LOGIC; + SIGNAL niOiOl1OO : STD_LOGIC; + SIGNAL niOiOli0i : STD_LOGIC; + SIGNAL niOiOli0l : STD_LOGIC; + SIGNAL niOiOli0O : STD_LOGIC; + SIGNAL niOiOli1i : STD_LOGIC; + SIGNAL niOiOli1l : STD_LOGIC; + SIGNAL niOiOli1O : STD_LOGIC; + SIGNAL niOiOliii : STD_LOGIC; + SIGNAL niOiOliil : STD_LOGIC; + SIGNAL niOiOliiO : STD_LOGIC; + SIGNAL niOiOlili : STD_LOGIC; + SIGNAL niOiOlill : STD_LOGIC; + SIGNAL niOiOlilO : STD_LOGIC; + SIGNAL niOiOliOi : STD_LOGIC; + SIGNAL niOiOliOl : STD_LOGIC; + SIGNAL niOiOliOO : STD_LOGIC; + SIGNAL niOiOll0i : STD_LOGIC; + SIGNAL niOiOll0l : STD_LOGIC; + SIGNAL niOiOll0O : STD_LOGIC; + SIGNAL niOiOll1i : STD_LOGIC; + SIGNAL niOiOll1l : STD_LOGIC; + SIGNAL niOiOll1O : STD_LOGIC; + SIGNAL niOiOllii : STD_LOGIC; + SIGNAL niOiOllil : STD_LOGIC; + SIGNAL niOiOlliO : STD_LOGIC; + SIGNAL niOiOllli : STD_LOGIC; + SIGNAL niOiOllll : STD_LOGIC; + SIGNAL niOiOlllO : STD_LOGIC; + SIGNAL niOiOllOi : STD_LOGIC; + SIGNAL niOiOllOl : STD_LOGIC; + SIGNAL niOiOllOO : STD_LOGIC; + SIGNAL niOiOlO0i : STD_LOGIC; + SIGNAL niOiOlO0l : STD_LOGIC; + SIGNAL niOiOlO0O : STD_LOGIC; + SIGNAL niOiOlO1i : STD_LOGIC; + SIGNAL niOiOlO1l : STD_LOGIC; + SIGNAL niOiOlO1O : STD_LOGIC; + SIGNAL niOiOlOii : STD_LOGIC; + SIGNAL niOiOlOil : STD_LOGIC; + SIGNAL niOiOlOiO : STD_LOGIC; + SIGNAL niOiOlOli : STD_LOGIC; + SIGNAL niOiOlOll : STD_LOGIC; + SIGNAL niOiOlOlO : STD_LOGIC; + SIGNAL niOiOlOOi : STD_LOGIC; + SIGNAL niOiOlOOl : STD_LOGIC; + SIGNAL niOiOlOOO : STD_LOGIC; + SIGNAL niOiOO00i : STD_LOGIC; + SIGNAL niOiOO00l : STD_LOGIC; + SIGNAL niOiOO00O : STD_LOGIC; + SIGNAL niOiOO01i : STD_LOGIC; + SIGNAL niOiOO01l : STD_LOGIC; + SIGNAL niOiOO01O : STD_LOGIC; + SIGNAL niOiOO0ii : STD_LOGIC; + SIGNAL niOiOO0il : STD_LOGIC; + SIGNAL niOiOO0iO : STD_LOGIC; + SIGNAL niOiOO0li : STD_LOGIC; + SIGNAL niOiOO0ll : STD_LOGIC; + SIGNAL niOiOO0lO : STD_LOGIC; + SIGNAL niOiOO0Oi : STD_LOGIC; + SIGNAL niOiOO0Ol : STD_LOGIC; + SIGNAL niOiOO0OO : STD_LOGIC; + SIGNAL niOiOO10i : STD_LOGIC; + SIGNAL niOiOO10l : STD_LOGIC; + SIGNAL niOiOO10O : STD_LOGIC; + SIGNAL niOiOO11i : STD_LOGIC; + SIGNAL niOiOO11l : STD_LOGIC; + SIGNAL niOiOO11O : STD_LOGIC; + SIGNAL niOiOO1ii : STD_LOGIC; + SIGNAL niOiOO1il : STD_LOGIC; + SIGNAL niOiOO1iO : STD_LOGIC; + SIGNAL niOiOO1li : STD_LOGIC; + SIGNAL niOiOO1ll : STD_LOGIC; + SIGNAL niOiOO1lO : STD_LOGIC; + SIGNAL niOiOO1Oi : STD_LOGIC; + SIGNAL niOiOO1Ol : STD_LOGIC; + SIGNAL niOiOO1OO : STD_LOGIC; + SIGNAL niOiOOi0i : STD_LOGIC; + SIGNAL niOiOOi0l : STD_LOGIC; + SIGNAL niOiOOi0O : STD_LOGIC; + SIGNAL niOiOOi1i : STD_LOGIC; + SIGNAL niOiOOi1l : STD_LOGIC; + SIGNAL niOiOOi1O : STD_LOGIC; + SIGNAL niOiOOiii : STD_LOGIC; + SIGNAL niOiOOiil : STD_LOGIC; + SIGNAL niOiOOiiO : STD_LOGIC; + SIGNAL niOiOOili : STD_LOGIC; + SIGNAL niOiOOill : STD_LOGIC; + SIGNAL niOiOOilO : STD_LOGIC; + SIGNAL niOiOOiOi : STD_LOGIC; + SIGNAL niOiOOiOl : STD_LOGIC; + SIGNAL niOiOOiOO : STD_LOGIC; + SIGNAL niOiOOl0i : STD_LOGIC; + SIGNAL niOiOOl0l : STD_LOGIC; + SIGNAL niOiOOl0O : STD_LOGIC; + SIGNAL niOiOOl1i : STD_LOGIC; + SIGNAL niOiOOl1l : STD_LOGIC; + SIGNAL niOiOOl1O : STD_LOGIC; + SIGNAL niOiOOlii : STD_LOGIC; + SIGNAL niOiOOlil : STD_LOGIC; + SIGNAL niOiOOliO : STD_LOGIC; + SIGNAL niOiOOlli : STD_LOGIC; + SIGNAL niOiOOlll : STD_LOGIC; + SIGNAL niOiOOllO : STD_LOGIC; + SIGNAL niOiOOlOi : STD_LOGIC; + SIGNAL niOiOOlOl : STD_LOGIC; + SIGNAL niOiOOlOO : STD_LOGIC; + SIGNAL niOiOOO0i : STD_LOGIC; + SIGNAL niOiOOO0l : STD_LOGIC; + SIGNAL niOiOOO0O : STD_LOGIC; + SIGNAL niOiOOO1i : STD_LOGIC; + SIGNAL niOiOOO1l : STD_LOGIC; + SIGNAL niOiOOO1O : STD_LOGIC; + SIGNAL niOiOOOii : STD_LOGIC; + SIGNAL niOiOOOil : STD_LOGIC; + SIGNAL niOiOOOiO : STD_LOGIC; + SIGNAL niOiOOOli : STD_LOGIC; + SIGNAL niOiOOOll : STD_LOGIC; + SIGNAL niOiOOOlO : STD_LOGIC; + SIGNAL niOiOOOOi : STD_LOGIC; + SIGNAL niOiOOOOl : STD_LOGIC; + SIGNAL niOiOOOOO : STD_LOGIC; + SIGNAL niOl0000i : STD_LOGIC; + SIGNAL niOl0000l : STD_LOGIC; + SIGNAL niOl0000O : STD_LOGIC; + SIGNAL niOl0001i : STD_LOGIC; + SIGNAL niOl0001l : STD_LOGIC; + SIGNAL niOl0001O : STD_LOGIC; + SIGNAL niOl000ii : STD_LOGIC; + SIGNAL niOl000il : STD_LOGIC; + SIGNAL niOl000iO : STD_LOGIC; + SIGNAL niOl000li : STD_LOGIC; + SIGNAL niOl000ll : STD_LOGIC; + SIGNAL niOl000lO : STD_LOGIC; + SIGNAL niOl000Oi : STD_LOGIC; + SIGNAL niOl000Ol : STD_LOGIC; + SIGNAL niOl000OO : STD_LOGIC; + SIGNAL niOl0010i : STD_LOGIC; + SIGNAL niOl0010l : STD_LOGIC; + SIGNAL niOl0010O : STD_LOGIC; + SIGNAL niOl0011i : STD_LOGIC; + SIGNAL niOl0011l : STD_LOGIC; + SIGNAL niOl0011O : STD_LOGIC; + SIGNAL niOl001ii : STD_LOGIC; + SIGNAL niOl001il : STD_LOGIC; + SIGNAL niOl001iO : STD_LOGIC; + SIGNAL niOl001li : STD_LOGIC; + SIGNAL niOl001ll : STD_LOGIC; + SIGNAL niOl001lO : STD_LOGIC; + SIGNAL niOl001Oi : STD_LOGIC; + SIGNAL niOl001Ol : STD_LOGIC; + SIGNAL niOl001OO : STD_LOGIC; + SIGNAL niOl00i0i : STD_LOGIC; + SIGNAL niOl00i0l : STD_LOGIC; + SIGNAL niOl00i0O : STD_LOGIC; + SIGNAL niOl00i1i : STD_LOGIC; + SIGNAL niOl00i1l : STD_LOGIC; + SIGNAL niOl00i1O : STD_LOGIC; + SIGNAL niOl00iii : STD_LOGIC; + SIGNAL niOl00iil : STD_LOGIC; + SIGNAL niOl00iiO : STD_LOGIC; + SIGNAL niOl00ili : STD_LOGIC; + SIGNAL niOl00ill : STD_LOGIC; + SIGNAL niOl00ilO : STD_LOGIC; + SIGNAL niOl00iOi : STD_LOGIC; + SIGNAL niOl00iOl : STD_LOGIC; + SIGNAL niOl00iOO : STD_LOGIC; + SIGNAL niOl00l0i : STD_LOGIC; + SIGNAL niOl00l0l : STD_LOGIC; + SIGNAL niOl00l0O : STD_LOGIC; + SIGNAL niOl00l1i : STD_LOGIC; + SIGNAL niOl00l1l : STD_LOGIC; + SIGNAL niOl00l1O : STD_LOGIC; + SIGNAL niOl00lii : STD_LOGIC; + SIGNAL niOl00lil : STD_LOGIC; + SIGNAL niOl00liO : STD_LOGIC; + SIGNAL niOl00lli : STD_LOGIC; + SIGNAL niOl00lll : STD_LOGIC; + SIGNAL niOl00llO : STD_LOGIC; + SIGNAL niOl00lOi : STD_LOGIC; + SIGNAL niOl00lOl : STD_LOGIC; + SIGNAL niOl00lOO : STD_LOGIC; + SIGNAL niOl00O0i : STD_LOGIC; + SIGNAL niOl00O0l : STD_LOGIC; + SIGNAL niOl00O0O : STD_LOGIC; + SIGNAL niOl00O1i : STD_LOGIC; + SIGNAL niOl00O1l : STD_LOGIC; + SIGNAL niOl00O1O : STD_LOGIC; + SIGNAL niOl00Oii : STD_LOGIC; + SIGNAL niOl00Oil : STD_LOGIC; + SIGNAL niOl00OiO : STD_LOGIC; + SIGNAL niOl00Oli : STD_LOGIC; + SIGNAL niOl00Oll : STD_LOGIC; + SIGNAL niOl00OlO : STD_LOGIC; + SIGNAL niOl00OOi : STD_LOGIC; + SIGNAL niOl00OOl : STD_LOGIC; + SIGNAL niOl00OOO : STD_LOGIC; + SIGNAL niOl0100i : STD_LOGIC; + SIGNAL niOl0100l : STD_LOGIC; + SIGNAL niOl0100O : STD_LOGIC; + SIGNAL niOl0101i : STD_LOGIC; + SIGNAL niOl0101l : STD_LOGIC; + SIGNAL niOl0101O : STD_LOGIC; + SIGNAL niOl010ii : STD_LOGIC; + SIGNAL niOl010il : STD_LOGIC; + SIGNAL niOl010iO : STD_LOGIC; + SIGNAL niOl010li : STD_LOGIC; + SIGNAL niOl010ll : STD_LOGIC; + SIGNAL niOl010lO : STD_LOGIC; + SIGNAL niOl010Oi : STD_LOGIC; + SIGNAL niOl010Ol : STD_LOGIC; + SIGNAL niOl010OO : STD_LOGIC; + SIGNAL niOl0110i : STD_LOGIC; + SIGNAL niOl0110l : STD_LOGIC; + SIGNAL niOl0110O : STD_LOGIC; + SIGNAL niOl0111i : STD_LOGIC; + SIGNAL niOl0111l : STD_LOGIC; + SIGNAL niOl0111O : STD_LOGIC; + SIGNAL niOl011ii : STD_LOGIC; + SIGNAL niOl011il : STD_LOGIC; + SIGNAL niOl011iO : STD_LOGIC; + SIGNAL niOl011li : STD_LOGIC; + SIGNAL niOl011ll : STD_LOGIC; + SIGNAL niOl011lO : STD_LOGIC; + SIGNAL niOl011Oi : STD_LOGIC; + SIGNAL niOl011Ol : STD_LOGIC; + SIGNAL niOl011OO : STD_LOGIC; + SIGNAL niOl01i0i : STD_LOGIC; + SIGNAL niOl01i0l : STD_LOGIC; + SIGNAL niOl01i0O : STD_LOGIC; + SIGNAL niOl01i1i : STD_LOGIC; + SIGNAL niOl01i1l : STD_LOGIC; + SIGNAL niOl01i1O : STD_LOGIC; + SIGNAL niOl01iii : STD_LOGIC; + SIGNAL niOl01iil : STD_LOGIC; + SIGNAL niOl01iiO : STD_LOGIC; + SIGNAL niOl01ili : STD_LOGIC; + SIGNAL niOl01ill : STD_LOGIC; + SIGNAL niOl01ilO : STD_LOGIC; + SIGNAL niOl01iOi : STD_LOGIC; + SIGNAL niOl01iOl : STD_LOGIC; + SIGNAL niOl01iOO : STD_LOGIC; + SIGNAL niOl01l0i : STD_LOGIC; + SIGNAL niOl01l0l : STD_LOGIC; + SIGNAL niOl01l0O : STD_LOGIC; + SIGNAL niOl01l1i : STD_LOGIC; + SIGNAL niOl01l1l : STD_LOGIC; + SIGNAL niOl01l1O : STD_LOGIC; + SIGNAL niOl01lii : STD_LOGIC; + SIGNAL niOl01lil : STD_LOGIC; + SIGNAL niOl01liO : STD_LOGIC; + SIGNAL niOl01lli : STD_LOGIC; + SIGNAL niOl01lll : STD_LOGIC; + SIGNAL niOl01llO : STD_LOGIC; + SIGNAL niOl01lOi : STD_LOGIC; + SIGNAL niOl01lOl : STD_LOGIC; + SIGNAL niOl01lOO : STD_LOGIC; + SIGNAL niOl01O0i : STD_LOGIC; + SIGNAL niOl01O0l : STD_LOGIC; + SIGNAL niOl01O0O : STD_LOGIC; + SIGNAL niOl01O1i : STD_LOGIC; + SIGNAL niOl01O1l : STD_LOGIC; + SIGNAL niOl01O1O : STD_LOGIC; + SIGNAL niOl01Oii : STD_LOGIC; + SIGNAL niOl01Oil : STD_LOGIC; + SIGNAL niOl01OiO : STD_LOGIC; + SIGNAL niOl01Oli : STD_LOGIC; + SIGNAL niOl01Oll : STD_LOGIC; + SIGNAL niOl01OlO : STD_LOGIC; + SIGNAL niOl01OOi : STD_LOGIC; + SIGNAL niOl01OOl : STD_LOGIC; + SIGNAL niOl01OOO : STD_LOGIC; + SIGNAL niOl0i00i : STD_LOGIC; + SIGNAL niOl0i00l : STD_LOGIC; + SIGNAL niOl0i00O : STD_LOGIC; + SIGNAL niOl0i01i : STD_LOGIC; + SIGNAL niOl0i01l : STD_LOGIC; + SIGNAL niOl0i01O : STD_LOGIC; + SIGNAL niOl0i0ii : STD_LOGIC; + SIGNAL niOl0i0il : STD_LOGIC; + SIGNAL niOl0i0iO : STD_LOGIC; + SIGNAL niOl0i0li : STD_LOGIC; + SIGNAL niOl0i0ll : STD_LOGIC; + SIGNAL niOl0i0lO : STD_LOGIC; + SIGNAL niOl0i0Oi : STD_LOGIC; + SIGNAL niOl0i0Ol : STD_LOGIC; + SIGNAL niOl0i0OO : STD_LOGIC; + SIGNAL niOl0i10i : STD_LOGIC; + SIGNAL niOl0i10l : STD_LOGIC; + SIGNAL niOl0i10O : STD_LOGIC; + SIGNAL niOl0i11i : STD_LOGIC; + SIGNAL niOl0i11l : STD_LOGIC; + SIGNAL niOl0i11O : STD_LOGIC; + SIGNAL niOl0i1ii : STD_LOGIC; + SIGNAL niOl0i1il : STD_LOGIC; + SIGNAL niOl0i1iO : STD_LOGIC; + SIGNAL niOl0i1li : STD_LOGIC; + SIGNAL niOl0i1ll : STD_LOGIC; + SIGNAL niOl0i1lO : STD_LOGIC; + SIGNAL niOl0i1Oi : STD_LOGIC; + SIGNAL niOl0i1Ol : STD_LOGIC; + SIGNAL niOl0i1OO : STD_LOGIC; + SIGNAL niOl0ii0i : STD_LOGIC; + SIGNAL niOl0ii0l : STD_LOGIC; + SIGNAL niOl0ii0O : STD_LOGIC; + SIGNAL niOl0ii1i : STD_LOGIC; + SIGNAL niOl0ii1l : STD_LOGIC; + SIGNAL niOl0ii1O : STD_LOGIC; + SIGNAL niOl0iiii : STD_LOGIC; + SIGNAL niOl0iiil : STD_LOGIC; + SIGNAL niOl0iiiO : STD_LOGIC; + SIGNAL niOl0iili : STD_LOGIC; + SIGNAL niOl0iill : STD_LOGIC; + SIGNAL niOl0iilO : STD_LOGIC; + SIGNAL niOl0iiOi : STD_LOGIC; + SIGNAL niOl0iiOl : STD_LOGIC; + SIGNAL niOl0iiOO : STD_LOGIC; + SIGNAL niOl0il0i : STD_LOGIC; + SIGNAL niOl0il0l : STD_LOGIC; + SIGNAL niOl0il0O : STD_LOGIC; + SIGNAL niOl0il1i : STD_LOGIC; + SIGNAL niOl0il1l : STD_LOGIC; + SIGNAL niOl0il1O : STD_LOGIC; + SIGNAL niOl0ilii : STD_LOGIC; + SIGNAL niOl0ilil : STD_LOGIC; + SIGNAL niOl0iliO : STD_LOGIC; + SIGNAL niOl0illi : STD_LOGIC; + SIGNAL niOl0illl : STD_LOGIC; + SIGNAL niOl0illO : STD_LOGIC; + SIGNAL niOl0ilOi : STD_LOGIC; + SIGNAL niOl0ilOl : STD_LOGIC; + SIGNAL niOl0ilOO : STD_LOGIC; + SIGNAL niOl0iO0i : STD_LOGIC; + SIGNAL niOl0iO0l : STD_LOGIC; + SIGNAL niOl0iO0O : STD_LOGIC; + SIGNAL niOl0iO1i : STD_LOGIC; + SIGNAL niOl0iO1l : STD_LOGIC; + SIGNAL niOl0iO1O : STD_LOGIC; + SIGNAL niOl0iOii : STD_LOGIC; + SIGNAL niOl0iOil : STD_LOGIC; + SIGNAL niOl0iOiO : STD_LOGIC; + SIGNAL niOl0iOli : STD_LOGIC; + SIGNAL niOl0iOll : STD_LOGIC; + SIGNAL niOl0iOlO : STD_LOGIC; + SIGNAL niOl0iOOi : STD_LOGIC; + SIGNAL niOl0iOOl : STD_LOGIC; + SIGNAL niOl0iOOO : STD_LOGIC; + SIGNAL niOl0l00i : STD_LOGIC; + SIGNAL niOl0l00l : STD_LOGIC; + SIGNAL niOl0l00O : STD_LOGIC; + SIGNAL niOl0l01i : STD_LOGIC; + SIGNAL niOl0l01l : STD_LOGIC; + SIGNAL niOl0l01O : STD_LOGIC; + SIGNAL niOl0l0ii : STD_LOGIC; + SIGNAL niOl0l0il : STD_LOGIC; + SIGNAL niOl0l0iO : STD_LOGIC; + SIGNAL niOl0l0li : STD_LOGIC; + SIGNAL niOl0l0ll : STD_LOGIC; + SIGNAL niOl0l0lO : STD_LOGIC; + SIGNAL niOl0l0Oi : STD_LOGIC; + SIGNAL niOl0l0Ol : STD_LOGIC; + SIGNAL niOl0l0OO : STD_LOGIC; + SIGNAL niOl0l10i : STD_LOGIC; + SIGNAL niOl0l10l : STD_LOGIC; + SIGNAL niOl0l10O : STD_LOGIC; + SIGNAL niOl0l11i : STD_LOGIC; + SIGNAL niOl0l11l : STD_LOGIC; + SIGNAL niOl0l11O : STD_LOGIC; + SIGNAL niOl0l1ii : STD_LOGIC; + SIGNAL niOl0l1il : STD_LOGIC; + SIGNAL niOl0l1iO : STD_LOGIC; + SIGNAL niOl0l1li : STD_LOGIC; + SIGNAL niOl0l1ll : STD_LOGIC; + SIGNAL niOl0l1lO : STD_LOGIC; + SIGNAL niOl0l1Oi : STD_LOGIC; + SIGNAL niOl0l1Ol : STD_LOGIC; + SIGNAL niOl0l1OO : STD_LOGIC; + SIGNAL niOl0li0i : STD_LOGIC; + SIGNAL niOl0li0l : STD_LOGIC; + SIGNAL niOl0li0O : STD_LOGIC; + SIGNAL niOl0li1i : STD_LOGIC; + SIGNAL niOl0li1l : STD_LOGIC; + SIGNAL niOl0li1O : STD_LOGIC; + SIGNAL niOl0liii : STD_LOGIC; + SIGNAL niOl0liil : STD_LOGIC; + SIGNAL niOl0liiO : STD_LOGIC; + SIGNAL niOl0lili : STD_LOGIC; + SIGNAL niOl0lill : STD_LOGIC; + SIGNAL niOl0lilO : STD_LOGIC; + SIGNAL niOl0liOi : STD_LOGIC; + SIGNAL niOl0liOl : STD_LOGIC; + SIGNAL niOl0liOO : STD_LOGIC; + SIGNAL niOl0ll0i : STD_LOGIC; + SIGNAL niOl0ll0l : STD_LOGIC; + SIGNAL niOl0ll0O : STD_LOGIC; + SIGNAL niOl0ll1i : STD_LOGIC; + SIGNAL niOl0ll1l : STD_LOGIC; + SIGNAL niOl0ll1O : STD_LOGIC; + SIGNAL niOl0llii : STD_LOGIC; + SIGNAL niOl0llil : STD_LOGIC; + SIGNAL niOl0lliO : STD_LOGIC; + SIGNAL niOl0llli : STD_LOGIC; + SIGNAL niOl0llll : STD_LOGIC; + SIGNAL niOl0lllO : STD_LOGIC; + SIGNAL niOl0llOi : STD_LOGIC; + SIGNAL niOl0llOl : STD_LOGIC; + SIGNAL niOl0llOO : STD_LOGIC; + SIGNAL niOl0lO0i : STD_LOGIC; + SIGNAL niOl0lO0l : STD_LOGIC; + SIGNAL niOl0lO0O : STD_LOGIC; + SIGNAL niOl0lO1i : STD_LOGIC; + SIGNAL niOl0lO1l : STD_LOGIC; + SIGNAL niOl0lO1O : STD_LOGIC; + SIGNAL niOl0lOii : STD_LOGIC; + SIGNAL niOl0lOil : STD_LOGIC; + SIGNAL niOl0lOiO : STD_LOGIC; + SIGNAL niOl0lOli : STD_LOGIC; + SIGNAL niOl0lOll : STD_LOGIC; + SIGNAL niOl0lOlO : STD_LOGIC; + SIGNAL niOl0lOOi : STD_LOGIC; + SIGNAL niOl0lOOl : STD_LOGIC; + SIGNAL niOl0lOOO : STD_LOGIC; + SIGNAL niOl0O00i : STD_LOGIC; + SIGNAL niOl0O00l : STD_LOGIC; + SIGNAL niOl0O00O : STD_LOGIC; + SIGNAL niOl0O01i : STD_LOGIC; + SIGNAL niOl0O01l : STD_LOGIC; + SIGNAL niOl0O01O : STD_LOGIC; + SIGNAL niOl0O0ii : STD_LOGIC; + SIGNAL niOl0O0il : STD_LOGIC; + SIGNAL niOl0O0iO : STD_LOGIC; + SIGNAL niOl0O0li : STD_LOGIC; + SIGNAL niOl0O0ll : STD_LOGIC; + SIGNAL niOl0O0lO : STD_LOGIC; + SIGNAL niOl0O0Oi : STD_LOGIC; + SIGNAL niOl0O0Ol : STD_LOGIC; + SIGNAL niOl0O0OO : STD_LOGIC; + SIGNAL niOl0O10i : STD_LOGIC; + SIGNAL niOl0O10l : STD_LOGIC; + SIGNAL niOl0O10O : STD_LOGIC; + SIGNAL niOl0O11i : STD_LOGIC; + SIGNAL niOl0O11l : STD_LOGIC; + SIGNAL niOl0O11O : STD_LOGIC; + SIGNAL niOl0O1ii : STD_LOGIC; + SIGNAL niOl0O1il : STD_LOGIC; + SIGNAL niOl0O1iO : STD_LOGIC; + SIGNAL niOl0O1li : STD_LOGIC; + SIGNAL niOl0O1ll : STD_LOGIC; + SIGNAL niOl0O1lO : STD_LOGIC; + SIGNAL niOl0O1Oi : STD_LOGIC; + SIGNAL niOl0O1Ol : STD_LOGIC; + SIGNAL niOl0O1OO : STD_LOGIC; + SIGNAL niOl0Oi0i : STD_LOGIC; + SIGNAL niOl0Oi0l : STD_LOGIC; + SIGNAL niOl0Oi0O : STD_LOGIC; + SIGNAL niOl0Oi1i : STD_LOGIC; + SIGNAL niOl0Oi1l : STD_LOGIC; + SIGNAL niOl0Oi1O : STD_LOGIC; + SIGNAL niOl0Oiii : STD_LOGIC; + SIGNAL niOl0Oiil : STD_LOGIC; + SIGNAL niOl0OiiO : STD_LOGIC; + SIGNAL niOl0Oili : STD_LOGIC; + SIGNAL niOl0Oill : STD_LOGIC; + SIGNAL niOl0OilO : STD_LOGIC; + SIGNAL niOl0OiOi : STD_LOGIC; + SIGNAL niOl0OiOl : STD_LOGIC; + SIGNAL niOl0OiOO : STD_LOGIC; + SIGNAL niOl0Ol0i : STD_LOGIC; + SIGNAL niOl0Ol0l : STD_LOGIC; + SIGNAL niOl0Ol0O : STD_LOGIC; + SIGNAL niOl0Ol1i : STD_LOGIC; + SIGNAL niOl0Ol1l : STD_LOGIC; + SIGNAL niOl0Ol1O : STD_LOGIC; + SIGNAL niOl0Olii : STD_LOGIC; + SIGNAL niOl0Olil : STD_LOGIC; + SIGNAL niOl0OliO : STD_LOGIC; + SIGNAL niOl0Olli : STD_LOGIC; + SIGNAL niOl0Olll : STD_LOGIC; + SIGNAL niOl0OllO : STD_LOGIC; + SIGNAL niOl0OlOi : STD_LOGIC; + SIGNAL niOl0OlOl : STD_LOGIC; + SIGNAL niOl0OlOO : STD_LOGIC; + SIGNAL niOl0OO0i : STD_LOGIC; + SIGNAL niOl0OO0l : STD_LOGIC; + SIGNAL niOl0OO0O : STD_LOGIC; + SIGNAL niOl0OO1i : STD_LOGIC; + SIGNAL niOl0OO1l : STD_LOGIC; + SIGNAL niOl0OO1O : STD_LOGIC; + SIGNAL niOl0OOii : STD_LOGIC; + SIGNAL niOl0OOil : STD_LOGIC; + SIGNAL niOl0OOiO : STD_LOGIC; + SIGNAL niOl0OOli : STD_LOGIC; + SIGNAL niOl0OOll : STD_LOGIC; + SIGNAL niOl0OOlO : STD_LOGIC; + SIGNAL niOl0OOOi : STD_LOGIC; + SIGNAL niOl0OOOl : STD_LOGIC; + SIGNAL niOl0OOOO : STD_LOGIC; + SIGNAL niOl1000i : STD_LOGIC; + SIGNAL niOl1000l : STD_LOGIC; + SIGNAL niOl1000O : STD_LOGIC; + SIGNAL niOl1001i : STD_LOGIC; + SIGNAL niOl1001l : STD_LOGIC; + SIGNAL niOl1001O : STD_LOGIC; + SIGNAL niOl100ii : STD_LOGIC; + SIGNAL niOl100il : STD_LOGIC; + SIGNAL niOl100iO : STD_LOGIC; + SIGNAL niOl100li : STD_LOGIC; + SIGNAL niOl100ll : STD_LOGIC; + SIGNAL niOl100lO : STD_LOGIC; + SIGNAL niOl100Oi : STD_LOGIC; + SIGNAL niOl100Ol : STD_LOGIC; + SIGNAL niOl100OO : STD_LOGIC; + SIGNAL niOl1010i : STD_LOGIC; + SIGNAL niOl1010l : STD_LOGIC; + SIGNAL niOl1010O : STD_LOGIC; + SIGNAL niOl1011i : STD_LOGIC; + SIGNAL niOl1011l : STD_LOGIC; + SIGNAL niOl1011O : STD_LOGIC; + SIGNAL niOl101ii : STD_LOGIC; + SIGNAL niOl101il : STD_LOGIC; + SIGNAL niOl101iO : STD_LOGIC; + SIGNAL niOl101li : STD_LOGIC; + SIGNAL niOl101ll : STD_LOGIC; + SIGNAL niOl101lO : STD_LOGIC; + SIGNAL niOl101Oi : STD_LOGIC; + SIGNAL niOl101Ol : STD_LOGIC; + SIGNAL niOl101OO : STD_LOGIC; + SIGNAL niOl10i0i : STD_LOGIC; + SIGNAL niOl10i0l : STD_LOGIC; + SIGNAL niOl10i0O : STD_LOGIC; + SIGNAL niOl10i1i : STD_LOGIC; + SIGNAL niOl10i1l : STD_LOGIC; + SIGNAL niOl10i1O : STD_LOGIC; + SIGNAL niOl10iii : STD_LOGIC; + SIGNAL niOl10iil : STD_LOGIC; + SIGNAL niOl10iiO : STD_LOGIC; + SIGNAL niOl10ili : STD_LOGIC; + SIGNAL niOl10ill : STD_LOGIC; + SIGNAL niOl10ilO : STD_LOGIC; + SIGNAL niOl10iOi : STD_LOGIC; + SIGNAL niOl10iOl : STD_LOGIC; + SIGNAL niOl10iOO : STD_LOGIC; + SIGNAL niOl10l0i : STD_LOGIC; + SIGNAL niOl10l0l : STD_LOGIC; + SIGNAL niOl10l0O : STD_LOGIC; + SIGNAL niOl10l1i : STD_LOGIC; + SIGNAL niOl10l1l : STD_LOGIC; + SIGNAL niOl10l1O : STD_LOGIC; + SIGNAL niOl10lii : STD_LOGIC; + SIGNAL niOl10lil : STD_LOGIC; + SIGNAL niOl10liO : STD_LOGIC; + SIGNAL niOl10lli : STD_LOGIC; + SIGNAL niOl10lll : STD_LOGIC; + SIGNAL niOl10llO : STD_LOGIC; + SIGNAL niOl10lOi : STD_LOGIC; + SIGNAL niOl10lOl : STD_LOGIC; + SIGNAL niOl10lOO : STD_LOGIC; + SIGNAL niOl10O0i : STD_LOGIC; + SIGNAL niOl10O0l : STD_LOGIC; + SIGNAL niOl10O0O : STD_LOGIC; + SIGNAL niOl10O1i : STD_LOGIC; + SIGNAL niOl10O1l : STD_LOGIC; + SIGNAL niOl10O1O : STD_LOGIC; + SIGNAL niOl10Oii : STD_LOGIC; + SIGNAL niOl10Oil : STD_LOGIC; + SIGNAL niOl10OiO : STD_LOGIC; + SIGNAL niOl10Oli : STD_LOGIC; + SIGNAL niOl10Oll : STD_LOGIC; + SIGNAL niOl10OlO : STD_LOGIC; + SIGNAL niOl10OOi : STD_LOGIC; + SIGNAL niOl10OOl : STD_LOGIC; + SIGNAL niOl10OOO : STD_LOGIC; + SIGNAL niOl1100i : STD_LOGIC; + SIGNAL niOl1100l : STD_LOGIC; + SIGNAL niOl1100O : STD_LOGIC; + SIGNAL niOl1101i : STD_LOGIC; + SIGNAL niOl1101l : STD_LOGIC; + SIGNAL niOl1101O : STD_LOGIC; + SIGNAL niOl110ii : STD_LOGIC; + SIGNAL niOl110il : STD_LOGIC; + SIGNAL niOl110iO : STD_LOGIC; + SIGNAL niOl110li : STD_LOGIC; + SIGNAL niOl110ll : STD_LOGIC; + SIGNAL niOl110lO : STD_LOGIC; + SIGNAL niOl110Oi : STD_LOGIC; + SIGNAL niOl110Ol : STD_LOGIC; + SIGNAL niOl110OO : STD_LOGIC; + SIGNAL niOl1110i : STD_LOGIC; + SIGNAL niOl1110l : STD_LOGIC; + SIGNAL niOl1110O : STD_LOGIC; + SIGNAL niOl1111i : STD_LOGIC; + SIGNAL niOl1111l : STD_LOGIC; + SIGNAL niOl1111O : STD_LOGIC; + SIGNAL niOl111ii : STD_LOGIC; + SIGNAL niOl111il : STD_LOGIC; + SIGNAL niOl111iO : STD_LOGIC; + SIGNAL niOl111li : STD_LOGIC; + SIGNAL niOl111ll : STD_LOGIC; + SIGNAL niOl111lO : STD_LOGIC; + SIGNAL niOl111Oi : STD_LOGIC; + SIGNAL niOl111Ol : STD_LOGIC; + SIGNAL niOl111OO : STD_LOGIC; + SIGNAL niOl11i0i : STD_LOGIC; + SIGNAL niOl11i0l : STD_LOGIC; + SIGNAL niOl11i0O : STD_LOGIC; + SIGNAL niOl11i1i : STD_LOGIC; + SIGNAL niOl11i1l : STD_LOGIC; + SIGNAL niOl11i1O : STD_LOGIC; + SIGNAL niOl11iii : STD_LOGIC; + SIGNAL niOl11iil : STD_LOGIC; + SIGNAL niOl11iiO : STD_LOGIC; + SIGNAL niOl11ili : STD_LOGIC; + SIGNAL niOl11ill : STD_LOGIC; + SIGNAL niOl11ilO : STD_LOGIC; + SIGNAL niOl11iOi : STD_LOGIC; + SIGNAL niOl11iOl : STD_LOGIC; + SIGNAL niOl11iOO : STD_LOGIC; + SIGNAL niOl11l0i : STD_LOGIC; + SIGNAL niOl11l0l : STD_LOGIC; + SIGNAL niOl11l0O : STD_LOGIC; + SIGNAL niOl11l1i : STD_LOGIC; + SIGNAL niOl11l1l : STD_LOGIC; + SIGNAL niOl11l1O : STD_LOGIC; + SIGNAL niOl11lii : STD_LOGIC; + SIGNAL niOl11lil : STD_LOGIC; + SIGNAL niOl11liO : STD_LOGIC; + SIGNAL niOl11lli : STD_LOGIC; + SIGNAL niOl11lll : STD_LOGIC; + SIGNAL niOl11llO : STD_LOGIC; + SIGNAL niOl11lOi : STD_LOGIC; + SIGNAL niOl11lOl : STD_LOGIC; + SIGNAL niOl11lOO : STD_LOGIC; + SIGNAL niOl11O0i : STD_LOGIC; + SIGNAL niOl11O0l : STD_LOGIC; + SIGNAL niOl11O0O : STD_LOGIC; + SIGNAL niOl11O1i : STD_LOGIC; + SIGNAL niOl11O1l : STD_LOGIC; + SIGNAL niOl11O1O : STD_LOGIC; + SIGNAL niOl11Oii : STD_LOGIC; + SIGNAL niOl11Oil : STD_LOGIC; + SIGNAL niOl11OiO : STD_LOGIC; + SIGNAL niOl11Oli : STD_LOGIC; + SIGNAL niOl11Oll : STD_LOGIC; + SIGNAL niOl11OlO : STD_LOGIC; + SIGNAL niOl11OOi : STD_LOGIC; + SIGNAL niOl11OOl : STD_LOGIC; + SIGNAL niOl11OOO : STD_LOGIC; + SIGNAL niOl1i00i : STD_LOGIC; + SIGNAL niOl1i00l : STD_LOGIC; + SIGNAL niOl1i00O : STD_LOGIC; + SIGNAL niOl1i01i : STD_LOGIC; + SIGNAL niOl1i01l : STD_LOGIC; + SIGNAL niOl1i01O : STD_LOGIC; + SIGNAL niOl1i0ii : STD_LOGIC; + SIGNAL niOl1i0il : STD_LOGIC; + SIGNAL niOl1i0iO : STD_LOGIC; + SIGNAL niOl1i0li : STD_LOGIC; + SIGNAL niOl1i0ll : STD_LOGIC; + SIGNAL niOl1i0lO : STD_LOGIC; + SIGNAL niOl1i0Oi : STD_LOGIC; + SIGNAL niOl1i0Ol : STD_LOGIC; + SIGNAL niOl1i0OO : STD_LOGIC; + SIGNAL niOl1i10i : STD_LOGIC; + SIGNAL niOl1i10l : STD_LOGIC; + SIGNAL niOl1i10O : STD_LOGIC; + SIGNAL niOl1i11i : STD_LOGIC; + SIGNAL niOl1i11l : STD_LOGIC; + SIGNAL niOl1i11O : STD_LOGIC; + SIGNAL niOl1i1ii : STD_LOGIC; + SIGNAL niOl1i1il : STD_LOGIC; + SIGNAL niOl1i1iO : STD_LOGIC; + SIGNAL niOl1i1li : STD_LOGIC; + SIGNAL niOl1i1ll : STD_LOGIC; + SIGNAL niOl1i1lO : STD_LOGIC; + SIGNAL niOl1i1Oi : STD_LOGIC; + SIGNAL niOl1i1Ol : STD_LOGIC; + SIGNAL niOl1i1OO : STD_LOGIC; + SIGNAL niOl1ii0i : STD_LOGIC; + SIGNAL niOl1ii0l : STD_LOGIC; + SIGNAL niOl1ii0O : STD_LOGIC; + SIGNAL niOl1ii1i : STD_LOGIC; + SIGNAL niOl1ii1l : STD_LOGIC; + SIGNAL niOl1ii1O : STD_LOGIC; + SIGNAL niOl1iiii : STD_LOGIC; + SIGNAL niOl1iiil : STD_LOGIC; + SIGNAL niOl1iiiO : STD_LOGIC; + SIGNAL niOl1iili : STD_LOGIC; + SIGNAL niOl1iill : STD_LOGIC; + SIGNAL niOl1iilO : STD_LOGIC; + SIGNAL niOl1iiOi : STD_LOGIC; + SIGNAL niOl1iiOl : STD_LOGIC; + SIGNAL niOl1iiOO : STD_LOGIC; + SIGNAL niOl1il0i : STD_LOGIC; + SIGNAL niOl1il0l : STD_LOGIC; + SIGNAL niOl1il0O : STD_LOGIC; + SIGNAL niOl1il1i : STD_LOGIC; + SIGNAL niOl1il1l : STD_LOGIC; + SIGNAL niOl1il1O : STD_LOGIC; + SIGNAL niOl1ilii : STD_LOGIC; + SIGNAL niOl1ilil : STD_LOGIC; + SIGNAL niOl1iliO : STD_LOGIC; + SIGNAL niOl1illi : STD_LOGIC; + SIGNAL niOl1illl : STD_LOGIC; + SIGNAL niOl1illO : STD_LOGIC; + SIGNAL niOl1ilOi : STD_LOGIC; + SIGNAL niOl1ilOl : STD_LOGIC; + SIGNAL niOl1ilOO : STD_LOGIC; + SIGNAL niOl1iO0i : STD_LOGIC; + SIGNAL niOl1iO0l : STD_LOGIC; + SIGNAL niOl1iO0O : STD_LOGIC; + SIGNAL niOl1iO1i : STD_LOGIC; + SIGNAL niOl1iO1l : STD_LOGIC; + SIGNAL niOl1iO1O : STD_LOGIC; + SIGNAL niOl1iOii : STD_LOGIC; + SIGNAL niOl1iOil : STD_LOGIC; + SIGNAL niOl1iOiO : STD_LOGIC; + SIGNAL niOl1iOli : STD_LOGIC; + SIGNAL niOl1iOll : STD_LOGIC; + SIGNAL niOl1iOlO : STD_LOGIC; + SIGNAL niOl1iOOi : STD_LOGIC; + SIGNAL niOl1iOOl : STD_LOGIC; + SIGNAL niOl1iOOO : STD_LOGIC; + SIGNAL niOl1l00i : STD_LOGIC; + SIGNAL niOl1l00l : STD_LOGIC; + SIGNAL niOl1l00O : STD_LOGIC; + SIGNAL niOl1l01i : STD_LOGIC; + SIGNAL niOl1l01l : STD_LOGIC; + SIGNAL niOl1l01O : STD_LOGIC; + SIGNAL niOl1l0ii : STD_LOGIC; + SIGNAL niOl1l0il : STD_LOGIC; + SIGNAL niOl1l0iO : STD_LOGIC; + SIGNAL niOl1l0li : STD_LOGIC; + SIGNAL niOl1l0ll : STD_LOGIC; + SIGNAL niOl1l0lO : STD_LOGIC; + SIGNAL niOl1l0Oi : STD_LOGIC; + SIGNAL niOl1l0Ol : STD_LOGIC; + SIGNAL niOl1l0OO : STD_LOGIC; + SIGNAL niOl1l10i : STD_LOGIC; + SIGNAL niOl1l10l : STD_LOGIC; + SIGNAL niOl1l10O : STD_LOGIC; + SIGNAL niOl1l11i : STD_LOGIC; + SIGNAL niOl1l11l : STD_LOGIC; + SIGNAL niOl1l11O : STD_LOGIC; + SIGNAL niOl1l1ii : STD_LOGIC; + SIGNAL niOl1l1il : STD_LOGIC; + SIGNAL niOl1l1iO : STD_LOGIC; + SIGNAL niOl1l1li : STD_LOGIC; + SIGNAL niOl1l1ll : STD_LOGIC; + SIGNAL niOl1l1lO : STD_LOGIC; + SIGNAL niOl1l1Oi : STD_LOGIC; + SIGNAL niOl1l1Ol : STD_LOGIC; + SIGNAL niOl1l1OO : STD_LOGIC; + SIGNAL niOl1li0i : STD_LOGIC; + SIGNAL niOl1li0l : STD_LOGIC; + SIGNAL niOl1li0O : STD_LOGIC; + SIGNAL niOl1li1i : STD_LOGIC; + SIGNAL niOl1li1l : STD_LOGIC; + SIGNAL niOl1li1O : STD_LOGIC; + SIGNAL niOl1liii : STD_LOGIC; + SIGNAL niOl1liil : STD_LOGIC; + SIGNAL niOl1liiO : STD_LOGIC; + SIGNAL niOl1lili : STD_LOGIC; + SIGNAL niOl1lill : STD_LOGIC; + SIGNAL niOl1lilO : STD_LOGIC; + SIGNAL niOl1liOi : STD_LOGIC; + SIGNAL niOl1liOl : STD_LOGIC; + SIGNAL niOl1liOO : STD_LOGIC; + SIGNAL niOl1ll0i : STD_LOGIC; + SIGNAL niOl1ll0l : STD_LOGIC; + SIGNAL niOl1ll0O : STD_LOGIC; + SIGNAL niOl1ll1i : STD_LOGIC; + SIGNAL niOl1ll1l : STD_LOGIC; + SIGNAL niOl1ll1O : STD_LOGIC; + SIGNAL niOl1llii : STD_LOGIC; + SIGNAL niOl1llil : STD_LOGIC; + SIGNAL niOl1lliO : STD_LOGIC; + SIGNAL niOl1llli : STD_LOGIC; + SIGNAL niOl1llll : STD_LOGIC; + SIGNAL niOl1lllO : STD_LOGIC; + SIGNAL niOl1llOi : STD_LOGIC; + SIGNAL niOl1llOl : STD_LOGIC; + SIGNAL niOl1llOO : STD_LOGIC; + SIGNAL niOl1lO0i : STD_LOGIC; + SIGNAL niOl1lO0l : STD_LOGIC; + SIGNAL niOl1lO0O : STD_LOGIC; + SIGNAL niOl1lO1i : STD_LOGIC; + SIGNAL niOl1lO1l : STD_LOGIC; + SIGNAL niOl1lO1O : STD_LOGIC; + SIGNAL niOl1lOii : STD_LOGIC; + SIGNAL niOl1lOil : STD_LOGIC; + SIGNAL niOl1lOiO : STD_LOGIC; + SIGNAL niOl1lOli : STD_LOGIC; + SIGNAL niOl1lOll : STD_LOGIC; + SIGNAL niOl1lOlO : STD_LOGIC; + SIGNAL niOl1lOOi : STD_LOGIC; + SIGNAL niOl1lOOl : STD_LOGIC; + SIGNAL niOl1lOOO : STD_LOGIC; + SIGNAL niOl1O00i : STD_LOGIC; + SIGNAL niOl1O00l : STD_LOGIC; + SIGNAL niOl1O00O : STD_LOGIC; + SIGNAL niOl1O01i : STD_LOGIC; + SIGNAL niOl1O01l : STD_LOGIC; + SIGNAL niOl1O01O : STD_LOGIC; + SIGNAL niOl1O0ii : STD_LOGIC; + SIGNAL niOl1O0il : STD_LOGIC; + SIGNAL niOl1O0iO : STD_LOGIC; + SIGNAL niOl1O0li : STD_LOGIC; + SIGNAL niOl1O0ll : STD_LOGIC; + SIGNAL niOl1O0lO : STD_LOGIC; + SIGNAL niOl1O0Oi : STD_LOGIC; + SIGNAL niOl1O0Ol : STD_LOGIC; + SIGNAL niOl1O0OO : STD_LOGIC; + SIGNAL niOl1O10i : STD_LOGIC; + SIGNAL niOl1O10l : STD_LOGIC; + SIGNAL niOl1O10O : STD_LOGIC; + SIGNAL niOl1O11i : STD_LOGIC; + SIGNAL niOl1O11l : STD_LOGIC; + SIGNAL niOl1O11O : STD_LOGIC; + SIGNAL niOl1O1ii : STD_LOGIC; + SIGNAL niOl1O1il : STD_LOGIC; + SIGNAL niOl1O1iO : STD_LOGIC; + SIGNAL niOl1O1li : STD_LOGIC; + SIGNAL niOl1O1ll : STD_LOGIC; + SIGNAL niOl1O1lO : STD_LOGIC; + SIGNAL niOl1O1Oi : STD_LOGIC; + SIGNAL niOl1O1Ol : STD_LOGIC; + SIGNAL niOl1O1OO : STD_LOGIC; + SIGNAL niOl1Oi0i : STD_LOGIC; + SIGNAL niOl1Oi0l : STD_LOGIC; + SIGNAL niOl1Oi0O : STD_LOGIC; + SIGNAL niOl1Oi1i : STD_LOGIC; + SIGNAL niOl1Oi1l : STD_LOGIC; + SIGNAL niOl1Oi1O : STD_LOGIC; + SIGNAL niOl1Oiii : STD_LOGIC; + SIGNAL niOl1Oiil : STD_LOGIC; + SIGNAL niOl1OiiO : STD_LOGIC; + SIGNAL niOl1Oili : STD_LOGIC; + SIGNAL niOl1Oill : STD_LOGIC; + SIGNAL niOl1OilO : STD_LOGIC; + SIGNAL niOl1OiOi : STD_LOGIC; + SIGNAL niOl1OiOl : STD_LOGIC; + SIGNAL niOl1OiOO : STD_LOGIC; + SIGNAL niOl1Ol0i : STD_LOGIC; + SIGNAL niOl1Ol0l : STD_LOGIC; + SIGNAL niOl1Ol0O : STD_LOGIC; + SIGNAL niOl1Ol1i : STD_LOGIC; + SIGNAL niOl1Ol1l : STD_LOGIC; + SIGNAL niOl1Ol1O : STD_LOGIC; + SIGNAL niOl1Olii : STD_LOGIC; + SIGNAL niOl1Olil : STD_LOGIC; + SIGNAL niOl1OliO : STD_LOGIC; + SIGNAL niOl1Olli : STD_LOGIC; + SIGNAL niOl1Olll : STD_LOGIC; + SIGNAL niOl1OllO : STD_LOGIC; + SIGNAL niOl1OlOi : STD_LOGIC; + SIGNAL niOl1OlOl : STD_LOGIC; + SIGNAL niOl1OlOO : STD_LOGIC; + SIGNAL niOl1OO0i : STD_LOGIC; + SIGNAL niOl1OO0l : STD_LOGIC; + SIGNAL niOl1OO0O : STD_LOGIC; + SIGNAL niOl1OO1i : STD_LOGIC; + SIGNAL niOl1OO1l : STD_LOGIC; + SIGNAL niOl1OO1O : STD_LOGIC; + SIGNAL niOl1OOii : STD_LOGIC; + SIGNAL niOl1OOil : STD_LOGIC; + SIGNAL niOl1OOiO : STD_LOGIC; + SIGNAL niOl1OOli : STD_LOGIC; + SIGNAL niOl1OOll : STD_LOGIC; + SIGNAL niOl1OOlO : STD_LOGIC; + SIGNAL niOl1OOOi : STD_LOGIC; + SIGNAL niOl1OOOl : STD_LOGIC; + SIGNAL niOl1OOOO : STD_LOGIC; + SIGNAL niOli000i : STD_LOGIC; + SIGNAL niOli000l : STD_LOGIC; + SIGNAL niOli000O : STD_LOGIC; + SIGNAL niOli001i : STD_LOGIC; + SIGNAL niOli001l : STD_LOGIC; + SIGNAL niOli001O : STD_LOGIC; + SIGNAL niOli00ii : STD_LOGIC; + SIGNAL niOli00il : STD_LOGIC; + SIGNAL niOli00iO : STD_LOGIC; + SIGNAL niOli00li : STD_LOGIC; + SIGNAL niOli00ll : STD_LOGIC; + SIGNAL niOli00lO : STD_LOGIC; + SIGNAL niOli00Oi : STD_LOGIC; + SIGNAL niOli00Ol : STD_LOGIC; + SIGNAL niOli00OO : STD_LOGIC; + SIGNAL niOli010i : STD_LOGIC; + SIGNAL niOli010l : STD_LOGIC; + SIGNAL niOli010O : STD_LOGIC; + SIGNAL niOli011i : STD_LOGIC; + SIGNAL niOli011l : STD_LOGIC; + SIGNAL niOli011O : STD_LOGIC; + SIGNAL niOli01ii : STD_LOGIC; + SIGNAL niOli01il : STD_LOGIC; + SIGNAL niOli01iO : STD_LOGIC; + SIGNAL niOli01li : STD_LOGIC; + SIGNAL niOli01ll : STD_LOGIC; + SIGNAL niOli01lO : STD_LOGIC; + SIGNAL niOli01Oi : STD_LOGIC; + SIGNAL niOli01Ol : STD_LOGIC; + SIGNAL niOli01OO : STD_LOGIC; + SIGNAL niOli0i0i : STD_LOGIC; + SIGNAL niOli0i0l : STD_LOGIC; + SIGNAL niOli0i0O : STD_LOGIC; + SIGNAL niOli0i1i : STD_LOGIC; + SIGNAL niOli0i1l : STD_LOGIC; + SIGNAL niOli0i1O : STD_LOGIC; + SIGNAL niOli0iii : STD_LOGIC; + SIGNAL niOli0iil : STD_LOGIC; + SIGNAL niOli0iiO : STD_LOGIC; + SIGNAL niOli0ili : STD_LOGIC; + SIGNAL niOli0ill : STD_LOGIC; + SIGNAL niOli0ilO : STD_LOGIC; + SIGNAL niOli0iOi : STD_LOGIC; + SIGNAL niOli0iOl : STD_LOGIC; + SIGNAL niOli0iOO : STD_LOGIC; + SIGNAL niOli0l0i : STD_LOGIC; + SIGNAL niOli0l0l : STD_LOGIC; + SIGNAL niOli0l0O : STD_LOGIC; + SIGNAL niOli0l1i : STD_LOGIC; + SIGNAL niOli0l1l : STD_LOGIC; + SIGNAL niOli0l1O : STD_LOGIC; + SIGNAL niOli0lii : STD_LOGIC; + SIGNAL niOli0lil : STD_LOGIC; + SIGNAL niOli0liO : STD_LOGIC; + SIGNAL niOli0lli : STD_LOGIC; + SIGNAL niOli0lll : STD_LOGIC; + SIGNAL niOli0llO : STD_LOGIC; + SIGNAL niOli0lOi : STD_LOGIC; + SIGNAL niOli0lOl : STD_LOGIC; + SIGNAL niOli0lOO : STD_LOGIC; + SIGNAL niOli0O0i : STD_LOGIC; + SIGNAL niOli0O0l : STD_LOGIC; + SIGNAL niOli0O0O : STD_LOGIC; + SIGNAL niOli0O1i : STD_LOGIC; + SIGNAL niOli0O1l : STD_LOGIC; + SIGNAL niOli0O1O : STD_LOGIC; + SIGNAL niOli0Oii : STD_LOGIC; + SIGNAL niOli0Oil : STD_LOGIC; + SIGNAL niOli0OiO : STD_LOGIC; + SIGNAL niOli0Oli : STD_LOGIC; + SIGNAL niOli0Oll : STD_LOGIC; + SIGNAL niOli0OlO : STD_LOGIC; + SIGNAL niOli0OOi : STD_LOGIC; + SIGNAL niOli0OOl : STD_LOGIC; + SIGNAL niOli0OOO : STD_LOGIC; + SIGNAL niOli100i : STD_LOGIC; + SIGNAL niOli100l : STD_LOGIC; + SIGNAL niOli100O : STD_LOGIC; + SIGNAL niOli101i : STD_LOGIC; + SIGNAL niOli101l : STD_LOGIC; + SIGNAL niOli101O : STD_LOGIC; + SIGNAL niOli10ii : STD_LOGIC; + SIGNAL niOli10il : STD_LOGIC; + SIGNAL niOli10iO : STD_LOGIC; + SIGNAL niOli10li : STD_LOGIC; + SIGNAL niOli10ll : STD_LOGIC; + SIGNAL niOli10lO : STD_LOGIC; + SIGNAL niOli10Oi : STD_LOGIC; + SIGNAL niOli10Ol : STD_LOGIC; + SIGNAL niOli10OO : STD_LOGIC; + SIGNAL niOli110i : STD_LOGIC; + SIGNAL niOli110l : STD_LOGIC; + SIGNAL niOli110O : STD_LOGIC; + SIGNAL niOli111i : STD_LOGIC; + SIGNAL niOli111l : STD_LOGIC; + SIGNAL niOli111O : STD_LOGIC; + SIGNAL niOli11ii : STD_LOGIC; + SIGNAL niOli11il : STD_LOGIC; + SIGNAL niOli11iO : STD_LOGIC; + SIGNAL niOli11li : STD_LOGIC; + SIGNAL niOli11ll : STD_LOGIC; + SIGNAL niOli11lO : STD_LOGIC; + SIGNAL niOli11Oi : STD_LOGIC; + SIGNAL niOli11Ol : STD_LOGIC; + SIGNAL niOli11OO : STD_LOGIC; + SIGNAL niOli1i0i : STD_LOGIC; + SIGNAL niOli1i0l : STD_LOGIC; + SIGNAL niOli1i0O : STD_LOGIC; + SIGNAL niOli1i1i : STD_LOGIC; + SIGNAL niOli1i1l : STD_LOGIC; + SIGNAL niOli1i1O : STD_LOGIC; + SIGNAL niOli1iii : STD_LOGIC; + SIGNAL niOli1iil : STD_LOGIC; + SIGNAL niOli1iiO : STD_LOGIC; + SIGNAL niOli1ili : STD_LOGIC; + SIGNAL niOli1ill : STD_LOGIC; + SIGNAL niOli1ilO : STD_LOGIC; + SIGNAL niOli1iOi : STD_LOGIC; + SIGNAL niOli1iOl : STD_LOGIC; + SIGNAL niOli1iOO : STD_LOGIC; + SIGNAL niOli1l0i : STD_LOGIC; + SIGNAL niOli1l0l : STD_LOGIC; + SIGNAL niOli1l0O : STD_LOGIC; + SIGNAL niOli1l1i : STD_LOGIC; + SIGNAL niOli1l1l : STD_LOGIC; + SIGNAL niOli1l1O : STD_LOGIC; + SIGNAL niOli1lii : STD_LOGIC; + SIGNAL niOli1lil : STD_LOGIC; + SIGNAL niOli1liO : STD_LOGIC; + SIGNAL niOli1lli : STD_LOGIC; + SIGNAL niOli1lll : STD_LOGIC; + SIGNAL niOli1llO : STD_LOGIC; + SIGNAL niOli1lOi : STD_LOGIC; + SIGNAL niOli1lOl : STD_LOGIC; + SIGNAL niOli1lOO : STD_LOGIC; + SIGNAL niOli1O0i : STD_LOGIC; + SIGNAL niOli1O0l : STD_LOGIC; + SIGNAL niOli1O0O : STD_LOGIC; + SIGNAL niOli1O1i : STD_LOGIC; + SIGNAL niOli1O1l : STD_LOGIC; + SIGNAL niOli1O1O : STD_LOGIC; + SIGNAL niOli1Oii : STD_LOGIC; + SIGNAL niOli1Oil : STD_LOGIC; + SIGNAL niOli1OiO : STD_LOGIC; + SIGNAL niOli1Oli : STD_LOGIC; + SIGNAL niOli1Oll : STD_LOGIC; + SIGNAL niOli1OlO : STD_LOGIC; + SIGNAL niOli1OOi : STD_LOGIC; + SIGNAL niOli1OOl : STD_LOGIC; + SIGNAL niOli1OOO : STD_LOGIC; + SIGNAL niOlii00i : STD_LOGIC; + SIGNAL niOlii00l : STD_LOGIC; + SIGNAL niOlii00O : STD_LOGIC; + SIGNAL niOlii01i : STD_LOGIC; + SIGNAL niOlii01l : STD_LOGIC; + SIGNAL niOlii01O : STD_LOGIC; + SIGNAL niOlii0ii : STD_LOGIC; + SIGNAL niOlii0il : STD_LOGIC; + SIGNAL niOlii0iO : STD_LOGIC; + SIGNAL niOlii0li : STD_LOGIC; + SIGNAL niOlii0ll : STD_LOGIC; + SIGNAL niOlii0lO : STD_LOGIC; + SIGNAL niOlii0Oi : STD_LOGIC; + SIGNAL niOlii0Ol : STD_LOGIC; + SIGNAL niOlii0OO : STD_LOGIC; + SIGNAL niOlii10i : STD_LOGIC; + SIGNAL niOlii10l : STD_LOGIC; + SIGNAL niOlii10O : STD_LOGIC; + SIGNAL niOlii11i : STD_LOGIC; + SIGNAL niOlii11l : STD_LOGIC; + SIGNAL niOlii11O : STD_LOGIC; + SIGNAL niOlii1ii : STD_LOGIC; + SIGNAL niOlii1il : STD_LOGIC; + SIGNAL niOlii1iO : STD_LOGIC; + SIGNAL niOlii1li : STD_LOGIC; + SIGNAL niOlii1ll : STD_LOGIC; + SIGNAL niOlii1lO : STD_LOGIC; + SIGNAL niOlii1Oi : STD_LOGIC; + SIGNAL niOlii1Ol : STD_LOGIC; + SIGNAL niOlii1OO : STD_LOGIC; + SIGNAL niOliii0i : STD_LOGIC; + SIGNAL niOliii0l : STD_LOGIC; + SIGNAL niOliii0O : STD_LOGIC; + SIGNAL niOliii1i : STD_LOGIC; + SIGNAL niOliii1l : STD_LOGIC; + SIGNAL niOliii1O : STD_LOGIC; + SIGNAL niOliiiii : STD_LOGIC; + SIGNAL niOliiiil : STD_LOGIC; + SIGNAL niOliiiiO : STD_LOGIC; + SIGNAL niOliiili : STD_LOGIC; + SIGNAL niOliiill : STD_LOGIC; + SIGNAL niOliiilO : STD_LOGIC; + SIGNAL niOliiiOi : STD_LOGIC; + SIGNAL niOliiiOl : STD_LOGIC; + SIGNAL niOliiiOO : STD_LOGIC; + SIGNAL niOliil0i : STD_LOGIC; + SIGNAL niOliil0l : STD_LOGIC; + SIGNAL niOliil0O : STD_LOGIC; + SIGNAL niOliil1i : STD_LOGIC; + SIGNAL niOliil1l : STD_LOGIC; + SIGNAL niOliil1O : STD_LOGIC; + SIGNAL niOliilii : STD_LOGIC; + SIGNAL niOliilil : STD_LOGIC; + SIGNAL niOliiliO : STD_LOGIC; + SIGNAL niOliilli : STD_LOGIC; + SIGNAL niOliilll : STD_LOGIC; + SIGNAL niOliillO : STD_LOGIC; + SIGNAL niOliilOi : STD_LOGIC; + SIGNAL niOliilOl : STD_LOGIC; + SIGNAL niOliilOO : STD_LOGIC; + SIGNAL niOliiO0i : STD_LOGIC; + SIGNAL niOliiO0l : STD_LOGIC; + SIGNAL niOliiO0O : STD_LOGIC; + SIGNAL niOliiO1i : STD_LOGIC; + SIGNAL niOliiO1l : STD_LOGIC; + SIGNAL niOliiO1O : STD_LOGIC; + SIGNAL niOliiOii : STD_LOGIC; + SIGNAL niOliiOil : STD_LOGIC; + SIGNAL niOliiOiO : STD_LOGIC; + SIGNAL niOliiOli : STD_LOGIC; + SIGNAL niOliiOll : STD_LOGIC; + SIGNAL niOliiOlO : STD_LOGIC; + SIGNAL niOliiOOi : STD_LOGIC; + SIGNAL niOliiOOl : STD_LOGIC; + SIGNAL niOliiOOO : STD_LOGIC; + SIGNAL niOlil00i : STD_LOGIC; + SIGNAL niOlil00l : STD_LOGIC; + SIGNAL niOlil00O : STD_LOGIC; + SIGNAL niOlil01i : STD_LOGIC; + SIGNAL niOlil01l : STD_LOGIC; + SIGNAL niOlil01O : STD_LOGIC; + SIGNAL niOlil0ii : STD_LOGIC; + SIGNAL niOlil0il : STD_LOGIC; + SIGNAL niOlil0iO : STD_LOGIC; + SIGNAL niOlil0li : STD_LOGIC; + SIGNAL niOlil0ll : STD_LOGIC; + SIGNAL niOlil0lO : STD_LOGIC; + SIGNAL niOlil0Oi : STD_LOGIC; + SIGNAL niOlil0Ol : STD_LOGIC; + SIGNAL niOlil0OO : STD_LOGIC; + SIGNAL niOlil10i : STD_LOGIC; + SIGNAL niOlil10l : STD_LOGIC; + SIGNAL niOlil10O : STD_LOGIC; + SIGNAL niOlil11i : STD_LOGIC; + SIGNAL niOlil11l : STD_LOGIC; + SIGNAL niOlil11O : STD_LOGIC; + SIGNAL niOlil1ii : STD_LOGIC; + SIGNAL niOlil1il : STD_LOGIC; + SIGNAL niOlil1iO : STD_LOGIC; + SIGNAL niOlil1li : STD_LOGIC; + SIGNAL niOlil1ll : STD_LOGIC; + SIGNAL niOlil1lO : STD_LOGIC; + SIGNAL niOlil1Oi : STD_LOGIC; + SIGNAL niOlil1Ol : STD_LOGIC; + SIGNAL niOlil1OO : STD_LOGIC; + SIGNAL niOlili0i : STD_LOGIC; + SIGNAL niOlili0l : STD_LOGIC; + SIGNAL niOlili0O : STD_LOGIC; + SIGNAL niOlili1i : STD_LOGIC; + SIGNAL niOlili1l : STD_LOGIC; + SIGNAL niOlili1O : STD_LOGIC; + SIGNAL niOliliii : STD_LOGIC; + SIGNAL niOliliil : STD_LOGIC; + SIGNAL niOliliiO : STD_LOGIC; + SIGNAL niOlilili : STD_LOGIC; + SIGNAL niOlilill : STD_LOGIC; + SIGNAL niOlililO : STD_LOGIC; + SIGNAL niOliliOi : STD_LOGIC; + SIGNAL niOliliOl : STD_LOGIC; + SIGNAL niOliliOO : STD_LOGIC; + SIGNAL niOlill0i : STD_LOGIC; + SIGNAL niOlill0l : STD_LOGIC; + SIGNAL niOlill0O : STD_LOGIC; + SIGNAL niOlill1i : STD_LOGIC; + SIGNAL niOlill1l : STD_LOGIC; + SIGNAL niOlill1O : STD_LOGIC; + SIGNAL niOlillii : STD_LOGIC; + SIGNAL niOlillil : STD_LOGIC; + SIGNAL niOlilliO : STD_LOGIC; + SIGNAL niOlillli : STD_LOGIC; + SIGNAL niOlillll : STD_LOGIC; + SIGNAL niOlilllO : STD_LOGIC; + SIGNAL niOlillOi : STD_LOGIC; + SIGNAL niOlillOl : STD_LOGIC; + SIGNAL niOlillOO : STD_LOGIC; + SIGNAL niOlilO0i : STD_LOGIC; + SIGNAL niOlilO0l : STD_LOGIC; + SIGNAL niOlilO0O : STD_LOGIC; + SIGNAL niOlilO1i : STD_LOGIC; + SIGNAL niOlilO1l : STD_LOGIC; + SIGNAL niOlilO1O : STD_LOGIC; + SIGNAL niOlilOii : STD_LOGIC; + SIGNAL niOlilOil : STD_LOGIC; + SIGNAL niOlilOiO : STD_LOGIC; + SIGNAL niOlilOli : STD_LOGIC; + SIGNAL niOlilOll : STD_LOGIC; + SIGNAL niOlilOlO : STD_LOGIC; + SIGNAL niOlilOOi : STD_LOGIC; + SIGNAL niOlilOOl : STD_LOGIC; + SIGNAL niOlilOOO : STD_LOGIC; + SIGNAL niOliO00i : STD_LOGIC; + SIGNAL niOliO00l : STD_LOGIC; + SIGNAL niOliO00O : STD_LOGIC; + SIGNAL niOliO01i : STD_LOGIC; + SIGNAL niOliO01l : STD_LOGIC; + SIGNAL niOliO01O : STD_LOGIC; + SIGNAL niOliO0ii : STD_LOGIC; + SIGNAL niOliO0il : STD_LOGIC; + SIGNAL niOliO0iO : STD_LOGIC; + SIGNAL niOliO0li : STD_LOGIC; + SIGNAL niOliO0ll : STD_LOGIC; + SIGNAL niOliO0lO : STD_LOGIC; + SIGNAL niOliO0Oi : STD_LOGIC; + SIGNAL niOliO0Ol : STD_LOGIC; + SIGNAL niOliO0OO : STD_LOGIC; + SIGNAL niOliO10i : STD_LOGIC; + SIGNAL niOliO10l : STD_LOGIC; + SIGNAL niOliO10O : STD_LOGIC; + SIGNAL niOliO11i : STD_LOGIC; + SIGNAL niOliO11l : STD_LOGIC; + SIGNAL niOliO11O : STD_LOGIC; + SIGNAL niOliO1ii : STD_LOGIC; + SIGNAL niOliO1il : STD_LOGIC; + SIGNAL niOliO1iO : STD_LOGIC; + SIGNAL niOliO1li : STD_LOGIC; + SIGNAL niOliO1ll : STD_LOGIC; + SIGNAL niOliO1lO : STD_LOGIC; + SIGNAL niOliO1Oi : STD_LOGIC; + SIGNAL niOliO1Ol : STD_LOGIC; + SIGNAL niOliO1OO : STD_LOGIC; + SIGNAL niOliOi0i : STD_LOGIC; + SIGNAL niOliOi0l : STD_LOGIC; + SIGNAL niOliOi0O : STD_LOGIC; + SIGNAL niOliOi1i : STD_LOGIC; + SIGNAL niOliOi1l : STD_LOGIC; + SIGNAL niOliOi1O : STD_LOGIC; + SIGNAL niOliOiii : STD_LOGIC; + SIGNAL niOliOiil : STD_LOGIC; + SIGNAL niOliOiiO : STD_LOGIC; + SIGNAL niOliOili : STD_LOGIC; + SIGNAL niOliOill : STD_LOGIC; + SIGNAL niOliOilO : STD_LOGIC; + SIGNAL niOliOiOi : STD_LOGIC; + SIGNAL niOliOiOl : STD_LOGIC; + SIGNAL niOliOiOO : STD_LOGIC; + SIGNAL niOliOl0i : STD_LOGIC; + SIGNAL niOliOl0l : STD_LOGIC; + SIGNAL niOliOl0O : STD_LOGIC; + SIGNAL niOliOl1i : STD_LOGIC; + SIGNAL niOliOl1l : STD_LOGIC; + SIGNAL niOliOl1O : STD_LOGIC; + SIGNAL niOliOlii : STD_LOGIC; + SIGNAL niOliOlil : STD_LOGIC; + SIGNAL niOliOliO : STD_LOGIC; + SIGNAL niOliOlli : STD_LOGIC; + SIGNAL niOliOlll : STD_LOGIC; + SIGNAL niOliOllO : STD_LOGIC; + SIGNAL niOliOlOi : STD_LOGIC; + SIGNAL niOliOlOl : STD_LOGIC; + SIGNAL niOliOlOO : STD_LOGIC; + SIGNAL niOliOO0i : STD_LOGIC; + SIGNAL niOliOO0l : STD_LOGIC; + SIGNAL niOliOO0O : STD_LOGIC; + SIGNAL niOliOO1i : STD_LOGIC; + SIGNAL niOliOO1l : STD_LOGIC; + SIGNAL niOliOO1O : STD_LOGIC; + SIGNAL niOliOOii : STD_LOGIC; + SIGNAL niOliOOil : STD_LOGIC; + SIGNAL niOliOOiO : STD_LOGIC; + SIGNAL niOliOOli : STD_LOGIC; + SIGNAL niOliOOll : STD_LOGIC; + SIGNAL niOliOOlO : STD_LOGIC; + SIGNAL niOliOOOi : STD_LOGIC; + SIGNAL niOliOOOl : STD_LOGIC; + SIGNAL niOliOOOO : STD_LOGIC; + SIGNAL niOll000i : STD_LOGIC; + SIGNAL niOll000l : STD_LOGIC; + SIGNAL niOll000O : STD_LOGIC; + SIGNAL niOll001i : STD_LOGIC; + SIGNAL niOll001l : STD_LOGIC; + SIGNAL niOll001O : STD_LOGIC; + SIGNAL niOll00ii : STD_LOGIC; + SIGNAL niOll00il : STD_LOGIC; + SIGNAL niOll00iO : STD_LOGIC; + SIGNAL niOll00li : STD_LOGIC; + SIGNAL niOll00ll : STD_LOGIC; + SIGNAL niOll00lO : STD_LOGIC; + SIGNAL niOll00Oi : STD_LOGIC; + SIGNAL niOll00Ol : STD_LOGIC; + SIGNAL niOll00OO : STD_LOGIC; + SIGNAL niOll010i : STD_LOGIC; + SIGNAL niOll010l : STD_LOGIC; + SIGNAL niOll010O : STD_LOGIC; + SIGNAL niOll011i : STD_LOGIC; + SIGNAL niOll011l : STD_LOGIC; + SIGNAL niOll011O : STD_LOGIC; + SIGNAL niOll01ii : STD_LOGIC; + SIGNAL niOll01il : STD_LOGIC; + SIGNAL niOll01iO : STD_LOGIC; + SIGNAL niOll01li : STD_LOGIC; + SIGNAL niOll01ll : STD_LOGIC; + SIGNAL niOll01lO : STD_LOGIC; + SIGNAL niOll01Oi : STD_LOGIC; + SIGNAL niOll01Ol : STD_LOGIC; + SIGNAL niOll01OO : STD_LOGIC; + SIGNAL niOll0i0i : STD_LOGIC; + SIGNAL niOll0i0l : STD_LOGIC; + SIGNAL niOll0i0O : STD_LOGIC; + SIGNAL niOll0i1i : STD_LOGIC; + SIGNAL niOll0i1l : STD_LOGIC; + SIGNAL niOll0i1O : STD_LOGIC; + SIGNAL niOll0iii : STD_LOGIC; + SIGNAL niOll0iil : STD_LOGIC; + SIGNAL niOll0iiO : STD_LOGIC; + SIGNAL niOll0ili : STD_LOGIC; + SIGNAL niOll0ill : STD_LOGIC; + SIGNAL niOll0ilO : STD_LOGIC; + SIGNAL niOll0iOi : STD_LOGIC; + SIGNAL niOll0iOl : STD_LOGIC; + SIGNAL niOll0iOO : STD_LOGIC; + SIGNAL niOll0l0i : STD_LOGIC; + SIGNAL niOll0l0l : STD_LOGIC; + SIGNAL niOll0l0O : STD_LOGIC; + SIGNAL niOll0l1i : STD_LOGIC; + SIGNAL niOll0l1l : STD_LOGIC; + SIGNAL niOll0l1O : STD_LOGIC; + SIGNAL niOll0lii : STD_LOGIC; + SIGNAL niOll0lil : STD_LOGIC; + SIGNAL niOll0liO : STD_LOGIC; + SIGNAL niOll0lli : STD_LOGIC; + SIGNAL niOll0lll : STD_LOGIC; + SIGNAL niOll0llO : STD_LOGIC; + SIGNAL niOll0lOi : STD_LOGIC; + SIGNAL niOll0lOl : STD_LOGIC; + SIGNAL niOll0lOO : STD_LOGIC; + SIGNAL niOll0O0i : STD_LOGIC; + SIGNAL niOll0O0l : STD_LOGIC; + SIGNAL niOll0O0O : STD_LOGIC; + SIGNAL niOll0O1i : STD_LOGIC; + SIGNAL niOll0O1l : STD_LOGIC; + SIGNAL niOll0O1O : STD_LOGIC; + SIGNAL niOll0Oii : STD_LOGIC; + SIGNAL niOll0Oil : STD_LOGIC; + SIGNAL niOll0OiO : STD_LOGIC; + SIGNAL niOll0Oli : STD_LOGIC; + SIGNAL niOll0Oll : STD_LOGIC; + SIGNAL niOll0OlO : STD_LOGIC; + SIGNAL niOll0OOi : STD_LOGIC; + SIGNAL niOll0OOl : STD_LOGIC; + SIGNAL niOll0OOO : STD_LOGIC; + SIGNAL niOll100i : STD_LOGIC; + SIGNAL niOll100l : STD_LOGIC; + SIGNAL niOll100O : STD_LOGIC; + SIGNAL niOll101i : STD_LOGIC; + SIGNAL niOll101l : STD_LOGIC; + SIGNAL niOll101O : STD_LOGIC; + SIGNAL niOll10ii : STD_LOGIC; + SIGNAL niOll10il : STD_LOGIC; + SIGNAL niOll10iO : STD_LOGIC; + SIGNAL niOll10li : STD_LOGIC; + SIGNAL niOll10ll : STD_LOGIC; + SIGNAL niOll10lO : STD_LOGIC; + SIGNAL niOll10Oi : STD_LOGIC; + SIGNAL niOll10Ol : STD_LOGIC; + SIGNAL niOll10OO : STD_LOGIC; + SIGNAL niOll110i : STD_LOGIC; + SIGNAL niOll110l : STD_LOGIC; + SIGNAL niOll110O : STD_LOGIC; + SIGNAL niOll111i : STD_LOGIC; + SIGNAL niOll111l : STD_LOGIC; + SIGNAL niOll111O : STD_LOGIC; + SIGNAL niOll11ii : STD_LOGIC; + SIGNAL niOll11il : STD_LOGIC; + SIGNAL niOll11iO : STD_LOGIC; + SIGNAL niOll11li : STD_LOGIC; + SIGNAL niOll11ll : STD_LOGIC; + SIGNAL niOll11lO : STD_LOGIC; + SIGNAL niOll11Oi : STD_LOGIC; + SIGNAL niOll11Ol : STD_LOGIC; + SIGNAL niOll11OO : STD_LOGIC; + SIGNAL niOll1i0i : STD_LOGIC; + SIGNAL niOll1i0l : STD_LOGIC; + SIGNAL niOll1i0O : STD_LOGIC; + SIGNAL niOll1i1i : STD_LOGIC; + SIGNAL niOll1i1l : STD_LOGIC; + SIGNAL niOll1i1O : STD_LOGIC; + SIGNAL niOll1iii : STD_LOGIC; + SIGNAL niOll1iil : STD_LOGIC; + SIGNAL niOll1iiO : STD_LOGIC; + SIGNAL niOll1ili : STD_LOGIC; + SIGNAL niOll1ill : STD_LOGIC; + SIGNAL niOll1ilO : STD_LOGIC; + SIGNAL niOll1iOi : STD_LOGIC; + SIGNAL niOll1iOl : STD_LOGIC; + SIGNAL niOll1iOO : STD_LOGIC; + SIGNAL niOll1l0i : STD_LOGIC; + SIGNAL niOll1l0l : STD_LOGIC; + SIGNAL niOll1l0O : STD_LOGIC; + SIGNAL niOll1l1i : STD_LOGIC; + SIGNAL niOll1l1l : STD_LOGIC; + SIGNAL niOll1l1O : STD_LOGIC; + SIGNAL niOll1lii : STD_LOGIC; + SIGNAL niOll1lil : STD_LOGIC; + SIGNAL niOll1liO : STD_LOGIC; + SIGNAL niOll1lli : STD_LOGIC; + SIGNAL niOll1lll : STD_LOGIC; + SIGNAL niOll1llO : STD_LOGIC; + SIGNAL niOll1lOi : STD_LOGIC; + SIGNAL niOll1lOl : STD_LOGIC; + SIGNAL niOll1lOO : STD_LOGIC; + SIGNAL niOll1O0i : STD_LOGIC; + SIGNAL niOll1O0l : STD_LOGIC; + SIGNAL niOll1O0O : STD_LOGIC; + SIGNAL niOll1O1i : STD_LOGIC; + SIGNAL niOll1O1l : STD_LOGIC; + SIGNAL niOll1O1O : STD_LOGIC; + SIGNAL niOll1Oii : STD_LOGIC; + SIGNAL niOll1Oil : STD_LOGIC; + SIGNAL niOll1OiO : STD_LOGIC; + SIGNAL niOll1Oli : STD_LOGIC; + SIGNAL niOll1Oll : STD_LOGIC; + SIGNAL niOll1OlO : STD_LOGIC; + SIGNAL niOll1OOi : STD_LOGIC; + SIGNAL niOll1OOl : STD_LOGIC; + SIGNAL niOll1OOO : STD_LOGIC; + SIGNAL niOlli00i : STD_LOGIC; + SIGNAL niOlli00l : STD_LOGIC; + SIGNAL niOlli00O : STD_LOGIC; + SIGNAL niOlli01i : STD_LOGIC; + SIGNAL niOlli01l : STD_LOGIC; + SIGNAL niOlli01O : STD_LOGIC; + SIGNAL niOlli0ii : STD_LOGIC; + SIGNAL niOlli0il : STD_LOGIC; + SIGNAL niOlli0iO : STD_LOGIC; + SIGNAL niOlli0li : STD_LOGIC; + SIGNAL niOlli0ll : STD_LOGIC; + SIGNAL niOlli0lO : STD_LOGIC; + SIGNAL niOlli0Oi : STD_LOGIC; + SIGNAL niOlli0Ol : STD_LOGIC; + SIGNAL niOlli0OO : STD_LOGIC; + SIGNAL niOlli10i : STD_LOGIC; + SIGNAL niOlli10l : STD_LOGIC; + SIGNAL niOlli10O : STD_LOGIC; + SIGNAL niOlli11i : STD_LOGIC; + SIGNAL niOlli11l : STD_LOGIC; + SIGNAL niOlli11O : STD_LOGIC; + SIGNAL niOlli1ii : STD_LOGIC; + SIGNAL niOlli1il : STD_LOGIC; + SIGNAL niOlli1iO : STD_LOGIC; + SIGNAL niOlli1li : STD_LOGIC; + SIGNAL niOlli1ll : STD_LOGIC; + SIGNAL niOlli1lO : STD_LOGIC; + SIGNAL niOlli1Oi : STD_LOGIC; + SIGNAL niOlli1Ol : STD_LOGIC; + SIGNAL niOlli1OO : STD_LOGIC; + SIGNAL niOllii0i : STD_LOGIC; + SIGNAL niOllii0l : STD_LOGIC; + SIGNAL niOllii0O : STD_LOGIC; + SIGNAL niOllii1i : STD_LOGIC; + SIGNAL niOllii1l : STD_LOGIC; + SIGNAL niOllii1O : STD_LOGIC; + SIGNAL niOlliiii : STD_LOGIC; + SIGNAL niOlliiil : STD_LOGIC; + SIGNAL niOlliiiO : STD_LOGIC; + SIGNAL niOlliili : STD_LOGIC; + SIGNAL niOlliill : STD_LOGIC; + SIGNAL niOlliilO : STD_LOGIC; + SIGNAL niOlliiOi : STD_LOGIC; + SIGNAL niOlliiOl : STD_LOGIC; + SIGNAL niOlliiOO : STD_LOGIC; + SIGNAL niOllil0i : STD_LOGIC; + SIGNAL niOllil0l : STD_LOGIC; + SIGNAL niOllil0O : STD_LOGIC; + SIGNAL niOllil1i : STD_LOGIC; + SIGNAL niOllil1l : STD_LOGIC; + SIGNAL niOllil1O : STD_LOGIC; + SIGNAL niOllilii : STD_LOGIC; + SIGNAL niOllilil : STD_LOGIC; + SIGNAL niOlliliO : STD_LOGIC; + SIGNAL niOllilli : STD_LOGIC; + SIGNAL niOllilll : STD_LOGIC; + SIGNAL niOllillO : STD_LOGIC; + SIGNAL niOllilOi : STD_LOGIC; + SIGNAL niOllilOl : STD_LOGIC; + SIGNAL niOllilOO : STD_LOGIC; + SIGNAL niOlliO0i : STD_LOGIC; + SIGNAL niOlliO0l : STD_LOGIC; + SIGNAL niOlliO0O : STD_LOGIC; + SIGNAL niOlliO1i : STD_LOGIC; + SIGNAL niOlliO1l : STD_LOGIC; + SIGNAL niOlliO1O : STD_LOGIC; + SIGNAL niOlliOii : STD_LOGIC; + SIGNAL niOlliOil : STD_LOGIC; + SIGNAL niOlliOiO : STD_LOGIC; + SIGNAL niOlliOli : STD_LOGIC; + SIGNAL niOlliOll : STD_LOGIC; + SIGNAL niOlliOlO : STD_LOGIC; + SIGNAL niOlliOOi : STD_LOGIC; + SIGNAL niOlliOOl : STD_LOGIC; + SIGNAL niOlliOOO : STD_LOGIC; + SIGNAL niOlll00i : STD_LOGIC; + SIGNAL niOlll00l : STD_LOGIC; + SIGNAL niOlll00O : STD_LOGIC; + SIGNAL niOlll01i : STD_LOGIC; + SIGNAL niOlll01l : STD_LOGIC; + SIGNAL niOlll01O : STD_LOGIC; + SIGNAL niOlll0ii : STD_LOGIC; + SIGNAL niOlll0il : STD_LOGIC; + SIGNAL niOlll0iO : STD_LOGIC; + SIGNAL niOlll0li : STD_LOGIC; + SIGNAL niOlll0ll : STD_LOGIC; + SIGNAL niOlll0lO : STD_LOGIC; + SIGNAL niOlll0Oi : STD_LOGIC; + SIGNAL niOlll0Ol : STD_LOGIC; + SIGNAL niOlll0OO : STD_LOGIC; + SIGNAL niOlll10i : STD_LOGIC; + SIGNAL niOlll10l : STD_LOGIC; + SIGNAL niOlll10O : STD_LOGIC; + SIGNAL niOlll11i : STD_LOGIC; + SIGNAL niOlll11l : STD_LOGIC; + SIGNAL niOlll11O : STD_LOGIC; + SIGNAL niOlll1ii : STD_LOGIC; + SIGNAL niOlll1il : STD_LOGIC; + SIGNAL niOlll1iO : STD_LOGIC; + SIGNAL niOlll1li : STD_LOGIC; + SIGNAL niOlll1ll : STD_LOGIC; + SIGNAL niOlll1lO : STD_LOGIC; + SIGNAL niOlll1Oi : STD_LOGIC; + SIGNAL niOlll1Ol : STD_LOGIC; + SIGNAL niOlll1OO : STD_LOGIC; + SIGNAL niOllli0i : STD_LOGIC; + SIGNAL niOllli0l : STD_LOGIC; + SIGNAL niOllli0O : STD_LOGIC; + SIGNAL niOllli1i : STD_LOGIC; + SIGNAL niOllli1l : STD_LOGIC; + SIGNAL niOllli1O : STD_LOGIC; + SIGNAL niOllliii : STD_LOGIC; + SIGNAL niOllliil : STD_LOGIC; + SIGNAL niOllliiO : STD_LOGIC; + SIGNAL niOlllili : STD_LOGIC; + SIGNAL niOlllill : STD_LOGIC; + SIGNAL niOlllilO : STD_LOGIC; + SIGNAL niOllliOi : STD_LOGIC; + SIGNAL niOllliOl : STD_LOGIC; + SIGNAL niOllliOO : STD_LOGIC; + SIGNAL niOllll0i : STD_LOGIC; + SIGNAL niOllll0l : STD_LOGIC; + SIGNAL niOllll0O : STD_LOGIC; + SIGNAL niOllll1i : STD_LOGIC; + SIGNAL niOllll1l : STD_LOGIC; + SIGNAL niOllll1O : STD_LOGIC; + SIGNAL niOllllii : STD_LOGIC; + SIGNAL niOllllil : STD_LOGIC; + SIGNAL niOlllliO : STD_LOGIC; + SIGNAL niOllllli : STD_LOGIC; + SIGNAL niOllllll : STD_LOGIC; + SIGNAL niOlllllO : STD_LOGIC; + SIGNAL niOllllOi : STD_LOGIC; + SIGNAL niOllllOl : STD_LOGIC; + SIGNAL niOllllOO : STD_LOGIC; + SIGNAL niOlllO0i : STD_LOGIC; + SIGNAL niOlllO0l : STD_LOGIC; + SIGNAL niOlllO0O : STD_LOGIC; + SIGNAL niOlllO1i : STD_LOGIC; + SIGNAL niOlllO1l : STD_LOGIC; + SIGNAL niOlllO1O : STD_LOGIC; + SIGNAL niOlllOii : STD_LOGIC; + SIGNAL niOlllOil : STD_LOGIC; + SIGNAL niOlllOiO : STD_LOGIC; + SIGNAL niOlllOli : STD_LOGIC; + SIGNAL niOlllOll : STD_LOGIC; + SIGNAL niOlllOlO : STD_LOGIC; + SIGNAL niOlllOOi : STD_LOGIC; + SIGNAL niOlllOOl : STD_LOGIC; + SIGNAL niOlllOOO : STD_LOGIC; + SIGNAL niOllO00i : STD_LOGIC; + SIGNAL niOllO00l : STD_LOGIC; + SIGNAL niOllO00O : STD_LOGIC; + SIGNAL niOllO01i : STD_LOGIC; + SIGNAL niOllO01l : STD_LOGIC; + SIGNAL niOllO01O : STD_LOGIC; + SIGNAL niOllO0ii : STD_LOGIC; + SIGNAL niOllO0il : STD_LOGIC; + SIGNAL niOllO0iO : STD_LOGIC; + SIGNAL niOllO0li : STD_LOGIC; + SIGNAL niOllO0ll : STD_LOGIC; + SIGNAL niOllO0lO : STD_LOGIC; + SIGNAL niOllO0Oi : STD_LOGIC; + SIGNAL niOllO0Ol : STD_LOGIC; + SIGNAL niOllO0OO : STD_LOGIC; + SIGNAL niOllO10i : STD_LOGIC; + SIGNAL niOllO10l : STD_LOGIC; + SIGNAL niOllO10O : STD_LOGIC; + SIGNAL niOllO11i : STD_LOGIC; + SIGNAL niOllO11l : STD_LOGIC; + SIGNAL niOllO11O : STD_LOGIC; + SIGNAL niOllO1ii : STD_LOGIC; + SIGNAL niOllO1il : STD_LOGIC; + SIGNAL niOllO1iO : STD_LOGIC; + SIGNAL niOllO1li : STD_LOGIC; + SIGNAL niOllO1ll : STD_LOGIC; + SIGNAL niOllO1lO : STD_LOGIC; + SIGNAL niOllO1Oi : STD_LOGIC; + SIGNAL niOllO1Ol : STD_LOGIC; + SIGNAL niOllO1OO : STD_LOGIC; + SIGNAL niOllOi0i : STD_LOGIC; + SIGNAL niOllOi0l : STD_LOGIC; + SIGNAL niOllOi0O : STD_LOGIC; + SIGNAL niOllOi1i : STD_LOGIC; + SIGNAL niOllOi1l : STD_LOGIC; + SIGNAL niOllOi1O : STD_LOGIC; + SIGNAL niOllOiii : STD_LOGIC; + SIGNAL niOllOiil : STD_LOGIC; + SIGNAL niOllOiiO : STD_LOGIC; + SIGNAL niOllOili : STD_LOGIC; + SIGNAL niOllOill : STD_LOGIC; + SIGNAL niOllOilO : STD_LOGIC; + SIGNAL niOllOiOi : STD_LOGIC; + SIGNAL niOllOiOl : STD_LOGIC; + SIGNAL niOllOiOO : STD_LOGIC; + SIGNAL niOllOl0i : STD_LOGIC; + SIGNAL niOllOl0l : STD_LOGIC; + SIGNAL niOllOl0O : STD_LOGIC; + SIGNAL niOllOl1i : STD_LOGIC; + SIGNAL niOllOl1l : STD_LOGIC; + SIGNAL niOllOl1O : STD_LOGIC; + SIGNAL niOllOlii : STD_LOGIC; + SIGNAL niOllOlil : STD_LOGIC; + SIGNAL niOllOliO : STD_LOGIC; + SIGNAL niOllOlli : STD_LOGIC; + SIGNAL niOllOlll : STD_LOGIC; + SIGNAL niOllOllO : STD_LOGIC; + SIGNAL niOllOlOi : STD_LOGIC; + SIGNAL niOllOlOl : STD_LOGIC; + SIGNAL niOllOlOO : STD_LOGIC; + SIGNAL niOllOO0i : STD_LOGIC; + SIGNAL niOllOO0l : STD_LOGIC; + SIGNAL niOllOO0O : STD_LOGIC; + SIGNAL niOllOO1i : STD_LOGIC; + SIGNAL niOllOO1l : STD_LOGIC; + SIGNAL niOllOO1O : STD_LOGIC; + SIGNAL niOllOOii : STD_LOGIC; + SIGNAL niOllOOil : STD_LOGIC; + SIGNAL niOllOOiO : STD_LOGIC; + SIGNAL niOllOOli : STD_LOGIC; + SIGNAL niOllOOll : STD_LOGIC; + SIGNAL niOllOOlO : STD_LOGIC; + SIGNAL niOllOOOi : STD_LOGIC; + SIGNAL niOllOOOl : STD_LOGIC; + SIGNAL niOllOOOO : STD_LOGIC; + SIGNAL niOlO000i : STD_LOGIC; + SIGNAL niOlO000l : STD_LOGIC; + SIGNAL niOlO000O : STD_LOGIC; + SIGNAL niOlO001i : STD_LOGIC; + SIGNAL niOlO001l : STD_LOGIC; + SIGNAL niOlO001O : STD_LOGIC; + SIGNAL niOlO00ii : STD_LOGIC; + SIGNAL niOlO00il : STD_LOGIC; + SIGNAL niOlO00iO : STD_LOGIC; + SIGNAL niOlO00li : STD_LOGIC; + SIGNAL niOlO00ll : STD_LOGIC; + SIGNAL niOlO00lO : STD_LOGIC; + SIGNAL niOlO00Oi : STD_LOGIC; + SIGNAL niOlO00Ol : STD_LOGIC; + SIGNAL niOlO00OO : STD_LOGIC; + SIGNAL niOlO010i : STD_LOGIC; + SIGNAL niOlO010l : STD_LOGIC; + SIGNAL niOlO010O : STD_LOGIC; + SIGNAL niOlO011i : STD_LOGIC; + SIGNAL niOlO011l : STD_LOGIC; + SIGNAL niOlO011O : STD_LOGIC; + SIGNAL niOlO01ii : STD_LOGIC; + SIGNAL niOlO01il : STD_LOGIC; + SIGNAL niOlO01iO : STD_LOGIC; + SIGNAL niOlO01li : STD_LOGIC; + SIGNAL niOlO01ll : STD_LOGIC; + SIGNAL niOlO01lO : STD_LOGIC; + SIGNAL niOlO01Oi : STD_LOGIC; + SIGNAL niOlO01Ol : STD_LOGIC; + SIGNAL niOlO01OO : STD_LOGIC; + SIGNAL niOlO0i0i : STD_LOGIC; + SIGNAL niOlO0i0l : STD_LOGIC; + SIGNAL niOlO0i0O : STD_LOGIC; + SIGNAL niOlO0i1i : STD_LOGIC; + SIGNAL niOlO0i1l : STD_LOGIC; + SIGNAL niOlO0i1O : STD_LOGIC; + SIGNAL niOlO0iii : STD_LOGIC; + SIGNAL niOlO0iil : STD_LOGIC; + SIGNAL niOlO0iiO : STD_LOGIC; + SIGNAL niOlO0ili : STD_LOGIC; + SIGNAL niOlO0ill : STD_LOGIC; + SIGNAL niOlO0ilO : STD_LOGIC; + SIGNAL niOlO0iOi : STD_LOGIC; + SIGNAL niOlO0iOl : STD_LOGIC; + SIGNAL niOlO0iOO : STD_LOGIC; + SIGNAL niOlO0l0i : STD_LOGIC; + SIGNAL niOlO0l0l : STD_LOGIC; + SIGNAL niOlO0l0O : STD_LOGIC; + SIGNAL niOlO0l1i : STD_LOGIC; + SIGNAL niOlO0l1l : STD_LOGIC; + SIGNAL niOlO0l1O : STD_LOGIC; + SIGNAL niOlO0lii : STD_LOGIC; + SIGNAL niOlO0lil : STD_LOGIC; + SIGNAL niOlO0liO : STD_LOGIC; + SIGNAL niOlO0lli : STD_LOGIC; + SIGNAL niOlO0lll : STD_LOGIC; + SIGNAL niOlO0llO : STD_LOGIC; + SIGNAL niOlO0lOi : STD_LOGIC; + SIGNAL niOlO0lOl : STD_LOGIC; + SIGNAL niOlO0lOO : STD_LOGIC; + SIGNAL niOlO0O0i : STD_LOGIC; + SIGNAL niOlO0O0l : STD_LOGIC; + SIGNAL niOlO0O0O : STD_LOGIC; + SIGNAL niOlO0O1i : STD_LOGIC; + SIGNAL niOlO0O1l : STD_LOGIC; + SIGNAL niOlO0O1O : STD_LOGIC; + SIGNAL niOlO0Oii : STD_LOGIC; + SIGNAL niOlO0Oil : STD_LOGIC; + SIGNAL niOlO0OiO : STD_LOGIC; + SIGNAL niOlO0Oli : STD_LOGIC; + SIGNAL niOlO0Oll : STD_LOGIC; + SIGNAL niOlO0OlO : STD_LOGIC; + SIGNAL niOlO0OOi : STD_LOGIC; + SIGNAL niOlO0OOl : STD_LOGIC; + SIGNAL niOlO0OOO : STD_LOGIC; + SIGNAL niOlO100i : STD_LOGIC; + SIGNAL niOlO100l : STD_LOGIC; + SIGNAL niOlO100O : STD_LOGIC; + SIGNAL niOlO101i : STD_LOGIC; + SIGNAL niOlO101l : STD_LOGIC; + SIGNAL niOlO101O : STD_LOGIC; + SIGNAL niOlO10ii : STD_LOGIC; + SIGNAL niOlO10il : STD_LOGIC; + SIGNAL niOlO10iO : STD_LOGIC; + SIGNAL niOlO10li : STD_LOGIC; + SIGNAL niOlO10ll : STD_LOGIC; + SIGNAL niOlO10lO : STD_LOGIC; + SIGNAL niOlO10Oi : STD_LOGIC; + SIGNAL niOlO10Ol : STD_LOGIC; + SIGNAL niOlO10OO : STD_LOGIC; + SIGNAL niOlO110i : STD_LOGIC; + SIGNAL niOlO110l : STD_LOGIC; + SIGNAL niOlO110O : STD_LOGIC; + SIGNAL niOlO111i : STD_LOGIC; + SIGNAL niOlO111l : STD_LOGIC; + SIGNAL niOlO111O : STD_LOGIC; + SIGNAL niOlO11ii : STD_LOGIC; + SIGNAL niOlO11il : STD_LOGIC; + SIGNAL niOlO11iO : STD_LOGIC; + SIGNAL niOlO11li : STD_LOGIC; + SIGNAL niOlO11ll : STD_LOGIC; + SIGNAL niOlO11lO : STD_LOGIC; + SIGNAL niOlO11Oi : STD_LOGIC; + SIGNAL niOlO11Ol : STD_LOGIC; + SIGNAL niOlO11OO : STD_LOGIC; + SIGNAL niOlO1i0i : STD_LOGIC; + SIGNAL niOlO1i0l : STD_LOGIC; + SIGNAL niOlO1i0O : STD_LOGIC; + SIGNAL niOlO1i1i : STD_LOGIC; + SIGNAL niOlO1i1l : STD_LOGIC; + SIGNAL niOlO1i1O : STD_LOGIC; + SIGNAL niOlO1iii : STD_LOGIC; + SIGNAL niOlO1iil : STD_LOGIC; + SIGNAL niOlO1iiO : STD_LOGIC; + SIGNAL niOlO1ili : STD_LOGIC; + SIGNAL niOlO1ill : STD_LOGIC; + SIGNAL niOlO1ilO : STD_LOGIC; + SIGNAL niOlO1iOi : STD_LOGIC; + SIGNAL niOlO1iOl : STD_LOGIC; + SIGNAL niOlO1iOO : STD_LOGIC; + SIGNAL niOlO1l0i : STD_LOGIC; + SIGNAL niOlO1l0l : STD_LOGIC; + SIGNAL niOlO1l0O : STD_LOGIC; + SIGNAL niOlO1l1i : STD_LOGIC; + SIGNAL niOlO1l1l : STD_LOGIC; + SIGNAL niOlO1l1O : STD_LOGIC; + SIGNAL niOlO1lii : STD_LOGIC; + SIGNAL niOlO1lil : STD_LOGIC; + SIGNAL niOlO1liO : STD_LOGIC; + SIGNAL niOlO1lli : STD_LOGIC; + SIGNAL niOlO1lll : STD_LOGIC; + SIGNAL niOlO1llO : STD_LOGIC; + SIGNAL niOlO1lOi : STD_LOGIC; + SIGNAL niOlO1lOl : STD_LOGIC; + SIGNAL niOlO1lOO : STD_LOGIC; + SIGNAL niOlO1O0i : STD_LOGIC; + SIGNAL niOlO1O0l : STD_LOGIC; + SIGNAL niOlO1O0O : STD_LOGIC; + SIGNAL niOlO1O1i : STD_LOGIC; + SIGNAL niOlO1O1l : STD_LOGIC; + SIGNAL niOlO1O1O : STD_LOGIC; + SIGNAL niOlO1Oii : STD_LOGIC; + SIGNAL niOlO1Oil : STD_LOGIC; + SIGNAL niOlO1OiO : STD_LOGIC; + SIGNAL niOlO1Oli : STD_LOGIC; + SIGNAL niOlO1Oll : STD_LOGIC; + SIGNAL niOlO1OlO : STD_LOGIC; + SIGNAL niOlO1OOi : STD_LOGIC; + SIGNAL niOlO1OOl : STD_LOGIC; + SIGNAL niOlO1OOO : STD_LOGIC; + SIGNAL niOlOi00i : STD_LOGIC; + SIGNAL niOlOi00l : STD_LOGIC; + SIGNAL niOlOi00O : STD_LOGIC; + SIGNAL niOlOi01i : STD_LOGIC; + SIGNAL niOlOi01l : STD_LOGIC; + SIGNAL niOlOi01O : STD_LOGIC; + SIGNAL niOlOi0ii : STD_LOGIC; + SIGNAL niOlOi0il : STD_LOGIC; + SIGNAL niOlOi0iO : STD_LOGIC; + SIGNAL niOlOi0li : STD_LOGIC; + SIGNAL niOlOi0ll : STD_LOGIC; + SIGNAL niOlOi0lO : STD_LOGIC; + SIGNAL niOlOi0Oi : STD_LOGIC; + SIGNAL niOlOi0Ol : STD_LOGIC; + SIGNAL niOlOi0OO : STD_LOGIC; + SIGNAL niOlOi10i : STD_LOGIC; + SIGNAL niOlOi10l : STD_LOGIC; + SIGNAL niOlOi10O : STD_LOGIC; + SIGNAL niOlOi11i : STD_LOGIC; + SIGNAL niOlOi11l : STD_LOGIC; + SIGNAL niOlOi11O : STD_LOGIC; + SIGNAL niOlOi1ii : STD_LOGIC; + SIGNAL niOlOi1il : STD_LOGIC; + SIGNAL niOlOi1iO : STD_LOGIC; + SIGNAL niOlOi1li : STD_LOGIC; + SIGNAL niOlOi1ll : STD_LOGIC; + SIGNAL niOlOi1lO : STD_LOGIC; + SIGNAL niOlOi1Oi : STD_LOGIC; + SIGNAL niOlOi1Ol : STD_LOGIC; + SIGNAL niOlOi1OO : STD_LOGIC; + SIGNAL niOlOii0i : STD_LOGIC; + SIGNAL niOlOii0l : STD_LOGIC; + SIGNAL niOlOii0O : STD_LOGIC; + SIGNAL niOlOii1i : STD_LOGIC; + SIGNAL niOlOii1l : STD_LOGIC; + SIGNAL niOlOii1O : STD_LOGIC; + SIGNAL niOlOiiii : STD_LOGIC; + SIGNAL niOlOiiil : STD_LOGIC; + SIGNAL niOlOiiiO : STD_LOGIC; + SIGNAL niOlOiili : STD_LOGIC; + SIGNAL niOlOiill : STD_LOGIC; + SIGNAL niOlOiilO : STD_LOGIC; + SIGNAL niOlOiiOi : STD_LOGIC; + SIGNAL niOlOiiOl : STD_LOGIC; + SIGNAL niOlOiiOO : STD_LOGIC; + SIGNAL niOlOil0i : STD_LOGIC; + SIGNAL niOlOil0l : STD_LOGIC; + SIGNAL niOlOil0O : STD_LOGIC; + SIGNAL niOlOil1i : STD_LOGIC; + SIGNAL niOlOil1l : STD_LOGIC; + SIGNAL niOlOil1O : STD_LOGIC; + SIGNAL niOlOilii : STD_LOGIC; + SIGNAL niOlOilil : STD_LOGIC; + SIGNAL niOlOiliO : STD_LOGIC; + SIGNAL niOlOilli : STD_LOGIC; + SIGNAL niOlOilll : STD_LOGIC; + SIGNAL niOlOillO : STD_LOGIC; + SIGNAL niOlOilOi : STD_LOGIC; + SIGNAL niOlOilOl : STD_LOGIC; + SIGNAL niOlOilOO : STD_LOGIC; + SIGNAL niOlOiO0i : STD_LOGIC; + SIGNAL niOlOiO0l : STD_LOGIC; + SIGNAL niOlOiO0O : STD_LOGIC; + SIGNAL niOlOiO1i : STD_LOGIC; + SIGNAL niOlOiO1l : STD_LOGIC; + SIGNAL niOlOiO1O : STD_LOGIC; + SIGNAL niOlOiOii : STD_LOGIC; + SIGNAL niOlOiOil : STD_LOGIC; + SIGNAL niOlOiOiO : STD_LOGIC; + SIGNAL niOlOiOli : STD_LOGIC; + SIGNAL niOlOiOll : STD_LOGIC; + SIGNAL niOlOiOlO : STD_LOGIC; + SIGNAL niOlOiOOi : STD_LOGIC; + SIGNAL niOlOiOOl : STD_LOGIC; + SIGNAL niOlOiOOO : STD_LOGIC; + SIGNAL niOlOl00i : STD_LOGIC; + SIGNAL niOlOl00l : STD_LOGIC; + SIGNAL niOlOl00O : STD_LOGIC; + SIGNAL niOlOl01i : STD_LOGIC; + SIGNAL niOlOl01l : STD_LOGIC; + SIGNAL niOlOl01O : STD_LOGIC; + SIGNAL niOlOl0ii : STD_LOGIC; + SIGNAL niOlOl0il : STD_LOGIC; + SIGNAL niOlOl0iO : STD_LOGIC; + SIGNAL niOlOl0li : STD_LOGIC; + SIGNAL niOlOl0ll : STD_LOGIC; + SIGNAL niOlOl0lO : STD_LOGIC; + SIGNAL niOlOl0Oi : STD_LOGIC; + SIGNAL niOlOl0Ol : STD_LOGIC; + SIGNAL niOlOl0OO : STD_LOGIC; + SIGNAL niOlOl10i : STD_LOGIC; + SIGNAL niOlOl10l : STD_LOGIC; + SIGNAL niOlOl10O : STD_LOGIC; + SIGNAL niOlOl11i : STD_LOGIC; + SIGNAL niOlOl11l : STD_LOGIC; + SIGNAL niOlOl11O : STD_LOGIC; + SIGNAL niOlOl1ii : STD_LOGIC; + SIGNAL niOlOl1il : STD_LOGIC; + SIGNAL niOlOl1iO : STD_LOGIC; + SIGNAL niOlOl1li : STD_LOGIC; + SIGNAL niOlOl1ll : STD_LOGIC; + SIGNAL niOlOl1lO : STD_LOGIC; + SIGNAL niOlOl1Oi : STD_LOGIC; + SIGNAL niOlOl1Ol : STD_LOGIC; + SIGNAL niOlOl1OO : STD_LOGIC; + SIGNAL niOlOli0i : STD_LOGIC; + SIGNAL niOlOli0l : STD_LOGIC; + SIGNAL niOlOli0O : STD_LOGIC; + SIGNAL niOlOli1i : STD_LOGIC; + SIGNAL niOlOli1l : STD_LOGIC; + SIGNAL niOlOli1O : STD_LOGIC; + SIGNAL niOlOliii : STD_LOGIC; + SIGNAL niOlOliil : STD_LOGIC; + SIGNAL niOlOliiO : STD_LOGIC; + SIGNAL niOlOlili : STD_LOGIC; + SIGNAL niOlOlill : STD_LOGIC; + SIGNAL niOlOlilO : STD_LOGIC; + SIGNAL niOlOliOi : STD_LOGIC; + SIGNAL niOlOliOl : STD_LOGIC; + SIGNAL niOlOliOO : STD_LOGIC; + SIGNAL niOlOll0i : STD_LOGIC; + SIGNAL niOlOll0l : STD_LOGIC; + SIGNAL niOlOll0O : STD_LOGIC; + SIGNAL niOlOll1i : STD_LOGIC; + SIGNAL niOlOll1l : STD_LOGIC; + SIGNAL niOlOll1O : STD_LOGIC; + SIGNAL niOlOllii : STD_LOGIC; + SIGNAL niOlOllil : STD_LOGIC; + SIGNAL niOlOlliO : STD_LOGIC; + SIGNAL niOlOllli : STD_LOGIC; + SIGNAL niOlOllll : STD_LOGIC; + SIGNAL niOlOlllO : STD_LOGIC; + SIGNAL niOlOllOi : STD_LOGIC; + SIGNAL niOlOllOl : STD_LOGIC; + SIGNAL niOlOllOO : STD_LOGIC; + SIGNAL niOlOlO0i : STD_LOGIC; + SIGNAL niOlOlO0l : STD_LOGIC; + SIGNAL niOlOlO0O : STD_LOGIC; + SIGNAL niOlOlO1i : STD_LOGIC; + SIGNAL niOlOlO1l : STD_LOGIC; + SIGNAL niOlOlO1O : STD_LOGIC; + SIGNAL niOlOlOii : STD_LOGIC; + SIGNAL niOlOlOil : STD_LOGIC; + SIGNAL niOlOlOiO : STD_LOGIC; + SIGNAL niOlOlOli : STD_LOGIC; + SIGNAL niOlOlOll : STD_LOGIC; + SIGNAL niOlOlOlO : STD_LOGIC; + SIGNAL niOlOlOOi : STD_LOGIC; + SIGNAL niOlOlOOl : STD_LOGIC; + SIGNAL niOlOlOOO : STD_LOGIC; + SIGNAL niOlOO00i : STD_LOGIC; + SIGNAL niOlOO00l : STD_LOGIC; + SIGNAL niOlOO00O : STD_LOGIC; + SIGNAL niOlOO01i : STD_LOGIC; + SIGNAL niOlOO01l : STD_LOGIC; + SIGNAL niOlOO01O : STD_LOGIC; + SIGNAL niOlOO0ii : STD_LOGIC; + SIGNAL niOlOO0il : STD_LOGIC; + SIGNAL niOlOO0iO : STD_LOGIC; + SIGNAL niOlOO0li : STD_LOGIC; + SIGNAL niOlOO0ll : STD_LOGIC; + SIGNAL niOlOO0lO : STD_LOGIC; + SIGNAL niOlOO0Oi : STD_LOGIC; + SIGNAL niOlOO0Ol : STD_LOGIC; + SIGNAL niOlOO0OO : STD_LOGIC; + SIGNAL niOlOO10i : STD_LOGIC; + SIGNAL niOlOO10l : STD_LOGIC; + SIGNAL niOlOO10O : STD_LOGIC; + SIGNAL niOlOO11i : STD_LOGIC; + SIGNAL niOlOO11l : STD_LOGIC; + SIGNAL niOlOO11O : STD_LOGIC; + SIGNAL niOlOO1ii : STD_LOGIC; + SIGNAL niOlOO1il : STD_LOGIC; + SIGNAL niOlOO1iO : STD_LOGIC; + SIGNAL niOlOO1li : STD_LOGIC; + SIGNAL niOlOO1ll : STD_LOGIC; + SIGNAL niOlOO1lO : STD_LOGIC; + SIGNAL niOlOO1Oi : STD_LOGIC; + SIGNAL niOlOO1Ol : STD_LOGIC; + SIGNAL niOlOO1OO : STD_LOGIC; + SIGNAL niOlOOi0i : STD_LOGIC; + SIGNAL niOlOOi0l : STD_LOGIC; + SIGNAL niOlOOi0O : STD_LOGIC; + SIGNAL niOlOOi1i : STD_LOGIC; + SIGNAL niOlOOi1l : STD_LOGIC; + SIGNAL niOlOOi1O : STD_LOGIC; + SIGNAL niOlOOiii : STD_LOGIC; + SIGNAL niOlOOiil : STD_LOGIC; + SIGNAL niOlOOiiO : STD_LOGIC; + SIGNAL niOlOOili : STD_LOGIC; + SIGNAL niOlOOill : STD_LOGIC; + SIGNAL niOlOOilO : STD_LOGIC; + SIGNAL niOlOOiOi : STD_LOGIC; + SIGNAL niOlOOiOl : STD_LOGIC; + SIGNAL niOlOOiOO : STD_LOGIC; + SIGNAL niOlOOl0i : STD_LOGIC; + SIGNAL niOlOOl0l : STD_LOGIC; + SIGNAL niOlOOl0O : STD_LOGIC; + SIGNAL niOlOOl1i : STD_LOGIC; + SIGNAL niOlOOl1l : STD_LOGIC; + SIGNAL niOlOOl1O : STD_LOGIC; + SIGNAL niOlOOlii : STD_LOGIC; + SIGNAL niOlOOlil : STD_LOGIC; + SIGNAL niOlOOliO : STD_LOGIC; + SIGNAL niOlOOlli : STD_LOGIC; + SIGNAL niOlOOlll : STD_LOGIC; + SIGNAL niOlOOllO : STD_LOGIC; + SIGNAL niOlOOlOi : STD_LOGIC; + SIGNAL niOlOOlOl : STD_LOGIC; + SIGNAL niOlOOlOO : STD_LOGIC; + SIGNAL niOlOOO0i : STD_LOGIC; + SIGNAL niOlOOO0l : STD_LOGIC; + SIGNAL niOlOOO0O : STD_LOGIC; + SIGNAL niOlOOO1i : STD_LOGIC; + SIGNAL niOlOOO1l : STD_LOGIC; + SIGNAL niOlOOO1O : STD_LOGIC; + SIGNAL niOlOOOii : STD_LOGIC; + SIGNAL niOlOOOil : STD_LOGIC; + SIGNAL niOlOOOiO : STD_LOGIC; + SIGNAL niOlOOOli : STD_LOGIC; + SIGNAL niOlOOOll : STD_LOGIC; + SIGNAL niOlOOOlO : STD_LOGIC; + SIGNAL niOlOOOOi : STD_LOGIC; + SIGNAL niOlOOOOl : STD_LOGIC; + SIGNAL niOlOOOOO : STD_LOGIC; + SIGNAL niOO0000i : STD_LOGIC; + SIGNAL niOO0000l : STD_LOGIC; + SIGNAL niOO0000O : STD_LOGIC; + SIGNAL niOO0001i : STD_LOGIC; + SIGNAL niOO0001l : STD_LOGIC; + SIGNAL niOO0001O : STD_LOGIC; + SIGNAL niOO000ii : STD_LOGIC; + SIGNAL niOO000il : STD_LOGIC; + SIGNAL niOO000iO : STD_LOGIC; + SIGNAL niOO000li : STD_LOGIC; + SIGNAL niOO000ll : STD_LOGIC; + SIGNAL niOO000lO : STD_LOGIC; + SIGNAL niOO000Oi : STD_LOGIC; + SIGNAL niOO000Ol : STD_LOGIC; + SIGNAL niOO000OO : STD_LOGIC; + SIGNAL niOO0010i : STD_LOGIC; + SIGNAL niOO0010l : STD_LOGIC; + SIGNAL niOO0010O : STD_LOGIC; + SIGNAL niOO0011i : STD_LOGIC; + SIGNAL niOO0011O : STD_LOGIC; + SIGNAL niOO001ii : STD_LOGIC; + SIGNAL niOO001il : STD_LOGIC; + SIGNAL niOO001iO : STD_LOGIC; + SIGNAL niOO001li : STD_LOGIC; + SIGNAL niOO001ll : STD_LOGIC; + SIGNAL niOO001lO : STD_LOGIC; + SIGNAL niOO001Oi : STD_LOGIC; + SIGNAL niOO001Ol : STD_LOGIC; + SIGNAL niOO001OO : STD_LOGIC; + SIGNAL niOO00i0i : STD_LOGIC; + SIGNAL niOO00i0l : STD_LOGIC; + SIGNAL niOO00i0O : STD_LOGIC; + SIGNAL niOO00i1i : STD_LOGIC; + SIGNAL niOO00i1l : STD_LOGIC; + SIGNAL niOO00i1O : STD_LOGIC; + SIGNAL niOO00iii : STD_LOGIC; + SIGNAL niOO00iil : STD_LOGIC; + SIGNAL niOO00iiO : STD_LOGIC; + SIGNAL niOO00ili : STD_LOGIC; + SIGNAL niOO00ill : STD_LOGIC; + SIGNAL niOO00ilO : STD_LOGIC; + SIGNAL niOO00iOi : STD_LOGIC; + SIGNAL niOO00iOl : STD_LOGIC; + SIGNAL niOO00iOO : STD_LOGIC; + SIGNAL niOO00l0i : STD_LOGIC; + SIGNAL niOO00l0l : STD_LOGIC; + SIGNAL niOO00l0O : STD_LOGIC; + SIGNAL niOO00l1i : STD_LOGIC; + SIGNAL niOO00l1l : STD_LOGIC; + SIGNAL niOO00l1O : STD_LOGIC; + SIGNAL niOO00lii : STD_LOGIC; + SIGNAL niOO00lil : STD_LOGIC; + SIGNAL niOO00liO : STD_LOGIC; + SIGNAL niOO00lli : STD_LOGIC; + SIGNAL niOO00lll : STD_LOGIC; + SIGNAL niOO00llO : STD_LOGIC; + SIGNAL niOO00lOi : STD_LOGIC; + SIGNAL niOO00lOl : STD_LOGIC; + SIGNAL niOO00lOO : STD_LOGIC; + SIGNAL niOO00O0i : STD_LOGIC; + SIGNAL niOO00O0l : STD_LOGIC; + SIGNAL niOO00O0O : STD_LOGIC; + SIGNAL niOO00O1i : STD_LOGIC; + SIGNAL niOO00O1l : STD_LOGIC; + SIGNAL niOO00O1O : STD_LOGIC; + SIGNAL niOO00Oii : STD_LOGIC; + SIGNAL niOO00Oil : STD_LOGIC; + SIGNAL niOO00OiO : STD_LOGIC; + SIGNAL niOO00Oli : STD_LOGIC; + SIGNAL niOO00Oll : STD_LOGIC; + SIGNAL niOO00OlO : STD_LOGIC; + SIGNAL niOO00OOi : STD_LOGIC; + SIGNAL niOO00OOl : STD_LOGIC; + SIGNAL niOO00OOO : STD_LOGIC; + SIGNAL niOO0100i : STD_LOGIC; + SIGNAL niOO0100l : STD_LOGIC; + SIGNAL niOO0100O : STD_LOGIC; + SIGNAL niOO0101i : STD_LOGIC; + SIGNAL niOO0101l : STD_LOGIC; + SIGNAL niOO0101O : STD_LOGIC; + SIGNAL niOO010ii : STD_LOGIC; + SIGNAL niOO010il : STD_LOGIC; + SIGNAL niOO010iO : STD_LOGIC; + SIGNAL niOO010li : STD_LOGIC; + SIGNAL niOO010ll : STD_LOGIC; + SIGNAL niOO010lO : STD_LOGIC; + SIGNAL niOO010Oi : STD_LOGIC; + SIGNAL niOO010Ol : STD_LOGIC; + SIGNAL niOO010OO : STD_LOGIC; + SIGNAL niOO0110i : STD_LOGIC; + SIGNAL niOO0110l : STD_LOGIC; + SIGNAL niOO0110O : STD_LOGIC; + SIGNAL niOO0111i : STD_LOGIC; + SIGNAL niOO0111l : STD_LOGIC; + SIGNAL niOO0111O : STD_LOGIC; + SIGNAL niOO011ii : STD_LOGIC; + SIGNAL niOO011il : STD_LOGIC; + SIGNAL niOO011iO : STD_LOGIC; + SIGNAL niOO011li : STD_LOGIC; + SIGNAL niOO011ll : STD_LOGIC; + SIGNAL niOO011lO : STD_LOGIC; + SIGNAL niOO011Oi : STD_LOGIC; + SIGNAL niOO011Ol : STD_LOGIC; + SIGNAL niOO011OO : STD_LOGIC; + SIGNAL niOO01i0i : STD_LOGIC; + SIGNAL niOO01i0l : STD_LOGIC; + SIGNAL niOO01i0O : STD_LOGIC; + SIGNAL niOO01i1i : STD_LOGIC; + SIGNAL niOO01i1l : STD_LOGIC; + SIGNAL niOO01i1O : STD_LOGIC; + SIGNAL niOO01iii : STD_LOGIC; + SIGNAL niOO01iil : STD_LOGIC; + SIGNAL niOO01iiO : STD_LOGIC; + SIGNAL niOO01ili : STD_LOGIC; + SIGNAL niOO01ill : STD_LOGIC; + SIGNAL niOO01ilO : STD_LOGIC; + SIGNAL niOO01iOi : STD_LOGIC; + SIGNAL niOO01iOl : STD_LOGIC; + SIGNAL niOO01iOO : STD_LOGIC; + SIGNAL niOO01l0i : STD_LOGIC; + SIGNAL niOO01l0l : STD_LOGIC; + SIGNAL niOO01l0O : STD_LOGIC; + SIGNAL niOO01l1i : STD_LOGIC; + SIGNAL niOO01l1l : STD_LOGIC; + SIGNAL niOO01l1O : STD_LOGIC; + SIGNAL niOO01lii : STD_LOGIC; + SIGNAL niOO01lil : STD_LOGIC; + SIGNAL niOO01liO : STD_LOGIC; + SIGNAL niOO01lli : STD_LOGIC; + SIGNAL niOO01lll : STD_LOGIC; + SIGNAL niOO01llO : STD_LOGIC; + SIGNAL niOO01lOi : STD_LOGIC; + SIGNAL niOO01lOl : STD_LOGIC; + SIGNAL niOO01lOO : STD_LOGIC; + SIGNAL niOO01O0i : STD_LOGIC; + SIGNAL niOO01O0l : STD_LOGIC; + SIGNAL niOO01O0O : STD_LOGIC; + SIGNAL niOO01O1i : STD_LOGIC; + SIGNAL niOO01Oii : STD_LOGIC; + SIGNAL niOO01Oil : STD_LOGIC; + SIGNAL niOO01OiO : STD_LOGIC; + SIGNAL niOO01Oli : STD_LOGIC; + SIGNAL niOO01Oll : STD_LOGIC; + SIGNAL niOO01OlO : STD_LOGIC; + SIGNAL niOO01OOi : STD_LOGIC; + SIGNAL niOO01OOl : STD_LOGIC; + SIGNAL niOO01OOO : STD_LOGIC; + SIGNAL niOO0i00i : STD_LOGIC; + SIGNAL niOO0i00l : STD_LOGIC; + SIGNAL niOO0i00O : STD_LOGIC; + SIGNAL niOO0i01i : STD_LOGIC; + SIGNAL niOO0i01l : STD_LOGIC; + SIGNAL niOO0i01O : STD_LOGIC; + SIGNAL niOO0i0ii : STD_LOGIC; + SIGNAL niOO0i0il : STD_LOGIC; + SIGNAL niOO0i0iO : STD_LOGIC; + SIGNAL niOO0i0li : STD_LOGIC; + SIGNAL niOO0i0ll : STD_LOGIC; + SIGNAL niOO0i0lO : STD_LOGIC; + SIGNAL niOO0i0Oi : STD_LOGIC; + SIGNAL niOO0i0Ol : STD_LOGIC; + SIGNAL niOO0i0OO : STD_LOGIC; + SIGNAL niOO0i10i : STD_LOGIC; + SIGNAL niOO0i10l : STD_LOGIC; + SIGNAL niOO0i10O : STD_LOGIC; + SIGNAL niOO0i11i : STD_LOGIC; + SIGNAL niOO0i11l : STD_LOGIC; + SIGNAL niOO0i11O : STD_LOGIC; + SIGNAL niOO0i1ii : STD_LOGIC; + SIGNAL niOO0i1il : STD_LOGIC; + SIGNAL niOO0i1iO : STD_LOGIC; + SIGNAL niOO0i1li : STD_LOGIC; + SIGNAL niOO0i1ll : STD_LOGIC; + SIGNAL niOO0i1lO : STD_LOGIC; + SIGNAL niOO0i1Oi : STD_LOGIC; + SIGNAL niOO0i1Ol : STD_LOGIC; + SIGNAL niOO0i1OO : STD_LOGIC; + SIGNAL niOO0ii0i : STD_LOGIC; + SIGNAL niOO0ii0l : STD_LOGIC; + SIGNAL niOO0ii0O : STD_LOGIC; + SIGNAL niOO0ii1i : STD_LOGIC; + SIGNAL niOO0ii1l : STD_LOGIC; + SIGNAL niOO0ii1O : STD_LOGIC; + SIGNAL niOO0iiii : STD_LOGIC; + SIGNAL niOO0iiil : STD_LOGIC; + SIGNAL niOO0iiiO : STD_LOGIC; + SIGNAL niOO0iili : STD_LOGIC; + SIGNAL niOO0iill : STD_LOGIC; + SIGNAL niOO0iilO : STD_LOGIC; + SIGNAL niOO0iiOi : STD_LOGIC; + SIGNAL niOO0iiOl : STD_LOGIC; + SIGNAL niOO0iiOO : STD_LOGIC; + SIGNAL niOO0il0i : STD_LOGIC; + SIGNAL niOO0il0l : STD_LOGIC; + SIGNAL niOO0il0O : STD_LOGIC; + SIGNAL niOO0il1i : STD_LOGIC; + SIGNAL niOO0il1l : STD_LOGIC; + SIGNAL niOO0il1O : STD_LOGIC; + SIGNAL niOO0ilii : STD_LOGIC; + SIGNAL niOO0illl : STD_LOGIC; + SIGNAL niOO0illO : STD_LOGIC; + SIGNAL niOO0ilOi : STD_LOGIC; + SIGNAL niOO0ilOl : STD_LOGIC; + SIGNAL niOO0ilOO : STD_LOGIC; + SIGNAL niOO0iO0i : STD_LOGIC; + SIGNAL niOO0iO0l : STD_LOGIC; + SIGNAL niOO0iO0O : STD_LOGIC; + SIGNAL niOO0iO1i : STD_LOGIC; + SIGNAL niOO0iO1l : STD_LOGIC; + SIGNAL niOO0iO1O : STD_LOGIC; + SIGNAL niOO0iOii : STD_LOGIC; + SIGNAL niOO0iOil : STD_LOGIC; + SIGNAL niOO0iOll : STD_LOGIC; + SIGNAL niOO0iOlO : STD_LOGIC; + SIGNAL niOO0iOOi : STD_LOGIC; + SIGNAL niOO0iOOl : STD_LOGIC; + SIGNAL niOO0iOOO : STD_LOGIC; + SIGNAL niOO0l00i : STD_LOGIC; + SIGNAL niOO0l00l : STD_LOGIC; + SIGNAL niOO0l00O : STD_LOGIC; + SIGNAL niOO0l01i : STD_LOGIC; + SIGNAL niOO0l01l : STD_LOGIC; + SIGNAL niOO0l01O : STD_LOGIC; + SIGNAL niOO0l0il : STD_LOGIC; + SIGNAL niOO0l0iO : STD_LOGIC; + SIGNAL niOO0l0li : STD_LOGIC; + SIGNAL niOO0l0ll : STD_LOGIC; + SIGNAL niOO0l0lO : STD_LOGIC; + SIGNAL niOO0l0Oi : STD_LOGIC; + SIGNAL niOO0l0Ol : STD_LOGIC; + SIGNAL niOO0l0OO : STD_LOGIC; + SIGNAL niOO0l10i : STD_LOGIC; + SIGNAL niOO0l10l : STD_LOGIC; + SIGNAL niOO0l10O : STD_LOGIC; + SIGNAL niOO0l11i : STD_LOGIC; + SIGNAL niOO0l11l : STD_LOGIC; + SIGNAL niOO0l11O : STD_LOGIC; + SIGNAL niOO0l1ii : STD_LOGIC; + SIGNAL niOO0l1il : STD_LOGIC; + SIGNAL niOO0l1iO : STD_LOGIC; + SIGNAL niOO0l1li : STD_LOGIC; + SIGNAL niOO0l1OO : STD_LOGIC; + SIGNAL niOO0li0i : STD_LOGIC; + SIGNAL niOO0li0l : STD_LOGIC; + SIGNAL niOO0li0O : STD_LOGIC; + SIGNAL niOO0li1i : STD_LOGIC; + SIGNAL niOO0li1l : STD_LOGIC; + SIGNAL niOO0li1O : STD_LOGIC; + SIGNAL niOO0liii : STD_LOGIC; + SIGNAL niOO0liil : STD_LOGIC; + SIGNAL niOO0liiO : STD_LOGIC; + SIGNAL niOO0lili : STD_LOGIC; + SIGNAL niOO0lill : STD_LOGIC; + SIGNAL niOO0lilO : STD_LOGIC; + SIGNAL niOO0liOi : STD_LOGIC; + SIGNAL niOO0liOl : STD_LOGIC; + SIGNAL niOO0liOO : STD_LOGIC; + SIGNAL niOO0ll0i : STD_LOGIC; + SIGNAL niOO0ll1i : STD_LOGIC; + SIGNAL niOO0ll1l : STD_LOGIC; + SIGNAL niOO0ll1O : STD_LOGIC; + SIGNAL niOO0lliO : STD_LOGIC; + SIGNAL niOO0llll : STD_LOGIC; + SIGNAL niOO0lllO : STD_LOGIC; + SIGNAL niOO0llOi : STD_LOGIC; + SIGNAL niOO0lOlO : STD_LOGIC; + SIGNAL niOO0lOOi : STD_LOGIC; + SIGNAL niOO0lOOl : STD_LOGIC; + SIGNAL niOO0O10O : STD_LOGIC; + SIGNAL niOO0O11l : STD_LOGIC; + SIGNAL niOO0O11O : STD_LOGIC; + SIGNAL niOO0O1ll : STD_LOGIC; + SIGNAL niOO0O1lO : STD_LOGIC; + SIGNAL niOO0O1OO : STD_LOGIC; + SIGNAL niOO1000i : STD_LOGIC; + SIGNAL niOO1000l : STD_LOGIC; + SIGNAL niOO1000O : STD_LOGIC; + SIGNAL niOO1001i : STD_LOGIC; + SIGNAL niOO1001l : STD_LOGIC; + SIGNAL niOO1001O : STD_LOGIC; + SIGNAL niOO100ii : STD_LOGIC; + SIGNAL niOO100il : STD_LOGIC; + SIGNAL niOO100iO : STD_LOGIC; + SIGNAL niOO100li : STD_LOGIC; + SIGNAL niOO100ll : STD_LOGIC; + SIGNAL niOO100lO : STD_LOGIC; + SIGNAL niOO100Oi : STD_LOGIC; + SIGNAL niOO100Ol : STD_LOGIC; + SIGNAL niOO100OO : STD_LOGIC; + SIGNAL niOO1010i : STD_LOGIC; + SIGNAL niOO1010l : STD_LOGIC; + SIGNAL niOO1010O : STD_LOGIC; + SIGNAL niOO1011i : STD_LOGIC; + SIGNAL niOO1011l : STD_LOGIC; + SIGNAL niOO1011O : STD_LOGIC; + SIGNAL niOO101ii : STD_LOGIC; + SIGNAL niOO101il : STD_LOGIC; + SIGNAL niOO101iO : STD_LOGIC; + SIGNAL niOO101li : STD_LOGIC; + SIGNAL niOO101ll : STD_LOGIC; + SIGNAL niOO101lO : STD_LOGIC; + SIGNAL niOO101Oi : STD_LOGIC; + SIGNAL niOO101Ol : STD_LOGIC; + SIGNAL niOO101OO : STD_LOGIC; + SIGNAL niOO10i0i : STD_LOGIC; + SIGNAL niOO10i0l : STD_LOGIC; + SIGNAL niOO10i0O : STD_LOGIC; + SIGNAL niOO10i1i : STD_LOGIC; + SIGNAL niOO10i1l : STD_LOGIC; + SIGNAL niOO10i1O : STD_LOGIC; + SIGNAL niOO10iii : STD_LOGIC; + SIGNAL niOO10iil : STD_LOGIC; + SIGNAL niOO10iiO : STD_LOGIC; + SIGNAL niOO10ili : STD_LOGIC; + SIGNAL niOO10ill : STD_LOGIC; + SIGNAL niOO10ilO : STD_LOGIC; + SIGNAL niOO10iOi : STD_LOGIC; + SIGNAL niOO10iOl : STD_LOGIC; + SIGNAL niOO10iOO : STD_LOGIC; + SIGNAL niOO10l0i : STD_LOGIC; + SIGNAL niOO10l0l : STD_LOGIC; + SIGNAL niOO10l0O : STD_LOGIC; + SIGNAL niOO10l1i : STD_LOGIC; + SIGNAL niOO10l1l : STD_LOGIC; + SIGNAL niOO10l1O : STD_LOGIC; + SIGNAL niOO10lii : STD_LOGIC; + SIGNAL niOO10lil : STD_LOGIC; + SIGNAL niOO10liO : STD_LOGIC; + SIGNAL niOO10lli : STD_LOGIC; + SIGNAL niOO10lll : STD_LOGIC; + SIGNAL niOO10llO : STD_LOGIC; + SIGNAL niOO10lOi : STD_LOGIC; + SIGNAL niOO10lOl : STD_LOGIC; + SIGNAL niOO10lOO : STD_LOGIC; + SIGNAL niOO10O0i : STD_LOGIC; + SIGNAL niOO10O0l : STD_LOGIC; + SIGNAL niOO10O0O : STD_LOGIC; + SIGNAL niOO10O1i : STD_LOGIC; + SIGNAL niOO10O1l : STD_LOGIC; + SIGNAL niOO10O1O : STD_LOGIC; + SIGNAL niOO10Oii : STD_LOGIC; + SIGNAL niOO10Oil : STD_LOGIC; + SIGNAL niOO10OiO : STD_LOGIC; + SIGNAL niOO10OlO : STD_LOGIC; + SIGNAL niOO10OOi : STD_LOGIC; + SIGNAL niOO10OOl : STD_LOGIC; + SIGNAL niOO10OOO : STD_LOGIC; + SIGNAL niOO1100i : STD_LOGIC; + SIGNAL niOO1100l : STD_LOGIC; + SIGNAL niOO1100O : STD_LOGIC; + SIGNAL niOO1101i : STD_LOGIC; + SIGNAL niOO1101l : STD_LOGIC; + SIGNAL niOO1101O : STD_LOGIC; + SIGNAL niOO110ii : STD_LOGIC; + SIGNAL niOO110il : STD_LOGIC; + SIGNAL niOO110iO : STD_LOGIC; + SIGNAL niOO110li : STD_LOGIC; + SIGNAL niOO110ll : STD_LOGIC; + SIGNAL niOO110lO : STD_LOGIC; + SIGNAL niOO110Oi : STD_LOGIC; + SIGNAL niOO110Ol : STD_LOGIC; + SIGNAL niOO110OO : STD_LOGIC; + SIGNAL niOO1110i : STD_LOGIC; + SIGNAL niOO1110l : STD_LOGIC; + SIGNAL niOO1110O : STD_LOGIC; + SIGNAL niOO1111i : STD_LOGIC; + SIGNAL niOO1111l : STD_LOGIC; + SIGNAL niOO1111O : STD_LOGIC; + SIGNAL niOO111ii : STD_LOGIC; + SIGNAL niOO111il : STD_LOGIC; + SIGNAL niOO111iO : STD_LOGIC; + SIGNAL niOO111li : STD_LOGIC; + SIGNAL niOO111ll : STD_LOGIC; + SIGNAL niOO111lO : STD_LOGIC; + SIGNAL niOO111Oi : STD_LOGIC; + SIGNAL niOO111Ol : STD_LOGIC; + SIGNAL niOO111OO : STD_LOGIC; + SIGNAL niOO11i0i : STD_LOGIC; + SIGNAL niOO11i0l : STD_LOGIC; + SIGNAL niOO11i0O : STD_LOGIC; + SIGNAL niOO11i1i : STD_LOGIC; + SIGNAL niOO11i1l : STD_LOGIC; + SIGNAL niOO11i1O : STD_LOGIC; + SIGNAL niOO11iii : STD_LOGIC; + SIGNAL niOO11iil : STD_LOGIC; + SIGNAL niOO11iiO : STD_LOGIC; + SIGNAL niOO11ili : STD_LOGIC; + SIGNAL niOO11ill : STD_LOGIC; + SIGNAL niOO11ilO : STD_LOGIC; + SIGNAL niOO11iOi : STD_LOGIC; + SIGNAL niOO11iOl : STD_LOGIC; + SIGNAL niOO11iOO : STD_LOGIC; + SIGNAL niOO11l0i : STD_LOGIC; + SIGNAL niOO11l0l : STD_LOGIC; + SIGNAL niOO11l0O : STD_LOGIC; + SIGNAL niOO11l1i : STD_LOGIC; + SIGNAL niOO11l1l : STD_LOGIC; + SIGNAL niOO11l1O : STD_LOGIC; + SIGNAL niOO11lii : STD_LOGIC; + SIGNAL niOO11lil : STD_LOGIC; + SIGNAL niOO11liO : STD_LOGIC; + SIGNAL niOO11lli : STD_LOGIC; + SIGNAL niOO11lll : STD_LOGIC; + SIGNAL niOO11llO : STD_LOGIC; + SIGNAL niOO11lOi : STD_LOGIC; + SIGNAL niOO11lOl : STD_LOGIC; + SIGNAL niOO11lOO : STD_LOGIC; + SIGNAL niOO11O0i : STD_LOGIC; + SIGNAL niOO11O0l : STD_LOGIC; + SIGNAL niOO11O0O : STD_LOGIC; + SIGNAL niOO11O1i : STD_LOGIC; + SIGNAL niOO11O1l : STD_LOGIC; + SIGNAL niOO11O1O : STD_LOGIC; + SIGNAL niOO11Oii : STD_LOGIC; + SIGNAL niOO11Oil : STD_LOGIC; + SIGNAL niOO11OiO : STD_LOGIC; + SIGNAL niOO11Oli : STD_LOGIC; + SIGNAL niOO11Oll : STD_LOGIC; + SIGNAL niOO11OlO : STD_LOGIC; + SIGNAL niOO11OOi : STD_LOGIC; + SIGNAL niOO11OOl : STD_LOGIC; + SIGNAL niOO11OOO : STD_LOGIC; + SIGNAL niOO1i00i : STD_LOGIC; + SIGNAL niOO1i00l : STD_LOGIC; + SIGNAL niOO1i00O : STD_LOGIC; + SIGNAL niOO1i01i : STD_LOGIC; + SIGNAL niOO1i01l : STD_LOGIC; + SIGNAL niOO1i01O : STD_LOGIC; + SIGNAL niOO1i0ii : STD_LOGIC; + SIGNAL niOO1i0il : STD_LOGIC; + SIGNAL niOO1i0iO : STD_LOGIC; + SIGNAL niOO1i0li : STD_LOGIC; + SIGNAL niOO1i0ll : STD_LOGIC; + SIGNAL niOO1i0lO : STD_LOGIC; + SIGNAL niOO1i0Oi : STD_LOGIC; + SIGNAL niOO1i0Ol : STD_LOGIC; + SIGNAL niOO1i0OO : STD_LOGIC; + SIGNAL niOO1i10i : STD_LOGIC; + SIGNAL niOO1i10l : STD_LOGIC; + SIGNAL niOO1i10O : STD_LOGIC; + SIGNAL niOO1i11i : STD_LOGIC; + SIGNAL niOO1i11l : STD_LOGIC; + SIGNAL niOO1i11O : STD_LOGIC; + SIGNAL niOO1i1ii : STD_LOGIC; + SIGNAL niOO1i1il : STD_LOGIC; + SIGNAL niOO1i1iO : STD_LOGIC; + SIGNAL niOO1i1li : STD_LOGIC; + SIGNAL niOO1i1ll : STD_LOGIC; + SIGNAL niOO1i1lO : STD_LOGIC; + SIGNAL niOO1i1Oi : STD_LOGIC; + SIGNAL niOO1i1Ol : STD_LOGIC; + SIGNAL niOO1i1OO : STD_LOGIC; + SIGNAL niOO1ii0i : STD_LOGIC; + SIGNAL niOO1ii0l : STD_LOGIC; + SIGNAL niOO1ii0O : STD_LOGIC; + SIGNAL niOO1ii1i : STD_LOGIC; + SIGNAL niOO1ii1l : STD_LOGIC; + SIGNAL niOO1ii1O : STD_LOGIC; + SIGNAL niOO1iiii : STD_LOGIC; + SIGNAL niOO1iiil : STD_LOGIC; + SIGNAL niOO1iiiO : STD_LOGIC; + SIGNAL niOO1iili : STD_LOGIC; + SIGNAL niOO1iill : STD_LOGIC; + SIGNAL niOO1iilO : STD_LOGIC; + SIGNAL niOO1iiOi : STD_LOGIC; + SIGNAL niOO1iiOl : STD_LOGIC; + SIGNAL niOO1iiOO : STD_LOGIC; + SIGNAL niOO1il0i : STD_LOGIC; + SIGNAL niOO1il0l : STD_LOGIC; + SIGNAL niOO1il0O : STD_LOGIC; + SIGNAL niOO1il1i : STD_LOGIC; + SIGNAL niOO1il1l : STD_LOGIC; + SIGNAL niOO1il1O : STD_LOGIC; + SIGNAL niOO1ilii : STD_LOGIC; + SIGNAL niOO1ilil : STD_LOGIC; + SIGNAL niOO1iliO : STD_LOGIC; + SIGNAL niOO1illi : STD_LOGIC; + SIGNAL niOO1illl : STD_LOGIC; + SIGNAL niOO1illO : STD_LOGIC; + SIGNAL niOO1ilOi : STD_LOGIC; + SIGNAL niOO1ilOl : STD_LOGIC; + SIGNAL niOO1ilOO : STD_LOGIC; + SIGNAL niOO1iO0i : STD_LOGIC; + SIGNAL niOO1iO0l : STD_LOGIC; + SIGNAL niOO1iO0O : STD_LOGIC; + SIGNAL niOO1iO1i : STD_LOGIC; + SIGNAL niOO1iO1l : STD_LOGIC; + SIGNAL niOO1iO1O : STD_LOGIC; + SIGNAL niOO1iOii : STD_LOGIC; + SIGNAL niOO1iOil : STD_LOGIC; + SIGNAL niOO1iOiO : STD_LOGIC; + SIGNAL niOO1iOli : STD_LOGIC; + SIGNAL niOO1iOll : STD_LOGIC; + SIGNAL niOO1iOlO : STD_LOGIC; + SIGNAL niOO1iOOi : STD_LOGIC; + SIGNAL niOO1iOOl : STD_LOGIC; + SIGNAL niOO1iOOO : STD_LOGIC; + SIGNAL niOO1l00i : STD_LOGIC; + SIGNAL niOO1l00l : STD_LOGIC; + SIGNAL niOO1l00O : STD_LOGIC; + SIGNAL niOO1l01i : STD_LOGIC; + SIGNAL niOO1l01l : STD_LOGIC; + SIGNAL niOO1l01O : STD_LOGIC; + SIGNAL niOO1l0ii : STD_LOGIC; + SIGNAL niOO1l0il : STD_LOGIC; + SIGNAL niOO1l0iO : STD_LOGIC; + SIGNAL niOO1l0li : STD_LOGIC; + SIGNAL niOO1l0ll : STD_LOGIC; + SIGNAL niOO1l0lO : STD_LOGIC; + SIGNAL niOO1l0Oi : STD_LOGIC; + SIGNAL niOO1l0Ol : STD_LOGIC; + SIGNAL niOO1l0OO : STD_LOGIC; + SIGNAL niOO1l10i : STD_LOGIC; + SIGNAL niOO1l10l : STD_LOGIC; + SIGNAL niOO1l10O : STD_LOGIC; + SIGNAL niOO1l11i : STD_LOGIC; + SIGNAL niOO1l11l : STD_LOGIC; + SIGNAL niOO1l11O : STD_LOGIC; + SIGNAL niOO1l1ii : STD_LOGIC; + SIGNAL niOO1l1il : STD_LOGIC; + SIGNAL niOO1l1iO : STD_LOGIC; + SIGNAL niOO1l1li : STD_LOGIC; + SIGNAL niOO1l1ll : STD_LOGIC; + SIGNAL niOO1l1lO : STD_LOGIC; + SIGNAL niOO1l1Oi : STD_LOGIC; + SIGNAL niOO1l1Ol : STD_LOGIC; + SIGNAL niOO1l1OO : STD_LOGIC; + SIGNAL niOO1li0i : STD_LOGIC; + SIGNAL niOO1li0l : STD_LOGIC; + SIGNAL niOO1li0O : STD_LOGIC; + SIGNAL niOO1li1i : STD_LOGIC; + SIGNAL niOO1li1l : STD_LOGIC; + SIGNAL niOO1li1O : STD_LOGIC; + SIGNAL niOO1liii : STD_LOGIC; + SIGNAL niOO1liil : STD_LOGIC; + SIGNAL niOO1liiO : STD_LOGIC; + SIGNAL niOO1lili : STD_LOGIC; + SIGNAL niOO1lill : STD_LOGIC; + SIGNAL niOO1lilO : STD_LOGIC; + SIGNAL niOO1liOi : STD_LOGIC; + SIGNAL niOO1liOl : STD_LOGIC; + SIGNAL niOO1liOO : STD_LOGIC; + SIGNAL niOO1ll0i : STD_LOGIC; + SIGNAL niOO1ll0l : STD_LOGIC; + SIGNAL niOO1ll0O : STD_LOGIC; + SIGNAL niOO1ll1i : STD_LOGIC; + SIGNAL niOO1ll1l : STD_LOGIC; + SIGNAL niOO1ll1O : STD_LOGIC; + SIGNAL niOO1llii : STD_LOGIC; + SIGNAL niOO1llil : STD_LOGIC; + SIGNAL niOO1lliO : STD_LOGIC; + SIGNAL niOO1llli : STD_LOGIC; + SIGNAL niOO1llll : STD_LOGIC; + SIGNAL niOO1lllO : STD_LOGIC; + SIGNAL niOO1llOi : STD_LOGIC; + SIGNAL niOO1llOl : STD_LOGIC; + SIGNAL niOO1llOO : STD_LOGIC; + SIGNAL niOO1lO0i : STD_LOGIC; + SIGNAL niOO1lO0l : STD_LOGIC; + SIGNAL niOO1lO0O : STD_LOGIC; + SIGNAL niOO1lO1i : STD_LOGIC; + SIGNAL niOO1lO1l : STD_LOGIC; + SIGNAL niOO1lO1O : STD_LOGIC; + SIGNAL niOO1lOii : STD_LOGIC; + SIGNAL niOO1lOil : STD_LOGIC; + SIGNAL niOO1lOiO : STD_LOGIC; + SIGNAL niOO1lOli : STD_LOGIC; + SIGNAL niOO1lOll : STD_LOGIC; + SIGNAL niOO1lOlO : STD_LOGIC; + SIGNAL niOO1lOOi : STD_LOGIC; + SIGNAL niOO1lOOl : STD_LOGIC; + SIGNAL niOO1lOOO : STD_LOGIC; + SIGNAL niOO1O00i : STD_LOGIC; + SIGNAL niOO1O00l : STD_LOGIC; + SIGNAL niOO1O00O : STD_LOGIC; + SIGNAL niOO1O01i : STD_LOGIC; + SIGNAL niOO1O01l : STD_LOGIC; + SIGNAL niOO1O01O : STD_LOGIC; + SIGNAL niOO1O0ii : STD_LOGIC; + SIGNAL niOO1O0il : STD_LOGIC; + SIGNAL niOO1O0iO : STD_LOGIC; + SIGNAL niOO1O0li : STD_LOGIC; + SIGNAL niOO1O0ll : STD_LOGIC; + SIGNAL niOO1O0lO : STD_LOGIC; + SIGNAL niOO1O0Oi : STD_LOGIC; + SIGNAL niOO1O0Ol : STD_LOGIC; + SIGNAL niOO1O0OO : STD_LOGIC; + SIGNAL niOO1O10i : STD_LOGIC; + SIGNAL niOO1O10l : STD_LOGIC; + SIGNAL niOO1O10O : STD_LOGIC; + SIGNAL niOO1O11i : STD_LOGIC; + SIGNAL niOO1O11l : STD_LOGIC; + SIGNAL niOO1O11O : STD_LOGIC; + SIGNAL niOO1O1ii : STD_LOGIC; + SIGNAL niOO1O1il : STD_LOGIC; + SIGNAL niOO1O1iO : STD_LOGIC; + SIGNAL niOO1O1li : STD_LOGIC; + SIGNAL niOO1O1ll : STD_LOGIC; + SIGNAL niOO1O1lO : STD_LOGIC; + SIGNAL niOO1O1Oi : STD_LOGIC; + SIGNAL niOO1O1Ol : STD_LOGIC; + SIGNAL niOO1O1OO : STD_LOGIC; + SIGNAL niOO1Oi0i : STD_LOGIC; + SIGNAL niOO1Oi0l : STD_LOGIC; + SIGNAL niOO1Oi0O : STD_LOGIC; + SIGNAL niOO1Oi1i : STD_LOGIC; + SIGNAL niOO1Oi1l : STD_LOGIC; + SIGNAL niOO1Oi1O : STD_LOGIC; + SIGNAL niOO1Oiii : STD_LOGIC; + SIGNAL niOO1Oiil : STD_LOGIC; + SIGNAL niOO1OiiO : STD_LOGIC; + SIGNAL niOO1Oili : STD_LOGIC; + SIGNAL niOO1Oill : STD_LOGIC; + SIGNAL niOO1OilO : STD_LOGIC; + SIGNAL niOO1OiOi : STD_LOGIC; + SIGNAL niOO1OiOl : STD_LOGIC; + SIGNAL niOO1OiOO : STD_LOGIC; + SIGNAL niOO1Ol0i : STD_LOGIC; + SIGNAL niOO1Ol0l : STD_LOGIC; + SIGNAL niOO1Ol0O : STD_LOGIC; + SIGNAL niOO1Ol1i : STD_LOGIC; + SIGNAL niOO1Ol1l : STD_LOGIC; + SIGNAL niOO1Ol1O : STD_LOGIC; + SIGNAL niOO1Olii : STD_LOGIC; + SIGNAL niOO1Olil : STD_LOGIC; + SIGNAL niOO1OliO : STD_LOGIC; + SIGNAL niOO1Olli : STD_LOGIC; + SIGNAL niOO1Olll : STD_LOGIC; + SIGNAL niOO1OllO : STD_LOGIC; + SIGNAL niOO1OlOi : STD_LOGIC; + SIGNAL niOO1OlOl : STD_LOGIC; + SIGNAL niOO1OlOO : STD_LOGIC; + SIGNAL niOO1OO0i : STD_LOGIC; + SIGNAL niOO1OO0l : STD_LOGIC; + SIGNAL niOO1OO0O : STD_LOGIC; + SIGNAL niOO1OO1i : STD_LOGIC; + SIGNAL niOO1OO1l : STD_LOGIC; + SIGNAL niOO1OO1O : STD_LOGIC; + SIGNAL niOO1OOii : STD_LOGIC; + SIGNAL niOO1OOil : STD_LOGIC; + SIGNAL niOO1OOiO : STD_LOGIC; + SIGNAL niOO1OOli : STD_LOGIC; + SIGNAL niOO1OOll : STD_LOGIC; + SIGNAL niOO1OOlO : STD_LOGIC; + SIGNAL niOO1OOOi : STD_LOGIC; + SIGNAL niOO1OOOl : STD_LOGIC; + SIGNAL niOO1OOOO : STD_LOGIC; + SIGNAL w_ni00O11O10767w : STD_LOGIC; + SIGNAL w_nl0liO1Oi51818w : STD_LOGIC; + SIGNAL w_nl0lO0Oii50931w : STD_LOGIC; + SIGNAL w_nl0O01i1l50047w : STD_LOGIC; + SIGNAL wire_w_cpl_err_range8533w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_cpl_err_range8525w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_cpl_err_range8517w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_cpl_err_range8509w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phycfg_range7707w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phycfg_range7699w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phycfg_range7691w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phycfg_range7683w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phypm_range7753w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phypm_range7745w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phypm_range7737w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_dl_req_phypm_range7729w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45712w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range47794w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45915w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45913w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45911w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range49299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range47787w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range47783w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45710w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range47776w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range48482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45818w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range48494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45930w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45708w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range51061w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range51119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range51117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45805w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45803w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range45801w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range50184w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_bar_range47798w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range46288w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range46286w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range44263w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range44115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range43970w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range44000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range47998w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range48000w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range48002w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range48004w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range48006w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range48008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range48010w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range48012w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range29168w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range1869w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range46162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range46175w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range46173w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range46194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range24588w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_conf_range9950w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_dev_range52044w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_dev_range52047w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range28022w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range28020w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range54181w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range55029w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range25479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range25481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range2434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range1050w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range9015w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_gbl_hip_range23582w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_k_hip_range2413w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_mode_range8895w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_mode_range8897w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swdn_in_range8389w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swdn_in_range8381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swdn_in_range8373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swup_in_range8358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swup_in_range8350w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swup_in_range8342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swup_in_range8334w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swup_in_range8326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swup_in_range8318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_swup_in_range8310w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_test_in_hip_range61746w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_test_in_hip_range61747w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_test_in_hip_range61715w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_test_in_hip_range61717w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc0_0_range4011w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc0_0_range4013w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc0_0_range4016w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc0_0_range4008w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc0_0_range4005w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc1_0_range2393w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc1_0_range2395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc1_0_range2398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc1_0_range2390w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_tx_data_vc1_0_range2387w : STD_LOGIC_VECTOR (0 DOWNTO 0); + COMPONENT cycloneiv_pciehip_pciexp_dcram_rtry + GENERIC + ( + addr_width : NATURAL; + data_width : NATURAL + ); + PORT + ( + data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + rdclock : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + wrclock : IN STD_LOGIC; + wren : IN STD_LOGIC + ); + END COMPONENT; + COMPONENT cycloneiv_pciehip_pciexp_dcram_rxvc + GENERIC + ( + addr_width : NATURAL; + data_width : NATURAL + ); + PORT + ( + data : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + rdclock : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + wrclock : IN STD_LOGIC; + wren : IN STD_LOGIC + ); + END COMPONENT; + BEGIN + + wire_gnd <= '0'; + wire_vcc <= '1'; + wire_w20922w(0) <= wire_w_lg_w_lg_w_lg_niOl0l01i20919w20920w20921w(0) AND niOl0l00l; + wire_w_lg_w4020w4021w(0) <= wire_w4020w(0) AND niOO00O0O; + wire_w_lg_w2402w2403w(0) <= wire_w2402w(0) AND niOO0li1i; + wire_w_lg_w_lg_w_lg_niOl0l01i20919w20920w20921w(0) <= wire_w_lg_w_lg_niOl0l01i20919w20920w(0) AND niOl0l1lO; + wire_w_lg_w_lg_w_lg_niOl0l1OO20911w20912w20913w(0) <= wire_w_lg_w_lg_niOl0l1OO20911w20912w(0) AND niOl0Oiii; + wire_w_lg_w_lg_w_lg_niOi0010l53612w53627w53629w(0) <= wire_w_lg_w_lg_niOi0010l53612w53627w(0) AND wire_w_lg_niOi00O1O53628w(0); + wire_w_lg_w_lg_w_lg_niOiOilil35819w35821w35822w(0) <= wire_w_lg_w_lg_niOiOilil35819w35821w(0) AND wire_nlOiO010i_dataout; + wire_w_lg_w_lg_w_lg_niOiOilli35807w35809w35810w(0) <= wire_w_lg_w_lg_niOiOilli35807w35809w(0) AND wire_nlOiO01il_dataout; + wire_w_lg_w_lg_w_lg_niOiOiO0l35813w35815w35816w(0) <= wire_w_lg_w_lg_niOiOiO0l35813w35815w(0) AND wire_nlOiO01ii_dataout; + wire_w_lg_w_lg_w_lg_niOiOiOii35801w35803w35804w(0) <= wire_w_lg_w_lg_niOiOiOii35801w35803w(0) AND wire_nlOiO01ll_dataout; + wire_w_lg_w_lg_w_lg_niOlii0iO18300w18304w18305w(0) <= wire_w_lg_w_lg_niOlii0iO18300w18304w(0) AND wire_n1OiOl1O_o; + wire_w_lg_w_lg_w_lg_niOliliil17393w17397w17398w(0) <= wire_w_lg_w_lg_niOliliil17393w17397w(0) AND wire_n010i0ii_o; + wire_w_lg_w_lg_w_lg_niOliOlii16486w16490w16491w(0) <= wire_w_lg_w_lg_niOliOlii16486w16490w(0) AND wire_n01OOOll_o; + wire_w_lg_w_lg_w_lg_niOll1O0O15579w15583w15584w(0) <= wire_w_lg_w_lg_niOll1O0O15579w15583w(0) AND wire_n00liiOO_o; + wire_w_lg_w_lg_w_lg_niOlli10l14672w14676w14677w(0) <= wire_w_lg_w_lg_niOlli10l14672w14676w(0) AND wire_n0ii100i_o; + wire_w_lg_w_lg_w_lg_niOlll00i13765w13769w13770w(0) <= wire_w_lg_w_lg_niOlll00i13765w13769w(0) AND wire_n0l1iOil_o; + wire_w_lg_w_lg_w_lg_niOllOi1O12858w12862w12863w(0) <= wire_w_lg_w_lg_niOllOi1O12858w12862w(0) AND wire_n0lO1ilO_o; + wire_w_lg_w_lg_w_lg_niOlO1l1l11947w11951w11952w(0) <= wire_w_lg_w_lg_niOlO1l1l11947w11951w(0) AND wire_n0Oil01i_o; + wire_w_lg_w_lg_w_lg_niOO10l1i20908w21151w21152w(0) <= wire_w_lg_w_lg_niOO10l1i20908w21151w(0) AND niOli1iOl; + wire_w_lg_w_lg_w_lg_niOO10lOO8902w23242w23243w(0) <= wire_w_lg_w_lg_niOO10lOO8902w23242w(0) AND nlOlOilOl; + wire_w_lg_w_lg_w_lg_w_k_hip_range2413w2429w5669w5670w(0) <= wire_w_lg_w_lg_w_k_hip_range2413w2429w5669w(0) AND niOO010ii; + wire_w4018w(0) <= wire_w_lg_w_lg_w_tx_data_vc0_0_range4011w4012w4015w(0) AND wire_w_lg_w_tx_data_vc0_0_range4016w4017w(0); + wire_w4020w(0) <= wire_w_lg_w_lg_w_tx_data_vc0_0_range4008w4009w4010w(0) AND wire_w_lg_w4018w4019w(0); + wire_w2400w(0) <= wire_w_lg_w_lg_w_tx_data_vc1_0_range2393w2394w2397w(0) AND wire_w_lg_w_tx_data_vc1_0_range2398w2399w(0); + wire_w2402w(0) <= wire_w_lg_w_lg_w_tx_data_vc1_0_range2390w2391w2392w(0) AND wire_w_lg_w2400w2401w(0); + wire_w_lg_w_lg_niOi011ii54835w54836w(0) <= wire_w_lg_niOi011ii54835w(0) AND nl1OO010i; + wire_w_lg_w_lg_niOi1i10O59849w59850w(0) <= wire_w_lg_niOi1i10O59849w(0) AND wire_nl111011l_dataout; + wire_w_lg_w_lg_niOii1OOl52070w52071w(0) <= wire_w_lg_niOii1OOl52070w(0) AND niOii1llO; + wire_w_lg_w_lg_niOii1OOl52076w52077w(0) <= wire_w_lg_niOii1OOl52076w(0) AND niOii1llO; + wire_w_lg_w_lg_niOiiO0Ol47768w47769w(0) <= wire_w_lg_niOiiO0Ol47768w(0) AND wire_nl0Ol10li_o; + wire_w_lg_w_lg_niOiO1lii42830w42831w(0) <= wire_w_lg_niOiO1lii42830w(0) AND nlliiilil; + wire_w_lg_w_lg_niOiOi10l36263w36264w(0) <= wire_w_lg_niOiOi10l36263w(0) AND nll0O0iOl; + wire_w_lg_w_lg_niOl0l01i20919w20920w(0) <= wire_w_lg_niOl0l01i20919w(0) AND niOli101i; + wire_w_lg_w_lg_niOl0l1OO20911w20912w(0) <= wire_w_lg_niOl0l1OO20911w(0) AND niOl0l1Oi; + wire_w_lg_w_lg_tx_valid_vc04031w4033w(0) <= wire_w_lg_tx_valid_vc04031w(0) AND wire_w_lg_niOO00lOO4032w(0); + wire_w_lg_w_lg_tx_valid_vc12414w2416w(0) <= wire_w_lg_tx_valid_vc12414w(0) AND wire_w_lg_niOO0l0li2415w(0); + wire_w_lg_w_lg_w_k_conf_range29168w29169w29170w(0) <= wire_w_lg_w_k_conf_range29168w29169w(0) AND wire_nlOl1l0Ol_dataout; + wire_w_lg_w_lg_w_k_gbl_hip_range55029w55032w55033w(0) <= wire_w_lg_w_k_gbl_hip_range55029w55032w(0) AND niOi1Oiil; + wire_w_lg_w_lg_w_k_hip_range2413w5661w5662w(0) <= wire_w_lg_w_k_hip_range2413w5661w(0) AND niOO010ii; + wire_w_lg_w_lg_w_k_hip_range2413w3330w3332w(0) <= wire_w_lg_w_k_hip_range2413w3330w(0) AND wire_ni1llii_w_lg_n0Oli1i3331w(0); + wire_w_lg_w_lg_w_k_hip_range2413w5220w5224w(0) <= wire_w_lg_w_k_hip_range2413w5220w(0) AND wire_nl11llO_w_lg_w_lg_nlliO01l5221w5223w(0); + wire_w_lg_w_lg_w_k_hip_range2413w5663w5667w(0) <= wire_w_lg_w_k_hip_range2413w5663w(0) AND wire_nl1000i_w_lg_w_lg_w_lg_nliO0l1l5664w5665w5666w(0); + wire_w_lg_w_lg_niOi0010l53612w53627w(0) <= wire_w_lg_niOi0010l53612w(0) AND wire_w_lg_niOi00lil53626w(0); + wire_w_lg_w_lg_niOi001iO53573w53578w(0) <= wire_w_lg_niOi001iO53573w(0) AND wire_nlill0Oll_w53577w(0); + wire_w_lg_w_lg_niOi001iO53573w53579w(0) <= wire_w_lg_niOi001iO53573w(0) AND niOi001il; + wire_w_lg_w_lg_niOi0lOOi53212w53213w(0) <= wire_w_lg_niOi0lOOi53212w(0) AND niOi00O1l; + wire_w_lg_w_lg_niOi1i1Ol60233w60234w(0) <= wire_w_lg_niOi1i1Ol60233w(0) AND wire_nlill0Oll_w_lg_nl11OO00O59842w(0); + wire_w_lg_w_lg_niOi1OllO54888w56529w(0) <= wire_w_lg_niOi1OllO54888w(0) AND wire_nl1iiliOi_w_lg_o56528w(0); + wire_w_lg_w_lg_niOii1liO52084w52085w(0) <= wire_w_lg_niOii1liO52084w(0) AND niOii1lil; + wire_w_lg_w_lg_niOiiO0il47745w47748w(0) <= wire_w_lg_niOiiO0il47745w(0) AND wire_w_lg_w_lg_niOiiO0Ol47734w47747w(0); + wire_w_lg_w_lg_niOiiO0Ol47734w47764w(0) <= wire_w_lg_niOiiO0Ol47734w(0) AND wire_w_lg_niOiiO00O47763w(0); + wire_w_lg_w_lg_niOiiO0Ol47734w47747w(0) <= wire_w_lg_niOiiO0Ol47734w(0) AND wire_w_lg_niOiiO0ii47746w(0); + wire_w_lg_w_lg_niOiiO0Ol47734w47736w(0) <= wire_w_lg_niOiiO0Ol47734w(0) AND wire_w_lg_niOiiO0Oi47735w(0); + wire_w_lg_w_lg_niOilllOl44309w44310w(0) <= wire_w_lg_niOilllOl44309w(0) AND niOilll0i; + wire_w_lg_w_lg_niOilllOl44309w45114w(0) <= wire_w_lg_niOilllOl44309w(0) AND niOO10lii; + wire_w_lg_w_lg_niOilOO1i43375w43401w(0) <= wire_w_lg_niOilOO1i43375w(0) AND niOilOiii; + wire_w_lg_w_lg_niOilOO1i43375w43962w(0) <= wire_w_lg_niOilOO1i43375w(0) AND nlil00iiO; + wire_w_lg_w_lg_niOiOilil35819w35821w(0) <= wire_w_lg_niOiOilil35819w(0) AND wire_w_lg_niOiOillO35820w(0); + wire_w_lg_w_lg_niOiOilli35807w35809w(0) <= wire_w_lg_niOiOilli35807w(0) AND wire_w_lg_niOiOilOl35808w(0); + wire_w_lg_w_lg_niOiOiO0l35813w35815w(0) <= wire_w_lg_niOiOiO0l35813w(0) AND wire_w_lg_niOiOiO1i35814w(0); + wire_w_lg_w_lg_niOiOiO1l35899w35901w(0) <= wire_w_lg_niOiOiO1l35899w(0) AND wire_nl1000i_w_lg_nlli0iO1O35900w(0); + wire_w_lg_w_lg_niOiOiOii35801w35803w(0) <= wire_w_lg_niOiOiOii35801w(0) AND wire_w_lg_niOiOiO1O35802w(0); + wire_w_lg_w_lg_niOl0l0Ol24321w24322w(0) <= wire_w_lg_niOl0l0Ol24321w(0) AND niOl1lill; + wire_w_lg_w_lg_niOl0li0O24326w24327w(0) <= wire_w_lg_niOl0li0O24326w(0) AND niOl1lilO; + wire_w_lg_w_lg_niOl0li1i20883w20886w(0) <= wire_w_lg_niOl0li1i20883w(0) AND wire_w_lg_niOl0l0OO20885w(0); + wire_w_lg_w_lg_niOl0li1i20883w24187w(0) <= wire_w_lg_niOl0li1i20883w(0) AND wire_w_lg_niOl0l0OO24186w(0); + wire_w_lg_w_lg_niOl0liil20875w20878w(0) <= wire_w_lg_niOl0liil20875w(0) AND wire_w_lg_niOl0liii20877w(0); + wire_w_lg_w_lg_niOl0liil20875w24182w(0) <= wire_w_lg_niOl0liil20875w(0) AND wire_w_lg_niOl0liii24181w(0); + wire_w_lg_w_lg_niOl0liOi24331w24332w(0) <= wire_w_lg_niOl0liOi24331w(0) AND niOl1liOi; + wire_w_lg_w_lg_niOl0liOO20867w20870w(0) <= wire_w_lg_niOl0liOO20867w(0) AND wire_w_lg_niOl0liOl20869w(0); + wire_w_lg_w_lg_niOl0liOO20867w24177w(0) <= wire_w_lg_niOl0liOO20867w(0) AND wire_w_lg_niOl0liOl24176w(0); + wire_w_lg_w_lg_niOl0ll0l24336w24337w(0) <= wire_w_lg_niOl0ll0l24336w(0) AND niOl1liOl; + wire_w_lg_w_lg_niOl0llii20859w20862w(0) <= wire_w_lg_niOl0llii20859w(0) AND wire_w_lg_niOl0ll0O20861w(0); + wire_w_lg_w_lg_niOl0llii20859w24172w(0) <= wire_w_lg_niOl0llii20859w(0) AND wire_w_lg_niOl0ll0O24171w(0); + wire_w_lg_w_lg_niOl0lllO24341w24342w(0) <= wire_w_lg_niOl0lllO24341w(0) AND niOl1liOO; + wire_w_lg_w_lg_niOl0llOl20851w20854w(0) <= wire_w_lg_niOl0llOl20851w(0) AND wire_w_lg_niOl0llOi20853w(0); + wire_w_lg_w_lg_niOl0llOl20851w24167w(0) <= wire_w_lg_niOl0llOl20851w(0) AND wire_w_lg_niOl0llOi24166w(0); + wire_w_lg_w_lg_niOl0lO0i24346w24347w(0) <= wire_w_lg_niOl0lO0i24346w(0) AND niOl1ll1i; + wire_w_lg_w_lg_niOl0lO0O20843w20846w(0) <= wire_w_lg_niOl0lO0O20843w(0) AND wire_w_lg_niOl0lO0l20845w(0); + wire_w_lg_w_lg_niOl0lO0O20843w24162w(0) <= wire_w_lg_niOl0lO0O20843w(0) AND wire_w_lg_niOl0lO0l24161w(0); + wire_w_lg_w_lg_niOl0lOll24351w24352w(0) <= wire_w_lg_niOl0lOll24351w(0) AND niOl1ll1l; + wire_w_lg_w_lg_niOl0lOOi20835w20838w(0) <= wire_w_lg_niOl0lOOi20835w(0) AND wire_w_lg_niOl0lOlO20837w(0); + wire_w_lg_w_lg_niOl0lOOi20835w24157w(0) <= wire_w_lg_niOl0lOOi20835w(0) AND wire_w_lg_niOl0lOlO24156w(0); + wire_w_lg_w_lg_niOl0O10l20827w20830w(0) <= wire_w_lg_niOl0O10l20827w(0) AND wire_w_lg_niOl0O10i20829w(0); + wire_w_lg_w_lg_niOl0O10l20827w24152w(0) <= wire_w_lg_niOl0O10l20827w(0) AND wire_w_lg_niOl0O10i24151w(0); + wire_w_lg_w_lg_niOl0O11O24356w24357w(0) <= wire_w_lg_niOl0O11O24356w(0) AND niOl1ll1O; + wire_w_lg_w_lg_niOl0Oi1i23454w23455w(0) <= wire_w_lg_niOl0Oi1i23454w(0) AND n1lillil; + wire_w_lg_w_lg_niOl0Oiii20898w20915w(0) <= wire_w_lg_niOl0Oiii20898w(0) AND wire_w_lg_niOl0l0il20914w(0); + wire_w_lg_w_lg_niOl0Oiii20898w20899w(0) <= wire_w_lg_niOl0Oiii20898w(0) AND niOl0l0il; + wire_w_lg_w_lg_niOl0Ol0i21223w23872w(0) <= wire_w_lg_niOl0Ol0i21223w(0) AND wire_nlOii10ii_w_lg_w_lg_dataout23869w23871w(0); + wire_w_lg_w_lg_niOl10ilO28539w28540w(0) <= wire_w_lg_niOl10ilO28539w(0) AND niOl10l1i; + wire_w_lg_w_lg_niOli101i20192w23502w(0) <= wire_w_lg_niOli101i20192w(0) AND n1lillil; + wire_w_lg_w_lg_niOli101l20190w20191w(0) <= wire_w_lg_niOli101l20190w(0) AND n1lillil; + wire_w_lg_w_lg_niOlii0iO18300w18304w(0) <= wire_w_lg_niOlii0iO18300w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n1Oi101l18301w18302w18303w(0); + wire_w_lg_w_lg_niOliiiOO18267w18279w(0) <= wire_w_lg_niOliiiOO18267w(0) AND niOlii0OO; + wire_w_lg_w_lg_niOliilii18159w18433w(0) <= wire_w_lg_niOliilii18159w(0) AND wire_w_lg_niOliil0l18160w(0); + wire_w_lg_w_lg_niOliilii18159w18435w(0) <= wire_w_lg_niOliilii18159w(0) AND n1Ol001O; + wire_w_lg_w_lg_niOliilii18159w18297w(0) <= wire_w_lg_niOliilii18159w(0) AND niOlii0Oi; + wire_w_lg_w_lg_niOliliil17393w17397w(0) <= wire_w_lg_niOliliil17393w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n011iO0O17394w17395w17396w(0); + wire_w_lg_w_lg_niOlillOl17360w17372w(0) <= wire_w_lg_niOlillOl17360w(0) AND niOliliOl; + wire_w_lg_w_lg_niOlilO0O17252w17526w(0) <= wire_w_lg_niOlilO0O17252w(0) AND wire_w_lg_niOlilO0i17253w(0); + wire_w_lg_w_lg_niOlilO0O17252w17528w(0) <= wire_w_lg_niOlilO0O17252w(0) AND n010lOii; + wire_w_lg_w_lg_niOlilO0O17252w17390w(0) <= wire_w_lg_niOlilO0O17252w(0) AND niOlililO; + wire_w_lg_w_lg_niOliOlii16486w16490w(0) <= wire_w_lg_niOliOlii16486w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n01O1ili16487w16488w16489w(0); + wire_w_lg_w_lg_niOliOOOi16453w16465w(0) <= wire_w_lg_niOliOOOi16453w(0) AND niOliOlOi; + wire_w_lg_w_lg_niOll000i15438w15712w(0) <= wire_w_lg_niOll000i15438w(0) AND wire_w_lg_niOll001l15439w(0); + wire_w_lg_w_lg_niOll000i15438w15714w(0) <= wire_w_lg_niOll000i15438w(0) AND n00lO1OO; + wire_w_lg_w_lg_niOll000i15438w15576w(0) <= wire_w_lg_niOll000i15438w(0) AND niOll1Oli; + wire_w_lg_w_lg_niOll01lO15546w15558w(0) <= wire_w_lg_niOll01lO15546w(0) AND niOll1OlO; + wire_w_lg_w_lg_niOll110l16345w16619w(0) <= wire_w_lg_niOll110l16345w(0) AND wire_w_lg_niOll111O16346w(0); + wire_w_lg_w_lg_niOll110l16345w16621w(0) <= wire_w_lg_niOll110l16345w(0) AND n0010ill; + wire_w_lg_w_lg_niOll110l16345w16483w(0) <= wire_w_lg_niOll110l16345w(0) AND niOliOlll; + wire_w_lg_w_lg_niOll1O0O15579w15583w(0) <= wire_w_lg_niOll1O0O15579w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n00il1Ol15580w15581w15582w(0); + wire_w_lg_w_lg_niOlli0ll14639w14651w(0) <= wire_w_lg_niOlli0ll14639w(0) AND niOlli1ll; + wire_w_lg_w_lg_niOlli10l14672w14676w(0) <= wire_w_lg_niOlli10l14672w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n0i01O1O14673w14674w14675w(0); + wire_w_lg_w_lg_niOllii1O14531w14805w(0) <= wire_w_lg_niOllii1O14531w(0) AND wire_w_lg_niOllii1i14532w(0); + wire_w_lg_w_lg_niOllii1O14531w14807w(0) <= wire_w_lg_niOllii1O14531w(0) AND n0ii0O0i; + wire_w_lg_w_lg_niOllii1O14531w14669w(0) <= wire_w_lg_niOllii1O14531w(0) AND niOlli1iO; + wire_w_lg_w_lg_niOlll00i13765w13769w(0) <= wire_w_lg_niOlll00i13765w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n0iOliii13766w13767w13768w(0); + wire_w_lg_w_lg_niOlllili13732w13744w(0) <= wire_w_lg_niOlllili13732w(0) AND niOlll0li; + wire_w_lg_w_lg_niOllll1l13624w13898w(0) <= wire_w_lg_niOllll1l13624w(0) AND wire_w_lg_niOllliOO13625w(0); + wire_w_lg_w_lg_niOllll1l13624w13900w(0) <= wire_w_lg_niOllll1l13624w(0) AND n0l1Oiil; + wire_w_lg_w_lg_niOllll1l13624w13762w(0) <= wire_w_lg_niOllll1l13624w(0) AND niOlll0il; + wire_w_lg_w_lg_niOllOi1O12858w12862w(0) <= wire_w_lg_niOllOi1O12858w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n0ll01ll12859w12860w12861w(0); + wire_w_lg_w_lg_niOllOliO12825w12837w(0) <= wire_w_lg_niOllOliO12825w(0) AND niOllOiiO; + wire_w_lg_w_lg_niOllOO1i12717w12991w(0) <= wire_w_lg_niOllOO1i12717w(0) AND wire_w_lg_niOllOlOl12718w(0); + wire_w_lg_w_lg_niOllOO1i12717w12993w(0) <= wire_w_lg_niOllOO1i12717w(0) AND n0lOi1lO; + wire_w_lg_w_lg_niOllOO1i12717w12855w(0) <= wire_w_lg_niOllOO1i12717w(0) AND niOllOiii; + wire_w_lg_w_lg_niOlO011i11806w12080w(0) <= wire_w_lg_niOlO011i11806w(0) AND wire_w_lg_niOlO1OOl11807w(0); + wire_w_lg_w_lg_niOlO011i11806w12082w(0) <= wire_w_lg_niOlO011i11806w(0) AND n0OiOO1i; + wire_w_lg_w_lg_niOlO011i11806w11944w(0) <= wire_w_lg_niOlO011i11806w(0) AND niOlO1l0O; + wire_w_lg_w_lg_niOlO1l1l11947w11951w(0) <= wire_w_lg_niOlO1l1l11947w(0) AND wire_niO01iOi_w_lg_w_lg_w_lg_n0O0llOO11948w11949w11950w(0); + wire_w_lg_w_lg_niOlO1O0i20967w23870w(0) <= wire_w_lg_niOlO1O0i20967w(0) AND wire_w_lg_niOl1OOli23839w(0); + wire_w_lg_w_lg_niOlO1OiO11914w11926w(0) <= wire_w_lg_niOlO1OiO11914w(0) AND niOlO1lil; + wire_w_lg_w_lg_niOlOl0Ol10165w11472w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0ilO; + wire_w_lg_w_lg_niOlOl0Ol10165w11468w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0iOl; + wire_w_lg_w_lg_niOlOl0Ol10165w11456w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0l0l; + wire_w_lg_w_lg_niOlOl0Ol10165w11464w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0l1i; + wire_w_lg_w_lg_niOlOl0Ol10165w11460w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0l1O; + wire_w_lg_w_lg_niOlOl0Ol10165w11452w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0liO; + wire_w_lg_w_lg_niOlOl0Ol10165w11391w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0lOl; + wire_w_lg_w_lg_niOlOl0Ol10165w11379w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0O0l; + wire_w_lg_w_lg_niOlOl0Ol10165w11387w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0O1i; + wire_w_lg_w_lg_niOlOl0Ol10165w11383w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0O1O; + wire_w_lg_w_lg_niOlOl0Ol10165w11375w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0Oii; + wire_w_lg_w_lg_niOlOl0Ol10165w11371w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlO0Oll; + wire_w_lg_w_lg_niOlOl0Ol10165w11225w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi00l; + wire_w_lg_w_lg_niOlOl0Ol10165w11229w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi01O; + wire_w_lg_w_lg_niOlOl0Ol10165w11221w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi0ii; + wire_w_lg_w_lg_niOlOl0Ol10165w11217w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi0iO; + wire_w_lg_w_lg_niOlOl0Ol10165w11213w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi0ll; + wire_w_lg_w_lg_niOlOl0Ol10165w11209w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi0OO; + wire_w_lg_w_lg_niOlOl0Ol10165w11302w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi10l; + wire_w_lg_w_lg_niOlOl0Ol10165w11310w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi11i; + wire_w_lg_w_lg_niOlOl0Ol10165w11306w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi11O; + wire_w_lg_w_lg_niOlOl0Ol10165w11298w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi1ii; + wire_w_lg_w_lg_niOlOl0Ol10165w11294w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi1iO; + wire_w_lg_w_lg_niOlOl0Ol10165w11290w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOi1Oi; + wire_w_lg_w_lg_niOlOl0Ol10165w11148w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOii0l; + wire_w_lg_w_lg_niOlOl0Ol10165w11144w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiiii; + wire_w_lg_w_lg_niOlOl0Ol10165w11140w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiiiO; + wire_w_lg_w_lg_niOlOl0Ol10165w11136w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiill; + wire_w_lg_w_lg_niOlOl0Ol10165w11132w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiiOi; + wire_w_lg_w_lg_niOlOl0Ol10165w11128w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOil1l; + wire_w_lg_w_lg_niOlOl0Ol10165w11067w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOilii; + wire_w_lg_w_lg_niOlOl0Ol10165w11063w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiliO; + wire_w_lg_w_lg_niOlOl0Ol10165w11059w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOilll; + wire_w_lg_w_lg_niOlOl0Ol10165w11055w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOilOi; + wire_w_lg_w_lg_niOlOl0Ol10165w11051w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOilOO; + wire_w_lg_w_lg_niOlOl0Ol10165w11047w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiO0i; + wire_w_lg_w_lg_niOlOl0Ol10165w10986w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiOiO; + wire_w_lg_w_lg_niOlOl0Ol10165w10982w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiOll; + wire_w_lg_w_lg_niOlOl0Ol10165w10978w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiOOi; + wire_w_lg_w_lg_niOlOl0Ol10165w10974w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOiOOO; + wire_w_lg_w_lg_niOlOl0Ol10165w10889w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl00i; + wire_w_lg_w_lg_niOlOl0Ol10165w10893w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl01l; + wire_w_lg_w_lg_niOlOl0Ol10165w10885w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl0il; + wire_w_lg_w_lg_niOlOl0Ol10165w10966w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl10O; + wire_w_lg_w_lg_niOlOl0Ol10165w10970w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl11l; + wire_w_lg_w_lg_niOlOl0Ol10165w10905w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl1ll; + wire_w_lg_w_lg_niOlOl0Ol10165w10901w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl1Oi; + wire_w_lg_w_lg_niOlOl0Ol10165w10897w(0) <= wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl1OO; + wire_w_lg_w_lg_niOlOllll10854w10874w(0) <= wire_w_lg_niOlOllll10854w(0) AND niOlOl0ii; + wire_w_lg_w_lg_niOlOlO0l10935w10955w(0) <= wire_w_lg_niOlOlO0l10935w(0) AND niOlOl10l; + wire_w_lg_w_lg_niOlOlOOl11016w11036w(0) <= wire_w_lg_niOlOlOOl11016w(0) AND niOlOiO1O; + wire_w_lg_w_lg_niOlOO01l11178w11198w(0) <= wire_w_lg_niOlOO01l11178w(0) AND niOlOi0Ol; + wire_w_lg_w_lg_niOlOO0ll11259w11279w(0) <= wire_w_lg_niOlOO0ll11259w(0) AND niOlOi1lO; + wire_w_lg_w_lg_niOlOO1il11097w11117w(0) <= wire_w_lg_niOlOO1il11097w(0) AND niOlOil1i; + wire_w_lg_w_lg_niOlOOi0l11340w11360w(0) <= wire_w_lg_niOlOOi0l11340w(0) AND niOlO0Oli; + wire_w_lg_w_lg_niOlOOiOl11421w11441w(0) <= wire_w_lg_niOlOOiOl11421w(0) AND niOlO0lil; + wire_w_lg_w_lg_niOlOOO1O9954w9955w(0) <= wire_w_lg_niOlOOO1O9954w(0) AND niOlOOO1l; + wire_w_lg_w_lg_niOO000ll4352w29665w(0) <= wire_w_lg_niOO000ll4352w(0) AND nlO1Oi10l; + wire_w_lg_w_lg_niOO00llO4046w4048w(0) <= wire_w_lg_niOO00llO4046w(0) AND wire_w_lg_niOO00lll4047w(0); + wire_w_lg_w_lg_niOO10l1i20908w21151w(0) <= wire_w_lg_niOO10l1i20908w(0) AND wire_niO01ill_w_lg_n11li1ii21150w(0); + wire_w_lg_w_lg_niOO10lOO8902w21166w(0) <= wire_w_lg_niOO10lOO8902w(0) AND wire_nlOii0l0O_dataout; + wire_w_lg_w_lg_niOO10lOO8902w21191w(0) <= wire_w_lg_niOO10lOO8902w(0) AND n1110Oil; + wire_w_lg_w_lg_niOO10lOO8902w23242w(0) <= wire_w_lg_niOO10lOO8902w(0) AND n11O0iOl; + wire_w_lg_w_lg_niOO10lOO8902w23489w(0) <= wire_w_lg_niOO10lOO8902w(0) AND niOli1OiO; + wire_w_lg_w_lg_niOO1iiiO8535w8537w(0) <= wire_w_lg_niOO1iiiO8535w(0) AND wire_w_lg_w_cpl_err_range8533w8536w(0); + wire_w_lg_w_lg_niOO1iili8527w8529w(0) <= wire_w_lg_niOO1iili8527w(0) AND wire_w_lg_w_cpl_err_range8525w8528w(0); + wire_w_lg_w_lg_niOO1iill8519w8521w(0) <= wire_w_lg_niOO1iill8519w(0) AND wire_w_lg_w_cpl_err_range8517w8520w(0); + wire_w_lg_w_lg_niOO1iilO8511w8513w(0) <= wire_w_lg_niOO1iilO8511w(0) AND wire_w_lg_w_cpl_err_range8509w8512w(0); + wire_w_lg_w_lg_w_k_bar_range45712w45713w51280w(0) <= wire_w_lg_w_k_bar_range45712w45713w(0) AND niOii00ii; + wire_w_lg_w_lg_w_k_bar_range45915w45916w49517w(0) <= wire_w_lg_w_k_bar_range45915w45916w(0) AND niOiiO1iO; + wire_w_lg_w_lg_w_k_bar_range45913w45914w49643w(0) <= wire_w_lg_w_k_bar_range45913w45914w(0) AND wire_w_k_bar_range45911w(0); + wire_w_lg_w_lg_w_k_bar_range47787w47788w47789w(0) <= wire_w_lg_w_k_bar_range47787w47788w(0) AND niOiiO1iO; + wire_w_lg_w_lg_w_k_bar_range45710w45711w51414w(0) <= wire_w_lg_w_k_bar_range45710w45711w(0) AND wire_w_k_bar_range45708w(0); + wire_w_lg_w_lg_w_k_bar_range51119w51288w51289w(0) <= wire_w_lg_w_k_bar_range51119w51288w(0) AND niOii00ii; + wire_w_lg_w_lg_w_k_bar_range45805w45806w50402w(0) <= wire_w_lg_w_k_bar_range45805w45806w(0) AND niOiiO10l; + wire_w_lg_w_lg_w_k_bar_range45803w45804w50527w(0) <= wire_w_lg_w_k_bar_range45803w45804w(0) AND wire_w_k_bar_range45801w(0); + wire_w_lg_w_lg_w_k_bar_range47798w47799w47800w(0) <= wire_w_lg_w_k_bar_range47798w47799w(0) AND niOiiO10l; + wire_w_lg_w_lg_w_k_conf_range1869w46186w46226w(0) <= wire_w_lg_w_k_conf_range1869w46186w(0) AND nl0iOiOll; + wire_w_lg_w_lg_w_k_conf_range9950w9951w9959w(0) <= wire_w_lg_w_k_conf_range9950w9951w(0) AND niOlOOO0i; + wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3415w(0) <= wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_ni1lOlO_w_lg_n0Ol0OO3414w(0); + wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3417w(0) <= wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_ni1lOlO_w_lg_n0Ol0OO3389w(0); + wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5729w(0) <= wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_nl1000i_w_lg_nlliO01i5728w(0); + wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5731w(0) <= wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_nl1000i_w_lg_nlliO01i5704w(0); + wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3419w(0) <= wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND n0Ol0Oi; + wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5733w(0) <= wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND nlliO1Ol; + wire_w_lg_w_lg_w_k_gbl_hip_range23582w23583w23584w(0) <= wire_w_lg_w_k_gbl_hip_range23582w23583w(0) AND n111i0il; + wire_w_lg_w_lg_w_k_hip_range2413w2429w5669w(0) <= wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_nl1000i_w_lg_nll0O0iOl5342w(0); + wire_w_lg_w_lg_w_tx_data_vc0_0_range4011w4012w4015w(0) <= wire_w_lg_w_tx_data_vc0_0_range4011w4012w(0) AND wire_w_lg_w_tx_data_vc0_0_range4013w4014w(0); + wire_w_lg_w_lg_w_tx_data_vc0_0_range4008w4009w4010w(0) <= wire_w_lg_w_tx_data_vc0_0_range4008w4009w(0) AND wire_w_tx_data_vc0_0_range4005w(0); + wire_w_lg_w_lg_w_tx_data_vc0_0_range4005w4006w4007w(0) <= wire_w_lg_w_tx_data_vc0_0_range4005w4006w(0) AND niOO00O0O; + wire_w_lg_w_lg_w_tx_data_vc1_0_range2393w2394w2397w(0) <= wire_w_lg_w_tx_data_vc1_0_range2393w2394w(0) AND wire_w_lg_w_tx_data_vc1_0_range2395w2396w(0); + wire_w_lg_w_lg_w_tx_data_vc1_0_range2390w2391w2392w(0) <= wire_w_lg_w_tx_data_vc1_0_range2390w2391w(0) AND wire_w_tx_data_vc1_0_range2387w(0); + wire_w_lg_w_lg_w_tx_data_vc1_0_range2387w2388w2389w(0) <= wire_w_lg_w_tx_data_vc1_0_range2387w2388w(0) AND niOO0li1i; + wire_w_lg_w20916w20917w(0) <= wire_w20916w(0) AND niOl0l01i; + wire_w54874w(0) <= wire_w_lg_w_lg_w_lg_niOi1Olii54871w54872w54873w(0) AND nl1ll0iOi; + wire_w_lg_w_lg_w_lg_niOliii0l18289w18291w18292w(0) <= wire_w_lg_w_lg_niOliii0l18289w18291w(0) AND niOliii1i; + wire_w_lg_w_lg_w_lg_niOlill0i17382w17384w17385w(0) <= wire_w_lg_w_lg_niOlill0i17382w17384w(0) AND niOliliOO; + wire_w_lg_w_lg_w_lg_niOliOO1O16475w16477w16478w(0) <= wire_w_lg_w_lg_niOliOO1O16475w16477w(0) AND niOliOlOl; + wire_w_lg_w_lg_w_lg_niOll011l15568w15570w15571w(0) <= wire_w_lg_w_lg_niOll011l15568w15570w(0) AND niOll1OOi; + wire_w_lg_w_lg_w_lg_niOlli01i14661w14663w14664w(0) <= wire_w_lg_w_lg_niOlli01i14661w14663w(0) AND niOlli1lO; + wire_w_lg_w_lg_w_lg_niOlll0OO13754w13756w13757w(0) <= wire_w_lg_w_lg_niOlll0OO13754w13756w(0) AND niOlll0ll; + wire_w_lg_w_lg_w_lg_niOllOiOl12847w12849w12850w(0) <= wire_w_lg_w_lg_niOllOiOl12847w12849w(0) AND niOllOili; + wire_w_lg_w_lg_w_lg_niOlO1lOi11936w11938w11939w(0) <= wire_w_lg_w_lg_niOlO1lOi11936w11938w(0) AND niOlO1liO; + wire_w_lg_w_lg_w_lg_niOO01lll5093w5094w5095w(0) <= wire_w_lg_w_lg_niOO01lll5093w5094w(0) AND nlliO11i; + wire_w_lg_w_lg_w_lg_w_lg_niOO00l0i4100w4103w4104w4105w(0) <= wire_w_lg_w_lg_w_lg_niOO00l0i4100w4103w4104w(0) AND n1l010l; + wire_w_lg_w_lg_w_lg_w_lg_niOO0l01l2477w2480w2481w2482w(0) <= wire_w_lg_w_lg_w_lg_niOO0l01l2477w2480w2481w(0) AND ni1llli; + wire_w_lg_w_lg_niOi00OOO53184w53185w(0) <= wire_w_lg_niOi00OOO53184w(0) AND nl01l0l0l; + wire_w_lg_w_lg_niOi1Olii54871w54872w(0) <= wire_w_lg_niOi1Olii54871w(0) AND niOi1Ol0l; + wire_w_lg_w_lg_niOiiO00O47759w47760w(0) <= wire_w_lg_niOiiO00O47759w(0) AND niOiiO0iO; + wire_w_lg_w_lg_niOiiO0lO47741w47742w(0) <= wire_w_lg_niOiiO0lO47741w(0) AND niOiiO0iO; + wire_w_lg_w_lg_niOilOO0l44001w44002w(0) <= wire_w_lg_niOilOO0l44001w(0) AND niOillOOO; + wire_w_lg_w_lg_niOli11il20299w20300w(0) <= wire_w_lg_niOli11il20299w(0) AND n1lillil; + wire_w_lg_w_lg_niOO01llO5097w5098w(0) <= wire_w_lg_niOO01llO5097w(0) AND nllilO1i; + wire_w_lg_niOi001iO53582w(0) <= niOi001iO AND wire_w_lg_niOi001il53581w(0); + wire_w_lg_niOi00i0l53401w(0) <= niOi00i0l AND wire_w_lg_niOili0iO53400w(0); + wire_w_lg_niOi00iii53398w(0) <= niOi00iii AND wire_w_lg_niOili0li53397w(0); + wire_w_lg_niOi00iiO53395w(0) <= niOi00iiO AND wire_w_lg_niOili0ll53394w(0); + wire_w_lg_niOi00l1i53429w(0) <= niOi00l1i AND wire_nli1lli1i_w_lg_w_lg_dataout53427w53428w(0); + wire_w_lg_niOi00l1l53424w(0) <= niOi00l1l AND wire_nli1ll0OO_w_lg_dataout53423w(0); + wire_w_lg_niOi00Oli53183w(0) <= niOi00Oli AND wire_w_lg_niOi00OOO53182w(0); + wire_w_lg_niOi00Oll53194w(0) <= niOi00Oll AND wire_nl00l111l_w_lg_w_lg_dataout53191w53193w(0); + wire_w_lg_niOi0110l54839w(0) <= niOi0110l AND wire_nlill0Oll_w_lg_w_lg_nl1OO010l54837w54838w(0); + wire_w_lg_niOi011ii54835w(0) <= niOi011ii AND wire_w_lg_niOi0110O54834w(0); + wire_w_lg_niOi01i0l55508w(0) <= niOi01i0l AND wire_nl1lOOl0l_w_lg_dataout54725w(0); + wire_w_lg_niOi01i0l54727w(0) <= niOi01i0l AND wire_w_lg_niOi1OO1i54726w(0); + wire_w_lg_niOi01i0l55397w(0) <= niOi01i0l AND niOi1O1ii; + wire_w_lg_niOi0lOii53437w(0) <= niOi0lOii AND nl01O011l; + wire_w_lg_niOi0lOOi53215w(0) <= niOi0lOOi AND wire_w_lg_niOi00O1i53214w(0); + wire_w_lg_niOi0lOOi53624w(0) <= niOi0lOOi AND niOi00O1l; + wire_w_lg_niOi10lOl59875w(0) <= niOi10lOl AND wire_nl10iiOOl_w_lg_w_lg_dataout59597w59874w(0); + wire_w_lg_niOi10lOl59871w(0) <= niOi10lOl AND wire_nl10iiOOl_w_lg_dataout59870w(0); + wire_w_lg_niOi10O0O59712w(0) <= niOi10O0O AND wire_w_lg_niOili0iO53400w(0); + wire_w_lg_niOi10Oil59710w(0) <= niOi10Oil AND wire_w_lg_niOili0li53397w(0); + wire_w_lg_niOi1i10O59849w(0) <= niOi1i10O AND niOi10liO; + wire_w_lg_niOi1ii0l58908w(0) <= niOi1ii0l AND wire_w_lg_niOi1ii0i58907w(0); + wire_w_lg_niOi1iiiO58800w(0) <= niOi1iiiO AND wire_w_lg_niOi1iiil58799w(0); + wire_w_lg_niOi1iiOi58693w(0) <= niOi1iiOi AND wire_w_lg_niOi1iilO58692w(0); + wire_w_lg_niOi1O11O55414w(0) <= niOi1O11O AND wire_w_lg_niOi1O11i55413w(0); + wire_w_lg_niOi1Ol1O54885w(0) <= niOi1Ol1O AND wire_nlill0Oll_w_lg_w_lg_w_lg_nl1OllOOO54880w54882w54884w(0); + wire_w_lg_niOi1OliO55198w(0) <= niOi1OliO AND nl1OillOi; + wire_w_lg_niOi1OlOi55403w(0) <= niOi1OlOi AND wire_nl1OlOi1l_w_lg_dataout55402w(0); + wire_w_lg_niOii1l0i52104w(0) <= niOii1l0i AND wire_w_lg_niOi0Olli52103w(0); + wire_w_lg_niOii1liO52092w(0) <= niOii1liO AND niOii1lil; + wire_w_lg_niOii1OiO52069w(0) <= niOii1OiO AND niOii1lli; + wire_w_lg_niOii1OOl52070w(0) <= niOii1OOl AND wire_w_lg_niOii1OiO52069w(0); + wire_w_lg_niOii1OOl52076w(0) <= niOii1OOl AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_w_lg_niOiili0O48151w(0) <= niOiili0O AND wire_w_lg_niOili0ii48150w(0); + wire_w_lg_niOiill0O48070w(0) <= niOiill0O AND wire_nlill0Oll_w_lg_nli10011i48069w(0); + wire_w_lg_niOiillil48057w(0) <= niOiillil AND wire_nlill0Oll_w_lg_w_lg_nli1i011i48055w48056w(0); + wire_w_lg_niOiiO0Ol47768w(0) <= niOiiO0Ol AND wire_nl0Ol10lO_o; + wire_w_lg_niOiiOi1l48051w(0) <= niOiiOi1l AND wire_nlill0Oll_w_lg_nli10Olll48050w(0); + wire_w_lg_niOili01O51907w(0) <= niOili01O AND wire_w_lg_w_lg_w_k_conf_range1869w46275w51906w(0); + wire_w_lg_niOili0ii48150w(0) <= niOili0ii AND niOiilO1O; + wire_w_lg_niOilliOl45266w(0) <= niOilliOl AND wire_w_lg_w_lg_niOilllOl45264w45265w(0); + wire_w_lg_niOilliOO45272w(0) <= niOilliOO AND wire_nliiOliOi_w_lg_w_lg_w_lg_dataout44320w45270w45271w(0); + wire_w_lg_niOilll0i44317w(0) <= niOilll0i AND wire_nliiOiilO_w_lg_nliiO011l44316w(0); + wire_w_lg_niOilll0i44301w(0) <= niOilll0i AND wire_nliiOiilO_w_lg_nliiO0iii44300w(0); + wire_w_lg_niOilll0i44295w(0) <= niOilll0i AND wire_nliiOiilO_w_lg_nliiO0iil44294w(0); + wire_w_lg_niOilll0i44285w(0) <= niOilll0i AND wire_nliiO0iOl_w_lg_nliiO0ili44284w(0); + wire_w_lg_niOilll0i44280w(0) <= niOilll0i AND wire_nliiOiilO_w_lg_nliiO0ill44279w(0); + wire_w_lg_niOilllOi53566w(0) <= niOilllOi AND wire_nl01l01iO_w_lg_dataout53565w(0); + wire_w_lg_niOilllOl45264w(0) <= niOilllOl AND nliiO0O0O; + wire_w_lg_niOilO0iO43943w(0) <= niOilO0iO AND wire_nlill0Oll_w_lg_nlil01i0i43942w(0); + wire_w_lg_niOilOlOO43941w(0) <= niOilOlOO AND wire_nlill0Oll_w_lg_nlil1lOil43935w(0); + wire_w_lg_niOilOO1i43390w(0) <= niOilOO1i AND wire_w_lg_niOilOlOO43389w(0); + wire_w_lg_niOilOO1i43936w(0) <= niOilOO1i AND wire_nlill0Oll_w_lg_nlil1lOil43935w(0); + wire_w_lg_niOilOO1i43987w(0) <= niOilOO1i AND wire_w_lg_w_lg_niOilOi1O43404w43986w(0); + wire_w_lg_niOiO0Oll36547w(0) <= niOiO0Oll AND wire_nl1000i_w_lg_nll0ll1OO36546w(0); + wire_w_lg_niOiO1lii42830w(0) <= niOiO1lii AND nlliiiliO; + wire_w_lg_niOiOi10l36263w(0) <= niOiOi10l AND wire_nlOiOi11i_w_lg_dataout36238w(0); + wire_w_lg_niOiOii0l35874w(0) <= niOiOii0l AND wire_nl1000i_w_lg_w_lg_w_lg_nlliliiOO35871w35872w35873w(0); + wire_w_lg_niOiOiiil35854w(0) <= niOiOiiil AND wire_nl1000i_w_lg_niOOi1i0i35853w(0); + wire_w_lg_niOiOiiiO35851w(0) <= niOiOiiiO AND wire_nl1000i_w_lg_niOOi1i0i35850w(0); + wire_w_lg_niOiOiili35848w(0) <= niOiOiili AND wire_nl1000i_w_lg_w_lg_niOOi1i0i35846w35847w(0); + wire_w_lg_niOiOilii35902w(0) <= niOiOilii AND wire_w_lg_w_lg_niOiOiO1l35899w35901w(0); + wire_w_lg_niOiOiliO35911w(0) <= niOiOiliO AND wire_nl1000i_w_lg_w_lg_nllilOlOi35909w35910w(0); + wire_w_lg_niOiOiO1l35907w(0) <= niOiOiO1l AND wire_w_lg_w_lg_niOiOilii35903w35906w(0); + wire_w_lg_niOiOiOli36492w(0) <= niOiOiOli AND wire_nl1000i_w_lg_nll0OOOOi36491w(0); + wire_w_lg_niOl01l0i23892w(0) <= niOl01l0i AND wire_w_lg_niOO10lOO23891w(0); + wire_w_lg_niOl0i0OO21015w(0) <= niOl0i0OO AND wire_w_lg_niOlOOlOl21014w(0); + wire_w_lg_niOl0l01i20919w(0) <= niOl0l01i AND wire_w_lg_niOl0l0li20891w(0); + wire_w_lg_niOl0l0Ol24258w(0) <= niOl0l0Ol AND n0O0O0OO; + wire_w_lg_niOl0l0Ol20884w(0) <= niOl0l0Ol AND niOl0l0Oi; + wire_w_lg_niOl0l0Ol24185w(0) <= niOl0l0Ol AND niOl1lill; + wire_w_lg_niOl0l0OO24219w(0) <= niOl0l0OO AND wire_nlOOO0l1O_w_lg_dataout24218w(0); + wire_w_lg_niOl0l0OO24259w(0) <= niOl0l0OO AND wire_w_lg_niOl0l0Ol24258w(0); + wire_w_lg_niOl0l0OO20885w(0) <= niOl0l0OO AND wire_w_lg_niOl0l0Ol20884w(0); + wire_w_lg_niOl0l0OO24186w(0) <= niOl0l0OO AND wire_w_lg_niOl0l0Ol24185w(0); + wire_w_lg_niOl0l1OO20911w(0) <= niOl0l1OO AND niOl0l1Ol; + wire_w_lg_niOl0li0O24254w(0) <= niOl0li0O AND n0ll0lll; + wire_w_lg_niOl0li0O20876w(0) <= niOl0li0O AND niOl0li0l; + wire_w_lg_niOl0li0O24180w(0) <= niOl0li0O AND niOl1lilO; + wire_w_lg_niOl0li1l20887w(0) <= niOl0li1l AND wire_w_lg_w_lg_niOl0li1i20883w20886w(0); + wire_w_lg_niOl0li1l24188w(0) <= niOl0li1l AND wire_w_lg_w_lg_niOl0li1i20883w24187w(0); + wire_w_lg_niOl0liii24215w(0) <= niOl0liii AND wire_nlOOO0l0O_w_lg_dataout24214w(0); + wire_w_lg_niOl0liii24255w(0) <= niOl0liii AND wire_w_lg_niOl0li0O24254w(0); + wire_w_lg_niOl0liii20877w(0) <= niOl0liii AND wire_w_lg_niOl0li0O20876w(0); + wire_w_lg_niOl0liii24181w(0) <= niOl0liii AND wire_w_lg_niOl0li0O24180w(0); + wire_w_lg_niOl0liiO20879w(0) <= niOl0liiO AND wire_w_lg_w_lg_niOl0liil20875w20878w(0); + wire_w_lg_niOl0liiO24183w(0) <= niOl0liiO AND wire_w_lg_w_lg_niOl0liil20875w24182w(0); + wire_w_lg_niOl0liOi24250w(0) <= niOl0liOi AND n0iOO1ii; + wire_w_lg_niOl0liOi20868w(0) <= niOl0liOi AND niOl0lilO; + wire_w_lg_niOl0liOi24175w(0) <= niOl0liOi AND niOl1liOi; + wire_w_lg_niOl0liOl24211w(0) <= niOl0liOl AND wire_nlOOO0liO_w_lg_dataout24210w(0); + wire_w_lg_niOl0liOl24251w(0) <= niOl0liOl AND wire_w_lg_niOl0liOi24250w(0); + wire_w_lg_niOl0liOl20869w(0) <= niOl0liOl AND wire_w_lg_niOl0liOi20868w(0); + wire_w_lg_niOl0liOl24176w(0) <= niOl0liOl AND wire_w_lg_niOl0liOi24175w(0); + wire_w_lg_niOl0ll0l24246w(0) <= niOl0ll0l AND n0i00i1O; + wire_w_lg_niOl0ll0l20860w(0) <= niOl0ll0l AND niOl0ll0i; + wire_w_lg_niOl0ll0l24170w(0) <= niOl0ll0l AND niOl1liOl; + wire_w_lg_niOl0ll0O24207w(0) <= niOl0ll0O AND wire_nlOOO0llO_w_lg_dataout24206w(0); + wire_w_lg_niOl0ll0O24247w(0) <= niOl0ll0O AND wire_w_lg_niOl0ll0l24246w(0); + wire_w_lg_niOl0ll0O20861w(0) <= niOl0ll0O AND wire_w_lg_niOl0ll0l20860w(0); + wire_w_lg_niOl0ll0O24171w(0) <= niOl0ll0O AND wire_w_lg_niOl0ll0l24170w(0); + wire_w_lg_niOl0ll1i20871w(0) <= niOl0ll1i AND wire_w_lg_w_lg_niOl0liOO20867w20870w(0); + wire_w_lg_niOl0ll1i24178w(0) <= niOl0ll1i AND wire_w_lg_w_lg_niOl0liOO20867w24177w(0); + wire_w_lg_niOl0llil20863w(0) <= niOl0llil AND wire_w_lg_w_lg_niOl0llii20859w20862w(0); + wire_w_lg_niOl0llil24173w(0) <= niOl0llil AND wire_w_lg_w_lg_niOl0llii20859w24172w(0); + wire_w_lg_niOl0lllO24242w(0) <= niOl0lllO AND n00illOl; + wire_w_lg_niOl0lllO20852w(0) <= niOl0lllO AND niOl0llll; + wire_w_lg_niOl0lllO24165w(0) <= niOl0lllO AND niOl1liOO; + wire_w_lg_niOl0llOi24203w(0) <= niOl0llOi AND wire_nlOOO0lOO_w_lg_dataout24202w(0); + wire_w_lg_niOl0llOi24243w(0) <= niOl0llOi AND wire_w_lg_niOl0lllO24242w(0); + wire_w_lg_niOl0llOi20853w(0) <= niOl0llOi AND wire_w_lg_niOl0lllO20852w(0); + wire_w_lg_niOl0llOi24166w(0) <= niOl0llOi AND wire_w_lg_niOl0lllO24165w(0); + wire_w_lg_niOl0llOO20855w(0) <= niOl0llOO AND wire_w_lg_w_lg_niOl0llOl20851w20854w(0); + wire_w_lg_niOl0llOO24168w(0) <= niOl0llOO AND wire_w_lg_w_lg_niOl0llOl20851w24167w(0); + wire_w_lg_niOl0lO0i24238w(0) <= niOl0lO0i AND n01O01li; + wire_w_lg_niOl0lO0i20844w(0) <= niOl0lO0i AND niOl0lO1O; + wire_w_lg_niOl0lO0i24160w(0) <= niOl0lO0i AND niOl1ll1i; + wire_w_lg_niOl0lO0l24199w(0) <= niOl0lO0l AND wire_nlOOO0O1O_w_lg_dataout24198w(0); + wire_w_lg_niOl0lO0l24239w(0) <= niOl0lO0l AND wire_w_lg_niOl0lO0i24238w(0); + wire_w_lg_niOl0lO0l20845w(0) <= niOl0lO0l AND wire_w_lg_niOl0lO0i20844w(0); + wire_w_lg_niOl0lO0l24161w(0) <= niOl0lO0l AND wire_w_lg_niOl0lO0i24160w(0); + wire_w_lg_niOl0lOii20847w(0) <= niOl0lOii AND wire_w_lg_w_lg_niOl0lO0O20843w20846w(0); + wire_w_lg_niOl0lOii24163w(0) <= niOl0lOii AND wire_w_lg_w_lg_niOl0lO0O20843w24162w(0); + wire_w_lg_niOl0lOll24234w(0) <= niOl0lOll AND n011li0O; + wire_w_lg_niOl0lOll20836w(0) <= niOl0lOll AND niOl0lOli; + wire_w_lg_niOl0lOll24155w(0) <= niOl0lOll AND niOl1ll1l; + wire_w_lg_niOl0lOlO24195w(0) <= niOl0lOlO AND wire_nlOOO0O0O_w_lg_dataout24194w(0); + wire_w_lg_niOl0lOlO24235w(0) <= niOl0lOlO AND wire_w_lg_niOl0lOll24234w(0); + wire_w_lg_niOl0lOlO20837w(0) <= niOl0lOlO AND wire_w_lg_niOl0lOll20836w(0); + wire_w_lg_niOl0lOlO24156w(0) <= niOl0lOlO AND wire_w_lg_niOl0lOll24155w(0); + wire_w_lg_niOl0lOOl20839w(0) <= niOl0lOOl AND wire_w_lg_w_lg_niOl0lOOi20835w20838w(0); + wire_w_lg_niOl0lOOl24158w(0) <= niOl0lOOl AND wire_w_lg_w_lg_niOl0lOOi20835w24157w(0); + wire_w_lg_niOl0O10i24191w(0) <= niOl0O10i AND wire_nlOOO0OiO_w_lg_dataout24190w(0); + wire_w_lg_niOl0O10i24231w(0) <= niOl0O10i AND wire_w_lg_niOl0O11O24230w(0); + wire_w_lg_niOl0O10i20829w(0) <= niOl0O10i AND wire_w_lg_niOl0O11O20828w(0); + wire_w_lg_niOl0O10i24151w(0) <= niOl0O10i AND wire_w_lg_niOl0O11O24150w(0); + wire_w_lg_niOl0O10O20831w(0) <= niOl0O10O AND wire_w_lg_w_lg_niOl0O10l20827w20830w(0); + wire_w_lg_niOl0O10O24153w(0) <= niOl0O10O AND wire_w_lg_w_lg_niOl0O10l20827w24152w(0); + wire_w_lg_niOl0O11O24230w(0) <= niOl0O11O AND n1Oi1O1l; + wire_w_lg_niOl0O11O20828w(0) <= niOl0O11O AND niOl0O11l; + wire_w_lg_niOl0O11O24150w(0) <= niOl0O11O AND niOl1ll1O; + wire_w_lg_niOl0Ol0l24924w(0) <= niOl0Ol0l AND wire_w_lg_niOl1Olli24923w(0); + wire_w_lg_niOl10O0i28350w(0) <= niOl10O0i AND wire_w_lg_niOl1i11O28120w(0); + wire_w_lg_niOl11OOi29015w(0) <= niOl11OOi AND wire_nl1000i_w_lg_w_lg_niOOi1ill29013w29014w(0); + wire_w_lg_niOl1Olli24923w(0) <= niOl1Olli AND n1lillil; + wire_w_lg_niOl1Olli24779w(0) <= niOl1Olli AND niOl0iOOO; + wire_w_lg_niOli0i1O19683w(0) <= niOli0i1O AND wire_w_lg_niOli1lOl19682w(0); + wire_w_lg_niOli101i21149w(0) <= niOli101i AND wire_w_lg_niOl0i10l21148w(0); + wire_w_lg_niOli1iOl21214w(0) <= niOli1iOl AND wire_w_lg_niOl00iOO21213w(0); + wire_w_lg_niOliii0l18289w(0) <= niOliii0l AND n1Oilili; + wire_w_lg_niOliii1l18290w(0) <= niOliii1l AND n1OiliiO; + wire_w_lg_niOliil0l18156w(0) <= niOliil0l AND n1Ol000i; + wire_w_lg_niOlill0i17382w(0) <= niOlill0i AND n01001Ol; + wire_w_lg_niOlill1i17383w(0) <= niOlill1i AND n01001Oi; + wire_w_lg_niOlilO0i17249w(0) <= niOlilO0i AND n010lOil; + wire_w_lg_niOliOlOO16476w(0) <= niOliOlOO AND n01OlO1l; + wire_w_lg_niOliOO1O16475w(0) <= niOliOO1O AND n01OlO1O; + wire_w_lg_niOll001l15435w(0) <= niOll001l AND n00lO01i; + wire_w_lg_niOll011l15568w(0) <= niOll011l AND n00l0iii; + wire_w_lg_niOll111O16342w(0) <= niOll111O AND n0010ilO; + wire_w_lg_niOll1OOl15569w(0) <= niOll1OOl AND n00l0i0O; + wire_w_lg_niOlli01i14661w(0) <= niOlli01i AND n0i0O1ll; + wire_w_lg_niOlli1Oi14662w(0) <= niOlli1Oi AND n0i0O1li; + wire_w_lg_niOllii1i14528w(0) <= niOllii1i AND n0ii0O0l; + wire_w_lg_niOlll0lO13755w(0) <= niOlll0lO AND n0l10lOl; + wire_w_lg_niOlll0OO13754w(0) <= niOlll0OO AND n0l10lOO; + wire_w_lg_niOllliOO13621w(0) <= niOllliOO AND n0l1OiiO; + wire_w_lg_niOllOill12848w(0) <= niOllOill AND n0llOi1O; + wire_w_lg_niOllOiOl12847w(0) <= niOllOiOl AND n0llOi0i; + wire_w_lg_niOllOlOl12714w(0) <= niOllOlOl AND n0lOi1Oi; + wire_w_lg_niOlO1lli11937w(0) <= niOlO1lli AND n0Oii1ii; + wire_w_lg_niOlO1lOi11936w(0) <= niOlO1lOi AND n0Oii1il; + wire_w_lg_niOlO1OOl11803w(0) <= niOlO1OOl AND n0OiOO1l; + wire_w_lg_niOlOOlOl21014w(0) <= niOlOOlOl AND wire_nlOi00l1O_w_lg_w_lg_dataout21012w21013w(0); + wire_w_lg_niOO000ll4355w(0) <= niOO000ll AND wire_nlll0lli_w_q_range4070w(0); + wire_w_lg_niOO000Ol4401w(0) <= niOO000Ol AND wire_w_lg_w_k_hip_range2413w4400w(0); + wire_w_lg_niOO00i1O4326w(0) <= niOO00i1O AND niOO00i1i; + wire_w_lg_niOO00ill4320w(0) <= niOO00ill AND wire_nl1000i_w_lg_w_lg_w_lg_w_lg_n1l000l4315w4317w4318w4319w(0); + wire_w_lg_niOO00ill4312w(0) <= niOO00ill AND wire_nlO0OllO_dataout; + wire_w_lg_niOO00l0i4100w(0) <= niOO00l0i AND nlOili0l; + wire_w_lg_niOO00lli4305w(0) <= niOO00lli AND wire_nlll0lli_w_lg_w_q_range4087w4304w(0); + wire_w_lg_niOO00lll4327w(0) <= niOO00lll AND wire_w_lg_niOO00i1O4326w(0); + wire_w_lg_niOO00llO4041w(0) <= niOO00llO AND wire_nl1000i_w_lg_nlOili0l4040w(0); + wire_w_lg_niOO01i1O5602w(0) <= niOO01i1O AND wire_nl1000i_w_lg_nll0O0iOl5601w(0); + wire_w_lg_niOO01lll5093w(0) <= niOO01lll AND wire_w_lg_niOO01lli5092w(0); + wire_w_lg_niOO01lll5096w(0) <= niOO01lll AND nlliO11i; + wire_w_lg_niOO0i1OO3744w(0) <= niOO0i1OO AND wire_w_lg_niOO00OOO3743w(0); + wire_w_lg_niOO0l00O2566w(0) <= niOO0l00O AND wire_n0OOO0O_w_lg_w_q_range2464w2565w(0); + wire_w_lg_niOO0l01l2477w(0) <= niOO0l01l AND ni1iOOO; + wire_w_lg_niOO10lOl56228w(0) <= niOO10lOl AND wire_nlill0Oll_w_lg_nl1OilO0O56227w(0); + wire_w_lg_niOO10lOO21168w(0) <= niOO10lOO AND wire_w_lg_niOl00OiO21167w(0); + wire_w_lg_niOO10lOO9957w(0) <= niOO10lOO AND wire_niil0i1l_w_lg_w_lg_w_lg_dataout9952w9953w9956w(0); + wire_w_lg_niOO10lOO23473w(0) <= niOO10lOO AND wire_nlOii10ii_w_lg_dataout23472w(0); + wire_w_lg_niOO1OO1l6096w(0) <= niOO1OO1l AND wire_w_lg_niOO1Ol1l6095w(0); + wire_w_lg_tx_valid_vc04037w(0) <= tx_valid_vc0 AND wire_w_lg_niOO00lOO4032w(0); + wire_w_lg_tx_valid_vc04031w(0) <= tx_valid_vc0 AND tx_sop_vc0_0; + wire_w_lg_tx_valid_vc12420w(0) <= tx_valid_vc1 AND wire_w_lg_niOO0l0li2415w(0); + wire_w_lg_tx_valid_vc12414w(0) <= tx_valid_vc1 AND tx_sop_vc1_0; + wire_w_lg_w_ni00O11O10767w10769w(0) <= w_ni00O11O10767w AND wire_niO01ill_w_lg_ni0i1lll10768w(0); + wire_w_lg_w_nl0liO1Oi51818w51819w(0) <= w_nl0liO1Oi51818w AND wire_w_lg_w_lg_niOil0lil51645w51646w(0); + wire_w_lg_w_nl0lO0Oii50931w50932w(0) <= w_nl0lO0Oii50931w AND wire_w_lg_w_lg_niOil1Oli50758w50759w(0); + wire_w_lg_w_nl0O01i1l50047w50048w(0) <= w_nl0O01i1l50047w AND wire_w_lg_w_lg_niOil11lO49874w49875w(0); + wire_w_lg_w_cpl_err_range8533w8538w(0) <= wire_w_cpl_err_range8533w(0) AND wire_w_lg_w_lg_niOO1iiiO8535w8537w(0); + wire_w_lg_w_cpl_err_range8525w8530w(0) <= wire_w_cpl_err_range8525w(0) AND wire_w_lg_w_lg_niOO1iili8527w8529w(0); + wire_w_lg_w_cpl_err_range8517w8522w(0) <= wire_w_cpl_err_range8517w(0) AND wire_w_lg_w_lg_niOO1iill8519w8521w(0); + wire_w_lg_w_cpl_err_range8509w8514w(0) <= wire_w_cpl_err_range8509w(0) AND wire_w_lg_w_lg_niOO1iilO8511w8513w(0); + wire_w_lg_w_k_bar_range45712w51281w(0) <= wire_w_k_bar_range45712w(0) AND niOii000O; + wire_w_lg_w_k_bar_range47794w47796w(0) <= wire_w_k_bar_range47794w(0) AND wire_w_lg_niOiiO10O47795w(0); + wire_w_lg_w_k_bar_range45915w49518w(0) <= wire_w_k_bar_range45915w(0) AND niOiiO1il; + wire_w_lg_w_k_bar_range49299w49515w(0) <= wire_w_k_bar_range49299w(0) AND wire_nlill0Oll_w_lg_nl0O0i10O49514w(0); + wire_w_lg_w_k_bar_range47787w51990w(0) <= wire_w_k_bar_range47787w(0) AND wire_w51989w(0); + wire_w_lg_w_k_bar_range47787w47790w(0) <= wire_w_k_bar_range47787w(0) AND niOiiO1il; + wire_w_lg_w_k_bar_range47783w47785w(0) <= wire_w_k_bar_range47783w(0) AND wire_w_lg_niOiiO1li47784w(0); + wire_w_lg_w_k_bar_range47776w47779w(0) <= wire_w_k_bar_range47776w(0) AND wire_nlill0Oll_w_lg_w_lg_nl01l0O1l47777w47778w(0); + wire_w_lg_w_k_bar_range48482w48483w(0) <= wire_w_k_bar_range48482w(0) AND wire_w_lg_niOili1OO45976w(0); + wire_w_lg_w_k_bar_range48482w48878w(0) <= wire_w_k_bar_range48482w(0) AND wire_w_lg_w_k_bar_range45818w45819w(0); + wire_w_lg_w_k_bar_range45818w48487w(0) <= wire_w_k_bar_range45818w(0) AND wire_w_lg_niOili1OO45976w(0); + wire_w_lg_w_k_bar_range48494w48495w(0) <= wire_w_k_bar_range48494w(0) AND wire_w_lg_niOili1OO45976w(0); + wire_w_lg_w_k_bar_range48494w48609w(0) <= wire_w_k_bar_range48494w(0) AND wire_w_lg_w_k_bar_range45930w45931w(0); + wire_w_lg_w_k_bar_range45930w48491w(0) <= wire_w_k_bar_range45930w(0) AND wire_w_lg_niOili1OO45976w(0); + wire_w_lg_w_k_bar_range51061w51278w(0) <= wire_w_k_bar_range51061w(0) AND wire_nlill0Oll_w_lg_nl0ll1O1l51277w(0); + wire_w_lg_w_k_bar_range51119w51982w(0) <= wire_w_k_bar_range51119w(0) AND wire_w51981w(0); + wire_w_lg_w_k_bar_range51119w51290w(0) <= wire_w_k_bar_range51119w(0) AND niOii000O; + wire_w_lg_w_k_bar_range51117w51286w(0) <= wire_w_k_bar_range51117w(0) AND wire_w_lg_niOii0liO51285w(0); + wire_w_lg_w_k_bar_range45805w50403w(0) <= wire_w_k_bar_range45805w(0) AND niOiiO10i; + wire_w_lg_w_k_bar_range50184w50400w(0) <= wire_w_k_bar_range50184w(0) AND wire_nlill0Oll_w_lg_nl0lOlill50399w(0); + wire_w_lg_w_k_bar_range47798w51986w(0) <= wire_w_k_bar_range47798w(0) AND wire_w51985w(0); + wire_w_lg_w_k_bar_range47798w47801w(0) <= wire_w_k_bar_range47798w(0) AND niOiiO10i; + wire_w_lg_w_k_conf_range46288w48197w(0) <= wire_w_k_conf_range46288w(0) AND wire_nl0l1lO1O_w_lg_w_lg_dataout48195w48196w(0); + wire_w_lg_w_k_conf_range46286w48200w(0) <= wire_w_k_conf_range46286w(0) AND wire_nl0l1lO1O_w_lg_dataout48199w(0); + wire_w_lg_w_k_conf_range44263w44363w(0) <= wire_w_k_conf_range44263w(0) AND wire_w_lg_niOill0OO44360w(0); + wire_w_lg_w_k_conf_range44263w44327w(0) <= wire_w_k_conf_range44263w(0) AND wire_w_lg_niOillliO44326w(0); + wire_w_lg_w_k_conf_range44263w44368w(0) <= wire_w_k_conf_range44263w(0) AND wire_nliiOiilO_w_lg_nliiO100O44367w(0); + wire_w_lg_w_k_conf_range44263w44430w(0) <= wire_w_k_conf_range44263w(0) AND nliiO100O; + wire_w_lg_w_k_conf_range44115w44116w(0) <= wire_w_k_conf_range44115w(0) AND wire_w_lg_niOilOO1i43375w(0); + wire_w_lg_w_k_conf_range43970w43999w(0) <= wire_w_k_conf_range43970w(0) AND wire_nilOO0ii_w_lg_dataout43998w(0); + wire_w_lg_w_k_conf_range43970w43972w(0) <= wire_w_k_conf_range43970w(0) AND wire_nlill0Oll_w_lg_nli1il10l43971w(0); + wire_w_lg_w_k_conf_range44000w44004w(0) <= wire_w_k_conf_range44000w(0) AND wire_nilOO0ii_w_lg_dataout44003w(0); + wire_w_lg_w_k_conf_range47998w47999w(0) <= wire_w_k_conf_range47998w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range48000w48001w(0) <= wire_w_k_conf_range48000w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range48002w48003w(0) <= wire_w_k_conf_range48002w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range48004w48005w(0) <= wire_w_k_conf_range48004w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range48006w48007w(0) <= wire_w_k_conf_range48006w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range48008w48009w(0) <= wire_w_k_conf_range48008w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range48010w48011w(0) <= wire_w_k_conf_range48010w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range48012w48013w(0) <= wire_w_k_conf_range48012w(0) AND wire_w_lg_niOiilOlO47917w(0); + wire_w_lg_w_k_conf_range29168w29457w(0) <= wire_w_k_conf_range29168w(0) AND wire_w_lg_niOl11l1i29456w(0); + wire_w_lg_w_k_conf_range29168w29169w(0) <= wire_w_k_conf_range29168w(0) AND nlO0OlOii; + wire_w_lg_w_k_conf_range1869w51903w(0) <= wire_w_k_conf_range1869w(0) AND niOili01O; + wire_w_lg_w_k_conf_range1869w46275w(0) <= wire_w_k_conf_range1869w(0) AND nl0iOiOlO; + wire_w_lg_w_k_conf_range46162w51908w(0) <= wire_w_k_conf_range46162w(0) AND wire_w_lg_niOili01O51907w(0); + wire_w_lg_w_k_conf_range46162w51900w(0) <= wire_w_k_conf_range46162w(0) AND wire_nlill0Oll_w_lg_nl0iOil1O51899w(0); + wire_w_lg_w_k_conf_range46162w51902w(0) <= wire_w_k_conf_range46162w(0) AND wire_nlill0Oll_w_lg_nl0iOiOli51901w(0); + wire_w_lg_w_k_conf_range46162w51905w(0) <= wire_w_k_conf_range46162w(0) AND wire_nlill0Oll_w_lg_nl0iOiOll51904w(0); + wire_w_lg_w_k_conf_range46162w51958w(0) <= wire_w_k_conf_range46162w(0) AND niOili0ii; + wire_w_lg_w_k_conf_range46175w51978w(0) <= wire_w_k_conf_range46175w(0) AND wire_w_lg_w_k_conf_range46173w46174w(0); + wire_w_lg_w_k_conf_range46194w51896w(0) <= wire_w_k_conf_range46194w(0) AND wire_nlill0Oll_w_lg_nl0iOil0i51895w(0); + wire_w_lg_w_k_conf_range24588w24591w(0) <= wire_w_k_conf_range24588w(0) AND wire_niO01ill_w_lg_nlOO1O1Ol24590w(0); + wire_w_lg_w_k_conf_range24588w24630w(0) <= wire_w_k_conf_range24588w(0) AND niOl1iOOi; + wire_w_lg_w_k_dev_range52044w52499w(0) <= wire_w_k_dev_range52044w(0) AND wire_w_lg_w_k_dev_range52047w52497w(0); + wire_w_lg_w_k_gbl_hip_range28022w28028w(0) <= wire_w_k_gbl_hip_range28022w(0) AND wire_nlOl1l0OO_w_lg_dataout28027w(0); + wire_w_lg_w_k_gbl_hip_range28022w28025w(0) <= wire_w_k_gbl_hip_range28022w(0) AND nlOl1li0l; + wire_w_lg_w_k_gbl_hip_range28020w28029w(0) <= wire_w_k_gbl_hip_range28020w(0) AND wire_w_lg_w_k_gbl_hip_range28022w28028w(0); + wire_w_lg_w_k_gbl_hip_range54181w54184w(0) <= wire_w_k_gbl_hip_range54181w(0) AND wire_nl011Ol1l_w_lg_dataout54183w(0); + wire_w_lg_w_k_gbl_hip_range54181w54216w(0) <= wire_w_k_gbl_hip_range54181w(0) AND wire_nl011Ol1O_w_lg_dataout54215w(0); + wire_w_lg_w_k_gbl_hip_range54181w54586w(0) <= wire_w_k_gbl_hip_range54181w(0) AND wire_nlill0Oll_w_lg_nl1OO010i8963w(0); + wire_w_lg_w_k_gbl_hip_range54181w54855w(0) <= wire_w_k_gbl_hip_range54181w(0) AND nl1OO010i; + wire_w_lg_w_k_gbl_hip_range55029w55039w(0) <= wire_w_k_gbl_hip_range55029w(0) AND wire_nlill0Oll_w_lg_nl1Ol1l0l55038w(0); + wire_w_lg_w_k_gbl_hip_range55029w55032w(0) <= wire_w_k_gbl_hip_range55029w(0) AND wire_nlill0Oll_w_lg_nl1Ol1l0l55031w(0); + wire_w_lg_w_k_gbl_hip_range25479w25493w(0) <= wire_w_k_gbl_hip_range25479w(0) AND wire_w_lg_w_k_gbl_hip_range25481w25482w(0); + wire_w_lg_w_k_gbl_hip_range2434w35935w(0) <= wire_w_k_gbl_hip_range2434w(0) AND wire_nl1000i_w_lg_w_lg_nlli0illi35932w35934w(0); + wire_w_lg_w_k_gbl_hip_range2434w59722w(0) <= wire_w_k_gbl_hip_range2434w(0) AND nlOili1O; + wire_w_lg_w_k_gbl_hip_range1050w3435w(0) <= wire_w_k_gbl_hip_range1050w(0) AND wire_w_lg_w_k_hip_range2413w2429w(0); + wire_w_lg_w_k_gbl_hip_range9015w9022w(0) <= wire_w_k_gbl_hip_range9015w(0) AND wire_nlOi0iiiO_w_lg_w_lg_w_lg_w_lg_dataout9016w9018w9019w9021w(0); + wire_w_lg_w_k_hip_range2413w3817w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni01lOi_w3816w(0); + wire_w_lg_w_k_hip_range2413w2813w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w2812w(0); + wire_w_lg_w_k_hip_range2413w6169w(0) <= wire_w_k_hip_range2413w(0) AND wire_niOOO0O_w6168w(0); + wire_w_lg_w_k_hip_range2413w4666w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w4665w(0); + wire_w_lg_w_k_hip_range2413w4077w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_w_lg_n1l01ii4073w4076w(0); + wire_w_lg_w_k_hip_range2413w2455w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_w_lg_ni1lllO2451w2454w(0); + wire_w_lg_w_k_hip_range2413w4034w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_tx_valid_vc04031w4033w(0); + wire_w_lg_w_k_hip_range2413w2417w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_tx_valid_vc12414w2416w(0); + wire_w_lg_w_k_hip_range2413w4342w(0) <= wire_w_k_hip_range2413w(0) AND wire_nlO0Oill_w_lg_w_lg_dataout4340w4341w(0); + wire_w_lg_w_k_hip_range2413w4049w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_niOO00llO4046w4048w(0); + wire_w_lg_w_k_hip_range2413w5661w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_w_lg_nll0O0iOl5342w5660w(0); + wire_w_lg_w_k_hip_range2413w3416w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3415w(0); + wire_w_lg_w_k_hip_range2413w3418w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3417w(0); + wire_w_lg_w_k_hip_range2413w5730w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5729w(0); + wire_w_lg_w_k_hip_range2413w5732w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5731w(0); + wire_w_lg_w_k_hip_range2413w3420w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w3419w(0); + wire_w_lg_w_k_hip_range2413w5734w(0) <= wire_w_k_hip_range2413w(0) AND wire_w_lg_w_lg_w_k_gbl_hip_range1050w1051w5733w(0); + wire_w_lg_w_k_hip_range2413w3343w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_n0Oii1O3342w(0); + wire_w_lg_w_k_hip_range2413w3409w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1llii_w_lg_n0Oli1i3408w(0); + wire_w_lg_w_k_hip_range2413w4081w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_n1l011i4080w(0); + wire_w_lg_w_k_hip_range2413w4079w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_n1l01ii4078w(0); + wire_w_lg_w_k_hip_range2413w2459w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_ni1ll0l2458w(0); + wire_w_lg_w_k_hip_range2413w2457w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_ni1lllO2456w(0); + wire_w_lg_w_k_hip_range2413w5610w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_nll0Oiii5609w(0); + wire_w_lg_w_k_hip_range2413w5724w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl11llO_w_lg_nlliO01l5723w(0); + wire_w_lg_w_k_hip_range2413w3330w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_n0Ol11l3329w(0); + wire_w_lg_w_k_hip_range2413w4061w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_n1l000O4060w(0); + wire_w_lg_w_k_hip_range2413w2424w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_ni1lliO2423w(0); + wire_w_lg_w_k_hip_range2413w2438w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_ni1lOll2437w(0); + wire_w_lg_w_k_hip_range2413w6420w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_nl0OiO0O6419w(0); + wire_w_lg_w_k_hip_range2413w5220w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_nllilO1l5219w(0); + wire_w_lg_w_k_hip_range2413w3383w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1lOlO_w_lg_w_lg_w_lg_n0Oii0l3379w3380w3382w(0); + wire_w_lg_w_k_hip_range2413w5653w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_w_lg_w_lg_nll0OiiO5649w5650w5652w(0); + wire_w_lg_w_k_hip_range2413w3432w(0) <= wire_w_k_hip_range2413w(0) AND wire_ni1llii_w_lg_w_lg_n0Oli1i3428w3431w(0); + wire_w_lg_w_k_hip_range2413w4400w(0) <= wire_w_k_hip_range2413w(0) AND wire_nlll0lli_w_lg_w_lg_w_q_range4070w4398w4399w(0); + wire_w_lg_w_k_hip_range2413w5340w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w5339w(0); + wire_w_lg_w_k_hip_range2413w5753w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nlliO01l5740w5745w5748w5752w(0); + wire_w_lg_w_k_hip_range2413w5680w(0) <= wire_w_k_hip_range2413w(0) AND wire_nl1000i_w_lg_nll0Oili5679w(0); + wire_w_lg_w_k_hip_range2413w3337w(0) <= wire_w_k_hip_range2413w(0) AND n0Oii0i; + wire_w_lg_w_k_hip_range2413w3338w(0) <= wire_w_k_hip_range2413w(0) AND n0Oii0O; + wire_w_lg_w_k_hip_range2413w5663w(0) <= wire_w_k_hip_range2413w(0) AND niOO010Ol; + wire_w_lg_w_k_hip_range2413w5612w(0) <= wire_w_k_hip_range2413w(0) AND niOO01i1O; + wire_w_lg_w_k_hip_range2413w5604w(0) <= wire_w_k_hip_range2413w(0) AND nll0Oiil; + wire_w_lg_w_k_hip_range2413w5606w(0) <= wire_w_k_hip_range2413w(0) AND nll0Oili; + wire_w_lg_w_mode_range8895w9840w(0) <= wire_w_mode_range8895w(0) AND wire_w_lg_w_mode_range8897w9838w(0); + wire_w_lg_w_test_in_hip_range61746w61749w(0) <= wire_w_test_in_hip_range61746w(0) AND wire_w_lg_w_test_in_hip_range61747w61748w(0); + wire_w_lg_w_test_in_hip_range61715w61726w(0) <= wire_w_test_in_hip_range61715w(0) AND wire_w_lg_w_test_in_hip_range61717w61725w(0); + wire_w_lg_w4018w4019w(0) <= NOT wire_w4018w(0); + wire_w_lg_w2400w2401w(0) <= NOT wire_w2400w(0); + wire_w51989w(0) <= NOT wire_w_lg_w_lg_w_k_bar_range45913w45914w49643w(0); + wire_w51981w(0) <= NOT wire_w_lg_w_lg_w_k_bar_range45710w45711w51414w(0); + wire_w51985w(0) <= NOT wire_w_lg_w_lg_w_k_bar_range45803w45804w50527w(0); + wire_w_lg_w_lg_niOilllOl45264w45265w(0) <= NOT wire_w_lg_niOilllOl45264w(0); + wire_w_lg_w_lg_niOil0lil51645w51646w(0) <= NOT wire_w_lg_niOil0lil51645w(0); + wire_w_lg_w_lg_niOil11lO49874w49875w(0) <= NOT wire_w_lg_niOil11lO49874w(0); + wire_w_lg_w_lg_niOil1Oli50758w50759w(0) <= NOT wire_w_lg_niOil1Oli50758w(0); + wire_w_lg_w_lg_niOl10l1O28513w28514w(0) <= NOT wire_w_lg_niOl10l1O28513w(0); + wire_w_lg_w_lg_niOl10O0l28328w28329w(0) <= NOT wire_w_lg_niOl10O0l28328w(0); + wire_w_lg_niOi0001l53584w(0) <= NOT niOi0001l; + wire_w_lg_niOi000li53454w(0) <= NOT niOi000li; + wire_w_lg_niOi000lO53415w(0) <= NOT niOi000lO; + wire_w_lg_niOi0010i53645w(0) <= NOT niOi0010i; + wire_w_lg_niOi0010l53612w(0) <= NOT niOi0010l; + wire_w_lg_niOi001il53581w(0) <= NOT niOi001il; + wire_w_lg_niOi001iO53573w(0) <= NOT niOi001iO; + wire_w_lg_niOi001li54067w(0) <= NOT niOi001li; + wire_w_lg_niOi001OO53534w(0) <= NOT niOi001OO; + wire_w_lg_niOi00lii53229w(0) <= NOT niOi00lii; + wire_w_lg_niOi00lil53626w(0) <= NOT niOi00lil; + wire_w_lg_niOi00liO53634w(0) <= NOT niOi00liO; + wire_w_lg_niOi00O0i53602w(0) <= NOT niOi00O0i; + wire_w_lg_niOi00O0l53601w(0) <= NOT niOi00O0l; + wire_w_lg_niOi00O0O53607w(0) <= NOT niOi00O0O; + wire_w_lg_niOi00O1O53628w(0) <= NOT niOi00O1O; + wire_w_lg_niOi00Oii53609w(0) <= NOT niOi00Oii; + wire_w_lg_niOi00Oil53600w(0) <= NOT niOi00Oil; + wire_w_lg_niOi00Oli53198w(0) <= NOT niOi00Oli; + wire_w_lg_niOi00OOO53182w(0) <= NOT niOi00OOO; + wire_w_lg_niOi0101i54853w(0) <= NOT niOi0101i; + wire_w_lg_niOi0110O54834w(0) <= NOT niOi0110O; + wire_w_lg_niOi011Oi54831w(0) <= NOT niOi011Oi; + wire_w_lg_niOi011OO54520w(0) <= NOT niOi011OO; + wire_w_lg_niOi01i0l54724w(0) <= NOT niOi01i0l; + wire_w_lg_niOi01i0O54209w(0) <= NOT niOi01i0O; + wire_w_lg_niOi01i1l54196w(0) <= NOT niOi01i1l; + wire_w_lg_niOi01l1l54090w(0) <= NOT niOi01l1l; + wire_w_lg_niOi01lli54052w(0) <= NOT niOi01lli; + wire_w_lg_niOi01lll54217w(0) <= NOT niOi01lll; + wire_w_lg_niOi01Oll54001w(0) <= NOT niOi01Oll; + wire_w_lg_niOi0i11l53116w(0) <= NOT niOi0i11l; + wire_w_lg_niOi0lO0O52760w(0) <= NOT niOi0lO0O; + wire_w_lg_niOi0lOil52614w(0) <= NOT niOi0lOil; + wire_w_lg_niOi0lOli53605w(0) <= NOT niOi0lOli; + wire_w_lg_niOi0lOll53190w(0) <= NOT niOi0lOll; + wire_w_lg_niOi0lOOi53212w(0) <= NOT niOi0lOOi; + wire_w_lg_niOi0lOOl53453w(0) <= NOT niOi0lOOl; + wire_w_lg_niOi0O00i52177w(0) <= NOT niOi0O00i; + wire_w_lg_niOi0O01i52553w(0) <= NOT niOi0O01i; + wire_w_lg_niOi0O01l52176w(0) <= NOT niOi0O01l; + wire_w_lg_niOi0O11i52280w(0) <= NOT niOi0O11i; + wire_w_lg_niOi0O11l52275w(0) <= NOT niOi0O11l; + wire_w_lg_niOi0O1ii52250w(0) <= NOT niOi0O1ii; + wire_w_lg_niOi0O1iO52247w(0) <= NOT niOi0O1iO; + wire_w_lg_niOi0O1ll52243w(0) <= NOT niOi0O1ll; + wire_w_lg_niOi0O1lO52249w(0) <= NOT niOi0O1lO; + wire_w_lg_niOi0Oi0O52137w(0) <= NOT niOi0Oi0O; + wire_w_lg_niOi0Oi1l52159w(0) <= NOT niOi0Oi1l; + wire_w_lg_niOi0Oiii52517w(0) <= NOT niOi0Oiii; + wire_w_lg_niOi0Oili52124w(0) <= NOT niOi0Oili; + wire_w_lg_niOi0Oill52127w(0) <= NOT niOi0Oill; + wire_w_lg_niOi0OilO52128w(0) <= NOT niOi0OilO; + wire_w_lg_niOi0Olii52139w(0) <= NOT niOi0Olii; + wire_w_lg_niOi0OliO52105w(0) <= NOT niOi0OliO; + wire_w_lg_niOi0Olli52103w(0) <= NOT niOi0Olli; + wire_w_lg_niOi10i1i61548w(0) <= NOT niOi10i1i; + wire_w_lg_niOi10i1l60239w(0) <= NOT niOi10i1l; + wire_w_lg_niOi10iil60170w(0) <= NOT niOi10iil; + wire_w_lg_niOi10iiO60253w(0) <= NOT niOi10iiO; + wire_w_lg_niOi10ill59981w(0) <= NOT niOi10ill; + wire_w_lg_niOi10iOi60173w(0) <= NOT niOi10iOi; + wire_w_lg_niOi10iOO59973w(0) <= NOT niOi10iOO; + wire_w_lg_niOi10l0i60003w(0) <= NOT niOi10l0i; + wire_w_lg_niOi10l0O60193w(0) <= NOT niOi10l0O; + wire_w_lg_niOi10lOl59979w(0) <= NOT niOi10lOl; + wire_w_lg_niOi10lOO59856w(0) <= NOT niOi10lOO; + wire_w_lg_niOi10O0i59855w(0) <= NOT niOi10O0i; + wire_w_lg_niOi10OlO61533w(0) <= NOT niOi10OlO; + wire_w_lg_niOi11ilO61846w(0) <= NOT niOi11ilO; + wire_w_lg_niOi11iOi61838w(0) <= NOT niOi11iOi; + wire_w_lg_niOi11iOO61783w(0) <= NOT niOi11iOO; + wire_w_lg_niOi11l1i61765w(0) <= NOT niOi11l1i; + wire_w_lg_niOi11O0l61544w(0) <= NOT niOi11O0l; + wire_w_lg_niOi11O0O61539w(0) <= NOT niOi11O0O; + wire_w_lg_niOi11Oii61529w(0) <= NOT niOi11Oii; + wire_w_lg_niOi11Oil61526w(0) <= NOT niOi11Oil; + wire_w_lg_niOi11Oli61464w(0) <= NOT niOi11Oli; + wire_w_lg_niOi11OlO61462w(0) <= NOT niOi11OlO; + wire_w_lg_niOi1i00l59715w(0) <= NOT niOi1i00l; + wire_w_lg_niOi1i00O59724w(0) <= NOT niOi1i00O; + wire_w_lg_niOi1i0Oi58933w(0) <= NOT niOi1i0Oi; + wire_w_lg_niOi1i0Ol58929w(0) <= NOT niOi1i0Ol; + wire_w_lg_niOi1i0OO58925w(0) <= NOT niOi1i0OO; + wire_w_lg_niOi1i10O59857w(0) <= NOT niOi1i10O; + wire_w_lg_niOi1i1Ol60233w(0) <= NOT niOi1i1Ol; + wire_w_lg_niOi1i1OO60237w(0) <= NOT niOi1i1OO; + wire_w_lg_niOi1ii0i58907w(0) <= NOT niOi1ii0i; + wire_w_lg_niOi1ii1O58911w(0) <= NOT niOi1ii1O; + wire_w_lg_niOi1iiii58803w(0) <= NOT niOi1iiii; + wire_w_lg_niOi1iiil58799w(0) <= NOT niOi1iiil; + wire_w_lg_niOi1iill58695w(0) <= NOT niOi1iill; + wire_w_lg_niOi1iilO58692w(0) <= NOT niOi1iilO; + wire_w_lg_niOi1illO57815w(0) <= NOT niOi1illO; + wire_w_lg_niOi1ilOl57737w(0) <= NOT niOi1ilOl; + wire_w_lg_niOi1li1l56196w(0) <= NOT niOi1li1l; + wire_w_lg_niOi1ll1i56068w(0) <= NOT niOi1ll1i; + wire_w_lg_niOi1llll55853w(0) <= NOT niOi1llll; + wire_w_lg_niOi1lO0l55827w(0) <= NOT niOi1lO0l; + wire_w_lg_niOi1lO0O55569w(0) <= NOT niOi1lO0O; + wire_w_lg_niOi1lOil55566w(0) <= NOT niOi1lOil; + wire_w_lg_niOi1lOll55514w(0) <= NOT niOi1lOll; + wire_w_lg_niOi1O0li55222w(0) <= NOT niOi1O0li; + wire_w_lg_niOi1O0Oi55215w(0) <= NOT niOi1O0Oi; + wire_w_lg_niOi1O0Ol55208w(0) <= NOT niOi1O0Ol; + wire_w_lg_niOi1O0OO55207w(0) <= NOT niOi1O0OO; + wire_w_lg_niOi1O11i55413w(0) <= NOT niOi1O11i; + wire_w_lg_niOi1O1li56089w(0) <= NOT niOi1O1li; + wire_w_lg_niOi1Oi0O55062w(0) <= NOT niOi1Oi0O; + wire_w_lg_niOi1Oi1O55066w(0) <= NOT niOi1Oi1O; + wire_w_lg_niOi1Oiil55040w(0) <= NOT niOi1Oiil; + wire_w_lg_niOi1Ol0i55828w(0) <= NOT niOi1Ol0i; + wire_w_lg_niOi1Ol1i54886w(0) <= NOT niOi1Ol1i; + wire_w_lg_niOi1OllO54888w(0) <= NOT niOi1OllO; + wire_w_lg_niOi1OlOi56853w(0) <= NOT niOi1OlOi; + wire_w_lg_niOi1OOOi54859w(0) <= NOT niOi1OOOi; + wire_w_lg_niOi1OOOl54858w(0) <= NOT niOi1OOOl; + wire_w_lg_niOii000i53801w(0) <= NOT niOii000i; + wire_w_lg_niOii01il51966w(0) <= NOT niOii01il; + wire_w_lg_niOii0lil51127w(0) <= NOT niOii0lil; + wire_w_lg_niOii0liO51285w(0) <= NOT niOii0liO; + wire_w_lg_niOii0O0O53809w(0) <= NOT niOii0O0O; + wire_w_lg_niOii1liO52084w(0) <= NOT niOii1liO; + wire_w_lg_niOii1Oll52063w(0) <= NOT niOii1Oll; + wire_w_lg_niOii1OOi52160w(0) <= NOT niOii1OOi; + wire_w_lg_niOii1OOl52072w(0) <= NOT niOii1OOl; + wire_w_lg_niOii1OOO52111w(0) <= NOT niOii1OOO; + wire_w_lg_niOiii0ii50248w(0) <= NOT niOiii0ii; + wire_w_lg_niOiiii0i53818w(0) <= NOT niOiiii0i; + wire_w_lg_niOiiiO0l49363w(0) <= NOT niOiiiO0l; + wire_w_lg_niOiil0iO48178w(0) <= NOT niOiil0iO; + wire_w_lg_niOiiliOi48102w(0) <= NOT niOiiliOi; + wire_w_lg_niOiilO1i48030w(0) <= NOT niOiilO1i; + wire_w_lg_niOiilOlO47917w(0) <= NOT niOiilOlO; + wire_w_lg_niOiiO00O47763w(0) <= NOT niOiiO00O; + wire_w_lg_niOiiO0ii47746w(0) <= NOT niOiiO0ii; + wire_w_lg_niOiiO0il47745w(0) <= NOT niOiiO0il; + wire_w_lg_niOiiO0Oi47735w(0) <= NOT niOiiO0Oi; + wire_w_lg_niOiiO0Ol47734w(0) <= NOT niOiiO0Ol; + wire_w_lg_niOiiO10O47795w(0) <= NOT niOiiO10O; + wire_w_lg_niOiiO11l47838w(0) <= NOT niOiiO11l; + wire_w_lg_niOiiO11O47846w(0) <= NOT niOiiO11O; + wire_w_lg_niOiiO1li47784w(0) <= NOT niOiiO1li; + wire_w_lg_niOiiOi0i46473w(0) <= NOT niOiiOi0i; + wire_w_lg_niOiiOi0l46472w(0) <= NOT niOiiOi0l; + wire_w_lg_niOiiOi0O46459w(0) <= NOT niOiiOi0O; + wire_w_lg_niOiiOi1i46476w(0) <= NOT niOiiOi1i; + wire_w_lg_niOiiOi1l46475w(0) <= NOT niOiiOi1l; + wire_w_lg_niOiiOi1O46474w(0) <= NOT niOiiOi1O; + wire_w_lg_niOiiOiii46324w(0) <= NOT niOiiOiii; + wire_w_lg_niOiiOiOi46161w(0) <= NOT niOiiOiOi; + wire_w_lg_niOiiOiOl46160w(0) <= NOT niOiiOiOl; + wire_w_lg_niOiiOiOO46159w(0) <= NOT niOiiOiOO; + wire_w_lg_niOiiOl0i46155w(0) <= NOT niOiiOl0i; + wire_w_lg_niOiiOl0l46154w(0) <= NOT niOiiOl0l; + wire_w_lg_niOiiOl0O46153w(0) <= NOT niOiiOl0O; + wire_w_lg_niOiiOl1i46158w(0) <= NOT niOiiOl1i; + wire_w_lg_niOiiOl1l46157w(0) <= NOT niOiiOl1l; + wire_w_lg_niOiiOl1O46156w(0) <= NOT niOiiOl1O; + wire_w_lg_niOiiOlii46152w(0) <= NOT niOiiOlii; + wire_w_lg_niOiiOlil46151w(0) <= NOT niOiiOlil; + wire_w_lg_niOiiOliO46150w(0) <= NOT niOiiOliO; + wire_w_lg_niOiiOlli46149w(0) <= NOT niOiiOlli; + wire_w_lg_niOiiOlll46148w(0) <= NOT niOiiOlll; + wire_w_lg_niOiiOllO46147w(0) <= NOT niOiiOllO; + wire_w_lg_niOiiOlOi46146w(0) <= NOT niOiiOlOi; + wire_w_lg_niOiiOlOl46145w(0) <= NOT niOiiOlOl; + wire_w_lg_niOiiOlOO46144w(0) <= NOT niOiiOlOO; + wire_w_lg_niOiiOO0i46140w(0) <= NOT niOiiOO0i; + wire_w_lg_niOiiOO1i46143w(0) <= NOT niOiiOO1i; + wire_w_lg_niOiiOO1l46142w(0) <= NOT niOiiOO1l; + wire_w_lg_niOiiOO1O46141w(0) <= NOT niOiiOO1O; + wire_w_lg_niOiiOOil45971w(0) <= NOT niOiiOOil; + wire_w_lg_niOiiOOiO45970w(0) <= NOT niOiiOOiO; + wire_w_lg_niOiiOOli45969w(0) <= NOT niOiiOOli; + wire_w_lg_niOiiOOll45968w(0) <= NOT niOiiOOll; + wire_w_lg_niOiiOOlO45967w(0) <= NOT niOiiOOlO; + wire_w_lg_niOiiOOOi45966w(0) <= NOT niOiiOOOi; + wire_w_lg_niOiiOOOl45965w(0) <= NOT niOiiOOOl; + wire_w_lg_niOiiOOOO45964w(0) <= NOT niOiiOOOO; + wire_w_lg_niOil000i45784w(0) <= NOT niOil000i; + wire_w_lg_niOil000l45783w(0) <= NOT niOil000l; + wire_w_lg_niOil000O45782w(0) <= NOT niOil000O; + wire_w_lg_niOil001i45787w(0) <= NOT niOil001i; + wire_w_lg_niOil001l45786w(0) <= NOT niOil001l; + wire_w_lg_niOil001O45785w(0) <= NOT niOil001O; + wire_w_lg_niOil00ii45781w(0) <= NOT niOil00ii; + wire_w_lg_niOil00il45780w(0) <= NOT niOil00il; + wire_w_lg_niOil00iO45779w(0) <= NOT niOil00iO; + wire_w_lg_niOil00li45778w(0) <= NOT niOil00li; + wire_w_lg_niOil00ll45777w(0) <= NOT niOil00ll; + wire_w_lg_niOil00lO45776w(0) <= NOT niOil00lO; + wire_w_lg_niOil00Oi45775w(0) <= NOT niOil00Oi; + wire_w_lg_niOil00Ol45774w(0) <= NOT niOil00Ol; + wire_w_lg_niOil00OO45773w(0) <= NOT niOil00OO; + wire_w_lg_niOil010l45798w(0) <= NOT niOil010l; + wire_w_lg_niOil010O45797w(0) <= NOT niOil010O; + wire_w_lg_niOil011i45826w(0) <= NOT niOil011i; + wire_w_lg_niOil011l45825w(0) <= NOT niOil011l; + wire_w_lg_niOil011O45824w(0) <= NOT niOil011O; + wire_w_lg_niOil01ii45796w(0) <= NOT niOil01ii; + wire_w_lg_niOil01il45795w(0) <= NOT niOil01il; + wire_w_lg_niOil01iO45794w(0) <= NOT niOil01iO; + wire_w_lg_niOil01li45793w(0) <= NOT niOil01li; + wire_w_lg_niOil01ll45792w(0) <= NOT niOil01ll; + wire_w_lg_niOil01lO45791w(0) <= NOT niOil01lO; + wire_w_lg_niOil01Oi45790w(0) <= NOT niOil01Oi; + wire_w_lg_niOil01Ol45789w(0) <= NOT niOil01Ol; + wire_w_lg_niOil01OO45788w(0) <= NOT niOil01OO; + wire_w_lg_niOil0i0i45741w(0) <= NOT niOil0i0i; + wire_w_lg_niOil0i0l45740w(0) <= NOT niOil0i0l; + wire_w_lg_niOil0i0O45739w(0) <= NOT niOil0i0O; + wire_w_lg_niOil0i1i45772w(0) <= NOT niOil0i1i; + wire_w_lg_niOil0i1l45771w(0) <= NOT niOil0i1l; + wire_w_lg_niOil0iii45738w(0) <= NOT niOil0iii; + wire_w_lg_niOil0iil45737w(0) <= NOT niOil0iil; + wire_w_lg_niOil0iiO45736w(0) <= NOT niOil0iiO; + wire_w_lg_niOil0ili45735w(0) <= NOT niOil0ili; + wire_w_lg_niOil0ill45734w(0) <= NOT niOil0ill; + wire_w_lg_niOil0ilO45733w(0) <= NOT niOil0ilO; + wire_w_lg_niOil0iOi45732w(0) <= NOT niOil0iOi; + wire_w_lg_niOil0iOl45731w(0) <= NOT niOil0iOl; + wire_w_lg_niOil0iOO45730w(0) <= NOT niOil0iOO; + wire_w_lg_niOil0l0i45726w(0) <= NOT niOil0l0i; + wire_w_lg_niOil0l0l45725w(0) <= NOT niOil0l0l; + wire_w_lg_niOil0l0O45724w(0) <= NOT niOil0l0O; + wire_w_lg_niOil0l1i45729w(0) <= NOT niOil0l1i; + wire_w_lg_niOil0l1l45728w(0) <= NOT niOil0l1l; + wire_w_lg_niOil0l1O45727w(0) <= NOT niOil0l1O; + wire_w_lg_niOil0lii45723w(0) <= NOT niOil0lii; + wire_w_lg_niOil0lil45722w(0) <= NOT niOil0lil; + wire_w_lg_niOil0liO45721w(0) <= NOT niOil0liO; + wire_w_lg_niOil0lli45720w(0) <= NOT niOil0lli; + wire_w_lg_niOil0lll45719w(0) <= NOT niOil0lll; + wire_w_lg_niOil0llO45718w(0) <= NOT niOil0llO; + wire_w_lg_niOil0lOi45717w(0) <= NOT niOil0lOi; + wire_w_lg_niOil0lOl45716w(0) <= NOT niOil0lOl; + wire_w_lg_niOil0lOO45715w(0) <= NOT niOil0lOO; + wire_w_lg_niOil0O0i45703w(0) <= NOT niOil0O0i; + wire_w_lg_niOil0O0l45702w(0) <= NOT niOil0O0l; + wire_w_lg_niOil0O0O45701w(0) <= NOT niOil0O0O; + wire_w_lg_niOil0O1i45714w(0) <= NOT niOil0O1i; + wire_w_lg_niOil0O1l45705w(0) <= NOT niOil0O1l; + wire_w_lg_niOil0O1O45704w(0) <= NOT niOil0O1O; + wire_w_lg_niOil0Oii45700w(0) <= NOT niOil0Oii; + wire_w_lg_niOil0Oil45699w(0) <= NOT niOil0Oil; + wire_w_lg_niOil0OiO45698w(0) <= NOT niOil0OiO; + wire_w_lg_niOil0Oli45697w(0) <= NOT niOil0Oli; + wire_w_lg_niOil0Oll45696w(0) <= NOT niOil0Oll; + wire_w_lg_niOil0OlO45695w(0) <= NOT niOil0OlO; + wire_w_lg_niOil0OOi45694w(0) <= NOT niOil0OOi; + wire_w_lg_niOil0OOl45693w(0) <= NOT niOil0OOl; + wire_w_lg_niOil0OOO45692w(0) <= NOT niOil0OOO; + wire_w_lg_niOil100i45945w(0) <= NOT niOil100i; + wire_w_lg_niOil100l45944w(0) <= NOT niOil100l; + wire_w_lg_niOil101i45948w(0) <= NOT niOil101i; + wire_w_lg_niOil101l45947w(0) <= NOT niOil101l; + wire_w_lg_niOil101O45946w(0) <= NOT niOil101O; + wire_w_lg_niOil10ii45908w(0) <= NOT niOil10ii; + wire_w_lg_niOil10il45907w(0) <= NOT niOil10il; + wire_w_lg_niOil10iO45906w(0) <= NOT niOil10iO; + wire_w_lg_niOil10li45905w(0) <= NOT niOil10li; + wire_w_lg_niOil10ll45904w(0) <= NOT niOil10ll; + wire_w_lg_niOil10lO45903w(0) <= NOT niOil10lO; + wire_w_lg_niOil10Oi45902w(0) <= NOT niOil10Oi; + wire_w_lg_niOil10Ol45901w(0) <= NOT niOil10Ol; + wire_w_lg_niOil10OO45900w(0) <= NOT niOil10OO; + wire_w_lg_niOil110i45960w(0) <= NOT niOil110i; + wire_w_lg_niOil110l45959w(0) <= NOT niOil110l; + wire_w_lg_niOil110O45958w(0) <= NOT niOil110O; + wire_w_lg_niOil111i45963w(0) <= NOT niOil111i; + wire_w_lg_niOil111l45962w(0) <= NOT niOil111l; + wire_w_lg_niOil111O45961w(0) <= NOT niOil111O; + wire_w_lg_niOil11ii45957w(0) <= NOT niOil11ii; + wire_w_lg_niOil11il45956w(0) <= NOT niOil11il; + wire_w_lg_niOil11iO45955w(0) <= NOT niOil11iO; + wire_w_lg_niOil11li45954w(0) <= NOT niOil11li; + wire_w_lg_niOil11ll45953w(0) <= NOT niOil11ll; + wire_w_lg_niOil11lO45952w(0) <= NOT niOil11lO; + wire_w_lg_niOil11Oi45951w(0) <= NOT niOil11Oi; + wire_w_lg_niOil11Ol45950w(0) <= NOT niOil11Ol; + wire_w_lg_niOil11OO45949w(0) <= NOT niOil11OO; + wire_w_lg_niOil1i0i45896w(0) <= NOT niOil1i0i; + wire_w_lg_niOil1i0l45895w(0) <= NOT niOil1i0l; + wire_w_lg_niOil1i0O45894w(0) <= NOT niOil1i0O; + wire_w_lg_niOil1i1i45899w(0) <= NOT niOil1i1i; + wire_w_lg_niOil1i1l45898w(0) <= NOT niOil1i1l; + wire_w_lg_niOil1i1O45897w(0) <= NOT niOil1i1O; + wire_w_lg_niOil1iii45893w(0) <= NOT niOil1iii; + wire_w_lg_niOil1iil45892w(0) <= NOT niOil1iil; + wire_w_lg_niOil1iiO45891w(0) <= NOT niOil1iiO; + wire_w_lg_niOil1ili45890w(0) <= NOT niOil1ili; + wire_w_lg_niOil1ill45889w(0) <= NOT niOil1ill; + wire_w_lg_niOil1ilO45888w(0) <= NOT niOil1ilO; + wire_w_lg_niOil1iOi45887w(0) <= NOT niOil1iOi; + wire_w_lg_niOil1iOl45886w(0) <= NOT niOil1iOl; + wire_w_lg_niOil1iOO45885w(0) <= NOT niOil1iOO; + wire_w_lg_niOil1l0i45881w(0) <= NOT niOil1l0i; + wire_w_lg_niOil1l0O45851w(0) <= NOT niOil1l0O; + wire_w_lg_niOil1l1i45884w(0) <= NOT niOil1l1i; + wire_w_lg_niOil1l1l45883w(0) <= NOT niOil1l1l; + wire_w_lg_niOil1l1O45882w(0) <= NOT niOil1l1O; + wire_w_lg_niOil1lii45850w(0) <= NOT niOil1lii; + wire_w_lg_niOil1lil45849w(0) <= NOT niOil1lil; + wire_w_lg_niOil1liO45848w(0) <= NOT niOil1liO; + wire_w_lg_niOil1lli45847w(0) <= NOT niOil1lli; + wire_w_lg_niOil1lll45846w(0) <= NOT niOil1lll; + wire_w_lg_niOil1llO45845w(0) <= NOT niOil1llO; + wire_w_lg_niOil1lOi45844w(0) <= NOT niOil1lOi; + wire_w_lg_niOil1lOl45843w(0) <= NOT niOil1lOl; + wire_w_lg_niOil1lOO45842w(0) <= NOT niOil1lOO; + wire_w_lg_niOil1O0i45838w(0) <= NOT niOil1O0i; + wire_w_lg_niOil1O0l45837w(0) <= NOT niOil1O0l; + wire_w_lg_niOil1O0O45836w(0) <= NOT niOil1O0O; + wire_w_lg_niOil1O1i45841w(0) <= NOT niOil1O1i; + wire_w_lg_niOil1O1l45840w(0) <= NOT niOil1O1l; + wire_w_lg_niOil1O1O45839w(0) <= NOT niOil1O1O; + wire_w_lg_niOil1Oii45835w(0) <= NOT niOil1Oii; + wire_w_lg_niOil1Oil45834w(0) <= NOT niOil1Oil; + wire_w_lg_niOil1OiO45833w(0) <= NOT niOil1OiO; + wire_w_lg_niOil1Oli45832w(0) <= NOT niOil1Oli; + wire_w_lg_niOil1Oll45831w(0) <= NOT niOil1Oll; + wire_w_lg_niOil1OlO45830w(0) <= NOT niOil1OlO; + wire_w_lg_niOil1OOi45829w(0) <= NOT niOil1OOi; + wire_w_lg_niOil1OOl45828w(0) <= NOT niOil1OOl; + wire_w_lg_niOil1OOO45827w(0) <= NOT niOil1OOO; + wire_w_lg_niOili00i47932w(0) <= NOT niOili00i; + wire_w_lg_niOili00l47930w(0) <= NOT niOili00l; + wire_w_lg_niOili00O47928w(0) <= NOT niOili00O; + wire_w_lg_niOili01i45527w(0) <= NOT niOili01i; + wire_w_lg_niOili0ii45092w(0) <= NOT niOili0ii; + wire_w_lg_niOili0iO53400w(0) <= NOT niOili0iO; + wire_w_lg_niOili0li53397w(0) <= NOT niOili0li; + wire_w_lg_niOili0ll53394w(0) <= NOT niOili0ll; + wire_w_lg_niOili0Ol45064w(0) <= NOT niOili0Ol; + wire_w_lg_niOili10i45688w(0) <= NOT niOili10i; + wire_w_lg_niOili10l45687w(0) <= NOT niOili10l; + wire_w_lg_niOili10O45686w(0) <= NOT niOili10O; + wire_w_lg_niOili11i45691w(0) <= NOT niOili11i; + wire_w_lg_niOili11l45690w(0) <= NOT niOili11l; + wire_w_lg_niOili11O45689w(0) <= NOT niOili11O; + wire_w_lg_niOili1ii45685w(0) <= NOT niOili1ii; + wire_w_lg_niOili1il45684w(0) <= NOT niOili1il; + wire_w_lg_niOili1iO45683w(0) <= NOT niOili1iO; + wire_w_lg_niOili1li45682w(0) <= NOT niOili1li; + wire_w_lg_niOili1ll45681w(0) <= NOT niOili1ll; + wire_w_lg_niOili1lO45680w(0) <= NOT niOili1lO; + wire_w_lg_niOili1Oi45679w(0) <= NOT niOili1Oi; + wire_w_lg_niOili1Ol45678w(0) <= NOT niOili1Ol; + wire_w_lg_niOili1OO45976w(0) <= NOT niOili1OO; + wire_w_lg_niOiliiOl45052w(0) <= NOT niOiliiOl; + wire_w_lg_niOiliiOO45050w(0) <= NOT niOiliiOO; + wire_w_lg_niOilil0i45036w(0) <= NOT niOilil0i; + wire_w_lg_niOilil0O45034w(0) <= NOT niOilil0O; + wire_w_lg_niOilil1O45126w(0) <= NOT niOilil1O; + wire_w_lg_niOill00i45131w(0) <= NOT niOill00i; + wire_w_lg_niOill00l45129w(0) <= NOT niOill00l; + wire_w_lg_niOill00O45127w(0) <= NOT niOill00O; + wire_w_lg_niOill01i45137w(0) <= NOT niOill01i; + wire_w_lg_niOill01l45135w(0) <= NOT niOill01l; + wire_w_lg_niOill01O45133w(0) <= NOT niOill01O; + wire_w_lg_niOill0iO44369w(0) <= NOT niOill0iO; + wire_w_lg_niOill0Ol45197w(0) <= NOT niOill0Ol; + wire_w_lg_niOill0OO44360w(0) <= NOT niOill0OO; + wire_w_lg_niOill1ll45147w(0) <= NOT niOill1ll; + wire_w_lg_niOill1lO45145w(0) <= NOT niOill1lO; + wire_w_lg_niOill1Oi45143w(0) <= NOT niOill1Oi; + wire_w_lg_niOill1Ol45141w(0) <= NOT niOill1Ol; + wire_w_lg_niOill1OO45139w(0) <= NOT niOill1OO; + wire_w_lg_niOilli0i45236w(0) <= NOT niOilli0i; + wire_w_lg_niOilli0l45240w(0) <= NOT niOilli0l; + wire_w_lg_niOilll0O44332w(0) <= NOT niOilll0O; + wire_w_lg_niOilll1i44485w(0) <= NOT niOilll1i; + wire_w_lg_niOilllii44330w(0) <= NOT niOilllii; + wire_w_lg_niOilllil44328w(0) <= NOT niOilllil; + wire_w_lg_niOillliO44326w(0) <= NOT niOillliO; + wire_w_lg_niOilllOl44309w(0) <= NOT niOilllOl; + wire_w_lg_niOilllOO44447w(0) <= NOT niOilllOO; + wire_w_lg_niOillO0i46470w(0) <= NOT niOillO0i; + wire_w_lg_niOillO0l46471w(0) <= NOT niOillO0l; + wire_w_lg_niOillOil44080w(0) <= NOT niOillOil; + wire_w_lg_niOillOiO44057w(0) <= NOT niOillOiO; + wire_w_lg_niOilO0ii43817w(0) <= NOT niOilO0ii; + wire_w_lg_niOilO11i52530w(0) <= NOT niOilO11i; + wire_w_lg_niOilOi1l43406w(0) <= NOT niOilOi1l; + wire_w_lg_niOilOi1O43404w(0) <= NOT niOilOi1O; + wire_w_lg_niOilOl1l43927w(0) <= NOT niOilOl1l; + wire_w_lg_niOilOlii43399w(0) <= NOT niOilOlii; + wire_w_lg_niOilOlli43955w(0) <= NOT niOilOlli; + wire_w_lg_niOilOlll44007w(0) <= NOT niOilOlll; + wire_w_lg_niOilOlOi44008w(0) <= NOT niOilOlOi; + wire_w_lg_niOilOlOl44009w(0) <= NOT niOilOlOl; + wire_w_lg_niOilOlOO43389w(0) <= NOT niOilOlOO; + wire_w_lg_niOilOO1i43375w(0) <= NOT niOilOO1i; + wire_w_lg_niOiO10Oi42898w(0) <= NOT niOiO10Oi; + wire_w_lg_niOiO110i42934w(0) <= NOT niOiO110i; + wire_w_lg_niOiO111l42937w(0) <= NOT niOiO111l; + wire_w_lg_niOiO1i0i42896w(0) <= NOT niOiO1i0i; + wire_w_lg_niOiO1i1l42897w(0) <= NOT niOiO1i1l; + wire_w_lg_niOiO1lOO42299w(0) <= NOT niOiO1lOO; + wire_w_lg_niOiO1O1l42254w(0) <= NOT niOiO1O1l; + wire_w_lg_niOiO1Oii42231w(0) <= NOT niOiO1Oii; + wire_w_lg_niOiO1OiO42230w(0) <= NOT niOiO1OiO; + wire_w_lg_niOiO1Oli42229w(0) <= NOT niOiO1Oli; + wire_w_lg_niOiO1OOl42297w(0) <= NOT niOiO1OOl; + wire_w_lg_niOiOi00i36176w(0) <= NOT niOiOi00i; + wire_w_lg_niOiOi01O36178w(0) <= NOT niOiOi01O; + wire_w_lg_niOiOi0li35985w(0) <= NOT niOiOi0li; + wire_w_lg_niOiOi1li36212w(0) <= NOT niOiOi1li; + wire_w_lg_niOiOi1ll36204w(0) <= NOT niOiOi1ll; + wire_w_lg_niOiOi1lO36222w(0) <= NOT niOiOi1lO; + wire_w_lg_niOiOi1Oi36215w(0) <= NOT niOiOi1Oi; + wire_w_lg_niOiOi1Ol36207w(0) <= NOT niOiOi1Ol; + wire_w_lg_niOiOi1OO36187w(0) <= NOT niOiOi1OO; + wire_w_lg_niOiOii0O35888w(0) <= NOT niOiOii0O; + wire_w_lg_niOiOilii35903w(0) <= NOT niOiOilii; + wire_w_lg_niOiOilil35819w(0) <= NOT niOiOilil; + wire_w_lg_niOiOiliO35913w(0) <= NOT niOiOiliO; + wire_w_lg_niOiOilli35807w(0) <= NOT niOiOilli; + wire_w_lg_niOiOillO35820w(0) <= NOT niOiOillO; + wire_w_lg_niOiOilOl35808w(0) <= NOT niOiOilOl; + wire_w_lg_niOiOiO0l35813w(0) <= NOT niOiOiO0l; + wire_w_lg_niOiOiO1i35814w(0) <= NOT niOiOiO1i; + wire_w_lg_niOiOiO1l35899w(0) <= NOT niOiOiO1l; + wire_w_lg_niOiOiO1O35802w(0) <= NOT niOiOiO1O; + wire_w_lg_niOiOiOii35801w(0) <= NOT niOiOiOii; + wire_w_lg_niOiOl1ii34770w(0) <= NOT niOiOl1ii; + wire_w_lg_niOiOli1i34556w(0) <= NOT niOiOli1i; + wire_w_lg_niOiOOiil29534w(0) <= NOT niOiOOiil; + wire_w_lg_niOl0011O23416w(0) <= NOT niOl0011O; + wire_w_lg_niOl00iiO23552w(0) <= NOT niOl00iiO; + wire_w_lg_niOl00iOl21215w(0) <= NOT niOl00iOl; + wire_w_lg_niOl00iOO21213w(0) <= NOT niOl00iOO; + wire_w_lg_niOl00l0O23857w(0) <= NOT niOl00l0O; + wire_w_lg_niOl00lil21194w(0) <= NOT niOl00lil; + wire_w_lg_niOl00lli21189w(0) <= NOT niOl00lli; + wire_w_lg_niOl00lOi21181w(0) <= NOT niOl00lOi; + wire_w_lg_niOl00lOO21178w(0) <= NOT niOl00lOO; + wire_w_lg_niOl00O0i26921w(0) <= NOT niOl00O0i; + wire_w_lg_niOl00O0l26919w(0) <= NOT niOl00O0l; + wire_w_lg_niOl00O0O26917w(0) <= NOT niOl00O0O; + wire_w_lg_niOl00O1i26927w(0) <= NOT niOl00O1i; + wire_w_lg_niOl00O1l26925w(0) <= NOT niOl00O1l; + wire_w_lg_niOl00O1O26923w(0) <= NOT niOl00O1O; + wire_w_lg_niOl00Oii26915w(0) <= NOT niOl00Oii; + wire_w_lg_niOl00Oil26914w(0) <= NOT niOl00Oil; + wire_w_lg_niOl00OiO21167w(0) <= NOT niOl00OiO; + wire_w_lg_niOl00Oll21164w(0) <= NOT niOl00Oll; + wire_w_lg_niOl0100O23590w(0) <= NOT niOl0100O; + wire_w_lg_niOl010ii23580w(0) <= NOT niOl010ii; + wire_w_lg_niOl010il23577w(0) <= NOT niOl010il; + wire_w_lg_niOl010iO23581w(0) <= NOT niOl010iO; + wire_w_lg_niOl010li23576w(0) <= NOT niOl010li; + wire_w_lg_niOl011Oi23591w(0) <= NOT niOl011Oi; + wire_w_lg_niOl01l0l23485w(0) <= NOT niOl01l0l; + wire_w_lg_niOl01lii23553w(0) <= NOT niOl01lii; + wire_w_lg_niOl01lli23469w(0) <= NOT niOl01lli; + wire_w_lg_niOl01lll23467w(0) <= NOT niOl01lll; + wire_w_lg_niOl01O0O23447w(0) <= NOT niOl01O0O; + wire_w_lg_niOl01Oii23445w(0) <= NOT niOl01Oii; + wire_w_lg_niOl01OiO23443w(0) <= NOT niOl01OiO; + wire_w_lg_niOl01Oli23441w(0) <= NOT niOl01Oli; + wire_w_lg_niOl01Oll23438w(0) <= NOT niOl01Oll; + wire_w_lg_niOl0i01l21114w(0) <= NOT niOl0i01l; + wire_w_lg_niOl0i0li21031w(0) <= NOT niOl0i0li; + wire_w_lg_niOl0i10l21148w(0) <= NOT niOl0i10l; + wire_w_lg_niOl0i1ii21161w(0) <= NOT niOl0i1ii; + wire_w_lg_niOl0ii0O21003w(0) <= NOT niOl0ii0O; + wire_w_lg_niOl0iill20999w(0) <= NOT niOl0iill; + wire_w_lg_niOl0iiOi20998w(0) <= NOT niOl0iiOi; + wire_w_lg_niOl0il0i20989w(0) <= NOT niOl0il0i; + wire_w_lg_niOl0il1l20993w(0) <= NOT niOl0il1l; + wire_w_lg_niOl0il1O20991w(0) <= NOT niOl0il1O; + wire_w_lg_niOl0iO0O20959w(0) <= NOT niOl0iO0O; + wire_w_lg_niOl0iOlO20945w(0) <= NOT niOl0iOlO; + wire_w_lg_niOl0iOOO20933w(0) <= NOT niOl0iOOO; + wire_w_lg_niOl0l00O20903w(0) <= NOT niOl0l00O; + wire_w_lg_niOl0l01l20907w(0) <= NOT niOl0l01l; + wire_w_lg_niOl0l01O20906w(0) <= NOT niOl0l01O; + wire_w_lg_niOl0l0il20914w(0) <= NOT niOl0l0il; + wire_w_lg_niOl0l0li20891w(0) <= NOT niOl0l0li; + wire_w_lg_niOl0l0lO20888w(0) <= NOT niOl0l0lO; + wire_w_lg_niOl0l0Oi26105w(0) <= NOT niOl0l0Oi; + wire_w_lg_niOl0l0Ol24321w(0) <= NOT niOl0l0Ol; + wire_w_lg_niOl0l0OO24320w(0) <= NOT niOl0l0OO; + wire_w_lg_niOl0l10O23466w(0) <= NOT niOl0l10O; + wire_w_lg_niOl0l11i20932w(0) <= NOT niOl0l11i; + wire_w_lg_niOl0l1iO23508w(0) <= NOT niOl0l1iO; + wire_w_lg_niOl0l1OO20936w(0) <= NOT niOl0l1OO; + wire_w_lg_niOl0li0i20880w(0) <= NOT niOl0li0i; + wire_w_lg_niOl0li0l26103w(0) <= NOT niOl0li0l; + wire_w_lg_niOl0li0O24326w(0) <= NOT niOl0li0O; + wire_w_lg_niOl0li1i20883w(0) <= NOT niOl0li1i; + wire_w_lg_niOl0liii24325w(0) <= NOT niOl0liii; + wire_w_lg_niOl0liil20875w(0) <= NOT niOl0liil; + wire_w_lg_niOl0lill20872w(0) <= NOT niOl0lill; + wire_w_lg_niOl0lilO26101w(0) <= NOT niOl0lilO; + wire_w_lg_niOl0liOi24331w(0) <= NOT niOl0liOi; + wire_w_lg_niOl0liOl24330w(0) <= NOT niOl0liOl; + wire_w_lg_niOl0liOO20867w(0) <= NOT niOl0liOO; + wire_w_lg_niOl0ll0i26099w(0) <= NOT niOl0ll0i; + wire_w_lg_niOl0ll0l24336w(0) <= NOT niOl0ll0l; + wire_w_lg_niOl0ll0O24335w(0) <= NOT niOl0ll0O; + wire_w_lg_niOl0ll1O20864w(0) <= NOT niOl0ll1O; + wire_w_lg_niOl0llii20859w(0) <= NOT niOl0llii; + wire_w_lg_niOl0llli20856w(0) <= NOT niOl0llli; + wire_w_lg_niOl0llll26097w(0) <= NOT niOl0llll; + wire_w_lg_niOl0lllO24341w(0) <= NOT niOl0lllO; + wire_w_lg_niOl0llOi24340w(0) <= NOT niOl0llOi; + wire_w_lg_niOl0llOl20851w(0) <= NOT niOl0llOl; + wire_w_lg_niOl0lO0i24346w(0) <= NOT niOl0lO0i; + wire_w_lg_niOl0lO0l24345w(0) <= NOT niOl0lO0l; + wire_w_lg_niOl0lO0O20843w(0) <= NOT niOl0lO0O; + wire_w_lg_niOl0lO1l20848w(0) <= NOT niOl0lO1l; + wire_w_lg_niOl0lO1O26095w(0) <= NOT niOl0lO1O; + wire_w_lg_niOl0lOiO20840w(0) <= NOT niOl0lOiO; + wire_w_lg_niOl0lOli26093w(0) <= NOT niOl0lOli; + wire_w_lg_niOl0lOll24351w(0) <= NOT niOl0lOll; + wire_w_lg_niOl0lOlO24350w(0) <= NOT niOl0lOlO; + wire_w_lg_niOl0lOOi20835w(0) <= NOT niOl0lOOi; + wire_w_lg_niOl0O00i25976w(0) <= NOT niOl0O00i; + wire_w_lg_niOl0O00l23564w(0) <= NOT niOl0O00l; + wire_w_lg_niOl0O00O23565w(0) <= NOT niOl0O00O; + wire_w_lg_niOl0O01i25981w(0) <= NOT niOl0O01i; + wire_w_lg_niOl0O01l25979w(0) <= NOT niOl0O01l; + wire_w_lg_niOl0O01O25977w(0) <= NOT niOl0O01O; + wire_w_lg_niOl0O0ii23566w(0) <= NOT niOl0O0ii; + wire_w_lg_niOl0O0il23567w(0) <= NOT niOl0O0il; + wire_w_lg_niOl0O0iO23568w(0) <= NOT niOl0O0iO; + wire_w_lg_niOl0O0li23569w(0) <= NOT niOl0O0li; + wire_w_lg_niOl0O0ll23570w(0) <= NOT niOl0O0ll; + wire_w_lg_niOl0O0lO23571w(0) <= NOT niOl0O0lO; + wire_w_lg_niOl0O0Oi20806w(0) <= NOT niOl0O0Oi; + wire_w_lg_niOl0O10i24355w(0) <= NOT niOl0O10i; + wire_w_lg_niOl0O10l20827w(0) <= NOT niOl0O10l; + wire_w_lg_niOl0O11i20832w(0) <= NOT niOl0O11i; + wire_w_lg_niOl0O11l26092w(0) <= NOT niOl0O11l; + wire_w_lg_niOl0O11O24356w(0) <= NOT niOl0O11O; + wire_w_lg_niOl0O1lO25989w(0) <= NOT niOl0O1lO; + wire_w_lg_niOl0O1Oi25987w(0) <= NOT niOl0O1Oi; + wire_w_lg_niOl0O1Ol25985w(0) <= NOT niOl0O1Ol; + wire_w_lg_niOl0O1OO25983w(0) <= NOT niOl0O1OO; + wire_w_lg_niOl0Oi1i23454w(0) <= NOT niOl0Oi1i; + wire_w_lg_niOl0Oiii20898w(0) <= NOT niOl0Oiii; + wire_w_lg_niOl0Ol0i21223w(0) <= NOT niOl0Ol0i; + wire_w_lg_niOl0Ol0l24926w(0) <= NOT niOl0Ol0l; + wire_w_lg_niOl0Ol0O20757w(0) <= NOT niOl0Ol0O; + wire_w_lg_niOl0Ol1l20786w(0) <= NOT niOl0Ol1l; + wire_w_lg_niOl0Ol1O20785w(0) <= NOT niOl0Ol1O; + wire_w_lg_niOl0Olil20684w(0) <= NOT niOl0Olil; + wire_w_lg_niOl0OO0l20555w(0) <= NOT niOl0OO0l; + wire_w_lg_niOl0OO0O25392w(0) <= NOT niOl0OO0O; + wire_w_lg_niOl0OO1O20640w(0) <= NOT niOl0OO1O; + wire_w_lg_niOl0OOii25390w(0) <= NOT niOl0OOii; + wire_w_lg_niOl0OOil25388w(0) <= NOT niOl0OOil; + wire_w_lg_niOl0OOiO25386w(0) <= NOT niOl0OOiO; + wire_w_lg_niOl0OOli25384w(0) <= NOT niOl0OOli; + wire_w_lg_niOl0OOll25382w(0) <= NOT niOl0OOll; + wire_w_lg_niOl0OOlO25380w(0) <= NOT niOl0OOlO; + wire_w_lg_niOl0OOOi25379w(0) <= NOT niOl0OOOi; + wire_w_lg_niOl0OOOl20506w(0) <= NOT niOl0OOOl; + wire_w_lg_niOl1000l28781w(0) <= NOT niOl1000l; + wire_w_lg_niOl1000O28779w(0) <= NOT niOl1000O; + wire_w_lg_niOl1001i28835w(0) <= NOT niOl1001i; + wire_w_lg_niOl1001O28823w(0) <= NOT niOl1001O; + wire_w_lg_niOl100ii28773w(0) <= NOT niOl100ii; + wire_w_lg_niOl100il28766w(0) <= NOT niOl100il; + wire_w_lg_niOl100iO28759w(0) <= NOT niOl100iO; + wire_w_lg_niOl100li28752w(0) <= NOT niOl100li; + wire_w_lg_niOl100ll28745w(0) <= NOT niOl100ll; + wire_w_lg_niOl100lO28738w(0) <= NOT niOl100lO; + wire_w_lg_niOl100Oi28731w(0) <= NOT niOl100Oi; + wire_w_lg_niOl100Ol28724w(0) <= NOT niOl100Ol; + wire_w_lg_niOl100OO28717w(0) <= NOT niOl100OO; + wire_w_lg_niOl1010l29171w(0) <= NOT niOl1010l; + wire_w_lg_niOl1011O28876w(0) <= NOT niOl1011O; + wire_w_lg_niOl101ii28869w(0) <= NOT niOl101ii; + wire_w_lg_niOl101il28868w(0) <= NOT niOl101il; + wire_w_lg_niOl101iO29694w(0) <= NOT niOl101iO; + wire_w_lg_niOl101lO29696w(0) <= NOT niOl101lO; + wire_w_lg_niOl101OO28842w(0) <= NOT niOl101OO; + wire_w_lg_niOl10i0l28669w(0) <= NOT niOl10i0l; + wire_w_lg_niOl10i1l28688w(0) <= NOT niOl10i1l; + wire_w_lg_niOl10i1O28686w(0) <= NOT niOl10i1O; + wire_w_lg_niOl10iii28651w(0) <= NOT niOl10iii; + wire_w_lg_niOl10iil28649w(0) <= NOT niOl10iil; + wire_w_lg_niOl10ill28541w(0) <= NOT niOl10ill; + wire_w_lg_niOl10ilO28539w(0) <= NOT niOl10ilO; + wire_w_lg_niOl10iOl28534w(0) <= NOT niOl10iOl; + wire_w_lg_niOl10l0i28518w(0) <= NOT niOl10l0i; + wire_w_lg_niOl10l1l28529w(0) <= NOT niOl10l1l; + wire_w_lg_niOl10l1O28516w(0) <= NOT niOl10l1O; + wire_w_lg_niOl10lii28478w(0) <= NOT niOl10lii; + wire_w_lg_niOl10lil28482w(0) <= NOT niOl10lil; + wire_w_lg_niOl10liO28475w(0) <= NOT niOl10liO; + wire_w_lg_niOl10lli28474w(0) <= NOT niOl10lli; + wire_w_lg_niOl10lll28464w(0) <= NOT niOl10lll; + wire_w_lg_niOl10lOl28356w(0) <= NOT niOl10lOl; + wire_w_lg_niOl10lOO28354w(0) <= NOT niOl10lOO; + wire_w_lg_niOl10O0i28344w(0) <= NOT niOl10O0i; + wire_w_lg_niOl10O0l28331w(0) <= NOT niOl10O0l; + wire_w_lg_niOl10O0O28333w(0) <= NOT niOl10O0O; + wire_w_lg_niOl10O1l28349w(0) <= NOT niOl10O1l; + wire_w_lg_niOl10OiO28293w(0) <= NOT niOl10OiO; + wire_w_lg_niOl10Oli28297w(0) <= NOT niOl10Oli; + wire_w_lg_niOl10Oll28290w(0) <= NOT niOl10Oll; + wire_w_lg_niOl10OlO28289w(0) <= NOT niOl10OlO; + wire_w_lg_niOl10OOi28279w(0) <= NOT niOl10OOi; + wire_w_lg_niOl10OOl28272w(0) <= NOT niOl10OOl; + wire_w_lg_niOl10OOO28265w(0) <= NOT niOl10OOO; + wire_w_lg_niOl1100i29483w(0) <= NOT niOl1100i; + wire_w_lg_niOl1100l29482w(0) <= NOT niOl1100l; + wire_w_lg_niOl1100O29481w(0) <= NOT niOl1100O; + wire_w_lg_niOl1101i29486w(0) <= NOT niOl1101i; + wire_w_lg_niOl1101l29485w(0) <= NOT niOl1101l; + wire_w_lg_niOl1101O29484w(0) <= NOT niOl1101O; + wire_w_lg_niOl110ii29480w(0) <= NOT niOl110ii; + wire_w_lg_niOl110il29479w(0) <= NOT niOl110il; + wire_w_lg_niOl110iO29478w(0) <= NOT niOl110iO; + wire_w_lg_niOl110li29477w(0) <= NOT niOl110li; + wire_w_lg_niOl110ll29476w(0) <= NOT niOl110ll; + wire_w_lg_niOl110lO29475w(0) <= NOT niOl110lO; + wire_w_lg_niOl110Oi29474w(0) <= NOT niOl110Oi; + wire_w_lg_niOl110Ol29473w(0) <= NOT niOl110Ol; + wire_w_lg_niOl110OO29472w(0) <= NOT niOl110OO; + wire_w_lg_niOl111Oi29489w(0) <= NOT niOl111Oi; + wire_w_lg_niOl111Ol29488w(0) <= NOT niOl111Ol; + wire_w_lg_niOl111OO29487w(0) <= NOT niOl111OO; + wire_w_lg_niOl11i0i29468w(0) <= NOT niOl11i0i; + wire_w_lg_niOl11i0l29467w(0) <= NOT niOl11i0l; + wire_w_lg_niOl11i0O29466w(0) <= NOT niOl11i0O; + wire_w_lg_niOl11i1i29471w(0) <= NOT niOl11i1i; + wire_w_lg_niOl11i1l29470w(0) <= NOT niOl11i1l; + wire_w_lg_niOl11i1O29469w(0) <= NOT niOl11i1O; + wire_w_lg_niOl11iii29465w(0) <= NOT niOl11iii; + wire_w_lg_niOl11iil29464w(0) <= NOT niOl11iil; + wire_w_lg_niOl11iiO29463w(0) <= NOT niOl11iiO; + wire_w_lg_niOl11ili29462w(0) <= NOT niOl11ili; + wire_w_lg_niOl11ill29461w(0) <= NOT niOl11ill; + wire_w_lg_niOl11ilO29460w(0) <= NOT niOl11ilO; + wire_w_lg_niOl11iOi29459w(0) <= NOT niOl11iOi; + wire_w_lg_niOl11iOl29458w(0) <= NOT niOl11iOl; + wire_w_lg_niOl11l1i29456w(0) <= NOT niOl11l1i; + wire_w_lg_niOl11l1O32019w(0) <= NOT niOl11l1O; + wire_w_lg_niOl11lll29365w(0) <= NOT niOl11lll; + wire_w_lg_niOl11OOl34628w(0) <= NOT niOl11OOl; + wire_w_lg_niOl1i01O24999w(0) <= NOT niOl1i01O; + wire_w_lg_niOl1i0OO24782w(0) <= NOT niOl1i0OO; + wire_w_lg_niOl1i11O28120w(0) <= NOT niOl1i11O; + wire_w_lg_niOl1i1ii28036w(0) <= NOT niOl1i1ii; + wire_w_lg_niOl1i1li25150w(0) <= NOT niOl1i1li; + wire_w_lg_niOl1i1ll25149w(0) <= NOT niOl1i1ll; + wire_w_lg_niOl1i1Oi25148w(0) <= NOT niOl1i1Oi; + wire_w_lg_niOl1i1OO25058w(0) <= NOT niOl1i1OO; + wire_w_lg_niOl1il1l24681w(0) <= NOT niOl1il1l; + wire_w_lg_niOl1iOli24631w(0) <= NOT niOl1iOli; + wire_w_lg_niOl1iOOi24593w(0) <= NOT niOl1iOOi; + wire_w_lg_niOl1iOOl24592w(0) <= NOT niOl1iOOl; + wire_w_lg_niOl1l00i24425w(0) <= NOT niOl1l00i; + wire_w_lg_niOl1l00l24429w(0) <= NOT niOl1l00l; + wire_w_lg_niOl1l00O24433w(0) <= NOT niOl1l00O; + wire_w_lg_niOl1l01l24417w(0) <= NOT niOl1l01l; + wire_w_lg_niOl1l01O24421w(0) <= NOT niOl1l01O; + wire_w_lg_niOl1l0ii24437w(0) <= NOT niOl1l0ii; + wire_w_lg_niOl1l0il24441w(0) <= NOT niOl1l0il; + wire_w_lg_niOl1l0iO24445w(0) <= NOT niOl1l0iO; + wire_w_lg_niOl1l11i24589w(0) <= NOT niOl1l11i; + wire_w_lg_niOl1lO0l24102w(0) <= NOT niOl1lO0l; + wire_w_lg_niOl1lO0O24100w(0) <= NOT niOl1lO0O; + wire_w_lg_niOl1lOii24098w(0) <= NOT niOl1lOii; + wire_w_lg_niOl1lOil24096w(0) <= NOT niOl1lOil; + wire_w_lg_niOl1lOiO24094w(0) <= NOT niOl1lOiO; + wire_w_lg_niOl1lOli24092w(0) <= NOT niOl1lOli; + wire_w_lg_niOl1lOll24090w(0) <= NOT niOl1lOll; + wire_w_lg_niOl1lOlO24088w(0) <= NOT niOl1lOlO; + wire_w_lg_niOl1lOOi26657w(0) <= NOT niOl1lOOi; + wire_w_lg_niOl1lOOl26652w(0) <= NOT niOl1lOOl; + wire_w_lg_niOl1lOOO26647w(0) <= NOT niOl1lOOO; + wire_w_lg_niOl1O00i23992w(0) <= NOT niOl1O00i; + wire_w_lg_niOl1O00l23990w(0) <= NOT niOl1O00l; + wire_w_lg_niOl1O00O23988w(0) <= NOT niOl1O00O; + wire_w_lg_niOl1O01l23996w(0) <= NOT niOl1O01l; + wire_w_lg_niOl1O01O23994w(0) <= NOT niOl1O01O; + wire_w_lg_niOl1O0ii23986w(0) <= NOT niOl1O0ii; + wire_w_lg_niOl1O0il23984w(0) <= NOT niOl1O0il; + wire_w_lg_niOl1O0iO23983w(0) <= NOT niOl1O0iO; + wire_w_lg_niOl1O10i26627w(0) <= NOT niOl1O10i; + wire_w_lg_niOl1O10l26623w(0) <= NOT niOl1O10l; + wire_w_lg_niOl1O11i26642w(0) <= NOT niOl1O11i; + wire_w_lg_niOl1O11l26637w(0) <= NOT niOl1O11l; + wire_w_lg_niOl1O11O26632w(0) <= NOT niOl1O11O; + wire_w_lg_niOl1OliO23853w(0) <= NOT niOl1OliO; + wire_w_lg_niOl1OOli23839w(0) <= NOT niOl1OOli; + wire_w_lg_niOli000i19580w(0) <= NOT niOli000i; + wire_w_lg_niOli01il19578w(0) <= NOT niOli01il; + wire_w_lg_niOli01iO19565w(0) <= NOT niOli01iO; + wire_w_lg_niOli01OO19562w(0) <= NOT niOli01OO; + wire_w_lg_niOli0i1O19660w(0) <= NOT niOli0i1O; + wire_w_lg_niOli0iil18989w(0) <= NOT niOli0iil; + wire_w_lg_niOli0ill19512w(0) <= NOT niOli0ill; + wire_w_lg_niOli0iOi19465w(0) <= NOT niOli0iOi; + wire_w_lg_niOli0l0i19564w(0) <= NOT niOli0l0i; + wire_w_lg_niOli0l0O18972w(0) <= NOT niOli0l0O; + wire_w_lg_niOli0llO18964w(0) <= NOT niOli0llO; + wire_w_lg_niOli0lOl18958w(0) <= NOT niOli0lOl; + wire_w_lg_niOli0lOO18956w(0) <= NOT niOli0lOO; + wire_w_lg_niOli0O1i19670w(0) <= NOT niOli0O1i; + wire_w_lg_niOli0O1l19558w(0) <= NOT niOli0O1l; + wire_w_lg_niOli0O1O18941w(0) <= NOT niOli0O1O; + wire_w_lg_niOli0OlO18770w(0) <= NOT niOli0OlO; + wire_w_lg_niOli101i20192w(0) <= NOT niOli101i; + wire_w_lg_niOli101l20190w(0) <= NOT niOli101l; + wire_w_lg_niOli101O20189w(0) <= NOT niOli101O; + wire_w_lg_niOli10il21112w(0) <= NOT niOli10il; + wire_w_lg_niOli10Ol20065w(0) <= NOT niOli10Ol; + wire_w_lg_niOli111l20301w(0) <= NOT niOli111l; + wire_w_lg_niOli11iO20255w(0) <= NOT niOli11iO; + wire_w_lg_niOli11ll20252w(0) <= NOT niOli11ll; + wire_w_lg_niOli11Ol20248w(0) <= NOT niOli11Ol; + wire_w_lg_niOli1iiO20055w(0) <= NOT niOli1iiO; + wire_w_lg_niOli1iOl20954w(0) <= NOT niOli1iOl; + wire_w_lg_niOli1iOO20777w(0) <= NOT niOli1iOO; + wire_w_lg_niOli1l1i20778w(0) <= NOT niOli1l1i; + wire_w_lg_niOli1l1O19995w(0) <= NOT niOli1l1O; + wire_w_lg_niOli1lli19684w(0) <= NOT niOli1lli; + wire_w_lg_niOli1lOl19682w(0) <= NOT niOli1lOl; + wire_w_lg_niOli1lOO19594w(0) <= NOT niOli1lOO; + wire_w_lg_niOli1O0O19579w(0) <= NOT niOli1O0O; + wire_w_lg_niOli1OiO23494w(0) <= NOT niOli1OiO; + wire_w_lg_niOlii00l18351w(0) <= NOT niOlii00l; + wire_w_lg_niOlii01l18354w(0) <= NOT niOlii01l; + wire_w_lg_niOlii0iO18300w(0) <= NOT niOlii0iO; + wire_w_lg_niOlii0Oi18229w(0) <= NOT niOlii0Oi; + wire_w_lg_niOlii11i18931w(0) <= NOT niOlii11i; + wire_w_lg_niOlii1Oi18396w(0) <= NOT niOlii1Oi; + wire_w_lg_niOliiiil18296w(0) <= NOT niOliiiil; + wire_w_lg_niOliiiOO18267w(0) <= NOT niOliiiOO; + wire_w_lg_niOliil0l18160w(0) <= NOT niOliil0l; + wire_w_lg_niOliil1i18278w(0) <= NOT niOliil1i; + wire_w_lg_niOliil1O18295w(0) <= NOT niOliil1O; + wire_w_lg_niOliilii18159w(0) <= NOT niOliilii; + wire_w_lg_niOliilli18117w(0) <= NOT niOliilli; + wire_w_lg_niOlil0lO17489w(0) <= NOT niOlil0lO; + wire_w_lg_niOlil1li17913w(0) <= NOT niOlil1li; + wire_w_lg_niOlil1ll18059w(0) <= NOT niOlil1ll; + wire_w_lg_niOlil1lO17908w(0) <= NOT niOlil1lO; + wire_w_lg_niOlil1Oi17916w(0) <= NOT niOlil1Oi; + wire_w_lg_niOlili0i17444w(0) <= NOT niOlili0i; + wire_w_lg_niOlili1i17447w(0) <= NOT niOlili1i; + wire_w_lg_niOliliil17393w(0) <= NOT niOliliil; + wire_w_lg_niOlililO17322w(0) <= NOT niOlililO; + wire_w_lg_niOlillii17389w(0) <= NOT niOlillii; + wire_w_lg_niOlillOl17360w(0) <= NOT niOlillOl; + wire_w_lg_niOlillOO17371w(0) <= NOT niOlillOO; + wire_w_lg_niOlilO0i17253w(0) <= NOT niOlilO0i; + wire_w_lg_niOlilO0O17252w(0) <= NOT niOlilO0O; + wire_w_lg_niOlilO1l17388w(0) <= NOT niOlilO1l; + wire_w_lg_niOlilOiO17210w(0) <= NOT niOlilOiO; + wire_w_lg_niOliO0iO17006w(0) <= NOT niOliO0iO; + wire_w_lg_niOliO0li17152w(0) <= NOT niOliO0li; + wire_w_lg_niOliO0ll17001w(0) <= NOT niOliO0ll; + wire_w_lg_niOliO0lO17009w(0) <= NOT niOliO0lO; + wire_w_lg_niOliOill16582w(0) <= NOT niOliOill; + wire_w_lg_niOliOiOO16540w(0) <= NOT niOliOiOO; + wire_w_lg_niOliOl1O16537w(0) <= NOT niOliOl1O; + wire_w_lg_niOliOlii16486w(0) <= NOT niOliOlii; + wire_w_lg_niOliOlll16415w(0) <= NOT niOliOlll; + wire_w_lg_niOliOO0O16482w(0) <= NOT niOliOO0O; + wire_w_lg_niOliOOOi16453w(0) <= NOT niOliOOOi; + wire_w_lg_niOliOOOl16464w(0) <= NOT niOliOOOl; + wire_w_lg_niOll000i15438w(0) <= NOT niOll000i; + wire_w_lg_niOll001l15439w(0) <= NOT niOll001l; + wire_w_lg_niOll00ii15396w(0) <= NOT niOll00ii; + wire_w_lg_niOll010l15575w(0) <= NOT niOll010l; + wire_w_lg_niOll01lO15546w(0) <= NOT niOll01lO; + wire_w_lg_niOll01Oi15557w(0) <= NOT niOll01Oi; + wire_w_lg_niOll01OO15574w(0) <= NOT niOll01OO; + wire_w_lg_niOll0lii15192w(0) <= NOT niOll0lii; + wire_w_lg_niOll0lil15338w(0) <= NOT niOll0lil; + wire_w_lg_niOll0liO15187w(0) <= NOT niOll0liO; + wire_w_lg_niOll0lli15195w(0) <= NOT niOll0lli; + wire_w_lg_niOll0OiO14768w(0) <= NOT niOll0OiO; + wire_w_lg_niOll0OOi14726w(0) <= NOT niOll0OOi; + wire_w_lg_niOll110l16345w(0) <= NOT niOll110l; + wire_w_lg_niOll111i16481w(0) <= NOT niOll111i; + wire_w_lg_niOll111O16346w(0) <= NOT niOll111O; + wire_w_lg_niOll11il16303w(0) <= NOT niOll11il; + wire_w_lg_niOll1iil16099w(0) <= NOT niOll1iil; + wire_w_lg_niOll1iiO16245w(0) <= NOT niOll1iiO; + wire_w_lg_niOll1ili16094w(0) <= NOT niOll1ili; + wire_w_lg_niOll1ill16102w(0) <= NOT niOll1ill; + wire_w_lg_niOll1lli15675w(0) <= NOT niOll1lli; + wire_w_lg_niOll1lOl15633w(0) <= NOT niOll1lOl; + wire_w_lg_niOll1O0O15579w(0) <= NOT niOll1O0O; + wire_w_lg_niOll1O1l15630w(0) <= NOT niOll1O1l; + wire_w_lg_niOll1Oli15508w(0) <= NOT niOll1Oli; + wire_w_lg_niOlli00i14668w(0) <= NOT niOlli00i; + wire_w_lg_niOlli0ll14639w(0) <= NOT niOlli0ll; + wire_w_lg_niOlli0lO14650w(0) <= NOT niOlli0lO; + wire_w_lg_niOlli0Ol14667w(0) <= NOT niOlli0Ol; + wire_w_lg_niOlli10l14672w(0) <= NOT niOlli10l; + wire_w_lg_niOlli11i14723w(0) <= NOT niOlli11i; + wire_w_lg_niOlli1iO14601w(0) <= NOT niOlli1iO; + wire_w_lg_niOllii0O14489w(0) <= NOT niOllii0O; + wire_w_lg_niOllii1i14532w(0) <= NOT niOllii1i; + wire_w_lg_niOllii1O14531w(0) <= NOT niOllii1O; + wire_w_lg_niOlliO0O14285w(0) <= NOT niOlliO0O; + wire_w_lg_niOlliOii14431w(0) <= NOT niOlliOii; + wire_w_lg_niOlliOil14280w(0) <= NOT niOlliOil; + wire_w_lg_niOlliOiO14288w(0) <= NOT niOlliOiO; + wire_w_lg_niOlll00i13765w(0) <= NOT niOlll00i; + wire_w_lg_niOlll0il13694w(0) <= NOT niOlll0il; + wire_w_lg_niOlll1il13861w(0) <= NOT niOlll1il; + wire_w_lg_niOlll1lO13819w(0) <= NOT niOlll1lO; + wire_w_lg_niOlll1OO13816w(0) <= NOT niOlll1OO; + wire_w_lg_niOllli1O13761w(0) <= NOT niOllli1O; + wire_w_lg_niOlllili13732w(0) <= NOT niOlllili; + wire_w_lg_niOlllill13743w(0) <= NOT niOlllill; + wire_w_lg_niOllliOi13760w(0) <= NOT niOllliOi; + wire_w_lg_niOllliOO13625w(0) <= NOT niOllliOO; + wire_w_lg_niOllll0l13582w(0) <= NOT niOllll0l; + wire_w_lg_niOllll1l13624w(0) <= NOT niOllll1l; + wire_w_lg_niOllO0ii12954w(0) <= NOT niOllO0ii; + wire_w_lg_niOllO0ll12912w(0) <= NOT niOllO0ll; + wire_w_lg_niOllO0Ol12909w(0) <= NOT niOllO0Ol; + wire_w_lg_niOllO10l13378w(0) <= NOT niOllO10l; + wire_w_lg_niOllO10O13524w(0) <= NOT niOllO10O; + wire_w_lg_niOllO1ii13373w(0) <= NOT niOllO1ii; + wire_w_lg_niOllO1il13381w(0) <= NOT niOllO1il; + wire_w_lg_niOllOi1O12858w(0) <= NOT niOllOi1O; + wire_w_lg_niOllOiii12787w(0) <= NOT niOllOiii; + wire_w_lg_niOllOl1l12854w(0) <= NOT niOllOl1l; + wire_w_lg_niOllOliO12825w(0) <= NOT niOllOliO; + wire_w_lg_niOllOlli12836w(0) <= NOT niOllOlli; + wire_w_lg_niOllOllO12853w(0) <= NOT niOllOllO; + wire_w_lg_niOllOlOl12718w(0) <= NOT niOllOlOl; + wire_w_lg_niOllOO0i12675w(0) <= NOT niOllOO0i; + wire_w_lg_niOllOO1i12717w(0) <= NOT niOllOO1i; + wire_w_lg_niOlO010i11764w(0) <= NOT niOlO010i; + wire_w_lg_niOlO011i11806w(0) <= NOT niOlO011i; + wire_w_lg_niOlO0i0i11558w(0) <= NOT niOlO0i0i; + wire_w_lg_niOlO0i0l11706w(0) <= NOT niOlO0i0l; + wire_w_lg_niOlO0i0O11553w(0) <= NOT niOlO0i0O; + wire_w_lg_niOlO0iii11562w(0) <= NOT niOlO0iii; + wire_w_lg_niOlO0liO11440w(0) <= NOT niOlO0liO; + wire_w_lg_niOlO0Oll11359w(0) <= NOT niOlO0Oll; + wire_w_lg_niOlO100i12471w(0) <= NOT niOlO100i; + wire_w_lg_niOlO100l12617w(0) <= NOT niOlO100l; + wire_w_lg_niOlO100O12466w(0) <= NOT niOlO100O; + wire_w_lg_niOlO10ii12474w(0) <= NOT niOlO10ii; + wire_w_lg_niOlO1i0O12043w(0) <= NOT niOlO1i0O; + wire_w_lg_niOlO1ili12001w(0) <= NOT niOlO1ili; + wire_w_lg_niOlO1iOi11998w(0) <= NOT niOlO1iOi; + wire_w_lg_niOlO1l0O11876w(0) <= NOT niOlO1l0O; + wire_w_lg_niOlO1l1l11947w(0) <= NOT niOlO1l1l; + wire_w_lg_niOlO1O0i20967w(0) <= NOT niOlO1O0i; + wire_w_lg_niOlO1O1i11943w(0) <= NOT niOlO1O1i; + wire_w_lg_niOlO1OiO11914w(0) <= NOT niOlO1OiO; + wire_w_lg_niOlO1Oli11925w(0) <= NOT niOlO1Oli; + wire_w_lg_niOlO1OlO11942w(0) <= NOT niOlO1OlO; + wire_w_lg_niOlO1OOl11807w(0) <= NOT niOlO1OOl; + wire_w_lg_niOlOi0OO11197w(0) <= NOT niOlOi0OO; + wire_w_lg_niOlOi1Oi11278w(0) <= NOT niOlOi1Oi; + wire_w_lg_niOlOil1l11116w(0) <= NOT niOlOil1l; + wire_w_lg_niOlOiO0i11035w(0) <= NOT niOlOiO0i; + wire_w_lg_niOlOl0il10873w(0) <= NOT niOlOl0il; + wire_w_lg_niOlOl0Ol10165w(0) <= NOT niOlOl0Ol; + wire_w_lg_niOlOl10O10954w(0) <= NOT niOlOl10O; + wire_w_lg_niOlOli0i10824w(0) <= NOT niOlOli0i; + wire_w_lg_niOlOli0l10822w(0) <= NOT niOlOli0l; + wire_w_lg_niOlOli0O10820w(0) <= NOT niOlOli0O; + wire_w_lg_niOlOli1l10828w(0) <= NOT niOlOli1l; + wire_w_lg_niOlOli1O10826w(0) <= NOT niOlOli1O; + wire_w_lg_niOlOliii10818w(0) <= NOT niOlOliii; + wire_w_lg_niOlOliil10816w(0) <= NOT niOlOliil; + wire_w_lg_niOlOliiO10815w(0) <= NOT niOlOliiO; + wire_w_lg_niOlOll0l10155w(0) <= NOT niOlOll0l; + wire_w_lg_niOlOll1i10154w(0) <= NOT niOlOll1i; + wire_w_lg_niOlOll1O10153w(0) <= NOT niOlOll1O; + wire_w_lg_niOlOllll10854w(0) <= NOT niOlOllll; + wire_w_lg_niOlOlO0l10935w(0) <= NOT niOlOlO0l; + wire_w_lg_niOlOlOOl11016w(0) <= NOT niOlOlOOl; + wire_w_lg_niOlOO01l11178w(0) <= NOT niOlOO01l; + wire_w_lg_niOlOO0ll11259w(0) <= NOT niOlOO0ll; + wire_w_lg_niOlOO1il11097w(0) <= NOT niOlOO1il; + wire_w_lg_niOlOOi0l11340w(0) <= NOT niOlOOi0l; + wire_w_lg_niOlOOiOl11421w(0) <= NOT niOlOOiOl; + wire_w_lg_niOlOOO1l9961w(0) <= NOT niOlOOO1l; + wire_w_lg_niOlOOO1O9954w(0) <= NOT niOlOOO1O; + wire_w_lg_niOO000ll4352w(0) <= NOT niOO000ll; + wire_w_lg_niOO000Oi4345w(0) <= NOT niOO000Oi; + wire_w_lg_niOO0010l4569w(0) <= NOT niOO0010l; + wire_w_lg_niOO0011i4578w(0) <= NOT niOO0011i; + wire_w_lg_niOO0011O4571w(0) <= NOT niOO0011O; + wire_w_lg_niOO001ii4567w(0) <= NOT niOO001ii; + wire_w_lg_niOO001iO4486w(0) <= NOT niOO001iO; + wire_w_lg_niOO001li4490w(0) <= NOT niOO001li; + wire_w_lg_niOO001ll4483w(0) <= NOT niOO001ll; + wire_w_lg_niOO001lO4482w(0) <= NOT niOO001lO; + wire_w_lg_niOO00llO4046w(0) <= NOT niOO00llO; + wire_w_lg_niOO00lOO4032w(0) <= NOT niOO00lOO; + wire_w_lg_niOO00O0l4023w(0) <= NOT niOO00O0l; + wire_w_lg_niOO00Oii3766w(0) <= NOT niOO00Oii; + wire_w_lg_niOO00Oil3768w(0) <= NOT niOO00Oil; + wire_w_lg_niOO00OOl3742w(0) <= NOT niOO00OOl; + wire_w_lg_niOO00OOO3743w(0) <= NOT niOO00OOO; + wire_w_lg_niOO010iO5648w(0) <= NOT niOO010iO; + wire_w_lg_niOO01i1l5387w(0) <= NOT niOO01i1l; + wire_w_lg_niOO01l0l5119w(0) <= NOT niOO01l0l; + wire_w_lg_niOO01lii5127w(0) <= NOT niOO01lii; + wire_w_lg_niOO01liO5159w(0) <= NOT niOO01liO; + wire_w_lg_niOO01lli5092w(0) <= NOT niOO01lli; + wire_w_lg_niOO01lOi5719w(0) <= NOT niOO01lOi; + wire_w_lg_niOO01lOl5214w(0) <= NOT niOO01lOl; + wire_w_lg_niOO01O0i4613w(0) <= NOT niOO01O0i; + wire_w_lg_niOO01O0l4615w(0) <= NOT niOO01O0l; + wire_w_lg_niOO01Oll4589w(0) <= NOT niOO01Oll; + wire_w_lg_niOO01OlO4590w(0) <= NOT niOO01OlO; + wire_w_lg_niOO01OOl4583w(0) <= NOT niOO01OOl; + wire_w_lg_niOO0i10i3731w(0) <= NOT niOO0i10i; + wire_w_lg_niOO0i10l3724w(0) <= NOT niOO0i10l; + wire_w_lg_niOO0i11l3736w(0) <= NOT niOO0i11l; + wire_w_lg_niOO0i1ii3722w(0) <= NOT niOO0i1ii; + wire_w_lg_niOO0i1iO3720w(0) <= NOT niOO0i1iO; + wire_w_lg_niOO0i1ll3640w(0) <= NOT niOO0i1ll; + wire_w_lg_niOO0i1lO3644w(0) <= NOT niOO0i1lO; + wire_w_lg_niOO0i1Oi3637w(0) <= NOT niOO0i1Oi; + wire_w_lg_niOO0i1Ol3636w(0) <= NOT niOO0i1Ol; + wire_w_lg_niOO0i1OO3830w(0) <= NOT niOO0i1OO; + wire_w_lg_niOO0iiOi3378w(0) <= NOT niOO0iiOi; + wire_w_lg_niOO0iiOO3252w(0) <= NOT niOO0iiOO; + wire_w_lg_niOO0il0i3404w(0) <= NOT niOO0il0i; + wire_w_lg_niOO0il0l3327w(0) <= NOT niOO0il0l; + wire_w_lg_niOO0il1O3274w(0) <= NOT niOO0il1O; + wire_w_lg_niOO0illl2759w(0) <= NOT niOO0illl; + wire_w_lg_niOO0illO2761w(0) <= NOT niOO0illO; + wire_w_lg_niOO0iO0i2736w(0) <= NOT niOO0iO0i; + wire_w_lg_niOO0iO0O2729w(0) <= NOT niOO0iO0O; + wire_w_lg_niOO0iO1O2735w(0) <= NOT niOO0iO1O; + wire_w_lg_niOO0iOil2724w(0) <= NOT niOO0iOil; + wire_w_lg_niOO0iOll2717w(0) <= NOT niOO0iOll; + wire_w_lg_niOO0iOOi2715w(0) <= NOT niOO0iOOi; + wire_w_lg_niOO0iOOO2713w(0) <= NOT niOO0iOOO; + wire_w_lg_niOO0l0li2415w(0) <= NOT niOO0l0li; + wire_w_lg_niOO0l0OO2405w(0) <= NOT niOO0l0OO; + wire_w_lg_niOO0l10i2627w(0) <= NOT niOO0l10i; + wire_w_lg_niOO0l10l2626w(0) <= NOT niOO0l10l; + wire_w_lg_niOO0l11l2630w(0) <= NOT niOO0l11l; + wire_w_lg_niOO0l11O2634w(0) <= NOT niOO0l11O; + wire_w_lg_niOO0lOOi2256w(0) <= NOT niOO0lOOi; + wire_w_lg_niOO0lOOl2255w(0) <= NOT niOO0lOOl; + wire_w_lg_niOO0O11l2254w(0) <= NOT niOO0O11l; + wire_w_lg_niOO0O11O2253w(0) <= NOT niOO0O11O; + wire_w_lg_niOO0O1ll4426w(0) <= NOT niOO0O1ll; + wire_w_lg_niOO0O1lO2591w(0) <= NOT niOO0O1lO; + wire_w_lg_niOO10ilO9183w(0) <= NOT niOO10ilO; + wire_w_lg_niOO10iOi9182w(0) <= NOT niOO10iOi; + wire_w_lg_niOO10iOl9024w(0) <= NOT niOO10iOl; + wire_w_lg_niOO10iOO9023w(0) <= NOT niOO10iOO; + wire_w_lg_niOO10l1i20908w(0) <= NOT niOO10l1i; + wire_w_lg_niOO10lii45508w(0) <= NOT niOO10lii; + wire_w_lg_niOO10lil45510w(0) <= NOT niOO10lil; + wire_w_lg_niOO10liO45516w(0) <= NOT niOO10liO; + wire_w_lg_niOO10lll45518w(0) <= NOT niOO10lll; + wire_w_lg_niOO10llO45512w(0) <= NOT niOO10llO; + wire_w_lg_niOO10lOi45514w(0) <= NOT niOO10lOi; + wire_w_lg_niOO10lOO8902w(0) <= NOT niOO10lOO; + wire_w_lg_niOO10O0i59411w(0) <= NOT niOO10O0i; + wire_w_lg_niOO10O0O43993w(0) <= NOT niOO10O0O; + wire_w_lg_niOO10O1l8900w(0) <= NOT niOO10O1l; + wire_w_lg_niOO10Oii8785w(0) <= NOT niOO10Oii; + wire_w_lg_niOO10Oil8776w(0) <= NOT niOO10Oil; + wire_w_lg_niOO10OiO8767w(0) <= NOT niOO10OiO; + wire_w_lg_niOO10OOi46502w(0) <= NOT niOO10OOi; + wire_w_lg_niOO1i11l8582w(0) <= NOT niOO1i11l; + wire_w_lg_niOO1i11O8580w(0) <= NOT niOO1i11O; + wire_w_lg_niOO1iiil8542w(0) <= NOT niOO1iiil; + wire_w_lg_niOO1iiiO8535w(0) <= NOT niOO1iiiO; + wire_w_lg_niOO1iili8527w(0) <= NOT niOO1iili; + wire_w_lg_niOO1iill8519w(0) <= NOT niOO1iill; + wire_w_lg_niOO1iilO8511w(0) <= NOT niOO1iilO; + wire_w_lg_niOO1iiOl8493w(0) <= NOT niOO1iiOl; + wire_w_lg_niOO1iiOO8486w(0) <= NOT niOO1iiOO; + wire_w_lg_niOO1il0i8435w(0) <= NOT niOO1il0i; + wire_w_lg_niOO1il0l8423w(0) <= NOT niOO1il0l; + wire_w_lg_niOO1il0O8417w(0) <= NOT niOO1il0O; + wire_w_lg_niOO1il1i8479w(0) <= NOT niOO1il1i; + wire_w_lg_niOO1il1l8472w(0) <= NOT niOO1il1l; + wire_w_lg_niOO1ilii8410w(0) <= NOT niOO1ilii; + wire_w_lg_niOO1ilil8403w(0) <= NOT niOO1ilil; + wire_w_lg_niOO1iliO8391w(0) <= NOT niOO1iliO; + wire_w_lg_niOO1illi8383w(0) <= NOT niOO1illi; + wire_w_lg_niOO1illl8375w(0) <= NOT niOO1illl; + wire_w_lg_niOO1illO8367w(0) <= NOT niOO1illO; + wire_w_lg_niOO1ilOi8360w(0) <= NOT niOO1ilOi; + wire_w_lg_niOO1ilOl8352w(0) <= NOT niOO1ilOl; + wire_w_lg_niOO1ilOO8344w(0) <= NOT niOO1ilOO; + wire_w_lg_niOO1iO0i8312w(0) <= NOT niOO1iO0i; + wire_w_lg_niOO1iO0l8304w(0) <= NOT niOO1iO0l; + wire_w_lg_niOO1iO0O8297w(0) <= NOT niOO1iO0O; + wire_w_lg_niOO1iO1i8336w(0) <= NOT niOO1iO1i; + wire_w_lg_niOO1iO1l8328w(0) <= NOT niOO1iO1l; + wire_w_lg_niOO1iO1O8320w(0) <= NOT niOO1iO1O; + wire_w_lg_niOO1iOii8290w(0) <= NOT niOO1iOii; + wire_w_lg_niOO1iOil8283w(0) <= NOT niOO1iOil; + wire_w_lg_niOO1iOiO8276w(0) <= NOT niOO1iOiO; + wire_w_lg_niOO1iOli8269w(0) <= NOT niOO1iOli; + wire_w_lg_niOO1iOll8262w(0) <= NOT niOO1iOll; + wire_w_lg_niOO1iOlO8255w(0) <= NOT niOO1iOlO; + wire_w_lg_niOO1iOOl8224w(0) <= NOT niOO1iOOl; + wire_w_lg_niOO1iOOO8222w(0) <= NOT niOO1iOOO; + wire_w_lg_niOO1l00l7950w(0) <= NOT niOO1l00l; + wire_w_lg_niOO1l00O7936w(0) <= NOT niOO1l00O; + wire_w_lg_niOO1l01i8004w(0) <= NOT niOO1l01i; + wire_w_lg_niOO1l01O7992w(0) <= NOT niOO1l01O; + wire_w_lg_niOO1l0ii7929w(0) <= NOT niOO1l0ii; + wire_w_lg_niOO1l0il7922w(0) <= NOT niOO1l0il; + wire_w_lg_niOO1l0iO7915w(0) <= NOT niOO1l0iO; + wire_w_lg_niOO1l0li7908w(0) <= NOT niOO1l0li; + wire_w_lg_niOO1l0ll7901w(0) <= NOT niOO1l0ll; + wire_w_lg_niOO1l0Oi7894w(0) <= NOT niOO1l0Oi; + wire_w_lg_niOO1l0OO7876w(0) <= NOT niOO1l0OO; + wire_w_lg_niOO1l10l8179w(0) <= NOT niOO1l10l; + wire_w_lg_niOO1l10O8173w(0) <= NOT niOO1l10O; + wire_w_lg_niOO1l11l8204w(0) <= NOT niOO1l11l; + wire_w_lg_niOO1l11O8198w(0) <= NOT niOO1l11O; + wire_w_lg_niOO1l1il8145w(0) <= NOT niOO1l1il; + wire_w_lg_niOO1l1iO8136w(0) <= NOT niOO1l1iO; + wire_w_lg_niOO1l1ll8060w(0) <= NOT niOO1l1ll; + wire_w_lg_niOO1l1lO8035w(0) <= NOT niOO1l1lO; + wire_w_lg_niOO1l1Ol8018w(0) <= NOT niOO1l1Ol; + wire_w_lg_niOO1l1OO8011w(0) <= NOT niOO1l1OO; + wire_w_lg_niOO1li0i35176w(0) <= NOT niOO1li0i; + wire_w_lg_niOO1li1l7858w(0) <= NOT niOO1li1l; + wire_w_lg_niOO1li1O7856w(0) <= NOT niOO1li1O; + wire_w_lg_niOO1liiO7821w(0) <= NOT niOO1liiO; + wire_w_lg_niOO1lill7803w(0) <= NOT niOO1lill; + wire_w_lg_niOO1lilO7801w(0) <= NOT niOO1lilO; + wire_w_lg_niOO1ll0i7747w(0) <= NOT niOO1ll0i; + wire_w_lg_niOO1ll0l7739w(0) <= NOT niOO1ll0l; + wire_w_lg_niOO1ll0O7731w(0) <= NOT niOO1ll0O; + wire_w_lg_niOO1ll1i7768w(0) <= NOT niOO1ll1i; + wire_w_lg_niOO1ll1l7762w(0) <= NOT niOO1ll1l; + wire_w_lg_niOO1ll1O7755w(0) <= NOT niOO1ll1O; + wire_w_lg_niOO1llii7723w(0) <= NOT niOO1llii; + wire_w_lg_niOO1llil7716w(0) <= NOT niOO1llil; + wire_w_lg_niOO1lliO7709w(0) <= NOT niOO1lliO; + wire_w_lg_niOO1llli7701w(0) <= NOT niOO1llli; + wire_w_lg_niOO1llll7693w(0) <= NOT niOO1llll; + wire_w_lg_niOO1lllO7685w(0) <= NOT niOO1lllO; + wire_w_lg_niOO1llOl7599w(0) <= NOT niOO1llOl; + wire_w_lg_niOO1llOO7572w(0) <= NOT niOO1llOO; + wire_w_lg_niOO1lO0O7361w(0) <= NOT niOO1lO0O; + wire_w_lg_niOO1lO1i7566w(0) <= NOT niOO1lO1i; + wire_w_lg_niOO1lO1l7559w(0) <= NOT niOO1lO1l; + wire_w_lg_niOO1lOii7359w(0) <= NOT niOO1lOii; + wire_w_lg_niOO1lOli7233w(0) <= NOT niOO1lOli; + wire_w_lg_niOO1lOll7231w(0) <= NOT niOO1lOll; + wire_w_lg_niOO1Oi0i6385w(0) <= NOT niOO1Oi0i; + wire_w_lg_niOO1Oi0l6383w(0) <= NOT niOO1Oi0l; + wire_w_lg_niOO1Oiii6365w(0) <= NOT niOO1Oiii; + wire_w_lg_niOO1Oiil6359w(0) <= NOT niOO1Oiil; + wire_w_lg_niOO1OiiO6118w(0) <= NOT niOO1OiiO; + wire_w_lg_niOO1Oili6120w(0) <= NOT niOO1Oili; + wire_w_lg_niOO1Ol0i6088w(0) <= NOT niOO1Ol0i; + wire_w_lg_niOO1Ol0O6083w(0) <= NOT niOO1Ol0O; + wire_w_lg_niOO1Ol1i6094w(0) <= NOT niOO1Ol1i; + wire_w_lg_niOO1Ol1l6095w(0) <= NOT niOO1Ol1l; + wire_w_lg_niOO1Olii6076w(0) <= NOT niOO1Olii; + wire_w_lg_niOO1OliO6074w(0) <= NOT niOO1OliO; + wire_w_lg_niOO1Olll6072w(0) <= NOT niOO1Olll; + wire_w_lg_niOO1OlOi5992w(0) <= NOT niOO1OlOi; + wire_w_lg_niOO1OlOl5996w(0) <= NOT niOO1OlOl; + wire_w_lg_niOO1OlOO5989w(0) <= NOT niOO1OlOO; + wire_w_lg_niOO1OO1i5988w(0) <= NOT niOO1OO1i; + wire_w_lg_niOO1OO1l6182w(0) <= NOT niOO1OO1l; + wire_w_lg_tx_eop_vc0_04425w(0) <= NOT tx_eop_vc0_0; + wire_w_lg_tx_eop_vc1_02590w(0) <= NOT tx_eop_vc1_0; + wire_w_lg_tx_err_vc04036w(0) <= NOT tx_err_vc0; + wire_w_lg_tx_err_vc12419w(0) <= NOT tx_err_vc1; + wire_w_lg_tx_sop_vc0_04025w(0) <= NOT tx_sop_vc0_0; + wire_w_lg_tx_sop_vc0_14026w(0) <= NOT tx_sop_vc0_1; + wire_w_lg_tx_sop_vc1_02407w(0) <= NOT tx_sop_vc1_0; + wire_w_lg_tx_sop_vc1_12408w(0) <= NOT tx_sop_vc1_1; + wire_w_lg_w_k_bar_range45712w45713w(0) <= NOT wire_w_k_bar_range45712w(0); + wire_w_lg_w_k_bar_range45915w45916w(0) <= NOT wire_w_k_bar_range45915w(0); + wire_w_lg_w_k_bar_range45913w45914w(0) <= NOT wire_w_k_bar_range45913w(0); + wire_w_lg_w_k_bar_range47787w47788w(0) <= NOT wire_w_k_bar_range47787w(0); + wire_w_lg_w_k_bar_range45710w45711w(0) <= NOT wire_w_k_bar_range45710w(0); + wire_w_lg_w_k_bar_range45818w45819w(0) <= NOT wire_w_k_bar_range45818w(0); + wire_w_lg_w_k_bar_range45930w45931w(0) <= NOT wire_w_k_bar_range45930w(0); + wire_w_lg_w_k_bar_range51119w51288w(0) <= NOT wire_w_k_bar_range51119w(0); + wire_w_lg_w_k_bar_range45805w45806w(0) <= NOT wire_w_k_bar_range45805w(0); + wire_w_lg_w_k_bar_range45803w45804w(0) <= NOT wire_w_k_bar_range45803w(0); + wire_w_lg_w_k_bar_range47798w47799w(0) <= NOT wire_w_k_bar_range47798w(0); + wire_w_lg_w_k_conf_range44263w44264w(0) <= NOT wire_w_k_conf_range44263w(0); + wire_w_lg_w_k_conf_range1869w46186w(0) <= NOT wire_w_k_conf_range1869w(0); + wire_w_lg_w_k_conf_range46173w46174w(0) <= NOT wire_w_k_conf_range46173w(0); + wire_w_lg_w_k_conf_range9950w9951w(0) <= NOT wire_w_k_conf_range9950w(0); + wire_w_lg_w_k_dev_range52047w52497w(0) <= NOT wire_w_k_dev_range52047w(0); + wire_w_lg_w_k_gbl_hip_range25481w25482w(0) <= NOT wire_w_k_gbl_hip_range25481w(0); + wire_w_lg_w_k_gbl_hip_range1050w1051w(0) <= NOT wire_w_k_gbl_hip_range1050w(0); + wire_w_lg_w_k_gbl_hip_range23582w23583w(0) <= NOT wire_w_k_gbl_hip_range23582w(0); + wire_w_lg_w_k_hip_range2413w2429w(0) <= NOT wire_w_k_hip_range2413w(0); + wire_w_lg_w_mode_range8897w9838w(0) <= NOT wire_w_mode_range8897w(0); + wire_w_lg_w_test_in_hip_range61747w61748w(0) <= NOT wire_w_test_in_hip_range61747w(0); + wire_w_lg_w_test_in_hip_range61717w61725w(0) <= NOT wire_w_test_in_hip_range61717w(0); + wire_w_lg_w_tx_data_vc0_0_range4011w4012w(0) <= NOT wire_w_tx_data_vc0_0_range4011w(0); + wire_w_lg_w_tx_data_vc0_0_range4013w4014w(0) <= NOT wire_w_tx_data_vc0_0_range4013w(0); + wire_w_lg_w_tx_data_vc0_0_range4016w4017w(0) <= NOT wire_w_tx_data_vc0_0_range4016w(0); + wire_w_lg_w_tx_data_vc0_0_range4008w4009w(0) <= NOT wire_w_tx_data_vc0_0_range4008w(0); + wire_w_lg_w_tx_data_vc0_0_range4005w4006w(0) <= NOT wire_w_tx_data_vc0_0_range4005w(0); + wire_w_lg_w_tx_data_vc1_0_range2393w2394w(0) <= NOT wire_w_tx_data_vc1_0_range2393w(0); + wire_w_lg_w_tx_data_vc1_0_range2395w2396w(0) <= NOT wire_w_tx_data_vc1_0_range2395w(0); + wire_w_lg_w_tx_data_vc1_0_range2398w2399w(0) <= NOT wire_w_tx_data_vc1_0_range2398w(0); + wire_w_lg_w_tx_data_vc1_0_range2390w2391w(0) <= NOT wire_w_tx_data_vc1_0_range2390w(0); + wire_w_lg_w_tx_data_vc1_0_range2387w2388w(0) <= NOT wire_w_tx_data_vc1_0_range2387w(0); + wire_w20916w(0) <= wire_w_lg_w_lg_w_lg_niOl0l1OO20911w20912w20913w(0) OR wire_w_lg_w_lg_niOl0Oiii20898w20915w(0); + wire_w35817w(0) <= wire_w_lg_w_lg_w_lg_niOiOiO0l35813w35815w35816w(0) OR wire_nlOiO010O_dataout; + wire_w35805w(0) <= wire_w_lg_w_lg_w_lg_niOiOiOii35801w35803w35804w(0) OR wire_nlOiO01li_dataout; + wire_w_lg_w_lg_w_lg_w_k_hip_range2413w5661w5662w5668w(0) <= wire_w_lg_w_lg_w_k_hip_range2413w5661w5662w(0) OR wire_w_lg_w_lg_w_k_hip_range2413w5663w5667w(0); + wire_w_lg_w_lg_w_lg_niOi001iO53573w53578w53580w(0) <= wire_w_lg_w_lg_niOi001iO53573w53578w(0) OR wire_w_lg_w_lg_niOi001iO53573w53579w(0); + wire_w_lg_w_lg_w_lg_niOl0Oiii20898w20899w20900w(0) <= wire_w_lg_w_lg_niOl0Oiii20898w20899w(0) OR niOl0Oiii; + wire_w_lg_w_lg_w_lg_niOl0Ol0i21223w23872w23873w(0) <= wire_w_lg_w_lg_niOl0Ol0i21223w23872w(0) OR nlOlliOOO; + wire_w_lg_w_lg_w_lg_niOi1Olii54871w54872w54873w(0) <= wire_w_lg_w_lg_niOi1Olii54871w54872w(0) OR niOi1Ol0i; + wire_w_lg_w_lg_niOiOilii35902w35908w(0) <= wire_w_lg_niOiOilii35902w(0) OR wire_w_lg_niOiOiO1l35907w(0); + wire_w_lg_w_lg_niOliii0l18289w18291w(0) <= wire_w_lg_niOliii0l18289w(0) OR wire_w_lg_niOliii1l18290w(0); + wire_w_lg_w_lg_niOliil0l18156w18157w(0) <= wire_w_lg_niOliil0l18156w(0) OR niOliiiOi; + wire_w_lg_w_lg_niOlill0i17382w17384w(0) <= wire_w_lg_niOlill0i17382w(0) OR wire_w_lg_niOlill1i17383w(0); + wire_w_lg_w_lg_niOlilO0i17249w17250w(0) <= wire_w_lg_niOlilO0i17249w(0) OR niOlilllO; + wire_w_lg_w_lg_niOliOO1O16475w16477w(0) <= wire_w_lg_niOliOO1O16475w(0) OR wire_w_lg_niOliOlOO16476w(0); + wire_w_lg_w_lg_niOll001l15435w15436w(0) <= wire_w_lg_niOll001l15435w(0) OR niOll01li; + wire_w_lg_w_lg_niOll011l15568w15570w(0) <= wire_w_lg_niOll011l15568w(0) OR wire_w_lg_niOll1OOl15569w(0); + wire_w_lg_w_lg_niOll111O16342w16343w(0) <= wire_w_lg_niOll111O16342w(0) OR niOliOOll; + wire_w_lg_w_lg_niOlli01i14661w14663w(0) <= wire_w_lg_niOlli01i14661w(0) OR wire_w_lg_niOlli1Oi14662w(0); + wire_w_lg_w_lg_niOllii1i14528w14529w(0) <= wire_w_lg_niOllii1i14528w(0) OR niOlli0iO; + wire_w_lg_w_lg_niOlll0OO13754w13756w(0) <= wire_w_lg_niOlll0OO13754w(0) OR wire_w_lg_niOlll0lO13755w(0); + wire_w_lg_w_lg_niOllliOO13621w13622w(0) <= wire_w_lg_niOllliOO13621w(0) OR niOllliil; + wire_w_lg_w_lg_niOllOiOl12847w12849w(0) <= wire_w_lg_niOllOiOl12847w(0) OR wire_w_lg_niOllOill12848w(0); + wire_w_lg_w_lg_niOllOlOl12714w12715w(0) <= wire_w_lg_niOllOlOl12714w(0) OR niOllOlii; + wire_w_lg_w_lg_niOlO1lOi11936w11938w(0) <= wire_w_lg_niOlO1lOi11936w(0) OR wire_w_lg_niOlO1lli11937w(0); + wire_w_lg_w_lg_niOlO1OOl11803w11804w(0) <= wire_w_lg_niOlO1OOl11803w(0) OR niOlO1Oii; + wire_w_lg_w_lg_niOO00l0i4100w4103w(0) <= wire_w_lg_niOO00l0i4100w(0) OR wire_nl1000i_w_lg_n1l000O4102w(0); + wire_w_lg_w_lg_niOO00lli4305w4306w(0) <= wire_w_lg_niOO00lli4305w(0) OR wire_nlll0lli_w_q_range4087w(0); + wire_w_lg_w_lg_niOO01lll5093w5094w(0) <= wire_w_lg_niOO01lll5093w(0) OR niOO01llO; + wire_w_lg_w_lg_niOO0l00O2566w2567w(0) <= wire_w_lg_niOO0l00O2566w(0) OR wire_n0OOO0O_w_q_range2464w(0); + wire_w_lg_w_lg_niOO0l01l2477w2480w(0) <= wire_w_lg_niOO0l01l2477w(0) OR wire_ni1lOlO_w_lg_ni1lOll2479w(0); + wire_w_lg_w_lg_w_k_conf_range1869w46275w51906w(0) <= wire_w_lg_w_k_conf_range1869w46275w(0) OR wire_w_lg_w_lg_w_k_conf_range1869w46186w46226w(0); + wire_w_lg_w_lg_niOi000lO53415w53448w(0) <= wire_w_lg_niOi000lO53415w(0) OR wire_nli1lli0i_w_lg_dataout53447w(0); + wire_w_lg_w_lg_niOi0010i53645w53646w(0) <= wire_w_lg_niOi0010i53645w(0) OR niOi0011O; + wire_w_lg_w_lg_niOi0010l53612w53621w(0) <= wire_w_lg_niOi0010l53612w(0) OR wire_nilOiOlO_w_lg_w_lg_w_lg_dataout49188w53619w53620w(0); + wire_w_lg_w_lg_niOi1ii1O58911w58926w(0) <= wire_w_lg_niOi1ii1O58911w(0) OR wire_w_lg_niOi1i0OO58925w(0); + wire_w_lg_w_lg_niOi1iiii58803w58930w(0) <= wire_w_lg_niOi1iiii58803w(0) OR wire_w_lg_niOi1i0Ol58929w(0); + wire_w_lg_w_lg_niOi1iill58695w58934w(0) <= wire_w_lg_niOi1iill58695w(0) OR wire_w_lg_niOi1i0Oi58933w(0); + wire_w_lg_w_lg_niOilOi1O43404w43986w(0) <= wire_w_lg_niOilOi1O43404w(0) OR niOilOi0l; + wire_w_lg_w_lg_niOiOilii35903w35906w(0) <= wire_w_lg_niOiOilii35903w(0) OR wire_w_lg_niOiOiO0i35905w(0); + wire_w_lg_w_lg_niOiOiliO35913w35916w(0) <= wire_w_lg_niOiOiliO35913w(0) OR wire_w_lg_niOiOiO0O35915w(0); + wire_w_lg_w_lg_niOl0Ol0l24926w24927w(0) <= wire_w_lg_niOl0Ol0l24926w(0) OR nlOlliOOO; + wire_w_lg_w_lg_niOli0iil18989w19425w(0) <= wire_w_lg_niOli0iil18989w(0) OR n1lilO0l; + wire_w_lg_w_lg_w_k_conf_range44263w44264w44269w(0) <= wire_w_lg_w_k_conf_range44263w44264w(0) OR niOillliO; + wire_w_lg_w_lg_w_k_hip_range2413w2429w3333w(0) <= wire_w_lg_w_k_hip_range2413w2429w(0) OR wire_w_lg_w_lg_w_k_hip_range2413w3330w3332w(0); + wire_w_lg_w_lg_w_k_hip_range2413w2429w5225w(0) <= wire_w_lg_w_k_hip_range2413w2429w(0) OR wire_w_lg_w_lg_w_k_hip_range2413w5220w5224w(0); + wire_w_lg_w35817w35818w(0) <= wire_w35817w(0) OR wire_nlOiO010l_dataout; + wire_w_lg_w35805w35806w(0) <= wire_w35805w(0) OR wire_nlOiO01iO_dataout; + wire_w5671w(0) <= wire_w_lg_w_lg_w_lg_w_k_hip_range2413w5661w5662w5668w(0) OR wire_w_lg_w_lg_w_lg_w_k_hip_range2413w2429w5669w5670w(0); + wire_w53583w(0) <= wire_w_lg_w_lg_w_lg_niOi001iO53573w53578w53580w(0) OR wire_w_lg_niOi001iO53582w(0); + wire_w_lg_w_lg_w_lg_niOiOilii35902w35908w35912w(0) <= wire_w_lg_w_lg_niOiOilii35902w35908w(0) OR wire_w_lg_niOiOiliO35911w(0); + wire_w_lg_w_lg_w_lg_niOliil0l18156w18157w18158w(0) <= wire_w_lg_w_lg_niOliil0l18156w18157w(0) OR niOliiilO; + wire_w_lg_w_lg_w_lg_niOlilO0i17249w17250w17251w(0) <= wire_w_lg_w_lg_niOlilO0i17249w17250w(0) OR niOlillll; + wire_w_lg_w_lg_w_lg_niOll001l15435w15436w15437w(0) <= wire_w_lg_w_lg_niOll001l15435w15436w(0) OR niOll01iO; + wire_w_lg_w_lg_w_lg_niOll111O16342w16343w16344w(0) <= wire_w_lg_w_lg_niOll111O16342w16343w(0) OR niOliOOli; + wire_w_lg_w_lg_w_lg_niOllii1i14528w14529w14530w(0) <= wire_w_lg_w_lg_niOllii1i14528w14529w(0) OR niOlli0il; + wire_w_lg_w_lg_w_lg_niOllliOO13621w13622w13623w(0) <= wire_w_lg_w_lg_niOllliOO13621w13622w(0) OR niOllliii; + wire_w_lg_w_lg_w_lg_niOllOlOl12714w12715w12716w(0) <= wire_w_lg_w_lg_niOllOlOl12714w12715w(0) OR niOllOl0O; + wire_w_lg_w_lg_w_lg_niOlO1OOl11803w11804w11805w(0) <= wire_w_lg_w_lg_niOlO1OOl11803w11804w(0) OR niOlO1O0O; + wire_w_lg_w_lg_w_lg_niOO00l0i4100w4103w4104w(0) <= wire_w_lg_w_lg_niOO00l0i4100w4103w(0) OR wire_nl1000i_w_lg_n1l000O4060w(0); + wire_w_lg_w_lg_w_lg_niOO0l01l2477w2480w2481w(0) <= wire_w_lg_w_lg_niOO0l01l2477w2480w(0) OR wire_ni1lOlO_w_lg_ni1lOll2437w(0); + wire_w_lg_w_lg_w_lg_niOi1ii1O58911w58926w58927w(0) <= wire_w_lg_w_lg_niOi1ii1O58911w58926w(0) OR nl10llill; + wire_w_lg_w_lg_w_lg_niOi1iiii58803w58930w58931w(0) <= wire_w_lg_w_lg_niOi1iiii58803w58930w(0) OR nl10llili; + wire_w_lg_w_lg_w_lg_niOi1iill58695w58934w58935w(0) <= wire_w_lg_w_lg_niOi1iill58695w58934w(0) OR nl10lliiO; + wire_w_lg_w_lg_w_lg_niOli0iil18989w19425w19426w(0) <= wire_w_lg_w_lg_niOli0iil18989w19425w(0) OR n1lilO0i; + wire_w44270w(0) <= wire_w_lg_w_lg_w_k_conf_range44263w44264w44269w(0) OR niOilllil; + wire_w_lg_w53583w53586w(0) <= wire_w53583w(0) OR wire_nl01illOl_w_lg_o53585w(0); + wire_w35918w(0) <= wire_w_lg_w_lg_w_lg_niOiOilii35902w35908w35912w(0) OR wire_nl1000i_w_lg_nllilOlOi35917w(0); + wire_w_lg_w44270w44271w(0) <= wire_w44270w(0) OR niOilllii; + wire_w_lg_w_lg_w53583w53586w53589w(0) <= wire_w_lg_w53583w53586w(0) OR wire_nl01l1OOl_w_lg_w_lg_dataout53587w53588w(0); + wire_w_lg_w_lg_w44270w44271w44272w(0) <= wire_w_lg_w44270w44271w(0) OR niOilll0O; + wire_w_lg_w_lg_w_lg_w53583w53586w53589w53593w(0) <= wire_w_lg_w_lg_w53583w53586w53589w(0) OR wire_nlill0Oll_w_lg_w_lg_nl01l0llO53591w53592w(0); + wire_w_lg_w_lg_w_lg_w42915w42916w42917w42918w(0) <= wire_w_lg_w_lg_w42915w42916w42917w(0) OR niOiO101i; + wire_w_lg_w_lg_w42915w42916w42917w(0) <= wire_w_lg_w42915w42916w(0) OR niOiO101l; + wire_w_lg_w42915w42916w(0) <= wire_w42915w(0) OR niOiO101O; + wire_w42915w(0) <= wire_w_lg_w_lg_w_lg_niOiO10il42912w42913w42914w(0) OR niOiO100i; + wire_w42246w(0) <= wire_w_lg_w_lg_w_lg_niOiO1Oii42243w42244w42245w(0) OR niOiO1Oli; + wire_w_lg_w_lg_w_lg_niOiO10il42912w42913w42914w(0) <= wire_w_lg_w_lg_niOiO10il42912w42913w(0) OR niOiO100l; + wire_w_lg_w_lg_w_lg_niOiO1Oii42243w42244w42245w(0) <= wire_w_lg_w_lg_niOiO1Oii42243w42244w(0) OR niOiO1OiO; + wire_w_lg_w_lg_w_lg_niOl0ilOl20972w20973w20974w(0) <= wire_w_lg_w_lg_niOl0ilOl20972w20973w(0) OR niOl0illl; + wire_w_lg_w_lg_niOi00Oii53617w53618w(0) <= wire_w_lg_niOi00Oii53617w(0) OR niOi00O0O; + wire_w_lg_w_lg_niOi10l0O60203w60205w(0) <= wire_w_lg_niOi10l0O60203w(0) OR wire_nlill0Oll_w_lg_nl11OO0li60204w(0); + wire_w_lg_w_lg_niOi1i01O59406w59407w(0) <= wire_w_lg_niOi1i01O59406w(0) OR niOi1i01l; + wire_w_lg_w_lg_niOiil0Ol48209w48210w(0) <= wire_w_lg_niOiil0Ol48209w(0) OR niOiil0Oi; + wire_w_lg_w_lg_niOiO10il42912w42913w(0) <= wire_w_lg_niOiO10il42912w(0) OR niOiO100O; + wire_w_lg_w_lg_niOiO1Oii42243w42244w(0) <= wire_w_lg_niOiO1Oii42243w(0) OR niOiO1Oil; + wire_w_lg_w_lg_niOl0ilOl20972w20973w(0) <= wire_w_lg_niOl0ilOl20972w(0) OR niOl0illO; + wire_w_lg_w_lg_niOl0O1iO20894w20895w(0) <= wire_w_lg_niOl0O1iO20894w(0) OR niOl0l0iO; + wire_w_lg_w_lg_niOl0O1li20824w20825w(0) <= wire_w_lg_niOl0O1li20824w(0) OR niOl0O1il; + wire_w_lg_w_lg_niOlii0lO18269w18270w(0) <= wire_w_lg_niOlii0lO18269w(0) OR niOlii0li; + wire_w_lg_w_lg_niOlilill17362w17363w(0) <= wire_w_lg_niOlilill17362w(0) OR niOliliiO; + wire_w_lg_w_lg_niOliOlli16455w16456w(0) <= wire_w_lg_niOliOlli16455w(0) OR niOliOlil; + wire_w_lg_w_lg_niOll1OiO15548w15549w(0) <= wire_w_lg_niOll1OiO15548w(0) OR niOll1Oii; + wire_w_lg_w_lg_niOlli1il14641w14642w(0) <= wire_w_lg_niOlli1il14641w(0) OR niOlli10O; + wire_w_lg_w_lg_niOlll0ii13734w13735w(0) <= wire_w_lg_niOlll0ii13734w(0) OR niOlll00l; + wire_w_lg_w_lg_niOllOi0O12827w12828w(0) <= wire_w_lg_niOllOi0O12827w(0) OR niOllOi0i; + wire_w_lg_w_lg_niOlO1l0l11916w11917w(0) <= wire_w_lg_niOlO1l0l11916w(0) OR niOlO1l1O; + wire_w_lg_w_lg_w_k_bar_range45805w51984w51987w(0) <= wire_w_lg_w_k_bar_range45805w51984w(0) OR wire_w_lg_w_k_bar_range47798w51986w(0); + wire_w_lg_niOi00O1i53214w(0) <= niOi00O1i OR niOi00lOO; + wire_w_lg_niOi00Oii53617w(0) <= niOi00Oii OR niOi0lOli; + wire_w_lg_niOi00OOO53184w(0) <= niOi00OOO OR niOi00OOl; + wire_w_lg_niOi0lOii53444w(0) <= niOi0lOii OR wire_w_lg_niOi000lO53415w(0); + wire_w_lg_niOi10l0O60203w(0) <= niOi10l0O OR nl11OO0ll; + wire_w_lg_niOi1i01O59406w(0) <= niOi1i01O OR wire_nlill0Oll_w_lg_nl10iOOli59405w(0); + wire_w_lg_niOi1Olii54871w(0) <= niOi1Olii OR niOi1Ol0O; + wire_w_lg_niOi1OO1i54726w(0) <= niOi1OO1i OR wire_nl1lOOl0l_w_lg_dataout54725w(0); + wire_w_lg_niOiil0Ol48209w(0) <= niOiil0Ol OR niOiil0OO; + wire_w_lg_niOiiO00O47759w(0) <= niOiiO00O OR wire_nlill0Oll_w_lg_w47757w47758w(0); + wire_w_lg_niOiiO0lO47741w(0) <= niOiiO0lO OR wire_nlill0Oll_w_lg_nl0OiOl0l47740w(0); + wire_w_lg_niOilOO0l44001w(0) <= niOilOO0l OR nlil00ill; + wire_w_lg_niOiO10il42912w(0) <= niOiO10il OR niOiO10ii; + wire_w_lg_niOiO1lOl42295w(0) <= niOiO1lOl OR wire_nlillllOO_w_lg_o42294w(0); + wire_w_lg_niOiO1O0O42242w(0) <= niOiO1O0O OR wire_nl1000i_w_lg_nlilOO0ll42241w(0); + wire_w_lg_niOiO1Oii42243w(0) <= niOiO1Oii OR wire_w_lg_niOiO1O0O42242w(0); + wire_w_lg_niOiOil0l35920w(0) <= niOiOil0l OR wire_w_lg_niOiOil0O35919w(0); + wire_w_lg_niOiOil0O35919w(0) <= niOiOil0O OR wire_w35918w(0); + wire_w_lg_niOiOilOO35904w(0) <= niOiOilOO OR niOiOil0i; + wire_w_lg_niOiOiO0i35905w(0) <= niOiOiO0i OR wire_w_lg_niOiOilOO35904w(0); + wire_w_lg_niOiOiO0O35915w(0) <= niOiOiO0O OR wire_w_lg_niOiOiO1l35914w(0); + wire_w_lg_niOiOiO1l35914w(0) <= niOiOiO1l OR niOiOil1O; + wire_w_lg_niOiOl0li34626w(0) <= niOiOl0li OR wire_nl1000i_w_lg_nlll0101l34625w(0); + wire_w_lg_niOl0il0O20992w(0) <= niOl0il0O OR wire_w_lg_niOl0il1O20991w(0); + wire_w_lg_niOl0ilOl20972w(0) <= niOl0ilOl OR niOl0ilOi; + wire_w_lg_niOl0O1iO20894w(0) <= niOl0O1iO OR niOl0O1il; + wire_w_lg_niOl0O1li20824w(0) <= niOl0O1li OR niOl0O1iO; + wire_w_lg_niOl0Ol0l23874w(0) <= niOl0Ol0l OR wire_w_lg_w_lg_w_lg_niOl0Ol0i21223w23872w23873w(0); + wire_w_lg_niOli11il20299w(0) <= niOli11il OR niOli111O; + wire_w_lg_niOli1OiO23876w(0) <= niOli1OiO OR wire_nlOii0l0O_w_lg_dataout23875w(0); + wire_w_lg_niOlii0lO18269w(0) <= niOlii0lO OR niOlii0ll; + wire_w_lg_niOlilill17362w(0) <= niOlilill OR niOlilili; + wire_w_lg_niOliOlli16455w(0) <= niOliOlli OR niOliOliO; + wire_w_lg_niOll1OiO15548w(0) <= niOll1OiO OR niOll1Oil; + wire_w_lg_niOlli1il14641w(0) <= niOlli1il OR niOlli1ii; + wire_w_lg_niOlll0ii13734w(0) <= niOlll0ii OR niOlll00O; + wire_w_lg_niOllOi0O12827w(0) <= niOllOi0O OR niOllOi0l; + wire_w_lg_niOlO1l0l11916w(0) <= niOlO1l0l OR niOlO1l0i; + wire_w_lg_niOO00iii4313w(0) <= niOO00iii OR wire_w_lg_niOO00ill4312w(0); + wire_w_lg_niOO00lll4047w(0) <= niOO00lll OR wire_nl1000i_w_lg_n1l010i4042w(0); + wire_w_lg_niOO010li5677w(0) <= niOO010li OR wire_nl1000i_w_lg_w_lg_nll0OilO5675w5676w(0); + wire_w_lg_niOO01lil5707w(0) <= niOO01lil OR wire_nl1000i_w_lg_w_lg_nllilO1i5110w5706w(0); + wire_w_lg_niOO01llO5097w(0) <= niOO01llO OR wire_w_lg_niOO01lll5096w(0); + wire_w_lg_niOO0il1l3392w(0) <= niOO0il1l OR wire_ni1lOlO_w_lg_w_lg_n0Ol11i3240w3391w(0); + wire_w_lg_niOO10lOO23891w(0) <= niOO10lOO OR wire_nlOii0l0O_w_lg_dataout21190w(0); + wire_w_lg_niOO10lOO23893w(0) <= niOO10lOO OR wire_w_lg_niOli1OiO23494w(0); + wire_w_lg_w_k_bar_range45712w51983w(0) <= wire_w_k_bar_range45712w(0) OR wire_w_lg_w_k_bar_range51119w51982w(0); + wire_w_lg_w_k_bar_range45915w51988w(0) <= wire_w_k_bar_range45915w(0) OR wire_w_lg_w_lg_w_k_bar_range45805w51984w51987w(0); + wire_w_lg_w_k_bar_range45805w51984w(0) <= wire_w_k_bar_range45805w(0) OR wire_w_lg_w_k_bar_range45712w51983w(0); + wire_w_lg_w_k_gbl_hip_range1050w3226w(0) <= wire_w_k_gbl_hip_range1050w(0) OR wire_niO01O0O_dataout; + wire_w_lg_w_k_gbl_hip_range23582w23621w(0) <= wire_w_k_gbl_hip_range23582w(0) OR wire_niO01ill_w_lg_nlOO0iilO20976w(0); + wire_w_lg_niOil0lil51645w(0) <= niOil0lil XOR niOii0i1O; + wire_w_lg_niOil11lO49874w(0) <= niOil11lO XOR niOiiiiOO; + wire_w_lg_niOil1Oli50758w(0) <= niOil1Oli XOR niOiii11l; + wire_w_lg_niOl10l0l28505w(0) <= niOl10l0l XOR nlOil01iO; + wire_w_lg_niOl10l1O28513w(0) <= niOl10l1O XOR nlOil1OlO; + wire_w_lg_niOl10O0l28328w(0) <= niOl10O0l XOR nlOill1ll; + wire_w_lg_niOl10Oii28320w(0) <= niOl10Oii XOR nlOill0il; + wire_w_lg_w_cpl_err_range8533w8536w(0) <= wire_w_cpl_err_range8533w(0) XOR niOlOOOl; + wire_w_lg_w_cpl_err_range8525w8528w(0) <= wire_w_cpl_err_range8525w(0) XOR niOO10ii; + wire_w_lg_w_cpl_err_range8517w8520w(0) <= wire_w_cpl_err_range8517w(0) XOR niOO1iOO; + wire_w_lg_w_cpl_err_range8509w8512w(0) <= wire_w_cpl_err_range8509w(0) XOR niOO1Oil; + wire_w_lg_w_dl_req_phycfg_range7707w7710w(0) <= wire_w_dl_req_phycfg_range7707w(0) XOR nl1Ol1Oi; + wire_w_lg_w_dl_req_phycfg_range7699w7702w(0) <= wire_w_dl_req_phycfg_range7699w(0) XOR nl1Oli0O; + wire_w_lg_w_dl_req_phycfg_range7691w7694w(0) <= wire_w_dl_req_phycfg_range7691w(0) XOR nl1OllOl; + wire_w_lg_w_dl_req_phycfg_range7683w7686w(0) <= wire_w_dl_req_phycfg_range7683w(0) XOR nl1OO1ii; + wire_w_lg_w_dl_req_phypm_range7753w7756w(0) <= wire_w_dl_req_phypm_range7753w(0) XOR nl1O00li; + wire_w_lg_w_dl_req_phypm_range7745w7748w(0) <= wire_w_dl_req_phypm_range7745w(0) XOR nl1O0l1O; + wire_w_lg_w_dl_req_phypm_range7737w7740w(0) <= wire_w_dl_req_phypm_range7737w(0) XOR nl1O0Oll; + wire_w_lg_w_dl_req_phypm_range7729w7732w(0) <= wire_w_dl_req_phypm_range7729w(0) XOR nl1Oi00i; + wire_w_lg_w_swdn_in_range8389w8392w(0) <= wire_w_swdn_in_range8389w(0) XOR nl11110l; + wire_w_lg_w_swdn_in_range8381w8384w(0) <= wire_w_swdn_in_range8381w(0) XOR nl1110Oi; + wire_w_lg_w_swdn_in_range8373w8376w(0) <= wire_w_swdn_in_range8373w(0) XOR nl111l0O; + wire_w_lg_w_swup_in_range8358w8361w(0) <= wire_w_swup_in_range8358w(0) XOR nl1100ii; + wire_w_lg_w_swup_in_range8350w8353w(0) <= wire_w_swup_in_range8350w(0) XOR nl110iOO; + wire_w_lg_w_swup_in_range8342w8345w(0) <= wire_w_swup_in_range8342w(0) XOR nl110Oil; + wire_w_lg_w_swup_in_range8334w8337w(0) <= wire_w_swup_in_range8334w(0) XOR nl11i01i; + wire_w_lg_w_swup_in_range8326w8329w(0) <= wire_w_swup_in_range8326w(0) XOR nl11iiiO; + wire_w_lg_w_swup_in_range8318w8321w(0) <= wire_w_swup_in_range8318w(0) XOR nl11iO1l; + wire_w_lg_w_swup_in_range8310w8313w(0) <= wire_w_swup_in_range8310w(0) XOR nl11l1li; + adrd_rcv0 <= ( nl1Ol1Oil & nl1Ol1Oii & nl1Ol1O0O & nl1Ol1O0l & nl1Ol1O0i & nl1Ol1O1O & nl1Ol1O1l & nl1Ol1O1i & nl1Ol1lOO); + adrd_rcv1 <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + adrd_rpl <= ( wire_nlliOOi1l_dataout & wire_nlliOOi1i_dataout & wire_nlliOO0OO_dataout & wire_nlliOO0Ol_dataout & wire_nlliOO0Oi_dataout & wire_nlliOO0lO_dataout & wire_nlliOO0ll_dataout & wire_nlliOO0li_dataout); + adwr_rcv0 <= ( wire_nl011100O_dataout & wire_nl011100l_dataout & wire_nl011100i_dataout & wire_nl011101O_dataout & wire_nl011101l_dataout & wire_nl011101i_dataout & wire_nl01111OO_dataout & wire_nl01111Ol_dataout & wire_nl01111Oi_dataout); + adwr_rcv1 <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + adwr_rpl <= ( nlll1lO0O & nlll1lO0l & nlll1lO0i & nlll1lO1O & nlll1lO1l & nlll1lO1i & nlll1llOO & nlll1llOl); + clr_rxpath <= nl1ll0li; + core_clk_vc0 <= wire_niO0011O_dataout; + core_clk_vc1 <= wire_niO0011l_dataout; + din_rcv0 <= ( wire_nl01011li_dataout & wire_nl01011iO_dataout & wire_nl01011il_dataout & wire_nl01011ii_dataout & wire_nl010110O_dataout & nl0100ilO & nl0100ill & niOO0O1OO & wire_nl010110i_dataout & nl0100iil & nl0100iii & nl0100i0O & wire_nl010111O_dataout & wire_nl010111l_dataout & wire_nl010111i_dataout & wire_nl011OOOO_dataout & nl0100i1i & nl01000OO & nl01000Ol & nl01000Oi & wire_nl011OOOl_dataout & wire_nl011OOOi_dataout & nl01000li & nl01000iO & nl01000il & nl01000ii & nl010000O & nl010000l & nl010000i & nl010001O & nl010001l & nl010001i & nl01001OO & nl01001Ol & nl01001Oi & nl01001lO & nl01001ll & nl01001li & nl01001iO & nl01001il & nl01001ii & nl010010O & nl010010l & nl010010i & nl010011O & nl010011l & nl010011i & nl0101OOO & nl0101OOl & nl0101OOi & nl0101OlO & nl0101Oll & nl0101Oli & nl0101OiO & nl0101Oil & nl0101Oii & nl0101O0O & nl0101O0l & nl0101O0i & nl0101O1O & nl0101O1l & nl0101O1i & nl0101lOO & nl0101lOl); + din_rcv1 <= ( wire_nl01011li_dataout & wire_nl01011iO_dataout & wire_nl01011il_dataout & wire_nl01011ii_dataout & wire_nl010110O_dataout & nl0100ilO & nl0100ill & niOO0O1OO & wire_nl010110i_dataout & nl0100iil & nl0100iii & nl0100i0O & wire_nl010111O_dataout & wire_nl010111l_dataout & wire_nl010111i_dataout & wire_nl011OOOO_dataout & nl0100i1i & nl01000OO & nl01000Ol & nl01000Oi & wire_nl011OOOl_dataout & wire_nl011OOOi_dataout & nl01000li & nl01000iO & nl01000il & nl01000ii & nl010000O & nl010000l & nl010000i & nl010001O & nl010001l & nl010001i & nl01001OO & nl01001Ol & nl01001Oi & nl01001lO & nl01001ll & nl01001li & nl01001iO & nl01001il & nl01001ii & nl010010O & nl010010l & nl010010i & nl010011O & nl010011l & nl010011i & nl0101OOO & nl0101OOl & nl0101OOi & nl0101OlO & nl0101Oll & nl0101Oli & nl0101OiO & nl0101Oil & nl0101Oii & nl0101O0O & nl0101O0l & nl0101O0i & nl0101O1O & nl0101O1l & nl0101O1i & nl0101lOO & nl0101lOl); + din_rpl <= ( wire_nilO0OOl_dataout & wire_nilO0OOi_dataout & wire_nilO0OlO_dataout & wire_nilO0Oll_dataout & wire_nilO0Oli_dataout & wire_nilO0OiO_dataout & wire_nilO0Oil_dataout & wire_nilO0Oii_dataout & wire_nilO0O0O_dataout & wire_nilO0O0l_dataout & wire_nilO0O0i_dataout & wire_nilO0O1O_dataout & wire_nilO0O1l_dataout & wire_nilO0O1i_dataout & wire_nilO0lOO_dataout & wire_nilO0lOl_dataout & wire_nilO0lOi_dataout & wire_nilO0llO_dataout & wire_nilO0lll_dataout & wire_nilO0lli_dataout & wire_nilO0liO_dataout & wire_nilO0lil_dataout & wire_nilO0lii_dataout & wire_nilO0l0O_dataout & wire_nilO0l0l_dataout & wire_nilO0l0i_dataout & wire_nilO0l1O_dataout & wire_nilO0l1l_dataout & wire_nilO0l1i_dataout & wire_nilO0iOO_dataout & wire_nilO0iOl_dataout & wire_nilO0iOi_dataout & wire_nilO0ilO_dataout & wire_nilO0ill_dataout & wire_nilO0ili_dataout & wire_nilO0iiO_dataout & wire_nilO0iil_dataout & wire_nilO0iii_dataout & wire_nilO0i0O_dataout & wire_nilO0i0l_dataout & wire_nilO0i0i_dataout & wire_nilO0i1O_dataout & wire_nilO0i1l_dataout & wire_nilO0i1i_dataout & wire_nilO00OO_dataout & wire_nilO00Ol_dataout & wire_nilO00Oi_dataout & wire_nilO00lO_dataout & wire_nilO00ll_dataout & wire_nilO00li_dataout & wire_nilO00iO_dataout & wire_nilO00il_dataout & wire_nilO00ii_dataout & wire_nilO000O_dataout & wire_nilO000l_dataout & wire_nilO000i_dataout & wire_nilO001O_dataout & wire_nilO001l_dataout & wire_nilO001i_dataout & wire_nilO01OO_dataout & wire_nilO01Ol_dataout & wire_nilO01Oi_dataout & wire_nilO01lO_dataout & wire_nilO01ll_dataout); + dl_ack_phypm <= ( nl1Oilil & nl1Oi0OO); + dl_ack_req_upfc <= nl010OOl; + dl_ack_snd_upfc <= nl01i0ii; + dl_current_deemp <= nl1iOO0O; + dl_current_speed <= ( nl1il10l & nl1il1lO); + dl_dll_req <= nl1llOil; + dl_err_dll <= ( nl1l000l & nl1l1OlO & nl1l1l0i & nl1l10ll & nl1l111O); + dl_err_phy <= nl1l0iOi; + dl_link_auto_bdw_status <= nl1iOOiO; + dl_link_bdw_mng_status <= nl1iOOlO; + dl_ltssm <= ( nl1lil0O & nl1lil0l & nl1lil0i & nl1lil1O & nl1liO0i); + dl_rpbuf_emp <= nl1llO1i; + dl_rst_enter_comp_bit <= nl1iii0i; + dl_rst_tx_margin_field <= nl1iillO; + dl_rx_typ_pm <= ( nl1lO00O & nl1lO00l & nl1lOi1O); + dl_rx_val_fc <= wire_nlOi01O0O_dataout; + dl_rx_val_pm <= nl1lO0ii; + dl_tx_ack_pm <= nl1O1O0l; + dl_up <= nl1l0O1O; + dl_vc_status <= ( nl10OiiO & nl10Oi0O & nl10Oi1O & nl10O0OO & nl10O0lO & nl10O0iO & nl10O00O & nl10O01O); + dlup_exit <= niO01i0O; + eidle_infer_sel <= ( nlOlO10il & nlOlO10ii & nlOllOO1i); + ev_128ns <= niOO0OiO; + ev_1us <= niOO0l1i; + hotrst_exit <= niO0100O; + int_status <= ( nl11O01i & nl11lOil & nl11liOO & nl11l0ii); + l2_exit <= niO0110O; + lane_act <= ( nl1li11i & nl1l0OOO & nl1l0OOl & nl1li1lO); + lane_reversal_enable <= n1101iiO; + link_up <= nl1liiiO; + lmi_ack <= ni0O01O; + lmi_dout <= ( ni0Ol0l & ni0Ol0i & ni0Ol1O & ni0Ol1l & ni0Ol1i & ni0OiOO & ni0OiOl & ni0OiOi & ni0OilO & ni0Oill & ni0Oili & ni0OiiO & ni0Oiil & ni0Oiii & ni0Oi0O & ni0Oi0l & ni0Oi0i & ni0Oi1O & ni0Oi1l & ni0Oi1i & ni0O0OO & ni0O0Ol & ni0O0Oi & ni0O0lO & ni0O0ll & ni0O0li & ni0O0iO & ni0O0il & ni0O0ii & ni0O00O & ni0O00l & ni0O00i); + niOi0000i <= ((wire_nilOii0i_w_lg_w_lg_w53887w53888w53895w(0) AND wire_nilOi0Oi_dataout) AND wire_nilOi0lO_dataout); + niOi0000l <= ((wire_nilOii0i_w_lg_w_lg_w53887w53888w53895w(0) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_dataout); + niOi0000O <= ((wire_nilOii0i_w_lg_w_lg_w53887w53888w53895w(0) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_w_lg_dataout53094w(0)); + niOi0001i <= (nl01l0lOl OR niOilllOi); + niOi0001l <= ((((wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53500w53501w53502w(0) OR wire_nlill0Oll_w53506w(0)) OR wire_nlill0Oll_w53511w(0)) OR wire_nlill0Oll_w53515w(0)) AND (((wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0iOO53517w53518w53519w(0) OR (wire_nlill0Oll_w_lg_w_lg_nl01l0iOO53517w53518w(0) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0))) OR ((wire_nlill0Oll_w_lg_nl01l0iOO53517w(0) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0))) OR ((wire_nlill0Oll_w_lg_nl01l0iOO53528w(0) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0)))); + niOi0001O <= (((wire_nilOii0i_w_lg_w53887w53901w(0) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_w_lg_dataout53094w(0)); + niOi000ii <= (((wire_nilOii0i_w_lg_w53887w53888w(0) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_dataout) AND wire_nilOi0lO_dataout); + niOi000il <= (((wire_nilOii0i_w_lg_w53887w53888w(0) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_dataout); + niOi000iO <= (((wire_nilOii0i_w_lg_w53887w53888w(0) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_w_lg_dataout53094w(0)); + niOi000li <= (wire_nilO010O_w_lg_dataout8973w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOi000ll <= (((wire_nlill0Oll_w_lg_w53515w53840w(0) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0)); + niOi000lO <= ((wire_nilOl11l_w_lg_dataout49175w(0) AND wire_nilOl11i_w_lg_dataout49181w(0)) AND wire_nilOiOOO_w_lg_dataout49183w(0)); + niOi000Oi <= (((nl01l0lll AND niOi00i1i) OR (nl01l0lll AND niOi000OO)) OR (nl01l0lll AND niOi000Ol)); + niOi000Ol <= ((((wire_nlill0Oll_w53867w(0) AND wire_nlill0Oll_w_lg_nl01l0iOO53574w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0)); + niOi000OO <= ((wire_nlill0Oll_w_lg_w_lg_w53515w53863w53864w(0) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0)); + niOi0010i <= (((((((NOT (wire_nli1ll0OO_dataout AND wire_w_lg_niOii000i53801w(0))) AND (NOT (wire_nli1lli1i_dataout AND (NOT (niOii0liO OR niOii001O))))) AND (NOT (wire_nli1lli1l_dataout AND wire_w_lg_niOii0O0O53809w(0)))) AND (NOT (wire_nli1lli1O_dataout AND (NOT (niOiiO10O OR niOii0O0l))))) AND (NOT (wire_nli1lli0i_dataout AND wire_w_lg_niOiiii0i53818w(0)))) AND (NOT (wire_nli1lli0l_dataout AND (NOT (niOiiO1li OR niOiiii1O))))) AND (NOT (wire_nli1lli0O_dataout AND (niOiiOiOl XOR (k_bar(203) AND wire_nl01l1lii_o(10)))))); + niOi0010l <= ((wire_nilOl10O_w_lg_dataout49168w(0) AND wire_nilOl10l_w_lg_dataout49170w(0)) AND wire_nilOl10i_w_lg_dataout49172w(0)); + niOi0010O <= ((wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53201w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_dataout); + niOi0011i <= ((wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53201w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOi0011l <= (wire_nilOl1Oi_w_lg_dataout43272w(0) AND wire_nilOl1lO_w44969w(0)); + niOi0011O <= ((((((wire_nli1lli0O_w_lg_dataout53379w(0) AND wire_nli1lli0l_w_lg_dataout53381w(0)) AND wire_nli1lli0i_w_lg_dataout53447w(0)) AND wire_nli1lli1O_w_lg_dataout53834w(0)) AND wire_nli1lli1l_w_lg_dataout53836w(0)) AND wire_nli1lli1i_w_lg_dataout53427w(0)) AND wire_nli1ll0OO_w_lg_dataout53423w(0)); + niOi001ii <= (wire_nlill0Oll_w_lg_w_lg_w53924w53926w53930w(0) AND wire_nlill0Oll_w_lg_nl01l00OO53931w(0)); + niOi001il <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53514w(0) AND wire_nlill0Oll_w_lg_nl01l0l1i53845w(0)); + niOi001iO <= ((wire_nlill0Oll_w_lg_w53924w53926w(0) AND wire_nlill0Oll_w_lg_nl01l0i1i53927w(0)) AND nl01l00OO); + niOi001li <= (nl0100O1i AND wire_w_lg_niOi01l1l54090w(0)); + niOi001ll <= ((wire_nlill0Oll_w_lg_nli1iOilO42904w(0) AND wire_nlill0Oll_w_lg_nli1iOill42899w(0)) AND wire_nlill0Oll_w_lg_nli1iOili42902w(0)); + niOi001lO <= ((wire_nlill0Oll_w_lg_nli1iOilO42904w(0) AND wire_nlill0Oll_w_lg_nli1iOill42899w(0)) AND nli1iOili); + niOi001Oi <= (wire_nlill0Oll_w_lg_w_lg_nli1iOilO42904w42905w(0) AND wire_nlill0Oll_w_lg_nli1iOili42902w(0)); + niOi001Ol <= (wire_nlill0Oll_w_lg_w_lg_nli1iOilO42904w42905w(0) AND nli1iOili); + niOi001OO <= (wire_nlill0Oll_w_lg_nli1iOilO42900w(0) AND wire_nlill0Oll_w_lg_nli1iOili42902w(0)); + niOi00i0i <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53510w(0) AND wire_nlill0Oll_w_lg_nl01l0l1i53845w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOO53574w(0)); + niOi00i0l <= (nl01l0lll AND niOi00i0O); + niOi00i0O <= ((((wire_nlill0Oll_w53511w(0) AND wire_nlill0Oll_w_lg_nl01l0iOO53574w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND nl01l0iOi) AND nl01l0ilO); + niOi00i1i <= (((wire_nlill0Oll_w_lg_w53515w53840w(0) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND nl01l0ilO); + niOi00i1l <= ((((((((((((((((((((wire_nilOl1OO_w49173w(0) AND wire_nilOl11O_w_lg_dataout49178w(0)) AND wire_nilOl11l_w_lg_dataout49175w(0)) AND wire_nilOl11i_w_lg_dataout49181w(0)) AND wire_nilOiOOO_w_lg_dataout49183w(0)) AND wire_nilOiOOl_w_lg_dataout49185w(0)) AND wire_nilOiOOi_w_lg_dataout49186w(0)) AND wire_nilOiOlO_w_lg_dataout49188w(0)) AND wire_nilOiOll_w_lg_dataout49190w(0)) AND wire_nilOiOli_w_lg_dataout49192w(0)) AND wire_nilOiOiO_w_lg_dataout49194w(0)) AND wire_nilOiOil_w_lg_dataout53723w(0)) AND wire_nilOiOii_w_lg_dataout53724w(0)) AND wire_nilOiO0O_w_lg_dataout53726w(0)) AND wire_nilOiO0l_w_lg_dataout53728w(0)) AND wire_nilOiO0i_w_lg_dataout53730w(0)) AND wire_nilOiO1O_w_lg_dataout53732w(0)) AND wire_nilOiO1l_w_lg_dataout53734w(0)) AND wire_nilOiO1i_w_lg_dataout53736w(0)) AND wire_nilOilOO_w_lg_dataout53156w(0)) AND wire_nilOilOl_w_lg_dataout53154w(0)); + niOi00i1O <= (nl01l0lll AND niOi00i0i); + niOi00iii <= (nl01l0lll AND niOi00iil); + niOi00iil <= ((((wire_nlill0Oll_w53511w(0) AND wire_nlill0Oll_w_lg_nl01l0iOO53574w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND nl01l0ilO); + niOi00iiO <= (nl01l0lll AND niOi00ili); + niOi00ili <= ((((wire_nlill0Oll_w53511w(0) AND wire_nlill0Oll_w_lg_nl01l0iOO53574w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0)); + niOi00ill <= (nl01l0lll AND niOi00ilO); + niOi00ilO <= (((wire_nlill0Oll_w_lg_w53515w53840w(0) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND nl01l0iOi) AND nl01l0ilO); + niOi00iOi <= (nl01l0lll AND niOi00iOl); + niOi00iOl <= (((wire_nlill0Oll_w_lg_w53846w53847w(0) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0)) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0)) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0)); + niOi00iOO <= ((wire_nlill0Oll_w_lg_w_lg_nl01l0lOO53327w53328w(0) OR wire_nl1000i_w_lg_w_lg_niOOi01il42910w53329w(0)) OR wire_nl1000i_w_lg_w_lg_niOOi01il42910w53331w(0)); + niOi00l0i <= (wire_nl1000i_w_lg_niOOi01il42910w(0) AND wire_nlill0Oll_w_lg_nl01l0lOl53382w(0)); + niOi00l0l <= (nl01l0lll AND nl01ii1OO); + niOi00l0O <= (nlill0lll OR niOi0iOli); + niOi00l1i <= (nl01l0O1l AND wire_nli1lli0O_w_lg_dataout53379w(0)); + niOi00l1l <= (nl01l0O1i AND wire_nli1lliii_w_lg_dataout53377w(0)); + niOi00l1O <= (nl01l0O1i AND niOi00i1l); + niOi00lii <= (((((((wire_w_lg_w_lg_niOi0lOOi53212w53213w(0) OR wire_w_lg_niOi0lOOi53215w(0)) OR (wire_w_lg_niOi0lOOi53212w(0) AND (niOi00lOl OR niOi00lOi))) OR (wire_w_lg_niOi0lOOi53212w(0) AND (niOi00llO OR niOi00lll))) OR (niOi0lOOi AND niOi00lli)) OR (niOi0lOOi AND niOi00liO)) OR niOi00lil) OR niOi00O1O); + niOi00lil <= (((((wire_nilOii0i_w_lg_w_lg_dataout45173w53875w(0) AND wire_nilOii1l_dataout) AND wire_nilOii1i_dataout) AND wire_nilOi0OO_dataout) AND wire_nilOi0Ol_dataout) AND wire_nilOi0Oi_dataout); + niOi00liO <= ((((wire_nilOii0i_w53877w(0) AND wire_nilOi0OO_w_lg_dataout45178w(0)) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_w_lg_dataout53094w(0)); + niOi00lli <= (((((wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w53764w(0) AND wire_nilOii1i_w_lg_dataout53100w(0)) AND wire_nilOi0OO_w_lg_dataout45178w(0)) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_w_lg_dataout53094w(0)); + niOi00lll <= ((((wire_nilOii0i_w45177w(0) AND wire_nilOi0OO_w_lg_dataout45178w(0)) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_dataout) AND wire_nilOi0lO_dataout); + niOi00llO <= (((wire_nilOii0i_w45177w(0) AND wire_nilOi0OO_w_lg_dataout45178w(0)) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)); + niOi00lOi <= (((wire_nilOii0i_w_lg_w53765w53770w(0) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_dataout) AND wire_nilOi0lO_dataout); + niOi00lOl <= (((wire_nilOii0i_w_lg_w53765w53770w(0) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_w_lg_dataout53094w(0)); + niOi00lOO <= (((wire_nilOii0i_w_lg_w53765w53770w(0) AND wire_nilOi0Ol_w_lg_dataout45180w(0)) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_dataout); + niOi00O0i <= wire_nilOl1lO_w44969w(0); + niOi00O0l <= wire_nilOl1lO_w_lg_dataout53761w(0); + niOi00O0O <= ((wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53757w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_dataout); + niOi00O1i <= ((wire_nilOii0i_w_lg_w_lg_w53765w53766w53767w(0) AND wire_nilOi0Oi_w_lg_dataout53096w(0)) AND wire_nilOi0lO_w_lg_dataout53094w(0)); + niOi00O1l <= ((wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w45176w(0) AND wire_nilOii1i_w_lg_dataout53100w(0)) AND wire_nilOi0OO_w_lg_dataout45178w(0)); + niOi00O1O <= (niOi0lOOi AND ((((((niOi000iO OR niOi000il) OR niOi000ii) OR niOi0000O) OR niOi0000l) OR niOi0000i) OR niOi0001O)); + niOi00Oii <= (wire_nilOl1lO_w53755w(0) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOi00Oil <= ((wire_nilOl1Ol_w_lg_dataout43262w(0) AND (wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53201w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0))) OR niOi00OiO); + niOi00OiO <= ((wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53201w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOi00Oli <= (wire_nlill0Oll_w_lg_w_lg_nl01l01Oi53740w53741w(0) AND wire_nlill0Oll_w_lg_nl01l01ll53742w(0)); + niOi00Oll <= (wire_nilOi00l_dataout AND (wire_nilOi0iO_dataout AND nl01l0liO)); + niOi00OlO <= (((((((((wire_nilOiOil_w_lg_dataout53723w(0) AND wire_nilOiOii_w_lg_dataout53724w(0)) AND wire_nilOiO0O_w_lg_dataout53726w(0)) AND wire_nilOiO0l_w_lg_dataout53728w(0)) AND wire_nilOiO0i_w_lg_dataout53730w(0)) AND wire_nilOiO1O_w_lg_dataout53732w(0)) AND wire_nilOiO1l_w_lg_dataout53734w(0)) AND wire_nilOiO1i_w_lg_dataout53736w(0)) AND wire_nilOilOO_w_lg_dataout53156w(0)) AND wire_nilOilOl_dataout); + niOi00OOi <= (wire_nilOi0iO_dataout AND wire_nilOi00l_dataout); + niOi00OOl <= (wire_nl00l111l_dataout AND wire_nl00l111i_w_lg_dataout53192w(0)); + niOi00OOO <= (wire_nl00l111l_w_lg_dataout53191w(0) AND wire_nl00l111i_dataout); + niOi0100i <= (wire_nl011Ol1O_dataout AND niOi0100l); + niOi0100l <= (((((((((NOT (k_ptr0(9) XOR wire_nl011110i_dataout)) AND (NOT (k_ptr0(10) XOR wire_nl011110l_dataout))) AND (NOT (k_ptr0(11) XOR wire_nl011110O_dataout))) AND (NOT (k_ptr0(12) XOR wire_nl01111ii_dataout))) AND (NOT (k_ptr0(13) XOR wire_nl01111il_dataout))) AND (NOT (k_ptr0(14) XOR wire_nl01111iO_dataout))) AND (NOT (k_ptr0(15) XOR wire_nl01111li_dataout))) AND (NOT (k_ptr0(16) XOR wire_nl01111ll_dataout))) AND (NOT (k_ptr0(17) XOR wire_nl01111lO_dataout))); + niOi0100O <= (wire_nl011Ol1O_dataout AND wire_w_lg_niOi01lll54217w(0)); + niOi0101i <= (wire_nlill0Oll_w_lg_nl1OilO0O54864w(0) AND (wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0) AND (wire_nlill0Oll_w_lg_nl1OilOii54862w(0) AND (wire_nlill0Oll_w_lg_nl1OOii1l8961w(0) AND wire_nliliO10i_w_lg_nl1OilO0i56530w(0))))); + niOi0101l <= (((((((((NOT (wire_nl011110i_dataout XOR wire_nl1OOO0il_o(1))) AND (NOT (wire_nl011110l_dataout XOR wire_nl1OOO0il_o(2)))) AND (NOT (wire_nl011110O_dataout XOR wire_nl1OOO0il_o(3)))) AND (NOT (wire_nl01111ii_dataout XOR wire_nl1OOO0il_o(4)))) AND (NOT (wire_nl01111il_dataout XOR wire_nl1OOO0il_o(5)))) AND (NOT (wire_nl01111iO_dataout XOR wire_nl1OOO0il_o(6)))) AND (NOT (wire_nl01111li_dataout XOR wire_nl1OOO0il_o(7)))) AND (NOT (wire_nl01111ll_dataout XOR wire_nl1OOO0il_o(8)))) AND (NOT (wire_nl01111lO_dataout XOR wire_nl1OOO0il_o(9)))); + niOi0101O <= (niOi0100O AND wire_nl1OOOiOO_o); + niOi010ii <= wire_w_lg_w_k_gbl_hip_range54181w54216w(0); + niOi010il <= (((((((((NOT (k_ptr0(27) XOR wire_nl01111Oi_dataout)) AND (NOT (k_ptr0(28) XOR wire_nl01111Ol_dataout))) AND (NOT (k_ptr0(29) XOR wire_nl01111OO_dataout))) AND (NOT (k_ptr0(30) XOR wire_nl011101i_dataout))) AND (NOT (k_ptr0(31) XOR wire_nl011101l_dataout))) AND (NOT (k_ptr0(32) XOR wire_nl011101O_dataout))) AND (NOT (k_ptr0(33) XOR wire_nl011100i_dataout))) AND (NOT (k_ptr0(34) XOR wire_nl011100l_dataout))) AND (NOT (k_ptr0(35) XOR wire_nl011100O_dataout))); + niOi010iO <= (wire_nl011Ol1O_dataout AND niOi010li); + niOi010li <= (((((((((NOT (k_ptr0(9) XOR wire_nl01111Oi_dataout)) AND (NOT (k_ptr0(10) XOR wire_nl01111Ol_dataout))) AND (NOT (k_ptr0(11) XOR wire_nl01111OO_dataout))) AND (NOT (k_ptr0(12) XOR wire_nl011101i_dataout))) AND (NOT (k_ptr0(13) XOR wire_nl011101l_dataout))) AND (NOT (k_ptr0(14) XOR wire_nl011101O_dataout))) AND (NOT (k_ptr0(15) XOR wire_nl011100i_dataout))) AND (NOT (k_ptr0(16) XOR wire_nl011100l_dataout))) AND (NOT (k_ptr0(17) XOR wire_nl011100O_dataout))); + niOi010ll <= (nl01ii1ll OR (nl01ii1lO OR nl01ii1iO)); + niOi010lO <= (wire_nilOi0ii_dataout AND (wire_w_lg_niOi01i0O54209w(0) OR niOi010Oi)); + niOi010Oi <= ((wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w52011w(0) AND wire_nl1lOOlOO_w_lg_dataout52012w(0)) AND wire_nl1lOOlOl_w_lg_dataout52282w(0)); + niOi010Ol <= (k_gbl_hip(26) AND niOi01i1l); + niOi010OO <= (wire_nl011Ol1l_dataout AND ((NOT k_gbl_hip(26)) OR wire_w_lg_niOi01i1l54196w(0))); + niOi0110i <= ((wire_nlill0Oll_w_lg_nl1OOii1l54830w(0) AND wire_w_lg_niOi011Oi54831w(0)) AND nl1OilO0i); + niOi0110l <= (niOi011ii AND niOi0110O); + niOi0110O <= (wire_nl1OOi10l_w_lg_dataout56726w(0) AND wire_nl1OOi10i_w_lg_dataout56727w(0)); + niOi0111i <= ((NOT k_gbl_hip(26)) OR wire_niO01O0O_dataout); + niOi0111l <= (niOi0111O AND wire_w_lg_w_k_gbl_hip_range54181w54586w(0)); + niOi0111O <= ((niOi0110l AND niOi0110i) AND nli1100i); + niOi011ii <= (k_gbl_hip(26) AND wire_nl1OOi11i_o); + niOi011il <= ((wire_nl011Ol1l_dataout AND nl1OOii1O) AND niOi011li); + niOi011iO <= (niOi011li AND (wire_nl011Ol1l_dataout OR wire_nliliO10i_w_lg_nl1OOii1O54515w(0))); + niOi011li <= (wire_nlill0Oll_w_lg_nl1OOii1l8961w(0) OR niOi011Oi); + niOi011ll <= (wire_nl011Ol1l_dataout AND niOi011lO); + niOi011lO <= (((((((NOT (nl1OOiill XOR nl1OOii0i)) AND (NOT (nl1OOiilO XOR nl1OOii0l))) AND (NOT (nl1OOiiOi XOR nl1OOii0O))) AND (NOT (nl1OOiiOl XOR nl1OOiiii))) AND (NOT (nl1OOiiOO XOR nl1OOiiil))) AND (NOT (nl1OOil1i XOR nl1OOiiiO))) AND (NOT (nl1OOil1l XOR nl1OOiili))); + niOi011Oi <= (nl1OO010l OR nl1OllOOO); + niOi011Ol <= (((((((NOT (wire_nl1OOlOii_o(0) XOR nl1OOiill)) AND (NOT (wire_nl1OOlOii_o(1) XOR nl1OOiilO))) AND (NOT (wire_nl1OOlOii_o(2) XOR nl1OOiiOi))) AND (NOT (wire_nl1OOlOii_o(3) XOR nl1OOiiOl))) AND (NOT (wire_nl1OOlOii_o(4) XOR nl1OOiiOO))) AND (NOT (wire_nl1OOlOii_o(5) XOR nl1OOil1i))) AND (NOT (wire_nl1OOlOii_o(6) XOR nl1OOil1l))); + niOi011OO <= (wire_nlill0Oll_w_lg_nl1OOi01i54582w(0) AND niOi011iO); + niOi01i0i <= (wire_nilOOO0i_w_lg_dataout47830w(0) AND wire_nilOO00O_w_lg_dataout47986w(0)); + niOi01i0l <= (k_gbl_hip(32) OR niOi01i0O); + niOi01i0O <= (niOi01iii OR (wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_w_lg_dataout25163w(0))); + niOi01i1i <= wire_w_lg_w_k_gbl_hip_range54181w54184w(0); + niOi01i1l <= (wire_nlill0Oll_w_lg_nl0100lOi56535w(0) AND nl0100llO); + niOi01i1O <= (k_gbl_hip(26) AND niOi01i0i); + niOi01iii <= wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0); + niOi01iil <= ((wire_nlill0Oll_w_lg_nl00lliOl54160w(0) AND wire_nlill0Oll_w_lg_nl00lliOi54161w(0)) AND wire_nlill0Oll_w_lg_nl00llilO54163w(0)); + niOi01iiO <= ((wire_nlill0Oll_w_lg_nl00lliOl54160w(0) AND wire_nlill0Oll_w_lg_nl00lliOi54161w(0)) AND nl00llilO); + niOi01ili <= (wire_nlill0Oll_w_lg_w_lg_nl00lliOl54160w54166w(0) AND wire_nlill0Oll_w_lg_nl00llilO54163w(0)); + niOi01ill <= (wire_nlill0Oll_w_lg_w_lg_nl00lliOl54160w54166w(0) AND nl00llilO); + niOi01ilO <= (wire_nlill0Oll_w_lg_nl00lliOl54169w(0) AND wire_nlill0Oll_w_lg_nl00llilO54163w(0)); + niOi01iOi <= (wire_nlill0Oll_w_lg_nl00lliOl54169w(0) AND nl00llilO); + niOi01iOl <= ((nl00lliOl AND nl00lliOi) AND wire_nlill0Oll_w_lg_nl00llilO54163w(0)); + niOi01iOO <= (wire_nlill0Oll_w_lg_nl011l1ii54095w(0) AND nl1OilO0l); + niOi01l0i <= ((wire_nl011OiiO_dataout OR nl10lliOO) AND wire_nlill0Oll_w_lg_nl011ll1O54081w(0)); + niOi01l0l <= (wire_nilOi00l_dataout AND nl011OO1O); + niOi01l0O <= (wire_nilOl1Ol_w_lg_dataout43262w(0) AND (wire_nilOi0li_dataout AND wire_nilOi00l_dataout)); + niOi01l1i <= (wire_nilOO0ii_dataout AND wire_nlOilOO1O_dataout); + niOi01l1l <= (((((wire_nlill0Oll_w_lg_nl1i1101l59140w(0) AND wire_nlill0Oll_w_lg_nl1i1101i59141w(0)) AND wire_nlill0Oll_w_lg_nl1i111OO59143w(0)) AND wire_nlill0Oll_w_lg_nl1i111Ol59145w(0)) AND wire_nlill0Oll_w_lg_nl1i111Oi59147w(0)) AND wire_nlill0Oll_w_lg_nl10O0OOi59149w(0)); + niOi01l1O <= (wire_nilOll0l_w_lg_dataout54086w(0) OR wire_nlill0Oll_w_lg_w_lg_nl011ll1l54087w54088w(0)); + niOi01lii <= (wire_nilOl1Ol_dataout AND (wire_nilOi0li_dataout AND wire_nilOi00l_dataout)); + niOi01lil <= (wire_nilOi0li_dataout AND wire_nilOi00l_dataout); + niOi01liO <= (((((((((wire_nilOiOil_w_lg_dataout53723w(0) AND wire_nilOiOii_w_lg_dataout53724w(0)) AND wire_nilOiO0O_w_lg_dataout53726w(0)) AND wire_nilOiO0l_w_lg_dataout53728w(0)) AND wire_nilOiO0i_w_lg_dataout53730w(0)) AND wire_nilOiO1O_w_lg_dataout53732w(0)) AND wire_nilOiO1l_w_lg_dataout53734w(0)) AND wire_nilOiO1i_w_lg_dataout53736w(0)) AND wire_nilOilOO_w_lg_dataout53156w(0)) AND wire_nilOilOl_dataout); + niOi01lli <= ((((((NOT (niOi1il1l AND niOi1i0iO)) AND (NOT (wire_nl1i11l0O_o AND niOi1i0iO))) AND (NOT (niOi1il1O AND niOi1i0il))) AND (NOT ((wire_nl1i11l1O_o AND wire_w_lg_niOi1ilOl57737w(0)) AND niOi1i0il))) AND (NOT ((wire_w_lg_niOi1illO57815w(0) AND niOi1il0i) AND niOi1i0ii))) AND (NOT ((wire_nl1i11iOi_o AND wire_w_lg_niOi1illO57815w(0)) AND niOi1i0ii))); + niOi01lll <= (((((((((NOT (wire_nl1OOO10i_dataout XOR nl1Ol1l0O)) AND (NOT (wire_nl1OOO10l_dataout XOR nl1Ol1lii))) AND (NOT (wire_nl1OOO10O_dataout XOR nl1Ol1lil))) AND (NOT (wire_nl1OOO1ii_dataout XOR nl1Ol1liO))) AND (NOT (wire_nl1OOO1il_dataout XOR nl1Ol1lli))) AND (NOT (wire_nl1OOO1iO_dataout XOR nl1Ol1lll))) AND (NOT (wire_nl1OOO1li_dataout XOR nl1Ol1llO))) AND (NOT (wire_nl1OOO1ll_dataout XOR nl1Ol1lOi))) AND (NOT (wire_nl1OOO1lO_dataout XOR nl1Ol1lOl))); + niOi01llO <= ((wire_nl010Oi0i_w_lg_dataout54122w(0) AND wire_nl010Oi1O_w_lg_dataout54123w(0)) AND wire_nl010Oi1l_w_lg_dataout54125w(0)); + niOi01lOi <= ((wire_nl010Oi0i_w_lg_dataout54122w(0) AND wire_nl010Oi1O_w_lg_dataout54123w(0)) AND wire_nl010Oi1l_dataout); + niOi01lOl <= ((((((((NOT (wire_nilOOO0i_dataout AND niOi01llO)) AND (NOT (wire_nilOOO0l_dataout AND niOi01lOi))) AND (NOT (wire_nilOOO0O_dataout AND (wire_nl010Oi0i_w_lg_w_lg_dataout54122w54133w(0) AND wire_nl010Oi1l_w_lg_dataout54125w(0))))) AND (NOT (wire_nilOOOii_dataout AND (wire_nl010Oi0i_w_lg_w_lg_dataout54122w54133w(0) AND wire_nl010Oi1l_dataout)))) AND (NOT (wire_nilOOOil_dataout AND (wire_nl010Oi0i_w_lg_dataout54142w(0) AND wire_nl010Oi1l_w_lg_dataout54125w(0))))) AND (NOT (wire_nilOOOiO_dataout AND (wire_nl010Oi0i_w_lg_dataout54142w(0) AND wire_nl010Oi1l_dataout)))) AND (NOT (wire_nilOOOli_dataout AND ((wire_nl010Oi0i_dataout AND wire_nl010Oi1O_dataout) AND wire_nl010Oi1l_w_lg_dataout54125w(0))))) AND (NOT (wire_nilOOOll_dataout AND ((wire_nl010Oi0i_dataout AND wire_nl010Oi1O_dataout) AND wire_nl010Oi1l_dataout)))); + niOi01lOO <= (wire_nilOi0li_dataout AND wire_nilOi00l_dataout); + niOi01O0i <= (wire_nilOl10O_w_lg_w_lg_dataout49168w54114w(0) AND wire_nilOl10i_dataout); + niOi01O0l <= (wire_nilOl10O_w_lg_dataout54117w(0) AND wire_nilOl10i_w_lg_dataout49172w(0)); + niOi01O0O <= (wire_nilOl10O_w_lg_dataout54117w(0) AND wire_nilOl10i_dataout); + niOi01O1i <= ((wire_nilOl10O_w_lg_dataout49168w(0) AND wire_nilOl10l_w_lg_dataout49170w(0)) AND wire_nilOl10i_w_lg_dataout49172w(0)); + niOi01O1l <= ((wire_nilOl10O_w_lg_dataout49168w(0) AND wire_nilOl10l_w_lg_dataout49170w(0)) AND wire_nilOl10i_dataout); + niOi01O1O <= (wire_nilOl10O_w_lg_w_lg_dataout49168w54114w(0) AND wire_nilOl10i_w_lg_dataout49172w(0)); + niOi01Oii <= ((wire_nilOl10O_dataout AND wire_nilOl10l_dataout) AND wire_nilOl10i_w_lg_dataout49172w(0)); + niOi01Oil <= (((((((wire_nlill0Oll_w_lg_nl010OlOO54098w(0) AND wire_nlill0Oll_w_lg_nl010OlOl54099w(0)) AND wire_nlill0Oll_w_lg_nl010OlOi54101w(0)) AND wire_nlill0Oll_w_lg_nl010OllO54103w(0)) AND wire_nlill0Oll_w_lg_nl010Olll54105w(0)) AND wire_nlill0Oll_w_lg_nl010Olli54107w(0)) AND wire_nlill0Oll_w_lg_nl010OliO54109w(0)) AND wire_nlill0Oll_w_lg_nl010Olil54111w(0)); + niOi01OiO <= (wire_nilOi00l_dataout AND (wire_nilOi0li_dataout AND (niOi01OOl OR (wire_nilOl1Oi_w_lg_dataout43272w(0) AND niOi01Oli)))); + niOi01Oli <= ((wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53757w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOi01Oll <= (wire_nilOilOO_w_lg_dataout53156w(0) AND wire_nilOilOl_w_lg_dataout53154w(0)); + niOi01OlO <= (wire_nl01i10lO_o OR niOi01OOi); + niOi01OOi <= (((((((((wire_nilOiOil_w_lg_dataout53723w(0) AND wire_nilOiOii_w_lg_dataout53724w(0)) AND wire_nilOiO0O_w_lg_dataout53726w(0)) AND wire_nilOiO0l_w_lg_dataout53728w(0)) AND wire_nilOiO0i_w_lg_dataout53730w(0)) AND wire_nilOiO1O_w_lg_dataout53732w(0)) AND wire_nilOiO1l_w_lg_dataout53734w(0)) AND wire_nilOiO1i_w_lg_dataout53736w(0)) AND wire_nilOilOO_w_lg_dataout53156w(0)) AND wire_nilOilOl_w_lg_dataout53154w(0)); + niOi01OOl <= (wire_nilOl1Oi_w_lg_dataout43272w(0) AND niOi01OOO); + niOi01OOO <= ((wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53757w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_dataout); + niOi0i00i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(15)); + niOi0i00l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(16)); + niOi0i00O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(17)); + niOi0i01i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(12)); + niOi0i01l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(13)); + niOi0i01O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(14)); + niOi0i0ii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(18)); + niOi0i0il <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(19)); + niOi0i0iO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(20)); + niOi0i0li <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(21)); + niOi0i0ll <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(22)); + niOi0i0lO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(23)); + niOi0i0Oi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(24)); + niOi0i0Ol <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(25)); + niOi0i0OO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(26)); + niOi0i10i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(0)); + niOi0i10l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(1)); + niOi0i10O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(2)); + niOi0i11i <= (((((((((((NOT wire_nl01lliOO_o(3)) AND (NOT wire_nl01lliOO_o(4))) AND (NOT wire_nl01lliOO_o(5))) AND (NOT wire_nl01lliOO_o(6))) AND (NOT wire_nl01lliOO_o(7))) AND (NOT wire_nl01lliOO_o(8))) AND (NOT wire_nl01lliOO_o(9))) AND (NOT wire_nl01lliOO_o(10))) AND (NOT wire_nl01lliOO_o(11))) AND (NOT wire_nl01lliOO_o(12))) AND (NOT wire_nl01lliOO_o(13))); + niOi0i11l <= ((wire_nilOiilO_w_lg_dataout53905w(0) AND wire_nilOiill_w_lg_dataout53906w(0)) AND wire_nilOiili_w_lg_dataout53908w(0)); + niOi0i11O <= (((((((((wire_nilOiOil_w_lg_dataout53723w(0) AND wire_nilOiOii_w_lg_dataout53724w(0)) AND wire_nilOiO0O_w_lg_dataout53726w(0)) AND wire_nilOiO0l_w_lg_dataout53728w(0)) AND wire_nilOiO0i_w_lg_dataout53730w(0)) AND wire_nilOiO1O_w_lg_dataout53732w(0)) AND wire_nilOiO1l_w_lg_dataout53734w(0)) AND wire_nilOiO1i_w_lg_dataout53736w(0)) AND wire_nilOilOO_w_lg_dataout53156w(0)) AND wire_nilOilOl_w_lg_dataout53154w(0)); + niOi0i1ii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(3)); + niOi0i1il <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(4)); + niOi0i1iO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(5)); + niOi0i1li <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(6)); + niOi0i1ll <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(7)); + niOi0i1lO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(8)); + niOi0i1Oi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(9)); + niOi0i1Ol <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(10)); + niOi0i1OO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(11)); + niOi0ii0i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(30)); + niOi0ii0l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(31)); + niOi0ii0O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(32)); + niOi0ii1i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(27)); + niOi0ii1l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(28)); + niOi0ii1O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(29)); + niOi0iiii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(33)); + niOi0iiil <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(34)); + niOi0iiiO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(35)); + niOi0iili <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(36)); + niOi0iill <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(37)); + niOi0iilO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(38)); + niOi0iiOi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(39)); + niOi0iiOl <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(40)); + niOi0iiOO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(41)); + niOi0il0i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(45)); + niOi0il0l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(46)); + niOi0il0O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(47)); + niOi0il1i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(42)); + niOi0il1l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(43)); + niOi0il1O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(44)); + niOi0ilii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(48)); + niOi0ilil <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(49)); + niOi0iliO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(50)); + niOi0illi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(51)); + niOi0illl <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(52)); + niOi0illO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(53)); + niOi0ilOi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(54)); + niOi0ilOl <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(55)); + niOi0ilOO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(56)); + niOi0iO0i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(60)); + niOi0iO0l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(61)); + niOi0iO0O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(62)); + niOi0iO1i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(57)); + niOi0iO1l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(58)); + niOi0iO1O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(59)); + niOi0iOii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl001lliO_o(63)); + niOi0iOil <= (wire_nilOi0ii_w_lg_w_lg_w_lg_dataout52927w52932w52933w(0) AND (wire_nlill0Oll_w_lg_nl01i0OOO52934w(0) AND wire_nlill0Oll_w_lg_nl01i0OOl52935w(0))); + niOi0iOiO <= (niOi0iOli AND ((wire_nlill0Oll_w_lg_nl01i0Oii52921w(0) AND wire_nlill0Oll_w_lg_nl01i0O0O52922w(0)) AND wire_nlill0Oll_w_lg_nl01i0O1i52924w(0))); + niOi0iOli <= (wire_nilOi00l_dataout AND wire_nilOi00i_dataout); + niOi0iOll <= (wire_nlill0Oll_w_lg_nl11lOO1i45149w(0) AND (wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOlOO44945w44946w52772w(0) AND wire_nlill0Oll_w_lg_nl11lOllO45169w(0))); + niOi0iOlO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(0)); + niOi0iOOi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(1)); + niOi0iOOl <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(2)); + niOi0iOOO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(3)); + niOi0l00i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(22)); + niOi0l00l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(23)); + niOi0l00O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(24)); + niOi0l01i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(19)); + niOi0l01l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(20)); + niOi0l01O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(21)); + niOi0l0ii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(25)); + niOi0l0il <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(26)); + niOi0l0iO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(27)); + niOi0l0li <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(28)); + niOi0l0ll <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(29)); + niOi0l0lO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(30)); + niOi0l0Oi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(31)); + niOi0l0Ol <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(32)); + niOi0l0OO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(33)); + niOi0l10i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(7)); + niOi0l10l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(8)); + niOi0l10O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(9)); + niOi0l11i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(4)); + niOi0l11l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(5)); + niOi0l11O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(6)); + niOi0l1ii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(10)); + niOi0l1il <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(11)); + niOi0l1iO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(12)); + niOi0l1li <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(13)); + niOi0l1ll <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(14)); + niOi0l1lO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(15)); + niOi0l1Oi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(16)); + niOi0l1Ol <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(17)); + niOi0l1OO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(18)); + niOi0li0i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(37)); + niOi0li0l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(38)); + niOi0li0O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(39)); + niOi0li1i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(34)); + niOi0li1l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(35)); + niOi0li1O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(36)); + niOi0liii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(40)); + niOi0liil <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(41)); + niOi0liiO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(42)); + niOi0lili <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(43)); + niOi0lill <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(44)); + niOi0lilO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(45)); + niOi0liOi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(46)); + niOi0liOl <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(47)); + niOi0liOO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(48)); + niOi0ll0i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(52)); + niOi0ll0l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(53)); + niOi0ll0O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(54)); + niOi0ll1i <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(49)); + niOi0ll1l <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(50)); + niOi0ll1O <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(51)); + niOi0llii <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(55)); + niOi0llil <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(56)); + niOi0lliO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(57)); + niOi0llli <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(58)); + niOi0llll <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(59)); + niOi0lllO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(60)); + niOi0llOi <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(61)); + niOi0llOl <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(62)); + niOi0llOO <= (wire_nl00il01l_w_lg_o52792w(0) AND wire_nl00il01i_o(63)); + niOi0lO0i <= (wire_nilOi11l_dataout AND ((wire_nlill0Oll_w_lg_nl11lO01O52762w(0) AND wire_nlill0Oll_w_lg_nl11lO01l52763w(0)) AND wire_nlill0Oll_w_lg_nl11lO01i52765w(0))); + niOi0lO0l <= (niOi0lOll OR wire_niO01O0O_dataout); + niOi0lO0O <= (wire_nilOiOOl_w_lg_dataout49185w(0) AND wire_nilOiOOi_w_lg_dataout49186w(0)); + niOi0lO1i <= (wire_nlill0Oll_w_lg_nl11lOO1i45149w(0) AND niOi0lO1l); + niOi0lO1l <= (wire_nlill0Oll_w53689w(0) AND wire_nlill0Oll_w_lg_nl11lOlll45171w(0)); + niOi0lO1O <= (wire_nlill0Oll_w_lg_nl11lOO1l45164w(0) AND (wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOlOO44945w44946w52768w(0) AND wire_nlill0Oll_w_lg_nl11lOllO45169w(0))); + niOi0lOii <= (nl00l11iO AND wire_w_lg_niOi0lOil52614w(0)); + niOi0lOil <= (((((((((((((NOT (wire_nilOl11O_dataout XOR wire_nl0iO0l0i_dataout)) AND (NOT (wire_nilOl10i_dataout XOR wire_nl0iO0l0l_dataout))) AND (NOT (wire_nilOl10l_dataout XOR wire_nl0iO0l0O_dataout))) AND (NOT (wire_nilOl10O_dataout XOR wire_nl0iO0lii_dataout))) AND (NOT (wire_nilOl1ii_dataout XOR wire_nl0iO0lil_dataout))) AND (NOT (wire_nilOl1il_dataout XOR wire_nl0iO0liO_dataout))) AND (NOT (wire_nilOl1iO_dataout XOR wire_nl0iO0lli_dataout))) AND (NOT (wire_nilOl1li_dataout XOR wire_nl0iO0lll_dataout))) AND (NOT (wire_nilOl1ll_dataout XOR wire_nl0iO0llO_dataout))) AND (NOT (wire_nilOl1lO_dataout XOR wire_nl0iO0lOi_dataout))) AND (NOT (wire_nilOl1Oi_dataout XOR wire_nl0iO0lOl_dataout))) AND (NOT (wire_nilOl1Ol_dataout XOR wire_nl0iO0lOO_dataout))) AND (NOT (wire_nilOl1OO_dataout XOR wire_nl0iO0O1i_dataout))); + niOi0lOiO <= (wire_nilOi0li_dataout AND wire_nilOi00l_dataout); + niOi0lOli <= ((wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53757w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOi0lOll <= (niOi0lOOO OR niOi0lOlO); + niOi0lOlO <= (wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOi0lOOi <= ((niOi0lOOO OR niOi0lOOl) OR wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0)); + niOi0lOOl <= wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0); + niOi0lOOO <= wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0); + niOi0O00i <= (wire_nl1lOO1li_dataout AND wire_nl1lOO10O_dataout); + niOi0O00l <= (wire_nl1lOO1ii_dataout AND wire_nl1lOO10l_dataout); + niOi0O00O <= (wire_nl1lOO1il_dataout AND wire_nl1lOO10l_dataout); + niOi0O01i <= (wire_nl1lOOiOl_w_lg_w52547w52549w(0) AND wire_nl1lOOi0l_w_lg_dataout52550w(0)); + niOi0O01l <= (wire_nl1lOO1il_dataout AND wire_nl1lOO10O_dataout); + niOi0O01O <= (wire_nl1lOO1iO_dataout AND wire_nl1lOO10O_dataout); + niOi0O0ii <= (wire_nl1lOO1iO_dataout AND wire_nl1lOO10l_dataout); + niOi0O0il <= (wire_nl1lOO1li_dataout AND wire_nl1lOO10l_dataout); + niOi0O0iO <= (wire_nl1lOO1ii_dataout AND wire_nl1lOO10i_dataout); + niOi0O0li <= (wire_nl1lOO1il_dataout AND wire_nl1lOO10i_dataout); + niOi0O0ll <= (wire_nl1lOO1iO_dataout AND wire_nl1lOO10i_dataout); + niOi0O0lO <= (wire_nl1lOO1li_dataout AND wire_nl1lOO10i_dataout); + niOi0O0Oi <= (wire_nl1lOO1ii_dataout AND wire_nl1lOO11O_dataout); + niOi0O0Ol <= (wire_nl1lOO1il_dataout AND wire_nl1lOO11O_dataout); + niOi0O0OO <= (wire_nl1lOO1iO_dataout AND wire_nl1lOO11O_dataout); + niOi0O10i <= (nl0l0100l AND (nl0l0101O AND wire_nlill0Oll_w_lg_nl0l0101l52252w(0))); + niOi0O10l <= (nl0l0100l AND (wire_nlill0Oll_w_lg_nl0l0101O52251w(0) AND nl0l0101l)); + niOi0O10O <= (nl0l0100l AND (wire_nlill0Oll_w_lg_nl0l0101O52251w(0) AND wire_nlill0Oll_w_lg_nl0l0101l52252w(0))); + niOi0O11i <= (nlOili1l OR nlOil01i); + niOi0O11l <= ((((wire_nl0i1lOlO_w_lg_dataout52600w(0) AND wire_nl0i1lOll_w_lg_dataout52601w(0)) AND wire_nl0i1lOli_w_lg_dataout52603w(0)) AND wire_nl0i1lOiO_w_lg_dataout52605w(0)) AND wire_nl0i1lOil_w_lg_dataout52607w(0)); + niOi0O11O <= (nl0l0100l AND (nl0l0101O AND nl0l0101l)); + niOi0O1ii <= (((((wire_nlill0Oll_w_lg_nl0illlli52592w(0) AND wire_nlill0Oll_w_lg_nl0illliO52587w(0)) AND wire_nlill0Oll_w_lg_nl0illlil52588w(0)) AND wire_nlill0Oll_w_lg_nl0illlii52590w(0)) AND wire_nlill0Oll_w_lg_nl0illl0O52596w(0)) AND wire_nlill0Oll_w_lg_nl0illl0l52598w(0)); + niOi0O1il <= ((wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w5086w(0) AND wire_nl1lOOlOO_w_lg_dataout52012w(0)) AND wire_nl1lOOlOl_dataout); + niOi0O1iO <= ((wire_nlill0Oll_w_lg_nl0illliO52587w(0) AND wire_nlill0Oll_w_lg_nl0illlil52588w(0)) AND wire_nlill0Oll_w_lg_nl0illlii52590w(0)); + niOi0O1li <= (niOii1OOl AND wire_nlill0Oll_w_lg_nlil1lOii52245w(0)); + niOi0O1ll <= (((((((((((((((((((((((((((((((wire_nlill0Oll_w_lg_nl0l0Oili46243w(0) AND wire_nlill0Oll_w_lg_nl0l0OiiO46244w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oiil46245w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oiii46246w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oi0O46247w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oi0l46248w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oi0i46249w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oi1O46250w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oi1l46251w(0)) AND wire_nlill0Oll_w_lg_nl0l0Oi1i46252w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0OO46253w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0Ol46254w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0Oi46255w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0lO46256w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0ll46257w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0li46258w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0iO46259w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0il46260w(0)) AND wire_nlill0Oll_w_lg_nl0l0O0ii46261w(0)) AND wire_nlill0Oll_w_lg_nl0l0O00O46262w(0)) AND wire_nlill0Oll_w_lg_nl0l0O00l46263w(0)) AND wire_nlill0Oll_w_lg_nl0l0O00i46264w(0)) AND wire_nlill0Oll_w_lg_nl0l0O01O46265w(0)) AND wire_nlill0Oll_w_lg_nl0l0O01l46266w(0)) AND wire_nlill0Oll_w_lg_nl0l0O01i46267w(0)) AND wire_nlill0Oll_w_lg_nl0l0O1OO46268w(0)) AND wire_nlill0Oll_w_lg_nl0l0O1Ol46269w(0)) AND wire_nlill0Oll_w_lg_nl0l0O1Oi46270w(0)) AND wire_nlill0Oll_w_lg_nl0l0O1lO46271w(0)) AND wire_nlill0Oll_w_lg_nl0l0O1ll46272w(0)) AND wire_nlill0Oll_w_lg_nl0l0O1li46273w(0)) AND wire_nlill0Oll_w_lg_nl0l0O1iO46274w(0)); + niOi0O1lO <= (nl011l1ii AND (niOi0Oiil OR (wire_nl1lOOO0l_dataout OR (niOi0O1Ol OR wire_nl1lOOl0i_dataout)))); + niOi0O1Oi <= (nl011l1ii AND niOi0O1Ol); + niOi0O1Ol <= (nl1OilOil OR (nl1Oillll AND nl1Oillli)); + niOi0O1OO <= (wire_nl1lOOiOl_w_lg_w_lg_w52547w52549w52552w(0) AND wire_w_lg_niOi0O01i52553w(0)); + niOi0Oi0i <= (wire_nl1lOO11O_dataout AND wire_nl1lOO10O_w_lg_w_lg_dataout52141w52142w(0)); + niOi0Oi0l <= (wire_nl1lOO10O_dataout AND wire_nl1lOO11O_dataout); + niOi0Oi0O <= (((((((wire_w_lg_niOi0Oiii52517w(0) AND wire_nl0ilOiiO_w_lg_dataout52518w(0)) AND wire_nl0ilOiil_w_lg_dataout52520w(0)) AND wire_nl0ilOiii_w_lg_dataout52522w(0)) AND wire_nl0ilOi0O_w_lg_dataout52524w(0)) AND wire_nl0ilOi0l_w_lg_dataout52526w(0)) AND wire_nl0ilOi0i_w_lg_dataout52528w(0)) AND wire_w_lg_niOilO11i52530w(0)); + niOi0Oi1i <= (wire_nl1lOO1li_dataout AND wire_nl1lOO11O_dataout); + niOi0Oi1l <= ((wire_nl1lOO10O_w52150w(0) OR (wire_nl1lOO10O_w_lg_w_lg_w_lg_dataout52141w52142w52151w(0) AND wire_nl1lOO11O_w_lg_dataout52144w(0))) OR (((wire_nl1lOO10O_dataout AND wire_nl1lOO10l_dataout) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_w_lg_dataout52144w(0))); + niOi0Oi1O <= (wire_nl1lOO10O_dataout AND (wire_nl1lOO10i_dataout AND wire_nl1lOO11O_w_lg_dataout52144w(0))); + niOi0Oiii <= ((nl011l1ii AND niOii1Oll) AND (niOi0Oiil OR niOii1llO)); + niOi0Oiil <= (wire_nlill0Oll_w_lg_nl1OilOil55037w(0) AND wire_nlill0Oll_w_lg_nl1Oillll55051w(0)); + niOi0OiiO <= (wire_nlill0Oll_w_lg_nl0ilOlll52123w(0) AND wire_w_lg_niOi0Oili52124w(0)); + niOi0Oili <= ((((((((NOT (nl0ilOl1O XOR wire_nl0l0i1iO_dataout)) AND (NOT (wire_nl0iO0i0O_dataout XOR nl0ilOl0i))) AND (NOT (wire_nl0iO0i0l_dataout XOR nl0ilOl0l))) AND (NOT (wire_nl0iO0i0i_dataout XOR nl0ilOl0O))) AND (NOT (wire_nl0iO0i1O_dataout XOR nl0ilOlii))) AND (NOT (wire_nl0iO0i1l_dataout XOR nl0ilOlil))) AND (NOT (wire_nl0iO0i1i_dataout XOR nl0ilOliO))) AND (NOT (wire_nl0iO00Ol_dataout XOR nl0ilOlli))); + niOi0Oill <= (wire_nl0iO0i1i_dataout XOR nl0ilOliO); + niOi0OilO <= (wire_nl0iO0i1l_dataout XOR nl0ilOlil); + niOi0OiOi <= (wire_nl0iO0i1O_dataout XOR nl0ilOlii); + niOi0OiOl <= (wire_nl0iO0i0i_dataout XOR nl0ilOl0O); + niOi0OiOO <= (wire_nl0iO0i0l_dataout XOR nl0ilOl0l); + niOi0Ol0i <= ((NOT k_dev(0)) AND wire_w_lg_w_k_dev_range52047w52497w(0)); + niOi0Ol0l <= wire_w_lg_w_k_dev_range52044w52499w(0); + niOi0Ol0O <= ((NOT k_dev(0)) AND k_dev(1)); + niOi0Ol1i <= (wire_nl0iO0i0O_dataout XOR nl0ilOl0i); + niOi0Ol1l <= (nl0ilOl1O XOR wire_nl0l0i1iO_dataout); + niOi0Ol1O <= (niOii011i OR niOii1OOO); + niOi0Olii <= (wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOi0Olil <= (nl0iOiiOO OR nl0iOiiOl); + niOi0OliO <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11OOO52342w52344w52346w(0) AND wire_nlill0Oll_w_lg_nl0l11OlO52347w(0)); + niOi0Olli <= (wire_nl0l0111l_w_lg_w_lg_w_lg_dataout52335w52337w52339w(0) AND wire_nl0l1OOOl_w_lg_dataout52340w(0)); + niOi0Olll <= (wire_nl0l0111l_w52414w(0) AND wire_nl0l1OOOi_w_lg_dataout52411w(0)); + niOi0OllO <= (((wire_nl0l0111l_w_lg_dataout52416w(0) AND wire_nl0l1OOOO_w_lg_dataout52338w(0)) AND wire_nl0l1OOOl_w_lg_dataout52340w(0)) AND wire_nl0l1OOOi_w_lg_dataout52411w(0)); + niOi0OlOi <= ((wire_nl0l0111l_w_lg_w_lg_w_lg_dataout52335w52337w52339w(0) AND wire_nl0l1OOOl_w_lg_dataout52340w(0)) AND wire_nl0l1OOOi_dataout); + niOi0OlOl <= ((wire_nl0l0111l_w_lg_w_lg_w_lg_dataout52335w52337w52339w(0) AND wire_nl0l1OOOl_w_lg_dataout52340w(0)) AND wire_nl0l1OOOi_w_lg_dataout52411w(0)); + niOi0OlOO <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52353w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OO0i <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52362w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OO0l <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52362w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_dataout); + niOi0OO0O <= (wire_nl0l1OOlO_w52366w(0) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OO1i <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52353w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_dataout); + niOi0OO1l <= (wire_nl0l1OOlO_w52359w(0) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OO1O <= (wire_nl0l1OOlO_w52359w(0) AND wire_nl0l1OOil_dataout); + niOi0OOii <= (wire_nl0l1OOlO_w52366w(0) AND wire_nl0l1OOil_dataout); + niOi0OOil <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52370w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OOiO <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52370w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_dataout); + niOi0OOli <= (wire_nl0l1OOlO_w52374w(0) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OOll <= (wire_nl0l1OOlO_w52374w(0) AND wire_nl0l1OOil_dataout); + niOi0OOlO <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52377w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OOOi <= ((wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52377w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_dataout); + niOi0OOOl <= (wire_nl0l1OOlO_w52381w(0) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOi0OOOO <= (wire_nl0l1OOlO_w52381w(0) AND wire_nl0l1OOil_dataout); + niOi1000i <= (nl11Oii0O AND niOi1001l); + niOi1000l <= (wire_nlill0Oll_w_lg_nl111OO1l60374w(0) AND (((wire_nlill0Oll_w_lg_nl1110liO60375w(0) AND wire_nlill0Oll_w_lg_nl1110lil60376w(0)) AND wire_nlill0Oll_w_lg_nl1110lii60378w(0)) AND wire_nlill0Oll_w_lg_nl1110l0O60380w(0))); + niOi1000O <= ((niOi10iiO AND niOi10iOO) OR niOi100il); + niOi1001i <= (nl11Oii0O AND niOi101Ol); + niOi1001l <= (wire_nlill0Oll_w_lg_nl11OiOOO61551w(0) AND wire_nlill0Oll_w_lg_nl11OiOOl61552w(0)); + niOi1001O <= (nl11Oilli AND niOi1001l); + niOi100ii <= ((niOi10iiO AND niOi100il) OR niOi100li); + niOi100il <= (nl11Oii0l AND wire_nlill0Oll_w_lg_nl11Oii0i60369w(0)); + niOi100iO <= ((niOi10iiO AND niOi100li) OR niOilOi1O); + niOi100li <= (wire_nlill0Oll_w_lg_nl11Oii0l59845w(0) AND nl11Oii0i); + niOi100ll <= (wire_w_lg_niOi10iiO60253w(0) AND niOi10i1l); + niOi100lO <= (niOi10iiO AND wire_w_lg_niOi10i1l60239w(0)); + niOi100Oi <= (wire_nlill0Oll_w_lg_nl11OO0li59541w(0) AND (wire_nlill0Oll_w_lg_nl11OO0ll59542w(0) AND (wire_nliliO10i_w_lg_nl11OOi1O60227w(0) AND wire_nlill0Oll_w_lg_w_lg_nl11OiliO60228w60229w(0)))); + niOi100Ol <= (((((((((wire_nl1000i_w_lg_nlOil1ll60273w(0) AND wire_nl1000i_w_lg_nlOil1li60274w(0)) AND wire_nl1000i_w_lg_nlOil1iO60276w(0)) AND wire_nl1000i_w_lg_nlOil1il60278w(0)) AND wire_nl1000i_w_lg_nlOil1ii60280w(0)) AND wire_nl1000i_w_lg_nlOil10O60282w(0)) AND wire_nl1000i_w_lg_nlOil10l60284w(0)) AND wire_nl1000i_w_lg_nlOil10i60286w(0)) AND wire_nl1000i_w_lg_nlOil11O59625w(0)) AND wire_nl1000i_w_lg_nlOil11l59626w(0)); + niOi100OO <= ((((wire_nlill0Oll_w_lg_nl0i00i0l60213w(0) AND wire_nlill0Oll_w_lg_nl0i00i0i60221w(0)) AND wire_nlill0Oll_w_lg_nl0i00i1O60215w(0)) AND wire_nlill0Oll_w_lg_nl0i00i1l60364w(0)) AND wire_nlill0Oll_w_lg_nl0i00i1i60366w(0)); + niOi1010i <= (wire_nilOliOO_dataout AND niOi1i00i); + niOi1010l <= (niOi1i00i AND niOi1010O); + niOi1010O <= (wire_nilOliOl_dataout AND wire_nilOliOi_w_lg_dataout61595w(0)); + niOi1011i <= (nl111OO0l OR wire_nl111OlOl_o); + niOi1011l <= (((((((((((wire_nilOli1i_w_lg_dataout61571w(0) AND wire_nilOl0OO_w_lg_dataout61572w(0)) AND wire_nilOl0Ol_w_lg_dataout61574w(0)) AND wire_nilOl0Oi_w_lg_dataout61576w(0)) AND wire_nilOl0lO_w_lg_dataout61578w(0)) AND wire_nilOl0ll_w_lg_dataout61580w(0)) AND wire_nilOl0li_w_lg_dataout61582w(0)) AND wire_nilOl0iO_w_lg_dataout61584w(0)) AND wire_nilOl0il_w_lg_dataout61586w(0)) AND wire_nilOl0ii_w_lg_dataout61588w(0)) AND wire_nilOl00O_w_lg_dataout61590w(0)) AND wire_nilOl00l_w_lg_dataout61592w(0)); + niOi1011O <= (((((((wire_nilOliiO_w_lg_dataout61556w(0) AND wire_nilOliil_w_lg_dataout61557w(0)) AND wire_nilOliii_w_lg_dataout61559w(0)) AND wire_nilOli0O_w_lg_dataout61561w(0)) AND wire_nilOli0l_w_lg_dataout61563w(0)) AND wire_nilOli0i_w_lg_dataout61565w(0)) AND wire_nilOli1O_w_lg_dataout61567w(0)) AND wire_nilOli1l_w_lg_dataout61569w(0)); + niOi101ii <= (niOi1i00i AND niOi101il); + niOi101il <= (wire_nilOliOl_w_lg_dataout61594w(0) AND wire_nilOliOi_dataout); + niOi101iO <= (wire_nilOliOl_w_lg_dataout61594w(0) AND wire_nilOliOi_w_lg_dataout61595w(0)); + niOi101li <= (niOi1i00i AND niOi101iO); + niOi101ll <= (nl11OiOOO AND wire_nlill0Oll_w_lg_nl11OiOOl61552w(0)); + niOi101lO <= (nl11Oilli AND niOi101ll); + niOi101Oi <= (nl11Oii0O AND niOi101ll); + niOi101Ol <= (wire_nlill0Oll_w_lg_nl11OiOOO61551w(0) AND nl11OiOOl); + niOi101OO <= (nl11Oilli AND niOi101Ol); + niOi10i0i <= (((((nl11OOi1l OR nl11OOi1i) OR nl11OO0OO) OR nl11OO0Ol) OR nl11OO0Oi) OR nl11OO0lO); + niOi10i0l <= ((nl11OOi1l OR nl11OOi1i) OR nl11OO0OO); + niOi10i0O <= (nl11OOi1i OR nl11OO0ll); + niOi10i1i <= (wire_nlill0Oll_w60217w(0) AND wire_nlill0Oll_w_lg_nl0i00i0O60218w(0)); + niOi10i1l <= ((wire_nlill0Oll_w_lg_nl11OO0il60206w(0) OR (wire_nliliO10i_w_lg_nl11OO0ii59868w(0) AND (nl11OO0Ol OR nl11OO0Oi))) OR wire_nlill0Oll_w_lg_nl11OO0lO60209w(0)); + niOi10i1O <= ((((nl11OO0Ol OR nl11OO0Oi) OR nl11OO0lO) OR nl11OO0ll) OR nl11OO0li); + niOi10iii <= (((nl11OOi1l OR nl11OOi1i) OR nl11OO0OO) OR nl11OO0ll); + niOi10iil <= (niOi10iOi OR niOi10iiO); + niOi10iiO <= (wire_nilOO01O_dataout AND (niOi1i1Ol OR nl11lOO0i)); + niOi10ili <= (wire_nliliO10i_w_lg_nl11OO0ii59868w(0) AND wire_nl1000i_w_lg_nlOili0O4300w(0)); + niOi10ill <= (wire_nl10ii1lO_dataout AND nlOili0O); + niOi10ilO <= (wire_nlill0Oll_w_lg_nl11OOi0i59976w(0) AND wire_nliliO10i_w_lg_nl11OO0ii59868w(0)); + niOi10iOi <= (niOi10iOl OR wire_nlill0Oll_w_lg_nl11Oii0l59845w(0)); + niOi10iOl <= (wire_nilOOO0i_w_lg_dataout47830w(0) OR wire_nl11Oilii_dataout); + niOi10iOO <= (nl11Oii0l AND nl11Oii0i); + niOi10l0i <= (nl0i00iii AND nl0i00i0O); + niOi10l0l <= (wire_nlill0Oll_w_lg_nl11OO0lO59867w(0) AND wire_nliliO10i_w_lg_nl11OO0ii59868w(0)); + niOi10l0O <= ((niOi10lil OR niOi10lii) AND nl11OOi1O); + niOi10l1i <= (niOi10lOl AND wire_nl10ii1lO_w_lg_dataout59873w(0)); + niOi10l1l <= (wire_w_lg_niOi10lOO59856w(0) AND (niOi1i10O AND nlOili0l)); + niOi10l1O <= (wire_w_lg_niOi10lOO59856w(0) AND nlOili0l); + niOi10lii <= (wire_nilOOO0i_dataout AND (((NOT (wire_nl101Oi1O_o OR wire_nl101O0OO_o)) AND (wire_w_lg_niOi10O0i59855w(0) AND (wire_w_lg_niOi10lOO59856w(0) AND (wire_w_lg_niOi1i10O59857w(0) AND (niOi10liO AND nlOili0l))))) AND wire_nl11101li_dataout)); + niOi10lil <= (wire_nilOOO0i_dataout AND ((NOT (wire_nl101Oi1i_o OR wire_nl101O0OO_o)) AND wire_w_lg_w_lg_niOi1i10O59849w59850w(0))); + niOi10liO <= ((wire_nlill0Oll_w_lg_nl11OO00O59842w(0) AND wire_nl11Oilii_w_lg_dataout59843w(0)) AND wire_nlill0Oll_w_lg_nl11Oii0l59845w(0)); + niOi10lli <= ((((((((NOT (nl0OOO1iO XOR nlOiiiii)) AND (NOT (nl0OOO1li XOR nlOiiiil))) AND (NOT (nl0OOO1ll XOR nlOiiiiO))) AND (NOT (nl0OOO1lO XOR nlOiiili))) AND (NOT (nl0OOO1Oi XOR nlOiiill))) AND (NOT (nl0OOO1Ol XOR nlOiiilO))) AND (NOT (nl0OOO1OO XOR nlOiiiOi))) AND (NOT (nl0OOO01i XOR nlOiiiOl))); + niOi10lll <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlOil0OO59692w60307w60313w(0) AND wire_nl1000i_w_lg_nlOil0lO60309w(0)) AND nlOil0ll); + niOi10llO <= (nl11OO0ll AND nl0i00i0O); + niOi10lOi <= (niOi1i10O AND nl11OOi1O); + niOi10lOl <= (((k_gbl_hip(32) AND nlOili1i) AND wire_nlO0Olll_dataout) OR nlOili1l); + niOi10lOO <= ((wire_w_lg_niOi1i00O59724w(0) AND wire_nl1000i_w_lg_nlOili1i59697w(0)) AND niOi10O1i); + niOi10O0i <= ((niOi1i00l AND nlOili0l) AND ((((niOi10O0l AND niOi10OiO) AND wire_w_lg_niOili0ll53394w(0)) OR wire_w_lg_niOi10Oil59710w(0)) OR wire_w_lg_niOi10O0O59712w(0))); + niOi10O0l <= ((((wire_nl1000i_w60343w(0) AND wire_nl1000i_w_lg_nlOiil1O60344w(0)) AND wire_nl1000i_w_lg_nlOiil1l60346w(0)) AND wire_nl1000i_w_lg_nlOiil1i60348w(0)) AND wire_nl1000i_w_lg_nlOiiiOO60350w(0)); + niOi10O0O <= (niOi10Oii AND niOi10OiO); + niOi10O1i <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlOil0OO59692w60307w60313w(0) AND wire_nl1000i_w_lg_nlOil0lO60309w(0)) AND wire_nl1000i_w_lg_nlOil0ll60311w(0)); + niOi10O1l <= (nl11OOOii OR nl11OO0il); + niOi10O1O <= (wire_w_lg_niOi1i00l59715w(0) OR wire_niO01O0O_dataout); + niOi10Oii <= ((((wire_nl1000i_w60343w(0) AND wire_nl1000i_w_lg_nlOiil1O60344w(0)) AND wire_nl1000i_w_lg_nlOiil1l60346w(0)) AND nlOiil1i) AND nlOiiiOO); + niOi10Oil <= (niOi10Oli AND niOi10OiO); + niOi10OiO <= (wire_nl1000i_w_lg_w_lg_w_lg_nlOili1l60355w60356w60357w(0) AND wire_nl1000i_w_lg_nlOil0Ol59700w(0)); + niOi10Oli <= ((((wire_nl1000i_w60343w(0) AND wire_nl1000i_w_lg_nlOiil1O60344w(0)) AND wire_nl1000i_w_lg_nlOiil1l60346w(0)) AND wire_nl1000i_w_lg_nlOiil1i60348w(0)) AND nlOiiiOO); + niOi10Oll <= (((wire_nl1000i_w_lg_w_lg_nlOil0OO59692w60307w(0) AND wire_nl1000i_w_lg_nlOil0Oi59694w(0)) AND wire_nl1000i_w_lg_nlOil0lO60309w(0)) AND wire_nl1000i_w_lg_nlOil0ll60311w(0)); + niOi10OlO <= (wire_nl1000i_w59696w(0) AND wire_nl1000i_w_lg_nlOili1i59697w(0)); + niOi10OOi <= (((((((((wire_nl10il1il_w_lg_dataout60290w(0) AND wire_nl10il1ii_w_lg_dataout60291w(0)) AND wire_nl10il10O_w_lg_dataout60293w(0)) AND wire_nl10il10l_w_lg_dataout60295w(0)) AND wire_nl10il10i_w_lg_dataout60297w(0)) AND wire_nl10il11O_w_lg_dataout60299w(0)) AND wire_nl10il11l_w_lg_dataout60301w(0)) AND wire_nl10il11i_w_lg_dataout60303w(0)) AND wire_nl10iiOOO_w_lg_dataout59596w(0)) AND wire_nl10iiOOl_w_lg_dataout59597w(0)); + niOi10OOl <= (k_gbl_hip(32) AND wire_nlO0Olll_dataout); + niOi10OOO <= (niOi10OOi AND nlOili1l); + niOi11ill <= (niOO0OlOl XOR niOO0OllO); + niOi11ilO <= (((((((NOT (test_in_hip(0) XOR niOO0OO1O)) AND (NOT (test_in_hip(1) XOR niOO0OO0i))) AND (NOT (test_in_hip(2) XOR niOO0OO0l))) AND (NOT (test_in_hip(3) XOR niOO0OO0O))) AND (NOT (test_in_hip(5) XOR niOO0OOii))) AND (NOT (test_in_hip(6) XOR niOO0OOil))) AND (NOT (test_in_hip(31) XOR niOO0OOiO))); + niOi11iOi <= (niOO0OlOO XOR niOO0Olil); + niOi11iOl <= (niOOi01OO XOR niOOi01Oi); + niOi11iOO <= (((((((((((((((((NOT (test_in_hip(4) XOR niOOi000i)) AND (NOT (test_in_hip(7) XOR niOOi000l))) AND (NOT (test_in_hip(16) XOR niOOi000O))) AND (NOT (test_in_hip(17) XOR niOOi00ii))) AND (NOT (test_in_hip(18) XOR niOOi00il))) AND (NOT (test_in_hip(19) XOR niOOi00iO))) AND (NOT (test_in_hip(20) XOR niOOi00li))) AND (NOT (test_in_hip(21) XOR niOOi00ll))) AND (NOT (test_in_hip(22) XOR niOOi00lO))) AND (NOT (test_in_hip(23) XOR niOOi00Oi))) AND (NOT (test_in_hip(24) XOR niOOi00Ol))) AND (NOT (test_in_hip(25) XOR niOOi00OO))) AND (NOT (test_in_hip(26) XOR niOOi0i1i))) AND (NOT (test_in_hip(27) XOR niOOi0i1l))) AND (NOT (test_in_hip(28) XOR niOOi0i1O))) AND (NOT (test_in_hip(29) XOR niOOi0i0i))) AND (NOT (test_in_hip(30) XOR niOOi0i0l))); + niOi11l0i <= (wire_w_lg_w_test_in_hip_range61746w61749w(0) AND test_in_hip(15)); + niOi11l0l <= (((NOT test_in_hip(13)) AND wire_w_lg_w_test_in_hip_range61747w61748w(0)) AND test_in_hip(15)); + niOi11l0O <= ((test_in_hip(13) AND test_in_hip(14)) AND (NOT test_in_hip(15))); + niOi11l1i <= (niOOi001i XOR niOOi01iO); + niOi11l1l <= ((test_in_hip(13) AND test_in_hip(14)) AND test_in_hip(15)); + niOi11l1O <= (((NOT test_in_hip(13)) AND test_in_hip(14)) AND test_in_hip(15)); + niOi11lii <= (((NOT test_in_hip(13)) AND test_in_hip(14)) AND (NOT test_in_hip(15))); + niOi11lil <= (wire_w_lg_w_test_in_hip_range61746w61749w(0) AND (NOT test_in_hip(15))); + niOi11liO <= ((((NOT test_in_hip(8)) AND test_in_hip(9)) AND (NOT test_in_hip(10))) AND (NOT test_in_hip(11))); + niOi11lli <= ((wire_w_lg_w_test_in_hip_range61715w61726w(0) AND (NOT test_in_hip(10))) AND (NOT test_in_hip(11))); + niOi11lll <= (((test_in_hip(8) AND test_in_hip(9)) AND (NOT test_in_hip(10))) AND (NOT test_in_hip(11))); + niOi11llO <= ((((NOT test_in_hip(8)) AND wire_w_lg_w_test_in_hip_range61717w61725w(0)) AND test_in_hip(10)) AND (NOT test_in_hip(11))); + niOi11lOi <= ((wire_w_lg_w_test_in_hip_range61715w61726w(0) AND test_in_hip(10)) AND (NOT test_in_hip(11))); + niOi11lOl <= ((((NOT test_in_hip(8)) AND wire_w_lg_w_test_in_hip_range61717w61725w(0)) AND (NOT test_in_hip(10))) AND (NOT test_in_hip(11))); + niOi11lOO <= ((((NOT test_in_hip(8)) AND test_in_hip(9)) AND test_in_hip(10)) AND (NOT test_in_hip(11))); + niOi11O0i <= ((((NOT test_in_hip(8)) AND test_in_hip(9)) AND (NOT test_in_hip(10))) AND test_in_hip(11)); + niOi11O0l <= (((((((((((wire_nlill0Oll_w_lg_nl1110OOl61660w(0) AND wire_nlill0Oll_w_lg_nl1110OOi61661w(0)) AND wire_nlill0Oll_w_lg_nl1110OlO61663w(0)) AND wire_nlill0Oll_w_lg_nl1110Oll61665w(0)) AND wire_nlill0Oll_w_lg_nl1110Oli61667w(0)) AND wire_nlill0Oll_w_lg_nl1110OiO61669w(0)) AND wire_nlill0Oll_w_lg_nl1110Oil61671w(0)) AND wire_nlill0Oll_w_lg_nl1110Oii61673w(0)) AND wire_nlill0Oll_w_lg_nl1110O0O61675w(0)) AND wire_nlill0Oll_w_lg_nl1110O0l61677w(0)) AND wire_nlill0Oll_w_lg_nl1110O0i61679w(0)) AND wire_nlill0Oll_w_lg_nl1110O1O61681w(0)); + niOi11O0O <= (((((((((((wire_nlill0Oll_w_lg_nl1110i0i61683w(0) AND wire_nlill0Oll_w_lg_nl1110i1O61684w(0)) AND wire_nlill0Oll_w_lg_nl1110i1l61686w(0)) AND wire_nlill0Oll_w_lg_nl1110i1i61688w(0)) AND wire_nlill0Oll_w_lg_nl11100OO61690w(0)) AND wire_nlill0Oll_w_lg_nl11100Ol61692w(0)) AND wire_nlill0Oll_w_lg_nl11100Oi61694w(0)) AND wire_nlill0Oll_w_lg_nl11100lO61696w(0)) AND wire_nlill0Oll_w_lg_nl11100ll61698w(0)) AND wire_nlill0Oll_w_lg_nl11100li61700w(0)) AND wire_nlill0Oll_w_lg_nl11100iO61702w(0)) AND wire_nlill0Oll_w_lg_nl11101il61704w(0)); + niOi11O1i <= (((test_in_hip(8) AND test_in_hip(9)) AND test_in_hip(10)) AND (NOT test_in_hip(11))); + niOi11O1l <= ((((NOT test_in_hip(8)) AND wire_w_lg_w_test_in_hip_range61717w61725w(0)) AND (NOT test_in_hip(10))) AND test_in_hip(11)); + niOi11O1O <= ((wire_w_lg_w_test_in_hip_range61715w61726w(0) AND (NOT test_in_hip(10))) AND test_in_hip(11)); + niOi11Oii <= (((((((((((wire_nlill0Oll_w_lg_nl1110liO60375w(0) AND wire_nlill0Oll_w_lg_nl1110lil60376w(0)) AND wire_nlill0Oll_w_lg_nl1110lii60378w(0)) AND wire_nlill0Oll_w_lg_nl1110l0O60380w(0)) AND wire_nlill0Oll_w_lg_nl1110l0l61644w(0)) AND wire_nlill0Oll_w_lg_nl1110l0i61646w(0)) AND wire_nlill0Oll_w_lg_nl1110l1O61648w(0)) AND wire_nlill0Oll_w_lg_nl1110l1l61650w(0)) AND wire_nlill0Oll_w_lg_nl1110l1i61652w(0)) AND wire_nlill0Oll_w_lg_nl1110iOO61654w(0)) AND wire_nlill0Oll_w_lg_nl1110iOl61656w(0)) AND wire_nlill0Oll_w_lg_nl1110iOi61658w(0)); + niOi11Oil <= (((((((wire_nlill0Oll_w_lg_nl1110O1l61614w(0) AND wire_nlill0Oll_w_lg_nl1110O1i61615w(0)) AND wire_nlill0Oll_w_lg_nl1110lOO61617w(0)) AND wire_nlill0Oll_w_lg_nl1110lOl61619w(0)) AND wire_nlill0Oll_w_lg_nl1110lOi61621w(0)) AND wire_nlill0Oll_w_lg_nl1110llO61623w(0)) AND wire_nlill0Oll_w_lg_nl1110lll61625w(0)) AND wire_nlill0Oll_w_lg_nl1110lli61627w(0)); + niOi11OiO <= (nl111OO1i OR wire_w_lg_niOi11Oli61464w(0)); + niOi11Oli <= (((((((wire_nlill0Oll_w_lg_nl1110ilO61629w(0) AND wire_nlill0Oll_w_lg_nl1110ill61630w(0)) AND wire_nlill0Oll_w_lg_nl1110ili61632w(0)) AND wire_nlill0Oll_w_lg_nl1110iiO61634w(0)) AND wire_nlill0Oll_w_lg_nl1110iil61636w(0)) AND wire_nlill0Oll_w_lg_nl1110iii61638w(0)) AND wire_nlill0Oll_w_lg_nl1110i0O61640w(0)) AND wire_nlill0Oll_w_lg_nl1110i0l61642w(0)); + niOi11Oll <= (nl111OO0l OR wire_w_lg_niOi11OlO61462w(0)); + niOi11OlO <= (((((((wire_nlill0Oll_w_lg_nl111i1ii61599w(0) AND wire_nlill0Oll_w_lg_nl111i10O61600w(0)) AND wire_nlill0Oll_w_lg_nl111i10l61602w(0)) AND wire_nlill0Oll_w_lg_nl111i10i61604w(0)) AND wire_nlill0Oll_w_lg_nl111i11O61606w(0)) AND wire_nlill0Oll_w_lg_nl111i11l61608w(0)) AND wire_nlill0Oll_w_lg_nl111i11i61610w(0)) AND wire_nlill0Oll_w_lg_nl1110OOO61612w(0)); + niOi11OOi <= (nl111OO1i OR wire_nl111O0ll_o); + niOi11OOl <= (nl111OO1l OR wire_nl111Oi1O_o); + niOi11OOO <= (nl111OO1O OR wire_nl111Oili_o); + niOi1i00i <= (wire_nilOll1i_dataout AND ((wire_nlill0lOl_w_lg_dataout59394w(0) AND wire_nlill0lOi_w_lg_dataout59395w(0)) AND wire_nlill0llO_w_lg_dataout59397w(0))); + niOi1i00l <= (wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0) OR wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0)); + niOi1i00O <= ((wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) OR wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0)) OR wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0)); + niOi1i01i <= ((wire_w_lg_w_lg_niOi1i01O59406w59407w(0) AND wire_nlill0Oll_w_lg_nl10iOOll59408w(0)) AND niOO10O0i); + niOi1i01l <= ((((((((NOT (wire_nilOOO0i_dataout AND nl10ilOOl)) AND (NOT (wire_nilOOO0l_dataout AND nl10iOO1O))) AND (NOT (wire_nilOOO0O_dataout AND nl10iOO0i))) AND (NOT (wire_nilOOOii_dataout AND nl10iOO0l))) AND (NOT (wire_nilOOOil_dataout AND nl10iOO0O))) AND (NOT (wire_nilOOOiO_dataout AND nl10iOOii))) AND (NOT (wire_nilOOOli_dataout AND nl10iOOil))) AND (NOT (wire_nilOOOll_dataout AND nl10iOOiO))); + niOi1i01O <= (wire_nilOO01O_dataout AND wire_nilOi11i_w_lg_dataout59400w(0)); + niOi1i0ii <= (wire_nl0101llO_dataout AND wire_nl0101lll_w_lg_dataout59086w(0)); + niOi1i0il <= (wire_nl0101llO_w_lg_dataout59085w(0) AND wire_nl0101lll_dataout); + niOi1i0iO <= (wire_nl0101llO_w_lg_dataout59085w(0) AND wire_nl0101lll_w_lg_dataout59086w(0)); + niOi1i0li <= (wire_nlill0Oll_w_lg_nl10lliil8959w(0) AND (NOT ((wire_nlill0Oll_w_lg_nl10llill58949w(0) AND wire_nlill0Oll_w_lg_nl10llili58950w(0)) AND wire_nlill0Oll_w_lg_nl10lliiO58952w(0)))); + niOi1i0ll <= (wire_nl011l0il_dataout OR niOi1ii1i); + niOi1i0lO <= (wire_nlill0Oll_w_lg_nl10lliOO54079w(0) AND (NOT ((wire_nlill0Oll_w_lg_nl10lll1O58937w(0) AND wire_nlill0Oll_w_lg_nl10lll1l58938w(0)) AND wire_nlill0Oll_w_lg_nl10lll1i58940w(0)))); + niOi1i0Oi <= ((((((((NOT (nl1i0110i XOR nl10O0lil)) AND (NOT (nl1i0110l XOR nl10O0liO))) AND (NOT (nl1i0110O XOR nl10O0lli))) AND (NOT (nl1i011ii XOR nl10O0lll))) AND (NOT (nl1i011il XOR nl10O0llO))) AND (NOT (nl1i011iO XOR nl10O0lOi))) AND (NOT (nl1i011li XOR nl10O0lOl))) AND (NOT (nl1i011ll XOR nl10O0lOO))); + niOi1i0Ol <= ((((((((NOT (nl1i1OOll XOR nl10O0iOO)) AND (NOT (nl1i1OOlO XOR nl10O0l1i))) AND (NOT (nl1i1OOOi XOR nl10O0l1l))) AND (NOT (nl1i1OOOl XOR nl10O0l1O))) AND (NOT (nl1i1OOOO XOR nl10O0l0i))) AND (NOT (nl1i0111i XOR nl10O0l0l))) AND (NOT (nl1i0111l XOR nl10O0l0O))) AND (NOT (nl1i0111O XOR nl10O0lii))); + niOi1i0OO <= ((((((((NOT (nl1i1Ol0O XOR nl10O00li)) AND (NOT (nl1i1Olii XOR nl10O00ll))) AND (NOT (nl1i1Olil XOR nl10O00lO))) AND (NOT (nl1i1OliO XOR nl10O00Oi))) AND (NOT (nl1i1Olli XOR nl10O00Ol))) AND (NOT (nl1i1Olll XOR nl10O00OO))) AND (NOT (nl1i1OllO XOR nl10O0i1i))) AND (NOT (nl1i1OlOi XOR nl10O0i1l))); + niOi1i10i <= ((wire_nilOll1i_dataout OR (wire_nilOO00O_w_lg_dataout47986w(0) OR niOi1i10l)) OR nl111i1il); + niOi1i10l <= (((((((wire_nilOOOll_w_lg_dataout59496w(0) AND wire_nilOOOli_w_lg_dataout59497w(0)) AND wire_nilOOOiO_w_lg_dataout59499w(0)) AND wire_nilOOOil_w_lg_dataout59501w(0)) AND wire_nilOOOii_w_lg_dataout59503w(0)) AND wire_nilOOO0O_w_lg_dataout59505w(0)) AND wire_nilOOO0l_w_lg_dataout59507w(0)) AND wire_nilOOO0i_w_lg_dataout47830w(0)); + niOi1i10O <= (((wire_nl10iOilO_w_lg_dataout59414w(0) AND wire_nl10iOill_w_lg_dataout59415w(0)) AND wire_nl10iOili_w_lg_dataout59417w(0)) AND wire_nlililOOl_dataout); + niOi1i11i <= ((NOT k_gbl_hip(32)) OR wire_nlO0Olll_w_lg_dataout59543w(0)); + niOi1i11l <= (wire_nilOO00O_dataout AND (wire_nilOO0ii_dataout AND wire_nlOilOO1O_dataout)); + niOi1i11O <= ((((((((NOT (k_cnt(120) XOR nl10ilO0O)) AND (NOT (k_cnt(121) XOR nl10ilOii))) AND (NOT (k_cnt(122) XOR nl10ilOil))) AND (NOT (k_cnt(123) XOR nl10ilOiO))) AND (NOT (k_cnt(124) XOR nl10ilOli))) AND (NOT (k_cnt(125) XOR nl10ilOll))) AND (NOT (k_cnt(126) XOR nl10ilOlO))) AND (NOT (k_cnt(127) XOR nl10ilOOi))); + niOi1i1ii <= ((wire_nlill0Oll_w_lg_nl0i000Ol59482w(0) AND wire_nlill0Oll_w_lg_nl0i000Oi59483w(0)) AND wire_nlill0Oll_w_lg_nl0i000lO59485w(0)); + niOi1i1il <= ((wire_nlill0Oll_w_lg_nl0i000Ol59482w(0) AND wire_nlill0Oll_w_lg_nl0i000Oi59483w(0)) AND nl0i000lO); + niOi1i1iO <= (wire_nlill0Oll_w_lg_w_lg_nl0i000Ol59482w59488w(0) AND wire_nlill0Oll_w_lg_nl0i000lO59485w(0)); + niOi1i1li <= (wire_nlill0Oll_w_lg_w_lg_nl0i000Ol59482w59488w(0) AND nl0i000lO); + niOi1i1ll <= (wire_nlill0Oll_w_lg_nl0i000Ol59491w(0) AND wire_nlill0Oll_w_lg_nl0i000lO59485w(0)); + niOi1i1lO <= (wire_nlill0Oll_w_lg_nl0i000Ol59491w(0) AND nl0i000lO); + niOi1i1Oi <= ((nl0i000Ol AND nl0i000Oi) AND wire_nlill0Oll_w_lg_nl0i000lO59485w(0)); + niOi1i1Ol <= (wire_nilOi11i_dataout AND nl10ilOOl); + niOi1i1OO <= (wire_nilOi11l_dataout AND nl10ilOOl); + niOi1ii0i <= ((((((((NOT wire_nl1i11liO_o(1)) AND (NOT wire_nl1i11liO_o(2))) AND (NOT wire_nl1i11liO_o(3))) AND (NOT wire_nl1i11liO_o(4))) AND (NOT wire_nl1i11liO_o(5))) AND (NOT wire_nl1i11liO_o(6))) AND (NOT wire_nl1i11liO_o(7))) AND (NOT wire_nl1i11liO_o(8))); + niOi1ii0l <= ((((((((NOT (nl1i11Oli XOR nl10O00li)) AND (NOT (nl1i11Oll XOR nl10O00ll))) AND (NOT (nl1i11OlO XOR nl10O00lO))) AND (NOT (nl1i11OOi XOR nl10O00Oi))) AND (NOT (nl1i11OOl XOR nl10O00Ol))) AND (NOT (nl1i11OOO XOR nl10O00OO))) AND (NOT (nl1i1011i XOR nl10O0i1i))) AND (NOT (nl1i1011l XOR nl10O0i1l))); + niOi1ii0O <= (wire_nl10lOOOi_w_lg_o58801w(0) OR (wire_nl10lOOiO_w_lg_o58802w(0) AND wire_w_lg_niOi1iiii58803w(0))); + niOi1ii1i <= (wire_nlill0Oll_w_lg_nl1i010iO58944w(0) OR (wire_nilOOO0i_w_lg_dataout47830w(0) OR wire_nilOO0ii_w_lg_dataout43403w(0))); + niOi1ii1l <= (wire_nl10lOO0l_w_lg_o58909w(0) OR (wire_nl10lOO1i_w_lg_o58910w(0) AND wire_w_lg_niOi1ii1O58911w(0))); + niOi1ii1O <= ((((((((((((NOT (nl1i10iOi XOR nl10O100l)) AND (NOT (nl1i1Oili XOR nl10O01Ol))) AND (NOT (nl1i1Oill XOR nl10O01OO))) AND (NOT (nl1i1OilO XOR nl10O001i))) AND (NOT (nl1i1OiOi XOR nl10O001l))) AND (NOT (nl1i1OiOl XOR nl10O001O))) AND (NOT (nl1i1OiOO XOR nl10O000i))) AND (NOT (nl1i1Ol1i XOR nl10O000l))) AND (NOT (nl1i1Ol1l XOR nl10O000O))) AND (NOT (nl1i1Ol1O XOR nl10O00ii))) AND (NOT (nl1i1Ol0i XOR nl10O00il))) AND (NOT (nl1i1Ol0l XOR nl10O00iO))); + niOi1iiii <= ((((((((((((NOT (nl1i1OlOl XOR nl10O0i1O)) AND (NOT (nl1i1OlOO XOR nl10O0i0i))) AND (NOT (nl1i1OO1i XOR nl10O0i0l))) AND (NOT (nl1i1OO1l XOR nl10O0i0O))) AND (NOT (nl1i1OO1O XOR nl10O0iii))) AND (NOT (nl1i1OO0i XOR nl10O0iil))) AND (NOT (nl1i1OO0l XOR nl10O0iiO))) AND (NOT (nl1i1OO0O XOR nl10O0ili))) AND (NOT (nl1i1OOii XOR nl10O0ill))) AND (NOT (nl1i1OOil XOR nl10O0ilO))) AND (NOT (nl1i1OOiO XOR nl10O0iOi))) AND (NOT (nl1i1OOli XOR nl10O0iOl))); + niOi1iiil <= ((((((((NOT wire_nl1i11lll_o(1)) AND (NOT wire_nl1i11lll_o(2))) AND (NOT wire_nl1i11lll_o(3))) AND (NOT wire_nl1i11lll_o(4))) AND (NOT wire_nl1i11lll_o(5))) AND (NOT wire_nl1i11lll_o(6))) AND (NOT wire_nl1i11lll_o(7))) AND (NOT wire_nl1i11lll_o(8))); + niOi1iiiO <= ((((((((NOT (nl1i101OO XOR nl10O0iOO)) AND (NOT (nl1i1001i XOR nl10O0l1i))) AND (NOT (nl1i1001l XOR nl10O0l1l))) AND (NOT (nl1i1001O XOR nl10O0l1O))) AND (NOT (nl1i1000i XOR nl10O0l0i))) AND (NOT (nl1i1000l XOR nl10O0l0l))) AND (NOT (nl1i1000O XOR nl10O0l0O))) AND (NOT (nl1i100ii XOR nl10O0lii))); + niOi1iili <= (wire_nl10O110l_w_lg_o58694w(0) OR wire_nl10O111i_w_lg_o58696w(0)); + niOi1iill <= ((((((((((((NOT (nl1i011lO XOR nl10O0O1i)) AND (NOT (nl1i011Oi XOR nl10O0O1l))) AND (NOT (nl1i011Ol XOR nl10O0O1O))) AND (NOT (nl1i011OO XOR nl10O0O0i))) AND (NOT (nl1i0101i XOR nl10O0O0l))) AND (NOT (nl1i0101l XOR nl10O0O0O))) AND (NOT (nl1i0101O XOR nl10O0Oii))) AND (NOT (nl1i0100i XOR nl10O0Oil))) AND (NOT (nl1i0100l XOR nl10O0OiO))) AND (NOT (nl1i0100O XOR nl10O0Oli))) AND (NOT (nl1i010ii XOR nl10O0Oll))) AND (NOT (nl1i010il XOR nl10O0OlO))); + niOi1iilO <= ((((((((NOT wire_nl1i11lOi_o(1)) AND (NOT wire_nl1i11lOi_o(2))) AND (NOT wire_nl1i11lOi_o(3))) AND (NOT wire_nl1i11lOi_o(4))) AND (NOT wire_nl1i11lOi_o(5))) AND (NOT wire_nl1i11lOi_o(6))) AND (NOT wire_nl1i11lOi_o(7))) AND (NOT wire_nl1i11lOi_o(8))); + niOi1iiOi <= ((((((((NOT (nl1i100il XOR nl10O0lil)) AND (NOT (nl1i100iO XOR nl10O0liO))) AND (NOT (nl1i100li XOR nl10O0lli))) AND (NOT (nl1i100ll XOR nl10O0lll))) AND (NOT (nl1i100lO XOR nl10O0llO))) AND (NOT (nl1i100Oi XOR nl10O0lOi))) AND (NOT (nl1i100Ol XOR nl10O0lOl))) AND (NOT (nl1i100OO XOR nl10O0lOO))); + niOi1iiOl <= (wire_nl011l0il_dataout AND wire_nl10lli1O_dataout); + niOi1iiOO <= (wire_nl011l0il_dataout AND wire_nl10lli0i_dataout); + niOi1il0i <= ((((((((NOT wire_nl1i11liO_o(1)) AND (NOT wire_nl1i11liO_o(2))) AND (NOT wire_nl1i11liO_o(3))) AND (NOT wire_nl1i11liO_o(4))) AND (NOT wire_nl1i11liO_o(5))) AND (NOT wire_nl1i11liO_o(6))) AND (NOT wire_nl1i11liO_o(7))) AND (NOT wire_nl1i11liO_o(8))); + niOi1il0l <= (wire_nl011OilO_dataout AND wire_w_lg_niOi1illO57815w(0)); + niOi1il0O <= (wire_nl011OilO_dataout AND niOi1ilii); + niOi1il1i <= (wire_nl011l0il_dataout AND wire_nl10lli0l_dataout); + niOi1il1l <= ((((((((NOT wire_nl1i11lOi_o(1)) AND (NOT wire_nl1i11lOi_o(2))) AND (NOT wire_nl1i11lOi_o(3))) AND (NOT wire_nl1i11lOi_o(4))) AND (NOT wire_nl1i11lOi_o(5))) AND (NOT wire_nl1i11lOi_o(6))) AND (NOT wire_nl1i11lOi_o(7))) AND (NOT wire_nl1i11lOi_o(8))); + niOi1il1O <= ((((((((NOT wire_nl1i11lll_o(1)) AND (NOT wire_nl1i11lll_o(2))) AND (NOT wire_nl1i11lll_o(3))) AND (NOT wire_nl1i11lll_o(4))) AND (NOT wire_nl1i11lll_o(5))) AND (NOT wire_nl1i11lll_o(6))) AND (NOT wire_nl1i11lll_o(7))) AND (NOT wire_nl1i11lll_o(8))); + niOi1ilii <= (nl0100lOi AND wire_nlill0Oll_w_lg_nl0100llO59067w(0)); + niOi1ilil <= (wire_nl011OilO_dataout AND niOi1iliO); + niOi1iliO <= (wire_nlill0Oll_w_lg_nl0100lOi56535w(0) AND nl0100llO); + niOi1illi <= (wire_nlill0Oll_w_lg_nl0100lOi56535w(0) AND wire_nlill0Oll_w_lg_nl0100llO59067w(0)); + niOi1illl <= (wire_nl011OilO_dataout AND niOi1illi); + niOi1illO <= ((((((((((((((((((((NOT k_vc0(36)) AND (NOT k_vc0(37))) AND (NOT k_vc0(38))) AND (NOT k_vc0(39))) AND (NOT k_vc0(40))) AND (NOT k_vc0(41))) AND (NOT k_vc0(42))) AND (NOT k_vc0(43))) AND (NOT k_vc0(44))) AND (NOT k_vc0(45))) AND (NOT k_vc0(46))) AND (NOT k_vc0(47))) AND (NOT k_vc0(48))) AND (NOT k_vc0(49))) AND (NOT k_vc0(50))) AND (NOT k_vc0(51))) AND (NOT k_vc0(52))) AND (NOT k_vc0(53))) AND (NOT k_vc0(54))) AND (NOT k_vc0(55))); + niOi1ilOi <= (niOi1l0Oi AND (nl1iiO0lO AND wire_nlill0Oll_w_lg_nl1iiO0ll57606w(0))); + niOi1ilOl <= ((((((((NOT k_vc0(28)) AND (NOT k_vc0(29))) AND (NOT k_vc0(30))) AND (NOT k_vc0(31))) AND (NOT k_vc0(32))) AND (NOT k_vc0(33))) AND (NOT k_vc0(34))) AND (NOT k_vc0(35))); + niOi1ilOO <= (nl1iiO0Oi AND niOi1iO1i); + niOi1iO0i <= ((niOi1iOli OR niOi1iO0l) OR niOi1iOOi); + niOi1iO0l <= ((wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59038w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND niOOi1ilO); + niOi1iO0O <= ((niOi1iOOl OR niOi1iOii) OR niOi1iOiO); + niOi1iO1i <= (niOi1l0Oi AND (wire_nlill0Oll_w_lg_nl1iiO0lO57605w(0) AND nl1iiO0ll)); + niOi1iO1l <= (wire_nilOOO0i_w_lg_dataout47830w(0) AND wire_nilOO00O_w_lg_dataout47986w(0)); + niOi1iO1O <= (niOi1l0Oi AND (wire_nlill0Oll_w_lg_nl1iiO0lO57605w(0) AND wire_nlill0Oll_w_lg_nl1iiO0ll57606w(0))); + niOi1iOii <= ((wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59023w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1iOil <= ((niOi1iOll OR niOi1iOli) OR niOi1iOiO); + niOi1iOiO <= ((((niOOi1l1i AND niOOi1iOO) AND wire_nl1000i_w_lg_niOOi1iOl59017w(0)) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1iOli <= (wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59038w59039w(0) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1iOll <= ((wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59038w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1iOlO <= ((niOi1iOOO OR niOi1iOOl) OR niOi1iOOi); + niOi1iOOi <= (wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59031w59050w(0) AND niOOi1ilO); + niOi1iOOl <= ((wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59023w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND niOOi1ilO); + niOi1iOOO <= (wire_nl1000i_w59044w(0) AND niOOi1ilO); + niOi1l00i <= ((wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59035w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l00l <= (wire_nl1000i_w59024w(0) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l00O <= ((niOi1l0iO OR niOi1l0il) OR niOi1l0ii); + niOi1l01i <= (wire_nl1000i_w59027w(0) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l01l <= ((niOi1l00l OR niOi1l00i) OR niOi1l01O); + niOi1l01O <= ((wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59031w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l0ii <= (wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59038w59039w(0) AND niOOi1ilO); + niOi1l0il <= (wire_nl1000i_w59027w(0) AND niOOi1ilO); + niOi1l0iO <= ((wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59018w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND niOOi1ilO); + niOi1l0li <= wire_nlOiilO1l_w_lg_w_lg_w_lg_w_lg_dataout9857w9858w9868w9869w(0); + niOi1l0ll <= (wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9859w(0) AND wire_nlOiillOl_w_lg_dataout9855w(0)); + niOi1l0lO <= ((wire_nlOiilO1l_w_lg_w_lg_dataout9857w9862w(0) AND wire_nlOiillOO_w_lg_dataout9853w(0)) AND wire_nlOiillOl_w_lg_dataout9855w(0)); + niOi1l0Oi <= (((wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout52008w56221w56222w(0) AND (wire_w_lg_niOi01i0l54724w(0) OR wire_w_lg_niOi01i0l55508w(0))) OR wire_nlill0Oll_w_lg_w_lg_w_lg_nl1iiO0li56217w56224w56225w(0)) OR wire_w_lg_niOO10lOl56228w(0)); + niOi1l0Ol <= ((wire_nlill0Oll_w_lg_w56923w56925w(0) AND wire_nlill0Oll_w_lg_nl1ll0l1l56929w(0)) AND wire_nlill0Oll_w_lg_nl1ll0l1i56927w(0)); + niOi1l0OO <= ((wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w5086w(0) AND wire_nl1lOOlOO_w_lg_dataout52012w(0)) AND wire_nl1lOOlOl_w_lg_dataout52282w(0)); + niOi1l10i <= ((wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59041w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND niOOi1ilO); + niOi1l10l <= ((niOi1l1il OR niOi1l1ii) OR niOi1l10O); + niOi1l10O <= (wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59031w59050w(0) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l11i <= ((niOi1l1ii OR niOi1l11l) OR niOi1l1li); + niOi1l11l <= (wire_nl1000i_w59048w(0) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l11O <= ((niOi1l1ll OR niOi1l10i) OR niOi1l10O); + niOi1l1ii <= (wire_nl1000i_w59048w(0) AND niOOi1ilO); + niOi1l1il <= ((wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59035w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND niOOi1ilO); + niOi1l1iO <= ((niOi1l1lO OR niOi1l1ll) OR niOi1l1li); + niOi1l1li <= ((wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59031w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND niOOi1ilO); + niOi1l1ll <= (wire_nl1000i_w59044w(0) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l1lO <= ((wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59041w(0) AND wire_nl1000i_w_lg_niOOi1iOi59019w(0)) AND wire_nl1000i_w_lg_niOOi1ilO59025w(0)); + niOi1l1Oi <= ((niOi1l1Ol OR niOi1l00i) OR niOi1l0ii); + niOi1l1Ol <= (wire_nl1000i_w59024w(0) AND niOOi1ilO); + niOi1l1OO <= ((niOi1l01i OR niOi1l0il) OR niOi1l01O); + niOi1li0i <= (wire_nlill0Oll_w_lg_nl1ll0lOi56098w(0) AND wire_nlill0Oll_w_lg_w_lg_nl1OilOii54862w54863w(0)); + niOi1li0l <= (niOi1liii AND nl1iiOiii); + niOi1li0O <= (niOi1liii AND wire_nlill0Oll_w_lg_nl1iiOiii56091w(0)); + niOi1li1i <= (wire_nl1lOOO0i_w_lg_dataout5075w(0) AND wire_nl1lOOO1O_w_lg_w_lg_w_lg_w_lg_dataout5082w56204w56205w56206w(0)); + niOi1li1l <= (wire_nl1lOOi0O_w_lg_dataout52548w(0) AND wire_nl1lOOi0l_w_lg_dataout52550w(0)); + niOi1li1O <= (wire_nl1il001O_o AND wire_nlill0Oll_w_lg_nl1il1i1O56135w(0)); + niOi1liii <= ((nl1ll0iOi AND niOi1lOil) AND wire_nlill0Oll_w_lg_nl1il1i1l56094w(0)); + niOi1liil <= (wire_nl1lOOlOi_dataout XOR wire_nl1lOOi0l_dataout); + niOi1liiO <= (wire_nl1lOOlOi_dataout AND niOi1O11l); + niOi1lili <= (wire_nl1lOOiOl_w_lg_w52547w56985w(0) AND wire_nl1lOOi0l_w_lg_dataout52550w(0)); + niOi1lill <= ((wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout54760w56981w56982w(0) AND wire_nl1lOOO1i_w_lg_dataout5085w(0)) AND wire_nl1lOOlOO_dataout); + niOi1lilO <= (((((((((((wire_nl1lOO1Ol_w_lg_dataout56965w(0) AND wire_nl1lOO1Oi_w_lg_dataout56966w(0)) AND wire_nl1lOO1lO_w_lg_dataout56968w(0)) AND wire_nl1lOO1ll_w_lg_dataout56970w(0)) AND wire_nl1lOO1li_w_lg_dataout52289w(0)) AND wire_nl1lOO1iO_w_lg_dataout52298w(0)) AND wire_nl1lOO1il_w_lg_dataout52291w(0)) AND wire_nl1lOO1ii_w_lg_dataout52322w(0)) AND wire_nl1lOO10O_w_lg_dataout52141w(0)) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_w_lg_dataout52144w(0)); + niOi1liOi <= (wire_nl1lOOl1i_w_lg_dataout56962w(0) AND wire_nl1lOOiOO_w_lg_dataout56960w(0)); + niOi1liOl <= (wire_nl1lOOl1i_w_lg_dataout56962w(0) AND wire_nl1lOOiOO_dataout); + niOi1liOO <= (wire_nl1lOOl1i_dataout AND wire_nl1lOOiOO_w_lg_dataout56960w(0)); + niOi1ll0i <= (nl1ll0ili AND niOi1ll0l); + niOi1ll0l <= (nl1ll0iOi AND niOi1llOi); + niOi1ll0O <= (nl1ll0ili AND niOi1llil); + niOi1ll1i <= wire_nl1iliill_w_lg_w_o_range56060w56980w(0); + niOi1ll1l <= (wire_nl1ili00O_o OR (wire_nl1iliill_w_lg_w_o_range56060w56061w(0) AND wire_nl1iliill_w_lg_w_o_range56062w56063w(0))); + niOi1ll1O <= (wire_nlill0Oll_w_lg_nl1ll0ili55858w(0) AND niOi1ll0l); + niOi1llii <= (nl1ll0ill OR (wire_nlill0Oll_w_lg_nl1ll0ili55858w(0) AND niOi1llil)); + niOi1llil <= (niOi1OiiO AND (wire_nlill0Oll_w_lg_nl1ll0llO55838w(0) AND nl1ll0iOi)); + niOi1lliO <= (wire_nlill0Oll_w_lg_nl1OilllO54891w(0) AND nl1ll0iOl); + niOi1llli <= (nl1OlO11l AND nl1ll0iOl); + niOi1llll <= (nl1OilllO AND nl1ll0iOl); + niOi1lllO <= (niOi1OiiO AND (nl1Ol1l0l AND wire_nlill0Oll_w_lg_nl1ll0llO55838w(0))); + niOi1llOi <= (nl1ll0llO AND wire_nllillil_w_lg_dataout55059w(0)); + niOi1llOl <= (wire_nl1lOOl0l_dataout AND nl1ll0iOl); + niOi1llOO <= (wire_nl1lOOi0l_w_lg_dataout52550w(0) AND niOi1lO1i); + niOi1lO0i <= (nl1ll0ilO OR nl1ll0ill); + niOi1lO0l <= (((nl1ll0llO AND wire_nllillil_dataout) OR (nl1Ol1l0l AND nl1ll0llO)) OR (nl1Ol1l0l AND niOi1lOiO)); + niOi1lO0O <= (nl1OillOO AND niOi1O10l); + niOi1lO1i <= (wire_nl1lOOO0i_dataout AND wire_nl1lOOlOi_dataout); + niOi1lO1l <= (wire_nl1lOOi0l_dataout AND niOi1lO1O); + niOi1lO1O <= (wire_nl1lOOO0i_w_lg_dataout5075w(0) AND wire_nl1lOOlOi_w_lg_dataout55789w(0)); + niOi1lOii <= (wire_nl1Ol1ili_dataout AND niOi1O1il); + niOi1lOil <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl1ll0iiO55841w55843w55844w(0) AND (wire_nlill0Oll_w_lg_nl1ll0lOi55058w(0) OR wire_nlill0Oll_w_lg_nl1ll0lOi55845w(0))) OR nl1l0lOli); + niOi1lOiO <= (nl1ll0lOi AND wire_nllillil_dataout); + niOi1lOli <= (niOi1Ol0l AND wire_nl1il001O_o); + niOi1lOll <= ((niOi01i0l AND niOi1O11O) AND wire_w_lg_niOi1O11i55413w(0)); + niOi1lOlO <= (nl1OlO11l OR (wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55507w(0) AND (wire_w_lg_niOi01i0l54724w(0) OR wire_w_lg_niOi01i0l55508w(0)))); + niOi1lOOi <= (nl1OilO0O AND (wire_nl1lOOO0l_dataout AND wire_nl1lOOO0i_dataout)); + niOi1lOOl <= (niOi01i0l AND wire_nl1lOOO0l_w_lg_dataout52008w(0)); + niOi1lOOO <= ((nl1OlO11l OR wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0)) OR wire_nl1llO1li_o); + niOi1O00i <= (wire_nlill0Oll_w_lg_nl1O1ii1l56938w(0) AND wire_nlill0Oll_w_lg_nl1O1ii1i56939w(0)); + niOi1O00l <= (wire_nlill0Oll_w_lg_nl1O1ii1l56938w(0) AND nl1O1ii1i); + niOi1O00O <= (nl1O1ii1l AND wire_nlill0Oll_w_lg_nl1O1ii1i56939w(0)); + niOi1O01i <= ((wire_nl1lO0i0i_w_lg_w_lg_dataout55287w55288w(0) AND wire_nl1lO0i1l_w_lg_dataout56946w(0)) AND wire_nl1lO0i1i_w_lg_dataout56948w(0)); + niOi1O01l <= ((wire_nl1lO0i0i_w_lg_w_lg_dataout55287w55288w(0) AND wire_nl1lO0i1l_w_lg_dataout56946w(0)) AND wire_nl1lO0i1i_dataout); + niOi1O01O <= (wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w55288w55289w(0) AND wire_nl1lO0i1i_w_lg_dataout56948w(0)); + niOi1O0ii <= (wire_nlill0Oll_w_lg_nl1O1i0OO56932w(0) AND wire_nlill0Oll_w_lg_nl1lO1ilO56933w(0)); + niOi1O0il <= (wire_nlill0Oll_w_lg_nl1O1i0OO56932w(0) AND nl1lO1ilO); + niOi1O0iO <= (nl1O1i0OO AND wire_nlill0Oll_w_lg_nl1lO1ilO56933w(0)); + niOi1O0li <= (wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND wire_nlill0Oll_w_lg_nl1OilO1i55216w(0)); + niOi1O0ll <= (nl1Ol011O AND nl1OilO1l); + niOi1O0lO <= (nl1OilO0i AND wire_nlill0Oll_w_lg_nl1OilllO54891w(0)); + niOi1O0Oi <= (nl1Ol1l0l AND (nl1OilO1l OR nl1OillOl)); + niOi1O0Ol <= (nl1O1ii1l AND nl1O1ii1i); + niOi1O0OO <= (nl1O1i0OO AND nl1lO1ilO); + niOi1O10i <= ((nl1OilllO AND (niOi1OliO AND (wire_w_lg_niOi1OlOi55403w(0) AND wire_w_lg_niOi1OllO54888w(0)))) AND niOi1O10l); + niOi1O10l <= (wire_nl1lOOO0l_dataout OR niOi1O1li); + niOi1O10O <= (niOi1O1il AND (((wire_nl1Ol1ili_dataout AND niOi1O1ii) OR wire_nlill0Oll_w_lg_w_lg_nl1Ol1l0l55394w55395w(0)) OR wire_nl1Ol1ill_w_lg_dataout55398w(0))); + niOi1O11i <= (wire_nl1lOOO0l_w_lg_w_lg_dataout52008w54761w(0) AND wire_nl1lOOO1O_dataout); + niOi1O11l <= wire_nl1lOOiOl_w_lg_w_lg_w52547w52549w52552w(0); + niOi1O11O <= (niOi1OO1i AND wire_nl1lOOl0l_dataout); + niOi1O1ii <= (nl1Ol1l0l OR nl1O0iiii); + niOi1O1il <= (nl1OilO1l AND niOi1Ol0l); + niOi1O1iO <= (wire_nl1lOOO0i_dataout AND niOi1O1li); + niOi1O1li <= (niOi01i0l AND wire_nl1lOOl0l_dataout); + niOi1O1ll <= (wire_nl1lOOiOl_w_lg_w52547w52549w(0) AND wire_nl1lOOi0l_w_lg_dataout52550w(0)); + niOi1O1lO <= (wire_nl1lOOO0i_w_lg_dataout5075w(0) AND (wire_w_lg_niOi01i0l54724w(0) OR wire_nl1lOOl0l_w_lg_dataout54725w(0))); + niOi1O1Oi <= ((wire_nl1lO0i0i_w_lg_w_lg_dataout55287w56945w(0) AND wire_nl1lO0i1l_w_lg_dataout56946w(0)) AND wire_nl1lO0i1i_dataout); + niOi1O1Ol <= (wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w56945w56951w(0) AND wire_nl1lO0i1i_w_lg_dataout56948w(0)); + niOi1O1OO <= (wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w56945w56951w(0) AND wire_nl1lO0i1i_dataout); + niOi1Oi0i <= (niOO10lOl AND nl1OilO0O); + niOi1Oi0l <= (nl1OilOii AND nlliO1Oi); + niOi1Oi0O <= (niOi1OiiO AND wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0)); + niOi1Oi1i <= ((nlill0lll OR nl1OilO1i) OR (NOT (wire_nlill0Oll_w_lg_nl1OllOOl54881w(0) AND wire_nlill0Oll_w_lg_nl1Ol011O54883w(0)))); + niOi1Oi1l <= (nl1OilO1i OR nl1OillOl); + niOi1Oi1O <= (nl1OilliO OR niOi1Oiil); + niOi1Oiii <= (niOi1OllO OR niOi1OiOl); + niOi1Oiil <= (wire_nlill0Oll_w_lg_nl1Oillll55053w(0) AND wire_nlill0Oll_w_lg_nl1Oillli55050w(0)); + niOi1OiiO <= (wire_nlill0Oll_w_lg_nl1ll0lOi55058w(0) OR wire_nllillil_w_lg_dataout55059w(0)); + niOi1Oili <= (((((((((NOT (k_ptr0(27) XOR nl1Ol1lOO)) AND (NOT (k_ptr0(28) XOR nl1Ol1O1i))) AND (NOT (k_ptr0(29) XOR nl1Ol1O1l))) AND (NOT (k_ptr0(30) XOR nl1Ol1O1O))) AND (NOT (k_ptr0(31) XOR nl1Ol1O0i))) AND (NOT (k_ptr0(32) XOR nl1Ol1O0l))) AND (NOT (k_ptr0(33) XOR nl1Ol1O0O))) AND (NOT (k_ptr0(34) XOR nl1Ol1Oii))) AND (NOT (k_ptr0(35) XOR nl1Ol1Oil))); + niOi1Oill <= (((((((((NOT (k_ptr0(9) XOR nl1Ol1lOO)) AND (NOT (k_ptr0(10) XOR nl1Ol1O1i))) AND (NOT (k_ptr0(11) XOR nl1Ol1O1l))) AND (NOT (k_ptr0(12) XOR nl1Ol1O1O))) AND (NOT (k_ptr0(13) XOR nl1Ol1O0i))) AND (NOT (k_ptr0(14) XOR nl1Ol1O0l))) AND (NOT (k_ptr0(15) XOR nl1Ol1O0O))) AND (NOT (k_ptr0(16) XOR nl1Ol1Oii))) AND (NOT (k_ptr0(17) XOR nl1Ol1Oil))); + niOi1OilO <= (wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND niOi1Ol0l); + niOi1OiOi <= (niOi1OlOi AND nl1OilllO); + niOi1OiOl <= (niOi1OlOi AND wire_nlill0Oll_w_lg_nl1OilllO54891w(0)); + niOi1OiOO <= (wire_w_lg_niOi1Ol1O54885w(0) AND wire_w_lg_niOi1Ol1i54886w(0)); + niOi1Ol0i <= ((wire_nlill0Oll_w_lg_w56923w56925w(0) AND wire_nlill0Oll_w_lg_nl1ll0l1l56929w(0)) AND wire_nlill0Oll_w_lg_nl1ll0l1i56927w(0)); + niOi1Ol0l <= (nl1ll0ill OR (nl1ll0iOl OR (nl1OilO1l OR ((wire_w_lg_niOi1lO0l55827w(0) AND wire_w_lg_niOi1Ol0i55828w(0)) OR wire_nlill0Oll_w_lg_nl1OilO1O55832w(0))))); + niOi1Ol0O <= ((wire_nlill0Oll_w_lg_w56923w56925w(0) AND wire_nlill0Oll_w_lg_nl1ll0l1l56929w(0)) AND nl1ll0l1i); + niOi1Ol1i <= ((wire_w_lg_niOi1OlOi56853w(0) AND wire_nl1OlOi1l_w_lg_dataout55402w(0)) AND wire_w_lg_niOi1OllO54888w(0)); + niOi1Ol1l <= (niOi1Ol1O AND wire_w_lg_niOi1Ol1i54886w(0)); + niOi1Ol1O <= (niOi1OliO AND (niOi1Olil OR ((NOT k_gbl_hip(44)) AND (wire_w54874w(0) AND wire_nl1Ol1ill_w_lg_dataout54875w(0))))); + niOi1Olii <= (wire_nlill0Oll_w_lg_w_lg_w56923w56925w56926w(0) AND wire_nlill0Oll_w_lg_nl1ll0l1i56927w(0)); + niOi1Olil <= (nl1ll0iOO OR nl1ll0ilO); + niOi1OliO <= ((niOi1Olll AND nl1OilO0i) AND niOi1Olli); + niOi1Olli <= (niOO10lOl OR wire_nlill0Oll_w_lg_nl1OilO0O54864w(0)); + niOi1Olll <= wire_nlill0Oll_w_lg_w_lg_nl1OilOii54862w54863w(0); + niOi1OllO <= ((wire_w_lg_w_k_gbl_hip_range54181w54855w(0) AND wire_nl1000i_w_lg_nli1100i54856w(0)) AND (wire_w_lg_niOi1OOOl54858w(0) OR wire_w_lg_niOi1OOOi54859w(0))); + niOi1OlOi <= (niOi0110i AND (NOT (wire_w_lg_w_lg_niOi011ii54835w54836w(0) OR wire_w_lg_niOi0110l54839w(0)))); + niOi1OlOl <= ((niOi01i0l AND (niOi1OOOl AND wire_nl1lOOl0l_dataout)) AND niOi1OOli); + niOi1OlOO <= ((wire_w_lg_niOi01i0l54724w(0) OR wire_w_lg_niOi01i0l54727w(0)) AND niOi1OOOl); + niOi1OO0i <= (((((((((NOT (k_ptr0(27) XOR nl1OO1Oli)) AND (NOT (k_ptr0(28) XOR nl1OO1Oll))) AND (NOT (k_ptr0(29) XOR nl1OO1OlO))) AND (NOT (k_ptr0(30) XOR nl1OO1OOi))) AND (NOT (k_ptr0(31) XOR nl1OO1OOl))) AND (NOT (k_ptr0(32) XOR nl1OO1OOO))) AND (NOT (k_ptr0(33) XOR nl1OO011i))) AND (NOT (k_ptr0(34) XOR nl1OO011l))) AND (NOT (k_ptr0(35) XOR nl1OO011O))); + niOi1OO0l <= (((niOi01i0l AND (niOi1OOOl AND niOi1OO0O)) AND niOi1OOli) AND wire_nl1lOOl0l_dataout); + niOi1OO0O <= ((((((((((NOT wire_nl1OO1ili_o(8)) AND (NOT (k_ptr0(27) XOR nl1OO1Oli))) AND (NOT (k_ptr0(28) XOR wire_nl1OO1ili_o(0)))) AND (NOT (k_ptr0(29) XOR wire_nl1OO1ili_o(1)))) AND (NOT (k_ptr0(30) XOR wire_nl1OO1ili_o(2)))) AND (NOT (k_ptr0(31) XOR wire_nl1OO1ili_o(3)))) AND (NOT (k_ptr0(32) XOR wire_nl1OO1ili_o(4)))) AND (NOT (k_ptr0(33) XOR wire_nl1OO1ili_o(5)))) AND (NOT (k_ptr0(34) XOR wire_nl1OO1ili_o(6)))) AND (NOT (k_ptr0(35) XOR wire_nl1OO1ili_o(7)))); + niOi1OO1i <= (wire_nl1lOOO0l_w_lg_dataout52008w(0) AND wire_nl1lOOO0i_w_lg_dataout5075w(0)); + niOi1OO1l <= (niOi1OOOl AND niOi1OO1O); + niOi1OO1O <= ((((((((NOT (k_ptr0(28) XOR nl1OO1Oll)) AND (NOT (k_ptr0(29) XOR nl1OO1OlO))) AND (NOT (k_ptr0(30) XOR nl1OO1OOi))) AND (NOT (k_ptr0(31) XOR nl1OO1OOl))) AND (NOT (k_ptr0(32) XOR nl1OO1OOO))) AND (NOT (k_ptr0(33) XOR nl1OO011i))) AND (NOT (k_ptr0(34) XOR nl1OO011l))) AND (NOT (k_ptr0(35) XOR nl1OO011O))); + niOi1OOii <= ((niOi1OOil AND niOi1OOli) AND wire_nl1lOOl0l_dataout); + niOi1OOil <= (niOi01i0l AND (niOi1OOOl AND niOi1OO0i)); + niOi1OOiO <= (((niOi01i0l AND (niOi1OOOl AND niOi1OOll)) AND niOi1OOli) AND wire_nl1lOOl0l_dataout); + niOi1OOli <= (wire_nl1lOOO0l_w_lg_dataout54760w(0) OR wire_nl1lOOO0l_w_lg_w_lg_dataout52008w54761w(0)); + niOi1OOll <= ((((((((((NOT wire_nl1OO1lOl_o(9)) AND (NOT (k_ptr0(27) XOR wire_nl1OO1lOl_o(0)))) AND (NOT (k_ptr0(28) XOR wire_nl1OO1lOl_o(1)))) AND (NOT (k_ptr0(29) XOR wire_nl1OO1lOl_o(2)))) AND (NOT (k_ptr0(30) XOR wire_nl1OO1lOl_o(3)))) AND (NOT (k_ptr0(31) XOR wire_nl1OO1lOl_o(4)))) AND (NOT (k_ptr0(32) XOR wire_nl1OO1lOl_o(5)))) AND (NOT (k_ptr0(33) XOR wire_nl1OO1lOl_o(6)))) AND (NOT (k_ptr0(34) XOR wire_nl1OO1lOl_o(7)))) AND (NOT (k_ptr0(35) XOR wire_nl1OO1lOl_o(8)))); + niOi1OOlO <= (niOi0111O AND wire_nlill0Oll_w_lg_nl1OO010i8963w(0)); + niOi1OOOi <= (((((((((NOT (nl1OO1Oli XOR nl1OlO11O)) AND (NOT (nl1OO1Oll XOR nl1OO1O1l))) AND (NOT (nl1OO1OlO XOR nl1OO1O1O))) AND (NOT (nl1OO1OOi XOR nl1OO1O0i))) AND (NOT (nl1OO1OOl XOR nl1OO1O0l))) AND (NOT (nl1OO1OOO XOR nl1OO1O0O))) AND (NOT (nl1OO011i XOR nl1OO1Oii))) AND (NOT (nl1OO011l XOR nl1OO1Oil))) AND (NOT (nl1OO011O XOR nl1OO1OiO))); + niOi1OOOl <= (nl1OlO11i AND nlliO1Oi); + niOi1OOOO <= (nl1OO010i OR nli1100i); + niOii000i <= ((((((((NOT (niOil0O1l XOR (k_bar(4) AND wire_nl01l1lii_o(3)))) AND (NOT (niOil0O1O XOR (k_bar(5) AND wire_nl01l1lii_o(4))))) AND (NOT (niOil0O0i XOR (k_bar(6) AND wire_nl01l1lii_o(5))))) AND (NOT (niOil0O0l XOR (k_bar(7) AND wire_nl01l1lii_o(6))))) AND (NOT (niOil0O0O XOR (k_bar(8) AND wire_nl01l1lii_o(7))))) AND (NOT (niOil0Oii XOR (k_bar(9) AND wire_nl01l1lii_o(8))))) AND (NOT (niOil0Oil XOR (k_bar(10) AND wire_nl01l1lii_o(9))))) AND (NOT (niOil0OiO XOR (k_bar(11) AND wire_nl01l1lii_o(10))))); + niOii000l <= ((((((((((((((((((((((((((((NOT (niOil0i0i XOR niOii0lii)) AND (NOT (niOil0i0l XOR niOii0l0O))) AND (NOT (niOil0i0O XOR niOii0l0l))) AND (NOT (niOil0iii XOR niOii0l0i))) AND (NOT (niOil0iil XOR niOii0l1O))) AND (NOT (niOil0iiO XOR niOii0l1l))) AND (NOT (niOil0ili XOR niOii0l1i))) AND (NOT (niOil0ill XOR niOii0iOO))) AND (NOT (niOil0ilO XOR niOii0iOl))) AND (NOT (niOil0iOi XOR niOii0iOi))) AND (NOT (niOil0iOl XOR niOii0ilO))) AND (NOT (niOil0iOO XOR niOii0ill))) AND (NOT (niOil0l1i XOR niOii0ili))) AND (NOT (niOil0l1l XOR niOii0iiO))) AND (NOT (niOil0l1O XOR niOii0iil))) AND (NOT (niOil0l0i XOR niOii0iii))) AND (NOT (niOil0l0l XOR niOii0i0O))) AND (NOT (niOil0l0O XOR niOii0i0l))) AND (NOT (niOil0lii XOR niOii0i0i))) AND wire_w_lg_w_lg_niOil0lil51645w51646w(0)) AND (NOT (niOil0liO XOR niOii0i1l))) AND (NOT (niOil0lli XOR niOii0i1i))) AND (NOT (niOil0lll XOR niOii00OO))) AND (NOT (niOil0llO XOR niOii00Ol))) AND (NOT (niOil0lOi XOR niOii00Oi))) AND (NOT (niOil0lOl XOR niOii00lO))) AND (NOT (niOil0lOO XOR niOii00ll))) AND (NOT (niOil0O1i XOR niOii00li))); + niOii000O <= (nl01l0lOl AND wire_nli0O1OOl_dataout); + niOii001i <= (nl0iOil1i AND (nl0iOiO0l AND niOili01O)); + niOii001l <= (nl0iOil1i AND (nl0iOilil AND niOili01O)); + niOii001O <= ((((((((NOT (niOil0i0i XOR (k_bar(36) AND wire_nl01l1lii_o(3)))) AND (NOT (niOil0i0l XOR (k_bar(37) AND wire_nl01l1lii_o(4))))) AND (NOT (niOil0i0O XOR (k_bar(38) AND wire_nl01l1lii_o(5))))) AND (NOT (niOil0iii XOR (k_bar(39) AND wire_nl01l1lii_o(6))))) AND (NOT (niOil0iil XOR (k_bar(40) AND wire_nl01l1lii_o(7))))) AND (NOT (niOil0iiO XOR (k_bar(41) AND wire_nl01l1lii_o(8))))) AND (NOT (niOil0ili XOR (k_bar(42) AND wire_nl01l1lii_o(9))))) AND (NOT (niOil0ill XOR (k_bar(43) AND wire_nl01l1lii_o(10))))); + niOii00ii <= wire_nlill0Oll_w_lg_nl01l0O1l47777w(0); + niOii00il <= ((((((((((((((((((((((((((((NOT (niOil0O1l XOR (k_bar(4) AND wire_nilOiO1O_dataout))) AND (NOT (niOil0O1O XOR (k_bar(5) AND wire_nilOiO0i_dataout)))) AND (NOT (niOil0O0i XOR (k_bar(6) AND wire_nilOiO0l_dataout)))) AND (NOT (niOil0O0l XOR (k_bar(7) AND wire_nilOiO0O_dataout)))) AND (NOT (niOil0O0O XOR (k_bar(8) AND wire_nilOiOii_dataout)))) AND (NOT (niOil0Oii XOR (k_bar(9) AND wire_nilOiOil_dataout)))) AND (NOT (niOil0Oil XOR (k_bar(10) AND wire_nilOiOiO_dataout)))) AND (NOT (niOil0OiO XOR (k_bar(11) AND wire_nilOiOli_dataout)))) AND (NOT (niOil0Oli XOR (k_bar(12) AND wire_nilOiOll_dataout)))) AND (NOT (niOil0Oll XOR (k_bar(13) AND wire_nilOiOlO_dataout)))) AND (NOT (niOil0OlO XOR (k_bar(14) AND wire_nilOiOOi_dataout)))) AND (NOT (niOil0OOi XOR (k_bar(15) AND wire_nilOiOOl_dataout)))) AND (NOT (niOil0OOl XOR (k_bar(16) AND wire_nilOiOOO_dataout)))) AND (NOT (niOil0OOO XOR (k_bar(17) AND wire_nilOl11i_dataout)))) AND (NOT (niOili11i XOR (k_bar(18) AND wire_nilOl11l_dataout)))) AND (NOT (niOili11l XOR (k_bar(19) AND wire_nilOl11O_dataout)))) AND (NOT (niOili11O XOR (k_bar(20) AND wire_nilOl10i_dataout)))) AND (NOT (niOili10i XOR (k_bar(21) AND wire_nilOl10l_dataout)))) AND (NOT (niOili10l XOR (k_bar(22) AND wire_nilOl10O_dataout)))) AND (NOT (niOili10O XOR (k_bar(23) AND wire_nilOl1ii_dataout)))) AND (NOT (niOili1ii XOR (k_bar(24) AND wire_nilOl1il_dataout)))) AND (NOT (niOili1il XOR (k_bar(25) AND wire_nilOl1iO_dataout)))) AND (NOT (niOili1iO XOR (k_bar(26) AND wire_nilOl1li_dataout)))) AND (NOT (niOili1li XOR (k_bar(27) AND wire_nilOl1ll_dataout)))) AND (NOT (niOili1ll XOR (k_bar(28) AND wire_nilOl1lO_dataout)))) AND (NOT (niOili1lO XOR (k_bar(29) AND wire_nilOl1Oi_dataout)))) AND (NOT (niOili1Oi XOR (k_bar(30) AND wire_nilOl1Ol_dataout)))) AND (NOT (niOili1Ol XOR (k_bar(31) AND wire_nilOl1OO_dataout)))); + niOii00iO <= ((((((((wire_w_lg_w_nl0liO1Oi51818w51819w(0) AND (NOT (niOil0liO XOR niOii0i1l))) AND (NOT (niOil0lli XOR niOii0i1i))) AND (NOT (niOil0lll XOR niOii00OO))) AND (NOT (niOil0llO XOR niOii00Ol))) AND (NOT (niOil0lOi XOR niOii00Oi))) AND (NOT (niOil0lOl XOR niOii00lO))) AND (NOT (niOil0lOO XOR niOii00ll))) AND (NOT (niOil0O1i XOR niOii00li))); + niOii00li <= (k_bar(63) AND wire_nilOl1OO_dataout); + niOii00ll <= (k_bar(62) AND wire_nilOl1Ol_dataout); + niOii00lO <= (k_bar(61) AND wire_nilOl1Oi_dataout); + niOii00Oi <= (k_bar(60) AND wire_nilOl1lO_dataout); + niOii00Ol <= (k_bar(59) AND wire_nilOl1ll_dataout); + niOii00OO <= (k_bar(58) AND wire_nilOl1li_dataout); + niOii010i <= (nl0iOil1l AND niOii010O); + niOii010l <= (nl0iOil1i AND niOii010O); + niOii010O <= (nl0iOil0O AND niOili01O); + niOii011i <= wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0); + niOii011l <= wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0); + niOii011O <= (nl0iOil0i AND niOii010O); + niOii01ii <= ((wire_w_lg_w_k_conf_range46162w51958w(0) AND wire_nlill0Oll_w_lg_nl0l0i0li51959w(0)) AND wire_nlill0Oll_w_lg_w_lg_nli11l0Ol51961w51962w(0)); + niOii01il <= ((wire_nl0l0l0Oi_dataout OR niOiili0O) OR niOili0il); + niOii01iO <= (wire_w_lg_w_k_conf_range46175w51978w(0) AND (NOT k_conf(227))); + niOii01li <= wire_w_lg_w_k_conf_range46162w51908w(0); + niOii01ll <= wire_w_lg_w_k_conf_range46162w51905w(0); + niOii01lO <= wire_w_lg_w_k_conf_range46162w51902w(0); + niOii01Oi <= wire_w_lg_w_k_conf_range46162w51900w(0); + niOii01Ol <= (niOili1OO AND wire_w_lg_w_k_conf_range46194w51896w(0)); + niOii01OO <= (((NOT k_conf(225)) AND wire_w_lg_w_k_conf_range46173w46174w(0)) AND (NOT k_conf(227))); + niOii0i0i <= (k_bar(54) AND wire_nilOl10O_dataout); + niOii0i0l <= (k_bar(53) AND wire_nilOl10l_dataout); + niOii0i0O <= (k_bar(52) AND wire_nilOl10i_dataout); + niOii0i1i <= (k_bar(57) AND wire_nilOl1iO_dataout); + niOii0i1l <= (k_bar(56) AND wire_nilOl1il_dataout); + niOii0i1O <= (k_bar(55) AND wire_nilOl1ii_dataout); + niOii0iii <= (k_bar(51) AND wire_nilOl11O_dataout); + niOii0iil <= (k_bar(50) AND wire_nilOl11l_dataout); + niOii0iiO <= (k_bar(49) AND wire_nilOl11i_dataout); + niOii0ili <= (k_bar(48) AND wire_nilOiOOO_dataout); + niOii0ill <= (k_bar(47) AND wire_nilOiOOl_dataout); + niOii0ilO <= (k_bar(46) AND wire_nilOiOOi_dataout); + niOii0iOi <= (k_bar(45) AND wire_nilOiOlO_dataout); + niOii0iOl <= (k_bar(44) AND wire_nilOiOll_dataout); + niOii0iOO <= (k_bar(43) AND wire_nilOiOli_dataout); + niOii0l0i <= (k_bar(39) AND wire_nilOiO0O_dataout); + niOii0l0l <= (k_bar(38) AND wire_nilOiO0l_dataout); + niOii0l0O <= (k_bar(37) AND wire_nilOiO0i_dataout); + niOii0l1i <= (k_bar(42) AND wire_nilOiOiO_dataout); + niOii0l1l <= (k_bar(41) AND wire_nilOiOil_dataout); + niOii0l1O <= (k_bar(40) AND wire_nilOiOii_dataout); + niOii0lii <= (k_bar(36) AND wire_nilOiO1O_dataout); + niOii0lil <= (((((((((((((((((((((((((((((((wire_nlill0Oll_w_lg_nl0lllO1i51415w(0) AND wire_nlill0Oll_w_lg_nl0llllOO51416w(0)) AND wire_nlill0Oll_w_lg_nl0llllOl51418w(0)) AND wire_nlill0Oll_w_lg_nl0llllOi51420w(0)) AND wire_nlill0Oll_w_lg_nl0lllllO51422w(0)) AND wire_nlill0Oll_w_lg_nl0llllll51424w(0)) AND wire_nlill0Oll_w_lg_nl0llllli51426w(0)) AND wire_nlill0Oll_w_lg_nl0lllliO51428w(0)) AND wire_nlill0Oll_w_lg_nl0llllil51430w(0)) AND wire_nlill0Oll_w_lg_nl0llllii51432w(0)) AND wire_nlill0Oll_w_lg_nl0llll0O51434w(0)) AND wire_nlill0Oll_w_lg_nl0llll0l51436w(0)) AND wire_nlill0Oll_w_lg_nl0llll0i51438w(0)) AND wire_nlill0Oll_w_lg_nl0llll1O51440w(0)) AND wire_nlill0Oll_w_lg_nl0llll1l51442w(0)) AND wire_nlill0Oll_w_lg_nl0llll1i51444w(0)) AND wire_nlill0Oll_w_lg_nl0llliOO51446w(0)) AND wire_nlill0Oll_w_lg_nl0llliOl51448w(0)) AND wire_nlill0Oll_w_lg_nl0llliOi51450w(0)) AND wire_nlill0Oll_w_lg_nl0lllilO51452w(0)) AND wire_nlill0Oll_w_lg_nl0lllill51454w(0)) AND wire_nlill0Oll_w_lg_nl0lllili51456w(0)) AND wire_nlill0Oll_w_lg_nl0llliiO51458w(0)) AND wire_nlill0Oll_w_lg_nl0llliil51460w(0)) AND wire_nlill0Oll_w_lg_nl0llliii51462w(0)) AND wire_nlill0Oll_w_lg_nl0llli0O51464w(0)) AND wire_nlill0Oll_w_lg_nl0llli0l51466w(0)) AND wire_nlill0Oll_w_lg_nl0llli0i51468w(0)) AND wire_nlill0Oll_w_lg_nl0llli1O51470w(0)) AND wire_nlill0Oll_w_lg_nl0llli1l51472w(0)) AND wire_nlill0Oll_w_lg_nl0llli1i51474w(0)) AND wire_nlill0Oll_w_lg_nl0lliiiO51476w(0)); + niOii0liO <= wire_w_lg_w_lg_w_k_bar_range45710w45711w51414w(0); + niOii0lli <= (k_bar(35) AND nl0llli1O); + niOii0lll <= (k_bar(34) AND nl0llli1l); + niOii0llO <= (k_bar(33) AND nl0llli1i); + niOii0lOi <= (k_bar(32) AND nl0lliiiO); + niOii0lOl <= (nl0iOilli AND niOili01O); + niOii0lOO <= (niOii0O1i OR wire_niO01Oil_dataout); + niOii0O0i <= (((((((((((((((((((((((((((((((wire_w_lg_w_k_bar_range45712w45713w(0) AND wire_w_lg_w_k_bar_range45710w45711w(0)) AND (NOT k_bar(2))) AND (NOT k_bar(3))) AND (NOT k_bar(4))) AND (NOT k_bar(5))) AND (NOT k_bar(6))) AND (NOT k_bar(7))) AND (NOT k_bar(8))) AND (NOT k_bar(9))) AND (NOT k_bar(10))) AND (NOT k_bar(11))) AND (NOT k_bar(12))) AND (NOT k_bar(13))) AND (NOT k_bar(14))) AND (NOT k_bar(15))) AND (NOT k_bar(16))) AND (NOT k_bar(17))) AND (NOT k_bar(18))) AND (NOT k_bar(19))) AND (NOT k_bar(20))) AND (NOT k_bar(21))) AND (NOT k_bar(22))) AND (NOT k_bar(23))) AND (NOT k_bar(24))) AND (NOT k_bar(25))) AND (NOT k_bar(26))) AND (NOT k_bar(27))) AND (NOT k_bar(28))) AND (NOT k_bar(29))) AND (NOT k_bar(30))) AND (NOT k_bar(31))); + niOii0O0l <= ((((((((NOT (niOil1l0O XOR (k_bar(100) AND wire_nl01l1lii_o(3)))) AND (NOT (niOil1lii XOR (k_bar(101) AND wire_nl01l1lii_o(4))))) AND (NOT (niOil1lil XOR (k_bar(102) AND wire_nl01l1lii_o(5))))) AND (NOT (niOil1liO XOR (k_bar(103) AND wire_nl01l1lii_o(6))))) AND (NOT (niOil1lli XOR (k_bar(104) AND wire_nl01l1lii_o(7))))) AND (NOT (niOil1lll XOR (k_bar(105) AND wire_nl01l1lii_o(8))))) AND (NOT (niOil1llO XOR (k_bar(106) AND wire_nl01l1lii_o(9))))) AND (NOT (niOil1lOi XOR (k_bar(107) AND wire_nl01l1lii_o(10))))); + niOii0O0O <= ((((((((NOT (niOil010l XOR (k_bar(68) AND wire_nl01l1lii_o(3)))) AND (NOT (niOil010O XOR (k_bar(69) AND wire_nl01l1lii_o(4))))) AND (NOT (niOil01ii XOR (k_bar(70) AND wire_nl01l1lii_o(5))))) AND (NOT (niOil01il XOR (k_bar(71) AND wire_nl01l1lii_o(6))))) AND (NOT (niOil01iO XOR (k_bar(72) AND wire_nl01l1lii_o(7))))) AND (NOT (niOil01li XOR (k_bar(73) AND wire_nl01l1lii_o(8))))) AND (NOT (niOil01ll XOR (k_bar(74) AND wire_nl01l1lii_o(9))))) AND (NOT (niOil01lO XOR (k_bar(75) AND wire_nl01l1lii_o(10))))); + niOii0O1i <= (((((((((((((((((((((((((((((((wire_w_lg_w_k_bar_range51119w51288w(0) AND (NOT k_bar(33))) AND (NOT k_bar(34))) AND (NOT k_bar(35))) AND (NOT k_bar(36))) AND (NOT k_bar(37))) AND (NOT k_bar(38))) AND (NOT k_bar(39))) AND (NOT k_bar(40))) AND (NOT k_bar(41))) AND (NOT k_bar(42))) AND (NOT k_bar(43))) AND (NOT k_bar(44))) AND (NOT k_bar(45))) AND (NOT k_bar(46))) AND (NOT k_bar(47))) AND (NOT k_bar(48))) AND (NOT k_bar(49))) AND (NOT k_bar(50))) AND (NOT k_bar(51))) AND (NOT k_bar(52))) AND (NOT k_bar(53))) AND (NOT k_bar(54))) AND (NOT k_bar(55))) AND (NOT k_bar(56))) AND (NOT k_bar(57))) AND (NOT k_bar(58))) AND (NOT k_bar(59))) AND (NOT k_bar(60))) AND (NOT k_bar(61))) AND (NOT k_bar(62))) AND (NOT k_bar(63))); + niOii0O1l <= (nl0iOiliO AND niOili01O); + niOii0O1O <= (niOii0O0i OR wire_niO01Oil_dataout); + niOii0Oii <= ((((((((((((((((((((((((((((NOT (niOil010l XOR (k_bar(68) AND wire_nilOiO1O_dataout))) AND (NOT (niOil010O XOR (k_bar(69) AND wire_nilOiO0i_dataout)))) AND (NOT (niOil01ii XOR (k_bar(70) AND wire_nilOiO0l_dataout)))) AND (NOT (niOil01il XOR (k_bar(71) AND wire_nilOiO0O_dataout)))) AND (NOT (niOil01iO XOR (k_bar(72) AND wire_nilOiOii_dataout)))) AND (NOT (niOil01li XOR (k_bar(73) AND wire_nilOiOil_dataout)))) AND (NOT (niOil01ll XOR (k_bar(74) AND wire_nilOiOiO_dataout)))) AND (NOT (niOil01lO XOR (k_bar(75) AND wire_nilOiOli_dataout)))) AND (NOT (niOil01Oi XOR (k_bar(76) AND wire_nilOiOll_dataout)))) AND (NOT (niOil01Ol XOR (k_bar(77) AND wire_nilOiOlO_dataout)))) AND (NOT (niOil01OO XOR (k_bar(78) AND wire_nilOiOOi_dataout)))) AND (NOT (niOil001i XOR (k_bar(79) AND wire_nilOiOOl_dataout)))) AND (NOT (niOil001l XOR (k_bar(80) AND wire_nilOiOOO_dataout)))) AND (NOT (niOil001O XOR (k_bar(81) AND wire_nilOl11i_dataout)))) AND (NOT (niOil000i XOR (k_bar(82) AND wire_nilOl11l_dataout)))) AND (NOT (niOil000l XOR (k_bar(83) AND wire_nilOl11O_dataout)))) AND (NOT (niOil000O XOR (k_bar(84) AND wire_nilOl10i_dataout)))) AND (NOT (niOil00ii XOR (k_bar(85) AND wire_nilOl10l_dataout)))) AND (NOT (niOil00il XOR (k_bar(86) AND wire_nilOl10O_dataout)))) AND (NOT (niOil00iO XOR (k_bar(87) AND wire_nilOl1ii_dataout)))) AND (NOT (niOil00li XOR (k_bar(88) AND wire_nilOl1il_dataout)))) AND (NOT (niOil00ll XOR (k_bar(89) AND wire_nilOl1iO_dataout)))) AND (NOT (niOil00lO XOR (k_bar(90) AND wire_nilOl1li_dataout)))) AND (NOT (niOil00Oi XOR (k_bar(91) AND wire_nilOl1ll_dataout)))) AND (NOT (niOil00Ol XOR (k_bar(92) AND wire_nilOl1lO_dataout)))) AND (NOT (niOil00OO XOR (k_bar(93) AND wire_nilOl1Oi_dataout)))) AND (NOT (niOil0i1i XOR (k_bar(94) AND wire_nilOl1Ol_dataout)))) AND (NOT (niOil0i1l XOR (k_bar(95) AND wire_nilOl1OO_dataout)))); + niOii0Oil <= ((((((((wire_w_lg_w_nl0lO0Oii50931w50932w(0) AND (NOT (niOil1Oll XOR niOiii11i))) AND (NOT (niOil1OlO XOR niOii0OOO))) AND (NOT (niOil1OOi XOR niOii0OOl))) AND (NOT (niOil1OOl XOR niOii0OOi))) AND (NOT (niOil1OOO XOR niOii0OlO))) AND (NOT (niOil011i XOR niOii0Oll))) AND (NOT (niOil011l XOR niOii0Oli))) AND (NOT (niOil011O XOR niOii0OiO))); + niOii0OiO <= (k_bar(127) AND wire_nilOl1OO_dataout); + niOii0Oli <= (k_bar(126) AND wire_nilOl1Ol_dataout); + niOii0Oll <= (k_bar(125) AND wire_nilOl1Oi_dataout); + niOii0OlO <= (k_bar(124) AND wire_nilOl1lO_dataout); + niOii0OOi <= (k_bar(123) AND wire_nilOl1ll_dataout); + niOii0OOl <= (k_bar(122) AND wire_nilOl1li_dataout); + niOii0OOO <= (k_bar(121) AND wire_nilOl1iO_dataout); + niOii100i <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52429w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND nl0l11O0O); + niOii100l <= (wire_nlill0Oll_w52435w(0) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii100O <= (wire_nlill0Oll_w52435w(0) AND nl0l11O0O); + niOii101i <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11OOO52342w52344w52346w(0) AND wire_nlill0Oll_w_lg_nl0l11OlO52347w(0)) AND nl0l11Oll); + niOii101l <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11OOO52342w52344w52346w(0) AND wire_nlill0Oll_w_lg_nl0l11OlO52347w(0)) AND wire_nlill0Oll_w_lg_nl0l11Oll52487w(0)); + niOii101O <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52429w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii10ii <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52438w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii10il <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52438w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND nl0l11O0O); + niOii10iO <= (wire_nlill0Oll_w52442w(0) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii10li <= (wire_nlill0Oll_w52442w(0) AND nl0l11O0O); + niOii10ll <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52446w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii10lO <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52446w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND nl0l11O0O); + niOii10Oi <= (wire_nlill0Oll_w52450w(0) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii10Ol <= (wire_nlill0Oll_w52450w(0) AND nl0l11O0O); + niOii10OO <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52453w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii110i <= ((wire_nl0l1OOlO_w_lg_w_lg_dataout52384w52391w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOii110l <= ((wire_nl0l1OOlO_w_lg_w_lg_dataout52384w52391w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_dataout); + niOii110O <= (wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52384w52391w52395w(0) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOii111i <= (((wire_nl0l1OOlO_w_lg_dataout52384w(0) AND wire_nl0l1OOli_w_lg_dataout52352w(0)) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOii111l <= (((wire_nl0l1OOlO_w_lg_dataout52384w(0) AND wire_nl0l1OOli_w_lg_dataout52352w(0)) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_dataout); + niOii111O <= (((wire_nl0l1OOlO_w_lg_dataout52384w(0) AND wire_nl0l1OOli_w_lg_dataout52352w(0)) AND wire_nl0l1OOiO_dataout) AND wire_nl0l1OOil_dataout); + niOii11ii <= (wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52384w52391w52395w(0) AND wire_nl0l1OOil_dataout); + niOii11il <= ((wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52399w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_dataout); + niOii11iO <= (wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52399w52402w(0) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOii11li <= (wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52399w52402w(0) AND wire_nl0l1OOil_dataout); + niOii11ll <= ((wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52405w(0) AND wire_nl0l1OOiO_w_lg_dataout52354w(0)) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOii11lO <= (wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52405w52408w(0) AND wire_nl0l1OOil_w_lg_dataout52356w(0)); + niOii11Oi <= (wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52405w52408w(0) AND wire_nl0l1OOil_dataout); + niOii11Ol <= (wire_nlill0Oll_w52490w(0) AND wire_nlill0Oll_w_lg_nl0l11Oll52487w(0)); + niOii11OO <= (((wire_nlill0Oll_w_lg_nl0l11OOO52492w(0) AND wire_nlill0Oll_w_lg_nl0l11OOi52345w(0)) AND wire_nlill0Oll_w_lg_nl0l11OlO52347w(0)) AND wire_nlill0Oll_w_lg_nl0l11Oll52487w(0)); + niOii1i0i <= (((wire_nlill0Oll_w_lg_nl0l11Oli52460w(0) AND wire_nlill0Oll_w_lg_nl0l11Oil52428w(0)) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii1i0l <= (((wire_nlill0Oll_w_lg_nl0l11Oli52460w(0) AND wire_nlill0Oll_w_lg_nl0l11Oil52428w(0)) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND nl0l11O0O); + niOii1i0O <= (((wire_nlill0Oll_w_lg_nl0l11Oli52460w(0) AND wire_nlill0Oll_w_lg_nl0l11Oil52428w(0)) AND nl0l11Oii) AND nl0l11O0O); + niOii1i1i <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52453w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND nl0l11O0O); + niOii1i1l <= (wire_nlill0Oll_w52457w(0) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii1i1O <= (wire_nlill0Oll_w52457w(0) AND nl0l11O0O); + niOii1iii <= ((wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52460w52467w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii1iil <= ((wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52460w52467w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND nl0l11O0O); + niOii1iiO <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52460w52467w52471w(0) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii1ili <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52460w52467w52471w(0) AND nl0l11O0O); + niOii1ill <= ((wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52475w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND nl0l11O0O); + niOii1ilO <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52475w52478w(0) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii1iOi <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52475w52478w(0) AND nl0l11O0O); + niOii1iOl <= ((wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52481w(0) AND wire_nlill0Oll_w_lg_nl0l11Oii52430w(0)) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii1iOO <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52481w52484w(0) AND wire_nlill0Oll_w_lg_nl0l11O0O52432w(0)); + niOii1l0i <= (wire_nl0l1Oi1i_w_lg_dataout52091w(0) AND wire_nl0l1O0OO_w_lg_dataout52093w(0)); + niOii1l0l <= (nl0l101il OR nl0ili1ll); + niOii1l0O <= (nl010Oi1i AND (wire_w_lg_w_lg_niOii1liO52084w52085w(0) AND (nl0l1010O OR nl0l1010i))); + niOii1l1i <= (wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52481w52484w(0) AND nl0l11O0O); + niOii1l1l <= (((nl0l101ii OR nl0l1010l) AND niOii1l1O) AND nl0iOl10i); + niOii1l1O <= ((wire_nlill0Oll_w_lg_nl0l1011O52420w(0) AND wire_nlill0Oll_w_lg_nl0l1011l52421w(0)) AND wire_nlill0Oll_w_lg_nl0l1011i52423w(0)); + niOii1lii <= (niii0Ol OR niii0Oi); + niOii1lil <= ((wire_w_lg_w_lg_niOii1OOl52076w52077w(0) OR (wire_w_lg_niOii1OOl52072w(0) AND wire_nlill0Oll_w_lg_nl0i1liil52078w(0))) AND wire_nlill0Oll_w_lg_nl0iOl10i52081w(0)); + niOii1liO <= (wire_w_lg_w_lg_niOii1OOl52070w52071w(0) OR wire_nlill0Oll_w_lg_nl11OO00i52073w(0)); + niOii1lli <= ((wire_nl1lOOO0i_w_lg_w_lg_w_lg_w_lg_dataout5075w52330w52331w52332w(0) AND wire_nl1lOOlOO_w_lg_dataout52012w(0)) AND wire_nl1lOOlOl_w_lg_dataout52282w(0)); + niOii1lll <= (niOii1OOl AND niOii1llO); + niOii1llO <= ((wire_nlill0Oll_w_lg_nl0l01O1O52284w(0) AND wire_nlill0Oll_w_lg_nl0l01O1l52285w(0)) AND wire_nlill0Oll_w_lg_nl0l010OO52287w(0)); + niOii1lOi <= ((wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52299w52308w(0) AND wire_nl1lOO1ii_w_lg_dataout52322w(0)) AND wire_nl1lOO10O_w_lg_dataout52141w(0)); + niOii1lOl <= ((((wire_nl1lOO1li_w52309w(0) AND wire_nl1lOO10O_w_lg_dataout52141w(0)) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_w_lg_dataout52144w(0)); + niOii1lOO <= ((((wire_nl1lOO1li_w52309w(0) AND wire_nl1lOO10O_w_lg_dataout52141w(0)) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_dataout); + niOii1O0i <= (((wire_nl1lOO1li_w_lg_w52301w52302w(0) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_dataout) AND wire_nl1lOO11O_dataout); + niOii1O0l <= (((wire_nl1lOO1li_w_lg_w52301w52302w(0) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_dataout); + niOii1O0O <= ((((wire_nl1lOO1li_w52293w(0) AND wire_nl1lOO10O_w_lg_dataout52141w(0)) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_w_lg_dataout52144w(0)); + niOii1O1i <= ((((wire_nl1lOO1li_w52309w(0) AND wire_nl1lOO10O_w_lg_dataout52141w(0)) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_dataout) AND wire_nl1lOO11O_dataout); + niOii1O1l <= (((wire_nl1lOO1li_w_lg_w52301w52302w(0) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_w_lg_dataout52144w(0)); + niOii1O1O <= ((wire_nl1lOO1li_w_lg_w_lg_w52301w52318w52319w(0) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_w_lg_dataout52144w(0)); + niOii1Oii <= (((wire_nl1lOO1li_w_lg_w52323w52324w(0) AND wire_nl1lOO10l_w_lg_dataout52147w(0)) AND wire_nl1lOO10i_w_lg_dataout52155w(0)) AND wire_nl1lOO11O_w_lg_dataout52144w(0)); + niOii1Oil <= ((niOii1OiO AND ((wire_nl1lOOO0i_dataout AND wire_nl1lOOO1O_dataout) AND wire_nl1lOOO1l_w_lg_dataout5083w(0))) AND nl0l101il); + niOii1OiO <= (nl011l1ii AND niOii1Oli); + niOii1Oli <= (wire_nlill0Oll_w_lg_nl1OilOil55037w(0) AND wire_nlill0Oll_w_lg_w_lg_nl1Oillll55053w55054w(0)); + niOii1Oll <= (wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout52008w52009w52010w(0) OR (wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w52011w(0) AND wire_nl1lOOlOO_w_lg_dataout52012w(0))); + niOii1OlO <= (wire_nl1lOOO1O_w_lg_w_lg_w_lg_w_lg_dataout5082w5084w5086w52281w(0) AND wire_nl1lOOlOl_w_lg_dataout52282w(0)); + niOii1OOi <= (wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w5086w(0) AND wire_nl1lOOlOO_w_lg_dataout52012w(0)); + niOii1OOl <= ((niOii011l OR niOii011i) OR niOii1OOO); + niOii1OOO <= wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0); + niOiii00i <= (k_bar(102) AND wire_nilOiO0l_dataout); + niOiii00l <= (k_bar(101) AND wire_nilOiO0i_dataout); + niOiii00O <= (k_bar(100) AND wire_nilOiO1O_dataout); + niOiii01i <= (k_bar(105) AND wire_nilOiOil_dataout); + niOiii01l <= (k_bar(104) AND wire_nilOiOii_dataout); + niOiii01O <= (k_bar(103) AND wire_nilOiO0O_dataout); + niOiii0ii <= (((((((((((((((((((((((((((((((wire_nl0O10ilO_w_lg_dataout50528w(0) AND wire_nl0O10ill_w_lg_dataout50529w(0)) AND wire_nl0O10ili_w_lg_dataout50531w(0)) AND wire_nl0O10iiO_w_lg_dataout50533w(0)) AND wire_nl0O10iil_w_lg_dataout50535w(0)) AND wire_nl0O10iii_w_lg_dataout50537w(0)) AND wire_nl0O10i0O_w_lg_dataout50539w(0)) AND wire_nl0O10i0l_w_lg_dataout50541w(0)) AND wire_nl0O10i0i_w_lg_dataout50543w(0)) AND wire_nl0O10i1O_w_lg_dataout50545w(0)) AND wire_nl0O10i1l_w_lg_dataout50547w(0)) AND wire_nl0O10i1i_w_lg_dataout50549w(0)) AND wire_nl0O100OO_w_lg_dataout50551w(0)) AND wire_nl0O100Ol_w_lg_dataout50553w(0)) AND wire_nl0O100Oi_w_lg_dataout50555w(0)) AND wire_nl0O100lO_w_lg_dataout50557w(0)) AND wire_nl0O100ll_w_lg_dataout50559w(0)) AND wire_nl0O100li_w_lg_dataout50561w(0)) AND wire_nl0O100iO_w_lg_dataout50563w(0)) AND wire_nl0O100il_w_lg_dataout50565w(0)) AND wire_nl0O100ii_w_lg_dataout50567w(0)) AND wire_nl0O1000O_w_lg_dataout50569w(0)) AND wire_nl0O1000l_w_lg_dataout50571w(0)) AND wire_nl0O1000i_w_lg_dataout50573w(0)) AND wire_nl0O1001O_w_lg_dataout50575w(0)) AND wire_nl0O1001l_w_lg_dataout50577w(0)) AND wire_nl0O1001i_w_lg_dataout50579w(0)) AND wire_nl0O101OO_w_lg_dataout50581w(0)) AND wire_nl0O101Ol_w_lg_dataout50583w(0)) AND wire_nl0O101Oi_w_lg_dataout50585w(0)) AND wire_nl0O101lO_w_lg_dataout50587w(0)) AND wire_nl0O101ll_w_lg_dataout50589w(0)); + niOiii0il <= (k_bar(99) AND wire_nl0O101Ol_dataout); + niOiii0iO <= (k_bar(98) AND wire_nl0O101Oi_dataout); + niOiii0li <= (k_bar(97) AND wire_nl0O101lO_dataout); + niOiii0ll <= (k_bar(96) AND wire_nl0O101ll_dataout); + niOiii0lO <= (nl0iOillO AND niOili01O); + niOiii0Oi <= (niOiii0Ol OR wire_niO01Oil_dataout); + niOiii0Ol <= (((((((((((((((((((((((((((((((wire_w_lg_w_k_bar_range47798w47799w(0) AND (NOT k_bar(97))) AND (NOT k_bar(98))) AND (NOT k_bar(99))) AND (NOT k_bar(100))) AND (NOT k_bar(101))) AND (NOT k_bar(102))) AND (NOT k_bar(103))) AND (NOT k_bar(104))) AND (NOT k_bar(105))) AND (NOT k_bar(106))) AND (NOT k_bar(107))) AND (NOT k_bar(108))) AND (NOT k_bar(109))) AND (NOT k_bar(110))) AND (NOT k_bar(111))) AND (NOT k_bar(112))) AND (NOT k_bar(113))) AND (NOT k_bar(114))) AND (NOT k_bar(115))) AND (NOT k_bar(116))) AND (NOT k_bar(117))) AND (NOT k_bar(118))) AND (NOT k_bar(119))) AND (NOT k_bar(120))) AND (NOT k_bar(121))) AND (NOT k_bar(122))) AND (NOT k_bar(123))) AND (NOT k_bar(124))) AND (NOT k_bar(125))) AND (NOT k_bar(126))) AND (NOT k_bar(127))); + niOiii0OO <= (nl0iOilll AND niOili01O); + niOiii10i <= (k_bar(117) AND wire_nilOl10l_dataout); + niOiii10l <= (k_bar(116) AND wire_nilOl10i_dataout); + niOiii10O <= (k_bar(115) AND wire_nilOl11O_dataout); + niOiii11i <= (k_bar(120) AND wire_nilOl1il_dataout); + niOiii11l <= (k_bar(119) AND wire_nilOl1ii_dataout); + niOiii11O <= (k_bar(118) AND wire_nilOl10O_dataout); + niOiii1ii <= (k_bar(114) AND wire_nilOl11l_dataout); + niOiii1il <= (k_bar(113) AND wire_nilOl11i_dataout); + niOiii1iO <= (k_bar(112) AND wire_nilOiOOO_dataout); + niOiii1li <= (k_bar(111) AND wire_nilOiOOl_dataout); + niOiii1ll <= (k_bar(110) AND wire_nilOiOOi_dataout); + niOiii1lO <= (k_bar(109) AND wire_nilOiOlO_dataout); + niOiii1Oi <= (k_bar(108) AND wire_nilOiOll_dataout); + niOiii1Ol <= (k_bar(107) AND wire_nilOiOli_dataout); + niOiii1OO <= (k_bar(106) AND wire_nilOiOiO_dataout); + niOiiii0i <= ((((((((NOT (niOil10ii XOR (k_bar(132) AND wire_nl01l1lii_o(3)))) AND (NOT (niOil10il XOR (k_bar(133) AND wire_nl01l1lii_o(4))))) AND (NOT (niOil10iO XOR (k_bar(134) AND wire_nl01l1lii_o(5))))) AND (NOT (niOil10li XOR (k_bar(135) AND wire_nl01l1lii_o(6))))) AND (NOT (niOil10ll XOR (k_bar(136) AND wire_nl01l1lii_o(7))))) AND (NOT (niOil10lO XOR (k_bar(137) AND wire_nl01l1lii_o(8))))) AND (NOT (niOil10Oi XOR (k_bar(138) AND wire_nl01l1lii_o(9))))) AND (NOT (niOil10Ol XOR (k_bar(139) AND wire_nl01l1lii_o(10))))); + niOiiii0l <= ((((((((((((((((((((((((((((NOT (niOil10ii XOR (k_bar(132) AND wire_nilOiO1O_dataout))) AND (NOT (niOil10il XOR (k_bar(133) AND wire_nilOiO0i_dataout)))) AND (NOT (niOil10iO XOR (k_bar(134) AND wire_nilOiO0l_dataout)))) AND (NOT (niOil10li XOR (k_bar(135) AND wire_nilOiO0O_dataout)))) AND (NOT (niOil10ll XOR (k_bar(136) AND wire_nilOiOii_dataout)))) AND (NOT (niOil10lO XOR (k_bar(137) AND wire_nilOiOil_dataout)))) AND (NOT (niOil10Oi XOR (k_bar(138) AND wire_nilOiOiO_dataout)))) AND (NOT (niOil10Ol XOR (k_bar(139) AND wire_nilOiOli_dataout)))) AND (NOT (niOil10OO XOR (k_bar(140) AND wire_nilOiOll_dataout)))) AND (NOT (niOil1i1i XOR (k_bar(141) AND wire_nilOiOlO_dataout)))) AND (NOT (niOil1i1l XOR (k_bar(142) AND wire_nilOiOOi_dataout)))) AND (NOT (niOil1i1O XOR (k_bar(143) AND wire_nilOiOOl_dataout)))) AND (NOT (niOil1i0i XOR (k_bar(144) AND wire_nilOiOOO_dataout)))) AND (NOT (niOil1i0l XOR (k_bar(145) AND wire_nilOl11i_dataout)))) AND (NOT (niOil1i0O XOR (k_bar(146) AND wire_nilOl11l_dataout)))) AND (NOT (niOil1iii XOR (k_bar(147) AND wire_nilOl11O_dataout)))) AND (NOT (niOil1iil XOR (k_bar(148) AND wire_nilOl10i_dataout)))) AND (NOT (niOil1iiO XOR (k_bar(149) AND wire_nilOl10l_dataout)))) AND (NOT (niOil1ili XOR (k_bar(150) AND wire_nilOl10O_dataout)))) AND (NOT (niOil1ill XOR (k_bar(151) AND wire_nilOl1ii_dataout)))) AND (NOT (niOil1ilO XOR (k_bar(152) AND wire_nilOl1il_dataout)))) AND (NOT (niOil1iOi XOR (k_bar(153) AND wire_nilOl1iO_dataout)))) AND (NOT (niOil1iOl XOR (k_bar(154) AND wire_nilOl1li_dataout)))) AND (NOT (niOil1iOO XOR (k_bar(155) AND wire_nilOl1ll_dataout)))) AND (NOT (niOil1l1i XOR (k_bar(156) AND wire_nilOl1lO_dataout)))) AND (NOT (niOil1l1l XOR (k_bar(157) AND wire_nilOl1Oi_dataout)))) AND (NOT (niOil1l1O XOR (k_bar(158) AND wire_nilOl1Ol_dataout)))) AND (NOT (niOil1l0i XOR (k_bar(159) AND wire_nilOl1OO_dataout)))); + niOiiii0O <= ((((((((wire_w_lg_w_nl0O01i1l50047w50048w(0) AND (NOT (niOil11Oi XOR niOiiiiOl))) AND (NOT (niOil11Ol XOR niOiiiiOi))) AND (NOT (niOil11OO XOR niOiiiilO))) AND (NOT (niOil101i XOR niOiiiill))) AND (NOT (niOil101l XOR niOiiiili))) AND (NOT (niOil101O XOR niOiiiiiO))) AND (NOT (niOil100i XOR niOiiiiil))) AND (NOT (niOil100l XOR niOiiiiii))); + niOiiii1i <= (niOiiii1l OR wire_niO01Oil_dataout); + niOiiii1l <= (((((((((((((((((((((((((((((((wire_w_lg_w_k_bar_range45805w45806w(0) AND wire_w_lg_w_k_bar_range45803w45804w(0)) AND (NOT k_bar(66))) AND (NOT k_bar(67))) AND (NOT k_bar(68))) AND (NOT k_bar(69))) AND (NOT k_bar(70))) AND (NOT k_bar(71))) AND (NOT k_bar(72))) AND (NOT k_bar(73))) AND (NOT k_bar(74))) AND (NOT k_bar(75))) AND (NOT k_bar(76))) AND (NOT k_bar(77))) AND (NOT k_bar(78))) AND (NOT k_bar(79))) AND (NOT k_bar(80))) AND (NOT k_bar(81))) AND (NOT k_bar(82))) AND (NOT k_bar(83))) AND (NOT k_bar(84))) AND (NOT k_bar(85))) AND (NOT k_bar(86))) AND (NOT k_bar(87))) AND (NOT k_bar(88))) AND (NOT k_bar(89))) AND (NOT k_bar(90))) AND (NOT k_bar(91))) AND (NOT k_bar(92))) AND (NOT k_bar(93))) AND (NOT k_bar(94))) AND (NOT k_bar(95))); + niOiiii1O <= ((((((((NOT (niOiiOOil XOR (k_bar(164) AND wire_nl01l1lii_o(3)))) AND (NOT (niOiiOOiO XOR (k_bar(165) AND wire_nl01l1lii_o(4))))) AND (NOT (niOiiOOli XOR (k_bar(166) AND wire_nl01l1lii_o(5))))) AND (NOT (niOiiOOll XOR (k_bar(167) AND wire_nl01l1lii_o(6))))) AND (NOT (niOiiOOlO XOR (k_bar(168) AND wire_nl01l1lii_o(7))))) AND (NOT (niOiiOOOi XOR (k_bar(169) AND wire_nl01l1lii_o(8))))) AND (NOT (niOiiOOOl XOR (k_bar(170) AND wire_nl01l1lii_o(9))))) AND (NOT (niOiiOOOO XOR (k_bar(171) AND wire_nl01l1lii_o(10))))); + niOiiiiii <= (k_bar(191) AND wire_nilOl1OO_dataout); + niOiiiiil <= (k_bar(190) AND wire_nilOl1Ol_dataout); + niOiiiiiO <= (k_bar(189) AND wire_nilOl1Oi_dataout); + niOiiiili <= (k_bar(188) AND wire_nilOl1lO_dataout); + niOiiiill <= (k_bar(187) AND wire_nilOl1ll_dataout); + niOiiiilO <= (k_bar(186) AND wire_nilOl1li_dataout); + niOiiiiOi <= (k_bar(185) AND wire_nilOl1iO_dataout); + niOiiiiOl <= (k_bar(184) AND wire_nilOl1il_dataout); + niOiiiiOO <= (k_bar(183) AND wire_nilOl1ii_dataout); + niOiiil0i <= (k_bar(179) AND wire_nilOl11O_dataout); + niOiiil0l <= (k_bar(178) AND wire_nilOl11l_dataout); + niOiiil0O <= (k_bar(177) AND wire_nilOl11i_dataout); + niOiiil1i <= (k_bar(182) AND wire_nilOl10O_dataout); + niOiiil1l <= (k_bar(181) AND wire_nilOl10l_dataout); + niOiiil1O <= (k_bar(180) AND wire_nilOl10i_dataout); + niOiiilii <= (k_bar(176) AND wire_nilOiOOO_dataout); + niOiiilil <= (k_bar(175) AND wire_nilOiOOl_dataout); + niOiiiliO <= (k_bar(174) AND wire_nilOiOOi_dataout); + niOiiilli <= (k_bar(173) AND wire_nilOiOlO_dataout); + niOiiilll <= (k_bar(172) AND wire_nilOiOll_dataout); + niOiiillO <= (k_bar(171) AND wire_nilOiOli_dataout); + niOiiilOi <= (k_bar(170) AND wire_nilOiOiO_dataout); + niOiiilOl <= (k_bar(169) AND wire_nilOiOil_dataout); + niOiiilOO <= (k_bar(168) AND wire_nilOiOii_dataout); + niOiiiO0i <= (k_bar(164) AND wire_nilOiO1O_dataout); + niOiiiO0l <= (((((((((((((((((((((((((((((((wire_nl0Oi11ii_w_lg_dataout49644w(0) AND wire_nl0Oi110O_w_lg_dataout49645w(0)) AND wire_nl0Oi110l_w_lg_dataout49647w(0)) AND wire_nl0Oi110i_w_lg_dataout49649w(0)) AND wire_nl0Oi111O_w_lg_dataout49651w(0)) AND wire_nl0Oi111l_w_lg_dataout49653w(0)) AND wire_nl0Oi111i_w_lg_dataout49655w(0)) AND wire_nl0O0OOOO_w_lg_dataout49657w(0)) AND wire_nl0O0OOOl_w_lg_dataout49659w(0)) AND wire_nl0O0OOOi_w_lg_dataout49661w(0)) AND wire_nl0O0OOlO_w_lg_dataout49663w(0)) AND wire_nl0O0OOll_w_lg_dataout49665w(0)) AND wire_nl0O0OOli_w_lg_dataout49667w(0)) AND wire_nl0O0OOiO_w_lg_dataout49669w(0)) AND wire_nl0O0OOil_w_lg_dataout49671w(0)) AND wire_nl0O0OOii_w_lg_dataout49673w(0)) AND wire_nl0O0OO0O_w_lg_dataout49675w(0)) AND wire_nl0O0OO0l_w_lg_dataout49677w(0)) AND wire_nl0O0OO0i_w_lg_dataout49679w(0)) AND wire_nl0O0OO1O_w_lg_dataout49681w(0)) AND wire_nl0O0OO1l_w_lg_dataout49683w(0)) AND wire_nl0O0OO1i_w_lg_dataout49685w(0)) AND wire_nl0O0OlOO_w_lg_dataout49687w(0)) AND wire_nl0O0OlOl_w_lg_dataout49689w(0)) AND wire_nl0O0OlOi_w_lg_dataout49691w(0)) AND wire_nl0O0OllO_w_lg_dataout49693w(0)) AND wire_nl0O0Olll_w_lg_dataout49695w(0)) AND wire_nl0O0Olli_w_lg_dataout49697w(0)) AND wire_nl0O0OliO_w_lg_dataout49699w(0)) AND wire_nl0O0Olil_w_lg_dataout49701w(0)) AND wire_nl0O0Olii_w_lg_dataout49703w(0)) AND wire_nl0O0Ol0O_w_lg_dataout49705w(0)); + niOiiiO0O <= (k_bar(163) AND wire_nl0O0OliO_dataout); + niOiiiO1i <= (k_bar(167) AND wire_nilOiO0O_dataout); + niOiiiO1l <= (k_bar(166) AND wire_nilOiO0l_dataout); + niOiiiO1O <= (k_bar(165) AND wire_nilOiO0i_dataout); + niOiiiOii <= (k_bar(162) AND wire_nl0O0Olil_dataout); + niOiiiOil <= (k_bar(161) AND wire_nl0O0Olii_dataout); + niOiiiOiO <= (k_bar(160) AND wire_nl0O0Ol0O_dataout); + niOiiiOli <= (nl0iOilOl AND niOili01O); + niOiiiOll <= (niOiiiOlO OR wire_niO01Oil_dataout); + niOiiiOlO <= (((((((((((((((((((((((((((((((wire_w_lg_w_k_bar_range47787w47788w(0) AND (NOT k_bar(161))) AND (NOT k_bar(162))) AND (NOT k_bar(163))) AND (NOT k_bar(164))) AND (NOT k_bar(165))) AND (NOT k_bar(166))) AND (NOT k_bar(167))) AND (NOT k_bar(168))) AND (NOT k_bar(169))) AND (NOT k_bar(170))) AND (NOT k_bar(171))) AND (NOT k_bar(172))) AND (NOT k_bar(173))) AND (NOT k_bar(174))) AND (NOT k_bar(175))) AND (NOT k_bar(176))) AND (NOT k_bar(177))) AND (NOT k_bar(178))) AND (NOT k_bar(179))) AND (NOT k_bar(180))) AND (NOT k_bar(181))) AND (NOT k_bar(182))) AND (NOT k_bar(183))) AND (NOT k_bar(184))) AND (NOT k_bar(185))) AND (NOT k_bar(186))) AND (NOT k_bar(187))) AND (NOT k_bar(188))) AND (NOT k_bar(189))) AND (NOT k_bar(190))) AND (NOT k_bar(191))); + niOiiiOOi <= (nl0iOilOi AND niOili01O); + niOiiiOOl <= (niOiiiOOO OR wire_niO01Oil_dataout); + niOiiiOOO <= (((((((((((((((((((((((((((((((wire_w_lg_w_k_bar_range45915w45916w(0) AND wire_w_lg_w_k_bar_range45913w45914w(0)) AND (NOT k_bar(130))) AND (NOT k_bar(131))) AND (NOT k_bar(132))) AND (NOT k_bar(133))) AND (NOT k_bar(134))) AND (NOT k_bar(135))) AND (NOT k_bar(136))) AND (NOT k_bar(137))) AND (NOT k_bar(138))) AND (NOT k_bar(139))) AND (NOT k_bar(140))) AND (NOT k_bar(141))) AND (NOT k_bar(142))) AND (NOT k_bar(143))) AND (NOT k_bar(144))) AND (NOT k_bar(145))) AND (NOT k_bar(146))) AND (NOT k_bar(147))) AND (NOT k_bar(148))) AND (NOT k_bar(149))) AND (NOT k_bar(150))) AND (NOT k_bar(151))) AND (NOT k_bar(152))) AND (NOT k_bar(153))) AND (NOT k_bar(154))) AND (NOT k_bar(155))) AND (NOT k_bar(156))) AND (NOT k_bar(157))) AND (NOT k_bar(158))) AND (NOT k_bar(159))); + niOiil00i <= (nl0iOil1i AND niOiil00l); + niOiil00l <= (nl0iOilll AND niOiil01l); + niOiil00O <= (niOili01O AND ((nl0iOiO1l AND niOili1OO) OR wire_nlill0Oll_w_lg_nl0iOiO0i46164w(0))); + niOiil01i <= (nl0iOil1O AND niOiil00l); + niOiil01l <= (niOili01O AND wire_w_lg_niOili1OO45976w(0)); + niOiil01O <= (nl0iOil1l AND niOiil00l); + niOiil0ii <= (niOiil0il OR wire_niO01Oil_dataout); + niOiil0il <= ((((((((((((((((((((((((((((((((NOT k_bar(192)) AND (NOT k_bar(193))) AND (NOT k_bar(194))) AND (NOT k_bar(195))) AND (NOT k_bar(196))) AND (NOT k_bar(197))) AND (NOT k_bar(198))) AND (NOT k_bar(199))) AND (NOT k_bar(200))) AND (NOT k_bar(201))) AND (NOT k_bar(202))) AND (NOT k_bar(203))) AND (NOT k_bar(204))) AND (NOT k_bar(205))) AND (NOT k_bar(206))) AND (NOT k_bar(207))) AND (NOT k_bar(208))) AND (NOT k_bar(209))) AND (NOT k_bar(210))) AND (NOT k_bar(211))) AND (NOT k_bar(212))) AND (NOT k_bar(213))) AND (NOT k_bar(214))) AND (NOT k_bar(215))) AND (NOT k_bar(216))) AND (NOT k_bar(217))) AND (NOT k_bar(218))) AND (NOT k_bar(219))) AND (NOT k_bar(220))) AND (NOT k_bar(221))) AND (NOT k_bar(222))) AND (NOT k_bar(223))); + niOiil0iO <= (niOiil0ll OR niOiil0li); + niOiil0li <= (nli11illO AND wire_nlill0Oll_w_lg_nli11illl44167w(0)); + niOiil0ll <= (nli11illO AND nli11illl); + niOiil0lO <= (((niOiili1i OR niOiil0OO) OR niOiil0Ol) OR niOiil0Oi); + niOiil0Oi <= wire_w_lg_w_k_conf_range46286w48200w(0); + niOiil0Ol <= wire_w_lg_w_k_conf_range46288w48197w(0); + niOiil0OO <= (wire_nl0l1lO1O_dataout AND wire_nl0l1lO1l_dataout); + niOiil10i <= (wire_w_lg_w_k_bar_range48494w48609w(0) OR (k_bar(226) AND k_bar(227))); + niOiil10l <= (((((((((((((((((((((((((((((((wire_nlill0Oll_w_lg_nl0Ol01Ol46011w(0) AND wire_nlill0Oll_w_lg_nl0Ol01Oi46012w(0)) AND wire_nlill0Oll_w_lg_nl0Ol01lO46013w(0)) AND wire_nlill0Oll_w_lg_nl0Ol01ll46014w(0)) AND wire_nlill0Oll_w_lg_nl0Ol01li46015w(0)) AND wire_nlill0Oll_w_lg_nl0Ol01iO46016w(0)) AND wire_nlill0Oll_w_lg_nl0Ol01il46017w(0)) AND wire_nlill0Oll_w_lg_nl0Ol01ii46018w(0)) AND wire_nlill0Oll_w_lg_nl0Ol010O46019w(0)) AND wire_nlill0Oll_w_lg_nl0Ol010l46020w(0)) AND wire_nlill0Oll_w_lg_nl0Ol010i46021w(0)) AND wire_nlill0Oll_w_lg_nl0Ol011O46022w(0)) AND wire_nlill0Oll_w_lg_nl0Ol011l46023w(0)) AND wire_nlill0Oll_w_lg_nl0Ol011i46024w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1OOO46025w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1OOl46026w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1OOi46027w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1OlO46028w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1Oll46029w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1Oli46030w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1OiO46031w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1Oil46032w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1Oii46033w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1O0O46034w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1O0l46035w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1O0i46036w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1O1O46037w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1O1l46038w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1O1i46039w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1lOO46040w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1lOl46041w(0)) AND wire_nlill0Oll_w_lg_nl0Ol1lOi46042w(0)); + niOiil10O <= (((((((((((((((((((((((((((((((wire_nlill0Oll_w_lg_nl0Ol0lOi45978w(0) AND wire_nlill0Oll_w_lg_nl0Ol0llO45979w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0lll45980w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0lli45981w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0liO45982w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0lil45983w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0lii45984w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0l0O45985w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0l0l45986w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0l0i45987w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0l1O45988w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0l1l45989w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0l1i45990w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0iOO45991w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0iOl45992w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0iOi45993w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0ilO45994w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0ill45995w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0ili45996w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0iiO45997w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0iil45998w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0iii45999w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0i0O46000w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0i0l46001w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0i0i46002w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0i1O46003w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0i1l46004w(0)) AND wire_nlill0Oll_w_lg_nl0Ol0i1i46005w(0)) AND wire_nlill0Oll_w_lg_nl0Ol00OO46006w(0)) AND wire_nlill0Oll_w_lg_nl0Ol00Ol46007w(0)) AND wire_nlill0Oll_w_lg_nl0Ol00Oi46008w(0)) AND wire_nlill0Oll_w_lg_nl0Ol00lO46009w(0)); + niOiil11i <= (nl0iOil0i AND (nl0iOillO AND niOili01O)); + niOiil11l <= (k_conf(306) AND niOiiO0iO); + niOiil11O <= (nl0iOil1O AND (nl0iOiO0l AND niOiil01l)); + niOiil1ii <= (nl0iOiO1i AND niOiil1iO); + niOiil1il <= (nl0iOilOO AND niOiil1iO); + niOiil1iO <= (niOili01O AND wire_w_lg_w_k_bar_range45930w48491w(0)); + niOiil1li <= (nl0iOilOl AND (niOili01O AND wire_w_lg_w_k_bar_range48494w48495w(0))); + niOiil1ll <= (nl0iOilOi AND niOili01O); + niOiil1lO <= (nl0iOil1l AND niOiil1OO); + niOiil1Oi <= (nl0iOiO1l AND (niOili01O AND wire_w_lg_w_k_bar_range45818w48487w(0))); + niOiil1Ol <= (nl0iOil1i AND niOiil1OO); + niOiil1OO <= (nl0iOillO AND (niOili01O AND wire_w_lg_w_k_bar_range48482w48483w(0))); + niOiili0i <= (nl0iOl11O AND nl0iOiiOO); + niOiili0l <= (nl0iOil1l AND niOiili0i); + niOiili0O <= (((((((((((nli10Oili AND nli10011i) OR wire_nlill0Oll_w_lg_nli1i01li48116w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48119w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48122w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48125w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48128w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48131w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48134w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48139w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48144w(0)) OR wire_nlill0Oll_w_lg_nli1i01li48147w(0)); + niOiili1i <= (wire_nl0l1lO1O_w_lg_dataout48195w(0) AND wire_nl0l1lO1l_w_lg_dataout48198w(0)); + niOiili1l <= (nl0iOil1i AND niOiili0i); + niOiili1O <= (wire_nliiOiilO_w_lg_nli11l1lO48215w(0) AND niOOllOO); + niOiiliii <= (k_gbl_hip(34) AND niOiilO1i); + niOiiliil <= (nl0iOil1i AND niOiiliiO); + niOiiliiO <= (nl0iOil1l AND niOiilill); + niOiilili <= (nl0iOil1i AND niOiilill); + niOiilill <= (nl0iOiO1l AND niOili01l); + niOiililO <= (nl0iOil1i AND (nl0iOilOO AND (niOili01l AND ((niOiilOll OR niOiilOiO) OR niOiilO1O)))); + niOiiliOi <= ((((NOT k_conf(208)) AND (NOT k_conf(209))) AND (NOT k_conf(210))) AND (NOT k_conf(211))); + niOiiliOl <= (niOiill0O AND (wire_nlill0Oll_w_lg_nli101ilO48090w(0) OR wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48091w(0))); + niOiiliOO <= (niOiill0O AND (wire_nlill0Oll_w_lg_nli101lOl48084w(0) OR (wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48085w(0) AND wire_nlill0Oll_w_lg_nli11OOOO48086w(0)))); + niOiill0i <= (wire_nlill0Oll_w_lg_nli10011i48069w(0) AND niOiilO1O); + niOiill0l <= (wire_w_lg_niOiill0O48070w(0) AND wire_w_lg_niOO10OOi46502w(0)); + niOiill0O <= (nl0l010iO AND niOiilO1O); + niOiill1i <= (niOiill0O AND (wire_nlill0Oll_w_lg_nli10011i48078w(0) OR (wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48079w(0) AND wire_nlill0Oll_w_lg_nli101ilO48080w(0)))); + niOiill1l <= (wire_nl0l1O11O_dataout AND (nl0iOil0i AND (nl0iOilOi AND (niOili01l AND niOiilO1O)))); + niOiill1O <= (niOiill0i AND niOO10OOi); + niOiillii <= (nl0iOil1i AND (nl0iOillO AND (niOili01l AND niOiilO1O))); + niOiillil <= (wire_nl0illl1O_dataout AND nl0l0i0il); + niOiilliO <= (nl0iOil1O AND niOiilllO); + niOiillli <= (nl0iOil1l AND niOiilllO); + niOiillll <= (nl0iOil1i AND niOiilllO); + niOiilllO <= (nl0iOilll AND niOili01l); + niOiillOi <= (nl0iOil1l AND niOiillOl); + niOiillOl <= (nl0iOiliO AND niOili01l); + niOiillOO <= (nl0iOil1i AND niOiillOl); + niOiilO0i <= (nl0iOil1O AND niOiilO0O); + niOiilO0l <= (nl0iOil1l AND niOiilO0O); + niOiilO0O <= (nl0iOilii AND niOili01l); + niOiilO1i <= (wire_nli1l1ilO_w_lg_w_lg_w_lg_dataout46325w48154w48155w(0) AND wire_nli1l1iiO_w_lg_dataout46328w(0)); + niOiilO1l <= ((wire_nli1l1ilO_w_lg_w_lg_dataout46325w48154w(0) AND wire_nli1l1ili_w_lg_dataout46327w(0)) AND wire_nli1l1iiO_dataout); + niOiilO1O <= (wire_nilO010O_w_lg_dataout8973w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOiilOii <= (nl0iOil1i AND niOiilO0O); + niOiilOil <= (nl0l010Oi AND niOiilOlO); + niOiilOiO <= wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0); + niOiilOli <= (niOiilOll OR wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0)); + niOiilOll <= wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0); + niOiilOlO <= (niOiilOli OR niOiilOiO); + niOiilOOi <= ((((NOT k_conf(361)) AND (NOT k_conf(362))) AND (NOT k_conf(363))) AND (NOT k_conf(364))); + niOiilOOl <= (nl0iOil1i AND (nl0iOilli AND (nl0iOiiOl AND nl0iOiill))); + niOiilOOO <= (wire_nilO010O_w_lg_dataout8973w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOiiO00i <= ((((wire_nilOl1OO_w49173w(0) AND wire_nilOl11O_w_lg_dataout49178w(0)) AND wire_nilOl11l_w_lg_dataout49175w(0)) AND wire_nilOl11i_w_lg_dataout49181w(0)) AND wire_nilOiOOO_w_lg_dataout49183w(0)); + niOiiO00l <= (((((wire_nilOiOOl_w_lg_dataout49185w(0) AND wire_nilOiOOi_w_lg_dataout49186w(0)) AND wire_nilOiOlO_w_lg_dataout49188w(0)) AND wire_nilOiOll_w_lg_dataout49190w(0)) AND wire_nilOiOli_w_lg_dataout49192w(0)) AND wire_nilOiOiO_w_lg_dataout49194w(0)); + niOiiO00O <= (((wire_w_lg_w_k_bar_range48482w48878w(0) OR (k_bar(224) AND k_bar(225))) AND wire_nl0Ol1ill_o) AND wire_nl0Ol1iiO_o); + niOiiO01i <= ((((((((NOT (wire_nilOl1il_dataout XOR nl0OOO01l)) AND (NOT (wire_nilOl1iO_dataout XOR nl0OOO01O))) AND (NOT (wire_nilOl1li_dataout XOR nl0OOO00i))) AND (NOT (wire_nilOl1ll_dataout XOR nl0OOO00l))) AND (NOT (wire_nilOl1lO_dataout XOR nl0OOO00O))) AND (NOT (wire_nilOl1Oi_dataout XOR nl0OOO0ii))) AND (NOT (wire_nilOl1Ol_dataout XOR nl0OOO0il))) AND (NOT (wire_nilOl1OO_dataout XOR nl0OOO0iO))); + niOiiO01l <= ((((((((NOT (wire_nilOl1il_dataout XOR nl0OOO1iO)) AND (NOT (wire_nilOl1iO_dataout XOR nl0OOO1li))) AND (NOT (wire_nilOl1li_dataout XOR nl0OOO1ll))) AND (NOT (wire_nilOl1ll_dataout XOR nl0OOO1lO))) AND (NOT (wire_nilOl1lO_dataout XOR nl0OOO1Oi))) AND (NOT (wire_nilOl1Oi_dataout XOR nl0OOO1Ol))) AND (NOT (wire_nilOl1Ol_dataout XOR nl0OOO1OO))) AND (NOT (wire_nilOl1OO_dataout XOR nl0OOO01i))); + niOiiO01O <= (nl01l0llO OR (nl01l0lOi OR nl01l0liO)); + niOiiO0ii <= (wire_nl0Ol1lll_o AND wire_nl0Ol1lli_o); + niOiiO0il <= (wire_nlill0Oll_w_lg_nl0Ol1llO48605w(0) AND wire_nl0Ol1l0l_w_lg_o48607w(0)); + niOiiO0iO <= wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0); + niOiiO0li <= ((wire_nilOl1OO_w_lg_w49173w49174w(0) AND wire_nilOl11l_w_lg_dataout49175w(0)) AND wire_nilOl11i_dataout); + niOiiO0ll <= wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0); + niOiiO0lO <= (niOiiO0ii OR niOiiO0il); + niOiiO0Oi <= ((niOiil10i AND wire_nl0Ol1l1i_o) AND wire_nl0Ol1iOl_o); + niOiiO0Ol <= (niOiiO0iO OR niOiiO0ll); + niOiiO0OO <= (nl01l0O1l OR nl01l0O1i); + niOiiO10i <= (nl01l0lOl AND wire_nli0O1OOl_dataout); + niOiiO10l <= wire_nlill0Oll_w_lg_nl01l0O1l47777w(0); + niOiiO10O <= wire_w_lg_w_lg_w_k_bar_range45803w45804w50527w(0); + niOiiO11i <= (nl0iOil1i AND (nl0iOilil AND (nl0iOiiOl AND nl0iOiill))); + niOiiO11l <= ((NOT (((NOT k_conf(113)) AND (NOT k_conf(114))) AND (NOT k_conf(115)))) AND (NOT (((NOT k_conf(117)) AND (NOT k_conf(118))) AND (NOT k_conf(119))))); + niOiiO11O <= (wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0) OR (wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_w_lg_dataout25163w(0))); + niOiiO1ii <= ((((((((((((((((((((((((((((NOT (niOil1l0O XOR niOiii00O)) AND (NOT (niOil1lii XOR niOiii00l))) AND (NOT (niOil1lil XOR niOiii00i))) AND (NOT (niOil1liO XOR niOiii01O))) AND (NOT (niOil1lli XOR niOiii01l))) AND (NOT (niOil1lll XOR niOiii01i))) AND (NOT (niOil1llO XOR niOiii1OO))) AND (NOT (niOil1lOi XOR niOiii1Ol))) AND (NOT (niOil1lOl XOR niOiii1Oi))) AND (NOT (niOil1lOO XOR niOiii1lO))) AND (NOT (niOil1O1i XOR niOiii1ll))) AND (NOT (niOil1O1l XOR niOiii1li))) AND (NOT (niOil1O1O XOR niOiii1iO))) AND (NOT (niOil1O0i XOR niOiii1il))) AND (NOT (niOil1O0l XOR niOiii1ii))) AND (NOT (niOil1O0O XOR niOiii10O))) AND (NOT (niOil1Oii XOR niOiii10l))) AND (NOT (niOil1Oil XOR niOiii10i))) AND (NOT (niOil1OiO XOR niOiii11O))) AND wire_w_lg_w_lg_niOil1Oli50758w50759w(0)) AND (NOT (niOil1Oll XOR niOiii11i))) AND (NOT (niOil1OlO XOR niOii0OOO))) AND (NOT (niOil1OOi XOR niOii0OOl))) AND (NOT (niOil1OOl XOR niOii0OOi))) AND (NOT (niOil1OOO XOR niOii0OlO))) AND (NOT (niOil011i XOR niOii0Oll))) AND (NOT (niOil011l XOR niOii0Oli))) AND (NOT (niOil011O XOR niOii0OiO))); + niOiiO1il <= (nl01l0lOl AND wire_nli0O1OOl_dataout); + niOiiO1iO <= wire_nlill0Oll_w_lg_nl01l0O1l47777w(0); + niOiiO1li <= wire_w_lg_w_lg_w_k_bar_range45913w45914w49643w(0); + niOiiO1ll <= ((((((((((((((((((((((((((((NOT (niOiiOOil XOR niOiiiO0i)) AND (NOT (niOiiOOiO XOR niOiiiO1O))) AND (NOT (niOiiOOli XOR niOiiiO1l))) AND (NOT (niOiiOOll XOR niOiiiO1i))) AND (NOT (niOiiOOlO XOR niOiiilOO))) AND (NOT (niOiiOOOi XOR niOiiilOl))) AND (NOT (niOiiOOOl XOR niOiiilOi))) AND (NOT (niOiiOOOO XOR niOiiillO))) AND (NOT (niOil111i XOR niOiiilll))) AND (NOT (niOil111l XOR niOiiilli))) AND (NOT (niOil111O XOR niOiiiliO))) AND (NOT (niOil110i XOR niOiiilil))) AND (NOT (niOil110l XOR niOiiilii))) AND (NOT (niOil110O XOR niOiiil0O))) AND (NOT (niOil11ii XOR niOiiil0l))) AND (NOT (niOil11il XOR niOiiil0i))) AND (NOT (niOil11iO XOR niOiiil1O))) AND (NOT (niOil11li XOR niOiiil1l))) AND (NOT (niOil11ll XOR niOiiil1i))) AND wire_w_lg_w_lg_niOil11lO49874w49875w(0)) AND (NOT (niOil11Oi XOR niOiiiiOl))) AND (NOT (niOil11Ol XOR niOiiiiOi))) AND (NOT (niOil11OO XOR niOiiiilO))) AND (NOT (niOil101i XOR niOiiiill))) AND (NOT (niOil101l XOR niOiiiili))) AND (NOT (niOil101O XOR niOiiiiiO))) AND (NOT (niOil100i XOR niOiiiiil))) AND (NOT (niOil100l XOR niOiiiiii))); + niOiiO1lO <= (((((((((((((((((((((NOT (niOiiOiOl XOR (k_bar(203) AND wire_nilOiOli_dataout))) AND (NOT (niOiiOiOO XOR (k_bar(204) AND wire_nilOiOll_dataout)))) AND (NOT (niOiiOl1i XOR (k_bar(205) AND wire_nilOiOlO_dataout)))) AND (NOT (niOiiOl1l XOR (k_bar(206) AND wire_nilOiOOi_dataout)))) AND (NOT (niOiiOl1O XOR (k_bar(207) AND wire_nilOiOOl_dataout)))) AND (NOT (niOiiOl0i XOR (k_bar(208) AND wire_nilOiOOO_dataout)))) AND (NOT (niOiiOl0l XOR (k_bar(209) AND wire_nilOl11i_dataout)))) AND (NOT (niOiiOl0O XOR (k_bar(210) AND wire_nilOl11l_dataout)))) AND (NOT (niOiiOlii XOR (k_bar(211) AND wire_nilOl11O_dataout)))) AND (NOT (niOiiOlil XOR (k_bar(212) AND wire_nilOl10i_dataout)))) AND (NOT (niOiiOliO XOR (k_bar(213) AND wire_nilOl10l_dataout)))) AND (NOT (niOiiOlli XOR (k_bar(214) AND wire_nilOl10O_dataout)))) AND (NOT (niOiiOlll XOR (k_bar(215) AND wire_nilOl1ii_dataout)))) AND (NOT (niOiiOllO XOR (k_bar(216) AND wire_nilOl1il_dataout)))) AND (NOT (niOiiOlOi XOR (k_bar(217) AND wire_nilOl1iO_dataout)))) AND (NOT (niOiiOlOl XOR (k_bar(218) AND wire_nilOl1li_dataout)))) AND (NOT (niOiiOlOO XOR (k_bar(219) AND wire_nilOl1ll_dataout)))) AND (NOT (niOiiOO1i XOR (k_bar(220) AND wire_nilOl1lO_dataout)))) AND (NOT (niOiiOO1l XOR (k_bar(221) AND wire_nilOl1Oi_dataout)))) AND (NOT (niOiiOO1O XOR (k_bar(222) AND wire_nilOl1Ol_dataout)))) AND (NOT (niOiiOO0i XOR (k_bar(223) AND wire_nilOl1OO_dataout)))); + niOiiO1Oi <= (((wire_nl0ll0lli_o AND niOii000l) AND wire_w_lg_w_k_bar_range51117w51286w(0)) AND (wire_w_lg_w_lg_w_k_bar_range51119w51288w51289w(0) OR wire_w_lg_w_k_bar_range51119w51290w(0))); + niOiiO1Ol <= (wire_nli0O011i_dataout OR (wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0) OR wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0))); + niOiiO1OO <= (wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w43350w(0) OR (wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) AND wire_nilO010i_w_lg_dataout25163w(0))); + niOiiOi0i <= wire_w_lg_w_k_conf_range48004w48005w(0); + niOiiOi0l <= wire_w_lg_w_k_conf_range48006w48007w(0); + niOiiOi0O <= wire_w_lg_w_k_conf_range48012w48013w(0); + niOiiOi1i <= wire_w_lg_w_k_conf_range47998w47999w(0); + niOiiOi1l <= wire_w_lg_w_k_conf_range48000w48001w(0); + niOiiOi1O <= wire_w_lg_w_k_conf_range48002w48003w(0); + niOiiOiii <= (wire_nilO011O_dataout AND wire_w_lg_niOiilOlO47917w(0)); + niOiiOiil <= wire_w_lg_w_k_conf_range1869w46275w(0); + niOiiOiiO <= wire_w_lg_w_lg_w_k_conf_range1869w46186w46226w(0); + niOiiOili <= (k_conf(222) AND nl0iOiOll); + niOiiOill <= (nl0iOiO0l AND niOili1OO); + niOiiOilO <= wire_nlill0Oll_w_lg_nl0iOiO0i46164w(0); + niOiiOiOi <= (k_bar(223) AND nli111i1l); + niOiiOiOl <= (k_bar(203) AND nli11010i); + niOiiOiOO <= (k_bar(204) AND nli11010l); + niOiiOl0i <= (k_bar(208) AND nli1101iO); + niOiiOl0l <= (k_bar(209) AND nli1101li); + niOiiOl0O <= (k_bar(210) AND nli1101ll); + niOiiOl1i <= (k_bar(205) AND nli11010O); + niOiiOl1l <= (k_bar(206) AND nli1101ii); + niOiiOl1O <= (k_bar(207) AND nli1101il); + niOiiOlii <= (k_bar(211) AND nli1101lO); + niOiiOlil <= (k_bar(212) AND nli1101Oi); + niOiiOliO <= (k_bar(213) AND nli1101Ol); + niOiiOlli <= (k_bar(214) AND nli1101OO); + niOiiOlll <= (k_bar(215) AND nli11001i); + niOiiOllO <= (k_bar(216) AND nli11001l); + niOiiOlOi <= (k_bar(217) AND nli11001O); + niOiiOlOl <= (k_bar(218) AND nli11000i); + niOiiOlOO <= (k_bar(219) AND nli11000l); + niOiiOO0i <= (k_bar(223) AND nli1100iO); + niOiiOO0l <= (nl0iOiO1l AND niOili1OO); + niOiiOO0O <= (nl0iOiO1i AND niOili1OO); + niOiiOO1i <= (k_bar(220) AND nli11000O); + niOiiOO1l <= (k_bar(221) AND nli1100ii); + niOiiOO1O <= (k_bar(222) AND nli1100il); + niOiiOOii <= (nl0iOilOO AND wire_w_lg_niOili1OO45976w(0)); + niOiiOOil <= (k_bar(164) AND wire_nl0O0Olli_dataout); + niOiiOOiO <= (k_bar(165) AND wire_nl0O0Olll_dataout); + niOiiOOli <= (k_bar(166) AND wire_nl0O0OllO_dataout); + niOiiOOll <= (k_bar(167) AND wire_nl0O0OlOi_dataout); + niOiiOOlO <= (k_bar(168) AND wire_nl0O0OlOl_dataout); + niOiiOOOi <= (k_bar(169) AND wire_nl0O0OlOO_dataout); + niOiiOOOl <= (k_bar(170) AND wire_nl0O0OO1i_dataout); + niOiiOOOO <= (k_bar(171) AND wire_nl0O0OO1l_dataout); + niOil000i <= (k_bar(82) AND wire_nl0O10llO_dataout); + niOil000l <= (k_bar(83) AND wire_nl0O10lOi_dataout); + niOil000O <= (k_bar(84) AND wire_nl0O10lOl_dataout); + niOil001i <= (k_bar(79) AND wire_nl0O10liO_dataout); + niOil001l <= (k_bar(80) AND wire_nl0O10lli_dataout); + niOil001O <= (k_bar(81) AND wire_nl0O10lll_dataout); + niOil00ii <= (k_bar(85) AND wire_nl0O10lOO_dataout); + niOil00il <= (k_bar(86) AND wire_nl0O10O1i_dataout); + niOil00iO <= (k_bar(87) AND wire_nl0O10O1l_dataout); + niOil00li <= (k_bar(88) AND wire_nl0O10O1O_dataout); + niOil00ll <= (k_bar(89) AND wire_nl0O10O0i_dataout); + niOil00lO <= (k_bar(90) AND wire_nl0O10O0l_dataout); + niOil00Oi <= (k_bar(91) AND wire_nl0O10O0O_dataout); + niOil00Ol <= (k_bar(92) AND wire_nl0O10Oii_dataout); + niOil00OO <= (k_bar(93) AND wire_nl0O10Oil_dataout); + niOil010i <= (nl0iOillO AND niOili1OO); + niOil010l <= (k_bar(68) AND wire_nl0O10iOi_dataout); + niOil010O <= (k_bar(69) AND wire_nl0O10iOl_dataout); + niOil011i <= (k_bar(125) AND wire_nl0O10ili_dataout); + niOil011l <= (k_bar(126) AND wire_nl0O10ill_dataout); + niOil011O <= (k_bar(127) AND wire_nl0O10ilO_dataout); + niOil01ii <= (k_bar(70) AND wire_nl0O10iOO_dataout); + niOil01il <= (k_bar(71) AND wire_nl0O10l1i_dataout); + niOil01iO <= (k_bar(72) AND wire_nl0O10l1l_dataout); + niOil01li <= (k_bar(73) AND wire_nl0O10l1O_dataout); + niOil01ll <= (k_bar(74) AND wire_nl0O10l0i_dataout); + niOil01lO <= (k_bar(75) AND wire_nl0O10l0l_dataout); + niOil01Oi <= (k_bar(76) AND wire_nl0O10l0O_dataout); + niOil01Ol <= (k_bar(77) AND wire_nl0O10lii_dataout); + niOil01OO <= (k_bar(78) AND wire_nl0O10lil_dataout); + niOil0i0i <= (k_bar(36) AND nl0llli0i); + niOil0i0l <= (k_bar(37) AND nl0llli0l); + niOil0i0O <= (k_bar(38) AND nl0llli0O); + niOil0i1i <= (k_bar(94) AND wire_nl0O10OiO_dataout); + niOil0i1l <= (k_bar(95) AND wire_nl0O10Oli_dataout); + niOil0i1O <= (nl0iOilll AND niOili1OO); + niOil0iii <= (k_bar(39) AND nl0llliii); + niOil0iil <= (k_bar(40) AND nl0llliil); + niOil0iiO <= (k_bar(41) AND nl0llliiO); + niOil0ili <= (k_bar(42) AND nl0lllili); + niOil0ill <= (k_bar(43) AND nl0lllill); + niOil0ilO <= (k_bar(44) AND nl0lllilO); + niOil0iOi <= (k_bar(45) AND nl0llliOi); + niOil0iOl <= (k_bar(46) AND nl0llliOl); + niOil0iOO <= (k_bar(47) AND nl0llliOO); + niOil0l0i <= (k_bar(51) AND nl0llll0i); + niOil0l0l <= (k_bar(52) AND nl0llll0l); + niOil0l0O <= (k_bar(53) AND nl0llll0O); + niOil0l1i <= (k_bar(48) AND nl0llll1i); + niOil0l1l <= (k_bar(49) AND nl0llll1l); + niOil0l1O <= (k_bar(50) AND nl0llll1O); + niOil0lii <= (k_bar(54) AND nl0llllii); + niOil0lil <= (k_bar(55) AND nl0llllil); + niOil0liO <= (k_bar(56) AND nl0lllliO); + niOil0lli <= (k_bar(57) AND nl0llllli); + niOil0lll <= (k_bar(58) AND nl0llllll); + niOil0llO <= (k_bar(59) AND nl0lllllO); + niOil0lOi <= (k_bar(60) AND nl0llllOi); + niOil0lOl <= (k_bar(61) AND nl0llllOl); + niOil0lOO <= (k_bar(62) AND nl0llllOO); + niOil0O0i <= (k_bar(6) AND nl0lllO0i); + niOil0O0l <= (k_bar(7) AND nl0lllO0l); + niOil0O0O <= (k_bar(8) AND nl0lllO0O); + niOil0O1i <= (k_bar(63) AND nl0lllO1i); + niOil0O1l <= (k_bar(4) AND nl0lllO1l); + niOil0O1O <= (k_bar(5) AND nl0lllO1O); + niOil0Oii <= (k_bar(9) AND nl0lllOii); + niOil0Oil <= (k_bar(10) AND nl0lllOil); + niOil0OiO <= (k_bar(11) AND nl0lllOiO); + niOil0Oli <= (k_bar(12) AND nl0lllOli); + niOil0Oll <= (k_bar(13) AND nl0lllOll); + niOil0OlO <= (k_bar(14) AND nl0lllOlO); + niOil0OOi <= (k_bar(15) AND nl0lllOOi); + niOil0OOl <= (k_bar(16) AND nl0lllOOl); + niOil0OOO <= (k_bar(17) AND nl0lllOOO); + niOil100i <= (k_bar(190) AND wire_nl0Oi110O_dataout); + niOil100l <= (k_bar(191) AND wire_nl0Oi11ii_dataout); + niOil100O <= (nl0iOilOl AND niOili1OO); + niOil101i <= (k_bar(187) AND wire_nl0Oi111O_dataout); + niOil101l <= (k_bar(188) AND wire_nl0Oi110i_dataout); + niOil101O <= (k_bar(189) AND wire_nl0Oi110l_dataout); + niOil10ii <= (k_bar(132) AND wire_nl0Oi11il_dataout); + niOil10il <= (k_bar(133) AND wire_nl0Oi11iO_dataout); + niOil10iO <= (k_bar(134) AND wire_nl0Oi11li_dataout); + niOil10li <= (k_bar(135) AND wire_nl0Oi11ll_dataout); + niOil10ll <= (k_bar(136) AND wire_nl0Oi11lO_dataout); + niOil10lO <= (k_bar(137) AND wire_nl0Oi11Oi_dataout); + niOil10Oi <= (k_bar(138) AND wire_nl0Oi11Ol_dataout); + niOil10Ol <= (k_bar(139) AND wire_nl0Oi11OO_dataout); + niOil10OO <= (k_bar(140) AND wire_nl0Oi101i_dataout); + niOil110i <= (k_bar(175) AND wire_nl0O0OO0O_dataout); + niOil110l <= (k_bar(176) AND wire_nl0O0OOii_dataout); + niOil110O <= (k_bar(177) AND wire_nl0O0OOil_dataout); + niOil111i <= (k_bar(172) AND wire_nl0O0OO1O_dataout); + niOil111l <= (k_bar(173) AND wire_nl0O0OO0i_dataout); + niOil111O <= (k_bar(174) AND wire_nl0O0OO0l_dataout); + niOil11ii <= (k_bar(178) AND wire_nl0O0OOiO_dataout); + niOil11il <= (k_bar(179) AND wire_nl0O0OOli_dataout); + niOil11iO <= (k_bar(180) AND wire_nl0O0OOll_dataout); + niOil11li <= (k_bar(181) AND wire_nl0O0OOlO_dataout); + niOil11ll <= (k_bar(182) AND wire_nl0O0OOOi_dataout); + niOil11lO <= (k_bar(183) AND wire_nl0O0OOOl_dataout); + niOil11Oi <= (k_bar(184) AND wire_nl0O0OOOO_dataout); + niOil11Ol <= (k_bar(185) AND wire_nl0Oi111i_dataout); + niOil11OO <= (k_bar(186) AND wire_nl0Oi111l_dataout); + niOil1i0i <= (k_bar(144) AND wire_nl0Oi100l_dataout); + niOil1i0l <= (k_bar(145) AND wire_nl0Oi100O_dataout); + niOil1i0O <= (k_bar(146) AND wire_nl0Oi10ii_dataout); + niOil1i1i <= (k_bar(141) AND wire_nl0Oi101l_dataout); + niOil1i1l <= (k_bar(142) AND wire_nl0Oi101O_dataout); + niOil1i1O <= (k_bar(143) AND wire_nl0Oi100i_dataout); + niOil1iii <= (k_bar(147) AND wire_nl0Oi10il_dataout); + niOil1iil <= (k_bar(148) AND wire_nl0Oi10iO_dataout); + niOil1iiO <= (k_bar(149) AND wire_nl0Oi10li_dataout); + niOil1ili <= (k_bar(150) AND wire_nl0Oi10ll_dataout); + niOil1ill <= (k_bar(151) AND wire_nl0Oi10lO_dataout); + niOil1ilO <= (k_bar(152) AND wire_nl0Oi10Oi_dataout); + niOil1iOi <= (k_bar(153) AND wire_nl0Oi10Ol_dataout); + niOil1iOl <= (k_bar(154) AND wire_nl0Oi10OO_dataout); + niOil1iOO <= (k_bar(155) AND wire_nl0Oi1i1i_dataout); + niOil1l0i <= (k_bar(159) AND wire_nl0Oi1i0l_dataout); + niOil1l0l <= (nl0iOilOi AND niOili1OO); + niOil1l0O <= (k_bar(100) AND wire_nl0O101OO_dataout); + niOil1l1i <= (k_bar(156) AND wire_nl0Oi1i1l_dataout); + niOil1l1l <= (k_bar(157) AND wire_nl0Oi1i1O_dataout); + niOil1l1O <= (k_bar(158) AND wire_nl0Oi1i0i_dataout); + niOil1lii <= (k_bar(101) AND wire_nl0O1001i_dataout); + niOil1lil <= (k_bar(102) AND wire_nl0O1001l_dataout); + niOil1liO <= (k_bar(103) AND wire_nl0O1001O_dataout); + niOil1lli <= (k_bar(104) AND wire_nl0O1000i_dataout); + niOil1lll <= (k_bar(105) AND wire_nl0O1000l_dataout); + niOil1llO <= (k_bar(106) AND wire_nl0O1000O_dataout); + niOil1lOi <= (k_bar(107) AND wire_nl0O100ii_dataout); + niOil1lOl <= (k_bar(108) AND wire_nl0O100il_dataout); + niOil1lOO <= (k_bar(109) AND wire_nl0O100iO_dataout); + niOil1O0i <= (k_bar(113) AND wire_nl0O100Oi_dataout); + niOil1O0l <= (k_bar(114) AND wire_nl0O100Ol_dataout); + niOil1O0O <= (k_bar(115) AND wire_nl0O100OO_dataout); + niOil1O1i <= (k_bar(110) AND wire_nl0O100li_dataout); + niOil1O1l <= (k_bar(111) AND wire_nl0O100ll_dataout); + niOil1O1O <= (k_bar(112) AND wire_nl0O100lO_dataout); + niOil1Oii <= (k_bar(116) AND wire_nl0O10i1i_dataout); + niOil1Oil <= (k_bar(117) AND wire_nl0O10i1l_dataout); + niOil1OiO <= (k_bar(118) AND wire_nl0O10i1O_dataout); + niOil1Oli <= (k_bar(119) AND wire_nl0O10i0i_dataout); + niOil1Oll <= (k_bar(120) AND wire_nl0O10i0l_dataout); + niOil1OlO <= (k_bar(121) AND wire_nl0O10i0O_dataout); + niOil1OOi <= (k_bar(122) AND wire_nl0O10iii_dataout); + niOil1OOl <= (k_bar(123) AND wire_nl0O10iil_dataout); + niOil1OOO <= (k_bar(124) AND wire_nl0O10iiO_dataout); + niOili00i <= ((((((((((((NOT (wire_nilOOiii_dataout AND nliiO0iOO)) AND (NOT (wire_nilOOilO_dataout AND nliiO0iOi))) AND (NOT (nliiO0ilO AND nliiOOill))) AND (NOT (nliiO0ill AND nlii11i0O))) AND (NOT (nl10iO1li AND nliiO0ili))) AND (NOT (nliiO0iiO AND niOO10liO))) AND (NOT (nliiO0iil AND niOO1i0i))) AND (NOT (nliiO0iii AND niOO10lll))) AND (NOT (nliiO0i0O AND niOO10llO))) AND (NOT (nliiO0i0l AND niOO10lOi))) AND (NOT (nliiO0i0i AND niOO10lii))) AND (NOT (nliiO011l AND niOO10lil))); + niOili00l <= (((((((((NOT (wire_nilOOiii_dataout AND wire_nliiO0iOl_w_lg_nliiO0iOO44507w(0))) AND (NOT (wire_nilOOilO_dataout AND wire_nliiO0iOl_w_lg_nliiO0iOi44506w(0)))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0ilO44505w(0) AND nliiOOill))) AND (NOT (nl10iO1li AND wire_nliiO0iOl_w_lg_nliiO0ili44284w(0)))) AND (NOT (wire_nliiOiilO_w_lg_nliiO0iiO44289w(0) AND niOO10liO))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0i0O44504w(0) AND niOO10llO))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0i0l44503w(0) AND niOO10lOi))) AND (NOT (niOilliOl AND wire_w_lg_niOilli0i45236w(0)))) AND (NOT (niOilliOO AND wire_w_lg_niOilli0l45240w(0)))); + niOili00O <= (((((wire_nilOOill_w_lg_dataout45188w(0) AND wire_nilOOili_w_lg_dataout45189w(0)) AND wire_nilOOiiO_w_lg_dataout45191w(0)) AND wire_nilOOiil_w_lg_dataout45193w(0)) AND wire_nilOOi0O_w_lg_dataout45195w(0)) AND wire_w_lg_niOill0Ol45197w(0)); + niOili01i <= (wire_nlill0Oll_w_lg_nli11illO44166w(0) AND wire_nlill0Oll_w_lg_nli11illl44167w(0)); + niOili01l <= (nl0iOiiOO AND nl0iOiili); + niOili01O <= (nl0iOiiOO AND nl0iOiilO); + niOili0ii <= (wire_nli0O011i_dataout AND nl0l0Oill); + niOili0il <= (((nliii0O1i AND nliii100O) OR (nliii0lOO AND nliii01Oi)) OR (nliii000i AND nliii001O)); + niOili0iO <= (nl0OiOl0O AND niOilil1i); + niOili0li <= (nl0OiOl0O AND niOilil0l); + niOili0ll <= (nl0OiOl0O AND nli1iOl1l); + niOili0lO <= (niOilii1O AND niOililii); + niOili0Oi <= (niOiliiil AND niOilii1l); + niOili0Ol <= (((((((((((wire_nilOOilO_w_lg_dataout45501w(0) AND wire_nilOOiii_w_lg_dataout45502w(0)) AND wire_nlill0Oll_w_lg_nl10iO1li45504w(0)) AND wire_nlill0Oll_w_lg_nlii11i0O45506w(0)) AND wire_w_lg_niOO10lii45508w(0)) AND wire_w_lg_niOO10lil45510w(0)) AND wire_w_lg_niOO10llO45512w(0)) AND wire_w_lg_niOO10lOi45514w(0)) AND wire_w_lg_niOO10liO45516w(0)) AND wire_w_lg_niOO10lll45518w(0)) AND wire_nlill0Oll_w_lg_nliiOOill45520w(0)) AND wire_nl1000i_w_lg_niOO1i0i45522w(0)); + niOili0OO <= (nl0l010il OR nl0l010ii); + niOili10i <= (k_bar(21) AND nl0llO10i); + niOili10l <= (k_bar(22) AND nl0llO10l); + niOili10O <= (k_bar(23) AND nl0llO10O); + niOili11i <= (k_bar(18) AND nl0llO11i); + niOili11l <= (k_bar(19) AND nl0llO11l); + niOili11O <= (k_bar(20) AND nl0llO11O); + niOili1ii <= (k_bar(24) AND nl0llO1ii); + niOili1il <= (k_bar(25) AND nl0llO1il); + niOili1iO <= (k_bar(26) AND nl0llO1iO); + niOili1li <= (k_bar(27) AND nl0llO1li); + niOili1ll <= (k_bar(28) AND nl0llO1ll); + niOili1lO <= (k_bar(29) AND nl0llO1lO); + niOili1Oi <= (k_bar(30) AND nl0llO1Oi); + niOili1Ol <= (k_bar(31) AND nl0llO1Ol); + niOili1OO <= wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0); + niOilii0i <= (niOiliiil AND niOilii1O); + niOilii0l <= (niOilii1l AND niOililii); + niOilii0O <= (niOillliO OR niOilllil); + niOilii1i <= (niOilllOO OR niOililii); + niOilii1l <= (((((((((((((NOT (nl11lOl0O XOR wire_nl0iO0l0i_dataout)) AND (NOT (nl11lOlii XOR wire_nl0iO0l0l_dataout))) AND (NOT (nl11lOlil XOR wire_nl0iO0l0O_dataout))) AND (NOT (nl11lOliO XOR wire_nl0iO0lii_dataout))) AND (NOT (nl11lOlli XOR wire_nl0iO0lil_dataout))) AND (NOT (nl11lOlll XOR wire_nl0iO0liO_dataout))) AND (NOT (nl11lOllO XOR wire_nl0iO0lli_dataout))) AND (NOT (nl11lOlOi XOR wire_nl0iO0lll_dataout))) AND (NOT (nl11lOlOl XOR wire_nl0iO0llO_dataout))) AND (NOT (nl11lOlOO XOR wire_nl0iO0lOi_dataout))) AND (NOT (nl11lOO1i XOR wire_nl0iO0lOl_dataout))) AND (NOT (nl11lOO1l XOR wire_nl0iO0lOO_dataout))) AND (NOT (nl11lOO1O XOR wire_nl0iO0O1i_dataout))); + niOilii1O <= (((((((((((((NOT (wire_nl0iO0l0i_dataout XOR nlii1111i)) AND (NOT (wire_nl0iO0l0l_dataout XOR nlii1111l))) AND (NOT (wire_nl0iO0l0O_dataout XOR nlii1111O))) AND (NOT (wire_nl0iO0lii_dataout XOR nlii1110i))) AND (NOT (wire_nl0iO0lil_dataout XOR nlii1110l))) AND (NOT (wire_nl0iO0liO_dataout XOR nlii1110O))) AND (NOT (wire_nl0iO0lli_dataout XOR nlii111ii))) AND (NOT (wire_nl0iO0lll_dataout XOR nlii111il))) AND (NOT (wire_nl0iO0llO_dataout XOR nlii111iO))) AND (NOT (wire_nl0iO0lOi_dataout XOR nlii111li))) AND (NOT (wire_nl0iO0lOl_dataout XOR nlii111ll))) AND (NOT (wire_nl0iO0lOO_dataout XOR nlii111lO))) AND (NOT (wire_nl0iO0O1i_dataout XOR nlii111Oi))); + niOiliiii <= (((((((((((((NOT (wire_nl0iO0l0i_dataout XOR nlii11iii)) AND (NOT (wire_nl0iO0l0l_dataout XOR nlii10Oii))) AND (NOT (wire_nl0iO0l0O_dataout XOR nlii10Oil))) AND (NOT (wire_nl0iO0lii_dataout XOR nlii10OiO))) AND (NOT (wire_nl0iO0lil_dataout XOR nlii10Oli))) AND (NOT (wire_nl0iO0liO_dataout XOR nlii10Oll))) AND (NOT (wire_nl0iO0lli_dataout XOR nlii10OlO))) AND (NOT (wire_nl0iO0lll_dataout XOR nlii10OOi))) AND (NOT (wire_nl0iO0llO_dataout XOR nlii10OOl))) AND (NOT (wire_nl0iO0lOi_dataout XOR nlii10OOO))) AND (NOT (wire_nl0iO0lOl_dataout XOR nlii1i11i))) AND (NOT (wire_nl0iO0lOO_dataout XOR nlii1i11l))) AND (NOT (wire_nl0iO0O1i_dataout XOR nlii1i11O))); + niOiliiil <= (niOilllii OR niOilll0O); + niOiliiiO <= (((((((((((((NOT (wire_nl0iO0l0i_dataout XOR nlii111Ol)) AND (NOT (wire_nl0iO0l0l_dataout XOR nlii111OO))) AND (NOT (wire_nl0iO0l0O_dataout XOR nlii1101i))) AND (NOT (wire_nl0iO0lii_dataout XOR nlii1101l))) AND (NOT (wire_nl0iO0lil_dataout XOR nlii1101O))) AND (NOT (wire_nl0iO0liO_dataout XOR nlii1100i))) AND (NOT (wire_nl0iO0lli_dataout XOR nlii1100l))) AND (NOT (wire_nl0iO0lll_dataout XOR nlii1100O))) AND (NOT (wire_nl0iO0llO_dataout XOR nlii110ii))) AND (NOT (wire_nl0iO0lOi_dataout XOR nlii110il))) AND (NOT (wire_nl0iO0lOl_dataout XOR nlii110iO))) AND (NOT (wire_nl0iO0lOO_dataout XOR nlii110li))) AND (NOT (wire_nl0iO0O1i_dataout XOR nlii110ll))); + niOiliili <= ((niOilii0O OR niOilllii) OR niOilll0O); + niOiliill <= (nlii1i1ii OR nlii11i0i); + niOiliilO <= (nlii1i1il OR nlii11i0l); + niOiliiOi <= (niOilil1i AND wire_w_lg_niOiliiOl45052w(0)); + niOiliiOl <= ((((((((((((NOT (nliiO0iOO AND niOilil1O)) AND (NOT (nliiO0iOi AND niOill00O))) AND (NOT (nliiO0ilO AND niOill00l))) AND (NOT (nliiO0ill AND niOill00i))) AND (NOT (nliiO0ili AND niOill01O))) AND (NOT (nliiO0iiO AND niOill01l))) AND (NOT (nliiO0iil AND niOill01i))) AND (NOT (nliiO0iii AND niOill1OO))) AND (NOT (nliiO0i0O AND niOill1Ol))) AND (NOT (nliiO0i0l AND niOill1Oi))) AND (NOT (nliiO0i0i AND niOill1lO))) AND (NOT (nliiO011l AND (nli1iOiOl AND niOill1ll)))); + niOiliiOO <= ((((((((((((NOT (nliiO0iOO AND niOilil1O)) AND (NOT (nliiO0iOi AND niOill00O))) AND (NOT (nliiO0ilO AND niOill00l))) AND (NOT (nliiO0ill AND niOill00i))) AND (NOT (nliiO0ili AND niOill01O))) AND (NOT (nliiO0iiO AND niOill01l))) AND (NOT (nliiO0iil AND niOill01i))) AND (NOT (nliiO0iii AND niOill1OO))) AND (NOT (nliiO0i0O AND niOill1Ol))) AND (NOT (nliiO0i0l AND niOill1Oi))) AND (NOT (nliiO0i0i AND niOill1lO))) AND (NOT (nliiO011l AND (nli1iOiOl AND niOill1ll)))); + niOilil0i <= (((((((((NOT (wire_nliiO0iOl_w_lg_nliiO0iOO44507w(0) AND wire_nilOOiii_w_lg_dataout45038w(0))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0iOi44506w(0) AND wire_nilOOilO_w_lg_dataout45039w(0)))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0ilO44505w(0) AND wire_nliiOiilO_w_lg_w_lg_nliiO0OOl44500w45040w(0)))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0ili44284w(0) AND wire_nlill0Oll_w_lg_nl10iO1li45042w(0)))) AND (NOT (wire_nliiOiilO_w_lg_nliiO0iiO44289w(0) AND wire_nliiOiilO_w_lg_w_lg_nliiO0Oll44497w45043w(0)))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0i0O44504w(0) AND wire_nliiOiilO_w_lg_w_lg_nliiO0Oil44494w45046w(0)))) AND (NOT (wire_nliiO0iOl_w_lg_nliiO0i0l44503w(0) AND wire_nliiOiilO_w_lg_w_lg_nliiO0Oii44493w45047w(0)))) AND (NOT (wire_w_lg_niOilli0i45236w(0) AND wire_w_lg_niOilliOl45266w(0)))) AND (NOT (wire_w_lg_niOilli0l45240w(0) AND wire_nlill0Oll_w_lg_nli1iOiOl45273w(0)))); + niOilil0l <= (wire_nli0O011O_dataout OR nli1iOl1i); + niOilil0O <= ((((((NOT (wire_nilOOi0O_dataout AND wire_nliiOiilO_w_lg_nliiO1liO44519w(0))) AND (NOT (wire_nilOOiil_dataout AND wire_nliiOiilO_w_lg_nliiO1lil44518w(0)))) AND (NOT (wire_nilOOiiO_dataout AND wire_nliiOiilO_w_lg_nliiO1lii44517w(0)))) AND (NOT (wire_nilOOill_dataout AND wire_nliiOiilO_w_lg_nliiO1l0O44516w(0)))) AND (NOT (wire_nilOOili_dataout AND wire_nliiOiilO_w_lg_nliiO1l0l44515w(0)))) AND (NOT (niOill0Ol AND wire_nliiO0iOl_w_lg_nliiO10ii44514w(0)))); + niOilil1i <= (wire_nli0O011O_dataout OR nli1iOiOO); + niOilil1l <= (niOilil0l AND wire_w_lg_niOilil0i45036w(0)); + niOilil1O <= wire_nilOOiii_w_lg_dataout45038w(0); + niOililii <= (wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOililil <= ((((wire_nilOl1Ol_w_lg_w_lg_w_lg_dataout43262w45182w45183w(0) AND wire_nilOl1ll_w_lg_dataout43266w(0)) AND wire_nilOl1li_w_lg_dataout43291w(0)) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOililiO <= ((wire_nilOii0i_w45177w(0) AND wire_nilOi0OO_w_lg_dataout45178w(0)) AND wire_nilOi0Ol_w_lg_dataout45180w(0)); + niOililli <= (nl01l0liO AND niOililOi); + niOililll <= (nl01l0liO AND niOill1il); + niOilillO <= (niOill1iO AND wire_nilOl1lO_w44969w(0)); + niOililOi <= (wire_nlill0Oll_w_lg_nl01ii1Oi44963w(0) AND wire_nilOi0il_w_lg_w_lg_dataout44964w44965w(0)); + niOililOl <= (wire_nilOi00l_dataout AND (wire_nilOi00O_w_lg_dataout45023w(0) AND wire_nilOi00i_dataout)); + niOililOO <= ((((wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOO1l45164w45165w45166w(0) AND wire_nlill0Oll_w_lg_nl11lOlOl43385w(0)) AND wire_nlill0Oll_w_lg_nl11lOlOi45152w(0)) AND wire_nlill0Oll_w_lg_nl11lOllO45169w(0)) AND wire_nlill0Oll_w_lg_nl11lOlll45171w(0)); + niOiliO0i <= (wire_nilOi11l_dataout AND nl11lOl1i); + niOiliO0l <= (k_conf(112) AND nl0iOiiOi); + niOiliO0O <= (nl0iOilOO AND nliiO100O); + niOiliO1i <= ((wire_nlill0Oll_w45159w(0) AND wire_nlill0Oll_w_lg_nl11lO11O45160w(0)) AND wire_nlill0Oll_w_lg_nl11lO11l45162w(0)); + niOiliO1l <= (wire_nilOi11l_dataout AND niOiliO1O); + niOiliO1O <= ((wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOO1i45149w45150w45151w(0) AND wire_nlill0Oll_w_lg_nl11lOlOi45152w(0)) AND nl11lOllO); + niOiliOii <= (nl0iOilOl AND nliiO100O); + niOiliOil <= (nl0iOilOi AND nliiO100O); + niOiliOiO <= (nl0iOillO AND nliiO100O); + niOiliOli <= (niOill1ii AND wire_nliiOiilO_w_lg_nliii001i44467w(0)); + niOiliOll <= (niOill1ii AND wire_nliiOiilO_w_lg_nliii001O44476w(0)); + niOiliOlO <= (niOillO1l OR niOiliOOO); + niOiliOOi <= (niOillO1O OR niOill11i); + niOiliOOl <= (((niOillO1O OR niOillO1l) OR niOill11i) OR niOiliOOO); + niOiliOOO <= (niOilil0l AND wire_w_lg_niOilil0i45036w(0)); + niOill00i <= (wire_nliiOiilO_w_lg_nliiO0OOi44499w(0) AND nlii11i0O); + niOill00l <= wire_nliiOiilO_w_lg_w_lg_nliiO0OOl44500w45040w(0); + niOill00O <= wire_nilOOilO_w_lg_dataout45039w(0); + niOill01i <= (wire_nliiOiilO_w_lg_nliiO0Oli44496w(0) AND niOO1i0i); + niOill01l <= wire_nliiOiilO_w_lg_w_lg_nliiO0Oll44497w45043w(0); + niOill01O <= wire_nlill0Oll_w_lg_nl10iO1li45042w(0); + niOill0ii <= (wire_w_lg_w_k_conf_range44263w44430w(0) AND wire_nliiO1l1i_w_lg_o44431w(0)); + niOill0il <= (niOill0li AND wire_w_lg_niOill0iO44369w(0)); + niOill0iO <= (((((((((((wire_w_lg_niOilil1O45126w(0) AND wire_w_lg_niOill00O45127w(0)) AND wire_w_lg_niOill00l45129w(0)) AND wire_w_lg_niOill00i45131w(0)) AND wire_w_lg_niOill01O45133w(0)) AND wire_w_lg_niOill01l45135w(0)) AND wire_w_lg_niOill01i45137w(0)) AND wire_w_lg_niOill1OO45139w(0)) AND wire_w_lg_niOill1Ol45141w(0)) AND wire_w_lg_niOill1Oi45143w(0)) AND wire_w_lg_niOill1lO45145w(0)) AND wire_w_lg_niOill1ll45147w(0)); + niOill0li <= wire_w_lg_w_k_conf_range44263w44368w(0); + niOill0ll <= (nl0iOil1l AND niOill0Oi); + niOill0lO <= (nl0iOil1i AND niOill0Oi); + niOill0Oi <= (nl0iOilli AND niOilliOi); + niOill0Ol <= wire_w_lg_w_k_conf_range44263w44363w(0); + niOill0OO <= ((((((NOT (wire_nliiOiilO_w_lg_nliiO0ill44279w(0) AND nlii11i0O)) AND (NOT (wire_nliiOiilO_w_lg_nliiO0iiO44289w(0) AND niOO10lli))) AND (NOT (wire_nliiOiilO_w_lg_nliiO0iil44294w(0) AND niOO1i0i))) AND (NOT (wire_nliiOiilO_w_lg_nliiO0iii44300w(0) AND niOO10lll))) AND (NOT (wire_w_lg_w_lg_niOilllOl44309w45114w(0) AND (NOT (wire_w_lg_niOilllOl44309w(0) AND nliiO0i0i))))) AND (NOT ((wire_nliiOliOi_dataout AND niOO10lil) AND (NOT (wire_nliiOliOi_dataout AND nliiO011l))))); + niOill10i <= (nl0iOil1i AND (nl0iOiO1l AND niOillllO)); + niOill10l <= (wire_w_lg_w_k_conf_range44263w44264w(0) OR wire_w_lg_niOilllOO44447w(0)); + niOill10O <= (nl0iOil1i AND (nl0iOiO1i AND (niOillllO AND niOill1ii))); + niOill11i <= (niOilil1i AND wire_w_lg_niOiliiOO45050w(0)); + niOill11l <= ((nl0l0100O AND nl0OiOl0O) OR niOill11O); + niOill11O <= (nli1iOl1l AND wire_w_lg_niOilil0O45034w(0)); + niOill1ii <= (k_conf(112) AND niOilllOO); + niOill1il <= (wire_nilOi0iO_dataout AND wire_nilOi00l_dataout); + niOill1iO <= (wire_nilOi0li_dataout AND wire_nilOi00l_dataout); + niOill1li <= (niOill0li AND niOill0iO); + niOill1ll <= (wire_nliiOiilO_w_lg_nliiO0l1i44491w(0) AND niOO10lil); + niOill1lO <= (wire_nliiOiilO_w_lg_nliiO0O0O44492w(0) AND niOO10lii); + niOill1Oi <= wire_nliiOiilO_w_lg_w_lg_nliiO0Oii44493w45047w(0); + niOill1Ol <= wire_nliiOiilO_w_lg_w_lg_nliiO0Oil44494w45046w(0); + niOill1OO <= (wire_nliiOiilO_w_lg_nliiO0OiO44495w(0) AND niOO10lll); + niOilli0i <= (niOilllOl AND nliiO0i0i); + niOilli0l <= (wire_nliiOliOi_w_lg_dataout44320w(0) AND nliiO011l); + niOilli0O <= (nl0iOil1O AND niOilliil); + niOilli1i <= (nl0iOil1l AND niOilli1O); + niOilli1l <= (nl0iOil1i AND niOilli1O); + niOilli1O <= (nl0iOiliO AND niOillllO); + niOilliii <= (nl0iOil1l AND niOilliil); + niOilliil <= (nl0iOilil AND niOilliOi); + niOilliiO <= (nl0iOil1O AND niOillilO); + niOillili <= (nl0iOil1l AND niOillilO); + niOillill <= (niOillllO AND (((wire_w_lg_w_k_conf_range44263w44327w(0) AND wire_w_lg_niOilllil44328w(0)) AND wire_w_lg_niOilllii44330w(0)) AND wire_w_lg_niOilll0O44332w(0))); + niOillilO <= (nl0iOilii AND niOilliOi); + niOilliOi <= (k_conf(112) AND niOillllO); + niOilliOl <= (niOilllOl AND niOO10lii); + niOilliOO <= (wire_nliiOliOi_w_lg_dataout44320w(0) AND niOO10lil); + niOilll0i <= (nliiO1lli AND nliiO10ii); + niOilll0l <= (nl0iOil1l AND niOilllll); + niOilll0O <= wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0); + niOilll1i <= (nliiOiiii OR nliiOii0O); + niOilll1l <= (nl0iOil1O AND niOilllll); + niOilll1O <= (wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1O11i_dataout AND niOilll0l)); + niOilllii <= wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0); + niOilllil <= wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w43350w(0); + niOillliO <= (wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOilllli <= (nl0iOil1i AND niOilllll); + niOilllll <= (nl0iOil0O AND niOillllO); + niOillllO <= (nl0iOiiOl AND nl0iOiiOi); + niOilllOi <= (nl01l0O1l OR nl01l0O1i); + niOilllOl <= (niOillO1i OR niOilllOO); + niOilllOO <= (wire_nilO010O_w_lg_dataout8973w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOillO0i <= wire_w_lg_w_k_conf_range48010w48011w(0); + niOillO0l <= wire_w_lg_w_k_conf_range48008w48009w(0); + niOillO0O <= wire_w_lg_w_k_conf_range44115w44116w(0); + niOillO1i <= wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0); + niOillO1l <= (wire_nli0O011O_dataout AND (nl0l010ii AND nl0OiOl0O)); + niOillO1O <= (wire_nli0O011O_dataout AND (nl0l010il AND nl0OiOl0O)); + niOillOii <= ((((wire_nlill0Oll_w_lg_nlil1100O44088w(0) AND wire_nlill0Oll_w_lg_nlil1100i44089w(0)) AND nlil1101O) AND wire_nlOilOO1O_dataout) OR nliiOOilO); + niOillOil <= (((((NOT (k_cnt(107) XOR nlil11lll)) AND (NOT (k_cnt(108) XOR nlil11llO))) AND (NOT (k_cnt(109) XOR nlil11lOi))) AND (NOT (k_cnt(110) XOR nlil11lOl))) AND (NOT (k_cnt(111) XOR nlil11lOO))); + niOillOiO <= (((((NOT (k_cnt(107) XOR nlil11O1O)) AND (NOT (k_cnt(108) XOR nlil11O0i))) AND (NOT (k_cnt(109) XOR nlil11O0l))) AND (NOT (k_cnt(110) XOR nlil11O0O))) AND (NOT (k_cnt(111) XOR nlil11Oii))); + niOillOli <= ((wire_nlil1i10l_w_lg_dataout44029w(0) OR (wire_nilOOi0i_dataout OR wire_nilOO1iO_dataout)) OR nlil110ii); + niOillOll <= (nlil11O1i AND wire_nlOilOiiO_dataout); + niOillOlO <= (wire_nilOOi0i_dataout OR wire_nlil10OOO_w_lg_dataout44032w(0)); + niOillOOi <= (nlil11Oil AND wire_nlOilOiiO_dataout); + niOillOOl <= (wire_nl1000i_w_lg_niOOi1i1i44005w(0) AND niOillOOO); + niOillOOO <= (wire_nlill0Oll_w_lg_nli11illO44166w(0) AND wire_nlill0Oll_w_lg_nli11illl44167w(0)); + niOilO00i <= (wire_w_lg_niOilO0ii43817w(0) OR niOilO00l); + niOilO00l <= (niOilO00O AND wire_nlOilOO1O_dataout); + niOilO00O <= (((((((((wire_nlill0Oll_w_lg_nlil01i1l44140w(0) AND wire_nlill0Oll_w_lg_nlil01i1i44141w(0)) AND wire_nlill0Oll_w_lg_nlil010OO44143w(0)) AND wire_nlill0Oll_w_lg_nlil010Ol44145w(0)) AND wire_nlill0Oll_w_lg_nlil010Oi44147w(0)) AND wire_nlill0Oll_w_lg_nlil010lO44149w(0)) AND wire_nlill0Oll_w_lg_nlil010ll44151w(0)) AND wire_nlill0Oll_w_lg_nlil010li44153w(0)) AND wire_nlill0Oll_w_lg_nlil010iO44155w(0)) AND wire_nlill0Oll_w_lg_nlil010il44157w(0)); + niOilO01i <= ((wire_nilOO0ii_dataout AND nl0illl0O) OR wire_nlill0Oll_w_lg_nlil01i0i43933w(0)); + niOilO01l <= ((wire_nilOOi0i_dataout OR (nl0l0i00O OR (wire_nilOOi0l_w_lg_dataout43900w(0) OR wire_nlililOOl_w_lg_dataout43903w(0)))) OR nlil1lOil); + niOilO01O <= (wire_w_lg_niOilO0ii43817w(0) OR niOilO0il); + niOilO0ii <= (nli11l1ll AND nli11ilOi); + niOilO0il <= ((((((wire_nlill0Oll_w_lg_nlil010ii44127w(0) AND wire_nlill0Oll_w_lg_nlil0100O44128w(0)) AND wire_nlill0Oll_w_lg_nlil0100l44130w(0)) AND wire_nlill0Oll_w_lg_nlil0100i44132w(0)) AND wire_nlill0Oll_w_lg_nlil0101O44134w(0)) AND wire_nlill0Oll_w_lg_nlil0101l44136w(0)) AND wire_nlill0Oll_w_lg_nlil1OOlO44138w(0)); + niOilO0iO <= ((nli11l1ll AND nli11ilOi) AND wire_nliliiO1i_w48213w(0)); + niOilO0li <= (nl0illl0O AND ((niOilO0iO AND nlil1lOil) AND nlil1lOii)); + niOilO0ll <= ((((((((nlil00ilO OR nlil00ill) OR nlil00ili) OR nlil00iii) OR nlil00i0O) OR nlil00i1O) OR nlil00i1l) OR nlil00i1i) OR nlil000OO); + niOilO0lO <= ((((((((nlil00ilO OR nlil00ili) OR nlil00iil) OR nlil00iii) OR nlil00i0l) OR nlil00i0i) OR nlil00i1O) OR nlil00i1l) OR nlil000OO); + niOilO0Oi <= (nlil00ilO OR nlil000OO); + niOilO0Ol <= ((wire_nilO011l_w_lg_dataout43407w(0) AND niOilO0OO) AND nlil000Oi); + niOilO0OO <= (wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOilO10i <= (wire_nilOO0ii_w_lg_dataout43403w(0) AND wire_w_lg_w_lg_niOilOO1i43375w43401w(0)); + niOilO10l <= (wire_nlill0Oll_w_lg_nli1il10l43974w(0) AND niOilO1ii); + niOilO10O <= wire_w_lg_w_k_conf_range43970w43972w(0); + niOilO11i <= (nlil1lOil AND (wire_w_lg_niOilOO1i43375w(0) OR (nlil1lOii OR ni0lO1l))); + niOilO11l <= (wire_nilOO0ii_w_lg_dataout43403w(0) AND wire_w_lg_niOilOO1i43987w(0)); + niOilO11O <= (nli11l1ll AND (nli11ilOi OR niOiili1O)); + niOilO1ii <= (nl0l010li AND niOilOO1i); + niOilO1il <= (niOilOO1i AND niOilOllO); + niOilO1iO <= (wire_nlil1i10l_dataout AND (wire_w_lg_niOilOlll44007w(0) AND (wire_w_lg_niOilOlOi44008w(0) AND (wire_w_lg_niOilOlOl44009w(0) AND (wire_nlill0Oll_w_lg_nli11iiii44010w(0) AND (wire_nilOOi0i_w_lg_dataout44011w(0) AND (niOillOOl AND nlil11O1l))))))); + niOilO1li <= (nlil00ili OR (nlil00iii OR nlil00i1l)); + niOilO1ll <= ((niOilO1Oi AND ni0lO1l) AND wire_nlill0Oll_w_lg_nlil1llOl43953w(0)); + niOilO1lO <= ((niOilOlll AND niOilO1Oi) AND (wire_nlill0Oll_w_lg_nli1il10O43948w(0) OR wire_w_lg_niOilOlii43399w(0))); + niOilO1Oi <= (wire_w_lg_niOilOO1i43375w(0) AND wire_nlill0Oll_w_lg_nlil1lOil43935w(0)); + niOilO1Ol <= ((wire_w_lg_niOilOlOO43941w(0) AND wire_nlill0Oll_w_lg_nlil01i1O43944w(0)) AND wire_nlill0Oll_w_lg_nlil1llOi43939w(0)); + niOilO1OO <= (wire_nlill0Oll_w_lg_nl0l010lO43938w(0) AND wire_nlill0Oll_w_lg_nlil1llOi43939w(0)); + niOilOi0i <= (niOilOO1i AND niOilOi0l); + niOilOi0l <= (wire_nilOO1il_dataout OR (niOilO11O AND (((wire_nliliiO1i_dataout AND wire_nliliilOO_dataout) AND wire_nliliilOl_w_lg_dataout43980w(0)) AND wire_nliliilOi_w_lg_dataout43982w(0)))); + niOilOi0O <= wire_w_lg_w_lg_niOilOO1i43375w43401w(0); + niOilOi1i <= (wire_nilO011l_w_lg_dataout43407w(0) AND niOilOO1O); + niOilOi1l <= (wire_nilOO0ii_w_lg_dataout43403w(0) AND wire_w_lg_niOilOi1O43404w(0)); + niOilOi1O <= (wire_nlill0Oll_w_lg_nl11Oii0l59845w(0) AND wire_nlill0Oll_w_lg_nl11Oii0i60369w(0)); + niOilOiii <= (wire_nilOO1il_dataout OR wire_w_lg_niOilOi1O43404w(0)); + niOilOiil <= (wire_w_lg_niOilOlii43399w(0) AND nlil111Oi); + niOilOiiO <= (wire_nilOO1li_dataout AND wire_w_lg_niOilOO1i43375w(0)); + niOilOili <= (wire_nilOO0il_dataout AND (wire_w_lg_niOilOO1i43375w(0) AND niOilOl1l)); + niOilOill <= (niOilOO1i AND niOilOl1l); + niOilOilO <= (wire_nilOO1ll_dataout AND wire_w_lg_niOilOO1i43375w(0)); + niOilOiOi <= (wire_w_lg_niOilOO1i43375w(0) AND niOilOlOi); + niOilOiOl <= (wire_nilOi11l_w_lg_w_lg_w_lg_dataout43384w43387w43388w(0) AND wire_w_lg_niOilOO1i43390w(0)); + niOilOiOO <= (((wire_nlill0Oll_w_lg_w53748w53749w(0) AND wire_nlill0Oll_w_lg_nl11lO11l45162w(0)) AND nl11lO11i) AND nl11l0i1i); + niOilOl0i <= (nl0l010ll AND wire_w_lg_niOilOO1i43375w(0)); + niOilOl0l <= ((wire_nilOO0ii_dataout AND (wire_w_lg_niOilOO1i43375w(0) AND niOilOlll)) AND niOilOlii); + niOilOl0O <= (wire_nilOO0il_dataout AND (niOilOO1i AND niOilOlii)); + niOilOl1i <= (niOilOlOO AND niOilOl1l); + niOilOl1l <= (((wire_nlill0Oll_w_lg_nlil1OOll44159w(0) AND wire_nlill0Oll_w_lg_nlil1OOli44160w(0)) AND wire_nlill0Oll_w_lg_nlil1OOiO44162w(0)) AND wire_nlill0Oll_w_lg_nlil1lOli44164w(0)); + niOilOl1O <= (nl0l010lO AND niOilOO1i); + niOilOlii <= (nl111iOiO AND (wire_nlil10OOO_dataout AND ((wire_w_lg_niOilOlOi44008w(0) AND (wire_w_lg_niOilOlOl44009w(0) AND (wire_nlill0Oll_w_lg_nli11iiii44010w(0) AND (wire_nilOOi0i_w_lg_dataout44011w(0) AND (niOillOOl AND nlil11l0i))))) AND nlil111Oi))); + niOilOlil <= (wire_nilOO0il_dataout AND (wire_w_lg_niOilOO1i43375w(0) AND niOilOlOl)); + niOilOliO <= (wire_nilOO0il_dataout AND (nli11iiii AND niOilOO1i)); + niOilOlli <= ((((niOilOO0l OR nlil00iil) OR nlil00iii) OR nlil00i0O) OR nlil00i0l); + niOilOlll <= (wire_nilOOi1l_dataout AND ((wire_nilOOi1i_w_lg_dataout43355w(0) AND wire_nilOO0OO_dataout) AND wire_nilOO0Ol_dataout)); + niOilOllO <= (wire_nilOOi1l_dataout AND (wire_nilOOi1i_w_lg_dataout43363w(0) AND wire_nilOO0Ol_w_lg_dataout43358w(0))); + niOilOlOi <= (wire_nilOOi1l_dataout AND ((wire_nilOOi1i_w_lg_dataout43355w(0) AND wire_nilOO0OO_w_lg_dataout43356w(0)) AND wire_nilOO0Ol_dataout)); + niOilOlOl <= (wire_nilOOi1l_dataout AND ((wire_nilOOi1i_w_lg_dataout43355w(0) AND wire_nilOO0OO_w_lg_dataout43356w(0)) AND wire_nilOO0Ol_w_lg_dataout43358w(0))); + niOilOlOO <= (niOilOO0i OR niOilOO1l); + niOilOO0i <= ((wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) AND wire_nilO010i_w_lg_dataout25163w(0)) OR wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w43350w(0)); + niOilOO0l <= (nlil00ili OR nlil00iiO); + niOilOO0O <= ((NOT (wire_nlill0Oll_w_lg_nlil1i1OO43338w(0) AND wire_nlil1i1Oi_dataout)) AND (NOT (wire_nlil1i1Ol_dataout AND wire_nlill0Oll_w_lg_nlil11OiO43341w(0)))); + niOilOO1i <= ((niOilOO0i OR niOilOO1O) OR niOilOO1l); + niOilOO1l <= wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0); + niOilOO1O <= wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0); + niOilOOii <= (wire_nliliOO0i_w_lg_dataout43231w(0) AND wire_nliliOlll_o); + niOilOOil <= (wire_nliliOOOl_w_lg_dataout43190w(0) AND wire_nliliOO0O_o); + niOilOOiO <= (wire_nlill11iO_w_lg_dataout43154w(0) AND wire_nlill111i_o); + niOilOOli <= (wire_nlill100i_w_lg_dataout43113w(0) AND wire_nlill11ll_o); + niOilOOll <= (wire_nlill10Ol_w_lg_dataout43082w(0) AND wire_nlill100O_o); + niOilOOlO <= (wire_nlill1ili_w_lg_dataout43041w(0) AND wire_nlill1i1i_o); + niOilOOOi <= (wire_nlill1l1l_w_lg_dataout43005w(0) AND wire_nlill1ilO_o); + niOilOOOl <= (wire_nlill1l0i_o AND wire_nlill0Oll_w_lg_nliliO1li42964w(0)); + niOilOOOO <= (nlill1lil AND wire_w_lg_niOiO111l42937w(0)); + niOiO000i <= (nlli0ilil XOR nlli0ilii); + niOiO000l <= (nlli0ilii XOR nlli0il0O); + niOiO000O <= (nlli0il0O XOR nlli0il0l); + niOiO001i <= (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR niOiO01ll))); + niOiO001l <= (nlli0iill XOR niOiO00OO); + niOiO001O <= (nlli0iliO XOR nlli0ilil); + niOiO00ii <= (nlli0ilii XOR niOiO000O); + niOiO00il <= (nlli0ilil XOR niOiO01ll); + niOiO00iO <= (nlli0ilii XOR niOiO011i); + niOiO00li <= (nlli0iliO XOR niOiO000O); + niOiO00ll <= (nlli0ilil XOR niOiO00ii); + niOiO00lO <= (nlli0iliO XOR niOiO01il); + niOiO00Oi <= (nlli0il0O XOR niOiO011l); + niOiO00Ol <= (nlli0ilii XOR niOiO011l); + niOiO00OO <= (nlli0illl XOR niOiO010l); + niOiO010i <= (nlli0ilil XOR niOiO011l); + niOiO010l <= (nlli0iliO XOR niOiO01OO); + niOiO010O <= (nlli0iliO XOR niOiO011O); + niOiO011i <= (nlli0il0O XOR nlli0il0i); + niOiO011l <= (nlli0il0l XOR nlli0il0i); + niOiO011O <= (nlli0ilii XOR nlli0il0i); + niOiO01ii <= (nlli0ilil XOR nlli0il0O); + niOiO01il <= (nlli0ilii XOR niOiO00Oi); + niOiO01iO <= (nlli0iliO XOR niOiO00iO); + niOiO01li <= (nlli0ilil XOR nlli0il0i); + niOiO01ll <= (nlli0ilii XOR nlli0il0l); + niOiO01lO <= (nlli0ilil XOR niOiO011O); + niOiO01Oi <= (nlli0illl XOR (nlli0iliO XOR (nlli0ilil XOR niOiO00Ol))); + niOiO01Ol <= (nlli0illi XOR niOiO001O); + niOiO01OO <= (nlli0ilil XOR niOiO011i); + niOiO0i0i <= (nlli0il0O XOR nlli0il0i); + niOiO0i0l <= (nlli0il0l XOR nlli0il0i); + niOiO0i0O <= (nlli0il0O XOR niOiO0i0l); + niOiO0i1i <= (nlli0illi XOR niOiO00il); + niOiO0i1l <= (nlli0il0l XOR niOiO0l0i); + niOiO0i1O <= (nlli0il0O XOR niOiO0l0i); + niOiO0iii <= (nlli0ilii XOR nlli0il0O); + niOiO0iil <= (nlli0ilii XOR nlli0il0i); + niOiO0iiO <= (nlli0ilil XOR niOiO0i0l); + niOiO0ili <= (nlli0ilii XOR nlli0il0l); + niOiO0ill <= (nlli0illl XOR niOiO0ilO); + niOiO0ilO <= (nlli0iliO XOR (nlli0ilil XOR niOiO0i0i)); + niOiO0iOi <= (nlli0iliO XOR niOiO0iil); + niOiO0iOl <= (nlli0ilil XOR nlli0il0O); + niOiO0iOO <= (nlli0ilil XOR niOiO0ili); + niOiO0l0i <= (nlli0iO1i OR nlli0il0i); + niOiO0l0l <= (nlli0illl XOR (nlli0iliO XOR (nlli0ilil XOR niOiO0O1l))); + niOiO0l0O <= (nlli0illi XOR niOiO0liO); + niOiO0l1i <= (nlli0ilii XOR niOiO0i0i); + niOiO0l1l <= (nlli0il0O XOR nlli0il0l); + niOiO0l1O <= (nlli0ilii XOR niOiO0i0O); + niOiO0lii <= (nlli0ilil XOR niOiO0i1O); + niOiO0lil <= (nlli0ilii XOR nlli0il0l); + niOiO0liO <= (nlli0iliO XOR nlli0ilil); + niOiO0lli <= (nlli0ilil XOR nlli0ilii); + niOiO0lll <= (nlli0ilii XOR nlli0il0O); + niOiO0llO <= (nlli0ilil XOR niOiO0lil); + niOiO0lOi <= (nlli0ilii XOR niOiO0i1O); + niOiO0lOl <= (nlli0il0O XOR nlli0il0l); + niOiO0lOO <= (nlli0ilii XOR niOiO0lOl); + niOiO0O0i <= (nlli0illl XOR (nlli0iliO XOR niOiO0lii)); + niOiO0O0l <= (nlli0illi XOR niOiO0llO); + niOiO0O0O <= (k_conf(217) AND wire_nlOiOi11i_dataout); + niOiO0O1i <= (nlli0il0O XOR niOiO0i1l); + niOiO0O1l <= (nlli0ilii XOR niOiO0i1l); + niOiO0O1O <= (nlli0iO1i OR nlli0iiiO); + niOiO0Oii <= (nll0lO01i AND wire_nl1000i_w_lg_nll0ll1OO36546w(0)); + niOiO0Oil <= (wire_w_lg_niOiO0Oll36547w(0) OR (nll0lO01i AND nll0ll1OO)); + niOiO0OiO <= ((nll0O10OO AND niOiO0OOl) AND wire_nl1000i_w_lg_nll0liiOl29690w(0)); + niOiO0Oli <= (wire_nl1000i_w_lg_nll0OOOll36490w(0) AND wire_w_lg_niOiOiOli36492w(0)); + niOiO0Oll <= (niOiOiOll OR (wire_nl1000i_w_lg_nll0O10OO35783w(0) AND niOiO0OOl)); + niOiO0OlO <= ((wire_nl1000i_w_lg_nll0lOi1l36419w(0) OR nll0lO01i) OR niOl1011l); + niOiO0OOi <= (wire_nl1000i_w_lg_nlilOO0iO5228w(0) OR niOl1011l); + niOiO0OOl <= (wire_nl1000i_w_lg_nll0O1i1i35781w(0) AND niOiOi11i); + niOiO0OOO <= (nll0O1i1i AND niOiOi11i); + niOiO100i <= (wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43276w43301w43311w(0) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO100l <= (((((wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43264w(0) AND wire_nilOl1lO_w_lg_dataout43274w(0)) AND wire_nilOl1ll_w_lg_dataout43266w(0)) AND wire_nilOl1li_w_lg_dataout43291w(0)) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_dataout); + niOiO100O <= (((((wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43264w(0) AND wire_nilOl1lO_w_lg_dataout43274w(0)) AND wire_nilOl1ll_w_lg_dataout43266w(0)) AND wire_nilOl1li_w_lg_dataout43291w(0)) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO101i <= (wire_nilOl1OO_w_lg_w_lg_w_lg_w43284w43285w43313w43321w(0) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO101l <= (((((wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43268w43269w(0) AND wire_nilOl1lO_w_lg_dataout43274w(0)) AND wire_nilOl1ll_w_lg_dataout43266w(0)) AND wire_nilOl1li_w_lg_dataout43291w(0)) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO101O <= ((wire_nilOl1OO_w_lg_w_lg_w43284w43285w43313w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO10ii <= (wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43276w43301w43302w(0) AND wire_nilOl1il_dataout); + niOiO10il <= wire_nilOl1OO_w43303w(0); + niOiO10iO <= (wire_nlill0Oll_w_lg_nli1iOilO42900w(0) AND nli1iOili); + niOiO10li <= (wire_nlill0Oll_w_lg_nli1iOilO42900w(0) AND wire_nlill0Oll_w_lg_nli1iOili42902w(0)); + niOiO10ll <= (wire_nlill0Oll_w_lg_w_lg_nli1iOilO42904w42905w(0) AND nli1iOili); + niOiO10lO <= (wire_nlill0Oll_w_lg_w_lg_nli1iOilO42904w42905w(0) AND wire_nlill0Oll_w_lg_nli1iOili42902w(0)); + niOiO10Oi <= ((wire_nlill0Oll_w_lg_nli1iOilO42904w(0) AND wire_nlill0Oll_w_lg_nli1iOill42899w(0)) AND nli1iOili); + niOiO10Ol <= ((wire_nilOlilO_w_lg_dataout42890w(0) AND wire_nilOlill_w_lg_dataout42891w(0)) AND wire_nilOlili_w_lg_dataout42893w(0)); + niOiO10OO <= ((wire_nilOlilO_w_lg_dataout42890w(0) AND wire_nilOlill_w_lg_dataout42891w(0)) AND wire_nilOlili_w_lg_dataout42893w(0)); + niOiO110i <= (nl01ii1Ol OR (wire_nilOi0il_dataout OR nl01ii1Oi)); + niOiO110l <= (wire_nilOi0iO_dataout AND wire_nilOi00l_dataout); + niOiO110O <= (wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43296w43297w43298w(0) AND wire_nilOl1il_dataout); + niOiO111i <= (nlill1lil AND niOiO111l); + niOiO111l <= (((((((wire_nlill0Oll_w_lg_nl01ii1il43323w(0) AND wire_nlill0Oll_w_lg_nl01ii1ii43324w(0)) AND wire_nlill0Oll_w_lg_nl01ii10O43326w(0)) AND wire_nlill0Oll_w_lg_nl01ii10l43328w(0)) AND wire_nlill0Oll_w_lg_nl01ii10i43330w(0)) AND wire_nlill0Oll_w_lg_nl01ii11O43332w(0)) AND wire_nlill0Oll_w_lg_nl01ii11l43334w(0)) AND wire_nlill0Oll_w_lg_nl01ii11i43336w(0)); + niOiO111O <= ((wire_nilOi0li_w_lg_dataout42931w(0) AND wire_nilOi0iO_w_lg_dataout42932w(0)) AND wire_w_lg_niOiO110i42934w(0)); + niOiO11ii <= (wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43296w43297w43298w(0) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO11il <= (wire_nilOl1OO_w_lg_w_lg_w_lg_w43284w43290w43292w43293w(0) AND wire_nilOl1il_dataout); + niOiO11iO <= (wire_nilOl1OO_w_lg_w_lg_w_lg_w43284w43290w43292w43293w(0) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO11li <= ((wire_nilOl1OO_w_lg_w_lg_w43284w43285w43286w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_dataout); + niOiO11ll <= ((wire_nilOl1OO_w_lg_w_lg_w43284w43285w43286w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO11lO <= ((wire_nilOl1OO_w_lg_w_lg_w43275w43276w43277w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_dataout); + niOiO11Oi <= ((wire_nilOl1OO_w_lg_w_lg_w43275w43276w43277w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0)) AND wire_nilOl1il_w_lg_dataout43280w(0)); + niOiO11Ol <= (wire_nilOl1OO_w43270w(0) AND wire_nilOl1ll_w_lg_dataout43266w(0)); + niOiO11OO <= (wire_nilOl1OO_w43265w(0) AND wire_nilOl1ll_w_lg_dataout43266w(0)); + niOiO1i0i <= ((wire_nilOlilO_w_lg_dataout42890w(0) AND wire_nilOlill_w_lg_dataout42891w(0)) AND wire_nilOlili_w_lg_dataout42893w(0)); + niOiO1i0l <= (wire_niO1110i_w_lg_dataout42873w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1i0O <= wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w(0); + niOiO1i1i <= ((wire_nilOlilO_w_lg_dataout42890w(0) AND wire_nilOlill_w_lg_dataout42891w(0)) AND wire_nilOlili_w_lg_dataout42893w(0)); + niOiO1i1l <= ((wire_nilOlilO_w_lg_dataout42890w(0) AND wire_nilOlill_w_lg_dataout42891w(0)) AND wire_nilOlili_w_lg_dataout42893w(0)); + niOiO1i1O <= ((wire_nilOlilO_w_lg_dataout42890w(0) AND wire_nilOlill_w_lg_dataout42891w(0)) AND wire_nilOlili_w_lg_dataout42893w(0)); + niOiO1iii <= (wire_niO1111O_w_lg_dataout42869w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1iil <= wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w(0); + niOiO1iiO <= (wire_niO1111l_w_lg_dataout42865w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1ili <= wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w(0); + niOiO1ill <= (wire_niO1111i_w_lg_dataout42861w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1ilO <= wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w(0); + niOiO1iOi <= (wire_nilOOOOO_w_lg_dataout42857w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1iOl <= wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w(0); + niOiO1iOO <= (wire_nilOOOOl_w_lg_dataout42853w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1l0i <= (wire_nilOOOlO_w_lg_dataout42845w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1l0l <= (wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0)); + niOiO1l0O <= (niOiO1OOi OR (wire_nlilllOiO_w_lg_o42807w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0))); + niOiO1l1i <= wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w(0); + niOiO1l1l <= (wire_nilOOOOi_w_lg_dataout42849w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1l1O <= wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w(0); + niOiO1lii <= (((NOT (nlillOl1i XOR nlliiil1l)) AND (NOT (nlillOl1l XOR nlliiil1O))) AND (NOT (nlillOl1O XOR nlliiil0i))); + niOiO1lil <= (((nlillOlOi OR nlillOlli) OR nlillOliO) OR nlillOlii); + niOiO1liO <= (nlillOlOi OR nlillOlii); + niOiO1lli <= (nlillOllO OR nlillOlll); + niOiO1lll <= (niOiO1llO AND wire_w_lg_niOiO1OOl42297w(0)); + niOiO1llO <= (nlillil1i AND (nlilliiOO AND nlilliiOl)); + niOiO1lOi <= (wire_w_lg_niOiO1lOl42295w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1lOl <= (nlilliiOi AND niOiO1OOl); + niOiO1lOO <= (wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0)); + niOiO1O0i <= (wire_w42246w(0) OR wire_nl1000i_w_lg_nlilOO0li42249w(0)); + niOiO1O0l <= (nlilOO0li AND (wire_nilOOOOi_dataout AND wire_nl1000i_w_lg_nlilli0Oi42220w(0))); + niOiO1O0O <= (nlilOO0li AND (wire_nilOOOOl_dataout AND wire_nl1000i_w_lg_nlilli0Ol42223w(0))); + niOiO1O1i <= ((wire_w_lg_niOiO1O1l42254w(0) AND wire_nlOilOiiO_dataout) AND wire_nlOiii1il_dataout); + niOiO1O1l <= (((((wire_nl1000i_w_lg_nlillOiOl42879w(0) AND wire_nl1000i_w_lg_nlillOiOi42880w(0)) AND wire_nl1000i_w_lg_nlillOilO42882w(0)) AND wire_nl1000i_w_lg_nlillOill42884w(0)) AND wire_nl1000i_w_lg_nlillOili42886w(0)) AND wire_nl1000i_w_lg_nlillOiiO42888w(0)); + niOiO1O1O <= (((nlillOlOi OR wire_nlOi1Oi1O_dataout) OR nlillOllO) OR nlillOlll); + niOiO1Oii <= (nlilOO0li AND (wire_nilOOOOO_dataout AND wire_nl1000i_w_lg_nlilli0OO42226w(0))); + niOiO1Oil <= (nlilOO0li AND (wire_niO1111i_dataout AND wire_nl1000i_w_lg_nlillii1i42232w(0))); + niOiO1OiO <= (nlilOO0li AND (wire_niO1111l_dataout AND wire_nl1000i_w_lg_nlillii1l42235w(0))); + niOiO1Oli <= (nlilOO0li AND (wire_niO1111O_dataout AND wire_nl1000i_w_lg_nlillii1O42238w(0))); + niOiO1Oll <= (nlillOlil AND wire_nlOii0Oll_w_lg_dataout42177w(0)); + niOiO1OlO <= ((wire_nilOOOlO_dataout AND wire_nlOii0Oll_dataout) AND wire_nlOiii10i_dataout); + niOiO1OOi <= (((nlillOlil AND niOiO1OOl) AND nlilliiOi) AND niOiO1OOO); + niOiO1OOl <= (nlillOiil AND nlillOiii); + niOiO1OOO <= (wire_nlOi1Oi1O_dataout OR wire_nlOiii10i_w_lg_dataout42170w(0)); + niOiOi00i <= (wire_nl1000i_w_lg_w36978w36979w(0) AND wire_nl1000i_w_lg_nlli1Oili36980w(0)); + niOiOi00l <= (nlli0illO OR nlli0iili); + niOiOi00O <= (nlli0illO AND nlli0iili); + niOiOi01i <= (k_conf(217) AND wire_nlOiOi11i_dataout); + niOiOi01l <= ((((((((((((((((((((((((((((((((NOT (nlli0ii1l XOR wire_nl1000i_w_lg_nll0i0iOl37427w(0))) AND (NOT (nlli0ii1i XOR wire_nl1000i_w_lg_nll0i0iOO37430w(0)))) AND (NOT (nlli0i0OO XOR wire_nl1000i_w_lg_nll0i0l1i37434w(0)))) AND (NOT (nlli0i0Ol XOR wire_nl1000i_w_lg_nll0i0l1l37438w(0)))) AND (NOT (nlli0i0Oi XOR wire_nl1000i_w_lg_nll0i0l1O37442w(0)))) AND (NOT (nlli0i0lO XOR wire_nl1000i_w_lg_nll0i0l0i37446w(0)))) AND (NOT (nlli0i0ll XOR wire_nl1000i_w_lg_nll0i0l0l37450w(0)))) AND (NOT (nlli0i0li XOR wire_nl1000i_w_lg_nll0i0l0O37454w(0)))) AND (NOT (nlli0iili XOR wire_nl1000i_w_lg_nll0i0lii37458w(0)))) AND (NOT (nlli0iiiO XOR wire_nl1000i_w_lg_nll0i0lil37462w(0)))) AND (NOT (nlli0iiil XOR wire_nl1000i_w_lg_nll0i0liO37466w(0)))) AND (NOT (nlli0iiii XOR wire_nl1000i_w_lg_nll0i0lli37470w(0)))) AND (NOT (nlli0ii0O XOR wire_nl1000i_w_lg_nll0i0lll37474w(0)))) AND (NOT (nlli0ii0l XOR wire_nl1000i_w_lg_nll0i0llO37478w(0)))) AND (NOT (nlli0ii0i XOR wire_nl1000i_w_lg_nll0i0lOi37482w(0)))) AND (NOT (nlli0ii1O XOR wire_nl1000i_w_lg_nll0i0lOl37486w(0)))) AND (NOT (nlli0il1O XOR wire_nl1000i_w_lg_nll0i0lOO37490w(0)))) AND (NOT (nlli0il1l XOR wire_nl1000i_w_lg_nll0i0O1i37494w(0)))) AND (NOT (nlli0il1i XOR wire_nl1000i_w_lg_nll0i0O1l37498w(0)))) AND (NOT (nlli0iiOO XOR wire_nl1000i_w_lg_nll0i0O1O37502w(0)))) AND (NOT (nlli0iiOl XOR wire_nl1000i_w_lg_nll0i0O0i37506w(0)))) AND (NOT (nlli0iiOi XOR wire_nl1000i_w_lg_nll0i0O0l37510w(0)))) AND (NOT (nlli0iilO XOR wire_nl1000i_w_lg_nll0i0O0O37514w(0)))) AND (NOT (nlli0iill XOR wire_nl1000i_w_lg_nll0i0Oii37518w(0)))) AND (NOT (nlli0illl XOR wire_nl1000i_w_lg_nll0i0Oil37522w(0)))) AND (NOT (nlli0illi XOR wire_nl1000i_w_lg_nll0i0OiO37526w(0)))) AND (NOT (nlli0iliO XOR wire_nl1000i_w_lg_nll0i0Oli37530w(0)))) AND (NOT (nlli0ilil XOR wire_nl1000i_w_lg_nll0i0Oll37534w(0)))) AND (NOT (nlli0ilii XOR wire_nl1000i_w_lg_nll0i0OlO37538w(0)))) AND (NOT (nlli0il0O XOR wire_nl1000i_w_lg_nll0i0OOi37542w(0)))) AND (NOT (nlli0il0l XOR wire_nl1000i_w_lg_nll0i0OOl37546w(0)))) AND (NOT (nlli0il0i XOR wire_nl1000i_w_lg_nll0i0OOO37550w +(0)))); + niOiOi01O <= (wire_nl1000i_w_lg_w36978w36979w(0) AND nlli1Oili); + niOiOi0ii <= ((wire_nl1000i_w_lg_nlli0ilOl36234w(0) AND wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w36235w(0)) OR wire_nlOiOi11i_dataout); + niOiOi0il <= (wire_nl1000i_w_lg_nlli0ilOO5658w(0) AND wire_w_lg_niOiOi0li35985w(0)); + niOiOi0iO <= (wire_nl1000i_w_lg_w_lg_w_lg_nlli0ilOO5658w35983w35984w(0) OR (wire_nl1000i_w_lg_nlli0illO35982w(0) AND wire_nl1000i_w_lg_nlli0ilOO35986w(0))); + niOiOi0li <= ((((((((((wire_nl1000i_w_lg_nlli1OO1i36949w(0) AND wire_nl1000i_w_lg_nlli1OlOO36950w(0)) AND wire_nl1000i_w_lg_nlli1OlOl36952w(0)) AND wire_nl1000i_w_lg_nlli1OlOi36954w(0)) AND wire_nl1000i_w_lg_nlli1OllO36956w(0)) AND wire_nl1000i_w_lg_nlli1Olll36958w(0)) AND wire_nl1000i_w_lg_nlli1Olli36960w(0)) AND wire_nl1000i_w_lg_nlli1OliO36962w(0)) AND wire_nl1000i_w_lg_nlli1Olil36964w(0)) AND wire_nl1000i_w_lg_nlli1Olii36966w(0)) AND wire_nl1000i_w_lg_nlli1Ol0O36969w(0)); + niOiOi0ll <= ((((((((((wire_nl1000i_w_lg_nlli1OO1i36949w(0) AND wire_nl1000i_w_lg_nlli1OlOO36950w(0)) AND wire_nl1000i_w_lg_nlli1OlOl36952w(0)) AND wire_nl1000i_w_lg_nlli1OlOi36954w(0)) AND wire_nl1000i_w_lg_nlli1OllO36956w(0)) AND wire_nl1000i_w_lg_nlli1Olll36958w(0)) AND wire_nl1000i_w_lg_nlli1Olli36960w(0)) AND wire_nl1000i_w_lg_nlli1OliO36962w(0)) AND wire_nl1000i_w_lg_nlli1Olil36964w(0)) AND wire_nl1000i_w_lg_nlli1Olii36966w(0)) AND nlli1Ol0O); + niOiOi0lO <= wire_w_lg_w_k_gbl_hip_range2434w35935w(0); + niOiOi0Oi <= (nlli0illi AND niOiOi0Ol); + niOiOi0Ol <= (((((((((wire_nl1000i_w_lg_nlli0ii0i36930w(0) AND wire_nl1000i_w_lg_nlli0ii1O36931w(0)) AND wire_nl1000i_w_lg_nlli0ii1l36933w(0)) AND wire_nl1000i_w_lg_nlli0ii1i36935w(0)) AND wire_nl1000i_w_lg_nlli0i0OO36937w(0)) AND wire_nl1000i_w_lg_nlli0i0Ol36939w(0)) AND wire_nl1000i_w_lg_nlli0i0Oi36941w(0)) AND wire_nl1000i_w_lg_nlli0i0lO36943w(0)) AND wire_nl1000i_w_lg_nlli0i0ll36945w(0)) AND wire_nl1000i_w_lg_nlli0i0li36947w(0)); + niOiOi0OO <= (nlli0iO1l OR nlli0ilOO); + niOiOi10i <= ((((wire_w_lg_w_lg_niOiOi10l36263w36264w(0) AND wire_nl1000i_w_lg_nll0O0ilO36240w(0)) AND wire_nlOiilO1l_w_lg_w_lg_w_lg_w_lg_dataout9857w9858w9868w9869w(0)) AND wire_nl1000i_w_lg_nll0O0ill36243w(0)) AND nll0O0i1O); + niOiOi10l <= ((((((wire_nl1000i_w_lg_nll0O0ili37704w(0) AND wire_nl1000i_w_lg_nll0O0iiO37705w(0)) AND wire_nl1000i_w_lg_nll0O0iil37707w(0)) AND wire_nl1000i_w_lg_nll0O0iii37709w(0)) AND wire_nl1000i_w_lg_nll0O0i0O36253w(0)) AND wire_nl1000i_w_lg_nll0O0i0l36254w(0)) AND wire_nl1000i_w_lg_nll0O0i0i36246w(0)); + niOiOi10O <= ((((wire_nl1000i_w_lg_w36257w36258w(0) AND wire_nl1000i_w_lg_nll0O0ilO36240w(0)) AND (wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9859w(0) AND wire_nlOiillOl_w_lg_dataout9855w(0))) AND wire_nl1000i_w_lg_nll0O0ill36243w(0)) AND nll0O0i1O); + niOiOi11i <= (nll0OOOlO AND nll0O0i0i); + niOiOi11l <= ((((((((((((NOT wire_nll0O00lO_o(1)) AND (NOT wire_nll0O00lO_o(2))) AND (NOT wire_nll0O00lO_o(3))) AND (NOT wire_nll0O00lO_o(4))) AND (NOT wire_nll0O00lO_o(5))) AND (NOT wire_nll0O00lO_o(6))) AND (NOT wire_nll0O00lO_o(7))) AND (NOT wire_nll0O00lO_o(8))) AND (NOT wire_nll0O00lO_o(9))) AND (NOT wire_nll0O00lO_o(10))) AND (NOT wire_nll0O00lO_o(11))) AND (NOT wire_nll0O00lO_o(12))); + niOiOi11O <= (wire_nl1000i_w_lg_nll0O0iOl5342w(0) AND niOiOi0li); + niOiOi1ii <= ((((wire_nl1000i_w_lg_w_lg_w_lg_nll0O0i0i36246w36247w36248w(0) AND wire_nl1000i_w_lg_nll0O0ilO36240w(0)) AND ((wire_nlOiilO1l_w_lg_w_lg_dataout9857w9862w(0) AND wire_nlOiillOO_w_lg_dataout9853w(0)) AND wire_nlOiillOl_w_lg_dataout9855w(0))) AND wire_nl1000i_w_lg_nll0O0ill36243w(0)) AND nll0O0i1O); + niOiOi1il <= ((((wire_nl1000i_w_lg_nll0O0iOl36239w(0) AND wire_nl1000i_w_lg_nll0O0ilO36240w(0)) AND ((wire_nlOiilO1l_w_lg_dataout9852w(0) AND wire_nlOiillOO_w_lg_dataout9853w(0)) AND wire_nlOiillOl_w_lg_dataout9855w(0))) AND wire_nl1000i_w_lg_nll0O0ill36243w(0)) AND nll0O0i1O); + niOiOi1iO <= ((((((((NOT (nl0OOO1iO XOR nlli0il0i)) AND (NOT (nl0OOO1li XOR nlli0il0l))) AND (NOT (nl0OOO1ll XOR nlli0il0O))) AND (NOT (nl0OOO1lO XOR nlli0ilii))) AND (NOT (nl0OOO1Oi XOR nlli0ilil))) AND (NOT (nl0OOO1Ol XOR nlli0iliO))) AND (NOT (nl0OOO1OO XOR nlli0illi))) AND (NOT (nl0OOO01i XOR nlli0illl))); + niOiOi1li <= ((((((((((((((((((((((((((((((((NOT (nlli0ii1l XOR wire_nl1000i_w_lg_nll11O0ll37205w(0))) AND (NOT (nlli0ii1i XOR wire_nl1000i_w_lg_nll11O0lO37208w(0)))) AND (NOT (nlli0i0OO XOR wire_nl1000i_w_lg_nll11O0Oi37212w(0)))) AND (NOT (nlli0i0Ol XOR wire_nl1000i_w_lg_nll11O0Ol37216w(0)))) AND (NOT (nlli0i0Oi XOR wire_nl1000i_w_lg_nll11O0OO37220w(0)))) AND (NOT (nlli0i0lO XOR wire_nl1000i_w_lg_nll11Oi1i37224w(0)))) AND (NOT (nlli0i0ll XOR wire_nl1000i_w_lg_nll11Oi1l37228w(0)))) AND (NOT (nlli0i0li XOR wire_nl1000i_w_lg_nll11Oi1O37232w(0)))) AND (NOT (nlli0iili XOR wire_nl1000i_w_lg_nll11Oi0i37236w(0)))) AND (NOT (nlli0iiiO XOR wire_nl1000i_w_lg_nll11Oi0l37240w(0)))) AND (NOT (nlli0iiil XOR wire_nl1000i_w_lg_nll11Oi0O37244w(0)))) AND (NOT (nlli0iiii XOR wire_nl1000i_w_lg_nll11Oiii37248w(0)))) AND (NOT (nlli0ii0O XOR wire_nl1000i_w_lg_nll11Oiil37252w(0)))) AND (NOT (nlli0ii0l XOR wire_nl1000i_w_lg_nll11OiiO37256w(0)))) AND (NOT (nlli0ii0i XOR wire_nl1000i_w_lg_nll11Oili37260w(0)))) AND (NOT (nlli0ii1O XOR wire_nl1000i_w_lg_nll11Oill37264w(0)))) AND (NOT (nlli0il1O XOR wire_nl1000i_w_lg_nll11OilO37268w(0)))) AND (NOT (nlli0il1l XOR wire_nl1000i_w_lg_nll11OiOi37272w(0)))) AND (NOT (nlli0il1i XOR wire_nl1000i_w_lg_nll11OiOl37276w(0)))) AND (NOT (nlli0iiOO XOR wire_nl1000i_w_lg_nll11OiOO37280w(0)))) AND (NOT (nlli0iiOl XOR wire_nl1000i_w_lg_nll11Ol1i37284w(0)))) AND (NOT (nlli0iiOi XOR wire_nl1000i_w_lg_nll11Ol1l37288w(0)))) AND (NOT (nlli0iilO XOR wire_nl1000i_w_lg_nll11Ol1O37292w(0)))) AND (NOT (nlli0iill XOR wire_nl1000i_w_lg_nll11Ol0i37296w(0)))) AND (NOT (nlli0illl XOR wire_nl1000i_w_lg_nll11Ol0l37300w(0)))) AND (NOT (nlli0illi XOR wire_nl1000i_w_lg_nll11Ol0O37304w(0)))) AND (NOT (nlli0iliO XOR wire_nl1000i_w_lg_nll11Olii37308w(0)))) AND (NOT (nlli0ilil XOR wire_nl1000i_w_lg_nll11Olil37312w(0)))) AND (NOT (nlli0ilii XOR wire_nl1000i_w_lg_nll11OliO37316w(0)))) AND (NOT (nlli0il0O XOR wire_nl1000i_w_lg_nll11Olli37320w(0)))) AND (NOT (nlli0il0l XOR wire_nl1000i_w_lg_nll11Olll37324w(0)))) AND (NOT (nlli0il0i XOR wire_nl1000i_w_lg_nll11OllO37328w +(0)))); + niOiOi1ll <= ((((((((((((((((((((((((((((((((NOT (nlli11i1l XOR wire_nl1000i_w_lg_nll100Oil36983w(0))) AND (NOT (nlli11lli XOR wire_nl1000i_w_lg_nll11lOli36986w(0)))) AND (NOT (nlli11lll XOR wire_nl1000i_w_lg_nll11lOll36990w(0)))) AND (NOT (nlli11llO XOR wire_nl1000i_w_lg_nll11lOlO36994w(0)))) AND (NOT (nlli11lOi XOR wire_nl1000i_w_lg_nll11lOOi36998w(0)))) AND (NOT (nlli11lOl XOR wire_nl1000i_w_lg_nll11lOOl37002w(0)))) AND (NOT (nlli11lOO XOR wire_nl1000i_w_lg_nll11lOOO37006w(0)))) AND (NOT (nlli11O1i XOR wire_nl1000i_w_lg_nll11O11i37010w(0)))) AND (NOT (nlli11O1l XOR wire_nl1000i_w_lg_nll11O11l37014w(0)))) AND (NOT (nlli11O1O XOR wire_nl1000i_w_lg_nll11O11O37018w(0)))) AND (NOT (nlli11O0i XOR wire_nl1000i_w_lg_nll11O10i37022w(0)))) AND (NOT (nlli11O0l XOR wire_nl1000i_w_lg_nll11O10l37026w(0)))) AND (NOT (nlli11O0O XOR wire_nl1000i_w_lg_nll11O10O37030w(0)))) AND (NOT (nlli11Oii XOR wire_nl1000i_w_lg_nll11O1ii37034w(0)))) AND (NOT (nlli11Oil XOR wire_nl1000i_w_lg_nll11O1il37038w(0)))) AND (NOT (nlli11OiO XOR wire_nl1000i_w_lg_nll11O1iO37042w(0)))) AND (NOT (nlli11Oli XOR wire_nl1000i_w_lg_nll11O1li37046w(0)))) AND (NOT (nlli11Oll XOR wire_nl1000i_w_lg_nll11O1ll37050w(0)))) AND (NOT (nlli11OlO XOR wire_nl1000i_w_lg_nll11O1lO37054w(0)))) AND (NOT (nlli11OOi XOR wire_nl1000i_w_lg_nll11O1Oi37058w(0)))) AND (NOT (nlli11OOl XOR wire_nl1000i_w_lg_nll11O1Ol37062w(0)))) AND (NOT (nlli11OOO XOR wire_nl1000i_w_lg_nll11O1OO37066w(0)))) AND (NOT (nlli1011i XOR wire_nl1000i_w_lg_nll11O01i37070w(0)))) AND (NOT (nlli1011l XOR wire_nl1000i_w_lg_nll11O01l37074w(0)))) AND (NOT (nlli1011O XOR wire_nl1000i_w_lg_nll11O01O37078w(0)))) AND (NOT (nlli1010i XOR wire_nl1000i_w_lg_nll11O00i37082w(0)))) AND (NOT (nlli1010l XOR wire_nl1000i_w_lg_nll11O00l37086w(0)))) AND (NOT (nlli1010O XOR wire_nl1000i_w_lg_nll11O00O37090w(0)))) AND (NOT (nlli101ii XOR wire_nl1000i_w_lg_nll11O0ii37094w(0)))) AND (NOT (nlli101il XOR wire_nl1000i_w_lg_nll11O0il37098w(0)))) AND (NOT (nlli101iO XOR wire_nl1000i_w_lg_nll11O0iO37102w(0)))) AND (NOT (nlli101li XOR wire_nl1000i_w_lg_nll11O0li37106w +(0)))); + niOiOi1lO <= (wire_nl1000i_w_lg_nlli0i1Ol36193w(0) OR wire_nl1000i_w_lg_nlli0i1Oi36195w(0)); + niOiOi1Oi <= ((((((((((((((((((((((((((((((((NOT (nlli0ii1l XOR nll11O0ll)) AND (NOT (nlli0ii1i XOR nll11O0lO))) AND (NOT (nlli0i0OO XOR nll11O0Oi))) AND (NOT (nlli0i0Ol XOR nll11O0Ol))) AND (NOT (nlli0i0Oi XOR nll11O0OO))) AND (NOT (nlli0i0lO XOR nll11Oi1i))) AND (NOT (nlli0i0ll XOR nll11Oi1l))) AND (NOT (nlli0i0li XOR nll11Oi1O))) AND (NOT (nlli0iili XOR nll11Oi0i))) AND (NOT (nlli0iiiO XOR nll11Oi0l))) AND (NOT (nlli0iiil XOR nll11Oi0O))) AND (NOT (nlli0iiii XOR nll11Oiii))) AND (NOT (nlli0ii0O XOR nll11Oiil))) AND (NOT (nlli0ii0l XOR nll11OiiO))) AND (NOT (nlli0ii0i XOR nll11Oili))) AND (NOT (nlli0ii1O XOR nll11Oill))) AND (NOT (nlli0il1O XOR nll11OilO))) AND (NOT (nlli0il1l XOR nll11OiOi))) AND (NOT (nlli0il1i XOR nll11OiOl))) AND (NOT (nlli0iiOO XOR nll11OiOO))) AND (NOT (nlli0iiOl XOR nll11Ol1i))) AND (NOT (nlli0iiOi XOR nll11Ol1l))) AND (NOT (nlli0iilO XOR nll11Ol1O))) AND (NOT (nlli0iill XOR nll11Ol0i))) AND (NOT (nlli0illl XOR nll11Ol0l))) AND (NOT (nlli0illi XOR nll11Ol0O))) AND (NOT (nlli0iliO XOR nll11Olii))) AND (NOT (nlli0ilil XOR nll11Olil))) AND (NOT (nlli0ilii XOR nll11OliO))) AND (NOT (nlli0il0O XOR nll11Olli))) AND (NOT (nlli0il0l XOR nll11Olll))) AND (NOT (nlli0il0i XOR nll11OllO))); + niOiOi1Ol <= ((((((((((((((((((((((((((((((((NOT (nlli11i1l XOR nll100Oil)) AND (NOT (nlli11lli XOR nll11lOli))) AND (NOT (nlli11lll XOR nll11lOll))) AND (NOT (nlli11llO XOR nll11lOlO))) AND (NOT (nlli11lOi XOR nll11lOOi))) AND (NOT (nlli11lOl XOR nll11lOOl))) AND (NOT (nlli11lOO XOR nll11lOOO))) AND (NOT (nlli11O1i XOR nll11O11i))) AND (NOT (nlli11O1l XOR nll11O11l))) AND (NOT (nlli11O1O XOR nll11O11O))) AND (NOT (nlli11O0i XOR nll11O10i))) AND (NOT (nlli11O0l XOR nll11O10l))) AND (NOT (nlli11O0O XOR nll11O10O))) AND (NOT (nlli11Oii XOR nll11O1ii))) AND (NOT (nlli11Oil XOR nll11O1il))) AND (NOT (nlli11OiO XOR nll11O1iO))) AND (NOT (nlli11Oli XOR nll11O1li))) AND (NOT (nlli11Oll XOR nll11O1ll))) AND (NOT (nlli11OlO XOR nll11O1lO))) AND (NOT (nlli11OOi XOR nll11O1Oi))) AND (NOT (nlli11OOl XOR nll11O1Ol))) AND (NOT (nlli11OOO XOR nll11O1OO))) AND (NOT (nlli1011i XOR nll11O01i))) AND (NOT (nlli1011l XOR nll11O01l))) AND (NOT (nlli1011O XOR nll11O01O))) AND (NOT (nlli1010i XOR nll11O00i))) AND (NOT (nlli1010l XOR nll11O00l))) AND (NOT (nlli1010O XOR nll11O00O))) AND (NOT (nlli101ii XOR nll11O0ii))) AND (NOT (nlli101il XOR nll11O0il))) AND (NOT (nlli101iO XOR nll11O0iO))) AND (NOT (nlli101li XOR nll11O0li))); + niOiOi1OO <= ((((((((((((((((((((((((((((((((NOT (nlli11i1l XOR wire_nl1000i_w_lg_nll0iO1lO37554w(0))) AND (NOT (nlli11lli XOR wire_nl1000i_w_lg_nll0i01Oi37557w(0)))) AND (NOT (nlli11lll XOR wire_nl1000i_w_lg_nll0i01Ol37561w(0)))) AND (NOT (nlli11llO XOR wire_nl1000i_w_lg_nll0i01OO37565w(0)))) AND (NOT (nlli11lOi XOR wire_nl1000i_w_lg_nll0i001i37569w(0)))) AND (NOT (nlli11lOl XOR wire_nl1000i_w_lg_nll0i001l37573w(0)))) AND (NOT (nlli11lOO XOR wire_nl1000i_w_lg_nll0i001O37577w(0)))) AND (NOT (nlli11O1i XOR wire_nl1000i_w_lg_nll0i000i37581w(0)))) AND (NOT (nlli11O1l XOR wire_nl1000i_w_lg_nll0i000l37585w(0)))) AND (NOT (nlli11O1O XOR wire_nl1000i_w_lg_nll0i000O37589w(0)))) AND (NOT (nlli11O0i XOR wire_nl1000i_w_lg_nll0i00ii37593w(0)))) AND (NOT (nlli11O0l XOR wire_nl1000i_w_lg_nll0i00il37597w(0)))) AND (NOT (nlli11O0O XOR wire_nl1000i_w_lg_nll0i00iO37601w(0)))) AND (NOT (nlli11Oii XOR wire_nl1000i_w_lg_nll0i00li37605w(0)))) AND (NOT (nlli11Oil XOR wire_nl1000i_w_lg_nll0i00ll37609w(0)))) AND (NOT (nlli11OiO XOR wire_nl1000i_w_lg_nll0i00lO37613w(0)))) AND (NOT (nlli11Oli XOR wire_nl1000i_w_lg_nll0i00Oi37617w(0)))) AND (NOT (nlli11Oll XOR wire_nl1000i_w_lg_nll0i00Ol37621w(0)))) AND (NOT (nlli11OlO XOR wire_nl1000i_w_lg_nll0i00OO37625w(0)))) AND (NOT (nlli11OOi XOR wire_nl1000i_w_lg_nll0i0i1i37629w(0)))) AND (NOT (nlli11OOl XOR wire_nl1000i_w_lg_nll0i0i1l37633w(0)))) AND (NOT (nlli11OOO XOR wire_nl1000i_w_lg_nll0i0i1O37637w(0)))) AND (NOT (nlli1011i XOR wire_nl1000i_w_lg_nll0i0i0i37641w(0)))) AND (NOT (nlli1011l XOR wire_nl1000i_w_lg_nll0i0i0l37645w(0)))) AND (NOT (nlli1011O XOR wire_nl1000i_w_lg_nll0i0i0O37649w(0)))) AND (NOT (nlli1010i XOR wire_nl1000i_w_lg_nll0i0iii37653w(0)))) AND (NOT (nlli1010l XOR wire_nl1000i_w_lg_nll0i0iil37657w(0)))) AND (NOT (nlli1010O XOR wire_nl1000i_w_lg_nll0i0iiO37661w(0)))) AND (NOT (nlli101ii XOR wire_nl1000i_w_lg_nll0i0ili37665w(0)))) AND (NOT (nlli101il XOR wire_nl1000i_w_lg_nll0i0ill37669w(0)))) AND (NOT (nlli101iO XOR wire_nl1000i_w_lg_nll0i0ilO37673w(0)))) AND (NOT (nlli101li XOR wire_nl1000i_w_lg_nll0i0iOi37677w +(0)))); + niOiOii0i <= (niOiOii0O AND nlliiilOl); + niOiOii0l <= ((wire_nl1000i_w_lg_w_lg_w_lg_nllilil0l35858w35860w36926w(0) AND wire_nl1000i_w_lg_nllilil1l36927w(0)) AND wire_nl1000i_w_lg_nllilil1i35863w(0)); + niOiOii0O <= ((NOT ((wire_w_lg_niOiOiili35848w(0) OR wire_w_lg_niOiOiiiO35851w(0)) OR wire_w_lg_niOiOiiil35854w(0))) AND niOiOiiii); + niOiOii1i <= (wire_nl1000i_w_lg_w_lg_nlli0i01i35924w35925w(0) OR wire_nl1000i_w_lg_w_lg_nlli0i1OO35926w35927w(0)); + niOiOii1l <= (nllilOlOl OR nlli0ilOi); + niOiOii1O <= (niOiOiO0O OR nllilOlOl); + niOiOiiii <= ((((((((((((((((NOT (nllili11O XOR (nllili0ii XOR (nllili00l XOR (nllili00i XOR (nllilii0i XOR (nllilii1l XOR (nllilii1i XOR (nllili0OO XOR (nllili0Oi XOR (nllili0lO XOR (nlliliilO XOR (nlliliill XOR (nlliliili XOR (nlliliiiO XOR (nlliliiil XOR (nlliliiii XOR (nllilii0O XOR (nllilil0l XOR (nllilil0i XOR (nllilil1O XOR (nllilil1l XOR (nllilil1i XOR nlliliiOO))))))))))))))))))))))) AND (NOT (nllili10i XOR (NOT (nllili0il XOR (nllili00O XOR (nllili00l XOR (nllili00i XOR (nllilii1O XOR (nllilii1l XOR (nllilii1i XOR (nllili0Ol XOR (nllili0Oi XOR (nllili0lO XOR (nlliliilO XOR (nlliliill XOR (nlliliili XOR (nlliliiiO XOR (nlliliiil XOR (nlliliiii XOR (nllilii0l XOR (nllilil0l XOR (nllilil0i XOR (nllilil1O XOR (nllilil1l XOR nllilil1i))))))))))))))))))))))))) AND (NOT (nllili10l XOR (nllili0iO XOR (nllili0ii XOR (nllili00O XOR (nllili00l XOR (nllilii0i XOR (nllilii1O XOR (nllilii1l XOR (nllili0OO XOR (nllili0Ol XOR (nllili0Oi XOR (nllili0lO XOR (nlliliilO XOR (nlliliill XOR (nlliliili XOR (nlliliiiO XOR (nlliliiil XOR (nllilii0O XOR (nllilii0l XOR (nllilil0l XOR (nllilil0i XOR (nllilil1O XOR nllilil1l)))))))))))))))))))))))) AND (NOT (nllili10O XOR (nllili0li XOR (nllili0il XOR (nllili0ii XOR (nllili00O XOR (nllili00i XOR (nllilii0i XOR (nllilii1O XOR (nllilii1i XOR (nllili0OO XOR (nllili0Ol XOR (nllili0Oi XOR (nllili0lO XOR (nlliliilO XOR (nlliliill XOR (nlliliili XOR (nlliliiiO XOR (nlliliiii XOR (nllilii0O XOR (nllilii0l XOR (nllilil0l XOR (nllilil0i XOR (nllilil1O XOR nlliliiOi))))))))))))))))))))))))) AND (NOT (nllili1ii XOR (nllili0ll XOR (nllili0iO XOR (nllili0il XOR (nllili0ii XOR (nllili00l XOR (nllili00i XOR (nllilii0i XOR (nllilii1l XOR (nllilii1i XOR (nllili0OO XOR (nllili0Ol XOR (nllili0Oi XOR (nllili0lO XOR (nlliliilO XOR (nlliliill XOR (nlliliili XOR (nlliliiil XOR (nlliliiii XOR (nllilii0O XOR (nllilii0l XOR (nllilil0l XOR (nllilil0i XOR niOiOil1i))))))))))))))))))))))))) AND (NOT (nllili1il XOR (NOT (nllili0li XOR (nllili0iO XOR (nllili00O XOR (nllili00l XOR (nllilii1O XOR (nllilii1l XOR (nllili0Ol + XOR (nllili0lO XOR (nlliliilO XOR (nlliliill XOR (nlliliiii XOR (nllilii0l XOR (nllilil0l XOR (nllilil0i XOR (nllilil1l XOR niOiOiiOi))))))))))))))))))) AND (NOT (nllili1iO XOR (NOT (nllili0ll XOR (nllili0li XOR (nllili0ii XOR (nllili00O XOR (nllilii0i XOR (nllilii1O XOR (nllili0OO XOR (nllili0Oi XOR (nllili0lO XOR (nlliliilO XOR (nlliliiil XOR (nllilii0O XOR (nllilii0l XOR (nllilil0l XOR (nllilil1O XOR niOiOiill))))))))))))))))))) AND (NOT (nllili1li XOR (nllili0ll XOR (nllili0ii XOR (nllilii0i XOR (nllili0OO XOR (nllili0Ol XOR (nllili0lO XOR (nlliliiil XOR (nlliliiii XOR (nllilii0l XOR niOiOiilO)))))))))))) AND (NOT (nllili1ll XOR (NOT (nllili0il XOR (nllili00i XOR (nllilii1i XOR (nllili0OO XOR (nllili0Oi XOR (nlliliiiO XOR (nlliliiil XOR (nllilii0O XOR (nllilil0i XOR niOiOiill))))))))))))) AND (NOT (nllili1lO XOR (NOT (nllili0iO XOR (nllili00l XOR (nllilii1l XOR (nllilii1i XOR (nllili0Ol XOR (nlliliili XOR (nlliliiiO XOR (nlliliiii XOR (nllilil0l XOR (nllilil1O XOR (nllilil1l XOR niOiOil1l))))))))))))))) AND (NOT (nllili1Oi XOR (nllili0li XOR (nllili00O XOR (nllilii1O XOR (nllilii1l XOR (nllili0OO XOR (nlliliill XOR (nlliliili XOR (nlliliiil XOR (nllilii0l XOR (nllilil0i XOR niOiOiilO))))))))))))) AND (NOT (nllili1Ol XOR (nllili0ll XOR (nllili0ii XOR (nllilii0i XOR (nllilii1O XOR (nllilii1i XOR (nlliliilO XOR (nlliliill XOR (nlliliiiO XOR (nllilii0O XOR (nllilil0l XOR (nllilil0i XOR (nllilil1l XOR (nllilil1i XOR nlliliiOl)))))))))))))))) AND (NOT (nllili1OO XOR (NOT (nllilii0i XOR (nllilii1l XOR (nllilii1i XOR (nllili0OO XOR (nllili0Oi XOR (nllili0lO XOR (nlliliilO XOR (nlliliili XOR (nlliliiiO XOR (nlliliiil XOR (nlliliiii XOR (nllilii0O XOR (nllilii0l XOR (nllilil0l XOR (nllilil0i XOR (nllilil1O XOR niOiOiiOO)))))))))))))))))))) AND (NOT (nllili01i XOR (NOT (nllili00i XOR (nllilii1O XOR (nllilii1l XOR (nllilii1i XOR (nllili0Ol XOR (nllili0Oi XOR (nllili0lO XOR (nlliliill XOR (nlliliili XOR (nlliliiiO XOR (nlliliiil XOR (nlliliiii XOR (nllilii0O XOR (nllilii0l XOR (nllilil0l XOR (nllilil0i XOR niOiOiiOl))))) +))))))))))))))) AND (NOT (nllili01l XOR (nllili00l XOR (nllilii0i XOR (nllilii1O XOR (nllilii1l XOR (nllili0OO XOR (nllili0Ol XOR (nllili0Oi XOR (nlliliilO XOR (nlliliill XOR (nlliliili XOR (nlliliiiO XOR (nlliliiil XOR (nlliliiii XOR (nllilii0O XOR (nllilii0l XOR (nllilil0l XOR (nllilil1O XOR niOiOiiOl)))))))))))))))))))) AND (NOT (nllili01O XOR (NOT (nllili00O XOR (nllili00i XOR (nllilii0i XOR (nllilii1O XOR (nllilii1i XOR (nllili0OO XOR (nllili0Ol XOR (nllili0lO XOR (nlliliilO XOR (nlliliill XOR (nlliliili XOR (nlliliiiO XOR (nlliliiil XOR (nlliliiii XOR (nllilii0O XOR (nllilii0l XOR (nllilil0i XOR (nllilil1O XOR (nllilil1l XOR (nllilil1i XOR niOiOil1l)))))))))))))))))))))))); + niOiOiiil <= ((wire_nl1000i_w_lg_nllilil1i35863w(0) AND (NOT wire_nl1000i_w_lg_w_lg_nllilil0l35858w35860w(0))) AND (NOT (nllilil1O AND nllilil1l))); + niOiOiiiO <= ((wire_w_lg_niOiOii0l35874w(0) AND (NOT ((nlliliiOO AND nlliliiOl) AND wire_nl1000i_w_lg_nlliliiOi35868w(0)))) AND (NOT ((nlliliiOO AND nlliliiOl) AND nlliliiOi))); + niOiOiili <= ((wire_nl1000i_w_lg_w_lg_nllilil0l35858w35860w(0) AND wire_nl1000i_w_lg_nllilil1O35861w(0)) AND (((wire_nl1000i_w_lg_nllilil1i35863w(0) AND wire_nl1000i_w_lg_nlliliiOO35864w(0)) AND wire_nl1000i_w_lg_nlliliiOl35866w(0)) AND wire_nl1000i_w_lg_nlliliiOi35868w(0))); + niOiOiill <= (nllilil1l XOR (nllilil1i XOR niOiOil1i)); + niOiOiilO <= (nllilil1O XOR niOiOiiOi); + niOiOiiOi <= (nllilil1i XOR (nlliliiOO XOR nlliliiOi)); + niOiOiiOl <= (nllilil1l XOR niOiOiiOO); + niOiOiiOO <= (nllilil1i XOR (nlliliiOO XOR niOiOil1i)); + niOiOil0i <= (niOiOilOi OR niOiOiliO); + niOiOil0l <= ((wire_w_lg_w35817w35818w(0) OR wire_w_lg_w_lg_w_lg_niOiOilil35819w35821w35822w(0)) AND wire_nlOiOi11i_dataout); + niOiOil0O <= ((wire_w_lg_w35805w35806w(0) OR wire_w_lg_w_lg_w_lg_niOiOilli35807w35809w35810w(0)) AND wire_nlOiOi11i_dataout); + niOiOil1i <= (nlliliiOl XOR nlliliiOi); + niOiOil1l <= (nlliliiOO XOR nlliliiOl); + niOiOil1O <= (nllilOllO OR nllilOlll); + niOiOilii <= ((niOiOilil AND wire_nlOiO010i_dataout) AND wire_nlOiOi11i_dataout); + niOiOilil <= ((wire_nlOiO000i_w_lg_w36605w36606w(0) AND wire_nlOiO01Oi_w_lg_dataout36607w(0)) AND wire_nlOiO01lO_dataout); + niOiOiliO <= ((niOiOilli AND wire_nlOiO01il_dataout) AND wire_nlOiOi11i_dataout); + niOiOilli <= ((wire_nlOiO0l0O_w_lg_w36575w36576w(0) AND wire_nlOiO0iOO_w_lg_dataout36577w(0)) AND wire_nlOiO0iOl_dataout); + niOiOilll <= ((niOiOillO AND wire_nlOiO010i_dataout) AND wire_nlOiOi11i_dataout); + niOiOillO <= (wire_nlOiO000i_w_lg_w_lg_w36605w36606w36610w(0) AND wire_nlOiO01lO_w_lg_dataout36611w(0)); + niOiOilOi <= ((niOiOilOl AND wire_nlOiO01il_dataout) AND wire_nlOiOi11i_dataout); + niOiOilOl <= (wire_nlOiO0l0O_w_lg_w_lg_w36575w36576w36580w(0) AND wire_nlOiO0iOl_w_lg_dataout36581w(0)); + niOiOilOO <= ((niOiOiO1i AND wire_nlOiO01ii_dataout) AND wire_nlOiOi11i_dataout); + niOiOiO0i <= ((niOiOiO0l AND wire_nlOiO01ii_dataout) AND wire_nlOiOi11i_dataout); + niOiOiO0l <= (((wire_nlOiO0iOi_w36586w(0) AND wire_nlOiO0iil_w_lg_dataout36587w(0)) AND wire_nlOiO0iii_dataout) AND wire_nlOiO0i0O_dataout); + niOiOiO0O <= ((niOiOiOii AND wire_nlOiO01ll_dataout) AND wire_nlOiOi11i_dataout); + niOiOiO1i <= ((wire_nlOiO0iOi_w_lg_w_lg_w36595w36596w36597w(0) AND wire_nlOiO0iii_w_lg_dataout36598w(0)) AND wire_nlOiO0i0O_w_lg_dataout36600w(0)); + niOiOiO1l <= ((niOiOiO1O AND wire_nlOiO01ll_dataout) AND wire_nlOiOi11i_dataout); + niOiOiO1O <= ((wire_nlOiO0OOO_w_lg_w_lg_w36565w36566w36567w(0) AND wire_nlOiO0OiO_w_lg_dataout36568w(0)) AND wire_nlOiO0Oil_w_lg_dataout36570w(0)); + niOiOiOii <= (((wire_nlOiO0OOO_w36556w(0) AND wire_nlOiO0Oli_w_lg_dataout36557w(0)) AND wire_nlOiO0OiO_dataout) AND wire_nlOiO0Oil_dataout); + niOiOiOil <= (niOiOiOiO AND wire_nl1000i_w_lg_nll0O10OO35783w(0)); + niOiOiOiO <= (nll0OOOlO AND wire_nl1000i_w_lg_nll0O1i1i35781w(0)); + niOiOiOli <= (nll0OOOlO AND nll0O1i1i); + niOiOiOll <= (nll0OOOOi AND nll0O0i0i); + niOiOiOlO <= (wire_nl1000i_w_lg_nlll1OO0O966w(0) AND nlll1ilil); + niOiOiOOi <= (((((((NOT (k_rtry(1) XOR nlll1llOO)) AND (NOT (k_rtry(2) XOR nlll1lO1i))) AND (NOT (k_rtry(3) XOR nlll1lO1l))) AND (NOT (k_rtry(4) XOR nlll1lO1O))) AND (NOT (k_rtry(5) XOR nlll1lO0i))) AND (NOT (k_rtry(6) XOR nlll1lO0l))) AND (NOT (k_rtry(7) XOR nlll1lO0O))); + niOiOiOOl <= (wire_nl1000i_w_lg_nlliOl11l35175w(0) AND wire_w_lg_niOO1li0i35176w(0)); + niOiOiOOO <= (niOiOl11i AND niOiOl11l); + niOiOl00i <= (nlll1ilii AND (nlll010OO AND nlll010Ol)); + niOiOl00l <= (wire_nl1000i_w_lg_nlilOO0iO5228w(0) OR niOiOl0Oi); + niOiOl00O <= ((nlll0101O AND wire_nlOii0OOO_w_lg_dataout34636w(0)) AND wire_nlOilOiiO_dataout); + niOiOl01i <= (wire_w_lg_niOO000ll4352w(0) AND wire_nlOl1l0Ol_dataout); + niOiOl01l <= (nlll1il0O AND wire_w_lg_niOO000ll4352w(0)); + niOiOl01O <= (niOO000Oi AND wire_nlOl1l0Ol_dataout); + niOiOl0ii <= ((wire_nl1000i_w_lg_nlilOO0iO5228w(0) OR (niOiOl0Oi OR niOiOl0ll)) OR nlll1ilii); + niOiOl0il <= ((((((((((((NOT (wire_nlll0lOli_o(1) XOR nlll0iO1i)) AND (NOT (wire_nlll0lOli_o(2) XOR nlll0iO1l))) AND (NOT (wire_nlll0lOli_o(3) XOR nlll0iO1O))) AND (NOT (wire_nlll0lOli_o(4) XOR nlll0iO0i))) AND (NOT (wire_nlll0lOli_o(5) XOR nlll0iO0l))) AND (NOT (wire_nlll0lOli_o(6) XOR nlll0iO0O))) AND (NOT (wire_nlll0lOli_o(7) XOR nlll0iOii))) AND (NOT (wire_nlll0lOli_o(8) XOR nlll0iOil))) AND (NOT (wire_nlll0lOli_o(9) XOR nlll0iOiO))) AND (NOT (wire_nlll0lOli_o(10) XOR nlll0iOli))) AND (NOT (wire_nlll0lOli_o(11) XOR nlll0iOll))) AND (NOT (wire_nlll0lOli_o(12) XOR nlll0iOlO))); + niOiOl0iO <= (wire_nl1000i_w_lg_nlll1OO0O966w(0) AND nlO1O0O0i); + niOiOl0li <= (nlll00l1i AND nlll1ilil); + niOiOl0ll <= (niOiOl0lO AND wire_nlOilOiiO_dataout); + niOiOl0lO <= ((((((((((NOT (nil1100i XOR nlll0100i)) AND (NOT (nil1100l XOR nlll0100l))) AND (NOT (nil1100O XOR nlll0100O))) AND (NOT (nil110ii XOR nlll010ii))) AND (NOT (nil110il XOR nlll010il))) AND (NOT (nil110iO XOR nlll010iO))) AND (NOT (nil110li XOR nlll010li))) AND (NOT (nil110ll XOR nlll010ll))) AND (NOT (nil110lO XOR nlll010lO))) AND (NOT (nil110Oi XOR nlll010Oi))); + niOiOl0Oi <= (nlll0iOOl AND niOiOl0Ol); + niOiOl0Ol <= (wire_nl1000i_w_lg_nlll0iOOO34563w(0) AND nlll0ilOO); + niOiOl0OO <= ((((((((((((NOT wire_nlll0lOiO_o(1)) AND (NOT wire_nlll0lOiO_o(2))) AND (NOT wire_nlll0lOiO_o(3))) AND (NOT wire_nlll0lOiO_o(4))) AND (NOT wire_nlll0lOiO_o(5))) AND (NOT wire_nlll0lOiO_o(6))) AND (NOT wire_nlll0lOiO_o(7))) AND (NOT wire_nlll0lOiO_o(8))) AND (NOT wire_nlll0lOiO_o(9))) AND (NOT wire_nlll0lOiO_o(10))) AND (NOT wire_nlll0lOiO_o(11))) AND (NOT wire_nlll0lOiO_o(12))); + niOiOl10i <= ((((((((NOT (k_rtry(0) XOR wire_nlliO0lOi_q(0))) AND (NOT (k_rtry(1) XOR wire_nlliO0lOi_q(1)))) AND (NOT (k_rtry(2) XOR wire_nlliO0lOi_q(2)))) AND (NOT (k_rtry(3) XOR wire_nlliO0lOi_q(3)))) AND (NOT (k_rtry(4) XOR wire_nlliO0lOi_q(4)))) AND (NOT (k_rtry(5) XOR wire_nlliO0lOi_q(5)))) AND (NOT (k_rtry(6) XOR wire_nlliO0lOi_q(6)))) AND (NOT (k_rtry(7) XOR wire_nlliO0lOi_q(7)))); + niOiOl10l <= (nlll1ilil OR nlll1il1l); + niOiOl10O <= ((nlll1ilii OR nlll1il0l) OR nlll1il1l); + niOiOl11i <= (nlll11O1l OR (niOl11OOl AND wire_nlOl1l0Ol_dataout)); + niOiOl11l <= ((((((((NOT (k_rtry(0) XOR nlliOOlii)) AND (NOT (k_rtry(1) XOR nlliOOlil))) AND (NOT (k_rtry(2) XOR nlliOOliO))) AND (NOT (k_rtry(3) XOR nlliOOlli))) AND (NOT (k_rtry(4) XOR nlliOOlll))) AND (NOT (k_rtry(5) XOR nlliOOllO))) AND (NOT (k_rtry(6) XOR nlliOOlOi))) AND (NOT (k_rtry(7) XOR nlliOOlOl))); + niOiOl11O <= ((((((((NOT (k_rtry(0) XOR nlliOli1l)) AND (NOT (k_rtry(1) XOR nlliOOiOO))) AND (NOT (k_rtry(2) XOR nlliOOl1i))) AND (NOT (k_rtry(3) XOR nlliOOl1l))) AND (NOT (k_rtry(4) XOR nlliOOl1O))) AND (NOT (k_rtry(5) XOR nlliOOl0i))) AND (NOT (k_rtry(6) XOR nlliOOl0l))) AND (NOT (k_rtry(7) XOR nlliOOl0O))); + niOiOl1ii <= ((((((((((((NOT (nlll00i0i XOR nlll11l0l)) AND (NOT (nlll00i0l XOR nlll11l0O))) AND (NOT (nlll00i0O XOR nlll11lii))) AND (NOT (nlll00iii XOR nlll11lil))) AND (NOT (nlll00iil XOR nlll11liO))) AND (NOT (nlll00iiO XOR nlll11lli))) AND (NOT (nlll00ili XOR nlll11lll))) AND (NOT (nlll00ill XOR nlll11llO))) AND (NOT (nlll00ilO XOR nlll11lOi))) AND (NOT (nlll00iOi XOR nlll11lOl))) AND (NOT (nlll00iOl XOR nlll11lOO))) AND (NOT (nlll00iOO XOR nlll11O1i))); + niOiOl1il <= (wire_w_lg_niOl11OOl34628w(0) AND wire_nlOl1l0Ol_dataout); + niOiOl1iO <= (niOl1011i AND wire_nlOl1l0Ol_dataout); + niOiOl1li <= (nlll1OO0O OR (nlll1OOii AND wire_w_lg_niOO000ll4352w(0))); + niOiOl1ll <= (nlilOO0iO AND niOiOl0li); + niOiOl1lO <= (wire_nl1000i_w_lg_nlll1OO0O966w(0) AND nlO1O0O0i); + niOiOl1Oi <= (wire_nilO0OOO_dataout AND (wire_nl11llO_w_lg_nlll1OOii34761w(0) OR nlll1OO0O)); + niOiOl1Ol <= ((((((((NOT (k_rtry(0) XOR nlll1llOl)) AND (NOT (k_rtry(1) XOR nlll1llOO))) AND (NOT (k_rtry(2) XOR nlll1lO1i))) AND (NOT (k_rtry(3) XOR nlll1lO1l))) AND (NOT (k_rtry(4) XOR nlll1lO1O))) AND (NOT (k_rtry(5) XOR nlll1lO0i))) AND (NOT (k_rtry(6) XOR nlll1lO0l))) AND (NOT (k_rtry(7) XOR nlll1lO0O))); + niOiOl1OO <= (wire_nl11llO_w_lg_w_lg_nlll1OOii34722w34723w(0) OR wire_nilO0OOO_w_lg_w_lg_dataout34724w34725w(0)); + niOiOli0i <= (wire_nlll0lOil_o(12) OR wire_nlll0lOii_o); + niOiOli0l <= (wire_nlO0i0i1i_dataout XOR niOiOlO1l); + niOiOli0O <= (wire_nlO0i00OO_dataout XOR wire_nlO0i00Oi_dataout); + niOiOli1i <= ((((((((((((NOT wire_nlll0lOil_o(1)) AND (NOT wire_nlll0lOil_o(2))) AND (NOT wire_nlll0lOil_o(3))) AND (NOT wire_nlll0lOil_o(4))) AND (NOT wire_nlll0lOil_o(5))) AND (NOT wire_nlll0lOil_o(6))) AND (NOT wire_nlll0lOil_o(7))) AND (NOT wire_nlll0lOil_o(8))) AND (NOT wire_nlll0lOil_o(9))) AND (NOT wire_nlll0lOil_o(10))) AND (NOT wire_nlll0lOil_o(11))) AND (NOT wire_nlll0lOil_o(12))); + niOiOli1l <= (wire_nl1000i_w_lg_nlliiil0l34446w(0) AND wire_nl1000i_w_lg_niOOi1iii34492w(0)); + niOiOli1O <= (wire_nl1000i_w_lg_nlliiil0l34446w(0) AND (niOOi1iii AND niOOi1i0O)); + niOiOliii <= (wire_nlO0i00Ol_dataout XOR wire_nlO0i00Oi_dataout); + niOiOliil <= (wire_nlO0i0i1l_dataout XOR wire_nlO0i00Oi_dataout); + niOiOliiO <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00Ol_dataout); + niOiOlili <= (wire_nlO0i0i1O_dataout XOR niOiOllOi); + niOiOlill <= (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOlO1O))); + niOiOlilO <= (wire_nlO0i0i1l_dataout XOR niOiOliOO); + niOiOliOi <= (wire_nlO0i0i0i_dataout XOR niOiOll1O); + niOiOliOl <= (wire_nlO0i0i1l_dataout XOR niOiOli0O); + niOiOliOO <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00Oi_dataout); + niOiOll0i <= (wire_nlO0i0i1l_dataout XOR wire_nlO0i00OO_dataout); + niOiOll0l <= (wire_nlO0i0i1l_dataout XOR wire_nlO0i0i1i_dataout); + niOiOll0O <= (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOliiO))); + niOiOll1i <= (wire_nlO0i0i1l_dataout XOR niOiOliii); + niOiOll1l <= (wire_nlO0i0i1O_dataout XOR niOiOliOO); + niOiOll1O <= (wire_nlO0i0i1O_dataout XOR wire_nlO0i0i1l_dataout); + niOiOllii <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00OO_dataout); + niOiOllil <= (wire_nlO0i00OO_dataout XOR wire_nlO0i00Ol_dataout); + niOiOlliO <= (wire_nlO0i000l_dataout XOR niOiOlO0i); + niOiOllli <= (wire_nlO0i0i1i_dataout XOR niOiOllil); + niOiOllll <= (wire_nlO0i0i1O_dataout XOR niOiOliOl); + niOiOlllO <= (wire_nlO0i0i1l_dataout XOR niOiOliiO); + niOiOllOi <= (wire_nlO0i0i1i_dataout XOR niOiOli0O); + niOiOllOl <= (wire_nlO0i0i1O_dataout XOR niOiOllil); + niOiOllOO <= (wire_nlO0i0i1l_dataout XOR niOiOllli); + niOiOlO0i <= (wire_nlO0i0i0l_dataout XOR niOiOllll); + niOiOlO0l <= (wire_nlO0i0i0i_dataout XOR niOiOlllO); + niOiOlO0O <= (wire_nlO0i00Ol_dataout XOR niOiOO1il); + niOiOlO1i <= (wire_nlO0i0i1O_dataout XOR niOiOli0l); + niOiOlO1l <= (wire_nlO0i00OO_dataout XOR niOiOliii); + niOiOlO1O <= (wire_nlO0i0i1i_dataout XOR niOiOliii); + niOiOlOii <= (wire_nlO0i00OO_dataout XOR niOiOO1il); + niOiOlOil <= (wire_nlO0i0i1l_dataout XOR niOiOlOlO); + niOiOlOiO <= (wire_nlO0i0i0l_dataout XOR niOiOlOli); + niOiOlOli <= (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOlOll)); + niOiOlOll <= (wire_nlO0i00OO_dataout XOR wire_nlO0i00Oi_dataout); + niOiOlOlO <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00Ol_dataout); + niOiOlOOi <= (wire_nlO0i0i1l_dataout XOR wire_nlO0i00OO_dataout); + niOiOlOOl <= (wire_nlO0i0i1O_dataout XOR niOiOO11l); + niOiOlOOO <= (wire_nlO0i0i1l_dataout XOR niOiOO10O); + niOiOO00i <= (wire_nlO0i0i1i_dataout XOR niOiOO01O); + niOiOO00l <= (wire_nlO0i00OO_dataout XOR niOiOlO0O); + niOiOO00O <= (wire_nlO0i0i1i_dataout XOR niOiOlO0O); + niOiOO01i <= (wire_nlO0i0i1l_dataout XOR niOiOO1lO); + niOiOO01l <= (wire_nlO0i0i1i_dataout XOR niOiOlOii); + niOiOO01O <= (wire_nlO0i00OO_dataout XOR wire_nlO0i00Ol_dataout); + niOiOO0ii <= (wire_nlO0i001O_dataout OR nlO00O11i); + niOiOO0il <= (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO1ll)); + niOiOO0iO <= (wire_nlO0i0i0i_dataout XOR niOiOO01i); + niOiOO0li <= (k_conf(216) AND wire_nlOl1l0Ol_dataout); + niOiOO0ll <= (((wire_nl1000i_w_lg_w29780w29785w(0) AND wire_nl1000i_w_lg_nlOi1OiOi29643w(0)) AND wire_nl1000i_w_lg_nlOi1OilO29645w(0)) AND wire_nl1000i_w_lg_nlOi1Oill29647w(0)); + niOiOO0lO <= (nlO00O11i OR nlO00lOll); + niOiOO0Oi <= (k_conf(216) AND nlO1Ol1li); + niOiOO0Ol <= (nlO00lOli AND wire_nlOiilO1l_dataout); + niOiOO0OO <= (nlO00lOli AND wire_nlOiilO1l_w_lg_dataout9857w(0)); + niOiOO10i <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00OO_dataout); + niOiOO10l <= (wire_nlO0i00OO_dataout XOR niOiOO10O); + niOiOO10O <= (wire_nlO0i00Ol_dataout XOR wire_nlO0i00Oi_dataout); + niOiOO11i <= (wire_nlO0i0i1i_dataout XOR niOiOlOll); + niOiOO11l <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00Oi_dataout); + niOiOO11O <= (wire_nlO0i00OO_dataout XOR wire_nlO0i00Ol_dataout); + niOiOO1ii <= (wire_nlO0i0i1i_dataout XOR niOiOO10l); + niOiOO1il <= (wire_nlO0i00Oi_dataout OR nlO00O11i); + niOiOO1iO <= (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOO00O))); + niOiOO1li <= (wire_nlO0i0i0i_dataout XOR niOiOO1Oi); + niOiOO1ll <= (wire_nlO0i0i1l_dataout XOR niOiOlOii); + niOiOO1lO <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00Ol_dataout); + niOiOO1Oi <= (wire_nlO0i0i1O_dataout XOR wire_nlO0i0i1l_dataout); + niOiOO1Ol <= (wire_nlO0i0i1l_dataout XOR wire_nlO0i0i1i_dataout); + niOiOO1OO <= (wire_nlO0i0i1i_dataout XOR wire_nlO0i00OO_dataout); + niOiOOi0i <= (((nlO00O11i OR nlO00lOOl) OR nlO00lOOi) OR nlO00lOlO); + niOiOOi0l <= (nlO0iOiOO AND (k_conf(216) AND niOiOOiii)); + niOiOOi0O <= (wire_nl1000i_w_lg_nlO0iOiOO29413w(0) AND niOiOOiii); + niOiOOi1i <= (k_conf(216) AND nlO00lOlO); + niOiOOi1l <= (k_conf(216) AND nlO00lOOi); + niOiOOi1O <= ((nlO00lOOl OR nlO00lOOi) OR nlO00lOlO); + niOiOOiii <= ((wire_nl1000i_w_lg_w29769w29771w(0) AND wire_nl1000i_w_lg_nlO0liiOO29772w(0)) AND wire_nl1000i_w_lg_nlO0liiOl29775w(0)); + niOiOOiil <= (niOl11l0O AND nlO0iOiOO); + niOiOOiiO <= (nlO0OlOii AND wire_w_lg_niOl1010l29171w(0)); + niOiOOili <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOill); + niOiOOill <= (nllOili0l XOR (nllOili1O XOR (nllOili1l XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00O XOR (nllOil00i XOR (nllOil1OO XOR (nllOil1lO XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOlllO))))))))))))))))))))))); + niOiOOilO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOiOi); + niOiOOiOi <= (nllOili0O XOR (nllOili0i XOR (nllOili1O XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0iO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00l XOR (nllOil01i XOR (nllOil1Oi XOR (nllOil1il XOR (nllOil1ii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR niOiOllOi))))))))))))))))))))))); + niOiOOiOl <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOiOO); + niOiOOiOO <= (nllOili0O XOR (nllOili1O XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil1OO XOR (nllOil1ll XOR (nllOil1iO XOR (nllOil1il XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOll1l))))))))))))))))))))))))))); + niOiOOl0i <= (nllOili0l XOR (nllOili1O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil01l XOR (nllOil1Oi XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1ii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOlllO))))))))))))))))))))))))); + niOiOOl0l <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOl0O); + niOiOOl0O <= (nllOili0O XOR (nllOili0i XOR (nllOili1O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil01O XOR (nllOil1Ol XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1il XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOllOi))))))))))))))))))))))))); + niOiOOl1i <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOl1l); + niOiOOl1l <= (nllOili0i XOR (nllOili1l XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil01i XOR (nllOil1lO XOR (nllOil1li XOR (nllOil1iO XOR (nllOil10O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOll0i)))))))))))))))))))))))))); + niOiOOl1O <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOl0i); + niOiOOlii <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOlil); + niOiOOlil <= (nllOili0l XOR (nllOili0i XOR (nllOili1O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil00i XOR (nllOil1OO XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1iO XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOllOO)))))))))))))))))))))); + niOiOOliO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR niOiOOlli); + niOiOOlli <= (nllOili0O XOR (nllOili0l XOR (nllOili0i XOR (nllOili1O XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil00l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1li XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOli0l)))))))))))))))))))))); + niOiOOlll <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0Ol); + niOiOOllO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0OO); + niOiOOlOi <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOili1i); + niOiOOlOl <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOili1l); + niOiOOlOO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOili1O); + niOiOOO0i <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil00O); + niOiOOO0l <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0ii); + niOiOOO0O <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0il); + niOiOOO1i <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOili0i); + niOiOOO1l <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOili0l); + niOiOOO1O <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOili0O); + niOiOOOii <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0iO); + niOiOOOil <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0li); + niOiOOOiO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0ll); + niOiOOOli <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0lO); + niOiOOOll <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil0Oi); + niOiOOOlO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1Oi); + niOiOOOOi <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1Ol); + niOiOOOOl <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1OO); + niOiOOOOO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil01i); + niOl0000i <= (((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0liO) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1i) OR n11O0iOl); + niOl0000l <= ((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0llO) OR n11O0liO) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOl); + niOl0000O <= (((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0lil) OR n11O0lii) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl0001i <= (((((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0lli) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl0001l <= ((((((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl0001O <= ((((((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOl); + niOl000ii <= (((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOl); + niOl000il <= ((((((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0l) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl000iO <= ((((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0i) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl000li <= (((((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl000ll <= ((((((((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl000lO <= ((((((((((((((((n11O0Oil OR n11O0Oii) OR n11O0O0l) OR n11O0O1l) OR n11O0lOO) OR n11O0lOi) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl000Oi <= (((((((((((((((((((n11O0Oii OR n11O0O0l) OR n11O0O0i) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl000Ol <= ((((((((((((((((((((((n11O0Oii OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl000OO <= ((((((((((((((((((((n11O0Oii OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl0010i <= ((nlOlOilOi AND niOli1iOO) AND wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + niOl0010l <= (n11O0ili AND wire_niO01iOi_w_lg_n11O0iiO26588w(0)); + niOl0010O <= (n11O0iil AND wire_niO01iOi_w_lg_n11O0iii26586w(0)); + niOl0011i <= (n11O0i1O AND wire_niO01iOi_w_lg_n11O0i1l26592w(0)); + niOl0011l <= (wire_niO01ill_w_lg_n11l0OiO23413w(0) AND wire_w_lg_niOl0011O23416w(0)); + niOl0011O <= (((((((wire_niO10O1i_w_lg_dataout19787w(0) AND wire_niO10l1i_w_lg_dataout19790w(0)) AND wire_niO10i1i_w_lg_dataout19794w(0)) AND wire_niO1001i_w_lg_dataout19798w(0)) AND wire_niO1011i_w_lg_dataout19802w(0)) AND wire_niO11O1i_w_lg_dataout19806w(0)) AND wire_niO11l1i_w_lg_dataout19810w(0)) AND wire_niO11i1i_w_lg_dataout19814w(0)); + niOl001ii <= (n0O0O0OO AND n0O0O01O); + niOl001il <= (n0ll0lll AND n0ll0iOl); + niOl001iO <= (n0iOO1ii AND n0iOlOli); + niOl001li <= (n0i00i1O AND n0i0000O); + niOl001ll <= (n00illOl AND n00ill1l); + niOl001lO <= (n01O01li AND n01O1OOi); + niOl001Oi <= (n011li0O AND n011l0iO); + niOl001Ol <= (n1Oi1O1l AND n1Oi1l0l); + niOl001OO <= (n11O0lOl OR n11O0lll); + niOl00i0i <= (((((((((((((((((((((n11O0Oii OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl00i0l <= ((((((((((((((((((((n11O0Oii OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0liO) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl00i0O <= ((((((((((((((((((n11O0Oii OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0lOO) OR n11O0lOl) OR n11O0llO) OR n11O0lll) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl00i1i <= ((((((((((((((((((n11O0Oii OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0liO) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOl); + niOl00i1l <= ((((((((((((((((((((((n11O0Oii OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl00i1O <= (n11O0Oil OR n11O0O0O); + niOl00iii <= ((((((((((((((((((((((n11O0Oii OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0O1l) OR n11O0O1i) OR n11O0lOO) OR n11O0lOl) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl00iil <= (((((((((((((((((((n11O0Oii OR n11O0O0O) OR n11O0O0l) OR n11O0O0i) OR n11O0O1O) OR n11O0lOi) OR n11O0llO) OR n11O0lll) OR n11O0lli) OR n11O0liO) OR n11O0lil) OR n11O0lii) OR n11O0l0O) OR n11O0l0l) OR n11O0l0i) OR n11O0l1O) OR n11O0l1l) OR n11O0l1i) OR n11O0iOO) OR n11O0iOl); + niOl00iiO <= (niOlOOlOl AND ((nlOlliOOO AND nlOll000O) AND n1110O0l)); + niOl00ili <= (wire_w_lg_niOO10lOO8902w(0) AND (wire_w_lg_niOl0Ol0i21223w(0) OR wire_niO01ill_w_lg_nlOlOilOl21225w(0))); + niOl00ill <= (n1iiOlll AND (nlOlOiO1l AND wire_niO01ill_w_lg_nlOlOiliO21217w(0))); + niOl00ilO <= (niOO10l1i AND ((wire_nlOii0lOl_dataout AND niOl0i0OO) AND wire_w_lg_niOl0O0Oi20806w(0))); + niOl00iOi <= (wire_w_lg_niOli1iOl21214w(0) OR wire_w_lg_niOl00iOl21215w(0)); + niOl00iOl <= (((((((wire_niO01ill_w_lg_nlOO00ill26571w(0) AND wire_niO01ill_w_lg_nlOO00ili26572w(0)) AND wire_niO01ill_w_lg_nlOO00iiO26574w(0)) AND wire_niO01ill_w_lg_nlOO00iil26576w(0)) AND wire_niO01ill_w_lg_nlOO00iii26578w(0)) AND wire_niO01ill_w_lg_nlOO00i0O26580w(0)) AND wire_niO01ill_w_lg_nlOO00i0l26582w(0)) AND wire_niO01ill_w_lg_nlOO00i0i26584w(0)); + niOl00iOO <= ((((((((NOT ((niil01il OR nlOO00l0l) AND nlOOOl1ll)) AND (NOT ((niil01ii OR nlOO00l0O) AND nlOOOl1lO))) AND (NOT ((niil0iOO OR nlOO00lii) AND nlOOOl1Oi))) AND (NOT ((niil0l1l OR nlOO00lil) AND nlOOOl1Ol))) AND (NOT ((niil0l1O OR nlOO00liO) AND nlOOOl1OO))) AND (NOT ((niil0l0i OR nlOO00lli) AND nlOOOl01i))) AND (NOT ((niil0l0l OR nlOO00lll) AND nlOOOl01l))) AND (NOT ((niil0liO OR nlOO00llO) AND nlOOOl01O))); + niOl00l0i <= (wire_niO01ill_w_lg_n1il11ll21199w(0) OR (n1il11Ol AND n1110Oii)); + niOl00l0l <= ((niOO10lOO AND n1iO0l0O) AND niOl00l0O); + niOl00l0O <= (((((((wire_niO01ill_w_lg_nlOO00llO26929w(0) AND wire_niO01ill_w_lg_nlOO00lll26930w(0)) AND wire_niO01ill_w_lg_nlOO00lli26932w(0)) AND wire_niO01ill_w_lg_nlOO00liO26934w(0)) AND wire_niO01ill_w_lg_nlOO00lil26936w(0)) AND wire_niO01ill_w_lg_nlOO00lii26938w(0)) AND wire_niO01ill_w_lg_nlOO00l0O26940w(0)) AND wire_niO01ill_w_lg_nlOO00l0l26942w(0)); + niOl00l1i <= (wire_niO01ill_w_lg_n1iilliO21209w(0) AND wire_niO01ill_w_lg_n11O1lil21210w(0)); + niOl00l1l <= (wire_niO01ill_w_lg_n1110Oii21207w(0) OR wire_niO01ill_w_lg_n1110Oii21198w(0)); + niOl00l1O <= (wire_niO01ill_w_lg_niOO0Oi0l21202w(0) AND (wire_niO01ill_w_lg_n11O00OO21203w(0) OR wire_niO01ill_w_lg_nlOliiO0i21204w(0))); + niOl00lii <= (niOO10lOO AND wire_w_lg_niOl00lil21194w(0)); + niOl00lil <= ((((((((NOT (n111i1ii AND nlOOOiO1l)) AND (NOT (n111i1il AND nlOOOiO1O))) AND (NOT (n111i1iO AND nlOOOiO0i))) AND (NOT (n111i1li AND nlOOOiO0l))) AND (NOT (n111i1ll AND nlOOOiO0O))) AND (NOT (n111i1lO AND nlOOOiOii))) AND (NOT (n111i1Oi AND nlOOOiOil))) AND (NOT (n111i1Ol AND nlOOOiOiO))); + niOl00liO <= ((wire_nlOii0l0O_w_lg_dataout21190w(0) AND wire_w_lg_w_lg_niOO10lOO8902w21191w(0)) AND nlOOOi10i); + niOl00lli <= ((((((((NOT ((nlOO0iilO AND n1Oi01iO) AND wire_niO01ill_w_lg_n1101l1l17904w(0))) AND (NOT ((nlOO0iiOi AND n011llOi) AND wire_niO01ill_w_lg_n1101l1O16997w(0)))) AND (NOT ((nlOO0iiOl AND n01O0i1l) AND wire_niO01ill_w_lg_n1101l0i16090w(0)))) AND (NOT ((nlOO0iiOO AND n00iO10O) AND wire_niO01ill_w_lg_n1101l0l15183w(0)))) AND (NOT ((nlOO0il1i AND n0i00lli) AND wire_niO01ill_w_lg_n1101l0O14276w(0)))) AND (NOT ((nlOO0il1l AND n0iOO0Ol) AND wire_niO01ill_w_lg_n1101lii13369w(0)))) AND (NOT ((nlOO0il1O AND n0lli11O) AND wire_niO01ill_w_lg_n1101lil12462w(0)))) AND (NOT ((nlOO0il0i AND n0O0Olii) AND wire_niO01ill_w_lg_n1101liO11541w(0)))); + niOl00lll <= ((niOl0ii1O AND n1lillil) AND niOli101i); + niOl00llO <= (wire_n1l10lli_dataout OR (wire_w_lg_niOl00lOi21181w(0) AND n1lillil)); + niOl00lOi <= ((((((((NOT (wire_niO01ill_w_lg_n1101l1l17904w(0) AND nlOO00O0O)) AND (NOT (wire_niO01ill_w_lg_n1101l1O16997w(0) AND nlOO00Oii))) AND (NOT (wire_niO01ill_w_lg_n1101l0i16090w(0) AND nlOO00Oil))) AND (NOT (wire_niO01ill_w_lg_n1101l0l15183w(0) AND nlOO00OiO))) AND (NOT (wire_niO01ill_w_lg_n1101l0O14276w(0) AND nlOO00Oli))) AND (NOT (wire_niO01ill_w_lg_n1101lii13369w(0) AND nlOO00Oll))) AND (NOT (wire_niO01ill_w_lg_n1101lil12462w(0) AND nlOO00OlO))) AND (NOT (wire_niO01ill_w_lg_n1101liO11541w(0) AND nlOO00OOi))); + niOl00lOl <= (niOli1OiO OR (niOO10lOO AND wire_w_lg_niOl00lOO21178w(0))); + niOl00lOO <= ((((((((NOT (niOl00Oil AND wire_niO01ill_w_lg_n1101l1l17904w(0))) AND (NOT (niOl00Oii AND wire_niO01ill_w_lg_n1101l1O16997w(0)))) AND (NOT (niOl00O0O AND wire_niO01ill_w_lg_n1101l0i16090w(0)))) AND (NOT (niOl00O0l AND wire_niO01ill_w_lg_n1101l0l15183w(0)))) AND (NOT (niOl00O0i AND wire_niO01ill_w_lg_n1101l0O14276w(0)))) AND (NOT (niOl00O1O AND wire_niO01ill_w_lg_n1101lii13369w(0)))) AND (NOT (niOl00O1l AND wire_niO01ill_w_lg_n1101lil12462w(0)))) AND (NOT (niOl00O1i AND wire_niO01ill_w_lg_n1101liO11541w(0)))); + niOl00O0i <= (nlOO0il1i AND n0i00i0l); + niOl00O0l <= (nlOO0iiOO AND n00ilO1i); + niOl00O0O <= (nlOO0iiOl AND n01O01lO); + niOl00O1i <= (nlOO0il0i AND n0O0Oi1l); + niOl00O1l <= (nlOO0il1O AND n0ll0lOi); + niOl00O1O <= (nlOO0il1l AND n0iOO1iO); + niOl00Oii <= (nlOO0iiOi AND n011liil); + niOl00Oil <= (nlOO0iilO AND n1Oi1O0i); + niOl00OiO <= (((((((wire_niO01ill_w_lg_nlOO0i10O26448w(0) AND wire_niO01ill_w_lg_nlOO0i10l26449w(0)) AND wire_niO01ill_w_lg_nlOO0i10i26451w(0)) AND wire_niO01ill_w_lg_nlOO0i11O26453w(0)) AND wire_niO01ill_w_lg_nlOO0i11l26455w(0)) AND wire_niO01ill_w_lg_nlOO0i11i26457w(0)) AND wire_niO01ill_w_lg_nlOO00OOO26459w(0)) AND wire_niO01ill_w_lg_nlOO00OOl26461w(0)); + niOl00Oli <= (wire_w_lg_niOO10lOO8902w(0) AND wire_w_lg_niOl00Oll21164w(0)); + niOl00Oll <= (((((((wire_niO01ill_w_lg_n11O000O26433w(0) AND wire_niO01ill_w_lg_n11O000l26434w(0)) AND wire_niO01ill_w_lg_n11O000i26436w(0)) AND wire_niO01ill_w_lg_n11O001O26438w(0)) AND wire_niO01ill_w_lg_n11O001l26440w(0)) AND wire_niO01ill_w_lg_n11O001i26442w(0)) AND wire_niO01ill_w_lg_n11O01OO26444w(0)) AND wire_niO01ill_w_lg_n11O01Ol26446w(0)); + niOl00OlO <= (n1il11Ol OR niOl00OOi); + niOl00OOi <= (n1il11OO AND niOl00OOl); + niOl00OOl <= ((((((((NOT ((n111i1ii AND nlOO0ilOi) XOR n111i1ii)) AND (NOT ((n111i1il AND nlOOO0OlO) XOR n111i1il))) AND (NOT ((n111i1iO AND nlOOO0OOi) XOR n111i1iO))) AND (NOT ((n111i1li AND nlOOO0OOl) XOR n111i1li))) AND (NOT ((n111i1ll AND nlOOO0OOO) XOR n111i1ll))) AND (NOT ((n111i1lO AND nlOOOi11i) XOR n111i1lO))) AND (NOT ((n111i1Oi AND nlOOOi11l) XOR n111i1Oi))) AND (NOT ((n111i1Ol AND nlOOOi11O) XOR n111i1Ol))); + niOl00OOO <= ((niOl0i00i AND niOl0i11O) AND niOl0i11l); + niOl0100i <= (niOl0100O AND niOl0100l); + niOl0100l <= (n1101l0i OR (NOT (nlOO0iiOO AND nlOO0iiOl))); + niOl0100O <= (wire_w_lg_w_lg_w_k_gbl_hip_range23582w23583w23584w(0) OR wire_niO01ill_w_lg_n111i0il23585w(0)); + niOl0101i <= (n1101lii OR (NOT (nlOO0il1l AND nlOO0il1i))); + niOl0101l <= (n1101l1O OR (NOT (nlOO0iiOi AND nlOO0iilO))); + niOl0101O <= ((k_gbl_hip(43) AND n111i0il) AND niOl0100l); + niOl010ii <= (((nlOOOl01O AND nlOOOl01l) AND nlOOOl01i) AND nlOOOl1OO); + niOl010il <= (nlOO0il0i AND nlOO0il1O); + niOl010iO <= (((((((nlOOOl01O AND nlOOOl01l) AND nlOOOl01i) AND nlOOOl1OO) AND nlOOOl1Ol) AND nlOOOl1Oi) AND nlOOOl1lO) AND nlOOOl1ll); + niOl010li <= (((nlOOOl1Ol AND nlOOOl1Oi) AND nlOOOl1lO) AND nlOOOl1ll); + niOl010ll <= ((n11Oi1OO AND n1lillil) AND nlOO0ii1i); + niOl010lO <= ((niOO10lOO AND n1lillil) AND nlOO0ii1i); + niOl010Oi <= (niOl00i1O AND n1lillil); + niOl010Ol <= ((niOli101l OR niOli111O) AND n1lillil); + niOl010OO <= ((n11O0l1l AND ((wire_niO01ill_w_lg_n1110Oli23547w(0) AND n1110OiO) OR n1lillil)) AND nlOll000O); + niOl0110i <= (niOl0110O AND niOl0110l); + niOl0110l <= ((wire_nlOii0Oii_w_lg_w_lg_w_lg_w26809w26811w26813w26815w(0) AND wire_nlOlOi10O_w_lg_dataout26844w(0)) AND wire_nlOlOi10l_w_lg_dataout26817w(0)); + niOl0110O <= ((((((((((((wire_niO01ill_w_lg_nlOll000l26819w(0) AND wire_niO01ill_w_lg_nlOll000i26820w(0)) AND wire_niO01ill_w_lg_nlOll001O26822w(0)) AND wire_niO01ill_w_lg_nlOll001l26824w(0)) AND wire_niO01ill_w_lg_nlOll001i26826w(0)) AND wire_niO01ill_w_lg_nlOll01OO26828w(0)) AND wire_niO01ill_w_lg_nlOll01Ol26830w(0)) AND wire_niO01ill_w_lg_nlOll01Oi26832w(0)) AND wire_niO01ill_w_lg_nlOll01lO26834w(0)) AND wire_niO01ill_w_lg_nlOll01ll26836w(0)) AND wire_niO01ill_w_lg_nlOll01li26838w(0)) AND wire_niO01ill_w_lg_nlOll01iO26840w(0)) AND wire_niO01ill_w_lg_nlOliO0ll26842w(0)); + niOl0111i <= ((((((((((((((NOT wire_n11010li_o(13)) AND (NOT (wire_nlOlOi10l_dataout XOR nlOliO0ll))) AND (NOT (wire_n11010li_o(1) XOR nlOll01iO))) AND (NOT (wire_n11010li_o(2) XOR nlOll01li))) AND (NOT (wire_n11010li_o(3) XOR nlOll01ll))) AND (NOT (wire_n11010li_o(4) XOR nlOll01lO))) AND (NOT (wire_n11010li_o(5) XOR nlOll01Oi))) AND (NOT (wire_n11010li_o(6) XOR nlOll01Ol))) AND (NOT (wire_n11010li_o(7) XOR nlOll01OO))) AND (NOT (wire_n11010li_o(8) XOR nlOll001i))) AND (NOT (wire_n11010li_o(9) XOR nlOll001l))) AND (NOT (wire_n11010li_o(10) XOR nlOll001O))) AND (NOT (wire_n11010li_o(11) XOR nlOll000i))) AND (NOT (wire_n11010li_o(12) XOR nlOll000l))); + niOl0111l <= (niOl0111O AND niOl011il); + niOl0111O <= ((wire_nlOii0Oii_w_lg_w_lg_w_lg_w26809w26811w26813w26815w(0) AND wire_nlOlOi10O_w_lg_dataout26844w(0)) AND wire_nlOlOi10l_dataout); + niOl011ii <= (niOl011iO AND niOl011il); + niOl011il <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19841w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND n110OOOO); + niOl011iO <= (wire_nlOii0Oii_w26816w(0) AND wire_nlOlOi10l_w_lg_dataout26817w(0)); + niOl011li <= (n1101l0l OR (NOT (((nlOO0iiOO AND nlOO0iiOl) AND nlOO0iiOi) AND nlOO0iilO))); + niOl011ll <= (n1101l0O OR (NOT (((nlOO0il0i AND nlOO0il1O) AND nlOO0il1l) AND nlOO0il1i))); + niOl011lO <= (((n11Oi1Ol AND nlOO0ii1i) AND niOl0iO1i) AND n1lillil); + niOl011Oi <= ((wire_nlOO1iO0l_w_lg_dataout26694w(0) AND wire_nlOO1iO0i_w_lg_dataout24105w(0)) AND wire_nlOO1iO1O_w_lg_dataout24104w(0)); + niOl011Ol <= (wire_niO01ill_w_lg_n1101l1l17904w(0) AND (niOl1O1Ol AND niOl1iO0O)); + niOl011OO <= (n1101lil OR wire_w_lg_niOl010il23577w(0)); + niOl01i0i <= (n11O0l1l AND nlOll0O0O); + niOl01i0l <= (n1lillil AND wire_niO01ill_w_lg_n1lil0Ol23456w(0)); + niOl01i0O <= (wire_niO01ill_w_lg_w_lg_w19844w23519w23520w(0) AND wire_w_lg_niOl01lll23467w(0)); + niOl01i1i <= (niOl01i1l AND wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + niOl01i1l <= ((n11O0l1l AND n1lillil) AND nlOll0O0i); + niOl01i1O <= (niOl0i0Ol AND n1lillil); + niOl01iii <= (((wire_niO01ill_w_lg_w_lg_n11i111O19846w19924w(0) AND wire_niO01ill_w_lg_n110OOOO19843w(0)) AND n1lillil) AND n1110Oii); + niOl01iil <= (n11O0i1i AND (niOl01O0l AND wire_w_lg_niOli10Ol20065w(0))); + niOl01iiO <= (n1il11Ol AND n1lillil); + niOl01ili <= (wire_niO01iOi_w_lg_n1il11Ol20649w(0) AND n1lillil); + niOl01ill <= (wire_niO01iOi_w_lg_n1il11Ol20649w(0) AND niOl01l1O); + niOl01ilO <= (wire_niO01iOi_w_lg_n1il11Ol20649w(0) AND wire_w_lg_w_lg_niOli101i20192w23502w(0)); + niOl01iOi <= (((niOl0l1iO AND wire_niO01ill_w_lg_n1lil0Ol23456w(0)) OR niOli10Ol) AND n1lillil); + niOl01iOl <= ((n1iO0l0O OR (n1iOl0Ol AND (wire_w_lg_niOO10lOO8902w(0) AND wire_w_lg_niOli1OiO23494w(0)))) AND niOl01l1O); + niOl01iOO <= (niOl01l1i AND wire_niO01ill_w_lg_n1lil0Ol23456w(0)); + niOl01l0i <= (wire_niO01ill_w_lg_n11Oi1ii23487w(0) AND n11O0liO); + niOl01l0l <= (wire_n1l10lli_dataout OR (wire_w_lg_w_lg_niOO10lOO8902w21166w(0) OR wire_w_lg_w_lg_niOO10lOO8902w23489w(0))); + niOl01l0O <= (wire_niO01ill_w_lg_n11li10i21145w(0) AND wire_niO01ill_w_lg_w_lg_n11li10l21153w23483w(0)); + niOl01l1i <= (niOl0l1iO AND n1lillil); + niOl01l1l <= (niOl01l1O AND niOli101i); + niOl01l1O <= (niOli111O AND n1lillil); + niOl01lii <= ((niOl0i0ii AND n1lillil) AND niOli101i); + niOl01lil <= (n1lillll AND wire_niO01ill_w_lg_n1l00i0i23478w(0)); + niOl01liO <= (niOlOOlOl AND ((((wire_w_lg_niOO10lOO8902w(0) AND (n11O01iO OR n11O01il)) OR wire_w_lg_niOO10lOO23473w(0)) AND n1lillil) AND niOl0i0Ol)); + niOl01lli <= (niOli111l OR n1l00i0i); + niOl01lll <= (((wire_niO01ill_w_lg_n110OOll26678w(0) AND wire_niO01ill_w_lg_n110OOli26679w(0)) AND wire_niO01ill_w_lg_n110OOiO26681w(0)) AND wire_niO01ill_w_lg_n110OOil26683w(0)); + niOl01llO <= (n11O00Oi OR (wire_nlOi0iiOO_dataout AND wire_nlOi0iili_dataout)); + niOl01lOi <= (n1il11ll OR (n1il11Ol AND niOl00OOl)); + niOl01lOl <= (n11O00ll OR n11O1Oii); + niOl01lOO <= (wire_nlOi0iili_w_lg_dataout20928w(0) AND wire_niO01ill_w_lg_w_lg_nlOlOiliO21217w23459w(0)); + niOl01O0i <= ((wire_w_lg_niOl01O0O23447w(0) OR niOli101l) AND niOl01O0l); + niOl01O0l <= (wire_w_lg_niOl0l1iO23508w(0) AND n1lillil); + niOl01O0O <= (wire_niO01ill_w_lg_n11i111l19781w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)); + niOl01O1i <= (niOl0Oi1i AND n1lillil); + niOl01O1l <= (wire_w_lg_w_lg_niOl0Oi1i23454w23455w(0) AND wire_niO01ill_w_lg_n1lil0Ol23456w(0)); + niOl01O1O <= ((n1il11Ol AND (niOl0OlOl AND niOl0Oi0O)) AND nlOlOilOO); + niOl01Oii <= ((wire_niO01ill_w_lg_n11l0OOi26662w(0) AND wire_niO01ill_w_lg_n11l0OlO26663w(0)) AND wire_niO01ill_w_lg_n11l0Oll26665w(0)); + niOl01Oil <= (niOO10l1i AND wire_w_lg_niOl01OiO23443w(0)); + niOl01OiO <= ((((((((NOT ((wire_w_lg_niOl1O10l26623w(0) AND niOl1O1Ol) AND niOl1lili)) AND (NOT ((wire_w_lg_niOl1O10i26627w(0) AND niOl1O1lO) AND niOl1liiO))) AND (NOT ((niOl1OOOl AND wire_w_lg_niOl1O11O26632w(0)) AND niOl1liil))) AND (NOT ((wire_w_lg_niOl1O11l26637w(0) AND niOl1O1ll) AND niOl1liii))) AND (NOT ((niOl1OOOi AND wire_w_lg_niOl1O11i26642w(0)) AND niOl1li0O))) AND (NOT ((niOl1OOlO AND wire_w_lg_niOl1lOOO26647w(0)) AND niOl1li0l))) AND (NOT ((niOl1OOll AND wire_w_lg_niOl1lOOl26652w(0)) AND niOl1li0i))) AND (NOT ((wire_w_lg_niOl1lOOi26657w(0) AND niOl1O1li) AND niOl1li1O))); + niOl01Oli <= ((((((((NOT (niOl001Ol AND niOl1lili)) AND (NOT (niOl001Oi AND niOl1liiO))) AND (NOT (niOl001lO AND niOl1liil))) AND (NOT (niOl001ll AND niOl1liii))) AND (NOT (niOl001li AND niOl1li0O))) AND (NOT (niOl001iO AND niOl1li0l))) AND (NOT (niOl001il AND niOl1li0i))) AND (NOT (niOl001ii AND niOl1li1O))); + niOl01Oll <= ((wire_niO01ill_w_lg_n11li11l26618w(0) AND wire_niO01ill_w_lg_n11li11i26619w(0)) AND wire_niO01ill_w_lg_n11l0OOO26621w(0)); + niOl01OlO <= (n11O0i1i AND niOli1iOl); + niOl01OOi <= ((n1il11Ol AND niOli10Ol) AND niOl00OOl); + niOl01OOl <= (niOli10Ol AND n1lillil); + niOl01OOO <= (wire_niO01ill_w_lg_n11O0i1O26590w(0) AND n11O0i1l); + niOl0i00i <= (wire_n10l1i1i_o AND wire_niO01ill_w_lg_n11O0ilO21059w(0)); + niOl0i00l <= (wire_niO01ill_w_lg_n11li1il21048w(0) AND (wire_n10l1i1i_o OR n11l0Oli)); + niOl0i00O <= (wire_nlOii0Oii_w_lg_w_lg_w_lg_dataout21042w21043w21044w(0) AND (NOT (n11O0iOi XOR n11li1il))); + niOl0i01i <= ((wire_niO01ill_w_lg_n11li10i21129w(0) AND (wire_n10l1i1i_o OR wire_n10ilOOl_o)) AND niOli11iO); + niOl0i01l <= ((wire_niO01ill_w_lg_w_lg_n11O0iOi21061w21062w(0) OR (wire_w_lg_niOO10l1i20908w(0) AND (((((((wire_niO01ill_w_lg_n1101l1l21067w(0) AND wire_niO01ill_w_lg_n1101l1O21072w(0)) AND wire_niO01ill_w_lg_n1101l0i21078w(0)) AND wire_niO01ill_w_lg_n1101l0l21084w(0)) AND wire_niO01ill_w_lg_n1101l0O21090w(0)) AND wire_niO01ill_w_lg_n1101lii21096w(0)) AND wire_niO01ill_w_lg_n1101lil21102w(0)) AND wire_niO01ill_w_lg_n1101liO21108w(0)))) AND wire_w_lg_niOli10il21112w(0)); + niOl0i01O <= ((((((((NOT (nlOOOl1ll AND n1Oi1l0l)) AND (NOT (nlOOOl1lO AND n011l0iO))) AND (NOT (nlOOOl1Oi AND n01O1OOi))) AND (NOT (nlOOOl1Ol AND n00ill1l))) AND (NOT (nlOOOl1OO AND n0i0000O))) AND (NOT (nlOOOl01i AND n0iOlOli))) AND (NOT (nlOOOl01l AND n0ll0iOl))) AND (NOT (nlOOOl01O AND n0O0O01O))); + niOl0i0ii <= ((((((((n1101l1l OR nlOO0iilO) AND (n1101l1O OR nlOO0iiOi)) AND (n1101l0i OR nlOO0iiOl)) AND (n1101l0l OR nlOO0iiOO)) AND (n1101l0O OR nlOO0il1i)) AND (n1101lii OR nlOO0il1l)) AND (n1101lil OR nlOO0il1O)) AND (n1101liO OR nlOO0il0i)); + niOl0i0il <= ((n1110O0l AND niOl0i0Ol) AND (wire_nlOii11Ol_dataout OR niOlOOlOl)); + niOl0i0iO <= ((niOl0Ol0i AND niOl0i0lO) AND nlOOOi10i); + niOl0i0li <= ((((((((NOT (n111i1ii AND nlOO00l0l)) AND (NOT (n111i1il AND nlOO00l0O))) AND (NOT (n111i1iO AND nlOO00lii))) AND (NOT (n111i1li AND nlOO00lil))) AND (NOT (n111i1ll AND nlOO00liO))) AND (NOT (n111i1lO AND nlOO00lli))) AND (NOT (n111i1Oi AND nlOO00lll))) AND (NOT (n111i1Ol AND nlOO00llO))); + niOl0i0ll <= ((wire_nlOii10ii_dataout AND niOl0i0lO) AND nlOOOi10i); + niOl0i0lO <= ((nlOO01OOO OR wire_w_lg_niOl0i0li21031w(0)) OR nlOO0011i); + niOl0i0Oi <= ((wire_nlOi00iOl_dataout AND (niOl0ii1i OR n11O0iOi)) AND wire_n10lil0l_o); + niOl0i0Ol <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19841w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOl0i0OO <= (wire_w_lg_niOO10lOO8902w(0) AND n11li11O); + niOl0i10i <= (wire_w_lg_niOli101i21149w(0) AND (wire_w_lg_w_lg_w_lg_niOO10l1i20908w21151w21152w(0) OR wire_niO01ill_w_lg_n11li10l21153w(0))); + niOl0i10l <= (((((((wire_niO01ill_w_lg_nlOO000li26372w(0) AND wire_niO01ill_w_lg_nlOO000iO26373w(0)) AND wire_niO01ill_w_lg_nlOO000il26375w(0)) AND wire_niO01ill_w_lg_nlOO000ii26377w(0)) AND wire_niO01ill_w_lg_nlOO0000O26379w(0)) AND wire_niO01ill_w_lg_nlOO0000l26381w(0)) AND wire_niO01ill_w_lg_nlOO0000i26383w(0)) AND wire_niO01ill_w_lg_nlOO0001O26385w(0)); + niOl0i10O <= ((niOl0ii0i AND niOli11ll) AND (wire_niO01ill_w_lg_w_lg_n11li10O21143w21144w(0) OR wire_niO01ill_w_lg_n11li10i21145w(0))); + niOl0i11i <= ((niOl0i11O AND n11O0ilO) AND niOl0i11l); + niOl0i11l <= (((((((wire_niO01ill_w_lg_n1ilOOii26387w(0) AND wire_niO01ill_w_lg_n1ilOO0O26388w(0)) AND wire_niO01ill_w_lg_n1ilOO0l26390w(0)) AND wire_niO01ill_w_lg_n1ilOO0i26392w(0)) AND wire_niO01ill_w_lg_n1ilOO1O26394w(0)) AND wire_niO01ill_w_lg_n1ilOO1l26396w(0)) AND wire_niO01ill_w_lg_n1ilOO1i26398w(0)) AND wire_niO01ill_w_lg_n1illOiO26400w(0)); + niOl0i11O <= (niOl0l11O OR wire_w_lg_niOl0OO0l20555w(0)); + niOl0i1ii <= (niOO10l1i AND (((((((niOl0i1OO OR niOl0i1Ol) OR niOl0i1Oi) OR niOl0i1lO) OR niOl0i1ll) OR niOl0i1li) OR niOl0i1iO) OR niOl0i1il)); + niOl0i1il <= ((wire_niO01ill_w_lg_n0O0Ol1i21104w(0) AND n0O0OiOO) AND n0O0OiOl); + niOl0i1iO <= ((wire_niO01ill_w_lg_n0ll0OlO21098w(0) AND n0ll0Oll) AND n0ll0Oli); + niOl0i1li <= ((wire_niO01ill_w_lg_n0iOO0il21092w(0) AND n0iOO0ii) AND n0iOO00O); + niOl0i1ll <= ((wire_niO01ill_w_lg_n0i00l0i21086w(0) AND n0i00l1O) AND n0i00l1l); + niOl0i1lO <= ((wire_niO01ill_w_lg_n00ilOOO21080w(0) AND n00ilOOl) AND n00ilOOi); + niOl0i1Oi <= ((wire_niO01ill_w_lg_n01O00ll21074w(0) AND n01O00li) AND n01O00iO); + niOl0i1Ol <= ((wire_niO01ill_w_lg_n011llii21068w(0) AND n011ll0O) AND n011ll0l); + niOl0i1OO <= ((wire_niO01ill_w_lg_n1Oi011O21063w(0) AND n1Oi011l) AND n1Oi011i); + niOl0ii0i <= (niOli101i AND niOl0i0ii); + niOl0ii0l <= ((((((((NOT (wire_niO01ill_w_lg_n1101l1l17904w(0) XOR nlOO0ii0i)) AND (NOT (wire_niO01ill_w_lg_n1101l1O16997w(0) XOR nlOO0ii0l))) AND (NOT (wire_niO01ill_w_lg_n1101l0i16090w(0) XOR nlOO0ii0O))) AND (NOT (wire_niO01ill_w_lg_n1101l0l15183w(0) XOR nlOO0iiii))) AND (NOT (wire_niO01ill_w_lg_n1101l0O14276w(0) XOR nlOO0iiil))) AND (NOT (wire_niO01ill_w_lg_n1101lii13369w(0) XOR nlOO0iiiO))) AND (NOT (wire_niO01ill_w_lg_n1101lil12462w(0) XOR nlOO0iili))) AND (NOT (wire_niO01ill_w_lg_n1101liO11541w(0) XOR nlOO0iill))); + niOl0ii0O <= ((((((((NOT (wire_niO01ill_w_lg_n1101l1l17904w(0) XOR nlOO0iilO)) AND (NOT (wire_niO01ill_w_lg_n1101l1O16997w(0) XOR nlOO0iiOi))) AND (NOT (wire_niO01ill_w_lg_n1101l0i16090w(0) XOR nlOO0iiOl))) AND (NOT (wire_niO01ill_w_lg_n1101l0l15183w(0) XOR nlOO0iiOO))) AND (NOT (wire_niO01ill_w_lg_n1101l0O14276w(0) XOR nlOO0il1i))) AND (NOT (wire_niO01ill_w_lg_n1101lii13369w(0) XOR nlOO0il1l))) AND (NOT (wire_niO01ill_w_lg_n1101lil12462w(0) XOR nlOO0il1O))) AND (NOT (wire_niO01ill_w_lg_n1101liO11541w(0) XOR nlOO0il0i))); + niOl0ii1i <= ((wire_w_lg_niOl0i0OO21015w(0) AND wire_w_lg_niOl0O0Oi20806w(0)) AND niOl0Oiii); + niOl0ii1l <= (niOli101i AND niOl0ii1O); + niOl0ii1O <= ((((((((n1101l1l OR nlOO0il0l) AND (n1101l1O OR nlOO0il0O)) AND (n1101l0i OR nlOO0ilii)) AND (n1101l0l OR nlOO0ilil)) AND (n1101l0O OR nlOO0iliO)) AND (n1101lii OR nlOO0illi)) AND (n1101lil OR nlOO0illl)) AND (n1101liO OR nlOO0illO)); + niOl0iiii <= (niOl0iiiO AND niOl0iiil); + niOl0iiil <= ((((((((NOT ((NOT ((n1Oi001O AND n1Oi01iO) OR n1101l1l)) XOR nlOO0iilO)) AND (NOT ((NOT ((n011lOii AND n011llOi) OR n1101l1O)) XOR nlOO0iiOi))) AND (NOT ((NOT ((n01O0ill AND n01O0i1l) OR n1101l0i)) XOR nlOO0iiOl))) AND (NOT ((NOT ((n00iO1OO AND n00iO10O) OR n1101l0l)) XOR nlOO0iiOO))) AND (NOT ((NOT ((n0i00O0i AND n0i00lli) OR n1101l0O)) XOR nlOO0il1i))) AND (NOT ((NOT ((n0iOOiil AND n0iOO0Ol) OR n1101lii)) XOR nlOO0il1l))) AND (NOT ((NOT ((n0lli1lO AND n0lli11O) OR n1101lil)) XOR nlOO0il1O))) AND (NOT ((NOT ((n0O0OO1i AND n0O0Olii) OR n1101liO)) XOR nlOO0il0i))); + niOl0iiiO <= (niOl0iO1i AND nlOO0ii1i); + niOl0iili <= (niOl0iilO AND wire_w_lg_niOl0iill20999w(0)); + niOl0iill <= (((((((wire_w_lg_niOl0O0lO23571w(0) AND wire_w_lg_niOl0O0ll23570w(0)) AND wire_w_lg_niOl0O0li23569w(0)) AND wire_w_lg_niOl0O0iO23568w(0)) AND wire_w_lg_niOl0O0il23567w(0)) AND wire_w_lg_niOl0O0ii23566w(0)) AND wire_w_lg_niOl0O00O23565w(0)) AND wire_w_lg_niOl0O00l23564w(0)); + niOl0iilO <= (niOl0iiiO AND wire_w_lg_niOl0ii0O21003w(0)); + niOl0iiOi <= (((((((wire_niO01ill_w_lg_nlOO01l0l26130w(0) AND wire_niO01ill_w_lg_nlOO01l0i26131w(0)) AND wire_niO01ill_w_lg_nlOO01l1O26133w(0)) AND wire_niO01ill_w_lg_nlOO01l1l26135w(0)) AND wire_niO01ill_w_lg_nlOO01l1i26137w(0)) AND wire_niO01ill_w_lg_nlOO01iOO26139w(0)) AND wire_niO01ill_w_lg_nlOO01iOl26141w(0)) AND wire_niO01ill_w_lg_nlOO01iOi26143w(0)); + niOl0iiOl <= (wire_w_lg_niOO10lOO8902w(0) AND n11O00iO); + niOl0iiOO <= (n1iO0l0O OR niOl0iliO); + niOl0il0i <= ((((((((NOT ((wire_nlOOO01lO_dataout AND n1Oi1O1l) AND wire_niO01ill_w_lg_n1Oi001O26054w(0))) AND (NOT ((wire_nlOOO01il_dataout AND n011li0O) AND wire_niO01ill_w_lg_n011lOii26058w(0)))) AND (NOT ((wire_nlOOO010i_dataout AND n01O01li) AND wire_niO01ill_w_lg_n01O0ill26063w(0)))) AND (NOT ((wire_nlOOO1OOO_dataout AND n00illOl) AND wire_niO01ill_w_lg_n00iO1OO26068w(0)))) AND (NOT ((wire_nlOOO1Oll_dataout AND n0i00i1O) AND wire_niO01ill_w_lg_n0i00O0i26073w(0)))) AND (NOT ((wire_nlOOO1Oii_dataout AND n0iOO1ii) AND wire_niO01ill_w_lg_n0iOOiil26078w(0)))) AND (NOT ((wire_nlOOO1O1O_dataout AND n0ll0lll) AND wire_niO01ill_w_lg_n0lli1lO26083w(0)))) AND (NOT ((wire_nlOOO1lOl_dataout AND n0O0O0OO) AND wire_niO01ill_w_lg_n0O0OO1i26088w(0)))); + niOl0il0l <= (wire_w_lg_niOO10lOO8902w(0) AND wire_niO01ill_w_lg_w_lg_n11O1O1O20986w20987w(0)); + niOl0il0O <= (nlOOOi1Oi AND wire_w_lg_niOl0il0i20989w(0)); + niOl0il1i <= (niOO10lOO AND (wire_w_lg_niOl0il0O20992w(0) OR wire_w_lg_niOl0il1l20993w(0))); + niOl0il1l <= ((((((((NOT (nlOOOl1ll AND nlOO01Oii)) AND (NOT (nlOOOl1lO AND nlOO01Oil))) AND (NOT (nlOOOl1Oi AND nlOO01OiO))) AND (NOT (nlOOOl1Ol AND nlOO01Oli))) AND (NOT (nlOOOl1OO AND nlOO01Oll))) AND (NOT (nlOOOl01i AND nlOO01OlO))) AND (NOT (nlOOOl01l AND nlOO01OOi))) AND (NOT (nlOOOl01O AND nlOO01OOl))); + niOl0il1O <= (((((((wire_w_lg_niOl0O11l26092w(0) AND wire_w_lg_niOl0lOli26093w(0)) AND wire_w_lg_niOl0lO1O26095w(0)) AND wire_w_lg_niOl0llll26097w(0)) AND wire_w_lg_niOl0ll0i26099w(0)) AND wire_w_lg_niOl0lilO26101w(0)) AND wire_w_lg_niOl0li0l26103w(0)) AND wire_w_lg_niOl0l0Oi26105w(0)); + niOl0ilii <= ((((((((NOT (wire_niO01ill_w_lg_w_lg_n1101l1l17904w26022w(0) XOR wire_niO01ill_w_lg_n1101l1l17904w(0))) AND (NOT (wire_niO01ill_w_lg_w_lg_n1101l1O16997w26025w(0) XOR wire_niO01ill_w_lg_n1101l1O16997w(0)))) AND (NOT (wire_niO01ill_w_lg_w_lg_n1101l0i16090w26029w(0) XOR wire_niO01ill_w_lg_n1101l0i16090w(0)))) AND (NOT (wire_niO01ill_w_lg_w_lg_n1101l0l15183w26033w(0) XOR wire_niO01ill_w_lg_n1101l0l15183w(0)))) AND (NOT (wire_niO01ill_w_lg_w_lg_n1101l0O14276w26037w(0) XOR wire_niO01ill_w_lg_n1101l0O14276w(0)))) AND (NOT (wire_niO01ill_w_lg_w_lg_n1101lii13369w26041w(0) XOR wire_niO01ill_w_lg_n1101lii13369w(0)))) AND (NOT (wire_niO01ill_w_lg_w_lg_n1101lil12462w26045w(0) XOR wire_niO01ill_w_lg_n1101lil12462w(0)))) AND (NOT (wire_niO01ill_w_lg_w_lg_n1101liO11541w26049w(0) XOR wire_niO01ill_w_lg_n1101liO11541w(0)))); + niOl0ilil <= ((n1iO0l0O OR (((wire_niO01ill_w_lg_w_lg_nlOO0iilO20976w20977w(0) AND wire_niO01ill_w_lg_nlOO0iiOi20978w(0)) AND wire_niO01ill_w_lg_nlOO0iiOO20980w(0)) AND wire_niO01ill_w_lg_nlOO0il0i20982w(0))) OR niOl0iliO); + niOl0iliO <= ((((((((NOT ((nlOOOl1ll AND nlOO0i1ii) XOR nlOOOl1ll)) AND (NOT ((nlOOOl1lO AND nlOO0i1il) XOR nlOOOl1lO))) AND (NOT ((nlOOOl1Oi AND nlOO0i1iO) XOR nlOOOl1Oi))) AND (NOT ((nlOOOl1Ol AND nlOO0i1li) XOR nlOOOl1Ol))) AND (NOT ((nlOOOl1OO AND nlOO0i1ll) XOR nlOOOl1OO))) AND (NOT ((nlOOOl01i AND nlOO0i1lO) XOR nlOOOl01i))) AND (NOT ((nlOOOl01l AND nlOO0i1Oi) XOR nlOOOl01l))) AND (NOT ((nlOOOl01O AND nlOO0i1Ol) XOR nlOOOl01O))); + niOl0illi <= ((niOO10lOO AND nlOO0ii1i) AND wire_w_lg_w_lg_w_lg_niOl0ilOl20972w20973w20974w(0)); + niOl0illl <= (nlOO0il0i AND wire_nlOO1iO0l_dataout); + niOl0illO <= (nlOO0iiOO AND wire_nlOO1iO0i_dataout); + niOl0ilOi <= (nlOO0iiOi AND wire_nlOO1iO1O_dataout); + niOl0ilOl <= (nlOO0iilO AND niOl011Ol); + niOl0ilOO <= ((wire_w_lg_niOO10lOO8902w(0) AND nlOO0ii1i) AND niOl0iO1i); + niOl0iO0i <= (n1iO0l0O AND n1lillil); + niOl0iO0l <= (wire_n1l10lli_dataout OR ((niOl0iOii AND n1lillil) AND wire_w_lg_niOl0iO0O20959w(0))); + niOl0iO0O <= (((((((wire_w_lg_niOl0O00i25976w(0) AND wire_w_lg_niOl0O01O25977w(0)) AND wire_w_lg_niOl0O01l25979w(0)) AND wire_w_lg_niOl0O01i25981w(0)) AND wire_w_lg_niOl0O1OO25983w(0)) AND wire_w_lg_niOl0O1Ol25985w(0)) AND wire_w_lg_niOl0O1Oi25987w(0)) AND wire_w_lg_niOl0O1lO25989w(0)); + niOl0iO1i <= (((nlOO0iiOi OR nlOO0iilO) OR nlOO0iiOO) OR nlOO0il0i); + niOl0iO1l <= (nlOO0ii1i AND n1lillil); + niOl0iO1O <= (wire_w_lg_niOlO1O0i20967w(0) AND niOl0iO0i); + niOl0iOii <= ((((((((NOT (niOl0O00i XOR (nlOOOl1ll AND n1Oi1O1l))) AND (NOT (niOl0O01O XOR (nlOOOl1lO AND n011li0O)))) AND (NOT (niOl0O01l XOR (nlOOOl1Oi AND n01O01li)))) AND (NOT (niOl0O01i XOR (nlOOOl1Ol AND n00illOl)))) AND (NOT (niOl0O1OO XOR (nlOOOl1OO AND n0i00i1O)))) AND (NOT (niOl0O1Ol XOR (nlOOOl01i AND n0iOO1ii)))) AND (NOT (niOl0O1Oi XOR (nlOOOl01l AND n0ll0lll)))) AND (NOT (niOl0O1lO XOR (nlOOOl01O AND n0O0O0OO)))); + niOl0iOil <= (niOl0iOiO AND n1lillil); + niOl0iOiO <= (wire_w_lg_w_lg_niOO10lOO8902w21166w(0) OR wire_w_lg_niOO10lOO21168w(0)); + niOl0iOli <= (niOli101i AND wire_w_lg_niOl0l0li20891w(0)); + niOl0iOll <= (wire_niO01ill_w_lg_niOO0Oi0i20950w(0) AND wire_niO01ill_w_lg_niOO0Oi1O20952w(0)); + niOl0iOlO <= (((((((wire_niO01ill_w_lg_nlOO00l0i25930w(0) AND wire_niO01ill_w_lg_nlOO00l1O25931w(0)) AND wire_niO01ill_w_lg_nlOO00l1l25933w(0)) AND wire_niO01ill_w_lg_nlOO00l1i25935w(0)) AND wire_niO01ill_w_lg_nlOO00iOO25937w(0)) AND wire_niO01ill_w_lg_nlOO00iOl25939w(0)) AND wire_niO01ill_w_lg_nlOO00iOi25941w(0)) AND wire_niO01ill_w_lg_nlOO00ilO25943w(0)); + niOl0iOOi <= (wire_nlOi0iili_w_lg_w_lg_w20941w20942w20943w(0) AND wire_niO01ill_w19926w(0)); + niOl0iOOl <= ((((((((NOT ((nlOOOl1ll AND nlOOOiO1l) XOR nlOOOl1ll)) AND (NOT ((nlOOOl1lO AND nlOOOiO1O) XOR nlOOOl1lO))) AND (NOT ((nlOOOl1Oi AND nlOOOiO0i) XOR nlOOOl1Oi))) AND (NOT ((nlOOOl1Ol AND nlOOOiO0l) XOR nlOOOl1Ol))) AND (NOT ((nlOOOl1OO AND nlOOOiO0O) XOR nlOOOl1OO))) AND (NOT ((nlOOOl01i AND nlOOOiOii) XOR nlOOOl01i))) AND (NOT ((nlOOOl01l AND nlOOOiOil) XOR nlOOOl01l))) AND (NOT ((nlOOOl01O AND nlOOOiOiO) XOR nlOOOl01O))); + niOl0iOOO <= (((((((wire_niO01ill_w_lg_n1Oi1l0O27776w(0) AND wire_niO01ill_w_lg_n011l0li27777w(0)) AND wire_niO01ill_w_lg_n01O1OOl27779w(0)) AND wire_niO01ill_w_lg_n00ill1O27781w(0)) AND wire_niO01ill_w_lg_n0i000ii27783w(0)) AND wire_niO01ill_w_lg_n0iOlOll27785w(0)) AND wire_niO01ill_w_lg_n0ll0iOO27787w(0)) AND wire_niO01ill_w_lg_n0O0O00i27789w(0)); + niOl0l00i <= (n1iO0l0O AND (wire_w_lg_niOl0l00O20903w(0) AND niOl0l00l)); + niOl0l00l <= (((((((wire_niO01ill_w_lg_nlOO00OOi25869w(0) AND wire_niO01ill_w_lg_nlOO00OlO25870w(0)) AND wire_niO01ill_w_lg_nlOO00Oll25872w(0)) AND wire_niO01ill_w_lg_nlOO00Oli25874w(0)) AND wire_niO01ill_w_lg_nlOO00OiO25876w(0)) AND wire_niO01ill_w_lg_nlOO00Oil25878w(0)) AND wire_niO01ill_w_lg_nlOO00Oii25880w(0)) AND wire_niO01ill_w_lg_nlOO00O0O25882w(0)); + niOl0l00O <= ((((((((NOT ((nlOO0iilO AND nlOO00lOi) AND nlOOOl1ll)) AND (NOT ((nlOO0iiOi AND nlOO00lOl) AND nlOOOl1lO))) AND (NOT ((nlOO0iiOl AND nlOO00lOO) AND nlOOOl1Oi))) AND (NOT ((nlOO0iiOO AND nlOO00O1i) AND nlOOOl1Ol))) AND (NOT ((nlOO0il1i AND nlOO00O1l) AND nlOOOl1OO))) AND (NOT ((nlOO0il1l AND nlOO00O1O) AND nlOOOl01i))) AND (NOT ((nlOO0il1O AND nlOO00O0i) AND nlOOOl01l))) AND (NOT ((nlOO0il0i AND nlOO00O0l) AND nlOOOl01O))); + niOl0l01i <= (wire_niO01ill_w_lg_niOO0Oi1O20909w(0) AND n1iO0l0O); + niOl0l01l <= (((((((wire_niO01ill_w_lg_nlOO010ll25720w(0) AND wire_niO01ill_w_lg_nlOO010li25721w(0)) AND wire_niO01ill_w_lg_nlOO010iO25723w(0)) AND wire_niO01ill_w_lg_nlOO010il25725w(0)) AND wire_niO01ill_w_lg_nlOO010ii25727w(0)) AND wire_niO01ill_w_lg_nlOO0100O25729w(0)) AND wire_niO01ill_w_lg_nlOO0100l25731w(0)) AND wire_niO01ill_w_lg_nlOO1O1OO25733w(0)); + niOl0l01O <= (((((((niOl1O10l AND niOl1O10i) AND niOl1O11O) AND niOl1O11l) AND niOl1O11i) AND niOl1lOOO) AND niOl1lOOl) AND niOl1lOOi); + niOl0l0ii <= (wire_niO01ill_w20897w(0) AND wire_niO01ill_w_lg_niOO0Oi1l20901w(0)); + niOl0l0il <= ((((((((NOT ((nlOOOl1ll AND nlOOOiliO) XOR nlOOOl1ll)) AND (NOT ((nlOOOl1lO AND nlOOOilli) XOR nlOOOl1lO))) AND (NOT ((nlOOOl1Oi AND nlOOOilll) XOR nlOOOl1Oi))) AND (NOT ((nlOOOl1Ol AND nlOOOillO) XOR nlOOOl1Ol))) AND (NOT ((nlOOOl1OO AND nlOOOilOi) XOR nlOOOl1OO))) AND (NOT ((nlOOOl01i AND nlOOOilOl) XOR nlOOOl01i))) AND (NOT ((nlOOOl01l AND nlOOOilOO) XOR nlOOOl01l))) AND (NOT ((nlOOOl01O AND nlOOOiO1i) XOR nlOOOl01O))); + niOl0l0iO <= ((((((((NOT ((nlOO0iilO AND nlOO00O0O) XOR nlOO0iilO)) AND (NOT ((nlOO0iiOi AND nlOO00Oii) XOR nlOO0iiOi))) AND (NOT ((nlOO0iiOl AND nlOO00Oil) XOR nlOO0iiOl))) AND (NOT ((nlOO0iiOO AND nlOO00OiO) XOR nlOO0iiOO))) AND (NOT ((nlOO0il1i AND nlOO00Oli) XOR nlOO0il1i))) AND (NOT ((nlOO0il1l AND nlOO00Oll) XOR nlOO0il1l))) AND (NOT ((nlOO0il1O AND nlOO00OlO) XOR nlOO0il1O))) AND (NOT ((nlOO0il0i AND nlOO00OOi) XOR nlOO0il0i))); + niOl0l0li <= (((((((wire_niO01ill_w_lg_nlOO0il0i20982w(0) AND wire_niO01ill_w_lg_nlOO0il1O25827w(0)) AND wire_niO01ill_w_lg_nlOO0il1l25829w(0)) AND wire_niO01ill_w_lg_nlOO0il1i25831w(0)) AND wire_niO01ill_w_lg_nlOO0iiOO20980w(0)) AND wire_niO01ill_w_lg_nlOO0iiOl25834w(0)) AND wire_niO01ill_w_lg_nlOO0iiOi20978w(0)) AND wire_niO01ill_w_lg_nlOO0iilO20976w(0)); + niOl0l0ll <= ((wire_w_lg_niOl0li1l20887w(0) AND wire_w_lg_niOl0l0lO20888w(0)) OR nlOO0iill); + niOl0l0lO <= ((n11li1il XOR n0O0O01O) AND wire_nlOO1l01i_dataout); + niOl0l0Oi <= (wire_nlOOO1lOl_dataout AND n0O0O0Ol); + niOl0l0Ol <= ((wire_nlOO1l1il_dataout XOR n0O0OO1i) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0l0OO <= ((wire_nlOO1l1ii_dataout XOR n0O0Olii) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0l10i <= (n11O00Ol AND wire_niO01ill_w_lg_n11O1Oii20948w(0)); + niOl0l10l <= (((wire_nlOi0iili_dataout AND niOl0l1il) OR niOl0l1ii) AND niOl0l10O); + niOl0l10O <= (wire_niO01ill_w_lg_w_lg_n11i111O19857w19858w(0) AND n110OOOO); + niOl0l11i <= (((((((wire_niO01ill_w_lg_n11O011i25915w(0) AND wire_niO01ill_w_lg_n11O1OOO25916w(0)) AND wire_niO01ill_w_lg_n11O1OOl25918w(0)) AND wire_niO01ill_w_lg_n11O1OOi25920w(0)) AND wire_niO01ill_w_lg_n11O1OlO25922w(0)) AND wire_niO01ill_w_lg_n11O1Oll25924w(0)) AND wire_niO01ill_w_lg_n11O1Oli25926w(0)) AND wire_niO01ill_w_lg_n11O1OiO25928w(0)); + niOl0l11l <= ((wire_nlOi0iili_w_lg_dataout20928w(0) AND niOl0l11O) AND niOl0l10O); + niOl0l11O <= (wire_w_lg_niOl0l11i20932w(0) OR wire_w_lg_niOl0iOOO20933w(0)); + niOl0l1ii <= (wire_nlOi0iili_w_lg_dataout20928w(0) AND n11O00li); + niOl0l1il <= (niOO10lOO AND niOl0l11O); + niOl0l1iO <= ((n11i111l AND n11i111i) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOl0l1li <= (wire_w_lg_niOlO1O0i20967w(0) AND n1iO0l0O); + niOl0l1ll <= (wire_niO01ill_w_lg_niOO0Oi0i20918w(0) OR wire_w20922w(0)); + niOl0l1lO <= ((((((((NOT ((nlOO0iilO AND nlOO01l0O) XOR nlOO0iilO)) AND (NOT ((nlOO0iiOi AND nlOO01lii) XOR nlOO0iiOi))) AND (NOT ((nlOO0iiOl AND nlOO01lil) XOR nlOO0iiOl))) AND (NOT ((nlOO0iiOO AND nlOO01liO) XOR nlOO0iiOO))) AND (NOT ((nlOO0il1i AND nlOO01lli) XOR nlOO0il1i))) AND (NOT ((nlOO0il1l AND nlOO01lll) XOR nlOO0il1l))) AND (NOT ((nlOO0il1O AND nlOO01llO) XOR nlOO0il1O))) AND (NOT ((nlOO0il0i AND nlOO01lOi) XOR nlOO0il0i))); + niOl0l1Oi <= (((((((wire_niO01ill_w_lg_nlOO01i0i25781w(0) AND wire_niO01ill_w_lg_nlOO01i1O25782w(0)) AND wire_niO01ill_w_lg_nlOO01i1l25784w(0)) AND wire_niO01ill_w_lg_nlOO01i1i25786w(0)) AND wire_niO01ill_w_lg_nlOO010OO25788w(0)) AND wire_niO01ill_w_lg_nlOO010Ol25790w(0)) AND wire_niO01ill_w_lg_nlOO010Oi25792w(0)) AND wire_niO01ill_w_lg_nlOO010lO25794w(0)); + niOl0l1Ol <= ((((((((NOT ((niil01il AND nlOOOl1ll) XOR nlOOOl1ll)) AND (NOT ((niil01ii AND nlOOOl1lO) XOR nlOOOl1lO))) AND (NOT ((niil0iOO AND nlOOOl1Oi) XOR nlOOOl1Oi))) AND (NOT ((niil0l1l AND nlOOOl1Ol) XOR nlOOOl1Ol))) AND (NOT ((niil0l1O AND nlOOOl1OO) XOR nlOOOl1OO))) AND (NOT ((niil0l0i AND nlOOOl01i) XOR nlOOOl01i))) AND (NOT ((niil0l0l AND nlOOOl01l) XOR nlOOOl01l))) AND (NOT ((niil0liO AND nlOOOl01O) XOR nlOOOl01O))); + niOl0l1OO <= (((((((wire_niO01ill_w_lg_nlOOOiOiO25735w(0) AND wire_niO01ill_w_lg_nlOOOiOil25736w(0)) AND wire_niO01ill_w_lg_nlOOOiOii25738w(0)) AND wire_niO01ill_w_lg_nlOOOiO0O25740w(0)) AND wire_niO01ill_w_lg_nlOOOiO0l25742w(0)) AND wire_niO01ill_w_lg_nlOOOiO0i25744w(0)) AND wire_niO01ill_w_lg_nlOOOiO1O25746w(0)) AND wire_niO01ill_w_lg_nlOOOiO1l25748w(0)); + niOl0li0i <= ((n11li1il XOR n0ll0iOl) AND wire_nlOO1l01i_dataout); + niOl0li0l <= (wire_nlOOO1O1O_dataout AND n0ll0lli); + niOl0li0O <= ((wire_nlOO1l1il_dataout XOR n0lli1lO) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0li1i <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lO0l24102w(0)); + niOl0li1l <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24138w(0) OR (n11O0llO AND niOl1ll0i)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0li1O <= ((wire_w_lg_niOl0liiO20879w(0) AND wire_w_lg_niOl0li0i20880w(0)) OR nlOO0iili); + niOl0liii <= ((wire_nlOO1l1ii_dataout XOR n0lli11O) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0liil <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lO0O24100w(0)); + niOl0liiO <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24134w(0) OR (n11O0llO AND niOl1ll0O)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0lili <= ((wire_w_lg_niOl0ll1i20871w(0) AND wire_w_lg_niOl0lill20872w(0)) OR nlOO0iiiO); + niOl0lill <= ((n11li1il XOR n0iOlOli) AND wire_nlOO1l01i_dataout); + niOl0lilO <= (wire_nlOOO1Oii_dataout AND n0iOO10O); + niOl0liOi <= ((wire_nlOO1l1il_dataout XOR n0iOOiil) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0liOl <= ((wire_nlOO1l1ii_dataout XOR n0iOO0Ol) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0liOO <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lOii24098w(0)); + niOl0ll0i <= (wire_nlOOO1Oll_dataout AND n0i00i1l); + niOl0ll0l <= ((wire_nlOO1l1il_dataout XOR n0i00O0i) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0ll0O <= ((wire_nlOO1l1ii_dataout XOR n0i00lli) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0ll1i <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24130w(0) OR (n11O0llO AND niOl1llil)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0ll1l <= ((wire_w_lg_niOl0llil20863w(0) AND wire_w_lg_niOl0ll1O20864w(0)) OR nlOO0iiil); + niOl0ll1O <= ((n11li1il XOR n0i0000O) AND wire_nlOO1l01i_dataout); + niOl0llii <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lOil24096w(0)); + niOl0llil <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24126w(0) OR (n11O0llO AND niOl1llli)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0lliO <= ((wire_w_lg_niOl0llOO20855w(0) AND wire_w_lg_niOl0llli20856w(0)) OR nlOO0iiii); + niOl0llli <= ((n11li1il XOR n00ill1l) AND wire_nlOO1l01i_dataout); + niOl0llll <= (wire_nlOOO1OOO_dataout AND n00illOi); + niOl0lllO <= ((wire_nlOO1l1il_dataout XOR n00iO1OO) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0llOi <= ((wire_nlOO1l1ii_dataout XOR n00iO10O) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0llOl <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lOiO24094w(0)); + niOl0llOO <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24122w(0) OR (n11O0llO AND niOl1lllO)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0lO0i <= ((wire_nlOO1l1il_dataout XOR n01O0ill) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0lO0l <= ((wire_nlOO1l1ii_dataout XOR n01O0i1l) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0lO0O <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lOli24092w(0)); + niOl0lO1i <= ((wire_w_lg_niOl0lOii20847w(0) AND wire_w_lg_niOl0lO1l20848w(0)) OR nlOO0ii0O); + niOl0lO1l <= ((n11li1il XOR n01O1OOi) AND wire_nlOO1l01i_dataout); + niOl0lO1O <= (wire_nlOOO010i_dataout AND n01O01iO); + niOl0lOii <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24118w(0) OR (n11O0llO AND niOl1llOl)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0lOil <= ((wire_w_lg_niOl0lOOl20839w(0) AND wire_w_lg_niOl0lOiO20840w(0)) OR nlOO0ii0l); + niOl0lOiO <= ((n11li1il XOR n011l0iO) AND wire_nlOO1l01i_dataout); + niOl0lOli <= (wire_nlOOO01il_dataout AND n011li0l); + niOl0lOll <= ((wire_nlOO1l1il_dataout XOR n011lOii) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0lOlO <= ((wire_nlOO1l1ii_dataout XOR n011llOi) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0lOOi <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lOll24090w(0)); + niOl0lOOl <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24114w(0) OR (n11O0llO AND niOl1lO1i)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0lOOO <= ((wire_w_lg_niOl0O10O20831w(0) AND wire_w_lg_niOl0O11i20832w(0)) OR nlOO0ii0i); + niOl0O00i <= (nlOOOl1ll AND nlOO00O0O); + niOl0O00l <= (nlOOOl01O AND nlOO0il0i); + niOl0O00O <= (nlOOOl01l AND nlOO0il1O); + niOl0O01i <= (nlOOOl1Ol AND nlOO00OiO); + niOl0O01l <= (nlOOOl1Oi AND nlOO00Oil); + niOl0O01O <= (nlOOOl1lO AND nlOO00Oii); + niOl0O0ii <= (nlOOOl01i AND nlOO0il1l); + niOl0O0il <= (nlOOOl1OO AND nlOO0il1i); + niOl0O0iO <= (nlOOOl1Ol AND nlOO0iiOO); + niOl0O0li <= (nlOOOl1Oi AND nlOO0iiOl); + niOl0O0ll <= (nlOOOl1lO AND nlOO0iiOi); + niOl0O0lO <= (nlOOOl1ll AND nlOO0iilO); + niOl0O0Oi <= ((NOT (wire_w_lg_niOO10l1i20908w(0) XOR n11li1iO)) AND (NOT (niOO10l1i XOR n11li1li))); + niOl0O0Ol <= ((((((((NOT (wire_n1iiilOl_dataout XOR nlOOOl1ll)) AND (NOT (wire_n1iiilOO_dataout XOR nlOOOl1lO))) AND (NOT (wire_n1iiiO1i_dataout XOR nlOOOl1Oi))) AND (NOT (wire_n1iiiO1l_dataout XOR nlOOOl1Ol))) AND (NOT (wire_n1iiiO1O_dataout XOR nlOOOl1OO))) AND (NOT (wire_n1iiiO0i_dataout XOR nlOOOl01i))) AND (NOT (wire_n1iiiO0l_dataout XOR nlOOOl01l))) AND (NOT (wire_n1iiiO0O_dataout XOR nlOOOl01O))); + niOl0O0OO <= (((((((wire_niO01ill_w_lg_nlOOOl01O24770w(0) AND wire_niO01ill_w_lg_nlOOOl01l24771w(0)) AND wire_niO01ill_w_lg_nlOOOl01i24772w(0)) AND wire_niO01ill_w_lg_nlOOOl1OO24773w(0)) AND wire_niO01ill_w_lg_nlOOOl1Ol24774w(0)) AND wire_niO01ill_w_lg_nlOOOl1Oi24775w(0)) AND wire_niO01ill_w_lg_nlOOOl1lO24776w(0)) AND wire_niO01ill_w_lg_nlOOOl1ll24777w(0)); + niOl0O10i <= ((wire_nlOO1l1ii_dataout XOR n1Oi01iO) OR wire_nlOO1l1iO_w_lg_dataout24024w(0)); + niOl0O10l <= (wire_nlOO1l1il_dataout AND wire_w_lg_niOl1lOlO24088w(0)); + niOl0O10O <= ((wire_niO01ill_w_lg_w_lg_n11O0llO24108w24109w(0) OR (n11O0llO AND niOl1lO1O)) OR wire_nlOO1l1ii_w_lg_dataout24112w(0)); + niOl0O11i <= ((n11li1il XOR n1Oi1l0l) AND wire_nlOO1l01i_dataout); + niOl0O11l <= (wire_nlOOO01lO_dataout AND n1Oi1O1i); + niOl0O11O <= ((wire_nlOO1l1il_dataout XOR n1Oi001O) OR wire_nlOO1l1li_w_lg_dataout24007w(0)); + niOl0O1ii <= ((niOli101i AND niOl0O1ll) AND wire_w_lg_w_lg_niOl0O1li20824w20825w(0)); + niOl0O1il <= ((((((((NOT ((niOl0lOOO AND nlOOOl1ll) XOR nlOOOl1ll)) AND (NOT ((niOl0lOil AND nlOOOl1lO) XOR nlOOOl1lO))) AND (NOT ((niOl0lO1i AND nlOOOl1Oi) XOR nlOOOl1Oi))) AND (NOT ((niOl0lliO AND nlOOOl1Ol) XOR nlOOOl1Ol))) AND (NOT ((niOl0ll1l AND nlOOOl1OO) XOR nlOOOl1OO))) AND (NOT ((niOl0lili AND nlOOOl01i) XOR nlOOOl01i))) AND (NOT ((niOl0li1O AND nlOOOl01l) XOR nlOOOl01l))) AND (NOT ((niOl0l0ll AND nlOOOl01O) XOR nlOOOl01O))); + niOl0O1iO <= (((((((wire_niO01ill_w_lg_nlOO01lOi25605w(0) AND wire_niO01ill_w_lg_nlOO01llO25606w(0)) AND wire_niO01ill_w_lg_nlOO01lll25608w(0)) AND wire_niO01ill_w_lg_nlOO01lli25610w(0)) AND wire_niO01ill_w_lg_nlOO01liO25612w(0)) AND wire_niO01ill_w_lg_nlOO01lil25614w(0)) AND wire_niO01ill_w_lg_nlOO01lii25616w(0)) AND wire_niO01ill_w_lg_nlOO01l0O25618w(0)); + niOl0O1li <= ((((((((NOT (niOl0O00i XOR nlOOOl1ll)) AND (NOT (niOl0O01O XOR nlOOOl1lO))) AND (NOT (niOl0O01l XOR nlOOOl1Oi))) AND (NOT (niOl0O01i XOR nlOOOl1Ol))) AND (NOT (niOl0O1OO XOR nlOOOl1OO))) AND (NOT (niOl0O1Ol XOR nlOOOl01i))) AND (NOT (niOl0O1Oi XOR nlOOOl01l))) AND (NOT (niOl0O1lO XOR nlOOOl01O))); + niOl0O1ll <= ((((((((NOT (niOl0O0lO XOR nlOOOl1ll)) AND (NOT (niOl0O0ll XOR nlOOOl1lO))) AND (NOT (niOl0O0li XOR nlOOOl1Oi))) AND (NOT (niOl0O0iO XOR nlOOOl1Ol))) AND (NOT (niOl0O0il XOR nlOOOl1OO))) AND (NOT (niOl0O0ii XOR nlOOOl01i))) AND (NOT (niOl0O00O XOR nlOOOl01l))) AND (NOT (niOl0O00l XOR nlOOOl01O))); + niOl0O1lO <= (nlOOOl01O AND nlOO00OOi); + niOl0O1Oi <= (nlOOOl01l AND nlOO00OlO); + niOl0O1Ol <= (nlOOOl01i AND nlOO00Oll); + niOl0O1OO <= (nlOOOl1OO AND nlOO00Oli); + niOl0Oi0i <= (n1iO0l0O AND niOl0Oi1i); + niOl0Oi0l <= ((n1il11Ol AND (niOl0Oi0O AND niOli10Ol)) AND nlOlOilOO); + niOl0Oi0O <= (n1iO0l0O OR wire_w_lg_niOl0l1OO20936w(0)); + niOl0Oi1i <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19850w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND n110OOOO); + niOl0Oi1l <= (niOl0Oi0i AND niOl0Oi1O); + niOl0Oi1O <= ((((((((NOT (nlOOOl1ll XOR nlOOOl11O)) AND (NOT (nlOOOl1lO XOR nlOOOl10i))) AND (NOT (nlOOOl1Oi XOR nlOOOl10l))) AND (NOT (nlOOOl1Ol XOR nlOOOl10O))) AND (NOT (nlOOOl1OO XOR nlOOOl1ii))) AND (NOT (nlOOOl01i XOR nlOOOl1il))) AND (NOT (nlOOOl01l XOR nlOOOl1iO))) AND (NOT (nlOOOl01O XOR nlOOOl1li))); + niOl0Oiii <= ((((NOT k_conf(361)) AND k_conf(362)) AND (NOT k_conf(363))) AND (NOT k_conf(364))); + niOl0Oiil <= (((n11O0lli OR n1lillil) OR n11O0liO) OR n11O0O1O); + niOl0OiiO <= (nlOO0011i OR wire_w_lg_niOl0iOOO20933w(0)); + niOl0Oili <= ((((NOT k_gbl_hip(28)) AND wire_w_lg_w_k_gbl_hip_range25481w25482w(0)) AND k_gbl_hip(30)) AND (NOT k_gbl_hip(31))); + niOl0Oill <= ((((NOT k_gbl_hip(28)) AND k_gbl_hip(29)) AND (NOT k_gbl_hip(30))) AND (NOT k_gbl_hip(31))); + niOl0OilO <= ((wire_w_lg_w_k_gbl_hip_range25479w25493w(0) AND (NOT k_gbl_hip(30))) AND (NOT k_gbl_hip(31))); + niOl0OiOi <= ((((NOT k_gbl_hip(28)) AND wire_w_lg_w_k_gbl_hip_range25481w25482w(0)) AND k_gbl_hip(30)) AND k_gbl_hip(31)); + niOl0OiOl <= ((((NOT k_gbl_hip(28)) AND k_gbl_hip(29)) AND (NOT k_gbl_hip(30))) AND k_gbl_hip(31)); + niOl0OiOO <= ((wire_w_lg_w_k_gbl_hip_range25479w25493w(0) AND (NOT k_gbl_hip(30))) AND k_gbl_hip(31)); + niOl0Ol0i <= (wire_nlOi0OO0l_w_lg_dataout20783w(0) AND wire_nlOii10ll_dataout); + niOl0Ol0l <= (wire_nlOii101O_w_lg_dataout20779w(0) OR wire_nlOii101O_w_lg_w_lg_dataout20780w20781w(0)); + niOl0Ol0O <= (((((((((((((((((((wire_niO01ill_w_lg_n1iillil25440w(0) AND wire_niO01ill_w_lg_n1iillii25441w(0)) AND wire_niO01ill_w_lg_n1iill0O25443w(0)) AND wire_niO01ill_w_lg_n1iill0l25445w(0)) AND wire_niO01ill_w_lg_n1iill0i25447w(0)) AND wire_niO01ill_w_lg_n1iill1O25449w(0)) AND wire_niO01ill_w_lg_n1iill1l25451w(0)) AND wire_niO01ill_w_lg_n1iill1i25453w(0)) AND wire_niO01ill_w_lg_n1iiliOO25455w(0)) AND wire_niO01ill_w_lg_n1iiliOl25457w(0)) AND wire_niO01ill_w_lg_n1iiliOi25459w(0)) AND wire_niO01ill_w_lg_n1iililO25461w(0)) AND wire_niO01ill_w_lg_n1iilill25463w(0)) AND wire_niO01ill_w_lg_n1iilili25465w(0)) AND wire_niO01ill_w_lg_n1iiliiO25467w(0)) AND wire_niO01ill_w_lg_n1iiliil25469w(0)) AND wire_niO01ill_w_lg_n1iiliii25471w(0)) AND wire_niO01ill_w_lg_n1iili0O25473w(0)) AND wire_niO01ill_w_lg_n1iili0l25475w(0)) AND wire_niO01ill_w_lg_n11Oi0ii25477w(0)); + niOl0Ol1i <= ((((NOT k_gbl_hip(28)) AND k_gbl_hip(29)) AND k_gbl_hip(30)) AND (NOT k_gbl_hip(31))); + niOl0Ol1l <= ((wire_w_lg_w_k_gbl_hip_range25479w25493w(0) AND k_gbl_hip(30)) AND (NOT k_gbl_hip(31))); + niOl0Ol1O <= (((k_gbl_hip(28) AND k_gbl_hip(29)) AND (NOT k_gbl_hip(30))) AND (NOT k_gbl_hip(31))); + niOl0Olii <= (niOli101O AND n1il11Ol); + niOl0Olil <= ((((wire_niO01ill_w_lg_n1iiOlli25431w(0) AND wire_niO01ill_w_lg_n1iiOliO25432w(0)) AND wire_niO01ill_w_lg_n1iiOlil25434w(0)) AND wire_niO01ill_w_lg_n1iiOlii25436w(0)) AND wire_niO01ill_w_lg_n1iillli25438w(0)); + niOl0OliO <= (n1il11Ol AND n1il11li); + niOl0Olli <= (n1il11Ol AND wire_niO01ill_w_lg_n1il11Oi20651w(0)); + niOl0Olll <= ((n1il11Oi AND n1il11li) AND wire_niO01iOi_w_lg_n1il11Ol20649w(0)); + niOl0OllO <= ((wire_niO01iOi_w_lg_n1il11Ol20649w(0) AND wire_niO01ill_w_lg_n1il11Oi20651w(0)) AND wire_niO01ill_w_lg_n1il11lO20653w(0)); + niOl0OlOi <= (niOl0OlOO AND wire_niO01iOi_w_lg_n1il11Ol20649w(0)); + niOl0OlOl <= (niOli10Ol AND n1lillil); + niOl0OlOO <= (n1il11lO AND niOl0OlOl); + niOl0OO0i <= (n1il101i AND niOli10Ol); + niOl0OO0l <= (((((((wire_w_lg_niOl0OOOi25379w(0) AND wire_w_lg_niOl0OOlO25380w(0)) AND wire_w_lg_niOl0OOll25382w(0)) AND wire_w_lg_niOl0OOli25384w(0)) AND wire_w_lg_niOl0OOiO25386w(0)) AND wire_w_lg_niOl0OOil25388w(0)) AND wire_w_lg_niOl0OOii25390w(0)) AND wire_w_lg_niOl0OO0O25392w(0)); + niOl0OO0O <= (niil0liO AND n111i1Ol); + niOl0OO1i <= (wire_niO01iOi_w_lg_w_lg_n11Oi00O20642w20646w(0) AND wire_niO01ill_w_lg_n1il11il20644w(0)); + niOl0OO1l <= (wire_niO01iOi_w_lg_w_lg_n11Oi00O20642w20643w(0) AND wire_niO01ill_w_lg_n1il11il20644w(0)); + niOl0OO1O <= ((((((((((((((((((wire_niO01ill_w_lg_n1il1i0l25394w(0) AND wire_niO01ill_w_lg_n1il1i0i25395w(0)) AND wire_niO01ill_w_lg_n1il1i1O25397w(0)) AND wire_niO01ill_w_lg_n1il1i1l25399w(0)) AND wire_niO01ill_w_lg_n1il1i1i25401w(0)) AND wire_niO01ill_w_lg_n1il10OO25403w(0)) AND wire_niO01ill_w_lg_n1il10Ol25405w(0)) AND wire_niO01ill_w_lg_n1il10Oi25407w(0)) AND wire_niO01ill_w_lg_n1il10lO25409w(0)) AND wire_niO01ill_w_lg_n1il10ll25411w(0)) AND wire_niO01ill_w_lg_n1il10li25413w(0)) AND wire_niO01ill_w_lg_n1il10iO25415w(0)) AND wire_niO01ill_w_lg_n1il10il25417w(0)) AND wire_niO01ill_w_lg_n1il10ii25419w(0)) AND wire_niO01ill_w_lg_n1il100O25421w(0)) AND wire_niO01ill_w_lg_n1il100l25423w(0)) AND wire_niO01ill_w_lg_n1il100i25425w(0)) AND wire_niO01ill_w_lg_n1il101O25427w(0)) AND wire_niO01ill_w_lg_n1il101l25429w(0)); + niOl0OOii <= (niil0l0l AND n111i1Oi); + niOl0OOil <= (niil0l0i AND n111i1lO); + niOl0OOiO <= (niil0l1O AND n111i1ll); + niOl0OOli <= (niil0l1l AND n111i1li); + niOl0OOll <= (niil0iOO AND n111i1iO); + niOl0OOlO <= (niil01ii AND n111i1il); + niOl0OOOi <= (niil01il AND n111i1ii); + niOl0OOOl <= (((((((((((((((((((wire_nl11llO_w_lg_n1illOii25340w(0) AND wire_nl11llO_w_lg_n1illO0O25341w(0)) AND wire_nl11llO_w_lg_n1illO0l25343w(0)) AND wire_nl11llO_w_lg_n1illO0i25345w(0)) AND wire_nl11llO_w_lg_n1illO1O25347w(0)) AND wire_nl11llO_w_lg_n1illO1l25349w(0)) AND wire_nl11llO_w_lg_n1illO1i25351w(0)) AND wire_nl11llO_w_lg_n1illlOO25353w(0)) AND wire_nl11llO_w_lg_n1illlOl25355w(0)) AND wire_nl11llO_w_lg_n1illlOi25357w(0)) AND wire_nl11llO_w_lg_n1illllO25359w(0)) AND wire_nl11llO_w_lg_n1illlll25361w(0)) AND wire_nl11llO_w_lg_n1illlli25363w(0)) AND wire_nl11llO_w_lg_n1illliO25365w(0)) AND wire_nl11llO_w_lg_n1illlil25367w(0)) AND wire_nl11llO_w_lg_n1illlii25369w(0)) AND wire_nl11llO_w_lg_n1illl0O25371w(0)) AND wire_nl11llO_w_lg_n1illl0l25373w(0)) AND wire_nl11llO_w_lg_n1illl0i25375w(0)) AND wire_nl11llO_w_lg_n1illl1O25377w(0)); + niOl0OOOO <= (niOli111l AND n1lillil); + niOl1000i <= (nlOi0l01l XOR nlOi0l1OO); + niOl1000l <= (((((((((((((NOT (wire_niO111iO_dataout XOR nlOi0l00O)) AND (NOT (wire_niO111li_dataout XOR nlOi0l0ii))) AND (NOT (wire_niO111ll_dataout XOR nlOi0l0il))) AND (NOT (wire_niO111lO_dataout XOR nlOi0l0iO))) AND (NOT (wire_niO111Oi_dataout XOR nlOi0l0li))) AND (NOT (wire_niO111Ol_dataout XOR nlOi0l0ll))) AND (NOT (wire_niO111OO_dataout XOR nlOi0l0lO))) AND (NOT (wire_niO1101i_dataout XOR nlOi0l0Oi))) AND (NOT (wire_niO1101l_dataout XOR nlOi0l0Ol))) AND (NOT (wire_niO1101O_dataout XOR nlOi0l0OO))) AND (NOT (wire_niO1100i_dataout XOR nlOi0li1i))) AND (NOT (wire_niO1100l_dataout XOR nlOi0li1l))) AND (NOT (wire_niO1100O_dataout XOR nlOi0li1O))); + niOl1000O <= (nlOi0l01O XOR nlOi0l1ll); + niOl1001i <= (nlOi00i1l XOR nlOi000li); + niOl1001l <= (nlOi0i10i XOR nlOi0i11l); + niOl1001O <= (nlOi0i10l XOR nlOi00OOi); + niOl100ii <= (nlOi0O10O XOR nlOi0lOOl); + niOl100il <= (nlOi0O0OO XOR nlOi0O0il); + niOl100iO <= (nlOi0OliO XOR nlOi0Ol1l); + niOl100li <= (nlOii111O XOR nlOi0OOll); + niOl100ll <= (nlOii1ilO XOR nlOii1i0l); + niOl100lO <= (nlOii1O0O XOR nlOii1lOl); + niOl100Oi <= (nlOii01OO XOR nlOii01il); + niOl100Ol <= (nlOii0iiO XOR nlOii0i1l); + niOl100OO <= (nlOiii0iO XOR nlOiii01l); + niOl1010i <= (((wire_nl1000i_w_lg_nlO0OlOii28872w(0) AND niOl1010O) OR niOl1010l) AND wire_nlOl1l0Ol_dataout); + niOl1010l <= (wire_nl1000i_w_lg_nlOi1Ol1i29713w(0) AND wire_nl1000i_w_lg_nlOi1OiOO29159w(0)); + niOl1010O <= ((((((((((wire_nl1000i_w_lg_nlO0liiOi29715w(0) AND wire_nl1000i_w_lg_nlO0liilO29716w(0)) AND wire_nl1000i_w_lg_nlO0liill29718w(0)) AND wire_nl1000i_w_lg_nlO0liili29720w(0)) AND wire_nl1000i_w_lg_nlO0liiiO29722w(0)) AND wire_nl1000i_w_lg_nlO0liiil29724w(0)) AND wire_nl1000i_w_lg_nlO0liiii29726w(0)) AND wire_nl1000i_w_lg_nlO0lii0O29728w(0)) AND wire_nl1000i_w_lg_nlO0lii0l29730w(0)) AND wire_nl1000i_w_lg_nlO0lii0i29732w(0)) AND wire_nl1000i_w_lg_nlO0lii1O29734w(0)); + niOl1011i <= ((nlOi1Ol1i AND wire_nlOl1l0Ol_dataout) AND nlO0OlOii); + niOl1011l <= (wire_nlOi1Oiil_dataout OR wire_nlOi1Oi0i_dataout); + niOl1011O <= (((((((wire_nlOi01i1l_w_lg_dataout29698w(0) AND wire_nlOi01i1i_w_lg_dataout29699w(0)) AND wire_nlOi010OO_w_lg_dataout29701w(0)) AND wire_nlOi010Ol_w_lg_dataout29703w(0)) AND wire_nlOi010Oi_w_lg_dataout29705w(0)) AND wire_nlOi010lO_w_lg_dataout29707w(0)) AND wire_nlOi010ll_w_lg_dataout29709w(0)) AND wire_nlOi010li_w_lg_dataout29711w(0)); + niOl101ii <= ((((wire_nl1000i_w29780w(0) AND wire_nl1000i_w_lg_nlOi1OiOl29642w(0)) AND wire_nl1000i_w_lg_nlOi1OiOi29643w(0)) AND wire_nl1000i_w_lg_nlOi1OilO29645w(0)) AND wire_nl1000i_w_lg_nlOi1Oill29647w(0)); + niOl101il <= (((((((wire_nilOO0Oi_w_lg_dataout29675w(0) AND wire_nilOO11l_w_lg_dataout29684w(0)) AND wire_nilOO11i_w_lg_dataout29686w(0)) AND wire_nlillO1iO_w_lg_dataout29688w(0)) AND wire_nl1000i_w_lg_nll0liiOl29690w(0)) AND wire_nl1000i_w_lg_nll0liiOi29692w(0)) AND wire_w_lg_niOl101iO29694w(0)) AND wire_w_lg_niOl101lO29696w(0)); + niOl101iO <= (wire_nl1000i_w_lg_nlll1OOil35170w(0) AND nlll1il0i); + niOl101li <= (wire_nilOOi1O_w_lg_dataout29667w(0) AND wire_nlOi0lO0i_w_lg_dataout28858w(0)); + niOl101ll <= (wire_nl1000i_w_lg_nlilOO0iO5228w(0) AND wire_nlOi0lO0i_w_lg_dataout28858w(0)); + niOl101lO <= (wire_nilOi11O_dataout AND wire_nl1000i_w_lg_nlliOl10O28856w(0)); + niOl101Oi <= (nlliiilil AND wire_nl1000i_w_lg_nlliiilii28850w(0)); + niOl101Ol <= ((wire_nl11llO_w_lg_nlillOlOi42768w(0) AND (((NOT (nlillOl1i XOR nlliiil1l)) AND (NOT (nlillOl1l XOR nlliiil1O))) AND (NOT (nlillOl1O XOR nlliiil0i)))) AND ((wire_nl1000i_w_lg_nlillil1i42778w(0) OR wire_nl1000i_w_lg_nlilliiOO42779w(0)) OR wire_nl1000i_w_lg_nlilliiOl42781w(0))); + niOl101OO <= (nlOi001il XOR nlOi0011i); + niOl10i0i <= (nlOiiO1il XOR nlOiiO10O); + niOl10i0l <= (nlOiiO1iO XOR nlOiiO11l); + niOl10i0O <= (nlOiiOO1l XOR nlOiiOlOO); + niOl10i1i <= (nlOiil0ii XOR nlOiil00l); + niOl10i1l <= ((((((((NOT (nlOiil0ll XOR nlOlO0lOO)) AND (NOT (nlOiil0lO XOR nlOlOi1Oi))) AND (NOT (nlOiil0Oi XOR nlOlOi1Ol))) AND (NOT (nlOiil0Ol XOR nlOlOi1OO))) AND (NOT (nlOiil0OO XOR nlOlOi01i))) AND (NOT (nlOiili1i XOR nlOlOi01l))) AND (NOT (nlOiili1l XOR nlOlOi01O))) AND (NOT (nlOiili1O XOR nlOlOi00i))); + niOl10i1O <= (nlOiil0il XOR nlOiil01i); + niOl10iii <= (((((NOT (nlOiiOO0O XOR wire_n1l10OlO_dataout)) AND (NOT (nlOiiOOii XOR wire_n1l10OOi_dataout))) AND (NOT (nlOiiOOil XOR wire_n1l10OOl_dataout))) AND (NOT (nlOiiOOiO XOR wire_n1l10OOO_dataout))) AND (NOT (nlOiiOOli XOR wire_n1l1i11i_dataout))); + niOl10iil <= (nlOiiOO1O XOR nlOiiOlll); + niOl10iiO <= (((NOT (niOl10ilO OR wire_w_lg_niOl10ill28541w(0))) AND niOl10l1i) XOR nlOil1i1i); + niOl10ili <= ((wire_w_lg_w_lg_niOl10ilO28539w28540w(0) AND wire_w_lg_niOl10ill28541w(0)) XOR nlOil10OO); + niOl10ill <= (nlOil1i1i XOR nlOil10OO); + niOl10ilO <= (wire_w_lg_niOl10l1l28529w(0) OR wire_w_lg_niOl10iOl28534w(0)); + niOl10iOi <= ((wire_w_lg_niOl10iOl28534w(0) AND (niOl10l1l AND niOl10l1i)) XOR nlOil10Ol); + niOl10iOl <= ((nlOil10OO XOR nlOil10Ol) XOR nlOil1i1i); + niOl10iOO <= ((wire_w_lg_niOl10l1l28529w(0) AND niOl10l1i) XOR nlOil10Oi); + niOl10l0i <= (nlOil1OOO XOR nlOil1OOl); + niOl10l0l <= (niOl10l0O XOR nlOil01li); + niOl10l0O <= (nlOil01lO XOR nlOil01ll); + niOl10l1i <= (niOl1i10O AND wire_w_lg_niOl1i1ii28036w(0)); + niOl10l1l <= (((nlOil10Ol XOR nlOil10Oi) XOR nlOil10OO) XOR nlOil1i1i); + niOl10l1O <= (niOl10l0i XOR nlOil1OOi); + niOl10lii <= (nlOil010i XOR nlOil011O); + niOl10lil <= (wire_w_lg_niOl10lli28474w(0) OR wire_w_lg_niOl10liO28475w(0)); + niOl10liO <= ((nlOil011O XOR nlOil011l) XOR nlOil010i); + niOl10lli <= (((nlOil011l XOR nlOil011i) XOR nlOil011O) XOR nlOil010i); + niOl10lll <= (nlOili1Oi XOR nlOili10O); + niOl10llO <= (((NOT (niOl10lOO OR wire_w_lg_niOl10lOl28356w(0))) AND wire_w_lg_niOl1i11O28120w(0)) XOR nlOiliiOO); + niOl10lOi <= (((wire_w_lg_niOl10lOO28354w(0) AND wire_w_lg_niOl1i11O28120w(0)) AND wire_w_lg_niOl10lOl28356w(0)) XOR nlOiliiOl); + niOl10lOl <= (nlOiliiOO XOR nlOiliiOl); + niOl10lOO <= (wire_w_lg_niOl10O0i28344w(0) OR wire_w_lg_niOl10O1l28349w(0)); + niOl10O0i <= (((nlOiliiOi XOR nlOiliilO) XOR nlOiliiOl) XOR nlOiliiOO); + niOl10O0l <= (niOl10O0O XOR nlOill1lO); + niOl10O0O <= (nlOill1Ol XOR nlOill1Oi); + niOl10O1i <= ((wire_w_lg_niOl10O1l28349w(0) AND wire_w_lg_niOl10O0i28350w(0)) XOR nlOiliiOi); + niOl10O1l <= ((nlOiliiOl XOR nlOiliiOi) XOR nlOiliiOO); + niOl10O1O <= ((wire_w_lg_niOl10O0i28344w(0) AND wire_w_lg_niOl1i11O28120w(0)) XOR nlOiliilO); + niOl10Oii <= (niOl10Oil XOR nlOill0iO); + niOl10Oil <= (nlOill0ll XOR nlOill0li); + niOl10OiO <= (nlOill01O XOR nlOill01l); + niOl10Oli <= (wire_w_lg_niOl10OlO28289w(0) OR wire_w_lg_niOl10Oll28290w(0)); + niOl10Oll <= ((nlOill01l XOR nlOill01i) XOR nlOill01O); + niOl10OlO <= (((nlOill01i XOR nlOill1OO) XOR nlOill01l) XOR nlOill01O); + niOl10OOi <= (nlOilO0lO XOR nlOilO00l); + niOl10OOl <= (nlOilOl0O XOR nlOilOiOl); + niOl10OOO <= (nlOilOOOO XOR nlOilOOil); + niOl1100i <= (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlOl XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1l_dataout XOR wire_nlO0i0i1i_dataout))))))))))))))))))))))))); + niOl1100l <= (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOl0O XOR (nlO1lOl1l XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOill XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO1ii)))))))))))))))))))))); + niOl1100O <= (nlO1lOO0l XOR (nlO1lOO1l XOR (nlO1lOlOl XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1l XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiil XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1l_dataout XOR wire_nlO0i00Ol_dataout))))))))))))))))))))))))))))); + niOl1101i <= (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0l XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOi XOR (nlO1lOill XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOO10l))))))))))))))))))))))))))))))); + niOl1101l <= (nlO1lOO0O XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1l_dataout XOR wire_nlO0i00Oi_dataout))))))))))))))))))))))))))))); + niOl1101O <= (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOiii XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO10O)))))))))))))))))))))))))))))); + niOl110ii <= (nlO1lOO0i XOR (nlO1lOO1i XOR (nlO1lOlOi XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1i XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOiii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i1O_dataout XOR wire_nlO0i00OO_dataout))))))))))))))))))))))))))))); + niOl110il <= (nlO1lOO0O XOR (nlO1lOO1O XOR (nlO1lOlOO XOR (nlO1lOllO XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOiOO XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOO11l)))))))))))))))))))))))))))))); + niOl110iO <= (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO1l XOR (nlO1lOlOl XOR (nlO1lOlll XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOiOl XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiii XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOlOOO))))))))))))))))))))))))))))))); + niOl110li <= (nlO1lOO0O XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlli XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOiOl XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOO11l)))))))))))))))))))))))))))))))); + niOl110ll <= (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOliO XOR (nlO1lOl0O XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOiOl XOR (nlO1lOili XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO11i))))))))))))))))))))))); + niOl110lO <= (nlO1lOO0i XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOlil XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR wire_nlO0i00OO_dataout))))))))))))))))))))))); + niOl110Oi <= (nlO1lOO0O XOR (nlO1lOO1O XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlii XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOO XOR (nlO1lOiOi XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR niOiOO11l)))))))))))))))))))))))); + niOl110Ol <= (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOiOl XOR (nlO1lOill XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR niOiOlOli)))))))))))))))))))))))); + niOl110OO <= (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000l_dataout XOR niOiOlOiO))))))))))))))))))))))); + niOl1110i <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil00l); + niOl1110l <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOl11OO); + niOl1110O <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil10O); + niOl1111i <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil01l); + niOl1111l <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil01O); + niOl1111O <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil00i); + niOl111ii <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1ii); + niOl111il <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1il); + niOl111iO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1iO); + niOl111li <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1li); + niOl111ll <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1ll); + niOl111lO <= (wire_nl1000i_w_lg_nlO0il00i29492w(0) XOR nllOil1lO); + niOl111Oi <= (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOiOO XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOili XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOO10i)))))))))))))))))))))))))))))); + niOl111Ol <= (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOlOO XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOl0i XOR (nlO1lOl1i XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOO11O)))))))))))))))))))))))))))); + niOl111OO <= (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOlOl XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOl1O XOR (nlO1lOiOO XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOO10i)))))))))))))))))))))))))))); + niOl11i0i <= (nlO1lOO0O XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOlll XOR (nlO1lOliO XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOiOO XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOiii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOlOOl))))))))))))))))))))))); + niOl11i0l <= (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlli XOR (nlO1lOlil XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOiOl XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOi0O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOlOOO))))))))))))))))))))))))); + niOl11i0O <= (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOliO XOR (nlO1lOlii XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOiOi XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO11O)))))))))))))))))))))))))); + niOl11i1i <= (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl1O XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOili XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i000O_dataout XOR niOiOlOiO))))))))))))))))))); + niOl11i1l <= (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOlll XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl1l XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOiiO XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOlOlO)))))))))))))))))))))); + niOl11i1O <= (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOlli XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1i XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOiil XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOlOOi)))))))))))))))))))))); + niOl11iii <= (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOl0l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOili XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOO1ii)))))))))))))))))))))); + niOl11iil <= (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOl0i XOR (nlO1lOiOO XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOiiO XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR (wire_nlO0i0i1i_dataout XOR niOiOO11O)))))))))))))))))))))))); + niOl11iiO <= (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOl1O XOR (nlO1lOiOl XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOiil XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOO11i))))))))))))))))))))))))); + niOl11ili <= (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOl1l XOR (nlO1lOiOi XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOlOil))))))))))))))))))))))))); + niOl11ill <= (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOl1i XOR (nlO1lOilO XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOi0O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOlOOi)))))))))))))))))))))))))); + niOl11ilO <= (nlO1lOO0O XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOiOO XOR (nlO1lOill XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1O0l1i XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOlOOl))))))))))))))))))))))))))); + niOl11iOi <= (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl1i XOR (nlO1lOiOi XOR (nlO1lOiil XOR (nlO1lOiii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR niOiOO11i))))))))))))))))))))))); + niOl11iOl <= (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl0i XOR (nlO1lOiOO XOR (nlO1lOilO XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOlOil))))))))))))))))))))))); + niOl11iOO <= wire_w_lg_w_k_conf_range29168w29457w(0); + niOl11l0i <= (wire_nl1000i_w_lg_w_lg_w29769w29771w29774w(0) AND wire_nl1000i_w_lg_nlO0liiOl29775w(0)); + niOl11l0l <= (wire_nl1000i_w_lg_nlO0iOiOO29413w(0) AND niOl11lii); + niOl11l0O <= (k_conf(216) AND niOl11lii); + niOl11l1i <= (wire_nl1000i_w_lg_nlO0li0OO29490w(0) OR nlO00O11i); + niOl11l1l <= (k_conf(216) AND nlO00lOlO); + niOl11l1O <= (wire_nl1000i_w_lg_nlO0lii1i29421w(0) OR nlO00O11i); + niOl11lii <= ((wire_nl1000i_w_lg_w29769w29771w(0) AND wire_nl1000i_w_lg_nlO0liiOO29772w(0)) AND nlO0liiOl); + niOl11lil <= (wire_nl1000i_w_lg_w29769w29771w(0) AND wire_nl1000i_w_lg_nlO0liiOO29772w(0)); + niOl11liO <= (wire_nlOi01O0i_dataout AND wire_nlO0O000O_w_lg_dataout28852w(0)); + niOl11lli <= (wire_nlO0Oi1Oi_dataout AND (wire_nlOi01O0i_w_lg_dataout29166w(0) OR wire_nlO0O0OOi_w_lg_w_lg_dataout29186w29291w(0))); + niOl11lll <= (wire_nlO0O0OOi_dataout AND niOl11liO); + niOl11llO <= ((wire_nlO0Oi1Oi_dataout AND wire_nlO0O0OOi_dataout) AND niOl11liO); + niOl11lOi <= (nlO0OlOii AND wire_nlOl1l0Ol_dataout); + niOl11lOl <= (((((((((wire_nl1000i_w_lg_nlO0liiOi29715w(0) AND wire_nl1000i_w_lg_nlO0liilO29716w(0)) AND wire_nl1000i_w_lg_nlO0liill29718w(0)) AND wire_nl1000i_w_lg_nlO0liili29720w(0)) AND wire_nl1000i_w_lg_nlO0liiiO29722w(0)) AND wire_nl1000i_w_lg_nlO0liiil29724w(0)) AND wire_nl1000i_w_lg_nlO0liiii29726w(0)) AND wire_nl1000i_w_lg_nlO0lii0O29728w(0)) AND wire_nl1000i_w_lg_nlO0lii0l29730w(0)) AND wire_nl1000i_w_lg_nlO0lii0i29732w(0)); + niOl11lOO <= (wire_nlO0Oi1lO_w_lg_dataout29185w(0) AND wire_nlO0O0OOi_w_lg_dataout29186w(0)); + niOl11O0i <= (nlOi1OiOO AND nlO00O11l); + niOl11O0l <= (nlOi1OiOO AND wire_nl11llO_w_lg_nlO00O11l29156w(0)); + niOl11O0O <= (wire_nlOi1liiO_dataout XOR niOl11Oll); + niOl11O1i <= (wire_nlO0Oi1lO_dataout AND wire_nlO0O0OOi_dataout); + niOl11O1l <= (wire_nlO0Oi1Oi_dataout AND niOl11O1O); + niOl11O1O <= (((((((((wire_nlO0O0Oii_w_lg_dataout29736w(0) AND wire_nlO0O0O0O_w_lg_dataout29737w(0)) AND wire_nlO0O0O0l_w_lg_dataout29739w(0)) AND wire_nlO0O0O0i_w_lg_dataout29741w(0)) AND wire_nlO0O0O1O_w_lg_dataout29743w(0)) AND wire_nlO0O0O1l_w_lg_dataout29745w(0)) AND wire_nlO0O0O1i_w_lg_dataout29747w(0)) AND wire_nlO0O0lOO_w_lg_dataout29749w(0)) AND wire_nlO0O0lOl_w_lg_dataout29751w(0)) AND wire_nlO0O0lOi_w_lg_dataout29753w(0)); + niOl11Oii <= (wire_nlOi1lili_dataout XOR niOl11Oil); + niOl11Oil <= (wire_nlOi1liil_dataout XOR wire_nlOi1li0O_dataout); + niOl11OiO <= (wire_nlOi1liiO_dataout XOR niOl11Oli); + niOl11Oli <= (wire_nlOi1liil_dataout XOR niOl11Oll); + niOl11Oll <= (wire_nlOi1liii_dataout XOR wire_nlOi1li0O_dataout); + niOl11OlO <= (wire_nlOi1liil_dataout XOR wire_nlOi1liii_dataout); + niOl11OOi <= (nlOi1Ol1O OR nlOi1OilO); + niOl11OOl <= (nlOi1Ol1i AND niOl11OOO); + niOl11OOO <= (wire_nlOi1O0ll_o OR nlO0OlOii); + niOl1i00i <= ((n11O0llO OR n11O0lil) AND n1lillil); + niOl1i00l <= ((niOl0110i OR ((wire_n11010iO_w_lg_w_lg_o24929w24930w(0) OR wire_n110100l_w_lg_w_lg_o24931w24932w(0)) OR (niOl011ii AND niOli1iOO))) AND n1lillil); + niOl1i00O <= ((((((((((((((NOT wire_n110100O_o(14)) AND (NOT (wire_n110100O_o(1) XOR nlOliO0ll))) AND (NOT (wire_n110100O_o(2) XOR nlOll01iO))) AND (NOT (wire_n110100O_o(3) XOR nlOll01li))) AND (NOT (wire_n110100O_o(4) XOR nlOll01ll))) AND (NOT (wire_n110100O_o(5) XOR nlOll01lO))) AND (NOT (wire_n110100O_o(6) XOR nlOll01Oi))) AND (NOT (wire_n110100O_o(7) XOR nlOll01Ol))) AND (NOT (wire_n110100O_o(8) XOR nlOll01OO))) AND (NOT (wire_n110100O_o(9) XOR nlOll001i))) AND (NOT (wire_n110100O_o(10) XOR nlOll001l))) AND (NOT (wire_n110100O_o(11) XOR nlOll001O))) AND (NOT (wire_n110100O_o(12) XOR nlOll000i))) AND (NOT (wire_n110100O_o(13) XOR nlOll000l))); + niOl1i01i <= (niOlO1O0i AND wire_niO01ill_w_lg_n11O0O1O25056w(0)); + niOl1i01l <= ((wire_w_lg_niOl1i01O24999w(0) AND n1lillil) AND niOl011il); + niOl1i01O <= ((((((((((((wire_niO01ill_w_lg_nlOll000i26820w(0) AND wire_niO01ill_w_lg_nlOll001O26822w(0)) AND wire_niO01ill_w_lg_nlOll001l26824w(0)) AND wire_niO01ill_w_lg_nlOll001i26826w(0)) AND (NOT (wire_nlOlOi10l_dataout XOR nlOliO0ll))) AND (NOT (wire_nlOlOi10O_dataout XOR nlOll01iO))) AND (NOT (wire_nlOlOi1ii_dataout XOR nlOll01li))) AND (NOT (wire_nlOlOi1il_dataout XOR nlOll01ll))) AND (NOT (wire_nlOlOi1iO_dataout XOR nlOll01lO))) AND (NOT (wire_nlOlOi1li_dataout XOR nlOll01Oi))) AND (NOT (wire_nlOlOi1ll_dataout XOR nlOll01Ol))) AND (NOT (wire_nlOlOi1lO_dataout XOR nlOll01OO))) AND (NOT (wire_nlOii0Oii_dataout XOR nlOll000l))); + niOl1i0ii <= ((((((((((((((NOT wire_n11010li_o(13)) AND (NOT (wire_nlOlOi10l_dataout XOR nlOliO0ll))) AND (NOT (wire_n11010li_o(1) XOR nlOll01iO))) AND (NOT (wire_n11010li_o(2) XOR nlOll01li))) AND (NOT (wire_n11010li_o(3) XOR nlOll01ll))) AND (NOT (wire_n11010li_o(4) XOR nlOll01lO))) AND (NOT (wire_n11010li_o(5) XOR nlOll01Oi))) AND (NOT (wire_n11010li_o(6) XOR nlOll01Ol))) AND (NOT (wire_n11010li_o(7) XOR nlOll01OO))) AND (NOT (wire_n11010li_o(8) XOR nlOll001i))) AND (NOT (wire_n11010li_o(9) XOR nlOll001l))) AND (NOT (wire_n11010li_o(10) XOR nlOll001O))) AND (NOT (wire_n11010li_o(11) XOR nlOll000i))) AND (NOT (wire_n11010li_o(12) XOR nlOll000l))); + niOl1i0il <= (wire_niO01ill_w_lg_w_lg_nlOlOiliO21217w23459w(0) AND wire_w_lg_w_lg_niOl0Ol0l24926w24927w(0)); + niOl1i0iO <= (wire_nlOii0lOl_w_lg_dataout24922w(0) AND wire_w_lg_niOl0Ol0l24924w(0)); + niOl1i0li <= (((((((((((((wire_niO01ill_w_lg_nlOlliOlO27861w(0) AND wire_niO01ill_w_lg_nlOlliO1l27862w(0)) AND wire_niO01ill_w_lg_nlOlliO1i27864w(0)) AND (NOT (nlOlliO1O XOR nlOllil0l))) AND (NOT (nlOlliO0i XOR nlOllil0O))) AND (NOT (nlOlliO0l XOR nlOllilii))) AND (NOT (nlOlliO0O XOR nlOllilil))) AND (NOT (nlOlliOii XOR nlOlliliO))) AND (NOT (nlOlliOil XOR nlOllilli))) AND (NOT (nlOlliOiO XOR nlOllilll))) AND (NOT (nlOlliOli XOR nlOllillO))) AND (NOT (nlOlliOll XOR nlOllilOi))) AND (NOT (nlOlliOOi XOR nlOllilOl))) AND (NOT (nlOlliOOl XOR nlOllilOO))); + niOl1i0ll <= (niOl1l11O OR niOl1i0lO); + niOl1i0lO <= ((((((((NOT (wire_niO01ill_w_lg_n1101l1l17904w(0) XOR wire_niO01ill_w_lg_w_lg_n1101l1l17904w27830w(0))) AND (NOT (wire_niO01ill_w_lg_n1101l1O16997w(0) XOR wire_niO01ill_w_lg_w_lg_n1101l1O16997w27833w(0)))) AND (NOT (wire_niO01ill_w_lg_n1101l0i16090w(0) XOR wire_niO01ill_w_lg_w_lg_n1101l0i16090w27837w(0)))) AND (NOT (wire_niO01ill_w_lg_n1101l0l15183w(0) XOR wire_niO01ill_w_lg_w_lg_n1101l0l15183w27841w(0)))) AND (NOT (wire_niO01ill_w_lg_n1101l0O14276w(0) XOR wire_niO01ill_w_lg_w_lg_n1101l0O14276w27845w(0)))) AND (NOT (wire_niO01ill_w_lg_n1101lii13369w(0) XOR wire_niO01ill_w_lg_w_lg_n1101lii13369w27849w(0)))) AND (NOT (wire_niO01ill_w_lg_n1101lil12462w(0) XOR wire_niO01ill_w_lg_w_lg_n1101lil12462w27853w(0)))) AND (NOT (wire_niO01ill_w_lg_n1101liO11541w(0) XOR wire_niO01ill_w_lg_w_lg_n1101liO11541w27857w(0)))); + niOl1i0Oi <= (wire_niO01ill_w_lg_n111i10O9993w(0) AND nlOO1O1Oi); + niOl1i0Ol <= (wire_w_lg_niOl0Ol0i21223w(0) AND (wire_nlOii10ii_w_lg_dataout23869w(0) AND (niOl1Olli AND nlOO1O1Ol))); + niOl1i0OO <= ((((((((NOT (n111i1ii AND (wire_niO10O1l_dataout AND (wire_niO10lOl_dataout OR ni1110ii)))) AND (NOT (n111i1il AND (wire_niO10l1l_dataout AND (wire_niO10iOl_dataout OR ni11OOOl))))) AND (NOT (n111i1iO AND (wire_niO10i1l_dataout AND (wire_niO100Ol_dataout OR ni10Ol0O))))) AND (NOT (n111i1li AND (wire_niO1001l_dataout AND (wire_niO101Ol_dataout OR ni1iO0Oi))))) AND (NOT (n111i1ll AND (wire_niO1011l_dataout AND (wire_niO11OOl_dataout OR ni1lO10l))))) AND (NOT (n111i1lO AND (wire_niO11O1l_dataout AND (wire_niO11lOl_dataout OR ni1OlllO))))) AND (NOT (n111i1Oi AND (wire_niO11l1l_dataout AND (wire_niO11iOl_dataout OR ni01li0i))))) AND (NOT (n111i1Ol AND (wire_niO11i1l_dataout AND (wire_niO110Ol_dataout OR ni00l1ll))))); + niOl1i10i <= (wire_nlOiOl1lO_dataout AND (wire_nlOiOl1ll_w_lg_dataout18919w(0) AND n1lO0lOl)); + niOl1i10l <= (k_gbl_hip(23) AND niOl1i10O); + niOl1i10O <= (wire_niO01iOi_w_lg_w_lg_nlOiOO1lO28034w28035w(0) AND wire_w_lg_niOl1i1ii28036w(0)); + niOl1i11i <= (((wire_niO01ill_w28257w(0) AND wire_niO01ill_w_lg_nlOiO101l28258w(0)) AND wire_niO01ill_w_lg_nlOiO101i28260w(0)) AND nlOiO11OO); + niOl1i11l <= ((((nlOiO10Oi AND nlOiO10lO) AND nlOiO10ll) AND nlOiO10li) AND nlOiO10iO); + niOl1i11O <= ((((NOT (nlOiliilO XOR nlOiliiil)) AND (NOT (nlOiliiOi XOR nlOiliiiO))) AND (NOT (nlOiliiOl XOR nlOiliili))) AND (NOT (nlOiliiOO XOR nlOiliill))); + niOl1i1ii <= ((((NOT (nlOil10Oi XOR nlOil10iO)) AND (NOT (nlOil10Ol XOR nlOil10li))) AND (NOT (nlOil10OO XOR nlOil10ll))) AND (NOT (nlOil1i1i XOR nlOil10lO))); + niOl1i1il <= ((NOT k_gbl_hip(23)) OR niOl1i1iO); + niOl1i1iO <= (nlOl1li0l AND (nlO1Oi10i OR (nlO1Oi1lO OR nlOl1li0i))); + niOl1i1li <= ((((((((NOT (nlOOOl1ll AND (nlOliiO0l AND n1Oi101O))) AND (NOT (nlOOOl1lO AND (nlOliiO0O AND n011iOii)))) AND (NOT (nlOOOl1Oi AND (nlOliiOii AND n01O1ill)))) AND (NOT (nlOOOl1Ol AND (nlOliiOil AND n00il1OO)))) AND (NOT (nlOOOl1OO AND (nlOliiOiO AND n0i01O0i)))) AND (NOT (nlOOOl01i AND (nlOliiOli AND n0iOliil)))) AND (NOT (nlOOOl01l AND (nlOliiOll AND n0ll01lO)))) AND (NOT (nlOOOl01O AND (nlOliiOlO AND n0O0lO1i)))); + niOl1i1ll <= ((((((((NOT (nlOOOl1ll AND (nlOliiOOi AND n1Oi1l0i))) AND (NOT (nlOOOl1lO AND (nlOliiOOl AND n011l0il)))) AND (NOT (nlOOOl1Oi AND (nlOliiOOO AND n01O1OlO)))) AND (NOT (nlOOOl1Ol AND (nlOlil11i AND n00ill1i)))) AND (NOT (nlOOOl1OO AND (nlOlil11l AND n0i0000l)))) AND (NOT (nlOOOl01i AND (nlOlil11O AND n0iOlOiO)))) AND (NOT (nlOOOl01l AND (nlOlil10i AND n0ll0iOi)))) AND (NOT (nlOOOl01O AND (nlOlil10l AND n0O0O01l)))); + niOl1i1lO <= (wire_w_lg_niOli11Ol20248w(0) OR wire_w_lg_niOl1i1OO25058w(0)); + niOl1i1Oi <= (wire_niO01ill_w_lg_nlOOOl01O25070w(0) OR (wire_niO01ill_w_lg_nlOOOl01l25080w(0) OR (wire_niO01ill_w_lg_nlOOOl01i25090w(0) OR (wire_niO01ill_w_lg_nlOOOl1OO25100w(0) OR (wire_niO01ill_w_lg_nlOOOl1Ol25110w(0) OR (wire_niO01ill_w_lg_nlOOOl1Oi25120w(0) OR (wire_niO01ill_w_lg_nlOOOl1ll25130w(0) OR wire_niO01ill_w_lg_nlOOOl1lO25140w(0)))))))); + niOl1i1Ol <= ((wire_w_lg_niOli11Ol20248w(0) OR wire_w_lg_niOl1i1OO25058w(0)) AND n1lillil); + niOl1i1OO <= (((((((wire_niO01ill_w_lg_n1Oi1O1l27927w(0) AND wire_niO01ill_w_lg_n011li0O27928w(0)) AND wire_niO01ill_w_lg_n01O01li27930w(0)) AND wire_niO01ill_w_lg_n00illOl27932w(0)) AND wire_niO01ill_w_lg_n0i00i1O27934w(0)) AND wire_niO01ill_w_lg_n0iOO1ii27936w(0)) AND wire_niO01ill_w_lg_n0ll0lll27938w(0)) AND wire_niO01ill_w_lg_n0O0O0OO27940w(0)); + niOl1ii0i <= (niOl1ilOl AND niOli1iOl); + niOl1ii0l <= (n11O0lli AND wire_niO01ill_w_lg_n11O0ill20641w(0)); + niOl1ii0O <= (n11O0lli AND n11O0ill); + niOl1ii1i <= (n11Oi1lO AND wire_niO01ill_w_lg_n11O0lOl24768w(0)); + niOl1ii1l <= (n11Oi1ii AND n11O0O1O); + niOl1ii1O <= (n11Oi00l AND wire_niO01ill_w_lg_n11O0Oii24765w(0)); + niOl1iiii <= (wire_niO01ill_w_lg_n11Oi01l24760w(0) AND n11O0O0i); + niOl1iiil <= (niOl1iili AND nlOlO011l); + niOl1iiiO <= (nlOlOilOO AND (n1il11Ol AND (nlOlO1OOO AND niOli1iOl))); + niOl1iili <= (niOl01O0O AND n1lillil); + niOl1iill <= (nlOlOilOO AND (n1il11Ol AND (nlOlO011O AND niOli1iOl))); + niOl1iilO <= (niOl1iiOi AND wire_niO01ill_w_lg_nlOlO1l0i24728w(0)); + niOl1iiOi <= (n11Oi11i AND n11O0Oil); + niOl1iiOl <= (nlOO01OOO OR wire_w_lg_niOl00lil21194w(0)); + niOl1iiOO <= (wire_niO01ill_w_lg_nlOlOiO1i24684w(0) AND niOl1ilii); + niOl1il0i <= ((nlOO01OOO OR (wire_nlOii10ii_w_lg_dataout23869w(0) OR wire_w_lg_niOl00lil21194w(0))) AND n1lillil); + niOl1il0l <= (nlOlOilil AND n1lillil); + niOl1il0O <= (niOl0Ol0i AND n11O0lil); + niOl1il1i <= (n11O0l1l AND (wire_niO01ill_w_lg_n1110OOO24680w(0) OR wire_w_lg_niOl1il1l24681w(0))); + niOl1il1l <= (((((((wire_niO01ill_w_lg_nlOlOilii27709w(0) AND wire_niO01ill_w_lg_nlOlOil0O27710w(0)) AND wire_niO01ill_w_lg_nlOlOil0l27712w(0)) AND wire_niO01ill_w_lg_nlOlOil0i27714w(0)) AND wire_niO01ill_w_lg_nlOlOil1O27720w(0)) AND wire_niO01ill_w_lg_nlOlOil1l27722w(0)) AND wire_niO01ill_w_lg_nlOlOil1i27724w(0)) AND wire_niO01ill_w_lg_nlOlOi00l27726w(0)); + niOl1il1O <= (nlOlOiO1i AND nlOll0O0i); + niOl1ilii <= ((((((((NOT (k_cnt(57) XOR nlOlOi00l)) AND (NOT (k_cnt(58) XOR nlOlOil1i))) AND (NOT (k_cnt(59) XOR nlOlOil1l))) AND (NOT (k_cnt(60) XOR nlOlOil1O))) AND (NOT (k_cnt(61) XOR nlOlOil0i))) AND (NOT (k_cnt(62) XOR nlOlOil0l))) AND (NOT (k_cnt(63) XOR nlOlOil0O))) AND (NOT (k_cnt(64) XOR nlOlOilii))); + niOl1ilil <= (nlOlOilil AND niOli10Ol); + niOl1iliO <= (wire_niO01iOi_w_lg_nlOlOilOO24659w(0) AND niOl1ilii); + niOl1illi <= (nlOlOilOO AND niOli1iOO); + niOl1illl <= (wire_niO01iOi_w_lg_nlOlOilOO24659w(0) AND niOli1iOl); + niOl1illO <= (nlOlOilOO AND niOl1ilOi); + niOl1ilOi <= (((((((wire_niO01ill_w_lg_nlOlOilii27709w(0) AND wire_niO01ill_w_lg_nlOlOil0O27710w(0)) AND wire_niO01ill_w_lg_nlOlOil0l27712w(0)) AND wire_niO01ill_w_lg_nlOlOil0i27714w(0)) AND nlOlOil1O) AND nlOlOil1l) AND nlOlOil1i) AND nlOlOi00l); + niOl1ilOl <= (n11O0l0l AND wire_niO01ill_w_lg_n1110Oii21198w(0)); + niOl1ilOO <= (niOO10lOO AND n11O0O1O); + niOl1iO0i <= (wire_niO01ill_w_lg_n1101l1O16997w(0) AND (niOl1O1lO AND niOl1iO0l)); + niOl1iO0l <= ((((wire_niO01ill_w_lg_n011lllO27345w(0) AND wire_niO01ill_w_lg_n011llll27347w(0)) AND wire_niO01ill_w_lg_n011llli27689w(0)) AND wire_niO01ill_w_lg_n011lliO27691w(0)) AND wire_niO01ill_w_lg_n011llil27693w(0)); + niOl1iO0O <= ((((wire_niO01ill_w_lg_n1Oi01il27323w(0) AND wire_niO01ill_w_lg_n1Oi01ii27325w(0)) AND wire_niO01ill_w_lg_n1Oi010O27682w(0)) AND wire_niO01ill_w_lg_n1Oi010l27684w(0)) AND wire_niO01ill_w_lg_n1Oi010i27686w(0)); + niOl1iO1i <= ((((wire_niO01ill_w_lg_n0O0Ol0O27478w(0) AND wire_niO01ill_w_lg_n0O0Ol0l27480w(0)) AND wire_niO01ill_w_lg_n0O0Ol0i27703w(0)) AND wire_niO01ill_w_lg_n0O0Ol1O27705w(0)) AND wire_niO01ill_w_lg_n0O0Ol1l27707w(0)); + niOl1iO1l <= (wire_niO01ill_w_lg_n1101l0l15183w(0) AND (niOl1O1ll AND niOl1iO1O)); + niOl1iO1O <= ((((wire_niO01ill_w_lg_n00iO10l27389w(0) AND wire_niO01ill_w_lg_n00iO10i27391w(0)) AND wire_niO01ill_w_lg_n00iO11O27696w(0)) AND wire_niO01ill_w_lg_n00iO11l27698w(0)) AND wire_niO01ill_w_lg_n00iO11i27700w(0)); + niOl1iOii <= (niOO10lOO AND n11O0O1l); + niOl1iOil <= (wire_w_lg_niOO10lOO8902w(0) AND n11O0O1l); + niOl1iOiO <= (wire_w_lg_w_k_conf_range24588w24630w(0) OR wire_w_lg_niOl1iOli24631w(0)); + niOl1iOli <= ((((((((NOT (n111i1ii AND niOl1Oi1O)) AND (NOT (n111i1il AND niOl1Oi1l))) AND (NOT (n111i1iO AND niOl1Oi1i))) AND (NOT (n111i1li AND niOl1O0OO))) AND (NOT (n111i1ll AND niOl1O0Ol))) AND (NOT (n111i1lO AND niOl1O0Oi))) AND (NOT (n111i1Oi AND niOl1O0lO))) AND (NOT (n111i1Ol AND niOl1O0ll))); + niOl1iOll <= (niOl1l11O OR nlOllll0l); + niOl1iOlO <= (wire_w_lg_niOl1iOOl24592w(0) AND wire_w_lg_niOl1iOOi24593w(0)); + niOl1iOOi <= ((((((((NOT (k_cnt(44) XOR nlOO1i1Oi)) AND (NOT (k_cnt(45) XOR nlOO1O10O))) AND (NOT (k_cnt(46) XOR nlOO1O1ii))) AND (NOT (k_cnt(47) XOR nlOO1O1il))) AND (NOT (k_cnt(48) XOR nlOO1O1iO))) AND (NOT (k_cnt(49) XOR nlOO1O1li))) AND (NOT (k_cnt(50) XOR nlOO1O1ll))) AND (NOT (k_cnt(51) XOR nlOO1O1lO))); + niOl1iOOl <= ((((((((NOT (niOl0OOOi XOR n111i1ii)) AND (NOT (niOl0OOlO XOR n111i1il))) AND (NOT (niOl0OOll XOR n111i1iO))) AND (NOT (niOl0OOli XOR n111i1li))) AND (NOT (niOl0OOiO XOR n111i1ll))) AND (NOT (niOl0OOil XOR n111i1lO))) AND (NOT (niOl0OOii XOR n111i1Oi))) AND (NOT (niOl0OO0O XOR n111i1Ol))); + niOl1iOOO <= wire_w_lg_w_k_conf_range24588w24591w(0); + niOl1l00i <= (wire_w_lg_niOl0liOO20867w(0) AND niOl0ll1i); + niOl1l00l <= (wire_w_lg_niOl0llii20859w(0) AND niOl0llil); + niOl1l00O <= (wire_w_lg_niOl0llOl20851w(0) AND niOl0llOO); + niOl1l01i <= ((((((((NOT (wire_niO10O1l_w_lg_dataout27492w(0) AND (n111i1ii AND nlOO0011l))) AND (NOT (wire_niO10l1l_w_lg_dataout27496w(0) AND (n111i1il AND nlOO0011O)))) AND (NOT (wire_niO10i1l_w_lg_dataout27501w(0) AND (n111i1iO AND nlOO0010i)))) AND (NOT (wire_niO1001l_w_lg_dataout27506w(0) AND (n111i1li AND nlOO0010l)))) AND (NOT (wire_niO1011l_w_lg_dataout27511w(0) AND (n111i1ll AND nlOO0010O)))) AND (NOT (wire_niO11O1l_w_lg_dataout27516w(0) AND (n111i1lO AND nlOO001ii)))) AND (NOT (wire_niO11l1l_w_lg_dataout27521w(0) AND (n111i1Oi AND nlOO001il)))) AND (NOT (wire_niO11i1l_w_lg_dataout27526w(0) AND (n111i1Ol AND nlOO001iO)))); + niOl1l01l <= (wire_w_lg_niOl0li1i20883w(0) AND niOl0li1l); + niOl1l01O <= (wire_w_lg_niOl0liil20875w(0) AND niOl0liiO); + niOl1l0ii <= (wire_w_lg_niOl0lO0O20843w(0) AND niOl0lOii); + niOl1l0il <= (wire_w_lg_niOl0lOOi20835w(0) AND niOl0lOOl); + niOl1l0iO <= (wire_w_lg_niOl0O10l20827w(0) AND niOl0O10O); + niOl1l0li <= (niOl0li1l AND (wire_w_lg_niOl0li1i20883w(0) AND wire_w_lg_niOl0l0OO24259w(0))); + niOl1l0ll <= (niOl0liiO AND (wire_w_lg_niOl0liil20875w(0) AND wire_w_lg_niOl0liii24255w(0))); + niOl1l0lO <= (niOl0ll1i AND (wire_w_lg_niOl0liOO20867w(0) AND wire_w_lg_niOl0liOl24251w(0))); + niOl1l0Oi <= (niOl0llil AND (wire_w_lg_niOl0llii20859w(0) AND wire_w_lg_niOl0ll0O24247w(0))); + niOl1l0Ol <= (niOl0llOO AND (wire_w_lg_niOl0llOl20851w(0) AND wire_w_lg_niOl0llOi24243w(0))); + niOl1l0OO <= (niOl0lOii AND (wire_w_lg_niOl0lO0O20843w(0) AND wire_w_lg_niOl0lO0l24239w(0))); + niOl1l10i <= (n0O0O0OO AND n0O0lO1i); + niOl1l10l <= (n0ll0lll AND n0ll01lO); + niOl1l10O <= (n0iOO1ii AND n0iOliil); + niOl1l11i <= (((((((wire_niO01ill_w_lg_nlOO1O1lO27589w(0) AND wire_niO01ill_w_lg_nlOO1O1ll27590w(0)) AND wire_niO01ill_w_lg_nlOO1O1li27592w(0)) AND wire_niO01ill_w_lg_nlOO1O1iO27594w(0)) AND wire_niO01ill_w_lg_nlOO1O1il27596w(0)) AND wire_niO01ill_w_lg_nlOO1O1ii27598w(0)) AND wire_niO01ill_w_lg_nlOO1O10O27600w(0)) AND wire_niO01ill_w_lg_nlOO1i1Oi27602w(0)); + niOl1l11l <= (niOl1l11O OR wire_niO01iOi_w_lg_nlOllllii23948w(0)); + niOl1l11O <= (wire_niO01ill_w_lg_n11O0lil24584w(0) AND wire_niO01ill_w_lg_n11O0l1l24585w(0)); + niOl1l1ii <= (n0i00i1O AND n0i01O0i); + niOl1l1il <= (n00illOl AND n00il1OO); + niOl1l1iO <= (n01O01li AND n01O1ill); + niOl1l1li <= (n011li0O AND n011iOii); + niOl1l1ll <= (n1Oi1O1l AND n1Oi101O); + niOl1l1lO <= ((((((((NOT (n111i1ii XOR (n111i1ii AND n1Ol011i))) AND (NOT (n111i1il XOR (n111i1il AND n010ll0l)))) AND (NOT (n111i1iO XOR (n111i1iO AND n00100iO)))) AND (NOT (n111i1li XOR (n111i1li AND n00llOOi)))) AND (NOT (n111i1ll XOR (n111i1ll AND n0ii0l1l)))) AND (NOT (n111i1lO XOR (n111i1lO AND n0l1O00O)))) AND (NOT (n111i1Oi XOR (n111i1Oi AND n0lO0Oli)))) AND (NOT (n111i1Ol XOR (n111i1Ol AND n0OiOiOl)))); + niOl1l1Oi <= (n11O0lli OR niOl1Oi0i); + niOl1l1Ol <= (((((((nlOO0il0i AND nlOO0il1O) AND nlOO0il1l) AND nlOO0il1i) AND nlOO0iiOO) AND nlOO0iiOl) AND nlOO0iiOi) AND nlOO0iilO); + niOl1l1OO <= ((((((((NOT (n111i1ii AND n1Oi1O1l)) AND (NOT (n111i1il AND n011li0O))) AND (NOT (n111i1iO AND n01O01li))) AND (NOT (n111i1li AND n00illOl))) AND (NOT (n111i1ll AND n0i00i1O))) AND (NOT (n111i1lO AND n0iOO1ii))) AND (NOT (n111i1Oi AND n0ll0lll))) AND (NOT (n111i1Ol AND n0O0O0OO))); + niOl1li0i <= (niOl0liiO AND (wire_w_lg_niOl0liil20875w(0) AND wire_w_lg_niOl0liii24215w(0))); + niOl1li0l <= (niOl0ll1i AND (wire_w_lg_niOl0liOO20867w(0) AND wire_w_lg_niOl0liOl24211w(0))); + niOl1li0O <= (niOl0llil AND (wire_w_lg_niOl0llii20859w(0) AND wire_w_lg_niOl0ll0O24207w(0))); + niOl1li1i <= (niOl0lOOl AND (wire_w_lg_niOl0lOOi20835w(0) AND wire_w_lg_niOl0lOlO24235w(0))); + niOl1li1l <= (niOl0O10O AND (wire_w_lg_niOl0O10l20827w(0) AND wire_w_lg_niOl0O10i24231w(0))); + niOl1li1O <= (niOl0li1l AND (wire_w_lg_niOl0li1i20883w(0) AND wire_w_lg_niOl0l0OO24219w(0))); + niOl1liii <= (niOl0llOO AND (wire_w_lg_niOl0llOl20851w(0) AND wire_w_lg_niOl0llOi24203w(0))); + niOl1liil <= (niOl0lOii AND (wire_w_lg_niOl0lO0O20843w(0) AND wire_w_lg_niOl0lO0l24199w(0))); + niOl1liiO <= (niOl0lOOl AND (wire_w_lg_niOl0lOOi20835w(0) AND wire_w_lg_niOl0lOlO24195w(0))); + niOl1lili <= (niOl0O10O AND (wire_w_lg_niOl0O10l20827w(0) AND wire_w_lg_niOl0O10i24191w(0))); + niOl1lill <= (wire_nlOOO0l1O_dataout AND wire_nlOOO1lOl_dataout); + niOl1lilO <= (wire_nlOOO0l0O_dataout AND wire_nlOOO1O1O_dataout); + niOl1liOi <= (wire_nlOOO0liO_dataout AND wire_nlOOO1Oii_dataout); + niOl1liOl <= (wire_nlOOO0llO_dataout AND wire_nlOOO1Oll_dataout); + niOl1liOO <= (wire_nlOOO0lOO_dataout AND wire_nlOOO1OOO_dataout); + niOl1ll0i <= (((((NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0O0Ol1l)) AND (NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0O0Ol1O))) AND (NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0O0Ol0i))) AND wire_niO01ill_w_lg_n0O0Ol0O27478w(0)) AND wire_niO01ill_w_lg_n0O0Ol0l27480w(0)); + niOl1ll0l <= (((((NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0O0Ol1l)) AND (NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0O0Ol1O))) AND (NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0O0Ol0i))) AND wire_niO01ill_w_lg_n0O0Ol0O27478w(0)) AND wire_niO01ill_w_lg_n0O0Ol0l27480w(0)); + niOl1ll0O <= (((((NOT (n1101ilO XOR n0ll0OOi)) AND (NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0ll0OOl))) AND (NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0ll0OOO))) AND wire_niO01ill_w_lg_n0lli11l27456w(0)) AND wire_niO01ill_w_lg_n0lli11i27458w(0)); + niOl1ll1i <= (wire_nlOOO0O1O_dataout AND wire_nlOOO010i_dataout); + niOl1ll1l <= (wire_nlOOO0O0O_dataout AND wire_nlOOO01il_dataout); + niOl1ll1O <= (wire_nlOOO0OiO_dataout AND wire_nlOOO01lO_dataout); + niOl1llii <= (((((NOT (wire_nlOO1iO0l_dataout XOR n0ll0OOi)) AND (NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0ll0OOl))) AND (NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0ll0OOO))) AND wire_niO01ill_w_lg_n0lli11l27456w(0)) AND wire_niO01ill_w_lg_n0lli11i27458w(0)); + niOl1llil <= (((((NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0iOO0iO)) AND (NOT (n1101ilO XOR n0iOO0li))) AND (NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0iOO0ll))) AND wire_niO01ill_w_lg_n0iOO0Oi27434w(0)) AND wire_niO01ill_w_lg_n0iOO0lO27436w(0)); + niOl1lliO <= (((((NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0iOO0iO)) AND (NOT (wire_nlOO1iO0l_dataout XOR n0iOO0li))) AND (NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0iOO0ll))) AND wire_niO01ill_w_lg_n0iOO0Oi27434w(0)) AND wire_niO01ill_w_lg_n0iOO0lO27436w(0)); + niOl1llli <= (((((NOT (n1101ilO XOR n0i00l0l)) AND (NOT (n1101ilO XOR n0i00l0O))) AND (NOT (wire_niO01ill_w_lg_n1101ilO27420w(0) XOR n0i00lii))) AND wire_niO01ill_w_lg_n0i00liO27411w(0)) AND wire_niO01ill_w_lg_n0i00lil27413w(0)); + niOl1llll <= (((((NOT (wire_nlOO1iO0l_dataout XOR n0i00l0l)) AND (NOT (wire_nlOO1iO0l_dataout XOR n0i00l0O))) AND (NOT (wire_nlOO1iO0l_w_lg_dataout26694w(0) XOR n0i00lii))) AND wire_niO01ill_w_lg_n0i00liO27411w(0)) AND wire_niO01ill_w_lg_n0i00lil27413w(0)); + niOl1lllO <= (((((NOT (wire_nlOOO10il_dataout XOR n00iO11i)) AND (NOT (wire_nlOOO10iO_dataout XOR n00iO11l))) AND (NOT (n1101ilO XOR n00iO11O))) AND wire_niO01ill_w_lg_n00iO10l27389w(0)) AND wire_niO01ill_w_lg_n00iO10i27391w(0)); + niOl1llOi <= (((((NOT (wire_nlOOO1i1O_dataout XOR n00iO11i)) AND (NOT (wire_nlOOO1i0i_dataout XOR n00iO11l))) AND (NOT (wire_nlOO1iO0l_dataout XOR n00iO11O))) AND wire_niO01ill_w_lg_n00iO10l27389w(0)) AND wire_niO01ill_w_lg_n00iO10i27391w(0)); + niOl1llOl <= (((((NOT (wire_nlOOO10li_dataout XOR n01O00lO)) AND (NOT (wire_nlOOO10ll_dataout XOR n01O00Oi))) AND (NOT (n1101ilO XOR n01O00Ol))) AND wire_niO01ill_w_lg_n01O0i1i27367w(0)) AND wire_niO01ill_w_lg_n01O00OO27369w(0)); + niOl1llOO <= (((((NOT (wire_nlOOO1i0l_dataout XOR n01O00lO)) AND (NOT (wire_nlOOO1i0O_dataout XOR n01O00Oi))) AND (NOT (wire_nlOO1iO0l_dataout XOR n01O00Ol))) AND wire_niO01ill_w_lg_n01O0i1i27367w(0)) AND wire_niO01ill_w_lg_n01O00OO27369w(0)); + niOl1lO0i <= (((((NOT (wire_nlOOO1ili_dataout XOR n1Oi010i)) AND (NOT (wire_nlOOO1ill_dataout XOR n1Oi010l))) AND (NOT (wire_nlOO1iO0l_dataout XOR n1Oi010O))) AND wire_niO01ill_w_lg_n1Oi01il27323w(0)) AND wire_niO01ill_w_lg_n1Oi01ii27325w(0)); + niOl1lO0l <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n0O0Olil)) AND (NOT (wire_nlOO10OOl_dataout XOR n0O0OliO))) AND (NOT (wire_nlOO10OOO_dataout XOR n0O0Olli))) AND (NOT (wire_nlOO1i11i_dataout XOR n0O0Olll))) AND (NOT (wire_nlOO1i11l_dataout XOR n0O0OllO))) AND (NOT (wire_nlOO1i11O_dataout XOR n0O0OlOi))) AND (NOT (wire_nlOO1i10i_dataout XOR n0O0OlOl))) AND (NOT (wire_nlOO1i10l_dataout XOR n0O0OlOO))); + niOl1lO0O <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n0lli10i)) AND (NOT (wire_nlOO10OOl_dataout XOR n0lli10l))) AND (NOT (wire_nlOO10OOO_dataout XOR n0lli10O))) AND (NOT (wire_nlOO1i11i_dataout XOR n0lli1ii))) AND (NOT (wire_nlOO1i11l_dataout XOR n0lli1il))) AND (NOT (wire_nlOO1i11O_dataout XOR n0lli1iO))) AND (NOT (wire_nlOO1i10i_dataout XOR n0lli1li))) AND (NOT (wire_nlOO1i10l_dataout XOR n0lli1ll))); + niOl1lO1i <= (((((NOT (wire_nlOOO10lO_dataout XOR n011llil)) AND (NOT (wire_nlOOO10Oi_dataout XOR n011lliO))) AND (NOT (n1101ilO XOR n011llli))) AND wire_niO01ill_w_lg_n011lllO27345w(0)) AND wire_niO01ill_w_lg_n011llll27347w(0)); + niOl1lO1l <= (((((NOT (wire_nlOOO1iii_dataout XOR n011llil)) AND (NOT (wire_nlOOO1iil_dataout XOR n011lliO))) AND (NOT (wire_nlOO1iO0l_dataout XOR n011llli))) AND wire_niO01ill_w_lg_n011lllO27345w(0)) AND wire_niO01ill_w_lg_n011llll27347w(0)); + niOl1lO1O <= (((((NOT (wire_nlOOO10OO_dataout XOR n1Oi010i)) AND (NOT (wire_nlOOO1i1i_dataout XOR n1Oi010l))) AND (NOT (n1101ilO XOR n1Oi010O))) AND wire_niO01ill_w_lg_n1Oi01il27323w(0)) AND wire_niO01ill_w_lg_n1Oi01ii27325w(0)); + niOl1lOii <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n0iOO0OO)) AND (NOT (wire_nlOO10OOl_dataout XOR n0iOOi1i))) AND (NOT (wire_nlOO10OOO_dataout XOR n0iOOi1l))) AND (NOT (wire_nlOO1i11i_dataout XOR n0iOOi1O))) AND (NOT (wire_nlOO1i11l_dataout XOR n0iOOi0i))) AND (NOT (wire_nlOO1i11O_dataout XOR n0iOOi0l))) AND (NOT (wire_nlOO1i10i_dataout XOR n0iOOi0O))) AND (NOT (wire_nlOO1i10l_dataout XOR n0iOOiii))); + niOl1lOil <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n0i00lll)) AND (NOT (wire_nlOO10OOl_dataout XOR n0i00llO))) AND (NOT (wire_nlOO10OOO_dataout XOR n0i00lOi))) AND (NOT (wire_nlOO1i11i_dataout XOR n0i00lOl))) AND (NOT (wire_nlOO1i11l_dataout XOR n0i00lOO))) AND (NOT (wire_nlOO1i11O_dataout XOR n0i00O1i))) AND (NOT (wire_nlOO1i10i_dataout XOR n0i00O1l))) AND (NOT (wire_nlOO1i10l_dataout XOR n0i00O1O))); + niOl1lOiO <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n00iO1ii)) AND (NOT (wire_nlOO10OOl_dataout XOR n00iO1il))) AND (NOT (wire_nlOO10OOO_dataout XOR n00iO1iO))) AND (NOT (wire_nlOO1i11i_dataout XOR n00iO1li))) AND (NOT (wire_nlOO1i11l_dataout XOR n00iO1ll))) AND (NOT (wire_nlOO1i11O_dataout XOR n00iO1lO))) AND (NOT (wire_nlOO1i10i_dataout XOR n00iO1Oi))) AND (NOT (wire_nlOO1i10l_dataout XOR n00iO1Ol))); + niOl1lOli <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n01O0i1O)) AND (NOT (wire_nlOO10OOl_dataout XOR n01O0i0i))) AND (NOT (wire_nlOO10OOO_dataout XOR n01O0i0l))) AND (NOT (wire_nlOO1i11i_dataout XOR n01O0i0O))) AND (NOT (wire_nlOO1i11l_dataout XOR n01O0iii))) AND (NOT (wire_nlOO1i11O_dataout XOR n01O0iil))) AND (NOT (wire_nlOO1i10i_dataout XOR n01O0iiO))) AND (NOT (wire_nlOO1i10l_dataout XOR n01O0ili))); + niOl1lOll <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n011llOl)) AND (NOT (wire_nlOO10OOl_dataout XOR n011llOO))) AND (NOT (wire_nlOO10OOO_dataout XOR n011lO1i))) AND (NOT (wire_nlOO1i11i_dataout XOR n011lO1l))) AND (NOT (wire_nlOO1i11l_dataout XOR n011lO1O))) AND (NOT (wire_nlOO1i11O_dataout XOR n011lO0i))) AND (NOT (wire_nlOO1i10i_dataout XOR n011lO0l))) AND (NOT (wire_nlOO1i10l_dataout XOR n011lO0O))); + niOl1lOlO <= ((((((((NOT (wire_nlOO10OOi_dataout XOR n1Oi01li)) AND (NOT (wire_nlOO10OOl_dataout XOR n1Oi01ll))) AND (NOT (wire_nlOO10OOO_dataout XOR n1Oi01lO))) AND (NOT (wire_nlOO1i11i_dataout XOR n1Oi01Oi))) AND (NOT (wire_nlOO1i11l_dataout XOR n1Oi01Ol))) AND (NOT (wire_nlOO1i11O_dataout XOR n1Oi01OO))) AND (NOT (wire_nlOO1i10i_dataout XOR n1Oi001i))) AND (NOT (wire_nlOO1i10l_dataout XOR n1Oi001l))); + niOl1lOOi <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n0O0OiOO)) AND wire_niO01ill_w_lg_n0O0Ol1i21104w(0)) AND n0O0OiOl))); + niOl1lOOl <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n0ll0Oll)) AND wire_niO01ill_w_lg_n0ll0OlO21098w(0)) AND n0ll0Oli))); + niOl1lOOO <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n0iOO0ii)) AND wire_niO01ill_w_lg_n0iOO0il21092w(0)) AND n0iOO00O))); + niOl1O00i <= (((((NOT (nlOOOi0iO XOR n0iOO0iO)) AND (NOT (nlOOOi0li XOR n0iOO0li))) AND (NOT (nlOOOi0ll XOR n0iOO0ll))) AND (NOT (nlOOOi0lO XOR n0iOO0lO))) AND (NOT (nlOOOi0Oi XOR n0iOO0Oi))); + niOl1O00l <= (((((NOT (nlOOOi0Ol XOR n0i00l0l)) AND (NOT (nlOOOi0OO XOR n0i00l0O))) AND (NOT (nlOOOii1i XOR n0i00lii))) AND (NOT (nlOOOii1l XOR n0i00lil))) AND (NOT (nlOOOii1O XOR n0i00liO))); + niOl1O00O <= (((((NOT (nlOOOii0i XOR n00iO11i)) AND (NOT (nlOOOii0l XOR n00iO11l))) AND (NOT (nlOOOii0O XOR n00iO11O))) AND (NOT (nlOOOiiii XOR n00iO10i))) AND (NOT (nlOOOiiil XOR n00iO10l))); + niOl1O01i <= (wire_nlOO1l1lO_dataout AND wire_nlOO1l1ll_w_lg_dataout27120w(0)); + niOl1O01l <= (((((NOT (nlOOOi1Ol XOR n0O0Ol1l)) AND (NOT (nlOOOi1OO XOR n0O0Ol1O))) AND (NOT (nlOOOi01i XOR n0O0Ol0i))) AND (NOT (nlOOOi01l XOR n0O0Ol0l))) AND (NOT (nlOOOi01O XOR n0O0Ol0O))); + niOl1O01O <= (((((NOT (nlOOOi00i XOR n0ll0OOi)) AND (NOT (nlOOOi00l XOR n0ll0OOl))) AND (NOT (nlOOOi00O XOR n0ll0OOO))) AND (NOT (nlOOOi0ii XOR n0lli11i))) AND (NOT (nlOOOi0il XOR n0lli11l))); + niOl1O0ii <= (((((NOT (nlOOOiiiO XOR n01O00lO)) AND (NOT (nlOOOiili XOR n01O00Oi))) AND (NOT (nlOOOiill XOR n01O00Ol))) AND (NOT (nlOOOiilO XOR n01O00OO))) AND (NOT (nlOOOiiOi XOR n01O0i1i))); + niOl1O0il <= (((((NOT (nlOOOiiOl XOR n011llil)) AND (NOT (nlOOOiiOO XOR n011lliO))) AND (NOT (nlOOOil1i XOR n011llli))) AND (NOT (nlOOOil1l XOR n011llll))) AND (NOT (nlOOOil1O XOR n011lllO))); + niOl1O0iO <= (((((NOT (nlOOOil0i XOR n1Oi010i)) AND (NOT (nlOOOil0l XOR n1Oi010l))) AND (NOT (nlOOOil0O XOR n1Oi010O))) AND (NOT (nlOOOilii XOR n1Oi01ii))) AND (NOT (nlOOOilil XOR n1Oi01il))); + niOl1O0li <= (n11O0O1l OR n11O0O1i); + niOl1O0ll <= (wire_niO01llO_w_lg_niil0liO23964w(0) AND nlOOOl11l); + niOl1O0lO <= (wire_niO01llO_w_lg_niil0l0l23962w(0) AND nlOOOl11i); + niOl1O0Oi <= (wire_niO01llO_w_lg_niil0l0i23960w(0) AND nlOOOiOOO); + niOl1O0Ol <= (wire_niO01llO_w_lg_niil0l1O23958w(0) AND nlOOOiOOl); + niOl1O0OO <= (wire_niO01llO_w_lg_niil0l1l23956w(0) AND nlOOOiOOi); + niOl1O10i <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n011ll0O)) AND wire_niO01ill_w_lg_n011llii21068w(0)) AND n011ll0l))); + niOl1O10l <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n1Oi011l)) AND wire_niO01ill_w_lg_n1Oi011O21063w(0)) AND n1Oi011i))); + niOl1O10O <= ((wire_nlOO1l1OO_w_lg_dataout27122w(0) AND wire_nlOO1l1Ol_w_lg_dataout27123w(0)) AND wire_nlOO1l1Oi_w_lg_dataout27125w(0)); + niOl1O11i <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n0i00l1O)) AND wire_niO01ill_w_lg_n0i00l0i21086w(0)) AND n0i00l1l))); + niOl1O11l <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n00ilOOl)) AND wire_niO01ill_w_lg_n00ilOOO21080w(0)) AND n00ilOOi))); + niOl1O11O <= (wire_nlOO1l10O_dataout AND (NOT (((NOT (niOO10l1i XOR n01O00li)) AND wire_niO01ill_w_lg_n01O00ll21074w(0)) AND n01O00iO))); + niOl1O1ii <= ((wire_nlOO1l1OO_w_lg_dataout27122w(0) AND wire_nlOO1l1Ol_w_lg_dataout27123w(0)) AND wire_nlOO1l1Oi_dataout); + niOl1O1il <= (wire_nlOO1l1OO_w_lg_w_lg_dataout27122w27128w(0) AND wire_nlOO1l1Oi_w_lg_dataout27125w(0)); + niOl1O1iO <= (wire_nlOO1l1OO_w_lg_w_lg_dataout27122w27128w(0) AND wire_nlOO1l1Oi_dataout); + niOl1O1li <= (n0O0O0OO OR n0O0O0Ol); + niOl1O1ll <= (n00illOl OR n00illOi); + niOl1O1lO <= (n011li0O OR n011li0l); + niOl1O1Oi <= (wire_nlOO1l1lO_dataout AND wire_nlOO1l1ll_dataout); + niOl1O1Ol <= (n1Oi1O1l OR n1Oi1O1i); + niOl1O1OO <= (wire_nlOO1l1lO_w_lg_dataout27118w(0) AND wire_nlOO1l1ll_dataout); + niOl1Oi0i <= (niOlO1O0i OR wire_niO01iOi_w_lg_nlOllllii23948w(0)); + niOl1Oi0l <= (wire_niO11i1i_dataout AND niOl0Oi1i); + niOl1Oi0O <= (wire_niO11l1i_dataout AND niOl0Oi1i); + niOl1Oi1i <= (wire_niO01llO_w_lg_niil0iOO23954w(0) AND nlOOOiOlO); + niOl1Oi1l <= (wire_niO01llO_w_lg_niil01ii23952w(0) AND nlOOOiOll); + niOl1Oi1O <= (wire_niO01llO_w_lg_niil01il23950w(0) AND nlOOOiOli); + niOl1Oiii <= (wire_niO11O1i_dataout AND niOl0Oi1i); + niOl1Oiil <= (wire_niO1011i_dataout AND niOl0Oi1i); + niOl1OiiO <= (wire_niO1001i_dataout AND niOl0Oi1i); + niOl1Oili <= (wire_niO10i1i_dataout AND niOl0Oi1i); + niOl1Oill <= (wire_niO10l1i_dataout AND niOl0Oi1i); + niOl1OilO <= (wire_niO10O1i_dataout AND niOl0Oi1i); + niOl1OiOi <= ((((((((n1101l1l OR nlOO001li) AND (n1101l1O OR nlOO001ll)) AND (n1101l0i OR nlOO001lO)) AND (n1101l0l OR nlOO001Oi)) AND (n1101l0O OR nlOO001Ol)) AND (n1101lii OR nlOO001OO)) AND (n1101lil OR nlOO0001i)) AND (n1101liO OR nlOO0001l)); + niOl1OiOl <= ((((((((NOT (wire_niO10O1l_dataout AND wire_niO01ill_w_lg_n1101l1l17904w(0))) AND (NOT (wire_niO10l1l_dataout AND wire_niO01ill_w_lg_n1101l1O16997w(0)))) AND (NOT (wire_niO10i1l_dataout AND wire_niO01ill_w_lg_n1101l0i16090w(0)))) AND (NOT (wire_niO1001l_dataout AND wire_niO01ill_w_lg_n1101l0l15183w(0)))) AND (NOT (wire_niO1011l_dataout AND wire_niO01ill_w_lg_n1101l0O14276w(0)))) AND (NOT (wire_niO11O1l_dataout AND wire_niO01ill_w_lg_n1101lii13369w(0)))) AND (NOT (wire_niO11l1l_dataout AND wire_niO01ill_w_lg_n1101lil12462w(0)))) AND (NOT (wire_niO11i1l_dataout AND wire_niO01ill_w_lg_n1101liO11541w(0)))); + niOl1OiOO <= ((((((((NOT (niOl1Olil AND n111i1ii)) AND (NOT (niOl1Olii AND n111i1il))) AND (NOT (niOl1Ol0O AND n111i1iO))) AND (NOT (niOl1Ol0l AND n111i1li))) AND (NOT (niOl1Ol0i AND n111i1ll))) AND (NOT (niOl1Ol1O AND n111i1lO))) AND (NOT (niOl1Ol1l AND n111i1Oi))) AND (NOT (niOl1Ol1i AND n111i1Ol))); + niOl1Ol0i <= (nlOO00liO OR n0i000ii); + niOl1Ol0l <= (nlOO00lil OR n00ill1O); + niOl1Ol0O <= (nlOO00lii OR n01O1OOl); + niOl1Ol1i <= (nlOO00llO OR n0O0O00i); + niOl1Ol1l <= (nlOO00lll OR n0ll0iOO); + niOl1Ol1O <= (nlOO00lli OR n0iOlOll); + niOl1Olii <= (nlOO00l0O OR n011l0li); + niOl1Olil <= (nlOO00l0l OR n1Oi1l0O); + niOl1OliO <= (((((((wire_w_lg_niOl00Oil26914w(0) AND wire_w_lg_niOl00Oii26915w(0)) AND wire_w_lg_niOl00O0O26917w(0)) AND wire_w_lg_niOl00O0l26919w(0)) AND wire_w_lg_niOl00O0i26921w(0)) AND wire_w_lg_niOl00O1O26923w(0)) AND wire_w_lg_niOl00O1l26925w(0)) AND wire_w_lg_niOl00O1i26927w(0)); + niOl1Olli <= (n11O0lil OR n11O0l1l); + niOl1Olll <= (((((((wire_niO01ill_w_lg_n1101liO11541w(0) AND wire_niO01ill_w_lg_n1101lil12462w(0)) AND wire_niO01ill_w_lg_n1101lii13369w(0)) AND wire_niO01ill_w_lg_n1101l0O14276w(0)) AND wire_niO01ill_w_lg_n1101l0l15183w(0)) AND wire_niO01ill_w_lg_n1101l0i16090w(0)) AND wire_niO01ill_w_lg_n1101l1O16997w(0)) AND wire_niO01ill_w_lg_n1101l1l17904w(0)); + niOl1OllO <= (((niOl1OO1i OR niOl1OlOO) OR niOl1OlOl) OR niOl1OlOi); + niOl1OlOi <= ((((wire_niO01ill_w_lg_w_lg_w_lg_n1101liO26878w26879w26880w(0) AND wire_niO01ill_w_lg_n1101l0l15183w(0)) AND n1101l0i) AND n1101l1O) AND n1101l1l); + niOl1OlOl <= ((wire_niO01ill_w_lg_w26895w26896w(0) AND wire_niO01ill_w_lg_n1101l1O16997w(0)) AND n1101l1l); + niOl1OlOO <= (wire_niO01ill_w_lg_w_lg_w26895w26896w26908w(0) AND wire_niO01ill_w_lg_n1101l1l17904w(0)); + niOl1OO0i <= ((wire_niO01ill_w_lg_w26895w26896w(0) AND wire_niO01ill_w_lg_n1101l1O16997w(0)) AND wire_niO01ill_w_lg_n1101l1l17904w(0)); + niOl1OO0l <= (((((((wire_niO01ill_w_lg_n1101liO11541w(0) AND wire_niO01ill_w_lg_n1101lil12462w(0)) AND n1101lii) AND n1101l0O) AND n1101l0l) AND n1101l0i) AND n1101l1O) AND n1101l1l); + niOl1OO0O <= (niOl1OOil OR niOl1OOii); + niOl1OO1i <= (((((((wire_niO01ill_w_lg_n1101liO11541w(0) AND n1101lil) AND n1101lii) AND n1101l0O) AND n1101l0l) AND n1101l0i) AND n1101l1O) AND n1101l1l); + niOl1OO1l <= ((niOl1OO0l OR niOl1OO0i) OR niOl1OO1O); + niOl1OO1O <= ((((wire_niO01ill_w_lg_w_lg_w_lg_n1101liO26878w26879w26880w(0) AND wire_niO01ill_w_lg_n1101l0l15183w(0)) AND wire_niO01ill_w_lg_n1101l0i16090w(0)) AND n1101l1O) AND n1101l1l); + niOl1OOii <= (((((((wire_niO01ill_w_lg_n1101liO11541w(0) AND wire_niO01ill_w_lg_n1101lil12462w(0)) AND wire_niO01ill_w_lg_n1101lii13369w(0)) AND wire_niO01ill_w_lg_n1101l0O14276w(0)) AND n1101l0l) AND n1101l0i) AND n1101l1O) AND n1101l1l); + niOl1OOil <= ((((wire_niO01ill_w_lg_w_lg_w_lg_n1101liO26878w26879w26880w(0) AND wire_niO01ill_w_lg_n1101l0l15183w(0)) AND wire_niO01ill_w_lg_n1101l0i16090w(0)) AND wire_niO01ill_w_lg_n1101l1O16997w(0)) AND wire_niO01ill_w_lg_n1101l1l17904w(0)); + niOl1OOiO <= (n11O0O1O OR n11O0lOl); + niOl1OOli <= ((((((((NOT (n111i1ii AND niOl1O1Ol)) AND (NOT (n111i1il AND niOl1O1lO))) AND (NOT (niOl1OOOl AND n111i1iO))) AND (NOT (n111i1li AND niOl1O1ll))) AND (NOT (niOl1OOOi AND n111i1ll))) AND (NOT (niOl1OOlO AND n111i1lO))) AND (NOT (niOl1OOll AND n111i1Oi))) AND (NOT (n111i1Ol AND niOl1O1li))); + niOl1OOll <= (n0ll0lll OR n0ll0lli); + niOl1OOlO <= (n0iOO1ii OR n0iOO10O); + niOl1OOOi <= (n0i00i1O OR n0i00i1l); + niOl1OOOl <= (n01O01li OR n01O01iO); + niOl1OOOO <= ((((((((((((((NOT wire_n110100O_o(14)) AND (NOT (wire_n110100O_o(1) XOR nlOliO0ll))) AND (NOT (wire_n110100O_o(2) XOR nlOll01iO))) AND (NOT (wire_n110100O_o(3) XOR nlOll01li))) AND (NOT (wire_n110100O_o(4) XOR nlOll01ll))) AND (NOT (wire_n110100O_o(5) XOR nlOll01lO))) AND (NOT (wire_n110100O_o(6) XOR nlOll01Oi))) AND (NOT (wire_n110100O_o(7) XOR nlOll01Ol))) AND (NOT (wire_n110100O_o(8) XOR nlOll01OO))) AND (NOT (wire_n110100O_o(9) XOR nlOll001i))) AND (NOT (wire_n110100O_o(10) XOR nlOll001l))) AND (NOT (wire_n110100O_o(11) XOR nlOll001O))) AND (NOT (wire_n110100O_o(12) XOR nlOll000i))) AND (NOT (wire_n110100O_o(13) XOR nlOll000l))); + niOli000i <= (niOli00ii AND wire_w_lg_niOli0O1l19558w(0)); + niOli000l <= (wire_niO01ill_w_lg_n1101lli18954w(0) AND (wire_niO01ill_w_lg_n11O0lli18955w(0) AND (((n1lilO0l AND wire_n1l1Ol0O_dataout) AND wire_w_lg_niOli0lOO18956w(0)) AND wire_w_lg_niOli0lOl18958w(0)))); + niOli000O <= ((wire_niO01ill_w_lg_w_lg_w19898w19899w19900w(0) AND wire_niO01ill_w_lg_n1l001il19881w(0)) AND wire_niO01ill_w_lg_n1l001ii19891w(0)); + niOli001i <= (n1lilO0l AND niOli0l1O); + niOli001l <= (n1lilO0l AND niOli0l0O); + niOli001O <= (n1lilO0l AND niOli0lil); + niOli00ii <= ((wire_niO01ill_w_lg_w_lg_w19887w19888w19889w(0) AND wire_niO01ill_w_lg_n1l001il19881w(0)) AND wire_niO01ill_w_lg_n1l001ii19891w(0)); + niOli00il <= (nlOlOiO1O AND n1l0001i); + niOli00iO <= (n1lilO0l AND niOli0lOl); + niOli00li <= (n1lillOi AND niOli0lOO); + niOli00ll <= (n1lilO0l AND niOli0lli); + niOli00lO <= (n1lilO0l AND niOli0l0O); + niOli00Oi <= (n1lilO0l AND niOli0l0l); + niOli00Ol <= (n1lilO0l AND niOli0l0i); + niOli00OO <= (n1lilO0l AND niOli0l1O); + niOli010i <= ((wire_n1l1Ol0O_dataout AND niOli000O) AND wire_niO01ill_w_lg_w_lg_n1l0011O19569w19570w(0)); + niOli010l <= (niOli00ii AND niOli0l0l); + niOli010O <= (niOli01ii AND niOli0l0l); + niOli011i <= (wire_niO01ill_w_lg_w_lg_w_lg_n1lill0O19911w19913w19914w(0) AND n1lill1O); + niOli011l <= (wire_niO01ill_w_lg_w_lg_n1lill0O19918w19919w(0) AND wire_niO01ill_w_lg_n1lill1O19915w(0)); + niOli011O <= (n1l0011O AND wire_niO01ill_w_lg_n1l0011l19903w(0)); + niOli01ii <= ((wire_niO01ill_w_lg_w_lg_w_lg_w19876w19877w19879w19880w(0) AND wire_niO01ill_w_lg_n1l001il19881w(0)) AND n1l001ii); + niOli01il <= (n1l000lO AND wire_niO01ill_w_lg_n1l000ll19831w(0)); + niOli01iO <= (wire_niO01ill_w_lg_n1l000lO19828w(0) AND wire_niO01ill_w_lg_n1l000ll19831w(0)); + niOli01li <= ((n1l000Oi AND n1l000lO) AND wire_niO01ill_w_lg_n1l000ll19831w(0)); + niOli01ll <= (wire_niO01ill_w_lg_n1l000Oi19865w(0) AND n1l000ll); + niOli01lO <= (wire_niO01ill_w_lg_n1l000Oi19865w(0) AND wire_niO01ill_w_lg_n1l000ll19831w(0)); + niOli01Oi <= (wire_niO01ill_w_lg_n1l000Oi19826w(0) AND n1l000lO); + niOli01Ol <= (n1lilO0l AND wire_w_lg_niOli01OO19562w(0)); + niOli01OO <= (wire_niO01ill_w_lg_n11i111l19781w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)); + niOli0i0i <= (((((((((((wire_w_lg_niOli0iil18989w(0) OR n1lilOil) OR n1lilO0i) OR n1lilO1l) OR n1lilO1i) OR n1lillOO) OR n1lillOl) OR n1lillOi) OR n1lilllO) OR n1lillll) OR n1lillli) OR n1lilliO); + niOli0i0l <= (((((((((((wire_w_lg_niOli0iil18989w(0) OR n1lilOil) OR n1lilO0i) OR n1lilO1O) OR n1lilO1l) OR n1lilO1i) OR n1lillOO) OR n1lillOl) OR n1lilllO) OR n1lillll) OR n1lillli) OR n1lilliO); + niOli0i0O <= ((n1lilO1i OR n1lillOO) OR n1lillOl); + niOli0i1i <= (n1lilO0l OR n1lilO0i); + niOli0i1l <= wire_niO01ill_w19844w(0); + niOli0i1O <= (n1lillOl OR (n1lilO0i AND wire_niO01ill_w_lg_n1lO0lOi9962w(0))); + niOli0iii <= ((wire_niO01ill_w_lg_n1lilO0l18986w(0) OR n1lillOO) OR n1lillOl); + niOli0iil <= ((((((((((((n1lilOil OR n1lilO0l) OR n1lilO0i) OR n1lilO1O) OR n1lilO1l) OR n1lilO1i) OR n1lillOO) OR n1lillOl) OR n1lillOi) OR n1lilllO) OR n1lillll) OR n1lillli) OR n1lilliO); + niOli0iiO <= (((((((wire_niO10O1i_w_lg_dataout19787w(0) AND wire_niO10l1i_w_lg_dataout19790w(0)) AND wire_niO10i1i_w_lg_dataout19794w(0)) AND wire_niO1001i_w_lg_dataout19798w(0)) AND wire_niO1011i_w_lg_dataout19802w(0)) AND wire_niO11O1i_w_lg_dataout19806w(0)) AND wire_niO11l1i_w_lg_dataout19810w(0)) AND wire_niO11i1i_w_lg_dataout19814w(0)); + niOli0ili <= (((wire_niO01ill_w_lg_n1l000Ol19825w(0) AND wire_niO01ill_w_lg_n1l000Oi19826w(0)) AND wire_niO01ill_w_lg_n1l000lO19828w(0)) AND n1l000ll); + niOli0ill <= (((wire_niO01ill_w_lg_n1l000Ol19825w(0) AND wire_niO01ill_w_lg_n1l000Oi19826w(0)) AND wire_niO01ill_w_lg_n1l000lO19828w(0)) AND wire_niO01ill_w_lg_n1l000ll19831w(0)); + niOli0ilO <= (((wire_niO01ill_w_lg_n1l00i1O19818w(0) AND wire_niO01ill_w_lg_n1l00i1l19819w(0)) AND wire_niO01ill_w_lg_n1l00i1i19784w(0)) AND n1l000OO); + niOli0iOi <= (((wire_niO01ill_w_lg_n1l00i1O19818w(0) AND wire_niO01ill_w_lg_n1l00i1l19819w(0)) AND wire_niO01ill_w_lg_n1l00i1i19784w(0)) AND wire_niO01ill_w_lg_n1l000OO19823w(0)); + niOli0iOl <= ((((((((NOT (wire_niO10O1i_w_lg_dataout19787w(0) AND n1l0001O)) AND (NOT (wire_niO10l1i_w_lg_dataout19790w(0) AND n1l0000i))) AND (NOT (wire_niO10i1i_w_lg_dataout19794w(0) AND n1l0000l))) AND (NOT (wire_niO1001i_w_lg_dataout19798w(0) AND n1l0000O))) AND (NOT (wire_niO1011i_w_lg_dataout19802w(0) AND n1l000ii))) AND (NOT (wire_niO11O1i_w_lg_dataout19806w(0) AND n1l000il))) AND (NOT (wire_niO11l1i_w_lg_dataout19810w(0) AND n1l000iO))) AND (NOT (wire_niO11i1i_w_lg_dataout19814w(0) AND n1l000li))); + niOli0iOO <= ((wire_niO01ill_w_lg_n1l00i1O19783w(0) AND wire_niO01ill_w_lg_n1l00i1i19784w(0)) AND n1l000OO); + niOli0l0i <= (wire_niO01ill_w_lg_w_lg_n11i111O19857w19858w(0) AND n110OOOO); + niOli0l0l <= wire_niO01ill_w19926w(0); + niOli0l0O <= ((wire_niO01ill_w_lg_n11i111O19846w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND n110OOOO); + niOli0l1i <= ((wire_niO01ill_w_lg_n1l00i1O19783w(0) AND wire_niO01ill_w_lg_n1l00i1i19784w(0)) AND wire_niO01ill_w_lg_n1l000OO19823w(0)); + niOli0l1l <= (wire_niO01ill_w_lg_n11i111l19781w(0) AND n11i111i); + niOli0l1O <= (wire_niO01ill_w_lg_w_lg_n11i111O19857w19858w(0) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli0lii <= (n11O0lli OR niOli0lil); + niOli0lil <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19841w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli0liO <= (((wire_niO01ill_w_lg_n1lill1l18967w(0) AND n1lill1i) AND niOli0lli) AND n1l00i0i); + niOli0lli <= ((wire_niO01ill_w_lg_n11i111O19846w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli0lll <= (((wire_niO01ill_w_lg_n1101lli18954w(0) AND (wire_niO01ill_w_lg_n11O0lli18955w(0) AND (wire_n1l1Ol0O_w_lg_dataout18957w(0) AND wire_w_lg_niOli0lOl18958w(0)))) AND wire_niO01ill_w_lg_n1lilill18949w(0)) AND ((niOli0lOi AND niOli0llO) OR wire_w_lg_niOli0llO18964w(0))); + niOli0llO <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19841w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND n110OOOO); + niOli0lOi <= ((((((((NOT (nlOlO0lOO XOR n1l1Ol0l)) AND (NOT (nlOlOi1Oi XOR n1l1O1il))) AND (NOT (nlOlOi1Ol XOR n1l1O1iO))) AND (NOT (nlOlOi1OO XOR n1l1O1li))) AND (NOT (nlOlOi01i XOR n1l1O1ll))) AND (NOT (nlOlOi01l XOR n1l1O1lO))) AND (NOT (nlOlOi01O XOR n1l1O1Oi))) AND (NOT (nlOlOi00i XOR n1l1O1Ol))); + niOli0lOl <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19850w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND n110OOOO); + niOli0lOO <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19850w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli0O0i <= (wire_niO01ill_w_lg_n1l1OlOi18938w(0) AND wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + niOli0O0l <= (n1lOi1OO OR (n1lOi01i OR (n1lOi01l OR (wire_niO01ill_w_lg_n1110O0O18762w(0) OR n1lOi01O)))); + niOli0O0O <= (niil010O OR niil010l); + niOli0O1i <= (wire_nlOi0il1i_dataout AND niOli0O1l); + niOli0O1l <= ((n11i111l AND n11i111i) AND n110OOOO); + niOli0O1O <= (n1l1OlOi AND n1lO0llO); + niOli0Oii <= ((wire_niO01ill_w_lg_n1lOi01O18792w(0) OR n1lOi01i) OR n1lOi1OO); + niOli0Oil <= ((wire_niO01ill_w_lg_n1lOi01O18792w(0) OR n1lOi01i) OR n1lOi1OO); + niOli0OiO <= (wire_niO01ill_w_lg_n1lOi01O18792w(0) OR n1lOi01i); + niOli0Oli <= ((wire_niO01ill_w_lg_n1lOi1Ol18942w(0) AND wire_niO01ill_w_lg_n1lOi1Oi18943w(0)) AND n1lOi1lO); + niOli0Oll <= (wire_nlOiOl1lO_dataout AND n1lO0lOl); + niOli0OlO <= (niil010O OR wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + niOli0OOi <= (n1l1OlOi AND n1lO0lOl); + niOli0OOl <= (wire_nlOiOl1lO_w_lg_dataout18765w(0) AND (wire_nlOiOl1ll_dataout AND n1lO0lOl)); + niOli0OOO <= (wire_niO01ill_w_lg_n1110O0O18762w(0) OR (wire_nlOiOi1ll_dataout AND n1lO0lOl)); + niOli100i <= (niOO0Olii AND n11O0llO); + niOli100l <= (niOO0Olii AND n11O0O0O); + niOli100O <= (((((((wire_niO01ill_w_lg_nlOO0i0ii25233w(0) AND wire_niO01ill_w_lg_nlOO0i00O25234w(0)) AND wire_niO01ill_w_lg_nlOO0i00l25236w(0)) AND wire_niO01ill_w_lg_nlOO0i00i25238w(0)) AND wire_niO01ill_w_lg_nlOO0i01O25240w(0)) AND wire_niO01ill_w_lg_nlOO0i01l25242w(0)) AND wire_niO01ill_w_lg_nlOO0i01i25244w(0)) AND wire_niO01ill_w_lg_nlOO0i1OO25246w(0)); + niOli101i <= (((((((((((wire_niO01ill_w_lg_n1iO0l0l25278w(0) AND wire_niO01ill_w_lg_n1iO0l0i25279w(0)) AND wire_niO01ill_w_lg_n1iO0l1O25281w(0)) AND wire_niO01ill_w_lg_n1iO0l1l25283w(0)) AND wire_niO01ill_w_lg_n1iO0l1i25285w(0)) AND wire_niO01ill_w_lg_n1iO0iOO25287w(0)) AND wire_niO01ill_w_lg_n1iO0iOl25289w(0)) AND wire_niO01ill_w_lg_n1iO0iOi25291w(0)) AND wire_niO01ill_w_lg_n1iO0ilO25293w(0)) AND wire_niO01ill_w_lg_n1iO0ill25295w(0)) AND wire_niO01ill_w_lg_n1iO0ili25297w(0)) AND wire_niO01ill_w_lg_n1iO001l25299w(0)); + niOli101l <= ((wire_niO01ill_w_lg_n11i111O19846w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli101O <= (n11O0l0O AND n1110Oii); + niOli10ii <= (((((((wire_niO01ill_w_lg_nlOO00i1O25248w(0) AND wire_niO01ill_w_lg_nlOO00i1l25249w(0)) AND wire_niO01ill_w_lg_nlOO00i1i25251w(0)) AND wire_niO01ill_w_lg_nlOO000OO25253w(0)) AND wire_niO01ill_w_lg_nlOO000Ol25255w(0)) AND wire_niO01ill_w_lg_nlOO000Oi25257w(0)) AND wire_niO01ill_w_lg_nlOO000lO25259w(0)) AND wire_niO01ill_w_lg_nlOO000ll25261w(0)); + niOli10il <= (((((((wire_niO01ill_w_lg_nlOO0i0OO26303w(0) AND wire_niO01ill_w_lg_nlOO0i0Ol26304w(0)) AND wire_niO01ill_w_lg_nlOO0i0Oi26306w(0)) AND wire_niO01ill_w_lg_nlOO0i0lO26308w(0)) AND wire_niO01ill_w_lg_nlOO0i0ll26310w(0)) AND wire_niO01ill_w_lg_nlOO0i0li26312w(0)) AND wire_niO01ill_w_lg_nlOO0i0iO26314w(0)) AND wire_niO01ill_w_lg_nlOO0i0il26316w(0)); + niOli10iO <= (((((((wire_niO01ill_w_lg_nlOO0illO25263w(0) AND wire_niO01ill_w_lg_nlOO0illl25264w(0)) AND wire_niO01ill_w_lg_nlOO0illi25266w(0)) AND wire_niO01ill_w_lg_nlOO0iliO25268w(0)) AND wire_niO01ill_w_lg_nlOO0ilil25270w(0)) AND wire_niO01ill_w_lg_nlOO0ilii25272w(0)) AND wire_niO01ill_w_lg_nlOO0il0O25274w(0)) AND wire_niO01ill_w_lg_nlOO0il0l25276w(0)); + niOli10li <= ((((wire_niO01ill_w_lg_n1iOl10i25220w(0) AND (NOT (wire_n1l11l1i_dataout XOR n1iOl10O))) AND (NOT (wire_n1l11l1l_dataout XOR n1iOl1ii))) AND (NOT (wire_n1l11l1O_dataout XOR n1iOl1il))) AND (NOT (wire_n1l11l0i_dataout XOR n1iOl1iO))); + niOli10ll <= ((((((wire_niO01ill_w_lg_w25198w25199w(0) AND (NOT (niOO0Olii XOR n1iOl01O))) AND (NOT (wire_niO01ill_w_lg_niOO0Olii20546w(0) XOR n1iOl0ii))) AND (NOT (wire_niO01ill_w_lg_niOO0Olii20546w(0) XOR n1iOl0iO))) AND (NOT (wire_niO01ill_w_lg_niOO0Olii20546w(0) XOR n1iOl0li))) AND (NOT (wire_niO01ill_w_lg_niOO0Olii20546w(0) XOR n1iOl0ll))) AND (NOT (wire_niO01ill_w_lg_niOO0Olii20546w(0) XOR n1iOl0lO))); + niOli10lO <= (niOli10OO OR niOli10Oi); + niOli10Oi <= (n11O0l0i AND wire_w_lg_niOli10Ol20065w(0)); + niOli10Ol <= ((wire_niO01ill_w_lg_w_lg_n11i111O19840w19850w(0) AND wire_niO01ill_w_lg_n11i111i19847w(0)) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli10OO <= (niOlO1O0i OR n1iOl0Ol); + niOli110i <= ((n1ilOOiO AND wire_niO01ill_w_lg_n1ilOOil20296w(0)) AND n11O0lll); + niOli110l <= ((((niOli101l AND n1lillil) OR n11O0i0O) OR niOli110O) OR niOli1iOl); + niOli110O <= (n1lillll AND n1lillil); + niOli111i <= (wire_w_lg_w_lg_niOli11il20299w20300w(0) AND wire_w_lg_niOli111l20301w(0)); + niOli111l <= (((((wire_niO01ill_w_lg_n1iO11il26667w(0) AND wire_niO01ill_w_lg_n1iO11ii26668w(0)) AND wire_niO01ill_w_lg_n1iO110O26670w(0)) AND wire_niO01ill_w_lg_n1iO110l26672w(0)) AND wire_niO01ill_w_lg_n1iO110i26674w(0)) AND wire_niO01ill_w_lg_n1iO111O26676w(0)); + niOli111O <= (wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19850w19921w(0) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli11ii <= ((wire_w_lg_niOli11iO20255w(0) AND n1lillil) AND niOli11il); + niOli11il <= (wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19850w19921w(0) AND n110OOOO); + niOli11iO <= ((((wire_niO01ill_w_lg_n1iO001i25331w(0) AND wire_niO01ill_w_lg_n1iO01OO25332w(0)) AND wire_niO01ill_w_lg_n1iO01Ol25334w(0)) AND wire_niO01ill_w_lg_n1iO01Oi25336w(0)) AND wire_niO01ill_w_lg_n1iO11iO25338w(0)); + niOli11li <= ((wire_n1iOilOO_w_lg_dataout20251w(0) OR wire_w_lg_niOli11ll20252w(0)) OR niOli11lO); + niOli11ll <= (((((((wire_niO01ill_w_lg_n1Oi11Oi26357w(0) AND wire_niO01ill_w_lg_n011iO1l26358w(0)) AND wire_niO01ill_w_lg_n01O1i0O26360w(0)) AND wire_niO01ill_w_lg_n00il1li26362w(0)) AND wire_niO01ill_w_lg_n0i01lOl26364w(0)) AND wire_niO01ill_w_lg_n0iOli1O26366w(0)) AND wire_niO01ill_w_lg_n0ll01ii26368w(0)) AND wire_niO01ill_w_lg_n0O0llll26370w(0)); + niOli11lO <= (wire_w_lg_niOli11Ol20248w(0) AND niOli11Oi); + niOli11Oi <= (((((((wire_niO01ill_w_lg_n1iO111l25316w(0) AND wire_niO01ill_w_lg_n1iO111i25317w(0)) AND wire_niO01ill_w_lg_n1ilOOOO25319w(0)) AND wire_niO01ill_w_lg_n1ilOOOl25321w(0)) AND wire_niO01ill_w_lg_n1ilOOOi25323w(0)) AND wire_niO01ill_w_lg_n1ilOOlO25325w(0)) AND wire_niO01ill_w_lg_n1ilOOll25327w(0)) AND wire_niO01ill_w_lg_n1ilOOli25329w(0)); + niOli11Ol <= (((((((wire_niO01ill_w_lg_n1Oi1O1i25301w(0) AND wire_niO01ill_w_lg_n011li0l25302w(0)) AND wire_niO01ill_w_lg_n01O01iO25304w(0)) AND wire_niO01ill_w_lg_n00illOi25306w(0)) AND wire_niO01ill_w_lg_n0i00i1l25308w(0)) AND wire_niO01ill_w_lg_n0iOO10O25310w(0)) AND wire_niO01ill_w_lg_n0ll0lli25312w(0)) AND wire_niO01ill_w_lg_n0O0O0Ol25314w(0)); + niOli11OO <= (wire_w_lg_w_lg_niOli101l20190w20191w(0) AND wire_w_lg_niOli101i20192w(0)); + niOli1i0i <= (wire_w_lg_niOl0llOO24168w(0) AND wire_w_lg_niOl0llli20856w(0)); + niOli1i0l <= (wire_w_lg_niOl0llil24173w(0) AND wire_w_lg_niOl0ll1O20864w(0)); + niOli1i0O <= (wire_w_lg_niOl0ll1i24178w(0) AND wire_w_lg_niOl0lill20872w(0)); + niOli1i1i <= (wire_w_lg_niOl0O10O24153w(0) AND wire_w_lg_niOl0O11i20832w(0)); + niOli1i1l <= (wire_w_lg_niOl0lOOl24158w(0) AND wire_w_lg_niOl0lOiO20840w(0)); + niOli1i1O <= (wire_w_lg_niOl0lOii24163w(0) AND wire_w_lg_niOl0lO1l20848w(0)); + niOli1iii <= (wire_w_lg_niOl0liiO24183w(0) AND wire_w_lg_niOl0li0i20880w(0)); + niOli1iil <= (wire_w_lg_niOl0li1l24188w(0) AND wire_w_lg_niOl0l0lO20888w(0)); + niOli1iiO <= (((((((wire_niO01ill_w_lg_n1l110il25165w(0) AND wire_niO01ill_w_lg_n1l110ii25166w(0)) AND wire_niO01ill_w_lg_n1l1100O25168w(0)) AND wire_niO01ill_w_lg_n1l1100l25170w(0)) AND wire_niO01ill_w_lg_n1l1100i25172w(0)) AND wire_niO01ill_w_lg_n1l1101O25174w(0)) AND wire_niO01ill_w_lg_n1l1101l25176w(0)) AND wire_niO01ill_w_lg_n1l1101i25178w(0)); + niOli1ili <= (niOO0Olii AND n11O0l0O); + niOli1ill <= (niOO0Olii AND (n11O0O0O OR n11O0llO)); + niOli1ilO <= (niOO0Olii AND niOli1iOi); + niOli1iOi <= (n11O0Oil OR n11O0Oii); + niOli1iOl <= wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0); + niOli1iOO <= (n11li1li AND wire_niO01iOi_w_lg_n11li1iO9835w(0)); + niOli1l0i <= (wire_nlOii0l0O_w_lg_dataout21190w(0) AND wire_nlOii0lli_w_lg_dataout25161w(0)); + niOli1l0l <= (wire_w_lg_niOli0i1O19683w(0) AND wire_w_lg_niOli1lli19684w(0)); + niOli1l0O <= (niOli0O1i AND niOli1lil); + niOli1l1i <= (wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0) OR niOli1l1O); + niOli1l1l <= (wire_w_lg_niOO10lOO8902w(0) AND wire_nlOii0lli_dataout); + niOli1l1O <= (wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_w_lg_dataout25163w(0)); + niOli1lii <= (wire_w_lg_niOli0i1O19660w(0) AND (niOli1lil AND n1l1OlOO)); + niOli1lil <= (niOli1lOO AND niOli1lOl); + niOli1liO <= (niOli0i1O AND niOli1lli); + niOli1lli <= (wire_niO01ill_w_lg_n1l1OO1l19974w(0) AND wire_niO01ill_w_lg_n1l1OO1i19975w(0)); + niOli1lll <= (wire_niO01ill_w_lg_n1lilO0l19657w(0) AND n1l1OllO); + niOli1llO <= (((((((((((NOT k_cnt(85)) AND (NOT k_cnt(86))) AND (NOT k_cnt(87))) AND (NOT k_cnt(88))) AND (NOT k_cnt(89))) AND (NOT k_cnt(90))) AND (NOT k_cnt(91))) AND (NOT k_cnt(92))) AND (NOT k_cnt(93))) AND (NOT k_cnt(94))) AND (NOT k_cnt(95))); + niOli1lOi <= (wire_w_lg_niOli1lOO19594w(0) OR niOli1lOl); + niOli1lOl <= ((((((((((wire_niO01iOi_w_lg_n1l1OOOi19932w(0) AND wire_niO01ill_w_lg_n1l1OOlO19933w(0)) AND wire_niO01ill_w_lg_n1l1OOll19935w(0)) AND wire_niO01iOi_w_lg_n1l1OOli19937w(0)) AND wire_niO01ill_w_lg_n1l1OOiO19939w(0)) AND wire_niO01iOi_w_lg_n1l1OOil19941w(0)) AND wire_niO01ill_w_lg_n1l1OOii19943w(0)) AND wire_niO01ill_w_lg_n1l1OO0O19945w(0)) AND wire_niO01iOi_w_lg_n1l1OO0l19947w(0)) AND wire_niO01ill_w_lg_n1l1OO0i19949w(0)) AND wire_niO01ill_w_lg_n1l1OO1O19951w(0)); + niOli1lOO <= (niOli0O1i OR ((wire_w_lg_niOli01OO19562w(0) AND wire_w_lg_niOli0O1l19558w(0)) OR niOli0lli)); + niOli1O0i <= (n1lilO0l AND niOli0l0l); + niOli1O0l <= (wire_niO01ill_w_lg_n1lilill18949w(0) AND wire_niO01ill_w_lg_n1lilO0l19585w(0)); + niOli1O0O <= (((wire_niO01ill_w_lg_n1l000Ol19825w(0) AND wire_niO01ill_w_lg_n1l000Oi19826w(0)) AND n1l000lO) AND n1l000ll); + niOli1O1i <= (n1lilO1O AND niOli0iOO); + niOli1O1l <= (n1lilO1O AND niOli1Oii); + niOli1O1O <= (n1lilO0l AND niOli0l0i); + niOli1Oii <= (wire_niO01ill_w_lg_w_lg_n1l00i1O19783w19928w(0) AND wire_niO01ill_w_lg_n1l000OO19823w(0)); + niOli1Oil <= (wire_niO01ill_w_lg_w_lg_n1l00i1O19905w19906w(0) AND n1l000OO); + niOli1OiO <= (niOli1l1l OR n1l10iiO); + niOli1Oli <= (wire_niO01ill_w_lg_w_lg_n1l00i1O19905w19906w(0) AND wire_niO01ill_w_lg_n1l000OO19823w(0)); + niOli1Oll <= ((wire_niO01ill_w_lg_n1l00i1O19905w(0) AND wire_niO01ill_w_lg_n1l00i1i19784w(0)) AND n1l000OO); + niOli1OlO <= (wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19850w19921w(0) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli1OOi <= (wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19850w19921w(0) AND n110OOOO); + niOli1OOl <= (wire_niO01ill_w_lg_w_lg_n11i111O19846w19924w(0) AND wire_niO01ill_w_lg_n110OOOO19843w(0)); + niOli1OOO <= (wire_niO01ill_w_lg_w_lg_w_lg_n1lill0O19911w19913w19914w(0) AND wire_niO01ill_w_lg_n1lill1O19915w(0)); + niOlii00i <= (n1Oili0O OR (niOlO1O0i OR n1Oiliil)); + niOlii00l <= ((((((wire_niO01ill_w_lg_w_lg_w18311w18314w18315w(0) AND ((((NOT (n1OililO XOR n1Oi1O0i)) AND (NOT (n1OiliOi XOR n1Oi1O0l))) AND (NOT (n1OiliOl XOR n1Oi1O0O))) AND (NOT (n1OiliOO XOR n1Oi1Oii)))) AND (((NOT (n1OilliO XOR n1Oi011i)) AND (NOT (n1Oillli XOR n1Oi011l))) AND (NOT (n1Oillll XOR n1Oi011O)))) AND (NOT (n1Oilili XOR n1Oi1O1l))) AND (NOT (n1OiliiO XOR n1Oi1O1i))) AND (NOT (n1Oilill XOR n1Oi1O1O))) AND (NOT (n1Oili0l XOR n1Oi1l0l))); + niOlii00O <= ((((((((NOT (n1Oill1i XOR n1Oi1Oil)) AND (NOT (n1Oill1l XOR n1Oi1OiO))) AND (NOT (n1Oill1O XOR n1Oi1Oli))) AND (NOT (n1Oill0i XOR n1Oi1Oll))) AND (NOT (n1Oill0l XOR n1Oi1OlO))) AND (NOT (n1Oill0O XOR n1Oi1OOi))) AND (NOT (n1Oillii XOR n1Oi1OOl))) AND (NOT (n1Oillil XOR n1Oi1OOO))); + niOlii01i <= ((n1Oiliii AND niOlii00l) AND wire_w_lg_niOlii01l18354w(0)); + niOlii01l <= (((((((n1Oi1lOO AND n1Oi1lOl) AND n1Oi1lOi) AND n1Oi1llO) AND n1Oi1lll) AND n1Oi1lli) AND n1Oi1liO) AND n1Oi1lil); + niOlii01O <= (n1Oiliii AND wire_w_lg_niOlii00l18351w(0)); + niOlii0ii <= ((((((((NOT (n1OilO1O XOR n1Oi01li)) AND (NOT (n1OilO0i XOR n1Oi01ll))) AND (NOT (n1OilO0l XOR n1Oi01lO))) AND (NOT (n1OilO0O XOR n1Oi01Oi))) AND (NOT (n1OilOii XOR n1Oi01Ol))) AND (NOT (n1OilOil XOR n1Oi01OO))) AND (NOT (n1OilOiO XOR n1Oi001i))) AND (NOT (n1OilOli XOR n1Oi001l))); + niOlii0il <= (((((NOT (n1OilllO XOR n1Oi010i)) AND (NOT (n1OillOi XOR n1Oi010l))) AND (NOT (n1OillOl XOR n1Oi010O))) AND (NOT (n1OillOO XOR n1Oi01ii))) AND (NOT (n1OilO1i XOR n1Oi01il))); + niOlii0iO <= (n1Ol00li AND niOlii1OO); + niOlii0li <= (wire_niO01iOi_w_lg_w_lg_n1OilOOO18272w18585w(0) AND wire_niO01iOi_w_lg_n1OilOlO18580w(0)); + niOlii0ll <= (wire_niO01iOi_w_lg_w_lg_n1OilOOO18272w18585w(0) AND n1OilOlO); + niOlii0lO <= (((n1OilOOO AND n1OilOOl) AND wire_niO01iOi_w_lg_n1OilOOi18273w(0)) AND wire_niO01iOi_w_lg_n1OilOlO18580w(0)); + niOlii0Oi <= (((n1OilOOO AND n1OilOOl) AND n1OilOOi) AND n1OilOlO); + niOlii0Ol <= ((niOliiiOO OR niOliii1i) OR (niOliil1i AND niOlii0OO)); + niOlii0OO <= (((n1OilOOO AND n1OilOOl) AND wire_niO01iOi_w_lg_n1OilOOi18273w(0)) AND n1OilOlO); + niOlii10i <= (((wire_niO01ill_w_lg_w18745w18746w(0) AND wire_niO01ill_w_lg_n1OO0O0l18747w(0)) AND wire_niO01ill_w_lg_n1OO0O0i18749w(0)) AND n1OO0O1O); + niOlii10l <= (wire_niO10O1O_dataout OR n111i10l); + niOlii10O <= (((wire_niO10Oll_w_lg_w18501w18502w(0) AND wire_niO10O0l_w_lg_dataout18503w(0)) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_dataout); + niOlii11i <= ((wire_niO01ill_w_lg_n1lOi1Ol18942w(0) AND wire_niO01ill_w_lg_n1lOi1Oi18943w(0)) AND wire_niO01ill_w_lg_n1lOi1lO18946w(0)); + niOlii11l <= (n1OO0O1O OR (NOT (n111i10i OR n1O01Oll))); + niOlii11O <= (((wire_niO01ill_w_lg_w_lg_w18756w18757w18758w(0) AND wire_niO01ill_w_lg_n1OO0O0l18747w(0)) AND wire_niO01ill_w_lg_n1OO0O0i18749w(0)) AND n1OO0O1O); + niOlii1ii <= (((wire_niO10Oll_w_lg_w_lg_w18520w18521w18522w(0) AND wire_niO10O0l_w_lg_dataout18503w(0)) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_dataout); + niOlii1il <= (wire_niO01ill_w_lg_n1O0OllO18667w(0) AND wire_niO01ill_w_lg_n1O0Olll18668w(0)); + niOlii1iO <= (n1O0OllO AND n1O0Olll); + niOlii1li <= (wire_niO01ill_w_lg_n1Ol000i18434w(0) OR wire_w_lg_w_lg_niOliilii18159w18435w(0)); + niOlii1ll <= (niOliii0l AND niOlii1Oi); + niOlii1lO <= (niOlii1OO AND wire_w_lg_niOlii1Oi18396w(0)); + niOlii1Oi <= (((wire_niO01iOi_w_lg_n1Oi101l18660w(0) AND wire_niO01iOi_w_lg_n1Oi101i18661w(0)) AND wire_niO01iOi_w_lg_n1Oi11OO18663w(0)) AND wire_niO01iOi_w_lg_n1Oi11Ol18665w(0)); + niOlii1Ol <= (((wire_niO10Oll_w_lg_w18655w18656w(0) AND wire_niO10O0l_w_lg_dataout18503w(0)) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_dataout); + niOlii1OO <= (wire_niO10O1l_dataout AND niOlii1Ol); + niOliii0i <= ((wire_niO10Oll_w_lg_w_lg_w18501w18552w18553w(0) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_w_lg_dataout18153w(0)); + niOliii0l <= (wire_niO10O1l_dataout AND (niOliiiii OR niOliii0O)); + niOliii0O <= ((wire_niO10Oll_w_lg_w_lg_w_lg_w18563w18564w18565w18566w(0) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_w_lg_dataout18153w(0)); + niOliii1i <= (((wire_niO01iOi_w_lg_n1OilOOO18577w(0) AND wire_niO01iOi_w_lg_n1OilOOl18271w(0)) AND wire_niO01iOi_w_lg_n1OilOOi18273w(0)) AND wire_niO01iOi_w_lg_n1OilOlO18580w(0)); + niOliii1l <= (wire_niO10O1l_dataout AND (niOliii0i OR niOliii1O)); + niOliii1O <= (wire_niO10Oll_w18572w(0) AND wire_niO10O1O_w_lg_dataout18153w(0)); + niOliiiii <= (wire_niO10Oll_w_lg_w_lg_w_lg_w18556w18557w18558w18559w(0) AND wire_niO10O1O_w_lg_dataout18153w(0)); + niOliiiil <= (n1Ol00li AND (niOliil1i OR niOliiiOO)); + niOliiiiO <= (niOlO1O0i OR (NOT (wire_niO10O1l_dataout AND niOliiili))); + niOliiili <= ((((((((wire_niO10O1O_w_lg_dataout18153w(0) AND wire_n1O0i01O_w_lg_dataout18535w(0)) AND wire_n1O0i01i_w_lg_dataout18537w(0)) AND wire_n1O0i1Ol_w_lg_dataout18539w(0)) AND wire_n1O0i1lO_w_lg_dataout18541w(0)) AND wire_n1O0i1li_w_lg_dataout18543w(0)) AND wire_n1O0i1ii_w_lg_dataout18545w(0)) AND wire_n1O0i10l_w_lg_dataout18547w(0)) AND wire_n1O0i11l_w_lg_dataout18549w(0)); + niOliiill <= (n1Ol00il AND n1Ol000O); + niOliiilO <= (niOliil0l AND (wire_niO01ill_w_lg_n1Ol00ii18201w(0) AND niOliiill)); + niOliiiOi <= (niOliil0l AND (n1Ol00ii AND (n1Ol00il AND wire_niO01ill_w_lg_n1Ol000O18196w(0)))); + niOliiiOl <= (niOliil0l AND n1Ol000l); + niOliiiOO <= (wire_niO10O1O_w_lg_dataout18153w(0) AND wire_niO10O1l_dataout); + niOliil0i <= (((wire_niO10Oll_w_lg_w_lg_w18520w18521w18522w(0) AND wire_niO10O0l_w_lg_dataout18503w(0)) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_dataout); + niOliil0l <= (wire_niO10O1l_dataout AND niOliil0O); + niOliil0O <= (((wire_niO10Oll_w_lg_w_lg_w18511w18512w18513w(0) AND wire_niO10O0l_w_lg_dataout18503w(0)) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_dataout); + niOliil1i <= (wire_niO10O1l_dataout AND niOliil1l); + niOliil1l <= (((((wire_niO10Oll_w_lg_w_lg_w_lg_dataout18526w18527w18528w(0) AND wire_niO10Oii_w_lg_dataout18529w(0)) AND wire_niO10O0O_dataout) AND wire_niO10O0l_dataout) AND wire_niO10O0i_dataout) AND wire_niO10O1O_dataout); + niOliil1O <= (wire_niO10O1l_dataout AND niOliil0i); + niOliilii <= (wire_niO10O1l_dataout AND niOliilil); + niOliilil <= (((wire_niO10Oll_w_lg_w18501w18502w(0) AND wire_niO10O0l_w_lg_dataout18503w(0)) AND wire_niO10O0i_w_lg_dataout18505w(0)) AND wire_niO10O1O_dataout); + niOliiliO <= (((wire_niO10lOl_w_lg_dataout18111w(0) AND wire_niO10llO_w_lg_dataout18112w(0)) OR wire_niO10lOl_w_lg_w_lg_dataout18114w18115w(0)) AND wire_w_lg_niOliilli18117w(0)); + niOliilli <= ((((((n1Ol0lOi AND n1Ol0llO) AND n1Ol0lll) AND n1Ol0lli) AND n1Ol0liO) AND n1Ol0lil) AND n1Ol00ll); + niOliilll <= ((wire_niO01ill_w_lg_n1OO0lOi17910w(0) AND wire_w_lg_niOlil1li17913w(0)) OR wire_niO01ill_w_lg_n1O0Ol1i18108w(0)); + niOliillO <= (((NOT (wire_niili00O_dataout XOR n1OliiiO)) AND (NOT (wire_niili0ii_dataout XOR n1Oliili))) AND (NOT (n1101l1i XOR n1Oliill))); + niOliilOi <= ((wire_niO01ill_w_lg_n1OO0lOi17910w(0) AND (wire_niO01ill_w_lg_n1OO0lOO17918w(0) AND wire_w_lg_niOlil1li17913w(0))) OR wire_niO01ill_w_lg_n1Olii0l17980w(0)); + niOliilOl <= (wire_niO01ill_w_lg_n1Oli0OO18480w(0) AND wire_niO01ill_w_lg_n1Oli0Oi18044w(0)); + niOliilOO <= (wire_niO01ill_w_lg_n1Oli0OO18480w(0) AND n1Oli0Oi); + niOliiO0i <= wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18050w(0); + niOliiO0l <= ((wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18467w(0) AND wire_niO01ill_w_lg_n1Oli0Ol18042w(0)) AND wire_niO01ill_w_lg_n1Oli0Oi18044w(0)); + niOliiO0O <= ((wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18467w(0) AND wire_niO01ill_w_lg_n1Oli0Ol18042w(0)) AND n1Oli0Oi); + niOliiO1i <= (niOlil11i AND wire_n1OO111O_o); + niOliiO1l <= (n1l0001i AND (wire_n1OO11ii_o AND niOlil11i)); + niOliiO1O <= (n1l0001i AND niOlil10O); + niOliiOii <= (wire_niO01ill_w_lg_w_lg_w_lg_n1Olii1i18049w18467w18471w(0) AND wire_niO01ill_w_lg_n1Oli0Oi18044w(0)); + niOliiOil <= (wire_niO01ill_w_lg_w_lg_w_lg_n1Olii1i18049w18467w18471w(0) AND n1Oli0Oi); + niOliiOiO <= ((wire_niO01ill_w_lg_n1Olii1i18474w(0) AND wire_niO01ill_w_lg_n1Oli0Ol18042w(0)) AND wire_niO01ill_w_lg_n1Oli0Oi18044w(0)); + niOliiOli <= ((wire_niO01ill_w_lg_n1Olii1i18474w(0) AND wire_niO01ill_w_lg_n1Oli0Ol18042w(0)) AND n1Oli0Oi); + niOliiOll <= (wire_niO01ill_w_lg_n1Olii1i18474w(0) AND n1Oli0Ol); + niOliiOlO <= (n1Olii1i AND n1Oli0OO); + niOliiOOi <= (wire_niO01ill_w_lg_n1Oliiii17987w(0) AND wire_n1Oli1lO_dataout); + niOliiOOl <= (n1Oliiii AND wire_n1Oli1lO_dataout); + niOliiOOO <= (wire_niO01ill_w_lg_nlOllO0iO17973w(0) AND niOlil11i); + niOlil00i <= (wire_niO10l1O_dataout OR n111i10l); + niOlil00l <= (((wire_niO10lll_w_lg_w17594w17595w(0) AND wire_niO10l0l_w_lg_dataout17596w(0)) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_dataout); + niOlil00O <= (((wire_niO10lll_w_lg_w_lg_w17613w17614w17615w(0) AND wire_niO10l0l_w_lg_dataout17596w(0)) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_dataout); + niOlil01i <= (n01iOiii OR (NOT (n111i10i OR n1OOliOO))); + niOlil01l <= (((wire_niO01ill_w_lg_w_lg_w17849w17850w17851w(0) AND wire_niO01ill_w_lg_n01iOiiO17840w(0)) AND wire_niO01ill_w_lg_n01iOiil17842w(0)) AND n01iOiii); + niOlil01O <= (((wire_niO01ill_w_lg_w17838w17839w(0) AND wire_niO01ill_w_lg_n01iOiiO17840w(0)) AND wire_niO01ill_w_lg_n01iOiil17842w(0)) AND n01iOiii); + niOlil0ii <= (wire_niO01ill_w_lg_n011ii1i17760w(0) AND wire_niO01ill_w_lg_n011i0OO17761w(0)); + niOlil0il <= (n011ii1i AND n011i0OO); + niOlil0iO <= (wire_niO01ill_w_lg_n010lOil17527w(0) OR wire_w_lg_w_lg_niOlilO0O17252w17528w(0)); + niOlil0li <= (niOlill0i AND niOlil0lO); + niOlil0ll <= (niOlil0Ol AND wire_w_lg_niOlil0lO17489w(0)); + niOlil0lO <= (((wire_niO01iOi_w_lg_n011iO0O17753w(0) AND wire_niO01iOi_w_lg_n011iO0l17754w(0)) AND wire_niO01iOi_w_lg_n011iO0i17756w(0)) AND wire_niO01iOi_w_lg_n011iO1O17758w(0)); + niOlil0Oi <= (((wire_niO10lll_w_lg_w17748w17749w(0) AND wire_niO10l0l_w_lg_dataout17596w(0)) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_dataout); + niOlil0Ol <= (wire_niO10l1l_dataout AND niOlil0Oi); + niOlil0OO <= ((n01001ll AND niOlili0i) AND wire_w_lg_niOlili1i17447w(0)); + niOlil10i <= ((((((NOT (wire_n1OOilil_dataout XOR n1Olii0O)) AND (NOT (wire_n1OOiliO_dataout XOR n1Oliiii))) AND (NOT (wire_n1OOilli_dataout XOR n1Oliiil))) AND (NOT (wire_n1OOilll_dataout XOR n1OliiiO))) AND (NOT (wire_n1OOillO_dataout XOR n1Oliili))) AND (NOT (wire_n1OOilOi_dataout XOR n1Oliill))); + niOlil10l <= (wire_niO01ill_w_lg_nlOllO0iO17973w(0) AND (niOlil10O OR wire_n1Oli1Ol_dataout)); + niOlil10O <= (n1OO0lOO AND wire_niO01ill_w_lg_n1OO0lOl17989w(0)); + niOlil11i <= (n1OO0lOO AND n1OO0lOl); + niOlil11l <= (wire_niO01ill_w_lg_w_lg_w_lg_n1OliilO17979w17981w17982w(0) OR (n11O0O0l AND nlOllO0iO)); + niOlil11O <= (n1OO0O1l OR (n1OO0lOO AND niOlil10i)); + niOlil1ii <= (wire_niO01ill_w_lg_nlOllO0iO17973w(0) AND n1OO0lOi); + niOlil1il <= (wire_n1OO0l1O_o OR n1OliilO); + niOlil1iO <= (wire_niO01ill_w_lg_n1OO0lOi17910w(0) AND (wire_niO01ill_w_lg_n1OO0lOO17918w(0) AND wire_w_lg_niOlil1lO17908w(0))); + niOlil1li <= ((n1OO0llO AND n1OO0lll) AND n1Oll0li); + niOlil1ll <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOlil1lO <= ((wire_niO01ill_w_lg_n1OO0llO18445w(0) AND n1OO0lll) AND n1Oll0li); + niOlil1Oi <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOlil1Ol <= (wire_niO01ill_w_lg_n1101l1l17904w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOlil1OO <= (wire_niO01ill_w_lg_n1101l1l17904w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOlili0i <= ((((((wire_niO01ill_w_lg_w_lg_w17404w17407w17408w(0) AND ((((NOT (n010001i XOR n011liil)) AND (NOT (n010001l XOR n011liiO))) AND (NOT (n010001O XOR n011lili))) AND (NOT (n010000i XOR n011lill)))) AND (((NOT (n01000Oi XOR n011ll0l)) AND (NOT (n01000Ol XOR n011ll0O))) AND (NOT (n01000OO XOR n011llii)))) AND (NOT (n01001Ol XOR n011li0O))) AND (NOT (n01001Oi XOR n011li0l))) AND (NOT (n01001OO XOR n011liii))) AND (NOT (n01001iO XOR n011l0iO))); + niOlili0l <= ((((((((NOT (n010000l XOR n011lilO)) AND (NOT (n010000O XOR n011liOi))) AND (NOT (n01000ii XOR n011liOl))) AND (NOT (n01000il XOR n011liOO))) AND (NOT (n01000iO XOR n011ll1i))) AND (NOT (n01000li XOR n011ll1l))) AND (NOT (n01000ll XOR n011ll1O))) AND (NOT (n01000lO XOR n011ll0i))); + niOlili0O <= ((((((((NOT (n0100iii XOR n011llOl)) AND (NOT (n0100iil XOR n011llOO))) AND (NOT (n0100iiO XOR n011lO1i))) AND (NOT (n0100ili XOR n011lO1l))) AND (NOT (n0100ill XOR n011lO1O))) AND (NOT (n0100ilO XOR n011lO0i))) AND (NOT (n0100iOi XOR n011lO0l))) AND (NOT (n0100iOl XOR n011lO0O))); + niOlili1i <= (((((((n011li0i AND n011li1O) AND n011li1l) AND n011li1i) AND n011l0OO) AND n011l0Ol) AND n011l0Oi) AND n011l0lO); + niOlili1l <= (n01001ll AND wire_w_lg_niOlili0i17444w(0)); + niOlili1O <= (n01001li OR (niOlO1O0i OR n01001lO)); + niOliliii <= (((((NOT (n0100i1i XOR n011llil)) AND (NOT (n0100i1l XOR n011lliO))) AND (NOT (n0100i1O XOR n011llli))) AND (NOT (n0100i0i XOR n011llll))) AND (NOT (n0100i0l XOR n011lllO))); + niOliliil <= (n010lOOl AND niOlil0Ol); + niOliliiO <= (wire_niO01iOi_w_lg_w_lg_n0100l0i17365w17678w(0) AND wire_niO01iOi_w_lg_n0100l1i17673w(0)); + niOlilili <= (wire_niO01iOi_w_lg_w_lg_n0100l0i17365w17678w(0) AND n0100l1i); + niOlilill <= (((n0100l0i AND n0100l1O) AND wire_niO01iOi_w_lg_n0100l1l17366w(0)) AND wire_niO01iOi_w_lg_n0100l1i17673w(0)); + niOlililO <= (((n0100l0i AND n0100l1O) AND n0100l1l) AND n0100l1i); + niOliliOi <= ((niOlillOl OR niOliliOO) OR (niOlillOO AND niOliliOl)); + niOliliOl <= (((n0100l0i AND n0100l1O) AND wire_niO01iOi_w_lg_n0100l1l17366w(0)) AND n0100l1i); + niOliliOO <= (((wire_niO01iOi_w_lg_n0100l0i17670w(0) AND wire_niO01iOi_w_lg_n0100l1O17364w(0)) AND wire_niO01iOi_w_lg_n0100l1l17366w(0)) AND wire_niO01iOi_w_lg_n0100l1i17673w(0)); + niOlill0i <= (wire_niO10l1l_dataout AND (niOlill0O OR niOlill0l)); + niOlill0l <= ((wire_niO10lll_w_lg_w_lg_w_lg_w17656w17657w17658w17659w(0) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_w_lg_dataout17246w(0)); + niOlill0O <= (wire_niO10lll_w_lg_w_lg_w_lg_w17649w17650w17651w17652w(0) AND wire_niO10l1O_w_lg_dataout17246w(0)); + niOlill1i <= (wire_niO10l1l_dataout AND (niOlill1O OR niOlill1l)); + niOlill1l <= (wire_niO10lll_w17665w(0) AND wire_niO10l1O_w_lg_dataout17246w(0)); + niOlill1O <= ((wire_niO10lll_w_lg_w_lg_w17594w17645w17646w(0) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_w_lg_dataout17246w(0)); + niOlillii <= (n010lOOl AND (niOlillOO OR niOlillOl)); + niOlillil <= (niOlO1O0i OR (NOT (wire_niO10l1l_dataout AND niOlilliO))); + niOlilliO <= ((((((((wire_niO10l1O_w_lg_dataout17246w(0) AND wire_n1OOOOii_w_lg_dataout17628w(0)) AND wire_n1OOOO0l_w_lg_dataout17630w(0)) AND wire_n1OOOO1O_w_lg_dataout17632w(0)) AND wire_n1OOOO1i_w_lg_dataout17634w(0)) AND wire_n1OOOlOl_w_lg_dataout17636w(0)) AND wire_n1OOOlll_w_lg_dataout17638w(0)) AND wire_n1OOOliO_w_lg_dataout17640w(0)) AND wire_n1OOOl0O_w_lg_dataout17642w(0)); + niOlillli <= (n010lOlO AND n010lOli); + niOlillll <= (niOlilO0i AND (wire_niO01ill_w_lg_n010lOll17294w(0) AND niOlillli)); + niOlilllO <= (niOlilO0i AND (n010lOll AND (n010lOlO AND wire_niO01ill_w_lg_n010lOli17289w(0)))); + niOlillOi <= (niOlilO0i AND n010lOiO); + niOlillOl <= (wire_niO10l1O_w_lg_dataout17246w(0) AND wire_niO10l1l_dataout); + niOlillOO <= (wire_niO10l1l_dataout AND niOlilO1i); + niOlilO0i <= (wire_niO10l1l_dataout AND niOlilO0l); + niOlilO0l <= (((wire_niO10lll_w_lg_w_lg_w17604w17605w17606w(0) AND wire_niO10l0l_w_lg_dataout17596w(0)) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_dataout); + niOlilO0O <= (wire_niO10l1l_dataout AND niOlilOii); + niOlilO1i <= (((((wire_niO10lll_w_lg_w_lg_w_lg_dataout17619w17620w17621w(0) AND wire_niO10lii_w_lg_dataout17622w(0)) AND wire_niO10l0O_dataout) AND wire_niO10l0l_dataout) AND wire_niO10l0i_dataout) AND wire_niO10l1O_dataout); + niOlilO1l <= (wire_niO10l1l_dataout AND niOlilO1O); + niOlilO1O <= (((wire_niO10lll_w_lg_w_lg_w17613w17614w17615w(0) AND wire_niO10l0l_w_lg_dataout17596w(0)) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_dataout); + niOlilOii <= (((wire_niO10lll_w_lg_w17594w17595w(0) AND wire_niO10l0l_w_lg_dataout17596w(0)) AND wire_niO10l0i_w_lg_dataout17598w(0)) AND wire_niO10l1O_dataout); + niOlilOil <= (((wire_niO10iOl_w_lg_dataout17204w(0) AND wire_niO10ilO_w_lg_dataout17205w(0)) OR wire_niO10iOl_w_lg_w_lg_dataout17207w17208w(0)) AND wire_w_lg_niOlilOiO17210w(0)); + niOlilOiO <= ((((((n010Oi1l AND n010Oi1i) AND n010O0OO) AND n010O0Ol) AND n010O0Oi) AND n010O0lO) AND n010lOOO); + niOlilOli <= ((wire_niO01ill_w_lg_n01iOi1l17003w(0) AND wire_w_lg_niOliO0iO17006w(0)) OR wire_niO01ill_w_lg_n011i00l17201w(0)); + niOlilOll <= (((NOT (wire_niili01O_dataout XOR n01i11Oi)) AND (NOT (wire_niili00i_dataout XOR n01i11Ol))) AND (NOT (n1101l1i XOR n01i11OO))); + niOlilOlO <= ((wire_niO01ill_w_lg_n01iOi1l17003w(0) AND (wire_niO01ill_w_lg_n01iOi0i17011w(0) AND wire_w_lg_niOliO0iO17006w(0))) OR wire_niO01ill_w_lg_n01i11iO17073w(0)); + niOlilOOi <= (wire_niO01ill_w_lg_n01i110i17573w(0) AND wire_niO01ill_w_lg_n01i111l17137w(0)); + niOlilOOl <= (wire_niO01ill_w_lg_n01i110i17573w(0) AND n01i111l); + niOlilOOO <= (niOliO1OO AND wire_n01iilii_o); + niOliO00i <= (wire_niO01ill_w_lg_nlOllOliO17066w(0) AND (niOliO00l OR wire_n010OO1O_dataout)); + niOliO00l <= (n01iOi0i AND wire_niO01ill_w_lg_n01iOi1O17082w(0)); + niOliO00O <= (wire_niO01ill_w_lg_nlOllOliO17066w(0) AND n01iOi1l); + niOliO01i <= (wire_niO01ill_w_lg_w_lg_w_lg_n01i101i17072w17074w17075w(0) OR (n11O0O0l AND nlOllOliO)); + niOliO01l <= (n01iOi0O OR (n01iOi0i AND niOliO01O)); + niOliO01O <= ((((((NOT (wire_n01l10lO_dataout XOR n01i11li)) AND (NOT (wire_n01l10Oi_dataout XOR n01i11ll))) AND (NOT (wire_n01l10Ol_dataout XOR n01i11lO))) AND (NOT (wire_n01l10OO_dataout XOR n01i11Oi))) AND (NOT (wire_n01l1i1i_dataout XOR n01i11Ol))) AND (NOT (wire_n01l1i1l_dataout XOR n01i11OO))); + niOliO0ii <= (wire_n01iO0ii_o OR n01i101i); + niOliO0il <= (wire_niO01ill_w_lg_n01iOi1l17003w(0) AND (wire_niO01ill_w_lg_n01iOi0i17011w(0) AND wire_w_lg_niOliO0ll17001w(0))); + niOliO0iO <= ((n01iOi1i AND n01iO0OO) AND n01i1OOl); + niOliO0li <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOliO0ll <= ((wire_niO01ill_w_lg_n01iOi1i17538w(0) AND n01iO0OO) AND n01i1OOl); + niOliO0lO <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOliO0Oi <= (wire_niO01ill_w_lg_n1101l1O16997w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOliO0Ol <= (wire_niO01ill_w_lg_n1101l1O16997w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOliO0OO <= (n000i1ll OR (NOT (n111i10i OR n01l000i))); + niOliO10i <= ((wire_niO01ill_w_lg_w_lg_n01i110l17142w17560w(0) AND wire_niO01ill_w_lg_n01i111O17135w(0)) AND wire_niO01ill_w_lg_n01i111l17137w(0)); + niOliO10l <= ((wire_niO01ill_w_lg_w_lg_n01i110l17142w17560w(0) AND wire_niO01ill_w_lg_n01i111O17135w(0)) AND n01i111l); + niOliO10O <= (wire_niO01ill_w_lg_w_lg_w_lg_n01i110l17142w17560w17564w(0) AND wire_niO01ill_w_lg_n01i111l17137w(0)); + niOliO11i <= (n1l0001i AND (wire_n01iilll_o AND niOliO1OO)); + niOliO11l <= (n1l0001i AND niOliO00l); + niOliO11O <= wire_niO01ill_w_lg_w_lg_n01i110l17142w17143w(0); + niOliO1ii <= (wire_niO01ill_w_lg_w_lg_w_lg_n01i110l17142w17560w17564w(0) AND n01i111l); + niOliO1il <= ((wire_niO01ill_w_lg_n01i110l17567w(0) AND wire_niO01ill_w_lg_n01i111O17135w(0)) AND wire_niO01ill_w_lg_n01i111l17137w(0)); + niOliO1iO <= ((wire_niO01ill_w_lg_n01i110l17567w(0) AND wire_niO01ill_w_lg_n01i111O17135w(0)) AND n01i111l); + niOliO1li <= (wire_niO01ill_w_lg_n01i110l17567w(0) AND n01i111O); + niOliO1ll <= (n01i110l AND n01i110i); + niOliO1lO <= (wire_niO01ill_w_lg_n01i11ll17080w(0) AND wire_n010OO1i_dataout); + niOliO1Oi <= (n01i11ll AND wire_n010OO1i_dataout); + niOliO1Ol <= (wire_niO01ill_w_lg_nlOllOliO17066w(0) AND niOliO1OO); + niOliO1OO <= (n01iOi0i AND n01iOi1O); + niOliOi0i <= (((wire_niO10ill_w_lg_w16687w16688w(0) AND wire_niO10i0l_w_lg_dataout16689w(0)) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_dataout); + niOliOi0l <= (((wire_niO10ill_w_lg_w_lg_w16706w16707w16708w(0) AND wire_niO10i0l_w_lg_dataout16689w(0)) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_dataout); + niOliOi0O <= (wire_niO01ill_w_lg_n01O110l16853w(0) AND wire_niO01ill_w_lg_n01O110i16854w(0)); + niOliOi1i <= (((wire_niO01ill_w_lg_w_lg_w16942w16943w16944w(0) AND wire_niO01ill_w_lg_n000i1Oi16933w(0)) AND wire_niO01ill_w_lg_n000i1lO16935w(0)) AND n000i1ll); + niOliOi1l <= (((wire_niO01ill_w_lg_w16931w16932w(0) AND wire_niO01ill_w_lg_n000i1Oi16933w(0)) AND wire_niO01ill_w_lg_n000i1lO16935w(0)) AND n000i1ll); + niOliOi1O <= (wire_niO10i1O_dataout OR n111i10l); + niOliOiii <= (n01O110l AND n01O110i); + niOliOiil <= (wire_niO01ill_w_lg_n0010ilO16620w(0) OR wire_w_lg_w_lg_niOll110l16345w16621w(0)); + niOliOiiO <= (niOliOO1O AND niOliOill); + niOliOili <= (niOliOiOi AND wire_w_lg_niOliOill16582w(0)); + niOliOill <= (((wire_niO01iOi_w_lg_n01O1ili16846w(0) AND wire_niO01iOi_w_lg_n01O1iiO16847w(0)) AND wire_niO01iOi_w_lg_n01O1iil16849w(0)) AND wire_niO01iOi_w_lg_n01O1iii16851w(0)); + niOliOilO <= (((wire_niO10ill_w_lg_w16841w16842w(0) AND wire_niO10i0l_w_lg_dataout16689w(0)) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_dataout); + niOliOiOi <= (wire_niO10i1l_dataout AND niOliOilO); + niOliOiOl <= ((n01OllOO AND niOliOl1O) AND wire_w_lg_niOliOiOO16540w(0)); + niOliOiOO <= (((((((n01O01il AND n01O01ii) AND n01O010O) AND n01O010l) AND n01O010i) AND n01O011O) AND n01O011l) AND n01O011i); + niOliOl0i <= ((((((((NOT (n01OlOiO XOR n01O001i)) AND (NOT (n01OlOli XOR n01O001l))) AND (NOT (n01OlOll XOR n01O001O))) AND (NOT (n01OlOlO XOR n01O000i))) AND (NOT (n01OlOOi XOR n01O000l))) AND (NOT (n01OlOOl XOR n01O000O))) AND (NOT (n01OlOOO XOR n01O00ii))) AND (NOT (n01OO11i XOR n01O00il))); + niOliOl0l <= ((((((((NOT (n01OO1ll XOR n01O0i1O)) AND (NOT (n01OO1lO XOR n01O0i0i))) AND (NOT (n01OO1Oi XOR n01O0i0l))) AND (NOT (n01OO1Ol XOR n01O0i0O))) AND (NOT (n01OO1OO XOR n01O0iii))) AND (NOT (n01OO01i XOR n01O0iil))) AND (NOT (n01OO01l XOR n01O0iiO))) AND (NOT (n01OO01O XOR n01O0ili))); + niOliOl0O <= (((((NOT (n01OO10l XOR n01O00lO)) AND (NOT (n01OO10O XOR n01O00Oi))) AND (NOT (n01OO1ii XOR n01O00Ol))) AND (NOT (n01OO1il XOR n01O00OO))) AND (NOT (n01OO1iO XOR n01O0i1i))); + niOliOl1i <= (n01OllOO AND wire_w_lg_niOliOl1O16537w(0)); + niOliOl1l <= (n01OllOl OR (niOlO1O0i OR n01OlO1i)); + niOliOl1O <= ((((((wire_niO01ill_w_lg_w_lg_w16497w16500w16501w(0) AND ((((NOT (n01OlO0l XOR n01O01lO)) AND (NOT (n01OlO0O XOR n01O01Oi))) AND (NOT (n01OlOii XOR n01O01Ol))) AND (NOT (n01OlOil XOR n01O01OO)))) AND (((NOT (n01OO11l XOR n01O00iO)) AND (NOT (n01OO11O XOR n01O00li))) AND (NOT (n01OO10i XOR n01O00ll)))) AND (NOT (n01OlO1O XOR n01O01li))) AND (NOT (n01OlO1l XOR n01O01iO))) AND (NOT (n01OlO0i XOR n01O01ll))) AND (NOT (n01OllOi XOR n01O1OOi))); + niOliOlii <= (n0010l1O AND niOliOiOi); + niOliOlil <= (wire_niO01iOi_w_lg_w_lg_n01OO0il16458w16771w(0) AND wire_niO01iOi_w_lg_n01OO00l16766w(0)); + niOliOliO <= (wire_niO01iOi_w_lg_w_lg_n01OO0il16458w16771w(0) AND n01OO00l); + niOliOlli <= (((n01OO0il AND n01OO0ii) AND wire_niO01iOi_w_lg_n01OO00O16459w(0)) AND wire_niO01iOi_w_lg_n01OO00l16766w(0)); + niOliOlll <= (((n01OO0il AND n01OO0ii) AND n01OO00O) AND n01OO00l); + niOliOllO <= ((niOliOOOi OR niOliOlOl) OR (niOliOOOl AND niOliOlOi)); + niOliOlOi <= (((n01OO0il AND n01OO0ii) AND wire_niO01iOi_w_lg_n01OO00O16459w(0)) AND n01OO00l); + niOliOlOl <= (((wire_niO01iOi_w_lg_n01OO0il16763w(0) AND wire_niO01iOi_w_lg_n01OO0ii16457w(0)) AND wire_niO01iOi_w_lg_n01OO00O16459w(0)) AND wire_niO01iOi_w_lg_n01OO00l16766w(0)); + niOliOlOO <= (wire_niO10i1l_dataout AND (niOliOO1l OR niOliOO1i)); + niOliOO0i <= ((wire_niO10ill_w_lg_w_lg_w_lg_w16749w16750w16751w16752w(0) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_w_lg_dataout16339w(0)); + niOliOO0l <= (wire_niO10ill_w_lg_w_lg_w_lg_w16742w16743w16744w16745w(0) AND wire_niO10i1O_w_lg_dataout16339w(0)); + niOliOO0O <= (n0010l1O AND (niOliOOOl OR niOliOOOi)); + niOliOO1i <= (wire_niO10ill_w16758w(0) AND wire_niO10i1O_w_lg_dataout16339w(0)); + niOliOO1l <= ((wire_niO10ill_w_lg_w_lg_w16687w16738w16739w(0) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_w_lg_dataout16339w(0)); + niOliOO1O <= (wire_niO10i1l_dataout AND (niOliOO0l OR niOliOO0i)); + niOliOOii <= (niOlO1O0i OR (NOT (wire_niO10i1l_dataout AND niOliOOil))); + niOliOOil <= ((((((((wire_niO10i1O_w_lg_dataout16339w(0) AND wire_n01liill_w_lg_dataout16721w(0)) AND wire_n01liiiO_w_lg_dataout16723w(0)) AND wire_n01liiii_w_lg_dataout16725w(0)) AND wire_n01lii0l_w_lg_dataout16727w(0)) AND wire_n01lii1O_w_lg_dataout16729w(0)) AND wire_n01li0OO_w_lg_dataout16731w(0)) AND wire_n01li0Oi_w_lg_dataout16733w(0)) AND wire_n01li0li_w_lg_dataout16735w(0)); + niOliOOiO <= (n0010l1i AND n0010iOl); + niOliOOli <= (niOll111O AND (wire_niO01ill_w_lg_n0010iOO16387w(0) AND niOliOOiO)); + niOliOOll <= (niOll111O AND (n0010iOO AND (n0010l1i AND wire_niO01ill_w_lg_n0010iOl16382w(0)))); + niOliOOlO <= (niOll111O AND n0010iOi); + niOliOOOi <= (wire_niO10i1O_w_lg_dataout16339w(0) AND wire_niO10i1l_dataout); + niOliOOOl <= (wire_niO10i1l_dataout AND niOliOOOO); + niOliOOOO <= (((((wire_niO10ill_w_lg_w_lg_w_lg_dataout16712w16713w16714w(0) AND wire_niO10iii_w_lg_dataout16715w(0)) AND wire_niO10i0O_dataout) AND wire_niO10i0l_dataout) AND wire_niO10i0i_dataout) AND wire_niO10i1O_dataout); + niOll000i <= (wire_niO1001l_dataout AND niOll000l); + niOll000l <= (((wire_niO100ll_w_lg_w15780w15781w(0) AND wire_niO1000l_w_lg_dataout15782w(0)) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_dataout); + niOll000O <= (((wire_niO101Ol_w_lg_dataout15390w(0) AND wire_niO101lO_w_lg_dataout15391w(0)) OR wire_niO101Ol_w_lg_w_lg_dataout15393w15394w(0)) AND wire_w_lg_niOll00ii15396w(0)); + niOll001i <= (((wire_niO100ll_w_lg_w_lg_w15799w15800w15801w(0) AND wire_niO1000l_w_lg_dataout15782w(0)) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_dataout); + niOll001l <= (wire_niO1001l_dataout AND niOll001O); + niOll001O <= (((wire_niO100ll_w_lg_w_lg_w15790w15791w15792w(0) AND wire_niO1000l_w_lg_dataout15782w(0)) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_dataout); + niOll00ii <= ((((((n00lOlli AND n00lOliO) AND n00lOlil) AND n00lOlii) AND n00lOl0O) AND n00lOl0l) AND n00lO0il); + niOll00il <= ((wire_niO01ill_w_lg_n00OOlli15189w(0) AND wire_w_lg_niOll0lii15192w(0)) OR wire_niO01ill_w_lg_n00iiiOi15387w(0)); + niOll00iO <= (((NOT (wire_niili1Ol_dataout XOR n00O1i0O)) AND (NOT (wire_niili1OO_dataout XOR n00O1iii))) AND (NOT (n1101l1i XOR n00O1iil))); + niOll00li <= ((wire_niO01ill_w_lg_n00OOlli15189w(0) AND (wire_niO01ill_w_lg_n00OOllO15197w(0) AND wire_w_lg_niOll0lii15192w(0))) OR wire_niO01ill_w_lg_n00O1i1l15259w(0)); + niOll00ll <= (wire_niO01ill_w_lg_n00O10lO15759w(0) AND wire_niO01ill_w_lg_n00O10li15323w(0)); + niOll00lO <= (wire_niO01ill_w_lg_n00O10lO15759w(0) AND n00O10li); + niOll00Oi <= (niOll0iOi AND wire_n00OiOOO_o); + niOll00Ol <= (n1l0001i AND (wire_n00Ol10i_o AND niOll0iOi)); + niOll00OO <= (n1l0001i AND niOll0l1O); + niOll010i <= (wire_niO100ll_w_lg_w_lg_w_lg_w15835w15836w15837w15838w(0) AND wire_niO1001O_w_lg_dataout15432w(0)); + niOll010l <= (n00lO0ii AND (niOll01Oi OR niOll01lO)); + niOll010O <= (niOlO1O0i OR (NOT (wire_niO1001l_dataout AND niOll01ii))); + niOll011i <= ((wire_niO100ll_w_lg_w_lg_w15780w15831w15832w(0) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_w_lg_dataout15432w(0)); + niOll011l <= (wire_niO1001l_dataout AND (niOll010i OR niOll011O)); + niOll011O <= ((wire_niO100ll_w_lg_w_lg_w_lg_w15842w15843w15844w15845w(0) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_w_lg_dataout15432w(0)); + niOll01ii <= ((((((((wire_niO1001O_w_lg_dataout15432w(0) AND wire_n00i11OO_w_lg_dataout15814w(0)) AND wire_n00i11Oi_w_lg_dataout15816w(0)) AND wire_n00i11ll_w_lg_dataout15818w(0)) AND wire_n00i11iO_w_lg_dataout15820w(0)) AND wire_n00i11ii_w_lg_dataout15822w(0)) AND wire_n00i110i_w_lg_dataout15824w(0)) AND wire_n00i111l_w_lg_dataout15826w(0)) AND wire_n000OOOl_w_lg_dataout15828w(0)); + niOll01il <= (n00lO00l AND n00lO01O); + niOll01iO <= (niOll001l AND (wire_niO01ill_w_lg_n00lO00i15480w(0) AND niOll01il)); + niOll01li <= (niOll001l AND (n00lO00i AND (n00lO00l AND wire_niO01ill_w_lg_n00lO01O15475w(0)))); + niOll01ll <= (niOll001l AND n00lO01l); + niOll01lO <= (wire_niO1001O_w_lg_dataout15432w(0) AND wire_niO1001l_dataout); + niOll01Oi <= (wire_niO1001l_dataout AND niOll01Ol); + niOll01Ol <= (((((wire_niO100ll_w_lg_w_lg_w_lg_dataout15805w15806w15807w(0) AND wire_niO100ii_w_lg_dataout15808w(0)) AND wire_niO1000O_dataout) AND wire_niO1000l_dataout) AND wire_niO1000i_dataout) AND wire_niO1001O_dataout); + niOll01OO <= (wire_niO1001l_dataout AND niOll001i); + niOll0i0i <= (wire_niO01ill_w_lg_w_lg_w_lg_n00O10Oi15328w15746w15750w(0) AND wire_niO01ill_w_lg_n00O10li15323w(0)); + niOll0i0l <= (wire_niO01ill_w_lg_w_lg_w_lg_n00O10Oi15328w15746w15750w(0) AND n00O10li); + niOll0i0O <= ((wire_niO01ill_w_lg_n00O10Oi15753w(0) AND wire_niO01ill_w_lg_n00O10ll15321w(0)) AND wire_niO01ill_w_lg_n00O10li15323w(0)); + niOll0i1i <= wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15329w(0); + niOll0i1l <= ((wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15746w(0) AND wire_niO01ill_w_lg_n00O10ll15321w(0)) AND wire_niO01ill_w_lg_n00O10li15323w(0)); + niOll0i1O <= ((wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15746w(0) AND wire_niO01ill_w_lg_n00O10ll15321w(0)) AND n00O10li); + niOll0iii <= ((wire_niO01ill_w_lg_n00O10Oi15753w(0) AND wire_niO01ill_w_lg_n00O10ll15321w(0)) AND n00O10li); + niOll0iil <= (wire_niO01ill_w_lg_n00O10Oi15753w(0) AND n00O10ll); + niOll0iiO <= (n00O10Oi AND n00O10lO); + niOll0ili <= (wire_niO01ill_w_lg_n00O1i0i15266w(0) AND wire_n00O11iO_dataout); + niOll0ill <= (n00O1i0i AND wire_n00O11iO_dataout); + niOll0ilO <= (wire_niO01ill_w_lg_nlOllOlll15252w(0) AND niOll0iOi); + niOll0iOi <= (n00OOllO AND n00OOlll); + niOll0iOl <= (wire_niO01ill_w_lg_w_lg_w_lg_n00O1iiO15258w15260w15261w(0) OR (n11O0O0l AND nlOllOlll)); + niOll0iOO <= (n00OOlOl OR (n00OOllO AND niOll0l1i)); + niOll0l0i <= (wire_niO01ill_w_lg_nlOllOlll15252w(0) AND n00OOlli); + niOll0l0l <= (wire_n00OOiOO_o OR n00O1iiO); + niOll0l0O <= (wire_niO01ill_w_lg_n00OOlli15189w(0) AND (wire_niO01ill_w_lg_n00OOllO15197w(0) AND wire_w_lg_niOll0liO15187w(0))); + niOll0l1i <= ((((((NOT (wire_n0i11l0l_dataout XOR n00O1i1O)) AND (NOT (wire_n0i11l0O_dataout XOR n00O1i0i))) AND (NOT (wire_n0i11lii_dataout XOR n00O1i0l))) AND (NOT (wire_n0i11lil_dataout XOR n00O1i0O))) AND (NOT (wire_n0i11liO_dataout XOR n00O1iii))) AND (NOT (wire_n0i11lli_dataout XOR n00O1iil))); + niOll0l1l <= (wire_niO01ill_w_lg_nlOllOlll15252w(0) AND (niOll0l1O OR wire_n00O11ll_dataout)); + niOll0l1O <= (n00OOllO AND wire_niO01ill_w_lg_n00OOlll15268w(0)); + niOll0lii <= ((n00OOliO AND n00OOlil) AND n00O00ii); + niOll0lil <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOll0liO <= ((wire_niO01ill_w_lg_n00OOliO15724w(0) AND n00OOlil) AND n00O00ii); + niOll0lli <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOll0lll <= (wire_niO01ill_w_lg_n1101l0l15183w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOll0llO <= (wire_niO01ill_w_lg_n1101l0l15183w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOll0lOi <= (n0ilii0i OR (NOT (n111i10i OR n0i10ilO))); + niOll0lOl <= (((wire_niO01ill_w_lg_w_lg_w15128w15129w15130w(0) AND wire_niO01ill_w_lg_n0ilii0O15119w(0)) AND wire_niO01ill_w_lg_n0ilii0l15121w(0)) AND n0ilii0i); + niOll0lOO <= (((wire_niO01ill_w_lg_w15117w15118w(0) AND wire_niO01ill_w_lg_n0ilii0O15119w(0)) AND wire_niO01ill_w_lg_n0ilii0l15121w(0)) AND n0ilii0i); + niOll0O0i <= (wire_niO01ill_w_lg_n0i010Oi15039w(0) AND wire_niO01ill_w_lg_n0i010lO15040w(0)); + niOll0O0l <= (n0i010Oi AND n0i010lO); + niOll0O0O <= (wire_niO01ill_w_lg_n0ii0O0l14806w(0) OR wire_w_lg_w_lg_niOllii1O14531w14807w(0)); + niOll0O1i <= (wire_niO1011O_dataout OR n111i10l); + niOll0O1l <= (((wire_niO101ll_w_lg_w14873w14874w(0) AND wire_niO1010l_w_lg_dataout14875w(0)) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_dataout); + niOll0O1O <= (((wire_niO101ll_w_lg_w_lg_w14892w14893w14894w(0) AND wire_niO1010l_w_lg_dataout14875w(0)) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_dataout); + niOll0Oii <= (niOlli01i AND niOll0OiO); + niOll0Oil <= (niOll0Oll AND wire_w_lg_niOll0OiO14768w(0)); + niOll0OiO <= (((wire_niO01iOi_w_lg_n0i01O1O15032w(0) AND wire_niO01iOi_w_lg_n0i01O1l15033w(0)) AND wire_niO01iOi_w_lg_n0i01O1i15035w(0)) AND wire_niO01iOi_w_lg_n0i01lOO15037w(0)); + niOll0Oli <= (((wire_niO101ll_w_lg_w15027w15028w(0) AND wire_niO1010l_w_lg_dataout14875w(0)) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_dataout); + niOll0Oll <= (wire_niO1011l_dataout AND niOll0Oli); + niOll0OlO <= ((n0i0O1il AND niOlli11i) AND wire_w_lg_niOll0OOi14726w(0)); + niOll0OOi <= (((((((n0i00i1i AND n0i000OO) AND n0i000Ol) AND n0i000Oi) AND n0i000lO) AND n0i000ll) AND n0i000li) AND n0i000iO); + niOll0OOl <= (n0i0O1il AND wire_w_lg_niOlli11i14723w(0)); + niOll0OOO <= (n0i0O1ii OR (niOlO1O0i OR n0i0O1iO)); + niOll100i <= ((wire_niO01ill_w_lg_w_lg_n001iliO16235w16653w(0) AND wire_niO01ill_w_lg_n001ilii16228w(0)) AND n001il0O); + niOll100l <= (wire_niO01ill_w_lg_w_lg_w_lg_n001iliO16235w16653w16657w(0) AND wire_niO01ill_w_lg_n001il0O16230w(0)); + niOll100O <= (wire_niO01ill_w_lg_w_lg_w_lg_n001iliO16235w16653w16657w(0) AND n001il0O); + niOll101i <= (n1l0001i AND niOll1i0i); + niOll101l <= wire_niO01ill_w_lg_w_lg_n001iliO16235w16236w(0); + niOll101O <= ((wire_niO01ill_w_lg_w_lg_n001iliO16235w16653w(0) AND wire_niO01ill_w_lg_n001ilii16228w(0)) AND wire_niO01ill_w_lg_n001il0O16230w(0)); + niOll10ii <= ((wire_niO01ill_w_lg_n001iliO16660w(0) AND wire_niO01ill_w_lg_n001ilii16228w(0)) AND wire_niO01ill_w_lg_n001il0O16230w(0)); + niOll10il <= ((wire_niO01ill_w_lg_n001iliO16660w(0) AND wire_niO01ill_w_lg_n001ilii16228w(0)) AND n001il0O); + niOll10iO <= (wire_niO01ill_w_lg_n001iliO16660w(0) AND n001ilii); + niOll10li <= (n001iliO AND n001ilil); + niOll10ll <= (wire_niO01ill_w_lg_n001ilOO16173w(0) AND wire_n001ii0l_dataout); + niOll10lO <= (n001ilOO AND wire_n001ii0l_dataout); + niOll10Oi <= (wire_niO01ill_w_lg_nlOllOlli16159w(0) AND niOll10Ol); + niOll10Ol <= (n000i1il AND n000i1ii); + niOll10OO <= (wire_niO01ill_w_lg_w_lg_w_lg_n001iO0l16165w16167w16168w(0) OR (n11O0O0l AND nlOllOlli)); + niOll110i <= (((wire_niO10ill_w_lg_w_lg_w16697w16698w16699w(0) AND wire_niO10i0l_w_lg_dataout16689w(0)) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_dataout); + niOll110l <= (wire_niO10i1l_dataout AND niOll110O); + niOll110O <= (((wire_niO10ill_w_lg_w16687w16688w(0) AND wire_niO10i0l_w_lg_dataout16689w(0)) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_dataout); + niOll111i <= (wire_niO10i1l_dataout AND niOll111l); + niOll111l <= (((wire_niO10ill_w_lg_w_lg_w16706w16707w16708w(0) AND wire_niO10i0l_w_lg_dataout16689w(0)) AND wire_niO10i0i_w_lg_dataout16691w(0)) AND wire_niO10i1O_dataout); + niOll111O <= (wire_niO10i1l_dataout AND niOll110i); + niOll11ii <= (((wire_niO100Ol_w_lg_dataout16297w(0) AND wire_niO100lO_w_lg_dataout16298w(0)) OR wire_niO100Ol_w_lg_w_lg_dataout16300w16301w(0)) AND wire_w_lg_niOll11il16303w(0)); + niOll11il <= ((((((n001i10O AND n001i10l) AND n001i10i) AND n001i11O) AND n001i11l) AND n001i11i) AND n0010l0i); + niOll11iO <= ((wire_niO01ill_w_lg_n000i10O16096w(0) AND wire_w_lg_niOll1iil16099w(0)) OR wire_niO01ill_w_lg_n01lOOiO16294w(0)); + niOll11li <= (((NOT (wire_niili01i_dataout XOR n001iO1l)) AND (NOT (wire_niili01l_dataout XOR n001iO1O))) AND (NOT (n1101l1i XOR n001iO0i))); + niOll11ll <= ((wire_niO01ill_w_lg_n000i10O16096w(0) AND (wire_niO01ill_w_lg_n000i1il16104w(0) AND wire_w_lg_niOll1iil16099w(0))) OR wire_niO01ill_w_lg_n001ilOi16166w(0)); + niOll11lO <= (wire_niO01ill_w_lg_n001ilil16666w(0) AND wire_niO01ill_w_lg_n001il0O16230w(0)); + niOll11Oi <= (wire_niO01ill_w_lg_n001ilil16666w(0) AND n001il0O); + niOll11Ol <= (niOll10Ol AND wire_n00010ll_o); + niOll11OO <= (n1l0001i AND (wire_n00010OO_o AND niOll10Ol)); + niOll1i0i <= (n000i1il AND wire_niO01ill_w_lg_n000i1ii16175w(0)); + niOll1i0l <= (wire_niO01ill_w_lg_nlOllOlli16159w(0) AND n000i10O); + niOll1i0O <= (wire_n0000Oll_o OR n001iO0l); + niOll1i1i <= (n000i1li OR (n000i1il AND niOll1i1l)); + niOll1i1l <= ((((((NOT (wire_n000l11i_dataout XOR n001ilOl)) AND (NOT (wire_n000l11l_dataout XOR n001ilOO))) AND (NOT (wire_n000l11O_dataout XOR n001iO1i))) AND (NOT (wire_n000l10i_dataout XOR n001iO1l))) AND (NOT (wire_n000l10l_dataout XOR n001iO1O))) AND (NOT (wire_n000l10O_dataout XOR n001iO0i))); + niOll1i1O <= (wire_niO01ill_w_lg_nlOllOlli16159w(0) AND (niOll1i0i OR wire_n001iiii_dataout)); + niOll1iii <= (wire_niO01ill_w_lg_n000i10O16096w(0) AND (wire_niO01ill_w_lg_n000i1il16104w(0) AND wire_w_lg_niOll1ili16094w(0))); + niOll1iil <= ((n000i10l AND n000i10i) AND n001ll1O); + niOll1iiO <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOll1ili <= ((wire_niO01ill_w_lg_n000i10l16631w(0) AND n000i10i) AND n001ll1O); + niOll1ill <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOll1ilO <= (wire_niO01ill_w_lg_n1101l0i16090w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOll1iOi <= (wire_niO01ill_w_lg_n1101l0i16090w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOll1iOl <= (n00OOlOO OR (NOT (n111i10i OR n000lOil))); + niOll1iOO <= (((wire_niO01ill_w_lg_w_lg_w16035w16036w16037w(0) AND wire_niO01ill_w_lg_n00OOO1l16026w(0)) AND wire_niO01ill_w_lg_n00OOO1i16028w(0)) AND n00OOlOO); + niOll1l0i <= (((wire_niO100ll_w_lg_w_lg_w15799w15800w15801w(0) AND wire_niO1000l_w_lg_dataout15782w(0)) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_dataout); + niOll1l0l <= (wire_niO01ill_w_lg_n00iiliO15946w(0) AND wire_niO01ill_w_lg_n00iilil15947w(0)); + niOll1l0O <= (n00iiliO AND n00iilil); + niOll1l1i <= (((wire_niO01ill_w_lg_w16024w16025w(0) AND wire_niO01ill_w_lg_n00OOO1l16026w(0)) AND wire_niO01ill_w_lg_n00OOO1i16028w(0)) AND n00OOlOO); + niOll1l1l <= (wire_niO1001O_dataout OR n111i10l); + niOll1l1O <= (((wire_niO100ll_w_lg_w15780w15781w(0) AND wire_niO1000l_w_lg_dataout15782w(0)) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_dataout); + niOll1lii <= (wire_niO01ill_w_lg_n00lO01i15713w(0) OR wire_w_lg_w_lg_niOll000i15438w15714w(0)); + niOll1lil <= (niOll011l AND niOll1lli); + niOll1liO <= (niOll1llO AND wire_w_lg_niOll1lli15675w(0)); + niOll1lli <= (((wire_niO01iOi_w_lg_n00il1Ol15939w(0) AND wire_niO01iOi_w_lg_n00il1Oi15940w(0)) AND wire_niO01iOi_w_lg_n00il1lO15942w(0)) AND wire_niO01iOi_w_lg_n00il1ll15944w(0)); + niOll1lll <= (((wire_niO100ll_w_lg_w15934w15935w(0) AND wire_niO1000l_w_lg_dataout15782w(0)) AND wire_niO1000i_w_lg_dataout15784w(0)) AND wire_niO1001O_dataout); + niOll1llO <= (wire_niO1001l_dataout AND niOll1lll); + niOll1lOi <= ((n00l0i0i AND niOll1O1l) AND wire_w_lg_niOll1lOl15633w(0)); + niOll1lOl <= (((((((n00illlO AND n00illll) AND n00illli) AND n00illiO) AND n00illil) AND n00illii) AND n00ill0O) AND n00ill0l); + niOll1lOO <= (n00l0i0i AND wire_w_lg_niOll1O1l15630w(0)); + niOll1O0i <= ((((((((NOT (n00l0lOO XOR n00iO1ii)) AND (NOT (n00l0O1i XOR n00iO1il))) AND (NOT (n00l0O1l XOR n00iO1iO))) AND (NOT (n00l0O1O XOR n00iO1li))) AND (NOT (n00l0O0i XOR n00iO1ll))) AND (NOT (n00l0O0l XOR n00iO1lO))) AND (NOT (n00l0O0O XOR n00iO1Oi))) AND (NOT (n00l0Oii XOR n00iO1Ol))); + niOll1O0l <= (((((NOT (n00l0liO XOR n00iO11i)) AND (NOT (n00l0lli XOR n00iO11l))) AND (NOT (n00l0lll XOR n00iO11O))) AND (NOT (n00l0llO XOR n00iO10i))) AND (NOT (n00l0lOi XOR n00iO10l))); + niOll1O0O <= (n00lO0ii AND niOll1llO); + niOll1O1i <= (n00l0i1O OR (niOlO1O0i OR n00l0i0l)); + niOll1O1l <= ((((((wire_niO01ill_w_lg_w_lg_w15590w15593w15594w(0) AND ((((NOT (n00l0iiO XOR n00ilO1i)) AND (NOT (n00l0ili XOR n00ilO1l))) AND (NOT (n00l0ill XOR n00ilO1O))) AND (NOT (n00l0ilO XOR n00ilO0i)))) AND (((NOT (n00l0l0O XOR n00ilOOi)) AND (NOT (n00l0lii XOR n00ilOOl))) AND (NOT (n00l0lil XOR n00ilOOO)))) AND (NOT (n00l0iii XOR n00illOl))) AND (NOT (n00l0i0O XOR n00illOi))) AND (NOT (n00l0iil XOR n00illOO))) AND (NOT (n00l0i1l XOR n00ill1l))); + niOll1O1O <= ((((((((NOT (n00l0iOi XOR n00ilO0l)) AND (NOT (n00l0iOl XOR n00ilO0O))) AND (NOT (n00l0iOO XOR n00ilOii))) AND (NOT (n00l0l1i XOR n00ilOil))) AND (NOT (n00l0l1l XOR n00ilOiO))) AND (NOT (n00l0l1O XOR n00ilOli))) AND (NOT (n00l0l0i XOR n00ilOll))) AND (NOT (n00l0l0l XOR n00ilOlO))); + niOll1Oii <= (wire_niO01iOi_w_lg_w_lg_n00l0OlO15551w15864w(0) AND wire_niO01iOi_w_lg_n00l0OiO15859w(0)); + niOll1Oil <= (wire_niO01iOi_w_lg_w_lg_n00l0OlO15551w15864w(0) AND n00l0OiO); + niOll1OiO <= (((n00l0OlO AND n00l0Oll) AND wire_niO01iOi_w_lg_n00l0Oli15552w(0)) AND wire_niO01iOi_w_lg_n00l0OiO15859w(0)); + niOll1Oli <= (((n00l0OlO AND n00l0Oll) AND n00l0Oli) AND n00l0OiO); + niOll1Oll <= ((niOll01lO OR niOll1OOi) OR (niOll01Oi AND niOll1OlO)); + niOll1OlO <= (((n00l0OlO AND n00l0Oll) AND wire_niO01iOi_w_lg_n00l0Oli15552w(0)) AND n00l0OiO); + niOll1OOi <= (((wire_niO01iOi_w_lg_n00l0OlO15856w(0) AND wire_niO01iOi_w_lg_n00l0Oll15550w(0)) AND wire_niO01iOi_w_lg_n00l0Oli15552w(0)) AND wire_niO01iOi_w_lg_n00l0OiO15859w(0)); + niOll1OOl <= (wire_niO1001l_dataout AND (niOll011i OR niOll1OOO)); + niOll1OOO <= (wire_niO100ll_w15851w(0) AND wire_niO1001O_w_lg_dataout15432w(0)); + niOlli00i <= (n0ii0Oll AND (niOlli0lO OR niOlli0ll)); + niOlli00l <= (niOlO1O0i OR (NOT (wire_niO1011l_dataout AND niOlli00O))); + niOlli00O <= ((((((((wire_niO1011O_w_lg_dataout14525w(0) AND wire_n0i1iO0i_w_lg_dataout14907w(0)) AND wire_n0i1iO1l_w_lg_dataout14909w(0)) AND wire_n0i1ilOO_w_lg_dataout14911w(0)) AND wire_n0i1ilOi_w_lg_dataout14913w(0)) AND wire_n0i1illl_w_lg_dataout14915w(0)) AND wire_n0i1ilil_w_lg_dataout14917w(0)) AND wire_n0i1il0O_w_lg_dataout14919w(0)) AND wire_n0i1il1O_w_lg_dataout14921w(0)); + niOlli01i <= (wire_niO1011l_dataout AND (niOlli01O OR niOlli01l)); + niOlli01l <= ((wire_niO101ll_w_lg_w_lg_w_lg_w14935w14936w14937w14938w(0) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_w_lg_dataout14525w(0)); + niOlli01O <= (wire_niO101ll_w_lg_w_lg_w_lg_w14928w14929w14930w14931w(0) AND wire_niO1011O_w_lg_dataout14525w(0)); + niOlli0ii <= (n0ii0OiO AND n0ii0Oii); + niOlli0il <= (niOllii1i AND (wire_niO01ill_w_lg_n0ii0Oil14573w(0) AND niOlli0ii)); + niOlli0iO <= (niOllii1i AND (n0ii0Oil AND (n0ii0OiO AND wire_niO01ill_w_lg_n0ii0Oii14568w(0)))); + niOlli0li <= (niOllii1i AND n0ii0O0O); + niOlli0ll <= (wire_niO1011O_w_lg_dataout14525w(0) AND wire_niO1011l_dataout); + niOlli0lO <= (wire_niO1011l_dataout AND niOlli0Oi); + niOlli0Oi <= (((((wire_niO101ll_w_lg_w_lg_w_lg_dataout14898w14899w14900w(0) AND wire_niO101ii_w_lg_dataout14901w(0)) AND wire_niO1010O_dataout) AND wire_niO1010l_dataout) AND wire_niO1010i_dataout) AND wire_niO1011O_dataout); + niOlli0Ol <= (wire_niO1011l_dataout AND niOlli0OO); + niOlli0OO <= (((wire_niO101ll_w_lg_w_lg_w14892w14893w14894w(0) AND wire_niO1010l_w_lg_dataout14875w(0)) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_dataout); + niOlli10i <= (((((NOT (n0i0O0Oi XOR n0i00l0l)) AND (NOT (n0i0O0Ol XOR n0i00l0O))) AND (NOT (n0i0O0OO XOR n0i00lii))) AND (NOT (n0i0Oi1i XOR n0i00lil))) AND (NOT (n0i0Oi1l XOR n0i00liO))); + niOlli10l <= (n0ii0Oll AND niOll0Oll); + niOlli10O <= (wire_niO01iOi_w_lg_w_lg_n0i0Ol1i14644w14957w(0) AND wire_niO01iOi_w_lg_n0i0OiOi14952w(0)); + niOlli11i <= ((((((wire_niO01ill_w_lg_w_lg_w14683w14686w14687w(0) AND ((((NOT (n0i0O1Oi XOR n0i00i0l)) AND (NOT (n0i0O1Ol XOR n0i00i0O))) AND (NOT (n0i0O1OO XOR n0i00iii))) AND (NOT (n0i0O01i XOR n0i00iil)))) AND (((NOT (n0i0O0li XOR n0i00l1l)) AND (NOT (n0i0O0ll XOR n0i00l1O))) AND (NOT (n0i0O0lO XOR n0i00l0i)))) AND (NOT (n0i0O1ll XOR n0i00i1O))) AND (NOT (n0i0O1li XOR n0i00i1l))) AND (NOT (n0i0O1lO XOR n0i00i0i))) AND (NOT (n0i0O10O XOR n0i0000O))); + niOlli11l <= ((((((((NOT (n0i0O01l XOR n0i00iiO)) AND (NOT (n0i0O01O XOR n0i00ili))) AND (NOT (n0i0O00i XOR n0i00ill))) AND (NOT (n0i0O00l XOR n0i00ilO))) AND (NOT (n0i0O00O XOR n0i00iOi))) AND (NOT (n0i0O0ii XOR n0i00iOl))) AND (NOT (n0i0O0il XOR n0i00iOO))) AND (NOT (n0i0O0iO XOR n0i00l1i))); + niOlli11O <= ((((((((NOT (n0i0Oi0i XOR n0i00lll)) AND (NOT (n0i0Oi0l XOR n0i00llO))) AND (NOT (n0i0Oi0O XOR n0i00lOi))) AND (NOT (n0i0Oiii XOR n0i00lOl))) AND (NOT (n0i0Oiil XOR n0i00lOO))) AND (NOT (n0i0OiiO XOR n0i00O1i))) AND (NOT (n0i0Oili XOR n0i00O1l))) AND (NOT (n0i0Oill XOR n0i00O1O))); + niOlli1ii <= (wire_niO01iOi_w_lg_w_lg_n0i0Ol1i14644w14957w(0) AND n0i0OiOi); + niOlli1il <= (((n0i0Ol1i AND n0i0OiOO) AND wire_niO01iOi_w_lg_n0i0OiOl14645w(0)) AND wire_niO01iOi_w_lg_n0i0OiOi14952w(0)); + niOlli1iO <= (((n0i0Ol1i AND n0i0OiOO) AND n0i0OiOl) AND n0i0OiOi); + niOlli1li <= ((niOlli0ll OR niOlli1lO) OR (niOlli0lO AND niOlli1ll)); + niOlli1ll <= (((n0i0Ol1i AND n0i0OiOO) AND wire_niO01iOi_w_lg_n0i0OiOl14645w(0)) AND n0i0OiOi); + niOlli1lO <= (((wire_niO01iOi_w_lg_n0i0Ol1i14949w(0) AND wire_niO01iOi_w_lg_n0i0OiOO14643w(0)) AND wire_niO01iOi_w_lg_n0i0OiOl14645w(0)) AND wire_niO01iOi_w_lg_n0i0OiOi14952w(0)); + niOlli1Oi <= (wire_niO1011l_dataout AND (niOlli1OO OR niOlli1Ol)); + niOlli1Ol <= (wire_niO101ll_w14944w(0) AND wire_niO1011O_w_lg_dataout14525w(0)); + niOlli1OO <= ((wire_niO101ll_w_lg_w_lg_w14873w14924w14925w(0) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_w_lg_dataout14525w(0)); + niOllii0i <= (((wire_niO101ll_w_lg_w14873w14874w(0) AND wire_niO1010l_w_lg_dataout14875w(0)) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_dataout); + niOllii0l <= (((wire_niO11OOl_w_lg_dataout14483w(0) AND wire_niO11OlO_w_lg_dataout14484w(0)) OR wire_niO11OOl_w_lg_w_lg_dataout14486w14487w(0)) AND wire_w_lg_niOllii0O14489w(0)); + niOllii0O <= ((((((n0iii0Ol AND n0iii0Oi) AND n0iii0lO) AND n0iii0ll) AND n0iii0li) AND n0iii0iO) AND n0ii0OlO); + niOllii1i <= (wire_niO1011l_dataout AND niOllii1l); + niOllii1l <= (((wire_niO101ll_w_lg_w_lg_w14883w14884w14885w(0) AND wire_niO1010l_w_lg_dataout14875w(0)) AND wire_niO1010i_w_lg_dataout14877w(0)) AND wire_niO1011O_dataout); + niOllii1O <= (wire_niO1011l_dataout AND niOllii0i); + niOlliiii <= ((wire_niO01ill_w_lg_n0ili0Ol14282w(0) AND wire_w_lg_niOlliO0O14285w(0)) OR wire_niO01ill_w_lg_n0i0101l14480w(0)); + niOlliiil <= (((NOT (n1101l1i XOR n0iil1li)) AND (NOT (n1101l1i XOR n0iil1ll))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0iil1lO))); + niOlliiiO <= ((wire_niO01ill_w_lg_n0ili0Ol14282w(0) AND (wire_niO01ill_w_lg_n0ilii1i14290w(0) AND wire_w_lg_niOlliO0O14285w(0))) OR wire_niO01ill_w_lg_n0iil10O14352w(0)); + niOlliili <= (wire_niO01ill_w_lg_n0iil11i14852w(0) AND wire_niO01ill_w_lg_n0iiiOOl14416w(0)); + niOlliill <= (wire_niO01ill_w_lg_n0iil11i14852w(0) AND n0iiiOOl); + niOlliilO <= (niOllillO AND wire_n0il1l0i_o); + niOlliiOi <= (n1l0001i AND (wire_n0il1lil_o AND niOllillO)); + niOlliiOl <= (n1l0001i AND niOlliO1l); + niOlliiOO <= wire_niO01ill_w_lg_w_lg_n0iil11l14421w14422w(0); + niOllil0i <= (wire_niO01ill_w_lg_w_lg_w_lg_n0iil11l14421w14839w14843w(0) AND n0iiiOOl); + niOllil0l <= ((wire_niO01ill_w_lg_n0iil11l14846w(0) AND wire_niO01ill_w_lg_n0iiiOOO14414w(0)) AND wire_niO01ill_w_lg_n0iiiOOl14416w(0)); + niOllil0O <= ((wire_niO01ill_w_lg_n0iil11l14846w(0) AND wire_niO01ill_w_lg_n0iiiOOO14414w(0)) AND n0iiiOOl); + niOllil1i <= ((wire_niO01ill_w_lg_w_lg_n0iil11l14421w14839w(0) AND wire_niO01ill_w_lg_n0iiiOOO14414w(0)) AND wire_niO01ill_w_lg_n0iiiOOl14416w(0)); + niOllil1l <= ((wire_niO01ill_w_lg_w_lg_n0iil11l14421w14839w(0) AND wire_niO01ill_w_lg_n0iiiOOO14414w(0)) AND n0iiiOOl); + niOllil1O <= (wire_niO01ill_w_lg_w_lg_w_lg_n0iil11l14421w14839w14843w(0) AND wire_niO01ill_w_lg_n0iiiOOl14416w(0)); + niOllilii <= (wire_niO01ill_w_lg_n0iil11l14846w(0) AND n0iiiOOO); + niOllilil <= (n0iil11l AND n0iil11i); + niOlliliO <= (wire_niO01ill_w_lg_n0iil1il14359w(0) AND wire_n0iiilOi_dataout); + niOllilli <= (n0iil1il AND wire_n0iiilOi_dataout); + niOllilll <= (wire_niO01ill_w_lg_nlOllOllO14345w(0) AND niOllillO); + niOllillO <= (n0ilii1i AND n0ili0OO); + niOllilOi <= (wire_niO01ill_w_lg_w_lg_w_lg_n0iil1Oi14351w14353w14354w(0) OR (n11O0O0l AND nlOllOllO)); + niOllilOl <= (n0ilii1O OR (n0ilii1i AND niOllilOO)); + niOllilOO <= ((((((NOT (wire_n0ill0iO_dataout XOR n0iil1ii)) AND (NOT (wire_n0ill0li_dataout XOR n0iil1il))) AND (NOT (wire_n0ill0ll_dataout XOR n0iil1iO))) AND (NOT (wire_n0ill0lO_dataout XOR n0iil1li))) AND (NOT (wire_n0ill0Oi_dataout XOR n0iil1ll))) AND (NOT (wire_n0ill0Ol_dataout XOR n0iil1lO))); + niOlliO0i <= (wire_n0ili00i_o OR n0iil1Oi); + niOlliO0l <= (wire_niO01ill_w_lg_n0ili0Ol14282w(0) AND (wire_niO01ill_w_lg_n0ilii1i14290w(0) AND wire_w_lg_niOlliOil14280w(0))); + niOlliO0O <= ((n0ili0Oi AND n0ili0lO) AND n0iilOll); + niOlliO1i <= (wire_niO01ill_w_lg_nlOllOllO14345w(0) AND (niOlliO1l OR wire_n0iiilOO_dataout)); + niOlliO1l <= (n0ilii1i AND wire_niO01ill_w_lg_n0ili0OO14361w(0)); + niOlliO1O <= (wire_niO01ill_w_lg_nlOllOllO14345w(0) AND n0ili0Ol); + niOlliOii <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOlliOil <= ((wire_niO01ill_w_lg_n0ili0Oi14817w(0) AND n0ili0lO) AND n0iilOll); + niOlliOiO <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOlliOli <= (wire_niO01ill_w_lg_n1101l0O14276w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOlliOll <= (wire_niO01ill_w_lg_n1101l0O14276w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOlliOlO <= (n0li11il OR (NOT (n111i10i OR n0ilO01i))); + niOlliOOi <= (((wire_niO01ill_w_lg_w_lg_w14221w14222w14223w(0) AND wire_niO01ill_w_lg_n0li11li14212w(0)) AND wire_niO01ill_w_lg_n0li11iO14214w(0)) AND n0li11il); + niOlliOOl <= (((wire_niO01ill_w_lg_w14210w14211w(0) AND wire_niO01ill_w_lg_n0li11li14212w(0)) AND wire_niO01ill_w_lg_n0li11iO14214w(0)) AND n0li11il); + niOlliOOO <= (wire_niO11O1O_dataout OR n111i10l); + niOlll00i <= (n0l1OiOO AND niOlll1li); + niOlll00l <= (wire_niO01iOi_w_lg_w_lg_n0l1i00l13737w14050w(0) AND wire_niO01iOi_w_lg_n0l1i01l14045w(0)); + niOlll00O <= (wire_niO01iOi_w_lg_w_lg_n0l1i00l13737w14050w(0) AND n0l1i01l); + niOlll01i <= ((((((((NOT (n0l10O0O XOR n0iOO1Oi)) AND (NOT (n0l10Oii XOR n0iOO1Ol))) AND (NOT (n0l10Oil XOR n0iOO1OO))) AND (NOT (n0l10OiO XOR n0iOO01i))) AND (NOT (n0l10Oli XOR n0iOO01l))) AND (NOT (n0l10Oll XOR n0iOO01O))) AND (NOT (n0l10OlO XOR n0iOO00i))) AND (NOT (n0l10OOi XOR n0iOO00l))); + niOlll01l <= ((((((((NOT (n0l1i1il XOR n0iOO0OO)) AND (NOT (n0l1i1iO XOR n0iOOi1i))) AND (NOT (n0l1i1li XOR n0iOOi1l))) AND (NOT (n0l1i1ll XOR n0iOOi1O))) AND (NOT (n0l1i1lO XOR n0iOOi0i))) AND (NOT (n0l1i1Oi XOR n0iOOi0l))) AND (NOT (n0l1i1Ol XOR n0iOOi0O))) AND (NOT (n0l1i1OO XOR n0iOOiii))); + niOlll01O <= (((((NOT (n0l1i11l XOR n0iOO0iO)) AND (NOT (n0l1i11O XOR n0iOO0li))) AND (NOT (n0l1i10i XOR n0iOO0ll))) AND (NOT (n0l1i10l XOR n0iOO0lO))) AND (NOT (n0l1i10O XOR n0iOO0Oi))); + niOlll0ii <= (((n0l1i00l AND n0l1i00i) AND wire_niO01iOi_w_lg_n0l1i01O13738w(0)) AND wire_niO01iOi_w_lg_n0l1i01l14045w(0)); + niOlll0il <= (((n0l1i00l AND n0l1i00i) AND n0l1i01O) AND n0l1i01l); + niOlll0iO <= ((niOlllili OR niOlll0ll) OR (niOlllill AND niOlll0li)); + niOlll0li <= (((n0l1i00l AND n0l1i00i) AND wire_niO01iOi_w_lg_n0l1i01O13738w(0)) AND n0l1i01l); + niOlll0ll <= (((wire_niO01iOi_w_lg_n0l1i00l14042w(0) AND wire_niO01iOi_w_lg_n0l1i00i13736w(0)) AND wire_niO01iOi_w_lg_n0l1i01O13738w(0)) AND wire_niO01iOi_w_lg_n0l1i01l14045w(0)); + niOlll0lO <= (wire_niO11O1l_dataout AND (niOlll0Ol OR niOlll0Oi)); + niOlll0Oi <= (wire_niO11Oll_w14037w(0) AND wire_niO11O1O_w_lg_dataout13618w(0)); + niOlll0Ol <= ((wire_niO11Oll_w_lg_w_lg_w13966w14017w14018w(0) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_w_lg_dataout13618w(0)); + niOlll0OO <= (wire_niO11O1l_dataout AND (niOllli1l OR niOllli1i)); + niOlll10i <= (n0iOl11l AND n0iOl11i); + niOlll10l <= (wire_niO01ill_w_lg_n0l1OiiO13899w(0) OR wire_w_lg_w_lg_niOllll1l13624w13900w(0)); + niOlll10O <= (niOlll0OO AND niOlll1il); + niOlll11i <= (((wire_niO11Oll_w_lg_w13966w13967w(0) AND wire_niO11O0l_w_lg_dataout13968w(0)) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_dataout); + niOlll11l <= (((wire_niO11Oll_w_lg_w_lg_w13985w13986w13987w(0) AND wire_niO11O0l_w_lg_dataout13968w(0)) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_dataout); + niOlll11O <= (wire_niO01ill_w_lg_n0iOl11l14132w(0) AND wire_niO01ill_w_lg_n0iOl11i14133w(0)); + niOlll1ii <= (niOlll1li AND wire_w_lg_niOlll1il13861w(0)); + niOlll1il <= (((wire_niO01iOi_w_lg_n0iOliii14125w(0) AND wire_niO01iOi_w_lg_n0iOli0O14126w(0)) AND wire_niO01iOi_w_lg_n0iOli0l14128w(0)) AND wire_niO01iOi_w_lg_n0iOli0i14130w(0)); + niOlll1iO <= (((wire_niO11Oll_w_lg_w14120w14121w(0) AND wire_niO11O0l_w_lg_dataout13968w(0)) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_dataout); + niOlll1li <= (wire_niO11O1l_dataout AND niOlll1iO); + niOlll1ll <= ((n0l10llO AND niOlll1OO) AND wire_w_lg_niOlll1lO13819w(0)); + niOlll1lO <= (((((((n0iOO10l AND n0iOO10i) AND n0iOO11O) AND n0iOO11l) AND n0iOO11i) AND n0iOlOOO) AND n0iOlOOl) AND n0iOlOOi); + niOlll1Oi <= (n0l10llO AND wire_w_lg_niOlll1OO13816w(0)); + niOlll1Ol <= (n0l10lll OR (niOlO1O0i OR n0l10lOi)); + niOlll1OO <= ((((((wire_niO01ill_w_lg_w_lg_w13776w13779w13780w(0) AND ((((NOT (n0l10O1l XOR n0iOO1iO)) AND (NOT (n0l10O1O XOR n0iOO1li))) AND (NOT (n0l10O0i XOR n0iOO1ll))) AND (NOT (n0l10O0l XOR n0iOO1lO)))) AND (((NOT (n0l10OOl XOR n0iOO00O)) AND (NOT (n0l10OOO XOR n0iOO0ii))) AND (NOT (n0l1i11i XOR n0iOO0il)))) AND (NOT (n0l10lOO XOR n0iOO1ii))) AND (NOT (n0l10lOl XOR n0iOO10O))) AND (NOT (n0l10O1i XOR n0iOO1il))) AND (NOT (n0l10lli XOR n0iOlOli))); + niOllli0i <= (niOlO1O0i OR (NOT (wire_niO11O1l_dataout AND niOllli0l))); + niOllli0l <= ((((((((wire_niO11O1O_w_lg_dataout13618w(0) AND wire_n0iO1iil_w_lg_dataout14000w(0)) AND wire_n0iO1i0O_w_lg_dataout14002w(0)) AND wire_n0iO1i0i_w_lg_dataout14004w(0)) AND wire_n0iO1i1l_w_lg_dataout14006w(0)) AND wire_n0iO10OO_w_lg_dataout14008w(0)) AND wire_n0iO10lO_w_lg_dataout14010w(0)) AND wire_n0iO10li_w_lg_dataout14012w(0)) AND wire_n0iO10ii_w_lg_dataout14014w(0)); + niOllli0O <= (n0l1OiOi AND n0l1Oill); + niOllli1i <= ((wire_niO11Oll_w_lg_w_lg_w_lg_w14028w14029w14030w14031w(0) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_w_lg_dataout13618w(0)); + niOllli1l <= (wire_niO11Oll_w_lg_w_lg_w_lg_w14021w14022w14023w14024w(0) AND wire_niO11O1O_w_lg_dataout13618w(0)); + niOllli1O <= (n0l1OiOO AND (niOlllill OR niOlllili)); + niOllliii <= (niOllliOO AND (wire_niO01ill_w_lg_n0l1OilO13666w(0) AND niOllli0O)); + niOllliil <= (niOllliOO AND (n0l1OilO AND (n0l1OiOi AND wire_niO01ill_w_lg_n0l1Oill13661w(0)))); + niOllliiO <= (niOllliOO AND n0l1Oili); + niOlllili <= (wire_niO11O1O_w_lg_dataout13618w(0) AND wire_niO11O1l_dataout); + niOlllill <= (wire_niO11O1l_dataout AND niOlllilO); + niOlllilO <= (((((wire_niO11Oll_w_lg_w_lg_w_lg_dataout13991w13992w13993w(0) AND wire_niO11Oii_w_lg_dataout13994w(0)) AND wire_niO11O0O_dataout) AND wire_niO11O0l_dataout) AND wire_niO11O0i_dataout) AND wire_niO11O1O_dataout); + niOllliOi <= (wire_niO11O1l_dataout AND niOllliOl); + niOllliOl <= (((wire_niO11Oll_w_lg_w_lg_w13985w13986w13987w(0) AND wire_niO11O0l_w_lg_dataout13968w(0)) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_dataout); + niOllliOO <= (wire_niO11O1l_dataout AND niOllll1i); + niOllll0i <= (((wire_niO11lOl_w_lg_dataout13576w(0) AND wire_niO11llO_w_lg_dataout13577w(0)) OR wire_niO11lOl_w_lg_w_lg_dataout13579w13580w(0)) AND wire_w_lg_niOllll0l13582w(0)); + niOllll0l <= ((((((n0l0111O AND n0l0111l) AND n0l0111i) AND n0l1OOOO) AND n0l1OOOl) AND n0l1OOOi) AND n0l1Ol1i); + niOllll0O <= ((wire_niO01ill_w_lg_n0li111O13375w(0) AND wire_w_lg_niOllO10l13378w(0)) OR wire_niO01ill_w_lg_n0iOiO0O13573w(0)); + niOllll1i <= (((wire_niO11Oll_w_lg_w_lg_w13976w13977w13978w(0) AND wire_niO11O0l_w_lg_dataout13968w(0)) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_dataout); + niOllll1l <= (wire_niO11O1l_dataout AND niOllll1O); + niOllll1O <= (((wire_niO11Oll_w_lg_w13966w13967w(0) AND wire_niO11O0l_w_lg_dataout13968w(0)) AND wire_niO11O0i_w_lg_dataout13970w(0)) AND wire_niO11O1O_dataout); + niOllllii <= (((NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0l01lOl)) AND (NOT (n1101l1i XOR n0l01lOO))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0l01O1i))); + niOllllil <= ((wire_niO01ill_w_lg_n0li111O13375w(0) AND (wire_niO01ill_w_lg_n0li110l13383w(0) AND wire_w_lg_niOllO10l13378w(0))) OR wire_niO01ill_w_lg_n0l01lli13445w(0)); + niOlllliO <= (wire_niO01ill_w_lg_n0l01l0l13945w(0) AND wire_niO01ill_w_lg_n0l01l1O13509w(0)); + niOllllli <= (wire_niO01ill_w_lg_n0l01l0l13945w(0) AND n0l01l1O); + niOllllll <= (niOlllOll AND wire_n0l0l0il_o); + niOlllllO <= (n1l0001i AND (wire_n0l0l0lO_o AND niOlllOll)); + niOllllOi <= (n1l0001i AND niOllO11i); + niOllllOl <= wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13515w(0); + niOllllOO <= ((wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13932w(0) AND wire_niO01ill_w_lg_n0l01l0i13507w(0)) AND wire_niO01ill_w_lg_n0l01l1O13509w(0)); + niOlllO0i <= ((wire_niO01ill_w_lg_n0l01l0O13939w(0) AND wire_niO01ill_w_lg_n0l01l0i13507w(0)) AND wire_niO01ill_w_lg_n0l01l1O13509w(0)); + niOlllO0l <= ((wire_niO01ill_w_lg_n0l01l0O13939w(0) AND wire_niO01ill_w_lg_n0l01l0i13507w(0)) AND n0l01l1O); + niOlllO0O <= (wire_niO01ill_w_lg_n0l01l0O13939w(0) AND n0l01l0i); + niOlllO1i <= ((wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13932w(0) AND wire_niO01ill_w_lg_n0l01l0i13507w(0)) AND n0l01l1O); + niOlllO1l <= (wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0O13514w13932w13936w(0) AND wire_niO01ill_w_lg_n0l01l1O13509w(0)); + niOlllO1O <= (wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0O13514w13932w13936w(0) AND n0l01l1O); + niOlllOii <= (n0l01l0O AND n0l01l0l); + niOlllOil <= (wire_niO01ill_w_lg_n0l01llO13452w(0) AND wire_n0l01i1l_dataout); + niOlllOiO <= (n0l01llO AND wire_n0l01i1l_dataout); + niOlllOli <= (wire_niO01ill_w_lg_nlOllOlOi13438w(0) AND niOlllOll); + niOlllOll <= (n0li110l AND n0li110i); + niOlllOlO <= (wire_niO01ill_w_lg_w_lg_w_lg_n0l01O1l13444w13446w13447w(0) OR (n11O0O0l AND nlOllOlOi)); + niOlllOOi <= (n0li11ii OR (n0li110l AND niOlllOOl)); + niOlllOOl <= ((((((NOT (wire_n0li1OOi_dataout XOR n0l01lll)) AND (NOT (wire_n0li1OOl_dataout XOR n0l01llO))) AND (NOT (wire_n0li1OOO_dataout XOR n0l01lOi))) AND (NOT (wire_n0li011i_dataout XOR n0l01lOl))) AND (NOT (wire_n0li011l_dataout XOR n0l01lOO))) AND (NOT (wire_n0li011O_dataout XOR n0l01O1i))); + niOlllOOO <= (wire_niO01ill_w_lg_nlOllOlOi13438w(0) AND (niOllO11i OR wire_n0l01i0i_dataout)); + niOllO00i <= (wire_niO01ill_w_lg_n0lOi1Oi12992w(0) OR wire_w_lg_w_lg_niOllOO1i12717w12993w(0)); + niOllO00l <= (niOllOiOl AND niOllO0ii); + niOllO00O <= (niOllO0iO AND wire_w_lg_niOllO0ii12954w(0)); + niOllO01i <= (((wire_niO11lll_w_lg_w_lg_w13078w13079w13080w(0) AND wire_niO11l0l_w_lg_dataout13061w(0)) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_dataout); + niOllO01l <= (wire_niO01ill_w_lg_n0ll1l0O13225w(0) AND wire_niO01ill_w_lg_n0ll1l0l13226w(0)); + niOllO01O <= (n0ll1l0O AND n0ll1l0l); + niOllO0ii <= (((wire_niO01iOi_w_lg_n0ll01ll13218w(0) AND wire_niO01iOi_w_lg_n0ll01li13219w(0)) AND wire_niO01iOi_w_lg_n0ll01iO13221w(0)) AND wire_niO01iOi_w_lg_n0ll01il13223w(0)); + niOllO0il <= (((wire_niO11lll_w_lg_w13213w13214w(0) AND wire_niO11l0l_w_lg_dataout13061w(0)) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_dataout); + niOllO0iO <= (wire_niO11l1l_dataout AND niOllO0il); + niOllO0li <= ((n0llOi1i AND niOllO0Ol) AND wire_w_lg_niOllO0ll12912w(0)); + niOllO0ll <= (((((((n0ll0liO AND n0ll0lil) AND n0ll0lii) AND n0ll0l0O) AND n0ll0l0l) AND n0ll0l0i) AND n0ll0l1O) AND n0ll0l1l); + niOllO0lO <= (n0llOi1i AND wire_w_lg_niOllO0Ol12909w(0)); + niOllO0Oi <= (n0llO0OO OR (niOlO1O0i OR n0llOi1l)); + niOllO0Ol <= ((((((wire_niO01ill_w_lg_w_lg_w12869w12872w12873w(0) AND ((((NOT (n0llOi0O XOR n0ll0lOi)) AND (NOT (n0llOiii XOR n0ll0lOl))) AND (NOT (n0llOiil XOR n0ll0lOO))) AND (NOT (n0llOiiO XOR n0ll0O1i)))) AND (((NOT (n0llOl1O XOR n0ll0Oli)) AND (NOT (n0llOl0i XOR n0ll0Oll))) AND (NOT (n0llOl0l XOR n0ll0OlO)))) AND (NOT (n0llOi0i XOR n0ll0lll))) AND (NOT (n0llOi1O XOR n0ll0lli))) AND (NOT (n0llOi0l XOR n0ll0llO))) AND (NOT (n0llO0Ol XOR n0ll0iOl))); + niOllO0OO <= ((((((((NOT (n0llOili XOR n0ll0O1l)) AND (NOT (n0llOill XOR n0ll0O1O))) AND (NOT (n0llOilO XOR n0ll0O0i))) AND (NOT (n0llOiOi XOR n0ll0O0l))) AND (NOT (n0llOiOl XOR n0ll0O0O))) AND (NOT (n0llOiOO XOR n0ll0Oii))) AND (NOT (n0llOl1i XOR n0ll0Oil))) AND (NOT (n0llOl1l XOR n0ll0OiO))); + niOllO10i <= (wire_niO01ill_w_lg_n0li111O13375w(0) AND (wire_niO01ill_w_lg_n0li110l13383w(0) AND wire_w_lg_niOllO1ii13373w(0))); + niOllO10l <= ((n0li111l AND n0li111i) AND n0l00iOO); + niOllO10O <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOllO11i <= (n0li110l AND wire_niO01ill_w_lg_n0li110i13454w(0)); + niOllO11l <= (wire_niO01ill_w_lg_nlOllOlOi13438w(0) AND n0li111O); + niOllO11O <= (wire_n0l0OOil_o OR n0l01O1l); + niOllO1ii <= ((wire_niO01ill_w_lg_n0li111l13910w(0) AND n0li111i) AND n0l00iOO); + niOllO1il <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOllO1iO <= (wire_niO01ill_w_lg_n1101lii13369w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOllO1li <= (wire_niO01ill_w_lg_n1101lii13369w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOllO1ll <= (n0O1illO OR (NOT (n111i10i OR n0li0O0l))); + niOllO1lO <= (((wire_niO01ill_w_lg_w_lg_w13314w13315w13316w(0) AND wire_niO01ill_w_lg_n0O1ilOl13305w(0)) AND wire_niO01ill_w_lg_n0O1ilOi13307w(0)) AND n0O1illO); + niOllO1Oi <= (((wire_niO01ill_w_lg_w13303w13304w(0) AND wire_niO01ill_w_lg_n0O1ilOl13305w(0)) AND wire_niO01ill_w_lg_n0O1ilOi13307w(0)) AND n0O1illO); + niOllO1Ol <= (wire_niO11l1O_dataout OR n111i10l); + niOllO1OO <= (((wire_niO11lll_w_lg_w13059w13060w(0) AND wire_niO11l0l_w_lg_dataout13061w(0)) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_dataout); + niOllOi0i <= (wire_niO01iOi_w_lg_w_lg_n0llOOiO12830w13143w(0) AND wire_niO01iOi_w_lg_n0llOO0O13138w(0)); + niOllOi0l <= (wire_niO01iOi_w_lg_w_lg_n0llOOiO12830w13143w(0) AND n0llOO0O); + niOllOi0O <= (((n0llOOiO AND n0llOOil) AND wire_niO01iOi_w_lg_n0llOOii12831w(0)) AND wire_niO01iOi_w_lg_n0llOO0O13138w(0)); + niOllOi1i <= ((((((((NOT (n0llOllO XOR n0lli10i)) AND (NOT (n0llOlOi XOR n0lli10l))) AND (NOT (n0llOlOl XOR n0lli10O))) AND (NOT (n0llOlOO XOR n0lli1ii))) AND (NOT (n0llOO1i XOR n0lli1il))) AND (NOT (n0llOO1l XOR n0lli1iO))) AND (NOT (n0llOO1O XOR n0lli1li))) AND (NOT (n0llOO0i XOR n0lli1ll))); + niOllOi1l <= (((((NOT (n0llOl0O XOR n0ll0OOi)) AND (NOT (n0llOlii XOR n0ll0OOl))) AND (NOT (n0llOlil XOR n0ll0OOO))) AND (NOT (n0llOliO XOR n0lli11i))) AND (NOT (n0llOlli XOR n0lli11l))); + niOllOi1O <= (n0lOi00i AND niOllO0iO); + niOllOiii <= (((n0llOOiO AND n0llOOil) AND n0llOOii) AND n0llOO0O); + niOllOiil <= ((niOllOliO OR niOllOili) OR (niOllOlli AND niOllOiiO)); + niOllOiiO <= (((n0llOOiO AND n0llOOil) AND wire_niO01iOi_w_lg_n0llOOii12831w(0)) AND n0llOO0O); + niOllOili <= (((wire_niO01iOi_w_lg_n0llOOiO13135w(0) AND wire_niO01iOi_w_lg_n0llOOil12829w(0)) AND wire_niO01iOi_w_lg_n0llOOii12831w(0)) AND wire_niO01iOi_w_lg_n0llOO0O13138w(0)); + niOllOill <= (wire_niO11l1l_dataout AND (niOllOiOi OR niOllOilO)); + niOllOilO <= (wire_niO11lll_w13130w(0) AND wire_niO11l1O_w_lg_dataout12711w(0)); + niOllOiOi <= ((wire_niO11lll_w_lg_w_lg_w13059w13110w13111w(0) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_w_lg_dataout12711w(0)); + niOllOiOl <= (wire_niO11l1l_dataout AND (niOllOl1i OR niOllOiOO)); + niOllOiOO <= ((wire_niO11lll_w_lg_w_lg_w_lg_w13121w13122w13123w13124w(0) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_w_lg_dataout12711w(0)); + niOllOl0i <= ((((((((wire_niO11l1O_w_lg_dataout12711w(0) AND wire_n0lil1lO_w_lg_dataout13093w(0)) AND wire_n0lil1li_w_lg_dataout13095w(0)) AND wire_n0lil1il_w_lg_dataout13097w(0)) AND wire_n0lil10O_w_lg_dataout13099w(0)) AND wire_n0lil10i_w_lg_dataout13101w(0)) AND wire_n0lil11i_w_lg_dataout13103w(0)) AND wire_n0liiOOl_w_lg_dataout13105w(0)) AND wire_n0liiOll_w_lg_dataout13107w(0)); + niOllOl0l <= (n0lOi01l AND n0lOi1OO); + niOllOl0O <= (niOllOlOl AND (wire_niO01ill_w_lg_n0lOi01i12759w(0) AND niOllOl0l)); + niOllOl1i <= (wire_niO11lll_w_lg_w_lg_w_lg_w13114w13115w13116w13117w(0) AND wire_niO11l1O_w_lg_dataout12711w(0)); + niOllOl1l <= (n0lOi00i AND (niOllOlli OR niOllOliO)); + niOllOl1O <= (niOlO1O0i OR (NOT (wire_niO11l1l_dataout AND niOllOl0i))); + niOllOlii <= (niOllOlOl AND (n0lOi01i AND (n0lOi01l AND wire_niO01ill_w_lg_n0lOi1OO12754w(0)))); + niOllOlil <= (niOllOlOl AND n0lOi1Ol); + niOllOliO <= (wire_niO11l1O_w_lg_dataout12711w(0) AND wire_niO11l1l_dataout); + niOllOlli <= (wire_niO11l1l_dataout AND niOllOlll); + niOllOlll <= (((((wire_niO11lll_w_lg_w_lg_w_lg_dataout13084w13085w13086w(0) AND wire_niO11lii_w_lg_dataout13087w(0)) AND wire_niO11l0O_dataout) AND wire_niO11l0l_dataout) AND wire_niO11l0i_dataout) AND wire_niO11l1O_dataout); + niOllOllO <= (wire_niO11l1l_dataout AND niOllOlOi); + niOllOlOi <= (((wire_niO11lll_w_lg_w_lg_w13078w13079w13080w(0) AND wire_niO11l0l_w_lg_dataout13061w(0)) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_dataout); + niOllOlOl <= (wire_niO11l1l_dataout AND niOllOlOO); + niOllOlOO <= (((wire_niO11lll_w_lg_w_lg_w13069w13070w13071w(0) AND wire_niO11l0l_w_lg_dataout13061w(0)) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_dataout); + niOllOO0i <= ((((((n0lOilii AND n0lOil0O) AND n0lOil0l) AND n0lOil0i) AND n0lOil1O) AND n0lOil1l) AND n0lOi00l); + niOllOO0l <= ((wire_niO01ill_w_lg_n0O1ilii12468w(0) AND wire_w_lg_niOlO100i12471w(0)) OR wire_niO01ill_w_lg_n0ll1ili12666w(0)); + niOllOO0O <= (((NOT (n1101l1i XOR n0lOli1O)) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0lOli0i))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0lOli0l))); + niOllOO1i <= (wire_niO11l1l_dataout AND niOllOO1l); + niOllOO1l <= (((wire_niO11lll_w_lg_w13059w13060w(0) AND wire_niO11l0l_w_lg_dataout13061w(0)) AND wire_niO11l0i_w_lg_dataout13063w(0)) AND wire_niO11l1O_dataout); + niOllOO1O <= (((wire_niO11iOl_w_lg_dataout12669w(0) AND wire_niO11ilO_w_lg_dataout12670w(0)) OR wire_niO11iOl_w_lg_w_lg_dataout12672w12673w(0)) AND wire_w_lg_niOllOO0i12675w(0)); + niOllOOii <= ((wire_niO01ill_w_lg_n0O1ilii12468w(0) AND (wire_niO01ill_w_lg_n0O1iliO12476w(0) AND wire_w_lg_niOlO100i12471w(0))) OR wire_niO01ill_w_lg_n0lOl0Ol12538w(0)); + niOllOOil <= (wire_niO01ill_w_lg_n0lOl0iO13038w(0) AND wire_niO01ill_w_lg_n0lOl0ii12602w(0)); + niOllOOiO <= (wire_niO01ill_w_lg_n0lOl0iO13038w(0) AND n0lOl0ii); + niOllOOli <= (niOlO11li AND wire_n0O11OlO_o); + niOllOOll <= (n1l0001i AND (wire_n0O1011i_o AND niOlO11li)); + niOllOOlO <= (n1l0001i AND niOlO11OO); + niOllOOOi <= wire_niO01ill_w_lg_w_lg_n0lOl0li12607w12608w(0); + niOllOOOl <= ((wire_niO01ill_w_lg_w_lg_n0lOl0li12607w13025w(0) AND wire_niO01ill_w_lg_n0lOl0il12600w(0)) AND wire_niO01ill_w_lg_n0lOl0ii12602w(0)); + niOllOOOO <= ((wire_niO01ill_w_lg_w_lg_n0lOl0li12607w13025w(0) AND wire_niO01ill_w_lg_n0lOl0il12600w(0)) AND n0lOl0ii); + niOlO000i <= ((wire_niO01ill_w_lg_n0Ol1OOl12124w(0) AND wire_niO01ill_w_lg_n0Ol1OlO11689w(0)) AND n0Ol1Oll); + niOlO000l <= (wire_niO01ill_w_lg_n0Ol1OOl12124w(0) AND n0Ol1OlO); + niOlO000O <= (n0Ol1OOl AND n0Ol1OOi); + niOlO001i <= (wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOl11696w12117w12121w(0) AND wire_niO01ill_w_lg_n0Ol1Oll11691w(0)); + niOlO001l <= (wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOl11696w12117w12121w(0) AND n0Ol1Oll); + niOlO001O <= ((wire_niO01ill_w_lg_n0Ol1OOl12124w(0) AND wire_niO01ill_w_lg_n0Ol1OlO11689w(0)) AND wire_niO01ill_w_lg_n0Ol1Oll11691w(0)); + niOlO00ii <= (wire_niO01ill_w_lg_n0Ol010l11633w(0) AND wire_n0Ol1lli_dataout); + niOlO00il <= (n0Ol010l AND wire_n0Ol1lli_dataout); + niOlO00iO <= (wire_niO01ill_w_lg_nlOllOlOO11619w(0) AND niOlO00li); + niOlO00li <= (n0OO10Oi AND n0OO10lO); + niOlO00ll <= (wire_niO01ill_w_lg_w_lg_w_lg_n0Ol01li11625w11627w11628w(0) OR (n11O0O0l AND nlOllOlOO)); + niOlO00lO <= (n0OO10OO OR (n0OO10Oi AND niOlO00Oi)); + niOlO00Oi <= ((((((NOT (wire_n0OO000O_dataout XOR n0Ol010i)) AND (NOT (wire_n0OO00ii_dataout XOR n0Ol010l))) AND (NOT (wire_n0OO00il_dataout XOR n0Ol010O))) AND (NOT (wire_n0OO00iO_dataout XOR n0Ol01ii))) AND (NOT (wire_n0OO00li_dataout XOR n0Ol01il))) AND (NOT (wire_n0OO00ll_dataout XOR n0Ol01iO))); + niOlO00Ol <= (wire_niO01ill_w_lg_nlOllOlOO11619w(0) AND (niOlO00OO OR wire_n0Ol1llO_dataout)); + niOlO00OO <= (n0OO10Oi AND wire_niO01ill_w_lg_n0OO10lO11635w(0)); + niOlO010i <= ((((((n0Ol10ll AND n0Ol10li) AND n0Ol10iO) AND n0Ol10il) AND n0Ol10ii) AND n0Ol100O) AND n0OiOOiO); + niOlO010l <= ((wire_niO01ill_w_lg_n0OO10ll11555w(0) AND wire_w_lg_niOlO0i0i11558w(0)) OR wire_niO01ill_w_lg_n0O0l1Ol11755w(0)); + niOlO010O <= (((NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0Ol01ii)) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0Ol01il))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0Ol01iO))); + niOlO011i <= (wire_niO11i1l_dataout AND niOlO011l); + niOlO011l <= (((wire_niO11ill_w_lg_w12151w12152w(0) AND wire_niO11i0l_w_lg_dataout12153w(0)) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_dataout); + niOlO011O <= (((wire_niO110Ol_w_lg_dataout11758w(0) AND wire_niO110lO_w_lg_dataout11759w(0)) OR wire_niO110Ol_w_lg_w_lg_dataout11761w11762w(0)) AND wire_w_lg_niOlO010i11764w(0)); + niOlO01ii <= ((wire_niO01ill_w_lg_n0OO10ll11555w(0) AND (wire_niO01ill_w_lg_n0OO10Oi11564w(0) AND wire_w_lg_niOlO0i0i11558w(0))) OR wire_niO01ill_w_lg_n0Ol011O11626w(0)); + niOlO01il <= (wire_niO01ill_w_lg_n0Ol1OOi12130w(0) AND wire_niO01ill_w_lg_n0Ol1Oll11691w(0)); + niOlO01iO <= (wire_niO01ill_w_lg_n0Ol1OOi12130w(0) AND n0Ol1Oll); + niOlO01li <= (niOlO00li AND wire_n0Olll1i_o); + niOlO01ll <= (n1l0001i AND (wire_n0Olll0l_o AND niOlO00li)); + niOlO01lO <= (n1l0001i AND niOlO00OO); + niOlO01Oi <= wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w11697w(0); + niOlO01Ol <= ((wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w12117w(0) AND wire_niO01ill_w_lg_n0Ol1OlO11689w(0)) AND wire_niO01ill_w_lg_n0Ol1Oll11691w(0)); + niOlO01OO <= ((wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w12117w(0) AND wire_niO01ill_w_lg_n0Ol1OlO11689w(0)) AND n0Ol1Oll); + niOlO0i0i <= ((n0OO10li AND n0OO10iO) AND n0Ol0Oil); + niOlO0i0l <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOlO0i0O <= ((wire_niO01ill_w_lg_n0OO10li12093w(0) AND n0OO10iO) AND n0Ol0Oil); + niOlO0i1i <= (wire_niO01ill_w_lg_nlOllOlOO11619w(0) AND n0OO10ll); + niOlO0i1l <= (wire_n0OO101i_o OR n0Ol01li); + niOlO0i1O <= (wire_niO01ill_w_lg_n0OO10ll11555w(0) AND (wire_niO01ill_w_lg_n0OO10Oi11564w(0) AND wire_w_lg_niOlO0i0O11553w(0))); + niOlO0iii <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOlO0iil <= (wire_niO01ill_w_lg_n1101liO11541w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOlO0iiO <= (wire_niO01ill_w_lg_n1101liO11541w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOlO0ili <= (wire_w_lg_niOlOOiOl11421w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11472w(0) OR (niOlOl0Ol AND niOlO0lil))); + niOlO0ill <= (wire_w_lg_niOlOOiOl11421w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11468w(0) OR (niOlOl0Ol AND niOlO0ilO))); + niOlO0ilO <= ((ni111llO AND ni111lll) AND wire_niO01ill_w_lg_ni111lli11446w(0)); + niOlO0iOi <= (wire_w_lg_niOlOOiOl11421w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11464w(0) OR (niOlOl0Ol AND niOlO0iOl))); + niOlO0iOl <= (wire_niO01ill_w_lg_ni111llO11482w(0) AND ni111lli); + niOlO0iOO <= (wire_w_lg_niOlOOiOl11421w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11460w(0) OR (niOlOl0Ol AND niOlO0l1i))); + niOlO0l0i <= (wire_w_lg_niOlOOiOl11421w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11452w(0) OR (niOlOl0Ol AND niOlO0l0l))); + niOlO0l0l <= (wire_niO01ill_w_lg_w_lg_ni111llO11443w11479w(0) AND wire_niO01ill_w_lg_ni111lli11446w(0)); + niOlO0l0O <= (wire_w_lg_niOlOOiOl11421w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni111llO11443w(0) AND wire_niO01ill_w_lg_ni111lll11444w(0)) AND wire_niO01ill_w_lg_ni111lli11446w(0))) OR (niOlOl0Ol AND niOlO0liO))); + niOlO0l1i <= (wire_niO01ill_w_lg_ni111llO11482w(0) AND wire_niO01ill_w_lg_ni111lli11446w(0)); + niOlO0l1l <= (wire_w_lg_niOlOOiOl11421w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11456w(0) OR (niOlOl0Ol AND niOlO0l1O))); + niOlO0l1O <= (wire_niO01ill_w_lg_w_lg_ni111llO11443w11479w(0) AND ni111lli); + niOlO0lii <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOOiOl11421w11441w(0)); + niOlO0lil <= ((ni111llO AND ni111lll) AND ni111lli); + niOlO0liO <= ((wire_niO01ill_w_lg_ni111llO11443w(0) AND wire_niO01ill_w_lg_ni111lll11444w(0)) AND ni111lli); + niOlO0lli <= (wire_w_lg_niOlOOiOl11421w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlO0lll <= (niOlOOiOl AND niOlOl0Ol); + niOlO0llO <= (wire_w_lg_niOlOOi0l11340w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11391w(0) OR (niOlOl0Ol AND niOlO0Oli))); + niOlO0lOi <= (wire_w_lg_niOlOOi0l11340w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11387w(0) OR (niOlOl0Ol AND niOlO0lOl))); + niOlO0lOl <= ((ni101i0i AND ni101i1O) AND wire_niO01ill_w_lg_ni101i1l11365w(0)); + niOlO0lOO <= (wire_w_lg_niOlOOi0l11340w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11383w(0) OR (niOlOl0Ol AND niOlO0O1i))); + niOlO0O0i <= (wire_w_lg_niOlOOi0l11340w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11375w(0) OR (niOlOl0Ol AND niOlO0O0l))); + niOlO0O0l <= (wire_niO01ill_w_lg_w_lg_ni101i0i11362w11398w(0) AND ni101i1l); + niOlO0O0O <= (wire_w_lg_niOlOOi0l11340w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11371w(0) OR (niOlOl0Ol AND niOlO0Oii))); + niOlO0O1i <= (wire_niO01ill_w_lg_ni101i0i11401w(0) AND ni101i1l); + niOlO0O1l <= (wire_w_lg_niOlOOi0l11340w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11379w(0) OR (niOlOl0Ol AND niOlO0O1O))); + niOlO0O1O <= (wire_niO01ill_w_lg_ni101i0i11401w(0) AND wire_niO01ill_w_lg_ni101i1l11365w(0)); + niOlO0Oii <= (wire_niO01ill_w_lg_w_lg_ni101i0i11362w11398w(0) AND wire_niO01ill_w_lg_ni101i1l11365w(0)); + niOlO0Oil <= (wire_w_lg_niOlOOi0l11340w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni101i0i11362w(0) AND wire_niO01ill_w_lg_ni101i1O11363w(0)) AND wire_niO01ill_w_lg_ni101i1l11365w(0))) OR (niOlOl0Ol AND niOlO0Oll))); + niOlO0OiO <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOOi0l11340w11360w(0)); + niOlO0Oli <= ((ni101i0i AND ni101i1O) AND ni101i1l); + niOlO0Oll <= ((wire_niO01ill_w_lg_ni101i0i11362w(0) AND wire_niO01ill_w_lg_ni101i1O11363w(0)) AND ni101i1l); + niOlO0OlO <= (wire_w_lg_niOlOOi0l11340w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlO0OOi <= (niOlOOi0l AND niOlOl0Ol); + niOlO0OOl <= (wire_w_lg_niOlOO0ll11259w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11310w(0) OR (niOlOl0Ol AND niOlOi1lO))); + niOlO0OOO <= (wire_w_lg_niOlOO0ll11259w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11306w(0) OR (niOlOl0Ol AND niOlOi11i))); + niOlO100i <= ((n0O1il0O AND n0O1il0l) AND n0lOO00i); + niOlO100l <= ((n1l0010O AND n1l0010l) AND n1l0010i); + niOlO100O <= ((wire_niO01ill_w_lg_n0O1il0O13003w(0) AND n0O1il0l) AND n0lOO00i); + niOlO101i <= (wire_niO01ill_w_lg_nlOllOlOl12531w(0) AND n0O1ilii); + niOlO101l <= (wire_n0O1iilO_o OR n0lOli0O); + niOlO101O <= (wire_niO01ill_w_lg_n0O1ilii12468w(0) AND (wire_niO01ill_w_lg_n0O1iliO12476w(0) AND wire_w_lg_niOlO100O12466w(0))); + niOlO10ii <= (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND n1l0010i); + niOlO10il <= (wire_niO01ill_w_lg_n1101lil12462w(0) AND (wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) AND wire_niO01ill_w_lg_n1l0010i11548w(0))); + niOlO10iO <= (wire_niO01ill_w_lg_n1101lil12462w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0)); + niOlO10li <= (n0OO1i1i OR (NOT (n111i10i OR n0O1OiiO))); + niOlO10ll <= (((wire_niO01ill_w_lg_w_lg_w12407w12408w12409w(0) AND wire_niO01ill_w_lg_n0OO1i1O12398w(0)) AND wire_niO01ill_w_lg_n0OO1i1l12400w(0)) AND n0OO1i1i); + niOlO10lO <= (((wire_niO01ill_w_lg_w12396w12397w(0) AND wire_niO01ill_w_lg_n0OO1i1O12398w(0)) AND wire_niO01ill_w_lg_n0OO1i1l12400w(0)) AND n0OO1i1i); + niOlO10Oi <= (wire_niO11i1O_dataout OR n111i10l); + niOlO10Ol <= (((wire_niO11ill_w_lg_w12151w12152w(0) AND wire_niO11i0l_w_lg_dataout12153w(0)) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_dataout); + niOlO10OO <= (((wire_niO11ill_w_lg_w_lg_w12170w12171w12172w(0) AND wire_niO11i0l_w_lg_dataout12153w(0)) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_dataout); + niOlO110i <= ((wire_niO01ill_w_lg_n0lOl0li13032w(0) AND wire_niO01ill_w_lg_n0lOl0il12600w(0)) AND n0lOl0ii); + niOlO110l <= (wire_niO01ill_w_lg_n0lOl0li13032w(0) AND n0lOl0il); + niOlO110O <= (n0lOl0li AND n0lOl0iO); + niOlO111i <= (wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0li12607w13025w13029w(0) AND wire_niO01ill_w_lg_n0lOl0ii12602w(0)); + niOlO111l <= (wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0li12607w13025w13029w(0) AND n0lOl0ii); + niOlO111O <= ((wire_niO01ill_w_lg_n0lOl0li13032w(0) AND wire_niO01ill_w_lg_n0lOl0il12600w(0)) AND wire_niO01ill_w_lg_n0lOl0ii12602w(0)); + niOlO11ii <= (wire_niO01ill_w_lg_n0lOli1i12545w(0) AND wire_n0lOl10O_dataout); + niOlO11il <= (n0lOli1i AND wire_n0lOl10O_dataout); + niOlO11iO <= (wire_niO01ill_w_lg_nlOllOlOl12531w(0) AND niOlO11li); + niOlO11li <= (n0O1iliO AND n0O1ilil); + niOlO11ll <= (wire_niO01ill_w_lg_w_lg_w_lg_n0lOli0O12537w12539w12540w(0) OR (n11O0O0l AND nlOllOlOl)); + niOlO11lO <= (n0O1illl OR (n0O1iliO AND niOlO11Oi)); + niOlO11Oi <= ((((((NOT (wire_n0O1ll1l_dataout XOR n0lOl0OO)) AND (NOT (wire_n0O1ll1O_dataout XOR n0lOli1i))) AND (NOT (wire_n0O1ll0i_dataout XOR n0lOli1l))) AND (NOT (wire_n0O1ll0l_dataout XOR n0lOli1O))) AND (NOT (wire_n0O1ll0O_dataout XOR n0lOli0i))) AND (NOT (wire_n0O1llii_dataout XOR n0lOli0l))); + niOlO11Ol <= (wire_niO01ill_w_lg_nlOllOlOl12531w(0) AND (niOlO11OO OR wire_n0lOl1il_dataout)); + niOlO11OO <= (n0O1iliO AND wire_niO01ill_w_lg_n0O1ilil12547w(0)); + niOlO1i0i <= (niOlO1lOi AND niOlO1i0O); + niOlO1i0l <= (niOlO1iil AND wire_w_lg_niOlO1i0O12043w(0)); + niOlO1i0O <= (((wire_niO01iOi_w_lg_n0O0llOO12310w(0) AND wire_niO01iOi_w_lg_n0O0llOl12311w(0)) AND wire_niO01iOi_w_lg_n0O0llOi12313w(0)) AND wire_niO01iOi_w_lg_n0O0lllO12315w(0)); + niOlO1i1i <= (wire_niO01ill_w_lg_n0O0l0li12317w(0) AND wire_niO01ill_w_lg_n0O0l0iO12318w(0)); + niOlO1i1l <= (n0O0l0li AND n0O0l0iO); + niOlO1i1O <= (wire_niO01ill_w_lg_n0OiOO1l12081w(0) OR wire_w_lg_w_lg_niOlO011i11806w12082w(0)); + niOlO1iii <= (((wire_niO11ill_w_lg_w12305w12306w(0) AND wire_niO11i0l_w_lg_dataout12153w(0)) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_dataout); + niOlO1iil <= (wire_niO11i1l_dataout AND niOlO1iii); + niOlO1iiO <= ((n0Oii10l AND niOlO1iOi) AND wire_w_lg_niOlO1ili12001w(0)); + niOlO1ili <= (((((((n0O0O0Oi AND n0O0O0lO) AND n0O0O0ll) AND n0O0O0li) AND n0O0O0iO) AND n0O0O0il) AND n0O0O0ii) AND n0O0O00O); + niOlO1ill <= (n0Oii10l AND wire_w_lg_niOlO1iOi11998w(0)); + niOlO1ilO <= (n0Oii10i OR (niOlO1O0i OR n0Oii10O)); + niOlO1iOi <= ((((((wire_niO01ill_w_lg_w_lg_w11958w11961w11962w(0) AND ((((NOT (n0Oii1li XOR n0O0Oi1l)) AND (NOT (n0Oii1ll XOR n0O0Oi1O))) AND (NOT (n0Oii1lO XOR n0O0Oi0i))) AND (NOT (n0Oii1Oi XOR n0O0Oi0l)))) AND (((NOT (n0Oii0ii XOR n0O0OiOl)) AND (NOT (n0Oii0il XOR n0O0OiOO))) AND (NOT (n0Oii0iO XOR n0O0Ol1i)))) AND (NOT (n0Oii1il XOR n0O0O0OO))) AND (NOT (n0Oii1ii XOR n0O0O0Ol))) AND (NOT (n0Oii1iO XOR n0O0Oi1i))) AND (NOT (n0Oii11O XOR n0O0O01O))); + niOlO1iOl <= ((((((((NOT (n0Oii1Ol XOR n0O0Oi0O)) AND (NOT (n0Oii1OO XOR n0O0Oiii))) AND (NOT (n0Oii01i XOR n0O0Oiil))) AND (NOT (n0Oii01l XOR n0O0OiiO))) AND (NOT (n0Oii01O XOR n0O0Oili))) AND (NOT (n0Oii00i XOR n0O0Oill))) AND (NOT (n0Oii00l XOR n0O0OilO))) AND (NOT (n0Oii00O XOR n0O0OiOi))); + niOlO1iOO <= ((((((((NOT (n0Oiii1i XOR n0O0Olil)) AND (NOT (n0Oiii1l XOR n0O0OliO))) AND (NOT (n0Oiii1O XOR n0O0Olli))) AND (NOT (n0Oiii0i XOR n0O0Olll))) AND (NOT (n0Oiii0l XOR n0O0OllO))) AND (NOT (n0Oiii0O XOR n0O0OlOi))) AND (NOT (n0Oiiiii XOR n0O0OlOl))) AND (NOT (n0Oiiiil XOR n0O0OlOO))); + niOlO1l0i <= (wire_niO01iOi_w_lg_w_lg_n0OiiiOi11919w12235w(0) AND n0Oiiili); + niOlO1l0l <= (((n0OiiiOi AND n0OiiilO) AND wire_niO01iOi_w_lg_n0Oiiill11920w(0)) AND wire_niO01iOi_w_lg_n0Oiiili12230w(0)); + niOlO1l0O <= (((n0OiiiOi AND n0OiiilO) AND n0Oiiill) AND n0Oiiili); + niOlO1l1i <= (((((NOT (n0Oii0li XOR n0O0Ol1l)) AND (NOT (n0Oii0ll XOR n0O0Ol1O))) AND (NOT (n0Oii0lO XOR n0O0Ol0i))) AND (NOT (n0Oii0Oi XOR n0O0Ol0l))) AND (NOT (n0Oii0Ol XOR n0O0Ol0O))); + niOlO1l1l <= (n0OiOOil AND niOlO1iil); + niOlO1l1O <= (wire_niO01iOi_w_lg_w_lg_n0OiiiOi11919w12235w(0) AND wire_niO01iOi_w_lg_n0Oiiili12230w(0)); + niOlO1lii <= ((niOlO1OiO OR niOlO1liO) OR (niOlO1Oli AND niOlO1lil)); + niOlO1lil <= (((n0OiiiOi AND n0OiiilO) AND wire_niO01iOi_w_lg_n0Oiiill11920w(0)) AND n0Oiiili); + niOlO1liO <= (((wire_niO01iOi_w_lg_n0OiiiOi12227w(0) AND wire_niO01iOi_w_lg_n0OiiilO11918w(0)) AND wire_niO01iOi_w_lg_n0Oiiill11920w(0)) AND wire_niO01iOi_w_lg_n0Oiiili12230w(0)); + niOlO1lli <= (wire_niO11i1l_dataout AND (niOlO1llO OR niOlO1lll)); + niOlO1lll <= (wire_niO11ill_w12222w(0) AND wire_niO11i1O_w_lg_dataout11800w(0)); + niOlO1llO <= ((wire_niO11ill_w_lg_w_lg_w12151w12202w12203w(0) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_w_lg_dataout11800w(0)); + niOlO1lOi <= (wire_niO11i1l_dataout AND (niOlO1lOO OR niOlO1lOl)); + niOlO1lOl <= ((wire_niO11ill_w_lg_w_lg_w_lg_w12213w12214w12215w12216w(0) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_w_lg_dataout11800w(0)); + niOlO1lOO <= (wire_niO11ill_w_lg_w_lg_w_lg_w12206w12207w12208w12209w(0) AND wire_niO11i1O_w_lg_dataout11800w(0)); + niOlO1O0i <= (((((((((((((((((((((((((n11O0OlO XOR n11O0iOl) OR (n11O0OOi XOR n11O0iOO)) OR (n11O0OOl XOR n11O0l1i)) OR (n11O0OOO XOR n11O0l1l)) OR (n11Oi11i XOR n11O0l1O)) OR (n11Oi11l XOR n11O0l0i)) OR (n11Oi11O XOR n11O0l0l)) OR (n11Oi10i XOR n11O0l0O)) OR (n11Oi10l XOR n11O0lii)) OR (n11Oi10O XOR n11O0lil)) OR (n11Oi1ii XOR n11O0liO)) OR (n11Oi1il XOR n11O0lli)) OR (n11Oi1iO XOR n11O0lll)) OR (n11Oi1li XOR n11O0llO)) OR (n11Oi1ll XOR n11O0lOi)) OR (n11Oi1lO XOR n11O0lOl)) OR (n11Oi1Oi XOR n11O0lOO)) OR (n11Oi1Ol XOR n11O0O1i)) OR (n11Oi1OO XOR n11O0O1l)) OR (n11Oi01i XOR n11O0O1O)) OR (n11Oi01l XOR n11O0O0i)) OR (n11Oi01O XOR n11O0O0l)) OR (n11Oi00i XOR n11O0O0O)) OR (n11Oi00l XOR n11O0Oii)) OR (n11Oi00O XOR n11O0Oil)); + niOlO1O0l <= (n0OiOO0O AND n0OiOO0i); + niOlO1O0O <= (niOlO1OOl AND (wire_niO01ill_w_lg_n0OiOO0l11848w(0) AND niOlO1O0l)); + niOlO1O1i <= (n0OiOOil AND (niOlO1Oli OR niOlO1OiO)); + niOlO1O1l <= (niOlO1O0i OR (NOT (wire_niO11i1l_dataout AND niOlO1O1O))); + niOlO1O1O <= ((((((((wire_niO11i1O_w_lg_dataout11800w(0) AND wire_n0O01O1i_w_lg_dataout12185w(0)) AND wire_n0O01lOl_w_lg_dataout12187w(0)) AND wire_n0O01llO_w_lg_dataout12189w(0)) AND wire_n0O01lli_w_lg_dataout12191w(0)) AND wire_n0O01lil_w_lg_dataout12193w(0)) AND wire_n0O01l0l_w_lg_dataout12195w(0)) AND wire_n0O01l1O_w_lg_dataout12197w(0)) AND wire_n0O01iOO_w_lg_dataout12199w(0)); + niOlO1Oii <= (niOlO1OOl AND (n0OiOO0l AND (n0OiOO0O AND wire_niO01ill_w_lg_n0OiOO0i11843w(0)))); + niOlO1Oil <= (niOlO1OOl AND n0OiOO1O); + niOlO1OiO <= (wire_niO11i1O_w_lg_dataout11800w(0) AND wire_niO11i1l_dataout); + niOlO1Oli <= (wire_niO11i1l_dataout AND niOlO1Oll); + niOlO1Oll <= (((((wire_niO11ill_w_lg_w_lg_w_lg_dataout12176w12177w12178w(0) AND wire_niO11iii_w_lg_dataout12179w(0)) AND wire_niO11i0O_dataout) AND wire_niO11i0l_dataout) AND wire_niO11i0i_dataout) AND wire_niO11i1O_dataout); + niOlO1OlO <= (wire_niO11i1l_dataout AND niOlO1OOi); + niOlO1OOi <= (((wire_niO11ill_w_lg_w_lg_w12170w12171w12172w(0) AND wire_niO11i0l_w_lg_dataout12153w(0)) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_dataout); + niOlO1OOl <= (wire_niO11i1l_dataout AND niOlO1OOO); + niOlO1OOO <= (((wire_niO11ill_w_lg_w_lg_w12161w12162w12163w(0) AND wire_niO11i0l_w_lg_dataout12153w(0)) AND wire_niO11i0i_w_lg_dataout12155w(0)) AND wire_niO11i1O_dataout); + niOlOi00i <= (wire_w_lg_niOlOO01l11178w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11221w(0) OR (niOlOl0Ol AND niOlOi00l))); + niOlOi00l <= (wire_niO01ill_w_lg_ni1iOO1O11239w(0) AND ni1iOO1i); + niOlOi00O <= (wire_w_lg_niOlOO01l11178w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11217w(0) OR (niOlOl0Ol AND niOlOi0ii))); + niOlOi01i <= (wire_w_lg_niOlOO01l11178w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11229w(0) OR (niOlOl0Ol AND niOlOi0Ol))); + niOlOi01l <= (wire_w_lg_niOlOO01l11178w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11225w(0) OR (niOlOl0Ol AND niOlOi01O))); + niOlOi01O <= ((ni1iOO1O AND ni1iOO1l) AND wire_niO01ill_w_lg_ni1iOO1i11203w(0)); + niOlOi0ii <= (wire_niO01ill_w_lg_ni1iOO1O11239w(0) AND wire_niO01ill_w_lg_ni1iOO1i11203w(0)); + niOlOi0il <= (wire_w_lg_niOlOO01l11178w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11213w(0) OR (niOlOl0Ol AND niOlOi0iO))); + niOlOi0iO <= (wire_niO01ill_w_lg_w_lg_ni1iOO1O11200w11236w(0) AND ni1iOO1i); + niOlOi0li <= (wire_w_lg_niOlOO01l11178w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11209w(0) OR (niOlOl0Ol AND niOlOi0ll))); + niOlOi0ll <= (wire_niO01ill_w_lg_w_lg_ni1iOO1O11200w11236w(0) AND wire_niO01ill_w_lg_ni1iOO1i11203w(0)); + niOlOi0lO <= (wire_w_lg_niOlOO01l11178w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni1iOO1O11200w(0) AND wire_niO01ill_w_lg_ni1iOO1l11201w(0)) AND wire_niO01ill_w_lg_ni1iOO1i11203w(0))) OR (niOlOl0Ol AND niOlOi0OO))); + niOlOi0Oi <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOO01l11178w11198w(0)); + niOlOi0Ol <= ((ni1iOO1O AND ni1iOO1l) AND ni1iOO1i); + niOlOi0OO <= ((wire_niO01ill_w_lg_ni1iOO1O11200w(0) AND wire_niO01ill_w_lg_ni1iOO1l11201w(0)) AND ni1iOO1i); + niOlOi10i <= (wire_w_lg_niOlOO0ll11259w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11298w(0) OR (niOlOl0Ol AND niOlOi10l))); + niOlOi10l <= (wire_niO01ill_w_lg_ni1i11ll11320w(0) AND wire_niO01ill_w_lg_ni1i11iO11284w(0)); + niOlOi10O <= (wire_w_lg_niOlOO0ll11259w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11294w(0) OR (niOlOl0Ol AND niOlOi1ii))); + niOlOi11i <= ((ni1i11ll AND ni1i11li) AND wire_niO01ill_w_lg_ni1i11iO11284w(0)); + niOlOi11l <= (wire_w_lg_niOlOO0ll11259w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11302w(0) OR (niOlOl0Ol AND niOlOi11O))); + niOlOi11O <= (wire_niO01ill_w_lg_ni1i11ll11320w(0) AND ni1i11iO); + niOlOi1ii <= (wire_niO01ill_w_lg_w_lg_ni1i11ll11281w11317w(0) AND ni1i11iO); + niOlOi1il <= (wire_w_lg_niOlOO0ll11259w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11290w(0) OR (niOlOl0Ol AND niOlOi1iO))); + niOlOi1iO <= (wire_niO01ill_w_lg_w_lg_ni1i11ll11281w11317w(0) AND wire_niO01ill_w_lg_ni1i11iO11284w(0)); + niOlOi1li <= (wire_w_lg_niOlOO0ll11259w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni1i11ll11281w(0) AND wire_niO01ill_w_lg_ni1i11li11282w(0)) AND wire_niO01ill_w_lg_ni1i11iO11284w(0))) OR (niOlOl0Ol AND niOlOi1Oi))); + niOlOi1ll <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOO0ll11259w11279w(0)); + niOlOi1lO <= ((ni1i11ll AND ni1i11li) AND ni1i11iO); + niOlOi1Oi <= ((wire_niO01ill_w_lg_ni1i11ll11281w(0) AND wire_niO01ill_w_lg_ni1i11li11282w(0)) AND ni1i11iO); + niOlOi1Ol <= (wire_w_lg_niOlOO0ll11259w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOi1OO <= (niOlOO0ll AND niOlOl0Ol); + niOlOii0i <= (wire_w_lg_niOlOO1il11097w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11144w(0) OR (niOlOl0Ol AND niOlOii0l))); + niOlOii0l <= ((ni1lOili AND ni1lOiiO) AND wire_niO01ill_w_lg_ni1lOiil11122w(0)); + niOlOii0O <= (wire_w_lg_niOlOO1il11097w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11140w(0) OR (niOlOl0Ol AND niOlOiiii))); + niOlOii1i <= (wire_w_lg_niOlOO01l11178w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOii1l <= (niOlOO01l AND niOlOl0Ol); + niOlOii1O <= (wire_w_lg_niOlOO1il11097w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11148w(0) OR (niOlOl0Ol AND niOlOil1i))); + niOlOiiii <= (wire_niO01ill_w_lg_ni1lOili11158w(0) AND ni1lOiil); + niOlOiiil <= (wire_w_lg_niOlOO1il11097w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11136w(0) OR (niOlOl0Ol AND niOlOiiiO))); + niOlOiiiO <= (wire_niO01ill_w_lg_ni1lOili11158w(0) AND wire_niO01ill_w_lg_ni1lOiil11122w(0)); + niOlOiili <= (wire_w_lg_niOlOO1il11097w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11132w(0) OR (niOlOl0Ol AND niOlOiill))); + niOlOiill <= (wire_niO01ill_w_lg_w_lg_ni1lOili11119w11155w(0) AND ni1lOiil); + niOlOiilO <= (wire_w_lg_niOlOO1il11097w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11128w(0) OR (niOlOl0Ol AND niOlOiiOi))); + niOlOiiOi <= (wire_niO01ill_w_lg_w_lg_ni1lOili11119w11155w(0) AND wire_niO01ill_w_lg_ni1lOiil11122w(0)); + niOlOiiOl <= (wire_w_lg_niOlOO1il11097w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni1lOili11119w(0) AND wire_niO01ill_w_lg_ni1lOiiO11120w(0)) AND wire_niO01ill_w_lg_ni1lOiil11122w(0))) OR (niOlOl0Ol AND niOlOil1l))); + niOlOiiOO <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOO1il11097w11117w(0)); + niOlOil0i <= (niOlOO1il AND niOlOl0Ol); + niOlOil0l <= (wire_w_lg_niOlOlOOl11016w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11067w(0) OR (niOlOl0Ol AND niOlOiO1O))); + niOlOil0O <= (wire_w_lg_niOlOlOOl11016w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11063w(0) OR (niOlOl0Ol AND niOlOilii))); + niOlOil1i <= ((ni1lOili AND ni1lOiiO) AND ni1lOiil); + niOlOil1l <= ((wire_niO01ill_w_lg_ni1lOili11119w(0) AND wire_niO01ill_w_lg_ni1lOiiO11120w(0)) AND ni1lOiil); + niOlOil1O <= (wire_w_lg_niOlOO1il11097w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOilii <= ((ni1OO01l AND ni1OO01i) AND wire_niO01ill_w_lg_ni1OO1OO11041w(0)); + niOlOilil <= (wire_w_lg_niOlOlOOl11016w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11059w(0) OR (niOlOl0Ol AND niOlOiliO))); + niOlOiliO <= (wire_niO01ill_w_lg_ni1OO01l11077w(0) AND ni1OO1OO); + niOlOilli <= (wire_w_lg_niOlOlOOl11016w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11055w(0) OR (niOlOl0Ol AND niOlOilll))); + niOlOilll <= (wire_niO01ill_w_lg_ni1OO01l11077w(0) AND wire_niO01ill_w_lg_ni1OO1OO11041w(0)); + niOlOillO <= (wire_w_lg_niOlOlOOl11016w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11051w(0) OR (niOlOl0Ol AND niOlOilOi))); + niOlOilOi <= (wire_niO01ill_w_lg_w_lg_ni1OO01l11038w11074w(0) AND ni1OO1OO); + niOlOilOl <= (wire_w_lg_niOlOlOOl11016w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w11047w(0) OR (niOlOl0Ol AND niOlOilOO))); + niOlOilOO <= (wire_niO01ill_w_lg_w_lg_ni1OO01l11038w11074w(0) AND wire_niO01ill_w_lg_ni1OO1OO11041w(0)); + niOlOiO0i <= ((wire_niO01ill_w_lg_ni1OO01l11038w(0) AND wire_niO01ill_w_lg_ni1OO01i11039w(0)) AND ni1OO1OO); + niOlOiO0l <= (wire_w_lg_niOlOlOOl11016w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOiO0O <= (niOlOlOOl AND niOlOl0Ol); + niOlOiO1i <= (wire_w_lg_niOlOlOOl11016w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni1OO01l11038w(0) AND wire_niO01ill_w_lg_ni1OO01i11039w(0)) AND wire_niO01ill_w_lg_ni1OO1OO11041w(0))) OR (niOlOl0Ol AND niOlOiO0i))); + niOlOiO1l <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOlOOl11016w11036w(0)); + niOlOiO1O <= ((ni1OO01l AND ni1OO01i) AND ni1OO1OO); + niOlOiOii <= (wire_w_lg_niOlOlO0l10935w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10986w(0) OR (niOlOl0Ol AND niOlOl10l))); + niOlOiOil <= (wire_w_lg_niOlOlO0l10935w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10982w(0) OR (niOlOl0Ol AND niOlOiOiO))); + niOlOiOiO <= ((ni01lOiO AND ni01lOil) AND wire_niO01ill_w_lg_ni01lOii10960w(0)); + niOlOiOli <= (wire_w_lg_niOlOlO0l10935w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10978w(0) OR (niOlOl0Ol AND niOlOiOll))); + niOlOiOll <= (wire_niO01ill_w_lg_ni01lOiO10996w(0) AND ni01lOii); + niOlOiOlO <= (wire_w_lg_niOlOlO0l10935w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10974w(0) OR (niOlOl0Ol AND niOlOiOOi))); + niOlOiOOi <= (wire_niO01ill_w_lg_ni01lOiO10996w(0) AND wire_niO01ill_w_lg_ni01lOii10960w(0)); + niOlOiOOl <= (wire_w_lg_niOlOlO0l10935w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10970w(0) OR (niOlOl0Ol AND niOlOiOOO))); + niOlOiOOO <= (wire_niO01ill_w_lg_w_lg_ni01lOiO10957w10993w(0) AND ni01lOii); + niOlOl00i <= (wire_niO01ill_w_lg_w_lg_ni00ll1i10876w10912w(0) AND wire_niO01ill_w_lg_ni00liOl10879w(0)); + niOlOl00l <= (wire_w_lg_niOlOllll10854w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni00ll1i10876w(0) AND wire_niO01ill_w_lg_ni00liOO10877w(0)) AND wire_niO01ill_w_lg_ni00liOl10879w(0))) OR (niOlOl0Ol AND niOlOl0il))); + niOlOl00O <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOllll10854w10874w(0)); + niOlOl01i <= (wire_w_lg_niOlOllll10854w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10889w(0) OR (niOlOl0Ol AND niOlOl01l))); + niOlOl01l <= (wire_niO01ill_w_lg_w_lg_ni00ll1i10876w10912w(0) AND ni00liOl); + niOlOl01O <= (wire_w_lg_niOlOllll10854w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10885w(0) OR (niOlOl0Ol AND niOlOl00i))); + niOlOl0ii <= ((ni00ll1i AND ni00liOO) AND ni00liOl); + niOlOl0il <= ((wire_niO01ill_w_lg_ni00ll1i10876w(0) AND wire_niO01ill_w_lg_ni00liOO10877w(0)) AND ni00liOl); + niOlOl0iO <= (wire_w_lg_niOlOllll10854w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOl0li <= (niOlOllll AND niOlOl0Ol); + niOlOl0ll <= ((niOlOli1i AND niOlOl0lO) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOl0lO <= (((((((wire_niO01ill_w_lg_ni111liO10174w(0) AND wire_niO01ill_w_lg_ni101i1i10177w(0)) AND wire_niO01ill_w_lg_ni1i11il10181w(0)) AND wire_niO01ill_w_lg_ni1iOlOO10185w(0)) AND wire_niO01ill_w_lg_ni1lOiii10189w(0)) AND wire_niO01ill_w_lg_ni1OO1Ol10193w(0)) AND wire_niO01ill_w_lg_ni01lO0O10197w(0)) AND wire_niO01ill_w_lg_ni00liOi10201w(0)); + niOlOl0Oi <= ((niOlOli1i AND niOlOl0OO) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOl0Ol <= ((((((((NOT (n111i1OO AND wire_niO01ill_w_lg_ni111liO10174w(0))) AND (NOT (n111i01i AND wire_niO01ill_w_lg_ni101i1i10177w(0)))) AND (NOT (n111i01l AND wire_niO01ill_w_lg_ni1i11il10181w(0)))) AND (NOT (n111i01O AND wire_niO01ill_w_lg_ni1iOlOO10185w(0)))) AND (NOT (n111i00i AND wire_niO01ill_w_lg_ni1lOiii10189w(0)))) AND (NOT (n111i00l AND wire_niO01ill_w_lg_ni1OO1Ol10193w(0)))) AND (NOT (n111i00O AND wire_niO01ill_w_lg_ni01lO0O10197w(0)))) AND (NOT (n111i0ii AND wire_niO01ill_w_lg_ni00liOi10201w(0)))); + niOlOl0OO <= (((((((wire_w_lg_niOlOliiO10815w(0) AND wire_w_lg_niOlOliil10816w(0)) AND wire_w_lg_niOlOliii10818w(0)) AND wire_w_lg_niOlOli0O10820w(0)) AND wire_w_lg_niOlOli0l10822w(0)) AND wire_w_lg_niOlOli0i10824w(0)) AND wire_w_lg_niOlOli1O10826w(0)) AND wire_w_lg_niOlOli1l10828w(0)); + niOlOl10i <= (wire_w_lg_niOlOl0Ol10165w(0) AND wire_w_lg_w_lg_niOlOlO0l10935w10955w(0)); + niOlOl10l <= ((ni01lOiO AND ni01lOil) AND ni01lOii); + niOlOl10O <= ((wire_niO01ill_w_lg_ni01lOiO10957w(0) AND wire_niO01ill_w_lg_ni01lOil10958w(0)) AND ni01lOii); + niOlOl11i <= (wire_w_lg_niOlOlO0l10935w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10966w(0) OR (niOlOl0Ol AND niOlOl11l))); + niOlOl11l <= (wire_niO01ill_w_lg_w_lg_ni01lOiO10957w10993w(0) AND wire_niO01ill_w_lg_ni01lOii10960w(0)); + niOlOl11O <= (wire_w_lg_niOlOlO0l10935w(0) AND ((wire_w_lg_niOlOl0Ol10165w(0) AND ((wire_niO01ill_w_lg_ni01lOiO10957w(0) AND wire_niO01ill_w_lg_ni01lOil10958w(0)) AND wire_niO01ill_w_lg_ni01lOii10960w(0))) OR (niOlOl0Ol AND niOlOl10O))); + niOlOl1ii <= (wire_w_lg_niOlOlO0l10935w(0) AND wire_w_lg_niOlOl0Ol10165w(0)); + niOlOl1il <= (niOlOlO0l AND niOlOl0Ol); + niOlOl1iO <= (wire_w_lg_niOlOllll10854w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10905w(0) OR (niOlOl0Ol AND niOlOl0ii))); + niOlOl1li <= (wire_w_lg_niOlOllll10854w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10901w(0) OR (niOlOl0Ol AND niOlOl1ll))); + niOlOl1ll <= ((ni00ll1i AND ni00liOO) AND wire_niO01ill_w_lg_ni00liOl10879w(0)); + niOlOl1lO <= (wire_w_lg_niOlOllll10854w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10897w(0) OR (niOlOl0Ol AND niOlOl1Oi))); + niOlOl1Oi <= (wire_niO01ill_w_lg_ni00ll1i10915w(0) AND ni00liOl); + niOlOl1Ol <= (wire_w_lg_niOlOllll10854w(0) AND (wire_w_lg_w_lg_niOlOl0Ol10165w10893w(0) OR (niOlOl0Ol AND niOlOl1OO))); + niOlOl1OO <= (wire_niO01ill_w_lg_ni00ll1i10915w(0) AND wire_niO01ill_w_lg_ni00liOl10879w(0)); + niOlOli0i <= (n111i00l AND nii0lllO); + niOlOli0l <= (n111i00i AND nii0O1ii); + niOlOli0O <= (n111i01O AND nii0Oi1l); + niOlOli1i <= (ni0i111O AND wire_w_lg_niOlOll0l10155w(0)); + niOlOli1l <= (n111i0ii AND ni0i0i0O); + niOlOli1O <= (n111i00O AND nii0li1l); + niOlOliii <= (n111i01l AND nii0OllO); + niOlOliil <= (n111i01i AND niii11ii); + niOlOliiO <= (n111i1OO AND niii1i1l); + niOlOlili <= ((ni0i0i0l AND ni0i0i0i) AND ni0i0i1O); + niOlOlill <= ((ni0i0i0l AND ni0i0i0i) AND wire_niO01ill_w_lg_ni0i0i1O10661w(0)); + niOlOlilO <= (wire_niO01ill_w_lg_ni0i0i0l10812w(0) AND ni0i0i1O); + niOlOliOi <= (wire_niO01ill_w_lg_ni0i0i0l10812w(0) AND wire_niO01ill_w_lg_ni0i0i1O10661w(0)); + niOlOliOl <= (((((((wire_niO01ill_w_lg_ni0i1iOi10794w(0) AND wire_niO01ill_w_lg_ni0i1ilO10795w(0)) AND wire_niO01ill_w_lg_ni0i1ill10797w(0)) AND wire_niO01ill_w_lg_ni0i1ili10799w(0)) AND wire_niO01ill_w_lg_ni0i1iiO10801w(0)) AND wire_niO01ill_w_lg_ni0i1iil10803w(0)) AND wire_niO01ill_w_lg_ni0i1iii10805w(0)) AND wire_niO01ill_w_lg_ni0i1i0O10807w(0)); + niOlOliOO <= ((((((((((((wire_w_lg_w_ni00O11O10767w10769w(0) AND wire_niO01ill_w_lg_ni0i1lli10770w(0)) AND wire_niO01ill_w_lg_ni0i1liO10772w(0)) AND wire_niO01ill_w_lg_ni0i1lil10774w(0)) AND wire_niO01ill_w_lg_ni0i1lii10776w(0)) AND wire_niO01ill_w_lg_ni0i1l0O10778w(0)) AND wire_niO01ill_w_lg_ni0i1l0l10780w(0)) AND wire_niO01ill_w_lg_ni0i1l0i10782w(0)) AND wire_niO01ill_w_lg_ni0i1l1O10784w(0)) AND wire_niO01ill_w_lg_ni0i1l1l10786w(0)) AND wire_niO01ill_w_lg_ni0i1l1i10788w(0)) AND wire_niO01ill_w_lg_ni0i1iOO10790w(0)) AND wire_niO01ill_w_lg_ni0i1iOl10792w(0)); + niOlOll0i <= ((wire_niO01ill_w_lg_ni0i0i0l10658w(0) AND wire_niO01ill_w_lg_ni0i0i0i10663w(0)) AND ni0i0i1O); + niOlOll0l <= ((wire_niO01ill_w_lg_ni0i0i0l10658w(0) AND wire_niO01ill_w_lg_ni0i0i0i10663w(0)) AND wire_niO01ill_w_lg_ni0i0i1O10661w(0)); + niOlOll0O <= (niOlOllil OR niOlOllii); + niOlOll1i <= (niOlOliOO AND niOlOliOl); + niOlOll1l <= (wire_niO01ill_w_lg_w_lg_ni0i0i0l10658w10659w(0) AND ni0i0i1O); + niOlOll1O <= (wire_niO01ill_w_lg_w_lg_ni0i0i0l10658w10659w(0) AND wire_niO01ill_w_lg_ni0i0i1O10661w(0)); + niOlOllii <= ((wire_niO01ill_w_lg_w_lg_w10651w10652w10653w(0) AND wire_niO01ill_w_lg_ni1111Ol10654w(0)) AND wire_niO01ill_w_lg_n0OOOllO10656w(0)); + niOlOllil <= (((wire_niO01ill_w_lg_w10640w10641w(0) AND wire_niO01ill_w_lg_ni1111OO10642w(0)) AND ni1111Ol) AND n0OOOllO); + niOlOlliO <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10608w10609w10610w(0) AND wire_niO01ill_w_lg_niiii11l10631w(0)) AND niiii11i) AND niii0OOO) AND niii0OOl) AND niii0i1l); + niOlOllli <= (n111i10O AND wire_niO01ill_w_lg_ni0i0i0O10123w(0)); + niOlOllll <= ((((((wire_niO01ill_w_lg_w_lg_niiiiOli10024w10122w(0) OR wire_niO01ill_w_lg_ni0i0i0O10123w(0)) OR niOlOlO1i) OR niOlOllOO) OR niOlOllOl) OR niOlOllOi) OR niOlOlllO); + niOlOlllO <= (((wire_niO01ill_w_lg_w_lg_w10625w10626w10627w(0) AND wire_niO01ill_w_lg_niii0OOO10593w(0)) AND wire_niO01ill_w_lg_niii0OOl10595w(0)) AND niii0i1l); + niOlOllOi <= (((wire_niO01ill_w_lg_w_lg_w10617w10618w10619w(0) AND wire_niO01ill_w_lg_niii0OOO10593w(0)) AND wire_niO01ill_w_lg_niii0OOl10595w(0)) AND niii0i1l); + niOlOllOl <= (((wire_niO01ill_w_lg_w10611w10612w(0) AND wire_niO01ill_w_lg_niii0OOO10593w(0)) AND wire_niO01ill_w_lg_niii0OOl10595w(0)) AND niii0i1l); + niOlOllOO <= (((wire_niO01ill_w_lg_w_lg_w10602w10603w10604w(0) AND wire_niO01ill_w_lg_niii0OOO10593w(0)) AND wire_niO01ill_w_lg_niii0OOl10595w(0)) AND niii0i1l); + niOlOlO0i <= (n111i10O AND wire_niO01ill_w_lg_nii0li1l10110w(0)); + niOlOlO0l <= ((((((wire_niO01ill_w_lg_w_lg_niiiiOll10022w10109w(0) OR wire_niO01ill_w_lg_nii0li1l10110w(0)) OR niOlOlOli) OR niOlOlOiO) OR niOlOlOil) OR niOlOlOii) OR niOlOlO0O); + niOlOlO0O <= (((wire_niO01ill_w_lg_w_lg_w10575w10576w10577w(0) AND wire_niO01ill_w_lg_niiii1iO10543w(0)) AND wire_niO01ill_w_lg_niiii1il10545w(0)) AND niiii1ii); + niOlOlO1i <= (((wire_niO01ill_w_lg_w10591w10592w(0) AND wire_niO01ill_w_lg_niii0OOO10593w(0)) AND wire_niO01ill_w_lg_niii0OOl10595w(0)) AND niii0i1l); + niOlOlO1l <= (((wire_niO01ill_w_lg_w10591w10592w(0) AND wire_niO01ill_w_lg_niii0OOO10593w(0)) AND wire_niO01ill_w_lg_niii0OOl10595w(0)) AND niii0i1l); + niOlOlO1O <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10558w10559w10560w(0) AND wire_niO01ill_w_lg_niiii1ll10581w(0)) AND niiii1li) AND niiii1iO) AND niiii1il) AND niiii1ii); + niOlOlOii <= (((wire_niO01ill_w_lg_w_lg_w10567w10568w10569w(0) AND wire_niO01ill_w_lg_niiii1iO10543w(0)) AND wire_niO01ill_w_lg_niiii1il10545w(0)) AND niiii1ii); + niOlOlOil <= (((wire_niO01ill_w_lg_w10561w10562w(0) AND wire_niO01ill_w_lg_niiii1iO10543w(0)) AND wire_niO01ill_w_lg_niiii1il10545w(0)) AND niiii1ii); + niOlOlOiO <= (((wire_niO01ill_w_lg_w_lg_w10552w10553w10554w(0) AND wire_niO01ill_w_lg_niiii1iO10543w(0)) AND wire_niO01ill_w_lg_niiii1il10545w(0)) AND niiii1ii); + niOlOlOli <= (((wire_niO01ill_w_lg_w10541w10542w(0) AND wire_niO01ill_w_lg_niiii1iO10543w(0)) AND wire_niO01ill_w_lg_niiii1il10545w(0)) AND niiii1ii); + niOlOlOll <= (((wire_niO01ill_w_lg_w10541w10542w(0) AND wire_niO01ill_w_lg_niiii1iO10543w(0)) AND wire_niO01ill_w_lg_niiii1il10545w(0)) AND niiii1ii); + niOlOlOlO <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10508w10509w10510w(0) AND wire_niO01ill_w_lg_niiii00l10531w(0)) AND niiii00i) AND niiii01O) AND niiii01l) AND niiii01i); + niOlOlOOi <= (n111i10O AND wire_niO01ill_w_lg_nii0lllO10097w(0)); + niOlOlOOl <= ((((((wire_niO01ill_w_lg_w_lg_niiiiOlO10020w10096w(0) OR wire_niO01ill_w_lg_nii0lllO10097w(0)) OR niOlOO10i) OR niOlOO11O) OR niOlOO11l) OR niOlOO11i) OR niOlOlOOO); + niOlOlOOO <= (((wire_niO01ill_w_lg_w_lg_w10525w10526w10527w(0) AND wire_niO01ill_w_lg_niiii01O10493w(0)) AND wire_niO01ill_w_lg_niiii01l10495w(0)) AND niiii01i); + niOlOO00i <= (((wire_niO01ill_w_lg_w_lg_w10417w10418w10419w(0) AND wire_niO01ill_w_lg_niiiii0O10393w(0)) AND wire_niO01ill_w_lg_niiiii0l10395w(0)) AND niiiii0i); + niOlOO00l <= (((wire_niO01ill_w_lg_w10411w10412w(0) AND wire_niO01ill_w_lg_niiiii0O10393w(0)) AND wire_niO01ill_w_lg_niiiii0l10395w(0)) AND niiiii0i); + niOlOO00O <= (((wire_niO01ill_w_lg_w_lg_w10402w10403w10404w(0) AND wire_niO01ill_w_lg_niiiii0O10393w(0)) AND wire_niO01ill_w_lg_niiiii0l10395w(0)) AND niiiii0i); + niOlOO01i <= (n111i10O AND wire_niO01ill_w_lg_nii0Oi1l10071w(0)); + niOlOO01l <= ((((((wire_niO01ill_w_lg_w_lg_niiiiOOl10016w10070w(0) OR wire_niO01ill_w_lg_nii0Oi1l10071w(0)) OR niOlOO0ii) OR niOlOO00O) OR niOlOO00l) OR niOlOO00i) OR niOlOO01O); + niOlOO01O <= (((wire_niO01ill_w_lg_w_lg_w10425w10426w10427w(0) AND wire_niO01ill_w_lg_niiiii0O10393w(0)) AND wire_niO01ill_w_lg_niiiii0l10395w(0)) AND niiiii0i); + niOlOO0ii <= (((wire_niO01ill_w_lg_w10391w10392w(0) AND wire_niO01ill_w_lg_niiiii0O10393w(0)) AND wire_niO01ill_w_lg_niiiii0l10395w(0)) AND niiiii0i); + niOlOO0il <= (((wire_niO01ill_w_lg_w10391w10392w(0) AND wire_niO01ill_w_lg_niiiii0O10393w(0)) AND wire_niO01ill_w_lg_niiiii0l10395w(0)) AND niiiii0i); + niOlOO0iO <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10358w10359w10360w(0) AND wire_niO01ill_w_lg_niiiil1l10381w(0)) AND niiiil1i) AND niiiiiOO) AND niiiiiOl) AND niiiiiOi); + niOlOO0li <= (n111i10O AND wire_niO01ill_w_lg_nii0OllO10058w(0)); + niOlOO0ll <= ((((((wire_niO01ill_w_lg_w_lg_niiiiOOO10014w10057w(0) OR wire_niO01ill_w_lg_nii0OllO10058w(0)) OR niOlOOi1i) OR niOlOO0OO) OR niOlOO0Ol) OR niOlOO0Oi) OR niOlOO0lO); + niOlOO0lO <= (((wire_niO01ill_w_lg_w_lg_w10375w10376w10377w(0) AND wire_niO01ill_w_lg_niiiiiOO10343w(0)) AND wire_niO01ill_w_lg_niiiiiOl10345w(0)) AND niiiiiOi); + niOlOO0Oi <= (((wire_niO01ill_w_lg_w_lg_w10367w10368w10369w(0) AND wire_niO01ill_w_lg_niiiiiOO10343w(0)) AND wire_niO01ill_w_lg_niiiiiOl10345w(0)) AND niiiiiOi); + niOlOO0Ol <= (((wire_niO01ill_w_lg_w10361w10362w(0) AND wire_niO01ill_w_lg_niiiiiOO10343w(0)) AND wire_niO01ill_w_lg_niiiiiOl10345w(0)) AND niiiiiOi); + niOlOO0OO <= (((wire_niO01ill_w_lg_w_lg_w10352w10353w10354w(0) AND wire_niO01ill_w_lg_niiiiiOO10343w(0)) AND wire_niO01ill_w_lg_niiiiiOl10345w(0)) AND niiiiiOi); + niOlOO10i <= (((wire_niO01ill_w_lg_w10491w10492w(0) AND wire_niO01ill_w_lg_niiii01O10493w(0)) AND wire_niO01ill_w_lg_niiii01l10495w(0)) AND niiii01i); + niOlOO10l <= (((wire_niO01ill_w_lg_w10491w10492w(0) AND wire_niO01ill_w_lg_niiii01O10493w(0)) AND wire_niO01ill_w_lg_niiii01l10495w(0)) AND niiii01i); + niOlOO10O <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10458w10459w10460w(0) AND wire_niO01ill_w_lg_niiii0Ol10481w(0)) AND niiii0Oi) AND niiii0lO) AND niiii0ll) AND niiii0li); + niOlOO11i <= (((wire_niO01ill_w_lg_w_lg_w10517w10518w10519w(0) AND wire_niO01ill_w_lg_niiii01O10493w(0)) AND wire_niO01ill_w_lg_niiii01l10495w(0)) AND niiii01i); + niOlOO11l <= (((wire_niO01ill_w_lg_w10511w10512w(0) AND wire_niO01ill_w_lg_niiii01O10493w(0)) AND wire_niO01ill_w_lg_niiii01l10495w(0)) AND niiii01i); + niOlOO11O <= (((wire_niO01ill_w_lg_w_lg_w10502w10503w10504w(0) AND wire_niO01ill_w_lg_niiii01O10493w(0)) AND wire_niO01ill_w_lg_niiii01l10495w(0)) AND niiii01i); + niOlOO1ii <= (n111i10O AND wire_niO01ill_w_lg_nii0O1ii10084w(0)); + niOlOO1il <= ((((((wire_niO01ill_w_lg_w_lg_niiiiOOi10018w10083w(0) OR wire_niO01ill_w_lg_nii0O1ii10084w(0)) OR niOlOO1Oi) OR niOlOO1lO) OR niOlOO1ll) OR niOlOO1li) OR niOlOO1iO); + niOlOO1iO <= (((wire_niO01ill_w_lg_w_lg_w10475w10476w10477w(0) AND wire_niO01ill_w_lg_niiii0lO10443w(0)) AND wire_niO01ill_w_lg_niiii0ll10445w(0)) AND niiii0li); + niOlOO1li <= (((wire_niO01ill_w_lg_w_lg_w10467w10468w10469w(0) AND wire_niO01ill_w_lg_niiii0lO10443w(0)) AND wire_niO01ill_w_lg_niiii0ll10445w(0)) AND niiii0li); + niOlOO1ll <= (((wire_niO01ill_w_lg_w10461w10462w(0) AND wire_niO01ill_w_lg_niiii0lO10443w(0)) AND wire_niO01ill_w_lg_niiii0ll10445w(0)) AND niiii0li); + niOlOO1lO <= (((wire_niO01ill_w_lg_w_lg_w10452w10453w10454w(0) AND wire_niO01ill_w_lg_niiii0lO10443w(0)) AND wire_niO01ill_w_lg_niiii0ll10445w(0)) AND niiii0li); + niOlOO1Oi <= (((wire_niO01ill_w_lg_w10441w10442w(0) AND wire_niO01ill_w_lg_niiii0lO10443w(0)) AND wire_niO01ill_w_lg_niiii0ll10445w(0)) AND niiii0li); + niOlOO1Ol <= (((wire_niO01ill_w_lg_w10441w10442w(0) AND wire_niO01ill_w_lg_niiii0lO10443w(0)) AND wire_niO01ill_w_lg_niiii0ll10445w(0)) AND niiii0li); + niOlOO1OO <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10408w10409w10410w(0) AND wire_niO01ill_w_lg_niiiiiil10431w(0)) AND niiiiiii) AND niiiii0O) AND niiiii0l) AND niiiii0i); + niOlOOi0i <= (n111i10O AND wire_niO01ill_w_lg_niii11ii10045w(0)); + niOlOOi0l <= ((((((wire_niO01ill_w_lg_w_lg_niiil11i10012w10044w(0) OR wire_niO01ill_w_lg_niii11ii10045w(0)) OR niOlOOili) OR niOlOOiiO) OR niOlOOiil) OR niOlOOiii) OR niOlOOi0O); + niOlOOi0O <= (((wire_niO01ill_w_lg_w_lg_w10325w10326w10327w(0) AND wire_niO01ill_w_lg_niiiiliO10293w(0)) AND wire_niO01ill_w_lg_niiiilil10295w(0)) AND niiiilii); + niOlOOi1i <= (((wire_niO01ill_w_lg_w10341w10342w(0) AND wire_niO01ill_w_lg_niiiiiOO10343w(0)) AND wire_niO01ill_w_lg_niiiiiOl10345w(0)) AND niiiiiOi); + niOlOOi1l <= (((wire_niO01ill_w_lg_w10341w10342w(0) AND wire_niO01ill_w_lg_niiiiiOO10343w(0)) AND wire_niO01ill_w_lg_niiiiiOl10345w(0)) AND niiiiiOi); + niOlOOi1O <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10308w10309w10310w(0) AND wire_niO01ill_w_lg_niiiilll10331w(0)) AND niiiilli) AND niiiiliO) AND niiiilil) AND niiiilii); + niOlOOiii <= (((wire_niO01ill_w_lg_w_lg_w10317w10318w10319w(0) AND wire_niO01ill_w_lg_niiiiliO10293w(0)) AND wire_niO01ill_w_lg_niiiilil10295w(0)) AND niiiilii); + niOlOOiil <= (((wire_niO01ill_w_lg_w10311w10312w(0) AND wire_niO01ill_w_lg_niiiiliO10293w(0)) AND wire_niO01ill_w_lg_niiiilil10295w(0)) AND niiiilii); + niOlOOiiO <= (((wire_niO01ill_w_lg_w_lg_w10302w10303w10304w(0) AND wire_niO01ill_w_lg_niiiiliO10293w(0)) AND wire_niO01ill_w_lg_niiiilil10295w(0)) AND niiiilii); + niOlOOili <= (((wire_niO01ill_w_lg_w10291w10292w(0) AND wire_niO01ill_w_lg_niiiiliO10293w(0)) AND wire_niO01ill_w_lg_niiiilil10295w(0)) AND niiiilii); + niOlOOill <= (((wire_niO01ill_w_lg_w10291w10292w(0) AND wire_niO01ill_w_lg_niiiiliO10293w(0)) AND wire_niO01ill_w_lg_niiiilil10295w(0)) AND niiiilii); + niOlOOilO <= (((((wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10258w10259w10260w(0) AND wire_niO01ill_w_lg_niiiiO0l10281w(0)) AND niiiiO0i) AND niiiiO1O) AND niiiiO1l) AND niiiiO1i); + niOlOOiOi <= (n111i10O AND wire_niO01ill_w_lg_niii1i1l10032w(0)); + niOlOOiOl <= ((((((wire_niO01ill_w_lg_w_lg_niiil11l10010w10031w(0) OR wire_niO01ill_w_lg_niii1i1l10032w(0)) OR niOlOOl0i) OR niOlOOl1O) OR niOlOOl1l) OR niOlOOl1i) OR niOlOOiOO); + niOlOOiOO <= (((wire_niO01ill_w_lg_w_lg_w10275w10276w10277w(0) AND wire_niO01ill_w_lg_niiiiO1O10243w(0)) AND wire_niO01ill_w_lg_niiiiO1l10245w(0)) AND niiiiO1i); + niOlOOl0i <= (((wire_niO01ill_w_lg_w10241w10242w(0) AND wire_niO01ill_w_lg_niiiiO1O10243w(0)) AND wire_niO01ill_w_lg_niiiiO1l10245w(0)) AND niiiiO1i); + niOlOOl0l <= ((niii0i1i AND niii00OO) AND niii1OlO); + niOlOOl0O <= (((wire_niO01ill_w_lg_w10241w10242w(0) AND wire_niO01ill_w_lg_niiiiO1O10243w(0)) AND wire_niO01ill_w_lg_niiiiO1l10245w(0)) AND niiiiO1i); + niOlOOl1i <= (((wire_niO01ill_w_lg_w_lg_w10267w10268w10269w(0) AND wire_niO01ill_w_lg_niiiiO1O10243w(0)) AND wire_niO01ill_w_lg_niiiiO1l10245w(0)) AND niiiiO1i); + niOlOOl1l <= (((wire_niO01ill_w_lg_w10261w10262w(0) AND wire_niO01ill_w_lg_niiiiO1O10243w(0)) AND wire_niO01ill_w_lg_niiiiO1l10245w(0)) AND niiiiO1i); + niOlOOl1O <= (((wire_niO01ill_w_lg_w_lg_w10252w10253w10254w(0) AND wire_niO01ill_w_lg_niiiiO1O10243w(0)) AND wire_niO01ill_w_lg_niiiiO1l10245w(0)) AND niiiiO1i); + niOlOOlii <= ((wire_niO01ill_w_lg_n111i10O9993w(0) OR niOlOOliO) OR niOlOOlil); + niOlOOlil <= ((((((((NOT (n111i1OO XOR niOlOliiO)) AND (NOT (n111i01i XOR niOlOliil))) AND (NOT (n111i01l XOR niOlOliii))) AND (NOT (n111i01O XOR niOlOli0O))) AND (NOT (n111i00i XOR niOlOli0l))) AND (NOT (n111i00l XOR niOlOli0i))) AND (NOT (n111i00O XOR niOlOli1O))) AND (NOT (n111i0ii XOR niOlOli1l))); + niOlOOliO <= (((((((wire_niO01ill_w_lg_niii1i1l10032w(0) AND wire_niO01ill_w_lg_niii11ii10045w(0)) AND wire_niO01ill_w_lg_nii0OllO10058w(0)) AND wire_niO01ill_w_lg_nii0Oi1l10071w(0)) AND wire_niO01ill_w_lg_nii0O1ii10084w(0)) AND wire_niO01ill_w_lg_nii0lllO10097w(0)) AND wire_niO01ill_w_lg_nii0li1l10110w(0)) AND wire_niO01ill_w_lg_ni0i0i0O10123w(0)); + niOlOOlli <= (((((((n111i0ii AND n111i00O) AND n111i00l) AND n111i00i) AND n111i01O) AND n111i01l) AND n111i01i) AND n111i1OO); + niOlOOlll <= (((((((wire_niO01ill_w_lg_n111i0ii9973w(0) AND wire_niO01ill_w_lg_n111i00O9974w(0)) AND wire_niO01ill_w_lg_n111i00l9976w(0)) AND wire_niO01ill_w_lg_n111i00i9978w(0)) AND n111i01O) AND n111i01l) AND n111i01i) AND n111i1OO); + niOlOOllO <= (((((((wire_niO01ill_w_lg_n111i0ii9973w(0) AND wire_niO01ill_w_lg_n111i00O9974w(0)) AND wire_niO01ill_w_lg_n111i00l9976w(0)) AND wire_niO01ill_w_lg_n111i00i9978w(0)) AND wire_niO01ill_w_lg_n111i01O9984w(0)) AND wire_niO01ill_w_lg_n111i01l9986w(0)) AND n111i01i) AND n111i1OO); + niOlOOlOi <= (((((((wire_niO01ill_w_lg_n111i0ii9973w(0) AND wire_niO01ill_w_lg_n111i00O9974w(0)) AND wire_niO01ill_w_lg_n111i00l9976w(0)) AND wire_niO01ill_w_lg_n111i00i9978w(0)) AND wire_niO01ill_w_lg_n111i01O9984w(0)) AND wire_niO01ill_w_lg_n111i01l9986w(0)) AND wire_niO01ill_w_lg_n111i01i9990w(0)) AND n111i1OO); + niOlOOlOl <= (wire_nlOiOi1ll_dataout AND (n1lO0lOl OR wire_niO01ill_w_lg_n1lO0lOi9962w(0))); + niOlOOlOO <= (wire_w_lg_w_lg_w_k_conf_range9950w9951w9959w(0) AND wire_niil0i1l_w_lg_dataout9952w(0)); + niOlOOO0i <= (wire_w_lg_niOlOOO1O9954w(0) AND wire_w_lg_niOlOOO1l9961w(0)); + niOlOOO0l <= ((n11li1li AND wire_niO01iOi_w_lg_n11li1iO9835w(0)) AND wire_nlOii0O1O_dataout); + niOlOOO0O <= (wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0) AND wire_nlOii0O1O_w_lg_dataout9833w(0)); + niOlOOO1i <= (wire_w_lg_w_k_conf_range9950w9951w(0) AND wire_w_lg_niOO10lOO9957w(0)); + niOlOOO1l <= (nlOlOiO1l OR nlOlOilOO); + niOlOOO1O <= (nlOlOiO1l OR nlOlOiO1i); + niOlOOOii <= (wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0) AND wire_nlOii0O1O_dataout); + niOlOOOil <= ((((NOT k_cnt(36)) AND (NOT k_cnt(37))) AND (NOT k_cnt(38))) AND (NOT k_cnt(39))); + niOlOOOiO <= ((((NOT k_cnt(40)) AND (NOT k_cnt(41))) AND (NOT k_cnt(42))) AND (NOT k_cnt(43))); + niOlOOOli <= ((((NOT k_cnt(53)) AND (NOT k_cnt(54))) AND (NOT k_cnt(55))) AND (NOT k_cnt(56))); + niOlOOOll <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOlOOOlO <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOlOOOOi <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9873w9879w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOlOOOOl <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOlOOOOO <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO0000i <= (wire_nlOl1l0Ol_dataout AND wire_nlO0Oill_w_lg_dataout4340w(0)); + niOO0000l <= (niOO0000O AND nlO0llli); + niOO0000O <= (wire_nlO0Oill_w_lg_dataout4340w(0) AND wire_w_lg_niOO000Ol4401w(0)); + niOO0001i <= (nlO0llll AND (niOO000ll OR nlO0lliO)); + niOO0001l <= (nlO0llli AND wire_nlll0lli_q(130)); + niOO0001O <= (wire_nlOl1l0Ol_dataout AND wire_nllli01O_w_lg_dataout4050w(0)); + niOO000ii <= ((((((((wire_nlll0lli_w_lg_w_q_range4231w4450w(0) AND (NOT wire_nlll0lli_q(34))) AND (NOT wire_nlll0lli_q(35))) AND (NOT wire_nlll0lli_q(36))) AND (NOT wire_nlll0lli_q(37))) AND (NOT wire_nlll0lli_q(38))) AND (NOT wire_nlll0lli_q(39))) AND (NOT wire_nlll0lli_q(40))) AND (NOT wire_nlll0lli_q(41))); + niOO000il <= (wire_nlO0Oill_w_lg_dataout4340w(0) AND (wire_nlll0lli_q(130) AND wire_nlll0lli_q(129))); + niOO000iO <= (wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_w_lg_niOO000ll4355w(0)); + niOO000li <= ((wire_w_lg_niOO000ll4352w(0) AND wire_nlll0lli_q(131)) AND wire_nllli01O_w_lg_dataout4050w(0)); + niOO000ll <= (nlOi1OiOO AND niOl11OOO); + niOO000lO <= (wire_w_lg_niOO000Oi4345w(0) AND (nllO0i0l AND nllO0i0i)); + niOO000Oi <= ((nlOi1OiOO AND wire_nlOl1l0Ol_dataout) AND nlO0OlOii); + niOO000Ol <= (wire_nlOl1l0Ol_w_lg_dataout4337w(0) AND wire_nl1000i_w_lg_nllO0i0O4338w(0)); + niOO000OO <= (wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w4436w4438w4440w4442w4446w(0) AND wire_nl1000i_w_lg_n1l01il4447w(0)); + niOO0010i <= (nlllllll XOR nlllllli); + niOO0010l <= (nllllill XOR niOO0011O); + niOO0010O <= (nllllliO XOR niOO0010i); + niOO0011i <= (((nllliill XOR nllliili) XOR nllliilO) XOR nllliiOi); + niOO0011O <= (nlllliOi XOR nllllilO); + niOO001ii <= (nllllili XOR niOO0010l); + niOO001il <= (nlllllil XOR niOO0010O); + niOO001iO <= (nlllll1l XOR nlllll1i); + niOO001li <= (wire_w_lg_niOO001lO4482w(0) OR wire_w_lg_niOO001ll4483w(0)); + niOO001ll <= ((nlllll1i XOR nlllliOO) XOR nlllll1l); + niOO001lO <= (((nlllliOO XOR nlllliOl) XOR nlllll1i) XOR nlllll1l); + niOO001Oi <= (((((NOT k_hip(12)) AND (NOT k_hip(13))) AND (NOT k_hip(14))) AND (NOT k_hip(15))) AND (NOT k_hip(16))); + niOO001Ol <= (niOO000ll AND (nlO0lllO AND nlO0lliO)); + niOO001OO <= wire_nlO0Oill_w_lg_w_lg_dataout4340w4341w(0); + niOO00i0i <= (wire_w_lg_w_k_hip_range2413w2429w(0) AND (n1l000l AND niOO00i1l)); + niOO00i0l <= (wire_nl1000i_w_lg_n1l00ii4074w(0) AND n1l010O); + niOO00i0O <= ((wire_w_lg_niOO00llO4046w(0) AND wire_nl1000i_w_lg_n1l001O4298w(0)) AND wire_nl1000i_w_lg_nlOili0O4300w(0)); + niOO00i1i <= wire_nl1000i_w_lg_w_lg_w_lg_w4436w4438w4440w4442w(0); + niOO00i1l <= (n1l00ii AND n1l000O); + niOO00i1O <= (nlOili0l AND niOO00i0i); + niOO00iii <= (wire_w_lg_niOO00llO4046w(0) AND (n1l011O OR wire_nlO0OllO_dataout)); + niOO00iil <= (wire_w_lg_niOO00llO4046w(0) AND (n1l000l AND niOO00liO)); + niOO00iiO <= (wire_w_lg_niOO00llO4046w(0) AND nlOiliii); + niOO00ili <= (n1l011i AND (wire_w_lg_niOO00llO4046w(0) OR niOO00ill)); + niOO00ill <= wire_w_lg_niOO00llO4041w(0); + niOO00ilO <= (wire_n1ll1Ol_w_lg_w_lg_dataout4108w4109w(0) AND (wire_nl1000i_w_lg_n1l00ii4074w(0) OR (n1l00ii AND niOO00iOi))); + niOO00iOi <= ((wire_nl1000i_w_lg_w_lg_w_lg_w4436w4438w4440w4442w(0) AND wire_nl1000i_w_lg_n1l01iO4443w(0)) AND n1l01il); + niOO00iOl <= (wire_w_lg_niOO00llO4046w(0) AND n1l011l); + niOO00iOO <= (wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_w_lg_niOO00llO4046w(0)); + niOO00l0i <= (n1l000O AND n1l000l); + niOO00l0l <= (niOO00lil AND niOO00l0O); + niOO00l0O <= (niOO00lll OR wire_nl1000i_w_lg_nlOili0l4166w(0)); + niOO00l1i <= (wire_nl11llO_w_lg_n1l011O4051w(0) AND niOO00l0O); + niOO00l1l <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_niO01O0O_dataout); + niOO00l1O <= (wire_w_lg_w_lg_w_lg_w_lg_niOO00l0i4100w4103w4104w4105w(0) OR (((wire_n1ll1Ol_w_lg_w_lg_dataout4106w4107w(0) OR wire_n1ll1Ol_w_lg_w_lg_dataout4108w4109w(0)) OR wire_nl1000i_w_lg_n1l000O4060w(0)) AND wire_nl1000i_w_lg_n1l010l4099w(0))); + niOO00lii <= (wire_nl1000i_w_lg_w_lg_w_lg_w4436w4438w4440w4442w(0) AND wire_nl1000i_w_lg_n1l01iO4443w(0)); + niOO00lil <= (wire_nllli01O_w_lg_dataout4050w(0) AND wire_nlll0lli_q(131)); + niOO00liO <= (wire_w_lg_w_k_hip_range2413w2429w(0) AND n1l000O); + niOO00lli <= (k_gbl_hip(32) AND wire_nlll0lli_q(79)); + niOO00lll <= (nl11OOOii OR (nl11OO0il OR nl00lllil)); + niOO00llO <= (nl11OO0ii OR nl11Ol11i); + niOO00lOi <= (wire_w_lg_tx_err_vc04036w(0) AND wire_w_lg_tx_valid_vc04037w(0)); + niOO00lOl <= wire_w_lg_w_k_hip_range2413w4034w(0); + niOO00lOO <= (wire_w_lg_tx_eop_vc0_04425w(0) AND wire_w_lg_niOO0O1ll4426w(0)); + niOO00O0i <= ((wire_w_lg_w_lg_w_tx_data_vc0_0_range4005w4006w4007w(0) OR wire_w_lg_w4020w4021w(0)) AND wire_w_lg_niOO00O0l4023w(0)); + niOO00O0l <= ((((wire_w_lg_w_lg_w_tx_data_vc0_0_range4011w4012w4015w(0) AND tx_data_vc0_0(26)) AND (NOT tx_data_vc0_0(27))) AND (NOT tx_data_vc0_0(28))) AND wire_w_lg_w_tx_data_vc0_0_range4008w4009w(0)); + niOO00O0O <= ((NOT tx_data_vc0_0(27)) AND (NOT tx_data_vc0_0(28))); + niOO00O1i <= (tx_valid_vc0 AND tx_err_vc0); + niOO00O1l <= (tx_data_vc0_0(30) AND niOO00O0i); + niOO00O1O <= (tx_valid_vc0 AND (NOT (wire_w_lg_tx_sop_vc0_04025w(0) AND wire_w_lg_tx_sop_vc0_14026w(0)))); + niOO00Oii <= (niOO00Oil XOR n1lOlOl); + niOO00Oil <= (niOO00OOl XOR n1lOlOO); + niOO00OiO <= (niOO00Oli XOR n1lOlli); + niOO00Oli <= (niOO00Oll XOR n1lOlll); + niOO00Oll <= (n1lOlOi XOR n1lOllO); + niOO00OlO <= ((niOO0i1OO AND (NOT (niOO00OOO OR wire_w_lg_niOO00OOl3742w(0)))) XOR n1lOO1l); + niOO00OOi <= ((wire_w_lg_niOO00OOl3742w(0) AND wire_w_lg_niOO0i1OO3744w(0)) XOR n1lOO1i); + niOO00OOl <= (n1lOO1l XOR n1lOO1i); + niOO00OOO <= (wire_w_lg_niOO0i10i3731w(0) OR wire_w_lg_niOO0i11l3736w(0)); + niOO0100i <= ((wire_nl1000i_w_lg_nlliO1Oi5683w(0) AND wire_nl1000i_w_lg_nllillOl5686w(0)) AND wire_nl1lOOO0i_w_lg_dataout5689w(0)); + niOO0100l <= (wire_nl1000i_w_lg_nll0O0iOi5672w(0) OR (nll0Ol1i AND niOO0100O)); + niOO0100O <= (nll0O0iOi AND (wire_w_lg_w_k_hip_range2413w2429w(0) OR wire_w_lg_w_k_hip_range2413w5680w(0))); + niOO0101i <= (nll0O0iOl OR (nlli0ilOO AND niOO01i1O)); + niOO0101l <= (wire_nlll0liO_dataout AND (nlliO11l AND wire_nl1000i_w_lg_nlliO11i5692w(0))); + niOO0101O <= (k_hip(0) AND nlliO01l); + niOO010ii <= (niOO01l1O OR (niOO010il OR (nlli101ll OR nll0OOOOl))); + niOO010il <= ((niOiOiOil OR (nll0OOOOi AND wire_nl1000i_w_lg_nll0Oii0i36228w(0))) AND nll0O0i0i); + niOO010iO <= ((wire_nl1000i_w_lg_w_lg_nll0O0iOl5342w5600w(0) OR wire_w_lg_niOO01i1O5602w(0)) OR ((((wire_nl1000i_w_lg_nll0O0iOl5342w(0) AND wire_w_lg_w_k_hip_range2413w5604w(0)) OR wire_nl1000i_w_lg_nll0OiOl5607w(0)) OR wire_w_lg_w_k_hip_range2413w5610w(0)) OR wire_nl1000i_w_lg_nll0O0iOl5613w(0))); + niOO010li <= (nll0OilO AND nll0OiiO); + niOO010ll <= (wire_w_lg_niOO010iO5648w(0) AND wire_w_lg_w_k_hip_range2413w5653w(0)); + niOO010lO <= (k_hip(0) AND nll0O0iOi); + niOO010Oi <= (wire_nl1000i_w_lg_nll0O0iOl5342w(0) OR niOO010Ol); + niOO010Ol <= (nlli0ilOO AND nll0O0iOl); + niOO010OO <= (((((((((wire_nl1000i_w_lg_nll0Oi1ll5962w(0) AND wire_nl1000i_w_lg_nll0Oi1li5963w(0)) AND wire_nl1000i_w_lg_nll0Oi1iO5965w(0)) AND wire_nl1000i_w_lg_nll0Oi1il5967w(0)) AND wire_nl1000i_w_lg_nll0Oi1ii5969w(0)) AND wire_nl1000i_w_lg_nll0Oi10O5971w(0)) AND wire_nl1000i_w_lg_nll0Oi10l5973w(0)) AND wire_nl1000i_w_lg_nll0Oi10i5975w(0)) AND wire_nl1000i_w_lg_nll0Oi11O5977w(0)) AND nll0Oi11l); + niOO0110i <= (wire_w_lg_niOO01lOi5719w(0) AND niOO0110l); + niOO0110l <= (nlliO1Ol AND nll0Ol0l); + niOO0110O <= (nliO0iil AND niOO011ii); + niOO0111i <= (nll0OilO AND nll0Oili); + niOO0111l <= wire_w_lg_w_k_hip_range2413w5724w(0); + niOO0111O <= (niOO01lOi AND niOO0110l); + niOO011ii <= (nlliO1OO AND nll0Ol0l); + niOO011il <= (nllilO1i AND (wire_nl1000i_w_lg_nlliO11i5100w(0) AND wire_nl1000i_w_lg_w_lg_nlliO11O5108w5714w(0))); + niOO011iO <= (nllilO1i AND (wire_nl1000i_w_lg_nlliO11i5100w(0) AND (nlliO11O AND niOO011li))); + niOO011li <= (nlliO1OO AND wire_nl1000i_w_lg_nlliO11l5089w(0)); + niOO011ll <= (nll0Ol0l AND ((nlliO1OO AND nlliO11l) AND wire_w_lg_niOO01lil5707w(0))); + niOO011lO <= ((wire_nlll0liO_w_lg_dataout5087w(0) OR wire_nl1000i_w_lg_w_lg_nlliO11i5100w5701w(0)) AND niOO011Oi); + niOO011Oi <= wire_nl1000i_w_lg_nlliO01i5704w(0); + niOO011Ol <= (nlliO01i AND wire_nl1000i_w_lg_nlliO11l5089w(0)); + niOO011OO <= (nlliO01l AND wire_nl1000i_w_lg_nlliO10i5698w(0)); + niOO01i0i <= (nll0O0iOi AND wire_nl1000i_w_lg_nli1i1ll5104w(0)); + niOO01i0l <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) OR wire_niO01O0O_dataout); + niOO01i0O <= (wire_nl1000i_w_lg_nll0Oii1i5265w(0) AND niOO01iiO); + niOO01i1i <= (k_hip(0) AND nll0Oii1l); + niOO01i1l <= ((nlli0ilOO AND nll0O0iOi) AND (niOO01i1O OR nliOlilO)); + niOO01i1O <= (nll0OOOOi OR (nll0OOOlO OR nll0OOOll)); + niOO01iii <= (nll0Oii1i AND (k_gbl_hip(32) AND nll0Oi01l)); + niOO01iil <= (nll0Oii1i AND niOO01iiO); + niOO01iiO <= ((NOT k_gbl_hip(32)) OR wire_nl1000i_w_lg_nll0Oi01l5329w(0)); + niOO01ili <= ((wire_nl1000i_w_lg_nll0Oi0iO5948w(0) AND wire_nl1000i_w_lg_nll0Oi0il5949w(0)) AND wire_nl1000i_w_lg_nll0Oi0ii5951w(0)); + niOO01ill <= ((wire_nl1000i_w_lg_nll0Oi0iO5948w(0) AND wire_nl1000i_w_lg_nll0Oi0il5949w(0)) AND nll0Oi0ii); + niOO01ilO <= (wire_nl1000i_w_lg_w_lg_nll0Oi0iO5948w5954w(0) AND wire_nl1000i_w_lg_nll0Oi0ii5951w(0)); + niOO01iOi <= (wire_nl1000i_w_lg_w_lg_nll0Oi0iO5948w5954w(0) AND nll0Oi0ii); + niOO01iOl <= (wire_nl1000i_w_lg_nll0Oi0iO5957w(0) AND wire_nl1000i_w_lg_nll0Oi0ii5951w(0)); + niOO01iOO <= (wire_nl1000i_w_lg_nll0Oi0iO5957w(0) AND nll0Oi0ii); + niOO01l0i <= ((wire_nl1lO0i0i_w_lg_w_lg_dataout55287w56945w(0) AND wire_nl1lO0i1l_w_lg_dataout56946w(0)) AND wire_nl1lO0i1i_w_lg_dataout56948w(0)); + niOO01l0l <= (nl1Ol1l0i OR (wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0) AND nl1ll0lOi)); + niOO01l0O <= (nl1Ol1l0i OR wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0)); + niOO01l1i <= ((nll0Oi0iO AND nll0Oi0il) AND wire_nl1000i_w_lg_nll0Oi0ii5951w(0)); + niOO01l1l <= (nlli0ilOl AND nll0O0iOi); + niOO01l1O <= (niOiOiOiO OR (nll0OOOOi OR nll0OOOll)); + niOO01lii <= (((wire_nl1000i_w_lg_w_lg_nlliO11i5102w5103w(0) OR wire_nl1000i_w_lg_nli1i1ll5104w(0)) OR (wire_nl1000i_w_lg_w_lg_w_lg_nlliO11l5089w5106w5107w(0) AND (wire_nl1000i_w_lg_w_lg_nlliO11O5108w5109w(0) OR wire_nl1000i_w_lg_nllilO1i5110w(0)))) OR niOO01lil); + niOO01lil <= (wire_nl1000i_w_lg_nlliO11i5100w(0) AND nllilO1i); + niOO01liO <= (wire_w_lg_w_lg_w_lg_niOO01lll5093w5094w5095w(0) OR wire_w_lg_w_lg_niOO01llO5097w5098w(0)); + niOO01lli <= (((((((((wire_nl1000i_w_lg_nllilOOO5930w(0) AND wire_nl1000i_w_lg_nllilOOl5931w(0)) AND wire_nl1000i_w_lg_nllilOOi5933w(0)) AND wire_nl1000i_w_lg_nllilOlO5935w(0)) AND wire_nl1000i_w_lg_nllilOll5937w(0)) AND wire_nl1000i_w_lg_nllilOli5939w(0)) AND wire_nl1000i_w_lg_nllilOiO5941w(0)) AND wire_nl1000i_w_lg_nllilOil5943w(0)) AND wire_nl1000i_w_lg_nllilOii5945w(0)) AND nllilO0O); + niOO01lll <= (wire_nlll0liO_dataout AND nlliO11l); + niOO01llO <= (wire_nlll0liO_w_lg_w_lg_dataout5087w5088w(0) OR wire_nl1000i_w_lg_nlliO11l5089w(0)); + niOO01lOi <= (wire_nl1000i_w_lg_nllillOl5218w(0) AND wire_nl1000i_w_lg_nlliO10i5226w(0)); + niOO01lOl <= wire_nl1000i_w_lg_nllillOl5080w(0); + niOO01lOO <= wire_w_lg_w_k_gbl_hip_range1050w3226w(0); + niOO01O0i <= (niOO01O0l XOR nllliili); + niOO01O0l <= (niOO01Oll XOR nllliill); + niOO01O0O <= (niOO01Oii XOR nlllii0O); + niOO01O1i <= ((((NOT k_hip(4)) AND (NOT k_hip(5))) AND (NOT k_hip(6))) AND (NOT k_hip(7))); + niOO01Oii <= (niOO01Oil XOR nllliiii); + niOO01Oil <= (nllliiiO XOR nllliiil); + niOO01OiO <= ((wire_nlllOl0O_dataout AND (NOT (niOO01OlO OR wire_w_lg_niOO01Oll4589w(0)))) XOR nllliiOi); + niOO01Oli <= ((wire_w_lg_niOO01Oll4589w(0) AND wire_nlllOl0O_w_lg_dataout4591w(0)) XOR nllliilO); + niOO01Oll <= (nllliiOi XOR nllliilO); + niOO01OlO <= (wire_w_lg_niOO0011i4578w(0) OR wire_w_lg_niOO01OOl4583w(0)); + niOO01OOi <= ((wire_w_lg_niOO01OOl4583w(0) AND (wire_nlllOl0O_dataout AND niOO0011i)) XOR nllliill); + niOO01OOl <= ((nllliilO XOR nllliill) XOR nllliiOi); + niOO01OOO <= ((wire_nlllOl0O_dataout AND wire_w_lg_niOO0011i4578w(0)) XOR nllliili); + niOO0i00i <= wire_w_lg_w_k_gbl_hip_range1050w3435w(0); + niOO0i00l <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND n0Ol0OO); + niOO0i00O <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_ni1lOlO_w_lg_n0Ol0OO3319w(0)); + niOO0i01i <= (wire_n1llO0O_q(129) AND wire_n1llO0O_q(130)); + niOO0i01l <= ((NOT wire_n1llO0O_q(130)) AND (NOT wire_n1llO0O_q(131))); + niOO0i01O <= (n0Oiiii AND (k_gbl_hip(33) AND k_hip(0))); + niOO0i0ii <= (n0Oii0O AND (n0Oiiii AND (k_gbl_hip(33) AND k_hip(0)))); + niOO0i0il <= (wire_ni1lOlO_w_lg_n0Oiiii3421w(0) AND (k_gbl_hip(33) AND k_hip(0))); + niOO0i0iO <= wire_w_lg_w_k_hip_range2413w3420w(0); + niOO0i0li <= wire_w_lg_w_k_hip_range2413w3418w(0); + niOO0i0ll <= wire_w_lg_w_k_hip_range2413w3416w(0); + niOO0i0lO <= (n0Oiiii AND n0Oii0O); + niOO0i0Oi <= wire_w_lg_w_k_hip_range2413w3409w(0); + niOO0i0Ol <= (niOO0il0i AND niOO0ii1i); + niOO0i0OO <= (wire_w_lg_niOO0il0i3404w(0) AND niOO0ii1i); + niOO0i10i <= (((n1lOlOO XOR n1lOlOl) XOR n1lOO1i) XOR n1lOO1l); + niOO0i10l <= (n1O1lOl XOR n1O1lOi); + niOO0i10O <= (n1O1Oll XOR n1O1Oli); + niOO0i11i <= ((wire_w_lg_niOO0i11l3736w(0) AND (niOO0i1OO AND niOO0i10i)) XOR n1lOlOO); + niOO0i11l <= ((n1lOO1i XOR n1lOlOO) XOR n1lOO1l); + niOO0i11O <= ((niOO0i1OO AND wire_w_lg_niOO0i10i3731w(0)) XOR n1lOlOl); + niOO0i1ii <= (n1O1llO XOR niOO0i10l); + niOO0i1il <= (n1O1OiO XOR niOO0i10O); + niOO0i1iO <= (n1O1lll XOR niOO0i1ii); + niOO0i1li <= (n1O1Oil XOR niOO0i1il); + niOO0i1ll <= (n1O1O1O XOR n1O1O1l); + niOO0i1lO <= (wire_w_lg_niOO0i1Ol3636w(0) OR wire_w_lg_niOO0i1Oi3637w(0)); + niOO0i1Oi <= ((n1O1O1l XOR n1O1O1i) XOR n1O1O1O); + niOO0i1Ol <= (((n1O1O1i XOR n1O1lOO) XOR n1O1O1l) XOR n1O1O1O); + niOO0i1OO <= (wire_n1O0lli_dataout AND n1O0liO); + niOO0ii0i <= (n0Ol11i AND (wire_ni1lOlO_w_lg_n0Ol01i3229w(0) AND wire_ni1lOlO_w_lg_w_lg_n0Ol01O3238w3399w(0))); + niOO0ii0l <= (n0Ol11i AND (wire_ni1lOlO_w_lg_n0Ol01i3229w(0) AND (n0Ol01O AND niOO0ii0O))); + niOO0ii0O <= (n0Ol0Ol AND wire_ni1lOlO_w_lg_n0Ol01l3235w(0)); + niOO0ii1i <= (n0Ol0Oi AND n0Oiill); + niOO0ii1l <= (n0il1iO AND niOO0ii1O); + niOO0ii1O <= (n0Ol0Ol AND n0Oiill); + niOO0iiii <= (n0Oiill AND ((n0Ol0Ol AND n0Ol01l) AND wire_w_lg_niOO0il1l3392w(0))); + niOO0iiil <= wire_ni1lOlO_w_lg_n0Ol0OO3389w(0); + niOO0iiiO <= (n0Ol0OO AND wire_ni1lOlO_w_lg_n0Ol01l3235w(0)); + niOO0iili <= (n0Oli1i AND wire_ni1lOlO_w_lg_n0Ol00i3386w(0)); + niOO0iill <= (k_hip(0) AND n0Oli1i); + niOO0iilO <= (wire_w_lg_niOO0iiOi3378w(0) AND wire_w_lg_w_k_hip_range2413w3383w(0)); + niOO0iiOi <= (n0Oii0l OR ((wire_w_lg_w_k_hip_range2413w3337w(0) OR wire_ni1lOlO_w_lg_n0OiiiO3339w(0)) OR wire_w_lg_w_k_hip_range2413w3343w(0))); + niOO0iiOl <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) OR wire_w_lg_w_k_gbl_hip_range1050w3226w(0)); + niOO0iiOO <= (((wire_ni1lOlO_w_lg_w_lg_n0Ol01i3231w3232w(0) OR wire_ni1lOlO_w_lg_n1O1lli3233w(0)) OR (wire_ni1lOlO_w_lg_w_lg_w_lg_n0Ol01l3235w3236w3237w(0) AND (wire_ni1lOlO_w_lg_w_lg_n0Ol01O3238w3239w(0) OR wire_ni1lOlO_w_lg_n0Ol11i3240w(0)))) OR niOO0il1l); + niOO0il0i <= (wire_ni1lOlO_w_lg_n0OiOOl3328w(0) AND wire_ni1lOlO_w_lg_n0Ol00i3334w(0)); + niOO0il0l <= wire_ni1lOlO_w_lg_n0OiOOl3227w(0); + niOO0il0O <= wire_w_lg_w_k_gbl_hip_range1050w3226w(0); + niOO0il1i <= (((((((((wire_ni1lOlO_w_lg_n0Ol1OO3610w(0) AND wire_ni1lOlO_w_lg_n0Ol1Ol3611w(0)) AND wire_ni1lOlO_w_lg_n0Ol1Oi3613w(0)) AND wire_ni1lOlO_w_lg_n0Ol1lO3615w(0)) AND wire_ni1lOlO_w_lg_n0Ol1ll3617w(0)) AND wire_ni1lOlO_w_lg_n0Ol1li3619w(0)) AND wire_ni1lOlO_w_lg_n0Ol1iO3621w(0)) AND wire_ni1lOlO_w_lg_n0Ol1il3623w(0)) AND wire_ni1lOlO_w_lg_n0Ol1ii3625w(0)) AND n0Ol10O); + niOO0il1l <= (wire_ni1lOlO_w_lg_n0Ol01i3229w(0) AND n0Ol11i); + niOO0il1O <= wire_ni1lOlO_w_lg_n0Ol01i3228w(0); + niOO0ilii <= ((((NOT k_hip(8)) AND (NOT k_hip(9))) AND (NOT k_hip(10))) AND (NOT k_hip(11))); + niOO0illl <= (niOO0illO XOR ni11l0O); + niOO0illO <= (niOO0iO1O XOR ni11lii); + niOO0ilOi <= (niOO0ilOl XOR ni11l1l); + niOO0ilOl <= (niOO0ilOO XOR ni11l1O); + niOO0ilOO <= (ni11l0l XOR ni11l0i); + niOO0iO0i <= (wire_w_lg_niOO0iOil2724w(0) OR wire_w_lg_niOO0iO0O2729w(0)); + niOO0iO0l <= ((wire_w_lg_niOO0iO0O2729w(0) AND (wire_ni1ilOl_dataout AND niOO0iOil)) XOR ni11lii); + niOO0iO0O <= ((ni11lil XOR ni11lii) XOR ni11liO); + niOO0iO1i <= ((wire_ni1ilOl_dataout AND (NOT (niOO0iO0i OR wire_w_lg_niOO0iO1O2735w(0)))) XOR ni11liO); + niOO0iO1l <= ((wire_w_lg_niOO0iO1O2735w(0) AND wire_ni1ilOl_w_lg_dataout2737w(0)) XOR ni11lil); + niOO0iO1O <= (ni11liO XOR ni11lil); + niOO0iOii <= ((wire_ni1ilOl_dataout AND wire_w_lg_niOO0iOil2724w(0)) XOR ni11l0O); + niOO0iOil <= (((ni11lii XOR ni11l0O) XOR ni11lil) XOR ni11liO); + niOO0iOll <= (ni10liO XOR ni10lil); + niOO0iOlO <= (ni10Oii XOR ni10O0O); + niOO0iOOi <= (ni10lii XOR niOO0iOll); + niOO0iOOl <= (ni10O0l XOR niOO0iOlO); + niOO0iOOO <= (ni10l0O XOR niOO0iOOi); + niOO0l00i <= ((((((((wire_ni1lOlO_w_lg_ni1lOii2593w(0) AND wire_ni1lOlO_w_lg_ni1lO0O2594w(0)) AND wire_ni1lOlO_w_lg_ni1lO0l2596w(0)) AND wire_ni1lOlO_w_lg_ni1lO0i2598w(0)) AND wire_ni1lOlO_w_lg_ni1lO1O2600w(0)) AND wire_ni1lOlO_w_lg_ni1lO1l2602w(0)) AND wire_ni1lOlO_w_lg_ni1lO1i2604w(0)) AND wire_ni1lOlO_w_lg_ni1llOO2606w(0)) AND wire_ni1lOlO_w_lg_ni1llOl2608w(0)); + niOO0l00l <= (wire_ni110Ol_w_lg_dataout2425w(0) AND wire_n0OOO0O_q(131)); + niOO0l00O <= (k_gbl_hip(32) AND wire_n0OOO0O_q(79)); + niOO0l01i <= (wire_w_lg_w_lg_w_lg_w_lg_niOO0l01l2477w2480w2481w2482w(0) OR (((wire_ni01ill_w_lg_w_lg_dataout2483w2484w(0) OR wire_ni01ill_w_lg_w_lg_dataout2485w2486w(0)) OR wire_ni1lOlO_w_lg_ni1lOll2437w(0)) AND wire_ni1lOlO_w_lg_ni1llli2476w(0))); + niOO0l01l <= (ni1lOll AND ni1lOli); + niOO0l01O <= (niOO0l00l AND wire_ni1lOlO_w_lg_ni1iOOO2462w(0)); + niOO0l0il <= (wire_w_lg_tx_err_vc12419w(0) AND wire_w_lg_tx_valid_vc12420w(0)); + niOO0l0iO <= wire_w_lg_w_k_hip_range2413w2417w(0); + niOO0l0li <= (wire_w_lg_tx_eop_vc1_02590w(0) AND wire_w_lg_niOO0O1lO2591w(0)); + niOO0l0ll <= (tx_valid_vc1 AND tx_err_vc1); + niOO0l0lO <= (tx_data_vc1_0(30) AND niOO0l0Ol); + niOO0l0Oi <= (tx_valid_vc1 AND (NOT (wire_w_lg_tx_sop_vc1_02407w(0) AND wire_w_lg_tx_sop_vc1_12408w(0)))); + niOO0l0Ol <= ((wire_w_lg_w_lg_w_tx_data_vc1_0_range2387w2388w2389w(0) OR wire_w_lg_w2402w2403w(0)) AND wire_w_lg_niOO0l0OO2405w(0)); + niOO0l0OO <= ((((wire_w_lg_w_lg_w_tx_data_vc1_0_range2393w2394w2397w(0) AND tx_data_vc1_0(26)) AND (NOT tx_data_vc1_0(27))) AND (NOT tx_data_vc1_0(28))) AND wire_w_lg_w_tx_data_vc1_0_range2390w2391w(0)); + niOO0l10i <= ((ni10llO XOR ni10lll) XOR ni10lOi); + niOO0l10l <= (((ni10lll XOR ni10lli) XOR ni10llO) XOR ni10lOi); + niOO0l10O <= (((((NOT k_hip(17)) AND (NOT k_hip(18))) AND (NOT k_hip(19))) AND (NOT k_hip(20))) AND (NOT k_hip(21))); + niOO0l11i <= (ni10O0i XOR niOO0iOOl); + niOO0l11l <= (ni10lOi XOR ni10llO); + niOO0l11O <= (wire_w_lg_niOO0l10l2626w(0) OR wire_w_lg_niOO0l10i2627w(0)); + niOO0l1ii <= (((((((((wire_ni1lOlO_w_lg_ni1lOii2593w(0) AND wire_ni1lOlO_w_lg_ni1lO0O2594w(0)) AND wire_ni1lOlO_w_lg_ni1lO0l2596w(0)) AND wire_ni1lOlO_w_lg_ni1lO0i2598w(0)) AND wire_ni1lOlO_w_lg_ni1lO1O2600w(0)) AND wire_ni1lOlO_w_lg_ni1lO1l2602w(0)) AND wire_ni1lOlO_w_lg_ni1lO1i2604w(0)) AND wire_ni1lOlO_w_lg_ni1llOO2606w(0)) AND wire_ni1lOlO_w_lg_ni1llOl2608w(0)) AND ni1llOi); + niOO0l1il <= (ni1lOOi AND ni1lOll); + niOO0l1iO <= (wire_ni1lOlO_w_lg_ni1lOil2559w(0) AND wire_ni1lOlO_w_lg_ni1l11i2560w(0)); + niOO0l1li <= (wire_ni1llii_w_lg_ni1llil2426w(0) AND wire_ni1lOlO_w_lg_ni1iOOO2462w(0)); + niOO0l1OO <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_niO01O0O_dataout); + niOO0li0i <= (wire_nlOi1Oiii_dataout OR (ni0i0OO AND wire_nl1000i_w_lg_nl1OOOii2349w(0))); + niOO0li0l <= (wire_nlOi1Oi0l_dataout OR (ni001Ol AND wire_nl1000i_w_lg_nl1OOOil2346w(0))); + niOO0li0O <= (nlliiilli AND wire_nl1000i_w_lg_ni0l0il2336w(0)); + niOO0li1i <= ((NOT tx_data_vc1_0(27)) AND (NOT tx_data_vc1_0(28))); + niOO0li1l <= (wire_nl1000i_w_lg_ni0i0OO2344w(0) AND nl1OOOii); + niOO0li1O <= (wire_nl1000i_w_lg_ni001Ol2342w(0) AND nl1OOOil); + niOO0liii <= (wire_nl0illl1O_dataout AND nl0l0i0ii); + niOO0liil <= (wire_nl1000i_w_lg_ni0lO1i2326w(0) AND nl101OiO); + niOO0liiO <= (wire_niOOO0O_w_lg_w_lg_ni0O01O2320w2321w(0) AND wire_niOOO0O_w_lg_ni0O1li2322w(0)); + niOO0lili <= (nl0l11l0O OR niii0lO); + niOO0lill <= (niOiO0l AND niOO0lilO); + niOO0lilO <= (((wire_nl1000i_w_lg_w_lg_w_lg_w2361w2371w2373w2383w(0) AND wire_nl1000i_w_lg_niOilii2376w(0)) AND wire_nl1000i_w_lg_niOil0O2367w(0)) AND wire_nl1000i_w_lg_niOil0l2369w(0)); + niOO0liOi <= (niOiO0l AND niOO0liOl); + niOO0liOl <= ((wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w2361w2371w2373w2375w2380w(0) AND wire_nl1000i_w_lg_niOil0O2367w(0)) AND wire_nl1000i_w_lg_niOil0l2369w(0)); + niOO0liOO <= (niOiO0l AND niOO0ll1i); + niOO0ll0i <= (wire_nl1000i_w_lg_w_lg_niOi01l2310w2311w(0) OR wire_nl1000i_w_lg_w_lg_niiiOOO2312w2313w(0)); + niOO0ll1i <= (((wire_nl1000i_w_lg_w_lg_w_lg_w2361w2371w2373w2375w(0) AND wire_nl1000i_w_lg_niOilii2376w(0)) AND wire_nl1000i_w_lg_niOil0O2367w(0)) AND wire_nl1000i_w_lg_niOil0l2369w(0)); + niOO0ll1l <= (niOiO0l AND niOO0ll1O); + niOO0ll1O <= ((wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w2361w2363w2364w2365w2366w(0) AND wire_nl1000i_w_lg_niOil0O2367w(0)) AND wire_nl1000i_w_lg_niOil0l2369w(0)); + niOO0lliO <= '1'; + niOO0llll <= (wire_nl1000i_w_lg_nl11l1O1558w(0) OR nl11ilO); + niOO0lllO <= (((nl11lll OR nl11l1O) OR nl11l1i) OR nl11ilO); + niOO0llOi <= (((((nl11lll OR nl11lii) OR nl11l0O) OR nl11l1O) OR nl11l1i) OR nl11ilO); + niOO0lOlO <= ((((((((nl11lll OR nl11liO) OR nl11lii) OR nl11l0O) OR nl11l0l) OR nl11l1O) OR nl11l1i) OR nl11iOi) OR nl11ilO); + niOO0lOOi <= (((((((nl11lOi OR nl11lli) OR nl11lil) OR nl11l0O) OR nl11l0i) OR nl11l1l) OR nl11iOO) OR nl11iOi); + niOO0lOOl <= (wire_nl11llO_w_lg_w_lg_w1088w1089w1090w(0) OR (NOT (niOO0lOOO14 XOR niOO0lOOO13))); + niOO0O10O <= ((wire_nl1000i_w_lg_w_lg_niOOOil1058w1059w(0) OR (wire_nl1000i_w_lg_niOOOil1061w(0) AND (niOO0O1iO8 XOR niOO0O1iO7))) OR (NOT (niOO0O1ii10 XOR niOO0O1ii9))); + niOO0O11l <= ((((wire_nl11llO_w_lg_w_lg_w_lg_nl11lOi1070w1071w1072w(0) OR nl11l0i) OR nl11l1O) OR nl11l1l) OR nl11l1i); + niOO0O11O <= (wire_nl11llO_w_lg_w_lg_w1074w1075w1076w(0) OR (NOT (niOO0O10i12 XOR niOO0O10i11))); + niOO0O1ll <= (tx_eop_vc0_0 XOR tx_eop_vc0_1); + niOO0O1lO <= ((tx_eop_vc1_0 XOR tx_eop_vc1_1) XOR (NOT (niOO0O1Oi6 XOR niOO0O1Oi5))); + niOO0O1OO <= (nl0100ili XOR (wire_nilOi0iO_dataout AND (nl0100lOl AND nll0O1i1l))); + niOO1000i <= (niOO11l1i AND niOO10l0O); + niOO1000l <= (niOO11iOl AND niOO10l0O); + niOO1000O <= (niOO11iOi AND niOO10l0O); + niOO1001i <= (niOO11l0i AND niOO10l0O); + niOO1001l <= (niOO11l1O AND niOO10l0O); + niOO1001O <= (niOO11l1l AND niOO10l0O); + niOO100ii <= (niOO11ilO AND niOO10l0O); + niOO100il <= (niOO11OOl AND niOO10l1O); + niOO100iO <= (niOO11Oll AND niOO10l1O); + niOO100li <= (niOO11OiO AND niOO10l1O); + niOO100ll <= (niOO11Oii AND niOO10l1O); + niOO100lO <= (niOO11O0i AND niOO10l1O); + niOO100Oi <= (niOO11O1O AND niOO10l1O); + niOO100Ol <= (niOO11O1l AND niOO10l1O); + niOO100OO <= (niOO11O1i AND niOO10l1O); + niOO1010i <= (niOO11O0i AND niOO10l0O); + niOO1010l <= (niOO11O1O AND niOO10l0O); + niOO1010O <= (niOO11O1l AND niOO10l0O); + niOO1011i <= (niOO11Oll AND niOO10l0O); + niOO1011l <= (niOO11OiO AND niOO10l0O); + niOO1011O <= (niOO11Oii AND niOO10l0O); + niOO101ii <= (niOO11O1i AND niOO10l0O); + niOO101il <= (niOO11lOl AND niOO10l0O); + niOO101iO <= (niOO11lOi AND niOO10l0O); + niOO101li <= (niOO11llO AND niOO10l0O); + niOO101ll <= (niOO11lll AND niOO10l0O); + niOO101lO <= (niOO11liO AND niOO10l0O); + niOO101Oi <= (niOO11lil AND niOO10l0O); + niOO101Ol <= (niOO11lii AND niOO10l0O); + niOO101OO <= (niOO11l0O AND niOO10l0O); + niOO10i0i <= (niOO11lll AND niOO10l1O); + niOO10i0l <= (niOO11liO AND niOO10l1O); + niOO10i0O <= (niOO11lil AND niOO10l1O); + niOO10i1i <= (niOO11lOl AND niOO10l1O); + niOO10i1l <= (niOO11lOi AND niOO10l1O); + niOO10i1O <= (niOO11llO AND niOO10l1O); + niOO10iii <= (niOO11lii AND niOO10l1O); + niOO10iil <= (niOO11l0O AND niOO10l1O); + niOO10iiO <= (niOO11l0i AND niOO10l1O); + niOO10ili <= (niOO11l1O AND niOO10l1O); + niOO10ill <= (niOO11l1l AND niOO10l1O); + niOO10ilO <= (niOO11l1i AND niOO10l1O); + niOO10iOi <= (niOO11iOl AND niOO10l1O); + niOO10iOl <= (niOO11iOi AND niOO10l1O); + niOO10iOO <= (niOO11ilO AND niOO10l1O); + niOO10l0i <= (wire_niO111ii_w_lg_dataout8980w(0) AND niOO10l0O); + niOO10l0l <= (wire_niO111ii_dataout AND niOO10l0O); + niOO10l0O <= (wire_nlOi00O0i_w_lg_dataout9865w(0) AND wire_nlOi00O1O_dataout); + niOO10l1i <= wire_w_lg_w_k_gbl_hip_range9015w9022w(0); + niOO10l1l <= (wire_niO111ii_dataout AND niOO10l1O); + niOO10l1O <= (wire_nlOi00O0i_dataout AND wire_nlOi00O1O_w_lg_dataout9870w(0)); + niOO10lii <= (wire_nlill0Oll_w_lg_nl01ii1Oi44963w(0) AND (wire_nilOi0il_w_lg_dataout44964w(0) AND (wire_nilOi0ii_dataout AND niOililOl))); + niOO10lil <= (((wire_nlill0Oll_w_lg_nl01ii1Oi44963w(0) AND (wire_nilOi0il_w_lg_dataout44964w(0) AND wire_nlill0Oll_w_lg_w_lg_nl01ii1lO45016w45017w(0))) OR niOO001i) OR niOO010O); + niOO10liO <= ((nliiO0iiO AND niOlOO1O) OR niOO11ll); + niOO10lli <= (wire_nliiOiilO_w_lg_nliiO0iiO44289w(0) AND niOlOO1O); + niOO10lll <= ((nl01ii1iO AND niOililOi) OR niOO1llO); + niOO10llO <= (nl01ii1Ol AND nli0OiiOi); + niOO10lOi <= (niOililOl AND (wire_nilOi0il_dataout OR nl01ii1Oi)); + niOO10lOl <= (nl011ilOl AND niOii1l0l); + niOO10lOO <= ((wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) OR wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0)) OR wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0)); + niOO10O0i <= (nl11OO00O AND wire_nlill0Oll_w_lg_nl11OO00l60211w(0)); + niOO10O0l <= (niOl101Ol AND nlliiilii); + niOO10O0O <= (niOilO11O AND (((wire_nliliiO1i_w_lg_dataout48219w(0) AND wire_nliliilOl_w_lg_dataout43980w(0)) AND wire_nliliilOi_w_lg_dataout43982w(0)) OR (wire_nliliiO1i_w_lg_w_lg_w_lg_dataout48201w48203w48212w(0) AND wire_nliliilOi_w_lg_dataout43982w(0)))); + niOO10O1i <= ((NOT mode(0)) AND wire_w_lg_w_mode_range8897w9838w(0)); + niOO10O1l <= wire_w_lg_w_mode_range8895w9840w(0); + niOO10O1O <= ((NOT k_gbl_hip(12)) AND ((NOT mode(0)) AND mode(1))); + niOO10Oii <= (niO011ll XOR niO011ii); + niOO10Oil <= (niO010ll XOR niO010ii); + niOO10OiO <= (niO01ilO XOR niO01iii); + niOO10OlO <= (k_hip(2) OR scan_mode); + niOO10OOi <= (((nli101lOl OR nli101ilO) OR nli11OOOO) AND niOiilO1O); + niOO10OOl <= ((niO0l0lO AND niO0l0ll) AND niO00O0O); + niOO10OOO <= ((niOi111i AND niO0OOOO) AND niO0lOOl); + niOO1100i <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1100l <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO1100O <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9873w9879w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1101i <= (wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w9921w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1101l <= (((wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0)) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1101O <= (((wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0)) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO110ii <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO110il <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO110iO <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9882w9886w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO110li <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO110ll <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO110lO <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9890w9894w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO110Oi <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO110Ol <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO110OO <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9896w9900w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1110i <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9890w9894w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1110l <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1110O <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO1111i <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9882w9886w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1111l <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO1111O <= ((wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO111ii <= (wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9896w9900w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO111il <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO111iO <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO111li <= (wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w9908w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO111ll <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO111lO <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO111Oi <= (wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w9914w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO111Ol <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO111OO <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO11i0i <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO11i0l <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO11i0O <= (wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w9914w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO11i1i <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO11i1l <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO11i1O <= (wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w9908w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO11iii <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO11iil <= ((wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w(0) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO11iiO <= (wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w9921w(0) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO11ili <= (((wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0)) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND wire_nl1000i_w_lg_nlillOi1O9876w(0)); + niOO11ill <= (((wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0)) AND wire_nl1000i_w_lg_nlillOi0i9874w(0)) AND nlillOi1O); + niOO11ilO <= (niOO11iOO AND niOO11Oli); + niOO11iOi <= (niOO11OOi AND niOO11iOO); + niOO11iOl <= (niOO11iOO AND niOO11O0l); + niOO11iOO <= ((wire_nilOll0i_w_lg_dataout9845w(0) AND wire_nilOll1O_w_lg_dataout9841w(0)) AND wire_nilOll1l_w_lg_dataout9843w(0)); + niOO11l0i <= ((niOO11l0l AND niOO11O0l) AND wire_nil0OO1O_o); + niOO11l0l <= ((wire_nilOll0i_w_lg_dataout9845w(0) AND wire_nilOll1O_w_lg_dataout9841w(0)) AND wire_nilOll1l_dataout); + niOO11l0O <= ((niOO11lli AND niOO11Oil) AND wire_nili111i_o); + niOO11l1i <= ((niOO11l0l AND niOO11Oil) AND wire_nil0OO1O_o); + niOO11l1l <= ((niOO11l0l AND niOO11Oli) AND wire_nil0OO1O_o); + niOO11l1O <= ((niOO11l0l AND niOO11OOi) AND wire_nil0OO1O_o); + niOO11lii <= ((niOO11lli AND niOO11Oli) AND wire_nili111i_o); + niOO11lil <= ((niOO11lli AND niOO11OOi) AND wire_nili111i_o); + niOO11liO <= ((niOO11lli AND niOO11O0l) AND wire_nili111i_o); + niOO11lli <= (wire_nilOll0i_w_lg_w_lg_dataout9845w9846w(0) AND wire_nilOll1l_w_lg_dataout9843w(0)); + niOO11lll <= ((niOO11lOO AND niOO11Oil) AND wire_nili11Ol_o); + niOO11llO <= ((niOO11lOO AND niOO11Oli) AND wire_nili11Ol_o); + niOO11lOi <= ((niOO11lOO AND niOO11OOi) AND wire_nili11Ol_o); + niOO11lOl <= ((niOO11lOO AND niOO11O0l) AND wire_nili11Ol_o); + niOO11lOO <= (wire_nilOll0i_w_lg_w_lg_dataout9845w9846w(0) AND wire_nilOll1l_dataout); + niOO11O0i <= ((niOO11O0O AND niOO11O0l) AND wire_nili10lO_o); + niOO11O0l <= wire_nlOiilO1l_w_lg_w_lg_w_lg_w_lg_dataout9857w9858w9868w9869w(0); + niOO11O0O <= (wire_nilOll0i_w_lg_dataout9842w(0) AND wire_nilOll1l_w_lg_dataout9843w(0)); + niOO11O1i <= ((niOO11O0O AND niOO11Oil) AND wire_nili10lO_o); + niOO11O1l <= ((niOO11O0O AND niOO11Oli) AND wire_nili10lO_o); + niOO11O1O <= ((niOO11O0O AND niOO11OOi) AND wire_nili10lO_o); + niOO11Oii <= ((niOO11Oil AND niOO11OlO) AND wire_nil0Olil_o); + niOO11Oil <= ((wire_nlOiilO1l_w_lg_dataout9852w(0) AND wire_nlOiillOO_w_lg_dataout9853w(0)) AND wire_nlOiillOl_w_lg_dataout9855w(0)); + niOO11OiO <= ((niOO11Oli AND niOO11OlO) AND wire_nil0Olil_o); + niOO11Oli <= ((wire_nlOiilO1l_w_lg_w_lg_dataout9857w9862w(0) AND wire_nlOiillOO_w_lg_dataout9853w(0)) AND wire_nlOiillOl_w_lg_dataout9855w(0)); + niOO11Oll <= ((niOO11OOi AND niOO11OlO) AND wire_nil0Olil_o); + niOO11OlO <= (wire_nilOll0i_w_lg_dataout9842w(0) AND wire_nilOll1l_dataout); + niOO11OOi <= (wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9859w(0) AND wire_nlOiillOl_w_lg_dataout9855w(0)); + niOO11OOl <= ((niOO11OlO AND niOO11O0l) AND wire_nil0Olil_o); + niOO11OOO <= (niOO11OOl AND niOO10l0O); + niOO1i00i <= (nli1lO1ii OR nlii1iOil); + niOO1i00l <= ((nli1lO1il OR nli1l00ll) OR nlii1iOiO); + niOO1i00O <= ((nli1lO1iO OR nli1l00lO) OR nlii1iOli); + niOO1i01i <= (nli1lO10i OR nlii1iO0l); + niOO1i01l <= (nli1lO10l OR nlii1iO0O); + niOO1i01O <= (nli1lO10O OR nlii1iOii); + niOO1i0ii <= ((nli1lO1li OR nli1l00Oi) OR nlii1iOll); + niOO1i0il <= (nli1lO1ll OR nlii1iOlO); + niOO1i0iO <= (nli1lO1lO OR nlii1iOOi); + niOO1i0li <= (nli1lO1Oi OR nlii1iOOl); + niOO1i0ll <= (nli1lO1Ol OR nlii1iOOO); + niOO1i0lO <= (nli1lO1OO OR nlii1l11i); + niOO1i0Oi <= (nli1lO01i OR nlii1l11l); + niOO1i0Ol <= (nli1lO01l OR nlii1l11O); + niOO1i0OO <= (nli1lO01O OR nlii1l10i); + niOO1i10i <= ((niOl10Oi AND niOl10lO) AND niOl10ll); + niOO1i10l <= ((nli1lliOO OR nli1l1Oll) OR nlii1i1li); + niOO1i10O <= ((nli1llOiO OR nli1l000i) OR nlii1illi); + niOO1i11i <= (niOiilli XOR niOiilil); + niOO1i11l <= (((((((((((((((((((((((((((((((((((((((((((((((NOT (niOiOlli XOR niOiilOl)) AND (NOT (niOiOlll XOR niOiilOO))) AND (NOT (niOiOllO XOR niOiiO1i))) AND (NOT (niOiOlOi XOR niOiiO1l))) AND (NOT (niOiOlOl XOR niOiiO1O))) AND (NOT (niOiOlOO XOR niOiiO0i))) AND (NOT (niOiOO1i XOR niOiiO0l))) AND (NOT (niOiOO1l XOR niOiiO0O))) AND (NOT (niOiOO1O XOR niOiiOii))) AND (NOT (niOiOO0i XOR niOiiOil))) AND (NOT (niOiOO0l XOR niOiiOiO))) AND (NOT (niOiOO0O XOR niOiiOli))) AND (NOT (niOiOOii XOR niOiiOll))) AND (NOT (niOiOOil XOR niOiiOlO))) AND (NOT (niOiOOiO XOR niOiiOOi))) AND (NOT (niOiOOli XOR niOiiOOl))) AND (NOT (niOiOOll XOR niOiiOOO))) AND (NOT (niOiOOlO XOR niOil11i))) AND (NOT (niOiOOOi XOR niOil11l))) AND (NOT (niOiOOOl XOR niOil11O))) AND (NOT (niOiOOOO XOR niOil10i))) AND (NOT (niOl111i XOR niOil10l))) AND (NOT (niOl111l XOR niOil10O))) AND (NOT (niOl111O XOR niOil1ii))) AND (NOT (niOl110i XOR niOil1il))) AND (NOT (niOl110l XOR niOil1iO))) AND (NOT (niOl110O XOR niOil1li))) AND (NOT (niOl11ii XOR niOil1ll))) AND (NOT (niOl11il XOR niOil1lO))) AND (NOT (niOl11iO XOR niOil1Oi))) AND (NOT (niOl11li XOR niOil1Ol))) AND (NOT (niOl11ll XOR niOil1OO))) AND (NOT (niOl11lO XOR niOil01i))) AND (NOT (niOl11Oi XOR niOil01l))) AND (NOT (niOl11Ol XOR niOil01O))) AND (NOT (niOl11OO XOR niOil00i))) AND (NOT (niOl101i XOR niOil00l))) AND (NOT (niOl101l XOR niOil00O))) AND (NOT (niOl101O XOR niOil0ii))) AND (NOT (niOl100i XOR niOil0il))) AND (NOT (niOl100l XOR niOil0iO))) AND (NOT (niOl100O XOR niOil0li))) AND (NOT (niOl10ii XOR niOil0ll))) AND (NOT (niOl10il XOR niOil0lO))) AND (NOT (niOl10iO XOR niOil0Oi))) AND (NOT (niOl10li XOR niOil0Ol))) AND (NOT (niOlii1O XOR niOil0OO))); + niOO1i11O <= (niOiilll XOR niOiil0i); + niOO1i1ii <= ((nli1llOli OR nli1l000l) OR nlii1illl); + niOO1i1il <= ((nli1llOll OR nli1l000O) OR nlii1illO); + niOO1i1iO <= ((nli1llOlO OR nli1l00ii) OR nlii1ilOi); + niOO1i1li <= ((nli1llOOi OR nli1l00il) OR nlii1ilOl); + niOO1i1ll <= ((nli1llOOl OR nli1l00iO) OR nlii1ilOO); + niOO1i1lO <= ((nli1llOOO OR nli1l00li) OR nlii1iO1i); + niOO1i1Oi <= (nli1lO11i OR nlii1iO1l); + niOO1i1Ol <= (nli1lO11l OR nlii1iO1O); + niOO1i1OO <= (nli1lO11O OR nlii1iO0i); + niOO1ii0i <= ((nli1lO0ii OR nli1l00Ol) OR nlii1l1il); + niOO1ii0l <= (nli1lO0il OR nlii1l1iO); + niOO1ii0O <= ((nli1lO0iO OR nli1l00OO) OR nlii1l1li); + niOO1ii1i <= (nli1lO00i OR nlii1l10l); + niOO1ii1l <= (nli1lO00l OR nlii1l10O); + niOO1ii1O <= (nli1lO00O OR nlii1l1ii); + niOO1iiii <= ((niOliOli AND niOliOiO) AND niOliOil); + niOO1iiil <= (niOlOl0i XOR niOlOilO); + niOO1iiiO <= (niOlOOll XOR niOlOO0i); + niOO1iili <= (niOO100i XOR niOO11lO); + niOO1iill <= (niOO1ilO XOR niOO1i0l); + niOO1iilO <= (niOO1O0l XOR niOO1lOi); + niOO1iiOi <= (niOO00il XOR niOO000O); + niOO1iiOl <= (niOO00iO XOR niOO001l); + niOO1iiOO <= (niOO0liO XOR niOO0l1l); + niOO1il0i <= (((((((((((NOT (tl_pm_data(0) XOR niOOl00i)) AND (NOT (tl_pm_data(1) XOR niOOl00l))) AND (NOT (tl_pm_data(2) XOR niOOl00O))) AND (NOT (tl_pm_data(3) XOR niOOl0ii))) AND (NOT (tl_pm_data(4) XOR niOOl0il))) AND (NOT (tl_pm_data(5) XOR niOOl0iO))) AND (NOT (tl_pm_data(6) XOR niOOl0li))) AND (NOT (tl_pm_data(7) XOR niOOl0ll))) AND (NOT (tl_pm_data(8) XOR niOOl0lO))) AND (NOT (tl_pm_data(9) XOR niOOl0Oi))) AND (NOT (tl_pm_auxpwr XOR niOOl0Ol))); + niOO1il0l <= (niOOl01i XOR niOOl1iO); + niOO1il0O <= (niOOlOil XOR niOOlO1i); + niOO1il1i <= (niOOi11l XOR niOO0Oli); + niOO1il1l <= (niOOi0li XOR niOOi01O); + niOO1il1O <= (niOOl1OO XOR niOOl1Oi); + niOO1ilii <= (niOOO1OO XOR niOOO1il); + niOO1ilil <= (niOOOiiO XOR niOOOi1l); + niOO1iliO <= (nl11111l XOR niOOOOli); + niOO1illi <= (nl1110li XOR nl11101O); + niOO1illl <= (nl111l1O XOR nl111ill); + niOO1illO <= (nl111Oll XOR nl111O0i); + niOO1ilOi <= (nl11000i XOR nl1101lO); + niOO1ilOl <= (nl110ilO XOR nl110i0l); + niOO1ilOO <= (nl110O0l XOR nl110lOi); + niOO1iO0i <= (nl11l1ii XOR nl11iOOO); + niOO1iO0l <= (nl11l0OO XOR nl11l0il); + niOO1iO0O <= (nl11llil XOR nl11ll1i); + niOO1iO1i <= (nl11i1Oi XOR nl11i10O); + niOO1iO1l <= (nl11ii0O XOR nl11i0Ol); + niOO1iO1O <= (nl11ilOl XOR nl11ilii); + niOO1iOii <= (nl11O11i XOR nl11lOiO); + niOO1iOil <= (nl11O0iO XOR nl11O01l); + niOO1iOiO <= (nl11Ol1l XOR nl11Oili); + niOO1iOli <= (nl11OOiO XOR nl11OO1l); + niOO1iOll <= (nl10101O XOR nl1011ll); + niOO1iOlO <= (nl101ili XOR nl101i1O); + niOO1iOOi <= (nl1000ii XOR nl10000l); + niOO1iOOl <= (((((((((NOT (ni0li1l XOR nl1000ll)) AND (NOT (ni0li0l XOR nl1000lO))) AND (NOT (ni0li0O XOR nl1000Oi))) AND (NOT (ni0liii XOR nl1000Ol))) AND (NOT (ni0liil XOR nl1000OO))) AND (NOT (ni0liiO XOR nl100i1i))) AND (NOT (ni0lili XOR nl100i1l))) AND (NOT (ni0lill XOR nl100i1O))) AND (NOT (ni0lilO XOR nl100i0i))); + niOO1iOOO <= (nl1000il XOR nl10001i); + niOO1l00i <= (nl1iO00i XOR nl1iO01l); + niOO1l00l <= (((((((((((((NOT (dl_ctrl_link2(0) XOR nl1iO0il)) AND (NOT (dl_ctrl_link2(1) XOR nl1iO0iO))) AND (NOT (dl_ctrl_link2(2) XOR nl1iO0li))) AND (NOT (dl_ctrl_link2(3) XOR nl1iO0ll))) AND (NOT (dl_ctrl_link2(4) XOR nl1iO0lO))) AND (NOT (dl_ctrl_link2(5) XOR nl1iO0Oi))) AND (NOT (dl_ctrl_link2(6) XOR nl1iO0Ol))) AND (NOT (dl_ctrl_link2(7) XOR nl1iO0OO))) AND (NOT (dl_ctrl_link2(8) XOR nl1iOi1i))) AND (NOT (dl_ctrl_link2(9) XOR nl1iOi1l))) AND (NOT (dl_ctrl_link2(10) XOR nl1iOi1O))) AND (NOT (dl_ctrl_link2(11) XOR nl1iOi0i))) AND (NOT (dl_ctrl_link2(12) XOR nl1iOi0l))); + niOO1l00O <= (nl1iO00l XOR nl1iO1Oi); + niOO1l01i <= (nl1iiO0l XOR nl1iilOi); + niOO1l01l <= (nl1il00i XOR nl1il01l); + niOO1l01O <= (nl1il00l XOR nl1il1Oi); + niOO1l0ii <= (nl1l11ll XOR nl1l110i); + niOO1l0il <= (nl1l1i0i XOR nl1l10lO); + niOO1l0iO <= (nl1l1llO XOR nl1l1l0l); + niOO1l0li <= (nl1l010l XOR nl1l1OOi); + niOO1l0ll <= (nl1l00Oi XOR nl1l000O); + niOO1l0lO <= (nllii0Oll OR wire_nlOiii1lO_dataout); + niOO1l0Oi <= (nl1l0l0O XOR nl1l0iOl); + niOO1l0Ol <= (nl1li00i XOR nl1li01l); + niOO1l0OO <= (nl1li00l XOR nl1li1Oi); + niOO1l10i <= (nl10iO1O XOR nl10iO1i); + niOO1l10l <= (((((NOT (tl_pex_msi_num(0) XOR nl10iOii)) AND (NOT (tl_pex_msi_num(1) XOR nl10iOil))) AND (NOT (tl_pex_msi_num(2) XOR nl10iOiO))) AND (NOT (tl_pex_msi_num(3) XOR nl10iOli))) AND (NOT (tl_pex_msi_num(4) XOR nl10iOll))); + niOO1l10O <= (nl10iO0i XOR nl10illO); + niOO1l11i <= (nl10i1ll XOR nl10i1iO); + niOO1l11l <= (((((NOT (tl_aer_msi_num(0) XOR nl10i1OO)) AND (NOT (tl_aer_msi_num(1) XOR nl10i01i))) AND (NOT (tl_aer_msi_num(2) XOR nl10i01l))) AND (NOT (tl_aer_msi_num(3) XOR nl10i01O))) AND (NOT (tl_aer_msi_num(4) XOR nl10i00i))); + niOO1l11O <= (nl10i1lO XOR nl10i10l); + niOO1l1ii <= (nl10lO1i XOR nl10llOl); + niOO1l1il <= ((((((((NOT (dl_vc_ctrl(0) XOR nl10lO0l)) AND (NOT (dl_vc_ctrl(1) XOR nl10lO0O))) AND (NOT (dl_vc_ctrl(2) XOR nl10lOii))) AND (NOT (dl_vc_ctrl(3) XOR nl10lOil))) AND (NOT (dl_vc_ctrl(4) XOR nl10lOiO))) AND (NOT (dl_vc_ctrl(5) XOR nl10lOli))) AND (NOT (dl_vc_ctrl(6) XOR nl10lOll))) AND (NOT (dl_vc_ctrl(7) XOR nl10lOlO))); + niOO1l1iO <= (nl10lO1l XOR nl10llli); + niOO1l1li <= (nl1i1O1O XOR nl1i1O1i); + niOO1l1ll <= ((((((((((((((((((((((((NOT (dl_vcid_map(0) XOR nl1i1Oii)) AND (NOT (dl_vcid_map(1) XOR nl1i1Oil))) AND (NOT (dl_vcid_map(2) XOR nl1i1OiO))) AND (NOT (dl_vcid_map(3) XOR nl1i1Oli))) AND (NOT (dl_vcid_map(4) XOR nl1i1Oll))) AND (NOT (dl_vcid_map(5) XOR nl1i1OlO))) AND (NOT (dl_vcid_map(6) XOR nl1i1OOi))) AND (NOT (dl_vcid_map(7) XOR nl1i1OOl))) AND (NOT (dl_vcid_map(8) XOR nl1i1OOO))) AND (NOT (dl_vcid_map(9) XOR nl1i011i))) AND (NOT (dl_vcid_map(10) XOR nl1i011l))) AND (NOT (dl_vcid_map(11) XOR nl1i011O))) AND (NOT (dl_vcid_map(12) XOR nl1i010i))) AND (NOT (dl_vcid_map(13) XOR nl1i010l))) AND (NOT (dl_vcid_map(14) XOR nl1i010O))) AND (NOT (dl_vcid_map(15) XOR nl1i01ii))) AND (NOT (dl_vcid_map(16) XOR nl1i01il))) AND (NOT (dl_vcid_map(17) XOR nl1i01iO))) AND (NOT (dl_vcid_map(18) XOR nl1i01li))) AND (NOT (dl_vcid_map(19) XOR nl1i01ll))) AND (NOT (dl_vcid_map(20) XOR nl1i01lO))) AND (NOT (dl_vcid_map(21) XOR nl1i01Oi))) AND (NOT (dl_vcid_map(22) XOR nl1i01Ol))) AND (NOT (dl_vcid_map(23) XOR nl1i01OO))); + niOO1l1lO <= (nl1i1O0i XOR nl1i1llO); + niOO1l1Oi <= (nl1ii1Ol XOR nl1ii1lO); + niOO1l1Ol <= (nl1ii1OO XOR nl1ii1il); + niOO1l1OO <= (nl1iiilO XOR nl1iii0l); + niOO1li0i <= (((((NOT (nlll00i0i XOR nlll11l0l)) AND (NOT (nlll00i0l XOR nlll11l0O))) AND (NOT (nlll00i0O XOR nlll11lii))) AND (NOT (nlll00iii XOR nlll11lil))) AND (NOT (nlll00iil XOR nlll11liO))); + niOO1li0l <= (nl1lli1i AND nl1ll0OO); + niOO1li0O <= ((wire_w_lg_niOl101il28868w(0) OR wire_w_lg_niOl101ii28869w(0)) OR nlO1Oi10O); + niOO1li1i <= (nl1liOll XOR nl1liOiO); + niOO1li1l <= (((((NOT (wire_nlOiiOi0i_dataout XOR nl1liOOO)) AND (NOT (wire_nlOiiOi0l_dataout XOR nl1ll11i))) AND (NOT (wire_nlOiiOi0O_dataout XOR nl1ll11l))) AND (NOT (wire_nlOiiOiii_dataout XOR nl1ll11O))) AND (NOT (wire_nlOiiOiil_dataout XOR nl1ll10i))); + niOO1li1O <= (nl1liOlO XOR nl1liO0l); + niOO1liii <= (nl1lll1i AND nl1lliOO); + niOO1liil <= (nl1llOOO XOR nl1llOOi); + niOO1liiO <= (nl1lO11i XOR nl1llOiO); + niOO1lili <= (nl1lOili XOR nl1lOiil); + niOO1lill <= (((((NOT (nl1lOO0i XOR nl1lOiOl)) AND (NOT (nl1lOO0l XOR nl1lOiOO))) AND (NOT (nl1lOO0O XOR nl1lOl1i))) AND (NOT (nl1lOOii XOR nl1lOl1l))) AND (NOT (nl1O110l XOR nl1lOl1O))); + niOO1lilO <= (nl1lOill XOR nl1lOi0i); + niOO1liOi <= (niOO0li0O OR nl1O11ii); + niOO1liOl <= (nl1O110O AND nl1lOOil); + niOO1liOO <= (nl1O1ilO XOR nl1O1ili); + niOO1ll0i <= (nl1O0iOO XOR nl1O0iil); + niOO1ll0l <= (nl1O0Oil XOR nl1O0O1i); + niOO1ll0O <= (nl1Oi01i XOR nl1Oi1iO); + niOO1ll1i <= (nl1O1iOi XOR nl1O1i0O); + niOO1ll1l <= (nl1O1OOi XOR nl1O1O0O); + niOO1ll1O <= (nl1O00ii XOR nl1O01OO); + niOO1llii <= (nl1Oiiil XOR nl1Oii1i); + niOO1llil <= (nl1OiO1i XOR nl1OiliO); + niOO1lliO <= (nl1Ol1li XOR nl1Ol11O); + niOO1llli <= (nl1Oli1O XOR nl1Ol0ll); + niOO1llll <= (nl1Ollll XOR nl1Oll0i); + niOO1lllO <= (nl1OO10i XOR nl1OlOlO); + niOO1llOi <= (nl011llO XOR nl011lli); + niOO1llOl <= (((((((((((((((((((((((((((NOT (dl_data_upfc(0) XOR nl011O1i)) AND (NOT (dl_data_upfc(1) XOR nl011O1l))) AND (NOT (dl_data_upfc(2) XOR nl011O1O))) AND (NOT (dl_data_upfc(3) XOR nl011O0i))) AND (NOT (dl_data_upfc(4) XOR nl011O0l))) AND (NOT (dl_data_upfc(5) XOR nl011O0O))) AND (NOT (dl_data_upfc(6) XOR nl011Oii))) AND (NOT (dl_data_upfc(7) XOR nl011Oil))) AND (NOT (dl_data_upfc(8) XOR nl011OiO))) AND (NOT (dl_data_upfc(9) XOR nl011Oli))) AND (NOT (dl_data_upfc(10) XOR nl011Oll))) AND (NOT (dl_data_upfc(11) XOR nl011OlO))) AND (NOT (dl_hdr_upfc(0) XOR nl011OOi))) AND (NOT (dl_hdr_upfc(1) XOR nl011OOl))) AND (NOT (dl_hdr_upfc(2) XOR nl011OOO))) AND (NOT (dl_hdr_upfc(3) XOR nl01011i))) AND (NOT (dl_hdr_upfc(4) XOR nl01011l))) AND (NOT (dl_hdr_upfc(5) XOR nl01011O))) AND (NOT (dl_hdr_upfc(6) XOR nl01010i))) AND (NOT (dl_hdr_upfc(7) XOR nl01010l))) AND (NOT (dl_vcid_upfc(0) XOR nl01010O))) AND (NOT (dl_vcid_upfc(1) XOR nl0101ii))) AND (NOT (dl_vcid_upfc(2) XOR nl0101il))) AND (NOT (dl_typ_upfc(0) XOR nl0101iO))) AND (NOT (dl_typ_upfc(1) XOR nl0101li))) AND (NOT (dl_snd_upfc XOR nl0101ll))) AND (NOT (dl_req_upfc XOR nl0101lO))); + niOO1llOO <= (nl011lOi XOR nl011l0O); + niOO1lO0i <= (nl01ilOi AND nl01illO); + niOO1lO0l <= (nl01OliO XOR nl01Olii); + niOO1lO0O <= (((((((((((((((((((((((((((((((((((((NOT (nl0000iO XOR nl01OlOi)) AND (NOT (nl0000li XOR nl01OlOl))) AND (NOT (nl0000ll XOR nl01OlOO))) AND (NOT (nl0000lO XOR nl01OO1i))) AND (NOT (nl0000Oi XOR nl01OO1l))) AND (NOT (nl0000Ol XOR nl01OO1O))) AND (NOT (nl0000OO XOR nl01OO0i))) AND (NOT (nl000i1i XOR nl01OO0l))) AND (NOT (nl000i1l XOR nl01OO0O))) AND (NOT (nl000i1O XOR nl01OOii))) AND (NOT (nl000i0i XOR nl01OOil))) AND (NOT (nl000i0l XOR nl01OOiO))) AND (NOT (nl000i0O XOR nl01OOli))) AND (NOT (nl000iii XOR nl01OOll))) AND (NOT (nl000iil XOR nl01OOlO))) AND (NOT (nl000iiO XOR nl01OOOi))) AND (NOT (nl000ili XOR nl01OOOl))) AND (NOT (nl000ill XOR nl01OOOO))) AND (NOT (nl000ilO XOR nl00111i))) AND (NOT (nl000iOi XOR nl00111l))) AND (NOT (nl000iOl XOR nl00111O))) AND (NOT (nl000iOO XOR nl00110i))) AND (NOT (nl000l1i XOR nl00110l))) AND (NOT (nl000l1l XOR nl00110O))) AND (NOT (nl000l1O XOR nl0011ii))) AND (NOT (nl000l0i XOR nl0011il))) AND (NOT (nl000l0l XOR nl0011iO))) AND (NOT (nl000l0O XOR nl0011li))) AND (NOT (nl000lii XOR nl0011ll))) AND (NOT (nl000lil XOR nl0011lO))) AND (NOT (nl000liO XOR nl0011Oi))) AND (NOT (nl000lli XOR nl0011Ol))) AND (NOT (nl000lll XOR nl0011OO))) AND (NOT (nl000llO XOR nl00101i))) AND (NOT (nl000lOi XOR nl00101l))) AND (NOT (nl000lOl XOR nl00101O))) AND (NOT (nl00ilOO XOR nl00100i))); + niOO1lO1i <= (nl01i1ii XOR nl010OOO); + niOO1lO1l <= (nl01i0OO XOR nl01i0il); + niOO1lO1O <= (nl01illl AND nl01il1l); + niOO1lOii <= (nl01Olli XOR nl01Ol1O); + niOO1lOil <= (nl00iO1i AND nl000lOO); + niOO1lOiO <= (nl00Olli XOR nl00Olil); + niOO1lOli <= (((((((((((((((((((((((((((((((((((((NOT (nl0i00li XOR nl00OlOl)) AND (NOT (nl0i00ll XOR nl00OlOO))) AND (NOT (nl0i00lO XOR nl00OO1i))) AND (NOT (nl0i00Oi XOR nl00OO1l))) AND (NOT (nl0i00Ol XOR nl00OO1O))) AND (NOT (nl0i00OO XOR nl00OO0i))) AND (NOT (nl0i0i1i XOR nl00OO0l))) AND (NOT (nl0i0i1l XOR nl00OO0O))) AND (NOT (nl0i0i1O XOR nl00OOii))) AND (NOT (nl0i0i0i XOR nl00OOil))) AND (NOT (nl0i0i0l XOR nl00OOiO))) AND (NOT (nl0i0i0O XOR nl00OOli))) AND (NOT (nl0i0iii XOR nl00OOll))) AND (NOT (nl0i0iil XOR nl00OOlO))) AND (NOT (nl0i0iiO XOR nl00OOOi))) AND (NOT (nl0i0ili XOR nl00OOOl))) AND (NOT (nl0i0ill XOR nl00OOOO))) AND (NOT (nl0i0ilO XOR nl0i111i))) AND (NOT (nl0i0iOi XOR nl0i111l))) AND (NOT (nl0i0iOl XOR nl0i111O))) AND (NOT (nl0i0iOO XOR nl0i110i))) AND (NOT (nl0i0l1i XOR nl0i110l))) AND (NOT (nl0i0l1l XOR nl0i110O))) AND (NOT (nl0i0l1O XOR nl0i11ii))) AND (NOT (nl0i0l0i XOR nl0i11il))) AND (NOT (nl0i0l0l XOR nl0i11iO))) AND (NOT (nl0i0l0O XOR nl0i11li))) AND (NOT (nl0i0lii XOR nl0i11ll))) AND (NOT (nl0i0lil XOR nl0i11lO))) AND (NOT (nl0i0liO XOR nl0i11Oi))) AND (NOT (nl0i0lli XOR nl0i11Ol))) AND (NOT (nl0i0lll XOR nl0i11OO))) AND (NOT (nl0i0llO XOR nl0i101i))) AND (NOT (nl0i0lOi XOR nl0i101l))) AND (NOT (nl0i0lOl XOR nl0i101O))) AND (NOT (nl0i0lOO XOR nl0i100i))) AND (NOT (nl0iiO1i XOR nl0i100l))); + niOO1lOll <= (nl00Olll XOR nl00Ol0i); + niOO1lOlO <= (nl0iiO1l AND nl0i0O1i); + niOO1lOOi <= (nl0illOl OR wire_nl0il0iO_o); + niOO1lOOl <= (wire_niOOO0O_w_lg_nl0illOl7062w(0) AND wire_nl0il0ll_o); + niOO1lOOO <= (nl0iO0lO OR wire_nl0ili0i_o); + niOO1O00i <= (((((((((((wire_niOOO0O_w_lg_nl0O11il7179w(0) AND wire_niOOO0O_w_lg_nl0O11ii7180w(0)) AND wire_niOOO0O_w_lg_nl0O110O7182w(0)) AND wire_niOOO0O_w_lg_nl0O110l7184w(0)) AND wire_niOOO0O_w_lg_nl0O110i7186w(0)) AND wire_niOOO0O_w_lg_nl0O111O7188w(0)) AND wire_niOOO0O_w_lg_nl0O111l7190w(0)) AND wire_niOOO0O_w_lg_nl0O111i7192w(0)) AND wire_niOOO0O_w_lg_nl0lOOOO7194w(0)) AND wire_niOOO0O_w_lg_nl0lOOOl7196w(0)) AND wire_niOOO0O_w_lg_nl0lOOOi7198w(0)) AND wire_niOOO0O_w_lg_nl0ll11l7200w(0)); + niOO1O00l <= (((((((((((wire_niOOO0O_w_lg_nl0O1i0l7156w(0) AND wire_niOOO0O_w_lg_nl0O1i0i7157w(0)) AND wire_niOOO0O_w_lg_nl0O1i1O7159w(0)) AND wire_niOOO0O_w_lg_nl0O1i1l7161w(0)) AND wire_niOOO0O_w_lg_nl0O1i1i7163w(0)) AND wire_niOOO0O_w_lg_nl0O10OO7165w(0)) AND wire_niOOO0O_w_lg_nl0O10Ol7167w(0)) AND wire_niOOO0O_w_lg_nl0O10Oi7169w(0)) AND wire_niOOO0O_w_lg_nl0O10lO7171w(0)) AND wire_niOOO0O_w_lg_nl0O10ll7173w(0)) AND wire_niOOO0O_w_lg_nl0O10li7175w(0)) AND wire_niOOO0O_w_lg_nl0O10iO7177w(0)); + niOO1O00O <= (((((((wire_niOOO0O_w_lg_nl0O101i7141w(0) AND wire_niOOO0O_w_lg_nl0O11OO7142w(0)) AND wire_niOOO0O_w_lg_nl0O11Ol7144w(0)) AND wire_niOOO0O_w_lg_nl0O11Oi7146w(0)) AND wire_niOOO0O_w_lg_nl0O11lO7148w(0)) AND wire_niOOO0O_w_lg_nl0O11ll7150w(0)) AND wire_niOOO0O_w_lg_nl0O11li7152w(0)) AND wire_niOOO0O_w_lg_nl0O11iO7154w(0)); + niOO1O01i <= (niOO1O01l AND (niOO1O0Oi AND niOO1O0iO)); + niOO1O01l <= ((nl0O1l0l AND nl0O10il) AND (niOO1O0OO AND niOO1O0ll)); + niOO1O01O <= (niOO1O1OO AND niOO1O0Oi); + niOO1O0ii <= (((((((wire_niOOO0O_w_lg_nl0O1iOi7126w(0) AND wire_niOOO0O_w_lg_nl0O1ilO7127w(0)) AND wire_niOOO0O_w_lg_nl0O1ill7129w(0)) AND wire_niOOO0O_w_lg_nl0O1ili7131w(0)) AND wire_niOOO0O_w_lg_nl0O1iiO7133w(0)) AND wire_niOOO0O_w_lg_nl0O1iil7135w(0)) AND wire_niOOO0O_w_lg_nl0O1iii7137w(0)) AND wire_niOOO0O_w_lg_nl0O1i0O7139w(0)); + niOO1O0il <= (niOO1O0li AND niOO1O0iO); + niOO1O0iO <= ((wire_niOOO0O_w_lg_nl0O100i7211w(0) AND wire_niOOO0O_w_lg_nl0O101O7212w(0)) AND wire_niOOO0O_w_lg_nl0O101l7214w(0)); + niOO1O0li <= ((nl0O10il AND nl0O10ii) AND niOO1O0ll); + niOO1O0ll <= (wire_niOOO0O_w_lg_nl0O100O7209w(0) AND nl0O100l); + niOO1O0lO <= (niOO1O0Ol AND niOO1O0Oi); + niOO1O0Oi <= ((wire_niOOO0O_w_lg_nl0O1l1i7204w(0) AND wire_niOOO0O_w_lg_nl0O1iOO7205w(0)) AND wire_niOOO0O_w_lg_nl0O1iOl7207w(0)); + niOO1O0Ol <= ((nl0O1l0l AND nl0O1l0i) AND niOO1O0OO); + niOO1O0OO <= (wire_niOOO0O_w_lg_nl0O1l1O7202w(0) AND nl0O1l1l); + niOO1O10i <= (niOO1O1OO AND niOO1O1il); + niOO1O10l <= (niOO1O0li AND niOO1O10O); + niOO1O10O <= ((wire_niOOO0O_w_lg_nl0O100i7211w(0) AND wire_niOOO0O_w_lg_nl0O101O7212w(0)) AND nl0O101l); + niOO1O11i <= (wire_niOOO0O_w_lg_nl0iO0lO6992w(0) AND wire_nl0ili0O_o); + niOO1O11l <= (niOO1O1Ol AND niOO1O10O); + niOO1O11O <= (niOO1O01l AND (niOO1O1il AND niOO1O10O)); + niOO1O1ii <= (niOO1O0Ol AND niOO1O1il); + niOO1O1il <= ((wire_niOOO0O_w_lg_nl0O1l1i7204w(0) AND wire_niOOO0O_w_lg_nl0O1iOO7205w(0)) AND nl0O1iOl); + niOO1O1iO <= (nl0li1Oi OR wire_nl0l0liO_o); + niOO1O1li <= (wire_niOOO0O_w_lg_nl0li1Oi6742w(0) AND wire_nl0l0lll_o); + niOO1O1ll <= (nl0lilll OR wire_nl0l0O0i_o); + niOO1O1lO <= (wire_niOOO0O_w_lg_nl0lilll6672w(0) AND wire_nl0l0O0O_o); + niOO1O1Oi <= (niOO1O1Ol AND niOO1O0iO); + niOO1O1Ol <= (nl0O10il AND niOO1O0ll); + niOO1O1OO <= (nl0O1l0l AND niOO1O0OO); + niOO1Oi0i <= (((((((((((wire_nl1000i_w_lg_nl0OO1Oi6388w(0) AND wire_nl1000i_w_lg_nl0OO1lO6389w(0)) AND wire_nl1000i_w_lg_nl0OO1ll6391w(0)) AND wire_nl1000i_w_lg_nl0OO1li6393w(0)) AND (NOT (nlliOl1li XOR nl0OO11l))) AND (NOT (nlliOl1ll XOR nl0OO11O))) AND (NOT (nlliOl1lO XOR nl0OO10i))) AND (NOT (nlliOl1Oi XOR nl0OO10l))) AND (NOT (nlliOl1Ol XOR nl0OO10O))) AND (NOT (nlliOl1OO XOR nl0OO1ii))) AND (NOT (nlliOl01i XOR nl0OO1il))) AND (NOT (nlliOl01l XOR nl0OO1iO))); + niOO1Oi0l <= (nl0OlOOl XOR nl0OlOii); + niOO1Oi0O <= (nl0OOOll XOR nl0OOOiO); + niOO1Oi1i <= (wire_w_lg_w_k_hip_range2413w2429w(0) OR wire_nl1000i_w_lg_nl0OiO0O6419w(0)); + niOO1Oi1l <= (wire_w_lg_w_k_hip_range2413w2429w(0) OR wire_w_lg_w_k_hip_range2413w6420w(0)); + niOO1Oi1O <= (nl0OlOOi XOR nl0OlOll); + niOO1Oiii <= (((((NOT (wire_nlliOl1ii_o(1) XOR nl0OOOOO)) AND (NOT (wire_nlliOl1ii_o(2) XOR nli1111i))) AND (NOT (wire_nlliOl1ii_o(3) XOR nli1111l))) AND (NOT (wire_nlliOl1ii_o(4) XOR nli1111O))) AND (NOT (wire_nlliOl1ii_o(5) XOR nli1110i))); + niOO1Oiil <= (nl0OOOlO XOR nl0OOO0l); + niOO1OiiO <= (niOO1Oili XOR nli101OO); + niOO1Oili <= (niOO1Ol1i XOR nli1001i); + niOO1Oill <= (niOO1OilO XOR nli101ll); + niOO1OilO <= (niOO1OiOi XOR nli101lO); + niOO1OiOi <= (nli101Ol XOR nli101Oi); + niOO1OiOl <= ((niOO1OO1l AND (NOT (niOO1Ol1l OR wire_w_lg_niOO1Ol1i6094w(0)))) XOR nli1001O); + niOO1OiOO <= ((wire_w_lg_niOO1Ol1i6094w(0) AND wire_w_lg_niOO1OO1l6096w(0)) XOR nli1001l); + niOO1Ol0i <= ((nli1001l XOR nli1001i) XOR nli1001O); + niOO1Ol0l <= ((niOO1OO1l AND wire_w_lg_niOO1Ol0O6083w(0)) XOR nli101OO); + niOO1Ol0O <= (((nli1001i XOR nli101OO) XOR nli1001l) XOR nli1001O); + niOO1Ol1i <= (nli1001O XOR nli1001l); + niOO1Ol1l <= (wire_w_lg_niOO1Ol0O6083w(0) OR wire_w_lg_niOO1Ol0i6088w(0)); + niOO1Ol1O <= ((wire_w_lg_niOO1Ol0i6088w(0) AND (niOO1OO1l AND niOO1Ol0O)) XOR nli1001i); + niOO1Olii <= (nli1i1OO XOR nli1i1Ol); + niOO1Olil <= (nli1i0lO XOR nli1i0ll); + niOO1OliO <= (nli1i1Oi XOR niOO1Olii); + niOO1Olli <= (nli1i0li XOR niOO1Olil); + niOO1Olll <= (nli1i1lO XOR niOO1OliO); + niOO1OllO <= (nli1i0iO XOR niOO1Olli); + niOO1OlOi <= (nli1i00i XOR nli1i01O); + niOO1OlOl <= (wire_w_lg_niOO1OO1i5988w(0) OR wire_w_lg_niOO1OlOO5989w(0)); + niOO1OlOO <= ((nli1i01O XOR nli1i01l) XOR nli1i00i); + niOO1OO0i <= ((NOT wire_nli110ii_q(130)) AND (NOT wire_nli110ii_q(131))); + niOO1OO0l <= (nll0OilO AND (k_gbl_hip(33) AND k_hip(0))); + niOO1OO0O <= wire_w_lg_w_k_gbl_hip_range1050w3435w(0); + niOO1OO1i <= (((nli1i01l XOR nli1i01i) XOR nli1i01O) XOR nli1i00i); + niOO1OO1l <= (wire_nli1l0il_dataout AND nli1l0ii); + niOO1OO1O <= (wire_nli110ii_q(129) AND wire_nli110ii_q(130)); + niOO1OOii <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND nlliO01i); + niOO1OOil <= (wire_w_lg_w_k_gbl_hip_range1050w1051w(0) AND wire_nl1000i_w_lg_nlliO01i5754w(0)); + niOO1OOiO <= (((((((((wire_nl1000i_w_lg_nllilOOO5930w(0) AND wire_nl1000i_w_lg_nllilOOl5931w(0)) AND wire_nl1000i_w_lg_nllilOOi5933w(0)) AND wire_nl1000i_w_lg_nllilOlO5935w(0)) AND wire_nl1000i_w_lg_nllilOll5937w(0)) AND wire_nl1000i_w_lg_nllilOli5939w(0)) AND wire_nl1000i_w_lg_nllilOiO5941w(0)) AND wire_nl1000i_w_lg_nllilOil5943w(0)) AND wire_nl1000i_w_lg_nllilOii5945w(0)) AND nllilO0O); + niOO1OOli <= (nll0OilO AND (k_gbl_hip(33) AND k_hip(0))); + niOO1OOll <= (nll0Oili AND (nll0OilO AND (k_gbl_hip(33) AND k_hip(0)))); + niOO1OOlO <= (wire_nl1000i_w_lg_nll0OilO5675w(0) AND (k_gbl_hip(33) AND k_hip(0))); + niOO1OOOi <= wire_w_lg_w_k_hip_range2413w5734w(0); + niOO1OOOl <= wire_w_lg_w_k_hip_range2413w5732w(0); + niOO1OOOO <= wire_w_lg_w_k_hip_range2413w5730w(0); + powerdown0 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + powerdown1 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + powerdown2 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + powerdown3 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + powerdown4 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + powerdown5 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + powerdown6 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + powerdown7 <= ( wire_niil0i0O_dataout & wire_niil0i0l_dataout); + prstn <= wire_niO001iO_dataout; + rate <= n11l0Oil; + reset_status <= niO0111i; + rx_bar_dec_vc0 <= ( wire_nl01iOO_dataout & wire_nl01iOl_dataout & wire_nl01iOi_dataout & wire_nl01ilO_dataout & wire_nl01ill_dataout & wire_nl01ili_dataout & wire_nl01iiO_dataout & wire_nl01iil_dataout); + rx_bar_dec_vc1 <= ( wire_nl01iii_dataout & wire_nl01i0O_dataout & wire_nl01i0l_dataout & wire_nl01i0i_dataout & wire_nl01i1O_dataout & wire_nl01i1l_dataout & wire_nl01i1i_dataout & wire_nl010OO_dataout); + rx_be_vc0_0 <= ( wire_nl010Ol_dataout & wire_nl010Oi_dataout & wire_nl010lO_dataout & wire_nl010ll_dataout & wire_nl010li_dataout & wire_nl010iO_dataout & wire_nl010il_dataout & wire_nl010ii_dataout); + rx_be_vc0_1 <= ( wire_nl0100O_dataout & wire_nl0100l_dataout & wire_nl0100i_dataout & wire_nl0101O_dataout & wire_nl0101l_dataout & wire_nl0101i_dataout & wire_nl011OO_dataout & wire_nl011Ol_dataout); + rx_be_vc1_0 <= ( wire_nl011Oi_dataout & wire_nl011lO_dataout & wire_nl011ll_dataout & wire_nl011li_dataout & wire_nl011iO_dataout & wire_nl011il_dataout & wire_nl011ii_dataout & wire_nl0110O_dataout); + rx_be_vc1_1 <= ( wire_nl0110l_dataout & wire_nl0110i_dataout & wire_nl0111O_dataout & wire_nl0111l_dataout & wire_nl0111i_dataout & wire_nl1OOOO_dataout & wire_nl1OOOl_dataout & wire_nl1OOOi_dataout); + rx_data_vc0_0 <= ( nli01i1i & nli010OO & nli010Ol & nli010Oi & nli010lO & nli010ll & nli010li & nli010iO & nli010il & nli010ii & nli0100O & nli0100l & nli0100i & nli0101O & nli0101l & nli0101i & nli011OO & nli011Ol & nli011Oi & nli011lO & nli011ll & nli011li & nli011iO & nli011il & nli011ii & nli0110O & nli0110l & nli0110i & nli0111O & nli0111l & nli0111i & nli1OOOO & nli1OOOl & nli1OOOi & nli1OOlO & nli1OOll & nli1OOli & nli1OOiO & nli1OOil & nli1OOii & nli1OO0O & nli1OO0l & nli1OO0i & nli1OO1O & nli1OO1l & nli1OO1i & nli1OlOO & nli1OlOl & nli1OlOi & nli1OllO & nli1Olll & nli1Olli & nli1OliO & nli1Olil & nli1Olii & nli1Ol0O & nli1Ol0l & nli1Ol0i & nli1Ol1O & nli1Ol1l & nli1Ol1i & nli1OiOO & nli1OiOl & nli1OiOi); + rx_data_vc0_1 <= ( nli1OilO & nli1Oill & nli1Oili & nli1OiiO & nli1Oiil & nli1Oiii & nli1Oi0O & nli1Oi0l & nli1Oi0i & nli1Oi1O & nli1Oi1l & nli1Oi1i & nli1O0OO & nli1O0Ol & nli1O0Oi & nli1O0lO & nli1O0ll & nli1O0li & nli1O0iO & nli1O0il & nli1O0ii & nli1O00O & nli1O00l & nli1O00i & nli1O01O & nli1O01l & nli1O01i & nli1O1OO & nli1O1Ol & nli1O1Oi & nli1O1lO & nli1O1ll & nli1O1li & nli1O1iO & nli1O1il & nli1O1ii & nli1O10O & nli1O10l & nli1O10i & nli1O11O & nli1O11l & nli1O11i & nli1lOOO & nli1lOOl & nli1lOOi & nli1lOlO & nli1lOll & nli1lOli & nli1lOiO & nli1lOil & nli1lOii & nli1lO0O & nli1lO0l & nli1lO0i & nli1lO1O & nli1lO1l & nli1lO1i & nli1llOO & nli1llOl & nli1llOi & nli1lllO & nli1llll & nli1llli & nli1lliO); + rx_data_vc1_0 <= ( wire_nl1OOil_dataout & wire_nl1OOii_dataout & wire_nl1OO0O_dataout & wire_nl1OO0l_dataout & wire_nl1OO0i_dataout & wire_nl1OO1O_dataout & wire_nl1OO1l_dataout & wire_nl1OO1i_dataout & wire_nl1OlOO_dataout & wire_nl1OlOl_dataout & wire_nl1OlOi_dataout & wire_nl1OllO_dataout & wire_nl1Olll_dataout & wire_nl1Olli_dataout & wire_nl1OliO_dataout & wire_nl1Olil_dataout & wire_nl1Olii_dataout & wire_nl1Ol0O_dataout & wire_nl1Ol0l_dataout & wire_nl1Ol0i_dataout & wire_nl1Ol1O_dataout & wire_nl1Ol1l_dataout & wire_nl1Ol1i_dataout & wire_nl1OiOO_dataout & wire_nl1OiOl_dataout & wire_nl1OiOi_dataout & wire_nl1OilO_dataout & wire_nl1Oill_dataout & wire_nl1Oili_dataout & wire_nl1OiiO_dataout & wire_nl1Oiil_dataout & wire_nl1Oiii_dataout & wire_nl1Oi0O_dataout & wire_nl1Oi0l_dataout & wire_nl1Oi0i_dataout & wire_nl1Oi1O_dataout & wire_nl1Oi1l_dataout & wire_nl1Oi1i_dataout & wire_nl1O0OO_dataout & wire_nl1O0Ol_dataout & wire_nl1O0Oi_dataout & wire_nl1O0lO_dataout & wire_nl1O0ll_dataout & wire_nl1O0li_dataout & wire_nl1O0iO_dataout & wire_nl1O0il_dataout & wire_nl1O0ii_dataout & wire_nl1O00O_dataout & wire_nl1O00l_dataout & wire_nl1O00i_dataout & wire_nl1O01O_dataout & wire_nl1O01l_dataout & wire_nl1O01i_dataout & wire_nl1O1OO_dataout & wire_nl1O1Ol_dataout & wire_nl1O1Oi_dataout & wire_nl1O1lO_dataout & wire_nl1O1ll_dataout & wire_nl1O1li_dataout & wire_nl1O1iO_dataout & wire_nl1O1il_dataout & wire_nl1O1ii_dataout & wire_nl1O10O_dataout & wire_nl1O10l_dataout); + rx_data_vc1_1 <= ( wire_nl1O10i_dataout & wire_nl1O11O_dataout & wire_nl1O11l_dataout & wire_nl1O11i_dataout & wire_nl1lOOO_dataout & wire_nl1lOOl_dataout & wire_nl1lOOi_dataout & wire_nl1lOlO_dataout & wire_nl1lOll_dataout & wire_nl1lOli_dataout & wire_nl1lOiO_dataout & wire_nl1lOil_dataout & wire_nl1lOii_dataout & wire_nl1lO0O_dataout & wire_nl1lO0l_dataout & wire_nl1lO0i_dataout & wire_nl1lO1O_dataout & wire_nl1lO1l_dataout & wire_nl1lO1i_dataout & wire_nl1llOO_dataout & wire_nl1llOl_dataout & wire_nl1llOi_dataout & wire_nl1lllO_dataout & wire_nl1llll_dataout & wire_nl1llli_dataout & wire_nl1lliO_dataout & wire_nl1llil_dataout & wire_nl1llii_dataout & wire_nl1ll0O_dataout & wire_nl1ll0l_dataout & wire_nl1ll0i_dataout & wire_nl1ll1O_dataout & wire_nl1ll1l_dataout & wire_nl1ll1i_dataout & wire_nl1liOO_dataout & wire_nl1liOl_dataout & wire_nl1liOi_dataout & wire_nl1lilO_dataout & wire_nl1lill_dataout & wire_nl1lili_dataout & wire_nl1liiO_dataout & wire_nl1liil_dataout & wire_nl1liii_dataout & wire_nl1li0O_dataout & wire_nl1li0l_dataout & wire_nl1li0i_dataout & wire_nl1li1O_dataout & wire_nl1li1l_dataout & wire_nl1li1i_dataout & wire_nl1l0OO_dataout & wire_nl1l0Ol_dataout & wire_nl1l0Oi_dataout & wire_nl1l0lO_dataout & wire_nl1l0ll_dataout & wire_nl1l0li_dataout & wire_nl1l0iO_dataout & wire_nl1l0il_dataout & wire_nl1l0ii_dataout & wire_nl1l00O_dataout & wire_nl1l00l_dataout & wire_nl1l00i_dataout & wire_nl1l01O_dataout & wire_nl1l01l_dataout & wire_nl1l01i_dataout); + rx_eop_vc0_0 <= nli01ill; + rx_eop_vc0_1 <= ((nli01ill XOR nli01ili) XOR (NOT (niOO0O01O2 XOR niOO0O01O1))); + rx_eop_vc1_0 <= n1OlO0l; + rx_eop_vc1_1 <= (n1OlO0l XOR n1OlO0i); + rx_err_vc0 <= nli1l0Ol; + rx_err_vc1 <= n1O0O1i; + rx_fifo_empty_vc0 <= nli11l1O; + rx_fifo_empty_vc1 <= n1lO01l; + rx_fifo_full_vc0 <= nli110il; + rx_fifo_full_vc1 <= n1llOii; + rx_fifo_rdp0 <= ( nli11OOi & nli11OlO & nli11Oll & nli11Oli); + rx_fifo_rdp1 <= ( n1lOilO & n1lOill & n1lOili & n1lOiiO); + rx_fifo_wrp0 <= ( nli1011l & nli1011i & nli11OOO & nli11OOl); + rx_fifo_wrp1 <= ( n1lOl1i & n1lOiOO & n1lOiOl & n1lOiOi); + rx_sop_vc0_0 <= nli01iOi; + rx_sop_vc0_1 <= nli01ilO; + rx_sop_vc1_0 <= n1OlOii; + rx_sop_vc1_1 <= n1OlO0O; + rx_valid_vc0 <= nli01iOl; + rx_valid_vc1 <= n1OlOil; + rxpolarity0 <= nlOlO10iO; + rxpolarity1 <= nlOlO1ilO; + rxpolarity2 <= nlOlO1iOi; + rxpolarity3 <= nlOlO1iOl; + rxpolarity4 <= nlOlO1iOO; + rxpolarity5 <= nlOlO1l1i; + rxpolarity6 <= nlOlO1l1l; + rxpolarity7 <= nlOlO1l1O; + serr_out <= niOOi01l; + successful_speed_negotiation_int <= n11O0ill; + swdn_wake <= nl11OiiO; + swup_hotrst <= nl111O1O; + test_out_hip <= ( wire_niOOli1Ol_dataout & wire_niOOli1Oi_dataout & wire_niOOli1lO_dataout & wire_niOOli1ll_dataout & wire_niOOli1li_dataout & wire_niOOli1iO_dataout & wire_niOOli1il_dataout & wire_niOOli1ii_dataout & wire_niOOli10O_dataout & wire_niOOli10l_dataout & wire_niOOli10i_dataout & wire_niOOli11O_dataout & wire_niOOli11l_dataout & wire_niOOli11i_dataout & wire_niOOl0OOO_dataout & wire_niOOl0OOl_dataout & wire_niOOl0OOi_dataout & wire_niOOl0OlO_dataout & wire_niOOl0Oll_dataout & wire_niOOl0Oli_dataout & wire_niOOl0OiO_dataout & wire_niOOl0Oil_dataout & wire_niOOl0Oii_dataout & wire_niOOl0O0O_dataout & wire_niOOl0O0l_dataout & wire_niOOl0O0i_dataout & wire_niOOl0O1O_dataout & wire_niOOl0O1l_dataout & wire_niOOl0O1i_dataout & wire_niOOl0lOO_dataout & wire_niOOl0lOl_dataout & wire_niOOl0lOi_dataout & wire_niOOl0llO_dataout & wire_niOOl0lll_dataout & wire_niOOl0lli_dataout & wire_niOOl0liO_dataout & wire_niOOl0lil_dataout & wire_niOOl0lii_dataout & wire_niOOl0l0O_dataout & wire_niOOl0l0l_dataout & wire_niOOl0l0i_dataout & wire_niOOl0l1O_dataout & wire_niOOl0l1l_dataout & wire_niOOl0l1i_dataout & wire_niOOl0iOO_dataout & wire_niOOl0iOl_dataout & wire_niOOl0iOi_dataout & wire_niOOl0ilO_dataout & wire_niOOl0ill_dataout & wire_niOOl0ili_dataout & wire_niOOl0iiO_dataout & wire_niOOl0iil_dataout & wire_niOOl0iii_dataout & wire_niOOl0i0O_dataout & wire_niOOl0i0l_dataout & wire_niOOl0i0i_dataout & wire_niOOl0i1O_dataout & wire_niOOl0i1l_dataout & wire_niOOl0i1i_dataout & wire_niOOl00OO_dataout & wire_niOOl00Ol_dataout & wire_niOOl00Oi_dataout & wire_niOOl00lO_dataout & wire_niOOl00ll_dataout); + tl_app_inta_ack <= nl11OO1i; + tl_app_msi_ack <= nl101i1l; + tl_cfg_add <= ( niO0lOOi & niO0lOlO & niO0lOll & niO0lOli); + tl_cfg_ctl <= ( niO0lOiO & niO0lOil & niO0lOii & niO0lO0O & niO0lO0l & niO0lO0i & niO0lO1O & niO0lO1l & niO0lO1i & niO0llOO & niO0llOl & niO0llOi & niO0lllO & niO0llll & niO0llli & niO0lliO & niO0llil & niO0llii & niO0ll0O & niO0ll0l & niO0ll0i & niO0ll1O & niO0ll1l & niO0ll1i & niO0liOO & niO0liOl & niO0liOi & niO0lilO & niO0lill & niO0lili & niO0liiO & niO0liil); + tl_cfg_ctl_wr <= niO0OOOl; + tl_cfg_sts <= ( niO00O0l & niO00O0i & niO00O1O & niO00O1l & niO00O1i & niO00lOO & niO00lOl & niO00lOi & niO00llO & niO00lll & niO00lli & niO00liO & niO00lil & niO00lii & niO00l0O & niO00l0l & niO00l0i & niO00l1O & niO00l1l & niO00l1i & niO00iOO & niO00iOl & niO00iOi & niO00ilO & niO00ill & niO00ili & niO00iiO & niO00iil & niO00iii & niO00i0O & niO00i0l & niO00i0i & niO00i1O & niO00i1l & niO00i1i & niO000OO & niO000Ol & niO000Oi & niO000lO & niO000ll & niO000li & niO000iO & niO000il & niO000ii & niO0000O & niO0000l & niO0000i & niO0001O & niO0001l & niO0001i & niO001OO & niO001Ol & niO001Oi); + tl_cfg_sts_wr <= niO0l0li; + tl_pme_to_sr <= niOOO1ii; + tx_cred_vc0 <= ( wire_nl00ilO_dataout & wire_nl00ill_dataout & wire_nl00ili_dataout & wire_nl00iiO_dataout & wire_nl00iil_dataout & wire_nl00iii_dataout & wire_nl00i0O_dataout & wire_nl00i0l_dataout & wire_nl00i0i_dataout & wire_nl00i1O_dataout & wire_nl00i1l_dataout & wire_nl00i1i_dataout & wire_nl000OO_dataout & wire_nl000Ol_dataout & wire_nl000Oi_dataout & wire_nl000lO_dataout & wire_nl000ll_dataout & wire_nl000li_dataout & wire_nl000iO_dataout & wire_nl000il_dataout & wire_nl000ii_dataout & wire_nl0000O_dataout & wire_nl0000l_dataout & wire_nl0000i_dataout & wire_nl0001O_dataout & wire_nl0001l_dataout & wire_nl0001i_dataout & wire_nl001OO_dataout & wire_nl001Ol_dataout & wire_nl001Oi_dataout & wire_nl001lO_dataout & wire_nl001ll_dataout & wire_nl001li_dataout & wire_nl001iO_dataout & wire_nl001il_dataout & wire_nl001ii_dataout); + tx_cred_vc1 <= ( wire_nl0010O_dataout & wire_nl0010l_dataout & wire_nl0010i_dataout & wire_nl0011O_dataout & wire_nl0011l_dataout & wire_nl0011i_dataout & wire_nl01OOO_dataout & wire_nl01OOl_dataout & wire_nl01OOi_dataout & wire_nl01OlO_dataout & wire_nl01Oll_dataout & wire_nl01Oli_dataout & wire_nl01OiO_dataout & wire_nl01Oil_dataout & wire_nl01Oii_dataout & wire_nl01O0O_dataout & wire_nl01O0l_dataout & wire_nl01O0i_dataout & wire_nl01O1O_dataout & wire_nl01O1l_dataout & wire_nl01O1i_dataout & wire_nl01lOO_dataout & wire_nl01lOl_dataout & wire_nl01lOi_dataout & wire_nl01llO_dataout & wire_nl01lll_dataout & wire_nl01lli_dataout & wire_nl01liO_dataout & wire_nl01lil_dataout & wire_nl01lii_dataout & wire_nl01l0O_dataout & wire_nl01l0l_dataout & wire_nl01l0i_dataout & wire_nl01l1O_dataout & wire_nl01l1l_dataout & wire_nl01l1i_dataout); + tx_deemph <= n11i110i; + tx_fifo_empty_vc0 <= nlll0lll; + tx_fifo_empty_vc1 <= n0OOOii; + tx_fifo_full_vc0 <= nlllliiO; + tx_fifo_full_vc1 <= ni10l0l; + tx_fifo_rdp_vc0 <= ( nlllliil & nlllliii & nlllli0O & nlllli0l); + tx_fifo_rdp_vc1 <= ( ni10l0i & ni10l1O & ni10l1l & ni10l1i); + tx_fifo_wrp_vc0 <= ( nlllli0i & nlllli1O & nlllli1l & nlllli1i); + tx_fifo_wrp_vc1 <= ( ni10iOO & ni10iOl & ni10iOi & ni10ilO); + tx_margin <= ( n11O01Oi & n11O01lO & n11O01ll); + tx_ready_vc0 <= wire_niOOO0O_w_lg_nlllliiO546w(0); + tx_ready_vc1 <= wire_ni01lOi_w_lg_ni10l0l762w(0); + txcompl0 <= n1OliiOi; + txcompl1 <= n01i101l; + txcompl2 <= n001iO0O; + txcompl3 <= n00O1ili; + txcompl4 <= n0iil1Ol; + txcompl5 <= n0l01O1O; + txcompl6 <= n0lOliii; + txcompl7 <= n0Ol01ll; + txdata0 <= ( n1Oli0ll & n1Oli0li & n1Oli0iO & n1Oli0il & n1Oli0ii & n1Oli00O & n1Oli00l & n1Oli00i); + txdata1 <= ( n010OOOO & n010OOOl & n010OOOi & n010OOlO & n010OOll & n010OOli & n010OOiO & n010OOil); + txdata2 <= ( n001il0i & n001il1O & n001il1l & n001il1i & n001iiOO & n001iiOl & n001iiOi & n001iilO); + txdata3 <= ( n00O10il & n00O10ii & n00O100O & n00O100l & n00O100i & n00O101O & n00O101l & n00O101i); + txdata4 <= ( n0iiiOlO & n0iiiOll & n0iiiOli & n0iiiOiO & n0iiiOil & n0iiiOii & n0iiiO0O & n0iiiO0l); + txdata5 <= ( n0l01l1i & n0l01iOO & n0l01iOl & n0l01iOi & n0l01ilO & n0l01ill & n0l01ili & n0l01iiO); + txdata6 <= ( n0lOl00l & n0lOl00i & n0lOl01O & n0lOl01l & n0lOl01i & n0lOl1OO & n0lOl1Ol & n0lOl1Oi); + txdata7 <= ( n0Ol1OiO & n0Ol1Oil & n0Ol1Oii & n0Ol1O0O & n0Ol1O0l & n0Ol1O0i & n0Ol1O1O & n0Ol1O1l); + txdatak0 <= n1Oli0lO; + txdatak1 <= n01i111i; + txdatak2 <= n001il0l; + txdatak3 <= n00O10iO; + txdatak4 <= n0iiiOOi; + txdatak5 <= n0l01l1l; + txdatak6 <= n0lOl00O; + txdatak7 <= n0Ol1Oli; + txdetectrx0 <= n1l0001O; + txdetectrx1 <= n1l0000i; + txdetectrx2 <= n1l0000l; + txdetectrx3 <= n1l0000O; + txdetectrx4 <= n1l000ii; + txdetectrx5 <= n1l000il; + txdetectrx6 <= n1l000iO; + txdetectrx7 <= n1l000li; + txelecidle0 <= wire_niil0l0O_dataout; + txelecidle1 <= wire_niil0l1i_dataout; + txelecidle2 <= wire_niil0iOl_dataout; + txelecidle3 <= wire_niil0iOi_dataout; + txelecidle4 <= wire_niil0ilO_dataout; + txelecidle5 <= wire_niil0ill_dataout; + txelecidle6 <= wire_niil0ili_dataout; + txelecidle7 <= wire_niil0iiO_dataout; + urstn <= wire_niO0010l_dataout; + usrst <= wire_niO01O0O_dataout; + w_ni00O11O10767w <= ((((((((((((((((((((((((((((((((((((((((((((((((((wire_niO01ill_w_lg_ni0i0i1l10666w(0) AND wire_niO01ill_w_lg_ni0i0i1i10667w(0)) AND wire_niO01ill_w_lg_ni0i00OO10669w(0)) AND wire_niO01ill_w_lg_ni0i00Ol10671w(0)) AND wire_niO01ill_w_lg_ni0i00Oi10673w(0)) AND wire_niO01ill_w_lg_ni0i00lO10675w(0)) AND wire_niO01ill_w_lg_ni0i00ll10677w(0)) AND wire_niO01ill_w_lg_ni0i00li10679w(0)) AND wire_niO01ill_w_lg_ni0i00iO10681w(0)) AND wire_niO01ill_w_lg_ni0i00il10683w(0)) AND wire_niO01ill_w_lg_ni0i00ii10685w(0)) AND wire_niO01ill_w_lg_ni0i000O10687w(0)) AND wire_niO01ill_w_lg_ni0i000l10689w(0)) AND wire_niO01ill_w_lg_ni0i000i10691w(0)) AND wire_niO01ill_w_lg_ni0i001O10693w(0)) AND wire_niO01ill_w_lg_ni0i001l10695w(0)) AND wire_niO01ill_w_lg_ni0i001i10697w(0)) AND wire_niO01ill_w_lg_ni0i01OO10699w(0)) AND wire_niO01ill_w_lg_ni0i01Ol10701w(0)) AND wire_niO01ill_w_lg_ni0i01Oi10703w(0)) AND wire_niO01ill_w_lg_ni0i01lO10705w(0)) AND wire_niO01ill_w_lg_ni0i01ll10707w(0)) AND wire_niO01ill_w_lg_ni0i01li10709w(0)) AND wire_niO01ill_w_lg_ni0i01iO10711w(0)) AND wire_niO01ill_w_lg_ni0i01il10713w(0)) AND wire_niO01ill_w_lg_ni0i01ii10715w(0)) AND wire_niO01ill_w_lg_ni0i010O10717w(0)) AND wire_niO01ill_w_lg_ni0i010l10719w(0)) AND wire_niO01ill_w_lg_ni0i010i10721w(0)) AND wire_niO01ill_w_lg_ni0i011O10723w(0)) AND wire_niO01ill_w_lg_ni0i011l10725w(0)) AND wire_niO01ill_w_lg_ni0i011i10727w(0)) AND wire_niO01ill_w_lg_ni0i1OOO10729w(0)) AND wire_niO01ill_w_lg_ni0i1OOl10731w(0)) AND wire_niO01ill_w_lg_ni0i1OOi10733w(0)) AND wire_niO01ill_w_lg_ni0i1OlO10735w(0)) AND wire_niO01ill_w_lg_ni0i1Oll10737w(0)) AND wire_niO01ill_w_lg_ni0i1Oli10739w(0)) AND wire_niO01ill_w_lg_ni0i1OiO10741w(0)) AND wire_niO01ill_w_lg_ni0i1Oil10743w(0)) AND wire_niO01ill_w_lg_ni0i1Oii10745w(0)) AND wire_niO01ill_w_lg_ni0i1O0O10747w(0)) AND wire_niO01ill_w_lg_ni0i1O0l10749w(0)) AND wire_niO01ill_w_lg_ni0i1O0i10751w(0)) AND wire_niO01ill_w_lg_ni0i1O1O10753w(0)) AND wire_niO01ill_w_lg_ni0i1O1l10755w(0)) AND wire_niO01ill_w_lg_ni0i1O1i10757w(0)) AND wire_niO01ill_w_lg_ni0i1lOO10759w +(0)) AND wire_niO01ill_w_lg_ni0i1lOl10761w(0)) AND wire_niO01ill_w_lg_ni0i1lOi10763w(0)) AND wire_niO01ill_w_lg_ni0i1llO10765w(0)); + w_nl0liO1Oi51818w <= (((((((((((((((((((((((((((((((((((((((((((((((((((NOT (niOil0O1l XOR (k_bar(4) AND wire_nilOii1i_dataout))) AND (NOT (niOil0O1O XOR (k_bar(5) AND wire_nilOii1l_dataout)))) AND (NOT (niOil0O0i XOR (k_bar(6) AND wire_nilOii1O_dataout)))) AND (NOT (niOil0O0l XOR (k_bar(7) AND wire_nilOii0i_dataout)))) AND (NOT (niOil0O0O XOR (k_bar(8) AND wire_nilOii0l_dataout)))) AND (NOT (niOil0Oii XOR (k_bar(9) AND wire_nilOii0O_dataout)))) AND (NOT (niOil0Oil XOR (k_bar(10) AND wire_nilOiiii_dataout)))) AND (NOT (niOil0OiO XOR (k_bar(11) AND wire_nilOiiil_dataout)))) AND (NOT (niOil0Oli XOR (k_bar(12) AND wire_nilOiiiO_dataout)))) AND (NOT (niOil0Oll XOR (k_bar(13) AND wire_nilOiili_dataout)))) AND (NOT (niOil0OlO XOR (k_bar(14) AND wire_nilOiill_dataout)))) AND (NOT (niOil0OOi XOR (k_bar(15) AND wire_nilOiilO_dataout)))) AND (NOT (niOil0OOl XOR (k_bar(16) AND wire_nilOiiOi_dataout)))) AND (NOT (niOil0OOO XOR (k_bar(17) AND wire_nilOiiOl_dataout)))) AND (NOT (niOili11i XOR (k_bar(18) AND wire_nilOiiOO_dataout)))) AND (NOT (niOili11l XOR (k_bar(19) AND wire_nilOil1i_dataout)))) AND (NOT (niOili11O XOR (k_bar(20) AND wire_nilOil1l_dataout)))) AND (NOT (niOili10i XOR (k_bar(21) AND wire_nilOil1O_dataout)))) AND (NOT (niOili10l XOR (k_bar(22) AND wire_nilOil0i_dataout)))) AND (NOT (niOili10O XOR (k_bar(23) AND wire_nilOil0l_dataout)))) AND (NOT (niOili1ii XOR (k_bar(24) AND wire_nilOil0O_dataout)))) AND (NOT (niOili1il XOR (k_bar(25) AND wire_nilOilii_dataout)))) AND (NOT (niOili1iO XOR (k_bar(26) AND wire_nilOilil_dataout)))) AND (NOT (niOili1li XOR (k_bar(27) AND wire_nilOiliO_dataout)))) AND (NOT (niOili1ll XOR (k_bar(28) AND wire_nilOilli_dataout)))) AND (NOT (niOili1lO XOR (k_bar(29) AND wire_nilOilll_dataout)))) AND (NOT (niOili1Oi XOR (k_bar(30) AND wire_nilOillO_dataout)))) AND (NOT (niOili1Ol XOR (k_bar(31) AND wire_nilOilOi_dataout)))) AND (NOT (niOii0lOi XOR (k_bar(32) AND wire_nilOilOl_dataout)))) AND (NOT (niOii0llO XOR (k_bar(33) AND wire_nilOilOO_dataout)))) AND (NOT (niOii0lll XOR (k_bar(34) AND + wire_nilOiO1i_dataout)))) AND (NOT (niOii0lli XOR (k_bar(35) AND wire_nilOiO1l_dataout)))) AND (NOT (niOil0i0i XOR niOii0lii))) AND (NOT (niOil0i0l XOR niOii0l0O))) AND (NOT (niOil0i0O XOR niOii0l0l))) AND (NOT (niOil0iii XOR niOii0l0i))) AND (NOT (niOil0iil XOR niOii0l1O))) AND (NOT (niOil0iiO XOR niOii0l1l))) AND (NOT (niOil0ili XOR niOii0l1i))) AND (NOT (niOil0ill XOR niOii0iOO))) AND (NOT (niOil0ilO XOR niOii0iOl))) AND (NOT (niOil0iOi XOR niOii0iOi))) AND (NOT (niOil0iOl XOR niOii0ilO))) AND (NOT (niOil0iOO XOR niOii0ill))) AND (NOT (niOil0l1i XOR niOii0ili))) AND (NOT (niOil0l1l XOR niOii0iiO))) AND (NOT (niOil0l1O XOR niOii0iil))) AND (NOT (niOil0l0i XOR niOii0iii))) AND (NOT (niOil0l0l XOR niOii0i0O))) AND (NOT (niOil0l0O XOR niOii0i0l))) AND (NOT (niOil0lii XOR niOii0i0i))); + w_nl0lO0Oii50931w <= (((((((((((((((((((((((((((((((((((((((((((((((((((NOT (niOil010l XOR (k_bar(68) AND wire_nilOii1i_dataout))) AND (NOT (niOil010O XOR (k_bar(69) AND wire_nilOii1l_dataout)))) AND (NOT (niOil01ii XOR (k_bar(70) AND wire_nilOii1O_dataout)))) AND (NOT (niOil01il XOR (k_bar(71) AND wire_nilOii0i_dataout)))) AND (NOT (niOil01iO XOR (k_bar(72) AND wire_nilOii0l_dataout)))) AND (NOT (niOil01li XOR (k_bar(73) AND wire_nilOii0O_dataout)))) AND (NOT (niOil01ll XOR (k_bar(74) AND wire_nilOiiii_dataout)))) AND (NOT (niOil01lO XOR (k_bar(75) AND wire_nilOiiil_dataout)))) AND (NOT (niOil01Oi XOR (k_bar(76) AND wire_nilOiiiO_dataout)))) AND (NOT (niOil01Ol XOR (k_bar(77) AND wire_nilOiili_dataout)))) AND (NOT (niOil01OO XOR (k_bar(78) AND wire_nilOiill_dataout)))) AND (NOT (niOil001i XOR (k_bar(79) AND wire_nilOiilO_dataout)))) AND (NOT (niOil001l XOR (k_bar(80) AND wire_nilOiiOi_dataout)))) AND (NOT (niOil001O XOR (k_bar(81) AND wire_nilOiiOl_dataout)))) AND (NOT (niOil000i XOR (k_bar(82) AND wire_nilOiiOO_dataout)))) AND (NOT (niOil000l XOR (k_bar(83) AND wire_nilOil1i_dataout)))) AND (NOT (niOil000O XOR (k_bar(84) AND wire_nilOil1l_dataout)))) AND (NOT (niOil00ii XOR (k_bar(85) AND wire_nilOil1O_dataout)))) AND (NOT (niOil00il XOR (k_bar(86) AND wire_nilOil0i_dataout)))) AND (NOT (niOil00iO XOR (k_bar(87) AND wire_nilOil0l_dataout)))) AND (NOT (niOil00li XOR (k_bar(88) AND wire_nilOil0O_dataout)))) AND (NOT (niOil00ll XOR (k_bar(89) AND wire_nilOilii_dataout)))) AND (NOT (niOil00lO XOR (k_bar(90) AND wire_nilOilil_dataout)))) AND (NOT (niOil00Oi XOR (k_bar(91) AND wire_nilOiliO_dataout)))) AND (NOT (niOil00Ol XOR (k_bar(92) AND wire_nilOilli_dataout)))) AND (NOT (niOil00OO XOR (k_bar(93) AND wire_nilOilll_dataout)))) AND (NOT (niOil0i1i XOR (k_bar(94) AND wire_nilOillO_dataout)))) AND (NOT (niOil0i1l XOR (k_bar(95) AND wire_nilOilOi_dataout)))) AND (NOT (niOiii0ll XOR (k_bar(96) AND wire_nilOilOl_dataout)))) AND (NOT (niOiii0li XOR (k_bar(97) AND wire_nilOilOO_dataout)))) AND (NOT (niOiii0iO XOR (k_bar(98 +) AND wire_nilOiO1i_dataout)))) AND (NOT (niOiii0il XOR (k_bar(99) AND wire_nilOiO1l_dataout)))) AND (NOT (niOil1l0O XOR niOiii00O))) AND (NOT (niOil1lii XOR niOiii00l))) AND (NOT (niOil1lil XOR niOiii00i))) AND (NOT (niOil1liO XOR niOiii01O))) AND (NOT (niOil1lli XOR niOiii01l))) AND (NOT (niOil1lll XOR niOiii01i))) AND (NOT (niOil1llO XOR niOiii1OO))) AND (NOT (niOil1lOi XOR niOiii1Ol))) AND (NOT (niOil1lOl XOR niOiii1Oi))) AND (NOT (niOil1lOO XOR niOiii1lO))) AND (NOT (niOil1O1i XOR niOiii1ll))) AND (NOT (niOil1O1l XOR niOiii1li))) AND (NOT (niOil1O1O XOR niOiii1iO))) AND (NOT (niOil1O0i XOR niOiii1il))) AND (NOT (niOil1O0l XOR niOiii1ii))) AND (NOT (niOil1O0O XOR niOiii10O))) AND (NOT (niOil1Oii XOR niOiii10l))) AND (NOT (niOil1Oil XOR niOiii10i))) AND (NOT (niOil1OiO XOR niOiii11O))); + w_nl0O01i1l50047w <= (((((((((((((((((((((((((((((((((((((((((((((((((((NOT (niOil10ii XOR (k_bar(132) AND wire_nilOii1i_dataout))) AND (NOT (niOil10il XOR (k_bar(133) AND wire_nilOii1l_dataout)))) AND (NOT (niOil10iO XOR (k_bar(134) AND wire_nilOii1O_dataout)))) AND (NOT (niOil10li XOR (k_bar(135) AND wire_nilOii0i_dataout)))) AND (NOT (niOil10ll XOR (k_bar(136) AND wire_nilOii0l_dataout)))) AND (NOT (niOil10lO XOR (k_bar(137) AND wire_nilOii0O_dataout)))) AND (NOT (niOil10Oi XOR (k_bar(138) AND wire_nilOiiii_dataout)))) AND (NOT (niOil10Ol XOR (k_bar(139) AND wire_nilOiiil_dataout)))) AND (NOT (niOil10OO XOR (k_bar(140) AND wire_nilOiiiO_dataout)))) AND (NOT (niOil1i1i XOR (k_bar(141) AND wire_nilOiili_dataout)))) AND (NOT (niOil1i1l XOR (k_bar(142) AND wire_nilOiill_dataout)))) AND (NOT (niOil1i1O XOR (k_bar(143) AND wire_nilOiilO_dataout)))) AND (NOT (niOil1i0i XOR (k_bar(144) AND wire_nilOiiOi_dataout)))) AND (NOT (niOil1i0l XOR (k_bar(145) AND wire_nilOiiOl_dataout)))) AND (NOT (niOil1i0O XOR (k_bar(146) AND wire_nilOiiOO_dataout)))) AND (NOT (niOil1iii XOR (k_bar(147) AND wire_nilOil1i_dataout)))) AND (NOT (niOil1iil XOR (k_bar(148) AND wire_nilOil1l_dataout)))) AND (NOT (niOil1iiO XOR (k_bar(149) AND wire_nilOil1O_dataout)))) AND (NOT (niOil1ili XOR (k_bar(150) AND wire_nilOil0i_dataout)))) AND (NOT (niOil1ill XOR (k_bar(151) AND wire_nilOil0l_dataout)))) AND (NOT (niOil1ilO XOR (k_bar(152) AND wire_nilOil0O_dataout)))) AND (NOT (niOil1iOi XOR (k_bar(153) AND wire_nilOilii_dataout)))) AND (NOT (niOil1iOl XOR (k_bar(154) AND wire_nilOilil_dataout)))) AND (NOT (niOil1iOO XOR (k_bar(155) AND wire_nilOiliO_dataout)))) AND (NOT (niOil1l1i XOR (k_bar(156) AND wire_nilOilli_dataout)))) AND (NOT (niOil1l1l XOR (k_bar(157) AND wire_nilOilll_dataout)))) AND (NOT (niOil1l1O XOR (k_bar(158) AND wire_nilOillO_dataout)))) AND (NOT (niOil1l0i XOR (k_bar(159) AND wire_nilOilOi_dataout)))) AND (NOT (niOiiiOiO XOR (k_bar(160) AND wire_nilOilOl_dataout)))) AND (NOT (niOiiiOil XOR (k_bar(161) AND wire_nilOilOO_dataout)))) AND + (NOT (niOiiiOii XOR (k_bar(162) AND wire_nilOiO1i_dataout)))) AND (NOT (niOiiiO0O XOR (k_bar(163) AND wire_nilOiO1l_dataout)))) AND (NOT (niOiiOOil XOR niOiiiO0i))) AND (NOT (niOiiOOiO XOR niOiiiO1O))) AND (NOT (niOiiOOli XOR niOiiiO1l))) AND (NOT (niOiiOOll XOR niOiiiO1i))) AND (NOT (niOiiOOlO XOR niOiiilOO))) AND (NOT (niOiiOOOi XOR niOiiilOl))) AND (NOT (niOiiOOOl XOR niOiiilOi))) AND (NOT (niOiiOOOO XOR niOiiillO))) AND (NOT (niOil111i XOR niOiiilll))) AND (NOT (niOil111l XOR niOiiilli))) AND (NOT (niOil111O XOR niOiiiliO))) AND (NOT (niOil110i XOR niOiiilil))) AND (NOT (niOil110l XOR niOiiilii))) AND (NOT (niOil110O XOR niOiiil0O))) AND (NOT (niOil11ii XOR niOiiil0l))) AND (NOT (niOil11il XOR niOiiil0i))) AND (NOT (niOil11iO XOR niOiiil1O))) AND (NOT (niOil11li XOR niOiiil1l))) AND (NOT (niOil11ll XOR niOiiil1i))); + wake_oen <= wire_nilOO01l_w_lg_dataout295w(0); + wren_rcv0 <= ((wire_nilOi00l_dataout AND wire_nl011Ol1O_dataout) AND (niOO0O01i4 XOR niOO0O01i3)); + wren_rcv1 <= (wire_nilOi00l_dataout AND wire_nl011Ol0i_dataout); + wren_rpl <= wire_nl1000i_w_lg_nlll1OO0O966w(0); + wire_w_cpl_err_range8533w(0) <= cpl_err(0); + wire_w_cpl_err_range8525w(0) <= cpl_err(1); + wire_w_cpl_err_range8517w(0) <= cpl_err(2); + wire_w_cpl_err_range8509w(0) <= cpl_err(3); + wire_w_dl_req_phycfg_range7707w(0) <= dl_req_phycfg(0); + wire_w_dl_req_phycfg_range7699w(0) <= dl_req_phycfg(1); + wire_w_dl_req_phycfg_range7691w(0) <= dl_req_phycfg(2); + wire_w_dl_req_phycfg_range7683w(0) <= dl_req_phycfg(3); + wire_w_dl_req_phypm_range7753w(0) <= dl_req_phypm(0); + wire_w_dl_req_phypm_range7745w(0) <= dl_req_phypm(1); + wire_w_dl_req_phypm_range7737w(0) <= dl_req_phypm(2); + wire_w_dl_req_phypm_range7729w(0) <= dl_req_phypm(3); + wire_w_k_bar_range45712w(0) <= k_bar(0); + wire_w_k_bar_range47794w(0) <= k_bar(127); + wire_w_k_bar_range45915w(0) <= k_bar(128); + wire_w_k_bar_range45913w(0) <= k_bar(129); + wire_w_k_bar_range45911w(0) <= k_bar(130); + wire_w_k_bar_range49299w(0) <= k_bar(159); + wire_w_k_bar_range47787w(0) <= k_bar(160); + wire_w_k_bar_range47783w(0) <= k_bar(191); + wire_w_k_bar_range45710w(0) <= k_bar(1); + wire_w_k_bar_range47776w(0) <= k_bar(223); + wire_w_k_bar_range48482w(0) <= k_bar(224); + wire_w_k_bar_range45818w(0) <= k_bar(225); + wire_w_k_bar_range48494w(0) <= k_bar(226); + wire_w_k_bar_range45930w(0) <= k_bar(227); + wire_w_k_bar_range45708w(0) <= k_bar(2); + wire_w_k_bar_range51061w(0) <= k_bar(31); + wire_w_k_bar_range51119w(0) <= k_bar(32); + wire_w_k_bar_range51117w(0) <= k_bar(63); + wire_w_k_bar_range45805w(0) <= k_bar(64); + wire_w_k_bar_range45803w(0) <= k_bar(65); + wire_w_k_bar_range45801w(0) <= k_bar(66); + wire_w_k_bar_range50184w(0) <= k_bar(95); + wire_w_k_bar_range47798w(0) <= k_bar(96); + wire_w_k_conf_range46288w(0) <= k_conf(105); + wire_w_k_conf_range46286w(0) <= k_conf(106); + wire_w_k_conf_range44263w(0) <= k_conf(112); + wire_w_k_conf_range44115w(0) <= k_conf(131); + wire_w_k_conf_range43970w(0) <= k_conf(152); + wire_w_k_conf_range44000w(0) <= k_conf(153); + wire_w_k_conf_range47998w(0) <= k_conf(160); + wire_w_k_conf_range48000w(0) <= k_conf(161); + wire_w_k_conf_range48002w(0) <= k_conf(162); + wire_w_k_conf_range48004w(0) <= k_conf(163); + wire_w_k_conf_range48006w(0) <= k_conf(164); + wire_w_k_conf_range48008w(0) <= k_conf(165); + wire_w_k_conf_range48010w(0) <= k_conf(166); + wire_w_k_conf_range48012w(0) <= k_conf(178); + wire_w_k_conf_range29168w(0) <= k_conf(216); + wire_w_k_conf_range1869w(0) <= k_conf(222); + wire_w_k_conf_range46162w(0) <= k_conf(224); + wire_w_k_conf_range46175w(0) <= k_conf(225); + wire_w_k_conf_range46173w(0) <= k_conf(226); + wire_w_k_conf_range46194w(0) <= k_conf(230); + wire_w_k_conf_range24588w(0) <= k_conf(371); + wire_w_k_conf_range9950w(0) <= k_conf(372); + wire_w_k_dev_range52044w(0) <= k_dev(0); + wire_w_k_dev_range52047w(0) <= k_dev(1); + wire_w_k_gbl_hip_range28022w(0) <= k_gbl_hip(23); + wire_w_k_gbl_hip_range28020w(0) <= k_gbl_hip(24); + wire_w_k_gbl_hip_range54181w(0) <= k_gbl_hip(26); + wire_w_k_gbl_hip_range55029w(0) <= k_gbl_hip(27); + wire_w_k_gbl_hip_range25479w(0) <= k_gbl_hip(28); + wire_w_k_gbl_hip_range25481w(0) <= k_gbl_hip(29); + wire_w_k_gbl_hip_range2434w(0) <= k_gbl_hip(32); + wire_w_k_gbl_hip_range1050w(0) <= k_gbl_hip(33); + wire_w_k_gbl_hip_range9015w(0) <= k_gbl_hip(34); + wire_w_k_gbl_hip_range23582w(0) <= k_gbl_hip(43); + wire_w_k_hip_range2413w(0) <= k_hip(0); + wire_w_mode_range8895w(0) <= mode(0); + wire_w_mode_range8897w(0) <= mode(1); + wire_w_swdn_in_range8389w(0) <= swdn_in(0); + wire_w_swdn_in_range8381w(0) <= swdn_in(1); + wire_w_swdn_in_range8373w(0) <= swdn_in(2); + wire_w_swup_in_range8358w(0) <= swup_in(0); + wire_w_swup_in_range8350w(0) <= swup_in(1); + wire_w_swup_in_range8342w(0) <= swup_in(2); + wire_w_swup_in_range8334w(0) <= swup_in(3); + wire_w_swup_in_range8326w(0) <= swup_in(4); + wire_w_swup_in_range8318w(0) <= swup_in(5); + wire_w_swup_in_range8310w(0) <= swup_in(6); + wire_w_test_in_hip_range61746w(0) <= test_in_hip(13); + wire_w_test_in_hip_range61747w(0) <= test_in_hip(14); + wire_w_test_in_hip_range61715w(0) <= test_in_hip(8); + wire_w_test_in_hip_range61717w(0) <= test_in_hip(9); + wire_w_tx_data_vc0_0_range4011w(0) <= tx_data_vc0_0(24); + wire_w_tx_data_vc0_0_range4013w(0) <= tx_data_vc0_0(25); + wire_w_tx_data_vc0_0_range4016w(0) <= tx_data_vc0_0(26); + wire_w_tx_data_vc0_0_range4008w(0) <= tx_data_vc0_0(29); + wire_w_tx_data_vc0_0_range4005w(0) <= tx_data_vc0_0(30); + wire_w_tx_data_vc1_0_range2393w(0) <= tx_data_vc1_0(24); + wire_w_tx_data_vc1_0_range2395w(0) <= tx_data_vc1_0(25); + wire_w_tx_data_vc1_0_range2398w(0) <= tx_data_vc1_0(26); + wire_w_tx_data_vc1_0_range2390w(0) <= tx_data_vc1_0(29); + wire_w_tx_data_vc1_0_range2387w(0) <= tx_data_vc1_0(30); + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0011l71 <= niOO0011l72; + END IF; + if (now = 0 ns) then + niOO0011l71 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0011l72 <= niOO0011l71; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO01O1l75 <= niOO01O1l76; + END IF; + if (now = 0 ns) then + niOO01O1l75 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO01O1l76 <= niOO01O1l75; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO01O1O73 <= niOO01O1O74; + END IF; + if (now = 0 ns) then + niOO01O1O73 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO01O1O74 <= niOO01O1O73; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0ilil69 <= niOO0ilil70; + END IF; + if (now = 0 ns) then + niOO0ilil69 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0ilil70 <= niOO0ilil69; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0iliO67 <= niOO0iliO68; + END IF; + if (now = 0 ns) then + niOO0iliO67 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0iliO68 <= niOO0iliO67; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0illi65 <= niOO0illi66; + END IF; + if (now = 0 ns) then + niOO0illi65 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0illi66 <= niOO0illi65; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0iOiO63 <= niOO0iOiO64; + END IF; + if (now = 0 ns) then + niOO0iOiO63 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0iOiO64 <= niOO0iOiO63; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0iOli61 <= niOO0iOli62; + END IF; + if (now = 0 ns) then + niOO0iOli61 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0iOli62 <= niOO0iOli61; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l0ii51 <= niOO0l0ii52; + END IF; + if (now = 0 ns) then + niOO0l0ii51 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l0ii52 <= niOO0l0ii51; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1ll59 <= niOO0l1ll60; + END IF; + if (now = 0 ns) then + niOO0l1ll59 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1ll60 <= niOO0l1ll59; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1lO57 <= niOO0l1lO58; + END IF; + if (now = 0 ns) then + niOO0l1lO57 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1lO58 <= niOO0l1lO57; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1Oi55 <= niOO0l1Oi56; + END IF; + if (now = 0 ns) then + niOO0l1Oi55 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1Oi56 <= niOO0l1Oi55; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1Ol53 <= niOO0l1Ol54; + END IF; + if (now = 0 ns) then + niOO0l1Ol53 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0l1Ol54 <= niOO0l1Ol53; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0ll0l49 <= niOO0ll0l50; + END IF; + if (now = 0 ns) then + niOO0ll0l49 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0ll0l50 <= niOO0ll0l49; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0ll0O47 <= niOO0ll0O48; + END IF; + if (now = 0 ns) then + niOO0ll0O47 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0ll0O48 <= niOO0ll0O47; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llii45 <= niOO0llii46; + END IF; + if (now = 0 ns) then + niOO0llii45 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llii46 <= niOO0llii45; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llil43 <= niOO0llil44; + END IF; + if (now = 0 ns) then + niOO0llil43 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llil44 <= niOO0llil43; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llli41 <= niOO0llli42; + END IF; + if (now = 0 ns) then + niOO0llli41 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llli42 <= niOO0llli41; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llOl39 <= niOO0llOl40; + END IF; + if (now = 0 ns) then + niOO0llOl39 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llOl40 <= niOO0llOl39; + END IF; + END PROCESS; + wire_niOO0llOl40_w_lg_w_lg_q1262w1263w(0) <= wire_niOO0llOl40_w_lg_q1262w(0) AND nl11iOl; + wire_niOO0llOl40_w_lg_q1262w(0) <= niOO0llOl40 XOR niOO0llOl39; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llOO37 <= niOO0llOO38; + END IF; + if (now = 0 ns) then + niOO0llOO37 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0llOO38 <= niOO0llOO37; + END IF; + END PROCESS; + wire_niOO0llOO38_w_lg_w_lg_q1253w1254w(0) <= wire_niOO0llOO38_w_lg_q1253w(0) AND nl0Ol0ill; + wire_niOO0llOO38_w_lg_q1253w(0) <= niOO0llOO38 XOR niOO0llOO37; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO0i29 <= niOO0lO0i30; + END IF; + if (now = 0 ns) then + niOO0lO0i29 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO0i30 <= niOO0lO0i29; + END IF; + END PROCESS; + wire_niOO0lO0i30_w_lg_w_lg_q1179w1180w(0) <= wire_niOO0lO0i30_w_lg_q1179w(0) AND nl0Ol1OOO; + wire_niOO0lO0i30_w_lg_q1179w(0) <= niOO0lO0i30 XOR niOO0lO0i29; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO0l27 <= niOO0lO0l28; + END IF; + if (now = 0 ns) then + niOO0lO0l27 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO0l28 <= niOO0lO0l27; + END IF; + END PROCESS; + wire_niOO0lO0l28_w_lg_w_lg_q1167w1168w(0) <= wire_niOO0lO0l28_w_lg_q1167w(0) AND nl11l1l; + wire_niOO0lO0l28_w_lg_q1167w(0) <= niOO0lO0l28 XOR niOO0lO0l27; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO0O25 <= niOO0lO0O26; + END IF; + if (now = 0 ns) then + niOO0lO0O25 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO0O26 <= niOO0lO0O25; + END IF; + END PROCESS; + wire_niOO0lO0O26_w_lg_w_lg_q1164w1165w(0) <= wire_niOO0lO0O26_w_lg_q1164w(0) AND nl11iOO; + wire_niOO0lO0O26_w_lg_q1164w(0) <= niOO0lO0O26 XOR niOO0lO0O25; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO1i35 <= niOO0lO1i36; + END IF; + if (now = 0 ns) then + niOO0lO1i35 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO1i36 <= niOO0lO1i35; + END IF; + END PROCESS; + wire_niOO0lO1i36_w_lg_w_lg_q1245w1246w(0) <= wire_niOO0lO1i36_w_lg_q1245w(0) AND nl11lOi; + wire_niOO0lO1i36_w_lg_q1245w(0) <= niOO0lO1i36 XOR niOO0lO1i35; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO1l33 <= niOO0lO1l34; + END IF; + if (now = 0 ns) then + niOO0lO1l33 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO1l34 <= niOO0lO1l33; + END IF; + END PROCESS; + wire_niOO0lO1l34_w_lg_w_lg_q1217w1218w(0) <= wire_niOO0lO1l34_w_lg_q1217w(0) AND nl11l1l; + wire_niOO0lO1l34_w_lg_q1217w(0) <= niOO0lO1l34 XOR niOO0lO1l33; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO1O31 <= niOO0lO1O32; + END IF; + if (now = 0 ns) then + niOO0lO1O31 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lO1O32 <= niOO0lO1O31; + END IF; + END PROCESS; + wire_niOO0lO1O32_w_lg_w_lg_q1190w1191w(0) <= wire_niOO0lO1O32_w_lg_q1190w(0) AND nl11iOl; + wire_niOO0lO1O32_w_lg_q1190w(0) <= niOO0lO1O32 XOR niOO0lO1O31; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOii23 <= niOO0lOii24; + END IF; + if (now = 0 ns) then + niOO0lOii23 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOii24 <= niOO0lOii23; + END IF; + END PROCESS; + wire_niOO0lOii24_w_lg_w_lg_q1146w1147w(0) <= wire_niOO0lOii24_w_lg_q1146w(0) AND niOO0lOlO; + wire_niOO0lOii24_w_lg_q1146w(0) <= niOO0lOii24 XOR niOO0lOii23; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOil21 <= niOO0lOil22; + END IF; + if (now = 0 ns) then + niOO0lOil21 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOil22 <= niOO0lOil21; + END IF; + END PROCESS; + wire_niOO0lOil22_w_lg_w_lg_q1136w1137w(0) <= wire_niOO0lOil22_w_lg_q1136w(0) AND nli1iO0OO; + wire_niOO0lOil22_w_lg_q1136w(0) <= niOO0lOil22 XOR niOO0lOil21; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOiO19 <= niOO0lOiO20; + END IF; + if (now = 0 ns) then + niOO0lOiO19 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOiO20 <= niOO0lOiO19; + END IF; + END PROCESS; + wire_niOO0lOiO20_w_lg_w_lg_q1127w1128w(0) <= wire_niOO0lOiO20_w_lg_q1127w(0) AND nl0Ol0l1i; + wire_niOO0lOiO20_w_lg_q1127w(0) <= niOO0lOiO20 XOR niOO0lOiO19; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOli17 <= niOO0lOli18; + END IF; + if (now = 0 ns) then + niOO0lOli17 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOli18 <= niOO0lOli17; + END IF; + END PROCESS; + wire_niOO0lOli18_w_lg_w_lg_q1120w1121w(0) <= wire_niOO0lOli18_w_lg_q1120w(0) AND nl11lOi; + wire_niOO0lOli18_w_lg_q1120w(0) <= niOO0lOli18 XOR niOO0lOli17; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOll15 <= niOO0lOll16; + END IF; + if (now = 0 ns) then + niOO0lOll15 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOll16 <= niOO0lOll15; + END IF; + END PROCESS; + wire_niOO0lOll16_w_lg_w_lg_q1114w1115w(0) <= wire_niOO0lOll16_w_lg_q1114w(0) AND nl11l0i; + wire_niOO0lOll16_w_lg_q1114w(0) <= niOO0lOll16 XOR niOO0lOll15; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOOO13 <= niOO0lOOO14; + END IF; + if (now = 0 ns) then + niOO0lOOO13 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0lOOO14 <= niOO0lOOO13; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O01i3 <= niOO0O01i4; + END IF; + if (now = 0 ns) then + niOO0O01i3 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O01i4 <= niOO0O01i3; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O01O1 <= niOO0O01O2; + END IF; + if (now = 0 ns) then + niOO0O01O1 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O01O2 <= niOO0O01O1; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O10i11 <= niOO0O10i12; + END IF; + if (now = 0 ns) then + niOO0O10i11 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O10i12 <= niOO0O10i11; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O1ii10 <= niOO0O1ii9; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O1ii9 <= niOO0O1ii10; + END IF; + if (now = 0 ns) then + niOO0O1ii9 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O1iO7 <= niOO0O1iO8; + END IF; + if (now = 0 ns) then + niOO0O1iO7 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O1iO8 <= niOO0O1iO7; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O1Oi5 <= niOO0O1Oi6; + END IF; + if (now = 0 ns) then + niOO0O1Oi5 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO0O1Oi6 <= niOO0O1Oi5; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO10Oli79 <= niOO10Oli80; + END IF; + if (now = 0 ns) then + niOO10Oli79 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO10Oli80 <= niOO10Oli79; + END IF; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO10Oll77 <= niOO10Oll78; + END IF; + if (now = 0 ns) then + niOO10Oll77 <= '1' after 1 ps; + end if; + END PROCESS; + PROCESS (wire_niO0011O_dataout) + BEGIN + IF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN niOO10Oll78 <= niOO10Oll77; + END IF; + END PROCESS; + PROCESS (wire_niO01OOO_dataout, wire_ni01lOi_PRN, wire_niO01lil_dataout) + BEGIN + IF (wire_ni01lOi_PRN = '0') THEN + n0OOOii <= '1'; + n1llOii <= '1'; + n1lO00i <= '1'; + n1lO01l <= '1'; + n1lO01O <= '1'; + n1lOi0i <= '1'; + n1lOiiO <= '1'; + n1lOili <= '1'; + n1lOill <= '1'; + n1lOilO <= '1'; + n1lOiOi <= '1'; + n1lOiOl <= '1'; + n1lOiOO <= '1'; + n1lOl0i <= '1'; + n1lOl0l <= '1'; + n1lOl0O <= '1'; + n1lOl1i <= '1'; + n1lOl1l <= '1'; + n1lOl1O <= '1'; + n1lOlii <= '1'; + n1lOlil <= '1'; + n1lOliO <= '1'; + n1lOlli <= '1'; + n1lOlll <= '1'; + n1lOllO <= '1'; + n1lOlOi <= '1'; + n1lOlOl <= '1'; + n1lOlOO <= '1'; + n1lOO1i <= '1'; + n1lOO1l <= '1'; + n1O0l0O <= '1'; + n1O0liO <= '1'; + n1O0O0i <= '1'; + n1O0O0l <= '1'; + n1O0O0O <= '1'; + n1O0O1i <= '1'; + n1O0O1l <= '1'; + n1O0O1O <= '1'; + n1O0Oii <= '1'; + n1O0Oil <= '1'; + n1O0OiO <= '1'; + n1O0Oli <= '1'; + n1O0Oll <= '1'; + n1O0OlO <= '1'; + n1O0OOi <= '1'; + n1O0OOl <= '1'; + n1O0OOO <= '1'; + n1Oi00i <= '1'; + n1Oi00l <= '1'; + n1Oi00O <= '1'; + n1Oi01i <= '1'; + n1Oi01l <= '1'; + n1Oi01O <= '1'; + n1Oi0ii <= '1'; + n1Oi0il <= '1'; + n1Oi0iO <= '1'; + n1Oi0li <= '1'; + n1Oi0ll <= '1'; + n1Oi0lO <= '1'; + n1Oi0Oi <= '1'; + n1Oi0Ol <= '1'; + n1Oi0OO <= '1'; + n1Oi10i <= '1'; + n1Oi10l <= '1'; + n1Oi10O <= '1'; + n1Oi11i <= '1'; + n1Oi11l <= '1'; + n1Oi11O <= '1'; + n1Oi1ii <= '1'; + n1Oi1il <= '1'; + n1Oi1iO <= '1'; + n1Oi1li <= '1'; + n1Oi1ll <= '1'; + n1Oi1lO <= '1'; + n1Oi1Oi <= '1'; + n1Oi1Ol <= '1'; + n1Oi1OO <= '1'; + n1Oii0i <= '1'; + n1Oii0l <= '1'; + n1Oii0O <= '1'; + n1Oii1i <= '1'; + n1Oii1l <= '1'; + n1Oii1O <= '1'; + n1Oiiii <= '1'; + n1Oiiil <= '1'; + n1OiiiO <= '1'; + n1Oiili <= '1'; + n1Oiill <= '1'; + n1OiilO <= '1'; + n1OiiOi <= '1'; + n1OiiOl <= '1'; + n1OiiOO <= '1'; + n1Oil0i <= '1'; + n1Oil0l <= '1'; + n1Oil0O <= '1'; + n1Oil1i <= '1'; + n1Oil1l <= '1'; + n1Oil1O <= '1'; + n1Oilii <= '1'; + n1Oilil <= '1'; + n1OiliO <= '1'; + n1Oilli <= '1'; + n1Oilll <= '1'; + n1OillO <= '1'; + n1OilOi <= '1'; + n1OilOl <= '1'; + n1OilOO <= '1'; + n1OiO0i <= '1'; + n1OiO0l <= '1'; + n1OiO0O <= '1'; + n1OiO1i <= '1'; + n1OiO1l <= '1'; + n1OiO1O <= '1'; + n1OiOii <= '1'; + n1OiOil <= '1'; + n1OiOiO <= '1'; + n1OiOli <= '1'; + n1OiOll <= '1'; + n1OiOlO <= '1'; + n1OiOOi <= '1'; + n1OiOOl <= '1'; + n1OiOOO <= '1'; + n1Ol00i <= '1'; + n1Ol00l <= '1'; + n1Ol00O <= '1'; + n1Ol01i <= '1'; + n1Ol01l <= '1'; + n1Ol01O <= '1'; + n1Ol0ii <= '1'; + n1Ol0il <= '1'; + n1Ol0iO <= '1'; + n1Ol0li <= '1'; + n1Ol0ll <= '1'; + n1Ol0lO <= '1'; + n1Ol0Oi <= '1'; + n1Ol0Ol <= '1'; + n1Ol0OO <= '1'; + n1Ol10i <= '1'; + n1Ol10l <= '1'; + n1Ol10O <= '1'; + n1Ol11i <= '1'; + n1Ol11l <= '1'; + n1Ol11O <= '1'; + n1Ol1ii <= '1'; + n1Ol1il <= '1'; + n1Ol1iO <= '1'; + n1Ol1li <= '1'; + n1Ol1ll <= '1'; + n1Ol1lO <= '1'; + n1Ol1Oi <= '1'; + n1Ol1Ol <= '1'; + n1Ol1OO <= '1'; + n1Oli0i <= '1'; + n1Oli0l <= '1'; + n1Oli0O <= '1'; + n1Oli1i <= '1'; + n1Oli1l <= '1'; + n1Oli1O <= '1'; + n1Oliii <= '1'; + n1Oliil <= '1'; + n1OliiO <= '1'; + n1Olili <= '1'; + n1Olill <= '1'; + n1OlilO <= '1'; + n1OliOi <= '1'; + n1OliOl <= '1'; + n1OliOO <= '1'; + n1Oll0i <= '1'; + n1Oll0l <= '1'; + n1Oll0O <= '1'; + n1Oll1i <= '1'; + n1Oll1l <= '1'; + n1Oll1O <= '1'; + n1Ollii <= '1'; + n1Ollil <= '1'; + n1OlliO <= '1'; + n1Ollli <= '1'; + n1Ollll <= '1'; + n1OlllO <= '1'; + n1OllOi <= '1'; + n1OllOl <= '1'; + n1OllOO <= '1'; + n1OlO0i <= '1'; + n1OlO0l <= '1'; + n1OlO0O <= '1'; + n1OlO1i <= '1'; + n1OlO1l <= '1'; + n1OlO1O <= '1'; + n1OlOii <= '1'; + n1OlOil <= '1'; + ni01lll <= '1'; + ni01llO <= '1'; + ni01lOl <= '1'; + ni10iii <= '1'; + ni10ilO <= '1'; + ni10iOi <= '1'; + ni10iOl <= '1'; + ni10iOO <= '1'; + ni10l0i <= '1'; + ni10l0l <= '1'; + ni10l0O <= '1'; + ni10l1i <= '1'; + ni10l1l <= '1'; + ni10l1O <= '1'; + ni10lii <= '1'; + ni10lil <= '1'; + ni10liO <= '1'; + ni10llO <= '1'; + ni10lOi <= '1'; + ni10O0i <= '1'; + ni10O0l <= '1'; + ni10O0O <= '1'; + ni10O1i <= '1'; + ni10O1l <= '1'; + ni10O1O <= '1'; + ni10Oii <= '1'; + ni1lOOl <= '1'; + ELSIF (wire_niO01lil_dataout = '0') THEN + n0OOOii <= '0'; + n1llOii <= '0'; + n1lO00i <= '0'; + n1lO01l <= '0'; + n1lO01O <= '0'; + n1lOi0i <= '0'; + n1lOiiO <= '0'; + n1lOili <= '0'; + n1lOill <= '0'; + n1lOilO <= '0'; + n1lOiOi <= '0'; + n1lOiOl <= '0'; + n1lOiOO <= '0'; + n1lOl0i <= '0'; + n1lOl0l <= '0'; + n1lOl0O <= '0'; + n1lOl1i <= '0'; + n1lOl1l <= '0'; + n1lOl1O <= '0'; + n1lOlii <= '0'; + n1lOlil <= '0'; + n1lOliO <= '0'; + n1lOlli <= '0'; + n1lOlll <= '0'; + n1lOllO <= '0'; + n1lOlOi <= '0'; + n1lOlOl <= '0'; + n1lOlOO <= '0'; + n1lOO1i <= '0'; + n1lOO1l <= '0'; + n1O0l0O <= '0'; + n1O0liO <= '0'; + n1O0O0i <= '0'; + n1O0O0l <= '0'; + n1O0O0O <= '0'; + n1O0O1i <= '0'; + n1O0O1l <= '0'; + n1O0O1O <= '0'; + n1O0Oii <= '0'; + n1O0Oil <= '0'; + n1O0OiO <= '0'; + n1O0Oli <= '0'; + n1O0Oll <= '0'; + n1O0OlO <= '0'; + n1O0OOi <= '0'; + n1O0OOl <= '0'; + n1O0OOO <= '0'; + n1Oi00i <= '0'; + n1Oi00l <= '0'; + n1Oi00O <= '0'; + n1Oi01i <= '0'; + n1Oi01l <= '0'; + n1Oi01O <= '0'; + n1Oi0ii <= '0'; + n1Oi0il <= '0'; + n1Oi0iO <= '0'; + n1Oi0li <= '0'; + n1Oi0ll <= '0'; + n1Oi0lO <= '0'; + n1Oi0Oi <= '0'; + n1Oi0Ol <= '0'; + n1Oi0OO <= '0'; + n1Oi10i <= '0'; + n1Oi10l <= '0'; + n1Oi10O <= '0'; + n1Oi11i <= '0'; + n1Oi11l <= '0'; + n1Oi11O <= '0'; + n1Oi1ii <= '0'; + n1Oi1il <= '0'; + n1Oi1iO <= '0'; + n1Oi1li <= '0'; + n1Oi1ll <= '0'; + n1Oi1lO <= '0'; + n1Oi1Oi <= '0'; + n1Oi1Ol <= '0'; + n1Oi1OO <= '0'; + n1Oii0i <= '0'; + n1Oii0l <= '0'; + n1Oii0O <= '0'; + n1Oii1i <= '0'; + n1Oii1l <= '0'; + n1Oii1O <= '0'; + n1Oiiii <= '0'; + n1Oiiil <= '0'; + n1OiiiO <= '0'; + n1Oiili <= '0'; + n1Oiill <= '0'; + n1OiilO <= '0'; + n1OiiOi <= '0'; + n1OiiOl <= '0'; + n1OiiOO <= '0'; + n1Oil0i <= '0'; + n1Oil0l <= '0'; + n1Oil0O <= '0'; + n1Oil1i <= '0'; + n1Oil1l <= '0'; + n1Oil1O <= '0'; + n1Oilii <= '0'; + n1Oilil <= '0'; + n1OiliO <= '0'; + n1Oilli <= '0'; + n1Oilll <= '0'; + n1OillO <= '0'; + n1OilOi <= '0'; + n1OilOl <= '0'; + n1OilOO <= '0'; + n1OiO0i <= '0'; + n1OiO0l <= '0'; + n1OiO0O <= '0'; + n1OiO1i <= '0'; + n1OiO1l <= '0'; + n1OiO1O <= '0'; + n1OiOii <= '0'; + n1OiOil <= '0'; + n1OiOiO <= '0'; + n1OiOli <= '0'; + n1OiOll <= '0'; + n1OiOlO <= '0'; + n1OiOOi <= '0'; + n1OiOOl <= '0'; + n1OiOOO <= '0'; + n1Ol00i <= '0'; + n1Ol00l <= '0'; + n1Ol00O <= '0'; + n1Ol01i <= '0'; + n1Ol01l <= '0'; + n1Ol01O <= '0'; + n1Ol0ii <= '0'; + n1Ol0il <= '0'; + n1Ol0iO <= '0'; + n1Ol0li <= '0'; + n1Ol0ll <= '0'; + n1Ol0lO <= '0'; + n1Ol0Oi <= '0'; + n1Ol0Ol <= '0'; + n1Ol0OO <= '0'; + n1Ol10i <= '0'; + n1Ol10l <= '0'; + n1Ol10O <= '0'; + n1Ol11i <= '0'; + n1Ol11l <= '0'; + n1Ol11O <= '0'; + n1Ol1ii <= '0'; + n1Ol1il <= '0'; + n1Ol1iO <= '0'; + n1Ol1li <= '0'; + n1Ol1ll <= '0'; + n1Ol1lO <= '0'; + n1Ol1Oi <= '0'; + n1Ol1Ol <= '0'; + n1Ol1OO <= '0'; + n1Oli0i <= '0'; + n1Oli0l <= '0'; + n1Oli0O <= '0'; + n1Oli1i <= '0'; + n1Oli1l <= '0'; + n1Oli1O <= '0'; + n1Oliii <= '0'; + n1Oliil <= '0'; + n1OliiO <= '0'; + n1Olili <= '0'; + n1Olill <= '0'; + n1OlilO <= '0'; + n1OliOi <= '0'; + n1OliOl <= '0'; + n1OliOO <= '0'; + n1Oll0i <= '0'; + n1Oll0l <= '0'; + n1Oll0O <= '0'; + n1Oll1i <= '0'; + n1Oll1l <= '0'; + n1Oll1O <= '0'; + n1Ollii <= '0'; + n1Ollil <= '0'; + n1OlliO <= '0'; + n1Ollli <= '0'; + n1Ollll <= '0'; + n1OlllO <= '0'; + n1OllOi <= '0'; + n1OllOl <= '0'; + n1OllOO <= '0'; + n1OlO0i <= '0'; + n1OlO0l <= '0'; + n1OlO0O <= '0'; + n1OlO1i <= '0'; + n1OlO1l <= '0'; + n1OlO1O <= '0'; + n1OlOii <= '0'; + n1OlOil <= '0'; + ni01lll <= '0'; + ni01llO <= '0'; + ni01lOl <= '0'; + ni10iii <= '0'; + ni10ilO <= '0'; + ni10iOi <= '0'; + ni10iOl <= '0'; + ni10iOO <= '0'; + ni10l0i <= '0'; + ni10l0l <= '0'; + ni10l0O <= '0'; + ni10l1i <= '0'; + ni10l1l <= '0'; + ni10l1O <= '0'; + ni10lii <= '0'; + ni10lil <= '0'; + ni10liO <= '0'; + ni10llO <= '0'; + ni10lOi <= '0'; + ni10O0i <= '0'; + ni10O0l <= '0'; + ni10O0O <= '0'; + ni10O1i <= '0'; + ni10O1l <= '0'; + ni10O1O <= '0'; + ni10Oii <= '0'; + ni1lOOl <= '0'; + ELSIF (wire_niO01OOO_dataout = '1' AND wire_niO01OOO_dataout'event) THEN + n0OOOii <= n0OOOiO; + n1llOii <= n1llOiO; + n1lO00i <= wire_n1lO0iO_dataout; + n1lO01l <= wire_n1lO0ii_dataout; + n1lO01O <= wire_n1lO0il_dataout; + n1lOi0i <= wire_n1lOOil_dataout; + n1lOiiO <= wire_n1lOOiO_dataout; + n1lOili <= wire_n1lOOli_dataout; + n1lOill <= wire_n1lOOll_dataout; + n1lOilO <= wire_n1lOOlO_dataout; + n1lOiOi <= wire_n1lOOOi_dataout; + n1lOiOl <= wire_n1lOOOl_dataout; + n1lOiOO <= wire_n1lOOOO_dataout; + n1lOl0i <= wire_n1O111O_dataout; + n1lOl0l <= wire_n1O110i_dataout; + n1lOl0O <= wire_n1O110l_dataout; + n1lOl1i <= wire_n1O11il_dataout; + n1lOl1l <= wire_n1O111i_dataout; + n1lOl1O <= wire_n1O111l_dataout; + n1lOlii <= wire_n1O110O_dataout; + n1lOlil <= wire_n1O11ii_dataout; + n1lOliO <= wire_n1O11il_dataout; + n1lOlli <= wire_n1O11iO_dataout; + n1lOlll <= wire_n1O11li_dataout; + n1lOllO <= wire_n1O11ll_dataout; + n1lOlOi <= wire_n1O11lO_dataout; + n1lOlOl <= wire_n1O11Oi_dataout; + n1lOlOO <= wire_n1O11Ol_dataout; + n1lOO1i <= wire_n1O11OO_dataout; + n1lOO1l <= wire_n1O101i_dataout; + n1O0l0O <= wire_n1OlOiO_dataout; + n1O0liO <= wire_n1O0lii_dataout; + n1O0O0i <= wire_n1OlOOi_dataout; + n1O0O0l <= wire_n1OlOOl_dataout; + n1O0O0O <= wire_n1OlOOO_dataout; + n1O0O1i <= wire_n1OlOli_dataout; + n1O0O1l <= wire_n1OlOll_dataout; + n1O0O1O <= wire_n1OlOlO_dataout; + n1O0Oii <= wire_n1OO11i_dataout; + n1O0Oil <= wire_n1OO11l_dataout; + n1O0OiO <= wire_n1OO11O_dataout; + n1O0Oli <= wire_n1OO10i_dataout; + n1O0Oll <= wire_n1OO10l_dataout; + n1O0OlO <= wire_n1OO10O_dataout; + n1O0OOi <= wire_n1OO1ii_dataout; + n1O0OOl <= wire_n1OO1il_dataout; + n1O0OOO <= wire_n1OO1iO_dataout; + n1Oi00i <= wire_n1OOi0O_dataout; + n1Oi00l <= wire_n1OOiii_dataout; + n1Oi00O <= wire_n1OOiil_dataout; + n1Oi01i <= wire_n1OOi1O_dataout; + n1Oi01l <= wire_n1OOi0i_dataout; + n1Oi01O <= wire_n1OOi0l_dataout; + n1Oi0ii <= wire_n1OOiiO_dataout; + n1Oi0il <= wire_n1OOili_dataout; + n1Oi0iO <= wire_n1OOill_dataout; + n1Oi0li <= wire_n1OOilO_dataout; + n1Oi0ll <= wire_n1OOiOi_dataout; + n1Oi0lO <= wire_n1OOiOl_dataout; + n1Oi0Oi <= wire_n1OOiOO_dataout; + n1Oi0Ol <= wire_n1OOl1i_dataout; + n1Oi0OO <= wire_n1OOl1l_dataout; + n1Oi10i <= wire_n1OO00O_dataout; + n1Oi10l <= wire_n1OO0ii_dataout; + n1Oi10O <= wire_n1OO0il_dataout; + n1Oi11i <= wire_n1OO1li_dataout; + n1Oi11l <= wire_n1OO1ll_dataout; + n1Oi11O <= wire_n1OO00l_dataout; + n1Oi1ii <= wire_n1OO0iO_dataout; + n1Oi1il <= wire_n1OO0li_dataout; + n1Oi1iO <= wire_n1OO0ll_dataout; + n1Oi1li <= wire_n1OO0lO_dataout; + n1Oi1ll <= wire_n1OO0Oi_dataout; + n1Oi1lO <= wire_n1OO0Ol_dataout; + n1Oi1Oi <= wire_n1OO0OO_dataout; + n1Oi1Ol <= wire_n1OOi1i_dataout; + n1Oi1OO <= wire_n1OOi1l_dataout; + n1Oii0i <= wire_n1OOl0O_dataout; + n1Oii0l <= wire_n1OOlii_dataout; + n1Oii0O <= wire_n1OOlil_dataout; + n1Oii1i <= wire_n1OOl1O_dataout; + n1Oii1l <= wire_n1OOl0i_dataout; + n1Oii1O <= wire_n1OOl0l_dataout; + n1Oiiii <= wire_n1OOliO_dataout; + n1Oiiil <= wire_n1OOlli_dataout; + n1OiiiO <= wire_n1OOlll_dataout; + n1Oiili <= wire_n1OOllO_dataout; + n1Oiill <= wire_n1OOlOi_dataout; + n1OiilO <= wire_n1OOlOl_dataout; + n1OiiOi <= wire_n1OOlOO_dataout; + n1OiiOl <= wire_n1OOO1i_dataout; + n1OiiOO <= wire_n1OOO1l_dataout; + n1Oil0i <= wire_n1OOO0O_dataout; + n1Oil0l <= wire_n1OOOii_dataout; + n1Oil0O <= wire_n1OOOil_dataout; + n1Oil1i <= wire_n1OOO1O_dataout; + n1Oil1l <= wire_n1OOO0i_dataout; + n1Oil1O <= wire_n1OOO0l_dataout; + n1Oilii <= wire_n1OOOiO_dataout; + n1Oilil <= wire_n1OOOli_dataout; + n1OiliO <= wire_n1OOOll_dataout; + n1Oilli <= wire_n1OOOlO_dataout; + n1Oilll <= wire_n1OOOOi_dataout; + n1OillO <= wire_n1OOOOl_dataout; + n1OilOi <= wire_n1OOOOO_dataout; + n1OilOl <= wire_n01111i_dataout; + n1OilOO <= wire_n01111l_dataout; + n1OiO0i <= wire_n01110O_dataout; + n1OiO0l <= wire_n0111ii_dataout; + n1OiO0O <= wire_n0111il_dataout; + n1OiO1i <= wire_n01111O_dataout; + n1OiO1l <= wire_n01110i_dataout; + n1OiO1O <= wire_n01110l_dataout; + n1OiOii <= wire_n0111iO_dataout; + n1OiOil <= wire_n0111li_dataout; + n1OiOiO <= wire_n0111ll_dataout; + n1OiOli <= wire_n0111lO_dataout; + n1OiOll <= wire_n0111Oi_dataout; + n1OiOlO <= wire_n0111Ol_dataout; + n1OiOOi <= wire_n0111OO_dataout; + n1OiOOl <= wire_n01101i_dataout; + n1OiOOO <= wire_n01101l_dataout; + n1Ol00i <= wire_n011i0O_dataout; + n1Ol00l <= wire_n011iii_dataout; + n1Ol00O <= wire_n011iil_dataout; + n1Ol01i <= wire_n011i1O_dataout; + n1Ol01l <= wire_n011i0i_dataout; + n1Ol01O <= wire_n011i0l_dataout; + n1Ol0ii <= wire_n011iiO_dataout; + n1Ol0il <= wire_n011ili_dataout; + n1Ol0iO <= wire_n011ill_dataout; + n1Ol0li <= wire_n011ilO_dataout; + n1Ol0ll <= wire_n011iOi_dataout; + n1Ol0lO <= wire_n011iOl_dataout; + n1Ol0Oi <= wire_n011iOO_dataout; + n1Ol0Ol <= wire_n011l1i_dataout; + n1Ol0OO <= wire_n011l1l_dataout; + n1Ol10i <= wire_n01100O_dataout; + n1Ol10l <= wire_n0110ii_dataout; + n1Ol10O <= wire_n0110il_dataout; + n1Ol11i <= wire_n01101O_dataout; + n1Ol11l <= wire_n01100i_dataout; + n1Ol11O <= wire_n01100l_dataout; + n1Ol1ii <= wire_n0110iO_dataout; + n1Ol1il <= wire_n0110li_dataout; + n1Ol1iO <= wire_n0110ll_dataout; + n1Ol1li <= wire_n0110lO_dataout; + n1Ol1ll <= wire_n0110Oi_dataout; + n1Ol1lO <= wire_n0110Ol_dataout; + n1Ol1Oi <= wire_n0110OO_dataout; + n1Ol1Ol <= wire_n011i1i_dataout; + n1Ol1OO <= wire_n011i1l_dataout; + n1Oli0i <= wire_n011l0O_dataout; + n1Oli0l <= wire_n011lii_dataout; + n1Oli0O <= wire_n011lil_dataout; + n1Oli1i <= wire_n011l1O_dataout; + n1Oli1l <= wire_n011l0i_dataout; + n1Oli1O <= wire_n011l0l_dataout; + n1Oliii <= wire_n011liO_dataout; + n1Oliil <= wire_n011lli_dataout; + n1OliiO <= wire_n011lll_dataout; + n1Olili <= wire_n011llO_dataout; + n1Olill <= wire_n011lOi_dataout; + n1OlilO <= wire_n011lOl_dataout; + n1OliOi <= wire_n011lOO_dataout; + n1OliOl <= wire_n011O1i_dataout; + n1OliOO <= wire_n011O1l_dataout; + n1Oll0i <= wire_n011O0O_dataout; + n1Oll0l <= wire_n011Oii_dataout; + n1Oll0O <= wire_n011Oil_dataout; + n1Oll1i <= wire_n011O1O_dataout; + n1Oll1l <= wire_n011O0i_dataout; + n1Oll1O <= wire_n011O0l_dataout; + n1Ollii <= wire_n011OiO_dataout; + n1Ollil <= wire_n011Oli_dataout; + n1OlliO <= wire_n011Oll_dataout; + n1Ollli <= wire_n011OlO_dataout; + n1Ollll <= wire_n1OO1lO_dataout; + n1OlllO <= wire_n1OO1Oi_dataout; + n1OllOi <= wire_n1OO1Ol_dataout; + n1OllOl <= wire_n1OO1OO_dataout; + n1OllOO <= wire_n1OO01i_dataout; + n1OlO0i <= wire_n011OOi_dataout; + n1OlO0l <= wire_n011OOl_dataout; + n1OlO0O <= wire_n011OOO_dataout; + n1OlO1i <= wire_n1OO01l_dataout; + n1OlO1l <= wire_n1OO01O_dataout; + n1OlO1O <= wire_n1OO00i_dataout; + n1OlOii <= wire_n01011i_dataout; + n1OlOil <= wire_n01011l_dataout; + ni01lll <= wire_ni01O1i_dataout; + ni01llO <= wire_ni01O1l_dataout; + ni01lOl <= wire_ni01O1O_dataout; + ni10iii <= wire_ni10Oil_dataout; + ni10ilO <= wire_ni10OiO_dataout; + ni10iOi <= wire_ni10Oli_dataout; + ni10iOl <= wire_ni10Oll_dataout; + ni10iOO <= wire_ni10OlO_dataout; + ni10l0i <= wire_ni1i11i_dataout; + ni10l0l <= wire_ni1i11l_dataout; + ni10l0O <= wire_ni1i11O_dataout; + ni10l1i <= wire_ni10OOi_dataout; + ni10l1l <= wire_ni10OOl_dataout; + ni10l1O <= wire_ni10OOO_dataout; + ni10lii <= wire_ni1i10i_dataout; + ni10lil <= wire_ni1i10l_dataout; + ni10liO <= wire_ni1i10O_dataout; + ni10llO <= wire_ni1i1iO_dataout; + ni10lOi <= wire_ni1i1li_dataout; + ni10O0i <= wire_ni1i1OO_dataout; + ni10O0l <= wire_ni1i01i_dataout; + ni10O0O <= wire_ni1i01l_dataout; + ni10O1i <= wire_ni1i1lO_dataout; + ni10O1l <= wire_ni1i1Oi_dataout; + ni10O1O <= wire_ni1i1Ol_dataout; + ni10Oii <= wire_ni1i01O_dataout; + ni1lOOl <= wire_ni01lOO_dataout; + END IF; + END PROCESS; + wire_ni01lOi_PRN <= (niOO0l0ii52 XOR niOO0l0ii51); + wire_ni01lOi_w3816w(0) <= wire_ni01lOi_w_lg_w_lg_w_lg_w_lg_n1lOlOl3806w3807w3810w3813w(0) AND wire_ni01lOi_w_lg_w_lg_n1lOO1l3814w3815w(0); + wire_ni01lOi_w_lg_w_lg_w_lg_w_lg_n1lOlOl3806w3807w3810w3813w(0) <= wire_ni01lOi_w_lg_w_lg_w_lg_n1lOlOl3806w3807w3810w(0) AND wire_ni01lOi_w_lg_w_lg_n1lOO1i3811w3812w(0); + wire_ni01lOi_w_lg_w_lg_w_lg_n1lOlOl3806w3807w3810w(0) <= wire_ni01lOi_w_lg_w_lg_n1lOlOl3806w3807w(0) AND wire_ni01lOi_w_lg_w_lg_n1lOlOO3808w3809w(0); + wire_ni01lOi_w_lg_n1lO00i3832w(0) <= n1lO00i AND n1lO01O; + wire_ni01lOi_w_lg_w_lg_n1lOlOl3806w3807w(0) <= NOT wire_ni01lOi_w_lg_n1lOlOl3806w(0); + wire_ni01lOi_w_lg_w_lg_n1lOlOO3808w3809w(0) <= NOT wire_ni01lOi_w_lg_n1lOlOO3808w(0); + wire_ni01lOi_w_lg_w_lg_n1lOO1i3811w3812w(0) <= NOT wire_ni01lOi_w_lg_n1lOO1i3811w(0); + wire_ni01lOi_w_lg_w_lg_n1lOO1l3814w3815w(0) <= NOT wire_ni01lOi_w_lg_n1lOO1l3814w(0); + wire_ni01lOi_w_lg_n1lOi0i3805w(0) <= NOT n1lOi0i; + wire_ni01lOi_w_lg_n1lOO1l3771w(0) <= NOT n1lOO1l; + wire_ni01lOi_w_lg_ni10l0l762w(0) <= NOT ni10l0l; + wire_ni01lOi_w_lg_ni10liO2719w(0) <= NOT ni10liO; + wire_ni01lOi_w_lg_n1lOlOl3806w(0) <= n1lOlOl XOR n1lOl1l; + wire_ni01lOi_w_lg_n1lOlOO3808w(0) <= n1lOlOO XOR n1lOl1O; + wire_ni01lOi_w_lg_n1lOO1i3811w(0) <= n1lOO1i XOR n1lOl0i; + wire_ni01lOi_w_lg_n1lOO1l3814w(0) <= n1lOO1l XOR n1lOl0l; + PROCESS (wire_niO01OOO_dataout, wire_ni10lOl_PRN, wire_ni10lOl_CLRN) + BEGIN + IF (wire_ni10lOl_PRN = '0') THEN + ni10lli <= '1'; + ni10lll <= '1'; + ni10lOO <= '1'; + ELSIF (wire_ni10lOl_CLRN = '0') THEN + ni10lli <= '0'; + ni10lll <= '0'; + ni10lOO <= '0'; + ELSIF (wire_niO01OOO_dataout = '1' AND wire_niO01OOO_dataout'event) THEN + ni10lli <= wire_ni1i1ii_dataout; + ni10lll <= wire_ni1i1il_dataout; + ni10lOO <= wire_ni1i1ll_dataout; + END IF; + if (now = 0 ns) then + ni10lli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni10lll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni10lOO <= '1' after 1 ps; + end if; + END PROCESS; + wire_ni10lOl_CLRN <= (niOO0iOli62 XOR niOO0iOli61); + wire_ni10lOl_PRN <= ((niOO0iOiO64 XOR niOO0iOiO63) AND wire_niO01lil_dataout); + PROCESS (wire_niO0011l_dataout, wire_ni11lll_PRN) + BEGIN + IF (wire_ni11lll_PRN = '0') THEN + n1lOO0l <= '1'; + n1lOO0O <= '1'; + n1lOO1O <= '1'; + n1lOOii <= '1'; + ni1100l <= '1'; + ni1100O <= '1'; + ni1101i <= '1'; + ni11llO <= '1'; + ELSIF (wire_niO0011l_dataout = '1' AND wire_niO0011l_dataout'event) THEN + n1lOO0l <= wire_n1O1lil_dataout; + n1lOO0O <= wire_n1O1liO_dataout; + n1lOO1O <= wire_n1O1lii_dataout; + n1lOOii <= wire_n1O1l0O_dataout; + ni1100l <= wire_ni11i0O_dataout; + ni1100O <= wire_ni11i0l_dataout; + ni1101i <= wire_ni11iii_dataout; + ni11llO <= wire_ni11iil_dataout; + END IF; + END PROCESS; + wire_ni11lll_PRN <= (niOO0ilil70 XOR niOO0ilil69); + PROCESS (wire_niO01OOO_dataout, wire_ni11lOO_PRN, wire_ni11lOO_CLRN) + BEGIN + IF (wire_ni11lOO_PRN = '0') THEN + n0OOOiO <= '1'; + n1llOiO <= '1'; + n1lO00l <= '1'; + n1lO00O <= '1'; + n1lO01i <= '1'; + n1lOO0i <= '1'; + ni11lli <= '1'; + ni11lOi <= '1'; + ni11lOl <= '1'; + ni11O1i <= '1'; + ELSIF (wire_ni11lOO_CLRN = '0') THEN + n0OOOiO <= '0'; + n1llOiO <= '0'; + n1lO00l <= '0'; + n1lO00O <= '0'; + n1lO01i <= '0'; + n1lOO0i <= '0'; + ni11lli <= '0'; + ni11lOi <= '0'; + ni11lOl <= '0'; + ni11O1i <= '0'; + ELSIF (wire_niO01OOO_dataout = '1' AND wire_niO01OOO_dataout'event) THEN + n0OOOiO <= n0OOOil; + n1llOiO <= n1llOil; + n1lO00l <= wire_n1lOi0O_dataout; + n1lO00O <= wire_n1lOi0l_dataout; + n1lO01i <= wire_n1lOiii_dataout; + n1lOO0i <= wire_n1lOiil_dataout; + ni11lli <= wire_ni10iiO_dataout; + ni11lOi <= wire_ni10ili_dataout; + ni11lOl <= wire_ni10ill_dataout; + ni11O1i <= wire_ni10iil_dataout; + END IF; + END PROCESS; + wire_ni11lOO_CLRN <= (niOO0illi66 XOR niOO0illi65); + wire_ni11lOO_PRN <= (niOO0iliO68 XOR niOO0iliO67); + PROCESS (wire_niO0011l_dataout, wire_ni1llii_PRN, wire_ni1llii_CLRN) + BEGIN + IF (wire_ni1llii_PRN = '0') THEN + n0Oli1i <= '1'; + n1O1lOO <= '1'; + n1O1O0i <= '1'; + n1O1O1i <= '1'; + ni1llil <= '1'; + ELSIF (wire_ni1llii_CLRN = '0') THEN + n0Oli1i <= '0'; + n1O1lOO <= '0'; + n1O1O0i <= '0'; + n1O1O1i <= '0'; + ni1llil <= '0'; + ELSIF (wire_niO0011l_dataout = '1' AND wire_niO0011l_dataout'event) THEN + n0Oli1i <= wire_n0OlO0O_dataout; + n1O1lOO <= wire_n1O011O_dataout; + n1O1O0i <= wire_n1O01ii_dataout; + n1O1O1i <= wire_n1O010i_dataout; + ni1llil <= wire_ni1O11O_dataout; + END IF; + if (now = 0 ns) then + n0Oli1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1O1lOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1O1O0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1O1O1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + ni1llil <= '1' after 1 ps; + end if; + END PROCESS; + wire_ni1llii_CLRN <= (niOO0l1lO58 XOR niOO0l1lO57); + wire_ni1llii_PRN <= ((niOO0l1ll60 XOR niOO0l1ll59) AND wire_niO0010l_dataout); + wire_ni1llii_w_lg_n0Oli1i3408w(0) <= n0Oli1i AND n0Ol00i; + wire_ni1llii_w_lg_n0Oli1i3428w(0) <= n0Oli1i AND n0Ol11O; + wire_ni1llii_w_lg_ni1llil2426w(0) <= ni1llil AND wire_ni110Ol_w_lg_dataout2425w(0); + wire_ni1llii_w_lg_ni1llil2568w(0) <= ni1llil AND wire_w_lg_w_lg_niOO0l00O2566w2567w(0); + wire_ni1llii_w_lg_ni1llil2431w(0) <= NOT ni1llil; + wire_ni1llii_w_lg_w_lg_n0Oli1i3428w3431w(0) <= wire_ni1llii_w_lg_n0Oli1i3428w(0) OR wire_ni1lOlO_w_lg_w_lg_n0Ol11i3240w3430w(0); + wire_ni1llii_w_lg_w_lg_ni1llil2426w2427w(0) <= wire_ni1llii_w_lg_ni1llil2426w(0) OR ni1l11l; + wire_ni1llii_w_lg_n0Oli1i3312w(0) <= n0Oli1i OR n0Ol0Oi; + wire_ni1llii_w_lg_n0Oli1i3331w(0) <= n0Oli1i OR n0Ol0OO; + PROCESS (wire_niO0011l_dataout, wire_ni1lOlO_PRN, wire_ni1lOlO_CLRN) + BEGIN + IF (wire_ni1lOlO_PRN = '0') THEN + n0il00i <= '1'; + n0il00l <= '1'; + n0il00O <= '1'; + n0il01i <= '1'; + n0il01l <= '1'; + n0il01O <= '1'; + n0il0ii <= '1'; + n0il0il <= '1'; + n0il0iO <= '1'; + n0il0li <= '1'; + n0il0ll <= '1'; + n0il0lO <= '1'; + n0il0Oi <= '1'; + n0il0Ol <= '1'; + n0il0OO <= '1'; + n0il10O <= '1'; + n0il1ii <= '1'; + n0il1il <= '1'; + n0il1iO <= '1'; + n0il1li <= '1'; + n0il1ll <= '1'; + n0il1lO <= '1'; + n0il1Oi <= '1'; + n0il1Ol <= '1'; + n0il1OO <= '1'; + n0ili0i <= '1'; + n0ili0l <= '1'; + n0ili0O <= '1'; + n0ili1i <= '1'; + n0ili1l <= '1'; + n0ili1O <= '1'; + n0iliii <= '1'; + n0iliil <= '1'; + n0iliiO <= '1'; + n0ilili <= '1'; + n0ilill <= '1'; + n0ililO <= '1'; + n0iliOi <= '1'; + n0iliOl <= '1'; + n0iliOO <= '1'; + n0ill0i <= '1'; + n0ill0l <= '1'; + n0ill0O <= '1'; + n0ill1i <= '1'; + n0ill1l <= '1'; + n0ill1O <= '1'; + n0illii <= '1'; + n0illil <= '1'; + n0illiO <= '1'; + n0illli <= '1'; + n0illll <= '1'; + n0illlO <= '1'; + n0illOi <= '1'; + n0illOl <= '1'; + n0illOO <= '1'; + n0ilO0i <= '1'; + n0ilO0l <= '1'; + n0ilO0O <= '1'; + n0ilO1i <= '1'; + n0ilO1l <= '1'; + n0ilO1O <= '1'; + n0ilOii <= '1'; + n0ilOil <= '1'; + n0ilOiO <= '1'; + n0ilOli <= '1'; + n0ilOll <= '1'; + n0ilOlO <= '1'; + n0ilOOi <= '1'; + n0ilOOl <= '1'; + n0ilOOO <= '1'; + n0iO00i <= '1'; + n0iO00l <= '1'; + n0iO00O <= '1'; + n0iO01i <= '1'; + n0iO01l <= '1'; + n0iO01O <= '1'; + n0iO0ii <= '1'; + n0iO0il <= '1'; + n0iO0iO <= '1'; + n0iO0li <= '1'; + n0iO0ll <= '1'; + n0iO0lO <= '1'; + n0iO0Oi <= '1'; + n0iO0Ol <= '1'; + n0iO0OO <= '1'; + n0iO10i <= '1'; + n0iO10l <= '1'; + n0iO10O <= '1'; + n0iO11i <= '1'; + n0iO11l <= '1'; + n0iO11O <= '1'; + n0iO1ii <= '1'; + n0iO1il <= '1'; + n0iO1iO <= '1'; + n0iO1li <= '1'; + n0iO1ll <= '1'; + n0iO1lO <= '1'; + n0iO1Oi <= '1'; + n0iO1Ol <= '1'; + n0iO1OO <= '1'; + n0iOi0i <= '1'; + n0iOi0l <= '1'; + n0iOi0O <= '1'; + n0iOi1i <= '1'; + n0iOi1l <= '1'; + n0iOi1O <= '1'; + n0iOiii <= '1'; + n0iOiil <= '1'; + n0iOiiO <= '1'; + n0iOili <= '1'; + n0iOill <= '1'; + n0iOilO <= '1'; + n0iOiOi <= '1'; + n0iOiOl <= '1'; + n0iOiOO <= '1'; + n0iOl0i <= '1'; + n0iOl0l <= '1'; + n0iOl0O <= '1'; + n0iOl1i <= '1'; + n0iOl1l <= '1'; + n0iOl1O <= '1'; + n0iOlii <= '1'; + n0iOlil <= '1'; + n0iOliO <= '1'; + n0iOlli <= '1'; + n0iOlll <= '1'; + n0iOllO <= '1'; + n0iOlOi <= '1'; + n0iOlOl <= '1'; + n0iOlOO <= '1'; + n0iOO0i <= '1'; + n0iOO0l <= '1'; + n0iOO0O <= '1'; + n0iOO1i <= '1'; + n0iOO1l <= '1'; + n0iOO1O <= '1'; + n0iOOii <= '1'; + n0iOOil <= '1'; + n0iOOiO <= '1'; + n0iOOli <= '1'; + n0iOOll <= '1'; + n0iOOlO <= '1'; + n0iOOOi <= '1'; + n0iOOOl <= '1'; + n0iOOOO <= '1'; + n0l110i <= '1'; + n0l110l <= '1'; + n0l110O <= '1'; + n0l111i <= '1'; + n0l111l <= '1'; + n0l111O <= '1'; + n0l11ii <= '1'; + n0l11il <= '1'; + n0l11iO <= '1'; + n0l11li <= '1'; + n0l11ll <= '1'; + n0l11lO <= '1'; + n0Oi0il <= '1'; + n0Oi0iO <= '1'; + n0Oi0li <= '1'; + n0Oi0ll <= '1'; + n0Oi0lO <= '1'; + n0Oi0Oi <= '1'; + n0Oi0Ol <= '1'; + n0Oi0OO <= '1'; + n0Oii0i <= '1'; + n0Oii0l <= '1'; + n0Oii0O <= '1'; + n0Oii1i <= '1'; + n0Oii1l <= '1'; + n0Oii1O <= '1'; + n0Oiiii <= '1'; + n0Oiiil <= '1'; + n0OiiiO <= '1'; + n0Oiili <= '1'; + n0Oiill <= '1'; + n0OiOOi <= '1'; + n0OiOOl <= '1'; + n0OiOOO <= '1'; + n0Ol00i <= '1'; + n0Ol00l <= '1'; + n0Ol00O <= '1'; + n0Ol01i <= '1'; + n0Ol01l <= '1'; + n0Ol01O <= '1'; + n0Ol0ii <= '1'; + n0Ol0il <= '1'; + n0Ol0iO <= '1'; + n0Ol0li <= '1'; + n0Ol0ll <= '1'; + n0Ol0lO <= '1'; + n0Ol0Oi <= '1'; + n0Ol0Ol <= '1'; + n0Ol0OO <= '1'; + n0Ol10i <= '1'; + n0Ol10l <= '1'; + n0Ol10O <= '1'; + n0Ol11i <= '1'; + n0Ol11l <= '1'; + n0Ol11O <= '1'; + n0Ol1ii <= '1'; + n0Ol1il <= '1'; + n0Ol1iO <= '1'; + n0Ol1li <= '1'; + n0Ol1ll <= '1'; + n0Ol1lO <= '1'; + n0Ol1Oi <= '1'; + n0Ol1Ol <= '1'; + n0Ol1OO <= '1'; + n0OOOil <= '1'; + n1llOil <= '1'; + n1O1l0l <= '1'; + n1O1lli <= '1'; + n1O1lll <= '1'; + n1O1llO <= '1'; + n1O1lOi <= '1'; + n1O1lOl <= '1'; + n1O1O0l <= '1'; + n1O1O0O <= '1'; + n1O1O1l <= '1'; + n1O1O1O <= '1'; + n1O1Oii <= '1'; + n1O1Oil <= '1'; + n1O1OiO <= '1'; + n1O1Oli <= '1'; + n1O1Oll <= '1'; + ni1100i <= '1'; + ni1101l <= '1'; + ni1101O <= '1'; + ni11i0i <= '1'; + ni11iiO <= '1'; + ni11ili <= '1'; + ni11ill <= '1'; + ni11ilO <= '1'; + ni11iOi <= '1'; + ni11iOl <= '1'; + ni11iOO <= '1'; + ni11l0i <= '1'; + ni11l0l <= '1'; + ni11l0O <= '1'; + ni11l1i <= '1'; + ni11l1l <= '1'; + ni11l1O <= '1'; + ni11lii <= '1'; + ni11lil <= '1'; + ni11liO <= '1'; + ni1iO0i <= '1'; + ni1iOlO <= '1'; + ni1iOOi <= '1'; + ni1iOOl <= '1'; + ni1iOOO <= '1'; + ni1l11i <= '1'; + ni1l11l <= '1'; + ni1ll0l <= '1'; + ni1ll0O <= '1'; + ni1lliO <= '1'; + ni1llli <= '1'; + ni1llll <= '1'; + ni1lllO <= '1'; + ni1llOi <= '1'; + ni1llOl <= '1'; + ni1llOO <= '1'; + ni1lO0i <= '1'; + ni1lO0l <= '1'; + ni1lO0O <= '1'; + ni1lO1i <= '1'; + ni1lO1l <= '1'; + ni1lO1O <= '1'; + ni1lOii <= '1'; + ni1lOil <= '1'; + ni1lOiO <= '1'; + ni1lOli <= '1'; + ni1lOll <= '1'; + ni1lOOi <= '1'; + ELSIF (wire_ni1lOlO_CLRN = '0') THEN + n0il00i <= '0'; + n0il00l <= '0'; + n0il00O <= '0'; + n0il01i <= '0'; + n0il01l <= '0'; + n0il01O <= '0'; + n0il0ii <= '0'; + n0il0il <= '0'; + n0il0iO <= '0'; + n0il0li <= '0'; + n0il0ll <= '0'; + n0il0lO <= '0'; + n0il0Oi <= '0'; + n0il0Ol <= '0'; + n0il0OO <= '0'; + n0il10O <= '0'; + n0il1ii <= '0'; + n0il1il <= '0'; + n0il1iO <= '0'; + n0il1li <= '0'; + n0il1ll <= '0'; + n0il1lO <= '0'; + n0il1Oi <= '0'; + n0il1Ol <= '0'; + n0il1OO <= '0'; + n0ili0i <= '0'; + n0ili0l <= '0'; + n0ili0O <= '0'; + n0ili1i <= '0'; + n0ili1l <= '0'; + n0ili1O <= '0'; + n0iliii <= '0'; + n0iliil <= '0'; + n0iliiO <= '0'; + n0ilili <= '0'; + n0ilill <= '0'; + n0ililO <= '0'; + n0iliOi <= '0'; + n0iliOl <= '0'; + n0iliOO <= '0'; + n0ill0i <= '0'; + n0ill0l <= '0'; + n0ill0O <= '0'; + n0ill1i <= '0'; + n0ill1l <= '0'; + n0ill1O <= '0'; + n0illii <= '0'; + n0illil <= '0'; + n0illiO <= '0'; + n0illli <= '0'; + n0illll <= '0'; + n0illlO <= '0'; + n0illOi <= '0'; + n0illOl <= '0'; + n0illOO <= '0'; + n0ilO0i <= '0'; + n0ilO0l <= '0'; + n0ilO0O <= '0'; + n0ilO1i <= '0'; + n0ilO1l <= '0'; + n0ilO1O <= '0'; + n0ilOii <= '0'; + n0ilOil <= '0'; + n0ilOiO <= '0'; + n0ilOli <= '0'; + n0ilOll <= '0'; + n0ilOlO <= '0'; + n0ilOOi <= '0'; + n0ilOOl <= '0'; + n0ilOOO <= '0'; + n0iO00i <= '0'; + n0iO00l <= '0'; + n0iO00O <= '0'; + n0iO01i <= '0'; + n0iO01l <= '0'; + n0iO01O <= '0'; + n0iO0ii <= '0'; + n0iO0il <= '0'; + n0iO0iO <= '0'; + n0iO0li <= '0'; + n0iO0ll <= '0'; + n0iO0lO <= '0'; + n0iO0Oi <= '0'; + n0iO0Ol <= '0'; + n0iO0OO <= '0'; + n0iO10i <= '0'; + n0iO10l <= '0'; + n0iO10O <= '0'; + n0iO11i <= '0'; + n0iO11l <= '0'; + n0iO11O <= '0'; + n0iO1ii <= '0'; + n0iO1il <= '0'; + n0iO1iO <= '0'; + n0iO1li <= '0'; + n0iO1ll <= '0'; + n0iO1lO <= '0'; + n0iO1Oi <= '0'; + n0iO1Ol <= '0'; + n0iO1OO <= '0'; + n0iOi0i <= '0'; + n0iOi0l <= '0'; + n0iOi0O <= '0'; + n0iOi1i <= '0'; + n0iOi1l <= '0'; + n0iOi1O <= '0'; + n0iOiii <= '0'; + n0iOiil <= '0'; + n0iOiiO <= '0'; + n0iOili <= '0'; + n0iOill <= '0'; + n0iOilO <= '0'; + n0iOiOi <= '0'; + n0iOiOl <= '0'; + n0iOiOO <= '0'; + n0iOl0i <= '0'; + n0iOl0l <= '0'; + n0iOl0O <= '0'; + n0iOl1i <= '0'; + n0iOl1l <= '0'; + n0iOl1O <= '0'; + n0iOlii <= '0'; + n0iOlil <= '0'; + n0iOliO <= '0'; + n0iOlli <= '0'; + n0iOlll <= '0'; + n0iOllO <= '0'; + n0iOlOi <= '0'; + n0iOlOl <= '0'; + n0iOlOO <= '0'; + n0iOO0i <= '0'; + n0iOO0l <= '0'; + n0iOO0O <= '0'; + n0iOO1i <= '0'; + n0iOO1l <= '0'; + n0iOO1O <= '0'; + n0iOOii <= '0'; + n0iOOil <= '0'; + n0iOOiO <= '0'; + n0iOOli <= '0'; + n0iOOll <= '0'; + n0iOOlO <= '0'; + n0iOOOi <= '0'; + n0iOOOl <= '0'; + n0iOOOO <= '0'; + n0l110i <= '0'; + n0l110l <= '0'; + n0l110O <= '0'; + n0l111i <= '0'; + n0l111l <= '0'; + n0l111O <= '0'; + n0l11ii <= '0'; + n0l11il <= '0'; + n0l11iO <= '0'; + n0l11li <= '0'; + n0l11ll <= '0'; + n0l11lO <= '0'; + n0Oi0il <= '0'; + n0Oi0iO <= '0'; + n0Oi0li <= '0'; + n0Oi0ll <= '0'; + n0Oi0lO <= '0'; + n0Oi0Oi <= '0'; + n0Oi0Ol <= '0'; + n0Oi0OO <= '0'; + n0Oii0i <= '0'; + n0Oii0l <= '0'; + n0Oii0O <= '0'; + n0Oii1i <= '0'; + n0Oii1l <= '0'; + n0Oii1O <= '0'; + n0Oiiii <= '0'; + n0Oiiil <= '0'; + n0OiiiO <= '0'; + n0Oiili <= '0'; + n0Oiill <= '0'; + n0OiOOi <= '0'; + n0OiOOl <= '0'; + n0OiOOO <= '0'; + n0Ol00i <= '0'; + n0Ol00l <= '0'; + n0Ol00O <= '0'; + n0Ol01i <= '0'; + n0Ol01l <= '0'; + n0Ol01O <= '0'; + n0Ol0ii <= '0'; + n0Ol0il <= '0'; + n0Ol0iO <= '0'; + n0Ol0li <= '0'; + n0Ol0ll <= '0'; + n0Ol0lO <= '0'; + n0Ol0Oi <= '0'; + n0Ol0Ol <= '0'; + n0Ol0OO <= '0'; + n0Ol10i <= '0'; + n0Ol10l <= '0'; + n0Ol10O <= '0'; + n0Ol11i <= '0'; + n0Ol11l <= '0'; + n0Ol11O <= '0'; + n0Ol1ii <= '0'; + n0Ol1il <= '0'; + n0Ol1iO <= '0'; + n0Ol1li <= '0'; + n0Ol1ll <= '0'; + n0Ol1lO <= '0'; + n0Ol1Oi <= '0'; + n0Ol1Ol <= '0'; + n0Ol1OO <= '0'; + n0OOOil <= '0'; + n1llOil <= '0'; + n1O1l0l <= '0'; + n1O1lli <= '0'; + n1O1lll <= '0'; + n1O1llO <= '0'; + n1O1lOi <= '0'; + n1O1lOl <= '0'; + n1O1O0l <= '0'; + n1O1O0O <= '0'; + n1O1O1l <= '0'; + n1O1O1O <= '0'; + n1O1Oii <= '0'; + n1O1Oil <= '0'; + n1O1OiO <= '0'; + n1O1Oli <= '0'; + n1O1Oll <= '0'; + ni1100i <= '0'; + ni1101l <= '0'; + ni1101O <= '0'; + ni11i0i <= '0'; + ni11iiO <= '0'; + ni11ili <= '0'; + ni11ill <= '0'; + ni11ilO <= '0'; + ni11iOi <= '0'; + ni11iOl <= '0'; + ni11iOO <= '0'; + ni11l0i <= '0'; + ni11l0l <= '0'; + ni11l0O <= '0'; + ni11l1i <= '0'; + ni11l1l <= '0'; + ni11l1O <= '0'; + ni11lii <= '0'; + ni11lil <= '0'; + ni11liO <= '0'; + ni1iO0i <= '0'; + ni1iOlO <= '0'; + ni1iOOi <= '0'; + ni1iOOl <= '0'; + ni1iOOO <= '0'; + ni1l11i <= '0'; + ni1l11l <= '0'; + ni1ll0l <= '0'; + ni1ll0O <= '0'; + ni1lliO <= '0'; + ni1llli <= '0'; + ni1llll <= '0'; + ni1lllO <= '0'; + ni1llOi <= '0'; + ni1llOl <= '0'; + ni1llOO <= '0'; + ni1lO0i <= '0'; + ni1lO0l <= '0'; + ni1lO0O <= '0'; + ni1lO1i <= '0'; + ni1lO1l <= '0'; + ni1lO1O <= '0'; + ni1lOii <= '0'; + ni1lOil <= '0'; + ni1lOiO <= '0'; + ni1lOli <= '0'; + ni1lOll <= '0'; + ni1lOOi <= '0'; + ELSIF (wire_niO0011l_dataout = '1' AND wire_niO0011l_dataout'event) THEN + n0il00i <= wire_n0l10ll_dataout; + n0il00l <= wire_n0l10lO_dataout; + n0il00O <= wire_n0l10Oi_dataout; + n0il01i <= wire_n0l10il_dataout; + n0il01l <= wire_n0l10iO_dataout; + n0il01O <= wire_n0l10li_dataout; + n0il0ii <= wire_n0l10Ol_dataout; + n0il0il <= wire_n0l10OO_dataout; + n0il0iO <= wire_n0l1i1i_dataout; + n0il0li <= wire_n0l1i1l_dataout; + n0il0ll <= wire_n0l1i1O_dataout; + n0il0lO <= wire_n0l1i0i_dataout; + n0il0Oi <= wire_n0l1i0l_dataout; + n0il0Ol <= wire_n0l1i0O_dataout; + n0il0OO <= wire_n0l1iii_dataout; + n0il10O <= wire_n0l11Oi_dataout; + n0il1ii <= wire_n0l11Ol_dataout; + n0il1il <= wire_n0l11OO_dataout; + n0il1iO <= wire_n0l101i_dataout; + n0il1li <= wire_n0l101l_dataout; + n0il1ll <= wire_n0l101O_dataout; + n0il1lO <= wire_n0l100i_dataout; + n0il1Oi <= wire_n0l100l_dataout; + n0il1Ol <= wire_n0l100O_dataout; + n0il1OO <= wire_n0l10ii_dataout; + n0ili0i <= wire_n0l1ill_dataout; + n0ili0l <= wire_n0l1ilO_dataout; + n0ili0O <= wire_n0l1iOi_dataout; + n0ili1i <= wire_n0l1iil_dataout; + n0ili1l <= wire_n0l1iiO_dataout; + n0ili1O <= wire_n0l1ili_dataout; + n0iliii <= wire_n0l1iOl_dataout; + n0iliil <= wire_n0l1iOO_dataout; + n0iliiO <= wire_n0l1l1i_dataout; + n0ilili <= wire_n0l1l1l_dataout; + n0ilill <= wire_n0l1l1O_dataout; + n0ililO <= wire_n0l1l0i_dataout; + n0iliOi <= wire_n0l1l0l_dataout; + n0iliOl <= wire_n0l1l0O_dataout; + n0iliOO <= wire_n0l1lii_dataout; + n0ill0i <= wire_n0l1lll_dataout; + n0ill0l <= wire_n0l1llO_dataout; + n0ill0O <= wire_n0l1lOi_dataout; + n0ill1i <= wire_n0l1lil_dataout; + n0ill1l <= wire_n0l1liO_dataout; + n0ill1O <= wire_n0l1lli_dataout; + n0illii <= wire_n0l1lOl_dataout; + n0illil <= wire_n0l1lOO_dataout; + n0illiO <= wire_n0l1O1i_dataout; + n0illli <= wire_n0l1O1l_dataout; + n0illll <= wire_n0l1O1O_dataout; + n0illlO <= wire_n0l1O0i_dataout; + n0illOi <= wire_n0l1O0l_dataout; + n0illOl <= wire_n0l1O0O_dataout; + n0illOO <= wire_n0l1Oii_dataout; + n0ilO0i <= wire_n0l1Oll_dataout; + n0ilO0l <= wire_n0l1OlO_dataout; + n0ilO0O <= wire_n0l1OOi_dataout; + n0ilO1i <= wire_n0l1Oil_dataout; + n0ilO1l <= wire_n0l1OiO_dataout; + n0ilO1O <= wire_n0l1Oli_dataout; + n0ilOii <= wire_n0l1OOl_dataout; + n0ilOil <= wire_n0l1OOO_dataout; + n0ilOiO <= wire_n0l011i_dataout; + n0ilOli <= wire_n0l011l_dataout; + n0ilOll <= wire_n0l011O_dataout; + n0ilOlO <= wire_n0l010i_dataout; + n0ilOOi <= wire_n0l010l_dataout; + n0ilOOl <= wire_n0l010O_dataout; + n0ilOOO <= wire_n0l01ii_dataout; + n0iO00i <= wire_n0l00ll_dataout; + n0iO00l <= wire_n0l00lO_dataout; + n0iO00O <= wire_n0l00Oi_dataout; + n0iO01i <= wire_n0l00il_dataout; + n0iO01l <= wire_n0l00iO_dataout; + n0iO01O <= wire_n0l00li_dataout; + n0iO0ii <= wire_n0l00Ol_dataout; + n0iO0il <= wire_n0l00OO_dataout; + n0iO0iO <= wire_n0l0i1i_dataout; + n0iO0li <= wire_n0l0i1l_dataout; + n0iO0ll <= wire_n0l0i1O_dataout; + n0iO0lO <= wire_n0l0i0i_dataout; + n0iO0Oi <= wire_n0l0i0l_dataout; + n0iO0Ol <= wire_n0l0i0O_dataout; + n0iO0OO <= wire_n0l0iii_dataout; + n0iO10i <= wire_n0l01ll_dataout; + n0iO10l <= wire_n0l01lO_dataout; + n0iO10O <= wire_n0l01Oi_dataout; + n0iO11i <= wire_n0l01il_dataout; + n0iO11l <= wire_n0l01iO_dataout; + n0iO11O <= wire_n0l01li_dataout; + n0iO1ii <= wire_n0l01Ol_dataout; + n0iO1il <= wire_n0l01OO_dataout; + n0iO1iO <= wire_n0l001i_dataout; + n0iO1li <= wire_n0l001l_dataout; + n0iO1ll <= wire_n0l001O_dataout; + n0iO1lO <= wire_n0l000i_dataout; + n0iO1Oi <= wire_n0l000l_dataout; + n0iO1Ol <= wire_n0l000O_dataout; + n0iO1OO <= wire_n0l00ii_dataout; + n0iOi0i <= wire_n0l0ill_dataout; + n0iOi0l <= wire_n0l0ilO_dataout; + n0iOi0O <= wire_n0l0iOi_dataout; + n0iOi1i <= wire_n0l0iil_dataout; + n0iOi1l <= wire_n0l0iiO_dataout; + n0iOi1O <= wire_n0l0ili_dataout; + n0iOiii <= wire_n0l0iOl_dataout; + n0iOiil <= wire_n0l0iOO_dataout; + n0iOiiO <= wire_n0l0l1i_dataout; + n0iOili <= wire_n0l0l1l_dataout; + n0iOill <= wire_n0l0l1O_dataout; + n0iOilO <= wire_n0l0l0i_dataout; + n0iOiOi <= wire_n0l0l0l_dataout; + n0iOiOl <= wire_n0l0l0O_dataout; + n0iOiOO <= wire_n0l0lii_dataout; + n0iOl0i <= wire_n0l0lll_dataout; + n0iOl0l <= wire_n0l0llO_dataout; + n0iOl0O <= wire_n0l0lOi_dataout; + n0iOl1i <= wire_n0l0lil_dataout; + n0iOl1l <= wire_n0l0liO_dataout; + n0iOl1O <= wire_n0l0lli_dataout; + n0iOlii <= wire_n0l0lOl_dataout; + n0iOlil <= wire_n0l0lOO_dataout; + n0iOliO <= wire_n0l0O1i_dataout; + n0iOlli <= wire_n0l0O1l_dataout; + n0iOlll <= wire_n0l0O1O_dataout; + n0iOllO <= wire_n0l0O0i_dataout; + n0iOlOi <= wire_n0l0O0l_dataout; + n0iOlOl <= wire_n0l0O0O_dataout; + n0iOlOO <= wire_n0l0Oii_dataout; + n0iOO0i <= wire_n0l0Oll_dataout; + n0iOO0l <= wire_n0l0OlO_dataout; + n0iOO0O <= wire_n0l0OOi_dataout; + n0iOO1i <= wire_n0l0Oil_dataout; + n0iOO1l <= wire_n0l0OiO_dataout; + n0iOO1O <= wire_n0l0Oli_dataout; + n0iOOii <= wire_n0l0OOl_dataout; + n0iOOil <= wire_n0l0OOO_dataout; + n0iOOiO <= wire_n0li11i_dataout; + n0iOOli <= wire_n0li11l_dataout; + n0iOOll <= wire_n0li11O_dataout; + n0iOOlO <= wire_n0li10i_dataout; + n0iOOOi <= wire_n0li10l_dataout; + n0iOOOl <= wire_n0li10O_dataout; + n0iOOOO <= wire_n0li1ii_dataout; + n0l110i <= wire_n0li1ll_dataout; + n0l110l <= wire_n0li1lO_dataout; + n0l110O <= wire_n0li1Oi_dataout; + n0l111i <= wire_n0li1il_dataout; + n0l111l <= wire_n0li1iO_dataout; + n0l111O <= wire_n0li1li_dataout; + n0l11ii <= wire_n0li1Ol_dataout; + n0l11il <= wire_n0li1OO_dataout; + n0l11iO <= wire_n0li01i_dataout; + n0l11li <= wire_n0li01l_dataout; + n0l11ll <= wire_n0li01O_dataout; + n0l11lO <= wire_n0li00i_dataout; + n0Oi0il <= wire_n0OiilO_dataout; + n0Oi0iO <= wire_n0OiiOi_dataout; + n0Oi0li <= wire_n0OiiOl_dataout; + n0Oi0ll <= wire_n0OiiOO_dataout; + n0Oi0lO <= wire_n0Oil1i_dataout; + n0Oi0Oi <= wire_n0Oil1l_dataout; + n0Oi0Ol <= wire_n0Oil1O_dataout; + n0Oi0OO <= wire_n0Oil0i_dataout; + n0Oii0i <= wire_n0Oilil_dataout; + n0Oii0l <= wire_n0OiliO_dataout; + n0Oii0O <= wire_n0Oilli_dataout; + n0Oii1i <= wire_n0Oil0l_dataout; + n0Oii1l <= wire_n0Oil0O_dataout; + n0Oii1O <= wire_n0Oilii_dataout; + n0Oiiii <= wire_n0Oilll_dataout; + n0Oiiil <= wire_n0OillO_dataout; + n0OiiiO <= wire_n0OilOi_dataout; + n0Oiili <= wire_n0OilOl_dataout; + n0Oiill <= wire_n0Oli1l_dataout; + n0OiOOi <= wire_n0Oli1O_dataout; + n0OiOOl <= wire_n0Oli0i_dataout; + n0OiOOO <= wire_n0Oli0l_dataout; + n0Ol00i <= wire_n0OlliO_dataout; + n0Ol00l <= wire_n0Ollli_dataout; + n0Ol00O <= wire_n0Ollll_dataout; + n0Ol01i <= wire_n0Oll0O_dataout; + n0Ol01l <= wire_n0Ollii_dataout; + n0Ol01O <= wire_n0Ollil_dataout; + n0Ol0ii <= wire_n0OlllO_dataout; + n0Ol0il <= wire_n0OllOi_dataout; + n0Ol0iO <= wire_n0OllOl_dataout; + n0Ol0li <= wire_n0OllOO_dataout; + n0Ol0ll <= wire_n0OlO1i_dataout; + n0Ol0lO <= wire_n0OlO1l_dataout; + n0Ol0Oi <= wire_n0OlO1O_dataout; + n0Ol0Ol <= wire_n0OlO0i_dataout; + n0Ol0OO <= wire_n0OlO0l_dataout; + n0Ol10i <= wire_n0OliiO_dataout; + n0Ol10l <= wire_n0Olili_dataout; + n0Ol10O <= wire_n0Olill_dataout; + n0Ol11i <= wire_n0Oli0O_dataout; + n0Ol11l <= wire_n0Oliii_dataout; + n0Ol11O <= wire_n0Oliil_dataout; + n0Ol1ii <= wire_n0OlilO_dataout; + n0Ol1il <= wire_n0OliOi_dataout; + n0Ol1iO <= wire_n0OliOl_dataout; + n0Ol1li <= wire_n0OliOO_dataout; + n0Ol1ll <= wire_n0Oll1i_dataout; + n0Ol1lO <= wire_n0Oll1l_dataout; + n0Ol1Oi <= wire_n0Oll1O_dataout; + n0Ol1Ol <= wire_n0Oll0i_dataout; + n0Ol1OO <= wire_n0Oll0l_dataout; + n0OOOil <= ni1101l; + n1llOil <= n1O1lli; + n1O1l0l <= wire_n1O1OlO_dataout; + n1O1lli <= wire_n1O1OOi_dataout; + n1O1lll <= wire_n1O1OOl_dataout; + n1O1llO <= wire_n1O1OOO_dataout; + n1O1lOi <= wire_n1O011i_dataout; + n1O1lOl <= wire_n1O011l_dataout; + n1O1O0l <= wire_n1O01il_dataout; + n1O1O0O <= wire_n1O01iO_dataout; + n1O1O1l <= wire_n1O010l_dataout; + n1O1O1O <= wire_n1O010O_dataout; + n1O1Oii <= wire_n1O01li_dataout; + n1O1Oil <= wire_n1O01ll_dataout; + n1O1OiO <= wire_n1O01lO_dataout; + n1O1Oli <= wire_n1O01Oi_dataout; + n1O1Oll <= wire_n1O01Ol_dataout; + ni1100i <= wire_ni110iO_dataout; + ni1101l <= wire_ni110ii_dataout; + ni1101O <= wire_ni110il_dataout; + ni11i0i <= wire_ni11O1l_dataout; + ni11iiO <= wire_ni11O1O_dataout; + ni11ili <= wire_ni11O0i_dataout; + ni11ill <= wire_ni11O0l_dataout; + ni11ilO <= wire_ni11O0O_dataout; + ni11iOi <= wire_ni11Oii_dataout; + ni11iOl <= wire_ni11Oil_dataout; + ni11iOO <= wire_ni11OiO_dataout; + ni11l0i <= wire_ni11OOi_dataout; + ni11l0l <= wire_ni11OOl_dataout; + ni11l0O <= wire_ni11OOO_dataout; + ni11l1i <= wire_ni11Oli_dataout; + ni11l1l <= wire_ni11Oll_dataout; + ni11l1O <= wire_ni11OlO_dataout; + ni11lii <= wire_ni1011i_dataout; + ni11lil <= wire_ni1011l_dataout; + ni11liO <= wire_ni1011O_dataout; + ni1iO0i <= wire_ni1l11O_dataout; + ni1iOlO <= wire_ni1l10i_dataout; + ni1iOOi <= wire_ni1l10l_dataout; + ni1iOOl <= wire_ni1l10O_dataout; + ni1iOOO <= wire_ni1l1ii_dataout; + ni1l11i <= wire_ni1l1il_dataout; + ni1l11l <= wire_ni1lOOO_dataout; + ni1ll0l <= wire_ni1O11i_dataout; + ni1ll0O <= wire_ni1O11l_dataout; + ni1lliO <= wire_ni1O10i_dataout; + ni1llli <= wire_ni1O10l_dataout; + ni1llll <= wire_ni1O10O_dataout; + ni1lllO <= wire_ni1O1ii_dataout; + ni1llOi <= wire_ni1O1il_dataout; + ni1llOl <= wire_ni1O1iO_dataout; + ni1llOO <= wire_ni1O1li_dataout; + ni1lO0i <= wire_ni1O1Ol_dataout; + ni1lO0l <= wire_ni1O1OO_dataout; + ni1lO0O <= wire_ni1O01i_dataout; + ni1lO1i <= wire_ni1O1ll_dataout; + ni1lO1l <= wire_ni1O1lO_dataout; + ni1lO1O <= wire_ni1O1Oi_dataout; + ni1lOii <= wire_ni1O01l_dataout; + ni1lOil <= wire_ni1O01O_dataout; + ni1lOiO <= wire_ni1O00i_dataout; + ni1lOli <= wire_ni1O00l_dataout; + ni1lOll <= wire_ni1O00O_dataout; + ni1lOOi <= wire_ni1O0ii_dataout; + END IF; + END PROCESS; + wire_ni1lOlO_CLRN <= ((niOO0l1Ol54 XOR niOO0l1Ol53) AND wire_niO0010l_dataout); + wire_ni1lOlO_PRN <= (niOO0l1Oi56 XOR niOO0l1Oi55); + wire_ni1lOlO_w2812w(0) <= wire_ni1lOlO_w_lg_w_lg_w_lg_w_lg_ni11l0O2802w2803w2806w2809w(0) AND wire_ni1lOlO_w_lg_w_lg_ni11liO2810w2811w(0); + wire_ni1lOlO_w_lg_w_lg_w_lg_w_lg_ni11l0O2802w2803w2806w2809w(0) <= wire_ni1lOlO_w_lg_w_lg_w_lg_ni11l0O2802w2803w2806w(0) AND wire_ni1lOlO_w_lg_w_lg_ni11lil2807w2808w(0); + wire_ni1lOlO_w_lg_w_lg_w_lg_n0Ol01l3235w3236w3237w(0) <= wire_ni1lOlO_w_lg_w_lg_n0Ol01l3235w3236w(0) AND niOO0il1i; + wire_ni1lOlO_w_lg_w_lg_n0Ol01i3231w3232w(0) <= wire_ni1lOlO_w_lg_n0Ol01i3231w(0) AND n0Ol01l; + wire_ni1lOlO_w_lg_w_lg_ni1lllO2451w2454w(0) <= wire_ni1lOlO_w_lg_ni1lllO2451w(0) AND wire_ni1lOlO_w_lg_w_lg_ni1lOOi2452w2453w(0); + wire_ni1lOlO_w_lg_w_lg_w_lg_ni11l0O2802w2803w2806w(0) <= wire_ni1lOlO_w_lg_w_lg_ni11l0O2802w2803w(0) AND wire_ni1lOlO_w_lg_w_lg_ni11lii2804w2805w(0); + wire_ni1lOlO_w_lg_w_lg_n0Ol01i3229w3411w(0) <= wire_ni1lOlO_w_lg_n0Ol01i3229w(0) AND wire_ni1lOlO_w_lg_n0Ol11i3240w(0); + wire_ni1lOlO_w_lg_w_lg_n0Ol01l3235w3412w(0) <= wire_ni1lOlO_w_lg_n0Ol01l3235w(0) AND wire_ni1lOlO_w_lg_n0Ol01i3228w(0); + wire_ni1lOlO_w_lg_w_lg_n0Ol01l3235w3236w(0) <= wire_ni1lOlO_w_lg_n0Ol01l3235w(0) AND n0Ol01i; + wire_ni1lOlO_w_lg_w_lg_n0Ol01O3238w3239w(0) <= wire_ni1lOlO_w_lg_n0Ol01O3238w(0) AND n0Ol11i; + wire_ni1lOlO_w_lg_w_lg_n0Ol01O3238w3399w(0) <= wire_ni1lOlO_w_lg_n0Ol01O3238w(0) AND niOO0ii0O; + wire_ni1lOlO_w_lg_w_lg_n0Ol11i3240w3430w(0) <= wire_ni1lOlO_w_lg_n0Ol11i3240w(0) AND wire_ni1lOlO_w_lg_n0Ol0OO3429w(0); + wire_ni1lOlO_w_lg_w_lg_n0Ol11i3240w3391w(0) <= wire_ni1lOlO_w_lg_n0Ol11i3240w(0) AND niOO0il1i; + wire_ni1lOlO_w_lg_w_lg_ni1lOOi2452w2562w(0) <= wire_ni1lOlO_w_lg_ni1lOOi2452w(0) AND ni1llll; + wire_ni1lOlO_w_lg_w_lg_n0Oii0l3379w3380w(0) <= wire_ni1lOlO_w_lg_n0Oii0l3379w(0) AND wire_n0Oi1lO_o; + wire_ni1lOlO_w_lg_n0Oii0O3381w(0) <= n0Oii0O AND n0Oii1O; + wire_ni1lOlO_w_lg_n0Oii1O3342w(0) <= n0Oii1O AND wire_ni1lOlO_w_lg_n0Oiiii3341w(0); + wire_ni1lOlO_w_lg_n0Oiiii3341w(0) <= n0Oiiii AND n0Oii0l; + wire_ni1lOlO_w_lg_n0OiiiO3339w(0) <= n0OiiiO AND wire_w_lg_w_k_hip_range2413w3338w(0); + wire_ni1lOlO_w_lg_n0OiOOl3227w(0) <= n0OiOOl AND n1O1lli; + wire_ni1lOlO_w_lg_n0Ol00i3334w(0) <= n0Ol00i AND wire_w_lg_w_lg_w_k_hip_range2413w2429w3333w(0); + wire_ni1lOlO_w_lg_n0Ol01i3231w(0) <= n0Ol01i AND niOO0il1i; + wire_ni1lOlO_w_lg_n0Ol0OO3429w(0) <= n0Ol0OO AND wire_ni1lOlO_w_lg_n0Ol01i3229w(0); + wire_ni1lOlO_w_lg_n0Ol0OO3414w(0) <= n0Ol0OO AND wire_ni1lOlO_w_lg_w_lg_w_lg_n0Ol01i3229w3411w3413w(0); + wire_ni1lOlO_w_lg_n0Ol0OO3389w(0) <= n0Ol0OO AND n0Ol01l; + wire_ni1lOlO_w_lg_ni1100i2828w(0) <= ni1100i AND ni1101O; + wire_ni1lOlO_w_lg_ni1ll0l2460w(0) <= ni1ll0l AND wire_n0OOO0O_w_q_range2445w(0); + wire_ni1lOlO_w_lg_ni1ll0l2458w(0) <= ni1ll0l AND wire_n0OOO0O_w_q_range2448w(0); + wire_ni1lOlO_w_lg_ni1ll0O2564w(0) <= ni1ll0O AND wire_ni1lOlO_w_lg_ni1lOOi2563w(0); + wire_ni1lOlO_w_lg_ni1lllO2456w(0) <= ni1lllO AND ni1l11l; + wire_ni1lOlO_w_lg_ni1lllO2451w(0) <= ni1lllO AND ni1ll0O; + wire_ni1lOlO_w_lg_ni1lOil2559w(0) <= ni1lOil AND wire_ni1lOlO_w_lg_ni1iOlO2558w(0); + wire_ni1lOlO_w_lg_ni1lOll2479w(0) <= ni1lOll AND wire_ni1lOlO_w_lg_ni1lOli2478w(0); + wire_ni1lOlO_w_lg_w_lg_n0OiOOl3227w3968w(0) <= NOT wire_ni1lOlO_w_lg_n0OiOOl3227w(0); + wire_ni1lOlO_w_lg_w_lg_ni11l0O2802w2803w(0) <= NOT wire_ni1lOlO_w_lg_ni11l0O2802w(0); + wire_ni1lOlO_w_lg_w_lg_ni11lii2804w2805w(0) <= NOT wire_ni1lOlO_w_lg_ni11lii2804w(0); + wire_ni1lOlO_w_lg_w_lg_ni11lil2807w2808w(0) <= NOT wire_ni1lOlO_w_lg_ni11lil2807w(0); + wire_ni1lOlO_w_lg_w_lg_ni11liO2810w2811w(0) <= NOT wire_ni1lOlO_w_lg_ni11liO2810w(0); + wire_ni1lOlO_w_lg_n0Oiiii3421w(0) <= NOT n0Oiiii; + wire_ni1lOlO_w_lg_n0OiOOl3328w(0) <= NOT n0OiOOl; + wire_ni1lOlO_w_lg_n0Ol00i3386w(0) <= NOT n0Ol00i; + wire_ni1lOlO_w_lg_n0Ol01i3229w(0) <= NOT n0Ol01i; + wire_ni1lOlO_w_lg_n0Ol01l3235w(0) <= NOT n0Ol01l; + wire_ni1lOlO_w_lg_n0Ol01O3238w(0) <= NOT n0Ol01O; + wire_ni1lOlO_w_lg_n0Ol0OO3319w(0) <= NOT n0Ol0OO; + wire_ni1lOlO_w_lg_n0Ol11i3240w(0) <= NOT n0Ol11i; + wire_ni1lOlO_w_lg_n0Ol11l3329w(0) <= NOT n0Ol11l; + wire_ni1lOlO_w_lg_n0Ol1ii3625w(0) <= NOT n0Ol1ii; + wire_ni1lOlO_w_lg_n0Ol1il3623w(0) <= NOT n0Ol1il; + wire_ni1lOlO_w_lg_n0Ol1iO3621w(0) <= NOT n0Ol1iO; + wire_ni1lOlO_w_lg_n0Ol1li3619w(0) <= NOT n0Ol1li; + wire_ni1lOlO_w_lg_n0Ol1ll3617w(0) <= NOT n0Ol1ll; + wire_ni1lOlO_w_lg_n0Ol1lO3615w(0) <= NOT n0Ol1lO; + wire_ni1lOlO_w_lg_n0Ol1Oi3613w(0) <= NOT n0Ol1Oi; + wire_ni1lOlO_w_lg_n0Ol1Ol3611w(0) <= NOT n0Ol1Ol; + wire_ni1lOlO_w_lg_n0Ol1OO3610w(0) <= NOT n0Ol1OO; + wire_ni1lOlO_w_lg_n1O1lli3233w(0) <= NOT n1O1lli; + wire_ni1lOlO_w_lg_n1O1lOl3726w(0) <= NOT n1O1lOl; + wire_ni1lOlO_w_lg_ni11i0i2801w(0) <= NOT ni11i0i; + wire_ni1lOlO_w_lg_ni11liO2764w(0) <= NOT ni11liO; + wire_ni1lOlO_w_lg_ni1iO0i2556w(0) <= NOT ni1iO0i; + wire_ni1lOlO_w_lg_ni1iOlO2558w(0) <= NOT ni1iOlO; + wire_ni1lOlO_w_lg_ni1iOOO2462w(0) <= NOT ni1iOOO; + wire_ni1lOlO_w_lg_ni1l11i2560w(0) <= NOT ni1l11i; + wire_ni1lOlO_w_lg_ni1l11l2447w(0) <= NOT ni1l11l; + wire_ni1lOlO_w_lg_ni1lliO2423w(0) <= NOT ni1lliO; + wire_ni1lOlO_w_lg_ni1llli2476w(0) <= NOT ni1llli; + wire_ni1lOlO_w_lg_ni1llll2574w(0) <= NOT ni1llll; + wire_ni1lOlO_w_lg_ni1llOl2608w(0) <= NOT ni1llOl; + wire_ni1lOlO_w_lg_ni1llOO2606w(0) <= NOT ni1llOO; + wire_ni1lOlO_w_lg_ni1lO0i2598w(0) <= NOT ni1lO0i; + wire_ni1lOlO_w_lg_ni1lO0l2596w(0) <= NOT ni1lO0l; + wire_ni1lOlO_w_lg_ni1lO0O2594w(0) <= NOT ni1lO0O; + wire_ni1lOlO_w_lg_ni1lO1i2604w(0) <= NOT ni1lO1i; + wire_ni1lOlO_w_lg_ni1lO1l2602w(0) <= NOT ni1lO1l; + wire_ni1lOlO_w_lg_ni1lO1O2600w(0) <= NOT ni1lO1O; + wire_ni1lOlO_w_lg_ni1lOii2593w(0) <= NOT ni1lOii; + wire_ni1lOlO_w_lg_ni1lOli2478w(0) <= NOT ni1lOli; + wire_ni1lOlO_w_lg_ni1lOll2437w(0) <= NOT ni1lOll; + wire_ni1lOlO_w_lg_ni1lOOi2452w(0) <= NOT ni1lOOi; + wire_ni1lOlO_w_lg_w_lg_w_lg_n0Ol01i3229w3411w3413w(0) <= wire_ni1lOlO_w_lg_w_lg_n0Ol01i3229w3411w(0) OR wire_ni1lOlO_w_lg_w_lg_n0Ol01l3235w3412w(0); + wire_ni1lOlO_w_lg_w_lg_w_lg_n0Oii0l3379w3380w3382w(0) <= wire_ni1lOlO_w_lg_w_lg_n0Oii0l3379w3380w(0) OR wire_ni1lOlO_w_lg_n0Oii0O3381w(0); + wire_ni1lOlO_w_lg_w_lg_ni1lOOi2452w2453w(0) <= wire_ni1lOlO_w_lg_ni1lOOi2452w(0) OR niOO0l00i; + wire_ni1lOlO_w_lg_n0Oii0l3379w(0) <= n0Oii0l OR n0Oii0i; + wire_ni1lOlO_w_lg_n0Ol01i3228w(0) <= n0Ol01i OR n0Ol11i; + wire_ni1lOlO_w_lg_ni1ll0l2534w(0) <= ni1ll0l OR ni1l11l; + wire_ni1lOlO_w_lg_ni1lOOi2563w(0) <= ni1lOOi OR wire_ni1lOlO_w_lg_w_lg_ni1lOOi2452w2562w(0); + wire_ni1lOlO_w_lg_ni11l0O2802w(0) <= ni11l0O XOR ni11iiO; + wire_ni1lOlO_w_lg_ni11lii2804w(0) <= ni11lii XOR ni11ili; + wire_ni1lOlO_w_lg_ni11lil2807w(0) <= ni11lil XOR ni11ill; + wire_ni1lOlO_w_lg_ni11liO2810w(0) <= ni11liO XOR ni11ilO; + PROCESS (core_clk, core_rstn) + BEGIN + IF (core_rstn = '0') THEN + niO001ii <= '0'; + niO01OOl <= '0'; + ELSIF (core_clk = '1' AND core_clk'event) THEN + niO001ii <= niOO0lliO; + niO01OOl <= niO001ii; + END IF; + END PROCESS; + wire_niO0010O_w_lg_niO01OOl8791w(0) <= NOT niO01OOl; + PROCESS (phy_clk, phy_rstn) + BEGIN + IF (phy_rstn = '0') THEN + niO001il <= '0'; + niO001ll <= '0'; + ELSIF (phy_clk = '1' AND phy_clk'event) THEN + niO001il <= niO001ll; + niO001ll <= niOO0lliO; + END IF; + END PROCESS; + PROCESS (phy_clk, wire_niO001iO_dataout) + BEGIN + IF (wire_niO001iO_dataout = '0') THEN + n000i00i <= '0'; + n000i01i <= '0'; + n000i01l <= '0'; + n000i01O <= '0'; + n000i10i <= '0'; + n000i10l <= '0'; + n000i10O <= '0'; + n000i1ii <= '0'; + n000i1il <= '0'; + n000i1iO <= '0'; + n000i1li <= '0'; + n000i1ll <= '0'; + n000i1lO <= '0'; + n000i1Oi <= '0'; + n000i1Ol <= '0'; + n000i1OO <= '0'; + n000lilO <= '0'; + n000llil <= '0'; + n000lliO <= '0'; + n000llli <= '0'; + n000llll <= '0'; + n000lllO <= '0'; + n000llOi <= '0'; + n000llOl <= '0'; + n000llOO <= '0'; + n000lO0i <= '0'; + n000lO0l <= '0'; + n000lO0O <= '0'; + n000lO1i <= '0'; + n000lO1l <= '0'; + n000lO1O <= '0'; + n000lOii <= '0'; + n000lOil <= '0'; + n00100ii <= '0'; + n00100il <= '0'; + n00100iO <= '0'; + n00100li <= '0'; + n0010ili <= '0'; + n0010ill <= '0'; + n0010ilO <= '0'; + n0010iOi <= '0'; + n0010iOl <= '0'; + n0010iOO <= '0'; + n0010l0i <= '0'; + n0010l1i <= '0'; + n0010l1l <= '0'; + n0010l1O <= '0'; + n001i10i <= '0'; + n001i10l <= '0'; + n001i10O <= '0'; + n001i11i <= '0'; + n001i11l <= '0'; + n001i11O <= '0'; + n001iilO <= '0'; + n001iiOi <= '0'; + n001iiOl <= '0'; + n001iiOO <= '0'; + n001il0i <= '0'; + n001il0l <= '0'; + n001il0O <= '0'; + n001il1i <= '0'; + n001il1l <= '0'; + n001il1O <= '0'; + n001ilii <= '0'; + n001ilil <= '0'; + n001iliO <= '0'; + n001illi <= '0'; + n001illl <= '0'; + n001illO <= '0'; + n001ilOi <= '0'; + n001ilOl <= '0'; + n001ilOO <= '0'; + n001iO0i <= '0'; + n001iO0l <= '0'; + n001iO0O <= '0'; + n001iO1i <= '0'; + n001iO1l <= '0'; + n001iO1O <= '0'; + n001iOii <= '0'; + n001ll1O <= '0'; + n00i100i <= '0'; + n00i100l <= '0'; + n00i100O <= '0'; + n00i101l <= '0'; + n00i101O <= '0'; + n00i10ii <= '0'; + n00i10il <= '0'; + n00i10iO <= '0'; + n00i10li <= '0'; + n00i10ll <= '0'; + n00i10lO <= '0'; + n00i10Oi <= '0'; + n00i10Ol <= '0'; + n00i10OO <= '0'; + n00i110O <= '0'; + n00i1i1i <= '0'; + n00iii0i <= '0'; + n00iii0l <= '0'; + n00iii1l <= '0'; + n00iii1O <= '0'; + n00iiiOi <= '0'; + n00iilii <= '0'; + n00iilil <= '0'; + n00iiliO <= '0'; + n00iilli <= '0'; + n00il1li <= '0'; + n00il1OO <= '0'; + n00ill0i <= '0'; + n00ill0l <= '0'; + n00ill0O <= '0'; + n00ill1i <= '0'; + n00ill1l <= '0'; + n00ill1O <= '0'; + n00illii <= '0'; + n00illil <= '0'; + n00illiO <= '0'; + n00illli <= '0'; + n00illll <= '0'; + n00illlO <= '0'; + n00illOi <= '0'; + n00illOl <= '0'; + n00illOO <= '0'; + n00ilO0i <= '0'; + n00ilO0l <= '0'; + n00ilO0O <= '0'; + n00ilO1i <= '0'; + n00ilO1l <= '0'; + n00ilO1O <= '0'; + n00ilOii <= '0'; + n00ilOil <= '0'; + n00ilOiO <= '0'; + n00ilOli <= '0'; + n00ilOll <= '0'; + n00ilOlO <= '0'; + n00ilOOi <= '0'; + n00ilOOl <= '0'; + n00ilOOO <= '0'; + n00iO01i <= '0'; + n00iO10i <= '0'; + n00iO10l <= '0'; + n00iO10O <= '0'; + n00iO11i <= '0'; + n00iO11l <= '0'; + n00iO11O <= '0'; + n00iO1ii <= '0'; + n00iO1il <= '0'; + n00iO1iO <= '0'; + n00iO1li <= '0'; + n00iO1ll <= '0'; + n00iO1lO <= '0'; + n00iO1Oi <= '0'; + n00iO1Ol <= '0'; + n00iO1OO <= '0'; + n00l0i0i <= '0'; + n00l0i0l <= '0'; + n00l0i0O <= '0'; + n00l0i1i <= '0'; + n00l0i1l <= '0'; + n00l0i1O <= '0'; + n00l0iii <= '0'; + n00l0iil <= '0'; + n00l0iiO <= '0'; + n00l0ili <= '0'; + n00l0ill <= '0'; + n00l0ilO <= '0'; + n00l0iOi <= '0'; + n00l0iOl <= '0'; + n00l0iOO <= '0'; + n00l0l0i <= '0'; + n00l0l0l <= '0'; + n00l0l0O <= '0'; + n00l0l1i <= '0'; + n00l0l1l <= '0'; + n00l0l1O <= '0'; + n00l0lii <= '0'; + n00l0lil <= '0'; + n00l0liO <= '0'; + n00l0lli <= '0'; + n00l0lll <= '0'; + n00l0llO <= '0'; + n00l0lOi <= '0'; + n00l0lOl <= '0'; + n00l0lOO <= '0'; + n00l0O0i <= '0'; + n00l0O0l <= '0'; + n00l0O0O <= '0'; + n00l0O1i <= '0'; + n00l0O1l <= '0'; + n00l0O1O <= '0'; + n00l0Oii <= '0'; + n00l0Oil <= '0'; + n00l0OOi <= '0'; + n00llOll <= '0'; + n00llOlO <= '0'; + n00llOOi <= '0'; + n00llOOl <= '0'; + n00lO00i <= '0'; + n00lO00l <= '0'; + n00lO00O <= '0'; + n00lO01i <= '0'; + n00lO01l <= '0'; + n00lO01O <= '0'; + n00lO0ii <= '0'; + n00lO0il <= '0'; + n00lO1Ol <= '0'; + n00lO1OO <= '0'; + n00lOl0l <= '0'; + n00lOl0O <= '0'; + n00lOlii <= '0'; + n00lOlil <= '0'; + n00lOliO <= '0'; + n00lOlli <= '0'; + n00O00ii <= '0'; + n00O100i <= '0'; + n00O100l <= '0'; + n00O100O <= '0'; + n00O101i <= '0'; + n00O101l <= '0'; + n00O101O <= '0'; + n00O10ii <= '0'; + n00O10il <= '0'; + n00O10iO <= '0'; + n00O10li <= '0'; + n00O10ll <= '0'; + n00O10lO <= '0'; + n00O10Oi <= '0'; + n00O10Ol <= '0'; + n00O10OO <= '0'; + n00O1i0i <= '0'; + n00O1i0l <= '0'; + n00O1i0O <= '0'; + n00O1i1i <= '0'; + n00O1i1l <= '0'; + n00O1i1O <= '0'; + n00O1iii <= '0'; + n00O1iil <= '0'; + n00O1iiO <= '0'; + n00O1ili <= '0'; + n00O1ill <= '0'; + n00OOlil <= '0'; + n00OOliO <= '0'; + n00OOlli <= '0'; + n00OOlll <= '0'; + n00OOllO <= '0'; + n00OOlOi <= '0'; + n00OOlOl <= '0'; + n00OOlOO <= '0'; + n00OOO0i <= '0'; + n00OOO0l <= '0'; + n00OOO0O <= '0'; + n00OOO1i <= '0'; + n00OOO1l <= '0'; + n00OOO1O <= '0'; + n00OOOii <= '0'; + n00OOOil <= '0'; + n010000i <= '0'; + n010000l <= '0'; + n010000O <= '0'; + n010001i <= '0'; + n010001l <= '0'; + n010001O <= '0'; + n01000ii <= '0'; + n01000il <= '0'; + n01000iO <= '0'; + n01000li <= '0'; + n01000ll <= '0'; + n01000lO <= '0'; + n01000Oi <= '0'; + n01000Ol <= '0'; + n01000OO <= '0'; + n01001il <= '0'; + n01001iO <= '0'; + n01001li <= '0'; + n01001ll <= '0'; + n01001lO <= '0'; + n01001Oi <= '0'; + n01001Ol <= '0'; + n01001OO <= '0'; + n0100i0i <= '0'; + n0100i0l <= '0'; + n0100i0O <= '0'; + n0100i1i <= '0'; + n0100i1l <= '0'; + n0100i1O <= '0'; + n0100iii <= '0'; + n0100iil <= '0'; + n0100iiO <= '0'; + n0100ili <= '0'; + n0100ill <= '0'; + n0100ilO <= '0'; + n0100iOi <= '0'; + n0100iOl <= '0'; + n0100iOO <= '0'; + n0100l0l <= '0'; + n010ll0i <= '0'; + n010ll0l <= '0'; + n010ll0O <= '0'; + n010ll1O <= '0'; + n010lO0O <= '0'; + n010lOii <= '0'; + n010lOil <= '0'; + n010lOiO <= '0'; + n010lOli <= '0'; + n010lOll <= '0'; + n010lOlO <= '0'; + n010lOOi <= '0'; + n010lOOl <= '0'; + n010lOOO <= '0'; + n010O0lO <= '0'; + n010O0Oi <= '0'; + n010O0Ol <= '0'; + n010O0OO <= '0'; + n010Oi1i <= '0'; + n010Oi1l <= '0'; + n010OOil <= '0'; + n010OOiO <= '0'; + n010OOli <= '0'; + n010OOll <= '0'; + n010OOlO <= '0'; + n010OOOi <= '0'; + n010OOOl <= '0'; + n010OOOO <= '0'; + n011110i <= '0'; + n011110l <= '0'; + n011110O <= '0'; + n011111i <= '0'; + n011111l <= '0'; + n011111O <= '0'; + n01111ii <= '0'; + n01111il <= '0'; + n011i00l <= '0'; + n011i0Ol <= '0'; + n011i0OO <= '0'; + n011i1iO <= '0'; + n011i1li <= '0'; + n011i1ll <= '0'; + n011i1lO <= '0'; + n011ii1i <= '0'; + n011ii1l <= '0'; + n011iO1l <= '0'; + n011iOii <= '0'; + n011l0il <= '0'; + n011l0iO <= '0'; + n011l0li <= '0'; + n011l0ll <= '0'; + n011l0lO <= '0'; + n011l0Oi <= '0'; + n011l0Ol <= '0'; + n011l0OO <= '0'; + n011li0i <= '0'; + n011li0l <= '0'; + n011li0O <= '0'; + n011li1i <= '0'; + n011li1l <= '0'; + n011li1O <= '0'; + n011liii <= '0'; + n011liil <= '0'; + n011liiO <= '0'; + n011lili <= '0'; + n011lill <= '0'; + n011lilO <= '0'; + n011liOi <= '0'; + n011liOl <= '0'; + n011liOO <= '0'; + n011ll0i <= '0'; + n011ll0l <= '0'; + n011ll0O <= '0'; + n011ll1i <= '0'; + n011ll1l <= '0'; + n011ll1O <= '0'; + n011llii <= '0'; + n011llil <= '0'; + n011lliO <= '0'; + n011llli <= '0'; + n011llll <= '0'; + n011lllO <= '0'; + n011llOi <= '0'; + n011llOl <= '0'; + n011llOO <= '0'; + n011lO0i <= '0'; + n011lO0l <= '0'; + n011lO0O <= '0'; + n011lO1i <= '0'; + n011lO1l <= '0'; + n011lO1O <= '0'; + n011lOii <= '0'; + n011lOil <= '0'; + n01i101i <= '0'; + n01i101l <= '0'; + n01i101O <= '0'; + n01i110i <= '0'; + n01i110l <= '0'; + n01i110O <= '0'; + n01i111i <= '0'; + n01i111l <= '0'; + n01i111O <= '0'; + n01i11ii <= '0'; + n01i11il <= '0'; + n01i11iO <= '0'; + n01i11li <= '0'; + n01i11ll <= '0'; + n01i11lO <= '0'; + n01i11Oi <= '0'; + n01i11Ol <= '0'; + n01i11OO <= '0'; + n01i1OOl <= '0'; + n01iO0OO <= '0'; + n01iOi0i <= '0'; + n01iOi0l <= '0'; + n01iOi0O <= '0'; + n01iOi1i <= '0'; + n01iOi1l <= '0'; + n01iOi1O <= '0'; + n01iOiii <= '0'; + n01iOiil <= '0'; + n01iOiiO <= '0'; + n01iOili <= '0'; + n01iOill <= '0'; + n01iOilO <= '0'; + n01iOiOi <= '0'; + n01iOiOl <= '0'; + n01iOiOO <= '0'; + n01l000i <= '0'; + n01l001i <= '0'; + n01l001l <= '0'; + n01l001O <= '0'; + n01l010i <= '0'; + n01l010l <= '0'; + n01l010O <= '0'; + n01l01ii <= '0'; + n01l01il <= '0'; + n01l01iO <= '0'; + n01l01li <= '0'; + n01l01ll <= '0'; + n01l01lO <= '0'; + n01l01Oi <= '0'; + n01l01Ol <= '0'; + n01l01OO <= '0'; + n01l1Oil <= '0'; + n01lii1l <= '0'; + n01liiOi <= '0'; + n01liiOl <= '0'; + n01liiOO <= '0'; + n01lil0i <= '0'; + n01lil0l <= '0'; + n01lil0O <= '0'; + n01lil1i <= '0'; + n01lil1l <= '0'; + n01lil1O <= '0'; + n01lilii <= '0'; + n01lilil <= '0'; + n01liliO <= '0'; + n01lilli <= '0'; + n01lilll <= '0'; + n01lillO <= '0'; + n01lOlOi <= '0'; + n01lOlOl <= '0'; + n01lOlOO <= '0'; + n01lOO1i <= '0'; + n01lOOiO <= '0'; + n01O000i <= '0'; + n01O000l <= '0'; + n01O000O <= '0'; + n01O001i <= '0'; + n01O001l <= '0'; + n01O001O <= '0'; + n01O00ii <= '0'; + n01O00il <= '0'; + n01O00iO <= '0'; + n01O00li <= '0'; + n01O00ll <= '0'; + n01O00lO <= '0'; + n01O00Oi <= '0'; + n01O00Ol <= '0'; + n01O00OO <= '0'; + n01O010i <= '0'; + n01O010l <= '0'; + n01O010O <= '0'; + n01O011i <= '0'; + n01O011l <= '0'; + n01O011O <= '0'; + n01O01ii <= '0'; + n01O01il <= '0'; + n01O01iO <= '0'; + n01O01li <= '0'; + n01O01ll <= '0'; + n01O01lO <= '0'; + n01O01Oi <= '0'; + n01O01Ol <= '0'; + n01O01OO <= '0'; + n01O0i0i <= '0'; + n01O0i0l <= '0'; + n01O0i0O <= '0'; + n01O0i1i <= '0'; + n01O0i1l <= '0'; + n01O0i1O <= '0'; + n01O0iii <= '0'; + n01O0iil <= '0'; + n01O0iiO <= '0'; + n01O0ili <= '0'; + n01O0ill <= '0'; + n01O0ilO <= '0'; + n01O110i <= '0'; + n01O110l <= '0'; + n01O110O <= '0'; + n01O111O <= '0'; + n01O1i0O <= '0'; + n01O1ill <= '0'; + n01O1OlO <= '0'; + n01O1OOi <= '0'; + n01O1OOl <= '0'; + n01O1OOO <= '0'; + n01OlllO <= '0'; + n01OllOi <= '0'; + n01OllOl <= '0'; + n01OllOO <= '0'; + n01OlO0i <= '0'; + n01OlO0l <= '0'; + n01OlO0O <= '0'; + n01OlO1i <= '0'; + n01OlO1l <= '0'; + n01OlO1O <= '0'; + n01OlOii <= '0'; + n01OlOil <= '0'; + n01OlOiO <= '0'; + n01OlOli <= '0'; + n01OlOll <= '0'; + n01OlOlO <= '0'; + n01OlOOi <= '0'; + n01OlOOl <= '0'; + n01OlOOO <= '0'; + n01OO00i <= '0'; + n01OO01i <= '0'; + n01OO01l <= '0'; + n01OO01O <= '0'; + n01OO0iO <= '0'; + n01OO10i <= '0'; + n01OO10l <= '0'; + n01OO10O <= '0'; + n01OO11i <= '0'; + n01OO11l <= '0'; + n01OO11O <= '0'; + n01OO1ii <= '0'; + n01OO1il <= '0'; + n01OO1iO <= '0'; + n01OO1li <= '0'; + n01OO1ll <= '0'; + n01OO1lO <= '0'; + n01OO1Oi <= '0'; + n01OO1Ol <= '0'; + n01OO1OO <= '0'; + n0i0000l <= '0'; + n0i0000O <= '0'; + n0i000ii <= '0'; + n0i000il <= '0'; + n0i000iO <= '0'; + n0i000li <= '0'; + n0i000ll <= '0'; + n0i000lO <= '0'; + n0i000Oi <= '0'; + n0i000Ol <= '0'; + n0i000OO <= '0'; + n0i00i0i <= '0'; + n0i00i0l <= '0'; + n0i00i0O <= '0'; + n0i00i1i <= '0'; + n0i00i1l <= '0'; + n0i00i1O <= '0'; + n0i00iii <= '0'; + n0i00iil <= '0'; + n0i00iiO <= '0'; + n0i00ili <= '0'; + n0i00ill <= '0'; + n0i00ilO <= '0'; + n0i00iOi <= '0'; + n0i00iOl <= '0'; + n0i00iOO <= '0'; + n0i00l0i <= '0'; + n0i00l0l <= '0'; + n0i00l0O <= '0'; + n0i00l1i <= '0'; + n0i00l1l <= '0'; + n0i00l1O <= '0'; + n0i00lii <= '0'; + n0i00lil <= '0'; + n0i00liO <= '0'; + n0i00lli <= '0'; + n0i00lll <= '0'; + n0i00llO <= '0'; + n0i00lOi <= '0'; + n0i00lOl <= '0'; + n0i00lOO <= '0'; + n0i00O0i <= '0'; + n0i00O0l <= '0'; + n0i00O1i <= '0'; + n0i00O1l <= '0'; + n0i00O1O <= '0'; + n0i0101l <= '0'; + n0i010ll <= '0'; + n0i010lO <= '0'; + n0i010Oi <= '0'; + n0i010Ol <= '0'; + n0i0110O <= '0'; + n0i011ii <= '0'; + n0i011il <= '0'; + n0i011iO <= '0'; + n0i01lOl <= '0'; + n0i01O0i <= '0'; + n0i0O00i <= '0'; + n0i0O00l <= '0'; + n0i0O00O <= '0'; + n0i0O01i <= '0'; + n0i0O01l <= '0'; + n0i0O01O <= '0'; + n0i0O0ii <= '0'; + n0i0O0il <= '0'; + n0i0O0iO <= '0'; + n0i0O0li <= '0'; + n0i0O0ll <= '0'; + n0i0O0lO <= '0'; + n0i0O0Oi <= '0'; + n0i0O0Ol <= '0'; + n0i0O0OO <= '0'; + n0i0O10l <= '0'; + n0i0O10O <= '0'; + n0i0O1ii <= '0'; + n0i0O1il <= '0'; + n0i0O1iO <= '0'; + n0i0O1li <= '0'; + n0i0O1ll <= '0'; + n0i0O1lO <= '0'; + n0i0O1Oi <= '0'; + n0i0O1Ol <= '0'; + n0i0O1OO <= '0'; + n0i0Oi0i <= '0'; + n0i0Oi0l <= '0'; + n0i0Oi0O <= '0'; + n0i0Oi1i <= '0'; + n0i0Oi1l <= '0'; + n0i0Oi1O <= '0'; + n0i0Oiii <= '0'; + n0i0Oiil <= '0'; + n0i0OiiO <= '0'; + n0i0Oili <= '0'; + n0i0Oill <= '0'; + n0i0OilO <= '0'; + n0i0Ol1l <= '0'; + n0i1001i <= '0'; + n0i100lO <= '0'; + n0i100Oi <= '0'; + n0i100Ol <= '0'; + n0i100OO <= '0'; + n0i10i0i <= '0'; + n0i10i0l <= '0'; + n0i10i0O <= '0'; + n0i10i1i <= '0'; + n0i10i1l <= '0'; + n0i10i1O <= '0'; + n0i10iii <= '0'; + n0i10iil <= '0'; + n0i10iiO <= '0'; + n0i10ili <= '0'; + n0i10ill <= '0'; + n0i10ilO <= '0'; + n0i1illi <= '0'; + n0i1iO0O <= '0'; + n0i1iOii <= '0'; + n0i1iOil <= '0'; + n0i1iOiO <= '0'; + n0i1iOli <= '0'; + n0i1iOll <= '0'; + n0i1iOlO <= '0'; + n0i1iOOi <= '0'; + n0i1iOOl <= '0'; + n0i1iOOO <= '0'; + n0i1l10i <= '0'; + n0i1l10l <= '0'; + n0i1l11i <= '0'; + n0i1l11l <= '0'; + n0i1l11O <= '0'; + n0ii0iOO <= '0'; + n0ii0l1i <= '0'; + n0ii0l1l <= '0'; + n0ii0l1O <= '0'; + n0ii0O0i <= '0'; + n0ii0O0l <= '0'; + n0ii0O0O <= '0'; + n0ii0O1O <= '0'; + n0ii0Oii <= '0'; + n0ii0Oil <= '0'; + n0ii0OiO <= '0'; + n0ii0Oli <= '0'; + n0ii0Oll <= '0'; + n0ii0OlO <= '0'; + n0iii0iO <= '0'; + n0iii0li <= '0'; + n0iii0ll <= '0'; + n0iii0lO <= '0'; + n0iii0Oi <= '0'; + n0iii0Ol <= '0'; + n0iiiO0l <= '0'; + n0iiiO0O <= '0'; + n0iiiOii <= '0'; + n0iiiOil <= '0'; + n0iiiOiO <= '0'; + n0iiiOli <= '0'; + n0iiiOll <= '0'; + n0iiiOlO <= '0'; + n0iiiOOi <= '0'; + n0iiiOOl <= '0'; + n0iiiOOO <= '0'; + n0iil10i <= '0'; + n0iil10l <= '0'; + n0iil10O <= '0'; + n0iil11i <= '0'; + n0iil11l <= '0'; + n0iil11O <= '0'; + n0iil1ii <= '0'; + n0iil1il <= '0'; + n0iil1iO <= '0'; + n0iil1li <= '0'; + n0iil1ll <= '0'; + n0iil1lO <= '0'; + n0iil1Oi <= '0'; + n0iil1Ol <= '0'; + n0iil1OO <= '0'; + n0iilOll <= '0'; + n0ili0lO <= '0'; + n0ili0Oi <= '0'; + n0ili0Ol <= '0'; + n0ili0OO <= '0'; + n0ilii0i <= '0'; + n0ilii0l <= '0'; + n0ilii0O <= '0'; + n0ilii1i <= '0'; + n0ilii1l <= '0'; + n0ilii1O <= '0'; + n0iliiii <= '0'; + n0iliiil <= '0'; + n0iliiiO <= '0'; + n0iliili <= '0'; + n0iliill <= '0'; + n0iliilO <= '0'; + n0illO0l <= '0'; + n0ilO01i <= '0'; + n0ilO10i <= '0'; + n0ilO10l <= '0'; + n0ilO10O <= '0'; + n0ilO11i <= '0'; + n0ilO11l <= '0'; + n0ilO11O <= '0'; + n0ilO1ii <= '0'; + n0ilO1il <= '0'; + n0ilO1iO <= '0'; + n0ilO1li <= '0'; + n0ilO1ll <= '0'; + n0ilO1lO <= '0'; + n0ilO1Oi <= '0'; + n0ilO1Ol <= '0'; + n0ilO1OO <= '0'; + n0iO10Ol <= '0'; + n0iO1ili <= '0'; + n0iO1ill <= '0'; + n0iO1ilO <= '0'; + n0iO1iOi <= '0'; + n0iO1iOl <= '0'; + n0iO1iOO <= '0'; + n0iO1l0i <= '0'; + n0iO1l0l <= '0'; + n0iO1l0O <= '0'; + n0iO1l1i <= '0'; + n0iO1l1l <= '0'; + n0iO1l1O <= '0'; + n0iO1lii <= '0'; + n0iO1lil <= '0'; + n0iO1liO <= '0'; + n0iOilli <= '0'; + n0iOilll <= '0'; + n0iOillO <= '0'; + n0iOilOi <= '0'; + n0iOiO0O <= '0'; + n0iOiOOO <= '0'; + n0iOl11i <= '0'; + n0iOl11l <= '0'; + n0iOl11O <= '0'; + n0iOli1O <= '0'; + n0iOliil <= '0'; + n0iOlOiO <= '0'; + n0iOlOli <= '0'; + n0iOlOll <= '0'; + n0iOlOlO <= '0'; + n0iOlOOi <= '0'; + n0iOlOOl <= '0'; + n0iOlOOO <= '0'; + n0iOO00i <= '0'; + n0iOO00l <= '0'; + n0iOO00O <= '0'; + n0iOO01i <= '0'; + n0iOO01l <= '0'; + n0iOO01O <= '0'; + n0iOO0ii <= '0'; + n0iOO0il <= '0'; + n0iOO0iO <= '0'; + n0iOO0li <= '0'; + n0iOO0ll <= '0'; + n0iOO0lO <= '0'; + n0iOO0Oi <= '0'; + n0iOO0Ol <= '0'; + n0iOO0OO <= '0'; + n0iOO10i <= '0'; + n0iOO10l <= '0'; + n0iOO10O <= '0'; + n0iOO11i <= '0'; + n0iOO11l <= '0'; + n0iOO11O <= '0'; + n0iOO1ii <= '0'; + n0iOO1il <= '0'; + n0iOO1iO <= '0'; + n0iOO1li <= '0'; + n0iOO1ll <= '0'; + n0iOO1lO <= '0'; + n0iOO1Oi <= '0'; + n0iOO1Ol <= '0'; + n0iOO1OO <= '0'; + n0iOOi0i <= '0'; + n0iOOi0l <= '0'; + n0iOOi0O <= '0'; + n0iOOi1i <= '0'; + n0iOOi1l <= '0'; + n0iOOi1O <= '0'; + n0iOOiii <= '0'; + n0iOOiil <= '0'; + n0iOOiiO <= '0'; + n0l00iOO <= '0'; + n0l0111i <= '0'; + n0l0111l <= '0'; + n0l0111O <= '0'; + n0l01iiO <= '0'; + n0l01ili <= '0'; + n0l01ill <= '0'; + n0l01ilO <= '0'; + n0l01iOi <= '0'; + n0l01iOl <= '0'; + n0l01iOO <= '0'; + n0l01l0i <= '0'; + n0l01l0l <= '0'; + n0l01l0O <= '0'; + n0l01l1i <= '0'; + n0l01l1l <= '0'; + n0l01l1O <= '0'; + n0l01lii <= '0'; + n0l01lil <= '0'; + n0l01liO <= '0'; + n0l01lli <= '0'; + n0l01lll <= '0'; + n0l01llO <= '0'; + n0l01lOi <= '0'; + n0l01lOl <= '0'; + n0l01lOO <= '0'; + n0l01O0i <= '0'; + n0l01O1i <= '0'; + n0l01O1l <= '0'; + n0l01O1O <= '0'; + n0l10liO <= '0'; + n0l10lli <= '0'; + n0l10lll <= '0'; + n0l10llO <= '0'; + n0l10lOi <= '0'; + n0l10lOl <= '0'; + n0l10lOO <= '0'; + n0l10O0i <= '0'; + n0l10O0l <= '0'; + n0l10O0O <= '0'; + n0l10O1i <= '0'; + n0l10O1l <= '0'; + n0l10O1O <= '0'; + n0l10Oii <= '0'; + n0l10Oil <= '0'; + n0l10OiO <= '0'; + n0l10Oli <= '0'; + n0l10Oll <= '0'; + n0l10OlO <= '0'; + n0l10OOi <= '0'; + n0l10OOl <= '0'; + n0l10OOO <= '0'; + n0l1i00O <= '0'; + n0l1i01i <= '0'; + n0l1i10i <= '0'; + n0l1i10l <= '0'; + n0l1i10O <= '0'; + n0l1i11i <= '0'; + n0l1i11l <= '0'; + n0l1i11O <= '0'; + n0l1i1ii <= '0'; + n0l1i1il <= '0'; + n0l1i1iO <= '0'; + n0l1i1li <= '0'; + n0l1i1ll <= '0'; + n0l1i1lO <= '0'; + n0l1i1Oi <= '0'; + n0l1i1Ol <= '0'; + n0l1i1OO <= '0'; + n0l1O00i <= '0'; + n0l1O00l <= '0'; + n0l1O00O <= '0'; + n0l1O0ii <= '0'; + n0l1Oiii <= '0'; + n0l1Oiil <= '0'; + n0l1OiiO <= '0'; + n0l1Oili <= '0'; + n0l1Oill <= '0'; + n0l1OilO <= '0'; + n0l1OiOi <= '0'; + n0l1OiOl <= '0'; + n0l1OiOO <= '0'; + n0l1Ol1i <= '0'; + n0l1OOOi <= '0'; + n0l1OOOl <= '0'; + n0l1OOOO <= '0'; + n0li0iiO <= '0'; + n0li0l0l <= '0'; + n0li0l0O <= '0'; + n0li0lii <= '0'; + n0li0lil <= '0'; + n0li0liO <= '0'; + n0li0lli <= '0'; + n0li0lll <= '0'; + n0li0llO <= '0'; + n0li0lOi <= '0'; + n0li0lOl <= '0'; + n0li0lOO <= '0'; + n0li0O0i <= '0'; + n0li0O0l <= '0'; + n0li0O1i <= '0'; + n0li0O1l <= '0'; + n0li0O1O <= '0'; + n0li101i <= '0'; + n0li110i <= '0'; + n0li110l <= '0'; + n0li110O <= '0'; + n0li111i <= '0'; + n0li111l <= '0'; + n0li111O <= '0'; + n0li11ii <= '0'; + n0li11il <= '0'; + n0li11iO <= '0'; + n0li11li <= '0'; + n0li11ll <= '0'; + n0li11lO <= '0'; + n0li11Oi <= '0'; + n0li11Ol <= '0'; + n0li11OO <= '0'; + n0lil00i <= '0'; + n0lil00l <= '0'; + n0lil00O <= '0'; + n0lil01i <= '0'; + n0lil01l <= '0'; + n0lil01O <= '0'; + n0lil0ii <= '0'; + n0lil0il <= '0'; + n0lil0iO <= '0'; + n0lil0li <= '0'; + n0lil0ll <= '0'; + n0lil0lO <= '0'; + n0lil0Oi <= '0'; + n0lil11O <= '0'; + n0lil1Ol <= '0'; + n0lil1OO <= '0'; + n0ll01ii <= '0'; + n0ll01lO <= '0'; + n0ll0iOi <= '0'; + n0ll0iOl <= '0'; + n0ll0iOO <= '0'; + n0ll0l0i <= '0'; + n0ll0l0l <= '0'; + n0ll0l0O <= '0'; + n0ll0l1i <= '0'; + n0ll0l1l <= '0'; + n0ll0l1O <= '0'; + n0ll0lii <= '0'; + n0ll0lil <= '0'; + n0ll0liO <= '0'; + n0ll0lli <= '0'; + n0ll0lll <= '0'; + n0ll0llO <= '0'; + n0ll0lOi <= '0'; + n0ll0lOl <= '0'; + n0ll0lOO <= '0'; + n0ll0O0i <= '0'; + n0ll0O0l <= '0'; + n0ll0O0O <= '0'; + n0ll0O1i <= '0'; + n0ll0O1l <= '0'; + n0ll0O1O <= '0'; + n0ll0Oii <= '0'; + n0ll0Oil <= '0'; + n0ll0OiO <= '0'; + n0ll0Oli <= '0'; + n0ll0Oll <= '0'; + n0ll0OlO <= '0'; + n0ll0OOi <= '0'; + n0ll0OOl <= '0'; + n0ll0OOO <= '0'; + n0ll10Ol <= '0'; + n0ll10OO <= '0'; + n0ll1i1i <= '0'; + n0ll1i1l <= '0'; + n0ll1ili <= '0'; + n0ll1l0i <= '0'; + n0ll1l0l <= '0'; + n0ll1l0O <= '0'; + n0ll1lii <= '0'; + n0lli10i <= '0'; + n0lli10l <= '0'; + n0lli10O <= '0'; + n0lli11i <= '0'; + n0lli11l <= '0'; + n0lli11O <= '0'; + n0lli1ii <= '0'; + n0lli1il <= '0'; + n0lli1iO <= '0'; + n0lli1li <= '0'; + n0lli1ll <= '0'; + n0lli1lO <= '0'; + n0lli1Oi <= '0'; + n0llO0Oi <= '0'; + n0llO0Ol <= '0'; + n0llO0OO <= '0'; + n0llOi0i <= '0'; + n0llOi0l <= '0'; + n0llOi0O <= '0'; + n0llOi1i <= '0'; + n0llOi1l <= '0'; + n0llOi1O <= '0'; + n0llOiii <= '0'; + n0llOiil <= '0'; + n0llOiiO <= '0'; + n0llOili <= '0'; + n0llOill <= '0'; + n0llOilO <= '0'; + n0llOiOi <= '0'; + n0llOiOl <= '0'; + n0llOiOO <= '0'; + n0llOl0i <= '0'; + n0llOl0l <= '0'; + n0llOl0O <= '0'; + n0llOl1i <= '0'; + n0llOl1l <= '0'; + n0llOl1O <= '0'; + n0llOlii <= '0'; + n0llOlil <= '0'; + n0llOliO <= '0'; + n0llOlli <= '0'; + n0llOlll <= '0'; + n0llOllO <= '0'; + n0llOlOi <= '0'; + n0llOlOl <= '0'; + n0llOlOO <= '0'; + n0llOO0i <= '0'; + n0llOO0l <= '0'; + n0llOO1i <= '0'; + n0llOO1l <= '0'; + n0llOO1O <= '0'; + n0llOOli <= '0'; + n0lO0Oil <= '0'; + n0lO0OiO <= '0'; + n0lO0Oli <= '0'; + n0lO0Oll <= '0'; + n0lOi00i <= '0'; + n0lOi00l <= '0'; + n0lOi01i <= '0'; + n0lOi01l <= '0'; + n0lOi01O <= '0'; + n0lOi1ll <= '0'; + n0lOi1lO <= '0'; + n0lOi1Oi <= '0'; + n0lOi1Ol <= '0'; + n0lOi1OO <= '0'; + n0lOil0i <= '0'; + n0lOil0l <= '0'; + n0lOil0O <= '0'; + n0lOil1l <= '0'; + n0lOil1O <= '0'; + n0lOilii <= '0'; + n0lOl00i <= '0'; + n0lOl00l <= '0'; + n0lOl00O <= '0'; + n0lOl01i <= '0'; + n0lOl01l <= '0'; + n0lOl01O <= '0'; + n0lOl0ii <= '0'; + n0lOl0il <= '0'; + n0lOl0iO <= '0'; + n0lOl0li <= '0'; + n0lOl0ll <= '0'; + n0lOl0lO <= '0'; + n0lOl0Oi <= '0'; + n0lOl0Ol <= '0'; + n0lOl0OO <= '0'; + n0lOl1Oi <= '0'; + n0lOl1Ol <= '0'; + n0lOl1OO <= '0'; + n0lOli0i <= '0'; + n0lOli0l <= '0'; + n0lOli0O <= '0'; + n0lOli1i <= '0'; + n0lOli1l <= '0'; + n0lOli1O <= '0'; + n0lOliii <= '0'; + n0lOliil <= '0'; + n0lOO00i <= '0'; + n0O0011i <= '0'; + n0O0011l <= '0'; + n0O01lii <= '0'; + n0O01O0i <= '0'; + n0O01O0l <= '0'; + n0O01O0O <= '0'; + n0O01O1O <= '0'; + n0O01Oii <= '0'; + n0O01Oil <= '0'; + n0O01OiO <= '0'; + n0O01Oli <= '0'; + n0O01Oll <= '0'; + n0O01OlO <= '0'; + n0O01OOi <= '0'; + n0O01OOl <= '0'; + n0O01OOO <= '0'; + n0O0l0il <= '0'; + n0O0l0iO <= '0'; + n0O0l0li <= '0'; + n0O0l0ll <= '0'; + n0O0l10i <= '0'; + n0O0l10l <= '0'; + n0O0l10O <= '0'; + n0O0l11O <= '0'; + n0O0l1Ol <= '0'; + n0O0llll <= '0'; + n0O0lO1i <= '0'; + n0O0O00i <= '0'; + n0O0O00l <= '0'; + n0O0O00O <= '0'; + n0O0O01l <= '0'; + n0O0O01O <= '0'; + n0O0O0ii <= '0'; + n0O0O0il <= '0'; + n0O0O0iO <= '0'; + n0O0O0li <= '0'; + n0O0O0ll <= '0'; + n0O0O0lO <= '0'; + n0O0O0Oi <= '0'; + n0O0O0Ol <= '0'; + n0O0O0OO <= '0'; + n0O0Oi0i <= '0'; + n0O0Oi0l <= '0'; + n0O0Oi0O <= '0'; + n0O0Oi1i <= '0'; + n0O0Oi1l <= '0'; + n0O0Oi1O <= '0'; + n0O0Oiii <= '0'; + n0O0Oiil <= '0'; + n0O0OiiO <= '0'; + n0O0Oili <= '0'; + n0O0Oill <= '0'; + n0O0OilO <= '0'; + n0O0OiOi <= '0'; + n0O0OiOl <= '0'; + n0O0OiOO <= '0'; + n0O0Ol0i <= '0'; + n0O0Ol0l <= '0'; + n0O0Ol0O <= '0'; + n0O0Ol1i <= '0'; + n0O0Ol1l <= '0'; + n0O0Ol1O <= '0'; + n0O0Olii <= '0'; + n0O0Olil <= '0'; + n0O0OliO <= '0'; + n0O0Olli <= '0'; + n0O0Olll <= '0'; + n0O0OllO <= '0'; + n0O0OlOi <= '0'; + n0O0OlOl <= '0'; + n0O0OlOO <= '0'; + n0O0OO1i <= '0'; + n0O0OO1l <= '0'; + n0O1il0l <= '0'; + n0O1il0O <= '0'; + n0O1ilii <= '0'; + n0O1ilil <= '0'; + n0O1iliO <= '0'; + n0O1illi <= '0'; + n0O1illl <= '0'; + n0O1illO <= '0'; + n0O1ilOi <= '0'; + n0O1ilOl <= '0'; + n0O1ilOO <= '0'; + n0O1iO0i <= '0'; + n0O1iO0l <= '0'; + n0O1iO1i <= '0'; + n0O1iO1l <= '0'; + n0O1iO1O <= '0'; + n0O1O0iO <= '0'; + n0O1O0li <= '0'; + n0O1O0ll <= '0'; + n0O1O0lO <= '0'; + n0O1O0Oi <= '0'; + n0O1O0Ol <= '0'; + n0O1O0OO <= '0'; + n0O1O1Oi <= '0'; + n0O1Oi0i <= '0'; + n0O1Oi0l <= '0'; + n0O1Oi0O <= '0'; + n0O1Oi1i <= '0'; + n0O1Oi1l <= '0'; + n0O1Oi1O <= '0'; + n0O1Oiii <= '0'; + n0O1Oiil <= '0'; + n0O1OiiO <= '0'; + n0Oii00i <= '0'; + n0Oii00l <= '0'; + n0Oii00O <= '0'; + n0Oii01i <= '0'; + n0Oii01l <= '0'; + n0Oii01O <= '0'; + n0Oii0ii <= '0'; + n0Oii0il <= '0'; + n0Oii0iO <= '0'; + n0Oii0li <= '0'; + n0Oii0ll <= '0'; + n0Oii0lO <= '0'; + n0Oii0Oi <= '0'; + n0Oii0Ol <= '0'; + n0Oii0OO <= '0'; + n0Oii10i <= '0'; + n0Oii10l <= '0'; + n0Oii10O <= '0'; + n0Oii11l <= '0'; + n0Oii11O <= '0'; + n0Oii1ii <= '0'; + n0Oii1il <= '0'; + n0Oii1iO <= '0'; + n0Oii1li <= '0'; + n0Oii1ll <= '0'; + n0Oii1lO <= '0'; + n0Oii1Oi <= '0'; + n0Oii1Ol <= '0'; + n0Oii1OO <= '0'; + n0Oiii0i <= '0'; + n0Oiii0l <= '0'; + n0Oiii0O <= '0'; + n0Oiii1i <= '0'; + n0Oiii1l <= '0'; + n0Oiii1O <= '0'; + n0Oiiiii <= '0'; + n0Oiiiil <= '0'; + n0OiiiiO <= '0'; + n0OiiiOl <= '0'; + n0OiOilO <= '0'; + n0OiOiOi <= '0'; + n0OiOiOl <= '0'; + n0OiOiOO <= '0'; + n0OiOlOO <= '0'; + n0OiOO0i <= '0'; + n0OiOO0l <= '0'; + n0OiOO0O <= '0'; + n0OiOO1i <= '0'; + n0OiOO1l <= '0'; + n0OiOO1O <= '0'; + n0OiOOii <= '0'; + n0OiOOil <= '0'; + n0OiOOiO <= '0'; + n0Ol010i <= '0'; + n0Ol010l <= '0'; + n0Ol010O <= '0'; + n0Ol011i <= '0'; + n0Ol011l <= '0'; + n0Ol011O <= '0'; + n0Ol01ii <= '0'; + n0Ol01il <= '0'; + n0Ol01iO <= '0'; + n0Ol01li <= '0'; + n0Ol01ll <= '0'; + n0Ol01lO <= '0'; + n0Ol0Oil <= '0'; + n0Ol100O <= '0'; + n0Ol10ii <= '0'; + n0Ol10il <= '0'; + n0Ol10iO <= '0'; + n0Ol10li <= '0'; + n0Ol10ll <= '0'; + n0Ol1O0i <= '0'; + n0Ol1O0l <= '0'; + n0Ol1O0O <= '0'; + n0Ol1O1l <= '0'; + n0Ol1O1O <= '0'; + n0Ol1Oii <= '0'; + n0Ol1Oil <= '0'; + n0Ol1OiO <= '0'; + n0Ol1Oli <= '0'; + n0Ol1Oll <= '0'; + n0Ol1OlO <= '0'; + n0Ol1OOi <= '0'; + n0Ol1OOl <= '0'; + n0Ol1OOO <= '0'; + n0OO0iii <= '0'; + n0OO0iil <= '0'; + n0OO0iiO <= '0'; + n0OO0ili <= '0'; + n0OO0ill <= '0'; + n0OO0ilO <= '0'; + n0OO0iOi <= '0'; + n0OO0iOl <= '0'; + n0OO0iOO <= '0'; + n0OO0OOi <= '0'; + n0OO0OOl <= '0'; + n0OO0OOO <= '0'; + n0OO10iO <= '0'; + n0OO10li <= '0'; + n0OO10ll <= '0'; + n0OO10lO <= '0'; + n0OO10Oi <= '0'; + n0OO10Ol <= '0'; + n0OO10OO <= '0'; + n0OO1i0i <= '0'; + n0OO1i0l <= '0'; + n0OO1i0O <= '0'; + n0OO1i1i <= '0'; + n0OO1i1l <= '0'; + n0OO1i1O <= '0'; + n0OO1iii <= '0'; + n0OO1iil <= '0'; + n0OO1iiO <= '0'; + n0OOi10i <= '0'; + n0OOi10l <= '0'; + n0OOi10O <= '0'; + n0OOi11i <= '0'; + n0OOi11l <= '0'; + n0OOi11O <= '0'; + n0OOi1ii <= '0'; + n0OOiiiO <= '0'; + n0OOiili <= '0'; + n0OOiill <= '0'; + n0OOiilO <= '0'; + n0OOiiOi <= '0'; + n0OOiiOl <= '0'; + n0OOiiOO <= '0'; + n0OOil1i <= '0'; + n0OOil1l <= '0'; + n0OOl10i <= '0'; + n0OOl10l <= '0'; + n0OOl10O <= '0'; + n0OOl1ii <= '0'; + n0OOl1il <= '0'; + n0OOl1iO <= '0'; + n0OOl1li <= '0'; + n0OOl1ll <= '0'; + n0OOl1lO <= '0'; + n0OOliOl <= '0'; + n0OOliOO <= '0'; + n0OOll0i <= '0'; + n0OOll0l <= '0'; + n0OOll0O <= '0'; + n0OOll1i <= '0'; + n0OOll1l <= '0'; + n0OOll1O <= '0'; + n0OOllii <= '0'; + n0OOO01i <= '0'; + n0OOO01l <= '0'; + n0OOO1iO <= '0'; + n0OOO1li <= '0'; + n0OOO1ll <= '0'; + n0OOO1lO <= '0'; + n0OOO1Oi <= '0'; + n0OOO1Ol <= '0'; + n0OOO1OO <= '0'; + n0OOOl0i <= '0'; + n0OOOl0l <= '0'; + n0OOOl0O <= '0'; + n0OOOlii <= '0'; + n0OOOlil <= '0'; + n0OOOliO <= '0'; + n0OOOlli <= '0'; + n0OOOlll <= '0'; + n0OOOllO <= '0'; + n1101iiO <= '0'; + n1101ili <= '0'; + n1101ill <= '0'; + n1101ilO <= '0'; + n1101iOi <= '0'; + n1101iOl <= '0'; + n1101iOO <= '0'; + n1101l0i <= '0'; + n1101l0l <= '0'; + n1101l0O <= '0'; + n1101l1i <= '0'; + n1101l1l <= '0'; + n1101l1O <= '0'; + n1101lii <= '0'; + n1101lil <= '0'; + n1101liO <= '0'; + n1101lli <= '0'; + n110OOii <= '0'; + n110OOil <= '0'; + n110OOiO <= '0'; + n110OOli <= '0'; + n110OOll <= '0'; + n110OOlO <= '0'; + n110OOOi <= '0'; + n110OOOl <= '0'; + n110OOOO <= '0'; + n1110O0l <= '0'; + n1110O0O <= '0'; + n1110Oii <= '0'; + n1110Oil <= '0'; + n1110OiO <= '0'; + n1110Oli <= '0'; + n1110Oll <= '0'; + n1110OlO <= '0'; + n1110OOi <= '0'; + n1110OOl <= '0'; + n1110OOO <= '0'; + n111i00i <= '0'; + n111i00l <= '0'; + n111i00O <= '0'; + n111i01i <= '0'; + n111i01l <= '0'; + n111i01O <= '0'; + n111i0ii <= '0'; + n111i0il <= '0'; + n111i10i <= '0'; + n111i10l <= '0'; + n111i10O <= '0'; + n111i11i <= '0'; + n111i11l <= '0'; + n111i11O <= '0'; + n111i1ii <= '0'; + n111i1il <= '0'; + n111i1iO <= '0'; + n111i1li <= '0'; + n111i1ll <= '0'; + n111i1lO <= '0'; + n111i1Oi <= '0'; + n111i1Ol <= '0'; + n111i1OO <= '0'; + n11i111i <= '0'; + n11i111l <= '0'; + n11i111O <= '0'; + n11l0Oii <= '0'; + n11l0Oil <= '0'; + n11l0OiO <= '0'; + n11l0Oli <= '0'; + n11l0Oll <= '0'; + n11l0OlO <= '0'; + n11l0OOi <= '0'; + n11l0OOl <= '0'; + n11l0OOO <= '0'; + n11li10i <= '0'; + n11li10l <= '0'; + n11li10O <= '0'; + n11li11i <= '0'; + n11li11l <= '0'; + n11li11O <= '0'; + n11li1ii <= '0'; + n11li1il <= '0'; + n11li1li <= '0'; + n11O000i <= '0'; + n11O000l <= '0'; + n11O000O <= '0'; + n11O001i <= '0'; + n11O001l <= '0'; + n11O001O <= '0'; + n11O00ii <= '0'; + n11O00il <= '0'; + n11O00iO <= '0'; + n11O00li <= '0'; + n11O00ll <= '0'; + n11O00lO <= '0'; + n11O00Oi <= '0'; + n11O00Ol <= '0'; + n11O00OO <= '0'; + n11O010i <= '0'; + n11O010O <= '0'; + n11O011i <= '0'; + n11O011l <= '0'; + n11O011O <= '0'; + n11O01ii <= '0'; + n11O01il <= '0'; + n11O01iO <= '0'; + n11O01li <= '0'; + n11O01ll <= '0'; + n11O01lO <= '0'; + n11O01Oi <= '0'; + n11O01Ol <= '0'; + n11O01OO <= '0'; + n11O0i0i <= '0'; + n11O0i0O <= '0'; + n11O0i1i <= '0'; + n11O0i1O <= '0'; + n11O0iil <= '0'; + n11O0ili <= '0'; + n11O0ill <= '0'; + n11O0ilO <= '0'; + n11O0iOi <= '0'; + n11O0iOl <= '0'; + n11O0iOO <= '0'; + n11O0l0i <= '0'; + n11O0l0l <= '0'; + n11O0l0O <= '0'; + n11O0l1i <= '0'; + n11O0l1l <= '0'; + n11O0l1O <= '0'; + n11O0lii <= '0'; + n11O0lil <= '0'; + n11O0liO <= '0'; + n11O0lli <= '0'; + n11O0lll <= '0'; + n11O0llO <= '0'; + n11O0lOi <= '0'; + n11O0lOl <= '0'; + n11O0lOO <= '0'; + n11O0O0i <= '0'; + n11O0O0l <= '0'; + n11O0O0O <= '0'; + n11O0O1i <= '0'; + n11O0O1l <= '0'; + n11O0O1O <= '0'; + n11O0Oii <= '0'; + n11O0OiO <= '0'; + n11O0Oli <= '0'; + n11O0Oll <= '0'; + n11O0OlO <= '0'; + n11O0OOi <= '0'; + n11O0OOl <= '0'; + n11O0OOO <= '0'; + n11O1l0O <= '0'; + n11O1lii <= '0'; + n11O1lil <= '0'; + n11O1O0i <= '0'; + n11O1O0l <= '0'; + n11O1O0O <= '0'; + n11O1O1O <= '0'; + n11O1Oii <= '0'; + n11O1Oil <= '0'; + n11O1OiO <= '0'; + n11O1Oli <= '0'; + n11O1Oll <= '0'; + n11O1OlO <= '0'; + n11O1OOi <= '0'; + n11O1OOl <= '0'; + n11O1OOO <= '0'; + n11Oi00i <= '0'; + n11Oi00l <= '0'; + n11Oi01i <= '0'; + n11Oi01l <= '0'; + n11Oi01O <= '0'; + n11Oi0ii <= '0'; + n11Oi10i <= '0'; + n11Oi10l <= '0'; + n11Oi10O <= '0'; + n11Oi11i <= '0'; + n11Oi11l <= '0'; + n11Oi11O <= '0'; + n11Oi1ii <= '0'; + n11Oi1il <= '0'; + n11Oi1iO <= '0'; + n11Oi1li <= '0'; + n11Oi1ll <= '0'; + n11Oi1lO <= '0'; + n11Oi1Oi <= '0'; + n11Oi1Ol <= '0'; + n11Oi1OO <= '0'; + n1iiii1i <= '0'; + n1iili0l <= '0'; + n1iili0O <= '0'; + n1iiliii <= '0'; + n1iiliil <= '0'; + n1iiliiO <= '0'; + n1iilili <= '0'; + n1iilill <= '0'; + n1iililO <= '0'; + n1iiliOi <= '0'; + n1iiliOl <= '0'; + n1iiliOO <= '0'; + n1iill0i <= '0'; + n1iill0l <= '0'; + n1iill0O <= '0'; + n1iill1i <= '0'; + n1iill1l <= '0'; + n1iill1O <= '0'; + n1iillii <= '0'; + n1iillil <= '0'; + n1iilliO <= '0'; + n1iillli <= '0'; + n1iiOlii <= '0'; + n1iiOlil <= '0'; + n1iiOliO <= '0'; + n1iiOlli <= '0'; + n1iiOlll <= '0'; + n1il100i <= '0'; + n1il100l <= '0'; + n1il100O <= '0'; + n1il101i <= '0'; + n1il101l <= '0'; + n1il101O <= '0'; + n1il10ii <= '0'; + n1il10il <= '0'; + n1il10iO <= '0'; + n1il10li <= '0'; + n1il10ll <= '0'; + n1il10lO <= '0'; + n1il10Oi <= '0'; + n1il10Ol <= '0'; + n1il10OO <= '0'; + n1il11il <= '0'; + n1il11li <= '0'; + n1il11ll <= '0'; + n1il11lO <= '0'; + n1il11Oi <= '0'; + n1il11OO <= '0'; + n1il1i0i <= '0'; + n1il1i0l <= '0'; + n1il1i1i <= '0'; + n1il1i1l <= '0'; + n1il1i1O <= '0'; + n1illOiO <= '0'; + n1ilOO0i <= '0'; + n1ilOO0l <= '0'; + n1ilOO0O <= '0'; + n1ilOO1i <= '0'; + n1ilOO1l <= '0'; + n1ilOO1O <= '0'; + n1ilOOii <= '0'; + n1ilOOil <= '0'; + n1ilOOiO <= '0'; + n1ilOOli <= '0'; + n1ilOOll <= '0'; + n1ilOOlO <= '0'; + n1ilOOOi <= '0'; + n1ilOOOl <= '0'; + n1ilOOOO <= '0'; + n1iO001i <= '0'; + n1iO001l <= '0'; + n1iO01Oi <= '0'; + n1iO01Ol <= '0'; + n1iO01OO <= '0'; + n1iO0ili <= '0'; + n1iO0ill <= '0'; + n1iO0ilO <= '0'; + n1iO0iOi <= '0'; + n1iO0iOl <= '0'; + n1iO0iOO <= '0'; + n1iO0l0i <= '0'; + n1iO0l0l <= '0'; + n1iO0l0O <= '0'; + n1iO0l1i <= '0'; + n1iO0l1l <= '0'; + n1iO0l1O <= '0'; + n1iO110i <= '0'; + n1iO110l <= '0'; + n1iO110O <= '0'; + n1iO111i <= '0'; + n1iO111l <= '0'; + n1iO111O <= '0'; + n1iO11ii <= '0'; + n1iO11il <= '0'; + n1iO11iO <= '0'; + n1iOl00i <= '0'; + n1iOl00l <= '0'; + n1iOl00O <= '0'; + n1iOl01i <= '0'; + n1iOl01l <= '0'; + n1iOl01O <= '0'; + n1iOl0ii <= '0'; + n1iOl0il <= '0'; + n1iOl0iO <= '0'; + n1iOl0li <= '0'; + n1iOl0ll <= '0'; + n1iOl0lO <= '0'; + n1iOl0Oi <= '0'; + n1iOl0Ol <= '0'; + n1iOl10i <= '0'; + n1iOl10l <= '0'; + n1iOl10O <= '0'; + n1iOl1ii <= '0'; + n1iOl1il <= '0'; + n1iOl1iO <= '0'; + n1iOl1li <= '0'; + n1iOl1ll <= '0'; + n1iOl1lO <= '0'; + n1iOl1Oi <= '0'; + n1iOl1Ol <= '0'; + n1iOl1OO <= '0'; + n1l0000i <= '0'; + n1l0000l <= '0'; + n1l0000O <= '0'; + n1l0001i <= '0'; + n1l0001l <= '0'; + n1l0001O <= '0'; + n1l000ii <= '0'; + n1l000il <= '0'; + n1l000iO <= '0'; + n1l000li <= '0'; + n1l000ll <= '0'; + n1l000lO <= '0'; + n1l000Oi <= '0'; + n1l000Ol <= '0'; + n1l000OO <= '0'; + n1l0010i <= '0'; + n1l0010l <= '0'; + n1l0010O <= '0'; + n1l0011l <= '0'; + n1l0011O <= '0'; + n1l001ii <= '0'; + n1l001il <= '0'; + n1l001iO <= '0'; + n1l001li <= '0'; + n1l001ll <= '0'; + n1l001lO <= '0'; + n1l001Oi <= '0'; + n1l001Ol <= '0'; + n1l001OO <= '0'; + n1l00i0i <= '0'; + n1l00i1i <= '0'; + n1l00i1l <= '0'; + n1l00i1O <= '0'; + n1l10iiO <= '0'; + n1l1100i <= '0'; + n1l1100l <= '0'; + n1l1100O <= '0'; + n1l1101i <= '0'; + n1l1101l <= '0'; + n1l1101O <= '0'; + n1l110ii <= '0'; + n1l110il <= '0'; + n1l110iO <= '0'; + n1l1O1il <= '0'; + n1l1O1iO <= '0'; + n1l1O1li <= '0'; + n1l1O1ll <= '0'; + n1l1O1lO <= '0'; + n1l1O1Oi <= '0'; + n1l1O1Ol <= '0'; + n1l1O1OO <= '0'; + n1l1Ol0l <= '0'; + n1l1Olll <= '0'; + n1l1OllO <= '0'; + n1l1OlOi <= '0'; + n1l1OlOl <= '0'; + n1l1OlOO <= '0'; + n1l1OO0i <= '0'; + n1l1OO0O <= '0'; + n1l1OO1i <= '0'; + n1l1OO1l <= '0'; + n1l1OO1O <= '0'; + n1l1OOii <= '0'; + n1l1OOiO <= '0'; + n1l1OOll <= '0'; + n1l1OOlO <= '0'; + n1l1OOOl <= '0'; + n1lil0Ol <= '0'; + n1lili0l <= '0'; + n1lilill <= '0'; + n1liliOi <= '0'; + n1liliOl <= '0'; + n1liliOO <= '0'; + n1lill0i <= '0'; + n1lill0l <= '0'; + n1lill0O <= '0'; + n1lill1i <= '0'; + n1lill1l <= '0'; + n1lill1O <= '0'; + n1lillii <= '0'; + n1lillil <= '0'; + n1lilliO <= '0'; + n1lillli <= '0'; + n1lillll <= '0'; + n1lilllO <= '0'; + n1lillOi <= '0'; + n1lillOl <= '0'; + n1lillOO <= '0'; + n1lilO0i <= '0'; + n1lilO0l <= '0'; + n1lilO1i <= '0'; + n1lilO1l <= '0'; + n1lilO1O <= '0'; + n1lilOii <= '0'; + n1lilOil <= '0'; + n1llO1Ol <= '0'; + n1lO0llO <= '0'; + n1lO0lOi <= '0'; + n1lO0lOl <= '0'; + n1lOi00i <= '0'; + n1lOi00l <= '0'; + n1lOi00O <= '0'; + n1lOi01i <= '0'; + n1lOi01l <= '0'; + n1lOi01O <= '0'; + n1lOi0il <= '0'; + n1lOi1lO <= '0'; + n1lOi1Oi <= '0'; + n1lOi1Ol <= '0'; + n1lOi1OO <= '0'; + n1lOO00i <= '0'; + n1lOO00l <= '0'; + n1lOO00O <= '0'; + n1lOO01i <= '0'; + n1lOO01l <= '0'; + n1lOO01O <= '0'; + n1lOO0ii <= '0'; + n1lOO0il <= '0'; + n1lOO0iO <= '0'; + n1lOO0li <= '0'; + n1lOO0ll <= '0'; + n1lOO0lO <= '0'; + n1lOO0Oi <= '0'; + n1lOO0Ol <= '0'; + n1lOO0OO <= '0'; + n1lOO10i <= '0'; + n1lOO10l <= '0'; + n1lOO10O <= '0'; + n1lOO11l <= '0'; + n1lOO11O <= '0'; + n1lOO1ii <= '0'; + n1lOO1il <= '0'; + n1lOO1iO <= '0'; + n1lOO1li <= '0'; + n1lOO1ll <= '0'; + n1lOO1lO <= '0'; + n1lOO1Oi <= '0'; + n1lOO1Ol <= '0'; + n1lOO1OO <= '0'; + n1lOOi0i <= '0'; + n1lOOi0l <= '0'; + n1lOOi0O <= '0'; + n1lOOi1i <= '0'; + n1lOOi1l <= '0'; + n1lOOi1O <= '0'; + n1lOOiii <= '0'; + n1lOOiil <= '0'; + n1lOOiiO <= '0'; + n1lOOili <= '0'; + n1lOOill <= '0'; + n1lOOilO <= '0'; + n1lOOiOi <= '0'; + n1lOOiOl <= '0'; + n1lOOiOO <= '0'; + n1lOOl0i <= '0'; + n1lOOl0l <= '0'; + n1lOOl0O <= '0'; + n1lOOl1i <= '0'; + n1lOOl1l <= '0'; + n1lOOl1O <= '0'; + n1lOOlii <= '0'; + n1lOOlil <= '0'; + n1lOOliO <= '0'; + n1lOOlli <= '0'; + n1lOOlll <= '0'; + n1lOOllO <= '0'; + n1lOOlOi <= '0'; + n1lOOlOl <= '0'; + n1lOOlOO <= '0'; + n1lOOO0i <= '0'; + n1lOOO0l <= '0'; + n1lOOO0O <= '0'; + n1lOOO1i <= '0'; + n1lOOO1l <= '0'; + n1lOOO1O <= '0'; + n1lOOOii <= '0'; + n1lOOOil <= '0'; + n1lOOOiO <= '0'; + n1lOOOli <= '0'; + n1lOOOll <= '0'; + n1lOOOlO <= '0'; + n1O01iOO <= '0'; + n1O01lll <= '0'; + n1O01llO <= '0'; + n1O01lOi <= '0'; + n1O01lOl <= '0'; + n1O01lOO <= '0'; + n1O01O0i <= '0'; + n1O01O0l <= '0'; + n1O01O0O <= '0'; + n1O01O1i <= '0'; + n1O01O1l <= '0'; + n1O01O1O <= '0'; + n1O01Oii <= '0'; + n1O01Oil <= '0'; + n1O01OiO <= '0'; + n1O01Oli <= '0'; + n1O01Oll <= '0'; + n1O0i00l <= '0'; + n1O0i00O <= '0'; + n1O0i0ii <= '0'; + n1O0i0il <= '0'; + n1O0i0iO <= '0'; + n1O0i0li <= '0'; + n1O0i0ll <= '0'; + n1O0i0lO <= '0'; + n1O0i0Oi <= '0'; + n1O0i0Ol <= '0'; + n1O0i0OO <= '0'; + n1O0i1iO <= '0'; + n1O0ii0i <= '0'; + n1O0ii1i <= '0'; + n1O0ii1l <= '0'; + n1O0ii1O <= '0'; + n1O0Oi0l <= '0'; + n1O0Oi0O <= '0'; + n1O0Oiii <= '0'; + n1O0Oiil <= '0'; + n1O0Ol1i <= '0'; + n1O0Olli <= '0'; + n1O0Olll <= '0'; + n1O0OllO <= '0'; + n1O0OlOi <= '0'; + n1Oi000i <= '0'; + n1Oi001i <= '0'; + n1Oi001l <= '0'; + n1Oi001O <= '0'; + n1Oi010i <= '0'; + n1Oi010l <= '0'; + n1Oi010O <= '0'; + n1Oi011i <= '0'; + n1Oi011l <= '0'; + n1Oi011O <= '0'; + n1Oi01ii <= '0'; + n1Oi01il <= '0'; + n1Oi01iO <= '0'; + n1Oi01li <= '0'; + n1Oi01ll <= '0'; + n1Oi01lO <= '0'; + n1Oi01Oi <= '0'; + n1Oi01Ol <= '0'; + n1Oi01OO <= '0'; + n1Oi101O <= '0'; + n1Oi11Oi <= '0'; + n1Oi1l0i <= '0'; + n1Oi1l0l <= '0'; + n1Oi1l0O <= '0'; + n1Oi1lii <= '0'; + n1Oi1lil <= '0'; + n1Oi1liO <= '0'; + n1Oi1lli <= '0'; + n1Oi1lll <= '0'; + n1Oi1llO <= '0'; + n1Oi1lOi <= '0'; + n1Oi1lOl <= '0'; + n1Oi1lOO <= '0'; + n1Oi1O0i <= '0'; + n1Oi1O0l <= '0'; + n1Oi1O0O <= '0'; + n1Oi1O1i <= '0'; + n1Oi1O1l <= '0'; + n1Oi1O1O <= '0'; + n1Oi1Oii <= '0'; + n1Oi1Oil <= '0'; + n1Oi1OiO <= '0'; + n1Oi1Oli <= '0'; + n1Oi1Oll <= '0'; + n1Oi1OlO <= '0'; + n1Oi1OOi <= '0'; + n1Oi1OOl <= '0'; + n1Oi1OOO <= '0'; + n1Oili0i <= '0'; + n1Oili0l <= '0'; + n1Oili0O <= '0'; + n1Oiliii <= '0'; + n1Oiliil <= '0'; + n1OiliiO <= '0'; + n1Oilili <= '0'; + n1Oilill <= '0'; + n1OililO <= '0'; + n1OiliOi <= '0'; + n1OiliOl <= '0'; + n1OiliOO <= '0'; + n1Oill0i <= '0'; + n1Oill0l <= '0'; + n1Oill0O <= '0'; + n1Oill1i <= '0'; + n1Oill1l <= '0'; + n1Oill1O <= '0'; + n1Oillii <= '0'; + n1Oillil <= '0'; + n1OilliO <= '0'; + n1Oillli <= '0'; + n1Oillll <= '0'; + n1OilllO <= '0'; + n1OillOi <= '0'; + n1OillOl <= '0'; + n1OillOO <= '0'; + n1OilO0i <= '0'; + n1OilO0l <= '0'; + n1OilO0O <= '0'; + n1OilO1i <= '0'; + n1OilO1l <= '0'; + n1OilO1O <= '0'; + n1OilOii <= '0'; + n1OilOil <= '0'; + n1OilOiO <= '0'; + n1OilOli <= '0'; + n1OilOll <= '0'; + n1OiO11i <= '0'; + n1Ol000i <= '0'; + n1Ol000l <= '0'; + n1Ol000O <= '0'; + n1Ol001l <= '0'; + n1Ol001O <= '0'; + n1Ol00ii <= '0'; + n1Ol00il <= '0'; + n1Ol00iO <= '0'; + n1Ol00li <= '0'; + n1Ol00ll <= '0'; + n1Ol011i <= '0'; + n1Ol011l <= '0'; + n1Ol0lil <= '0'; + n1Ol0liO <= '0'; + n1Ol0lli <= '0'; + n1Ol0lll <= '0'; + n1Ol0llO <= '0'; + n1Ol0lOi <= '0'; + n1Ol1OOl <= '0'; + n1Ol1OOO <= '0'; + n1Oli00i <= '0'; + n1Oli00l <= '0'; + n1Oli00O <= '0'; + n1Oli0ii <= '0'; + n1Oli0il <= '0'; + n1Oli0iO <= '0'; + n1Oli0li <= '0'; + n1Oli0ll <= '0'; + n1Oli0lO <= '0'; + n1Oli0Oi <= '0'; + n1Oli0Ol <= '0'; + n1Oli0OO <= '0'; + n1Olii0i <= '0'; + n1Olii0l <= '0'; + n1Olii0O <= '0'; + n1Olii1i <= '0'; + n1Olii1l <= '0'; + n1Olii1O <= '0'; + n1Oliiii <= '0'; + n1Oliiil <= '0'; + n1OliiiO <= '0'; + n1Oliili <= '0'; + n1Oliill <= '0'; + n1OliilO <= '0'; + n1OliiOi <= '0'; + n1OliiOl <= '0'; + n1Oll0li <= '0'; + n1OO0lll <= '0'; + n1OO0llO <= '0'; + n1OO0lOi <= '0'; + n1OO0lOl <= '0'; + n1OO0lOO <= '0'; + n1OO0O0i <= '0'; + n1OO0O0l <= '0'; + n1OO0O0O <= '0'; + n1OO0O1i <= '0'; + n1OO0O1l <= '0'; + n1OO0O1O <= '0'; + n1OO0Oii <= '0'; + n1OO0Oil <= '0'; + n1OO0OiO <= '0'; + n1OO0Oli <= '0'; + n1OO0Oll <= '0'; + n1OOl00i <= '0'; + n1OOl0OO <= '0'; + n1OOli0i <= '0'; + n1OOli0l <= '0'; + n1OOli0O <= '0'; + n1OOli1i <= '0'; + n1OOli1l <= '0'; + n1OOli1O <= '0'; + n1OOliii <= '0'; + n1OOliil <= '0'; + n1OOliiO <= '0'; + n1OOlili <= '0'; + n1OOlill <= '0'; + n1OOlilO <= '0'; + n1OOliOi <= '0'; + n1OOliOl <= '0'; + n1OOliOO <= '0'; + n1OOOlOi <= '0'; + n1OOOOiO <= '0'; + n1OOOOli <= '0'; + n1OOOOll <= '0'; + n1OOOOlO <= '0'; + n1OOOOOi <= '0'; + n1OOOOOl <= '0'; + n1OOOOOO <= '0'; + ni00011i <= '0'; + ni000i0i <= '0'; + ni000i0l <= '0'; + ni000i0O <= '0'; + ni000i1O <= '0'; + ni000iii <= '0'; + ni000iil <= '0'; + ni000iiO <= '0'; + ni000ili <= '0'; + ni000ill <= '0'; + ni000OOi <= '0'; + ni000OOl <= '0'; + ni000OOO <= '0'; + ni0010Oi <= '0'; + ni0010Ol <= '0'; + ni0010OO <= '0'; + ni001i0i <= '0'; + ni001i0l <= '0'; + ni001i0O <= '0'; + ni001i1i <= '0'; + ni001i1l <= '0'; + ni001i1O <= '0'; + ni001Oil <= '0'; + ni001OiO <= '0'; + ni001Oli <= '0'; + ni001Oll <= '0'; + ni001OlO <= '0'; + ni001OOi <= '0'; + ni001OOl <= '0'; + ni001OOO <= '0'; + ni00i10i <= '0'; + ni00i10l <= '0'; + ni00i10O <= '0'; + ni00i11i <= '0'; + ni00i11l <= '0'; + ni00i11O <= '0'; + ni00iiil <= '0'; + ni00iiiO <= '0'; + ni00iili <= '0'; + ni00iill <= '0'; + ni00iilO <= '0'; + ni00iiOi <= '0'; + ni00iiOl <= '0'; + ni00iiOO <= '0'; + ni00il1i <= '0'; + ni00l10i <= '0'; + ni00l10l <= '0'; + ni00l10O <= '0'; + ni00l11O <= '0'; + ni00l1ii <= '0'; + ni00l1il <= '0'; + ni00l1iO <= '0'; + ni00l1li <= '0'; + ni00l1ll <= '0'; + ni00liOi <= '0'; + ni00liOl <= '0'; + ni00liOO <= '0'; + ni00ll1i <= '0'; + ni01000i <= '0'; + ni01000l <= '0'; + ni01000O <= '0'; + ni01001i <= '0'; + ni01001l <= '0'; + ni01001O <= '0'; + ni0100ii <= '0'; + ni0100il <= '0'; + ni0100iO <= '0'; + ni010lll <= '0'; + ni010llO <= '0'; + ni010lOi <= '0'; + ni010lOl <= '0'; + ni010lOO <= '0'; + ni010O0i <= '0'; + ni010O1i <= '0'; + ni010O1l <= '0'; + ni010O1O <= '0'; + ni01100i <= '0'; + ni01101i <= '0'; + ni01101l <= '0'; + ni01101O <= '0'; + ni0111li <= '0'; + ni0111ll <= '0'; + ni0111lO <= '0'; + ni0111Oi <= '0'; + ni0111Ol <= '0'; + ni0111OO <= '0'; + ni011l0O <= '0'; + ni011lii <= '0'; + ni011lil <= '0'; + ni011liO <= '0'; + ni011lli <= '0'; + ni011lll <= '0'; + ni011llO <= '0'; + ni011lOi <= '0'; + ni011lOl <= '0'; + ni01i00O <= '0'; + ni01i0ii <= '0'; + ni01i0il <= '0'; + ni01i0iO <= '0'; + ni01i0li <= '0'; + ni01i0ll <= '0'; + ni01i0lO <= '0'; + ni01i0Oi <= '0'; + ni01i0Ol <= '0'; + ni01iO0i <= '0'; + ni01iO0l <= '0'; + ni01iO0O <= '0'; + ni01iO1i <= '0'; + ni01iO1l <= '0'; + ni01iO1O <= '0'; + ni01iOii <= '0'; + ni01iOil <= '0'; + ni01iOiO <= '0'; + ni01l0ll <= '0'; + ni01l0lO <= '0'; + ni01l0Oi <= '0'; + ni01l0Ol <= '0'; + ni01l0OO <= '0'; + ni01li0i <= '0'; + ni01li1i <= '0'; + ni01li1l <= '0'; + ni01li1O <= '0'; + ni01lO0O <= '0'; + ni01lOii <= '0'; + ni01lOil <= '0'; + ni01lOiO <= '0'; + ni01O0ll <= '0'; + ni01O0lO <= '0'; + ni01O0Oi <= '0'; + ni01O0Ol <= '0'; + ni01O0OO <= '0'; + ni01Oi0i <= '0'; + ni01Oi1i <= '0'; + ni01Oi1l <= '0'; + ni01Oi1O <= '0'; + ni01OO0i <= '0'; + ni01OO0l <= '0'; + ni01OO0O <= '0'; + ni01OO1l <= '0'; + ni01OO1O <= '0'; + ni01OOii <= '0'; + ni01OOil <= '0'; + ni01OOiO <= '0'; + ni01OOli <= '0'; + ni01OOll <= '0'; + ni0i000i <= '0'; + ni0i000l <= '0'; + ni0i000O <= '0'; + ni0i001i <= '0'; + ni0i001l <= '0'; + ni0i001O <= '0'; + ni0i00ii <= '0'; + ni0i00il <= '0'; + ni0i00iO <= '0'; + ni0i00li <= '0'; + ni0i00ll <= '0'; + ni0i00lO <= '0'; + ni0i00Oi <= '0'; + ni0i00Ol <= '0'; + ni0i00OO <= '0'; + ni0i010i <= '0'; + ni0i010l <= '0'; + ni0i010O <= '0'; + ni0i011i <= '0'; + ni0i011l <= '0'; + ni0i011O <= '0'; + ni0i01ii <= '0'; + ni0i01il <= '0'; + ni0i01iO <= '0'; + ni0i01li <= '0'; + ni0i01ll <= '0'; + ni0i01lO <= '0'; + ni0i01Oi <= '0'; + ni0i01Ol <= '0'; + ni0i01OO <= '0'; + ni0i0i0i <= '0'; + ni0i0i0l <= '0'; + ni0i0i0O <= '0'; + ni0i0i1i <= '0'; + ni0i0i1l <= '0'; + ni0i0i1O <= '0'; + ni0i100i <= '0'; + ni0i100l <= '0'; + ni0i100O <= '0'; + ni0i101i <= '0'; + ni0i101l <= '0'; + ni0i101O <= '0'; + ni0i10ii <= '0'; + ni0i10il <= '0'; + ni0i10iO <= '0'; + ni0i10li <= '0'; + ni0i10ll <= '0'; + ni0i10lO <= '0'; + ni0i10Oi <= '0'; + ni0i10Ol <= '0'; + ni0i10OO <= '0'; + ni0i110i <= '0'; + ni0i110l <= '0'; + ni0i111l <= '0'; + ni0i111O <= '0'; + ni0i1i0i <= '0'; + ni0i1i0l <= '0'; + ni0i1i0O <= '0'; + ni0i1i1i <= '0'; + ni0i1i1l <= '0'; + ni0i1i1O <= '0'; + ni0i1iii <= '0'; + ni0i1iil <= '0'; + ni0i1iiO <= '0'; + ni0i1ili <= '0'; + ni0i1ill <= '0'; + ni0i1ilO <= '0'; + ni0i1iOi <= '0'; + ni0i1iOl <= '0'; + ni0i1iOO <= '0'; + ni0i1l0i <= '0'; + ni0i1l0l <= '0'; + ni0i1l0O <= '0'; + ni0i1l1i <= '0'; + ni0i1l1l <= '0'; + ni0i1l1O <= '0'; + ni0i1lii <= '0'; + ni0i1lil <= '0'; + ni0i1liO <= '0'; + ni0i1lli <= '0'; + ni0i1lll <= '0'; + ni0i1llO <= '0'; + ni0i1lOi <= '0'; + ni0i1lOl <= '0'; + ni0i1lOO <= '0'; + ni0i1O0i <= '0'; + ni0i1O0l <= '0'; + ni0i1O0O <= '0'; + ni0i1O1i <= '0'; + ni0i1O1l <= '0'; + ni0i1O1O <= '0'; + ni0i1Oii <= '0'; + ni0i1Oil <= '0'; + ni0i1OiO <= '0'; + ni0i1Oli <= '0'; + ni0i1Oll <= '0'; + ni0i1OlO <= '0'; + ni0i1OOi <= '0'; + ni0i1OOl <= '0'; + ni0i1OOO <= '0'; + ni1000lO <= '0'; + ni1000Oi <= '0'; + ni1000Ol <= '0'; + ni1000OO <= '0'; + ni100i0i <= '0'; + ni100i0l <= '0'; + ni100i0O <= '0'; + ni100i1i <= '0'; + ni100i1l <= '0'; + ni100i1O <= '0'; + ni100Oil <= '0'; + ni100OiO <= '0'; + ni100Oli <= '0'; + ni100Oll <= '0'; + ni100OlO <= '0'; + ni100OOi <= '0'; + ni100OOl <= '0'; + ni100OOO <= '0'; + ni101i0i <= '0'; + ni101i1i <= '0'; + ni101i1l <= '0'; + ni101i1O <= '0'; + ni101O0O <= '0'; + ni101Oii <= '0'; + ni101Oil <= '0'; + ni101OiO <= '0'; + ni101Oli <= '0'; + ni101Oll <= '0'; + ni101OlO <= '0'; + ni101OOi <= '0'; + ni101OOl <= '0'; + ni10i11i <= '0'; + ni10ii0i <= '0'; + ni10ii0l <= '0'; + ni10ii0O <= '0'; + ni10ii1O <= '0'; + ni10iiii <= '0'; + ni10iiil <= '0'; + ni10iiiO <= '0'; + ni10iili <= '0'; + ni10iill <= '0'; + ni10iOOi <= '0'; + ni10iOOl <= '0'; + ni10iOOO <= '0'; + ni10l10i <= '0'; + ni10l10l <= '0'; + ni10l10O <= '0'; + ni10l11i <= '0'; + ni10l11l <= '0'; + ni10l11O <= '0'; + ni10liil <= '0'; + ni10liiO <= '0'; + ni10lili <= '0'; + ni10lill <= '0'; + ni10lilO <= '0'; + ni10liOi <= '0'; + ni10liOl <= '0'; + ni10liOO <= '0'; + ni10ll1i <= '0'; + ni10O10i <= '0'; + ni10O10l <= '0'; + ni10O10O <= '0'; + ni10O11O <= '0'; + ni10O1ii <= '0'; + ni10O1il <= '0'; + ni10O1iO <= '0'; + ni10O1li <= '0'; + ni10O1ll <= '0'; + ni10OiOi <= '0'; + ni10OiOl <= '0'; + ni10OiOO <= '0'; + ni10Ol0i <= '0'; + ni10Ol0l <= '0'; + ni10Ol0O <= '0'; + ni10Ol1i <= '0'; + ni10Ol1l <= '0'; + ni10Ol1O <= '0'; + ni11000i <= '0'; + ni11000l <= '0'; + ni11000O <= '0'; + ni11001i <= '0'; + ni11001l <= '0'; + ni11001O <= '0'; + ni1100ii <= '0'; + ni1101Ol <= '0'; + ni1101OO <= '0'; + ni110l0l <= '0'; + ni110l0O <= '0'; + ni110lii <= '0'; + ni110lil <= '0'; + ni110liO <= '0'; + ni110lli <= '0'; + ni110lll <= '0'; + ni110llO <= '0'; + ni110lOi <= '0'; + ni110lOl <= '0'; + ni11100i <= '0'; + ni11100l <= '0'; + ni11100O <= '0'; + ni11101i <= '0'; + ni11101l <= '0'; + ni11101O <= '0'; + ni1110ii <= '0'; + ni1111Ol <= '0'; + ni1111OO <= '0'; + ni111liO <= '0'; + ni111lli <= '0'; + ni111lll <= '0'; + ni111llO <= '0'; + ni11i00i <= '0'; + ni11i00l <= '0'; + ni11i00O <= '0'; + ni11i01i <= '0'; + ni11i01l <= '0'; + ni11i01O <= '0'; + ni11i0ii <= '0'; + ni11i0il <= '0'; + ni11i0iO <= '0'; + ni11illl <= '0'; + ni11illO <= '0'; + ni11ilOi <= '0'; + ni11ilOl <= '0'; + ni11ilOO <= '0'; + ni11iO0i <= '0'; + ni11iO1i <= '0'; + ni11iO1l <= '0'; + ni11iO1O <= '0'; + ni11l00O <= '0'; + ni11l0ii <= '0'; + ni11l0il <= '0'; + ni11l0iO <= '0'; + ni11l0li <= '0'; + ni11l0ll <= '0'; + ni11l0lO <= '0'; + ni11l0Oi <= '0'; + ni11l0Ol <= '0'; + ni11lO0i <= '0'; + ni11lO0l <= '0'; + ni11lO0O <= '0'; + ni11lO1i <= '0'; + ni11lO1l <= '0'; + ni11lO1O <= '0'; + ni11lOii <= '0'; + ni11lOil <= '0'; + ni11lOiO <= '0'; + ni11O0ll <= '0'; + ni11O0lO <= '0'; + ni11O0Oi <= '0'; + ni11O0Ol <= '0'; + ni11O0OO <= '0'; + ni11Oi0i <= '0'; + ni11Oi1i <= '0'; + ni11Oi1l <= '0'; + ni11Oi1O <= '0'; + ni11OO0O <= '0'; + ni11OOii <= '0'; + ni11OOil <= '0'; + ni11OOiO <= '0'; + ni11OOli <= '0'; + ni11OOll <= '0'; + ni11OOlO <= '0'; + ni11OOOi <= '0'; + ni11OOOl <= '0'; + ni1i010i <= '0'; + ni1i010l <= '0'; + ni1i010O <= '0'; + ni1i01ii <= '0'; + ni1i01il <= '0'; + ni1i01iO <= '0'; + ni1i01li <= '0'; + ni1i01ll <= '0'; + ni1i01lO <= '0'; + ni1i01Oi <= '0'; + ni1i0iOO <= '0'; + ni1i0l0i <= '0'; + ni1i0l0l <= '0'; + ni1i0l0O <= '0'; + ni1i0l1i <= '0'; + ni1i0l1l <= '0'; + ni1i0l1O <= '0'; + ni1i0lii <= '0'; + ni1i0lil <= '0'; + ni1i11il <= '0'; + ni1i11iO <= '0'; + ni1i11li <= '0'; + ni1i11ll <= '0'; + ni1i1iOi <= '0'; + ni1i1iOl <= '0'; + ni1i1iOO <= '0'; + ni1i1l0i <= '0'; + ni1i1l0l <= '0'; + ni1i1l0O <= '0'; + ni1i1l1i <= '0'; + ni1i1l1l <= '0'; + ni1i1l1O <= '0'; + ni1ii01i <= '0'; + ni1ii01l <= '0'; + ni1ii01O <= '0'; + ni1ii1li <= '0'; + ni1ii1ll <= '0'; + ni1ii1lO <= '0'; + ni1ii1Oi <= '0'; + ni1ii1Ol <= '0'; + ni1ii1OO <= '0'; + ni1iil0l <= '0'; + ni1iil0O <= '0'; + ni1iilii <= '0'; + ni1iilil <= '0'; + ni1iiliO <= '0'; + ni1iilli <= '0'; + ni1iilll <= '0'; + ni1iillO <= '0'; + ni1iilOi <= '0'; + ni1il00i <= '0'; + ni1il00l <= '0'; + ni1il00O <= '0'; + ni1il01i <= '0'; + ni1il01l <= '0'; + ni1il01O <= '0'; + ni1il0ii <= '0'; + ni1il0il <= '0'; + ni1il1OO <= '0'; + ni1illli <= '0'; + ni1illll <= '0'; + ni1illlO <= '0'; + ni1illOi <= '0'; + ni1illOl <= '0'; + ni1illOO <= '0'; + ni1ilO1i <= '0'; + ni1ilO1l <= '0'; + ni1ilO1O <= '0'; + ni1iO00l <= '0'; + ni1iO00O <= '0'; + ni1iO0ii <= '0'; + ni1iO0il <= '0'; + ni1iO0iO <= '0'; + ni1iO0li <= '0'; + ni1iO0ll <= '0'; + ni1iO0lO <= '0'; + ni1iO0Oi <= '0'; + ni1iOlOO <= '0'; + ni1iOO1i <= '0'; + ni1iOO1l <= '0'; + ni1iOO1O <= '0'; + ni1l00ii <= '0'; + ni1l00il <= '0'; + ni1l00iO <= '0'; + ni1l00li <= '0'; + ni1l00ll <= '0'; + ni1l00lO <= '0'; + ni1l00Oi <= '0'; + ni1l00Ol <= '0'; + ni1l00OO <= '0'; + ni1l0O0i <= '0'; + ni1l0O0l <= '0'; + ni1l0O0O <= '0'; + ni1l0O1l <= '0'; + ni1l0O1O <= '0'; + ni1l0Oii <= '0'; + ni1l0Oil <= '0'; + ni1l0OiO <= '0'; + ni1l0Oli <= '0'; + ni1l100l <= '0'; + ni1l100O <= '0'; + ni1l10ii <= '0'; + ni1l10il <= '0'; + ni1l10iO <= '0'; + ni1l10li <= '0'; + ni1l10ll <= '0'; + ni1l10lO <= '0'; + ni1l10Oi <= '0'; + ni1l1lll <= '0'; + ni1l1llO <= '0'; + ni1l1lOi <= '0'; + ni1l1lOl <= '0'; + ni1l1lOO <= '0'; + ni1l1O0i <= '0'; + ni1l1O0l <= '0'; + ni1l1O1i <= '0'; + ni1l1O1l <= '0'; + ni1l1O1O <= '0'; + ni1li0lO <= '0'; + ni1li0Oi <= '0'; + ni1li0Ol <= '0'; + ni1li0OO <= '0'; + ni1lii0i <= '0'; + ni1lii0l <= '0'; + ni1lii1i <= '0'; + ni1lii1l <= '0'; + ni1lii1O <= '0'; + ni1liOii <= '0'; + ni1liOil <= '0'; + ni1liOiO <= '0'; + ni1liOli <= '0'; + ni1liOll <= '0'; + ni1liOlO <= '0'; + ni1liOOi <= '0'; + ni1liOOl <= '0'; + ni1liOOO <= '0'; + ni1lli0i <= '0'; + ni1lli0l <= '0'; + ni1lli0O <= '0'; + ni1lli1l <= '0'; + ni1lli1O <= '0'; + ni1lliii <= '0'; + ni1lliil <= '0'; + ni1lliiO <= '0'; + ni1llili <= '0'; + ni1llOlO <= '0'; + ni1llOOi <= '0'; + ni1llOOl <= '0'; + ni1llOOO <= '0'; + ni1lO10i <= '0'; + ni1lO10l <= '0'; + ni1lO11i <= '0'; + ni1lO11l <= '0'; + ni1lO11O <= '0'; + ni1lOiii <= '0'; + ni1lOiil <= '0'; + ni1lOiiO <= '0'; + ni1lOili <= '0'; + ni1lOOlO <= '0'; + ni1lOOOi <= '0'; + ni1lOOOl <= '0'; + ni1lOOOO <= '0'; + ni1O010i <= '0'; + ni1O010l <= '0'; + ni1O010O <= '0'; + ni1O011i <= '0'; + ni1O011l <= '0'; + ni1O011O <= '0'; + ni1O01ii <= '0'; + ni1O0iiO <= '0'; + ni1O0ili <= '0'; + ni1O0ill <= '0'; + ni1O0ilO <= '0'; + ni1O0iOi <= '0'; + ni1O0iOl <= '0'; + ni1O0iOO <= '0'; + ni1O0l1i <= '0'; + ni1O0l1l <= '0'; + ni1O110i <= '0'; + ni1O110l <= '0'; + ni1O111i <= '0'; + ni1O111l <= '0'; + ni1O111O <= '0'; + ni1O1i0i <= '0'; + ni1O1i0l <= '0'; + ni1O1i0O <= '0'; + ni1O1i1O <= '0'; + ni1O1iii <= '0'; + ni1O1iil <= '0'; + ni1O1iiO <= '0'; + ni1O1ili <= '0'; + ni1O1ill <= '0'; + ni1O1ilO <= '0'; + ni1O1OOl <= '0'; + ni1O1OOO <= '0'; + ni1Oi10i <= '0'; + ni1Oi10l <= '0'; + ni1Oi10O <= '0'; + ni1Oi1ii <= '0'; + ni1Oi1il <= '0'; + ni1Oi1iO <= '0'; + ni1Oi1li <= '0'; + ni1Oi1ll <= '0'; + ni1Oi1lO <= '0'; + ni1OiiOl <= '0'; + ni1OiiOO <= '0'; + ni1Oil0i <= '0'; + ni1Oil0l <= '0'; + ni1Oil0O <= '0'; + ni1Oil1i <= '0'; + ni1Oil1l <= '0'; + ni1Oil1O <= '0'; + ni1Oilii <= '0'; + ni1Ol01i <= '0'; + ni1Ol01l <= '0'; + ni1Ol1iO <= '0'; + ni1Ol1li <= '0'; + ni1Ol1ll <= '0'; + ni1Ol1lO <= '0'; + ni1Ol1Oi <= '0'; + ni1Ol1Ol <= '0'; + ni1Ol1OO <= '0'; + ni1Oll0i <= '0'; + ni1Oll0l <= '0'; + ni1Oll0O <= '0'; + ni1Ollii <= '0'; + ni1Ollil <= '0'; + ni1OlliO <= '0'; + ni1Ollli <= '0'; + ni1Ollll <= '0'; + ni1OlllO <= '0'; + ni1OO01i <= '0'; + ni1OO01l <= '0'; + ni1OO1Ol <= '0'; + ni1OO1OO <= '0'; + ni1OOl0i <= '0'; + ni1OOl0l <= '0'; + ni1OOl0O <= '0'; + ni1OOlii <= '0'; + ni1OOlil <= '0'; + ni1OOliO <= '0'; + ni1OOlli <= '0'; + ni1OOlll <= '0'; + ni1OOllO <= '0'; + nii0li1l <= '0'; + nii0lllO <= '0'; + nii0O1ii <= '0'; + nii0Oi1l <= '0'; + nii0OllO <= '0'; + niii00OO <= '0'; + niii0i1i <= '0'; + niii0i1l <= '0'; + niii0OOl <= '0'; + niii0OOO <= '0'; + niii11ii <= '0'; + niii1i1l <= '0'; + niii1llO <= '0'; + niii1O0l <= '0'; + niii1O0O <= '0'; + niii1Oii <= '0'; + niii1Oil <= '0'; + niii1OiO <= '0'; + niii1Oli <= '0'; + niii1Oll <= '0'; + niii1OlO <= '0'; + niiii00i <= '0'; + niiii00l <= '0'; + niiii00O <= '0'; + niiii01i <= '0'; + niiii01l <= '0'; + niiii01O <= '0'; + niiii0ii <= '0'; + niiii0il <= '0'; + niiii0iO <= '0'; + niiii0li <= '0'; + niiii0ll <= '0'; + niiii0lO <= '0'; + niiii0Oi <= '0'; + niiii0Ol <= '0'; + niiii0OO <= '0'; + niiii10i <= '0'; + niiii10l <= '0'; + niiii10O <= '0'; + niiii11i <= '0'; + niiii11l <= '0'; + niiii11O <= '0'; + niiii1ii <= '0'; + niiii1il <= '0'; + niiii1iO <= '0'; + niiii1li <= '0'; + niiii1ll <= '0'; + niiii1lO <= '0'; + niiii1Oi <= '0'; + niiii1Ol <= '0'; + niiii1OO <= '0'; + niiiii0i <= '0'; + niiiii0l <= '0'; + niiiii0O <= '0'; + niiiii1i <= '0'; + niiiii1l <= '0'; + niiiii1O <= '0'; + niiiiiii <= '0'; + niiiiiil <= '0'; + niiiiiiO <= '0'; + niiiiili <= '0'; + niiiiill <= '0'; + niiiiilO <= '0'; + niiiiiOi <= '0'; + niiiiiOl <= '0'; + niiiiiOO <= '0'; + niiiil0i <= '0'; + niiiil0l <= '0'; + niiiil0O <= '0'; + niiiil1i <= '0'; + niiiil1l <= '0'; + niiiil1O <= '0'; + niiiilii <= '0'; + niiiilil <= '0'; + niiiiliO <= '0'; + niiiilli <= '0'; + niiiilll <= '0'; + niiiillO <= '0'; + niiiilOi <= '0'; + niiiilOl <= '0'; + niiiilOO <= '0'; + niiiiO0i <= '0'; + niiiiO0l <= '0'; + niiiiO0O <= '0'; + niiiiO1i <= '0'; + niiiiO1l <= '0'; + niiiiO1O <= '0'; + niiiiOii <= '0'; + niiiiOil <= '0'; + niiiiOiO <= '0'; + niiiiOli <= '0'; + niiiiOll <= '0'; + niiiiOlO <= '0'; + niiiiOOi <= '0'; + niiiiOOl <= '0'; + niiiiOOO <= '0'; + niiil11i <= '0'; + niiil11l <= '0'; + niil00Ol <= '0'; + niil010i <= '0'; + niil010l <= '0'; + niil010O <= '0'; + niO010ii <= '0'; + niO010ll <= '0'; + niO011ii <= '0'; + niO011ll <= '0'; + niO01iii <= '0'; + niO01ilO <= '0'; + niO10OlO <= '0'; + niO10OOi <= '0'; + niO10OOl <= '0'; + niO10OOO <= '0'; + niO1i00i <= '0'; + niO1i00l <= '0'; + niO1i00O <= '0'; + niO1i01i <= '0'; + niO1i01l <= '0'; + niO1i01O <= '0'; + niO1i0ii <= '0'; + niO1i0il <= '0'; + niO1i0iO <= '0'; + niO1i0li <= '0'; + niO1i0ll <= '0'; + niO1i0lO <= '0'; + niO1i0Oi <= '0'; + niO1i0Ol <= '0'; + niO1i0OO <= '0'; + niO1i10i <= '0'; + niO1i10l <= '0'; + niO1i10O <= '0'; + niO1i11i <= '0'; + niO1i11l <= '0'; + niO1i11O <= '0'; + niO1i1ii <= '0'; + niO1i1il <= '0'; + niO1i1iO <= '0'; + niO1i1li <= '0'; + niO1i1ll <= '0'; + niO1i1lO <= '0'; + niO1i1Oi <= '0'; + niO1i1Ol <= '0'; + niO1i1OO <= '0'; + niO1ii0i <= '0'; + niO1ii0l <= '0'; + niO1ii0O <= '0'; + niO1ii1i <= '0'; + niO1ii1l <= '0'; + niO1ii1O <= '0'; + niO1iiii <= '0'; + niO1iiil <= '0'; + niO1iiiO <= '0'; + niO1iili <= '0'; + niO1iill <= '0'; + niO1iilO <= '0'; + niO1iiOi <= '0'; + niO1iiOl <= '0'; + niO1iiOO <= '0'; + niO1il0i <= '0'; + niO1il0l <= '0'; + niO1il0O <= '0'; + niO1il1i <= '0'; + niO1il1l <= '0'; + niO1il1O <= '0'; + niO1ilii <= '0'; + niO1ilil <= '0'; + niO1iliO <= '0'; + niO1illi <= '0'; + niO1illl <= '0'; + niO1illO <= '0'; + niO1ilOi <= '0'; + niO1ilOl <= '0'; + niO1ilOO <= '0'; + niO1iO0i <= '0'; + niO1iO0l <= '0'; + niO1iO0O <= '0'; + niO1iO1i <= '0'; + niO1iO1l <= '0'; + niO1iO1O <= '0'; + niO1iOii <= '0'; + niO1iOil <= '0'; + niO1iOiO <= '0'; + niO1iOli <= '0'; + niO1iOll <= '0'; + niO1iOlO <= '0'; + niO1iOOi <= '0'; + niO1iOOl <= '0'; + niO1iOOO <= '0'; + niO1l00i <= '0'; + niO1l00l <= '0'; + niO1l00O <= '0'; + niO1l01i <= '0'; + niO1l01l <= '0'; + niO1l01O <= '0'; + niO1l0ii <= '0'; + niO1l0il <= '0'; + niO1l0iO <= '0'; + niO1l0li <= '0'; + niO1l0ll <= '0'; + niO1l0lO <= '0'; + niO1l0Oi <= '0'; + niO1l0Ol <= '0'; + niO1l0OO <= '0'; + niO1l10i <= '0'; + niO1l10l <= '0'; + niO1l10O <= '0'; + niO1l11i <= '0'; + niO1l11l <= '0'; + niO1l11O <= '0'; + niO1l1ii <= '0'; + niO1l1il <= '0'; + niO1l1iO <= '0'; + niO1l1li <= '0'; + niO1l1ll <= '0'; + niO1l1lO <= '0'; + niO1l1Oi <= '0'; + niO1l1Ol <= '0'; + niO1l1OO <= '0'; + niO1li1i <= '0'; + niO1li1l <= '0'; + niO1OOlO <= '0'; + niOO0O0OO <= '0'; + niOO0Oi0i <= '0'; + niOO0Oi0l <= '0'; + niOO0Oi1i <= '0'; + niOO0Oi1l <= '0'; + niOO0Oi1O <= '0'; + niOO0Olii <= '0'; + niOO0OllO <= '0'; + niOO0OlOl <= '0'; + nlOi000li <= '0'; + nlOi0011i <= '0'; + nlOi001il <= '0'; + nlOi001ll <= '0'; + nlOi00i0l <= '0'; + nlOi00i1l <= '0'; + nlOi00iOO <= '0'; + nlOi00l0i <= '0'; + nlOi00liO <= '0'; + nlOi00lOi <= '0'; + nlOi00OOi <= '0'; + nlOi0i00l <= '0'; + nlOi0i10l <= '0'; + nlOi0i1il <= '0'; + nlOi0i1iO <= '0'; + nlOi0il0i <= '0'; + nlOi0il0l <= '0'; + nlOi0il0O <= '0'; + nlOi0il1O <= '0'; + nlOi0ilii <= '0'; + nlOi0ilil <= '0'; + nlOi0iliO <= '0'; + nlOi0illi <= '0'; + nlOi0illl <= '0'; + nlOi0illO <= '0'; + nlOi0ilOi <= '0'; + nlOi0l01l <= '0'; + nlOi0l1li <= '0'; + nlOi0l1OO <= '0'; + nlOi0lO0O <= '0'; + nlOi0lOOi <= '0'; + nlOi0O0il <= '0'; + nlOi0O0OO <= '0'; + nlOi0O10l <= '0'; + nlOi0O11O <= '0'; + nlOi0Oi1O <= '0'; + nlOi0Ol1l <= '0'; + nlOi0OliO <= '0'; + nlOi0OllO <= '0'; + nlOi0OOli <= '0'; + nlOi0OOOO <= '0'; + nlOii001O <= '0'; + nlOii01il <= '0'; + nlOii01OO <= '0'; + nlOii0i1l <= '0'; + nlOii0iiO <= '0'; + nlOii0ilO <= '0'; + nlOii0lii <= '0'; + nlOii0lll <= '0'; + nlOii0lOO <= '0'; + nlOii0O0i <= '0'; + nlOii0Oil <= '0'; + nlOii0OOi <= '0'; + nlOii100i <= '0'; + nlOii10il <= '0'; + nlOii10lO <= '0'; + nlOii111l <= '0'; + nlOii11OO <= '0'; + nlOii1i0l <= '0'; + nlOii1ilO <= '0'; + nlOii1iOO <= '0'; + nlOii1lOl <= '0'; + nlOii1O0O <= '0'; + nlOii1OiO <= '0'; + nlOiii01l <= '0'; + nlOiii0iO <= '0'; + nlOiii0lO <= '0'; + nlOiii10O <= '0'; + nlOiii11l <= '0'; + nlOiii1li <= '0'; + nlOiiiiOl <= '0'; + nlOiil01i <= '0'; + nlOiil0il <= '0'; + nlOiil0ll <= '0'; + nlOiil0lO <= '0'; + nlOiil0Oi <= '0'; + nlOiil0Ol <= '0'; + nlOiil0OO <= '0'; + nlOiili1i <= '0'; + nlOiili1l <= '0'; + nlOiili1O <= '0'; + nlOiiO11l <= '0'; + nlOiiO1iO <= '0'; + nlOiiO1lO <= '0'; + nlOiiO1Oi <= '0'; + nlOiiO1Ol <= '0'; + nlOiiO1OO <= '0'; + nlOiiOlll <= '0'; + nlOiiOO0O <= '0'; + nlOiiOO1O <= '0'; + nlOiiOOii <= '0'; + nlOiiOOil <= '0'; + nlOiiOOiO <= '0'; + nlOiiOOli <= '0'; + nlOil10iO <= '0'; + nlOil10li <= '0'; + nlOil10ll <= '0'; + nlOil10lO <= '0'; + nlOil10Oi <= '0'; + nlOil10Ol <= '0'; + nlOil10OO <= '0'; + nlOil1i1i <= '0'; + nlOili01i <= '0'; + nlOili10O <= '0'; + nlOili1Oi <= '0'; + nlOill00l <= '0'; + nlOill00O <= '0'; + nlOill01l <= '0'; + nlOill01O <= '0'; + nlOill0ii <= '0'; + nlOill0il <= '0'; + nlOill0iO <= '0'; + nlOill0li <= '0'; + nlOill0ll <= '0'; + nlOill0lO <= '0'; + nlOill0Oi <= '0'; + nlOill0Ol <= '0'; + nlOill0OO <= '0'; + nlOill11l <= '0'; + nlOill1ii <= '0'; + nlOill1il <= '0'; + nlOill1iO <= '0'; + nlOill1li <= '0'; + nlOill1ll <= '0'; + nlOill1lO <= '0'; + nlOill1Oi <= '0'; + nlOill1Ol <= '0'; + nlOilO00l <= '0'; + nlOilO0lO <= '0'; + nlOilO0OO <= '0'; + nlOilOiOl <= '0'; + nlOilOl0O <= '0'; + nlOilOliO <= '0'; + nlOilOOil <= '0'; + nlOilOOOO <= '0'; + nlOiO011i <= '0'; + nlOiO100i <= '0'; + nlOiO100l <= '0'; + nlOiO100O <= '0'; + nlOiO101i <= '0'; + nlOiO101l <= '0'; + nlOiO101O <= '0'; + nlOiO10ii <= '0'; + nlOiO10il <= '0'; + nlOiO10iO <= '0'; + nlOiO10li <= '0'; + nlOiO10ll <= '0'; + nlOiO10lO <= '0'; + nlOiO10Oi <= '0'; + nlOiO111O <= '0'; + nlOiO11OO <= '0'; + nlOiO1lOO <= '0'; + nlOiOi11l <= '0'; + nlOiOi11O <= '0'; + nlOiOl00i <= '0'; + nlOiOl00l <= '0'; + nlOiOl00O <= '0'; + nlOiOl01i <= '0'; + nlOiOl01l <= '0'; + nlOiOl01O <= '0'; + nlOiOl0ii <= '0'; + nlOiOl0il <= '0'; + nlOiOl0iO <= '0'; + nlOiOl0li <= '0'; + nlOiOl0ll <= '0'; + nlOiOl0lO <= '0'; + nlOiOl0Oi <= '0'; + nlOiOl0Ol <= '0'; + nlOiOl0OO <= '0'; + nlOiOl1Oi <= '0'; + nlOiOl1Ol <= '0'; + nlOiOl1OO <= '0'; + nlOiOli0i <= '0'; + nlOiOli0l <= '0'; + nlOiOli0O <= '0'; + nlOiOli1i <= '0'; + nlOiOli1l <= '0'; + nlOiOli1O <= '0'; + nlOiOliii <= '0'; + nlOiOliil <= '0'; + nlOiOliiO <= '0'; + nlOiOlili <= '0'; + nlOiOlill <= '0'; + nlOiOlilO <= '0'; + nlOiOliOi <= '0'; + nlOiOliOl <= '0'; + nlOiOliOO <= '0'; + nlOiOll0i <= '0'; + nlOiOll0l <= '0'; + nlOiOll0O <= '0'; + nlOiOll1i <= '0'; + nlOiOll1l <= '0'; + nlOiOll1O <= '0'; + nlOiOllii <= '0'; + nlOiOllil <= '0'; + nlOiOlliO <= '0'; + nlOiOllli <= '0'; + nlOiOllll <= '0'; + nlOiOlllO <= '0'; + nlOiOllOi <= '0'; + nlOiOllOl <= '0'; + nlOiOllOO <= '0'; + nlOiOlO0i <= '0'; + nlOiOlO0l <= '0'; + nlOiOlO0O <= '0'; + nlOiOlO1i <= '0'; + nlOiOlO1l <= '0'; + nlOiOlO1O <= '0'; + nlOiOlOii <= '0'; + nlOiOlOil <= '0'; + nlOiOlOiO <= '0'; + nlOiOlOli <= '0'; + nlOiOlOll <= '0'; + nlOiOlOlO <= '0'; + nlOiOlOOi <= '0'; + nlOiOlOOl <= '0'; + nlOiOlOOO <= '0'; + nlOiOO10i <= '0'; + nlOiOO10l <= '0'; + nlOiOO10O <= '0'; + nlOiOO11i <= '0'; + nlOiOO11l <= '0'; + nlOiOO11O <= '0'; + nlOiOO1ii <= '0'; + nlOiOO1il <= '0'; + nlOiOO1iO <= '0'; + nlOiOO1li <= '0'; + nlOiOO1ll <= '0'; + nlOliiO0i <= '0'; + nlOliiO0l <= '0'; + nlOliiO0O <= '0'; + nlOliiOii <= '0'; + nlOliiOil <= '0'; + nlOliiOiO <= '0'; + nlOliiOli <= '0'; + nlOliiOll <= '0'; + nlOliiOlO <= '0'; + nlOliiOOi <= '0'; + nlOliiOOl <= '0'; + nlOliiOOO <= '0'; + nlOlil10i <= '0'; + nlOlil10l <= '0'; + nlOlil11i <= '0'; + nlOlil11l <= '0'; + nlOlil11O <= '0'; + nlOliO00i <= '0'; + nlOliO00l <= '0'; + nlOliO01i <= '0'; + nlOliO01l <= '0'; + nlOliO0ii <= '0'; + nlOliO0il <= '0'; + nlOliO0li <= '0'; + nlOliO0ll <= '0'; + nlOliO10i <= '0'; + nlOliO10l <= '0'; + nlOliO11i <= '0'; + nlOliO11l <= '0'; + nlOliO1ii <= '0'; + nlOliO1il <= '0'; + nlOliO1li <= '0'; + nlOliO1ll <= '0'; + nlOliO1Oi <= '0'; + nlOliO1Ol <= '0'; + nlOll000i <= '0'; + nlOll000l <= '0'; + nlOll000O <= '0'; + nlOll001i <= '0'; + nlOll001l <= '0'; + nlOll001O <= '0'; + nlOll01iO <= '0'; + nlOll01li <= '0'; + nlOll01ll <= '0'; + nlOll01lO <= '0'; + nlOll01Oi <= '0'; + nlOll01Ol <= '0'; + nlOll01OO <= '0'; + nlOll0O0i <= '0'; + nlOll0O0l <= '0'; + nlOll0O0O <= '0'; + nlOllil0l <= '0'; + nlOllil0O <= '0'; + nlOllilii <= '0'; + nlOllilil <= '0'; + nlOlliliO <= '0'; + nlOllilli <= '0'; + nlOllilll <= '0'; + nlOllillO <= '0'; + nlOllilOi <= '0'; + nlOllilOl <= '0'; + nlOllilOO <= '0'; + nlOlliO0i <= '0'; + nlOlliO0l <= '0'; + nlOlliO0O <= '0'; + nlOlliO1i <= '0'; + nlOlliO1l <= '0'; + nlOlliO1O <= '0'; + nlOlliOii <= '0'; + nlOlliOil <= '0'; + nlOlliOiO <= '0'; + nlOlliOli <= '0'; + nlOlliOll <= '0'; + nlOlliOlO <= '0'; + nlOlliOOi <= '0'; + nlOlliOOl <= '0'; + nlOlliOOO <= '0'; + nlOllll0l <= '0'; + nlOllll0O <= '0'; + nlOllllil <= '0'; + nlOllO0iO <= '0'; + nlOllOliO <= '0'; + nlOllOlli <= '0'; + nlOllOlll <= '0'; + nlOllOllO <= '0'; + nlOllOlOi <= '0'; + nlOllOlOl <= '0'; + nlOllOlOO <= '0'; + nlOllOO1i <= '0'; + nlOlO010i <= '0'; + nlOlO010l <= '0'; + nlOlO011i <= '0'; + nlOlO011l <= '0'; + nlOlO011O <= '0'; + nlOlO0lOO <= '0'; + nlOlO10ii <= '0'; + nlOlO10il <= '0'; + nlOlO10iO <= '0'; + nlOlO1ilO <= '0'; + nlOlO1iOi <= '0'; + nlOlO1iOl <= '0'; + nlOlO1iOO <= '0'; + nlOlO1l0i <= '0'; + nlOlO1l1i <= '0'; + nlOlO1l1l <= '0'; + nlOlO1l1O <= '0'; + nlOlO1OOO <= '0'; + nlOlOi00i <= '0'; + nlOlOi00l <= '0'; + nlOlOi01i <= '0'; + nlOlOi01l <= '0'; + nlOlOi01O <= '0'; + nlOlOi1Oi <= '0'; + nlOlOi1Ol <= '0'; + nlOlOi1OO <= '0'; + nlOlOil0i <= '0'; + nlOlOil0l <= '0'; + nlOlOil0O <= '0'; + nlOlOil1i <= '0'; + nlOlOil1l <= '0'; + nlOlOil1O <= '0'; + nlOlOilii <= '0'; + nlOlOilil <= '0'; + nlOlOiliO <= '0'; + nlOlOilli <= '0'; + nlOlOillO <= '0'; + nlOlOilOi <= '0'; + nlOlOilOl <= '0'; + nlOlOiO1i <= '0'; + nlOlOiO1l <= '0'; + nlOlOiO1O <= '0'; + nlOO0000i <= '0'; + nlOO0000l <= '0'; + nlOO0000O <= '0'; + nlOO0001i <= '0'; + nlOO0001l <= '0'; + nlOO0001O <= '0'; + nlOO000ii <= '0'; + nlOO000il <= '0'; + nlOO000iO <= '0'; + nlOO000li <= '0'; + nlOO000ll <= '0'; + nlOO000lO <= '0'; + nlOO000Oi <= '0'; + nlOO000Ol <= '0'; + nlOO000OO <= '0'; + nlOO0010i <= '0'; + nlOO0010l <= '0'; + nlOO0010O <= '0'; + nlOO0011i <= '0'; + nlOO0011l <= '0'; + nlOO0011O <= '0'; + nlOO001ii <= '0'; + nlOO001il <= '0'; + nlOO001iO <= '0'; + nlOO001li <= '0'; + nlOO001ll <= '0'; + nlOO001lO <= '0'; + nlOO001Oi <= '0'; + nlOO001Ol <= '0'; + nlOO001OO <= '0'; + nlOO00i0i <= '0'; + nlOO00i0l <= '0'; + nlOO00i0O <= '0'; + nlOO00i1i <= '0'; + nlOO00i1l <= '0'; + nlOO00i1O <= '0'; + nlOO00iii <= '0'; + nlOO00iil <= '0'; + nlOO00iiO <= '0'; + nlOO00ili <= '0'; + nlOO00ill <= '0'; + nlOO00ilO <= '0'; + nlOO00iOi <= '0'; + nlOO00iOl <= '0'; + nlOO00iOO <= '0'; + nlOO00l0i <= '0'; + nlOO00l0l <= '0'; + nlOO00l0O <= '0'; + nlOO00l1i <= '0'; + nlOO00l1l <= '0'; + nlOO00l1O <= '0'; + nlOO00lii <= '0'; + nlOO00lil <= '0'; + nlOO00liO <= '0'; + nlOO00lli <= '0'; + nlOO00lll <= '0'; + nlOO00llO <= '0'; + nlOO00lOi <= '0'; + nlOO00lOl <= '0'; + nlOO00lOO <= '0'; + nlOO00O0i <= '0'; + nlOO00O0l <= '0'; + nlOO00O0O <= '0'; + nlOO00O1i <= '0'; + nlOO00O1l <= '0'; + nlOO00O1O <= '0'; + nlOO00Oii <= '0'; + nlOO00Oil <= '0'; + nlOO00OiO <= '0'; + nlOO00Oli <= '0'; + nlOO00Oll <= '0'; + nlOO00OlO <= '0'; + nlOO00OOi <= '0'; + nlOO00OOl <= '0'; + nlOO00OOO <= '0'; + nlOO0100l <= '0'; + nlOO0100O <= '0'; + nlOO010ii <= '0'; + nlOO010il <= '0'; + nlOO010iO <= '0'; + nlOO010li <= '0'; + nlOO010ll <= '0'; + nlOO010lO <= '0'; + nlOO010Oi <= '0'; + nlOO010Ol <= '0'; + nlOO010OO <= '0'; + nlOO01i0i <= '0'; + nlOO01i0l <= '0'; + nlOO01i0O <= '0'; + nlOO01i1i <= '0'; + nlOO01i1l <= '0'; + nlOO01i1O <= '0'; + nlOO01iii <= '0'; + nlOO01iil <= '0'; + nlOO01iiO <= '0'; + nlOO01ili <= '0'; + nlOO01ill <= '0'; + nlOO01ilO <= '0'; + nlOO01iOi <= '0'; + nlOO01iOl <= '0'; + nlOO01iOO <= '0'; + nlOO01l0i <= '0'; + nlOO01l0l <= '0'; + nlOO01l0O <= '0'; + nlOO01l1i <= '0'; + nlOO01l1l <= '0'; + nlOO01l1O <= '0'; + nlOO01lii <= '0'; + nlOO01lil <= '0'; + nlOO01liO <= '0'; + nlOO01lli <= '0'; + nlOO01lll <= '0'; + nlOO01llO <= '0'; + nlOO01lOi <= '0'; + nlOO01lOl <= '0'; + nlOO01lOO <= '0'; + nlOO01O0i <= '0'; + nlOO01O0l <= '0'; + nlOO01O0O <= '0'; + nlOO01O1i <= '0'; + nlOO01O1l <= '0'; + nlOO01O1O <= '0'; + nlOO01Oii <= '0'; + nlOO01Oil <= '0'; + nlOO01OiO <= '0'; + nlOO01Oli <= '0'; + nlOO01Oll <= '0'; + nlOO01OlO <= '0'; + nlOO01OOi <= '0'; + nlOO01OOl <= '0'; + nlOO01OOO <= '0'; + nlOO0i00i <= '0'; + nlOO0i00l <= '0'; + nlOO0i00O <= '0'; + nlOO0i01i <= '0'; + nlOO0i01l <= '0'; + nlOO0i01O <= '0'; + nlOO0i0ii <= '0'; + nlOO0i0il <= '0'; + nlOO0i0iO <= '0'; + nlOO0i0li <= '0'; + nlOO0i0ll <= '0'; + nlOO0i0lO <= '0'; + nlOO0i0Oi <= '0'; + nlOO0i0Ol <= '0'; + nlOO0i0OO <= '0'; + nlOO0i10i <= '0'; + nlOO0i10l <= '0'; + nlOO0i10O <= '0'; + nlOO0i11i <= '0'; + nlOO0i11l <= '0'; + nlOO0i11O <= '0'; + nlOO0i1ii <= '0'; + nlOO0i1il <= '0'; + nlOO0i1iO <= '0'; + nlOO0i1li <= '0'; + nlOO0i1ll <= '0'; + nlOO0i1lO <= '0'; + nlOO0i1Oi <= '0'; + nlOO0i1Ol <= '0'; + nlOO0i1OO <= '0'; + nlOO0ii0i <= '0'; + nlOO0ii0l <= '0'; + nlOO0ii0O <= '0'; + nlOO0ii1i <= '0'; + nlOO0ii1l <= '0'; + nlOO0ii1O <= '0'; + nlOO0iiii <= '0'; + nlOO0iiil <= '0'; + nlOO0iiiO <= '0'; + nlOO0iili <= '0'; + nlOO0iill <= '0'; + nlOO0iilO <= '0'; + nlOO0iiOi <= '0'; + nlOO0iiOl <= '0'; + nlOO0iiOO <= '0'; + nlOO0il0i <= '0'; + nlOO0il0l <= '0'; + nlOO0il0O <= '0'; + nlOO0il1i <= '0'; + nlOO0il1l <= '0'; + nlOO0il1O <= '0'; + nlOO0ilii <= '0'; + nlOO0ilil <= '0'; + nlOO0iliO <= '0'; + nlOO0illi <= '0'; + nlOO0illl <= '0'; + nlOO0illO <= '0'; + nlOO0ilOi <= '0'; + nlOO10Oli <= '0'; + nlOO1i10O <= '0'; + nlOO1i1ii <= '0'; + nlOO1i1il <= '0'; + nlOO1i1iO <= '0'; + nlOO1i1li <= '0'; + nlOO1i1ll <= '0'; + nlOO1i1lO <= '0'; + nlOO1i1Oi <= '0'; + nlOO1O10O <= '0'; + nlOO1O1ii <= '0'; + nlOO1O1il <= '0'; + nlOO1O1iO <= '0'; + nlOO1O1li <= '0'; + nlOO1O1ll <= '0'; + nlOO1O1lO <= '0'; + nlOO1O1Oi <= '0'; + nlOO1O1Ol <= '0'; + nlOO1O1OO <= '0'; + nlOOO0OlO <= '0'; + nlOOO0OOi <= '0'; + nlOOO0OOl <= '0'; + nlOOO0OOO <= '0'; + nlOOOi00i <= '0'; + nlOOOi00l <= '0'; + nlOOOi00O <= '0'; + nlOOOi01i <= '0'; + nlOOOi01l <= '0'; + nlOOOi01O <= '0'; + nlOOOi0ii <= '0'; + nlOOOi0il <= '0'; + nlOOOi0iO <= '0'; + nlOOOi0li <= '0'; + nlOOOi0ll <= '0'; + nlOOOi0lO <= '0'; + nlOOOi0Oi <= '0'; + nlOOOi0Ol <= '0'; + nlOOOi0OO <= '0'; + nlOOOi10i <= '0'; + nlOOOi10l <= '0'; + nlOOOi10O <= '0'; + nlOOOi11i <= '0'; + nlOOOi11l <= '0'; + nlOOOi11O <= '0'; + nlOOOi1ii <= '0'; + nlOOOi1il <= '0'; + nlOOOi1iO <= '0'; + nlOOOi1li <= '0'; + nlOOOi1ll <= '0'; + nlOOOi1lO <= '0'; + nlOOOi1Oi <= '0'; + nlOOOi1Ol <= '0'; + nlOOOi1OO <= '0'; + nlOOOii0i <= '0'; + nlOOOii0l <= '0'; + nlOOOii0O <= '0'; + nlOOOii1i <= '0'; + nlOOOii1l <= '0'; + nlOOOii1O <= '0'; + nlOOOiiii <= '0'; + nlOOOiiil <= '0'; + nlOOOiiiO <= '0'; + nlOOOiili <= '0'; + nlOOOiill <= '0'; + nlOOOiilO <= '0'; + nlOOOiiOi <= '0'; + nlOOOiiOl <= '0'; + nlOOOiiOO <= '0'; + nlOOOil0i <= '0'; + nlOOOil0l <= '0'; + nlOOOil0O <= '0'; + nlOOOil1i <= '0'; + nlOOOil1l <= '0'; + nlOOOil1O <= '0'; + nlOOOilii <= '0'; + nlOOOilil <= '0'; + nlOOOiliO <= '0'; + nlOOOilli <= '0'; + nlOOOilll <= '0'; + nlOOOillO <= '0'; + nlOOOilOi <= '0'; + nlOOOilOl <= '0'; + nlOOOilOO <= '0'; + nlOOOiO0i <= '0'; + nlOOOiO0l <= '0'; + nlOOOiO0O <= '0'; + nlOOOiO1i <= '0'; + nlOOOiO1l <= '0'; + nlOOOiO1O <= '0'; + nlOOOiOii <= '0'; + nlOOOiOil <= '0'; + nlOOOiOiO <= '0'; + nlOOOiOli <= '0'; + nlOOOiOll <= '0'; + nlOOOiOlO <= '0'; + nlOOOiOOi <= '0'; + nlOOOiOOl <= '0'; + nlOOOiOOO <= '0'; + nlOOOl00i <= '0'; + nlOOOl01i <= '0'; + nlOOOl01l <= '0'; + nlOOOl01O <= '0'; + nlOOOl10i <= '0'; + nlOOOl10l <= '0'; + nlOOOl10O <= '0'; + nlOOOl11i <= '0'; + nlOOOl11l <= '0'; + nlOOOl11O <= '0'; + nlOOOl1ii <= '0'; + nlOOOl1il <= '0'; + nlOOOl1iO <= '0'; + nlOOOl1li <= '0'; + nlOOOl1ll <= '0'; + nlOOOl1lO <= '0'; + nlOOOl1Oi <= '0'; + nlOOOl1Ol <= '0'; + nlOOOl1OO <= '0'; + ELSIF (phy_clk = '1' AND phy_clk'event) THEN + n000i00i <= wire_n000ii0O_dataout; + n000i01i <= wire_n000ii1O_dataout; + n000i01l <= wire_n000ii0i_dataout; + n000i01O <= wire_n000ii0l_dataout; + n000i10i <= wire_n000i00O_dataout; + n000i10l <= wire_n000i0ii_dataout; + n000i10O <= wire_n000i0il_dataout; + n000i1ii <= wire_n000i0iO_dataout; + n000i1il <= wire_n000i0li_dataout; + n000i1iO <= wire_n000i0ll_dataout; + n000i1li <= wire_n000i0lO_dataout; + n000i1ll <= wire_n000i0Oi_dataout; + n000i1lO <= wire_n000i0Ol_dataout; + n000i1Oi <= wire_n000i0OO_dataout; + n000i1Ol <= wire_n000ii1i_dataout; + n000i1OO <= wire_n000ii1l_dataout; + n000lilO <= wire_n000lOiO_dataout; + n000llil <= wire_n000lOli_dataout; + n000lliO <= wire_n000lOll_dataout; + n000llli <= wire_n000lOlO_dataout; + n000llll <= wire_n000lOOi_dataout; + n000lllO <= wire_n000lOOl_dataout; + n000llOi <= wire_n000lOOO_dataout; + n000llOl <= wire_n000O11i_dataout; + n000llOO <= wire_n000O11l_dataout; + n000lO0i <= wire_n000O10O_dataout; + n000lO0l <= wire_n000O1ii_dataout; + n000lO0O <= wire_n000O1il_dataout; + n000lO1i <= wire_n000O11O_dataout; + n000lO1l <= wire_n000O10i_dataout; + n000lO1O <= wire_n000O10l_dataout; + n000lOii <= wire_n000O1iO_dataout; + n000lOil <= wire_n000OiOi_dataout; + n00100ii <= wire_n00100lO_dataout; + n00100il <= wire_n00100Oi_dataout; + n00100iO <= wire_n00100Ol_dataout; + n00100li <= wire_n0010l0l_dataout; + n0010ili <= wire_n0010l0O_dataout; + n0010ill <= wire_n0010lii_dataout; + n0010ilO <= wire_n0010lil_dataout; + n0010iOi <= wire_n0010liO_dataout; + n0010iOl <= wire_n0010lli_dataout; + n0010iOO <= wire_n0010lll_dataout; + n0010l0i <= wire_n001i1il_dataout; + n0010l1i <= wire_n0010llO_dataout; + n0010l1l <= wire_n0010lOi_dataout; + n0010l1O <= wire_n0010lOl_dataout; + n001i10i <= wire_n001i1lO_dataout; + n001i10l <= wire_n001i1Oi_dataout; + n001i10O <= wire_n001i1Ol_dataout; + n001i11i <= wire_n001i1iO_dataout; + n001i11l <= wire_n001i1li_dataout; + n001i11O <= wire_n001i1ll_dataout; + n001iilO <= wire_n001iOiO_dataout; + n001iiOi <= wire_n001iOli_dataout; + n001iiOl <= wire_n001iOll_dataout; + n001iiOO <= wire_n001iOlO_dataout; + n001il0i <= wire_n001l11i_dataout; + n001il0l <= wire_n001l11l_dataout; + n001il0O <= wire_n001l11O_dataout; + n001il1i <= wire_n001iOOi_dataout; + n001il1l <= wire_n001iOOl_dataout; + n001il1O <= wire_n001iOOO_dataout; + n001ilii <= wire_n001l10i_dataout; + n001ilil <= wire_n001l10l_dataout; + n001iliO <= wire_n001l10O_dataout; + n001illi <= wire_n001l1ii_dataout; + n001illl <= wire_n001l1il_dataout; + n001illO <= wire_n001l1iO_dataout; + n001ilOi <= wire_n001l1li_dataout; + n001ilOl <= wire_n001l1ll_dataout; + n001ilOO <= wire_n001l1lO_dataout; + n001iO0i <= wire_n001l01i_dataout; + n001iO0l <= wire_n001l01l_dataout; + n001iO0O <= wire_n001l00i_dataout; + n001iO1i <= wire_n001l1Oi_dataout; + n001iO1l <= wire_n001l1Ol_dataout; + n001iO1O <= wire_n001l1OO_dataout; + n001iOii <= wire_n001l01O_dataout; + n001ll1O <= wire_n000i00l_dataout; + n00i100i <= wire_n00i1i0l_dataout; + n00i100l <= wire_n00i1i0O_dataout; + n00i100O <= wire_n00i1iii_dataout; + n00i101l <= wire_n00i1i1O_dataout; + n00i101O <= wire_n00i1i0i_dataout; + n00i10ii <= wire_n00i1iil_dataout; + n00i10il <= wire_n00i1iiO_dataout; + n00i10iO <= wire_n00i1ili_dataout; + n00i10li <= wire_n00i1ill_dataout; + n00i10ll <= wire_n00i1ilO_dataout; + n00i10lO <= wire_n00i1iOi_dataout; + n00i10Oi <= wire_n00i1iOl_dataout; + n00i10Ol <= wire_n00i1iOO_dataout; + n00i10OO <= wire_n00i1l1i_dataout; + n00i110O <= wire_n00i1i1l_dataout; + n00i1i1i <= wire_n00i1l1l_dataout; + n00iii0i <= wire_n00iiiiO_dataout; + n00iii0l <= wire_n00iilll_dataout; + n00iii1l <= wire_n00iiiii_dataout; + n00iii1O <= wire_n00iiiil_dataout; + n00iiiOi <= wire_n00iii0O_dataout; + n00iilii <= wire_n00iillO_dataout; + n00iilil <= wire_n00iilOi_dataout; + n00iiliO <= wire_n00iilOl_dataout; + n00iilli <= wire_n00il01i_dataout; + n00il1li <= wire_n00il01l_dataout; + n00il1OO <= wire_n00iO01l_dataout; + n00ill0i <= wire_n00iO00O_dataout; + n00ill0l <= wire_n00iO0ii_dataout; + n00ill0O <= wire_n00iO0il_dataout; + n00ill1i <= wire_n00iO01O_dataout; + n00ill1l <= wire_n00iO00i_dataout; + n00ill1O <= wire_n00iO00l_dataout; + n00illii <= wire_n00iO0iO_dataout; + n00illil <= wire_n00iO0li_dataout; + n00illiO <= wire_n00iO0ll_dataout; + n00illli <= wire_n00iO0lO_dataout; + n00illll <= wire_n00iO0Oi_dataout; + n00illlO <= wire_n00iO0Ol_dataout; + n00illOi <= wire_n00iO0OO_dataout; + n00illOl <= wire_n00iOi1i_dataout; + n00illOO <= wire_n00iOi1l_dataout; + n00ilO0i <= wire_n00iOi0O_dataout; + n00ilO0l <= wire_n00iOiii_dataout; + n00ilO0O <= wire_n00iOiil_dataout; + n00ilO1i <= wire_n00iOi1O_dataout; + n00ilO1l <= wire_n00iOi0i_dataout; + n00ilO1O <= wire_n00iOi0l_dataout; + n00ilOii <= wire_n00iOiiO_dataout; + n00ilOil <= wire_n00iOili_dataout; + n00ilOiO <= wire_n00iOill_dataout; + n00ilOli <= wire_n00iOilO_dataout; + n00ilOll <= wire_n00iOiOi_dataout; + n00ilOlO <= wire_n00iOiOl_dataout; + n00ilOOi <= wire_n00iOiOO_dataout; + n00ilOOl <= wire_n00iOl1i_dataout; + n00ilOOO <= wire_n00iOl1l_dataout; + n00iO01i <= wire_n00l0OOl_dataout; + n00iO10i <= wire_n00iOl0O_dataout; + n00iO10l <= wire_n00iOlii_dataout; + n00iO10O <= wire_n00iOlil_dataout; + n00iO11i <= wire_n00iOl1O_dataout; + n00iO11l <= wire_n00iOl0i_dataout; + n00iO11O <= wire_n00iOl0l_dataout; + n00iO1ii <= wire_n00iOliO_dataout; + n00iO1il <= wire_n00iOlli_dataout; + n00iO1iO <= wire_n00iOlll_dataout; + n00iO1li <= wire_n00iOllO_dataout; + n00iO1ll <= wire_n00iOlOi_dataout; + n00iO1lO <= wire_n00iOlOl_dataout; + n00iO1Oi <= wire_n00iOlOO_dataout; + n00iO1Ol <= wire_n00iOO1i_dataout; + n00iO1OO <= wire_n00iOO1l_dataout; + n00l0i0i <= wire_n00li11O_dataout; + n00l0i0l <= wire_n00li10i_dataout; + n00l0i0O <= wire_n00li10l_dataout; + n00l0i1i <= wire_n00l0OOO_dataout; + n00l0i1l <= wire_n00li11i_dataout; + n00l0i1O <= wire_n00li11l_dataout; + n00l0iii <= wire_n00li10O_dataout; + n00l0iil <= wire_n00li1ii_dataout; + n00l0iiO <= wire_n00li1il_dataout; + n00l0ili <= wire_n00li1iO_dataout; + n00l0ill <= wire_n00li1li_dataout; + n00l0ilO <= wire_n00li1ll_dataout; + n00l0iOi <= wire_n00li1lO_dataout; + n00l0iOl <= wire_n00li1Oi_dataout; + n00l0iOO <= wire_n00li1Ol_dataout; + n00l0l0i <= wire_n00li01O_dataout; + n00l0l0l <= wire_n00li00i_dataout; + n00l0l0O <= wire_n00li00l_dataout; + n00l0l1i <= wire_n00li1OO_dataout; + n00l0l1l <= wire_n00li01i_dataout; + n00l0l1O <= wire_n00li01l_dataout; + n00l0lii <= wire_n00li00O_dataout; + n00l0lil <= wire_n00li0ii_dataout; + n00l0liO <= wire_n00li0il_dataout; + n00l0lli <= wire_n00li0iO_dataout; + n00l0lll <= wire_n00li0li_dataout; + n00l0llO <= wire_n00li0ll_dataout; + n00l0lOi <= wire_n00li0lO_dataout; + n00l0lOl <= wire_n00li0Oi_dataout; + n00l0lOO <= wire_n00li0Ol_dataout; + n00l0O0i <= wire_n00lii1O_dataout; + n00l0O0l <= wire_n00lii0i_dataout; + n00l0O0O <= wire_n00lii0l_dataout; + n00l0O1i <= wire_n00li0OO_dataout; + n00l0O1l <= wire_n00lii1i_dataout; + n00l0O1O <= wire_n00lii1l_dataout; + n00l0Oii <= wire_n00lii0O_dataout; + n00l0Oil <= wire_n00liiii_dataout; + n00l0OOi <= wire_n00llOOO_dataout; + n00llOll <= wire_n00lO11i_dataout; + n00llOlO <= wire_n00lO11l_dataout; + n00llOOi <= wire_n00lO11O_dataout; + n00llOOl <= wire_n00lO0iO_dataout; + n00lO00i <= wire_n00lO0OO_dataout; + n00lO00l <= wire_n00lOi1i_dataout; + n00lO00O <= wire_n00lOi1l_dataout; + n00lO01i <= wire_n00lO0lO_dataout; + n00lO01l <= wire_n00lO0Oi_dataout; + n00lO01O <= wire_n00lO0Ol_dataout; + n00lO0ii <= wire_n00lOi1O_dataout; + n00lO0il <= wire_n00lOllO_dataout; + n00lO1Ol <= wire_n00lO0li_dataout; + n00lO1OO <= wire_n00lO0ll_dataout; + n00lOl0l <= wire_n00lOlOi_dataout; + n00lOl0O <= wire_n00lOlOl_dataout; + n00lOlii <= wire_n00lOlOO_dataout; + n00lOlil <= wire_n00lOO1i_dataout; + n00lOliO <= wire_n00lOO1l_dataout; + n00lOlli <= wire_n00lOO1O_dataout; + n00O00ii <= wire_n00OOOiO_dataout; + n00O100i <= wire_n00O1l1i_dataout; + n00O100l <= wire_n00O1l1l_dataout; + n00O100O <= wire_n00O1l1O_dataout; + n00O101i <= wire_n00O1iOi_dataout; + n00O101l <= wire_n00O1iOl_dataout; + n00O101O <= wire_n00O1iOO_dataout; + n00O10ii <= wire_n00O1l0i_dataout; + n00O10il <= wire_n00O1l0l_dataout; + n00O10iO <= wire_n00O1l0O_dataout; + n00O10li <= wire_n00O1lii_dataout; + n00O10ll <= wire_n00O1lil_dataout; + n00O10lO <= wire_n00O1liO_dataout; + n00O10Oi <= wire_n00O1lli_dataout; + n00O10Ol <= wire_n00O1lll_dataout; + n00O10OO <= wire_n00O1llO_dataout; + n00O1i0i <= wire_n00O1O1i_dataout; + n00O1i0l <= wire_n00O1O1l_dataout; + n00O1i0O <= wire_n00O1O1O_dataout; + n00O1i1i <= wire_n00O1lOi_dataout; + n00O1i1l <= wire_n00O1lOl_dataout; + n00O1i1O <= wire_n00O1lOO_dataout; + n00O1iii <= wire_n00O1O0i_dataout; + n00O1iil <= wire_n00O1O0l_dataout; + n00O1iiO <= wire_n00O1O0O_dataout; + n00O1ili <= wire_n00O1Oil_dataout; + n00O1ill <= wire_n00O1Oii_dataout; + n00OOlil <= wire_n00OOOli_dataout; + n00OOliO <= wire_n00OOOll_dataout; + n00OOlli <= wire_n00OOOlO_dataout; + n00OOlll <= wire_n00OOOOi_dataout; + n00OOllO <= wire_n00OOOOl_dataout; + n00OOlOi <= wire_n00OOOOO_dataout; + n00OOlOl <= wire_n0i1111i_dataout; + n00OOlOO <= wire_n0i1111l_dataout; + n00OOO0i <= wire_n0i1110O_dataout; + n00OOO0l <= wire_n0i111ii_dataout; + n00OOO0O <= wire_n0i111il_dataout; + n00OOO1i <= wire_n0i1111O_dataout; + n00OOO1l <= wire_n0i1110i_dataout; + n00OOO1O <= wire_n0i1110l_dataout; + n00OOOii <= wire_n0i111iO_dataout; + n00OOOil <= wire_n0i111li_dataout; + n010000i <= wire_n0100O1O_dataout; + n010000l <= wire_n0100O0i_dataout; + n010000O <= wire_n0100O0l_dataout; + n010001i <= wire_n0100lOO_dataout; + n010001l <= wire_n0100O1i_dataout; + n010001O <= wire_n0100O1l_dataout; + n01000ii <= wire_n0100O0O_dataout; + n01000il <= wire_n0100Oii_dataout; + n01000iO <= wire_n0100Oil_dataout; + n01000li <= wire_n0100OiO_dataout; + n01000ll <= wire_n0100Oli_dataout; + n01000lO <= wire_n0100Oll_dataout; + n01000Oi <= wire_n0100OlO_dataout; + n01000Ol <= wire_n0100OOi_dataout; + n01000OO <= wire_n0100OOl_dataout; + n01001il <= wire_n0100lii_dataout; + n01001iO <= wire_n0100lil_dataout; + n01001li <= wire_n0100liO_dataout; + n01001ll <= wire_n0100lli_dataout; + n01001lO <= wire_n0100lll_dataout; + n01001Oi <= wire_n0100llO_dataout; + n01001Ol <= wire_n0100lOi_dataout; + n01001OO <= wire_n0100lOl_dataout; + n0100i0i <= wire_n010i11O_dataout; + n0100i0l <= wire_n010i10i_dataout; + n0100i0O <= wire_n010i10l_dataout; + n0100i1i <= wire_n0100OOO_dataout; + n0100i1l <= wire_n010i11i_dataout; + n0100i1O <= wire_n010i11l_dataout; + n0100iii <= wire_n010i10O_dataout; + n0100iil <= wire_n010i1ii_dataout; + n0100iiO <= wire_n010i1il_dataout; + n0100ili <= wire_n010i1iO_dataout; + n0100ill <= wire_n010i1li_dataout; + n0100ilO <= wire_n010i1ll_dataout; + n0100iOi <= wire_n010i1lO_dataout; + n0100iOl <= wire_n010i1Oi_dataout; + n0100iOO <= wire_n010i1Ol_dataout; + n0100l0l <= wire_n010llii_dataout; + n010ll0i <= wire_n010lliO_dataout; + n010ll0l <= wire_n010llli_dataout; + n010ll0O <= wire_n010O11i_dataout; + n010ll1O <= wire_n010llil_dataout; + n010lO0O <= wire_n010O11l_dataout; + n010lOii <= wire_n010O11O_dataout; + n010lOil <= wire_n010O10i_dataout; + n010lOiO <= wire_n010O10l_dataout; + n010lOli <= wire_n010O10O_dataout; + n010lOll <= wire_n010O1ii_dataout; + n010lOlO <= wire_n010O1il_dataout; + n010lOOi <= wire_n010O1iO_dataout; + n010lOOl <= wire_n010O1li_dataout; + n010lOOO <= wire_n010Oi0i_dataout; + n010O0lO <= wire_n010Oi0l_dataout; + n010O0Oi <= wire_n010Oi0O_dataout; + n010O0Ol <= wire_n010Oiii_dataout; + n010O0OO <= wire_n010Oiil_dataout; + n010Oi1i <= wire_n010OiiO_dataout; + n010Oi1l <= wire_n010Oili_dataout; + n010OOil <= wire_n01i100l_dataout; + n010OOiO <= wire_n01i100O_dataout; + n010OOli <= wire_n01i10ii_dataout; + n010OOll <= wire_n01i10il_dataout; + n010OOlO <= wire_n01i10iO_dataout; + n010OOOi <= wire_n01i10li_dataout; + n010OOOl <= wire_n01i10ll_dataout; + n010OOOO <= wire_n01i10lO_dataout; + n011110i <= wire_n011100l_dataout; + n011110l <= wire_n011100O_dataout; + n011110O <= wire_n01110ii_dataout; + n011111i <= wire_n011101l_dataout; + n011111l <= wire_n011101O_dataout; + n011111O <= wire_n011100i_dataout; + n01111ii <= wire_n01110il_dataout; + n01111il <= wire_n01110iO_dataout; + n011i00l <= wire_n011i1Oi_dataout; + n011i0Ol <= wire_n011ii0i_dataout; + n011i0OO <= wire_n011ii0l_dataout; + n011i1iO <= wire_n011i1Ol_dataout; + n011i1li <= wire_n011i1OO_dataout; + n011i1ll <= wire_n011i01i_dataout; + n011i1lO <= wire_n011ii1O_dataout; + n011ii1i <= wire_n011ii0O_dataout; + n011ii1l <= wire_n011iOil_dataout; + n011iO1l <= wire_n011iOiO_dataout; + n011iOii <= wire_n011lOiO_dataout; + n011l0il <= wire_n011lOli_dataout; + n011l0iO <= wire_n011lOll_dataout; + n011l0li <= wire_n011lOlO_dataout; + n011l0ll <= wire_n011lOOi_dataout; + n011l0lO <= wire_n011lOOl_dataout; + n011l0Oi <= wire_n011lOOO_dataout; + n011l0Ol <= wire_n011O11i_dataout; + n011l0OO <= wire_n011O11l_dataout; + n011li0i <= wire_n011O10O_dataout; + n011li0l <= wire_n011O1ii_dataout; + n011li0O <= wire_n011O1il_dataout; + n011li1i <= wire_n011O11O_dataout; + n011li1l <= wire_n011O10i_dataout; + n011li1O <= wire_n011O10l_dataout; + n011liii <= wire_n011O1iO_dataout; + n011liil <= wire_n011O1li_dataout; + n011liiO <= wire_n011O1ll_dataout; + n011lili <= wire_n011O1lO_dataout; + n011lill <= wire_n011O1Oi_dataout; + n011lilO <= wire_n011O1Ol_dataout; + n011liOi <= wire_n011O1OO_dataout; + n011liOl <= wire_n011O01i_dataout; + n011liOO <= wire_n011O01l_dataout; + n011ll0i <= wire_n011O00O_dataout; + n011ll0l <= wire_n011O0ii_dataout; + n011ll0O <= wire_n011O0il_dataout; + n011ll1i <= wire_n011O01O_dataout; + n011ll1l <= wire_n011O00i_dataout; + n011ll1O <= wire_n011O00l_dataout; + n011llii <= wire_n011O0iO_dataout; + n011llil <= wire_n011O0li_dataout; + n011lliO <= wire_n011O0ll_dataout; + n011llli <= wire_n011O0lO_dataout; + n011llll <= wire_n011O0Oi_dataout; + n011lllO <= wire_n011O0Ol_dataout; + n011llOi <= wire_n011O0OO_dataout; + n011llOl <= wire_n011Oi1i_dataout; + n011llOO <= wire_n011Oi1l_dataout; + n011lO0i <= wire_n011Oi0O_dataout; + n011lO0l <= wire_n011Oiii_dataout; + n011lO0O <= wire_n011Oiil_dataout; + n011lO1i <= wire_n011Oi1O_dataout; + n011lO1l <= wire_n011Oi0i_dataout; + n011lO1O <= wire_n011Oi0l_dataout; + n011lOii <= wire_n011OiiO_dataout; + n011lOil <= wire_n0100l0O_dataout; + n01i101i <= wire_n01i1iOi_dataout; + n01i101l <= wire_n01i1iOO_dataout; + n01i101O <= wire_n01i1iOl_dataout; + n01i110i <= wire_n01i1i1i_dataout; + n01i110l <= wire_n01i1i1l_dataout; + n01i110O <= wire_n01i1i1O_dataout; + n01i111i <= wire_n01i10Oi_dataout; + n01i111l <= wire_n01i10Ol_dataout; + n01i111O <= wire_n01i10OO_dataout; + n01i11ii <= wire_n01i1i0i_dataout; + n01i11il <= wire_n01i1i0l_dataout; + n01i11iO <= wire_n01i1i0O_dataout; + n01i11li <= wire_n01i1iii_dataout; + n01i11ll <= wire_n01i1iil_dataout; + n01i11lO <= wire_n01i1iiO_dataout; + n01i11Oi <= wire_n01i1ili_dataout; + n01i11Ol <= wire_n01i1ill_dataout; + n01i11OO <= wire_n01i1ilO_dataout; + n01i1OOl <= wire_n01iOl1i_dataout; + n01iO0OO <= wire_n01iOl1l_dataout; + n01iOi0i <= wire_n01iOl0O_dataout; + n01iOi0l <= wire_n01iOlii_dataout; + n01iOi0O <= wire_n01iOlil_dataout; + n01iOi1i <= wire_n01iOl1O_dataout; + n01iOi1l <= wire_n01iOl0i_dataout; + n01iOi1O <= wire_n01iOl0l_dataout; + n01iOiii <= wire_n01iOliO_dataout; + n01iOiil <= wire_n01iOlli_dataout; + n01iOiiO <= wire_n01iOlll_dataout; + n01iOili <= wire_n01iOllO_dataout; + n01iOill <= wire_n01iOlOi_dataout; + n01iOilO <= wire_n01iOlOl_dataout; + n01iOiOi <= wire_n01iOlOO_dataout; + n01iOiOl <= wire_n01iOO1i_dataout; + n01iOiOO <= wire_n01iOO1l_dataout; + n01l000i <= wire_n01l0OiO_dataout; + n01l001i <= wire_n01l0i1O_dataout; + n01l001l <= wire_n01l0i0i_dataout; + n01l001O <= wire_n01l0i0l_dataout; + n01l010i <= wire_n01l000O_dataout; + n01l010l <= wire_n01l00ii_dataout; + n01l010O <= wire_n01l00il_dataout; + n01l01ii <= wire_n01l00iO_dataout; + n01l01il <= wire_n01l00li_dataout; + n01l01iO <= wire_n01l00ll_dataout; + n01l01li <= wire_n01l00lO_dataout; + n01l01ll <= wire_n01l00Oi_dataout; + n01l01lO <= wire_n01l00Ol_dataout; + n01l01Oi <= wire_n01l00OO_dataout; + n01l01Ol <= wire_n01l0i1i_dataout; + n01l01OO <= wire_n01l0i1l_dataout; + n01l1Oil <= wire_n01l000l_dataout; + n01lii1l <= wire_n01lilOi_dataout; + n01liiOi <= wire_n01lilOl_dataout; + n01liiOl <= wire_n01lilOO_dataout; + n01liiOO <= wire_n01liO1i_dataout; + n01lil0i <= wire_n01liO0l_dataout; + n01lil0l <= wire_n01liO0O_dataout; + n01lil0O <= wire_n01liOii_dataout; + n01lil1i <= wire_n01liO1l_dataout; + n01lil1l <= wire_n01liO1O_dataout; + n01lil1O <= wire_n01liO0i_dataout; + n01lilii <= wire_n01liOil_dataout; + n01lilil <= wire_n01liOiO_dataout; + n01liliO <= wire_n01liOli_dataout; + n01lilli <= wire_n01liOll_dataout; + n01lilll <= wire_n01liOlO_dataout; + n01lillO <= wire_n01liOOi_dataout; + n01lOlOi <= wire_n01lOO1O_dataout; + n01lOlOl <= wire_n01lOO0i_dataout; + n01lOlOO <= wire_n01lOO0l_dataout; + n01lOO1i <= wire_n01O11ii_dataout; + n01lOOiO <= wire_n01lOO1l_dataout; + n01O000i <= wire_n01O0O0O_dataout; + n01O000l <= wire_n01O0Oii_dataout; + n01O000O <= wire_n01O0Oil_dataout; + n01O001i <= wire_n01O0O1O_dataout; + n01O001l <= wire_n01O0O0i_dataout; + n01O001O <= wire_n01O0O0l_dataout; + n01O00ii <= wire_n01O0OiO_dataout; + n01O00il <= wire_n01O0Oli_dataout; + n01O00iO <= wire_n01O0Oll_dataout; + n01O00li <= wire_n01O0OlO_dataout; + n01O00ll <= wire_n01O0OOi_dataout; + n01O00lO <= wire_n01O0OOl_dataout; + n01O00Oi <= wire_n01O0OOO_dataout; + n01O00Ol <= wire_n01Oi11i_dataout; + n01O00OO <= wire_n01Oi11l_dataout; + n01O010i <= wire_n01O0l0O_dataout; + n01O010l <= wire_n01O0lii_dataout; + n01O010O <= wire_n01O0lil_dataout; + n01O011i <= wire_n01O0l1O_dataout; + n01O011l <= wire_n01O0l0i_dataout; + n01O011O <= wire_n01O0l0l_dataout; + n01O01ii <= wire_n01O0liO_dataout; + n01O01il <= wire_n01O0lli_dataout; + n01O01iO <= wire_n01O0lll_dataout; + n01O01li <= wire_n01O0llO_dataout; + n01O01ll <= wire_n01O0lOi_dataout; + n01O01lO <= wire_n01O0lOl_dataout; + n01O01Oi <= wire_n01O0lOO_dataout; + n01O01Ol <= wire_n01O0O1i_dataout; + n01O01OO <= wire_n01O0O1l_dataout; + n01O0i0i <= wire_n01Oi10O_dataout; + n01O0i0l <= wire_n01Oi1ii_dataout; + n01O0i0O <= wire_n01Oi1il_dataout; + n01O0i1i <= wire_n01Oi11O_dataout; + n01O0i1l <= wire_n01Oi10i_dataout; + n01O0i1O <= wire_n01Oi10l_dataout; + n01O0iii <= wire_n01Oi1iO_dataout; + n01O0iil <= wire_n01Oi1li_dataout; + n01O0iiO <= wire_n01Oi1ll_dataout; + n01O0ili <= wire_n01Oi1lO_dataout; + n01O0ill <= wire_n01Oi1Oi_dataout; + n01O0ilO <= wire_n01OO0li_dataout; + n01O110i <= wire_n01O11iO_dataout; + n01O110l <= wire_n01O11li_dataout; + n01O110O <= wire_n01O1ilO_dataout; + n01O111O <= wire_n01O11il_dataout; + n01O1i0O <= wire_n01O1iOi_dataout; + n01O1ill <= wire_n01O0iOi_dataout; + n01O1OlO <= wire_n01O0iOl_dataout; + n01O1OOi <= wire_n01O0iOO_dataout; + n01O1OOl <= wire_n01O0l1i_dataout; + n01O1OOO <= wire_n01O0l1l_dataout; + n01OlllO <= wire_n01OO0ll_dataout; + n01OllOi <= wire_n01OO0lO_dataout; + n01OllOl <= wire_n01OO0Oi_dataout; + n01OllOO <= wire_n01OO0Ol_dataout; + n01OlO0i <= wire_n01OOi1O_dataout; + n01OlO0l <= wire_n01OOi0i_dataout; + n01OlO0O <= wire_n01OOi0l_dataout; + n01OlO1i <= wire_n01OO0OO_dataout; + n01OlO1l <= wire_n01OOi1i_dataout; + n01OlO1O <= wire_n01OOi1l_dataout; + n01OlOii <= wire_n01OOi0O_dataout; + n01OlOil <= wire_n01OOiii_dataout; + n01OlOiO <= wire_n01OOiil_dataout; + n01OlOli <= wire_n01OOiiO_dataout; + n01OlOll <= wire_n01OOili_dataout; + n01OlOlO <= wire_n01OOill_dataout; + n01OlOOi <= wire_n01OOilO_dataout; + n01OlOOl <= wire_n01OOiOi_dataout; + n01OlOOO <= wire_n01OOiOl_dataout; + n01OO00i <= wire_n01OOO1O_dataout; + n01OO01i <= wire_n01OOlOO_dataout; + n01OO01l <= wire_n01OOO1i_dataout; + n01OO01O <= wire_n01OOO1l_dataout; + n01OO0iO <= wire_n00100ll_dataout; + n01OO10i <= wire_n01OOl1O_dataout; + n01OO10l <= wire_n01OOl0i_dataout; + n01OO10O <= wire_n01OOl0l_dataout; + n01OO11i <= wire_n01OOiOO_dataout; + n01OO11l <= wire_n01OOl1i_dataout; + n01OO11O <= wire_n01OOl1l_dataout; + n01OO1ii <= wire_n01OOl0O_dataout; + n01OO1il <= wire_n01OOlii_dataout; + n01OO1iO <= wire_n01OOlil_dataout; + n01OO1li <= wire_n01OOliO_dataout; + n01OO1ll <= wire_n01OOlli_dataout; + n01OO1lO <= wire_n01OOlll_dataout; + n01OO1Oi <= wire_n01OOllO_dataout; + n01OO1Ol <= wire_n01OOlOi_dataout; + n01OO1OO <= wire_n01OOlOl_dataout; + n0i0000l <= wire_n0i00Oii_dataout; + n0i0000O <= wire_n0i00Oil_dataout; + n0i000ii <= wire_n0i00OiO_dataout; + n0i000il <= wire_n0i00Oli_dataout; + n0i000iO <= wire_n0i00Oll_dataout; + n0i000li <= wire_n0i00OlO_dataout; + n0i000ll <= wire_n0i00OOi_dataout; + n0i000lO <= wire_n0i00OOl_dataout; + n0i000Oi <= wire_n0i00OOO_dataout; + n0i000Ol <= wire_n0i0i11i_dataout; + n0i000OO <= wire_n0i0i11l_dataout; + n0i00i0i <= wire_n0i0i10O_dataout; + n0i00i0l <= wire_n0i0i1ii_dataout; + n0i00i0O <= wire_n0i0i1il_dataout; + n0i00i1i <= wire_n0i0i11O_dataout; + n0i00i1l <= wire_n0i0i10i_dataout; + n0i00i1O <= wire_n0i0i10l_dataout; + n0i00iii <= wire_n0i0i1iO_dataout; + n0i00iil <= wire_n0i0i1li_dataout; + n0i00iiO <= wire_n0i0i1ll_dataout; + n0i00ili <= wire_n0i0i1lO_dataout; + n0i00ill <= wire_n0i0i1Oi_dataout; + n0i00ilO <= wire_n0i0i1Ol_dataout; + n0i00iOi <= wire_n0i0i1OO_dataout; + n0i00iOl <= wire_n0i0i01i_dataout; + n0i00iOO <= wire_n0i0i01l_dataout; + n0i00l0i <= wire_n0i0i00O_dataout; + n0i00l0l <= wire_n0i0i0ii_dataout; + n0i00l0O <= wire_n0i0i0il_dataout; + n0i00l1i <= wire_n0i0i01O_dataout; + n0i00l1l <= wire_n0i0i00i_dataout; + n0i00l1O <= wire_n0i0i00l_dataout; + n0i00lii <= wire_n0i0i0iO_dataout; + n0i00lil <= wire_n0i0i0li_dataout; + n0i00liO <= wire_n0i0i0ll_dataout; + n0i00lli <= wire_n0i0i0lO_dataout; + n0i00lll <= wire_n0i0i0Oi_dataout; + n0i00llO <= wire_n0i0i0Ol_dataout; + n0i00lOi <= wire_n0i0i0OO_dataout; + n0i00lOl <= wire_n0i0ii1i_dataout; + n0i00lOO <= wire_n0i0ii1l_dataout; + n0i00O0i <= wire_n0i0ii0O_dataout; + n0i00O0l <= wire_n0i0Ol1O_dataout; + n0i00O1i <= wire_n0i0ii1O_dataout; + n0i00O1l <= wire_n0i0ii0i_dataout; + n0i00O1O <= wire_n0i0ii0l_dataout; + n0i0101l <= wire_n0i011li_dataout; + n0i010ll <= wire_n0i01i1i_dataout; + n0i010lO <= wire_n0i01i1l_dataout; + n0i010Oi <= wire_n0i01i1O_dataout; + n0i010Ol <= wire_n0i01O0l_dataout; + n0i0110O <= wire_n0i011ll_dataout; + n0i011ii <= wire_n0i011lO_dataout; + n0i011il <= wire_n0i011Oi_dataout; + n0i011iO <= wire_n0i010OO_dataout; + n0i01lOl <= wire_n0i01O0O_dataout; + n0i01O0i <= wire_n0i00O0O_dataout; + n0i0O00i <= wire_n0i0OO1O_dataout; + n0i0O00l <= wire_n0i0OO0i_dataout; + n0i0O00O <= wire_n0i0OO0l_dataout; + n0i0O01i <= wire_n0i0OlOO_dataout; + n0i0O01l <= wire_n0i0OO1i_dataout; + n0i0O01O <= wire_n0i0OO1l_dataout; + n0i0O0ii <= wire_n0i0OO0O_dataout; + n0i0O0il <= wire_n0i0OOii_dataout; + n0i0O0iO <= wire_n0i0OOil_dataout; + n0i0O0li <= wire_n0i0OOiO_dataout; + n0i0O0ll <= wire_n0i0OOli_dataout; + n0i0O0lO <= wire_n0i0OOll_dataout; + n0i0O0Oi <= wire_n0i0OOlO_dataout; + n0i0O0Ol <= wire_n0i0OOOi_dataout; + n0i0O0OO <= wire_n0i0OOOl_dataout; + n0i0O10l <= wire_n0i0Ol0i_dataout; + n0i0O10O <= wire_n0i0Ol0l_dataout; + n0i0O1ii <= wire_n0i0Ol0O_dataout; + n0i0O1il <= wire_n0i0Olii_dataout; + n0i0O1iO <= wire_n0i0Olil_dataout; + n0i0O1li <= wire_n0i0OliO_dataout; + n0i0O1ll <= wire_n0i0Olli_dataout; + n0i0O1lO <= wire_n0i0Olll_dataout; + n0i0O1Oi <= wire_n0i0OllO_dataout; + n0i0O1Ol <= wire_n0i0OlOi_dataout; + n0i0O1OO <= wire_n0i0OlOl_dataout; + n0i0Oi0i <= wire_n0ii111O_dataout; + n0i0Oi0l <= wire_n0ii110i_dataout; + n0i0Oi0O <= wire_n0ii110l_dataout; + n0i0Oi1i <= wire_n0i0OOOO_dataout; + n0i0Oi1l <= wire_n0ii111i_dataout; + n0i0Oi1O <= wire_n0ii111l_dataout; + n0i0Oiii <= wire_n0ii110O_dataout; + n0i0Oiil <= wire_n0ii11ii_dataout; + n0i0OiiO <= wire_n0ii11il_dataout; + n0i0Oili <= wire_n0ii11iO_dataout; + n0i0Oill <= wire_n0ii11li_dataout; + n0i0OilO <= wire_n0ii11ll_dataout; + n0i0Ol1l <= wire_n0ii0l0i_dataout; + n0i1001i <= wire_n0i10iOi_dataout; + n0i100lO <= wire_n0i10iOl_dataout; + n0i100Oi <= wire_n0i10iOO_dataout; + n0i100Ol <= wire_n0i10l1i_dataout; + n0i100OO <= wire_n0i10l1l_dataout; + n0i10i0i <= wire_n0i10l0O_dataout; + n0i10i0l <= wire_n0i10lii_dataout; + n0i10i0O <= wire_n0i10lil_dataout; + n0i10i1i <= wire_n0i10l1O_dataout; + n0i10i1l <= wire_n0i10l0i_dataout; + n0i10i1O <= wire_n0i10l0l_dataout; + n0i10iii <= wire_n0i10liO_dataout; + n0i10iil <= wire_n0i10lli_dataout; + n0i10iiO <= wire_n0i10lll_dataout; + n0i10ili <= wire_n0i10llO_dataout; + n0i10ill <= wire_n0i10lOi_dataout; + n0i10ilO <= wire_n0i1i01l_dataout; + n0i1illi <= wire_n0i1l10O_dataout; + n0i1iO0O <= wire_n0i1l1ii_dataout; + n0i1iOii <= wire_n0i1l1il_dataout; + n0i1iOil <= wire_n0i1l1iO_dataout; + n0i1iOiO <= wire_n0i1l1li_dataout; + n0i1iOli <= wire_n0i1l1ll_dataout; + n0i1iOll <= wire_n0i1l1lO_dataout; + n0i1iOlO <= wire_n0i1l1Oi_dataout; + n0i1iOOi <= wire_n0i1l1Ol_dataout; + n0i1iOOl <= wire_n0i1l1OO_dataout; + n0i1iOOO <= wire_n0i1l01i_dataout; + n0i1l10i <= wire_n0i1l00l_dataout; + n0i1l10l <= wire_n0i1l00O_dataout; + n0i1l11i <= wire_n0i1l01l_dataout; + n0i1l11l <= wire_n0i1l01O_dataout; + n0i1l11O <= wire_n0i1l00i_dataout; + n0ii0iOO <= wire_n0ii0l0l_dataout; + n0ii0l1i <= wire_n0ii0l0O_dataout; + n0ii0l1l <= wire_n0ii0lii_dataout; + n0ii0l1O <= wire_n0ii0OOi_dataout; + n0ii0O0i <= wire_n0ii0OOO_dataout; + n0ii0O0l <= wire_n0iii11i_dataout; + n0ii0O0O <= wire_n0iii11l_dataout; + n0ii0O1O <= wire_n0ii0OOl_dataout; + n0ii0Oii <= wire_n0iii11O_dataout; + n0ii0Oil <= wire_n0iii10i_dataout; + n0ii0OiO <= wire_n0iii10l_dataout; + n0ii0Oli <= wire_n0iii10O_dataout; + n0ii0Oll <= wire_n0iii1ii_dataout; + n0ii0OlO <= wire_n0iiii1i_dataout; + n0iii0iO <= wire_n0iiii1l_dataout; + n0iii0li <= wire_n0iiii1O_dataout; + n0iii0ll <= wire_n0iiii0i_dataout; + n0iii0lO <= wire_n0iiii0l_dataout; + n0iii0Oi <= wire_n0iiii0O_dataout; + n0iii0Ol <= wire_n0iiiiii_dataout; + n0iiiO0l <= wire_n0iil01l_dataout; + n0iiiO0O <= wire_n0iil01O_dataout; + n0iiiOii <= wire_n0iil00i_dataout; + n0iiiOil <= wire_n0iil00l_dataout; + n0iiiOiO <= wire_n0iil00O_dataout; + n0iiiOli <= wire_n0iil0ii_dataout; + n0iiiOll <= wire_n0iil0il_dataout; + n0iiiOlO <= wire_n0iil0iO_dataout; + n0iiiOOi <= wire_n0iil0li_dataout; + n0iiiOOl <= wire_n0iil0ll_dataout; + n0iiiOOO <= wire_n0iil0lO_dataout; + n0iil10i <= wire_n0iili1i_dataout; + n0iil10l <= wire_n0iili1l_dataout; + n0iil10O <= wire_n0iili1O_dataout; + n0iil11i <= wire_n0iil0Oi_dataout; + n0iil11l <= wire_n0iil0Ol_dataout; + n0iil11O <= wire_n0iil0OO_dataout; + n0iil1ii <= wire_n0iili0i_dataout; + n0iil1il <= wire_n0iili0l_dataout; + n0iil1iO <= wire_n0iili0O_dataout; + n0iil1li <= wire_n0iiliii_dataout; + n0iil1ll <= wire_n0iiliil_dataout; + n0iil1lO <= wire_n0iiliiO_dataout; + n0iil1Oi <= wire_n0iilili_dataout; + n0iil1Ol <= wire_n0iililO_dataout; + n0iil1OO <= wire_n0iilill_dataout; + n0iilOll <= wire_n0iliiOi_dataout; + n0ili0lO <= wire_n0iliiOl_dataout; + n0ili0Oi <= wire_n0iliiOO_dataout; + n0ili0Ol <= wire_n0ilil1i_dataout; + n0ili0OO <= wire_n0ilil1l_dataout; + n0ilii0i <= wire_n0ilil0O_dataout; + n0ilii0l <= wire_n0ililii_dataout; + n0ilii0O <= wire_n0ililil_dataout; + n0ilii1i <= wire_n0ilil1O_dataout; + n0ilii1l <= wire_n0ilil0i_dataout; + n0ilii1O <= wire_n0ilil0l_dataout; + n0iliiii <= wire_n0ililiO_dataout; + n0iliiil <= wire_n0ililli_dataout; + n0iliiiO <= wire_n0ililll_dataout; + n0iliili <= wire_n0ilillO_dataout; + n0iliill <= wire_n0ililOi_dataout; + n0iliilO <= wire_n0ililOl_dataout; + n0illO0l <= wire_n0ilO01l_dataout; + n0ilO01i <= wire_n0ilOO0O_dataout; + n0ilO10i <= wire_n0ilO00O_dataout; + n0ilO10l <= wire_n0ilO0ii_dataout; + n0ilO10O <= wire_n0ilO0il_dataout; + n0ilO11i <= wire_n0ilO01O_dataout; + n0ilO11l <= wire_n0ilO00i_dataout; + n0ilO11O <= wire_n0ilO00l_dataout; + n0ilO1ii <= wire_n0ilO0iO_dataout; + n0ilO1il <= wire_n0ilO0li_dataout; + n0ilO1iO <= wire_n0ilO0ll_dataout; + n0ilO1li <= wire_n0ilO0lO_dataout; + n0ilO1ll <= wire_n0ilO0Oi_dataout; + n0ilO1lO <= wire_n0ilO0Ol_dataout; + n0ilO1Oi <= wire_n0ilO0OO_dataout; + n0ilO1Ol <= wire_n0ilOi1i_dataout; + n0ilO1OO <= wire_n0ilOi1l_dataout; + n0iO10Ol <= wire_n0iO1lli_dataout; + n0iO1ili <= wire_n0iO1lll_dataout; + n0iO1ill <= wire_n0iO1llO_dataout; + n0iO1ilO <= wire_n0iO1lOi_dataout; + n0iO1iOi <= wire_n0iO1lOl_dataout; + n0iO1iOl <= wire_n0iO1lOO_dataout; + n0iO1iOO <= wire_n0iO1O1i_dataout; + n0iO1l0i <= wire_n0iO1O0l_dataout; + n0iO1l0l <= wire_n0iO1O0O_dataout; + n0iO1l0O <= wire_n0iO1Oii_dataout; + n0iO1l1i <= wire_n0iO1O1l_dataout; + n0iO1l1l <= wire_n0iO1O1O_dataout; + n0iO1l1O <= wire_n0iO1O0i_dataout; + n0iO1lii <= wire_n0iO1Oil_dataout; + n0iO1lil <= wire_n0iO1OiO_dataout; + n0iO1liO <= wire_n0iO1Oli_dataout; + n0iOilli <= wire_n0iOilOO_dataout; + n0iOilll <= wire_n0iOiO1i_dataout; + n0iOillO <= wire_n0iOiO1l_dataout; + n0iOilOi <= wire_n0iOl10i_dataout; + n0iOiO0O <= wire_n0iOilOl_dataout; + n0iOiOOO <= wire_n0iOl10l_dataout; + n0iOl11i <= wire_n0iOl10O_dataout; + n0iOl11l <= wire_n0iOl1ii_dataout; + n0iOl11O <= wire_n0iOliiO_dataout; + n0iOli1O <= wire_n0iOlili_dataout; + n0iOliil <= wire_n0iOOili_dataout; + n0iOlOiO <= wire_n0iOOill_dataout; + n0iOlOli <= wire_n0iOOilO_dataout; + n0iOlOll <= wire_n0iOOiOi_dataout; + n0iOlOlO <= wire_n0iOOiOl_dataout; + n0iOlOOi <= wire_n0iOOiOO_dataout; + n0iOlOOl <= wire_n0iOOl1i_dataout; + n0iOlOOO <= wire_n0iOOl1l_dataout; + n0iOO00i <= wire_n0iOOO0O_dataout; + n0iOO00l <= wire_n0iOOOii_dataout; + n0iOO00O <= wire_n0iOOOil_dataout; + n0iOO01i <= wire_n0iOOO1O_dataout; + n0iOO01l <= wire_n0iOOO0i_dataout; + n0iOO01O <= wire_n0iOOO0l_dataout; + n0iOO0ii <= wire_n0iOOOiO_dataout; + n0iOO0il <= wire_n0iOOOli_dataout; + n0iOO0iO <= wire_n0iOOOll_dataout; + n0iOO0li <= wire_n0iOOOlO_dataout; + n0iOO0ll <= wire_n0iOOOOi_dataout; + n0iOO0lO <= wire_n0iOOOOl_dataout; + n0iOO0Oi <= wire_n0iOOOOO_dataout; + n0iOO0Ol <= wire_n0l1111i_dataout; + n0iOO0OO <= wire_n0l1111l_dataout; + n0iOO10i <= wire_n0iOOl0O_dataout; + n0iOO10l <= wire_n0iOOlii_dataout; + n0iOO10O <= wire_n0iOOlil_dataout; + n0iOO11i <= wire_n0iOOl1O_dataout; + n0iOO11l <= wire_n0iOOl0i_dataout; + n0iOO11O <= wire_n0iOOl0l_dataout; + n0iOO1ii <= wire_n0iOOliO_dataout; + n0iOO1il <= wire_n0iOOlli_dataout; + n0iOO1iO <= wire_n0iOOlll_dataout; + n0iOO1li <= wire_n0iOOllO_dataout; + n0iOO1ll <= wire_n0iOOlOi_dataout; + n0iOO1lO <= wire_n0iOOlOl_dataout; + n0iOO1Oi <= wire_n0iOOlOO_dataout; + n0iOO1Ol <= wire_n0iOOO1i_dataout; + n0iOO1OO <= wire_n0iOOO1l_dataout; + n0iOOi0i <= wire_n0l1110O_dataout; + n0iOOi0l <= wire_n0l111ii_dataout; + n0iOOi0O <= wire_n0l111il_dataout; + n0iOOi1i <= wire_n0l1111O_dataout; + n0iOOi1l <= wire_n0l1110i_dataout; + n0iOOi1O <= wire_n0l1110l_dataout; + n0iOOiii <= wire_n0l111iO_dataout; + n0iOOiil <= wire_n0l111li_dataout; + n0iOOiiO <= wire_n0l1i0ii_dataout; + n0l00iOO <= wire_n0li101l_dataout; + n0l0111i <= wire_n0l011iO_dataout; + n0l0111l <= wire_n0l011li_dataout; + n0l0111O <= wire_n0l011ll_dataout; + n0l01iiO <= wire_n0l01O0O_dataout; + n0l01ili <= wire_n0l01Oii_dataout; + n0l01ill <= wire_n0l01Oil_dataout; + n0l01ilO <= wire_n0l01OiO_dataout; + n0l01iOi <= wire_n0l01Oli_dataout; + n0l01iOl <= wire_n0l01Oll_dataout; + n0l01iOO <= wire_n0l01OlO_dataout; + n0l01l0i <= wire_n0l0011i_dataout; + n0l01l0l <= wire_n0l0011l_dataout; + n0l01l0O <= wire_n0l0011O_dataout; + n0l01l1i <= wire_n0l01OOi_dataout; + n0l01l1l <= wire_n0l01OOl_dataout; + n0l01l1O <= wire_n0l01OOO_dataout; + n0l01lii <= wire_n0l0010i_dataout; + n0l01lil <= wire_n0l0010l_dataout; + n0l01liO <= wire_n0l0010O_dataout; + n0l01lli <= wire_n0l001ii_dataout; + n0l01lll <= wire_n0l001il_dataout; + n0l01llO <= wire_n0l001iO_dataout; + n0l01lOi <= wire_n0l001li_dataout; + n0l01lOl <= wire_n0l001ll_dataout; + n0l01lOO <= wire_n0l001lO_dataout; + n0l01O0i <= wire_n0l001OO_dataout; + n0l01O1i <= wire_n0l001Oi_dataout; + n0l01O1l <= wire_n0l001Ol_dataout; + n0l01O1O <= wire_n0l0001i_dataout; + n0l10liO <= wire_n0l1i0il_dataout; + n0l10lli <= wire_n0l1i0iO_dataout; + n0l10lll <= wire_n0l1i0li_dataout; + n0l10llO <= wire_n0l1i0ll_dataout; + n0l10lOi <= wire_n0l1i0lO_dataout; + n0l10lOl <= wire_n0l1i0Oi_dataout; + n0l10lOO <= wire_n0l1i0Ol_dataout; + n0l10O0i <= wire_n0l1ii1O_dataout; + n0l10O0l <= wire_n0l1ii0i_dataout; + n0l10O0O <= wire_n0l1ii0l_dataout; + n0l10O1i <= wire_n0l1i0OO_dataout; + n0l10O1l <= wire_n0l1ii1i_dataout; + n0l10O1O <= wire_n0l1ii1l_dataout; + n0l10Oii <= wire_n0l1ii0O_dataout; + n0l10Oil <= wire_n0l1iiii_dataout; + n0l10OiO <= wire_n0l1iiil_dataout; + n0l10Oli <= wire_n0l1iiiO_dataout; + n0l10Oll <= wire_n0l1iili_dataout; + n0l10OlO <= wire_n0l1iill_dataout; + n0l10OOi <= wire_n0l1iilO_dataout; + n0l10OOl <= wire_n0l1iiOi_dataout; + n0l10OOO <= wire_n0l1iiOl_dataout; + n0l1i00O <= wire_n0l1O0il_dataout; + n0l1i01i <= wire_n0l1ilOO_dataout; + n0l1i10i <= wire_n0l1il1O_dataout; + n0l1i10l <= wire_n0l1il0i_dataout; + n0l1i10O <= wire_n0l1il0l_dataout; + n0l1i11i <= wire_n0l1iiOO_dataout; + n0l1i11l <= wire_n0l1il1i_dataout; + n0l1i11O <= wire_n0l1il1l_dataout; + n0l1i1ii <= wire_n0l1il0O_dataout; + n0l1i1il <= wire_n0l1ilii_dataout; + n0l1i1iO <= wire_n0l1ilil_dataout; + n0l1i1li <= wire_n0l1iliO_dataout; + n0l1i1ll <= wire_n0l1illi_dataout; + n0l1i1lO <= wire_n0l1illl_dataout; + n0l1i1Oi <= wire_n0l1illO_dataout; + n0l1i1Ol <= wire_n0l1ilOi_dataout; + n0l1i1OO <= wire_n0l1ilOl_dataout; + n0l1O00i <= wire_n0l1O0iO_dataout; + n0l1O00l <= wire_n0l1O0li_dataout; + n0l1O00O <= wire_n0l1O0ll_dataout; + n0l1O0ii <= wire_n0l1Ol1l_dataout; + n0l1Oiii <= wire_n0l1Ol1O_dataout; + n0l1Oiil <= wire_n0l1Ol0i_dataout; + n0l1OiiO <= wire_n0l1Ol0l_dataout; + n0l1Oili <= wire_n0l1Ol0O_dataout; + n0l1Oill <= wire_n0l1Olii_dataout; + n0l1OilO <= wire_n0l1Olil_dataout; + n0l1OiOi <= wire_n0l1OliO_dataout; + n0l1OiOl <= wire_n0l1Olli_dataout; + n0l1OiOO <= wire_n0l1Olll_dataout; + n0l1Ol1i <= wire_n0l0110l_dataout; + n0l1OOOi <= wire_n0l0110O_dataout; + n0l1OOOl <= wire_n0l011ii_dataout; + n0l1OOOO <= wire_n0l011il_dataout; + n0li0iiO <= wire_n0li0O0O_dataout; + n0li0l0l <= wire_n0li0Oii_dataout; + n0li0l0O <= wire_n0li0Oil_dataout; + n0li0lii <= wire_n0li0OiO_dataout; + n0li0lil <= wire_n0li0Oli_dataout; + n0li0liO <= wire_n0li0Oll_dataout; + n0li0lli <= wire_n0li0OlO_dataout; + n0li0lll <= wire_n0li0OOi_dataout; + n0li0llO <= wire_n0li0OOl_dataout; + n0li0lOi <= wire_n0li0OOO_dataout; + n0li0lOl <= wire_n0lii11i_dataout; + n0li0lOO <= wire_n0lii11l_dataout; + n0li0O0i <= wire_n0lii10O_dataout; + n0li0O0l <= wire_n0liiili_dataout; + n0li0O1i <= wire_n0lii11O_dataout; + n0li0O1l <= wire_n0lii10i_dataout; + n0li0O1O <= wire_n0lii10l_dataout; + n0li101i <= wire_n0li1i1O_dataout; + n0li110i <= wire_n0li100O_dataout; + n0li110l <= wire_n0li10ii_dataout; + n0li110O <= wire_n0li10il_dataout; + n0li111i <= wire_n0li101O_dataout; + n0li111l <= wire_n0li100i_dataout; + n0li111O <= wire_n0li100l_dataout; + n0li11ii <= wire_n0li10iO_dataout; + n0li11il <= wire_n0li10li_dataout; + n0li11iO <= wire_n0li10ll_dataout; + n0li11li <= wire_n0li10lO_dataout; + n0li11ll <= wire_n0li10Oi_dataout; + n0li11lO <= wire_n0li10Ol_dataout; + n0li11Oi <= wire_n0li10OO_dataout; + n0li11Ol <= wire_n0li1i1i_dataout; + n0li11OO <= wire_n0li1i1l_dataout; + n0lil00i <= wire_n0lili0l_dataout; + n0lil00l <= wire_n0lili0O_dataout; + n0lil00O <= wire_n0liliii_dataout; + n0lil01i <= wire_n0lili1l_dataout; + n0lil01l <= wire_n0lili1O_dataout; + n0lil01O <= wire_n0lili0i_dataout; + n0lil0ii <= wire_n0liliil_dataout; + n0lil0il <= wire_n0liliiO_dataout; + n0lil0iO <= wire_n0lilili_dataout; + n0lil0li <= wire_n0lilill_dataout; + n0lil0ll <= wire_n0lililO_dataout; + n0lil0lO <= wire_n0liliOi_dataout; + n0lil0Oi <= wire_n0liliOl_dataout; + n0lil11O <= wire_n0lil0Ol_dataout; + n0lil1Ol <= wire_n0lil0OO_dataout; + n0lil1OO <= wire_n0lili1i_dataout; + n0ll01ii <= wire_n0ll01Ol_dataout; + n0ll01lO <= wire_n0lli1Ol_dataout; + n0ll0iOi <= wire_n0lli1OO_dataout; + n0ll0iOl <= wire_n0lli01i_dataout; + n0ll0iOO <= wire_n0lli01l_dataout; + n0ll0l0i <= wire_n0lli00O_dataout; + n0ll0l0l <= wire_n0lli0ii_dataout; + n0ll0l0O <= wire_n0lli0il_dataout; + n0ll0l1i <= wire_n0lli01O_dataout; + n0ll0l1l <= wire_n0lli00i_dataout; + n0ll0l1O <= wire_n0lli00l_dataout; + n0ll0lii <= wire_n0lli0iO_dataout; + n0ll0lil <= wire_n0lli0li_dataout; + n0ll0liO <= wire_n0lli0ll_dataout; + n0ll0lli <= wire_n0lli0lO_dataout; + n0ll0lll <= wire_n0lli0Oi_dataout; + n0ll0llO <= wire_n0lli0Ol_dataout; + n0ll0lOi <= wire_n0lli0OO_dataout; + n0ll0lOl <= wire_n0llii1i_dataout; + n0ll0lOO <= wire_n0llii1l_dataout; + n0ll0O0i <= wire_n0llii0O_dataout; + n0ll0O0l <= wire_n0lliiii_dataout; + n0ll0O0O <= wire_n0lliiil_dataout; + n0ll0O1i <= wire_n0llii1O_dataout; + n0ll0O1l <= wire_n0llii0i_dataout; + n0ll0O1O <= wire_n0llii0l_dataout; + n0ll0Oii <= wire_n0lliiiO_dataout; + n0ll0Oil <= wire_n0lliili_dataout; + n0ll0OiO <= wire_n0lliill_dataout; + n0ll0Oli <= wire_n0lliilO_dataout; + n0ll0Oll <= wire_n0lliiOi_dataout; + n0ll0OlO <= wire_n0lliiOl_dataout; + n0ll0OOi <= wire_n0lliiOO_dataout; + n0ll0OOl <= wire_n0llil1i_dataout; + n0ll0OOO <= wire_n0llil1l_dataout; + n0ll10Ol <= wire_n0ll1i0i_dataout; + n0ll10OO <= wire_n0ll1i0l_dataout; + n0ll1i1i <= wire_n0ll1i0O_dataout; + n0ll1i1l <= wire_n0ll1lil_dataout; + n0ll1ili <= wire_n0ll1i1O_dataout; + n0ll1l0i <= wire_n0ll1liO_dataout; + n0ll1l0l <= wire_n0ll1lli_dataout; + n0ll1l0O <= wire_n0ll1lll_dataout; + n0ll1lii <= wire_n0ll01Oi_dataout; + n0lli10i <= wire_n0llil0O_dataout; + n0lli10l <= wire_n0llilii_dataout; + n0lli10O <= wire_n0llilil_dataout; + n0lli11i <= wire_n0llil1O_dataout; + n0lli11l <= wire_n0llil0i_dataout; + n0lli11O <= wire_n0llil0l_dataout; + n0lli1ii <= wire_n0lliliO_dataout; + n0lli1il <= wire_n0llilli_dataout; + n0lli1iO <= wire_n0llilll_dataout; + n0lli1li <= wire_n0llillO_dataout; + n0lli1ll <= wire_n0llilOi_dataout; + n0lli1lO <= wire_n0llilOl_dataout; + n0lli1Oi <= wire_n0llOOll_dataout; + n0llO0Oi <= wire_n0llOOlO_dataout; + n0llO0Ol <= wire_n0llOOOi_dataout; + n0llO0OO <= wire_n0llOOOl_dataout; + n0llOi0i <= wire_n0lO111O_dataout; + n0llOi0l <= wire_n0lO110i_dataout; + n0llOi0O <= wire_n0lO110l_dataout; + n0llOi1i <= wire_n0llOOOO_dataout; + n0llOi1l <= wire_n0lO111i_dataout; + n0llOi1O <= wire_n0lO111l_dataout; + n0llOiii <= wire_n0lO110O_dataout; + n0llOiil <= wire_n0lO11ii_dataout; + n0llOiiO <= wire_n0lO11il_dataout; + n0llOili <= wire_n0lO11iO_dataout; + n0llOill <= wire_n0lO11li_dataout; + n0llOilO <= wire_n0lO11ll_dataout; + n0llOiOi <= wire_n0lO11lO_dataout; + n0llOiOl <= wire_n0lO11Oi_dataout; + n0llOiOO <= wire_n0lO11Ol_dataout; + n0llOl0i <= wire_n0lO101O_dataout; + n0llOl0l <= wire_n0lO100i_dataout; + n0llOl0O <= wire_n0lO100l_dataout; + n0llOl1i <= wire_n0lO11OO_dataout; + n0llOl1l <= wire_n0lO101i_dataout; + n0llOl1O <= wire_n0lO101l_dataout; + n0llOlii <= wire_n0lO100O_dataout; + n0llOlil <= wire_n0lO10ii_dataout; + n0llOliO <= wire_n0lO10il_dataout; + n0llOlli <= wire_n0lO10iO_dataout; + n0llOlll <= wire_n0lO10li_dataout; + n0llOllO <= wire_n0lO10ll_dataout; + n0llOlOi <= wire_n0lO10lO_dataout; + n0llOlOl <= wire_n0lO10Oi_dataout; + n0llOlOO <= wire_n0lO10Ol_dataout; + n0llOO0i <= wire_n0lO1i1O_dataout; + n0llOO0l <= wire_n0lO1i0i_dataout; + n0llOO1i <= wire_n0lO10OO_dataout; + n0llOO1l <= wire_n0lO1i1i_dataout; + n0llOO1O <= wire_n0lO1i1l_dataout; + n0llOOli <= wire_n0lO0OlO_dataout; + n0lO0Oil <= wire_n0lO0OOi_dataout; + n0lO0OiO <= wire_n0lO0OOl_dataout; + n0lO0Oli <= wire_n0lO0OOO_dataout; + n0lO0Oll <= wire_n0lOi00O_dataout; + n0lOi00i <= wire_n0lOi0OO_dataout; + n0lOi00l <= wire_n0lOiliO_dataout; + n0lOi01i <= wire_n0lOi0lO_dataout; + n0lOi01l <= wire_n0lOi0Oi_dataout; + n0lOi01O <= wire_n0lOi0Ol_dataout; + n0lOi1ll <= wire_n0lOi0ii_dataout; + n0lOi1lO <= wire_n0lOi0il_dataout; + n0lOi1Oi <= wire_n0lOi0iO_dataout; + n0lOi1Ol <= wire_n0lOi0li_dataout; + n0lOi1OO <= wire_n0lOi0ll_dataout; + n0lOil0i <= wire_n0lOillO_dataout; + n0lOil0l <= wire_n0lOilOi_dataout; + n0lOil0O <= wire_n0lOilOl_dataout; + n0lOil1l <= wire_n0lOilli_dataout; + n0lOil1O <= wire_n0lOilll_dataout; + n0lOilii <= wire_n0lOilOO_dataout; + n0lOl00i <= wire_n0lOll1i_dataout; + n0lOl00l <= wire_n0lOll1l_dataout; + n0lOl00O <= wire_n0lOll1O_dataout; + n0lOl01i <= wire_n0lOliOi_dataout; + n0lOl01l <= wire_n0lOliOl_dataout; + n0lOl01O <= wire_n0lOliOO_dataout; + n0lOl0ii <= wire_n0lOll0i_dataout; + n0lOl0il <= wire_n0lOll0l_dataout; + n0lOl0iO <= wire_n0lOll0O_dataout; + n0lOl0li <= wire_n0lOllii_dataout; + n0lOl0ll <= wire_n0lOllil_dataout; + n0lOl0lO <= wire_n0lOlliO_dataout; + n0lOl0Oi <= wire_n0lOllli_dataout; + n0lOl0Ol <= wire_n0lOllll_dataout; + n0lOl0OO <= wire_n0lOlllO_dataout; + n0lOl1Oi <= wire_n0lOlili_dataout; + n0lOl1Ol <= wire_n0lOlill_dataout; + n0lOl1OO <= wire_n0lOlilO_dataout; + n0lOli0i <= wire_n0lOlO1i_dataout; + n0lOli0l <= wire_n0lOlO1l_dataout; + n0lOli0O <= wire_n0lOlO1O_dataout; + n0lOli1i <= wire_n0lOllOi_dataout; + n0lOli1l <= wire_n0lOllOl_dataout; + n0lOli1O <= wire_n0lOllOO_dataout; + n0lOliii <= wire_n0lOlO0l_dataout; + n0lOliil <= wire_n0lOlO0i_dataout; + n0lOO00i <= wire_n0O1iO0O_dataout; + n0O0011i <= wire_n0O0001l_dataout; + n0O0011l <= wire_n0O0001O_dataout; + n0O01lii <= wire_n0O0011O_dataout; + n0O01O0i <= wire_n0O0010l_dataout; + n0O01O0l <= wire_n0O0010O_dataout; + n0O01O0O <= wire_n0O001ii_dataout; + n0O01O1O <= wire_n0O0010i_dataout; + n0O01Oii <= wire_n0O001il_dataout; + n0O01Oil <= wire_n0O001iO_dataout; + n0O01OiO <= wire_n0O001li_dataout; + n0O01Oli <= wire_n0O001ll_dataout; + n0O01Oll <= wire_n0O001lO_dataout; + n0O01OlO <= wire_n0O001Oi_dataout; + n0O01OOi <= wire_n0O001Ol_dataout; + n0O01OOl <= wire_n0O001OO_dataout; + n0O01OOO <= wire_n0O0001i_dataout; + n0O0l0il <= wire_n0O0l0Oi_dataout; + n0O0l0iO <= wire_n0O0l0Ol_dataout; + n0O0l0li <= wire_n0O0l0OO_dataout; + n0O0l0ll <= wire_n0O0lO1l_dataout; + n0O0l10i <= wire_n0O0l1iO_dataout; + n0O0l10l <= wire_n0O0l1li_dataout; + n0O0l10O <= wire_n0O0l0lO_dataout; + n0O0l11O <= wire_n0O0l1il_dataout; + n0O0l1Ol <= wire_n0O0l1ii_dataout; + n0O0llll <= wire_n0O0lO1O_dataout; + n0O0lO1i <= wire_n0O0OO1O_dataout; + n0O0O00i <= wire_n0O0OO0O_dataout; + n0O0O00l <= wire_n0O0OOii_dataout; + n0O0O00O <= wire_n0O0OOil_dataout; + n0O0O01l <= wire_n0O0OO0i_dataout; + n0O0O01O <= wire_n0O0OO0l_dataout; + n0O0O0ii <= wire_n0O0OOiO_dataout; + n0O0O0il <= wire_n0O0OOli_dataout; + n0O0O0iO <= wire_n0O0OOll_dataout; + n0O0O0li <= wire_n0O0OOlO_dataout; + n0O0O0ll <= wire_n0O0OOOi_dataout; + n0O0O0lO <= wire_n0O0OOOl_dataout; + n0O0O0Oi <= wire_n0O0OOOO_dataout; + n0O0O0Ol <= wire_n0Oi111i_dataout; + n0O0O0OO <= wire_n0Oi111l_dataout; + n0O0Oi0i <= wire_n0Oi110O_dataout; + n0O0Oi0l <= wire_n0Oi11ii_dataout; + n0O0Oi0O <= wire_n0Oi11il_dataout; + n0O0Oi1i <= wire_n0Oi111O_dataout; + n0O0Oi1l <= wire_n0Oi110i_dataout; + n0O0Oi1O <= wire_n0Oi110l_dataout; + n0O0Oiii <= wire_n0Oi11iO_dataout; + n0O0Oiil <= wire_n0Oi11li_dataout; + n0O0OiiO <= wire_n0Oi11ll_dataout; + n0O0Oili <= wire_n0Oi11lO_dataout; + n0O0Oill <= wire_n0Oi11Oi_dataout; + n0O0OilO <= wire_n0Oi11Ol_dataout; + n0O0OiOi <= wire_n0Oi11OO_dataout; + n0O0OiOl <= wire_n0Oi101i_dataout; + n0O0OiOO <= wire_n0Oi101l_dataout; + n0O0Ol0i <= wire_n0Oi100O_dataout; + n0O0Ol0l <= wire_n0Oi10ii_dataout; + n0O0Ol0O <= wire_n0Oi10il_dataout; + n0O0Ol1i <= wire_n0Oi101O_dataout; + n0O0Ol1l <= wire_n0Oi100i_dataout; + n0O0Ol1O <= wire_n0Oi100l_dataout; + n0O0Olii <= wire_n0Oi10iO_dataout; + n0O0Olil <= wire_n0Oi10li_dataout; + n0O0OliO <= wire_n0Oi10ll_dataout; + n0O0Olli <= wire_n0Oi10lO_dataout; + n0O0Olll <= wire_n0Oi10Oi_dataout; + n0O0OllO <= wire_n0Oi10Ol_dataout; + n0O0OlOi <= wire_n0Oi10OO_dataout; + n0O0OlOl <= wire_n0Oi1i1i_dataout; + n0O0OlOO <= wire_n0Oi1i1l_dataout; + n0O0OO1i <= wire_n0Oi1i1O_dataout; + n0O0OO1l <= wire_n0OiiiOO_dataout; + n0O1il0l <= wire_n0O1iOii_dataout; + n0O1il0O <= wire_n0O1iOil_dataout; + n0O1ilii <= wire_n0O1iOiO_dataout; + n0O1ilil <= wire_n0O1iOli_dataout; + n0O1iliO <= wire_n0O1iOll_dataout; + n0O1illi <= wire_n0O1iOlO_dataout; + n0O1illl <= wire_n0O1iOOi_dataout; + n0O1illO <= wire_n0O1iOOl_dataout; + n0O1ilOi <= wire_n0O1iOOO_dataout; + n0O1ilOl <= wire_n0O1l11i_dataout; + n0O1ilOO <= wire_n0O1l11l_dataout; + n0O1iO0i <= wire_n0O1l10O_dataout; + n0O1iO0l <= wire_n0O1l1ii_dataout; + n0O1iO1i <= wire_n0O1l11O_dataout; + n0O1iO1l <= wire_n0O1l10i_dataout; + n0O1iO1O <= wire_n0O1l10l_dataout; + n0O1O0iO <= wire_n0O1Oill_dataout; + n0O1O0li <= wire_n0O1OilO_dataout; + n0O1O0ll <= wire_n0O1OiOi_dataout; + n0O1O0lO <= wire_n0O1OiOl_dataout; + n0O1O0Oi <= wire_n0O1OiOO_dataout; + n0O1O0Ol <= wire_n0O1Ol1i_dataout; + n0O1O0OO <= wire_n0O1Ol1l_dataout; + n0O1O1Oi <= wire_n0O1Oili_dataout; + n0O1Oi0i <= wire_n0O1Ol0O_dataout; + n0O1Oi0l <= wire_n0O1Olii_dataout; + n0O1Oi0O <= wire_n0O1Olil_dataout; + n0O1Oi1i <= wire_n0O1Ol1O_dataout; + n0O1Oi1l <= wire_n0O1Ol0i_dataout; + n0O1Oi1O <= wire_n0O1Ol0l_dataout; + n0O1Oiii <= wire_n0O1OliO_dataout; + n0O1Oiil <= wire_n0O1Olli_dataout; + n0O1OiiO <= wire_n0O011Ol_dataout; + n0Oii00i <= wire_n0OiiO1O_dataout; + n0Oii00l <= wire_n0OiiO0i_dataout; + n0Oii00O <= wire_n0OiiO0l_dataout; + n0Oii01i <= wire_n0OiilOO_dataout; + n0Oii01l <= wire_n0OiiO1i_dataout; + n0Oii01O <= wire_n0OiiO1l_dataout; + n0Oii0ii <= wire_n0OiiO0O_dataout; + n0Oii0il <= wire_n0OiiOii_dataout; + n0Oii0iO <= wire_n0OiiOil_dataout; + n0Oii0li <= wire_n0OiiOiO_dataout; + n0Oii0ll <= wire_n0OiiOli_dataout; + n0Oii0lO <= wire_n0OiiOll_dataout; + n0Oii0Oi <= wire_n0OiiOlO_dataout; + n0Oii0Ol <= wire_n0OiiOOi_dataout; + n0Oii0OO <= wire_n0OiiOOl_dataout; + n0Oii10i <= wire_n0Oiil1O_dataout; + n0Oii10l <= wire_n0Oiil0i_dataout; + n0Oii10O <= wire_n0Oiil0l_dataout; + n0Oii11l <= wire_n0Oiil1i_dataout; + n0Oii11O <= wire_n0Oiil1l_dataout; + n0Oii1ii <= wire_n0Oiil0O_dataout; + n0Oii1il <= wire_n0Oiilii_dataout; + n0Oii1iO <= wire_n0Oiilil_dataout; + n0Oii1li <= wire_n0OiiliO_dataout; + n0Oii1ll <= wire_n0Oiilli_dataout; + n0Oii1lO <= wire_n0Oiilll_dataout; + n0Oii1Oi <= wire_n0OiillO_dataout; + n0Oii1Ol <= wire_n0OiilOi_dataout; + n0Oii1OO <= wire_n0OiilOl_dataout; + n0Oiii0i <= wire_n0Oil11O_dataout; + n0Oiii0l <= wire_n0Oil10i_dataout; + n0Oiii0O <= wire_n0Oil10l_dataout; + n0Oiii1i <= wire_n0OiiOOO_dataout; + n0Oiii1l <= wire_n0Oil11i_dataout; + n0Oiii1O <= wire_n0Oil11l_dataout; + n0Oiiiii <= wire_n0Oil10O_dataout; + n0Oiiiil <= wire_n0Oil1ii_dataout; + n0OiiiiO <= wire_n0Oil1il_dataout; + n0OiiiOl <= wire_n0OiOl1i_dataout; + n0OiOilO <= wire_n0OiOl1l_dataout; + n0OiOiOi <= wire_n0OiOl1O_dataout; + n0OiOiOl <= wire_n0OiOl0i_dataout; + n0OiOiOO <= wire_n0OiOOli_dataout; + n0OiOlOO <= wire_n0OiOOll_dataout; + n0OiOO0i <= wire_n0OiOOOO_dataout; + n0OiOO0l <= wire_n0Ol111i_dataout; + n0OiOO0O <= wire_n0Ol111l_dataout; + n0OiOO1i <= wire_n0OiOOlO_dataout; + n0OiOO1l <= wire_n0OiOOOi_dataout; + n0OiOO1O <= wire_n0OiOOOl_dataout; + n0OiOOii <= wire_n0Ol111O_dataout; + n0OiOOil <= wire_n0Ol110i_dataout; + n0OiOOiO <= wire_n0Ol10Oi_dataout; + n0Ol010i <= wire_n0Ol0i1i_dataout; + n0Ol010l <= wire_n0Ol0i1l_dataout; + n0Ol010O <= wire_n0Ol0i1O_dataout; + n0Ol011i <= wire_n0Ol00Oi_dataout; + n0Ol011l <= wire_n0Ol00Ol_dataout; + n0Ol011O <= wire_n0Ol00OO_dataout; + n0Ol01ii <= wire_n0Ol0i0i_dataout; + n0Ol01il <= wire_n0Ol0i0l_dataout; + n0Ol01iO <= wire_n0Ol0i0O_dataout; + n0Ol01li <= wire_n0Ol0iii_dataout; + n0Ol01ll <= wire_n0Ol0iiO_dataout; + n0Ol01lO <= wire_n0Ol0iil_dataout; + n0Ol0Oil <= wire_n0OO1ili_dataout; + n0Ol100O <= wire_n0Ol10Ol_dataout; + n0Ol10ii <= wire_n0Ol10OO_dataout; + n0Ol10il <= wire_n0Ol1i1i_dataout; + n0Ol10iO <= wire_n0Ol1i1l_dataout; + n0Ol10li <= wire_n0Ol1i1O_dataout; + n0Ol10ll <= wire_n0Ol1i0i_dataout; + n0Ol1O0i <= wire_n0Ol001i_dataout; + n0Ol1O0l <= wire_n0Ol001l_dataout; + n0Ol1O0O <= wire_n0Ol001O_dataout; + n0Ol1O1l <= wire_n0Ol01Ol_dataout; + n0Ol1O1O <= wire_n0Ol01OO_dataout; + n0Ol1Oii <= wire_n0Ol000i_dataout; + n0Ol1Oil <= wire_n0Ol000l_dataout; + n0Ol1OiO <= wire_n0Ol000O_dataout; + n0Ol1Oli <= wire_n0Ol00ii_dataout; + n0Ol1Oll <= wire_n0Ol00il_dataout; + n0Ol1OlO <= wire_n0Ol00iO_dataout; + n0Ol1OOi <= wire_n0Ol00li_dataout; + n0Ol1OOl <= wire_n0Ol00ll_dataout; + n0Ol1OOO <= wire_n0Ol00lO_dataout; + n0OO0iii <= wire_n0OO0l1l_dataout; + n0OO0iil <= wire_n0OO0l1O_dataout; + n0OO0iiO <= wire_n0OO0l0i_dataout; + n0OO0ili <= wire_n0OO0l0l_dataout; + n0OO0ill <= wire_n0OO0l0O_dataout; + n0OO0ilO <= wire_n0OO0lii_dataout; + n0OO0iOi <= wire_n0OO0lil_dataout; + n0OO0iOl <= wire_n0OO0liO_dataout; + n0OO0iOO <= wire_n0OOi1il_dataout; + n0OO0OOi <= wire_n0OO0l1i_dataout; + n0OO0OOl <= wire_n0OOi1iO_dataout; + n0OO0OOO <= wire_n0OOi1li_dataout; + n0OO10iO <= wire_n0OO1ill_dataout; + n0OO10li <= wire_n0OO1ilO_dataout; + n0OO10ll <= wire_n0OO1iOi_dataout; + n0OO10lO <= wire_n0OO1iOl_dataout; + n0OO10Oi <= wire_n0OO1iOO_dataout; + n0OO10Ol <= wire_n0OO1l1i_dataout; + n0OO10OO <= wire_n0OO1l1l_dataout; + n0OO1i0i <= wire_n0OO1l0O_dataout; + n0OO1i0l <= wire_n0OO1lii_dataout; + n0OO1i0O <= wire_n0OO1lil_dataout; + n0OO1i1i <= wire_n0OO1l1O_dataout; + n0OO1i1l <= wire_n0OO1l0i_dataout; + n0OO1i1O <= wire_n0OO1l0l_dataout; + n0OO1iii <= wire_n0OO1liO_dataout; + n0OO1iil <= wire_n0OO1lli_dataout; + n0OO1iiO <= wire_n0OO1lll_dataout; + n0OOi10i <= wire_n0OOi1Ol_dataout; + n0OOi10l <= wire_n0OOi1OO_dataout; + n0OOi10O <= wire_n0OOi01i_dataout; + n0OOi11i <= wire_n0OOi1ll_dataout; + n0OOi11l <= wire_n0OOi1lO_dataout; + n0OOi11O <= wire_n0OOi1Oi_dataout; + n0OOi1ii <= wire_n0OOil1O_dataout; + n0OOiiiO <= wire_n0OOil0i_dataout; + n0OOiili <= wire_n0OOil0l_dataout; + n0OOiill <= wire_n0OOil0O_dataout; + n0OOiilO <= wire_n0OOilii_dataout; + n0OOiiOi <= wire_n0OOilil_dataout; + n0OOiiOl <= wire_n0OOiliO_dataout; + n0OOiiOO <= wire_n0OOilli_dataout; + n0OOil1i <= wire_n0OOilll_dataout; + n0OOil1l <= wire_n0OOl1Oi_dataout; + n0OOl10i <= wire_n0OOl1Ol_dataout; + n0OOl10l <= wire_n0OOl1OO_dataout; + n0OOl10O <= wire_n0OOl01i_dataout; + n0OOl1ii <= wire_n0OOl01l_dataout; + n0OOl1il <= wire_n0OOl01O_dataout; + n0OOl1iO <= wire_n0OOl00i_dataout; + n0OOl1li <= wire_n0OOl00l_dataout; + n0OOl1ll <= wire_n0OOl00O_dataout; + n0OOl1lO <= wire_n0OOllil_dataout; + n0OOliOl <= wire_n0OOlliO_dataout; + n0OOliOO <= wire_n0OOllli_dataout; + n0OOll0i <= wire_n0OOllOl_dataout; + n0OOll0l <= wire_n0OOllOO_dataout; + n0OOll0O <= wire_n0OOlO1i_dataout; + n0OOll1i <= wire_n0OOllll_dataout; + n0OOll1l <= wire_n0OOlllO_dataout; + n0OOll1O <= wire_n0OOllOi_dataout; + n0OOllii <= wire_n0OOO01O_dataout; + n0OOO01i <= wire_n0OOO0ll_dataout; + n0OOO01l <= wire_n0OOOlOi_dataout; + n0OOO1iO <= wire_n0OOO00i_dataout; + n0OOO1li <= wire_n0OOO00l_dataout; + n0OOO1ll <= wire_n0OOO00O_dataout; + n0OOO1lO <= wire_n0OOO0ii_dataout; + n0OOO1Oi <= wire_n0OOO0il_dataout; + n0OOO1Ol <= wire_n0OOO0iO_dataout; + n0OOO1OO <= wire_n0OOO0li_dataout; + n0OOOl0i <= wire_n0OOOlOl_dataout; + n0OOOl0l <= wire_n0OOOlOO_dataout; + n0OOOl0O <= wire_n0OOOO1i_dataout; + n0OOOlii <= wire_n0OOOO1l_dataout; + n0OOOlil <= wire_n0OOOO1O_dataout; + n0OOOliO <= wire_n0OOOO0i_dataout; + n0OOOlli <= wire_n0OOOO0l_dataout; + n0OOOlll <= wire_n0OOOO0O_dataout; + n0OOOllO <= wire_ni1110il_dataout; + n1101iiO <= wire_n1101llO_dataout; + n1101ili <= wire_n1101lOi_dataout; + n1101ill <= wire_n1101lOl_dataout; + n1101ilO <= wire_n1101lOO_dataout; + n1101iOi <= wire_n1101O1i_dataout; + n1101iOl <= wire_n1101O1l_dataout; + n1101iOO <= wire_n1101O1O_dataout; + n1101l0i <= wire_n1101Oii_dataout; + n1101l0l <= wire_n1101Oil_dataout; + n1101l0O <= wire_n1101OiO_dataout; + n1101l1i <= wire_n1101O0i_dataout; + n1101l1l <= wire_n1101O0l_dataout; + n1101l1O <= wire_n1101O0O_dataout; + n1101lii <= wire_n1101Oli_dataout; + n1101lil <= wire_n1101Oll_dataout; + n1101liO <= wire_n1101OlO_dataout; + n1101lli <= wire_n11i110l_dataout; + n110OOii <= wire_n11i110O_dataout; + n110OOil <= wire_n11i11ii_dataout; + n110OOiO <= wire_n11i11il_dataout; + n110OOli <= wire_n11i11iO_dataout; + n110OOll <= wire_n11i11li_dataout; + n110OOlO <= wire_n11i11ll_dataout; + n110OOOi <= wire_n11i11lO_dataout; + n110OOOl <= wire_n11i11Oi_dataout; + n110OOOO <= wire_n11i11Ol_dataout; + n1110O0l <= wire_n111i0li_dataout; + n1110O0O <= wire_n111i0ll_dataout; + n1110Oii <= wire_n111i0lO_dataout; + n1110Oil <= wire_n111i0Oi_dataout; + n1110OiO <= wire_n111i0Ol_dataout; + n1110Oli <= wire_n111i0OO_dataout; + n1110Oll <= wire_n111ii1i_dataout; + n1110OlO <= wire_n111ii1l_dataout; + n1110OOi <= wire_n111ii1O_dataout; + n1110OOl <= wire_n111ii0i_dataout; + n1110OOO <= wire_n111ii0l_dataout; + n111i00i <= wire_n111iliO_dataout; + n111i00l <= wire_n111illi_dataout; + n111i00O <= wire_n111illl_dataout; + n111i01i <= wire_n111il0O_dataout; + n111i01l <= wire_n111ilii_dataout; + n111i01O <= wire_n111ilil_dataout; + n111i0ii <= wire_n111illO_dataout; + n111i0il <= wire_n1101lll_dataout; + n111i10i <= wire_n111iiiO_dataout; + n111i10l <= wire_n111iili_dataout; + n111i10O <= wire_n111iill_dataout; + n111i11i <= wire_n111ii0O_dataout; + n111i11l <= wire_n111iiii_dataout; + n111i11O <= wire_n111iiil_dataout; + n111i1ii <= wire_n111iilO_dataout; + n111i1il <= wire_n111iiOi_dataout; + n111i1iO <= wire_n111iiOl_dataout; + n111i1li <= wire_n111iiOO_dataout; + n111i1ll <= wire_n111il1i_dataout; + n111i1lO <= wire_n111il1l_dataout; + n111i1Oi <= wire_n111il1O_dataout; + n111i1Ol <= wire_n111il0i_dataout; + n111i1OO <= wire_n111il0l_dataout; + n11i111i <= wire_n11i11OO_dataout; + n11i111l <= wire_n11i101i_dataout; + n11i111O <= wire_n11i101l_dataout; + n11l0Oii <= wire_n11li1Ol_dataout; + n11l0Oil <= wire_n11li1lO_dataout; + n11l0OiO <= wire_n11li1OO_dataout; + n11l0Oli <= wire_n11li01i_dataout; + n11l0Oll <= wire_n11li01l_dataout; + n11l0OlO <= wire_n11li01O_dataout; + n11l0OOi <= wire_n11li00i_dataout; + n11l0OOl <= wire_n11li00l_dataout; + n11l0OOO <= wire_n11li00O_dataout; + n11li10i <= wire_n11li0li_dataout; + n11li10l <= wire_n11li0ll_dataout; + n11li10O <= wire_n11li0lO_dataout; + n11li11i <= wire_n11li0ii_dataout; + n11li11l <= wire_n11li0il_dataout; + n11li11O <= wire_n11li0iO_dataout; + n11li1ii <= wire_n11li0Oi_dataout; + n11li1il <= wire_n11li0Ol_dataout; + n11li1li <= wire_n11lii1i_dataout; + n11O000i <= wire_n11Oilli_dataout; + n11O000l <= wire_n11Oilll_dataout; + n11O000O <= wire_n11OillO_dataout; + n11O001i <= wire_n11Oilii_dataout; + n11O001l <= wire_n11Oilil_dataout; + n11O001O <= wire_n11OiliO_dataout; + n11O00ii <= wire_n11OilOi_dataout; + n11O00il <= wire_n11OilOl_dataout; + n11O00iO <= wire_n11OilOO_dataout; + n11O00li <= wire_n11OiO1i_dataout; + n11O00ll <= wire_n11OiO1l_dataout; + n11O00lO <= wire_n11OiO1O_dataout; + n11O00Oi <= wire_n11OiO0i_dataout; + n11O00Ol <= wire_n11OiO0l_dataout; + n11O00OO <= wire_n11OiO0O_dataout; + n11O010i <= wire_n11Oiili_dataout; + n11O010O <= wire_n11OiilO_dataout; + n11O011i <= wire_n11Oiiii_dataout; + n11O011l <= wire_n11Oiiil_dataout; + n11O011O <= wire_n11OiiiO_dataout; + n11O01ii <= wire_n11OiiOi_dataout; + n11O01il <= wire_n11OiiOl_dataout; + n11O01iO <= wire_n11OiiOO_dataout; + n11O01li <= wire_n11Oil1i_dataout; + n11O01ll <= wire_n11Oil1l_dataout; + n11O01lO <= wire_n11Oil1O_dataout; + n11O01Oi <= wire_n11Oil0i_dataout; + n11O01Ol <= wire_n11Oil0l_dataout; + n11O01OO <= wire_n11Oil0O_dataout; + n11O0i0i <= wire_n11OiOli_dataout; + n11O0i0O <= wire_n11OiOlO_dataout; + n11O0i1i <= wire_n11OiOii_dataout; + n11O0i1O <= wire_n11OiOiO_dataout; + n11O0iil <= wire_n11OiOOl_dataout; + n11O0ili <= wire_n11Ol11i_dataout; + n11O0ill <= wire_n11Ol11l_dataout; + n11O0ilO <= wire_n11Ol11O_dataout; + n11O0iOi <= wire_n11Ol10i_dataout; + n11O0iOl <= wire_n11Ol10l_dataout; + n11O0iOO <= wire_n11Ol10O_dataout; + n11O0l0i <= wire_n11Ol1li_dataout; + n11O0l0l <= wire_n11Ol1ll_dataout; + n11O0l0O <= wire_n11Ol1lO_dataout; + n11O0l1i <= wire_n11Ol1ii_dataout; + n11O0l1l <= wire_n11Ol1il_dataout; + n11O0l1O <= wire_n11Ol1iO_dataout; + n11O0lii <= wire_n11Ol1Oi_dataout; + n11O0lil <= wire_n11Ol1Ol_dataout; + n11O0liO <= wire_n11Ol1OO_dataout; + n11O0lli <= wire_n11Ol01i_dataout; + n11O0lll <= wire_n11Ol01l_dataout; + n11O0llO <= wire_n11Ol01O_dataout; + n11O0lOi <= wire_n11Ol00i_dataout; + n11O0lOl <= wire_n11Ol00l_dataout; + n11O0lOO <= wire_n11Ol00O_dataout; + n11O0O0i <= wire_n11Ol0li_dataout; + n11O0O0l <= wire_n11Ol0ll_dataout; + n11O0O0O <= wire_n11Ol0lO_dataout; + n11O0O1i <= wire_n11Ol0ii_dataout; + n11O0O1l <= wire_n11Ol0il_dataout; + n11O0O1O <= wire_n11Ol0iO_dataout; + n11O0Oii <= wire_n11Ol0Oi_dataout; + n11O0OiO <= wire_n11Ol0OO_dataout; + n11O0Oli <= wire_n11Oli1i_dataout; + n11O0Oll <= wire_n11Oli1l_dataout; + n11O0OlO <= wire_n11Oli1O_dataout; + n11O0OOi <= wire_n11Oli0i_dataout; + n11O0OOl <= wire_n11Oli0l_dataout; + n11O0OOO <= wire_n11Oli0O_dataout; + n11O1l0O <= wire_n11O1liO_dataout; + n11O1lii <= wire_n11O1lli_dataout; + n11O1lil <= wire_n11Oi0il_dataout; + n11O1O0i <= wire_n11Oi0li_dataout; + n11O1O0l <= wire_n11Oi0ll_dataout; + n11O1O0O <= wire_n11Oi0lO_dataout; + n11O1O1O <= wire_n11Oi0iO_dataout; + n11O1Oii <= wire_n11Oi0Oi_dataout; + n11O1Oil <= wire_n11Oi0Ol_dataout; + n11O1OiO <= wire_n11Oi0OO_dataout; + n11O1Oli <= wire_n11Oii1i_dataout; + n11O1Oll <= wire_n11Oii1l_dataout; + n11O1OlO <= wire_n11Oii1O_dataout; + n11O1OOi <= wire_n11Oii0i_dataout; + n11O1OOl <= wire_n11Oii0l_dataout; + n11O1OOO <= wire_n11Oii0O_dataout; + n11Oi00i <= wire_n11OlliO_dataout; + n11Oi00l <= wire_n11Ollli_dataout; + n11Oi01i <= wire_n11Oll0O_dataout; + n11Oi01l <= wire_n11Ollii_dataout; + n11Oi01O <= wire_n11Ollil_dataout; + n11Oi0ii <= wire_n1iillll_dataout; + n11Oi10i <= wire_n11Olili_dataout; + n11Oi10l <= wire_n11Olill_dataout; + n11Oi10O <= wire_n111ii0i_dataout; + n11Oi11i <= wire_n11Oliii_dataout; + n11Oi11l <= wire_n11Oliil_dataout; + n11Oi11O <= wire_n11OliiO_dataout; + n11Oi1ii <= wire_n11OlilO_dataout; + n11Oi1il <= wire_n11OliOi_dataout; + n11Oi1iO <= wire_n11OliOl_dataout; + n11Oi1li <= wire_n11OliOO_dataout; + n11Oi1ll <= wire_n11Oll1i_dataout; + n11Oi1lO <= wire_n11Oll1l_dataout; + n11Oi1Oi <= wire_n11Oll1O_dataout; + n11Oi1Ol <= wire_n11Oll0i_dataout; + n11Oi1OO <= wire_n11Oll0l_dataout; + n1iiii1i <= wire_nlOlil1ii_dataout; + n1iili0l <= wire_n1iilllO_dataout; + n1iili0O <= wire_n1iillOi_dataout; + n1iiliii <= wire_n1iillOl_dataout; + n1iiliil <= wire_n1iillOO_dataout; + n1iiliiO <= wire_n1iilO1i_dataout; + n1iilili <= wire_n1iilO1l_dataout; + n1iilill <= wire_n1iilO1O_dataout; + n1iililO <= wire_n1iilO0i_dataout; + n1iiliOi <= wire_n1iilO0l_dataout; + n1iiliOl <= wire_n1iilO0O_dataout; + n1iiliOO <= wire_n1iilOii_dataout; + n1iill0i <= wire_n1iilOll_dataout; + n1iill0l <= wire_n1iilOlO_dataout; + n1iill0O <= wire_n1iilOOi_dataout; + n1iill1i <= wire_n1iilOil_dataout; + n1iill1l <= wire_n1iilOiO_dataout; + n1iill1O <= wire_n1iilOli_dataout; + n1iillii <= wire_n1iilOOl_dataout; + n1iillil <= wire_n1iilOOO_dataout; + n1iilliO <= wire_n1iiO11i_dataout; + n1iillli <= wire_n1iiOlOi_dataout; + n1iiOlii <= wire_n1iiOlOl_dataout; + n1iiOlil <= wire_n1iiOlOO_dataout; + n1iiOliO <= wire_n1iiOO1i_dataout; + n1iiOlli <= wire_n1iiOO1l_dataout; + n1iiOlll <= wire_n1iiOO1O_dataout; + n1il100i <= wire_n1il1iOi_dataout; + n1il100l <= wire_n1il1iOl_dataout; + n1il100O <= wire_n1il1iOO_dataout; + n1il101i <= wire_n1il1ili_dataout; + n1il101l <= wire_n1il1ill_dataout; + n1il101O <= wire_n1il1ilO_dataout; + n1il10ii <= wire_n1il1l1i_dataout; + n1il10il <= wire_n1il1l1l_dataout; + n1il10iO <= wire_n1il1l1O_dataout; + n1il10li <= wire_n1il1l0i_dataout; + n1il10ll <= wire_n1il1l0l_dataout; + n1il10lO <= wire_n1il1l0O_dataout; + n1il10Oi <= wire_n1il1lii_dataout; + n1il10Ol <= wire_n1il1lil_dataout; + n1il10OO <= wire_n1il1liO_dataout; + n1il11il <= wire_n1il1iii_dataout; + n1il11li <= wire_nlOll1OOi_dataout; + n1il11ll <= wire_nlOll1O1O_dataout; + n1il11lO <= wire_nlOll1lli_dataout; + n1il11Oi <= wire_n1il1iil_dataout; + n1il11OO <= wire_n1il1iiO_dataout; + n1il1i0i <= wire_n1il1lOi_dataout; + n1il1i0l <= wire_n1il1lOl_dataout; + n1il1i1i <= wire_n1il1lli_dataout; + n1il1i1l <= wire_n1il1lll_dataout; + n1il1i1O <= wire_n1il1llO_dataout; + n1illOiO <= wire_n1iO11li_dataout; + n1ilOO0i <= wire_n1iO11Ol_dataout; + n1ilOO0l <= wire_n1iO11OO_dataout; + n1ilOO0O <= wire_n1iO101i_dataout; + n1ilOO1i <= wire_n1iO11ll_dataout; + n1ilOO1l <= wire_n1iO11lO_dataout; + n1ilOO1O <= wire_n1iO11Oi_dataout; + n1ilOOii <= wire_n1iO101l_dataout; + n1ilOOil <= wire_n1iO101O_dataout; + n1ilOOiO <= wire_n1iO100i_dataout; + n1ilOOli <= wire_n1iO100l_dataout; + n1ilOOll <= wire_n1iO100O_dataout; + n1ilOOlO <= wire_n1iO10ii_dataout; + n1ilOOOi <= wire_n1iO10il_dataout; + n1ilOOOl <= wire_n1iO10iO_dataout; + n1ilOOOO <= wire_n1iO10li_dataout; + n1iO001i <= wire_n1iO00ii_dataout; + n1iO001l <= wire_n1iO0lii_dataout; + n1iO01Oi <= wire_n1iO000i_dataout; + n1iO01Ol <= wire_n1iO000l_dataout; + n1iO01OO <= wire_n1iO000O_dataout; + n1iO0ili <= wire_n1iO0lil_dataout; + n1iO0ill <= wire_n1iO0liO_dataout; + n1iO0ilO <= wire_n1iO0lli_dataout; + n1iO0iOi <= wire_n1iO0lll_dataout; + n1iO0iOl <= wire_n1iO0llO_dataout; + n1iO0iOO <= wire_n1iO0lOi_dataout; + n1iO0l0i <= wire_n1iO0O1l_dataout; + n1iO0l0l <= wire_n1iO0O1O_dataout; + n1iO0l0O <= wire_n1iOl0OO_dataout; + n1iO0l1i <= wire_n1iO0lOl_dataout; + n1iO0l1l <= wire_n1iO0lOO_dataout; + n1iO0l1O <= wire_n1iO0O1i_dataout; + n1iO110i <= wire_n1iO10Ol_dataout; + n1iO110l <= wire_n1iO10OO_dataout; + n1iO110O <= wire_n1iO1i1i_dataout; + n1iO111i <= wire_n1iO10ll_dataout; + n1iO111l <= wire_n1iO10lO_dataout; + n1iO111O <= wire_n1iO10Oi_dataout; + n1iO11ii <= wire_n1iO1i1l_dataout; + n1iO11il <= wire_n1iO1i1O_dataout; + n1iO11iO <= wire_n1iO001O_dataout; + n1iOl00i <= wire_n1iOll1i_dataout; + n1iOl00l <= wire_n1iOll1l_dataout; + n1iOl00O <= wire_n1iOll1O_dataout; + n1iOl01i <= wire_n1iOliOi_dataout; + n1iOl01l <= wire_n1iOliOl_dataout; + n1iOl01O <= wire_n1iOliOO_dataout; + n1iOl0ii <= wire_n1iOll0i_dataout; + n1iOl0il <= wire_n1iOll0l_dataout; + n1iOl0iO <= wire_n1iOll0O_dataout; + n1iOl0li <= wire_n1iOllii_dataout; + n1iOl0ll <= wire_n1iOllil_dataout; + n1iOl0lO <= wire_n1iOlliO_dataout; + n1iOl0Oi <= wire_n1iOllli_dataout; + n1iOl0Ol <= wire_n1l11i1O_dataout; + n1iOl10i <= wire_n1iOli1i_dataout; + n1iOl10l <= wire_n1iOli1l_dataout; + n1iOl10O <= wire_n1iOli1O_dataout; + n1iOl1ii <= wire_n1iOli0i_dataout; + n1iOl1il <= wire_n1iOli0l_dataout; + n1iOl1iO <= wire_n1iOli0O_dataout; + n1iOl1li <= wire_n1iOliii_dataout; + n1iOl1ll <= wire_n1iOliil_dataout; + n1iOl1lO <= wire_n1iOliiO_dataout; + n1iOl1Oi <= wire_n1iOlili_dataout; + n1iOl1Ol <= wire_n1iOlill_dataout; + n1iOl1OO <= wire_n1iOlilO_dataout; + n1l0000i <= wire_n1l00lil_dataout; + n1l0000l <= wire_n1l00liO_dataout; + n1l0000O <= wire_n1l00lli_dataout; + n1l0001i <= wire_n1l00l0l_dataout; + n1l0001l <= wire_n1l00l0O_dataout; + n1l0001O <= wire_n1l00lii_dataout; + n1l000ii <= wire_n1l00lll_dataout; + n1l000il <= wire_n1l00llO_dataout; + n1l000iO <= wire_n1l00lOi_dataout; + n1l000li <= wire_n1l00lOl_dataout; + n1l000ll <= wire_n1l00lOO_dataout; + n1l000lO <= wire_n1l00O1i_dataout; + n1l000Oi <= wire_n1l00O1l_dataout; + n1l000Ol <= wire_n1l00O1O_dataout; + n1l000OO <= wire_n1l00O0i_dataout; + n1l0010i <= wire_n1l00iil_dataout; + n1l0010l <= wire_n1l00iiO_dataout; + n1l0010O <= wire_n1l00ili_dataout; + n1l0011l <= wire_n1l00i0O_dataout; + n1l0011O <= wire_n1l00iii_dataout; + n1l001ii <= wire_n1l00ill_dataout; + n1l001il <= wire_n1l00ilO_dataout; + n1l001iO <= wire_n1l00iOi_dataout; + n1l001li <= wire_n1l00iOl_dataout; + n1l001ll <= wire_n1l00iOO_dataout; + n1l001lO <= wire_n1l00l1i_dataout; + n1l001Oi <= wire_n1l00l1l_dataout; + n1l001Ol <= wire_n1l00l1O_dataout; + n1l001OO <= wire_n1l00l0i_dataout; + n1l00i0i <= wire_n1lil0OO_dataout; + n1l00i1i <= wire_n1l00O0l_dataout; + n1l00i1l <= wire_n1l00O0O_dataout; + n1l00i1O <= wire_n1l00Oii_dataout; + n1l10iiO <= wire_n1l10l1i_dataout; + n1l1100i <= wire_n1l110Oi_dataout; + n1l1100l <= wire_n1l110Ol_dataout; + n1l1100O <= wire_n1l110OO_dataout; + n1l1101i <= wire_n1l110li_dataout; + n1l1101l <= wire_n1l110ll_dataout; + n1l1101O <= wire_n1l110lO_dataout; + n1l110ii <= wire_n1l11i1i_dataout; + n1l110il <= wire_n1l11i1l_dataout; + n1l110iO <= wire_n1l10ili_dataout; + n1l1O1il <= wire_n1l1O01l_dataout; + n1l1O1iO <= wire_n1l1O01O_dataout; + n1l1O1li <= wire_n1l1O00i_dataout; + n1l1O1ll <= wire_n1l1O00l_dataout; + n1l1O1lO <= wire_n1l1O00O_dataout; + n1l1O1Oi <= wire_n1l1O0ii_dataout; + n1l1O1Ol <= wire_n1l1O0il_dataout; + n1l1O1OO <= wire_n1l1OOOO_dataout; + n1l1Ol0l <= wire_n1l1O01i_dataout; + n1l1Olll <= wire_n1l0111i_dataout; + n1l1OllO <= wire_n1l0111l_dataout; + n1l1OlOi <= wire_n1l0111O_dataout; + n1l1OlOl <= wire_n1l0110i_dataout; + n1l1OlOO <= wire_n1l0110l_dataout; + n1l1OO0i <= wire_n1l011iO_dataout; + n1l1OO0O <= wire_n1l011ll_dataout; + n1l1OO1i <= wire_n1l0110O_dataout; + n1l1OO1l <= wire_n1l011ii_dataout; + n1l1OO1O <= wire_n1l011il_dataout; + n1l1OOii <= wire_n1l011lO_dataout; + n1l1OOiO <= wire_n1l011Ol_dataout; + n1l1OOll <= wire_n1l0101i_dataout; + n1l1OOlO <= wire_n1l0101l_dataout; + n1l1OOOl <= wire_n1l00i0l_dataout; + n1lil0Ol <= wire_n1lili0O_dataout; + n1lili0l <= wire_n1lilOiO_dataout; + n1lilill <= wire_n1lilOli_dataout; + n1liliOi <= wire_n1lilOlO_dataout; + n1liliOl <= wire_n1lilOOi_dataout; + n1liliOO <= wire_n1lilOOl_dataout; + n1lill0i <= wire_n1liO11O_dataout; + n1lill0l <= wire_n1liO10i_dataout; + n1lill0O <= wire_n1liO10l_dataout; + n1lill1i <= wire_n1lilOOO_dataout; + n1lill1l <= wire_n1liO11i_dataout; + n1lill1O <= wire_n1liO11l_dataout; + n1lillii <= wire_n1liO10O_dataout; + n1lillil <= wire_n1liO1ii_dataout; + n1lilliO <= wire_n1liO1li_dataout; + n1lillli <= wire_n1liO1ll_dataout; + n1lillll <= wire_n1liO1lO_dataout; + n1lilllO <= wire_n1liO1Oi_dataout; + n1lillOi <= wire_n1liO1Ol_dataout; + n1lillOl <= wire_n1liO1OO_dataout; + n1lillOO <= wire_n1liO01i_dataout; + n1lilO0i <= wire_n1liO00l_dataout; + n1lilO0l <= wire_n1liO00O_dataout; + n1lilO1i <= wire_n1liO01l_dataout; + n1lilO1l <= wire_n1liO01O_dataout; + n1lilO1O <= wire_n1liO00i_dataout; + n1lilOii <= wire_n1liO1il_dataout; + n1lilOil <= wire_n1liO1iO_dataout; + n1llO1Ol <= wire_n1lO0lOO_dataout; + n1lO0llO <= wire_n1lO0O1i_dataout; + n1lO0lOi <= wire_n1lO0O1l_dataout; + n1lO0lOl <= wire_n1lOi0iO_dataout; + n1lOi00i <= wire_n1lOii1l_dataout; + n1lOi00l <= wire_n1lOii1O_dataout; + n1lOi00O <= wire_n1lOii0i_dataout; + n1lOi01i <= wire_n1lOi0Ol_dataout; + n1lOi01l <= wire_n1lOi0OO_dataout; + n1lOi01O <= wire_n1lOii1i_dataout; + n1lOi0il <= wire_n1lOOOOi_dataout; + n1lOi1lO <= wire_n1lOi0li_dataout; + n1lOi1Oi <= wire_n1lOi0ll_dataout; + n1lOi1Ol <= wire_n1lOi0lO_dataout; + n1lOi1OO <= wire_n1lOi0Oi_dataout; + n1lOO00i <= wire_n1O1101i_dataout; + n1lOO00l <= wire_n1O1101l_dataout; + n1lOO00O <= wire_n1O1101O_dataout; + n1lOO01i <= wire_n1O111Oi_dataout; + n1lOO01l <= wire_n1O111Ol_dataout; + n1lOO01O <= wire_n1O111OO_dataout; + n1lOO0ii <= wire_n1O1100i_dataout; + n1lOO0il <= wire_n1O1100l_dataout; + n1lOO0iO <= wire_n1O1100O_dataout; + n1lOO0li <= wire_n1O110ii_dataout; + n1lOO0ll <= wire_n1O110il_dataout; + n1lOO0lO <= wire_n1O110iO_dataout; + n1lOO0Oi <= wire_n1O110li_dataout; + n1lOO0Ol <= wire_n1O110ll_dataout; + n1lOO0OO <= wire_n1O110lO_dataout; + n1lOO10i <= wire_n1O1111i_dataout; + n1lOO10l <= wire_n1O1111l_dataout; + n1lOO10O <= wire_n1O1111O_dataout; + n1lOO11l <= wire_n1lOOOOl_dataout; + n1lOO11O <= wire_n1lOOOOO_dataout; + n1lOO1ii <= wire_n1O1110i_dataout; + n1lOO1il <= wire_n1O1110l_dataout; + n1lOO1iO <= wire_n1O1110O_dataout; + n1lOO1li <= wire_n1O111ii_dataout; + n1lOO1ll <= wire_n1O111il_dataout; + n1lOO1lO <= wire_n1O111iO_dataout; + n1lOO1Oi <= wire_n1O111li_dataout; + n1lOO1Ol <= wire_n1O111ll_dataout; + n1lOO1OO <= wire_n1O111lO_dataout; + n1lOOi0i <= wire_n1O11i1i_dataout; + n1lOOi0l <= wire_n1O11i1l_dataout; + n1lOOi0O <= wire_n1O11i1O_dataout; + n1lOOi1i <= wire_n1O110Oi_dataout; + n1lOOi1l <= wire_n1O110Ol_dataout; + n1lOOi1O <= wire_n1O110OO_dataout; + n1lOOiii <= wire_n1O11i0i_dataout; + n1lOOiil <= wire_n1O11i0l_dataout; + n1lOOiiO <= wire_n1O11i0O_dataout; + n1lOOili <= wire_n1O11iii_dataout; + n1lOOill <= wire_n1O11iil_dataout; + n1lOOilO <= wire_n1O11iiO_dataout; + n1lOOiOi <= wire_n1O11ili_dataout; + n1lOOiOl <= wire_n1O11ill_dataout; + n1lOOiOO <= wire_n1O11ilO_dataout; + n1lOOl0i <= wire_n1O11l1i_dataout; + n1lOOl0l <= wire_n1O11l1l_dataout; + n1lOOl0O <= wire_n1O11l1O_dataout; + n1lOOl1i <= wire_n1O11iOi_dataout; + n1lOOl1l <= wire_n1O11iOl_dataout; + n1lOOl1O <= wire_n1O11iOO_dataout; + n1lOOlii <= wire_n1O11l0i_dataout; + n1lOOlil <= wire_n1O11l0l_dataout; + n1lOOliO <= wire_n1O11l0O_dataout; + n1lOOlli <= wire_n1O11lii_dataout; + n1lOOlll <= wire_n1O11lil_dataout; + n1lOOllO <= wire_n1O11liO_dataout; + n1lOOlOi <= wire_n1O11lli_dataout; + n1lOOlOl <= wire_n1O11lll_dataout; + n1lOOlOO <= wire_n1O11llO_dataout; + n1lOOO0i <= wire_n1O11O1i_dataout; + n1lOOO0l <= wire_n1O11O1l_dataout; + n1lOOO0O <= wire_n1O11O1O_dataout; + n1lOOO1i <= wire_n1O11lOi_dataout; + n1lOOO1l <= wire_n1O11lOl_dataout; + n1lOOO1O <= wire_n1O11lOO_dataout; + n1lOOOii <= wire_n1O11O0i_dataout; + n1lOOOil <= wire_n1O11O0l_dataout; + n1lOOOiO <= wire_n1O11O0O_dataout; + n1lOOOli <= wire_n1O11Oii_dataout; + n1lOOOll <= wire_n1O11Oil_dataout; + n1lOOOlO <= wire_n1O11OiO_dataout; + n1O01iOO <= wire_n1O01OlO_dataout; + n1O01lll <= wire_n1O01OOi_dataout; + n1O01llO <= wire_n1O01OOl_dataout; + n1O01lOi <= wire_n1O01OOO_dataout; + n1O01lOl <= wire_n1O0011i_dataout; + n1O01lOO <= wire_n1O0011l_dataout; + n1O01O0i <= wire_n1O0010O_dataout; + n1O01O0l <= wire_n1O001ii_dataout; + n1O01O0O <= wire_n1O001il_dataout; + n1O01O1i <= wire_n1O0011O_dataout; + n1O01O1l <= wire_n1O0010i_dataout; + n1O01O1O <= wire_n1O0010l_dataout; + n1O01Oii <= wire_n1O001iO_dataout; + n1O01Oil <= wire_n1O001li_dataout; + n1O01OiO <= wire_n1O001ll_dataout; + n1O01Oli <= wire_n1O001lO_dataout; + n1O01Oll <= wire_n1O00l1i_dataout; + n1O0i00l <= wire_n1O0ii0O_dataout; + n1O0i00O <= wire_n1O0iiii_dataout; + n1O0i0ii <= wire_n1O0iiil_dataout; + n1O0i0il <= wire_n1O0iiiO_dataout; + n1O0i0iO <= wire_n1O0iili_dataout; + n1O0i0li <= wire_n1O0iill_dataout; + n1O0i0ll <= wire_n1O0iilO_dataout; + n1O0i0lO <= wire_n1O0iiOi_dataout; + n1O0i0Oi <= wire_n1O0iiOl_dataout; + n1O0i0Ol <= wire_n1O0iiOO_dataout; + n1O0i0OO <= wire_n1O0il1i_dataout; + n1O0i1iO <= wire_n1O0ii0l_dataout; + n1O0ii0i <= wire_n1O0il0l_dataout; + n1O0ii1i <= wire_n1O0il1l_dataout; + n1O0ii1l <= wire_n1O0il1O_dataout; + n1O0ii1O <= wire_n1O0il0i_dataout; + n1O0Oi0l <= wire_n1O0Oili_dataout; + n1O0Oi0O <= wire_n1O0Oill_dataout; + n1O0Oiii <= wire_n1O0OilO_dataout; + n1O0Oiil <= wire_n1O0OlOl_dataout; + n1O0Ol1i <= wire_n1O0OiiO_dataout; + n1O0Olli <= wire_n1O0OlOO_dataout; + n1O0Olll <= wire_n1O0OO1i_dataout; + n1O0OllO <= wire_n1O0OO1l_dataout; + n1O0OlOi <= wire_n1Oi100i_dataout; + n1Oi000i <= wire_n1OiO11l_dataout; + n1Oi001i <= wire_n1Oi0O1O_dataout; + n1Oi001l <= wire_n1Oi0O0i_dataout; + n1Oi001O <= wire_n1Oi0O0l_dataout; + n1Oi010i <= wire_n1Oi0l0O_dataout; + n1Oi010l <= wire_n1Oi0lii_dataout; + n1Oi010O <= wire_n1Oi0lil_dataout; + n1Oi011i <= wire_n1Oi0l1O_dataout; + n1Oi011l <= wire_n1Oi0l0i_dataout; + n1Oi011O <= wire_n1Oi0l0l_dataout; + n1Oi01ii <= wire_n1Oi0liO_dataout; + n1Oi01il <= wire_n1Oi0lli_dataout; + n1Oi01iO <= wire_n1Oi0lll_dataout; + n1Oi01li <= wire_n1Oi0llO_dataout; + n1Oi01ll <= wire_n1Oi0lOi_dataout; + n1Oi01lO <= wire_n1Oi0lOl_dataout; + n1Oi01Oi <= wire_n1Oi0lOO_dataout; + n1Oi01Ol <= wire_n1Oi0O1i_dataout; + n1Oi01OO <= wire_n1Oi0O1l_dataout; + n1Oi101O <= wire_n1Oi000l_dataout; + n1Oi11Oi <= wire_n1Oi100l_dataout; + n1Oi1l0i <= wire_n1Oi000O_dataout; + n1Oi1l0l <= wire_n1Oi00ii_dataout; + n1Oi1l0O <= wire_n1Oi00il_dataout; + n1Oi1lii <= wire_n1Oi00iO_dataout; + n1Oi1lil <= wire_n1Oi00li_dataout; + n1Oi1liO <= wire_n1Oi00ll_dataout; + n1Oi1lli <= wire_n1Oi00lO_dataout; + n1Oi1lll <= wire_n1Oi00Oi_dataout; + n1Oi1llO <= wire_n1Oi00Ol_dataout; + n1Oi1lOi <= wire_n1Oi00OO_dataout; + n1Oi1lOl <= wire_n1Oi0i1i_dataout; + n1Oi1lOO <= wire_n1Oi0i1l_dataout; + n1Oi1O0i <= wire_n1Oi0i0O_dataout; + n1Oi1O0l <= wire_n1Oi0iii_dataout; + n1Oi1O0O <= wire_n1Oi0iil_dataout; + n1Oi1O1i <= wire_n1Oi0i1O_dataout; + n1Oi1O1l <= wire_n1Oi0i0i_dataout; + n1Oi1O1O <= wire_n1Oi0i0l_dataout; + n1Oi1Oii <= wire_n1Oi0iiO_dataout; + n1Oi1Oil <= wire_n1Oi0ili_dataout; + n1Oi1OiO <= wire_n1Oi0ill_dataout; + n1Oi1Oli <= wire_n1Oi0ilO_dataout; + n1Oi1Oll <= wire_n1Oi0iOi_dataout; + n1Oi1OlO <= wire_n1Oi0iOl_dataout; + n1Oi1OOi <= wire_n1Oi0iOO_dataout; + n1Oi1OOl <= wire_n1Oi0l1i_dataout; + n1Oi1OOO <= wire_n1Oi0l1l_dataout; + n1Oili0i <= wire_n1OiO11O_dataout; + n1Oili0l <= wire_n1OiO10i_dataout; + n1Oili0O <= wire_n1OiO10l_dataout; + n1Oiliii <= wire_n1OiO10O_dataout; + n1Oiliil <= wire_n1OiO1ii_dataout; + n1OiliiO <= wire_n1OiO1il_dataout; + n1Oilili <= wire_n1OiO1iO_dataout; + n1Oilill <= wire_n1OiO1li_dataout; + n1OililO <= wire_n1OiO1ll_dataout; + n1OiliOi <= wire_n1OiO1lO_dataout; + n1OiliOl <= wire_n1OiO1Oi_dataout; + n1OiliOO <= wire_n1OiO1Ol_dataout; + n1Oill0i <= wire_n1OiO01O_dataout; + n1Oill0l <= wire_n1OiO00i_dataout; + n1Oill0O <= wire_n1OiO00l_dataout; + n1Oill1i <= wire_n1OiO1OO_dataout; + n1Oill1l <= wire_n1OiO01i_dataout; + n1Oill1O <= wire_n1OiO01l_dataout; + n1Oillii <= wire_n1OiO00O_dataout; + n1Oillil <= wire_n1OiO0ii_dataout; + n1OilliO <= wire_n1OiO0il_dataout; + n1Oillli <= wire_n1OiO0iO_dataout; + n1Oillll <= wire_n1OiO0li_dataout; + n1OilllO <= wire_n1OiO0ll_dataout; + n1OillOi <= wire_n1OiO0lO_dataout; + n1OillOl <= wire_n1OiO0Oi_dataout; + n1OillOO <= wire_n1OiO0Ol_dataout; + n1OilO0i <= wire_n1OiOi1O_dataout; + n1OilO0l <= wire_n1OiOi0i_dataout; + n1OilO0O <= wire_n1OiOi0l_dataout; + n1OilO1i <= wire_n1OiO0OO_dataout; + n1OilO1l <= wire_n1OiOi1i_dataout; + n1OilO1O <= wire_n1OiOi1l_dataout; + n1OilOii <= wire_n1OiOi0O_dataout; + n1OilOil <= wire_n1OiOiii_dataout; + n1OilOiO <= wire_n1OiOiil_dataout; + n1OilOli <= wire_n1OiOiiO_dataout; + n1OilOll <= wire_n1OiOili_dataout; + n1OiO11i <= wire_n1Ol011O_dataout; + n1Ol000i <= wire_n1Ol00OO_dataout; + n1Ol000l <= wire_n1Ol0i1i_dataout; + n1Ol000O <= wire_n1Ol0i1l_dataout; + n1Ol001l <= wire_n1Ol00Oi_dataout; + n1Ol001O <= wire_n1Ol00Ol_dataout; + n1Ol00ii <= wire_n1Ol0i1O_dataout; + n1Ol00il <= wire_n1Ol0i0i_dataout; + n1Ol00iO <= wire_n1Ol0i0l_dataout; + n1Ol00li <= wire_n1Ol0i0O_dataout; + n1Ol00ll <= wire_n1Ol0lOO_dataout; + n1Ol011i <= wire_n1Ol010O_dataout; + n1Ol011l <= wire_n1Ol00lO_dataout; + n1Ol0lil <= wire_n1Ol0O1i_dataout; + n1Ol0liO <= wire_n1Ol0O1l_dataout; + n1Ol0lli <= wire_n1Ol0O1O_dataout; + n1Ol0lll <= wire_n1Ol0O0i_dataout; + n1Ol0llO <= wire_n1Ol0O0l_dataout; + n1Ol0lOi <= wire_n1Ol0O0O_dataout; + n1Ol1OOl <= wire_n1Ol010i_dataout; + n1Ol1OOO <= wire_n1Ol010l_dataout; + n1Oli00i <= wire_n1Olil1i_dataout; + n1Oli00l <= wire_n1Olil1l_dataout; + n1Oli00O <= wire_n1Olil1O_dataout; + n1Oli0ii <= wire_n1Olil0i_dataout; + n1Oli0il <= wire_n1Olil0l_dataout; + n1Oli0iO <= wire_n1Olil0O_dataout; + n1Oli0li <= wire_n1Olilii_dataout; + n1Oli0ll <= wire_n1Olilil_dataout; + n1Oli0lO <= wire_n1OliliO_dataout; + n1Oli0Oi <= wire_n1Olilli_dataout; + n1Oli0Ol <= wire_n1Olilll_dataout; + n1Oli0OO <= wire_n1OlillO_dataout; + n1Olii0i <= wire_n1OliO1i_dataout; + n1Olii0l <= wire_n1OliO1l_dataout; + n1Olii0O <= wire_n1OliO1O_dataout; + n1Olii1i <= wire_n1OlilOi_dataout; + n1Olii1l <= wire_n1OlilOl_dataout; + n1Olii1O <= wire_n1OlilOO_dataout; + n1Oliiii <= wire_n1OliO0i_dataout; + n1Oliiil <= wire_n1OliO0l_dataout; + n1OliiiO <= wire_n1OliO0O_dataout; + n1Oliili <= wire_n1OliOii_dataout; + n1Oliill <= wire_n1OliOil_dataout; + n1OliilO <= wire_n1OliOiO_dataout; + n1OliiOi <= wire_n1OliOll_dataout; + n1OliiOl <= wire_n1OliOli_dataout; + n1Oll0li <= wire_n1OO0OlO_dataout; + n1OO0lll <= wire_n1OO0OOi_dataout; + n1OO0llO <= wire_n1OO0OOl_dataout; + n1OO0lOi <= wire_n1OO0OOO_dataout; + n1OO0lOl <= wire_n1OOi11i_dataout; + n1OO0lOO <= wire_n1OOi11l_dataout; + n1OO0O0i <= wire_n1OOi10O_dataout; + n1OO0O0l <= wire_n1OOi1ii_dataout; + n1OO0O0O <= wire_n1OOi1il_dataout; + n1OO0O1i <= wire_n1OOi11O_dataout; + n1OO0O1l <= wire_n1OOi10i_dataout; + n1OO0O1O <= wire_n1OOi10l_dataout; + n1OO0Oii <= wire_n1OOi1iO_dataout; + n1OO0Oil <= wire_n1OOi1li_dataout; + n1OO0OiO <= wire_n1OOi1ll_dataout; + n1OO0Oli <= wire_n1OOi1lO_dataout; + n1OO0Oll <= wire_n1OOi1Oi_dataout; + n1OOl00i <= wire_n1OOll1i_dataout; + n1OOl0OO <= wire_n1OOll1l_dataout; + n1OOli0i <= wire_n1OOll0O_dataout; + n1OOli0l <= wire_n1OOllii_dataout; + n1OOli0O <= wire_n1OOllil_dataout; + n1OOli1i <= wire_n1OOll1O_dataout; + n1OOli1l <= wire_n1OOll0i_dataout; + n1OOli1O <= wire_n1OOll0l_dataout; + n1OOliii <= wire_n1OOlliO_dataout; + n1OOliil <= wire_n1OOllli_dataout; + n1OOliiO <= wire_n1OOllll_dataout; + n1OOlili <= wire_n1OOlllO_dataout; + n1OOlill <= wire_n1OOllOi_dataout; + n1OOlilO <= wire_n1OOllOl_dataout; + n1OOliOi <= wire_n1OOllOO_dataout; + n1OOliOl <= wire_n1OOlO1i_dataout; + n1OOliOO <= wire_n1OOO00l_dataout; + n1OOOlOi <= wire_n01111iO_dataout; + n1OOOOiO <= wire_n01111li_dataout; + n1OOOOli <= wire_n01111ll_dataout; + n1OOOOll <= wire_n01111lO_dataout; + n1OOOOlO <= wire_n01111Oi_dataout; + n1OOOOOi <= wire_n01111Ol_dataout; + n1OOOOOl <= wire_n01111OO_dataout; + n1OOOOOO <= wire_n011101i_dataout; + ni00011i <= wire_ni000ilO_dataout; + ni000i0i <= wire_ni000iOl_dataout; + ni000i0l <= wire_ni000iOO_dataout; + ni000i0O <= wire_ni000l1i_dataout; + ni000i1O <= wire_ni000iOi_dataout; + ni000iii <= wire_ni000l1l_dataout; + ni000iil <= wire_ni000l1O_dataout; + ni000iiO <= wire_ni000l0i_dataout; + ni000ili <= wire_ni000l0l_dataout; + ni000ill <= wire_ni00i1ii_dataout; + ni000OOi <= wire_ni00i1il_dataout; + ni000OOl <= wire_ni00i1iO_dataout; + ni000OOO <= wire_ni00i1li_dataout; + ni0010Oi <= wire_ni001iil_dataout; + ni0010Ol <= wire_ni001iiO_dataout; + ni0010OO <= wire_ni001ili_dataout; + ni001i0i <= wire_ni001iOl_dataout; + ni001i0l <= wire_ni001iOO_dataout; + ni001i0O <= wire_ni00011l_dataout; + ni001i1i <= wire_ni001ill_dataout; + ni001i1l <= wire_ni001ilO_dataout; + ni001i1O <= wire_ni001iOi_dataout; + ni001Oil <= wire_ni00011O_dataout; + ni001OiO <= wire_ni00010i_dataout; + ni001Oli <= wire_ni00010l_dataout; + ni001Oll <= wire_ni00010O_dataout; + ni001OlO <= wire_ni0001ii_dataout; + ni001OOi <= wire_ni0001il_dataout; + ni001OOl <= wire_ni0001iO_dataout; + ni001OOO <= wire_ni0001li_dataout; + ni00i10i <= wire_ni00i1Ol_dataout; + ni00i10l <= wire_ni00i1OO_dataout; + ni00i10O <= wire_ni00il1l_dataout; + ni00i11i <= wire_ni00i1ll_dataout; + ni00i11l <= wire_ni00i1lO_dataout; + ni00i11O <= wire_ni00i1Oi_dataout; + ni00iiil <= wire_ni00il1O_dataout; + ni00iiiO <= wire_ni00il0i_dataout; + ni00iili <= wire_ni00il0l_dataout; + ni00iill <= wire_ni00il0O_dataout; + ni00iilO <= wire_ni00ilii_dataout; + ni00iiOi <= wire_ni00ilil_dataout; + ni00iiOl <= wire_ni00iliO_dataout; + ni00iiOO <= wire_ni00illi_dataout; + ni00il1i <= wire_ni00l1lO_dataout; + ni00l10i <= wire_ni00l1Ol_dataout; + ni00l10l <= wire_ni00l1OO_dataout; + ni00l10O <= wire_ni00l01i_dataout; + ni00l11O <= wire_ni00l1Oi_dataout; + ni00l1ii <= wire_ni00l01l_dataout; + ni00l1il <= wire_ni00l01O_dataout; + ni00l1iO <= wire_ni00l00i_dataout; + ni00l1li <= wire_ni00l00l_dataout; + ni00l1ll <= wire_ni00ll1l_dataout; + ni00liOi <= wire_ni00ll1O_dataout; + ni00liOl <= wire_ni00ll0i_dataout; + ni00liOO <= wire_ni00ll0l_dataout; + ni00ll1i <= wire_ni00ll0O_dataout; + ni01000i <= wire_ni0100Ol_dataout; + ni01000l <= wire_ni0100OO_dataout; + ni01000O <= wire_ni010i1i_dataout; + ni01001i <= wire_ni0100ll_dataout; + ni01001l <= wire_ni0100lO_dataout; + ni01001O <= wire_ni0100Oi_dataout; + ni0100ii <= wire_ni010i1l_dataout; + ni0100il <= wire_ni010i1O_dataout; + ni0100iO <= wire_ni010O0l_dataout; + ni010lll <= wire_ni010O0O_dataout; + ni010llO <= wire_ni010Oii_dataout; + ni010lOi <= wire_ni010Oil_dataout; + ni010lOl <= wire_ni010OiO_dataout; + ni010lOO <= wire_ni010Oli_dataout; + ni010O0i <= wire_ni01i0OO_dataout; + ni010O1i <= wire_ni010Oll_dataout; + ni010O1l <= wire_ni010OlO_dataout; + ni010O1O <= wire_ni010OOi_dataout; + ni01100i <= wire_ni011lOO_dataout; + ni01101i <= wire_ni0110ll_dataout; + ni01101l <= wire_ni0110lO_dataout; + ni01101O <= wire_ni0110Oi_dataout; + ni0111li <= wire_ni1OOlOi_dataout; + ni0111ll <= wire_ni01100O_dataout; + ni0111lO <= wire_ni0110ii_dataout; + ni0111Oi <= wire_ni0110il_dataout; + ni0111Ol <= wire_ni0110iO_dataout; + ni0111OO <= wire_ni0110li_dataout; + ni011l0O <= wire_ni011O1i_dataout; + ni011lii <= wire_ni011O1l_dataout; + ni011lil <= wire_ni011O1O_dataout; + ni011liO <= wire_ni011O0i_dataout; + ni011lli <= wire_ni011O0l_dataout; + ni011lll <= wire_ni011O0O_dataout; + ni011llO <= wire_ni011Oii_dataout; + ni011lOi <= wire_ni011Oil_dataout; + ni011lOl <= wire_ni0100li_dataout; + ni01i00O <= wire_ni01ii1i_dataout; + ni01i0ii <= wire_ni01ii1l_dataout; + ni01i0il <= wire_ni01ii1O_dataout; + ni01i0iO <= wire_ni01ii0i_dataout; + ni01i0li <= wire_ni01ii0l_dataout; + ni01i0ll <= wire_ni01ii0O_dataout; + ni01i0lO <= wire_ni01iiii_dataout; + ni01i0Oi <= wire_ni01iiil_dataout; + ni01i0Ol <= wire_ni01iOli_dataout; + ni01iO0i <= wire_ni01iOOl_dataout; + ni01iO0l <= wire_ni01iOOO_dataout; + ni01iO0O <= wire_ni01l11i_dataout; + ni01iO1i <= wire_ni01iOll_dataout; + ni01iO1l <= wire_ni01iOlO_dataout; + ni01iO1O <= wire_ni01iOOi_dataout; + ni01iOii <= wire_ni01l11l_dataout; + ni01iOil <= wire_ni01l11O_dataout; + ni01iOiO <= wire_ni01li0l_dataout; + ni01l0ll <= wire_ni01li0O_dataout; + ni01l0lO <= wire_ni01liii_dataout; + ni01l0Oi <= wire_ni01liil_dataout; + ni01l0Ol <= wire_ni01liiO_dataout; + ni01l0OO <= wire_ni01lili_dataout; + ni01li0i <= wire_ni01lOli_dataout; + ni01li1i <= wire_ni01lill_dataout; + ni01li1l <= wire_ni01lilO_dataout; + ni01li1O <= wire_ni01liOi_dataout; + ni01lO0O <= wire_ni01lOll_dataout; + ni01lOii <= wire_ni01lOlO_dataout; + ni01lOil <= wire_ni01lOOi_dataout; + ni01lOiO <= wire_ni01lOOl_dataout; + ni01O0ll <= wire_ni01Oi0O_dataout; + ni01O0lO <= wire_ni01Oiii_dataout; + ni01O0Oi <= wire_ni01Oiil_dataout; + ni01O0Ol <= wire_ni01OiiO_dataout; + ni01O0OO <= wire_ni01Oili_dataout; + ni01Oi0i <= wire_ni01OOlO_dataout; + ni01Oi1i <= wire_ni01Oill_dataout; + ni01Oi1l <= wire_ni01OilO_dataout; + ni01Oi1O <= wire_ni01OiOi_dataout; + ni01OO0i <= wire_ni01OOOl_dataout; + ni01OO0l <= wire_ni01OOOO_dataout; + ni01OO0O <= wire_ni00111i_dataout; + ni01OO1l <= wire_ni01Oi0l_dataout; + ni01OO1O <= wire_ni01OOOi_dataout; + ni01OOii <= wire_ni00111l_dataout; + ni01OOil <= wire_ni00111O_dataout; + ni01OOiO <= wire_ni00110i_dataout; + ni01OOli <= wire_ni00110l_dataout; + ni01OOll <= wire_ni001iii_dataout; + ni0i000i <= wire_ni0iiili_dataout; + ni0i000l <= wire_ni0iiill_dataout; + ni0i000O <= wire_ni0iiilO_dataout; + ni0i001i <= wire_ni0iiiii_dataout; + ni0i001l <= wire_ni0iiiil_dataout; + ni0i001O <= wire_ni0iiiiO_dataout; + ni0i00ii <= wire_ni0iiiOi_dataout; + ni0i00il <= wire_ni0iiiOl_dataout; + ni0i00iO <= wire_ni0iiiOO_dataout; + ni0i00li <= wire_ni0iil1i_dataout; + ni0i00ll <= wire_ni0iil1l_dataout; + ni0i00lO <= wire_ni0iil1O_dataout; + ni0i00Oi <= wire_ni0iil0i_dataout; + ni0i00Ol <= wire_ni0iil0l_dataout; + ni0i00OO <= wire_ni0iil0O_dataout; + ni0i010i <= wire_ni0ii0li_dataout; + ni0i010l <= wire_ni0ii0ll_dataout; + ni0i010O <= wire_ni0ii0lO_dataout; + ni0i011i <= wire_ni0ii0ii_dataout; + ni0i011l <= wire_ni0ii0il_dataout; + ni0i011O <= wire_ni0ii0iO_dataout; + ni0i01ii <= wire_ni0ii0Oi_dataout; + ni0i01il <= wire_ni0ii0Ol_dataout; + ni0i01iO <= wire_ni0ii0OO_dataout; + ni0i01li <= wire_ni0iii1i_dataout; + ni0i01ll <= wire_ni0iii1l_dataout; + ni0i01lO <= wire_ni0iii1O_dataout; + ni0i01Oi <= wire_ni0iii0i_dataout; + ni0i01Ol <= wire_ni0iii0l_dataout; + ni0i01OO <= wire_ni0iii0O_dataout; + ni0i0i0i <= wire_ni0iilli_dataout; + ni0i0i0l <= wire_ni0iilll_dataout; + ni0i0i0O <= wire_nii0li1O_dataout; + ni0i0i1i <= wire_ni0iilii_dataout; + ni0i0i1l <= wire_ni0iilil_dataout; + ni0i0i1O <= wire_ni0iiliO_dataout; + ni0i100i <= wire_ni0i0ili_dataout; + ni0i100l <= wire_ni0i0ill_dataout; + ni0i100O <= wire_ni0i0ilO_dataout; + ni0i101i <= wire_ni0i110O_dataout; + ni0i101l <= wire_ni0i0iil_dataout; + ni0i101O <= wire_ni0i0iiO_dataout; + ni0i10ii <= wire_ni0i0iOi_dataout; + ni0i10il <= wire_ni0i0iOl_dataout; + ni0i10iO <= wire_ni0i0iOO_dataout; + ni0i10li <= wire_ni0i0l1i_dataout; + ni0i10ll <= wire_ni0i0l1l_dataout; + ni0i10lO <= wire_ni0i0l1O_dataout; + ni0i10Oi <= wire_ni0i0l0i_dataout; + ni0i10Ol <= wire_ni0i0l0l_dataout; + ni0i10OO <= wire_ni0i0l0O_dataout; + ni0i110i <= wire_ni0i11iO_dataout; + ni0i110l <= wire_ni0i0iii_dataout; + ni0i111l <= wire_ni0i11ii_dataout; + ni0i111O <= wire_ni0i11il_dataout; + ni0i1i0i <= wire_ni0i0lli_dataout; + ni0i1i0l <= wire_ni0i0lll_dataout; + ni0i1i0O <= wire_ni0i0llO_dataout; + ni0i1i1i <= wire_ni0i0lii_dataout; + ni0i1i1l <= wire_ni0i0lil_dataout; + ni0i1i1O <= wire_ni0i0liO_dataout; + ni0i1iii <= wire_ni0i0lOi_dataout; + ni0i1iil <= wire_ni0i0lOl_dataout; + ni0i1iiO <= wire_ni0i0lOO_dataout; + ni0i1ili <= wire_ni0i0O1i_dataout; + ni0i1ill <= wire_ni0i0O1l_dataout; + ni0i1ilO <= wire_ni0i0O1O_dataout; + ni0i1iOi <= wire_ni0i0O0i_dataout; + ni0i1iOl <= wire_ni0i0O0l_dataout; + ni0i1iOO <= wire_ni0i0O0O_dataout; + ni0i1l0i <= wire_ni0i0Oli_dataout; + ni0i1l0l <= wire_ni0i0Oll_dataout; + ni0i1l0O <= wire_ni0i0OlO_dataout; + ni0i1l1i <= wire_ni0i0Oii_dataout; + ni0i1l1l <= wire_ni0i0Oil_dataout; + ni0i1l1O <= wire_ni0i0OiO_dataout; + ni0i1lii <= wire_ni0i0OOi_dataout; + ni0i1lil <= wire_ni0i0OOl_dataout; + ni0i1liO <= wire_ni0i0OOO_dataout; + ni0i1lli <= wire_ni0ii11i_dataout; + ni0i1lll <= wire_ni0ii11l_dataout; + ni0i1llO <= wire_ni0ii11O_dataout; + ni0i1lOi <= wire_ni0ii10i_dataout; + ni0i1lOl <= wire_ni0ii10l_dataout; + ni0i1lOO <= wire_ni0ii10O_dataout; + ni0i1O0i <= wire_ni0ii1li_dataout; + ni0i1O0l <= wire_ni0ii1ll_dataout; + ni0i1O0O <= wire_ni0ii1lO_dataout; + ni0i1O1i <= wire_ni0ii1ii_dataout; + ni0i1O1l <= wire_ni0ii1il_dataout; + ni0i1O1O <= wire_ni0ii1iO_dataout; + ni0i1Oii <= wire_ni0ii1Oi_dataout; + ni0i1Oil <= wire_ni0ii1Ol_dataout; + ni0i1OiO <= wire_ni0ii1OO_dataout; + ni0i1Oli <= wire_ni0ii01i_dataout; + ni0i1Oll <= wire_ni0ii01l_dataout; + ni0i1OlO <= wire_ni0ii01O_dataout; + ni0i1OOi <= wire_ni0ii00i_dataout; + ni0i1OOl <= wire_ni0ii00l_dataout; + ni0i1OOO <= wire_ni0ii00O_dataout; + ni1000lO <= wire_ni101OOO_dataout; + ni1000Oi <= wire_ni100iil_dataout; + ni1000Ol <= wire_ni100iiO_dataout; + ni1000OO <= wire_ni100ili_dataout; + ni100i0i <= wire_ni100iOl_dataout; + ni100i0l <= wire_ni100iOO_dataout; + ni100i0O <= wire_ni10i11l_dataout; + ni100i1i <= wire_ni100ill_dataout; + ni100i1l <= wire_ni100ilO_dataout; + ni100i1O <= wire_ni100iOi_dataout; + ni100Oil <= wire_ni10i11O_dataout; + ni100OiO <= wire_ni10i10i_dataout; + ni100Oli <= wire_ni10i10l_dataout; + ni100Oll <= wire_ni10i10O_dataout; + ni100OlO <= wire_ni10i1ii_dataout; + ni100OOi <= wire_ni10i1il_dataout; + ni100OOl <= wire_ni10i1iO_dataout; + ni100OOO <= wire_ni10i1li_dataout; + ni101i0i <= wire_ni101iiO_dataout; + ni101i1i <= wire_ni101i0O_dataout; + ni101i1l <= wire_ni101iii_dataout; + ni101i1O <= wire_ni101iil_dataout; + ni101O0O <= wire_ni10011i_dataout; + ni101Oii <= wire_ni10011l_dataout; + ni101Oil <= wire_ni10011O_dataout; + ni101OiO <= wire_ni10010i_dataout; + ni101Oli <= wire_ni10010l_dataout; + ni101Oll <= wire_ni10010O_dataout; + ni101OlO <= wire_ni1001ii_dataout; + ni101OOi <= wire_ni1001il_dataout; + ni101OOl <= wire_ni100iii_dataout; + ni10i11i <= wire_ni10iilO_dataout; + ni10ii0i <= wire_ni10iiOl_dataout; + ni10ii0l <= wire_ni10iiOO_dataout; + ni10ii0O <= wire_ni10il1i_dataout; + ni10ii1O <= wire_ni10iiOi_dataout; + ni10iiii <= wire_ni10il1l_dataout; + ni10iiil <= wire_ni10il1O_dataout; + ni10iiiO <= wire_ni10il0i_dataout; + ni10iili <= wire_ni10il0l_dataout; + ni10iill <= wire_ni10l1ii_dataout; + ni10iOOi <= wire_ni10l1il_dataout; + ni10iOOl <= wire_ni10l1iO_dataout; + ni10iOOO <= wire_ni10l1li_dataout; + ni10l10i <= wire_ni10l1Ol_dataout; + ni10l10l <= wire_ni10l1OO_dataout; + ni10l10O <= wire_ni10ll1l_dataout; + ni10l11i <= wire_ni10l1ll_dataout; + ni10l11l <= wire_ni10l1lO_dataout; + ni10l11O <= wire_ni10l1Oi_dataout; + ni10liil <= wire_ni10ll1O_dataout; + ni10liiO <= wire_ni10ll0i_dataout; + ni10lili <= wire_ni10ll0l_dataout; + ni10lill <= wire_ni10ll0O_dataout; + ni10lilO <= wire_ni10llii_dataout; + ni10liOi <= wire_ni10llil_dataout; + ni10liOl <= wire_ni10lliO_dataout; + ni10liOO <= wire_ni10llli_dataout; + ni10ll1i <= wire_ni10O1lO_dataout; + ni10O10i <= wire_ni10O1Ol_dataout; + ni10O10l <= wire_ni10O1OO_dataout; + ni10O10O <= wire_ni10O01i_dataout; + ni10O11O <= wire_ni10O1Oi_dataout; + ni10O1ii <= wire_ni10O01l_dataout; + ni10O1il <= wire_ni10O01O_dataout; + ni10O1iO <= wire_ni10O00i_dataout; + ni10O1li <= wire_ni10O00l_dataout; + ni10O1ll <= wire_ni10Olii_dataout; + ni10OiOi <= wire_ni10Olil_dataout; + ni10OiOl <= wire_ni10OliO_dataout; + ni10OiOO <= wire_ni10Olli_dataout; + ni10Ol0i <= wire_ni10OlOl_dataout; + ni10Ol0l <= wire_ni10OlOO_dataout; + ni10Ol0O <= wire_ni1i11lO_dataout; + ni10Ol1i <= wire_ni10Olll_dataout; + ni10Ol1l <= wire_ni10OllO_dataout; + ni10Ol1O <= wire_ni10OlOi_dataout; + ni11000i <= wire_ni1100Ol_dataout; + ni11000l <= wire_ni1100OO_dataout; + ni11000O <= wire_ni110i1i_dataout; + ni11001i <= wire_ni1100ll_dataout; + ni11001l <= wire_ni1100lO_dataout; + ni11001O <= wire_ni1100Oi_dataout; + ni1100ii <= wire_ni110lOO_dataout; + ni1101Ol <= wire_ni1100iO_dataout; + ni1101OO <= wire_ni1100li_dataout; + ni110l0l <= wire_ni1100il_dataout; + ni110l0O <= wire_ni110O1i_dataout; + ni110lii <= wire_ni110O1l_dataout; + ni110lil <= wire_ni110O1O_dataout; + ni110liO <= wire_ni110O0i_dataout; + ni110lli <= wire_ni110O0l_dataout; + ni110lll <= wire_ni110O0O_dataout; + ni110llO <= wire_ni110Oii_dataout; + ni110lOi <= wire_ni110Oil_dataout; + ni110lOl <= wire_ni11i0li_dataout; + ni11100i <= wire_ni1110Ol_dataout; + ni11100l <= wire_ni1110OO_dataout; + ni11100O <= wire_ni111i1i_dataout; + ni11101i <= wire_ni1110ll_dataout; + ni11101l <= wire_ni1110lO_dataout; + ni11101O <= wire_ni1110Oi_dataout; + ni1110ii <= wire_ni111lOi_dataout; + ni1111Ol <= wire_ni1110iO_dataout; + ni1111OO <= wire_ni1110li_dataout; + ni111liO <= wire_ni111lOl_dataout; + ni111lli <= wire_ni111lOO_dataout; + ni111lll <= wire_ni111O1i_dataout; + ni111llO <= wire_ni111O1l_dataout; + ni11i00i <= wire_ni11i0Ol_dataout; + ni11i00l <= wire_ni11i0OO_dataout; + ni11i00O <= wire_ni11ii1i_dataout; + ni11i01i <= wire_ni11i0ll_dataout; + ni11i01l <= wire_ni11i0lO_dataout; + ni11i01O <= wire_ni11i0Oi_dataout; + ni11i0ii <= wire_ni11ii1l_dataout; + ni11i0il <= wire_ni11ii1O_dataout; + ni11i0iO <= wire_ni11iO0l_dataout; + ni11illl <= wire_ni11iO0O_dataout; + ni11illO <= wire_ni11iOii_dataout; + ni11ilOi <= wire_ni11iOil_dataout; + ni11ilOl <= wire_ni11iOiO_dataout; + ni11ilOO <= wire_ni11iOli_dataout; + ni11iO0i <= wire_ni11l0OO_dataout; + ni11iO1i <= wire_ni11iOll_dataout; + ni11iO1l <= wire_ni11iOlO_dataout; + ni11iO1O <= wire_ni11iOOi_dataout; + ni11l00O <= wire_ni11li1i_dataout; + ni11l0ii <= wire_ni11li1l_dataout; + ni11l0il <= wire_ni11li1O_dataout; + ni11l0iO <= wire_ni11li0i_dataout; + ni11l0li <= wire_ni11li0l_dataout; + ni11l0ll <= wire_ni11li0O_dataout; + ni11l0lO <= wire_ni11liii_dataout; + ni11l0Oi <= wire_ni11liil_dataout; + ni11l0Ol <= wire_ni11lOli_dataout; + ni11lO0i <= wire_ni11lOOl_dataout; + ni11lO0l <= wire_ni11lOOO_dataout; + ni11lO0O <= wire_ni11O11i_dataout; + ni11lO1i <= wire_ni11lOll_dataout; + ni11lO1l <= wire_ni11lOlO_dataout; + ni11lO1O <= wire_ni11lOOi_dataout; + ni11lOii <= wire_ni11O11l_dataout; + ni11lOil <= wire_ni11O11O_dataout; + ni11lOiO <= wire_ni11Oi0l_dataout; + ni11O0ll <= wire_ni11Oi0O_dataout; + ni11O0lO <= wire_ni11Oiii_dataout; + ni11O0Oi <= wire_ni11Oiil_dataout; + ni11O0Ol <= wire_ni11OiiO_dataout; + ni11O0OO <= wire_ni11Oili_dataout; + ni11Oi0i <= wire_ni11OOOO_dataout; + ni11Oi1i <= wire_ni11Oill_dataout; + ni11Oi1l <= wire_ni11OilO_dataout; + ni11Oi1O <= wire_ni11OiOi_dataout; + ni11OO0O <= wire_ni10111i_dataout; + ni11OOii <= wire_ni10111l_dataout; + ni11OOil <= wire_ni10111O_dataout; + ni11OOiO <= wire_ni10110i_dataout; + ni11OOli <= wire_ni10110l_dataout; + ni11OOll <= wire_ni10110O_dataout; + ni11OOlO <= wire_ni1011ii_dataout; + ni11OOOi <= wire_ni1011il_dataout; + ni11OOOl <= wire_ni101i0l_dataout; + ni1i010i <= wire_ni1i1lii_dataout; + ni1i010l <= wire_ni1i01OO_dataout; + ni1i010O <= wire_ni1i001i_dataout; + ni1i01ii <= wire_ni1i001l_dataout; + ni1i01il <= wire_ni1i001O_dataout; + ni1i01iO <= wire_ni1i000i_dataout; + ni1i01li <= wire_ni1i000l_dataout; + ni1i01ll <= wire_ni1i000O_dataout; + ni1i01lO <= wire_ni1i00ii_dataout; + ni1i01Oi <= wire_ni1i0liO_dataout; + ni1i0iOO <= wire_ni1i0lli_dataout; + ni1i0l0i <= wire_ni1i0lOl_dataout; + ni1i0l0l <= wire_ni1i0lOO_dataout; + ni1i0l0O <= wire_ni1i0O1i_dataout; + ni1i0l1i <= wire_ni1i0lll_dataout; + ni1i0l1l <= wire_ni1i0llO_dataout; + ni1i0l1O <= wire_ni1i0lOi_dataout; + ni1i0lii <= wire_ni1i0O1l_dataout; + ni1i0lil <= wire_ni1ii00i_dataout; + ni1i11il <= wire_ni1i11Oi_dataout; + ni1i11iO <= wire_ni1i11Ol_dataout; + ni1i11li <= wire_ni1i11OO_dataout; + ni1i11ll <= wire_ni1i101i_dataout; + ni1i1iOi <= wire_ni1i1lil_dataout; + ni1i1iOl <= wire_ni1i1liO_dataout; + ni1i1iOO <= wire_ni1i1lli_dataout; + ni1i1l0i <= wire_ni1i1lOl_dataout; + ni1i1l0l <= wire_ni1i1lOO_dataout; + ni1i1l0O <= wire_ni1i01Ol_dataout; + ni1i1l1i <= wire_ni1i1lll_dataout; + ni1i1l1l <= wire_ni1i1llO_dataout; + ni1i1l1O <= wire_ni1i1lOi_dataout; + ni1ii01i <= wire_ni1ii0ll_dataout; + ni1ii01l <= wire_ni1ii0lO_dataout; + ni1ii01O <= wire_ni1iilOl_dataout; + ni1ii1li <= wire_ni1ii00l_dataout; + ni1ii1ll <= wire_ni1ii00O_dataout; + ni1ii1lO <= wire_ni1ii0ii_dataout; + ni1ii1Oi <= wire_ni1ii0il_dataout; + ni1ii1Ol <= wire_ni1ii0iO_dataout; + ni1ii1OO <= wire_ni1ii0li_dataout; + ni1iil0l <= wire_ni1iilOO_dataout; + ni1iil0O <= wire_ni1iiO1i_dataout; + ni1iilii <= wire_ni1iiO1l_dataout; + ni1iilil <= wire_ni1iiO1O_dataout; + ni1iiliO <= wire_ni1iiO0i_dataout; + ni1iilli <= wire_ni1iiO0l_dataout; + ni1iilll <= wire_ni1iiO0O_dataout; + ni1iillO <= wire_ni1iiOii_dataout; + ni1iilOi <= wire_ni1il0iO_dataout; + ni1il00i <= wire_ni1il0Ol_dataout; + ni1il00l <= wire_ni1il0OO_dataout; + ni1il00O <= wire_ni1ili1i_dataout; + ni1il01i <= wire_ni1il0ll_dataout; + ni1il01l <= wire_ni1il0lO_dataout; + ni1il01O <= wire_ni1il0Oi_dataout; + ni1il0ii <= wire_ni1ili1l_dataout; + ni1il0il <= wire_ni1ilO0i_dataout; + ni1il1OO <= wire_ni1il0li_dataout; + ni1illli <= wire_ni1ilO0l_dataout; + ni1illll <= wire_ni1ilO0O_dataout; + ni1illlO <= wire_ni1ilOii_dataout; + ni1illOi <= wire_ni1ilOil_dataout; + ni1illOl <= wire_ni1ilOiO_dataout; + ni1illOO <= wire_ni1ilOli_dataout; + ni1ilO1i <= wire_ni1ilOll_dataout; + ni1ilO1l <= wire_ni1ilOlO_dataout; + ni1ilO1O <= wire_ni1iO0Ol_dataout; + ni1iO00l <= wire_ni1iO0OO_dataout; + ni1iO00O <= wire_ni1iOi1i_dataout; + ni1iO0ii <= wire_ni1iOi1l_dataout; + ni1iO0il <= wire_ni1iOi1O_dataout; + ni1iO0iO <= wire_ni1iOi0i_dataout; + ni1iO0li <= wire_ni1iOi0l_dataout; + ni1iO0ll <= wire_ni1iOi0O_dataout; + ni1iO0lO <= wire_ni1iOiii_dataout; + ni1iO0Oi <= wire_ni1iOO0i_dataout; + ni1iOlOO <= wire_ni1iOO0l_dataout; + ni1iOO1i <= wire_ni1iOO0O_dataout; + ni1iOO1l <= wire_ni1iOOii_dataout; + ni1iOO1O <= wire_ni1iOOil_dataout; + ni1l00ii <= wire_ni1l0i1l_dataout; + ni1l00il <= wire_ni1l0i1O_dataout; + ni1l00iO <= wire_ni1l0i0i_dataout; + ni1l00li <= wire_ni1l0i0l_dataout; + ni1l00ll <= wire_ni1l0i0O_dataout; + ni1l00lO <= wire_ni1l0iii_dataout; + ni1l00Oi <= wire_ni1l0iil_dataout; + ni1l00Ol <= wire_ni1l0iiO_dataout; + ni1l00OO <= wire_ni1l0Oll_dataout; + ni1l0O0i <= wire_ni1l0OOl_dataout; + ni1l0O0l <= wire_ni1l0OOO_dataout; + ni1l0O0O <= wire_ni1li11i_dataout; + ni1l0O1l <= wire_ni1l0OlO_dataout; + ni1l0O1O <= wire_ni1l0OOi_dataout; + ni1l0Oii <= wire_ni1li11l_dataout; + ni1l0Oil <= wire_ni1li11O_dataout; + ni1l0OiO <= wire_ni1li10i_dataout; + ni1l0Oli <= wire_ni1lii0O_dataout; + ni1l100l <= wire_ni1l10OO_dataout; + ni1l100O <= wire_ni1l1i1i_dataout; + ni1l10ii <= wire_ni1l1i1l_dataout; + ni1l10il <= wire_ni1l1i1O_dataout; + ni1l10iO <= wire_ni1l1i0i_dataout; + ni1l10li <= wire_ni1l1i0l_dataout; + ni1l10ll <= wire_ni1l1i0O_dataout; + ni1l10lO <= wire_ni1l1iii_dataout; + ni1l10Oi <= wire_ni1l1O0O_dataout; + ni1l1lll <= wire_ni1l10Ol_dataout; + ni1l1llO <= wire_ni1l1Oii_dataout; + ni1l1lOi <= wire_ni1l1Oil_dataout; + ni1l1lOl <= wire_ni1l1OiO_dataout; + ni1l1lOO <= wire_ni1l1Oli_dataout; + ni1l1O0i <= wire_ni1l1OOl_dataout; + ni1l1O0l <= wire_ni1l0i1i_dataout; + ni1l1O1i <= wire_ni1l1Oll_dataout; + ni1l1O1l <= wire_ni1l1OlO_dataout; + ni1l1O1O <= wire_ni1l1OOi_dataout; + ni1li0lO <= wire_ni1liiii_dataout; + ni1li0Oi <= wire_ni1liiil_dataout; + ni1li0Ol <= wire_ni1liiiO_dataout; + ni1li0OO <= wire_ni1liili_dataout; + ni1lii0i <= wire_ni1liiOl_dataout; + ni1lii0l <= wire_ni1ll11i_dataout; + ni1lii1i <= wire_ni1liill_dataout; + ni1lii1l <= wire_ni1liilO_dataout; + ni1lii1O <= wire_ni1liiOi_dataout; + ni1liOii <= wire_ni1ll11l_dataout; + ni1liOil <= wire_ni1ll11O_dataout; + ni1liOiO <= wire_ni1ll10i_dataout; + ni1liOli <= wire_ni1ll10l_dataout; + ni1liOll <= wire_ni1ll10O_dataout; + ni1liOlO <= wire_ni1ll1ii_dataout; + ni1liOOi <= wire_ni1ll1il_dataout; + ni1liOOl <= wire_ni1ll1iO_dataout; + ni1liOOO <= wire_ni1llill_dataout; + ni1lli0i <= wire_ni1lliOl_dataout; + ni1lli0l <= wire_ni1lliOO_dataout; + ni1lli0O <= wire_ni1lll1i_dataout; + ni1lli1l <= wire_ni1llilO_dataout; + ni1lli1O <= wire_ni1lliOi_dataout; + ni1lliii <= wire_ni1lll1l_dataout; + ni1lliil <= wire_ni1lll1O_dataout; + ni1lliiO <= wire_ni1lll0i_dataout; + ni1llili <= wire_ni1lO10O_dataout; + ni1llOlO <= wire_ni1lO1ii_dataout; + ni1llOOi <= wire_ni1lO1il_dataout; + ni1llOOl <= wire_ni1lO1iO_dataout; + ni1llOOO <= wire_ni1lO1li_dataout; + ni1lO10i <= wire_ni1lO1Ol_dataout; + ni1lO10l <= wire_ni1lOill_dataout; + ni1lO11i <= wire_ni1lO1ll_dataout; + ni1lO11l <= wire_ni1lO1lO_dataout; + ni1lO11O <= wire_ni1lO1Oi_dataout; + ni1lOiii <= wire_ni1lOilO_dataout; + ni1lOiil <= wire_ni1lOiOi_dataout; + ni1lOiiO <= wire_ni1lOiOl_dataout; + ni1lOili <= wire_ni1lOiOO_dataout; + ni1lOOlO <= wire_ni1O11ii_dataout; + ni1lOOOi <= wire_ni1O11il_dataout; + ni1lOOOl <= wire_ni1O11iO_dataout; + ni1lOOOO <= wire_ni1O11li_dataout; + ni1O010i <= wire_ni1O01Ol_dataout; + ni1O010l <= wire_ni1O01OO_dataout; + ni1O010O <= wire_ni1O001i_dataout; + ni1O011i <= wire_ni1O01ll_dataout; + ni1O011l <= wire_ni1O01lO_dataout; + ni1O011O <= wire_ni1O01Oi_dataout; + ni1O01ii <= wire_ni1O0l1O_dataout; + ni1O0iiO <= wire_ni1O0l0i_dataout; + ni1O0ili <= wire_ni1O0l0l_dataout; + ni1O0ill <= wire_ni1O0l0O_dataout; + ni1O0ilO <= wire_ni1O0lii_dataout; + ni1O0iOi <= wire_ni1O0lil_dataout; + ni1O0iOl <= wire_ni1O0liO_dataout; + ni1O0iOO <= wire_ni1O0lli_dataout; + ni1O0l1i <= wire_ni1O0lll_dataout; + ni1O0l1l <= wire_ni1Oi1Oi_dataout; + ni1O110i <= wire_ni1O11Ol_dataout; + ni1O110l <= wire_ni1O1iOi_dataout; + ni1O111i <= wire_ni1O11ll_dataout; + ni1O111l <= wire_ni1O11lO_dataout; + ni1O111O <= wire_ni1O11Oi_dataout; + ni1O1i0i <= wire_ni1O1iOl_dataout; + ni1O1i0l <= wire_ni1O1iOO_dataout; + ni1O1i0O <= wire_ni1O1l1i_dataout; + ni1O1i1O <= wire_ni1O110O_dataout; + ni1O1iii <= wire_ni1O1l1l_dataout; + ni1O1iil <= wire_ni1O1l1O_dataout; + ni1O1iiO <= wire_ni1O1l0i_dataout; + ni1O1ili <= wire_ni1O1l0l_dataout; + ni1O1ill <= wire_ni1O1l0O_dataout; + ni1O1ilO <= wire_ni1O01il_dataout; + ni1O1OOl <= wire_ni1O01iO_dataout; + ni1O1OOO <= wire_ni1O01li_dataout; + ni1Oi10i <= wire_ni1Oi1Ol_dataout; + ni1Oi10l <= wire_ni1Oi1OO_dataout; + ni1Oi10O <= wire_ni1Oi01i_dataout; + ni1Oi1ii <= wire_ni1Oi01l_dataout; + ni1Oi1il <= wire_ni1Oi01O_dataout; + ni1Oi1iO <= wire_ni1Oi00i_dataout; + ni1Oi1li <= wire_ni1Oi00l_dataout; + ni1Oi1ll <= wire_ni1Oi00O_dataout; + ni1Oi1lO <= wire_ni1Oilil_dataout; + ni1OiiOl <= wire_ni1OiliO_dataout; + ni1OiiOO <= wire_ni1Oilli_dataout; + ni1Oil0i <= wire_ni1OilOl_dataout; + ni1Oil0l <= wire_ni1OilOO_dataout; + ni1Oil0O <= wire_ni1OiO1i_dataout; + ni1Oil1i <= wire_ni1Oilll_dataout; + ni1Oil1l <= wire_ni1OillO_dataout; + ni1Oil1O <= wire_ni1OilOi_dataout; + ni1Oilii <= wire_ni1Ol01O_dataout; + ni1Ol01i <= wire_ni1Ol0ll_dataout; + ni1Ol01l <= wire_ni1OllOi_dataout; + ni1Ol1iO <= wire_ni1Ol00i_dataout; + ni1Ol1li <= wire_ni1Ol00l_dataout; + ni1Ol1ll <= wire_ni1Ol00O_dataout; + ni1Ol1lO <= wire_ni1Ol0ii_dataout; + ni1Ol1Oi <= wire_ni1Ol0il_dataout; + ni1Ol1Ol <= wire_ni1Ol0iO_dataout; + ni1Ol1OO <= wire_ni1Ol0li_dataout; + ni1Oll0i <= wire_ni1OllOl_dataout; + ni1Oll0l <= wire_ni1OllOO_dataout; + ni1Oll0O <= wire_ni1OlO1i_dataout; + ni1Ollii <= wire_ni1OlO1l_dataout; + ni1Ollil <= wire_ni1OlO1O_dataout; + ni1OlliO <= wire_ni1OlO0i_dataout; + ni1Ollli <= wire_ni1OlO0l_dataout; + ni1Ollll <= wire_ni1OlO0O_dataout; + ni1OlllO <= wire_ni1OO01O_dataout; + ni1OO01i <= wire_ni1OO00O_dataout; + ni1OO01l <= wire_ni1OO0ii_dataout; + ni1OO1Ol <= wire_ni1OO00i_dataout; + ni1OO1OO <= wire_ni1OO00l_dataout; + ni1OOl0i <= wire_ni1OOlOl_dataout; + ni1OOl0l <= wire_ni1OOlOO_dataout; + ni1OOl0O <= wire_ni1OOO1i_dataout; + ni1OOlii <= wire_ni1OOO1l_dataout; + ni1OOlil <= wire_ni1OOO1O_dataout; + ni1OOliO <= wire_ni1OOO0i_dataout; + ni1OOlli <= wire_ni1OOO0l_dataout; + ni1OOlll <= wire_ni1OOO0O_dataout; + ni1OOllO <= wire_ni01100l_dataout; + nii0li1l <= wire_nii0llOi_dataout; + nii0lllO <= wire_nii0O1il_dataout; + nii0O1ii <= wire_nii0Oi1O_dataout; + nii0Oi1l <= wire_nii0OlOi_dataout; + nii0OllO <= wire_niii11il_dataout; + niii00OO <= wire_niii0i0i_dataout; + niii0i1i <= wire_niii0i0l_dataout; + niii0i1l <= wire_niiil11O_dataout; + niii0OOl <= wire_niiil10i_dataout; + niii0OOO <= wire_niiil10l_dataout; + niii11ii <= wire_niii1i1O_dataout; + niii1i1l <= wire_niii1lOi_dataout; + niii1llO <= wire_niii00ll_dataout; + niii1O0l <= wire_niii00ii_dataout; + niii1O0O <= wire_niii001O_dataout; + niii1Oii <= wire_niii01Ol_dataout; + niii1Oil <= wire_niii01li_dataout; + niii1OiO <= wire_niii010O_dataout; + niii1Oli <= wire_niii011l_dataout; + niii1Oll <= wire_niii1OOi_dataout; + niii1OlO <= wire_niii0i1O_dataout; + niiii00i <= wire_niiil0iO_dataout; + niiii00l <= wire_niiil0li_dataout; + niiii00O <= wire_niiil0ll_dataout; + niiii01i <= wire_niiil00O_dataout; + niiii01l <= wire_niiil0ii_dataout; + niiii01O <= wire_niiil0il_dataout; + niiii0ii <= wire_niiil0lO_dataout; + niiii0il <= wire_niiil0Oi_dataout; + niiii0iO <= wire_niiil0Ol_dataout; + niiii0li <= wire_niiil0OO_dataout; + niiii0ll <= wire_niiili1i_dataout; + niiii0lO <= wire_niiili1l_dataout; + niiii0Oi <= wire_niiili1O_dataout; + niiii0Ol <= wire_niiili0i_dataout; + niiii0OO <= wire_niiili0l_dataout; + niiii10i <= wire_niiil1iO_dataout; + niiii10l <= wire_niiil1li_dataout; + niiii10O <= wire_niiil1ll_dataout; + niiii11i <= wire_niiil10O_dataout; + niiii11l <= wire_niiil1ii_dataout; + niiii11O <= wire_niiil1il_dataout; + niiii1ii <= wire_niiil1lO_dataout; + niiii1il <= wire_niiil1Oi_dataout; + niiii1iO <= wire_niiil1Ol_dataout; + niiii1li <= wire_niiil1OO_dataout; + niiii1ll <= wire_niiil01i_dataout; + niiii1lO <= wire_niiil01l_dataout; + niiii1Oi <= wire_niiil01O_dataout; + niiii1Ol <= wire_niiil00i_dataout; + niiii1OO <= wire_niiil00l_dataout; + niiiii0i <= wire_niiiliiO_dataout; + niiiii0l <= wire_niiilili_dataout; + niiiii0O <= wire_niiilill_dataout; + niiiii1i <= wire_niiili0O_dataout; + niiiii1l <= wire_niiiliii_dataout; + niiiii1O <= wire_niiiliil_dataout; + niiiiiii <= wire_niiililO_dataout; + niiiiiil <= wire_niiiliOi_dataout; + niiiiiiO <= wire_niiiliOl_dataout; + niiiiili <= wire_niiiliOO_dataout; + niiiiill <= wire_niiill1i_dataout; + niiiiilO <= wire_niiill1l_dataout; + niiiiiOi <= wire_niiill1O_dataout; + niiiiiOl <= wire_niiill0i_dataout; + niiiiiOO <= wire_niiill0l_dataout; + niiiil0i <= wire_niiilliO_dataout; + niiiil0l <= wire_niiillli_dataout; + niiiil0O <= wire_niiillll_dataout; + niiiil1i <= wire_niiill0O_dataout; + niiiil1l <= wire_niiillii_dataout; + niiiil1O <= wire_niiillil_dataout; + niiiilii <= wire_niiilllO_dataout; + niiiilil <= wire_niiillOi_dataout; + niiiiliO <= wire_niiillOl_dataout; + niiiilli <= wire_niiillOO_dataout; + niiiilll <= wire_niiilO1i_dataout; + niiiillO <= wire_niiilO1l_dataout; + niiiilOi <= wire_niiilO1O_dataout; + niiiilOl <= wire_niiilO0i_dataout; + niiiilOO <= wire_niiilO0l_dataout; + niiiiO0i <= wire_niiilOiO_dataout; + niiiiO0l <= wire_niiilOli_dataout; + niiiiO0O <= wire_niiilOll_dataout; + niiiiO1i <= wire_niiilO0O_dataout; + niiiiO1l <= wire_niiilOii_dataout; + niiiiO1O <= wire_niiilOil_dataout; + niiiiOii <= wire_niiilOlO_dataout; + niiiiOil <= wire_niiilOOi_dataout; + niiiiOiO <= wire_niiilOOl_dataout; + niiiiOli <= wire_niiilOOO_dataout; + niiiiOll <= wire_niiiO11i_dataout; + niiiiOlO <= wire_niiiO11l_dataout; + niiiiOOi <= wire_niiiO11O_dataout; + niiiiOOl <= wire_niiiO10i_dataout; + niiiiOOO <= wire_niiiO10l_dataout; + niiil11i <= wire_niiiO10O_dataout; + niiil11l <= wire_niiiO1ii_dataout; + niil00Ol <= wire_niil01iO_dataout; + niil010i <= wire_niil01li_dataout; + niil010l <= wire_niil01ll_dataout; + niil010O <= wire_niil01lO_dataout; + niO010ii <= niO0100i; + niO010ll <= wire_niO010Oi_dataout; + niO011ii <= niO0110i; + niO011ll <= wire_niO011Oi_dataout; + niO01iii <= niO01i0i; + niO01ilO <= wire_niO01iOO_dataout; + niO10OlO <= wire_niO1li0O_dataout; + niO10OOi <= wire_niO1liii_dataout; + niO10OOl <= wire_niO1liil_dataout; + niO10OOO <= wire_niO1liiO_dataout; + niO1i00i <= wire_niO1llOi_dataout; + niO1i00l <= wire_niO1llOl_dataout; + niO1i00O <= wire_niO1llOO_dataout; + niO1i01i <= wire_niO1llli_dataout; + niO1i01l <= wire_niO1llll_dataout; + niO1i01O <= wire_niO1lllO_dataout; + niO1i0ii <= wire_niO1lO1i_dataout; + niO1i0il <= wire_niO1lO1l_dataout; + niO1i0iO <= wire_niO1lO1O_dataout; + niO1i0li <= wire_niO1lO0i_dataout; + niO1i0ll <= wire_niO1lO0l_dataout; + niO1i0lO <= wire_niO1lO0O_dataout; + niO1i0Oi <= wire_niO1lOii_dataout; + niO1i0Ol <= wire_niO1lOil_dataout; + niO1i0OO <= wire_niO1lOiO_dataout; + niO1i10i <= wire_niO1liOi_dataout; + niO1i10l <= wire_niO1liOl_dataout; + niO1i10O <= wire_niO1liOO_dataout; + niO1i11i <= wire_niO1lili_dataout; + niO1i11l <= wire_niO1lill_dataout; + niO1i11O <= wire_niO1lilO_dataout; + niO1i1ii <= wire_niO1ll1i_dataout; + niO1i1il <= wire_niO1ll1l_dataout; + niO1i1iO <= wire_niO1ll1O_dataout; + niO1i1li <= wire_niO1ll0i_dataout; + niO1i1ll <= wire_niO1ll0l_dataout; + niO1i1lO <= wire_niO1ll0O_dataout; + niO1i1Oi <= wire_niO1llii_dataout; + niO1i1Ol <= wire_niO1llil_dataout; + niO1i1OO <= wire_niO1lliO_dataout; + niO1ii0i <= wire_niO1lOOi_dataout; + niO1ii0l <= wire_niO1lOOl_dataout; + niO1ii0O <= wire_niO1lOOO_dataout; + niO1ii1i <= wire_niO1lOli_dataout; + niO1ii1l <= wire_niO1lOll_dataout; + niO1ii1O <= wire_niO1lOlO_dataout; + niO1iiii <= wire_niO1O11i_dataout; + niO1iiil <= wire_niO1O11l_dataout; + niO1iiiO <= wire_niO1O11O_dataout; + niO1iili <= wire_niO1O10i_dataout; + niO1iill <= wire_niO1O10l_dataout; + niO1iilO <= wire_niO1O10O_dataout; + niO1iiOi <= wire_niO1O1ii_dataout; + niO1iiOl <= wire_niO1O1il_dataout; + niO1iiOO <= wire_niO1O1iO_dataout; + niO1il0i <= wire_niO1O1Oi_dataout; + niO1il0l <= wire_niO1O1Ol_dataout; + niO1il0O <= wire_niO1O1OO_dataout; + niO1il1i <= wire_niO1O1li_dataout; + niO1il1l <= wire_niO1O1ll_dataout; + niO1il1O <= wire_niO1O1lO_dataout; + niO1ilii <= wire_niO1O01i_dataout; + niO1ilil <= wire_niO1O01l_dataout; + niO1iliO <= wire_niO1O01O_dataout; + niO1illi <= wire_niO1O00i_dataout; + niO1illl <= wire_niO1O00l_dataout; + niO1illO <= wire_niO1O00O_dataout; + niO1ilOi <= wire_niO1O0ii_dataout; + niO1ilOl <= wire_niO1O0il_dataout; + niO1ilOO <= wire_niO1O0iO_dataout; + niO1iO0i <= wire_niO1O0Oi_dataout; + niO1iO0l <= wire_niO1O0Ol_dataout; + niO1iO0O <= wire_niO1O0OO_dataout; + niO1iO1i <= wire_niO1O0li_dataout; + niO1iO1l <= wire_niO1O0ll_dataout; + niO1iO1O <= wire_niO1O0lO_dataout; + niO1iOii <= wire_niO1Oi1i_dataout; + niO1iOil <= wire_niO1Oi1l_dataout; + niO1iOiO <= wire_niO1Oi1O_dataout; + niO1iOli <= wire_niO1Oi0i_dataout; + niO1iOll <= wire_niO1Oi0l_dataout; + niO1iOlO <= wire_niO1Oi0O_dataout; + niO1iOOi <= wire_niO1Oiii_dataout; + niO1iOOl <= wire_niO1Oiil_dataout; + niO1iOOO <= wire_niO1OiiO_dataout; + niO1l00i <= wire_niO1OlOi_dataout; + niO1l00l <= wire_niO1OlOl_dataout; + niO1l00O <= wire_niO1OlOO_dataout; + niO1l01i <= wire_niO1Olli_dataout; + niO1l01l <= wire_niO1Olll_dataout; + niO1l01O <= wire_niO1OllO_dataout; + niO1l0ii <= wire_niO1OO1i_dataout; + niO1l0il <= wire_niO1OO1l_dataout; + niO1l0iO <= wire_niO1OO1O_dataout; + niO1l0li <= wire_niO1OO0i_dataout; + niO1l0ll <= wire_niO1OO0l_dataout; + niO1l0lO <= wire_niO1OO0O_dataout; + niO1l0Oi <= wire_niO1OOii_dataout; + niO1l0Ol <= wire_niO1OOil_dataout; + niO1l0OO <= wire_niO1OOiO_dataout; + niO1l10i <= wire_niO1OiOi_dataout; + niO1l10l <= wire_niO1OiOl_dataout; + niO1l10O <= wire_niO1OiOO_dataout; + niO1l11i <= wire_niO1Oili_dataout; + niO1l11l <= wire_niO1Oill_dataout; + niO1l11O <= wire_niO1OilO_dataout; + niO1l1ii <= wire_niO1Ol1i_dataout; + niO1l1il <= wire_niO1Ol1l_dataout; + niO1l1iO <= wire_niO1Ol1O_dataout; + niO1l1li <= wire_niO1Ol0i_dataout; + niO1l1ll <= wire_niO1Ol0l_dataout; + niO1l1lO <= wire_niO1Ol0O_dataout; + niO1l1Oi <= wire_niO1Olii_dataout; + niO1l1Ol <= wire_niO1Olil_dataout; + niO1l1OO <= wire_niO1OliO_dataout; + niO1li1i <= wire_niO1OOli_dataout; + niO1li1l <= wire_niO1OOll_dataout; + niO1OOlO <= wire_niO1li0l_dataout; + niOO0O0OO <= wire_niOO0Oiil_dataout; + niOO0Oi0i <= wire_niOO0OilO_dataout; + niOO0Oi0l <= wire_niOO0OiOi_dataout; + niOO0Oi1i <= wire_niOO0OiiO_dataout; + niOO0Oi1l <= wire_niOO0Oili_dataout; + niOO0Oi1O <= wire_niOO0Oill_dataout; + niOO0Olii <= wire_niOO0Oiii_dataout; + niOO0OllO <= wire_niOO0OO1i_dataout; + niOO0OlOl <= wire_niOO0OO1l_dataout; + nlOi000li <= wire_nlOi000Oi_dataout; + nlOi0011i <= wire_nlOi0010i_dataout; + nlOi001il <= wire_nlOi001lO_dataout; + nlOi001ll <= wire_nlOi001Oi_dataout; + nlOi00i0l <= wire_nlOi00iii_dataout; + nlOi00i1l <= wire_nlOi00i0O_dataout; + nlOi00iOO <= nlOi00l1l; + nlOi00l0i <= nlOi00l0O; + nlOi00liO <= n11O1O0l; + nlOi00lOi <= n11O1O0O; + nlOi00OOi <= wire_nlOi0i11i_dataout; + nlOi0i00l <= n11i110i; + nlOi0i10l <= wire_nlOi0i1li_dataout; + nlOi0i1il <= wire_nlOi0i1ll_dataout; + nlOi0i1iO <= wire_nlOi0i1lO_dataout; + nlOi0il0i <= wire_nlOi0iO1l_dataout; + nlOi0il0l <= wire_nlOi0iO1O_dataout; + nlOi0il0O <= wire_nlOi0iO0i_dataout; + nlOi0il1O <= wire_nlOi0iO1i_dataout; + nlOi0ilii <= wire_nlOi0iO0l_dataout; + nlOi0ilil <= wire_nlOi0iO0O_dataout; + nlOi0iliO <= wire_nlOi0iOii_dataout; + nlOi0illi <= wire_nlOi0iOil_dataout; + nlOi0illl <= wire_nlOi0iOiO_dataout; + nlOi0illO <= wire_nlOi0iOli_dataout; + nlOi0ilOi <= wire_nlOi0iOll_dataout; + nlOi0l01l <= wire_nlOi0l00l_dataout; + nlOi0l1li <= wire_nlOi0ilOO_dataout; + nlOi0l1OO <= wire_nlOi0l00i_dataout; + nlOi0lO0O <= n1110O0l; + nlOi0lOOi <= wire_nlOi0lOli_dataout; + nlOi0O0il <= wire_nlOi0O0ll_dataout; + nlOi0O0OO <= wire_nlOi0Oi0i_dataout; + nlOi0O10l <= wire_nlOi0O1il_dataout; + nlOi0O11O <= wire_nlOi0O1ii_dataout; + nlOi0Oi1O <= wire_nlOi0Oi0l_dataout; + nlOi0Ol1l <= wire_nlOi0Ol0l_dataout; + nlOi0OliO <= wire_nlOi0OlOi_dataout; + nlOi0OllO <= wire_nlOi0OlOl_dataout; + nlOi0OOli <= wire_nlOi0OOii_dataout; + nlOi0OOOO <= wire_nlOii110i_dataout; + nlOii001O <= wire_nlOii000l_dataout; + nlOii01il <= wire_nlOii01ll_dataout; + nlOii01OO <= wire_nlOii000i_dataout; + nlOii0i1l <= wire_nlOii0i0l_dataout; + nlOii0iiO <= wire_nlOii0iOi_dataout; + nlOii0ilO <= wire_nlOii0iOl_dataout; + nlOii0lii <= nlOii0liO; + nlOii0lll <= nlOii0lOi; + nlOii0lOO <= nlOii0O1l; + nlOii0O0i <= nlOii0O0O; + nlOii0Oil <= nlOii0Oli; + nlOii0OOi <= n1110OlO; + nlOii100i <= nlOii100O; + nlOii10il <= nlOii10li; + nlOii10lO <= nlOii10Ol; + nlOii111l <= wire_nlOii110l_dataout; + nlOii11OO <= nlOii101l; + nlOii1i0l <= wire_nlOii1iil_dataout; + nlOii1ilO <= wire_nlOii1l1i_dataout; + nlOii1iOO <= wire_nlOii1l1l_dataout; + nlOii1lOl <= wire_nlOii1O1l_dataout; + nlOii1O0O <= wire_nlOii1Oli_dataout; + nlOii1OiO <= wire_nlOii1Oll_dataout; + nlOiii01l <= wire_nlOiii00l_dataout; + nlOiii0iO <= wire_nlOiii0Oi_dataout; + nlOiii0lO <= wire_nlOiii0Ol_dataout; + nlOiii10O <= n1110OOl; + nlOiii11l <= n1110Oll; + nlOiii1li <= n1110OOi; + nlOiiiiOl <= wire_nlOiiil1l_dataout; + nlOiil01i <= wire_nlOiil00i_dataout; + nlOiil0il <= wire_nlOiili0i_dataout; + nlOiil0ll <= wire_nlOiili0l_dataout; + nlOiil0lO <= wire_nlOiili0O_dataout; + nlOiil0Oi <= wire_nlOiiliii_dataout; + nlOiil0Ol <= wire_nlOiiliil_dataout; + nlOiil0OO <= wire_nlOiiliiO_dataout; + nlOiili1i <= wire_nlOiilili_dataout; + nlOiili1l <= wire_nlOiilill_dataout; + nlOiili1O <= wire_nlOiililO_dataout; + nlOiiO11l <= wire_nlOiiO10l_dataout; + nlOiiO1iO <= wire_nlOiiO01i_dataout; + nlOiiO1lO <= wire_nlOiiO01l_dataout; + nlOiiO1Oi <= wire_nlOiiO01O_dataout; + nlOiiO1Ol <= wire_nlOiiO00i_dataout; + nlOiiO1OO <= wire_nlOiiO00l_dataout; + nlOiiOlll <= wire_nlOiiOlOl_dataout; + nlOiiOO0O <= wire_nlOiiOOlO_dataout; + nlOiiOO1O <= wire_nlOiiOOll_dataout; + nlOiiOOii <= wire_nlOiiOOOi_dataout; + nlOiiOOil <= wire_nlOiiOOOl_dataout; + nlOiiOOiO <= wire_nlOiiOOOO_dataout; + nlOiiOOli <= wire_nlOil111i_dataout; + nlOil10iO <= wire_nlOil1iii_dataout; + nlOil10li <= wire_nlOil1iil_dataout; + nlOil10ll <= wire_nlOil1iiO_dataout; + nlOil10lO <= wire_nlOil1ili_dataout; + nlOil10Oi <= wire_nlOil1ill_dataout; + nlOil10Ol <= wire_nlOil1ilO_dataout; + nlOil10OO <= wire_nlOil1iOi_dataout; + nlOil1i1i <= wire_nlOil1iOl_dataout; + nlOili01i <= wire_nlOili01O_dataout; + nlOili10O <= wire_nlOili1iO_dataout; + nlOili1Oi <= wire_nlOili01l_dataout; + nlOill00l <= wire_nlOilliOO_dataout; + nlOill00O <= wire_nlOilll1i_dataout; + nlOill01l <= wire_nlOillilO_dataout; + nlOill01O <= wire_nlOilliOi_dataout; + nlOill0ii <= wire_nlOilll1l_dataout; + nlOill0il <= wire_nlOilll1O_dataout; + nlOill0iO <= wire_nlOilll0i_dataout; + nlOill0li <= wire_nlOilll0l_dataout; + nlOill0ll <= wire_nlOilll0O_dataout; + nlOill0lO <= wire_nlOilllii_dataout; + nlOill0Oi <= wire_nlOilllil_dataout; + nlOill0Ol <= wire_nlOillliO_dataout; + nlOill0OO <= wire_nlOilllli_dataout; + nlOill11l <= wire_nlOilli1i_dataout; + nlOill1ii <= wire_nlOilli1l_dataout; + nlOill1il <= wire_nlOilli1O_dataout; + nlOill1iO <= wire_nlOilli0i_dataout; + nlOill1li <= wire_nlOilli0l_dataout; + nlOill1ll <= wire_nlOilli0O_dataout; + nlOill1lO <= wire_nlOilliii_dataout; + nlOill1Oi <= wire_nlOilliil_dataout; + nlOill1Ol <= wire_nlOilliiO_dataout; + nlOilO00l <= wire_nlOilO0il_dataout; + nlOilO0lO <= wire_nlOilOi1i_dataout; + nlOilO0OO <= wire_nlOilOi1l_dataout; + nlOilOiOl <= wire_nlOilOl1l_dataout; + nlOilOl0O <= wire_nlOilOlli_dataout; + nlOilOliO <= wire_nlOilOlll_dataout; + nlOilOOil <= wire_nlOilOOll_dataout; + nlOilOOOO <= wire_nlOiO110i_dataout; + nlOiO011i <= wire_nlOiOi10i_dataout; + nlOiO100i <= wire_nlOiO1i0l_dataout; + nlOiO100l <= wire_nlOiO1i0O_dataout; + nlOiO100O <= wire_nlOiO1iii_dataout; + nlOiO101i <= wire_nlOiO1i1l_dataout; + nlOiO101l <= wire_nlOiO1i1O_dataout; + nlOiO101O <= wire_nlOiO1i0i_dataout; + nlOiO10ii <= wire_nlOiO1iil_dataout; + nlOiO10il <= wire_nlOiO1iiO_dataout; + nlOiO10iO <= wire_nlOiO1ili_dataout; + nlOiO10li <= wire_nlOiO1ill_dataout; + nlOiO10ll <= wire_nlOiO1ilO_dataout; + nlOiO10lO <= wire_nlOiO1iOi_dataout; + nlOiO10Oi <= wire_nlOiO1iOl_dataout; + nlOiO111O <= wire_nlOiO110l_dataout; + nlOiO11OO <= wire_nlOiO1i1i_dataout; + nlOiO1lOO <= wire_nlOiO10OO_dataout; + nlOiOi11l <= wire_nlOiOi10l_dataout; + nlOiOi11O <= wire_nlOiOO1Oi_dataout; + nlOiOl00i <= wire_nlOiOO00l_dataout; + nlOiOl00l <= wire_nlOiOO00O_dataout; + nlOiOl00O <= wire_nlOiOO0ii_dataout; + nlOiOl01i <= wire_nlOiOO01l_dataout; + nlOiOl01l <= wire_nlOiOO01O_dataout; + nlOiOl01O <= wire_nlOiOO00i_dataout; + nlOiOl0ii <= wire_nlOiOO0il_dataout; + nlOiOl0il <= wire_nlOiOO0iO_dataout; + nlOiOl0iO <= wire_nlOiOO0li_dataout; + nlOiOl0li <= wire_nlOiOO0ll_dataout; + nlOiOl0ll <= wire_nlOiOO0lO_dataout; + nlOiOl0lO <= wire_nlOiOO0Oi_dataout; + nlOiOl0Oi <= wire_nlOiOO0Ol_dataout; + nlOiOl0Ol <= wire_nlOiOO0OO_dataout; + nlOiOl0OO <= wire_nlOiOOi1i_dataout; + nlOiOl1Oi <= wire_nlOiOO1Ol_dataout; + nlOiOl1Ol <= wire_nlOiOO1OO_dataout; + nlOiOl1OO <= wire_nlOiOO01i_dataout; + nlOiOli0i <= wire_nlOiOOi0l_dataout; + nlOiOli0l <= wire_nlOiOOi0O_dataout; + nlOiOli0O <= wire_nlOiOOiii_dataout; + nlOiOli1i <= wire_nlOiOOi1l_dataout; + nlOiOli1l <= wire_nlOiOOi1O_dataout; + nlOiOli1O <= wire_nlOiOOi0i_dataout; + nlOiOliii <= wire_nlOiOOiil_dataout; + nlOiOliil <= wire_nlOiOOiiO_dataout; + nlOiOliiO <= wire_nlOiOOili_dataout; + nlOiOlili <= wire_nlOiOOill_dataout; + nlOiOlill <= wire_nlOiOOilO_dataout; + nlOiOlilO <= wire_nlOiOOiOi_dataout; + nlOiOliOi <= wire_nlOiOOiOl_dataout; + nlOiOliOl <= wire_nlOiOOiOO_dataout; + nlOiOliOO <= wire_nlOiOOl1i_dataout; + nlOiOll0i <= wire_nlOiOOl0l_dataout; + nlOiOll0l <= wire_nlOiOOl0O_dataout; + nlOiOll0O <= wire_nlOiOOlii_dataout; + nlOiOll1i <= wire_nlOiOOl1l_dataout; + nlOiOll1l <= wire_nlOiOOl1O_dataout; + nlOiOll1O <= wire_nlOiOOl0i_dataout; + nlOiOllii <= wire_nlOiOOlil_dataout; + nlOiOllil <= wire_nlOiOOliO_dataout; + nlOiOlliO <= wire_nlOiOOlli_dataout; + nlOiOllli <= wire_nlOiOOlll_dataout; + nlOiOllll <= wire_nlOiOOllO_dataout; + nlOiOlllO <= wire_nlOiOOlOi_dataout; + nlOiOllOi <= wire_nlOiOOlOl_dataout; + nlOiOllOl <= wire_nlOiOOlOO_dataout; + nlOiOllOO <= wire_nlOiOOO1i_dataout; + nlOiOlO0i <= wire_nlOiOOO0l_dataout; + nlOiOlO0l <= wire_nlOiOOO0O_dataout; + nlOiOlO0O <= wire_nlOiOOOii_dataout; + nlOiOlO1i <= wire_nlOiOOO1l_dataout; + nlOiOlO1l <= wire_nlOiOOO1O_dataout; + nlOiOlO1O <= wire_nlOiOOO0i_dataout; + nlOiOlOii <= wire_nlOiOOOil_dataout; + nlOiOlOil <= wire_nlOiOOOiO_dataout; + nlOiOlOiO <= wire_nlOiOOOli_dataout; + nlOiOlOli <= wire_nlOiOOOll_dataout; + nlOiOlOll <= wire_nlOiOOOlO_dataout; + nlOiOlOlO <= wire_nlOiOOOOi_dataout; + nlOiOlOOi <= wire_nlOiOOOOl_dataout; + nlOiOlOOl <= wire_nlOiOOOOO_dataout; + nlOiOlOOO <= wire_nlOl1111i_dataout; + nlOiOO10i <= wire_nlOl1110l_dataout; + nlOiOO10l <= wire_nlOl1110O_dataout; + nlOiOO10O <= wire_nlOl111ii_dataout; + nlOiOO11i <= wire_nlOl1111l_dataout; + nlOiOO11l <= wire_nlOl1111O_dataout; + nlOiOO11O <= wire_nlOl1110i_dataout; + nlOiOO1ii <= wire_nlOl111il_dataout; + nlOiOO1il <= wire_nlOl111iO_dataout; + nlOiOO1iO <= wire_nlOl111li_dataout; + nlOiOO1li <= wire_nlOl111ll_dataout; + nlOiOO1ll <= wire_nlOl111lO_dataout; + nlOliiO0i <= wire_nlOlil1il_dataout; + nlOliiO0l <= wire_nlOlil1iO_dataout; + nlOliiO0O <= wire_nlOlil1li_dataout; + nlOliiOii <= wire_nlOlil1ll_dataout; + nlOliiOil <= wire_nlOlil1lO_dataout; + nlOliiOiO <= wire_nlOlil1Oi_dataout; + nlOliiOli <= wire_nlOlil1Ol_dataout; + nlOliiOll <= wire_nlOlil1OO_dataout; + nlOliiOlO <= wire_nlOlil01i_dataout; + nlOliiOOi <= wire_nlOlil01l_dataout; + nlOliiOOl <= wire_nlOlil01O_dataout; + nlOliiOOO <= wire_nlOlil00i_dataout; + nlOlil10i <= wire_nlOlil0il_dataout; + nlOlil10l <= wire_nlOlil0iO_dataout; + nlOlil11i <= wire_nlOlil00l_dataout; + nlOlil11l <= wire_nlOlil00O_dataout; + nlOlil11O <= wire_nlOlil0ii_dataout; + nlOliO00i <= wire_nlOliOl1i_dataout; + nlOliO00l <= wire_nlOliOl1l_dataout; + nlOliO01i <= wire_nlOliOiOi_dataout; + nlOliO01l <= wire_nlOliOiOl_dataout; + nlOliO0ii <= wire_nlOliOl0i_dataout; + nlOliO0il <= wire_nlOliOl0l_dataout; + nlOliO0li <= wire_nlOliOlii_dataout; + nlOliO0ll <= wire_nlOll00ii_dataout; + nlOliO10i <= wire_nlOliOi1i_dataout; + nlOliO10l <= wire_nlOliOi1l_dataout; + nlOliO11i <= wire_nlOliO0Oi_dataout; + nlOliO11l <= wire_nlOliO0Ol_dataout; + nlOliO1ii <= wire_nlOliOi0i_dataout; + nlOliO1il <= wire_nlOliOi0l_dataout; + nlOliO1li <= wire_nlOliOiii_dataout; + nlOliO1ll <= wire_nlOliOiil_dataout; + nlOliO1Oi <= wire_nlOliOili_dataout; + nlOliO1Ol <= wire_nlOliOill_dataout; + nlOll000i <= wire_nlOll0i1O_dataout; + nlOll000l <= wire_nlOll0i0i_dataout; + nlOll000O <= wire_nlOll0Oil_dataout; + nlOll001i <= wire_nlOll00OO_dataout; + nlOll001l <= wire_nlOll0i1i_dataout; + nlOll001O <= wire_nlOll0i1l_dataout; + nlOll01iO <= wire_nlOll00il_dataout; + nlOll01li <= wire_nlOll00iO_dataout; + nlOll01ll <= wire_nlOll00li_dataout; + nlOll01lO <= wire_nlOll00ll_dataout; + nlOll01Oi <= wire_nlOll00lO_dataout; + nlOll01Ol <= wire_nlOll00Oi_dataout; + nlOll01OO <= wire_nlOll00Ol_dataout; + nlOll0O0i <= wire_nlOll0OiO_dataout; + nlOll0O0l <= wire_nlOll0Oli_dataout; + nlOll0O0O <= wire_nlOll0Oll_dataout; + nlOllil0l <= wire_nlOlll11i_dataout; + nlOllil0O <= wire_nlOlll11l_dataout; + nlOllilii <= wire_nlOlll11O_dataout; + nlOllilil <= wire_nlOlll10i_dataout; + nlOlliliO <= wire_nlOlll10l_dataout; + nlOllilli <= wire_nlOlll10O_dataout; + nlOllilll <= wire_nlOlll1ii_dataout; + nlOllillO <= wire_nlOlll1il_dataout; + nlOllilOi <= wire_nlOlll1iO_dataout; + nlOllilOl <= wire_nlOlll1li_dataout; + nlOllilOO <= wire_nlOlll1li_dataout; + nlOlliO0i <= wire_nlOlll1Ol_dataout; + nlOlliO0l <= wire_nlOlll1OO_dataout; + nlOlliO0O <= wire_nlOlll01i_dataout; + nlOlliO1i <= wire_nlOlll1ll_dataout; + nlOlliO1l <= wire_nlOlll1lO_dataout; + nlOlliO1O <= wire_nlOlll1Oi_dataout; + nlOlliOii <= wire_nlOlll01l_dataout; + nlOlliOil <= wire_nlOlll01O_dataout; + nlOlliOiO <= wire_nlOlll00i_dataout; + nlOlliOli <= wire_nlOlll00l_dataout; + nlOlliOll <= wire_nlOlll00O_dataout; + nlOlliOlO <= wire_nlOlll0ii_dataout; + nlOlliOOi <= wire_nlOlll0il_dataout; + nlOlliOOl <= wire_nlOlll0iO_dataout; + nlOlliOOO <= wire_nlOlllliO_dataout; + nlOllll0l <= wire_nlOllllli_dataout; + nlOllll0O <= wire_nlOllllll_dataout; + nlOllllil <= wire_nlOllO0li_dataout; + nlOllO0iO <= wire_nlOllOO1l_dataout; + nlOllOliO <= wire_nlOllOO1O_dataout; + nlOllOlli <= wire_nlOllOO0i_dataout; + nlOllOlll <= wire_nlOllOO0l_dataout; + nlOllOllO <= wire_nlOllOO0O_dataout; + nlOllOlOi <= wire_nlOllOOii_dataout; + nlOllOlOl <= wire_nlOllOOil_dataout; + nlOllOlOO <= wire_nlOllOOiO_dataout; + nlOllOO1i <= wire_nlOlO10li_dataout; + nlOlO010i <= wire_nlOlO01ll_dataout; + nlOlO010l <= wire_nlOlO0O1i_dataout; + nlOlO011i <= wire_nlOlO01il_dataout; + nlOlO011l <= wire_nlOlO01iO_dataout; + nlOlO011O <= wire_nlOlO01li_dataout; + nlOlO0lOO <= wire_nlOlOi00O_dataout; + nlOlO10ii <= wire_nlOlO10ll_dataout; + nlOlO10il <= wire_nlOlO10lO_dataout; + nlOlO10iO <= wire_nlOlO1l0l_dataout; + nlOlO1ilO <= wire_nlOlO1l0O_dataout; + nlOlO1iOi <= wire_nlOlO1lii_dataout; + nlOlO1iOl <= wire_nlOlO1lil_dataout; + nlOlO1iOO <= wire_nlOlO1liO_dataout; + nlOlO1l0i <= wire_nlOlO010O_dataout; + nlOlO1l1i <= wire_nlOlO1lli_dataout; + nlOlO1l1l <= wire_nlOlO1lll_dataout; + nlOlO1l1O <= wire_nlOlO1llO_dataout; + nlOlO1OOO <= wire_nlOlO01ii_dataout; + nlOlOi00i <= wire_nlOlOi0Oi_dataout; + nlOlOi00l <= wire_nlOlOiO0i_dataout; + nlOlOi01i <= wire_nlOlOi0li_dataout; + nlOlOi01l <= wire_nlOlOi0ll_dataout; + nlOlOi01O <= wire_nlOlOi0lO_dataout; + nlOlOi1Oi <= wire_nlOlOi0ii_dataout; + nlOlOi1Ol <= wire_nlOlOi0il_dataout; + nlOlOi1OO <= wire_nlOlOi0iO_dataout; + nlOlOil0i <= wire_nlOlOiOil_dataout; + nlOlOil0l <= wire_nlOlOiOiO_dataout; + nlOlOil0O <= wire_nlOlOiOli_dataout; + nlOlOil1i <= wire_nlOlOiO0l_dataout; + nlOlOil1l <= wire_nlOlOiO0O_dataout; + nlOlOil1O <= wire_nlOlOiOii_dataout; + nlOlOilii <= wire_nlOlOiOll_dataout; + nlOlOilil <= wire_nlOlOiOlO_dataout; + nlOlOiliO <= wire_nlOlOiOOi_dataout; + nlOlOilli <= wire_nlOlOiOOl_dataout; + nlOlOillO <= wire_nlOlOl11i_dataout; + nlOlOilOi <= wire_nlOlOl11l_dataout; + nlOlOilOl <= wire_nlOlOl11O_dataout; + nlOlOiO1i <= wire_nlOlOl10l_dataout; + nlOlOiO1l <= wire_nlOlOl10O_dataout; + nlOlOiO1O <= wire_nlOO10Oll_dataout; + nlOO0000i <= wire_nlOO0llOl_dataout; + nlOO0000l <= wire_nlOO0llOO_dataout; + nlOO0000O <= wire_nlOO0lO1i_dataout; + nlOO0001i <= wire_nlOO0llll_dataout; + nlOO0001l <= wire_nlOO0lllO_dataout; + nlOO0001O <= wire_nlOO0llOi_dataout; + nlOO000ii <= wire_nlOO0lO1l_dataout; + nlOO000il <= wire_nlOO0lO1O_dataout; + nlOO000iO <= wire_nlOO0lO0i_dataout; + nlOO000li <= wire_nlOO0lO0l_dataout; + nlOO000ll <= wire_nlOO0lO0O_dataout; + nlOO000lO <= wire_nlOO0lOii_dataout; + nlOO000Oi <= wire_nlOO0lOil_dataout; + nlOO000Ol <= wire_nlOO0lOiO_dataout; + nlOO000OO <= wire_nlOO0lOli_dataout; + nlOO0010i <= wire_nlOO0liOl_dataout; + nlOO0010l <= wire_nlOO0liOO_dataout; + nlOO0010O <= wire_nlOO0ll1i_dataout; + nlOO0011i <= wire_nlOO0lill_dataout; + nlOO0011l <= wire_nlOO0lilO_dataout; + nlOO0011O <= wire_nlOO0liOi_dataout; + nlOO001ii <= wire_nlOO0ll1l_dataout; + nlOO001il <= wire_nlOO0ll1O_dataout; + nlOO001iO <= wire_nlOO0ll0i_dataout; + nlOO001li <= wire_nlOO0ll0l_dataout; + nlOO001ll <= wire_nlOO0ll0O_dataout; + nlOO001lO <= wire_nlOO0llii_dataout; + nlOO001Oi <= wire_nlOO0llil_dataout; + nlOO001Ol <= wire_nlOO0lliO_dataout; + nlOO001OO <= wire_nlOO0llli_dataout; + nlOO00i0i <= wire_nlOO0lOOl_dataout; + nlOO00i0l <= wire_nlOO0lOOO_dataout; + nlOO00i0O <= wire_nlOO0O11i_dataout; + nlOO00i1i <= wire_nlOO0lOll_dataout; + nlOO00i1l <= wire_nlOO0lOlO_dataout; + nlOO00i1O <= wire_nlOO0lOOi_dataout; + nlOO00iii <= wire_nlOO0O11l_dataout; + nlOO00iil <= wire_nlOO0O11O_dataout; + nlOO00iiO <= wire_nlOO0O10i_dataout; + nlOO00ili <= wire_nlOO0O10l_dataout; + nlOO00ill <= wire_nlOO0O10O_dataout; + nlOO00ilO <= wire_nlOO0O1ii_dataout; + nlOO00iOi <= wire_nlOO0O1il_dataout; + nlOO00iOl <= wire_nlOO0O1iO_dataout; + nlOO00iOO <= wire_nlOO0O1li_dataout; + nlOO00l0i <= wire_nlOO0O1Ol_dataout; + nlOO00l0l <= wire_nlOO0O1OO_dataout; + nlOO00l0O <= wire_nlOO0O01i_dataout; + nlOO00l1i <= wire_nlOO0O1ll_dataout; + nlOO00l1l <= wire_nlOO0O1lO_dataout; + nlOO00l1O <= wire_nlOO0O1Oi_dataout; + nlOO00lii <= wire_nlOO0O01l_dataout; + nlOO00lil <= wire_nlOO0O01O_dataout; + nlOO00liO <= wire_nlOO0O00i_dataout; + nlOO00lli <= wire_nlOO0O00l_dataout; + nlOO00lll <= wire_nlOO0O00O_dataout; + nlOO00llO <= wire_nlOO0O0ii_dataout; + nlOO00lOi <= wire_nlOO0O0il_dataout; + nlOO00lOl <= wire_nlOO0O0iO_dataout; + nlOO00lOO <= wire_nlOO0O0li_dataout; + nlOO00O0i <= wire_nlOO0O0Ol_dataout; + nlOO00O0l <= wire_nlOO0O0OO_dataout; + nlOO00O0O <= wire_nlOO0Oi1i_dataout; + nlOO00O1i <= wire_nlOO0O0ll_dataout; + nlOO00O1l <= wire_nlOO0O0lO_dataout; + nlOO00O1O <= wire_nlOO0O0Oi_dataout; + nlOO00Oii <= wire_nlOO0Oi1l_dataout; + nlOO00Oil <= wire_nlOO0Oi1O_dataout; + nlOO00OiO <= wire_nlOO0Oi0i_dataout; + nlOO00Oli <= wire_nlOO0Oi0l_dataout; + nlOO00Oll <= wire_nlOO0Oi0O_dataout; + nlOO00OlO <= wire_nlOO0Oiii_dataout; + nlOO00OOi <= wire_nlOO0Oiil_dataout; + nlOO00OOl <= wire_nlOO0OiiO_dataout; + nlOO00OOO <= wire_nlOO0Oili_dataout; + nlOO0100l <= wire_nlOO0ilOO_dataout; + nlOO0100O <= wire_nlOO0iO1i_dataout; + nlOO010ii <= wire_nlOO0iO1l_dataout; + nlOO010il <= wire_nlOO0iO1O_dataout; + nlOO010iO <= wire_nlOO0iO0i_dataout; + nlOO010li <= wire_nlOO0iO0l_dataout; + nlOO010ll <= wire_nlOO0iO0O_dataout; + nlOO010lO <= wire_nlOO0iOii_dataout; + nlOO010Oi <= wire_nlOO0iOil_dataout; + nlOO010Ol <= wire_nlOO0iOiO_dataout; + nlOO010OO <= wire_nlOO0iOli_dataout; + nlOO01i0i <= wire_nlOO0iOOl_dataout; + nlOO01i0l <= wire_nlOO0iOOO_dataout; + nlOO01i0O <= wire_nlOO0l11i_dataout; + nlOO01i1i <= wire_nlOO0iOll_dataout; + nlOO01i1l <= wire_nlOO0iOlO_dataout; + nlOO01i1O <= wire_nlOO0iOOi_dataout; + nlOO01iii <= wire_nlOO0l11l_dataout; + nlOO01iil <= wire_nlOO0l11O_dataout; + nlOO01iiO <= wire_nlOO0l10i_dataout; + nlOO01ili <= wire_nlOO0l10l_dataout; + nlOO01ill <= wire_nlOO0l10O_dataout; + nlOO01ilO <= wire_nlOO0l1ii_dataout; + nlOO01iOi <= wire_nlOO0l1il_dataout; + nlOO01iOl <= wire_nlOO0l1iO_dataout; + nlOO01iOO <= wire_nlOO0l1li_dataout; + nlOO01l0i <= wire_nlOO0l1Ol_dataout; + nlOO01l0l <= wire_nlOO0l1OO_dataout; + nlOO01l0O <= wire_nlOO0l01i_dataout; + nlOO01l1i <= wire_nlOO0l1ll_dataout; + nlOO01l1l <= wire_nlOO0l1lO_dataout; + nlOO01l1O <= wire_nlOO0l1Oi_dataout; + nlOO01lii <= wire_nlOO0l01l_dataout; + nlOO01lil <= wire_nlOO0l01O_dataout; + nlOO01liO <= wire_nlOO0l00i_dataout; + nlOO01lli <= wire_nlOO0l00l_dataout; + nlOO01lll <= wire_nlOO0l00O_dataout; + nlOO01llO <= wire_nlOO0l0ii_dataout; + nlOO01lOi <= wire_nlOO0l0il_dataout; + nlOO01lOl <= wire_nlOO0l0iO_dataout; + nlOO01lOO <= wire_nlOO0l0li_dataout; + nlOO01O0i <= wire_nlOO0l0Ol_dataout; + nlOO01O0l <= wire_nlOO0l0OO_dataout; + nlOO01O0O <= wire_nlOO0li1i_dataout; + nlOO01O1i <= wire_nlOO0l0ll_dataout; + nlOO01O1l <= wire_nlOO0l0lO_dataout; + nlOO01O1O <= wire_nlOO0l0Oi_dataout; + nlOO01Oii <= wire_nlOO0li1l_dataout; + nlOO01Oil <= wire_nlOO0li1O_dataout; + nlOO01OiO <= wire_nlOO0li0i_dataout; + nlOO01Oli <= wire_nlOO0li0l_dataout; + nlOO01Oll <= wire_nlOO0li0O_dataout; + nlOO01OlO <= wire_nlOO0liii_dataout; + nlOO01OOi <= wire_nlOO0liil_dataout; + nlOO01OOl <= wire_nlOO0liiO_dataout; + nlOO01OOO <= wire_nlOO0lili_dataout; + nlOO0i00i <= wire_nlOO0OlOl_dataout; + nlOO0i00l <= wire_nlOO0OlOO_dataout; + nlOO0i00O <= wire_nlOO0OO1i_dataout; + nlOO0i01i <= wire_nlOO0Olll_dataout; + nlOO0i01l <= wire_nlOO0OllO_dataout; + nlOO0i01O <= wire_nlOO0OlOi_dataout; + nlOO0i0ii <= wire_nlOO0OO1l_dataout; + nlOO0i0il <= wire_nlOO0OO1O_dataout; + nlOO0i0iO <= wire_nlOO0OO0i_dataout; + nlOO0i0li <= wire_nlOO0OO0l_dataout; + nlOO0i0ll <= wire_nlOO0OO0O_dataout; + nlOO0i0lO <= wire_nlOO0OOii_dataout; + nlOO0i0Oi <= wire_nlOO0OOil_dataout; + nlOO0i0Ol <= wire_nlOO0OOiO_dataout; + nlOO0i0OO <= wire_nlOO0OOli_dataout; + nlOO0i10i <= wire_nlOO0OiOl_dataout; + nlOO0i10l <= wire_nlOO0OiOO_dataout; + nlOO0i10O <= wire_nlOO0Ol1i_dataout; + nlOO0i11i <= wire_nlOO0Oill_dataout; + nlOO0i11l <= wire_nlOO0OilO_dataout; + nlOO0i11O <= wire_nlOO0OiOi_dataout; + nlOO0i1ii <= wire_nlOO0Ol1l_dataout; + nlOO0i1il <= wire_nlOO0Ol1O_dataout; + nlOO0i1iO <= wire_nlOO0Ol0i_dataout; + nlOO0i1li <= wire_nlOO0Ol0l_dataout; + nlOO0i1ll <= wire_nlOO0Ol0O_dataout; + nlOO0i1lO <= wire_nlOO0Olii_dataout; + nlOO0i1Oi <= wire_nlOO0Olil_dataout; + nlOO0i1Ol <= wire_nlOO0OliO_dataout; + nlOO0i1OO <= wire_nlOO0Olli_dataout; + nlOO0ii0i <= wire_nlOO0OOOl_dataout; + nlOO0ii0l <= wire_nlOO0OOOO_dataout; + nlOO0ii0O <= wire_nlOOi111i_dataout; + nlOO0ii1i <= wire_nlOO0OOll_dataout; + nlOO0ii1l <= wire_nlOO0OOlO_dataout; + nlOO0ii1O <= wire_nlOO0OOOi_dataout; + nlOO0iiii <= wire_nlOOi111l_dataout; + nlOO0iiil <= wire_nlOOi111O_dataout; + nlOO0iiiO <= wire_nlOOi110i_dataout; + nlOO0iili <= wire_nlOOi110l_dataout; + nlOO0iill <= wire_nlOOi110O_dataout; + nlOO0iilO <= wire_nlOOi11ii_dataout; + nlOO0iiOi <= wire_nlOOi11il_dataout; + nlOO0iiOl <= wire_nlOOi11iO_dataout; + nlOO0iiOO <= wire_nlOOi11li_dataout; + nlOO0il0i <= wire_nlOOi11Ol_dataout; + nlOO0il0l <= wire_nlOOi11OO_dataout; + nlOO0il0O <= wire_nlOOi101i_dataout; + nlOO0il1i <= wire_nlOOi11ll_dataout; + nlOO0il1l <= wire_nlOOi11lO_dataout; + nlOO0il1O <= wire_nlOOi11Oi_dataout; + nlOO0ilii <= wire_nlOOi101l_dataout; + nlOO0ilil <= wire_nlOOi101O_dataout; + nlOO0iliO <= wire_nlOOi100i_dataout; + nlOO0illi <= wire_nlOOi100l_dataout; + nlOO0illl <= wire_nlOOi100O_dataout; + nlOO0illO <= wire_nlOOi10ii_dataout; + nlOO0ilOi <= wire_nlOOOl00l_dataout; + nlOO10Oli <= wire_nlOO1i1Ol_dataout; + nlOO1i10O <= wire_nlOO1i1OO_dataout; + nlOO1i1ii <= wire_nlOO1i01i_dataout; + nlOO1i1il <= wire_nlOO1i01l_dataout; + nlOO1i1iO <= wire_nlOO1i01O_dataout; + nlOO1i1li <= wire_nlOO1i00i_dataout; + nlOO1i1ll <= wire_nlOO1i00l_dataout; + nlOO1i1lO <= wire_nlOO1i00O_dataout; + nlOO1i1Oi <= wire_nlOO1O01i_dataout; + nlOO1O10O <= wire_nlOO1O01l_dataout; + nlOO1O1ii <= wire_nlOO1O01O_dataout; + nlOO1O1il <= wire_nlOO1O00i_dataout; + nlOO1O1iO <= wire_nlOO1O00l_dataout; + nlOO1O1li <= wire_nlOO1O00O_dataout; + nlOO1O1ll <= wire_nlOO1O0ii_dataout; + nlOO1O1lO <= wire_nlOO1O0il_dataout; + nlOO1O1Oi <= wire_nlOO1O0iO_dataout; + nlOO1O1Ol <= wire_nlOO1O0li_dataout; + nlOO1O1OO <= wire_nlOO0ilOl_dataout; + nlOOO0OlO <= wire_nlOOOl00O_dataout; + nlOOO0OOi <= wire_nlOOOl0ii_dataout; + nlOOO0OOl <= wire_nlOOOl0il_dataout; + nlOOO0OOO <= wire_nlOOOl0iO_dataout; + nlOOOi00i <= wire_nlOOOliOi_dataout; + nlOOOi00l <= wire_nlOOOliOl_dataout; + nlOOOi00O <= wire_nlOOOliOO_dataout; + nlOOOi01i <= wire_nlOOOlili_dataout; + nlOOOi01l <= wire_nlOOOlill_dataout; + nlOOOi01O <= wire_nlOOOlilO_dataout; + nlOOOi0ii <= wire_nlOOOll1i_dataout; + nlOOOi0il <= wire_nlOOOll1l_dataout; + nlOOOi0iO <= wire_nlOOOll1O_dataout; + nlOOOi0li <= wire_nlOOOll0i_dataout; + nlOOOi0ll <= wire_nlOOOll0l_dataout; + nlOOOi0lO <= wire_nlOOOll0O_dataout; + nlOOOi0Oi <= wire_nlOOOllii_dataout; + nlOOOi0Ol <= wire_nlOOOllil_dataout; + nlOOOi0OO <= wire_nlOOOlliO_dataout; + nlOOOi10i <= wire_nlOOOl0Oi_dataout; + nlOOOi10l <= wire_nlOOOl0Ol_dataout; + nlOOOi10O <= wire_nlOOOl0OO_dataout; + nlOOOi11i <= wire_nlOOOl0li_dataout; + nlOOOi11l <= wire_nlOOOl0ll_dataout; + nlOOOi11O <= wire_nlOOOl0lO_dataout; + nlOOOi1ii <= wire_nlOOOli1i_dataout; + nlOOOi1il <= wire_nlOOOli1l_dataout; + nlOOOi1iO <= wire_nlOOOli1O_dataout; + nlOOOi1li <= wire_nlOOOli0i_dataout; + nlOOOi1ll <= wire_nlOOOli0l_dataout; + nlOOOi1lO <= wire_nlOOOli0O_dataout; + nlOOOi1Oi <= wire_nlOOOliii_dataout; + nlOOOi1Ol <= wire_nlOOOliil_dataout; + nlOOOi1OO <= wire_nlOOOliiO_dataout; + nlOOOii0i <= wire_nlOOOllOi_dataout; + nlOOOii0l <= wire_nlOOOllOl_dataout; + nlOOOii0O <= wire_nlOOOllOO_dataout; + nlOOOii1i <= wire_nlOOOllli_dataout; + nlOOOii1l <= wire_nlOOOllll_dataout; + nlOOOii1O <= wire_nlOOOlllO_dataout; + nlOOOiiii <= wire_nlOOOlO1i_dataout; + nlOOOiiil <= wire_nlOOOlO1l_dataout; + nlOOOiiiO <= wire_nlOOOlO1O_dataout; + nlOOOiili <= wire_nlOOOlO0i_dataout; + nlOOOiill <= wire_nlOOOlO0l_dataout; + nlOOOiilO <= wire_nlOOOlO0O_dataout; + nlOOOiiOi <= wire_nlOOOlOii_dataout; + nlOOOiiOl <= wire_nlOOOlOil_dataout; + nlOOOiiOO <= wire_nlOOOlOiO_dataout; + nlOOOil0i <= wire_nlOOOlOOi_dataout; + nlOOOil0l <= wire_nlOOOlOOl_dataout; + nlOOOil0O <= wire_nlOOOlOOO_dataout; + nlOOOil1i <= wire_nlOOOlOli_dataout; + nlOOOil1l <= wire_nlOOOlOll_dataout; + nlOOOil1O <= wire_nlOOOlOlO_dataout; + nlOOOilii <= wire_nlOOOO11i_dataout; + nlOOOilil <= wire_nlOOOO11l_dataout; + nlOOOiliO <= wire_nlOOOO11O_dataout; + nlOOOilli <= wire_nlOOOO10i_dataout; + nlOOOilll <= wire_nlOOOO10l_dataout; + nlOOOillO <= wire_nlOOOO10O_dataout; + nlOOOilOi <= wire_nlOOOO1ii_dataout; + nlOOOilOl <= wire_nlOOOO1il_dataout; + nlOOOilOO <= wire_nlOOOO1iO_dataout; + nlOOOiO0i <= wire_nlOOOO1Oi_dataout; + nlOOOiO0l <= wire_nlOOOO1Ol_dataout; + nlOOOiO0O <= wire_nlOOOO1OO_dataout; + nlOOOiO1i <= wire_nlOOOO1li_dataout; + nlOOOiO1l <= wire_nlOOOO1ll_dataout; + nlOOOiO1O <= wire_nlOOOO1lO_dataout; + nlOOOiOii <= wire_nlOOOO01i_dataout; + nlOOOiOil <= wire_nlOOOO01l_dataout; + nlOOOiOiO <= wire_nlOOOO01O_dataout; + nlOOOiOli <= wire_nlOOOO00i_dataout; + nlOOOiOll <= wire_nlOOOO00l_dataout; + nlOOOiOlO <= wire_nlOOOO00O_dataout; + nlOOOiOOi <= wire_nlOOOO0ii_dataout; + nlOOOiOOl <= wire_nlOOOO0il_dataout; + nlOOOiOOO <= wire_nlOOOO0iO_dataout; + nlOOOl00i <= wire_n111i0iO_dataout; + nlOOOl01i <= wire_nlOOOOili_dataout; + nlOOOl01l <= wire_nlOOOOill_dataout; + nlOOOl01O <= wire_nlOOOOilO_dataout; + nlOOOl10i <= wire_nlOOOO0Oi_dataout; + nlOOOl10l <= wire_nlOOOO0Ol_dataout; + nlOOOl10O <= wire_nlOOOO0OO_dataout; + nlOOOl11i <= wire_nlOOOO0li_dataout; + nlOOOl11l <= wire_nlOOOO0ll_dataout; + nlOOOl11O <= wire_nlOOOO0lO_dataout; + nlOOOl1ii <= wire_nlOOOOi1i_dataout; + nlOOOl1il <= wire_nlOOOOi1l_dataout; + nlOOOl1iO <= wire_nlOOOOi1O_dataout; + nlOOOl1li <= wire_nlOOOOi0i_dataout; + nlOOOl1ll <= wire_nlOOOOi0l_dataout; + nlOOOl1lO <= wire_nlOOOOi0O_dataout; + nlOOOl1Oi <= wire_nlOOOOiii_dataout; + nlOOOl1Ol <= wire_nlOOOOiil_dataout; + nlOOOl1OO <= wire_nlOOOOiiO_dataout; + END IF; + END PROCESS; + wire_niO01ill_w_lg_w25198w25199w(0) <= wire_niO01ill_w25198w(0) AND n1iOl1li; + wire_niO01ill_w25198w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_w25193w25195w25196w25197w(0) AND n1iOl1ll; + wire_niO01ill_w_lg_w_lg_w_lg_w25193w25195w25196w25197w(0) <= wire_niO01ill_w_lg_w_lg_w25193w25195w25196w(0) AND n1iOl1lO; + wire_niO01ill_w_lg_w_lg_w25193w25195w25196w(0) <= wire_niO01ill_w_lg_w25193w25195w(0) AND n1iOl1Oi; + wire_niO01ill_w_lg_w25193w25195w(0) <= wire_niO01ill_w25193w(0) AND wire_niO01ill_w_lg_n1iOl1Ol25194w(0); + wire_niO01ill_w25193w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_w25186w25188w25189w25191w(0) AND wire_niO01ill_w_lg_n1iOl1OO25192w(0); + wire_niO01ill_w_lg_w_lg_w_lg_w25186w25188w25189w25191w(0) <= wire_niO01ill_w_lg_w_lg_w25186w25188w25189w(0) AND wire_niO01ill_w_lg_n1iOl01i25190w(0); + wire_niO01ill_w_lg_w_lg_w_lg_w19876w19877w19879w19880w(0) <= wire_niO01ill_w_lg_w_lg_w19876w19877w19879w(0) AND n1l001iO; + wire_niO01ill_w_lg_w_lg_w26895w26896w26908w(0) <= wire_niO01ill_w_lg_w26895w26896w(0) AND n1101l1O; + wire_niO01ill_w_lg_w_lg_w19898w19899w19900w(0) <= wire_niO01ill_w_lg_w19898w19899w(0) AND n1l001iO; + wire_niO01ill_w_lg_w_lg_w19887w19888w19889w(0) <= wire_niO01ill_w_lg_w19887w19888w(0) AND n1l001iO; + wire_niO01ill_w_lg_w_lg_w10651w10652w10653w(0) <= wire_niO01ill_w_lg_w10651w10652w(0) AND ni1111OO; + wire_niO01ill_w_lg_w_lg_w16942w16943w16944w(0) <= wire_niO01ill_w_lg_w16942w16943w(0) AND n000i1Ol; + wire_niO01ill_w_lg_w_lg_w16035w16036w16037w(0) <= wire_niO01ill_w_lg_w16035w16036w(0) AND n00OOO1O; + wire_niO01ill_w_lg_w_lg_w17849w17850w17851w(0) <= wire_niO01ill_w_lg_w17849w17850w(0) AND n01iOili; + wire_niO01ill_w_lg_w_lg_w15128w15129w15130w(0) <= wire_niO01ill_w_lg_w15128w15129w(0) AND n0iliiii; + wire_niO01ill_w_lg_w_lg_w14221w14222w14223w(0) <= wire_niO01ill_w_lg_w14221w14222w(0) AND n0li11ll; + wire_niO01ill_w_lg_w_lg_w13314w13315w13316w(0) <= wire_niO01ill_w_lg_w13314w13315w(0) AND n0O1ilOO; + wire_niO01ill_w_lg_w_lg_w12407w12408w12409w(0) <= wire_niO01ill_w_lg_w12407w12408w(0) AND n0OO1i0i; + wire_niO01ill_w_lg_w_lg_w19844w23519w23520w(0) <= wire_niO01ill_w_lg_w19844w23519w(0) AND n1110Oii; + wire_niO01ill_w_lg_w_lg_w25186w25188w25189w(0) <= wire_niO01ill_w_lg_w25186w25188w(0) AND n1iOl01l; + wire_niO01ill_w_lg_w_lg_w19876w19877w19879w(0) <= wire_niO01ill_w_lg_w19876w19877w(0) AND wire_niO01ill_w_lg_n1l001li19878w(0); + wire_niO01ill_w_lg_w_lg_w18756w18757w18758w(0) <= wire_niO01ill_w_lg_w18756w18757w(0) AND n1OO0O0O; + wire_niO01ill_w_lg_w_lg_w10502w10503w10504w(0) <= wire_niO01ill_w_lg_w10502w10503w(0) AND niiii00i; + wire_niO01ill_w_lg_w_lg_w10517w10518w10519w(0) <= wire_niO01ill_w_lg_w10517w10518w(0) AND niiii00i; + wire_niO01ill_w_lg_w_lg_w10525w10526w10527w(0) <= wire_niO01ill_w_lg_w10525w10526w(0) AND niiii00i; + wire_niO01ill_w_lg_w_lg_w10602w10603w10604w(0) <= wire_niO01ill_w_lg_w10602w10603w(0) AND niiii11i; + wire_niO01ill_w_lg_w_lg_w10617w10618w10619w(0) <= wire_niO01ill_w_lg_w10617w10618w(0) AND niiii11i; + wire_niO01ill_w_lg_w_lg_w10625w10626w10627w(0) <= wire_niO01ill_w_lg_w10625w10626w(0) AND niiii11i; + wire_niO01ill_w_lg_w_lg_w10552w10553w10554w(0) <= wire_niO01ill_w_lg_w10552w10553w(0) AND niiii1li; + wire_niO01ill_w_lg_w_lg_w10567w10568w10569w(0) <= wire_niO01ill_w_lg_w10567w10568w(0) AND niiii1li; + wire_niO01ill_w_lg_w_lg_w10575w10576w10577w(0) <= wire_niO01ill_w_lg_w10575w10576w(0) AND niiii1li; + wire_niO01ill_w_lg_w_lg_w10452w10453w10454w(0) <= wire_niO01ill_w_lg_w10452w10453w(0) AND niiii0Oi; + wire_niO01ill_w_lg_w_lg_w10467w10468w10469w(0) <= wire_niO01ill_w_lg_w10467w10468w(0) AND niiii0Oi; + wire_niO01ill_w_lg_w_lg_w10475w10476w10477w(0) <= wire_niO01ill_w_lg_w10475w10476w(0) AND niiii0Oi; + wire_niO01ill_w_lg_w_lg_w10402w10403w10404w(0) <= wire_niO01ill_w_lg_w10402w10403w(0) AND niiiiiii; + wire_niO01ill_w_lg_w_lg_w10417w10418w10419w(0) <= wire_niO01ill_w_lg_w10417w10418w(0) AND niiiiiii; + wire_niO01ill_w_lg_w_lg_w10425w10426w10427w(0) <= wire_niO01ill_w_lg_w10425w10426w(0) AND niiiiiii; + wire_niO01ill_w_lg_w_lg_w10352w10353w10354w(0) <= wire_niO01ill_w_lg_w10352w10353w(0) AND niiiil1i; + wire_niO01ill_w_lg_w_lg_w10367w10368w10369w(0) <= wire_niO01ill_w_lg_w10367w10368w(0) AND niiiil1i; + wire_niO01ill_w_lg_w_lg_w10375w10376w10377w(0) <= wire_niO01ill_w_lg_w10375w10376w(0) AND niiiil1i; + wire_niO01ill_w_lg_w_lg_w10302w10303w10304w(0) <= wire_niO01ill_w_lg_w10302w10303w(0) AND niiiilli; + wire_niO01ill_w_lg_w_lg_w10317w10318w10319w(0) <= wire_niO01ill_w_lg_w10317w10318w(0) AND niiiilli; + wire_niO01ill_w_lg_w_lg_w10325w10326w10327w(0) <= wire_niO01ill_w_lg_w10325w10326w(0) AND niiiilli; + wire_niO01ill_w_lg_w_lg_w10252w10253w10254w(0) <= wire_niO01ill_w_lg_w10252w10253w(0) AND niiiiO0i; + wire_niO01ill_w_lg_w_lg_w10267w10268w10269w(0) <= wire_niO01ill_w_lg_w10267w10268w(0) AND niiiiO0i; + wire_niO01ill_w_lg_w_lg_w10275w10276w10277w(0) <= wire_niO01ill_w_lg_w10275w10276w(0) AND niiiiO0i; + wire_niO01ill_w_lg_w16931w16932w(0) <= wire_niO01ill_w16931w(0) AND n000i1Ol; + wire_niO01ill_w_lg_w16024w16025w(0) <= wire_niO01ill_w16024w(0) AND n00OOO1O; + wire_niO01ill_w_lg_w17838w17839w(0) <= wire_niO01ill_w17838w(0) AND n01iOili; + wire_niO01ill_w_lg_w15117w15118w(0) <= wire_niO01ill_w15117w(0) AND n0iliiii; + wire_niO01ill_w_lg_w14210w14211w(0) <= wire_niO01ill_w14210w(0) AND n0li11ll; + wire_niO01ill_w_lg_w13303w13304w(0) <= wire_niO01ill_w13303w(0) AND n0O1ilOO; + wire_niO01ill_w_lg_w12396w12397w(0) <= wire_niO01ill_w12396w(0) AND n0OO1i0i; + wire_niO01ill_w_lg_w26895w26896w(0) <= wire_niO01ill_w26895w(0) AND n1101l0i; + wire_niO01ill_w_lg_w19898w19899w(0) <= wire_niO01ill_w19898w(0) AND n1l001li; + wire_niO01ill_w_lg_w19887w19888w(0) <= wire_niO01ill_w19887w(0) AND n1l001li; + wire_niO01ill_w_lg_w18745w18746w(0) <= wire_niO01ill_w18745w(0) AND n1OO0O0O; + wire_niO01ill_w_lg_w10651w10652w(0) <= wire_niO01ill_w10651w(0) AND ni11101i; + wire_niO01ill_w_lg_w10640w10641w(0) <= wire_niO01ill_w10640w(0) AND ni11101i; + wire_niO01ill_w_lg_w10491w10492w(0) <= wire_niO01ill_w10491w(0) AND niiii00i; + wire_niO01ill_w_lg_w10511w10512w(0) <= wire_niO01ill_w10511w(0) AND niiii00i; + wire_niO01ill_w_lg_w10591w10592w(0) <= wire_niO01ill_w10591w(0) AND niiii11i; + wire_niO01ill_w_lg_w10611w10612w(0) <= wire_niO01ill_w10611w(0) AND niiii11i; + wire_niO01ill_w_lg_w10541w10542w(0) <= wire_niO01ill_w10541w(0) AND niiii1li; + wire_niO01ill_w_lg_w10561w10562w(0) <= wire_niO01ill_w10561w(0) AND niiii1li; + wire_niO01ill_w_lg_w10441w10442w(0) <= wire_niO01ill_w10441w(0) AND niiii0Oi; + wire_niO01ill_w_lg_w10461w10462w(0) <= wire_niO01ill_w10461w(0) AND niiii0Oi; + wire_niO01ill_w_lg_w10391w10392w(0) <= wire_niO01ill_w10391w(0) AND niiiiiii; + wire_niO01ill_w_lg_w10411w10412w(0) <= wire_niO01ill_w10411w(0) AND niiiiiii; + wire_niO01ill_w_lg_w10341w10342w(0) <= wire_niO01ill_w10341w(0) AND niiiil1i; + wire_niO01ill_w_lg_w10361w10362w(0) <= wire_niO01ill_w10361w(0) AND niiiil1i; + wire_niO01ill_w_lg_w10291w10292w(0) <= wire_niO01ill_w10291w(0) AND niiiilli; + wire_niO01ill_w_lg_w10311w10312w(0) <= wire_niO01ill_w10311w(0) AND niiiilli; + wire_niO01ill_w_lg_w10241w10242w(0) <= wire_niO01ill_w10241w(0) AND niiiiO0i; + wire_niO01ill_w_lg_w10261w10262w(0) <= wire_niO01ill_w10261w(0) AND niiiiO0i; + wire_niO01ill_w_lg_w_lg_w15590w15593w15594w(0) <= wire_niO01ill_w_lg_w15590w15593w(0) AND niOll1O1O; + wire_niO01ill_w_lg_w_lg_w17404w17407w17408w(0) <= wire_niO01ill_w_lg_w17404w17407w(0) AND niOlili0l; + wire_niO01ill_w_lg_w_lg_w16497w16500w16501w(0) <= wire_niO01ill_w_lg_w16497w16500w(0) AND niOliOl0i; + wire_niO01ill_w_lg_w_lg_w14683w14686w14687w(0) <= wire_niO01ill_w_lg_w14683w14686w(0) AND niOlli11l; + wire_niO01ill_w_lg_w_lg_w13776w13779w13780w(0) <= wire_niO01ill_w_lg_w13776w13779w(0) AND niOlll01i; + wire_niO01ill_w_lg_w_lg_w12869w12872w12873w(0) <= wire_niO01ill_w_lg_w12869w12872w(0) AND niOllO0OO; + wire_niO01ill_w_lg_w_lg_w11958w11961w11962w(0) <= wire_niO01ill_w_lg_w11958w11961w(0) AND niOlO1iOl; + wire_niO01ill_w_lg_w_lg_w18311w18314w18315w(0) <= wire_niO01ill_w_lg_w18311w18314w(0) AND niOlii00O; + wire_niO01ill_w_lg_w16942w16943w(0) <= wire_niO01ill_w16942w(0) AND n000i1OO; + wire_niO01ill_w_lg_w16035w16036w(0) <= wire_niO01ill_w16035w(0) AND n00OOO0i; + wire_niO01ill_w_lg_w17849w17850w(0) <= wire_niO01ill_w17849w(0) AND n01iOill; + wire_niO01ill_w_lg_w15128w15129w(0) <= wire_niO01ill_w15128w(0) AND n0iliiil; + wire_niO01ill_w_lg_w14221w14222w(0) <= wire_niO01ill_w14221w(0) AND n0li11lO; + wire_niO01ill_w_lg_w13314w13315w(0) <= wire_niO01ill_w13314w(0) AND n0O1iO1i; + wire_niO01ill_w_lg_w12407w12408w(0) <= wire_niO01ill_w12407w(0) AND n0OO1i0l; + wire_niO01ill_w_lg_w19844w23519w(0) <= wire_niO01ill_w19844w(0) AND n1lillil; + wire_niO01ill_w_lg_w25186w25188w(0) <= wire_niO01ill_w25186w(0) AND wire_niO01ill_w_lg_n1iOl00i25187w(0); + wire_niO01ill_w_lg_w19876w19877w(0) <= wire_niO01ill_w19876w(0) AND n1l001ll; + wire_niO01ill_w_lg_w18756w18757w(0) <= wire_niO01ill_w18756w(0) AND n1OO0Oii; + wire_niO01ill_w_lg_w10502w10503w(0) <= wire_niO01ill_w10502w(0) AND niiii00l; + wire_niO01ill_w_lg_w10517w10518w(0) <= wire_niO01ill_w10517w(0) AND niiii00l; + wire_niO01ill_w_lg_w10525w10526w(0) <= wire_niO01ill_w10525w(0) AND niiii00l; + wire_niO01ill_w_lg_w10602w10603w(0) <= wire_niO01ill_w10602w(0) AND niiii11l; + wire_niO01ill_w_lg_w10617w10618w(0) <= wire_niO01ill_w10617w(0) AND niiii11l; + wire_niO01ill_w_lg_w10625w10626w(0) <= wire_niO01ill_w10625w(0) AND niiii11l; + wire_niO01ill_w_lg_w10552w10553w(0) <= wire_niO01ill_w10552w(0) AND niiii1ll; + wire_niO01ill_w_lg_w10567w10568w(0) <= wire_niO01ill_w10567w(0) AND niiii1ll; + wire_niO01ill_w_lg_w10575w10576w(0) <= wire_niO01ill_w10575w(0) AND niiii1ll; + wire_niO01ill_w_lg_w10452w10453w(0) <= wire_niO01ill_w10452w(0) AND niiii0Ol; + wire_niO01ill_w_lg_w10467w10468w(0) <= wire_niO01ill_w10467w(0) AND niiii0Ol; + wire_niO01ill_w_lg_w10475w10476w(0) <= wire_niO01ill_w10475w(0) AND niiii0Ol; + wire_niO01ill_w_lg_w10402w10403w(0) <= wire_niO01ill_w10402w(0) AND niiiiiil; + wire_niO01ill_w_lg_w10417w10418w(0) <= wire_niO01ill_w10417w(0) AND niiiiiil; + wire_niO01ill_w_lg_w10425w10426w(0) <= wire_niO01ill_w10425w(0) AND niiiiiil; + wire_niO01ill_w_lg_w10352w10353w(0) <= wire_niO01ill_w10352w(0) AND niiiil1l; + wire_niO01ill_w_lg_w10367w10368w(0) <= wire_niO01ill_w10367w(0) AND niiiil1l; + wire_niO01ill_w_lg_w10375w10376w(0) <= wire_niO01ill_w10375w(0) AND niiiil1l; + wire_niO01ill_w_lg_w10302w10303w(0) <= wire_niO01ill_w10302w(0) AND niiiilll; + wire_niO01ill_w_lg_w10317w10318w(0) <= wire_niO01ill_w10317w(0) AND niiiilll; + wire_niO01ill_w_lg_w10325w10326w(0) <= wire_niO01ill_w10325w(0) AND niiiilll; + wire_niO01ill_w_lg_w10252w10253w(0) <= wire_niO01ill_w10252w(0) AND niiiiO0l; + wire_niO01ill_w_lg_w10267w10268w(0) <= wire_niO01ill_w10267w(0) AND niiiiO0l; + wire_niO01ill_w_lg_w10275w10276w(0) <= wire_niO01ill_w10275w(0) AND niiiiO0l; + wire_niO01ill_w16931w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n000i00i16928w16929w16930w(0) AND n000i1OO; + wire_niO01ill_w16024w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n00OOOil16021w16022w16023w(0) AND n00OOO0i; + wire_niO01ill_w17838w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n01iOiOO17835w17836w17837w(0) AND n01iOill; + wire_niO01ill_w15117w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0iliilO15114w15115w15116w(0) AND n0iliiil; + wire_niO01ill_w14210w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0li101i14207w14208w14209w(0) AND n0li11lO; + wire_niO01ill_w13303w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0O1iO0l13300w13301w13302w(0) AND n0O1iO1i; + wire_niO01ill_w12396w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0OO1iiO12393w12394w12395w(0) AND n0OO1i0l; + wire_niO01ill_w26895w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1101liO26878w26879w26880w(0) AND n1101l0l; + wire_niO01ill_w20897w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1iO0l0O20892w20893w20896w(0) AND niOli101i; + wire_niO01ill_w19898w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19894w19895w19897w(0) AND n1l001ll; + wire_niO01ill_w19887w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19884w19885w19886w(0) AND n1l001ll; + wire_niO01ill_w18745w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1OO0Oll18742w18743w18744w(0) AND n1OO0Oii; + wire_niO01ill_w10651w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_ni11100O10647w10648w10650w(0) AND ni11101l; + wire_niO01ill_w10640w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_ni11100O10637w10638w10639w(0) AND ni11101l; + wire_niO01ill_w10491w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10488w10489w10490w(0) AND niiii00l; + wire_niO01ill_w10511w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10508w10509w10510w(0) AND niiii00l; + wire_niO01ill_w10591w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10588w10589w10590w(0) AND niiii11l; + wire_niO01ill_w10611w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10608w10609w10610w(0) AND niiii11l; + wire_niO01ill_w10541w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10538w10539w10540w(0) AND niiii1ll; + wire_niO01ill_w10561w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10558w10559w10560w(0) AND niiii1ll; + wire_niO01ill_w10441w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10438w10439w10440w(0) AND niiii0Ol; + wire_niO01ill_w10461w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10458w10459w10460w(0) AND niiii0Ol; + wire_niO01ill_w10391w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10388w10389w10390w(0) AND niiiiiil; + wire_niO01ill_w10411w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10408w10409w10410w(0) AND niiiiiil; + wire_niO01ill_w10341w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10338w10339w10340w(0) AND niiiil1l; + wire_niO01ill_w10361w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10358w10359w10360w(0) AND niiiil1l; + wire_niO01ill_w10291w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10288w10289w10290w(0) AND niiiilll; + wire_niO01ill_w10311w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10308w10309w10310w(0) AND niiiilll; + wire_niO01ill_w10241w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10238w10239w10240w(0) AND niiiiO0l; + wire_niO01ill_w10261w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10258w10259w10260w(0) AND niiiiO0l; + wire_niO01ill_w28257w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_nlOiO10ii28254w28255w28256w(0) AND nlOiO101O; + wire_niO01ill_w_lg_w15590w15593w(0) <= wire_niO01ill_w15590w(0) AND wire_niO01ill_w_lg_w_lg_n00l0Oil15591w15592w(0); + wire_niO01ill_w_lg_w17404w17407w(0) <= wire_niO01ill_w17404w(0) AND wire_niO01ill_w_lg_w_lg_n0100iOO17405w17406w(0); + wire_niO01ill_w_lg_w16497w16500w(0) <= wire_niO01ill_w16497w(0) AND wire_niO01ill_w_lg_w_lg_n01OO00i16498w16499w(0); + wire_niO01ill_w_lg_w14683w14686w(0) <= wire_niO01ill_w14683w(0) AND wire_niO01ill_w_lg_w_lg_n0i0OilO14684w14685w(0); + wire_niO01ill_w_lg_w13776w13779w(0) <= wire_niO01ill_w13776w(0) AND wire_niO01ill_w_lg_w_lg_n0l1i01i13777w13778w(0); + wire_niO01ill_w_lg_w12869w12872w(0) <= wire_niO01ill_w12869w(0) AND wire_niO01ill_w_lg_w_lg_n0llOO0l12870w12871w(0); + wire_niO01ill_w_lg_w11958w11961w(0) <= wire_niO01ill_w11958w(0) AND wire_niO01ill_w_lg_w_lg_n0OiiiiO11959w11960w(0); + wire_niO01ill_w_lg_w18311w18314w(0) <= wire_niO01ill_w18311w(0) AND wire_niO01ill_w_lg_w_lg_n1OilOll18312w18313w(0); + wire_niO01ill_w16942w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n000i00i16938w16939w16941w(0) AND n000i01i; + wire_niO01ill_w16238w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n001iliO16235w16236w16237w(0) AND wire_niO01ill_w_lg_n001il0O16230w(0); + wire_niO01ill_w15331w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n00O10Oi15328w15329w15330w(0) AND wire_niO01ill_w_lg_n00O10li15323w(0); + wire_niO01ill_w16035w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n00OOOil16031w16032w16034w(0) AND n00OOO0l; + wire_niO01ill_w17145w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n01i110l17142w17143w17144w(0) AND wire_niO01ill_w_lg_n01i111l17137w(0); + wire_niO01ill_w17849w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n01iOiOO17845w17846w17848w(0) AND n01iOilO; + wire_niO01ill_w14424w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0iil11l14421w14422w14423w(0) AND wire_niO01ill_w_lg_n0iiiOOl14416w(0); + wire_niO01ill_w15128w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0iliilO15124w15125w15127w(0) AND n0iliiiO; + wire_niO01ill_w13517w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0O13514w13515w13516w(0) AND wire_niO01ill_w_lg_n0l01l1O13509w(0); + wire_niO01ill_w14221w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0li101i14217w14218w14220w(0) AND n0li11Oi; + wire_niO01ill_w12610w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0li12607w12608w12609w(0) AND wire_niO01ill_w_lg_n0lOl0ii12602w(0); + wire_niO01ill_w13314w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0O1iO0l13310w13311w13313w(0) AND n0O1iO1l; + wire_niO01ill_w11699w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOl11696w11697w11698w(0) AND wire_niO01ill_w_lg_n0Ol1Oll11691w(0); + wire_niO01ill_w12407w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0OO1iiO12403w12404w12406w(0) AND n0OO1i0O; + wire_niO01ill_w19844w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19841w19842w(0) AND wire_niO01ill_w_lg_n110OOOO19843w(0); + wire_niO01ill_w19926w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19841w19842w(0) AND n110OOOO; + wire_niO01ill_w25186w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1iOl0Oi25180w25182w25184w(0) AND wire_niO01ill_w_lg_n1iOl00l25185w(0); + wire_niO01ill_w19876w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19872w19873w19875w(0) AND n1l001lO; + wire_niO01ill_w18052w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1Olii1i18049w18050w18051w(0) AND wire_niO01ill_w_lg_n1Oli0Oi18044w(0); + wire_niO01ill_w18756w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1OO0Oll18752w18753w18755w(0) AND n1OO0Oil; + wire_niO01ill_w10502w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10499w10501w(0) AND niiii00O; + wire_niO01ill_w10517w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10499w10516w(0) AND niiii00O; + wire_niO01ill_w10525w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10523w10524w(0) AND niiii00O; + wire_niO01ill_w10602w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10599w10601w(0) AND niiii11O; + wire_niO01ill_w10617w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10599w10616w(0) AND niiii11O; + wire_niO01ill_w10625w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10623w10624w(0) AND niiii11O; + wire_niO01ill_w10552w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10549w10551w(0) AND niiii1lO; + wire_niO01ill_w10567w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10549w10566w(0) AND niiii1lO; + wire_niO01ill_w10575w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10573w10574w(0) AND niiii1lO; + wire_niO01ill_w10452w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10449w10451w(0) AND niiii0OO; + wire_niO01ill_w10467w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10449w10466w(0) AND niiii0OO; + wire_niO01ill_w10475w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10473w10474w(0) AND niiii0OO; + wire_niO01ill_w10402w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10399w10401w(0) AND niiiiiiO; + wire_niO01ill_w10417w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10399w10416w(0) AND niiiiiiO; + wire_niO01ill_w10425w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10423w10424w(0) AND niiiiiiO; + wire_niO01ill_w10352w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10349w10351w(0) AND niiiil1O; + wire_niO01ill_w10367w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10349w10366w(0) AND niiiil1O; + wire_niO01ill_w10375w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10373w10374w(0) AND niiiil1O; + wire_niO01ill_w10302w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10299w10301w(0) AND niiiillO; + wire_niO01ill_w10317w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10299w10316w(0) AND niiiillO; + wire_niO01ill_w10325w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10323w10324w(0) AND niiiillO; + wire_niO01ill_w10252w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10249w10251w(0) AND niiiiO0O; + wire_niO01ill_w10267w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10249w10266w(0) AND niiiiO0O; + wire_niO01ill_w10275w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10273w10274w(0) AND niiiiO0O; + wire_niO01ill_w_lg_w_lg_w_lg_n000i00i16928w16929w16930w(0) <= wire_niO01ill_w_lg_w_lg_n000i00i16928w16929w(0) AND n000i01i; + wire_niO01ill_w_lg_w_lg_w_lg_n00OOOil16021w16022w16023w(0) <= wire_niO01ill_w_lg_w_lg_n00OOOil16021w16022w(0) AND n00OOO0l; + wire_niO01ill_w_lg_w_lg_w_lg_n01iOiOO17835w17836w17837w(0) <= wire_niO01ill_w_lg_w_lg_n01iOiOO17835w17836w(0) AND n01iOilO; + wire_niO01ill_w_lg_w_lg_w_lg_n0iliilO15114w15115w15116w(0) <= wire_niO01ill_w_lg_w_lg_n0iliilO15114w15115w(0) AND n0iliiiO; + wire_niO01ill_w_lg_w_lg_w_lg_n0li101i14207w14208w14209w(0) <= wire_niO01ill_w_lg_w_lg_n0li101i14207w14208w(0) AND n0li11Oi; + wire_niO01ill_w_lg_w_lg_w_lg_n0O1iO0l13300w13301w13302w(0) <= wire_niO01ill_w_lg_w_lg_n0O1iO0l13300w13301w(0) AND n0O1iO1l; + wire_niO01ill_w_lg_w_lg_w_lg_n0OO1iiO12393w12394w12395w(0) <= wire_niO01ill_w_lg_w_lg_n0OO1iiO12393w12394w(0) AND n0OO1i0O; + wire_niO01ill_w_lg_w_lg_w_lg_n1101liO26878w26879w26880w(0) <= wire_niO01ill_w_lg_w_lg_n1101liO26878w26879w(0) AND n1101l0O; + wire_niO01ill_w_lg_w_lg_w_lg_n1iO0l0O20892w20893w20896w(0) <= wire_niO01ill_w_lg_w_lg_n1iO0l0O20892w20893w(0) AND wire_w_lg_w_lg_niOl0O1iO20894w20895w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19894w19895w19897w(0) <= wire_niO01ill_w_lg_w_lg_n1l001OO19894w19895w(0) AND wire_niO01ill_w_lg_n1l001lO19896w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19884w19885w19886w(0) <= wire_niO01ill_w_lg_w_lg_n1l001OO19884w19885w(0) AND n1l001lO; + wire_niO01ill_w_lg_w_lg_w_lg_n1OO0Oll18742w18743w18744w(0) <= wire_niO01ill_w_lg_w_lg_n1OO0Oll18742w18743w(0) AND n1OO0Oil; + wire_niO01ill_w_lg_w_lg_w_lg_ni11100O10647w10648w10650w(0) <= wire_niO01ill_w_lg_w_lg_ni11100O10647w10648w(0) AND wire_niO01ill_w_lg_ni11101O10649w(0); + wire_niO01ill_w_lg_w_lg_w_lg_ni11100O10637w10638w10639w(0) <= wire_niO01ill_w_lg_w_lg_ni11100O10637w10638w(0) AND ni11101O; + wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10488w10489w10490w(0) <= wire_niO01ill_w_lg_w_lg_niiii0iO10488w10489w(0) AND niiii00O; + wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10508w10509w10510w(0) <= wire_niO01ill_w_lg_w_lg_niiii0iO10508w10509w(0) AND niiii00O; + wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10588w10589w10590w(0) <= wire_niO01ill_w_lg_w_lg_niiii10O10588w10589w(0) AND niiii11O; + wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10608w10609w10610w(0) <= wire_niO01ill_w_lg_w_lg_niiii10O10608w10609w(0) AND niiii11O; + wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10538w10539w10540w(0) <= wire_niO01ill_w_lg_w_lg_niiii1OO10538w10539w(0) AND niiii1lO; + wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10558w10559w10560w(0) <= wire_niO01ill_w_lg_w_lg_niiii1OO10558w10559w(0) AND niiii1lO; + wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10438w10439w10440w(0) <= wire_niO01ill_w_lg_w_lg_niiiii1O10438w10439w(0) AND niiii0OO; + wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10458w10459w10460w(0) <= wire_niO01ill_w_lg_w_lg_niiiii1O10458w10459w(0) AND niiii0OO; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10388w10389w10390w(0) <= wire_niO01ill_w_lg_w_lg_niiiiilO10388w10389w(0) AND niiiiiiO; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10408w10409w10410w(0) <= wire_niO01ill_w_lg_w_lg_niiiiilO10408w10409w(0) AND niiiiiiO; + wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10338w10339w10340w(0) <= wire_niO01ill_w_lg_w_lg_niiiil0O10338w10339w(0) AND niiiil1O; + wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10358w10359w10360w(0) <= wire_niO01ill_w_lg_w_lg_niiiil0O10358w10359w(0) AND niiiil1O; + wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10288w10289w10290w(0) <= wire_niO01ill_w_lg_w_lg_niiiilOO10288w10289w(0) AND niiiillO; + wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10308w10309w10310w(0) <= wire_niO01ill_w_lg_w_lg_niiiilOO10308w10309w(0) AND niiiillO; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10238w10239w10240w(0) <= wire_niO01ill_w_lg_w_lg_niiiiOiO10238w10239w(0) AND niiiiO0O; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10258w10259w10260w(0) <= wire_niO01ill_w_lg_w_lg_niiiiOiO10258w10259w(0) AND niiiiO0O; + wire_niO01ill_w_lg_w_lg_w_lg_nlOiO10ii28254w28255w28256w(0) <= wire_niO01ill_w_lg_w_lg_nlOiO10ii28254w28255w(0) AND nlOiO100i; + wire_niO01ill_w15590w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n00l0lOl15587w15588w15589w(0) AND niOll1O0i; + wire_niO01ill_w17404w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0100i0O17401w17402w17403w(0) AND niOlili0O; + wire_niO01ill_w16497w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n01OO1li16494w16495w16496w(0) AND niOliOl0l; + wire_niO01ill_w14683w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0i0Oi1O14680w14681w14682w(0) AND niOlli11O; + wire_niO01ill_w13776w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0l1i1ii13773w13774w13775w(0) AND niOlll01l; + wire_niO01ill_w12869w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0llOlll12866w12867w12868w(0) AND niOllOi1i; + wire_niO01ill_w11958w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n0Oii0OO11955w11956w11957w(0) AND niOlO1iOO; + wire_niO01ill_w18311w(0) <= wire_niO01ill_w_lg_w_lg_w_lg_n1OilO1l18308w18309w18310w(0) AND niOlii0ii; + wire_niO01ill_w_lg_w_lg_w_lg_n000i00i16938w16939w16941w(0) <= wire_niO01ill_w_lg_w_lg_n000i00i16938w16939w(0) AND wire_niO01ill_w_lg_n000i01l16940w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n001ilil16227w16229w16231w(0) <= wire_niO01ill_w_lg_w_lg_n001ilil16227w16229w(0) AND wire_niO01ill_w_lg_n001il0O16230w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n001iliO16235w16236w16237w(0) <= wire_niO01ill_w_lg_w_lg_n001iliO16235w16236w(0) AND wire_niO01ill_w_lg_n001ilii16228w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n001iliO16235w16653w16657w(0) <= wire_niO01ill_w_lg_w_lg_n001iliO16235w16653w(0) AND n001ilii; + wire_niO01ill_w_lg_w_lg_w_lg_n001iO0l16165w16167w16168w(0) <= wire_niO01ill_w_lg_w_lg_n001iO0l16165w16167w(0) AND niOll1i1i; + wire_niO01ill_w_lg_w_lg_w_lg_n00ilOOO21080w21082w21083w(0) <= wire_niO01ill_w_lg_w_lg_n00ilOOO21080w21082w(0) AND n00ilOOi; + wire_niO01ill_w_lg_w_lg_w_lg_n00O10lO15320w15322w15324w(0) <= wire_niO01ill_w_lg_w_lg_n00O10lO15320w15322w(0) AND wire_niO01ill_w_lg_n00O10li15323w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n00O10Oi15328w15329w15330w(0) <= wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15329w(0) AND wire_niO01ill_w_lg_n00O10ll15321w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n00O10Oi15328w15746w15750w(0) <= wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15746w(0) AND n00O10ll; + wire_niO01ill_w_lg_w_lg_w_lg_n00O1iiO15258w15260w15261w(0) <= wire_niO01ill_w_lg_w_lg_n00O1iiO15258w15260w(0) AND niOll0iOO; + wire_niO01ill_w_lg_w_lg_w_lg_n00OOOil16031w16032w16034w(0) <= wire_niO01ill_w_lg_w_lg_n00OOOil16031w16032w(0) AND wire_niO01ill_w_lg_n00OOO0O16033w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n011llii21068w21070w21071w(0) <= wire_niO01ill_w_lg_w_lg_n011llii21068w21070w(0) AND n011ll0l; + wire_niO01ill_w_lg_w_lg_w_lg_n01i101i17072w17074w17075w(0) <= wire_niO01ill_w_lg_w_lg_n01i101i17072w17074w(0) AND niOliO01l; + wire_niO01ill_w_lg_w_lg_w_lg_n01i110i17134w17136w17138w(0) <= wire_niO01ill_w_lg_w_lg_n01i110i17134w17136w(0) AND wire_niO01ill_w_lg_n01i111l17137w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n01i110l17142w17143w17144w(0) <= wire_niO01ill_w_lg_w_lg_n01i110l17142w17143w(0) AND wire_niO01ill_w_lg_n01i111O17135w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n01i110l17142w17560w17564w(0) <= wire_niO01ill_w_lg_w_lg_n01i110l17142w17560w(0) AND n01i111O; + wire_niO01ill_w_lg_w_lg_w_lg_n01iOiOO17845w17846w17848w(0) <= wire_niO01ill_w_lg_w_lg_n01iOiOO17845w17846w(0) AND wire_niO01ill_w_lg_n01iOiOi17847w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n01O00ll21074w21076w21077w(0) <= wire_niO01ill_w_lg_w_lg_n01O00ll21074w21076w(0) AND n01O00iO; + wire_niO01ill_w_lg_w_lg_w_lg_n0i00l0i21086w21088w21089w(0) <= wire_niO01ill_w_lg_w_lg_n0i00l0i21086w21088w(0) AND n0i00l1l; + wire_niO01ill_w_lg_w_lg_w_lg_n0iil11i14413w14415w14417w(0) <= wire_niO01ill_w_lg_w_lg_n0iil11i14413w14415w(0) AND wire_niO01ill_w_lg_n0iiiOOl14416w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0iil11l14421w14422w14423w(0) <= wire_niO01ill_w_lg_w_lg_n0iil11l14421w14422w(0) AND wire_niO01ill_w_lg_n0iiiOOO14414w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0iil11l14421w14839w14843w(0) <= wire_niO01ill_w_lg_w_lg_n0iil11l14421w14839w(0) AND n0iiiOOO; + wire_niO01ill_w_lg_w_lg_w_lg_n0iil1Oi14351w14353w14354w(0) <= wire_niO01ill_w_lg_w_lg_n0iil1Oi14351w14353w(0) AND niOllilOl; + wire_niO01ill_w_lg_w_lg_w_lg_n0iliilO15124w15125w15127w(0) <= wire_niO01ill_w_lg_w_lg_n0iliilO15124w15125w(0) AND wire_niO01ill_w_lg_n0iliili15126w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0iOO0il21092w21094w21095w(0) <= wire_niO01ill_w_lg_w_lg_n0iOO0il21092w21094w(0) AND n0iOO00O; + wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0l13506w13508w13510w(0) <= wire_niO01ill_w_lg_w_lg_n0l01l0l13506w13508w(0) AND wire_niO01ill_w_lg_n0l01l1O13509w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0O13514w13515w13516w(0) <= wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13515w(0) AND wire_niO01ill_w_lg_n0l01l0i13507w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0O13514w13932w13936w(0) <= wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13932w(0) AND n0l01l0i; + wire_niO01ill_w_lg_w_lg_w_lg_n0l01O1l13444w13446w13447w(0) <= wire_niO01ill_w_lg_w_lg_n0l01O1l13444w13446w(0) AND niOlllOOi; + wire_niO01ill_w_lg_w_lg_w_lg_n0li101i14217w14218w14220w(0) <= wire_niO01ill_w_lg_w_lg_n0li101i14217w14218w(0) AND wire_niO01ill_w_lg_n0li11Ol14219w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0ll0OlO21098w21100w21101w(0) <= wire_niO01ill_w_lg_w_lg_n0ll0OlO21098w21100w(0) AND n0ll0Oli; + wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0iO12599w12601w12603w(0) <= wire_niO01ill_w_lg_w_lg_n0lOl0iO12599w12601w(0) AND wire_niO01ill_w_lg_n0lOl0ii12602w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0li12607w12608w12609w(0) <= wire_niO01ill_w_lg_w_lg_n0lOl0li12607w12608w(0) AND wire_niO01ill_w_lg_n0lOl0il12600w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0li12607w13025w13029w(0) <= wire_niO01ill_w_lg_w_lg_n0lOl0li12607w13025w(0) AND n0lOl0il; + wire_niO01ill_w_lg_w_lg_w_lg_n0lOli0O12537w12539w12540w(0) <= wire_niO01ill_w_lg_w_lg_n0lOli0O12537w12539w(0) AND niOlO11lO; + wire_niO01ill_w_lg_w_lg_w_lg_n0O0Ol1i21104w21106w21107w(0) <= wire_niO01ill_w_lg_w_lg_n0O0Ol1i21104w21106w(0) AND n0O0OiOl; + wire_niO01ill_w_lg_w_lg_w_lg_n0O1iO0l13310w13311w13313w(0) <= wire_niO01ill_w_lg_w_lg_n0O1iO0l13310w13311w(0) AND wire_niO01ill_w_lg_n0O1iO1O13312w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0Ol01li11625w11627w11628w(0) <= wire_niO01ill_w_lg_w_lg_n0Ol01li11625w11627w(0) AND niOlO00lO; + wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOi11688w11690w11692w(0) <= wire_niO01ill_w_lg_w_lg_n0Ol1OOi11688w11690w(0) AND wire_niO01ill_w_lg_n0Ol1Oll11691w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOl11696w11697w11698w(0) <= wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w11697w(0) AND wire_niO01ill_w_lg_n0Ol1OlO11689w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOl11696w12117w12121w(0) <= wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w12117w(0) AND n0Ol1OlO; + wire_niO01ill_w_lg_w_lg_w_lg_n0OO1iiO12403w12404w12406w(0) <= wire_niO01ill_w_lg_w_lg_n0OO1iiO12403w12404w(0) AND wire_niO01ill_w_lg_n0OO1iii12405w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19850w19921w(0) <= wire_niO01ill_w_lg_w_lg_n11i111O19840w19850w(0) AND n11i111i; + wire_niO01ill_w_lg_w_lg_w_lg_n11i111O19840w19841w19842w(0) <= wire_niO01ill_w_lg_w_lg_n11i111O19840w19841w(0) AND n11i111i; + wire_niO01ill_w_lg_w_lg_w_lg_n1iOl0Oi25180w25182w25184w(0) <= wire_niO01ill_w_lg_w_lg_n1iOl0Oi25180w25182w(0) AND wire_niO01ill_w_lg_n1iOl00O25183w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n1l0010O11542w11544w11545w(0) <= wire_niO01ill_w_lg_w_lg_n1l0010O11542w11544w(0) AND n1l0010i; + wire_niO01ill_w_lg_w_lg_w_lg_n1l001OO19872w19873w19875w(0) <= wire_niO01ill_w_lg_w_lg_n1l001OO19872w19873w(0) AND wire_niO01ill_w_lg_n1l001Oi19874w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n1lill0O19911w19913w19914w(0) <= wire_niO01ill_w_lg_w_lg_n1lill0O19911w19913w(0) AND n1lill0i; + wire_niO01ill_w_lg_w_lg_w_lg_n1Oi011O21063w21065w21066w(0) <= wire_niO01ill_w_lg_w_lg_n1Oi011O21063w21065w(0) AND n1Oi011i; + wire_niO01ill_w_lg_w_lg_w_lg_n1Oli0OO18041w18043w18045w(0) <= wire_niO01ill_w_lg_w_lg_n1Oli0OO18041w18043w(0) AND wire_niO01ill_w_lg_n1Oli0Oi18044w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n1Olii1i18049w18050w18051w(0) <= wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18050w(0) AND wire_niO01ill_w_lg_n1Oli0Ol18042w(0); + wire_niO01ill_w_lg_w_lg_w_lg_n1Olii1i18049w18467w18471w(0) <= wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18467w(0) AND n1Oli0Ol; + wire_niO01ill_w_lg_w_lg_w_lg_n1OliilO17979w17981w17982w(0) <= wire_niO01ill_w_lg_w_lg_n1OliilO17979w17981w(0) AND niOlil11O; + wire_niO01ill_w_lg_w_lg_w_lg_n1OO0Oll18752w18753w18755w(0) <= wire_niO01ill_w_lg_w_lg_n1OO0Oll18752w18753w(0) AND wire_niO01ill_w_lg_n1OO0OiO18754w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10499w10501w(0) <= wire_niO01ill_w_lg_w_lg_niiii0iO10498w10499w(0) AND wire_niO01ill_w_lg_niiii0ii10500w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10499w10516w(0) <= wire_niO01ill_w_lg_w_lg_niiii0iO10498w10499w(0) AND niiii0ii; + wire_niO01ill_w_lg_w_lg_w_lg_niiii0iO10498w10523w10524w(0) <= wire_niO01ill_w_lg_w_lg_niiii0iO10498w10523w(0) AND niiii0ii; + wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10599w10601w(0) <= wire_niO01ill_w_lg_w_lg_niiii10O10598w10599w(0) AND wire_niO01ill_w_lg_niiii10i10600w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10599w10616w(0) <= wire_niO01ill_w_lg_w_lg_niiii10O10598w10599w(0) AND niiii10i; + wire_niO01ill_w_lg_w_lg_w_lg_niiii10O10598w10623w10624w(0) <= wire_niO01ill_w_lg_w_lg_niiii10O10598w10623w(0) AND niiii10i; + wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10549w10551w(0) <= wire_niO01ill_w_lg_w_lg_niiii1OO10548w10549w(0) AND wire_niO01ill_w_lg_niiii1Oi10550w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10549w10566w(0) <= wire_niO01ill_w_lg_w_lg_niiii1OO10548w10549w(0) AND niiii1Oi; + wire_niO01ill_w_lg_w_lg_w_lg_niiii1OO10548w10573w10574w(0) <= wire_niO01ill_w_lg_w_lg_niiii1OO10548w10573w(0) AND niiii1Oi; + wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10449w10451w(0) <= wire_niO01ill_w_lg_w_lg_niiiii1O10448w10449w(0) AND wire_niO01ill_w_lg_niiiii1i10450w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10449w10466w(0) <= wire_niO01ill_w_lg_w_lg_niiiii1O10448w10449w(0) AND niiiii1i; + wire_niO01ill_w_lg_w_lg_w_lg_niiiii1O10448w10473w10474w(0) <= wire_niO01ill_w_lg_w_lg_niiiii1O10448w10473w(0) AND niiiii1i; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10399w10401w(0) <= wire_niO01ill_w_lg_w_lg_niiiiilO10398w10399w(0) AND wire_niO01ill_w_lg_niiiiili10400w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10399w10416w(0) <= wire_niO01ill_w_lg_w_lg_niiiiilO10398w10399w(0) AND niiiiili; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiilO10398w10423w10424w(0) <= wire_niO01ill_w_lg_w_lg_niiiiilO10398w10423w(0) AND niiiiili; + wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10349w10351w(0) <= wire_niO01ill_w_lg_w_lg_niiiil0O10348w10349w(0) AND wire_niO01ill_w_lg_niiiil0i10350w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10349w10366w(0) <= wire_niO01ill_w_lg_w_lg_niiiil0O10348w10349w(0) AND niiiil0i; + wire_niO01ill_w_lg_w_lg_w_lg_niiiil0O10348w10373w10374w(0) <= wire_niO01ill_w_lg_w_lg_niiiil0O10348w10373w(0) AND niiiil0i; + wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10299w10301w(0) <= wire_niO01ill_w_lg_w_lg_niiiilOO10298w10299w(0) AND wire_niO01ill_w_lg_niiiilOi10300w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10299w10316w(0) <= wire_niO01ill_w_lg_w_lg_niiiilOO10298w10299w(0) AND niiiilOi; + wire_niO01ill_w_lg_w_lg_w_lg_niiiilOO10298w10323w10324w(0) <= wire_niO01ill_w_lg_w_lg_niiiilOO10298w10323w(0) AND niiiilOi; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10249w10251w(0) <= wire_niO01ill_w_lg_w_lg_niiiiOiO10248w10249w(0) AND wire_niO01ill_w_lg_niiiiOii10250w(0); + wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10249w10266w(0) <= wire_niO01ill_w_lg_w_lg_niiiiOiO10248w10249w(0) AND niiiiOii; + wire_niO01ill_w_lg_w_lg_w_lg_niiiiOiO10248w10273w10274w(0) <= wire_niO01ill_w_lg_w_lg_niiiiOiO10248w10273w(0) AND niiiiOii; + wire_niO01ill_w_lg_w_lg_w_lg_nlOO1O1Ol24778w24780w24781w(0) <= wire_niO01ill_w_lg_w_lg_nlOO1O1Ol24778w24780w(0) AND nlOllllii; + wire_niO01ill_w_lg_w_lg_n000i00i16928w16929w(0) <= wire_niO01ill_w_lg_n000i00i16928w(0) AND n000i01l; + wire_niO01ill_w_lg_w_lg_n00OOOil16021w16022w(0) <= wire_niO01ill_w_lg_n00OOOil16021w(0) AND n00OOO0O; + wire_niO01ill_w_lg_w_lg_n01iOiOO17835w17836w(0) <= wire_niO01ill_w_lg_n01iOiOO17835w(0) AND n01iOiOi; + wire_niO01ill_w_lg_w_lg_n0iliilO15114w15115w(0) <= wire_niO01ill_w_lg_n0iliilO15114w(0) AND n0iliili; + wire_niO01ill_w_lg_w_lg_n0li101i14207w14208w(0) <= wire_niO01ill_w_lg_n0li101i14207w(0) AND n0li11Ol; + wire_niO01ill_w_lg_w_lg_n0O1iO0l13300w13301w(0) <= wire_niO01ill_w_lg_n0O1iO0l13300w(0) AND n0O1iO1O; + wire_niO01ill_w_lg_w_lg_n0OO1iiO12393w12394w(0) <= wire_niO01ill_w_lg_n0OO1iiO12393w(0) AND n0OO1iii; + wire_niO01ill_w_lg_w_lg_n1101liO26878w26879w(0) <= wire_niO01ill_w_lg_n1101liO26878w(0) AND n1101lii; + wire_niO01ill_w_lg_w_lg_n11i111O19846w19924w(0) <= wire_niO01ill_w_lg_n11i111O19846w(0) AND n11i111i; + wire_niO01ill_w_lg_w_lg_n11i111O19857w19858w(0) <= wire_niO01ill_w_lg_n11i111O19857w(0) AND n11i111i; + wire_niO01ill_w_lg_w_lg_n1iO0l0O20892w20893w(0) <= wire_niO01ill_w_lg_n1iO0l0O20892w(0) AND niOli101i; + wire_niO01ill_w_lg_w_lg_n1l001OO19894w19895w(0) <= wire_niO01ill_w_lg_n1l001OO19894w(0) AND wire_niO01ill_w_lg_n1l001Oi19874w(0); + wire_niO01ill_w_lg_w_lg_n1l001OO19884w19885w(0) <= wire_niO01ill_w_lg_n1l001OO19884w(0) AND wire_niO01ill_w_lg_n1l001Oi19874w(0); + wire_niO01ill_w_lg_w_lg_n1l00i1O19905w19906w(0) <= wire_niO01ill_w_lg_n1l00i1O19905w(0) AND n1l00i1i; + wire_niO01ill_w_lg_w_lg_n1l00i1O19783w19928w(0) <= wire_niO01ill_w_lg_n1l00i1O19783w(0) AND n1l00i1i; + wire_niO01ill_w_lg_w_lg_n1lill0O19918w19919w(0) <= wire_niO01ill_w_lg_n1lill0O19918w(0) AND n1lill0i; + wire_niO01ill_w_lg_w_lg_n1OO0Oll18742w18743w(0) <= wire_niO01ill_w_lg_n1OO0Oll18742w(0) AND n1OO0OiO; + wire_niO01ill_w_lg_w_lg_ni11100O10647w10648w(0) <= wire_niO01ill_w_lg_ni11100O10647w(0) AND ni11100i; + wire_niO01ill_w_lg_w_lg_ni11100O10637w10638w(0) <= wire_niO01ill_w_lg_ni11100O10637w(0) AND ni11100i; + wire_niO01ill_w_lg_w_lg_niiii0iO10488w10489w(0) <= wire_niO01ill_w_lg_niiii0iO10488w(0) AND niiii0ii; + wire_niO01ill_w_lg_w_lg_niiii0iO10508w10509w(0) <= wire_niO01ill_w_lg_niiii0iO10508w(0) AND niiii0ii; + wire_niO01ill_w_lg_w_lg_niiii10O10588w10589w(0) <= wire_niO01ill_w_lg_niiii10O10588w(0) AND niiii10i; + wire_niO01ill_w_lg_w_lg_niiii10O10608w10609w(0) <= wire_niO01ill_w_lg_niiii10O10608w(0) AND niiii10i; + wire_niO01ill_w_lg_w_lg_niiii1OO10538w10539w(0) <= wire_niO01ill_w_lg_niiii1OO10538w(0) AND niiii1Oi; + wire_niO01ill_w_lg_w_lg_niiii1OO10558w10559w(0) <= wire_niO01ill_w_lg_niiii1OO10558w(0) AND niiii1Oi; + wire_niO01ill_w_lg_w_lg_niiiii1O10438w10439w(0) <= wire_niO01ill_w_lg_niiiii1O10438w(0) AND niiiii1i; + wire_niO01ill_w_lg_w_lg_niiiii1O10458w10459w(0) <= wire_niO01ill_w_lg_niiiii1O10458w(0) AND niiiii1i; + wire_niO01ill_w_lg_w_lg_niiiiilO10388w10389w(0) <= wire_niO01ill_w_lg_niiiiilO10388w(0) AND niiiiili; + wire_niO01ill_w_lg_w_lg_niiiiilO10408w10409w(0) <= wire_niO01ill_w_lg_niiiiilO10408w(0) AND niiiiili; + wire_niO01ill_w_lg_w_lg_niiiil0O10338w10339w(0) <= wire_niO01ill_w_lg_niiiil0O10338w(0) AND niiiil0i; + wire_niO01ill_w_lg_w_lg_niiiil0O10358w10359w(0) <= wire_niO01ill_w_lg_niiiil0O10358w(0) AND niiiil0i; + wire_niO01ill_w_lg_w_lg_niiiilOO10288w10289w(0) <= wire_niO01ill_w_lg_niiiilOO10288w(0) AND niiiilOi; + wire_niO01ill_w_lg_w_lg_niiiilOO10308w10309w(0) <= wire_niO01ill_w_lg_niiiilOO10308w(0) AND niiiilOi; + wire_niO01ill_w_lg_w_lg_niiiiOiO10238w10239w(0) <= wire_niO01ill_w_lg_niiiiOiO10238w(0) AND niiiiOii; + wire_niO01ill_w_lg_w_lg_niiiiOiO10258w10259w(0) <= wire_niO01ill_w_lg_niiiiOiO10258w(0) AND niiiiOii; + wire_niO01ill_w_lg_w_lg_nlOiO10ii28254w28255w(0) <= wire_niO01ill_w_lg_nlOiO10ii28254w(0) AND nlOiO100l; + wire_niO01ill_w_lg_w_lg_w_lg_n00l0lOl15587w15588w15589w(0) <= wire_niO01ill_w_lg_w_lg_n00l0lOl15587w15588w(0) AND niOll1O0l; + wire_niO01ill_w_lg_w_lg_w_lg_n0100i0O17401w17402w17403w(0) <= wire_niO01ill_w_lg_w_lg_n0100i0O17401w17402w(0) AND niOliliii; + wire_niO01ill_w_lg_w_lg_w_lg_n01OO1li16494w16495w16496w(0) <= wire_niO01ill_w_lg_w_lg_n01OO1li16494w16495w(0) AND niOliOl0O; + wire_niO01ill_w_lg_w_lg_w_lg_n0i0Oi1O14680w14681w14682w(0) <= wire_niO01ill_w_lg_w_lg_n0i0Oi1O14680w14681w(0) AND niOlli10i; + wire_niO01ill_w_lg_w_lg_w_lg_n0l1i1ii13773w13774w13775w(0) <= wire_niO01ill_w_lg_w_lg_n0l1i1ii13773w13774w(0) AND niOlll01O; + wire_niO01ill_w_lg_w_lg_w_lg_n0llOlll12866w12867w12868w(0) <= wire_niO01ill_w_lg_w_lg_n0llOlll12866w12867w(0) AND niOllOi1l; + wire_niO01ill_w_lg_w_lg_w_lg_n0Oii0OO11955w11956w11957w(0) <= wire_niO01ill_w_lg_w_lg_n0Oii0OO11955w11956w(0) AND niOlO1l1i; + wire_niO01ill_w_lg_w_lg_w_lg_n1OilO1l18308w18309w18310w(0) <= wire_niO01ill_w_lg_w_lg_n1OilO1l18308w18309w(0) AND niOlii0il; + wire_niO01ill_w_lg_w_lg_n000i00i16938w16939w(0) <= wire_niO01ill_w_lg_n000i00i16938w(0) AND wire_niO01ill_w_lg_n000i01O16927w(0); + wire_niO01ill_w_lg_w_lg_n001ilil16227w16229w(0) <= wire_niO01ill_w_lg_n001ilil16227w(0) AND wire_niO01ill_w_lg_n001ilii16228w(0); + wire_niO01ill_w_lg_w_lg_n001iliO16235w16236w(0) <= wire_niO01ill_w_lg_n001iliO16235w(0) AND wire_niO01ill_w_lg_n001ilil16227w(0); + wire_niO01ill_w_lg_w_lg_n001iliO16235w16653w(0) <= wire_niO01ill_w_lg_n001iliO16235w(0) AND n001ilil; + wire_niO01ill_w_lg_w_lg_n001iO0l16165w16167w(0) <= wire_niO01ill_w_lg_n001iO0l16165w(0) AND wire_niO01ill_w_lg_n001ilOi16166w(0); + wire_niO01ill_w_lg_w_lg_n00ilOOO21080w21082w(0) <= wire_niO01ill_w_lg_n00ilOOO21080w(0) AND wire_niO01ill_w_lg_n00ilOOl21081w(0); + wire_niO01ill_w_lg_w_lg_n00O10lO15320w15322w(0) <= wire_niO01ill_w_lg_n00O10lO15320w(0) AND wire_niO01ill_w_lg_n00O10ll15321w(0); + wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15329w(0) <= wire_niO01ill_w_lg_n00O10Oi15328w(0) AND wire_niO01ill_w_lg_n00O10lO15320w(0); + wire_niO01ill_w_lg_w_lg_n00O10Oi15328w15746w(0) <= wire_niO01ill_w_lg_n00O10Oi15328w(0) AND n00O10lO; + wire_niO01ill_w_lg_w_lg_n00O1iiO15258w15260w(0) <= wire_niO01ill_w_lg_n00O1iiO15258w(0) AND wire_niO01ill_w_lg_n00O1i1l15259w(0); + wire_niO01ill_w_lg_w_lg_n00OOOil16031w16032w(0) <= wire_niO01ill_w_lg_n00OOOil16031w(0) AND wire_niO01ill_w_lg_n00OOOii16020w(0); + wire_niO01ill_w_lg_w_lg_n011llii21068w21070w(0) <= wire_niO01ill_w_lg_n011llii21068w(0) AND wire_niO01ill_w_lg_n011ll0O21069w(0); + wire_niO01ill_w_lg_w_lg_n01i101i17072w17074w(0) <= wire_niO01ill_w_lg_n01i101i17072w(0) AND wire_niO01ill_w_lg_n01i11iO17073w(0); + wire_niO01ill_w_lg_w_lg_n01i110i17134w17136w(0) <= wire_niO01ill_w_lg_n01i110i17134w(0) AND wire_niO01ill_w_lg_n01i111O17135w(0); + wire_niO01ill_w_lg_w_lg_n01i110l17142w17143w(0) <= wire_niO01ill_w_lg_n01i110l17142w(0) AND wire_niO01ill_w_lg_n01i110i17134w(0); + wire_niO01ill_w_lg_w_lg_n01i110l17142w17560w(0) <= wire_niO01ill_w_lg_n01i110l17142w(0) AND n01i110i; + wire_niO01ill_w_lg_w_lg_n01iOiOO17845w17846w(0) <= wire_niO01ill_w_lg_n01iOiOO17845w(0) AND wire_niO01ill_w_lg_n01iOiOl17834w(0); + wire_niO01ill_w_lg_w_lg_n01O00ll21074w21076w(0) <= wire_niO01ill_w_lg_n01O00ll21074w(0) AND wire_niO01ill_w_lg_n01O00li21075w(0); + wire_niO01ill_w_lg_w_lg_n0i00l0i21086w21088w(0) <= wire_niO01ill_w_lg_n0i00l0i21086w(0) AND wire_niO01ill_w_lg_n0i00l1O21087w(0); + wire_niO01ill_w_lg_w_lg_n0iil11i14413w14415w(0) <= wire_niO01ill_w_lg_n0iil11i14413w(0) AND wire_niO01ill_w_lg_n0iiiOOO14414w(0); + wire_niO01ill_w_lg_w_lg_n0iil11l14421w14422w(0) <= wire_niO01ill_w_lg_n0iil11l14421w(0) AND wire_niO01ill_w_lg_n0iil11i14413w(0); + wire_niO01ill_w_lg_w_lg_n0iil11l14421w14839w(0) <= wire_niO01ill_w_lg_n0iil11l14421w(0) AND n0iil11i; + wire_niO01ill_w_lg_w_lg_n0iil1Oi14351w14353w(0) <= wire_niO01ill_w_lg_n0iil1Oi14351w(0) AND wire_niO01ill_w_lg_n0iil10O14352w(0); + wire_niO01ill_w_lg_w_lg_n0iliilO15124w15125w(0) <= wire_niO01ill_w_lg_n0iliilO15124w(0) AND wire_niO01ill_w_lg_n0iliill15113w(0); + wire_niO01ill_w_lg_w_lg_n0iOO0il21092w21094w(0) <= wire_niO01ill_w_lg_n0iOO0il21092w(0) AND wire_niO01ill_w_lg_n0iOO0ii21093w(0); + wire_niO01ill_w_lg_w_lg_n0l01l0l13506w13508w(0) <= wire_niO01ill_w_lg_n0l01l0l13506w(0) AND wire_niO01ill_w_lg_n0l01l0i13507w(0); + wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13515w(0) <= wire_niO01ill_w_lg_n0l01l0O13514w(0) AND wire_niO01ill_w_lg_n0l01l0l13506w(0); + wire_niO01ill_w_lg_w_lg_n0l01l0O13514w13932w(0) <= wire_niO01ill_w_lg_n0l01l0O13514w(0) AND n0l01l0l; + wire_niO01ill_w_lg_w_lg_n0l01O1l13444w13446w(0) <= wire_niO01ill_w_lg_n0l01O1l13444w(0) AND wire_niO01ill_w_lg_n0l01lli13445w(0); + wire_niO01ill_w_lg_w_lg_n0li101i14217w14218w(0) <= wire_niO01ill_w_lg_n0li101i14217w(0) AND wire_niO01ill_w_lg_n0li11OO14206w(0); + wire_niO01ill_w_lg_w_lg_n0ll0OlO21098w21100w(0) <= wire_niO01ill_w_lg_n0ll0OlO21098w(0) AND wire_niO01ill_w_lg_n0ll0Oll21099w(0); + wire_niO01ill_w_lg_w_lg_n0lOl0iO12599w12601w(0) <= wire_niO01ill_w_lg_n0lOl0iO12599w(0) AND wire_niO01ill_w_lg_n0lOl0il12600w(0); + wire_niO01ill_w_lg_w_lg_n0lOl0li12607w12608w(0) <= wire_niO01ill_w_lg_n0lOl0li12607w(0) AND wire_niO01ill_w_lg_n0lOl0iO12599w(0); + wire_niO01ill_w_lg_w_lg_n0lOl0li12607w13025w(0) <= wire_niO01ill_w_lg_n0lOl0li12607w(0) AND n0lOl0iO; + wire_niO01ill_w_lg_w_lg_n0lOli0O12537w12539w(0) <= wire_niO01ill_w_lg_n0lOli0O12537w(0) AND wire_niO01ill_w_lg_n0lOl0Ol12538w(0); + wire_niO01ill_w_lg_w_lg_n0O0Ol1i21104w21106w(0) <= wire_niO01ill_w_lg_n0O0Ol1i21104w(0) AND wire_niO01ill_w_lg_n0O0OiOO21105w(0); + wire_niO01ill_w_lg_w_lg_n0O1iO0l13310w13311w(0) <= wire_niO01ill_w_lg_n0O1iO0l13310w(0) AND wire_niO01ill_w_lg_n0O1iO0i13299w(0); + wire_niO01ill_w_lg_w_lg_n0Ol01li11625w11627w(0) <= wire_niO01ill_w_lg_n0Ol01li11625w(0) AND wire_niO01ill_w_lg_n0Ol011O11626w(0); + wire_niO01ill_w_lg_w_lg_n0Ol1OOi11688w11690w(0) <= wire_niO01ill_w_lg_n0Ol1OOi11688w(0) AND wire_niO01ill_w_lg_n0Ol1OlO11689w(0); + wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w11697w(0) <= wire_niO01ill_w_lg_n0Ol1OOl11696w(0) AND wire_niO01ill_w_lg_n0Ol1OOi11688w(0); + wire_niO01ill_w_lg_w_lg_n0Ol1OOl11696w12117w(0) <= wire_niO01ill_w_lg_n0Ol1OOl11696w(0) AND n0Ol1OOi; + wire_niO01ill_w_lg_w_lg_n0OO1iiO12403w12404w(0) <= wire_niO01ill_w_lg_n0OO1iiO12403w(0) AND wire_niO01ill_w_lg_n0OO1iil12392w(0); + wire_niO01ill_w_lg_w_lg_n1101l0i16090w26029w(0) <= wire_niO01ill_w_lg_n1101l0i16090w(0) AND nlOO01OiO; + wire_niO01ill_w_lg_w_lg_n1101l0i16090w27837w(0) <= wire_niO01ill_w_lg_n1101l0i16090w(0) AND nlOOOi1ii; + wire_niO01ill_w_lg_w_lg_n1101l0l15183w26033w(0) <= wire_niO01ill_w_lg_n1101l0l15183w(0) AND nlOO01Oli; + wire_niO01ill_w_lg_w_lg_n1101l0l15183w27841w(0) <= wire_niO01ill_w_lg_n1101l0l15183w(0) AND nlOOOi1il; + wire_niO01ill_w_lg_w_lg_n1101l0O14276w26037w(0) <= wire_niO01ill_w_lg_n1101l0O14276w(0) AND nlOO01Oll; + wire_niO01ill_w_lg_w_lg_n1101l0O14276w27845w(0) <= wire_niO01ill_w_lg_n1101l0O14276w(0) AND nlOOOi1iO; + wire_niO01ill_w_lg_w_lg_n1101l1l17904w26022w(0) <= wire_niO01ill_w_lg_n1101l1l17904w(0) AND nlOO01Oii; + wire_niO01ill_w_lg_w_lg_n1101l1l17904w27830w(0) <= wire_niO01ill_w_lg_n1101l1l17904w(0) AND nlOOOi10l; + wire_niO01ill_w_lg_w_lg_n1101l1O16997w26025w(0) <= wire_niO01ill_w_lg_n1101l1O16997w(0) AND nlOO01Oil; + wire_niO01ill_w_lg_w_lg_n1101l1O16997w27833w(0) <= wire_niO01ill_w_lg_n1101l1O16997w(0) AND nlOOOi10O; + wire_niO01ill_w_lg_w_lg_n1101lii13369w26041w(0) <= wire_niO01ill_w_lg_n1101lii13369w(0) AND nlOO01OlO; + wire_niO01ill_w_lg_w_lg_n1101lii13369w27849w(0) <= wire_niO01ill_w_lg_n1101lii13369w(0) AND nlOOOi1li; + wire_niO01ill_w_lg_w_lg_n1101lil12462w26045w(0) <= wire_niO01ill_w_lg_n1101lil12462w(0) AND nlOO01OOi; + wire_niO01ill_w_lg_w_lg_n1101lil12462w27853w(0) <= wire_niO01ill_w_lg_n1101lil12462w(0) AND nlOOOi1ll; + wire_niO01ill_w_lg_w_lg_n1101liO11541w26049w(0) <= wire_niO01ill_w_lg_n1101liO11541w(0) AND nlOO01OOl; + wire_niO01ill_w_lg_w_lg_n1101liO11541w27857w(0) <= wire_niO01ill_w_lg_n1101liO11541w(0) AND nlOOOi1lO; + wire_niO01ill_w_lg_w_lg_n11i111O19840w19850w(0) <= wire_niO01ill_w_lg_n11i111O19840w(0) AND wire_niO01ill_w_lg_n11i111l19781w(0); + wire_niO01ill_w_lg_w_lg_n11i111O19840w19841w(0) <= wire_niO01ill_w_lg_n11i111O19840w(0) AND n11i111l; + wire_niO01ill_w_lg_w_lg_n11li10l21153w23483w(0) <= wire_niO01ill_w_lg_n11li10l21153w(0) AND niOl01lii; + wire_niO01ill_w_lg_w_lg_n11li10O21143w21144w(0) <= wire_niO01ill_w_lg_n11li10O21143w(0) AND niOli1iOl; + wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0) <= wire_niO01ill_w_lg_n11li1li9830w(0) AND n11li1iO; + wire_niO01ill_w_lg_w_lg_n11O0iOi21061w21062w(0) <= wire_niO01ill_w_lg_n11O0iOi21061w(0) AND niOl0i01O; + wire_niO01ill_w_lg_w_lg_n11O0lii19984w19985w(0) <= wire_niO01ill_w_lg_n11O0lii19984w(0) AND niOli1l0i; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24138w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1ll0l; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24134w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1llii; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24130w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1lliO; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24126w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1llll; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24122w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1llOi; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24118w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1llOO; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24109w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1lO0i; + wire_niO01ill_w_lg_w_lg_n11O0llO24108w24114w(0) <= wire_niO01ill_w_lg_n11O0llO24108w(0) AND niOl1lO1l; + wire_niO01ill_w_lg_w_lg_n11Oi1ll23889w23890w(0) <= wire_niO01ill_w_lg_n11Oi1ll23889w(0) AND n11O0lOi; + wire_niO01ill_w_lg_w_lg_n1iOl0Oi25180w25182w(0) <= wire_niO01ill_w_lg_n1iOl0Oi25180w(0) AND wire_niO01ill_w_lg_n1iOl0il25181w(0); + wire_niO01ill_w_lg_w_lg_n1l0010O11542w11544w(0) <= wire_niO01ill_w_lg_n1l0010O11542w(0) AND wire_niO01ill_w_lg_n1l0010l11543w(0); + wire_niO01ill_w_lg_w_lg_n1l0010O11542w11547w(0) <= wire_niO01ill_w_lg_n1l0010O11542w(0) AND n1l0010l; + wire_niO01ill_w_lg_w_lg_n1l0011O19569w19570w(0) <= wire_niO01ill_w_lg_n1l0011O19569w(0) AND n1l0011l; + wire_niO01ill_w_lg_w_lg_n1l001OO19872w19873w(0) <= wire_niO01ill_w_lg_n1l001OO19872w(0) AND n1l001Ol; + wire_niO01ill_w_lg_w_lg_n1lill0O19911w19913w(0) <= wire_niO01ill_w_lg_n1lill0O19911w(0) AND wire_niO01ill_w_lg_n1lill0l19912w(0); + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17912w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlil1ll; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17907w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlil1Oi; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17005w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOliO0li; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17000w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOliO0lO; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15191w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOll0lil; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15186w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOll0lli; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16098w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOll1iiO; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16093w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOll1ill; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14284w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlliOii; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14279w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlliOiO; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13377w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOllO10O; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13372w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOllO1il; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11557w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlO0i0l; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11552w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlO0iii; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12470w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlO100l; + wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12465w(0) <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOlO10ii; + wire_niO01ill_w_lg_w_lg_n1Oi011O21063w21065w(0) <= wire_niO01ill_w_lg_n1Oi011O21063w(0) AND wire_niO01ill_w_lg_n1Oi011l21064w(0); + wire_niO01ill_w_lg_w_lg_n1Oli0OO18041w18043w(0) <= wire_niO01ill_w_lg_n1Oli0OO18041w(0) AND wire_niO01ill_w_lg_n1Oli0Ol18042w(0); + wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18050w(0) <= wire_niO01ill_w_lg_n1Olii1i18049w(0) AND wire_niO01ill_w_lg_n1Oli0OO18041w(0); + wire_niO01ill_w_lg_w_lg_n1Olii1i18049w18467w(0) <= wire_niO01ill_w_lg_n1Olii1i18049w(0) AND n1Oli0OO; + wire_niO01ill_w_lg_w_lg_n1OliilO17979w17981w(0) <= wire_niO01ill_w_lg_n1OliilO17979w(0) AND wire_niO01ill_w_lg_n1Olii0l17980w(0); + wire_niO01ill_w_lg_w_lg_n1OO0Oll18752w18753w(0) <= wire_niO01ill_w_lg_n1OO0Oll18752w(0) AND wire_niO01ill_w_lg_n1OO0Oli18741w(0); + wire_niO01ill_w_lg_w_lg_ni00ll1i10876w10912w(0) <= wire_niO01ill_w_lg_ni00ll1i10876w(0) AND ni00liOO; + wire_niO01ill_w_lg_w_lg_ni01lOiO10957w10993w(0) <= wire_niO01ill_w_lg_ni01lOiO10957w(0) AND ni01lOil; + wire_niO01ill_w_lg_w_lg_ni0i0i0l10658w10659w(0) <= wire_niO01ill_w_lg_ni0i0i0l10658w(0) AND ni0i0i0i; + wire_niO01ill_w_lg_w_lg_ni101i0i11362w11398w(0) <= wire_niO01ill_w_lg_ni101i0i11362w(0) AND ni101i1O; + wire_niO01ill_w_lg_w_lg_ni111llO11443w11479w(0) <= wire_niO01ill_w_lg_ni111llO11443w(0) AND ni111lll; + wire_niO01ill_w_lg_w_lg_ni1i11ll11281w11317w(0) <= wire_niO01ill_w_lg_ni1i11ll11281w(0) AND ni1i11li; + wire_niO01ill_w_lg_w_lg_ni1iOO1O11200w11236w(0) <= wire_niO01ill_w_lg_ni1iOO1O11200w(0) AND ni1iOO1l; + wire_niO01ill_w_lg_w_lg_ni1lOili11119w11155w(0) <= wire_niO01ill_w_lg_ni1lOili11119w(0) AND ni1lOiiO; + wire_niO01ill_w_lg_w_lg_ni1OO01l11038w11074w(0) <= wire_niO01ill_w_lg_ni1OO01l11038w(0) AND ni1OO01i; + wire_niO01ill_w_lg_w_lg_niiii0iO10498w10499w(0) <= wire_niO01ill_w_lg_niiii0iO10498w(0) AND wire_niO01ill_w_lg_niiii0il10487w(0); + wire_niO01ill_w_lg_w_lg_niiii0iO10498w10523w(0) <= wire_niO01ill_w_lg_niiii0iO10498w(0) AND niiii0il; + wire_niO01ill_w_lg_w_lg_niiii10O10598w10599w(0) <= wire_niO01ill_w_lg_niiii10O10598w(0) AND wire_niO01ill_w_lg_niiii10l10587w(0); + wire_niO01ill_w_lg_w_lg_niiii10O10598w10623w(0) <= wire_niO01ill_w_lg_niiii10O10598w(0) AND niiii10l; + wire_niO01ill_w_lg_w_lg_niiii1OO10548w10549w(0) <= wire_niO01ill_w_lg_niiii1OO10548w(0) AND wire_niO01ill_w_lg_niiii1Ol10537w(0); + wire_niO01ill_w_lg_w_lg_niiii1OO10548w10573w(0) <= wire_niO01ill_w_lg_niiii1OO10548w(0) AND niiii1Ol; + wire_niO01ill_w_lg_w_lg_niiiii1O10448w10449w(0) <= wire_niO01ill_w_lg_niiiii1O10448w(0) AND wire_niO01ill_w_lg_niiiii1l10437w(0); + wire_niO01ill_w_lg_w_lg_niiiii1O10448w10473w(0) <= wire_niO01ill_w_lg_niiiii1O10448w(0) AND niiiii1l; + wire_niO01ill_w_lg_w_lg_niiiiilO10398w10399w(0) <= wire_niO01ill_w_lg_niiiiilO10398w(0) AND wire_niO01ill_w_lg_niiiiill10387w(0); + wire_niO01ill_w_lg_w_lg_niiiiilO10398w10423w(0) <= wire_niO01ill_w_lg_niiiiilO10398w(0) AND niiiiill; + wire_niO01ill_w_lg_w_lg_niiiil0O10348w10349w(0) <= wire_niO01ill_w_lg_niiiil0O10348w(0) AND wire_niO01ill_w_lg_niiiil0l10337w(0); + wire_niO01ill_w_lg_w_lg_niiiil0O10348w10373w(0) <= wire_niO01ill_w_lg_niiiil0O10348w(0) AND niiiil0l; + wire_niO01ill_w_lg_w_lg_niiiilOO10298w10299w(0) <= wire_niO01ill_w_lg_niiiilOO10298w(0) AND wire_niO01ill_w_lg_niiiilOl10287w(0); + wire_niO01ill_w_lg_w_lg_niiiilOO10298w10323w(0) <= wire_niO01ill_w_lg_niiiilOO10298w(0) AND niiiilOl; + wire_niO01ill_w_lg_w_lg_niiiiOiO10248w10249w(0) <= wire_niO01ill_w_lg_niiiiOiO10248w(0) AND wire_niO01ill_w_lg_niiiiOil10237w(0); + wire_niO01ill_w_lg_w_lg_niiiiOiO10248w10273w(0) <= wire_niO01ill_w_lg_niiiiOiO10248w(0) AND niiiiOil; + wire_niO01ill_w_lg_w_lg_niOO0O0OO19990w19991w(0) <= wire_niO01ill_w_lg_niOO0O0OO19990w(0) AND niOli1l0i; + wire_niO01ill_w_lg_w_lg_nlOlOiliO21217w23459w(0) <= wire_niO01ill_w_lg_nlOlOiliO21217w(0) AND n1lillil; + wire_niO01ill_w_lg_w_lg_nlOO0iilO20976w20977w(0) <= wire_niO01ill_w_lg_nlOO0iilO20976w(0) AND nlOO0ii1i; + wire_niO01ill_w_lg_w_lg_nlOO1O1Ol24778w24780w(0) <= wire_niO01ill_w_lg_nlOO1O1Ol24778w(0) AND wire_w_lg_niOl1Olli24779w(0); + wire_niO01ill_w_lg_n000i00i16928w(0) <= n000i00i AND wire_niO01ill_w_lg_n000i01O16927w(0); + wire_niO01ill_w_lg_n0010ilO16620w(0) <= n0010ilO AND wire_w_lg_w_lg_niOll110l16345w16619w(0); + wire_niO01ill_w_lg_n001ilil16666w(0) <= n001ilil AND wire_niO01ill_w_lg_n001ilii16228w(0); + wire_niO01ill_w_lg_n001iliO16660w(0) <= n001iliO AND wire_niO01ill_w_lg_n001ilil16227w(0); + wire_niO01ill_w_lg_n00lO01i15713w(0) <= n00lO01i AND wire_w_lg_w_lg_niOll000i15438w15712w(0); + wire_niO01ill_w_lg_n00O10lO15759w(0) <= n00O10lO AND wire_niO01ill_w_lg_n00O10ll15321w(0); + wire_niO01ill_w_lg_n00O10Oi15753w(0) <= n00O10Oi AND wire_niO01ill_w_lg_n00O10lO15320w(0); + wire_niO01ill_w_lg_n00OOOil16021w(0) <= n00OOOil AND wire_niO01ill_w_lg_n00OOOii16020w(0); + wire_niO01ill_w_lg_n010lOil17527w(0) <= n010lOil AND wire_w_lg_w_lg_niOlilO0O17252w17526w(0); + wire_niO01ill_w_lg_n01i110i17573w(0) <= n01i110i AND wire_niO01ill_w_lg_n01i111O17135w(0); + wire_niO01ill_w_lg_n01i110l17567w(0) <= n01i110l AND wire_niO01ill_w_lg_n01i110i17134w(0); + wire_niO01ill_w_lg_n01iOiOO17835w(0) <= n01iOiOO AND wire_niO01ill_w_lg_n01iOiOl17834w(0); + wire_niO01ill_w_lg_n0ii0O0l14806w(0) <= n0ii0O0l AND wire_w_lg_w_lg_niOllii1O14531w14805w(0); + wire_niO01ill_w_lg_n0iil11i14852w(0) <= n0iil11i AND wire_niO01ill_w_lg_n0iiiOOO14414w(0); + wire_niO01ill_w_lg_n0iil11l14846w(0) <= n0iil11l AND wire_niO01ill_w_lg_n0iil11i14413w(0); + wire_niO01ill_w_lg_n0iliilO15114w(0) <= n0iliilO AND wire_niO01ill_w_lg_n0iliill15113w(0); + wire_niO01ill_w_lg_n0l01l0l13945w(0) <= n0l01l0l AND wire_niO01ill_w_lg_n0l01l0i13507w(0); + wire_niO01ill_w_lg_n0l01l0O13939w(0) <= n0l01l0O AND wire_niO01ill_w_lg_n0l01l0l13506w(0); + wire_niO01ill_w_lg_n0l1OiiO13899w(0) <= n0l1OiiO AND wire_w_lg_w_lg_niOllll1l13624w13898w(0); + wire_niO01ill_w_lg_n0li101i14207w(0) <= n0li101i AND wire_niO01ill_w_lg_n0li11OO14206w(0); + wire_niO01ill_w_lg_n0lOi1Oi12992w(0) <= n0lOi1Oi AND wire_w_lg_w_lg_niOllOO1i12717w12991w(0); + wire_niO01ill_w_lg_n0lOl0iO13038w(0) <= n0lOl0iO AND wire_niO01ill_w_lg_n0lOl0il12600w(0); + wire_niO01ill_w_lg_n0lOl0li13032w(0) <= n0lOl0li AND wire_niO01ill_w_lg_n0lOl0iO12599w(0); + wire_niO01ill_w_lg_n0O1iO0l13300w(0) <= n0O1iO0l AND wire_niO01ill_w_lg_n0O1iO0i13299w(0); + wire_niO01ill_w_lg_n0OiOO1l12081w(0) <= n0OiOO1l AND wire_w_lg_w_lg_niOlO011i11806w12080w(0); + wire_niO01ill_w_lg_n0Ol1OOi12130w(0) <= n0Ol1OOi AND wire_niO01ill_w_lg_n0Ol1OlO11689w(0); + wire_niO01ill_w_lg_n0Ol1OOl12124w(0) <= n0Ol1OOl AND wire_niO01ill_w_lg_n0Ol1OOi11688w(0); + wire_niO01ill_w_lg_n0OO1iiO12393w(0) <= n0OO1iiO AND wire_niO01ill_w_lg_n0OO1iil12392w(0); + wire_niO01ill_w_lg_n1101l0i21078w(0) <= n1101l0i AND wire_niO01ill_w_lg_w_lg_w_lg_n01O00ll21074w21076w21077w(0); + wire_niO01ill_w_lg_n1101l0l21084w(0) <= n1101l0l AND wire_niO01ill_w_lg_w_lg_w_lg_n00ilOOO21080w21082w21083w(0); + wire_niO01ill_w_lg_n1101l0O21090w(0) <= n1101l0O AND wire_niO01ill_w_lg_w_lg_w_lg_n0i00l0i21086w21088w21089w(0); + wire_niO01ill_w_lg_n1101l1l21067w(0) <= n1101l1l AND wire_niO01ill_w_lg_w_lg_w_lg_n1Oi011O21063w21065w21066w(0); + wire_niO01ill_w_lg_n1101l1O21072w(0) <= n1101l1O AND wire_niO01ill_w_lg_w_lg_w_lg_n011llii21068w21070w21071w(0); + wire_niO01ill_w_lg_n1101lii21096w(0) <= n1101lii AND wire_niO01ill_w_lg_w_lg_w_lg_n0iOO0il21092w21094w21095w(0); + wire_niO01ill_w_lg_n1101lil21102w(0) <= n1101lil AND wire_niO01ill_w_lg_w_lg_w_lg_n0ll0OlO21098w21100w21101w(0); + wire_niO01ill_w_lg_n1101liO21108w(0) <= n1101liO AND wire_niO01ill_w_lg_w_lg_w_lg_n0O0Ol1i21104w21106w21107w(0); + wire_niO01ill_w_lg_n1101liO26878w(0) <= n1101liO AND n1101lil; + wire_niO01ill_w_lg_n1110Oii21207w(0) <= n1110Oii AND wire_w_lg_niOl0iO0O20959w(0); + wire_niO01ill_w_lg_n1110OOO24680w(0) <= n1110OOO AND wire_niO01ill_w_lg_nlOOOi10i24679w(0); + wire_niO01ill_w_lg_n11i111O19846w(0) <= n11i111O AND wire_niO01ill_w_lg_n11i111l19781w(0); + wire_niO01ill_w_lg_n11i111O19857w(0) <= n11i111O AND n11i111l; + wire_niO01ill_w_lg_n11li10i21129w(0) <= n11li10i AND wire_w_lg_niOl0l0li20891w(0); + wire_niO01ill_w_lg_n11li1il21048w(0) <= n11li1il AND wire_w_lg_niOl0l0li20891w(0); + wire_niO01ill_w_lg_n11O0l1O23854w(0) <= n11O0l1O AND wire_w_lg_niOl1OliO23853w(0); + wire_niO01ill_w_lg_n11O0llO23840w(0) <= n11O0llO AND wire_w_lg_niOl1OOli23839w(0); + wire_niO01ill_w_lg_n11O1O1O20986w(0) <= n11O1O1O AND niOl0ilii; + wire_niO01ill_w_lg_n1il11ll21199w(0) <= n1il11ll AND wire_niO01ill_w_lg_n1110Oii21198w(0); + wire_niO01ill_w_lg_n1iO0l0O20892w(0) <= n1iO0l0O AND wire_w_lg_niOl0l0li20891w(0); + wire_niO01ill_w_lg_n1iOl10i25220w(0) <= n1iOl10i AND wire_n1l11iOO_w_lg_w_lg_dataout25218w25219w(0); + wire_niO01ill_w_lg_n1l000Oi19865w(0) <= n1l000Oi AND wire_niO01ill_w_lg_n1l000lO19828w(0); + wire_niO01ill_w_lg_n1l001OO19894w(0) <= n1l001OO AND wire_niO01ill_w_lg_n1l001Ol19893w(0); + wire_niO01ill_w_lg_n1l001OO19884w(0) <= n1l001OO AND n1l001Ol; + wire_niO01ill_w_lg_n1l00i1O19905w(0) <= n1l00i1O AND wire_niO01ill_w_lg_n1l00i1l19819w(0); + wire_niO01ill_w_lg_n1l00i1O19783w(0) <= n1l00i1O AND n1l00i1l; + wire_niO01ill_w_lg_n1l1OlOi18938w(0) <= n1l1OlOi AND wire_nlOiOi1ll_w_lg_w_lg_dataout18936w18937w(0); + wire_niO01ill_w_lg_n1lill0O19918w(0) <= n1lill0O AND wire_niO01ill_w_lg_n1lill0l19912w(0); + wire_niO01ill_w_lg_n1lilO0l19585w(0) <= n1lilO0l AND wire_niO01iOi_w19584w(0); + wire_niO01ill_w_lg_n1Ol000i18434w(0) <= n1Ol000i AND wire_w_lg_w_lg_niOliilii18159w18433w(0); + wire_niO01ill_w_lg_n1Oli0OO18480w(0) <= n1Oli0OO AND wire_niO01ill_w_lg_n1Oli0Ol18042w(0); + wire_niO01ill_w_lg_n1Olii1i18474w(0) <= n1Olii1i AND wire_niO01ill_w_lg_n1Oli0OO18041w(0); + wire_niO01ill_w_lg_n1OO0Oll18742w(0) <= n1OO0Oll AND wire_niO01ill_w_lg_n1OO0Oli18741w(0); + wire_niO01ill_w_lg_ni00ll1i10915w(0) <= ni00ll1i AND wire_niO01ill_w_lg_ni00liOO10877w(0); + wire_niO01ill_w_lg_ni01lOiO10996w(0) <= ni01lOiO AND wire_niO01ill_w_lg_ni01lOil10958w(0); + wire_niO01ill_w_lg_ni0i0i0l10812w(0) <= ni0i0i0l AND wire_niO01ill_w_lg_ni0i0i0i10663w(0); + wire_niO01ill_w_lg_ni101i0i11401w(0) <= ni101i0i AND wire_niO01ill_w_lg_ni101i1O11363w(0); + wire_niO01ill_w_lg_ni11100O10647w(0) <= ni11100O AND wire_niO01ill_w_lg_ni11100l10646w(0); + wire_niO01ill_w_lg_ni11100O10637w(0) <= ni11100O AND ni11100l; + wire_niO01ill_w_lg_ni111llO11482w(0) <= ni111llO AND wire_niO01ill_w_lg_ni111lll11444w(0); + wire_niO01ill_w_lg_ni1i11ll11320w(0) <= ni1i11ll AND wire_niO01ill_w_lg_ni1i11li11282w(0); + wire_niO01ill_w_lg_ni1iOO1O11239w(0) <= ni1iOO1O AND wire_niO01ill_w_lg_ni1iOO1l11201w(0); + wire_niO01ill_w_lg_ni1lOili11158w(0) <= ni1lOili AND wire_niO01ill_w_lg_ni1lOiiO11120w(0); + wire_niO01ill_w_lg_ni1OO01l11077w(0) <= ni1OO01l AND wire_niO01ill_w_lg_ni1OO01i11039w(0); + wire_niO01ill_w_lg_niiii0iO10488w(0) <= niiii0iO AND wire_niO01ill_w_lg_niiii0il10487w(0); + wire_niO01ill_w_lg_niiii0iO10508w(0) <= niiii0iO AND niiii0il; + wire_niO01ill_w_lg_niiii10O10588w(0) <= niiii10O AND wire_niO01ill_w_lg_niiii10l10587w(0); + wire_niO01ill_w_lg_niiii10O10608w(0) <= niiii10O AND niiii10l; + wire_niO01ill_w_lg_niiii1OO10538w(0) <= niiii1OO AND wire_niO01ill_w_lg_niiii1Ol10537w(0); + wire_niO01ill_w_lg_niiii1OO10558w(0) <= niiii1OO AND niiii1Ol; + wire_niO01ill_w_lg_niiiii1O10438w(0) <= niiiii1O AND wire_niO01ill_w_lg_niiiii1l10437w(0); + wire_niO01ill_w_lg_niiiii1O10458w(0) <= niiiii1O AND niiiii1l; + wire_niO01ill_w_lg_niiiiilO10388w(0) <= niiiiilO AND wire_niO01ill_w_lg_niiiiill10387w(0); + wire_niO01ill_w_lg_niiiiilO10408w(0) <= niiiiilO AND niiiiill; + wire_niO01ill_w_lg_niiiil0O10338w(0) <= niiiil0O AND wire_niO01ill_w_lg_niiiil0l10337w(0); + wire_niO01ill_w_lg_niiiil0O10358w(0) <= niiiil0O AND niiiil0l; + wire_niO01ill_w_lg_niiiilOO10288w(0) <= niiiilOO AND wire_niO01ill_w_lg_niiiilOl10287w(0); + wire_niO01ill_w_lg_niiiilOO10308w(0) <= niiiilOO AND niiiilOl; + wire_niO01ill_w_lg_niiiiOiO10238w(0) <= niiiiOiO AND wire_niO01ill_w_lg_niiiiOil10237w(0); + wire_niO01ill_w_lg_niiiiOiO10258w(0) <= niiiiOiO AND niiiiOil; + wire_niO01ill_w_lg_niOO0O0OO43259w(0) <= niOO0O0OO AND wire_nlill0Oll_w_lg_nlilillil43258w(0); + wire_niO01ill_w_lg_niOO0Oi1l20951w(0) <= niOO0Oi1l AND wire_w_lg_niOl0l1OO20936w(0); + wire_niO01ill_w_lg_nlOiO10ii28254w(0) <= nlOiO10ii AND nlOiO100O; + wire_niO01ill_w_lg_nlOliO00i25139w(0) <= nlOliO00i AND wire_niO01iOi_w25138w(0); + wire_niO01ill_w_lg_nlOliO01i25119w(0) <= nlOliO01i AND wire_niO01iOi_w25118w(0); + wire_niO01ill_w_lg_nlOliO0ii25129w(0) <= nlOliO0ii AND wire_niO01iOi_w25128w(0); + wire_niO01ill_w_lg_nlOliO10i25079w(0) <= nlOliO10i AND wire_niO01iOi_w25078w(0); + wire_niO01ill_w_lg_nlOliO11i25069w(0) <= nlOliO11i AND wire_niO01iOi_w25068w(0); + wire_niO01ill_w_lg_nlOliO1ii25089w(0) <= nlOliO1ii AND wire_niO01iOi_w25088w(0); + wire_niO01ill_w_lg_nlOliO1li25099w(0) <= nlOliO1li AND wire_niO01iOi_w25098w(0); + wire_niO01ill_w_lg_nlOliO1Oi25109w(0) <= nlOliO1Oi AND wire_niO01iOi_w25108w(0); + wire_niO01ill_w_lg_nlOll0O0O24678w(0) <= nlOll0O0O AND niOl1il1l; + wire_niO01ill_w_lg_nlOlOilOl21225w(0) <= nlOlOilOl AND wire_nlOlO0Oii_w_lg_dataout21224w(0); + wire_niO01ill_w_lg_nlOOOi10i24752w(0) <= nlOOOi10i AND wire_nlOii0l0O_w_lg_w_lg_dataout21190w24751w(0); + wire_niO01ill_w_lg_nlOOOi10i24679w(0) <= nlOOOi10i AND wire_niO01ill_w_lg_nlOll0O0O24678w(0); + wire_niO01ill_w_lg_nlOOOl01i25090w(0) <= nlOOOl01i AND wire_niO01ill_w_lg_nlOliO1ii25089w(0); + wire_niO01ill_w_lg_nlOOOl01l25080w(0) <= nlOOOl01l AND wire_niO01ill_w_lg_nlOliO10i25079w(0); + wire_niO01ill_w_lg_nlOOOl01O25070w(0) <= nlOOOl01O AND wire_niO01ill_w_lg_nlOliO11i25069w(0); + wire_niO01ill_w_lg_nlOOOl1ll25130w(0) <= nlOOOl1ll AND wire_niO01ill_w_lg_nlOliO0ii25129w(0); + wire_niO01ill_w_lg_nlOOOl1lO25140w(0) <= nlOOOl1lO AND wire_niO01ill_w_lg_nlOliO00i25139w(0); + wire_niO01ill_w_lg_nlOOOl1Oi25120w(0) <= nlOOOl1Oi AND wire_niO01ill_w_lg_nlOliO01i25119w(0); + wire_niO01ill_w_lg_nlOOOl1Ol25110w(0) <= nlOOOl1Ol AND wire_niO01ill_w_lg_nlOliO1Oi25109w(0); + wire_niO01ill_w_lg_nlOOOl1OO25100w(0) <= nlOOOl1OO AND wire_niO01ill_w_lg_nlOliO1li25099w(0); + wire_niO01ill_w_lg_w_lg_n00l0lOl15587w15588w(0) <= NOT wire_niO01ill_w_lg_n00l0lOl15587w(0); + wire_niO01ill_w_lg_w_lg_n00l0Oil15591w15592w(0) <= NOT wire_niO01ill_w_lg_n00l0Oil15591w(0); + wire_niO01ill_w_lg_w_lg_n0100i0O17401w17402w(0) <= NOT wire_niO01ill_w_lg_n0100i0O17401w(0); + wire_niO01ill_w_lg_w_lg_n0100iOO17405w17406w(0) <= NOT wire_niO01ill_w_lg_n0100iOO17405w(0); + wire_niO01ill_w_lg_w_lg_n01OO00i16498w16499w(0) <= NOT wire_niO01ill_w_lg_n01OO00i16498w(0); + wire_niO01ill_w_lg_w_lg_n01OO1li16494w16495w(0) <= NOT wire_niO01ill_w_lg_n01OO1li16494w(0); + wire_niO01ill_w_lg_w_lg_n0i0Oi1O14680w14681w(0) <= NOT wire_niO01ill_w_lg_n0i0Oi1O14680w(0); + wire_niO01ill_w_lg_w_lg_n0i0OilO14684w14685w(0) <= NOT wire_niO01ill_w_lg_n0i0OilO14684w(0); + wire_niO01ill_w_lg_w_lg_n0l1i01i13777w13778w(0) <= NOT wire_niO01ill_w_lg_n0l1i01i13777w(0); + wire_niO01ill_w_lg_w_lg_n0l1i1ii13773w13774w(0) <= NOT wire_niO01ill_w_lg_n0l1i1ii13773w(0); + wire_niO01ill_w_lg_w_lg_n0llOlll12866w12867w(0) <= NOT wire_niO01ill_w_lg_n0llOlll12866w(0); + wire_niO01ill_w_lg_w_lg_n0llOO0l12870w12871w(0) <= NOT wire_niO01ill_w_lg_n0llOO0l12870w(0); + wire_niO01ill_w_lg_w_lg_n0Oii0OO11955w11956w(0) <= NOT wire_niO01ill_w_lg_n0Oii0OO11955w(0); + wire_niO01ill_w_lg_w_lg_n0OiiiiO11959w11960w(0) <= NOT wire_niO01ill_w_lg_n0OiiiiO11959w(0); + wire_niO01ill_w_lg_w_lg_n1OilO1l18308w18309w(0) <= NOT wire_niO01ill_w_lg_n1OilO1l18308w(0); + wire_niO01ill_w_lg_w_lg_n1OilOll18312w18313w(0) <= NOT wire_niO01ill_w_lg_n1OilOll18312w(0); + wire_niO01ill_w_lg_w_lg_nlOliO00i25133w25134w(0) <= NOT wire_niO01ill_w_lg_nlOliO00i25133w(0); + wire_niO01ill_w_lg_w_lg_nlOliO00l25136w25137w(0) <= NOT wire_niO01ill_w_lg_nlOliO00l25136w(0); + wire_niO01ill_w_lg_w_lg_nlOliO01i25113w25114w(0) <= NOT wire_niO01ill_w_lg_nlOliO01i25113w(0); + wire_niO01ill_w_lg_w_lg_nlOliO01l25116w25117w(0) <= NOT wire_niO01ill_w_lg_nlOliO01l25116w(0); + wire_niO01ill_w_lg_w_lg_nlOliO0ii25123w25124w(0) <= NOT wire_niO01ill_w_lg_nlOliO0ii25123w(0); + wire_niO01ill_w_lg_w_lg_nlOliO0il25126w25127w(0) <= NOT wire_niO01ill_w_lg_nlOliO0il25126w(0); + wire_niO01ill_w_lg_w_lg_nlOliO10i25073w25074w(0) <= NOT wire_niO01ill_w_lg_nlOliO10i25073w(0); + wire_niO01ill_w_lg_w_lg_nlOliO10l25076w25077w(0) <= NOT wire_niO01ill_w_lg_nlOliO10l25076w(0); + wire_niO01ill_w_lg_w_lg_nlOliO11i25063w25064w(0) <= NOT wire_niO01ill_w_lg_nlOliO11i25063w(0); + wire_niO01ill_w_lg_w_lg_nlOliO11l25066w25067w(0) <= NOT wire_niO01ill_w_lg_nlOliO11l25066w(0); + wire_niO01ill_w_lg_w_lg_nlOliO1ii25083w25084w(0) <= NOT wire_niO01ill_w_lg_nlOliO1ii25083w(0); + wire_niO01ill_w_lg_w_lg_nlOliO1il25086w25087w(0) <= NOT wire_niO01ill_w_lg_nlOliO1il25086w(0); + wire_niO01ill_w_lg_w_lg_nlOliO1li25093w25094w(0) <= NOT wire_niO01ill_w_lg_nlOliO1li25093w(0); + wire_niO01ill_w_lg_w_lg_nlOliO1ll25096w25097w(0) <= NOT wire_niO01ill_w_lg_nlOliO1ll25096w(0); + wire_niO01ill_w_lg_w_lg_nlOliO1Oi25103w25104w(0) <= NOT wire_niO01ill_w_lg_nlOliO1Oi25103w(0); + wire_niO01ill_w_lg_w_lg_nlOliO1Ol25106w25107w(0) <= NOT wire_niO01ill_w_lg_nlOliO1Ol25106w(0); + wire_niO01ill_w_lg_n000i00i16938w(0) <= NOT n000i00i; + wire_niO01ill_w_lg_n000i01l16940w(0) <= NOT n000i01l; + wire_niO01ill_w_lg_n000i01O16927w(0) <= NOT n000i01O; + wire_niO01ill_w_lg_n000i10l16631w(0) <= NOT n000i10l; + wire_niO01ill_w_lg_n000i10O16096w(0) <= NOT n000i10O; + wire_niO01ill_w_lg_n000i1ii16175w(0) <= NOT n000i1ii; + wire_niO01ill_w_lg_n000i1il16104w(0) <= NOT n000i1il; + wire_niO01ill_w_lg_n000i1lO16935w(0) <= NOT n000i1lO; + wire_niO01ill_w_lg_n000i1Oi16933w(0) <= NOT n000i1Oi; + wire_niO01ill_w_lg_n00100iO16371w(0) <= NOT n00100iO; + wire_niO01ill_w_lg_n0010iOl16382w(0) <= NOT n0010iOl; + wire_niO01ill_w_lg_n0010iOO16387w(0) <= NOT n0010iOO; + wire_niO01ill_w_lg_n001il0O16230w(0) <= NOT n001il0O; + wire_niO01ill_w_lg_n001ilii16228w(0) <= NOT n001ilii; + wire_niO01ill_w_lg_n001ilil16227w(0) <= NOT n001ilil; + wire_niO01ill_w_lg_n001iliO16235w(0) <= NOT n001iliO; + wire_niO01ill_w_lg_n001ilOi16166w(0) <= NOT n001ilOi; + wire_niO01ill_w_lg_n001ilOO16173w(0) <= NOT n001ilOO; + wire_niO01ill_w_lg_n001iO0l16165w(0) <= NOT n001iO0l; + wire_niO01ill_w_lg_n00iiiOi15387w(0) <= NOT n00iiiOi; + wire_niO01ill_w_lg_n00iilii15716w(0) <= NOT n00iilii; + wire_niO01ill_w_lg_n00iilil15947w(0) <= NOT n00iilil; + wire_niO01ill_w_lg_n00iiliO15946w(0) <= NOT n00iiliO; + wire_niO01ill_w_lg_n00il1li26362w(0) <= NOT n00il1li; + wire_niO01ill_w_lg_n00ill1O27781w(0) <= NOT n00ill1O; + wire_niO01ill_w_lg_n00illOi25306w(0) <= NOT n00illOi; + wire_niO01ill_w_lg_n00illOl27932w(0) <= NOT n00illOl; + wire_niO01ill_w_lg_n00ilOOl21081w(0) <= NOT n00ilOOl; + wire_niO01ill_w_lg_n00ilOOO21080w(0) <= NOT n00ilOOO; + wire_niO01ill_w_lg_n00iO10i27391w(0) <= NOT n00iO10i; + wire_niO01ill_w_lg_n00iO10l27389w(0) <= NOT n00iO10l; + wire_niO01ill_w_lg_n00iO11i27700w(0) <= NOT n00iO11i; + wire_niO01ill_w_lg_n00iO11l27698w(0) <= NOT n00iO11l; + wire_niO01ill_w_lg_n00iO11O27696w(0) <= NOT n00iO11O; + wire_niO01ill_w_lg_n00iO1OO26068w(0) <= NOT n00iO1OO; + wire_niO01ill_w_lg_n00l0i0l15572w(0) <= NOT n00l0i0l; + wire_niO01ill_w_lg_n00llOOi15464w(0) <= NOT n00llOOi; + wire_niO01ill_w_lg_n00lO00i15480w(0) <= NOT n00lO00i; + wire_niO01ill_w_lg_n00lO01O15475w(0) <= NOT n00lO01O; + wire_niO01ill_w_lg_n00O10li15323w(0) <= NOT n00O10li; + wire_niO01ill_w_lg_n00O10ll15321w(0) <= NOT n00O10ll; + wire_niO01ill_w_lg_n00O10lO15320w(0) <= NOT n00O10lO; + wire_niO01ill_w_lg_n00O10Oi15328w(0) <= NOT n00O10Oi; + wire_niO01ill_w_lg_n00O1i0i15266w(0) <= NOT n00O1i0i; + wire_niO01ill_w_lg_n00O1i1l15259w(0) <= NOT n00O1i1l; + wire_niO01ill_w_lg_n00O1iiO15258w(0) <= NOT n00O1iiO; + wire_niO01ill_w_lg_n00OOliO15724w(0) <= NOT n00OOliO; + wire_niO01ill_w_lg_n00OOlli15189w(0) <= NOT n00OOlli; + wire_niO01ill_w_lg_n00OOlll15268w(0) <= NOT n00OOlll; + wire_niO01ill_w_lg_n00OOllO15197w(0) <= NOT n00OOllO; + wire_niO01ill_w_lg_n00OOO0O16033w(0) <= NOT n00OOO0O; + wire_niO01ill_w_lg_n00OOO1i16028w(0) <= NOT n00OOO1i; + wire_niO01ill_w_lg_n00OOO1l16026w(0) <= NOT n00OOO1l; + wire_niO01ill_w_lg_n00OOOii16020w(0) <= NOT n00OOOii; + wire_niO01ill_w_lg_n00OOOil16031w(0) <= NOT n00OOOil; + wire_niO01ill_w_lg_n01001lO17386w(0) <= NOT n01001lO; + wire_niO01ill_w_lg_n010ll0l17278w(0) <= NOT n010ll0l; + wire_niO01ill_w_lg_n010lOli17289w(0) <= NOT n010lOli; + wire_niO01ill_w_lg_n010lOll17294w(0) <= NOT n010lOll; + wire_niO01ill_w_lg_n011i00l17201w(0) <= NOT n011i00l; + wire_niO01ill_w_lg_n011i0Ol17530w(0) <= NOT n011i0Ol; + wire_niO01ill_w_lg_n011i0OO17761w(0) <= NOT n011i0OO; + wire_niO01ill_w_lg_n011ii1i17760w(0) <= NOT n011ii1i; + wire_niO01ill_w_lg_n011iO1l26358w(0) <= NOT n011iO1l; + wire_niO01ill_w_lg_n011l0li27777w(0) <= NOT n011l0li; + wire_niO01ill_w_lg_n011li0l25302w(0) <= NOT n011li0l; + wire_niO01ill_w_lg_n011li0O27928w(0) <= NOT n011li0O; + wire_niO01ill_w_lg_n011ll0O21069w(0) <= NOT n011ll0O; + wire_niO01ill_w_lg_n011llii21068w(0) <= NOT n011llii; + wire_niO01ill_w_lg_n011llil27693w(0) <= NOT n011llil; + wire_niO01ill_w_lg_n011lliO27691w(0) <= NOT n011lliO; + wire_niO01ill_w_lg_n011llli27689w(0) <= NOT n011llli; + wire_niO01ill_w_lg_n011llll27347w(0) <= NOT n011llll; + wire_niO01ill_w_lg_n011lllO27345w(0) <= NOT n011lllO; + wire_niO01ill_w_lg_n011lOii26058w(0) <= NOT n011lOii; + wire_niO01ill_w_lg_n01i101i17072w(0) <= NOT n01i101i; + wire_niO01ill_w_lg_n01i110i17134w(0) <= NOT n01i110i; + wire_niO01ill_w_lg_n01i110l17142w(0) <= NOT n01i110l; + wire_niO01ill_w_lg_n01i111l17137w(0) <= NOT n01i111l; + wire_niO01ill_w_lg_n01i111O17135w(0) <= NOT n01i111O; + wire_niO01ill_w_lg_n01i11iO17073w(0) <= NOT n01i11iO; + wire_niO01ill_w_lg_n01i11ll17080w(0) <= NOT n01i11ll; + wire_niO01ill_w_lg_n01iOi0i17011w(0) <= NOT n01iOi0i; + wire_niO01ill_w_lg_n01iOi1i17538w(0) <= NOT n01iOi1i; + wire_niO01ill_w_lg_n01iOi1l17003w(0) <= NOT n01iOi1l; + wire_niO01ill_w_lg_n01iOi1O17082w(0) <= NOT n01iOi1O; + wire_niO01ill_w_lg_n01iOiil17842w(0) <= NOT n01iOiil; + wire_niO01ill_w_lg_n01iOiiO17840w(0) <= NOT n01iOiiO; + wire_niO01ill_w_lg_n01iOiOi17847w(0) <= NOT n01iOiOi; + wire_niO01ill_w_lg_n01iOiOl17834w(0) <= NOT n01iOiOl; + wire_niO01ill_w_lg_n01iOiOO17845w(0) <= NOT n01iOiOO; + wire_niO01ill_w_lg_n01lOOiO16294w(0) <= NOT n01lOOiO; + wire_niO01ill_w_lg_n01O00li21075w(0) <= NOT n01O00li; + wire_niO01ill_w_lg_n01O00ll21074w(0) <= NOT n01O00ll; + wire_niO01ill_w_lg_n01O00OO27369w(0) <= NOT n01O00OO; + wire_niO01ill_w_lg_n01O01iO25304w(0) <= NOT n01O01iO; + wire_niO01ill_w_lg_n01O01li27930w(0) <= NOT n01O01li; + wire_niO01ill_w_lg_n01O0i1i27367w(0) <= NOT n01O0i1i; + wire_niO01ill_w_lg_n01O0ill26063w(0) <= NOT n01O0ill; + wire_niO01ill_w_lg_n01O110i16854w(0) <= NOT n01O110i; + wire_niO01ill_w_lg_n01O110l16853w(0) <= NOT n01O110l; + wire_niO01ill_w_lg_n01O111O16623w(0) <= NOT n01O111O; + wire_niO01ill_w_lg_n01O1i0O26360w(0) <= NOT n01O1i0O; + wire_niO01ill_w_lg_n01O1OOl27779w(0) <= NOT n01O1OOl; + wire_niO01ill_w_lg_n01OlO1i16479w(0) <= NOT n01OlO1i; + wire_niO01ill_w_lg_n0i000ii27783w(0) <= NOT n0i000ii; + wire_niO01ill_w_lg_n0i00i1l25308w(0) <= NOT n0i00i1l; + wire_niO01ill_w_lg_n0i00i1O27934w(0) <= NOT n0i00i1O; + wire_niO01ill_w_lg_n0i00l0i21086w(0) <= NOT n0i00l0i; + wire_niO01ill_w_lg_n0i00l1O21087w(0) <= NOT n0i00l1O; + wire_niO01ill_w_lg_n0i00lil27413w(0) <= NOT n0i00lil; + wire_niO01ill_w_lg_n0i00liO27411w(0) <= NOT n0i00liO; + wire_niO01ill_w_lg_n0i00O0i26073w(0) <= NOT n0i00O0i; + wire_niO01ill_w_lg_n0i0101l14480w(0) <= NOT n0i0101l; + wire_niO01ill_w_lg_n0i010ll14809w(0) <= NOT n0i010ll; + wire_niO01ill_w_lg_n0i010lO15040w(0) <= NOT n0i010lO; + wire_niO01ill_w_lg_n0i010Oi15039w(0) <= NOT n0i010Oi; + wire_niO01ill_w_lg_n0i01lOl26364w(0) <= NOT n0i01lOl; + wire_niO01ill_w_lg_n0i0O1iO14665w(0) <= NOT n0i0O1iO; + wire_niO01ill_w_lg_n0ii0l1l14557w(0) <= NOT n0ii0l1l; + wire_niO01ill_w_lg_n0ii0Oii14568w(0) <= NOT n0ii0Oii; + wire_niO01ill_w_lg_n0ii0Oil14573w(0) <= NOT n0ii0Oil; + wire_niO01ill_w_lg_n0iiiOOl14416w(0) <= NOT n0iiiOOl; + wire_niO01ill_w_lg_n0iiiOOO14414w(0) <= NOT n0iiiOOO; + wire_niO01ill_w_lg_n0iil10O14352w(0) <= NOT n0iil10O; + wire_niO01ill_w_lg_n0iil11i14413w(0) <= NOT n0iil11i; + wire_niO01ill_w_lg_n0iil11l14421w(0) <= NOT n0iil11l; + wire_niO01ill_w_lg_n0iil1il14359w(0) <= NOT n0iil1il; + wire_niO01ill_w_lg_n0iil1Oi14351w(0) <= NOT n0iil1Oi; + wire_niO01ill_w_lg_n0ili0Oi14817w(0) <= NOT n0ili0Oi; + wire_niO01ill_w_lg_n0ili0Ol14282w(0) <= NOT n0ili0Ol; + wire_niO01ill_w_lg_n0ili0OO14361w(0) <= NOT n0ili0OO; + wire_niO01ill_w_lg_n0ilii0l15121w(0) <= NOT n0ilii0l; + wire_niO01ill_w_lg_n0ilii0O15119w(0) <= NOT n0ilii0O; + wire_niO01ill_w_lg_n0ilii1i14290w(0) <= NOT n0ilii1i; + wire_niO01ill_w_lg_n0iliili15126w(0) <= NOT n0iliili; + wire_niO01ill_w_lg_n0iliill15113w(0) <= NOT n0iliill; + wire_niO01ill_w_lg_n0iliilO15124w(0) <= NOT n0iliilO; + wire_niO01ill_w_lg_n0iOiO0O13573w(0) <= NOT n0iOiO0O; + wire_niO01ill_w_lg_n0iOiOOO13902w(0) <= NOT n0iOiOOO; + wire_niO01ill_w_lg_n0iOl11i14133w(0) <= NOT n0iOl11i; + wire_niO01ill_w_lg_n0iOl11l14132w(0) <= NOT n0iOl11l; + wire_niO01ill_w_lg_n0iOli1O26366w(0) <= NOT n0iOli1O; + wire_niO01ill_w_lg_n0iOlOll27785w(0) <= NOT n0iOlOll; + wire_niO01ill_w_lg_n0iOO0ii21093w(0) <= NOT n0iOO0ii; + wire_niO01ill_w_lg_n0iOO0il21092w(0) <= NOT n0iOO0il; + wire_niO01ill_w_lg_n0iOO0lO27436w(0) <= NOT n0iOO0lO; + wire_niO01ill_w_lg_n0iOO0Oi27434w(0) <= NOT n0iOO0Oi; + wire_niO01ill_w_lg_n0iOO10O25310w(0) <= NOT n0iOO10O; + wire_niO01ill_w_lg_n0iOO1ii27936w(0) <= NOT n0iOO1ii; + wire_niO01ill_w_lg_n0iOOiil26078w(0) <= NOT n0iOOiil; + wire_niO01ill_w_lg_n0l01l0i13507w(0) <= NOT n0l01l0i; + wire_niO01ill_w_lg_n0l01l0l13506w(0) <= NOT n0l01l0l; + wire_niO01ill_w_lg_n0l01l0O13514w(0) <= NOT n0l01l0O; + wire_niO01ill_w_lg_n0l01l1O13509w(0) <= NOT n0l01l1O; + wire_niO01ill_w_lg_n0l01lli13445w(0) <= NOT n0l01lli; + wire_niO01ill_w_lg_n0l01llO13452w(0) <= NOT n0l01llO; + wire_niO01ill_w_lg_n0l01O1l13444w(0) <= NOT n0l01O1l; + wire_niO01ill_w_lg_n0l10lOi13758w(0) <= NOT n0l10lOi; + wire_niO01ill_w_lg_n0l1O00O13650w(0) <= NOT n0l1O00O; + wire_niO01ill_w_lg_n0l1Oill13661w(0) <= NOT n0l1Oill; + wire_niO01ill_w_lg_n0l1OilO13666w(0) <= NOT n0l1OilO; + wire_niO01ill_w_lg_n0li101i14217w(0) <= NOT n0li101i; + wire_niO01ill_w_lg_n0li110i13454w(0) <= NOT n0li110i; + wire_niO01ill_w_lg_n0li110l13383w(0) <= NOT n0li110l; + wire_niO01ill_w_lg_n0li111l13910w(0) <= NOT n0li111l; + wire_niO01ill_w_lg_n0li111O13375w(0) <= NOT n0li111O; + wire_niO01ill_w_lg_n0li11iO14214w(0) <= NOT n0li11iO; + wire_niO01ill_w_lg_n0li11li14212w(0) <= NOT n0li11li; + wire_niO01ill_w_lg_n0li11Ol14219w(0) <= NOT n0li11Ol; + wire_niO01ill_w_lg_n0li11OO14206w(0) <= NOT n0li11OO; + wire_niO01ill_w_lg_n0ll01ii26368w(0) <= NOT n0ll01ii; + wire_niO01ill_w_lg_n0ll0iOO27787w(0) <= NOT n0ll0iOO; + wire_niO01ill_w_lg_n0ll0lli25312w(0) <= NOT n0ll0lli; + wire_niO01ill_w_lg_n0ll0lll27938w(0) <= NOT n0ll0lll; + wire_niO01ill_w_lg_n0ll0Oll21099w(0) <= NOT n0ll0Oll; + wire_niO01ill_w_lg_n0ll0OlO21098w(0) <= NOT n0ll0OlO; + wire_niO01ill_w_lg_n0ll1ili12666w(0) <= NOT n0ll1ili; + wire_niO01ill_w_lg_n0ll1l0i12995w(0) <= NOT n0ll1l0i; + wire_niO01ill_w_lg_n0ll1l0l13226w(0) <= NOT n0ll1l0l; + wire_niO01ill_w_lg_n0ll1l0O13225w(0) <= NOT n0ll1l0O; + wire_niO01ill_w_lg_n0lli11i27458w(0) <= NOT n0lli11i; + wire_niO01ill_w_lg_n0lli11l27456w(0) <= NOT n0lli11l; + wire_niO01ill_w_lg_n0lli1lO26083w(0) <= NOT n0lli1lO; + wire_niO01ill_w_lg_n0llOi1l12851w(0) <= NOT n0llOi1l; + wire_niO01ill_w_lg_n0lO0Oli12743w(0) <= NOT n0lO0Oli; + wire_niO01ill_w_lg_n0lOi01i12759w(0) <= NOT n0lOi01i; + wire_niO01ill_w_lg_n0lOi1OO12754w(0) <= NOT n0lOi1OO; + wire_niO01ill_w_lg_n0lOl0ii12602w(0) <= NOT n0lOl0ii; + wire_niO01ill_w_lg_n0lOl0il12600w(0) <= NOT n0lOl0il; + wire_niO01ill_w_lg_n0lOl0iO12599w(0) <= NOT n0lOl0iO; + wire_niO01ill_w_lg_n0lOl0li12607w(0) <= NOT n0lOl0li; + wire_niO01ill_w_lg_n0lOl0Ol12538w(0) <= NOT n0lOl0Ol; + wire_niO01ill_w_lg_n0lOli0O12537w(0) <= NOT n0lOli0O; + wire_niO01ill_w_lg_n0lOli1i12545w(0) <= NOT n0lOli1i; + wire_niO01ill_w_lg_n0O0l0il12084w(0) <= NOT n0O0l0il; + wire_niO01ill_w_lg_n0O0l0iO12318w(0) <= NOT n0O0l0iO; + wire_niO01ill_w_lg_n0O0l0li12317w(0) <= NOT n0O0l0li; + wire_niO01ill_w_lg_n0O0l1Ol11755w(0) <= NOT n0O0l1Ol; + wire_niO01ill_w_lg_n0O0llll26370w(0) <= NOT n0O0llll; + wire_niO01ill_w_lg_n0O0O00i27789w(0) <= NOT n0O0O00i; + wire_niO01ill_w_lg_n0O0O0Ol25314w(0) <= NOT n0O0O0Ol; + wire_niO01ill_w_lg_n0O0O0OO27940w(0) <= NOT n0O0O0OO; + wire_niO01ill_w_lg_n0O0OiOO21105w(0) <= NOT n0O0OiOO; + wire_niO01ill_w_lg_n0O0Ol0i27703w(0) <= NOT n0O0Ol0i; + wire_niO01ill_w_lg_n0O0Ol0l27480w(0) <= NOT n0O0Ol0l; + wire_niO01ill_w_lg_n0O0Ol0O27478w(0) <= NOT n0O0Ol0O; + wire_niO01ill_w_lg_n0O0Ol1i21104w(0) <= NOT n0O0Ol1i; + wire_niO01ill_w_lg_n0O0Ol1l27707w(0) <= NOT n0O0Ol1l; + wire_niO01ill_w_lg_n0O0Ol1O27705w(0) <= NOT n0O0Ol1O; + wire_niO01ill_w_lg_n0O0OO1i26088w(0) <= NOT n0O0OO1i; + wire_niO01ill_w_lg_n0O1il0O13003w(0) <= NOT n0O1il0O; + wire_niO01ill_w_lg_n0O1ilii12468w(0) <= NOT n0O1ilii; + wire_niO01ill_w_lg_n0O1ilil12547w(0) <= NOT n0O1ilil; + wire_niO01ill_w_lg_n0O1iliO12476w(0) <= NOT n0O1iliO; + wire_niO01ill_w_lg_n0O1ilOi13307w(0) <= NOT n0O1ilOi; + wire_niO01ill_w_lg_n0O1ilOl13305w(0) <= NOT n0O1ilOl; + wire_niO01ill_w_lg_n0O1iO0i13299w(0) <= NOT n0O1iO0i; + wire_niO01ill_w_lg_n0O1iO0l13310w(0) <= NOT n0O1iO0l; + wire_niO01ill_w_lg_n0O1iO1O13312w(0) <= NOT n0O1iO1O; + wire_niO01ill_w_lg_n0Oii10O11940w(0) <= NOT n0Oii10O; + wire_niO01ill_w_lg_n0OiOiOl11832w(0) <= NOT n0OiOiOl; + wire_niO01ill_w_lg_n0OiOO0i11843w(0) <= NOT n0OiOO0i; + wire_niO01ill_w_lg_n0OiOO0l11848w(0) <= NOT n0OiOO0l; + wire_niO01ill_w_lg_n0Ol010l11633w(0) <= NOT n0Ol010l; + wire_niO01ill_w_lg_n0Ol011O11626w(0) <= NOT n0Ol011O; + wire_niO01ill_w_lg_n0Ol01li11625w(0) <= NOT n0Ol01li; + wire_niO01ill_w_lg_n0Ol1Oll11691w(0) <= NOT n0Ol1Oll; + wire_niO01ill_w_lg_n0Ol1OlO11689w(0) <= NOT n0Ol1OlO; + wire_niO01ill_w_lg_n0Ol1OOi11688w(0) <= NOT n0Ol1OOi; + wire_niO01ill_w_lg_n0Ol1OOl11696w(0) <= NOT n0Ol1OOl; + wire_niO01ill_w_lg_n0OO10li12093w(0) <= NOT n0OO10li; + wire_niO01ill_w_lg_n0OO10ll11555w(0) <= NOT n0OO10ll; + wire_niO01ill_w_lg_n0OO10lO11635w(0) <= NOT n0OO10lO; + wire_niO01ill_w_lg_n0OO10Oi11564w(0) <= NOT n0OO10Oi; + wire_niO01ill_w_lg_n0OO1i1l12400w(0) <= NOT n0OO1i1l; + wire_niO01ill_w_lg_n0OO1i1O12398w(0) <= NOT n0OO1i1O; + wire_niO01ill_w_lg_n0OO1iii12405w(0) <= NOT n0OO1iii; + wire_niO01ill_w_lg_n0OO1iil12392w(0) <= NOT n0OO1iil; + wire_niO01ill_w_lg_n0OO1iiO12403w(0) <= NOT n0OO1iiO; + wire_niO01ill_w_lg_n0OOOllO10656w(0) <= NOT n0OOOllO; + wire_niO01ill_w_lg_n1101ili24106w(0) <= NOT n1101ili; + wire_niO01ill_w_lg_n1101ill24107w(0) <= NOT n1101ill; + wire_niO01ill_w_lg_n1101ilO27420w(0) <= NOT n1101ilO; + wire_niO01ill_w_lg_n1101iOl9948w(0) <= NOT n1101iOl; + wire_niO01ill_w_lg_n1101iOO9949w(0) <= NOT n1101iOO; + wire_niO01ill_w_lg_n1101l0i16090w(0) <= NOT n1101l0i; + wire_niO01ill_w_lg_n1101l0l15183w(0) <= NOT n1101l0l; + wire_niO01ill_w_lg_n1101l0O14276w(0) <= NOT n1101l0O; + wire_niO01ill_w_lg_n1101l1i11551w(0) <= NOT n1101l1i; + wire_niO01ill_w_lg_n1101l1l17904w(0) <= NOT n1101l1l; + wire_niO01ill_w_lg_n1101l1O16997w(0) <= NOT n1101l1O; + wire_niO01ill_w_lg_n1101lii13369w(0) <= NOT n1101lii; + wire_niO01ill_w_lg_n1101lil12462w(0) <= NOT n1101lil; + wire_niO01ill_w_lg_n1101liO11541w(0) <= NOT n1101liO; + wire_niO01ill_w_lg_n1101lli18954w(0) <= NOT n1101lli; + wire_niO01ill_w_lg_n110OOii23546w(0) <= NOT n110OOii; + wire_niO01ill_w_lg_n110OOil26683w(0) <= NOT n110OOil; + wire_niO01ill_w_lg_n110OOiO26681w(0) <= NOT n110OOiO; + wire_niO01ill_w_lg_n110OOli26679w(0) <= NOT n110OOli; + wire_niO01ill_w_lg_n110OOll26678w(0) <= NOT n110OOll; + wire_niO01ill_w_lg_n110OOlO23486w(0) <= NOT n110OOlO; + wire_niO01ill_w_lg_n110OOOi19589w(0) <= NOT n110OOOi; + wire_niO01ill_w_lg_n110OOOl19590w(0) <= NOT n110OOOl; + wire_niO01ill_w_lg_n110OOOO19843w(0) <= NOT n110OOOO; + wire_niO01ill_w_lg_n1110O0O18762w(0) <= NOT n1110O0O; + wire_niO01ill_w_lg_n1110Oii21198w(0) <= NOT n1110Oii; + wire_niO01ill_w_lg_n1110Oli23547w(0) <= NOT n1110Oli; + wire_niO01ill_w_lg_n111i00i9978w(0) <= NOT n111i00i; + wire_niO01ill_w_lg_n111i00l9976w(0) <= NOT n111i00l; + wire_niO01ill_w_lg_n111i00O9974w(0) <= NOT n111i00O; + wire_niO01ill_w_lg_n111i01i9990w(0) <= NOT n111i01i; + wire_niO01ill_w_lg_n111i01l9986w(0) <= NOT n111i01l; + wire_niO01ill_w_lg_n111i01O9984w(0) <= NOT n111i01O; + wire_niO01ill_w_lg_n111i0ii9973w(0) <= NOT n111i0ii; + wire_niO01ill_w_lg_n111i0il23585w(0) <= NOT n111i0il; + wire_niO01ill_w_lg_n111i10i12354w(0) <= NOT n111i10i; + wire_niO01ill_w_lg_n111i10l23888w(0) <= NOT n111i10l; + wire_niO01ill_w_lg_n111i10O9993w(0) <= NOT n111i10O; + wire_niO01ill_w_lg_n111i1OO10028w(0) <= NOT n111i1OO; + wire_niO01ill_w_lg_n11i111i19847w(0) <= NOT n11i111i; + wire_niO01ill_w_lg_n11i111l19781w(0) <= NOT n11i111l; + wire_niO01ill_w_lg_n11i111O19840w(0) <= NOT n11i111O; + wire_niO01ill_w_lg_n11l0Oii20659w(0) <= NOT n11l0Oii; + wire_niO01ill_w_lg_n11l0OiO23413w(0) <= NOT n11l0OiO; + wire_niO01ill_w_lg_n11l0Oli23446w(0) <= NOT n11l0Oli; + wire_niO01ill_w_lg_n11l0Oll26665w(0) <= NOT n11l0Oll; + wire_niO01ill_w_lg_n11l0OlO26663w(0) <= NOT n11l0OlO; + wire_niO01ill_w_lg_n11l0OOi26662w(0) <= NOT n11l0OOi; + wire_niO01ill_w_lg_n11l0OOl23442w(0) <= NOT n11l0OOl; + wire_niO01ill_w_lg_n11l0OOO26621w(0) <= NOT n11l0OOO; + wire_niO01ill_w_lg_n11li10i21145w(0) <= NOT n11li10i; + wire_niO01ill_w_lg_n11li10l21153w(0) <= NOT n11li10l; + wire_niO01ill_w_lg_n11li10O21143w(0) <= NOT n11li10O; + wire_niO01ill_w_lg_n11li11i26619w(0) <= NOT n11li11i; + wire_niO01ill_w_lg_n11li11l26618w(0) <= NOT n11li11l; + wire_niO01ill_w_lg_n11li1ii21150w(0) <= NOT n11li1ii; + wire_niO01ill_w_lg_n11li1li9830w(0) <= NOT n11li1li; + wire_niO01ill_w_lg_n11O000i26436w(0) <= NOT n11O000i; + wire_niO01ill_w_lg_n11O000l26434w(0) <= NOT n11O000l; + wire_niO01ill_w_lg_n11O000O26433w(0) <= NOT n11O000O; + wire_niO01ill_w_lg_n11O001i26442w(0) <= NOT n11O001i; + wire_niO01ill_w_lg_n11O001l26440w(0) <= NOT n11O001l; + wire_niO01ill_w_lg_n11O001O26438w(0) <= NOT n11O001O; + wire_niO01ill_w_lg_n11O00ll20660w(0) <= NOT n11O00ll; + wire_niO01ill_w_lg_n11O00OO21203w(0) <= NOT n11O00OO; + wire_niO01ill_w_lg_n11O011i25915w(0) <= NOT n11O011i; + wire_niO01ill_w_lg_n11O01Ol26446w(0) <= NOT n11O01Ol; + wire_niO01ill_w_lg_n11O01OO26444w(0) <= NOT n11O01OO; + wire_niO01ill_w_lg_n11O0i1i20661w(0) <= NOT n11O0i1i; + wire_niO01ill_w_lg_n11O0i1O26590w(0) <= NOT n11O0i1O; + wire_niO01ill_w_lg_n11O0ill20641w(0) <= NOT n11O0ill; + wire_niO01ill_w_lg_n11O0ilO21059w(0) <= NOT n11O0ilO; + wire_niO01ill_w_lg_n11O0iOi21061w(0) <= NOT n11O0iOi; + wire_niO01ill_w_lg_n11O0l1l24585w(0) <= NOT n11O0l1l; + wire_niO01ill_w_lg_n11O0l1O19986w(0) <= NOT n11O0l1O; + wire_niO01ill_w_lg_n11O0lii19984w(0) <= NOT n11O0lii; + wire_niO01ill_w_lg_n11O0lil24584w(0) <= NOT n11O0lil; + wire_niO01ill_w_lg_n11O0lli18955w(0) <= NOT n11O0lli; + wire_niO01ill_w_lg_n11O0lll20250w(0) <= NOT n11O0lll; + wire_niO01ill_w_lg_n11O0llO24108w(0) <= NOT n11O0llO; + wire_niO01ill_w_lg_n11O0lOl24768w(0) <= NOT n11O0lOl; + wire_niO01ill_w_lg_n11O0O1O25056w(0) <= NOT n11O0O1O; + wire_niO01ill_w_lg_n11O0Oii24765w(0) <= NOT n11O0Oii; + wire_niO01ill_w_lg_n11O0OiO21115w(0) <= NOT n11O0OiO; + wire_niO01ill_w_lg_n11O0Oli21040w(0) <= NOT n11O0Oli; + wire_niO01ill_w_lg_n11O0Oll20924w(0) <= NOT n11O0Oll; + wire_niO01ill_w_lg_n11O0OlO19978w(0) <= NOT n11O0OlO; + wire_niO01ill_w_lg_n11O0OOi19979w(0) <= NOT n11O0OOi; + wire_niO01ill_w_lg_n11O1lil21210w(0) <= NOT n11O1lil; + wire_niO01ill_w_lg_n11O1Oii20948w(0) <= NOT n11O1Oii; + wire_niO01ill_w_lg_n11O1OiO25928w(0) <= NOT n11O1OiO; + wire_niO01ill_w_lg_n11O1Oli25926w(0) <= NOT n11O1Oli; + wire_niO01ill_w_lg_n11O1Oll25924w(0) <= NOT n11O1Oll; + wire_niO01ill_w_lg_n11O1OlO25922w(0) <= NOT n11O1OlO; + wire_niO01ill_w_lg_n11O1OOi25920w(0) <= NOT n11O1OOi; + wire_niO01ill_w_lg_n11O1OOl25918w(0) <= NOT n11O1OOl; + wire_niO01ill_w_lg_n11O1OOO25916w(0) <= NOT n11O1OOO; + wire_niO01ill_w_lg_n11Oi01l24760w(0) <= NOT n11Oi01l; + wire_niO01ill_w_lg_n11Oi0ii25477w(0) <= NOT n11Oi0ii; + wire_niO01ill_w_lg_n11Oi10i23897w(0) <= NOT n11Oi10i; + wire_niO01ill_w_lg_n11Oi10l20175w(0) <= NOT n11Oi10l; + wire_niO01ill_w_lg_n11Oi10O19980w(0) <= NOT n11Oi10O; + wire_niO01ill_w_lg_n11Oi1ii23487w(0) <= NOT n11Oi1ii; + wire_niO01ill_w_lg_n11Oi1il19977w(0) <= NOT n11Oi1il; + wire_niO01ill_w_lg_n11Oi1ll23889w(0) <= NOT n11Oi1ll; + wire_niO01ill_w_lg_n1iili0l25475w(0) <= NOT n1iili0l; + wire_niO01ill_w_lg_n1iili0O25473w(0) <= NOT n1iili0O; + wire_niO01ill_w_lg_n1iiliii25471w(0) <= NOT n1iiliii; + wire_niO01ill_w_lg_n1iiliil25469w(0) <= NOT n1iiliil; + wire_niO01ill_w_lg_n1iiliiO25467w(0) <= NOT n1iiliiO; + wire_niO01ill_w_lg_n1iilili25465w(0) <= NOT n1iilili; + wire_niO01ill_w_lg_n1iilill25463w(0) <= NOT n1iilill; + wire_niO01ill_w_lg_n1iililO25461w(0) <= NOT n1iililO; + wire_niO01ill_w_lg_n1iiliOi25459w(0) <= NOT n1iiliOi; + wire_niO01ill_w_lg_n1iiliOl25457w(0) <= NOT n1iiliOl; + wire_niO01ill_w_lg_n1iiliOO25455w(0) <= NOT n1iiliOO; + wire_niO01ill_w_lg_n1iill0i25447w(0) <= NOT n1iill0i; + wire_niO01ill_w_lg_n1iill0l25445w(0) <= NOT n1iill0l; + wire_niO01ill_w_lg_n1iill0O25443w(0) <= NOT n1iill0O; + wire_niO01ill_w_lg_n1iill1i25453w(0) <= NOT n1iill1i; + wire_niO01ill_w_lg_n1iill1l25451w(0) <= NOT n1iill1l; + wire_niO01ill_w_lg_n1iill1O25449w(0) <= NOT n1iill1O; + wire_niO01ill_w_lg_n1iillii25441w(0) <= NOT n1iillii; + wire_niO01ill_w_lg_n1iillil25440w(0) <= NOT n1iillil; + wire_niO01ill_w_lg_n1iillli25438w(0) <= NOT n1iillli; + wire_niO01ill_w_lg_n1iiOlii25436w(0) <= NOT n1iiOlii; + wire_niO01ill_w_lg_n1iiOlil25434w(0) <= NOT n1iiOlil; + wire_niO01ill_w_lg_n1iiOliO25432w(0) <= NOT n1iiOliO; + wire_niO01ill_w_lg_n1iiOlli25431w(0) <= NOT n1iiOlli; + wire_niO01ill_w_lg_n1il100i25425w(0) <= NOT n1il100i; + wire_niO01ill_w_lg_n1il100l25423w(0) <= NOT n1il100l; + wire_niO01ill_w_lg_n1il100O25421w(0) <= NOT n1il100O; + wire_niO01ill_w_lg_n1il101l25429w(0) <= NOT n1il101l; + wire_niO01ill_w_lg_n1il101O25427w(0) <= NOT n1il101O; + wire_niO01ill_w_lg_n1il10ii25419w(0) <= NOT n1il10ii; + wire_niO01ill_w_lg_n1il10il25417w(0) <= NOT n1il10il; + wire_niO01ill_w_lg_n1il10iO25415w(0) <= NOT n1il10iO; + wire_niO01ill_w_lg_n1il10li25413w(0) <= NOT n1il10li; + wire_niO01ill_w_lg_n1il10ll25411w(0) <= NOT n1il10ll; + wire_niO01ill_w_lg_n1il10lO25409w(0) <= NOT n1il10lO; + wire_niO01ill_w_lg_n1il10Oi25407w(0) <= NOT n1il10Oi; + wire_niO01ill_w_lg_n1il10Ol25405w(0) <= NOT n1il10Ol; + wire_niO01ill_w_lg_n1il10OO25403w(0) <= NOT n1il10OO; + wire_niO01ill_w_lg_n1il11il20644w(0) <= NOT n1il11il; + wire_niO01ill_w_lg_n1il11lO20653w(0) <= NOT n1il11lO; + wire_niO01ill_w_lg_n1il11Oi20651w(0) <= NOT n1il11Oi; + wire_niO01ill_w_lg_n1il1i0i25395w(0) <= NOT n1il1i0i; + wire_niO01ill_w_lg_n1il1i0l25394w(0) <= NOT n1il1i0l; + wire_niO01ill_w_lg_n1il1i1i25401w(0) <= NOT n1il1i1i; + wire_niO01ill_w_lg_n1il1i1l25399w(0) <= NOT n1il1i1l; + wire_niO01ill_w_lg_n1il1i1O25397w(0) <= NOT n1il1i1O; + wire_niO01ill_w_lg_n1illOiO26400w(0) <= NOT n1illOiO; + wire_niO01ill_w_lg_n1ilOO0i26392w(0) <= NOT n1ilOO0i; + wire_niO01ill_w_lg_n1ilOO0l26390w(0) <= NOT n1ilOO0l; + wire_niO01ill_w_lg_n1ilOO0O26388w(0) <= NOT n1ilOO0O; + wire_niO01ill_w_lg_n1ilOO1i26398w(0) <= NOT n1ilOO1i; + wire_niO01ill_w_lg_n1ilOO1l26396w(0) <= NOT n1ilOO1l; + wire_niO01ill_w_lg_n1ilOO1O26394w(0) <= NOT n1ilOO1O; + wire_niO01ill_w_lg_n1ilOOii26387w(0) <= NOT n1ilOOii; + wire_niO01ill_w_lg_n1ilOOil20296w(0) <= NOT n1ilOOil; + wire_niO01ill_w_lg_n1ilOOli25329w(0) <= NOT n1ilOOli; + wire_niO01ill_w_lg_n1ilOOll25327w(0) <= NOT n1ilOOll; + wire_niO01ill_w_lg_n1ilOOlO25325w(0) <= NOT n1ilOOlO; + wire_niO01ill_w_lg_n1ilOOOi25323w(0) <= NOT n1ilOOOi; + wire_niO01ill_w_lg_n1ilOOOl25321w(0) <= NOT n1ilOOOl; + wire_niO01ill_w_lg_n1ilOOOO25319w(0) <= NOT n1ilOOOO; + wire_niO01ill_w_lg_n1iO001i25331w(0) <= NOT n1iO001i; + wire_niO01ill_w_lg_n1iO001l25299w(0) <= NOT n1iO001l; + wire_niO01ill_w_lg_n1iO01Oi25336w(0) <= NOT n1iO01Oi; + wire_niO01ill_w_lg_n1iO01Ol25334w(0) <= NOT n1iO01Ol; + wire_niO01ill_w_lg_n1iO01OO25332w(0) <= NOT n1iO01OO; + wire_niO01ill_w_lg_n1iO0ili25297w(0) <= NOT n1iO0ili; + wire_niO01ill_w_lg_n1iO0ill25295w(0) <= NOT n1iO0ill; + wire_niO01ill_w_lg_n1iO0ilO25293w(0) <= NOT n1iO0ilO; + wire_niO01ill_w_lg_n1iO0iOi25291w(0) <= NOT n1iO0iOi; + wire_niO01ill_w_lg_n1iO0iOl25289w(0) <= NOT n1iO0iOl; + wire_niO01ill_w_lg_n1iO0iOO25287w(0) <= NOT n1iO0iOO; + wire_niO01ill_w_lg_n1iO0l0i25279w(0) <= NOT n1iO0l0i; + wire_niO01ill_w_lg_n1iO0l0l25278w(0) <= NOT n1iO0l0l; + wire_niO01ill_w_lg_n1iO0l1i25285w(0) <= NOT n1iO0l1i; + wire_niO01ill_w_lg_n1iO0l1l25283w(0) <= NOT n1iO0l1l; + wire_niO01ill_w_lg_n1iO0l1O25281w(0) <= NOT n1iO0l1O; + wire_niO01ill_w_lg_n1iO110i26674w(0) <= NOT n1iO110i; + wire_niO01ill_w_lg_n1iO110l26672w(0) <= NOT n1iO110l; + wire_niO01ill_w_lg_n1iO110O26670w(0) <= NOT n1iO110O; + wire_niO01ill_w_lg_n1iO111i25317w(0) <= NOT n1iO111i; + wire_niO01ill_w_lg_n1iO111l25316w(0) <= NOT n1iO111l; + wire_niO01ill_w_lg_n1iO111O26676w(0) <= NOT n1iO111O; + wire_niO01ill_w_lg_n1iO11ii26668w(0) <= NOT n1iO11ii; + wire_niO01ill_w_lg_n1iO11il26667w(0) <= NOT n1iO11il; + wire_niO01ill_w_lg_n1iO11iO25338w(0) <= NOT n1iO11iO; + wire_niO01ill_w_lg_n1iOl00i25187w(0) <= NOT n1iOl00i; + wire_niO01ill_w_lg_n1iOl00l25185w(0) <= NOT n1iOl00l; + wire_niO01ill_w_lg_n1iOl00O25183w(0) <= NOT n1iOl00O; + wire_niO01ill_w_lg_n1iOl01i25190w(0) <= NOT n1iOl01i; + wire_niO01ill_w_lg_n1iOl0il25181w(0) <= NOT n1iOl0il; + wire_niO01ill_w_lg_n1iOl0Oi25180w(0) <= NOT n1iOl0Oi; + wire_niO01ill_w_lg_n1iOl1Ol25194w(0) <= NOT n1iOl1Ol; + wire_niO01ill_w_lg_n1iOl1OO25192w(0) <= NOT n1iOl1OO; + wire_niO01ill_w_lg_n1l0001i11682w(0) <= NOT n1l0001i; + wire_niO01ill_w_lg_n1l000ll19831w(0) <= NOT n1l000ll; + wire_niO01ill_w_lg_n1l000lO19828w(0) <= NOT n1l000lO; + wire_niO01ill_w_lg_n1l000Oi19826w(0) <= NOT n1l000Oi; + wire_niO01ill_w_lg_n1l000Ol19825w(0) <= NOT n1l000Ol; + wire_niO01ill_w_lg_n1l000OO19823w(0) <= NOT n1l000OO; + wire_niO01ill_w_lg_n1l0010i11548w(0) <= NOT n1l0010i; + wire_niO01ill_w_lg_n1l0010l11543w(0) <= NOT n1l0010l; + wire_niO01ill_w_lg_n1l0010O11542w(0) <= NOT n1l0010O; + wire_niO01ill_w_lg_n1l0011l19903w(0) <= NOT n1l0011l; + wire_niO01ill_w_lg_n1l0011O19569w(0) <= NOT n1l0011O; + wire_niO01ill_w_lg_n1l001ii19891w(0) <= NOT n1l001ii; + wire_niO01ill_w_lg_n1l001il19881w(0) <= NOT n1l001il; + wire_niO01ill_w_lg_n1l001li19878w(0) <= NOT n1l001li; + wire_niO01ill_w_lg_n1l001lO19896w(0) <= NOT n1l001lO; + wire_niO01ill_w_lg_n1l001Oi19874w(0) <= NOT n1l001Oi; + wire_niO01ill_w_lg_n1l001Ol19893w(0) <= NOT n1l001Ol; + wire_niO01ill_w_lg_n1l001OO19872w(0) <= NOT n1l001OO; + wire_niO01ill_w_lg_n1l00i0i23478w(0) <= NOT n1l00i0i; + wire_niO01ill_w_lg_n1l00i1i19784w(0) <= NOT n1l00i1i; + wire_niO01ill_w_lg_n1l00i1l19819w(0) <= NOT n1l00i1l; + wire_niO01ill_w_lg_n1l00i1O19818w(0) <= NOT n1l00i1O; + wire_niO01ill_w_lg_n1l10iiO19988w(0) <= NOT n1l10iiO; + wire_niO01ill_w_lg_n1l1100i25172w(0) <= NOT n1l1100i; + wire_niO01ill_w_lg_n1l1100l25170w(0) <= NOT n1l1100l; + wire_niO01ill_w_lg_n1l1100O25168w(0) <= NOT n1l1100O; + wire_niO01ill_w_lg_n1l1101i25178w(0) <= NOT n1l1101i; + wire_niO01ill_w_lg_n1l1101l25176w(0) <= NOT n1l1101l; + wire_niO01ill_w_lg_n1l1101O25174w(0) <= NOT n1l1101O; + wire_niO01ill_w_lg_n1l110ii25166w(0) <= NOT n1l110ii; + wire_niO01ill_w_lg_n1l110il25165w(0) <= NOT n1l110il; + wire_niO01ill_w_lg_n1l110iO20000w(0) <= NOT n1l110iO; + wire_niO01ill_w_lg_n1l1OlOi18773w(0) <= NOT n1l1OlOi; + wire_niO01ill_w_lg_n1l1OO0i19949w(0) <= NOT n1l1OO0i; + wire_niO01ill_w_lg_n1l1OO0O19945w(0) <= NOT n1l1OO0O; + wire_niO01ill_w_lg_n1l1OO1i19975w(0) <= NOT n1l1OO1i; + wire_niO01ill_w_lg_n1l1OO1l19974w(0) <= NOT n1l1OO1l; + wire_niO01ill_w_lg_n1l1OO1O19951w(0) <= NOT n1l1OO1O; + wire_niO01ill_w_lg_n1l1OOii19943w(0) <= NOT n1l1OOii; + wire_niO01ill_w_lg_n1l1OOiO19939w(0) <= NOT n1l1OOiO; + wire_niO01ill_w_lg_n1l1OOll19935w(0) <= NOT n1l1OOll; + wire_niO01ill_w_lg_n1l1OOlO19933w(0) <= NOT n1l1OOlO; + wire_niO01ill_w_lg_n1l1OOOl11561w(0) <= NOT n1l1OOOl; + wire_niO01ill_w_lg_n1lil0Ol23456w(0) <= NOT n1lil0Ol; + wire_niO01ill_w_lg_n1lilill18949w(0) <= NOT n1lilill; + wire_niO01ill_w_lg_n1lill0l19912w(0) <= NOT n1lill0l; + wire_niO01ill_w_lg_n1lill0O19911w(0) <= NOT n1lill0O; + wire_niO01ill_w_lg_n1lill1l18967w(0) <= NOT n1lill1l; + wire_niO01ill_w_lg_n1lill1O19915w(0) <= NOT n1lill1O; + wire_niO01ill_w_lg_n1lillii18973w(0) <= NOT n1lillii; + wire_niO01ill_w_lg_n1lilO0l19657w(0) <= NOT n1lilO0l; + wire_niO01ill_w_lg_n1lO0lOi9962w(0) <= NOT n1lO0lOi; + wire_niO01ill_w_lg_n1lOi1lO18946w(0) <= NOT n1lOi1lO; + wire_niO01ill_w_lg_n1lOi1Oi18943w(0) <= NOT n1lOi1Oi; + wire_niO01ill_w_lg_n1lOi1Ol18942w(0) <= NOT n1lOi1Ol; + wire_niO01ill_w_lg_n1O0Ol1i18108w(0) <= NOT n1O0Ol1i; + wire_niO01ill_w_lg_n1O0Olli18437w(0) <= NOT n1O0Olli; + wire_niO01ill_w_lg_n1O0Olll18668w(0) <= NOT n1O0Olll; + wire_niO01ill_w_lg_n1O0OllO18667w(0) <= NOT n1O0OllO; + wire_niO01ill_w_lg_n1Oi001O26054w(0) <= NOT n1Oi001O; + wire_niO01ill_w_lg_n1Oi010i27686w(0) <= NOT n1Oi010i; + wire_niO01ill_w_lg_n1Oi010l27684w(0) <= NOT n1Oi010l; + wire_niO01ill_w_lg_n1Oi010O27682w(0) <= NOT n1Oi010O; + wire_niO01ill_w_lg_n1Oi011l21064w(0) <= NOT n1Oi011l; + wire_niO01ill_w_lg_n1Oi011O21063w(0) <= NOT n1Oi011O; + wire_niO01ill_w_lg_n1Oi01ii27325w(0) <= NOT n1Oi01ii; + wire_niO01ill_w_lg_n1Oi01il27323w(0) <= NOT n1Oi01il; + wire_niO01ill_w_lg_n1Oi11Oi26357w(0) <= NOT n1Oi11Oi; + wire_niO01ill_w_lg_n1Oi1l0O27776w(0) <= NOT n1Oi1l0O; + wire_niO01ill_w_lg_n1Oi1O1i25301w(0) <= NOT n1Oi1O1i; + wire_niO01ill_w_lg_n1Oi1O1l27927w(0) <= NOT n1Oi1O1l; + wire_niO01ill_w_lg_n1Oiliil18293w(0) <= NOT n1Oiliil; + wire_niO01ill_w_lg_n1Ol000O18196w(0) <= NOT n1Ol000O; + wire_niO01ill_w_lg_n1Ol00ii18201w(0) <= NOT n1Ol00ii; + wire_niO01ill_w_lg_n1Ol011i18185w(0) <= NOT n1Ol011i; + wire_niO01ill_w_lg_n1Oli0Oi18044w(0) <= NOT n1Oli0Oi; + wire_niO01ill_w_lg_n1Oli0Ol18042w(0) <= NOT n1Oli0Ol; + wire_niO01ill_w_lg_n1Oli0OO18041w(0) <= NOT n1Oli0OO; + wire_niO01ill_w_lg_n1Olii0l17980w(0) <= NOT n1Olii0l; + wire_niO01ill_w_lg_n1Olii1i18049w(0) <= NOT n1Olii1i; + wire_niO01ill_w_lg_n1Oliiii17987w(0) <= NOT n1Oliiii; + wire_niO01ill_w_lg_n1OliilO17979w(0) <= NOT n1OliilO; + wire_niO01ill_w_lg_n1OO0llO18445w(0) <= NOT n1OO0llO; + wire_niO01ill_w_lg_n1OO0lOi17910w(0) <= NOT n1OO0lOi; + wire_niO01ill_w_lg_n1OO0lOl17989w(0) <= NOT n1OO0lOl; + wire_niO01ill_w_lg_n1OO0lOO17918w(0) <= NOT n1OO0lOO; + wire_niO01ill_w_lg_n1OO0O0i18749w(0) <= NOT n1OO0O0i; + wire_niO01ill_w_lg_n1OO0O0l18747w(0) <= NOT n1OO0O0l; + wire_niO01ill_w_lg_n1OO0OiO18754w(0) <= NOT n1OO0OiO; + wire_niO01ill_w_lg_n1OO0Oli18741w(0) <= NOT n1OO0Oli; + wire_niO01ill_w_lg_n1OO0Oll18752w(0) <= NOT n1OO0Oll; + wire_niO01ill_w_lg_ni00liOi10201w(0) <= NOT ni00liOi; + wire_niO01ill_w_lg_ni00liOl10879w(0) <= NOT ni00liOl; + wire_niO01ill_w_lg_ni00liOO10877w(0) <= NOT ni00liOO; + wire_niO01ill_w_lg_ni00ll1i10876w(0) <= NOT ni00ll1i; + wire_niO01ill_w_lg_ni01lO0O10197w(0) <= NOT ni01lO0O; + wire_niO01ill_w_lg_ni01lOii10960w(0) <= NOT ni01lOii; + wire_niO01ill_w_lg_ni01lOil10958w(0) <= NOT ni01lOil; + wire_niO01ill_w_lg_ni01lOiO10957w(0) <= NOT ni01lOiO; + wire_niO01ill_w_lg_ni0i000i10691w(0) <= NOT ni0i000i; + wire_niO01ill_w_lg_ni0i000l10689w(0) <= NOT ni0i000l; + wire_niO01ill_w_lg_ni0i000O10687w(0) <= NOT ni0i000O; + wire_niO01ill_w_lg_ni0i001i10697w(0) <= NOT ni0i001i; + wire_niO01ill_w_lg_ni0i001l10695w(0) <= NOT ni0i001l; + wire_niO01ill_w_lg_ni0i001O10693w(0) <= NOT ni0i001O; + wire_niO01ill_w_lg_ni0i00ii10685w(0) <= NOT ni0i00ii; + wire_niO01ill_w_lg_ni0i00il10683w(0) <= NOT ni0i00il; + wire_niO01ill_w_lg_ni0i00iO10681w(0) <= NOT ni0i00iO; + wire_niO01ill_w_lg_ni0i00li10679w(0) <= NOT ni0i00li; + wire_niO01ill_w_lg_ni0i00ll10677w(0) <= NOT ni0i00ll; + wire_niO01ill_w_lg_ni0i00lO10675w(0) <= NOT ni0i00lO; + wire_niO01ill_w_lg_ni0i00Oi10673w(0) <= NOT ni0i00Oi; + wire_niO01ill_w_lg_ni0i00Ol10671w(0) <= NOT ni0i00Ol; + wire_niO01ill_w_lg_ni0i00OO10669w(0) <= NOT ni0i00OO; + wire_niO01ill_w_lg_ni0i010i10721w(0) <= NOT ni0i010i; + wire_niO01ill_w_lg_ni0i010l10719w(0) <= NOT ni0i010l; + wire_niO01ill_w_lg_ni0i010O10717w(0) <= NOT ni0i010O; + wire_niO01ill_w_lg_ni0i011i10727w(0) <= NOT ni0i011i; + wire_niO01ill_w_lg_ni0i011l10725w(0) <= NOT ni0i011l; + wire_niO01ill_w_lg_ni0i011O10723w(0) <= NOT ni0i011O; + wire_niO01ill_w_lg_ni0i01ii10715w(0) <= NOT ni0i01ii; + wire_niO01ill_w_lg_ni0i01il10713w(0) <= NOT ni0i01il; + wire_niO01ill_w_lg_ni0i01iO10711w(0) <= NOT ni0i01iO; + wire_niO01ill_w_lg_ni0i01li10709w(0) <= NOT ni0i01li; + wire_niO01ill_w_lg_ni0i01ll10707w(0) <= NOT ni0i01ll; + wire_niO01ill_w_lg_ni0i01lO10705w(0) <= NOT ni0i01lO; + wire_niO01ill_w_lg_ni0i01Oi10703w(0) <= NOT ni0i01Oi; + wire_niO01ill_w_lg_ni0i01Ol10701w(0) <= NOT ni0i01Ol; + wire_niO01ill_w_lg_ni0i01OO10699w(0) <= NOT ni0i01OO; + wire_niO01ill_w_lg_ni0i0i0i10663w(0) <= NOT ni0i0i0i; + wire_niO01ill_w_lg_ni0i0i0l10658w(0) <= NOT ni0i0i0l; + wire_niO01ill_w_lg_ni0i0i0O10123w(0) <= NOT ni0i0i0O; + wire_niO01ill_w_lg_ni0i0i1i10667w(0) <= NOT ni0i0i1i; + wire_niO01ill_w_lg_ni0i0i1l10666w(0) <= NOT ni0i0i1l; + wire_niO01ill_w_lg_ni0i0i1O10661w(0) <= NOT ni0i0i1O; + wire_niO01ill_w_lg_ni0i1i0O10807w(0) <= NOT ni0i1i0O; + wire_niO01ill_w_lg_ni0i1iii10805w(0) <= NOT ni0i1iii; + wire_niO01ill_w_lg_ni0i1iil10803w(0) <= NOT ni0i1iil; + wire_niO01ill_w_lg_ni0i1iiO10801w(0) <= NOT ni0i1iiO; + wire_niO01ill_w_lg_ni0i1ili10799w(0) <= NOT ni0i1ili; + wire_niO01ill_w_lg_ni0i1ill10797w(0) <= NOT ni0i1ill; + wire_niO01ill_w_lg_ni0i1ilO10795w(0) <= NOT ni0i1ilO; + wire_niO01ill_w_lg_ni0i1iOi10794w(0) <= NOT ni0i1iOi; + wire_niO01ill_w_lg_ni0i1iOl10792w(0) <= NOT ni0i1iOl; + wire_niO01ill_w_lg_ni0i1iOO10790w(0) <= NOT ni0i1iOO; + wire_niO01ill_w_lg_ni0i1l0i10782w(0) <= NOT ni0i1l0i; + wire_niO01ill_w_lg_ni0i1l0l10780w(0) <= NOT ni0i1l0l; + wire_niO01ill_w_lg_ni0i1l0O10778w(0) <= NOT ni0i1l0O; + wire_niO01ill_w_lg_ni0i1l1i10788w(0) <= NOT ni0i1l1i; + wire_niO01ill_w_lg_ni0i1l1l10786w(0) <= NOT ni0i1l1l; + wire_niO01ill_w_lg_ni0i1l1O10784w(0) <= NOT ni0i1l1O; + wire_niO01ill_w_lg_ni0i1lii10776w(0) <= NOT ni0i1lii; + wire_niO01ill_w_lg_ni0i1lil10774w(0) <= NOT ni0i1lil; + wire_niO01ill_w_lg_ni0i1liO10772w(0) <= NOT ni0i1liO; + wire_niO01ill_w_lg_ni0i1lli10770w(0) <= NOT ni0i1lli; + wire_niO01ill_w_lg_ni0i1lll10768w(0) <= NOT ni0i1lll; + wire_niO01ill_w_lg_ni0i1llO10765w(0) <= NOT ni0i1llO; + wire_niO01ill_w_lg_ni0i1lOi10763w(0) <= NOT ni0i1lOi; + wire_niO01ill_w_lg_ni0i1lOl10761w(0) <= NOT ni0i1lOl; + wire_niO01ill_w_lg_ni0i1lOO10759w(0) <= NOT ni0i1lOO; + wire_niO01ill_w_lg_ni0i1O0i10751w(0) <= NOT ni0i1O0i; + wire_niO01ill_w_lg_ni0i1O0l10749w(0) <= NOT ni0i1O0l; + wire_niO01ill_w_lg_ni0i1O0O10747w(0) <= NOT ni0i1O0O; + wire_niO01ill_w_lg_ni0i1O1i10757w(0) <= NOT ni0i1O1i; + wire_niO01ill_w_lg_ni0i1O1l10755w(0) <= NOT ni0i1O1l; + wire_niO01ill_w_lg_ni0i1O1O10753w(0) <= NOT ni0i1O1O; + wire_niO01ill_w_lg_ni0i1Oii10745w(0) <= NOT ni0i1Oii; + wire_niO01ill_w_lg_ni0i1Oil10743w(0) <= NOT ni0i1Oil; + wire_niO01ill_w_lg_ni0i1OiO10741w(0) <= NOT ni0i1OiO; + wire_niO01ill_w_lg_ni0i1Oli10739w(0) <= NOT ni0i1Oli; + wire_niO01ill_w_lg_ni0i1Oll10737w(0) <= NOT ni0i1Oll; + wire_niO01ill_w_lg_ni0i1OlO10735w(0) <= NOT ni0i1OlO; + wire_niO01ill_w_lg_ni0i1OOi10733w(0) <= NOT ni0i1OOi; + wire_niO01ill_w_lg_ni0i1OOl10731w(0) <= NOT ni0i1OOl; + wire_niO01ill_w_lg_ni0i1OOO10729w(0) <= NOT ni0i1OOO; + wire_niO01ill_w_lg_ni101i0i11362w(0) <= NOT ni101i0i; + wire_niO01ill_w_lg_ni101i1i10177w(0) <= NOT ni101i1i; + wire_niO01ill_w_lg_ni101i1l11365w(0) <= NOT ni101i1l; + wire_niO01ill_w_lg_ni101i1O11363w(0) <= NOT ni101i1O; + wire_niO01ill_w_lg_ni11100l10646w(0) <= NOT ni11100l; + wire_niO01ill_w_lg_ni11101O10649w(0) <= NOT ni11101O; + wire_niO01ill_w_lg_ni1111Ol10654w(0) <= NOT ni1111Ol; + wire_niO01ill_w_lg_ni1111OO10642w(0) <= NOT ni1111OO; + wire_niO01ill_w_lg_ni111liO10174w(0) <= NOT ni111liO; + wire_niO01ill_w_lg_ni111lli11446w(0) <= NOT ni111lli; + wire_niO01ill_w_lg_ni111lll11444w(0) <= NOT ni111lll; + wire_niO01ill_w_lg_ni111llO11443w(0) <= NOT ni111llO; + wire_niO01ill_w_lg_ni1i11il10181w(0) <= NOT ni1i11il; + wire_niO01ill_w_lg_ni1i11iO11284w(0) <= NOT ni1i11iO; + wire_niO01ill_w_lg_ni1i11li11282w(0) <= NOT ni1i11li; + wire_niO01ill_w_lg_ni1i11ll11281w(0) <= NOT ni1i11ll; + wire_niO01ill_w_lg_ni1iOlOO10185w(0) <= NOT ni1iOlOO; + wire_niO01ill_w_lg_ni1iOO1i11203w(0) <= NOT ni1iOO1i; + wire_niO01ill_w_lg_ni1iOO1l11201w(0) <= NOT ni1iOO1l; + wire_niO01ill_w_lg_ni1iOO1O11200w(0) <= NOT ni1iOO1O; + wire_niO01ill_w_lg_ni1lOiii10189w(0) <= NOT ni1lOiii; + wire_niO01ill_w_lg_ni1lOiil11122w(0) <= NOT ni1lOiil; + wire_niO01ill_w_lg_ni1lOiiO11120w(0) <= NOT ni1lOiiO; + wire_niO01ill_w_lg_ni1lOili11119w(0) <= NOT ni1lOili; + wire_niO01ill_w_lg_ni1OO01i11039w(0) <= NOT ni1OO01i; + wire_niO01ill_w_lg_ni1OO01l11038w(0) <= NOT ni1OO01l; + wire_niO01ill_w_lg_ni1OO1Ol10193w(0) <= NOT ni1OO1Ol; + wire_niO01ill_w_lg_ni1OO1OO11041w(0) <= NOT ni1OO1OO; + wire_niO01ill_w_lg_nii0li1l10110w(0) <= NOT nii0li1l; + wire_niO01ill_w_lg_nii0lllO10097w(0) <= NOT nii0lllO; + wire_niO01ill_w_lg_nii0O1ii10084w(0) <= NOT nii0O1ii; + wire_niO01ill_w_lg_nii0Oi1l10071w(0) <= NOT nii0Oi1l; + wire_niO01ill_w_lg_nii0OllO10058w(0) <= NOT nii0OllO; + wire_niO01ill_w_lg_niii0OOl10595w(0) <= NOT niii0OOl; + wire_niO01ill_w_lg_niii0OOO10593w(0) <= NOT niii0OOO; + wire_niO01ill_w_lg_niii11ii10045w(0) <= NOT niii11ii; + wire_niO01ill_w_lg_niii1i1l10032w(0) <= NOT niii1i1l; + wire_niO01ill_w_lg_niiii00l10531w(0) <= NOT niiii00l; + wire_niO01ill_w_lg_niiii01l10495w(0) <= NOT niiii01l; + wire_niO01ill_w_lg_niiii01O10493w(0) <= NOT niiii01O; + wire_niO01ill_w_lg_niiii0ii10500w(0) <= NOT niiii0ii; + wire_niO01ill_w_lg_niiii0il10487w(0) <= NOT niiii0il; + wire_niO01ill_w_lg_niiii0iO10498w(0) <= NOT niiii0iO; + wire_niO01ill_w_lg_niiii0ll10445w(0) <= NOT niiii0ll; + wire_niO01ill_w_lg_niiii0lO10443w(0) <= NOT niiii0lO; + wire_niO01ill_w_lg_niiii0Ol10481w(0) <= NOT niiii0Ol; + wire_niO01ill_w_lg_niiii10i10600w(0) <= NOT niiii10i; + wire_niO01ill_w_lg_niiii10l10587w(0) <= NOT niiii10l; + wire_niO01ill_w_lg_niiii10O10598w(0) <= NOT niiii10O; + wire_niO01ill_w_lg_niiii11l10631w(0) <= NOT niiii11l; + wire_niO01ill_w_lg_niiii1il10545w(0) <= NOT niiii1il; + wire_niO01ill_w_lg_niiii1iO10543w(0) <= NOT niiii1iO; + wire_niO01ill_w_lg_niiii1ll10581w(0) <= NOT niiii1ll; + wire_niO01ill_w_lg_niiii1Oi10550w(0) <= NOT niiii1Oi; + wire_niO01ill_w_lg_niiii1Ol10537w(0) <= NOT niiii1Ol; + wire_niO01ill_w_lg_niiii1OO10548w(0) <= NOT niiii1OO; + wire_niO01ill_w_lg_niiiii0l10395w(0) <= NOT niiiii0l; + wire_niO01ill_w_lg_niiiii0O10393w(0) <= NOT niiiii0O; + wire_niO01ill_w_lg_niiiii1i10450w(0) <= NOT niiiii1i; + wire_niO01ill_w_lg_niiiii1l10437w(0) <= NOT niiiii1l; + wire_niO01ill_w_lg_niiiii1O10448w(0) <= NOT niiiii1O; + wire_niO01ill_w_lg_niiiiiil10431w(0) <= NOT niiiiiil; + wire_niO01ill_w_lg_niiiiili10400w(0) <= NOT niiiiili; + wire_niO01ill_w_lg_niiiiill10387w(0) <= NOT niiiiill; + wire_niO01ill_w_lg_niiiiilO10398w(0) <= NOT niiiiilO; + wire_niO01ill_w_lg_niiiiiOl10345w(0) <= NOT niiiiiOl; + wire_niO01ill_w_lg_niiiiiOO10343w(0) <= NOT niiiiiOO; + wire_niO01ill_w_lg_niiiil0i10350w(0) <= NOT niiiil0i; + wire_niO01ill_w_lg_niiiil0l10337w(0) <= NOT niiiil0l; + wire_niO01ill_w_lg_niiiil0O10348w(0) <= NOT niiiil0O; + wire_niO01ill_w_lg_niiiil1l10381w(0) <= NOT niiiil1l; + wire_niO01ill_w_lg_niiiilil10295w(0) <= NOT niiiilil; + wire_niO01ill_w_lg_niiiiliO10293w(0) <= NOT niiiiliO; + wire_niO01ill_w_lg_niiiilll10331w(0) <= NOT niiiilll; + wire_niO01ill_w_lg_niiiilOi10300w(0) <= NOT niiiilOi; + wire_niO01ill_w_lg_niiiilOl10287w(0) <= NOT niiiilOl; + wire_niO01ill_w_lg_niiiilOO10298w(0) <= NOT niiiilOO; + wire_niO01ill_w_lg_niiiiO0l10281w(0) <= NOT niiiiO0l; + wire_niO01ill_w_lg_niiiiO1l10245w(0) <= NOT niiiiO1l; + wire_niO01ill_w_lg_niiiiO1O10243w(0) <= NOT niiiiO1O; + wire_niO01ill_w_lg_niiiiOii10250w(0) <= NOT niiiiOii; + wire_niO01ill_w_lg_niiiiOil10237w(0) <= NOT niiiiOil; + wire_niO01ill_w_lg_niiiiOiO10248w(0) <= NOT niiiiOiO; + wire_niO01ill_w_lg_niiiiOli10024w(0) <= NOT niiiiOli; + wire_niO01ill_w_lg_niiiiOll10022w(0) <= NOT niiiiOll; + wire_niO01ill_w_lg_niiiiOlO10020w(0) <= NOT niiiiOlO; + wire_niO01ill_w_lg_niiiiOOi10018w(0) <= NOT niiiiOOi; + wire_niO01ill_w_lg_niiiiOOl10016w(0) <= NOT niiiiOOl; + wire_niO01ill_w_lg_niiiiOOO10014w(0) <= NOT niiiiOOO; + wire_niO01ill_w_lg_niiil11i10012w(0) <= NOT niiil11i; + wire_niO01ill_w_lg_niiil11l10010w(0) <= NOT niiil11l; + wire_niO01ill_w_lg_niil010i18930w(0) <= NOT niil010i; + wire_niO01ill_w_lg_niil010O18772w(0) <= NOT niil010O; + wire_niO01ill_w_lg_niO010ll8775w(0) <= NOT niO010ll; + wire_niO01ill_w_lg_niO011ll8784w(0) <= NOT niO011ll; + wire_niO01ill_w_lg_niO01ilO8766w(0) <= NOT niO01ilO; + wire_niO01ill_w_lg_niOO0O0OO19990w(0) <= NOT niOO0O0OO; + wire_niO01ill_w_lg_niOO0Oi0i20950w(0) <= NOT niOO0Oi0i; + wire_niO01ill_w_lg_niOO0Oi0l21202w(0) <= NOT niOO0Oi0l; + wire_niO01ill_w_lg_niOO0Oi1O20909w(0) <= NOT niOO0Oi1O; + wire_niO01ill_w_lg_niOO0Olii20546w(0) <= NOT niOO0Olii; + wire_niO01ill_w_lg_nlOi001il28841w(0) <= NOT nlOi001il; + wire_niO01ill_w_lg_nlOi00i1l28834w(0) <= NOT nlOi00i1l; + wire_niO01ill_w_lg_nlOi0i10l28824w(0) <= NOT nlOi0i10l; + wire_niO01ill_w_lg_nlOi0lOOi28776w(0) <= NOT nlOi0lOOi; + wire_niO01ill_w_lg_nlOi0O0OO28765w(0) <= NOT nlOi0O0OO; + wire_niO01ill_w_lg_nlOi0OliO28758w(0) <= NOT nlOi0OliO; + wire_niO01ill_w_lg_nlOi0OOli28755w(0) <= NOT nlOi0OOli; + wire_niO01ill_w_lg_nlOii01OO28730w(0) <= NOT nlOii01OO; + wire_niO01ill_w_lg_nlOii0iiO28723w(0) <= NOT nlOii0iiO; + wire_niO01ill_w_lg_nlOii1ilO28744w(0) <= NOT nlOii1ilO; + wire_niO01ill_w_lg_nlOii1O0O28737w(0) <= NOT nlOii1O0O; + wire_niO01ill_w_lg_nlOiii0iO28716w(0) <= NOT nlOiii0iO; + wire_niO01ill_w_lg_nlOiil0il28687w(0) <= NOT nlOiil0il; + wire_niO01ill_w_lg_nlOiiO1iO28670w(0) <= NOT nlOiiO1iO; + wire_niO01ill_w_lg_nlOiiOO1O28650w(0) <= NOT nlOiiOO1O; + wire_niO01ill_w_lg_nlOili1Oi28463w(0) <= NOT nlOili1Oi; + wire_niO01ill_w_lg_nlOill1Ol28335w(0) <= NOT nlOill1Ol; + wire_niO01ill_w_lg_nlOilO0lO28278w(0) <= NOT nlOilO0lO; + wire_niO01ill_w_lg_nlOilOl0O28271w(0) <= NOT nlOilOl0O; + wire_niO01ill_w_lg_nlOilOOOO28264w(0) <= NOT nlOilOOOO; + wire_niO01ill_w_lg_nlOiO101i28260w(0) <= NOT nlOiO101i; + wire_niO01ill_w_lg_nlOiO101l28258w(0) <= NOT nlOiO101l; + wire_niO01ill_w_lg_nlOiOO1ll28114w(0) <= NOT nlOiOO1ll; + wire_niO01ill_w_lg_nlOliiO0i21204w(0) <= NOT nlOliiO0i; + wire_niO01ill_w_lg_nlOliO0ll26842w(0) <= NOT nlOliO0ll; + wire_niO01ill_w_lg_nlOll000i26820w(0) <= NOT nlOll000i; + wire_niO01ill_w_lg_nlOll000l26819w(0) <= NOT nlOll000l; + wire_niO01ill_w_lg_nlOll001i26826w(0) <= NOT nlOll001i; + wire_niO01ill_w_lg_nlOll001l26824w(0) <= NOT nlOll001l; + wire_niO01ill_w_lg_nlOll001O26822w(0) <= NOT nlOll001O; + wire_niO01ill_w_lg_nlOll01iO26840w(0) <= NOT nlOll01iO; + wire_niO01ill_w_lg_nlOll01li26838w(0) <= NOT nlOll01li; + wire_niO01ill_w_lg_nlOll01ll26836w(0) <= NOT nlOll01ll; + wire_niO01ill_w_lg_nlOll01lO26834w(0) <= NOT nlOll01lO; + wire_niO01ill_w_lg_nlOll01Oi26832w(0) <= NOT nlOll01Oi; + wire_niO01ill_w_lg_nlOll01Ol26830w(0) <= NOT nlOll01Ol; + wire_niO01ill_w_lg_nlOll01OO26828w(0) <= NOT nlOll01OO; + wire_niO01ill_w_lg_nlOll0O0i19983w(0) <= NOT nlOll0O0i; + wire_niO01ill_w_lg_nlOll0O0O21039w(0) <= NOT nlOll0O0O; + wire_niO01ill_w_lg_nlOlliO1i27864w(0) <= NOT nlOlliO1i; + wire_niO01ill_w_lg_nlOlliO1l27862w(0) <= NOT nlOlliO1l; + wire_niO01ill_w_lg_nlOlliOlO27861w(0) <= NOT nlOlliOlO; + wire_niO01ill_w_lg_nlOllll0l19981w(0) <= NOT nlOllll0l; + wire_niO01ill_w_lg_nlOllll0O19982w(0) <= NOT nlOllll0O; + wire_niO01ill_w_lg_nlOllO0iO17973w(0) <= NOT nlOllO0iO; + wire_niO01ill_w_lg_nlOllOliO17066w(0) <= NOT nlOllOliO; + wire_niO01ill_w_lg_nlOllOlli16159w(0) <= NOT nlOllOlli; + wire_niO01ill_w_lg_nlOllOlll15252w(0) <= NOT nlOllOlll; + wire_niO01ill_w_lg_nlOllOllO14345w(0) <= NOT nlOllOllO; + wire_niO01ill_w_lg_nlOllOlOi13438w(0) <= NOT nlOllOlOi; + wire_niO01ill_w_lg_nlOllOlOl12531w(0) <= NOT nlOllOlOl; + wire_niO01ill_w_lg_nlOllOlOO11619w(0) <= NOT nlOllOlOO; + wire_niO01ill_w_lg_nlOlO010i8774w(0) <= NOT nlOlO010i; + wire_niO01ill_w_lg_nlOlO010l8783w(0) <= NOT nlOlO010l; + wire_niO01ill_w_lg_nlOlO011i8765w(0) <= NOT nlOlO011i; + wire_niO01ill_w_lg_nlOlO1l0i24728w(0) <= NOT nlOlO1l0i; + wire_niO01ill_w_lg_nlOlOi00l27726w(0) <= NOT nlOlOi00l; + wire_niO01ill_w_lg_nlOlOil0i27714w(0) <= NOT nlOlOil0i; + wire_niO01ill_w_lg_nlOlOil0l27712w(0) <= NOT nlOlOil0l; + wire_niO01ill_w_lg_nlOlOil0O27710w(0) <= NOT nlOlOil0O; + wire_niO01ill_w_lg_nlOlOil1i27724w(0) <= NOT nlOlOil1i; + wire_niO01ill_w_lg_nlOlOil1l27722w(0) <= NOT nlOlOil1l; + wire_niO01ill_w_lg_nlOlOil1O27720w(0) <= NOT nlOlOil1O; + wire_niO01ill_w_lg_nlOlOilii27709w(0) <= NOT nlOlOilii; + wire_niO01ill_w_lg_nlOlOiliO21217w(0) <= NOT nlOlOiliO; + wire_niO01ill_w_lg_nlOlOilli24721w(0) <= NOT nlOlOilli; + wire_niO01ill_w_lg_nlOlOilOl24719w(0) <= NOT nlOlOilOl; + wire_niO01ill_w_lg_nlOlOiO1i24684w(0) <= NOT nlOlOiO1i; + wire_niO01ill_w_lg_nlOO0000i26383w(0) <= NOT nlOO0000i; + wire_niO01ill_w_lg_nlOO0000l26381w(0) <= NOT nlOO0000l; + wire_niO01ill_w_lg_nlOO0000O26379w(0) <= NOT nlOO0000O; + wire_niO01ill_w_lg_nlOO0001O26385w(0) <= NOT nlOO0001O; + wire_niO01ill_w_lg_nlOO000ii26377w(0) <= NOT nlOO000ii; + wire_niO01ill_w_lg_nlOO000il26375w(0) <= NOT nlOO000il; + wire_niO01ill_w_lg_nlOO000iO26373w(0) <= NOT nlOO000iO; + wire_niO01ill_w_lg_nlOO000li26372w(0) <= NOT nlOO000li; + wire_niO01ill_w_lg_nlOO000ll25261w(0) <= NOT nlOO000ll; + wire_niO01ill_w_lg_nlOO000lO25259w(0) <= NOT nlOO000lO; + wire_niO01ill_w_lg_nlOO000Oi25257w(0) <= NOT nlOO000Oi; + wire_niO01ill_w_lg_nlOO000Ol25255w(0) <= NOT nlOO000Ol; + wire_niO01ill_w_lg_nlOO000OO25253w(0) <= NOT nlOO000OO; + wire_niO01ill_w_lg_nlOO00i0i26584w(0) <= NOT nlOO00i0i; + wire_niO01ill_w_lg_nlOO00i0l26582w(0) <= NOT nlOO00i0l; + wire_niO01ill_w_lg_nlOO00i0O26580w(0) <= NOT nlOO00i0O; + wire_niO01ill_w_lg_nlOO00i1i25251w(0) <= NOT nlOO00i1i; + wire_niO01ill_w_lg_nlOO00i1l25249w(0) <= NOT nlOO00i1l; + wire_niO01ill_w_lg_nlOO00i1O25248w(0) <= NOT nlOO00i1O; + wire_niO01ill_w_lg_nlOO00iii26578w(0) <= NOT nlOO00iii; + wire_niO01ill_w_lg_nlOO00iil26576w(0) <= NOT nlOO00iil; + wire_niO01ill_w_lg_nlOO00iiO26574w(0) <= NOT nlOO00iiO; + wire_niO01ill_w_lg_nlOO00ili26572w(0) <= NOT nlOO00ili; + wire_niO01ill_w_lg_nlOO00ill26571w(0) <= NOT nlOO00ill; + wire_niO01ill_w_lg_nlOO00ilO25943w(0) <= NOT nlOO00ilO; + wire_niO01ill_w_lg_nlOO00iOi25941w(0) <= NOT nlOO00iOi; + wire_niO01ill_w_lg_nlOO00iOl25939w(0) <= NOT nlOO00iOl; + wire_niO01ill_w_lg_nlOO00iOO25937w(0) <= NOT nlOO00iOO; + wire_niO01ill_w_lg_nlOO00l0i25930w(0) <= NOT nlOO00l0i; + wire_niO01ill_w_lg_nlOO00l0l26942w(0) <= NOT nlOO00l0l; + wire_niO01ill_w_lg_nlOO00l0O26940w(0) <= NOT nlOO00l0O; + wire_niO01ill_w_lg_nlOO00l1i25935w(0) <= NOT nlOO00l1i; + wire_niO01ill_w_lg_nlOO00l1l25933w(0) <= NOT nlOO00l1l; + wire_niO01ill_w_lg_nlOO00l1O25931w(0) <= NOT nlOO00l1O; + wire_niO01ill_w_lg_nlOO00lii26938w(0) <= NOT nlOO00lii; + wire_niO01ill_w_lg_nlOO00lil26936w(0) <= NOT nlOO00lil; + wire_niO01ill_w_lg_nlOO00liO26934w(0) <= NOT nlOO00liO; + wire_niO01ill_w_lg_nlOO00lli26932w(0) <= NOT nlOO00lli; + wire_niO01ill_w_lg_nlOO00lll26930w(0) <= NOT nlOO00lll; + wire_niO01ill_w_lg_nlOO00llO26929w(0) <= NOT nlOO00llO; + wire_niO01ill_w_lg_nlOO00O0O25882w(0) <= NOT nlOO00O0O; + wire_niO01ill_w_lg_nlOO00Oii25880w(0) <= NOT nlOO00Oii; + wire_niO01ill_w_lg_nlOO00Oil25878w(0) <= NOT nlOO00Oil; + wire_niO01ill_w_lg_nlOO00OiO25876w(0) <= NOT nlOO00OiO; + wire_niO01ill_w_lg_nlOO00Oli25874w(0) <= NOT nlOO00Oli; + wire_niO01ill_w_lg_nlOO00Oll25872w(0) <= NOT nlOO00Oll; + wire_niO01ill_w_lg_nlOO00OlO25870w(0) <= NOT nlOO00OlO; + wire_niO01ill_w_lg_nlOO00OOi25869w(0) <= NOT nlOO00OOi; + wire_niO01ill_w_lg_nlOO00OOl26461w(0) <= NOT nlOO00OOl; + wire_niO01ill_w_lg_nlOO00OOO26459w(0) <= NOT nlOO00OOO; + wire_niO01ill_w_lg_nlOO0100l25731w(0) <= NOT nlOO0100l; + wire_niO01ill_w_lg_nlOO0100O25729w(0) <= NOT nlOO0100O; + wire_niO01ill_w_lg_nlOO010ii25727w(0) <= NOT nlOO010ii; + wire_niO01ill_w_lg_nlOO010il25725w(0) <= NOT nlOO010il; + wire_niO01ill_w_lg_nlOO010iO25723w(0) <= NOT nlOO010iO; + wire_niO01ill_w_lg_nlOO010li25721w(0) <= NOT nlOO010li; + wire_niO01ill_w_lg_nlOO010ll25720w(0) <= NOT nlOO010ll; + wire_niO01ill_w_lg_nlOO010lO25794w(0) <= NOT nlOO010lO; + wire_niO01ill_w_lg_nlOO010Oi25792w(0) <= NOT nlOO010Oi; + wire_niO01ill_w_lg_nlOO010Ol25790w(0) <= NOT nlOO010Ol; + wire_niO01ill_w_lg_nlOO010OO25788w(0) <= NOT nlOO010OO; + wire_niO01ill_w_lg_nlOO01i0i25781w(0) <= NOT nlOO01i0i; + wire_niO01ill_w_lg_nlOO01i1i25786w(0) <= NOT nlOO01i1i; + wire_niO01ill_w_lg_nlOO01i1l25784w(0) <= NOT nlOO01i1l; + wire_niO01ill_w_lg_nlOO01i1O25782w(0) <= NOT nlOO01i1O; + wire_niO01ill_w_lg_nlOO01iOi26143w(0) <= NOT nlOO01iOi; + wire_niO01ill_w_lg_nlOO01iOl26141w(0) <= NOT nlOO01iOl; + wire_niO01ill_w_lg_nlOO01iOO26139w(0) <= NOT nlOO01iOO; + wire_niO01ill_w_lg_nlOO01l0i26131w(0) <= NOT nlOO01l0i; + wire_niO01ill_w_lg_nlOO01l0l26130w(0) <= NOT nlOO01l0l; + wire_niO01ill_w_lg_nlOO01l0O25618w(0) <= NOT nlOO01l0O; + wire_niO01ill_w_lg_nlOO01l1i26137w(0) <= NOT nlOO01l1i; + wire_niO01ill_w_lg_nlOO01l1l26135w(0) <= NOT nlOO01l1l; + wire_niO01ill_w_lg_nlOO01l1O26133w(0) <= NOT nlOO01l1O; + wire_niO01ill_w_lg_nlOO01lii25616w(0) <= NOT nlOO01lii; + wire_niO01ill_w_lg_nlOO01lil25614w(0) <= NOT nlOO01lil; + wire_niO01ill_w_lg_nlOO01liO25612w(0) <= NOT nlOO01liO; + wire_niO01ill_w_lg_nlOO01lli25610w(0) <= NOT nlOO01lli; + wire_niO01ill_w_lg_nlOO01lll25608w(0) <= NOT nlOO01lll; + wire_niO01ill_w_lg_nlOO01llO25606w(0) <= NOT nlOO01llO; + wire_niO01ill_w_lg_nlOO01lOi25605w(0) <= NOT nlOO01lOi; + wire_niO01ill_w_lg_nlOO0i00i25238w(0) <= NOT nlOO0i00i; + wire_niO01ill_w_lg_nlOO0i00l25236w(0) <= NOT nlOO0i00l; + wire_niO01ill_w_lg_nlOO0i00O25234w(0) <= NOT nlOO0i00O; + wire_niO01ill_w_lg_nlOO0i01i25244w(0) <= NOT nlOO0i01i; + wire_niO01ill_w_lg_nlOO0i01l25242w(0) <= NOT nlOO0i01l; + wire_niO01ill_w_lg_nlOO0i01O25240w(0) <= NOT nlOO0i01O; + wire_niO01ill_w_lg_nlOO0i0ii25233w(0) <= NOT nlOO0i0ii; + wire_niO01ill_w_lg_nlOO0i0il26316w(0) <= NOT nlOO0i0il; + wire_niO01ill_w_lg_nlOO0i0iO26314w(0) <= NOT nlOO0i0iO; + wire_niO01ill_w_lg_nlOO0i0li26312w(0) <= NOT nlOO0i0li; + wire_niO01ill_w_lg_nlOO0i0ll26310w(0) <= NOT nlOO0i0ll; + wire_niO01ill_w_lg_nlOO0i0lO26308w(0) <= NOT nlOO0i0lO; + wire_niO01ill_w_lg_nlOO0i0Oi26306w(0) <= NOT nlOO0i0Oi; + wire_niO01ill_w_lg_nlOO0i0Ol26304w(0) <= NOT nlOO0i0Ol; + wire_niO01ill_w_lg_nlOO0i0OO26303w(0) <= NOT nlOO0i0OO; + wire_niO01ill_w_lg_nlOO0i10i26451w(0) <= NOT nlOO0i10i; + wire_niO01ill_w_lg_nlOO0i10l26449w(0) <= NOT nlOO0i10l; + wire_niO01ill_w_lg_nlOO0i10O26448w(0) <= NOT nlOO0i10O; + wire_niO01ill_w_lg_nlOO0i11i26457w(0) <= NOT nlOO0i11i; + wire_niO01ill_w_lg_nlOO0i11l26455w(0) <= NOT nlOO0i11l; + wire_niO01ill_w_lg_nlOO0i11O26453w(0) <= NOT nlOO0i11O; + wire_niO01ill_w_lg_nlOO0i1OO25246w(0) <= NOT nlOO0i1OO; + wire_niO01ill_w_lg_nlOO0iilO20976w(0) <= NOT nlOO0iilO; + wire_niO01ill_w_lg_nlOO0iiOi20978w(0) <= NOT nlOO0iiOi; + wire_niO01ill_w_lg_nlOO0iiOl25834w(0) <= NOT nlOO0iiOl; + wire_niO01ill_w_lg_nlOO0iiOO20980w(0) <= NOT nlOO0iiOO; + wire_niO01ill_w_lg_nlOO0il0i20982w(0) <= NOT nlOO0il0i; + wire_niO01ill_w_lg_nlOO0il0l25276w(0) <= NOT nlOO0il0l; + wire_niO01ill_w_lg_nlOO0il0O25274w(0) <= NOT nlOO0il0O; + wire_niO01ill_w_lg_nlOO0il1i25831w(0) <= NOT nlOO0il1i; + wire_niO01ill_w_lg_nlOO0il1l25829w(0) <= NOT nlOO0il1l; + wire_niO01ill_w_lg_nlOO0il1O25827w(0) <= NOT nlOO0il1O; + wire_niO01ill_w_lg_nlOO0ilii25272w(0) <= NOT nlOO0ilii; + wire_niO01ill_w_lg_nlOO0ilil25270w(0) <= NOT nlOO0ilil; + wire_niO01ill_w_lg_nlOO0iliO25268w(0) <= NOT nlOO0iliO; + wire_niO01ill_w_lg_nlOO0illi25266w(0) <= NOT nlOO0illi; + wire_niO01ill_w_lg_nlOO0illl25264w(0) <= NOT nlOO0illl; + wire_niO01ill_w_lg_nlOO0illO25263w(0) <= NOT nlOO0illO; + wire_niO01ill_w_lg_nlOO1i1Oi27602w(0) <= NOT nlOO1i1Oi; + wire_niO01ill_w_lg_nlOO1O10O27600w(0) <= NOT nlOO1O10O; + wire_niO01ill_w_lg_nlOO1O1ii27598w(0) <= NOT nlOO1O1ii; + wire_niO01ill_w_lg_nlOO1O1il27596w(0) <= NOT nlOO1O1il; + wire_niO01ill_w_lg_nlOO1O1iO27594w(0) <= NOT nlOO1O1iO; + wire_niO01ill_w_lg_nlOO1O1li27592w(0) <= NOT nlOO1O1li; + wire_niO01ill_w_lg_nlOO1O1ll27590w(0) <= NOT nlOO1O1ll; + wire_niO01ill_w_lg_nlOO1O1lO27589w(0) <= NOT nlOO1O1lO; + wire_niO01ill_w_lg_nlOO1O1Ol24778w(0) <= NOT nlOO1O1Ol; + wire_niO01ill_w_lg_nlOO1O1OO25733w(0) <= NOT nlOO1O1OO; + wire_niO01ill_w_lg_nlOOOiO0i25744w(0) <= NOT nlOOOiO0i; + wire_niO01ill_w_lg_nlOOOiO0l25742w(0) <= NOT nlOOOiO0l; + wire_niO01ill_w_lg_nlOOOiO0O25740w(0) <= NOT nlOOOiO0O; + wire_niO01ill_w_lg_nlOOOiO1l25748w(0) <= NOT nlOOOiO1l; + wire_niO01ill_w_lg_nlOOOiO1O25746w(0) <= NOT nlOOOiO1O; + wire_niO01ill_w_lg_nlOOOiOii25738w(0) <= NOT nlOOOiOii; + wire_niO01ill_w_lg_nlOOOiOil25736w(0) <= NOT nlOOOiOil; + wire_niO01ill_w_lg_nlOOOiOiO25735w(0) <= NOT nlOOOiOiO; + wire_niO01ill_w_lg_nlOOOl00i21006w(0) <= NOT nlOOOl00i; + wire_niO01ill_w_lg_nlOOOl01i24772w(0) <= NOT nlOOOl01i; + wire_niO01ill_w_lg_nlOOOl01l24771w(0) <= NOT nlOOOl01l; + wire_niO01ill_w_lg_nlOOOl01O24770w(0) <= NOT nlOOOl01O; + wire_niO01ill_w_lg_nlOOOl1ll24777w(0) <= NOT nlOOOl1ll; + wire_niO01ill_w_lg_nlOOOl1lO24776w(0) <= NOT nlOOOl1lO; + wire_niO01ill_w_lg_nlOOOl1Oi24775w(0) <= NOT nlOOOl1Oi; + wire_niO01ill_w_lg_nlOOOl1Ol24774w(0) <= NOT nlOOOl1Ol; + wire_niO01ill_w_lg_nlOOOl1OO24773w(0) <= NOT nlOOOl1OO; + wire_niO01ill_w_lg_w_lg_n11O1O1O20986w20987w(0) <= wire_niO01ill_w_lg_n11O1O1O20986w(0) OR niOl0il0O; + wire_niO01ill_w_lg_w_lg_n111i00i9978w10081w(0) <= wire_niO01ill_w_lg_n111i00i9978w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_n111i00l9976w10094w(0) <= wire_niO01ill_w_lg_n111i00l9976w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_n111i00O9974w10107w(0) <= wire_niO01ill_w_lg_n111i00O9974w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_n111i01i9990w10042w(0) <= wire_niO01ill_w_lg_n111i01i9990w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_n111i01l9986w10055w(0) <= wire_niO01ill_w_lg_n111i01l9986w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_n111i01O9984w10068w(0) <= wire_niO01ill_w_lg_n111i01O9984w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_n111i0ii9973w10120w(0) <= wire_niO01ill_w_lg_n111i0ii9973w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_n111i1OO10028w10029w(0) <= wire_niO01ill_w_lg_n111i1OO10028w(0) OR niOlOOl0l; + wire_niO01ill_w_lg_w_lg_niiiiOli10024w10122w(0) <= wire_niO01ill_w_lg_niiiiOli10024w(0) OR niii1Oll; + wire_niO01ill_w_lg_w_lg_niiiiOll10022w10109w(0) <= wire_niO01ill_w_lg_niiiiOll10022w(0) OR niii1Oli; + wire_niO01ill_w_lg_w_lg_niiiiOlO10020w10096w(0) <= wire_niO01ill_w_lg_niiiiOlO10020w(0) OR niii1OiO; + wire_niO01ill_w_lg_w_lg_niiiiOOi10018w10083w(0) <= wire_niO01ill_w_lg_niiiiOOi10018w(0) OR niii1Oil; + wire_niO01ill_w_lg_w_lg_niiiiOOl10016w10070w(0) <= wire_niO01ill_w_lg_niiiiOOl10016w(0) OR niii1Oii; + wire_niO01ill_w_lg_w_lg_niiiiOOO10014w10057w(0) <= wire_niO01ill_w_lg_niiiiOOO10014w(0) OR niii1O0O; + wire_niO01ill_w_lg_w_lg_niiil11i10012w10044w(0) <= wire_niO01ill_w_lg_niiil11i10012w(0) OR niii1O0l; + wire_niO01ill_w_lg_w_lg_niiil11l10010w10031w(0) <= wire_niO01ill_w_lg_niiil11l10010w(0) OR niii1llO; + wire_niO01ill_w_lg_w_lg_w_lg_n11O0O0O22889w22890w22891w(0) <= wire_niO01ill_w_lg_w_lg_n11O0O0O22889w22890w(0) OR n11O0l0O; + wire_niO01ill_w_lg_w_lg_n11O0O0O22889w22890w(0) <= wire_niO01ill_w_lg_n11O0O0O22889w(0) OR n11O0llO; + wire_niO01ill_w_lg_w_lg_n1lilO0l19027w19028w(0) <= wire_niO01ill_w_lg_n1lilO0l19027w(0) OR n1lillOl; + wire_niO01ill_w_lg_w_lg_n1lOi01l18853w18854w(0) <= wire_niO01ill_w_lg_n1lOi01l18853w(0) OR n1lOi1OO; + wire_niO01ill_w_lg_w_lg_n1lOi01O18871w18872w(0) <= wire_niO01ill_w_lg_n1lOi01O18871w(0) OR n1lOi1OO; + wire_niO01ill_w_lg_w_lg_n1lOi01O18792w18888w(0) <= wire_niO01ill_w_lg_n1lOi01O18792w(0) OR n1lOi1OO; + wire_niO01ill_w_lg_n11O0iOl23838w(0) <= n11O0iOl OR wire_niO01ill_w_lg_n11O0iOO23837w(0); + wire_niO01ill_w_lg_n11O0iOO23837w(0) <= n11O0iOO OR wire_niO01iOi_w_lg_n11O0Oil23836w(0); + wire_niO01ill_w_lg_n11O0l0l23097w(0) <= n11O0l0l OR n11O0l0i; + wire_niO01ill_w_lg_n11O0O0O22889w(0) <= n11O0O0O OR n11O0O0i; + wire_niO01ill_w_lg_n11Oi01i24741w(0) <= n11Oi01i OR wire_niO01ill_w_lg_n11Oi11l24740w(0); + wire_niO01ill_w_lg_n11Oi10i24739w(0) <= n11Oi10i OR wire_niO01ill_w_lg_n11Oi1ii24738w(0); + wire_niO01ill_w_lg_n11Oi11l24740w(0) <= n11Oi11l OR wire_niO01ill_w_lg_n11Oi10i24739w(0); + wire_niO01ill_w_lg_n11Oi1ii24738w(0) <= n11Oi1ii OR wire_niO01ill_w_lg_n11Oi1li24737w(0); + wire_niO01ill_w_lg_n11Oi1il24747w(0) <= n11Oi1il OR wire_niO01ill_w_lg_n11Oi1ll24746w(0); + wire_niO01ill_w_lg_n11Oi1li24737w(0) <= n11Oi1li OR n11Oi1iO; + wire_niO01ill_w_lg_n11Oi1ll24746w(0) <= n11Oi1ll OR wire_niO01ill_w_lg_n11Oi1lO24745w(0); + wire_niO01ill_w_lg_n11Oi1lO24745w(0) <= n11Oi1lO OR wire_niO01ill_w_lg_n11Oi1Oi24744w(0); + wire_niO01ill_w_lg_n11Oi1Oi24744w(0) <= n11Oi1Oi OR wire_niO01ill_w_lg_n11Oi1Ol24743w(0); + wire_niO01ill_w_lg_n11Oi1Ol24743w(0) <= n11Oi1Ol OR wire_niO01ill_w_lg_n11Oi1OO24742w(0); + wire_niO01ill_w_lg_n11Oi1OO24742w(0) <= n11Oi1OO OR wire_niO01ill_w_lg_n11Oi01i24741w(0); + wire_niO01ill_w_lg_n1iilliO21209w(0) <= n1iilliO OR wire_niO01ill_w_lg_n1110Oii21198w(0); + wire_niO01ill_w_lg_n1lillOO19215w(0) <= n1lillOO OR n1lillOl; + wire_niO01ill_w_lg_n1lilO0l19027w(0) <= n1lilO0l OR n1lillOO; + wire_niO01ill_w_lg_n1lilO0l18986w(0) <= n1lilO0l OR n1lilO1i; + wire_niO01ill_w_lg_n1lOi01l18853w(0) <= n1lOi01l OR n1lOi01i; + wire_niO01ill_w_lg_n1lOi01O18871w(0) <= n1lOi01O OR n1lOi01i; + wire_niO01ill_w_lg_n1lOi01O18792w(0) <= n1lOi01O OR n1lOi01l; + wire_niO01ill_w_lg_niOO0Oi0i20918w(0) <= niOO0Oi0i OR wire_w_lg_w20916w20917w(0); + wire_niO01ill_w_lg_niOO0Oi1l20901w(0) <= niOO0Oi1l OR wire_w_lg_w_lg_w_lg_niOl0Oiii20898w20899w20900w(0); + wire_niO01ill_w_lg_niOO0Oi1O20952w(0) <= niOO0Oi1O OR wire_niO01ill_w_lg_niOO0Oi1l20951w(0); + wire_niO01ill_w_lg_nlOO1O1Ol24590w(0) <= nlOO1O1Ol OR wire_w_lg_niOl1l11i24589w(0); + wire_niO01ill_w_lg_w_lg_nlOlO010i8774w8777w(0) <= wire_niO01ill_w_lg_nlOlO010i8774w(0) XOR niO010lO; + wire_niO01ill_w_lg_w_lg_nlOlO010l8783w8786w(0) <= wire_niO01ill_w_lg_nlOlO010l8783w(0) XOR niO011lO; + wire_niO01ill_w_lg_w_lg_nlOlO011i8765w8768w(0) <= wire_niO01ill_w_lg_nlOlO011i8765w(0) XOR niO01iOl; + wire_niO01ill_w_lg_n00l0lOl15587w(0) <= n00l0lOl XOR n00iO10O; + wire_niO01ill_w_lg_n00l0Oil15591w(0) <= n00l0Oil XOR n00iO1OO; + wire_niO01ill_w_lg_n0100i0O17401w(0) <= n0100i0O XOR n011llOi; + wire_niO01ill_w_lg_n0100iOO17405w(0) <= n0100iOO XOR n011lOii; + wire_niO01ill_w_lg_n01OO00i16498w(0) <= n01OO00i XOR n01O0ill; + wire_niO01ill_w_lg_n01OO1li16494w(0) <= n01OO1li XOR n01O0i1l; + wire_niO01ill_w_lg_n0i0Oi1O14680w(0) <= n0i0Oi1O XOR n0i00lli; + wire_niO01ill_w_lg_n0i0OilO14684w(0) <= n0i0OilO XOR n0i00O0i; + wire_niO01ill_w_lg_n0l1i01i13777w(0) <= n0l1i01i XOR n0iOOiil; + wire_niO01ill_w_lg_n0l1i1ii13773w(0) <= n0l1i1ii XOR n0iOO0Ol; + wire_niO01ill_w_lg_n0llOlll12866w(0) <= n0llOlll XOR n0lli11O; + wire_niO01ill_w_lg_n0llOO0l12870w(0) <= n0llOO0l XOR n0lli1lO; + wire_niO01ill_w_lg_n0Oii0OO11955w(0) <= n0Oii0OO XOR n0O0Olii; + wire_niO01ill_w_lg_n0OiiiiO11959w(0) <= n0OiiiiO XOR n0O0OO1i; + wire_niO01ill_w_lg_n1OilO1l18308w(0) <= n1OilO1l XOR n1Oi01iO; + wire_niO01ill_w_lg_n1OilOll18312w(0) <= n1OilOll XOR n1Oi001O; + wire_niO01ill_w_lg_nlOliO00i25133w(0) <= nlOliO00i XOR n011ll0O; + wire_niO01ill_w_lg_nlOliO00l25136w(0) <= nlOliO00l XOR n011llii; + wire_niO01ill_w_lg_nlOliO01i25113w(0) <= nlOliO01i XOR n01O00li; + wire_niO01ill_w_lg_nlOliO01l25116w(0) <= nlOliO01l XOR n01O00ll; + wire_niO01ill_w_lg_nlOliO0ii25123w(0) <= nlOliO0ii XOR n1Oi011l; + wire_niO01ill_w_lg_nlOliO0il25126w(0) <= nlOliO0il XOR n1Oi011O; + wire_niO01ill_w_lg_nlOliO10i25073w(0) <= nlOliO10i XOR n0ll0Oll; + wire_niO01ill_w_lg_nlOliO10l25076w(0) <= nlOliO10l XOR n0ll0OlO; + wire_niO01ill_w_lg_nlOliO11i25063w(0) <= nlOliO11i XOR n0O0OiOO; + wire_niO01ill_w_lg_nlOliO11l25066w(0) <= nlOliO11l XOR n0O0Ol1i; + wire_niO01ill_w_lg_nlOliO1ii25083w(0) <= nlOliO1ii XOR n0iOO0ii; + wire_niO01ill_w_lg_nlOliO1il25086w(0) <= nlOliO1il XOR n0iOO0il; + wire_niO01ill_w_lg_nlOliO1li25093w(0) <= nlOliO1li XOR n0i00l1O; + wire_niO01ill_w_lg_nlOliO1ll25096w(0) <= nlOliO1ll XOR n0i00l0i; + wire_niO01ill_w_lg_nlOliO1Oi25103w(0) <= nlOliO1Oi XOR n00ilOOl; + wire_niO01ill_w_lg_nlOliO1Ol25106w(0) <= nlOliO1Ol XOR n00ilOOO; + PROCESS (phy_clk, wire_niO001iO_dataout) + BEGIN + IF (wire_niO001iO_dataout = '0') THEN + n001i1ii <= '1'; + n00il1ll <= '1'; + n00il1lO <= '1'; + n00il1Oi <= '1'; + n00il1Ol <= '1'; + n00l0OiO <= '1'; + n00l0Oli <= '1'; + n00l0Oll <= '1'; + n00l0OlO <= '1'; + n00lOlll <= '1'; + n0100l0i <= '1'; + n0100l1i <= '1'; + n0100l1l <= '1'; + n0100l1O <= '1'; + n010Oi1O <= '1'; + n011iO0i <= '1'; + n011iO0l <= '1'; + n011iO0O <= '1'; + n011iO1O <= '1'; + n01O1iii <= '1'; + n01O1iil <= '1'; + n01O1iiO <= '1'; + n01O1ili <= '1'; + n01OO00l <= '1'; + n01OO00O <= '1'; + n01OO0ii <= '1'; + n01OO0il <= '1'; + n0i01lOO <= '1'; + n0i01O1i <= '1'; + n0i01O1l <= '1'; + n0i01O1O <= '1'; + n0i0OiOi <= '1'; + n0i0OiOl <= '1'; + n0i0OiOO <= '1'; + n0i0Ol1i <= '1'; + n0iii0OO <= '1'; + n0iOli0i <= '1'; + n0iOli0l <= '1'; + n0iOli0O <= '1'; + n0iOliii <= '1'; + n0l0110i <= '1'; + n0l1i00i <= '1'; + n0l1i00l <= '1'; + n0l1i01l <= '1'; + n0l1i01O <= '1'; + n0ll01il <= '1'; + n0ll01iO <= '1'; + n0ll01li <= '1'; + n0ll01ll <= '1'; + n0llOO0O <= '1'; + n0llOOii <= '1'; + n0llOOil <= '1'; + n0llOOiO <= '1'; + n0lOilil <= '1'; + n0O0lllO <= '1'; + n0O0llOi <= '1'; + n0O0llOl <= '1'; + n0O0llOO <= '1'; + n0Oiiili <= '1'; + n0Oiiill <= '1'; + n0OiiilO <= '1'; + n0OiiiOi <= '1'; + n0Ol10lO <= '1'; + n11i110i <= '1'; + n11l0O0O <= '1'; + n11li1iO <= '1'; + n11O010l <= '1'; + n11O0i0l <= '1'; + n11O0i1l <= '1'; + n11O0iii <= '1'; + n11O0iiO <= '1'; + n11O0Oil <= '1'; + n11Oi00O <= '1'; + n1il11Ol <= '1'; + n1l1OO0l <= '1'; + n1l1OOil <= '1'; + n1l1OOli <= '1'; + n1l1OOOi <= '1'; + n1lililO <= '1'; + n1lilO0O <= '1'; + n1lOi0ii <= '1'; + n1Oi101i <= '1'; + n1Oi101l <= '1'; + n1Oi11Ol <= '1'; + n1Oi11OO <= '1'; + n1OilOlO <= '1'; + n1OilOOi <= '1'; + n1OilOOl <= '1'; + n1OilOOO <= '1'; + n1Ol0lOl <= '1'; + niO010lO <= '1'; + niO011lO <= '1'; + niO01iOl <= '1'; + nlOill00i <= '1'; + nlOill01i <= '1'; + nlOill1OO <= '1'; + nlOiO10Ol <= '1'; + nlOiOO1lO <= '1'; + nlOlil10O <= '1'; + nlOliO00O <= '1'; + nlOliO01O <= '1'; + nlOliO0iO <= '1'; + nlOliO10O <= '1'; + nlOliO11O <= '1'; + nlOliO1iO <= '1'; + nlOliO1lO <= '1'; + nlOliO1OO <= '1'; + nlOll0Oii <= '1'; + nlOllllii <= '1'; + nlOlOilll <= '1'; + nlOlOilOO <= '1'; + ELSIF (phy_clk = '1' AND phy_clk'event) THEN + n001i1ii <= wire_n001iOil_dataout; + n00il1ll <= wire_n00il01O_dataout; + n00il1lO <= wire_n00il00i_dataout; + n00il1Oi <= wire_n00il00l_dataout; + n00il1Ol <= wire_n00il00O_dataout; + n00l0OiO <= wire_n00liiil_dataout; + n00l0Oli <= wire_n00liiiO_dataout; + n00l0Oll <= wire_n00liili_dataout; + n00l0OlO <= wire_n00liill_dataout; + n00lOlll <= wire_n00O1ilO_dataout; + n0100l0i <= wire_n010i01O_dataout; + n0100l1i <= wire_n010i1OO_dataout; + n0100l1l <= wire_n010i01i_dataout; + n0100l1O <= wire_n010i01l_dataout; + n010Oi1O <= wire_n01i100i_dataout; + n011iO0i <= wire_n011iOll_dataout; + n011iO0l <= wire_n011iOlO_dataout; + n011iO0O <= wire_n011iOOi_dataout; + n011iO1O <= wire_n011iOli_dataout; + n01O1iii <= wire_n01O1iOl_dataout; + n01O1iil <= wire_n01O1iOO_dataout; + n01O1iiO <= wire_n01O1l1i_dataout; + n01O1ili <= wire_n01O1l1l_dataout; + n01OO00l <= wire_n01OOO0i_dataout; + n01OO00O <= wire_n01OOO0l_dataout; + n01OO0ii <= wire_n01OOO0O_dataout; + n01OO0il <= wire_n01OOOii_dataout; + n0i01lOO <= wire_n0i01Oii_dataout; + n0i01O1i <= wire_n0i01Oil_dataout; + n0i01O1l <= wire_n0i01OiO_dataout; + n0i01O1O <= wire_n0i01Oli_dataout; + n0i0OiOi <= wire_n0ii11lO_dataout; + n0i0OiOl <= wire_n0ii11Oi_dataout; + n0i0OiOO <= wire_n0ii11Ol_dataout; + n0i0Ol1i <= wire_n0ii11OO_dataout; + n0iii0OO <= wire_n0iil01i_dataout; + n0iOli0i <= wire_n0iOlill_dataout; + n0iOli0l <= wire_n0iOlilO_dataout; + n0iOli0O <= wire_n0iOliOi_dataout; + n0iOliii <= wire_n0iOliOl_dataout; + n0l0110i <= wire_n0l01O0l_dataout; + n0l1i00i <= wire_n0l1iO1O_dataout; + n0l1i00l <= wire_n0l1iO0i_dataout; + n0l1i01l <= wire_n0l1iO1i_dataout; + n0l1i01O <= wire_n0l1iO1l_dataout; + n0ll01il <= wire_n0ll01OO_dataout; + n0ll01iO <= wire_n0ll001i_dataout; + n0ll01li <= wire_n0ll001l_dataout; + n0ll01ll <= wire_n0ll001O_dataout; + n0llOO0O <= wire_n0lO1i0l_dataout; + n0llOOii <= wire_n0lO1i0O_dataout; + n0llOOil <= wire_n0lO1iii_dataout; + n0llOOiO <= wire_n0lO1iil_dataout; + n0lOilil <= wire_n0lOliiO_dataout; + n0O0lllO <= wire_n0O0lO0i_dataout; + n0O0llOi <= wire_n0O0lO0l_dataout; + n0O0llOl <= wire_n0O0lO0O_dataout; + n0O0llOO <= wire_n0O0lOii_dataout; + n0Oiiili <= wire_n0Oil1iO_dataout; + n0Oiiill <= wire_n0Oil1li_dataout; + n0OiiilO <= wire_n0Oil1ll_dataout; + n0OiiiOi <= wire_n0Oil1lO_dataout; + n0Ol10lO <= wire_n0Ol01Oi_dataout; + n11i110i <= wire_n11li1ll_dataout; + n11l0O0O <= wire_n11li1Oi_dataout; + n11li1iO <= wire_n11li0OO_dataout; + n11O010l <= wire_n11Oiill_dataout; + n11O0i0l <= wire_n11OiOll_dataout; + n11O0i1l <= wire_n11OiOil_dataout; + n11O0iii <= wire_n11OiOOi_dataout; + n11O0iiO <= wire_n11OiOOO_dataout; + n11O0Oil <= wire_n11Ol0Ol_dataout; + n11Oi00O <= wire_n11Ollll_dataout; + n1il11Ol <= wire_nlOll1iOO_dataout; + n1l1OO0l <= wire_n1l011li_dataout; + n1l1OOil <= wire_n1l011Oi_dataout; + n1l1OOli <= wire_n1l011OO_dataout; + n1l1OOOi <= wire_n1l0101O_dataout; + n1lililO <= wire_n1lilOll_dataout; + n1lilO0O <= wire_n1liO0ii_dataout; + n1lOi0ii <= wire_n1lOii0l_dataout; + n1Oi101i <= wire_n1Oi10il_dataout; + n1Oi101l <= wire_n1Oi10iO_dataout; + n1Oi11Ol <= wire_n1Oi100O_dataout; + n1Oi11OO <= wire_n1Oi10ii_dataout; + n1OilOlO <= wire_n1OiOill_dataout; + n1OilOOi <= wire_n1OiOilO_dataout; + n1OilOOl <= wire_n1OiOiOi_dataout; + n1OilOOO <= wire_n1OiOiOl_dataout; + n1Ol0lOl <= wire_n1OliiOO_dataout; + niO010lO <= wire_niO01i1l_dataout; + niO011lO <= wire_niO0101l_dataout; + niO01iOl <= wire_niO01l0i_dataout; + nlOill00i <= wire_nlOilliOl_dataout; + nlOill01i <= wire_nlOillill_dataout; + nlOill1OO <= wire_nlOillili_dataout; + nlOiO10Ol <= wire_nlOiO011l_dataout; + nlOiOO1lO <= wire_nlOl1i01O_dataout; + nlOlil10O <= wire_nlOliO0lO_dataout; + nlOliO00O <= wire_nlOliOl1O_dataout; + nlOliO01O <= wire_nlOliOiOO_dataout; + nlOliO0iO <= wire_nlOliOl0O_dataout; + nlOliO10O <= wire_nlOliOi1O_dataout; + nlOliO11O <= wire_nlOliO0OO_dataout; + nlOliO1iO <= wire_nlOliOi0O_dataout; + nlOliO1lO <= wire_nlOliOiiO_dataout; + nlOliO1OO <= wire_nlOliOilO_dataout; + nlOll0Oii <= wire_nlOll0OlO_dataout; + nlOllllii <= wire_nlOlllllO_dataout; + nlOlOilll <= wire_nlOlOiOOO_dataout; + nlOlOilOO <= wire_nlOlOl10i_dataout; + END IF; + if (now = 0 ns) then + n001i1ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00il1ll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00il1lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00il1Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00il1Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00l0OiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00l0Oli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00l0Oll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00l0OlO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n00lOlll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0100l0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0100l1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0100l1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0100l1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n010Oi1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n011iO0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n011iO0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n011iO0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n011iO1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01O1iii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01O1iil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01O1iiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01O1ili <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01OO00l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01OO00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01OO0ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n01OO0il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i01lOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i01O1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i01O1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i01O1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i0OiOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i0OiOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i0OiOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0i0Ol1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iii0OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOli0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOli0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOli0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0iOliii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0l0110i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0l1i00i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0l1i00l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0l1i01l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0l1i01O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0ll01il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0ll01iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0ll01li <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0ll01ll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0llOO0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0llOOii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0llOOil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0llOOiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0lOilil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0O0lllO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0O0llOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0O0llOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0O0llOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0Oiiili <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0Oiiill <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0OiiilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0OiiiOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n0Ol10lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11i110i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11l0O0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11li1iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11O010l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11O0i0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11O0i1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11O0iii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11O0iiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11O0Oil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n11Oi00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1il11Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l1OO0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l1OOil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l1OOli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l1OOOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1lililO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1lilO0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1lOi0ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1Oi101i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1Oi101l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1Oi11Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1Oi11OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1OilOlO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1OilOOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1OilOOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1OilOOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1Ol0lOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niO010lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niO011lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niO01iOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOill00i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOill01i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOill1OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOiO10Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOiOO1lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOlil10O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO00O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO01O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO0iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO10O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO11O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO1iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO1lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOliO1OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOll0Oii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOllllii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOlOilll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOlOilOO <= '1' after 1 ps; + end if; + END PROCESS; + wire_niO01iOi_w19584w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_n1lilO0O19581w19582w19583w(0) AND wire_n1l1Ol0O_dataout; + wire_niO01iOi_w_lg_w_lg_w_lg_n00il1Ol15580w15581w15582w(0) <= wire_niO01iOi_w_lg_w_lg_n00il1Ol15580w15581w(0) AND n00il1ll; + wire_niO01iOi_w_lg_w_lg_w_lg_n00l0OlO15551w15553w15554w(0) <= wire_niO01iOi_w_lg_w_lg_n00l0OlO15551w15553w(0) AND n00l0OiO; + wire_niO01iOi_w_lg_w_lg_w_lg_n0100l0i17365w17367w17368w(0) <= wire_niO01iOi_w_lg_w_lg_n0100l0i17365w17367w(0) AND n0100l1i; + wire_niO01iOi_w_lg_w_lg_w_lg_n011iO0O17394w17395w17396w(0) <= wire_niO01iOi_w_lg_w_lg_n011iO0O17394w17395w(0) AND n011iO1O; + wire_niO01iOi_w_lg_w_lg_w_lg_n01O1ili16487w16488w16489w(0) <= wire_niO01iOi_w_lg_w_lg_n01O1ili16487w16488w(0) AND n01O1iii; + wire_niO01iOi_w_lg_w_lg_w_lg_n01OO0il16458w16460w16461w(0) <= wire_niO01iOi_w_lg_w_lg_n01OO0il16458w16460w(0) AND n01OO00l; + wire_niO01iOi_w_lg_w_lg_w_lg_n0i01O1O14673w14674w14675w(0) <= wire_niO01iOi_w_lg_w_lg_n0i01O1O14673w14674w(0) AND n0i01lOO; + wire_niO01iOi_w_lg_w_lg_w_lg_n0i0Ol1i14644w14646w14647w(0) <= wire_niO01iOi_w_lg_w_lg_n0i0Ol1i14644w14646w(0) AND n0i0OiOi; + wire_niO01iOi_w_lg_w_lg_w_lg_n0iOliii13766w13767w13768w(0) <= wire_niO01iOi_w_lg_w_lg_n0iOliii13766w13767w(0) AND n0iOli0i; + wire_niO01iOi_w_lg_w_lg_w_lg_n0l1i00l13737w13739w13740w(0) <= wire_niO01iOi_w_lg_w_lg_n0l1i00l13737w13739w(0) AND n0l1i01l; + wire_niO01iOi_w_lg_w_lg_w_lg_n0ll01ll12859w12860w12861w(0) <= wire_niO01iOi_w_lg_w_lg_n0ll01ll12859w12860w(0) AND n0ll01il; + wire_niO01iOi_w_lg_w_lg_w_lg_n0llOOiO12830w12832w12833w(0) <= wire_niO01iOi_w_lg_w_lg_n0llOOiO12830w12832w(0) AND n0llOO0O; + wire_niO01iOi_w_lg_w_lg_w_lg_n0O0llOO11948w11949w11950w(0) <= wire_niO01iOi_w_lg_w_lg_n0O0llOO11948w11949w(0) AND n0O0lllO; + wire_niO01iOi_w_lg_w_lg_w_lg_n0OiiiOi11919w11921w11922w(0) <= wire_niO01iOi_w_lg_w_lg_n0OiiiOi11919w11921w(0) AND n0Oiiili; + wire_niO01iOi_w_lg_w_lg_w_lg_n1Oi101l18301w18302w18303w(0) <= wire_niO01iOi_w_lg_w_lg_n1Oi101l18301w18302w(0) AND n1Oi11Ol; + wire_niO01iOi_w_lg_w_lg_w_lg_n1OilOOO18272w18274w18275w(0) <= wire_niO01iOi_w_lg_w_lg_n1OilOOO18272w18274w(0) AND n1OilOlO; + wire_niO01iOi_w25068w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOlil10O25061w25062w25065w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO11l25066w25067w(0); + wire_niO01iOi_w25128w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO00O25121w25122w25125w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO0il25126w25127w(0); + wire_niO01iOi_w25138w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO01O25131w25132w25135w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO00l25136w25137w(0); + wire_niO01iOi_w25088w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO10O25081w25082w25085w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO1il25086w25087w(0); + wire_niO01iOi_w25078w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO11O25071w25072w25075w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO10l25076w25077w(0); + wire_niO01iOi_w25098w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1iO25091w25092w25095w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO1ll25096w25097w(0); + wire_niO01iOi_w25108w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1lO25101w25102w25105w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO1Ol25106w25107w(0); + wire_niO01iOi_w25118w(0) <= wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1OO25111w25112w25115w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO01l25116w25117w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_n1lilO0O19581w19582w19583w(0) <= wire_niO01iOi_w_lg_w_lg_n1lilO0O19581w19582w(0) AND wire_w_lg_niOli0lOl18958w(0); + wire_niO01iOi_w_lg_w_lg_n00il1Ol15580w15581w(0) <= wire_niO01iOi_w_lg_n00il1Ol15580w(0) AND n00il1lO; + wire_niO01iOi_w_lg_w_lg_n00l0OlO15551w15553w(0) <= wire_niO01iOi_w_lg_n00l0OlO15551w(0) AND wire_niO01iOi_w_lg_n00l0Oli15552w(0); + wire_niO01iOi_w_lg_w_lg_n00l0OlO15551w15864w(0) <= wire_niO01iOi_w_lg_n00l0OlO15551w(0) AND n00l0Oli; + wire_niO01iOi_w_lg_w_lg_n0100l0i17365w17367w(0) <= wire_niO01iOi_w_lg_n0100l0i17365w(0) AND wire_niO01iOi_w_lg_n0100l1l17366w(0); + wire_niO01iOi_w_lg_w_lg_n0100l0i17365w17678w(0) <= wire_niO01iOi_w_lg_n0100l0i17365w(0) AND n0100l1l; + wire_niO01iOi_w_lg_w_lg_n011iO0O17394w17395w(0) <= wire_niO01iOi_w_lg_n011iO0O17394w(0) AND n011iO0i; + wire_niO01iOi_w_lg_w_lg_n01O1ili16487w16488w(0) <= wire_niO01iOi_w_lg_n01O1ili16487w(0) AND n01O1iil; + wire_niO01iOi_w_lg_w_lg_n01OO0il16458w16460w(0) <= wire_niO01iOi_w_lg_n01OO0il16458w(0) AND wire_niO01iOi_w_lg_n01OO00O16459w(0); + wire_niO01iOi_w_lg_w_lg_n01OO0il16458w16771w(0) <= wire_niO01iOi_w_lg_n01OO0il16458w(0) AND n01OO00O; + wire_niO01iOi_w_lg_w_lg_n0i01O1O14673w14674w(0) <= wire_niO01iOi_w_lg_n0i01O1O14673w(0) AND n0i01O1i; + wire_niO01iOi_w_lg_w_lg_n0i0Ol1i14644w14646w(0) <= wire_niO01iOi_w_lg_n0i0Ol1i14644w(0) AND wire_niO01iOi_w_lg_n0i0OiOl14645w(0); + wire_niO01iOi_w_lg_w_lg_n0i0Ol1i14644w14957w(0) <= wire_niO01iOi_w_lg_n0i0Ol1i14644w(0) AND n0i0OiOl; + wire_niO01iOi_w_lg_w_lg_n0iOliii13766w13767w(0) <= wire_niO01iOi_w_lg_n0iOliii13766w(0) AND n0iOli0l; + wire_niO01iOi_w_lg_w_lg_n0l1i00l13737w13739w(0) <= wire_niO01iOi_w_lg_n0l1i00l13737w(0) AND wire_niO01iOi_w_lg_n0l1i01O13738w(0); + wire_niO01iOi_w_lg_w_lg_n0l1i00l13737w14050w(0) <= wire_niO01iOi_w_lg_n0l1i00l13737w(0) AND n0l1i01O; + wire_niO01iOi_w_lg_w_lg_n0ll01ll12859w12860w(0) <= wire_niO01iOi_w_lg_n0ll01ll12859w(0) AND n0ll01iO; + wire_niO01iOi_w_lg_w_lg_n0llOOiO12830w12832w(0) <= wire_niO01iOi_w_lg_n0llOOiO12830w(0) AND wire_niO01iOi_w_lg_n0llOOii12831w(0); + wire_niO01iOi_w_lg_w_lg_n0llOOiO12830w13143w(0) <= wire_niO01iOi_w_lg_n0llOOiO12830w(0) AND n0llOOii; + wire_niO01iOi_w_lg_w_lg_n0O0llOO11948w11949w(0) <= wire_niO01iOi_w_lg_n0O0llOO11948w(0) AND n0O0llOi; + wire_niO01iOi_w_lg_w_lg_n0OiiiOi11919w11921w(0) <= wire_niO01iOi_w_lg_n0OiiiOi11919w(0) AND wire_niO01iOi_w_lg_n0Oiiill11920w(0); + wire_niO01iOi_w_lg_w_lg_n0OiiiOi11919w12235w(0) <= wire_niO01iOi_w_lg_n0OiiiOi11919w(0) AND n0Oiiill; + wire_niO01iOi_w_lg_w_lg_n1Oi101l18301w18302w(0) <= wire_niO01iOi_w_lg_n1Oi101l18301w(0) AND n1Oi11OO; + wire_niO01iOi_w_lg_w_lg_n1OilOOO18272w18274w(0) <= wire_niO01iOi_w_lg_n1OilOOO18272w(0) AND wire_niO01iOi_w_lg_n1OilOOi18273w(0); + wire_niO01iOi_w_lg_w_lg_n1OilOOO18272w18585w(0) <= wire_niO01iOi_w_lg_n1OilOOO18272w(0) AND n1OilOOi; + wire_niO01iOi_w_lg_w_lg_nlOllllii23878w23879w(0) <= wire_niO01iOi_w_lg_nlOllllii23878w(0) AND niOl1OiOl; + wire_niO01iOi_w_lg_w_lg_w_lg_nlOlil10O25061w25062w25065w(0) <= wire_niO01iOi_w_lg_w_lg_nlOlil10O25061w25062w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO11i25063w25064w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO00O25121w25122w25125w(0) <= wire_niO01iOi_w_lg_w_lg_nlOliO00O25121w25122w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO0ii25123w25124w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO01O25131w25132w25135w(0) <= wire_niO01iOi_w_lg_w_lg_nlOliO01O25131w25132w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO00i25133w25134w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO10O25081w25082w25085w(0) <= wire_niO01iOi_w_lg_w_lg_nlOliO10O25081w25082w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO1ii25083w25084w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO11O25071w25072w25075w(0) <= wire_niO01iOi_w_lg_w_lg_nlOliO11O25071w25072w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO10i25073w25074w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1iO25091w25092w25095w(0) <= wire_niO01iOi_w_lg_w_lg_nlOliO1iO25091w25092w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO1li25093w25094w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1lO25101w25102w25105w(0) <= wire_niO01iOi_w_lg_w_lg_nlOliO1lO25101w25102w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO1Oi25103w25104w(0); + wire_niO01iOi_w_lg_w_lg_w_lg_nlOliO1OO25111w25112w25115w(0) <= wire_niO01iOi_w_lg_w_lg_nlOliO1OO25111w25112w(0) AND wire_niO01ill_w_lg_w_lg_nlOliO01i25113w25114w(0); + wire_niO01iOi_w_lg_w_lg_n11Oi00O20642w20643w(0) <= wire_niO01iOi_w_lg_n11Oi00O20642w(0) AND niOli1iOl; + wire_niO01iOi_w_lg_w_lg_n11Oi00O20642w20646w(0) <= wire_niO01iOi_w_lg_n11Oi00O20642w(0) AND niOli1iOO; + wire_niO01iOi_w_lg_w_lg_n1lilO0O19581w19582w(0) <= wire_niO01iOi_w_lg_n1lilO0O19581w(0) AND wire_w_lg_niOli0lOO18956w(0); + wire_niO01iOi_w_lg_w_lg_nlOiOO1lO28034w28035w(0) <= wire_niO01iOi_w_lg_nlOiOO1lO28034w(0) AND n1lO0lOl; + wire_niO01iOi_w_lg_n00il1Ol15580w(0) <= n00il1Ol AND n00il1Oi; + wire_niO01iOi_w_lg_n00l0OlO15551w(0) <= n00l0OlO AND wire_niO01iOi_w_lg_n00l0Oll15550w(0); + wire_niO01iOi_w_lg_n0100l0i17365w(0) <= n0100l0i AND wire_niO01iOi_w_lg_n0100l1O17364w(0); + wire_niO01iOi_w_lg_n011iO0O17394w(0) <= n011iO0O AND n011iO0l; + wire_niO01iOi_w_lg_n01O1ili16487w(0) <= n01O1ili AND n01O1iiO; + wire_niO01iOi_w_lg_n01OO0il16458w(0) <= n01OO0il AND wire_niO01iOi_w_lg_n01OO0ii16457w(0); + wire_niO01iOi_w_lg_n0i01O1O14673w(0) <= n0i01O1O AND n0i01O1l; + wire_niO01iOi_w_lg_n0i0Ol1i14644w(0) <= n0i0Ol1i AND wire_niO01iOi_w_lg_n0i0OiOO14643w(0); + wire_niO01iOi_w_lg_n0iOliii13766w(0) <= n0iOliii AND n0iOli0O; + wire_niO01iOi_w_lg_n0l1i00l13737w(0) <= n0l1i00l AND wire_niO01iOi_w_lg_n0l1i00i13736w(0); + wire_niO01iOi_w_lg_n0ll01ll12859w(0) <= n0ll01ll AND n0ll01li; + wire_niO01iOi_w_lg_n0llOOiO12830w(0) <= n0llOOiO AND wire_niO01iOi_w_lg_n0llOOil12829w(0); + wire_niO01iOi_w_lg_n0O0llOO11948w(0) <= n0O0llOO AND n0O0llOl; + wire_niO01iOi_w_lg_n0OiiiOi11919w(0) <= n0OiiiOi AND wire_niO01iOi_w_lg_n0OiiilO11918w(0); + wire_niO01iOi_w_lg_n1Oi101l18301w(0) <= n1Oi101l AND n1Oi101i; + wire_niO01iOi_w_lg_n1OilOOO18272w(0) <= n1OilOOO AND wire_niO01iOi_w_lg_n1OilOOl18271w(0); + wire_niO01iOi_w_lg_nlOllllii23878w(0) <= nlOllllii AND niOl1OiOO; + wire_niO01iOi_w_lg_w_lg_nlOlil10O25061w25062w(0) <= NOT wire_niO01iOi_w_lg_nlOlil10O25061w(0); + wire_niO01iOi_w_lg_w_lg_nlOliO00O25121w25122w(0) <= NOT wire_niO01iOi_w_lg_nlOliO00O25121w(0); + wire_niO01iOi_w_lg_w_lg_nlOliO01O25131w25132w(0) <= NOT wire_niO01iOi_w_lg_nlOliO01O25131w(0); + wire_niO01iOi_w_lg_w_lg_nlOliO10O25081w25082w(0) <= NOT wire_niO01iOi_w_lg_nlOliO10O25081w(0); + wire_niO01iOi_w_lg_w_lg_nlOliO11O25071w25072w(0) <= NOT wire_niO01iOi_w_lg_nlOliO11O25071w(0); + wire_niO01iOi_w_lg_w_lg_nlOliO1iO25091w25092w(0) <= NOT wire_niO01iOi_w_lg_nlOliO1iO25091w(0); + wire_niO01iOi_w_lg_w_lg_nlOliO1lO25101w25102w(0) <= NOT wire_niO01iOi_w_lg_nlOliO1lO25101w(0); + wire_niO01iOi_w_lg_w_lg_nlOliO1OO25111w25112w(0) <= NOT wire_niO01iOi_w_lg_nlOliO1OO25111w(0); + wire_niO01iOi_w_lg_n00il1ll15944w(0) <= NOT n00il1ll; + wire_niO01iOi_w_lg_n00il1lO15942w(0) <= NOT n00il1lO; + wire_niO01iOi_w_lg_n00il1Oi15940w(0) <= NOT n00il1Oi; + wire_niO01iOi_w_lg_n00il1Ol15939w(0) <= NOT n00il1Ol; + wire_niO01iOi_w_lg_n00l0OiO15859w(0) <= NOT n00l0OiO; + wire_niO01iOi_w_lg_n00l0Oli15552w(0) <= NOT n00l0Oli; + wire_niO01iOi_w_lg_n00l0Oll15550w(0) <= NOT n00l0Oll; + wire_niO01iOi_w_lg_n00l0OlO15856w(0) <= NOT n00l0OlO; + wire_niO01iOi_w_lg_n0100l0i17670w(0) <= NOT n0100l0i; + wire_niO01iOi_w_lg_n0100l1i17673w(0) <= NOT n0100l1i; + wire_niO01iOi_w_lg_n0100l1l17366w(0) <= NOT n0100l1l; + wire_niO01iOi_w_lg_n0100l1O17364w(0) <= NOT n0100l1O; + wire_niO01iOi_w_lg_n011iO0i17756w(0) <= NOT n011iO0i; + wire_niO01iOi_w_lg_n011iO0l17754w(0) <= NOT n011iO0l; + wire_niO01iOi_w_lg_n011iO0O17753w(0) <= NOT n011iO0O; + wire_niO01iOi_w_lg_n011iO1O17758w(0) <= NOT n011iO1O; + wire_niO01iOi_w_lg_n01O1iii16851w(0) <= NOT n01O1iii; + wire_niO01iOi_w_lg_n01O1iil16849w(0) <= NOT n01O1iil; + wire_niO01iOi_w_lg_n01O1iiO16847w(0) <= NOT n01O1iiO; + wire_niO01iOi_w_lg_n01O1ili16846w(0) <= NOT n01O1ili; + wire_niO01iOi_w_lg_n01OO00l16766w(0) <= NOT n01OO00l; + wire_niO01iOi_w_lg_n01OO00O16459w(0) <= NOT n01OO00O; + wire_niO01iOi_w_lg_n01OO0ii16457w(0) <= NOT n01OO0ii; + wire_niO01iOi_w_lg_n01OO0il16763w(0) <= NOT n01OO0il; + wire_niO01iOi_w_lg_n0i01lOO15037w(0) <= NOT n0i01lOO; + wire_niO01iOi_w_lg_n0i01O1i15035w(0) <= NOT n0i01O1i; + wire_niO01iOi_w_lg_n0i01O1l15033w(0) <= NOT n0i01O1l; + wire_niO01iOi_w_lg_n0i01O1O15032w(0) <= NOT n0i01O1O; + wire_niO01iOi_w_lg_n0i0OiOi14952w(0) <= NOT n0i0OiOi; + wire_niO01iOi_w_lg_n0i0OiOl14645w(0) <= NOT n0i0OiOl; + wire_niO01iOi_w_lg_n0i0OiOO14643w(0) <= NOT n0i0OiOO; + wire_niO01iOi_w_lg_n0i0Ol1i14949w(0) <= NOT n0i0Ol1i; + wire_niO01iOi_w_lg_n0iOli0i14130w(0) <= NOT n0iOli0i; + wire_niO01iOi_w_lg_n0iOli0l14128w(0) <= NOT n0iOli0l; + wire_niO01iOi_w_lg_n0iOli0O14126w(0) <= NOT n0iOli0O; + wire_niO01iOi_w_lg_n0iOliii14125w(0) <= NOT n0iOliii; + wire_niO01iOi_w_lg_n0l1i00i13736w(0) <= NOT n0l1i00i; + wire_niO01iOi_w_lg_n0l1i00l14042w(0) <= NOT n0l1i00l; + wire_niO01iOi_w_lg_n0l1i01l14045w(0) <= NOT n0l1i01l; + wire_niO01iOi_w_lg_n0l1i01O13738w(0) <= NOT n0l1i01O; + wire_niO01iOi_w_lg_n0ll01il13223w(0) <= NOT n0ll01il; + wire_niO01iOi_w_lg_n0ll01iO13221w(0) <= NOT n0ll01iO; + wire_niO01iOi_w_lg_n0ll01li13219w(0) <= NOT n0ll01li; + wire_niO01iOi_w_lg_n0ll01ll13218w(0) <= NOT n0ll01ll; + wire_niO01iOi_w_lg_n0llOO0O13138w(0) <= NOT n0llOO0O; + wire_niO01iOi_w_lg_n0llOOii12831w(0) <= NOT n0llOOii; + wire_niO01iOi_w_lg_n0llOOil12829w(0) <= NOT n0llOOil; + wire_niO01iOi_w_lg_n0llOOiO13135w(0) <= NOT n0llOOiO; + wire_niO01iOi_w_lg_n0O0lllO12315w(0) <= NOT n0O0lllO; + wire_niO01iOi_w_lg_n0O0llOi12313w(0) <= NOT n0O0llOi; + wire_niO01iOi_w_lg_n0O0llOl12311w(0) <= NOT n0O0llOl; + wire_niO01iOi_w_lg_n0O0llOO12310w(0) <= NOT n0O0llOO; + wire_niO01iOi_w_lg_n0Oiiili12230w(0) <= NOT n0Oiiili; + wire_niO01iOi_w_lg_n0Oiiill11920w(0) <= NOT n0Oiiill; + wire_niO01iOi_w_lg_n0OiiilO11918w(0) <= NOT n0OiiilO; + wire_niO01iOi_w_lg_n0OiiiOi12227w(0) <= NOT n0OiiiOi; + wire_niO01iOi_w_lg_n11li1iO9835w(0) <= NOT n11li1iO; + wire_niO01iOi_w_lg_n11O0i0l21009w(0) <= NOT n11O0i0l; + wire_niO01iOi_w_lg_n11O0i1l26592w(0) <= NOT n11O0i1l; + wire_niO01iOi_w_lg_n11O0iii26586w(0) <= NOT n11O0iii; + wire_niO01iOi_w_lg_n11O0iiO26588w(0) <= NOT n11O0iiO; + wire_niO01iOi_w_lg_n11Oi00O20642w(0) <= NOT n11Oi00O; + wire_niO01iOi_w_lg_n1il11Ol20649w(0) <= NOT n1il11Ol; + wire_niO01iOi_w_lg_n1l1OO0l19947w(0) <= NOT n1l1OO0l; + wire_niO01iOi_w_lg_n1l1OOil19941w(0) <= NOT n1l1OOil; + wire_niO01iOi_w_lg_n1l1OOli19937w(0) <= NOT n1l1OOli; + wire_niO01iOi_w_lg_n1l1OOOi19932w(0) <= NOT n1l1OOOi; + wire_niO01iOi_w_lg_n1lilO0O19581w(0) <= NOT n1lilO0O; + wire_niO01iOi_w_lg_n1Oi101i18661w(0) <= NOT n1Oi101i; + wire_niO01iOi_w_lg_n1Oi101l18660w(0) <= NOT n1Oi101l; + wire_niO01iOi_w_lg_n1Oi11Ol18665w(0) <= NOT n1Oi11Ol; + wire_niO01iOi_w_lg_n1Oi11OO18663w(0) <= NOT n1Oi11OO; + wire_niO01iOi_w_lg_n1OilOlO18580w(0) <= NOT n1OilOlO; + wire_niO01iOi_w_lg_n1OilOOi18273w(0) <= NOT n1OilOOi; + wire_niO01iOi_w_lg_n1OilOOl18271w(0) <= NOT n1OilOOl; + wire_niO01iOi_w_lg_n1OilOOO18577w(0) <= NOT n1OilOOO; + wire_niO01iOi_w_lg_nlOiO10Ol28193w(0) <= NOT nlOiO10Ol; + wire_niO01iOi_w_lg_nlOiOO1lO28034w(0) <= NOT nlOiOO1lO; + wire_niO01iOi_w_lg_nlOllllii23948w(0) <= NOT nlOllllii; + wire_niO01iOi_w_lg_nlOlOilOO24659w(0) <= NOT nlOlOilOO; + wire_niO01iOi_w_lg_w_lg_n11O0Oil21254w21255w(0) <= wire_niO01iOi_w_lg_n11O0Oil21254w(0) OR n11O0lOl; + wire_niO01iOi_w_lg_n11O0Oil23855w(0) <= n11O0Oil OR wire_niO01ill_w_lg_n11O0l1O23854w(0); + wire_niO01iOi_w_lg_n11O0Oil21467w(0) <= n11O0Oil OR n11O0lli; + wire_niO01iOi_w_lg_n11O0Oil21254w(0) <= n11O0Oil OR n11O0O1l; + wire_niO01iOi_w_lg_n11O0Oil23836w(0) <= n11O0Oil OR nlOllll0O; + wire_niO01iOi_w_lg_nlOlil10O25061w(0) <= nlOlil10O XOR n0O0OiOl; + wire_niO01iOi_w_lg_nlOliO00O25121w(0) <= nlOliO00O XOR n1Oi011i; + wire_niO01iOi_w_lg_nlOliO01O25131w(0) <= nlOliO01O XOR n011ll0l; + wire_niO01iOi_w_lg_nlOliO10O25081w(0) <= nlOliO10O XOR n0iOO00O; + wire_niO01iOi_w_lg_nlOliO11O25071w(0) <= nlOliO11O XOR n0ll0Oli; + wire_niO01iOi_w_lg_nlOliO1iO25091w(0) <= nlOliO1iO XOR n0i00l1l; + wire_niO01iOi_w_lg_nlOliO1lO25101w(0) <= nlOliO1lO XOR n00ilOOi; + wire_niO01iOi_w_lg_nlOliO1OO25111w(0) <= nlOliO1OO XOR n01O00iO; + PROCESS (pld_clk, pld_rstn) + BEGIN + IF (pld_rstn = '0') THEN + niO01lii <= '0'; + niO01lli <= '0'; + ELSIF (pld_clk = '1' AND pld_clk'event) THEN + niO01lii <= niO01lli; + niO01lli <= niOO0lliO; + END IF; + END PROCESS; + PROCESS (phy_clk, wire_niO01llO_CLRN) + BEGIN + IF (wire_niO01llO_CLRN = '0') THEN + n1iiOllO <= '0'; + niil01ii <= '0'; + niil01il <= '0'; + niil0iOO <= '0'; + niil0l0i <= '0'; + niil0l0l <= '0'; + niil0l1l <= '0'; + niil0l1O <= '0'; + niil0liO <= '0'; + niil0llO <= '0'; + niil0lOi <= '0'; + niil0lOl <= '0'; + niili1iO <= '0'; + niili1li <= '0'; + niili1ll <= '0'; + niili1lO <= '0'; + niili1Oi <= '0'; + niO0100i <= '0'; + niO0110i <= '0'; + niO01i0i <= '0'; + niO01lll <= '0'; + niO01lOi <= '0'; + niO110ii <= '0'; + niO110il <= '0'; + niO110iO <= '0'; + niO110li <= '0'; + niO110ll <= '0'; + niO1li0i <= '0'; + niO1li1O <= '0'; + niO1OOOi <= '0'; + niOO0Olli <= '0'; + nlOi0000O <= '0'; + nlOi00l0O <= '0'; + nlOi00l1l <= '0'; + nlOi00O0O <= '0'; + nlOi01OlO <= '0'; + nlOi0l1Oi <= '0'; + nlOi0O01O <= '0'; + nlOi0O11i <= '0'; + nlOi0OilO <= '0'; + nlOi0OOOi <= '0'; + nlOii00Oi <= '0'; + nlOii010i <= '0'; + nlOii0liO <= '0'; + nlOii0lOi <= '0'; + nlOii0O0O <= '0'; + nlOii0O1l <= '0'; + nlOii0Oli <= '0'; + nlOii100O <= '0'; + nlOii101l <= '0'; + nlOii10li <= '0'; + nlOii10Ol <= '0'; + nlOii1i1i <= '0'; + nlOii1lli <= '0'; + nlOiii1Oi <= '0'; + nlOiiiOlO <= '0'; + nlOiilO0O <= '0'; + nlOiiOiOi <= '0'; + nlOil101l <= '0'; + nlOil101O <= '0'; + nlOil10il <= '0'; + nlOil1i1O <= '0'; + nlOili11l <= '0'; + nlOilil0i <= '0'; + nlOilil0l <= '0'; + nlOilil1i <= '0'; + nlOilil1O <= '0'; + nlOilO01i <= '0'; + nlOilOili <= '0'; + nlOilOO0i <= '0'; + ELSIF (phy_clk = '1' AND phy_clk'event) THEN + n1iiOllO <= wire_n1il11iO_dataout; + niil01ii <= niil0lOi; + niil01il <= niil0llO; + niil0iOO <= niil0lOl; + niil0l0i <= niili1ll; + niil0l0l <= niili1lO; + niil0l1l <= niili1iO; + niil0l1O <= niili1li; + niil0liO <= niili1Oi; + niil0llO <= wire_niO10lOO_dataout; + niil0lOi <= wire_niO10iOO_dataout; + niil0lOl <= wire_niO100OO_dataout; + niili1iO <= wire_niO101OO_dataout; + niili1li <= wire_niO11OOO_dataout; + niili1ll <= wire_niO11lOO_dataout; + niili1lO <= wire_niO11iOO_dataout; + niili1Oi <= wire_niO110OO_dataout; + niO0100i <= niO010iO; + niO0110i <= niO011iO; + niO01i0i <= niO01iiO; + niO01lll <= phy_srst; + niO01lOi <= niO01lll; + niO110ii <= rxelecidle0; + niO110il <= rxelecidle1; + niO110iO <= rxelecidle2; + niO110li <= rxelecidle3; + niO110ll <= rxelecidle4; + niO1li0i <= rxelecidle7; + niO1li1O <= rxelecidle6; + niO1OOOi <= rxelecidle5; + niOO0Olli <= wire_niOO0OlOi_dataout; + nlOi0000O <= wire_nlOi000ll_dataout; + nlOi00l0O <= nlOi00l0l; + nlOi00l1l <= nlOi00l1i; + nlOi00O0O <= wire_nlOi00OOl_dataout; + nlOi01OlO <= wire_nlOi0011l_dataout; + nlOi0l1Oi <= wire_nlOi0l01i_dataout; + nlOi0O01O <= wire_nlOi0O0iO_dataout; + nlOi0O11i <= wire_nlOi0O10i_dataout; + nlOi0OilO <= wire_nlOi0Ol1O_dataout; + nlOi0OOOi <= wire_nlOii111i_dataout; + nlOii00Oi <= wire_nlOii0i1O_dataout; + nlOii010i <= wire_nlOii01iO_dataout; + nlOii0liO <= nlOii0lil; + nlOii0lOi <= nlOii0llO; + nlOii0O0O <= nlOii0O0l; + nlOii0O1l <= nlOii0O1i; + nlOii0Oli <= nlOii0OiO; + nlOii100O <= nlOii100l; + nlOii101l <= nlOii101i; + nlOii10li <= nlOii10iO; + nlOii10Ol <= nlOii10Oi; + nlOii1i1i <= wire_nlOii1i0O_dataout; + nlOii1lli <= wire_nlOii1lOO_dataout; + nlOiii1Oi <= wire_nlOiii01O_dataout; + nlOiiiOlO <= wire_nlOiil01l_dataout; + nlOiilO0O <= wire_nlOiiO11O_dataout; + nlOiiOiOi <= wire_nlOiiOllO_dataout; + nlOil101l <= wire_nlOil100i_dataout; + nlOil101O <= wire_nlOil100l_dataout; + nlOil10il <= wire_nlOil100O_dataout; + nlOil1i1O <= wire_nlOil10ii_dataout; + nlOili11l <= wire_nlOili1ii_dataout; + nlOilil0i <= wire_nlOill10O_dataout; + nlOilil0l <= wire_nlOill11O_dataout; + nlOilil1i <= wire_nlOill10i_dataout; + nlOilil1O <= wire_nlOill10l_dataout; + nlOilO01i <= wire_nlOilO00O_dataout; + nlOilOili <= wire_nlOilOiOO_dataout; + nlOilOO0i <= wire_nlOilOOiO_dataout; + END IF; + END PROCESS; + wire_niO01llO_CLRN <= (niOO10Oli80 XOR niOO10Oli79); + wire_niO01llO_w_lg_niil01ii23952w(0) <= NOT niil01ii; + wire_niO01llO_w_lg_niil01il23950w(0) <= NOT niil01il; + wire_niO01llO_w_lg_niil0iOO23954w(0) <= NOT niil0iOO; + wire_niO01llO_w_lg_niil0l0i23960w(0) <= NOT niil0l0i; + wire_niO01llO_w_lg_niil0l0l23962w(0) <= NOT niil0l0l; + wire_niO01llO_w_lg_niil0l1l23956w(0) <= NOT niil0l1l; + wire_niO01llO_w_lg_niil0l1O23958w(0) <= NOT niil0l1O; + wire_niO01llO_w_lg_niil0liO23964w(0) <= NOT niil0liO; + PROCESS (core_clk, wire_niO01OlO_PRN, core_npor) + BEGIN + IF (wire_niO01OlO_PRN = '0') THEN + niO01Oll <= '1'; + niO01OOi <= '1'; + ELSIF (core_npor = '0') THEN + niO01Oll <= '0'; + niO01OOi <= '0'; + ELSIF (core_clk = '1' AND core_clk'event) THEN + niO01Oll <= niO01OOi; + niO01OOi <= niOO0lliO; + END IF; + END PROCESS; + wire_niO01OlO_PRN <= (niOO10Oll78 XOR niOO10Oll77); + PROCESS (pld_clk, wire_niOOO0O_PRN, wire_niOOO0O_CLRN) + BEGIN + IF (wire_niOOO0O_PRN = '0') THEN + n1l00il <= '1'; + n1lliil <= '1'; + n1lliiO <= '1'; + n1llili <= '1'; + ni0li0l <= '1'; + ni0li0O <= '1'; + ni0li1l <= '1'; + ni0liii <= '1'; + ni0liil <= '1'; + ni0liiO <= '1'; + ni0lili <= '1'; + ni0lill <= '1'; + ni0lilO <= '1'; + ni0O00i <= '1'; + ni0O00l <= '1'; + ni0O00O <= '1'; + ni0O01i <= '1'; + ni0O01l <= '1'; + ni0O01O <= '1'; + ni0O0ii <= '1'; + ni0O0il <= '1'; + ni0O0iO <= '1'; + ni0O0li <= '1'; + ni0O0ll <= '1'; + ni0O0lO <= '1'; + ni0O0Oi <= '1'; + ni0O0Ol <= '1'; + ni0O0OO <= '1'; + ni0O1li <= '1'; + ni0Oi0i <= '1'; + ni0Oi0l <= '1'; + ni0Oi0O <= '1'; + ni0Oi1i <= '1'; + ni0Oi1l <= '1'; + ni0Oi1O <= '1'; + ni0Oiii <= '1'; + ni0Oiil <= '1'; + ni0OiiO <= '1'; + ni0Oili <= '1'; + ni0Oill <= '1'; + ni0OilO <= '1'; + ni0OiOi <= '1'; + ni0OiOl <= '1'; + ni0OiOO <= '1'; + ni0Ol0i <= '1'; + ni0Ol0l <= '1'; + ni0Ol1i <= '1'; + ni0Ol1l <= '1'; + ni0Ol1O <= '1'; + niO010iO <= '1'; + niO010li <= '1'; + niO011iO <= '1'; + niO011li <= '1'; + niO01iiO <= '1'; + niO01ili <= '1'; + niOiil0i <= '1'; + niOiilll <= '1'; + niOiilOl <= '1'; + niOiilOO <= '1'; + niOiiO0i <= '1'; + niOiiO0l <= '1'; + niOiiO0O <= '1'; + niOiiO1i <= '1'; + niOiiO1l <= '1'; + niOiiO1O <= '1'; + niOiiOii <= '1'; + niOiiOil <= '1'; + niOiiOiO <= '1'; + niOiiOli <= '1'; + niOiiOll <= '1'; + niOiiOlO <= '1'; + niOiiOOi <= '1'; + niOiiOOl <= '1'; + niOiiOOO <= '1'; + niOil00i <= '1'; + niOil00l <= '1'; + niOil00O <= '1'; + niOil01i <= '1'; + niOil01l <= '1'; + niOil01O <= '1'; + niOil0ii <= '1'; + niOil0il <= '1'; + niOil0iO <= '1'; + niOil0li <= '1'; + niOil0ll <= '1'; + niOil0lO <= '1'; + niOil0Oi <= '1'; + niOil0Ol <= '1'; + niOil0OO <= '1'; + niOil10i <= '1'; + niOil10l <= '1'; + niOil10O <= '1'; + niOil11i <= '1'; + niOil11l <= '1'; + niOil11O <= '1'; + niOil1ii <= '1'; + niOil1il <= '1'; + niOil1iO <= '1'; + niOil1li <= '1'; + niOil1ll <= '1'; + niOil1lO <= '1'; + niOil1Oi <= '1'; + niOil1Ol <= '1'; + niOil1OO <= '1'; + niOiOii <= '1'; + niOiOlli <= '1'; + niOiOlll <= '1'; + niOiOllO <= '1'; + niOiOlOi <= '1'; + niOiOlOl <= '1'; + niOiOlOO <= '1'; + niOiOO0i <= '1'; + niOiOO0l <= '1'; + niOiOO0O <= '1'; + niOiOO1i <= '1'; + niOiOO1l <= '1'; + niOiOO1O <= '1'; + niOiOOii <= '1'; + niOiOOil <= '1'; + niOiOOiO <= '1'; + niOiOOli <= '1'; + niOiOOll <= '1'; + niOiOOlO <= '1'; + niOiOOOi <= '1'; + niOiOOOl <= '1'; + niOiOOOO <= '1'; + niOl100i <= '1'; + niOl100l <= '1'; + niOl100O <= '1'; + niOl101i <= '1'; + niOl101l <= '1'; + niOl101O <= '1'; + niOl10ii <= '1'; + niOl10il <= '1'; + niOl10iO <= '1'; + niOl10li <= '1'; + niOl10ll <= '1'; + niOl10lO <= '1'; + niOl10Oi <= '1'; + niOl110i <= '1'; + niOl110l <= '1'; + niOl110O <= '1'; + niOl111i <= '1'; + niOl111l <= '1'; + niOl111O <= '1'; + niOl11ii <= '1'; + niOl11il <= '1'; + niOl11iO <= '1'; + niOl11li <= '1'; + niOl11ll <= '1'; + niOl11lO <= '1'; + niOl11Oi <= '1'; + niOl11Ol <= '1'; + niOl11OO <= '1'; + niOlii1O <= '1'; + niOlOilO <= '1'; + niOlOl0i <= '1'; + niOlOlii <= '1'; + niOlOO0i <= '1'; + niOlOOll <= '1'; + niOlOOOl <= '1'; + niOO001l <= '1'; + niOO00iO <= '1'; + niOO00lO <= '1'; + niOO00O <= '1'; + niOO00Oi <= '1'; + niOO00Ol <= '1'; + niOO0ii <= '1'; + niOO0il <= '1'; + niOO0ill <= '1'; + niOO0iO <= '1'; + niOO0l0O <= '1'; + niOO0l1i <= '1'; + niOO0li <= '1'; + niOO0lil <= '1'; + niOO0ll <= '1'; + niOO0lO <= '1'; + niOO0Oi <= '1'; + niOO0OiO <= '1'; + niOO0Ol <= '1'; + niOO0Olil <= '1'; + niOO0OlOO <= '1'; + niOO0OO <= '1'; + niOO0OO0i <= '1'; + niOO0OO0l <= '1'; + niOO0OO0O <= '1'; + niOO0OO1O <= '1'; + niOO0OOii <= '1'; + niOO0OOil <= '1'; + niOO0OOiO <= '1'; + niOO0OOl <= '1'; + niOO100i <= '1'; + niOO10ii <= '1'; + niOO11lO <= '1'; + niOO1i0l <= '1'; + niOO1ilO <= '1'; + niOO1iOO <= '1'; + niOO1lOi <= '1'; + niOO1O0l <= '1'; + niOO1Oil <= '1'; + niOOi000i <= '1'; + niOOi000l <= '1'; + niOOi000O <= '1'; + niOOi001i <= '1'; + niOOi00ii <= '1'; + niOOi00il <= '1'; + niOOi00iO <= '1'; + niOOi00li <= '1'; + niOOi00ll <= '1'; + niOOi00lO <= '1'; + niOOi00Oi <= '1'; + niOOi00Ol <= '1'; + niOOi00OO <= '1'; + niOOi01iO <= '1'; + niOOi01l <= '1'; + niOOi0i <= '1'; + niOOi0i0i <= '1'; + niOOi0i0l <= '1'; + niOOi0i1i <= '1'; + niOOi0i1l <= '1'; + niOOi0i1O <= '1'; + niOOi0ii <= '1'; + niOOi0iO <= '1'; + niOOi0l <= '1'; + niOOi0O <= '1'; + niOOi11i <= '1'; + niOOi1i <= '1'; + niOOi1l <= '1'; + niOOi1O <= '1'; + niOOiii <= '1'; + niOOiil <= '1'; + niOOiiO <= '1'; + niOOili <= '1'; + niOOill <= '1'; + niOOilO <= '1'; + niOOiOi <= '1'; + niOOiOl <= '1'; + niOOiOO <= '1'; + niOOl00i <= '1'; + niOOl00l <= '1'; + niOOl00O <= '1'; + niOOl01i <= '1'; + niOOl0i <= '1'; + niOOl0ii <= '1'; + niOOl0il <= '1'; + niOOl0iO <= '1'; + niOOl0l <= '1'; + niOOl0li <= '1'; + niOOl0ll <= '1'; + niOOl0lO <= '1'; + niOOl0O <= '1'; + niOOl0Oi <= '1'; + niOOl0Ol <= '1'; + niOOl1i <= '1'; + niOOl1iO <= '1'; + niOOl1l <= '1'; + niOOl1O <= '1'; + niOOlii <= '1'; + niOOlil <= '1'; + niOOliO <= '1'; + niOOlli <= '1'; + niOOlll <= '1'; + niOOllO <= '1'; + niOOlO1i <= '1'; + niOOlOi <= '1'; + niOOlOil <= '1'; + niOOlOl <= '1'; + niOOlOll <= '1'; + niOOlOO <= '1'; + niOOO0i <= '1'; + niOOO0l <= '1'; + niOOO1i <= '1'; + niOOO1ii <= '1'; + niOOO1l <= '1'; + niOOO1lO <= '1'; + niOOO1O <= '1'; + niOOO1Ol <= '1'; + niOOOi1l <= '1'; + niOOOii <= '1'; + niOOOiiO <= '1'; + niOOOilO <= '1'; + niOOOl0O <= '1'; + niOOOliO <= '1'; + niOOOllO <= '1'; + niOOOlOO <= '1'; + niOOOO1O <= '1'; + niOOOOli <= '1'; + nl00li0i <= '1'; + nl00li0l <= '1'; + nl00li0O <= '1'; + nl00li1l <= '1'; + nl00li1O <= '1'; + nl00liii <= '1'; + nl00liil <= '1'; + nl00liiO <= '1'; + nl00lili <= '1'; + nl00lill <= '1'; + nl00lilO <= '1'; + nl00liOi <= '1'; + nl00liOl <= '1'; + nl00liOO <= '1'; + nl00ll0i <= '1'; + nl00ll0l <= '1'; + nl00ll0O <= '1'; + nl00ll1i <= '1'; + nl00ll1l <= '1'; + nl00ll1O <= '1'; + nl00llii <= '1'; + nl00llil <= '1'; + nl00lliO <= '1'; + nl00llli <= '1'; + nl00llll <= '1'; + nl00lllO <= '1'; + nl00llOi <= '1'; + nl00llOl <= '1'; + nl00llOO <= '1'; + nl00Ol1O <= '1'; + nl00Olil <= '1'; + nl00Olli <= '1'; + nl01010i <= '1'; + nl01010l <= '1'; + nl01010O <= '1'; + nl01011i <= '1'; + nl01011l <= '1'; + nl01011O <= '1'; + nl0101ii <= '1'; + nl0101il <= '1'; + nl0101iO <= '1'; + nl0101li <= '1'; + nl0101ll <= '1'; + nl0101lO <= '1'; + nl010OOl <= '1'; + nl011l0O <= '1'; + nl011lOi <= '1'; + nl011O0i <= '1'; + nl011O0l <= '1'; + nl011O0O <= '1'; + nl011O1i <= '1'; + nl011O1l <= '1'; + nl011O1O <= '1'; + nl011Oii <= '1'; + nl011Oil <= '1'; + nl011OiO <= '1'; + nl011Oli <= '1'; + nl011Oll <= '1'; + nl011OlO <= '1'; + nl011OOi <= '1'; + nl011OOl <= '1'; + nl011OOO <= '1'; + nl01i0ii <= '1'; + nl01i0lO <= '1'; + nl01i0Ol <= '1'; + nl01i10i <= '1'; + nl01i10O <= '1'; + nl01iiOi <= '1'; + nl01il1l <= '1'; + nl01illl <= '1'; + nl01li0i <= '1'; + nl01li0l <= '1'; + nl01li0O <= '1'; + nl01li1i <= '1'; + nl01li1l <= '1'; + nl01li1O <= '1'; + nl01liii <= '1'; + nl01liil <= '1'; + nl01liiO <= '1'; + nl01lili <= '1'; + nl01lill <= '1'; + nl01lilO <= '1'; + nl01liOi <= '1'; + nl01liOl <= '1'; + nl01liOO <= '1'; + nl01ll0i <= '1'; + nl01ll0l <= '1'; + nl01ll0O <= '1'; + nl01ll1i <= '1'; + nl01ll1l <= '1'; + nl01ll1O <= '1'; + nl01llii <= '1'; + nl01llil <= '1'; + nl01lliO <= '1'; + nl01llli <= '1'; + nl01llll <= '1'; + nl01lllO <= '1'; + nl01llOi <= '1'; + nl01llOl <= '1'; + nl01Ol1l <= '1'; + nl01Olii <= '1'; + nl01OliO <= '1'; + nl0il10l <= '1'; + nl0il10O <= '1'; + nl0il1ii <= '1'; + nl0il1il <= '1'; + nl0il1iO <= '1'; + nl0il1li <= '1'; + nl0iliii <= '1'; + nl0ilili <= '1'; + nl0ilill <= '1'; + nl0ililO <= '1'; + nl0iliOi <= '1'; + nl0iliOl <= '1'; + nl0iliOO <= '1'; + nl0ill0i <= '1'; + nl0ill0l <= '1'; + nl0ill0O <= '1'; + nl0ill1i <= '1'; + nl0ill1l <= '1'; + nl0ill1O <= '1'; + nl0illii <= '1'; + nl0illil <= '1'; + nl0illiO <= '1'; + nl0illli <= '1'; + nl0illll <= '1'; + nl0illlO <= '1'; + nl0illOi <= '1'; + nl0illOl <= '1'; + nl0iO0lO <= '1'; + nl0iO0Oi <= '1'; + nl0iO0Ol <= '1'; + nl0iO0OO <= '1'; + nl0iOi0i <= '1'; + nl0iOi0l <= '1'; + nl0iOi0O <= '1'; + nl0iOi1i <= '1'; + nl0iOi1l <= '1'; + nl0iOi1O <= '1'; + nl0iOiii <= '1'; + nl0iOiil <= '1'; + nl0iOiiO <= '1'; + nl0iOili <= '1'; + nl0iOill <= '1'; + nl0iOilO <= '1'; + nl0iOiOi <= '1'; + nl0iOiOl <= '1'; + nl0iOiOO <= '1'; + nl0iOl1i <= '1'; + nl0iOl1l <= '1'; + nl0iOl1O <= '1'; + nl0l0i0l <= '1'; + nl0l0i0O <= '1'; + nl0l0iii <= '1'; + nl0l0iil <= '1'; + nl0l0iiO <= '1'; + nl0l0ili <= '1'; + nl0l0OiO <= '1'; + nl0l0Oli <= '1'; + nl0l0Oll <= '1'; + nl0l0OlO <= '1'; + nl0l0OOi <= '1'; + nl0l0OOl <= '1'; + nl0l0OOO <= '1'; + nl0li10i <= '1'; + nl0li10l <= '1'; + nl0li10O <= '1'; + nl0li11i <= '1'; + nl0li11l <= '1'; + nl0li11O <= '1'; + nl0li1ii <= '1'; + nl0li1il <= '1'; + nl0li1iO <= '1'; + nl0li1li <= '1'; + nl0li1ll <= '1'; + nl0li1lO <= '1'; + nl0li1Oi <= '1'; + nl0lilll <= '1'; + nl0lillO <= '1'; + nl0lilOi <= '1'; + nl0lilOl <= '1'; + nl0lilOO <= '1'; + nl0liO0i <= '1'; + nl0liO0l <= '1'; + nl0liO0O <= '1'; + nl0liO1i <= '1'; + nl0liO1l <= '1'; + nl0liO1O <= '1'; + nl0liOii <= '1'; + nl0liOil <= '1'; + nl0liOiO <= '1'; + nl0liOli <= '1'; + nl0liOll <= '1'; + nl0liOlO <= '1'; + nl0liOOi <= '1'; + nl0liOOl <= '1'; + nl0liOOO <= '1'; + nl0ll11i <= '1'; + nl0ll11l <= '1'; + nl0lOOOi <= '1'; + nl0lOOOl <= '1'; + nl0lOOOO <= '1'; + nl0O100i <= '1'; + nl0O100l <= '1'; + nl0O100O <= '1'; + nl0O101i <= '1'; + nl0O101l <= '1'; + nl0O101O <= '1'; + nl0O10ii <= '1'; + nl0O10il <= '1'; + nl0O10iO <= '1'; + nl0O10li <= '1'; + nl0O10ll <= '1'; + nl0O10lO <= '1'; + nl0O10Oi <= '1'; + nl0O10Ol <= '1'; + nl0O10OO <= '1'; + nl0O110i <= '1'; + nl0O110l <= '1'; + nl0O110O <= '1'; + nl0O111i <= '1'; + nl0O111l <= '1'; + nl0O111O <= '1'; + nl0O11ii <= '1'; + nl0O11il <= '1'; + nl0O11iO <= '1'; + nl0O11li <= '1'; + nl0O11ll <= '1'; + nl0O11lO <= '1'; + nl0O11Oi <= '1'; + nl0O11Ol <= '1'; + nl0O11OO <= '1'; + nl0O1i0i <= '1'; + nl0O1i0l <= '1'; + nl0O1i0O <= '1'; + nl0O1i1i <= '1'; + nl0O1i1l <= '1'; + nl0O1i1O <= '1'; + nl0O1iii <= '1'; + nl0O1iil <= '1'; + nl0O1iiO <= '1'; + nl0O1ili <= '1'; + nl0O1ill <= '1'; + nl0O1ilO <= '1'; + nl0O1iOi <= '1'; + nl0O1iOl <= '1'; + nl0O1iOO <= '1'; + nl0O1l0i <= '1'; + nl0O1l0l <= '1'; + nl0O1l1i <= '1'; + nl0O1l1l <= '1'; + nl0O1l1O <= '1'; + nl0Ol0Ol <= '1'; + nl0Ol0OO <= '1'; + nl0Oli0i <= '1'; + nl0Oli0l <= '1'; + nl0Oli0O <= '1'; + nl0Oli1i <= '1'; + nl0Oli1l <= '1'; + nl0Oli1O <= '1'; + nl0Oliii <= '1'; + nl0Oliil <= '1'; + nl0OliiO <= '1'; + nl0OlO0O <= '1'; + nl0OlOll <= '1'; + nl0OlOOi <= '1'; + nl0OOl0i <= '1'; + nl0OOl0l <= '1'; + nl0OOl0O <= '1'; + nl0OOl1O <= '1'; + nl0OOO0i <= '1'; + nl0OOOiO <= '1'; + nl0OOOll <= '1'; + nl10001i <= '1'; + nl1000il <= '1'; + nl1000ll <= '1'; + nl1000lO <= '1'; + nl1000Oi <= '1'; + nl1000Ol <= '1'; + nl1000OO <= '1'; + nl100i0i <= '1'; + nl100i1i <= '1'; + nl100i1l <= '1'; + nl100i1O <= '1'; + nl10100O <= '1'; + nl10101O <= '1'; + nl1011ll <= '1'; + nl101i1l <= '1'; + nl101iii <= '1'; + nl101iiO <= '1'; + nl10i00i <= '1'; + nl10i01i <= '1'; + nl10i01l <= '1'; + nl10i01O <= '1'; + nl10i10l <= '1'; + nl10i1lO <= '1'; + nl10i1OO <= '1'; + nl10illO <= '1'; + nl10iO0i <= '1'; + nl10iOii <= '1'; + nl10iOil <= '1'; + nl10iOiO <= '1'; + nl10iOli <= '1'; + nl10iOll <= '1'; + nl10l01O <= '1'; + nl10l1lO <= '1'; + nl10l1OO <= '1'; + nl10llli <= '1'; + nl10lO0l <= '1'; + nl10lO0O <= '1'; + nl10lO1l <= '1'; + nl10lOii <= '1'; + nl10lOil <= '1'; + nl10lOiO <= '1'; + nl10lOli <= '1'; + nl10lOll <= '1'; + nl10lOlO <= '1'; + nl10O00O <= '1'; + nl10O01O <= '1'; + nl10O0iO <= '1'; + nl10O0lO <= '1'; + nl10O0OO <= '1'; + nl10Oi0O <= '1'; + nl10Oi1O <= '1'; + nl10OiiO <= '1'; + nl11000i <= '1'; + nl1100ii <= '1'; + nl1101lO <= '1'; + nl110i0l <= '1'; + nl110ilO <= '1'; + nl110iOO <= '1'; + nl110lOi <= '1'; + nl110O0l <= '1'; + nl110Oil <= '1'; + nl11101O <= '1'; + nl1110li <= '1'; + nl1110Oi <= '1'; + nl11110l <= '1'; + nl11111l <= '1'; + nl111ill <= '1'; + nl111l0O <= '1'; + nl111l1O <= '1'; + nl111O1O <= '1'; + nl111Oil <= '1'; + nl111Oli <= '1'; + nl11i01i <= '1'; + nl11i0Ol <= '1'; + nl11i10O <= '1'; + nl11i1Oi <= '1'; + nl11ii0O <= '1'; + nl11iiiO <= '1'; + nl11ilii <= '1'; + nl11ilOl <= '1'; + nl11iO1l <= '1'; + nl11iOOO <= '1'; + nl11l0ii <= '1'; + nl11l0lO <= '1'; + nl11l0Ol <= '1'; + nl11l1ii <= '1'; + nl11l1li <= '1'; + nl11liOO <= '1'; + nl11ll0l <= '1'; + nl11llii <= '1'; + nl11lOil <= '1'; + nl11lOOi <= '1'; + nl11lOOO <= '1'; + nl11O00O <= '1'; + nl11O01i <= '1'; + nl11O0il <= '1'; + nl11OiiO <= '1'; + nl11OiOl <= '1'; + nl11Ol1i <= '1'; + nl11OO0O <= '1'; + nl11OO1i <= '1'; + nl11OOil <= '1'; + nl1i010i <= '1'; + nl1i010l <= '1'; + nl1i010O <= '1'; + nl1i011i <= '1'; + nl1i011l <= '1'; + nl1i011O <= '1'; + nl1i01ii <= '1'; + nl1i01il <= '1'; + nl1i01iO <= '1'; + nl1i01li <= '1'; + nl1i01ll <= '1'; + nl1i01lO <= '1'; + nl1i01Oi <= '1'; + nl1i01Ol <= '1'; + nl1i01OO <= '1'; + nl1i1llO <= '1'; + nl1i1O0i <= '1'; + nl1i1Oii <= '1'; + nl1i1Oil <= '1'; + nl1i1OiO <= '1'; + nl1i1Oli <= '1'; + nl1i1Oll <= '1'; + nl1i1OlO <= '1'; + nl1i1OOi <= '1'; + nl1i1OOl <= '1'; + nl1i1OOO <= '1'; + nl1ii00i <= '1'; + nl1ii00l <= '1'; + nl1ii01O <= '1'; + nl1ii1il <= '1'; + nl1ii1OO <= '1'; + nl1iii0i <= '1'; + nl1iiiiO <= '1'; + nl1iiill <= '1'; + nl1iillO <= '1'; + nl1iiO0i <= '1'; + nl1iiO1l <= '1'; + nl1il00i <= '1'; + nl1il01l <= '1'; + nl1il10l <= '1'; + nl1il1lO <= '1'; + nl1iO00l <= '1'; + nl1iO0il <= '1'; + nl1iO0iO <= '1'; + nl1iO0li <= '1'; + nl1iO0ll <= '1'; + nl1iO0lO <= '1'; + nl1iO0Oi <= '1'; + nl1iO0Ol <= '1'; + nl1iO0OO <= '1'; + nl1iO1Oi <= '1'; + nl1iOi0i <= '1'; + nl1iOi0l <= '1'; + nl1iOi1i <= '1'; + nl1iOi1l <= '1'; + nl1iOi1O <= '1'; + nl1iOO0O <= '1'; + nl1iOOiO <= '1'; + nl1iOOlO <= '1'; + nl1l000l <= '1'; + nl1l00li <= '1'; + nl1l00lO <= '1'; + nl1l010i <= '1'; + nl1l011l <= '1'; + nl1l0iOi <= '1'; + nl1l0l0l <= '1'; + nl1l0l1O <= '1'; + nl1l0O1O <= '1'; + nl1l0Oii <= '1'; + nl1l0OOl <= '1'; + nl1l0OOO <= '1'; + nl1l10ll <= '1'; + nl1l111O <= '1'; + nl1l11il <= '1'; + nl1l11li <= '1'; + nl1l1i1i <= '1'; + nl1l1i1O <= '1'; + nl1l1l0i <= '1'; + nl1l1liO <= '1'; + nl1l1lll <= '1'; + nl1l1OlO <= '1'; + nl1li00i <= '1'; + nl1li01l <= '1'; + nl1li11i <= '1'; + nl1li1lO <= '1'; + nl1liiiO <= '1'; + nl1lil0i <= '1'; + nl1lil0l <= '1'; + nl1lil0O <= '1'; + nl1lil1O <= '1'; + nl1liO0i <= '1'; + nl1liOiO <= '1'; + nl1liOll <= '1'; + nl1ll00l <= '1'; + nl1ll0il <= '1'; + nl1ll0li <= '1'; + nl1llO1i <= '1'; + nl1llOil <= '1'; + nl1llOOi <= '1'; + nl1llOOO <= '1'; + nl1lO00l <= '1'; + nl1lO00O <= '1'; + nl1lO0ii <= '1'; + nl1lOi1O <= '1'; + nl1lOiil <= '1'; + nl1lOili <= '1'; + nl1O00ii <= '1'; + nl1O00li <= '1'; + nl1O01OO <= '1'; + nl1O0iil <= '1'; + nl1O0iOO <= '1'; + nl1O0l1O <= '1'; + nl1O0O1i <= '1'; + nl1O0Oil <= '1'; + nl1O0Oll <= '1'; + nl1O1i0O <= '1'; + nl1O1iOi <= '1'; + nl1O1l0i <= '1'; + nl1O1l1i <= '1'; + nl1O1l1l <= '1'; + nl1O1l1O <= '1'; + nl1O1O0l <= '1'; + nl1O1Oli <= '1'; + nl1O1OlO <= '1'; + nl1Oi00i <= '1'; + nl1Oi01i <= '1'; + nl1Oi0OO <= '1'; + nl1Oi1iO <= '1'; + nl1Oii0l <= '1'; + nl1Oiiii <= '1'; + nl1Oilil <= '1'; + nl1OilOi <= '1'; + nl1OilOO <= '1'; + nl1Ol0ll <= '1'; + nl1Ol11O <= '1'; + nl1Ol1li <= '1'; + nl1Ol1Oi <= '1'; + nl1Oli0O <= '1'; + nl1Oli1O <= '1'; + nl1Oll0i <= '1'; + nl1Ollll <= '1'; + nl1OllOl <= '1'; + nl1OlOlO <= '1'; + nl1OO10i <= '1'; + nl1OO1ii <= '1'; + nli0100i <= '1'; + nli0100l <= '1'; + nli0100O <= '1'; + nli0101i <= '1'; + nli0101l <= '1'; + nli0101O <= '1'; + nli010ii <= '1'; + nli010il <= '1'; + nli010iO <= '1'; + nli010li <= '1'; + nli010ll <= '1'; + nli010lO <= '1'; + nli010Oi <= '1'; + nli010Ol <= '1'; + nli010OO <= '1'; + nli0110i <= '1'; + nli0110l <= '1'; + nli0110O <= '1'; + nli0111i <= '1'; + nli0111l <= '1'; + nli0111O <= '1'; + nli011ii <= '1'; + nli011il <= '1'; + nli011iO <= '1'; + nli011li <= '1'; + nli011ll <= '1'; + nli011lO <= '1'; + nli011Oi <= '1'; + nli011Ol <= '1'; + nli011OO <= '1'; + nli01i0i <= '1'; + nli01i0l <= '1'; + nli01i0O <= '1'; + nli01i1i <= '1'; + nli01i1l <= '1'; + nli01i1O <= '1'; + nli01iii <= '1'; + nli01iil <= '1'; + nli01iiO <= '1'; + nli01ili <= '1'; + nli01ill <= '1'; + nli01ilO <= '1'; + nli01iOi <= '1'; + nli01iOl <= '1'; + nli1001i <= '1'; + nli1001l <= '1'; + nli1001O <= '1'; + nli1010i <= '1'; + nli1010l <= '1'; + nli1010O <= '1'; + nli1011i <= '1'; + nli1011l <= '1'; + nli1011O <= '1'; + nli101ii <= '1'; + nli101il <= '1'; + nli101iO <= '1'; + nli101li <= '1'; + nli101ll <= '1'; + nli101lO <= '1'; + nli101Oi <= '1'; + nli101Ol <= '1'; + nli101OO <= '1'; + nli1100l <= '1'; + nli110il <= '1'; + nli11l0i <= '1'; + nli11l0l <= '1'; + nli11l1O <= '1'; + nli11O0l <= '1'; + nli11Oli <= '1'; + nli11Oll <= '1'; + nli11OlO <= '1'; + nli11OOi <= '1'; + nli11OOl <= '1'; + nli11OOO <= '1'; + nli1l00i <= '1'; + nli1l0ii <= '1'; + nli1l0Ol <= '1'; + nli1l0OO <= '1'; + nli1li0i <= '1'; + nli1li0l <= '1'; + nli1li0O <= '1'; + nli1li1i <= '1'; + nli1li1l <= '1'; + nli1li1O <= '1'; + nli1liii <= '1'; + nli1liil <= '1'; + nli1liiO <= '1'; + nli1lili <= '1'; + nli1lill <= '1'; + nli1lilO <= '1'; + nli1liOi <= '1'; + nli1liOl <= '1'; + nli1liOO <= '1'; + nli1ll0i <= '1'; + nli1ll0l <= '1'; + nli1ll0O <= '1'; + nli1ll1i <= '1'; + nli1ll1l <= '1'; + nli1ll1O <= '1'; + nli1llii <= '1'; + nli1llil <= '1'; + nli1lliO <= '1'; + nli1llli <= '1'; + nli1llll <= '1'; + nli1lllO <= '1'; + nli1llOi <= '1'; + nli1llOl <= '1'; + nli1llOO <= '1'; + nli1lO0i <= '1'; + nli1lO0l <= '1'; + nli1lO0O <= '1'; + nli1lO1i <= '1'; + nli1lO1l <= '1'; + nli1lO1O <= '1'; + nli1lOii <= '1'; + nli1lOil <= '1'; + nli1lOiO <= '1'; + nli1lOli <= '1'; + nli1lOll <= '1'; + nli1lOlO <= '1'; + nli1lOOi <= '1'; + nli1lOOl <= '1'; + nli1lOOO <= '1'; + nli1O00i <= '1'; + nli1O00l <= '1'; + nli1O00O <= '1'; + nli1O01i <= '1'; + nli1O01l <= '1'; + nli1O01O <= '1'; + nli1O0ii <= '1'; + nli1O0il <= '1'; + nli1O0iO <= '1'; + nli1O0li <= '1'; + nli1O0ll <= '1'; + nli1O0lO <= '1'; + nli1O0Oi <= '1'; + nli1O0Ol <= '1'; + nli1O0OO <= '1'; + nli1O10i <= '1'; + nli1O10l <= '1'; + nli1O10O <= '1'; + nli1O11i <= '1'; + nli1O11l <= '1'; + nli1O11O <= '1'; + nli1O1ii <= '1'; + nli1O1il <= '1'; + nli1O1iO <= '1'; + nli1O1li <= '1'; + nli1O1ll <= '1'; + nli1O1lO <= '1'; + nli1O1Oi <= '1'; + nli1O1Ol <= '1'; + nli1O1OO <= '1'; + nli1Oi0i <= '1'; + nli1Oi0l <= '1'; + nli1Oi0O <= '1'; + nli1Oi1i <= '1'; + nli1Oi1l <= '1'; + nli1Oi1O <= '1'; + nli1Oiii <= '1'; + nli1Oiil <= '1'; + nli1OiiO <= '1'; + nli1Oili <= '1'; + nli1Oill <= '1'; + nli1OilO <= '1'; + nli1OiOi <= '1'; + nli1OiOl <= '1'; + nli1OiOO <= '1'; + nli1Ol0i <= '1'; + nli1Ol0l <= '1'; + nli1Ol0O <= '1'; + nli1Ol1i <= '1'; + nli1Ol1l <= '1'; + nli1Ol1O <= '1'; + nli1Olii <= '1'; + nli1Olil <= '1'; + nli1OliO <= '1'; + nli1Olli <= '1'; + nli1Olll <= '1'; + nli1OllO <= '1'; + nli1OlOi <= '1'; + nli1OlOl <= '1'; + nli1OlOO <= '1'; + nli1OO0i <= '1'; + nli1OO0l <= '1'; + nli1OO0O <= '1'; + nli1OO1i <= '1'; + nli1OO1l <= '1'; + nli1OO1O <= '1'; + nli1OOii <= '1'; + nli1OOil <= '1'; + nli1OOiO <= '1'; + nli1OOli <= '1'; + nli1OOll <= '1'; + nli1OOlO <= '1'; + nli1OOOi <= '1'; + nli1OOOl <= '1'; + nli1OOOO <= '1'; + nlll0lll <= '1'; + nllll0ll <= '1'; + nlllli0i <= '1'; + nlllli0l <= '1'; + nlllli0O <= '1'; + nlllli1i <= '1'; + nlllli1l <= '1'; + nlllli1O <= '1'; + nlllliii <= '1'; + nlllliil <= '1'; + nlllliiO <= '1'; + nllllili <= '1'; + nllllill <= '1'; + nllllilO <= '1'; + nlllliOi <= '1'; + nlllll0l <= '1'; + nlllll0O <= '1'; + nlllll1i <= '1'; + nlllll1l <= '1'; + nlllllii <= '1'; + nlllllil <= '1'; + nllllliO <= '1'; + nlllllli <= '1'; + nlllllll <= '1'; + ELSIF (wire_niOOO0O_CLRN = '0') THEN + n1l00il <= '0'; + n1lliil <= '0'; + n1lliiO <= '0'; + n1llili <= '0'; + ni0li0l <= '0'; + ni0li0O <= '0'; + ni0li1l <= '0'; + ni0liii <= '0'; + ni0liil <= '0'; + ni0liiO <= '0'; + ni0lili <= '0'; + ni0lill <= '0'; + ni0lilO <= '0'; + ni0O00i <= '0'; + ni0O00l <= '0'; + ni0O00O <= '0'; + ni0O01i <= '0'; + ni0O01l <= '0'; + ni0O01O <= '0'; + ni0O0ii <= '0'; + ni0O0il <= '0'; + ni0O0iO <= '0'; + ni0O0li <= '0'; + ni0O0ll <= '0'; + ni0O0lO <= '0'; + ni0O0Oi <= '0'; + ni0O0Ol <= '0'; + ni0O0OO <= '0'; + ni0O1li <= '0'; + ni0Oi0i <= '0'; + ni0Oi0l <= '0'; + ni0Oi0O <= '0'; + ni0Oi1i <= '0'; + ni0Oi1l <= '0'; + ni0Oi1O <= '0'; + ni0Oiii <= '0'; + ni0Oiil <= '0'; + ni0OiiO <= '0'; + ni0Oili <= '0'; + ni0Oill <= '0'; + ni0OilO <= '0'; + ni0OiOi <= '0'; + ni0OiOl <= '0'; + ni0OiOO <= '0'; + ni0Ol0i <= '0'; + ni0Ol0l <= '0'; + ni0Ol1i <= '0'; + ni0Ol1l <= '0'; + ni0Ol1O <= '0'; + niO010iO <= '0'; + niO010li <= '0'; + niO011iO <= '0'; + niO011li <= '0'; + niO01iiO <= '0'; + niO01ili <= '0'; + niOiil0i <= '0'; + niOiilll <= '0'; + niOiilOl <= '0'; + niOiilOO <= '0'; + niOiiO0i <= '0'; + niOiiO0l <= '0'; + niOiiO0O <= '0'; + niOiiO1i <= '0'; + niOiiO1l <= '0'; + niOiiO1O <= '0'; + niOiiOii <= '0'; + niOiiOil <= '0'; + niOiiOiO <= '0'; + niOiiOli <= '0'; + niOiiOll <= '0'; + niOiiOlO <= '0'; + niOiiOOi <= '0'; + niOiiOOl <= '0'; + niOiiOOO <= '0'; + niOil00i <= '0'; + niOil00l <= '0'; + niOil00O <= '0'; + niOil01i <= '0'; + niOil01l <= '0'; + niOil01O <= '0'; + niOil0ii <= '0'; + niOil0il <= '0'; + niOil0iO <= '0'; + niOil0li <= '0'; + niOil0ll <= '0'; + niOil0lO <= '0'; + niOil0Oi <= '0'; + niOil0Ol <= '0'; + niOil0OO <= '0'; + niOil10i <= '0'; + niOil10l <= '0'; + niOil10O <= '0'; + niOil11i <= '0'; + niOil11l <= '0'; + niOil11O <= '0'; + niOil1ii <= '0'; + niOil1il <= '0'; + niOil1iO <= '0'; + niOil1li <= '0'; + niOil1ll <= '0'; + niOil1lO <= '0'; + niOil1Oi <= '0'; + niOil1Ol <= '0'; + niOil1OO <= '0'; + niOiOii <= '0'; + niOiOlli <= '0'; + niOiOlll <= '0'; + niOiOllO <= '0'; + niOiOlOi <= '0'; + niOiOlOl <= '0'; + niOiOlOO <= '0'; + niOiOO0i <= '0'; + niOiOO0l <= '0'; + niOiOO0O <= '0'; + niOiOO1i <= '0'; + niOiOO1l <= '0'; + niOiOO1O <= '0'; + niOiOOii <= '0'; + niOiOOil <= '0'; + niOiOOiO <= '0'; + niOiOOli <= '0'; + niOiOOll <= '0'; + niOiOOlO <= '0'; + niOiOOOi <= '0'; + niOiOOOl <= '0'; + niOiOOOO <= '0'; + niOl100i <= '0'; + niOl100l <= '0'; + niOl100O <= '0'; + niOl101i <= '0'; + niOl101l <= '0'; + niOl101O <= '0'; + niOl10ii <= '0'; + niOl10il <= '0'; + niOl10iO <= '0'; + niOl10li <= '0'; + niOl10ll <= '0'; + niOl10lO <= '0'; + niOl10Oi <= '0'; + niOl110i <= '0'; + niOl110l <= '0'; + niOl110O <= '0'; + niOl111i <= '0'; + niOl111l <= '0'; + niOl111O <= '0'; + niOl11ii <= '0'; + niOl11il <= '0'; + niOl11iO <= '0'; + niOl11li <= '0'; + niOl11ll <= '0'; + niOl11lO <= '0'; + niOl11Oi <= '0'; + niOl11Ol <= '0'; + niOl11OO <= '0'; + niOlii1O <= '0'; + niOlOilO <= '0'; + niOlOl0i <= '0'; + niOlOlii <= '0'; + niOlOO0i <= '0'; + niOlOOll <= '0'; + niOlOOOl <= '0'; + niOO001l <= '0'; + niOO00iO <= '0'; + niOO00lO <= '0'; + niOO00O <= '0'; + niOO00Oi <= '0'; + niOO00Ol <= '0'; + niOO0ii <= '0'; + niOO0il <= '0'; + niOO0ill <= '0'; + niOO0iO <= '0'; + niOO0l0O <= '0'; + niOO0l1i <= '0'; + niOO0li <= '0'; + niOO0lil <= '0'; + niOO0ll <= '0'; + niOO0lO <= '0'; + niOO0Oi <= '0'; + niOO0OiO <= '0'; + niOO0Ol <= '0'; + niOO0Olil <= '0'; + niOO0OlOO <= '0'; + niOO0OO <= '0'; + niOO0OO0i <= '0'; + niOO0OO0l <= '0'; + niOO0OO0O <= '0'; + niOO0OO1O <= '0'; + niOO0OOii <= '0'; + niOO0OOil <= '0'; + niOO0OOiO <= '0'; + niOO0OOl <= '0'; + niOO100i <= '0'; + niOO10ii <= '0'; + niOO11lO <= '0'; + niOO1i0l <= '0'; + niOO1ilO <= '0'; + niOO1iOO <= '0'; + niOO1lOi <= '0'; + niOO1O0l <= '0'; + niOO1Oil <= '0'; + niOOi000i <= '0'; + niOOi000l <= '0'; + niOOi000O <= '0'; + niOOi001i <= '0'; + niOOi00ii <= '0'; + niOOi00il <= '0'; + niOOi00iO <= '0'; + niOOi00li <= '0'; + niOOi00ll <= '0'; + niOOi00lO <= '0'; + niOOi00Oi <= '0'; + niOOi00Ol <= '0'; + niOOi00OO <= '0'; + niOOi01iO <= '0'; + niOOi01l <= '0'; + niOOi0i <= '0'; + niOOi0i0i <= '0'; + niOOi0i0l <= '0'; + niOOi0i1i <= '0'; + niOOi0i1l <= '0'; + niOOi0i1O <= '0'; + niOOi0ii <= '0'; + niOOi0iO <= '0'; + niOOi0l <= '0'; + niOOi0O <= '0'; + niOOi11i <= '0'; + niOOi1i <= '0'; + niOOi1l <= '0'; + niOOi1O <= '0'; + niOOiii <= '0'; + niOOiil <= '0'; + niOOiiO <= '0'; + niOOili <= '0'; + niOOill <= '0'; + niOOilO <= '0'; + niOOiOi <= '0'; + niOOiOl <= '0'; + niOOiOO <= '0'; + niOOl00i <= '0'; + niOOl00l <= '0'; + niOOl00O <= '0'; + niOOl01i <= '0'; + niOOl0i <= '0'; + niOOl0ii <= '0'; + niOOl0il <= '0'; + niOOl0iO <= '0'; + niOOl0l <= '0'; + niOOl0li <= '0'; + niOOl0ll <= '0'; + niOOl0lO <= '0'; + niOOl0O <= '0'; + niOOl0Oi <= '0'; + niOOl0Ol <= '0'; + niOOl1i <= '0'; + niOOl1iO <= '0'; + niOOl1l <= '0'; + niOOl1O <= '0'; + niOOlii <= '0'; + niOOlil <= '0'; + niOOliO <= '0'; + niOOlli <= '0'; + niOOlll <= '0'; + niOOllO <= '0'; + niOOlO1i <= '0'; + niOOlOi <= '0'; + niOOlOil <= '0'; + niOOlOl <= '0'; + niOOlOll <= '0'; + niOOlOO <= '0'; + niOOO0i <= '0'; + niOOO0l <= '0'; + niOOO1i <= '0'; + niOOO1ii <= '0'; + niOOO1l <= '0'; + niOOO1lO <= '0'; + niOOO1O <= '0'; + niOOO1Ol <= '0'; + niOOOi1l <= '0'; + niOOOii <= '0'; + niOOOiiO <= '0'; + niOOOilO <= '0'; + niOOOl0O <= '0'; + niOOOliO <= '0'; + niOOOllO <= '0'; + niOOOlOO <= '0'; + niOOOO1O <= '0'; + niOOOOli <= '0'; + nl00li0i <= '0'; + nl00li0l <= '0'; + nl00li0O <= '0'; + nl00li1l <= '0'; + nl00li1O <= '0'; + nl00liii <= '0'; + nl00liil <= '0'; + nl00liiO <= '0'; + nl00lili <= '0'; + nl00lill <= '0'; + nl00lilO <= '0'; + nl00liOi <= '0'; + nl00liOl <= '0'; + nl00liOO <= '0'; + nl00ll0i <= '0'; + nl00ll0l <= '0'; + nl00ll0O <= '0'; + nl00ll1i <= '0'; + nl00ll1l <= '0'; + nl00ll1O <= '0'; + nl00llii <= '0'; + nl00llil <= '0'; + nl00lliO <= '0'; + nl00llli <= '0'; + nl00llll <= '0'; + nl00lllO <= '0'; + nl00llOi <= '0'; + nl00llOl <= '0'; + nl00llOO <= '0'; + nl00Ol1O <= '0'; + nl00Olil <= '0'; + nl00Olli <= '0'; + nl01010i <= '0'; + nl01010l <= '0'; + nl01010O <= '0'; + nl01011i <= '0'; + nl01011l <= '0'; + nl01011O <= '0'; + nl0101ii <= '0'; + nl0101il <= '0'; + nl0101iO <= '0'; + nl0101li <= '0'; + nl0101ll <= '0'; + nl0101lO <= '0'; + nl010OOl <= '0'; + nl011l0O <= '0'; + nl011lOi <= '0'; + nl011O0i <= '0'; + nl011O0l <= '0'; + nl011O0O <= '0'; + nl011O1i <= '0'; + nl011O1l <= '0'; + nl011O1O <= '0'; + nl011Oii <= '0'; + nl011Oil <= '0'; + nl011OiO <= '0'; + nl011Oli <= '0'; + nl011Oll <= '0'; + nl011OlO <= '0'; + nl011OOi <= '0'; + nl011OOl <= '0'; + nl011OOO <= '0'; + nl01i0ii <= '0'; + nl01i0lO <= '0'; + nl01i0Ol <= '0'; + nl01i10i <= '0'; + nl01i10O <= '0'; + nl01iiOi <= '0'; + nl01il1l <= '0'; + nl01illl <= '0'; + nl01li0i <= '0'; + nl01li0l <= '0'; + nl01li0O <= '0'; + nl01li1i <= '0'; + nl01li1l <= '0'; + nl01li1O <= '0'; + nl01liii <= '0'; + nl01liil <= '0'; + nl01liiO <= '0'; + nl01lili <= '0'; + nl01lill <= '0'; + nl01lilO <= '0'; + nl01liOi <= '0'; + nl01liOl <= '0'; + nl01liOO <= '0'; + nl01ll0i <= '0'; + nl01ll0l <= '0'; + nl01ll0O <= '0'; + nl01ll1i <= '0'; + nl01ll1l <= '0'; + nl01ll1O <= '0'; + nl01llii <= '0'; + nl01llil <= '0'; + nl01lliO <= '0'; + nl01llli <= '0'; + nl01llll <= '0'; + nl01lllO <= '0'; + nl01llOi <= '0'; + nl01llOl <= '0'; + nl01Ol1l <= '0'; + nl01Olii <= '0'; + nl01OliO <= '0'; + nl0il10l <= '0'; + nl0il10O <= '0'; + nl0il1ii <= '0'; + nl0il1il <= '0'; + nl0il1iO <= '0'; + nl0il1li <= '0'; + nl0iliii <= '0'; + nl0ilili <= '0'; + nl0ilill <= '0'; + nl0ililO <= '0'; + nl0iliOi <= '0'; + nl0iliOl <= '0'; + nl0iliOO <= '0'; + nl0ill0i <= '0'; + nl0ill0l <= '0'; + nl0ill0O <= '0'; + nl0ill1i <= '0'; + nl0ill1l <= '0'; + nl0ill1O <= '0'; + nl0illii <= '0'; + nl0illil <= '0'; + nl0illiO <= '0'; + nl0illli <= '0'; + nl0illll <= '0'; + nl0illlO <= '0'; + nl0illOi <= '0'; + nl0illOl <= '0'; + nl0iO0lO <= '0'; + nl0iO0Oi <= '0'; + nl0iO0Ol <= '0'; + nl0iO0OO <= '0'; + nl0iOi0i <= '0'; + nl0iOi0l <= '0'; + nl0iOi0O <= '0'; + nl0iOi1i <= '0'; + nl0iOi1l <= '0'; + nl0iOi1O <= '0'; + nl0iOiii <= '0'; + nl0iOiil <= '0'; + nl0iOiiO <= '0'; + nl0iOili <= '0'; + nl0iOill <= '0'; + nl0iOilO <= '0'; + nl0iOiOi <= '0'; + nl0iOiOl <= '0'; + nl0iOiOO <= '0'; + nl0iOl1i <= '0'; + nl0iOl1l <= '0'; + nl0iOl1O <= '0'; + nl0l0i0l <= '0'; + nl0l0i0O <= '0'; + nl0l0iii <= '0'; + nl0l0iil <= '0'; + nl0l0iiO <= '0'; + nl0l0ili <= '0'; + nl0l0OiO <= '0'; + nl0l0Oli <= '0'; + nl0l0Oll <= '0'; + nl0l0OlO <= '0'; + nl0l0OOi <= '0'; + nl0l0OOl <= '0'; + nl0l0OOO <= '0'; + nl0li10i <= '0'; + nl0li10l <= '0'; + nl0li10O <= '0'; + nl0li11i <= '0'; + nl0li11l <= '0'; + nl0li11O <= '0'; + nl0li1ii <= '0'; + nl0li1il <= '0'; + nl0li1iO <= '0'; + nl0li1li <= '0'; + nl0li1ll <= '0'; + nl0li1lO <= '0'; + nl0li1Oi <= '0'; + nl0lilll <= '0'; + nl0lillO <= '0'; + nl0lilOi <= '0'; + nl0lilOl <= '0'; + nl0lilOO <= '0'; + nl0liO0i <= '0'; + nl0liO0l <= '0'; + nl0liO0O <= '0'; + nl0liO1i <= '0'; + nl0liO1l <= '0'; + nl0liO1O <= '0'; + nl0liOii <= '0'; + nl0liOil <= '0'; + nl0liOiO <= '0'; + nl0liOli <= '0'; + nl0liOll <= '0'; + nl0liOlO <= '0'; + nl0liOOi <= '0'; + nl0liOOl <= '0'; + nl0liOOO <= '0'; + nl0ll11i <= '0'; + nl0ll11l <= '0'; + nl0lOOOi <= '0'; + nl0lOOOl <= '0'; + nl0lOOOO <= '0'; + nl0O100i <= '0'; + nl0O100l <= '0'; + nl0O100O <= '0'; + nl0O101i <= '0'; + nl0O101l <= '0'; + nl0O101O <= '0'; + nl0O10ii <= '0'; + nl0O10il <= '0'; + nl0O10iO <= '0'; + nl0O10li <= '0'; + nl0O10ll <= '0'; + nl0O10lO <= '0'; + nl0O10Oi <= '0'; + nl0O10Ol <= '0'; + nl0O10OO <= '0'; + nl0O110i <= '0'; + nl0O110l <= '0'; + nl0O110O <= '0'; + nl0O111i <= '0'; + nl0O111l <= '0'; + nl0O111O <= '0'; + nl0O11ii <= '0'; + nl0O11il <= '0'; + nl0O11iO <= '0'; + nl0O11li <= '0'; + nl0O11ll <= '0'; + nl0O11lO <= '0'; + nl0O11Oi <= '0'; + nl0O11Ol <= '0'; + nl0O11OO <= '0'; + nl0O1i0i <= '0'; + nl0O1i0l <= '0'; + nl0O1i0O <= '0'; + nl0O1i1i <= '0'; + nl0O1i1l <= '0'; + nl0O1i1O <= '0'; + nl0O1iii <= '0'; + nl0O1iil <= '0'; + nl0O1iiO <= '0'; + nl0O1ili <= '0'; + nl0O1ill <= '0'; + nl0O1ilO <= '0'; + nl0O1iOi <= '0'; + nl0O1iOl <= '0'; + nl0O1iOO <= '0'; + nl0O1l0i <= '0'; + nl0O1l0l <= '0'; + nl0O1l1i <= '0'; + nl0O1l1l <= '0'; + nl0O1l1O <= '0'; + nl0Ol0Ol <= '0'; + nl0Ol0OO <= '0'; + nl0Oli0i <= '0'; + nl0Oli0l <= '0'; + nl0Oli0O <= '0'; + nl0Oli1i <= '0'; + nl0Oli1l <= '0'; + nl0Oli1O <= '0'; + nl0Oliii <= '0'; + nl0Oliil <= '0'; + nl0OliiO <= '0'; + nl0OlO0O <= '0'; + nl0OlOll <= '0'; + nl0OlOOi <= '0'; + nl0OOl0i <= '0'; + nl0OOl0l <= '0'; + nl0OOl0O <= '0'; + nl0OOl1O <= '0'; + nl0OOO0i <= '0'; + nl0OOOiO <= '0'; + nl0OOOll <= '0'; + nl10001i <= '0'; + nl1000il <= '0'; + nl1000ll <= '0'; + nl1000lO <= '0'; + nl1000Oi <= '0'; + nl1000Ol <= '0'; + nl1000OO <= '0'; + nl100i0i <= '0'; + nl100i1i <= '0'; + nl100i1l <= '0'; + nl100i1O <= '0'; + nl10100O <= '0'; + nl10101O <= '0'; + nl1011ll <= '0'; + nl101i1l <= '0'; + nl101iii <= '0'; + nl101iiO <= '0'; + nl10i00i <= '0'; + nl10i01i <= '0'; + nl10i01l <= '0'; + nl10i01O <= '0'; + nl10i10l <= '0'; + nl10i1lO <= '0'; + nl10i1OO <= '0'; + nl10illO <= '0'; + nl10iO0i <= '0'; + nl10iOii <= '0'; + nl10iOil <= '0'; + nl10iOiO <= '0'; + nl10iOli <= '0'; + nl10iOll <= '0'; + nl10l01O <= '0'; + nl10l1lO <= '0'; + nl10l1OO <= '0'; + nl10llli <= '0'; + nl10lO0l <= '0'; + nl10lO0O <= '0'; + nl10lO1l <= '0'; + nl10lOii <= '0'; + nl10lOil <= '0'; + nl10lOiO <= '0'; + nl10lOli <= '0'; + nl10lOll <= '0'; + nl10lOlO <= '0'; + nl10O00O <= '0'; + nl10O01O <= '0'; + nl10O0iO <= '0'; + nl10O0lO <= '0'; + nl10O0OO <= '0'; + nl10Oi0O <= '0'; + nl10Oi1O <= '0'; + nl10OiiO <= '0'; + nl11000i <= '0'; + nl1100ii <= '0'; + nl1101lO <= '0'; + nl110i0l <= '0'; + nl110ilO <= '0'; + nl110iOO <= '0'; + nl110lOi <= '0'; + nl110O0l <= '0'; + nl110Oil <= '0'; + nl11101O <= '0'; + nl1110li <= '0'; + nl1110Oi <= '0'; + nl11110l <= '0'; + nl11111l <= '0'; + nl111ill <= '0'; + nl111l0O <= '0'; + nl111l1O <= '0'; + nl111O1O <= '0'; + nl111Oil <= '0'; + nl111Oli <= '0'; + nl11i01i <= '0'; + nl11i0Ol <= '0'; + nl11i10O <= '0'; + nl11i1Oi <= '0'; + nl11ii0O <= '0'; + nl11iiiO <= '0'; + nl11ilii <= '0'; + nl11ilOl <= '0'; + nl11iO1l <= '0'; + nl11iOOO <= '0'; + nl11l0ii <= '0'; + nl11l0lO <= '0'; + nl11l0Ol <= '0'; + nl11l1ii <= '0'; + nl11l1li <= '0'; + nl11liOO <= '0'; + nl11ll0l <= '0'; + nl11llii <= '0'; + nl11lOil <= '0'; + nl11lOOi <= '0'; + nl11lOOO <= '0'; + nl11O00O <= '0'; + nl11O01i <= '0'; + nl11O0il <= '0'; + nl11OiiO <= '0'; + nl11OiOl <= '0'; + nl11Ol1i <= '0'; + nl11OO0O <= '0'; + nl11OO1i <= '0'; + nl11OOil <= '0'; + nl1i010i <= '0'; + nl1i010l <= '0'; + nl1i010O <= '0'; + nl1i011i <= '0'; + nl1i011l <= '0'; + nl1i011O <= '0'; + nl1i01ii <= '0'; + nl1i01il <= '0'; + nl1i01iO <= '0'; + nl1i01li <= '0'; + nl1i01ll <= '0'; + nl1i01lO <= '0'; + nl1i01Oi <= '0'; + nl1i01Ol <= '0'; + nl1i01OO <= '0'; + nl1i1llO <= '0'; + nl1i1O0i <= '0'; + nl1i1Oii <= '0'; + nl1i1Oil <= '0'; + nl1i1OiO <= '0'; + nl1i1Oli <= '0'; + nl1i1Oll <= '0'; + nl1i1OlO <= '0'; + nl1i1OOi <= '0'; + nl1i1OOl <= '0'; + nl1i1OOO <= '0'; + nl1ii00i <= '0'; + nl1ii00l <= '0'; + nl1ii01O <= '0'; + nl1ii1il <= '0'; + nl1ii1OO <= '0'; + nl1iii0i <= '0'; + nl1iiiiO <= '0'; + nl1iiill <= '0'; + nl1iillO <= '0'; + nl1iiO0i <= '0'; + nl1iiO1l <= '0'; + nl1il00i <= '0'; + nl1il01l <= '0'; + nl1il10l <= '0'; + nl1il1lO <= '0'; + nl1iO00l <= '0'; + nl1iO0il <= '0'; + nl1iO0iO <= '0'; + nl1iO0li <= '0'; + nl1iO0ll <= '0'; + nl1iO0lO <= '0'; + nl1iO0Oi <= '0'; + nl1iO0Ol <= '0'; + nl1iO0OO <= '0'; + nl1iO1Oi <= '0'; + nl1iOi0i <= '0'; + nl1iOi0l <= '0'; + nl1iOi1i <= '0'; + nl1iOi1l <= '0'; + nl1iOi1O <= '0'; + nl1iOO0O <= '0'; + nl1iOOiO <= '0'; + nl1iOOlO <= '0'; + nl1l000l <= '0'; + nl1l00li <= '0'; + nl1l00lO <= '0'; + nl1l010i <= '0'; + nl1l011l <= '0'; + nl1l0iOi <= '0'; + nl1l0l0l <= '0'; + nl1l0l1O <= '0'; + nl1l0O1O <= '0'; + nl1l0Oii <= '0'; + nl1l0OOl <= '0'; + nl1l0OOO <= '0'; + nl1l10ll <= '0'; + nl1l111O <= '0'; + nl1l11il <= '0'; + nl1l11li <= '0'; + nl1l1i1i <= '0'; + nl1l1i1O <= '0'; + nl1l1l0i <= '0'; + nl1l1liO <= '0'; + nl1l1lll <= '0'; + nl1l1OlO <= '0'; + nl1li00i <= '0'; + nl1li01l <= '0'; + nl1li11i <= '0'; + nl1li1lO <= '0'; + nl1liiiO <= '0'; + nl1lil0i <= '0'; + nl1lil0l <= '0'; + nl1lil0O <= '0'; + nl1lil1O <= '0'; + nl1liO0i <= '0'; + nl1liOiO <= '0'; + nl1liOll <= '0'; + nl1ll00l <= '0'; + nl1ll0il <= '0'; + nl1ll0li <= '0'; + nl1llO1i <= '0'; + nl1llOil <= '0'; + nl1llOOi <= '0'; + nl1llOOO <= '0'; + nl1lO00l <= '0'; + nl1lO00O <= '0'; + nl1lO0ii <= '0'; + nl1lOi1O <= '0'; + nl1lOiil <= '0'; + nl1lOili <= '0'; + nl1O00ii <= '0'; + nl1O00li <= '0'; + nl1O01OO <= '0'; + nl1O0iil <= '0'; + nl1O0iOO <= '0'; + nl1O0l1O <= '0'; + nl1O0O1i <= '0'; + nl1O0Oil <= '0'; + nl1O0Oll <= '0'; + nl1O1i0O <= '0'; + nl1O1iOi <= '0'; + nl1O1l0i <= '0'; + nl1O1l1i <= '0'; + nl1O1l1l <= '0'; + nl1O1l1O <= '0'; + nl1O1O0l <= '0'; + nl1O1Oli <= '0'; + nl1O1OlO <= '0'; + nl1Oi00i <= '0'; + nl1Oi01i <= '0'; + nl1Oi0OO <= '0'; + nl1Oi1iO <= '0'; + nl1Oii0l <= '0'; + nl1Oiiii <= '0'; + nl1Oilil <= '0'; + nl1OilOi <= '0'; + nl1OilOO <= '0'; + nl1Ol0ll <= '0'; + nl1Ol11O <= '0'; + nl1Ol1li <= '0'; + nl1Ol1Oi <= '0'; + nl1Oli0O <= '0'; + nl1Oli1O <= '0'; + nl1Oll0i <= '0'; + nl1Ollll <= '0'; + nl1OllOl <= '0'; + nl1OlOlO <= '0'; + nl1OO10i <= '0'; + nl1OO1ii <= '0'; + nli0100i <= '0'; + nli0100l <= '0'; + nli0100O <= '0'; + nli0101i <= '0'; + nli0101l <= '0'; + nli0101O <= '0'; + nli010ii <= '0'; + nli010il <= '0'; + nli010iO <= '0'; + nli010li <= '0'; + nli010ll <= '0'; + nli010lO <= '0'; + nli010Oi <= '0'; + nli010Ol <= '0'; + nli010OO <= '0'; + nli0110i <= '0'; + nli0110l <= '0'; + nli0110O <= '0'; + nli0111i <= '0'; + nli0111l <= '0'; + nli0111O <= '0'; + nli011ii <= '0'; + nli011il <= '0'; + nli011iO <= '0'; + nli011li <= '0'; + nli011ll <= '0'; + nli011lO <= '0'; + nli011Oi <= '0'; + nli011Ol <= '0'; + nli011OO <= '0'; + nli01i0i <= '0'; + nli01i0l <= '0'; + nli01i0O <= '0'; + nli01i1i <= '0'; + nli01i1l <= '0'; + nli01i1O <= '0'; + nli01iii <= '0'; + nli01iil <= '0'; + nli01iiO <= '0'; + nli01ili <= '0'; + nli01ill <= '0'; + nli01ilO <= '0'; + nli01iOi <= '0'; + nli01iOl <= '0'; + nli1001i <= '0'; + nli1001l <= '0'; + nli1001O <= '0'; + nli1010i <= '0'; + nli1010l <= '0'; + nli1010O <= '0'; + nli1011i <= '0'; + nli1011l <= '0'; + nli1011O <= '0'; + nli101ii <= '0'; + nli101il <= '0'; + nli101iO <= '0'; + nli101li <= '0'; + nli101ll <= '0'; + nli101lO <= '0'; + nli101Oi <= '0'; + nli101Ol <= '0'; + nli101OO <= '0'; + nli1100l <= '0'; + nli110il <= '0'; + nli11l0i <= '0'; + nli11l0l <= '0'; + nli11l1O <= '0'; + nli11O0l <= '0'; + nli11Oli <= '0'; + nli11Oll <= '0'; + nli11OlO <= '0'; + nli11OOi <= '0'; + nli11OOl <= '0'; + nli11OOO <= '0'; + nli1l00i <= '0'; + nli1l0ii <= '0'; + nli1l0Ol <= '0'; + nli1l0OO <= '0'; + nli1li0i <= '0'; + nli1li0l <= '0'; + nli1li0O <= '0'; + nli1li1i <= '0'; + nli1li1l <= '0'; + nli1li1O <= '0'; + nli1liii <= '0'; + nli1liil <= '0'; + nli1liiO <= '0'; + nli1lili <= '0'; + nli1lill <= '0'; + nli1lilO <= '0'; + nli1liOi <= '0'; + nli1liOl <= '0'; + nli1liOO <= '0'; + nli1ll0i <= '0'; + nli1ll0l <= '0'; + nli1ll0O <= '0'; + nli1ll1i <= '0'; + nli1ll1l <= '0'; + nli1ll1O <= '0'; + nli1llii <= '0'; + nli1llil <= '0'; + nli1lliO <= '0'; + nli1llli <= '0'; + nli1llll <= '0'; + nli1lllO <= '0'; + nli1llOi <= '0'; + nli1llOl <= '0'; + nli1llOO <= '0'; + nli1lO0i <= '0'; + nli1lO0l <= '0'; + nli1lO0O <= '0'; + nli1lO1i <= '0'; + nli1lO1l <= '0'; + nli1lO1O <= '0'; + nli1lOii <= '0'; + nli1lOil <= '0'; + nli1lOiO <= '0'; + nli1lOli <= '0'; + nli1lOll <= '0'; + nli1lOlO <= '0'; + nli1lOOi <= '0'; + nli1lOOl <= '0'; + nli1lOOO <= '0'; + nli1O00i <= '0'; + nli1O00l <= '0'; + nli1O00O <= '0'; + nli1O01i <= '0'; + nli1O01l <= '0'; + nli1O01O <= '0'; + nli1O0ii <= '0'; + nli1O0il <= '0'; + nli1O0iO <= '0'; + nli1O0li <= '0'; + nli1O0ll <= '0'; + nli1O0lO <= '0'; + nli1O0Oi <= '0'; + nli1O0Ol <= '0'; + nli1O0OO <= '0'; + nli1O10i <= '0'; + nli1O10l <= '0'; + nli1O10O <= '0'; + nli1O11i <= '0'; + nli1O11l <= '0'; + nli1O11O <= '0'; + nli1O1ii <= '0'; + nli1O1il <= '0'; + nli1O1iO <= '0'; + nli1O1li <= '0'; + nli1O1ll <= '0'; + nli1O1lO <= '0'; + nli1O1Oi <= '0'; + nli1O1Ol <= '0'; + nli1O1OO <= '0'; + nli1Oi0i <= '0'; + nli1Oi0l <= '0'; + nli1Oi0O <= '0'; + nli1Oi1i <= '0'; + nli1Oi1l <= '0'; + nli1Oi1O <= '0'; + nli1Oiii <= '0'; + nli1Oiil <= '0'; + nli1OiiO <= '0'; + nli1Oili <= '0'; + nli1Oill <= '0'; + nli1OilO <= '0'; + nli1OiOi <= '0'; + nli1OiOl <= '0'; + nli1OiOO <= '0'; + nli1Ol0i <= '0'; + nli1Ol0l <= '0'; + nli1Ol0O <= '0'; + nli1Ol1i <= '0'; + nli1Ol1l <= '0'; + nli1Ol1O <= '0'; + nli1Olii <= '0'; + nli1Olil <= '0'; + nli1OliO <= '0'; + nli1Olli <= '0'; + nli1Olll <= '0'; + nli1OllO <= '0'; + nli1OlOi <= '0'; + nli1OlOl <= '0'; + nli1OlOO <= '0'; + nli1OO0i <= '0'; + nli1OO0l <= '0'; + nli1OO0O <= '0'; + nli1OO1i <= '0'; + nli1OO1l <= '0'; + nli1OO1O <= '0'; + nli1OOii <= '0'; + nli1OOil <= '0'; + nli1OOiO <= '0'; + nli1OOli <= '0'; + nli1OOll <= '0'; + nli1OOlO <= '0'; + nli1OOOi <= '0'; + nli1OOOl <= '0'; + nli1OOOO <= '0'; + nlll0lll <= '0'; + nllll0ll <= '0'; + nlllli0i <= '0'; + nlllli0l <= '0'; + nlllli0O <= '0'; + nlllli1i <= '0'; + nlllli1l <= '0'; + nlllli1O <= '0'; + nlllliii <= '0'; + nlllliil <= '0'; + nlllliiO <= '0'; + nllllili <= '0'; + nllllill <= '0'; + nllllilO <= '0'; + nlllliOi <= '0'; + nlllll0l <= '0'; + nlllll0O <= '0'; + nlllll1i <= '0'; + nlllll1l <= '0'; + nlllllii <= '0'; + nlllllil <= '0'; + nllllliO <= '0'; + nlllllli <= '0'; + nlllllll <= '0'; + ELSIF (pld_clk = '1' AND pld_clk'event) THEN + n1l00il <= wire_n1llill_dataout; + n1lliil <= wire_n1llilO_dataout; + n1lliiO <= wire_n1lliOi_dataout; + n1llili <= wire_n1lliOl_dataout; + ni0li0l <= wire_ni0liOO_dataout; + ni0li0O <= wire_ni0ll1i_dataout; + ni0li1l <= wire_ni0liOl_dataout; + ni0liii <= wire_ni0ll1l_dataout; + ni0liil <= wire_ni0ll1O_dataout; + ni0liiO <= wire_ni0ll0i_dataout; + ni0lili <= wire_ni0ll0l_dataout; + ni0lill <= wire_ni0ll0O_dataout; + ni0lilO <= wire_ni0llii_dataout; + ni0O00i <= wire_ni0Olll_dataout; + ni0O00l <= wire_ni0OllO_dataout; + ni0O00O <= wire_ni0OlOi_dataout; + ni0O01i <= wire_ni0Olil_dataout; + ni0O01l <= wire_ni0OliO_dataout; + ni0O01O <= wire_ni0Olli_dataout; + ni0O0ii <= wire_ni0OlOl_dataout; + ni0O0il <= wire_ni0OlOO_dataout; + ni0O0iO <= wire_ni0OO1i_dataout; + ni0O0li <= wire_ni0OO1l_dataout; + ni0O0ll <= wire_ni0OO1O_dataout; + ni0O0lO <= wire_ni0OO0i_dataout; + ni0O0Oi <= wire_ni0OO0l_dataout; + ni0O0Ol <= wire_ni0OO0O_dataout; + ni0O0OO <= wire_ni0OOii_dataout; + ni0O1li <= wire_ni0Olii_dataout; + ni0Oi0i <= wire_ni0OOll_dataout; + ni0Oi0l <= wire_ni0OOlO_dataout; + ni0Oi0O <= wire_ni0OOOi_dataout; + ni0Oi1i <= wire_ni0OOil_dataout; + ni0Oi1l <= wire_ni0OOiO_dataout; + ni0Oi1O <= wire_ni0OOli_dataout; + ni0Oiii <= wire_ni0OOOl_dataout; + ni0Oiil <= wire_ni0OOOO_dataout; + ni0OiiO <= wire_nii111i_dataout; + ni0Oili <= wire_nii111l_dataout; + ni0Oill <= wire_nii111O_dataout; + ni0OilO <= wire_nii110i_dataout; + ni0OiOi <= wire_nii110l_dataout; + ni0OiOl <= wire_nii110O_dataout; + ni0OiOO <= wire_nii11ii_dataout; + ni0Ol0i <= wire_nii11ll_dataout; + ni0Ol0l <= wire_nii11lO_dataout; + ni0Ol1i <= wire_nii11il_dataout; + ni0Ol1l <= wire_nii11iO_dataout; + ni0Ol1O <= wire_nii11li_dataout; + niO010iO <= niO010li; + niO010li <= niO010il; + niO011iO <= niO011li; + niO011li <= niO011il; + niO01iiO <= niO01ili; + niO01ili <= niO01iil; + niOiil0i <= wire_niOiilii_dataout; + niOiilll <= wire_niOili1i_dataout; + niOiilOl <= wire_niOili1l_dataout; + niOiilOO <= wire_niOili1O_dataout; + niOiiO0i <= wire_niOiliii_dataout; + niOiiO0l <= wire_niOiliil_dataout; + niOiiO0O <= wire_niOiliiO_dataout; + niOiiO1i <= wire_niOili0i_dataout; + niOiiO1l <= wire_niOili0l_dataout; + niOiiO1O <= wire_niOili0O_dataout; + niOiiOii <= wire_niOilili_dataout; + niOiiOil <= wire_niOilill_dataout; + niOiiOiO <= wire_niOililO_dataout; + niOiiOli <= wire_niOiliOi_dataout; + niOiiOll <= wire_niOiliOl_dataout; + niOiiOlO <= wire_niOiliOO_dataout; + niOiiOOi <= wire_niOill1i_dataout; + niOiiOOl <= wire_niOill1l_dataout; + niOiiOOO <= wire_niOill1O_dataout; + niOil00i <= wire_niOilOii_dataout; + niOil00l <= wire_niOilOil_dataout; + niOil00O <= wire_niOilOiO_dataout; + niOil01i <= wire_niOilO0i_dataout; + niOil01l <= wire_niOilO0l_dataout; + niOil01O <= wire_niOilO0O_dataout; + niOil0ii <= wire_niOilOli_dataout; + niOil0il <= wire_niOilOll_dataout; + niOil0iO <= wire_niOilOlO_dataout; + niOil0li <= wire_niOilOOi_dataout; + niOil0ll <= wire_niOilOOl_dataout; + niOil0lO <= wire_niOilOOO_dataout; + niOil0Oi <= wire_niOiO11i_dataout; + niOil0Ol <= wire_niOiO11l_dataout; + niOil0OO <= wire_niOiO11O_dataout; + niOil10i <= wire_niOillii_dataout; + niOil10l <= wire_niOillil_dataout; + niOil10O <= wire_niOilliO_dataout; + niOil11i <= wire_niOill0i_dataout; + niOil11l <= wire_niOill0l_dataout; + niOil11O <= wire_niOill0O_dataout; + niOil1ii <= wire_niOillli_dataout; + niOil1il <= wire_niOillll_dataout; + niOil1iO <= wire_niOilllO_dataout; + niOil1li <= wire_niOillOi_dataout; + niOil1ll <= wire_niOillOl_dataout; + niOil1lO <= wire_niOillOO_dataout; + niOil1Oi <= wire_niOilO1i_dataout; + niOil1Ol <= wire_niOilO1l_dataout; + niOil1OO <= wire_niOilO1O_dataout; + niOiOii <= wire_niOOOiO_dataout; + niOiOlli <= wire_niOl10OO_dataout; + niOiOlll <= wire_niOl1i1i_dataout; + niOiOllO <= wire_niOl1i1l_dataout; + niOiOlOi <= wire_niOl1i1O_dataout; + niOiOlOl <= wire_niOl1i0i_dataout; + niOiOlOO <= wire_niOl1i0l_dataout; + niOiOO0i <= wire_niOl1iiO_dataout; + niOiOO0l <= wire_niOl1ili_dataout; + niOiOO0O <= wire_niOl1ill_dataout; + niOiOO1i <= wire_niOl1i0O_dataout; + niOiOO1l <= wire_niOl1iii_dataout; + niOiOO1O <= wire_niOl1iil_dataout; + niOiOOii <= wire_niOl1ilO_dataout; + niOiOOil <= wire_niOl1iOi_dataout; + niOiOOiO <= wire_niOl1iOl_dataout; + niOiOOli <= wire_niOl1iOO_dataout; + niOiOOll <= wire_niOl1l1i_dataout; + niOiOOlO <= wire_niOl1l1l_dataout; + niOiOOOi <= wire_niOl1l1O_dataout; + niOiOOOl <= wire_niOl1l0i_dataout; + niOiOOOO <= wire_niOl1l0l_dataout; + niOl100i <= wire_niOl1OiO_dataout; + niOl100l <= wire_niOl1Oli_dataout; + niOl100O <= wire_niOl1Oll_dataout; + niOl101i <= wire_niOl1O0O_dataout; + niOl101l <= wire_niOl1Oii_dataout; + niOl101O <= wire_niOl1Oil_dataout; + niOl10ii <= wire_niOl1OlO_dataout; + niOl10il <= wire_niOl1OOi_dataout; + niOl10iO <= wire_niOl1OOl_dataout; + niOl10li <= wire_niOl1OOO_dataout; + niOl10ll <= wire_niOl011i_dataout; + niOl10lO <= wire_niOl011l_dataout; + niOl10Oi <= wire_niOl011O_dataout; + niOl110i <= wire_niOl1liO_dataout; + niOl110l <= wire_niOl1lli_dataout; + niOl110O <= wire_niOl1lll_dataout; + niOl111i <= wire_niOl1l0O_dataout; + niOl111l <= wire_niOl1lii_dataout; + niOl111O <= wire_niOl1lil_dataout; + niOl11ii <= wire_niOl1llO_dataout; + niOl11il <= wire_niOl1lOi_dataout; + niOl11iO <= wire_niOl1lOl_dataout; + niOl11li <= wire_niOl1lOO_dataout; + niOl11ll <= wire_niOl1O1i_dataout; + niOl11lO <= wire_niOl1O1l_dataout; + niOl11Oi <= wire_niOl1O1O_dataout; + niOl11Ol <= wire_niOl1O0i_dataout; + niOl11OO <= wire_niOl1O0l_dataout; + niOlii1O <= wire_niOl10Ol_dataout; + niOlOilO <= wire_niOlOiOO_dataout; + niOlOl0i <= wire_niOlOlil_dataout; + niOlOlii <= wire_niOlOliO_dataout; + niOlOO0i <= wire_niOlOOii_dataout; + niOlOOll <= wire_niOlOOOO_dataout; + niOlOOOl <= wire_niOO111i_dataout; + niOO001l <= wire_niOO000l_dataout; + niOO00iO <= wire_niOO00OO_dataout; + niOO00lO <= wire_niOO0i1i_dataout; + niOO00O <= wire_niOOOli_dataout; + niOO00Oi <= wire_niOO0i1l_dataout; + niOO00Ol <= wire_niOO0i1O_dataout; + niOO0ii <= wire_niOOOll_dataout; + niOO0il <= wire_niOOOlO_dataout; + niOO0ill <= tl_slotclk_cfg; + niOO0iO <= wire_niOOOOi_dataout; + niOO0l0O <= wire_niOO0lli_dataout; + niOO0l1i <= wire_niOO0iOl_dataout; + niOO0li <= wire_niOOOOl_dataout; + niOO0lil <= wire_niOO0lll_dataout; + niOO0ll <= wire_niOOOOO_dataout; + niOO0lO <= wire_nl1111i_dataout; + niOO0Oi <= wire_nl1111l_dataout; + niOO0OiO <= wire_niOO0Oii_dataout; + niOO0Ol <= wire_nl1111O_dataout; + niOO0Olil <= wire_niOO0Olll_dataout; + niOO0OlOO <= wire_niOO0OOli_dataout; + niOO0OO <= wire_nl1110i_dataout; + niOO0OO0i <= wire_niOO0OOlO_dataout; + niOO0OO0l <= wire_niOO0OOOi_dataout; + niOO0OO0O <= wire_niOO0OOOl_dataout; + niOO0OO1O <= wire_niOO0OOll_dataout; + niOO0OOii <= wire_niOO0OOOO_dataout; + niOO0OOil <= wire_niOOi111i_dataout; + niOO0OOiO <= wire_niOOi111l_dataout; + niOO0OOl <= wire_niOOi11O_dataout; + niOO100i <= wire_niOO10il_dataout; + niOO10ii <= wire_niOO10iO_dataout; + niOO11lO <= wire_niOO11OO_dataout; + niOO1i0l <= wire_niOO1iil_dataout; + niOO1ilO <= wire_niOO1l1i_dataout; + niOO1iOO <= wire_niOO1l1l_dataout; + niOO1lOi <= wire_niOO1O1i_dataout; + niOO1O0l <= wire_niOO1OiO_dataout; + niOO1Oil <= wire_niOO1Oli_dataout; + niOOi000i <= wire_niOOi0iii_dataout; + niOOi000l <= wire_niOOi0iil_dataout; + niOOi000O <= wire_niOOi0iiO_dataout; + niOOi001i <= wire_niOOi0i0O_dataout; + niOOi00ii <= wire_niOOi0ili_dataout; + niOOi00il <= wire_niOOi0ill_dataout; + niOOi00iO <= wire_niOOi0ilO_dataout; + niOOi00li <= wire_niOOi0iOi_dataout; + niOOi00ll <= wire_niOOi0iOl_dataout; + niOOi00lO <= wire_niOOi0iOO_dataout; + niOOi00Oi <= wire_niOOi0l1i_dataout; + niOOi00Ol <= wire_niOOi0l1l_dataout; + niOOi00OO <= wire_niOOi0l1O_dataout; + niOOi01iO <= wire_niOOi01lO_dataout; + niOOi01l <= wire_niOOi1OO_dataout; + niOOi0i <= wire_nl111il_dataout; + niOOi0i0i <= wire_niOOi0lii_dataout; + niOOi0i0l <= wire_niOOi0lil_dataout; + niOOi0i1i <= wire_niOOi0l0i_dataout; + niOOi0i1l <= wire_niOOi0l0l_dataout; + niOOi0i1O <= wire_niOOi0l0O_dataout; + niOOi0ii <= wire_niOOi0ll_dataout; + niOOi0iO <= wire_niOOi0lO_dataout; + niOOi0l <= wire_nl111iO_dataout; + niOOi0O <= wire_nl111li_dataout; + niOOi11i <= wire_niOOi10i_dataout; + niOOi1i <= wire_nl1110l_dataout; + niOOi1l <= wire_nl1110O_dataout; + niOOi1O <= wire_nl111ii_dataout; + niOOiii <= wire_nl111ll_dataout; + niOOiil <= wire_nl111lO_dataout; + niOOiiO <= wire_nl111Oi_dataout; + niOOili <= wire_nl111Ol_dataout; + niOOill <= wire_nl111OO_dataout; + niOOilO <= wire_nl1101i_dataout; + niOOiOi <= wire_nl1101l_dataout; + niOOiOl <= wire_nl1101O_dataout; + niOOiOO <= wire_nl1100i_dataout; + niOOl00i <= wire_niOOli1i_dataout; + niOOl00l <= wire_niOOli1l_dataout; + niOOl00O <= wire_niOOli1O_dataout; + niOOl01i <= wire_niOOl0OO_dataout; + niOOl0i <= wire_nl110il_dataout; + niOOl0ii <= wire_niOOli0i_dataout; + niOOl0il <= wire_niOOli0l_dataout; + niOOl0iO <= wire_niOOli0O_dataout; + niOOl0l <= wire_nl110iO_dataout; + niOOl0li <= wire_niOOliii_dataout; + niOOl0ll <= wire_niOOliil_dataout; + niOOl0lO <= wire_niOOliiO_dataout; + niOOl0O <= wire_nl110li_dataout; + niOOl0Oi <= wire_niOOlili_dataout; + niOOl0Ol <= wire_niOOlill_dataout; + niOOl1i <= wire_nl1100l_dataout; + niOOl1iO <= wire_niOOl1lO_dataout; + niOOl1l <= wire_nl1100O_dataout; + niOOl1O <= wire_nl110ii_dataout; + niOOlii <= wire_nl110ll_dataout; + niOOlil <= wire_nl110lO_dataout; + niOOliO <= wire_nl110Oi_dataout; + niOOlli <= wire_nl110Ol_dataout; + niOOlll <= wire_nl110OO_dataout; + niOOllO <= wire_nl11i1i_dataout; + niOOlO1i <= wire_niOOlO0i_dataout; + niOOlOi <= wire_nl11i1l_dataout; + niOOlOil <= wire_niOOlOlO_dataout; + niOOlOl <= wire_nl11i1O_dataout; + niOOlOll <= wire_niOOlOOi_dataout; + niOOlOO <= wire_nl11i0i_dataout; + niOOO0i <= wire_nl11iil_dataout; + niOOO0l <= wire_nl11iiO_dataout; + niOOO1i <= wire_nl11i0l_dataout; + niOOO1ii <= wire_niOOO10l_dataout; + niOOO1l <= wire_nl11i0O_dataout; + niOOO1lO <= wire_niOOO01i_dataout; + niOOO1O <= wire_nl11iii_dataout; + niOOO1Ol <= wire_niOOO01l_dataout; + niOOOi1l <= wire_niOOOi0l_dataout; + niOOOii <= wire_nl11ili_dataout; + niOOOiiO <= wire_niOOOiOi_dataout; + niOOOilO <= wire_niOOOiOl_dataout; + niOOOl0O <= tl_hpg_ctrler(0); + niOOOliO <= tl_hpg_ctrler(1); + niOOOllO <= tl_hpg_ctrler(2); + niOOOlOO <= tl_hpg_ctrler(3); + niOOOO1O <= tl_hpg_ctrler(4); + niOOOOli <= wire_niOOOOOi_dataout; + nl00li0i <= wire_nl00lO0l_dataout; + nl00li0l <= wire_nl00lO0O_dataout; + nl00li0O <= wire_nl00lOii_dataout; + nl00li1l <= wire_nl00lO1O_dataout; + nl00li1O <= wire_nl00lO0i_dataout; + nl00liii <= wire_nl00lOil_dataout; + nl00liil <= wire_nl00lOiO_dataout; + nl00liiO <= wire_nl00lOli_dataout; + nl00lili <= wire_nl00lOll_dataout; + nl00lill <= wire_nl00lOlO_dataout; + nl00lilO <= wire_nl00lOOi_dataout; + nl00liOi <= wire_nl00lOOl_dataout; + nl00liOl <= wire_nl00lOOO_dataout; + nl00liOO <= wire_nl00O11i_dataout; + nl00ll0i <= wire_nl00O10l_dataout; + nl00ll0l <= wire_nl00O10O_dataout; + nl00ll0O <= wire_nl00O1ii_dataout; + nl00ll1i <= wire_nl00O11l_dataout; + nl00ll1l <= wire_nl00O11O_dataout; + nl00ll1O <= wire_nl00O10i_dataout; + nl00llii <= wire_nl00O1il_dataout; + nl00llil <= wire_nl00O1iO_dataout; + nl00lliO <= wire_nl00O1li_dataout; + nl00llli <= wire_nl00O1ll_dataout; + nl00llll <= wire_nl00O1lO_dataout; + nl00lllO <= wire_nl00O1Oi_dataout; + nl00llOi <= wire_nl00O1Ol_dataout; + nl00llOl <= wire_nl00O1OO_dataout; + nl00llOO <= wire_nl00O01i_dataout; + nl00Ol1O <= wire_nl00lO1l_dataout; + nl00Olil <= wire_nl00OllO_dataout; + nl00Olli <= wire_nl00OlOi_dataout; + nl01010i <= wire_nl010i1l_dataout; + nl01010l <= wire_nl010i1O_dataout; + nl01010O <= wire_nl010i0i_dataout; + nl01011i <= wire_nl0100Ol_dataout; + nl01011l <= wire_nl0100OO_dataout; + nl01011O <= wire_nl010i1i_dataout; + nl0101ii <= wire_nl010i0l_dataout; + nl0101il <= wire_nl010i0O_dataout; + nl0101iO <= wire_nl010iii_dataout; + nl0101li <= wire_nl010iil_dataout; + nl0101ll <= wire_nl010iiO_dataout; + nl0101lO <= wire_nl010ili_dataout; + nl010OOl <= wire_nl010OlO_dataout; + nl011l0O <= wire_nl011liO_dataout; + nl011lOi <= wire_nl0101Oi_dataout; + nl011O0i <= wire_nl01001l_dataout; + nl011O0l <= wire_nl01001O_dataout; + nl011O0O <= wire_nl01000i_dataout; + nl011O1i <= wire_nl0101Ol_dataout; + nl011O1l <= wire_nl0101OO_dataout; + nl011O1O <= wire_nl01001i_dataout; + nl011Oii <= wire_nl01000l_dataout; + nl011Oil <= wire_nl01000O_dataout; + nl011OiO <= wire_nl0100ii_dataout; + nl011Oli <= wire_nl0100il_dataout; + nl011Oll <= wire_nl0100iO_dataout; + nl011OlO <= wire_nl0100li_dataout; + nl011OOi <= wire_nl0100ll_dataout; + nl011OOl <= wire_nl0100lO_dataout; + nl011OOO <= wire_nl0100Oi_dataout; + nl01i0ii <= wire_nl01i00l_dataout; + nl01i0lO <= wire_nl01ii1i_dataout; + nl01i0Ol <= wire_nl01ii1l_dataout; + nl01i10i <= wire_nl01i1il_dataout; + nl01i10O <= wire_nl01i1iO_dataout; + nl01iiOi <= nl01iiOl; + nl01il1l <= wire_nl01il0l_dataout; + nl01illl <= wire_nl01il0i_dataout; + nl01li0i <= wire_nl01lO0l_dataout; + nl01li0l <= wire_nl01lO0O_dataout; + nl01li0O <= wire_nl01lOii_dataout; + nl01li1i <= wire_nl01lO1l_dataout; + nl01li1l <= wire_nl01lO1O_dataout; + nl01li1O <= wire_nl01lO0i_dataout; + nl01liii <= wire_nl01lOil_dataout; + nl01liil <= wire_nl01lOiO_dataout; + nl01liiO <= wire_nl01lOli_dataout; + nl01lili <= wire_nl01lOll_dataout; + nl01lill <= wire_nl01lOlO_dataout; + nl01lilO <= wire_nl01lOOi_dataout; + nl01liOi <= wire_nl01lOOl_dataout; + nl01liOl <= wire_nl01lOOO_dataout; + nl01liOO <= wire_nl01O11i_dataout; + nl01ll0i <= wire_nl01O10l_dataout; + nl01ll0l <= wire_nl01O10O_dataout; + nl01ll0O <= wire_nl01O1ii_dataout; + nl01ll1i <= wire_nl01O11l_dataout; + nl01ll1l <= wire_nl01O11O_dataout; + nl01ll1O <= wire_nl01O10i_dataout; + nl01llii <= wire_nl01O1il_dataout; + nl01llil <= wire_nl01O1iO_dataout; + nl01lliO <= wire_nl01O1li_dataout; + nl01llli <= wire_nl01O1ll_dataout; + nl01llll <= wire_nl01O1lO_dataout; + nl01lllO <= wire_nl01O1Oi_dataout; + nl01llOi <= wire_nl01O1Ol_dataout; + nl01llOl <= wire_nl01O1OO_dataout; + nl01Ol1l <= wire_nl01lO1i_dataout; + nl01Olii <= wire_nl01Olll_dataout; + nl01OliO <= wire_nl01OllO_dataout; + nl0il10l <= wire_nl0il1lO_dataout; + nl0il10O <= wire_nl0il1Oi_dataout; + nl0il1ii <= wire_nl0il1Ol_dataout; + nl0il1il <= wire_nl0il1OO_dataout; + nl0il1iO <= wire_nl0il01i_dataout; + nl0il1li <= wire_nl0illOO_dataout; + nl0iliii <= wire_nl0il1ll_dataout; + nl0ilili <= wire_nl0ilO1i_dataout; + nl0ilill <= wire_nl0ilO1l_dataout; + nl0ililO <= wire_nl0ilO1O_dataout; + nl0iliOi <= wire_nl0ilO0i_dataout; + nl0iliOl <= wire_nl0ilO0l_dataout; + nl0iliOO <= wire_nl0ilO0O_dataout; + nl0ill0i <= wire_nl0ilOli_dataout; + nl0ill0l <= wire_nl0ilOll_dataout; + nl0ill0O <= wire_nl0ilOlO_dataout; + nl0ill1i <= wire_nl0ilOii_dataout; + nl0ill1l <= wire_nl0ilOil_dataout; + nl0ill1O <= wire_nl0ilOiO_dataout; + nl0illii <= wire_nl0ilOOi_dataout; + nl0illil <= wire_nl0ilOOl_dataout; + nl0illiO <= wire_nl0ilOOO_dataout; + nl0illli <= wire_nl0iO11i_dataout; + nl0illll <= wire_nl0iO11l_dataout; + nl0illlO <= wire_nl0iO11O_dataout; + nl0illOi <= wire_nl0iO10i_dataout; + nl0illOl <= wire_nl0iOl0i_dataout; + nl0iO0lO <= wire_nl0iOl0l_dataout; + nl0iO0Oi <= wire_nl0iOl0O_dataout; + nl0iO0Ol <= wire_nl0iOlii_dataout; + nl0iO0OO <= wire_nl0iOlil_dataout; + nl0iOi0i <= wire_nl0iOllO_dataout; + nl0iOi0l <= wire_nl0iOlOi_dataout; + nl0iOi0O <= wire_nl0iOlOl_dataout; + nl0iOi1i <= wire_nl0iOliO_dataout; + nl0iOi1l <= wire_nl0iOlli_dataout; + nl0iOi1O <= wire_nl0iOlll_dataout; + nl0iOiii <= wire_nl0iOlOO_dataout; + nl0iOiil <= wire_nl0iOO1i_dataout; + nl0iOiiO <= wire_nl0iOO1l_dataout; + nl0iOili <= wire_nl0iOO1O_dataout; + nl0iOill <= wire_nl0iOO0i_dataout; + nl0iOilO <= wire_nl0iOO0l_dataout; + nl0iOiOi <= wire_nl0iOO0O_dataout; + nl0iOiOl <= wire_nl0iOOii_dataout; + nl0iOiOO <= wire_nl0iOOil_dataout; + nl0iOl1i <= wire_nl0iOOiO_dataout; + nl0iOl1l <= wire_nl0iOOli_dataout; + nl0iOl1O <= wire_nl0l0ill_dataout; + nl0l0i0l <= wire_nl0l0ilO_dataout; + nl0l0i0O <= wire_nl0l0iOi_dataout; + nl0l0iii <= wire_nl0l0iOl_dataout; + nl0l0iil <= wire_nl0l0iOO_dataout; + nl0l0iiO <= wire_nl0l0l1i_dataout; + nl0l0ili <= wire_nl0li1Ol_dataout; + nl0l0OiO <= wire_nl0li1OO_dataout; + nl0l0Oli <= wire_nl0li01i_dataout; + nl0l0Oll <= wire_nl0li01l_dataout; + nl0l0OlO <= wire_nl0li01O_dataout; + nl0l0OOi <= wire_nl0li00i_dataout; + nl0l0OOl <= wire_nl0li00l_dataout; + nl0l0OOO <= wire_nl0li00O_dataout; + nl0li10i <= wire_nl0li0li_dataout; + nl0li10l <= wire_nl0li0ll_dataout; + nl0li10O <= wire_nl0li0lO_dataout; + nl0li11i <= wire_nl0li0ii_dataout; + nl0li11l <= wire_nl0li0il_dataout; + nl0li11O <= wire_nl0li0iO_dataout; + nl0li1ii <= wire_nl0li0Oi_dataout; + nl0li1il <= wire_nl0li0Ol_dataout; + nl0li1iO <= wire_nl0li0OO_dataout; + nl0li1li <= wire_nl0lii1i_dataout; + nl0li1ll <= wire_nl0lii1l_dataout; + nl0li1lO <= wire_nl0lii1O_dataout; + nl0li1Oi <= wire_nl0ll11O_dataout; + nl0lilll <= wire_nl0ll10i_dataout; + nl0lillO <= wire_nl0ll10l_dataout; + nl0lilOi <= wire_nl0ll10O_dataout; + nl0lilOl <= wire_nl0ll1ii_dataout; + nl0lilOO <= wire_nl0ll1il_dataout; + nl0liO0i <= wire_nl0ll1lO_dataout; + nl0liO0l <= wire_nl0ll1Oi_dataout; + nl0liO0O <= wire_nl0ll1Ol_dataout; + nl0liO1i <= wire_nl0ll1iO_dataout; + nl0liO1l <= wire_nl0ll1li_dataout; + nl0liO1O <= wire_nl0ll1ll_dataout; + nl0liOii <= wire_nl0ll1OO_dataout; + nl0liOil <= wire_nl0ll01i_dataout; + nl0liOiO <= wire_nl0ll01l_dataout; + nl0liOli <= wire_nl0ll01O_dataout; + nl0liOll <= wire_nl0ll00i_dataout; + nl0liOlO <= wire_nl0ll00l_dataout; + nl0liOOi <= wire_nl0ll00O_dataout; + nl0liOOl <= wire_nl0ll0ii_dataout; + nl0liOOO <= wire_nl0ll0il_dataout; + nl0ll11i <= wire_nl0ll0iO_dataout; + nl0ll11l <= wire_nl0O1lii_dataout; + nl0lOOOi <= wire_nl0O1lil_dataout; + nl0lOOOl <= wire_nl0O1liO_dataout; + nl0lOOOO <= wire_nl0O1lli_dataout; + nl0O100i <= wire_nl0O1OOl_dataout; + nl0O100l <= wire_nl0O1OOO_dataout; + nl0O100O <= wire_nl0O011i_dataout; + nl0O101i <= wire_nl0O1Oll_dataout; + nl0O101l <= wire_nl0O1OlO_dataout; + nl0O101O <= wire_nl0O1OOi_dataout; + nl0O10ii <= wire_nl0O011l_dataout; + nl0O10il <= wire_nl0O011O_dataout; + nl0O10iO <= wire_nl0O010i_dataout; + nl0O10li <= wire_nl0O010l_dataout; + nl0O10ll <= wire_nl0O010O_dataout; + nl0O10lO <= wire_nl0O01ii_dataout; + nl0O10Oi <= wire_nl0O01il_dataout; + nl0O10Ol <= wire_nl0O01iO_dataout; + nl0O10OO <= wire_nl0O01li_dataout; + nl0O110i <= wire_nl0O1lOl_dataout; + nl0O110l <= wire_nl0O1lOO_dataout; + nl0O110O <= wire_nl0O1O1i_dataout; + nl0O111i <= wire_nl0O1lll_dataout; + nl0O111l <= wire_nl0O1llO_dataout; + nl0O111O <= wire_nl0O1lOi_dataout; + nl0O11ii <= wire_nl0O1O1l_dataout; + nl0O11il <= wire_nl0O1O1O_dataout; + nl0O11iO <= wire_nl0O1O0i_dataout; + nl0O11li <= wire_nl0O1O0l_dataout; + nl0O11ll <= wire_nl0O1O0O_dataout; + nl0O11lO <= wire_nl0O1Oii_dataout; + nl0O11Oi <= wire_nl0O1Oil_dataout; + nl0O11Ol <= wire_nl0O1OiO_dataout; + nl0O11OO <= wire_nl0O1Oli_dataout; + nl0O1i0i <= wire_nl0O01Ol_dataout; + nl0O1i0l <= wire_nl0O01OO_dataout; + nl0O1i0O <= wire_nl0O001i_dataout; + nl0O1i1i <= wire_nl0O01ll_dataout; + nl0O1i1l <= wire_nl0O01lO_dataout; + nl0O1i1O <= wire_nl0O01Oi_dataout; + nl0O1iii <= wire_nl0O001l_dataout; + nl0O1iil <= wire_nl0O001O_dataout; + nl0O1iiO <= wire_nl0O000i_dataout; + nl0O1ili <= wire_nl0O000l_dataout; + nl0O1ill <= wire_nl0O000O_dataout; + nl0O1ilO <= wire_nl0O00ii_dataout; + nl0O1iOi <= wire_nl0O00il_dataout; + nl0O1iOl <= wire_nl0O00iO_dataout; + nl0O1iOO <= wire_nl0O00li_dataout; + nl0O1l0i <= wire_nl0O00Ol_dataout; + nl0O1l0l <= wire_nl0O00OO_dataout; + nl0O1l1i <= wire_nl0O00ll_dataout; + nl0O1l1l <= wire_nl0O00lO_dataout; + nl0O1l1O <= wire_nl0O00Oi_dataout; + nl0Ol0Ol <= wire_nl0OlilO_dataout; + nl0Ol0OO <= wire_nl0OliOi_dataout; + nl0Oli0i <= wire_nl0Oll1l_dataout; + nl0Oli0l <= wire_nl0Oll1O_dataout; + nl0Oli0O <= wire_nl0Oll0i_dataout; + nl0Oli1i <= wire_nl0OliOl_dataout; + nl0Oli1l <= wire_nl0OliOO_dataout; + nl0Oli1O <= wire_nl0Oll1i_dataout; + nl0Oliii <= wire_nl0Oll0l_dataout; + nl0Oliil <= wire_nl0Oll0O_dataout; + nl0OliiO <= wire_nl0Ollii_dataout; + nl0OlO0O <= wire_nl0Olill_dataout; + nl0OlOll <= wire_nl0OlOOO_dataout; + nl0OlOOi <= wire_nl0OO11i_dataout; + nl0OOl0i <= wire_nl0OOlli_dataout; + nl0OOl0l <= wire_nl0OOlll_dataout; + nl0OOl0O <= wire_nl0OOllO_dataout; + nl0OOl1O <= wire_nl0OOliO_dataout; + nl0OOO0i <= wire_nl0OOlil_dataout; + nl0OOOiO <= wire_nl0OOOOi_dataout; + nl0OOOll <= wire_nl0OOOOl_dataout; + nl10001i <= wire_nl10000i_dataout; + nl1000il <= wire_nl100i0l_dataout; + nl1000ll <= wire_nl100i0O_dataout; + nl1000lO <= wire_nl100iii_dataout; + nl1000Oi <= wire_nl100iil_dataout; + nl1000Ol <= wire_nl100iiO_dataout; + nl1000OO <= wire_nl100ili_dataout; + nl100i0i <= wire_nl100iOl_dataout; + nl100i1i <= wire_nl100ill_dataout; + nl100i1l <= wire_nl100ilO_dataout; + nl100i1O <= wire_nl100iOi_dataout; + nl10100O <= wire_nl1010il_dataout; + nl10101O <= wire_nl1010ii_dataout; + nl1011ll <= wire_nl1011Ol_dataout; + nl101i1l <= wire_nl1010OO_dataout; + nl101iii <= wire_nl101ill_dataout; + nl101iiO <= wire_nl101ilO_dataout; + nl10i00i <= wire_nl10i0li_dataout; + nl10i01i <= wire_nl10i0ii_dataout; + nl10i01l <= wire_nl10i0il_dataout; + nl10i01O <= wire_nl10i0iO_dataout; + nl10i10l <= wire_nl10i1il_dataout; + nl10i1lO <= wire_nl10i00l_dataout; + nl10i1OO <= wire_nl10i00O_dataout; + nl10illO <= wire_nl10ilOO_dataout; + nl10iO0i <= wire_nl10iOlO_dataout; + nl10iOii <= wire_nl10iOOi_dataout; + nl10iOil <= wire_nl10iOOl_dataout; + nl10iOiO <= wire_nl10iOOO_dataout; + nl10iOli <= wire_nl10l11i_dataout; + nl10iOll <= wire_nl10l11l_dataout; + nl10l01O <= dl_comclk_reg; + nl10l1lO <= dl_rx_ecrcchk; + nl10l1OO <= dl_aspm_cr0; + nl10llli <= wire_nl10llOi_dataout; + nl10lO0l <= wire_nl10lOOl_dataout; + nl10lO0O <= wire_nl10lOOO_dataout; + nl10lO1l <= wire_nl10lOOi_dataout; + nl10lOii <= wire_nl10O11i_dataout; + nl10lOil <= wire_nl10O11l_dataout; + nl10lOiO <= wire_nl10O11O_dataout; + nl10lOli <= wire_nl10O10i_dataout; + nl10lOll <= wire_nl10O10l_dataout; + nl10lOlO <= wire_nl10O10O_dataout; + nl10O00O <= nl10O0il; + nl10O01O <= nl10O00l; + nl10O0iO <= nl10O0ll; + nl10O0lO <= nl10O0Ol; + nl10O0OO <= nl10Oi1l; + nl10Oi0O <= nl10Oiil; + nl10Oi1O <= nl10Oi0l; + nl10OiiO <= nl10Oill; + nl11000i <= wire_nl1100il_dataout; + nl1100ii <= wire_nl1100iO_dataout; + nl1101lO <= wire_nl1101OO_dataout; + nl110i0l <= wire_nl110iil_dataout; + nl110ilO <= wire_nl110l1i_dataout; + nl110iOO <= wire_nl110l1l_dataout; + nl110lOi <= wire_nl110O1i_dataout; + nl110O0l <= wire_nl110OiO_dataout; + nl110Oil <= wire_nl110Oli_dataout; + nl11101O <= wire_nl11100O_dataout; + nl1110li <= wire_nl1110Ol_dataout; + nl1110Oi <= wire_nl1110OO_dataout; + nl11110l <= wire_nl1111ii_dataout; + nl11111l <= wire_nl11110O_dataout; + nl111ill <= wire_nl111iOl_dataout; + nl111l0O <= wire_nl111lil_dataout; + nl111l1O <= wire_nl111lii_dataout; + nl111O1O <= wire_nl111lOO_dataout; + nl111Oil <= wire_nl111OlO_dataout; + nl111Oli <= wire_nl111OOi_dataout; + nl11i01i <= wire_nl11i01O_dataout; + nl11i0Ol <= wire_nl11ii1l_dataout; + nl11i10O <= wire_nl11i1iO_dataout; + nl11i1Oi <= wire_nl11i01l_dataout; + nl11ii0O <= wire_nl11iili_dataout; + nl11iiiO <= wire_nl11iill_dataout; + nl11ilii <= wire_nl11illi_dataout; + nl11ilOl <= wire_nl11iO1O_dataout; + nl11iO1l <= wire_nl11iO0i_dataout; + nl11iOOO <= wire_nl11l11O_dataout; + nl11l0ii <= wire_nl11l00i_dataout; + nl11l0lO <= wire_nl11li1i_dataout; + nl11l0Ol <= wire_nl11li1l_dataout; + nl11l1ii <= wire_nl11l1ll_dataout; + nl11l1li <= wire_nl11l1lO_dataout; + nl11liOO <= wire_nl11lilO_dataout; + nl11ll0l <= wire_nl11lliO_dataout; + nl11llii <= wire_nl11llli_dataout; + nl11lOil <= wire_nl11lO0l_dataout; + nl11lOOi <= wire_nl11O11l_dataout; + nl11lOOO <= wire_nl11O11O_dataout; + nl11O00O <= wire_nl11O0li_dataout; + nl11O01i <= wire_nl11O1Oi_dataout; + nl11O0il <= wire_nl11O0ll_dataout; + nl11OiiO <= wire_nl11Oi0O_dataout; + nl11OiOl <= wire_nl11Ol1O_dataout; + nl11Ol1i <= wire_nl11Ol0i_dataout; + nl11OO0O <= wire_nl11OOli_dataout; + nl11OO1i <= wire_nl11OlOl_dataout; + nl11OOil <= wire_nl11OOll_dataout; + nl1i010i <= wire_nl1i00Ol_dataout; + nl1i010l <= wire_nl1i00OO_dataout; + nl1i010O <= wire_nl1i0i1i_dataout; + nl1i011i <= wire_nl1i00ll_dataout; + nl1i011l <= wire_nl1i00lO_dataout; + nl1i011O <= wire_nl1i00Oi_dataout; + nl1i01ii <= wire_nl1i0i1l_dataout; + nl1i01il <= wire_nl1i0i1O_dataout; + nl1i01iO <= wire_nl1i0i0i_dataout; + nl1i01li <= wire_nl1i0i0l_dataout; + nl1i01ll <= wire_nl1i0i0O_dataout; + nl1i01lO <= wire_nl1i0iii_dataout; + nl1i01Oi <= wire_nl1i0iil_dataout; + nl1i01Ol <= wire_nl1i0iiO_dataout; + nl1i01OO <= wire_nl1i0ili_dataout; + nl1i1llO <= wire_nl1i1lOO_dataout; + nl1i1O0i <= wire_nl1i001i_dataout; + nl1i1Oii <= wire_nl1i001l_dataout; + nl1i1Oil <= wire_nl1i001O_dataout; + nl1i1OiO <= wire_nl1i000i_dataout; + nl1i1Oli <= wire_nl1i000l_dataout; + nl1i1Oll <= wire_nl1i000O_dataout; + nl1i1OlO <= wire_nl1i00ii_dataout; + nl1i1OOi <= wire_nl1i00il_dataout; + nl1i1OOl <= wire_nl1i00iO_dataout; + nl1i1OOO <= wire_nl1i00li_dataout; + nl1ii00i <= wire_nl1ii0il_dataout; + nl1ii00l <= wire_nl1ii0iO_dataout; + nl1ii01O <= wire_nl1ii0ii_dataout; + nl1ii1il <= wire_nl1ii1ll_dataout; + nl1ii1OO <= wire_nl1ii00O_dataout; + nl1iii0i <= wire_nl1iii1l_dataout; + nl1iiiiO <= wire_nl1iiiOi_dataout; + nl1iiill <= wire_nl1iiiOl_dataout; + nl1iillO <= wire_nl1iilli_dataout; + nl1iiO0i <= wire_nl1iiOii_dataout; + nl1iiO1l <= wire_nl1iiO0O_dataout; + nl1il00i <= wire_nl1il0ii_dataout; + nl1il01l <= wire_nl1il00O_dataout; + nl1il10l <= wire_nl1il1il_dataout; + nl1il1lO <= wire_nl1il1ii_dataout; + nl1iO00l <= wire_nl1iOi0O_dataout; + nl1iO0il <= wire_nl1iOiii_dataout; + nl1iO0iO <= wire_nl1iOiil_dataout; + nl1iO0li <= wire_nl1iOiiO_dataout; + nl1iO0ll <= wire_nl1iOili_dataout; + nl1iO0lO <= wire_nl1iOill_dataout; + nl1iO0Oi <= wire_nl1iOilO_dataout; + nl1iO0Ol <= wire_nl1iOiOi_dataout; + nl1iO0OO <= wire_nl1iOiOl_dataout; + nl1iO1Oi <= wire_nl1iO01i_dataout; + nl1iOi0i <= wire_nl1iOl1O_dataout; + nl1iOi0l <= wire_nl1iOl0i_dataout; + nl1iOi1i <= wire_nl1iOiOO_dataout; + nl1iOi1l <= wire_nl1iOl1i_dataout; + nl1iOi1O <= wire_nl1iOl1l_dataout; + nl1iOO0O <= nl1iOOil; + nl1iOOiO <= nl1iOOll; + nl1iOOlO <= nl1iOOOl; + nl1l000l <= wire_nl1l001O_dataout; + nl1l00li <= wire_nl1l00Ol_dataout; + nl1l00lO <= wire_nl1l00OO_dataout; + nl1l010i <= wire_nl1l01ii_dataout; + nl1l011l <= wire_nl1l010O_dataout; + nl1l0iOi <= wire_nl1l0ill_dataout; + nl1l0l0l <= wire_nl1l0lil_dataout; + nl1l0l1O <= wire_nl1l0lii_dataout; + nl1l0O1O <= nl1l0O0l; + nl1l0Oii <= dl_req_wake; + nl1l0OOl <= wire_nl1li10i_dataout; + nl1l0OOO <= wire_nl1li10l_dataout; + nl1l10ll <= wire_nl1l10iO_dataout; + nl1l111O <= wire_nl1l111i_dataout; + nl1l11il <= wire_nl1l11lO_dataout; + nl1l11li <= wire_nl1l11Oi_dataout; + nl1l1i1i <= wire_nl1l1i0l_dataout; + nl1l1i1O <= wire_nl1l1i0O_dataout; + nl1l1l0i <= wire_nl1l1l1l_dataout; + nl1l1liO <= wire_nl1l1lOi_dataout; + nl1l1lll <= wire_nl1l1lOl_dataout; + nl1l1OlO <= wire_nl1l1Oli_dataout; + nl1li00i <= wire_nl1li0ii_dataout; + nl1li01l <= wire_nl1li00O_dataout; + nl1li11i <= wire_nl1li10O_dataout; + nl1li1lO <= wire_nl1li11O_dataout; + nl1liiiO <= nl1liill; + nl1lil0i <= wire_nl1lilli_dataout; + nl1lil0l <= wire_nl1lilll_dataout; + nl1lil0O <= wire_nl1lillO_dataout; + nl1lil1O <= wire_nl1liliO_dataout; + nl1liO0i <= wire_nl1lilil_dataout; + nl1liOiO <= wire_nl1liOOi_dataout; + nl1liOll <= wire_nl1liOOl_dataout; + nl1ll00l <= dl_txcfg_extsy; + nl1ll0il <= dl_inh_dllp; + nl1ll0li <= nl1ll0lO; + nl1llO1i <= wire_nl1llO0i_dataout; + nl1llOil <= wire_nl1llO1O_dataout; + nl1llOOi <= wire_nl1lO11l_dataout; + nl1llOOO <= wire_nl1lO11O_dataout; + nl1lO00l <= wire_nl1lO0li_dataout; + nl1lO00O <= wire_nl1lO0ll_dataout; + nl1lO0ii <= wire_nl1lO0lO_dataout; + nl1lOi1O <= wire_nl1lO0iO_dataout; + nl1lOiil <= wire_nl1lOilO_dataout; + nl1lOili <= wire_nl1lOiOi_dataout; + nl1O00ii <= wire_nl1O00ll_dataout; + nl1O00li <= wire_nl1O00lO_dataout; + nl1O01OO <= wire_nl1O001O_dataout; + nl1O0iil <= wire_nl1O0ill_dataout; + nl1O0iOO <= wire_nl1O0l0i_dataout; + nl1O0l1O <= wire_nl1O0l0l_dataout; + nl1O0O1i <= wire_nl1O0O0i_dataout; + nl1O0Oil <= wire_nl1O0OlO_dataout; + nl1O0Oll <= wire_nl1O0OOi_dataout; + nl1O1i0O <= wire_nl1O1iiO_dataout; + nl1O1iOi <= wire_nl1O1l0l_dataout; + nl1O1l0i <= wire_nl1O1liO_dataout; + nl1O1l1i <= wire_nl1O1l0O_dataout; + nl1O1l1l <= wire_nl1O1lii_dataout; + nl1O1l1O <= wire_nl1O1lil_dataout; + nl1O1O0l <= wire_nl1O1O1O_dataout; + nl1O1Oli <= wire_nl1O1OOl_dataout; + nl1O1OlO <= wire_nl1O1OOO_dataout; + nl1Oi00i <= wire_nl1Oi00O_dataout; + nl1Oi01i <= wire_nl1Oi00l_dataout; + nl1Oi0OO <= wire_nl1Oi0Oi_dataout; + nl1Oi1iO <= wire_nl1Oi1lO_dataout; + nl1Oii0l <= wire_nl1OiiiO_dataout; + nl1Oiiii <= wire_nl1Oiili_dataout; + nl1Oilil <= wire_nl1Oil0O_dataout; + nl1OilOi <= wire_nl1OiO1l_dataout; + nl1OilOO <= wire_nl1OiO1O_dataout; + nl1Ol0ll <= wire_nl1Ol0Ol_dataout; + nl1Ol11O <= wire_nl1Ol10O_dataout; + nl1Ol1li <= wire_nl1Ol1Ol_dataout; + nl1Ol1Oi <= wire_nl1Ol1OO_dataout; + nl1Oli0O <= wire_nl1Oliil_dataout; + nl1Oli1O <= wire_nl1Oliii_dataout; + nl1Oll0i <= wire_nl1Ollii_dataout; + nl1Ollll <= wire_nl1OllOO_dataout; + nl1OllOl <= wire_nl1OlO1i_dataout; + nl1OlOlO <= wire_nl1OlOOO_dataout; + nl1OO10i <= wire_nl1OO1il_dataout; + nl1OO1ii <= wire_nl1OO1iO_dataout; + nli0100i <= wire_nli0iiOO_dataout; + nli0100l <= wire_nli0il1i_dataout; + nli0100O <= wire_nli0il1l_dataout; + nli0101i <= wire_nli0iilO_dataout; + nli0101l <= wire_nli0iiOi_dataout; + nli0101O <= wire_nli0iiOl_dataout; + nli010ii <= wire_nli0il1O_dataout; + nli010il <= wire_nli0il0i_dataout; + nli010iO <= wire_nli0il0l_dataout; + nli010li <= wire_nli0il0O_dataout; + nli010ll <= wire_nli0ilii_dataout; + nli010lO <= wire_nli0ilil_dataout; + nli010Oi <= wire_nli0iliO_dataout; + nli010Ol <= wire_nli0illi_dataout; + nli010OO <= wire_nli0illl_dataout; + nli0110i <= wire_nli0i0OO_dataout; + nli0110l <= wire_nli0ii1i_dataout; + nli0110O <= wire_nli0ii1l_dataout; + nli0111i <= wire_nli0i0lO_dataout; + nli0111l <= wire_nli0i0Oi_dataout; + nli0111O <= wire_nli0i0Ol_dataout; + nli011ii <= wire_nli0ii1O_dataout; + nli011il <= wire_nli0ii0i_dataout; + nli011iO <= wire_nli0ii0l_dataout; + nli011li <= wire_nli0ii0O_dataout; + nli011ll <= wire_nli0iiii_dataout; + nli011lO <= wire_nli0iiil_dataout; + nli011Oi <= wire_nli0iiiO_dataout; + nli011Ol <= wire_nli0iili_dataout; + nli011OO <= wire_nli0iill_dataout; + nli01i0i <= wire_nli01OOl_dataout; + nli01i0l <= wire_nli01OOO_dataout; + nli01i0O <= wire_nli0011i_dataout; + nli01i1i <= wire_nli0illO_dataout; + nli01i1l <= wire_nli01OlO_dataout; + nli01i1O <= wire_nli01OOi_dataout; + nli01iii <= wire_nli0011l_dataout; + nli01iil <= wire_nli0011O_dataout; + nli01iiO <= wire_nli0010i_dataout; + nli01ili <= wire_nli0ilOi_dataout; + nli01ill <= wire_nli0ilOl_dataout; + nli01ilO <= wire_nli0ilOO_dataout; + nli01iOi <= wire_nli0iO1i_dataout; + nli01iOl <= wire_nli0iO1l_dataout; + nli1001i <= wire_nli10iOO_dataout; + nli1001l <= wire_nli10l1i_dataout; + nli1001O <= wire_nli10l1l_dataout; + nli1010i <= wire_nli10i1O_dataout; + nli1010l <= wire_nli10i0i_dataout; + nli1010O <= wire_nli10i0l_dataout; + nli1011i <= wire_nli10i1i_dataout; + nli1011l <= wire_nli10iiO_dataout; + nli1011O <= wire_nli10i1l_dataout; + nli101ii <= wire_nli10i0O_dataout; + nli101il <= wire_nli10iii_dataout; + nli101iO <= wire_nli10iil_dataout; + nli101li <= wire_nli10iiO_dataout; + nli101ll <= wire_nli10ili_dataout; + nli101lO <= wire_nli10ill_dataout; + nli101Oi <= wire_nli10ilO_dataout; + nli101Ol <= wire_nli10iOi_dataout; + nli101OO <= wire_nli10iOl_dataout; + nli1100l <= rx_mask_vc0; + nli110il <= nli110li; + nli11l0i <= wire_nli11liO_dataout; + nli11l0l <= wire_nli11lli_dataout; + nli11l1O <= wire_nli11lil_dataout; + nli11O0l <= wire_nli100iO_dataout; + nli11Oli <= wire_nli100li_dataout; + nli11Oll <= wire_nli100ll_dataout; + nli11OlO <= wire_nli100lO_dataout; + nli11OOi <= wire_nli100Oi_dataout; + nli11OOl <= wire_nli100Ol_dataout; + nli11OOO <= wire_nli100OO_dataout; + nli1l00i <= wire_nli01l1i_dataout; + nli1l0ii <= wire_nli1l00l_dataout; + nli1l0Ol <= wire_nli01l1l_dataout; + nli1l0OO <= wire_nli01l1O_dataout; + nli1li0i <= wire_nli01lii_dataout; + nli1li0l <= wire_nli01lil_dataout; + nli1li0O <= wire_nli01liO_dataout; + nli1li1i <= wire_nli01l0i_dataout; + nli1li1l <= wire_nli01l0l_dataout; + nli1li1O <= wire_nli01l0O_dataout; + nli1liii <= wire_nli01lli_dataout; + nli1liil <= wire_nli01lll_dataout; + nli1liiO <= wire_nli01llO_dataout; + nli1lili <= wire_nli01lOi_dataout; + nli1lill <= wire_nli01lOl_dataout; + nli1lilO <= wire_nli01lOO_dataout; + nli1liOi <= wire_nli01O1i_dataout; + nli1liOl <= wire_nli01O1l_dataout; + nli1liOO <= wire_nli01O1O_dataout; + nli1ll0i <= wire_nli01Oii_dataout; + nli1ll0l <= wire_nli01Oil_dataout; + nli1ll0O <= wire_nli01OiO_dataout; + nli1ll1i <= wire_nli01O0i_dataout; + nli1ll1l <= wire_nli01O0l_dataout; + nli1ll1O <= wire_nli01O0O_dataout; + nli1llii <= wire_nli01Oli_dataout; + nli1llil <= wire_nli01Oll_dataout; + nli1lliO <= wire_nli0010l_dataout; + nli1llli <= wire_nli0010O_dataout; + nli1llll <= wire_nli001ii_dataout; + nli1lllO <= wire_nli001il_dataout; + nli1llOi <= wire_nli001iO_dataout; + nli1llOl <= wire_nli001li_dataout; + nli1llOO <= wire_nli001ll_dataout; + nli1lO0i <= wire_nli001OO_dataout; + nli1lO0l <= wire_nli0001i_dataout; + nli1lO0O <= wire_nli0001l_dataout; + nli1lO1i <= wire_nli001lO_dataout; + nli1lO1l <= wire_nli001Oi_dataout; + nli1lO1O <= wire_nli001Ol_dataout; + nli1lOii <= wire_nli0001O_dataout; + nli1lOil <= wire_nli0000i_dataout; + nli1lOiO <= wire_nli0000l_dataout; + nli1lOli <= wire_nli0000O_dataout; + nli1lOll <= wire_nli000ii_dataout; + nli1lOlO <= wire_nli000il_dataout; + nli1lOOi <= wire_nli000iO_dataout; + nli1lOOl <= wire_nli000li_dataout; + nli1lOOO <= wire_nli000ll_dataout; + nli1O00i <= wire_nli00iOO_dataout; + nli1O00l <= wire_nli00l1i_dataout; + nli1O00O <= wire_nli00l1l_dataout; + nli1O01i <= wire_nli00ilO_dataout; + nli1O01l <= wire_nli00iOi_dataout; + nli1O01O <= wire_nli00iOl_dataout; + nli1O0ii <= wire_nli00l1O_dataout; + nli1O0il <= wire_nli00l0i_dataout; + nli1O0iO <= wire_nli00l0l_dataout; + nli1O0li <= wire_nli00l0O_dataout; + nli1O0ll <= wire_nli00lii_dataout; + nli1O0lO <= wire_nli00lil_dataout; + nli1O0Oi <= wire_nli00liO_dataout; + nli1O0Ol <= wire_nli00lli_dataout; + nli1O0OO <= wire_nli00lll_dataout; + nli1O10i <= wire_nli000OO_dataout; + nli1O10l <= wire_nli00i1i_dataout; + nli1O10O <= wire_nli00i1l_dataout; + nli1O11i <= wire_nli000lO_dataout; + nli1O11l <= wire_nli000Oi_dataout; + nli1O11O <= wire_nli000Ol_dataout; + nli1O1ii <= wire_nli00i1O_dataout; + nli1O1il <= wire_nli00i0i_dataout; + nli1O1iO <= wire_nli00i0l_dataout; + nli1O1li <= wire_nli00i0O_dataout; + nli1O1ll <= wire_nli00iii_dataout; + nli1O1lO <= wire_nli00iil_dataout; + nli1O1Oi <= wire_nli00iiO_dataout; + nli1O1Ol <= wire_nli00ili_dataout; + nli1O1OO <= wire_nli00ill_dataout; + nli1Oi0i <= wire_nli00lOO_dataout; + nli1Oi0l <= wire_nli00O1i_dataout; + nli1Oi0O <= wire_nli00O1l_dataout; + nli1Oi1i <= wire_nli00llO_dataout; + nli1Oi1l <= wire_nli00lOi_dataout; + nli1Oi1O <= wire_nli00lOl_dataout; + nli1Oiii <= wire_nli00O1O_dataout; + nli1Oiil <= wire_nli00O0i_dataout; + nli1OiiO <= wire_nli00O0l_dataout; + nli1Oili <= wire_nli00O0O_dataout; + nli1Oill <= wire_nli00Oii_dataout; + nli1OilO <= wire_nli00Oil_dataout; + nli1OiOi <= wire_nli00OiO_dataout; + nli1OiOl <= wire_nli00Oli_dataout; + nli1OiOO <= wire_nli00Oll_dataout; + nli1Ol0i <= wire_nli00OOO_dataout; + nli1Ol0l <= wire_nli0i11i_dataout; + nli1Ol0O <= wire_nli0i11l_dataout; + nli1Ol1i <= wire_nli00OlO_dataout; + nli1Ol1l <= wire_nli00OOi_dataout; + nli1Ol1O <= wire_nli00OOl_dataout; + nli1Olii <= wire_nli0i11O_dataout; + nli1Olil <= wire_nli0i10i_dataout; + nli1OliO <= wire_nli0i10l_dataout; + nli1Olli <= wire_nli0i10O_dataout; + nli1Olll <= wire_nli0i1ii_dataout; + nli1OllO <= wire_nli0i1il_dataout; + nli1OlOi <= wire_nli0i1iO_dataout; + nli1OlOl <= wire_nli0i1li_dataout; + nli1OlOO <= wire_nli0i1ll_dataout; + nli1OO0i <= wire_nli0i1OO_dataout; + nli1OO0l <= wire_nli0i01i_dataout; + nli1OO0O <= wire_nli0i01l_dataout; + nli1OO1i <= wire_nli0i1lO_dataout; + nli1OO1l <= wire_nli0i1Oi_dataout; + nli1OO1O <= wire_nli0i1Ol_dataout; + nli1OOii <= wire_nli0i01O_dataout; + nli1OOil <= wire_nli0i00i_dataout; + nli1OOiO <= wire_nli0i00l_dataout; + nli1OOli <= wire_nli0i00O_dataout; + nli1OOll <= wire_nli0i0ii_dataout; + nli1OOlO <= wire_nli0i0il_dataout; + nli1OOOi <= wire_nli0i0iO_dataout; + nli1OOOl <= wire_nli0i0li_dataout; + nli1OOOO <= wire_nli0i0ll_dataout; + nlll0lll <= nlll0lOi; + nllll0ll <= wire_nllllllO_dataout; + nlllli0i <= wire_nllllO1i_dataout; + nlllli0l <= wire_nllllO1l_dataout; + nlllli0O <= wire_nllllO1O_dataout; + nlllli1i <= wire_nlllllOi_dataout; + nlllli1l <= wire_nlllllOl_dataout; + nlllli1O <= wire_nlllllOO_dataout; + nlllliii <= wire_nllllO0i_dataout; + nlllliil <= wire_nllllO0l_dataout; + nlllliiO <= wire_nllllO0O_dataout; + nllllili <= wire_nllllOii_dataout; + nllllill <= wire_nllllOil_dataout; + nllllilO <= wire_nllllOiO_dataout; + nlllliOi <= wire_nllllOli_dataout; + nlllll0l <= wire_nlllO11i_dataout; + nlllll0O <= wire_nlllO11l_dataout; + nlllll1i <= wire_nllllOOi_dataout; + nlllll1l <= wire_nllllOOl_dataout; + nlllllii <= wire_nlllO11O_dataout; + nlllllil <= wire_nlllO10i_dataout; + nllllliO <= wire_nlllO10l_dataout; + nlllllli <= wire_nlllO10O_dataout; + nlllllll <= wire_nlllO1ii_dataout; + END IF; + END PROCESS; + wire_niOOO0O_CLRN <= ((niOO0ll0O48 XOR niOO0ll0O47) AND wire_niO01lil_dataout); + wire_niOOO0O_PRN <= (niOO0ll0l50 XOR niOO0ll0l49); + wire_niOOO0O_w6168w(0) <= wire_niOOO0O_w_lg_w_lg_w_lg_w_lg_nli101OO6158w6159w6162w6165w(0) AND wire_niOOO0O_w_lg_w_lg_nli1001O6166w6167w(0); + wire_niOOO0O_w_lg_w_lg_w_lg_w_lg_nli101OO6158w6159w6162w6165w(0) <= wire_niOOO0O_w_lg_w_lg_w_lg_nli101OO6158w6159w6162w(0) AND wire_niOOO0O_w_lg_w_lg_nli1001l6163w6164w(0); + wire_niOOO0O_w_lg_w_lg_w_lg_nli101OO6158w6159w6162w(0) <= wire_niOOO0O_w_lg_w_lg_nli101OO6158w6159w(0) AND wire_niOOO0O_w_lg_w_lg_nli1001i6160w6161w(0); + wire_niOOO0O_w_lg_w_lg_ni0O01O2320w2321w(0) <= wire_niOOO0O_w_lg_ni0O01O2320w(0) AND ni0O01i; + wire_niOOO0O_w_lg_nli11l0l6184w(0) <= nli11l0l AND nli11l0i; + wire_niOOO0O_w_lg_w_lg_nli1001i6160w6161w(0) <= NOT wire_niOOO0O_w_lg_nli1001i6160w(0); + wire_niOOO0O_w_lg_w_lg_nli1001l6163w6164w(0) <= NOT wire_niOOO0O_w_lg_nli1001l6163w(0); + wire_niOOO0O_w_lg_w_lg_nli1001O6166w6167w(0) <= NOT wire_niOOO0O_w_lg_nli1001O6166w(0); + wire_niOOO0O_w_lg_w_lg_nli101OO6158w6159w(0) <= NOT wire_niOOO0O_w_lg_nli101OO6158w(0); + wire_niOOO0O_w_lg_ni0O01O2320w(0) <= NOT ni0O01O; + wire_niOOO0O_w_lg_ni0O1li2322w(0) <= NOT ni0O1li; + wire_niOOO0O_w_lg_niOiilll8581w(0) <= NOT niOiilll; + wire_niOOO0O_w_lg_niOlOl0i8541w(0) <= NOT niOlOl0i; + wire_niOOO0O_w_lg_niOlOOll8534w(0) <= NOT niOlOOll; + wire_niOOO0O_w_lg_niOO00iO8496w(0) <= NOT niOO00iO; + wire_niOOO0O_w_lg_niOO0OlOO61845w(0) <= NOT niOO0OlOO; + wire_niOOO0O_w_lg_niOO100i8526w(0) <= NOT niOO100i; + wire_niOOO0O_w_lg_niOO1ilO8518w(0) <= NOT niOO1ilO; + wire_niOOO0O_w_lg_niOO1O0l8510w(0) <= NOT niOO1O0l; + wire_niOOO0O_w_lg_niOOi001i61782w(0) <= NOT niOOi001i; + wire_niOOO0O_w_lg_niOOl01i8434w(0) <= NOT niOOl01i; + wire_niOOO0O_w_lg_niOOlOil8416w(0) <= NOT niOOlOil; + wire_niOOO0O_w_lg_niOOOiiO8402w(0) <= NOT niOOOiiO; + wire_niOOO0O_w_lg_nl011lOi7598w(0) <= NOT nl011lOi; + wire_niOOO0O_w_lg_nl0il1li6950w(0) <= NOT nl0il1li; + wire_niOOO0O_w_lg_nl0ilili6952w(0) <= NOT nl0ilili; + wire_niOOO0O_w_lg_nl0ilill6954w(0) <= NOT nl0ilill; + wire_niOOO0O_w_lg_nl0ililO6956w(0) <= NOT nl0ililO; + wire_niOOO0O_w_lg_nl0iliOi6958w(0) <= NOT nl0iliOi; + wire_niOOO0O_w_lg_nl0iliOl6960w(0) <= NOT nl0iliOl; + wire_niOOO0O_w_lg_nl0iliOO6962w(0) <= NOT nl0iliOO; + wire_niOOO0O_w_lg_nl0ill0i6970w(0) <= NOT nl0ill0i; + wire_niOOO0O_w_lg_nl0ill0l6972w(0) <= NOT nl0ill0l; + wire_niOOO0O_w_lg_nl0ill0O6916w(0) <= NOT nl0ill0O; + wire_niOOO0O_w_lg_nl0ill1i6964w(0) <= NOT nl0ill1i; + wire_niOOO0O_w_lg_nl0ill1l6966w(0) <= NOT nl0ill1l; + wire_niOOO0O_w_lg_nl0ill1O6968w(0) <= NOT nl0ill1O; + wire_niOOO0O_w_lg_nl0illii6918w(0) <= NOT nl0illii; + wire_niOOO0O_w_lg_nl0illil6920w(0) <= NOT nl0illil; + wire_niOOO0O_w_lg_nl0illiO6922w(0) <= NOT nl0illiO; + wire_niOOO0O_w_lg_nl0illli6924w(0) <= NOT nl0illli; + wire_niOOO0O_w_lg_nl0illll6926w(0) <= NOT nl0illll; + wire_niOOO0O_w_lg_nl0illlO6928w(0) <= NOT nl0illlO; + wire_niOOO0O_w_lg_nl0illOi6930w(0) <= NOT nl0illOi; + wire_niOOO0O_w_lg_nl0illOl7062w(0) <= NOT nl0illOl; + wire_niOOO0O_w_lg_nl0iO0lO6992w(0) <= NOT nl0iO0lO; + wire_niOOO0O_w_lg_nl0l0ili6630w(0) <= NOT nl0l0ili; + wire_niOOO0O_w_lg_nl0l0OiO6632w(0) <= NOT nl0l0OiO; + wire_niOOO0O_w_lg_nl0l0Oli6634w(0) <= NOT nl0l0Oli; + wire_niOOO0O_w_lg_nl0l0Oll6636w(0) <= NOT nl0l0Oll; + wire_niOOO0O_w_lg_nl0l0OlO6638w(0) <= NOT nl0l0OlO; + wire_niOOO0O_w_lg_nl0l0OOi6640w(0) <= NOT nl0l0OOi; + wire_niOOO0O_w_lg_nl0l0OOl6642w(0) <= NOT nl0l0OOl; + wire_niOOO0O_w_lg_nl0l0OOO6644w(0) <= NOT nl0l0OOO; + wire_niOOO0O_w_lg_nl0li10i6652w(0) <= NOT nl0li10i; + wire_niOOO0O_w_lg_nl0li10l6596w(0) <= NOT nl0li10l; + wire_niOOO0O_w_lg_nl0li10O6598w(0) <= NOT nl0li10O; + wire_niOOO0O_w_lg_nl0li11i6646w(0) <= NOT nl0li11i; + wire_niOOO0O_w_lg_nl0li11l6648w(0) <= NOT nl0li11l; + wire_niOOO0O_w_lg_nl0li11O6650w(0) <= NOT nl0li11O; + wire_niOOO0O_w_lg_nl0li1ii6600w(0) <= NOT nl0li1ii; + wire_niOOO0O_w_lg_nl0li1il6602w(0) <= NOT nl0li1il; + wire_niOOO0O_w_lg_nl0li1iO6604w(0) <= NOT nl0li1iO; + wire_niOOO0O_w_lg_nl0li1li6606w(0) <= NOT nl0li1li; + wire_niOOO0O_w_lg_nl0li1ll6608w(0) <= NOT nl0li1ll; + wire_niOOO0O_w_lg_nl0li1lO6610w(0) <= NOT nl0li1lO; + wire_niOOO0O_w_lg_nl0li1Oi6742w(0) <= NOT nl0li1Oi; + wire_niOOO0O_w_lg_nl0lilll6672w(0) <= NOT nl0lilll; + wire_niOOO0O_w_lg_nl0ll11l7200w(0) <= NOT nl0ll11l; + wire_niOOO0O_w_lg_nl0lOOOi7198w(0) <= NOT nl0lOOOi; + wire_niOOO0O_w_lg_nl0lOOOl7196w(0) <= NOT nl0lOOOl; + wire_niOOO0O_w_lg_nl0lOOOO7194w(0) <= NOT nl0lOOOO; + wire_niOOO0O_w_lg_nl0O100i7211w(0) <= NOT nl0O100i; + wire_niOOO0O_w_lg_nl0O100O7209w(0) <= NOT nl0O100O; + wire_niOOO0O_w_lg_nl0O101i7141w(0) <= NOT nl0O101i; + wire_niOOO0O_w_lg_nl0O101l7214w(0) <= NOT nl0O101l; + wire_niOOO0O_w_lg_nl0O101O7212w(0) <= NOT nl0O101O; + wire_niOOO0O_w_lg_nl0O10iO7177w(0) <= NOT nl0O10iO; + wire_niOOO0O_w_lg_nl0O10li7175w(0) <= NOT nl0O10li; + wire_niOOO0O_w_lg_nl0O10ll7173w(0) <= NOT nl0O10ll; + wire_niOOO0O_w_lg_nl0O10lO7171w(0) <= NOT nl0O10lO; + wire_niOOO0O_w_lg_nl0O10Oi7169w(0) <= NOT nl0O10Oi; + wire_niOOO0O_w_lg_nl0O10Ol7167w(0) <= NOT nl0O10Ol; + wire_niOOO0O_w_lg_nl0O10OO7165w(0) <= NOT nl0O10OO; + wire_niOOO0O_w_lg_nl0O110i7186w(0) <= NOT nl0O110i; + wire_niOOO0O_w_lg_nl0O110l7184w(0) <= NOT nl0O110l; + wire_niOOO0O_w_lg_nl0O110O7182w(0) <= NOT nl0O110O; + wire_niOOO0O_w_lg_nl0O111i7192w(0) <= NOT nl0O111i; + wire_niOOO0O_w_lg_nl0O111l7190w(0) <= NOT nl0O111l; + wire_niOOO0O_w_lg_nl0O111O7188w(0) <= NOT nl0O111O; + wire_niOOO0O_w_lg_nl0O11ii7180w(0) <= NOT nl0O11ii; + wire_niOOO0O_w_lg_nl0O11il7179w(0) <= NOT nl0O11il; + wire_niOOO0O_w_lg_nl0O11iO7154w(0) <= NOT nl0O11iO; + wire_niOOO0O_w_lg_nl0O11li7152w(0) <= NOT nl0O11li; + wire_niOOO0O_w_lg_nl0O11ll7150w(0) <= NOT nl0O11ll; + wire_niOOO0O_w_lg_nl0O11lO7148w(0) <= NOT nl0O11lO; + wire_niOOO0O_w_lg_nl0O11Oi7146w(0) <= NOT nl0O11Oi; + wire_niOOO0O_w_lg_nl0O11Ol7144w(0) <= NOT nl0O11Ol; + wire_niOOO0O_w_lg_nl0O11OO7142w(0) <= NOT nl0O11OO; + wire_niOOO0O_w_lg_nl0O1i0i7157w(0) <= NOT nl0O1i0i; + wire_niOOO0O_w_lg_nl0O1i0l7156w(0) <= NOT nl0O1i0l; + wire_niOOO0O_w_lg_nl0O1i0O7139w(0) <= NOT nl0O1i0O; + wire_niOOO0O_w_lg_nl0O1i1i7163w(0) <= NOT nl0O1i1i; + wire_niOOO0O_w_lg_nl0O1i1l7161w(0) <= NOT nl0O1i1l; + wire_niOOO0O_w_lg_nl0O1i1O7159w(0) <= NOT nl0O1i1O; + wire_niOOO0O_w_lg_nl0O1iii7137w(0) <= NOT nl0O1iii; + wire_niOOO0O_w_lg_nl0O1iil7135w(0) <= NOT nl0O1iil; + wire_niOOO0O_w_lg_nl0O1iiO7133w(0) <= NOT nl0O1iiO; + wire_niOOO0O_w_lg_nl0O1ili7131w(0) <= NOT nl0O1ili; + wire_niOOO0O_w_lg_nl0O1ill7129w(0) <= NOT nl0O1ill; + wire_niOOO0O_w_lg_nl0O1ilO7127w(0) <= NOT nl0O1ilO; + wire_niOOO0O_w_lg_nl0O1iOi7126w(0) <= NOT nl0O1iOi; + wire_niOOO0O_w_lg_nl0O1iOl7207w(0) <= NOT nl0O1iOl; + wire_niOOO0O_w_lg_nl0O1iOO7205w(0) <= NOT nl0O1iOO; + wire_niOOO0O_w_lg_nl0O1l1i7204w(0) <= NOT nl0O1l1i; + wire_niOOO0O_w_lg_nl0O1l1O7202w(0) <= NOT nl0O1l1O; + wire_niOOO0O_w_lg_nl1000il8223w(0) <= NOT nl1000il; + wire_niOOO0O_w_lg_nl10101O8261w(0) <= NOT nl10101O; + wire_niOOO0O_w_lg_nl10i1lO8203w(0) <= NOT nl10i1lO; + wire_niOOO0O_w_lg_nl10iO0i8178w(0) <= NOT nl10iO0i; + wire_niOOO0O_w_lg_nl10lO1l8144w(0) <= NOT nl10lO1l; + wire_niOOO0O_w_lg_nl11000i8359w(0) <= NOT nl11000i; + wire_niOOO0O_w_lg_nl110ilO8351w(0) <= NOT nl110ilO; + wire_niOOO0O_w_lg_nl110O0l8343w(0) <= NOT nl110O0l; + wire_niOOO0O_w_lg_nl1110li8382w(0) <= NOT nl1110li; + wire_niOOO0O_w_lg_nl11111l8390w(0) <= NOT nl11111l; + wire_niOOO0O_w_lg_nl111l1O8374w(0) <= NOT nl111l1O; + wire_niOOO0O_w_lg_nl111O1O8370w(0) <= NOT nl111O1O; + wire_niOOO0O_w_lg_nl11i1Oi8335w(0) <= NOT nl11i1Oi; + wire_niOOO0O_w_lg_nl11ii0O8327w(0) <= NOT nl11ii0O; + wire_niOOO0O_w_lg_nl11ilOl8319w(0) <= NOT nl11ilOl; + wire_niOOO0O_w_lg_nl11l0ii8307w(0) <= NOT nl11l0ii; + wire_niOOO0O_w_lg_nl11l1ii8311w(0) <= NOT nl11l1ii; + wire_niOOO0O_w_lg_nl11liOO8300w(0) <= NOT nl11liOO; + wire_niOOO0O_w_lg_nl11lOil8293w(0) <= NOT nl11lOil; + wire_niOOO0O_w_lg_nl11O01i8286w(0) <= NOT nl11O01i; + wire_niOOO0O_w_lg_nl11OiiO8279w(0) <= NOT nl11OiiO; + wire_niOOO0O_w_lg_nl1i1O0i8059w(0) <= NOT nl1i1O0i; + wire_niOOO0O_w_lg_nl1ii1OO8021w(0) <= NOT nl1ii1OO; + wire_niOOO0O_w_lg_nl1iO00l7949w(0) <= NOT nl1iO00l; + wire_niOOO0O_w_lg_nl1O00ii7754w(0) <= NOT nl1O00ii; + wire_niOOO0O_w_lg_nl1O0iOO7746w(0) <= NOT nl1O0iOO; + wire_niOOO0O_w_lg_nl1O0Oil7738w(0) <= NOT nl1O0Oil; + wire_niOOO0O_w_lg_nl1O1iOi7772w(0) <= NOT nl1O1iOi; + wire_niOOO0O_w_lg_nl1Oi01i7730w(0) <= NOT nl1Oi01i; + wire_niOOO0O_w_lg_nl1Ol1li7708w(0) <= NOT nl1Ol1li; + wire_niOOO0O_w_lg_nl1Oli1O7700w(0) <= NOT nl1Oli1O; + wire_niOOO0O_w_lg_nl1Ollll7692w(0) <= NOT nl1Ollll; + wire_niOOO0O_w_lg_nl1OO10i7684w(0) <= NOT nl1OO10i; + wire_niOOO0O_w_lg_nli1001O6123w(0) <= NOT nli1001O; + wire_niOOO0O_w_lg_nli11O0l6157w(0) <= NOT nli11O0l; + wire_niOOO0O_w_lg_nlllliiO546w(0) <= NOT nlllliiO; + wire_niOOO0O_w_lg_nlllliOi4573w(0) <= NOT nlllliOi; + wire_niOOO0O_w_lg_nli1001i6160w(0) <= nli1001i XOR nli1010i; + wire_niOOO0O_w_lg_nli1001l6163w(0) <= nli1001l XOR nli1010l; + wire_niOOO0O_w_lg_nli1001O6166w(0) <= nli1001O XOR nli1010O; + wire_niOOO0O_w_lg_nli101OO6158w(0) <= nli101OO XOR nli1011O; + PROCESS (core_clk, wire_nl1000i_CLRN) + BEGIN + IF (wire_nl1000i_CLRN = '0') THEN + n1illl1i <= '0'; + n1illOil <= '0'; + n1l000i <= '0'; + n1l000l <= '0'; + n1l000O <= '0'; + n1l001i <= '0'; + n1l001l <= '0'; + n1l001O <= '0'; + n1l00ii <= '0'; + n1l010i <= '0'; + n1l010l <= '0'; + n1l010O <= '0'; + n1l011i <= '0'; + n1l011l <= '0'; + n1l01ii <= '0'; + n1l01il <= '0'; + n1l01iO <= '0'; + n1l01li <= '0'; + n1l01ll <= '0'; + n1l01lO <= '0'; + n1l01Oi <= '0'; + n1l01Ol <= '0'; + n1l01OO <= '0'; + ni0000i <= '0'; + ni0000l <= '0'; + ni0000O <= '0'; + ni0001i <= '0'; + ni0001l <= '0'; + ni0001O <= '0'; + ni000ii <= '0'; + ni000il <= '0'; + ni000iO <= '0'; + ni000li <= '0'; + ni000ll <= '0'; + ni000lO <= '0'; + ni000Oi <= '0'; + ni000Ol <= '0'; + ni000OO <= '0'; + ni001Ol <= '0'; + ni001OO <= '0'; + ni00i0i <= '0'; + ni00i0l <= '0'; + ni00i0O <= '0'; + ni00i1i <= '0'; + ni00i1l <= '0'; + ni00i1O <= '0'; + ni00iii <= '0'; + ni00iil <= '0'; + ni00iiO <= '0'; + ni00ili <= '0'; + ni00ill <= '0'; + ni00ilO <= '0'; + ni0i0OO <= '0'; + ni0l00i <= '0'; + ni0l00l <= '0'; + ni0l00O <= '0'; + ni0l0ii <= '0'; + ni0l0il <= '0'; + ni0liOi <= '0'; + ni0llil <= '0'; + ni0lliO <= '0'; + ni0llli <= '0'; + ni0llll <= '0'; + ni0lllO <= '0'; + ni0llOi <= '0'; + ni0llOl <= '0'; + ni0llOO <= '0'; + ni0lO1i <= '0'; + ni0lO1l <= '0'; + ni0O1iO <= '0'; + ni0Ol0O <= '0'; + nii000i <= '0'; + nii000l <= '0'; + nii000O <= '0'; + nii001i <= '0'; + nii001l <= '0'; + nii001O <= '0'; + nii00ii <= '0'; + nii00il <= '0'; + nii00iO <= '0'; + nii00li <= '0'; + nii00ll <= '0'; + nii00lO <= '0'; + nii00Oi <= '0'; + nii00Ol <= '0'; + nii00OO <= '0'; + nii010i <= '0'; + nii010l <= '0'; + nii010O <= '0'; + nii011i <= '0'; + nii011l <= '0'; + nii011O <= '0'; + nii01ii <= '0'; + nii01il <= '0'; + nii01iO <= '0'; + nii01li <= '0'; + nii01ll <= '0'; + nii01lO <= '0'; + nii01Oi <= '0'; + nii01Ol <= '0'; + nii01OO <= '0'; + nii0i0i <= '0'; + nii0i0l <= '0'; + nii0i0O <= '0'; + nii0i1i <= '0'; + nii0i1l <= '0'; + nii0i1O <= '0'; + nii0iii <= '0'; + nii0iil <= '0'; + nii0iiO <= '0'; + nii0ili <= '0'; + nii0ill <= '0'; + nii0ilO <= '0'; + nii0iOi <= '0'; + nii0iOl <= '0'; + nii0iOO <= '0'; + nii0l0i <= '0'; + nii0l0l <= '0'; + nii0l0O <= '0'; + nii0l1i <= '0'; + nii0l1l <= '0'; + nii0l1O <= '0'; + nii0lii <= '0'; + nii0lil <= '0'; + nii0liO <= '0'; + nii0lli <= '0'; + nii0lll <= '0'; + nii0llO <= '0'; + nii0lOi <= '0'; + nii0lOl <= '0'; + nii0lOO <= '0'; + nii0O0i <= '0'; + nii0O0l <= '0'; + nii0O0O <= '0'; + nii0O1i <= '0'; + nii0O1l <= '0'; + nii0O1O <= '0'; + nii0Oii <= '0'; + nii0Oil <= '0'; + nii0OiO <= '0'; + nii0Oli <= '0'; + nii0Oll <= '0'; + nii0OlO <= '0'; + nii0OOi <= '0'; + nii0OOl <= '0'; + nii0OOO <= '0'; + nii1l0l <= '0'; + nii1l0O <= '0'; + nii1lii <= '0'; + nii1lil <= '0'; + nii1liO <= '0'; + nii1lli <= '0'; + nii1lll <= '0'; + nii1llO <= '0'; + nii1lOi <= '0'; + nii1lOl <= '0'; + nii1lOO <= '0'; + nii1O0i <= '0'; + nii1O0l <= '0'; + nii1O0O <= '0'; + nii1O1i <= '0'; + nii1O1l <= '0'; + nii1O1O <= '0'; + nii1Oii <= '0'; + nii1Oil <= '0'; + nii1OiO <= '0'; + nii1Oli <= '0'; + nii1Oll <= '0'; + nii1OlO <= '0'; + nii1OOi <= '0'; + nii1OOl <= '0'; + nii1OOO <= '0'; + niii00i <= '0'; + niii00l <= '0'; + niii00O <= '0'; + niii01i <= '0'; + niii01l <= '0'; + niii01O <= '0'; + niii0ii <= '0'; + niii0il <= '0'; + niii0iO <= '0'; + niii0li <= '0'; + niii0ll <= '0'; + niii0lO <= '0'; + niii0Oi <= '0'; + niii0Ol <= '0'; + niii0OO <= '0'; + niii10i <= '0'; + niii10l <= '0'; + niii10O <= '0'; + niii11i <= '0'; + niii11l <= '0'; + niii11O <= '0'; + niii1ii <= '0'; + niii1il <= '0'; + niii1iO <= '0'; + niii1li <= '0'; + niii1ll <= '0'; + niii1lO <= '0'; + niii1Oi <= '0'; + niii1Ol <= '0'; + niii1OO <= '0'; + niiii0i <= '0'; + niiii0l <= '0'; + niiii0O <= '0'; + niiii1i <= '0'; + niiii1l <= '0'; + niiii1O <= '0'; + niiiiii <= '0'; + niiiiil <= '0'; + niiiiiO <= '0'; + niiiili <= '0'; + niiiill <= '0'; + niiiilO <= '0'; + niiiiOi <= '0'; + niiiiOl <= '0'; + niiiiOO <= '0'; + niiil0i <= '0'; + niiil0l <= '0'; + niiil0O <= '0'; + niiil1i <= '0'; + niiil1l <= '0'; + niiil1O <= '0'; + niiilii <= '0'; + niiilil <= '0'; + niiiliO <= '0'; + niiilli <= '0'; + niiilll <= '0'; + niiillO <= '0'; + niiilOi <= '0'; + niiilOl <= '0'; + niiilOO <= '0'; + niiiO0i <= '0'; + niiiO0l <= '0'; + niiiO0O <= '0'; + niiiO1i <= '0'; + niiiO1l <= '0'; + niiiO1O <= '0'; + niiiOii <= '0'; + niiiOil <= '0'; + niiiOiO <= '0'; + niiiOli <= '0'; + niiiOll <= '0'; + niiiOlO <= '0'; + niiiOOi <= '0'; + niiiOOl <= '0'; + niiiOOO <= '0'; + niO0000i <= '0'; + niO0000l <= '0'; + niO0000O <= '0'; + niO0001i <= '0'; + niO0001l <= '0'; + niO0001O <= '0'; + niO000ii <= '0'; + niO000il <= '0'; + niO000iO <= '0'; + niO000li <= '0'; + niO000ll <= '0'; + niO000lO <= '0'; + niO000Oi <= '0'; + niO000Ol <= '0'; + niO000OO <= '0'; + niO001Oi <= '0'; + niO001Ol <= '0'; + niO001OO <= '0'; + niO00i0i <= '0'; + niO00i0l <= '0'; + niO00i0O <= '0'; + niO00i1i <= '0'; + niO00i1l <= '0'; + niO00i1O <= '0'; + niO00iii <= '0'; + niO00iil <= '0'; + niO00iiO <= '0'; + niO00ili <= '0'; + niO00ill <= '0'; + niO00ilO <= '0'; + niO00iOi <= '0'; + niO00iOl <= '0'; + niO00iOO <= '0'; + niO00l0i <= '0'; + niO00l0l <= '0'; + niO00l0O <= '0'; + niO00l1i <= '0'; + niO00l1l <= '0'; + niO00l1O <= '0'; + niO00lii <= '0'; + niO00lil <= '0'; + niO00liO <= '0'; + niO00lli <= '0'; + niO00lll <= '0'; + niO00llO <= '0'; + niO00lOi <= '0'; + niO00lOl <= '0'; + niO00lOO <= '0'; + niO00O0i <= '0'; + niO00O0l <= '0'; + niO00O0O <= '0'; + niO00O1i <= '0'; + niO00O1l <= '0'; + niO00O1O <= '0'; + niO0l0li <= '0'; + niO0l0ll <= '0'; + niO0l0lO <= '0'; + niO0l0Oi <= '0'; + niO0liil <= '0'; + niO0liiO <= '0'; + niO0lili <= '0'; + niO0lill <= '0'; + niO0lilO <= '0'; + niO0liOi <= '0'; + niO0liOl <= '0'; + niO0liOO <= '0'; + niO0ll0i <= '0'; + niO0ll0l <= '0'; + niO0ll0O <= '0'; + niO0ll1i <= '0'; + niO0ll1l <= '0'; + niO0ll1O <= '0'; + niO0llii <= '0'; + niO0llil <= '0'; + niO0lliO <= '0'; + niO0llli <= '0'; + niO0llll <= '0'; + niO0lllO <= '0'; + niO0llOi <= '0'; + niO0llOl <= '0'; + niO0llOO <= '0'; + niO0lO0i <= '0'; + niO0lO0l <= '0'; + niO0lO0O <= '0'; + niO0lO1i <= '0'; + niO0lO1l <= '0'; + niO0lO1O <= '0'; + niO0lOii <= '0'; + niO0lOil <= '0'; + niO0lOiO <= '0'; + niO0lOli <= '0'; + niO0lOll <= '0'; + niO0lOlO <= '0'; + niO0lOOi <= '0'; + niO0lOOl <= '0'; + niO0OOOl <= '0'; + niO0OOOO <= '0'; + niOi000i <= '0'; + niOi000l <= '0'; + niOi000O <= '0'; + niOi001i <= '0'; + niOi001l <= '0'; + niOi001O <= '0'; + niOi00i <= '0'; + niOi00ii <= '0'; + niOi00il <= '0'; + niOi00iO <= '0'; + niOi00l <= '0'; + niOi00li <= '0'; + niOi00ll <= '0'; + niOi00lO <= '0'; + niOi00O <= '0'; + niOi00Oi <= '0'; + niOi010i <= '0'; + niOi010l <= '0'; + niOi010O <= '0'; + niOi011i <= '0'; + niOi011l <= '0'; + niOi011O <= '0'; + niOi01ii <= '0'; + niOi01il <= '0'; + niOi01iO <= '0'; + niOi01l <= '0'; + niOi01li <= '0'; + niOi01ll <= '0'; + niOi01lO <= '0'; + niOi01O <= '0'; + niOi01Oi <= '0'; + niOi01Ol <= '0'; + niOi01OO <= '0'; + niOi0ii <= '0'; + niOi0il <= '0'; + niOi0iO <= '0'; + niOi0li <= '0'; + niOi0ll <= '0'; + niOi0lO <= '0'; + niOi0Oi <= '0'; + niOi0Ol <= '0'; + niOi0OO <= '0'; + niOi111i <= '0'; + niOi111l <= '0'; + niOi1lOl <= '0'; + niOi1lOO <= '0'; + niOi1O0i <= '0'; + niOi1O0l <= '0'; + niOi1O0O <= '0'; + niOi1O1i <= '0'; + niOi1O1l <= '0'; + niOi1O1O <= '0'; + niOi1Oii <= '0'; + niOi1Oil <= '0'; + niOi1OiO <= '0'; + niOi1Oli <= '0'; + niOi1Oll <= '0'; + niOi1OlO <= '0'; + niOi1OOi <= '0'; + niOi1OOl <= '0'; + niOi1OOO <= '0'; + niOii0i <= '0'; + niOii0l <= '0'; + niOii0O <= '0'; + niOii1i <= '0'; + niOii1l <= '0'; + niOii1O <= '0'; + niOiiii <= '0'; + niOiiil <= '0'; + niOiiiO <= '0'; + niOiil1O <= '0'; + niOiili <= '0'; + niOiilil <= '0'; + niOiill <= '0'; + niOiilli <= '0'; + niOiilO <= '0'; + niOiiOi <= '0'; + niOiiOl <= '0'; + niOiiOO <= '0'; + niOil0i <= '0'; + niOil0l <= '0'; + niOil0O <= '0'; + niOil1i <= '0'; + niOil1l <= '0'; + niOil1O <= '0'; + niOilii <= '0'; + niOilil <= '0'; + niOiliO <= '0'; + niOilli <= '0'; + niOilll <= '0'; + niOillO <= '0'; + niOilOi <= '0'; + niOilOl <= '0'; + niOilOO <= '0'; + niOiO0i <= '0'; + niOiO0l <= '0'; + niOiO0O <= '0'; + niOiO1i <= '0'; + niOiO1l <= '0'; + niOiO1O <= '0'; + niOlii0l <= '0'; + niOlii0O <= '0'; + niOliiii <= '0'; + niOliiil <= '0'; + niOliiiO <= '0'; + niOliili <= '0'; + niOliill <= '0'; + niOliilO <= '0'; + niOliiOi <= '0'; + niOliiOl <= '0'; + niOliiOO <= '0'; + niOlil0i <= '0'; + niOlil0l <= '0'; + niOlil0O <= '0'; + niOlil1i <= '0'; + niOlil1l <= '0'; + niOlil1O <= '0'; + niOlilii <= '0'; + niOlilil <= '0'; + niOliliO <= '0'; + niOlilli <= '0'; + niOlilll <= '0'; + niOlillO <= '0'; + niOlilOi <= '0'; + niOlilOl <= '0'; + niOlilOO <= '0'; + niOliO0i <= '0'; + niOliO0l <= '0'; + niOliO0O <= '0'; + niOliO1i <= '0'; + niOliO1l <= '0'; + niOliO1O <= '0'; + niOliOii <= '0'; + niOliOil <= '0'; + niOliOiO <= '0'; + niOliOli <= '0'; + niOlOi0O <= '0'; + niOlOill <= '0'; + niOlOl1i <= '0'; + niOlOl1O <= '0'; + niOlOO1O <= '0'; + niOlOOil <= '0'; + niOlOOli <= '0'; + niOO000O <= '0'; + niOO001i <= '0'; + niOO00il <= '0'; + niOO010O <= '0'; + niOO01ii <= '0'; + niOO0ili <= '0'; + niOO0l1l <= '0'; + niOO0liO <= '0'; + niOO0llO <= '0'; + niOO0Oli <= '0'; + niOO101i <= '0'; + niOO101O <= '0'; + niOO11ll <= '0'; + niOO1i0i <= '0'; + niOO1iiO <= '0'; + niOO1ill <= '0'; + niOO1llO <= '0'; + niOO1O0i <= '0'; + niOO1O1l <= '0'; + niOOi01il <= '0'; + niOOi01O <= '0'; + niOOi01Oi <= '0'; + niOOi01OO <= '0'; + niOOi0li <= '0'; + niOOi0Oi <= '0'; + niOOi10l <= '0'; + niOOi11l <= '0'; + niOOi1i0i <= '0'; + niOOi1i0l <= '0'; + niOOi1i0O <= '0'; + niOOi1i1i <= '0'; + niOOi1i1l <= '0'; + niOOi1i1O <= '0'; + niOOi1iii <= '0'; + niOOi1iil <= '0'; + niOOi1iiO <= '0'; + niOOi1ili <= '0'; + niOOi1ill <= '0'; + niOOi1ilO <= '0'; + niOOi1iOi <= '0'; + niOOi1iOl <= '0'; + niOOi1iOO <= '0'; + niOOi1l1i <= '0'; + niOOil0i <= '0'; + niOOil0l <= '0'; + niOOil0O <= '0'; + niOOilii <= '0'; + niOOilil <= '0'; + niOOiliO <= '0'; + niOOilli <= '0'; + niOOilll <= '0'; + niOOillO <= '0'; + niOOilOi <= '0'; + niOOl1il <= '0'; + niOOl1Oi <= '0'; + niOOl1OO <= '0'; + niOOllOO <= '0'; + niOOlO0l <= '0'; + niOOlOii <= '0'; + niOOO01O <= '0'; + niOOO1il <= '0'; + niOOO1OO <= '0'; + niOOOi0O <= '0'; + niOOOi1i <= '0'; + niOOOiil <= '0'; + niOOOil <= '0'; + niOOOl0l <= '0'; + niOOOlil <= '0'; + niOOOlll <= '0'; + niOOOlOl <= '0'; + niOOOO1l <= '0'; + niOOOOiO <= '0'; + niOOOOOl <= '0'; + nl0000iO <= '0'; + nl0000li <= '0'; + nl0000ll <= '0'; + nl0000lO <= '0'; + nl0000Oi <= '0'; + nl0000Ol <= '0'; + nl0000OO <= '0'; + nl000i0i <= '0'; + nl000i0l <= '0'; + nl000i0O <= '0'; + nl000i1i <= '0'; + nl000i1l <= '0'; + nl000i1O <= '0'; + nl000iii <= '0'; + nl000iil <= '0'; + nl000iiO <= '0'; + nl000ili <= '0'; + nl000ill <= '0'; + nl000ilO <= '0'; + nl000iOi <= '0'; + nl000iOl <= '0'; + nl000iOO <= '0'; + nl000l0i <= '0'; + nl000l0l <= '0'; + nl000l0O <= '0'; + nl000l1i <= '0'; + nl000l1l <= '0'; + nl000l1O <= '0'; + nl000lii <= '0'; + nl000lil <= '0'; + nl000liO <= '0'; + nl000lli <= '0'; + nl000lll <= '0'; + nl000llO <= '0'; + nl000lOi <= '0'; + nl000lOl <= '0'; + nl000lOO <= '0'; + nl00100i <= '0'; + nl00101i <= '0'; + nl00101l <= '0'; + nl00101O <= '0'; + nl00110i <= '0'; + nl00110l <= '0'; + nl00110O <= '0'; + nl00111i <= '0'; + nl00111l <= '0'; + nl00111O <= '0'; + nl0011ii <= '0'; + nl0011il <= '0'; + nl0011iO <= '0'; + nl0011li <= '0'; + nl0011ll <= '0'; + nl0011lO <= '0'; + nl0011Oi <= '0'; + nl0011Ol <= '0'; + nl0011OO <= '0'; + nl00ilOO <= '0'; + nl00iO1i <= '0'; + nl00iO1l <= '0'; + nl00Ol0i <= '0'; + nl00Olll <= '0'; + nl00OlOl <= '0'; + nl00OlOO <= '0'; + nl00OO0i <= '0'; + nl00OO0l <= '0'; + nl00OO0O <= '0'; + nl00OO1i <= '0'; + nl00OO1l <= '0'; + nl00OO1O <= '0'; + nl00OOii <= '0'; + nl00OOil <= '0'; + nl00OOiO <= '0'; + nl00OOli <= '0'; + nl00OOll <= '0'; + nl00OOlO <= '0'; + nl00OOOi <= '0'; + nl00OOOl <= '0'; + nl00OOOO <= '0'; + nl010OOO <= '0'; + nl011l0l <= '0'; + nl011lli <= '0'; + nl011llO <= '0'; + nl01i0il <= '0'; + nl01i0OO <= '0'; + nl01i1ii <= '0'; + nl01i1li <= '0'; + nl01ii1O <= '0'; + nl01il1O <= '0'; + nl01illO <= '0'; + nl01ilOi <= '0'; + nl01Ol1O <= '0'; + nl01Olli <= '0'; + nl01OlOi <= '0'; + nl01OlOl <= '0'; + nl01OlOO <= '0'; + nl01OO0i <= '0'; + nl01OO0l <= '0'; + nl01OO0O <= '0'; + nl01OO1i <= '0'; + nl01OO1l <= '0'; + nl01OO1O <= '0'; + nl01OOii <= '0'; + nl01OOil <= '0'; + nl01OOiO <= '0'; + nl01OOli <= '0'; + nl01OOll <= '0'; + nl01OOlO <= '0'; + nl01OOOi <= '0'; + nl01OOOl <= '0'; + nl01OOOO <= '0'; + nl0i00li <= '0'; + nl0i00ll <= '0'; + nl0i00lO <= '0'; + nl0i00Oi <= '0'; + nl0i00Ol <= '0'; + nl0i00OO <= '0'; + nl0i0i0i <= '0'; + nl0i0i0l <= '0'; + nl0i0i0O <= '0'; + nl0i0i1i <= '0'; + nl0i0i1l <= '0'; + nl0i0i1O <= '0'; + nl0i0iii <= '0'; + nl0i0iil <= '0'; + nl0i0iiO <= '0'; + nl0i0ili <= '0'; + nl0i0ill <= '0'; + nl0i0ilO <= '0'; + nl0i0iOi <= '0'; + nl0i0iOl <= '0'; + nl0i0iOO <= '0'; + nl0i0l0i <= '0'; + nl0i0l0l <= '0'; + nl0i0l0O <= '0'; + nl0i0l1i <= '0'; + nl0i0l1l <= '0'; + nl0i0l1O <= '0'; + nl0i0lii <= '0'; + nl0i0lil <= '0'; + nl0i0liO <= '0'; + nl0i0lli <= '0'; + nl0i0lll <= '0'; + nl0i0llO <= '0'; + nl0i0lOi <= '0'; + nl0i0lOl <= '0'; + nl0i0lOO <= '0'; + nl0i0O1i <= '0'; + nl0i100i <= '0'; + nl0i100l <= '0'; + nl0i101i <= '0'; + nl0i101l <= '0'; + nl0i101O <= '0'; + nl0i110i <= '0'; + nl0i110l <= '0'; + nl0i110O <= '0'; + nl0i111i <= '0'; + nl0i111l <= '0'; + nl0i111O <= '0'; + nl0i11ii <= '0'; + nl0i11il <= '0'; + nl0i11iO <= '0'; + nl0i11li <= '0'; + nl0i11ll <= '0'; + nl0i11lO <= '0'; + nl0i11Oi <= '0'; + nl0i11Ol <= '0'; + nl0i11OO <= '0'; + nl0iiO1i <= '0'; + nl0iiO1l <= '0'; + nl0iiO1O <= '0'; + nl0O1l0O <= '0'; + nl0Oiili <= '0'; + nl0Oiill <= '0'; + nl0OiilO <= '0'; + nl0OiiOi <= '0'; + nl0OiiOl <= '0'; + nl0OiiOO <= '0'; + nl0Oil0i <= '0'; + nl0Oil0l <= '0'; + nl0Oil0O <= '0'; + nl0Oil1i <= '0'; + nl0Oil1l <= '0'; + nl0Oil1O <= '0'; + nl0Oilii <= '0'; + nl0Oilil <= '0'; + nl0OiliO <= '0'; + nl0Oilli <= '0'; + nl0Oilll <= '0'; + nl0OillO <= '0'; + nl0OilOi <= '0'; + nl0OilOl <= '0'; + nl0OilOO <= '0'; + nl0OiO0i <= '0'; + nl0OiO0l <= '0'; + nl0OiO0O <= '0'; + nl0OiO1i <= '0'; + nl0OiO1l <= '0'; + nl0OiO1O <= '0'; + nl0OlOii <= '0'; + nl0OlOOl <= '0'; + nl0OO10i <= '0'; + nl0OO10l <= '0'; + nl0OO10O <= '0'; + nl0OO11l <= '0'; + nl0OO11O <= '0'; + nl0OO1ii <= '0'; + nl0OO1il <= '0'; + nl0OO1iO <= '0'; + nl0OO1li <= '0'; + nl0OO1ll <= '0'; + nl0OO1lO <= '0'; + nl0OO1Oi <= '0'; + nl0OOO0l <= '0'; + nl0OOOlO <= '0'; + nl0OOOOO <= '0'; + nl10000l <= '0'; + nl1000ii <= '0'; + nl1000l <= '0'; + nl1001i <= '0'; + nl1001l <= '0'; + nl1001O <= '0'; + nl1001OO <= '0'; + nl100O0i <= '0'; + nl100O0l <= '0'; + nl100O0O <= '0'; + nl100O1O <= '0'; + nl10101l <= '0'; + nl1010i <= '0'; + nl1010l <= '0'; + nl1010O <= '0'; + nl1011i <= '0'; + nl1011l <= '0'; + nl1011li <= '0'; + nl1011O <= '0'; + nl1011OO <= '0'; + nl101i1O <= '0'; + nl101ii <= '0'; + nl101il <= '0'; + nl101ili <= '0'; + nl101iO <= '0'; + nl101iOi <= '0'; + nl101li <= '0'; + nl101ll <= '0'; + nl101lO <= '0'; + nl101O0i <= '0'; + nl101O0l <= '0'; + nl101O0O <= '0'; + nl101O1l <= '0'; + nl101O1O <= '0'; + nl101Oi <= '0'; + nl101Oii <= '0'; + nl101Oil <= '0'; + nl101OiO <= '0'; + nl101Ol <= '0'; + nl101OO <= '0'; + nl10i10i <= '0'; + nl10i1iO <= '0'; + nl10i1ll <= '0'; + nl10iili <= '0'; + nl10iill <= '0'; + nl10iilO <= '0'; + nl10iiOi <= '0'; + nl10illl <= '0'; + nl10iO1i <= '0'; + nl10iO1O <= '0'; + nl10l01l <= '0'; + nl10l0Ol <= '0'; + nl10l0OO <= '0'; + nl10l1ll <= '0'; + nl10l1Ol <= '0'; + nl10li0i <= '0'; + nl10li0l <= '0'; + nl10li1i <= '0'; + nl10li1l <= '0'; + nl10li1O <= '0'; + nl10lliO <= '0'; + nl10llOl <= '0'; + nl10lO1i <= '0'; + nl10O00i <= '0'; + nl10O0ii <= '0'; + nl10O0li <= '0'; + nl10O0Oi <= '0'; + nl10Oi0i <= '0'; + nl10Oi1i <= '0'; + nl10Oiii <= '0'; + nl10Oili <= '0'; + nl10OOii <= '0'; + nl10OOil <= '0'; + nl10OOiO <= '0'; + nl10OOli <= '0'; + nl10OOll <= '0'; + nl10OOlO <= '0'; + nl10OOOi <= '0'; + nl10OOOl <= '0'; + nl10OOOO <= '0'; + nl11001i <= '0'; + nl11001O <= '0'; + nl1101ll <= '0'; + nl110i0i <= '0'; + nl110iiO <= '0'; + nl110ill <= '0'; + nl110llO <= '0'; + nl110O0i <= '0'; + nl110O1l <= '0'; + nl11101l <= '0'; + nl1110ii <= '0'; + nl1110iO <= '0'; + nl11111i <= '0'; + nl111ili <= '0'; + nl111iOO <= '0'; + nl111l1l <= '0'; + nl111O0i <= '0'; + nl111Oll <= '0'; + nl111OOl <= '0'; + nl11i0Oi <= '0'; + nl11i10l <= '0'; + nl11i1li <= '0'; + nl11i1lO <= '0'; + nl11ii0l <= '0'; + nl11ii1O <= '0'; + nl11il0O <= '0'; + nl11illl <= '0'; + nl11ilO <= '0'; + nl11ilOi <= '0'; + nl11iOi <= '0'; + nl11iOl <= '0'; + nl11iOO <= '0'; + nl11iOOl <= '0'; + nl11l0i <= '0'; + nl11l0il <= '0'; + nl11l0l <= '0'; + nl11l0O <= '0'; + nl11l0OO <= '0'; + nl11l10i <= '0'; + nl11l10O <= '0'; + nl11l1i <= '0'; + nl11l1l <= '0'; + nl11l1O <= '0'; + nl11li1O <= '0'; + nl11lii <= '0'; + nl11lil <= '0'; + nl11liO <= '0'; + nl11ll1i <= '0'; + nl11lli <= '0'; + nl11llil <= '0'; + nl11lll <= '0'; + nl11llll <= '0'; + nl11lOiO <= '0'; + nl11lOl <= '0'; + nl11lOO <= '0'; + nl11O01l <= '0'; + nl11O0i <= '0'; + nl11O0iO <= '0'; + nl11O0l <= '0'; + nl11O0lO <= '0'; + nl11O0O <= '0'; + nl11O10i <= '0'; + nl11O11i <= '0'; + nl11O1i <= '0'; + nl11O1l <= '0'; + nl11O1O <= '0'; + nl11Oii <= '0'; + nl11Oil <= '0'; + nl11Oili <= '0'; + nl11OiO <= '0'; + nl11Ol0l <= '0'; + nl11Ol1l <= '0'; + nl11Oli <= '0'; + nl11Oll <= '0'; + nl11OlO <= '0'; + nl11OO1l <= '0'; + nl11OOi <= '0'; + nl11OOiO <= '0'; + nl11OOl <= '0'; + nl11OOlO <= '0'; + nl11OOO <= '0'; + nl1i0OlO <= '0'; + nl1i0OOi <= '0'; + nl1i110i <= '0'; + nl1i110l <= '0'; + nl1i110O <= '0'; + nl1i111i <= '0'; + nl1i111l <= '0'; + nl1i111O <= '0'; + nl1i11ii <= '0'; + nl1i11il <= '0'; + nl1i11iO <= '0'; + nl1i11li <= '0'; + nl1i11ll <= '0'; + nl1i11lO <= '0'; + nl1i1O1i <= '0'; + nl1i1O1O <= '0'; + nl1ii1ii <= '0'; + nl1ii1lO <= '0'; + nl1ii1Ol <= '0'; + nl1iii0l <= '0'; + nl1iiilO <= '0'; + nl1iiiOO <= '0'; + nl1iilOi <= '0'; + nl1iiO0l <= '0'; + nl1iiOil <= '0'; + nl1il00l <= '0'; + nl1il0il <= '0'; + nl1il0iO <= '0'; + nl1il1Oi <= '0'; + nl1ill0i <= '0'; + nl1ill0l <= '0'; + nl1ill0O <= '0'; + nl1ill1l <= '0'; + nl1ill1O <= '0'; + nl1illii <= '0'; + nl1illil <= '0'; + nl1illiO <= '0'; + nl1illli <= '0'; + nl1illll <= '0'; + nl1illlO <= '0'; + nl1illOi <= '0'; + nl1iO00i <= '0'; + nl1iO01l <= '0'; + nl1iO1lO <= '0'; + nl1iOOii <= '0'; + nl1iOOli <= '0'; + nl1iOOOi <= '0'; + nl1l000O <= '0'; + nl1l00Oi <= '0'; + nl1l010l <= '0'; + nl1l01il <= '0'; + nl1l0i1i <= '0'; + nl1l0iOl <= '0'; + nl1l0l0O <= '0'; + nl1l0liO <= '0'; + nl1l0O0i <= '0'; + nl1l0O0O <= '0'; + nl1l10lO <= '0'; + nl1l110i <= '0'; + nl1l11ll <= '0'; + nl1l11Ol <= '0'; + nl1l1i0i <= '0'; + nl1l1iii <= '0'; + nl1l1l0l <= '0'; + nl1l1llO <= '0'; + nl1l1lOO <= '0'; + nl1l1OOi <= '0'; + nl1li00l <= '0'; + nl1li0il <= '0'; + nl1li0iO <= '0'; + nl1li0li <= '0'; + nl1li0ll <= '0'; + nl1li1Oi <= '0'; + nl1liili <= '0'; + nl1liO0l <= '0'; + nl1liOlO <= '0'; + nl1liOOO <= '0'; + nl1ll00i <= '0'; + nl1ll0ii <= '0'; + nl1ll0ll <= '0'; + nl1ll0Ol <= '0'; + nl1ll0OO <= '0'; + nl1ll10i <= '0'; + nl1ll11i <= '0'; + nl1ll11l <= '0'; + nl1ll11O <= '0'; + nl1lli1i <= '0'; + nl1llilO <= '0'; + nl1lliOl <= '0'; + nl1lliOO <= '0'; + nl1lll1i <= '0'; + nl1llllO <= '0'; + nl1llOiO <= '0'; + nl1lO10i <= '0'; + nl1lO10l <= '0'; + nl1lO11i <= '0'; + nl1lOi0i <= '0'; + nl1lOill <= '0'; + nl1lOiOl <= '0'; + nl1lOiOO <= '0'; + nl1lOl1i <= '0'; + nl1lOl1l <= '0'; + nl1lOl1O <= '0'; + nl1lOO0i <= '0'; + nl1lOO0l <= '0'; + nl1lOO0O <= '0'; + nl1lOOii <= '0'; + nl1lOOil <= '0'; + nl1O000i <= '0'; + nl1O000O <= '0'; + nl1O011i <= '0'; + nl1O01Ol <= '0'; + nl1O0iii <= '0'; + nl1O0ilO <= '0'; + nl1O0iOl <= '0'; + nl1O0lOO <= '0'; + nl1O0O0l <= '0'; + nl1O0Oii <= '0'; + nl1O10ii <= '0'; + nl1O10il <= '0'; + nl1O10iO <= '0'; + nl1O110l <= '0'; + nl1O110O <= '0'; + nl1O11ii <= '0'; + nl1O1i0l <= '0'; + nl1O1ili <= '0'; + nl1O1ilO <= '0'; + nl1O1O0O <= '0'; + nl1O1OOi <= '0'; + nl1Oi1il <= '0'; + nl1Oi1Oi <= '0'; + nl1Oi1OO <= '0'; + nl1Oii1i <= '0'; + nl1Oiiil <= '0'; + nl1Oiill <= '0'; + nl1OiliO <= '0'; + nl1OiO0i <= '0'; + nl1OiO1i <= '0'; + nl1Ol0li <= '0'; + nl1Ol0OO <= '0'; + nl1Ol11l <= '0'; + nl1Ol1ii <= '0'; + nl1Ol1iO <= '0'; + nl1Oli1l <= '0'; + nl1Oll1O <= '0'; + nl1Ollil <= '0'; + nl1Ollli <= '0'; + nl1OlOll <= '0'; + nl1OO11i <= '0'; + nl1OO11O <= '0'; + nl1OOiOi <= '0'; + nl1OOiOl <= '0'; + nl1OOiOO <= '0'; + nl1OOl0i <= '0'; + nl1OOl0l <= '0'; + nl1OOl0O <= '0'; + nl1OOl1i <= '0'; + nl1OOl1l <= '0'; + nl1OOl1O <= '0'; + nl1OOlii <= '0'; + nl1OOlil <= '0'; + nl1OOliO <= '0'; + nl1OOlli <= '0'; + nl1OOlll <= '0'; + nl1OOllO <= '0'; + nl1OOlOi <= '0'; + nl1OOlOl <= '0'; + nl1OOlOO <= '0'; + nl1OOO0i <= '0'; + nl1OOO0l <= '0'; + nl1OOO0O <= '0'; + nl1OOO1i <= '0'; + nl1OOO1l <= '0'; + nl1OOO1O <= '0'; + nl1OOOii <= '0'; + nl1OOOil <= '0'; + nli01iOO <= '0'; + nli1100i <= '0'; + nli110iO <= '0'; + nli1110i <= '0'; + nli1111i <= '0'; + nli1111l <= '0'; + nli1111O <= '0'; + nli1i00i <= '0'; + nli1i00O <= '0'; + nli1i01O <= '0'; + nli1i0ii <= '0'; + nli1i0il <= '0'; + nli1i0iO <= '0'; + nli1i0li <= '0'; + nli1i0ll <= '0'; + nli1i0lO <= '0'; + nli1i10O <= '0'; + nli1i1ll <= '0'; + nli1i1lO <= '0'; + nli1i1Oi <= '0'; + nli1i1Ol <= '0'; + nli1i1OO <= '0'; + nlilli0Oi <= '0'; + nlilli0Ol <= '0'; + nlilli0OO <= '0'; + nlillii0i <= '0'; + nlillii0l <= '0'; + nlillii0O <= '0'; + nlillii1i <= '0'; + nlillii1l <= '0'; + nlillii1O <= '0'; + nlilliiii <= '0'; + nlilliiil <= '0'; + nlilliiiO <= '0'; + nlilliili <= '0'; + nlilliill <= '0'; + nlilliilO <= '0'; + nlilliiOi <= '0'; + nlilliiOl <= '0'; + nlilliiOO <= '0'; + nlillil1i <= '0'; + nlillil1l <= '0'; + nlillil1O <= '0'; + nlillO00i <= '0'; + nlillO00l <= '0'; + nlillO00O <= '0'; + nlillO01i <= '0'; + nlillO01l <= '0'; + nlillO01O <= '0'; + nlillO0ii <= '0'; + nlillO0il <= '0'; + nlillO0iO <= '0'; + nlillO0li <= '0'; + nlillO0ll <= '0'; + nlillO0lO <= '0'; + nlillO0Oi <= '0'; + nlillO0Ol <= '0'; + nlillO0OO <= '0'; + nlillO1Oi <= '0'; + nlillO1Ol <= '0'; + nlillO1OO <= '0'; + nlillOi0i <= '0'; + nlillOi0l <= '0'; + nlillOi0O <= '0'; + nlillOi1i <= '0'; + nlillOi1l <= '0'; + nlillOi1O <= '0'; + nlillOiii <= '0'; + nlillOiil <= '0'; + nlillOiiO <= '0'; + nlillOili <= '0'; + nlillOill <= '0'; + nlillOilO <= '0'; + nlillOiOi <= '0'; + nlillOiOl <= '0'; + nlillOiOO <= '0'; + nlillOl0i <= '0'; + nlillOl0l <= '0'; + nlillOl0O <= '0'; + nlillOl1i <= '0'; + nlillOl1l <= '0'; + nlillOl1O <= '0'; + nlillOlii <= '0'; + nlillOlil <= '0'; + nlillOliO <= '0'; + nlillOlli <= '0'; + nlillOlll <= '0'; + nlillOllO <= '0'; + nlillOlOl <= '0'; + nlilOilli <= '0'; + nlilOilll <= '0'; + nlilOillO <= '0'; + nlilOilOi <= '0'; + nlilOilOl <= '0'; + nlilOilOO <= '0'; + nlilOiO0i <= '0'; + nlilOiO0l <= '0'; + nlilOiO0O <= '0'; + nlilOiO1i <= '0'; + nlilOiO1l <= '0'; + nlilOiO1O <= '0'; + nlilOiOii <= '0'; + nlilOiOil <= '0'; + nlilOiOiO <= '0'; + nlilOiOli <= '0'; + nlilOiOll <= '0'; + nlilOiOlO <= '0'; + nlilOiOOi <= '0'; + nlilOiOOl <= '0'; + nlilOO0iO <= '0'; + nlilOO0li <= '0'; + nlilOO0ll <= '0'; + nliO0i0l <= '0'; + nliO0i0O <= '0'; + nliO0iii <= '0'; + nliO0iil <= '0'; + nliO0iiO <= '0'; + nliO0ili <= '0'; + nliO0ill <= '0'; + nliO0ilO <= '0'; + nliO0iOi <= '0'; + nliO0iOl <= '0'; + nliO0iOO <= '0'; + nliO0l0i <= '0'; + nliO0l0l <= '0'; + nliO0l0O <= '0'; + nliO0l1i <= '0'; + nliO0l1l <= '0'; + nliO0l1O <= '0'; + nliO0lii <= '0'; + nliO0lil <= '0'; + nliO0liO <= '0'; + nliO0lli <= '0'; + nliO0lll <= '0'; + nliO0llO <= '0'; + nliO0lOi <= '0'; + nliO0lOl <= '0'; + nliO0lOO <= '0'; + nliO0O0i <= '0'; + nliO0O0l <= '0'; + nliO0O0O <= '0'; + nliO0O1i <= '0'; + nliO0O1l <= '0'; + nliO0O1O <= '0'; + nliO0Oii <= '0'; + nliO0Oil <= '0'; + nliO0OiO <= '0'; + nliO0Oli <= '0'; + nliO0Oll <= '0'; + nliO0OlO <= '0'; + nliO0OOi <= '0'; + nliO0OOl <= '0'; + nliO0OOO <= '0'; + nliOi00i <= '0'; + nliOi00l <= '0'; + nliOi00O <= '0'; + nliOi01i <= '0'; + nliOi01l <= '0'; + nliOi01O <= '0'; + nliOi0ii <= '0'; + nliOi0il <= '0'; + nliOi0iO <= '0'; + nliOi0li <= '0'; + nliOi0ll <= '0'; + nliOi0lO <= '0'; + nliOi0Oi <= '0'; + nliOi0Ol <= '0'; + nliOi0OO <= '0'; + nliOi10i <= '0'; + nliOi10l <= '0'; + nliOi10O <= '0'; + nliOi11i <= '0'; + nliOi11l <= '0'; + nliOi11O <= '0'; + nliOi1ii <= '0'; + nliOi1il <= '0'; + nliOi1iO <= '0'; + nliOi1li <= '0'; + nliOi1ll <= '0'; + nliOi1lO <= '0'; + nliOi1Oi <= '0'; + nliOi1Ol <= '0'; + nliOi1OO <= '0'; + nliOii0i <= '0'; + nliOii0l <= '0'; + nliOii0O <= '0'; + nliOii1i <= '0'; + nliOii1l <= '0'; + nliOii1O <= '0'; + nliOiiii <= '0'; + nliOiiil <= '0'; + nliOiiiO <= '0'; + nliOiili <= '0'; + nliOiill <= '0'; + nliOiilO <= '0'; + nliOiiOi <= '0'; + nliOiiOl <= '0'; + nliOiiOO <= '0'; + nliOil0i <= '0'; + nliOil0l <= '0'; + nliOil0O <= '0'; + nliOil1i <= '0'; + nliOil1l <= '0'; + nliOil1O <= '0'; + nliOilii <= '0'; + nliOilil <= '0'; + nliOiliO <= '0'; + nliOilli <= '0'; + nliOilll <= '0'; + nliOillO <= '0'; + nliOilOi <= '0'; + nliOilOl <= '0'; + nliOilOO <= '0'; + nliOiO0i <= '0'; + nliOiO0l <= '0'; + nliOiO0O <= '0'; + nliOiO1i <= '0'; + nliOiO1l <= '0'; + nliOiO1O <= '0'; + nliOiOii <= '0'; + nliOiOil <= '0'; + nliOiOiO <= '0'; + nliOiOli <= '0'; + nliOiOll <= '0'; + nliOiOlO <= '0'; + nliOiOOi <= '0'; + nliOiOOl <= '0'; + nliOiOOO <= '0'; + nliOl00i <= '0'; + nliOl00l <= '0'; + nliOl00O <= '0'; + nliOl01i <= '0'; + nliOl01l <= '0'; + nliOl01O <= '0'; + nliOl0ii <= '0'; + nliOl0il <= '0'; + nliOl0iO <= '0'; + nliOl0li <= '0'; + nliOl0ll <= '0'; + nliOl0lO <= '0'; + nliOl0Oi <= '0'; + nliOl0Ol <= '0'; + nliOl0OO <= '0'; + nliOl10i <= '0'; + nliOl10l <= '0'; + nliOl10O <= '0'; + nliOl11i <= '0'; + nliOl11l <= '0'; + nliOl11O <= '0'; + nliOl1ii <= '0'; + nliOl1il <= '0'; + nliOl1iO <= '0'; + nliOl1li <= '0'; + nliOl1ll <= '0'; + nliOl1lO <= '0'; + nliOl1Oi <= '0'; + nliOl1Ol <= '0'; + nliOl1OO <= '0'; + nliOli0i <= '0'; + nliOli0l <= '0'; + nliOli0O <= '0'; + nliOli1i <= '0'; + nliOli1l <= '0'; + nliOli1O <= '0'; + nliOliii <= '0'; + nliOliil <= '0'; + nliOliiO <= '0'; + nliOlili <= '0'; + nliOlill <= '0'; + nll0i000i <= '0'; + nll0i000l <= '0'; + nll0i000O <= '0'; + nll0i001i <= '0'; + nll0i001l <= '0'; + nll0i001O <= '0'; + nll0i00ii <= '0'; + nll0i00il <= '0'; + nll0i00iO <= '0'; + nll0i00li <= '0'; + nll0i00ll <= '0'; + nll0i00lO <= '0'; + nll0i00Oi <= '0'; + nll0i00Ol <= '0'; + nll0i00OO <= '0'; + nll0i01Oi <= '0'; + nll0i01Ol <= '0'; + nll0i01OO <= '0'; + nll0i0i0i <= '0'; + nll0i0i0l <= '0'; + nll0i0i0O <= '0'; + nll0i0i1i <= '0'; + nll0i0i1l <= '0'; + nll0i0i1O <= '0'; + nll0i0iii <= '0'; + nll0i0iil <= '0'; + nll0i0iiO <= '0'; + nll0i0ili <= '0'; + nll0i0ill <= '0'; + nll0i0ilO <= '0'; + nll0i0iOi <= '0'; + nll0i0iOl <= '0'; + nll0i0iOO <= '0'; + nll0i0l0i <= '0'; + nll0i0l0l <= '0'; + nll0i0l0O <= '0'; + nll0i0l1i <= '0'; + nll0i0l1l <= '0'; + nll0i0l1O <= '0'; + nll0i0lii <= '0'; + nll0i0lil <= '0'; + nll0i0liO <= '0'; + nll0i0lli <= '0'; + nll0i0lll <= '0'; + nll0i0llO <= '0'; + nll0i0lOi <= '0'; + nll0i0lOl <= '0'; + nll0i0lOO <= '0'; + nll0i0O0i <= '0'; + nll0i0O0l <= '0'; + nll0i0O0O <= '0'; + nll0i0O1i <= '0'; + nll0i0O1l <= '0'; + nll0i0O1O <= '0'; + nll0i0Oii <= '0'; + nll0i0Oil <= '0'; + nll0i0OiO <= '0'; + nll0i0Oli <= '0'; + nll0i0Oll <= '0'; + nll0i0OlO <= '0'; + nll0i0OOi <= '0'; + nll0i0OOl <= '0'; + nll0i0OOO <= '0'; + nll0iO1lO <= '0'; + nll0liiOi <= '0'; + nll0liiOl <= '0'; + nll0liiOO <= '0'; + nll0lilil <= '0'; + nll0liOii <= '0'; + nll0liOil <= '0'; + nll0liOiO <= '0'; + nll0liOli <= '0'; + nll0liOll <= '0'; + nll0liOlO <= '0'; + nll0liOOi <= '0'; + nll0liOOl <= '0'; + nll0liOOO <= '0'; + nll0ll10i <= '0'; + nll0ll10l <= '0'; + nll0ll10O <= '0'; + nll0ll11i <= '0'; + nll0ll11l <= '0'; + nll0ll11O <= '0'; + nll0ll1ii <= '0'; + nll0ll1il <= '0'; + nll0ll1iO <= '0'; + nll0ll1li <= '0'; + nll0ll1ll <= '0'; + nll0ll1lO <= '0'; + nll0ll1Oi <= '0'; + nll0ll1Ol <= '0'; + nll0ll1OO <= '0'; + nll0lO01i <= '0'; + nll0lO0ii <= '0'; + nll0lO0il <= '0'; + nll0lO0iO <= '0'; + nll0lO0li <= '0'; + nll0lO0ll <= '0'; + nll0lO0lO <= '0'; + nll0lO0Oi <= '0'; + nll0lO0Ol <= '0'; + nll0lO0OO <= '0'; + nll0lOi1i <= '0'; + nll0lOi1l <= '0'; + nll0lOi1O <= '0'; + nll0O0i0i <= '0'; + nll0O0i0l <= '0'; + nll0O0i0O <= '0'; + nll0O0i1O <= '0'; + nll0O0iii <= '0'; + nll0O0iil <= '0'; + nll0O0iiO <= '0'; + nll0O0ili <= '0'; + nll0O0ill <= '0'; + nll0O0ilO <= '0'; + nll0O0iOi <= '0'; + nll0O0iOl <= '0'; + nll0O0iOO <= '0'; + nll0O0l0i <= '0'; + nll0O0l0l <= '0'; + nll0O0l0O <= '0'; + nll0O0l1i <= '0'; + nll0O0l1l <= '0'; + nll0O0l1O <= '0'; + nll0O0lii <= '0'; + nll0O0lil <= '0'; + nll0O0liO <= '0'; + nll0O0lli <= '0'; + nll0O0lll <= '0'; + nll0O0llO <= '0'; + nll0O0lO <= '0'; + nll0O0lOi <= '0'; + nll0O0lOl <= '0'; + nll0O0lOO <= '0'; + nll0O0O0i <= '0'; + nll0O0O0l <= '0'; + nll0O0O0O <= '0'; + nll0O0O1i <= '0'; + nll0O0O1l <= '0'; + nll0O0O1O <= '0'; + nll0O0Oi <= '0'; + nll0O0Oii <= '0'; + nll0O0Oil <= '0'; + nll0O0OiO <= '0'; + nll0O0Ol <= '0'; + nll0O0Oli <= '0'; + nll0O0Oll <= '0'; + nll0O0OlO <= '0'; + nll0O0OO <= '0'; + nll0O0OOi <= '0'; + nll0O0OOl <= '0'; + nll0O0OOO <= '0'; + nll0O100i <= '0'; + nll0O100l <= '0'; + nll0O100O <= '0'; + nll0O101i <= '0'; + nll0O101l <= '0'; + nll0O101O <= '0'; + nll0O10ii <= '0'; + nll0O10il <= '0'; + nll0O10iO <= '0'; + nll0O10li <= '0'; + nll0O10ll <= '0'; + nll0O10lO <= '0'; + nll0O10Oi <= '0'; + nll0O10Ol <= '0'; + nll0O10OO <= '0'; + nll0O11ii <= '0'; + nll0O11il <= '0'; + nll0O11iO <= '0'; + nll0O11li <= '0'; + nll0O11ll <= '0'; + nll0O11lO <= '0'; + nll0O11Oi <= '0'; + nll0O11Ol <= '0'; + nll0O11OO <= '0'; + nll0O1i1i <= '0'; + nll0O1i1l <= '0'; + nll0Oi00i <= '0'; + nll0Oi00l <= '0'; + nll0Oi00O <= '0'; + nll0Oi01i <= '0'; + nll0Oi01l <= '0'; + nll0Oi01O <= '0'; + nll0Oi0i <= '0'; + nll0Oi0ii <= '0'; + nll0Oi0il <= '0'; + nll0Oi0iO <= '0'; + nll0Oi0l <= '0'; + nll0Oi0li <= '0'; + nll0Oi0ll <= '0'; + nll0Oi0lO <= '0'; + nll0Oi0O <= '0'; + nll0Oi0Oi <= '0'; + nll0Oi0Ol <= '0'; + nll0Oi0OO <= '0'; + nll0Oi10i <= '0'; + nll0Oi10l <= '0'; + nll0Oi10O <= '0'; + nll0Oi11i <= '0'; + nll0Oi11l <= '0'; + nll0Oi11O <= '0'; + nll0Oi1i <= '0'; + nll0Oi1ii <= '0'; + nll0Oi1il <= '0'; + nll0Oi1iO <= '0'; + nll0Oi1l <= '0'; + nll0Oi1li <= '0'; + nll0Oi1ll <= '0'; + nll0Oi1lO <= '0'; + nll0Oi1O <= '0'; + nll0Oi1Oi <= '0'; + nll0Oi1Ol <= '0'; + nll0Oi1OO <= '0'; + nll0Oii0i <= '0'; + nll0Oii1i <= '0'; + nll0Oii1l <= '0'; + nll0Oii1O <= '0'; + nll0Oiii <= '0'; + nll0Oiil <= '0'; + nll0OiiO <= '0'; + nll0Oili <= '0'; + nll0OilO <= '0'; + nll0OiOi <= '0'; + nll0OiOl <= '0'; + nll0OiOO <= '0'; + nll0Ol0i <= '0'; + nll0Ol0l <= '0'; + nll0Ol1i <= '0'; + nll0Ol1l <= '0'; + nll0Ol1O <= '0'; + nll0OOOll <= '0'; + nll0OOOlO <= '0'; + nll0OOOOi <= '0'; + nll0OOOOl <= '0'; + nll100Oil <= '0'; + nll11lOli <= '0'; + nll11lOll <= '0'; + nll11lOlO <= '0'; + nll11lOOi <= '0'; + nll11lOOl <= '0'; + nll11lOOO <= '0'; + nll11O00i <= '0'; + nll11O00l <= '0'; + nll11O00O <= '0'; + nll11O01i <= '0'; + nll11O01l <= '0'; + nll11O01O <= '0'; + nll11O0ii <= '0'; + nll11O0il <= '0'; + nll11O0iO <= '0'; + nll11O0li <= '0'; + nll11O0ll <= '0'; + nll11O0lO <= '0'; + nll11O0Oi <= '0'; + nll11O0Ol <= '0'; + nll11O0OO <= '0'; + nll11O10i <= '0'; + nll11O10l <= '0'; + nll11O10O <= '0'; + nll11O11i <= '0'; + nll11O11l <= '0'; + nll11O11O <= '0'; + nll11O1ii <= '0'; + nll11O1il <= '0'; + nll11O1iO <= '0'; + nll11O1li <= '0'; + nll11O1ll <= '0'; + nll11O1lO <= '0'; + nll11O1Oi <= '0'; + nll11O1Ol <= '0'; + nll11O1OO <= '0'; + nll11Oi0i <= '0'; + nll11Oi0l <= '0'; + nll11Oi0O <= '0'; + nll11Oi1i <= '0'; + nll11Oi1l <= '0'; + nll11Oi1O <= '0'; + nll11Oiii <= '0'; + nll11Oiil <= '0'; + nll11OiiO <= '0'; + nll11Oili <= '0'; + nll11Oill <= '0'; + nll11OilO <= '0'; + nll11OiOi <= '0'; + nll11OiOl <= '0'; + nll11OiOO <= '0'; + nll11Ol0i <= '0'; + nll11Ol0l <= '0'; + nll11Ol0O <= '0'; + nll11Ol1i <= '0'; + nll11Ol1l <= '0'; + nll11Ol1O <= '0'; + nll11Olii <= '0'; + nll11Olil <= '0'; + nll11OliO <= '0'; + nll11Olli <= '0'; + nll11Olll <= '0'; + nll11OllO <= '0'; + nlli0i00i <= '0'; + nlli0i00l <= '0'; + nlli0i00O <= '0'; + nlli0i01i <= '0'; + nlli0i01l <= '0'; + nlli0i01O <= '0'; + nlli0i0ii <= '0'; + nlli0i0il <= '0'; + nlli0i0iO <= '0'; + nlli0i0li <= '0'; + nlli0i0ll <= '0'; + nlli0i0lO <= '0'; + nlli0i0Oi <= '0'; + nlli0i0Ol <= '0'; + nlli0i0OO <= '0'; + nlli0i1lO <= '0'; + nlli0i1Oi <= '0'; + nlli0i1Ol <= '0'; + nlli0i1OO <= '0'; + nlli0ii0i <= '0'; + nlli0ii0l <= '0'; + nlli0ii0O <= '0'; + nlli0ii1i <= '0'; + nlli0ii1l <= '0'; + nlli0ii1O <= '0'; + nlli0iiii <= '0'; + nlli0iiil <= '0'; + nlli0iiiO <= '0'; + nlli0iili <= '0'; + nlli0iill <= '0'; + nlli0iilO <= '0'; + nlli0iiOi <= '0'; + nlli0iiOl <= '0'; + nlli0iiOO <= '0'; + nlli0il0i <= '0'; + nlli0il0l <= '0'; + nlli0il0O <= '0'; + nlli0il1i <= '0'; + nlli0il1l <= '0'; + nlli0il1O <= '0'; + nlli0ilii <= '0'; + nlli0ilil <= '0'; + nlli0iliO <= '0'; + nlli0illi <= '0'; + nlli0illl <= '0'; + nlli0illO <= '0'; + nlli0ilOi <= '0'; + nlli0ilOl <= '0'; + nlli0ilOO <= '0'; + nlli0iO1i <= '0'; + nlli0iO1l <= '0'; + nlli0iO1O <= '0'; + nlli1010i <= '0'; + nlli1010l <= '0'; + nlli1010O <= '0'; + nlli1011i <= '0'; + nlli1011l <= '0'; + nlli1011O <= '0'; + nlli101ii <= '0'; + nlli101il <= '0'; + nlli101iO <= '0'; + nlli101li <= '0'; + nlli101ll <= '0'; + nlli1100O <= '0'; + nlli11i1l <= '0'; + nlli11lli <= '0'; + nlli11lll <= '0'; + nlli11llO <= '0'; + nlli11lOi <= '0'; + nlli11lOl <= '0'; + nlli11lOO <= '0'; + nlli11O0i <= '0'; + nlli11O0l <= '0'; + nlli11O0O <= '0'; + nlli11O1i <= '0'; + nlli11O1l <= '0'; + nlli11O1O <= '0'; + nlli11Oii <= '0'; + nlli11Oil <= '0'; + nlli11OiO <= '0'; + nlli11Oli <= '0'; + nlli11Oll <= '0'; + nlli11OlO <= '0'; + nlli11OOi <= '0'; + nlli11OOl <= '0'; + nlli11OOO <= '0'; + nlli1Oi0i <= '0'; + nlli1Oili <= '0'; + nlli1Oill <= '0'; + nlli1OilO <= '0'; + nlli1OiOi <= '0'; + nlli1OiOl <= '0'; + nlli1OiOO <= '0'; + nlli1Ol0i <= '0'; + nlli1Ol0l <= '0'; + nlli1Ol0O <= '0'; + nlli1Ol1i <= '0'; + nlli1Ol1l <= '0'; + nlli1Ol1O <= '0'; + nlli1Olii <= '0'; + nlli1Olil <= '0'; + nlli1OliO <= '0'; + nlli1Olli <= '0'; + nlli1Olll <= '0'; + nlli1OllO <= '0'; + nlli1OlOi <= '0'; + nlli1OlOl <= '0'; + nlli1OlOO <= '0'; + nlli1OO1i <= '0'; + nlli1OO1l <= '0'; + nllii0Oll <= '0'; + nllii0OlO <= '0'; + nlliii0Oi <= '0'; + nlliii0Ol <= '0'; + nlliii0OO <= '0'; + nlliiii0i <= '0'; + nlliiii0l <= '0'; + nlliiii0O <= '0'; + nlliiii1i <= '0'; + nlliiii1l <= '0'; + nlliiii1O <= '0'; + nlliiiiii <= '0'; + nlliiiiil <= '0'; + nlliiiiiO <= '0'; + nlliiiili <= '0'; + nlliiiill <= '0'; + nlliiiilO <= '0'; + nlliiiiOi <= '0'; + nlliiiiOl <= '0'; + nlliiiiOO <= '0'; + nlliiil0i <= '0'; + nlliiil0l <= '0'; + nlliiil0O <= '0'; + nlliiil1i <= '0'; + nlliiil1l <= '0'; + nlliiil1O <= '0'; + nlliiilii <= '0'; + nlliiilil <= '0'; + nlliiiliO <= '0'; + nlliiilli <= '0'; + nlliiilll <= '0'; + nlliiillO <= '0'; + nlliiilOi <= '0'; + nlliiilOl <= '0'; + nllili00i <= '0'; + nllili00l <= '0'; + nllili00O <= '0'; + nllili01i <= '0'; + nllili01l <= '0'; + nllili01O <= '0'; + nllili0ii <= '0'; + nllili0il <= '0'; + nllili0iO <= '0'; + nllili0li <= '0'; + nllili0ll <= '0'; + nllili0lO <= '0'; + nllili0Oi <= '0'; + nllili0Ol <= '0'; + nllili0OO <= '0'; + nllili10i <= '0'; + nllili10l <= '0'; + nllili10O <= '0'; + nllili11O <= '0'; + nllili1ii <= '0'; + nllili1il <= '0'; + nllili1iO <= '0'; + nllili1li <= '0'; + nllili1ll <= '0'; + nllili1lO <= '0'; + nllili1Oi <= '0'; + nllili1Ol <= '0'; + nllili1OO <= '0'; + nllilii0i <= '0'; + nllilii0l <= '0'; + nllilii0O <= '0'; + nllilii1i <= '0'; + nllilii1l <= '0'; + nllilii1O <= '0'; + nlliliiii <= '0'; + nlliliiil <= '0'; + nlliliiiO <= '0'; + nlliliili <= '0'; + nlliliill <= '0'; + nlliliilO <= '0'; + nlliliiOi <= '0'; + nlliliiOl <= '0'; + nlliliiOO <= '0'; + nllilil0i <= '0'; + nllilil0l <= '0'; + nllilil0O <= '0'; + nllilil1i <= '0'; + nllilil1l <= '0'; + nllilil1O <= '0'; + nllillOi <= '0'; + nllillOl <= '0'; + nllillOO <= '0'; + nllilO0i <= '0'; + nllilO0l <= '0'; + nllilO0O <= '0'; + nllilO1i <= '0'; + nllilO1l <= '0'; + nllilO1O <= '0'; + nllilOii <= '0'; + nllilOil <= '0'; + nllilOiO <= '0'; + nllilOli <= '0'; + nllilOll <= '0'; + nllilOlll <= '0'; + nllilOllO <= '0'; + nllilOlO <= '0'; + nllilOlOi <= '0'; + nllilOlOl <= '0'; + nllilOlOO <= '0'; + nllilOO0i <= '0'; + nllilOO0l <= '0'; + nllilOO0O <= '0'; + nllilOO1i <= '0'; + nllilOO1l <= '0'; + nllilOO1O <= '0'; + nllilOOi <= '0'; + nllilOOii <= '0'; + nllilOOil <= '0'; + nllilOOiO <= '0'; + nllilOOl <= '0'; + nllilOOli <= '0'; + nllilOOll <= '0'; + nllilOOlO <= '0'; + nllilOOO <= '0'; + nllilOOOi <= '0'; + nllilOOOl <= '0'; + nllilOOOO <= '0'; + nlliO01i <= '0'; + nlliO101i <= '0'; + nlliO10i <= '0'; + nlliO10l <= '0'; + nlliO10O <= '0'; + nlliO110i <= '0'; + nlliO110l <= '0'; + nlliO110O <= '0'; + nlliO111i <= '0'; + nlliO111l <= '0'; + nlliO111O <= '0'; + nlliO11i <= '0'; + nlliO11ii <= '0'; + nlliO11il <= '0'; + nlliO11iO <= '0'; + nlliO11l <= '0'; + nlliO11li <= '0'; + nlliO11ll <= '0'; + nlliO11lO <= '0'; + nlliO11O <= '0'; + nlliO11Oi <= '0'; + nlliO11Ol <= '0'; + nlliO11OO <= '0'; + nlliO1ii <= '0'; + nlliO1il <= '0'; + nlliO1iO <= '0'; + nlliO1li <= '0'; + nlliO1ll <= '0'; + nlliO1lO <= '0'; + nlliO1Oi <= '0'; + nlliO1Ol <= '0'; + nlliO1OO <= '0'; + nlliOl00i <= '0'; + nlliOl00l <= '0'; + nlliOl00O <= '0'; + nlliOl01i <= '0'; + nlliOl01l <= '0'; + nlliOl01O <= '0'; + nlliOl0ii <= '0'; + nlliOl0il <= '0'; + nlliOl0iO <= '0'; + nlliOl0li <= '0'; + nlliOl0ll <= '0'; + nlliOl0lO <= '0'; + nlliOl0Oi <= '0'; + nlliOl0Ol <= '0'; + nlliOl0OO <= '0'; + nlliOl10O <= '0'; + nlliOl11l <= '0'; + nlliOl1li <= '0'; + nlliOl1ll <= '0'; + nlliOl1lO <= '0'; + nlliOl1Oi <= '0'; + nlliOl1Ol <= '0'; + nlliOl1OO <= '0'; + nlliOli1i <= '0'; + nlliOli1l <= '0'; + nlliOOiOO <= '0'; + nlliOOl0i <= '0'; + nlliOOl0l <= '0'; + nlliOOl0O <= '0'; + nlliOOl1i <= '0'; + nlliOOl1l <= '0'; + nlliOOl1O <= '0'; + nlliOOlii <= '0'; + nlliOOlil <= '0'; + nlliOOliO <= '0'; + nlliOOlli <= '0'; + nlliOOlll <= '0'; + nlliOOllO <= '0'; + nlliOOlOi <= '0'; + nlliOOlOl <= '0'; + nlll000il <= '0'; + nlll000iO <= '0'; + nlll000li <= '0'; + nlll000ll <= '0'; + nlll000lO <= '0'; + nlll000Oi <= '0'; + nlll000Ol <= '0'; + nlll000OO <= '0'; + nlll00i0i <= '0'; + nlll00i0l <= '0'; + nlll00i0O <= '0'; + nlll00i1i <= '0'; + nlll00i1l <= '0'; + nlll00i1O <= '0'; + nlll00iii <= '0'; + nlll00iil <= '0'; + nlll00iiO <= '0'; + nlll00ili <= '0'; + nlll00ill <= '0'; + nlll00ilO <= '0'; + nlll00iOi <= '0'; + nlll00iOl <= '0'; + nlll00iOO <= '0'; + nlll00l1i <= '0'; + nlll0100i <= '0'; + nlll0100l <= '0'; + nlll0100O <= '0'; + nlll0101i <= '0'; + nlll0101l <= '0'; + nlll0101O <= '0'; + nlll010ii <= '0'; + nlll010il <= '0'; + nlll010iO <= '0'; + nlll010li <= '0'; + nlll010ll <= '0'; + nlll010lO <= '0'; + nlll010Oi <= '0'; + nlll010Ol <= '0'; + nlll010OO <= '0'; + nlll011OO <= '0'; + nlll01i1i <= '0'; + nlll0il1O <= '0'; + nlll0ilOl <= '0'; + nlll0ilOO <= '0'; + nlll0iO0i <= '0'; + nlll0iO0l <= '0'; + nlll0iO0O <= '0'; + nlll0iO1i <= '0'; + nlll0iO1l <= '0'; + nlll0iO1O <= '0'; + nlll0iOii <= '0'; + nlll0iOil <= '0'; + nlll0iOiO <= '0'; + nlll0iOli <= '0'; + nlll0iOll <= '0'; + nlll0iOlO <= '0'; + nlll0iOOi <= '0'; + nlll0iOOl <= '0'; + nlll0iOOO <= '0'; + nlll0llO <= '0'; + nlll11l0l <= '0'; + nlll11l0O <= '0'; + nlll11lii <= '0'; + nlll11lil <= '0'; + nlll11liO <= '0'; + nlll11lli <= '0'; + nlll11lll <= '0'; + nlll11llO <= '0'; + nlll11lOi <= '0'; + nlll11lOl <= '0'; + nlll11lOO <= '0'; + nlll11O1i <= '0'; + nlll11O1l <= '0'; + nlll1il0i <= '0'; + nlll1il0l <= '0'; + nlll1il0O <= '0'; + nlll1il1l <= '0'; + nlll1il1O <= '0'; + nlll1ilii <= '0'; + nlll1iliO <= '0'; + nlll1llOl <= '0'; + nlll1llOO <= '0'; + nlll1lO0i <= '0'; + nlll1lO0l <= '0'; + nlll1lO0O <= '0'; + nlll1lO1i <= '0'; + nlll1lO1l <= '0'; + nlll1lO1O <= '0'; + nlll1lOii <= '0'; + nlll1lOil <= '0'; + nlll1lOiO <= '0'; + nlll1lOli <= '0'; + nlll1lOll <= '0'; + nlll1lOlO <= '0'; + nlll1lOOi <= '0'; + nlll1lOOl <= '0'; + nlll1lOOO <= '0'; + nlll1OO0O <= '0'; + nlll1OOil <= '0'; + nllli0il <= '0'; + nllli0Oi <= '0'; + nllli0Ol <= '0'; + nllli0OO <= '0'; + nllli10O <= '0'; + nllli1ii <= '0'; + nllli1il <= '0'; + nlllii0i <= '0'; + nlllii0l <= '0'; + nlllii0O <= '0'; + nlllii1i <= '0'; + nlllii1l <= '0'; + nlllii1O <= '0'; + nllliiii <= '0'; + nllliiil <= '0'; + nllliiiO <= '0'; + nllliili <= '0'; + nllliill <= '0'; + nllliilO <= '0'; + nllliiOi <= '0'; + nlllOlll <= '0'; + nlllOllO <= '0'; + nlllOlOi <= '0'; + nlllOlOl <= '0'; + nlllOlOO <= '0'; + nlllOO0i <= '0'; + nlllOO0l <= '0'; + nlllOO0O <= '0'; + nlllOO1i <= '0'; + nlllOO1l <= '0'; + nlllOO1O <= '0'; + nlllOOii <= '0'; + nlllOOil <= '0'; + nlllOOiO <= '0'; + nlllOOli <= '0'; + nlllOOll <= '0'; + nlllOOlO <= '0'; + nlllOOOi <= '0'; + nlllOOOl <= '0'; + nlllOOOO <= '0'; + nllO000i <= '0'; + nllO000l <= '0'; + nllO000O <= '0'; + nllO001i <= '0'; + nllO001l <= '0'; + nllO001O <= '0'; + nllO00ii <= '0'; + nllO00il <= '0'; + nllO00iO <= '0'; + nllO00li <= '0'; + nllO00ll <= '0'; + nllO00lO <= '0'; + nllO00Oi <= '0'; + nllO00Ol <= '0'; + nllO00OO <= '0'; + nllO010i <= '0'; + nllO010l <= '0'; + nllO010O <= '0'; + nllO011i <= '0'; + nllO011l <= '0'; + nllO011O <= '0'; + nllO01ii <= '0'; + nllO01il <= '0'; + nllO01iO <= '0'; + nllO01li <= '0'; + nllO01ll <= '0'; + nllO01lO <= '0'; + nllO01Oi <= '0'; + nllO01Ol <= '0'; + nllO01OO <= '0'; + nllO0i0i <= '0'; + nllO0i0l <= '0'; + nllO0i0O <= '0'; + nllO0i1i <= '0'; + nllO0i1l <= '0'; + nllO0i1O <= '0'; + nllO100i <= '0'; + nllO100l <= '0'; + nllO100O <= '0'; + nllO101i <= '0'; + nllO101l <= '0'; + nllO101O <= '0'; + nllO10ii <= '0'; + nllO10il <= '0'; + nllO10iO <= '0'; + nllO10li <= '0'; + nllO10ll <= '0'; + nllO10lO <= '0'; + nllO10Oi <= '0'; + nllO10Ol <= '0'; + nllO10OO <= '0'; + nllO110i <= '0'; + nllO110l <= '0'; + nllO110O <= '0'; + nllO111i <= '0'; + nllO111l <= '0'; + nllO111O <= '0'; + nllO11ii <= '0'; + nllO11il <= '0'; + nllO11iO <= '0'; + nllO11li <= '0'; + nllO11ll <= '0'; + nllO11lO <= '0'; + nllO11Oi <= '0'; + nllO11Ol <= '0'; + nllO11OO <= '0'; + nllO1i0i <= '0'; + nllO1i0l <= '0'; + nllO1i0O <= '0'; + nllO1i1i <= '0'; + nllO1i1l <= '0'; + nllO1i1O <= '0'; + nllO1iii <= '0'; + nllO1iil <= '0'; + nllO1iiO <= '0'; + nllO1ili <= '0'; + nllO1ill <= '0'; + nllO1ilO <= '0'; + nllO1iOi <= '0'; + nllO1iOl <= '0'; + nllO1iOO <= '0'; + nllO1l0i <= '0'; + nllO1l0l <= '0'; + nllO1l0O <= '0'; + nllO1l1i <= '0'; + nllO1l1l <= '0'; + nllO1l1O <= '0'; + nllO1lii <= '0'; + nllO1lil <= '0'; + nllO1liO <= '0'; + nllO1lli <= '0'; + nllO1lll <= '0'; + nllO1llO <= '0'; + nllO1lOi <= '0'; + nllO1lOl <= '0'; + nllO1lOO <= '0'; + nllO1O0i <= '0'; + nllO1O0l <= '0'; + nllO1O0O <= '0'; + nllO1O1i <= '0'; + nllO1O1l <= '0'; + nllO1O1O <= '0'; + nllO1Oii <= '0'; + nllO1Oil <= '0'; + nllO1OiO <= '0'; + nllO1Oli <= '0'; + nllO1Oll <= '0'; + nllO1OlO <= '0'; + nllO1OOi <= '0'; + nllO1OOl <= '0'; + nllO1OOO <= '0'; + nllOil00i <= '0'; + nllOil00l <= '0'; + nllOil00O <= '0'; + nllOil01i <= '0'; + nllOil01l <= '0'; + nllOil01O <= '0'; + nllOil0ii <= '0'; + nllOil0il <= '0'; + nllOil0iO <= '0'; + nllOil0li <= '0'; + nllOil0ll <= '0'; + nllOil0lO <= '0'; + nllOil0Oi <= '0'; + nllOil0Ol <= '0'; + nllOil0OO <= '0'; + nllOil10O <= '0'; + nllOil1ii <= '0'; + nllOil1il <= '0'; + nllOil1iO <= '0'; + nllOil1li <= '0'; + nllOil1ll <= '0'; + nllOil1lO <= '0'; + nllOil1Oi <= '0'; + nllOil1Ol <= '0'; + nllOil1OO <= '0'; + nllOili0i <= '0'; + nllOili0l <= '0'; + nllOili0O <= '0'; + nllOili1i <= '0'; + nllOili1l <= '0'; + nllOili1O <= '0'; + nllOl11OO <= '0'; + nlO00lOiO <= '0'; + nlO00lOli <= '0'; + nlO00lOll <= '0'; + nlO00lOlO <= '0'; + nlO00lOOi <= '0'; + nlO00lOOl <= '0'; + nlO00lOOO <= '0'; + nlO00O11i <= '0'; + nlO00O11O <= '0'; + nlO0il00i <= '0'; + nlO0il00l <= '0'; + nlO0il00O <= '0'; + nlO0il01O <= '0'; + nlO0il0ii <= '0'; + nlO0il0il <= '0'; + nlO0il0iO <= '0'; + nlO0il0li <= '0'; + nlO0il0ll <= '0'; + nlO0il0lO <= '0'; + nlO0il0Oi <= '0'; + nlO0il0Ol <= '0'; + nlO0il0OO <= '0'; + nlO0ili0i <= '0'; + nlO0ili0l <= '0'; + nlO0ili0O <= '0'; + nlO0ili1i <= '0'; + nlO0ili1l <= '0'; + nlO0ili1O <= '0'; + nlO0iliii <= '0'; + nlO0iliil <= '0'; + nlO0iliiO <= '0'; + nlO0ilili <= '0'; + nlO0ilill <= '0'; + nlO0ililO <= '0'; + nlO0iliOi <= '0'; + nlO0iliOl <= '0'; + nlO0iliOO <= '0'; + nlO0ill0i <= '0'; + nlO0ill0l <= '0'; + nlO0ill0O <= '0'; + nlO0ill1i <= '0'; + nlO0ill1l <= '0'; + nlO0ill1O <= '0'; + nlO0illii <= '0'; + nlO0illil <= '0'; + nlO0illiO <= '0'; + nlO0illli <= '0'; + nlO0illll <= '0'; + nlO0illlO <= '0'; + nlO0illOi <= '0'; + nlO0illOl <= '0'; + nlO0illOO <= '0'; + nlO0ilO0i <= '0'; + nlO0ilO0l <= '0'; + nlO0ilO0O <= '0'; + nlO0ilO1i <= '0'; + nlO0ilO1l <= '0'; + nlO0ilO1O <= '0'; + nlO0ilOii <= '0'; + nlO0ilOil <= '0'; + nlO0ilOiO <= '0'; + nlO0ilOli <= '0'; + nlO0ilOll <= '0'; + nlO0ilOlO <= '0'; + nlO0ilOOi <= '0'; + nlO0ilOOl <= '0'; + nlO0ilOOO <= '0'; + nlO0iO00i <= '0'; + nlO0iO00l <= '0'; + nlO0iO00O <= '0'; + nlO0iO01i <= '0'; + nlO0iO01l <= '0'; + nlO0iO01O <= '0'; + nlO0iO0ii <= '0'; + nlO0iO0il <= '0'; + nlO0iO0iO <= '0'; + nlO0iO0li <= '0'; + nlO0iO0ll <= '0'; + nlO0iO0lO <= '0'; + nlO0iO0Oi <= '0'; + nlO0iO0Ol <= '0'; + nlO0iO0OO <= '0'; + nlO0iO10i <= '0'; + nlO0iO10l <= '0'; + nlO0iO10O <= '0'; + nlO0iO11i <= '0'; + nlO0iO11l <= '0'; + nlO0iO11O <= '0'; + nlO0iO1ii <= '0'; + nlO0iO1il <= '0'; + nlO0iO1iO <= '0'; + nlO0iO1li <= '0'; + nlO0iO1ll <= '0'; + nlO0iO1lO <= '0'; + nlO0iO1Oi <= '0'; + nlO0iO1Ol <= '0'; + nlO0iO1OO <= '0'; + nlO0iOi0i <= '0'; + nlO0iOi0l <= '0'; + nlO0iOi0O <= '0'; + nlO0iOi1i <= '0'; + nlO0iOi1l <= '0'; + nlO0iOi1O <= '0'; + nlO0iOiii <= '0'; + nlO0iOiil <= '0'; + nlO0iOiiO <= '0'; + nlO0iOili <= '0'; + nlO0iOill <= '0'; + nlO0iOilO <= '0'; + nlO0iOiOi <= '0'; + nlO0iOiOl <= '0'; + nlO0iOiOO <= '0'; + nlO0li0OO <= '0'; + nlO0lii0i <= '0'; + nlO0lii0l <= '0'; + nlO0lii0O <= '0'; + nlO0lii1i <= '0'; + nlO0lii1l <= '0'; + nlO0lii1O <= '0'; + nlO0liiii <= '0'; + nlO0liiil <= '0'; + nlO0liiiO <= '0'; + nlO0liili <= '0'; + nlO0liill <= '0'; + nlO0liilO <= '0'; + nlO0liiOi <= '0'; + nlO0liiOl <= '0'; + nlO0liiOO <= '0'; + nlO0lil0i <= '0'; + nlO0lil0l <= '0'; + nlO0lil0O <= '0'; + nlO0lil1i <= '0'; + nlO0lil1l <= '0'; + nlO0lil1O <= '0'; + nlO0lilii <= '0'; + nlO0lilil <= '0'; + nlO0liliO <= '0'; + nlO0lilli <= '0'; + nlO0lliO <= '0'; + nlO0llli <= '0'; + nlO0llll <= '0'; + nlO0llOi <= '0'; + nlO0Ol00l <= '0'; + nlO0Ol00O <= '0'; + nlO0Ol0ii <= '0'; + nlO0Ol0il <= '0'; + nlO0Ol0iO <= '0'; + nlO0Ol0li <= '0'; + nlO0Ol0ll <= '0'; + nlO0Ol0lO <= '0'; + nlO0Ol0Oi <= '0'; + nlO0Ol0Ol <= '0'; + nlO0Ol0OO <= '0'; + nlO0Oli0i <= '0'; + nlO0Oli0l <= '0'; + nlO0Oli0O <= '0'; + nlO0Oli1i <= '0'; + nlO0Oli1l <= '0'; + nlO0Oli1O <= '0'; + nlO0Oliii <= '0'; + nlO0Oliil <= '0'; + nlO0OliiO <= '0'; + nlO0Olili <= '0'; + nlO0Olill <= '0'; + nlO0OlilO <= '0'; + nlO0OliOi <= '0'; + nlO0OliOl <= '0'; + nlO0OliOO <= '0'; + nlO0Oll0i <= '0'; + nlO0Oll0l <= '0'; + nlO0Oll0O <= '0'; + nlO0Oll1i <= '0'; + nlO0Oll1l <= '0'; + nlO0Oll1O <= '0'; + nlO0Ollii <= '0'; + nlO0Ollil <= '0'; + nlO0OlliO <= '0'; + nlO0Ollli <= '0'; + nlO0Ollll <= '0'; + nlO0OlllO <= '0'; + nlO0OllOi <= '0'; + nlO0OllOl <= '0'; + nlO0OllOO <= '0'; + nlO0OlO0i <= '0'; + nlO0OlO0l <= '0'; + nlO0OlO0O <= '0'; + nlO0OlO1i <= '0'; + nlO0OlO1l <= '0'; + nlO0OlO1O <= '0'; + nlO0OlOii <= '0'; + nlO0OOOO <= '0'; + nlO1iiOi <= '0'; + nlO1lOi0O <= '0'; + nlO1lOiii <= '0'; + nlO1lOiil <= '0'; + nlO1lOiiO <= '0'; + nlO1lOili <= '0'; + nlO1lOill <= '0'; + nlO1lOilO <= '0'; + nlO1lOiOi <= '0'; + nlO1lOiOl <= '0'; + nlO1lOiOO <= '0'; + nlO1lOl0i <= '0'; + nlO1lOl0l <= '0'; + nlO1lOl0O <= '0'; + nlO1lOl1i <= '0'; + nlO1lOl1l <= '0'; + nlO1lOl1O <= '0'; + nlO1lOlii <= '0'; + nlO1lOlil <= '0'; + nlO1lOliO <= '0'; + nlO1lOlli <= '0'; + nlO1lOlll <= '0'; + nlO1lOllO <= '0'; + nlO1lOlOi <= '0'; + nlO1lOlOl <= '0'; + nlO1lOlOO <= '0'; + nlO1lOO0i <= '0'; + nlO1lOO0l <= '0'; + nlO1lOO0O <= '0'; + nlO1lOO1i <= '0'; + nlO1lOO1l <= '0'; + nlO1lOO1O <= '0'; + nlO1O0l1i <= '0'; + nlO1O0O0i <= '0'; + nlO1Oi00i <= '0'; + nlO1Oi00l <= '0'; + nlO1Oi00O <= '0'; + nlO1Oi01i <= '0'; + nlO1Oi01l <= '0'; + nlO1Oi01O <= '0'; + nlO1Oi0ii <= '0'; + nlO1Oi0il <= '0'; + nlO1Oi0iO <= '0'; + nlO1Oi0li <= '0'; + nlO1Oi0ll <= '0'; + nlO1Oi0lO <= '0'; + nlO1Oi0Oi <= '0'; + nlO1Oi0Ol <= '0'; + nlO1Oi0OO <= '0'; + nlO1Oi10i <= '0'; + nlO1Oi10l <= '0'; + nlO1Oi10O <= '0'; + nlO1Oi1ll <= '0'; + nlO1Oi1lO <= '0'; + nlO1Oi1Oi <= '0'; + nlO1Oi1Ol <= '0'; + nlO1Oi1OO <= '0'; + nlO1Oii0i <= '0'; + nlO1Oii0l <= '0'; + nlO1Oii0O <= '0'; + nlO1Oii1i <= '0'; + nlO1Oii1l <= '0'; + nlO1Oii1O <= '0'; + nlO1Oiiii <= '0'; + nlO1Oiiil <= '0'; + nlO1OiiiO <= '0'; + nlO1Oiili <= '0'; + nlO1Oiill <= '0'; + nlO1OiilO <= '0'; + nlO1OiiOi <= '0'; + nlO1OiiOl <= '0'; + nlO1OiiOO <= '0'; + nlO1Oil0i <= '0'; + nlO1Oil0l <= '0'; + nlO1Oil0O <= '0'; + nlO1Oil1i <= '0'; + nlO1Oil1l <= '0'; + nlO1Oil1O <= '0'; + nlO1Oilii <= '0'; + nlO1Oilil <= '0'; + nlO1OiliO <= '0'; + nlO1Oilli <= '0'; + nlO1Oilll <= '0'; + nlO1OillO <= '0'; + nlO1OilOi <= '0'; + nlO1OilOl <= '0'; + nlO1OilOO <= '0'; + nlO1OiO0i <= '0'; + nlO1OiO0l <= '0'; + nlO1OiO0O <= '0'; + nlO1OiO1i <= '0'; + nlO1OiO1l <= '0'; + nlO1OiO1O <= '0'; + nlO1OiOii <= '0'; + nlO1OiOil <= '0'; + nlO1OiOiO <= '0'; + nlO1OiOli <= '0'; + nlO1OiOll <= '0'; + nlO1OiOlO <= '0'; + nlO1OiOOi <= '0'; + nlO1OiOOl <= '0'; + nlO1OiOOO <= '0'; + nlO1Ol10i <= '0'; + nlO1Ol10l <= '0'; + nlO1Ol10O <= '0'; + nlO1Ol11i <= '0'; + nlO1Ol11l <= '0'; + nlO1Ol11O <= '0'; + nlO1Ol1ii <= '0'; + nlO1Ol1il <= '0'; + nlO1Ol1iO <= '0'; + nlO1Ol1li <= '0'; + nlOi000i <= '0'; + nlOi000iO <= '0'; + nlOi000l <= '0'; + nlOi000O <= '0'; + nlOi000Ol <= '0'; + nlOi0010l <= '0'; + nlOi001i <= '0'; + nlOi001ii <= '0'; + nlOi001l <= '0'; + nlOi001O <= '0'; + nlOi00i1i <= '0'; + nlOi00ii <= '0'; + nlOi00il <= '0'; + nlOi00iO <= '0'; + nlOi00l0l <= '0'; + nlOi00l1i <= '0'; + nlOi00li <= '0'; + nlOi00lil <= '0'; + nlOi00ll <= '0'; + nlOi00llO <= '0'; + nlOi00lO <= '0'; + nlOi00O0l <= '0'; + nlOi00Oi <= '0'; + nlOi00Ol <= '0'; + nlOi00OlO <= '0'; + nlOi00OO <= '0'; + nlOi010i <= '0'; + nlOi010l <= '0'; + nlOi010O <= '0'; + nlOi011i <= '0'; + nlOi011l <= '0'; + nlOi011O <= '0'; + nlOi01ii <= '0'; + nlOi01il <= '0'; + nlOi01iO <= '0'; + nlOi01li <= '0'; + nlOi01ll <= '0'; + nlOi01lO <= '0'; + nlOi01Oi <= '0'; + nlOi01Ol <= '0'; + nlOi01OO <= '0'; + nlOi01OOO <= '0'; + nlOi0i00i <= '0'; + nlOi0i0i <= '0'; + nlOi0i0l <= '0'; + nlOi0i0O <= '0'; + nlOi0i10i <= '0'; + nlOi0i11l <= '0'; + nlOi0i1i <= '0'; + nlOi0i1l <= '0'; + nlOi0i1O <= '0'; + nlOi0iii <= '0'; + nlOi0iil <= '0'; + nlOi0iiO <= '0'; + nlOi0ili <= '0'; + nlOi0ill <= '0'; + nlOi0ilO <= '0'; + nlOi0iOi <= '0'; + nlOi0iOl <= '0'; + nlOi0iOO <= '0'; + nlOi0l00O <= '0'; + nlOi0l01O <= '0'; + nlOi0l0i <= '0'; + nlOi0l0ii <= '0'; + nlOi0l0il <= '0'; + nlOi0l0iO <= '0'; + nlOi0l0l <= '0'; + nlOi0l0li <= '0'; + nlOi0l0ll <= '0'; + nlOi0l0lO <= '0'; + nlOi0l0O <= '0'; + nlOi0l0Oi <= '0'; + nlOi0l0Ol <= '0'; + nlOi0l0OO <= '0'; + nlOi0l1i <= '0'; + nlOi0l1l <= '0'; + nlOi0l1ll <= '0'; + nlOi0l1O <= '0'; + nlOi0li1i <= '0'; + nlOi0li1l <= '0'; + nlOi0li1O <= '0'; + nlOi0lii <= '0'; + nlOi0lil <= '0'; + nlOi0liO <= '0'; + nlOi0lli <= '0'; + nlOi0lll <= '0'; + nlOi0llO <= '0'; + nlOi0lO0l <= '0'; + nlOi0lOi <= '0'; + nlOi0lOl <= '0'; + nlOi0lOO <= '0'; + nlOi0lOOl <= '0'; + nlOi0O0i <= '0'; + nlOi0O0ii <= '0'; + nlOi0O0l <= '0'; + nlOi0O0lO <= '0'; + nlOi0O0O <= '0'; + nlOi0O0Ol <= '0'; + nlOi0O10O <= '0'; + nlOi0O1i <= '0'; + nlOi0O1iO <= '0'; + nlOi0O1l <= '0'; + nlOi0O1O <= '0'; + nlOi0Oii <= '0'; + nlOi0Oil <= '0'; + nlOi0OiO <= '0'; + nlOi0Ol0O <= '0'; + nlOi0Ol1i <= '0'; + nlOi0Oli <= '0'; + nlOi0Olil <= '0'; + nlOi0Oll <= '0'; + nlOi0OlO <= '0'; + nlOi0OOi <= '0'; + nlOi0OOl <= '0'; + nlOi0OOll <= '0'; + nlOi0OOO <= '0'; + nlOi100i <= '0'; + nlOi100l <= '0'; + nlOi100O <= '0'; + nlOi101i <= '0'; + nlOi101l <= '0'; + nlOi101O <= '0'; + nlOi10ii <= '0'; + nlOi10il <= '0'; + nlOi10iO <= '0'; + nlOi10li <= '0'; + nlOi10ll <= '0'; + nlOi10lO <= '0'; + nlOi10Oi <= '0'; + nlOi10Ol <= '0'; + nlOi10OO <= '0'; + nlOi110i <= '0'; + nlOi110l <= '0'; + nlOi110O <= '0'; + nlOi111i <= '0'; + nlOi111l <= '0'; + nlOi111O <= '0'; + nlOi11ii <= '0'; + nlOi11il <= '0'; + nlOi11iO <= '0'; + nlOi11li <= '0'; + nlOi11ll <= '0'; + nlOi11lO <= '0'; + nlOi11Oi <= '0'; + nlOi11Ol <= '0'; + nlOi11OO <= '0'; + nlOi1i0i <= '0'; + nlOi1i0l <= '0'; + nlOi1i0O <= '0'; + nlOi1i1i <= '0'; + nlOi1i1l <= '0'; + nlOi1i1O <= '0'; + nlOi1iii <= '0'; + nlOi1iil <= '0'; + nlOi1iiO <= '0'; + nlOi1ili <= '0'; + nlOi1ill <= '0'; + nlOi1ilO <= '0'; + nlOi1iOi <= '0'; + nlOi1iOl <= '0'; + nlOi1iOO <= '0'; + nlOi1l0i <= '0'; + nlOi1l0l <= '0'; + nlOi1l0O <= '0'; + nlOi1l1i <= '0'; + nlOi1l1l <= '0'; + nlOi1l1O <= '0'; + nlOi1lii <= '0'; + nlOi1lil <= '0'; + nlOi1liO <= '0'; + nlOi1lli <= '0'; + nlOi1lll <= '0'; + nlOi1llO <= '0'; + nlOi1lOi <= '0'; + nlOi1lOl <= '0'; + nlOi1lOO <= '0'; + nlOi1O0i <= '0'; + nlOi1O0l <= '0'; + nlOi1O0O <= '0'; + nlOi1O1i <= '0'; + nlOi1O1l <= '0'; + nlOi1O1O <= '0'; + nlOi1Oii <= '0'; + nlOi1Oil <= '0'; + nlOi1Oill <= '0'; + nlOi1OilO <= '0'; + nlOi1OiO <= '0'; + nlOi1OiOi <= '0'; + nlOi1OiOl <= '0'; + nlOi1OiOO <= '0'; + nlOi1Ol1i <= '0'; + nlOi1Ol1l <= '0'; + nlOi1Ol1O <= '0'; + nlOi1Oli <= '0'; + nlOi1Oll <= '0'; + nlOi1OlO <= '0'; + nlOi1OOi <= '0'; + nlOi1OOl <= '0'; + nlOi1OOO <= '0'; + nlOii00i <= '0'; + nlOii00l <= '0'; + nlOii00O <= '0'; + nlOii01i <= '0'; + nlOii01ii <= '0'; + nlOii01l <= '0'; + nlOii01lO <= '0'; + nlOii01O <= '0'; + nlOii01Ol <= '0'; + nlOii0i0O <= '0'; + nlOii0i1i <= '0'; + nlOii0ii <= '0'; + nlOii0iil <= '0'; + nlOii0il <= '0'; + nlOii0iO <= '0'; + nlOii0li <= '0'; + nlOii0lil <= '0'; + nlOii0ll <= '0'; + nlOii0llO <= '0'; + nlOii0lO <= '0'; + nlOii0O0l <= '0'; + nlOii0O1i <= '0'; + nlOii0Oi <= '0'; + nlOii0OiO <= '0'; + nlOii0Ol <= '0'; + nlOii0OlO <= '0'; + nlOii0OO <= '0'; + nlOii100l <= '0'; + nlOii101i <= '0'; + nlOii10i <= '0'; + nlOii10iO <= '0'; + nlOii10l <= '0'; + nlOii10O <= '0'; + nlOii10Oi <= '0'; + nlOii110O <= '0'; + nlOii111O <= '0'; + nlOii11i <= '0'; + nlOii11l <= '0'; + nlOii11O <= '0'; + nlOii1i0i <= '0'; + nlOii1ii <= '0'; + nlOii1iiO <= '0'; + nlOii1il <= '0'; + nlOii1ill <= '0'; + nlOii1iO <= '0'; + nlOii1li <= '0'; + nlOii1ll <= '0'; + nlOii1lO <= '0'; + nlOii1lOi <= '0'; + nlOii1O0l <= '0'; + nlOii1O1O <= '0'; + nlOii1Oi <= '0'; + nlOii1Ol <= '0'; + nlOii1OO <= '0'; + nlOiii00O <= '0'; + nlOiii01i <= '0'; + nlOiii0i <= '0'; + nlOiii0il <= '0'; + nlOiii0l <= '0'; + nlOiii0O <= '0'; + nlOiii10l <= '0'; + nlOiii11i <= '0'; + nlOiii1i <= '0'; + nlOiii1iO <= '0'; + nlOiii1l <= '0'; + nlOiii1O <= '0'; + nlOiiiii <= '0'; + nlOiiiiiO <= '0'; + nlOiiiil <= '0'; + nlOiiiill <= '0'; + nlOiiiiO <= '0'; + nlOiiiiOi <= '0'; + nlOiiili <= '0'; + nlOiiill <= '0'; + nlOiiilO <= '0'; + nlOiiiO0l <= '0'; + nlOiiiO0O <= '0'; + nlOiiiOi <= '0'; + nlOiiiOii <= '0'; + nlOiiiOil <= '0'; + nlOiiiOiO <= '0'; + nlOiiiOl <= '0'; + nlOiiiOli <= '0'; + nlOiiiOll <= '0'; + nlOiiiOO <= '0'; + nlOiil00l <= '0'; + nlOiil0i <= '0'; + nlOiil0ii <= '0'; + nlOiil0l <= '0'; + nlOiil0O <= '0'; + nlOiil1i <= '0'; + nlOiil1l <= '0'; + nlOiil1O <= '0'; + nlOiil1OO <= '0'; + nlOiilii <= '0'; + nlOiilil <= '0'; + nlOiiliO <= '0'; + nlOiilli <= '0'; + nlOiilll <= '0'; + nlOiillO <= '0'; + nlOiilO0i <= '0'; + nlOiilO0l <= '0'; + nlOiilO1O <= '0'; + nlOiilOi <= '0'; + nlOiilOl <= '0'; + nlOiilOO <= '0'; + nlOiiO0i <= '0'; + nlOiiO0l <= '0'; + nlOiiO0O <= '0'; + nlOiiO10O <= '0'; + nlOiiO11i <= '0'; + nlOiiO1i <= '0'; + nlOiiO1il <= '0'; + nlOiiO1l <= '0'; + nlOiiO1O <= '0'; + nlOiiOii <= '0'; + nlOiiOiiO <= '0'; + nlOiiOil <= '0'; + nlOiiOili <= '0'; + nlOiiOill <= '0'; + nlOiiOilO <= '0'; + nlOiiOiO <= '0'; + nlOiiOli <= '0'; + nlOiiOll <= '0'; + nlOiiOlli <= '0'; + nlOiiOlO <= '0'; + nlOiiOlOO <= '0'; + nlOiiOO1l <= '0'; + nlOiiOOi <= '0'; + nlOiiOOl <= '0'; + nlOiiOOO <= '0'; + nlOil001i <= '0'; + nlOil00i <= '0'; + nlOil00l <= '0'; + nlOil00O <= '0'; + nlOil010i <= '0'; + nlOil010O <= '0'; + nlOil011O <= '0'; + nlOil01i <= '0'; + nlOil01ii <= '0'; + nlOil01il <= '0'; + nlOil01iO <= '0'; + nlOil01l <= '0'; + nlOil01li <= '0'; + nlOil01ll <= '0'; + nlOil01lO <= '0'; + nlOil01O <= '0'; + nlOil01Oi <= '0'; + nlOil01Ol <= '0'; + nlOil01OO <= '0'; + nlOil0ii <= '0'; + nlOil0il <= '0'; + nlOil0iO <= '0'; + nlOil0li <= '0'; + nlOil0ll <= '0'; + nlOil0lO <= '0'; + nlOil0Oi <= '0'; + nlOil0Ol <= '0'; + nlOil0OO <= '0'; + nlOil10i <= '0'; + nlOil10l <= '0'; + nlOil10O <= '0'; + nlOil11i <= '0'; + nlOil11l <= '0'; + nlOil11O <= '0'; + nlOil1ii <= '0'; + nlOil1il <= '0'; + nlOil1iO <= '0'; + nlOil1li <= '0'; + nlOil1ll <= '0'; + nlOil1lO <= '0'; + nlOil1O1O <= '0'; + nlOil1Oi <= '0'; + nlOil1Oil <= '0'; + nlOil1OiO <= '0'; + nlOil1Ol <= '0'; + nlOil1Oli <= '0'; + nlOil1Oll <= '0'; + nlOil1OlO <= '0'; + nlOil1OO <= '0'; + nlOil1OOi <= '0'; + nlOil1OOl <= '0'; + nlOil1OOO <= '0'; + nlOili0i <= '0'; + nlOili0l <= '0'; + nlOili0O <= '0'; + nlOili10l <= '0'; + nlOili1i <= '0'; + nlOili1l <= '0'; + nlOili1li <= '0'; + nlOili1lO <= '0'; + nlOili1O <= '0'; + nlOiliii <= '0'; + nlOiliiil <= '0'; + nlOiliiiO <= '0'; + nlOiliili <= '0'; + nlOiliill <= '0'; + nlOiliilO <= '0'; + nlOiliiOi <= '0'; + nlOiliiOl <= '0'; + nlOiliiOO <= '0'; + nlOilO00i <= '0'; + nlOilO0iO <= '0'; + nlOilO0ll <= '0'; + nlOilOiOi <= '0'; + nlOilOl0l <= '0'; + nlOilOl1O <= '0'; + nlOilOOii <= '0'; + nlOilOOlO <= '0'; + nlOilOOOl <= '0'; + nlOl1i01l <= '0'; + nlOl1li0i <= '0'; + nlOl1li0l <= '0'; + ELSIF (core_clk = '1' AND core_clk'event) THEN + n1illl1i <= wire_n1illOli_dataout; + n1illOil <= wire_n1ilO01i_dataout; + n1l000i <= wire_n1l0iOi_dataout; + n1l000l <= wire_n1l0iOl_dataout; + n1l000O <= wire_n1l0iOO_dataout; + n1l001i <= wire_n1l0ili_dataout; + n1l001l <= wire_n1l0ill_dataout; + n1l001O <= wire_n1l0ilO_dataout; + n1l00ii <= wire_n1l0l1i_dataout; + n1l010i <= wire_n1l00Oi_dataout; + n1l010l <= wire_n1l00Ol_dataout; + n1l010O <= wire_n1l00OO_dataout; + n1l011i <= wire_n1l00li_dataout; + n1l011l <= wire_n1l00ll_dataout; + n1l01ii <= wire_n1l0i1i_dataout; + n1l01il <= wire_n1l0i1l_dataout; + n1l01iO <= wire_n1l0i1O_dataout; + n1l01li <= wire_n1l0i0i_dataout; + n1l01ll <= wire_n1l0i0l_dataout; + n1l01lO <= wire_n1l0i0O_dataout; + n1l01Oi <= wire_n1l0iii_dataout; + n1l01Ol <= wire_n1l0iil_dataout; + n1l01OO <= wire_n1l0iiO_dataout; + ni0000i <= wire_ni00l0i_dataout; + ni0000l <= wire_ni00l0l_dataout; + ni0000O <= wire_ni00l0O_dataout; + ni0001i <= wire_ni00l1i_dataout; + ni0001l <= wire_ni00l1l_dataout; + ni0001O <= wire_ni00l1O_dataout; + ni000ii <= wire_ni00lii_dataout; + ni000il <= wire_ni00lil_dataout; + ni000iO <= wire_ni00liO_dataout; + ni000li <= wire_ni00lli_dataout; + ni000ll <= wire_ni00lll_dataout; + ni000lO <= wire_ni00llO_dataout; + ni000Oi <= wire_ni00lOi_dataout; + ni000Ol <= wire_ni00lOl_dataout; + ni000OO <= wire_ni00lOO_dataout; + ni001Ol <= wire_ni00iOl_dataout; + ni001OO <= wire_ni00iOO_dataout; + ni00i0i <= wire_ni00O0i_dataout; + ni00i0l <= wire_ni00O0l_dataout; + ni00i0O <= wire_ni00O0O_dataout; + ni00i1i <= wire_ni00O1i_dataout; + ni00i1l <= wire_ni00O1l_dataout; + ni00i1O <= wire_ni00O1O_dataout; + ni00iii <= wire_ni00Oii_dataout; + ni00iil <= wire_ni00Oil_dataout; + ni00iiO <= wire_ni00OiO_dataout; + ni00ili <= wire_ni00Oli_dataout; + ni00ill <= wire_ni00Oll_dataout; + ni00ilO <= wire_ni0l0iO_dataout; + ni0i0OO <= wire_ni00iOi_dataout; + ni0l00i <= wire_ni0l0li_dataout; + ni0l00l <= wire_ni0l0ll_dataout; + ni0l00O <= wire_ni0l0lO_dataout; + ni0l0ii <= wire_ni0l0Oi_dataout; + ni0l0il <= wire_ni0li1O_dataout; + ni0liOi <= wire_ni0lO1O_dataout; + ni0llil <= wire_ni0lO0i_dataout; + ni0lliO <= wire_ni0lO0l_dataout; + ni0llli <= wire_ni0lO0O_dataout; + ni0llll <= wire_ni0lOii_dataout; + ni0lllO <= wire_ni0lOil_dataout; + ni0llOi <= wire_ni0lOiO_dataout; + ni0llOl <= wire_ni0lOli_dataout; + ni0llOO <= wire_ni0lOll_dataout; + ni0lO1i <= wire_ni0lOlO_dataout; + ni0lO1l <= wire_ni0O1ll_dataout; + ni0O1iO <= wire_ni0O1lO_dataout; + ni0Ol0O <= wire_niil11i_dataout; + nii000i <= wire_niill1i_dataout; + nii000l <= wire_niill1l_dataout; + nii000O <= wire_niill1O_dataout; + nii001i <= wire_niiliOi_dataout; + nii001l <= wire_niiliOl_dataout; + nii001O <= wire_niiliOO_dataout; + nii00ii <= wire_niill0i_dataout; + nii00il <= wire_niill0l_dataout; + nii00iO <= wire_niill0O_dataout; + nii00li <= wire_niillii_dataout; + nii00ll <= wire_niillil_dataout; + nii00lO <= wire_niilliO_dataout; + nii00Oi <= wire_niillli_dataout; + nii00Ol <= wire_niillll_dataout; + nii00OO <= wire_niilllO_dataout; + nii010i <= wire_niili1i_dataout; + nii010l <= wire_niili1l_dataout; + nii010O <= wire_niili1O_dataout; + nii011i <= wire_niil0Oi_dataout; + nii011l <= wire_niil0Ol_dataout; + nii011O <= wire_niil0OO_dataout; + nii01ii <= wire_niili0i_dataout; + nii01il <= wire_niili0l_dataout; + nii01iO <= wire_niili0O_dataout; + nii01li <= wire_niiliii_dataout; + nii01ll <= wire_niiliil_dataout; + nii01lO <= wire_niiliiO_dataout; + nii01Oi <= wire_niilili_dataout; + nii01Ol <= wire_niilill_dataout; + nii01OO <= wire_niililO_dataout; + nii0i0i <= wire_niilO1i_dataout; + nii0i0l <= wire_niilO1l_dataout; + nii0i0O <= wire_niilO1O_dataout; + nii0i1i <= wire_niillOi_dataout; + nii0i1l <= wire_niillOl_dataout; + nii0i1O <= wire_niillOO_dataout; + nii0iii <= wire_niilO0i_dataout; + nii0iil <= wire_niilO0l_dataout; + nii0iiO <= wire_niilO0O_dataout; + nii0ili <= wire_niilOii_dataout; + nii0ill <= wire_niilOil_dataout; + nii0ilO <= wire_niilOiO_dataout; + nii0iOi <= wire_niilOli_dataout; + nii0iOl <= wire_niilOll_dataout; + nii0iOO <= wire_niilOlO_dataout; + nii0l0i <= wire_niiO11i_dataout; + nii0l0l <= wire_niiO11l_dataout; + nii0l0O <= wire_niiO11O_dataout; + nii0l1i <= wire_niilOOi_dataout; + nii0l1l <= wire_niilOOl_dataout; + nii0l1O <= wire_niilOOO_dataout; + nii0lii <= wire_niiO10i_dataout; + nii0lil <= wire_niiO10l_dataout; + nii0liO <= wire_niiO10O_dataout; + nii0lli <= wire_niiO1ii_dataout; + nii0lll <= wire_niiO1il_dataout; + nii0llO <= wire_niiO1iO_dataout; + nii0lOi <= wire_niiO1li_dataout; + nii0lOl <= wire_niiO1ll_dataout; + nii0lOO <= wire_niiO1lO_dataout; + nii0O0i <= wire_niiO01i_dataout; + nii0O0l <= wire_niiO01l_dataout; + nii0O0O <= wire_niiO01O_dataout; + nii0O1i <= wire_niiO1Oi_dataout; + nii0O1l <= wire_niiO1Ol_dataout; + nii0O1O <= wire_niiO1OO_dataout; + nii0Oii <= wire_niiO00i_dataout; + nii0Oil <= wire_niiO00l_dataout; + nii0OiO <= wire_niiO00O_dataout; + nii0Oli <= wire_niiO0ii_dataout; + nii0Oll <= wire_niiO0il_dataout; + nii0OlO <= wire_niiO0iO_dataout; + nii0OOi <= wire_niiO0li_dataout; + nii0OOl <= wire_niiO0ll_dataout; + nii0OOO <= wire_niiO0lO_dataout; + nii1l0l <= wire_niil11l_dataout; + nii1l0O <= wire_niil11O_dataout; + nii1lii <= wire_niil10i_dataout; + nii1lil <= wire_niil10l_dataout; + nii1liO <= wire_niil10O_dataout; + nii1lli <= wire_niil1ii_dataout; + nii1lll <= wire_niil1il_dataout; + nii1llO <= wire_niil1iO_dataout; + nii1lOi <= wire_niil1li_dataout; + nii1lOl <= wire_niil1ll_dataout; + nii1lOO <= wire_niil1lO_dataout; + nii1O0i <= wire_niil01i_dataout; + nii1O0l <= wire_niil01l_dataout; + nii1O0O <= wire_niil01O_dataout; + nii1O1i <= wire_niil1Oi_dataout; + nii1O1l <= wire_niil1Ol_dataout; + nii1O1O <= wire_niil1OO_dataout; + nii1Oii <= wire_niil00i_dataout; + nii1Oil <= wire_niil00l_dataout; + nii1OiO <= wire_niil00O_dataout; + nii1Oli <= wire_niil0ii_dataout; + nii1Oll <= wire_niil0il_dataout; + nii1OlO <= wire_niil0iO_dataout; + nii1OOi <= wire_niil0li_dataout; + nii1OOl <= wire_niil0ll_dataout; + nii1OOO <= wire_niil0lO_dataout; + niii00i <= wire_niiOl1i_dataout; + niii00l <= wire_niiOl1l_dataout; + niii00O <= wire_niiOl1O_dataout; + niii01i <= wire_niiOiOi_dataout; + niii01l <= wire_niiOiOl_dataout; + niii01O <= wire_niiOiOO_dataout; + niii0ii <= wire_niiOl0i_dataout; + niii0il <= wire_niiOl0l_dataout; + niii0iO <= wire_niiOl0O_dataout; + niii0li <= wire_niiOlii_dataout; + niii0ll <= wire_niiOlil_dataout; + niii0lO <= wire_niiOliO_dataout; + niii0Oi <= wire_niiOlli_dataout; + niii0Ol <= wire_niiOlll_dataout; + niii0OO <= wire_niiOllO_dataout; + niii10i <= wire_niiOi1i_dataout; + niii10l <= wire_niiOi1l_dataout; + niii10O <= wire_niiOi1O_dataout; + niii11i <= wire_niiO0Oi_dataout; + niii11l <= wire_niiO0Ol_dataout; + niii11O <= wire_niiO0OO_dataout; + niii1ii <= wire_niiOi0i_dataout; + niii1il <= wire_niiOi0l_dataout; + niii1iO <= wire_niiOi0O_dataout; + niii1li <= wire_niiOiii_dataout; + niii1ll <= wire_niiOiil_dataout; + niii1lO <= wire_niiOiiO_dataout; + niii1Oi <= wire_niiOili_dataout; + niii1Ol <= wire_niiOill_dataout; + niii1OO <= wire_niiOilO_dataout; + niiii0i <= wire_niiOO1i_dataout; + niiii0l <= wire_niiOO1l_dataout; + niiii0O <= wire_niiOO1O_dataout; + niiii1i <= wire_niiOlOi_dataout; + niiii1l <= wire_niiOlOl_dataout; + niiii1O <= wire_niiOlOO_dataout; + niiiiii <= wire_niiOO0i_dataout; + niiiiil <= wire_niiOO0l_dataout; + niiiiiO <= wire_niiOO0O_dataout; + niiiili <= wire_niiOOii_dataout; + niiiill <= wire_niiOOil_dataout; + niiiilO <= wire_niiOOiO_dataout; + niiiiOi <= wire_niiOOli_dataout; + niiiiOl <= wire_niiOOll_dataout; + niiiiOO <= wire_niiOOlO_dataout; + niiil0i <= wire_nil111i_dataout; + niiil0l <= wire_nil111l_dataout; + niiil0O <= wire_nil111O_dataout; + niiil1i <= wire_niiOOOi_dataout; + niiil1l <= wire_niiOOOl_dataout; + niiil1O <= wire_niiOOOO_dataout; + niiilii <= wire_nil110i_dataout; + niiilil <= wire_nil110l_dataout; + niiiliO <= wire_nil110O_dataout; + niiilli <= wire_nil11ii_dataout; + niiilll <= wire_nil11il_dataout; + niiillO <= wire_nil11iO_dataout; + niiilOi <= wire_nil11li_dataout; + niiilOl <= wire_nil11ll_dataout; + niiilOO <= wire_nil11lO_dataout; + niiiO0i <= wire_nil101i_dataout; + niiiO0l <= wire_nil101l_dataout; + niiiO0O <= wire_nil101O_dataout; + niiiO1i <= wire_nil11Oi_dataout; + niiiO1l <= wire_nil11Ol_dataout; + niiiO1O <= wire_nil11OO_dataout; + niiiOii <= wire_nil100i_dataout; + niiiOil <= wire_nil100l_dataout; + niiiOiO <= wire_nil100O_dataout; + niiiOli <= wire_nil10ii_dataout; + niiiOll <= wire_nil10il_dataout; + niiiOlO <= wire_nil10iO_dataout; + niiiOOi <= wire_nil10li_dataout; + niiiOOl <= wire_nil10ll_dataout; + niiiOOO <= wire_niOiOil_dataout; + niO0000i <= wire_niO00OOl_dataout; + niO0000l <= wire_niO00OOO_dataout; + niO0000O <= wire_niO0i11i_dataout; + niO0001i <= wire_niO00Oll_dataout; + niO0001l <= wire_niO00OlO_dataout; + niO0001O <= wire_niO00OOi_dataout; + niO000ii <= wire_niO0i11l_dataout; + niO000il <= wire_niO0i11O_dataout; + niO000iO <= wire_niO0i10i_dataout; + niO000li <= wire_niO0i10l_dataout; + niO000ll <= wire_niO0i10O_dataout; + niO000lO <= wire_niO0i1ii_dataout; + niO000Oi <= wire_niO0i1il_dataout; + niO000Ol <= wire_niO0i1iO_dataout; + niO000OO <= wire_niO0i1li_dataout; + niO001Oi <= wire_niO00Oil_dataout; + niO001Ol <= wire_niO00OiO_dataout; + niO001OO <= wire_niO00Oli_dataout; + niO00i0i <= wire_niO0i1Ol_dataout; + niO00i0l <= wire_niO0i1OO_dataout; + niO00i0O <= wire_niO0i01i_dataout; + niO00i1i <= wire_niO0i1ll_dataout; + niO00i1l <= wire_niO0i1lO_dataout; + niO00i1O <= wire_niO0i1Oi_dataout; + niO00iii <= wire_niO0i01l_dataout; + niO00iil <= wire_niO0i01O_dataout; + niO00iiO <= wire_niO0i00i_dataout; + niO00ili <= wire_niO0i00l_dataout; + niO00ill <= wire_niO0i00O_dataout; + niO00ilO <= wire_niO0i0ii_dataout; + niO00iOi <= wire_niO0i0il_dataout; + niO00iOl <= wire_niO0i0iO_dataout; + niO00iOO <= wire_niO0i0li_dataout; + niO00l0i <= wire_niO0i0Ol_dataout; + niO00l0l <= wire_niO0i0OO_dataout; + niO00l0O <= wire_niO0ii1i_dataout; + niO00l1i <= wire_niO0i0ll_dataout; + niO00l1l <= wire_niO0i0lO_dataout; + niO00l1O <= wire_niO0i0Oi_dataout; + niO00lii <= wire_niO0ii1l_dataout; + niO00lil <= wire_niO0ii1O_dataout; + niO00liO <= wire_niO0ii0i_dataout; + niO00lli <= wire_niO0ii0l_dataout; + niO00lll <= wire_niO0ii0O_dataout; + niO00llO <= wire_niO0iiii_dataout; + niO00lOi <= wire_niO0iiil_dataout; + niO00lOl <= wire_niO0iiiO_dataout; + niO00lOO <= wire_niO0iili_dataout; + niO00O0i <= wire_niO0iiOl_dataout; + niO00O0l <= wire_niO0iiOO_dataout; + niO00O0O <= wire_niO0l0Ol_dataout; + niO00O1i <= wire_niO0iill_dataout; + niO00O1l <= wire_niO0iilO_dataout; + niO00O1O <= wire_niO0iiOi_dataout; + niO0l0li <= wire_niO00Oii_dataout; + niO0l0ll <= wire_niO0l0OO_dataout; + niO0l0lO <= wire_niO0li1i_dataout; + niO0l0Oi <= wire_niO0li1l_dataout; + niO0liil <= wire_niO0O11i_dataout; + niO0liiO <= wire_niO0O11l_dataout; + niO0lili <= wire_niO0O11O_dataout; + niO0lill <= wire_niO0O10i_dataout; + niO0lilO <= wire_niO0O10l_dataout; + niO0liOi <= wire_niO0O10O_dataout; + niO0liOl <= wire_niO0O1ii_dataout; + niO0liOO <= wire_niO0O1il_dataout; + niO0ll0i <= wire_niO0O1lO_dataout; + niO0ll0l <= wire_niO0O1Oi_dataout; + niO0ll0O <= wire_niO0O1Ol_dataout; + niO0ll1i <= wire_niO0O1iO_dataout; + niO0ll1l <= wire_niO0O1li_dataout; + niO0ll1O <= wire_niO0O1ll_dataout; + niO0llii <= wire_niO0O1OO_dataout; + niO0llil <= wire_niO0O01i_dataout; + niO0lliO <= wire_niO0O01l_dataout; + niO0llli <= wire_niO0O01O_dataout; + niO0llll <= wire_niO0O00i_dataout; + niO0lllO <= wire_niO0O00l_dataout; + niO0llOi <= wire_niO0O00O_dataout; + niO0llOl <= wire_niO0O0ii_dataout; + niO0llOO <= wire_niO0O0il_dataout; + niO0lO0i <= wire_niO0O0lO_dataout; + niO0lO0l <= wire_niO0O0Oi_dataout; + niO0lO0O <= wire_niO0O0Ol_dataout; + niO0lO1i <= wire_niO0O0iO_dataout; + niO0lO1l <= wire_niO0O0li_dataout; + niO0lO1O <= wire_niO0O0ll_dataout; + niO0lOii <= wire_niO0O0OO_dataout; + niO0lOil <= wire_niO0Oi1i_dataout; + niO0lOiO <= wire_niO0Oi1l_dataout; + niO0lOli <= wire_niO0Oi1O_dataout; + niO0lOll <= wire_niO0Oi0i_dataout; + niO0lOlO <= wire_niO0Oi0l_dataout; + niO0lOOi <= wire_niO0Oi0O_dataout; + niO0lOOl <= wire_niOi111O_dataout; + niO0OOOl <= wire_niO0lOOO_dataout; + niO0OOOO <= wire_niOi110i_dataout; + niOi000i <= wire_niOi0O0O_dataout; + niOi000l <= wire_niOi0Oii_dataout; + niOi000O <= wire_niOi0Oil_dataout; + niOi001i <= wire_niOi0O1O_dataout; + niOi001l <= wire_niOi0O0i_dataout; + niOi001O <= wire_niOi0O0l_dataout; + niOi00i <= wire_niOiOll_dataout; + niOi00ii <= wire_niOi0OiO_dataout; + niOi00il <= wire_niOi0Oli_dataout; + niOi00iO <= wire_niOi0Oll_dataout; + niOi00l <= wire_niOiOlO_dataout; + niOi00li <= wire_niOi0OlO_dataout; + niOi00ll <= wire_niOi0OOi_dataout; + niOi00lO <= wire_niOi0OOl_dataout; + niOi00O <= wire_niOiOOi_dataout; + niOi00Oi <= wire_niOi0OOO_dataout; + niOi010i <= wire_niOi0l0O_dataout; + niOi010l <= wire_niOi0lii_dataout; + niOi010O <= wire_niOi0lil_dataout; + niOi011i <= wire_niOi0l1O_dataout; + niOi011l <= wire_niOi0l0i_dataout; + niOi011O <= wire_niOi0l0l_dataout; + niOi01ii <= wire_niOi0liO_dataout; + niOi01il <= wire_niOi0lli_dataout; + niOi01iO <= wire_niOi0lll_dataout; + niOi01l <= wire_niOiOiO_dataout; + niOi01li <= wire_niOi0llO_dataout; + niOi01ll <= wire_niOi0lOi_dataout; + niOi01lO <= wire_niOi0lOl_dataout; + niOi01O <= wire_niOiOli_dataout; + niOi01Oi <= wire_niOi0lOO_dataout; + niOi01Ol <= wire_niOi0O1i_dataout; + niOi01OO <= wire_niOi0O1l_dataout; + niOi0ii <= wire_niOiOOl_dataout; + niOi0il <= wire_niOiOOO_dataout; + niOi0iO <= wire_niOl11i_dataout; + niOi0li <= wire_niOl11l_dataout; + niOi0ll <= wire_niOl11O_dataout; + niOi0lO <= wire_niOl10i_dataout; + niOi0Oi <= wire_niOl10l_dataout; + niOi0Ol <= wire_niOl10O_dataout; + niOi0OO <= wire_niOl1ii_dataout; + niOi111i <= wire_niOi110l_dataout; + niOi111l <= wire_niOi110O_dataout; + niOi1lOl <= wire_niOi0i1i_dataout; + niOi1lOO <= wire_niOi0i1l_dataout; + niOi1O0i <= wire_niOi0i0O_dataout; + niOi1O0l <= wire_niOi0iii_dataout; + niOi1O0O <= wire_niOi0iil_dataout; + niOi1O1i <= wire_niOi0i1O_dataout; + niOi1O1l <= wire_niOi0i0i_dataout; + niOi1O1O <= wire_niOi0i0l_dataout; + niOi1Oii <= wire_niOi0iiO_dataout; + niOi1Oil <= wire_niOi0ili_dataout; + niOi1OiO <= wire_niOi0ill_dataout; + niOi1Oli <= wire_niOi0ilO_dataout; + niOi1Oll <= wire_niOi0iOi_dataout; + niOi1OlO <= wire_niOi0iOl_dataout; + niOi1OOi <= wire_niOi0iOO_dataout; + niOi1OOl <= wire_niOi0l1i_dataout; + niOi1OOO <= wire_niOi0l1l_dataout; + niOii0i <= wire_niOl1ll_dataout; + niOii0l <= wire_niOl1lO_dataout; + niOii0O <= wire_niOl1Oi_dataout; + niOii1i <= wire_niOl1il_dataout; + niOii1l <= wire_niOl1iO_dataout; + niOii1O <= wire_niOl1li_dataout; + niOiiii <= wire_niOl1Ol_dataout; + niOiiil <= wire_niOl1OO_dataout; + niOiiiO <= wire_niOl01i_dataout; + niOiil1O <= wire_niOi00OO_dataout; + niOiili <= wire_niOl01l_dataout; + niOiilil <= wire_niOiillO_dataout; + niOiill <= wire_niOl01O_dataout; + niOiilli <= wire_niOiilOi_dataout; + niOiilO <= wire_niOl00i_dataout; + niOiiOi <= wire_niOl00l_dataout; + niOiiOl <= wire_niOl00O_dataout; + niOiiOO <= wire_niOl0ii_dataout; + niOil0i <= wire_niOl0ll_dataout; + niOil0l <= wire_niOl0lO_dataout; + niOil0O <= wire_niOl0Oi_dataout; + niOil1i <= wire_niOl0il_dataout; + niOil1l <= wire_niOl0iO_dataout; + niOil1O <= wire_niOl0li_dataout; + niOilii <= wire_niOl0Ol_dataout; + niOilil <= wire_niOl0OO_dataout; + niOiliO <= wire_niOli1i_dataout; + niOilli <= wire_niOli1l_dataout; + niOilll <= wire_niOli1O_dataout; + niOillO <= wire_niOli0i_dataout; + niOilOi <= wire_niOli0l_dataout; + niOilOl <= wire_niOli0O_dataout; + niOilOO <= wire_niOliii_dataout; + niOiO0i <= wire_niOlill_dataout; + niOiO0l <= wire_niOlilO_dataout; + niOiO0O <= wire_niOliOi_dataout; + niOiO1i <= wire_niOliil_dataout; + niOiO1l <= wire_niOliiO_dataout; + niOiO1O <= wire_niOlili_dataout; + niOlii0l <= wire_niOliOlO_dataout; + niOlii0O <= wire_niOliOOi_dataout; + niOliiii <= wire_niOliOOl_dataout; + niOliiil <= wire_niOliOOO_dataout; + niOliiiO <= wire_niOll11i_dataout; + niOliili <= wire_niOll11l_dataout; + niOliill <= wire_niOll11O_dataout; + niOliilO <= wire_niOll10i_dataout; + niOliiOi <= wire_niOll10l_dataout; + niOliiOl <= wire_niOll10O_dataout; + niOliiOO <= wire_niOll1ii_dataout; + niOlil0i <= wire_niOll1ll_dataout; + niOlil0l <= wire_niOll1lO_dataout; + niOlil0O <= wire_niOll1Oi_dataout; + niOlil1i <= wire_niOll1il_dataout; + niOlil1l <= wire_niOll1iO_dataout; + niOlil1O <= wire_niOll1li_dataout; + niOlilii <= wire_niOll1Ol_dataout; + niOlilil <= wire_niOll1OO_dataout; + niOliliO <= wire_niOll01i_dataout; + niOlilli <= wire_niOll01l_dataout; + niOlilll <= wire_niOll01O_dataout; + niOlillO <= wire_niOll00i_dataout; + niOlilOi <= wire_niOll00l_dataout; + niOlilOl <= wire_niOll00O_dataout; + niOlilOO <= wire_niOll0ii_dataout; + niOliO0i <= wire_niOll0ll_dataout; + niOliO0l <= wire_niOll0lO_dataout; + niOliO0O <= wire_niOll0Oi_dataout; + niOliO1i <= wire_niOll0il_dataout; + niOliO1l <= wire_niOll0iO_dataout; + niOliO1O <= wire_niOll0li_dataout; + niOliOii <= wire_niOll0Ol_dataout; + niOliOil <= wire_niOll0OO_dataout; + niOliOiO <= wire_niOlli1i_dataout; + niOliOli <= wire_niOlli1l_dataout; + niOlOi0O <= wire_niOliOll_dataout; + niOlOill <= wire_niOlOiil_dataout; + niOlOl1i <= wire_niOlOl0l_dataout; + niOlOl1O <= wire_niOlOl0O_dataout; + niOlOO1O <= wire_niOlOO1i_dataout; + niOlOOil <= wire_niOlOOlO_dataout; + niOlOOli <= wire_niOlOOOi_dataout; + niOO000O <= wire_niOO00li_dataout; + niOO001i <= wire_niOO01iO_dataout; + niOO00il <= wire_niOO00ll_dataout; + niOO010O <= wire_niOO01li_dataout; + niOO01ii <= wire_niOO01ll_dataout; + niOO0ili <= niOO0ilO; + niOO0l1l <= wire_niOO0l0l_dataout; + niOO0liO <= wire_niOO0lOi_dataout; + niOO0llO <= wire_niOO0lOl_dataout; + niOO0Oli <= wire_niOO0OOi_dataout; + niOO101i <= wire_niOO100l_dataout; + niOO101O <= wire_niOO100O_dataout; + niOO11ll <= wire_niOO11iO_dataout; + niOO1i0i <= wire_niOO1i1l_dataout; + niOO1iiO <= wire_niOO1iOi_dataout; + niOO1ill <= wire_niOO1iOl_dataout; + niOO1llO <= wire_niOO1lli_dataout; + niOO1O0i <= wire_niOO1Oii_dataout; + niOO1O1l <= wire_niOO1O0O_dataout; + niOOi01il <= wire_niOOi1l1O_dataout; + niOOi01O <= wire_niOOi00O_dataout; + niOOi01Oi <= wire_niOOi001l_dataout; + niOOi01OO <= wire_niOOi001O_dataout; + niOOi0li <= wire_niOOi0Ol_dataout; + niOOi0Oi <= wire_niOOi0OO_dataout; + niOOi10l <= wire_niOOi1ii_dataout; + niOOi11l <= wire_niOOi10O_dataout; + niOOi1i0i <= wire_niOOi1lii_dataout; + niOOi1i0l <= wire_niOOi1lil_dataout; + niOOi1i0O <= wire_niOOi1liO_dataout; + niOOi1i1i <= wire_niOOi1l0i_dataout; + niOOi1i1l <= wire_niOOi1l0l_dataout; + niOOi1i1O <= wire_niOOi1l0O_dataout; + niOOi1iii <= wire_niOOi1lli_dataout; + niOOi1iil <= wire_niOOi1lll_dataout; + niOOi1iiO <= wire_niOOi1llO_dataout; + niOOi1ili <= wire_niOOi1lOi_dataout; + niOOi1ill <= wire_niOOi1lOl_dataout; + niOOi1ilO <= wire_niOOi1lOO_dataout; + niOOi1iOi <= wire_niOOi1O1i_dataout; + niOOi1iOl <= wire_niOOi1O1l_dataout; + niOOi1iOO <= wire_niOOi1O1O_dataout; + niOOi1l1i <= wire_niOOi1O0i_dataout; + niOOil0i <= wire_niOOiO1i_dataout; + niOOil0l <= wire_niOOiO1l_dataout; + niOOil0O <= wire_niOOiO1O_dataout; + niOOilii <= wire_niOOiO0i_dataout; + niOOilil <= wire_niOOiO0l_dataout; + niOOiliO <= wire_niOOiO0O_dataout; + niOOilli <= wire_niOOiOii_dataout; + niOOilll <= wire_niOOiOil_dataout; + niOOillO <= wire_niOOiOiO_dataout; + niOOilOi <= wire_niOOiOli_dataout; + niOOl1il <= wire_niOOilOO_dataout; + niOOl1Oi <= wire_niOOl01l_dataout; + niOOl1OO <= wire_niOOl01O_dataout; + niOOllOO <= wire_niOOlllO_dataout; + niOOlO0l <= wire_niOOlOiO_dataout; + niOOlOii <= wire_niOOlOli_dataout; + niOOO01O <= wire_niOOO00l_dataout; + niOOO1il <= wire_niOOO1ll_dataout; + niOOO1OO <= wire_niOOO00i_dataout; + niOOOi0O <= wire_niOOOili_dataout; + niOOOi1i <= wire_niOOO0Oi_dataout; + niOOOiil <= wire_niOOOill_dataout; + niOOOil <= wire_nl1000O_dataout; + niOOOl0l <= niOOOlii; + niOOOlil <= niOOOlli; + niOOOlll <= niOOOlOi; + niOOOlOl <= niOOOO1i; + niOOOO1l <= niOOOO0i; + niOOOOiO <= wire_niOOOO0O_dataout; + niOOOOOl <= wire_nl11111O_dataout; + nl0000iO <= wire_nl000O1l_dataout; + nl0000li <= wire_nl000O1O_dataout; + nl0000ll <= wire_nl000O0i_dataout; + nl0000lO <= wire_nl000O0l_dataout; + nl0000Oi <= wire_nl000O0O_dataout; + nl0000Ol <= wire_nl000Oii_dataout; + nl0000OO <= wire_nl000Oil_dataout; + nl000i0i <= wire_nl000OlO_dataout; + nl000i0l <= wire_nl000OOi_dataout; + nl000i0O <= wire_nl000OOl_dataout; + nl000i1i <= wire_nl000OiO_dataout; + nl000i1l <= wire_nl000Oli_dataout; + nl000i1O <= wire_nl000Oll_dataout; + nl000iii <= wire_nl000OOO_dataout; + nl000iil <= wire_nl00i11i_dataout; + nl000iiO <= wire_nl00i11l_dataout; + nl000ili <= wire_nl00i11O_dataout; + nl000ill <= wire_nl00i10i_dataout; + nl000ilO <= wire_nl00i10l_dataout; + nl000iOi <= wire_nl00i10O_dataout; + nl000iOl <= wire_nl00i1ii_dataout; + nl000iOO <= wire_nl00i1il_dataout; + nl000l0i <= wire_nl00i1lO_dataout; + nl000l0l <= wire_nl00i1Oi_dataout; + nl000l0O <= wire_nl00i1Ol_dataout; + nl000l1i <= wire_nl00i1iO_dataout; + nl000l1l <= wire_nl00i1li_dataout; + nl000l1O <= wire_nl00i1ll_dataout; + nl000lii <= wire_nl00i1OO_dataout; + nl000lil <= wire_nl00i01i_dataout; + nl000liO <= wire_nl00i01l_dataout; + nl000lli <= wire_nl00i01O_dataout; + nl000lll <= wire_nl00i00i_dataout; + nl000llO <= wire_nl00i00l_dataout; + nl000lOi <= wire_nl00i00O_dataout; + nl000lOl <= wire_nl00i0ii_dataout; + nl000lOO <= wire_nl00iO1O_dataout; + nl00100i <= wire_nl001llO_dataout; + nl00101i <= wire_nl001liO_dataout; + nl00101l <= wire_nl001lli_dataout; + nl00101O <= wire_nl001lll_dataout; + nl00110i <= wire_nl001ilO_dataout; + nl00110l <= wire_nl001iOi_dataout; + nl00110O <= wire_nl001iOl_dataout; + nl00111i <= wire_nl001iiO_dataout; + nl00111l <= wire_nl001ili_dataout; + nl00111O <= wire_nl001ill_dataout; + nl0011ii <= wire_nl001iOO_dataout; + nl0011il <= wire_nl001l1i_dataout; + nl0011iO <= wire_nl001l1l_dataout; + nl0011li <= wire_nl001l1O_dataout; + nl0011ll <= wire_nl001l0i_dataout; + nl0011lO <= wire_nl001l0l_dataout; + nl0011Oi <= wire_nl001l0O_dataout; + nl0011Ol <= wire_nl001lii_dataout; + nl0011OO <= wire_nl001lil_dataout; + nl00ilOO <= wire_nl000O1i_dataout; + nl00iO1i <= wire_nl00iO0i_dataout; + nl00iO1l <= wire_nl00iO0l_dataout; + nl00Ol0i <= wire_nl00Olii_dataout; + nl00Olll <= wire_nl0i100O_dataout; + nl00OlOl <= wire_nl0i10ii_dataout; + nl00OlOO <= wire_nl0i10il_dataout; + nl00OO0i <= wire_nl0i10lO_dataout; + nl00OO0l <= wire_nl0i10Oi_dataout; + nl00OO0O <= wire_nl0i10Ol_dataout; + nl00OO1i <= wire_nl0i10iO_dataout; + nl00OO1l <= wire_nl0i10li_dataout; + nl00OO1O <= wire_nl0i10ll_dataout; + nl00OOii <= wire_nl0i10OO_dataout; + nl00OOil <= wire_nl0i1i1i_dataout; + nl00OOiO <= wire_nl0i1i1l_dataout; + nl00OOli <= wire_nl0i1i1O_dataout; + nl00OOll <= wire_nl0i1i0i_dataout; + nl00OOlO <= wire_nl0i1i0l_dataout; + nl00OOOi <= wire_nl0i1i0O_dataout; + nl00OOOl <= wire_nl0i1iii_dataout; + nl00OOOO <= wire_nl0i1iil_dataout; + nl010OOO <= wire_nl01i11O_dataout; + nl011l0l <= wire_nl1OOOli_dataout; + nl011lli <= wire_nl011lOl_dataout; + nl011llO <= wire_nl011lOO_dataout; + nl01i0il <= wire_nl01i0ll_dataout; + nl01i0OO <= wire_nl01ii0i_dataout; + nl01i1ii <= wire_nl01i1ll_dataout; + nl01i1li <= wire_nl01i1lO_dataout; + nl01ii1O <= wire_nl01ii0l_dataout; + nl01il1O <= wire_nl01ilOl_dataout; + nl01illO <= wire_nl01ilOO_dataout; + nl01ilOi <= wire_nl01iO1i_dataout; + nl01Ol1O <= wire_nl01Ol0O_dataout; + nl01Olli <= wire_nl00100l_dataout; + nl01OlOi <= wire_nl00100O_dataout; + nl01OlOl <= wire_nl0010ii_dataout; + nl01OlOO <= wire_nl0010il_dataout; + nl01OO0i <= wire_nl0010lO_dataout; + nl01OO0l <= wire_nl0010Oi_dataout; + nl01OO0O <= wire_nl0010Ol_dataout; + nl01OO1i <= wire_nl0010iO_dataout; + nl01OO1l <= wire_nl0010li_dataout; + nl01OO1O <= wire_nl0010ll_dataout; + nl01OOii <= wire_nl0010OO_dataout; + nl01OOil <= wire_nl001i1i_dataout; + nl01OOiO <= wire_nl001i1l_dataout; + nl01OOli <= wire_nl001i1O_dataout; + nl01OOll <= wire_nl001i0i_dataout; + nl01OOlO <= wire_nl001i0l_dataout; + nl01OOOi <= wire_nl001i0O_dataout; + nl01OOOl <= wire_nl001iii_dataout; + nl01OOOO <= wire_nl001iil_dataout; + nl0i00li <= wire_nl0i0O1O_dataout; + nl0i00ll <= wire_nl0i0O0i_dataout; + nl0i00lO <= wire_nl0i0O0l_dataout; + nl0i00Oi <= wire_nl0i0O0O_dataout; + nl0i00Ol <= wire_nl0i0Oii_dataout; + nl0i00OO <= wire_nl0i0Oil_dataout; + nl0i0i0i <= wire_nl0i0OlO_dataout; + nl0i0i0l <= wire_nl0i0OOi_dataout; + nl0i0i0O <= wire_nl0i0OOl_dataout; + nl0i0i1i <= wire_nl0i0OiO_dataout; + nl0i0i1l <= wire_nl0i0Oli_dataout; + nl0i0i1O <= wire_nl0i0Oll_dataout; + nl0i0iii <= wire_nl0i0OOO_dataout; + nl0i0iil <= wire_nl0ii11i_dataout; + nl0i0iiO <= wire_nl0ii11l_dataout; + nl0i0ili <= wire_nl0ii11O_dataout; + nl0i0ill <= wire_nl0ii10i_dataout; + nl0i0ilO <= wire_nl0ii10l_dataout; + nl0i0iOi <= wire_nl0ii10O_dataout; + nl0i0iOl <= wire_nl0ii1ii_dataout; + nl0i0iOO <= wire_nl0ii1il_dataout; + nl0i0l0i <= wire_nl0ii1lO_dataout; + nl0i0l0l <= wire_nl0ii1Oi_dataout; + nl0i0l0O <= wire_nl0ii1Ol_dataout; + nl0i0l1i <= wire_nl0ii1iO_dataout; + nl0i0l1l <= wire_nl0ii1li_dataout; + nl0i0l1O <= wire_nl0ii1ll_dataout; + nl0i0lii <= wire_nl0ii1OO_dataout; + nl0i0lil <= wire_nl0ii01i_dataout; + nl0i0liO <= wire_nl0ii01l_dataout; + nl0i0lli <= wire_nl0ii01O_dataout; + nl0i0lll <= wire_nl0ii00i_dataout; + nl0i0llO <= wire_nl0ii00l_dataout; + nl0i0lOi <= wire_nl0ii00O_dataout; + nl0i0lOl <= wire_nl0ii0ii_dataout; + nl0i0lOO <= wire_nl0ii0il_dataout; + nl0i0O1i <= wire_nl0iiO0i_dataout; + nl0i100i <= wire_nl0i1llO_dataout; + nl0i100l <= wire_nl0i1lOi_dataout; + nl0i101i <= wire_nl0i1liO_dataout; + nl0i101l <= wire_nl0i1lli_dataout; + nl0i101O <= wire_nl0i1lll_dataout; + nl0i110i <= wire_nl0i1ilO_dataout; + nl0i110l <= wire_nl0i1iOi_dataout; + nl0i110O <= wire_nl0i1iOl_dataout; + nl0i111i <= wire_nl0i1iiO_dataout; + nl0i111l <= wire_nl0i1ili_dataout; + nl0i111O <= wire_nl0i1ill_dataout; + nl0i11ii <= wire_nl0i1iOO_dataout; + nl0i11il <= wire_nl0i1l1i_dataout; + nl0i11iO <= wire_nl0i1l1l_dataout; + nl0i11li <= wire_nl0i1l1O_dataout; + nl0i11ll <= wire_nl0i1l0i_dataout; + nl0i11lO <= wire_nl0i1l0l_dataout; + nl0i11Oi <= wire_nl0i1l0O_dataout; + nl0i11Ol <= wire_nl0i1lii_dataout; + nl0i11OO <= wire_nl0i1lil_dataout; + nl0iiO1i <= wire_nl0i0O1l_dataout; + nl0iiO1l <= wire_nl0iiO0l_dataout; + nl0iiO1O <= wire_nl0iiO0O_dataout; + nl0O1l0O <= wire_nl0OiOii_dataout; + nl0Oiili <= wire_nl0OiOil_dataout; + nl0Oiill <= wire_nl0OiOiO_dataout; + nl0OiilO <= wire_nl0OiOli_dataout; + nl0OiiOi <= wire_nl0OiOll_dataout; + nl0OiiOl <= wire_nl0OiOlO_dataout; + nl0OiiOO <= wire_nl0OiOOi_dataout; + nl0Oil0i <= wire_nl0Ol11l_dataout; + nl0Oil0l <= wire_nl0Ol11O_dataout; + nl0Oil0O <= wire_nl0Ol10i_dataout; + nl0Oil1i <= wire_nl0OiOOl_dataout; + nl0Oil1l <= wire_nl0OiOOO_dataout; + nl0Oil1O <= wire_nl0Ol11i_dataout; + nl0Oilii <= wire_nl0Ol10l_dataout; + nl0Oilil <= wire_nl0Ol10O_dataout; + nl0OiliO <= wire_nl0Ol1ii_dataout; + nl0Oilli <= wire_nl0Ol1il_dataout; + nl0Oilll <= wire_nl0Ol1iO_dataout; + nl0OillO <= wire_nl0Ol1li_dataout; + nl0OilOi <= wire_nl0Ol1ll_dataout; + nl0OilOl <= wire_nl0Ol1lO_dataout; + nl0OilOO <= wire_nl0Ol1Oi_dataout; + nl0OiO0i <= wire_nl0Ol01l_dataout; + nl0OiO0l <= wire_nl0Ol01O_dataout; + nl0OiO0O <= wire_nl0Ol00i_dataout; + nl0OiO1i <= wire_nl0Ol1Ol_dataout; + nl0OiO1l <= wire_nl0Ol1OO_dataout; + nl0OiO1O <= wire_nl0Ol01i_dataout; + nl0OlOii <= wire_nl0OlOli_dataout; + nl0OlOOl <= wire_nl0OO1Ol_dataout; + nl0OO10i <= wire_nl0OO01l_dataout; + nl0OO10l <= wire_nl0OO01O_dataout; + nl0OO10O <= wire_nl0OO00i_dataout; + nl0OO11l <= wire_nl0OO1OO_dataout; + nl0OO11O <= wire_nl0OO01i_dataout; + nl0OO1ii <= wire_nl0OO00l_dataout; + nl0OO1il <= wire_nl0OO00O_dataout; + nl0OO1iO <= wire_nl0OO0ii_dataout; + nl0OO1li <= wire_nl0OO0il_dataout; + nl0OO1ll <= wire_nl0OO0iO_dataout; + nl0OO1lO <= wire_nl0OO0li_dataout; + nl0OO1Oi <= wire_nl0OO0ll_dataout; + nl0OOO0l <= wire_nl0OOOil_dataout; + nl0OOOlO <= wire_nli1110l_dataout; + nl0OOOOO <= wire_nli1110O_dataout; + nl10000l <= wire_nl1000iO_dataout; + nl1000ii <= wire_nl1000li_dataout; + nl1000l <= wire_nl10OOi_dataout; + nl1001i <= wire_nl10Oli_dataout; + nl1001l <= wire_nl10Oll_dataout; + nl1001O <= wire_nl10OlO_dataout; + nl1001OO <= wire_nl101Oll_dataout; + nl100O0i <= wire_nl100Oli_dataout; + nl100O0l <= wire_nl100Oll_dataout; + nl100O0O <= wire_nl100OlO_dataout; + nl100O1O <= wire_nl100OiO_dataout; + nl10101l <= wire_nl10100l_dataout; + nl1010i <= wire_nl10lOi_dataout; + nl1010l <= wire_nl10lOl_dataout; + nl1010O <= wire_nl10lOO_dataout; + nl1011i <= wire_nl10lli_dataout; + nl1011l <= wire_nl10lll_dataout; + nl1011li <= wire_nl1011ii_dataout; + nl1011O <= wire_nl10llO_dataout; + nl1011OO <= wire_nl10100i_dataout; + nl101i1O <= wire_nl101i0O_dataout; + nl101ii <= wire_nl10O1i_dataout; + nl101il <= wire_nl10O1l_dataout; + nl101ili <= wire_nl101iOl_dataout; + nl101iO <= wire_nl10O1O_dataout; + nl101iOi <= wire_nl101iOO_dataout; + nl101li <= wire_nl10O0i_dataout; + nl101ll <= wire_nl10O0l_dataout; + nl101lO <= wire_nl10O0O_dataout; + nl101O0i <= wire_nl101OOl_dataout; + nl101O0l <= wire_nl101OOO_dataout; + nl101O0O <= wire_nl10011i_dataout; + nl101O1l <= wire_nl101OlO_dataout; + nl101O1O <= wire_nl101OOi_dataout; + nl101Oi <= wire_nl10Oii_dataout; + nl101Oii <= wire_nl10011l_dataout; + nl101Oil <= wire_nl10011O_dataout; + nl101OiO <= wire_nl10010i_dataout; + nl101Ol <= wire_nl10Oil_dataout; + nl101OO <= wire_nl10OiO_dataout; + nl10i10i <= wire_nl100Oil_dataout; + nl10i1iO <= wire_nl10i1Oi_dataout; + nl10i1ll <= wire_nl10i1Ol_dataout; + nl10iili <= wire_nl10il1i_dataout; + nl10iill <= wire_nl10il1l_dataout; + nl10iilO <= wire_nl10il1O_dataout; + nl10iiOi <= wire_nl10il0i_dataout; + nl10illl <= wire_nl10iiOO_dataout; + nl10iO1i <= wire_nl10iO0l_dataout; + nl10iO1O <= wire_nl10iO0O_dataout; + nl10l01l <= nl10l00i; + nl10l0Ol <= wire_nl10liil_dataout; + nl10l0OO <= wire_nl10liiO_dataout; + nl10l1ll <= nl10l1Oi; + nl10l1Ol <= nl10l01i; + nl10li0i <= wire_nl10liOi_dataout; + nl10li0l <= wire_nl10liOl_dataout; + nl10li1i <= wire_nl10lili_dataout; + nl10li1l <= wire_nl10lill_dataout; + nl10li1O <= wire_nl10lilO_dataout; + nl10lliO <= wire_nl10liii_dataout; + nl10llOl <= wire_nl10lO1O_dataout; + nl10lO1i <= wire_nl10lO0i_dataout; + nl10O00i <= nlillii0l; + nl10O0ii <= nlillii0O; + nl10O0li <= nlilliiii; + nl10O0Oi <= nlilliiil; + nl10Oi0i <= nlilliili; + nl10Oi1i <= nlilliiiO; + nl10Oiii <= nlilliill; + nl10Oili <= nlilliilO; + nl10OOii <= wire_nl1i11Ol_dataout; + nl10OOil <= wire_nl1i11OO_dataout; + nl10OOiO <= wire_nl1i101i_dataout; + nl10OOli <= wire_nl1i101l_dataout; + nl10OOll <= wire_nl1i101O_dataout; + nl10OOlO <= wire_nl1i100i_dataout; + nl10OOOi <= wire_nl1i100l_dataout; + nl10OOOl <= wire_nl1i100O_dataout; + nl10OOOO <= wire_nl1i10ii_dataout; + nl11001i <= wire_nl11000l_dataout; + nl11001O <= wire_nl11000O_dataout; + nl1101ll <= wire_nl1101il_dataout; + nl110i0i <= wire_nl110i1i_dataout; + nl110iiO <= wire_nl110iOi_dataout; + nl110ill <= wire_nl110iOl_dataout; + nl110llO <= wire_nl110liO_dataout; + nl110O0i <= wire_nl110Oii_dataout; + nl110O1l <= wire_nl110O0O_dataout; + nl11101l <= wire_nl1111Ol_dataout; + nl1110ii <= wire_nl1110ll_dataout; + nl1110iO <= wire_nl1110lO_dataout; + nl11111i <= wire_nl11110i_dataout; + nl111ili <= wire_nl111iii_dataout; + nl111iOO <= wire_nl111l0i_dataout; + nl111l1l <= wire_nl111l0l_dataout; + nl111O0i <= wire_nl111Oii_dataout; + nl111Oll <= wire_nl111OOO_dataout; + nl111OOl <= wire_nl11011i_dataout; + nl11i0Oi <= wire_nl11i0li_dataout; + nl11i10l <= wire_nl11i11l_dataout; + nl11i1li <= wire_nl11i1Ol_dataout; + nl11i1lO <= wire_nl11i1OO_dataout; + nl11ii0l <= wire_nl11iiil_dataout; + nl11ii1O <= wire_nl11iiii_dataout; + nl11il0O <= wire_nl11il1O_dataout; + nl11illl <= wire_nl11ilOO_dataout; + nl11ilO <= wire_nl100ii_dataout; + nl11ilOi <= wire_nl11iO1i_dataout; + nl11iOi <= wire_nl100il_dataout; + nl11iOl <= wire_nl100iO_dataout; + nl11iOO <= wire_nl100li_dataout; + nl11iOOl <= wire_nl11iOll_dataout; + nl11l0i <= wire_nl100Ol_dataout; + nl11l0il <= wire_nl11l0ll_dataout; + nl11l0l <= wire_nl100OO_dataout; + nl11l0O <= wire_nl10i1i_dataout; + nl11l0OO <= wire_nl11li0i_dataout; + nl11l10i <= wire_nl11l1il_dataout; + nl11l10O <= wire_nl11l1iO_dataout; + nl11l1i <= wire_nl100ll_dataout; + nl11l1l <= wire_nl100lO_dataout; + nl11l1O <= wire_nl100Oi_dataout; + nl11li1O <= wire_nl11li0l_dataout; + nl11lii <= wire_nl10i1l_dataout; + nl11lil <= wire_nl10i1O_dataout; + nl11liO <= wire_nl10i0i_dataout; + nl11ll1i <= wire_nl11ll0i_dataout; + nl11lli <= wire_nl10i0l_dataout; + nl11llil <= wire_nl11lllO_dataout; + nl11lll <= wire_nl10i0O_dataout; + nl11llll <= wire_nl11llOi_dataout; + nl11lOiO <= wire_nl11lOlO_dataout; + nl11lOl <= wire_nl10iil_dataout; + nl11lOO <= wire_nl10iiO_dataout; + nl11O01l <= wire_nl11O00l_dataout; + nl11O0i <= wire_nl10iOi_dataout; + nl11O0iO <= wire_nl11O0Oi_dataout; + nl11O0l <= wire_nl10iOl_dataout; + nl11O0lO <= wire_nl11O0Ol_dataout; + nl11O0O <= wire_nl10iOO_dataout; + nl11O10i <= wire_nl11O10O_dataout; + nl11O11i <= wire_nl11O10l_dataout; + nl11O1i <= wire_nl10ili_dataout; + nl11O1l <= wire_nl10ill_dataout; + nl11O1O <= wire_nl10ilO_dataout; + nl11Oii <= wire_nl10l1i_dataout; + nl11Oil <= wire_nl10l1l_dataout; + nl11Oili <= wire_nl11OiOi_dataout; + nl11OiO <= wire_nl10l1O_dataout; + nl11Ol0l <= wire_nl11Olii_dataout; + nl11Ol1l <= wire_nl11Ol0O_dataout; + nl11Oli <= wire_nl10l0i_dataout; + nl11Oll <= wire_nl10l0l_dataout; + nl11OlO <= wire_nl10l0O_dataout; + nl11OO1l <= wire_nl11OO0l_dataout; + nl11OOi <= wire_nl10lii_dataout; + nl11OOiO <= wire_nl11OOOi_dataout; + nl11OOl <= wire_nl10lil_dataout; + nl11OOlO <= wire_nl11OOOl_dataout; + nl11OOO <= wire_nl10liO_dataout; + nl1i0OlO <= wire_nl1ii11i_dataout; + nl1i0OOi <= wire_nl1ii11l_dataout; + nl1i110i <= wire_nl1i10ll_dataout; + nl1i110l <= wire_nl1i10lO_dataout; + nl1i110O <= wire_nl1i10Oi_dataout; + nl1i111i <= wire_nl1i10il_dataout; + nl1i111l <= wire_nl1i10iO_dataout; + nl1i111O <= wire_nl1i10li_dataout; + nl1i11ii <= wire_nl1i10Ol_dataout; + nl1i11il <= wire_nl1i10OO_dataout; + nl1i11iO <= wire_nl1i1i1i_dataout; + nl1i11li <= wire_nl1i1i1l_dataout; + nl1i11ll <= wire_nl1i1i1O_dataout; + nl1i11lO <= wire_nl1i1i0i_dataout; + nl1i1O1i <= wire_nl1i1O0l_dataout; + nl1i1O1O <= wire_nl1i1O0O_dataout; + nl1ii1ii <= wire_nl1i0OOO_dataout; + nl1ii1lO <= wire_nl1ii01i_dataout; + nl1ii1Ol <= wire_nl1ii01l_dataout; + nl1iii0l <= wire_nl1iiiil_dataout; + nl1iiilO <= wire_nl1iil1i_dataout; + nl1iiiOO <= wire_nl1iil1l_dataout; + nl1iilOi <= wire_nl1iiO1i_dataout; + nl1iiO0l <= wire_nl1iiOiO_dataout; + nl1iiOil <= wire_nl1iiOli_dataout; + nl1il00l <= wire_nl1il0li_dataout; + nl1il0il <= wire_nl1il0ll_dataout; + nl1il0iO <= wire_nl1il0lO_dataout; + nl1il1Oi <= wire_nl1il01i_dataout; + nl1ill0i <= wire_nl1ilO1O_dataout; + nl1ill0l <= wire_nl1ilO0i_dataout; + nl1ill0O <= wire_nl1ilO0l_dataout; + nl1ill1l <= wire_nl1ilO1i_dataout; + nl1ill1O <= wire_nl1ilO1l_dataout; + nl1illii <= wire_nl1ilO0O_dataout; + nl1illil <= wire_nl1ilOii_dataout; + nl1illiO <= wire_nl1ilOil_dataout; + nl1illli <= wire_nl1ilOiO_dataout; + nl1illll <= wire_nl1ilOli_dataout; + nl1illlO <= wire_nl1ilOll_dataout; + nl1illOi <= wire_nl1ilOlO_dataout; + nl1iO00i <= wire_nl1iO0ii_dataout; + nl1iO01l <= wire_nl1iO00O_dataout; + nl1iO1lO <= wire_nl1illOO_dataout; + nl1iOOii <= wire_nlOi0i01O_dataout; + nl1iOOli <= wire_nlOi00lii_dataout; + nl1iOOOi <= wire_nlOi00lll_dataout; + nl1l000O <= wire_nl1l00iO_dataout; + nl1l00Oi <= wire_nl1l0i1l_dataout; + nl1l010l <= wire_nl1l01iO_dataout; + nl1l01il <= wire_nl1l01li_dataout; + nl1l0i1i <= wire_nl1l0i1O_dataout; + nl1l0iOl <= wire_nl1l0l1l_dataout; + nl1l0l0O <= wire_nl1l0lli_dataout; + nl1l0liO <= wire_nl1l0lll_dataout; + nl1l0O0i <= nlilOO0iO; + nl1l0O0O <= nl1l0Oil; + nl1l10lO <= wire_nl1l10OO_dataout; + nl1l110i <= wire_nl1l11ii_dataout; + nl1l11ll <= wire_nl1l11OO_dataout; + nl1l11Ol <= wire_nl1l101i_dataout; + nl1l1i0i <= wire_nl1l1iil_dataout; + nl1l1iii <= wire_nl1l1iiO_dataout; + nl1l1l0l <= wire_nl1l1lil_dataout; + nl1l1llO <= wire_nl1l1O1i_dataout; + nl1l1lOO <= wire_nl1l1O1l_dataout; + nl1l1OOi <= wire_nl1l011i_dataout; + nl1li00l <= wire_nl1li0lO_dataout; + nl1li0il <= wire_nl1li0Oi_dataout; + nl1li0iO <= wire_nl1li0Ol_dataout; + nl1li0li <= wire_nl1li0OO_dataout; + nl1li0ll <= wire_nl1lii1i_dataout; + nl1li1Oi <= wire_nl1li01i_dataout; + nl1liili <= wire_nlOii0Oll_dataout; + nl1liO0l <= wire_nl1liOil_dataout; + nl1liOlO <= wire_nl1ll10l_dataout; + nl1liOOO <= wire_nl1ll10O_dataout; + nl1ll00i <= nl1ll00O; + nl1ll0ii <= nl1ll0iO; + nl1ll0ll <= wire_nlOilO1OO_dataout; + nl1ll0Ol <= wire_nl1lli1O_dataout; + nl1ll0OO <= wire_nl1lli0i_dataout; + nl1ll10i <= wire_nl1ll1li_dataout; + nl1ll11i <= wire_nl1ll1ii_dataout; + nl1ll11l <= wire_nl1ll1il_dataout; + nl1ll11O <= wire_nl1ll1iO_dataout; + nl1lli1i <= wire_nl1lli0l_dataout; + nl1llilO <= wire_nl1lli1l_dataout; + nl1lliOl <= wire_nl1lll1O_dataout; + nl1lliOO <= wire_nl1lll0i_dataout; + nl1lll1i <= wire_nl1lll0l_dataout; + nl1llllO <= wire_nl1lll1l_dataout; + nl1llOiO <= wire_nl1llOlO_dataout; + nl1lO10i <= wire_nl1lO1ii_dataout; + nl1lO10l <= wire_nl1lO1il_dataout; + nl1lO11i <= wire_nl1lO10O_dataout; + nl1lOi0i <= wire_nl1lOiii_dataout; + nl1lOill <= wire_nl1lOl0i_dataout; + nl1lOiOl <= wire_nl1lOl0l_dataout; + nl1lOiOO <= wire_nl1lOl0O_dataout; + nl1lOl1i <= wire_nl1lOlii_dataout; + nl1lOl1l <= wire_nl1lOlil_dataout; + nl1lOl1O <= wire_nl1lOliO_dataout; + nl1lOO0i <= wire_nl1lOOli_dataout; + nl1lOO0l <= wire_nl1lOOll_dataout; + nl1lOO0O <= wire_nl1lOOlO_dataout; + nl1lOOii <= wire_nl1lOOOi_dataout; + nl1lOOil <= wire_nl1O11il_dataout; + nl1O000i <= wire_nl1O00il_dataout; + nl1O000O <= wire_nl1O00iO_dataout; + nl1O011i <= wire_nl1O011O_dataout; + nl1O01Ol <= wire_nl1O01ll_dataout; + nl1O0iii <= wire_nl1O0i0i_dataout; + nl1O0ilO <= wire_nl1O0l1i_dataout; + nl1O0iOl <= wire_nl1O0l1l_dataout; + nl1O0lOO <= wire_nl1O0llO_dataout; + nl1O0O0l <= wire_nl1O0OiO_dataout; + nl1O0Oii <= wire_nl1O0Oli_dataout; + nl1O10ii <= wire_nl1O10lO_dataout; + nl1O10il <= wire_nl1O10Oi_dataout; + nl1O10iO <= wire_nl1O10Ol_dataout; + nl1O110l <= wire_nl1lOOiO_dataout; + nl1O110O <= wire_nl1O11iO_dataout; + nl1O11ii <= wire_nl1O11li_dataout; + nl1O1i0l <= wire_nl1O10ll_dataout; + nl1O1ili <= wire_nl1O1iOl_dataout; + nl1O1ilO <= wire_nl1O1iOO_dataout; + nl1O1O0O <= wire_nl1O1OiO_dataout; + nl1O1OOi <= wire_nl1O011l_dataout; + nl1Oi1il <= wire_nl1Oi10l_dataout; + nl1Oi1Oi <= wire_nl1Oi01l_dataout; + nl1Oi1OO <= wire_nl1Oi01O_dataout; + nl1Oii1i <= wire_nl1Oii0i_dataout; + nl1Oiiil <= wire_nl1OiilO_dataout; + nl1Oiill <= wire_nl1OiiOi_dataout; + nl1OiliO <= wire_nl1OillO_dataout; + nl1OiO0i <= wire_nl1OiO0O_dataout; + nl1OiO1i <= wire_nl1OiO0l_dataout; + nl1Ol0li <= wire_nl1Ol0ii_dataout; + nl1Ol0OO <= wire_nl1Oli0i_dataout; + nl1Ol11l <= wire_nl1OiOOl_dataout; + nl1Ol1ii <= wire_nl1Ol1ll_dataout; + nl1Ol1iO <= wire_nl1Ol1lO_dataout; + nl1Oli1l <= wire_nl1Oli0l_dataout; + nl1Oll1O <= wire_nl1OliOO_dataout; + nl1Ollil <= wire_nl1OlllO_dataout; + nl1Ollli <= wire_nl1OllOi_dataout; + nl1OlOll <= wire_nl1OlOil_dataout; + nl1OO11i <= wire_nl1OO10l_dataout; + nl1OO11O <= wire_nl1OO10O_dataout; + nl1OOiOi <= wire_nl1OOOll_dataout; + nl1OOiOl <= wire_nl1OOOlO_dataout; + nl1OOiOO <= wire_nl1OOOOi_dataout; + nl1OOl0i <= wire_nl01111l_dataout; + nl1OOl0l <= wire_nl01111O_dataout; + nl1OOl0O <= wire_nl01110i_dataout; + nl1OOl1i <= wire_nl1OOOOl_dataout; + nl1OOl1l <= wire_nl1OOOOO_dataout; + nl1OOl1O <= wire_nl01111i_dataout; + nl1OOlii <= wire_nl01110l_dataout; + nl1OOlil <= wire_nl01110O_dataout; + nl1OOliO <= wire_nl0111ii_dataout; + nl1OOlli <= wire_nl0111il_dataout; + nl1OOlll <= wire_nl0111iO_dataout; + nl1OOllO <= wire_nl0111li_dataout; + nl1OOlOi <= wire_nl0111ll_dataout; + nl1OOlOl <= wire_nl0111lO_dataout; + nl1OOlOO <= wire_nl0111Oi_dataout; + nl1OOO0i <= wire_nl01101l_dataout; + nl1OOO0l <= wire_nl01101O_dataout; + nl1OOO0O <= wire_nl01100i_dataout; + nl1OOO1i <= wire_nl0111Ol_dataout; + nl1OOO1l <= wire_nl0111OO_dataout; + nl1OOO1O <= wire_nl01101i_dataout; + nl1OOOii <= wire_nl01100l_dataout; + nl1OOOil <= wire_nl01100O_dataout; + nli01iOO <= wire_nliOliOi_dataout; + nli1100i <= nli1100O; + nli110iO <= nli1i1ll; + nli1110i <= wire_nli111li_dataout; + nli1111i <= wire_nli111ii_dataout; + nli1111l <= wire_nli111il_dataout; + nli1111O <= wire_nli111iO_dataout; + nli1i00i <= wire_nli1iiii_dataout; + nli1i00O <= wire_nli1iiiO_dataout; + nli1i01O <= wire_nli1ii0O_dataout; + nli1i0ii <= wire_nli1iili_dataout; + nli1i0il <= wire_nli1iill_dataout; + nli1i0iO <= wire_nli1iilO_dataout; + nli1i0li <= wire_nli1iiOi_dataout; + nli1i0ll <= wire_nli1iiOl_dataout; + nli1i0lO <= wire_nli1iiOO_dataout; + nli1i10O <= wire_nli1i0Oi_dataout; + nli1i1ll <= wire_nli1i0Ol_dataout; + nli1i1lO <= wire_nli1i0OO_dataout; + nli1i1Oi <= wire_nli1ii1i_dataout; + nli1i1Ol <= wire_nli1ii1l_dataout; + nli1i1OO <= wire_nli1ii1O_dataout; + nlilli0Oi <= wire_nlillil0l_dataout; + nlilli0Ol <= wire_nlillil0O_dataout; + nlilli0OO <= wire_nlillilii_dataout; + nlillii0i <= wire_nlillilll_dataout; + nlillii0l <= wire_nlillillO_dataout; + nlillii0O <= wire_nlillilOi_dataout; + nlillii1i <= wire_nlillilil_dataout; + nlillii1l <= wire_nlilliliO_dataout; + nlillii1O <= wire_nlillilli_dataout; + nlilliiii <= wire_nlillilOl_dataout; + nlilliiil <= wire_nlillilOO_dataout; + nlilliiiO <= wire_nlilliO1i_dataout; + nlilliili <= wire_nlilliO1l_dataout; + nlilliill <= wire_nlilliO1O_dataout; + nlilliilO <= wire_nlilliO0i_dataout; + nlilliiOi <= wire_nlilliO0l_dataout; + nlilliiOl <= wire_nlilliO0O_dataout; + nlilliiOO <= wire_nlilliOii_dataout; + nlillil1i <= wire_nlilliOil_dataout; + nlillil1l <= wire_nlillil0i_dataout; + nlillil1O <= wire_nlillOlOO_dataout; + nlillO00i <= wire_nlillOOii_dataout; + nlillO00l <= wire_nlillOOil_dataout; + nlillO00O <= wire_nlillOOiO_dataout; + nlillO01i <= wire_nlillOO0i_dataout; + nlillO01l <= wire_nlillOO0l_dataout; + nlillO01O <= wire_nlillOO0O_dataout; + nlillO0ii <= wire_nlillOOli_dataout; + nlillO0il <= wire_nlillOOll_dataout; + nlillO0iO <= wire_nlillOOlO_dataout; + nlillO0li <= wire_nlillOOOi_dataout; + nlillO0ll <= wire_nlillOOOl_dataout; + nlillO0lO <= wire_nlillOOOO_dataout; + nlillO0Oi <= wire_nlilO111i_dataout; + nlillO0Ol <= wire_nlilO111l_dataout; + nlillO0OO <= wire_nlilO111O_dataout; + nlillO1Oi <= wire_nlillOO1i_dataout; + nlillO1Ol <= wire_nlillOO1l_dataout; + nlillO1OO <= wire_nlillOO1O_dataout; + nlillOi0i <= wire_nlilO11ii_dataout; + nlillOi0l <= wire_nlilO11il_dataout; + nlillOi0O <= wire_nlilO11iO_dataout; + nlillOi1i <= wire_nlilO110i_dataout; + nlillOi1l <= wire_nlilO110l_dataout; + nlillOi1O <= wire_nlilO110O_dataout; + nlillOiii <= wire_nlilO11li_dataout; + nlillOiil <= wire_nlilO11ll_dataout; + nlillOiiO <= wire_nlilO11lO_dataout; + nlillOili <= wire_nlilO11Oi_dataout; + nlillOill <= wire_nlilO11Ol_dataout; + nlillOilO <= wire_nlilO11OO_dataout; + nlillOiOi <= wire_nlilO101i_dataout; + nlillOiOl <= wire_nlilO101l_dataout; + nlillOiOO <= wire_nlilO101O_dataout; + nlillOl0i <= wire_nlilO10ii_dataout; + nlillOl0l <= wire_nlilO10il_dataout; + nlillOl0O <= wire_nlilO10iO_dataout; + nlillOl1i <= wire_nlilO100i_dataout; + nlillOl1l <= wire_nlilO100l_dataout; + nlillOl1O <= wire_nlilO100O_dataout; + nlillOlii <= wire_nlilO10li_dataout; + nlillOlil <= wire_nlilO10ll_dataout; + nlillOliO <= wire_nlilO10lO_dataout; + nlillOlli <= wire_nlilO10Oi_dataout; + nlillOlll <= wire_nlilO10Ol_dataout; + nlillOllO <= wire_nlilO10OO_dataout; + nlillOlOl <= wire_nlilOiOOO_dataout; + nlilOilli <= wire_nlilOl11i_dataout; + nlilOilll <= wire_nlilOl11l_dataout; + nlilOillO <= wire_nlilOl11O_dataout; + nlilOilOi <= wire_nlilOl10i_dataout; + nlilOilOl <= wire_nlilOl10l_dataout; + nlilOilOO <= wire_nlilOl10O_dataout; + nlilOiO0i <= wire_nlilOl1li_dataout; + nlilOiO0l <= wire_nlilOl1ll_dataout; + nlilOiO0O <= wire_nlilOl1lO_dataout; + nlilOiO1i <= wire_nlilOl1ii_dataout; + nlilOiO1l <= wire_nlilOl1il_dataout; + nlilOiO1O <= wire_nlilOl1iO_dataout; + nlilOiOii <= wire_nlilOl1Oi_dataout; + nlilOiOil <= wire_nlilOl1Ol_dataout; + nlilOiOiO <= wire_nlilOl1OO_dataout; + nlilOiOli <= wire_nlilOl01i_dataout; + nlilOiOll <= wire_nlilOl01l_dataout; + nlilOiOlO <= wire_nlilOl01O_dataout; + nlilOiOOi <= wire_nlilOl00i_dataout; + nlilOiOOl <= wire_nlilOO0Oi_dataout; + nlilOO0iO <= wire_nlilOO0Ol_dataout; + nlilOO0li <= wire_nlilOO0OO_dataout; + nlilOO0ll <= wire_nlilOOi1i_dataout; + nliO0i0l <= wire_nliOliOl_dataout; + nliO0i0O <= wire_nliOliOO_dataout; + nliO0iii <= wire_nliOll1i_dataout; + nliO0iil <= wire_nliOll1l_dataout; + nliO0iiO <= wire_nliOll1O_dataout; + nliO0ili <= wire_nliOll0i_dataout; + nliO0ill <= wire_nliOll0l_dataout; + nliO0ilO <= wire_nliOll0O_dataout; + nliO0iOi <= wire_nliOllii_dataout; + nliO0iOl <= wire_nliOllil_dataout; + nliO0iOO <= wire_nliOlliO_dataout; + nliO0l0i <= wire_nliOllOi_dataout; + nliO0l0l <= wire_nliOllOl_dataout; + nliO0l0O <= wire_nliOllOO_dataout; + nliO0l1i <= wire_nliOllli_dataout; + nliO0l1l <= wire_nliOllll_dataout; + nliO0l1O <= wire_nliOlllO_dataout; + nliO0lii <= wire_nliOlO1i_dataout; + nliO0lil <= wire_nliOlO1l_dataout; + nliO0liO <= wire_nliOlO1O_dataout; + nliO0lli <= wire_nliOlO0i_dataout; + nliO0lll <= wire_nliOlO0l_dataout; + nliO0llO <= wire_nliOlO0O_dataout; + nliO0lOi <= wire_nliOlOii_dataout; + nliO0lOl <= wire_nliOlOil_dataout; + nliO0lOO <= wire_nliOlOiO_dataout; + nliO0O0i <= wire_nliOlOOi_dataout; + nliO0O0l <= wire_nliOlOOl_dataout; + nliO0O0O <= wire_nliOlOOO_dataout; + nliO0O1i <= wire_nliOlOli_dataout; + nliO0O1l <= wire_nliOlOll_dataout; + nliO0O1O <= wire_nliOlOlO_dataout; + nliO0Oii <= wire_nliOO11i_dataout; + nliO0Oil <= wire_nliOO11l_dataout; + nliO0OiO <= wire_nliOO11O_dataout; + nliO0Oli <= wire_nliOO10i_dataout; + nliO0Oll <= wire_nliOO10l_dataout; + nliO0OlO <= wire_nliOO10O_dataout; + nliO0OOi <= wire_nliOO1ii_dataout; + nliO0OOl <= wire_nliOO1il_dataout; + nliO0OOO <= wire_nliOO1iO_dataout; + nliOi00i <= wire_nliOO0Oi_dataout; + nliOi00l <= wire_nliOO0Ol_dataout; + nliOi00O <= wire_nliOO0OO_dataout; + nliOi01i <= wire_nliOO0li_dataout; + nliOi01l <= wire_nliOO0ll_dataout; + nliOi01O <= wire_nliOO0lO_dataout; + nliOi0ii <= wire_nliOOi1i_dataout; + nliOi0il <= wire_nliOOi1l_dataout; + nliOi0iO <= wire_nliOOi1O_dataout; + nliOi0li <= wire_nliOOi0i_dataout; + nliOi0ll <= wire_nliOOi0l_dataout; + nliOi0lO <= wire_nliOOi0O_dataout; + nliOi0Oi <= wire_nliOOiii_dataout; + nliOi0Ol <= wire_nliOOiil_dataout; + nliOi0OO <= wire_nliOOiiO_dataout; + nliOi10i <= wire_nliOO1Oi_dataout; + nliOi10l <= wire_nliOO1Ol_dataout; + nliOi10O <= wire_nliOO1OO_dataout; + nliOi11i <= wire_nliOO1li_dataout; + nliOi11l <= wire_nliOO1ll_dataout; + nliOi11O <= wire_nliOO1lO_dataout; + nliOi1ii <= wire_nliOO01i_dataout; + nliOi1il <= wire_nliOO01l_dataout; + nliOi1iO <= wire_nliOO01O_dataout; + nliOi1li <= wire_nliOO00i_dataout; + nliOi1ll <= wire_nliOO00l_dataout; + nliOi1lO <= wire_nliOO00O_dataout; + nliOi1Oi <= wire_nliOO0ii_dataout; + nliOi1Ol <= wire_nliOO0il_dataout; + nliOi1OO <= wire_nliOO0iO_dataout; + nliOii0i <= wire_nliOOiOi_dataout; + nliOii0l <= wire_nliOOiOl_dataout; + nliOii0O <= wire_nliOOiOO_dataout; + nliOii1i <= wire_nliOOili_dataout; + nliOii1l <= wire_nliOOill_dataout; + nliOii1O <= wire_nliOOilO_dataout; + nliOiiii <= wire_nliOOl1i_dataout; + nliOiiil <= wire_nliOOl1l_dataout; + nliOiiiO <= wire_nliOOl1O_dataout; + nliOiili <= wire_nliOOl0i_dataout; + nliOiill <= wire_nliOOl0l_dataout; + nliOiilO <= wire_nliOOl0O_dataout; + nliOiiOi <= wire_nliOOlii_dataout; + nliOiiOl <= wire_nliOOlil_dataout; + nliOiiOO <= wire_nliOOliO_dataout; + nliOil0i <= wire_nliOOlOi_dataout; + nliOil0l <= wire_nliOOlOl_dataout; + nliOil0O <= wire_nliOOlOO_dataout; + nliOil1i <= wire_nliOOlli_dataout; + nliOil1l <= wire_nliOOlll_dataout; + nliOil1O <= wire_nliOOllO_dataout; + nliOilii <= wire_nliOOO1i_dataout; + nliOilil <= wire_nliOOO1l_dataout; + nliOiliO <= wire_nliOOO1O_dataout; + nliOilli <= wire_nliOOO0i_dataout; + nliOilll <= wire_nliOOO0l_dataout; + nliOillO <= wire_nliOOO0O_dataout; + nliOilOi <= wire_nliOOOii_dataout; + nliOilOl <= wire_nliOOOil_dataout; + nliOilOO <= wire_nliOOOiO_dataout; + nliOiO0i <= wire_nliOOOOi_dataout; + nliOiO0l <= wire_nliOOOOl_dataout; + nliOiO0O <= wire_nliOOOOO_dataout; + nliOiO1i <= wire_nliOOOli_dataout; + nliOiO1l <= wire_nliOOOll_dataout; + nliOiO1O <= wire_nliOOOlO_dataout; + nliOiOii <= wire_nll1111i_dataout; + nliOiOil <= wire_nll1111l_dataout; + nliOiOiO <= wire_nll1111O_dataout; + nliOiOli <= wire_nll1110i_dataout; + nliOiOll <= wire_nll1110l_dataout; + nliOiOlO <= wire_nll1110O_dataout; + nliOiOOi <= wire_nll111ii_dataout; + nliOiOOl <= wire_nll111il_dataout; + nliOiOOO <= wire_nll111iO_dataout; + nliOl00i <= wire_nll110Oi_dataout; + nliOl00l <= wire_nll110Ol_dataout; + nliOl00O <= wire_nll110OO_dataout; + nliOl01i <= wire_nll110li_dataout; + nliOl01l <= wire_nll110ll_dataout; + nliOl01O <= wire_nll110lO_dataout; + nliOl0ii <= wire_nll11i1i_dataout; + nliOl0il <= wire_nll11i1l_dataout; + nliOl0iO <= wire_nll11i1O_dataout; + nliOl0li <= wire_nll11i0i_dataout; + nliOl0ll <= wire_nll11i0l_dataout; + nliOl0lO <= wire_nll11i0O_dataout; + nliOl0Oi <= wire_nll11iii_dataout; + nliOl0Ol <= wire_nll11iil_dataout; + nliOl0OO <= wire_nll11iiO_dataout; + nliOl10i <= wire_nll111Oi_dataout; + nliOl10l <= wire_nll111Ol_dataout; + nliOl10O <= wire_nll111OO_dataout; + nliOl11i <= wire_nll111li_dataout; + nliOl11l <= wire_nll111ll_dataout; + nliOl11O <= wire_nll111lO_dataout; + nliOl1ii <= wire_nll1101i_dataout; + nliOl1il <= wire_nll1101l_dataout; + nliOl1iO <= wire_nll1101O_dataout; + nliOl1li <= wire_nll1100i_dataout; + nliOl1ll <= wire_nll1100l_dataout; + nliOl1lO <= wire_nll1100O_dataout; + nliOl1Oi <= wire_nll110ii_dataout; + nliOl1Ol <= wire_nll110il_dataout; + nliOl1OO <= wire_nll110iO_dataout; + nliOli0i <= wire_nll11iOi_dataout; + nliOli0l <= wire_nll11iOl_dataout; + nliOli0O <= wire_nll11iOO_dataout; + nliOli1i <= wire_nll11ili_dataout; + nliOli1l <= wire_nll11ill_dataout; + nliOli1O <= wire_nll11ilO_dataout; + nliOliii <= wire_nll11l1i_dataout; + nliOliil <= wire_nll11l1l_dataout; + nliOliiO <= wire_nll11l1O_dataout; + nliOlili <= wire_nll11l0i_dataout; + nliOlill <= wire_nll11l0l_dataout; + nll0i000i <= wire_nll0ii1il_dataout; + nll0i000l <= wire_nll0ii1iO_dataout; + nll0i000O <= wire_nll0ii1li_dataout; + nll0i001i <= wire_nll0ii10l_dataout; + nll0i001l <= wire_nll0ii10O_dataout; + nll0i001O <= wire_nll0ii1ii_dataout; + nll0i00ii <= wire_nll0ii1ll_dataout; + nll0i00il <= wire_nll0ii1lO_dataout; + nll0i00iO <= wire_nll0ii1Oi_dataout; + nll0i00li <= wire_nll0ii1Ol_dataout; + nll0i00ll <= wire_nll0ii1OO_dataout; + nll0i00lO <= wire_nll0ii01i_dataout; + nll0i00Oi <= wire_nll0ii01l_dataout; + nll0i00Ol <= wire_nll0ii01O_dataout; + nll0i00OO <= wire_nll0ii00i_dataout; + nll0i01Oi <= wire_nll0ii11l_dataout; + nll0i01Ol <= wire_nll0ii11O_dataout; + nll0i01OO <= wire_nll0ii10i_dataout; + nll0i0i0i <= wire_nll0ii0il_dataout; + nll0i0i0l <= wire_nll0ii0iO_dataout; + nll0i0i0O <= wire_nll0ii0li_dataout; + nll0i0i1i <= wire_nll0ii00l_dataout; + nll0i0i1l <= wire_nll0ii00O_dataout; + nll0i0i1O <= wire_nll0ii0ii_dataout; + nll0i0iii <= wire_nll0ii0ll_dataout; + nll0i0iil <= wire_nll0ii0lO_dataout; + nll0i0iiO <= wire_nll0ii0Oi_dataout; + nll0i0ili <= wire_nll0ii0Ol_dataout; + nll0i0ill <= wire_nll0ii0OO_dataout; + nll0i0ilO <= wire_nll0iii1i_dataout; + nll0i0iOi <= wire_nll0iii1l_dataout; + nll0i0iOl <= wire_nll0iii1O_dataout; + nll0i0iOO <= wire_nll0iii0i_dataout; + nll0i0l0i <= wire_nll0iiiil_dataout; + nll0i0l0l <= wire_nll0iiiiO_dataout; + nll0i0l0O <= wire_nll0iiili_dataout; + nll0i0l1i <= wire_nll0iii0l_dataout; + nll0i0l1l <= wire_nll0iii0O_dataout; + nll0i0l1O <= wire_nll0iiiii_dataout; + nll0i0lii <= wire_nll0iiill_dataout; + nll0i0lil <= wire_nll0iiilO_dataout; + nll0i0liO <= wire_nll0iiiOi_dataout; + nll0i0lli <= wire_nll0iiiOl_dataout; + nll0i0lll <= wire_nll0iiiOO_dataout; + nll0i0llO <= wire_nll0iil1i_dataout; + nll0i0lOi <= wire_nll0iil1l_dataout; + nll0i0lOl <= wire_nll0iil1O_dataout; + nll0i0lOO <= wire_nll0iil0i_dataout; + nll0i0O0i <= wire_nll0iilil_dataout; + nll0i0O0l <= wire_nll0iiliO_dataout; + nll0i0O0O <= wire_nll0iilli_dataout; + nll0i0O1i <= wire_nll0iil0l_dataout; + nll0i0O1l <= wire_nll0iil0O_dataout; + nll0i0O1O <= wire_nll0iilii_dataout; + nll0i0Oii <= wire_nll0iilll_dataout; + nll0i0Oil <= wire_nll0iillO_dataout; + nll0i0OiO <= wire_nll0iilOi_dataout; + nll0i0Oli <= wire_nll0iilOl_dataout; + nll0i0Oll <= wire_nll0iilOO_dataout; + nll0i0OlO <= wire_nll0iiO1i_dataout; + nll0i0OOi <= wire_nll0iiO1l_dataout; + nll0i0OOl <= wire_nll0iiO1O_dataout; + nll0i0OOO <= wire_nll0iiO0i_dataout; + nll0iO1lO <= wire_nll0ii11i_dataout; + nll0liiOi <= wire_nll0lil1l_dataout; + nll0liiOl <= wire_nll0lil1O_dataout; + nll0liiOO <= wire_nll0ll01i_dataout; + nll0lilil <= wire_nll0lil1i_dataout; + nll0liOii <= wire_nll0ll01l_dataout; + nll0liOil <= wire_nll0ll01O_dataout; + nll0liOiO <= wire_nll0ll00i_dataout; + nll0liOli <= wire_nll0ll00l_dataout; + nll0liOll <= wire_nll0ll00O_dataout; + nll0liOlO <= wire_nll0ll0ii_dataout; + nll0liOOi <= wire_nll0ll0il_dataout; + nll0liOOl <= wire_nll0ll0iO_dataout; + nll0liOOO <= wire_nll0ll0li_dataout; + nll0ll10i <= wire_nll0ll0Ol_dataout; + nll0ll10l <= wire_nll0ll0OO_dataout; + nll0ll10O <= wire_nll0lli1i_dataout; + nll0ll11i <= wire_nll0ll0ll_dataout; + nll0ll11l <= wire_nll0ll0lO_dataout; + nll0ll11O <= wire_nll0ll0Oi_dataout; + nll0ll1ii <= wire_nll0lli1l_dataout; + nll0ll1il <= wire_nll0lli1O_dataout; + nll0ll1iO <= wire_nll0lli0i_dataout; + nll0ll1li <= wire_nll0lli0l_dataout; + nll0ll1ll <= wire_nll0lli0O_dataout; + nll0ll1lO <= wire_nll0lliii_dataout; + nll0ll1Oi <= wire_nll0lliil_dataout; + nll0ll1Ol <= wire_nll0lliiO_dataout; + nll0ll1OO <= wire_nll0lO01l_dataout; + nll0lO01i <= wire_nll0lOi0i_dataout; + nll0lO0ii <= wire_nll0lOi0l_dataout; + nll0lO0il <= wire_nll0lOi0O_dataout; + nll0lO0iO <= wire_nll0lOiii_dataout; + nll0lO0li <= wire_nll0lOiil_dataout; + nll0lO0ll <= wire_nll0lOiiO_dataout; + nll0lO0lO <= wire_nll0lOili_dataout; + nll0lO0Oi <= wire_nll0lOill_dataout; + nll0lO0Ol <= wire_nll0lOilO_dataout; + nll0lO0OO <= wire_nll0lOiOi_dataout; + nll0lOi1i <= wire_nll0lOiOl_dataout; + nll0lOi1l <= wire_nll0lOiOO_dataout; + nll0lOi1O <= wire_nll0O1i1O_dataout; + nll0O0i0i <= wire_nlliil01i_dataout; + nll0O0i0l <= wire_nll0Oiiii_dataout; + nll0O0i0O <= wire_nll0Oiiil_dataout; + nll0O0i1O <= wire_nll0Oii0O_dataout; + nll0O0iii <= wire_nll0OiiiO_dataout; + nll0O0iil <= wire_nll0Oiili_dataout; + nll0O0iiO <= wire_nll0Oiill_dataout; + nll0O0ili <= wire_nll0OiilO_dataout; + nll0O0ill <= wire_nll0OiiOi_dataout; + nll0O0ilO <= wire_nll0OiiOl_dataout; + nll0O0iOi <= wire_nll0OiiOO_dataout; + nll0O0iOl <= wire_nll0Oil1i_dataout; + nll0O0iOO <= wire_nll0Oil1l_dataout; + nll0O0l0i <= wire_nll0Oil0O_dataout; + nll0O0l0l <= wire_nll0Oilii_dataout; + nll0O0l0O <= wire_nll0Oilil_dataout; + nll0O0l1i <= wire_nll0Oil1O_dataout; + nll0O0l1l <= wire_nll0Oil0i_dataout; + nll0O0l1O <= wire_nll0Oil0l_dataout; + nll0O0lii <= wire_nll0OiliO_dataout; + nll0O0lil <= wire_nll0Oilli_dataout; + nll0O0liO <= wire_nll0Oilll_dataout; + nll0O0lli <= wire_nll0OillO_dataout; + nll0O0lll <= wire_nll0OilOi_dataout; + nll0O0llO <= wire_nll0OilOl_dataout; + nll0O0lO <= wire_nll0Olii_dataout; + nll0O0lOi <= wire_nll0OilOO_dataout; + nll0O0lOl <= wire_nll0OiO1i_dataout; + nll0O0lOO <= wire_nll0OiO1l_dataout; + nll0O0O0i <= wire_nll0OiO0O_dataout; + nll0O0O0l <= wire_nll0OiOii_dataout; + nll0O0O0O <= wire_nll0OiOil_dataout; + nll0O0O1i <= wire_nll0OiO1O_dataout; + nll0O0O1l <= wire_nll0OiO0i_dataout; + nll0O0O1O <= wire_nll0OiO0l_dataout; + nll0O0Oi <= wire_nll0Olil_dataout; + nll0O0Oii <= wire_nll0OiOiO_dataout; + nll0O0Oil <= wire_nll0OiOli_dataout; + nll0O0OiO <= wire_nll0OiOll_dataout; + nll0O0Ol <= wire_nll0OliO_dataout; + nll0O0Oli <= wire_nll0OiOlO_dataout; + nll0O0Oll <= wire_nll0OiOOi_dataout; + nll0O0OlO <= wire_nll0OiOOl_dataout; + nll0O0OO <= wire_nll0Olli_dataout; + nll0O0OOi <= wire_nll0OiOOO_dataout; + nll0O0OOl <= wire_nll0Ol11i_dataout; + nll0O0OOO <= wire_nll0Ol11l_dataout; + nll0O100i <= wire_nll0O1l1i_dataout; + nll0O100l <= wire_nll0O1l1l_dataout; + nll0O100O <= wire_nll0O1l1O_dataout; + nll0O101i <= wire_nll0O1iOi_dataout; + nll0O101l <= wire_nll0O1iOl_dataout; + nll0O101O <= wire_nll0O1iOO_dataout; + nll0O10ii <= wire_nll0O1l0i_dataout; + nll0O10il <= wire_nll0O1l0l_dataout; + nll0O10iO <= wire_nll0O1l0O_dataout; + nll0O10li <= wire_nll0O1lii_dataout; + nll0O10ll <= wire_nll0O1lil_dataout; + nll0O10lO <= wire_nll0O1liO_dataout; + nll0O10Oi <= wire_nll0O1lli_dataout; + nll0O10Ol <= wire_nll0O1lll_dataout; + nll0O10OO <= wire_nll0O1llO_dataout; + nll0O11ii <= wire_nll0O1i0i_dataout; + nll0O11il <= wire_nll0O1i0l_dataout; + nll0O11iO <= wire_nll0O1i0O_dataout; + nll0O11li <= wire_nll0O1iii_dataout; + nll0O11ll <= wire_nll0O1iil_dataout; + nll0O11lO <= wire_nll0O1iiO_dataout; + nll0O11Oi <= wire_nll0O1ili_dataout; + nll0O11Ol <= wire_nll0O1ill_dataout; + nll0O11OO <= wire_nll0O1ilO_dataout; + nll0O1i1i <= wire_nll0O1lOi_dataout; + nll0O1i1l <= wire_nll0Oii0l_dataout; + nll0Oi00i <= wire_nll0Ol00O_dataout; + nll0Oi00l <= wire_nll0Ol0ii_dataout; + nll0Oi00O <= wire_nll0Ol0il_dataout; + nll0Oi01i <= wire_nll0Ol01O_dataout; + nll0Oi01l <= wire_nll0Ol00i_dataout; + nll0Oi01O <= wire_nll0Ol00l_dataout; + nll0Oi0i <= wire_nll0OlOl_dataout; + nll0Oi0ii <= wire_nll0Ol0iO_dataout; + nll0Oi0il <= wire_nll0Ol0li_dataout; + nll0Oi0iO <= wire_nll0Ol0ll_dataout; + nll0Oi0l <= wire_nll0OlOO_dataout; + nll0Oi0li <= wire_nll0Ol0lO_dataout; + nll0Oi0ll <= wire_nll0Ol0Oi_dataout; + nll0Oi0lO <= wire_nll0Ol0Ol_dataout; + nll0Oi0O <= wire_nll0OO1i_dataout; + nll0Oi0Oi <= wire_nll0Ol0OO_dataout; + nll0Oi0Ol <= wire_nll0Oli1i_dataout; + nll0Oi0OO <= wire_nll0Oli1l_dataout; + nll0Oi10i <= wire_nll0Ol10O_dataout; + nll0Oi10l <= wire_nll0Ol1ii_dataout; + nll0Oi10O <= wire_nll0Ol1il_dataout; + nll0Oi11i <= wire_nll0Ol11O_dataout; + nll0Oi11l <= wire_nll0Ol10i_dataout; + nll0Oi11O <= wire_nll0Ol10l_dataout; + nll0Oi1i <= wire_nll0Olll_dataout; + nll0Oi1ii <= wire_nll0Ol1iO_dataout; + nll0Oi1il <= wire_nll0Ol1li_dataout; + nll0Oi1iO <= wire_nll0Ol1ll_dataout; + nll0Oi1l <= wire_nll0OllO_dataout; + nll0Oi1li <= wire_nll0Ol1lO_dataout; + nll0Oi1ll <= wire_nll0Ol1Oi_dataout; + nll0Oi1lO <= wire_nll0Ol1Ol_dataout; + nll0Oi1O <= wire_nll0OlOi_dataout; + nll0Oi1Oi <= wire_nll0Ol1OO_dataout; + nll0Oi1Ol <= wire_nll0Ol01i_dataout; + nll0Oi1OO <= wire_nll0Ol01l_dataout; + nll0Oii0i <= wire_nll0OOOOO_dataout; + nll0Oii1i <= wire_nll0Oli1O_dataout; + nll0Oii1l <= wire_nll0Oli0i_dataout; + nll0Oii1O <= wire_nll0Oli0l_dataout; + nll0Oiii <= wire_nll0OO1l_dataout; + nll0Oiil <= wire_nll0OO1O_dataout; + nll0OiiO <= wire_nll0OO0i_dataout; + nll0Oili <= wire_nll0OO0l_dataout; + nll0OilO <= wire_nll0OOii_dataout; + nll0OiOi <= wire_nll0OOil_dataout; + nll0OiOl <= wire_nll0OOiO_dataout; + nll0OiOO <= wire_nll0OOli_dataout; + nll0Ol0i <= wire_nll0OOOl_dataout; + nll0Ol0l <= wire_nlliO01O_dataout; + nll0Ol1i <= wire_nll0OOll_dataout; + nll0Ol1l <= wire_nll0OOlO_dataout; + nll0Ol1O <= wire_nll0OOOi_dataout; + nll0OOOll <= wire_nlli1111i_dataout; + nll0OOOlO <= wire_nlli1111l_dataout; + nll0OOOOi <= wire_nlli1111O_dataout; + nll0OOOOl <= wire_nlli110ii_dataout; + nll100Oil <= wire_nll11OlOi_dataout; + nll11lOli <= wire_nll11OlOl_dataout; + nll11lOll <= wire_nll11OlOO_dataout; + nll11lOlO <= wire_nll11OO1i_dataout; + nll11lOOi <= wire_nll11OO1l_dataout; + nll11lOOl <= wire_nll11OO1O_dataout; + nll11lOOO <= wire_nll11OO0i_dataout; + nll11O00i <= wire_nll1011il_dataout; + nll11O00l <= wire_nll1011iO_dataout; + nll11O00O <= wire_nll1011li_dataout; + nll11O01i <= wire_nll10110l_dataout; + nll11O01l <= wire_nll10110O_dataout; + nll11O01O <= wire_nll1011ii_dataout; + nll11O0ii <= wire_nll1011ll_dataout; + nll11O0il <= wire_nll1011lO_dataout; + nll11O0iO <= wire_nll1011Oi_dataout; + nll11O0li <= wire_nll1011Ol_dataout; + nll11O0ll <= wire_nll1011OO_dataout; + nll11O0lO <= wire_nll10101i_dataout; + nll11O0Oi <= wire_nll10101l_dataout; + nll11O0Ol <= wire_nll10101O_dataout; + nll11O0OO <= wire_nll10100i_dataout; + nll11O10i <= wire_nll11OOil_dataout; + nll11O10l <= wire_nll11OOiO_dataout; + nll11O10O <= wire_nll11OOli_dataout; + nll11O11i <= wire_nll11OO0l_dataout; + nll11O11l <= wire_nll11OO0O_dataout; + nll11O11O <= wire_nll11OOii_dataout; + nll11O1ii <= wire_nll11OOll_dataout; + nll11O1il <= wire_nll11OOlO_dataout; + nll11O1iO <= wire_nll11OOOi_dataout; + nll11O1li <= wire_nll11OOOl_dataout; + nll11O1ll <= wire_nll11OOOO_dataout; + nll11O1lO <= wire_nll10111i_dataout; + nll11O1Oi <= wire_nll10111l_dataout; + nll11O1Ol <= wire_nll10111O_dataout; + nll11O1OO <= wire_nll10110i_dataout; + nll11Oi0i <= wire_nll1010il_dataout; + nll11Oi0l <= wire_nll1010iO_dataout; + nll11Oi0O <= wire_nll1010li_dataout; + nll11Oi1i <= wire_nll10100l_dataout; + nll11Oi1l <= wire_nll10100O_dataout; + nll11Oi1O <= wire_nll1010ii_dataout; + nll11Oiii <= wire_nll1010ll_dataout; + nll11Oiil <= wire_nll1010lO_dataout; + nll11OiiO <= wire_nll1010Oi_dataout; + nll11Oili <= wire_nll1010Ol_dataout; + nll11Oill <= wire_nll1010OO_dataout; + nll11OilO <= wire_nll101i1i_dataout; + nll11OiOi <= wire_nll101i1l_dataout; + nll11OiOl <= wire_nll101i1O_dataout; + nll11OiOO <= wire_nll101i0i_dataout; + nll11Ol0i <= wire_nll101iil_dataout; + nll11Ol0l <= wire_nll101iiO_dataout; + nll11Ol0O <= wire_nll101ili_dataout; + nll11Ol1i <= wire_nll101i0l_dataout; + nll11Ol1l <= wire_nll101i0O_dataout; + nll11Ol1O <= wire_nll101iii_dataout; + nll11Olii <= wire_nll101ill_dataout; + nll11Olil <= wire_nll101ilO_dataout; + nll11OliO <= wire_nll101iOi_dataout; + nll11Olli <= wire_nll101iOl_dataout; + nll11Olll <= wire_nll101iOO_dataout; + nll11OllO <= wire_nll101l1i_dataout; + nlli0i00i <= wire_nlli0iOlO_dataout; + nlli0i00l <= wire_nlli0iOOi_dataout; + nlli0i00O <= wire_nlli0iOOl_dataout; + nlli0i01i <= wire_nlli0iOiO_dataout; + nlli0i01l <= wire_nlli0iOli_dataout; + nlli0i01O <= wire_nlli0iOll_dataout; + nlli0i0ii <= wire_nlli0iOOO_dataout; + nlli0i0il <= wire_nlli0l11i_dataout; + nlli0i0iO <= wire_nlli0l11l_dataout; + nlli0i0li <= wire_nlli0l11O_dataout; + nlli0i0ll <= wire_nlli0l10i_dataout; + nlli0i0lO <= wire_nlli0l10l_dataout; + nlli0i0Oi <= wire_nlli0l10O_dataout; + nlli0i0Ol <= wire_nlli0l1ii_dataout; + nlli0i0OO <= wire_nlli0l1il_dataout; + nlli0i1lO <= wire_nlli0iO0l_dataout; + nlli0i1Oi <= wire_nlli0iO0O_dataout; + nlli0i1Ol <= wire_nlli0iOii_dataout; + nlli0i1OO <= wire_nlli0iOil_dataout; + nlli0ii0i <= wire_nlli0l1lO_dataout; + nlli0ii0l <= wire_nlli0l1Oi_dataout; + nlli0ii0O <= wire_nlli0l1Ol_dataout; + nlli0ii1i <= wire_nlli0l1iO_dataout; + nlli0ii1l <= wire_nlli0l1li_dataout; + nlli0ii1O <= wire_nlli0l1ll_dataout; + nlli0iiii <= wire_nlli0l1OO_dataout; + nlli0iiil <= wire_nlli0l01i_dataout; + nlli0iiiO <= wire_nlli0l01l_dataout; + nlli0iili <= wire_nlli0l01O_dataout; + nlli0iill <= wire_nlli0l00i_dataout; + nlli0iilO <= wire_nlli0l00l_dataout; + nlli0iiOi <= wire_nlli0l00O_dataout; + nlli0iiOl <= wire_nlli0l0ii_dataout; + nlli0iiOO <= wire_nlli0l0il_dataout; + nlli0il0i <= wire_nlli0l0lO_dataout; + nlli0il0l <= wire_nlli0l0Oi_dataout; + nlli0il0O <= wire_nlli0l0Ol_dataout; + nlli0il1i <= wire_nlli0l0iO_dataout; + nlli0il1l <= wire_nlli0l0li_dataout; + nlli0il1O <= wire_nlli0l0ll_dataout; + nlli0ilii <= wire_nlli0l0OO_dataout; + nlli0ilil <= wire_nlli0li1i_dataout; + nlli0iliO <= wire_nlli0li1l_dataout; + nlli0illi <= wire_nlli0li1O_dataout; + nlli0illl <= wire_nlli0li0i_dataout; + nlli0illO <= wire_nlli0li0l_dataout; + nlli0ilOi <= wire_nlli0li0O_dataout; + nlli0ilOl <= wire_nlli0liii_dataout; + nlli0ilOO <= wire_nlli0liil_dataout; + nlli0iO1i <= wire_nlli0liiO_dataout; + nlli0iO1l <= wire_nlli0lili_dataout; + nlli0iO1O <= wire_nllii0OOi_dataout; + nlli1010i <= wire_nlli10iii_dataout; + nlli1010l <= wire_nlli10iil_dataout; + nlli1010O <= wire_nlli10iiO_dataout; + nlli1011i <= wire_nlli10i0i_dataout; + nlli1011l <= wire_nlli10i0l_dataout; + nlli1011O <= wire_nlli10i0O_dataout; + nlli101ii <= wire_nlli10ili_dataout; + nlli101il <= wire_nlli10ill_dataout; + nlli101iO <= wire_nlli10ilO_dataout; + nlli101li <= wire_nlli10iOi_dataout; + nlli101ll <= wire_nlli1Oi0l_dataout; + nlli1100O <= wire_nlli11i1O_dataout; + nlli11i1l <= wire_nlli101lO_dataout; + nlli11lli <= wire_nlli101Oi_dataout; + nlli11lll <= wire_nlli101Ol_dataout; + nlli11llO <= wire_nlli101OO_dataout; + nlli11lOi <= wire_nlli1001i_dataout; + nlli11lOl <= wire_nlli1001l_dataout; + nlli11lOO <= wire_nlli1001O_dataout; + nlli11O0i <= wire_nlli100ii_dataout; + nlli11O0l <= wire_nlli100il_dataout; + nlli11O0O <= wire_nlli100iO_dataout; + nlli11O1i <= wire_nlli1000i_dataout; + nlli11O1l <= wire_nlli1000l_dataout; + nlli11O1O <= wire_nlli1000O_dataout; + nlli11Oii <= wire_nlli100li_dataout; + nlli11Oil <= wire_nlli100ll_dataout; + nlli11OiO <= wire_nlli100lO_dataout; + nlli11Oli <= wire_nlli100Oi_dataout; + nlli11Oll <= wire_nlli100Ol_dataout; + nlli11OlO <= wire_nlli100OO_dataout; + nlli11OOi <= wire_nlli10i1i_dataout; + nlli11OOl <= wire_nlli10i1l_dataout; + nlli11OOO <= wire_nlli10i1O_dataout; + nlli1Oi0i <= wire_nlli1OO1O_dataout; + nlli1Oili <= wire_nlli1OO0i_dataout; + nlli1Oill <= wire_nlli1OO0l_dataout; + nlli1OilO <= wire_nlli1OO0O_dataout; + nlli1OiOi <= wire_nlli1OOii_dataout; + nlli1OiOl <= wire_nlli1OOil_dataout; + nlli1OiOO <= wire_nlli1OOiO_dataout; + nlli1Ol0i <= wire_nlli1OOOi_dataout; + nlli1Ol0l <= wire_nlli1OOOl_dataout; + nlli1Ol0O <= wire_nlli1OOOO_dataout; + nlli1Ol1i <= wire_nlli1OOli_dataout; + nlli1Ol1l <= wire_nlli1OOll_dataout; + nlli1Ol1O <= wire_nlli1OOlO_dataout; + nlli1Olii <= wire_nlli0111i_dataout; + nlli1Olil <= wire_nlli0111l_dataout; + nlli1OliO <= wire_nlli0111O_dataout; + nlli1Olli <= wire_nlli0110i_dataout; + nlli1Olll <= wire_nlli0110l_dataout; + nlli1OllO <= wire_nlli0110O_dataout; + nlli1OlOi <= wire_nlli011ii_dataout; + nlli1OlOl <= wire_nlli011il_dataout; + nlli1OlOO <= wire_nlli011iO_dataout; + nlli1OO1i <= wire_nlli011li_dataout; + nlli1OO1l <= wire_nlli0iO0i_dataout; + nllii0Oll <= wire_nllii0OOl_dataout; + nllii0OlO <= wire_nlliiilOO_dataout; + nlliii0Oi <= wire_nlliiiO1i_dataout; + nlliii0Ol <= wire_nlliiiO1l_dataout; + nlliii0OO <= wire_nlliiiO1O_dataout; + nlliiii0i <= wire_nlliiiOii_dataout; + nlliiii0l <= wire_nlliiiOil_dataout; + nlliiii0O <= wire_nlliiiOiO_dataout; + nlliiii1i <= wire_nlliiiO0i_dataout; + nlliiii1l <= wire_nlliiiO0l_dataout; + nlliiii1O <= wire_nlliiiO0O_dataout; + nlliiiiii <= wire_nlliiiOli_dataout; + nlliiiiil <= wire_nlliiiOll_dataout; + nlliiiiiO <= wire_nlliiiOlO_dataout; + nlliiiili <= wire_nlliiiOOi_dataout; + nlliiiill <= wire_nlliiiOOl_dataout; + nlliiiilO <= wire_nlliiiOOO_dataout; + nlliiiiOi <= wire_nlliil11i_dataout; + nlliiiiOl <= wire_nlliil11l_dataout; + nlliiiiOO <= wire_nlliil11O_dataout; + nlliiil0i <= wire_nlliil1ii_dataout; + nlliiil0l <= wire_nlliil1il_dataout; + nlliiil0O <= wire_nlliil1iO_dataout; + nlliiil1i <= wire_nlliil10i_dataout; + nlliiil1l <= wire_nlliil10l_dataout; + nlliiil1O <= wire_nlliil10O_dataout; + nlliiilii <= wire_nlliil1li_dataout; + nlliiilil <= wire_nlliil1ll_dataout; + nlliiiliO <= wire_nlliil1lO_dataout; + nlliiilli <= wire_nlliil1Oi_dataout; + nlliiilll <= wire_nlliil1Ol_dataout; + nlliiillO <= wire_nlliil1OO_dataout; + nlliiilOi <= wire_nlliil01i_dataout; + nlliiilOl <= wire_nllililii_dataout; + nllili00i <= wire_nlliliOiO_dataout; + nllili00l <= wire_nlliliOli_dataout; + nllili00O <= wire_nlliliOll_dataout; + nllili01i <= wire_nlliliO0O_dataout; + nllili01l <= wire_nlliliOii_dataout; + nllili01O <= wire_nlliliOil_dataout; + nllili0ii <= wire_nlliliOlO_dataout; + nllili0il <= wire_nlliliOOi_dataout; + nllili0iO <= wire_nlliliOOl_dataout; + nllili0li <= wire_nlliliOOO_dataout; + nllili0ll <= wire_nllill11i_dataout; + nllili0lO <= wire_nllill11l_dataout; + nllili0Oi <= wire_nllill11O_dataout; + nllili0Ol <= wire_nllill10i_dataout; + nllili0OO <= wire_nllill10l_dataout; + nllili10i <= wire_nllililiO_dataout; + nllili10l <= wire_nllililli_dataout; + nllili10O <= wire_nllililll_dataout; + nllili11O <= wire_nllililil_dataout; + nllili1ii <= wire_nllilillO_dataout; + nllili1il <= wire_nllililOi_dataout; + nllili1iO <= wire_nllililOl_dataout; + nllili1li <= wire_nllililOO_dataout; + nllili1ll <= wire_nlliliO1i_dataout; + nllili1lO <= wire_nlliliO1l_dataout; + nllili1Oi <= wire_nlliliO1O_dataout; + nllili1Ol <= wire_nlliliO0i_dataout; + nllili1OO <= wire_nlliliO0l_dataout; + nllilii0i <= wire_nllill1iO_dataout; + nllilii0l <= wire_nllill1li_dataout; + nllilii0O <= wire_nllill1ll_dataout; + nllilii1i <= wire_nllill10O_dataout; + nllilii1l <= wire_nllill1ii_dataout; + nllilii1O <= wire_nllill1il_dataout; + nlliliiii <= wire_nllill1lO_dataout; + nlliliiil <= wire_nllill1Oi_dataout; + nlliliiiO <= wire_nllill1Ol_dataout; + nlliliili <= wire_nllill1OO_dataout; + nlliliill <= wire_nllill01i_dataout; + nlliliilO <= wire_nllill01l_dataout; + nlliliiOi <= wire_nllill01O_dataout; + nlliliiOl <= wire_nllill00i_dataout; + nlliliiOO <= wire_nllill00l_dataout; + nllilil0i <= wire_nllill0iO_dataout; + nllilil0l <= wire_nllill0li_dataout; + nllilil0O <= wire_nlliO101l_dataout; + nllilil1i <= wire_nllill00O_dataout; + nllilil1l <= wire_nllill0ii_dataout; + nllilil1O <= wire_nllill0il_dataout; + nllillOi <= wire_nlliO00i_dataout; + nllillOl <= wire_nlliO00l_dataout; + nllillOO <= wire_nlliO00O_dataout; + nllilO0i <= wire_nlliO0li_dataout; + nllilO0l <= wire_nlliO0ll_dataout; + nllilO0O <= wire_nlliO0lO_dataout; + nllilO1i <= wire_nlliO0ii_dataout; + nllilO1l <= wire_nlliO0il_dataout; + nllilO1O <= wire_nlliO0iO_dataout; + nllilOii <= wire_nlliO0Oi_dataout; + nllilOil <= wire_nlliO0Ol_dataout; + nllilOiO <= wire_nlliO0OO_dataout; + nllilOli <= wire_nlliOi1i_dataout; + nllilOll <= wire_nlliOi1l_dataout; + nllilOlll <= wire_nlliO101O_dataout; + nllilOllO <= wire_nlliO100i_dataout; + nllilOlO <= wire_nlliOi1O_dataout; + nllilOlOi <= wire_nlliO100l_dataout; + nllilOlOl <= wire_nlliO100O_dataout; + nllilOlOO <= wire_nlliO10ii_dataout; + nllilOO0i <= wire_nlliO10ll_dataout; + nllilOO0l <= wire_nlliO10lO_dataout; + nllilOO0O <= wire_nlliO10Oi_dataout; + nllilOO1i <= wire_nlliO10il_dataout; + nllilOO1l <= wire_nlliO10iO_dataout; + nllilOO1O <= wire_nlliO10li_dataout; + nllilOOi <= wire_nlliOi0i_dataout; + nllilOOii <= wire_nlliO10Ol_dataout; + nllilOOil <= wire_nlliO10OO_dataout; + nllilOOiO <= wire_nlliO1i1i_dataout; + nllilOOl <= wire_nlliOi0l_dataout; + nllilOOli <= wire_nlliO1i1l_dataout; + nllilOOll <= wire_nlliO1i1O_dataout; + nllilOOlO <= wire_nlliO1i0i_dataout; + nllilOOO <= wire_nlliOi0O_dataout; + nllilOOOi <= wire_nlliO1i0l_dataout; + nllilOOOl <= wire_nlliO1i0O_dataout; + nllilOOOO <= wire_nlliO1iii_dataout; + nlliO01i <= wire_nlliOlii_dataout; + nlliO101i <= wire_nlliO1lil_dataout; + nlliO10i <= wire_nlliOili_dataout; + nlliO10l <= wire_nlliOill_dataout; + nlliO10O <= wire_nlliOilO_dataout; + nlliO110i <= wire_nlliO1ill_dataout; + nlliO110l <= wire_nlliO1ilO_dataout; + nlliO110O <= wire_nlliO1iOi_dataout; + nlliO111i <= wire_nlliO1iil_dataout; + nlliO111l <= wire_nlliO1iiO_dataout; + nlliO111O <= wire_nlliO1ili_dataout; + nlliO11i <= wire_nlliOiii_dataout; + nlliO11ii <= wire_nlliO1iOl_dataout; + nlliO11il <= wire_nlliO1iOO_dataout; + nlliO11iO <= wire_nlliO1l1i_dataout; + nlliO11l <= wire_nlliOiil_dataout; + nlliO11li <= wire_nlliO1l1l_dataout; + nlliO11ll <= wire_nlliO1l1O_dataout; + nlliO11lO <= wire_nlliO1l0i_dataout; + nlliO11O <= wire_nlliOiiO_dataout; + nlliO11Oi <= wire_nlliO1l0l_dataout; + nlliO11Ol <= wire_nlliO1l0O_dataout; + nlliO11OO <= wire_nlliO1lii_dataout; + nlliO1ii <= wire_nlliOiOi_dataout; + nlliO1il <= wire_nlliOiOl_dataout; + nlliO1iO <= wire_nlliOiOO_dataout; + nlliO1li <= wire_nlliOl1i_dataout; + nlliO1ll <= wire_nlliOl1l_dataout; + nlliO1lO <= wire_nlliOl1O_dataout; + nlliO1Oi <= wire_nlliOl0i_dataout; + nlliO1Ol <= wire_nlliOl0l_dataout; + nlliO1OO <= wire_nlliOl0O_dataout; + nlliOl00i <= wire_nlliOliOi_dataout; + nlliOl00l <= wire_nlliOliOl_dataout; + nlliOl00O <= wire_nlliOliOO_dataout; + nlliOl01i <= wire_nlliOlili_dataout; + nlliOl01l <= wire_nlliOlill_dataout; + nlliOl01O <= wire_nlliOlilO_dataout; + nlliOl0ii <= wire_nlliOll1i_dataout; + nlliOl0il <= wire_nlliOll1l_dataout; + nlliOl0iO <= wire_nlliOll1O_dataout; + nlliOl0li <= wire_nlliOll0i_dataout; + nlliOl0ll <= wire_nlliOll0l_dataout; + nlliOl0lO <= wire_nlliOll0O_dataout; + nlliOl0Oi <= wire_nlliOllii_dataout; + nlliOl0Ol <= wire_nlliOllil_dataout; + nlliOl0OO <= wire_nlliOlliO_dataout; + nlliOl10O <= wire_nlliOl11O_dataout; + nlliOl11l <= wire_nlliOli1O_dataout; + nlliOl1li <= wire_nlliOli0i_dataout; + nlliOl1ll <= wire_nlliOli0l_dataout; + nlliOl1lO <= wire_nlliOli0O_dataout; + nlliOl1Oi <= wire_nlliOliii_dataout; + nlliOl1Ol <= wire_nlliOliil_dataout; + nlliOl1OO <= wire_nlliOliiO_dataout; + nlliOli1i <= wire_nlliOllli_dataout; + nlliOli1l <= wire_nlll11O1O_dataout; + nlliOOiOO <= wire_nlll11O0i_dataout; + nlliOOl0i <= wire_nlll11Oil_dataout; + nlliOOl0l <= wire_nlll11OiO_dataout; + nlliOOl0O <= wire_nlll11Oli_dataout; + nlliOOl1i <= wire_nlll11O0l_dataout; + nlliOOl1l <= wire_nlll11O0O_dataout; + nlliOOl1O <= wire_nlll11Oii_dataout; + nlliOOlii <= wire_nlll11Oll_dataout; + nlliOOlil <= wire_nlll11OlO_dataout; + nlliOOliO <= wire_nlll11OOi_dataout; + nlliOOlli <= wire_nlll11OOl_dataout; + nlliOOlll <= wire_nlll11OOO_dataout; + nlliOOllO <= wire_nlll1011i_dataout; + nlliOOlOi <= wire_nlll1011l_dataout; + nlliOOlOl <= wire_nlll1011O_dataout; + nlll000il <= wire_nlll00l1O_dataout; + nlll000iO <= wire_nlll00l0i_dataout; + nlll000li <= wire_nlll00l0l_dataout; + nlll000ll <= wire_nlll00l0O_dataout; + nlll000lO <= wire_nlll00lii_dataout; + nlll000Oi <= wire_nlll00lil_dataout; + nlll000Ol <= wire_nlll00liO_dataout; + nlll000OO <= wire_nlll00lli_dataout; + nlll00i0i <= wire_nlll00lOl_dataout; + nlll00i0l <= wire_nlll00lOO_dataout; + nlll00i0O <= wire_nlll00O1i_dataout; + nlll00i1i <= wire_nlll00lll_dataout; + nlll00i1l <= wire_nlll00llO_dataout; + nlll00i1O <= wire_nlll00lOi_dataout; + nlll00iii <= wire_nlll00O1l_dataout; + nlll00iil <= wire_nlll00O1O_dataout; + nlll00iiO <= wire_nlll00O0i_dataout; + nlll00ili <= wire_nlll00O0l_dataout; + nlll00ill <= wire_nlll00O0O_dataout; + nlll00ilO <= wire_nlll00Oii_dataout; + nlll00iOi <= wire_nlll00Oil_dataout; + nlll00iOl <= wire_nlll00OiO_dataout; + nlll00iOO <= wire_nlll00Oli_dataout; + nlll00l1i <= wire_nlll0il0i_dataout; + nlll0100i <= wire_nlll01iii_dataout; + nlll0100l <= wire_nlll01iil_dataout; + nlll0100O <= wire_nlll01iiO_dataout; + nlll0101i <= wire_nlll01i0i_dataout; + nlll0101l <= wire_nlll01i0l_dataout; + nlll0101O <= wire_nlll01i0O_dataout; + nlll010ii <= wire_nlll01ili_dataout; + nlll010il <= wire_nlll01ill_dataout; + nlll010iO <= wire_nlll01ilO_dataout; + nlll010li <= wire_nlll01iOi_dataout; + nlll010ll <= wire_nlll01iOl_dataout; + nlll010lO <= wire_nlll01iOO_dataout; + nlll010Oi <= wire_nlll01l1i_dataout; + nlll010Ol <= wire_nlll01l1l_dataout; + nlll010OO <= wire_nlll01l1O_dataout; + nlll011OO <= wire_nlll01i1O_dataout; + nlll01i1i <= wire_nlll00l1l_dataout; + nlll0il1O <= wire_nlll0l11i_dataout; + nlll0ilOl <= wire_nlll0l11l_dataout; + nlll0ilOO <= wire_nlll0l11O_dataout; + nlll0iO0i <= wire_nlll0l1ii_dataout; + nlll0iO0l <= wire_nlll0l1il_dataout; + nlll0iO0O <= wire_nlll0l1iO_dataout; + nlll0iO1i <= wire_nlll0l10i_dataout; + nlll0iO1l <= wire_nlll0l10l_dataout; + nlll0iO1O <= wire_nlll0l10O_dataout; + nlll0iOii <= wire_nlll0l1li_dataout; + nlll0iOil <= wire_nlll0l1ll_dataout; + nlll0iOiO <= wire_nlll0l1lO_dataout; + nlll0iOli <= wire_nlll0l1Oi_dataout; + nlll0iOll <= wire_nlll0l1Ol_dataout; + nlll0iOlO <= wire_nlll0l1OO_dataout; + nlll0iOOi <= wire_nlll0l01i_dataout; + nlll0iOOl <= wire_nlll0l01l_dataout; + nlll0iOOO <= wire_nlll0l01O_dataout; + nlll0llO <= nllli10O; + nlll11l0l <= wire_nlll1010i_dataout; + nlll11l0O <= wire_nlll1010l_dataout; + nlll11lii <= wire_nlll1010O_dataout; + nlll11lil <= wire_nlll101ii_dataout; + nlll11liO <= wire_nlll101il_dataout; + nlll11lli <= wire_nlll101iO_dataout; + nlll11lll <= wire_nlll101li_dataout; + nlll11llO <= wire_nlll101ll_dataout; + nlll11lOi <= wire_nlll101lO_dataout; + nlll11lOl <= wire_nlll101Oi_dataout; + nlll11lOO <= wire_nlll101Ol_dataout; + nlll11O1i <= wire_nlll101OO_dataout; + nlll11O1l <= wire_nlll1illi_dataout; + nlll1il0i <= wire_nlll1ilOi_dataout; + nlll1il0l <= wire_nlll1ilOl_dataout; + nlll1il0O <= wire_nlll1ilOO_dataout; + nlll1il1l <= wire_nlll1illl_dataout; + nlll1il1O <= wire_nlll1illO_dataout; + nlll1ilii <= wire_nlll1iO1i_dataout; + nlll1iliO <= wire_nlll1O11i_dataout; + nlll1llOl <= wire_nlll1O11l_dataout; + nlll1llOO <= wire_nlll1O11O_dataout; + nlll1lO0i <= wire_nlll1O1ii_dataout; + nlll1lO0l <= wire_nlll1O1il_dataout; + nlll1lO0O <= wire_nlll1O1iO_dataout; + nlll1lO1i <= wire_nlll1O10i_dataout; + nlll1lO1l <= wire_nlll1O10l_dataout; + nlll1lO1O <= wire_nlll1O10O_dataout; + nlll1lOii <= wire_nlll1O1li_dataout; + nlll1lOil <= wire_nlll1O1ll_dataout; + nlll1lOiO <= wire_nlll1O1lO_dataout; + nlll1lOli <= wire_nlll1O1Oi_dataout; + nlll1lOll <= wire_nlll1O1Ol_dataout; + nlll1lOlO <= wire_nlll1O1OO_dataout; + nlll1lOOi <= wire_nlll1O01i_dataout; + nlll1lOOl <= wire_nlll1O01l_dataout; + nlll1lOOO <= wire_nlll1OOiO_dataout; + nlll1OO0O <= wire_nlll1OOli_dataout; + nlll1OOil <= wire_nlll01i1l_dataout; + nllli0il <= wire_nlllil0O_dataout; + nllli0Oi <= wire_nlllilii_dataout; + nllli0Ol <= wire_nlllilil_dataout; + nllli0OO <= wire_nllliliO_dataout; + nllli10O <= wire_nllli1ll_dataout; + nllli1ii <= wire_nllli1lO_dataout; + nllli1il <= wire_nllli1Oi_dataout; + nlllii0i <= wire_nlllilOi_dataout; + nlllii0l <= wire_nlllilOl_dataout; + nlllii0O <= wire_nlllilOO_dataout; + nlllii1i <= wire_nlllilli_dataout; + nlllii1l <= wire_nlllilll_dataout; + nlllii1O <= wire_nlllillO_dataout; + nllliiii <= wire_nllliO1i_dataout; + nllliiil <= wire_nllliO1l_dataout; + nllliiiO <= wire_nllliO1O_dataout; + nllliili <= wire_nllliO0i_dataout; + nllliill <= wire_nllliO0l_dataout; + nllliilO <= wire_nllliO0O_dataout; + nllliiOi <= wire_nllliOii_dataout; + nlllOlll <= wire_nllO0iil_dataout; + nlllOllO <= wire_nllO0iiO_dataout; + nlllOlOi <= wire_nllO0ili_dataout; + nlllOlOl <= wire_nllO0ill_dataout; + nlllOlOO <= wire_nllO0ilO_dataout; + nlllOO0i <= wire_nllO0l1i_dataout; + nlllOO0l <= wire_nllO0l1l_dataout; + nlllOO0O <= wire_nllO0l1O_dataout; + nlllOO1i <= wire_nllO0iOi_dataout; + nlllOO1l <= wire_nllO0iOl_dataout; + nlllOO1O <= wire_nllO0iOO_dataout; + nlllOOii <= wire_nllO0l0i_dataout; + nlllOOil <= wire_nllO0l0l_dataout; + nlllOOiO <= wire_nllO0l0O_dataout; + nlllOOli <= wire_nllO0lii_dataout; + nlllOOll <= wire_nllO0lil_dataout; + nlllOOlO <= wire_nllO0liO_dataout; + nlllOOOi <= wire_nllO0lli_dataout; + nlllOOOl <= wire_nllO0lll_dataout; + nlllOOOO <= wire_nllO0llO_dataout; + nllO000i <= wire_nllOl11i_dataout; + nllO000l <= wire_nllOl11l_dataout; + nllO000O <= wire_nllOl11O_dataout; + nllO001i <= wire_nllOiOOi_dataout; + nllO001l <= wire_nllOiOOl_dataout; + nllO001O <= wire_nllOiOOO_dataout; + nllO00ii <= wire_nllOl10i_dataout; + nllO00il <= wire_nllOl10l_dataout; + nllO00iO <= wire_nllOl10O_dataout; + nllO00li <= wire_nllOl1ii_dataout; + nllO00ll <= wire_nllOl1il_dataout; + nllO00lO <= wire_nllOl1iO_dataout; + nllO00Oi <= wire_nllOl1li_dataout; + nllO00Ol <= wire_nllOl1ll_dataout; + nllO00OO <= wire_nllOl1lO_dataout; + nllO010i <= wire_nllOiO1i_dataout; + nllO010l <= wire_nllOiO1l_dataout; + nllO010O <= wire_nllOiO1O_dataout; + nllO011i <= wire_nllOilOi_dataout; + nllO011l <= wire_nllOilOl_dataout; + nllO011O <= wire_nllOilOO_dataout; + nllO01ii <= wire_nllOiO0i_dataout; + nllO01il <= wire_nllOiO0l_dataout; + nllO01iO <= wire_nllOiO0O_dataout; + nllO01li <= wire_nllOiOii_dataout; + nllO01ll <= wire_nllOiOil_dataout; + nllO01lO <= wire_nllOiOiO_dataout; + nllO01Oi <= wire_nllOiOli_dataout; + nllO01Ol <= wire_nllOiOll_dataout; + nllO01OO <= wire_nllOiOlO_dataout; + nllO0i0i <= wire_nllOl01i_dataout; + nllO0i0l <= wire_nllOl01l_dataout; + nllO0i0O <= wire_nlO0llOl_dataout; + nllO0i1i <= wire_nllOl1Oi_dataout; + nllO0i1l <= wire_nllOl1Ol_dataout; + nllO0i1O <= wire_nllOl1OO_dataout; + nllO100i <= wire_nllOi11i_dataout; + nllO100l <= wire_nllOi11l_dataout; + nllO100O <= wire_nllOi11O_dataout; + nllO101i <= wire_nllO0OOi_dataout; + nllO101l <= wire_nllO0OOl_dataout; + nllO101O <= wire_nllO0OOO_dataout; + nllO10ii <= wire_nllOi10i_dataout; + nllO10il <= wire_nllOi10l_dataout; + nllO10iO <= wire_nllOi10O_dataout; + nllO10li <= wire_nllOi1ii_dataout; + nllO10ll <= wire_nllOi1il_dataout; + nllO10lO <= wire_nllOi1iO_dataout; + nllO10Oi <= wire_nllOi1li_dataout; + nllO10Ol <= wire_nllOi1ll_dataout; + nllO10OO <= wire_nllOi1lO_dataout; + nllO110i <= wire_nllO0O1i_dataout; + nllO110l <= wire_nllO0O1l_dataout; + nllO110O <= wire_nllO0O1O_dataout; + nllO111i <= wire_nllO0lOi_dataout; + nllO111l <= wire_nllO0lOl_dataout; + nllO111O <= wire_nllO0lOO_dataout; + nllO11ii <= wire_nllO0O0i_dataout; + nllO11il <= wire_nllO0O0l_dataout; + nllO11iO <= wire_nllO0O0O_dataout; + nllO11li <= wire_nllO0Oii_dataout; + nllO11ll <= wire_nllO0Oil_dataout; + nllO11lO <= wire_nllO0OiO_dataout; + nllO11Oi <= wire_nllO0Oli_dataout; + nllO11Ol <= wire_nllO0Oll_dataout; + nllO11OO <= wire_nllO0OlO_dataout; + nllO1i0i <= wire_nllOi01i_dataout; + nllO1i0l <= wire_nllOi01l_dataout; + nllO1i0O <= wire_nllOi01O_dataout; + nllO1i1i <= wire_nllOi1Oi_dataout; + nllO1i1l <= wire_nllOi1Ol_dataout; + nllO1i1O <= wire_nllOi1OO_dataout; + nllO1iii <= wire_nllOi00i_dataout; + nllO1iil <= wire_nllOi00l_dataout; + nllO1iiO <= wire_nllOi00O_dataout; + nllO1ili <= wire_nllOi0ii_dataout; + nllO1ill <= wire_nllOi0il_dataout; + nllO1ilO <= wire_nllOi0iO_dataout; + nllO1iOi <= wire_nllOi0li_dataout; + nllO1iOl <= wire_nllOi0ll_dataout; + nllO1iOO <= wire_nllOi0lO_dataout; + nllO1l0i <= wire_nllOii1i_dataout; + nllO1l0l <= wire_nllOii1l_dataout; + nllO1l0O <= wire_nllOii1O_dataout; + nllO1l1i <= wire_nllOi0Oi_dataout; + nllO1l1l <= wire_nllOi0Ol_dataout; + nllO1l1O <= wire_nllOi0OO_dataout; + nllO1lii <= wire_nllOii0i_dataout; + nllO1lil <= wire_nllOii0l_dataout; + nllO1liO <= wire_nllOii0O_dataout; + nllO1lli <= wire_nllOiiii_dataout; + nllO1lll <= wire_nllOiiil_dataout; + nllO1llO <= wire_nllOiiiO_dataout; + nllO1lOi <= wire_nllOiili_dataout; + nllO1lOl <= wire_nllOiill_dataout; + nllO1lOO <= wire_nllOiilO_dataout; + nllO1O0i <= wire_nllOil1i_dataout; + nllO1O0l <= wire_nllOil1l_dataout; + nllO1O0O <= wire_nllOil1O_dataout; + nllO1O1i <= wire_nllOiiOi_dataout; + nllO1O1l <= wire_nllOiiOl_dataout; + nllO1O1O <= wire_nllOiiOO_dataout; + nllO1Oii <= wire_nllOil0i_dataout; + nllO1Oil <= wire_nllOil0l_dataout; + nllO1OiO <= wire_nllOil0O_dataout; + nllO1Oli <= wire_nllOilii_dataout; + nllO1Oll <= wire_nllOilil_dataout; + nllO1OlO <= wire_nllOiliO_dataout; + nllO1OOi <= wire_nllOilli_dataout; + nllO1OOl <= wire_nllOilll_dataout; + nllO1OOO <= wire_nllOillO_dataout; + nllOil00i <= wire_nllOill0O_dataout; + nllOil00l <= wire_nllOillii_dataout; + nllOil00O <= wire_nllOillil_dataout; + nllOil01i <= wire_nllOill1O_dataout; + nllOil01l <= wire_nllOill0i_dataout; + nllOil01O <= wire_nllOill0l_dataout; + nllOil0ii <= wire_nllOilliO_dataout; + nllOil0il <= wire_nllOillli_dataout; + nllOil0iO <= wire_nllOillll_dataout; + nllOil0li <= wire_nllOilllO_dataout; + nllOil0ll <= wire_nllOillOi_dataout; + nllOil0lO <= wire_nllOillOl_dataout; + nllOil0Oi <= wire_nllOillOO_dataout; + nllOil0Ol <= wire_nllOilO1i_dataout; + nllOil0OO <= wire_nllOilO1l_dataout; + nllOil10O <= wire_nllOiliil_dataout; + nllOil1ii <= wire_nllOiliiO_dataout; + nllOil1il <= wire_nllOilili_dataout; + nllOil1iO <= wire_nllOilill_dataout; + nllOil1li <= wire_nllOililO_dataout; + nllOil1ll <= wire_nllOiliOi_dataout; + nllOil1lO <= wire_nllOiliOl_dataout; + nllOil1Oi <= wire_nllOiliOO_dataout; + nllOil1Ol <= wire_nllOill1i_dataout; + nllOil1OO <= wire_nllOill1l_dataout; + nllOili0i <= wire_nllOilO0O_dataout; + nllOili0l <= wire_nllOilOii_dataout; + nllOili0O <= wire_nllOilOil_dataout; + nllOili1i <= wire_nllOilO1O_dataout; + nllOili1l <= wire_nllOilO0i_dataout; + nllOili1O <= wire_nllOilO0l_dataout; + nllOl11OO <= wire_nllOiliii_dataout; + nlO00lOiO <= wire_nlO00O10l_dataout; + nlO00lOli <= wire_nlO00O10O_dataout; + nlO00lOll <= wire_nlO00O1ii_dataout; + nlO00lOlO <= wire_nlO00O1il_dataout; + nlO00lOOi <= wire_nlO00O1iO_dataout; + nlO00lOOl <= wire_nlO00O1li_dataout; + nlO00lOOO <= wire_nlO00O1ll_dataout; + nlO00O11i <= wire_nlO00O1lO_dataout; + nlO00O11O <= wire_nlO0iOl1i_dataout; + nlO0il00i <= wire_nlO0iOl1O_dataout; + nlO0il00l <= wire_nlO0iOl0i_dataout; + nlO0il00O <= wire_nlO0iOl0l_dataout; + nlO0il01O <= wire_nlO0iOl1l_dataout; + nlO0il0ii <= wire_nlO0iOl0O_dataout; + nlO0il0il <= wire_nlO0iOlii_dataout; + nlO0il0iO <= wire_nlO0iOlil_dataout; + nlO0il0li <= wire_nlO0iOliO_dataout; + nlO0il0ll <= wire_nlO0iOlli_dataout; + nlO0il0lO <= wire_nlO0iOlll_dataout; + nlO0il0Oi <= wire_nlO0iOllO_dataout; + nlO0il0Ol <= wire_nlO0iOlOi_dataout; + nlO0il0OO <= wire_nlO0iOlOl_dataout; + nlO0ili0i <= wire_nlO0iOO1O_dataout; + nlO0ili0l <= wire_nlO0iOO0i_dataout; + nlO0ili0O <= wire_nlO0iOO0l_dataout; + nlO0ili1i <= wire_nlO0iOlOO_dataout; + nlO0ili1l <= wire_nlO0iOO1i_dataout; + nlO0ili1O <= wire_nlO0iOO1l_dataout; + nlO0iliii <= wire_nlO0iOO0O_dataout; + nlO0iliil <= wire_nlO0iOOii_dataout; + nlO0iliiO <= wire_nlO0iOOil_dataout; + nlO0ilili <= wire_nlO0iOOiO_dataout; + nlO0ilill <= wire_nlO0iOOli_dataout; + nlO0ililO <= wire_nlO0iOOll_dataout; + nlO0iliOi <= wire_nlO0iOOlO_dataout; + nlO0iliOl <= wire_nlO0iOOOi_dataout; + nlO0iliOO <= wire_nlO0iOOOl_dataout; + nlO0ill0i <= wire_nlO0l111O_dataout; + nlO0ill0l <= wire_nlO0l110i_dataout; + nlO0ill0O <= wire_nlO0l110l_dataout; + nlO0ill1i <= wire_nlO0iOOOO_dataout; + nlO0ill1l <= wire_nlO0l111i_dataout; + nlO0ill1O <= wire_nlO0l111l_dataout; + nlO0illii <= wire_nlO0l110O_dataout; + nlO0illil <= wire_nlO0l11ii_dataout; + nlO0illiO <= wire_nlO0l11il_dataout; + nlO0illli <= wire_nlO0l11iO_dataout; + nlO0illll <= wire_nlO0l11li_dataout; + nlO0illlO <= wire_nlO0l11ll_dataout; + nlO0illOi <= wire_nlO0l11lO_dataout; + nlO0illOl <= wire_nlO0l11Oi_dataout; + nlO0illOO <= wire_nlO0l11Ol_dataout; + nlO0ilO0i <= wire_nlO0l101O_dataout; + nlO0ilO0l <= wire_nlO0l100i_dataout; + nlO0ilO0O <= wire_nlO0l100l_dataout; + nlO0ilO1i <= wire_nlO0l11OO_dataout; + nlO0ilO1l <= wire_nlO0l101i_dataout; + nlO0ilO1O <= wire_nlO0l101l_dataout; + nlO0ilOii <= wire_nlO0l100O_dataout; + nlO0ilOil <= wire_nlO0l10ii_dataout; + nlO0ilOiO <= wire_nlO0l10il_dataout; + nlO0ilOli <= wire_nlO0l10iO_dataout; + nlO0ilOll <= wire_nlO0l10li_dataout; + nlO0ilOlO <= wire_nlO0l10ll_dataout; + nlO0ilOOi <= wire_nlO0l10lO_dataout; + nlO0ilOOl <= wire_nlO0l10Oi_dataout; + nlO0ilOOO <= wire_nlO0l10Ol_dataout; + nlO0iO00i <= wire_nlO0l1l1O_dataout; + nlO0iO00l <= wire_nlO0l1l0i_dataout; + nlO0iO00O <= wire_nlO0l1l0l_dataout; + nlO0iO01i <= wire_nlO0l1iOO_dataout; + nlO0iO01l <= wire_nlO0l1l1i_dataout; + nlO0iO01O <= wire_nlO0l1l1l_dataout; + nlO0iO0ii <= wire_nlO0l1l0O_dataout; + nlO0iO0il <= wire_nlO0l1lii_dataout; + nlO0iO0iO <= wire_nlO0l1lil_dataout; + nlO0iO0li <= wire_nlO0l1liO_dataout; + nlO0iO0ll <= wire_nlO0l1lli_dataout; + nlO0iO0lO <= wire_nlO0l1lll_dataout; + nlO0iO0Oi <= wire_nlO0l1llO_dataout; + nlO0iO0Ol <= wire_nlO0l1lOi_dataout; + nlO0iO0OO <= wire_nlO0l1lOl_dataout; + nlO0iO10i <= wire_nlO0l1i1O_dataout; + nlO0iO10l <= wire_nlO0l1i0i_dataout; + nlO0iO10O <= wire_nlO0l1i0l_dataout; + nlO0iO11i <= wire_nlO0l10OO_dataout; + nlO0iO11l <= wire_nlO0l1i1i_dataout; + nlO0iO11O <= wire_nlO0l1i1l_dataout; + nlO0iO1ii <= wire_nlO0l1i0O_dataout; + nlO0iO1il <= wire_nlO0l1iii_dataout; + nlO0iO1iO <= wire_nlO0l1iil_dataout; + nlO0iO1li <= wire_nlO0l1iiO_dataout; + nlO0iO1ll <= wire_nlO0l1ili_dataout; + nlO0iO1lO <= wire_nlO0l1ill_dataout; + nlO0iO1Oi <= wire_nlO0l1ilO_dataout; + nlO0iO1Ol <= wire_nlO0l1iOi_dataout; + nlO0iO1OO <= wire_nlO0l1iOl_dataout; + nlO0iOi0i <= wire_nlO0l1O1O_dataout; + nlO0iOi0l <= wire_nlO0l1O0i_dataout; + nlO0iOi0O <= wire_nlO0l1O0l_dataout; + nlO0iOi1i <= wire_nlO0l1lOO_dataout; + nlO0iOi1l <= wire_nlO0l1O1i_dataout; + nlO0iOi1O <= wire_nlO0l1O1l_dataout; + nlO0iOiii <= wire_nlO0l1O0O_dataout; + nlO0iOiil <= wire_nlO0l1Oii_dataout; + nlO0iOiiO <= wire_nlO0l1Oil_dataout; + nlO0iOili <= wire_nlO0l1OiO_dataout; + nlO0iOill <= wire_nlO0l1Oli_dataout; + nlO0iOilO <= wire_nlO0l1Oll_dataout; + nlO0iOiOi <= wire_nlO0l1OlO_dataout; + nlO0iOiOl <= wire_nlO0l1OOi_dataout; + nlO0iOiOO <= wire_nlO0lilll_dataout; + nlO0li0OO <= wire_nlO0lillO_dataout; + nlO0lii0i <= wire_nlO0liO1i_dataout; + nlO0lii0l <= wire_nlO0liO1l_dataout; + nlO0lii0O <= wire_nlO0liO1O_dataout; + nlO0lii1i <= wire_nlO0lilOi_dataout; + nlO0lii1l <= wire_nlO0lilOl_dataout; + nlO0lii1O <= wire_nlO0lilOO_dataout; + nlO0liiii <= wire_nlO0liO0i_dataout; + nlO0liiil <= wire_nlO0liO0l_dataout; + nlO0liiiO <= wire_nlO0liO0O_dataout; + nlO0liili <= wire_nlO0liOii_dataout; + nlO0liill <= wire_nlO0liOil_dataout; + nlO0liilO <= wire_nlO0liOiO_dataout; + nlO0liiOi <= wire_nlO0liOli_dataout; + nlO0liiOl <= wire_nlO0liOll_dataout; + nlO0liiOO <= wire_nlO0liOlO_dataout; + nlO0lil0i <= wire_nlO0ll11i_dataout; + nlO0lil0l <= wire_nlO0ll11l_dataout; + nlO0lil0O <= wire_nlO0ll11O_dataout; + nlO0lil1i <= wire_nlO0liOOi_dataout; + nlO0lil1l <= wire_nlO0liOOl_dataout; + nlO0lil1O <= wire_nlO0liOOO_dataout; + nlO0lilii <= wire_nlO0ll10i_dataout; + nlO0lilil <= wire_nlO0ll10l_dataout; + nlO0liliO <= wire_nlO0ll10O_dataout; + nlO0lilli <= wire_nlO0OlOil_dataout; + nlO0lliO <= wire_nlO0llOO_dataout; + nlO0llli <= wire_nlO0lO1i_dataout; + nlO0llll <= wire_nlO0lO1l_dataout; + nlO0llOi <= wire_nlOiliil_dataout; + nlO0Ol00l <= wire_nlO0OlOiO_dataout; + nlO0Ol00O <= wire_nlO0OlOli_dataout; + nlO0Ol0ii <= wire_nlO0OlOll_dataout; + nlO0Ol0il <= wire_nlO0OlOlO_dataout; + nlO0Ol0iO <= wire_nlO0OlOOi_dataout; + nlO0Ol0li <= wire_nlO0OlOOl_dataout; + nlO0Ol0ll <= wire_nlO0OlOOO_dataout; + nlO0Ol0lO <= wire_nlO0OO11i_dataout; + nlO0Ol0Oi <= wire_nlO0OO11l_dataout; + nlO0Ol0Ol <= wire_nlO0OO11O_dataout; + nlO0Ol0OO <= wire_nlO0OO10i_dataout; + nlO0Oli0i <= wire_nlO0OO1il_dataout; + nlO0Oli0l <= wire_nlO0OO1iO_dataout; + nlO0Oli0O <= wire_nlO0OO1li_dataout; + nlO0Oli1i <= wire_nlO0OO10l_dataout; + nlO0Oli1l <= wire_nlO0OO10O_dataout; + nlO0Oli1O <= wire_nlO0OO1ii_dataout; + nlO0Oliii <= wire_nlO0OO1ll_dataout; + nlO0Oliil <= wire_nlO0OO1lO_dataout; + nlO0OliiO <= wire_nlO0OO1Oi_dataout; + nlO0Olili <= wire_nlO0OO1Ol_dataout; + nlO0Olill <= wire_nlO0OO1OO_dataout; + nlO0OlilO <= wire_nlO0OO01i_dataout; + nlO0OliOi <= wire_nlO0OO01l_dataout; + nlO0OliOl <= wire_nlO0OO01O_dataout; + nlO0OliOO <= wire_nlO0OO00i_dataout; + nlO0Oll0i <= wire_nlO0OO0il_dataout; + nlO0Oll0l <= wire_nlO0OO0iO_dataout; + nlO0Oll0O <= wire_nlO0OO0li_dataout; + nlO0Oll1i <= wire_nlO0OO00l_dataout; + nlO0Oll1l <= wire_nlO0OO00O_dataout; + nlO0Oll1O <= wire_nlO0OO0ii_dataout; + nlO0Ollii <= wire_nlO0OO0ll_dataout; + nlO0Ollil <= wire_nlO0OO0lO_dataout; + nlO0OlliO <= wire_nlO0OO0Oi_dataout; + nlO0Ollli <= wire_nlO0OO0Ol_dataout; + nlO0Ollll <= wire_nlO0OO0OO_dataout; + nlO0OlllO <= wire_nlO0OOi1i_dataout; + nlO0OllOi <= wire_nlO0OOi1l_dataout; + nlO0OllOl <= wire_nlO0OOi1O_dataout; + nlO0OllOO <= wire_nlO0OOi0i_dataout; + nlO0OlO0i <= wire_nlO0OOiil_dataout; + nlO0OlO0l <= wire_nlO0OOiiO_dataout; + nlO0OlO0O <= wire_nlO0OOili_dataout; + nlO0OlO1i <= wire_nlO0OOi0l_dataout; + nlO0OlO1l <= wire_nlO0OOi0O_dataout; + nlO0OlO1O <= wire_nlO0OOiii_dataout; + nlO0OlOii <= wire_nlOi1Ol0i_dataout; + nlO0OOOO <= wire_nlOiliiO_dataout; + nlO1iiOi <= wire_nllO0iii_dataout; + nlO1lOi0O <= wire_nlO1lOOil_dataout; + nlO1lOiii <= wire_nlO1lOOiO_dataout; + nlO1lOiil <= wire_nlO1lOOli_dataout; + nlO1lOiiO <= wire_nlO1lOOll_dataout; + nlO1lOili <= wire_nlO1lOOlO_dataout; + nlO1lOill <= wire_nlO1lOOOi_dataout; + nlO1lOilO <= wire_nlO1lOOOl_dataout; + nlO1lOiOi <= wire_nlO1lOOOO_dataout; + nlO1lOiOl <= wire_nlO1O111i_dataout; + nlO1lOiOO <= wire_nlO1O111l_dataout; + nlO1lOl0i <= wire_nlO1O110O_dataout; + nlO1lOl0l <= wire_nlO1O11ii_dataout; + nlO1lOl0O <= wire_nlO1O11il_dataout; + nlO1lOl1i <= wire_nlO1O111O_dataout; + nlO1lOl1l <= wire_nlO1O110i_dataout; + nlO1lOl1O <= wire_nlO1O110l_dataout; + nlO1lOlii <= wire_nlO1O11iO_dataout; + nlO1lOlil <= wire_nlO1O11li_dataout; + nlO1lOliO <= wire_nlO1O11ll_dataout; + nlO1lOlli <= wire_nlO1O11lO_dataout; + nlO1lOlll <= wire_nlO1O11Oi_dataout; + nlO1lOllO <= wire_nlO1O11Ol_dataout; + nlO1lOlOi <= wire_nlO1O11OO_dataout; + nlO1lOlOl <= wire_nlO1O101i_dataout; + nlO1lOlOO <= wire_nlO1O101l_dataout; + nlO1lOO0i <= wire_nlO1O100O_dataout; + nlO1lOO0l <= wire_nlO1O10ii_dataout; + nlO1lOO0O <= wire_nlO1O10il_dataout; + nlO1lOO1i <= wire_nlO1O101O_dataout; + nlO1lOO1l <= wire_nlO1O100i_dataout; + nlO1lOO1O <= wire_nlO1O100l_dataout; + nlO1O0l1i <= wire_nlO1lOOii_dataout; + nlO1O0O0i <= wire_nlO1Oi1ii_dataout; + nlO1Oi00i <= wire_nlO1Ol00l_dataout; + nlO1Oi00l <= wire_nlO1Ol00O_dataout; + nlO1Oi00O <= wire_nlO1Ol0ii_dataout; + nlO1Oi01i <= wire_nlO1Ol01l_dataout; + nlO1Oi01l <= wire_nlO1Ol01O_dataout; + nlO1Oi01O <= wire_nlO1Ol00i_dataout; + nlO1Oi0ii <= wire_nlO1Ol0il_dataout; + nlO1Oi0il <= wire_nlO1Ol0iO_dataout; + nlO1Oi0iO <= wire_nlO1Ol0li_dataout; + nlO1Oi0li <= wire_nlO1Ol0ll_dataout; + nlO1Oi0ll <= wire_nlO1Ol0lO_dataout; + nlO1Oi0lO <= wire_nlO1Ol0Oi_dataout; + nlO1Oi0Oi <= wire_nlO1Ol0Ol_dataout; + nlO1Oi0Ol <= wire_nlO1Ol0OO_dataout; + nlO1Oi0OO <= wire_nlO1Oli1i_dataout; + nlO1Oi10i <= wire_nlO1O0O0l_dataout; + nlO1Oi10l <= wire_nlO1Oi1il_dataout; + nlO1Oi10O <= wire_nlO1Ol1ll_dataout; + nlO1Oi1ll <= wire_nlO1Ol1lO_dataout; + nlO1Oi1lO <= wire_nlO1Ol1Oi_dataout; + nlO1Oi1Oi <= wire_nlO1Ol1Ol_dataout; + nlO1Oi1Ol <= wire_nlO1Ol1OO_dataout; + nlO1Oi1OO <= wire_nlO1Ol01i_dataout; + nlO1Oii0i <= wire_nlO1Oli0l_dataout; + nlO1Oii0l <= wire_nlO1Oli0O_dataout; + nlO1Oii0O <= wire_nlO1Oliii_dataout; + nlO1Oii1i <= wire_nlO1Oli1l_dataout; + nlO1Oii1l <= wire_nlO1Oli1O_dataout; + nlO1Oii1O <= wire_nlO1Oli0i_dataout; + nlO1Oiiii <= wire_nlO1Oliil_dataout; + nlO1Oiiil <= wire_nlO1OliiO_dataout; + nlO1OiiiO <= wire_nlO1Olili_dataout; + nlO1Oiili <= wire_nlO1Olill_dataout; + nlO1Oiill <= wire_nlO1OlilO_dataout; + nlO1OiilO <= wire_nlO1OliOi_dataout; + nlO1OiiOi <= wire_nlO1OliOl_dataout; + nlO1OiiOl <= wire_nlO1OliOO_dataout; + nlO1OiiOO <= wire_nlO1Oll1i_dataout; + nlO1Oil0i <= wire_nlO1Oll0l_dataout; + nlO1Oil0l <= wire_nlO1Oll0O_dataout; + nlO1Oil0O <= wire_nlO1Ollii_dataout; + nlO1Oil1i <= wire_nlO1Oll1l_dataout; + nlO1Oil1l <= wire_nlO1Oll1O_dataout; + nlO1Oil1O <= wire_nlO1Oll0i_dataout; + nlO1Oilii <= wire_nlO1Ollil_dataout; + nlO1Oilil <= wire_nlO1OlliO_dataout; + nlO1OiliO <= wire_nlO1Ollli_dataout; + nlO1Oilli <= wire_nlO1Ollll_dataout; + nlO1Oilll <= wire_nlO1OlllO_dataout; + nlO1OillO <= wire_nlO1OllOi_dataout; + nlO1OilOi <= wire_nlO1OllOl_dataout; + nlO1OilOl <= wire_nlO1OllOO_dataout; + nlO1OilOO <= wire_nlO1OlO1i_dataout; + nlO1OiO0i <= wire_nlO1OlO0l_dataout; + nlO1OiO0l <= wire_nlO1OlO0O_dataout; + nlO1OiO0O <= wire_nlO1OlOii_dataout; + nlO1OiO1i <= wire_nlO1OlO1l_dataout; + nlO1OiO1l <= wire_nlO1OlO1O_dataout; + nlO1OiO1O <= wire_nlO1OlO0i_dataout; + nlO1OiOii <= wire_nlO1OlOil_dataout; + nlO1OiOil <= wire_nlO1OlOiO_dataout; + nlO1OiOiO <= wire_nlO1OlOli_dataout; + nlO1OiOli <= wire_nlO1OlOll_dataout; + nlO1OiOll <= wire_nlO1OlOlO_dataout; + nlO1OiOlO <= wire_nlO1OlOOi_dataout; + nlO1OiOOi <= wire_nlO1OlOOl_dataout; + nlO1OiOOl <= wire_nlO1OlOOO_dataout; + nlO1OiOOO <= wire_nlO1OO11i_dataout; + nlO1Ol10i <= wire_nlO1OO10l_dataout; + nlO1Ol10l <= wire_nlO1OO10O_dataout; + nlO1Ol10O <= wire_nlO1OO1ii_dataout; + nlO1Ol11i <= wire_nlO1OO11l_dataout; + nlO1Ol11l <= wire_nlO1OO11O_dataout; + nlO1Ol11O <= wire_nlO1OO10i_dataout; + nlO1Ol1ii <= wire_nlO1OO1il_dataout; + nlO1Ol1il <= wire_nlO1OO1iO_dataout; + nlO1Ol1iO <= wire_nlO1OO1li_dataout; + nlO1Ol1li <= wire_nlO00O10i_dataout; + nlOi000i <= wire_nlOiOlOi_dataout; + nlOi000iO <= wire_nlOi000ii_dataout; + nlOi000l <= wire_nlOiOlOl_dataout; + nlOi000O <= wire_nlOiOlOO_dataout; + nlOi000Ol <= wire_nlOi00i1O_dataout; + nlOi0010l <= wire_nlOi001iO_dataout; + nlOi001i <= wire_nlOiOlli_dataout; + nlOi001ii <= wire_nlOi001li_dataout; + nlOi001l <= wire_nlOiOlll_dataout; + nlOi001O <= wire_nlOiOllO_dataout; + nlOi00i1i <= wire_nlOi00i0i_dataout; + nlOi00ii <= wire_nlOiOO1i_dataout; + nlOi00il <= wire_nlOiOO1l_dataout; + nlOi00iO <= wire_nlOiOO1O_dataout; + nlOi00l0l <= wire_nilOO11O_dataout; + nlOi00l1i <= nlilOiOOl; + nlOi00li <= wire_nlOiOO0i_dataout; + nlOi00lil <= nlOi00lli; + nlOi00ll <= wire_nlOiOO0l_dataout; + nlOi00llO <= nlOi00lOl; + nlOi00lO <= wire_nlOiOO0O_dataout; + nlOi00O0l <= wire_nlOi00Oil_dataout; + nlOi00Oi <= wire_nlOiOOii_dataout; + nlOi00Ol <= wire_nlOiOOil_dataout; + nlOi00OlO <= wire_nlOi00Oii_dataout; + nlOi00OO <= wire_nlOiOOiO_dataout; + nlOi010i <= wire_nlOiOiOi_dataout; + nlOi010l <= wire_nlOiOiOl_dataout; + nlOi010O <= wire_nlOiOiOO_dataout; + nlOi011i <= wire_nlOiOili_dataout; + nlOi011l <= wire_nlOiOill_dataout; + nlOi011O <= wire_nlOiOilO_dataout; + nlOi01ii <= wire_nlOiOl1i_dataout; + nlOi01il <= wire_nlOiOl1l_dataout; + nlOi01iO <= wire_nlOiOl1O_dataout; + nlOi01li <= wire_nlOiOl0i_dataout; + nlOi01ll <= wire_nlOiOl0l_dataout; + nlOi01lO <= wire_nlOiOl0O_dataout; + nlOi01Oi <= wire_nlOiOlii_dataout; + nlOi01Ol <= wire_nlOiOlil_dataout; + nlOi01OO <= wire_nlOiOliO_dataout; + nlOi01OOO <= wire_nlOi01OOi_dataout; + nlOi0i00i <= nlOi0i00O; + nlOi0i0i <= wire_nlOiOOOi_dataout; + nlOi0i0l <= wire_nlOiOOOl_dataout; + nlOi0i0O <= wire_nlOiOOOO_dataout; + nlOi0i10i <= wire_nlOi0i1ii_dataout; + nlOi0i11l <= wire_nlOi0i10O_dataout; + nlOi0i1i <= wire_nlOiOOli_dataout; + nlOi0i1l <= wire_nlOiOOll_dataout; + nlOi0i1O <= wire_nlOiOOlO_dataout; + nlOi0iii <= wire_nlOl111i_dataout; + nlOi0iil <= wire_nlOl111l_dataout; + nlOi0iiO <= wire_nlOl111O_dataout; + nlOi0ili <= wire_nlOl110i_dataout; + nlOi0ill <= wire_nlOl110l_dataout; + nlOi0ilO <= wire_nlOl110O_dataout; + nlOi0iOi <= wire_nlOl11ii_dataout; + nlOi0iOl <= wire_nlOl11il_dataout; + nlOi0iOO <= wire_nlOl11iO_dataout; + nlOi0l00O <= wire_nlOi0li0l_dataout; + nlOi0l01O <= wire_nlOi0li0i_dataout; + nlOi0l0i <= wire_nlOl11Oi_dataout; + nlOi0l0ii <= wire_nlOi0li0O_dataout; + nlOi0l0il <= wire_nlOi0liii_dataout; + nlOi0l0iO <= wire_nlOi0liil_dataout; + nlOi0l0l <= wire_nlOl11Ol_dataout; + nlOi0l0li <= wire_nlOi0liiO_dataout; + nlOi0l0ll <= wire_nlOi0lili_dataout; + nlOi0l0lO <= wire_nlOi0lill_dataout; + nlOi0l0O <= wire_nlOl11OO_dataout; + nlOi0l0Oi <= wire_nlOi0lilO_dataout; + nlOi0l0Ol <= wire_nlOi0liOi_dataout; + nlOi0l0OO <= wire_nlOi0liOl_dataout; + nlOi0l1i <= wire_nlOl11li_dataout; + nlOi0l1l <= wire_nlOl11ll_dataout; + nlOi0l1ll <= wire_nlOi0l1Ol_dataout; + nlOi0l1O <= wire_nlOl11lO_dataout; + nlOi0li1i <= wire_nlOi0liOO_dataout; + nlOi0li1l <= wire_nlOi0ll1i_dataout; + nlOi0li1O <= wire_nlOi0ll1l_dataout; + nlOi0lii <= wire_nlOl101i_dataout; + nlOi0lil <= wire_nlOl101l_dataout; + nlOi0liO <= wire_nlOl101O_dataout; + nlOi0lli <= wire_nlOl100i_dataout; + nlOi0lll <= wire_nlOl100l_dataout; + nlOi0llO <= wire_nlOl100O_dataout; + nlOi0lO0l <= nlOi0lOii; + nlOi0lOi <= wire_nlOl10ii_dataout; + nlOi0lOl <= wire_nlOl10il_dataout; + nlOi0lOO <= wire_nlOl10iO_dataout; + nlOi0lOOl <= wire_nlOi0O11l_dataout; + nlOi0O0i <= wire_nlOl10Oi_dataout; + nlOi0O0ii <= wire_nlOi0O00i_dataout; + nlOi0O0l <= wire_nlOl10Ol_dataout; + nlOi0O0lO <= wire_nlOi0Oi1i_dataout; + nlOi0O0O <= wire_nlOl10OO_dataout; + nlOi0O0Ol <= wire_nlOi0Oi1l_dataout; + nlOi0O10O <= wire_nlOi0O1li_dataout; + nlOi0O1i <= wire_nlOl10li_dataout; + nlOi0O1iO <= wire_nlOi0O1ll_dataout; + nlOi0O1l <= wire_nlOl10ll_dataout; + nlOi0O1O <= wire_nlOl10lO_dataout; + nlOi0Oii <= wire_nlOl1i1i_dataout; + nlOi0Oil <= wire_nlOl1i1l_dataout; + nlOi0OiO <= wire_nlOl1i1O_dataout; + nlOi0Ol0O <= wire_nlOi0Olli_dataout; + nlOi0Ol1i <= wire_nlOi0OiOi_dataout; + nlOi0Oli <= wire_nlOl1i0i_dataout; + nlOi0Olil <= wire_nlOi0Olll_dataout; + nlOi0Oll <= wire_nlOl1i0l_dataout; + nlOi0OlO <= wire_nlOl1i0O_dataout; + nlOi0OOi <= wire_nlOl1iii_dataout; + nlOi0OOl <= wire_nlOl1iil_dataout; + nlOi0OOll <= wire_nlOi0OOOl_dataout; + nlOi0OOO <= wire_nlOl1iiO_dataout; + nlOi100i <= wire_nlOillOi_dataout; + nlOi100l <= wire_nlOillOl_dataout; + nlOi100O <= wire_nlOillOO_dataout; + nlOi101i <= wire_nlOillli_dataout; + nlOi101l <= wire_nlOillll_dataout; + nlOi101O <= wire_nlOilllO_dataout; + nlOi10ii <= wire_nlOilO1i_dataout; + nlOi10il <= wire_nlOilO1l_dataout; + nlOi10iO <= wire_nlOilO1O_dataout; + nlOi10li <= wire_nlOilO0i_dataout; + nlOi10ll <= wire_nlOilO0l_dataout; + nlOi10lO <= wire_nlOilO0O_dataout; + nlOi10Oi <= wire_nlOilOii_dataout; + nlOi10Ol <= wire_nlOilOil_dataout; + nlOi10OO <= wire_nlOilOiO_dataout; + nlOi110i <= wire_nlOiliOi_dataout; + nlOi110l <= wire_nlOiliOl_dataout; + nlOi110O <= wire_nlOiliOO_dataout; + nlOi111i <= wire_nlOilili_dataout; + nlOi111l <= wire_nlOilill_dataout; + nlOi111O <= wire_nlOililO_dataout; + nlOi11ii <= wire_nlOill1i_dataout; + nlOi11il <= wire_nlOill1l_dataout; + nlOi11iO <= wire_nlOill1O_dataout; + nlOi11li <= wire_nlOill0i_dataout; + nlOi11ll <= wire_nlOill0l_dataout; + nlOi11lO <= wire_nlOill0O_dataout; + nlOi11Oi <= wire_nlOillii_dataout; + nlOi11Ol <= wire_nlOillil_dataout; + nlOi11OO <= wire_nlOilliO_dataout; + nlOi1i0i <= wire_nlOilOOi_dataout; + nlOi1i0l <= wire_nlOilOOl_dataout; + nlOi1i0O <= wire_nlOilOOO_dataout; + nlOi1i1i <= wire_nlOilOli_dataout; + nlOi1i1l <= wire_nlOilOll_dataout; + nlOi1i1O <= wire_nlOilOlO_dataout; + nlOi1iii <= wire_nlOiO11i_dataout; + nlOi1iil <= wire_nlOiO11l_dataout; + nlOi1iiO <= wire_nlOiO11O_dataout; + nlOi1ili <= wire_nlOiO10i_dataout; + nlOi1ill <= wire_nlOiO10l_dataout; + nlOi1ilO <= wire_nlOiO10O_dataout; + nlOi1iOi <= wire_nlOiO1ii_dataout; + nlOi1iOl <= wire_nlOiO1il_dataout; + nlOi1iOO <= wire_nlOiO1iO_dataout; + nlOi1l0i <= wire_nlOiO1Oi_dataout; + nlOi1l0l <= wire_nlOiO1Ol_dataout; + nlOi1l0O <= wire_nlOiO1OO_dataout; + nlOi1l1i <= wire_nlOiO1li_dataout; + nlOi1l1l <= wire_nlOiO1ll_dataout; + nlOi1l1O <= wire_nlOiO1lO_dataout; + nlOi1lii <= wire_nlOiO01i_dataout; + nlOi1lil <= wire_nlOiO01l_dataout; + nlOi1liO <= wire_nlOiO01O_dataout; + nlOi1lli <= wire_nlOiO00i_dataout; + nlOi1lll <= wire_nlOiO00l_dataout; + nlOi1llO <= wire_nlOiO00O_dataout; + nlOi1lOi <= wire_nlOiO0ii_dataout; + nlOi1lOl <= wire_nlOiO0il_dataout; + nlOi1lOO <= wire_nlOiO0iO_dataout; + nlOi1O0i <= wire_nlOiO0Oi_dataout; + nlOi1O0l <= wire_nlOiO0Ol_dataout; + nlOi1O0O <= wire_nlOiO0OO_dataout; + nlOi1O1i <= wire_nlOiO0li_dataout; + nlOi1O1l <= wire_nlOiO0ll_dataout; + nlOi1O1O <= wire_nlOiO0lO_dataout; + nlOi1Oii <= wire_nlOiOi1i_dataout; + nlOi1Oil <= wire_nlOiOi1l_dataout; + nlOi1Oill <= wire_nlOi1Ol0l_dataout; + nlOi1OilO <= wire_nlOi1Ol0O_dataout; + nlOi1OiO <= wire_nlOiOi1O_dataout; + nlOi1OiOi <= wire_nlOi1Olii_dataout; + nlOi1OiOl <= wire_nlOi1Olil_dataout; + nlOi1OiOO <= wire_nlOi1OliO_dataout; + nlOi1Ol1i <= wire_nlOi1Olli_dataout; + nlOi1Ol1l <= wire_nlOi1Olll_dataout; + nlOi1Ol1O <= wire_nlOi1OllO_dataout; + nlOi1Oli <= wire_nlOiOi0i_dataout; + nlOi1Oll <= wire_nlOiOi0l_dataout; + nlOi1OlO <= wire_nlOiOi0O_dataout; + nlOi1OOi <= wire_nlOiOiii_dataout; + nlOi1OOl <= wire_nlOiOiil_dataout; + nlOi1OOO <= wire_nlOiOiiO_dataout; + nlOii00i <= wire_nlOl1lOi_dataout; + nlOii00l <= wire_nlOl1lOl_dataout; + nlOii00O <= wire_nlOl1lOO_dataout; + nlOii01i <= wire_nlOl1lli_dataout; + nlOii01ii <= wire_nlOii010l_dataout; + nlOii01l <= wire_nlOl1lll_dataout; + nlOii01lO <= wire_nlOii001i_dataout; + nlOii01O <= wire_nlOl1llO_dataout; + nlOii01Ol <= wire_nlOii001l_dataout; + nlOii0i0O <= wire_nlOii0ili_dataout; + nlOii0i1i <= wire_nlOii00Ol_dataout; + nlOii0ii <= wire_nlOl1O1i_dataout; + nlOii0iil <= wire_nlOii0ill_dataout; + nlOii0il <= wire_nlOl1O1l_dataout; + nlOii0iO <= wire_nlOl1O1O_dataout; + nlOii0li <= wire_nlOl1O0i_dataout; + nlOii0lil <= wire_nilOO10i_dataout; + nlOii0ll <= wire_nlOl1O0l_dataout; + nlOii0llO <= wire_nilOO10l_dataout; + nlOii0lO <= wire_nlOl1O0O_dataout; + nlOii0O0l <= nli1il11i; + nlOii0O1i <= wire_nilOO10O_dataout; + nlOii0Oi <= wire_nlOl1Oii_dataout; + nlOii0OiO <= wire_nilOO01i_dataout; + nlOii0Ol <= wire_nlOl1Oil_dataout; + nlOii0OlO <= nlOii0OOl; + nlOii0OO <= wire_nlOl1OiO_dataout; + nlOii100l <= wire_nilOO1Oi_dataout; + nlOii101i <= wire_nilOO1lO_dataout; + nlOii10i <= wire_nlOl1iOi_dataout; + nlOii10iO <= wire_nilOO1Ol_dataout; + nlOii10l <= wire_nlOl1iOl_dataout; + nlOii10O <= wire_nlOl1iOO_dataout; + nlOii10Oi <= wire_nilOO1OO_dataout; + nlOii110O <= wire_nlOii11il_dataout; + nlOii111O <= wire_nlOii11ii_dataout; + nlOii11i <= wire_nlOl1ili_dataout; + nlOii11l <= wire_nlOl1ill_dataout; + nlOii11O <= wire_nlOl1ilO_dataout; + nlOii1i0i <= wire_nlOii1i1l_dataout; + nlOii1ii <= wire_nlOl1l1i_dataout; + nlOii1iiO <= wire_nlOii1iOi_dataout; + nlOii1il <= wire_nlOl1l1l_dataout; + nlOii1ill <= wire_nlOii1iOl_dataout; + nlOii1iO <= wire_nlOl1l1O_dataout; + nlOii1li <= wire_nlOl1l0i_dataout; + nlOii1ll <= wire_nlOl1l0l_dataout; + nlOii1lO <= wire_nlOl1l0O_dataout; + nlOii1lOi <= wire_nlOii1lll_dataout; + nlOii1O0l <= wire_nlOii1Oil_dataout; + nlOii1O1O <= wire_nlOii1Oii_dataout; + nlOii1Oi <= wire_nlOl1lii_dataout; + nlOii1Ol <= wire_nlOl1lil_dataout; + nlOii1OO <= wire_nlOl1liO_dataout; + nlOiii00O <= wire_nlOiii0li_dataout; + nlOiii01i <= wire_nlOiii1Ol_dataout; + nlOiii0i <= wire_nlOl1OOi_dataout; + nlOiii0il <= wire_nlOiii0ll_dataout; + nlOiii0l <= wire_nlOl1OOl_dataout; + nlOiii0O <= wire_nlOl1OOO_dataout; + nlOiii10l <= nlOiii1ii; + nlOiii11i <= nlOiii11O; + nlOiii1i <= wire_nlOl1Oli_dataout; + nlOiii1iO <= nlOiii1ll; + nlOiii1l <= wire_nlOl1Oll_dataout; + nlOiii1O <= wire_nlOl1OlO_dataout; + nlOiiiii <= wire_nlOl011i_dataout; + nlOiiiiiO <= wire_nlOiiiiii_dataout; + nlOiiiil <= wire_nlOl011l_dataout; + nlOiiiill <= wire_nlOiiiiOO_dataout; + nlOiiiiO <= wire_nlOl011O_dataout; + nlOiiiiOi <= wire_nlOiiil1i_dataout; + nlOiiili <= wire_nlOl010i_dataout; + nlOiiill <= wire_nlOl010l_dataout; + nlOiiilO <= wire_nlOl010O_dataout; + nlOiiiO0l <= wire_nlOiiiOOl_dataout; + nlOiiiO0O <= wire_nlOiiiOOO_dataout; + nlOiiiOi <= wire_nlOl01ii_dataout; + nlOiiiOii <= wire_nlOiil11i_dataout; + nlOiiiOil <= wire_nlOiil11l_dataout; + nlOiiiOiO <= wire_nlOiil11O_dataout; + nlOiiiOl <= wire_nlOl01il_dataout; + nlOiiiOli <= wire_nlOiil10i_dataout; + nlOiiiOll <= wire_nlOiil10l_dataout; + nlOiiiOO <= wire_nlOl01iO_dataout; + nlOiil00l <= wire_nlOiil0iO_dataout; + nlOiil0i <= wire_nlOl01Oi_dataout; + nlOiil0ii <= wire_nlOiil0li_dataout; + nlOiil0l <= wire_nlOl01Ol_dataout; + nlOiil0O <= wire_nlOl01OO_dataout; + nlOiil1i <= wire_nlOl01li_dataout; + nlOiil1l <= wire_nlOl01ll_dataout; + nlOiil1O <= wire_nlOl01lO_dataout; + nlOiil1OO <= wire_nlOiiiOOi_dataout; + nlOiilii <= wire_nlOl001i_dataout; + nlOiilil <= wire_nlOl001l_dataout; + nlOiiliO <= wire_nlOl001O_dataout; + nlOiilli <= wire_nlOl000i_dataout; + nlOiilll <= wire_nlOl000l_dataout; + nlOiillO <= wire_nlOl000O_dataout; + nlOiilO0i <= wire_nlOiilOiO_dataout; + nlOiilO0l <= wire_nlOiilOli_dataout; + nlOiilO1O <= wire_nlOiilOil_dataout; + nlOiilOi <= wire_nlOl00ii_dataout; + nlOiilOl <= wire_nlOl00il_dataout; + nlOiilOO <= wire_nlOl00iO_dataout; + nlOiiO0i <= wire_nlOl00Oi_dataout; + nlOiiO0l <= wire_nlOl00Ol_dataout; + nlOiiO0O <= wire_nlOl00OO_dataout; + nlOiiO10O <= wire_nlOiiO1li_dataout; + nlOiiO11i <= wire_nlOiilOii_dataout; + nlOiiO1i <= wire_nlOl00li_dataout; + nlOiiO1il <= wire_nlOiiO1ll_dataout; + nlOiiO1l <= wire_nlOl00ll_dataout; + nlOiiO1O <= wire_nlOl00lO_dataout; + nlOiiOii <= wire_nlOl0i1i_dataout; + nlOiiOiiO <= wire_nlOiiOiOO_dataout; + nlOiiOil <= wire_nlOl0i1l_dataout; + nlOiiOili <= wire_nlOiiOl1i_dataout; + nlOiiOill <= wire_nlOiiOl1l_dataout; + nlOiiOilO <= wire_nlOiiOl1O_dataout; + nlOiiOiO <= wire_nlOl0i1O_dataout; + nlOiiOli <= wire_nlOl0i0i_dataout; + nlOiiOll <= wire_nlOl0i0l_dataout; + nlOiiOlli <= wire_nlOiiOiOl_dataout; + nlOiiOlO <= wire_nlOl0i0O_dataout; + nlOiiOlOO <= wire_nlOiiOO0i_dataout; + nlOiiOO1l <= wire_nlOiiOO0l_dataout; + nlOiiOOi <= wire_nlOl0iii_dataout; + nlOiiOOl <= wire_nlOl0iil_dataout; + nlOiiOOO <= wire_nlOl0iiO_dataout; + nlOil001i <= wire_nlOil0ill_dataout; + nlOil00i <= wire_nlOl0lOi_dataout; + nlOil00l <= wire_nlOl0lOl_dataout; + nlOil00O <= wire_nlOl0lOO_dataout; + nlOil010i <= wire_nlOil00Ol_dataout; + nlOil010O <= wire_nlOil0i1i_dataout; + nlOil011O <= wire_nlOil00Oi_dataout; + nlOil01i <= wire_nlOl0lli_dataout; + nlOil01ii <= wire_nlOil0i1l_dataout; + nlOil01il <= wire_nlOil0i1O_dataout; + nlOil01iO <= wire_nlOil0i0i_dataout; + nlOil01l <= wire_nlOl0lll_dataout; + nlOil01li <= wire_nlOil0i0l_dataout; + nlOil01ll <= wire_nlOil0i0O_dataout; + nlOil01lO <= wire_nlOil0iii_dataout; + nlOil01O <= wire_nlOl0llO_dataout; + nlOil01Oi <= wire_nlOil0iil_dataout; + nlOil01Ol <= wire_nlOil0iiO_dataout; + nlOil01OO <= wire_nlOil0ili_dataout; + nlOil0ii <= wire_nlOl0O1i_dataout; + nlOil0il <= wire_nlOl0O1l_dataout; + nlOil0iO <= wire_nlOl0O1O_dataout; + nlOil0li <= wire_nlOl0O0i_dataout; + nlOil0ll <= wire_nlOl0O0l_dataout; + nlOil0lO <= wire_nlOl0O0O_dataout; + nlOil0Oi <= wire_nlOl0Oii_dataout; + nlOil0Ol <= wire_nlOl0Oil_dataout; + nlOil0OO <= wire_nlOl0OiO_dataout; + nlOil10i <= wire_nlOl0iOi_dataout; + nlOil10l <= wire_nlOl0iOl_dataout; + nlOil10O <= wire_nlOl0iOO_dataout; + nlOil11i <= wire_nlOl0ili_dataout; + nlOil11l <= wire_nlOl0ill_dataout; + nlOil11O <= wire_nlOl0ilO_dataout; + nlOil1ii <= wire_nlOl0l1i_dataout; + nlOil1il <= wire_nlOl0l1l_dataout; + nlOil1iO <= wire_nlOl0l1O_dataout; + nlOil1li <= wire_nlOl0l0i_dataout; + nlOil1ll <= wire_nlOl0l0l_dataout; + nlOil1lO <= wire_nlOl0l0O_dataout; + nlOil1O1O <= wire_nlOil001l_dataout; + nlOil1Oi <= wire_nlOl0lii_dataout; + nlOil1Oil <= wire_nlOil001O_dataout; + nlOil1OiO <= wire_nlOil000i_dataout; + nlOil1Ol <= wire_nlOl0lil_dataout; + nlOil1Oli <= wire_nlOil000l_dataout; + nlOil1Oll <= wire_nlOil000O_dataout; + nlOil1OlO <= wire_nlOil00ii_dataout; + nlOil1OO <= wire_nlOl0liO_dataout; + nlOil1OOi <= wire_nlOil00il_dataout; + nlOil1OOl <= wire_nlOil00iO_dataout; + nlOil1OOO <= wire_nlOil00li_dataout; + nlOili0i <= wire_nlOl0OOi_dataout; + nlOili0l <= wire_nlOl0OOl_dataout; + nlOili0O <= wire_nlOl0OOO_dataout; + nlOili10l <= wire_nlOili11O_dataout; + nlOili1i <= wire_nlOl0Oli_dataout; + nlOili1l <= wire_nlOl0Oll_dataout; + nlOili1li <= wire_nlOili1Ol_dataout; + nlOili1lO <= wire_nlOili1OO_dataout; + nlOili1O <= wire_nlOl0OlO_dataout; + nlOiliii <= wire_n1l00iO_dataout; + nlOiliiil <= wire_nlOilil0O_dataout; + nlOiliiiO <= wire_nlOililii_dataout; + nlOiliili <= wire_nlOililil_dataout; + nlOiliill <= wire_nlOililiO_dataout; + nlOiliilO <= wire_nlOililli_dataout; + nlOiliiOi <= wire_nlOililll_dataout; + nlOiliiOl <= wire_nlOilillO_dataout; + nlOiliiOO <= wire_nlOililOi_dataout; + nlOilO00i <= wire_nlOilO01l_dataout; + nlOilO0iO <= wire_nlOilO0Oi_dataout; + nlOilO0ll <= wire_nlOilO0Ol_dataout; + nlOilOiOi <= wire_nlOilOill_dataout; + nlOilOl0l <= wire_nlOilOlil_dataout; + nlOilOl1O <= wire_nlOilOlii_dataout; + nlOilOOii <= wire_nlOilOO0l_dataout; + nlOilOOlO <= wire_nlOiO111i_dataout; + nlOilOOOl <= wire_nlOiO111l_dataout; + nlOl1i01l <= wire_nlOl1li0O_dataout; + nlOl1li0i <= wire_nlOl1liii_dataout; + nlOl1li0l <= wire_nlOl1liil_dataout; + END IF; + END PROCESS; + wire_nl1000i_CLRN <= ((niOO0llli42 XOR niOO0llli41) AND wire_niO0010l_dataout); + wire_nl1000i_w_lg_w_lg_w29769w29771w29774w(0) <= wire_nl1000i_w_lg_w29769w29771w(0) AND nlO0liiOO; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w2361w2363w2364w2365w2366w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w2361w2363w2364w2365w(0) AND niOilii; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w2361w2371w2373w2375w2380w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w2361w2371w2373w2375w(0) AND niOilii; + wire_nl1000i_w_lg_w36978w36979w(0) <= wire_nl1000i_w36978w(0) AND nlli1Oill; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_w4436w4438w4440w4442w4446w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w4436w4438w4440w4442w(0) AND n1l01iO; + wire_nl1000i_w_lg_w29769w29771w(0) <= wire_nl1000i_w29769w(0) AND wire_nl1000i_w_lg_nlO0lil1i29770w(0); + wire_nl1000i_w_lg_w_lg_w_lg_w2361w2363w2364w2365w(0) <= wire_nl1000i_w_lg_w_lg_w2361w2363w2364w(0) AND niOilil; + wire_nl1000i_w_lg_w_lg_w_lg_w2361w2371w2373w2375w(0) <= wire_nl1000i_w_lg_w_lg_w2361w2371w2373w(0) AND wire_nl1000i_w_lg_niOilil2374w(0); + wire_nl1000i_w_lg_w_lg_w_lg_w2361w2371w2373w2383w(0) <= wire_nl1000i_w_lg_w_lg_w2361w2371w2373w(0) AND niOilil; + wire_nl1000i_w36978w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w36974w36975w36976w36977w(0) AND nlli1OilO; + wire_nl1000i_w_lg_w_lg_w_lg_w4436w4438w4440w4442w(0) <= wire_nl1000i_w_lg_w_lg_w4436w4438w4440w(0) AND wire_nl1000i_w_lg_n1l01li4441w(0); + wire_nl1000i_w29769w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w29761w29763w29765w29767w(0) AND wire_nl1000i_w_lg_nlO0lil1l29768w(0); + wire_nl1000i_w_lg_w_lg_w2361w2363w2364w(0) <= wire_nl1000i_w_lg_w2361w2363w(0) AND niOiliO; + wire_nl1000i_w_lg_w_lg_w2361w2371w2373w(0) <= wire_nl1000i_w_lg_w2361w2371w(0) AND wire_nl1000i_w_lg_niOiliO2372w(0); + wire_nl1000i_w_lg_w_lg_w_lg_w36974w36975w36976w36977w(0) <= wire_nl1000i_w_lg_w_lg_w36974w36975w36976w(0) AND nlli1OiOi; + wire_nl1000i_w_lg_w_lg_w4436w4438w4440w(0) <= wire_nl1000i_w_lg_w4436w4438w(0) AND wire_nl1000i_w_lg_n1l01ll4439w(0); + wire_nl1000i_w_lg_w_lg_w_lg_w29761w29763w29765w29767w(0) <= wire_nl1000i_w_lg_w_lg_w29761w29763w29765w(0) AND wire_nl1000i_w_lg_nlO0lil1O29766w(0); + wire_nl1000i_w_lg_w2361w2363w(0) <= wire_nl1000i_w2361w(0) AND wire_nl1000i_w_lg_niOilli2362w(0); + wire_nl1000i_w_lg_w2361w2371w(0) <= wire_nl1000i_w2361w(0) AND niOilli; + wire_nl1000i_w_lg_w_lg_w36974w36975w36976w(0) <= wire_nl1000i_w_lg_w36974w36975w(0) AND nlli1OiOl; + wire_nl1000i_w_lg_w4436w4438w(0) <= wire_nl1000i_w4436w(0) AND wire_nl1000i_w_lg_n1l01lO4437w(0); + wire_nl1000i_w_lg_w_lg_w29761w29763w29765w(0) <= wire_nl1000i_w_lg_w29761w29763w(0) AND wire_nl1000i_w_lg_nlO0lil0i29764w(0); + wire_nl1000i_w2361w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w_lg_niOiO1i2353w2355w2357w2359w(0) AND wire_nl1000i_w_lg_niOilll2360w(0); + wire_nl1000i_w_lg_w36974w36975w(0) <= wire_nl1000i_w36974w(0) AND nlli1OiOO; + wire_nl1000i_w4436w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w_lg_n1l001l4428w4430w4432w4434w(0) AND wire_nl1000i_w_lg_n1l01Oi4435w(0); + wire_nl1000i_w_lg_w36257w36258w(0) <= wire_nl1000i_w36257w(0) AND nll0O0iOl; + wire_nl1000i_w_lg_w29761w29763w(0) <= wire_nl1000i_w29761w(0) AND wire_nl1000i_w_lg_nlO0lil0l29762w(0); + wire_nl1000i_w_lg_w29780w29785w(0) <= wire_nl1000i_w29780w(0) AND nlOi1OiOl; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_niOiO1i2353w2355w2357w2359w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_niOiO1i2353w2355w2357w(0) AND wire_nl1000i_w_lg_niOillO2358w(0); + wire_nl1000i_w36974w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlli1Ol0l36971w36972w36973w(0) AND nlli1Ol1i; + wire_nl1000i_w4665w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nllliili4655w4656w4659w4662w(0) AND wire_nl1000i_w_lg_w_lg_nllliiOi4663w4664w(0); + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_n1l001l4428w4430w4432w4434w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_n1l001l4428w4430w4432w(0) AND wire_nl1000i_w_lg_n1l01Ol4433w(0); + wire_nl1000i_w59027w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59018w(0) AND niOOi1iOi; + wire_nl1000i_w59044w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59041w(0) AND niOOi1iOi; + wire_nl1000i_w59024w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59023w(0) AND niOOi1iOi; + wire_nl1000i_w59048w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59035w(0) AND niOOi1iOi; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w9921w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w(0) AND nlillOi0i; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w9914w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w(0) AND nlillOi0i; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w9908w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w(0) AND nlillOi0i; + wire_nl1000i_w36257w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nll0O0i0O36253w36255w36256w(0) AND wire_nlOiOi11i_w_lg_dataout36238w(0); + wire_nl1000i_w29761w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlO0liliO29755w29757w29759w(0) AND wire_nl1000i_w_lg_nlO0lil0O29760w(0); + wire_nl1000i_w29780w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlOi1Ol1O29650w29652w29779w(0) AND wire_nl1000i_w_lg_nlOi1OiOO29159w(0); + wire_nl1000i_w60343w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlOiilii60339w60341w60342w(0) AND nlOiil0i; + wire_nl1000i_w59696w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nlOil0OO59692w59693w59695w(0) AND nlOil0lO; + wire_nl1000i_w_lg_w_lg_w_lg_niOiO1i2353w2355w2357w(0) <= wire_nl1000i_w_lg_w_lg_niOiO1i2353w2355w(0) AND wire_nl1000i_w_lg_niOilOi2356w(0); + wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59038w59039w(0) <= wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59038w(0) AND niOOi1iOi; + wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59030w59031w59050w(0) <= wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59031w(0) AND niOOi1iOi; + wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9896w9900w(0) <= wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w(0) AND nlillOi0i; + wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9889w9890w9894w(0) <= wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w(0) AND nlillOi0i; + wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9882w9886w(0) <= wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w(0) AND nlillOi0i; + wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9872w9873w9879w(0) <= wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w(0) AND nlillOi0i; + wire_nl1000i_w_lg_w_lg_w_lg_nll0Oii1l5332w5333w5334w(0) <= wire_nl1000i_w_lg_w_lg_nll0Oii1l5332w5333w(0) AND niOO01iiO; + wire_nl1000i_w_lg_w_lg_w_lg_nlli1Ol0l36971w36972w36973w(0) <= wire_nl1000i_w_lg_w_lg_nlli1Ol0l36971w36972w(0) AND nlli1Ol1l; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nllliili4655w4656w4659w4662w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nllliili4655w4656w4659w(0) AND wire_nl1000i_w_lg_w_lg_nllliilO4660w4661w(0); + wire_nl1000i_w_lg_w_lg_w_lg_n1l001l4428w4430w4432w(0) <= wire_nl1000i_w_lg_w_lg_n1l001l4428w4430w(0) AND wire_nl1000i_w_lg_n1l01OO4431w(0); + wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59018w(0) <= wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59016w(0) AND wire_nl1000i_w_lg_niOOi1iOl59017w(0); + wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59016w59041w(0) <= wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59016w(0) AND niOOi1iOl; + wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59023w(0) <= wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59022w(0) AND wire_nl1000i_w_lg_niOOi1iOl59017w(0); + wire_nl1000i_w_lg_w_lg_w_lg_niOOi1l1i59014w59022w59035w(0) <= wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59022w(0) AND niOOi1iOl; + wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9916w9917w(0) <= wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) AND nlillOl0i; + wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9910w(0) <= wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9903w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nlillOl0O9902w9903w9904w(0) <= wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9903w(0) AND nlillOl0i; + wire_nl1000i_w_lg_w_lg_w_lg_nll0O0i0i36246w36247w36248w(0) <= wire_nl1000i_w_lg_w_lg_nll0O0i0i36246w36247w(0) AND nll0O0iOl; + wire_nl1000i_w_lg_w_lg_w_lg_nll0O0i0O36253w36255w36256w(0) <= wire_nl1000i_w_lg_w_lg_nll0O0i0O36253w36255w(0) AND wire_nl1000i_w_lg_nll0O0i0i36246w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nllilil0l35858w35860w36926w(0) <= wire_nl1000i_w_lg_w_lg_nllilil0l35858w35860w(0) AND nllilil1O; + wire_nl1000i_w_lg_w_lg_w_lg_nlliO11l5089w5106w5107w(0) <= wire_nl1000i_w_lg_w_lg_nlliO11l5089w5106w(0) AND niOO01lli; + wire_nl1000i_w_lg_w_lg_w_lg_nlO0liliO29755w29757w29759w(0) <= wire_nl1000i_w_lg_w_lg_nlO0liliO29755w29757w(0) AND wire_nl1000i_w_lg_nlO0lilii29758w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nlOi1Ol1O29650w29652w29779w(0) <= wire_nl1000i_w_lg_w_lg_nlOi1Ol1O29650w29652w(0) AND wire_nl1000i_w_lg_nlOi1Ol1i29713w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nlOiilii60339w60341w60342w(0) <= wire_nl1000i_w_lg_w_lg_nlOiilii60339w60341w(0) AND nlOiil0l; + wire_nl1000i_w_lg_w_lg_w_lg_nlOil0OO59692w60307w60313w(0) <= wire_nl1000i_w_lg_w_lg_nlOil0OO59692w60307w(0) AND nlOil0Oi; + wire_nl1000i_w_lg_w_lg_w_lg_nlOil0OO59692w59693w59695w(0) <= wire_nl1000i_w_lg_w_lg_nlOil0OO59692w59693w(0) AND wire_nl1000i_w_lg_nlOil0Oi59694w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nlOili1l60355w60356w60357w(0) <= wire_nl1000i_w_lg_w_lg_nlOili1l60355w60356w(0) AND nlOil0OO; + wire_nl1000i_w_lg_w_lg_n1l01ii4073w4076w(0) <= wire_nl1000i_w_lg_n1l01ii4073w(0) AND wire_nl1000i_w_lg_w_lg_n1l00ii4074w4075w(0); + wire_nl1000i_w_lg_w_lg_niOiO1i2353w2355w(0) <= wire_nl1000i_w_lg_niOiO1i2353w(0) AND wire_nl1000i_w_lg_niOilOl2354w(0); + wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59038w(0) <= wire_nl1000i_w_lg_niOOi1l1i59030w(0) AND wire_nl1000i_w_lg_niOOi1iOl59017w(0); + wire_nl1000i_w_lg_w_lg_niOOi1l1i59030w59031w(0) <= wire_nl1000i_w_lg_niOOi1l1i59030w(0) AND niOOi1iOl; + wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9896w(0) <= wire_nl1000i_w_lg_nlillOl0O9889w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0); + wire_nl1000i_w_lg_w_lg_nlillOl0O9889w9890w(0) <= wire_nl1000i_w_lg_nlillOl0O9889w(0) AND nlillOl0i; + wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9882w(0) <= wire_nl1000i_w_lg_nlillOl0O9872w(0) AND wire_nl1000i_w_lg_nlillOl0i9881w(0); + wire_nl1000i_w_lg_w_lg_nlillOl0O9872w9873w(0) <= wire_nl1000i_w_lg_nlillOl0O9872w(0) AND nlillOl0i; + wire_nl1000i_w_lg_w_lg_nll0Oii1l5332w5333w(0) <= wire_nl1000i_w_lg_nll0Oii1l5332w(0) AND niOO010OO; + wire_nl1000i_w_lg_w_lg_nlli0iO1i36270w36271w(0) <= wire_nl1000i_w_lg_nlli0iO1i36270w(0) AND wire_nll0O0i1i_o; + wire_nl1000i_w_lg_w_lg_nlli1Ol0l36971w36972w(0) <= wire_nl1000i_w_lg_nlli1Ol0l36971w(0) AND nlli1Ol1O; + wire_nl1000i_w_lg_w_lg_nlliliiOO35871w35872w(0) <= wire_nl1000i_w_lg_nlliliiOO35871w(0) AND nlliliiOi; + wire_nl1000i_w_lg_w_lg_nlliO11i5102w5103w(0) <= wire_nl1000i_w_lg_nlliO11i5102w(0) AND nlliO11l; + wire_nl1000i_w_lg_w_lg_nlOil0OO59701w59702w(0) <= wire_nl1000i_w_lg_nlOil0OO59701w(0) AND nlOili1i; + wire_nl1000i_w_lg_w_lg_w_lg_nllliili4655w4656w4659w(0) <= wire_nl1000i_w_lg_w_lg_nllliili4655w4656w(0) AND wire_nl1000i_w_lg_w_lg_nllliill4657w4658w(0); + wire_nl1000i_w_lg_w_lg_n1l000l4101w4316w(0) <= wire_nl1000i_w_lg_n1l000l4101w(0) AND n1l010O; + wire_nl1000i_w_lg_w_lg_n1l001l4428w4430w(0) <= wire_nl1000i_w_lg_n1l001l4428w(0) AND wire_nl1000i_w_lg_n1l001i4429w(0); + wire_nl1000i_w_lg_w_lg_niiiOOO2312w2313w(0) <= wire_nl1000i_w_lg_niiiOOO2312w(0) AND niOi00lO; + wire_nl1000i_w_lg_w_lg_niOi01l2310w2311w(0) <= wire_nl1000i_w_lg_niOi01l2310w(0) AND niOi00Oi; + wire_nl1000i_w_lg_w_lg_niOOi01il42910w42911w(0) <= wire_nl1000i_w_lg_niOOi01il42910w(0) AND wire_nilOi0li_dataout; + wire_nl1000i_w_lg_w_lg_niOOi01il42910w53644w(0) <= wire_nl1000i_w_lg_niOOi01il42910w(0) AND niOi0001i; + wire_nl1000i_w_lg_w_lg_niOOi01il42910w53331w(0) <= wire_nl1000i_w_lg_niOOi01il42910w(0) AND niOi00l1i; + wire_nl1000i_w_lg_w_lg_niOOi01il42910w53329w(0) <= wire_nl1000i_w_lg_niOOi01il42910w(0) AND niOi00l1l; + wire_nl1000i_w_lg_w_lg_niOOi1i0i35846w35847w(0) <= wire_nl1000i_w_lg_niOOi1i0i35846w(0) AND niOOi1i1O; + wire_nl1000i_w_lg_w_lg_niOOi1i1i44005w48206w(0) <= wire_nl1000i_w_lg_niOOi1i1i44005w(0) AND nl0iOiiOO; + wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36216w(0) <= wire_nl1000i_w_lg_niOOi1i1l36191w(0) AND wire_w_lg_niOiOi1Oi36215w(0); + wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36208w(0) <= wire_nl1000i_w_lg_niOOi1i1l36191w(0) AND wire_w_lg_niOiOi1Ol36207w(0); + wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36200w(0) <= wire_nl1000i_w_lg_niOOi1i1l36191w(0) AND niOiOi1li; + wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36198w(0) <= wire_nl1000i_w_lg_niOOi1i1l36191w(0) AND niOiOi1ll; + wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36194w(0) <= wire_nl1000i_w_lg_niOOi1i1l36191w(0) AND niOiOi1Oi; + wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36192w(0) <= wire_nl1000i_w_lg_niOOi1i1l36191w(0) AND niOiOi1Ol; + wire_nl1000i_w_lg_w_lg_niOOi1ill29013w29014w(0) <= wire_nl1000i_w_lg_niOOi1ill29013w(0) AND niOOi1ili; + wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59016w(0) <= wire_nl1000i_w_lg_niOOi1l1i59014w(0) AND wire_nl1000i_w_lg_niOOi1iOO59015w(0); + wire_nl1000i_w_lg_w_lg_niOOi1l1i59014w59022w(0) <= wire_nl1000i_w_lg_niOOi1l1i59014w(0) AND niOOi1iOO; + wire_nl1000i_w_lg_w_lg_niOOOil1058w1059w(0) <= wire_nl1000i_w_lg_niOOOil1058w(0) AND niO0OOOl; + wire_nl1000i_w_lg_w_lg_nlilliiOi42828w42829w(0) <= wire_nl1000i_w_lg_nlilliiOi42828w(0) AND niOiO1llO; + wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9916w(0) <= wire_nl1000i_w_lg_nlillOl0O9902w(0) AND wire_nl1000i_w_lg_nlillOl0l9888w(0); + wire_nl1000i_w_lg_w_lg_nlillOl0O9902w9903w(0) <= wire_nl1000i_w_lg_nlillOl0O9902w(0) AND nlillOl0l; + wire_nl1000i_w_lg_w_lg_nll0O0i0i36246w36247w(0) <= wire_nl1000i_w_lg_nll0O0i0i36246w(0) AND wire_nlOiOi11i_w_lg_dataout36238w(0); + wire_nl1000i_w_lg_w_lg_nll0O0i0O36253w36255w(0) <= wire_nl1000i_w_lg_nll0O0i0O36253w(0) AND wire_nl1000i_w_lg_nll0O0i0l36254w(0); + wire_nl1000i_w_lg_w_lg_nll0O0iOl5342w5660w(0) <= wire_nl1000i_w_lg_nll0O0iOl5342w(0) AND wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w5659w(0); + wire_nl1000i_w_lg_w_lg_nll0O0iOl5342w5600w(0) <= wire_nl1000i_w_lg_nll0O0iOl5342w(0) AND nll0OiiO; + wire_nl1000i_w_lg_w_lg_nll0Oi0iO5948w5954w(0) <= wire_nl1000i_w_lg_nll0Oi0iO5948w(0) AND nll0Oi0il; + wire_nl1000i_w_lg_w_lg_nll0Oii1l5335w5338w(0) <= wire_nl1000i_w_lg_nll0Oii1l5335w(0) AND wire_nl1000i_w_lg_nll0Oii1i5265w(0); + wire_nl1000i_w_lg_w_lg_nll0Oii1l5335w5336w(0) <= wire_nl1000i_w_lg_nll0Oii1l5335w(0) AND niOO01iiO; + wire_nl1000i_w_lg_w_lg_nll0OilO5675w5676w(0) <= wire_nl1000i_w_lg_nll0OilO5675w(0) AND nll0Oiil; + wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w5678w(0) <= wire_nl1000i_w_lg_nlli0ilOO5658w(0) AND wire_w_lg_niOO010li5677w(0); + wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w5659w(0) <= wire_nl1000i_w_lg_nlli0ilOO5658w(0) AND niOO01i1O; + wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w36235w(0) <= wire_nl1000i_w_lg_nlli0ilOO5658w(0) AND nll0O0ilO; + wire_nl1000i_w_lg_w_lg_nllilil0l35858w35860w(0) <= wire_nl1000i_w_lg_nllilil0l35858w(0) AND wire_nl1000i_w_lg_nllilil0i35859w(0); + wire_nl1000i_w_lg_w_lg_nllilO1i5110w5747w(0) <= wire_nl1000i_w_lg_nllilO1i5110w(0) AND wire_nl1000i_w_lg_nlliO01i5746w(0); + wire_nl1000i_w_lg_w_lg_nllilO1i5110w5743w(0) <= wire_nl1000i_w_lg_nllilO1i5110w(0) AND wire_nl1000i_w_lg_nlliO11l5742w(0); + wire_nl1000i_w_lg_w_lg_nllilO1i5110w5706w(0) <= wire_nl1000i_w_lg_nllilO1i5110w(0) AND niOO01lli; + wire_nl1000i_w_lg_w_lg_nllilOlOi35909w35910w(0) <= wire_nl1000i_w_lg_nllilOlOi35909w(0) AND wire_nl1000i_w_lg_nlli0iO1O35900w(0); + wire_nl1000i_w_lg_w_lg_nlliO11i5100w5701w(0) <= wire_nl1000i_w_lg_nlliO11i5100w(0) AND wire_nl1000i_w_lg_nllilO1i5110w(0); + wire_nl1000i_w_lg_w_lg_nlliO11l5089w5726w(0) <= wire_nl1000i_w_lg_nlliO11l5089w(0) AND wire_nl1000i_w_lg_nlliO11i5692w(0); + wire_nl1000i_w_lg_w_lg_nlliO11l5089w5106w(0) <= wire_nl1000i_w_lg_nlliO11l5089w(0) AND nlliO11i; + wire_nl1000i_w_lg_w_lg_nlliO11O5108w5714w(0) <= wire_nl1000i_w_lg_nlliO11O5108w(0) AND niOO011li; + wire_nl1000i_w_lg_w_lg_nlliO11O5108w5109w(0) <= wire_nl1000i_w_lg_nlliO11O5108w(0) AND nllilO1i; + wire_nl1000i_w_lg_w_lg_nlO0liliO29755w29757w(0) <= wire_nl1000i_w_lg_nlO0liliO29755w(0) AND wire_nl1000i_w_lg_nlO0lilil29756w(0); + wire_nl1000i_w_lg_w_lg_nlOi1Ol1O29650w29652w(0) <= wire_nl1000i_w_lg_nlOi1Ol1O29650w(0) AND wire_nl1000i_w_lg_nlOi1Ol1l29651w(0); + wire_nl1000i_w_lg_w_lg_nlOiilii60339w60341w(0) <= wire_nl1000i_w_lg_nlOiilii60339w(0) AND wire_nl1000i_w_lg_nlOiil0O60340w(0); + wire_nl1000i_w_lg_w_lg_nlOil0OO59692w60307w(0) <= wire_nl1000i_w_lg_nlOil0OO59692w(0) AND wire_nl1000i_w_lg_nlOil0Ol59700w(0); + wire_nl1000i_w_lg_w_lg_nlOil0OO59692w59693w(0) <= wire_nl1000i_w_lg_nlOil0OO59692w(0) AND nlOil0Ol; + wire_nl1000i_w_lg_w_lg_nlOil11O59625w59627w(0) <= wire_nl1000i_w_lg_nlOil11O59625w(0) AND wire_nl1000i_w_lg_nlOil11l59626w(0); + wire_nl1000i_w_lg_w_lg_nlOili1l60355w60356w(0) <= wire_nl1000i_w_lg_nlOili1l60355w(0) AND nlOili1i; + wire_nl1000i_w_lg_w_lg_w_lg_n1l000l4315w4317w4318w(0) <= wire_nl1000i_w_lg_w_lg_n1l000l4315w4317w(0) AND niOO00iOi; + wire_nl1000i_w_lg_w_lg_w_lg_nlli0ilOO5658w35983w35984w(0) <= wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w35983w(0) AND niOiOi0ll; + wire_nl1000i_w_lg_w_lg_nll0OiiO5649w5650w(0) <= wire_nl1000i_w_lg_nll0OiiO5649w(0) AND wire_nll0O1il_o; + wire_nl1000i_w_lg_n1l000l4315w(0) <= n1l000l AND wire_nl1000i_w_lg_n1l010O4314w(0); + wire_nl1000i_w_lg_n1l000O4102w(0) <= n1l000O AND wire_nl1000i_w_lg_n1l000l4101w(0); + wire_nl1000i_w_lg_n1l001O4298w(0) <= n1l001O AND wire_nl1000i_w_lg_nlO0OOOO4297w(0); + wire_nl1000i_w_lg_n1l011i4082w(0) <= n1l011i AND wire_nlll0lli_w_q_range4067w(0); + wire_nl1000i_w_lg_n1l011i4080w(0) <= n1l011i AND wire_nlll0lli_w_q_range4070w(0); + wire_nl1000i_w_lg_n1l011l4303w(0) <= n1l011l AND wire_nl1000i_w_lg_n1l00ii4302w(0); + wire_nl1000i_w_lg_n1l01ii4073w(0) <= n1l01ii AND n1l011l; + wire_nl1000i_w_lg_n1l01ii4078w(0) <= n1l01ii AND nlOiliii; + wire_nl1000i_w_lg_niOiO1i2353w(0) <= niOiO1i AND wire_nl1000i_w_lg_niOilOO2352w(0); + wire_nl1000i_w_lg_niOOi1i0i35850w(0) <= niOOi1i0i AND wire_nl1000i_w_lg_niOOi1i1O35849w(0); + wire_nl1000i_w_lg_niOOi1i0i35853w(0) <= niOOi1i0i AND niOOi1i1O; + wire_nl1000i_w_lg_niOOi1iii34492w(0) <= niOOi1iii AND wire_nl1000i_w_lg_niOOi1i0O34491w(0); + wire_nl1000i_w_lg_niOOi1ill29017w(0) <= niOOi1ill AND wire_nl1000i_w_lg_niOOi1ili29016w(0); + wire_nl1000i_w_lg_niOOi1l1i59030w(0) <= niOOi1l1i AND wire_nl1000i_w_lg_niOOi1iOO59015w(0); + wire_nl1000i_w_lg_niOOOil1061w(0) <= niOOOil AND wire_nl1000i_w_lg_niO0OOOl1060w(0); + wire_nl1000i_w_lg_nlillOl0O9889w(0) <= nlillOl0O AND wire_nl1000i_w_lg_nlillOl0l9888w(0); + wire_nl1000i_w_lg_nlillOl0O9872w(0) <= nlillOl0O AND nlillOl0l; + wire_nl1000i_w_lg_nlilOO0li42249w(0) <= nlilOO0li AND wire_niO1110i_w_lg_dataout42248w(0); + wire_nl1000i_w_lg_nll0O0iOi5672w(0) <= nll0O0iOi AND wire_w5671w(0); + wire_nl1000i_w_lg_nll0O0iOl5613w(0) <= nll0O0iOl AND wire_w_lg_w_k_hip_range2413w5612w(0); + wire_nl1000i_w_lg_nll0O0iOl36239w(0) <= nll0O0iOl AND wire_nlOiOi11i_w_lg_dataout36238w(0); + wire_nl1000i_w_lg_nll0O0iOl5601w(0) <= nll0O0iOl AND nll0OiiO; + wire_nl1000i_w_lg_nll0Oi0iO5957w(0) <= nll0Oi0iO AND wire_nl1000i_w_lg_nll0Oi0il5949w(0); + wire_nl1000i_w_lg_nll0Oii1l5332w(0) <= nll0Oii1l AND wire_nl1000i_w_lg_nll0Oii1i5265w(0); + wire_nl1000i_w_lg_nll0Oiii5609w(0) <= nll0Oiii AND niOO010li; + wire_nl1000i_w_lg_nll0Oili5651w(0) <= nll0Oili AND nll0Oiii; + wire_nl1000i_w_lg_nll0OiOl5607w(0) <= nll0OiOl AND wire_w_lg_w_k_hip_range2413w5606w(0); + wire_nl1000i_w_lg_nlli0i01i36199w(0) <= nlli0i01i AND wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36198w(0); + wire_nl1000i_w_lg_nlli0i01i36177w(0) <= nlli0i01i AND wire_w_lg_niOiOi00i36176w(0); + wire_nl1000i_w_lg_nlli0i01i36186w(0) <= nlli0i01i AND wire_nl1000i_w_lg_nlli1100O36185w(0); + wire_nl1000i_w_lg_nlli0i01i36206w(0) <= nlli0i01i AND wire_nl1000i_w_lg_niOOi1i1l36205w(0); + wire_nl1000i_w_lg_nlli0i1Oi36217w(0) <= nlli0i1Oi AND wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36216w(0); + wire_nl1000i_w_lg_nlli0i1Oi36195w(0) <= nlli0i1Oi AND wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36194w(0); + wire_nl1000i_w_lg_nlli0i1Ol36209w(0) <= nlli0i1Ol AND wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36208w(0); + wire_nl1000i_w_lg_nlli0i1Ol36193w(0) <= nlli0i1Ol AND wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36192w(0); + wire_nl1000i_w_lg_nlli0i1OO36201w(0) <= nlli0i1OO AND wire_nl1000i_w_lg_w_lg_niOOi1i1l36191w36200w(0); + wire_nl1000i_w_lg_nlli0i1OO36179w(0) <= nlli0i1OO AND wire_w_lg_niOiOi01O36178w(0); + wire_nl1000i_w_lg_nlli0i1OO36188w(0) <= nlli0i1OO AND wire_w_lg_niOiOi1OO36187w(0); + wire_nl1000i_w_lg_nlli0i1OO36214w(0) <= nlli0i1OO AND wire_nl1000i_w_lg_niOOi1i1l36213w(0); + wire_nl1000i_w_lg_nlli0iliO35933w(0) <= nlli0iliO AND nlli0iili; + wire_nl1000i_w_lg_nlli0illi35932w(0) <= nlli0illi AND nlli0iili; + wire_nl1000i_w_lg_nlli0ilOO35986w(0) <= nlli0ilOO AND wire_w_lg_niOiOi0li35985w(0); + wire_nl1000i_w_lg_nlli0iO1i36270w(0) <= nlli0iO1i AND nlli0illi; + wire_nl1000i_w_lg_nlli0iO1l36184w(0) <= nlli0iO1l AND wire_niO1110O_w_lg_dataout36183w(0); + wire_nl1000i_w_lg_nlli0iO1l36221w(0) <= nlli0iO1l AND wire_nl1000i_w_lg_w_lg_nlli0i1lO36211w36220w(0); + wire_nl1000i_w_lg_nlli1Ol0l36971w(0) <= nlli1Ol0l AND nlli1Ol0i; + wire_nl1000i_w_lg_nlliiilii42785w(0) <= nlliiilii AND wire_nl1000i_w_lg_nlliiil0O42784w(0); + wire_nl1000i_w_lg_nlliliiOO35871w(0) <= nlliliiOO AND wire_nl1000i_w_lg_nlliliiOl35866w(0); + wire_nl1000i_w_lg_nllillOl5686w(0) <= nllillOl AND wire_nlill0Oll_w_lg_w_lg_nl1OilOii5684w5685w(0); + wire_nl1000i_w_lg_nllillOl5080w(0) <= nllillOl AND nli1i1ll; + wire_nl1000i_w_lg_nllilO1i5749w(0) <= nllilO1i AND wire_nl1000i_w_lg_nlliO01i5746w(0); + wire_nl1000i_w_lg_nllilOlOi35917w(0) <= nllilOlOi AND wire_w_lg_w_lg_niOiOiliO35913w35916w(0); + wire_nl1000i_w_lg_nlliO01i5746w(0) <= nlliO01i AND wire_nl1000i_w_lg_nlliO11i5100w(0); + wire_nl1000i_w_lg_nlliO01i5728w(0) <= nlliO01i AND wire_nl1000i_w_lg_w_lg_w_lg_nlliO11i5100w5701w5727w(0); + wire_nl1000i_w_lg_nlliO01i5741w(0) <= nlliO01i AND niOO1OOiO; + wire_nl1000i_w_lg_nlliO01i5704w(0) <= nlliO01i AND nlliO11l; + wire_nl1000i_w_lg_nlliO10i5226w(0) <= nlliO10i AND wire_w_lg_w_lg_w_k_hip_range2413w2429w5225w(0); + wire_nl1000i_w_lg_nlliO11i5102w(0) <= nlliO11i AND niOO01lli; + wire_nl1000i_w_lg_nlliO11l5751w(0) <= nlliO11l AND wire_nlll0liO_w_lg_dataout5750w(0); + wire_nl1000i_w_lg_nlliO11l5742w(0) <= nlliO11l AND wire_nl1000i_w_lg_nlliO01i5741w(0); + wire_nl1000i_w_lg_nllli1il4681w(0) <= nllli1il AND nllli1ii; + wire_nl1000i_w_lg_nlOi1OiOl29018w(0) <= nlOi1OiOl AND wire_nl1000i_w_lg_niOOi1ill29017w(0); + wire_nl1000i_w_lg_nlOil0OO59701w(0) <= nlOil0OO AND wire_nl1000i_w_lg_nlOil0Ol59700w(0); + wire_nl1000i_w_lg_nlOili0l4040w(0) <= nlOili0l AND wire_nl1000i_w_lg_nlOili0i4039w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nlliliiOO35871w35872w35873w(0) <= NOT wire_nl1000i_w_lg_w_lg_nlliliiOO35871w35872w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nlOil11O59625w59627w59628w(0) <= NOT wire_nl1000i_w_lg_w_lg_nlOil11O59625w59627w(0); + wire_nl1000i_w_lg_w_lg_nllillOl5080w6320w(0) <= NOT wire_nl1000i_w_lg_nllillOl5080w(0); + wire_nl1000i_w_lg_w_lg_nllliili4655w4656w(0) <= NOT wire_nl1000i_w_lg_nllliili4655w(0); + wire_nl1000i_w_lg_w_lg_nllliill4657w4658w(0) <= NOT wire_nl1000i_w_lg_nllliill4657w(0); + wire_nl1000i_w_lg_w_lg_nllliilO4660w4661w(0) <= NOT wire_nl1000i_w_lg_nllliilO4660w(0); + wire_nl1000i_w_lg_w_lg_nllliiOi4663w4664w(0) <= NOT wire_nl1000i_w_lg_nllliiOi4663w(0); + wire_nl1000i_w_lg_n1l000l4101w(0) <= NOT n1l000l; + wire_nl1000i_w_lg_n1l000O4060w(0) <= NOT n1l000O; + wire_nl1000i_w_lg_n1l001i4429w(0) <= NOT n1l001i; + wire_nl1000i_w_lg_n1l001l4428w(0) <= NOT n1l001l; + wire_nl1000i_w_lg_n1l00ii4074w(0) <= NOT n1l00ii; + wire_nl1000i_w_lg_n1l010i4042w(0) <= NOT n1l010i; + wire_nl1000i_w_lg_n1l010l4099w(0) <= NOT n1l010l; + wire_nl1000i_w_lg_n1l010O4314w(0) <= NOT n1l010O; + wire_nl1000i_w_lg_n1l01il4447w(0) <= NOT n1l01il; + wire_nl1000i_w_lg_n1l01iO4443w(0) <= NOT n1l01iO; + wire_nl1000i_w_lg_n1l01li4441w(0) <= NOT n1l01li; + wire_nl1000i_w_lg_n1l01ll4439w(0) <= NOT n1l01ll; + wire_nl1000i_w_lg_n1l01lO4437w(0) <= NOT n1l01lO; + wire_nl1000i_w_lg_n1l01Oi4435w(0) <= NOT n1l01Oi; + wire_nl1000i_w_lg_n1l01Ol4433w(0) <= NOT n1l01Ol; + wire_nl1000i_w_lg_n1l01OO4431w(0) <= NOT n1l01OO; + wire_nl1000i_w_lg_ni001Ol2342w(0) <= NOT ni001Ol; + wire_nl1000i_w_lg_ni00ilO2338w(0) <= NOT ni00ilO; + wire_nl1000i_w_lg_ni0i0OO2344w(0) <= NOT ni0i0OO; + wire_nl1000i_w_lg_ni0l0il2336w(0) <= NOT ni0l0il; + wire_nl1000i_w_lg_ni0lO1i2326w(0) <= NOT ni0lO1i; + wire_nl1000i_w_lg_ni0O1iO2324w(0) <= NOT ni0O1iO; + wire_nl1000i_w_lg_niiiOOO2312w(0) <= NOT niiiOOO; + wire_nl1000i_w_lg_niO0l0li8755w(0) <= NOT niO0l0li; + wire_nl1000i_w_lg_niO0OOOl1060w(0) <= NOT niO0OOOl; + wire_nl1000i_w_lg_niOi01l2310w(0) <= NOT niOi01l; + wire_nl1000i_w_lg_niOil0l2369w(0) <= NOT niOil0l; + wire_nl1000i_w_lg_niOil0O2367w(0) <= NOT niOil0O; + wire_nl1000i_w_lg_niOilii2376w(0) <= NOT niOilii; + wire_nl1000i_w_lg_niOilil2374w(0) <= NOT niOilil; + wire_nl1000i_w_lg_niOiliO2372w(0) <= NOT niOiliO; + wire_nl1000i_w_lg_niOilli2362w(0) <= NOT niOilli; + wire_nl1000i_w_lg_niOilll2360w(0) <= NOT niOilll; + wire_nl1000i_w_lg_niOillO2358w(0) <= NOT niOillO; + wire_nl1000i_w_lg_niOilOi2356w(0) <= NOT niOilOi; + wire_nl1000i_w_lg_niOilOl2354w(0) <= NOT niOilOl; + wire_nl1000i_w_lg_niOilOO2352w(0) <= NOT niOilOO; + wire_nl1000i_w_lg_niOlOill8545w(0) <= NOT niOlOill; + wire_nl1000i_w_lg_niOO001i44257w(0) <= NOT niOO001i; + wire_nl1000i_w_lg_niOO010O44258w(0) <= NOT niOO010O; + wire_nl1000i_w_lg_niOO0ili46420w(0) <= NOT niOO0ili; + wire_nl1000i_w_lg_niOO0liO8485w(0) <= NOT niOO0liO; + wire_nl1000i_w_lg_niOO1i0i45522w(0) <= NOT niOO1i0i; + wire_nl1000i_w_lg_niOOi01il42910w(0) <= NOT niOOi01il; + wire_nl1000i_w_lg_niOOi0li8471w(0) <= NOT niOOi0li; + wire_nl1000i_w_lg_niOOi11l8478w(0) <= NOT niOOi11l; + wire_nl1000i_w_lg_niOOi1i0i35846w(0) <= NOT niOOi1i0i; + wire_nl1000i_w_lg_niOOi1i0O34491w(0) <= NOT niOOi1i0O; + wire_nl1000i_w_lg_niOOi1i1i44005w(0) <= NOT niOOi1i1i; + wire_nl1000i_w_lg_niOOi1i1l36191w(0) <= NOT niOOi1i1l; + wire_nl1000i_w_lg_niOOi1i1O35849w(0) <= NOT niOOi1i1O; + wire_nl1000i_w_lg_niOOi1iii34557w(0) <= NOT niOOi1iii; + wire_nl1000i_w_lg_niOOi1ili29016w(0) <= NOT niOOi1ili; + wire_nl1000i_w_lg_niOOi1ill29013w(0) <= NOT niOOi1ill; + wire_nl1000i_w_lg_niOOi1ilO59025w(0) <= NOT niOOi1ilO; + wire_nl1000i_w_lg_niOOi1iOi59019w(0) <= NOT niOOi1iOi; + wire_nl1000i_w_lg_niOOi1iOl59017w(0) <= NOT niOOi1iOl; + wire_nl1000i_w_lg_niOOi1iOO59015w(0) <= NOT niOOi1iOO; + wire_nl1000i_w_lg_niOOi1l1i59014w(0) <= NOT niOOi1l1i; + wire_nl1000i_w_lg_niOOil0i46311w(0) <= NOT niOOil0i; + wire_nl1000i_w_lg_niOOil0l46309w(0) <= NOT niOOil0l; + wire_nl1000i_w_lg_niOOil0O46308w(0) <= NOT niOOil0O; + wire_nl1000i_w_lg_niOOilii46307w(0) <= NOT niOOilii; + wire_nl1000i_w_lg_niOOilil46306w(0) <= NOT niOOilil; + wire_nl1000i_w_lg_niOOiliO46305w(0) <= NOT niOOiliO; + wire_nl1000i_w_lg_niOOilli46304w(0) <= NOT niOOilli; + wire_nl1000i_w_lg_niOOilll46303w(0) <= NOT niOOilll; + wire_nl1000i_w_lg_niOOillO46302w(0) <= NOT niOOillO; + wire_nl1000i_w_lg_niOOilOi46364w(0) <= NOT niOOilOi; + wire_nl1000i_w_lg_niOOl1il46312w(0) <= NOT niOOl1il; + wire_nl1000i_w_lg_niOOllOO8420w(0) <= NOT niOOllOO; + wire_nl1000i_w_lg_niOOO1OO8409w(0) <= NOT niOOO1OO; + wire_nl1000i_w_lg_niOOOi1i8406w(0) <= NOT niOOOi1i; + wire_nl1000i_w_lg_niOOOil1058w(0) <= NOT niOOOil; + wire_nl1000i_w_lg_niOOOOiO8394w(0) <= NOT niOOOOiO; + wire_nl1000i_w_lg_nl00ilOO7356w(0) <= NOT nl00ilOO; + wire_nl1000i_w_lg_nl00Olll7232w(0) <= NOT nl00Olll; + wire_nl1000i_w_lg_nl01i0OO7558w(0) <= NOT nl01i0OO; + wire_nl1000i_w_lg_nl01i1ii7565w(0) <= NOT nl01i1ii; + wire_nl1000i_w_lg_nl01Olli7360w(0) <= NOT nl01Olli; + wire_nl1000i_w_lg_nl0iiO1i7228w(0) <= NOT nl0iiO1i; + wire_nl1000i_w_lg_nl0OiO0O6419w(0) <= NOT nl0OiO0O; + wire_nl1000i_w_lg_nl0OlOOl6384w(0) <= NOT nl0OlOOl; + wire_nl1000i_w_lg_nl0OO1li6393w(0) <= NOT nl0OO1li; + wire_nl1000i_w_lg_nl0OO1ll6391w(0) <= NOT nl0OO1ll; + wire_nl1000i_w_lg_nl0OO1lO6389w(0) <= NOT nl0OO1lO; + wire_nl1000i_w_lg_nl0OO1Oi6388w(0) <= NOT nl0OO1Oi; + wire_nl1000i_w_lg_nl0OOOlO6364w(0) <= NOT nl0OOOlO; + wire_nl1000i_w_lg_nl100O0i44666w(0) <= NOT nl100O0i; + wire_nl1000i_w_lg_nl100O0l44665w(0) <= NOT nl100O0l; + wire_nl1000i_w_lg_nl100O0O44664w(0) <= NOT nl100O0O; + wire_nl1000i_w_lg_nl100O1O44667w(0) <= NOT nl100O1O; + wire_nl1000i_w_lg_nl1011li8265w(0) <= NOT nl1011li; + wire_nl1000i_w_lg_nl101ili8254w(0) <= NOT nl101ili; + wire_nl1000i_w_lg_nl10i10i44668w(0) <= NOT nl10i10i; + wire_nl1000i_w_lg_nl10iili46322w(0) <= NOT nl10iili; + wire_nl1000i_w_lg_nl10iill46321w(0) <= NOT nl10iill; + wire_nl1000i_w_lg_nl10iilO46320w(0) <= NOT nl10iilO; + wire_nl1000i_w_lg_nl10iiOi46319w(0) <= NOT nl10iiOi; + wire_nl1000i_w_lg_nl10illl46323w(0) <= NOT nl10illl; + wire_nl1000i_w_lg_nl1101ll8363w(0) <= NOT nl1101ll; + wire_nl1000i_w_lg_nl110i0i8355w(0) <= NOT nl110i0i; + wire_nl1000i_w_lg_nl110llO8347w(0) <= NOT nl110llO; + wire_nl1000i_w_lg_nl11101l8386w(0) <= NOT nl11101l; + wire_nl1000i_w_lg_nl111ili8378w(0) <= NOT nl111ili; + wire_nl1000i_w_lg_nl111Oll8366w(0) <= NOT nl111Oll; + wire_nl1000i_w_lg_nl11i0Oi8331w(0) <= NOT nl11i0Oi; + wire_nl1000i_w_lg_nl11i10l8339w(0) <= NOT nl11i10l; + wire_nl1000i_w_lg_nl11il0O8323w(0) <= NOT nl11il0O; + wire_nl1000i_w_lg_nl11ilO2143w(0) <= NOT nl11ilO; + wire_nl1000i_w_lg_nl11iOi2246w(0) <= NOT nl11iOi; + wire_nl1000i_w_lg_nl11iOl2239w(0) <= NOT nl11iOl; + wire_nl1000i_w_lg_nl11iOO2232w(0) <= NOT nl11iOO; + wire_nl1000i_w_lg_nl11iOOl8315w(0) <= NOT nl11iOOl; + wire_nl1000i_w_lg_nl11l0i2204w(0) <= NOT nl11l0i; + wire_nl1000i_w_lg_nl11l0l2197w(0) <= NOT nl11l0l; + wire_nl1000i_w_lg_nl11l0O2190w(0) <= NOT nl11l0O; + wire_nl1000i_w_lg_nl11l0OO8303w(0) <= NOT nl11l0OO; + wire_nl1000i_w_lg_nl11l1i2225w(0) <= NOT nl11l1i; + wire_nl1000i_w_lg_nl11l1l2218w(0) <= NOT nl11l1l; + wire_nl1000i_w_lg_nl11l1O2211w(0) <= NOT nl11l1O; + wire_nl1000i_w_lg_nl11lii2183w(0) <= NOT nl11lii; + wire_nl1000i_w_lg_nl11lil2176w(0) <= NOT nl11lil; + wire_nl1000i_w_lg_nl11liO2169w(0) <= NOT nl11liO; + wire_nl1000i_w_lg_nl11lli2162w(0) <= NOT nl11lli; + wire_nl1000i_w_lg_nl11llil8296w(0) <= NOT nl11llil; + wire_nl1000i_w_lg_nl11lll2155w(0) <= NOT nl11lll; + wire_nl1000i_w_lg_nl11O0iO8282w(0) <= NOT nl11O0iO; + wire_nl1000i_w_lg_nl11O11i8289w(0) <= NOT nl11O11i; + wire_nl1000i_w_lg_nl11Ol1l8275w(0) <= NOT nl11Ol1l; + wire_nl1000i_w_lg_nl11OOiO8268w(0) <= NOT nl11OOiO; + wire_nl1000i_w_lg_nl1iiilO8010w(0) <= NOT nl1iiilO; + wire_nl1000i_w_lg_nl1iiO0l8003w(0) <= NOT nl1iiO0l; + wire_nl1000i_w_lg_nl1il00l7993w(0) <= NOT nl1il00l; + wire_nl1000i_w_lg_nl1l00Oi7900w(0) <= NOT nl1l00Oi; + wire_nl1000i_w_lg_nl1l010l7907w(0) <= NOT nl1l010l; + wire_nl1000i_w_lg_nl1l0l0O7893w(0) <= NOT nl1l0l0O; + wire_nl1000i_w_lg_nl1l11ll7928w(0) <= NOT nl1l11ll; + wire_nl1000i_w_lg_nl1l1i0i7921w(0) <= NOT nl1l1i0i; + wire_nl1000i_w_lg_nl1l1llO7914w(0) <= NOT nl1l1llO; + wire_nl1000i_w_lg_nl1li00l7877w(0) <= NOT nl1li00l; + wire_nl1000i_w_lg_nl1liOlO7857w(0) <= NOT nl1liOlO; + wire_nl1000i_w_lg_nl1lO11i7822w(0) <= NOT nl1lO11i; + wire_nl1000i_w_lg_nl1lOill7802w(0) <= NOT nl1lOill; + wire_nl1000i_w_lg_nl1O01Ol7758w(0) <= NOT nl1O01Ol; + wire_nl1000i_w_lg_nl1O0iii7750w(0) <= NOT nl1O0iii; + wire_nl1000i_w_lg_nl1O0lOO7742w(0) <= NOT nl1O0lOO; + wire_nl1000i_w_lg_nl1O110l7798w(0) <= NOT nl1O110l; + wire_nl1000i_w_lg_nl1O1OOi7761w(0) <= NOT nl1O1OOi; + wire_nl1000i_w_lg_nl1Oi1il7734w(0) <= NOT nl1Oi1il; + wire_nl1000i_w_lg_nl1Oiiil7722w(0) <= NOT nl1Oiiil; + wire_nl1000i_w_lg_nl1OiO1i7715w(0) <= NOT nl1OiO1i; + wire_nl1000i_w_lg_nl1Ol0li7704w(0) <= NOT nl1Ol0li; + wire_nl1000i_w_lg_nl1Ol11l7712w(0) <= NOT nl1Ol11l; + wire_nl1000i_w_lg_nl1Oll1O7696w(0) <= NOT nl1Oll1O; + wire_nl1000i_w_lg_nl1OlOll7688w(0) <= NOT nl1OlOll; + wire_nl1000i_w_lg_nl1OOOii2349w(0) <= NOT nl1OOOii; + wire_nl1000i_w_lg_nl1OOOil2346w(0) <= NOT nl1OOOil; + wire_nl1000i_w_lg_nli1100i54856w(0) <= NOT nli1100i; + wire_nl1000i_w_lg_nli1i1ll5104w(0) <= NOT nli1i1ll; + wire_nl1000i_w_lg_nli1i1OO6078w(0) <= NOT nli1i1OO; + wire_nl1000i_w_lg_nlilli0Oi42220w(0) <= NOT nlilli0Oi; + wire_nl1000i_w_lg_nlilli0Ol42223w(0) <= NOT nlilli0Ol; + wire_nl1000i_w_lg_nlilli0OO42226w(0) <= NOT nlilli0OO; + wire_nl1000i_w_lg_nlillii0i42247w(0) <= NOT nlillii0i; + wire_nl1000i_w_lg_nlillii1i42232w(0) <= NOT nlillii1i; + wire_nl1000i_w_lg_nlillii1l42235w(0) <= NOT nlillii1l; + wire_nl1000i_w_lg_nlillii1O42238w(0) <= NOT nlillii1O; + wire_nl1000i_w_lg_nlilliiOi42828w(0) <= NOT nlilliiOi; + wire_nl1000i_w_lg_nlilliiOl42781w(0) <= NOT nlilliiOl; + wire_nl1000i_w_lg_nlilliiOO42779w(0) <= NOT nlilliiOO; + wire_nl1000i_w_lg_nlillil1i42778w(0) <= NOT nlillil1i; + wire_nl1000i_w_lg_nlillOi0i9874w(0) <= NOT nlillOi0i; + wire_nl1000i_w_lg_nlillOi1O9876w(0) <= NOT nlillOi1O; + wire_nl1000i_w_lg_nlillOiiO42888w(0) <= NOT nlillOiiO; + wire_nl1000i_w_lg_nlillOili42886w(0) <= NOT nlillOili; + wire_nl1000i_w_lg_nlillOill42884w(0) <= NOT nlillOill; + wire_nl1000i_w_lg_nlillOilO42882w(0) <= NOT nlillOilO; + wire_nl1000i_w_lg_nlillOiOi42880w(0) <= NOT nlillOiOi; + wire_nl1000i_w_lg_nlillOiOl42879w(0) <= NOT nlillOiOl; + wire_nl1000i_w_lg_nlillOl0i9881w(0) <= NOT nlillOl0i; + wire_nl1000i_w_lg_nlillOl0l9888w(0) <= NOT nlillOl0l; + wire_nl1000i_w_lg_nlillOl0O9902w(0) <= NOT nlillOl0O; + wire_nl1000i_w_lg_nlillOlii42167w(0) <= NOT nlillOlii; + wire_nl1000i_w_lg_nlillOlil42168w(0) <= NOT nlillOlil; + wire_nl1000i_w_lg_nlillOlli42169w(0) <= NOT nlillOlli; + wire_nl1000i_w_lg_nlilOO0iO5228w(0) <= NOT nlilOO0iO; + wire_nl1000i_w_lg_nlilOO0li42165w(0) <= NOT nlilOO0li; + wire_nl1000i_w_lg_nlilOO0ll42166w(0) <= NOT nlilOO0ll; + wire_nl1000i_w_lg_nll0i000i37581w(0) <= NOT nll0i000i; + wire_nl1000i_w_lg_nll0i000l37585w(0) <= NOT nll0i000l; + wire_nl1000i_w_lg_nll0i000O37589w(0) <= NOT nll0i000O; + wire_nl1000i_w_lg_nll0i001i37569w(0) <= NOT nll0i001i; + wire_nl1000i_w_lg_nll0i001l37573w(0) <= NOT nll0i001l; + wire_nl1000i_w_lg_nll0i001O37577w(0) <= NOT nll0i001O; + wire_nl1000i_w_lg_nll0i00ii37593w(0) <= NOT nll0i00ii; + wire_nl1000i_w_lg_nll0i00il37597w(0) <= NOT nll0i00il; + wire_nl1000i_w_lg_nll0i00iO37601w(0) <= NOT nll0i00iO; + wire_nl1000i_w_lg_nll0i00li37605w(0) <= NOT nll0i00li; + wire_nl1000i_w_lg_nll0i00ll37609w(0) <= NOT nll0i00ll; + wire_nl1000i_w_lg_nll0i00lO37613w(0) <= NOT nll0i00lO; + wire_nl1000i_w_lg_nll0i00Oi37617w(0) <= NOT nll0i00Oi; + wire_nl1000i_w_lg_nll0i00Ol37621w(0) <= NOT nll0i00Ol; + wire_nl1000i_w_lg_nll0i00OO37625w(0) <= NOT nll0i00OO; + wire_nl1000i_w_lg_nll0i01Oi37557w(0) <= NOT nll0i01Oi; + wire_nl1000i_w_lg_nll0i01Ol37561w(0) <= NOT nll0i01Ol; + wire_nl1000i_w_lg_nll0i01OO37565w(0) <= NOT nll0i01OO; + wire_nl1000i_w_lg_nll0i0i0i37641w(0) <= NOT nll0i0i0i; + wire_nl1000i_w_lg_nll0i0i0l37645w(0) <= NOT nll0i0i0l; + wire_nl1000i_w_lg_nll0i0i0O37649w(0) <= NOT nll0i0i0O; + wire_nl1000i_w_lg_nll0i0i1i37629w(0) <= NOT nll0i0i1i; + wire_nl1000i_w_lg_nll0i0i1l37633w(0) <= NOT nll0i0i1l; + wire_nl1000i_w_lg_nll0i0i1O37637w(0) <= NOT nll0i0i1O; + wire_nl1000i_w_lg_nll0i0iii37653w(0) <= NOT nll0i0iii; + wire_nl1000i_w_lg_nll0i0iil37657w(0) <= NOT nll0i0iil; + wire_nl1000i_w_lg_nll0i0iiO37661w(0) <= NOT nll0i0iiO; + wire_nl1000i_w_lg_nll0i0ili37665w(0) <= NOT nll0i0ili; + wire_nl1000i_w_lg_nll0i0ill37669w(0) <= NOT nll0i0ill; + wire_nl1000i_w_lg_nll0i0ilO37673w(0) <= NOT nll0i0ilO; + wire_nl1000i_w_lg_nll0i0iOi37677w(0) <= NOT nll0i0iOi; + wire_nl1000i_w_lg_nll0i0iOl37427w(0) <= NOT nll0i0iOl; + wire_nl1000i_w_lg_nll0i0iOO37430w(0) <= NOT nll0i0iOO; + wire_nl1000i_w_lg_nll0i0l0i37446w(0) <= NOT nll0i0l0i; + wire_nl1000i_w_lg_nll0i0l0l37450w(0) <= NOT nll0i0l0l; + wire_nl1000i_w_lg_nll0i0l0O37454w(0) <= NOT nll0i0l0O; + wire_nl1000i_w_lg_nll0i0l1i37434w(0) <= NOT nll0i0l1i; + wire_nl1000i_w_lg_nll0i0l1l37438w(0) <= NOT nll0i0l1l; + wire_nl1000i_w_lg_nll0i0l1O37442w(0) <= NOT nll0i0l1O; + wire_nl1000i_w_lg_nll0i0lii37458w(0) <= NOT nll0i0lii; + wire_nl1000i_w_lg_nll0i0lil37462w(0) <= NOT nll0i0lil; + wire_nl1000i_w_lg_nll0i0liO37466w(0) <= NOT nll0i0liO; + wire_nl1000i_w_lg_nll0i0lli37470w(0) <= NOT nll0i0lli; + wire_nl1000i_w_lg_nll0i0lll37474w(0) <= NOT nll0i0lll; + wire_nl1000i_w_lg_nll0i0llO37478w(0) <= NOT nll0i0llO; + wire_nl1000i_w_lg_nll0i0lOi37482w(0) <= NOT nll0i0lOi; + wire_nl1000i_w_lg_nll0i0lOl37486w(0) <= NOT nll0i0lOl; + wire_nl1000i_w_lg_nll0i0lOO37490w(0) <= NOT nll0i0lOO; + wire_nl1000i_w_lg_nll0i0O0i37506w(0) <= NOT nll0i0O0i; + wire_nl1000i_w_lg_nll0i0O0l37510w(0) <= NOT nll0i0O0l; + wire_nl1000i_w_lg_nll0i0O0O37514w(0) <= NOT nll0i0O0O; + wire_nl1000i_w_lg_nll0i0O1i37494w(0) <= NOT nll0i0O1i; + wire_nl1000i_w_lg_nll0i0O1l37498w(0) <= NOT nll0i0O1l; + wire_nl1000i_w_lg_nll0i0O1O37502w(0) <= NOT nll0i0O1O; + wire_nl1000i_w_lg_nll0i0Oii37518w(0) <= NOT nll0i0Oii; + wire_nl1000i_w_lg_nll0i0Oil37522w(0) <= NOT nll0i0Oil; + wire_nl1000i_w_lg_nll0i0OiO37526w(0) <= NOT nll0i0OiO; + wire_nl1000i_w_lg_nll0i0Oli37530w(0) <= NOT nll0i0Oli; + wire_nl1000i_w_lg_nll0i0Oll37534w(0) <= NOT nll0i0Oll; + wire_nl1000i_w_lg_nll0i0OlO37538w(0) <= NOT nll0i0OlO; + wire_nl1000i_w_lg_nll0i0OOi37542w(0) <= NOT nll0i0OOi; + wire_nl1000i_w_lg_nll0i0OOl37546w(0) <= NOT nll0i0OOl; + wire_nl1000i_w_lg_nll0i0OOO37550w(0) <= NOT nll0i0OOO; + wire_nl1000i_w_lg_nll0iO1lO37554w(0) <= NOT nll0iO1lO; + wire_nl1000i_w_lg_nll0liiOi29692w(0) <= NOT nll0liiOi; + wire_nl1000i_w_lg_nll0liiOl29690w(0) <= NOT nll0liiOl; + wire_nl1000i_w_lg_nll0ll1OO36546w(0) <= NOT nll0ll1OO; + wire_nl1000i_w_lg_nll0lOi1l36419w(0) <= NOT nll0lOi1l; + wire_nl1000i_w_lg_nll0lOi1O36327w(0) <= NOT nll0lOi1O; + wire_nl1000i_w_lg_nll0O0i0i36246w(0) <= NOT nll0O0i0i; + wire_nl1000i_w_lg_nll0O0i0l36254w(0) <= NOT nll0O0i0l; + wire_nl1000i_w_lg_nll0O0i0O36253w(0) <= NOT nll0O0i0O; + wire_nl1000i_w_lg_nll0O0iii37709w(0) <= NOT nll0O0iii; + wire_nl1000i_w_lg_nll0O0iil37707w(0) <= NOT nll0O0iil; + wire_nl1000i_w_lg_nll0O0iiO37705w(0) <= NOT nll0O0iiO; + wire_nl1000i_w_lg_nll0O0ili37704w(0) <= NOT nll0O0ili; + wire_nl1000i_w_lg_nll0O0ill36243w(0) <= NOT nll0O0ill; + wire_nl1000i_w_lg_nll0O0ilO36240w(0) <= NOT nll0O0ilO; + wire_nl1000i_w_lg_nll0O0iOl5342w(0) <= NOT nll0O0iOl; + wire_nl1000i_w_lg_nll0O101i36347w(0) <= NOT nll0O101i; + wire_nl1000i_w_lg_nll0O101l36349w(0) <= NOT nll0O101l; + wire_nl1000i_w_lg_nll0O10OO35783w(0) <= NOT nll0O10OO; + wire_nl1000i_w_lg_nll0O11ii36329w(0) <= NOT nll0O11ii; + wire_nl1000i_w_lg_nll0O11il36331w(0) <= NOT nll0O11il; + wire_nl1000i_w_lg_nll0O11iO36333w(0) <= NOT nll0O11iO; + wire_nl1000i_w_lg_nll0O11li36335w(0) <= NOT nll0O11li; + wire_nl1000i_w_lg_nll0O11ll36337w(0) <= NOT nll0O11ll; + wire_nl1000i_w_lg_nll0O11lO36339w(0) <= NOT nll0O11lO; + wire_nl1000i_w_lg_nll0O11Oi36341w(0) <= NOT nll0O11Oi; + wire_nl1000i_w_lg_nll0O11Ol36343w(0) <= NOT nll0O11Ol; + wire_nl1000i_w_lg_nll0O11OO36345w(0) <= NOT nll0O11OO; + wire_nl1000i_w_lg_nll0O1i1i35781w(0) <= NOT nll0O1i1i; + wire_nl1000i_w_lg_nll0Oi01l5329w(0) <= NOT nll0Oi01l; + wire_nl1000i_w_lg_nll0Oi0ii5951w(0) <= NOT nll0Oi0ii; + wire_nl1000i_w_lg_nll0Oi0il5949w(0) <= NOT nll0Oi0il; + wire_nl1000i_w_lg_nll0Oi0iO5948w(0) <= NOT nll0Oi0iO; + wire_nl1000i_w_lg_nll0Oi10i5975w(0) <= NOT nll0Oi10i; + wire_nl1000i_w_lg_nll0Oi10l5973w(0) <= NOT nll0Oi10l; + wire_nl1000i_w_lg_nll0Oi10O5971w(0) <= NOT nll0Oi10O; + wire_nl1000i_w_lg_nll0Oi11O5977w(0) <= NOT nll0Oi11O; + wire_nl1000i_w_lg_nll0Oi1ii5969w(0) <= NOT nll0Oi1ii; + wire_nl1000i_w_lg_nll0Oi1il5967w(0) <= NOT nll0Oi1il; + wire_nl1000i_w_lg_nll0Oi1iO5965w(0) <= NOT nll0Oi1iO; + wire_nl1000i_w_lg_nll0Oi1li5963w(0) <= NOT nll0Oi1li; + wire_nl1000i_w_lg_nll0Oi1ll5962w(0) <= NOT nll0Oi1ll; + wire_nl1000i_w_lg_nll0Oii0i36228w(0) <= NOT nll0Oii0i; + wire_nl1000i_w_lg_nll0Oii1i5265w(0) <= NOT nll0Oii1i; + wire_nl1000i_w_lg_nll0Oii1l5335w(0) <= NOT nll0Oii1l; + wire_nl1000i_w_lg_nll0OilO5675w(0) <= NOT nll0OilO; + wire_nl1000i_w_lg_nll0OOOll36490w(0) <= NOT nll0OOOll; + wire_nl1000i_w_lg_nll0OOOOi36491w(0) <= NOT nll0OOOOi; + wire_nl1000i_w_lg_nll100Oil36983w(0) <= NOT nll100Oil; + wire_nl1000i_w_lg_nll11lOli36986w(0) <= NOT nll11lOli; + wire_nl1000i_w_lg_nll11lOll36990w(0) <= NOT nll11lOll; + wire_nl1000i_w_lg_nll11lOlO36994w(0) <= NOT nll11lOlO; + wire_nl1000i_w_lg_nll11lOOi36998w(0) <= NOT nll11lOOi; + wire_nl1000i_w_lg_nll11lOOl37002w(0) <= NOT nll11lOOl; + wire_nl1000i_w_lg_nll11lOOO37006w(0) <= NOT nll11lOOO; + wire_nl1000i_w_lg_nll11O00i37082w(0) <= NOT nll11O00i; + wire_nl1000i_w_lg_nll11O00l37086w(0) <= NOT nll11O00l; + wire_nl1000i_w_lg_nll11O00O37090w(0) <= NOT nll11O00O; + wire_nl1000i_w_lg_nll11O01i37070w(0) <= NOT nll11O01i; + wire_nl1000i_w_lg_nll11O01l37074w(0) <= NOT nll11O01l; + wire_nl1000i_w_lg_nll11O01O37078w(0) <= NOT nll11O01O; + wire_nl1000i_w_lg_nll11O0ii37094w(0) <= NOT nll11O0ii; + wire_nl1000i_w_lg_nll11O0il37098w(0) <= NOT nll11O0il; + wire_nl1000i_w_lg_nll11O0iO37102w(0) <= NOT nll11O0iO; + wire_nl1000i_w_lg_nll11O0li37106w(0) <= NOT nll11O0li; + wire_nl1000i_w_lg_nll11O0ll37205w(0) <= NOT nll11O0ll; + wire_nl1000i_w_lg_nll11O0lO37208w(0) <= NOT nll11O0lO; + wire_nl1000i_w_lg_nll11O0Oi37212w(0) <= NOT nll11O0Oi; + wire_nl1000i_w_lg_nll11O0Ol37216w(0) <= NOT nll11O0Ol; + wire_nl1000i_w_lg_nll11O0OO37220w(0) <= NOT nll11O0OO; + wire_nl1000i_w_lg_nll11O10i37022w(0) <= NOT nll11O10i; + wire_nl1000i_w_lg_nll11O10l37026w(0) <= NOT nll11O10l; + wire_nl1000i_w_lg_nll11O10O37030w(0) <= NOT nll11O10O; + wire_nl1000i_w_lg_nll11O11i37010w(0) <= NOT nll11O11i; + wire_nl1000i_w_lg_nll11O11l37014w(0) <= NOT nll11O11l; + wire_nl1000i_w_lg_nll11O11O37018w(0) <= NOT nll11O11O; + wire_nl1000i_w_lg_nll11O1ii37034w(0) <= NOT nll11O1ii; + wire_nl1000i_w_lg_nll11O1il37038w(0) <= NOT nll11O1il; + wire_nl1000i_w_lg_nll11O1iO37042w(0) <= NOT nll11O1iO; + wire_nl1000i_w_lg_nll11O1li37046w(0) <= NOT nll11O1li; + wire_nl1000i_w_lg_nll11O1ll37050w(0) <= NOT nll11O1ll; + wire_nl1000i_w_lg_nll11O1lO37054w(0) <= NOT nll11O1lO; + wire_nl1000i_w_lg_nll11O1Oi37058w(0) <= NOT nll11O1Oi; + wire_nl1000i_w_lg_nll11O1Ol37062w(0) <= NOT nll11O1Ol; + wire_nl1000i_w_lg_nll11O1OO37066w(0) <= NOT nll11O1OO; + wire_nl1000i_w_lg_nll11Oi0i37236w(0) <= NOT nll11Oi0i; + wire_nl1000i_w_lg_nll11Oi0l37240w(0) <= NOT nll11Oi0l; + wire_nl1000i_w_lg_nll11Oi0O37244w(0) <= NOT nll11Oi0O; + wire_nl1000i_w_lg_nll11Oi1i37224w(0) <= NOT nll11Oi1i; + wire_nl1000i_w_lg_nll11Oi1l37228w(0) <= NOT nll11Oi1l; + wire_nl1000i_w_lg_nll11Oi1O37232w(0) <= NOT nll11Oi1O; + wire_nl1000i_w_lg_nll11Oiii37248w(0) <= NOT nll11Oiii; + wire_nl1000i_w_lg_nll11Oiil37252w(0) <= NOT nll11Oiil; + wire_nl1000i_w_lg_nll11OiiO37256w(0) <= NOT nll11OiiO; + wire_nl1000i_w_lg_nll11Oili37260w(0) <= NOT nll11Oili; + wire_nl1000i_w_lg_nll11Oill37264w(0) <= NOT nll11Oill; + wire_nl1000i_w_lg_nll11OilO37268w(0) <= NOT nll11OilO; + wire_nl1000i_w_lg_nll11OiOi37272w(0) <= NOT nll11OiOi; + wire_nl1000i_w_lg_nll11OiOl37276w(0) <= NOT nll11OiOl; + wire_nl1000i_w_lg_nll11OiOO37280w(0) <= NOT nll11OiOO; + wire_nl1000i_w_lg_nll11Ol0i37296w(0) <= NOT nll11Ol0i; + wire_nl1000i_w_lg_nll11Ol0l37300w(0) <= NOT nll11Ol0l; + wire_nl1000i_w_lg_nll11Ol0O37304w(0) <= NOT nll11Ol0O; + wire_nl1000i_w_lg_nll11Ol1i37284w(0) <= NOT nll11Ol1i; + wire_nl1000i_w_lg_nll11Ol1l37288w(0) <= NOT nll11Ol1l; + wire_nl1000i_w_lg_nll11Ol1O37292w(0) <= NOT nll11Ol1O; + wire_nl1000i_w_lg_nll11Olii37308w(0) <= NOT nll11Olii; + wire_nl1000i_w_lg_nll11Olil37312w(0) <= NOT nll11Olil; + wire_nl1000i_w_lg_nll11OliO37316w(0) <= NOT nll11OliO; + wire_nl1000i_w_lg_nll11Olli37320w(0) <= NOT nll11Olli; + wire_nl1000i_w_lg_nll11Olll37324w(0) <= NOT nll11Olll; + wire_nl1000i_w_lg_nll11OllO37328w(0) <= NOT nll11OllO; + wire_nl1000i_w_lg_nlli0i0li36947w(0) <= NOT nlli0i0li; + wire_nl1000i_w_lg_nlli0i0ll36945w(0) <= NOT nlli0i0ll; + wire_nl1000i_w_lg_nlli0i0lO36943w(0) <= NOT nlli0i0lO; + wire_nl1000i_w_lg_nlli0i0Oi36941w(0) <= NOT nlli0i0Oi; + wire_nl1000i_w_lg_nlli0i0Ol36939w(0) <= NOT nlli0i0Ol; + wire_nl1000i_w_lg_nlli0i0OO36937w(0) <= NOT nlli0i0OO; + wire_nl1000i_w_lg_nlli0ii0i36930w(0) <= NOT nlli0ii0i; + wire_nl1000i_w_lg_nlli0ii1i36935w(0) <= NOT nlli0ii1i; + wire_nl1000i_w_lg_nlli0ii1l36933w(0) <= NOT nlli0ii1l; + wire_nl1000i_w_lg_nlli0ii1O36931w(0) <= NOT nlli0ii1O; + wire_nl1000i_w_lg_nlli0illO35982w(0) <= NOT nlli0illO; + wire_nl1000i_w_lg_nlli0ilOi35930w(0) <= NOT nlli0ilOi; + wire_nl1000i_w_lg_nlli0ilOl36234w(0) <= NOT nlli0ilOl; + wire_nl1000i_w_lg_nlli0ilOO5658w(0) <= NOT nlli0ilOO; + wire_nl1000i_w_lg_nlli0iO1O35900w(0) <= NOT nlli0iO1O; + wire_nl1000i_w_lg_nlli1100O36185w(0) <= NOT nlli1100O; + wire_nl1000i_w_lg_nlli1Oili36980w(0) <= NOT nlli1Oili; + wire_nl1000i_w_lg_nlli1Ol0O36969w(0) <= NOT nlli1Ol0O; + wire_nl1000i_w_lg_nlli1Olii36966w(0) <= NOT nlli1Olii; + wire_nl1000i_w_lg_nlli1Olil36964w(0) <= NOT nlli1Olil; + wire_nl1000i_w_lg_nlli1OliO36962w(0) <= NOT nlli1OliO; + wire_nl1000i_w_lg_nlli1Olli36960w(0) <= NOT nlli1Olli; + wire_nl1000i_w_lg_nlli1Olll36958w(0) <= NOT nlli1Olll; + wire_nl1000i_w_lg_nlli1OllO36956w(0) <= NOT nlli1OllO; + wire_nl1000i_w_lg_nlli1OlOi36954w(0) <= NOT nlli1OlOi; + wire_nl1000i_w_lg_nlli1OlOl36952w(0) <= NOT nlli1OlOl; + wire_nl1000i_w_lg_nlli1OlOO36950w(0) <= NOT nlli1OlOO; + wire_nl1000i_w_lg_nlli1OO1i36949w(0) <= NOT nlli1OO1i; + wire_nl1000i_w_lg_nlliiil0l34446w(0) <= NOT nlliiil0l; + wire_nl1000i_w_lg_nlliiil0O42784w(0) <= NOT nlliiil0O; + wire_nl1000i_w_lg_nlliiilii28850w(0) <= NOT nlliiilii; + wire_nl1000i_w_lg_nlliliiOi35868w(0) <= NOT nlliliiOi; + wire_nl1000i_w_lg_nlliliiOl35866w(0) <= NOT nlliliiOl; + wire_nl1000i_w_lg_nlliliiOO35864w(0) <= NOT nlliliiOO; + wire_nl1000i_w_lg_nllilil0i35859w(0) <= NOT nllilil0i; + wire_nl1000i_w_lg_nllilil0l35858w(0) <= NOT nllilil0l; + wire_nl1000i_w_lg_nllilil1i35863w(0) <= NOT nllilil1i; + wire_nl1000i_w_lg_nllilil1l36927w(0) <= NOT nllilil1l; + wire_nl1000i_w_lg_nllilil1O35861w(0) <= NOT nllilil1O; + wire_nl1000i_w_lg_nllillOl5218w(0) <= NOT nllillOl; + wire_nl1000i_w_lg_nllilO1i5110w(0) <= NOT nllilO1i; + wire_nl1000i_w_lg_nllilO1l5219w(0) <= NOT nllilO1l; + wire_nl1000i_w_lg_nllilOii5945w(0) <= NOT nllilOii; + wire_nl1000i_w_lg_nllilOil5943w(0) <= NOT nllilOil; + wire_nl1000i_w_lg_nllilOiO5941w(0) <= NOT nllilOiO; + wire_nl1000i_w_lg_nllilOli5939w(0) <= NOT nllilOli; + wire_nl1000i_w_lg_nllilOll5937w(0) <= NOT nllilOll; + wire_nl1000i_w_lg_nllilOlO5935w(0) <= NOT nllilOlO; + wire_nl1000i_w_lg_nllilOlOi35909w(0) <= NOT nllilOlOi; + wire_nl1000i_w_lg_nllilOOi5933w(0) <= NOT nllilOOi; + wire_nl1000i_w_lg_nllilOOl5931w(0) <= NOT nllilOOl; + wire_nl1000i_w_lg_nllilOOO5930w(0) <= NOT nllilOOO; + wire_nl1000i_w_lg_nlliO01i5754w(0) <= NOT nlliO01i; + wire_nl1000i_w_lg_nlliO10i5698w(0) <= NOT nlliO10i; + wire_nl1000i_w_lg_nlliO11i5100w(0) <= NOT nlliO11i; + wire_nl1000i_w_lg_nlliO11l5089w(0) <= NOT nlliO11l; + wire_nl1000i_w_lg_nlliO11O5108w(0) <= NOT nlliO11O; + wire_nl1000i_w_lg_nlliO1Oi5683w(0) <= NOT nlliO1Oi; + wire_nl1000i_w_lg_nlliOl00i35348w(0) <= NOT nlliOl00i; + wire_nl1000i_w_lg_nlliOl00l35350w(0) <= NOT nlliOl00l; + wire_nl1000i_w_lg_nlliOl00O35352w(0) <= NOT nlliOl00O; + wire_nl1000i_w_lg_nlliOl01O35346w(0) <= NOT nlliOl01O; + wire_nl1000i_w_lg_nlliOl0ii35354w(0) <= NOT nlliOl0ii; + wire_nl1000i_w_lg_nlliOl0il35356w(0) <= NOT nlliOl0il; + wire_nl1000i_w_lg_nlliOl0iO35358w(0) <= NOT nlliOl0iO; + wire_nl1000i_w_lg_nlliOl10O28856w(0) <= NOT nlliOl10O; + wire_nl1000i_w_lg_nlliOl11l35175w(0) <= NOT nlliOl11l; + wire_nl1000i_w_lg_nlll000il34361w(0) <= NOT nlll000il; + wire_nl1000i_w_lg_nlll000iO34363w(0) <= NOT nlll000iO; + wire_nl1000i_w_lg_nlll000li34365w(0) <= NOT nlll000li; + wire_nl1000i_w_lg_nlll000ll34367w(0) <= NOT nlll000ll; + wire_nl1000i_w_lg_nlll000lO34369w(0) <= NOT nlll000lO; + wire_nl1000i_w_lg_nlll000Oi34371w(0) <= NOT nlll000Oi; + wire_nl1000i_w_lg_nlll000Ol34373w(0) <= NOT nlll000Ol; + wire_nl1000i_w_lg_nlll000OO34375w(0) <= NOT nlll000OO; + wire_nl1000i_w_lg_nlll00i0i35436w(0) <= NOT nlll00i0i; + wire_nl1000i_w_lg_nlll00i0l35438w(0) <= NOT nlll00i0l; + wire_nl1000i_w_lg_nlll00i0O35440w(0) <= NOT nlll00i0O; + wire_nl1000i_w_lg_nlll00i1i34377w(0) <= NOT nlll00i1i; + wire_nl1000i_w_lg_nlll00i1l34379w(0) <= NOT nlll00i1l; + wire_nl1000i_w_lg_nlll00i1O34381w(0) <= NOT nlll00i1O; + wire_nl1000i_w_lg_nlll00iii35442w(0) <= NOT nlll00iii; + wire_nl1000i_w_lg_nlll00iil35444w(0) <= NOT nlll00iil; + wire_nl1000i_w_lg_nlll0101l34625w(0) <= NOT nlll0101l; + wire_nl1000i_w_lg_nlll01i1i34359w(0) <= NOT nlll01i1i; + wire_nl1000i_w_lg_nlll0il1O34569w(0) <= NOT nlll0il1O; + wire_nl1000i_w_lg_nlll0iOOO34563w(0) <= NOT nlll0iOOO; + wire_nl1000i_w_lg_nlll1il0l34166w(0) <= NOT nlll1il0l; + wire_nl1000i_w_lg_nlll1il1l34164w(0) <= NOT nlll1il1l; + wire_nl1000i_w_lg_nlll1il1O34165w(0) <= NOT nlll1il1O; + wire_nl1000i_w_lg_nlll1lOOO34167w(0) <= NOT nlll1lOOO; + wire_nl1000i_w_lg_nlll1OO0O966w(0) <= NOT nlll1OO0O; + wire_nl1000i_w_lg_nlll1OOil35170w(0) <= NOT nlll1OOil; + wire_nl1000i_w_lg_nllli0il4654w(0) <= NOT nllli0il; + wire_nl1000i_w_lg_nllliiOi4618w(0) <= NOT nllliiOi; + wire_nl1000i_w_lg_nllO0i0l4357w(0) <= NOT nllO0i0l; + wire_nl1000i_w_lg_nllO0i0O4338w(0) <= NOT nllO0i0O; + wire_nl1000i_w_lg_nlO00lOiO29672w(0) <= NOT nlO00lOiO; + wire_nl1000i_w_lg_nlO00lOli29673w(0) <= NOT nlO00lOli; + wire_nl1000i_w_lg_nlO00lOll29674w(0) <= NOT nlO00lOll; + wire_nl1000i_w_lg_nlO00lOlO28853w(0) <= NOT nlO00lOlO; + wire_nl1000i_w_lg_nlO00lOOi28854w(0) <= NOT nlO00lOOi; + wire_nl1000i_w_lg_nlO00lOOl28855w(0) <= NOT nlO00lOOl; + wire_nl1000i_w_lg_nlO0il00i29492w(0) <= NOT nlO0il00i; + wire_nl1000i_w_lg_nlO0il01O29664w(0) <= NOT nlO0il01O; + wire_nl1000i_w_lg_nlO0iOiOO29413w(0) <= NOT nlO0iOiOO; + wire_nl1000i_w_lg_nlO0li0OO29490w(0) <= NOT nlO0li0OO; + wire_nl1000i_w_lg_nlO0lii0i29732w(0) <= NOT nlO0lii0i; + wire_nl1000i_w_lg_nlO0lii0l29730w(0) <= NOT nlO0lii0l; + wire_nl1000i_w_lg_nlO0lii0O29728w(0) <= NOT nlO0lii0O; + wire_nl1000i_w_lg_nlO0lii1i29421w(0) <= NOT nlO0lii1i; + wire_nl1000i_w_lg_nlO0lii1O29734w(0) <= NOT nlO0lii1O; + wire_nl1000i_w_lg_nlO0liiii29726w(0) <= NOT nlO0liiii; + wire_nl1000i_w_lg_nlO0liiil29724w(0) <= NOT nlO0liiil; + wire_nl1000i_w_lg_nlO0liiiO29722w(0) <= NOT nlO0liiiO; + wire_nl1000i_w_lg_nlO0liili29720w(0) <= NOT nlO0liili; + wire_nl1000i_w_lg_nlO0liill29718w(0) <= NOT nlO0liill; + wire_nl1000i_w_lg_nlO0liilO29716w(0) <= NOT nlO0liilO; + wire_nl1000i_w_lg_nlO0liiOi29715w(0) <= NOT nlO0liiOi; + wire_nl1000i_w_lg_nlO0liiOl29775w(0) <= NOT nlO0liiOl; + wire_nl1000i_w_lg_nlO0liiOO29772w(0) <= NOT nlO0liiOO; + wire_nl1000i_w_lg_nlO0lil0i29764w(0) <= NOT nlO0lil0i; + wire_nl1000i_w_lg_nlO0lil0l29762w(0) <= NOT nlO0lil0l; + wire_nl1000i_w_lg_nlO0lil0O29760w(0) <= NOT nlO0lil0O; + wire_nl1000i_w_lg_nlO0lil1i29770w(0) <= NOT nlO0lil1i; + wire_nl1000i_w_lg_nlO0lil1l29768w(0) <= NOT nlO0lil1l; + wire_nl1000i_w_lg_nlO0lil1O29766w(0) <= NOT nlO0lil1O; + wire_nl1000i_w_lg_nlO0lilii29758w(0) <= NOT nlO0lilii; + wire_nl1000i_w_lg_nlO0lilil29756w(0) <= NOT nlO0lilil; + wire_nl1000i_w_lg_nlO0liliO29755w(0) <= NOT nlO0liliO; + wire_nl1000i_w_lg_nlO0lliO4409w(0) <= NOT nlO0lliO; + wire_nl1000i_w_lg_nlO0llOi4286w(0) <= NOT nlO0llOi; + wire_nl1000i_w_lg_nlO0OlOii28872w(0) <= NOT nlO0OlOii; + wire_nl1000i_w_lg_nlO0OOOO4297w(0) <= NOT nlO0OOOO; + wire_nl1000i_w_lg_nlO1lOi0O29449w(0) <= NOT nlO1lOi0O; + wire_nl1000i_w_lg_nlO1lOiii29450w(0) <= NOT nlO1lOiii; + wire_nl1000i_w_lg_nlO1lOiil29451w(0) <= NOT nlO1lOiil; + wire_nl1000i_w_lg_nlO1lOiiO29452w(0) <= NOT nlO1lOiiO; + wire_nl1000i_w_lg_nlO1lOili29453w(0) <= NOT nlO1lOili; + wire_nl1000i_w_lg_nlO1lOill29454w(0) <= NOT nlO1lOill; + wire_nl1000i_w_lg_nlO1lOilO29455w(0) <= NOT nlO1lOilO; + wire_nl1000i_w_lg_nlO1lOiOi29440w(0) <= NOT nlO1lOiOi; + wire_nl1000i_w_lg_nlO1lOiOl29441w(0) <= NOT nlO1lOiOl; + wire_nl1000i_w_lg_nlO1lOiOO29442w(0) <= NOT nlO1lOiOO; + wire_nl1000i_w_lg_nlO1lOl0i29446w(0) <= NOT nlO1lOl0i; + wire_nl1000i_w_lg_nlO1lOl0l29447w(0) <= NOT nlO1lOl0l; + wire_nl1000i_w_lg_nlO1lOl0O29432w(0) <= NOT nlO1lOl0O; + wire_nl1000i_w_lg_nlO1lOl1i29443w(0) <= NOT nlO1lOl1i; + wire_nl1000i_w_lg_nlO1lOl1l29444w(0) <= NOT nlO1lOl1l; + wire_nl1000i_w_lg_nlO1lOl1O29445w(0) <= NOT nlO1lOl1O; + wire_nl1000i_w_lg_nlO1lOlii29433w(0) <= NOT nlO1lOlii; + wire_nl1000i_w_lg_nlO1lOlil29434w(0) <= NOT nlO1lOlil; + wire_nl1000i_w_lg_nlO1lOliO29435w(0) <= NOT nlO1lOliO; + wire_nl1000i_w_lg_nlO1lOlli29436w(0) <= NOT nlO1lOlli; + wire_nl1000i_w_lg_nlO1lOlll29437w(0) <= NOT nlO1lOlll; + wire_nl1000i_w_lg_nlO1lOllO29438w(0) <= NOT nlO1lOllO; + wire_nl1000i_w_lg_nlO1lOlOi29439w(0) <= NOT nlO1lOlOi; + wire_nl1000i_w_lg_nlO1lOlOl29424w(0) <= NOT nlO1lOlOl; + wire_nl1000i_w_lg_nlO1lOlOO29425w(0) <= NOT nlO1lOlOO; + wire_nl1000i_w_lg_nlO1lOO0i29429w(0) <= NOT nlO1lOO0i; + wire_nl1000i_w_lg_nlO1lOO0l29430w(0) <= NOT nlO1lOO0l; + wire_nl1000i_w_lg_nlO1lOO0O29431w(0) <= NOT nlO1lOO0O; + wire_nl1000i_w_lg_nlO1lOO1i29426w(0) <= NOT nlO1lOO1i; + wire_nl1000i_w_lg_nlO1lOO1l29427w(0) <= NOT nlO1lOO1l; + wire_nl1000i_w_lg_nlO1lOO1O29428w(0) <= NOT nlO1lOO1O; + wire_nl1000i_w_lg_nlO1O0l1i29448w(0) <= NOT nlO1O0l1i; + wire_nl1000i_w_lg_nlO1Oi1ll28015w(0) <= NOT nlO1Oi1ll; + wire_nl1000i_w_lg_nlO1Ol1li29671w(0) <= NOT nlO1Ol1li; + wire_nl1000i_w_lg_nlOi0l01O28780w(0) <= NOT nlOi0l01O; + wire_nl1000i_w_lg_nlOi0O0ii28769w(0) <= NOT nlOi0O0ii; + wire_nl1000i_w_lg_nlOi0O10O28772w(0) <= NOT nlOi0O10O; + wire_nl1000i_w_lg_nlOi0Ol1i28762w(0) <= NOT nlOi0Ol1i; + wire_nl1000i_w_lg_nlOi1Oill29647w(0) <= NOT nlOi1Oill; + wire_nl1000i_w_lg_nlOi1OilO29645w(0) <= NOT nlOi1OilO; + wire_nl1000i_w_lg_nlOi1OiOi29643w(0) <= NOT nlOi1OiOi; + wire_nl1000i_w_lg_nlOi1OiOl29642w(0) <= NOT nlOi1OiOl; + wire_nl1000i_w_lg_nlOi1OiOO29159w(0) <= NOT nlOi1OiOO; + wire_nl1000i_w_lg_nlOi1Ol1i29713w(0) <= NOT nlOi1Ol1i; + wire_nl1000i_w_lg_nlOi1Ol1l29651w(0) <= NOT nlOi1Ol1l; + wire_nl1000i_w_lg_nlOi1Ol1O29650w(0) <= NOT nlOi1Ol1O; + wire_nl1000i_w_lg_nlOii111O28751w(0) <= NOT nlOii111O; + wire_nl1000i_w_lg_nlOiiiOO60350w(0) <= NOT nlOiiiOO; + wire_nl1000i_w_lg_nlOiil0O60340w(0) <= NOT nlOiil0O; + wire_nl1000i_w_lg_nlOiil1i60348w(0) <= NOT nlOiil1i; + wire_nl1000i_w_lg_nlOiil1l60346w(0) <= NOT nlOiil1l; + wire_nl1000i_w_lg_nlOiil1O60344w(0) <= NOT nlOiil1O; + wire_nl1000i_w_lg_nlOiilii60339w(0) <= NOT nlOiilii; + wire_nl1000i_w_lg_nlOil0ll60311w(0) <= NOT nlOil0ll; + wire_nl1000i_w_lg_nlOil0lO60309w(0) <= NOT nlOil0lO; + wire_nl1000i_w_lg_nlOil0Oi59694w(0) <= NOT nlOil0Oi; + wire_nl1000i_w_lg_nlOil0Ol59700w(0) <= NOT nlOil0Ol; + wire_nl1000i_w_lg_nlOil0OO59692w(0) <= NOT nlOil0OO; + wire_nl1000i_w_lg_nlOil10i60286w(0) <= NOT nlOil10i; + wire_nl1000i_w_lg_nlOil10l60284w(0) <= NOT nlOil10l; + wire_nl1000i_w_lg_nlOil10O60282w(0) <= NOT nlOil10O; + wire_nl1000i_w_lg_nlOil11l59626w(0) <= NOT nlOil11l; + wire_nl1000i_w_lg_nlOil11O59625w(0) <= NOT nlOil11O; + wire_nl1000i_w_lg_nlOil1ii60280w(0) <= NOT nlOil1ii; + wire_nl1000i_w_lg_nlOil1il60278w(0) <= NOT nlOil1il; + wire_nl1000i_w_lg_nlOil1iO60276w(0) <= NOT nlOil1iO; + wire_nl1000i_w_lg_nlOil1li60274w(0) <= NOT nlOil1li; + wire_nl1000i_w_lg_nlOil1ll60273w(0) <= NOT nlOil1ll; + wire_nl1000i_w_lg_nlOil1O1O28018w(0) <= NOT nlOil1O1O; + wire_nl1000i_w_lg_nlOil1OOO28520w(0) <= NOT nlOil1OOO; + wire_nl1000i_w_lg_nlOili0i4039w(0) <= NOT nlOili0i; + wire_nl1000i_w_lg_nlOili0l4166w(0) <= NOT nlOili0l; + wire_nl1000i_w_lg_nlOili0O4300w(0) <= NOT nlOili0O; + wire_nl1000i_w_lg_nlOili1i59697w(0) <= NOT nlOili1i; + wire_nl1000i_w_lg_nlOili1l60355w(0) <= NOT nlOili1l; + wire_nl1000i_w_lg_nlOiliii4069w(0) <= NOT nlOiliii; + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nll0Oii1l5332w5333w5334w5337w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_nll0Oii1l5332w5333w5334w(0) OR wire_nl1000i_w_lg_w_lg_nll0Oii1l5335w5336w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nlliO11i5100w5701w5727w(0) <= wire_nl1000i_w_lg_w_lg_nlliO11i5100w5701w(0) OR wire_nl1000i_w_lg_w_lg_nlliO11l5089w5726w(0); + wire_nl1000i_w_lg_w_lg_w_lg_w_lg_n1l000l4315w4317w4318w4319w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_n1l000l4315w4317w4318w(0) OR niOO00i0l; + wire_nl1000i_w_lg_w_lg_w_lg_nll0OiiO5649w5650w5652w(0) <= wire_nl1000i_w_lg_w_lg_nll0OiiO5649w5650w(0) OR wire_nl1000i_w_lg_nll0Oili5651w(0); + wire_nl1000i_w_lg_w_lg_n1l000l4315w4317w(0) <= wire_nl1000i_w_lg_n1l000l4315w(0) OR wire_nl1000i_w_lg_w_lg_n1l000l4101w4316w(0); + wire_nl1000i_w_lg_w_lg_nlli0i01i36206w36210w(0) <= wire_nl1000i_w_lg_nlli0i01i36206w(0) OR wire_nl1000i_w_lg_nlli0i1Ol36209w(0); + wire_nl1000i_w_lg_w_lg_nlli0i1OO36214w36218w(0) <= wire_nl1000i_w_lg_nlli0i1OO36214w(0) OR wire_nl1000i_w_lg_nlli0i1Oi36217w(0); + wire_nl1000i_w_lg_w_lg_nlli0illi35932w35934w(0) <= wire_nl1000i_w_lg_nlli0illi35932w(0) OR wire_nl1000i_w_lg_nlli0iliO35933w(0); + wire_nl1000i_w_lg_w_lg_n1l00ii4074w4075w(0) <= wire_nl1000i_w_lg_n1l00ii4074w(0) OR niOO00lii; + wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w35983w(0) <= wire_nl1000i_w_lg_nlli0ilOO5658w(0) OR wire_nl1000i_w_lg_nlli0illO35982w(0); + wire_nl1000i_w5339w(0) <= wire_nl1000i_w_lg_w_lg_w_lg_w_lg_nll0Oii1l5332w5333w5334w5337w(0) OR wire_nl1000i_w_lg_w_lg_nll0Oii1l5335w5338w(0); + wire_nl1000i_w_lg_w_lg_w_lg_nliO0l1l5664w5665w5666w(0) <= wire_nl1000i_w_lg_w_lg_nliO0l1l5664w5665w(0) OR nliO0i0l; + wire_nl1000i_w_lg_w_lg_w_lg_nlO00O11i29542w29563w29564w(0) <= wire_nl1000i_w_lg_w_lg_nlO00O11i29542w29563w(0) OR nlO00lOlO; + wire_nl1000i_w_lg_w_lg_nliO0l1l5664w5665w(0) <= wire_nl1000i_w_lg_nliO0l1l5664w(0) OR nliO0i0O; + wire_nl1000i_w_lg_w_lg_nlli0i01i35924w35925w(0) <= wire_nl1000i_w_lg_nlli0i01i35924w(0) OR nlli0i1lO; + wire_nl1000i_w_lg_w_lg_nlli0i1lO36211w36220w(0) <= wire_nl1000i_w_lg_nlli0i1lO36211w(0) OR wire_nl1000i_w_lg_nlli1OO1l36219w(0); + wire_nl1000i_w_lg_w_lg_nlli0i1OO35926w35927w(0) <= wire_nl1000i_w_lg_nlli0i1OO35926w(0) OR nlli1OO1l; + wire_nl1000i_w_lg_w_lg_nlO00O11i29542w29543w(0) <= wire_nl1000i_w_lg_nlO00O11i29542w(0) OR nlO00lOOi; + wire_nl1000i_w_lg_w_lg_nlO00O11i29542w29563w(0) <= wire_nl1000i_w_lg_nlO00O11i29542w(0) OR nlO00lOOl; + wire_nl1000i_w_lg_n1l00ii4302w(0) <= n1l00ii OR niOO00i0l; + wire_nl1000i_w_lg_n1l011i4156w(0) <= n1l011i OR nlOiliii; + wire_nl1000i_w_lg_niOOi1i1l36213w(0) <= niOOi1i1l OR wire_w_lg_niOiOi1li36212w(0); + wire_nl1000i_w_lg_niOOi1i1l36205w(0) <= niOOi1i1l OR wire_w_lg_niOiOi1ll36204w(0); + wire_nl1000i_w_lg_nl11l1O1558w(0) <= nl11l1O OR nl11l1i; + wire_nl1000i_w_lg_nlilOO0ll42241w(0) <= nlilOO0ll OR niOiO1O0l; + wire_nl1000i_w_lg_nliO0l1l5664w(0) <= nliO0l1l OR nliO0iii; + wire_nl1000i_w_lg_nll0OiiO5649w(0) <= nll0OiiO OR nll0Oiil; + wire_nl1000i_w_lg_nll0Oili5679w(0) <= nll0Oili OR wire_nl1000i_w_lg_w_lg_nlli0ilOO5658w5678w(0); + wire_nl1000i_w_lg_nll0Oili5471w(0) <= nll0Oili OR nll0Oiil; + wire_nl1000i_w_lg_nlli0i01i35924w(0) <= nlli0i01i OR nlli0i1Ol; + wire_nl1000i_w_lg_nlli0i1lO36211w(0) <= nlli0i1lO OR wire_nl1000i_w_lg_w_lg_nlli0i01i36206w36210w(0); + wire_nl1000i_w_lg_nlli0i1OO35926w(0) <= nlli0i1OO OR nlli0i1Oi; + wire_nl1000i_w_lg_nlli1OO1l36219w(0) <= nlli1OO1l OR wire_nl1000i_w_lg_w_lg_nlli0i1OO36214w36218w(0); + wire_nl1000i_w_lg_nlliO11i5692w(0) <= nlliO11i OR nllilO1i; + wire_nl1000i_w_lg_nlliO1OO5141w(0) <= nlliO1OO OR nlliO1Ol; + wire_nl1000i_w_lg_nlll1il0l34806w(0) <= nlll1il0l OR nlll1il1l; + wire_nl1000i_w_lg_nlll1ilii34837w(0) <= nlll1ilii OR nlll1il1l; + wire_nl1000i_w_lg_nlO00lOOl29539w(0) <= nlO00lOOl OR nlO00lOlO; + wire_nl1000i_w_lg_nlO00O11i29542w(0) <= nlO00O11i OR nlO00lOOO; + wire_nl1000i_w_lg_nlOi1OiOi29020w(0) <= nlOi1OiOi OR nlOi1Oill; + wire_nl1000i_w_lg_nlOi1Ol1l29021w(0) <= nlOi1Ol1l OR wire_nl1000i_w_lg_nlOi1OiOi29020w(0); + wire_nl1000i_w_lg_nllliili4655w(0) <= nllliili XOR nllli0Oi; + wire_nl1000i_w_lg_nllliill4657w(0) <= nllliill XOR nllli0Ol; + wire_nl1000i_w_lg_nllliilO4660w(0) <= nllliilO XOR nllli0OO; + wire_nl1000i_w_lg_nllliiOi4663w(0) <= nllliiOi XOR nlllii1i; + PROCESS (core_clk, wire_nl11llO_PRN, wire_nl11llO_CLRN) + BEGIN + IF (wire_nl11llO_PRN = '0') THEN + n1illl0i <= '1'; + n1illl0l <= '1'; + n1illl0O <= '1'; + n1illl1O <= '1'; + n1illlii <= '1'; + n1illlil <= '1'; + n1illliO <= '1'; + n1illlli <= '1'; + n1illlll <= '1'; + n1illllO <= '1'; + n1illlOi <= '1'; + n1illlOl <= '1'; + n1illlOO <= '1'; + n1illO0i <= '1'; + n1illO0l <= '1'; + n1illO0O <= '1'; + n1illO1i <= '1'; + n1illO1l <= '1'; + n1illO1O <= '1'; + n1illOii <= '1'; + n1l011O <= '1'; + nil10lli <= '1'; + nil10lll <= '1'; + nil10llO <= '1'; + nil10lOi <= '1'; + nil10lOl <= '1'; + nil10lOO <= '1'; + nil10O0i <= '1'; + nil10O0l <= '1'; + nil10O0O <= '1'; + nil10O1i <= '1'; + nil10O1l <= '1'; + nil10O1O <= '1'; + nil10Oii <= '1'; + nil10Oil <= '1'; + nil10OiO <= '1'; + nil10Oli <= '1'; + nil10Oll <= '1'; + nil10OlO <= '1'; + nil10OOi <= '1'; + nil10OOl <= '1'; + nil10OOO <= '1'; + nil1100i <= '1'; + nil1100l <= '1'; + nil1100O <= '1'; + nil110ii <= '1'; + nil110il <= '1'; + nil110iO <= '1'; + nil110li <= '1'; + nil110ll <= '1'; + nil110lO <= '1'; + nil110Oi <= '1'; + nil110Ol <= '1'; + nil110OO <= '1'; + nil11i0i <= '1'; + nil11i0l <= '1'; + nil11i0O <= '1'; + nil11i1i <= '1'; + nil11i1l <= '1'; + nil11i1O <= '1'; + nil11iii <= '1'; + nil11iil <= '1'; + nil11iiO <= '1'; + nil1i10i <= '1'; + nil1i10l <= '1'; + nil1i11i <= '1'; + nil1i11l <= '1'; + nil1i11O <= '1'; + nl11lOi <= '1'; + nli1i00l <= '1'; + nli1i01i <= '1'; + nli1i01l <= '1'; + nlillOlOi <= '1'; + nlilOO0lO <= '1'; + nliOlilO <= '1'; + nll0Oill <= '1'; + nlliO01l <= '1'; + nlll1ilil <= '1'; + nlll1OOii <= '1'; + nlO00O11l <= '1'; + nlO0lllO <= '1'; + nlOil010l <= '1'; + nlOil011i <= '1'; + nlOil011l <= '1'; + ELSIF (wire_nl11llO_CLRN = '0') THEN + n1illl0i <= '0'; + n1illl0l <= '0'; + n1illl0O <= '0'; + n1illl1O <= '0'; + n1illlii <= '0'; + n1illlil <= '0'; + n1illliO <= '0'; + n1illlli <= '0'; + n1illlll <= '0'; + n1illllO <= '0'; + n1illlOi <= '0'; + n1illlOl <= '0'; + n1illlOO <= '0'; + n1illO0i <= '0'; + n1illO0l <= '0'; + n1illO0O <= '0'; + n1illO1i <= '0'; + n1illO1l <= '0'; + n1illO1O <= '0'; + n1illOii <= '0'; + n1l011O <= '0'; + nil10lli <= '0'; + nil10lll <= '0'; + nil10llO <= '0'; + nil10lOi <= '0'; + nil10lOl <= '0'; + nil10lOO <= '0'; + nil10O0i <= '0'; + nil10O0l <= '0'; + nil10O0O <= '0'; + nil10O1i <= '0'; + nil10O1l <= '0'; + nil10O1O <= '0'; + nil10Oii <= '0'; + nil10Oil <= '0'; + nil10OiO <= '0'; + nil10Oli <= '0'; + nil10Oll <= '0'; + nil10OlO <= '0'; + nil10OOi <= '0'; + nil10OOl <= '0'; + nil10OOO <= '0'; + nil1100i <= '0'; + nil1100l <= '0'; + nil1100O <= '0'; + nil110ii <= '0'; + nil110il <= '0'; + nil110iO <= '0'; + nil110li <= '0'; + nil110ll <= '0'; + nil110lO <= '0'; + nil110Oi <= '0'; + nil110Ol <= '0'; + nil110OO <= '0'; + nil11i0i <= '0'; + nil11i0l <= '0'; + nil11i0O <= '0'; + nil11i1i <= '0'; + nil11i1l <= '0'; + nil11i1O <= '0'; + nil11iii <= '0'; + nil11iil <= '0'; + nil11iiO <= '0'; + nil1i10i <= '0'; + nil1i10l <= '0'; + nil1i11i <= '0'; + nil1i11l <= '0'; + nil1i11O <= '0'; + nl11lOi <= '0'; + nli1i00l <= '0'; + nli1i01i <= '0'; + nli1i01l <= '0'; + nlillOlOi <= '0'; + nlilOO0lO <= '0'; + nliOlilO <= '0'; + nll0Oill <= '0'; + nlliO01l <= '0'; + nlll1ilil <= '0'; + nlll1OOii <= '0'; + nlO00O11l <= '0'; + nlO0lllO <= '0'; + nlOil010l <= '0'; + nlOil011i <= '0'; + nlOil011l <= '0'; + ELSIF (core_clk = '1' AND core_clk'event) THEN + n1illl0i <= wire_n1illOlO_dataout; + n1illl0l <= wire_n1illOOi_dataout; + n1illl0O <= wire_n1illOOl_dataout; + n1illl1O <= wire_n1illOll_dataout; + n1illlii <= wire_n1illOOO_dataout; + n1illlil <= wire_n1ilO11i_dataout; + n1illliO <= wire_n1ilO11l_dataout; + n1illlli <= wire_n1ilO11O_dataout; + n1illlll <= wire_n1ilO10i_dataout; + n1illllO <= wire_n1ilO10l_dataout; + n1illlOi <= wire_n1ilO10O_dataout; + n1illlOl <= wire_n1ilO1ii_dataout; + n1illlOO <= wire_n1ilO1il_dataout; + n1illO0i <= wire_n1ilO1lO_dataout; + n1illO0l <= wire_n1ilO1Oi_dataout; + n1illO0O <= wire_n1ilO1Ol_dataout; + n1illO1i <= wire_n1ilO1iO_dataout; + n1illO1l <= wire_n1ilO1li_dataout; + n1illO1O <= wire_n1ilO1ll_dataout; + n1illOii <= wire_n1ilO1OO_dataout; + n1l011O <= wire_n1l00lO_dataout; + nil10lli <= wire_nil1i1ii_dataout; + nil10lll <= wire_nil1i1il_dataout; + nil10llO <= wire_nil1i1iO_dataout; + nil10lOi <= wire_nil1i1li_dataout; + nil10lOl <= wire_nil1i1ll_dataout; + nil10lOO <= wire_nil1i1lO_dataout; + nil10O0i <= wire_nil1i01i_dataout; + nil10O0l <= wire_nil1i01l_dataout; + nil10O0O <= wire_nil1i01O_dataout; + nil10O1i <= wire_nil1i1Oi_dataout; + nil10O1l <= wire_nil1i1Ol_dataout; + nil10O1O <= wire_nil1i1OO_dataout; + nil10Oii <= wire_nil1i00i_dataout; + nil10Oil <= wire_nil1i00l_dataout; + nil10OiO <= wire_nil1i00O_dataout; + nil10Oli <= wire_nil1i0ii_dataout; + nil10Oll <= wire_nil1i0il_dataout; + nil10OlO <= wire_nil1i0iO_dataout; + nil10OOi <= wire_nil1i0li_dataout; + nil10OOl <= wire_nil1i0ll_dataout; + nil10OOO <= wire_nil1i0lO_dataout; + nil1100i <= wire_nil11ili_dataout; + nil1100l <= wire_nil11ill_dataout; + nil1100O <= wire_nil11ilO_dataout; + nil110ii <= wire_nil11iOi_dataout; + nil110il <= wire_nil11iOl_dataout; + nil110iO <= wire_nil11iOO_dataout; + nil110li <= wire_nil11l1i_dataout; + nil110ll <= wire_nil11l1l_dataout; + nil110lO <= wire_nil11l1O_dataout; + nil110Oi <= wire_nil11l0i_dataout; + nil110Ol <= wire_nil11l0l_dataout; + nil110OO <= wire_nil11l0O_dataout; + nil11i0i <= wire_nil11lli_dataout; + nil11i0l <= wire_nil11lll_dataout; + nil11i0O <= wire_nil11llO_dataout; + nil11i1i <= wire_nil11lii_dataout; + nil11i1l <= wire_nil11lil_dataout; + nil11i1O <= wire_nil11liO_dataout; + nil11iii <= wire_nil11lOi_dataout; + nil11iil <= wire_nil11lOl_dataout; + nil11iiO <= wire_nil1i10O_dataout; + nil1i10i <= wire_nil1ii1i_dataout; + nil1i10l <= wire_nil1ii1l_dataout; + nil1i11i <= wire_nil1i0Oi_dataout; + nil1i11l <= wire_nil1i0Ol_dataout; + nil1i11O <= wire_nil1i0OO_dataout; + nl11lOi <= wire_nl10iii_dataout; + nli1i00l <= wire_nli1iiil_dataout; + nli1i01i <= wire_nli1ii0i_dataout; + nli1i01l <= wire_nli1ii0l_dataout; + nlillOlOi <= wire_nlilO1i1i_dataout; + nlilOO0lO <= wire_nlilOOi1l_dataout; + nliOlilO <= wire_nll0Ol0O_dataout; + nll0Oill <= wire_nll0OO0O_dataout; + nlliO01l <= wire_nlliOlil_dataout; + nlll1ilil <= wire_nlll1iO1l_dataout; + nlll1OOii <= wire_nlll1OOll_dataout; + nlO00O11l <= wire_nlO00O1Oi_dataout; + nlO0lllO <= wire_nlO0lO1O_dataout; + nlOil010l <= wire_nlOil00OO_dataout; + nlOil011i <= wire_nlOil00ll_dataout; + nlOil011l <= wire_nlOil00lO_dataout; + END IF; + if (now = 0 ns) then + n1illl0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illl0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illl0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illl1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illlii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illlil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illliO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illlli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illlll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illllO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illlOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illlOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illlOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illO0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illO0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illO0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illO1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illO1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illO1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1illOii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + n1l011O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10lli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10lll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10llO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10lOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10lOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10lOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10O0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10O0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10O0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10O1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10O1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10O1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10Oii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10Oil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10OiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10Oli <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10Oll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10OlO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10OOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10OOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil10OOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1100i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1100l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1100O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110li <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110ll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110Oi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110Ol <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil110OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11i0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11i0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11i0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11i1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11i1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11i1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11iii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11iil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil11iiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1i10i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1i10l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1i11i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1i11l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nil1i11O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl11lOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i00l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i01i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i01l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlillOlOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlilOO0lO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliOlilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nll0Oill <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlliO01l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll1ilil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlll1OOii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO00O11l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlO0lllO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOil010l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOil011i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlOil011l <= '1' after 1 ps; + end if; + END PROCESS; + wire_nl11llO_CLRN <= (niOO0llil44 XOR niOO0llil43); + wire_nl11llO_PRN <= ((niOO0llii46 XOR niOO0llii45) AND wire_niO0010l_dataout); + wire_nl11llO_w_lg_w_lg_nlll1OOii34722w34723w(0) <= wire_nl11llO_w_lg_nlll1OOii34722w(0) AND niOO000Oi; + wire_nl11llO_w_lg_n1l011O4051w(0) <= n1l011O AND wire_nllli01O_w_lg_dataout4050w(0); + wire_nl11llO_w_lg_n1l011O4307w(0) <= n1l011O AND wire_w_lg_w_lg_niOO00lli4305w4306w(0); + wire_nl11llO_w_lg_nlliO01l5740w(0) <= nlliO01l AND nllilO1O; + wire_nl11llO_w_lg_nlliO01l5723w(0) <= nlliO01l AND nlliO10i; + wire_nl11llO_w_lg_nlll1OOii34722w(0) <= nlll1OOii AND wire_nlOl1l0Ol_dataout; + wire_nl11llO_w_lg_n1illl0i25375w(0) <= NOT n1illl0i; + wire_nl11llO_w_lg_n1illl0l25373w(0) <= NOT n1illl0l; + wire_nl11llO_w_lg_n1illl0O25371w(0) <= NOT n1illl0O; + wire_nl11llO_w_lg_n1illl1O25377w(0) <= NOT n1illl1O; + wire_nl11llO_w_lg_n1illlii25369w(0) <= NOT n1illlii; + wire_nl11llO_w_lg_n1illlil25367w(0) <= NOT n1illlil; + wire_nl11llO_w_lg_n1illliO25365w(0) <= NOT n1illliO; + wire_nl11llO_w_lg_n1illlli25363w(0) <= NOT n1illlli; + wire_nl11llO_w_lg_n1illlll25361w(0) <= NOT n1illlll; + wire_nl11llO_w_lg_n1illllO25359w(0) <= NOT n1illllO; + wire_nl11llO_w_lg_n1illlOi25357w(0) <= NOT n1illlOi; + wire_nl11llO_w_lg_n1illlOl25355w(0) <= NOT n1illlOl; + wire_nl11llO_w_lg_n1illlOO25353w(0) <= NOT n1illlOO; + wire_nl11llO_w_lg_n1illO0i25345w(0) <= NOT n1illO0i; + wire_nl11llO_w_lg_n1illO0l25343w(0) <= NOT n1illO0l; + wire_nl11llO_w_lg_n1illO0O25341w(0) <= NOT n1illO0O; + wire_nl11llO_w_lg_n1illO1i25351w(0) <= NOT n1illO1i; + wire_nl11llO_w_lg_n1illO1l25349w(0) <= NOT n1illO1l; + wire_nl11llO_w_lg_n1illO1O25347w(0) <= NOT n1illO1O; + wire_nl11llO_w_lg_n1illOii25340w(0) <= NOT n1illOii; + wire_nl11llO_w_lg_n1l011O4055w(0) <= NOT n1l011O; + wire_nl11llO_w_lg_nl11lOi2148w(0) <= NOT nl11lOi; + wire_nl11llO_w_lg_nlillOlOi42768w(0) <= NOT nlillOlOi; + wire_nl11llO_w_lg_nlll1ilil35500w(0) <= NOT nlll1ilil; + wire_nl11llO_w_lg_nlll1OOii34761w(0) <= NOT nlll1OOii; + wire_nl11llO_w_lg_nlO00O11l29156w(0) <= NOT nlO00O11l; + wire_nl11llO_w_lg_nlO0lllO4336w(0) <= NOT nlO0lllO; + wire_nl11llO_w_lg_w_lg_n1l011O4051w4052w(0) <= wire_nl11llO_w_lg_n1l011O4051w(0) OR nlOiliii; + wire_nl11llO_w_lg_w_lg_nlliO01l5740w5745w(0) <= wire_nl11llO_w_lg_nlliO01l5740w(0) OR wire_nlll0liO_w_lg_dataout5744w(0); + wire_nl11llO_w_lg_w_lg_w_lg_nlliO01l5740w5745w5748w(0) <= wire_nl11llO_w_lg_w_lg_nlliO01l5740w5745w(0) OR wire_nl1000i_w_lg_w_lg_nllilO1i5110w5747w(0); + wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nlliO01l5740w5745w5748w5752w(0) <= wire_nl11llO_w_lg_w_lg_w_lg_nlliO01l5740w5745w5748w(0) OR wire_nl1000i_w_lg_nlliO11l5751w(0); + wire_nl11llO_w_lg_w_lg_w1088w1089w1090w(0) <= wire_nl11llO_w_lg_w1088w1089w(0) OR nl11iOl; + wire_nl11llO_w_lg_w_lg_w1074w1075w1076w(0) <= wire_nl11llO_w_lg_w1074w1075w(0) OR nl11l0l; + wire_nl11llO_w_lg_w1088w1089w(0) <= wire_nl11llO_w1088w(0) OR nl11iOO; + wire_nl11llO_w_lg_w1074w1075w(0) <= wire_nl11llO_w1074w(0) OR nl11l0O; + wire_nl11llO_w1088w(0) <= wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nl11lOi1070w1085w1086w1087w(0) OR nl11l1O; + wire_nl11llO_w1074w(0) <= wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nl11lOi1070w1071w1072w1073w(0) OR nl11lii; + wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nl11lOi1070w1085w1086w1087w(0) <= wire_nl11llO_w_lg_w_lg_w_lg_nl11lOi1070w1085w1086w(0) OR nl11l0i; + wire_nl11llO_w_lg_w_lg_w_lg_w_lg_nl11lOi1070w1071w1072w1073w(0) <= wire_nl11llO_w_lg_w_lg_w_lg_nl11lOi1070w1071w1072w(0) OR nl11lil; + wire_nl11llO_w_lg_w_lg_w_lg_nl11lOi1070w1085w1086w(0) <= wire_nl11llO_w_lg_w_lg_nl11lOi1070w1085w(0) OR nl11lii; + wire_nl11llO_w_lg_w_lg_w_lg_nl11lOi1070w1071w1072w(0) <= wire_nl11llO_w_lg_w_lg_nl11lOi1070w1071w(0) OR nl11liO; + wire_nl11llO_w_lg_w_lg_w_lg_nlll1ilil34878w34879w34880w(0) <= wire_nl11llO_w_lg_w_lg_nlll1ilil34878w34879w(0) OR nlll1il1l; + wire_nl11llO_w_lg_w_lg_nl11lOi1070w1085w(0) <= wire_nl11llO_w_lg_nl11lOi1070w(0) OR nl11lil; + wire_nl11llO_w_lg_w_lg_nl11lOi1070w1071w(0) <= wire_nl11llO_w_lg_nl11lOi1070w(0) OR nl11lli; + wire_nl11llO_w_lg_w_lg_nlillOlOi42755w42756w(0) <= wire_nl11llO_w_lg_nlillOlOi42755w(0) OR nlillOlil; + wire_nl11llO_w_lg_w_lg_nlillOlOi42452w42453w(0) <= wire_nl11llO_w_lg_nlillOlOi42452w(0) OR nlillOlli; + wire_nl11llO_w_lg_w_lg_nlliO01l5221w5223w(0) <= wire_nl11llO_w_lg_nlliO01l5221w(0) OR wire_nlill0Oll_w_lg_nl1ll0lOl5222w(0); + wire_nl11llO_w_lg_w_lg_nlll1ilil34878w34879w(0) <= wire_nl11llO_w_lg_nlll1ilil34878w(0) OR nlll1il0O; + wire_nl11llO_w_lg_nl11lOi1070w(0) <= nl11lOi OR nl11lll; + wire_nl11llO_w_lg_nlillOlOi42755w(0) <= nlillOlOi OR nlillOliO; + wire_nl11llO_w_lg_nlillOlOi42452w(0) <= nlillOlOi OR nlillOlll; + wire_nl11llO_w_lg_nlliO01l5221w(0) <= nlliO01l OR nlliO01i; + wire_nl11llO_w_lg_nlliO01l5197w(0) <= nlliO01l OR nlliO1Ol; + wire_nl11llO_w_lg_nlliO01l5207w(0) <= nlliO01l OR nlliO1OO; + wire_nl11llO_w_lg_nlll1ilil34878w(0) <= nlll1ilil OR nlll1ilii; + PROCESS (wire_niO0011O_dataout, wire_niO01Oli_dataout) + BEGIN + IF (wire_niO01Oli_dataout = '0') THEN + nliii0O1l <= '0'; + nliii0OOi <= '0'; + nliii0OOl <= '0'; + nliii0OOO <= '0'; + nliiii00i <= '0'; + nliiii00l <= '0'; + nliiii00O <= '0'; + nliiii01i <= '0'; + nliiii01l <= '0'; + nliiii01O <= '0'; + nliiii0ii <= '0'; + nliiii0il <= '0'; + nliiii0iO <= '0'; + nliiii0li <= '0'; + nliiii0ll <= '0'; + nliiii0lO <= '0'; + nliiii0Oi <= '0'; + nliiii0Ol <= '0'; + nliiii0OO <= '0'; + nliiii10i <= '0'; + nliiii10l <= '0'; + nliiii10O <= '0'; + nliiii11i <= '0'; + nliiii11l <= '0'; + nliiii11O <= '0'; + nliiii1ii <= '0'; + nliiii1il <= '0'; + nliiii1iO <= '0'; + nliiii1li <= '0'; + nliiii1ll <= '0'; + nliiii1lO <= '0'; + nliiii1Oi <= '0'; + nliiii1Ol <= '0'; + nliiii1OO <= '0'; + nliiiii0i <= '0'; + nliiiii0l <= '0'; + nliiiii0O <= '0'; + nliiiii1i <= '0'; + nliiiii1l <= '0'; + nliiiii1O <= '0'; + nliiiiiii <= '0'; + nliiiiiil <= '0'; + nliiiiiiO <= '0'; + nliiiiili <= '0'; + nliiiiill <= '0'; + nliiiiilO <= '0'; + nliiiiiOi <= '0'; + nliiiiiOl <= '0'; + nliiiiiOO <= '0'; + nliiiil0i <= '0'; + nliiiil0l <= '0'; + nliiiil0O <= '0'; + nliiiil1i <= '0'; + nliiiil1l <= '0'; + nliiiil1O <= '0'; + nliiiilii <= '0'; + nliiiilil <= '0'; + nliiiiliO <= '0'; + nliiiilli <= '0'; + nliiiilll <= '0'; + nliiiillO <= '0'; + nliiiilOi <= '0'; + nliiiilOl <= '0'; + nliiiiO1i <= '0'; + ELSIF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN + IF (niOill0li = '1') THEN + nliii0O1l <= wire_nliiiOill_dataout; + nliii0OOi <= wire_nliiiOilO_dataout; + nliii0OOl <= wire_nliiiOiOi_dataout; + nliii0OOO <= wire_nliiiOiOl_dataout; + nliiii00i <= wire_nliiiOO1O_dataout; + nliiii00l <= wire_nliiiOO0i_dataout; + nliiii00O <= wire_nliiiOO0l_dataout; + nliiii01i <= wire_nliiiOlOO_dataout; + nliiii01l <= wire_nliiiOO1i_dataout; + nliiii01O <= wire_nliiiOO1l_dataout; + nliiii0ii <= wire_nliiiOO0O_dataout; + nliiii0il <= wire_nliiiOOii_dataout; + nliiii0iO <= wire_nliiiOOil_dataout; + nliiii0li <= wire_nliiiOOiO_dataout; + nliiii0ll <= wire_nliiiOOli_dataout; + nliiii0lO <= wire_nliiiOOll_dataout; + nliiii0Oi <= wire_nliiiOOlO_dataout; + nliiii0Ol <= wire_nliiiOOOi_dataout; + nliiii0OO <= wire_nliiiOOOl_dataout; + nliiii10i <= wire_nliiiOl1O_dataout; + nliiii10l <= wire_nliiiOl0i_dataout; + nliiii10O <= wire_nliiiOl0l_dataout; + nliiii11i <= wire_nliiiOiOO_dataout; + nliiii11l <= wire_nliiiOl1i_dataout; + nliiii11O <= wire_nliiiOl1l_dataout; + nliiii1ii <= wire_nliiiOl0O_dataout; + nliiii1il <= wire_nliiiOlii_dataout; + nliiii1iO <= wire_nliiiOlil_dataout; + nliiii1li <= wire_nliiiOliO_dataout; + nliiii1ll <= wire_nliiiOlli_dataout; + nliiii1lO <= wire_nliiiOlll_dataout; + nliiii1Oi <= wire_nliiiOllO_dataout; + nliiii1Ol <= wire_nliiiOlOi_dataout; + nliiii1OO <= wire_nliiiOlOl_dataout; + nliiiii0i <= wire_nliil111O_dataout; + nliiiii0l <= wire_nliil110i_dataout; + nliiiii0O <= wire_nliil110l_dataout; + nliiiii1i <= wire_nliiiOOOO_dataout; + nliiiii1l <= wire_nliil111i_dataout; + nliiiii1O <= wire_nliil111l_dataout; + nliiiiiii <= wire_nliil110O_dataout; + nliiiiiil <= wire_nliil11ii_dataout; + nliiiiiiO <= wire_nliil11il_dataout; + nliiiiili <= wire_nliil11iO_dataout; + nliiiiill <= wire_nliil11li_dataout; + nliiiiilO <= wire_nliil11ll_dataout; + nliiiiiOi <= wire_nliil11lO_dataout; + nliiiiiOl <= wire_nliil11Oi_dataout; + nliiiiiOO <= wire_nliil11Ol_dataout; + nliiiil0i <= wire_nliil101O_dataout; + nliiiil0l <= wire_nliil100i_dataout; + nliiiil0O <= wire_nliil100l_dataout; + nliiiil1i <= wire_nliil11OO_dataout; + nliiiil1l <= wire_nliil101i_dataout; + nliiiil1O <= wire_nliil101l_dataout; + nliiiilii <= wire_nliil100O_dataout; + nliiiilil <= wire_nliil10ii_dataout; + nliiiiliO <= wire_nliil10il_dataout; + nliiiilli <= wire_nliil10iO_dataout; + nliiiilll <= wire_nliil10li_dataout; + nliiiillO <= wire_nliil10ll_dataout; + nliiiilOi <= wire_nliil10lO_dataout; + nliiiilOl <= wire_nliil10Oi_dataout; + nliiiiO1i <= wire_nliil10Ol_dataout; + END IF; + END IF; + END PROCESS; + wire_nliiiilOO_w_lg_nliii0O1l44660w(0) <= NOT nliii0O1l; + wire_nliiiilOO_w_lg_nliii0OOi44659w(0) <= NOT nliii0OOi; + wire_nliiiilOO_w_lg_nliii0OOl44658w(0) <= NOT nliii0OOl; + wire_nliiiilOO_w_lg_nliii0OOO44657w(0) <= NOT nliii0OOO; + wire_nliiiilOO_w_lg_nliiii00i44638w(0) <= NOT nliiii00i; + wire_nliiiilOO_w_lg_nliiii00l44637w(0) <= NOT nliiii00l; + wire_nliiiilOO_w_lg_nliiii00O44636w(0) <= NOT nliiii00O; + wire_nliiiilOO_w_lg_nliiii01i44641w(0) <= NOT nliiii01i; + wire_nliiiilOO_w_lg_nliiii01l44640w(0) <= NOT nliiii01l; + wire_nliiiilOO_w_lg_nliiii01O44639w(0) <= NOT nliiii01O; + wire_nliiiilOO_w_lg_nliiii0ii44635w(0) <= NOT nliiii0ii; + wire_nliiiilOO_w_lg_nliiii0il44634w(0) <= NOT nliiii0il; + wire_nliiiilOO_w_lg_nliiii0iO44633w(0) <= NOT nliiii0iO; + wire_nliiiilOO_w_lg_nliiii0li44632w(0) <= NOT nliiii0li; + wire_nliiiilOO_w_lg_nliiii0ll44631w(0) <= NOT nliiii0ll; + wire_nliiiilOO_w_lg_nliiii0lO44630w(0) <= NOT nliiii0lO; + wire_nliiiilOO_w_lg_nliiii0Oi44629w(0) <= NOT nliiii0Oi; + wire_nliiiilOO_w_lg_nliiii0Ol44627w(0) <= NOT nliiii0Ol; + wire_nliiiilOO_w_lg_nliiii0OO44626w(0) <= NOT nliiii0OO; + wire_nliiiilOO_w_lg_nliiii10i44653w(0) <= NOT nliiii10i; + wire_nliiiilOO_w_lg_nliiii10l44652w(0) <= NOT nliiii10l; + wire_nliiiilOO_w_lg_nliiii10O44651w(0) <= NOT nliiii10O; + wire_nliiiilOO_w_lg_nliiii11i44656w(0) <= NOT nliiii11i; + wire_nliiiilOO_w_lg_nliiii11l44655w(0) <= NOT nliiii11l; + wire_nliiiilOO_w_lg_nliiii11O44654w(0) <= NOT nliiii11O; + wire_nliiiilOO_w_lg_nliiii1ii44650w(0) <= NOT nliiii1ii; + wire_nliiiilOO_w_lg_nliiii1il44649w(0) <= NOT nliiii1il; + wire_nliiiilOO_w_lg_nliiii1iO44648w(0) <= NOT nliiii1iO; + wire_nliiiilOO_w_lg_nliiii1li44647w(0) <= NOT nliiii1li; + wire_nliiiilOO_w_lg_nliiii1ll44646w(0) <= NOT nliiii1ll; + wire_nliiiilOO_w_lg_nliiii1lO44645w(0) <= NOT nliiii1lO; + wire_nliiiilOO_w_lg_nliiii1Oi44644w(0) <= NOT nliiii1Oi; + wire_nliiiilOO_w_lg_nliiii1Ol44643w(0) <= NOT nliiii1Ol; + wire_nliiiilOO_w_lg_nliiii1OO44642w(0) <= NOT nliiii1OO; + wire_nliiiilOO_w_lg_nliiiii0i44622w(0) <= NOT nliiiii0i; + wire_nliiiilOO_w_lg_nliiiii0l44621w(0) <= NOT nliiiii0l; + wire_nliiiilOO_w_lg_nliiiii0O44620w(0) <= NOT nliiiii0O; + wire_nliiiilOO_w_lg_nliiiii1i44625w(0) <= NOT nliiiii1i; + wire_nliiiilOO_w_lg_nliiiii1l44624w(0) <= NOT nliiiii1l; + wire_nliiiilOO_w_lg_nliiiii1O44623w(0) <= NOT nliiiii1O; + wire_nliiiilOO_w_lg_nliiiiiii44619w(0) <= NOT nliiiiiii; + wire_nliiiilOO_w_lg_nliiiiiil44618w(0) <= NOT nliiiiiil; + wire_nliiiilOO_w_lg_nliiiiiiO44617w(0) <= NOT nliiiiiiO; + wire_nliiiilOO_w_lg_nliiiiili44616w(0) <= NOT nliiiiili; + wire_nliiiilOO_w_lg_nliiiiill44615w(0) <= NOT nliiiiill; + wire_nliiiilOO_w_lg_nliiiiilO44614w(0) <= NOT nliiiiilO; + wire_nliiiilOO_w_lg_nliiiiiOi44613w(0) <= NOT nliiiiiOi; + wire_nliiiilOO_w_lg_nliiiiiOl44612w(0) <= NOT nliiiiiOl; + wire_nliiiilOO_w_lg_nliiiiiOO44611w(0) <= NOT nliiiiiOO; + wire_nliiiilOO_w_lg_nliiiil0i44607w(0) <= NOT nliiiil0i; + wire_nliiiilOO_w_lg_nliiiil0l44606w(0) <= NOT nliiiil0l; + wire_nliiiilOO_w_lg_nliiiil0O44605w(0) <= NOT nliiiil0O; + wire_nliiiilOO_w_lg_nliiiil1i44610w(0) <= NOT nliiiil1i; + wire_nliiiilOO_w_lg_nliiiil1l44609w(0) <= NOT nliiiil1l; + wire_nliiiilOO_w_lg_nliiiil1O44608w(0) <= NOT nliiiil1O; + wire_nliiiilOO_w_lg_nliiiilii44604w(0) <= NOT nliiiilii; + wire_nliiiilOO_w_lg_nliiiilil44603w(0) <= NOT nliiiilil; + wire_nliiiilOO_w_lg_nliiiiliO44602w(0) <= NOT nliiiiliO; + wire_nliiiilOO_w_lg_nliiiilli44601w(0) <= NOT nliiiilli; + wire_nliiiilOO_w_lg_nliiiilll44600w(0) <= NOT nliiiilll; + wire_nliiiilOO_w_lg_nliiiillO44599w(0) <= NOT nliiiillO; + wire_nliiiilOO_w_lg_nliiiilOi44598w(0) <= NOT nliiiilOi; + wire_nliiiilOO_w_lg_nliiiilOl44597w(0) <= NOT nliiiilOl; + wire_nliiiilOO_w_lg_nliiiiO1i44596w(0) <= NOT nliiiiO1i; + PROCESS (wire_niO0011O_dataout, wire_niO01Oli_dataout) + BEGIN + IF (wire_niO01Oli_dataout = '0') THEN + nli11O01O <= '1'; + nli11O1OO <= '1'; + nliiO0i0l <= '1'; + nliiO0i0O <= '1'; + nliiO0ili <= '1'; + nliiO0ilO <= '1'; + nliiO0iOi <= '1'; + nliiO0iOO <= '1'; + nliiO10ii <= '1'; + ELSIF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN + nli11O01O <= wire_nli11Oili_dataout; + nli11O1OO <= wire_nli11Oiii_dataout; + nliiO0i0l <= wire_nliiO0l0i_dataout; + nliiO0i0O <= wire_nliiO0l0l_dataout; + nliiO0ili <= wire_nliiO0lli_dataout; + nliiO0ilO <= wire_nliiO0lOi_dataout; + nliiO0iOi <= wire_nliiO0O1i_dataout; + nliiO0iOO <= nliiO0iOO; + nliiO10ii <= wire_nliiO1lll_dataout; + END IF; + if (now = 0 ns) then + nli11O01O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli11O1OO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiO0i0l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiO0i0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiO0ili <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiO0ilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiO0iOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiO0iOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliiO10ii <= '1' after 1 ps; + end if; + END PROCESS; + wire_nliiO0iOl_w_lg_nliiO0i0l44503w(0) <= NOT nliiO0i0l; + wire_nliiO0iOl_w_lg_nliiO0i0O44504w(0) <= NOT nliiO0i0O; + wire_nliiO0iOl_w_lg_nliiO0ili44284w(0) <= NOT nliiO0ili; + wire_nliiO0iOl_w_lg_nliiO0ilO44505w(0) <= NOT nliiO0ilO; + wire_nliiO0iOl_w_lg_nliiO0iOi44506w(0) <= NOT nliiO0iOi; + wire_nliiO0iOl_w_lg_nliiO0iOO44507w(0) <= NOT nliiO0iOO; + wire_nliiO0iOl_w_lg_nliiO10ii44514w(0) <= NOT nliiO10ii; + PROCESS (wire_niO0011O_dataout, wire_niO01Oli_dataout) + BEGIN + IF (wire_niO01Oli_dataout = '0') THEN + nl0ilOllO <= '0'; + nl0iO0Oii <= '0'; + nl0iO0Oil <= '0'; + nl0iO0OiO <= '0'; + nl0iO0Oli <= '0'; + nl0iO0Oll <= '0'; + nl0iO0OlO <= '0'; + nl0iO0OOi <= '0'; + nl0iO0OOl <= '0'; + nl0iO0OOO <= '0'; + nl0iOi11i <= '0'; + nl0iOi11l <= '0'; + nl0iOi11O <= '0'; + nli11ilOi <= '0'; + nli11l1ll <= '0'; + nli11l1lO <= '0'; + nli11li1i <= '0'; + nli11O00i <= '0'; + nli11O00l <= '0'; + nli11O00O <= '0'; + nli11O01i <= '0'; + nli11O01l <= '0'; + nli11O1il <= '0'; + nli11O1iO <= '0'; + nli11O1li <= '0'; + nli11O1ll <= '0'; + nli11O1lO <= '0'; + nli11O1Oi <= '0'; + nli11O1Ol <= '0'; + nli1ilO1O <= '0'; + nlii0OO0l <= '0'; + nlii0OO0O <= '0'; + nlii0OOii <= '0'; + nlii0OOil <= '0'; + nlii0OOiO <= '0'; + nlii0OOli <= '0'; + nlii0OOll <= '0'; + nlii0OOlO <= '0'; + nlii0OOOi <= '0'; + nlii0OOOl <= '0'; + nlii0OOOO <= '0'; + nlii1l1ll <= '0'; + nliii001i <= '0'; + nliii001l <= '0'; + nliii001O <= '0'; + nliii01Oi <= '0'; + nliii01Ol <= '0'; + nliii01OO <= '0'; + nliii100i <= '0'; + nliii100l <= '0'; + nliii100O <= '0'; + nliii101i <= '0'; + nliii101l <= '0'; + nliii101O <= '0'; + nliii110i <= '0'; + nliii110l <= '0'; + nliii110O <= '0'; + nliii111i <= '0'; + nliii111l <= '0'; + nliii111O <= '0'; + nliii11ii <= '0'; + nliii11il <= '0'; + nliii11iO <= '0'; + nliii11li <= '0'; + nliii11ll <= '0'; + nliii11lO <= '0'; + nliii11Oi <= '0'; + nliii11Ol <= '0'; + nliii11OO <= '0'; + nliiiiO0i <= '0'; + nliiiiO0l <= '0'; + nliiiiO0O <= '0'; + nliiiiO1l <= '0'; + nliiiiO1O <= '0'; + nliiiiOii <= '0'; + nliiiiOil <= '0'; + nliiiiOiO <= '0'; + nliiiiOli <= '0'; + nliiiiOll <= '0'; + nliiiiOlO <= '0'; + nliiiiOOi <= '0'; + nliiiiOOl <= '0'; + nliiiiOOO <= '0'; + nliiil00i <= '0'; + nliiil00l <= '0'; + nliiil00O <= '0'; + nliiil01i <= '0'; + nliiil01l <= '0'; + nliiil01O <= '0'; + nliiil0ii <= '0'; + nliiil0il <= '0'; + nliiil0iO <= '0'; + nliiil0li <= '0'; + nliiil0ll <= '0'; + nliiil0lO <= '0'; + nliiil0Oi <= '0'; + nliiil0Ol <= '0'; + nliiil0OO <= '0'; + nliiil10i <= '0'; + nliiil10l <= '0'; + nliiil10O <= '0'; + nliiil11i <= '0'; + nliiil11l <= '0'; + nliiil11O <= '0'; + nliiil1ii <= '0'; + nliiil1il <= '0'; + nliiil1iO <= '0'; + nliiil1li <= '0'; + nliiil1ll <= '0'; + nliiil1lO <= '0'; + nliiil1Oi <= '0'; + nliiil1Ol <= '0'; + nliiil1OO <= '0'; + nliiili0i <= '0'; + nliiili0l <= '0'; + nliiili0O <= '0'; + nliiili1i <= '0'; + nliiili1l <= '0'; + nliiili1O <= '0'; + nliiiliii <= '0'; + nliiiliil <= '0'; + nliiiliiO <= '0'; + nliiilili <= '0'; + nliiilill <= '0'; + nliiililO <= '0'; + nliiiliOi <= '0'; + nliiiliOl <= '0'; + nliiiliOO <= '0'; + nliiill0i <= '0'; + nliiill0l <= '0'; + nliiill0O <= '0'; + nliiill1i <= '0'; + nliiill1l <= '0'; + nliiill1O <= '0'; + nliiO011i <= '0'; + nliiO011l <= '0'; + nliiO0i0i <= '0'; + nliiO0iii <= '0'; + nliiO0iil <= '0'; + nliiO0iiO <= '0'; + nliiO0ill <= '0'; + nliiO0l1i <= '0'; + nliiO0O0O <= '0'; + nliiO0Oii <= '0'; + nliiO0Oil <= '0'; + nliiO0OiO <= '0'; + nliiO0Oli <= '0'; + nliiO0Oll <= '0'; + nliiO0OlO <= '0'; + nliiO0OOi <= '0'; + nliiO0OOl <= '0'; + nliiO0OOO <= '0'; + nliiO100i <= '0'; + nliiO100l <= '0'; + nliiO100O <= '0'; + nliiO101i <= '0'; + nliiO101l <= '0'; + nliiO101O <= '0'; + nliiO11OO <= '0'; + nliiO1l0l <= '0'; + nliiO1l0O <= '0'; + nliiO1lii <= '0'; + nliiO1lil <= '0'; + nliiO1liO <= '0'; + nliiO1lli <= '0'; + nliiO1OlO <= '0'; + nliiO1OOi <= '0'; + nliiO1OOl <= '0'; + nliiO1OOO <= '0'; + nliiOi11i <= '0'; + nliiOi11l <= '0'; + nliiOii0i <= '0'; + nliiOii0l <= '0'; + nliiOii0O <= '0'; + nliiOii1i <= '0'; + nliiOii1l <= '0'; + nliiOii1O <= '0'; + nliiOiiii <= '0'; + nliiOiiil <= '0'; + nliiOiiiO <= '0'; + nliiOiili <= '0'; + nliiOiill <= '0'; + nliiOiiOi <= '0'; + ELSIF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN + nl0ilOllO <= wire_nl0iOi10l_dataout; + nl0iO0Oii <= wire_nl0iOi10O_dataout; + nl0iO0Oil <= wire_nl0iOi1ii_dataout; + nl0iO0OiO <= wire_nl0iOi1il_dataout; + nl0iO0Oli <= wire_nl0iOi1iO_dataout; + nl0iO0Oll <= wire_nl0iOi1li_dataout; + nl0iO0OlO <= wire_nl0iOi1ll_dataout; + nl0iO0OOi <= wire_nl0iOi1lO_dataout; + nl0iO0OOl <= wire_nl0iOi1Oi_dataout; + nl0iO0OOO <= wire_nl0iOi1Ol_dataout; + nl0iOi11i <= wire_nl0iOi1OO_dataout; + nl0iOi11l <= wire_nl0iOi01i_dataout; + nl0iOi11O <= wire_nl0iOi01l_dataout; + nli11ilOi <= wire_nli11l1Oi_dataout; + nli11l1ll <= wire_nli11l01O_dataout; + nli11l1lO <= niOOllOO; + nli11li1i <= wire_nli11O0il_dataout; + nli11O00i <= wire_nli11Oill_dataout; + nli11O00l <= wire_nli11OilO_dataout; + nli11O00O <= wire_nli11OiOi_dataout; + nli11O01i <= wire_nli11Oiil_dataout; + nli11O01l <= wire_nli11OiiO_dataout; + nli11O1il <= wire_nli11O0iO_dataout; + nli11O1iO <= wire_nli11O0li_dataout; + nli11O1li <= wire_nli11O0ll_dataout; + nli11O1ll <= wire_nli11O0lO_dataout; + nli11O1lO <= wire_nli11O0Oi_dataout; + nli11O1Oi <= wire_nli11Oi0i_dataout; + nli11O1Ol <= wire_nli11Oi0O_dataout; + nli1ilO1O <= wire_nli1iOi1i_dataout; + nlii0OO0l <= wire_nliii10il_dataout; + nlii0OO0O <= wire_nliii10iO_dataout; + nlii0OOii <= wire_nliii10li_dataout; + nlii0OOil <= wire_nliii10ll_dataout; + nlii0OOiO <= wire_nliii10lO_dataout; + nlii0OOli <= wire_nliii10Oi_dataout; + nlii0OOll <= wire_nliii10Ol_dataout; + nlii0OOlO <= wire_nliii10OO_dataout; + nlii0OOOi <= wire_nliii1i1i_dataout; + nlii0OOOl <= wire_nliii1i1l_dataout; + nlii0OOOO <= wire_nliii1i1O_dataout; + nlii1l1ll <= wire_nliii10ii_dataout; + nliii001i <= wire_nliii0ili_dataout; + nliii001l <= wire_nliii0l1l_dataout; + nliii001O <= wire_nliii0lii_dataout; + nliii01Oi <= wire_nliii00iO_dataout; + nliii01Ol <= wire_nliii00Ol_dataout; + nliii01OO <= wire_nliii0i0l_dataout; + nliii100i <= wire_nliii1OiO_dataout; + nliii100l <= wire_nliii1Oli_dataout; + nliii100O <= wire_nliii000l_dataout; + nliii101i <= wire_nliii1O0O_dataout; + nliii101l <= wire_nliii1Oii_dataout; + nliii101O <= wire_nliii1Oil_dataout; + nliii110i <= wire_nliii1iii_dataout; + nliii110l <= wire_nliii1lli_dataout; + nliii110O <= wire_nliii1lll_dataout; + nliii111i <= wire_nliii1i0i_dataout; + nliii111l <= wire_nliii1i0l_dataout; + nliii111O <= wire_nliii1i0O_dataout; + nliii11ii <= wire_nliii1llO_dataout; + nliii11il <= wire_nliii1lOi_dataout; + nliii11iO <= wire_nliii1lOl_dataout; + nliii11li <= wire_nliii1lOO_dataout; + nliii11ll <= wire_nliii1O1i_dataout; + nliii11lO <= wire_nliii1O1l_dataout; + nliii11Oi <= wire_nliii1O1O_dataout; + nliii11Ol <= wire_nliii1O0i_dataout; + nliii11OO <= wire_nliii1O0l_dataout; + nliiiiO0i <= wire_nliiilliO_dataout; + nliiiiO0l <= wire_nliiillli_dataout; + nliiiiO0O <= wire_nliiillll_dataout; + nliiiiO1l <= wire_nliiillii_dataout; + nliiiiO1O <= wire_nliiillil_dataout; + nliiiiOii <= wire_nliiilllO_dataout; + nliiiiOil <= wire_nliiillOi_dataout; + nliiiiOiO <= wire_nliiillOl_dataout; + nliiiiOli <= wire_nliiillOO_dataout; + nliiiiOll <= wire_nliiilO1i_dataout; + nliiiiOlO <= wire_nliiilO1l_dataout; + nliiiiOOi <= wire_nliiilO1O_dataout; + nliiiiOOl <= wire_nliiilO0i_dataout; + nliiiiOOO <= wire_nliiilO0l_dataout; + nliiil00i <= wire_nliiiO1iO_dataout; + nliiil00l <= wire_nliiiO1li_dataout; + nliiil00O <= wire_nliiiO1ll_dataout; + nliiil01i <= wire_nliiiO10O_dataout; + nliiil01l <= wire_nliiiO1ii_dataout; + nliiil01O <= wire_nliiiO1il_dataout; + nliiil0ii <= wire_nliiiO1lO_dataout; + nliiil0il <= wire_nliiiO1Oi_dataout; + nliiil0iO <= wire_nliiiO1Ol_dataout; + nliiil0li <= wire_nliiiO1OO_dataout; + nliiil0ll <= wire_nliiiO01i_dataout; + nliiil0lO <= wire_nliiiO01l_dataout; + nliiil0Oi <= wire_nliiiO01O_dataout; + nliiil0Ol <= wire_nliiiO00i_dataout; + nliiil0OO <= wire_nliiiO00l_dataout; + nliiil10i <= wire_nliiilOiO_dataout; + nliiil10l <= wire_nliiilOli_dataout; + nliiil10O <= wire_nliiilOll_dataout; + nliiil11i <= wire_nliiilO0O_dataout; + nliiil11l <= wire_nliiilOii_dataout; + nliiil11O <= wire_nliiilOil_dataout; + nliiil1ii <= wire_nliiilOlO_dataout; + nliiil1il <= wire_nliiilOOi_dataout; + nliiil1iO <= wire_nliiilOOl_dataout; + nliiil1li <= wire_nliiilOOO_dataout; + nliiil1ll <= wire_nliiiO11i_dataout; + nliiil1lO <= wire_nliiiO11l_dataout; + nliiil1Oi <= wire_nliiiO11O_dataout; + nliiil1Ol <= wire_nliiiO10i_dataout; + nliiil1OO <= wire_nliiiO10l_dataout; + nliiili0i <= wire_nliiiO0iO_dataout; + nliiili0l <= wire_nliiiO0li_dataout; + nliiili0O <= wire_nliiiO0ll_dataout; + nliiili1i <= wire_nliiiO00O_dataout; + nliiili1l <= wire_nliiiO0ii_dataout; + nliiili1O <= wire_nliiiO0il_dataout; + nliiiliii <= wire_nliiiO0lO_dataout; + nliiiliil <= wire_nliiiO0Oi_dataout; + nliiiliiO <= wire_nliiiO0Ol_dataout; + nliiilili <= wire_nliiiO0OO_dataout; + nliiilill <= wire_nliiiOi1i_dataout; + nliiililO <= wire_nliiiOi1l_dataout; + nliiiliOi <= wire_nliiiOi1O_dataout; + nliiiliOl <= wire_nliiiOi0i_dataout; + nliiiliOO <= wire_nliiiOi0l_dataout; + nliiill0i <= wire_nliiiOiiO_dataout; + nliiill0l <= wire_nliiiOili_dataout; + nliiill0O <= wire_nliiO10il_dataout; + nliiill1i <= wire_nliiiOi0O_dataout; + nliiill1l <= wire_nliiiOiii_dataout; + nliiill1O <= wire_nliiiOiil_dataout; + nliiO011i <= wire_nliiO00iO_dataout; + nliiO011l <= wire_nliiO0l1l_dataout; + nliiO0i0i <= wire_nliiO0l1O_dataout; + nliiO0iii <= wire_nliiO0l0O_dataout; + nliiO0iil <= wire_nliiO0lil_dataout; + nliiO0iiO <= wire_nliiO0liO_dataout; + nliiO0ill <= wire_nliiO0lll_dataout; + nliiO0l1i <= wire_nliiOi11O_dataout; + nliiO0O0O <= wire_nliiOi10i_dataout; + nliiO0Oii <= wire_nliiOi10l_dataout; + nliiO0Oil <= wire_nliiOi10O_dataout; + nliiO0OiO <= wire_nliiOi1ii_dataout; + nliiO0Oli <= wire_nliiOi1iO_dataout; + nliiO0Oll <= wire_nliiOi1li_dataout; + nliiO0OlO <= wire_nliiOi1ll_dataout; + nliiO0OOi <= wire_nliiOi1lO_dataout; + nliiO0OOl <= wire_nliiOi1Ol_dataout; + nliiO0OOO <= wire_nliiOi0ii_dataout; + nliiO100i <= wire_nliiO1i0O_dataout; + nliiO100l <= wire_nliiO1iii_dataout; + nliiO100O <= wire_nliiO1iil_dataout; + nliiO101i <= wire_nliiO1i1O_dataout; + nliiO101l <= wire_nliiO1i0i_dataout; + nliiO101O <= wire_nliiO1i0l_dataout; + nliiO11OO <= wire_nliiO10Oi_dataout; + nliiO1l0l <= wire_nliiO1llO_dataout; + nliiO1l0O <= wire_nliiO1lOi_dataout; + nliiO1lii <= wire_nliiO1lOO_dataout; + nliiO1lil <= wire_nliiO1O1i_dataout; + nliiO1liO <= wire_nliiO1O1l_dataout; + nliiO1lli <= wire_nliiO011O_dataout; + nliiO1OlO <= wire_nliiO01ii_dataout; + nliiO1OOi <= wire_nliiO01ll_dataout; + nliiO1OOl <= wire_nliiO001i_dataout; + nliiO1OOO <= wire_nliiO000l_dataout; + nliiOi11i <= nliiOi11i; + nliiOi11l <= wire_nliiOiiOl_dataout; + nliiOii0i <= wire_nliiOiO0l_dataout; + nliiOii0l <= wire_nliiOiOlO_dataout; + nliiOii0O <= wire_nliiOl11O_dataout; + nliiOii1i <= wire_nliiOil0l_dataout; + nliiOii1l <= wire_nliiOillO_dataout; + nliiOii1O <= wire_nliiOiO1i_dataout; + nliiOiiii <= wire_nliiOl10l_dataout; + nliiOiiil <= wire_nliiOl1ll_dataout; + nliiOiiiO <= wire_nliiOl01l_dataout; + nliiOiili <= wire_nliiOl0li_dataout; + nliiOiill <= wire_nliiOli1O_dataout; + nliiOiiOi <= wire_nliiOliii_dataout; + END IF; + END PROCESS; + wire_nliiOiilO_w_lg_w_lg_nliiO0Oii44493w45047w(0) <= wire_nliiOiilO_w_lg_nliiO0Oii44493w(0) AND niOO10lOi; + wire_nliiOiilO_w_lg_w_lg_nliiO0Oil44494w45046w(0) <= wire_nliiOiilO_w_lg_nliiO0Oil44494w(0) AND niOO10llO; + wire_nliiOiilO_w_lg_w_lg_nliiO0Oll44497w45043w(0) <= wire_nliiOiilO_w_lg_nliiO0Oll44497w(0) AND niOO10liO; + wire_nliiOiilO_w_lg_w_lg_nliiO0OOl44500w45040w(0) <= wire_nliiOiilO_w_lg_nliiO0OOl44500w(0) AND nliiOOill; + wire_nliiOiilO_w_lg_nli11ilOi46310w(0) <= NOT nli11ilOi; + wire_nliiOiilO_w_lg_nli11l1ll46317w(0) <= NOT nli11l1ll; + wire_nliiOiilO_w_lg_nli11l1lO48215w(0) <= NOT nli11l1lO; + wire_nliiOiilO_w_lg_nli11li1i46531w(0) <= NOT nli11li1i; + wire_nliiOiilO_w_lg_nli11O1il46532w(0) <= NOT nli11O1il; + wire_nliiOiilO_w_lg_nli11O1iO46533w(0) <= NOT nli11O1iO; + wire_nliiOiilO_w_lg_nli11O1li46536w(0) <= NOT nli11O1li; + wire_nliiOiilO_w_lg_nli11O1ll46535w(0) <= NOT nli11O1ll; + wire_nliiOiilO_w_lg_nli11O1lO46534w(0) <= NOT nli11O1lO; + wire_nliiOiilO_w_lg_nli11O1Oi46539w(0) <= NOT nli11O1Oi; + wire_nliiOiilO_w_lg_nli1ilO1O46374w(0) <= NOT nli1ilO1O; + wire_nliiOiilO_w_lg_nlii0OO0l44688w(0) <= NOT nlii0OO0l; + wire_nliiOiilO_w_lg_nlii0OO0O44687w(0) <= NOT nlii0OO0O; + wire_nliiOiilO_w_lg_nlii0OOii44686w(0) <= NOT nlii0OOii; + wire_nliiOiilO_w_lg_nlii0OOil44685w(0) <= NOT nlii0OOil; + wire_nliiOiilO_w_lg_nlii0OOiO44684w(0) <= NOT nlii0OOiO; + wire_nliiOiilO_w_lg_nlii0OOli44683w(0) <= NOT nlii0OOli; + wire_nliiOiilO_w_lg_nlii0OOll44682w(0) <= NOT nlii0OOll; + wire_nliiOiilO_w_lg_nlii0OOlO44681w(0) <= NOT nlii0OOlO; + wire_nliiOiilO_w_lg_nlii0OOOi44680w(0) <= NOT nlii0OOOi; + wire_nliiOiilO_w_lg_nlii0OOOl44679w(0) <= NOT nlii0OOOl; + wire_nliiOiilO_w_lg_nlii0OOOO44678w(0) <= NOT nlii0OOOO; + wire_nliiOiilO_w_lg_nlii1l1ll44689w(0) <= NOT nlii1l1ll; + wire_nliiOiilO_w_lg_nliii001i44467w(0) <= NOT nliii001i; + wire_nliiOiilO_w_lg_nliii001l44673w(0) <= NOT nliii001l; + wire_nliiOiilO_w_lg_nliii001O44476w(0) <= NOT nliii001O; + wire_nliiOiilO_w_lg_nliii01Oi44670w(0) <= NOT nliii01Oi; + wire_nliiOiilO_w_lg_nliii01Ol44671w(0) <= NOT nliii01Ol; + wire_nliiOiilO_w_lg_nliii01OO44672w(0) <= NOT nliii01OO; + wire_nliiOiilO_w_lg_nliii100i44691w(0) <= NOT nliii100i; + wire_nliiOiilO_w_lg_nliii100l44690w(0) <= NOT nliii100l; + wire_nliiOiilO_w_lg_nliii100O44669w(0) <= NOT nliii100O; + wire_nliiOiilO_w_lg_nliii101i44694w(0) <= NOT nliii101i; + wire_nliiOiilO_w_lg_nliii101l44693w(0) <= NOT nliii101l; + wire_nliiOiilO_w_lg_nliii101O44692w(0) <= NOT nliii101O; + wire_nliiOiilO_w_lg_nliii110i44674w(0) <= NOT nliii110i; + wire_nliiOiilO_w_lg_nliii110l44705w(0) <= NOT nliii110l; + wire_nliiOiilO_w_lg_nliii110O44704w(0) <= NOT nliii110O; + wire_nliiOiilO_w_lg_nliii111i44677w(0) <= NOT nliii111i; + wire_nliiOiilO_w_lg_nliii111l44676w(0) <= NOT nliii111l; + wire_nliiOiilO_w_lg_nliii111O44675w(0) <= NOT nliii111O; + wire_nliiOiilO_w_lg_nliii11ii44703w(0) <= NOT nliii11ii; + wire_nliiOiilO_w_lg_nliii11il44702w(0) <= NOT nliii11il; + wire_nliiOiilO_w_lg_nliii11iO44701w(0) <= NOT nliii11iO; + wire_nliiOiilO_w_lg_nliii11li44700w(0) <= NOT nliii11li; + wire_nliiOiilO_w_lg_nliii11ll44699w(0) <= NOT nliii11ll; + wire_nliiOiilO_w_lg_nliii11lO44698w(0) <= NOT nliii11lO; + wire_nliiOiilO_w_lg_nliii11Oi44697w(0) <= NOT nliii11Oi; + wire_nliiOiilO_w_lg_nliii11Ol44696w(0) <= NOT nliii11Ol; + wire_nliiOiilO_w_lg_nliii11OO44695w(0) <= NOT nliii11OO; + wire_nliiOiilO_w_lg_nliiiiO0i44592w(0) <= NOT nliiiiO0i; + wire_nliiOiilO_w_lg_nliiiiO0l44591w(0) <= NOT nliiiiO0l; + wire_nliiOiilO_w_lg_nliiiiO0O44590w(0) <= NOT nliiiiO0O; + wire_nliiOiilO_w_lg_nliiiiO1l44594w(0) <= NOT nliiiiO1l; + wire_nliiOiilO_w_lg_nliiiiO1O44593w(0) <= NOT nliiiiO1O; + wire_nliiOiilO_w_lg_nliiiiOii44589w(0) <= NOT nliiiiOii; + wire_nliiOiilO_w_lg_nliiiiOil44588w(0) <= NOT nliiiiOil; + wire_nliiOiilO_w_lg_nliiiiOiO44587w(0) <= NOT nliiiiOiO; + wire_nliiOiilO_w_lg_nliiiiOli44586w(0) <= NOT nliiiiOli; + wire_nliiOiilO_w_lg_nliiiiOll44585w(0) <= NOT nliiiiOll; + wire_nliiOiilO_w_lg_nliiiiOlO44584w(0) <= NOT nliiiiOlO; + wire_nliiOiilO_w_lg_nliiiiOOi44583w(0) <= NOT nliiiiOOi; + wire_nliiOiilO_w_lg_nliiiiOOl44582w(0) <= NOT nliiiiOOl; + wire_nliiOiilO_w_lg_nliiiiOOO44581w(0) <= NOT nliiiiOOO; + wire_nliiOiilO_w_lg_nliiil00i44561w(0) <= NOT nliiil00i; + wire_nliiOiilO_w_lg_nliiil00l44560w(0) <= NOT nliiil00l; + wire_nliiOiilO_w_lg_nliiil00O44559w(0) <= NOT nliiil00O; + wire_nliiOiilO_w_lg_nliiil01i44565w(0) <= NOT nliiil01i; + wire_nliiOiilO_w_lg_nliiil01l44564w(0) <= NOT nliiil01l; + wire_nliiOiilO_w_lg_nliiil01O44563w(0) <= NOT nliiil01O; + wire_nliiOiilO_w_lg_nliiil0ii44558w(0) <= NOT nliiil0ii; + wire_nliiOiilO_w_lg_nliiil0il44557w(0) <= NOT nliiil0il; + wire_nliiOiilO_w_lg_nliiil0iO44556w(0) <= NOT nliiil0iO; + wire_nliiOiilO_w_lg_nliiil0li44555w(0) <= NOT nliiil0li; + wire_nliiOiilO_w_lg_nliiil0ll44554w(0) <= NOT nliiil0ll; + wire_nliiOiilO_w_lg_nliiil0lO44553w(0) <= NOT nliiil0lO; + wire_nliiOiilO_w_lg_nliiil0Oi44552w(0) <= NOT nliiil0Oi; + wire_nliiOiilO_w_lg_nliiil0Ol44551w(0) <= NOT nliiil0Ol; + wire_nliiOiilO_w_lg_nliiil0OO44550w(0) <= NOT nliiil0OO; + wire_nliiOiilO_w_lg_nliiil10i44577w(0) <= NOT nliiil10i; + wire_nliiOiilO_w_lg_nliiil10l44576w(0) <= NOT nliiil10l; + wire_nliiOiilO_w_lg_nliiil10O44575w(0) <= NOT nliiil10O; + wire_nliiOiilO_w_lg_nliiil11i44580w(0) <= NOT nliiil11i; + wire_nliiOiilO_w_lg_nliiil11l44579w(0) <= NOT nliiil11l; + wire_nliiOiilO_w_lg_nliiil11O44578w(0) <= NOT nliiil11O; + wire_nliiOiilO_w_lg_nliiil1ii44574w(0) <= NOT nliiil1ii; + wire_nliiOiilO_w_lg_nliiil1il44573w(0) <= NOT nliiil1il; + wire_nliiOiilO_w_lg_nliiil1iO44572w(0) <= NOT nliiil1iO; + wire_nliiOiilO_w_lg_nliiil1li44571w(0) <= NOT nliiil1li; + wire_nliiOiilO_w_lg_nliiil1ll44570w(0) <= NOT nliiil1ll; + wire_nliiOiilO_w_lg_nliiil1lO44569w(0) <= NOT nliiil1lO; + wire_nliiOiilO_w_lg_nliiil1Oi44568w(0) <= NOT nliiil1Oi; + wire_nliiOiilO_w_lg_nliiil1Ol44567w(0) <= NOT nliiil1Ol; + wire_nliiOiilO_w_lg_nliiil1OO44566w(0) <= NOT nliiil1OO; + wire_nliiOiilO_w_lg_nliiili0i44546w(0) <= NOT nliiili0i; + wire_nliiOiilO_w_lg_nliiili0l44545w(0) <= NOT nliiili0l; + wire_nliiOiilO_w_lg_nliiili0O44544w(0) <= NOT nliiili0O; + wire_nliiOiilO_w_lg_nliiili1i44549w(0) <= NOT nliiili1i; + wire_nliiOiilO_w_lg_nliiili1l44548w(0) <= NOT nliiili1l; + wire_nliiOiilO_w_lg_nliiili1O44547w(0) <= NOT nliiili1O; + wire_nliiOiilO_w_lg_nliiiliii44543w(0) <= NOT nliiiliii; + wire_nliiOiilO_w_lg_nliiiliil44542w(0) <= NOT nliiiliil; + wire_nliiOiilO_w_lg_nliiiliiO44541w(0) <= NOT nliiiliiO; + wire_nliiOiilO_w_lg_nliiilili44540w(0) <= NOT nliiilili; + wire_nliiOiilO_w_lg_nliiilill44539w(0) <= NOT nliiilill; + wire_nliiOiilO_w_lg_nliiililO44538w(0) <= NOT nliiililO; + wire_nliiOiilO_w_lg_nliiiliOi44537w(0) <= NOT nliiiliOi; + wire_nliiOiilO_w_lg_nliiiliOl44536w(0) <= NOT nliiiliOl; + wire_nliiOiilO_w_lg_nliiiliOO44535w(0) <= NOT nliiiliOO; + wire_nliiOiilO_w_lg_nliiill0i44531w(0) <= NOT nliiill0i; + wire_nliiOiilO_w_lg_nliiill0l44530w(0) <= NOT nliiill0l; + wire_nliiOiilO_w_lg_nliiill0O44520w(0) <= NOT nliiill0O; + wire_nliiOiilO_w_lg_nliiill1i44534w(0) <= NOT nliiill1i; + wire_nliiOiilO_w_lg_nliiill1l44533w(0) <= NOT nliiill1l; + wire_nliiOiilO_w_lg_nliiill1O44532w(0) <= NOT nliiill1O; + wire_nliiOiilO_w_lg_nliiO011i44513w(0) <= NOT nliiO011i; + wire_nliiOiilO_w_lg_nliiO011l44316w(0) <= NOT nliiO011l; + wire_nliiOiilO_w_lg_nliiO0i0i44311w(0) <= NOT nliiO0i0i; + wire_nliiOiilO_w_lg_nliiO0iii44300w(0) <= NOT nliiO0iii; + wire_nliiOiilO_w_lg_nliiO0iil44294w(0) <= NOT nliiO0iil; + wire_nliiOiilO_w_lg_nliiO0iiO44289w(0) <= NOT nliiO0iiO; + wire_nliiOiilO_w_lg_nliiO0ill44279w(0) <= NOT nliiO0ill; + wire_nliiOiilO_w_lg_nliiO0l1i44491w(0) <= NOT nliiO0l1i; + wire_nliiOiilO_w_lg_nliiO0O0O44492w(0) <= NOT nliiO0O0O; + wire_nliiOiilO_w_lg_nliiO0Oii44493w(0) <= NOT nliiO0Oii; + wire_nliiOiilO_w_lg_nliiO0Oil44494w(0) <= NOT nliiO0Oil; + wire_nliiOiilO_w_lg_nliiO0OiO44495w(0) <= NOT nliiO0OiO; + wire_nliiOiilO_w_lg_nliiO0Oli44496w(0) <= NOT nliiO0Oli; + wire_nliiOiilO_w_lg_nliiO0Oll44497w(0) <= NOT nliiO0Oll; + wire_nliiOiilO_w_lg_nliiO0OlO44498w(0) <= NOT nliiO0OlO; + wire_nliiOiilO_w_lg_nliiO0OOi44499w(0) <= NOT nliiO0OOi; + wire_nliiOiilO_w_lg_nliiO0OOl44500w(0) <= NOT nliiO0OOl; + wire_nliiOiilO_w_lg_nliiO0OOO44501w(0) <= NOT nliiO0OOO; + wire_nliiOiilO_w_lg_nliiO100i44525w(0) <= NOT nliiO100i; + wire_nliiOiilO_w_lg_nliiO100l44524w(0) <= NOT nliiO100l; + wire_nliiOiilO_w_lg_nliiO100O44367w(0) <= NOT nliiO100O; + wire_nliiOiilO_w_lg_nliiO101i44528w(0) <= NOT nliiO101i; + wire_nliiOiilO_w_lg_nliiO101l44527w(0) <= NOT nliiO101l; + wire_nliiOiilO_w_lg_nliiO101O44526w(0) <= NOT nliiO101O; + wire_nliiOiilO_w_lg_nliiO11OO44522w(0) <= NOT nliiO11OO; + wire_nliiOiilO_w_lg_nliiO1l0l44515w(0) <= NOT nliiO1l0l; + wire_nliiOiilO_w_lg_nliiO1l0O44516w(0) <= NOT nliiO1l0O; + wire_nliiOiilO_w_lg_nliiO1lii44517w(0) <= NOT nliiO1lii; + wire_nliiOiilO_w_lg_nliiO1lil44518w(0) <= NOT nliiO1lil; + wire_nliiOiilO_w_lg_nliiO1liO44519w(0) <= NOT nliiO1liO; + wire_nliiOiilO_w_lg_nliiO1lli44508w(0) <= NOT nliiO1lli; + wire_nliiOiilO_w_lg_nliiO1OlO44509w(0) <= NOT nliiO1OlO; + wire_nliiOiilO_w_lg_nliiO1OOi44510w(0) <= NOT nliiO1OOi; + wire_nliiOiilO_w_lg_nliiO1OOl44511w(0) <= NOT nliiO1OOl; + wire_nliiOiilO_w_lg_nliiO1OOO44512w(0) <= NOT nliiO1OOO; + wire_nliiOiilO_w_lg_nliiOi11i44502w(0) <= NOT nliiOi11i; + wire_nliiOiilO_w_lg_nliiOi11l44479w(0) <= NOT nliiOi11l; + wire_nliiOiilO_w_lg_nliiOii0i44483w(0) <= NOT nliiOii0i; + wire_nliiOiilO_w_lg_nliiOii0l44484w(0) <= NOT nliiOii0l; + wire_nliiOiilO_w_lg_nliiOii1i44480w(0) <= NOT nliiOii1i; + wire_nliiOiilO_w_lg_nliiOii1l44481w(0) <= NOT nliiOii1l; + wire_nliiOiilO_w_lg_nliiOii1O44482w(0) <= NOT nliiOii1O; + wire_nliiOiilO_w_lg_nliiOiiil44486w(0) <= NOT nliiOiiil; + wire_nliiOiilO_w_lg_nliiOiiiO44487w(0) <= NOT nliiOiiiO; + wire_nliiOiilO_w_lg_nliiOiili44488w(0) <= NOT nliiOiili; + wire_nliiOiilO_w_lg_nliiOiill44489w(0) <= NOT nliiOiill; + wire_nliiOiilO_w_lg_nliiOiiOi44490w(0) <= NOT nliiOiiOi; + PROCESS (wire_niO0011O_dataout, wire_niO0010l_dataout) + BEGIN + IF (wire_niO0010l_dataout = '0') THEN + nl010Oi1i <= '1'; + nl10liOii <= '1'; + nl10lliii <= '1'; + nl10lliOl <= '1'; + nl111i1il <= '1'; + nl111iOiO <= '1'; + nl11OO0ii <= '1'; + nl11OOi1O <= '1'; + nl1l1iO0O <= '1'; + nl1l1iOll <= '1'; + nl1ll0iOO <= '1'; + nl1OilO0i <= '1'; + nl1OOii1O <= '1'; + nli1i010i <= '1'; + nli1i010l <= '1'; + nli1i010O <= '1'; + nli1i011l <= '1'; + nli1i011O <= '1'; + nli1i01ii <= '1'; + nli1i01il <= '1'; + nli1i01iO <= '1'; + nli1iOi0O <= '1'; + nli1iOiil <= '1'; + nli1iOiOi <= '1'; + nli1lilll <= '1'; + nli1lillO <= '1'; + nli1lilOi <= '1'; + nli1lilOl <= '1'; + nli1lilOO <= '1'; + nli1liO1i <= '1'; + nli1liO1l <= '1'; + nlil00ilO <= '1'; + nliliO10l <= '1'; + ELSIF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN + nl010Oi1i <= wire_nl010OO1i_dataout; + nl10liOii <= wire_nl10liO1O_dataout; + nl10lliii <= wire_nl10lllii_dataout; + nl10lliOl <= wire_nl10lllOl_dataout; + nl111i1il <= wire_nl111iOll_dataout; + nl111iOiO <= wire_nl111iOlO_dataout; + nl11OO0ii <= wire_nl11OOOlO_dataout; + nl11OOi1O <= wire_nl10111il_dataout; + nl1l1iO0O <= wire_nl1l0O11O_dataout; + nl1l1iOll <= wire_nl1l0O1il_dataout; + nl1ll0iOO <= wire_nl1ll0OiO_dataout; + nl1OilO0i <= wire_nl1OiO1iO_dataout; + nl1OOii1O <= wire_nl1OOiOll_dataout; + nli1i010i <= wire_nli1i00iO_dataout; + nli1i010l <= wire_nli1i00li_dataout; + nli1i010O <= wire_nli1i00ll_dataout; + nli1i011l <= wire_nli1i00ii_dataout; + nli1i011O <= wire_nli1i00il_dataout; + nli1i01ii <= wire_nli1i00lO_dataout; + nli1i01il <= wire_nli1i00Oi_dataout; + nli1i01iO <= wire_nli1i00Ol_dataout; + nli1iOi0O <= wire_nli1iOl0l_dataout; + nli1iOiil <= wire_nli1iOlil_dataout; + nli1iOiOi <= wire_nli1iOlOi_dataout; + nli1lilll <= wire_nli1liO0l_dataout; + nli1lillO <= wire_nli1liO0O_dataout; + nli1lilOi <= wire_nli1liOii_dataout; + nli1lilOl <= wire_nli1liOil_dataout; + nli1lilOO <= wire_nli1liOiO_dataout; + nli1liO1i <= wire_nli1liOli_dataout; + nli1liO1l <= wire_nli1liOll_dataout; + nlil00ilO <= wire_nlil00lOi_dataout; + nliliO10l <= wire_nliliO00l_dataout; + END IF; + if (now = 0 ns) then + nl010Oi1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl10liOii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl10lliii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl10lliOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl111i1il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl111iOiO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl11OO0ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl11OOi1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1l1iO0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1l1iOll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1ll0iOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1OilO0i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nl1OOii1O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i010i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i010l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i010O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i011l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i011O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i01ii <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i01il <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1i01iO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1iOi0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1iOiil <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1iOiOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1lilll <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1lillO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1lilOi <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1lilOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1lilOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1liO1i <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nli1liO1l <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlil00ilO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nliliO10l <= '1' after 1 ps; + end if; + END PROCESS; + wire_nliliO10i_w_lg_w_lg_w_lg_w_lg_nl1OOii1O8962w8964w8965w8966w(0) <= wire_nliliO10i_w_lg_w_lg_w_lg_nl1OOii1O8962w8964w8965w(0) AND nl1ll0iOO; + wire_nliliO10i_w_lg_w_lg_w_lg_nl1OOii1O8962w8964w8965w(0) <= wire_nliliO10i_w_lg_w_lg_nl1OOii1O8962w8964w(0) AND nl1OilO0i; + wire_nliliO10i_w_lg_w_lg_nl1OOii1O8962w8964w(0) <= wire_nliliO10i_w_lg_nl1OOii1O8962w(0) AND wire_nlill0Oll_w_lg_nl1OO010i8963w(0); + wire_nliliO10i_w_lg_nl1OilO0i56530w(0) <= nl1OilO0i AND wire_w_lg_w_lg_niOi1OllO54888w56529w(0); + wire_nliliO10i_w_lg_nl1OOii1O8962w(0) <= nl1OOii1O AND wire_nlill0Oll_w_lg_nl1OOii1l8961w(0); + wire_nliliO10i_w_lg_nl10liOii43901w(0) <= NOT nl10liOii; + wire_nliliO10i_w_lg_nl111iOiO43397w(0) <= NOT nl111iOiO; + wire_nliliO10i_w_lg_nl11OO0ii59868w(0) <= NOT nl11OO0ii; + wire_nliliO10i_w_lg_nl11OOi1O60227w(0) <= NOT nl11OOi1O; + wire_nliliO10i_w_lg_nl1ll0iOO55045w(0) <= NOT nl1ll0iOO; + wire_nliliO10i_w_lg_nl1OilO0i55044w(0) <= NOT nl1OilO0i; + wire_nliliO10i_w_lg_nl1OOii1O54515w(0) <= NOT nl1OOii1O; + wire_nliliO10i_w_lg_nli1iOi0O46371w(0) <= NOT nli1iOi0O; + wire_nliliO10i_w_lg_nli1iOiil46373w(0) <= NOT nli1iOiil; + wire_nliliO10i_w_lg_nli1iOiOi46376w(0) <= NOT nli1iOiOi; + wire_nliliO10i_w_lg_nli1lilll47853w(0) <= NOT nli1lilll; + wire_nliliO10i_w_lg_nli1lillO47852w(0) <= NOT nli1lillO; + wire_nliliO10i_w_lg_nli1lilOi47851w(0) <= NOT nli1lilOi; + wire_nliliO10i_w_lg_nli1lilOl47850w(0) <= NOT nli1lilOl; + wire_nliliO10i_w_lg_nli1lilOO47849w(0) <= NOT nli1lilOO; + wire_nliliO10i_w_lg_nli1liO1i47848w(0) <= NOT nli1liO1i; + wire_nliliO10i_w_lg_nli1liO1l47847w(0) <= NOT nli1liO1l; + wire_nliliO10i_w_lg_w_lg_nl10liOii43901w43902w(0) <= wire_nliliO10i_w_lg_nl10liOii43901w(0) OR nlil00ill; + wire_nliliO10i_w_lg_w_lg_nl1ll0iOO55586w55587w(0) <= wire_nliliO10i_w_lg_nl1ll0iOO55586w(0) OR nl1ll0ilO; + wire_nliliO10i_w_lg_nl1ll0iOO55831w(0) <= nl1ll0iOO OR wire_nlill0Oll_w_lg_nl1ll0ilO55830w(0); + wire_nliliO10i_w_lg_nl1ll0iOO55586w(0) <= nl1ll0iOO OR nl1ll0iOl; + PROCESS (wire_niO0011O_dataout, wire_niO0010l_dataout) + BEGIN + IF (wire_niO0010l_dataout = '0') THEN + nl00l0O0i <= '0'; + nl00l0O0l <= '0'; + nl00l0O0O <= '0'; + nl00l0Oii <= '0'; + nl00l0Oil <= '0'; + nl00l0OiO <= '0'; + nl00l0Oli <= '0'; + nl00l0Oll <= '0'; + nl00l0OlO <= '0'; + nl00l0OOi <= '0'; + nl00l0OOl <= '0'; + nl00l0OOO <= '0'; + nl00l11il <= '0'; + nl00l11iO <= '0'; + nl00li00i <= '0'; + nl00li00l <= '0'; + nl00li00O <= '0'; + nl00li01i <= '0'; + nl00li01l <= '0'; + nl00li01O <= '0'; + nl00li0ii <= '0'; + nl00li0il <= '0'; + nl00li0iO <= '0'; + nl00li0li <= '0'; + nl00li0ll <= '0'; + nl00li0lO <= '0'; + nl00li0Oi <= '0'; + nl00li0Ol <= '0'; + nl00li0OO <= '0'; + nl00li10i <= '0'; + nl00li10l <= '0'; + nl00li10O <= '0'; + nl00li11i <= '0'; + nl00li11l <= '0'; + nl00li11O <= '0'; + nl00li1ii <= '0'; + nl00li1il <= '0'; + nl00li1iO <= '0'; + nl00li1li <= '0'; + nl00li1ll <= '0'; + nl00li1lO <= '0'; + nl00li1Oi <= '0'; + nl00li1Ol <= '0'; + nl00li1OO <= '0'; + nl00lii0i <= '0'; + nl00lii0l <= '0'; + nl00lii0O <= '0'; + nl00lii1i <= '0'; + nl00lii1l <= '0'; + nl00lii1O <= '0'; + nl00liiii <= '0'; + nl00liiil <= '0'; + nl00liiiO <= '0'; + nl00liili <= '0'; + nl00liill <= '0'; + nl00liilO <= '0'; + nl00liiOi <= '0'; + nl00liiOl <= '0'; + nl00liiOO <= '0'; + nl00lil0i <= '0'; + nl00lil0l <= '0'; + nl00lil0O <= '0'; + nl00lil1i <= '0'; + nl00lil1l <= '0'; + nl00lil1O <= '0'; + nl00lilii <= '0'; + nl00lilil <= '0'; + nl00liliO <= '0'; + nl00lilli <= '0'; + nl00lilll <= '0'; + nl00lillO <= '0'; + nl00lilOi <= '0'; + nl00lilOl <= '0'; + nl00lilOO <= '0'; + nl00liO0i <= '0'; + nl00liO0l <= '0'; + nl00liO0O <= '0'; + nl00liO1i <= '0'; + nl00liO1l <= '0'; + nl00liO1O <= '0'; + nl00liOii <= '0'; + nl00liOil <= '0'; + nl00liOiO <= '0'; + nl00liOli <= '0'; + nl00liOll <= '0'; + nl00liOlO <= '0'; + nl00liOOi <= '0'; + nl00liOOl <= '0'; + nl00liOOO <= '0'; + nl00ll00i <= '0'; + nl00ll00l <= '0'; + nl00ll00O <= '0'; + nl00ll01i <= '0'; + nl00ll01l <= '0'; + nl00ll01O <= '0'; + nl00ll0ii <= '0'; + nl00ll0il <= '0'; + nl00ll0iO <= '0'; + nl00ll0li <= '0'; + nl00ll0ll <= '0'; + nl00ll0lO <= '0'; + nl00ll0Oi <= '0'; + nl00ll0Ol <= '0'; + nl00ll0OO <= '0'; + nl00ll10i <= '0'; + nl00ll10l <= '0'; + nl00ll10O <= '0'; + nl00ll11i <= '0'; + nl00ll11l <= '0'; + nl00ll11O <= '0'; + nl00ll1ii <= '0'; + nl00ll1il <= '0'; + nl00ll1iO <= '0'; + nl00ll1li <= '0'; + nl00ll1ll <= '0'; + nl00ll1lO <= '0'; + nl00ll1Oi <= '0'; + nl00ll1Ol <= '0'; + nl00ll1OO <= '0'; + nl00lli0i <= '0'; + nl00lli0l <= '0'; + nl00lli0O <= '0'; + nl00lli1i <= '0'; + nl00lli1l <= '0'; + nl00lli1O <= '0'; + nl00lliii <= '0'; + nl00lliil <= '0'; + nl00lliiO <= '0'; + nl00llili <= '0'; + nl00llill <= '0'; + nl00llilO <= '0'; + nl00lliOi <= '0'; + nl00lliOl <= '0'; + nl00lliOO <= '0'; + nl00lll0i <= '0'; + nl00lll0l <= '0'; + nl00lll0O <= '0'; + nl00lll1i <= '0'; + nl00lll1l <= '0'; + nl00lll1O <= '0'; + nl00lllii <= '0'; + nl00lllil <= '0'; + nl010000i <= '0'; + nl010000l <= '0'; + nl010000O <= '0'; + nl010001i <= '0'; + nl010001l <= '0'; + nl010001O <= '0'; + nl01000ii <= '0'; + nl01000il <= '0'; + nl01000iO <= '0'; + nl01000li <= '0'; + nl01000ll <= '0'; + nl01000lO <= '0'; + nl01000Oi <= '0'; + nl01000Ol <= '0'; + nl01000OO <= '0'; + nl010010i <= '0'; + nl010010l <= '0'; + nl010010O <= '0'; + nl010011i <= '0'; + nl010011l <= '0'; + nl010011O <= '0'; + nl01001ii <= '0'; + nl01001il <= '0'; + nl01001iO <= '0'; + nl01001li <= '0'; + nl01001ll <= '0'; + nl01001lO <= '0'; + nl01001Oi <= '0'; + nl01001Ol <= '0'; + nl01001OO <= '0'; + nl0100i0i <= '0'; + nl0100i0l <= '0'; + nl0100i0O <= '0'; + nl0100i1i <= '0'; + nl0100i1l <= '0'; + nl0100i1O <= '0'; + nl0100iii <= '0'; + nl0100iil <= '0'; + nl0100iiO <= '0'; + nl0100ili <= '0'; + nl0100ill <= '0'; + nl0100ilO <= '0'; + nl0100iOi <= '0'; + nl0100iOl <= '0'; + nl0100iOO <= '0'; + nl0100l0i <= '0'; + nl0100l0l <= '0'; + nl0100l0O <= '0'; + nl0100l1i <= '0'; + nl0100l1l <= '0'; + nl0100l1O <= '0'; + nl0100lii <= '0'; + nl0100lil <= '0'; + nl0100liO <= '0'; + nl0100lli <= '0'; + nl0100lll <= '0'; + nl0100llO <= '0'; + nl0100lOi <= '0'; + nl0100lOl <= '0'; + nl0100lOO <= '0'; + nl0100O0i <= '0'; + nl0100O0l <= '0'; + nl0100O0O <= '0'; + nl0100O1i <= '0'; + nl0100O1l <= '0'; + nl0100O1O <= '0'; + nl0101lOl <= '0'; + nl0101lOO <= '0'; + nl0101O0i <= '0'; + nl0101O0l <= '0'; + nl0101O0O <= '0'; + nl0101O1i <= '0'; + nl0101O1l <= '0'; + nl0101O1O <= '0'; + nl0101Oii <= '0'; + nl0101Oil <= '0'; + nl0101OiO <= '0'; + nl0101Oli <= '0'; + nl0101Oll <= '0'; + nl0101OlO <= '0'; + nl0101OOi <= '0'; + nl0101OOl <= '0'; + nl0101OOO <= '0'; + nl010Olil <= '0'; + nl010OliO <= '0'; + nl010Olli <= '0'; + nl010Olll <= '0'; + nl010OllO <= '0'; + nl010OlOi <= '0'; + nl010OlOl <= '0'; + nl010OlOO <= '0'; + nl0111iil <= '0'; + nl0111iiO <= '0'; + nl0111ili <= '0'; + nl0111ill <= '0'; + nl0111ilO <= '0'; + nl0111iOi <= '0'; + nl0111iOl <= '0'; + nl0111iOO <= '0'; + nl0111l0i <= '0'; + nl0111l0l <= '0'; + nl0111l0O <= '0'; + nl0111l1i <= '0'; + nl0111l1l <= '0'; + nl0111l1O <= '0'; + nl0111lii <= '0'; + nl0111lil <= '0'; + nl0111liO <= '0'; + nl0111lli <= '0'; + nl0111lll <= '0'; + nl0111llO <= '0'; + nl0111lOi <= '0'; + nl0111lOl <= '0'; + nl0111lOO <= '0'; + nl0111O0i <= '0'; + nl0111O0l <= '0'; + nl0111O0O <= '0'; + nl0111O1i <= '0'; + nl0111O1l <= '0'; + nl0111O1O <= '0'; + nl0111Oii <= '0'; + nl0111Oil <= '0'; + nl0111OiO <= '0'; + nl0111Oli <= '0'; + nl0111Oll <= '0'; + nl0111OlO <= '0'; + nl011ilOl <= '0'; + nl011l0iO <= '0'; + nl011l0li <= '0'; + nl011l0ll <= '0'; + nl011l0lO <= '0'; + nl011l0Oi <= '0'; + nl011l0Ol <= '0'; + nl011l0OO <= '0'; + nl011l1ii <= '0'; + nl011l1il <= '0'; + nl011li0i <= '0'; + nl011li0l <= '0'; + nl011li0O <= '0'; + nl011li1i <= '0'; + nl011li1l <= '0'; + nl011li1O <= '0'; + nl011liii <= '0'; + nl011liil <= '0'; + nl011liiO <= '0'; + nl011lili <= '0'; + nl011lill <= '0'; + nl011lilO <= '0'; + nl011liOi <= '0'; + nl011liOl <= '0'; + nl011liOO <= '0'; + nl011ll0i <= '0'; + nl011ll1i <= '0'; + nl011ll1l <= '0'; + nl011ll1O <= '0'; + nl011OO1l <= '0'; + nl011OO1O <= '0'; + nl011OOlO <= '0'; + nl01i0O0O <= '0'; + nl01i0O1i <= '0'; + nl01i0Oii <= '0'; + nl01i0Oil <= '0'; + nl01i0OiO <= '0'; + nl01i0Oli <= '0'; + nl01i0Oll <= '0'; + nl01i0OlO <= '0'; + nl01i0OOi <= '0'; + nl01i0OOl <= '0'; + nl01i0OOO <= '0'; + nl01ii10i <= '0'; + nl01ii10l <= '0'; + nl01ii10O <= '0'; + nl01ii11i <= '0'; + nl01ii11l <= '0'; + nl01ii11O <= '0'; + nl01ii1ii <= '0'; + nl01ii1il <= '0'; + nl01ii1iO <= '0'; + nl01ii1li <= '0'; + nl01ii1ll <= '0'; + nl01ii1lO <= '0'; + nl01ii1Oi <= '0'; + nl01ii1Ol <= '0'; + nl01ii1OO <= '0'; + nl01l000i <= '0'; + nl01l000l <= '0'; + nl01l000O <= '0'; + nl01l001i <= '0'; + nl01l001l <= '0'; + nl01l001O <= '0'; + nl01l00ii <= '0'; + nl01l00il <= '0'; + nl01l00iO <= '0'; + nl01l00li <= '0'; + nl01l00ll <= '0'; + nl01l00lO <= '0'; + nl01l00Oi <= '0'; + nl01l00Ol <= '0'; + nl01l00OO <= '0'; + nl01l01ll <= '0'; + nl01l01lO <= '0'; + nl01l01Oi <= '0'; + nl01l01Ol <= '0'; + nl01l01OO <= '0'; + nl01l0i0i <= '0'; + nl01l0i0l <= '0'; + nl01l0i0O <= '0'; + nl01l0i1i <= '0'; + nl01l0i1l <= '0'; + nl01l0i1O <= '0'; + nl01l0iii <= '0'; + nl01l0iil <= '0'; + nl01l0iiO <= '0'; + nl01l0ili <= '0'; + nl01l0ill <= '0'; + nl01l0ilO <= '0'; + nl01l0iOi <= '0'; + nl01l0iOl <= '0'; + nl01l0iOO <= '0'; + nl01l0l0i <= '0'; + nl01l0l0l <= '0'; + nl01l0l0O <= '0'; + nl01l0l1i <= '0'; + nl01l0l1l <= '0'; + nl01l0l1O <= '0'; + nl01l0lii <= '0'; + nl01l0lil <= '0'; + nl01l0liO <= '0'; + nl01l0lli <= '0'; + nl01l0lll <= '0'; + nl01l0llO <= '0'; + nl01l0lOi <= '0'; + nl01l0lOl <= '0'; + nl01l0lOO <= '0'; + nl01l0O0i <= '0'; + nl01l0O1i <= '0'; + nl01l0O1l <= '0'; + nl01l0O1O <= '0'; + nl01lll0i <= '0'; + nl01lll0l <= '0'; + nl01lll0O <= '0'; + nl01lll1i <= '0'; + nl01lll1l <= '0'; + nl01lll1O <= '0'; + nl01lllii <= '0'; + nl01lllil <= '0'; + nl01llliO <= '0'; + nl01lllli <= '0'; + nl01lllll <= '0'; + nl01llllO <= '0'; + nl01lllOi <= '0'; + nl01lllOl <= '0'; + nl01lllOO <= '0'; + nl01lO0iO <= '0'; + nl01lO0li <= '0'; + nl01lO0ll <= '0'; + nl01lO0lO <= '0'; + nl01lO0Oi <= '0'; + nl01lO0Ol <= '0'; + nl01lO0OO <= '0'; + nl01lOi0i <= '0'; + nl01lOi0l <= '0'; + nl01lOi0O <= '0'; + nl01lOi1i <= '0'; + nl01lOi1l <= '0'; + nl01lOi1O <= '0'; + nl01lOiii <= '0'; + nl01lOiil <= '0'; + nl01lOiiO <= '0'; + nl01lOili <= '0'; + nl01lOill <= '0'; + nl01lOilO <= '0'; + nl01lOiOi <= '0'; + nl01lOiOl <= '0'; + nl01lOiOO <= '0'; + nl01lOl0i <= '0'; + nl01lOl0l <= '0'; + nl01lOl0O <= '0'; + nl01lOl1i <= '0'; + nl01lOl1l <= '0'; + nl01lOl1O <= '0'; + nl01lOlii <= '0'; + nl01lOlil <= '0'; + nl01lOliO <= '0'; + nl01lOlli <= '0'; + nl01lOlll <= '0'; + nl01lOllO <= '0'; + nl01lOlOi <= '0'; + nl01lOlOl <= '0'; + nl01lOlOO <= '0'; + nl01lOO0i <= '0'; + nl01lOO0l <= '0'; + nl01lOO0O <= '0'; + nl01lOO1i <= '0'; + nl01lOO1l <= '0'; + nl01lOO1O <= '0'; + nl01lOOii <= '0'; + nl01lOOil <= '0'; + nl01lOOiO <= '0'; + nl01lOOli <= '0'; + nl01lOOll <= '0'; + nl01lOOlO <= '0'; + nl01lOOOi <= '0'; + nl01lOOOl <= '0'; + nl01lOOOO <= '0'; + nl01O011i <= '0'; + nl01O011l <= '0'; + nl01O100i <= '0'; + nl01O100l <= '0'; + nl01O100O <= '0'; + nl01O101i <= '0'; + nl01O101l <= '0'; + nl01O101O <= '0'; + nl01O10ii <= '0'; + nl01O10il <= '0'; + nl01O10iO <= '0'; + nl01O10li <= '0'; + nl01O10ll <= '0'; + nl01O10lO <= '0'; + nl01O10Oi <= '0'; + nl01O10Ol <= '0'; + nl01O10OO <= '0'; + nl01O110i <= '0'; + nl01O110l <= '0'; + nl01O110O <= '0'; + nl01O111i <= '0'; + nl01O111l <= '0'; + nl01O111O <= '0'; + nl01O11ii <= '0'; + nl01O11il <= '0'; + nl01O11iO <= '0'; + nl01O11li <= '0'; + nl01O11ll <= '0'; + nl01O11lO <= '0'; + nl01O11Oi <= '0'; + nl01O11Ol <= '0'; + nl01O11OO <= '0'; + nl01O1i0i <= '0'; + nl01O1i0l <= '0'; + nl01O1i0O <= '0'; + nl01O1i1i <= '0'; + nl01O1i1l <= '0'; + nl01O1i1O <= '0'; + nl01O1iii <= '0'; + nl01O1iil <= '0'; + nl01O1iiO <= '0'; + nl01O1ili <= '0'; + nl01O1ill <= '0'; + nl01O1ilO <= '0'; + nl01O1iOi <= '0'; + nl01O1iOl <= '0'; + nl01O1iOO <= '0'; + nl01O1l0i <= '0'; + nl01O1l0l <= '0'; + nl01O1l0O <= '0'; + nl01O1l1i <= '0'; + nl01O1l1l <= '0'; + nl01O1l1O <= '0'; + nl01O1lii <= '0'; + nl01O1lil <= '0'; + nl01O1liO <= '0'; + nl01O1lli <= '0'; + nl01O1lll <= '0'; + nl01O1llO <= '0'; + nl01O1lOi <= '0'; + nl01O1lOl <= '0'; + nl01O1lOO <= '0'; + nl01O1O0i <= '0'; + nl01O1O0l <= '0'; + nl01O1O0O <= '0'; + nl01O1O1i <= '0'; + nl01O1O1l <= '0'; + nl01O1O1O <= '0'; + nl01O1Oii <= '0'; + nl01O1Oil <= '0'; + nl01O1OiO <= '0'; + nl01O1Oli <= '0'; + nl01O1Oll <= '0'; + nl01O1OlO <= '0'; + nl01O1OOi <= '0'; + nl01O1OOl <= '0'; + nl01O1OOO <= '0'; + nl0i0000i <= '0'; + nl0i0000l <= '0'; + nl0i0000O <= '0'; + nl0i0001i <= '0'; + nl0i0001l <= '0'; + nl0i0001O <= '0'; + nl0i000ii <= '0'; + nl0i000il <= '0'; + nl0i000iO <= '0'; + nl0i000li <= '0'; + nl0i000ll <= '0'; + nl0i000lO <= '0'; + nl0i000Oi <= '0'; + nl0i000Ol <= '0'; + nl0i000OO <= '0'; + nl0i0010i <= '0'; + nl0i0010l <= '0'; + nl0i0010O <= '0'; + nl0i0011i <= '0'; + nl0i0011l <= '0'; + nl0i0011O <= '0'; + nl0i001ii <= '0'; + nl0i001il <= '0'; + nl0i001iO <= '0'; + nl0i001li <= '0'; + nl0i001ll <= '0'; + nl0i001lO <= '0'; + nl0i001Oi <= '0'; + nl0i001Ol <= '0'; + nl0i001OO <= '0'; + nl0i00i0i <= '0'; + nl0i00i0l <= '0'; + nl0i00i0O <= '0'; + nl0i00i1i <= '0'; + nl0i00i1l <= '0'; + nl0i00i1O <= '0'; + nl0i00iii <= '0'; + nl0i00iil <= '0'; + nl0i00iiO <= '0'; + nl0i0100i <= '0'; + nl0i0100l <= '0'; + nl0i0100O <= '0'; + nl0i0101i <= '0'; + nl0i0101l <= '0'; + nl0i0101O <= '0'; + nl0i010ii <= '0'; + nl0i010il <= '0'; + nl0i010iO <= '0'; + nl0i010li <= '0'; + nl0i010ll <= '0'; + nl0i010lO <= '0'; + nl0i010Oi <= '0'; + nl0i010Ol <= '0'; + nl0i010OO <= '0'; + nl0i0110i <= '0'; + nl0i0110l <= '0'; + nl0i0110O <= '0'; + nl0i0111i <= '0'; + nl0i0111l <= '0'; + nl0i0111O <= '0'; + nl0i011ii <= '0'; + nl0i011il <= '0'; + nl0i011iO <= '0'; + nl0i011li <= '0'; + nl0i011ll <= '0'; + nl0i011lO <= '0'; + nl0i011Oi <= '0'; + nl0i011Ol <= '0'; + nl0i011OO <= '0'; + nl0i01i0i <= '0'; + nl0i01i0l <= '0'; + nl0i01i0O <= '0'; + nl0i01i1i <= '0'; + nl0i01i1l <= '0'; + nl0i01i1O <= '0'; + nl0i01iii <= '0'; + nl0i01iil <= '0'; + nl0i01iiO <= '0'; + nl0i01ili <= '0'; + nl0i01ill <= '0'; + nl0i01ilO <= '0'; + nl0i01iOi <= '0'; + nl0i01iOl <= '0'; + nl0i01iOO <= '0'; + nl0i01l0i <= '0'; + nl0i01l0l <= '0'; + nl0i01l0O <= '0'; + nl0i01l1i <= '0'; + nl0i01l1l <= '0'; + nl0i01l1O <= '0'; + nl0i01lii <= '0'; + nl0i01lil <= '0'; + nl0i01liO <= '0'; + nl0i01lli <= '0'; + nl0i01lll <= '0'; + nl0i01llO <= '0'; + nl0i01lOi <= '0'; + nl0i01lOl <= '0'; + nl0i01lOO <= '0'; + nl0i01O0i <= '0'; + nl0i01O0l <= '0'; + nl0i01O0O <= '0'; + nl0i01O1i <= '0'; + nl0i01O1l <= '0'; + nl0i01O1O <= '0'; + nl0i01Oii <= '0'; + nl0i01Oil <= '0'; + nl0i01OiO <= '0'; + nl0i01Oli <= '0'; + nl0i01Oll <= '0'; + nl0i01OlO <= '0'; + nl0i01OOi <= '0'; + nl0i01OOl <= '0'; + nl0i01OOO <= '0'; + nl0i1li0i <= '0'; + nl0i1li0l <= '0'; + nl0i1li0O <= '0'; + nl0i1li1O <= '0'; + nl0i1liii <= '0'; + nl0i1liil <= '0'; + nl0i1liiO <= '0'; + nl0i1lOOi <= '0'; + nl0i1lOOl <= '0'; + nl0i1lOOO <= '0'; + nl0i1O11i <= '0'; + nl0i1O1ii <= '0'; + nl0i1O1il <= '0'; + nl0i1O1iO <= '0'; + nl0i1O1li <= '0'; + nl0i1OiOi <= '0'; + nl0i1OiOl <= '0'; + nl0i1OiOO <= '0'; + nl0i1Ol0i <= '0'; + nl0i1Ol0l <= '0'; + nl0i1Ol0O <= '0'; + nl0i1Ol1i <= '0'; + nl0i1Ol1l <= '0'; + nl0i1Ol1O <= '0'; + nl0i1Olii <= '0'; + nl0i1Olil <= '0'; + nl0i1OliO <= '0'; + nl0i1Olli <= '0'; + nl0i1Olll <= '0'; + nl0i1OllO <= '0'; + nl0i1OlOi <= '0'; + nl0i1OlOl <= '0'; + nl0i1OlOO <= '0'; + nl0i1OO0i <= '0'; + nl0i1OO0l <= '0'; + nl0i1OO0O <= '0'; + nl0i1OO1i <= '0'; + nl0i1OO1l <= '0'; + nl0i1OO1O <= '0'; + nl0i1OOii <= '0'; + nl0i1OOil <= '0'; + nl0i1OOiO <= '0'; + nl0i1OOli <= '0'; + nl0i1OOll <= '0'; + nl0i1OOlO <= '0'; + nl0i1OOOi <= '0'; + nl0i1OOOl <= '0'; + nl0i1OOOO <= '0'; + nl0ili1ll <= '0'; + nl0illl0i <= '0'; + nl0illl0l <= '0'; + nl0illl0O <= '0'; + nl0illlii <= '0'; + nl0illlil <= '0'; + nl0illliO <= '0'; + nl0illlli <= '0'; + nl0illlll <= '0'; + nl0illllO <= '0'; + nl0ilOiOi <= '0'; + nl0ilOiOl <= '0'; + nl0ilOiOO <= '0'; + nl0ilOl0i <= '0'; + nl0ilOl0l <= '0'; + nl0ilOl0O <= '0'; + nl0ilOl1i <= '0'; + nl0ilOl1l <= '0'; + nl0ilOl1O <= '0'; + nl0ilOlii <= '0'; + nl0ilOlil <= '0'; + nl0ilOliO <= '0'; + nl0ilOlli <= '0'; + nl0ilOlll <= '0'; + nl0iOi10i <= '0'; + nl0iOiili <= '0'; + nl0iOiill <= '0'; + nl0iOiilO <= '0'; + nl0iOiiOi <= '0'; + nl0iOiiOl <= '0'; + nl0iOiiOO <= '0'; + nl0iOil0i <= '0'; + nl0iOil0l <= '0'; + nl0iOil0O <= '0'; + nl0iOil1i <= '0'; + nl0iOil1l <= '0'; + nl0iOil1O <= '0'; + nl0iOilii <= '0'; + nl0iOilil <= '0'; + nl0iOiliO <= '0'; + nl0iOilli <= '0'; + nl0iOilll <= '0'; + nl0iOillO <= '0'; + nl0iOilOi <= '0'; + nl0iOilOl <= '0'; + nl0iOilOO <= '0'; + nl0iOiO0i <= '0'; + nl0iOiO0l <= '0'; + nl0iOiO0O <= '0'; + nl0iOiO1i <= '0'; + nl0iOiO1l <= '0'; + nl0iOiO1O <= '0'; + nl0iOiOii <= '0'; + nl0iOiOil <= '0'; + nl0iOiOiO <= '0'; + nl0iOiOli <= '0'; + nl0iOiOll <= '0'; + nl0iOiOlO <= '0'; + nl0iOiOOi <= '0'; + nl0iOiOOl <= '0'; + nl0iOiOOO <= '0'; + nl0iOl10i <= '0'; + nl0iOl11i <= '0'; + nl0iOl11l <= '0'; + nl0iOl11O <= '0'; + nl0iOOO0i <= '0'; + nl0iOOO0l <= '0'; + nl0iOOO0O <= '0'; + nl0iOOO1l <= '0'; + nl0iOOO1O <= '0'; + nl0iOOOii <= '0'; + nl0iOOOil <= '0'; + nl0iOOOiO <= '0'; + nl0iOOOli <= '0'; + nl0iOOOll <= '0'; + nl0iOOOlO <= '0'; + nl0iOOOOi <= '0'; + nl0iOOOOl <= '0'; + nl0iOOOOO <= '0'; + nl0l000ll <= '0'; + nl0l001iO <= '0'; + nl0l001li <= '0'; + nl0l001ll <= '0'; + nl0l001lO <= '0'; + nl0l001Oi <= '0'; + nl0l001Ol <= '0'; + nl0l00iOl <= '0'; + nl0l00iOO <= '0'; + nl0l00l1i <= '0'; + nl0l00l1l <= '0'; + nl0l00l1O <= '0'; + nl0l0100i <= '0'; + nl0l0100l <= '0'; + nl0l0100O <= '0'; + nl0l0101l <= '0'; + nl0l0101O <= '0'; + nl0l010ii <= '0'; + nl0l010il <= '0'; + nl0l010iO <= '0'; + nl0l010li <= '0'; + nl0l010ll <= '0'; + nl0l010lO <= '0'; + nl0l010Oi <= '0'; + nl0l010Ol <= '0'; + nl0l010OO <= '0'; + nl0l01O1l <= '0'; + nl0l01O1O <= '0'; + nl0l0i00i <= '0'; + nl0l0i00l <= '0'; + nl0l0i00O <= '0'; + nl0l0i01i <= '0'; + nl0l0i01l <= '0'; + nl0l0i01O <= '0'; + nl0l0i0ii <= '0'; + nl0l0i0il <= '0'; + nl0l0i0iO <= '0'; + nl0l0i0li <= '0'; + nl0l0i0ll <= '0'; + nl0l0i1ii <= '0'; + nl0l0i1Oi <= '0'; + nl0l0i1Ol <= '0'; + nl0l0i1OO <= '0'; + nl0l0liiO <= '0'; + nl0l0lili <= '0'; + nl0l0lill <= '0'; + nl0l0lilO <= '0'; + nl0l0liOi <= '0'; + nl0l0liOl <= '0'; + nl0l0liOO <= '0'; + nl0l0ll0i <= '0'; + nl0l0ll0l <= '0'; + nl0l0ll0O <= '0'; + nl0l0ll1i <= '0'; + nl0l0ll1l <= '0'; + nl0l0ll1O <= '0'; + nl0l0llii <= '0'; + nl0l0llil <= '0'; + nl0l0lliO <= '0'; + nl0l0llli <= '0'; + nl0l0llll <= '0'; + nl0l0lllO <= '0'; + nl0l0llOi <= '0'; + nl0l0llOl <= '0'; + nl0l0llOO <= '0'; + nl0l0lO0i <= '0'; + nl0l0lO0l <= '0'; + nl0l0lO0O <= '0'; + nl0l0lO1i <= '0'; + nl0l0lO1l <= '0'; + nl0l0lO1O <= '0'; + nl0l0lOii <= '0'; + nl0l0lOil <= '0'; + nl0l0lOiO <= '0'; + nl0l0lOli <= '0'; + nl0l0lOll <= '0'; + nl0l0lOlO <= '0'; + nl0l0lOOi <= '0'; + nl0l0lOOl <= '0'; + nl0l0lOOO <= '0'; + nl0l0O00i <= '0'; + nl0l0O00l <= '0'; + nl0l0O00O <= '0'; + nl0l0O01i <= '0'; + nl0l0O01l <= '0'; + nl0l0O01O <= '0'; + nl0l0O0ii <= '0'; + nl0l0O0il <= '0'; + nl0l0O0iO <= '0'; + nl0l0O0li <= '0'; + nl0l0O0ll <= '0'; + nl0l0O0lO <= '0'; + nl0l0O0Oi <= '0'; + nl0l0O0Ol <= '0'; + nl0l0O0OO <= '0'; + nl0l0O10i <= '0'; + nl0l0O10l <= '0'; + nl0l0O10O <= '0'; + nl0l0O11i <= '0'; + nl0l0O11l <= '0'; + nl0l0O11O <= '0'; + nl0l0O1ii <= '0'; + nl0l0O1il <= '0'; + nl0l0O1iO <= '0'; + nl0l0O1li <= '0'; + nl0l0O1ll <= '0'; + nl0l0O1lO <= '0'; + nl0l0O1Oi <= '0'; + nl0l0O1Ol <= '0'; + nl0l0O1OO <= '0'; + nl0l0Oi0i <= '0'; + nl0l0Oi0l <= '0'; + nl0l0Oi0O <= '0'; + nl0l0Oi1i <= '0'; + nl0l0Oi1l <= '0'; + nl0l0Oi1O <= '0'; + nl0l0Oiii <= '0'; + nl0l0Oiil <= '0'; + nl0l0OiiO <= '0'; + nl0l0Oili <= '0'; + nl0l0Oill <= '0'; + nl0l0OilO <= '0'; + nl0l0OiOi <= '0'; + nl0l0OiOl <= '0'; + nl0l0OiOO <= '0'; + nl0l1010i <= '0'; + nl0l1010l <= '0'; + nl0l1010O <= '0'; + nl0l1011i <= '0'; + nl0l1011l <= '0'; + nl0l1011O <= '0'; + nl0l101ii <= '0'; + nl0l101il <= '0'; + nl0l1100i <= '0'; + nl0l1100l <= '0'; + nl0l1100O <= '0'; + nl0l1101i <= '0'; + nl0l1101l <= '0'; + nl0l1101O <= '0'; + nl0l110ii <= '0'; + nl0l110il <= '0'; + nl0l110iO <= '0'; + nl0l110li <= '0'; + nl0l110ll <= '0'; + nl0l110lO <= '0'; + nl0l110Oi <= '0'; + nl0l110Ol <= '0'; + nl0l110OO <= '0'; + nl0l1110i <= '0'; + nl0l1110l <= '0'; + nl0l1110O <= '0'; + nl0l1111i <= '0'; + nl0l1111l <= '0'; + nl0l1111O <= '0'; + nl0l111ii <= '0'; + nl0l111il <= '0'; + nl0l111iO <= '0'; + nl0l111li <= '0'; + nl0l111ll <= '0'; + nl0l111lO <= '0'; + nl0l111Oi <= '0'; + nl0l111Ol <= '0'; + nl0l111OO <= '0'; + nl0l11i0i <= '0'; + nl0l11i0l <= '0'; + nl0l11i0O <= '0'; + nl0l11i1i <= '0'; + nl0l11i1l <= '0'; + nl0l11i1O <= '0'; + nl0l11iii <= '0'; + nl0l11iil <= '0'; + nl0l11iiO <= '0'; + nl0l11ili <= '0'; + nl0l11ill <= '0'; + nl0l11ilO <= '0'; + nl0l11iOi <= '0'; + nl0l11iOl <= '0'; + nl0l11iOO <= '0'; + nl0l11l0i <= '0'; + nl0l11l0l <= '0'; + nl0l11l0O <= '0'; + nl0l11l1i <= '0'; + nl0l11l1l <= '0'; + nl0l11l1O <= '0'; + nl0l11lii <= '0'; + nl0l11lil <= '0'; + nl0l11liO <= '0'; + nl0l11lli <= '0'; + nl0l11lll <= '0'; + nl0l11llO <= '0'; + nl0l11lOi <= '0'; + nl0l11lOl <= '0'; + nl0l11lOO <= '0'; + nl0l11O0i <= '0'; + nl0l11O0l <= '0'; + nl0l11O0O <= '0'; + nl0l11O1i <= '0'; + nl0l11O1l <= '0'; + nl0l11O1O <= '0'; + nl0l11Oii <= '0'; + nl0l11Oil <= '0'; + nl0l11OiO <= '0'; + nl0l11Oli <= '0'; + nl0l11Oll <= '0'; + nl0l11OlO <= '0'; + nl0l11OOi <= '0'; + nl0l11OOl <= '0'; + nl0l11OOO <= '0'; + nl0lil00i <= '0'; + nl0lil00l <= '0'; + nl0lil00O <= '0'; + nl0lil0ii <= '0'; + nl0lil0il <= '0'; + nl0lil0iO <= '0'; + nl0lil0li <= '0'; + nl0lil0ll <= '0'; + nl0lil11i <= '0'; + nl0lil11l <= '0'; + nl0liliOO <= '0'; + nl0lill0i <= '0'; + nl0lill0l <= '0'; + nl0lill0O <= '0'; + nl0lill1i <= '0'; + nl0lill1l <= '0'; + nl0lill1O <= '0'; + nl0ll1O1l <= '0'; + nl0lliiiO <= '0'; + nl0llli0i <= '0'; + nl0llli0l <= '0'; + nl0llli0O <= '0'; + nl0llli1i <= '0'; + nl0llli1l <= '0'; + nl0llli1O <= '0'; + nl0llliii <= '0'; + nl0llliil <= '0'; + nl0llliiO <= '0'; + nl0lllili <= '0'; + nl0lllill <= '0'; + nl0lllilO <= '0'; + nl0llliOi <= '0'; + nl0llliOl <= '0'; + nl0llliOO <= '0'; + nl0llll0i <= '0'; + nl0llll0l <= '0'; + nl0llll0O <= '0'; + nl0llll1i <= '0'; + nl0llll1l <= '0'; + nl0llll1O <= '0'; + nl0llllii <= '0'; + nl0llllil <= '0'; + nl0lllliO <= '0'; + nl0llllli <= '0'; + nl0llllll <= '0'; + nl0lllllO <= '0'; + nl0llllOi <= '0'; + nl0llllOl <= '0'; + nl0llllOO <= '0'; + nl0lllO0i <= '0'; + nl0lllO0l <= '0'; + nl0lllO0O <= '0'; + nl0lllO1i <= '0'; + nl0lllO1l <= '0'; + nl0lllO1O <= '0'; + nl0lllOii <= '0'; + nl0lllOil <= '0'; + nl0lllOiO <= '0'; + nl0lllOli <= '0'; + nl0lllOll <= '0'; + nl0lllOlO <= '0'; + nl0lllOOi <= '0'; + nl0lllOOl <= '0'; + nl0lllOOO <= '0'; + nl0llO10i <= '0'; + nl0llO10l <= '0'; + nl0llO10O <= '0'; + nl0llO11i <= '0'; + nl0llO11l <= '0'; + nl0llO11O <= '0'; + nl0llO1ii <= '0'; + nl0llO1il <= '0'; + nl0llO1iO <= '0'; + nl0llO1li <= '0'; + nl0llO1ll <= '0'; + nl0llO1lO <= '0'; + nl0llO1Oi <= '0'; + nl0llO1Ol <= '0'; + nl0lOlill <= '0'; + nl0O0i10O <= '0'; + nl0O0llOi <= '0'; + nl0O10Oll <= '0'; + nl0O10OlO <= '0'; + nl0O10OOi <= '0'; + nl0O10OOl <= '0'; + nl0O10OOO <= '0'; + nl0O1101O <= '0'; + nl0O1i00i <= '0'; + nl0O1i00l <= '0'; + nl0O1i00O <= '0'; + nl0O1i01i <= '0'; + nl0O1i01l <= '0'; + nl0O1i01O <= '0'; + nl0O1i0ii <= '0'; + nl0O1i0il <= '0'; + nl0O1i0iO <= '0'; + nl0O1i0li <= '0'; + nl0O1i0ll <= '0'; + nl0O1i0lO <= '0'; + nl0O1i0Oi <= '0'; + nl0O1i0Ol <= '0'; + nl0O1i0OO <= '0'; + nl0O1i10i <= '0'; + nl0O1i10l <= '0'; + nl0O1i10O <= '0'; + nl0O1i11i <= '0'; + nl0O1i11l <= '0'; + nl0O1i11O <= '0'; + nl0O1i1ii <= '0'; + nl0O1i1il <= '0'; + nl0O1i1iO <= '0'; + nl0O1i1li <= '0'; + nl0O1i1ll <= '0'; + nl0O1i1lO <= '0'; + nl0O1i1Oi <= '0'; + nl0O1i1Ol <= '0'; + nl0O1i1OO <= '0'; + nl0O1ii0i <= '0'; + nl0O1ii0l <= '0'; + nl0O1ii0O <= '0'; + nl0O1ii1i <= '0'; + nl0O1ii1l <= '0'; + nl0O1ii1O <= '0'; + nl0O1iiii <= '0'; + nl0O1iiil <= '0'; + nl0O1iiiO <= '0'; + nl0O1iili <= '0'; + nl0O1iill <= '0'; + nl0O1iilO <= '0'; + nl0O1iiOi <= '0'; + nl0O1iiOl <= '0'; + nl0O1iiOO <= '0'; + nl0O1il0i <= '0'; + nl0O1il0l <= '0'; + nl0O1il0O <= '0'; + nl0O1il1i <= '0'; + nl0O1il1l <= '0'; + nl0O1il1O <= '0'; + nl0O1ilii <= '0'; + nl0O1ilil <= '0'; + nl0O1iliO <= '0'; + nl0Oi000i <= '0'; + nl0Oi001i <= '0'; + nl0Oi001l <= '0'; + nl0Oi001O <= '0'; + nl0Oi010i <= '0'; + nl0Oi010l <= '0'; + nl0Oi010O <= '0'; + nl0Oi011i <= '0'; + nl0Oi011l <= '0'; + nl0Oi011O <= '0'; + nl0Oi01ii <= '0'; + nl0Oi01il <= '0'; + nl0Oi01iO <= '0'; + nl0Oi01li <= '0'; + nl0Oi01ll <= '0'; + nl0Oi01lO <= '0'; + nl0Oi01Oi <= '0'; + nl0Oi01Ol <= '0'; + nl0Oi01OO <= '0'; + nl0Oi1i0O <= '0'; + nl0Oi1iii <= '0'; + nl0Oi1iil <= '0'; + nl0Oi1iiO <= '0'; + nl0Oi1ili <= '0'; + nl0Oi1ill <= '0'; + nl0Oi1ilO <= '0'; + nl0Oi1iOi <= '0'; + nl0Oi1iOl <= '0'; + nl0Oi1iOO <= '0'; + nl0Oi1l0i <= '0'; + nl0Oi1l0l <= '0'; + nl0Oi1l0O <= '0'; + nl0Oi1l1i <= '0'; + nl0Oi1l1l <= '0'; + nl0Oi1l1O <= '0'; + nl0Oi1lii <= '0'; + nl0Oi1lil <= '0'; + nl0Oi1liO <= '0'; + nl0Oi1lli <= '0'; + nl0Oi1lll <= '0'; + nl0Oi1llO <= '0'; + nl0Oi1lOi <= '0'; + nl0Oi1lOl <= '0'; + nl0Oi1lOO <= '0'; + nl0Oi1O0i <= '0'; + nl0Oi1O0l <= '0'; + nl0Oi1O0O <= '0'; + nl0Oi1O1i <= '0'; + nl0Oi1O1l <= '0'; + nl0Oi1O1O <= '0'; + nl0Oi1Oii <= '0'; + nl0Oi1Oil <= '0'; + nl0Oi1OiO <= '0'; + nl0Oi1Oli <= '0'; + nl0Oi1Oll <= '0'; + nl0Oi1OlO <= '0'; + nl0Oi1OOi <= '0'; + nl0Oi1OOl <= '0'; + nl0Oi1OOO <= '0'; + nl0OiO0li <= '0'; + nl0OiO1il <= '0'; + nl0OiO1iO <= '0'; + nl0OiO1li <= '0'; + nl0OiO1ll <= '0'; + nl0OiO1lO <= '0'; + nl0OiO1Oi <= '0'; + nl0OiOl0i <= '0'; + nl0OiOl0l <= '0'; + nl0OiOl0O <= '0'; + nl0OiOlii <= '0'; + nl0OiOlil <= '0'; + nl0Ol000i <= '0'; + nl0Ol000l <= '0'; + nl0Ol000O <= '0'; + nl0Ol001i <= '0'; + nl0Ol001l <= '0'; + nl0Ol001O <= '0'; + nl0Ol00ii <= '0'; + nl0Ol00il <= '0'; + nl0Ol00iO <= '0'; + nl0Ol00li <= '0'; + nl0Ol00ll <= '0'; + nl0Ol00lO <= '0'; + nl0Ol00Oi <= '0'; + nl0Ol00Ol <= '0'; + nl0Ol00OO <= '0'; + nl0Ol010i <= '0'; + nl0Ol010l <= '0'; + nl0Ol010O <= '0'; + nl0Ol011i <= '0'; + nl0Ol011l <= '0'; + nl0Ol011O <= '0'; + nl0Ol01ii <= '0'; + nl0Ol01il <= '0'; + nl0Ol01iO <= '0'; + nl0Ol01li <= '0'; + nl0Ol01ll <= '0'; + nl0Ol01lO <= '0'; + nl0Ol01Oi <= '0'; + nl0Ol01Ol <= '0'; + nl0Ol01OO <= '0'; + nl0Ol0i0i <= '0'; + nl0Ol0i0l <= '0'; + nl0Ol0i0O <= '0'; + nl0Ol0i1i <= '0'; + nl0Ol0i1l <= '0'; + nl0Ol0i1O <= '0'; + nl0Ol0iii <= '0'; + nl0Ol0iil <= '0'; + nl0Ol0iiO <= '0'; + nl0Ol0ili <= '0'; + nl0Ol0ill <= '0'; + nl0Ol0ilO <= '0'; + nl0Ol0iOi <= '0'; + nl0Ol0iOl <= '0'; + nl0Ol0iOO <= '0'; + nl0Ol0l0i <= '0'; + nl0Ol0l0l <= '0'; + nl0Ol0l0O <= '0'; + nl0Ol0l1i <= '0'; + nl0Ol0l1l <= '0'; + nl0Ol0l1O <= '0'; + nl0Ol0lii <= '0'; + nl0Ol0lil <= '0'; + nl0Ol0liO <= '0'; + nl0Ol0lli <= '0'; + nl0Ol0lll <= '0'; + nl0Ol0llO <= '0'; + nl0Ol0lOi <= '0'; + nl0Ol0lOl <= '0'; + nl0Ol0lOO <= '0'; + nl0Ol0O0i <= '0'; + nl0Ol0O0l <= '0'; + nl0Ol0O0O <= '0'; + nl0Ol0O1i <= '0'; + nl0Ol0O1l <= '0'; + nl0Ol0O1O <= '0'; + nl0Ol0Oii <= '0'; + nl0Ol0Oil <= '0'; + nl0Ol0OiO <= '0'; + nl0Ol0Oli <= '0'; + nl0Ol0Oll <= '0'; + nl0Ol1llO <= '0'; + nl0Ol1lOi <= '0'; + nl0Ol1lOl <= '0'; + nl0Ol1lOO <= '0'; + nl0Ol1O0i <= '0'; + nl0Ol1O0l <= '0'; + nl0Ol1O0O <= '0'; + nl0Ol1O1i <= '0'; + nl0Ol1O1l <= '0'; + nl0Ol1O1O <= '0'; + nl0Ol1Oii <= '0'; + nl0Ol1Oil <= '0'; + nl0Ol1OiO <= '0'; + nl0Ol1Oli <= '0'; + nl0Ol1Oll <= '0'; + nl0Ol1OlO <= '0'; + nl0Ol1OOi <= '0'; + nl0Ol1OOl <= '0'; + nl0Ol1OOO <= '0'; + nl0OO0Oii <= '0'; + nl0OO0Oil <= '0'; + nl0OO0OiO <= '0'; + nl0OO0Oli <= '0'; + nl0OO0Oll <= '0'; + nl0OO0OlO <= '0'; + nl0OO0OOi <= '0'; + nl0OO0OOl <= '0'; + nl0OO0OOO <= '0'; + nl0OO1iOO <= '0'; + nl0OO1l0i <= '0'; + nl0OO1l0l <= '0'; + nl0OO1l0O <= '0'; + nl0OO1l1i <= '0'; + nl0OO1l1l <= '0'; + nl0OO1l1O <= '0'; + nl0OO1lii <= '0'; + nl0OO1lil <= '0'; + nl0OO1liO <= '0'; + nl0OO1lli <= '0'; + nl0OO1lll <= '0'; + nl0OO1llO <= '0'; + nl0OO1lOi <= '0'; + nl0OO1lOl <= '0'; + nl0OO1lOO <= '0'; + nl0OO1O0i <= '0'; + nl0OO1O0l <= '0'; + nl0OO1O0O <= '0'; + nl0OO1O1i <= '0'; + nl0OO1O1l <= '0'; + nl0OO1O1O <= '0'; + nl0OO1Oii <= '0'; + nl0OO1Oil <= '0'; + nl0OOi00i <= '0'; + nl0OOi00l <= '0'; + nl0OOi00O <= '0'; + nl0OOi01i <= '0'; + nl0OOi01l <= '0'; + nl0OOi01O <= '0'; + nl0OOi0ii <= '0'; + nl0OOi0il <= '0'; + nl0OOi0iO <= '0'; + nl0OOi0li <= '0'; + nl0OOi0ll <= '0'; + nl0OOi0lO <= '0'; + nl0OOi0Oi <= '0'; + nl0OOi0Ol <= '0'; + nl0OOi0OO <= '0'; + nl0OOi10i <= '0'; + nl0OOi10l <= '0'; + nl0OOi10O <= '0'; + nl0OOi11i <= '0'; + nl0OOi11l <= '0'; + nl0OOi11O <= '0'; + nl0OOi1ii <= '0'; + nl0OOi1il <= '0'; + nl0OOi1iO <= '0'; + nl0OOi1li <= '0'; + nl0OOi1ll <= '0'; + nl0OOi1lO <= '0'; + nl0OOi1Oi <= '0'; + nl0OOi1Ol <= '0'; + nl0OOi1OO <= '0'; + nl0OOii1i <= '0'; + nl0OOO00i <= '0'; + nl0OOO00l <= '0'; + nl0OOO00O <= '0'; + nl0OOO01i <= '0'; + nl0OOO01l <= '0'; + nl0OOO01O <= '0'; + nl0OOO0ii <= '0'; + nl0OOO0il <= '0'; + nl0OOO0iO <= '0'; + nl0OOO10i <= '0'; + nl0OOO10l <= '0'; + nl0OOO10O <= '0'; + nl0OOO11l <= '0'; + nl0OOO11O <= '0'; + nl0OOO1ii <= '0'; + nl0OOO1il <= '0'; + nl0OOO1iO <= '0'; + nl0OOO1li <= '0'; + nl0OOO1ll <= '0'; + nl0OOO1lO <= '0'; + nl0OOO1Oi <= '0'; + nl0OOO1Ol <= '0'; + nl0OOO1OO <= '0'; + nl10ii0li <= '0'; + nl10ii0ll <= '0'; + nl10ilO0O <= '0'; + nl10ilOii <= '0'; + nl10ilOil <= '0'; + nl10ilOiO <= '0'; + nl10ilOli <= '0'; + nl10ilOll <= '0'; + nl10ilOlO <= '0'; + nl10ilOOi <= '0'; + nl10ilOOl <= '0'; + nl10iO1li <= '0'; + nl10iOO0i <= '0'; + nl10iOO0l <= '0'; + nl10iOO0O <= '0'; + nl10iOO1O <= '0'; + nl10iOOii <= '0'; + nl10iOOil <= '0'; + nl10iOOiO <= '0'; + nl10iOOli <= '0'; + nl10iOOll <= '0'; + nl10liO1l <= '0'; + nl10lli0O <= '0'; + nl10lliil <= '0'; + nl10lliiO <= '0'; + nl10llili <= '0'; + nl10llill <= '0'; + nl10llilO <= '0'; + nl10lliOi <= '0'; + nl10lliOO <= '0'; + nl10lll0i <= '0'; + nl10lll1i <= '0'; + nl10lll1l <= '0'; + nl10lll1O <= '0'; + nl10O000i <= '0'; + nl10O000l <= '0'; + nl10O000O <= '0'; + nl10O001i <= '0'; + nl10O001l <= '0'; + nl10O001O <= '0'; + nl10O00ii <= '0'; + nl10O00il <= '0'; + nl10O00iO <= '0'; + nl10O00li <= '0'; + nl10O00ll <= '0'; + nl10O00lO <= '0'; + nl10O00Oi <= '0'; + nl10O00Ol <= '0'; + nl10O00OO <= '0'; + nl10O01Ol <= '0'; + nl10O01OO <= '0'; + nl10O0i0i <= '0'; + nl10O0i0l <= '0'; + nl10O0i0O <= '0'; + nl10O0i1i <= '0'; + nl10O0i1l <= '0'; + nl10O0i1O <= '0'; + nl10O0iii <= '0'; + nl10O0iil <= '0'; + nl10O0iiO <= '0'; + nl10O0ili <= '0'; + nl10O0ill <= '0'; + nl10O0ilO <= '0'; + nl10O0iOi <= '0'; + nl10O0iOl <= '0'; + nl10O0iOO <= '0'; + nl10O0l0i <= '0'; + nl10O0l0l <= '0'; + nl10O0l0O <= '0'; + nl10O0l1i <= '0'; + nl10O0l1l <= '0'; + nl10O0l1O <= '0'; + nl10O0lii <= '0'; + nl10O0lil <= '0'; + nl10O0liO <= '0'; + nl10O0lli <= '0'; + nl10O0lll <= '0'; + nl10O0llO <= '0'; + nl10O0lOi <= '0'; + nl10O0lOl <= '0'; + nl10O0lOO <= '0'; + nl10O0O0i <= '0'; + nl10O0O0l <= '0'; + nl10O0O0O <= '0'; + nl10O0O1i <= '0'; + nl10O0O1l <= '0'; + nl10O0O1O <= '0'; + nl10O0Oii <= '0'; + nl10O0Oil <= '0'; + nl10O0OiO <= '0'; + nl10O0Oli <= '0'; + nl10O0Oll <= '0'; + nl10O0OlO <= '0'; + nl10O0OOi <= '0'; + nl10O100i <= '0'; + nl10O100l <= '0'; + nl10O101i <= '0'; + nl10O101l <= '0'; + nl10O101O <= '0'; + nl10O110O <= '0'; + nl10O11ii <= '0'; + nl10O11il <= '0'; + nl10O11iO <= '0'; + nl10O11li <= '0'; + nl10O11ll <= '0'; + nl10O11lO <= '0'; + nl10O11Oi <= '0'; + nl10O11Ol <= '0'; + nl10O11OO <= '0'; + nl110100i <= '0'; + nl110100l <= '0'; + nl110100O <= '0'; + nl110101i <= '0'; + nl110101l <= '0'; + nl110101O <= '0'; + nl11010ii <= '0'; + nl11010il <= '0'; + nl11010iO <= '0'; + nl11010li <= '0'; + nl11010ll <= '0'; + nl11010lO <= '0'; + nl11010Oi <= '0'; + nl11010Ol <= '0'; + nl11010OO <= '0'; + nl110110i <= '0'; + nl110110l <= '0'; + nl110110O <= '0'; + nl110111i <= '0'; + nl110111l <= '0'; + nl110111O <= '0'; + nl11011ii <= '0'; + nl11011il <= '0'; + nl11011iO <= '0'; + nl11011li <= '0'; + nl11011ll <= '0'; + nl11011lO <= '0'; + nl11011Oi <= '0'; + nl11011Ol <= '0'; + nl11011OO <= '0'; + nl1101i0i <= '0'; + nl1101i0l <= '0'; + nl1101i0O <= '0'; + nl1101i1i <= '0'; + nl1101i1l <= '0'; + nl1101i1O <= '0'; + nl1101iii <= '0'; + nl1101iil <= '0'; + nl1101iiO <= '0'; + nl1101ili <= '0'; + nl1101ill <= '0'; + nl1101ilO <= '0'; + nl1101iOi <= '0'; + nl1101iOl <= '0'; + nl1101iOO <= '0'; + nl1101l0i <= '0'; + nl1101l0l <= '0'; + nl1101l0O <= '0'; + nl1101l1i <= '0'; + nl1101l1l <= '0'; + nl1101l1O <= '0'; + nl110Oi0i <= '0'; + nl110Oi0l <= '0'; + nl110Oi0O <= '0'; + nl110Oi1l <= '0'; + nl110Oi1O <= '0'; + nl110Oiii <= '0'; + nl110Oiil <= '0'; + nl110OiiO <= '0'; + nl110Oili <= '0'; + nl110Oill <= '0'; + nl110OilO <= '0'; + nl110OiOi <= '0'; + nl110OiOl <= '0'; + nl110OiOO <= '0'; + nl110Ol0i <= '0'; + nl110Ol0l <= '0'; + nl110Ol0O <= '0'; + nl110Ol1i <= '0'; + nl110Ol1l <= '0'; + nl110Ol1O <= '0'; + nl110Olii <= '0'; + nl110Olil <= '0'; + nl110OliO <= '0'; + nl110Olli <= '0'; + nl110Olll <= '0'; + nl110OllO <= '0'; + nl110OlOi <= '0'; + nl110OlOl <= '0'; + nl110OlOO <= '0'; + nl110OO0i <= '0'; + nl110OO0l <= '0'; + nl110OO0O <= '0'; + nl110OO1i <= '0'; + nl110OO1l <= '0'; + nl110OO1O <= '0'; + nl110OOii <= '0'; + nl110OOil <= '0'; + nl110OOiO <= '0'; + nl110OOli <= '0'; + nl110OOll <= '0'; + nl110OOlO <= '0'; + nl110OOOi <= '0'; + nl110OOOl <= '0'; + nl110OOOO <= '0'; + nl11100iO <= '0'; + nl11100li <= '0'; + nl11100ll <= '0'; + nl11100lO <= '0'; + nl11100Oi <= '0'; + nl11100Ol <= '0'; + nl11100OO <= '0'; + nl11101il <= '0'; + nl1110i0i <= '0'; + nl1110i0l <= '0'; + nl1110i0O <= '0'; + nl1110i1i <= '0'; + nl1110i1l <= '0'; + nl1110i1O <= '0'; + nl1110iii <= '0'; + nl1110iil <= '0'; + nl1110iiO <= '0'; + nl1110ili <= '0'; + nl1110ill <= '0'; + nl1110ilO <= '0'; + nl1110iOi <= '0'; + nl1110iOl <= '0'; + nl1110iOO <= '0'; + nl1110l0i <= '0'; + nl1110l0l <= '0'; + nl1110l0O <= '0'; + nl1110l1i <= '0'; + nl1110l1l <= '0'; + nl1110l1O <= '0'; + nl1110lii <= '0'; + nl1110lil <= '0'; + nl1110liO <= '0'; + nl1110lli <= '0'; + nl1110lll <= '0'; + nl1110llO <= '0'; + nl1110lOi <= '0'; + nl1110lOl <= '0'; + nl1110lOO <= '0'; + nl1110O0i <= '0'; + nl1110O0l <= '0'; + nl1110O0O <= '0'; + nl1110O1i <= '0'; + nl1110O1l <= '0'; + nl1110O1O <= '0'; + nl1110Oii <= '0'; + nl1110Oil <= '0'; + nl1110OiO <= '0'; + nl1110Oli <= '0'; + nl1110Oll <= '0'; + nl1110OlO <= '0'; + nl1110OOi <= '0'; + nl1110OOl <= '0'; + nl1110OOO <= '0'; + nl111i10i <= '0'; + nl111i10l <= '0'; + nl111i10O <= '0'; + nl111i11i <= '0'; + nl111i11l <= '0'; + nl111i11O <= '0'; + nl111i1ii <= '0'; + nl111iOli <= '0'; + nl111l00i <= '0'; + nl111l00l <= '0'; + nl111l00O <= '0'; + nl111l01i <= '0'; + nl111l01l <= '0'; + nl111l01O <= '0'; + nl111l0ii <= '0'; + nl111l0il <= '0'; + nl111l0iO <= '0'; + nl111l0li <= '0'; + nl111l0ll <= '0'; + nl111l0lO <= '0'; + nl111l0Oi <= '0'; + nl111l0Ol <= '0'; + nl111l0OO <= '0'; + nl111l1lO <= '0'; + nl111l1Oi <= '0'; + nl111l1Ol <= '0'; + nl111l1OO <= '0'; + nl111li0i <= '0'; + nl111li0l <= '0'; + nl111li0O <= '0'; + nl111li1i <= '0'; + nl111li1l <= '0'; + nl111li1O <= '0'; + nl111liii <= '0'; + nl111liil <= '0'; + nl111liiO <= '0'; + nl111lili <= '0'; + nl111lill <= '0'; + nl111lilO <= '0'; + nl111liOi <= '0'; + nl111liOl <= '0'; + nl111liOO <= '0'; + nl111ll1i <= '0'; + nl111ll1l <= '0'; + nl111OO0i <= '0'; + nl111OO0l <= '0'; + nl111OO0O <= '0'; + nl111OO1i <= '0'; + nl111OO1l <= '0'; + nl111OO1O <= '0'; + nl111OOii <= '0'; + nl111OOil <= '0'; + nl111OOiO <= '0'; + nl111OOli <= '0'; + nl111OOll <= '0'; + nl111OOlO <= '0'; + nl111OOOi <= '0'; + nl111OOOl <= '0'; + nl111OOOO <= '0'; + nl11i110i <= '0'; + nl11i110l <= '0'; + nl11i110O <= '0'; + nl11i111i <= '0'; + nl11i111l <= '0'; + nl11i111O <= '0'; + nl11i11ii <= '0'; + nl11i11il <= '0'; + nl11i11iO <= '0'; + nl11i11li <= '0'; + nl11i11ll <= '0'; + nl11i11lO <= '0'; + nl11i11Oi <= '0'; + nl11i11Ol <= '0'; + nl11i11OO <= '0'; + nl11iiOOi <= '0'; + nl11iiOOl <= '0'; + nl11iiOOO <= '0'; + nl11il00i <= '0'; + nl11il00l <= '0'; + nl11il00O <= '0'; + nl11il01i <= '0'; + nl11il01l <= '0'; + nl11il01O <= '0'; + nl11il0ii <= '0'; + nl11il0il <= '0'; + nl11il0iO <= '0'; + nl11il0li <= '0'; + nl11il0ll <= '0'; + nl11il0lO <= '0'; + nl11il0Oi <= '0'; + nl11il0Ol <= '0'; + nl11il0OO <= '0'; + nl11il10i <= '0'; + nl11il10l <= '0'; + nl11il10O <= '0'; + nl11il11i <= '0'; + nl11il11l <= '0'; + nl11il11O <= '0'; + nl11il1ii <= '0'; + nl11il1il <= '0'; + nl11il1iO <= '0'; + nl11il1li <= '0'; + nl11il1ll <= '0'; + nl11il1lO <= '0'; + nl11il1Oi <= '0'; + nl11il1Ol <= '0'; + nl11il1OO <= '0'; + nl11ili0i <= '0'; + nl11ili0l <= '0'; + nl11ili0O <= '0'; + nl11ili1i <= '0'; + nl11ili1l <= '0'; + nl11ili1O <= '0'; + nl11iliii <= '0'; + nl11iliil <= '0'; + nl11iliiO <= '0'; + nl11ilili <= '0'; + nl11ilill <= '0'; + nl11ililO <= '0'; + nl11iliOi <= '0'; + nl11iliOl <= '0'; + nl11iliOO <= '0'; + nl11ill0i <= '0'; + nl11ill0l <= '0'; + nl11ill0O <= '0'; + nl11ill1i <= '0'; + nl11ill1l <= '0'; + nl11ill1O <= '0'; + nl11illii <= '0'; + nl11illil <= '0'; + nl11illiO <= '0'; + nl11illli <= '0'; + nl11illll <= '0'; + nl11illlO <= '0'; + nl11illOi <= '0'; + nl11illOl <= '0'; + nl11illOO <= '0'; + nl11ilO1i <= '0'; + nl11l000i <= '0'; + nl11l000l <= '0'; + nl11l000O <= '0'; + nl11l001i <= '0'; + nl11l001l <= '0'; + nl11l001O <= '0'; + nl11l00ii <= '0'; + nl11l00il <= '0'; + nl11l00iO <= '0'; + nl11l00li <= '0'; + nl11l00ll <= '0'; + nl11l00lO <= '0'; + nl11l00Oi <= '0'; + nl11l00Ol <= '0'; + nl11l00OO <= '0'; + nl11l010i <= '0'; + nl11l010l <= '0'; + nl11l010O <= '0'; + nl11l011i <= '0'; + nl11l011l <= '0'; + nl11l011O <= '0'; + nl11l01ii <= '0'; + nl11l01il <= '0'; + nl11l01iO <= '0'; + nl11l01li <= '0'; + nl11l01ll <= '0'; + nl11l01lO <= '0'; + nl11l01Oi <= '0'; + nl11l01Ol <= '0'; + nl11l01OO <= '0'; + nl11l0i1i <= '0'; + nl11l1ili <= '0'; + nl11l1iOi <= '0'; + nl11l1iOl <= '0'; + nl11l1iOO <= '0'; + nl11l1l0i <= '0'; + nl11l1l0l <= '0'; + nl11l1l0O <= '0'; + nl11l1l1i <= '0'; + nl11l1l1l <= '0'; + nl11l1l1O <= '0'; + nl11l1lii <= '0'; + nl11l1lil <= '0'; + nl11l1liO <= '0'; + nl11l1lli <= '0'; + nl11l1lll <= '0'; + nl11l1llO <= '0'; + nl11l1lOi <= '0'; + nl11l1lOl <= '0'; + nl11l1lOO <= '0'; + nl11l1O0i <= '0'; + nl11l1O0l <= '0'; + nl11l1O0O <= '0'; + nl11l1O1i <= '0'; + nl11l1O1l <= '0'; + nl11l1O1O <= '0'; + nl11l1Oii <= '0'; + nl11l1Oil <= '0'; + nl11l1OiO <= '0'; + nl11l1Oli <= '0'; + nl11l1Oll <= '0'; + nl11l1OlO <= '0'; + nl11l1OOi <= '0'; + nl11l1OOl <= '0'; + nl11l1OOO <= '0'; + nl11lO00i <= '0'; + nl11lO00l <= '0'; + nl11lO00O <= '0'; + nl11lO01i <= '0'; + nl11lO01l <= '0'; + nl11lO01O <= '0'; + nl11lO0ii <= '0'; + nl11lO0il <= '0'; + nl11lO0iO <= '0'; + nl11lO0li <= '0'; + nl11lO0ll <= '0'; + nl11lO0lO <= '0'; + nl11lO0Oi <= '0'; + nl11lO0Ol <= '0'; + nl11lO0OO <= '0'; + nl11lO10i <= '0'; + nl11lO10l <= '0'; + nl11lO10O <= '0'; + nl11lO11i <= '0'; + nl11lO11l <= '0'; + nl11lO11O <= '0'; + nl11lO1ii <= '0'; + nl11lO1il <= '0'; + nl11lO1iO <= '0'; + nl11lO1li <= '0'; + nl11lO1ll <= '0'; + nl11lO1lO <= '0'; + nl11lO1Oi <= '0'; + nl11lO1Ol <= '0'; + nl11lO1OO <= '0'; + nl11lOi0i <= '0'; + nl11lOi0l <= '0'; + nl11lOi0O <= '0'; + nl11lOi1i <= '0'; + nl11lOi1l <= '0'; + nl11lOi1O <= '0'; + nl11lOiii <= '0'; + nl11lOiil <= '0'; + nl11lOiiO <= '0'; + nl11lOili <= '0'; + nl11lOill <= '0'; + nl11lOilO <= '0'; + nl11lOiOi <= '0'; + nl11lOiOl <= '0'; + nl11lOiOO <= '0'; + nl11lOl0i <= '0'; + nl11lOl0l <= '0'; + nl11lOl0O <= '0'; + nl11lOl1i <= '0'; + nl11lOl1l <= '0'; + nl11lOl1O <= '0'; + nl11lOlii <= '0'; + nl11lOlil <= '0'; + nl11lOliO <= '0'; + nl11lOlli <= '0'; + nl11lOlll <= '0'; + nl11lOllO <= '0'; + nl11lOlOi <= '0'; + nl11lOlOl <= '0'; + nl11lOlOO <= '0'; + nl11lOO0i <= '0'; + nl11lOO1i <= '0'; + nl11lOO1l <= '0'; + nl11lOO1O <= '0'; + nl11Oii0i <= '0'; + nl11Oii0l <= '0'; + nl11Oii0O <= '0'; + nl11OiliO <= '0'; + nl11Oilli <= '0'; + nl11Oilll <= '0'; + nl11OillO <= '0'; + nl11OilOi <= '0'; + nl11OilOl <= '0'; + nl11OilOO <= '0'; + nl11OiO0i <= '0'; + nl11OiO0l <= '0'; + nl11OiO0O <= '0'; + nl11OiO1i <= '0'; + nl11OiO1l <= '0'; + nl11OiO1O <= '0'; + nl11OiOii <= '0'; + nl11OiOil <= '0'; + nl11OiOiO <= '0'; + nl11OiOli <= '0'; + nl11OiOll <= '0'; + nl11OiOlO <= '0'; + nl11OiOOi <= '0'; + nl11OiOOl <= '0'; + nl11OiOOO <= '0'; + nl11Ol11i <= '0'; + nl11OO00i <= '0'; + nl11OO00l <= '0'; + nl11OO00O <= '0'; + nl11OO0il <= '0'; + nl11OO0iO <= '0'; + nl11OO0li <= '0'; + nl11OO0ll <= '0'; + nl11OO0lO <= '0'; + nl11OO0Oi <= '0'; + nl11OO0Ol <= '0'; + nl11OO0OO <= '0'; + nl11OOi0i <= '0'; + nl11OOi0l <= '0'; + nl11OOi0O <= '0'; + nl11OOi1i <= '0'; + nl11OOi1l <= '0'; + nl11OOiii <= '0'; + nl11OOiil <= '0'; + nl11OOiiO <= '0'; + nl11OOili <= '0'; + nl11OOill <= '0'; + nl11OOilO <= '0'; + nl11OOiOi <= '0'; + nl11OOiOl <= '0'; + nl11OOiOO <= '0'; + nl11OOl0i <= '0'; + nl11OOl0l <= '0'; + nl11OOl0O <= '0'; + nl11OOl1i <= '0'; + nl11OOl1l <= '0'; + nl11OOl1O <= '0'; + nl11OOlii <= '0'; + nl11OOlil <= '0'; + nl11OOliO <= '0'; + nl11OOlli <= '0'; + nl11OOlll <= '0'; + nl11OOllO <= '0'; + nl11OOlOi <= '0'; + nl11OOlOl <= '0'; + nl11OOlOO <= '0'; + nl11OOO0i <= '0'; + nl11OOO0l <= '0'; + nl11OOO0O <= '0'; + nl11OOO1i <= '0'; + nl11OOO1l <= '0'; + nl11OOO1O <= '0'; + nl11OOOii <= '0'; + nl1i0100i <= '0'; + nl1i0100l <= '0'; + nl1i0100O <= '0'; + nl1i0101i <= '0'; + nl1i0101l <= '0'; + nl1i0101O <= '0'; + nl1i010ii <= '0'; + nl1i010il <= '0'; + nl1i010iO <= '0'; + nl1i0110i <= '0'; + nl1i0110l <= '0'; + nl1i0110O <= '0'; + nl1i0111i <= '0'; + nl1i0111l <= '0'; + nl1i0111O <= '0'; + nl1i011ii <= '0'; + nl1i011il <= '0'; + nl1i011iO <= '0'; + nl1i011li <= '0'; + nl1i011ll <= '0'; + nl1i011lO <= '0'; + nl1i011Oi <= '0'; + nl1i011Ol <= '0'; + nl1i011OO <= '0'; + nl1i1000i <= '0'; + nl1i1000l <= '0'; + nl1i1000O <= '0'; + nl1i1001i <= '0'; + nl1i1001l <= '0'; + nl1i1001O <= '0'; + nl1i100ii <= '0'; + nl1i100il <= '0'; + nl1i100iO <= '0'; + nl1i100li <= '0'; + nl1i100ll <= '0'; + nl1i100lO <= '0'; + nl1i100Oi <= '0'; + nl1i100Ol <= '0'; + nl1i100OO <= '0'; + nl1i1010i <= '0'; + nl1i1010l <= '0'; + nl1i1010O <= '0'; + nl1i1011i <= '0'; + nl1i1011l <= '0'; + nl1i1011O <= '0'; + nl1i101ii <= '0'; + nl1i101il <= '0'; + nl1i101iO <= '0'; + nl1i101li <= '0'; + nl1i101ll <= '0'; + nl1i101lO <= '0'; + nl1i101Oi <= '0'; + nl1i101Ol <= '0'; + nl1i101OO <= '0'; + nl1i10i0i <= '0'; + nl1i10i0l <= '0'; + nl1i10i0O <= '0'; + nl1i10i1i <= '0'; + nl1i10i1l <= '0'; + nl1i10i1O <= '0'; + nl1i10iii <= '0'; + nl1i10iil <= '0'; + nl1i10iiO <= '0'; + nl1i10ili <= '0'; + nl1i10ill <= '0'; + nl1i10ilO <= '0'; + nl1i10iOi <= '0'; + nl1i1101i <= '0'; + nl1i1101l <= '0'; + nl1i1101O <= '0'; + nl1i111Oi <= '0'; + nl1i111Ol <= '0'; + nl1i111OO <= '0'; + nl1i11lOl <= '0'; + nl1i11lOO <= '0'; + nl1i11O0i <= '0'; + nl1i11O0l <= '0'; + nl1i11O0O <= '0'; + nl1i11O1i <= '0'; + nl1i11O1l <= '0'; + nl1i11O1O <= '0'; + nl1i11Oii <= '0'; + nl1i11Oil <= '0'; + nl1i11OiO <= '0'; + nl1i11Oli <= '0'; + nl1i11Oll <= '0'; + nl1i11OlO <= '0'; + nl1i11OOi <= '0'; + nl1i11OOl <= '0'; + nl1i11OOO <= '0'; + nl1i1Oili <= '0'; + nl1i1Oill <= '0'; + nl1i1OilO <= '0'; + nl1i1OiOi <= '0'; + nl1i1OiOl <= '0'; + nl1i1OiOO <= '0'; + nl1i1Ol0i <= '0'; + nl1i1Ol0l <= '0'; + nl1i1Ol0O <= '0'; + nl1i1Ol1i <= '0'; + nl1i1Ol1l <= '0'; + nl1i1Ol1O <= '0'; + nl1i1Olii <= '0'; + nl1i1Olil <= '0'; + nl1i1OliO <= '0'; + nl1i1Olli <= '0'; + nl1i1Olll <= '0'; + nl1i1OllO <= '0'; + nl1i1OlOi <= '0'; + nl1i1OlOl <= '0'; + nl1i1OlOO <= '0'; + nl1i1OO0i <= '0'; + nl1i1OO0l <= '0'; + nl1i1OO0O <= '0'; + nl1i1OO1i <= '0'; + nl1i1OO1l <= '0'; + nl1i1OO1O <= '0'; + nl1i1OOii <= '0'; + nl1i1OOil <= '0'; + nl1i1OOiO <= '0'; + nl1i1OOli <= '0'; + nl1i1OOll <= '0'; + nl1i1OOlO <= '0'; + nl1i1OOOi <= '0'; + nl1i1OOOl <= '0'; + nl1i1OOOO <= '0'; + nl1iil0Ol <= '0'; + nl1iil10O <= '0'; + nl1iiO0li <= '0'; + nl1iiO0ll <= '0'; + nl1iiO0lO <= '0'; + nl1iiO0Oi <= '0'; + nl1iiO0Ol <= '0'; + nl1iiO0OO <= '0'; + nl1iiOi0i <= '0'; + nl1iiOi0l <= '0'; + nl1iiOi0O <= '0'; + nl1iiOi1i <= '0'; + nl1iiOi1l <= '0'; + nl1iiOi1O <= '0'; + nl1iiOiii <= '0'; + nl1il1i0i <= '0'; + nl1il1i0l <= '0'; + nl1il1i0O <= '0'; + nl1il1i1l <= '0'; + nl1il1i1O <= '0'; + nl1il1iii <= '0'; + nl1il1iil <= '0'; + nl1il1iiO <= '0'; + nl1il1ili <= '0'; + nl1il1ill <= '0'; + nl1il1ilO <= '0'; + nl1il1iOi <= '0'; + nl1il1iOl <= '0'; + nl1il1iOO <= '0'; + nl1l0000i <= '0'; + nl1l0000l <= '0'; + nl1l0000O <= '0'; + nl1l0001i <= '0'; + nl1l0001l <= '0'; + nl1l0001O <= '0'; + nl1l000ii <= '0'; + nl1l000il <= '0'; + nl1l000iO <= '0'; + nl1l000li <= '0'; + nl1l000ll <= '0'; + nl1l000lO <= '0'; + nl1l000Oi <= '0'; + nl1l000Ol <= '0'; + nl1l000OO <= '0'; + nl1l0010i <= '0'; + nl1l0010l <= '0'; + nl1l0010O <= '0'; + nl1l0011i <= '0'; + nl1l0011l <= '0'; + nl1l0011O <= '0'; + nl1l001ii <= '0'; + nl1l001il <= '0'; + nl1l001iO <= '0'; + nl1l001li <= '0'; + nl1l001ll <= '0'; + nl1l001lO <= '0'; + nl1l001Oi <= '0'; + nl1l001Ol <= '0'; + nl1l001OO <= '0'; + nl1l00i0i <= '0'; + nl1l00i0l <= '0'; + nl1l00i0O <= '0'; + nl1l00i1i <= '0'; + nl1l00i1l <= '0'; + nl1l00i1O <= '0'; + nl1l00iii <= '0'; + nl1l00iil <= '0'; + nl1l00iiO <= '0'; + nl1l00ili <= '0'; + nl1l00ill <= '0'; + nl1l00ilO <= '0'; + nl1l00iOi <= '0'; + nl1l00iOl <= '0'; + nl1l00iOO <= '0'; + nl1l00l0i <= '0'; + nl1l00l0l <= '0'; + nl1l00l0O <= '0'; + nl1l00l1i <= '0'; + nl1l00l1l <= '0'; + nl1l00l1O <= '0'; + nl1l00lii <= '0'; + nl1l00lil <= '0'; + nl1l00liO <= '0'; + nl1l00lli <= '0'; + nl1l00lll <= '0'; + nl1l00llO <= '0'; + nl1l00lOi <= '0'; + nl1l00lOl <= '0'; + nl1l00lOO <= '0'; + nl1l00O0i <= '0'; + nl1l00O0l <= '0'; + nl1l00O0O <= '0'; + nl1l00O1i <= '0'; + nl1l00O1l <= '0'; + nl1l00O1O <= '0'; + nl1l00Oii <= '0'; + nl1l00Oil <= '0'; + nl1l00OiO <= '0'; + nl1l00Oli <= '0'; + nl1l00Oll <= '0'; + nl1l00OlO <= '0'; + nl1l00OOi <= '0'; + nl1l00OOl <= '0'; + nl1l00OOO <= '0'; + nl1l0100i <= '0'; + nl1l0100l <= '0'; + nl1l0100O <= '0'; + nl1l0101i <= '0'; + nl1l0101l <= '0'; + nl1l0101O <= '0'; + nl1l010ii <= '0'; + nl1l010il <= '0'; + nl1l010iO <= '0'; + nl1l010li <= '0'; + nl1l010ll <= '0'; + nl1l010lO <= '0'; + nl1l010Oi <= '0'; + nl1l010Ol <= '0'; + nl1l010OO <= '0'; + nl1l0110i <= '0'; + nl1l0110l <= '0'; + nl1l0110O <= '0'; + nl1l0111i <= '0'; + nl1l0111l <= '0'; + nl1l0111O <= '0'; + nl1l011ii <= '0'; + nl1l011il <= '0'; + nl1l011iO <= '0'; + nl1l011li <= '0'; + nl1l011ll <= '0'; + nl1l011lO <= '0'; + nl1l011Oi <= '0'; + nl1l011Ol <= '0'; + nl1l011OO <= '0'; + nl1l01i0i <= '0'; + nl1l01i0l <= '0'; + nl1l01i0O <= '0'; + nl1l01i1i <= '0'; + nl1l01i1l <= '0'; + nl1l01i1O <= '0'; + nl1l01iii <= '0'; + nl1l01iil <= '0'; + nl1l01iiO <= '0'; + nl1l01ili <= '0'; + nl1l01ill <= '0'; + nl1l01ilO <= '0'; + nl1l01iOi <= '0'; + nl1l01iOl <= '0'; + nl1l01iOO <= '0'; + nl1l01l0i <= '0'; + nl1l01l0l <= '0'; + nl1l01l0O <= '0'; + nl1l01l1i <= '0'; + nl1l01l1l <= '0'; + nl1l01l1O <= '0'; + nl1l01lii <= '0'; + nl1l01lil <= '0'; + nl1l01liO <= '0'; + nl1l01lli <= '0'; + nl1l01lll <= '0'; + nl1l01llO <= '0'; + nl1l01lOi <= '0'; + nl1l01lOl <= '0'; + nl1l01lOO <= '0'; + nl1l01O0i <= '0'; + nl1l01O0l <= '0'; + nl1l01O0O <= '0'; + nl1l01O1i <= '0'; + nl1l01O1l <= '0'; + nl1l01O1O <= '0'; + nl1l01Oii <= '0'; + nl1l01Oil <= '0'; + nl1l01OiO <= '0'; + nl1l01Oli <= '0'; + nl1l01Oll <= '0'; + nl1l01OlO <= '0'; + nl1l01OOi <= '0'; + nl1l01OOl <= '0'; + nl1l01OOO <= '0'; + nl1l0i00i <= '0'; + nl1l0i00l <= '0'; + nl1l0i00O <= '0'; + nl1l0i01i <= '0'; + nl1l0i01l <= '0'; + nl1l0i01O <= '0'; + nl1l0i0ii <= '0'; + nl1l0i0il <= '0'; + nl1l0i0iO <= '0'; + nl1l0i0li <= '0'; + nl1l0i0ll <= '0'; + nl1l0i0lO <= '0'; + nl1l0i0Oi <= '0'; + nl1l0i0Ol <= '0'; + nl1l0i0OO <= '0'; + nl1l0i10i <= '0'; + nl1l0i10l <= '0'; + nl1l0i10O <= '0'; + nl1l0i11i <= '0'; + nl1l0i11l <= '0'; + nl1l0i11O <= '0'; + nl1l0i1ii <= '0'; + nl1l0i1il <= '0'; + nl1l0i1iO <= '0'; + nl1l0i1li <= '0'; + nl1l0i1ll <= '0'; + nl1l0i1lO <= '0'; + nl1l0i1Oi <= '0'; + nl1l0i1Ol <= '0'; + nl1l0i1OO <= '0'; + nl1l0ii0i <= '0'; + nl1l0ii0l <= '0'; + nl1l0ii0O <= '0'; + nl1l0ii1i <= '0'; + nl1l0ii1l <= '0'; + nl1l0ii1O <= '0'; + nl1l0iiii <= '0'; + nl1l0iiil <= '0'; + nl1l0iiiO <= '0'; + nl1l0iili <= '0'; + nl1l0iill <= '0'; + nl1l0iilO <= '0'; + nl1l0iiOi <= '0'; + nl1l0iiOl <= '0'; + nl1l0iiOO <= '0'; + nl1l0il0i <= '0'; + nl1l0il0l <= '0'; + nl1l0il0O <= '0'; + nl1l0il1i <= '0'; + nl1l0il1l <= '0'; + nl1l0il1O <= '0'; + nl1l0ilii <= '0'; + nl1l0ilil <= '0'; + nl1l0iliO <= '0'; + nl1l0illi <= '0'; + nl1l0illl <= '0'; + nl1l0illO <= '0'; + nl1l0ilOi <= '0'; + nl1l0ilOl <= '0'; + nl1l0ilOO <= '0'; + nl1l0iO0i <= '0'; + nl1l0iO0l <= '0'; + nl1l0iO0O <= '0'; + nl1l0iO1i <= '0'; + nl1l0iO1l <= '0'; + nl1l0iO1O <= '0'; + nl1l0iOii <= '0'; + nl1l0iOil <= '0'; + nl1l0iOiO <= '0'; + nl1l0iOli <= '0'; + nl1l0iOll <= '0'; + nl1l0iOlO <= '0'; + nl1l0iOOi <= '0'; + nl1l0iOOl <= '0'; + nl1l0iOOO <= '0'; + nl1l0l00i <= '0'; + nl1l0l00l <= '0'; + nl1l0l00O <= '0'; + nl1l0l01i <= '0'; + nl1l0l01l <= '0'; + nl1l0l01O <= '0'; + nl1l0l0ii <= '0'; + nl1l0l0il <= '0'; + nl1l0l0iO <= '0'; + nl1l0l0li <= '0'; + nl1l0l0ll <= '0'; + nl1l0l0lO <= '0'; + nl1l0l0Oi <= '0'; + nl1l0l0Ol <= '0'; + nl1l0l0OO <= '0'; + nl1l0l10i <= '0'; + nl1l0l10l <= '0'; + nl1l0l10O <= '0'; + nl1l0l11i <= '0'; + nl1l0l11l <= '0'; + nl1l0l11O <= '0'; + nl1l0l1ii <= '0'; + nl1l0l1il <= '0'; + nl1l0l1iO <= '0'; + nl1l0l1li <= '0'; + nl1l0l1ll <= '0'; + nl1l0l1lO <= '0'; + nl1l0l1Oi <= '0'; + nl1l0l1Ol <= '0'; + nl1l0l1OO <= '0'; + nl1l0li0i <= '0'; + nl1l0li0l <= '0'; + nl1l0li0O <= '0'; + nl1l0li1i <= '0'; + nl1l0li1l <= '0'; + nl1l0li1O <= '0'; + nl1l0liii <= '0'; + nl1l0liil <= '0'; + nl1l0liiO <= '0'; + nl1l0lili <= '0'; + nl1l0lill <= '0'; + nl1l0lilO <= '0'; + nl1l0liOi <= '0'; + nl1l0liOl <= '0'; + nl1l0liOO <= '0'; + nl1l0ll0i <= '0'; + nl1l0ll0l <= '0'; + nl1l0ll0O <= '0'; + nl1l0ll1i <= '0'; + nl1l0ll1l <= '0'; + nl1l0ll1O <= '0'; + nl1l0llii <= '0'; + nl1l0llil <= '0'; + nl1l0lliO <= '0'; + nl1l0llli <= '0'; + nl1l0llll <= '0'; + nl1l0lllO <= '0'; + nl1l0llOi <= '0'; + nl1l0llOl <= '0'; + nl1l0llOO <= '0'; + nl1l0lO0i <= '0'; + nl1l0lO0l <= '0'; + nl1l0lO0O <= '0'; + nl1l0lO1i <= '0'; + nl1l0lO1l <= '0'; + nl1l0lO1O <= '0'; + nl1l0lOii <= '0'; + nl1l0lOil <= '0'; + nl1l0lOiO <= '0'; + nl1l0lOli <= '0'; + nl1l1ilOO <= '0'; + nl1l1iO0i <= '0'; + nl1l1iO0l <= '0'; + nl1l1iO1i <= '0'; + nl1l1iO1l <= '0'; + nl1l1iO1O <= '0'; + nl1l1iOii <= '0'; + nl1l1iOil <= '0'; + nl1l1iOiO <= '0'; + nl1l1iOli <= '0'; + nl1l1iOlO <= '0'; + nl1l1iOOi <= '0'; + nl1l1iOOl <= '0'; + nl1l1iOOO <= '0'; + nl1l1l00i <= '0'; + nl1l1l00l <= '0'; + nl1l1l00O <= '0'; + nl1l1l01i <= '0'; + nl1l1l01l <= '0'; + nl1l1l01O <= '0'; + nl1l1l0ii <= '0'; + nl1l1l0il <= '0'; + nl1l1l0iO <= '0'; + nl1l1l0li <= '0'; + nl1l1l0ll <= '0'; + nl1l1l0lO <= '0'; + nl1l1l0Oi <= '0'; + nl1l1l0Ol <= '0'; + nl1l1l0OO <= '0'; + nl1l1l10i <= '0'; + nl1l1l10l <= '0'; + nl1l1l10O <= '0'; + nl1l1l11i <= '0'; + nl1l1l11l <= '0'; + nl1l1l11O <= '0'; + nl1l1l1ii <= '0'; + nl1l1l1il <= '0'; + nl1l1l1iO <= '0'; + nl1l1l1li <= '0'; + nl1l1l1ll <= '0'; + nl1l1l1lO <= '0'; + nl1l1l1Oi <= '0'; + nl1l1l1Ol <= '0'; + nl1l1l1OO <= '0'; + nl1l1li0i <= '0'; + nl1l1li0l <= '0'; + nl1l1li0O <= '0'; + nl1l1li1i <= '0'; + nl1l1li1l <= '0'; + nl1l1li1O <= '0'; + nl1l1liii <= '0'; + nl1l1liil <= '0'; + nl1l1liiO <= '0'; + nl1l1lili <= '0'; + nl1l1lill <= '0'; + nl1l1lilO <= '0'; + nl1l1liOi <= '0'; + nl1l1liOl <= '0'; + nl1l1liOO <= '0'; + nl1l1ll0i <= '0'; + nl1l1ll0l <= '0'; + nl1l1ll0O <= '0'; + nl1l1ll1i <= '0'; + nl1l1ll1l <= '0'; + nl1l1ll1O <= '0'; + nl1l1llii <= '0'; + nl1l1llil <= '0'; + nl1l1lliO <= '0'; + nl1l1llli <= '0'; + nl1l1llll <= '0'; + nl1l1lllO <= '0'; + nl1l1llOi <= '0'; + nl1l1llOl <= '0'; + nl1l1llOO <= '0'; + nl1l1lO0i <= '0'; + nl1l1lO0l <= '0'; + nl1l1lO0O <= '0'; + nl1l1lO1i <= '0'; + nl1l1lO1l <= '0'; + nl1l1lO1O <= '0'; + nl1l1lOii <= '0'; + nl1l1lOil <= '0'; + nl1l1lOiO <= '0'; + nl1l1lOli <= '0'; + nl1l1lOll <= '0'; + nl1l1lOlO <= '0'; + nl1l1lOOi <= '0'; + nl1l1lOOl <= '0'; + nl1l1lOOO <= '0'; + nl1l1O00i <= '0'; + nl1l1O00l <= '0'; + nl1l1O00O <= '0'; + nl1l1O01i <= '0'; + nl1l1O01l <= '0'; + nl1l1O01O <= '0'; + nl1l1O0ii <= '0'; + nl1l1O0il <= '0'; + nl1l1O0iO <= '0'; + nl1l1O0li <= '0'; + nl1l1O0ll <= '0'; + nl1l1O0lO <= '0'; + nl1l1O0Oi <= '0'; + nl1l1O0Ol <= '0'; + nl1l1O0OO <= '0'; + nl1l1O10i <= '0'; + nl1l1O10l <= '0'; + nl1l1O10O <= '0'; + nl1l1O11i <= '0'; + nl1l1O11l <= '0'; + nl1l1O11O <= '0'; + nl1l1O1ii <= '0'; + nl1l1O1il <= '0'; + nl1l1O1iO <= '0'; + nl1l1O1li <= '0'; + nl1l1O1ll <= '0'; + nl1l1O1lO <= '0'; + nl1l1O1Oi <= '0'; + nl1l1O1Ol <= '0'; + nl1l1O1OO <= '0'; + nl1l1Oi0i <= '0'; + nl1l1Oi0l <= '0'; + nl1l1Oi0O <= '0'; + nl1l1Oi1i <= '0'; + nl1l1Oi1l <= '0'; + nl1l1Oi1O <= '0'; + nl1l1Oiii <= '0'; + nl1l1Oiil <= '0'; + nl1l1OiiO <= '0'; + nl1l1Oili <= '0'; + nl1l1Oill <= '0'; + nl1l1OilO <= '0'; + nl1l1OiOi <= '0'; + nl1l1OiOl <= '0'; + nl1l1OiOO <= '0'; + nl1l1Ol0i <= '0'; + nl1l1Ol0l <= '0'; + nl1l1Ol0O <= '0'; + nl1l1Ol1i <= '0'; + nl1l1Ol1l <= '0'; + nl1l1Ol1O <= '0'; + nl1l1Olii <= '0'; + nl1l1Olil <= '0'; + nl1l1OliO <= '0'; + nl1l1Olli <= '0'; + nl1l1Olll <= '0'; + nl1l1OllO <= '0'; + nl1l1OlOi <= '0'; + nl1l1OlOl <= '0'; + nl1l1OlOO <= '0'; + nl1l1OO0i <= '0'; + nl1l1OO0l <= '0'; + nl1l1OO0O <= '0'; + nl1l1OO1i <= '0'; + nl1l1OO1l <= '0'; + nl1l1OO1O <= '0'; + nl1l1OOii <= '0'; + nl1l1OOil <= '0'; + nl1l1OOiO <= '0'; + nl1l1OOli <= '0'; + nl1l1OOll <= '0'; + nl1l1OOlO <= '0'; + nl1l1OOOi <= '0'; + nl1l1OOOl <= '0'; + nl1l1OOOO <= '0'; + nl1ll0iil <= '0'; + nl1ll0iiO <= '0'; + nl1ll0ili <= '0'; + nl1ll0ill <= '0'; + nl1ll0ilO <= '0'; + nl1ll0iOi <= '0'; + nl1ll0iOl <= '0'; + nl1ll0l0i <= '0'; + nl1ll0l0l <= '0'; + nl1ll0l0O <= '0'; + nl1ll0l1i <= '0'; + nl1ll0l1l <= '0'; + nl1ll0l1O <= '0'; + nl1ll0lii <= '0'; + nl1ll0lil <= '0'; + nl1ll0liO <= '0'; + nl1ll0lli <= '0'; + nl1ll0lll <= '0'; + nl1ll0llO <= '0'; + nl1ll0lOi <= '0'; + nl1ll0lOl <= '0'; + nl1ll0lOO <= '0'; + nl1lO1iiO <= '0'; + nl1lO1ilO <= '0'; + nl1O0000i <= '0'; + nl1O0000l <= '0'; + nl1O0000O <= '0'; + nl1O0001i <= '0'; + nl1O0001l <= '0'; + nl1O0001O <= '0'; + nl1O000ii <= '0'; + nl1O000il <= '0'; + nl1O000iO <= '0'; + nl1O000li <= '0'; + nl1O000ll <= '0'; + nl1O000lO <= '0'; + nl1O000Oi <= '0'; + nl1O000Ol <= '0'; + nl1O000OO <= '0'; + nl1O0010i <= '0'; + nl1O0010l <= '0'; + nl1O0010O <= '0'; + nl1O0011i <= '0'; + nl1O0011l <= '0'; + nl1O0011O <= '0'; + nl1O001ii <= '0'; + nl1O001il <= '0'; + nl1O001iO <= '0'; + nl1O001li <= '0'; + nl1O001ll <= '0'; + nl1O001lO <= '0'; + nl1O001Oi <= '0'; + nl1O001Ol <= '0'; + nl1O001OO <= '0'; + nl1O00i0i <= '0'; + nl1O00i0l <= '0'; + nl1O00i0O <= '0'; + nl1O00i1i <= '0'; + nl1O00i1l <= '0'; + nl1O00i1O <= '0'; + nl1O00iii <= '0'; + nl1O00iil <= '0'; + nl1O00iiO <= '0'; + nl1O00ili <= '0'; + nl1O00ill <= '0'; + nl1O00ilO <= '0'; + nl1O00iOi <= '0'; + nl1O00iOl <= '0'; + nl1O00iOO <= '0'; + nl1O00l0i <= '0'; + nl1O00l0l <= '0'; + nl1O00l0O <= '0'; + nl1O00l1i <= '0'; + nl1O00l1l <= '0'; + nl1O00l1O <= '0'; + nl1O00lii <= '0'; + nl1O00lil <= '0'; + nl1O00liO <= '0'; + nl1O00lli <= '0'; + nl1O00lll <= '0'; + nl1O00llO <= '0'; + nl1O00lOi <= '0'; + nl1O00lOl <= '0'; + nl1O00lOO <= '0'; + nl1O00O0i <= '0'; + nl1O00O0l <= '0'; + nl1O00O0O <= '0'; + nl1O00O1i <= '0'; + nl1O00O1l <= '0'; + nl1O00O1O <= '0'; + nl1O00Oii <= '0'; + nl1O00Oil <= '0'; + nl1O00OiO <= '0'; + nl1O00Oli <= '0'; + nl1O00Oll <= '0'; + nl1O00OlO <= '0'; + nl1O00OOi <= '0'; + nl1O00OOl <= '0'; + nl1O00OOO <= '0'; + nl1O0100i <= '0'; + nl1O0100l <= '0'; + nl1O0100O <= '0'; + nl1O0101i <= '0'; + nl1O0101l <= '0'; + nl1O0101O <= '0'; + nl1O010ii <= '0'; + nl1O010il <= '0'; + nl1O010iO <= '0'; + nl1O010li <= '0'; + nl1O010ll <= '0'; + nl1O010lO <= '0'; + nl1O010Oi <= '0'; + nl1O010Ol <= '0'; + nl1O010OO <= '0'; + nl1O0110i <= '0'; + nl1O0110l <= '0'; + nl1O0110O <= '0'; + nl1O0111i <= '0'; + nl1O0111l <= '0'; + nl1O0111O <= '0'; + nl1O011ii <= '0'; + nl1O011il <= '0'; + nl1O011iO <= '0'; + nl1O011li <= '0'; + nl1O011ll <= '0'; + nl1O011lO <= '0'; + nl1O011Oi <= '0'; + nl1O011Ol <= '0'; + nl1O011OO <= '0'; + nl1O01i0i <= '0'; + nl1O01i0l <= '0'; + nl1O01i0O <= '0'; + nl1O01i1i <= '0'; + nl1O01i1l <= '0'; + nl1O01i1O <= '0'; + nl1O01iii <= '0'; + nl1O01iil <= '0'; + nl1O01iiO <= '0'; + nl1O01ili <= '0'; + nl1O01ill <= '0'; + nl1O01ilO <= '0'; + nl1O01iOi <= '0'; + nl1O01iOl <= '0'; + nl1O01iOO <= '0'; + nl1O01l0i <= '0'; + nl1O01l0l <= '0'; + nl1O01l0O <= '0'; + nl1O01l1i <= '0'; + nl1O01l1l <= '0'; + nl1O01l1O <= '0'; + nl1O01lii <= '0'; + nl1O01lil <= '0'; + nl1O01liO <= '0'; + nl1O01lli <= '0'; + nl1O01lll <= '0'; + nl1O01llO <= '0'; + nl1O01lOi <= '0'; + nl1O01lOl <= '0'; + nl1O01lOO <= '0'; + nl1O01O0i <= '0'; + nl1O01O0l <= '0'; + nl1O01O0O <= '0'; + nl1O01O1i <= '0'; + nl1O01O1l <= '0'; + nl1O01O1O <= '0'; + nl1O01Oii <= '0'; + nl1O01Oil <= '0'; + nl1O01OiO <= '0'; + nl1O01Oli <= '0'; + nl1O01Oll <= '0'; + nl1O01OlO <= '0'; + nl1O01OOi <= '0'; + nl1O01OOl <= '0'; + nl1O01OOO <= '0'; + nl1O0i00i <= '0'; + nl1O0i00l <= '0'; + nl1O0i00O <= '0'; + nl1O0i01i <= '0'; + nl1O0i01l <= '0'; + nl1O0i01O <= '0'; + nl1O0i0ii <= '0'; + nl1O0i0il <= '0'; + nl1O0i0iO <= '0'; + nl1O0i0li <= '0'; + nl1O0i0ll <= '0'; + nl1O0i0lO <= '0'; + nl1O0i0Oi <= '0'; + nl1O0i0Ol <= '0'; + nl1O0i0OO <= '0'; + nl1O0i10i <= '0'; + nl1O0i10l <= '0'; + nl1O0i10O <= '0'; + nl1O0i11i <= '0'; + nl1O0i11l <= '0'; + nl1O0i11O <= '0'; + nl1O0i1ii <= '0'; + nl1O0i1il <= '0'; + nl1O0i1iO <= '0'; + nl1O0i1li <= '0'; + nl1O0i1ll <= '0'; + nl1O0i1lO <= '0'; + nl1O0i1Oi <= '0'; + nl1O0i1Ol <= '0'; + nl1O0i1OO <= '0'; + nl1O0ii0i <= '0'; + nl1O0ii0l <= '0'; + nl1O0ii0O <= '0'; + nl1O0ii1i <= '0'; + nl1O0ii1l <= '0'; + nl1O0ii1O <= '0'; + nl1O0iiii <= '0'; + nl1O1i0OO <= '0'; + nl1O1ii0i <= '0'; + nl1O1ii0l <= '0'; + nl1O1ii0O <= '0'; + nl1O1ii1i <= '0'; + nl1O1ii1l <= '0'; + nl1O1ii1O <= '0'; + nl1O1iiii <= '0'; + nl1O1iiil <= '0'; + nl1O1iiiO <= '0'; + nl1O1iili <= '0'; + nl1O1iill <= '0'; + nl1O1iilO <= '0'; + nl1O1iiOi <= '0'; + nl1O1iiOl <= '0'; + nl1O1iiOO <= '0'; + nl1O1il0i <= '0'; + nl1O1il0l <= '0'; + nl1O1il0O <= '0'; + nl1O1il1i <= '0'; + nl1O1il1l <= '0'; + nl1O1il1O <= '0'; + nl1O1ilii <= '0'; + nl1O1ilil <= '0'; + nl1O1iliO <= '0'; + nl1O1illi <= '0'; + nl1O1illl <= '0'; + nl1O1illO <= '0'; + nl1O1ilOi <= '0'; + nl1O1ilOl <= '0'; + nl1O1ilOO <= '0'; + nl1O1iO0i <= '0'; + nl1O1iO0l <= '0'; + nl1O1iO0O <= '0'; + nl1O1iO1i <= '0'; + nl1O1iO1l <= '0'; + nl1O1iO1O <= '0'; + nl1O1iOii <= '0'; + nl1O1iOil <= '0'; + nl1O1iOiO <= '0'; + nl1O1iOli <= '0'; + nl1O1iOll <= '0'; + nl1O1iOlO <= '0'; + nl1O1iOOi <= '0'; + nl1O1iOOl <= '0'; + nl1O1iOOO <= '0'; + nl1O1l00i <= '0'; + nl1O1l00l <= '0'; + nl1O1l00O <= '0'; + nl1O1l01i <= '0'; + nl1O1l01l <= '0'; + nl1O1l01O <= '0'; + nl1O1l0ii <= '0'; + nl1O1l0il <= '0'; + nl1O1l0iO <= '0'; + nl1O1l0li <= '0'; + nl1O1l0ll <= '0'; + nl1O1l0lO <= '0'; + nl1O1l0Oi <= '0'; + nl1O1l0Ol <= '0'; + nl1O1l0OO <= '0'; + nl1O1l10i <= '0'; + nl1O1l10l <= '0'; + nl1O1l10O <= '0'; + nl1O1l11i <= '0'; + nl1O1l11l <= '0'; + nl1O1l11O <= '0'; + nl1O1l1ii <= '0'; + nl1O1l1il <= '0'; + nl1O1l1iO <= '0'; + nl1O1l1li <= '0'; + nl1O1l1ll <= '0'; + nl1O1l1lO <= '0'; + nl1O1l1Oi <= '0'; + nl1O1l1Ol <= '0'; + nl1O1l1OO <= '0'; + nl1O1li0i <= '0'; + nl1O1li0l <= '0'; + nl1O1li0O <= '0'; + nl1O1li1i <= '0'; + nl1O1li1l <= '0'; + nl1O1li1O <= '0'; + nl1O1liii <= '0'; + nl1O1liil <= '0'; + nl1O1liiO <= '0'; + nl1O1lili <= '0'; + nl1O1lill <= '0'; + nl1O1lilO <= '0'; + nl1O1liOi <= '0'; + nl1O1liOl <= '0'; + nl1O1liOO <= '0'; + nl1O1ll0i <= '0'; + nl1O1ll0l <= '0'; + nl1O1ll0O <= '0'; + nl1O1ll1i <= '0'; + nl1O1ll1l <= '0'; + nl1O1ll1O <= '0'; + nl1O1llii <= '0'; + nl1O1llil <= '0'; + nl1O1lliO <= '0'; + nl1O1llli <= '0'; + nl1O1llll <= '0'; + nl1O1lllO <= '0'; + nl1O1llOi <= '0'; + nl1O1llOl <= '0'; + nl1O1llOO <= '0'; + nl1O1lO0i <= '0'; + nl1O1lO0l <= '0'; + nl1O1lO0O <= '0'; + nl1O1lO1i <= '0'; + nl1O1lO1l <= '0'; + nl1O1lO1O <= '0'; + nl1O1lOii <= '0'; + nl1O1lOil <= '0'; + nl1O1lOiO <= '0'; + nl1O1lOli <= '0'; + nl1O1lOll <= '0'; + nl1O1lOlO <= '0'; + nl1O1lOOi <= '0'; + nl1O1lOOl <= '0'; + nl1O1lOOO <= '0'; + nl1O1O00i <= '0'; + nl1O1O00l <= '0'; + nl1O1O00O <= '0'; + nl1O1O01i <= '0'; + nl1O1O01l <= '0'; + nl1O1O01O <= '0'; + nl1O1O0ii <= '0'; + nl1O1O0il <= '0'; + nl1O1O0iO <= '0'; + nl1O1O0li <= '0'; + nl1O1O0ll <= '0'; + nl1O1O0lO <= '0'; + nl1O1O0Oi <= '0'; + nl1O1O0Ol <= '0'; + nl1O1O0OO <= '0'; + nl1O1O10i <= '0'; + nl1O1O10l <= '0'; + nl1O1O10O <= '0'; + nl1O1O11i <= '0'; + nl1O1O11l <= '0'; + nl1O1O11O <= '0'; + nl1O1O1ii <= '0'; + nl1O1O1il <= '0'; + nl1O1O1iO <= '0'; + nl1O1O1li <= '0'; + nl1O1O1ll <= '0'; + nl1O1O1lO <= '0'; + nl1O1O1Oi <= '0'; + nl1O1O1Ol <= '0'; + nl1O1O1OO <= '0'; + nl1O1Oi0i <= '0'; + nl1O1Oi0l <= '0'; + nl1O1Oi0O <= '0'; + nl1O1Oi1i <= '0'; + nl1O1Oi1l <= '0'; + nl1O1Oi1O <= '0'; + nl1O1Oiii <= '0'; + nl1O1Oiil <= '0'; + nl1O1OiiO <= '0'; + nl1O1Oili <= '0'; + nl1O1Oill <= '0'; + nl1O1OilO <= '0'; + nl1O1OiOi <= '0'; + nl1O1OiOl <= '0'; + nl1O1OiOO <= '0'; + nl1O1Ol0i <= '0'; + nl1O1Ol0l <= '0'; + nl1O1Ol0O <= '0'; + nl1O1Ol1i <= '0'; + nl1O1Ol1l <= '0'; + nl1O1Ol1O <= '0'; + nl1O1Olii <= '0'; + nl1O1Olil <= '0'; + nl1O1OliO <= '0'; + nl1O1Olli <= '0'; + nl1O1Olll <= '0'; + nl1O1OllO <= '0'; + nl1O1OlOi <= '0'; + nl1O1OlOl <= '0'; + nl1O1OlOO <= '0'; + nl1O1OO0i <= '0'; + nl1O1OO0l <= '0'; + nl1O1OO0O <= '0'; + nl1O1OO1i <= '0'; + nl1O1OO1l <= '0'; + nl1O1OO1O <= '0'; + nl1O1OOii <= '0'; + nl1O1OOil <= '0'; + nl1O1OOiO <= '0'; + nl1O1OOli <= '0'; + nl1O1OOll <= '0'; + nl1O1OOlO <= '0'; + nl1O1OOOi <= '0'; + nl1O1OOOl <= '0'; + nl1O1OOOO <= '0'; + nl1Oill0l <= '0'; + nl1Oill0O <= '0'; + nl1Oillii <= '0'; + nl1Oillil <= '0'; + nl1OilliO <= '0'; + nl1Oillli <= '0'; + nl1Oillll <= '0'; + nl1OilllO <= '0'; + nl1OillOi <= '0'; + nl1OillOl <= '0'; + nl1OillOO <= '0'; + nl1OilO0l <= '0'; + nl1OilO0O <= '0'; + nl1OilO1i <= '0'; + nl1OilO1l <= '0'; + nl1OilO1O <= '0'; + nl1OilOii <= '0'; + nl1OilOil <= '0'; + nl1Ol011i <= '0'; + nl1Ol011l <= '0'; + nl1Ol011O <= '0'; + nl1Ol1l0i <= '0'; + nl1Ol1l0l <= '0'; + nl1Ol1l0O <= '0'; + nl1Ol1lii <= '0'; + nl1Ol1lil <= '0'; + nl1Ol1liO <= '0'; + nl1Ol1lli <= '0'; + nl1Ol1lll <= '0'; + nl1Ol1llO <= '0'; + nl1Ol1lOi <= '0'; + nl1Ol1lOl <= '0'; + nl1Ol1lOO <= '0'; + nl1Ol1O0i <= '0'; + nl1Ol1O0l <= '0'; + nl1Ol1O0O <= '0'; + nl1Ol1O1i <= '0'; + nl1Ol1O1l <= '0'; + nl1Ol1O1O <= '0'; + nl1Ol1Oii <= '0'; + nl1Ol1Oil <= '0'; + nl1Ol1OiO <= '0'; + nl1Ol1Oli <= '0'; + nl1Ol1Oll <= '0'; + nl1Ol1OlO <= '0'; + nl1Ol1OOi <= '0'; + nl1Ol1OOl <= '0'; + nl1Ol1OOO <= '0'; + nl1OllOOl <= '0'; + nl1OllOOO <= '0'; + nl1OlO11i <= '0'; + nl1OlO11l <= '0'; + nl1OlO11O <= '0'; + nl1OO010i <= '0'; + nl1OO010l <= '0'; + nl1OO010O <= '0'; + nl1OO011i <= '0'; + nl1OO011l <= '0'; + nl1OO011O <= '0'; + nl1OO1O0i <= '0'; + nl1OO1O0l <= '0'; + nl1OO1O0O <= '0'; + nl1OO1O1l <= '0'; + nl1OO1O1O <= '0'; + nl1OO1Oii <= '0'; + nl1OO1Oil <= '0'; + nl1OO1OiO <= '0'; + nl1OO1Oli <= '0'; + nl1OO1Oll <= '0'; + nl1OO1OlO <= '0'; + nl1OO1OOi <= '0'; + nl1OO1OOl <= '0'; + nl1OO1OOO <= '0'; + nl1OOi00i <= '0'; + nl1OOi00l <= '0'; + nl1OOi00O <= '0'; + nl1OOi01i <= '0'; + nl1OOi01l <= '0'; + nl1OOi01O <= '0'; + nl1OOi0ii <= '0'; + nl1OOi0il <= '0'; + nl1OOi0iO <= '0'; + nl1OOi0li <= '0'; + nl1OOi0ll <= '0'; + nl1OOi0lO <= '0'; + nl1OOi0Oi <= '0'; + nl1OOi0Ol <= '0'; + nl1OOi0OO <= '0'; + nl1OOi1lO <= '0'; + nl1OOi1Oi <= '0'; + nl1OOi1Ol <= '0'; + nl1OOi1OO <= '0'; + nl1OOii0i <= '0'; + nl1OOii0l <= '0'; + nl1OOii0O <= '0'; + nl1OOii1i <= '0'; + nl1OOii1l <= '0'; + nl1OOiiii <= '0'; + nl1OOiiil <= '0'; + nl1OOiiiO <= '0'; + nl1OOiili <= '0'; + nl1OOiill <= '0'; + nl1OOiilO <= '0'; + nl1OOiiOi <= '0'; + nl1OOiiOl <= '0'; + nl1OOiiOO <= '0'; + nl1OOil1i <= '0'; + nl1OOil1l <= '0'; + nl1OOil1O <= '0'; + nli0Oi0lO <= '0'; + nli0Oi0Ol <= '0'; + nli0Oi0OO <= '0'; + nli0Oiill <= '0'; + nli0OiilO <= '0'; + nli0OiiOi <= '0'; + nli0OOOlO <= '0'; + nli0OOOOi <= '0'; + nli0OOOOl <= '0'; + nli0OOOOO <= '0'; + nli10001i <= '0'; + nli10001l <= '0'; + nli10001O <= '0'; + nli10010i <= '0'; + nli10010l <= '0'; + nli10010O <= '0'; + nli10011i <= '0'; + nli10011l <= '0'; + nli10011O <= '0'; + nli1001ii <= '0'; + nli1001il <= '0'; + nli1001iO <= '0'; + nli1001li <= '0'; + nli1001ll <= '0'; + nli1001lO <= '0'; + nli1001Oi <= '0'; + nli1001Ol <= '0'; + nli1001OO <= '0'; + nli1010ll <= '0'; + nli1010lO <= '0'; + nli1010Oi <= '0'; + nli1010Ol <= '0'; + nli1010OO <= '0'; + nli101i0i <= '0'; + nli101i0l <= '0'; + nli101i0O <= '0'; + nli101i1i <= '0'; + nli101i1l <= '0'; + nli101i1O <= '0'; + nli101iii <= '0'; + nli101iil <= '0'; + nli101iiO <= '0'; + nli101ili <= '0'; + nli101ill <= '0'; + nli101ilO <= '0'; + nli101iOi <= '0'; + nli101iOl <= '0'; + nli101iOO <= '0'; + nli101l0i <= '0'; + nli101l0l <= '0'; + nli101l0O <= '0'; + nli101l1i <= '0'; + nli101l1l <= '0'; + nli101l1O <= '0'; + nli101lii <= '0'; + nli101lil <= '0'; + nli101liO <= '0'; + nli101lli <= '0'; + nli101lll <= '0'; + nli101llO <= '0'; + nli101lOi <= '0'; + nli101lOl <= '0'; + nli101lOO <= '0'; + nli101O0i <= '0'; + nli101O0l <= '0'; + nli101O0O <= '0'; + nli101O1i <= '0'; + nli101O1l <= '0'; + nli101O1O <= '0'; + nli101Oii <= '0'; + nli101Oil <= '0'; + nli101OiO <= '0'; + nli101Oli <= '0'; + nli101Oll <= '0'; + nli101OlO <= '0'; + nli101OOi <= '0'; + nli101OOl <= '0'; + nli101OOO <= '0'; + nli10Oiil <= '0'; + nli10OiiO <= '0'; + nli10Oili <= '0'; + nli10Oill <= '0'; + nli10Olil <= '0'; + nli10OliO <= '0'; + nli10Olli <= '0'; + nli10Olll <= '0'; + nli10OllO <= '0'; + nli10OlOi <= '0'; + nli10OlOl <= '0'; + nli10OlOO <= '0'; + nli10OO0i <= '0'; + nli10OO0l <= '0'; + nli10OO1i <= '0'; + nli10OO1l <= '0'; + nli10OO1O <= '0'; + nli11000i <= '0'; + nli11000l <= '0'; + nli11000O <= '0'; + nli11001i <= '0'; + nli11001l <= '0'; + nli11001O <= '0'; + nli1100ii <= '0'; + nli1100il <= '0'; + nli1100iO <= '0'; + nli11010i <= '0'; + nli11010l <= '0'; + nli11010O <= '0'; + nli1101ii <= '0'; + nli1101il <= '0'; + nli1101iO <= '0'; + nli1101li <= '0'; + nli1101ll <= '0'; + nli1101lO <= '0'; + nli1101Oi <= '0'; + nli1101Ol <= '0'; + nli1101OO <= '0'; + nli111i1l <= '0'; + nli11iiii <= '0'; + nli11iill <= '0'; + nli11ilil <= '0'; + nli11iliO <= '0'; + nli11illi <= '0'; + nli11illl <= '0'; + nli11illO <= '0'; + nli11l0Ol <= '0'; + nli11l0OO <= '0'; + nli11O0ii <= '0'; + nli11OiOl <= '0'; + nli11Ol0i <= '0'; + nli11Ol0l <= '0'; + nli11Ol0O <= '0'; + nli11Olii <= '0'; + nli11Olil <= '0'; + nli11OOll <= '0'; + nli11OOlO <= '0'; + nli11OOOi <= '0'; + nli11OOOl <= '0'; + nli11OOOO <= '0'; + nli1i001i <= '0'; + nli1i011i <= '0'; + nli1i01li <= '0'; + nli1i01ll <= '0'; + nli1i01lO <= '0'; + nli1i01Oi <= '0'; + nli1i01Ol <= '0'; + nli1i01OO <= '0'; + nli1i1OOi <= '0'; + nli1i1OOl <= '0'; + nli1i1OOO <= '0'; + nli1ii0li <= '0'; + nli1ii0ll <= '0'; + nli1iiiiO <= '0'; + nli1iiili <= '0'; + nli1iiill <= '0'; + nli1iiilO <= '0'; + nli1iiiOi <= '0'; + nli1iiiOl <= '0'; + nli1iiOlO <= '0'; + nli1iiOOi <= '0'; + nli1iiOOl <= '0'; + nli1iiOOO <= '0'; + nli1il10i <= '0'; + nli1il10l <= '0'; + nli1il10O <= '0'; + nli1il11i <= '0'; + nli1il11l <= '0'; + nli1il11O <= '0'; + nli1il1ii <= '0'; + nli1illiO <= '0'; + nli1illli <= '0'; + nli1illll <= '0'; + nli1illlO <= '0'; + nli1illOi <= '0'; + nli1illOl <= '0'; + nli1illOO <= '0'; + nli1ilO1i <= '0'; + nli1ilO1l <= '0'; + nli1iO0OO <= '0'; + nli1iOi0l <= '0'; + nli1iOiii <= '0'; + nli1iOiiO <= '0'; + nli1iOili <= '0'; + nli1iOill <= '0'; + nli1iOilO <= '0'; + nli1iOiOl <= '0'; + nli1iOiOO <= '0'; + nli1iOl1i <= '0'; + nli1iOl1l <= '0'; + nli1iOl1O <= '0'; + nli1l000i <= '0'; + nli1l000l <= '0'; + nli1l000O <= '0'; + nli1l001O <= '0'; + nli1l00ii <= '0'; + nli1l00il <= '0'; + nli1l00iO <= '0'; + nli1l00li <= '0'; + nli1l00ll <= '0'; + nli1l00lO <= '0'; + nli1l00Oi <= '0'; + nli1l00Ol <= '0'; + nli1l00OO <= '0'; + nli1l110O <= '0'; + nli1l11ii <= '0'; + nli1l11il <= '0'; + nli1l11iO <= '0'; + nli1l11li <= '0'; + nli1l11ll <= '0'; + nli1l11lO <= '0'; + nli1l11Oi <= '0'; + nli1l11Ol <= '0'; + nli1l1l0O <= '0'; + nli1l1lii <= '0'; + nli1l1lil <= '0'; + nli1l1liO <= '0'; + nli1l1lli <= '0'; + nli1l1lll <= '0'; + nli1l1llO <= '0'; + nli1l1lOi <= '0'; + nli1l1lOl <= '0'; + nli1l1lOO <= '0'; + nli1l1O0i <= '0'; + nli1l1O0l <= '0'; + nli1l1O0O <= '0'; + nli1l1O1i <= '0'; + nli1l1O1l <= '0'; + nli1l1O1O <= '0'; + nli1l1Oii <= '0'; + nli1l1Oil <= '0'; + nli1l1OiO <= '0'; + nli1l1Oli <= '0'; + nli1l1Oll <= '0'; + nli1lilli <= '0'; + nli1liO1O <= '0'; + nli1ll1ii <= '0'; + nli1ll1il <= '0'; + nli1ll1iO <= '0'; + nli1lliOO <= '0'; + nli1llOiO <= '0'; + nli1llOli <= '0'; + nli1llOll <= '0'; + nli1llOlO <= '0'; + nli1llOOi <= '0'; + nli1llOOl <= '0'; + nli1llOOO <= '0'; + nli1lO00i <= '0'; + nli1lO00l <= '0'; + nli1lO00O <= '0'; + nli1lO01i <= '0'; + nli1lO01l <= '0'; + nli1lO01O <= '0'; + nli1lO0ii <= '0'; + nli1lO0il <= '0'; + nli1lO0iO <= '0'; + nli1lO10i <= '0'; + nli1lO10l <= '0'; + nli1lO10O <= '0'; + nli1lO11i <= '0'; + nli1lO11l <= '0'; + nli1lO11O <= '0'; + nli1lO1ii <= '0'; + nli1lO1il <= '0'; + nli1lO1iO <= '0'; + nli1lO1li <= '0'; + nli1lO1ll <= '0'; + nli1lO1lO <= '0'; + nli1lO1Oi <= '0'; + nli1lO1Ol <= '0'; + nli1lO1OO <= '0'; + nlii10Oii <= '0'; + nlii10Oil <= '0'; + nlii10OiO <= '0'; + nlii10Oli <= '0'; + nlii10Oll <= '0'; + nlii10OlO <= '0'; + nlii10OOi <= '0'; + nlii10OOl <= '0'; + nlii10OOO <= '0'; + nlii1100i <= '0'; + nlii1100l <= '0'; + nlii1100O <= '0'; + nlii1101i <= '0'; + nlii1101l <= '0'; + nlii1101O <= '0'; + nlii110ii <= '0'; + nlii110il <= '0'; + nlii110iO <= '0'; + nlii110li <= '0'; + nlii110ll <= '0'; + nlii110lO <= '0'; + nlii110Oi <= '0'; + nlii110Ol <= '0'; + nlii110OO <= '0'; + nlii1110i <= '0'; + nlii1110l <= '0'; + nlii1110O <= '0'; + nlii1111i <= '0'; + nlii1111l <= '0'; + nlii1111O <= '0'; + nlii111ii <= '0'; + nlii111il <= '0'; + nlii111iO <= '0'; + nlii111li <= '0'; + nlii111ll <= '0'; + nlii111lO <= '0'; + nlii111Oi <= '0'; + nlii111Ol <= '0'; + nlii111OO <= '0'; + nlii11i0i <= '0'; + nlii11i0l <= '0'; + nlii11i0O <= '0'; + nlii11i1i <= '0'; + nlii11i1l <= '0'; + nlii11i1O <= '0'; + nlii11iii <= '0'; + nlii1i10i <= '0'; + nlii1i10l <= '0'; + nlii1i10O <= '0'; + nlii1i11i <= '0'; + nlii1i11l <= '0'; + nlii1i11O <= '0'; + nlii1i1ii <= '0'; + nlii1i1il <= '0'; + nlii1i1iO <= '0'; + nlii1i1li <= '0'; + nlii1illi <= '0'; + nlii1illl <= '0'; + nlii1illO <= '0'; + nlii1ilOi <= '0'; + nlii1ilOl <= '0'; + nlii1ilOO <= '0'; + nlii1iO0i <= '0'; + nlii1iO0l <= '0'; + nlii1iO0O <= '0'; + nlii1iO1i <= '0'; + nlii1iO1l <= '0'; + nlii1iO1O <= '0'; + nlii1iOii <= '0'; + nlii1iOil <= '0'; + nlii1iOiO <= '0'; + nlii1iOli <= '0'; + nlii1iOll <= '0'; + nlii1iOlO <= '0'; + nlii1iOOi <= '0'; + nlii1iOOl <= '0'; + nlii1iOOO <= '0'; + nlii1l10i <= '0'; + nlii1l10l <= '0'; + nlii1l10O <= '0'; + nlii1l11i <= '0'; + nlii1l11l <= '0'; + nlii1l11O <= '0'; + nlii1l1ii <= '0'; + nlii1l1il <= '0'; + nlii1l1iO <= '0'; + nlii1l1li <= '0'; + nliii000i <= '0'; + nliii0lOO <= '0'; + nliii0O1i <= '0'; + nliiOOiii <= '0'; + nliiOOiil <= '0'; + nliiOOiiO <= '0'; + nliiOOili <= '0'; + nliiOOill <= '0'; + nliiOOilO <= '0'; + nlil000Oi <= '0'; + nlil000Ol <= '0'; + nlil000OO <= '0'; + nlil00i0i <= '0'; + nlil00i0l <= '0'; + nlil00i0O <= '0'; + nlil00i1i <= '0'; + nlil00i1l <= '0'; + nlil00i1O <= '0'; + nlil00iii <= '0'; + nlil00iil <= '0'; + nlil00iiO <= '0'; + nlil00ili <= '0'; + nlil00ill <= '0'; + nlil0100i <= '0'; + nlil0100l <= '0'; + nlil0100O <= '0'; + nlil0101l <= '0'; + nlil0101O <= '0'; + nlil010ii <= '0'; + nlil010il <= '0'; + nlil010iO <= '0'; + nlil010li <= '0'; + nlil010ll <= '0'; + nlil010lO <= '0'; + nlil010Oi <= '0'; + nlil010Ol <= '0'; + nlil010OO <= '0'; + nlil01i0i <= '0'; + nlil01i0l <= '0'; + nlil01i1i <= '0'; + nlil01i1l <= '0'; + nlil01i1O <= '0'; + nlil1100i <= '0'; + nlil1100l <= '0'; + nlil1100O <= '0'; + nlil1101O <= '0'; + nlil110ii <= '0'; + nlil111Oi <= '0'; + nlil11l0i <= '0'; + nlil11lll <= '0'; + nlil11llO <= '0'; + nlil11lOi <= '0'; + nlil11lOl <= '0'; + nlil11lOO <= '0'; + nlil11O0i <= '0'; + nlil11O0l <= '0'; + nlil11O0O <= '0'; + nlil11O1i <= '0'; + nlil11O1l <= '0'; + nlil11O1O <= '0'; + nlil11Oii <= '0'; + nlil11Oil <= '0'; + nlil11OiO <= '0'; + nlil1i00i <= '0'; + nlil1i00l <= '0'; + nlil1i01i <= '0'; + nlil1i01l <= '0'; + nlil1i01O <= '0'; + nlil1i1OO <= '0'; + nlil1llOi <= '0'; + nlil1llOl <= '0'; + nlil1llOO <= '0'; + nlil1lO0i <= '0'; + nlil1lO0l <= '0'; + nlil1lO0O <= '0'; + nlil1lO1i <= '0'; + nlil1lO1l <= '0'; + nlil1lO1O <= '0'; + nlil1lOii <= '0'; + nlil1lOil <= '0'; + nlil1lOiO <= '0'; + nlil1lOli <= '0'; + nlil1OOiO <= '0'; + nlil1OOli <= '0'; + nlil1OOll <= '0'; + nlil1OOlO <= '0'; + nlilill1O <= '0'; + nlilillil <= '0'; + nlililliO <= '0'; + nlililOii <= '0'; + nlililOil <= '0'; + nlililOiO <= '0'; + nlililOli <= '0'; + nliliO10O <= '0'; + nliliO11i <= '0'; + nliliO11l <= '0'; + nliliO11O <= '0'; + nliliO1ii <= '0'; + nliliO1il <= '0'; + nliliO1iO <= '0'; + nliliO1li <= '0'; + nlill0lll <= '0'; + nlill0OlO <= '0'; + nlill1i0O <= '0'; + nlill1l0O <= '0'; + nlill1lii <= '0'; + nlill1lil <= '0'; + nlill1liO <= '0'; + nlill1lli <= '0'; + ELSIF (wire_niO0011O_dataout = '1' AND wire_niO0011O_dataout'event) THEN + nl00l0O0i <= wire_nl00lllli_dataout; + nl00l0O0l <= wire_nl00lllll_dataout; + nl00l0O0O <= wire_nl00llllO_dataout; + nl00l0Oii <= wire_nl00lllOi_dataout; + nl00l0Oil <= wire_nl00lllOl_dataout; + nl00l0OiO <= wire_nl00lllOO_dataout; + nl00l0Oli <= wire_nl00llO1i_dataout; + nl00l0Oll <= wire_nl00llO1l_dataout; + nl00l0OlO <= wire_nl00llO1O_dataout; + nl00l0OOi <= wire_nl00llO0i_dataout; + nl00l0OOl <= wire_nl00llO0l_dataout; + nl00l0OOO <= wire_nl00llO0O_dataout; + nl00l11il <= wire_nl00l11ll_dataout; + nl00l11iO <= wire_nl00l11lO_dataout; + nl00li00i <= wire_nl00lO1li_dataout; + nl00li00l <= wire_nl00lO1ll_dataout; + nl00li00O <= wire_nl00lO1lO_dataout; + nl00li01i <= wire_nl00lO1ii_dataout; + nl00li01l <= wire_nl00lO1il_dataout; + nl00li01O <= wire_nl00lO1iO_dataout; + nl00li0ii <= wire_nl00lO1Oi_dataout; + nl00li0il <= wire_nl00llliO_dataout; + nl00li0iO <= wire_nl00lO1Ol_dataout; + nl00li0li <= wire_nl00lO1OO_dataout; + nl00li0ll <= wire_nl00lO01i_dataout; + nl00li0lO <= wire_nl00lO01l_dataout; + nl00li0Oi <= wire_nl00lO01O_dataout; + nl00li0Ol <= wire_nl00lO00i_dataout; + nl00li0OO <= wire_nl00lO00l_dataout; + nl00li10i <= wire_nl00llOli_dataout; + nl00li10l <= wire_nl00llOll_dataout; + nl00li10O <= wire_nl00llOlO_dataout; + nl00li11i <= wire_nl00llOii_dataout; + nl00li11l <= wire_nl00llOil_dataout; + nl00li11O <= wire_nl00llOiO_dataout; + nl00li1ii <= wire_nl00llOOi_dataout; + nl00li1il <= wire_nl00llOOl_dataout; + nl00li1iO <= wire_nl00llOOO_dataout; + nl00li1li <= wire_nl00lO11i_dataout; + nl00li1ll <= wire_nl00lO11l_dataout; + nl00li1lO <= wire_nl00lO11O_dataout; + nl00li1Oi <= wire_nl00lO10i_dataout; + nl00li1Ol <= wire_nl00lO10l_dataout; + nl00li1OO <= wire_nl00lO10O_dataout; + nl00lii0i <= wire_nl00lO0iO_dataout; + nl00lii0l <= wire_nl00lO0li_dataout; + nl00lii0O <= wire_nl00lO0ll_dataout; + nl00lii1i <= wire_nl00lO00O_dataout; + nl00lii1l <= wire_nl00lO0ii_dataout; + nl00lii1O <= wire_nl00lO0il_dataout; + nl00liiii <= wire_nl00lO0lO_dataout; + nl00liiil <= wire_nl00lO0Oi_dataout; + nl00liiiO <= wire_nl00lO0Ol_dataout; + nl00liili <= wire_nl00lO0OO_dataout; + nl00liill <= wire_nl00lOi1i_dataout; + nl00liilO <= wire_nl00lOi1l_dataout; + nl00liiOi <= wire_nl00lOi1O_dataout; + nl00liiOl <= wire_nl00lOi0i_dataout; + nl00liiOO <= wire_nl00lOi0l_dataout; + nl00lil0i <= wire_nl00lOiiO_dataout; + nl00lil0l <= wire_nl00lOili_dataout; + nl00lil0O <= wire_nl00lOill_dataout; + nl00lil1i <= wire_nl00lOi0O_dataout; + nl00lil1l <= wire_nl00lOiii_dataout; + nl00lil1O <= wire_nl00lOiil_dataout; + nl00lilii <= wire_nl00lOilO_dataout; + nl00lilil <= wire_nl00lOiOi_dataout; + nl00liliO <= wire_nl00lOiOl_dataout; + nl00lilli <= wire_nl00lOiOO_dataout; + nl00lilll <= wire_nl00lOl1i_dataout; + nl00lillO <= wire_nl00lOl1l_dataout; + nl00lilOi <= wire_nl00lOl1O_dataout; + nl00lilOl <= wire_nl00lOl0i_dataout; + nl00lilOO <= wire_nl00lOl0l_dataout; + nl00liO0i <= wire_nl00lOliO_dataout; + nl00liO0l <= wire_nl00lOlli_dataout; + nl00liO0O <= wire_nl00lOlll_dataout; + nl00liO1i <= wire_nl00lOl0O_dataout; + nl00liO1l <= wire_nl00lOlii_dataout; + nl00liO1O <= wire_nl00lOlil_dataout; + nl00liOii <= wire_nl00lOllO_dataout; + nl00liOil <= wire_nl00lOlOi_dataout; + nl00liOiO <= wire_nl00lOlOl_dataout; + nl00liOli <= wire_nl00lOlOO_dataout; + nl00liOll <= wire_nl00lOO1i_dataout; + nl00liOlO <= wire_nl00lOO1l_dataout; + nl00liOOi <= wire_nl00lOO1O_dataout; + nl00liOOl <= wire_nl00lOO0i_dataout; + nl00liOOO <= wire_nl00lOO0l_dataout; + nl00ll00i <= wire_nl00O11iO_dataout; + nl00ll00l <= wire_nl00O11li_dataout; + nl00ll00O <= wire_nl00O11ll_dataout; + nl00ll01i <= wire_nl00O110O_dataout; + nl00ll01l <= wire_nl00O11ii_dataout; + nl00ll01O <= wire_nl00O11il_dataout; + nl00ll0ii <= wire_nl00O11lO_dataout; + nl00ll0il <= wire_nl00O11Oi_dataout; + nl00ll0iO <= wire_nl00O11Ol_dataout; + nl00ll0li <= wire_nl00O11OO_dataout; + nl00ll0ll <= wire_nl00O101i_dataout; + nl00ll0lO <= wire_nl00O101l_dataout; + nl00ll0Oi <= wire_nl00O101O_dataout; + nl00ll0Ol <= wire_nl00O100i_dataout; + nl00ll0OO <= wire_nl00O100l_dataout; + nl00ll10i <= wire_nl00lOOiO_dataout; + nl00ll10l <= wire_nl00lOOli_dataout; + nl00ll10O <= wire_nl00lOOll_dataout; + nl00ll11i <= wire_nl00lOO0O_dataout; + nl00ll11l <= wire_nl00lOOii_dataout; + nl00ll11O <= wire_nl00lOOil_dataout; + nl00ll1ii <= wire_nl00lOOlO_dataout; + nl00ll1il <= wire_nl00lOOOi_dataout; + nl00ll1iO <= wire_nl00lOOOl_dataout; + nl00ll1li <= wire_nl00lOOOO_dataout; + nl00ll1ll <= wire_nl00O111i_dataout; + nl00ll1lO <= wire_nl00O111l_dataout; + nl00ll1Oi <= wire_nl00O111O_dataout; + nl00ll1Ol <= wire_nl00O110i_dataout; + nl00ll1OO <= wire_nl00O110l_dataout; + nl00lli0i <= wire_nl00O10iO_dataout; + nl00lli0l <= wire_nl00O10li_dataout; + nl00lli0O <= wire_nl00O10ll_dataout; + nl00lli1i <= wire_nl00O100O_dataout; + nl00lli1l <= wire_nl00O10ii_dataout; + nl00lli1O <= wire_nl00O10il_dataout; + nl00lliii <= wire_nl00O10lO_dataout; + nl00lliil <= wire_nl00O10Oi_dataout; + nl00lliiO <= wire_nl00O10Ol_dataout; + nl00llili <= wire_nl00O10OO_dataout; + nl00llill <= wire_nl00O1i1i_dataout; + nl00llilO <= wire_nl00O1i1l_dataout; + nl00lliOi <= wire_nl00O1i1O_dataout; + nl00lliOl <= wire_nl00O1i0i_dataout; + nl00lliOO <= wire_nl00O1i0l_dataout; + nl00lll0i <= wire_nl00O1iiO_dataout; + nl00lll0l <= wire_nl00O1ili_dataout; + nl00lll0O <= wire_nl00O1ill_dataout; + nl00lll1i <= wire_nl00O1i0O_dataout; + nl00lll1l <= wire_nl00O1iii_dataout; + nl00lll1O <= wire_nl00O1iil_dataout; + nl00lllii <= wire_nl00O1ilO_dataout; + nl00lllil <= wire_nl0i1lili_dataout; + nl010000i <= wire_nl010i0Oi_dataout; + nl010000l <= wire_nl010i0Ol_dataout; + nl010000O <= wire_nl010i0OO_dataout; + nl010001i <= wire_nl010i0li_dataout; + nl010001l <= wire_nl010i0ll_dataout; + nl010001O <= wire_nl010i0lO_dataout; + nl01000ii <= wire_nl010ii1i_dataout; + nl01000il <= wire_nl010ii1l_dataout; + nl01000iO <= wire_nl010ii1O_dataout; + nl01000li <= wire_nl010ii0i_dataout; + nl01000ll <= wire_nl010ii0l_dataout; + nl01000lO <= wire_nl010ii0O_dataout; + nl01000Oi <= wire_nl010iiii_dataout; + nl01000Ol <= wire_nl010iiil_dataout; + nl01000OO <= wire_nl010iiiO_dataout; + nl010010i <= wire_nl010i1Oi_dataout; + nl010010l <= wire_nl010i1Ol_dataout; + nl010010O <= wire_nl010i1OO_dataout; + nl010011i <= wire_nl010i1li_dataout; + nl010011l <= wire_nl010i1ll_dataout; + nl010011O <= wire_nl010i1lO_dataout; + nl01001ii <= wire_nl010i01i_dataout; + nl01001il <= wire_nl010i01l_dataout; + nl01001iO <= wire_nl010i01O_dataout; + nl01001li <= wire_nl010i00i_dataout; + nl01001ll <= wire_nl010i00l_dataout; + nl01001lO <= wire_nl010i00O_dataout; + nl01001Oi <= wire_nl010i0ii_dataout; + nl01001Ol <= wire_nl010i0il_dataout; + nl01001OO <= wire_nl010i0iO_dataout; + nl0100i0i <= wire_nl010iiOi_dataout; + nl0100i0l <= wire_nl010iiOl_dataout; + nl0100i0O <= wire_nl010iiOO_dataout; + nl0100i1i <= wire_nl010iili_dataout; + nl0100i1l <= wire_nl010iill_dataout; + nl0100i1O <= wire_nl010iilO_dataout; + nl0100iii <= wire_nl010il1i_dataout; + nl0100iil <= wire_nl010il1l_dataout; + nl0100iiO <= wire_nl010il1O_dataout; + nl0100ili <= wire_nl010il0i_dataout; + nl0100ill <= wire_nl010il0l_dataout; + nl0100ilO <= wire_nl010il0O_dataout; + nl0100iOi <= wire_nl010ilii_dataout; + nl0100iOl <= wire_nl010ilil_dataout; + nl0100iOO <= wire_nl010iliO_dataout; + nl0100l0i <= wire_nl010ilOi_dataout; + nl0100l0l <= wire_nl010ilOl_dataout; + nl0100l0O <= wire_nl010ilOO_dataout; + nl0100l1i <= wire_nl010illi_dataout; + nl0100l1l <= wire_nl010illl_dataout; + nl0100l1O <= wire_nl010illO_dataout; + nl0100lii <= wire_nl010iO1i_dataout; + nl0100lil <= wire_nl010iO1l_dataout; + nl0100liO <= wire_nl010iO1O_dataout; + nl0100lli <= wire_nl010iO0i_dataout; + nl0100lll <= wire_nl010iO0l_dataout; + nl0100llO <= wire_nl010iO0O_dataout; + nl0100lOi <= wire_nl010iOii_dataout; + nl0100lOl <= wire_nl010iOil_dataout; + nl0100lOO <= wire_nl010iOiO_dataout; + nl0100O0i <= wire_nl010iOOi_dataout; + nl0100O0l <= wire_nl010iOOl_dataout; + nl0100O0O <= wire_nl010iOOO_dataout; + nl0100O1i <= wire_nl010iOli_dataout; + nl0100O1l <= wire_nl010iOll_dataout; + nl0100O1O <= wire_nl010iOlO_dataout; + nl0101lOl <= wire_nl0100Oil_dataout; + nl0101lOO <= wire_nl0100OiO_dataout; + nl0101O0i <= wire_nl0100OOi_dataout; + nl0101O0l <= wire_nl0100OOl_dataout; + nl0101O0O <= wire_nl0100OOO_dataout; + nl0101O1i <= wire_nl0100Oli_dataout; + nl0101O1l <= wire_nl0100Oll_dataout; + nl0101O1O <= wire_nl0100OlO_dataout; + nl0101Oii <= wire_nl010i11i_dataout; + nl0101Oil <= wire_nl010i11l_dataout; + nl0101OiO <= wire_nl010i11O_dataout; + nl0101Oli <= wire_nl010i10i_dataout; + nl0101Oll <= wire_nl010i10l_dataout; + nl0101OlO <= wire_nl010i10O_dataout; + nl0101OOi <= wire_nl010i1ii_dataout; + nl0101OOl <= wire_nl010i1il_dataout; + nl0101OOO <= wire_nl010i1iO_dataout; + nl010Olil <= wire_nl010OO1l_dataout; + nl010OliO <= wire_nl010OO1O_dataout; + nl010Olli <= wire_nl010OO0i_dataout; + nl010Olll <= wire_nl010OO0l_dataout; + nl010OllO <= wire_nl010OO0O_dataout; + nl010OlOi <= wire_nl010OOii_dataout; + nl010OlOl <= wire_nl010OOil_dataout; + nl010OlOO <= wire_nl010OOiO_dataout; + nl0111iil <= wire_nl0111OOl_dataout; + nl0111iiO <= wire_nl0111OOO_dataout; + nl0111ili <= wire_nl011011i_dataout; + nl0111ill <= wire_nl011011l_dataout; + nl0111ilO <= wire_nl011011O_dataout; + nl0111iOi <= wire_nl011010i_dataout; + nl0111iOl <= wire_nl011010l_dataout; + nl0111iOO <= wire_nl011010O_dataout; + nl0111l0i <= wire_nl01101li_dataout; + nl0111l0l <= wire_nl01101ll_dataout; + nl0111l0O <= wire_nl01101lO_dataout; + nl0111l1i <= wire_nl01101ii_dataout; + nl0111l1l <= wire_nl01101il_dataout; + nl0111l1O <= wire_nl01101iO_dataout; + nl0111lii <= wire_nl01101Oi_dataout; + nl0111lil <= wire_nl01101Ol_dataout; + nl0111liO <= wire_nl01101OO_dataout; + nl0111lli <= wire_nl011001i_dataout; + nl0111lll <= wire_nl011001l_dataout; + nl0111llO <= wire_nl011001O_dataout; + nl0111lOi <= wire_nl011000i_dataout; + nl0111lOl <= wire_nl011000l_dataout; + nl0111lOO <= wire_nl011000O_dataout; + nl0111O0i <= wire_nl01100li_dataout; + nl0111O0l <= wire_nl01100ll_dataout; + nl0111O0O <= wire_nl01100lO_dataout; + nl0111O1i <= wire_nl01100ii_dataout; + nl0111O1l <= wire_nl01100il_dataout; + nl0111O1O <= wire_nl01100iO_dataout; + nl0111Oii <= wire_nl01100Oi_dataout; + nl0111Oil <= wire_nl01100Ol_dataout; + nl0111OiO <= wire_nl01100OO_dataout; + nl0111Oli <= wire_nl0110i1i_dataout; + nl0111Oll <= wire_nl0110i1l_dataout; + nl0111OlO <= wire_nl0110i1O_dataout; + nl011ilOl <= wire_nl011l1iO_dataout; + nl011l0iO <= wire_nl011ll0O_dataout; + nl011l0li <= wire_nl011llii_dataout; + nl011l0ll <= wire_nl011llil_dataout; + nl011l0lO <= wire_nl011lliO_dataout; + nl011l0Oi <= wire_nl011llli_dataout; + nl011l0Ol <= wire_nl011llll_dataout; + nl011l0OO <= wire_nl011lllO_dataout; + nl011l1ii <= wire_nl011l1li_dataout; + nl011l1il <= wire_nl011ll0l_dataout; + nl011li0i <= wire_nl011lO1i_dataout; + nl011li0l <= wire_nl011lO1l_dataout; + nl011li0O <= wire_nl011lO1O_dataout; + nl011li1i <= wire_nl011llOi_dataout; + nl011li1l <= wire_nl011llOl_dataout; + nl011li1O <= wire_nl011llOO_dataout; + nl011liii <= wire_nl011lO0i_dataout; + nl011liil <= wire_nl011lO0l_dataout; + nl011liiO <= wire_nl011lO0O_dataout; + nl011lili <= wire_nl011lOii_dataout; + nl011lill <= wire_nl011lOil_dataout; + nl011lilO <= wire_nl011lOiO_dataout; + nl011liOi <= wire_nl011lOli_dataout; + nl011liOl <= wire_nl011lOll_dataout; + nl011liOO <= wire_nl011lOlO_dataout; + nl011ll0i <= wire_nl011OO0i_dataout; + nl011ll1i <= wire_nl011lOOi_dataout; + nl011ll1l <= wire_nl011lOOl_dataout; + nl011ll1O <= wire_nl011lOOO_dataout; + nl011OO1l <= wire_nl011OO0l_dataout; + nl011OO1O <= wire_nl011OO0O_dataout; + nl011OOlO <= wire_nl0100Oii_dataout; + nl01i0O0O <= wire_nl01ii01l_dataout; + nl01i0O1i <= wire_nl01ii01i_dataout; + nl01i0Oii <= wire_nl01ii01O_dataout; + nl01i0Oil <= wire_nl01ii00i_dataout; + nl01i0OiO <= wire_nl01ii00l_dataout; + nl01i0Oli <= wire_nl01ii00O_dataout; + nl01i0Oll <= wire_nl01ii0ii_dataout; + nl01i0OlO <= wire_nl01ii0il_dataout; + nl01i0OOi <= wire_nl01ii0iO_dataout; + nl01i0OOl <= wire_nl01ii0li_dataout; + nl01i0OOO <= wire_nl01ii0ll_dataout; + nl01ii10i <= wire_nl01ii0OO_dataout; + nl01ii10l <= wire_nl01iii1i_dataout; + nl01ii10O <= wire_nl01iii1l_dataout; + nl01ii11i <= wire_nl01ii0lO_dataout; + nl01ii11l <= wire_nl01ii0Oi_dataout; + nl01ii11O <= wire_nl01ii0Ol_dataout; + nl01ii1ii <= wire_nl01iii1O_dataout; + nl01ii1il <= wire_nl01iii0i_dataout; + nl01ii1iO <= wire_nl01iii0l_dataout; + nl01ii1li <= wire_nl01iii0O_dataout; + nl01ii1ll <= wire_nl01iiiii_dataout; + nl01ii1lO <= wire_nl01iiiil_dataout; + nl01ii1Oi <= wire_nl01iiiiO_dataout; + nl01ii1Ol <= wire_nl01iiili_dataout; + nl01ii1OO <= wire_nl01l1liO_dataout; + nl01l000i <= wire_nl01l0OOl_dataout; + nl01l000l <= wire_nl01l0OOO_dataout; + nl01l000O <= wire_nl01li11i_dataout; + nl01l001i <= wire_nl01l0Oll_dataout; + nl01l001l <= wire_nl01l0OlO_dataout; + nl01l001O <= wire_nl01l0OOi_dataout; + nl01l00ii <= wire_nl01li11l_dataout; + nl01l00il <= wire_nl01li11O_dataout; + nl01l00iO <= wire_nl01li10i_dataout; + nl01l00li <= wire_nl01li10l_dataout; + nl01l00ll <= wire_nl01li10O_dataout; + nl01l00lO <= wire_nl01li1ii_dataout; + nl01l00Oi <= wire_nl01li1il_dataout; + nl01l00Ol <= wire_nl01li1iO_dataout; + nl01l00OO <= wire_nl01li1li_dataout; + nl01l01ll <= wire_nl01l0O0O_dataout; + nl01l01lO <= wire_nl01l0Oii_dataout; + nl01l01Oi <= wire_nl01l0Oil_dataout; + nl01l01Ol <= wire_nl01l0OiO_dataout; + nl01l01OO <= wire_nl01l0Oli_dataout; + nl01l0i0i <= wire_nl01li1Ol_dataout; + nl01l0i0l <= wire_nl01li1OO_dataout; + nl01l0i0O <= wire_nl01li01i_dataout; + nl01l0i1i <= wire_nl01li1ll_dataout; + nl01l0i1l <= wire_nl01li1lO_dataout; + nl01l0i1O <= wire_nl01li1Oi_dataout; + nl01l0iii <= wire_nl01li01l_dataout; + nl01l0iil <= wire_nl01li01O_dataout; + nl01l0iiO <= wire_nl01li00i_dataout; + nl01l0ili <= wire_nl01li00l_dataout; + nl01l0ill <= wire_nl01li00O_dataout; + nl01l0ilO <= wire_nl01li0ii_dataout; + nl01l0iOi <= wire_nl01li0il_dataout; + nl01l0iOl <= wire_nl01li0iO_dataout; + nl01l0iOO <= wire_nl01li0li_dataout; + nl01l0l0i <= wire_nl01li0Ol_dataout; + nl01l0l0l <= wire_nl01li0OO_dataout; + nl01l0l0O <= wire_nl01l0O0l_dataout; + nl01l0l1i <= wire_nl01li0ll_dataout; + nl01l0l1l <= wire_nl01li0lO_dataout; + nl01l0l1O <= wire_nl01li0Oi_dataout; + nl01l0lii <= wire_nl01lii1i_dataout; + nl01l0lil <= wire_nl01lii1l_dataout; + nl01l0liO <= wire_nl01lii1O_dataout; + nl01l0lli <= wire_nl01lii0i_dataout; + nl01l0lll <= wire_nl01lii0l_dataout; + nl01l0llO <= wire_nl01lii0O_dataout; + nl01l0lOi <= wire_nl01liiii_dataout; + nl01l0lOl <= wire_nl01liiil_dataout; + nl01l0lOO <= wire_nl01liiiO_dataout; + nl01l0O0i <= wire_nl01llO1i_dataout; + nl01l0O1i <= wire_nl01liili_dataout; + nl01l0O1l <= wire_nl01liill_dataout; + nl01l0O1O <= wire_nl01liilO_dataout; + nl01lll0i <= wire_nl01llO0l_dataout; + nl01lll0l <= wire_nl01llO0O_dataout; + nl01lll0O <= wire_nl01llOii_dataout; + nl01lll1i <= wire_nl01llO1l_dataout; + nl01lll1l <= wire_nl01llO1O_dataout; + nl01lll1O <= wire_nl01llO0i_dataout; + nl01lllii <= wire_nl01llOil_dataout; + nl01lllil <= wire_nl01llOiO_dataout; + nl01llliO <= wire_nl01llOli_dataout; + nl01lllli <= wire_nl01llOll_dataout; + nl01lllll <= wire_nl01llOlO_dataout; + nl01llllO <= wire_nl01llOOi_dataout; + nl01lllOi <= wire_nl01llOOl_dataout; + nl01lllOl <= wire_nl01llOOO_dataout; + nl01lllOO <= wire_nl01lO11i_dataout; + nl01lO0iO <= wire_nl01O011O_dataout; + nl01lO0li <= wire_nl01O010i_dataout; + nl01lO0ll <= wire_nl01O010l_dataout; + nl01lO0lO <= wire_nl01O010O_dataout; + nl01lO0Oi <= wire_nl01O01ii_dataout; + nl01lO0Ol <= wire_nl01O01il_dataout; + nl01lO0OO <= wire_nl01O01iO_dataout; + nl01lOi0i <= wire_nl01O01Oi_dataout; + nl01lOi0l <= wire_nl01O01Ol_dataout; + nl01lOi0O <= wire_nl01O01OO_dataout; + nl01lOi1i <= wire_nl01O01li_dataout; + nl01lOi1l <= wire_nl01O01ll_dataout; + nl01lOi1O <= wire_nl01O01lO_dataout; + nl01lOiii <= wire_nl01O001i_dataout; + nl01lOiil <= wire_nl01O001l_dataout; + nl01lOiiO <= wire_nl01O001O_dataout; + nl01lOili <= wire_nl01O000i_dataout; + nl01lOill <= wire_nl01O000l_dataout; + nl01lOilO <= wire_nl01O000O_dataout; + nl01lOiOi <= wire_nl01O00ii_dataout; + nl01lOiOl <= wire_nl01O00il_dataout; + nl01lOiOO <= wire_nl01O00iO_dataout; + nl01lOl0i <= wire_nl01O00Oi_dataout; + nl01lOl0l <= wire_nl01O00Ol_dataout; + nl01lOl0O <= wire_nl01O00OO_dataout; + nl01lOl1i <= wire_nl01O00li_dataout; + nl01lOl1l <= wire_nl01O00ll_dataout; + nl01lOl1O <= wire_nl01O00lO_dataout; + nl01lOlii <= wire_nl01O0i1i_dataout; + nl01lOlil <= wire_nl01O0i1l_dataout; + nl01lOliO <= wire_nl01O0i1O_dataout; + nl01lOlli <= wire_nl01O0i0i_dataout; + nl01lOlll <= wire_nl01O0i0l_dataout; + nl01lOllO <= wire_nl01O0i0O_dataout; + nl01lOlOi <= wire_nl01O0iii_dataout; + nl01lOlOl <= wire_nl01O0iil_dataout; + nl01lOlOO <= wire_nl01O0iiO_dataout; + nl01lOO0i <= wire_nl01O0iOi_dataout; + nl01lOO0l <= wire_nl01O0iOl_dataout; + nl01lOO0O <= wire_nl01O0iOO_dataout; + nl01lOO1i <= wire_nl01O0ili_dataout; + nl01lOO1l <= wire_nl01O0ill_dataout; + nl01lOO1O <= wire_nl01O0ilO_dataout; + nl01lOOii <= wire_nl01O0l1i_dataout; + nl01lOOil <= wire_nl01O0l1l_dataout; + nl01lOOiO <= wire_nl01O0l1O_dataout; + nl01lOOli <= wire_nl01O0l0i_dataout; + nl01lOOll <= wire_nl01O0l0l_dataout; + nl01lOOlO <= wire_nl01O0l0O_dataout; + nl01lOOOi <= wire_nl01O0lii_dataout; + nl01lOOOl <= wire_nl01O0lil_dataout; + nl01lOOOO <= wire_nl01O0liO_dataout; + nl01O011i <= wire_nl01Oilli_dataout; + nl01O011l <= wire_nl00l11li_dataout; + nl01O100i <= wire_nl01O0OOi_dataout; + nl01O100l <= wire_nl01O0OOl_dataout; + nl01O100O <= wire_nl01O0OOO_dataout; + nl01O101i <= wire_nl01O0Oli_dataout; + nl01O101l <= wire_nl01O0Oll_dataout; + nl01O101O <= wire_nl01O0OlO_dataout; + nl01O10ii <= wire_nl01Oi11i_dataout; + nl01O10il <= wire_nl01Oi11l_dataout; + nl01O10iO <= wire_nl01Oi11O_dataout; + nl01O10li <= wire_nl01Oi10i_dataout; + nl01O10ll <= wire_nl01Oi10l_dataout; + nl01O10lO <= wire_nl01Oi10O_dataout; + nl01O10Oi <= wire_nl01Oi1ii_dataout; + nl01O10Ol <= wire_nl01Oi1il_dataout; + nl01O10OO <= wire_nl01Oi1iO_dataout; + nl01O110i <= wire_nl01O0lOi_dataout; + nl01O110l <= wire_nl01O0lOl_dataout; + nl01O110O <= wire_nl01O0lOO_dataout; + nl01O111i <= wire_nl01O0lli_dataout; + nl01O111l <= wire_nl01O0lll_dataout; + nl01O111O <= wire_nl01O0llO_dataout; + nl01O11ii <= wire_nl01O0O1i_dataout; + nl01O11il <= wire_nl01O0O1l_dataout; + nl01O11iO <= wire_nl01O0O1O_dataout; + nl01O11li <= wire_nl01O0O0i_dataout; + nl01O11ll <= wire_nl01O0O0l_dataout; + nl01O11lO <= wire_nl01O0O0O_dataout; + nl01O11Oi <= wire_nl01O0Oii_dataout; + nl01O11Ol <= wire_nl01O0Oil_dataout; + nl01O11OO <= wire_nl01O0OiO_dataout; + nl01O1i0i <= wire_nl01Oi1Oi_dataout; + nl01O1i0l <= wire_nl01Oi1Ol_dataout; + nl01O1i0O <= wire_nl01Oi1OO_dataout; + nl01O1i1i <= wire_nl01Oi1li_dataout; + nl01O1i1l <= wire_nl01Oi1ll_dataout; + nl01O1i1O <= wire_nl01Oi1lO_dataout; + nl01O1iii <= wire_nl01Oi01i_dataout; + nl01O1iil <= wire_nl01Oi01l_dataout; + nl01O1iiO <= wire_nl01Oi01O_dataout; + nl01O1ili <= wire_nl01Oi00i_dataout; + nl01O1ill <= wire_nl01Oi00l_dataout; + nl01O1ilO <= wire_nl01Oi00O_dataout; + nl01O1iOi <= wire_nl01Oi0ii_dataout; + nl01O1iOl <= wire_nl01Oi0il_dataout; + nl01O1iOO <= wire_nl01Oi0iO_dataout; + nl01O1l0i <= wire_nl01Oi0Oi_dataout; + nl01O1l0l <= wire_nl01Oi0Ol_dataout; + nl01O1l0O <= wire_nl01Oi0OO_dataout; + nl01O1l1i <= wire_nl01Oi0li_dataout; + nl01O1l1l <= wire_nl01Oi0ll_dataout; + nl01O1l1O <= wire_nl01Oi0lO_dataout; + nl01O1lii <= wire_nl01Oii1i_dataout; + nl01O1lil <= wire_nl01Oii1l_dataout; + nl01O1liO <= wire_nl01Oii1O_dataout; + nl01O1lli <= wire_nl01Oii0i_dataout; + nl01O1lll <= wire_nl01Oii0l_dataout; + nl01O1llO <= wire_nl01Oii0O_dataout; + nl01O1lOi <= wire_nl01Oiiii_dataout; + nl01O1lOl <= wire_nl01Oiiil_dataout; + nl01O1lOO <= wire_nl01OiiiO_dataout; + nl01O1O0i <= wire_nl01OiiOi_dataout; + nl01O1O0l <= wire_nl01OiiOl_dataout; + nl01O1O0O <= wire_nl01OiiOO_dataout; + nl01O1O1i <= wire_nl01Oiili_dataout; + nl01O1O1l <= wire_nl01Oiill_dataout; + nl01O1O1O <= wire_nl01OiilO_dataout; + nl01O1Oii <= wire_nl01Oil1i_dataout; + nl01O1Oil <= wire_nl01Oil1l_dataout; + nl01O1OiO <= wire_nl01Oil1O_dataout; + nl01O1Oli <= wire_nl01Oil0i_dataout; + nl01O1Oll <= wire_nl01Oil0l_dataout; + nl01O1OlO <= wire_nl01Oil0O_dataout; + nl01O1OOi <= wire_nl01Oilii_dataout; + nl01O1OOl <= wire_nl01Oilil_dataout; + nl01O1OOO <= wire_nl01OiliO_dataout; + nl0i0000i <= wire_nl0i0l01l_dataout; + nl0i0000l <= wire_nl0i0l01O_dataout; + nl0i0000O <= wire_nl0i0l00i_dataout; + nl0i0001i <= wire_nl0i0l1Ol_dataout; + nl0i0001l <= wire_nl0i0l1OO_dataout; + nl0i0001O <= wire_nl0i0l01i_dataout; + nl0i000ii <= wire_nl0i0l00l_dataout; + nl0i000il <= wire_nl0i0l00O_dataout; + nl0i000iO <= wire_nl0i0l0ii_dataout; + nl0i000li <= wire_nl0i0l0il_dataout; + nl0i000ll <= wire_nl0i0l0iO_dataout; + nl0i000lO <= wire_nl0i0l0li_dataout; + nl0i000Oi <= wire_nl0i0l0ll_dataout; + nl0i000Ol <= wire_nl0i0l0lO_dataout; + nl0i000OO <= wire_nl0i0l0Oi_dataout; + nl0i0010i <= wire_nl0i0l11l_dataout; + nl0i0010l <= wire_nl0i0l11O_dataout; + nl0i0010O <= wire_nl0i0l10i_dataout; + nl0i0011i <= wire_nl0i0iOOl_dataout; + nl0i0011l <= wire_nl0i0iOOO_dataout; + nl0i0011O <= wire_nl0i0l11i_dataout; + nl0i001ii <= wire_nl0i0l10l_dataout; + nl0i001il <= wire_nl0i0l10O_dataout; + nl0i001iO <= wire_nl0i0l1ii_dataout; + nl0i001li <= wire_nl0i0l1il_dataout; + nl0i001ll <= wire_nl0i0l1iO_dataout; + nl0i001lO <= wire_nl0i0l1li_dataout; + nl0i001Oi <= wire_nl0i0l1ll_dataout; + nl0i001Ol <= wire_nl0i0l1lO_dataout; + nl0i001OO <= wire_nl0i0l1Oi_dataout; + nl0i00i0i <= wire_nl0i0li1l_dataout; + nl0i00i0l <= wire_nl0i0li1O_dataout; + nl0i00i0O <= wire_nl0i0li0i_dataout; + nl0i00i1i <= wire_nl0i0l0Ol_dataout; + nl0i00i1l <= wire_nl0i0l0OO_dataout; + nl0i00i1O <= wire_nl0i0li1i_dataout; + nl0i00iii <= wire_nl0i0li0l_dataout; + nl0i00iil <= wire_nl0i0li0O_dataout; + nl0i00iiO <= wire_nl0ili1lO_dataout; + nl0i0100i <= wire_nl0i0i01l_dataout; + nl0i0100l <= wire_nl0i0i01O_dataout; + nl0i0100O <= wire_nl0i0i00i_dataout; + nl0i0101i <= wire_nl0i0i1Ol_dataout; + nl0i0101l <= wire_nl0i0i1OO_dataout; + nl0i0101O <= wire_nl0i0i01i_dataout; + nl0i010ii <= wire_nl0i0i00l_dataout; + nl0i010il <= wire_nl0i0i00O_dataout; + nl0i010iO <= wire_nl0i0i0ii_dataout; + nl0i010li <= wire_nl0i0i0il_dataout; + nl0i010ll <= wire_nl0i0i0iO_dataout; + nl0i010lO <= wire_nl0i0i0li_dataout; + nl0i010Oi <= wire_nl0i0i0ll_dataout; + nl0i010Ol <= wire_nl0i0i0lO_dataout; + nl0i010OO <= wire_nl0i0i0Oi_dataout; + nl0i0110i <= wire_nl0i0i11l_dataout; + nl0i0110l <= wire_nl0i0i11O_dataout; + nl0i0110O <= wire_nl0i0i10i_dataout; + nl0i0111i <= wire_nl0i00OOl_dataout; + nl0i0111l <= wire_nl0i00OOO_dataout; + nl0i0111O <= wire_nl0i0i11i_dataout; + nl0i011ii <= wire_nl0i0i10l_dataout; + nl0i011il <= wire_nl0i0i10O_dataout; + nl0i011iO <= wire_nl0i0i1ii_dataout; + nl0i011li <= wire_nl0i0i1il_dataout; + nl0i011ll <= wire_nl0i0i1iO_dataout; + nl0i011lO <= wire_nl0i0i1li_dataout; + nl0i011Oi <= wire_nl0i0i1ll_dataout; + nl0i011Ol <= wire_nl0i0i1lO_dataout; + nl0i011OO <= wire_nl0i0i1Oi_dataout; + nl0i01i0i <= wire_nl0i0ii1l_dataout; + nl0i01i0l <= wire_nl0i0ii1O_dataout; + nl0i01i0O <= wire_nl0i0ii0i_dataout; + nl0i01i1i <= wire_nl0i0i0Ol_dataout; + nl0i01i1l <= wire_nl0i0i0OO_dataout; + nl0i01i1O <= wire_nl0i0ii1i_dataout; + nl0i01iii <= wire_nl0i0ii0l_dataout; + nl0i01iil <= wire_nl0i0ii0O_dataout; + nl0i01iiO <= wire_nl0i0iiii_dataout; + nl0i01ili <= wire_nl0i0iiil_dataout; + nl0i01ill <= wire_nl0i0iiiO_dataout; + nl0i01ilO <= wire_nl0i0iili_dataout; + nl0i01iOi <= wire_nl0i0iill_dataout; + nl0i01iOl <= wire_nl0i0iilO_dataout; + nl0i01iOO <= wire_nl0i0iiOi_dataout; + nl0i01l0i <= wire_nl0i0il1l_dataout; + nl0i01l0l <= wire_nl0i0il1O_dataout; + nl0i01l0O <= wire_nl0i0il0i_dataout; + nl0i01l1i <= wire_nl0i0iiOl_dataout; + nl0i01l1l <= wire_nl0i0iiOO_dataout; + nl0i01l1O <= wire_nl0i0il1i_dataout; + nl0i01lii <= wire_nl0i0il0l_dataout; + nl0i01lil <= wire_nl0i0il0O_dataout; + nl0i01liO <= wire_nl0i0ilii_dataout; + nl0i01lli <= wire_nl0i0ilil_dataout; + nl0i01lll <= wire_nl0i0iliO_dataout; + nl0i01llO <= wire_nl0i0illi_dataout; + nl0i01lOi <= wire_nl0i0illl_dataout; + nl0i01lOl <= wire_nl0i0illO_dataout; + nl0i01lOO <= wire_nl0i0ilOi_dataout; + nl0i01O0i <= wire_nl0i0iO1l_dataout; + nl0i01O0l <= wire_nl0i0iO1O_dataout; + nl0i01O0O <= wire_nl0i0iO0i_dataout; + nl0i01O1i <= wire_nl0i0ilOl_dataout; + nl0i01O1l <= wire_nl0i0ilOO_dataout; + nl0i01O1O <= wire_nl0i0iO1i_dataout; + nl0i01Oii <= wire_nl0i0iO0l_dataout; + nl0i01Oil <= wire_nl0i0iO0O_dataout; + nl0i01OiO <= wire_nl0i0iOii_dataout; + nl0i01Oli <= wire_nl0i0iOil_dataout; + nl0i01Oll <= wire_nl0i0iOiO_dataout; + nl0i01OlO <= wire_nl0i0iOli_dataout; + nl0i01OOi <= wire_nl0i0iOll_dataout; + nl0i01OOl <= wire_nl0i0iOlO_dataout; + nl0i01OOO <= wire_nl0i0iOOi_dataout; + nl0i1li0i <= wire_nl0i1lilO_dataout; + nl0i1li0l <= wire_nl0i1liOi_dataout; + nl0i1li0O <= wire_nl0i1liOl_dataout; + nl0i1li1O <= wire_nl0i1lill_dataout; + nl0i1liii <= wire_nl0i1liOO_dataout; + nl0i1liil <= wire_nl0i1ll1i_dataout; + nl0i1liiO <= wire_nl0i1O11l_dataout; + nl0i1lOOi <= wire_nl0i1O11O_dataout; + nl0i1lOOl <= wire_nl0i1O10i_dataout; + nl0i1lOOO <= wire_nl0i1O10l_dataout; + nl0i1O11i <= wire_nl0i1O1ll_dataout; + nl0i1O1ii <= wire_nl0i1O1lO_dataout; + nl0i1O1il <= wire_nl0i1O1Oi_dataout; + nl0i1O1iO <= wire_nl0i1O1Ol_dataout; + nl0i1O1li <= wire_nl0i00ili_dataout; + nl0i1OiOi <= wire_nl0i00ill_dataout; + nl0i1OiOl <= wire_nl0i00ilO_dataout; + nl0i1OiOO <= wire_nl0i00iOi_dataout; + nl0i1Ol0i <= wire_nl0i00l1l_dataout; + nl0i1Ol0l <= wire_nl0i00l1O_dataout; + nl0i1Ol0O <= wire_nl0i00l0i_dataout; + nl0i1Ol1i <= wire_nl0i00iOl_dataout; + nl0i1Ol1l <= wire_nl0i00iOO_dataout; + nl0i1Ol1O <= wire_nl0i00l1i_dataout; + nl0i1Olii <= wire_nl0i00l0l_dataout; + nl0i1Olil <= wire_nl0i00l0O_dataout; + nl0i1OliO <= wire_nl0i00lii_dataout; + nl0i1Olli <= wire_nl0i00lil_dataout; + nl0i1Olll <= wire_nl0i00liO_dataout; + nl0i1OllO <= wire_nl0i00lli_dataout; + nl0i1OlOi <= wire_nl0i00lll_dataout; + nl0i1OlOl <= wire_nl0i00llO_dataout; + nl0i1OlOO <= wire_nl0i00lOi_dataout; + nl0i1OO0i <= wire_nl0i00O1l_dataout; + nl0i1OO0l <= wire_nl0i00O1O_dataout; + nl0i1OO0O <= wire_nl0i00O0i_dataout; + nl0i1OO1i <= wire_nl0i00lOl_dataout; + nl0i1OO1l <= wire_nl0i00lOO_dataout; + nl0i1OO1O <= wire_nl0i00O1i_dataout; + nl0i1OOii <= wire_nl0i00O0l_dataout; + nl0i1OOil <= wire_nl0i00O0O_dataout; + nl0i1OOiO <= wire_nl0i00Oii_dataout; + nl0i1OOli <= wire_nl0i00Oil_dataout; + nl0i1OOll <= wire_nl0i00OiO_dataout; + nl0i1OOlO <= wire_nl0i00Oli_dataout; + nl0i1OOOi <= wire_nl0i00Oll_dataout; + nl0i1OOOl <= wire_nl0i00OlO_dataout; + nl0i1OOOO <= wire_nl0i00OOi_dataout; + nl0ili1ll <= wire_nl0illlOi_dataout; + nl0illl0i <= wire_nl0illlOl_dataout; + nl0illl0l <= wire_nl0illlOO_dataout; + nl0illl0O <= wire_nl0illO1i_dataout; + nl0illlii <= wire_nl0illO1l_dataout; + nl0illlil <= wire_nl0illO1O_dataout; + nl0illliO <= wire_nl0illO0i_dataout; + nl0illlli <= wire_nl0illO0l_dataout; + nl0illlll <= wire_nl0illO0O_dataout; + nl0illllO <= wire_nl0illOii_dataout; + nl0ilOiOi <= wire_nl0ilOlOi_dataout; + nl0ilOiOl <= wire_nl0ilOlOl_dataout; + nl0ilOiOO <= wire_nl0ilOlOO_dataout; + nl0ilOl0i <= wire_nl0ilOO0i_dataout; + nl0ilOl0l <= wire_nl0ilOO0l_dataout; + nl0ilOl0O <= wire_nl0ilOO0O_dataout; + nl0ilOl1i <= wire_nl0ilOO1i_dataout; + nl0ilOl1l <= wire_nl0ilOO1l_dataout; + nl0ilOl1O <= wire_nl0ilOO1O_dataout; + nl0ilOlii <= wire_nl0ilOOii_dataout; + nl0ilOlil <= wire_nl0ilOOil_dataout; + nl0ilOliO <= wire_nl0ilOOiO_dataout; + nl0ilOlli <= wire_nl0ilOOli_dataout; + nl0ilOlll <= wire_nl0ilOOll_dataout; + nl0iOi10i <= wire_nl0iOl10l_dataout; + nl0iOiili <= wire_nl0iOl10O_dataout; + nl0iOiill <= wire_nl0iOl1ii_dataout; + nl0iOiilO <= wire_nl0iOl1il_dataout; + nl0iOiiOi <= wire_nl0iOl1iO_dataout; + nl0iOiiOl <= wire_nl0iOl1li_dataout; + nl0iOiiOO <= wire_nl0iOl1ll_dataout; + nl0iOil0i <= wire_nl0iOl1OO_dataout; + nl0iOil0l <= wire_nl0iOl01i_dataout; + nl0iOil0O <= wire_nl0iOl01l_dataout; + nl0iOil1i <= wire_nl0iOl1lO_dataout; + nl0iOil1l <= wire_nl0iOl1Oi_dataout; + nl0iOil1O <= wire_nl0iOl1Ol_dataout; + nl0iOilii <= wire_nl0iOl01O_dataout; + nl0iOilil <= wire_nl0iOl00i_dataout; + nl0iOiliO <= wire_nl0iOl00l_dataout; + nl0iOilli <= wire_nl0iOl00O_dataout; + nl0iOilll <= wire_nl0iOl0ii_dataout; + nl0iOillO <= wire_nl0iOl0il_dataout; + nl0iOilOi <= wire_nl0iOl0iO_dataout; + nl0iOilOl <= wire_nl0iOl0li_dataout; + nl0iOilOO <= wire_nl0iOl0ll_dataout; + nl0iOiO0i <= wire_nl0iOl0OO_dataout; + nl0iOiO0l <= wire_nl0iOli1i_dataout; + nl0iOiO0O <= wire_nl0iOli1l_dataout; + nl0iOiO1i <= wire_nl0iOl0lO_dataout; + nl0iOiO1l <= wire_nl0iOl0Oi_dataout; + nl0iOiO1O <= wire_nl0iOl0Ol_dataout; + nl0iOiOii <= wire_nl0iOli1O_dataout; + nl0iOiOil <= wire_nl0iOli0i_dataout; + nl0iOiOiO <= wire_nl0iOli0l_dataout; + nl0iOiOli <= wire_nl0iOli0O_dataout; + nl0iOiOll <= wire_nl0iOliii_dataout; + nl0iOiOlO <= wire_nl0iOliil_dataout; + nl0iOiOOi <= wire_nl0iOliiO_dataout; + nl0iOiOOl <= wire_nl0iOlili_dataout; + nl0iOiOOO <= wire_nl0iOlill_dataout; + nl0iOl10i <= wire_nl0l101iO_dataout; + nl0iOl11i <= wire_nl0iOlilO_dataout; + nl0iOl11l <= wire_nl0iOliOi_dataout; + nl0iOl11O <= wire_nl0iOliOl_dataout; + nl0iOOO0i <= wire_nl0l101lO_dataout; + nl0iOOO0l <= wire_nl0l101Oi_dataout; + nl0iOOO0O <= wire_nl0l101Ol_dataout; + nl0iOOO1l <= wire_nl0l101li_dataout; + nl0iOOO1O <= wire_nl0l101ll_dataout; + nl0iOOOii <= wire_nl0l101OO_dataout; + nl0iOOOil <= wire_nl0l1001i_dataout; + nl0iOOOiO <= wire_nl0l1001l_dataout; + nl0iOOOli <= wire_nl0l1001O_dataout; + nl0iOOOll <= wire_nl0l1000i_dataout; + nl0iOOOlO <= wire_nl0l1000l_dataout; + nl0iOOOOi <= wire_nl0l1000O_dataout; + nl0iOOOOl <= wire_nl0l100ii_dataout; + nl0iOOOOO <= wire_nl0l100il_dataout; + nl0l000ll <= wire_nl0l001OO_dataout; + nl0l001iO <= wire_nl0l0001i_dataout; + nl0l001li <= wire_nl0l0001l_dataout; + nl0l001ll <= wire_nl0l0001O_dataout; + nl0l001lO <= wire_nl0l0000i_dataout; + nl0l001Oi <= wire_nl0l0000l_dataout; + nl0l001Ol <= wire_nl0l00l0i_dataout; + nl0l00iOl <= wire_nl0l00l0l_dataout; + nl0l00iOO <= wire_nl0l00l0O_dataout; + nl0l00l1i <= wire_nl0l00lii_dataout; + nl0l00l1l <= wire_nl0l00lil_dataout; + nl0l00l1O <= wire_nl0l00liO_dataout; + nl0l0100i <= wire_nl0l01i0i_dataout; + nl0l0100l <= wire_nl0l01i0l_dataout; + nl0l0100O <= wire_nl0l01i0O_dataout; + nl0l0101l <= wire_nl0l01i1l_dataout; + nl0l0101O <= wire_nl0l01i1O_dataout; + nl0l010ii <= wire_nl0l01iii_dataout; + nl0l010il <= wire_nl0l01iil_dataout; + nl0l010iO <= wire_nl0l01iiO_dataout; + nl0l010li <= wire_nl0l01ili_dataout; + nl0l010ll <= wire_nl0l01ill_dataout; + nl0l010lO <= wire_nl0l01ilO_dataout; + nl0l010Oi <= wire_nl0l01iOi_dataout; + nl0l010Ol <= wire_nl0l01iOl_dataout; + nl0l010OO <= wire_nl0l01O0i_dataout; + nl0l01O1l <= wire_nl0l01O0l_dataout; + nl0l01O1O <= wire_nl0l01O0O_dataout; + nl0l0i00i <= wire_nl0l0ii0i_dataout; + nl0l0i00l <= wire_nl0l0ii0l_dataout; + nl0l0i00O <= wire_nl0l0ii0O_dataout; + nl0l0i01i <= wire_nl0l0ii1i_dataout; + nl0l0i01l <= wire_nl0l0ii1l_dataout; + nl0l0i01O <= wire_nl0l0ii1O_dataout; + nl0l0i0ii <= wire_nl0l0iiii_dataout; + nl0l0i0il <= wire_nl0l0iiil_dataout; + nl0l0i0iO <= wire_nl0l0iiiO_dataout; + nl0l0i0li <= wire_nl0l0iili_dataout; + nl0l0i0ll <= wire_nl0l0Ol1i_dataout; + nl0l0i1ii <= wire_nl0l0i0lO_dataout; + nl0l0i1Oi <= wire_nl0l0i0Oi_dataout; + nl0l0i1Ol <= wire_nl0l0i0Ol_dataout; + nl0l0i1OO <= wire_nl0l0i0OO_dataout; + nl0l0liiO <= wire_nl0l0Ol1l_dataout; + nl0l0lili <= wire_nl0l0Ol1O_dataout; + nl0l0lill <= wire_nl0l0Ol0i_dataout; + nl0l0lilO <= wire_nl0l0Ol0l_dataout; + nl0l0liOi <= wire_nl0l0Ol0O_dataout; + nl0l0liOl <= wire_nl0l0Olii_dataout; + nl0l0liOO <= wire_nl0l0Olil_dataout; + nl0l0ll0i <= wire_nl0l0OllO_dataout; + nl0l0ll0l <= wire_nl0l0OlOi_dataout; + nl0l0ll0O <= wire_nl0l0OlOl_dataout; + nl0l0ll1i <= wire_nl0l0OliO_dataout; + nl0l0ll1l <= wire_nl0l0Olli_dataout; + nl0l0ll1O <= wire_nl0l0Olll_dataout; + nl0l0llii <= wire_nl0l0OlOO_dataout; + nl0l0llil <= wire_nl0l0OO1i_dataout; + nl0l0lliO <= wire_nl0l0OO1l_dataout; + nl0l0llli <= wire_nl0l0OO1O_dataout; + nl0l0llll <= wire_nl0l0OO0i_dataout; + nl0l0lllO <= wire_nl0l0OO0l_dataout; + nl0l0llOi <= wire_nl0l0OO0O_dataout; + nl0l0llOl <= wire_nl0l0OOii_dataout; + nl0l0llOO <= wire_nl0l0OOil_dataout; + nl0l0lO0i <= wire_nl0l0OOlO_dataout; + nl0l0lO0l <= wire_nl0l0OOOi_dataout; + nl0l0lO0O <= wire_nl0l0OOOl_dataout; + nl0l0lO1i <= wire_nl0l0OOiO_dataout; + nl0l0lO1l <= wire_nl0l0OOli_dataout; + nl0l0lO1O <= wire_nl0l0OOll_dataout; + nl0l0lOii <= wire_nl0l0OOOO_dataout; + nl0l0lOil <= wire_nl0li111i_dataout; + nl0l0lOiO <= wire_nl0li111l_dataout; + nl0l0lOli <= wire_nl0li111O_dataout; + nl0l0lOll <= wire_nl0li110i_dataout; + nl0l0lOlO <= wire_nl0li110l_dataout; + nl0l0lOOi <= wire_nl0li110O_dataout; + nl0l0lOOl <= wire_nl0li11ii_dataout; + nl0l0lOOO <= wire_nl0li11il_dataout; + nl0l0O00i <= wire_nl0li10lO_dataout; + nl0l0O00l <= wire_nl0li10Oi_dataout; + nl0l0O00O <= wire_nl0li10Ol_dataout; + nl0l0O01i <= wire_nl0li10iO_dataout; + nl0l0O01l <= wire_nl0li10li_dataout; + nl0l0O01O <= wire_nl0li10ll_dataout; + nl0l0O0ii <= wire_nl0li10OO_dataout; + nl0l0O0il <= wire_nl0li1i1i_dataout; + nl0l0O0iO <= wire_nl0li1i1l_dataout; + nl0l0O0li <= wire_nl0li1i1O_dataout; + nl0l0O0ll <= wire_nl0li1i0i_dataout; + nl0l0O0lO <= wire_nl0li1i0l_dataout; + nl0l0O0Oi <= wire_nl0li1i0O_dataout; + nl0l0O0Ol <= wire_nl0li1iii_dataout; + nl0l0O0OO <= wire_nl0li1iil_dataout; + nl0l0O10i <= wire_nl0li11lO_dataout; + nl0l0O10l <= wire_nl0li11Oi_dataout; + nl0l0O10O <= wire_nl0li11Ol_dataout; + nl0l0O11i <= wire_nl0li11iO_dataout; + nl0l0O11l <= wire_nl0li11li_dataout; + nl0l0O11O <= wire_nl0li11ll_dataout; + nl0l0O1ii <= wire_nl0li11OO_dataout; + nl0l0O1il <= wire_nl0li101i_dataout; + nl0l0O1iO <= wire_nl0li101l_dataout; + nl0l0O1li <= wire_nl0li101O_dataout; + nl0l0O1ll <= wire_nl0li100i_dataout; + nl0l0O1lO <= wire_nl0li100l_dataout; + nl0l0O1Oi <= wire_nl0li100O_dataout; + nl0l0O1Ol <= wire_nl0li10ii_dataout; + nl0l0O1OO <= wire_nl0li10il_dataout; + nl0l0Oi0i <= wire_nl0li1ilO_dataout; + nl0l0Oi0l <= wire_nl0li1iOi_dataout; + nl0l0Oi0O <= wire_nl0li1iOl_dataout; + nl0l0Oi1i <= wire_nl0li1iiO_dataout; + nl0l0Oi1l <= wire_nl0li1ili_dataout; + nl0l0Oi1O <= wire_nl0li1ill_dataout; + nl0l0Oiii <= wire_nl0li1iOO_dataout; + nl0l0Oiil <= wire_nl0li1l1i_dataout; + nl0l0OiiO <= wire_nl0li1l1l_dataout; + nl0l0Oili <= wire_nl0li1l1O_dataout; + nl0l0Oill <= wire_nl0li1l0i_dataout; + nl0l0OilO <= wire_nl0li1l0l_dataout; + nl0l0OiOi <= wire_nl0li1l0O_dataout; + nl0l0OiOl <= wire_nl0li1lii_dataout; + nl0l0OiOO <= wire_nl0lil11O_dataout; + nl0l1010i <= wire_nl0l1i0lO_dataout; + nl0l1010l <= wire_nl0l1i0Oi_dataout; + nl0l1010O <= wire_nl0l1i0Ol_dataout; + nl0l1011i <= wire_nl0l1i0iO_dataout; + nl0l1011l <= wire_nl0l1i0li_dataout; + nl0l1011O <= wire_nl0l1i0ll_dataout; + nl0l101ii <= wire_nl0l1i0OO_dataout; + nl0l101il <= wire_nl0l01i1i_dataout; + nl0l1100i <= wire_nl0l10ilO_dataout; + nl0l1100l <= wire_nl0l10iOi_dataout; + nl0l1100O <= wire_nl0l10iOl_dataout; + nl0l1101i <= wire_nl0l10iiO_dataout; + nl0l1101l <= wire_nl0l10ili_dataout; + nl0l1101O <= wire_nl0l10ill_dataout; + nl0l110ii <= wire_nl0l10iOO_dataout; + nl0l110il <= wire_nl0l10l1i_dataout; + nl0l110iO <= wire_nl0l10l1l_dataout; + nl0l110li <= wire_nl0l10l1O_dataout; + nl0l110ll <= wire_nl0l10l0i_dataout; + nl0l110lO <= wire_nl0l10l0l_dataout; + nl0l110Oi <= wire_nl0l10l0O_dataout; + nl0l110Ol <= wire_nl0l10lii_dataout; + nl0l110OO <= wire_nl0l10lil_dataout; + nl0l1110i <= wire_nl0l100lO_dataout; + nl0l1110l <= wire_nl0l100Oi_dataout; + nl0l1110O <= wire_nl0l100Ol_dataout; + nl0l1111i <= wire_nl0l100iO_dataout; + nl0l1111l <= wire_nl0l100li_dataout; + nl0l1111O <= wire_nl0l100ll_dataout; + nl0l111ii <= wire_nl0l100OO_dataout; + nl0l111il <= wire_nl0l10i1i_dataout; + nl0l111iO <= wire_nl0l10i1l_dataout; + nl0l111li <= wire_nl0l10i1O_dataout; + nl0l111ll <= wire_nl0l10i0i_dataout; + nl0l111lO <= wire_nl0l10i0l_dataout; + nl0l111Oi <= wire_nl0l10i0O_dataout; + nl0l111Ol <= wire_nl0l10iii_dataout; + nl0l111OO <= wire_nl0l10iil_dataout; + nl0l11i0i <= wire_nl0l10llO_dataout; + nl0l11i0l <= wire_nl0l10lOi_dataout; + nl0l11i0O <= wire_nl0l10lOl_dataout; + nl0l11i1i <= wire_nl0l10liO_dataout; + nl0l11i1l <= wire_nl0l10lli_dataout; + nl0l11i1O <= wire_nl0l10lll_dataout; + nl0l11iii <= wire_nl0l10lOO_dataout; + nl0l11iil <= wire_nl0l10O1i_dataout; + nl0l11iiO <= wire_nl0l10O1l_dataout; + nl0l11ili <= wire_nl0l10O1O_dataout; + nl0l11ill <= wire_nl0l10O0i_dataout; + nl0l11ilO <= wire_nl0l10O0l_dataout; + nl0l11iOi <= wire_nl0l10O0O_dataout; + nl0l11iOl <= wire_nl0l10Oii_dataout; + nl0l11iOO <= wire_nl0l10Oil_dataout; + nl0l11l0i <= wire_nl0l10OlO_dataout; + nl0l11l0l <= wire_nl0l10OOi_dataout; + nl0l11l0O <= wire_nl0l10OOl_dataout; + nl0l11l1i <= wire_nl0l10OiO_dataout; + nl0l11l1l <= wire_nl0l10Oli_dataout; + nl0l11l1O <= wire_nl0l10Oll_dataout; + nl0l11lii <= wire_nl0l10OOO_dataout; + nl0l11lil <= wire_nl0l1i11i_dataout; + nl0l11liO <= wire_nl0l1i11l_dataout; + nl0l11lli <= wire_nl0l1i11O_dataout; + nl0l11lll <= wire_nl0l1i10i_dataout; + nl0l11llO <= wire_nl0l1i10l_dataout; + nl0l11lOi <= wire_nl0l1i10O_dataout; + nl0l11lOl <= wire_nl0l1i1ii_dataout; + nl0l11lOO <= wire_nl0l1i1il_dataout; + nl0l11O0i <= wire_nl0l1i1lO_dataout; + nl0l11O0l <= wire_nl0l1i1Oi_dataout; + nl0l11O0O <= wire_nl0l1i1Ol_dataout; + nl0l11O1i <= wire_nl0l1i1iO_dataout; + nl0l11O1l <= wire_nl0l1i1li_dataout; + nl0l11O1O <= wire_nl0l1i1ll_dataout; + nl0l11Oii <= wire_nl0l1i1OO_dataout; + nl0l11Oil <= wire_nl0l1i01i_dataout; + nl0l11OiO <= wire_nl0l1i01l_dataout; + nl0l11Oli <= wire_nl0l1i01O_dataout; + nl0l11Oll <= wire_nl0l1i00i_dataout; + nl0l11OlO <= wire_nl0l1i00l_dataout; + nl0l11OOi <= wire_nl0l1i00O_dataout; + nl0l11OOl <= wire_nl0l1i0ii_dataout; + nl0l11OOO <= wire_nl0l1i0il_dataout; + nl0lil00i <= wire_nl0lil0Oi_dataout; + nl0lil00l <= wire_nl0lil0Ol_dataout; + nl0lil00O <= wire_nl0lil0OO_dataout; + nl0lil0ii <= wire_nl0lili1i_dataout; + nl0lil0il <= wire_nl0lili1l_dataout; + nl0lil0iO <= wire_nl0lili1O_dataout; + nl0lil0li <= wire_nl0lili0i_dataout; + nl0lil0ll <= wire_nl0lillii_dataout; + nl0lil11i <= wire_nl0lil10i_dataout; + nl0lil11l <= wire_nl0lil0lO_dataout; + nl0liliOO <= wire_nl0lillil_dataout; + nl0lill0i <= wire_nl0lilllO_dataout; + nl0lill0l <= wire_nl0lillOi_dataout; + nl0lill0O <= wire_nl0lillOl_dataout; + nl0lill1i <= wire_nl0lilliO_dataout; + nl0lill1l <= wire_nl0lillli_dataout; + nl0lill1O <= wire_nl0lillll_dataout; + nl0ll1O1l <= wire_nl0lliili_dataout; + nl0lliiiO <= wire_nl0llO1OO_dataout; + nl0llli0i <= wire_nl0llO00i_dataout; + nl0llli0l <= wire_nl0llO00l_dataout; + nl0llli0O <= wire_nl0llO00O_dataout; + nl0llli1i <= wire_nl0llO01i_dataout; + nl0llli1l <= wire_nl0llO01l_dataout; + nl0llli1O <= wire_nl0llO01O_dataout; + nl0llliii <= wire_nl0llO0ii_dataout; + nl0llliil <= wire_nl0llO0il_dataout; + nl0llliiO <= wire_nl0llO0iO_dataout; + nl0lllili <= wire_nl0llO0li_dataout; + nl0lllill <= wire_nl0llO0ll_dataout; + nl0lllilO <= wire_nl0llO0lO_dataout; + nl0llliOi <= wire_nl0llO0Oi_dataout; + nl0llliOl <= wire_nl0llO0Ol_dataout; + nl0llliOO <= wire_nl0llO0OO_dataout; + nl0llll0i <= wire_nl0llOi0i_dataout; + nl0llll0l <= wire_nl0llOi0l_dataout; + nl0llll0O <= wire_nl0llOi0O_dataout; + nl0llll1i <= wire_nl0llOi1i_dataout; + nl0llll1l <= wire_nl0llOi1l_dataout; + nl0llll1O <= wire_nl0llOi1O_dataout; + nl0llllii <= wire_nl0llOiii_dataout; + nl0llllil <= wire_nl0llOiil_dataout; + nl0lllliO <= wire_nl0llOiiO_dataout; + nl0llllli <= wire_nl0llOili_dataout; + nl0llllll <= wire_nl0llOill_dataout; + nl0lllllO <= wire_nl0llOilO_dataout; + nl0llllOi <= wire_nl0llOiOi_dataout; + nl0llllOl <= wire_nl0llOiOl_dataout; + nl0llllOO <= wire_nl0llOiOO_dataout; + nl0lllO0i <= wire_nl0lO1ili_dataout; + nl0lllO0l <= wire_nl0lO1ill_dataout; + nl0lllO0O <= wire_nl0lO1ilO_dataout; + nl0lllO1i <= wire_nl0llOl1i_dataout; + nl0lllO1l <= wire_nl0lO1iil_dataout; + nl0lllO1O <= wire_nl0lO1iiO_dataout; + nl0lllOii <= wire_nl0lO1iOi_dataout; + nl0lllOil <= wire_nl0lO1iOl_dataout; + nl0lllOiO <= wire_nl0lO1iOO_dataout; + nl0lllOli <= wire_nl0lO1l1i_dataout; + nl0lllOll <= wire_nl0lO1l1l_dataout; + nl0lllOlO <= wire_nl0lO1l1O_dataout; + nl0lllOOi <= wire_nl0lO1l0i_dataout; + nl0lllOOl <= wire_nl0lO1l0l_dataout; + nl0lllOOO <= wire_nl0lO1l0O_dataout; + nl0llO10i <= wire_nl0lO1lli_dataout; + nl0llO10l <= wire_nl0lO1lll_dataout; + nl0llO10O <= wire_nl0lO1llO_dataout; + nl0llO11i <= wire_nl0lO1lii_dataout; + nl0llO11l <= wire_nl0lO1lil_dataout; + nl0llO11O <= wire_nl0lO1liO_dataout; + nl0llO1ii <= wire_nl0lO1lOi_dataout; + nl0llO1il <= wire_nl0lO1lOl_dataout; + nl0llO1iO <= wire_nl0lO1lOO_dataout; + nl0llO1li <= wire_nl0lO1O1i_dataout; + nl0llO1ll <= wire_nl0lO1O1l_dataout; + nl0llO1lO <= wire_nl0lO1O1O_dataout; + nl0llO1Oi <= wire_nl0lO1O0i_dataout; + nl0llO1Ol <= wire_nl0lO1O0l_dataout; + nl0lOlill <= wire_nl0O1100i_dataout; + nl0O0i10O <= wire_nl0O0llOl_dataout; + nl0O0llOi <= wire_nl0Oi000l_dataout; + nl0O10Oll <= wire_nl0O1illl_dataout; + nl0O10OlO <= wire_nl0O1illO_dataout; + nl0O10OOi <= wire_nl0O1ilOi_dataout; + nl0O10OOl <= wire_nl0O1ilOl_dataout; + nl0O10OOO <= wire_nl0O1ilOO_dataout; + nl0O1101O <= wire_nl0O1illi_dataout; + nl0O1i00i <= wire_nl0O1l10i_dataout; + nl0O1i00l <= wire_nl0O1l10l_dataout; + nl0O1i00O <= wire_nl0O1l10O_dataout; + nl0O1i01i <= wire_nl0O1l11i_dataout; + nl0O1i01l <= wire_nl0O1l11l_dataout; + nl0O1i01O <= wire_nl0O1l11O_dataout; + nl0O1i0ii <= wire_nl0O1l1ii_dataout; + nl0O1i0il <= wire_nl0O1l1il_dataout; + nl0O1i0iO <= wire_nl0O1l1iO_dataout; + nl0O1i0li <= wire_nl0O1l1li_dataout; + nl0O1i0ll <= wire_nl0O1l1ll_dataout; + nl0O1i0lO <= wire_nl0O1O11O_dataout; + nl0O1i0Oi <= wire_nl0O1O10i_dataout; + nl0O1i0Ol <= wire_nl0O1O10l_dataout; + nl0O1i0OO <= wire_nl0O1O10O_dataout; + nl0O1i10i <= wire_nl0O1iO0i_dataout; + nl0O1i10l <= wire_nl0O1iO0l_dataout; + nl0O1i10O <= wire_nl0O1iO0O_dataout; + nl0O1i11i <= wire_nl0O1iO1i_dataout; + nl0O1i11l <= wire_nl0O1iO1l_dataout; + nl0O1i11O <= wire_nl0O1iO1O_dataout; + nl0O1i1ii <= wire_nl0O1iOii_dataout; + nl0O1i1il <= wire_nl0O1iOil_dataout; + nl0O1i1iO <= wire_nl0O1iOiO_dataout; + nl0O1i1li <= wire_nl0O1iOli_dataout; + nl0O1i1ll <= wire_nl0O1iOll_dataout; + nl0O1i1lO <= wire_nl0O1iOlO_dataout; + nl0O1i1Oi <= wire_nl0O1iOOi_dataout; + nl0O1i1Ol <= wire_nl0O1iOOl_dataout; + nl0O1i1OO <= wire_nl0O1iOOO_dataout; + nl0O1ii0i <= wire_nl0O1O1li_dataout; + nl0O1ii0l <= wire_nl0O1O1ll_dataout; + nl0O1ii0O <= wire_nl0O1O1lO_dataout; + nl0O1ii1i <= wire_nl0O1O1ii_dataout; + nl0O1ii1l <= wire_nl0O1O1il_dataout; + nl0O1ii1O <= wire_nl0O1O1iO_dataout; + nl0O1iiii <= wire_nl0O1O1Oi_dataout; + nl0O1iiil <= wire_nl0O1O1Ol_dataout; + nl0O1iiiO <= wire_nl0O1O1OO_dataout; + nl0O1iili <= wire_nl0O1O01i_dataout; + nl0O1iill <= wire_nl0O1O01l_dataout; + nl0O1iilO <= wire_nl0O1O01O_dataout; + nl0O1iiOi <= wire_nl0O1O00i_dataout; + nl0O1iiOl <= wire_nl0O1O00l_dataout; + nl0O1iiOO <= wire_nl0O1O00O_dataout; + nl0O1il0i <= wire_nl0O1O0li_dataout; + nl0O1il0l <= wire_nl0O1O0ll_dataout; + nl0O1il0O <= wire_nl0O1O0lO_dataout; + nl0O1il1i <= wire_nl0O1O0ii_dataout; + nl0O1il1l <= wire_nl0O1O0il_dataout; + nl0O1il1O <= wire_nl0O1O0iO_dataout; + nl0O1ilii <= wire_nl0O1O0Oi_dataout; + nl0O1ilil <= wire_nl0O1O0Ol_dataout; + nl0O1iliO <= wire_nl0O1O0OO_dataout; + nl0Oi000i <= wire_nl0OiiOli_dataout; + nl0Oi001i <= wire_nl0OiiOii_dataout; + nl0Oi001l <= wire_nl0OiiOil_dataout; + nl0Oi001O <= wire_nl0OiiOiO_dataout; + nl0Oi010i <= wire_nl0Oiilli_dataout; + nl0Oi010l <= wire_nl0Oiilll_dataout; + nl0Oi010O <= wire_nl0OiillO_dataout; + nl0Oi011i <= wire_nl0Oiilii_dataout; + nl0Oi011l <= wire_nl0Oiilil_dataout; + nl0Oi011O <= wire_nl0OiiliO_dataout; + nl0Oi01ii <= wire_nl0OiilOi_dataout; + nl0Oi01il <= wire_nl0OiilOl_dataout; + nl0Oi01iO <= wire_nl0OiilOO_dataout; + nl0Oi01li <= wire_nl0OiiO1i_dataout; + nl0Oi01ll <= wire_nl0OiiO1l_dataout; + nl0Oi01lO <= wire_nl0OiiO1O_dataout; + nl0Oi01Oi <= wire_nl0OiiO0i_dataout; + nl0Oi01Ol <= wire_nl0OiiO0l_dataout; + nl0Oi01OO <= wire_nl0OiiO0O_dataout; + nl0Oi1i0O <= wire_nl0Oi000O_dataout; + nl0Oi1iii <= wire_nl0Oi00ii_dataout; + nl0Oi1iil <= wire_nl0Oi00il_dataout; + nl0Oi1iiO <= wire_nl0Oi00iO_dataout; + nl0Oi1ili <= wire_nl0Oi00li_dataout; + nl0Oi1ill <= wire_nl0Oi00ll_dataout; + nl0Oi1ilO <= wire_nl0Oi00lO_dataout; + nl0Oi1iOi <= wire_nl0Oi00Oi_dataout; + nl0Oi1iOl <= wire_nl0Oi00Ol_dataout; + nl0Oi1iOO <= wire_nl0Oi00OO_dataout; + nl0Oi1l0i <= wire_nl0Oi0i0i_dataout; + nl0Oi1l0l <= wire_nl0Oi0i0l_dataout; + nl0Oi1l0O <= wire_nl0Oi0i0O_dataout; + nl0Oi1l1i <= wire_nl0Oi0i1i_dataout; + nl0Oi1l1l <= wire_nl0Oi0i1l_dataout; + nl0Oi1l1O <= wire_nl0Oi0i1O_dataout; + nl0Oi1lii <= wire_nl0Oi0iii_dataout; + nl0Oi1lil <= wire_nl0Oi0iil_dataout; + nl0Oi1liO <= wire_nl0Oi0iiO_dataout; + nl0Oi1lli <= wire_nl0Oi0ili_dataout; + nl0Oi1lll <= wire_nl0Oi0ill_dataout; + nl0Oi1llO <= wire_nl0Oi0ilO_dataout; + nl0Oi1lOi <= wire_nl0Oi0iOi_dataout; + nl0Oi1lOl <= wire_nl0Oi0iOl_dataout; + nl0Oi1lOO <= wire_nl0Oi0iOO_dataout; + nl0Oi1O0i <= wire_nl0Oi0l0i_dataout; + nl0Oi1O0l <= wire_nl0Oi0l0l_dataout; + nl0Oi1O0O <= wire_nl0Oi0l0O_dataout; + nl0Oi1O1i <= wire_nl0Oi0l1i_dataout; + nl0Oi1O1l <= wire_nl0Oi0l1l_dataout; + nl0Oi1O1O <= wire_nl0Oi0l1O_dataout; + nl0Oi1Oii <= wire_nl0OiiiOi_dataout; + nl0Oi1Oil <= wire_nl0OiiiOl_dataout; + nl0Oi1OiO <= wire_nl0OiiiOO_dataout; + nl0Oi1Oli <= wire_nl0Oiil1i_dataout; + nl0Oi1Oll <= wire_nl0Oiil1l_dataout; + nl0Oi1OlO <= wire_nl0Oiil1O_dataout; + nl0Oi1OOi <= wire_nl0Oiil0i_dataout; + nl0Oi1OOl <= wire_nl0Oiil0l_dataout; + nl0Oi1OOO <= wire_nl0Oiil0O_dataout; + nl0OiO0li <= wire_nl0OiO1Ol_dataout; + nl0OiO1il <= wire_nl0OiO1OO_dataout; + nl0OiO1iO <= wire_nl0OiO01i_dataout; + nl0OiO1li <= wire_nl0OiO01l_dataout; + nl0OiO1ll <= wire_nl0OiO01O_dataout; + nl0OiO1lO <= wire_nl0OiO00i_dataout; + nl0OiO1Oi <= wire_nl0OiOliO_dataout; + nl0OiOl0i <= wire_nl0OiOlli_dataout; + nl0OiOl0l <= wire_nl0OiOlll_dataout; + nl0OiOl0O <= wire_nl0OiOllO_dataout; + nl0OiOlii <= wire_nl0OiOlOi_dataout; + nl0OiOlil <= wire_nl0Ol0OlO_dataout; + nl0Ol000i <= wire_nl0Olii0l_dataout; + nl0Ol000l <= wire_nl0Olii0O_dataout; + nl0Ol000O <= wire_nl0Oliiii_dataout; + nl0Ol001i <= wire_nl0Olii1l_dataout; + nl0Ol001l <= wire_nl0Olii1O_dataout; + nl0Ol001O <= wire_nl0Olii0i_dataout; + nl0Ol00ii <= wire_nl0Oliiil_dataout; + nl0Ol00il <= wire_nl0OliiiO_dataout; + nl0Ol00iO <= wire_nl0Oliili_dataout; + nl0Ol00li <= wire_nl0Oliill_dataout; + nl0Ol00ll <= wire_nl0OliilO_dataout; + nl0Ol00lO <= wire_nl0OliiOi_dataout; + nl0Ol00Oi <= wire_nl0OliiOl_dataout; + nl0Ol00Ol <= wire_nl0OliiOO_dataout; + nl0Ol00OO <= wire_nl0Olil1i_dataout; + nl0Ol010i <= wire_nl0Oli00l_dataout; + nl0Ol010l <= wire_nl0Oli00O_dataout; + nl0Ol010O <= wire_nl0Oli0ii_dataout; + nl0Ol011i <= wire_nl0Oli01l_dataout; + nl0Ol011l <= wire_nl0Oli01O_dataout; + nl0Ol011O <= wire_nl0Oli00i_dataout; + nl0Ol01ii <= wire_nl0Oli0il_dataout; + nl0Ol01il <= wire_nl0Oli0iO_dataout; + nl0Ol01iO <= wire_nl0Oli0li_dataout; + nl0Ol01li <= wire_nl0Oli0ll_dataout; + nl0Ol01ll <= wire_nl0Oli0lO_dataout; + nl0Ol01lO <= wire_nl0Oli0Oi_dataout; + nl0Ol01Oi <= wire_nl0Oli0Ol_dataout; + nl0Ol01Ol <= wire_nl0Oli0OO_dataout; + nl0Ol01OO <= wire_nl0Olii1i_dataout; + nl0Ol0i0i <= wire_nl0Olil0l_dataout; + nl0Ol0i0l <= wire_nl0Olil0O_dataout; + nl0Ol0i0O <= wire_nl0Olilii_dataout; + nl0Ol0i1i <= wire_nl0Olil1l_dataout; + nl0Ol0i1l <= wire_nl0Olil1O_dataout; + nl0Ol0i1O <= wire_nl0Olil0i_dataout; + nl0Ol0iii <= wire_nl0Olilil_dataout; + nl0Ol0iil <= wire_nl0OliliO_dataout; + nl0Ol0iiO <= wire_nl0Olilli_dataout; + nl0Ol0ili <= wire_nl0Olilll_dataout; + nl0Ol0ill <= wire_nl0OlillO_dataout; + nl0Ol0ilO <= wire_nl0OlilOi_dataout; + nl0Ol0iOi <= wire_nl0OlilOl_dataout; + nl0Ol0iOl <= wire_nl0OlilOO_dataout; + nl0Ol0iOO <= wire_nl0OliO1i_dataout; + nl0Ol0l0i <= wire_nl0OliO0l_dataout; + nl0Ol0l0l <= wire_nl0OliO0O_dataout; + nl0Ol0l0O <= wire_nl0OliOii_dataout; + nl0Ol0l1i <= wire_nl0OliO1l_dataout; + nl0Ol0l1l <= wire_nl0OliO1O_dataout; + nl0Ol0l1O <= wire_nl0OliO0i_dataout; + nl0Ol0lii <= wire_nl0OliOil_dataout; + nl0Ol0lil <= wire_nl0OliOiO_dataout; + nl0Ol0liO <= wire_nl0OliOli_dataout; + nl0Ol0lli <= wire_nl0OliOll_dataout; + nl0Ol0lll <= wire_nl0OliOlO_dataout; + nl0Ol0llO <= wire_nl0OliOOi_dataout; + nl0Ol0lOi <= wire_nl0OliOOl_dataout; + nl0Ol0lOl <= wire_nl0OliOOO_dataout; + nl0Ol0lOO <= wire_nl0Oll11i_dataout; + nl0Ol0O0i <= wire_nl0Oll10l_dataout; + nl0Ol0O0l <= wire_nl0Oll10O_dataout; + nl0Ol0O0O <= wire_nl0Oll1ii_dataout; + nl0Ol0O1i <= wire_nl0Oll11l_dataout; + nl0Ol0O1l <= wire_nl0Oll11O_dataout; + nl0Ol0O1O <= wire_nl0Oll10i_dataout; + nl0Ol0Oii <= wire_nl0Oll1il_dataout; + nl0Ol0Oil <= wire_nl0Oll1iO_dataout; + nl0Ol0OiO <= wire_nl0Oll1li_dataout; + nl0Ol0Oli <= wire_nl0Oll1ll_dataout; + nl0Ol0Oll <= wire_nl0OO1OiO_dataout; + nl0Ol1llO <= wire_nl0Ol0OOi_dataout; + nl0Ol1lOi <= wire_nl0Ol0OOl_dataout; + nl0Ol1lOl <= wire_nl0Ol0OOO_dataout; + nl0Ol1lOO <= wire_nl0Oli11i_dataout; + nl0Ol1O0i <= wire_nl0Oli10l_dataout; + nl0Ol1O0l <= wire_nl0Oli10O_dataout; + nl0Ol1O0O <= wire_nl0Oli1ii_dataout; + nl0Ol1O1i <= wire_nl0Oli11l_dataout; + nl0Ol1O1l <= wire_nl0Oli11O_dataout; + nl0Ol1O1O <= wire_nl0Oli10i_dataout; + nl0Ol1Oii <= wire_nl0Oli1il_dataout; + nl0Ol1Oil <= wire_nl0Oli1iO_dataout; + nl0Ol1OiO <= wire_nl0Oli1li_dataout; + nl0Ol1Oli <= wire_nl0Oli1ll_dataout; + nl0Ol1Oll <= wire_nl0Oli1lO_dataout; + nl0Ol1OlO <= wire_nl0Oli1Oi_dataout; + nl0Ol1OOi <= wire_nl0Oli1Ol_dataout; + nl0Ol1OOl <= wire_nl0Oli1OO_dataout; + nl0Ol1OOO <= wire_nl0Oli01i_dataout; + nl0OO0Oii <= wire_nl0OOii1O_dataout; + nl0OO0Oil <= wire_nl0OOii0i_dataout; + nl0OO0OiO <= wire_nl0OOii0l_dataout; + nl0OO0Oli <= wire_nl0OOii0O_dataout; + nl0OO0Oll <= wire_nl0OOiiii_dataout; + nl0OO0OlO <= wire_nl0OOiiil_dataout; + nl0OO0OOi <= wire_nl0OOiiiO_dataout; + nl0OO0OOl <= wire_nl0OOiili_dataout; + nl0OO0OOO <= wire_nl0OOiill_dataout; + nl0OO1iOO <= wire_nl0OO1Oli_dataout; + nl0OO1l0i <= wire_nl0OO1OOl_dataout; + nl0OO1l0l <= wire_nl0OO1OOO_dataout; + nl0OO1l0O <= wire_nl0OO011i_dataout; + nl0OO1l1i <= wire_nl0OO1Oll_dataout; + nl0OO1l1l <= wire_nl0OO1OlO_dataout; + nl0OO1l1O <= wire_nl0OO1OOi_dataout; + nl0OO1lii <= wire_nl0OO011l_dataout; + nl0OO1lil <= wire_nl0OO011O_dataout; + nl0OO1liO <= wire_nl0OO010i_dataout; + nl0OO1lli <= wire_nl0OO010l_dataout; + nl0OO1lll <= wire_nl0OO010O_dataout; + nl0OO1llO <= wire_nl0OO01ii_dataout; + nl0OO1lOi <= wire_nl0OO01il_dataout; + nl0OO1lOl <= wire_nl0OO01iO_dataout; + nl0OO1lOO <= wire_nl0OO01li_dataout; + nl0OO1O0i <= wire_nl0OO01Ol_dataout; + nl0OO1O0l <= wire_nl0OO01OO_dataout; + nl0OO1O0O <= wire_nl0OO001i_dataout; + nl0OO1O1i <= wire_nl0OO01ll_dataout; + nl0OO1O1l <= wire_nl0OO01lO_dataout; + nl0OO1O1O <= wire_nl0OO01Oi_dataout; + nl0OO1Oii <= wire_nl0OO001l_dataout; + nl0OO1Oil <= wire_nl0OOii1l_dataout; + nl0OOi00i <= wire_nl0OOilOO_dataout; + nl0OOi00l <= wire_nl0OOiO1i_dataout; + nl0OOi00O <= wire_nl0OOiO1l_dataout; + nl0OOi01i <= wire_nl0OOillO_dataout; + nl0OOi01l <= wire_nl0OOilOi_dataout; + nl0OOi01O <= wire_nl0OOilOl_dataout; + nl0OOi0ii <= wire_nl0OOiO1O_dataout; + nl0OOi0il <= wire_nl0OOiO0i_dataout; + nl0OOi0iO <= wire_nl0OOiO0l_dataout; + nl0OOi0li <= wire_nl0OOiO0O_dataout; + nl0OOi0ll <= wire_nl0OOiOii_dataout; + nl0OOi0lO <= wire_nl0OOiOil_dataout; + nl0OOi0Oi <= wire_nl0OOiOiO_dataout; + nl0OOi0Ol <= wire_nl0OOiOli_dataout; + nl0OOi0OO <= wire_nl0OOiOll_dataout; + nl0OOi10i <= wire_nl0OOiiOO_dataout; + nl0OOi10l <= wire_nl0OOil1i_dataout; + nl0OOi10O <= wire_nl0OOil1l_dataout; + nl0OOi11i <= wire_nl0OOiilO_dataout; + nl0OOi11l <= wire_nl0OOiiOi_dataout; + nl0OOi11O <= wire_nl0OOiiOl_dataout; + nl0OOi1ii <= wire_nl0OOil1O_dataout; + nl0OOi1il <= wire_nl0OOil0i_dataout; + nl0OOi1iO <= wire_nl0OOil0l_dataout; + nl0OOi1li <= wire_nl0OOil0O_dataout; + nl0OOi1ll <= wire_nl0OOilii_dataout; + nl0OOi1lO <= wire_nl0OOilil_dataout; + nl0OOi1Oi <= wire_nl0OOiliO_dataout; + nl0OOi1Ol <= wire_nl0OOilli_dataout; + nl0OOi1OO <= wire_nl0OOilll_dataout; + nl0OOii1i <= wire_nl0OOO0li_dataout; + nl0OOO00i <= wire_nl0OOOiOi_dataout; + nl0OOO00l <= wire_nl0OOOiOl_dataout; + nl0OOO00O <= wire_nl0OOOiOO_dataout; + nl0OOO01i <= wire_nl0OOOili_dataout; + nl0OOO01l <= wire_nl0OOOill_dataout; + nl0OOO01O <= wire_nl0OOOilO_dataout; + nl0OOO0ii <= wire_nl0OOOl1i_dataout; + nl0OOO0il <= wire_nl0OOOl1l_dataout; + nl0OOO0iO <= wire_nl0OOOl1O_dataout; + nl0OOO10i <= wire_nl0OOO0Oi_dataout; + nl0OOO10l <= wire_nl0OOO0Ol_dataout; + nl0OOO10O <= wire_nl0OOO0OO_dataout; + nl0OOO11l <= wire_nl0OOO0ll_dataout; + nl0OOO11O <= wire_nl0OOO0lO_dataout; + nl0OOO1ii <= wire_nl0OOOi1i_dataout; + nl0OOO1il <= wire_nl0OOOi1l_dataout; + nl0OOO1iO <= wire_nl0OOOi1O_dataout; + nl0OOO1li <= wire_nl0OOOi0i_dataout; + nl0OOO1ll <= wire_nl0OOOi0l_dataout; + nl0OOO1lO <= wire_nl0OOOi0O_dataout; + nl0OOO1Oi <= wire_nl0OOOiii_dataout; + nl0OOO1Ol <= wire_nl0OOOiil_dataout; + nl0OOO1OO <= wire_nl0OOOiiO_dataout; + nl10ii0li <= wire_nl10ii0Oi_dataout; + nl10ii0ll <= wire_nl10ii0Ol_dataout; + nl10ilO0O <= wire_nl10iO11i_dataout; + nl10ilOii <= wire_nl10iO11l_dataout; + nl10ilOil <= wire_nl10iO11O_dataout; + nl10ilOiO <= wire_nl10iO10i_dataout; + nl10ilOli <= wire_nl10iO10l_dataout; + nl10ilOll <= wire_nl10iO10O_dataout; + nl10ilOlO <= wire_nl10iO1ii_dataout; + nl10ilOOi <= wire_nl10iO1il_dataout; + nl10ilOOl <= wire_nl10iOOlO_dataout; + nl10iO1li <= wire_nl10ilOOO_dataout; + nl10iOO0i <= wire_nl10iOOOl_dataout; + nl10iOO0l <= wire_nl10iOOOO_dataout; + nl10iOO0O <= wire_nl10l111i_dataout; + nl10iOO1O <= wire_nl10iOOOi_dataout; + nl10iOOii <= wire_nl10l111l_dataout; + nl10iOOil <= wire_nl10l111O_dataout; + nl10iOOiO <= wire_nl10l110i_dataout; + nl10iOOli <= wire_nl10l110l_dataout; + nl10iOOll <= wire_nl10l110O_dataout; + nl10liO1l <= wire_nl10lll0l_dataout; + nl10lli0O <= wire_nl10lll0O_dataout; + nl10lliil <= wire_nl10lllil_dataout; + nl10lliiO <= wire_nl10llliO_dataout; + nl10llili <= wire_nl10lllli_dataout; + nl10llill <= wire_nl10lllll_dataout; + nl10llilO <= wire_nl10llllO_dataout; + nl10lliOi <= wire_nl10lllOi_dataout; + nl10lliOO <= wire_nl10lllOO_dataout; + nl10lll0i <= wire_nl10O100O_dataout; + nl10lll1i <= wire_nl10llO1i_dataout; + nl10lll1l <= wire_nl10llO1l_dataout; + nl10lll1O <= wire_nl10llO1O_dataout; + nl10O000i <= wire_nl10Oi10l_dataout; + nl10O000l <= wire_nl10Oi10O_dataout; + nl10O000O <= wire_nl10Oi1ii_dataout; + nl10O001i <= wire_nl10Oi11l_dataout; + nl10O001l <= wire_nl10Oi11O_dataout; + nl10O001O <= wire_nl10Oi10i_dataout; + nl10O00ii <= wire_nl10Oi1il_dataout; + nl10O00il <= wire_nl10Oi1iO_dataout; + nl10O00iO <= wire_nl10Oi1li_dataout; + nl10O00li <= wire_nl10Oi1ll_dataout; + nl10O00ll <= wire_nl10Oi1lO_dataout; + nl10O00lO <= wire_nl10Oi1Oi_dataout; + nl10O00Oi <= wire_nl10Oi1Ol_dataout; + nl10O00Ol <= wire_nl10Oi1OO_dataout; + nl10O00OO <= wire_nl10Oi01i_dataout; + nl10O01Ol <= wire_nl10O0OOO_dataout; + nl10O01OO <= wire_nl10Oi11i_dataout; + nl10O0i0i <= wire_nl10Oi00l_dataout; + nl10O0i0l <= wire_nl10Oi00O_dataout; + nl10O0i0O <= wire_nl10Oi0ii_dataout; + nl10O0i1i <= wire_nl10Oi01l_dataout; + nl10O0i1l <= wire_nl10Oi01O_dataout; + nl10O0i1O <= wire_nl10Oi00i_dataout; + nl10O0iii <= wire_nl10Oi0il_dataout; + nl10O0iil <= wire_nl10Oi0iO_dataout; + nl10O0iiO <= wire_nl10Oi0li_dataout; + nl10O0ili <= wire_nl10Oi0ll_dataout; + nl10O0ill <= wire_nl10Oi0lO_dataout; + nl10O0ilO <= wire_nl10Oi0Oi_dataout; + nl10O0iOi <= wire_nl10Oi0Ol_dataout; + nl10O0iOl <= wire_nl10Oi0OO_dataout; + nl10O0iOO <= wire_nl10Oii1i_dataout; + nl10O0l0i <= wire_nl10Oii0l_dataout; + nl10O0l0l <= wire_nl10Oii0O_dataout; + nl10O0l0O <= wire_nl10Oiiii_dataout; + nl10O0l1i <= wire_nl10Oii1l_dataout; + nl10O0l1l <= wire_nl10Oii1O_dataout; + nl10O0l1O <= wire_nl10Oii0i_dataout; + nl10O0lii <= wire_nl10Oiiil_dataout; + nl10O0lil <= wire_nl10OiiiO_dataout; + nl10O0liO <= wire_nl10Oiili_dataout; + nl10O0lli <= wire_nl10Oiill_dataout; + nl10O0lll <= wire_nl10OiilO_dataout; + nl10O0llO <= wire_nl10OiiOi_dataout; + nl10O0lOi <= wire_nl10OiiOl_dataout; + nl10O0lOl <= wire_nl10OiiOO_dataout; + nl10O0lOO <= wire_nl10Oil1i_dataout; + nl10O0O0i <= wire_nl10Oil0l_dataout; + nl10O0O0l <= wire_nl10Oil0O_dataout; + nl10O0O0O <= wire_nl10Oilii_dataout; + nl10O0O1i <= wire_nl10Oil1l_dataout; + nl10O0O1l <= wire_nl10Oil1O_dataout; + nl10O0O1O <= wire_nl10Oil0i_dataout; + nl10O0Oii <= wire_nl10Oilil_dataout; + nl10O0Oil <= wire_nl10OiliO_dataout; + nl10O0OiO <= wire_nl10Oilli_dataout; + nl10O0Oli <= wire_nl10Oilll_dataout; + nl10O0Oll <= wire_nl10OillO_dataout; + nl10O0OlO <= wire_nl10OilOi_dataout; + nl10O0OOi <= wire_nl1i1100i_dataout; + nl10O100i <= wire_nl10O1i0l_dataout; + nl10O100l <= wire_nl10O0OOl_dataout; + nl10O101i <= wire_nl10O1i1l_dataout; + nl10O101l <= wire_nl10O1i1O_dataout; + nl10O101O <= wire_nl10O1i0i_dataout; + nl10O110O <= wire_nl10O10ii_dataout; + nl10O11ii <= wire_nl10O10il_dataout; + nl10O11il <= wire_nl10O10iO_dataout; + nl10O11iO <= wire_nl10O10li_dataout; + nl10O11li <= wire_nl10O10ll_dataout; + nl10O11ll <= wire_nl10O10lO_dataout; + nl10O11lO <= wire_nl10O10Oi_dataout; + nl10O11Oi <= wire_nl10O10Ol_dataout; + nl10O11Ol <= wire_nl10O10OO_dataout; + nl10O11OO <= wire_nl10O1i1i_dataout; + nl110100i <= wire_nl11001ll_dataout; + nl110100l <= wire_nl11001lO_dataout; + nl110100O <= wire_nl11001Oi_dataout; + nl110101i <= wire_nl11001il_dataout; + nl110101l <= wire_nl11001iO_dataout; + nl110101O <= wire_nl11001li_dataout; + nl11010ii <= wire_nl11001Ol_dataout; + nl11010il <= wire_nl11001OO_dataout; + nl11010iO <= wire_nl110001i_dataout; + nl11010li <= wire_nl110001l_dataout; + nl11010ll <= wire_nl110001O_dataout; + nl11010lO <= wire_nl110000i_dataout; + nl11010Oi <= wire_nl110000l_dataout; + nl11010Ol <= wire_nl110000O_dataout; + nl11010OO <= wire_nl11000ii_dataout; + nl110110i <= wire_nl1101Oll_dataout; + nl110110l <= wire_nl1101OlO_dataout; + nl110110O <= wire_nl1101OOi_dataout; + nl110111i <= wire_nl1101Oil_dataout; + nl110111l <= wire_nl1101OiO_dataout; + nl110111O <= wire_nl1101Oli_dataout; + nl11011ii <= wire_nl1101OOl_dataout; + nl11011il <= wire_nl1101OOO_dataout; + nl11011iO <= wire_nl110011i_dataout; + nl11011li <= wire_nl110011l_dataout; + nl11011ll <= wire_nl110011O_dataout; + nl11011lO <= wire_nl110010i_dataout; + nl11011Oi <= wire_nl110010l_dataout; + nl11011Ol <= wire_nl110010O_dataout; + nl11011OO <= wire_nl11001ii_dataout; + nl1101i0i <= wire_nl11000ll_dataout; + nl1101i0l <= wire_nl11000lO_dataout; + nl1101i0O <= wire_nl11000Oi_dataout; + nl1101i1i <= wire_nl11000il_dataout; + nl1101i1l <= wire_nl11000iO_dataout; + nl1101i1O <= wire_nl11000li_dataout; + nl1101iii <= wire_nl11000Ol_dataout; + nl1101iil <= wire_nl11000OO_dataout; + nl1101iiO <= wire_nl1100i1i_dataout; + nl1101ili <= wire_nl1100i1l_dataout; + nl1101ill <= wire_nl1100i1O_dataout; + nl1101ilO <= wire_nl1100i0i_dataout; + nl1101iOi <= wire_nl1100i0l_dataout; + nl1101iOl <= wire_nl1100i0O_dataout; + nl1101iOO <= wire_nl1100iii_dataout; + nl1101l0i <= wire_nl1100ill_dataout; + nl1101l0l <= wire_nl1100ilO_dataout; + nl1101l0O <= wire_nl11i101i_dataout; + nl1101l1i <= wire_nl1100iil_dataout; + nl1101l1l <= wire_nl1100iiO_dataout; + nl1101l1O <= wire_nl1100ili_dataout; + nl110Oi0i <= wire_nl11i100i_dataout; + nl110Oi0l <= wire_nl11i100l_dataout; + nl110Oi0O <= wire_nl11i100O_dataout; + nl110Oi1l <= wire_nl11i101l_dataout; + nl110Oi1O <= wire_nl11i101O_dataout; + nl110Oiii <= wire_nl11i10ii_dataout; + nl110Oiil <= wire_nl11i10il_dataout; + nl110OiiO <= wire_nl11i10iO_dataout; + nl110Oili <= wire_nl11i10li_dataout; + nl110Oill <= wire_nl11i10ll_dataout; + nl110OilO <= wire_nl11i10lO_dataout; + nl110OiOi <= wire_nl11i10Oi_dataout; + nl110OiOl <= wire_nl11i10Ol_dataout; + nl110OiOO <= wire_nl11i10OO_dataout; + nl110Ol0i <= wire_nl11i1i0i_dataout; + nl110Ol0l <= wire_nl11i1i0l_dataout; + nl110Ol0O <= wire_nl11i1i0O_dataout; + nl110Ol1i <= wire_nl11i1i1i_dataout; + nl110Ol1l <= wire_nl11i1i1l_dataout; + nl110Ol1O <= wire_nl11i1i1O_dataout; + nl110Olii <= wire_nl11i1iii_dataout; + nl110Olil <= wire_nl11i1iil_dataout; + nl110OliO <= wire_nl11i1iiO_dataout; + nl110Olli <= wire_nl11i1ili_dataout; + nl110Olll <= wire_nl11i1ill_dataout; + nl110OllO <= wire_nl11i1ilO_dataout; + nl110OlOi <= wire_nl11i1iOi_dataout; + nl110OlOl <= wire_nl11i1iOl_dataout; + nl110OlOO <= wire_nl11i1iOO_dataout; + nl110OO0i <= wire_nl11i1l0i_dataout; + nl110OO0l <= wire_nl11i1l0l_dataout; + nl110OO0O <= wire_nl11i1l0O_dataout; + nl110OO1i <= wire_nl11i1l1i_dataout; + nl110OO1l <= wire_nl11i1l1l_dataout; + nl110OO1O <= wire_nl11i1l1O_dataout; + nl110OOii <= wire_nl11i1lii_dataout; + nl110OOil <= wire_nl11i1lil_dataout; + nl110OOiO <= wire_nl11i1liO_dataout; + nl110OOli <= wire_nl11i1lli_dataout; + nl110OOll <= wire_nl11i1lll_dataout; + nl110OOlO <= wire_nl11i1llO_dataout; + nl110OOOi <= wire_nl11i1lOi_dataout; + nl110OOOl <= wire_nl11i1lOl_dataout; + nl110OOOO <= wire_nl11i1lOO_dataout; + nl11100iO <= wire_nl111i1li_dataout; + nl11100li <= wire_nl111i1ll_dataout; + nl11100ll <= wire_nl111i1lO_dataout; + nl11100lO <= wire_nl111i1Oi_dataout; + nl11100Oi <= wire_nl111i1Ol_dataout; + nl11100Ol <= wire_nl111i1OO_dataout; + nl11100OO <= wire_nl111i01i_dataout; + nl11101il <= wire_nl111i1iO_dataout; + nl1110i0i <= wire_nl111i00l_dataout; + nl1110i0l <= wire_nl111i00O_dataout; + nl1110i0O <= wire_nl111i0ii_dataout; + nl1110i1i <= wire_nl111i01l_dataout; + nl1110i1l <= wire_nl111i01O_dataout; + nl1110i1O <= wire_nl111i00i_dataout; + nl1110iii <= wire_nl111i0il_dataout; + nl1110iil <= wire_nl111i0iO_dataout; + nl1110iiO <= wire_nl111i0li_dataout; + nl1110ili <= wire_nl111i0ll_dataout; + nl1110ill <= wire_nl111i0lO_dataout; + nl1110ilO <= wire_nl111i0Oi_dataout; + nl1110iOi <= wire_nl111i0Ol_dataout; + nl1110iOl <= wire_nl111i0OO_dataout; + nl1110iOO <= wire_nl111ii1i_dataout; + nl1110l0i <= wire_nl111ii0l_dataout; + nl1110l0l <= wire_nl111ii0O_dataout; + nl1110l0O <= wire_nl111iiii_dataout; + nl1110l1i <= wire_nl111ii1l_dataout; + nl1110l1l <= wire_nl111ii1O_dataout; + nl1110l1O <= wire_nl111ii0i_dataout; + nl1110lii <= wire_nl111iiil_dataout; + nl1110lil <= wire_nl111iiiO_dataout; + nl1110liO <= wire_nl111iili_dataout; + nl1110lli <= wire_nl111iill_dataout; + nl1110lll <= wire_nl111iilO_dataout; + nl1110llO <= wire_nl111iiOi_dataout; + nl1110lOi <= wire_nl111iiOl_dataout; + nl1110lOl <= wire_nl111iiOO_dataout; + nl1110lOO <= wire_nl111il1i_dataout; + nl1110O0i <= wire_nl111il0l_dataout; + nl1110O0l <= wire_nl111il0O_dataout; + nl1110O0O <= wire_nl111ilii_dataout; + nl1110O1i <= wire_nl111il1l_dataout; + nl1110O1l <= wire_nl111il1O_dataout; + nl1110O1O <= wire_nl111il0i_dataout; + nl1110Oii <= wire_nl111ilil_dataout; + nl1110Oil <= wire_nl111iliO_dataout; + nl1110OiO <= wire_nl111illi_dataout; + nl1110Oli <= wire_nl111illl_dataout; + nl1110Oll <= wire_nl111illO_dataout; + nl1110OlO <= wire_nl111ilOi_dataout; + nl1110OOi <= wire_nl111ilOl_dataout; + nl1110OOl <= wire_nl111ilOO_dataout; + nl1110OOO <= wire_nl111iO1i_dataout; + nl111i10i <= wire_nl111iO0l_dataout; + nl111i10l <= wire_nl111iO0O_dataout; + nl111i10O <= wire_nl111iOii_dataout; + nl111i11i <= wire_nl111iO1l_dataout; + nl111i11l <= wire_nl111iO1O_dataout; + nl111i11O <= wire_nl111iO0i_dataout; + nl111i1ii <= wire_nl111iOil_dataout; + nl111iOli <= wire_nl111ll1O_dataout; + nl111l00i <= wire_nl111llll_dataout; + nl111l00l <= wire_nl111lllO_dataout; + nl111l00O <= wire_nl111llOi_dataout; + nl111l01i <= wire_nl111llil_dataout; + nl111l01l <= wire_nl111lliO_dataout; + nl111l01O <= wire_nl111llli_dataout; + nl111l0ii <= wire_nl111llOl_dataout; + nl111l0il <= wire_nl111llOO_dataout; + nl111l0iO <= wire_nl111lO1i_dataout; + nl111l0li <= wire_nl111lO1l_dataout; + nl111l0ll <= wire_nl111lO1O_dataout; + nl111l0lO <= wire_nl111lO0i_dataout; + nl111l0Oi <= wire_nl111lO0l_dataout; + nl111l0Ol <= wire_nl111lO0O_dataout; + nl111l0OO <= wire_nl111lOii_dataout; + nl111l1lO <= wire_nl111ll0i_dataout; + nl111l1Oi <= wire_nl111ll0l_dataout; + nl111l1Ol <= wire_nl111ll0O_dataout; + nl111l1OO <= wire_nl111llii_dataout; + nl111li0i <= wire_nl111lOll_dataout; + nl111li0l <= wire_nl111lOlO_dataout; + nl111li0O <= wire_nl111lOOi_dataout; + nl111li1i <= wire_nl111lOil_dataout; + nl111li1l <= wire_nl111lOiO_dataout; + nl111li1O <= wire_nl111lOli_dataout; + nl111liii <= wire_nl111lOOl_dataout; + nl111liil <= wire_nl111lOOO_dataout; + nl111liiO <= wire_nl111O11i_dataout; + nl111lili <= wire_nl111O11l_dataout; + nl111lill <= wire_nl111O11O_dataout; + nl111lilO <= wire_nl111O10i_dataout; + nl111liOi <= wire_nl111O10l_dataout; + nl111liOl <= wire_nl111O10O_dataout; + nl111liOO <= wire_nl111O1ii_dataout; + nl111ll1i <= wire_nl111O1il_dataout; + nl111ll1l <= wire_nl1101lii_dataout; + nl111OO0i <= wire_nl1101lll_dataout; + nl111OO0l <= wire_nl1101llO_dataout; + nl111OO0O <= wire_nl1101lOi_dataout; + nl111OO1i <= wire_nl1101lil_dataout; + nl111OO1l <= wire_nl1101liO_dataout; + nl111OO1O <= wire_nl1101lli_dataout; + nl111OOii <= wire_nl1101lOl_dataout; + nl111OOil <= wire_nl1101lOO_dataout; + nl111OOiO <= wire_nl1101O1i_dataout; + nl111OOli <= wire_nl1101O1l_dataout; + nl111OOll <= wire_nl1101O1O_dataout; + nl111OOlO <= wire_nl1101O0i_dataout; + nl111OOOi <= wire_nl1101O0l_dataout; + nl111OOOl <= wire_nl1101O0O_dataout; + nl111OOOO <= wire_nl1101Oii_dataout; + nl11i110i <= wire_nl11i1O0i_dataout; + nl11i110l <= wire_nl11i1O0l_dataout; + nl11i110O <= wire_nl11i1O0O_dataout; + nl11i111i <= wire_nl11i1O1i_dataout; + nl11i111l <= wire_nl11i1O1l_dataout; + nl11i111O <= wire_nl11i1O1O_dataout; + nl11i11ii <= wire_nl11i1Oii_dataout; + nl11i11il <= wire_nl11i1Oil_dataout; + nl11i11iO <= wire_nl11i1OiO_dataout; + nl11i11li <= wire_nl11i1Oli_dataout; + nl11i11ll <= wire_nl11i1Oll_dataout; + nl11i11lO <= wire_nl11i1OlO_dataout; + nl11i11Oi <= wire_nl11i1OOi_dataout; + nl11i11Ol <= wire_nl11i1OOl_dataout; + nl11i11OO <= wire_nl11i1OOO_dataout; + nl11iiOOi <= wire_nl11ilO1O_dataout; + nl11iiOOl <= wire_nl11ilO0i_dataout; + nl11iiOOO <= wire_nl11ilO0l_dataout; + nl11il00i <= wire_nl11iO1iO_dataout; + nl11il00l <= wire_nl11iO1li_dataout; + nl11il00O <= wire_nl11iO1ll_dataout; + nl11il01i <= wire_nl11iO10O_dataout; + nl11il01l <= wire_nl11iO1ii_dataout; + nl11il01O <= wire_nl11iO1il_dataout; + nl11il0ii <= wire_nl11iO1lO_dataout; + nl11il0il <= wire_nl11iO1Oi_dataout; + nl11il0iO <= wire_nl11iO1Ol_dataout; + nl11il0li <= wire_nl11iO1OO_dataout; + nl11il0ll <= wire_nl11iO01i_dataout; + nl11il0lO <= wire_nl11iO01l_dataout; + nl11il0Oi <= wire_nl11iO01O_dataout; + nl11il0Ol <= wire_nl11iO00i_dataout; + nl11il0OO <= wire_nl11iO00l_dataout; + nl11il10i <= wire_nl11ilOiO_dataout; + nl11il10l <= wire_nl11ilOli_dataout; + nl11il10O <= wire_nl11ilOll_dataout; + nl11il11i <= wire_nl11ilO0O_dataout; + nl11il11l <= wire_nl11ilOii_dataout; + nl11il11O <= wire_nl11ilOil_dataout; + nl11il1ii <= wire_nl11ilOlO_dataout; + nl11il1il <= wire_nl11ilOOi_dataout; + nl11il1iO <= wire_nl11ilOOl_dataout; + nl11il1li <= wire_nl11ilOOO_dataout; + nl11il1ll <= wire_nl11iO11i_dataout; + nl11il1lO <= wire_nl11iO11l_dataout; + nl11il1Oi <= wire_nl11iO11O_dataout; + nl11il1Ol <= wire_nl11iO10i_dataout; + nl11il1OO <= wire_nl11iO10l_dataout; + nl11ili0i <= wire_nl11iO0iO_dataout; + nl11ili0l <= wire_nl11iO0li_dataout; + nl11ili0O <= wire_nl11iO0ll_dataout; + nl11ili1i <= wire_nl11iO00O_dataout; + nl11ili1l <= wire_nl11iO0ii_dataout; + nl11ili1O <= wire_nl11iO0il_dataout; + nl11iliii <= wire_nl11iO0lO_dataout; + nl11iliil <= wire_nl11iO0Oi_dataout; + nl11iliiO <= wire_nl11iO0Ol_dataout; + nl11ilili <= wire_nl11iO0OO_dataout; + nl11ilill <= wire_nl11iOi1i_dataout; + nl11ililO <= wire_nl11iOi1l_dataout; + nl11iliOi <= wire_nl11iOi1O_dataout; + nl11iliOl <= wire_nl11iOi0i_dataout; + nl11iliOO <= wire_nl11iOi0l_dataout; + nl11ill0i <= wire_nl11iOiiO_dataout; + nl11ill0l <= wire_nl11iOili_dataout; + nl11ill0O <= wire_nl11iOill_dataout; + nl11ill1i <= wire_nl11iOi0O_dataout; + nl11ill1l <= wire_nl11iOiii_dataout; + nl11ill1O <= wire_nl11iOiil_dataout; + nl11illii <= wire_nl11iOilO_dataout; + nl11illil <= wire_nl11iOiOi_dataout; + nl11illiO <= wire_nl11iOiOl_dataout; + nl11illli <= wire_nl11iOiOO_dataout; + nl11illll <= wire_nl11iOl1i_dataout; + nl11illlO <= wire_nl11iOl1l_dataout; + nl11illOi <= wire_nl11iOl1O_dataout; + nl11illOl <= wire_nl11iOl0i_dataout; + nl11illOO <= wire_nl11iOl0l_dataout; + nl11ilO1i <= wire_nl11l0i1l_dataout; + nl11l000i <= wire_nl11li1iO_dataout; + nl11l000l <= wire_nl11li1li_dataout; + nl11l000O <= wire_nl11li1ll_dataout; + nl11l001i <= wire_nl11li10O_dataout; + nl11l001l <= wire_nl11li1ii_dataout; + nl11l001O <= wire_nl11li1il_dataout; + nl11l00ii <= wire_nl11li1lO_dataout; + nl11l00il <= wire_nl11li1Oi_dataout; + nl11l00iO <= wire_nl11li1Ol_dataout; + nl11l00li <= wire_nl11li1OO_dataout; + nl11l00ll <= wire_nl11li01i_dataout; + nl11l00lO <= wire_nl11li01l_dataout; + nl11l00Oi <= wire_nl11li01O_dataout; + nl11l00Ol <= wire_nl11li00i_dataout; + nl11l00OO <= wire_nl11li00l_dataout; + nl11l010i <= wire_nl11l0OiO_dataout; + nl11l010l <= wire_nl11l0Oli_dataout; + nl11l010O <= wire_nl11l0Oll_dataout; + nl11l011i <= wire_nl11l0O0O_dataout; + nl11l011l <= wire_nl11l0Oii_dataout; + nl11l011O <= wire_nl11l0Oil_dataout; + nl11l01ii <= wire_nl11l0OlO_dataout; + nl11l01il <= wire_nl11l0OOi_dataout; + nl11l01iO <= wire_nl11l0OOl_dataout; + nl11l01li <= wire_nl11l0OOO_dataout; + nl11l01ll <= wire_nl11li11i_dataout; + nl11l01lO <= wire_nl11li11l_dataout; + nl11l01Oi <= wire_nl11li11O_dataout; + nl11l01Ol <= wire_nl11li10i_dataout; + nl11l01OO <= wire_nl11li10l_dataout; + nl11l0i1i <= wire_nl11lOO0l_dataout; + nl11l1ili <= wire_nl11ilO1l_dataout; + nl11l1iOi <= wire_nl11l0i1O_dataout; + nl11l1iOl <= wire_nl11l0i0i_dataout; + nl11l1iOO <= wire_nl11l0i0l_dataout; + nl11l1l0i <= wire_nl11l0iiO_dataout; + nl11l1l0l <= wire_nl11l0ili_dataout; + nl11l1l0O <= wire_nl11l0ill_dataout; + nl11l1l1i <= wire_nl11l0i0O_dataout; + nl11l1l1l <= wire_nl11l0iii_dataout; + nl11l1l1O <= wire_nl11l0iil_dataout; + nl11l1lii <= wire_nl11l0ilO_dataout; + nl11l1lil <= wire_nl11l0iOi_dataout; + nl11l1liO <= wire_nl11l0iOl_dataout; + nl11l1lli <= wire_nl11l0iOO_dataout; + nl11l1lll <= wire_nl11l0l1i_dataout; + nl11l1llO <= wire_nl11l0l1l_dataout; + nl11l1lOi <= wire_nl11l0l1O_dataout; + nl11l1lOl <= wire_nl11l0l0i_dataout; + nl11l1lOO <= wire_nl11l0l0l_dataout; + nl11l1O0i <= wire_nl11l0liO_dataout; + nl11l1O0l <= wire_nl11l0lli_dataout; + nl11l1O0O <= wire_nl11l0lll_dataout; + nl11l1O1i <= wire_nl11l0l0O_dataout; + nl11l1O1l <= wire_nl11l0lii_dataout; + nl11l1O1O <= wire_nl11l0lil_dataout; + nl11l1Oii <= wire_nl11l0llO_dataout; + nl11l1Oil <= wire_nl11l0lOi_dataout; + nl11l1OiO <= wire_nl11l0lOl_dataout; + nl11l1Oli <= wire_nl11l0lOO_dataout; + nl11l1Oll <= wire_nl11l0O1i_dataout; + nl11l1OlO <= wire_nl11l0O1l_dataout; + nl11l1OOi <= wire_nl11l0O1O_dataout; + nl11l1OOl <= wire_nl11l0O0i_dataout; + nl11l1OOO <= wire_nl11l0O0l_dataout; + nl11lO00i <= wire_nl11O11iO_dataout; + nl11lO00l <= wire_nl11O11li_dataout; + nl11lO00O <= wire_nl11O11ll_dataout; + nl11lO01i <= wire_nl11O110O_dataout; + nl11lO01l <= wire_nl11O11ii_dataout; + nl11lO01O <= wire_nl11O11il_dataout; + nl11lO0ii <= wire_nl11O11lO_dataout; + nl11lO0il <= wire_nl11O11Oi_dataout; + nl11lO0iO <= wire_nl11O11Ol_dataout; + nl11lO0li <= wire_nl11O11OO_dataout; + nl11lO0ll <= wire_nl11O101i_dataout; + nl11lO0lO <= wire_nl11O101l_dataout; + nl11lO0Oi <= wire_nl11O101O_dataout; + nl11lO0Ol <= wire_nl11O100i_dataout; + nl11lO0OO <= wire_nl11O100l_dataout; + nl11lO10i <= wire_nl11lOOiO_dataout; + nl11lO10l <= wire_nl11lOOli_dataout; + nl11lO10O <= wire_nl11lOOll_dataout; + nl11lO11i <= wire_nl11lOO0O_dataout; + nl11lO11l <= wire_nl11lOOii_dataout; + nl11lO11O <= wire_nl11lOOil_dataout; + nl11lO1ii <= wire_nl11lOOlO_dataout; + nl11lO1il <= wire_nl11lOOOi_dataout; + nl11lO1iO <= wire_nl11lOOOl_dataout; + nl11lO1li <= wire_nl11lOOOO_dataout; + nl11lO1ll <= wire_nl11O111i_dataout; + nl11lO1lO <= wire_nl11O111l_dataout; + nl11lO1Oi <= wire_nl11O111O_dataout; + nl11lO1Ol <= wire_nl11O110i_dataout; + nl11lO1OO <= wire_nl11O110l_dataout; + nl11lOi0i <= wire_nl11O10iO_dataout; + nl11lOi0l <= wire_nl11O10li_dataout; + nl11lOi0O <= wire_nl11O10ll_dataout; + nl11lOi1i <= wire_nl11O100O_dataout; + nl11lOi1l <= wire_nl11O10ii_dataout; + nl11lOi1O <= wire_nl11O10il_dataout; + nl11lOiii <= wire_nl11O10lO_dataout; + nl11lOiil <= wire_nl11O10Oi_dataout; + nl11lOiiO <= wire_nl11O10Ol_dataout; + nl11lOili <= wire_nl11O10OO_dataout; + nl11lOill <= wire_nl11O1i1i_dataout; + nl11lOilO <= wire_nl11O1i1l_dataout; + nl11lOiOi <= wire_nl11O1i1O_dataout; + nl11lOiOl <= wire_nl11O1i0i_dataout; + nl11lOiOO <= wire_nl11O1i0l_dataout; + nl11lOl0i <= wire_nl11O1iiO_dataout; + nl11lOl0l <= wire_nl11O1ili_dataout; + nl11lOl0O <= wire_nl11O1ill_dataout; + nl11lOl1i <= wire_nl11O1i0O_dataout; + nl11lOl1l <= wire_nl11O1iii_dataout; + nl11lOl1O <= wire_nl11O1iil_dataout; + nl11lOlii <= wire_nl11O1ilO_dataout; + nl11lOlil <= wire_nl11O1iOi_dataout; + nl11lOliO <= wire_nl11O1iOl_dataout; + nl11lOlli <= wire_nl11O1iOO_dataout; + nl11lOlll <= wire_nl11O1l1i_dataout; + nl11lOllO <= wire_nl11O1l1l_dataout; + nl11lOlOi <= wire_nl11O1l1O_dataout; + nl11lOlOl <= wire_nl11O1l0i_dataout; + nl11lOlOO <= wire_nl11O1l0l_dataout; + nl11lOO0i <= wire_nl11Oiiii_dataout; + nl11lOO1i <= wire_nl11O1l0O_dataout; + nl11lOO1l <= wire_nl11O1lii_dataout; + nl11lOO1O <= wire_nl11O1lil_dataout; + nl11Oii0i <= wire_nl11Oiiil_dataout; + nl11Oii0l <= wire_nl11OiiiO_dataout; + nl11Oii0O <= wire_nl11Ol11l_dataout; + nl11OiliO <= wire_nl11Ol11O_dataout; + nl11Oilli <= wire_nl11Ol10i_dataout; + nl11Oilll <= wire_nl11Ol10l_dataout; + nl11OillO <= wire_nl11Ol10O_dataout; + nl11OilOi <= wire_nl11Ol1ii_dataout; + nl11OilOl <= wire_nl11Ol1il_dataout; + nl11OilOO <= wire_nl11Ol1iO_dataout; + nl11OiO0i <= wire_nl11Ol1Oi_dataout; + nl11OiO0l <= wire_nl11Ol1Ol_dataout; + nl11OiO0O <= wire_nl11Ol1OO_dataout; + nl11OiO1i <= wire_nl11Ol1li_dataout; + nl11OiO1l <= wire_nl11Ol1ll_dataout; + nl11OiO1O <= wire_nl11Ol1lO_dataout; + nl11OiOii <= wire_nl11Ol01i_dataout; + nl11OiOil <= wire_nl11Ol01l_dataout; + nl11OiOiO <= wire_nl11Ol01O_dataout; + nl11OiOli <= wire_nl11Ol00i_dataout; + nl11OiOll <= wire_nl11Ol00l_dataout; + nl11OiOlO <= wire_nl11Ol00O_dataout; + nl11OiOOi <= wire_nl11Ol0ii_dataout; + nl11OiOOl <= wire_nl11Ol0il_dataout; + nl11OiOOO <= wire_nl11Ol0iO_dataout; + nl11Ol11i <= wire_nl11OOOil_dataout; + nl11OO00i <= wire_nl11OOOiO_dataout; + nl11OO00l <= wire_nl11OOOli_dataout; + nl11OO00O <= wire_nl11OOOll_dataout; + nl11OO0il <= wire_nl11OOOOi_dataout; + nl11OO0iO <= wire_nl11OOOOl_dataout; + nl11OO0li <= wire_nl11OOOOO_dataout; + nl11OO0ll <= wire_nl101111i_dataout; + nl11OO0lO <= wire_nl101111l_dataout; + nl11OO0Oi <= wire_nl101111O_dataout; + nl11OO0Ol <= wire_nl101110i_dataout; + nl11OO0OO <= wire_nl101110l_dataout; + nl11OOi0i <= wire_nl10111iO_dataout; + nl11OOi0l <= wire_nl10111li_dataout; + nl11OOi0O <= wire_nl10111ll_dataout; + nl11OOi1i <= wire_nl101110O_dataout; + nl11OOi1l <= wire_nl10111ii_dataout; + nl11OOiii <= wire_nl10111lO_dataout; + nl11OOiil <= wire_nl10111Oi_dataout; + nl11OOiiO <= wire_nl10111Ol_dataout; + nl11OOili <= wire_nl10111OO_dataout; + nl11OOill <= wire_nl101101i_dataout; + nl11OOilO <= wire_nl101101l_dataout; + nl11OOiOi <= wire_nl101101O_dataout; + nl11OOiOl <= wire_nl101100i_dataout; + nl11OOiOO <= wire_nl101100l_dataout; + nl11OOl0i <= wire_nl10110iO_dataout; + nl11OOl0l <= wire_nl10110li_dataout; + nl11OOl0O <= wire_nl10110ll_dataout; + nl11OOl1i <= wire_nl101100O_dataout; + nl11OOl1l <= wire_nl10110ii_dataout; + nl11OOl1O <= wire_nl10110il_dataout; + nl11OOlii <= wire_nl10110lO_dataout; + nl11OOlil <= wire_nl10110Oi_dataout; + nl11OOliO <= wire_nl10110Ol_dataout; + nl11OOlli <= wire_nl10110OO_dataout; + nl11OOlll <= wire_nl1011i1i_dataout; + nl11OOllO <= wire_nl1011i1l_dataout; + nl11OOlOi <= wire_nl1011i1O_dataout; + nl11OOlOl <= wire_nl1011i0i_dataout; + nl11OOlOO <= wire_nl1011i0l_dataout; + nl11OOO0i <= wire_nl1011iiO_dataout; + nl11OOO0l <= wire_nl1011ili_dataout; + nl11OOO0O <= wire_nl1011ill_dataout; + nl11OOO1i <= wire_nl1011i0O_dataout; + nl11OOO1l <= wire_nl1011iii_dataout; + nl11OOO1O <= wire_nl1011iil_dataout; + nl11OOOii <= wire_nl10ii0lO_dataout; + nl1i0100i <= wire_nl1i0010l_dataout; + nl1i0100l <= wire_nl1i0010O_dataout; + nl1i0100O <= wire_nl1i001ii_dataout; + nl1i0101i <= wire_nl1i0011l_dataout; + nl1i0101l <= wire_nl1i0011O_dataout; + nl1i0101O <= wire_nl1i0010i_dataout; + nl1i010ii <= wire_nl1i001il_dataout; + nl1i010il <= wire_nl1i001iO_dataout; + nl1i010iO <= wire_nl1i001li_dataout; + nl1i0110i <= wire_nl1i01O0l_dataout; + nl1i0110l <= wire_nl1i01O0O_dataout; + nl1i0110O <= wire_nl1i01Oii_dataout; + nl1i0111i <= wire_nl1i01O1l_dataout; + nl1i0111l <= wire_nl1i01O1O_dataout; + nl1i0111O <= wire_nl1i01O0i_dataout; + nl1i011ii <= wire_nl1i01Oil_dataout; + nl1i011il <= wire_nl1i01OiO_dataout; + nl1i011iO <= wire_nl1i01Oli_dataout; + nl1i011li <= wire_nl1i01Oll_dataout; + nl1i011ll <= wire_nl1i01OlO_dataout; + nl1i011lO <= wire_nl1i01OOi_dataout; + nl1i011Oi <= wire_nl1i01OOl_dataout; + nl1i011Ol <= wire_nl1i01OOO_dataout; + nl1i011OO <= wire_nl1i0011i_dataout; + nl1i1000i <= wire_nl1i1i10l_dataout; + nl1i1000l <= wire_nl1i1i10O_dataout; + nl1i1000O <= wire_nl1i1i1ii_dataout; + nl1i1001i <= wire_nl1i1i11l_dataout; + nl1i1001l <= wire_nl1i1i11O_dataout; + nl1i1001O <= wire_nl1i1i10i_dataout; + nl1i100ii <= wire_nl1i1i1il_dataout; + nl1i100il <= wire_nl1i1i1iO_dataout; + nl1i100iO <= wire_nl1i1i1li_dataout; + nl1i100li <= wire_nl1i1i1ll_dataout; + nl1i100ll <= wire_nl1i1i1lO_dataout; + nl1i100lO <= wire_nl1i1i1Oi_dataout; + nl1i100Oi <= wire_nl1i1i1Ol_dataout; + nl1i100Ol <= wire_nl1i1i1OO_dataout; + nl1i100OO <= wire_nl1i1i01i_dataout; + nl1i1010i <= wire_nl1i10O0l_dataout; + nl1i1010l <= wire_nl1i10O0O_dataout; + nl1i1010O <= wire_nl1i10Oii_dataout; + nl1i1011i <= wire_nl1i10O1l_dataout; + nl1i1011l <= wire_nl1i10O1O_dataout; + nl1i1011O <= wire_nl1i10O0i_dataout; + nl1i101ii <= wire_nl1i10Oil_dataout; + nl1i101il <= wire_nl1i10OiO_dataout; + nl1i101iO <= wire_nl1i10Oli_dataout; + nl1i101li <= wire_nl1i10Oll_dataout; + nl1i101ll <= wire_nl1i10OlO_dataout; + nl1i101lO <= wire_nl1i10OOi_dataout; + nl1i101Oi <= wire_nl1i10OOl_dataout; + nl1i101Ol <= wire_nl1i10OOO_dataout; + nl1i101OO <= wire_nl1i1i11i_dataout; + nl1i10i0i <= wire_nl1i1i00l_dataout; + nl1i10i0l <= wire_nl1i1i00O_dataout; + nl1i10i0O <= wire_nl1i1i0ii_dataout; + nl1i10i1i <= wire_nl1i1i01l_dataout; + nl1i10i1l <= wire_nl1i1i01O_dataout; + nl1i10i1O <= wire_nl1i1i00i_dataout; + nl1i10iii <= wire_nl1i1i0il_dataout; + nl1i10iil <= wire_nl1i1i0iO_dataout; + nl1i10iiO <= wire_nl1i1i0li_dataout; + nl1i10ili <= wire_nl1i1i0ll_dataout; + nl1i10ill <= wire_nl1i1i0lO_dataout; + nl1i10ilO <= wire_nl1i1i0Oi_dataout; + nl1i10iOi <= wire_nl1i010li_dataout; + nl1i1101i <= wire_nl1i110il_dataout; + nl1i1101l <= wire_nl1i110iO_dataout; + nl1i1101O <= wire_nl1i10iOl_dataout; + nl1i111Oi <= wire_nl1i1100l_dataout; + nl1i111Ol <= wire_nl1i1100O_dataout; + nl1i111OO <= wire_nl1i110ii_dataout; + nl1i11lOl <= wire_nl1i10iOO_dataout; + nl1i11lOO <= wire_nl1i10l1i_dataout; + nl1i11O0i <= wire_nl1i10l0l_dataout; + nl1i11O0l <= wire_nl1i10l0O_dataout; + nl1i11O0O <= wire_nl1i10lii_dataout; + nl1i11O1i <= wire_nl1i10l1l_dataout; + nl1i11O1l <= wire_nl1i10l1O_dataout; + nl1i11O1O <= wire_nl1i10l0i_dataout; + nl1i11Oii <= wire_nl1i10lil_dataout; + nl1i11Oil <= wire_nl1i10liO_dataout; + nl1i11OiO <= wire_nl1i10lli_dataout; + nl1i11Oli <= wire_nl1i10lll_dataout; + nl1i11Oll <= wire_nl1i10llO_dataout; + nl1i11OlO <= wire_nl1i10lOi_dataout; + nl1i11OOi <= wire_nl1i10lOl_dataout; + nl1i11OOl <= wire_nl1i10lOO_dataout; + nl1i11OOO <= wire_nl1i10O1i_dataout; + nl1i1Oili <= wire_nl1i010ll_dataout; + nl1i1Oill <= wire_nl1i010lO_dataout; + nl1i1OilO <= wire_nl1i010Oi_dataout; + nl1i1OiOi <= wire_nl1i010Ol_dataout; + nl1i1OiOl <= wire_nl1i010OO_dataout; + nl1i1OiOO <= wire_nl1i01i1i_dataout; + nl1i1Ol0i <= wire_nl1i01i0l_dataout; + nl1i1Ol0l <= wire_nl1i01i0O_dataout; + nl1i1Ol0O <= wire_nl1i01iii_dataout; + nl1i1Ol1i <= wire_nl1i01i1l_dataout; + nl1i1Ol1l <= wire_nl1i01i1O_dataout; + nl1i1Ol1O <= wire_nl1i01i0i_dataout; + nl1i1Olii <= wire_nl1i01iil_dataout; + nl1i1Olil <= wire_nl1i01iiO_dataout; + nl1i1OliO <= wire_nl1i01ili_dataout; + nl1i1Olli <= wire_nl1i01ill_dataout; + nl1i1Olll <= wire_nl1i01ilO_dataout; + nl1i1OllO <= wire_nl1i01iOi_dataout; + nl1i1OlOi <= wire_nl1i01iOl_dataout; + nl1i1OlOl <= wire_nl1i01iOO_dataout; + nl1i1OlOO <= wire_nl1i01l1i_dataout; + nl1i1OO0i <= wire_nl1i01l0l_dataout; + nl1i1OO0l <= wire_nl1i01l0O_dataout; + nl1i1OO0O <= wire_nl1i01lii_dataout; + nl1i1OO1i <= wire_nl1i01l1l_dataout; + nl1i1OO1l <= wire_nl1i01l1O_dataout; + nl1i1OO1O <= wire_nl1i01l0i_dataout; + nl1i1OOii <= wire_nl1i01lil_dataout; + nl1i1OOil <= wire_nl1i01liO_dataout; + nl1i1OOiO <= wire_nl1i01lli_dataout; + nl1i1OOli <= wire_nl1i01lll_dataout; + nl1i1OOll <= wire_nl1i01llO_dataout; + nl1i1OOlO <= wire_nl1i01lOi_dataout; + nl1i1OOOi <= wire_nl1i01lOl_dataout; + nl1i1OOOl <= wire_nl1i01lOO_dataout; + nl1i1OOOO <= wire_nl1i01O1i_dataout; + nl1iil0Ol <= wire_nl1iiOiil_dataout; + nl1iil10O <= wire_nl1l0lOll_dataout; + nl1iiO0li <= wire_nl1iiOiiO_dataout; + nl1iiO0ll <= wire_nl1iiOili_dataout; + nl1iiO0lO <= wire_nl1iiOill_dataout; + nl1iiO0Oi <= wire_nl1iiOilO_dataout; + nl1iiO0Ol <= wire_nl1iiOiOi_dataout; + nl1iiO0OO <= wire_nl1iiOiOl_dataout; + nl1iiOi0i <= wire_nl1iiOl1O_dataout; + nl1iiOi0l <= wire_nl1iiOl0i_dataout; + nl1iiOi0O <= wire_nl1iiOl0l_dataout; + nl1iiOi1i <= wire_nl1iiOiOO_dataout; + nl1iiOi1l <= wire_nl1iiOl1i_dataout; + nl1iiOi1O <= wire_nl1iiOl1l_dataout; + nl1iiOiii <= wire_nl1il1l1i_dataout; + nl1il1i0i <= wire_nl1il1l0i_dataout; + nl1il1i0l <= wire_nl1il1l0l_dataout; + nl1il1i0O <= wire_nl1il1l0O_dataout; + nl1il1i1l <= wire_nl1il1l1l_dataout; + nl1il1i1O <= wire_nl1il1l1O_dataout; + nl1il1iii <= wire_nl1il1lii_dataout; + nl1il1iil <= wire_nl1il00il_dataout; + nl1il1iiO <= wire_nl1il111l_dataout; + nl1il1ili <= wire_nl1iiOlil_dataout; + nl1il1ill <= wire_nl1iiO1il_dataout; + nl1il1ilO <= wire_nl1iili1i_dataout; + nl1il1iOi <= wire_nl1iil0ii_dataout; + nl1il1iOl <= wire_nl1iil1Ol_dataout; + nl1il1iOO <= wire_nl1iil10l_dataout; + nl1l0000i <= wire_nl1li0ilO_dataout; + nl1l0000l <= wire_nl1li0iOi_dataout; + nl1l0000O <= wire_nl1li0iOl_dataout; + nl1l0001i <= wire_nl1li0iiO_dataout; + nl1l0001l <= wire_nl1li0ili_dataout; + nl1l0001O <= wire_nl1li0ill_dataout; + nl1l000ii <= wire_nl1li0iOO_dataout; + nl1l000il <= wire_nl1li0l1i_dataout; + nl1l000iO <= wire_nl1li0l1l_dataout; + nl1l000li <= wire_nl1li0l1O_dataout; + nl1l000ll <= wire_nl1li0l0i_dataout; + nl1l000lO <= wire_nl1li0l0l_dataout; + nl1l000Oi <= wire_nl1liiOlO_dataout; + nl1l000Ol <= wire_nl1liiOOi_dataout; + nl1l000OO <= wire_nl1liiOOl_dataout; + nl1l0010i <= wire_nl1li00lO_dataout; + nl1l0010l <= wire_nl1li00Oi_dataout; + nl1l0010O <= wire_nl1li00Ol_dataout; + nl1l0011i <= wire_nl1li00iO_dataout; + nl1l0011l <= wire_nl1li00li_dataout; + nl1l0011O <= wire_nl1li00ll_dataout; + nl1l001ii <= wire_nl1li00OO_dataout; + nl1l001il <= wire_nl1li0i1i_dataout; + nl1l001iO <= wire_nl1li0i1l_dataout; + nl1l001li <= wire_nl1li0i1O_dataout; + nl1l001ll <= wire_nl1li0i0i_dataout; + nl1l001lO <= wire_nl1li0i0l_dataout; + nl1l001Oi <= wire_nl1li0i0O_dataout; + nl1l001Ol <= wire_nl1li0iii_dataout; + nl1l001OO <= wire_nl1li0iil_dataout; + nl1l00i0i <= wire_nl1lil11O_dataout; + nl1l00i0l <= wire_nl1lil10i_dataout; + nl1l00i0O <= wire_nl1lil10l_dataout; + nl1l00i1i <= wire_nl1liiOOO_dataout; + nl1l00i1l <= wire_nl1lil11i_dataout; + nl1l00i1O <= wire_nl1lil11l_dataout; + nl1l00iii <= wire_nl1lil10O_dataout; + nl1l00iil <= wire_nl1lil1ii_dataout; + nl1l00iiO <= wire_nl1lil1il_dataout; + nl1l00ili <= wire_nl1lil1iO_dataout; + nl1l00ill <= wire_nl1lil1li_dataout; + nl1l00ilO <= wire_nl1lil1ll_dataout; + nl1l00iOi <= wire_nl1lil1lO_dataout; + nl1l00iOl <= wire_nl1lil1Oi_dataout; + nl1l00iOO <= wire_nl1lil1Ol_dataout; + nl1l00l0i <= wire_nl1lil01O_dataout; + nl1l00l0l <= wire_nl1lil00i_dataout; + nl1l00l0O <= wire_nl1lil00l_dataout; + nl1l00l1i <= wire_nl1lil1OO_dataout; + nl1l00l1l <= wire_nl1lil01i_dataout; + nl1l00l1O <= wire_nl1lil01l_dataout; + nl1l00lii <= wire_nl1lil00O_dataout; + nl1l00lil <= wire_nl1lil0ii_dataout; + nl1l00liO <= wire_nl1lil0il_dataout; + nl1l00lli <= wire_nl1lil0iO_dataout; + nl1l00lll <= wire_nl1lil0li_dataout; + nl1l00llO <= wire_nl1lil0ll_dataout; + nl1l00lOi <= wire_nl1lil0lO_dataout; + nl1l00lOl <= wire_nl1lil0Oi_dataout; + nl1l00lOO <= wire_nl1lii1il_dataout; + nl1l00O0i <= wire_nl1lii1lO_dataout; + nl1l00O0l <= wire_nl1lii1Oi_dataout; + nl1l00O0O <= wire_nl1lii1Ol_dataout; + nl1l00O1i <= wire_nl1lii1iO_dataout; + nl1l00O1l <= wire_nl1lii1li_dataout; + nl1l00O1O <= wire_nl1lii1ll_dataout; + nl1l00Oii <= wire_nl1lii1OO_dataout; + nl1l00Oil <= wire_nl1lii01i_dataout; + nl1l00OiO <= wire_nl1lii01l_dataout; + nl1l00Oli <= wire_nl1lii01O_dataout; + nl1l00Oll <= wire_nl1lii00i_dataout; + nl1l00OlO <= wire_nl1lii00l_dataout; + nl1l00OOi <= wire_nl1lii00O_dataout; + nl1l00OOl <= wire_nl1lii0ii_dataout; + nl1l00OOO <= wire_nl1lii0il_dataout; + nl1l0100i <= wire_nl1li0i1i_dataout; + nl1l0100l <= wire_nl1li0i1l_dataout; + nl1l0100O <= wire_nl1li0i1O_dataout; + nl1l0101i <= wire_nl1li00Oi_dataout; + nl1l0101l <= wire_nl1li00Ol_dataout; + nl1l0101O <= wire_nl1li00OO_dataout; + nl1l010ii <= wire_nl1li0i0i_dataout; + nl1l010il <= wire_nl1li0i0l_dataout; + nl1l010iO <= wire_nl1li0i0O_dataout; + nl1l010li <= wire_nl1li0iii_dataout; + nl1l010ll <= wire_nl1li0iil_dataout; + nl1l010lO <= wire_nl1li0iiO_dataout; + nl1l010Oi <= wire_nl1li0ili_dataout; + nl1l010Ol <= wire_nl1li0ill_dataout; + nl1l010OO <= wire_nl1li0ilO_dataout; + nl1l0110i <= wire_nl1li001i_dataout; + nl1l0110l <= wire_nl1li001l_dataout; + nl1l0110O <= wire_nl1li001O_dataout; + nl1l0111i <= wire_nl1li01Oi_dataout; + nl1l0111l <= wire_nl1li01Ol_dataout; + nl1l0111O <= wire_nl1li01OO_dataout; + nl1l011ii <= wire_nl1li000i_dataout; + nl1l011il <= wire_nl1li000l_dataout; + nl1l011iO <= wire_nl1li000O_dataout; + nl1l011li <= wire_nl1li00ii_dataout; + nl1l011ll <= wire_nl1li00il_dataout; + nl1l011lO <= wire_nl1li00iO_dataout; + nl1l011Oi <= wire_nl1li00li_dataout; + nl1l011Ol <= wire_nl1li00ll_dataout; + nl1l011OO <= wire_nl1li00lO_dataout; + nl1l01i0i <= wire_nl1li0l1i_dataout; + nl1l01i0l <= wire_nl1li0l1l_dataout; + nl1l01i0O <= wire_nl1li0l1O_dataout; + nl1l01i1i <= wire_nl1li0iOi_dataout; + nl1l01i1l <= wire_nl1li0iOl_dataout; + nl1l01i1O <= wire_nl1li0iOO_dataout; + nl1l01iii <= wire_nl1li0l0i_dataout; + nl1l01iil <= wire_nl1li0l0l_dataout; + nl1l01iiO <= wire_nl1li000i_dataout; + nl1l01ili <= wire_nl1li000l_dataout; + nl1l01ill <= wire_nl1li000O_dataout; + nl1l01ilO <= wire_nl1li00ii_dataout; + nl1l01iOi <= wire_nl1li00il_dataout; + nl1l01iOl <= wire_nl1li00iO_dataout; + nl1l01iOO <= wire_nl1li00li_dataout; + nl1l01l0i <= wire_nl1li00Ol_dataout; + nl1l01l0l <= wire_nl1li00OO_dataout; + nl1l01l0O <= wire_nl1li0i1i_dataout; + nl1l01l1i <= wire_nl1li00ll_dataout; + nl1l01l1l <= wire_nl1li00lO_dataout; + nl1l01l1O <= wire_nl1li00Oi_dataout; + nl1l01lii <= wire_nl1li0i1l_dataout; + nl1l01lil <= wire_nl1li0i1O_dataout; + nl1l01liO <= wire_nl1li0i0i_dataout; + nl1l01lli <= wire_nl1li0i0l_dataout; + nl1l01lll <= wire_nl1li0i0O_dataout; + nl1l01llO <= wire_nl1li0iii_dataout; + nl1l01lOi <= wire_nl1li0iil_dataout; + nl1l01lOl <= wire_nl1li0iiO_dataout; + nl1l01lOO <= wire_nl1li0ili_dataout; + nl1l01O0i <= wire_nl1li0iOl_dataout; + nl1l01O0l <= wire_nl1li0iOO_dataout; + nl1l01O0O <= wire_nl1li0l1i_dataout; + nl1l01O1i <= wire_nl1li0ill_dataout; + nl1l01O1l <= wire_nl1li0ilO_dataout; + nl1l01O1O <= wire_nl1li0iOi_dataout; + nl1l01Oii <= wire_nl1li0l1l_dataout; + nl1l01Oil <= wire_nl1li0l1O_dataout; + nl1l01OiO <= wire_nl1li0l0i_dataout; + nl1l01Oli <= wire_nl1li0l0l_dataout; + nl1l01Oll <= wire_nl1li000i_dataout; + nl1l01OlO <= wire_nl1li000l_dataout; + nl1l01OOi <= wire_nl1li000O_dataout; + nl1l01OOl <= wire_nl1li00ii_dataout; + nl1l01OOO <= wire_nl1li00il_dataout; + nl1l0i00i <= wire_nl1liiilO_dataout; + nl1l0i00l <= wire_nl1liiiOi_dataout; + nl1l0i00O <= wire_nl1liiiOl_dataout; + nl1l0i01i <= wire_nl1liiiiO_dataout; + nl1l0i01l <= wire_nl1liiili_dataout; + nl1l0i01O <= wire_nl1liiill_dataout; + nl1l0i0ii <= wire_nl1liiiOO_dataout; + nl1l0i0il <= wire_nl1liil1i_dataout; + nl1l0i0iO <= wire_nl1liil1l_dataout; + nl1l0i0li <= wire_nl1liil1O_dataout; + nl1l0i0ll <= wire_nl1liil0i_dataout; + nl1l0i0lO <= wire_nl1liil0l_dataout; + nl1l0i0Oi <= wire_nl1liil0O_dataout; + nl1l0i0Ol <= wire_nl1liilii_dataout; + nl1l0i0OO <= wire_nl1liilil_dataout; + nl1l0i10i <= wire_nl1lii0lO_dataout; + nl1l0i10l <= wire_nl1lii0Oi_dataout; + nl1l0i10O <= wire_nl1lii0Ol_dataout; + nl1l0i11i <= wire_nl1lii0iO_dataout; + nl1l0i11l <= wire_nl1lii0li_dataout; + nl1l0i11O <= wire_nl1lii0ll_dataout; + nl1l0i1ii <= wire_nl1lii0OO_dataout; + nl1l0i1il <= wire_nl1liii1i_dataout; + nl1l0i1iO <= wire_nl1liii1l_dataout; + nl1l0i1li <= wire_nl1liii1O_dataout; + nl1l0i1ll <= wire_nl1liii0i_dataout; + nl1l0i1lO <= wire_nl1liii0l_dataout; + nl1l0i1Oi <= wire_nl1liii0O_dataout; + nl1l0i1Ol <= wire_nl1liiiii_dataout; + nl1l0i1OO <= wire_nl1liiiil_dataout; + nl1l0ii0i <= wire_nl1liillO_dataout; + nl1l0ii0l <= wire_nl1liilOi_dataout; + nl1l0ii0O <= wire_nl1liilOl_dataout; + nl1l0ii1i <= wire_nl1liiliO_dataout; + nl1l0ii1l <= wire_nl1liilli_dataout; + nl1l0ii1O <= wire_nl1liilll_dataout; + nl1l0iiii <= wire_nl1liilOO_dataout; + nl1l0iiil <= wire_nl1liiO1i_dataout; + nl1l0iiiO <= wire_nl1liiO1l_dataout; + nl1l0iili <= wire_nl1liiO1O_dataout; + nl1l0iill <= wire_nl1liiO0i_dataout; + nl1l0iilO <= wire_nl1liiO0l_dataout; + nl1l0iiOi <= wire_nl1liiO0O_dataout; + nl1l0iiOl <= wire_nl1liiOii_dataout; + nl1l0iiOO <= wire_nl1liiOil_dataout; + nl1l0il0i <= wire_nl1li0l0O_dataout; + nl1l0il0l <= wire_nl1li0lii_dataout; + nl1l0il0O <= wire_nl1li0lil_dataout; + nl1l0il1i <= wire_nl1liiOiO_dataout; + nl1l0il1l <= wire_nl1liiOli_dataout; + nl1l0il1O <= wire_nl1liiOll_dataout; + nl1l0ilii <= wire_nl1li0liO_dataout; + nl1l0ilil <= wire_nl1li0lli_dataout; + nl1l0iliO <= wire_nl1li0lll_dataout; + nl1l0illi <= wire_nl1li0llO_dataout; + nl1l0illl <= wire_nl1li0lOi_dataout; + nl1l0illO <= wire_nl1li0lOl_dataout; + nl1l0ilOi <= wire_nl1li0lOO_dataout; + nl1l0ilOl <= wire_nl1li0O1i_dataout; + nl1l0ilOO <= wire_nl1li0O1l_dataout; + nl1l0iO0i <= wire_nl1li0O0O_dataout; + nl1l0iO0l <= wire_nl1li0Oii_dataout; + nl1l0iO0O <= wire_nl1li0Oil_dataout; + nl1l0iO1i <= wire_nl1li0O1O_dataout; + nl1l0iO1l <= wire_nl1li0O0i_dataout; + nl1l0iO1O <= wire_nl1li0O0l_dataout; + nl1l0iOii <= wire_nl1li0OiO_dataout; + nl1l0iOil <= wire_nl1li0Oli_dataout; + nl1l0iOiO <= wire_nl1li0Oll_dataout; + nl1l0iOli <= wire_nl1li0OlO_dataout; + nl1l0iOll <= wire_nl1li0OOi_dataout; + nl1l0iOlO <= wire_nl1li0OOl_dataout; + nl1l0iOOi <= wire_nl1li0OOO_dataout; + nl1l0iOOl <= wire_nl1lii11i_dataout; + nl1l0iOOO <= wire_nl1lii11l_dataout; + nl1l0l00i <= dout_rcv0(53); + nl1l0l00l <= dout_rcv0(54); + nl1l0l00O <= dout_rcv0(55); + nl1l0l01i <= dout_rcv0(50); + nl1l0l01l <= dout_rcv0(51); + nl1l0l01O <= dout_rcv0(52); + nl1l0l0ii <= dout_rcv0(40); + nl1l0l0il <= dout_rcv0(41); + nl1l0l0iO <= dout_rcv0(42); + nl1l0l0li <= dout_rcv0(43); + nl1l0l0ll <= dout_rcv0(44); + nl1l0l0lO <= dout_rcv0(45); + nl1l0l0Oi <= dout_rcv0(46); + nl1l0l0Ol <= dout_rcv0(47); + nl1l0l0OO <= dout_rcv0(32); + nl1l0l10i <= wire_nl1lii10O_dataout; + nl1l0l10l <= wire_nl1lii1ii_dataout; + nl1l0l10O <= dout_rcv0(56); + nl1l0l11i <= wire_nl1lii11O_dataout; + nl1l0l11l <= wire_nl1lii10i_dataout; + nl1l0l11O <= wire_nl1lii10l_dataout; + nl1l0l1ii <= dout_rcv0(57); + nl1l0l1il <= dout_rcv0(58); + nl1l0l1iO <= dout_rcv0(59); + nl1l0l1li <= dout_rcv0(60); + nl1l0l1ll <= dout_rcv0(61); + nl1l0l1lO <= dout_rcv0(62); + nl1l0l1Oi <= dout_rcv0(63); + nl1l0l1Ol <= dout_rcv0(48); + nl1l0l1OO <= dout_rcv0(49); + nl1l0li0i <= dout_rcv0(36); + nl1l0li0l <= dout_rcv0(37); + nl1l0li0O <= dout_rcv0(38); + nl1l0li1i <= dout_rcv0(33); + nl1l0li1l <= dout_rcv0(34); + nl1l0li1O <= dout_rcv0(35); + nl1l0liii <= dout_rcv0(39); + nl1l0liil <= dout_rcv0(24); + nl1l0liiO <= dout_rcv0(25); + nl1l0lili <= dout_rcv0(26); + nl1l0lill <= dout_rcv0(27); + nl1l0lilO <= dout_rcv0(28); + nl1l0liOi <= dout_rcv0(29); + nl1l0liOl <= dout_rcv0(30); + nl1l0liOO <= dout_rcv0(31); + nl1l0ll0i <= dout_rcv0(19); + nl1l0ll0l <= dout_rcv0(20); + nl1l0ll0O <= dout_rcv0(21); + nl1l0ll1i <= dout_rcv0(16); + nl1l0ll1l <= dout_rcv0(17); + nl1l0ll1O <= dout_rcv0(18); + nl1l0llii <= dout_rcv0(22); + nl1l0llil <= dout_rcv0(23); + nl1l0lliO <= dout_rcv0(8); + nl1l0llli <= dout_rcv0(9); + nl1l0llll <= dout_rcv0(10); + nl1l0lllO <= dout_rcv0(11); + nl1l0llOi <= dout_rcv0(12); + nl1l0llOl <= dout_rcv0(13); + nl1l0llOO <= dout_rcv0(14); + nl1l0lO0i <= dout_rcv0(2); + nl1l0lO0l <= dout_rcv0(3); + nl1l0lO0O <= dout_rcv0(4); + nl1l0lO1i <= dout_rcv0(15); + nl1l0lO1l <= dout_rcv0(0); + nl1l0lO1O <= dout_rcv0(1); + nl1l0lOii <= dout_rcv0(5); + nl1l0lOil <= dout_rcv0(6); + nl1l0lOiO <= dout_rcv0(7); + nl1l0lOli <= wire_nl1ll0O1i_dataout; + nl1l1ilOO <= wire_nl1l0lOlO_dataout; + nl1l1iO0i <= wire_nl1l0O11i_dataout; + nl1l1iO0l <= wire_nl1l0O11l_dataout; + nl1l1iO1i <= wire_nl1l0lOOi_dataout; + nl1l1iO1l <= wire_nl1l0lOOl_dataout; + nl1l1iO1O <= wire_nl1l0lOOO_dataout; + nl1l1iOii <= wire_nl1l0O10i_dataout; + nl1l1iOil <= wire_nl1l0O10l_dataout; + nl1l1iOiO <= wire_nl1l0O10O_dataout; + nl1l1iOli <= wire_nl1l0O1ii_dataout; + nl1l1iOlO <= wire_nl1l0O1iO_dataout; + nl1l1iOOi <= wire_nl1l0O1li_dataout; + nl1l1iOOl <= wire_nl1l0O1ll_dataout; + nl1l1iOOO <= wire_nl1l0O1lO_dataout; + nl1l1l00i <= wire_nl1l0Oi1i_dataout; + nl1l1l00l <= wire_nl1l0Oi1l_dataout; + nl1l1l00O <= wire_nl1l0Oi1O_dataout; + nl1l1l01i <= wire_nl1l0O0Oi_dataout; + nl1l1l01l <= wire_nl1l0O0Ol_dataout; + nl1l1l01O <= wire_nl1l0O0OO_dataout; + nl1l1l0ii <= wire_nl1l0Oi0i_dataout; + nl1l1l0il <= wire_nl1l0Oi0l_dataout; + nl1l1l0iO <= wire_nl1l0Oi0O_dataout; + nl1l1l0li <= wire_nl1l0Oiii_dataout; + nl1l1l0ll <= wire_nl1l0Oiil_dataout; + nl1l1l0lO <= wire_nl1l0OiiO_dataout; + nl1l1l0Oi <= wire_nl1l0Oili_dataout; + nl1l1l0Ol <= wire_nl1l0Oill_dataout; + nl1l1l0OO <= wire_nl1l0OilO_dataout; + nl1l1l10i <= wire_nl1l0O01i_dataout; + nl1l1l10l <= wire_nl1l0O01l_dataout; + nl1l1l10O <= wire_nl1l0O01O_dataout; + nl1l1l11i <= wire_nl1l0O1Oi_dataout; + nl1l1l11l <= wire_nl1l0O1Ol_dataout; + nl1l1l11O <= wire_nl1l0O1OO_dataout; + nl1l1l1ii <= wire_nl1l0O00i_dataout; + nl1l1l1il <= wire_nl1l0O00l_dataout; + nl1l1l1iO <= wire_nl1l0O00O_dataout; + nl1l1l1li <= wire_nl1l0O0ii_dataout; + nl1l1l1ll <= wire_nl1l0O0il_dataout; + nl1l1l1lO <= wire_nl1l0O0iO_dataout; + nl1l1l1Oi <= wire_nl1l0O0li_dataout; + nl1l1l1Ol <= wire_nl1l0O0ll_dataout; + nl1l1l1OO <= wire_nl1l0O0lO_dataout; + nl1l1li0i <= wire_nl1l0Ol1i_dataout; + nl1l1li0l <= wire_nl1l0Ol1l_dataout; + nl1l1li0O <= wire_nl1l0Ol1O_dataout; + nl1l1li1i <= wire_nl1l0OiOi_dataout; + nl1l1li1l <= wire_nl1l0OiOl_dataout; + nl1l1li1O <= wire_nl1l0OiOO_dataout; + nl1l1liii <= wire_nl1l0Ol0i_dataout; + nl1l1liil <= wire_nl1l0Ol0l_dataout; + nl1l1liiO <= wire_nl1l0Ol0O_dataout; + nl1l1lili <= wire_nl1l0Olii_dataout; + nl1l1lill <= wire_nl1l0Olil_dataout; + nl1l1lilO <= wire_nl1l0OliO_dataout; + nl1l1liOi <= wire_nl1l0Olli_dataout; + nl1l1liOl <= wire_nl1l0Olll_dataout; + nl1l1liOO <= wire_nl1l0OllO_dataout; + nl1l1ll0i <= wire_nl1l0OO1i_dataout; + nl1l1ll0l <= wire_nl1l0OO1l_dataout; + nl1l1ll0O <= wire_nl1l0OO1O_dataout; + nl1l1ll1i <= wire_nl1l0OlOi_dataout; + nl1l1ll1l <= wire_nl1l0OlOl_dataout; + nl1l1ll1O <= wire_nl1l0OlOO_dataout; + nl1l1llii <= wire_nl1l0OO0i_dataout; + nl1l1llil <= wire_nl1l0OO0l_dataout; + nl1l1lliO <= wire_nl1l0OO0O_dataout; + nl1l1llli <= wire_nl1l0OOii_dataout; + nl1l1llll <= wire_nl1l0OOil_dataout; + nl1l1lllO <= wire_nl1l0OOiO_dataout; + nl1l1llOi <= wire_nl1l0OOli_dataout; + nl1l1llOl <= wire_nl1l0OOll_dataout; + nl1l1llOO <= wire_nl1l0OOlO_dataout; + nl1l1lO0i <= wire_nl1li111i_dataout; + nl1l1lO0l <= wire_nl1li111l_dataout; + nl1l1lO0O <= wire_nl1li111O_dataout; + nl1l1lO1i <= wire_nl1l0OOOi_dataout; + nl1l1lO1l <= wire_nl1l0OOOl_dataout; + nl1l1lO1O <= wire_nl1l0OOOO_dataout; + nl1l1lOii <= wire_nl1li110i_dataout; + nl1l1lOil <= wire_nl1li110l_dataout; + nl1l1lOiO <= wire_nl1li110O_dataout; + nl1l1lOli <= wire_nl1li11ii_dataout; + nl1l1lOll <= wire_nl1li11il_dataout; + nl1l1lOlO <= wire_nl1li11iO_dataout; + nl1l1lOOi <= wire_nl1li11li_dataout; + nl1l1lOOl <= wire_nl1li11ll_dataout; + nl1l1lOOO <= wire_nl1li11lO_dataout; + nl1l1O00i <= wire_nl1li1i1i_dataout; + nl1l1O00l <= wire_nl1li1i1l_dataout; + nl1l1O00O <= wire_nl1li1i1O_dataout; + nl1l1O01i <= wire_nl1li10Oi_dataout; + nl1l1O01l <= wire_nl1li10Ol_dataout; + nl1l1O01O <= wire_nl1li10OO_dataout; + nl1l1O0ii <= wire_nl1li1i0i_dataout; + nl1l1O0il <= wire_nl1li1i0l_dataout; + nl1l1O0iO <= wire_nl1li1i0O_dataout; + nl1l1O0li <= wire_nl1li1iii_dataout; + nl1l1O0ll <= wire_nl1li1iil_dataout; + nl1l1O0lO <= wire_nl1li1iiO_dataout; + nl1l1O0Oi <= wire_nl1li1ili_dataout; + nl1l1O0Ol <= wire_nl1li1ill_dataout; + nl1l1O0OO <= wire_nl1li1ilO_dataout; + nl1l1O10i <= wire_nl1li101i_dataout; + nl1l1O10l <= wire_nl1li101l_dataout; + nl1l1O10O <= wire_nl1li101O_dataout; + nl1l1O11i <= wire_nl1li11Oi_dataout; + nl1l1O11l <= wire_nl1li11Ol_dataout; + nl1l1O11O <= wire_nl1li11OO_dataout; + nl1l1O1ii <= wire_nl1li100i_dataout; + nl1l1O1il <= wire_nl1li100l_dataout; + nl1l1O1iO <= wire_nl1li100O_dataout; + nl1l1O1li <= wire_nl1li10ii_dataout; + nl1l1O1ll <= wire_nl1li10il_dataout; + nl1l1O1lO <= wire_nl1li10iO_dataout; + nl1l1O1Oi <= wire_nl1li10li_dataout; + nl1l1O1Ol <= wire_nl1li10ll_dataout; + nl1l1O1OO <= wire_nl1li10lO_dataout; + nl1l1Oi0i <= wire_nl1li1l1i_dataout; + nl1l1Oi0l <= wire_nl1li1l1l_dataout; + nl1l1Oi0O <= wire_nl1li1l1O_dataout; + nl1l1Oi1i <= wire_nl1li1iOi_dataout; + nl1l1Oi1l <= wire_nl1li1iOl_dataout; + nl1l1Oi1O <= wire_nl1li1iOO_dataout; + nl1l1Oiii <= wire_nl1li1l0i_dataout; + nl1l1Oiil <= wire_nl1li1l0l_dataout; + nl1l1OiiO <= wire_nl1li1l0O_dataout; + nl1l1Oili <= wire_nl1li1lii_dataout; + nl1l1Oill <= wire_nl1li1lil_dataout; + nl1l1OilO <= wire_nl1li1liO_dataout; + nl1l1OiOi <= wire_nl1li1lli_dataout; + nl1l1OiOl <= wire_nl1li1lll_dataout; + nl1l1OiOO <= wire_nl1li1llO_dataout; + nl1l1Ol0i <= wire_nl1li1O1i_dataout; + nl1l1Ol0l <= wire_nl1li1O1l_dataout; + nl1l1Ol0O <= wire_nl1li1O1O_dataout; + nl1l1Ol1i <= wire_nl1li1lOi_dataout; + nl1l1Ol1l <= wire_nl1li1lOl_dataout; + nl1l1Ol1O <= wire_nl1li1lOO_dataout; + nl1l1Olii <= wire_nl1li1O0i_dataout; + nl1l1Olil <= wire_nl1li1O0l_dataout; + nl1l1OliO <= wire_nl1li1O0O_dataout; + nl1l1Olli <= wire_nl1li1Oii_dataout; + nl1l1Olll <= wire_nl1li1Oil_dataout; + nl1l1OllO <= wire_nl1li1OiO_dataout; + nl1l1OlOi <= wire_nl1li1Oli_dataout; + nl1l1OlOl <= wire_nl1li1Oll_dataout; + nl1l1OlOO <= wire_nl1li1OlO_dataout; + nl1l1OO0i <= wire_nl1li011i_dataout; + nl1l1OO0l <= wire_nl1li011l_dataout; + nl1l1OO0O <= wire_nl1li011O_dataout; + nl1l1OO1i <= wire_nl1li1OOi_dataout; + nl1l1OO1l <= wire_nl1li1OOl_dataout; + nl1l1OO1O <= wire_nl1li1OOO_dataout; + nl1l1OOii <= wire_nl1li010i_dataout; + nl1l1OOil <= wire_nl1li010l_dataout; + nl1l1OOiO <= wire_nl1li010O_dataout; + nl1l1OOli <= wire_nl1li01ii_dataout; + nl1l1OOll <= wire_nl1li01il_dataout; + nl1l1OOlO <= wire_nl1li01iO_dataout; + nl1l1OOOi <= wire_nl1li01li_dataout; + nl1l1OOOl <= wire_nl1li01ll_dataout; + nl1l1OOOO <= wire_nl1li01lO_dataout; + nl1ll0iil <= wire_nl1ll0O1l_dataout; + nl1ll0iiO <= wire_nl1ll0O1O_dataout; + nl1ll0ili <= wire_nl1ll0O0i_dataout; + nl1ll0ill <= wire_nl1ll0O0l_dataout; + nl1ll0ilO <= wire_nl1ll0O0O_dataout; + nl1ll0iOi <= wire_nl1ll0Oii_dataout; + nl1ll0iOl <= wire_nl1ll0Oil_dataout; + nl1ll0l0i <= wire_nl1ll0OOi_dataout; + nl1ll0l0l <= wire_nl1ll0OOl_dataout; + nl1ll0l0O <= wire_nl1ll0OOO_dataout; + nl1ll0l1i <= wire_nl1ll0Oli_dataout; + nl1ll0l1l <= wire_nl1ll0Oll_dataout; + nl1ll0l1O <= wire_nl1ll0OlO_dataout; + nl1ll0lii <= wire_nl1lli11i_dataout; + nl1ll0lil <= wire_nl1lli11l_dataout; + nl1ll0liO <= wire_nl1lli11O_dataout; + nl1ll0lli <= wire_nl1lli10i_dataout; + nl1ll0lll <= wire_nl1lli10l_dataout; + nl1ll0llO <= wire_nl1lli10O_dataout; + nl1ll0lOi <= wire_nl1lli1ii_dataout; + nl1ll0lOl <= wire_nl1lli1il_dataout; + nl1ll0lOO <= wire_nl1lO1ili_dataout; + nl1lO1iiO <= wire_nl1lO1iOi_dataout; + nl1lO1ilO <= wire_nl1O0iiil_dataout; + nl1O0000i <= wire_nl1Oi1iiO_dataout; + nl1O0000l <= wire_nl1Oi1ili_dataout; + nl1O0000O <= wire_nl1Oi1ill_dataout; + nl1O0001i <= wire_nl1Oi1i0O_dataout; + nl1O0001l <= wire_nl1Oi1iii_dataout; + nl1O0001O <= wire_nl1Oi1iil_dataout; + nl1O000ii <= wire_nl1Oi1ilO_dataout; + nl1O000il <= wire_nl1Oi1iOi_dataout; + nl1O000iO <= wire_nl1Oi1iOl_dataout; + nl1O000li <= wire_nl1Oi1iOO_dataout; + nl1O000ll <= wire_nl1Oi1l1i_dataout; + nl1O000lO <= wire_nl1Oi1l1l_dataout; + nl1O000Oi <= wire_nl1Oi1l1O_dataout; + nl1O000Ol <= wire_nl1Oi1l0i_dataout; + nl1O000OO <= wire_nl1Oi1l0l_dataout; + nl1O0010i <= wire_nl1Oi10iO_dataout; + nl1O0010l <= wire_nl1Oi10li_dataout; + nl1O0010O <= wire_nl1Oi10ll_dataout; + nl1O0011i <= wire_nl1Oi100O_dataout; + nl1O0011l <= wire_nl1Oi10ii_dataout; + nl1O0011O <= wire_nl1Oi10il_dataout; + nl1O001ii <= wire_nl1Oi10lO_dataout; + nl1O001il <= wire_nl1Oi10Oi_dataout; + nl1O001iO <= wire_nl1Oi10Ol_dataout; + nl1O001li <= wire_nl1Oi10OO_dataout; + nl1O001ll <= wire_nl1Oi1i1i_dataout; + nl1O001lO <= wire_nl1Oi1i1l_dataout; + nl1O001Oi <= wire_nl1Oi1i1O_dataout; + nl1O001Ol <= wire_nl1Oi1i0i_dataout; + nl1O001OO <= wire_nl1Oi1i0l_dataout; + nl1O00i0i <= wire_nl1Oi1liO_dataout; + nl1O00i0l <= wire_nl1Oi1lli_dataout; + nl1O00i0O <= wire_nl1Oi1lll_dataout; + nl1O00i1i <= wire_nl1Oi1l0O_dataout; + nl1O00i1l <= wire_nl1Oi1lii_dataout; + nl1O00i1O <= wire_nl1Oi1lil_dataout; + nl1O00iii <= wire_nl1Oi1llO_dataout; + nl1O00iil <= wire_nl1Oi1lOi_dataout; + nl1O00iiO <= wire_nl1Oi1lOl_dataout; + nl1O00ili <= wire_nl1Oi1lOO_dataout; + nl1O00ill <= wire_nl1Oi1O1i_dataout; + nl1O00ilO <= wire_nl1Oi1O1l_dataout; + nl1O00iOi <= wire_nl1Oi1O1O_dataout; + nl1O00iOl <= wire_nl1Oi1O0i_dataout; + nl1O00iOO <= wire_nl1Oi1O0l_dataout; + nl1O00l0i <= wire_nl1Oi1OiO_dataout; + nl1O00l0l <= wire_nl1Oi1Oli_dataout; + nl1O00l0O <= wire_nl1Oi1Oll_dataout; + nl1O00l1i <= wire_nl1Oi1O0O_dataout; + nl1O00l1l <= wire_nl1Oi1Oii_dataout; + nl1O00l1O <= wire_nl1Oi1Oil_dataout; + nl1O00lii <= wire_nl1Oi1OlO_dataout; + nl1O00lil <= wire_nl1Oi1OOi_dataout; + nl1O00liO <= wire_nl1Oi1OOl_dataout; + nl1O00lli <= wire_nl1Oi1OOO_dataout; + nl1O00lll <= wire_nl1Oi011i_dataout; + nl1O00llO <= wire_nl1Oi011l_dataout; + nl1O00lOi <= wire_nl1Oi011O_dataout; + nl1O00lOl <= wire_nl1Oi010i_dataout; + nl1O00lOO <= wire_nl1Oi010l_dataout; + nl1O00O0i <= wire_nl1Oi01iO_dataout; + nl1O00O0l <= wire_nl1Oi01li_dataout; + nl1O00O0O <= wire_nl1Oi01ll_dataout; + nl1O00O1i <= wire_nl1Oi010O_dataout; + nl1O00O1l <= wire_nl1Oi01ii_dataout; + nl1O00O1O <= wire_nl1Oi01il_dataout; + nl1O00Oii <= wire_nl1Oi01lO_dataout; + nl1O00Oil <= wire_nl1Oi01Oi_dataout; + nl1O00OiO <= wire_nl1Oi01Ol_dataout; + nl1O00Oli <= wire_nl1Oi01OO_dataout; + nl1O00Oll <= wire_nl1Oi001i_dataout; + nl1O00OlO <= wire_nl1Oi001l_dataout; + nl1O00OOi <= wire_nl1Oi001O_dataout; + nl1O00OOl <= wire_nl1Oi000i_dataout; + nl1O00OOO <= wire_nl1Oi000l_dataout; + nl1O0100i <= wire_nl1O0OiiO_dataout; + nl1O0100l <= wire_nl1O0Oili_dataout; + nl1O0100O <= wire_nl1O0Oill_dataout; + nl1O0101i <= wire_nl1O0Oi0O_dataout; + nl1O0101l <= wire_nl1O0Oiii_dataout; + nl1O0101O <= wire_nl1O0Oiil_dataout; + nl1O010ii <= wire_nl1O0OilO_dataout; + nl1O010il <= wire_nl1O0OiOi_dataout; + nl1O010iO <= wire_nl1O0OiOl_dataout; + nl1O010li <= wire_nl1O0OiOO_dataout; + nl1O010ll <= wire_nl1O0Ol1i_dataout; + nl1O010lO <= wire_nl1O0Ol1l_dataout; + nl1O010Oi <= wire_nl1O0Ol1O_dataout; + nl1O010Ol <= wire_nl1O0Ol0i_dataout; + nl1O010OO <= wire_nl1O0Ol0l_dataout; + nl1O0110i <= wire_nl1O0O0iO_dataout; + nl1O0110l <= wire_nl1O0O0li_dataout; + nl1O0110O <= wire_nl1O0O0ll_dataout; + nl1O0111i <= wire_nl1O0O00O_dataout; + nl1O0111l <= wire_nl1O0O0ii_dataout; + nl1O0111O <= wire_nl1O0O0il_dataout; + nl1O011ii <= wire_nl1O0O0lO_dataout; + nl1O011il <= wire_nl1O0O0Oi_dataout; + nl1O011iO <= wire_nl1O0O0Ol_dataout; + nl1O011li <= wire_nl1O0O0OO_dataout; + nl1O011ll <= wire_nl1O0Oi1i_dataout; + nl1O011lO <= wire_nl1O0Oi1l_dataout; + nl1O011Oi <= wire_nl1O0Oi1O_dataout; + nl1O011Ol <= wire_nl1O0Oi0i_dataout; + nl1O011OO <= wire_nl1O0Oi0l_dataout; + nl1O01i0i <= wire_nl1O0OliO_dataout; + nl1O01i0l <= wire_nl1O0Olli_dataout; + nl1O01i0O <= wire_nl1O0Olll_dataout; + nl1O01i1i <= wire_nl1O0Ol0O_dataout; + nl1O01i1l <= wire_nl1O0Olii_dataout; + nl1O01i1O <= wire_nl1O0Olil_dataout; + nl1O01iii <= wire_nl1O0OllO_dataout; + nl1O01iil <= wire_nl1O0OlOi_dataout; + nl1O01iiO <= wire_nl1O0OlOl_dataout; + nl1O01ili <= wire_nl1O0OlOO_dataout; + nl1O01ill <= wire_nl1O0OO1i_dataout; + nl1O01ilO <= wire_nl1O0OO1l_dataout; + nl1O01iOi <= wire_nl1O0OO1O_dataout; + nl1O01iOl <= wire_nl1O0OO0i_dataout; + nl1O01iOO <= wire_nl1O0OO0l_dataout; + nl1O01l0i <= wire_nl1O0OOiO_dataout; + nl1O01l0l <= wire_nl1O0OOli_dataout; + nl1O01l0O <= wire_nl1O0OOll_dataout; + nl1O01l1i <= wire_nl1O0OO0O_dataout; + nl1O01l1l <= wire_nl1O0OOii_dataout; + nl1O01l1O <= wire_nl1O0OOil_dataout; + nl1O01lii <= wire_nl1O0OOlO_dataout; + nl1O01lil <= wire_nl1O0OOOi_dataout; + nl1O01liO <= wire_nl1O0OOOl_dataout; + nl1O01lli <= wire_nl1O0OOOO_dataout; + nl1O01lll <= wire_nl1Oi111i_dataout; + nl1O01llO <= wire_nl1Oi111l_dataout; + nl1O01lOi <= wire_nl1Oi111O_dataout; + nl1O01lOl <= wire_nl1Oi110i_dataout; + nl1O01lOO <= wire_nl1Oi110l_dataout; + nl1O01O0i <= wire_nl1Oi11iO_dataout; + nl1O01O0l <= wire_nl1Oi11li_dataout; + nl1O01O0O <= wire_nl1Oi11ll_dataout; + nl1O01O1i <= wire_nl1Oi110O_dataout; + nl1O01O1l <= wire_nl1Oi11ii_dataout; + nl1O01O1O <= wire_nl1Oi11il_dataout; + nl1O01Oii <= wire_nl1Oi11lO_dataout; + nl1O01Oil <= wire_nl1Oi11Oi_dataout; + nl1O01OiO <= wire_nl1Oi11Ol_dataout; + nl1O01Oli <= wire_nl1Oi11OO_dataout; + nl1O01Oll <= wire_nl1Oi101i_dataout; + nl1O01OlO <= wire_nl1Oi101l_dataout; + nl1O01OOi <= wire_nl1Oi101O_dataout; + nl1O01OOl <= wire_nl1Oi100i_dataout; + nl1O01OOO <= wire_nl1Oi100l_dataout; + nl1O0i00i <= wire_nl1Oi0iiO_dataout; + nl1O0i00l <= wire_nl1Oi0ili_dataout; + nl1O0i00O <= wire_nl1Oi0ill_dataout; + nl1O0i01i <= wire_nl1Oi0i0O_dataout; + nl1O0i01l <= wire_nl1Oi0iii_dataout; + nl1O0i01O <= wire_nl1Oi0iil_dataout; + nl1O0i0ii <= wire_nl1Oi0ilO_dataout; + nl1O0i0il <= wire_nl1Oi0iOi_dataout; + nl1O0i0iO <= wire_nl1Oi0iOl_dataout; + nl1O0i0li <= wire_nl1Oi0iOO_dataout; + nl1O0i0ll <= wire_nl1Oi0l1i_dataout; + nl1O0i0lO <= wire_nl1Oi0l1l_dataout; + nl1O0i0Oi <= wire_nl1Oi0l1O_dataout; + nl1O0i0Ol <= wire_nl1Oi0l0i_dataout; + nl1O0i0OO <= wire_nl1Oi0l0l_dataout; + nl1O0i10i <= wire_nl1Oi00iO_dataout; + nl1O0i10l <= wire_nl1Oi00li_dataout; + nl1O0i10O <= wire_nl1Oi00ll_dataout; + nl1O0i11i <= wire_nl1Oi000O_dataout; + nl1O0i11l <= wire_nl1Oi00ii_dataout; + nl1O0i11O <= wire_nl1Oi00il_dataout; + nl1O0i1ii <= wire_nl1Oi00lO_dataout; + nl1O0i1il <= wire_nl1Oi00Oi_dataout; + nl1O0i1iO <= wire_nl1Oi00Ol_dataout; + nl1O0i1li <= wire_nl1Oi00OO_dataout; + nl1O0i1ll <= wire_nl1Oi0i1i_dataout; + nl1O0i1lO <= wire_nl1Oi0i1l_dataout; + nl1O0i1Oi <= wire_nl1Oi0i1O_dataout; + nl1O0i1Ol <= wire_nl1Oi0i0i_dataout; + nl1O0i1OO <= wire_nl1Oi0i0l_dataout; + nl1O0ii0i <= wire_nl1Oi0liO_dataout; + nl1O0ii0l <= wire_nl1Oi0lli_dataout; + nl1O0ii0O <= wire_nl1Oi0lll_dataout; + nl1O0ii1i <= wire_nl1Oi0l0O_dataout; + nl1O0ii1l <= wire_nl1Oi0lii_dataout; + nl1O0ii1O <= wire_nl1Oi0lil_dataout; + nl1O0iiii <= wire_nl1OilOiO_dataout; + nl1O1i0OO <= wire_nl1O0iiiO_dataout; + nl1O1ii0i <= wire_nl1O0iiOi_dataout; + nl1O1ii0l <= wire_nl1O0iiOl_dataout; + nl1O1ii0O <= wire_nl1O0iiOO_dataout; + nl1O1ii1i <= wire_nl1O0iili_dataout; + nl1O1ii1l <= wire_nl1O0iill_dataout; + nl1O1ii1O <= wire_nl1O0iilO_dataout; + nl1O1iiii <= wire_nl1O0il1i_dataout; + nl1O1iiil <= wire_nl1O0il1l_dataout; + nl1O1iiiO <= wire_nl1O0il1O_dataout; + nl1O1iili <= wire_nl1O0il0i_dataout; + nl1O1iill <= wire_nl1O0il0l_dataout; + nl1O1iilO <= wire_nl1O0il0O_dataout; + nl1O1iiOi <= wire_nl1O0ilii_dataout; + nl1O1iiOl <= wire_nl1O0ilil_dataout; + nl1O1iiOO <= wire_nl1O0iliO_dataout; + nl1O1il0i <= wire_nl1O0ilOi_dataout; + nl1O1il0l <= wire_nl1O0ilOl_dataout; + nl1O1il0O <= wire_nl1O0ilOO_dataout; + nl1O1il1i <= wire_nl1O0illi_dataout; + nl1O1il1l <= wire_nl1O0illl_dataout; + nl1O1il1O <= wire_nl1O0illO_dataout; + nl1O1ilii <= wire_nl1O0iO1i_dataout; + nl1O1ilil <= wire_nl1O0iO1l_dataout; + nl1O1iliO <= wire_nl1O0iO1O_dataout; + nl1O1illi <= wire_nl1O0iO0i_dataout; + nl1O1illl <= wire_nl1O0iO0l_dataout; + nl1O1illO <= wire_nl1O0iO0O_dataout; + nl1O1ilOi <= wire_nl1O0iOii_dataout; + nl1O1ilOl <= wire_nl1O0iOil_dataout; + nl1O1ilOO <= wire_nl1O0iOiO_dataout; + nl1O1iO0i <= wire_nl1O0iOOi_dataout; + nl1O1iO0l <= wire_nl1O0iOOl_dataout; + nl1O1iO0O <= wire_nl1O0iOOO_dataout; + nl1O1iO1i <= wire_nl1O0iOli_dataout; + nl1O1iO1l <= wire_nl1O0iOll_dataout; + nl1O1iO1O <= wire_nl1O0iOlO_dataout; + nl1O1iOii <= wire_nl1O0l11i_dataout; + nl1O1iOil <= wire_nl1O0l11l_dataout; + nl1O1iOiO <= wire_nl1O0l11O_dataout; + nl1O1iOli <= wire_nl1O0l10i_dataout; + nl1O1iOll <= wire_nl1O0l10l_dataout; + nl1O1iOlO <= wire_nl1O0l10O_dataout; + nl1O1iOOi <= wire_nl1O0l1ii_dataout; + nl1O1iOOl <= wire_nl1O0l1il_dataout; + nl1O1iOOO <= wire_nl1O0l1iO_dataout; + nl1O1l00i <= wire_nl1O0l0Oi_dataout; + nl1O1l00l <= wire_nl1O0l0Ol_dataout; + nl1O1l00O <= wire_nl1O0l0OO_dataout; + nl1O1l01i <= wire_nl1O0l0li_dataout; + nl1O1l01l <= wire_nl1O0l0ll_dataout; + nl1O1l01O <= wire_nl1O0l0lO_dataout; + nl1O1l0ii <= dout_rcv0(0); + nl1O1l0il <= dout_rcv0(1); + nl1O1l0iO <= dout_rcv0(2); + nl1O1l0li <= dout_rcv0(3); + nl1O1l0ll <= dout_rcv0(4); + nl1O1l0lO <= dout_rcv0(5); + nl1O1l0Oi <= dout_rcv0(6); + nl1O1l0Ol <= dout_rcv0(7); + nl1O1l0OO <= dout_rcv0(8); + nl1O1l10i <= wire_nl1O0l1Oi_dataout; + nl1O1l10l <= wire_nl1O0l1Ol_dataout; + nl1O1l10O <= wire_nl1O0l1OO_dataout; + nl1O1l11i <= wire_nl1O0l1li_dataout; + nl1O1l11l <= wire_nl1O0l1ll_dataout; + nl1O1l11O <= wire_nl1O0l1lO_dataout; + nl1O1l1ii <= wire_nl1O0l01i_dataout; + nl1O1l1il <= wire_nl1O0l01l_dataout; + nl1O1l1iO <= wire_nl1O0l01O_dataout; + nl1O1l1li <= wire_nl1O0l00i_dataout; + nl1O1l1ll <= wire_nl1O0l00l_dataout; + nl1O1l1lO <= wire_nl1O0l00O_dataout; + nl1O1l1Oi <= wire_nl1O0l0ii_dataout; + nl1O1l1Ol <= wire_nl1O0l0il_dataout; + nl1O1l1OO <= wire_nl1O0l0iO_dataout; + nl1O1li0i <= dout_rcv0(12); + nl1O1li0l <= dout_rcv0(13); + nl1O1li0O <= dout_rcv0(14); + nl1O1li1i <= dout_rcv0(9); + nl1O1li1l <= dout_rcv0(10); + nl1O1li1O <= dout_rcv0(11); + nl1O1liii <= dout_rcv0(15); + nl1O1liil <= dout_rcv0(16); + nl1O1liiO <= dout_rcv0(17); + nl1O1lili <= dout_rcv0(18); + nl1O1lill <= dout_rcv0(19); + nl1O1lilO <= dout_rcv0(20); + nl1O1liOi <= dout_rcv0(21); + nl1O1liOl <= dout_rcv0(22); + nl1O1liOO <= dout_rcv0(23); + nl1O1ll0i <= dout_rcv0(27); + nl1O1ll0l <= dout_rcv0(28); + nl1O1ll0O <= dout_rcv0(29); + nl1O1ll1i <= dout_rcv0(24); + nl1O1ll1l <= dout_rcv0(25); + nl1O1ll1O <= dout_rcv0(26); + nl1O1llii <= dout_rcv0(30); + nl1O1llil <= dout_rcv0(31); + nl1O1lliO <= dout_rcv0(32); + nl1O1llli <= dout_rcv0(33); + nl1O1llll <= dout_rcv0(34); + nl1O1lllO <= dout_rcv0(35); + nl1O1llOi <= dout_rcv0(36); + nl1O1llOl <= dout_rcv0(37); + nl1O1llOO <= dout_rcv0(38); + nl1O1lO0i <= dout_rcv0(42); + nl1O1lO0l <= dout_rcv0(43); + nl1O1lO0O <= dout_rcv0(44); + nl1O1lO1i <= dout_rcv0(39); + nl1O1lO1l <= dout_rcv0(40); + nl1O1lO1O <= dout_rcv0(41); + nl1O1lOii <= dout_rcv0(45); + nl1O1lOil <= dout_rcv0(46); + nl1O1lOiO <= dout_rcv0(47); + nl1O1lOli <= dout_rcv0(48); + nl1O1lOll <= dout_rcv0(49); + nl1O1lOlO <= dout_rcv0(50); + nl1O1lOOi <= dout_rcv0(51); + nl1O1lOOl <= dout_rcv0(52); + nl1O1lOOO <= dout_rcv0(53); + nl1O1O00i <= wire_nl1O0liiO_dataout; + nl1O1O00l <= wire_nl1O0lili_dataout; + nl1O1O00O <= wire_nl1O0lill_dataout; + nl1O1O01i <= wire_nl1O0li0O_dataout; + nl1O1O01l <= wire_nl1O0liii_dataout; + nl1O1O01O <= wire_nl1O0liil_dataout; + nl1O1O0ii <= wire_nl1O0lilO_dataout; + nl1O1O0il <= wire_nl1O0liOi_dataout; + nl1O1O0iO <= wire_nl1O0liOl_dataout; + nl1O1O0li <= wire_nl1O0liOO_dataout; + nl1O1O0ll <= wire_nl1O0ll1i_dataout; + nl1O1O0lO <= wire_nl1O0ll1l_dataout; + nl1O1O0Oi <= wire_nl1O0ll1O_dataout; + nl1O1O0Ol <= wire_nl1O0ll0i_dataout; + nl1O1O0OO <= wire_nl1O0ll0l_dataout; + nl1O1O10i <= dout_rcv0(57); + nl1O1O10l <= dout_rcv0(58); + nl1O1O10O <= dout_rcv0(59); + nl1O1O11i <= dout_rcv0(54); + nl1O1O11l <= dout_rcv0(55); + nl1O1O11O <= dout_rcv0(56); + nl1O1O1ii <= dout_rcv0(60); + nl1O1O1il <= dout_rcv0(61); + nl1O1O1iO <= dout_rcv0(62); + nl1O1O1li <= dout_rcv0(63); + nl1O1O1ll <= wire_nl1O0li1i_dataout; + nl1O1O1lO <= wire_nl1O0li1l_dataout; + nl1O1O1Oi <= wire_nl1O0li1O_dataout; + nl1O1O1Ol <= wire_nl1O0li0i_dataout; + nl1O1O1OO <= wire_nl1O0li0l_dataout; + nl1O1Oi0i <= wire_nl1O0lliO_dataout; + nl1O1Oi0l <= wire_nl1O0llli_dataout; + nl1O1Oi0O <= wire_nl1O0llll_dataout; + nl1O1Oi1i <= wire_nl1O0ll0O_dataout; + nl1O1Oi1l <= wire_nl1O0llii_dataout; + nl1O1Oi1O <= wire_nl1O0llil_dataout; + nl1O1Oiii <= wire_nl1O0lllO_dataout; + nl1O1Oiil <= wire_nl1O0llOi_dataout; + nl1O1OiiO <= wire_nl1O0llOl_dataout; + nl1O1Oili <= wire_nl1O0llOO_dataout; + nl1O1Oill <= wire_nl1O0lO1i_dataout; + nl1O1OilO <= wire_nl1O0lO1l_dataout; + nl1O1OiOi <= wire_nl1O0lO1O_dataout; + nl1O1OiOl <= wire_nl1O0lO0i_dataout; + nl1O1OiOO <= wire_nl1O0lO0l_dataout; + nl1O1Ol0i <= wire_nl1O0lOiO_dataout; + nl1O1Ol0l <= wire_nl1O0lOli_dataout; + nl1O1Ol0O <= wire_nl1O0lOll_dataout; + nl1O1Ol1i <= wire_nl1O0lO0O_dataout; + nl1O1Ol1l <= wire_nl1O0lOii_dataout; + nl1O1Ol1O <= wire_nl1O0lOil_dataout; + nl1O1Olii <= wire_nl1O0lOlO_dataout; + nl1O1Olil <= wire_nl1O0lOOi_dataout; + nl1O1OliO <= wire_nl1O0lOOl_dataout; + nl1O1Olli <= wire_nl1O0lOOO_dataout; + nl1O1Olll <= wire_nl1O0O11i_dataout; + nl1O1OllO <= wire_nl1O0O11l_dataout; + nl1O1OlOi <= wire_nl1O0O11O_dataout; + nl1O1OlOl <= wire_nl1O0O10i_dataout; + nl1O1OlOO <= wire_nl1O0O10l_dataout; + nl1O1OO0i <= wire_nl1O0O1iO_dataout; + nl1O1OO0l <= wire_nl1O0O1li_dataout; + nl1O1OO0O <= wire_nl1O0O1ll_dataout; + nl1O1OO1i <= wire_nl1O0O10O_dataout; + nl1O1OO1l <= wire_nl1O0O1ii_dataout; + nl1O1OO1O <= wire_nl1O0O1il_dataout; + nl1O1OOii <= wire_nl1O0O1lO_dataout; + nl1O1OOil <= wire_nl1O0O1Oi_dataout; + nl1O1OOiO <= wire_nl1O0O1Ol_dataout; + nl1O1OOli <= wire_nl1O0O1OO_dataout; + nl1O1OOll <= wire_nl1O0O01i_dataout; + nl1O1OOlO <= wire_nl1O0O01l_dataout; + nl1O1OOOi <= wire_nl1O0O01O_dataout; + nl1O1OOOl <= wire_nl1O0O00i_dataout; + nl1O1OOOO <= wire_nl1O0O00l_dataout; + nl1Oill0l <= wire_nl1OilOli_dataout; + nl1Oill0O <= wire_nl1OilOll_dataout; + nl1Oillii <= wire_nl1OilOlO_dataout; + nl1Oillil <= wire_nl1OilOOi_dataout; + nl1OilliO <= wire_nl1OilOOl_dataout; + nl1Oillli <= wire_nl1OilOOO_dataout; + nl1Oillll <= wire_nl1OiO11i_dataout; + nl1OilllO <= wire_nl1OiO11l_dataout; + nl1OillOi <= wire_nl1OiO11O_dataout; + nl1OillOl <= wire_nl1OiO10i_dataout; + nl1OillOO <= wire_nl1OiO10l_dataout; + nl1OilO0l <= wire_nl1OiO1li_dataout; + nl1OilO0O <= wire_nl1OiO1ll_dataout; + nl1OilO1i <= wire_nl1OiO10O_dataout; + nl1OilO1l <= wire_nl1OiO1ii_dataout; + nl1OilO1O <= wire_nl1OiO1il_dataout; + nl1OilOii <= wire_nl1OiO1lO_dataout; + nl1OilOil <= wire_nl1Ol010i_dataout; + nl1Ol011i <= wire_nl1Ol0i1l_dataout; + nl1Ol011l <= wire_nl1Ol0i1O_dataout; + nl1Ol011O <= wire_nl1OlO10i_dataout; + nl1Ol1l0i <= wire_nl1Ol010l_dataout; + nl1Ol1l0l <= wire_nl1Ol010O_dataout; + nl1Ol1l0O <= wire_nl1Ol01ii_dataout; + nl1Ol1lii <= wire_nl1Ol01il_dataout; + nl1Ol1lil <= wire_nl1Ol01iO_dataout; + nl1Ol1liO <= wire_nl1Ol01li_dataout; + nl1Ol1lli <= wire_nl1Ol01ll_dataout; + nl1Ol1lll <= wire_nl1Ol01lO_dataout; + nl1Ol1llO <= wire_nl1Ol01Oi_dataout; + nl1Ol1lOi <= wire_nl1Ol01Ol_dataout; + nl1Ol1lOl <= wire_nl1Ol01OO_dataout; + nl1Ol1lOO <= wire_nl1Ol001i_dataout; + nl1Ol1O0i <= wire_nl1Ol000l_dataout; + nl1Ol1O0l <= wire_nl1Ol000O_dataout; + nl1Ol1O0O <= wire_nl1Ol00ii_dataout; + nl1Ol1O1i <= wire_nl1Ol001l_dataout; + nl1Ol1O1l <= wire_nl1Ol001O_dataout; + nl1Ol1O1O <= wire_nl1Ol000i_dataout; + nl1Ol1Oii <= wire_nl1Ol00il_dataout; + nl1Ol1Oil <= wire_nl1Ol00iO_dataout; + nl1Ol1OiO <= wire_nl1Ol00li_dataout; + nl1Ol1Oli <= wire_nl1Ol00ll_dataout; + nl1Ol1Oll <= wire_nl1Ol00lO_dataout; + nl1Ol1OlO <= wire_nl1Ol00Oi_dataout; + nl1Ol1OOi <= wire_nl1Ol00Ol_dataout; + nl1Ol1OOl <= wire_nl1Ol00OO_dataout; + nl1Ol1OOO <= wire_nl1Ol0i1i_dataout; + nl1OllOOl <= wire_nl1OlO10l_dataout; + nl1OllOOO <= wire_nl1OlO10O_dataout; + nl1OlO11i <= wire_nl1OlO1ii_dataout; + nl1OlO11l <= wire_nl1OlO1il_dataout; + nl1OlO11O <= wire_nl1OO01ii_dataout; + nl1OO010i <= wire_nl1OO00li_dataout; + nl1OO010l <= wire_nl1OO00ll_dataout; + nl1OO010O <= wire_nl1OOil0i_dataout; + nl1OO011i <= wire_nl1OO00ii_dataout; + nl1OO011l <= wire_nl1OO00il_dataout; + nl1OO011O <= wire_nl1OO00iO_dataout; + nl1OO1O0i <= wire_nl1OO01li_dataout; + nl1OO1O0l <= wire_nl1OO01ll_dataout; + nl1OO1O0O <= wire_nl1OO01lO_dataout; + nl1OO1O1l <= wire_nl1OO01il_dataout; + nl1OO1O1O <= wire_nl1OO01iO_dataout; + nl1OO1Oii <= wire_nl1OO01Oi_dataout; + nl1OO1Oil <= wire_nl1OO01Ol_dataout; + nl1OO1OiO <= wire_nl1OO01OO_dataout; + nl1OO1Oli <= wire_nl1OO001i_dataout; + nl1OO1Oll <= wire_nl1OO001l_dataout; + nl1OO1OlO <= wire_nl1OO001O_dataout; + nl1OO1OOi <= wire_nl1OO000i_dataout; + nl1OO1OOl <= wire_nl1OO000l_dataout; + nl1OO1OOO <= wire_nl1OO000O_dataout; + nl1OOi00i <= wire_nl1OOillO_dataout; + nl1OOi00l <= wire_nl1OOilOi_dataout; + nl1OOi00O <= wire_nl1OOilOl_dataout; + nl1OOi01i <= wire_nl1OOiliO_dataout; + nl1OOi01l <= wire_nl1OOilli_dataout; + nl1OOi01O <= wire_nl1OOilll_dataout; + nl1OOi0ii <= wire_nl1OOilOO_dataout; + nl1OOi0il <= wire_nl1OOiO1i_dataout; + nl1OOi0iO <= wire_nl1OOiO1l_dataout; + nl1OOi0li <= wire_nl1OOiO1O_dataout; + nl1OOi0ll <= wire_nl1OOiO0i_dataout; + nl1OOi0lO <= wire_nl1OOiO0l_dataout; + nl1OOi0Oi <= wire_nl1OOiO0O_dataout; + nl1OOi0Ol <= wire_nl1OOiOii_dataout; + nl1OOi0OO <= wire_nl1OOiOil_dataout; + nl1OOi1lO <= wire_nl1OOil0l_dataout; + nl1OOi1Oi <= wire_nl1OOil0O_dataout; + nl1OOi1Ol <= wire_nl1OOilii_dataout; + nl1OOi1OO <= wire_nl1OOilil_dataout; + nl1OOii0i <= wire_nl1OOiOlO_dataout; + nl1OOii0l <= wire_nl1OOiOOi_dataout; + nl1OOii0O <= wire_nl1OOiOOl_dataout; + nl1OOii1i <= wire_nl1OOiOiO_dataout; + nl1OOii1l <= wire_nl1OOiOli_dataout; + nl1OOiiii <= wire_nl1OOiOOO_dataout; + nl1OOiiil <= wire_nl1OOl11i_dataout; + nl1OOiiiO <= wire_nl1OOl11l_dataout; + nl1OOiili <= wire_nl1OOl11O_dataout; + nl1OOiill <= wire_nl1OOl10i_dataout; + nl1OOiilO <= wire_nl1OOl10l_dataout; + nl1OOiiOi <= wire_nl1OOl10O_dataout; + nl1OOiiOl <= wire_nl1OOl1ii_dataout; + nl1OOiiOO <= wire_nl1OOl1il_dataout; + nl1OOil1i <= wire_nl1OOl1iO_dataout; + nl1OOil1l <= wire_nl1OOl1li_dataout; + nl1OOil1O <= wire_nl0111OOi_dataout; + nli0Oi0lO <= wire_nli0Oii1i_dataout; + nli0Oi0Ol <= wire_nli0Oii1l_dataout; + nli0Oi0OO <= wire_nli0OiiOl_dataout; + nli0Oiill <= wire_nli0OiiOO_dataout; + nli0OiilO <= wire_nli0Oil1i_dataout; + nli0OiiOi <= wire_nlii11iil_dataout; + nli0OOOlO <= wire_nlii11iiO_dataout; + nli0OOOOi <= wire_nlii11ili_dataout; + nli0OOOOl <= wire_nlii11ill_dataout; + nli0OOOOO <= wire_nlii11ilO_dataout; + nli10001i <= wire_nli10i1li_dataout; + nli10001l <= wire_nli10i1ll_dataout; + nli10001O <= wire_nli10OilO_dataout; + nli10010i <= wire_nli100OOi_dataout; + nli10010l <= wire_nli100OOl_dataout; + nli10010O <= wire_nli100OOO_dataout; + nli10011i <= wire_nli100Oli_dataout; + nli10011l <= wire_nli100Oll_dataout; + nli10011O <= wire_nli100OlO_dataout; + nli1001ii <= wire_nli10i11i_dataout; + nli1001il <= wire_nli10i11l_dataout; + nli1001iO <= wire_nli10i11O_dataout; + nli1001li <= wire_nli10i10i_dataout; + nli1001ll <= wire_nli10i10l_dataout; + nli1001lO <= wire_nli10i10O_dataout; + nli1001Oi <= wire_nli10i1ii_dataout; + nli1001Ol <= wire_nli10i1il_dataout; + nli1001OO <= wire_nli10i1iO_dataout; + nli1010ll <= wire_nli10000l_dataout; + nli1010lO <= wire_nli10000O_dataout; + nli1010Oi <= wire_nli1000ii_dataout; + nli1010Ol <= wire_nli1000il_dataout; + nli1010OO <= wire_nli1000iO_dataout; + nli101i0i <= wire_nli1000Oi_dataout; + nli101i0l <= wire_nli1000Ol_dataout; + nli101i0O <= wire_nli1000OO_dataout; + nli101i1i <= wire_nli1000li_dataout; + nli101i1l <= wire_nli1000ll_dataout; + nli101i1O <= wire_nli1000lO_dataout; + nli101iii <= wire_nli100i1i_dataout; + nli101iil <= wire_nli100i1l_dataout; + nli101iiO <= wire_nli100i1O_dataout; + nli101ili <= wire_nli100i0i_dataout; + nli101ill <= wire_nli100i0l_dataout; + nli101ilO <= wire_nli100i0O_dataout; + nli101iOi <= wire_nli100iii_dataout; + nli101iOl <= wire_nli100iil_dataout; + nli101iOO <= wire_nli100iiO_dataout; + nli101l0i <= wire_nli100iOi_dataout; + nli101l0l <= wire_nli100iOl_dataout; + nli101l0O <= wire_nli100iOO_dataout; + nli101l1i <= wire_nli100ili_dataout; + nli101l1l <= wire_nli100ill_dataout; + nli101l1O <= wire_nli100ilO_dataout; + nli101lii <= wire_nli100l1i_dataout; + nli101lil <= wire_nli100l1l_dataout; + nli101liO <= wire_nli100l1O_dataout; + nli101lli <= wire_nli100l0i_dataout; + nli101lll <= wire_nli100l0l_dataout; + nli101llO <= wire_nli100l0O_dataout; + nli101lOi <= wire_nli100lii_dataout; + nli101lOl <= wire_nli100lil_dataout; + nli101lOO <= wire_nli100liO_dataout; + nli101O0i <= wire_nli100lOi_dataout; + nli101O0l <= wire_nli100lOl_dataout; + nli101O0O <= wire_nli100lOO_dataout; + nli101O1i <= wire_nli100lli_dataout; + nli101O1l <= wire_nli100lll_dataout; + nli101O1O <= wire_nli100llO_dataout; + nli101Oii <= wire_nli100O1i_dataout; + nli101Oil <= wire_nli100O1l_dataout; + nli101OiO <= wire_nli100O1O_dataout; + nli101Oli <= wire_nli100O0i_dataout; + nli101Oll <= wire_nli100O0l_dataout; + nli101OlO <= wire_nli100O0O_dataout; + nli101OOi <= wire_nli100Oii_dataout; + nli101OOl <= wire_nli100Oil_dataout; + nli101OOO <= wire_nli100OiO_dataout; + nli10Oiil <= wire_nli10OiOi_dataout; + nli10OiiO <= wire_nli10OiOl_dataout; + nli10Oili <= wire_nli10OiOO_dataout; + nli10Oill <= wire_nli10OO0O_dataout; + nli10Olil <= wire_nli10OOii_dataout; + nli10OliO <= wire_nli10OOil_dataout; + nli10Olli <= wire_nli10OOiO_dataout; + nli10Olll <= wire_nli10OOli_dataout; + nli10OllO <= wire_nli10OOll_dataout; + nli10OlOi <= wire_nli10OOlO_dataout; + nli10OlOl <= wire_nli10OOOi_dataout; + nli10OlOO <= wire_nli11l0Oi_dataout; + nli10OO0i <= wire_nli1i111l_dataout; + nli10OO0l <= wire_nli1i001l_dataout; + nli10OO1i <= wire_nli10OOOl_dataout; + nli10OO1l <= wire_nli10OOOO_dataout; + nli10OO1O <= wire_nli1i111i_dataout; + nli11000i <= wire_nli110ill_dataout; + nli11000l <= wire_nli110ilO_dataout; + nli11000O <= wire_nli110iOi_dataout; + nli11001i <= wire_nli110iil_dataout; + nli11001l <= wire_nli110iiO_dataout; + nli11001O <= wire_nli110ili_dataout; + nli1100ii <= wire_nli110iOl_dataout; + nli1100il <= wire_nli110iOO_dataout; + nli1100iO <= wire_nli110l1i_dataout; + nli11010i <= wire_nli1100ll_dataout; + nli11010l <= wire_nli1100lO_dataout; + nli11010O <= wire_nli1100Oi_dataout; + nli1101ii <= wire_nli1100Ol_dataout; + nli1101il <= wire_nli1100OO_dataout; + nli1101iO <= wire_nli110i1i_dataout; + nli1101li <= wire_nli110i1l_dataout; + nli1101ll <= wire_nli110i1O_dataout; + nli1101lO <= wire_nli110i0i_dataout; + nli1101Oi <= wire_nli110i0l_dataout; + nli1101Ol <= wire_nli110i0O_dataout; + nli1101OO <= wire_nli110iii_dataout; + nli111i1l <= wire_nli1100li_dataout; + nli11iiii <= wire_nli11iilO_dataout; + nli11iill <= wire_nli11ilOl_dataout; + nli11ilil <= wire_nli11ilOO_dataout; + nli11iliO <= wire_nli11iO1i_dataout; + nli11illi <= wire_nli11iO1l_dataout; + nli11illl <= wire_nli11iO1O_dataout; + nli11illO <= wire_nli11iO0i_dataout; + nli11l0Ol <= wire_nli11li1l_dataout; + nli11l0OO <= wire_nli11li1O_dataout; + nli11O0ii <= wire_nli11OiOO_dataout; + nli11OiOl <= wire_nli11OliO_dataout; + nli11Ol0i <= wire_nli11Olli_dataout; + nli11Ol0l <= wire_nli11Olll_dataout; + nli11Ol0O <= wire_nli11OllO_dataout; + nli11Olii <= wire_nli11OlOi_dataout; + nli11Olil <= wire_nli10111i_dataout; + nli11OOll <= wire_nli10111l_dataout; + nli11OOlO <= wire_nli10111O_dataout; + nli11OOOi <= wire_nli10110i_dataout; + nli11OOOl <= wire_nli10110l_dataout; + nli11OOOO <= wire_nli10000i_dataout; + nli1i001i <= wire_nli1ii0lO_dataout; + nli1i011i <= wire_nli1i000O_dataout; + nli1i01li <= wire_nli1i00OO_dataout; + nli1i01ll <= wire_nli1i0i1i_dataout; + nli1i01lO <= wire_nli1i0i1l_dataout; + nli1i01Oi <= wire_nli1i0i1O_dataout; + nli1i01Ol <= wire_nli1i0i0i_dataout; + nli1i01OO <= wire_nli1i0i0l_dataout; + nli1i1OOi <= wire_nli1i001O_dataout; + nli1i1OOl <= wire_nli1i000i_dataout; + nli1i1OOO <= wire_nli1i000l_dataout; + nli1ii0li <= wire_nli1ii0Oi_dataout; + nli1ii0ll <= wire_nli1iiiOO_dataout; + nli1iiiiO <= wire_nli1iil1i_dataout; + nli1iiili <= wire_nli1iil1l_dataout; + nli1iiill <= wire_nli1iil1O_dataout; + nli1iiilO <= wire_nli1iil0i_dataout; + nli1iiiOi <= wire_nli1iil0l_dataout; + nli1iiiOl <= wire_nli1il1il_dataout; + nli1iiOlO <= wire_nli1il1iO_dataout; + nli1iiOOi <= wire_nli1il1li_dataout; + nli1iiOOl <= wire_nli1il1ll_dataout; + nli1iiOOO <= wire_nli1il1lO_dataout; + nli1il10i <= wire_nli1il01i_dataout; + nli1il10l <= wire_nli1il01l_dataout; + nli1il10O <= wire_nli1il01O_dataout; + nli1il11i <= wire_nli1il1Oi_dataout; + nli1il11l <= wire_nli1il1Ol_dataout; + nli1il11O <= wire_nli1il1OO_dataout; + nli1il1ii <= wire_nli1ilO0i_dataout; + nli1illiO <= wire_nli1ilO0l_dataout; + nli1illli <= wire_nli1ilO0O_dataout; + nli1illll <= wire_nli1ilOii_dataout; + nli1illlO <= wire_nli1ilOil_dataout; + nli1illOi <= wire_nli1ilOiO_dataout; + nli1illOl <= wire_nli1iO1lO_dataout; + nli1illOO <= wire_nli1iO1Oi_dataout; + nli1ilO1i <= wire_nli1iO1Ol_dataout; + nli1ilO1l <= wire_nli1iO1OO_dataout; + nli1iO0OO <= wire_nli1iOlii_dataout; + nli1iOi0l <= wire_nli1iOl0i_dataout; + nli1iOiii <= wire_nli1iOl0O_dataout; + nli1iOiiO <= wire_nli1iOliO_dataout; + nli1iOili <= wire_nli1iOlli_dataout; + nli1iOill <= wire_nli1iOlll_dataout; + nli1iOilO <= wire_nli1iOllO_dataout; + nli1iOiOl <= wire_nli1iOlOl_dataout; + nli1iOiOO <= wire_nli1iOlOO_dataout; + nli1iOl1i <= wire_nli1iOO1i_dataout; + nli1iOl1l <= wire_nli1iOO1l_dataout; + nli1iOl1O <= wire_nli1l11OO_dataout; + nli1l000i <= wire_nli1l0i1l_dataout; + nli1l000l <= wire_nli1l0i1O_dataout; + nli1l000O <= wire_nli1l0i0i_dataout; + nli1l001O <= wire_nli1l1OlO_dataout; + nli1l00ii <= wire_nli1l0i0l_dataout; + nli1l00il <= wire_nli1l0i0O_dataout; + nli1l00iO <= wire_nli1l0iii_dataout; + nli1l00li <= wire_nli1l0iil_dataout; + nli1l00ll <= wire_nli1l0iiO_dataout; + nli1l00lO <= wire_nli1l0ili_dataout; + nli1l00Oi <= wire_nli1l0ill_dataout; + nli1l00Ol <= wire_nli1l0ilO_dataout; + nli1l00OO <= wire_nli1l0iOi_dataout; + nli1l110O <= wire_nli1l101i_dataout; + nli1l11ii <= wire_nli1l101l_dataout; + nli1l11il <= wire_nli1l101O_dataout; + nli1l11iO <= wire_nli1l100i_dataout; + nli1l11li <= wire_nli1l100l_dataout; + nli1l11ll <= wire_nli1l100O_dataout; + nli1l11lO <= wire_nli1l10ii_dataout; + nli1l11Oi <= wire_nli1l10il_dataout; + nli1l11Ol <= wire_nli1l10iO_dataout; + nli1l1l0O <= wire_nli1l1OOi_dataout; + nli1l1lii <= wire_nli1l1OOl_dataout; + nli1l1lil <= wire_nli1l1OOO_dataout; + nli1l1liO <= wire_nli1l011i_dataout; + nli1l1lli <= wire_nli1l011l_dataout; + nli1l1lll <= wire_nli1l011O_dataout; + nli1l1llO <= wire_nli1l010i_dataout; + nli1l1lOi <= wire_nli1l010l_dataout; + nli1l1lOl <= wire_nli1l010O_dataout; + nli1l1lOO <= wire_nli1l01ii_dataout; + nli1l1O0i <= wire_nli1l01ll_dataout; + nli1l1O0l <= wire_nli1l01lO_dataout; + nli1l1O0O <= wire_nli1l01Oi_dataout; + nli1l1O1i <= wire_nli1l01il_dataout; + nli1l1O1l <= wire_nli1l01iO_dataout; + nli1l1O1O <= wire_nli1l01li_dataout; + nli1l1Oii <= wire_nli1l01Ol_dataout; + nli1l1Oil <= wire_nli1l01OO_dataout; + nli1l1OiO <= wire_nli1l001i_dataout; + nli1l1Oli <= wire_nli1l001l_dataout; + nli1l1Oll <= wire_nli1l0i1i_dataout; + nli1lilli <= wire_nli1liO0i_dataout; + nli1liO1O <= wire_nli1ll1li_dataout; + nli1ll1ii <= wire_nli1ll1ll_dataout; + nli1ll1il <= wire_nli1ll1lO_dataout; + nli1ll1iO <= wire_nli1ll1Oi_dataout; + nli1lliOO <= wire_nli1lO0li_dataout; + nli1llOiO <= wire_nli1lO0ll_dataout; + nli1llOli <= wire_nli1lO0lO_dataout; + nli1llOll <= wire_nli1lO0Oi_dataout; + nli1llOlO <= wire_nli1lO0Ol_dataout; + nli1llOOi <= wire_nli1lO0OO_dataout; + nli1llOOl <= wire_nli1lOi1i_dataout; + nli1llOOO <= wire_nli1lOi1l_dataout; + nli1lO00i <= wire_nli1lOl0O_dataout; + nli1lO00l <= wire_nli1lOlii_dataout; + nli1lO00O <= wire_nli1lOlil_dataout; + nli1lO01i <= wire_nli1lOl1O_dataout; + nli1lO01l <= wire_nli1lOl0i_dataout; + nli1lO01O <= wire_nli1lOl0l_dataout; + nli1lO0ii <= wire_nli1lOliO_dataout; + nli1lO0il <= wire_nli1lOlli_dataout; + nli1lO0iO <= wire_nli1lOlll_dataout; + nli1lO10i <= wire_nli1lOi0O_dataout; + nli1lO10l <= wire_nli1lOiii_dataout; + nli1lO10O <= wire_nli1lOiil_dataout; + nli1lO11i <= wire_nli1lOi1O_dataout; + nli1lO11l <= wire_nli1lOi0i_dataout; + nli1lO11O <= wire_nli1lOi0l_dataout; + nli1lO1ii <= wire_nli1lOiiO_dataout; + nli1lO1il <= wire_nli1lOili_dataout; + nli1lO1iO <= wire_nli1lOill_dataout; + nli1lO1li <= wire_nli1lOilO_dataout; + nli1lO1ll <= wire_nli1lOiOi_dataout; + nli1lO1lO <= wire_nli1lOiOl_dataout; + nli1lO1Oi <= wire_nli1lOiOO_dataout; + nli1lO1Ol <= wire_nli1lOl1i_dataout; + nli1lO1OO <= wire_nli1lOl1l_dataout; + nlii10Oii <= wire_nlii1i1lO_dataout; + nlii10Oil <= wire_nlii1i1Oi_dataout; + nlii10OiO <= wire_nlii1i1Ol_dataout; + nlii10Oli <= wire_nlii1i1OO_dataout; + nlii10Oll <= wire_nlii1i01i_dataout; + nlii10OlO <= wire_nlii1i01l_dataout; + nlii10OOi <= wire_nlii1i01O_dataout; + nlii10OOl <= wire_nlii1i00i_dataout; + nlii10OOO <= wire_nlii1i00l_dataout; + nlii1100i <= wire_nlii11O1i_dataout; + nlii1100l <= wire_nlii11O1l_dataout; + nlii1100O <= wire_nlii11O1O_dataout; + nlii1101i <= wire_nlii11lOi_dataout; + nlii1101l <= wire_nlii11lOl_dataout; + nlii1101O <= wire_nlii11lOO_dataout; + nlii110ii <= wire_nlii11O0i_dataout; + nlii110il <= wire_nlii11O0l_dataout; + nlii110iO <= wire_nlii11O0O_dataout; + nlii110li <= wire_nlii11Oii_dataout; + nlii110ll <= wire_nlii11Oil_dataout; + nlii110lO <= wire_nlii11OiO_dataout; + nlii110Oi <= wire_nlii11Oli_dataout; + nlii110Ol <= wire_nlii11Oll_dataout; + nlii110OO <= wire_nlii11OlO_dataout; + nlii1110i <= wire_nlii11l1i_dataout; + nlii1110l <= wire_nlii11l1l_dataout; + nlii1110O <= wire_nlii11l1O_dataout; + nlii1111i <= wire_nlii11iOi_dataout; + nlii1111l <= wire_nlii11iOl_dataout; + nlii1111O <= wire_nlii11iOO_dataout; + nlii111ii <= wire_nlii11l0i_dataout; + nlii111il <= wire_nlii11l0l_dataout; + nlii111iO <= wire_nlii11l0O_dataout; + nlii111li <= wire_nlii11lii_dataout; + nlii111ll <= wire_nlii11lil_dataout; + nlii111lO <= wire_nlii11liO_dataout; + nlii111Oi <= wire_nlii11lli_dataout; + nlii111Ol <= wire_nlii11lll_dataout; + nlii111OO <= wire_nlii11llO_dataout; + nlii11i0i <= wire_nlii1011i_dataout; + nlii11i0l <= wire_nlii1011l_dataout; + nlii11i0O <= wire_nlii1011O_dataout; + nlii11i1i <= wire_nlii11OOi_dataout; + nlii11i1l <= wire_nlii11OOl_dataout; + nlii11i1O <= wire_nlii11OOO_dataout; + nlii11iii <= wire_nlii1i1ll_dataout; + nlii1i10i <= wire_nlii1i0iO_dataout; + nlii1i10l <= wire_nlii1i0li_dataout; + nlii1i10O <= wire_nlii1i0ll_dataout; + nlii1i11i <= wire_nlii1i00O_dataout; + nlii1i11l <= wire_nlii1i0ii_dataout; + nlii1i11O <= wire_nlii1i0il_dataout; + nlii1i1ii <= wire_nlii1i0lO_dataout; + nlii1i1il <= wire_nlii1i0Oi_dataout; + nlii1i1iO <= wire_nlii1i0Ol_dataout; + nlii1i1li <= wire_nlii1l1lO_dataout; + nlii1illi <= wire_nlii1l1Oi_dataout; + nlii1illl <= wire_nlii1l1Ol_dataout; + nlii1illO <= wire_nlii1l1OO_dataout; + nlii1ilOi <= wire_nlii1l01i_dataout; + nlii1ilOl <= wire_nlii1l01l_dataout; + nlii1ilOO <= wire_nlii1l01O_dataout; + nlii1iO0i <= wire_nlii1l0ii_dataout; + nlii1iO0l <= wire_nlii1l0il_dataout; + nlii1iO0O <= wire_nlii1l0iO_dataout; + nlii1iO1i <= wire_nlii1l00i_dataout; + nlii1iO1l <= wire_nlii1l00l_dataout; + nlii1iO1O <= wire_nlii1l00O_dataout; + nlii1iOii <= wire_nlii1l0li_dataout; + nlii1iOil <= wire_nlii1l0ll_dataout; + nlii1iOiO <= wire_nlii1l0lO_dataout; + nlii1iOli <= wire_nlii1l0Oi_dataout; + nlii1iOll <= wire_nlii1l0Ol_dataout; + nlii1iOlO <= wire_nlii1l0OO_dataout; + nlii1iOOi <= wire_nlii1li1i_dataout; + nlii1iOOl <= wire_nlii1li1l_dataout; + nlii1iOOO <= wire_nlii1li1O_dataout; + nlii1l10i <= wire_nlii1liii_dataout; + nlii1l10l <= wire_nlii1liil_dataout; + nlii1l10O <= wire_nlii1liiO_dataout; + nlii1l11i <= wire_nlii1li0i_dataout; + nlii1l11l <= wire_nlii1li0l_dataout; + nlii1l11O <= wire_nlii1li0O_dataout; + nlii1l1ii <= wire_nlii1lili_dataout; + nlii1l1il <= wire_nlii1lill_dataout; + nlii1l1iO <= wire_nlii1lilO_dataout; + nlii1l1li <= wire_nlii1liOi_dataout; + nliii000i <= wire_nliii0O1O_dataout; + nliii0lOO <= wire_nliii0O0i_dataout; + nliii0O1i <= wire_nliii0O0l_dataout; + nliiOOiii <= wire_nliiOOiOl_dataout; + nliiOOiil <= wire_nliiOOiOO_dataout; + nliiOOiiO <= wire_nliiOOl1i_dataout; + nliiOOili <= wire_nliiOOl1l_dataout; + nliiOOill <= wire_nliiOOl1O_dataout; + nliiOOilO <= wire_nlil111Ol_dataout; + nlil000Oi <= wire_nlil00iOl_dataout; + nlil000Ol <= wire_nlil00iOO_dataout; + nlil000OO <= wire_nlil00l1i_dataout; + nlil00i0i <= wire_nlil00l0l_dataout; + nlil00i0l <= wire_nlil00l0O_dataout; + nlil00i0O <= wire_nlil00lii_dataout; + nlil00i1i <= wire_nlil00l1l_dataout; + nlil00i1l <= wire_nlil00l1O_dataout; + nlil00i1O <= wire_nlil00l0i_dataout; + nlil00iii <= wire_nlil00lil_dataout; + nlil00iil <= wire_nlil00liO_dataout; + nlil00iiO <= wire_nlil00lli_dataout; + nlil00ili <= wire_nlil00lll_dataout; + nlil00ill <= wire_nlil00llO_dataout; + nlil0100i <= wire_nlil01iiO_dataout; + nlil0100l <= wire_nlil01ili_dataout; + nlil0100O <= wire_nlil01ill_dataout; + nlil0101l <= wire_nlil01iii_dataout; + nlil0101O <= wire_nlil01iil_dataout; + nlil010ii <= wire_nlil01ilO_dataout; + nlil010il <= wire_nlil01iOi_dataout; + nlil010iO <= wire_nlil01iOl_dataout; + nlil010li <= wire_nlil01iOO_dataout; + nlil010ll <= wire_nlil01l1i_dataout; + nlil010lO <= wire_nlil01l1l_dataout; + nlil010Oi <= wire_nlil01l1O_dataout; + nlil010Ol <= wire_nlil01l0i_dataout; + nlil010OO <= wire_nlil01l0l_dataout; + nlil01i0i <= wire_nlil01liO_dataout; + nlil01i0l <= wire_nlil00iOi_dataout; + nlil01i1i <= wire_nlil01l0O_dataout; + nlil01i1l <= wire_nlil01lii_dataout; + nlil01i1O <= wire_nlil01lil_dataout; + nlil1100i <= wire_nlil110li_dataout; + nlil1100l <= wire_nlil110ll_dataout; + nlil1100O <= wire_nlil110lO_dataout; + nlil1101O <= wire_nlil110iO_dataout; + nlil110ii <= wire_nlil11l0l_dataout; + nlil111Oi <= wire_nlil110il_dataout; + nlil11l0i <= wire_nlil11Oli_dataout; + nlil11lll <= wire_nlil11Oll_dataout; + nlil11llO <= wire_nlil11OlO_dataout; + nlil11lOi <= wire_nlil11OOi_dataout; + nlil11lOl <= wire_nlil11OOl_dataout; + nlil11lOO <= wire_nlil11OOO_dataout; + nlil11O0i <= wire_nlil1010i_dataout; + nlil11O0l <= wire_nlil1010l_dataout; + nlil11O0O <= wire_nlil1010O_dataout; + nlil11O1i <= wire_nlil1011i_dataout; + nlil11O1l <= wire_nlil1011l_dataout; + nlil11O1O <= wire_nlil1011O_dataout; + nlil11Oii <= wire_nlil101ii_dataout; + nlil11Oil <= wire_nlil101il_dataout; + nlil11OiO <= wire_nlil1i00O_dataout; + nlil1i00i <= wire_nlil1i0ll_dataout; + nlil1i00l <= wire_nlil1lOll_dataout; + nlil1i01i <= wire_nlil1i0il_dataout; + nlil1i01l <= wire_nlil1i0iO_dataout; + nlil1i01O <= wire_nlil1i0li_dataout; + nlil1i1OO <= wire_nlil1i0ii_dataout; + nlil1llOi <= wire_nlil1lOlO_dataout; + nlil1llOl <= wire_nlil1lOOi_dataout; + nlil1llOO <= wire_nlil1lOOl_dataout; + nlil1lO0i <= wire_nliiOOO0O_dataout; + nlil1lO0l <= wire_nlil1O11i_dataout; + nlil1lO0O <= wire_nlil1O11l_dataout; + nlil1lO1i <= wire_nlil1lOOO_dataout; + nlil1lO1l <= wire_nlil111lO_dataout; + nlil1lO1O <= wire_nliiOOOOl_dataout; + nlil1lOii <= wire_nlil1O11O_dataout; + nlil1lOil <= wire_nlil1O10i_dataout; + nlil1lOiO <= wire_nliiOOiOi_dataout; + nlil1lOli <= wire_nlil1OOOi_dataout; + nlil1OOiO <= wire_nlil1OOOl_dataout; + nlil1OOli <= wire_nlil1OOOO_dataout; + nlil1OOll <= wire_nlil0111i_dataout; + nlil1OOlO <= wire_nlil01i0O_dataout; + nlilill1O <= wire_nlilillli_dataout; + nlilillil <= wire_nlilillll_dataout; + nlililliO <= wire_nlililllO_dataout; + nlililOii <= wire_nlililOll_dataout; + nlililOil <= wire_nlililOlO_dataout; + nlililOiO <= wire_nlililOOi_dataout; + nlililOli <= wire_nliliO01i_dataout; + nliliO10O <= wire_nliliO1ll_dataout; + nliliO11i <= wire_nliliO01l_dataout; + nliliO11l <= wire_nliliO01O_dataout; + nliliO11O <= wire_nliliO00i_dataout; + nliliO1ii <= wire_nliliO1lO_dataout; + nliliO1il <= wire_nliliO1Oi_dataout; + nliliO1iO <= wire_nliliO1Ol_dataout; + nliliO1li <= wire_nliliO1OO_dataout; + nlill0lll <= wire_nlill0OOi_dataout; + nlill0OlO <= wire_nlill0OOl_dataout; + nlill1i0O <= wire_nlill1lll_dataout; + nlill1l0O <= wire_nlill1llO_dataout; + nlill1lii <= wire_nlill1lOi_dataout; + nlill1lil <= wire_nlill1lOl_dataout; + nlill1liO <= wire_nlill1lOO_dataout; + nlill1lli <= wire_nlill00Ol_dataout; + END IF; + END PROCESS; + wire_nlill0Oll_w_lg_w_lg_w53924w53926w53930w(0) <= wire_nlill0Oll_w_lg_w53924w53926w(0) AND nl01l0i1i; + wire_nlill0Oll_w_lg_w_lg_w56923w56925w56926w(0) <= wire_nlill0Oll_w_lg_w56923w56925w(0) AND nl1ll0l1l; + wire_nlill0Oll_w_lg_w53924w53926w(0) <= wire_nlill0Oll_w53924w(0) AND wire_nlill0Oll_w_lg_nl01l0i1l53925w(0); + wire_nlill0Oll_w_lg_w56923w56925w(0) <= wire_nlill0Oll_w56923w(0) AND wire_nlill0Oll_w_lg_nl1ll0l1O56924w(0); + wire_nlill0Oll_w53924w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_w53916w53918w53920w53922w(0) AND wire_nlill0Oll_w_lg_nl01l0i1O53923w(0); + wire_nlill0Oll_w56923w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_w56915w56917w56919w56921w(0) AND wire_nlill0Oll_w_lg_nl1ll0l0i56922w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_w53916w53918w53920w53922w(0) <= wire_nlill0Oll_w_lg_w_lg_w53916w53918w53920w(0) AND wire_nlill0Oll_w_lg_nl01l0i0i53921w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_w56915w56917w56919w56921w(0) <= wire_nlill0Oll_w_lg_w_lg_w56915w56917w56919w(0) AND wire_nlill0Oll_w_lg_nl1ll0l0l56920w(0); + wire_nlill0Oll_w_lg_w_lg_w53916w53918w53920w(0) <= wire_nlill0Oll_w_lg_w53916w53918w(0) AND wire_nlill0Oll_w_lg_nl01l0i0l53919w(0); + wire_nlill0Oll_w_lg_w_lg_w53515w53863w53864w(0) <= wire_nlill0Oll_w_lg_w53515w53863w(0) AND nl01l0iOl; + wire_nlill0Oll_w_lg_w_lg_w56915w56917w56919w(0) <= wire_nlill0Oll_w_lg_w56915w56917w(0) AND wire_nlill0Oll_w_lg_nl1ll0l0O56918w(0); + wire_nlill0Oll_w_lg_w53916w53918w(0) <= wire_nlill0Oll_w53916w(0) AND wire_nlill0Oll_w_lg_nl01l0i0O53917w(0); + wire_nlill0Oll_w_lg_w53515w53863w(0) <= wire_nlill0Oll_w53515w(0) AND wire_nlill0Oll_w_lg_nl01l0iOO53574w(0); + wire_nlill0Oll_w_lg_w53515w53840w(0) <= wire_nlill0Oll_w53515w(0) AND nl01l0iOO; + wire_nlill0Oll_w_lg_w53846w53847w(0) <= wire_nlill0Oll_w53846w(0) AND nl01l0iOO; + wire_nlill0Oll_w_lg_w53748w53749w(0) <= wire_nlill0Oll_w53748w(0) AND nl11lO11O; + wire_nlill0Oll_w_lg_w56915w56917w(0) <= wire_nlill0Oll_w56915w(0) AND wire_nlill0Oll_w_lg_nl1ll0lii56916w(0); + wire_nlill0Oll_w53916w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0ili53910w53912w53914w(0) AND wire_nlill0Oll_w_lg_nl01l0iii53915w(0); + wire_nlill0Oll_w53577w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0iOO53574w53575w53576w(0) AND wire_nlill0Oll_w_lg_nl01l0ilO53520w(0); + wire_nlill0Oll_w53515w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53514w(0) AND nl01l0l1i; + wire_nlill0Oll_w53511w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53510w(0) AND nl01l0l1i; + wire_nlill0Oll_w53846w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53504w53844w(0) AND wire_nlill0Oll_w_lg_nl01l0l1i53845w(0); + wire_nlill0Oll_w53867w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53504w53844w(0) AND nl01l0l1i; + wire_nlill0Oll_w53506w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53504w53505w(0) AND nl01l0l1i; + wire_nlill0Oll_w60217w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl0i00i0l60213w60214w60216w(0) AND nl0i00i1l; + wire_nlill0Oll_w52435w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52429w(0) AND nl0l11Oii; + wire_nlill0Oll_w52442w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52438w(0) AND nl0l11Oii; + wire_nlill0Oll_w52450w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52446w(0) AND nl0l11Oii; + wire_nlill0Oll_w52457w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52453w(0) AND nl0l11Oii; + wire_nlill0Oll_w52490w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11OOO52342w52344w52346w(0) AND nl0l11OlO; + wire_nlill0Oll_w53748w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lO1ii45155w45157w53747w(0) AND nl11lO10i; + wire_nlill0Oll_w45159w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lO1ii45155w45157w45158w(0) AND nl11lO10i; + wire_nlill0Oll_w53689w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOlOO44945w44946w52768w(0) AND nl11lOllO; + wire_nlill0Oll_w56915w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl1ll0lll56909w56911w56913w(0) AND wire_nlill0Oll_w_lg_nl1ll0lil56914w(0); + wire_nlill0Oll_w_lg_w47757w47758w(0) <= wire_nlill0Oll_w47757w(0) AND nl0OiOl0l; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0iOO53517w53518w53519w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0iOO53517w53518w(0) AND nl01l0ilO; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53500w53501w53502w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53500w53501w(0) AND nl01l0l1i; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l1010l52106w52107w52108w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l1010l52106w52107w(0) AND nl0iOl10i; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l1010l52099w52100w52101w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l1010l52099w52100w(0) AND nl0iOl10i; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52460w52467w52471w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52460w52467w(0) AND nl0l11Oii; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52475w52478w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52475w(0) AND nl0l11Oii; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52474w52481w52484w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52481w(0) AND nl0l11Oii; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0ili53910w53912w53914w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0ili53910w53912w(0) AND wire_nlill0Oll_w_lg_nl01l0iil53913w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0iOO53574w53575w53576w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0iOO53574w53575w(0) AND wire_nlill0Oll_w_lg_nl01l0iOi53523w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53514w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53509w(0) AND wire_nlill0Oll_w_lg_nl01l0l1l53513w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53509w53510w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53509w(0) AND nl01l0l1l; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53504w53844w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53504w(0) AND wire_nlill0Oll_w_lg_nl01l0l1l53513w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0l0i53503w53504w53505w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53504w(0) AND nl01l0l1l; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0i00i0l60213w60214w60216w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0i00i0l60213w60214w(0) AND wire_nlill0Oll_w_lg_nl0i00i1O60215w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52429w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52427w(0) AND wire_nlill0Oll_w_lg_nl0l11Oil52428w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52427w52438w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52427w(0) AND nl0l11Oil; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52446w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52445w(0) AND wire_nlill0Oll_w_lg_nl0l11Oil52428w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11Oli52425w52445w52453w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52445w(0) AND nl0l11Oil; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l11OOO52342w52344w52346w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0l11OOO52342w52344w(0) AND wire_nlill0Oll_w_lg_nl0l11OOi52345w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl111ll1i61431w61433w61435w(0) <= wire_nlill0Oll_w_lg_w_lg_nl111ll1i61431w61433w(0) AND wire_nlill0Oll_w_lg_nl111liOl61434w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lO1ii45155w45157w53747w(0) <= wire_nlill0Oll_w_lg_w_lg_nl11lO1ii45155w45157w(0) AND wire_nlill0Oll_w_lg_nl11lO10l53746w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lO1ii45155w45157w45158w(0) <= wire_nlill0Oll_w_lg_w_lg_nl11lO1ii45155w45157w(0) AND nl11lO10l; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOlOO44945w44946w52768w(0) <= wire_nlill0Oll_w_lg_w_lg_nl11lOlOO44945w44946w(0) AND wire_nlill0Oll_w_lg_nl11lOlOi45152w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOlOO44945w44946w52772w(0) <= wire_nlill0Oll_w_lg_w_lg_nl11lOlOO44945w44946w(0) AND nl11lOlOi; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOO1i45149w45150w45151w(0) <= wire_nlill0Oll_w_lg_w_lg_nl11lOO1i45149w45150w(0) AND nl11lOlOl; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl11lOO1l45164w45165w45166w(0) <= wire_nlill0Oll_w_lg_w_lg_nl11lOO1l45164w45165w(0) AND nl11lOlOO; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl1iiO0li56217w56224w56225w(0) <= wire_nlill0Oll_w_lg_w_lg_nl1iiO0li56217w56224w(0) AND niOi1l0Ol; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl1ll0lll56909w56911w56913w(0) <= wire_nlill0Oll_w_lg_w_lg_nl1ll0lll56909w56911w(0) AND wire_nlill0Oll_w_lg_nl1ll0liO56912w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl1OllOOO54880w54882w54884w(0) <= wire_nlill0Oll_w_lg_w_lg_nl1OllOOO54880w54882w(0) AND wire_nlill0Oll_w_lg_nl1Ol011O54883w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nlii110Ol44999w45000w45001w(0) <= wire_nlill0Oll_w_lg_w_lg_nlii110Ol44999w45000w(0) AND nlii110lO; + wire_nlill0Oll_w_lg_w_lg_w_lg_nlii110Ol44999w45002w45003w(0) <= wire_nlill0Oll_w_lg_w_lg_nlii110Ol44999w45002w(0) AND nlii110lO; + wire_nlill0Oll_w47757w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl0OiOl0i46167w47752w47753w(0) AND wire_nl0Ol1i0l_w_lg_w_lg_o47754w47756w(0); + wire_nlill0Oll_w_lg_w_lg_nl01l0iOO53517w53518w(0) <= wire_nlill0Oll_w_lg_nl01l0iOO53517w(0) AND nl01l0iOi; + wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53500w53501w(0) <= wire_nlill0Oll_w_lg_nl01l0l0i53500w(0) AND nl01l0l1l; + wire_nlill0Oll_w_lg_w_lg_nl01l0l0l53569w53570w(0) <= wire_nlill0Oll_w_lg_nl01l0l0l53569w(0) AND wire_nl01il01i_o; + wire_nlill0Oll_w_lg_w_lg_nl01l0liO53449w53450w(0) <= wire_nlill0Oll_w_lg_nl01l0liO53449w(0) AND niOi000li; + wire_nlill0Oll_w_lg_w_lg_nl01l0liO53445w53446w(0) <= wire_nlill0Oll_w_lg_nl01l0liO53445w(0) AND niOi0lOOl; + wire_nlill0Oll_w_lg_w_lg_nl01l0O1l47777w47778w(0) <= wire_nlill0Oll_w_lg_nl01l0O1l47777w(0) AND nli111i1l; + wire_nlill0Oll_w_lg_w_lg_nl0i00i0l60222w60223w(0) <= wire_nlill0Oll_w_lg_nl0i00i0l60222w(0) AND nl0i00i0O; + wire_nlill0Oll_w_lg_w_lg_nl0l1010l52106w52107w(0) <= wire_nlill0Oll_w_lg_nl0l1010l52106w(0) AND niOii1l1O; + wire_nlill0Oll_w_lg_w_lg_nl0l1010l52099w52100w(0) <= wire_nlill0Oll_w_lg_nl0l1010l52099w(0) AND niOii1l1O; + wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52460w52467w(0) <= wire_nlill0Oll_w_lg_nl0l11Oli52460w(0) AND nl0l11Oil; + wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52475w(0) <= wire_nlill0Oll_w_lg_nl0l11Oli52474w(0) AND wire_nlill0Oll_w_lg_nl0l11Oil52428w(0); + wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52474w52481w(0) <= wire_nlill0Oll_w_lg_nl0l11Oli52474w(0) AND nl0l11Oil; + wire_nlill0Oll_w_lg_w_lg_nl1OilOii5684w5685w(0) <= wire_nlill0Oll_w_lg_nl1OilOii5684w(0) AND wire_nl1000i_w_lg_nli1i1ll5104w(0); + wire_nlill0Oll_w_lg_w_lg_nl1OO010i54591w54592w(0) <= wire_nlill0Oll_w_lg_nl1OO010i54591w(0) AND niOi1OOOi; + wire_nlill0Oll_w_lg_w_lg_nlii110Ol44995w45005w(0) <= wire_nlill0Oll_w_lg_nlii110Ol44995w(0) AND nlii110lO; + wire_nlill0Oll_w_lg_w_lg_nlii110Ol45007w45010w(0) <= wire_nlill0Oll_w_lg_nlii110Ol45007w(0) AND nlii110lO; + wire_nlill0Oll_w_lg_w_lg_nl00lliOl54160w54166w(0) <= wire_nlill0Oll_w_lg_nl00lliOl54160w(0) AND nl00lliOi; + wire_nlill0Oll_w_lg_w_lg_nl011ll1l54087w54088w(0) <= wire_nlill0Oll_w_lg_nl011ll1l54087w(0) AND nl10lliOO; + wire_nlill0Oll_w_lg_w_lg_nl01l01Oi53740w53741w(0) <= wire_nlill0Oll_w_lg_nl01l01Oi53740w(0) AND nl01l01lO; + wire_nlill0Oll_w_lg_w_lg_nl01l0ili53910w53912w(0) <= wire_nlill0Oll_w_lg_nl01l0ili53910w(0) AND wire_nlill0Oll_w_lg_nl01l0iiO53911w(0); + wire_nlill0Oll_w_lg_w_lg_nl01l0iOO53574w53575w(0) <= wire_nlill0Oll_w_lg_nl01l0iOO53574w(0) AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0); + wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53509w(0) <= wire_nlill0Oll_w_lg_nl01l0l0i53503w(0) AND wire_nlill0Oll_w_lg_nl01l0l1O53508w(0); + wire_nlill0Oll_w_lg_w_lg_nl01l0l0i53503w53504w(0) <= wire_nlill0Oll_w_lg_nl01l0l0i53503w(0) AND nl01l0l1O; + wire_nlill0Oll_w_lg_w_lg_nl0i000Ol59482w59488w(0) <= wire_nlill0Oll_w_lg_nl0i000Ol59482w(0) AND nl0i000Oi; + wire_nlill0Oll_w_lg_w_lg_nl0i00i0l60213w60214w(0) <= wire_nlill0Oll_w_lg_nl0i00i0l60213w(0) AND nl0i00i0i; + wire_nlill0Oll_w_lg_w_lg_nl0iOil0l44799w47578w(0) <= wire_nlill0Oll_w_lg_nl0iOil0l44799w(0) AND wire_nli0i1i0l_dataout; + wire_nlill0Oll_w_lg_w_lg_nl0iOil0O47059w47236w(0) <= wire_nlill0Oll_w_lg_nl0iOil0O47059w(0) AND wire_nli0i011i_dataout; + wire_nlill0Oll_w_lg_w_lg_nl0iOil0O47059w47060w(0) <= wire_nlill0Oll_w_lg_nl0iOil0O47059w(0) AND wire_nli0O1O1l_dataout; + wire_nlill0Oll_w_lg_w_lg_nl0iOiO1O47492w47505w(0) <= wire_nlill0Oll_w_lg_nl0iOiO1O47492w(0) AND wire_nli0ilOiO_w_lg_dataout47504w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47539w(0) <= wire_nlill0Oll_w_lg_nl0iOiOii46913w(0) AND wire_nli0il1iO_w_lg_dataout47538w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47507w(0) <= wire_nlill0Oll_w_lg_nl0iOiOii46913w(0) AND wire_nli0il1li_w_lg_dataout47506w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47442w(0) <= wire_nlill0Oll_w_lg_nl0iOiOii46913w(0) AND wire_nli0il1lO_w_lg_dataout47441w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47289w(0) <= wire_nlill0Oll_w_lg_nl0iOiOii46913w(0) AND wire_nli0ilili_w_lg_dataout47288w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47258w(0) <= wire_nlill0Oll_w_lg_nl0iOiOii46913w(0) AND wire_nli0ilill_w_lg_dataout47257w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w46925w(0) <= wire_nlill0Oll_w_lg_nl0iOiOii46913w(0) AND wire_nli0illii_w_lg_dataout46924w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47290w(0) <= wire_nlill0Oll_w_lg_nl0iOiOiO47246w(0) AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47289w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47259w(0) <= wire_nlill0Oll_w_lg_nl0iOiOiO47246w(0) AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47258w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47707w(0) <= wire_nlill0Oll_w_lg_nl0iOiOiO47246w(0) AND wire_nli0il10i_w_lg_dataout47706w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47638w(0) <= wire_nlill0Oll_w_lg_nl0iOiOiO47246w(0) AND wire_nli0il10O_w_lg_dataout47637w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47350w(0) <= wire_nlill0Oll_w_lg_nl0iOiOiO47246w(0) AND wire_nli0iliil_w_lg_dataout47349w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47355w(0) <= wire_nlill0Oll_w_lg_nl0iOiOOl47245w(0) AND wire_nli0i000O_w_lg_dataout47354w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47324w(0) <= wire_nlill0Oll_w_lg_nl0iOiOOl47245w(0) AND wire_nli0i00ii_w_lg_dataout47323w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47295w(0) <= wire_nlill0Oll_w_lg_nl0iOiOOl47245w(0) AND wire_nli0i00il_w_lg_dataout47294w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47264w(0) <= wire_nlill0Oll_w_lg_nl0iOiOOl47245w(0) AND wire_nli0i00iO_w_lg_dataout47263w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47712w(0) <= wire_nlill0Oll_w_lg_nl0iOiOOl47245w(0) AND wire_nli0i01OO_w_lg_dataout47711w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47573w(0) <= wire_nlill0Oll_w_lg_nl0iOiOOl47245w(0) AND wire_nli0i0l0O_w_lg_dataout47572w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47710w(0) <= wire_nlill0Oll_w_lg_nl0iOl11l47151w(0) AND wire_nli0i0l1l_w_lg_dataout47709w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47230w(0) <= wire_nlill0Oll_w_lg_nl0iOl11l47151w(0) AND wire_nli0i0O1l_w_lg_dataout47229w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47199w(0) <= wire_nlill0Oll_w_lg_nl0iOl11l47151w(0) AND wire_nli0ii10l_w_lg_dataout47198w(0); + wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47167w(0) <= wire_nlill0Oll_w_lg_nl0iOl11l47151w(0) AND wire_nli0ii10O_w_lg_dataout47166w(0); + wire_nlill0Oll_w_lg_w_lg_nl0l0Oill46193w51964w(0) <= wire_nlill0Oll_w_lg_nl0l0Oill46193w(0) AND niOii01il; + wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52427w(0) <= wire_nlill0Oll_w_lg_nl0l11Oli52425w(0) AND wire_nlill0Oll_w_lg_nl0l11OiO52426w(0); + wire_nlill0Oll_w_lg_w_lg_nl0l11Oli52425w52445w(0) <= wire_nlill0Oll_w_lg_nl0l11Oli52425w(0) AND nl0l11OiO; + wire_nlill0Oll_w_lg_w_lg_nl0l11OOO52342w52344w(0) <= wire_nlill0Oll_w_lg_nl0l11OOO52342w(0) AND wire_nlill0Oll_w_lg_nl0l11OOl52343w(0); + wire_nlill0Oll_w_lg_w_lg_nl111ll1i61431w61433w(0) <= wire_nlill0Oll_w_lg_nl111ll1i61431w(0) AND wire_nlill0Oll_w_lg_nl111liOO61432w(0); + wire_nlill0Oll_w_lg_w_lg_nl11lO1ii45155w45157w(0) <= wire_nlill0Oll_w_lg_nl11lO1ii45155w(0) AND wire_nlill0Oll_w_lg_nl11lO10O45156w(0); + wire_nlill0Oll_w_lg_w_lg_nl11lOlOO44945w44946w(0) <= wire_nlill0Oll_w_lg_nl11lOlOO44945w(0) AND wire_nlill0Oll_w_lg_nl11lOlOl43385w(0); + wire_nlill0Oll_w_lg_w_lg_nl11lOO1i45149w45150w(0) <= wire_nlill0Oll_w_lg_nl11lOO1i45149w(0) AND wire_nlill0Oll_w_lg_nl11lOlOO44945w(0); + wire_nlill0Oll_w_lg_w_lg_nl11lOO1l45164w45165w(0) <= wire_nlill0Oll_w_lg_nl11lOO1l45164w(0) AND nl11lOO1i; + wire_nlill0Oll_w_lg_w_lg_nl11OiliO60228w60229w(0) <= wire_nlill0Oll_w_lg_nl11OiliO60228w(0) AND nlOi1O0O; + wire_nlill0Oll_w_lg_w_lg_nl1iiO0li56217w56224w(0) <= wire_nlill0Oll_w_lg_nl1iiO0li56217w(0) AND nl1iil0Ol; + wire_nlill0Oll_w_lg_w_lg_nl1ll0lll56909w56911w(0) <= wire_nlill0Oll_w_lg_nl1ll0lll56909w(0) AND wire_nlill0Oll_w_lg_nl1ll0lli56910w(0); + wire_nlill0Oll_w_lg_w_lg_nl1ll0llO55838w55842w(0) <= wire_nlill0Oll_w_lg_nl1ll0llO55838w(0) AND nl1ll0iil; + wire_nlill0Oll_w_lg_w_lg_nl1Oillll55053w55054w(0) <= wire_nlill0Oll_w_lg_nl1Oillll55053w(0) AND nl1Oillli; + wire_nlill0Oll_w_lg_w_lg_nl1Ol1l0l55394w55395w(0) <= wire_nlill0Oll_w_lg_nl1Ol1l0l55394w(0) AND wire_nl1lOOO0l_dataout; + wire_nlill0Oll_w_lg_w_lg_nl1OllOOO54880w54882w(0) <= wire_nlill0Oll_w_lg_nl1OllOOO54880w(0) AND wire_nlill0Oll_w_lg_nl1OllOOl54881w(0); + wire_nlill0Oll_w_lg_w_lg_nl1OOii1l8961w55191w(0) <= wire_nlill0Oll_w_lg_nl1OOii1l8961w(0) AND niOi1OliO; + wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48085w(0) <= wire_nlill0Oll_w_lg_nli10011i48069w(0) AND nli101ilO; + wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48079w(0) <= wire_nlill0Oll_w_lg_nli10011i48069w(0) AND nli101lOl; + wire_nlill0Oll_w_lg_w_lg_nli10011i48069w48091w(0) <= wire_nlill0Oll_w_lg_nli10011i48069w(0) AND nli11OOOO; + wire_nlill0Oll_w_lg_w_lg_nli1illll47936w47937w(0) <= wire_nlill0Oll_w_lg_nli1illll47936w(0) AND niOiliiOi; + wire_nlill0Oll_w_lg_w_lg_nli1illlO47940w47941w(0) <= wire_nlill0Oll_w_lg_nli1illlO47940w(0) AND niOilil1l; + wire_nlill0Oll_w_lg_w_lg_nli1iOilO42904w42905w(0) <= wire_nlill0Oll_w_lg_nli1iOilO42904w(0) AND nli1iOill; + wire_nlill0Oll_w_lg_w_lg_nlii110Ol44999w45000w(0) <= wire_nlill0Oll_w_lg_nlii110Ol44999w(0) AND wire_nlill0Oll_w_lg_nlii110Oi44994w(0); + wire_nlill0Oll_w_lg_w_lg_nlii110Ol44999w45002w(0) <= wire_nlill0Oll_w_lg_nlii110Ol44999w(0) AND nlii110Oi; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl0OiOl0i46167w47752w47753w(0) <= wire_nlill0Oll_w_lg_w_lg_nl0OiOl0i46167w47752w(0) AND niOiiO00i; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl1ll0iiO55841w55843w55844w(0) <= wire_nlill0Oll_w_lg_w_lg_nl1ll0iiO55841w55843w(0) AND niOi1Ol0i; + wire_nlill0Oll_w_lg_w_lg_nl01ii1lO45016w45017w(0) <= wire_nlill0Oll_w_lg_nl01ii1lO45016w(0) AND niOililOl; + wire_nlill0Oll_w_lg_w_lg_nl01l0llO53572w53594w(0) <= wire_nlill0Oll_w_lg_nl01l0llO53572w(0) AND wire_w_lg_w_lg_w_lg_w53583w53586w53589w53593w(0); + wire_nlill0Oll_w_lg_w_lg_nl01l0llO53591w53592w(0) <= wire_nlill0Oll_w_lg_nl01l0llO53591w(0) AND wire_w_lg_niOi001iO53573w(0); + wire_nlill0Oll_w_lg_nl00lliOl54169w(0) <= nl00lliOl AND wire_nlill0Oll_w_lg_nl00lliOi54161w(0); + wire_nlill0Oll_w_lg_nl011l1ii52064w(0) <= nl011l1ii AND wire_w_lg_niOii1Oll52063w(0); + wire_nlill0Oll_w_lg_nl01l0iOO53528w(0) <= nl01l0iOO AND wire_nlill0Oll_w_lg_nl01l0iOl53527w(0); + wire_nlill0Oll_w_lg_nl01l0iOO53517w(0) <= nl01l0iOO AND nl01l0iOl; + wire_nlill0Oll_w_lg_nl01l0l0i53500w(0) <= nl01l0l0i AND nl01l0l1O; + wire_nlill0Oll_w_lg_nl01l0l0l53569w(0) <= nl01l0l0l AND wire_nlill0Oll_w_lg_nl01l0lli53568w(0); + wire_nlill0Oll_w_lg_nl01l0liO53452w(0) <= nl01l0liO AND wire_nli1lli0i_w_lg_dataout53447w(0); + wire_nlill0Oll_w_lg_nl01l0liO53449w(0) <= nl01l0liO AND wire_w_lg_w_lg_niOi000lO53415w53448w(0); + wire_nlill0Oll_w_lg_nl01l0liO53445w(0) <= nl01l0liO AND wire_w_lg_niOi0lOii53444w(0); + wire_nlill0Oll_w_lg_nl01l0lll53411w(0) <= nl01l0lll AND nl01l0ill; + wire_nlill0Oll_w_lg_nl01l0llO53420w(0) <= nl01l0llO AND wire_nl01iOO1l_w_lg_o53419w(0); + wire_nlill0Oll_w_lg_nl01l0lOi53433w(0) <= nl01l0lOi AND wire_w_lg_niOi000lO53415w(0); + wire_nlill0Oll_w_lg_nl01l0lOi53417w(0) <= nl01l0lOi AND wire_nlill0Oll_w_lg_nl01l0lii53416w(0); + wire_nlill0Oll_w_lg_nl01l0lOi53435w(0) <= nl01l0lOi AND nl01l0lii; + wire_nlill0Oll_w_lg_nl01l0lOl53382w(0) <= nl01l0lOl AND wire_nli1lli0l_w_lg_dataout53381w(0); + wire_nlill0Oll_w_lg_nl01l0O1l47777w(0) <= nl01l0O1l AND wire_nli0O1OOO_dataout; + wire_nlill0Oll_w_lg_nl0i000Ol59491w(0) <= nl0i000Ol AND wire_nlill0Oll_w_lg_nl0i000Oi59483w(0); + wire_nlill0Oll_w_lg_nl0i00i0l60222w(0) <= nl0i00i0l AND wire_nlill0Oll_w_lg_nl0i00i0i60221w(0); + wire_nlill0Oll_w_lg_nl0iOiili47730w(0) <= nl0iOiili AND wire_nli000Oli_w_lg_w_lg_dataout47728w47729w(0); + wire_nlill0Oll_w_lg_nl0iOiili47691w(0) <= nl0iOiili AND wire_nli000Oll_w_lg_w_lg_dataout47689w47690w(0); + wire_nlill0Oll_w_lg_nl0iOiili47657w(0) <= nl0iOiili AND wire_nli000OlO_w_lg_w_lg_dataout47655w47656w(0); + wire_nlill0Oll_w_lg_nl0iOiili47623w(0) <= nl0iOiili AND wire_nli000OOi_w_lg_w_lg_dataout47621w47622w(0); + wire_nlill0Oll_w_lg_nl0iOiili47589w(0) <= nl0iOiili AND wire_nli000OOl_w_lg_w_lg_dataout47587w47588w(0); + wire_nlill0Oll_w_lg_nl0iOiili47555w(0) <= nl0iOiili AND wire_nli000OOO_w_lg_w_lg_dataout47553w47554w(0); + wire_nlill0Oll_w_lg_nl0iOiili46970w(0) <= nl0iOiili AND wire_nli00i00i_w_lg_w_lg_dataout46968w46969w(0); + wire_nlill0Oll_w_lg_nl0iOiili46940w(0) <= nl0iOiili AND wire_nli00i00l_w_lg_w_lg_dataout46938w46939w(0); + wire_nlill0Oll_w_lg_nl0iOiili46911w(0) <= nl0iOiili AND wire_nli00i00O_w_lg_w_lg_dataout46909w46910w(0); + wire_nlill0Oll_w_lg_nl0iOiili47057w(0) <= nl0iOiili AND wire_nli00i01i_w_lg_w_lg_dataout47055w47056w(0); + wire_nlill0Oll_w_lg_nl0iOiili47027w(0) <= nl0iOiili AND wire_nli00i01l_w_lg_w_lg_dataout47025w47026w(0); + wire_nlill0Oll_w_lg_nl0iOiili46998w(0) <= nl0iOiili AND wire_nli00i01O_w_lg_w_lg_dataout46996w46997w(0); + wire_nlill0Oll_w_lg_nl0iOiili46883w(0) <= nl0iOiili AND wire_nli00i0ii_w_lg_w_lg_dataout46881w46882w(0); + wire_nlill0Oll_w_lg_nl0iOiili46855w(0) <= nl0iOiili AND wire_nli00i0il_w_lg_w_lg_dataout46853w46854w(0); + wire_nlill0Oll_w_lg_nl0iOiili46828w(0) <= nl0iOiili AND wire_nli00i0iO_w_lg_w_lg_dataout46826w46827w(0); + wire_nlill0Oll_w_lg_nl0iOiili46801w(0) <= nl0iOiili AND wire_nli00i0li_w_lg_w_lg_dataout46799w46800w(0); + wire_nlill0Oll_w_lg_nl0iOiili46774w(0) <= nl0iOiili AND wire_nli00i0ll_w_lg_w_lg_dataout46772w46773w(0); + wire_nlill0Oll_w_lg_nl0iOiili47428w(0) <= nl0iOiili AND wire_nli00i10i_w_lg_w_lg_dataout47426w47427w(0); + wire_nlill0Oll_w_lg_nl0iOiili47399w(0) <= nl0iOiili AND wire_nli00i10l_w_lg_w_lg_dataout47397w47398w(0); + wire_nlill0Oll_w_lg_nl0iOiili47368w(0) <= nl0iOiili AND wire_nli00i10O_w_lg_w_lg_dataout47366w47367w(0); + wire_nlill0Oll_w_lg_nl0iOiili47524w(0) <= nl0iOiili AND wire_nli00i11i_w_lg_w_lg_dataout47522w47523w(0); + wire_nlill0Oll_w_lg_nl0iOiili47490w(0) <= nl0iOiili AND wire_nli00i11l_w_lg_w_lg_dataout47488w47489w(0); + wire_nlill0Oll_w_lg_nl0iOiili47460w(0) <= nl0iOiili AND wire_nli00i11O_w_lg_w_lg_dataout47458w47459w(0); + wire_nlill0Oll_w_lg_nl0iOiili47337w(0) <= nl0iOiili AND wire_nli00i1ii_w_lg_w_lg_dataout47335w47336w(0); + wire_nlill0Oll_w_lg_nl0iOiili47306w(0) <= nl0iOiili AND wire_nli00i1il_w_lg_w_lg_dataout47304w47305w(0); + wire_nlill0Oll_w_lg_nl0iOiili47276w(0) <= nl0iOiili AND wire_nli00i1iO_w_lg_w_lg_dataout47274w47275w(0); + wire_nlill0Oll_w_lg_nl0iOiili47243w(0) <= nl0iOiili AND wire_nli00i1li_w_lg_w_lg_dataout47241w47242w(0); + wire_nlill0Oll_w_lg_nl0iOiili47214w(0) <= nl0iOiili AND wire_nli00i1ll_w_lg_w_lg_dataout47212w47213w(0); + wire_nlill0Oll_w_lg_nl0iOiili47181w(0) <= nl0iOiili AND wire_nli00i1lO_w_lg_w_lg_dataout47179w47180w(0); + wire_nlill0Oll_w_lg_nl0iOiili47149w(0) <= nl0iOiili AND wire_nli00i1Oi_w_lg_w_lg_dataout47147w47148w(0); + wire_nlill0Oll_w_lg_nl0iOiili47121w(0) <= nl0iOiili AND wire_nli00i1Ol_w_lg_w_lg_dataout47119w47120w(0); + wire_nlill0Oll_w_lg_nl0iOiili47090w(0) <= nl0iOiili AND wire_nli00i1OO_w_lg_w_lg_dataout47088w47089w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47716w(0) <= nl0iOiilO AND wire_nli00i0OO_w_lg_w_lg_dataout47714w47715w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47577w(0) <= nl0iOiilO AND wire_nli00ii0i_w_lg_w_lg_dataout47575w47576w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47546w(0) <= nl0iOiilO AND wire_nli00ii0l_w_lg_w_lg_dataout47544w47545w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47514w(0) <= nl0iOiilO AND wire_nli00ii0O_w_lg_w_lg_dataout47512w47513w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47678w(0) <= nl0iOiilO AND wire_nli00ii1i_w_lg_w_lg_dataout47676w47677w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47645w(0) <= nl0iOiilO AND wire_nli00ii1l_w_lg_w_lg_dataout47643w47644w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47611w(0) <= nl0iOiilO AND wire_nli00ii1O_w_lg_w_lg_dataout47609w47610w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47480w(0) <= nl0iOiilO AND wire_nli00iiii_w_lg_w_lg_dataout47478w47479w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47450w(0) <= nl0iOiilO AND wire_nli00iiil_w_lg_w_lg_dataout47448w47449w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47419w(0) <= nl0iOiilO AND wire_nli00iiiO_w_lg_w_lg_dataout47417w47418w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47389w(0) <= nl0iOiilO AND wire_nli00iili_w_lg_w_lg_dataout47387w47388w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47359w(0) <= nl0iOiilO AND wire_nli00iill_w_lg_w_lg_dataout47357w47358w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47328w(0) <= nl0iOiilO AND wire_nli00iilO_w_lg_w_lg_dataout47326w47327w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47299w(0) <= nl0iOiilO AND wire_nli00iiOi_w_lg_w_lg_dataout47297w47298w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47268w(0) <= nl0iOiilO AND wire_nli00iiOl_w_lg_w_lg_dataout47266w47267w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47235w(0) <= nl0iOiilO AND wire_nli00iiOO_w_lg_w_lg_dataout47233w47234w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47113w(0) <= nl0iOiilO AND wire_nli00il0i_w_lg_w_lg_dataout47111w47112w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47081w(0) <= nl0iOiilO AND wire_nli00il0l_w_lg_w_lg_dataout47079w47080w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47048w(0) <= nl0iOiilO AND wire_nli00il0O_w_lg_w_lg_dataout47046w47047w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47204w(0) <= nl0iOiilO AND wire_nli00il1i_w_lg_w_lg_dataout47202w47203w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47172w(0) <= nl0iOiilO AND wire_nli00il1l_w_lg_w_lg_dataout47170w47171w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47141w(0) <= nl0iOiilO AND wire_nli00il1O_w_lg_w_lg_dataout47139w47140w(0); + wire_nlill0Oll_w_lg_nl0iOiilO47020w(0) <= nl0iOiilO AND wire_nli00ilii_w_lg_w_lg_dataout47018w47019w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46992w(0) <= nl0iOiilO AND wire_nli00ilil_w_lg_w_lg_dataout46990w46991w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46963w(0) <= nl0iOiilO AND wire_nli00iliO_w_lg_w_lg_dataout46961w46962w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46934w(0) <= nl0iOiilO AND wire_nli00illi_w_lg_w_lg_dataout46932w46933w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46904w(0) <= nl0iOiilO AND wire_nli00illl_w_lg_w_lg_dataout46902w46903w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46876w(0) <= nl0iOiilO AND wire_nli00illO_w_lg_w_lg_dataout46874w46875w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46849w(0) <= nl0iOiilO AND wire_nli00ilOi_w_lg_w_lg_dataout46847w46848w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46822w(0) <= nl0iOiilO AND wire_nli00ilOl_w_lg_w_lg_dataout46820w46821w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46796w(0) <= nl0iOiilO AND wire_nli00ilOO_w_lg_w_lg_dataout46794w46795w(0); + wire_nlill0Oll_w_lg_nl0iOiilO46769w(0) <= nl0iOiilO AND wire_nli00iO1i_w_lg_w_lg_dataout46767w46768w(0); + wire_nlill0Oll_w_lg_nl0iOil0i51895w(0) <= nl0iOil0i AND wire_nlill0Oll_w_lg_nl0iOiOOl51894w(0); + wire_nlill0Oll_w_lg_nl0iOil1i48208w(0) <= nl0iOil1i AND wire_nlill0Oll_w_lg_nl0iOl11O48207w(0); + wire_nlill0Oll_w_lg_nl0iOil1O51899w(0) <= nl0iOil1O AND wire_nlill0Oll_w_lg_nl0iOiOiO51898w(0); + wire_nlill0Oll_w_lg_nl0iOiO0i46164w(0) <= nl0iOiO0i AND wire_w_lg_niOili1OO45976w(0); + wire_nlill0Oll_w_lg_nl0iOiOiO51898w(0) <= nl0iOiOiO AND niOili01O; + wire_nlill0Oll_w_lg_nl0iOiOli51901w(0) <= nl0iOiOli AND niOili01O; + wire_nlill0Oll_w_lg_nl0iOiOll51904w(0) <= nl0iOiOll AND wire_w_lg_w_k_conf_range1869w51903w(0); + wire_nlill0Oll_w_lg_nl0iOiOOl51894w(0) <= nl0iOiOOl AND niOili01O; + wire_nlill0Oll_w_lg_nl0iOl11O48207w(0) <= nl0iOl11O AND wire_nl1000i_w_lg_w_lg_niOOi1i1i44005w48206w(0); + wire_nlill0Oll_w_lg_nl0l010lO43938w(0) <= nl0l010lO AND wire_nlill0Oll_w_lg_nlil00ill43937w(0); + wire_nlill0Oll_w_lg_nl0l1010l52106w(0) <= nl0l1010l AND wire_w_lg_niOi0OliO52105w(0); + wire_nlill0Oll_w_lg_nl0l1010l52099w(0) <= nl0l1010l AND niOi0OliO; + wire_nlill0Oll_w_lg_nl0l11Oli52460w(0) <= nl0l11Oli AND wire_nlill0Oll_w_lg_nl0l11OiO52426w(0); + wire_nlill0Oll_w_lg_nl0l11Oli52474w(0) <= nl0l11Oli AND nl0l11OiO; + wire_nlill0Oll_w_lg_nl0l11OOO52492w(0) <= nl0l11OOO AND wire_nlill0Oll_w_lg_nl0l11OOl52343w(0); + wire_nlill0Oll_w_lg_nl0OiOl0l47740w(0) <= nl0OiOl0l AND niOiiO0li; + wire_nlill0Oll_w_lg_nl0Ol1llO48605w(0) <= nl0Ol1llO AND wire_nl0Ol1lil_w_lg_o48604w(0); + wire_nlill0Oll_w_lg_nl10iO1li45042w(0) <= nl10iO1li AND wire_nliiOiilO_w_lg_nliiO0OlO44498w(0); + wire_nlill0Oll_w_lg_nl11lO1OO44950w(0) <= nl11lO1OO AND wire_nlill0Oll_w_lg_nl11lO1Ol44949w(0); + wire_nlill0Oll_w_lg_nl11lOlOO43386w(0) <= nl11lOlOO AND wire_nlill0Oll_w_lg_nl11lOlOl43385w(0); + wire_nlill0Oll_w_lg_nl11OO00i52073w(0) <= nl11OO00i AND wire_w_lg_niOii1OOl52072w(0); + wire_nlill0Oll_w_lg_nl11OO0li60204w(0) <= nl11OO0li AND wire_w_lg_niOi10iOO59973w(0); + wire_nlill0Oll_w_lg_nl11OO0lO60209w(0) <= nl11OO0lO AND wire_w_lg_niOi10iOO59973w(0); + wire_nlill0Oll_w_lg_nl11OOi0i59976w(0) <= nl11OOi0i AND wire_nl1000i_w_lg_nlOili0O4300w(0); + wire_nlill0Oll_w_lg_nl1ll0ilO55830w(0) <= nl1ll0ilO AND wire_nllillil_w_lg_dataout55059w(0); + wire_nlill0Oll_w_lg_nl1ll0iOi56097w(0) <= nl1ll0iOi AND wire_nllillil_w_lg_dataout55059w(0); + wire_nlill0Oll_w_lg_nl1ll0lOi56098w(0) <= nl1ll0lOi AND wire_nlill0Oll_w_lg_nl1ll0iOi56097w(0); + wire_nlill0Oll_w_lg_nl1ll0lOi55845w(0) <= nl1ll0lOi AND wire_nllillil_w_lg_dataout55059w(0); + wire_nlill0Oll_w_lg_nl1ll0lOl5222w(0) <= nl1ll0lOl AND nlliO1Ol; + wire_nlill0Oll_w_lg_nl1Oillll55051w(0) <= nl1Oillll AND wire_nlill0Oll_w_lg_nl1Oillli55050w(0); + wire_nlill0Oll_w_lg_nl1OilO0O56227w(0) <= nl1OilO0O AND nl1iiO0li; + wire_nlill0Oll_w_lg_nl1OilO1i55216w(0) <= nl1OilO1i AND wire_nlill0Oll_w_lg_nl1OilllO54891w(0); + wire_nlill0Oll_w_lg_nl1OilO1O55832w(0) <= nl1OilO1O AND wire_nliliO10i_w_lg_nl1ll0iOO55831w(0); + wire_nlill0Oll_w_lg_nl1OilOii5684w(0) <= nl1OilOii AND nli01iOO; + wire_nlill0Oll_w_lg_nl1Ol1l0l55038w(0) <= nl1Ol1l0l AND wire_nlill0Oll_w_lg_nl1OilOil55037w(0); + wire_nlill0Oll_w_lg_nl1Ol1l0l55031w(0) <= nl1Ol1l0l AND wire_nlill0Oll_w_lg_nl1Ol1l0i55030w(0); + wire_nlill0Oll_w_lg_nl1OO010i54591w(0) <= nl1OO010i AND niOi1OOOl; + wire_nlill0Oll_w_lg_nli10011i48078w(0) <= nli10011i AND wire_nlill0Oll_w_lg_nli101lOl48077w(0); + wire_nlill0Oll_w_lg_nli101ilO48090w(0) <= nli101ilO AND wire_nlill0Oll_w_lg_nli11OOOO48086w(0); + wire_nlill0Oll_w_lg_nli101lOl48084w(0) <= nli101lOl AND wire_nlill0Oll_w_lg_nli101ilO48080w(0); + wire_nlill0Oll_w_lg_nli10OO0l48130w(0) <= nli10OO0l AND nli10Olil; + wire_nlill0Oll_w_lg_nli1i01li48131w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli10OO0l48130w(0); + wire_nlill0Oll_w_lg_nli1i01li48128w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli1i01ll48127w(0); + wire_nlill0Oll_w_lg_nli1i01li48122w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli1i01lO48121w(0); + wire_nlill0Oll_w_lg_nli1i01li48119w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli1i01Oi48118w(0); + wire_nlill0Oll_w_lg_nli1i01li48125w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli1i01Ol48124w(0); + wire_nlill0Oll_w_lg_nli1i01li48116w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli1i01OO48115w(0); + wire_nlill0Oll_w_lg_nli1i01li48144w(0) <= nli1i01li AND wire_nli1i1O1i_w_lg_w_lg_dataout48141w48143w(0); + wire_nlill0Oll_w_lg_nli1i01li48139w(0) <= nli1i01li AND wire_nli1i1OiO_w_lg_w_lg_dataout48136w48138w(0); + wire_nlill0Oll_w_lg_nli1i01li48147w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli1i011i48146w(0); + wire_nlill0Oll_w_lg_nli1i01li48134w(0) <= nli1i01li AND wire_nlill0Oll_w_lg_nli1i1OOl48133w(0); + wire_nlill0Oll_w_lg_nli1i01ll48127w(0) <= nli1i01ll AND nli10Olli; + wire_nlill0Oll_w_lg_nli1i01lO48121w(0) <= nli1i01lO AND nli10OlOl; + wire_nlill0Oll_w_lg_nli1i01Oi48118w(0) <= nli1i01Oi AND nli10OO1i; + wire_nlill0Oll_w_lg_nli1i01Ol48124w(0) <= nli1i01Ol AND nli10OllO; + wire_nlill0Oll_w_lg_nli1i01OO48115w(0) <= nli1i01OO AND nli10OO1O; + wire_nlill0Oll_w_lg_nli1il10l43971w(0) <= nli1il10l AND niOilO1ii; + wire_nlill0Oll_w_lg_nli1iOilO42900w(0) <= nli1iOilO AND wire_nlill0Oll_w_lg_nli1iOill42899w(0); + wire_nlill0Oll_w_lg_nli1iOiOl45273w(0) <= nli1iOiOl AND wire_w_lg_niOilliOO45272w(0); + wire_nlill0Oll_w_lg_nlii110Ol44995w(0) <= nlii110Ol AND wire_nlill0Oll_w_lg_nlii110Oi44994w(0); + wire_nlill0Oll_w_lg_nlii110Ol45007w(0) <= nlii110Ol AND nlii110Oi; + wire_nlill0Oll_w_lg_nlil00ill43937w(0) <= nlil00ill AND wire_w_lg_niOilOO1i43936w(0); + wire_nlill0Oll_w_lg_nlil00ill43997w(0) <= nlil00ill AND niOillOOO; + wire_nlill0Oll_w_lg_nlil01i0i43933w(0) <= nlil01i0i AND wire_nlill0Oll_w_lg_nlil01i1O43932w(0); + wire_nlill0Oll_w_lg_nlil1100O44088w(0) <= nlil1100O AND wire_nlill0Oll_w_lg_nlil1100l44087w(0); + wire_nlill0Oll_w_lg_w_lg_nli1i011i48055w48056w(0) <= NOT wire_nlill0Oll_w_lg_nli1i011i48055w(0); + wire_nlill0Oll_w_lg_nl00llilO54163w(0) <= NOT nl00llilO; + wire_nlill0Oll_w_lg_nl00lliOi54161w(0) <= NOT nl00lliOi; + wire_nlill0Oll_w_lg_nl00lliOl54160w(0) <= NOT nl00lliOl; + wire_nlill0Oll_w_lg_nl0100llO59067w(0) <= NOT nl0100llO; + wire_nlill0Oll_w_lg_nl0100lOi56535w(0) <= NOT nl0100lOi; + wire_nlill0Oll_w_lg_nl010Olil54111w(0) <= NOT nl010Olil; + wire_nlill0Oll_w_lg_nl010OliO54109w(0) <= NOT nl010OliO; + wire_nlill0Oll_w_lg_nl010Olli54107w(0) <= NOT nl010Olli; + wire_nlill0Oll_w_lg_nl010Olll54105w(0) <= NOT nl010Olll; + wire_nlill0Oll_w_lg_nl010OllO54103w(0) <= NOT nl010OllO; + wire_nlill0Oll_w_lg_nl010OlOi54101w(0) <= NOT nl010OlOi; + wire_nlill0Oll_w_lg_nl010OlOl54099w(0) <= NOT nl010OlOl; + wire_nlill0Oll_w_lg_nl010OlOO54098w(0) <= NOT nl010OlOO; + wire_nlill0Oll_w_lg_nl011l1ii54095w(0) <= NOT nl011l1ii; + wire_nlill0Oll_w_lg_nl011ll1l54087w(0) <= NOT nl011ll1l; + wire_nlill0Oll_w_lg_nl011ll1O54081w(0) <= NOT nl011ll1O; + wire_nlill0Oll_w_lg_nl011OOlO54073w(0) <= NOT nl011OOlO; + wire_nlill0Oll_w_lg_nl01i0O0O52922w(0) <= NOT nl01i0O0O; + wire_nlill0Oll_w_lg_nl01i0O1i52924w(0) <= NOT nl01i0O1i; + wire_nlill0Oll_w_lg_nl01i0Oii52921w(0) <= NOT nl01i0Oii; + wire_nlill0Oll_w_lg_nl01i0OOl52935w(0) <= NOT nl01i0OOl; + wire_nlill0Oll_w_lg_nl01i0OOO52934w(0) <= NOT nl01i0OOO; + wire_nlill0Oll_w_lg_nl01ii10i43330w(0) <= NOT nl01ii10i; + wire_nlill0Oll_w_lg_nl01ii10l43328w(0) <= NOT nl01ii10l; + wire_nlill0Oll_w_lg_nl01ii10O43326w(0) <= NOT nl01ii10O; + wire_nlill0Oll_w_lg_nl01ii11i43336w(0) <= NOT nl01ii11i; + wire_nlill0Oll_w_lg_nl01ii11l43334w(0) <= NOT nl01ii11l; + wire_nlill0Oll_w_lg_nl01ii11O43332w(0) <= NOT nl01ii11O; + wire_nlill0Oll_w_lg_nl01ii1ii43324w(0) <= NOT nl01ii1ii; + wire_nlill0Oll_w_lg_nl01ii1il43323w(0) <= NOT nl01ii1il; + wire_nlill0Oll_w_lg_nl01ii1Oi44963w(0) <= NOT nl01ii1Oi; + wire_nlill0Oll_w_lg_nl01ii1Ol52930w(0) <= NOT nl01ii1Ol; + wire_nlill0Oll_w_lg_nl01l00OO53931w(0) <= NOT nl01l00OO; + wire_nlill0Oll_w_lg_nl01l01ll53742w(0) <= NOT nl01l01ll; + wire_nlill0Oll_w_lg_nl01l01Oi53740w(0) <= NOT nl01l01Oi; + wire_nlill0Oll_w_lg_nl01l0i0i53921w(0) <= NOT nl01l0i0i; + wire_nlill0Oll_w_lg_nl01l0i0l53919w(0) <= NOT nl01l0i0l; + wire_nlill0Oll_w_lg_nl01l0i0O53917w(0) <= NOT nl01l0i0O; + wire_nlill0Oll_w_lg_nl01l0i1i53927w(0) <= NOT nl01l0i1i; + wire_nlill0Oll_w_lg_nl01l0i1l53925w(0) <= NOT nl01l0i1l; + wire_nlill0Oll_w_lg_nl01l0i1O53923w(0) <= NOT nl01l0i1O; + wire_nlill0Oll_w_lg_nl01l0iii53915w(0) <= NOT nl01l0iii; + wire_nlill0Oll_w_lg_nl01l0iil53913w(0) <= NOT nl01l0iil; + wire_nlill0Oll_w_lg_nl01l0iiO53911w(0) <= NOT nl01l0iiO; + wire_nlill0Oll_w_lg_nl01l0ili53910w(0) <= NOT nl01l0ili; + wire_nlill0Oll_w_lg_nl01l0ilO53520w(0) <= NOT nl01l0ilO; + wire_nlill0Oll_w_lg_nl01l0iOi53523w(0) <= NOT nl01l0iOi; + wire_nlill0Oll_w_lg_nl01l0iOl53527w(0) <= NOT nl01l0iOl; + wire_nlill0Oll_w_lg_nl01l0iOO53574w(0) <= NOT nl01l0iOO; + wire_nlill0Oll_w_lg_nl01l0l0i53503w(0) <= NOT nl01l0l0i; + wire_nlill0Oll_w_lg_nl01l0l0l44252w(0) <= NOT nl01l0l0l; + wire_nlill0Oll_w_lg_nl01l0l1i53845w(0) <= NOT nl01l0l1i; + wire_nlill0Oll_w_lg_nl01l0l1l53513w(0) <= NOT nl01l0l1l; + wire_nlill0Oll_w_lg_nl01l0l1O53508w(0) <= NOT nl01l0l1O; + wire_nlill0Oll_w_lg_nl01l0lii53389w(0) <= NOT nl01l0lii; + wire_nlill0Oll_w_lg_nl01l0liO44990w(0) <= NOT nl01l0liO; + wire_nlill0Oll_w_lg_nl01l0O0i53186w(0) <= NOT nl01l0O0i; + wire_nlill0Oll_w_lg_nl0i000lO59485w(0) <= NOT nl0i000lO; + wire_nlill0Oll_w_lg_nl0i000Oi59483w(0) <= NOT nl0i000Oi; + wire_nlill0Oll_w_lg_nl0i000Ol59482w(0) <= NOT nl0i000Ol; + wire_nlill0Oll_w_lg_nl0i00i0i60221w(0) <= NOT nl0i00i0i; + wire_nlill0Oll_w_lg_nl0i00i0l60213w(0) <= NOT nl0i00i0l; + wire_nlill0Oll_w_lg_nl0i00i0O60218w(0) <= NOT nl0i00i0O; + wire_nlill0Oll_w_lg_nl0i00i1i60366w(0) <= NOT nl0i00i1i; + wire_nlill0Oll_w_lg_nl0i00i1l60364w(0) <= NOT nl0i00i1l; + wire_nlill0Oll_w_lg_nl0i00i1O60215w(0) <= NOT nl0i00i1O; + wire_nlill0Oll_w_lg_nl0i00iii61540w(0) <= NOT nl0i00iii; + wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) <= NOT nl0i00iiO; + wire_nlill0Oll_w_lg_nl0i1liii52277w(0) <= NOT nl0i1liii; + wire_nlill0Oll_w_lg_nl0i1liil52078w(0) <= NOT nl0i1liil; + wire_nlill0Oll_w_lg_nl0illl0l52598w(0) <= NOT nl0illl0l; + wire_nlill0Oll_w_lg_nl0illl0O52596w(0) <= NOT nl0illl0O; + wire_nlill0Oll_w_lg_nl0illlii52590w(0) <= NOT nl0illlii; + wire_nlill0Oll_w_lg_nl0illlil52588w(0) <= NOT nl0illlil; + wire_nlill0Oll_w_lg_nl0illliO52587w(0) <= NOT nl0illliO; + wire_nlill0Oll_w_lg_nl0illlli52592w(0) <= NOT nl0illlli; + wire_nlill0Oll_w_lg_nl0illllO52075w(0) <= NOT nl0illllO; + wire_nlill0Oll_w_lg_nl0ilOiOO52131w(0) <= NOT nl0ilOiOO; + wire_nlill0Oll_w_lg_nl0ilOl1i52130w(0) <= NOT nl0ilOl1i; + wire_nlill0Oll_w_lg_nl0ilOl1l52248w(0) <= NOT nl0ilOl1l; + wire_nlill0Oll_w_lg_nl0ilOlll52123w(0) <= NOT nl0ilOlll; + wire_nlill0Oll_w_lg_nl0iOil0l44799w(0) <= NOT nl0iOil0l; + wire_nlill0Oll_w_lg_nl0iOil0O47059w(0) <= NOT nl0iOil0O; + wire_nlill0Oll_w_lg_nl0iOilli47862w(0) <= NOT nl0iOilli; + wire_nlill0Oll_w_lg_nl0iOiO1O47492w(0) <= NOT nl0iOiO1O; + wire_nlill0Oll_w_lg_nl0iOiOii46913w(0) <= NOT nl0iOiOii; + wire_nlill0Oll_w_lg_nl0iOiOiO47246w(0) <= NOT nl0iOiOiO; + wire_nlill0Oll_w_lg_nl0iOiOOl47245w(0) <= NOT nl0iOiOOl; + wire_nlill0Oll_w_lg_nl0iOl10i52081w(0) <= NOT nl0iOl10i; + wire_nlill0Oll_w_lg_nl0iOl11l47151w(0) <= NOT nl0iOl11l; + wire_nlill0Oll_w_lg_nl0l000ll45592w(0) <= NOT nl0l000ll; + wire_nlill0Oll_w_lg_nl0l001iO45593w(0) <= NOT nl0l001iO; + wire_nlill0Oll_w_lg_nl0l001li45594w(0) <= NOT nl0l001li; + wire_nlill0Oll_w_lg_nl0l001ll45595w(0) <= NOT nl0l001ll; + wire_nlill0Oll_w_lg_nl0l001lO45596w(0) <= NOT nl0l001lO; + wire_nlill0Oll_w_lg_nl0l001Oi45597w(0) <= NOT nl0l001Oi; + wire_nlill0Oll_w_lg_nl0l001Ol45599w(0) <= NOT nl0l001Ol; + wire_nlill0Oll_w_lg_nl0l00iOl45600w(0) <= NOT nl0l00iOl; + wire_nlill0Oll_w_lg_nl0l00iOO45601w(0) <= NOT nl0l00iOO; + wire_nlill0Oll_w_lg_nl0l00l1i45602w(0) <= NOT nl0l00l1i; + wire_nlill0Oll_w_lg_nl0l00l1l45603w(0) <= NOT nl0l00l1l; + wire_nlill0Oll_w_lg_nl0l00l1O45604w(0) <= NOT nl0l00l1O; + wire_nlill0Oll_w_lg_nl0l0100i52257w(0) <= NOT nl0l0100i; + wire_nlill0Oll_w_lg_nl0l0101l52252w(0) <= NOT nl0l0101l; + wire_nlill0Oll_w_lg_nl0l0101O52251w(0) <= NOT nl0l0101O; + wire_nlill0Oll_w_lg_nl0l010OO52287w(0) <= NOT nl0l010OO; + wire_nlill0Oll_w_lg_nl0l01O1l52285w(0) <= NOT nl0l01O1l; + wire_nlill0Oll_w_lg_nl0l01O1O52284w(0) <= NOT nl0l01O1O; + wire_nlill0Oll_w_lg_nl0l0i00O45598w(0) <= NOT nl0l0i00O; + wire_nlill0Oll_w_lg_nl0l0i0li51959w(0) <= NOT nl0l0i0li; + wire_nlill0Oll_w_lg_nl0l0liOi46237w(0) <= NOT nl0l0liOi; + wire_nlill0Oll_w_lg_nl0l0liOl46236w(0) <= NOT nl0l0liOl; + wire_nlill0Oll_w_lg_nl0l0liOO46235w(0) <= NOT nl0l0liOO; + wire_nlill0Oll_w_lg_nl0l0ll0i46231w(0) <= NOT nl0l0ll0i; + wire_nlill0Oll_w_lg_nl0l0ll0l46230w(0) <= NOT nl0l0ll0l; + wire_nlill0Oll_w_lg_nl0l0ll0O46229w(0) <= NOT nl0l0ll0O; + wire_nlill0Oll_w_lg_nl0l0ll1i46234w(0) <= NOT nl0l0ll1i; + wire_nlill0Oll_w_lg_nl0l0ll1l46233w(0) <= NOT nl0l0ll1l; + wire_nlill0Oll_w_lg_nl0l0ll1O46232w(0) <= NOT nl0l0ll1O; + wire_nlill0Oll_w_lg_nl0l0llii46228w(0) <= NOT nl0l0llii; + wire_nlill0Oll_w_lg_nl0l0llil46227w(0) <= NOT nl0l0llil; + wire_nlill0Oll_w_lg_nl0l0lliO46224w(0) <= NOT nl0l0lliO; + wire_nlill0Oll_w_lg_nl0l0llli46223w(0) <= NOT nl0l0llli; + wire_nlill0Oll_w_lg_nl0l0llll46222w(0) <= NOT nl0l0llll; + wire_nlill0Oll_w_lg_nl0l0lllO46221w(0) <= NOT nl0l0lllO; + wire_nlill0Oll_w_lg_nl0l0llOi46220w(0) <= NOT nl0l0llOi; + wire_nlill0Oll_w_lg_nl0l0llOl46219w(0) <= NOT nl0l0llOl; + wire_nlill0Oll_w_lg_nl0l0llOO46218w(0) <= NOT nl0l0llOO; + wire_nlill0Oll_w_lg_nl0l0lO0i46214w(0) <= NOT nl0l0lO0i; + wire_nlill0Oll_w_lg_nl0l0lO0l46213w(0) <= NOT nl0l0lO0l; + wire_nlill0Oll_w_lg_nl0l0lO0O46212w(0) <= NOT nl0l0lO0O; + wire_nlill0Oll_w_lg_nl0l0lO1i46217w(0) <= NOT nl0l0lO1i; + wire_nlill0Oll_w_lg_nl0l0lO1l46216w(0) <= NOT nl0l0lO1l; + wire_nlill0Oll_w_lg_nl0l0lO1O46215w(0) <= NOT nl0l0lO1O; + wire_nlill0Oll_w_lg_nl0l0lOii46211w(0) <= NOT nl0l0lOii; + wire_nlill0Oll_w_lg_nl0l0lOil46210w(0) <= NOT nl0l0lOil; + wire_nlill0Oll_w_lg_nl0l0lOiO46209w(0) <= NOT nl0l0lOiO; + wire_nlill0Oll_w_lg_nl0l0lOli46208w(0) <= NOT nl0l0lOli; + wire_nlill0Oll_w_lg_nl0l0lOll46207w(0) <= NOT nl0l0lOll; + wire_nlill0Oll_w_lg_nl0l0lOlO46206w(0) <= NOT nl0l0lOlO; + wire_nlill0Oll_w_lg_nl0l0lOOi46205w(0) <= NOT nl0l0lOOi; + wire_nlill0Oll_w_lg_nl0l0lOOl46204w(0) <= NOT nl0l0lOOl; + wire_nlill0Oll_w_lg_nl0l0lOOO46203w(0) <= NOT nl0l0lOOO; + wire_nlill0Oll_w_lg_nl0l0O00i46264w(0) <= NOT nl0l0O00i; + wire_nlill0Oll_w_lg_nl0l0O00l46263w(0) <= NOT nl0l0O00l; + wire_nlill0Oll_w_lg_nl0l0O00O46262w(0) <= NOT nl0l0O00O; + wire_nlill0Oll_w_lg_nl0l0O01i46267w(0) <= NOT nl0l0O01i; + wire_nlill0Oll_w_lg_nl0l0O01l46266w(0) <= NOT nl0l0O01l; + wire_nlill0Oll_w_lg_nl0l0O01O46265w(0) <= NOT nl0l0O01O; + wire_nlill0Oll_w_lg_nl0l0O0ii46261w(0) <= NOT nl0l0O0ii; + wire_nlill0Oll_w_lg_nl0l0O0il46260w(0) <= NOT nl0l0O0il; + wire_nlill0Oll_w_lg_nl0l0O0iO46259w(0) <= NOT nl0l0O0iO; + wire_nlill0Oll_w_lg_nl0l0O0li46258w(0) <= NOT nl0l0O0li; + wire_nlill0Oll_w_lg_nl0l0O0ll46257w(0) <= NOT nl0l0O0ll; + wire_nlill0Oll_w_lg_nl0l0O0lO46256w(0) <= NOT nl0l0O0lO; + wire_nlill0Oll_w_lg_nl0l0O0Oi46255w(0) <= NOT nl0l0O0Oi; + wire_nlill0Oll_w_lg_nl0l0O0Ol46254w(0) <= NOT nl0l0O0Ol; + wire_nlill0Oll_w_lg_nl0l0O0OO46253w(0) <= NOT nl0l0O0OO; + wire_nlill0Oll_w_lg_nl0l0O10i46199w(0) <= NOT nl0l0O10i; + wire_nlill0Oll_w_lg_nl0l0O10l46198w(0) <= NOT nl0l0O10l; + wire_nlill0Oll_w_lg_nl0l0O10O46197w(0) <= NOT nl0l0O10O; + wire_nlill0Oll_w_lg_nl0l0O11i46202w(0) <= NOT nl0l0O11i; + wire_nlill0Oll_w_lg_nl0l0O11l46201w(0) <= NOT nl0l0O11l; + wire_nlill0Oll_w_lg_nl0l0O11O46200w(0) <= NOT nl0l0O11O; + wire_nlill0Oll_w_lg_nl0l0O1ii46196w(0) <= NOT nl0l0O1ii; + wire_nlill0Oll_w_lg_nl0l0O1il46195w(0) <= NOT nl0l0O1il; + wire_nlill0Oll_w_lg_nl0l0O1iO46274w(0) <= NOT nl0l0O1iO; + wire_nlill0Oll_w_lg_nl0l0O1li46273w(0) <= NOT nl0l0O1li; + wire_nlill0Oll_w_lg_nl0l0O1ll46272w(0) <= NOT nl0l0O1ll; + wire_nlill0Oll_w_lg_nl0l0O1lO46271w(0) <= NOT nl0l0O1lO; + wire_nlill0Oll_w_lg_nl0l0O1Oi46270w(0) <= NOT nl0l0O1Oi; + wire_nlill0Oll_w_lg_nl0l0O1Ol46269w(0) <= NOT nl0l0O1Ol; + wire_nlill0Oll_w_lg_nl0l0O1OO46268w(0) <= NOT nl0l0O1OO; + wire_nlill0Oll_w_lg_nl0l0Oi0i46249w(0) <= NOT nl0l0Oi0i; + wire_nlill0Oll_w_lg_nl0l0Oi0l46248w(0) <= NOT nl0l0Oi0l; + wire_nlill0Oll_w_lg_nl0l0Oi0O46247w(0) <= NOT nl0l0Oi0O; + wire_nlill0Oll_w_lg_nl0l0Oi1i46252w(0) <= NOT nl0l0Oi1i; + wire_nlill0Oll_w_lg_nl0l0Oi1l46251w(0) <= NOT nl0l0Oi1l; + wire_nlill0Oll_w_lg_nl0l0Oi1O46250w(0) <= NOT nl0l0Oi1O; + wire_nlill0Oll_w_lg_nl0l0Oiii46246w(0) <= NOT nl0l0Oiii; + wire_nlill0Oll_w_lg_nl0l0Oiil46245w(0) <= NOT nl0l0Oiil; + wire_nlill0Oll_w_lg_nl0l0OiiO46244w(0) <= NOT nl0l0OiiO; + wire_nlill0Oll_w_lg_nl0l0Oili46243w(0) <= NOT nl0l0Oili; + wire_nlill0Oll_w_lg_nl0l0Oill46193w(0) <= NOT nl0l0Oill; + wire_nlill0Oll_w_lg_nl0l0OilO46189w(0) <= NOT nl0l0OilO; + wire_nlill0Oll_w_lg_nl0l0OiOi46188w(0) <= NOT nl0l0OiOi; + wire_nlill0Oll_w_lg_nl0l0OiOl46187w(0) <= NOT nl0l0OiOl; + wire_nlill0Oll_w_lg_nl0l0OiOO46545w(0) <= NOT nl0l0OiOO; + wire_nlill0Oll_w_lg_nl0l1011i52423w(0) <= NOT nl0l1011i; + wire_nlill0Oll_w_lg_nl0l1011l52421w(0) <= NOT nl0l1011l; + wire_nlill0Oll_w_lg_nl0l1011O52420w(0) <= NOT nl0l1011O; + wire_nlill0Oll_w_lg_nl0l101il52065w(0) <= NOT nl0l101il; + wire_nlill0Oll_w_lg_nl0l11O0O52432w(0) <= NOT nl0l11O0O; + wire_nlill0Oll_w_lg_nl0l11Oii52430w(0) <= NOT nl0l11Oii; + wire_nlill0Oll_w_lg_nl0l11Oil52428w(0) <= NOT nl0l11Oil; + wire_nlill0Oll_w_lg_nl0l11OiO52426w(0) <= NOT nl0l11OiO; + wire_nlill0Oll_w_lg_nl0l11Oli52425w(0) <= NOT nl0l11Oli; + wire_nlill0Oll_w_lg_nl0l11Oll52487w(0) <= NOT nl0l11Oll; + wire_nlill0Oll_w_lg_nl0l11OlO52347w(0) <= NOT nl0l11OlO; + wire_nlill0Oll_w_lg_nl0l11OOi52345w(0) <= NOT nl0l11OOi; + wire_nlill0Oll_w_lg_nl0l11OOl52343w(0) <= NOT nl0l11OOl; + wire_nlill0Oll_w_lg_nl0l11OOO52342w(0) <= NOT nl0l11OOO; + wire_nlill0Oll_w_lg_nl0lil0ll45677w(0) <= NOT nl0lil0ll; + wire_nlill0Oll_w_lg_nl0lil11i46544w(0) <= NOT nl0lil11i; + wire_nlill0Oll_w_lg_nl0liliOO45676w(0) <= NOT nl0liliOO; + wire_nlill0Oll_w_lg_nl0lill0i45672w(0) <= NOT nl0lill0i; + wire_nlill0Oll_w_lg_nl0lill0l45671w(0) <= NOT nl0lill0l; + wire_nlill0Oll_w_lg_nl0lill0O45670w(0) <= NOT nl0lill0O; + wire_nlill0Oll_w_lg_nl0lill1i45675w(0) <= NOT nl0lill1i; + wire_nlill0Oll_w_lg_nl0lill1l45674w(0) <= NOT nl0lill1l; + wire_nlill0Oll_w_lg_nl0lill1O45673w(0) <= NOT nl0lill1O; + wire_nlill0Oll_w_lg_nl0ll1O1l51277w(0) <= NOT nl0ll1O1l; + wire_nlill0Oll_w_lg_nl0lliiiO51476w(0) <= NOT nl0lliiiO; + wire_nlill0Oll_w_lg_nl0llli0i51468w(0) <= NOT nl0llli0i; + wire_nlill0Oll_w_lg_nl0llli0l51466w(0) <= NOT nl0llli0l; + wire_nlill0Oll_w_lg_nl0llli0O51464w(0) <= NOT nl0llli0O; + wire_nlill0Oll_w_lg_nl0llli1i51474w(0) <= NOT nl0llli1i; + wire_nlill0Oll_w_lg_nl0llli1l51472w(0) <= NOT nl0llli1l; + wire_nlill0Oll_w_lg_nl0llli1O51470w(0) <= NOT nl0llli1O; + wire_nlill0Oll_w_lg_nl0llliii51462w(0) <= NOT nl0llliii; + wire_nlill0Oll_w_lg_nl0llliil51460w(0) <= NOT nl0llliil; + wire_nlill0Oll_w_lg_nl0llliiO51458w(0) <= NOT nl0llliiO; + wire_nlill0Oll_w_lg_nl0lllili51456w(0) <= NOT nl0lllili; + wire_nlill0Oll_w_lg_nl0lllill51454w(0) <= NOT nl0lllill; + wire_nlill0Oll_w_lg_nl0lllilO51452w(0) <= NOT nl0lllilO; + wire_nlill0Oll_w_lg_nl0llliOi51450w(0) <= NOT nl0llliOi; + wire_nlill0Oll_w_lg_nl0llliOl51448w(0) <= NOT nl0llliOl; + wire_nlill0Oll_w_lg_nl0llliOO51446w(0) <= NOT nl0llliOO; + wire_nlill0Oll_w_lg_nl0llll0i51438w(0) <= NOT nl0llll0i; + wire_nlill0Oll_w_lg_nl0llll0l51436w(0) <= NOT nl0llll0l; + wire_nlill0Oll_w_lg_nl0llll0O51434w(0) <= NOT nl0llll0O; + wire_nlill0Oll_w_lg_nl0llll1i51444w(0) <= NOT nl0llll1i; + wire_nlill0Oll_w_lg_nl0llll1l51442w(0) <= NOT nl0llll1l; + wire_nlill0Oll_w_lg_nl0llll1O51440w(0) <= NOT nl0llll1O; + wire_nlill0Oll_w_lg_nl0llllii51432w(0) <= NOT nl0llllii; + wire_nlill0Oll_w_lg_nl0llllil51430w(0) <= NOT nl0llllil; + wire_nlill0Oll_w_lg_nl0lllliO51428w(0) <= NOT nl0lllliO; + wire_nlill0Oll_w_lg_nl0llllli51426w(0) <= NOT nl0llllli; + wire_nlill0Oll_w_lg_nl0llllll51424w(0) <= NOT nl0llllll; + wire_nlill0Oll_w_lg_nl0lllllO51422w(0) <= NOT nl0lllllO; + wire_nlill0Oll_w_lg_nl0llllOi51420w(0) <= NOT nl0llllOi; + wire_nlill0Oll_w_lg_nl0llllOl51418w(0) <= NOT nl0llllOl; + wire_nlill0Oll_w_lg_nl0llllOO51416w(0) <= NOT nl0llllOO; + wire_nlill0Oll_w_lg_nl0lllO1i51415w(0) <= NOT nl0lllO1i; + wire_nlill0Oll_w_lg_nl0lOlill50399w(0) <= NOT nl0lOlill; + wire_nlill0Oll_w_lg_nl0O0i10O49514w(0) <= NOT nl0O0i10O; + wire_nlill0Oll_w_lg_nl0OiO0li45808w(0) <= NOT nl0OiO0li; + wire_nlill0Oll_w_lg_nl0OiO1il45809w(0) <= NOT nl0OiO1il; + wire_nlill0Oll_w_lg_nl0OiO1iO45810w(0) <= NOT nl0OiO1iO; + wire_nlill0Oll_w_lg_nl0OiO1li45811w(0) <= NOT nl0OiO1li; + wire_nlill0Oll_w_lg_nl0OiO1ll45812w(0) <= NOT nl0OiO1ll; + wire_nlill0Oll_w_lg_nl0OiO1lO45813w(0) <= NOT nl0OiO1lO; + wire_nlill0Oll_w_lg_nl0OiO1Oi46166w(0) <= NOT nl0OiO1Oi; + wire_nlill0Oll_w_lg_nl0OiOl0i46167w(0) <= NOT nl0OiOl0i; + wire_nlill0Oll_w_lg_nl0OiOl0l46168w(0) <= NOT nl0OiOl0l; + wire_nlill0Oll_w_lg_nl0OiOl0O46169w(0) <= NOT nl0OiOl0O; + wire_nlill0Oll_w_lg_nl0OiOlii46170w(0) <= NOT nl0OiOlii; + wire_nlill0Oll_w_lg_nl0OiOlil48606w(0) <= NOT nl0OiOlil; + wire_nlill0Oll_w_lg_nl0Ol000i45925w(0) <= NOT nl0Ol000i; + wire_nlill0Oll_w_lg_nl0Ol000l45924w(0) <= NOT nl0Ol000l; + wire_nlill0Oll_w_lg_nl0Ol000O45923w(0) <= NOT nl0Ol000O; + wire_nlill0Oll_w_lg_nl0Ol001i45928w(0) <= NOT nl0Ol001i; + wire_nlill0Oll_w_lg_nl0Ol001l45927w(0) <= NOT nl0Ol001l; + wire_nlill0Oll_w_lg_nl0Ol001O45926w(0) <= NOT nl0Ol001O; + wire_nlill0Oll_w_lg_nl0Ol00ii45922w(0) <= NOT nl0Ol00ii; + wire_nlill0Oll_w_lg_nl0Ol00il45921w(0) <= NOT nl0Ol00il; + wire_nlill0Oll_w_lg_nl0Ol00iO45920w(0) <= NOT nl0Ol00iO; + wire_nlill0Oll_w_lg_nl0Ol00li45919w(0) <= NOT nl0Ol00li; + wire_nlill0Oll_w_lg_nl0Ol00ll45918w(0) <= NOT nl0Ol00ll; + wire_nlill0Oll_w_lg_nl0Ol00lO46009w(0) <= NOT nl0Ol00lO; + wire_nlill0Oll_w_lg_nl0Ol00Oi46008w(0) <= NOT nl0Ol00Oi; + wire_nlill0Oll_w_lg_nl0Ol00Ol46007w(0) <= NOT nl0Ol00Ol; + wire_nlill0Oll_w_lg_nl0Ol00OO46006w(0) <= NOT nl0Ol00OO; + wire_nlill0Oll_w_lg_nl0Ol010i46021w(0) <= NOT nl0Ol010i; + wire_nlill0Oll_w_lg_nl0Ol010l46020w(0) <= NOT nl0Ol010l; + wire_nlill0Oll_w_lg_nl0Ol010O46019w(0) <= NOT nl0Ol010O; + wire_nlill0Oll_w_lg_nl0Ol011i46024w(0) <= NOT nl0Ol011i; + wire_nlill0Oll_w_lg_nl0Ol011l46023w(0) <= NOT nl0Ol011l; + wire_nlill0Oll_w_lg_nl0Ol011O46022w(0) <= NOT nl0Ol011O; + wire_nlill0Oll_w_lg_nl0Ol01ii46018w(0) <= NOT nl0Ol01ii; + wire_nlill0Oll_w_lg_nl0Ol01il46017w(0) <= NOT nl0Ol01il; + wire_nlill0Oll_w_lg_nl0Ol01iO46016w(0) <= NOT nl0Ol01iO; + wire_nlill0Oll_w_lg_nl0Ol01li46015w(0) <= NOT nl0Ol01li; + wire_nlill0Oll_w_lg_nl0Ol01ll46014w(0) <= NOT nl0Ol01ll; + wire_nlill0Oll_w_lg_nl0Ol01lO46013w(0) <= NOT nl0Ol01lO; + wire_nlill0Oll_w_lg_nl0Ol01Oi46012w(0) <= NOT nl0Ol01Oi; + wire_nlill0Oll_w_lg_nl0Ol01Ol46011w(0) <= NOT nl0Ol01Ol; + wire_nlill0Oll_w_lg_nl0Ol01OO45929w(0) <= NOT nl0Ol01OO; + wire_nlill0Oll_w_lg_nl0Ol0i0i46002w(0) <= NOT nl0Ol0i0i; + wire_nlill0Oll_w_lg_nl0Ol0i0l46001w(0) <= NOT nl0Ol0i0l; + wire_nlill0Oll_w_lg_nl0Ol0i0O46000w(0) <= NOT nl0Ol0i0O; + wire_nlill0Oll_w_lg_nl0Ol0i1i46005w(0) <= NOT nl0Ol0i1i; + wire_nlill0Oll_w_lg_nl0Ol0i1l46004w(0) <= NOT nl0Ol0i1l; + wire_nlill0Oll_w_lg_nl0Ol0i1O46003w(0) <= NOT nl0Ol0i1O; + wire_nlill0Oll_w_lg_nl0Ol0iii45999w(0) <= NOT nl0Ol0iii; + wire_nlill0Oll_w_lg_nl0Ol0iil45998w(0) <= NOT nl0Ol0iil; + wire_nlill0Oll_w_lg_nl0Ol0iiO45997w(0) <= NOT nl0Ol0iiO; + wire_nlill0Oll_w_lg_nl0Ol0ili45996w(0) <= NOT nl0Ol0ili; + wire_nlill0Oll_w_lg_nl0Ol0ill45995w(0) <= NOT nl0Ol0ill; + wire_nlill0Oll_w_lg_nl0Ol0ilO45994w(0) <= NOT nl0Ol0ilO; + wire_nlill0Oll_w_lg_nl0Ol0iOi45993w(0) <= NOT nl0Ol0iOi; + wire_nlill0Oll_w_lg_nl0Ol0iOl45992w(0) <= NOT nl0Ol0iOl; + wire_nlill0Oll_w_lg_nl0Ol0iOO45991w(0) <= NOT nl0Ol0iOO; + wire_nlill0Oll_w_lg_nl0Ol0l0i45987w(0) <= NOT nl0Ol0l0i; + wire_nlill0Oll_w_lg_nl0Ol0l0l45986w(0) <= NOT nl0Ol0l0l; + wire_nlill0Oll_w_lg_nl0Ol0l0O45985w(0) <= NOT nl0Ol0l0O; + wire_nlill0Oll_w_lg_nl0Ol0l1i45990w(0) <= NOT nl0Ol0l1i; + wire_nlill0Oll_w_lg_nl0Ol0l1l45989w(0) <= NOT nl0Ol0l1l; + wire_nlill0Oll_w_lg_nl0Ol0l1O45988w(0) <= NOT nl0Ol0l1O; + wire_nlill0Oll_w_lg_nl0Ol0lii45984w(0) <= NOT nl0Ol0lii; + wire_nlill0Oll_w_lg_nl0Ol0lil45983w(0) <= NOT nl0Ol0lil; + wire_nlill0Oll_w_lg_nl0Ol0liO45982w(0) <= NOT nl0Ol0liO; + wire_nlill0Oll_w_lg_nl0Ol0lli45981w(0) <= NOT nl0Ol0lli; + wire_nlill0Oll_w_lg_nl0Ol0lll45980w(0) <= NOT nl0Ol0lll; + wire_nlill0Oll_w_lg_nl0Ol0llO45979w(0) <= NOT nl0Ol0llO; + wire_nlill0Oll_w_lg_nl0Ol0lOi45978w(0) <= NOT nl0Ol0lOi; + wire_nlill0Oll_w_lg_nl0Ol0lOl45943w(0) <= NOT nl0Ol0lOl; + wire_nlill0Oll_w_lg_nl0Ol0lOO45942w(0) <= NOT nl0Ol0lOO; + wire_nlill0Oll_w_lg_nl0Ol0O0i45938w(0) <= NOT nl0Ol0O0i; + wire_nlill0Oll_w_lg_nl0Ol0O0l45937w(0) <= NOT nl0Ol0O0l; + wire_nlill0Oll_w_lg_nl0Ol0O0O45936w(0) <= NOT nl0Ol0O0O; + wire_nlill0Oll_w_lg_nl0Ol0O1i45941w(0) <= NOT nl0Ol0O1i; + wire_nlill0Oll_w_lg_nl0Ol0O1l45940w(0) <= NOT nl0Ol0O1l; + wire_nlill0Oll_w_lg_nl0Ol0O1O45939w(0) <= NOT nl0Ol0O1O; + wire_nlill0Oll_w_lg_nl0Ol0Oii45935w(0) <= NOT nl0Ol0Oii; + wire_nlill0Oll_w_lg_nl0Ol0Oil45934w(0) <= NOT nl0Ol0Oil; + wire_nlill0Oll_w_lg_nl0Ol0OiO45933w(0) <= NOT nl0Ol0OiO; + wire_nlill0Oll_w_lg_nl0Ol0Oli45932w(0) <= NOT nl0Ol0Oli; + wire_nlill0Oll_w_lg_nl0Ol0Oll45868w(0) <= NOT nl0Ol0Oll; + wire_nlill0Oll_w_lg_nl0Ol1lOi46042w(0) <= NOT nl0Ol1lOi; + wire_nlill0Oll_w_lg_nl0Ol1lOl46041w(0) <= NOT nl0Ol1lOl; + wire_nlill0Oll_w_lg_nl0Ol1lOO46040w(0) <= NOT nl0Ol1lOO; + wire_nlill0Oll_w_lg_nl0Ol1O0i46036w(0) <= NOT nl0Ol1O0i; + wire_nlill0Oll_w_lg_nl0Ol1O0l46035w(0) <= NOT nl0Ol1O0l; + wire_nlill0Oll_w_lg_nl0Ol1O0O46034w(0) <= NOT nl0Ol1O0O; + wire_nlill0Oll_w_lg_nl0Ol1O1i46039w(0) <= NOT nl0Ol1O1i; + wire_nlill0Oll_w_lg_nl0Ol1O1l46038w(0) <= NOT nl0Ol1O1l; + wire_nlill0Oll_w_lg_nl0Ol1O1O46037w(0) <= NOT nl0Ol1O1O; + wire_nlill0Oll_w_lg_nl0Ol1Oii46033w(0) <= NOT nl0Ol1Oii; + wire_nlill0Oll_w_lg_nl0Ol1Oil46032w(0) <= NOT nl0Ol1Oil; + wire_nlill0Oll_w_lg_nl0Ol1OiO46031w(0) <= NOT nl0Ol1OiO; + wire_nlill0Oll_w_lg_nl0Ol1Oli46030w(0) <= NOT nl0Ol1Oli; + wire_nlill0Oll_w_lg_nl0Ol1Oll46029w(0) <= NOT nl0Ol1Oll; + wire_nlill0Oll_w_lg_nl0Ol1OlO46028w(0) <= NOT nl0Ol1OlO; + wire_nlill0Oll_w_lg_nl0Ol1OOi46027w(0) <= NOT nl0Ol1OOi; + wire_nlill0Oll_w_lg_nl0Ol1OOl46026w(0) <= NOT nl0Ol1OOl; + wire_nlill0Oll_w_lg_nl0Ol1OOO46025w(0) <= NOT nl0Ol1OOO; + wire_nlill0Oll_w_lg_nl0OO0Oii46122w(0) <= NOT nl0OO0Oii; + wire_nlill0Oll_w_lg_nl0OO0Oil46121w(0) <= NOT nl0OO0Oil; + wire_nlill0Oll_w_lg_nl0OO0OiO46120w(0) <= NOT nl0OO0OiO; + wire_nlill0Oll_w_lg_nl0OO0Oli46119w(0) <= NOT nl0OO0Oli; + wire_nlill0Oll_w_lg_nl0OO0Oll46118w(0) <= NOT nl0OO0Oll; + wire_nlill0Oll_w_lg_nl0OO0OlO46117w(0) <= NOT nl0OO0OlO; + wire_nlill0Oll_w_lg_nl0OO0OOi46116w(0) <= NOT nl0OO0OOi; + wire_nlill0Oll_w_lg_nl0OO0OOl46115w(0) <= NOT nl0OO0OOl; + wire_nlill0Oll_w_lg_nl0OO0OOO46114w(0) <= NOT nl0OO0OOO; + wire_nlill0Oll_w_lg_nl0OO1iOO45867w(0) <= NOT nl0OO1iOO; + wire_nlill0Oll_w_lg_nl0OO1l0i45863w(0) <= NOT nl0OO1l0i; + wire_nlill0Oll_w_lg_nl0OO1l0l45862w(0) <= NOT nl0OO1l0l; + wire_nlill0Oll_w_lg_nl0OO1l0O45861w(0) <= NOT nl0OO1l0O; + wire_nlill0Oll_w_lg_nl0OO1l1i45866w(0) <= NOT nl0OO1l1i; + wire_nlill0Oll_w_lg_nl0OO1l1l45865w(0) <= NOT nl0OO1l1l; + wire_nlill0Oll_w_lg_nl0OO1l1O45864w(0) <= NOT nl0OO1l1O; + wire_nlill0Oll_w_lg_nl0OO1lii45860w(0) <= NOT nl0OO1lii; + wire_nlill0Oll_w_lg_nl0OO1lil45859w(0) <= NOT nl0OO1lil; + wire_nlill0Oll_w_lg_nl0OO1liO45858w(0) <= NOT nl0OO1liO; + wire_nlill0Oll_w_lg_nl0OO1lli45857w(0) <= NOT nl0OO1lli; + wire_nlill0Oll_w_lg_nl0OO1lll45880w(0) <= NOT nl0OO1lll; + wire_nlill0Oll_w_lg_nl0OO1llO45879w(0) <= NOT nl0OO1llO; + wire_nlill0Oll_w_lg_nl0OO1lOi45878w(0) <= NOT nl0OO1lOi; + wire_nlill0Oll_w_lg_nl0OO1lOl45877w(0) <= NOT nl0OO1lOl; + wire_nlill0Oll_w_lg_nl0OO1lOO45876w(0) <= NOT nl0OO1lOO; + wire_nlill0Oll_w_lg_nl0OO1O0i45872w(0) <= NOT nl0OO1O0i; + wire_nlill0Oll_w_lg_nl0OO1O0l45871w(0) <= NOT nl0OO1O0l; + wire_nlill0Oll_w_lg_nl0OO1O0O45870w(0) <= NOT nl0OO1O0O; + wire_nlill0Oll_w_lg_nl0OO1O1i45875w(0) <= NOT nl0OO1O1i; + wire_nlill0Oll_w_lg_nl0OO1O1l45874w(0) <= NOT nl0OO1O1l; + wire_nlill0Oll_w_lg_nl0OO1O1O45873w(0) <= NOT nl0OO1O1O; + wire_nlill0Oll_w_lg_nl0OO1Oii45869w(0) <= NOT nl0OO1Oii; + wire_nlill0Oll_w_lg_nl0OO1Oil46123w(0) <= NOT nl0OO1Oil; + wire_nlill0Oll_w_lg_nl0OOi00i46131w(0) <= NOT nl0OOi00i; + wire_nlill0Oll_w_lg_nl0OOi00l46130w(0) <= NOT nl0OOi00l; + wire_nlill0Oll_w_lg_nl0OOi00O46129w(0) <= NOT nl0OOi00O; + wire_nlill0Oll_w_lg_nl0OOi01i46134w(0) <= NOT nl0OOi01i; + wire_nlill0Oll_w_lg_nl0OOi01l46133w(0) <= NOT nl0OOi01l; + wire_nlill0Oll_w_lg_nl0OOi01O46132w(0) <= NOT nl0OOi01O; + wire_nlill0Oll_w_lg_nl0OOi0ii46128w(0) <= NOT nl0OOi0ii; + wire_nlill0Oll_w_lg_nl0OOi0il46127w(0) <= NOT nl0OOi0il; + wire_nlill0Oll_w_lg_nl0OOi0iO46126w(0) <= NOT nl0OOi0iO; + wire_nlill0Oll_w_lg_nl0OOi0li46125w(0) <= NOT nl0OOi0li; + wire_nlill0Oll_w_lg_nl0OOi0ll46124w(0) <= NOT nl0OOi0ll; + wire_nlill0Oll_w_lg_nl0OOi0lO45823w(0) <= NOT nl0OOi0lO; + wire_nlill0Oll_w_lg_nl0OOi0Oi45822w(0) <= NOT nl0OOi0Oi; + wire_nlill0Oll_w_lg_nl0OOi0Ol45821w(0) <= NOT nl0OOi0Ol; + wire_nlill0Oll_w_lg_nl0OOi0OO45820w(0) <= NOT nl0OOi0OO; + wire_nlill0Oll_w_lg_nl0OOi10i46110w(0) <= NOT nl0OOi10i; + wire_nlill0Oll_w_lg_nl0OOi10l46109w(0) <= NOT nl0OOi10l; + wire_nlill0Oll_w_lg_nl0OOi10O46108w(0) <= NOT nl0OOi10O; + wire_nlill0Oll_w_lg_nl0OOi11i46113w(0) <= NOT nl0OOi11i; + wire_nlill0Oll_w_lg_nl0OOi11l46112w(0) <= NOT nl0OOi11l; + wire_nlill0Oll_w_lg_nl0OOi11O46111w(0) <= NOT nl0OOi11O; + wire_nlill0Oll_w_lg_nl0OOi1ii45817w(0) <= NOT nl0OOi1ii; + wire_nlill0Oll_w_lg_nl0OOi1il45816w(0) <= NOT nl0OOi1il; + wire_nlill0Oll_w_lg_nl0OOi1iO45815w(0) <= NOT nl0OOi1iO; + wire_nlill0Oll_w_lg_nl0OOi1li45814w(0) <= NOT nl0OOi1li; + wire_nlill0Oll_w_lg_nl0OOi1ll46139w(0) <= NOT nl0OOi1ll; + wire_nlill0Oll_w_lg_nl0OOi1lO46138w(0) <= NOT nl0OOi1lO; + wire_nlill0Oll_w_lg_nl0OOi1Oi46137w(0) <= NOT nl0OOi1Oi; + wire_nlill0Oll_w_lg_nl0OOi1Ol46136w(0) <= NOT nl0OOi1Ol; + wire_nlill0Oll_w_lg_nl0OOi1OO46135w(0) <= NOT nl0OOi1OO; + wire_nlill0Oll_w_lg_nl0OOii1i45754w(0) <= NOT nl0OOii1i; + wire_nlill0Oll_w_lg_nl0OOO00i45768w(0) <= NOT nl0OOO00i; + wire_nlill0Oll_w_lg_nl0OOO00l45767w(0) <= NOT nl0OOO00l; + wire_nlill0Oll_w_lg_nl0OOO00O45766w(0) <= NOT nl0OOO00O; + wire_nlill0Oll_w_lg_nl0OOO01i45755w(0) <= NOT nl0OOO01i; + wire_nlill0Oll_w_lg_nl0OOO01l45770w(0) <= NOT nl0OOO01l; + wire_nlill0Oll_w_lg_nl0OOO01O45769w(0) <= NOT nl0OOO01O; + wire_nlill0Oll_w_lg_nl0OOO0ii45765w(0) <= NOT nl0OOO0ii; + wire_nlill0Oll_w_lg_nl0OOO0il45764w(0) <= NOT nl0OOO0il; + wire_nlill0Oll_w_lg_nl0OOO0iO45763w(0) <= NOT nl0OOO0iO; + wire_nlill0Oll_w_lg_nl0OOO10i45751w(0) <= NOT nl0OOO10i; + wire_nlill0Oll_w_lg_nl0OOO10l45750w(0) <= NOT nl0OOO10l; + wire_nlill0Oll_w_lg_nl0OOO10O45749w(0) <= NOT nl0OOO10O; + wire_nlill0Oll_w_lg_nl0OOO11l45753w(0) <= NOT nl0OOO11l; + wire_nlill0Oll_w_lg_nl0OOO11O45752w(0) <= NOT nl0OOO11O; + wire_nlill0Oll_w_lg_nl0OOO1ii45748w(0) <= NOT nl0OOO1ii; + wire_nlill0Oll_w_lg_nl0OOO1il45747w(0) <= NOT nl0OOO1il; + wire_nlill0Oll_w_lg_nl0OOO1iO45762w(0) <= NOT nl0OOO1iO; + wire_nlill0Oll_w_lg_nl0OOO1li45761w(0) <= NOT nl0OOO1li; + wire_nlill0Oll_w_lg_nl0OOO1ll45760w(0) <= NOT nl0OOO1ll; + wire_nlill0Oll_w_lg_nl0OOO1lO45759w(0) <= NOT nl0OOO1lO; + wire_nlill0Oll_w_lg_nl0OOO1Oi45758w(0) <= NOT nl0OOO1Oi; + wire_nlill0Oll_w_lg_nl0OOO1Ol45757w(0) <= NOT nl0OOO1Ol; + wire_nlill0Oll_w_lg_nl0OOO1OO45756w(0) <= NOT nl0OOO1OO; + wire_nlill0Oll_w_lg_nl10iO1li45504w(0) <= NOT nl10iO1li; + wire_nlill0Oll_w_lg_nl10iOOli59405w(0) <= NOT nl10iOOli; + wire_nlill0Oll_w_lg_nl10iOOll59408w(0) <= NOT nl10iOOll; + wire_nlill0Oll_w_lg_nl10lliil8959w(0) <= NOT nl10lliil; + wire_nlill0Oll_w_lg_nl10lliiO58952w(0) <= NOT nl10lliiO; + wire_nlill0Oll_w_lg_nl10llili58950w(0) <= NOT nl10llili; + wire_nlill0Oll_w_lg_nl10llill58949w(0) <= NOT nl10llill; + wire_nlill0Oll_w_lg_nl10lliOO54079w(0) <= NOT nl10lliOO; + wire_nlill0Oll_w_lg_nl10lll1i58940w(0) <= NOT nl10lll1i; + wire_nlill0Oll_w_lg_nl10lll1l58938w(0) <= NOT nl10lll1l; + wire_nlill0Oll_w_lg_nl10lll1O58937w(0) <= NOT nl10lll1O; + wire_nlill0Oll_w_lg_nl10O0OOi59149w(0) <= NOT nl10O0OOi; + wire_nlill0Oll_w_lg_nl11100iO61702w(0) <= NOT nl11100iO; + wire_nlill0Oll_w_lg_nl11100li61700w(0) <= NOT nl11100li; + wire_nlill0Oll_w_lg_nl11100ll61698w(0) <= NOT nl11100ll; + wire_nlill0Oll_w_lg_nl11100lO61696w(0) <= NOT nl11100lO; + wire_nlill0Oll_w_lg_nl11100Oi61694w(0) <= NOT nl11100Oi; + wire_nlill0Oll_w_lg_nl11100Ol61692w(0) <= NOT nl11100Ol; + wire_nlill0Oll_w_lg_nl11100OO61690w(0) <= NOT nl11100OO; + wire_nlill0Oll_w_lg_nl11101il61704w(0) <= NOT nl11101il; + wire_nlill0Oll_w_lg_nl1110i0i61683w(0) <= NOT nl1110i0i; + wire_nlill0Oll_w_lg_nl1110i0l61642w(0) <= NOT nl1110i0l; + wire_nlill0Oll_w_lg_nl1110i0O61640w(0) <= NOT nl1110i0O; + wire_nlill0Oll_w_lg_nl1110i1i61688w(0) <= NOT nl1110i1i; + wire_nlill0Oll_w_lg_nl1110i1l61686w(0) <= NOT nl1110i1l; + wire_nlill0Oll_w_lg_nl1110i1O61684w(0) <= NOT nl1110i1O; + wire_nlill0Oll_w_lg_nl1110iii61638w(0) <= NOT nl1110iii; + wire_nlill0Oll_w_lg_nl1110iil61636w(0) <= NOT nl1110iil; + wire_nlill0Oll_w_lg_nl1110iiO61634w(0) <= NOT nl1110iiO; + wire_nlill0Oll_w_lg_nl1110ili61632w(0) <= NOT nl1110ili; + wire_nlill0Oll_w_lg_nl1110ill61630w(0) <= NOT nl1110ill; + wire_nlill0Oll_w_lg_nl1110ilO61629w(0) <= NOT nl1110ilO; + wire_nlill0Oll_w_lg_nl1110iOi61658w(0) <= NOT nl1110iOi; + wire_nlill0Oll_w_lg_nl1110iOl61656w(0) <= NOT nl1110iOl; + wire_nlill0Oll_w_lg_nl1110iOO61654w(0) <= NOT nl1110iOO; + wire_nlill0Oll_w_lg_nl1110l0i61646w(0) <= NOT nl1110l0i; + wire_nlill0Oll_w_lg_nl1110l0l61644w(0) <= NOT nl1110l0l; + wire_nlill0Oll_w_lg_nl1110l0O60380w(0) <= NOT nl1110l0O; + wire_nlill0Oll_w_lg_nl1110l1i61652w(0) <= NOT nl1110l1i; + wire_nlill0Oll_w_lg_nl1110l1l61650w(0) <= NOT nl1110l1l; + wire_nlill0Oll_w_lg_nl1110l1O61648w(0) <= NOT nl1110l1O; + wire_nlill0Oll_w_lg_nl1110lii60378w(0) <= NOT nl1110lii; + wire_nlill0Oll_w_lg_nl1110lil60376w(0) <= NOT nl1110lil; + wire_nlill0Oll_w_lg_nl1110liO60375w(0) <= NOT nl1110liO; + wire_nlill0Oll_w_lg_nl1110lli61627w(0) <= NOT nl1110lli; + wire_nlill0Oll_w_lg_nl1110lll61625w(0) <= NOT nl1110lll; + wire_nlill0Oll_w_lg_nl1110llO61623w(0) <= NOT nl1110llO; + wire_nlill0Oll_w_lg_nl1110lOi61621w(0) <= NOT nl1110lOi; + wire_nlill0Oll_w_lg_nl1110lOl61619w(0) <= NOT nl1110lOl; + wire_nlill0Oll_w_lg_nl1110lOO61617w(0) <= NOT nl1110lOO; + wire_nlill0Oll_w_lg_nl1110O0i61679w(0) <= NOT nl1110O0i; + wire_nlill0Oll_w_lg_nl1110O0l61677w(0) <= NOT nl1110O0l; + wire_nlill0Oll_w_lg_nl1110O0O61675w(0) <= NOT nl1110O0O; + wire_nlill0Oll_w_lg_nl1110O1i61615w(0) <= NOT nl1110O1i; + wire_nlill0Oll_w_lg_nl1110O1l61614w(0) <= NOT nl1110O1l; + wire_nlill0Oll_w_lg_nl1110O1O61681w(0) <= NOT nl1110O1O; + wire_nlill0Oll_w_lg_nl1110Oii61673w(0) <= NOT nl1110Oii; + wire_nlill0Oll_w_lg_nl1110Oil61671w(0) <= NOT nl1110Oil; + wire_nlill0Oll_w_lg_nl1110OiO61669w(0) <= NOT nl1110OiO; + wire_nlill0Oll_w_lg_nl1110Oli61667w(0) <= NOT nl1110Oli; + wire_nlill0Oll_w_lg_nl1110Oll61665w(0) <= NOT nl1110Oll; + wire_nlill0Oll_w_lg_nl1110OlO61663w(0) <= NOT nl1110OlO; + wire_nlill0Oll_w_lg_nl1110OOi61661w(0) <= NOT nl1110OOi; + wire_nlill0Oll_w_lg_nl1110OOl61660w(0) <= NOT nl1110OOl; + wire_nlill0Oll_w_lg_nl1110OOO61612w(0) <= NOT nl1110OOO; + wire_nlill0Oll_w_lg_nl111i10i61604w(0) <= NOT nl111i10i; + wire_nlill0Oll_w_lg_nl111i10l61602w(0) <= NOT nl111i10l; + wire_nlill0Oll_w_lg_nl111i10O61600w(0) <= NOT nl111i10O; + wire_nlill0Oll_w_lg_nl111i11i61610w(0) <= NOT nl111i11i; + wire_nlill0Oll_w_lg_nl111i11l61608w(0) <= NOT nl111i11l; + wire_nlill0Oll_w_lg_nl111i11O61606w(0) <= NOT nl111i11O; + wire_nlill0Oll_w_lg_nl111i1ii61599w(0) <= NOT nl111i1ii; + wire_nlill0Oll_w_lg_nl111l0il61452w(0) <= NOT nl111l0il; + wire_nlill0Oll_w_lg_nl111l0iO61450w(0) <= NOT nl111l0iO; + wire_nlill0Oll_w_lg_nl111l0li61449w(0) <= NOT nl111l0li; + wire_nlill0Oll_w_lg_nl111l0ll61446w(0) <= NOT nl111l0ll; + wire_nlill0Oll_w_lg_nl111l0lO61444w(0) <= NOT nl111l0lO; + wire_nlill0Oll_w_lg_nl111l0Oi61443w(0) <= NOT nl111l0Oi; + wire_nlill0Oll_w_lg_nl111l0Ol61440w(0) <= NOT nl111l0Ol; + wire_nlill0Oll_w_lg_nl111l0OO61438w(0) <= NOT nl111l0OO; + wire_nlill0Oll_w_lg_nl111li1i61437w(0) <= NOT nl111li1i; + wire_nlill0Oll_w_lg_nl111liOl61434w(0) <= NOT nl111liOl; + wire_nlill0Oll_w_lg_nl111liOO61432w(0) <= NOT nl111liOO; + wire_nlill0Oll_w_lg_nl111ll1i61431w(0) <= NOT nl111ll1i; + wire_nlill0Oll_w_lg_nl111ll1l60372w(0) <= NOT nl111ll1l; + wire_nlill0Oll_w_lg_nl111OO0i60384w(0) <= NOT nl111OO0i; + wire_nlill0Oll_w_lg_nl111OO0l60385w(0) <= NOT nl111OO0l; + wire_nlill0Oll_w_lg_nl111OO1i60373w(0) <= NOT nl111OO1i; + wire_nlill0Oll_w_lg_nl111OO1l60374w(0) <= NOT nl111OO1l; + wire_nlill0Oll_w_lg_nl111OO1O60383w(0) <= NOT nl111OO1O; + wire_nlill0Oll_w_lg_nl11lO01i52765w(0) <= NOT nl11lO01i; + wire_nlill0Oll_w_lg_nl11lO01l52763w(0) <= NOT nl11lO01l; + wire_nlill0Oll_w_lg_nl11lO01O52762w(0) <= NOT nl11lO01O; + wire_nlill0Oll_w_lg_nl11lO10l53746w(0) <= NOT nl11lO10l; + wire_nlill0Oll_w_lg_nl11lO10O45156w(0) <= NOT nl11lO10O; + wire_nlill0Oll_w_lg_nl11lO11l45162w(0) <= NOT nl11lO11l; + wire_nlill0Oll_w_lg_nl11lO11O45160w(0) <= NOT nl11lO11O; + wire_nlill0Oll_w_lg_nl11lO1ii45155w(0) <= NOT nl11lO1ii; + wire_nlill0Oll_w_lg_nl11lO1Oi44951w(0) <= NOT nl11lO1Oi; + wire_nlill0Oll_w_lg_nl11lO1Ol44949w(0) <= NOT nl11lO1Ol; + wire_nlill0Oll_w_lg_nl11lO1OO44955w(0) <= NOT nl11lO1OO; + wire_nlill0Oll_w_lg_nl11lOlll45171w(0) <= NOT nl11lOlll; + wire_nlill0Oll_w_lg_nl11lOllO45169w(0) <= NOT nl11lOllO; + wire_nlill0Oll_w_lg_nl11lOlOi45152w(0) <= NOT nl11lOlOi; + wire_nlill0Oll_w_lg_nl11lOlOl43385w(0) <= NOT nl11lOlOl; + wire_nlill0Oll_w_lg_nl11lOlOO44945w(0) <= NOT nl11lOlOO; + wire_nlill0Oll_w_lg_nl11lOO1i45149w(0) <= NOT nl11lOO1i; + wire_nlill0Oll_w_lg_nl11lOO1l45164w(0) <= NOT nl11lOO1l; + wire_nlill0Oll_w_lg_nl11Oii0i60369w(0) <= NOT nl11Oii0i; + wire_nlill0Oll_w_lg_nl11Oii0l59845w(0) <= NOT nl11Oii0l; + wire_nlill0Oll_w_lg_nl11OiliO60228w(0) <= NOT nl11OiliO; + wire_nlill0Oll_w_lg_nl11Oilll60507w(0) <= NOT nl11Oilll; + wire_nlill0Oll_w_lg_nl11OillO60509w(0) <= NOT nl11OillO; + wire_nlill0Oll_w_lg_nl11OilOi60511w(0) <= NOT nl11OilOi; + wire_nlill0Oll_w_lg_nl11OilOl60513w(0) <= NOT nl11OilOl; + wire_nlill0Oll_w_lg_nl11OilOO60515w(0) <= NOT nl11OilOO; + wire_nlill0Oll_w_lg_nl11OiO0i60523w(0) <= NOT nl11OiO0i; + wire_nlill0Oll_w_lg_nl11OiO1i60517w(0) <= NOT nl11OiO1i; + wire_nlill0Oll_w_lg_nl11OiO1l60519w(0) <= NOT nl11OiO1l; + wire_nlill0Oll_w_lg_nl11OiO1O60521w(0) <= NOT nl11OiO1O; + wire_nlill0Oll_w_lg_nl11OiOOl61552w(0) <= NOT nl11OiOOl; + wire_nlill0Oll_w_lg_nl11OiOOO61551w(0) <= NOT nl11OiOOO; + wire_nlill0Oll_w_lg_nl11Ol11i59967w(0) <= NOT nl11Ol11i; + wire_nlill0Oll_w_lg_nl11OO00i59963w(0) <= NOT nl11OO00i; + wire_nlill0Oll_w_lg_nl11OO00l60211w(0) <= NOT nl11OO00l; + wire_nlill0Oll_w_lg_nl11OO00O59842w(0) <= NOT nl11OO00O; + wire_nlill0Oll_w_lg_nl11OO0li59541w(0) <= NOT nl11OO0li; + wire_nlill0Oll_w_lg_nl11OO0ll59542w(0) <= NOT nl11OO0ll; + wire_nlill0Oll_w_lg_nl11OO0lO59867w(0) <= NOT nl11OO0lO; + wire_nlill0Oll_w_lg_nl11OOi0i59982w(0) <= NOT nl11OOi0i; + wire_nlill0Oll_w_lg_nl11OOOii59718w(0) <= NOT nl11OOOii; + wire_nlill0Oll_w_lg_nl1i010iO58944w(0) <= NOT nl1i010iO; + wire_nlill0Oll_w_lg_nl1i1000i58138w(0) <= NOT nl1i1000i; + wire_nlill0Oll_w_lg_nl1i1000l58140w(0) <= NOT nl1i1000l; + wire_nlill0Oll_w_lg_nl1i1000O58142w(0) <= NOT nl1i1000O; + wire_nlill0Oll_w_lg_nl1i1001i58132w(0) <= NOT nl1i1001i; + wire_nlill0Oll_w_lg_nl1i1001l58134w(0) <= NOT nl1i1001l; + wire_nlill0Oll_w_lg_nl1i1001O58136w(0) <= NOT nl1i1001O; + wire_nlill0Oll_w_lg_nl1i100ii58144w(0) <= NOT nl1i100ii; + wire_nlill0Oll_w_lg_nl1i100il58058w(0) <= NOT nl1i100il; + wire_nlill0Oll_w_lg_nl1i100iO58060w(0) <= NOT nl1i100iO; + wire_nlill0Oll_w_lg_nl1i100li58062w(0) <= NOT nl1i100li; + wire_nlill0Oll_w_lg_nl1i100ll58064w(0) <= NOT nl1i100ll; + wire_nlill0Oll_w_lg_nl1i100lO58066w(0) <= NOT nl1i100lO; + wire_nlill0Oll_w_lg_nl1i100Oi58068w(0) <= NOT nl1i100Oi; + wire_nlill0Oll_w_lg_nl1i100Ol58070w(0) <= NOT nl1i100Ol; + wire_nlill0Oll_w_lg_nl1i100OO58072w(0) <= NOT nl1i100OO; + wire_nlill0Oll_w_lg_nl1i1010i58166w(0) <= NOT nl1i1010i; + wire_nlill0Oll_w_lg_nl1i1010l58168w(0) <= NOT nl1i1010l; + wire_nlill0Oll_w_lg_nl1i1010O58170w(0) <= NOT nl1i1010O; + wire_nlill0Oll_w_lg_nl1i1011i58214w(0) <= NOT nl1i1011i; + wire_nlill0Oll_w_lg_nl1i1011l58216w(0) <= NOT nl1i1011l; + wire_nlill0Oll_w_lg_nl1i1011O58164w(0) <= NOT nl1i1011O; + wire_nlill0Oll_w_lg_nl1i101ii58172w(0) <= NOT nl1i101ii; + wire_nlill0Oll_w_lg_nl1i101il58174w(0) <= NOT nl1i101il; + wire_nlill0Oll_w_lg_nl1i101iO58176w(0) <= NOT nl1i101iO; + wire_nlill0Oll_w_lg_nl1i101li58178w(0) <= NOT nl1i101li; + wire_nlill0Oll_w_lg_nl1i101ll58180w(0) <= NOT nl1i101ll; + wire_nlill0Oll_w_lg_nl1i101lO58182w(0) <= NOT nl1i101lO; + wire_nlill0Oll_w_lg_nl1i101Oi58184w(0) <= NOT nl1i101Oi; + wire_nlill0Oll_w_lg_nl1i101Ol58186w(0) <= NOT nl1i101Ol; + wire_nlill0Oll_w_lg_nl1i101OO58130w(0) <= NOT nl1i101OO; + wire_nlill0Oll_w_lg_nl1i10i0i58098w(0) <= NOT nl1i10i0i; + wire_nlill0Oll_w_lg_nl1i10i0l58100w(0) <= NOT nl1i10i0l; + wire_nlill0Oll_w_lg_nl1i10i0O58102w(0) <= NOT nl1i10i0O; + wire_nlill0Oll_w_lg_nl1i10i1i58092w(0) <= NOT nl1i10i1i; + wire_nlill0Oll_w_lg_nl1i10i1l58094w(0) <= NOT nl1i10i1l; + wire_nlill0Oll_w_lg_nl1i10i1O58096w(0) <= NOT nl1i10i1O; + wire_nlill0Oll_w_lg_nl1i10iii58104w(0) <= NOT nl1i10iii; + wire_nlill0Oll_w_lg_nl1i10iil58106w(0) <= NOT nl1i10iil; + wire_nlill0Oll_w_lg_nl1i10iiO58108w(0) <= NOT nl1i10iiO; + wire_nlill0Oll_w_lg_nl1i10ili58110w(0) <= NOT nl1i10ili; + wire_nlill0Oll_w_lg_nl1i10ill58112w(0) <= NOT nl1i10ill; + wire_nlill0Oll_w_lg_nl1i10ilO58114w(0) <= NOT nl1i10ilO; + wire_nlill0Oll_w_lg_nl1i1101i59141w(0) <= NOT nl1i1101i; + wire_nlill0Oll_w_lg_nl1i1101l59140w(0) <= NOT nl1i1101l; + wire_nlill0Oll_w_lg_nl1i1101O58236w(0) <= NOT nl1i1101O; + wire_nlill0Oll_w_lg_nl1i111Oi59147w(0) <= NOT nl1i111Oi; + wire_nlill0Oll_w_lg_nl1i111Ol59145w(0) <= NOT nl1i111Ol; + wire_nlill0Oll_w_lg_nl1i111OO59143w(0) <= NOT nl1i111OO; + wire_nlill0Oll_w_lg_nl1i11lOl58238w(0) <= NOT nl1i11lOl; + wire_nlill0Oll_w_lg_nl1i11lOO58240w(0) <= NOT nl1i11lOO; + wire_nlill0Oll_w_lg_nl1i11O0i58248w(0) <= NOT nl1i11O0i; + wire_nlill0Oll_w_lg_nl1i11O0l58250w(0) <= NOT nl1i11O0l; + wire_nlill0Oll_w_lg_nl1i11O0O58252w(0) <= NOT nl1i11O0O; + wire_nlill0Oll_w_lg_nl1i11O1i58242w(0) <= NOT nl1i11O1i; + wire_nlill0Oll_w_lg_nl1i11O1l58244w(0) <= NOT nl1i11O1l; + wire_nlill0Oll_w_lg_nl1i11O1O58246w(0) <= NOT nl1i11O1O; + wire_nlill0Oll_w_lg_nl1i11Oii58254w(0) <= NOT nl1i11Oii; + wire_nlill0Oll_w_lg_nl1i11Oil58256w(0) <= NOT nl1i11Oil; + wire_nlill0Oll_w_lg_nl1i11OiO58258w(0) <= NOT nl1i11OiO; + wire_nlill0Oll_w_lg_nl1i11Oli58202w(0) <= NOT nl1i11Oli; + wire_nlill0Oll_w_lg_nl1i11Oll58204w(0) <= NOT nl1i11Oll; + wire_nlill0Oll_w_lg_nl1i11OlO58206w(0) <= NOT nl1i11OlO; + wire_nlill0Oll_w_lg_nl1i11OOi58208w(0) <= NOT nl1i11OOi; + wire_nlill0Oll_w_lg_nl1i11OOl58210w(0) <= NOT nl1i11OOl; + wire_nlill0Oll_w_lg_nl1i11OOO58212w(0) <= NOT nl1i11OOO; + wire_nlill0Oll_w_lg_nl1iil10O55851w(0) <= NOT nl1iil10O; + wire_nlill0Oll_w_lg_nl1iiO0li56217w(0) <= NOT nl1iiO0li; + wire_nlill0Oll_w_lg_nl1iiO0ll57606w(0) <= NOT nl1iiO0ll; + wire_nlill0Oll_w_lg_nl1iiO0lO57605w(0) <= NOT nl1iiO0lO; + wire_nlill0Oll_w_lg_nl1iiOiii56091w(0) <= NOT nl1iiOiii; + wire_nlill0Oll_w_lg_nl1il1i1l56094w(0) <= NOT nl1il1i1l; + wire_nlill0Oll_w_lg_nl1il1i1O56135w(0) <= NOT nl1il1i1O; + wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) <= NOT nl1l1iOii; + wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) <= NOT nl1l1iOil; + wire_nlill0Oll_w_lg_nl1ll0iiO55841w(0) <= NOT nl1ll0iiO; + wire_nlill0Oll_w_lg_nl1ll0ili55858w(0) <= NOT nl1ll0ili; + wire_nlill0Oll_w_lg_nl1ll0ilO55035w(0) <= NOT nl1ll0ilO; + wire_nlill0Oll_w_lg_nl1ll0iOi54179w(0) <= NOT nl1ll0iOi; + wire_nlill0Oll_w_lg_nl1ll0iOl54180w(0) <= NOT nl1ll0iOl; + wire_nlill0Oll_w_lg_nl1ll0l0i56922w(0) <= NOT nl1ll0l0i; + wire_nlill0Oll_w_lg_nl1ll0l0l56920w(0) <= NOT nl1ll0l0l; + wire_nlill0Oll_w_lg_nl1ll0l0O56918w(0) <= NOT nl1ll0l0O; + wire_nlill0Oll_w_lg_nl1ll0l1i56927w(0) <= NOT nl1ll0l1i; + wire_nlill0Oll_w_lg_nl1ll0l1l56929w(0) <= NOT nl1ll0l1l; + wire_nlill0Oll_w_lg_nl1ll0l1O56924w(0) <= NOT nl1ll0l1O; + wire_nlill0Oll_w_lg_nl1ll0lii56916w(0) <= NOT nl1ll0lii; + wire_nlill0Oll_w_lg_nl1ll0lil56914w(0) <= NOT nl1ll0lil; + wire_nlill0Oll_w_lg_nl1ll0liO56912w(0) <= NOT nl1ll0liO; + wire_nlill0Oll_w_lg_nl1ll0lli56910w(0) <= NOT nl1ll0lli; + wire_nlill0Oll_w_lg_nl1ll0lll56909w(0) <= NOT nl1ll0lll; + wire_nlill0Oll_w_lg_nl1ll0llO55838w(0) <= NOT nl1ll0llO; + wire_nlill0Oll_w_lg_nl1ll0lOi55058w(0) <= NOT nl1ll0lOi; + wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0) <= NOT nl1ll0lOl; + wire_nlill0Oll_w_lg_nl1lO1ilO56933w(0) <= NOT nl1lO1ilO; + wire_nlill0Oll_w_lg_nl1O1i0OO56932w(0) <= NOT nl1O1i0OO; + wire_nlill0Oll_w_lg_nl1O1ii1i56939w(0) <= NOT nl1O1ii1i; + wire_nlill0Oll_w_lg_nl1O1ii1l56938w(0) <= NOT nl1O1ii1l; + wire_nlill0Oll_w_lg_nl1OilliO55056w(0) <= NOT nl1OilliO; + wire_nlill0Oll_w_lg_nl1Oillli55050w(0) <= NOT nl1Oillli; + wire_nlill0Oll_w_lg_nl1Oillll55053w(0) <= NOT nl1Oillll; + wire_nlill0Oll_w_lg_nl1OilllO54891w(0) <= NOT nl1OilllO; + wire_nlill0Oll_w_lg_nl1OillOl54176w(0) <= NOT nl1OillOl; + wire_nlill0Oll_w_lg_nl1OillOO54177w(0) <= NOT nl1OillOO; + wire_nlill0Oll_w_lg_nl1OilO0O54864w(0) <= NOT nl1OilO0O; + wire_nlill0Oll_w_lg_nl1OilO1i54178w(0) <= NOT nl1OilO1i; + wire_nlill0Oll_w_lg_nl1OilOii54862w(0) <= NOT nl1OilOii; + wire_nlill0Oll_w_lg_nl1OilOil55037w(0) <= NOT nl1OilOil; + wire_nlill0Oll_w_lg_nl1Ol011O54883w(0) <= NOT nl1Ol011O; + wire_nlill0Oll_w_lg_nl1Ol1l0i55030w(0) <= NOT nl1Ol1l0i; + wire_nlill0Oll_w_lg_nl1Ol1l0l55394w(0) <= NOT nl1Ol1l0l; + wire_nlill0Oll_w_lg_nl1OllOOl54881w(0) <= NOT nl1OllOOl; + wire_nlill0Oll_w_lg_nl1OllOOO54880w(0) <= NOT nl1OllOOO; + wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) <= NOT nl1OlO11l; + wire_nlill0Oll_w_lg_nl1OO010i8963w(0) <= NOT nl1OO010i; + wire_nlill0Oll_w_lg_nl1OO010l54593w(0) <= NOT nl1OO010l; + wire_nlill0Oll_w_lg_nl1OOi01i54582w(0) <= NOT nl1OOi01i; + wire_nlill0Oll_w_lg_nl1OOi01l54523w(0) <= NOT nl1OOi01l; + wire_nlill0Oll_w_lg_nl1OOi1OO54545w(0) <= NOT nl1OOi1OO; + wire_nlill0Oll_w_lg_nl1OOii1l8961w(0) <= NOT nl1OOii1l; + wire_nlill0Oll_w_lg_nli0Oi0Ol45090w(0) <= NOT nli0Oi0Ol; + wire_nlill0Oll_w_lg_nli0Oiill45088w(0) <= NOT nli0Oiill; + wire_nlill0Oll_w_lg_nli0OOOOi44975w(0) <= NOT nli0OOOOi; + wire_nlill0Oll_w_lg_nli0OOOOl44973w(0) <= NOT nli0OOOOl; + wire_nlill0Oll_w_lg_nli0OOOOO44972w(0) <= NOT nli0OOOOO; + wire_nlill0Oll_w_lg_nli10001O46501w(0) <= NOT nli10001O; + wire_nlill0Oll_w_lg_nli10011i48069w(0) <= NOT nli10011i; + wire_nlill0Oll_w_lg_nli101ilO48080w(0) <= NOT nli101ilO; + wire_nlill0Oll_w_lg_nli101lOl48077w(0) <= NOT nli101lOl; + wire_nlill0Oll_w_lg_nli10Oiil46500w(0) <= NOT nli10Oiil; + wire_nlill0Oll_w_lg_nli10OiiO46499w(0) <= NOT nli10OiiO; + wire_nlill0Oll_w_lg_nli10Oili46498w(0) <= NOT nli10Oili; + wire_nlill0Oll_w_lg_nli10Olil46477w(0) <= NOT nli10Olil; + wire_nlill0Oll_w_lg_nli10OliO46478w(0) <= NOT nli10OliO; + wire_nlill0Oll_w_lg_nli10Olli46481w(0) <= NOT nli10Olli; + wire_nlill0Oll_w_lg_nli10OllO46484w(0) <= NOT nli10OllO; + wire_nlill0Oll_w_lg_nli10OlOi48046w(0) <= NOT nli10OlOi; + wire_nlill0Oll_w_lg_nli10OlOl46482w(0) <= NOT nli10OlOl; + wire_nlill0Oll_w_lg_nli10OlOO46479w(0) <= NOT nli10OlOO; + wire_nlill0Oll_w_lg_nli10OO0i48038w(0) <= NOT nli10OO0i; + wire_nlill0Oll_w_lg_nli10OO0l46486w(0) <= NOT nli10OO0l; + wire_nlill0Oll_w_lg_nli10OO1i46483w(0) <= NOT nli10OO1i; + wire_nlill0Oll_w_lg_nli10OO1l46480w(0) <= NOT nli10OO1l; + wire_nlill0Oll_w_lg_nli10OO1O46485w(0) <= NOT nli10OO1O; + wire_nlill0Oll_w_lg_nli11iiii44010w(0) <= NOT nli11iiii; + wire_nlill0Oll_w_lg_nli11iill46316w(0) <= NOT nli11iill; + wire_nlill0Oll_w_lg_nli11ilil46315w(0) <= NOT nli11ilil; + wire_nlill0Oll_w_lg_nli11iliO46314w(0) <= NOT nli11iliO; + wire_nlill0Oll_w_lg_nli11illi46313w(0) <= NOT nli11illi; + wire_nlill0Oll_w_lg_nli11illl44167w(0) <= NOT nli11illl; + wire_nlill0Oll_w_lg_nli11illO44166w(0) <= NOT nli11illO; + wire_nlill0Oll_w_lg_nli11l0OO48152w(0) <= NOT nli11l0OO; + wire_nlill0Oll_w_lg_nli11O0ii46538w(0) <= NOT nli11O0ii; + wire_nlill0Oll_w_lg_nli11OiOl46525w(0) <= NOT nli11OiOl; + wire_nlill0Oll_w_lg_nli11Ol0i46529w(0) <= NOT nli11Ol0i; + wire_nlill0Oll_w_lg_nli11Ol0l46528w(0) <= NOT nli11Ol0l; + wire_nlill0Oll_w_lg_nli11Ol0O46527w(0) <= NOT nli11Ol0O; + wire_nlill0Oll_w_lg_nli11Olii46526w(0) <= NOT nli11Olii; + wire_nlill0Oll_w_lg_nli11Olil46520w(0) <= NOT nli11Olil; + wire_nlill0Oll_w_lg_nli11OOll46524w(0) <= NOT nli11OOll; + wire_nlill0Oll_w_lg_nli11OOlO46523w(0) <= NOT nli11OOlO; + wire_nlill0Oll_w_lg_nli11OOOi46522w(0) <= NOT nli11OOOi; + wire_nlill0Oll_w_lg_nli11OOOl46521w(0) <= NOT nli11OOOl; + wire_nlill0Oll_w_lg_nli11OOOO48086w(0) <= NOT nli11OOOO; + wire_nlill0Oll_w_lg_nli1i011i46487w(0) <= NOT nli1i011i; + wire_nlill0Oll_w_lg_nli1i01li46492w(0) <= NOT nli1i01li; + wire_nlill0Oll_w_lg_nli1i01ll46493w(0) <= NOT nli1i01ll; + wire_nlill0Oll_w_lg_nli1i01lO46494w(0) <= NOT nli1i01lO; + wire_nlill0Oll_w_lg_nli1i01Oi46495w(0) <= NOT nli1i01Oi; + wire_nlill0Oll_w_lg_nli1i01Ol46496w(0) <= NOT nli1i01Ol; + wire_nlill0Oll_w_lg_nli1i01OO46497w(0) <= NOT nli1i01OO; + wire_nlill0Oll_w_lg_nli1i1OOl48024w(0) <= NOT nli1i1OOl; + wire_nlill0Oll_w_lg_nli1ii0li47984w(0) <= NOT nli1ii0li; + wire_nlill0Oll_w_lg_nli1ii0ll47970w(0) <= NOT nli1ii0ll; + wire_nlill0Oll_w_lg_nli1iiiiO47976w(0) <= NOT nli1iiiiO; + wire_nlill0Oll_w_lg_nli1iiili46418w(0) <= NOT nli1iiili; + wire_nlill0Oll_w_lg_nli1iiill46417w(0) <= NOT nli1iiill; + wire_nlill0Oll_w_lg_nli1iiOOl46426w(0) <= NOT nli1iiOOl; + wire_nlill0Oll_w_lg_nli1iiOOO46427w(0) <= NOT nli1iiOOO; + wire_nlill0Oll_w_lg_nli1il10i46430w(0) <= NOT nli1il10i; + wire_nlill0Oll_w_lg_nli1il10l43974w(0) <= NOT nli1il10l; + wire_nlill0Oll_w_lg_nli1il10O43948w(0) <= NOT nli1il10O; + wire_nlill0Oll_w_lg_nli1il11i46428w(0) <= NOT nli1il11i; + wire_nlill0Oll_w_lg_nli1il11O46429w(0) <= NOT nli1il11O; + wire_nlill0Oll_w_lg_nli1illll47936w(0) <= NOT nli1illll; + wire_nlill0Oll_w_lg_nli1illlO47940w(0) <= NOT nli1illlO; + wire_nlill0Oll_w_lg_nli1illOi47944w(0) <= NOT nli1illOi; + wire_nlill0Oll_w_lg_nli1illOl46365w(0) <= NOT nli1illOl; + wire_nlill0Oll_w_lg_nli1illOO46366w(0) <= NOT nli1illOO; + wire_nlill0Oll_w_lg_nli1ilO1i46367w(0) <= NOT nli1ilO1i; + wire_nlill0Oll_w_lg_nli1ilO1l46368w(0) <= NOT nli1ilO1l; + wire_nlill0Oll_w_lg_nli1iO0OO46369w(0) <= NOT nli1iO0OO; + wire_nlill0Oll_w_lg_nli1iOi0l46372w(0) <= NOT nli1iOi0l; + wire_nlill0Oll_w_lg_nli1iOiii46370w(0) <= NOT nli1iOiii; + wire_nlill0Oll_w_lg_nli1iOiiO46375w(0) <= NOT nli1iOiiO; + wire_nlill0Oll_w_lg_nli1iOili42902w(0) <= NOT nli1iOili; + wire_nlill0Oll_w_lg_nli1iOill42899w(0) <= NOT nli1iOill; + wire_nlill0Oll_w_lg_nli1iOilO42904w(0) <= NOT nli1iOilO; + wire_nlill0Oll_w_lg_nli1iOiOl46377w(0) <= NOT nli1iOiOl; + wire_nlill0Oll_w_lg_nli1iOiOO46378w(0) <= NOT nli1iOiOO; + wire_nlill0Oll_w_lg_nli1iOl1i46379w(0) <= NOT nli1iOl1i; + wire_nlill0Oll_w_lg_nli1iOl1l46380w(0) <= NOT nli1iOl1l; + wire_nlill0Oll_w_lg_nli1iOl1O46332w(0) <= NOT nli1iOl1O; + wire_nlill0Oll_w_lg_nli1l110O46331w(0) <= NOT nli1l110O; + wire_nlill0Oll_w_lg_nli1l11ii46340w(0) <= NOT nli1l11ii; + wire_nlill0Oll_w_lg_nli1l11il46339w(0) <= NOT nli1l11il; + wire_nlill0Oll_w_lg_nli1l11iO46338w(0) <= NOT nli1l11iO; + wire_nlill0Oll_w_lg_nli1l11li46337w(0) <= NOT nli1l11li; + wire_nlill0Oll_w_lg_nli1l11ll46336w(0) <= NOT nli1l11ll; + wire_nlill0Oll_w_lg_nli1l11lO46335w(0) <= NOT nli1l11lO; + wire_nlill0Oll_w_lg_nli1l11Oi46334w(0) <= NOT nli1l11Oi; + wire_nlill0Oll_w_lg_nli1l11Ol46333w(0) <= NOT nli1l11Ol; + wire_nlill0Oll_w_lg_nli1lilli47854w(0) <= NOT nli1lilli; + wire_nlill0Oll_w_lg_nli1liO1O47844w(0) <= NOT nli1liO1O; + wire_nlill0Oll_w_lg_nli1ll1ii47843w(0) <= NOT nli1ll1ii; + wire_nlill0Oll_w_lg_nli1ll1il47842w(0) <= NOT nli1ll1il; + wire_nlill0Oll_w_lg_nli1ll1iO47841w(0) <= NOT nli1ll1iO; + wire_nlill0Oll_w_lg_nlii110lO44996w(0) <= NOT nlii110lO; + wire_nlill0Oll_w_lg_nlii110Oi44994w(0) <= NOT nlii110Oi; + wire_nlill0Oll_w_lg_nlii110Ol44999w(0) <= NOT nlii110Ol; + wire_nlill0Oll_w_lg_nlii11i0O45506w(0) <= NOT nlii11i0O; + wire_nlill0Oll_w_lg_nliii000i44663w(0) <= NOT nliii000i; + wire_nlill0Oll_w_lg_nliii0lOO44662w(0) <= NOT nliii0lOO; + wire_nlill0Oll_w_lg_nliii0O1i44661w(0) <= NOT nliii0O1i; + wire_nlill0Oll_w_lg_nliiOOiii44117w(0) <= NOT nliiOOiii; + wire_nlill0Oll_w_lg_nliiOOill45520w(0) <= NOT nliiOOill; + wire_nlill0Oll_w_lg_nlil00i0l43345w(0) <= NOT nlil00i0l; + wire_nlill0Oll_w_lg_nlil00i1i43347w(0) <= NOT nlil00i1i; + wire_nlill0Oll_w_lg_nlil00iil43346w(0) <= NOT nlil00iil; + wire_nlill0Oll_w_lg_nlil0100i44132w(0) <= NOT nlil0100i; + wire_nlill0Oll_w_lg_nlil0100l44130w(0) <= NOT nlil0100l; + wire_nlill0Oll_w_lg_nlil0100O44128w(0) <= NOT nlil0100O; + wire_nlill0Oll_w_lg_nlil0101l44136w(0) <= NOT nlil0101l; + wire_nlill0Oll_w_lg_nlil0101O44134w(0) <= NOT nlil0101O; + wire_nlill0Oll_w_lg_nlil010ii44127w(0) <= NOT nlil010ii; + wire_nlill0Oll_w_lg_nlil010il44157w(0) <= NOT nlil010il; + wire_nlill0Oll_w_lg_nlil010iO44155w(0) <= NOT nlil010iO; + wire_nlill0Oll_w_lg_nlil010li44153w(0) <= NOT nlil010li; + wire_nlill0Oll_w_lg_nlil010ll44151w(0) <= NOT nlil010ll; + wire_nlill0Oll_w_lg_nlil010lO44149w(0) <= NOT nlil010lO; + wire_nlill0Oll_w_lg_nlil010Oi44147w(0) <= NOT nlil010Oi; + wire_nlill0Oll_w_lg_nlil010Ol44145w(0) <= NOT nlil010Ol; + wire_nlill0Oll_w_lg_nlil010OO44143w(0) <= NOT nlil010OO; + wire_nlill0Oll_w_lg_nlil01i0i43942w(0) <= NOT nlil01i0i; + wire_nlill0Oll_w_lg_nlil01i1i44141w(0) <= NOT nlil01i1i; + wire_nlill0Oll_w_lg_nlil01i1l44140w(0) <= NOT nlil01i1l; + wire_nlill0Oll_w_lg_nlil01i1O43932w(0) <= NOT nlil01i1O; + wire_nlill0Oll_w_lg_nlil1100i44089w(0) <= NOT nlil1100i; + wire_nlill0Oll_w_lg_nlil1100l44087w(0) <= NOT nlil1100l; + wire_nlill0Oll_w_lg_nlil11O1i44035w(0) <= NOT nlil11O1i; + wire_nlill0Oll_w_lg_nlil11Oil44028w(0) <= NOT nlil11Oil; + wire_nlill0Oll_w_lg_nlil11OiO43341w(0) <= NOT nlil11OiO; + wire_nlill0Oll_w_lg_nlil1i1OO43338w(0) <= NOT nlil1i1OO; + wire_nlill0Oll_w_lg_nlil1llOi43939w(0) <= NOT nlil1llOi; + wire_nlill0Oll_w_lg_nlil1llOl43953w(0) <= NOT nlil1llOl; + wire_nlill0Oll_w_lg_nlil1lOii52245w(0) <= NOT nlil1lOii; + wire_nlill0Oll_w_lg_nlil1lOil43935w(0) <= NOT nlil1lOil; + wire_nlill0Oll_w_lg_nlil1lOli44164w(0) <= NOT nlil1lOli; + wire_nlill0Oll_w_lg_nlil1OOiO44162w(0) <= NOT nlil1OOiO; + wire_nlill0Oll_w_lg_nlil1OOli44160w(0) <= NOT nlil1OOli; + wire_nlill0Oll_w_lg_nlil1OOll44159w(0) <= NOT nlil1OOll; + wire_nlill0Oll_w_lg_nlil1OOlO44138w(0) <= NOT nlil1OOlO; + wire_nlill0Oll_w_lg_nlilillil43258w(0) <= NOT nlilillil; + wire_nlill0Oll_w_lg_nlililOli42942w(0) <= NOT nlililOli; + wire_nlill0Oll_w_lg_nliliO11i42940w(0) <= NOT nliliO11i; + wire_nlill0Oll_w_lg_nliliO11l42939w(0) <= NOT nliliO11l; + wire_nlill0Oll_w_lg_nliliO1li42964w(0) <= NOT nliliO1li; + wire_nlill0Oll_w_lg_nlill1i0O44980w(0) <= NOT nlill1i0O; + wire_nlill0Oll_w_lg_nlill1l0O44978w(0) <= NOT nlill1l0O; + wire_nlill0Oll_w_lg_nlill1lii44977w(0) <= NOT nlill1lii; + wire_nlill0Oll_w_lg_nlill1lli45669w(0) <= NOT nlill1lli; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0llO53572w53594w53595w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0llO53572w53594w(0) OR nl01ii1Oi; + wire_nlill0Oll_w_lg_w_lg_nl01l0lll53411w53412w(0) <= wire_nlill0Oll_w_lg_nl01l0lll53411w(0) OR niOi000Oi; + wire_nlill0Oll_w_lg_w_lg_nl01l0lOi53433w53434w(0) <= wire_nlill0Oll_w_lg_nl01l0lOi53433w(0) OR niOi00l0l; + wire_nlill0Oll_w_lg_w_lg_nl0OiOl0i46167w47752w(0) <= wire_nlill0Oll_w_lg_nl0OiOl0i46167w(0) OR niOiiO00l; + wire_nlill0Oll_w_lg_w_lg_nl1ll0iiO55841w55843w(0) <= wire_nlill0Oll_w_lg_nl1ll0iiO55841w(0) OR wire_nlill0Oll_w_lg_w_lg_nl1ll0llO55838w55842w(0); + wire_nlill0Oll_w_lg_w_lg_nl1OilOii54862w54863w(0) <= wire_nlill0Oll_w_lg_nl1OilOii54862w(0) OR nlliO1Oi; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lOi53433w53434w53436w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0lOi53433w53434w(0) OR wire_nlill0Oll_w_lg_nl01l0lOi53435w(0); + wire_nlill0Oll_w53438w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lOi53433w53434w53436w(0) OR wire_w_lg_niOi0lOii53437w(0); + wire_nlill0Oll_w53422w(0) <= wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lil53414w53418w53421w(0) OR niOi00l1O; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lil53414w53418w53421w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0lil53414w53418w(0) OR wire_nlill0Oll_w_lg_nl01l0llO53420w(0); + wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lOi53324w53325w53326w(0) <= wire_nlill0Oll_w_lg_w_lg_nl01l0lOi53324w53325w(0) OR niOi00l0i; + wire_nlill0Oll_w_lg_w_lg_w_lg_nl1OilO1O55178w55179w55180w(0) <= wire_nlill0Oll_w_lg_w_lg_nl1OilO1O55178w55179w(0) OR nl1OillOl; + wire_nlill0Oll_w_lg_w_lg_nl01l0lil53414w53418w(0) <= wire_nlill0Oll_w_lg_nl01l0lil53414w(0) OR wire_nlill0Oll_w_lg_nl01l0lOi53417w(0); + wire_nlill0Oll_w_lg_w_lg_nl01l0lOi53324w53325w(0) <= wire_nlill0Oll_w_lg_nl01l0lOi53324w(0) OR niOi00l0l; + wire_nlill0Oll_w_lg_w_lg_nl01l0lOO53327w53328w(0) <= wire_nlill0Oll_w_lg_nl01l0lOO53327w(0) OR niOi00l1O; + wire_nlill0Oll_w_lg_w_lg_nl10iO1li43256w43257w(0) <= wire_nlill0Oll_w_lg_nl10iO1li43256w(0) OR nli1il11l; + wire_nlill0Oll_w_lg_w_lg_nl1OilO1O55178w55179w(0) <= wire_nlill0Oll_w_lg_nl1OilO1O55178w(0) OR nl1OillOO; + wire_nlill0Oll_w_lg_w_lg_nl1OO010l54837w54838w(0) <= wire_nlill0Oll_w_lg_nl1OO010l54837w(0) OR nli1100i; + wire_nlill0Oll_w_lg_w_lg_nli11l0Ol51961w51962w(0) <= wire_nlill0Oll_w_lg_nli11l0Ol51961w(0) OR ni0llOO; + wire_nlill0Oll_w_lg_nl01ii1lO45016w(0) <= nl01ii1lO OR nl01ii1ll; + wire_nlill0Oll_w_lg_nl01l0lii53416w(0) <= nl01l0lii OR wire_w_lg_niOi000lO53415w(0); + wire_nlill0Oll_w_lg_nl01l0lil53414w(0) <= nl01l0lil OR niOi00l0l; + wire_nlill0Oll_w_lg_nl01l0liO53567w(0) <= nl01l0liO OR niOilllOi; + wire_nlill0Oll_w_lg_nl01l0lli53568w(0) <= nl01l0lli OR wire_nlill0Oll_w_lg_nl01l0liO53567w(0); + wire_nlill0Oll_w_lg_nl01l0llO53439w(0) <= nl01l0llO OR wire_nlill0Oll_w53438w(0); + wire_nlill0Oll_w_lg_nl01l0llO53572w(0) <= nl01l0llO OR wire_nlill0Oll_w_lg_nl01l0lOi53571w(0); + wire_nlill0Oll_w_lg_nl01l0llO53591w(0) <= nl01l0llO OR wire_nlill0Oll_w_lg_nl01l0lOl53590w(0); + wire_nlill0Oll_w_lg_nl01l0lOi53571w(0) <= nl01l0lOi OR niOi0001i; + wire_nlill0Oll_w_lg_nl01l0lOi53324w(0) <= nl01l0lOi OR nl01l0llO; + wire_nlill0Oll_w_lg_nl01l0lOl53590w(0) <= nl01l0lOl OR nl01l0lOi; + wire_nlill0Oll_w_lg_nl01l0lOO53327w(0) <= nl01l0lOO OR wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0lOi53324w53325w53326w(0); + wire_nlill0Oll_w_lg_nl10iO1li43256w(0) <= nl10iO1li OR wire_nilOOill_w_lg_dataout43255w(0); + wire_nlill0Oll_w_lg_nl10lliOO54083w(0) <= nl10lliOO OR nl10lliil; + wire_nlill0Oll_w_lg_nl111OO1l61530w(0) <= nl111OO1l OR wire_w_lg_niOi11Oii61529w(0); + wire_nlill0Oll_w_lg_nl111OO1O61527w(0) <= nl111OO1O OR wire_w_lg_niOi11Oil61526w(0); + wire_nlill0Oll_w_lg_nl11OO0il60206w(0) <= nl11OO0il OR wire_w_lg_w_lg_niOi10l0O60203w60205w(0); + wire_nlill0Oll_w_lg_nl11OO0OO60061w(0) <= nl11OO0OO OR nl11OO0ll; + wire_nlill0Oll_w_lg_nl1ll0llO55563w(0) <= nl1ll0llO OR wire_nlill0Oll_w_lg_nl1Ol1l0l55562w(0); + wire_nlill0Oll_w_lg_nl1OilO1O55178w(0) <= nl1OilO1O OR nl1OilO1i; + wire_nlill0Oll_w_lg_nl1Ol1l0l55562w(0) <= nl1Ol1l0l OR niOi1lOiO; + wire_nlill0Oll_w_lg_nl1OlO11l55412w(0) <= nl1OlO11l OR wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55411w(0); + wire_nlill0Oll_w_lg_nl1OlO11l55419w(0) <= nl1OlO11l OR wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55418w(0); + wire_nlill0Oll_w_lg_nl1OO010l54837w(0) <= nl1OO010l OR nl1OO010i; + wire_nlill0Oll_w_lg_nl1OOii1l54830w(0) <= nl1OOii1l OR wire_nl011Ol1l_w_lg_dataout54829w(0); + wire_nlill0Oll_w_lg_nli11l0Ol51961w(0) <= nli11l0Ol OR nli0Oi0lO; + wire_nlill0Oll_w_lg_nli1i011i48055w(0) <= nli1i011i OR nli10Olll; + wire_nlill0Oll_w_lg_nlil00i0l43959w(0) <= nlil00i0l OR wire_nlill0Oll_w_lg_nlil00i0O43958w(0); + wire_nlill0Oll_w_lg_nlil00i0O43958w(0) <= nlil00i0O OR nlil00i1i; + wire_nlill0Oll_w_lg_nlil01i1O43944w(0) <= nlil01i1O OR wire_w_lg_niOilO0iO43943w(0); + wire_nlill0Oll_w_lg_nli10Olll48050w(0) <= nli10Olll XOR niOOOO1l; + wire_nlill0Oll_w_lg_nli1i011i48146w(0) <= nli1i011i XOR nli1i1OOO; + wire_nlill0Oll_w_lg_nli1i1OOl48133w(0) <= nli1i1OOl XOR nli1i1OOi; + PROCESS (core_clk, wire_niO0010l_dataout) + BEGIN + IF (wire_niO0010l_dataout = '0') THEN + nlliOOlOO <= '0'; + nlliOOO0i <= '0'; + nlliOOO0l <= '0'; + nlliOOO0O <= '0'; + nlliOOO1i <= '0'; + nlliOOO1l <= '0'; + nlliOOO1O <= '0'; + nlliOOOii <= '0'; + nlliOOOil <= '0'; + nlliOOOiO <= '0'; + nlliOOOli <= '0'; + nlliOOOll <= '0'; + nlliOOOlO <= '0'; + nlliOOOOi <= '0'; + nlliOOOOl <= '0'; + nlliOOOOO <= '0'; + nlll1100i <= '0'; + nlll1100l <= '0'; + nlll1100O <= '0'; + nlll1101i <= '0'; + nlll1101l <= '0'; + nlll1101O <= '0'; + nlll110ii <= '0'; + nlll110il <= '0'; + nlll110iO <= '0'; + nlll110li <= '0'; + nlll110ll <= '0'; + nlll110lO <= '0'; + nlll110Oi <= '0'; + nlll110Ol <= '0'; + nlll110OO <= '0'; + nlll1110i <= '0'; + nlll1110l <= '0'; + nlll1110O <= '0'; + nlll1111i <= '0'; + nlll1111l <= '0'; + nlll1111O <= '0'; + nlll111ii <= '0'; + nlll111il <= '0'; + nlll111iO <= '0'; + nlll111li <= '0'; + nlll111ll <= '0'; + nlll111lO <= '0'; + nlll111Oi <= '0'; + nlll111Ol <= '0'; + nlll111OO <= '0'; + nlll11i0i <= '0'; + nlll11i0l <= '0'; + nlll11i0O <= '0'; + nlll11i1i <= '0'; + nlll11i1l <= '0'; + nlll11i1O <= '0'; + nlll11iii <= '0'; + nlll11iil <= '0'; + nlll11iiO <= '0'; + nlll11ili <= '0'; + nlll11ill <= '0'; + nlll11ilO <= '0'; + nlll11iOi <= '0'; + nlll11iOl <= '0'; + nlll11iOO <= '0'; + nlll11l0i <= '0'; + nlll11l1i <= '0'; + nlll11l1l <= '0'; + ELSIF (core_clk = '1' AND core_clk'event) THEN + IF (niOiOl11i = '1') THEN + nlliOOlOO <= dout_rpl(0); + nlliOOO0i <= dout_rpl(4); + nlliOOO0l <= dout_rpl(5); + nlliOOO0O <= dout_rpl(6); + nlliOOO1i <= dout_rpl(1); + nlliOOO1l <= dout_rpl(2); + nlliOOO1O <= dout_rpl(3); + nlliOOOii <= dout_rpl(7); + nlliOOOil <= dout_rpl(8); + nlliOOOiO <= dout_rpl(9); + nlliOOOli <= dout_rpl(10); + nlliOOOll <= dout_rpl(11); + nlliOOOlO <= dout_rpl(12); + nlliOOOOi <= dout_rpl(13); + nlliOOOOl <= dout_rpl(14); + nlliOOOOO <= dout_rpl(15); + nlll1100i <= dout_rpl(34); + nlll1100l <= dout_rpl(35); + nlll1100O <= dout_rpl(36); + nlll1101i <= dout_rpl(31); + nlll1101l <= dout_rpl(32); + nlll1101O <= dout_rpl(33); + nlll110ii <= dout_rpl(37); + nlll110il <= dout_rpl(38); + nlll110iO <= dout_rpl(39); + nlll110li <= dout_rpl(40); + nlll110ll <= dout_rpl(41); + nlll110lO <= dout_rpl(42); + nlll110Oi <= dout_rpl(43); + nlll110Ol <= dout_rpl(44); + nlll110OO <= dout_rpl(45); + nlll1110i <= dout_rpl(19); + nlll1110l <= dout_rpl(20); + nlll1110O <= dout_rpl(21); + nlll1111i <= dout_rpl(16); + nlll1111l <= dout_rpl(17); + nlll1111O <= dout_rpl(18); + nlll111ii <= dout_rpl(22); + nlll111il <= dout_rpl(23); + nlll111iO <= dout_rpl(24); + nlll111li <= dout_rpl(25); + nlll111ll <= dout_rpl(26); + nlll111lO <= dout_rpl(27); + nlll111Oi <= dout_rpl(28); + nlll111Ol <= dout_rpl(29); + nlll111OO <= dout_rpl(30); + nlll11i0i <= dout_rpl(49); + nlll11i0l <= dout_rpl(50); + nlll11i0O <= dout_rpl(51); + nlll11i1i <= dout_rpl(46); + nlll11i1l <= dout_rpl(47); + nlll11i1O <= dout_rpl(48); + nlll11iii <= dout_rpl(52); + nlll11iil <= dout_rpl(53); + nlll11iiO <= dout_rpl(54); + nlll11ili <= dout_rpl(55); + nlll11ill <= dout_rpl(56); + nlll11ilO <= dout_rpl(57); + nlll11iOi <= dout_rpl(58); + nlll11iOl <= dout_rpl(59); + nlll11iOO <= dout_rpl(60); + nlll11l0i <= dout_rpl(63); + nlll11l1i <= dout_rpl(61); + nlll11l1l <= dout_rpl(62); + END IF; + END IF; + END PROCESS; + PROCESS (core_clk) + BEGIN + IF (core_clk = '1' AND core_clk'event) THEN + n1il1i0O <= wire_n1illl1l_dataout; + niO0111l <= (niO01Oii OR (wire_niO0010O_w_lg_niO01OOl8791w(0) OR wire_nllliiOO_w_lg_niO1OOOl8792w(0))); + niO01O0i <= core_crst; + niO01O1l <= niO01O0i; + niO01Oii <= niO01OiO; + niO01OiO <= core_srst; + niO1OOOl <= niO1OOOO; + niO1OOOO <= niO001il; + niOiil0O <= wire_niOiiliO_dataout; + niOlOiOl <= wire_niOlOl1l_dataout; + niOlOO0O <= wire_niOlOOiO_dataout; + niOO000i <= wire_niOO00ii_dataout; + niOO0ilO <= niOO0ill; + niOO0iOi <= wire_niOO0l1O_dataout; + niOO0O0O <= wire_niOO0Oll_dataout; + niOO11Ol <= wire_niOO101l_dataout; + niOO1iii <= wire_niOO1ili_dataout; + niOO1lOO <= wire_niOO1O1O_dataout; + niOOi01ll <= wire_niOOi01Ol_dataout; + niOOi1Ol <= wire_niOOi00i_dataout; + niOOl1ll <= wire_niOOl1Ol_dataout; + niOOlO1O <= wire_niOOlO0O_dataout; + niOOO10i <= wire_niOOO1iO_dataout; + niOOOi0i <= wire_niOOOiii_dataout; + niOOOlii <= niOOOl0O; + niOOOlli <= niOOOliO; + niOOOlOi <= niOOOllO; + niOOOO0i <= niOOOO1O; + niOOOO1i <= niOOOlOO; + niOOOOlO <= wire_niOOOOOO_dataout; + nl00lO1i <= wire_nl00Ol0l_dataout; + nl010Oll <= wire_nl01i11i_dataout; + nl011lil <= wire_nl011lll_dataout; + nl01i00i <= wire_nl01i0iO_dataout; + nl01llOO <= wire_nl01Ol0i_dataout; + nl0Olili <= wire_nl0OlOil_dataout; + nl0OOlii <= wire_nl0OOO0O_dataout; + nl10001O <= wire_nl10000O_dataout; + nl1010Ol <= wire_nl101i0i_dataout; + nl1011Oi <= wire_nl10101i_dataout; + nl10i1ii <= wire_nl10i1li_dataout; + nl10ilOl <= wire_nl10iO1l_dataout; + nl10l00i <= nl10l01O; + nl10l01i <= nl10l1OO; + nl10l1Oi <= nl10l1lO; + nl10lllO <= wire_nl10llOO_dataout; + nl1101Ol <= wire_nl11001l_dataout; + nl110iii <= wire_nl110ili_dataout; + nl110lOO <= wire_nl110O1O_dataout; + nl11100l <= wire_nl1110il_dataout; + nl111iOi <= wire_nl111l1i_dataout; + nl111lOl <= wire_nl111O0l_dataout; + nl11i1il <= wire_nl11i1ll_dataout; + nl11ii1i <= wire_nl11ii0i_dataout; + nl11iliO <= wire_nl11illO_dataout; + nl11l01O <= wire_nl11l0iO_dataout; + nl11l11l <= wire_nl11l10l_dataout; + nl11lill <= wire_nl11ll1l_dataout; + nl11lO0i <= wire_nl11lOli_dataout; + nl11O1lO <= wire_nl11O01O_dataout; + nl11Oi0l <= wire_nl11Oill_dataout; + nl11OlOi <= wire_nl11OO1O_dataout; + nl1i1lOl <= wire_nl1i1O1l_dataout; + nl1ii1li <= wire_nl1ii1Oi_dataout; + nl1iii1i <= wire_nl1iii0O_dataout; + nl1iiliO <= wire_nl1iilOl_dataout; + nl1il10O <= wire_nl1il1Ol_dataout; + nl1iO1OO <= wire_nl1iO01O_dataout; + nl1iOOOO <= wire_nl1l110l_dataout; + nl1l001l <= wire_nl1l00ii_dataout; + nl1l0ili <= wire_nl1l0iOO_dataout; + nl1l0Oil <= nl1l0Oii; + nl1l10il <= wire_nl1l10Oi_dataout; + nl1l1l1i <= wire_nl1l1l0O_dataout; + nl1l1OiO <= wire_nl1l1OOl_dataout; + nl1li11l <= wire_nl1li1Ol_dataout; + nl1lilii <= wire_nl1liO0O_dataout; + nl1ll00O <= nl1ll00l; + nl1ll0iO <= nl1ll0il; + nl1llO1l <= wire_nl1llOli_dataout; + nl1lO0il <= wire_nl1lOi0l_dataout; + nl1O001l <= wire_nl1O000l_dataout; + nl1O0ili <= wire_nl1O0iOi_dataout; + nl1O0O1O <= wire_nl1O0O0O_dataout; + nl1O1iil <= wire_nl1O1ill_dataout; + nl1O1O1l <= wire_nl1O1Oii_dataout; + nl1Oi0lO <= wire_nl1Oii1l_dataout; + nl1Oi1ll <= wire_nl1Oi1Ol_dataout; + nl1Oil0l <= wire_nl1Oilli_dataout; + nl1Ol0Oi <= wire_nl1Oli1i_dataout; + nl1Ol10l <= wire_nl1Ol1il_dataout; + nl1Oll0O <= wire_nl1OlliO_dataout; + nl1OlOOl <= wire_nl1OO11l_dataout; + nli1000i <= wire_nli1i1il_dataout; + nli1000O <= wire_nli1i1iO_dataout; + nli100ii <= wire_nli1i1li_dataout; + nli100il <= wire_nli1i1ii_dataout; + nli1100O <= nli1100l; + nllli10l <= wire_nllli0ll_dataout; + nllli1iO <= wire_nllli0li_dataout; + nllli1li <= wire_nllli0iO_dataout; + nlllil1i <= wire_nllli0lO_dataout; + nlOi000lO <= wire_nlOi000OO_dataout; + nlOi0011O <= wire_nlOi0010O_dataout; + nlOi00lli <= nlOi00liO; + nlOi00lOl <= nlOi00lOi; + nlOi00OOO <= wire_nlOi0i11O_dataout; + nlOi0i00O <= nlOi0i00l; + nlOi0ilOl <= wire_nlOi0l1lO_dataout; + nlOi0lOii <= nlOi0lO0O; + nlOi0lOiO <= wire_nlOi0lOOO_dataout; + nlOi0O0li <= wire_nlOi0O0Oi_dataout; + nlOi0Ol0i <= wire_nlOi0Olii_dataout; + nlOi0OO0O <= wire_nlOi0OOlO_dataout; + nlOii01li <= wire_nlOii01Oi_dataout; + nlOii0i0i <= wire_nlOii0iii_dataout; + nlOii0OOl <= nlOii0OOi; + nlOii1iii <= wire_nlOii1ili_dataout; + nlOii1O1i <= wire_nlOii1O0i_dataout; + nlOiii00i <= wire_nlOiii0ii_dataout; + nlOiii11O <= nlOiii11l; + nlOiii1ii <= nlOiii10O; + nlOiii1ll <= nlOiii1li; + nlOiiiili <= wire_nlOiiiilO_dataout; + nlOiil01O <= wire_nlOiil00O_dataout; + nlOiiO10i <= wire_nlOiiO1ii_dataout; + nlOiiOlOi <= wire_nlOiiOO1i_dataout; + nlOil1i0i <= wire_nlOil1O0O_dataout; + nlOil1i0l <= wire_nlOil1Oii_dataout; + nlOil1i0O <= wire_nlOil1O0i_dataout; + nlOil1i1l <= wire_nlOil1O0l_dataout; + nlOili1il <= wire_nlOili1ll_dataout; + nlOilii1i <= wire_nlOilii1O_dataout; + nlOilii1l <= wire_nlOilii0i_dataout; + nlOiliiii <= wire_nlOilii0l_dataout; + nlOilil1l <= wire_nlOilii0O_dataout; + nlOilO0ii <= wire_nlOilO0li_dataout; + nlOilOl1i <= wire_nlOilOl0i_dataout; + nlOilOOli <= wire_nlOilOOOi_dataout; + END IF; + END PROCESS; + wire_nllliiOO_w_lg_niO1OOOl8792w(0) <= NOT niO1OOOl; + PROCESS (pld_clk, wire_nlllil0i_PRN, wire_nlllil0i_CLRN) + BEGIN + IF (wire_nlllil0i_PRN = '0') THEN + niO010il <= '1'; + niO0111i <= '1'; + niO0111O <= '1'; + niO011il <= '1'; + niO01iil <= '1'; + niO01lOl <= '1'; + niO01O1i <= '1'; + niOi00Ol <= '1'; + niOlOiii <= '1'; + niOlOlOO <= '1'; + niOO01il <= '1'; + niOO0l0i <= '1'; + niOO0Oi0O <= '1'; + niOO0OlO <= '1'; + niOO11il <= '1'; + niOO1i1i <= '1'; + niOO1liO <= '1'; + niOOi00l <= '1'; + niOOi1l1l <= '1'; + niOOilOl <= '1'; + niOOllll <= '1'; + niOOO0lO <= '1'; + niOOO1li <= '1'; + niOOOO0l <= '1'; + nl00Ol0O <= '1'; + nl01i0li <= '1'; + nl01i11l <= '1'; + nl01iiOl <= '1'; + nl01Ol0l <= '1'; + nl0OlOiO <= '1'; + nl0OOOii <= '1'; + nl100Oii <= '1'; + nl10110O <= '1'; + nl101i0l <= '1'; + nl101Oli <= '1'; + nl10iiOl <= '1'; + nl10li0O <= '1'; + nl10O00l <= '1'; + nl10O0il <= '1'; + nl10O0ll <= '1'; + nl10O0Ol <= '1'; + nl10Oi0l <= '1'; + nl10Oi1l <= '1'; + nl10Oiil <= '1'; + nl10Oill <= '1'; + nl1100OO <= '1'; + nl1101ii <= '1'; + nl110lil <= '1'; + nl1111Oi <= '1'; + nl111i0O <= '1'; + nl111O0O <= '1'; + nl11i0iO <= '1'; + nl11i11i <= '1'; + nl11il1l <= '1'; + nl11iOli <= '1'; + nl11l0li <= '1'; + nl11ll1O <= '1'; + nl11lOll <= '1'; + nl11O00i <= '1'; + nl11OilO <= '1'; + nl11OO0i <= '1'; + nl1i0OOl <= '1'; + nl1i11Oi <= '1'; + nl1iiiii <= '1'; + nl1iilOO <= '1'; + nl1il1OO <= '1'; + nl1illOl <= '1'; + nl1iOOil <= '1'; + nl1iOOll <= '1'; + nl1iOOOl <= '1'; + nl1l00il <= '1'; + nl1l0l1i <= '1'; + nl1l0O0l <= '1'; + nl1l10Ol <= '1'; + nl1l110O <= '1'; + nl1l1lii <= '1'; + nl1l1OOO <= '1'; + nl1li1OO <= '1'; + nl1liill <= '1'; + nl1liOii <= '1'; + nl1ll0lO <= '1'; + nl1llOll <= '1'; + nl1lOi0O <= '1'; + nl1O01li <= '1'; + nl1O0i1O <= '1'; + nl1O0lll <= '1'; + nl1O10li <= '1'; + nl1O1Oil <= '1'; + nl1Oi10i <= '1'; + nl1Oii1O <= '1'; + nl1Oilll <= '1'; + nl1OiOOi <= '1'; + nl1Ol00O <= '1'; + nl1OliOl <= '1'; + nl1OlOii <= '1'; + nl1OOOiO <= '1'; + nli1000l <= '1'; + nli110li <= '1'; + nli11l0O <= '1'; + nli11l1l <= '1'; + nli11lii <= '1'; + nlll0lOi <= '1'; + nllliiOl <= '1'; + nlllil0l <= '1'; + nlllil1l <= '1'; + nlllil1O <= '1'; + ELSIF (wire_nlllil0i_CLRN = '0') THEN + niO010il <= '0'; + niO0111i <= '0'; + niO0111O <= '0'; + niO011il <= '0'; + niO01iil <= '0'; + niO01lOl <= '0'; + niO01O1i <= '0'; + niOi00Ol <= '0'; + niOlOiii <= '0'; + niOlOlOO <= '0'; + niOO01il <= '0'; + niOO0l0i <= '0'; + niOO0Oi0O <= '0'; + niOO0OlO <= '0'; + niOO11il <= '0'; + niOO1i1i <= '0'; + niOO1liO <= '0'; + niOOi00l <= '0'; + niOOi1l1l <= '0'; + niOOilOl <= '0'; + niOOllll <= '0'; + niOOO0lO <= '0'; + niOOO1li <= '0'; + niOOOO0l <= '0'; + nl00Ol0O <= '0'; + nl01i0li <= '0'; + nl01i11l <= '0'; + nl01iiOl <= '0'; + nl01Ol0l <= '0'; + nl0OlOiO <= '0'; + nl0OOOii <= '0'; + nl100Oii <= '0'; + nl10110O <= '0'; + nl101i0l <= '0'; + nl101Oli <= '0'; + nl10iiOl <= '0'; + nl10li0O <= '0'; + nl10O00l <= '0'; + nl10O0il <= '0'; + nl10O0ll <= '0'; + nl10O0Ol <= '0'; + nl10Oi0l <= '0'; + nl10Oi1l <= '0'; + nl10Oiil <= '0'; + nl10Oill <= '0'; + nl1100OO <= '0'; + nl1101ii <= '0'; + nl110lil <= '0'; + nl1111Oi <= '0'; + nl111i0O <= '0'; + nl111O0O <= '0'; + nl11i0iO <= '0'; + nl11i11i <= '0'; + nl11il1l <= '0'; + nl11iOli <= '0'; + nl11l0li <= '0'; + nl11ll1O <= '0'; + nl11lOll <= '0'; + nl11O00i <= '0'; + nl11OilO <= '0'; + nl11OO0i <= '0'; + nl1i0OOl <= '0'; + nl1i11Oi <= '0'; + nl1iiiii <= '0'; + nl1iilOO <= '0'; + nl1il1OO <= '0'; + nl1illOl <= '0'; + nl1iOOil <= '0'; + nl1iOOll <= '0'; + nl1iOOOl <= '0'; + nl1l00il <= '0'; + nl1l0l1i <= '0'; + nl1l0O0l <= '0'; + nl1l10Ol <= '0'; + nl1l110O <= '0'; + nl1l1lii <= '0'; + nl1l1OOO <= '0'; + nl1li1OO <= '0'; + nl1liill <= '0'; + nl1liOii <= '0'; + nl1ll0lO <= '0'; + nl1llOll <= '0'; + nl1lOi0O <= '0'; + nl1O01li <= '0'; + nl1O0i1O <= '0'; + nl1O0lll <= '0'; + nl1O10li <= '0'; + nl1O1Oil <= '0'; + nl1Oi10i <= '0'; + nl1Oii1O <= '0'; + nl1Oilll <= '0'; + nl1OiOOi <= '0'; + nl1Ol00O <= '0'; + nl1OliOl <= '0'; + nl1OlOii <= '0'; + nl1OOOiO <= '0'; + nli1000l <= '0'; + nli110li <= '0'; + nli11l0O <= '0'; + nli11l1l <= '0'; + nli11lii <= '0'; + nlll0lOi <= '0'; + nllliiOl <= '0'; + nlllil0l <= '0'; + nlllil1l <= '0'; + nlllil1O <= '0'; + ELSIF (pld_clk = '1' AND pld_clk'event) THEN + niO010il <= niO010ll; + niO0111i <= niO0111O; + niO0111O <= niO0111l; + niO011il <= niO011ll; + niO01iil <= niO01ilO; + niO01lOl <= niO01O1i; + niO01O1i <= pld_srst; + niOi00Ol <= wire_niOiil0l_dataout; + niOlOiii <= wire_niOlOiOi_dataout; + niOlOlOO <= wire_niOlOO0l_dataout; + niOO01il <= wire_niOO001O_dataout; + niOO0l0i <= wire_niOO0lii_dataout; + niOO0Oi0O <= wire_niOO0OliO_dataout; + niOO0OlO <= wire_niOO0OOO_dataout; + niOO11il <= wire_niOO11Oi_dataout; + niOO1i1i <= wire_niOO1i0O_dataout; + niOO1liO <= wire_niOO1lOl_dataout; + niOOi00l <= wire_niOOi0il_dataout; + niOOi1l1l <= wire_niOOi01li_dataout; + niOOilOl <= wire_niOOl1li_dataout; + niOOllll <= wire_niOOlO1l_dataout; + niOOO0lO <= wire_niOOOi1O_dataout; + niOOO1li <= wire_niOOO1Oi_dataout; + niOOOO0l <= wire_niOOOOll_dataout; + nl00Ol0O <= wire_nl00OliO_dataout; + nl01i0li <= wire_nl01i0Oi_dataout; + nl01i11l <= wire_nl01i10l_dataout; + nl01iiOl <= nl01il1O; + nl01Ol0l <= wire_nl01Olil_dataout; + nl0OlOiO <= wire_nl0OlOlO_dataout; + nl0OOOii <= wire_nl0OOOli_dataout; + nl100Oii <= wire_nl10i10O_dataout; + nl10110O <= wire_nl1011lO_dataout; + nl101i0l <= wire_nl101iil_dataout; + nl101Oli <= wire_nl10001l_dataout; + nl10iiOl <= wire_nl10ilOi_dataout; + nl10li0O <= wire_nl10llll_dataout; + nl10O00l <= nl10O00i; + nl10O0il <= nl10O0ii; + nl10O0ll <= nl10O0li; + nl10O0Ol <= nl10O0Oi; + nl10Oi0l <= nl10Oi0i; + nl10Oi1l <= nl10Oi1i; + nl10Oiil <= nl10Oiii; + nl10Oill <= nl10Oili; + nl1100OO <= wire_nl110i0O_dataout; + nl1101ii <= wire_nl1101Oi_dataout; + nl110lil <= wire_nl110lOl_dataout; + nl1111Oi <= wire_nl11100i_dataout; + nl111i0O <= wire_nl111ilO_dataout; + nl111O0O <= wire_nl111OiO_dataout; + nl11i0iO <= wire_nl11i0OO_dataout; + nl11i11i <= wire_nl11i1ii_dataout; + nl11il1l <= wire_nl11ilil_dataout; + nl11iOli <= wire_nl11l11i_dataout; + nl11l0li <= wire_nl11l0Oi_dataout; + nl11ll1O <= wire_nl11ll0O_dataout; + nl11lOll <= wire_nl11lOOl_dataout; + nl11O00i <= wire_nl11O0ii_dataout; + nl11OilO <= wire_nl11OiOO_dataout; + nl11OO0i <= wire_nl11OOii_dataout; + nl1i0OOl <= wire_nl1ii1iO_dataout; + nl1i11Oi <= wire_nl1i1lOi_dataout; + nl1iiiii <= wire_nl1iiili_dataout; + nl1iilOO <= wire_nl1iiO1O_dataout; + nl1il1OO <= wire_nl1il01O_dataout; + nl1illOl <= wire_nl1iO1Ol_dataout; + nl1iOOil <= nl1iOOii; + nl1iOOll <= nl1iOOli; + nl1iOOOl <= nl1iOOOi; + nl1l00il <= wire_nl1l00ll_dataout; + nl1l0l1i <= wire_nl1l0l0i_dataout; + nl1l0O0l <= nl1l0O0i; + nl1l10Ol <= wire_nl1l1i1l_dataout; + nl1l110O <= wire_nl1l11iO_dataout; + nl1l1lii <= wire_nl1l1lli_dataout; + nl1l1OOO <= wire_nl1l011O_dataout; + nl1li1OO <= wire_nl1li01O_dataout; + nl1liill <= nl1liili; + nl1liOii <= wire_nl1liOli_dataout; + nl1ll0lO <= nl1ll0ll; + nl1llOll <= wire_nl1llOOl_dataout; + nl1lOi0O <= wire_nl1lOiiO_dataout; + nl1O01li <= wire_nl1O001i_dataout; + nl1O0i1O <= wire_nl1O0iiO_dataout; + nl1O0lll <= wire_nl1O0O1l_dataout; + nl1O10li <= wire_nl1O1iii_dataout; + nl1O1Oil <= wire_nl1O1Oll_dataout; + nl1Oi10i <= wire_nl1Oi1li_dataout; + nl1Oii1O <= wire_nl1Oii0O_dataout; + nl1Oilll <= wire_nl1OilOl_dataout; + nl1OiOOi <= wire_nl1Ol10i_dataout; + nl1Ol00O <= wire_nl1Ol0lO_dataout; + nl1OliOl <= wire_nl1Oll0l_dataout; + nl1OlOii <= wire_nl1OlOOi_dataout; + nl1OOOiO <= wire_nl011lii_dataout; + nli1000l <= wire_nli11OiO_dataout; + nli110li <= nli110iO; + nli11l0O <= wire_nli11Oii_dataout; + nli11l1l <= wire_nli11Oil_dataout; + nli11lii <= wire_nli11O0O_dataout; + nlll0lOi <= nlll0llO; + nllliiOl <= wire_nllll0Oi_dataout; + nlllil0l <= wire_nllll0lO_dataout; + nlllil1l <= wire_nllll0Ol_dataout; + nlllil1O <= wire_nllll0OO_dataout; + END IF; + END PROCESS; + wire_nlllil0i_CLRN <= (niOO01O1O74 XOR niOO01O1O73); + wire_nlllil0i_PRN <= (niOO01O1l76 XOR niOO01O1l75); + PROCESS (pld_clk, wire_niO01lil_dataout, wire_nlllll1O_CLRN) + BEGIN + IF (wire_niO01lil_dataout = '0') THEN + niO0100O <= '1'; + niO0110O <= '1'; + niO01i0O <= '1'; + nlllliOl <= '1'; + nlllliOO <= '1'; + nlllll0i <= '1'; + ELSIF (wire_nlllll1O_CLRN = '0') THEN + niO0100O <= '0'; + niO0110O <= '0'; + niO01i0O <= '0'; + nlllliOl <= '0'; + nlllliOO <= '0'; + nlllll0i <= '0'; + ELSIF (pld_clk = '1' AND pld_clk'event) THEN + niO0100O <= (NOT (niO010li XOR niO010iO)); + niO0110O <= (NOT (niO011li XOR niO011iO)); + niO01i0O <= (NOT (niO01ili XOR niO01iiO)); + nlllliOl <= wire_nllllOll_dataout; + nlllliOO <= wire_nllllOlO_dataout; + nlllll0i <= wire_nllllOOO_dataout; + END IF; + if (now = 0 ns) then + niO0100O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niO0110O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + niO01i0O <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlllliOl <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlllliOO <= '1' after 1 ps; + end if; + if (now = 0 ns) then + nlllll0i <= '1' after 1 ps; + end if; + END PROCESS; + wire_nlllll1O_CLRN <= (niOO0011l72 XOR niOO0011l71); + wire_n000000i_dataout <= n001il0i WHEN niOll10il = '1' ELSE wire_n00000Oi_dataout; + wire_n000000l_dataout <= wire_n00000Ol_dataout AND NOT(niOll10il); + wire_n000000O_dataout <= wire_n00000OO_dataout AND NOT(niOll10iO); + wire_n000001i_dataout <= n001il1i WHEN niOll10il = '1' ELSE wire_n00000li_dataout; + wire_n000001l_dataout <= n001il1l WHEN niOll10il = '1' ELSE wire_n00000ll_dataout; + wire_n000001O_dataout <= n001il1O WHEN niOll10il = '1' ELSE wire_n00000lO_dataout; + wire_n00000i_dataout <= wire_n00i1il_dataout AND NOT(niOO0i0ll); + wire_n00000ii_dataout <= wire_n0000i1i_dataout AND NOT(niOll10iO); + wire_n00000il_dataout <= wire_n0000i1l_dataout OR niOll10iO; + wire_n00000iO_dataout <= wire_n0000i1O_dataout OR niOll10iO; + wire_n00000l_dataout <= wire_n00i1iO_dataout AND NOT(niOO0i0ll); + wire_n00000li_dataout <= wire_n0000i0i_dataout OR niOll10iO; + wire_n00000ll_dataout <= wire_n0000i0l_dataout OR niOll10iO; + wire_n00000lO_dataout <= wire_n0000i0O_dataout AND NOT(niOll10iO); + wire_n00000O_dataout <= wire_n00i1li_dataout AND NOT(niOO0i0ll); + wire_n00000Oi_dataout <= wire_n0000iii_dataout OR niOll10iO; + wire_n00000Ol_dataout <= wire_n0000iil_dataout OR niOll10iO; + wire_n00000OO_dataout <= n001iilO AND NOT(niOll10li); + wire_n000010i_dataout <= n001i11i WHEN niOll10ii = '1' ELSE wire_n00001Oi_dataout; + wire_n000010l_dataout <= n001i11l WHEN niOll10ii = '1' ELSE wire_n00001Ol_dataout; + wire_n000010O_dataout <= n001i11O WHEN niOll10ii = '1' ELSE wire_n00001OO_dataout; + wire_n000011i_dataout <= wire_n00001li_dataout AND NOT(niOll100O); + wire_n000011l_dataout <= wire_n00001ll_dataout AND NOT(niOll100O); + wire_n000011O_dataout <= n0010l0i WHEN niOll10ii = '1' ELSE wire_n00001lO_dataout; + wire_n00001i_dataout <= wire_n00i10l_dataout AND NOT(niOO0i0ll); + wire_n00001ii_dataout <= n001i10i WHEN niOll10ii = '1' ELSE wire_n000001i_dataout; + wire_n00001il_dataout <= n001i10l WHEN niOll10ii = '1' ELSE wire_n000001l_dataout; + wire_n00001iO_dataout <= n001i10O WHEN niOll10ii = '1' ELSE wire_n000001O_dataout; + wire_n00001l_dataout <= wire_n00i10O_dataout AND NOT(niOO0i0ll); + wire_n00001li_dataout <= n01lOOiO WHEN niOll10ii = '1' ELSE wire_n000000i_dataout; + wire_n00001ll_dataout <= wire_n000000l_dataout AND NOT(niOll10ii); + wire_n00001lO_dataout <= n001iilO WHEN niOll10il = '1' ELSE wire_n000000O_dataout; + wire_n00001O_dataout <= wire_n00i1ii_dataout AND NOT(niOO0i0ll); + wire_n00001Oi_dataout <= n001iiOi WHEN niOll10il = '1' ELSE wire_n00000ii_dataout; + wire_n00001Ol_dataout <= n001iiOl WHEN niOll10il = '1' ELSE wire_n00000il_dataout; + wire_n00001OO_dataout <= n001iiOO WHEN niOll10il = '1' ELSE wire_n00000iO_dataout; + wire_n0000i0i_dataout <= n001il1i OR niOll10li; + wire_n0000i0l_dataout <= n001il1l OR niOll10li; + wire_n0000i0O_dataout <= n001il1O OR niOll10li; + wire_n0000i1i_dataout <= n001iiOi AND NOT(niOll10li); + wire_n0000i1l_dataout <= n001iiOl OR niOll10li; + wire_n0000i1O_dataout <= n001iiOO OR niOll10li; + wire_n0000ii_dataout <= wire_n00i1ll_dataout AND NOT(niOO0i0ll); + wire_n0000iii_dataout <= n001il0i OR niOll10li; + wire_n0000iil_dataout <= n001il0l OR niOll10li; + wire_n0000il_dataout <= wire_n00i1lO_dataout AND NOT(niOO0i0ll); + wire_n0000iO_dataout <= wire_n00i1Oi_dataout AND NOT(niOO0i0ll); + wire_n0000l0O_dataout <= wire_n0000llO_dataout AND NOT(niOll1iii); + wire_n0000li_dataout <= wire_n00i1Ol_dataout AND NOT(niOO0i0ll); + wire_n0000lii_dataout <= wire_n0000lOi_dataout AND NOT(niOll1iii); + wire_n0000lil_dataout <= wire_n0000lOl_dataout AND NOT(niOll1iii); + wire_n0000liO_dataout <= wire_n0000lOO_dataout AND NOT(niOll1iii); + wire_n0000ll_dataout <= wire_n00i1OO_dataout AND NOT(niOO0i0ll); + wire_n0000lli_dataout <= wire_n0000O1i_dataout AND NOT(niOll1iii); + wire_n0000lll_dataout <= wire_n0000O1l_dataout AND NOT(niOll1iii); + wire_n0000llO_dataout <= wire_n0000O1O_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001ilOl; + wire_n0000lO_dataout <= wire_n00i01i_dataout AND NOT(niOO0i0ll); + wire_n0000lOi_dataout <= wire_n0000O0i_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001ilOO; + wire_n0000lOl_dataout <= wire_n0000O0l_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001iO1i; + wire_n0000lOO_dataout <= wire_n0000O0O_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001iO1l; + wire_n0000O0i_dataout <= wire_n0000OiO_o(1) WHEN niOll1i0O = '1' ELSE n001ilOO; + wire_n0000O0l_dataout <= wire_n0000OiO_o(2) WHEN niOll1i0O = '1' ELSE n001iO1i; + wire_n0000O0O_dataout <= wire_n0000OiO_o(3) WHEN niOll1i0O = '1' ELSE n001iO1l; + wire_n0000O1i_dataout <= wire_n0000Oii_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001iO1O; + wire_n0000O1l_dataout <= wire_n0000Oil_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001iO0i; + wire_n0000O1O_dataout <= wire_n0000OiO_o(0) WHEN niOll1i0O = '1' ELSE n001ilOl; + wire_n0000Oi_dataout <= wire_n00i01l_dataout AND NOT(niOO0i0ll); + wire_n0000Oii_dataout <= wire_n0000OiO_o(4) WHEN niOll1i0O = '1' ELSE n001iO1O; + wire_n0000Oil_dataout <= wire_n0000OiO_o(5) WHEN niOll1i0O = '1' ELSE n001iO0i; + wire_n0000Ol_dataout <= wire_n00i01O_dataout AND NOT(niOO0i0ll); + wire_n0000OO_dataout <= wire_n00i00i_dataout AND NOT(niOO0i0ll); + wire_n0000OOl_dataout <= wire_n0000OOO_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16093w(0) AND wire_w_lg_niOll1ili16094w(0)); + wire_n0000OOO_dataout <= n001iO0l AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOll1ill16102w(0))); + wire_n000100i_dataout <= n001iiOO WHEN niOll11Oi = '1' ELSE wire_n01l1Oll_dataout; + wire_n000100l_dataout <= n001il1i WHEN niOll11Oi = '1' ELSE wire_n01l1OiO_dataout; + wire_n000100O_dataout <= n001il1l WHEN niOll11Oi = '1' ELSE wire_n01l1O0O_dataout; + wire_n000101i_dataout <= n001iilO WHEN niOll11Oi = '1' ELSE wire_n01l011l_dataout; + wire_n000101l_dataout <= n001iiOi WHEN niOll11Oi = '1' ELSE wire_n01l1OOO_dataout; + wire_n000101O_dataout <= n001iiOl WHEN niOll11Oi = '1' ELSE wire_n01l1OOi_dataout; + wire_n00010i_dataout <= n0Ol10i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n00010ii_dataout <= n001il1O WHEN niOll11Oi = '1' ELSE wire_n01l1O0i_dataout; + wire_n00010il_dataout <= n001il0i WHEN niOll11Oi = '1' ELSE wire_n01l1O1i_dataout; + wire_n00010iO_dataout <= n000i1ll AND NOT(niOll11Oi); + wire_n00010l_dataout <= wire_w_lg_w_k_hip_range2413w3432w(0) WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_n00010O_dataout; + wire_n00010O_dataout <= (n0Oiiil OR niOO0iilO) WHEN (n0Oiiii AND wire_w_lg_niOO0iiOi3378w(0)) = '1' ELSE niOO0iilO; + wire_n000110i_dataout <= wire_n00011Oi_dataout AND NOT(niOll11Ol); + wire_n000110l_dataout <= wire_n00011Ol_dataout AND NOT(niOll11Ol); + wire_n000110O_dataout <= wire_n00011OO_dataout AND NOT(niOll11Ol); + wire_n000111i_dataout <= wire_n00011li_dataout AND NOT(niOll11Ol); + wire_n000111l_dataout <= wire_n00011ll_dataout AND NOT(niOll11Ol); + wire_n000111O_dataout <= wire_n00011lO_dataout AND NOT(niOll11Ol); + wire_n00011ii_dataout <= n0010l0i WHEN niOll11lO = '1' ELSE wire_n000101i_dataout; + wire_n00011il_dataout <= n001i11i WHEN niOll11lO = '1' ELSE wire_n000101l_dataout; + wire_n00011iO_dataout <= n001i11l WHEN niOll11lO = '1' ELSE wire_n000101O_dataout; + wire_n00011li_dataout <= n001i11O WHEN niOll11lO = '1' ELSE wire_n000100i_dataout; + wire_n00011ll_dataout <= n001i10i WHEN niOll11lO = '1' ELSE wire_n000100l_dataout; + wire_n00011lO_dataout <= n001i10l WHEN niOll11lO = '1' ELSE wire_n000100O_dataout; + wire_n00011Oi_dataout <= n001i10O WHEN niOll11lO = '1' ELSE wire_n00010ii_dataout; + wire_n00011Ol_dataout <= n01lOOiO WHEN niOll11lO = '1' ELSE wire_n00010il_dataout; + wire_n00011OO_dataout <= wire_n00010iO_dataout AND NOT(niOll11lO); + wire_n0001i0i_dataout <= wire_n0001iOi_dataout AND NOT(niOll101l); + wire_n0001i0l_dataout <= wire_n0001iOl_dataout OR niOll101l; + wire_n0001i0O_dataout <= wire_n0001iOO_dataout OR niOll101l; + wire_n0001i1O_dataout <= wire_n0001ilO_dataout AND NOT(niOll101l); + wire_n0001iii_dataout <= wire_n0001l1i_dataout OR niOll101l; + wire_n0001iil_dataout <= wire_n0001l1l_dataout OR niOll101l; + wire_n0001iiO_dataout <= wire_n0001l1O_dataout AND NOT(niOll101l); + wire_n0001ili_dataout <= wire_n0001l0i_dataout OR niOll101l; + wire_n0001ill_dataout <= wire_n0001l0l_dataout OR niOll101l; + wire_n0001ilO_dataout <= wire_n0001l0O_dataout AND NOT(niOll101O); + wire_n0001iO_dataout <= n0Ol10l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0Oiili; + wire_n0001iOi_dataout <= wire_n0001lii_dataout AND NOT(niOll101O); + wire_n0001iOl_dataout <= wire_n0001lil_dataout OR niOll101O; + wire_n0001iOO_dataout <= wire_n0001liO_dataout OR niOll101O; + wire_n0001l0i_dataout <= wire_n0001lOi_dataout OR niOll101O; + wire_n0001l0l_dataout <= wire_n0001lOl_dataout OR niOll101O; + wire_n0001l0O_dataout <= wire_n0001lOO_dataout OR niOll100i; + wire_n0001l1i_dataout <= wire_n0001lli_dataout OR niOll101O; + wire_n0001l1l_dataout <= wire_n0001lll_dataout OR niOll101O; + wire_n0001l1O_dataout <= wire_n0001llO_dataout AND NOT(niOll101O); + wire_n0001li_dataout <= n0OiiiO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0001lii_dataout <= wire_n0001O1i_dataout AND NOT(niOll100i); + wire_n0001lil_dataout <= wire_n0001O1l_dataout OR niOll100i; + wire_n0001liO_dataout <= wire_n0001O1O_dataout AND NOT(niOll100i); + wire_n0001ll_dataout <= wire_n000OOO_dataout AND NOT(niOO0i0ll); + wire_n0001lli_dataout <= wire_n0001O0i_dataout OR niOll100i; + wire_n0001lll_dataout <= wire_n0001O0l_dataout OR niOll100i; + wire_n0001llO_dataout <= wire_n0001O0O_dataout AND NOT(niOll100i); + wire_n0001lO_dataout <= wire_n00i11i_dataout AND NOT(niOO0i0ll); + wire_n0001lOi_dataout <= wire_n0001Oii_dataout OR niOll100i; + wire_n0001lOl_dataout <= wire_n0001Oil_dataout AND NOT(niOll100i); + wire_n0001lOO_dataout <= wire_n0001OiO_dataout AND NOT(niOll100l); + wire_n0001O0i_dataout <= wire_n0001OOi_dataout OR niOll100l; + wire_n0001O0l_dataout <= wire_n0001OOl_dataout OR niOll100l; + wire_n0001O0O_dataout <= wire_n0001OOO_dataout AND NOT(niOll100l); + wire_n0001O1i_dataout <= wire_n0001Oli_dataout AND NOT(niOll100l); + wire_n0001O1l_dataout <= wire_n0001Oll_dataout OR niOll100l; + wire_n0001O1O_dataout <= wire_n0001OlO_dataout OR niOll100l; + wire_n0001Oi_dataout <= wire_n00i11l_dataout AND NOT(niOO0i0ll); + wire_n0001Oii_dataout <= wire_n000011i_dataout OR niOll100l; + wire_n0001Oil_dataout <= wire_n000011l_dataout OR niOll100l; + wire_n0001OiO_dataout <= wire_n000011O_dataout AND NOT(niOll100O); + wire_n0001Ol_dataout <= wire_n00i11O_dataout AND NOT(niOO0i0ll); + wire_n0001Oli_dataout <= wire_n000010i_dataout OR niOll100O; + wire_n0001Oll_dataout <= wire_n000010l_dataout AND NOT(niOll100O); + wire_n0001OlO_dataout <= wire_n000010O_dataout OR niOll100O; + wire_n0001OO_dataout <= wire_n00i10i_dataout AND NOT(niOO0i0ll); + wire_n0001OOi_dataout <= wire_n00001ii_dataout AND NOT(niOll100O); + wire_n0001OOl_dataout <= wire_n00001il_dataout AND NOT(niOll100O); + wire_n0001OOO_dataout <= wire_n00001iO_dataout OR niOll100O; + wire_n000i00l_dataout <= wire_n000iiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000i00O_dataout <= wire_n000iiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000i0i_dataout <= wire_n00i0il_dataout AND NOT(niOO0i0ll); + wire_n000i0ii_dataout <= wire_n000il1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000i0il_dataout <= wire_n000iiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000i0iO_dataout <= n000i1il AND NOT(wire_niO01lOO_dataout); + wire_n000i0l_dataout <= wire_n00i0iO_dataout AND NOT(niOO0i0ll); + wire_n000i0li_dataout <= nlOllOlli AND NOT(wire_niO01lOO_dataout); + wire_n000i0ll_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16098w(0) AND wire_w_lg_niOll1iil16099w(0)) AND wire_niO01ill_w_lg_n000i10O16096w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n000i0lO_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16093w(0) AND wire_w_lg_niOll1ili16094w(0)) AND wire_niO01ill_w_lg_n000i10O16096w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n000i0O_dataout <= wire_n00i0li_dataout AND NOT(niOO0i0ll); + wire_n000i0Oi_dataout <= wire_n000il1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000i0Ol_dataout <= wire_n000il0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000i0OO_dataout <= wire_n000il0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000i1i_dataout <= wire_n00i00l_dataout AND NOT(niOO0i0ll); + wire_n000i1l_dataout <= wire_n00i00O_dataout AND NOT(niOO0i0ll); + wire_n000i1O_dataout <= wire_n00i0ii_dataout AND NOT(niOO0i0ll); + wire_n000ii0i_dataout <= wire_n000illi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000ii0l_dataout <= wire_n000illl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000ii0O_dataout <= wire_n000illO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000ii1i_dataout <= wire_n000ilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000ii1l_dataout <= wire_n000ilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000ii1O_dataout <= wire_n000iliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000iii_dataout <= wire_n00i0ll_dataout AND NOT(niOO0i0ll); + wire_n000iil_dataout <= wire_n00i0lO_dataout AND NOT(niOO0i0ll); + wire_n000iiO_dataout <= wire_n00i0Oi_dataout AND NOT(niOO0i0ll); + wire_n000iiOi_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n000i10O; + wire_n000iiOl_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n001ll1O; + wire_n000iiOO_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n000i10i; + wire_n000il0i_dataout <= n1l001OO AND NOT(niOll1ilO); + wire_n000il0l_dataout <= wire_n1llOlli_dataout WHEN n1lO0lOi = '1' ELSE wire_n000ilOi_dataout; + wire_n000il0O_dataout <= wire_n1llOlll_dataout WHEN n1lO0lOi = '1' ELSE wire_n000ilOl_dataout; + wire_n000il1i_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n000i10l; + wire_n000il1l_dataout <= wire_n1lllOli_dataout WHEN n1lO0lOi = '1' ELSE wire_n000il1O_dataout; + wire_n000il1O_dataout <= wire_n000il0i_dataout AND NOT(niOll1iOi); + wire_n000ili_dataout <= wire_n00i0Ol_dataout AND NOT(niOO0i0ll); + wire_n000ilii_dataout <= wire_n1llOllO_dataout WHEN n1lO0lOi = '1' ELSE wire_n000ilOO_dataout; + wire_n000ilil_dataout <= wire_n1llOlOi_dataout WHEN n1lO0lOi = '1' ELSE wire_n000iO1i_dataout; + wire_n000iliO_dataout <= wire_n1llOlOl_dataout WHEN n1lO0lOi = '1' ELSE wire_n000iO1l_dataout; + wire_n000ill_dataout <= wire_n00i0OO_dataout AND NOT(niOO0i0ll); + wire_n000illi_dataout <= wire_n1llOlOO_dataout WHEN n1lO0lOi = '1' ELSE wire_n000iO1O_dataout; + wire_n000illl_dataout <= wire_n1llOO1i_dataout WHEN n1lO0lOi = '1' ELSE wire_n000iO0i_dataout; + wire_n000illO_dataout <= wire_n1llOO1l_dataout WHEN n1lO0lOi = '1' ELSE wire_n000iO0l_dataout; + wire_n000ilO_dataout <= wire_n00ii1i_dataout AND NOT(niOO0i0ll); + wire_n000ilOi_dataout <= wire_nlOO10OOi_dataout WHEN niOll1iOi = '1' ELSE wire_n000iO0O_dataout; + wire_n000ilOl_dataout <= wire_nlOO10OOl_dataout WHEN niOll1iOi = '1' ELSE wire_n000iOii_dataout; + wire_n000ilOO_dataout <= wire_nlOO10OOO_dataout WHEN niOll1iOi = '1' ELSE wire_n000iOil_dataout; + wire_n000iO0i_dataout <= wire_nlOO1i10i_dataout WHEN niOll1iOi = '1' ELSE wire_n000iOlO_dataout; + wire_n000iO0l_dataout <= wire_nlOO1i10l_dataout WHEN niOll1iOi = '1' ELSE wire_n000iOOi_dataout; + wire_n000iO0O_dataout <= wire_niili01i_dataout WHEN niOll1ilO = '1' ELSE n1l001ii; + wire_n000iO1i_dataout <= wire_nlOO1i11i_dataout WHEN niOll1iOi = '1' ELSE wire_n000iOiO_dataout; + wire_n000iO1l_dataout <= wire_nlOO1i11l_dataout WHEN niOll1iOi = '1' ELSE wire_n000iOli_dataout; + wire_n000iO1O_dataout <= wire_nlOO1i11O_dataout WHEN niOll1iOi = '1' ELSE wire_n000iOll_dataout; + wire_n000iOi_dataout <= wire_n00ii1l_dataout AND NOT(niOO0i0ll); + wire_n000iOii_dataout <= wire_niili01l_dataout WHEN niOll1ilO = '1' ELSE n1l001il; + wire_n000iOil_dataout <= n1101l1i WHEN niOll1ilO = '1' ELSE n1l001iO; + wire_n000iOiO_dataout <= n1l001li AND NOT(niOll1ilO); + wire_n000iOl_dataout <= wire_n00ii1O_dataout AND NOT(niOO0i0ll); + wire_n000iOli_dataout <= n1l001ll AND NOT(niOll1ilO); + wire_n000iOll_dataout <= n1l001lO AND NOT(niOll1ilO); + wire_n000iOlO_dataout <= n1l001Oi AND NOT(niOll1ilO); + wire_n000iOO_dataout <= wire_n00ii0i_dataout AND NOT(niOO0i0ll); + wire_n000iOOi_dataout <= n1l001Ol AND NOT(niOll1ilO); + wire_n000l0i_dataout <= wire_n00iiil_dataout AND NOT(niOO0i0ll); + wire_n000l0l_dataout <= wire_n00iiiO_dataout AND NOT(niOO0i0ll); + wire_n000l0O_dataout <= wire_n00iili_dataout AND NOT(niOO0i0ll); + wire_n000l10i_dataout <= k_cnt(60) AND NOT(wire_n000l1ii_o); + wire_n000l10l_dataout <= k_cnt(61) AND NOT(wire_n000l1ii_o); + wire_n000l10O_dataout <= k_cnt(62) AND NOT(wire_n000l1ii_o); + wire_n000l11i_dataout <= k_cnt(57) AND NOT(wire_n000l1ii_o); + wire_n000l11l_dataout <= k_cnt(58) AND NOT(wire_n000l1ii_o); + wire_n000l11O_dataout <= k_cnt(59) OR wire_n000l1ii_o; + wire_n000l1i_dataout <= wire_n00ii0l_dataout AND NOT(niOO0i0ll); + wire_n000l1l_dataout <= wire_n00ii0O_dataout AND NOT(niOO0i0ll); + wire_n000l1O_dataout <= wire_n00iiii_dataout AND NOT(niOO0i0ll); + wire_n000li0l_dataout <= n00OOOil WHEN niOll1iOl = '1' ELSE (n00OOOil XOR n000llOO); + wire_n000lii_dataout <= wire_n00iill_dataout AND NOT(niOO0i0ll); + wire_n000liil_dataout <= n00OOOii WHEN niOll1iOl = '1' ELSE (n00OOOii XOR n000lO1i); + wire_n000lil_dataout <= wire_n00iilO_dataout AND NOT(niOO0i0ll); + wire_n000lili_dataout <= n00OOO0O WHEN niOll1iOl = '1' ELSE (n00OOO0O XOR n000lO1l); + wire_n000liO_dataout <= wire_n00iiOi_dataout AND NOT(niOO0i0ll); + wire_n000liOi_dataout <= n00OOO0l WHEN niOll1iOl = '1' ELSE (n00OOO0l XOR n000lO1O); + wire_n000liOO_dataout <= n00OOO0i WHEN niOll1iOl = '1' ELSE (n00OOO0i XOR n000lO0i); + wire_n000ll0i_dataout <= n00OOO1l WHEN niOll1iOl = '1' ELSE (n00OOO1l XOR n000lO0O); + wire_n000ll0O_dataout <= n00OOO1i WHEN niOll1iOl = '1' ELSE (n00OOO1i XOR n000lOii); + wire_n000ll1l_dataout <= n00OOO1O WHEN niOll1iOl = '1' ELSE (n00OOO1O XOR n000lO0l); + wire_n000lli_dataout <= wire_n00iiOl_dataout AND NOT(niOO0i0ll); + wire_n000lll_dataout <= wire_n00iiOO_dataout AND NOT(niOO0i0ll); + wire_n000llO_dataout <= wire_n00il1i_dataout AND NOT(niOO0i0ll); + wire_n000lOi_dataout <= wire_n00il1l_dataout AND NOT(niOO0i0ll); + wire_n000lOiO_dataout <= wire_n000O1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000lOl_dataout <= wire_n00il1O_dataout AND NOT(niOO0i0ll); + wire_n000lOli_dataout <= wire_n000O1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000lOll_dataout <= wire_n000O1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000lOlO_dataout <= wire_n000O1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000lOO_dataout <= wire_n00il0i_dataout AND NOT(niOO0i0ll); + wire_n000lOOi_dataout <= wire_n000O1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000lOOl_dataout <= wire_n000O1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000lOOO_dataout <= wire_n000O01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O00i_dataout <= wire_n000Oi0l_dataout OR niOll1l1i; + wire_n000O00l_dataout <= wire_n000Oi0O_dataout OR niOll1l1i; + wire_n000O00O_dataout <= wire_n000Oiii_dataout OR niOll1l1i; + wire_n000O01i_dataout <= wire_n000Oi1l_dataout OR niOll1l1i; + wire_n000O01l_dataout <= wire_n000Oi1O_dataout OR niOll1l1i; + wire_n000O01O_dataout <= wire_n000Oi0i_dataout OR niOll1l1i; + wire_n000O0i_dataout <= wire_n00ilil_dataout AND NOT(niOO0i0ll); + wire_n000O0ii_dataout <= wire_n000Oiil_dataout OR niOll1l1i; + wire_n000O0il_dataout <= wire_n000OiiO_dataout OR niOll1l1i; + wire_n000O0iO_dataout <= wire_n000Oili_dataout OR niOll1l1i; + wire_n000O0l_dataout <= wire_n00iliO_dataout AND NOT(niOO0i0ll); + wire_n000O0li_dataout <= wire_n000Oill_dataout OR niOll1l1i; + wire_n000O0ll_dataout <= n000lilO WHEN niOll1iOO = '1' ELSE n000llOO; + wire_n000O0lO_dataout <= n000llil WHEN niOll1iOO = '1' ELSE n000lO1i; + wire_n000O0O_dataout <= wire_n00illi_dataout AND NOT(niOO0i0ll); + wire_n000O0Oi_dataout <= n000lliO WHEN niOll1iOO = '1' ELSE n000lO1l; + wire_n000O0Ol_dataout <= n000llli WHEN niOll1iOO = '1' ELSE (n000lO1O XOR n000llOO); + wire_n000O0OO_dataout <= n000llll WHEN niOll1iOO = '1' ELSE (n000llOO XOR (n000lO0i XOR n000lO1i)); + wire_n000O10i_dataout <= wire_n000O00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O10l_dataout <= wire_n000O00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O10O_dataout <= wire_n000O0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O11i_dataout <= wire_n000O01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O11l_dataout <= wire_n000O01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O11O_dataout <= wire_n000O00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O1i_dataout <= wire_n00il0l_dataout AND NOT(niOO0i0ll); + wire_n000O1ii_dataout <= wire_n000O0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O1il_dataout <= wire_n000O0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O1iO_dataout <= wire_n000O0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000O1l_dataout <= wire_n00il0O_dataout AND NOT(niOO0i0ll); + wire_n000O1li_dataout <= wire_n000O0ll_dataout OR niOll1l1i; + wire_n000O1ll_dataout <= wire_n000O0lO_dataout OR niOll1l1i; + wire_n000O1lO_dataout <= wire_n000O0Oi_dataout OR niOll1l1i; + wire_n000O1O_dataout <= wire_n00ilii_dataout AND NOT(niOO0i0ll); + wire_n000O1Oi_dataout <= wire_n000O0Ol_dataout OR niOll1l1i; + wire_n000O1Ol_dataout <= wire_n000O0OO_dataout OR niOll1l1i; + wire_n000O1OO_dataout <= wire_n000Oi1i_dataout OR niOll1l1i; + wire_n000Oi0i_dataout <= n000llOO WHEN niOll1iOO = '1' ELSE (n000lO1O XOR (n000lO0i XOR (n000lO0l XOR n000lilO))); + wire_n000Oi0l_dataout <= n000lO1i WHEN niOll1iOO = '1' ELSE (n000lO0i XOR (n000lO0l XOR (n000lO0O XOR n000llil))); + wire_n000Oi0O_dataout <= n000lO1l WHEN niOll1iOO = '1' ELSE (n000lO0l XOR (n000lO0O XOR (n000lOii XOR n000lliO))); + wire_n000Oi1i_dataout <= n000lllO WHEN niOll1iOO = '1' ELSE (n000llOO XOR (n000lO1i XOR (n000lO0l XOR n000lO1l))); + wire_n000Oi1l_dataout <= n000llOi WHEN niOll1iOO = '1' ELSE (n000lO1i XOR (n000lO1l XOR (n000lO0O XOR n000lO1O))); + wire_n000Oi1O_dataout <= n000llOl WHEN niOll1iOO = '1' ELSE (n000lO1l XOR (n000lO1O XOR (n000lOii XOR n000lO0i))); + wire_n000Oii_dataout <= wire_n00illl_dataout AND NOT(niOO0i0ll); + wire_n000Oiii_dataout <= n000lO1O WHEN niOll1iOO = '1' ELSE (n000lO0O XOR (n000lOii XOR n000llli)); + wire_n000Oiil_dataout <= n000lO0i WHEN niOll1iOO = '1' ELSE (n000lOii XOR n000llll); + wire_n000OiiO_dataout <= n000lO0l WHEN niOll1iOO = '1' ELSE n000lllO; + wire_n000Oil_dataout <= wire_n00illO_dataout AND NOT(niOO0i0ll); + wire_n000Oili_dataout <= n000lO0O WHEN niOll1iOO = '1' ELSE n000llOi; + wire_n000Oill_dataout <= n000lOii WHEN niOll1iOO = '1' ELSE n000llOl; + wire_n000OiO_dataout <= wire_n00ilOi_dataout AND NOT(niOO0i0ll); + wire_n000OiOi_dataout <= wire_n000OiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n000OiOl_dataout <= wire_n000OiOO_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n000lOil) AND niOll1l1i)); + wire_n000OiOO_dataout <= n000lOil OR n111i10i; + wire_n000Oli_dataout <= wire_n00ilOl_dataout AND NOT(niOO0i0ll); + wire_n000Oll_dataout <= wire_n00ilOO_dataout AND NOT(niOO0i0ll); + wire_n000OlO_dataout <= wire_n00iO1i_dataout AND NOT(niOO0i0ll); + wire_n000OOi_dataout <= wire_n00iO1l_dataout AND NOT(niOO0i0ll); + wire_n000OOl_dataout <= wire_n00iO1O_dataout AND NOT(niOO0i0ll); + wire_n000OOO_dataout <= wire_n00iO0i_dataout AND NOT(niOO0i0li); + wire_n000OOOl_dataout <= wire_niO100ll_dataout WHEN niOll1l1l = '1' ELSE (wire_niO100ll_dataout XOR n00i10iO); + wire_n000OOOl_w_lg_dataout15828w(0) <= NOT wire_n000OOOl_dataout; + wire_n00100i_dataout <= wire_n1llO0O_q(129) AND wire_n1O0lli_dataout; + wire_n00100l_dataout <= wire_n00100O_dataout WHEN wire_n1O0lli_dataout = '1' ELSE n1O0l0O; + wire_n00100ll_dataout <= wire_n00100OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00100lO_dataout <= wire_n0010i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00100O_dataout <= wire_n0010ii_dataout AND NOT(niOO0i01i); + wire_n00100Oi_dataout <= wire_n0010i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00100Ol_dataout <= wire_n0010i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00100OO_dataout <= wire_n0010i0i_dataout AND NOT(niOliOOii); + wire_n00101i_dataout <= wire_n1llO0O_q(130) AND wire_n1O0lli_dataout; + wire_n00101l_dataout <= wire_n1llO0O_q(131) AND wire_n1O0lli_dataout; + wire_n00101O_dataout <= wire_n1llO0O_q(128) AND wire_n1O0lli_dataout; + wire_n0010i0i_dataout <= wire_n0010iil_o(0) WHEN wire_niO01ill_w_lg_n00100iO16371w(0) = '1' ELSE n01OO0iO; + wire_n0010i0l_dataout <= wire_n0010iil_o(1) WHEN wire_niO01ill_w_lg_n00100iO16371w(0) = '1' ELSE n00100ii; + wire_n0010i0O_dataout <= wire_n0010iil_o(2) WHEN wire_niO01ill_w_lg_n00100iO16371w(0) = '1' ELSE n00100il; + wire_n0010i1i_dataout <= wire_n0010i0l_dataout AND NOT(niOliOOii); + wire_n0010i1l_dataout <= wire_n0010i0O_dataout AND NOT(niOliOOii); + wire_n0010i1O_dataout <= wire_n0010iii_dataout AND NOT(niOliOOii); + wire_n0010ii_dataout <= wire_n0010il_dataout OR NOT(((NOT wire_n1llO0O_q(128)) AND (NOT wire_n1llO0O_q(129)))); + wire_n0010iii_dataout <= wire_n0010iil_o(3) OR NOT(wire_niO01ill_w_lg_n00100iO16371w(0)); + wire_n0010il_dataout <= n1O0l0O AND niOO0i01l; + wire_n0010iO_dataout <= n0OiOOO AND NOT(wire_w_lg_w_k_hip_range2413w2429w(0)); + wire_n0010l0l_dataout <= (niOll110l AND n0010ill) AND NOT(wire_niO01lOO_dataout); + wire_n0010l0O_dataout <= (niOll110l AND n0010ilO) AND NOT(wire_niO01lOO_dataout); + wire_n0010li_dataout <= n0il0lO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n0010lii_dataout <= (wire_w_lg_w_lg_w_lg_niOll111O16342w16343w16344w(0) OR (wire_w_lg_niOll110l16345w(0) AND (wire_w_lg_niOll111O16346w(0) AND (n0010iOO AND niOliOOiO)))) AND NOT(wire_niO01lOO_dataout); + wire_n0010lil_dataout <= niOliOOlO AND NOT(wire_niO01lOO_dataout); + wire_n0010liO_dataout <= (niOll111O AND n0010l1O) AND NOT(wire_niO01lOO_dataout); + wire_n0010ll_dataout <= n0il0Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n0010lli_dataout <= n0010iOO AND NOT(wire_niO01lOO_dataout); + wire_n0010lll_dataout <= niOll111O AND NOT(wire_niO01lOO_dataout); + wire_n0010llO_dataout <= n0010l1l AND NOT(wire_niO01lOO_dataout); + wire_n0010lO_dataout <= n0il0Ol AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n0010lOi_dataout <= n0010l1O AND NOT(wire_niO01lOO_dataout); + wire_n0010lOl_dataout <= niOll110l AND NOT(wire_niO01lOO_dataout); + wire_n0010Oi_dataout <= n0il0OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n0010Ol_dataout <= n0ili1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n0010OO_dataout <= n0ili1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n00110i_dataout <= wire_n1llO0O_q(116) WHEN wire_n1O0lli_dataout = '1' ELSE n1OliOl; + wire_n00110l_dataout <= wire_n1llO0O_q(117) WHEN wire_n1O0lli_dataout = '1' ELSE n1OliOO; + wire_n00110li_dataout <= niOliOlOO WHEN wire_n00110Oi_o = '1' ELSE n01OlO1l; + wire_n00110ll_dataout <= niOliOO1O WHEN wire_n00110Oi_o = '1' ELSE n01OlO1O; + wire_n00110lO_dataout <= (wire_niO10i1l_dataout AND (niOliOO1l OR niOliOO0l)) WHEN wire_n00110Oi_o = '1' ELSE n01OlO0i; + wire_n00110O_dataout <= wire_n1llO0O_q(118) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oll1i; + wire_n00110Ol_dataout <= wire_niO10iil_dataout WHEN niOliOlil = '1' ELSE n01OlllO; + wire_n00110OO_dataout <= wire_niO10i0i_dataout WHEN niOliOlil = '1' ELSE n01OlO0l; + wire_n001110O_dataout <= wire_n00111ii_dataout AND NOT(niOliOO0O); + wire_n00111i_dataout <= wire_n1llO0O_q(113) WHEN wire_n1O0lli_dataout = '1' ELSE n1Olill; + wire_n00111ii_dataout <= wire_n00111il_dataout OR (wire_w_lg_niOliOOOl16464w(0) AND wire_w_lg_w_lg_niOliOOOi16453w16465w(0)); + wire_n00111il_dataout <= wire_n00111iO_dataout OR (wire_w_lg_niOliOOOi16453w(0) AND (wire_w_lg_w_lg_niOliOlli16455w16456w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n01OO0il16458w16460w16461w(0))); + wire_n00111iO_dataout <= wire_n00111li_dataout OR (wire_w_lg_niOliOOOi16453w(0) AND niOliOliO); + wire_n00111l_dataout <= wire_n1llO0O_q(114) WHEN wire_n1O0lli_dataout = '1' ELSE n1OlilO; + wire_n00111li_dataout <= n01OlO1i OR (wire_n001101l_o AND (((niOliOO1O XOR n01OlO1O) OR (niOliOlOO XOR n01OlO1l)) OR (NOT (n01OlO1O XOR n01OlO1l)))); + wire_n00111O_dataout <= wire_n1llO0O_q(115) WHEN wire_n1O0lli_dataout = '1' ELSE n1OliOi; + wire_n0011i0i_dataout <= wire_niO10ill_dataout WHEN niOliOliO = '1' ELSE n01OllOi; + wire_n0011i0l_dataout <= wire_niO10ili_dataout WHEN niOliOliO = '1' ELSE n01O0ilO; + wire_n0011i0O_dataout <= wire_niO10i0l_dataout WHEN niOliOliO = '1' ELSE n01OO11l; + wire_n0011i1i_dataout <= wire_niO10i0l_dataout WHEN niOliOlil = '1' ELSE n01OlO0O; + wire_n0011i1l_dataout <= wire_niO10i0O_dataout WHEN niOliOlil = '1' ELSE n01OlOii; + wire_n0011i1O_dataout <= wire_niO10iii_dataout WHEN niOliOlil = '1' ELSE n01OlOil; + wire_n0011ii_dataout <= wire_n1llO0O_q(119) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oll1l; + wire_n0011iii_dataout <= wire_niO10i0O_dataout WHEN niOliOliO = '1' ELSE n01OO11O; + wire_n0011iil_dataout <= n01OO10i AND NOT(niOliOliO); + wire_n0011iiO_dataout <= wire_niO10i0i_dataout WHEN niOliOlli = '1' ELSE n01OlOiO; + wire_n0011il_dataout <= wire_n1llO0O_q(120) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oll1O; + wire_n0011ili_dataout <= wire_niO10i0l_dataout WHEN niOliOlli = '1' ELSE n01OlOli; + wire_n0011ill_dataout <= wire_niO10i0O_dataout WHEN niOliOlli = '1' ELSE n01OlOll; + wire_n0011ilO_dataout <= wire_niO10iii_dataout WHEN niOliOlli = '1' ELSE n01OlOlO; + wire_n0011iO_dataout <= wire_n1llO0O_q(121) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oll0i; + wire_n0011iOi_dataout <= wire_niO10iil_dataout WHEN niOliOlli = '1' ELSE n01OlOOi; + wire_n0011iOl_dataout <= wire_niO10iiO_dataout WHEN niOliOlli = '1' ELSE n01OlOOl; + wire_n0011iOO_dataout <= wire_niO10ili_dataout WHEN niOliOlli = '1' ELSE n01OlOOO; + wire_n0011l0i_dataout <= wire_niO10i0O_dataout WHEN niOliOlOi = '1' ELSE n01OO1ii; + wire_n0011l0l_dataout <= wire_niO10iii_dataout WHEN niOliOlOi = '1' ELSE n01OO1il; + wire_n0011l0O_dataout <= wire_niO10iil_dataout WHEN niOliOlOi = '1' ELSE n01OO1iO; + wire_n0011l1i_dataout <= wire_niO10ill_dataout WHEN niOliOlli = '1' ELSE n01OO11i; + wire_n0011l1l_dataout <= wire_niO10i0i_dataout WHEN niOliOlOi = '1' ELSE n01OO10l; + wire_n0011l1O_dataout <= wire_niO10i0l_dataout WHEN niOliOlOi = '1' ELSE n01OO10O; + wire_n0011li_dataout <= wire_n1llO0O_q(122) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oll0l; + wire_n0011lii_dataout <= niOliOOOl WHEN niOliOlOi = '1' ELSE n01OO1li; + wire_n0011lil_dataout <= wire_niO10i0i_dataout WHEN niOliOO0O = '1' ELSE n01OO1ll; + wire_n0011liO_dataout <= wire_niO10i0l_dataout WHEN niOliOO0O = '1' ELSE n01OO1lO; + wire_n0011ll_dataout <= wire_n1llO0O_q(123) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oll0O; + wire_n0011lli_dataout <= wire_niO10i0O_dataout WHEN niOliOO0O = '1' ELSE n01OO1Oi; + wire_n0011lll_dataout <= wire_niO10iii_dataout WHEN niOliOO0O = '1' ELSE n01OO1Ol; + wire_n0011llO_dataout <= wire_niO10iil_dataout WHEN niOliOO0O = '1' ELSE n01OO1OO; + wire_n0011lO_dataout <= wire_n1llO0O_q(124) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ollii; + wire_n0011lOi_dataout <= wire_niO10iiO_dataout WHEN niOliOO0O = '1' ELSE n01OO01i; + wire_n0011lOl_dataout <= wire_niO10ili_dataout WHEN niOliOO0O = '1' ELSE n01OO01l; + wire_n0011lOO_dataout <= wire_niO10ill_dataout WHEN niOliOO0O = '1' ELSE n01OO01O; + wire_n0011O0i_dataout <= wire_n0011Oil_dataout OR niOliOO0O; + wire_n0011O0l_dataout <= wire_n0011OiO_dataout OR niOliOO0O; + wire_n0011O0O_dataout <= wire_n0011Oli_dataout WHEN wire_w_lg_niOliOlll16415w(0) = '1' ELSE n01OO00l; + wire_n0011O1i_dataout <= niOliOOOl WHEN niOliOO0O = '1' ELSE n01OO00i; + wire_n0011O1l_dataout <= wire_n0011O0O_dataout OR niOliOO0O; + wire_n0011O1O_dataout <= wire_n0011Oii_dataout AND NOT(niOliOO0O); + wire_n0011Oi_dataout <= wire_n1llO0O_q(125) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ollil; + wire_n0011Oii_dataout <= wire_n0011Oll_dataout WHEN wire_w_lg_niOliOlll16415w(0) = '1' ELSE n01OO00O; + wire_n0011Oil_dataout <= wire_n0011OlO_dataout WHEN wire_w_lg_niOliOlll16415w(0) = '1' ELSE n01OO0ii; + wire_n0011OiO_dataout <= wire_n0011OOi_dataout WHEN wire_w_lg_niOliOlll16415w(0) = '1' ELSE n01OO0il; + wire_n0011Ol_dataout <= wire_n1llO0O_q(126) WHEN wire_n1O0lli_dataout = '1' ELSE n1OlliO; + wire_n0011Oli_dataout <= wire_n0011OOl_o(1) AND niOliOllO; + wire_n0011Oll_dataout <= wire_n0011OOl_o(2) AND niOliOllO; + wire_n0011OlO_dataout <= wire_n0011OOl_o(3) AND niOliOllO; + wire_n0011OO_dataout <= wire_n1llO0O_q(127) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ollli; + wire_n0011OOi_dataout <= wire_n0011OOl_o(4) AND niOliOllO; + wire_n001i00i_dataout <= wire_n001i0ll_dataout AND NOT(niOll11iO); + wire_n001i00l_dataout <= wire_n001i0lO_dataout AND NOT(niOll11iO); + wire_n001i00O_dataout <= wire_n001i0Oi_dataout AND NOT(niOll11iO); + wire_n001i01i_dataout <= wire_n001i0il_dataout AND NOT(niOll11iO); + wire_n001i01l_dataout <= wire_n001i0iO_dataout AND NOT(niOll11iO); + wire_n001i01O_dataout <= wire_n001i0li_dataout AND NOT(niOll11iO); + wire_n001i0i_dataout <= wire_n0i0iiO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001i0ii_dataout <= wire_n001i0Ol_o(0) WHEN niOll11ii = '1' ELSE n0010l0i; + wire_n001i0il_dataout <= wire_n001i0Ol_o(1) WHEN niOll11ii = '1' ELSE n001i11i; + wire_n001i0iO_dataout <= wire_n001i0Ol_o(2) WHEN niOll11ii = '1' ELSE n001i11l; + wire_n001i0l_dataout <= wire_n0i0ili_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001i0li_dataout <= wire_n001i0Ol_o(3) WHEN niOll11ii = '1' ELSE n001i11O; + wire_n001i0ll_dataout <= wire_n001i0Ol_o(4) WHEN niOll11ii = '1' ELSE n001i10i; + wire_n001i0lO_dataout <= wire_n001i0Ol_o(5) WHEN niOll11ii = '1' ELSE n001i10l; + wire_n001i0O_dataout <= wire_n0i0ill_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001i0Oi_dataout <= wire_n001i0Ol_o(6) WHEN niOll11ii = '1' ELSE n001i10O; + wire_n001i1i_dataout <= n0ili1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001i1il_dataout <= wire_n001i1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001i1iO_dataout <= wire_n001i01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001i1l_dataout <= n0ili0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001i1li_dataout <= wire_n001i01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001i1ll_dataout <= wire_n001i01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001i1lO_dataout <= wire_n001i00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001i1O_dataout <= wire_n0i0iil_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001i1Oi_dataout <= wire_n001i00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001i1Ol_dataout <= wire_n001i00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001i1OO_dataout <= wire_n001i0ii_dataout AND NOT(niOll11iO); + wire_n001ii0i_dataout <= n001ilOi AND (((NOT (wire_niili01i_dataout XOR n001illi)) AND (NOT (wire_niili01l_dataout XOR n001illl))) AND (NOT (n1101l1i XOR n001illO))); + wire_n001ii0i_w_lg_w_lg_w_lg_dataout16226w16232w16233w(0) <= wire_n001ii0i_w_lg_w_lg_dataout16226w16232w(0) AND n001ilOi; + wire_n001ii0i_w_lg_w_lg_dataout16226w16232w(0) <= wire_n001ii0i_w_lg_dataout16226w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n001ilil16227w16229w16231w(0); + wire_n001ii0i_w_lg_dataout16239w(0) <= wire_n001ii0i_dataout AND wire_niO01ill_w16238w(0); + wire_n001ii0i_w_lg_dataout16226w(0) <= NOT wire_n001ii0i_dataout; + wire_n001ii0l_dataout <= n001iO0l AND (n001ilOl AND niOll11li); + wire_n001iii_dataout <= wire_n0i0ilO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001iiii_dataout <= n001iO0l AND ((NOT (n001iO1i XOR n001ilOO)) AND niOll11li); + wire_n001iil_dataout <= wire_n0i0iOi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001iili_dataout <= n001i1ii AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllOlli); + wire_n001iiO_dataout <= wire_n0i0iOl_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001ili_dataout <= wire_n0i0iOO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n001ill_dataout <= n0Ol00l WHEN niOO0i00O = '1' ELSE wire_n001l0i_dataout; + wire_n001ilO_dataout <= n0Ol00O WHEN niOO0i00O = '1' ELSE wire_n001l0l_dataout; + wire_n001iOi_dataout <= n0Ol0ii WHEN niOO0i00O = '1' ELSE wire_n001l0O_dataout; + wire_n001iOil_dataout <= wire_n001lO1i_dataout OR wire_niO01lOO_dataout; + wire_n001iOiO_dataout <= wire_n001lOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001iOl_dataout <= n0Ol0il WHEN niOO0i00O = '1' ELSE wire_n001lii_dataout; + wire_n001iOli_dataout <= wire_n001lOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001iOll_dataout <= wire_n001lOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001iOlO_dataout <= wire_n001lOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001iOO_dataout <= n0Ol0iO WHEN niOO0i00O = '1' ELSE wire_n001lil_dataout; + wire_n001iOOi_dataout <= wire_n001lOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001iOOl_dataout <= wire_n001lOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001iOOO_dataout <= wire_n001lOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l00i_dataout <= wire_n001liOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l00l_dataout <= wire_n001l0lO_dataout AND NOT(niOll11ll); + wire_n001l00O_dataout <= wire_n001l0Oi_dataout AND NOT(niOll11ll); + wire_n001l01i_dataout <= wire_n0000lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l01l_dataout <= wire_n0000OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l01O_dataout <= wire_n001liOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l0i_dataout <= wire_n001llO_dataout AND NOT(niOO0i00l); + wire_n001l0ii_dataout <= wire_n001l0Ol_dataout AND NOT(niOll11ll); + wire_n001l0il_dataout <= wire_n001l0OO_dataout AND NOT(niOll11ll); + wire_n001l0iO_dataout <= wire_n001li1i_dataout AND NOT(niOll11ll); + wire_n001l0l_dataout <= wire_n001lOi_dataout AND NOT(niOO0i00l); + wire_n001l0li_dataout <= wire_n001li1l_dataout AND NOT(niOll11ll); + wire_n001l0ll_dataout <= wire_n001li1O_dataout AND NOT(niOll11ll); + wire_n001l0lO_dataout <= wire_n001li0i_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001il0O; + wire_n001l0O_dataout <= wire_n001lOl_dataout AND NOT(niOO0i00l); + wire_n001l0Oi_dataout <= wire_n001li0i_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001ilii; + wire_n001l0Ol_dataout <= wire_n001li0i_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001ilil; + wire_n001l0OO_dataout <= wire_n001li0i_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001iliO; + wire_n001l10i_dataout <= wire_n001l00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l10l_dataout <= wire_n001l0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l10O_dataout <= wire_n001l0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l11i_dataout <= wire_n001lOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l11l_dataout <= wire_n001lOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l11O_dataout <= wire_n001l00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1i_dataout <= n0Ol0li WHEN niOO0i00O = '1' ELSE wire_n001liO_dataout; + wire_n001l1ii_dataout <= wire_n001l0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1il_dataout <= wire_n001l0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1iO_dataout <= wire_n001l0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1l_dataout <= n0Ol0ll WHEN niOO0i00O = '1' ELSE wire_n001lli_dataout; + wire_n001l1li_dataout <= wire_n001liil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1ll_dataout <= wire_n0000l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1lO_dataout <= wire_n0000lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1O_dataout <= n0Ol0lO WHEN niOO0i00O = '1' ELSE wire_n001lll_dataout; + wire_n001l1Oi_dataout <= wire_n0000lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1Ol_dataout <= wire_n0000liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001l1OO_dataout <= wire_n0000lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n001li1i_dataout <= wire_n001li0i_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001illi; + wire_n001li1l_dataout <= wire_n001li0i_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001illl; + wire_n001li1O_dataout <= wire_n001li0i_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n001illO; + wire_n001lii_dataout <= wire_n001lOO_dataout AND NOT(niOO0i00l); + wire_n001liil_dataout <= wire_n001liiO_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w16098w(0) AND wire_w_lg_niOll1iil16099w(0)); + wire_n001liiO_dataout <= n001ilOi AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOll1iiO16245w(0))); + wire_n001lil_dataout <= wire_n001O1i_dataout AND NOT(niOO0i00l); + wire_n001liO_dataout <= wire_n001O1l_dataout AND NOT(niOO0i00l); + wire_n001liOi_dataout <= n001iO0O WHEN nlOllOlli = '1' ELSE wire_n001liOl_dataout; + wire_n001liOl_dataout <= wire_n001liOO_dataout OR niOll1i1i; + wire_n001liOO_dataout <= wire_n001ll1i_dataout OR n000i1iO; + wire_n001ll0i_dataout <= wire_n001ll0l_dataout OR (wire_niO01ill_w_lg_n000i10O16096w(0) AND wire_n001ii0i_w_lg_dataout16239w(0)); + wire_n001ll0l_dataout <= wire_n001ll0O_dataout OR (wire_niO01ill_w_lg_n000i10O16096w(0) AND wire_n001ii0i_w_lg_w_lg_w_lg_dataout16226w16232w16233w(0)); + wire_n001ll0O_dataout <= n001iOii AND nlOllOlli; + wire_n001ll1i_dataout <= wire_n001ll1l_dataout OR (wire_niO01ill_w_lg_n000i10O16096w(0) AND (wire_n001ii0i_dataout AND niOll10li)); + wire_n001ll1l_dataout <= wire_n001ll0i_dataout OR (wire_niO01ill_w_lg_n000i10O16096w(0) AND (wire_n001ii0i_dataout AND niOll101O)); + wire_n001lli_dataout <= wire_n001O1O_dataout AND NOT(niOO0i00l); + wire_n001lll_dataout <= wire_n001O0i_dataout AND NOT(niOO0i00l); + wire_n001llO_dataout <= wire_n001O0l_dataout AND NOT(niOO0i00i); + wire_n001lO1i_dataout <= wire_n001lO1l_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n000i1il AND n001iO1i)) OR (n000i1il AND n001ilil)); + wire_n001lO1l_dataout <= n001i1ii AND nlOllOlli; + wire_n001lOi_dataout <= wire_n001O0O_dataout AND NOT(niOO0i00i); + wire_n001lOii_dataout <= wire_n01l011l_dataout WHEN niOll1i0l = '1' ELSE wire_n001O11i_dataout; + wire_n001lOil_dataout <= wire_n01l1OOO_dataout WHEN niOll1i0l = '1' ELSE wire_n001O11l_dataout; + wire_n001lOiO_dataout <= wire_n01l1OOi_dataout WHEN niOll1i0l = '1' ELSE wire_n001O11O_dataout; + wire_n001lOl_dataout <= wire_n001Oii_dataout AND NOT(niOO0i00i); + wire_n001lOli_dataout <= wire_n01l1Oll_dataout WHEN niOll1i0l = '1' ELSE wire_n001O10i_dataout; + wire_n001lOll_dataout <= wire_n01l1OiO_dataout WHEN niOll1i0l = '1' ELSE wire_n001O10l_dataout; + wire_n001lOlO_dataout <= wire_n01l1O0O_dataout WHEN niOll1i0l = '1' ELSE wire_n001O10O_dataout; + wire_n001lOO_dataout <= wire_n001Oil_dataout AND NOT(niOO0i00i); + wire_n001lOOi_dataout <= wire_n01l1O0i_dataout WHEN niOll1i0l = '1' ELSE wire_n001O1ii_dataout; + wire_n001lOOl_dataout <= wire_n01l1O1i_dataout WHEN niOll1i0l = '1' ELSE wire_n001O1il_dataout; + wire_n001lOOO_dataout <= n000i1ll WHEN niOll1i0l = '1' ELSE wire_n001O1iO_dataout; + wire_n001O00i_dataout <= wire_n001O0Oi_dataout AND NOT(niOll10Oi); + wire_n001O00l_dataout <= wire_n001O0Ol_dataout AND NOT(niOll10Oi); + wire_n001O00O_dataout <= wire_n001O0OO_dataout OR niOll10Oi; + wire_n001O01i_dataout <= wire_n001O0iO_dataout AND NOT(niOll10OO); + wire_n001O01l_dataout <= wire_n001O0li_dataout AND NOT(niOll10OO); + wire_n001O01O_dataout <= wire_n001O0ll_dataout AND NOT(niOll10OO); + wire_n001O0i_dataout <= wire_n001OlO_dataout AND NOT(niOO0i00i); + wire_n001O0ii_dataout <= wire_n001Oi1i_dataout OR niOll10Oi; + wire_n001O0il_dataout <= wire_n001Oi1l_dataout OR niOll10Oi; + wire_n001O0iO_dataout <= wire_n001Oi1O_dataout OR niOll10Oi; + wire_n001O0l_dataout <= n0il10O AND NOT(niOO0i01O); + wire_n001O0li_dataout <= wire_n001Oi0i_dataout OR niOll10Oi; + wire_n001O0ll_dataout <= wire_n001Oi0l_dataout AND NOT(niOll10Oi); + wire_n001O0lO_dataout <= wire_n001Oi0O_dataout OR niOll10Oi; + wire_n001O0O_dataout <= n0il1ii AND NOT(niOO0i01O); + wire_n001O0Oi_dataout <= wire_n001Oiii_dataout OR niOll10lO; + wire_n001O0Ol_dataout <= wire_n001Oiil_dataout AND NOT(niOll10lO); + wire_n001O0OO_dataout <= wire_n001OiiO_dataout OR niOll10lO; + wire_n001O10i_dataout <= wire_n001O1Ol_dataout OR niOll1i1O; + wire_n001O10l_dataout <= wire_n001O1OO_dataout OR niOll1i1O; + wire_n001O10O_dataout <= wire_n001O01i_dataout OR niOll1i1O; + wire_n001O11i_dataout <= wire_n001O1ll_dataout AND NOT(niOll1i1O); + wire_n001O11l_dataout <= wire_n001O1lO_dataout AND NOT(niOll1i1O); + wire_n001O11O_dataout <= wire_n001O1Oi_dataout OR niOll1i1O; + wire_n001O1i_dataout <= wire_n001OiO_dataout AND NOT(niOO0i00i); + wire_n001O1ii_dataout <= wire_n001O01l_dataout AND NOT(niOll1i1O); + wire_n001O1il_dataout <= wire_n001O01O_dataout OR niOll1i1O; + wire_n001O1iO_dataout <= wire_n001O1li_dataout OR niOll1i1O; + wire_n001O1l_dataout <= wire_n001Oli_dataout AND NOT(niOO0i00i); + wire_n001O1li_dataout <= wire_n001O0lO_dataout AND NOT(niOll10OO); + wire_n001O1ll_dataout <= wire_n001O00i_dataout AND NOT(niOll10OO); + wire_n001O1lO_dataout <= wire_n001O00l_dataout AND NOT(niOll10OO); + wire_n001O1O_dataout <= wire_n001Oll_dataout AND NOT(niOO0i00i); + wire_n001O1Oi_dataout <= wire_n001O00O_dataout AND NOT(niOll10OO); + wire_n001O1Ol_dataout <= wire_n001O0ii_dataout AND NOT(niOll10OO); + wire_n001O1OO_dataout <= wire_n001O0il_dataout AND NOT(niOll10OO); + wire_n001Oi0i_dataout <= wire_n001OiOi_dataout AND NOT(niOll10lO); + wire_n001Oi0l_dataout <= wire_n001OiOl_dataout OR niOll10lO; + wire_n001Oi0O_dataout <= wire_n001OiOO_dataout AND NOT(niOll10lO); + wire_n001Oi1i_dataout <= wire_n001Oili_dataout AND NOT(niOll10lO); + wire_n001Oi1l_dataout <= wire_n001Oill_dataout OR niOll10lO; + wire_n001Oi1O_dataout <= wire_n001OilO_dataout OR niOll10lO; + wire_n001Oii_dataout <= n0il1il AND NOT(niOO0i01O); + wire_n001Oiii_dataout <= wire_n001Ol1i_dataout AND NOT(niOll10ll); + wire_n001Oiil_dataout <= wire_n001Ol1l_dataout OR niOll10ll; + wire_n001OiiO_dataout <= wire_n001Ol1O_dataout AND NOT(niOll10ll); + wire_n001Oil_dataout <= n0il01O AND NOT(niOO0i01O); + wire_n001Oili_dataout <= wire_n001Ol0i_dataout OR niOll10ll; + wire_n001Oill_dataout <= wire_n001Ol0l_dataout AND NOT(niOll10ll); + wire_n001OilO_dataout <= wire_n001Ol0O_dataout AND NOT(niOll10ll); + wire_n001OiO_dataout <= n0il10O AND niOO0i01O; + wire_n001OiOi_dataout <= wire_n001Olii_dataout OR niOll10ll; + wire_n001OiOl_dataout <= wire_n001Olil_dataout AND NOT(niOll10ll); + wire_n001OiOO_dataout <= wire_n001OliO_dataout AND NOT(niOll10ll); + wire_n001Ol0i_dataout <= wire_n0001i0O_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001OlOi_dataout; + wire_n001Ol0l_dataout <= wire_n0001iii_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001OlOl_dataout; + wire_n001Ol0O_dataout <= wire_n0001iil_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001OlOO_dataout; + wire_n001Ol1i_dataout <= wire_n0001i1O_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001Olli_dataout; + wire_n001Ol1l_dataout <= wire_n0001i0i_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001Olll_dataout; + wire_n001Ol1O_dataout <= wire_n0001i0l_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001OllO_dataout; + wire_n001Oli_dataout <= n0il1ii AND niOO0i01O; + wire_n001Olii_dataout <= wire_n0001iiO_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001OO1i_dataout; + wire_n001Olil_dataout <= wire_n0001ili_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001OO1l_dataout; + wire_n001OliO_dataout <= wire_n0001ill_dataout WHEN wire_n001ii0i_dataout = '1' ELSE wire_n001OO1O_dataout; + wire_n001Oll_dataout <= n0il1il AND niOO0i01O; + wire_n001Olli_dataout <= wire_n001OO0i_dataout AND NOT(niOll101i); + wire_n001Olll_dataout <= wire_n001OO0l_dataout AND NOT(niOll101i); + wire_n001OllO_dataout <= wire_n001OO0O_dataout OR niOll101i; + wire_n001OlO_dataout <= n0il01O AND niOO0i01O; + wire_n001OlOi_dataout <= wire_n001OOii_dataout OR niOll101i; + wire_n001OlOl_dataout <= wire_n001OOil_dataout OR niOll101i; + wire_n001OlOO_dataout <= wire_n001OOiO_dataout OR niOll101i; + wire_n001OO0i_dataout <= wire_n001OOOi_dataout AND NOT(niOll11OO); + wire_n001OO0l_dataout <= wire_n001OOOl_dataout AND NOT(niOll11OO); + wire_n001OO0O_dataout <= wire_n001OOOO_dataout OR niOll11OO; + wire_n001OO1i_dataout <= wire_n001OOli_dataout AND NOT(niOll101i); + wire_n001OO1l_dataout <= wire_n001OOll_dataout OR niOll101i; + wire_n001OO1O_dataout <= wire_n001OOlO_dataout OR niOll101i; + wire_n001OOii_dataout <= wire_n000111i_dataout OR niOll11OO; + wire_n001OOil_dataout <= wire_n000111l_dataout OR niOll11OO; + wire_n001OOiO_dataout <= wire_n000111O_dataout OR niOll11OO; + wire_n001OOli_dataout <= wire_n000110i_dataout OR niOll11OO; + wire_n001OOll_dataout <= wire_n000110l_dataout AND NOT(niOll11OO); + wire_n001OOlO_dataout <= wire_n000110O_dataout OR niOll11OO; + wire_n001OOOi_dataout <= wire_n00011ii_dataout AND NOT(niOll11Ol); + wire_n001OOOl_dataout <= wire_n00011il_dataout AND NOT(niOll11Ol); + wire_n001OOOO_dataout <= wire_n00011iO_dataout AND NOT(niOll11Ol); + wire_n00i00i_dataout <= wire_n00l1il_dataout AND NOT(niOO0i0li); + wire_n00i00l_dataout <= wire_n00l1iO_dataout AND NOT(niOO0i0li); + wire_n00i00O_dataout <= wire_n00l1li_dataout AND NOT(niOO0i0li); + wire_n00i010i_dataout <= n00i1i1i WHEN niOll1l0i = '1' ELSE n00i10il; + wire_n00i011i_dataout <= n00i10Oi WHEN niOll1l0i = '1' ELSE (n00i1i1i XOR n00i100l); + wire_n00i011l_dataout <= n00i10Ol WHEN niOll1l0i = '1' ELSE n00i100O; + wire_n00i011O_dataout <= n00i10OO WHEN niOll1l0i = '1' ELSE n00i10ii; + wire_n00i01i_dataout <= wire_n00l10l_dataout AND NOT(niOO0i0li); + wire_n00i01l_dataout <= wire_n00l10O_dataout AND NOT(niOO0i0li); + wire_n00i01O_dataout <= wire_n00l1ii_dataout AND NOT(niOO0i0li); + wire_n00i0ii_dataout <= wire_n00l1ll_dataout AND NOT(niOO0i0li); + wire_n00i0il_dataout <= wire_n00l1lO_dataout AND NOT(niOO0i0li); + wire_n00i0iO_dataout <= wire_n00l1Oi_dataout AND NOT(niOO0i0li); + wire_n00i0li_dataout <= wire_n00l1Ol_dataout AND NOT(niOO0i0li); + wire_n00i0ll_dataout <= wire_n00l1OO_dataout AND NOT(niOO0i0li); + wire_n00i0lO_dataout <= wire_n00l01i_dataout AND NOT(niOO0i0li); + wire_n00i0Oi_dataout <= wire_n00l01l_dataout AND NOT(niOO0i0li); + wire_n00i0Ol_dataout <= wire_n00l01O_dataout AND NOT(niOO0i0li); + wire_n00i0OO_dataout <= wire_n00l00i_dataout AND NOT(niOO0i0li); + wire_n00i10i_dataout <= wire_n00iOil_dataout AND NOT(niOO0i0li); + wire_n00i10l_dataout <= wire_n00iOiO_dataout AND NOT(niOO0i0li); + wire_n00i10O_dataout <= wire_n00iOli_dataout AND NOT(niOO0i0li); + wire_n00i110i_dataout <= wire_niO100iO_dataout WHEN niOll1l1l = '1' ELSE (wire_niO100iO_dataout XOR n00i10ll); + wire_n00i110i_w_lg_dataout15824w(0) <= NOT wire_n00i110i_dataout; + wire_n00i111l_dataout <= wire_niO100li_dataout WHEN niOll1l1l = '1' ELSE (wire_niO100li_dataout XOR n00i10li); + wire_n00i111l_w_lg_dataout15826w(0) <= NOT wire_n00i111l_dataout; + wire_n00i11i_dataout <= wire_n00iO0l_dataout AND NOT(niOO0i0li); + wire_n00i11ii_dataout <= wire_niO100il_dataout WHEN niOll1l1l = '1' ELSE (wire_niO100il_dataout XOR n00i10lO); + wire_n00i11ii_w_lg_dataout15822w(0) <= NOT wire_n00i11ii_dataout; + wire_n00i11iO_dataout <= wire_niO100ii_dataout WHEN niOll1l1l = '1' ELSE (wire_niO100ii_dataout XOR n00i10Oi); + wire_n00i11iO_w_lg_dataout15820w(0) <= NOT wire_n00i11iO_dataout; + wire_n00i11l_dataout <= wire_n00iO0O_dataout AND NOT(niOO0i0li); + wire_n00i11ll_dataout <= wire_niO1000O_dataout WHEN niOll1l1l = '1' ELSE (wire_niO1000O_dataout XOR n00i10Ol); + wire_n00i11ll_w_lg_dataout15818w(0) <= NOT wire_n00i11ll_dataout; + wire_n00i11O_dataout <= wire_n00iOii_dataout AND NOT(niOO0i0li); + wire_n00i11Oi_dataout <= wire_niO1000l_dataout WHEN niOll1l1l = '1' ELSE (wire_niO1000l_dataout XOR n00i10OO); + wire_n00i11Oi_w_lg_dataout15816w(0) <= NOT wire_n00i11Oi_dataout; + wire_n00i11OO_dataout <= wire_niO1000i_dataout WHEN niOll1l1l = '1' ELSE (wire_niO1000i_dataout XOR n00i1i1i); + wire_n00i11OO_w_lg_dataout15814w(0) <= NOT wire_n00i11OO_dataout; + wire_n00i1i0i_dataout <= wire_n00i1l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1i0l_dataout <= wire_n00i1l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1i0O_dataout <= wire_n00i1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1i1l_dataout <= wire_n00i1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1i1O_dataout <= wire_n00i1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1ii_dataout <= wire_n00iOll_dataout AND NOT(niOO0i0li); + wire_n00i1iii_dataout <= wire_n00i1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1iil_dataout <= wire_n00i1liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1iiO_dataout <= wire_n00i1lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1il_dataout <= wire_n00iOlO_dataout AND NOT(niOO0i0li); + wire_n00i1ili_dataout <= wire_n00i1lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1ill_dataout <= wire_n00i1llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1ilO_dataout <= wire_n00i1lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1iO_dataout <= wire_n00iOOi_dataout AND NOT(niOO0i0li); + wire_n00i1iOi_dataout <= wire_n00i1lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1iOl_dataout <= wire_n00i1lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1iOO_dataout <= wire_n00i1O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1l0i_dataout <= wire_n00i1O0l_dataout OR niOll1l1O; + wire_n00i1l0l_dataout <= wire_n00i1O0O_dataout OR niOll1l1O; + wire_n00i1l0O_dataout <= wire_n00i1Oii_dataout OR niOll1l1O; + wire_n00i1l1i_dataout <= wire_n00i1O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1l1l_dataout <= wire_n00i1O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00i1l1O_dataout <= wire_n00i1O0i_dataout OR niOll1l1O; + wire_n00i1li_dataout <= wire_n00iOOl_dataout AND NOT(niOO0i0li); + wire_n00i1lii_dataout <= wire_n00i1Oil_dataout OR niOll1l1O; + wire_n00i1lil_dataout <= wire_n00i1OiO_dataout OR niOll1l1O; + wire_n00i1liO_dataout <= wire_n00i1Oli_dataout OR niOll1l1O; + wire_n00i1ll_dataout <= wire_n00iOOO_dataout AND NOT(niOO0i0li); + wire_n00i1lli_dataout <= wire_n00i1Oll_dataout OR niOll1l1O; + wire_n00i1lll_dataout <= wire_n00i1OlO_dataout OR niOll1l1O; + wire_n00i1llO_dataout <= wire_n00i1OOi_dataout OR niOll1l1O; + wire_n00i1lO_dataout <= wire_n00l11i_dataout AND NOT(niOO0i0li); + wire_n00i1lOi_dataout <= wire_n00i1OOl_dataout OR niOll1l1O; + wire_n00i1lOl_dataout <= wire_n00i1OOO_dataout OR niOll1l1O; + wire_n00i1lOO_dataout <= wire_n00i011i_dataout OR niOll1l1O; + wire_n00i1O0i_dataout <= n00i110O WHEN niOll1l0i = '1' ELSE n00i10iO; + wire_n00i1O0l_dataout <= n00i101l WHEN niOll1l0i = '1' ELSE n00i10li; + wire_n00i1O0O_dataout <= n00i101O WHEN niOll1l0i = '1' ELSE n00i10ll; + wire_n00i1O1i_dataout <= wire_n00i011l_dataout OR niOll1l1O; + wire_n00i1O1l_dataout <= wire_n00i011O_dataout OR niOll1l1O; + wire_n00i1O1O_dataout <= wire_n00i010i_dataout OR niOll1l1O; + wire_n00i1Oi_dataout <= wire_n00l11l_dataout AND NOT(niOO0i0li); + wire_n00i1Oii_dataout <= n00i100i WHEN niOll1l0i = '1' ELSE (n00i10lO XOR n00i10iO); + wire_n00i1Oil_dataout <= n00i100l WHEN niOll1l0i = '1' ELSE (n00i10iO XOR (n00i10Oi XOR n00i10li)); + wire_n00i1OiO_dataout <= n00i100O WHEN niOll1l0i = '1' ELSE (n00i10iO XOR (n00i10li XOR (n00i10Ol XOR n00i10ll))); + wire_n00i1Ol_dataout <= wire_n00l11O_dataout AND NOT(niOO0i0li); + wire_n00i1Oli_dataout <= n00i10ii WHEN niOll1l0i = '1' ELSE (n00i10li XOR (n00i10ll XOR (n00i10OO XOR n00i10lO))); + wire_n00i1Oll_dataout <= n00i10il WHEN niOll1l0i = '1' ELSE (n00i10ll XOR (n00i10lO XOR (n00i1i1i XOR n00i10Oi))); + wire_n00i1OlO_dataout <= n00i10iO WHEN niOll1l0i = '1' ELSE (n00i10lO XOR (n00i10Oi XOR (n00i10Ol XOR n00i110O))); + wire_n00i1OO_dataout <= wire_n00l10i_dataout AND NOT(niOO0i0li); + wire_n00i1OOi_dataout <= n00i10li WHEN niOll1l0i = '1' ELSE (n00i10Oi XOR (n00i10Ol XOR (n00i10OO XOR n00i101l))); + wire_n00i1OOl_dataout <= n00i10ll WHEN niOll1l0i = '1' ELSE (n00i10Ol XOR (n00i10OO XOR (n00i1i1i XOR n00i101O))); + wire_n00i1OOO_dataout <= n00i10lO WHEN niOll1l0i = '1' ELSE (n00i10OO XOR (n00i1i1i XOR n00i100i)); + wire_n00ii0i_dataout <= wire_n00l0il_dataout AND NOT(niOO0i0li); + wire_n00ii0il_dataout <= wire_niO1001O_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00ii0iO_dataout <= wire_n00i11OO_dataout AND wire_niO101Ol_w_lg_dataout15723w(0); + wire_n00ii0l_dataout <= wire_n00l0iO_dataout AND NOT(niOO0i0li); + wire_n00ii0li_dataout <= wire_n00i11Oi_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00ii0ll_dataout <= wire_n00i11ll_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00ii0lO_dataout <= wire_n00i11iO_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00ii0O_dataout <= wire_n00l0li_dataout AND NOT(niOO0i0li); + wire_n00ii0Oi_dataout <= wire_n00i11ii_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00ii0Ol_dataout <= wire_n00i110i_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00ii0OO_dataout <= wire_n00i111l_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00ii1i_dataout <= wire_n00l00l_dataout AND NOT(niOO0i0li); + wire_n00ii1l_dataout <= wire_n00l00O_dataout AND NOT(niOO0i0li); + wire_n00ii1O_dataout <= wire_n00l0ii_dataout AND NOT(niOO0i0li); + wire_n00iii0O_dataout <= wire_n00iiili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iii1i_dataout <= wire_n000OOOl_dataout OR NOT(wire_niO101Ol_w_lg_dataout15723w(0)); + wire_n00iiii_dataout <= wire_n00l0ll_dataout AND NOT(niOO0i0li); + wire_n00iiiii_dataout <= wire_n00iiiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iiiil_dataout <= wire_n00iiiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iiiiO_dataout <= wire_n00iil1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iiil_dataout <= wire_n00l0lO_dataout AND NOT(niOO0i0li); + wire_n00iiili_dataout <= wire_n00iiill_dataout AND n00O1i1l; + wire_n00iiill_dataout <= n00iiiOi OR (n00O1i1l AND n00iii1l); + wire_n00iiiO_dataout <= wire_n00l0Oi_dataout AND NOT(niOO0i0li); + wire_n00iiiOl_dataout <= ((wire_niO1001l_dataout AND niOll011O) AND n00iii1O) AND n00O1i1l; + wire_n00iiiOO_dataout <= (niOll000i AND n00iii0i) AND n00O1i1l; + wire_n00iil1i_dataout <= (n00lO0ii AND (wire_niO1001l_dataout AND niOll010i)) AND n00O1i1l; + wire_n00iili_dataout <= wire_n00l0Ol_dataout AND NOT(niOO0i0li); + wire_n00iill_dataout <= wire_n00l0OO_dataout AND NOT(niOO0i0li); + wire_n00iilll_dataout <= wire_n00iilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iillO_dataout <= wire_n00il10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iilO_dataout <= wire_n00li1i_dataout AND NOT(niOO0i0li); + wire_n00iilOi_dataout <= wire_n00iiO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iilOl_dataout <= wire_n00iiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iilOO_dataout <= wire_n00iiO1O_dataout AND NOT(niOll1l0l); + wire_n00iiO0i_dataout <= wire_n00iiOiO_dataout WHEN wire_niO01ill_w_lg_n00iilii15716w(0) = '1' ELSE wire_n00iiO0O_dataout; + wire_n00iiO0l_dataout <= wire_n00iiOli_dataout WHEN wire_niO01ill_w_lg_n00iilii15716w(0) = '1' ELSE wire_n00iiOii_dataout; + wire_n00iiO0O_dataout <= wire_n00iiOOO_dataout WHEN niOll01ll = '1' ELSE wire_n00iiOiO_dataout; + wire_n00iiO1i_dataout <= wire_n00il10i_dataout WHEN niOll1l0l = '1' ELSE wire_n00iiO0i_dataout; + wire_n00iiO1l_dataout <= wire_n00il10l_dataout WHEN niOll1l0l = '1' ELSE wire_n00iiO0l_dataout; + wire_n00iiO1O_dataout <= n00iii0l WHEN wire_niO01ill_w_lg_n00iilii15716w(0) = '1' ELSE wire_n00iiOil_dataout; + wire_n00iiOi_dataout <= wire_n00li1l_dataout AND NOT(niOO0i0li); + wire_n00iiOii_dataout <= wire_n00il11i_dataout WHEN niOll01ll = '1' ELSE wire_n00iiOli_dataout; + wire_n00iiOil_dataout <= wire_n00il11l_dataout WHEN niOll01ll = '1' ELSE n00iii0l; + wire_n00iiOiO_dataout <= n00iilil AND NOT(niOll1lii); + wire_n00iiOl_dataout <= wire_n00li1O_dataout AND NOT(niOO0i0li); + wire_n00iiOli_dataout <= n00iiliO AND NOT(niOll1lii); + wire_n00iiOO_dataout <= wire_n00li0i_dataout AND NOT(niOO0i0li); + wire_n00iiOOO_dataout <= n00iilil WHEN niOll1l0O = '1' ELSE wire_n00il11O_o(0); + wire_n00il00i_dataout <= wire_n00il0li_dataout OR wire_niO01lOO_dataout; + wire_n00il00l_dataout <= wire_n00il0ll_dataout OR wire_niO01lOO_dataout; + wire_n00il00O_dataout <= wire_n00il0lO_dataout OR wire_niO01lOO_dataout; + wire_n00il01i_dataout <= wire_n00il0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00il01l_dataout <= wire_n00il0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00il01O_dataout <= wire_n00il0iO_dataout OR wire_niO01lOO_dataout; + wire_n00il0i_dataout <= wire_n00liil_dataout AND NOT(niOO0i0li); + wire_n00il0ii_dataout <= wire_n00il0Oi_dataout OR niOll1O0O; + wire_n00il0il_dataout <= wire_n00il0Ol_dataout AND NOT(niOll1O0O); + wire_n00il0iO_dataout <= wire_n00il0OO_dataout OR niOll1O0O; + wire_n00il0l_dataout <= wire_n00liiO_dataout AND NOT(niOO0i0li); + wire_n00il0li_dataout <= wire_n00ili1i_dataout AND NOT(niOll1O0O); + wire_n00il0ll_dataout <= wire_n00ili1l_dataout OR niOll1O0O; + wire_n00il0lO_dataout <= wire_n00ili1O_dataout OR niOll1O0O; + wire_n00il0O_dataout <= wire_n00lili_dataout AND NOT(niOO0i0li); + wire_n00il0Oi_dataout <= wire_n00ili0i_dataout AND n00iilli; + wire_n00il0Ol_dataout <= wire_n00ili0l_dataout AND n00iilli; + wire_n00il0OO_dataout <= wire_n00ili0O_dataout OR NOT(n00iilli); + wire_n00il10i_dataout <= n00iilil OR niOll01ll; + wire_n00il10l_dataout <= n00iiliO AND NOT(niOll01ll); + wire_n00il10O_dataout <= wire_n00il1ii_dataout OR (niOll001l AND (n00lO1Ol OR n00llOOl)); + wire_n00il11i_dataout <= n00iiliO WHEN niOll1l0O = '1' ELSE wire_n00il11O_o(1); + wire_n00il11l_dataout <= n00iii0l OR niOll1l0O; + wire_n00il1i_dataout <= wire_n00li0l_dataout AND NOT(niOO0i0li); + wire_n00il1ii_dataout <= n00iilii AND NOT(niOll1lii); + wire_n00il1l_dataout <= wire_n00li0O_dataout AND NOT(niOO0i0li); + wire_n00il1O_dataout <= wire_n00liii_dataout AND NOT(niOO0i0li); + wire_n00ili0i_dataout <= n00iilli WHEN niOll1liO = '1' ELSE wire_n00ilili_dataout; + wire_n00ili0l_dataout <= niOll1lil AND NOT(niOll1liO); + wire_n00ili0O_dataout <= wire_n00ililO_o(1) OR NOT(niOll1liO); + wire_n00ili1i_dataout <= wire_n00iliii_dataout OR NOT(n00iilli); + wire_n00ili1l_dataout <= wire_n00iliil_dataout OR NOT(n00iilli); + wire_n00ili1O_dataout <= wire_n00iliiO_dataout OR NOT(n00iilli); + wire_n00ilii_dataout <= wire_n00lill_dataout AND NOT(niOO0i0li); + wire_n00iliii_dataout <= wire_n00ililO_o(2) OR NOT(niOll1liO); + wire_n00iliil_dataout <= wire_n00ililO_o(3) OR NOT(niOll1liO); + wire_n00iliiO_dataout <= wire_n00ililO_o(4) OR NOT(niOll1liO); + wire_n00ilil_dataout <= wire_n00lilO_dataout AND NOT(niOO0i0li); + wire_n00ilili_dataout <= n00iilli AND niOll1lil; + wire_n00iliO_dataout <= wire_n00liOi_dataout AND NOT(niOO0i0li); + wire_n00illi_dataout <= wire_n00liOl_dataout AND NOT(niOO0i0li); + wire_n00illl_dataout <= wire_n00liOO_dataout AND NOT(niOO0i0li); + wire_n00illO_dataout <= wire_n00ll1i_dataout AND NOT(niOO0i0li); + wire_n00ilOi_dataout <= wire_n00ll1l_dataout AND NOT(niOO0i0li); + wire_n00ilOl_dataout <= wire_n00ll1O_dataout AND NOT(niOO0i0li); + wire_n00ilOO_dataout <= wire_n00ll0i_dataout AND NOT(niOO0i0li); + wire_n00iO00i_dataout <= wire_n00l1i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO00l_dataout <= ((niOll01ll OR niOll01li) OR niOll01iO) AND NOT(wire_niO01lOO_dataout); + wire_n00iO00O_dataout <= (n00lO0ii AND (niOll000i OR niOll01OO)) AND NOT(wire_niO01lOO_dataout); + wire_n00iO01l_dataout <= wire_n00l1i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO01O_dataout <= wire_n00l1i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0i_dataout <= wire_n00llil_dataout AND NOT(niOO0i0iO); + wire_n00iO0ii_dataout <= wire_n00iOO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0il_dataout <= wire_n00iOO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0iO_dataout <= wire_n00iOO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0l_dataout <= wire_n00lliO_dataout AND NOT(niOO0i0iO); + wire_n00iO0li_dataout <= wire_n00iOO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0ll_dataout <= wire_n00iOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0lO_dataout <= wire_n00iOOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0O_dataout <= wire_n00llli_dataout AND NOT(niOO0i0iO); + wire_n00iO0Oi_dataout <= wire_n00iOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0Ol_dataout <= wire_n00iOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO0OO_dataout <= wire_n00l1i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iO1i_dataout <= wire_n00ll0l_dataout AND NOT(niOO0i0li); + wire_n00iO1l_dataout <= wire_n00ll0O_dataout AND NOT(niOO0i0li); + wire_n00iO1O_dataout <= wire_n00llii_dataout AND NOT(niOO0i0li); + wire_n00iOi0i_dataout <= wire_n00l1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOi0l_dataout <= wire_n00l1iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOi0O_dataout <= wire_n00l1ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOi1i_dataout <= wire_n00l1i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOi1l_dataout <= wire_n00l1i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOi1O_dataout <= wire_n00l1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOii_dataout <= wire_n00llll_dataout AND NOT(niOO0i0iO); + wire_n00iOiii_dataout <= wire_n00l1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOiil_dataout <= wire_n00l1ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOiiO_dataout <= wire_n00l1iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOil_dataout <= wire_n00lllO_dataout AND NOT(niOO0i0iO); + wire_n00iOili_dataout <= wire_n00l1iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOill_dataout <= wire_n00l1iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOilO_dataout <= wire_n00l1l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOiO_dataout <= wire_n00llOi_dataout AND NOT(niOO0i0iO); + wire_n00iOiOi_dataout <= wire_n00l1l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOiOl_dataout <= wire_n00l1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOiOO_dataout <= wire_n00l1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOl0i_dataout <= wire_n00l100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOl0l_dataout <= wire_n00l100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOl0O_dataout <= wire_n00l100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOl1i_dataout <= wire_n00l1l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOl1l_dataout <= wire_n00l1l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOl1O_dataout <= wire_n00l101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOli_dataout <= wire_n00llOl_dataout AND NOT(niOO0i0iO); + wire_n00iOlii_dataout <= wire_n00l10ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOlil_dataout <= wire_n00l1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOliO_dataout <= wire_n00l10il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOll_dataout <= wire_n00llOO_dataout AND NOT(niOO0i0iO); + wire_n00iOlli_dataout <= wire_n00l10iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOlll_dataout <= wire_n00l10li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOllO_dataout <= wire_n00l10ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOlO_dataout <= wire_n00lO1i_dataout AND NOT(niOO0i0iO); + wire_n00iOlOi_dataout <= wire_n00l10lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOlOl_dataout <= wire_n00l10Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOlOO_dataout <= wire_n00l10Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOO0i_dataout <= wire_n00iOOlO_dataout AND NOT(niOll1O1i); + wire_n00iOO0l_dataout <= wire_n00iOOOi_dataout AND NOT(niOll1O1i); + wire_n00iOO0O_dataout <= wire_n00iOOOl_dataout AND NOT(niOll1O1i); + wire_n00iOO1i_dataout <= wire_n00l10OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOO1l_dataout <= wire_n00l1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00iOO1O_dataout <= wire_n00iOOll_dataout AND NOT(niOll1O1i); + wire_n00iOOi_dataout <= wire_n00lO1l_dataout AND NOT(niOO0i0iO); + wire_n00iOOii_dataout <= wire_n00iOOOO_dataout AND NOT(niOll1O1i); + wire_n00iOOil_dataout <= wire_n00l111i_dataout AND NOT(niOll1O1i); + wire_n00iOOiO_dataout <= wire_n00l111l_dataout AND NOT(niOll1O1i); + wire_n00iOOl_dataout <= wire_n00lO1O_dataout AND NOT(niOO0i0iO); + wire_n00iOOli_dataout <= wire_n00l111O_dataout AND NOT(niOll1O1i); + wire_n00iOOll_dataout <= wire_n00l110i_dataout OR niOll1lOO; + wire_n00iOOlO_dataout <= wire_n00l110l_dataout AND NOT(niOll1lOO); + wire_n00iOOO_dataout <= wire_n00lO0i_dataout AND NOT(niOO0i0iO); + wire_n00iOOOi_dataout <= wire_n00l110O_dataout AND NOT(niOll1lOO); + wire_n00iOOOl_dataout <= wire_n00l11ii_dataout AND NOT(niOll1lOO); + wire_n00iOOOO_dataout <= wire_n00l11il_dataout AND NOT(niOll1lOO); + wire_n00l00i_dataout <= wire_n00O1il_dataout AND NOT(niOO0i0iO); + wire_n00l00l_dataout <= wire_n00O1iO_dataout AND NOT(niOO0i0iO); + wire_n00l00O_dataout <= wire_n00O1li_dataout AND NOT(niOO0i0iO); + wire_n00l010i_dataout <= n00l0lOi WHEN n00l0i0i = '1' ELSE n00iO10l; + wire_n00l010l_dataout <= n00l0lOl WHEN n00l0i0i = '1' ELSE n00iO10O; + wire_n00l010O_dataout <= n00l0lOO WHEN n00l0i0i = '1' ELSE n00iO1ii; + wire_n00l011i_dataout <= n00l0lli WHEN n00l0i0i = '1' ELSE n00iO11l; + wire_n00l011l_dataout <= n00l0lll WHEN n00l0i0i = '1' ELSE n00iO11O; + wire_n00l011O_dataout <= n00l0llO WHEN n00l0i0i = '1' ELSE n00iO10i; + wire_n00l01i_dataout <= wire_n00O10l_dataout AND NOT(niOO0i0iO); + wire_n00l01ii_dataout <= n00l0O1i WHEN n00l0i0i = '1' ELSE n00iO1il; + wire_n00l01il_dataout <= n00l0O1l WHEN n00l0i0i = '1' ELSE n00iO1iO; + wire_n00l01iO_dataout <= n00l0O1O WHEN n00l0i0i = '1' ELSE n00iO1li; + wire_n00l01l_dataout <= wire_n00O10O_dataout AND NOT(niOO0i0iO); + wire_n00l01li_dataout <= n00l0O0i WHEN n00l0i0i = '1' ELSE n00iO1ll; + wire_n00l01ll_dataout <= n00l0O0l WHEN n00l0i0i = '1' ELSE n00iO1lO; + wire_n00l01lO_dataout <= n00l0O0O WHEN n00l0i0i = '1' ELSE n00iO1Oi; + wire_n00l01O_dataout <= wire_n00O1ii_dataout AND NOT(niOO0i0iO); + wire_n00l01Oi_dataout <= n00l0Oii WHEN n00l0i0i = '1' ELSE n00iO1Ol; + wire_n00l01Ol_dataout <= n00l0Oil WHEN n00l0i0i = '1' ELSE n00iO1OO; + wire_n00l0ii_dataout <= wire_n00O1ll_dataout AND NOT(niOO0i0iO); + wire_n00l0il_dataout <= wire_n00O1lO_dataout AND NOT(niOO0i0iO); + wire_n00l0iO_dataout <= wire_n00O1Oi_dataout AND NOT(niOO0i0iO); + wire_n00l0li_dataout <= wire_n00O1Ol_dataout AND NOT(niOO0i0iO); + wire_n00l0ll_dataout <= wire_n00O1OO_dataout AND NOT(niOO0i0iO); + wire_n00l0lO_dataout <= wire_n00O01i_dataout AND NOT(niOO0i0iO); + wire_n00l0Oi_dataout <= wire_n00O01l_dataout AND NOT(niOO0i0iO); + wire_n00l0Ol_dataout <= wire_n00O01O_dataout AND NOT(niOO0i0iO); + wire_n00l0OO_dataout <= wire_n00O00i_dataout AND NOT(niOO0i0iO); + wire_n00l0OOl_dataout <= wire_n00ll1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00l0OOO_dataout <= wire_n00ll11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00l100i_dataout <= n00iO11l WHEN niOlO1O0i = '1' ELSE wire_n00l011i_dataout; + wire_n00l100l_dataout <= n00iO11O WHEN niOlO1O0i = '1' ELSE wire_n00l011l_dataout; + wire_n00l100O_dataout <= n00iO10i WHEN niOlO1O0i = '1' ELSE wire_n00l011O_dataout; + wire_n00l101O_dataout <= n00iO11i WHEN niOlO1O0i = '1' ELSE wire_n00l1OOO_dataout; + wire_n00l10i_dataout <= wire_n00lOil_dataout AND NOT(niOO0i0iO); + wire_n00l10ii_dataout <= n00iO10l WHEN niOlO1O0i = '1' ELSE wire_n00l010i_dataout; + wire_n00l10il_dataout <= n00iO1ii WHEN niOlO1O0i = '1' ELSE wire_n00l010O_dataout; + wire_n00l10iO_dataout <= n00iO1il WHEN niOlO1O0i = '1' ELSE wire_n00l01ii_dataout; + wire_n00l10l_dataout <= wire_n00lOiO_dataout AND NOT(niOO0i0iO); + wire_n00l10li_dataout <= n00iO1iO WHEN niOlO1O0i = '1' ELSE wire_n00l01il_dataout; + wire_n00l10ll_dataout <= n00iO1li WHEN niOlO1O0i = '1' ELSE wire_n00l01iO_dataout; + wire_n00l10lO_dataout <= n00iO1ll WHEN niOlO1O0i = '1' ELSE wire_n00l01li_dataout; + wire_n00l10O_dataout <= wire_n00lOli_dataout AND NOT(niOO0i0iO); + wire_n00l10Oi_dataout <= n00iO1lO WHEN niOlO1O0i = '1' ELSE wire_n00l01ll_dataout; + wire_n00l10Ol_dataout <= n00iO1Oi WHEN niOlO1O0i = '1' ELSE wire_n00l01lO_dataout; + wire_n00l10OO_dataout <= n00iO1Ol WHEN niOlO1O0i = '1' ELSE wire_n00l01Oi_dataout; + wire_n00l110i_dataout <= wire_n00l11lO_o(0) WHEN niOll1lOi = '1' ELSE n00ill0l; + wire_n00l110l_dataout <= wire_n00l11lO_o(1) WHEN niOll1lOi = '1' ELSE n00ill0O; + wire_n00l110O_dataout <= wire_n00l11lO_o(2) WHEN niOll1lOi = '1' ELSE n00illii; + wire_n00l111i_dataout <= wire_n00l11iO_dataout AND NOT(niOll1lOO); + wire_n00l111l_dataout <= wire_n00l11li_dataout AND NOT(niOll1lOO); + wire_n00l111O_dataout <= wire_n00l11ll_dataout AND NOT(niOll1lOO); + wire_n00l11i_dataout <= wire_n00lO0l_dataout AND NOT(niOO0i0iO); + wire_n00l11ii_dataout <= wire_n00l11lO_o(3) WHEN niOll1lOi = '1' ELSE n00illil; + wire_n00l11il_dataout <= wire_n00l11lO_o(4) WHEN niOll1lOi = '1' ELSE n00illiO; + wire_n00l11iO_dataout <= wire_n00l11lO_o(5) WHEN niOll1lOi = '1' ELSE n00illli; + wire_n00l11l_dataout <= wire_n00lO0O_dataout AND NOT(niOO0i0iO); + wire_n00l11li_dataout <= wire_n00l11lO_o(6) WHEN niOll1lOi = '1' ELSE n00illll; + wire_n00l11ll_dataout <= wire_n00l11lO_o(7) WHEN niOll1lOi = '1' ELSE n00illlO; + wire_n00l11O_dataout <= wire_n00lOii_dataout AND NOT(niOO0i0iO); + wire_n00l1i0i_dataout <= wire_n00l1llO_dataout AND NOT(niOlO1O0i); + wire_n00l1i0l_dataout <= wire_n00l1lOi_dataout AND NOT(niOlO1O0i); + wire_n00l1i0O_dataout <= wire_n00l1lOl_dataout AND NOT(niOlO1O0i); + wire_n00l1i1i_dataout <= wire_n00l1liO_dataout AND NOT(niOlO1O0i); + wire_n00l1i1l_dataout <= wire_n00l1lli_dataout AND NOT(niOlO1O0i); + wire_n00l1i1O_dataout <= wire_n00l1lll_dataout AND NOT(niOlO1O0i); + wire_n00l1ii_dataout <= wire_n00lOll_dataout AND NOT(niOO0i0iO); + wire_n00l1iii_dataout <= wire_n00l1lOO_dataout AND NOT(niOlO1O0i); + wire_n00l1iil_dataout <= wire_n00l1O1i_dataout AND NOT(niOlO1O0i); + wire_n00l1iiO_dataout <= wire_n00l1O1l_dataout AND NOT(niOlO1O0i); + wire_n00l1il_dataout <= wire_n00lOlO_dataout AND NOT(niOO0i0iO); + wire_n00l1ili_dataout <= wire_n00l1O1O_dataout AND NOT(niOlO1O0i); + wire_n00l1ill_dataout <= wire_n00l1O0i_dataout AND NOT(niOlO1O0i); + wire_n00l1ilO_dataout <= wire_n00l1O0l_dataout AND NOT(niOlO1O0i); + wire_n00l1iO_dataout <= wire_n00lOOi_dataout AND NOT(niOO0i0iO); + wire_n00l1iOi_dataout <= wire_n00l1O0O_dataout AND NOT(niOlO1O0i); + wire_n00l1iOl_dataout <= wire_n00l1Oii_dataout AND NOT(niOlO1O0i); + wire_n00l1iOO_dataout <= wire_n00l1Oil_dataout AND NOT(niOlO1O0i); + wire_n00l1l0i_dataout <= wire_n00l1OlO_dataout AND NOT(niOlO1O0i); + wire_n00l1l0l_dataout <= wire_n00l1OOi_dataout AND NOT(niOlO1O0i); + wire_n00l1l0O_dataout <= wire_n00l1OOl_dataout AND NOT(niOlO1O0i); + wire_n00l1l1i_dataout <= wire_n00l1OiO_dataout AND NOT(niOlO1O0i); + wire_n00l1l1l_dataout <= wire_n00l1Oli_dataout AND NOT(niOlO1O0i); + wire_n00l1l1O_dataout <= wire_n00l1Oll_dataout AND NOT(niOlO1O0i); + wire_n00l1li_dataout <= wire_n00lOOl_dataout AND NOT(niOO0i0iO); + wire_n00l1lii_dataout <= wire_n00l010l_dataout AND NOT(niOlO1O0i); + wire_n00l1lil_dataout <= wire_n00l01Ol_dataout AND NOT(niOlO1O0i); + wire_n00l1liO_dataout <= n00iO01i WHEN n00l0i0i = '1' ELSE n00il1OO; + wire_n00l1ll_dataout <= wire_n00lOOO_dataout AND NOT(niOO0i0iO); + wire_n00l1lli_dataout <= n00l0i1i WHEN n00l0i0i = '1' ELSE n00ill1i; + wire_n00l1lll_dataout <= n00l0i1l WHEN n00l0i0i = '1' ELSE n00ill1l; + wire_n00l1llO_dataout <= n00l0i0O WHEN n00l0i0i = '1' ELSE n00illOi; + wire_n00l1lO_dataout <= wire_n00O11i_dataout AND NOT(niOO0i0iO); + wire_n00l1lOi_dataout <= n00l0iii WHEN n00l0i0i = '1' ELSE n00illOl; + wire_n00l1lOl_dataout <= n00l0iil WHEN n00l0i0i = '1' ELSE n00illOO; + wire_n00l1lOO_dataout <= n00l0iiO WHEN n00l0i0i = '1' ELSE n00ilO1i; + wire_n00l1O0i_dataout <= n00l0iOi WHEN n00l0i0i = '1' ELSE n00ilO0l; + wire_n00l1O0l_dataout <= n00l0iOl WHEN n00l0i0i = '1' ELSE n00ilO0O; + wire_n00l1O0O_dataout <= n00l0iOO WHEN n00l0i0i = '1' ELSE n00ilOii; + wire_n00l1O1i_dataout <= n00l0ili WHEN n00l0i0i = '1' ELSE n00ilO1l; + wire_n00l1O1l_dataout <= n00l0ill WHEN n00l0i0i = '1' ELSE n00ilO1O; + wire_n00l1O1O_dataout <= n00l0ilO WHEN n00l0i0i = '1' ELSE n00ilO0i; + wire_n00l1Oi_dataout <= wire_n00O11l_dataout AND NOT(niOO0i0iO); + wire_n00l1Oii_dataout <= n00l0l1i WHEN n00l0i0i = '1' ELSE n00ilOil; + wire_n00l1Oil_dataout <= n00l0l1l WHEN n00l0i0i = '1' ELSE n00ilOiO; + wire_n00l1OiO_dataout <= n00l0l1O WHEN n00l0i0i = '1' ELSE n00ilOli; + wire_n00l1Ol_dataout <= wire_n00O11O_dataout AND NOT(niOO0i0iO); + wire_n00l1Oli_dataout <= n00l0l0i WHEN n00l0i0i = '1' ELSE n00ilOll; + wire_n00l1Oll_dataout <= n00l0l0l WHEN n00l0i0i = '1' ELSE n00ilOlO; + wire_n00l1OlO_dataout <= n00l0l0O WHEN n00l0i0i = '1' ELSE n00ilOOi; + wire_n00l1OO_dataout <= wire_n00O10i_dataout AND NOT(niOO0i0iO); + wire_n00l1OOi_dataout <= n00l0lii WHEN n00l0i0i = '1' ELSE n00ilOOl; + wire_n00l1OOl_dataout <= n00l0lil WHEN n00l0i0i = '1' ELSE n00ilOOO; + wire_n00l1OOO_dataout <= n00l0liO WHEN n00l0i0i = '1' ELSE n00iO11i; + wire_n00li00i_dataout <= wire_n00ll00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li00l_dataout <= wire_n00ll1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li00O_dataout <= wire_n00ll1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li01i_dataout <= wire_n00ll01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li01l_dataout <= wire_n00ll01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li01O_dataout <= wire_n00ll00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0i_dataout <= wire_n00O0il_dataout AND NOT(niOO0i0iO); + wire_n00li0ii_dataout <= wire_n00ll1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0il_dataout <= wire_n00ll00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0iO_dataout <= wire_n00ll0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0l_dataout <= wire_n00O0iO_dataout AND NOT(niOO0i0iO); + wire_n00li0li_dataout <= wire_n00ll0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0ll_dataout <= wire_n00ll0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0lO_dataout <= wire_n00ll0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0O_dataout <= wire_n00O0li_dataout AND NOT(niOO0i0iO); + wire_n00li0Oi_dataout <= wire_n00ll0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0Ol_dataout <= wire_n00ll0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li0OO_dataout <= wire_n00ll0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li10i_dataout <= wire_n00lilli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li10l_dataout <= wire_n00liOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li10O_dataout <= wire_n00liOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li11i_dataout <= wire_n00ll1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li11l_dataout <= ((wire_w_lg_niOll01OO15574w(0) AND (wire_w_lg_niOll010l15575w(0) AND wire_w_lg_w_lg_niOll000i15438w15576w(0))) AND (wire_w_lg_w_lg_w_lg_niOll1O0O15579w15583w15584w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n00li11O_dataout <= (wire_w_lg_w_lg_w_lg_niOll011l15568w15570w15571w(0) AND wire_niO01ill_w_lg_n00l0i0l15572w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n00li1i_dataout <= wire_n00O00l_dataout AND NOT(niOO0i0iO); + wire_n00li1ii_dataout <= wire_n00ll11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1il_dataout <= wire_n00ll10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1iO_dataout <= wire_n00ll10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1l_dataout <= wire_n00O00O_dataout AND NOT(niOO0i0iO); + wire_n00li1li_dataout <= wire_n00ll10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1ll_dataout <= wire_n00ll1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1lO_dataout <= wire_n00ll1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1O_dataout <= wire_n00O0ii_dataout AND NOT(niOO0i0iO); + wire_n00li1Oi_dataout <= wire_n00ll1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1Ol_dataout <= wire_n00ll1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00li1OO_dataout <= wire_n00ll01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lii0i_dataout <= wire_n00lli1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lii0l_dataout <= wire_n00lli1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lii0O_dataout <= wire_n00lli0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lii1i_dataout <= wire_n00ll0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lii1l_dataout <= wire_n00ll0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lii1O_dataout <= wire_n00lli1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00liii_dataout <= wire_n00O0ll_dataout AND NOT(niOO0i0iO); + wire_n00liiii_dataout <= wire_n00lli0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00liiil_dataout <= wire_n00lli0O_dataout OR wire_niO01lOO_dataout; + wire_n00liiiO_dataout <= wire_n00lliii_dataout OR wire_niO01lOO_dataout; + wire_n00liil_dataout <= wire_n00O0lO_dataout AND NOT(niOO0i0iO); + wire_n00liili_dataout <= wire_n00lliil_dataout OR wire_niO01lOO_dataout; + wire_n00liill_dataout <= wire_n00lliiO_dataout OR wire_niO01lOO_dataout; + wire_n00liiO_dataout <= wire_n00O0Oi_dataout AND NOT(niOO0i0iO); + wire_n00lili_dataout <= wire_n00O0Ol_dataout AND NOT(niOO0i0iO); + wire_n00lill_dataout <= wire_n00O0OO_dataout AND NOT(niOO0i0iO); + wire_n00lilli_dataout <= wire_n00lilll_dataout AND NOT(niOll010l); + wire_n00lilll_dataout <= wire_n00lillO_dataout OR (wire_w_lg_niOll01Oi15557w(0) AND wire_w_lg_w_lg_niOll01lO15546w15558w(0)); + wire_n00lillO_dataout <= wire_n00lilOi_dataout OR (wire_w_lg_niOll01lO15546w(0) AND (wire_w_lg_w_lg_niOll1OiO15548w15549w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n00l0OlO15551w15553w15554w(0))); + wire_n00lilO_dataout <= wire_n00Oi1i_dataout AND NOT(niOO0i0iO); + wire_n00lilOi_dataout <= wire_n00lilOl_dataout OR (wire_w_lg_niOll01lO15546w(0) AND niOll1Oil); + wire_n00lilOl_dataout <= n00l0i0l OR (wire_n00liO0O_o AND (((niOll011l XOR n00l0iii) OR (niOll1OOl XOR n00l0i0O)) OR (NOT (n00l0iii XOR n00l0i0O)))); + wire_n00liOi_dataout <= wire_n00Oi1l_dataout AND NOT(niOO0i0iO); + wire_n00liOl_dataout <= wire_n00Oi1O_dataout AND NOT(niOO0i0iO); + wire_n00liOO_dataout <= wire_n00Oi0i_dataout AND NOT(niOO0i0iO); + wire_n00liOOl_dataout <= niOll1OOl WHEN wire_n00ll11l_o = '1' ELSE n00l0i0O; + wire_n00liOOO_dataout <= niOll011l WHEN wire_n00ll11l_o = '1' ELSE n00l0iii; + wire_n00ll00i_dataout <= wire_niO100li_dataout WHEN niOll1OiO = '1' ELSE n00l0l0i; + wire_n00ll00l_dataout <= wire_niO100ll_dataout WHEN niOll1OiO = '1' ELSE n00l0l0l; + wire_n00ll00O_dataout <= wire_niO1000i_dataout WHEN niOll1OlO = '1' ELSE n00l0liO; + wire_n00ll01i_dataout <= wire_niO100ii_dataout WHEN niOll1OiO = '1' ELSE n00l0l1i; + wire_n00ll01l_dataout <= wire_niO100il_dataout WHEN niOll1OiO = '1' ELSE n00l0l1l; + wire_n00ll01O_dataout <= wire_niO100iO_dataout WHEN niOll1OiO = '1' ELSE n00l0l1O; + wire_n00ll0i_dataout <= wire_n00Oiil_dataout AND NOT(niOO0i0iO); + wire_n00ll0ii_dataout <= wire_niO1000l_dataout WHEN niOll1OlO = '1' ELSE n00l0lli; + wire_n00ll0il_dataout <= wire_niO1000O_dataout WHEN niOll1OlO = '1' ELSE n00l0lll; + wire_n00ll0iO_dataout <= wire_niO100ii_dataout WHEN niOll1OlO = '1' ELSE n00l0llO; + wire_n00ll0l_dataout <= wire_n00OiiO_dataout AND NOT(niOO0i0iO); + wire_n00ll0li_dataout <= wire_niO100il_dataout WHEN niOll1OlO = '1' ELSE n00l0lOi; + wire_n00ll0ll_dataout <= niOll01Oi WHEN niOll1OlO = '1' ELSE n00l0lOl; + wire_n00ll0lO_dataout <= wire_niO1000i_dataout WHEN niOll010l = '1' ELSE n00l0lOO; + wire_n00ll0O_dataout <= wire_n00Oili_dataout AND NOT(niOO0i0iO); + wire_n00ll0Oi_dataout <= wire_niO1000l_dataout WHEN niOll010l = '1' ELSE n00l0O1i; + wire_n00ll0Ol_dataout <= wire_niO1000O_dataout WHEN niOll010l = '1' ELSE n00l0O1l; + wire_n00ll0OO_dataout <= wire_niO100ii_dataout WHEN niOll010l = '1' ELSE n00l0O1O; + wire_n00ll10i_dataout <= wire_niO1000i_dataout WHEN niOll1Oii = '1' ELSE n00l0iiO; + wire_n00ll10l_dataout <= wire_niO1000l_dataout WHEN niOll1Oii = '1' ELSE n00l0ili; + wire_n00ll10O_dataout <= wire_niO1000O_dataout WHEN niOll1Oii = '1' ELSE n00l0ill; + wire_n00ll11i_dataout <= (wire_niO1001l_dataout AND (niOll011i OR niOll010i)) WHEN wire_n00ll11l_o = '1' ELSE n00l0iil; + wire_n00ll11O_dataout <= wire_niO100il_dataout WHEN niOll1Oii = '1' ELSE n00l0i1i; + wire_n00ll1i_dataout <= wire_n00Oi0l_dataout AND NOT(niOO0i0iO); + wire_n00ll1ii_dataout <= wire_niO100ii_dataout WHEN niOll1Oii = '1' ELSE n00l0ilO; + wire_n00ll1il_dataout <= wire_niO100ll_dataout WHEN niOll1Oil = '1' ELSE n00l0i1l; + wire_n00ll1iO_dataout <= wire_niO100li_dataout WHEN niOll1Oil = '1' ELSE n00iO01i; + wire_n00ll1l_dataout <= wire_n00Oi0O_dataout AND NOT(niOO0i0iO); + wire_n00ll1li_dataout <= wire_niO1000l_dataout WHEN niOll1Oil = '1' ELSE n00l0l0O; + wire_n00ll1ll_dataout <= wire_niO1000O_dataout WHEN niOll1Oil = '1' ELSE n00l0lii; + wire_n00ll1lO_dataout <= n00l0lil AND NOT(niOll1Oil); + wire_n00ll1O_dataout <= wire_n00Oiii_dataout AND NOT(niOO0i0iO); + wire_n00ll1Oi_dataout <= wire_niO1000i_dataout WHEN niOll1OiO = '1' ELSE n00l0iOi; + wire_n00ll1Ol_dataout <= wire_niO1000l_dataout WHEN niOll1OiO = '1' ELSE n00l0iOl; + wire_n00ll1OO_dataout <= wire_niO1000O_dataout WHEN niOll1OiO = '1' ELSE n00l0iOO; + wire_n00lli0i_dataout <= wire_niO100ll_dataout WHEN niOll010l = '1' ELSE n00l0Oii; + wire_n00lli0l_dataout <= niOll01Oi WHEN niOll010l = '1' ELSE n00l0Oil; + wire_n00lli0O_dataout <= wire_n00llili_dataout OR niOll010l; + wire_n00lli1i_dataout <= wire_niO100il_dataout WHEN niOll010l = '1' ELSE n00l0O0i; + wire_n00lli1l_dataout <= wire_niO100iO_dataout WHEN niOll010l = '1' ELSE n00l0O0l; + wire_n00lli1O_dataout <= wire_niO100li_dataout WHEN niOll010l = '1' ELSE n00l0O0O; + wire_n00llii_dataout <= wire_n00Oill_dataout AND NOT(niOO0i0iO); + wire_n00lliii_dataout <= wire_n00llill_dataout AND NOT(niOll010l); + wire_n00lliil_dataout <= wire_n00llilO_dataout OR niOll010l; + wire_n00lliiO_dataout <= wire_n00lliOi_dataout OR niOll010l; + wire_n00llil_dataout <= wire_n00OilO_dataout AND NOT(niOO0i0il); + wire_n00llili_dataout <= wire_n00lliOl_dataout WHEN wire_w_lg_niOll1Oli15508w(0) = '1' ELSE n00l0OiO; + wire_n00llill_dataout <= wire_n00lliOO_dataout WHEN wire_w_lg_niOll1Oli15508w(0) = '1' ELSE n00l0Oli; + wire_n00llilO_dataout <= wire_n00lll1i_dataout WHEN wire_w_lg_niOll1Oli15508w(0) = '1' ELSE n00l0Oll; + wire_n00lliO_dataout <= wire_n00OiOi_dataout AND NOT(niOO0i0il); + wire_n00lliOi_dataout <= wire_n00lll1l_dataout WHEN wire_w_lg_niOll1Oli15508w(0) = '1' ELSE n00l0OlO; + wire_n00lliOl_dataout <= wire_n00lll1O_o(1) AND niOll1Oll; + wire_n00lliOO_dataout <= wire_n00lll1O_o(2) AND niOll1Oll; + wire_n00lll1i_dataout <= wire_n00lll1O_o(3) AND niOll1Oll; + wire_n00lll1l_dataout <= wire_n00lll1O_o(4) AND niOll1Oll; + wire_n00llli_dataout <= wire_n00OiOl_dataout AND NOT(niOO0i0il); + wire_n00llll_dataout <= wire_n00OiOO_dataout AND NOT(niOO0i0il); + wire_n00lllO_dataout <= wire_n00Ol1i_dataout AND NOT(niOO0i0il); + wire_n00llOi_dataout <= wire_n00Ol1l_dataout AND NOT(niOO0i0il); + wire_n00llOl_dataout <= wire_n00Ol1O_dataout AND NOT(niOO0i0il); + wire_n00llOO_dataout <= wire_n00Ol0i_dataout AND NOT(niOO0i0il); + wire_n00llOOO_dataout <= wire_n00lO10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lO0i_dataout <= wire_n00Olil_dataout AND NOT(niOO0i0il); + wire_n00lO0iO_dataout <= (niOll000i AND n00lO1OO) AND NOT(wire_niO01lOO_dataout); + wire_n00lO0l_dataout <= wire_n00OliO_dataout AND NOT(niOO0i0il); + wire_n00lO0li_dataout <= (niOll000i AND n00lO01i) AND NOT(wire_niO01lOO_dataout); + wire_n00lO0ll_dataout <= (wire_w_lg_w_lg_w_lg_niOll001l15435w15436w15437w(0) OR (wire_w_lg_niOll000i15438w(0) AND (wire_w_lg_niOll001l15439w(0) AND (n00lO00i AND niOll01il)))) AND NOT(wire_niO01lOO_dataout); + wire_n00lO0lO_dataout <= niOll01ll AND NOT(wire_niO01lOO_dataout); + wire_n00lO0O_dataout <= wire_n00Olli_dataout AND NOT(niOO0i0il); + wire_n00lO0Oi_dataout <= (niOll001l AND n00lO0ii) AND NOT(wire_niO01lOO_dataout); + wire_n00lO0Ol_dataout <= n00lO00i AND NOT(wire_niO01lOO_dataout); + wire_n00lO0OO_dataout <= niOll001l AND NOT(wire_niO01lOO_dataout); + wire_n00lO10i_dataout <= wire_n00lO1il_dataout AND NOT(niOll010O); + wire_n00lO10l_dataout <= wire_n00lO1iO_dataout AND NOT(niOll010O); + wire_n00lO10O_dataout <= wire_n00lO1li_dataout AND NOT(niOll010O); + wire_n00lO11i_dataout <= wire_n00lO10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lO11l_dataout <= wire_n00lO10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lO11O_dataout <= wire_n00lO1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lO1i_dataout <= wire_n00Ol0l_dataout AND NOT(niOO0i0il); + wire_n00lO1ii_dataout <= wire_n00lO1ll_dataout AND NOT(niOll010O); + wire_n00lO1il_dataout <= wire_n00lO1lO_o(0) WHEN wire_niO01ill_w_lg_n00llOOi15464w(0) = '1' ELSE n00l0OOi; + wire_n00lO1iO_dataout <= wire_n00lO1lO_o(1) WHEN wire_niO01ill_w_lg_n00llOOi15464w(0) = '1' ELSE n00llOll; + wire_n00lO1l_dataout <= wire_n00Ol0O_dataout AND NOT(niOO0i0il); + wire_n00lO1li_dataout <= wire_n00lO1lO_o(2) WHEN wire_niO01ill_w_lg_n00llOOi15464w(0) = '1' ELSE n00llOlO; + wire_n00lO1ll_dataout <= wire_n00lO1lO_o(3) OR NOT(wire_niO01ill_w_lg_n00llOOi15464w(0)); + wire_n00lO1O_dataout <= wire_n00Olii_dataout AND NOT(niOO0i0il); + wire_n00lOi1i_dataout <= n00lO00O AND NOT(wire_niO01lOO_dataout); + wire_n00lOi1l_dataout <= n00lO0ii AND NOT(wire_niO01lOO_dataout); + wire_n00lOi1O_dataout <= niOll000i AND NOT(wire_niO01lOO_dataout); + wire_n00lOii_dataout <= wire_n00Olll_dataout AND NOT(niOO0i0il); + wire_n00lOil_dataout <= wire_n00OllO_dataout AND NOT(niOO0i0il); + wire_n00lOiO_dataout <= wire_n00OlOi_dataout AND NOT(niOO0i0il); + wire_n00lOli_dataout <= wire_n00OlOl_dataout AND NOT(niOO0i0il); + wire_n00lOll_dataout <= wire_n00OlOO_dataout AND NOT(niOO0i0il); + wire_n00lOllO_dataout <= wire_n00lOO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lOlO_dataout <= wire_n00OO1i_dataout AND NOT(niOO0i0il); + wire_n00lOlOi_dataout <= wire_n00lOO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lOlOl_dataout <= wire_n00lOO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lOlOO_dataout <= wire_n00lOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lOO0i_dataout <= wire_n00lOOll_dataout AND NOT(niOll00il); + wire_n00lOO0l_dataout <= wire_n00lOOlO_dataout AND NOT(niOll00il); + wire_n00lOO0O_dataout <= wire_n00lOOOi_dataout AND NOT(niOll00il); + wire_n00lOO1i_dataout <= wire_n00lOOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lOO1l_dataout <= wire_n00lOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lOO1O_dataout <= wire_n00lOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00lOOi_dataout <= wire_n00OO1l_dataout AND NOT(niOO0i0il); + wire_n00lOOii_dataout <= wire_n00lOOOl_dataout AND NOT(niOll00il); + wire_n00lOOil_dataout <= wire_n00lOOOO_dataout AND NOT(niOll00il); + wire_n00lOOiO_dataout <= wire_n00O111i_dataout AND NOT(niOll00il); + wire_n00lOOl_dataout <= wire_n00OO1O_dataout AND NOT(niOO0i0il); + wire_n00lOOli_dataout <= wire_n00O111l_dataout AND NOT(niOll00il); + wire_n00lOOll_dataout <= wire_n00O111O_o(0) WHEN niOll000O = '1' ELSE n00lO0il; + wire_n00lOOlO_dataout <= wire_n00O111O_o(1) WHEN niOll000O = '1' ELSE n00lOl0l; + wire_n00lOOO_dataout <= wire_n00OO0i_dataout AND NOT(niOO0i0il); + wire_n00lOOOi_dataout <= wire_n00O111O_o(2) WHEN niOll000O = '1' ELSE n00lOl0O; + wire_n00lOOOl_dataout <= wire_n00O111O_o(3) WHEN niOll000O = '1' ELSE n00lOlii; + wire_n00lOOOO_dataout <= wire_n00O111O_o(4) WHEN niOll000O = '1' ELSE n00lOlil; + wire_n00O000i_dataout <= wire_n00O000l_dataout OR n00OOlOi; + wire_n00O000l_dataout <= wire_n00O000O_dataout OR (wire_niO01ill_w_lg_n00OOlli15189w(0) AND (wire_n00O11il_dataout AND niOll0iiO)); + wire_n00O000O_dataout <= wire_n00O00il_dataout OR (wire_niO01ill_w_lg_n00OOlli15189w(0) AND (wire_n00O11il_dataout AND niOll0i1l)); + wire_n00O001l_dataout <= n00O1ili WHEN nlOllOlll = '1' ELSE wire_n00O001O_dataout; + wire_n00O001O_dataout <= wire_n00O000i_dataout OR niOll0iOO; + wire_n00O00i_dataout <= wire_n0i11il_dataout AND NOT(niOO0i0il); + wire_n00O00il_dataout <= wire_n00O00iO_dataout OR (wire_niO01ill_w_lg_n00OOlli15189w(0) AND wire_n00O11il_w_lg_dataout15332w(0)); + wire_n00O00iO_dataout <= wire_n00O00li_dataout OR (wire_niO01ill_w_lg_n00OOlli15189w(0) AND wire_n00O11il_w_lg_w_lg_w_lg_dataout15319w15325w15326w(0)); + wire_n00O00l_dataout <= wire_n0i11iO_dataout AND NOT(niOO0i0il); + wire_n00O00li_dataout <= n00O1ill AND nlOllOlll; + wire_n00O00O_dataout <= wire_n0i11li_dataout AND NOT(niOO0i0il); + wire_n00O010i_dataout <= wire_n00O01il_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O10Oi; + wire_n00O010l_dataout <= wire_n00O01il_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O10Ol; + wire_n00O010O_dataout <= wire_n00O01il_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O10OO; + wire_n00O011i_dataout <= wire_n00O01il_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O10li; + wire_n00O011l_dataout <= wire_n00O01il_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O10ll; + wire_n00O011O_dataout <= wire_n00O01il_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O10lO; + wire_n00O01i_dataout <= wire_n0i110l_dataout AND NOT(niOO0i0il); + wire_n00O01ii_dataout <= wire_n00O01il_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O1i1i; + wire_n00O01l_dataout <= wire_n0i110O_dataout AND NOT(niOO0i0il); + wire_n00O01lO_dataout <= wire_n00O01Oi_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15191w(0) AND wire_w_lg_niOll0lii15192w(0)); + wire_n00O01O_dataout <= wire_n0i11ii_dataout AND NOT(niOO0i0il); + wire_n00O01Oi_dataout <= n00O1i1l AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOll0lil15338w(0))); + wire_n00O0i0l_dataout <= wire_n00O0i0O_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n00OOllO AND n00O1i0l)) OR (n00OOllO AND n00O10lO)); + wire_n00O0i0O_dataout <= n00lOlll AND nlOllOlll; + wire_n00O0ii_dataout <= wire_n0i11ll_dataout AND NOT(niOO0i0il); + wire_n00O0il_dataout <= wire_n0i11lO_dataout AND NOT(niOO0i0il); + wire_n00O0ill_dataout <= wire_n000ll0O_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0l0l_dataout; + wire_n00O0ilO_dataout <= wire_n000ll0i_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0l0O_dataout; + wire_n00O0iO_dataout <= wire_n0i11Oi_dataout AND NOT(niOO0i0il); + wire_n00O0iOi_dataout <= wire_n000ll1l_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0lii_dataout; + wire_n00O0iOl_dataout <= wire_n000liOO_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0lil_dataout; + wire_n00O0iOO_dataout <= wire_n000liOi_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0liO_dataout; + wire_n00O0l0i_dataout <= n00OOlOO WHEN niOll0l0i = '1' ELSE wire_n00O0lOi_dataout; + wire_n00O0l0l_dataout <= wire_n00O0lOO_dataout AND NOT(niOll0l1l); + wire_n00O0l0O_dataout <= wire_n00O0O1i_dataout AND NOT(niOll0l1l); + wire_n00O0l1i_dataout <= wire_n000lili_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0lli_dataout; + wire_n00O0l1l_dataout <= wire_n000liil_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0lll_dataout; + wire_n00O0l1O_dataout <= wire_n000li0l_dataout WHEN niOll0l0i = '1' ELSE wire_n00O0llO_dataout; + wire_n00O0li_dataout <= wire_n0i11Ol_dataout AND NOT(niOO0i0il); + wire_n00O0lii_dataout <= wire_n00O0O1l_dataout OR niOll0l1l; + wire_n00O0lil_dataout <= wire_n00O0O1O_dataout OR niOll0l1l; + wire_n00O0liO_dataout <= wire_n00O0O0i_dataout OR niOll0l1l; + wire_n00O0ll_dataout <= wire_n0i11OO_dataout AND NOT(niOO0i0il); + wire_n00O0lli_dataout <= wire_n00O0O0l_dataout OR niOll0l1l; + wire_n00O0lll_dataout <= wire_n00O0O0O_dataout AND NOT(niOll0l1l); + wire_n00O0llO_dataout <= wire_n00O0Oii_dataout OR niOll0l1l; + wire_n00O0lO_dataout <= wire_n0i101i_dataout AND NOT(niOO0i0il); + wire_n00O0lOi_dataout <= wire_n00O0lOl_dataout OR niOll0l1l; + wire_n00O0lOl_dataout <= wire_n00Oi11i_dataout AND NOT(niOll0iOl); + wire_n00O0lOO_dataout <= wire_n00O0Oil_dataout AND NOT(niOll0iOl); + wire_n00O0O0i_dataout <= wire_n00O0OlO_dataout AND NOT(niOll0iOl); + wire_n00O0O0l_dataout <= wire_n00O0OOi_dataout AND NOT(niOll0iOl); + wire_n00O0O0O_dataout <= wire_n00O0OOl_dataout AND NOT(niOll0iOl); + wire_n00O0O1i_dataout <= wire_n00O0OiO_dataout AND NOT(niOll0iOl); + wire_n00O0O1l_dataout <= wire_n00O0Oli_dataout AND NOT(niOll0iOl); + wire_n00O0O1O_dataout <= wire_n00O0Oll_dataout AND NOT(niOll0iOl); + wire_n00O0Oi_dataout <= wire_n0i101l_dataout AND NOT(niOO0i0il); + wire_n00O0Oii_dataout <= wire_n00O0OOO_dataout AND NOT(niOll0iOl); + wire_n00O0Oil_dataout <= wire_n00Oi11l_dataout AND NOT(niOll0ilO); + wire_n00O0OiO_dataout <= wire_n00Oi11O_dataout AND NOT(niOll0ilO); + wire_n00O0Ol_dataout <= wire_n0i101O_dataout AND NOT(niOO0i0il); + wire_n00O0Oli_dataout <= wire_n00Oi10i_dataout OR niOll0ilO; + wire_n00O0Oll_dataout <= wire_n00Oi10l_dataout OR niOll0ilO; + wire_n00O0OlO_dataout <= wire_n00Oi10O_dataout OR niOll0ilO; + wire_n00O0OO_dataout <= wire_n0i100i_dataout AND NOT(niOO0i0il); + wire_n00O0OOi_dataout <= wire_n00Oi1ii_dataout OR niOll0ilO; + wire_n00O0OOl_dataout <= wire_n00Oi1il_dataout OR niOll0ilO; + wire_n00O0OOO_dataout <= wire_n00Oi1iO_dataout AND NOT(niOll0ilO); + wire_n00O10i_dataout <= wire_n00OOil_dataout AND NOT(niOO0i0il); + wire_n00O10l_dataout <= wire_n00OOiO_dataout AND NOT(niOO0i0il); + wire_n00O10O_dataout <= wire_n00OOli_dataout AND NOT(niOO0i0il); + wire_n00O111i_dataout <= wire_n00O111O_o(5) WHEN niOll000O = '1' ELSE n00lOliO; + wire_n00O111l_dataout <= wire_n00O111O_o(6) WHEN niOll000O = '1' ELSE n00lOlli; + wire_n00O11i_dataout <= wire_n00OO0l_dataout AND NOT(niOO0i0il); + wire_n00O11il_dataout <= n00O1i1l AND (((NOT (wire_niili1Ol_dataout XOR n00O10Ol)) AND (NOT (wire_niili1OO_dataout XOR n00O10OO))) AND (NOT (n1101l1i XOR n00O1i1i))); + wire_n00O11il_w_lg_w_lg_w_lg_dataout15319w15325w15326w(0) <= wire_n00O11il_w_lg_w_lg_dataout15319w15325w(0) AND n00O1i1l; + wire_n00O11il_w_lg_w_lg_dataout15319w15325w(0) <= wire_n00O11il_w_lg_dataout15319w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n00O10lO15320w15322w15324w(0); + wire_n00O11il_w_lg_dataout15332w(0) <= wire_n00O11il_dataout AND wire_niO01ill_w15331w(0); + wire_n00O11il_w_lg_dataout15319w(0) <= NOT wire_n00O11il_dataout; + wire_n00O11iO_dataout <= n00O1iiO AND (n00O1i1O AND niOll00iO); + wire_n00O11l_dataout <= wire_n00OO0O_dataout AND NOT(niOO0i0il); + wire_n00O11ll_dataout <= n00O1iiO AND ((NOT (n00O1i0l XOR n00O1i0i)) AND niOll00iO); + wire_n00O11O_dataout <= wire_n00OOii_dataout AND NOT(niOO0i0il); + wire_n00O11Ol_dataout <= n00lOlll AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllOlll); + wire_n00O1ii_dataout <= wire_n00OOll_dataout AND NOT(niOO0i0il); + wire_n00O1il_dataout <= wire_n00OOlO_dataout AND NOT(niOO0i0il); + wire_n00O1ilO_dataout <= wire_n00O0i0l_dataout OR wire_niO01lOO_dataout; + wire_n00O1iO_dataout <= wire_n00OOOi_dataout AND NOT(niOO0i0il); + wire_n00O1iOi_dataout <= wire_n00O0ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1iOl_dataout <= wire_n00O0ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1iOO_dataout <= wire_n00O0iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1l0i_dataout <= wire_n00O0l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1l0l_dataout <= wire_n00O0l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1l0O_dataout <= wire_n00O0l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1l1i_dataout <= wire_n00O0iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1l1l_dataout <= wire_n00O0iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1l1O_dataout <= wire_n00O0l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1li_dataout <= wire_n00OOOl_dataout AND NOT(niOO0i0il); + wire_n00O1lii_dataout <= wire_n00O1OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1lil_dataout <= wire_n00O1Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1liO_dataout <= wire_n00O1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1ll_dataout <= wire_n00OOOO_dataout AND NOT(niOO0i0il); + wire_n00O1lli_dataout <= wire_n00O1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1lll_dataout <= wire_n00O1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1llO_dataout <= wire_n00O1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1lO_dataout <= wire_n0i111i_dataout AND NOT(niOO0i0il); + wire_n00O1lOi_dataout <= wire_n00O1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1lOl_dataout <= wire_n00O01lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1lOO_dataout <= wire_n00OO0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1O0i_dataout <= wire_n00OO0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1O0l_dataout <= wire_n00OO0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1O0O_dataout <= wire_n00OOl1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1O1i_dataout <= wire_n00OO0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1O1l_dataout <= wire_n00OO0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1O1O_dataout <= wire_n00OO0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1Oi_dataout <= wire_n0i111l_dataout AND NOT(niOO0i0il); + wire_n00O1Oii_dataout <= wire_n00O001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1Oil_dataout <= wire_n00O001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00O1OiO_dataout <= wire_n00O011i_dataout AND NOT(niOll00li); + wire_n00O1Ol_dataout <= wire_n0i111O_dataout AND NOT(niOO0i0il); + wire_n00O1Oli_dataout <= wire_n00O011l_dataout AND NOT(niOll00li); + wire_n00O1Oll_dataout <= wire_n00O011O_dataout AND NOT(niOll00li); + wire_n00O1OlO_dataout <= wire_n00O010i_dataout AND NOT(niOll00li); + wire_n00O1OO_dataout <= wire_n0i110i_dataout AND NOT(niOO0i0il); + wire_n00O1OOi_dataout <= wire_n00O010l_dataout AND NOT(niOll00li); + wire_n00O1OOl_dataout <= wire_n00O010O_dataout AND NOT(niOll00li); + wire_n00O1OOO_dataout <= wire_n00O01ii_dataout AND NOT(niOll00li); + wire_n00Oi00i_dataout <= wire_n00Oi0Oi_dataout AND NOT(niOll0ili); + wire_n00Oi00l_dataout <= wire_n00Ol1ii_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oi0Ol_dataout; + wire_n00Oi00O_dataout <= wire_n00Ol1il_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oi0OO_dataout; + wire_n00Oi01i_dataout <= wire_n00Oi0li_dataout AND NOT(niOll0ili); + wire_n00Oi01l_dataout <= wire_n00Oi0ll_dataout OR niOll0ili; + wire_n00Oi01O_dataout <= wire_n00Oi0lO_dataout AND NOT(niOll0ili); + wire_n00Oi0i_dataout <= wire_n0i10il_dataout AND NOT(niOO0i0il); + wire_n00Oi0ii_dataout <= wire_n00Ol1iO_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oii1i_dataout; + wire_n00Oi0il_dataout <= wire_n00Ol1li_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oii1l_dataout; + wire_n00Oi0iO_dataout <= wire_n00Ol1ll_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oii1O_dataout; + wire_n00Oi0l_dataout <= wire_n0i10iO_dataout AND NOT(niOO0i0il); + wire_n00Oi0li_dataout <= wire_n00Ol1lO_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oii0i_dataout; + wire_n00Oi0ll_dataout <= wire_n00Ol1Oi_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oii0l_dataout; + wire_n00Oi0lO_dataout <= wire_n00Ol1Ol_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oii0O_dataout; + wire_n00Oi0O_dataout <= wire_n0i10li_dataout AND NOT(niOO0i0il); + wire_n00Oi0Oi_dataout <= wire_n00Ol1OO_dataout WHEN wire_n00O11il_dataout = '1' ELSE wire_n00Oiiii_dataout; + wire_n00Oi0Ol_dataout <= wire_n00Oiiil_dataout AND NOT(niOll00OO); + wire_n00Oi0OO_dataout <= wire_n00OiiiO_dataout AND NOT(niOll00OO); + wire_n00Oi10i_dataout <= wire_n00Oi1Oi_dataout OR niOll0ill; + wire_n00Oi10l_dataout <= wire_n00Oi1Ol_dataout AND NOT(niOll0ill); + wire_n00Oi10O_dataout <= wire_n00Oi1OO_dataout OR niOll0ill; + wire_n00Oi11i_dataout <= wire_n00Oi1li_dataout OR niOll0ilO; + wire_n00Oi11l_dataout <= wire_n00Oi1ll_dataout OR niOll0ill; + wire_n00Oi11O_dataout <= wire_n00Oi1lO_dataout AND NOT(niOll0ill); + wire_n00Oi1i_dataout <= wire_n0i100l_dataout AND NOT(niOO0i0il); + wire_n00Oi1ii_dataout <= wire_n00Oi01i_dataout OR niOll0ill; + wire_n00Oi1il_dataout <= wire_n00Oi01l_dataout AND NOT(niOll0ill); + wire_n00Oi1iO_dataout <= wire_n00Oi01O_dataout OR niOll0ill; + wire_n00Oi1l_dataout <= wire_n0i100O_dataout AND NOT(niOO0i0il); + wire_n00Oi1li_dataout <= wire_n00Oi00i_dataout AND NOT(niOll0ill); + wire_n00Oi1ll_dataout <= wire_n00Oi00l_dataout AND NOT(niOll0ili); + wire_n00Oi1lO_dataout <= wire_n00Oi00O_dataout OR niOll0ili; + wire_n00Oi1O_dataout <= wire_n0i10ii_dataout AND NOT(niOO0i0il); + wire_n00Oi1Oi_dataout <= wire_n00Oi0ii_dataout AND NOT(niOll0ili); + wire_n00Oi1Ol_dataout <= wire_n00Oi0il_dataout OR niOll0ili; + wire_n00Oi1OO_dataout <= wire_n00Oi0iO_dataout AND NOT(niOll0ili); + wire_n00Oii0i_dataout <= wire_n00OiiOi_dataout OR niOll00OO; + wire_n00Oii0l_dataout <= wire_n00OiiOl_dataout AND NOT(niOll00OO); + wire_n00Oii0O_dataout <= wire_n00OiiOO_dataout OR niOll00OO; + wire_n00Oii1i_dataout <= wire_n00Oiili_dataout OR niOll00OO; + wire_n00Oii1l_dataout <= wire_n00Oiill_dataout OR niOll00OO; + wire_n00Oii1O_dataout <= wire_n00OiilO_dataout OR niOll00OO; + wire_n00Oiii_dataout <= wire_n0i10ll_dataout AND NOT(niOO0i0il); + wire_n00Oiiii_dataout <= wire_n00Oil1i_dataout OR niOll00OO; + wire_n00Oiiil_dataout <= wire_n00Oil1l_dataout AND NOT(niOll00Ol); + wire_n00OiiiO_dataout <= wire_n00Oil1O_dataout AND NOT(niOll00Ol); + wire_n00Oiil_dataout <= wire_n0i10lO_dataout AND NOT(niOO0i0il); + wire_n00Oiili_dataout <= wire_n00Oil0i_dataout OR niOll00Ol; + wire_n00Oiill_dataout <= wire_n00Oil0l_dataout OR niOll00Ol; + wire_n00OiilO_dataout <= wire_n00Oil0O_dataout OR niOll00Ol; + wire_n00OiiO_dataout <= wire_n0i10Oi_dataout AND NOT(niOO0i0il); + wire_n00OiiOi_dataout <= wire_n00Oilii_dataout OR niOll00Ol; + wire_n00OiiOl_dataout <= wire_n00Oilil_dataout OR niOll00Ol; + wire_n00OiiOO_dataout <= wire_n00OiliO_dataout AND NOT(niOll00Ol); + wire_n00Oil0i_dataout <= wire_n00OilOi_dataout AND NOT(niOll00Oi); + wire_n00Oil0l_dataout <= wire_n00OilOl_dataout AND NOT(niOll00Oi); + wire_n00Oil0O_dataout <= wire_n00OilOO_dataout AND NOT(niOll00Oi); + wire_n00Oil1i_dataout <= wire_n00Oilli_dataout OR niOll00Ol; + wire_n00Oil1l_dataout <= wire_n00Oilll_dataout AND NOT(niOll00Oi); + wire_n00Oil1O_dataout <= wire_n00OillO_dataout AND NOT(niOll00Oi); + wire_n00Oili_dataout <= wire_n0i10Ol_dataout AND NOT(niOO0i0il); + wire_n00Oilii_dataout <= wire_n00OiO1i_dataout AND NOT(niOll00Oi); + wire_n00Oilil_dataout <= wire_n00OiO1l_dataout AND NOT(niOll00Oi); + wire_n00OiliO_dataout <= wire_n00OiO1O_dataout AND NOT(niOll00Oi); + wire_n00Oill_dataout <= wire_n0i10OO_dataout AND NOT(niOO0i0il); + wire_n00Oilli_dataout <= wire_n00OiO0i_dataout AND NOT(niOll00Oi); + wire_n00Oilll_dataout <= n00lO0il WHEN niOll00ll = '1' ELSE wire_n00OiO0l_dataout; + wire_n00OillO_dataout <= n00lOl0l WHEN niOll00ll = '1' ELSE wire_n00OiO0O_dataout; + wire_n00OilO_dataout <= n0iO0iO AND niOO0i0ii; + wire_n00OilOi_dataout <= n00lOl0O WHEN niOll00ll = '1' ELSE wire_n00OiOii_dataout; + wire_n00OilOl_dataout <= n00lOlii WHEN niOll00ll = '1' ELSE wire_n00OiOil_dataout; + wire_n00OilOO_dataout <= n00lOlil WHEN niOll00ll = '1' ELSE wire_n00OiOiO_dataout; + wire_n00OiO0i_dataout <= wire_n00OiOOi_dataout AND NOT(niOll00ll); + wire_n00OiO0l_dataout <= n00O101i WHEN niOll00lO = '1' ELSE wire_n000ll0O_dataout; + wire_n00OiO0O_dataout <= n00O101l WHEN niOll00lO = '1' ELSE wire_n000ll0i_dataout; + wire_n00OiO1i_dataout <= n00lOliO WHEN niOll00ll = '1' ELSE wire_n00OiOli_dataout; + wire_n00OiO1l_dataout <= n00lOlli WHEN niOll00ll = '1' ELSE wire_n00OiOll_dataout; + wire_n00OiO1O_dataout <= n00iiiOi WHEN niOll00ll = '1' ELSE wire_n00OiOlO_dataout; + wire_n00OiOi_dataout <= n0iO0li AND niOO0i0ii; + wire_n00OiOii_dataout <= n00O101O WHEN niOll00lO = '1' ELSE wire_n000ll1l_dataout; + wire_n00OiOil_dataout <= n00O100i WHEN niOll00lO = '1' ELSE wire_n000liOO_dataout; + wire_n00OiOiO_dataout <= n00O100l WHEN niOll00lO = '1' ELSE wire_n000liOi_dataout; + wire_n00OiOl_dataout <= n0iO0ll AND niOO0i0ii; + wire_n00OiOli_dataout <= n00O100O WHEN niOll00lO = '1' ELSE wire_n000lili_dataout; + wire_n00OiOll_dataout <= n00O10ii WHEN niOll00lO = '1' ELSE wire_n000liil_dataout; + wire_n00OiOlO_dataout <= n00O10il WHEN niOll00lO = '1' ELSE wire_n000li0l_dataout; + wire_n00OiOO_dataout <= n0iO0lO AND niOO0i0ii; + wire_n00OiOOi_dataout <= n00OOlOO AND NOT(niOll00lO); + wire_n00Ol00i_dataout <= wire_n00Ol0Oi_dataout OR niOll0i1l; + wire_n00Ol00l_dataout <= wire_n00Ol0Ol_dataout OR niOll0i1l; + wire_n00Ol00O_dataout <= wire_n00Ol0OO_dataout OR niOll0i1l; + wire_n00Ol01i_dataout <= wire_n00Ol0li_dataout AND NOT(niOll0i1l); + wire_n00Ol01l_dataout <= wire_n00Ol0ll_dataout AND NOT(niOll0i1l); + wire_n00Ol01O_dataout <= wire_n00Ol0lO_dataout OR niOll0i1l; + wire_n00Ol0i_dataout <= n0iOi1i AND niOO0i0ii; + wire_n00Ol0ii_dataout <= wire_n00Oli1i_dataout AND NOT(niOll0i1l); + wire_n00Ol0il_dataout <= wire_n00Oli1l_dataout OR niOll0i1l; + wire_n00Ol0iO_dataout <= wire_n00Oli1O_dataout OR niOll0i1l; + wire_n00Ol0l_dataout <= n0iOi1l AND niOO0i0ii; + wire_n00Ol0li_dataout <= wire_n00Oli0i_dataout OR niOll0i1O; + wire_n00Ol0ll_dataout <= wire_n00Oli0l_dataout AND NOT(niOll0i1O); + wire_n00Ol0lO_dataout <= wire_n00Oli0O_dataout OR niOll0i1O; + wire_n00Ol0O_dataout <= n0iOi1O AND niOO0i0ii; + wire_n00Ol0Oi_dataout <= wire_n00Oliii_dataout AND NOT(niOll0i1O); + wire_n00Ol0Ol_dataout <= wire_n00Oliil_dataout OR niOll0i1O; + wire_n00Ol0OO_dataout <= wire_n00OliiO_dataout OR niOll0i1O; + wire_n00Ol1i_dataout <= n0iO0Oi AND niOO0i0ii; + wire_n00Ol1ii_dataout <= wire_n00Ol01i_dataout AND NOT(niOll0i1i); + wire_n00Ol1il_dataout <= wire_n00Ol01l_dataout AND NOT(niOll0i1i); + wire_n00Ol1iO_dataout <= wire_n00Ol01O_dataout OR niOll0i1i; + wire_n00Ol1l_dataout <= n0iO0Ol AND niOO0i0ii; + wire_n00Ol1li_dataout <= wire_n00Ol00i_dataout OR niOll0i1i; + wire_n00Ol1ll_dataout <= wire_n00Ol00l_dataout OR niOll0i1i; + wire_n00Ol1lO_dataout <= wire_n00Ol00O_dataout OR niOll0i1i; + wire_n00Ol1O_dataout <= n0iO0OO AND niOO0i0ii; + wire_n00Ol1Oi_dataout <= wire_n00Ol0ii_dataout AND NOT(niOll0i1i); + wire_n00Ol1Ol_dataout <= wire_n00Ol0il_dataout OR niOll0i1i; + wire_n00Ol1OO_dataout <= wire_n00Ol0iO_dataout OR niOll0i1i; + wire_n00Oli0i_dataout <= wire_n00OliOi_dataout AND NOT(niOll0i0i); + wire_n00Oli0l_dataout <= wire_n00OliOl_dataout AND NOT(niOll0i0i); + wire_n00Oli0O_dataout <= wire_n00OliOO_dataout OR niOll0i0i; + wire_n00Oli1i_dataout <= wire_n00Olili_dataout AND NOT(niOll0i1O); + wire_n00Oli1l_dataout <= wire_n00Olill_dataout OR niOll0i1O; + wire_n00Oli1O_dataout <= wire_n00OlilO_dataout AND NOT(niOll0i1O); + wire_n00Olii_dataout <= n0iOi0i AND niOO0i0ii; + wire_n00Oliii_dataout <= wire_n00Oll1i_dataout OR niOll0i0i; + wire_n00Oliil_dataout <= wire_n00Oll1l_dataout OR niOll0i0i; + wire_n00OliiO_dataout <= wire_n00Oll1O_dataout OR niOll0i0i; + wire_n00Olil_dataout <= n0iOi0l AND niOO0i0ii; + wire_n00Olili_dataout <= wire_n00Oll0i_dataout AND NOT(niOll0i0i); + wire_n00Olill_dataout <= wire_n00Oll0l_dataout OR niOll0i0i; + wire_n00OlilO_dataout <= wire_n00Oll0O_dataout OR niOll0i0i; + wire_n00OliO_dataout <= n0iOi0O AND niOO0i0ii; + wire_n00OliOi_dataout <= wire_n00Ollii_dataout AND NOT(niOll0i0l); + wire_n00OliOl_dataout <= wire_n00Ollil_dataout OR niOll0i0l; + wire_n00OliOO_dataout <= wire_n00OlliO_dataout AND NOT(niOll0i0l); + wire_n00Oll0i_dataout <= wire_n00OllOi_dataout OR niOll0i0l; + wire_n00Oll0l_dataout <= wire_n00OllOl_dataout AND NOT(niOll0i0l); + wire_n00Oll0O_dataout <= wire_n00OllOO_dataout AND NOT(niOll0i0l); + wire_n00Oll1i_dataout <= wire_n00Ollli_dataout OR niOll0i0l; + wire_n00Oll1l_dataout <= wire_n00Ollll_dataout AND NOT(niOll0i0l); + wire_n00Oll1O_dataout <= wire_n00OlllO_dataout AND NOT(niOll0i0l); + wire_n00Olli_dataout <= n0iOiii AND niOO0i0ii; + wire_n00Ollii_dataout <= n00lO0il WHEN niOll0i0O = '1' ELSE wire_n00OlO1i_dataout; + wire_n00Ollil_dataout <= n00lOl0l WHEN niOll0i0O = '1' ELSE wire_n00OlO1l_dataout; + wire_n00OlliO_dataout <= n00lOl0O WHEN niOll0i0O = '1' ELSE wire_n00OlO1O_dataout; + wire_n00Olll_dataout <= n0iOiil AND niOO0i0ii; + wire_n00Ollli_dataout <= n00lOlii WHEN niOll0i0O = '1' ELSE wire_n00OlO0i_dataout; + wire_n00Ollll_dataout <= n00lOlil WHEN niOll0i0O = '1' ELSE wire_n00OlO0l_dataout; + wire_n00OlllO_dataout <= n00lOliO WHEN niOll0i0O = '1' ELSE wire_n00OlO0O_dataout; + wire_n00OllO_dataout <= n0iOiiO AND niOO0i0ii; + wire_n00OllOi_dataout <= n00lOlli WHEN niOll0i0O = '1' ELSE wire_n00OlOii_dataout; + wire_n00OllOl_dataout <= n00iiiOi WHEN niOll0i0O = '1' ELSE wire_n00OlOil_dataout; + wire_n00OllOO_dataout <= wire_n00OlOiO_dataout AND NOT(niOll0i0O); + wire_n00OlO0i_dataout <= n00O100i WHEN niOll0iii = '1' ELSE wire_n00OlOOi_dataout; + wire_n00OlO0l_dataout <= n00O100l WHEN niOll0iii = '1' ELSE wire_n00OlOOl_dataout; + wire_n00OlO0O_dataout <= n00O100O WHEN niOll0iii = '1' ELSE wire_n00OlOOO_dataout; + wire_n00OlO1i_dataout <= n00O101i WHEN niOll0iii = '1' ELSE wire_n00OlOli_dataout; + wire_n00OlO1l_dataout <= n00O101l WHEN niOll0iii = '1' ELSE wire_n00OlOll_dataout; + wire_n00OlO1O_dataout <= n00O101O WHEN niOll0iii = '1' ELSE wire_n00OlOlO_dataout; + wire_n00OlOi_dataout <= n0iOili AND niOO0i0ii; + wire_n00OlOii_dataout <= n00O10ii WHEN niOll0iii = '1' ELSE wire_n00OO11i_dataout; + wire_n00OlOil_dataout <= n00O10il WHEN niOll0iii = '1' ELSE wire_n00OO11l_dataout; + wire_n00OlOiO_dataout <= wire_n00OO11O_dataout AND NOT(niOll0iii); + wire_n00OlOl_dataout <= n0iOill AND niOO0i0ii; + wire_n00OlOli_dataout <= wire_n00OO10i_dataout AND NOT(niOll0iil); + wire_n00OlOll_dataout <= wire_n00OO10l_dataout AND NOT(niOll0iil); + wire_n00OlOlO_dataout <= wire_n00OO10O_dataout OR niOll0iil; + wire_n00OlOO_dataout <= n0iOilO AND niOO0i0ii; + wire_n00OlOOi_dataout <= wire_n00OO1ii_dataout OR niOll0iil; + wire_n00OlOOl_dataout <= wire_n00OO1il_dataout OR niOll0iil; + wire_n00OlOOO_dataout <= wire_n00OO1iO_dataout OR niOll0iil; + wire_n00OO0i_dataout <= n0iOl1i AND niOO0i0ii; + wire_n00OO0l_dataout <= n0iOl1l AND niOO0i0ii; + wire_n00OO0li_dataout <= wire_n00OOi1i_dataout AND NOT(niOll0l0O); + wire_n00OO0ll_dataout <= wire_n00OOi1l_dataout AND NOT(niOll0l0O); + wire_n00OO0lO_dataout <= wire_n00OOi1O_dataout AND NOT(niOll0l0O); + wire_n00OO0O_dataout <= n0iOl1O AND niOO0i0ii; + wire_n00OO0Oi_dataout <= wire_n00OOi0i_dataout AND NOT(niOll0l0O); + wire_n00OO0Ol_dataout <= wire_n00OOi0l_dataout AND NOT(niOll0l0O); + wire_n00OO0OO_dataout <= wire_n00OOi0O_dataout AND NOT(niOll0l0O); + wire_n00OO10i_dataout <= n00O101i AND NOT(niOll0iiO); + wire_n00OO10l_dataout <= n00O101l AND NOT(niOll0iiO); + wire_n00OO10O_dataout <= n00O101O OR niOll0iiO; + wire_n00OO11i_dataout <= wire_n00OO1li_dataout AND NOT(niOll0iil); + wire_n00OO11l_dataout <= wire_n00OO1ll_dataout OR niOll0iil; + wire_n00OO11O_dataout <= wire_n00OO1lO_dataout OR niOll0iil; + wire_n00OO1i_dataout <= n0iOiOi AND niOO0i0ii; + wire_n00OO1ii_dataout <= n00O100i OR niOll0iiO; + wire_n00OO1il_dataout <= n00O100l OR niOll0iiO; + wire_n00OO1iO_dataout <= n00O100O OR niOll0iiO; + wire_n00OO1l_dataout <= n0iOiOl AND niOO0i0ii; + wire_n00OO1li_dataout <= n00O10ii OR niOll0iiO; + wire_n00OO1ll_dataout <= n00O10il OR niOll0iiO; + wire_n00OO1lO_dataout <= n00O10iO OR niOll0iiO; + wire_n00OO1O_dataout <= n0iOiOO AND niOO0i0ii; + wire_n00OOi0i_dataout <= wire_n00OOili_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O1i0O; + wire_n00OOi0l_dataout <= wire_n00OOill_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O1iii; + wire_n00OOi0O_dataout <= wire_n00OOilO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O1iil; + wire_n00OOi1i_dataout <= wire_n00OOiii_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O1i1O; + wire_n00OOi1l_dataout <= wire_n00OOiil_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O1i0i; + wire_n00OOi1O_dataout <= wire_n00OOiiO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n00O1i0l; + wire_n00OOii_dataout <= n0iOl0i AND niOO0i0ii; + wire_n00OOiii_dataout <= wire_n00OOiOi_o(0) WHEN niOll0l0l = '1' ELSE n00O1i1O; + wire_n00OOiil_dataout <= wire_n00OOiOi_o(1) WHEN niOll0l0l = '1' ELSE n00O1i0i; + wire_n00OOiiO_dataout <= wire_n00OOiOi_o(2) WHEN niOll0l0l = '1' ELSE n00O1i0l; + wire_n00OOil_dataout <= n0iOl0l AND niOO0i0ii; + wire_n00OOili_dataout <= wire_n00OOiOi_o(3) WHEN niOll0l0l = '1' ELSE n00O1i0O; + wire_n00OOill_dataout <= wire_n00OOiOi_o(4) WHEN niOll0l0l = '1' ELSE n00O1iii; + wire_n00OOilO_dataout <= wire_n00OOiOi_o(5) WHEN niOll0l0l = '1' ELSE n00O1iil; + wire_n00OOiO_dataout <= n0iOl0O AND niOO0i0ii; + wire_n00OOl0i_dataout <= n00O1iiO AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOll0lli15195w(0))); + wire_n00OOl1O_dataout <= wire_n00OOl0i_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15186w(0) AND wire_w_lg_niOll0liO15187w(0)); + wire_n00OOli_dataout <= n0iOlii AND niOO0i0ii; + wire_n00OOll_dataout <= n0iOlil AND niOO0i0ii; + wire_n00OOlO_dataout <= n0iOliO AND niOO0i0ii; + wire_n00OOOi_dataout <= n0iOlli AND niOO0i0ii; + wire_n00OOOiO_dataout <= wire_n0i1101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00OOOl_dataout <= n0iOlll AND niOO0i0ii; + wire_n00OOOli_dataout <= wire_n0i1100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00OOOll_dataout <= wire_n0i1100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00OOOlO_dataout <= wire_n0i1101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n00OOOO_dataout <= n0iOllO AND niOO0i0ii; + wire_n00OOOOi_dataout <= n00OOllO AND NOT(wire_niO01lOO_dataout); + wire_n00OOOOl_dataout <= nlOllOlll AND NOT(wire_niO01lOO_dataout); + wire_n00OOOOO_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15191w(0) AND wire_w_lg_niOll0lii15192w(0)) AND wire_niO01ill_w_lg_n00OOlli15189w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n01000i_dataout <= wire_n01l0Oi_dataout WHEN n1O0liO = '1' ELSE n1Ollll; + wire_n01000l_dataout <= wire_n01l0Ol_dataout WHEN n1O0liO = '1' ELSE n1OlllO; + wire_n01000O_dataout <= wire_n01l0OO_dataout WHEN n1O0liO = '1' ELSE n1OllOi; + wire_n01001i_dataout <= wire_n01l0li_dataout WHEN n1O0liO = '1' ELSE n1O0OOO; + wire_n01001l_dataout <= wire_n01l0ll_dataout WHEN n1O0liO = '1' ELSE n1Oi11i; + wire_n01001O_dataout <= wire_n01l0lO_dataout WHEN n1O0liO = '1' ELSE n1Oi11l; + wire_n0100ii_dataout <= wire_n01li1i_dataout WHEN n1O0liO = '1' ELSE n1OllOl; + wire_n0100il_dataout <= wire_n01li1l_dataout WHEN n1O0liO = '1' ELSE n1OllOO; + wire_n0100iO_dataout <= wire_n01li1O_dataout WHEN n1O0liO = '1' ELSE n1OlO1i; + wire_n0100l0O_dataout <= wire_n010iO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100li_dataout <= wire_n01li0i_dataout WHEN n1O0liO = '1' ELSE n1OlO1l; + wire_n0100lii_dataout <= wire_n010illi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100lil_dataout <= wire_n010ilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100liO_dataout <= ((wire_w_lg_niOlilO1l17388w(0) AND (wire_w_lg_niOlillii17389w(0) AND wire_w_lg_w_lg_niOlilO0O17252w17390w(0))) AND (wire_w_lg_w_lg_w_lg_niOliliil17393w17397w17398w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n0100ll_dataout <= wire_n01li0l_dataout WHEN n1O0liO = '1' ELSE n1OlO1O; + wire_n0100lli_dataout <= (wire_w_lg_w_lg_w_lg_niOlill0i17382w17384w17385w(0) AND wire_niO01ill_w_lg_n01001lO17386w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0100lll_dataout <= wire_n010ii1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100llO_dataout <= wire_n010il0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100lO_dataout <= wire_n01liii_dataout AND n1O0liO; + wire_n0100lOi_dataout <= wire_n010ilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100lOl_dataout <= wire_n010ilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100lOO_dataout <= wire_n010illl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100O0i_dataout <= wire_n010iO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100O0l_dataout <= wire_n010iO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100O0O_dataout <= wire_n010iOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100O1i_dataout <= wire_n010illO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100O1l_dataout <= wire_n010ilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100O1O_dataout <= wire_n010ilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100Oi_dataout <= wire_n01liil_dataout WHEN n1O0liO = '1' ELSE n1Oi11O; + wire_n0100Oii_dataout <= wire_n010iOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100Oil_dataout <= wire_n010iOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100OiO_dataout <= wire_n010iOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100Ol_dataout <= wire_n01liiO_dataout WHEN n1O0liO = '1' ELSE n1Oi10i; + wire_n0100Oli_dataout <= wire_n010iOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100Oll_dataout <= wire_n010iOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100OlO_dataout <= wire_n010iO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100OO_dataout <= wire_n01lili_dataout WHEN n1O0liO = '1' ELSE n1Oi10l; + wire_n0100OOi_dataout <= wire_n010iO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100OOl_dataout <= wire_n010iO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0100OOO_dataout <= wire_n010iOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010100i_dataout <= wire_n0101ilO_dataout AND NOT(niOlO1O0i); + wire_n010100l_dataout <= wire_n0101iOi_dataout AND NOT(niOlO1O0i); + wire_n010100O_dataout <= wire_n0101iOl_dataout AND NOT(niOlO1O0i); + wire_n010101i_dataout <= wire_n0101iiO_dataout AND NOT(niOlO1O0i); + wire_n010101l_dataout <= wire_n0101ili_dataout AND NOT(niOlO1O0i); + wire_n010101O_dataout <= wire_n0101ill_dataout AND NOT(niOlO1O0i); + wire_n01010i_dataout <= wire_n01l1Oi_dataout WHEN n1O0liO = '1' ELSE n1O0O1O; + wire_n01010ii_dataout <= wire_n0101iOO_dataout AND NOT(niOlO1O0i); + wire_n01010il_dataout <= wire_n0101l1i_dataout AND NOT(niOlO1O0i); + wire_n01010iO_dataout <= wire_n0101l1l_dataout AND NOT(niOlO1O0i); + wire_n01010l_dataout <= wire_n01l1Ol_dataout WHEN n1O0liO = '1' ELSE n1O0O0i; + wire_n01010li_dataout <= wire_n0101l1O_dataout AND NOT(niOlO1O0i); + wire_n01010ll_dataout <= wire_n0101l0i_dataout AND NOT(niOlO1O0i); + wire_n01010lO_dataout <= wire_n0101l0l_dataout AND NOT(niOlO1O0i); + wire_n01010O_dataout <= wire_n01l1OO_dataout WHEN n1O0liO = '1' ELSE n1O0O0l; + wire_n01010Oi_dataout <= wire_n0101l0O_dataout AND NOT(niOlO1O0i); + wire_n01010Ol_dataout <= wire_n0101llO_dataout AND NOT(niOlO1O0i); + wire_n01010OO_dataout <= wire_n0101O0O_dataout AND NOT(niOlO1O0i); + wire_n010110i_dataout <= n011lO1O WHEN niOlO1O0i = '1' ELSE wire_n0101O1l_dataout; + wire_n010110l_dataout <= n011lO0i WHEN niOlO1O0i = '1' ELSE wire_n0101O1O_dataout; + wire_n010110O_dataout <= n011lO0l WHEN niOlO1O0i = '1' ELSE wire_n0101O0i_dataout; + wire_n010111i_dataout <= n011llOO WHEN niOlO1O0i = '1' ELSE wire_n0101lOl_dataout; + wire_n010111l_dataout <= n011lO1i WHEN niOlO1O0i = '1' ELSE wire_n0101lOO_dataout; + wire_n010111O_dataout <= n011lO1l WHEN niOlO1O0i = '1' ELSE wire_n0101O1i_dataout; + wire_n01011i_dataout <= wire_n01l1ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01011ii_dataout <= n011lO0O WHEN niOlO1O0i = '1' ELSE wire_n0101O0l_dataout; + wire_n01011il_dataout <= wire_n0101i1i_dataout AND NOT(niOlO1O0i); + wire_n01011iO_dataout <= wire_n0101i1l_dataout AND NOT(niOlO1O0i); + wire_n01011l_dataout <= wire_n0100lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01011li_dataout <= wire_n0101i1O_dataout AND NOT(niOlO1O0i); + wire_n01011ll_dataout <= wire_n0101i0i_dataout AND NOT(niOlO1O0i); + wire_n01011lO_dataout <= wire_n0101i0l_dataout AND NOT(niOlO1O0i); + wire_n01011O_dataout <= wire_n01l1lO_dataout WHEN n1O0liO = '1' ELSE n1O0O1l; + wire_n01011Oi_dataout <= wire_n0101i0O_dataout AND NOT(niOlO1O0i); + wire_n01011Ol_dataout <= wire_n0101iii_dataout AND NOT(niOlO1O0i); + wire_n01011OO_dataout <= wire_n0101iil_dataout AND NOT(niOlO1O0i); + wire_n0101i0i_dataout <= n01001Oi WHEN n01001ll = '1' ELSE n011li0l; + wire_n0101i0l_dataout <= n01001Ol WHEN n01001ll = '1' ELSE n011li0O; + wire_n0101i0O_dataout <= n01001OO WHEN n01001ll = '1' ELSE n011liii; + wire_n0101i1i_dataout <= n011lOil WHEN n01001ll = '1' ELSE n011iOii; + wire_n0101i1l_dataout <= n01001il WHEN n01001ll = '1' ELSE n011l0il; + wire_n0101i1O_dataout <= n01001iO WHEN n01001ll = '1' ELSE n011l0iO; + wire_n0101ii_dataout <= wire_n01l01i_dataout WHEN n1O0liO = '1' ELSE n1O0O0O; + wire_n0101iii_dataout <= n010001i WHEN n01001ll = '1' ELSE n011liil; + wire_n0101iil_dataout <= n010001l WHEN n01001ll = '1' ELSE n011liiO; + wire_n0101iiO_dataout <= n010001O WHEN n01001ll = '1' ELSE n011lili; + wire_n0101il_dataout <= wire_n01l01l_dataout WHEN n1O0liO = '1' ELSE n1O0Oii; + wire_n0101ili_dataout <= n010000i WHEN n01001ll = '1' ELSE n011lill; + wire_n0101ill_dataout <= n010000l WHEN n01001ll = '1' ELSE n011lilO; + wire_n0101ilO_dataout <= n010000O WHEN n01001ll = '1' ELSE n011liOi; + wire_n0101iO_dataout <= wire_n01l01O_dataout WHEN n1O0liO = '1' ELSE n1O0Oil; + wire_n0101iOi_dataout <= n01000ii WHEN n01001ll = '1' ELSE n011liOl; + wire_n0101iOl_dataout <= n01000il WHEN n01001ll = '1' ELSE n011liOO; + wire_n0101iOO_dataout <= n01000iO WHEN n01001ll = '1' ELSE n011ll1i; + wire_n0101l0i_dataout <= n01000Oi WHEN n01001ll = '1' ELSE n011ll0l; + wire_n0101l0l_dataout <= n01000Ol WHEN n01001ll = '1' ELSE n011ll0O; + wire_n0101l0O_dataout <= n01000OO WHEN n01001ll = '1' ELSE n011llii; + wire_n0101l1i_dataout <= n01000li WHEN n01001ll = '1' ELSE n011ll1l; + wire_n0101l1l_dataout <= n01000ll WHEN n01001ll = '1' ELSE n011ll1O; + wire_n0101l1O_dataout <= n01000lO WHEN n01001ll = '1' ELSE n011ll0i; + wire_n0101li_dataout <= wire_n01l00i_dataout WHEN n1O0liO = '1' ELSE n1O0OiO; + wire_n0101lii_dataout <= n0100i1i WHEN n01001ll = '1' ELSE n011llil; + wire_n0101lil_dataout <= n0100i1l WHEN n01001ll = '1' ELSE n011lliO; + wire_n0101liO_dataout <= n0100i1O WHEN n01001ll = '1' ELSE n011llli; + wire_n0101ll_dataout <= wire_n01l00l_dataout WHEN n1O0liO = '1' ELSE n1O0Oli; + wire_n0101lli_dataout <= n0100i0i WHEN n01001ll = '1' ELSE n011llll; + wire_n0101lll_dataout <= n0100i0l WHEN n01001ll = '1' ELSE n011lllO; + wire_n0101llO_dataout <= n0100i0O WHEN n01001ll = '1' ELSE n011llOi; + wire_n0101lO_dataout <= wire_n01l00O_dataout WHEN n1O0liO = '1' ELSE n1O0Oll; + wire_n0101lOi_dataout <= n0100iii WHEN n01001ll = '1' ELSE n011llOl; + wire_n0101lOl_dataout <= n0100iil WHEN n01001ll = '1' ELSE n011llOO; + wire_n0101lOO_dataout <= n0100iiO WHEN n01001ll = '1' ELSE n011lO1i; + wire_n0101O0i_dataout <= n0100iOi WHEN n01001ll = '1' ELSE n011lO0l; + wire_n0101O0l_dataout <= n0100iOl WHEN n01001ll = '1' ELSE n011lO0O; + wire_n0101O0O_dataout <= n0100iOO WHEN n01001ll = '1' ELSE n011lOii; + wire_n0101O1i_dataout <= n0100ili WHEN n01001ll = '1' ELSE n011lO1l; + wire_n0101O1l_dataout <= n0100ill WHEN n01001ll = '1' ELSE n011lO1O; + wire_n0101O1O_dataout <= n0100ilO WHEN n01001ll = '1' ELSE n011lO0i; + wire_n0101Oi_dataout <= wire_n01l0ii_dataout WHEN n1O0liO = '1' ELSE n1O0OlO; + wire_n0101Ol_dataout <= wire_n01l0il_dataout WHEN n1O0liO = '1' ELSE n1O0OOi; + wire_n0101OO_dataout <= wire_n01l0iO_dataout WHEN n1O0liO = '1' ELSE n1O0OOl; + wire_n010i01i_dataout <= wire_n010l1Ol_dataout OR wire_niO01lOO_dataout; + wire_n010i01l_dataout <= wire_n010l1OO_dataout OR wire_niO01lOO_dataout; + wire_n010i01O_dataout <= wire_n010l01i_dataout OR wire_niO01lOO_dataout; + wire_n010i0i_dataout <= wire_n01liOl_dataout WHEN n1O0liO = '1' ELSE n1Oi1iO; + wire_n010i0l_dataout <= wire_n01liOO_dataout WHEN n1O0liO = '1' ELSE n1Oi1li; + wire_n010i0O_dataout <= wire_n01ll1i_dataout WHEN n1O0liO = '1' ELSE n1Oi1ll; + wire_n010i10i_dataout <= wire_n010l11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i10l_dataout <= wire_n010l11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i10O_dataout <= wire_n010l10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i11i_dataout <= wire_n010iOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i11l_dataout <= wire_n010iOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i11O_dataout <= wire_n010l11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1i_dataout <= wire_n01lill_dataout WHEN n1O0liO = '1' ELSE n1Oi10O; + wire_n010i1ii_dataout <= wire_n010l10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1il_dataout <= wire_n010l10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1iO_dataout <= wire_n010l1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1l_dataout <= wire_n01lilO_dataout WHEN n1O0liO = '1' ELSE n1Oi1ii; + wire_n010i1li_dataout <= wire_n010l1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1ll_dataout <= wire_n010l1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1lO_dataout <= wire_n010l1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1O_dataout <= wire_n01liOi_dataout WHEN n1O0liO = '1' ELSE n1Oi1il; + wire_n010i1Oi_dataout <= wire_n010l1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1Ol_dataout <= wire_n010l1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010i1OO_dataout <= wire_n010l1Oi_dataout OR wire_niO01lOO_dataout; + wire_n010ii0i_dataout <= wire_n010ii0l_dataout OR (wire_w_lg_niOlillOl17360w(0) AND (wire_w_lg_w_lg_niOlilill17362w17363w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n0100l0i17365w17367w17368w(0))); + wire_n010ii0l_dataout <= wire_n010ii0O_dataout OR (wire_w_lg_niOlillOl17360w(0) AND niOlilili); + wire_n010ii0O_dataout <= n01001lO OR (wire_n010iiOi_o AND (((niOlill0i XOR n01001Ol) OR (niOlill1i XOR n01001Oi)) OR (NOT (n01001Ol XOR n01001Oi)))); + wire_n010ii1l_dataout <= wire_n010ii1O_dataout AND NOT(niOlillii); + wire_n010ii1O_dataout <= wire_n010ii0i_dataout OR (wire_w_lg_niOlillOO17371w(0) AND wire_w_lg_w_lg_niOlillOl17360w17372w(0)); + wire_n010iii_dataout <= wire_n01ll1l_dataout WHEN n1O0liO = '1' ELSE n1Oi1lO; + wire_n010iil_dataout <= wire_n01ll1O_dataout WHEN n1O0liO = '1' ELSE n1Oi1Oi; + wire_n010iiO_dataout <= wire_n01ll0i_dataout WHEN n1O0liO = '1' ELSE n1Oi1Ol; + wire_n010il0O_dataout <= niOlill1i WHEN wire_n010iliO_o = '1' ELSE n01001Oi; + wire_n010ili_dataout <= wire_n01ll0l_dataout WHEN n1O0liO = '1' ELSE n1Oi1OO; + wire_n010ilii_dataout <= niOlill0i WHEN wire_n010iliO_o = '1' ELSE n01001Ol; + wire_n010ilil_dataout <= (wire_niO10l1l_dataout AND (niOlill1O OR niOlill0O)) WHEN wire_n010iliO_o = '1' ELSE n01001OO; + wire_n010ill_dataout <= wire_n01ll0O_dataout WHEN n1O0liO = '1' ELSE n1Oi01i; + wire_n010illi_dataout <= wire_niO10lil_dataout WHEN niOliliiO = '1' ELSE n01001il; + wire_n010illl_dataout <= wire_niO10l0i_dataout WHEN niOliliiO = '1' ELSE n010001i; + wire_n010illO_dataout <= wire_niO10l0l_dataout WHEN niOliliiO = '1' ELSE n010001l; + wire_n010ilO_dataout <= wire_n01llii_dataout WHEN n1O0liO = '1' ELSE n1Oi01l; + wire_n010ilOi_dataout <= wire_niO10l0O_dataout WHEN niOliliiO = '1' ELSE n010001O; + wire_n010ilOl_dataout <= wire_niO10lii_dataout WHEN niOliliiO = '1' ELSE n010000i; + wire_n010ilOO_dataout <= wire_niO10lll_dataout WHEN niOlilili = '1' ELSE n01001iO; + wire_n010iO0i_dataout <= n01000OO AND NOT(niOlilili); + wire_n010iO0l_dataout <= wire_niO10l0i_dataout WHEN niOlilill = '1' ELSE n010000l; + wire_n010iO0O_dataout <= wire_niO10l0l_dataout WHEN niOlilill = '1' ELSE n010000O; + wire_n010iO1i_dataout <= wire_niO10lli_dataout WHEN niOlilili = '1' ELSE n011lOil; + wire_n010iO1l_dataout <= wire_niO10l0l_dataout WHEN niOlilili = '1' ELSE n01000Oi; + wire_n010iO1O_dataout <= wire_niO10l0O_dataout WHEN niOlilili = '1' ELSE n01000Ol; + wire_n010iOi_dataout <= wire_n01llil_dataout WHEN n1O0liO = '1' ELSE n1Oi01O; + wire_n010iOii_dataout <= wire_niO10l0O_dataout WHEN niOlilill = '1' ELSE n01000ii; + wire_n010iOil_dataout <= wire_niO10lii_dataout WHEN niOlilill = '1' ELSE n01000il; + wire_n010iOiO_dataout <= wire_niO10lil_dataout WHEN niOlilill = '1' ELSE n01000iO; + wire_n010iOl_dataout <= wire_n01lliO_dataout WHEN n1O0liO = '1' ELSE n1Oi00i; + wire_n010iOli_dataout <= wire_niO10liO_dataout WHEN niOlilill = '1' ELSE n01000li; + wire_n010iOll_dataout <= wire_niO10lli_dataout WHEN niOlilill = '1' ELSE n01000ll; + wire_n010iOlO_dataout <= wire_niO10lll_dataout WHEN niOlilill = '1' ELSE n01000lO; + wire_n010iOO_dataout <= wire_n01llli_dataout WHEN n1O0liO = '1' ELSE n1Oi00l; + wire_n010iOOi_dataout <= wire_niO10l0i_dataout WHEN niOliliOl = '1' ELSE n0100i1i; + wire_n010iOOl_dataout <= wire_niO10l0l_dataout WHEN niOliliOl = '1' ELSE n0100i1l; + wire_n010iOOO_dataout <= wire_niO10l0O_dataout WHEN niOliliOl = '1' ELSE n0100i1O; + wire_n010l00i_dataout <= wire_n010l0il_dataout WHEN wire_w_lg_niOlililO17322w(0) = '1' ELSE n0100l1O; + wire_n010l00l_dataout <= wire_n010l0iO_dataout WHEN wire_w_lg_niOlililO17322w(0) = '1' ELSE n0100l0i; + wire_n010l00O_dataout <= wire_n010l0li_o(1) AND niOliliOi; + wire_n010l01i_dataout <= wire_n010l00l_dataout OR niOlillii; + wire_n010l01l_dataout <= wire_n010l00O_dataout WHEN wire_w_lg_niOlililO17322w(0) = '1' ELSE n0100l1i; + wire_n010l01O_dataout <= wire_n010l0ii_dataout WHEN wire_w_lg_niOlililO17322w(0) = '1' ELSE n0100l1l; + wire_n010l0i_dataout <= wire_n01llOl_dataout WHEN n1O0liO = '1' ELSE n1Oi0iO; + wire_n010l0ii_dataout <= wire_n010l0li_o(2) AND niOliliOi; + wire_n010l0il_dataout <= wire_n010l0li_o(3) AND niOliliOi; + wire_n010l0iO_dataout <= wire_n010l0li_o(4) AND niOliliOi; + wire_n010l0l_dataout <= wire_n01llOO_dataout WHEN n1O0liO = '1' ELSE n1Oi0li; + wire_n010l0O_dataout <= wire_n01lO1i_dataout WHEN n1O0liO = '1' ELSE n1Oi0ll; + wire_n010l10i_dataout <= wire_niO10l0i_dataout WHEN niOlillii = '1' ELSE n0100iii; + wire_n010l10l_dataout <= wire_niO10l0l_dataout WHEN niOlillii = '1' ELSE n0100iil; + wire_n010l10O_dataout <= wire_niO10l0O_dataout WHEN niOlillii = '1' ELSE n0100iiO; + wire_n010l11i_dataout <= wire_niO10lii_dataout WHEN niOliliOl = '1' ELSE n0100i0i; + wire_n010l11l_dataout <= wire_niO10lil_dataout WHEN niOliliOl = '1' ELSE n0100i0l; + wire_n010l11O_dataout <= niOlillOO WHEN niOliliOl = '1' ELSE n0100i0O; + wire_n010l1i_dataout <= wire_n01llll_dataout WHEN n1O0liO = '1' ELSE n1Oi00O; + wire_n010l1ii_dataout <= wire_niO10lii_dataout WHEN niOlillii = '1' ELSE n0100ili; + wire_n010l1il_dataout <= wire_niO10lil_dataout WHEN niOlillii = '1' ELSE n0100ill; + wire_n010l1iO_dataout <= wire_niO10liO_dataout WHEN niOlillii = '1' ELSE n0100ilO; + wire_n010l1l_dataout <= wire_n01lllO_dataout WHEN n1O0liO = '1' ELSE n1Oi0ii; + wire_n010l1li_dataout <= wire_niO10lli_dataout WHEN niOlillii = '1' ELSE n0100iOi; + wire_n010l1ll_dataout <= wire_niO10lll_dataout WHEN niOlillii = '1' ELSE n0100iOl; + wire_n010l1lO_dataout <= niOlillOO WHEN niOlillii = '1' ELSE n0100iOO; + wire_n010l1O_dataout <= wire_n01llOi_dataout WHEN n1O0liO = '1' ELSE n1Oi0il; + wire_n010l1Oi_dataout <= wire_n010l01l_dataout OR niOlillii; + wire_n010l1Ol_dataout <= wire_n010l01O_dataout AND NOT(niOlillii); + wire_n010l1OO_dataout <= wire_n010l00i_dataout OR niOlillii; + wire_n010lii_dataout <= wire_n01lO1l_dataout WHEN n1O0liO = '1' ELSE n1Oi0lO; + wire_n010lil_dataout <= wire_n01lO1O_dataout WHEN n1O0liO = '1' ELSE n1Oi0Oi; + wire_n010liO_dataout <= wire_n01lO0i_dataout WHEN n1O0liO = '1' ELSE n1Oi0Ol; + wire_n010lli_dataout <= wire_n01lO0l_dataout WHEN n1O0liO = '1' ELSE n1Oi0OO; + wire_n010llii_dataout <= wire_n010llll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010llil_dataout <= wire_n010lllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010lliO_dataout <= wire_n010llOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010lll_dataout <= wire_n01lO0O_dataout WHEN n1O0liO = '1' ELSE n1Oii1i; + wire_n010llli_dataout <= wire_n010llOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010llll_dataout <= wire_n010llOO_dataout AND NOT(niOlillil); + wire_n010lllO_dataout <= wire_n010lO1i_dataout AND NOT(niOlillil); + wire_n010llO_dataout <= wire_n01lOii_dataout WHEN n1O0liO = '1' ELSE n1Oii1l; + wire_n010llOi_dataout <= wire_n010lO1l_dataout AND NOT(niOlillil); + wire_n010llOl_dataout <= wire_n010lO1O_dataout AND NOT(niOlillil); + wire_n010llOO_dataout <= wire_n010lO0i_o(0) WHEN wire_niO01ill_w_lg_n010ll0l17278w(0) = '1' ELSE n0100l0l; + wire_n010lO1i_dataout <= wire_n010lO0i_o(1) WHEN wire_niO01ill_w_lg_n010ll0l17278w(0) = '1' ELSE n010ll1O; + wire_n010lO1l_dataout <= wire_n010lO0i_o(2) WHEN wire_niO01ill_w_lg_n010ll0l17278w(0) = '1' ELSE n010ll0i; + wire_n010lO1O_dataout <= wire_n010lO0i_o(3) OR NOT(wire_niO01ill_w_lg_n010ll0l17278w(0)); + wire_n010lOi_dataout <= wire_n01lOil_dataout WHEN n1O0liO = '1' ELSE n1Oii1O; + wire_n010lOl_dataout <= wire_n01lOiO_dataout WHEN n1O0liO = '1' ELSE n1Oii0i; + wire_n010lOO_dataout <= wire_n01lOli_dataout WHEN n1O0liO = '1' ELSE n1Oii0l; + wire_n010O0i_dataout <= wire_n01lOOl_dataout WHEN n1O0liO = '1' ELSE n1OiiiO; + wire_n010O0l_dataout <= wire_n01lOOO_dataout WHEN n1O0liO = '1' ELSE n1Oiili; + wire_n010O0O_dataout <= wire_n01O11i_dataout WHEN n1O0liO = '1' ELSE n1Oiill; + wire_n010O10i_dataout <= niOlillOi AND NOT(wire_niO01lOO_dataout); + wire_n010O10l_dataout <= (niOlilO0i AND n010lOOl) AND NOT(wire_niO01lOO_dataout); + wire_n010O10O_dataout <= n010lOll AND NOT(wire_niO01lOO_dataout); + wire_n010O11i_dataout <= (niOlilO0O AND n010lOii) AND NOT(wire_niO01lOO_dataout); + wire_n010O11l_dataout <= (niOlilO0O AND n010lOil) AND NOT(wire_niO01lOO_dataout); + wire_n010O11O_dataout <= (wire_w_lg_w_lg_w_lg_niOlilO0i17249w17250w17251w(0) OR (wire_w_lg_niOlilO0O17252w(0) AND (wire_w_lg_niOlilO0i17253w(0) AND (n010lOll AND niOlillli)))) AND NOT(wire_niO01lOO_dataout); + wire_n010O1i_dataout <= wire_n01lOll_dataout WHEN n1O0liO = '1' ELSE n1Oii0O; + wire_n010O1ii_dataout <= niOlilO0i AND NOT(wire_niO01lOO_dataout); + wire_n010O1il_dataout <= n010lOOi AND NOT(wire_niO01lOO_dataout); + wire_n010O1iO_dataout <= n010lOOl AND NOT(wire_niO01lOO_dataout); + wire_n010O1l_dataout <= wire_n01lOlO_dataout WHEN n1O0liO = '1' ELSE n1Oiiii; + wire_n010O1li_dataout <= niOlilO0O AND NOT(wire_niO01lOO_dataout); + wire_n010O1O_dataout <= wire_n01lOOi_dataout WHEN n1O0liO = '1' ELSE n1Oiiil; + wire_n010Oi0i_dataout <= wire_n010Oill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010Oi0l_dataout <= wire_n010OilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010Oi0O_dataout <= wire_n010OiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010Oii_dataout <= wire_n01O11l_dataout WHEN n1O0liO = '1' ELSE n1OiilO; + wire_n010Oiii_dataout <= wire_n010OiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010Oiil_dataout <= wire_n010OiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010OiiO_dataout <= wire_n010Ol1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010Oil_dataout <= wire_n01O11O_dataout WHEN n1O0liO = '1' ELSE n1OiiOi; + wire_n010Oili_dataout <= wire_n010Ol1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n010Oill_dataout <= wire_n010Ol1O_dataout AND NOT(niOlilOli); + wire_n010OilO_dataout <= wire_n010Ol0i_dataout AND NOT(niOlilOli); + wire_n010OiO_dataout <= wire_n01O10i_dataout WHEN n1O0liO = '1' ELSE n1OiiOl; + wire_n010OiOi_dataout <= wire_n010Ol0l_dataout AND NOT(niOlilOli); + wire_n010OiOl_dataout <= wire_n010Ol0O_dataout AND NOT(niOlilOli); + wire_n010OiOO_dataout <= wire_n010Olii_dataout AND NOT(niOlilOli); + wire_n010Ol0i_dataout <= wire_n010Olli_o(1) WHEN niOlilOil = '1' ELSE n010O0lO; + wire_n010Ol0l_dataout <= wire_n010Olli_o(2) WHEN niOlilOil = '1' ELSE n010O0Oi; + wire_n010Ol0O_dataout <= wire_n010Olli_o(3) WHEN niOlilOil = '1' ELSE n010O0Ol; + wire_n010Ol1i_dataout <= wire_n010Olil_dataout AND NOT(niOlilOli); + wire_n010Ol1l_dataout <= wire_n010OliO_dataout AND NOT(niOlilOli); + wire_n010Ol1O_dataout <= wire_n010Olli_o(0) WHEN niOlilOil = '1' ELSE n010lOOO; + wire_n010Oli_dataout <= wire_n01O10l_dataout WHEN n1O0liO = '1' ELSE n1OiiOO; + wire_n010Olii_dataout <= wire_n010Olli_o(4) WHEN niOlilOil = '1' ELSE n010O0OO; + wire_n010Olil_dataout <= wire_n010Olli_o(5) WHEN niOlilOil = '1' ELSE n010Oi1i; + wire_n010OliO_dataout <= wire_n010Olli_o(6) WHEN niOlilOil = '1' ELSE n010Oi1l; + wire_n010Oll_dataout <= wire_n01O10O_dataout WHEN n1O0liO = '1' ELSE n1Oil1i; + wire_n010OlO_dataout <= wire_n01O1ii_dataout WHEN n1O0liO = '1' ELSE n1Oil1l; + wire_n010OlOO_dataout <= n01i11iO AND (((NOT (wire_niili01O_dataout XOR n01i110O)) AND (NOT (wire_niili00i_dataout XOR n01i11ii))) AND (NOT (n1101l1i XOR n01i11il))); + wire_n010OlOO_w_lg_w_lg_w_lg_dataout17133w17139w17140w(0) <= wire_n010OlOO_w_lg_w_lg_dataout17133w17139w(0) AND n01i11iO; + wire_n010OlOO_w_lg_w_lg_dataout17133w17139w(0) <= wire_n010OlOO_w_lg_dataout17133w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n01i110i17134w17136w17138w(0); + wire_n010OlOO_w_lg_dataout17146w(0) <= wire_n010OlOO_dataout AND wire_niO01ill_w17145w(0); + wire_n010OlOO_w_lg_dataout17133w(0) <= NOT wire_n010OlOO_dataout; + wire_n010OO0O_dataout <= n010Oi1O AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllOliO); + wire_n010OO1i_dataout <= n01i101i AND (n01i11li AND niOlilOll); + wire_n010OO1O_dataout <= n01i101i AND ((NOT (n01i11lO XOR n01i11ll)) AND niOlilOll); + wire_n010OOi_dataout <= wire_n01O1il_dataout WHEN n1O0liO = '1' ELSE n1Oil1O; + wire_n010OOl_dataout <= wire_n01O1iO_dataout WHEN n1O0liO = '1' ELSE n1Oil0i; + wire_n010OOO_dataout <= wire_n01O1li_dataout WHEN n1O0liO = '1' ELSE n1Oil0l; + wire_n01100i_dataout <= wire_n01i0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01100l_dataout <= wire_n01i0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01100O_dataout <= wire_n01i0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01101i_dataout <= wire_n01i0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01101l_dataout <= wire_n01i0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01101O_dataout <= wire_n01i0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110ii_dataout <= wire_n01i0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110il_dataout <= wire_n01ii1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110iO_dataout <= wire_n01ii1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110li_dataout <= wire_n01ii1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110ll_dataout <= wire_n01ii0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110lO_dataout <= wire_n01ii0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110Oi_dataout <= wire_n01ii0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110Ol_dataout <= wire_n01iiii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110OO_dataout <= wire_n01iiil_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0110OOO_dataout <= wire_niO10l1O_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011100i_dataout <= wire_n0111i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011100l_dataout <= wire_n0111i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011100O_dataout <= wire_n0111iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011101i_dataout <= wire_n0111i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011101l_dataout <= wire_n0111i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011101O_dataout <= wire_n0111i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01110i_dataout <= wire_n01i1lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01110ii_dataout <= wire_n0111iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01110il_dataout <= wire_n0111iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01110iO_dataout <= wire_n0111ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01110l_dataout <= wire_n01i1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01110li_dataout <= wire_n0111ill_dataout OR niOlil00l; + wire_n01110ll_dataout <= wire_n0111ilO_dataout OR niOlil00l; + wire_n01110lO_dataout <= wire_n0111iOi_dataout OR niOlil00l; + wire_n01110O_dataout <= wire_n01i1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01110Oi_dataout <= wire_n0111iOl_dataout OR niOlil00l; + wire_n01110Ol_dataout <= wire_n0111iOO_dataout OR niOlil00l; + wire_n01110OO_dataout <= wire_n0111l1i_dataout OR niOlil00l; + wire_n01111i_dataout <= wire_n01i1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01111iO_dataout <= wire_n01110li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01111l_dataout <= wire_n01i1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01111li_dataout <= wire_n01110ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01111ll_dataout <= wire_n01110lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01111lO_dataout <= wire_n01110Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01111O_dataout <= wire_n01i1ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n01111Oi_dataout <= wire_n01110Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01111Ol_dataout <= wire_n01110OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01111OO_dataout <= wire_n0111i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0111i0i_dataout <= wire_n0111l0l_dataout OR niOlil00l; + wire_n0111i0l_dataout <= wire_n0111l0O_dataout OR niOlil00l; + wire_n0111i0O_dataout <= wire_n0111lii_dataout OR niOlil00l; + wire_n0111i1i_dataout <= wire_n0111l1l_dataout OR niOlil00l; + wire_n0111i1l_dataout <= wire_n0111l1O_dataout OR niOlil00l; + wire_n0111i1O_dataout <= wire_n0111l0i_dataout OR niOlil00l; + wire_n0111ii_dataout <= wire_n01i1OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111iii_dataout <= wire_n0111lil_dataout OR niOlil00l; + wire_n0111iil_dataout <= wire_n0111liO_dataout OR niOlil00l; + wire_n0111iiO_dataout <= wire_n0111lli_dataout OR niOlil00l; + wire_n0111il_dataout <= wire_n01i01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111ili_dataout <= wire_n0111lll_dataout OR niOlil00l; + wire_n0111ill_dataout <= n1OOOlOi WHEN niOlil00O = '1' ELSE n011111i; + wire_n0111ilO_dataout <= n1OOOOiO WHEN niOlil00O = '1' ELSE n011111l; + wire_n0111iO_dataout <= wire_n01i01l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111iOi_dataout <= n1OOOOli WHEN niOlil00O = '1' ELSE n011111O; + wire_n0111iOl_dataout <= n1OOOOll WHEN niOlil00O = '1' ELSE (n011110i XOR n011111i); + wire_n0111iOO_dataout <= n1OOOOlO WHEN niOlil00O = '1' ELSE (n011111i XOR (n011110l XOR n011111l)); + wire_n0111l0i_dataout <= n011111i WHEN niOlil00O = '1' ELSE (n011110i XOR (n011110l XOR (n011110O XOR n1OOOlOi))); + wire_n0111l0l_dataout <= n011111l WHEN niOlil00O = '1' ELSE (n011110l XOR (n011110O XOR (n01111ii XOR n1OOOOiO))); + wire_n0111l0O_dataout <= n011111O WHEN niOlil00O = '1' ELSE (n011110O XOR (n01111ii XOR (n01111il XOR n1OOOOli))); + wire_n0111l1i_dataout <= n1OOOOOi WHEN niOlil00O = '1' ELSE (n011111i XOR (n011111l XOR (n011110O XOR n011111O))); + wire_n0111l1l_dataout <= n1OOOOOl WHEN niOlil00O = '1' ELSE (n011111l XOR (n011111O XOR (n01111ii XOR n011110i))); + wire_n0111l1O_dataout <= n1OOOOOO WHEN niOlil00O = '1' ELSE (n011111O XOR (n011110i XOR (n01111il XOR n011110l))); + wire_n0111li_dataout <= wire_n01i01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111lii_dataout <= n011110i WHEN niOlil00O = '1' ELSE (n01111ii XOR (n01111il XOR n1OOOOll)); + wire_n0111lil_dataout <= n011110l WHEN niOlil00O = '1' ELSE (n01111il XOR n1OOOOlO); + wire_n0111liO_dataout <= n011110O WHEN niOlil00O = '1' ELSE n1OOOOOi; + wire_n0111ll_dataout <= wire_n01i00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111lli_dataout <= n01111ii WHEN niOlil00O = '1' ELSE n1OOOOOl; + wire_n0111lll_dataout <= n01111il WHEN niOlil00O = '1' ELSE n1OOOOOO; + wire_n0111lO_dataout <= wire_n01i00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111Oi_dataout <= wire_n01i00O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111Ol_dataout <= wire_n01i0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n0111OO_dataout <= wire_n01i0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011i00O_dataout <= ((wire_niO10l1l_dataout AND niOlill0l) AND n011i1li) AND n01i11iO; + wire_n011i01i_dataout <= wire_n011i0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011i01l_dataout <= wire_n011i01O_dataout AND n01i11iO; + wire_n011i01O_dataout <= n011i00l OR (n01i11iO AND n011i1iO); + wire_n011i0i_dataout <= wire_n01iilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011i0ii_dataout <= (niOlilO0O AND n011i1ll) AND n01i11iO; + wire_n011i0il_dataout <= (n010lOOl AND (wire_niO10l1l_dataout AND niOlill0O)) AND n01i11iO; + wire_n011i0l_dataout <= wire_n01iiOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011i0O_dataout <= wire_n01iiOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011i10i_dataout <= wire_n1OOOO1i_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011i10l_dataout <= wire_n1OOOlOl_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011i10O_dataout <= wire_n1OOOlll_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011i11i_dataout <= wire_n1OOOOii_dataout AND wire_niO10iOl_w_lg_dataout17537w(0); + wire_n011i11l_dataout <= wire_n1OOOO0l_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011i11O_dataout <= wire_n1OOOO1O_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011i1i_dataout <= wire_n01iiiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011i1ii_dataout <= wire_n1OOOliO_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011i1il_dataout <= wire_n1OOOl0O_dataout OR NOT(wire_niO10iOl_w_lg_dataout17537w(0)); + wire_n011i1l_dataout <= wire_n01iili_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011i1O_dataout <= wire_n01iill_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011i1Oi_dataout <= wire_n011i01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011i1Ol_dataout <= wire_n011i00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011i1OO_dataout <= wire_n011i0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011ii0i_dataout <= wire_n011ilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011ii0l_dataout <= wire_n011iiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011ii0O_dataout <= wire_n011iiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011ii1O_dataout <= wire_n011iiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011iii_dataout <= wire_n01iiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011iiii_dataout <= wire_n011iili_dataout AND NOT(niOlil0ii); + wire_n011iiil_dataout <= wire_n011illl_dataout WHEN niOlil0ii = '1' ELSE wire_n011iill_dataout; + wire_n011iiiO_dataout <= wire_n011illO_dataout WHEN niOlil0ii = '1' ELSE wire_n011iilO_dataout; + wire_n011iil_dataout <= wire_n01il1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011iili_dataout <= n011i1lO WHEN wire_niO01ill_w_lg_n011i0Ol17530w(0) = '1' ELSE wire_n011iiOO_dataout; + wire_n011iill_dataout <= wire_n011il1i_dataout WHEN wire_niO01ill_w_lg_n011i0Ol17530w(0) = '1' ELSE wire_n011iiOi_dataout; + wire_n011iilO_dataout <= wire_n011il1l_dataout WHEN wire_niO01ill_w_lg_n011i0Ol17530w(0) = '1' ELSE wire_n011iiOl_dataout; + wire_n011iiO_dataout <= wire_n01il1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011iiOi_dataout <= wire_n011ilii_dataout WHEN niOlillOi = '1' ELSE wire_n011il1i_dataout; + wire_n011iiOl_dataout <= wire_n011ilil_dataout WHEN niOlillOi = '1' ELSE wire_n011il1l_dataout; + wire_n011iiOO_dataout <= wire_n011iliO_dataout WHEN niOlillOi = '1' ELSE n011i1lO; + wire_n011il1i_dataout <= n011i0OO AND NOT(niOlil0iO); + wire_n011il1l_dataout <= n011ii1i AND NOT(niOlil0iO); + wire_n011ili_dataout <= wire_n01il1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011ilii_dataout <= n011i0OO WHEN niOlil0il = '1' ELSE wire_n011illi_o(0); + wire_n011ilil_dataout <= n011ii1i WHEN niOlil0il = '1' ELSE wire_n011illi_o(1); + wire_n011iliO_dataout <= n011i1lO OR niOlil0il; + wire_n011ill_dataout <= wire_n01il0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011illl_dataout <= n011i0OO OR niOlillOi; + wire_n011illO_dataout <= n011ii1i AND NOT(niOlillOi); + wire_n011ilO_dataout <= wire_n01il0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011ilOi_dataout <= wire_n011ilOl_dataout OR (niOlilO0i AND (n010lO0O OR n010ll0O)); + wire_n011ilOl_dataout <= n011i0Ol AND NOT(niOlil0iO); + wire_n011iOi_dataout <= wire_n01il0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011iOil_dataout <= wire_n011iOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011iOiO_dataout <= wire_n011iOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011iOl_dataout <= wire_n01ilii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011iOli_dataout <= wire_n011l11i_dataout OR wire_niO01lOO_dataout; + wire_n011iOll_dataout <= wire_n011l11l_dataout OR wire_niO01lOO_dataout; + wire_n011iOlO_dataout <= wire_n011l11O_dataout OR wire_niO01lOO_dataout; + wire_n011iOO_dataout <= wire_n01ilil_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011iOOi_dataout <= wire_n011l10i_dataout OR wire_niO01lOO_dataout; + wire_n011iOOl_dataout <= wire_n011l10l_dataout OR niOliliil; + wire_n011iOOO_dataout <= wire_n011l10O_dataout AND NOT(niOliliil); + wire_n011l01i_dataout <= wire_n011l00i_o(4) OR NOT(niOlil0ll); + wire_n011l01l_dataout <= n011ii1l AND niOlil0li; + wire_n011l0i_dataout <= wire_n01illO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011l0l_dataout <= wire_n01ilOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011l0O_dataout <= wire_n01ilOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011l10i_dataout <= wire_n011l1li_dataout OR niOliliil; + wire_n011l10l_dataout <= wire_n011l1ll_dataout AND n011ii1l; + wire_n011l10O_dataout <= wire_n011l1lO_dataout AND n011ii1l; + wire_n011l11i_dataout <= wire_n011l1ii_dataout OR niOliliil; + wire_n011l11l_dataout <= wire_n011l1il_dataout AND NOT(niOliliil); + wire_n011l11O_dataout <= wire_n011l1iO_dataout OR niOliliil; + wire_n011l1i_dataout <= wire_n01iliO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011l1ii_dataout <= wire_n011l1Oi_dataout OR NOT(n011ii1l); + wire_n011l1il_dataout <= wire_n011l1Ol_dataout OR NOT(n011ii1l); + wire_n011l1iO_dataout <= wire_n011l1OO_dataout OR NOT(n011ii1l); + wire_n011l1l_dataout <= wire_n01illi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011l1li_dataout <= wire_n011l01i_dataout OR NOT(n011ii1l); + wire_n011l1ll_dataout <= n011ii1l WHEN niOlil0ll = '1' ELSE wire_n011l01l_dataout; + wire_n011l1lO_dataout <= niOlil0li AND NOT(niOlil0ll); + wire_n011l1O_dataout <= wire_n01illl_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011l1Oi_dataout <= wire_n011l00i_o(1) OR NOT(niOlil0ll); + wire_n011l1Ol_dataout <= wire_n011l00i_o(2) OR NOT(niOlil0ll); + wire_n011l1OO_dataout <= wire_n011l00i_o(3) OR NOT(niOlil0ll); + wire_n011lii_dataout <= wire_n01ilOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011lil_dataout <= wire_n01iO1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011liO_dataout <= wire_n01iO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011lli_dataout <= wire_n01iO1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011lll_dataout <= wire_n01iO0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011llO_dataout <= wire_n01iO0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011lOi_dataout <= wire_n01iO0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011lOiO_dataout <= wire_n01011il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011lOl_dataout <= wire_n01iOii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011lOli_dataout <= wire_n01011iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011lOll_dataout <= wire_n01011li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011lOlO_dataout <= ((niOlillOi OR niOlilllO) OR niOlillll) AND NOT(wire_niO01lOO_dataout); + wire_n011lOO_dataout <= wire_n01iOil_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011lOOi_dataout <= (n010lOOl AND (niOlilO0O OR niOlilO1l)) AND NOT(wire_niO01lOO_dataout); + wire_n011lOOl_dataout <= wire_n011Oili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011lOOO_dataout <= wire_n011Oill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O00i_dataout <= wire_n01010il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O00l_dataout <= wire_n01010iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O00O_dataout <= wire_n01010li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O01i_dataout <= wire_n010100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O01l_dataout <= wire_n010100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O01O_dataout <= wire_n01010ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0i_dataout <= wire_n01iOlO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011O0ii_dataout <= wire_n01010ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0il_dataout <= wire_n01010lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0iO_dataout <= wire_n01010Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0l_dataout <= wire_n01iOOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011O0li_dataout <= wire_n011OOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0ll_dataout <= wire_n011OOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0lO_dataout <= wire_n011OOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0O_dataout <= wire_n01iOOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011O0Oi_dataout <= wire_n011OOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0Ol_dataout <= wire_n011OOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O0OO_dataout <= wire_n01010Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O10i_dataout <= wire_n011OiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O10l_dataout <= wire_n011Ol1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O10O_dataout <= wire_n011Ol1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O11i_dataout <= wire_n011OilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O11l_dataout <= wire_n011OiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O11O_dataout <= wire_n011OiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1i_dataout <= wire_n01iOiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011O1ii_dataout <= wire_n01011ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1il_dataout <= wire_n01011lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1iO_dataout <= wire_n01011Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1l_dataout <= wire_n01iOli_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011O1li_dataout <= wire_n01011Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1ll_dataout <= wire_n01011OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1lO_dataout <= wire_n010101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1O_dataout <= wire_n01iOll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011O1Oi_dataout <= wire_n010101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1Ol_dataout <= wire_n010101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011O1OO_dataout <= wire_n010100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oi0i_dataout <= wire_n010111O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oi0l_dataout <= wire_n010110i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oi0O_dataout <= wire_n010110l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oi1i_dataout <= wire_n011OOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oi1l_dataout <= wire_n010111i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oi1O_dataout <= wire_n010111l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oii_dataout <= wire_n01iOOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011Oiii_dataout <= wire_n010110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oiil_dataout <= wire_n01011ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011OiiO_dataout <= wire_n01010OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n011Oil_dataout <= wire_n01l11i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011Oili_dataout <= wire_n011Ol1O_dataout AND NOT(niOlili1O); + wire_n011Oill_dataout <= wire_n011Ol0i_dataout AND NOT(niOlili1O); + wire_n011OilO_dataout <= wire_n011Ol0l_dataout AND NOT(niOlili1O); + wire_n011OiO_dataout <= wire_n01l11l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011OiOi_dataout <= wire_n011Ol0O_dataout AND NOT(niOlili1O); + wire_n011OiOl_dataout <= wire_n011Olii_dataout AND NOT(niOlili1O); + wire_n011OiOO_dataout <= wire_n011Olil_dataout AND NOT(niOlili1O); + wire_n011Ol0i_dataout <= wire_n011OllO_dataout AND NOT(niOlili1l); + wire_n011Ol0l_dataout <= wire_n011OlOi_dataout AND NOT(niOlili1l); + wire_n011Ol0O_dataout <= wire_n011OlOl_dataout AND NOT(niOlili1l); + wire_n011Ol1i_dataout <= wire_n011OliO_dataout AND NOT(niOlili1O); + wire_n011Ol1l_dataout <= wire_n011Olli_dataout AND NOT(niOlili1O); + wire_n011Ol1O_dataout <= wire_n011Olll_dataout OR niOlili1l; + wire_n011Oli_dataout <= wire_n01l11O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011Olii_dataout <= wire_n011OlOO_dataout AND NOT(niOlili1l); + wire_n011Olil_dataout <= wire_n011OO1i_dataout AND NOT(niOlili1l); + wire_n011OliO_dataout <= wire_n011OO1l_dataout AND NOT(niOlili1l); + wire_n011Oll_dataout <= wire_n01l10i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011Olli_dataout <= wire_n011OO1O_dataout AND NOT(niOlili1l); + wire_n011Olll_dataout <= wire_n011OO0i_o(0) WHEN niOlil0OO = '1' ELSE n011l0lO; + wire_n011OllO_dataout <= wire_n011OO0i_o(1) WHEN niOlil0OO = '1' ELSE n011l0Oi; + wire_n011OlO_dataout <= wire_n01l10l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011OlOi_dataout <= wire_n011OO0i_o(2) WHEN niOlil0OO = '1' ELSE n011l0Ol; + wire_n011OlOl_dataout <= wire_n011OO0i_o(3) WHEN niOlil0OO = '1' ELSE n011l0OO; + wire_n011OlOO_dataout <= wire_n011OO0i_o(4) WHEN niOlil0OO = '1' ELSE n011li1i; + wire_n011OO1i_dataout <= wire_n011OO0i_o(5) WHEN niOlil0OO = '1' ELSE n011li1l; + wire_n011OO1l_dataout <= wire_n011OO0i_o(6) WHEN niOlil0OO = '1' ELSE n011li1O; + wire_n011OO1O_dataout <= wire_n011OO0i_o(7) WHEN niOlil0OO = '1' ELSE n011li0i; + wire_n011OOi_dataout <= wire_n01l1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011OOl_dataout <= wire_n01l1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011OOli_dataout <= n011llil WHEN niOlO1O0i = '1' ELSE wire_n0101lii_dataout; + wire_n011OOll_dataout <= n011lliO WHEN niOlO1O0i = '1' ELSE wire_n0101lil_dataout; + wire_n011OOlO_dataout <= n011llli WHEN niOlO1O0i = '1' ELSE wire_n0101liO_dataout; + wire_n011OOO_dataout <= wire_n01l1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_n011OOOi_dataout <= n011llll WHEN niOlO1O0i = '1' ELSE wire_n0101lli_dataout; + wire_n011OOOl_dataout <= n011lllO WHEN niOlO1O0i = '1' ELSE wire_n0101lll_dataout; + wire_n011OOOO_dataout <= n011llOl WHEN niOlO1O0i = '1' ELSE wire_n0101lOi_dataout; + wire_n01i000i_dataout <= wire_n1OOl0ll_dataout WHEN niOliO00O = '1' ELSE wire_n01i00Oi_dataout; + wire_n01i000l_dataout <= wire_n1OOl0iO_dataout WHEN niOliO00O = '1' ELSE wire_n01i00Ol_dataout; + wire_n01i000O_dataout <= wire_n1OOl0ii_dataout WHEN niOliO00O = '1' ELSE wire_n01i00OO_dataout; + wire_n01i001O_dataout <= wire_n1OOl0Oi_dataout WHEN niOliO00O = '1' ELSE wire_n01i00lO_dataout; + wire_n01i00i_dataout <= wire_n01O0Ol_dataout WHEN n1O0liO = '1' ELSE n1OiOiO; + wire_n01i00ii_dataout <= wire_n1OOl00l_dataout WHEN niOliO00O = '1' ELSE wire_n01i0i1i_dataout; + wire_n01i00il_dataout <= wire_n1OOl01l_dataout WHEN niOliO00O = '1' ELSE wire_n01i0i1l_dataout; + wire_n01i00iO_dataout <= wire_n1OOl1OO_dataout WHEN niOliO00O = '1' ELSE wire_n01i0i1O_dataout; + wire_n01i00l_dataout <= wire_n01O0OO_dataout WHEN n1O0liO = '1' ELSE n1OiOli; + wire_n01i00li_dataout <= wire_n1OOl1lO_dataout WHEN niOliO00O = '1' ELSE wire_n01i0i0i_dataout; + wire_n01i00ll_dataout <= n01iOiii WHEN niOliO00O = '1' ELSE wire_n01i0i0l_dataout; + wire_n01i00lO_dataout <= wire_n01i0iii_dataout AND NOT(niOliO00i); + wire_n01i00O_dataout <= wire_n01Oi1i_dataout WHEN n1O0liO = '1' ELSE n1OiOll; + wire_n01i00Oi_dataout <= wire_n01i0iil_dataout AND NOT(niOliO00i); + wire_n01i00Ol_dataout <= wire_n01i0iiO_dataout OR niOliO00i; + wire_n01i00OO_dataout <= wire_n01i0ili_dataout OR niOliO00i; + wire_n01i011i_dataout <= wire_n01i011l_dataout OR (wire_niO01ill_w_lg_n01iOi1l17003w(0) AND wire_n010OlOO_w_lg_w_lg_w_lg_dataout17133w17139w17140w(0)); + wire_n01i011l_dataout <= n01i101O AND nlOllOliO; + wire_n01i01i_dataout <= wire_n01O0ll_dataout WHEN n1O0liO = '1' ELSE n1OiO0O; + wire_n01i01l_dataout <= wire_n01O0lO_dataout WHEN n1O0liO = '1' ELSE n1OiOii; + wire_n01i01lO_dataout <= wire_n01i01Oi_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n01iOi0i AND n01i11lO)) OR (n01iOi0i AND n01i110i)); + wire_n01i01O_dataout <= wire_n01O0Oi_dataout WHEN n1O0liO = '1' ELSE n1OiOil; + wire_n01i01Oi_dataout <= n010Oi1O AND nlOllOliO; + wire_n01i0i0i_dataout <= wire_n01i0iOl_dataout OR niOliO00i; + wire_n01i0i0l_dataout <= wire_n01i0i0O_dataout OR niOliO00i; + wire_n01i0i0O_dataout <= wire_n01i0lil_dataout AND NOT(niOliO01i); + wire_n01i0i1i_dataout <= wire_n01i0ill_dataout OR niOliO00i; + wire_n01i0i1l_dataout <= wire_n01i0ilO_dataout OR niOliO00i; + wire_n01i0i1O_dataout <= wire_n01i0iOi_dataout AND NOT(niOliO00i); + wire_n01i0ii_dataout <= wire_n01Oi1l_dataout WHEN n1O0liO = '1' ELSE n1OiOlO; + wire_n01i0iii_dataout <= wire_n01i0iOO_dataout AND NOT(niOliO01i); + wire_n01i0iil_dataout <= wire_n01i0l1i_dataout AND NOT(niOliO01i); + wire_n01i0iiO_dataout <= wire_n01i0l1l_dataout AND NOT(niOliO01i); + wire_n01i0il_dataout <= wire_n01Oi1O_dataout WHEN n1O0liO = '1' ELSE n1OiOOi; + wire_n01i0ili_dataout <= wire_n01i0l1O_dataout AND NOT(niOliO01i); + wire_n01i0ill_dataout <= wire_n01i0l0i_dataout AND NOT(niOliO01i); + wire_n01i0ilO_dataout <= wire_n01i0l0l_dataout AND NOT(niOliO01i); + wire_n01i0iO_dataout <= wire_n01Oi0i_dataout WHEN n1O0liO = '1' ELSE n1OiOOl; + wire_n01i0iOi_dataout <= wire_n01i0l0O_dataout AND NOT(niOliO01i); + wire_n01i0iOl_dataout <= wire_n01i0lii_dataout AND NOT(niOliO01i); + wire_n01i0iOO_dataout <= wire_n01i0liO_dataout AND NOT(niOliO1Ol); + wire_n01i0l0i_dataout <= wire_n01i0lOi_dataout OR niOliO1Ol; + wire_n01i0l0l_dataout <= wire_n01i0lOl_dataout OR niOliO1Ol; + wire_n01i0l0O_dataout <= wire_n01i0lOO_dataout OR niOliO1Ol; + wire_n01i0l1i_dataout <= wire_n01i0lli_dataout AND NOT(niOliO1Ol); + wire_n01i0l1l_dataout <= wire_n01i0lll_dataout OR niOliO1Ol; + wire_n01i0l1O_dataout <= wire_n01i0llO_dataout OR niOliO1Ol; + wire_n01i0li_dataout <= wire_n01Oi0l_dataout WHEN n1O0liO = '1' ELSE n1OiOOO; + wire_n01i0lii_dataout <= wire_n01i0O1i_dataout AND NOT(niOliO1Ol); + wire_n01i0lil_dataout <= wire_n01i0O1l_dataout OR niOliO1Ol; + wire_n01i0liO_dataout <= wire_n01i0O1O_dataout OR niOliO1Oi; + wire_n01i0ll_dataout <= wire_n01Oi0O_dataout WHEN n1O0liO = '1' ELSE n1Ol11i; + wire_n01i0lli_dataout <= wire_n01i0O0i_dataout AND NOT(niOliO1Oi); + wire_n01i0lll_dataout <= wire_n01i0O0l_dataout OR niOliO1Oi; + wire_n01i0llO_dataout <= wire_n01i0O0O_dataout AND NOT(niOliO1Oi); + wire_n01i0lO_dataout <= wire_n01Oiii_dataout WHEN n1O0liO = '1' ELSE n1Ol11l; + wire_n01i0lOi_dataout <= wire_n01i0Oii_dataout OR niOliO1Oi; + wire_n01i0lOl_dataout <= wire_n01i0Oil_dataout OR niOliO1Oi; + wire_n01i0lOO_dataout <= wire_n01i0OiO_dataout AND NOT(niOliO1Oi); + wire_n01i0O0i_dataout <= wire_n01i0OOi_dataout OR niOliO1lO; + wire_n01i0O0l_dataout <= wire_n01i0OOl_dataout AND NOT(niOliO1lO); + wire_n01i0O0O_dataout <= wire_n01i0OOO_dataout OR niOliO1lO; + wire_n01i0O1i_dataout <= wire_n01i0Oli_dataout OR niOliO1Oi; + wire_n01i0O1l_dataout <= wire_n01i0Oll_dataout AND NOT(niOliO1Oi); + wire_n01i0O1O_dataout <= wire_n01i0OlO_dataout AND NOT(niOliO1lO); + wire_n01i0Oi_dataout <= wire_n01Oiil_dataout WHEN n1O0liO = '1' ELSE n1Ol11O; + wire_n01i0Oii_dataout <= wire_n01ii11i_dataout AND NOT(niOliO1lO); + wire_n01i0Oil_dataout <= wire_n01ii11l_dataout AND NOT(niOliO1lO); + wire_n01i0OiO_dataout <= wire_n01ii11O_dataout OR niOliO1lO; + wire_n01i0Ol_dataout <= wire_n01OiiO_dataout WHEN n1O0liO = '1' ELSE n1Ol10i; + wire_n01i0Oli_dataout <= wire_n01ii10i_dataout AND NOT(niOliO1lO); + wire_n01i0Oll_dataout <= wire_n01ii10l_dataout AND NOT(niOliO1lO); + wire_n01i0OlO_dataout <= wire_n01iilOl_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii10O_dataout; + wire_n01i0OO_dataout <= wire_n01Oili_dataout WHEN n1O0liO = '1' ELSE n1Ol10l; + wire_n01i0OOi_dataout <= wire_n01iilOO_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1ii_dataout; + wire_n01i0OOl_dataout <= wire_n01iiO1i_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1il_dataout; + wire_n01i0OOO_dataout <= wire_n01iiO1l_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1iO_dataout; + wire_n01i100i_dataout <= wire_n01i01lO_dataout OR wire_niO01lOO_dataout; + wire_n01i100l_dataout <= wire_n01i001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i100O_dataout <= wire_n01i000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10i_dataout <= wire_n01O1Ol_dataout WHEN n1O0liO = '1' ELSE n1OiliO; + wire_n01i10ii_dataout <= wire_n01i000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10il_dataout <= wire_n01i000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10iO_dataout <= wire_n01i00ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10l_dataout <= wire_n01O1OO_dataout WHEN n1O0liO = '1' ELSE n1Oilli; + wire_n01i10li_dataout <= wire_n01i00il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10ll_dataout <= wire_n01i00iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10lO_dataout <= wire_n01i00li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10O_dataout <= wire_n01O01i_dataout WHEN n1O0liO = '1' ELSE n1Oilll; + wire_n01i10Oi_dataout <= wire_n01i00ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10Ol_dataout <= wire_n01i1l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i10OO_dataout <= wire_n01i1l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i11i_dataout <= wire_n01O1ll_dataout WHEN n1O0liO = '1' ELSE n1Oil0O; + wire_n01i11l_dataout <= wire_n01O1lO_dataout WHEN n1O0liO = '1' ELSE n1Oilii; + wire_n01i11O_dataout <= wire_n01O1Oi_dataout WHEN n1O0liO = '1' ELSE n1Oilil; + wire_n01i1i0i_dataout <= wire_n01i1l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1i0l_dataout <= wire_n01i1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1i0O_dataout <= wire_n01i1O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1i1i_dataout <= wire_n01i1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1i1l_dataout <= wire_n01i1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1i1O_dataout <= wire_n01i1l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1ii_dataout <= wire_n01O01l_dataout WHEN n1O0liO = '1' ELSE n1OillO; + wire_n01i1iii_dataout <= wire_n01iO11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1iil_dataout <= wire_n01iO11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1iiO_dataout <= wire_n01iO10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1il_dataout <= wire_n01O01O_dataout WHEN n1O0liO = '1' ELSE n1OilOi; + wire_n01i1ili_dataout <= wire_n01iO10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1ill_dataout <= wire_n01iO10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1ilO_dataout <= wire_n01iO1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1iO_dataout <= wire_n01O00i_dataout WHEN n1O0liO = '1' ELSE n1OilOl; + wire_n01i1iOi_dataout <= wire_n01iO0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1iOl_dataout <= wire_n01i1Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1iOO_dataout <= wire_n01i1OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01i1l0i_dataout <= wire_n01i1lll_dataout AND NOT(niOlilOlO); + wire_n01i1l0l_dataout <= wire_n01i1llO_dataout AND NOT(niOlilOlO); + wire_n01i1l0O_dataout <= wire_n01i1lOi_dataout AND NOT(niOlilOlO); + wire_n01i1l1i_dataout <= wire_n01i1lil_dataout AND NOT(niOlilOlO); + wire_n01i1l1l_dataout <= wire_n01i1liO_dataout AND NOT(niOlilOlO); + wire_n01i1l1O_dataout <= wire_n01i1lli_dataout AND NOT(niOlilOlO); + wire_n01i1li_dataout <= wire_n01O00l_dataout WHEN n1O0liO = '1' ELSE n1OilOO; + wire_n01i1lii_dataout <= wire_n01i1lOl_dataout AND NOT(niOlilOlO); + wire_n01i1lil_dataout <= wire_n01i1lOO_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i111l; + wire_n01i1liO_dataout <= wire_n01i1lOO_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i111O; + wire_n01i1ll_dataout <= wire_n01O00O_dataout WHEN n1O0liO = '1' ELSE n1OiO1i; + wire_n01i1lli_dataout <= wire_n01i1lOO_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i110i; + wire_n01i1lll_dataout <= wire_n01i1lOO_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i110l; + wire_n01i1llO_dataout <= wire_n01i1lOO_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i110O; + wire_n01i1lO_dataout <= wire_n01O0ii_dataout WHEN n1O0liO = '1' ELSE n1OiO1l; + wire_n01i1lOi_dataout <= wire_n01i1lOO_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11ii; + wire_n01i1lOl_dataout <= wire_n01i1lOO_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11il; + wire_n01i1O0i_dataout <= wire_n01i1O0l_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17005w(0) AND wire_w_lg_niOliO0iO17006w(0)); + wire_n01i1O0l_dataout <= n01i11iO AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOliO0li17152w(0))); + wire_n01i1Oi_dataout <= wire_n01O0il_dataout WHEN n1O0liO = '1' ELSE n1OiO1O; + wire_n01i1OiO_dataout <= n01i101l WHEN nlOllOliO = '1' ELSE wire_n01i1Oli_dataout; + wire_n01i1Ol_dataout <= wire_n01O0iO_dataout WHEN n1O0liO = '1' ELSE n1OiO0i; + wire_n01i1Oli_dataout <= wire_n01i1Oll_dataout OR niOliO01l; + wire_n01i1Oll_dataout <= wire_n01i1OlO_dataout OR n01iOi0l; + wire_n01i1OlO_dataout <= wire_n01i1OOi_dataout OR (wire_niO01ill_w_lg_n01iOi1l17003w(0) AND (wire_n010OlOO_dataout AND niOliO1ll)); + wire_n01i1OO_dataout <= wire_n01O0li_dataout WHEN n1O0liO = '1' ELSE n1OiO0l; + wire_n01i1OOi_dataout <= wire_n01i1OOO_dataout OR (wire_niO01ill_w_lg_n01iOi1l17003w(0) AND (wire_n010OlOO_dataout AND niOliO10i)); + wire_n01i1OOO_dataout <= wire_n01i011i_dataout OR (wire_niO01ill_w_lg_n01iOi1l17003w(0) AND wire_n010OlOO_w_lg_dataout17146w(0)); + wire_n01ii00i_dataout <= wire_n01ii0Oi_dataout OR niOliO11i; + wire_n01ii00l_dataout <= wire_n01ii0Ol_dataout OR niOliO11i; + wire_n01ii00O_dataout <= wire_n01ii0OO_dataout OR niOliO11i; + wire_n01ii01i_dataout <= wire_n01ii0li_dataout AND NOT(niOliO11i); + wire_n01ii01l_dataout <= wire_n01ii0ll_dataout OR niOliO11i; + wire_n01ii01O_dataout <= wire_n01ii0lO_dataout OR niOliO11i; + wire_n01ii0i_dataout <= wire_n01OiOl_dataout WHEN n1O0liO = '1' ELSE n1Ol1iO; + wire_n01ii0ii_dataout <= wire_n01iii1i_dataout AND NOT(niOliO11i); + wire_n01ii0il_dataout <= wire_n01iii1l_dataout OR niOliO11i; + wire_n01ii0iO_dataout <= wire_n01iii1O_dataout AND NOT(niOlilOOO); + wire_n01ii0l_dataout <= wire_n01OiOO_dataout WHEN n1O0liO = '1' ELSE n1Ol1li; + wire_n01ii0li_dataout <= wire_n01iii0i_dataout AND NOT(niOlilOOO); + wire_n01ii0ll_dataout <= wire_n01iii0l_dataout AND NOT(niOlilOOO); + wire_n01ii0lO_dataout <= wire_n01iii0O_dataout AND NOT(niOlilOOO); + wire_n01ii0O_dataout <= wire_n01Ol1i_dataout WHEN n1O0liO = '1' ELSE n1Ol1ll; + wire_n01ii0Oi_dataout <= wire_n01iiiii_dataout AND NOT(niOlilOOO); + wire_n01ii0Ol_dataout <= wire_n01iiiil_dataout AND NOT(niOlilOOO); + wire_n01ii0OO_dataout <= wire_n01iiiiO_dataout AND NOT(niOlilOOO); + wire_n01ii10i_dataout <= wire_n01iiO0O_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1Oi_dataout; + wire_n01ii10l_dataout <= wire_n01iiOii_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1Ol_dataout; + wire_n01ii10O_dataout <= wire_n01ii1OO_dataout AND NOT(niOliO11l); + wire_n01ii11i_dataout <= wire_n01iiO1O_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1li_dataout; + wire_n01ii11l_dataout <= wire_n01iiO0i_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1ll_dataout; + wire_n01ii11O_dataout <= wire_n01iiO0l_dataout WHEN wire_n010OlOO_dataout = '1' ELSE wire_n01ii1lO_dataout; + wire_n01ii1i_dataout <= wire_n01Oill_dataout WHEN n1O0liO = '1' ELSE n1Ol10O; + wire_n01ii1ii_dataout <= wire_n01ii01i_dataout AND NOT(niOliO11l); + wire_n01ii1il_dataout <= wire_n01ii01l_dataout OR niOliO11l; + wire_n01ii1iO_dataout <= wire_n01ii01O_dataout OR niOliO11l; + wire_n01ii1l_dataout <= wire_n01OilO_dataout WHEN n1O0liO = '1' ELSE n1Ol1ii; + wire_n01ii1li_dataout <= wire_n01ii00i_dataout OR niOliO11l; + wire_n01ii1ll_dataout <= wire_n01ii00l_dataout OR niOliO11l; + wire_n01ii1lO_dataout <= wire_n01ii00O_dataout AND NOT(niOliO11l); + wire_n01ii1O_dataout <= wire_n01OiOi_dataout WHEN n1O0liO = '1' ELSE n1Ol1il; + wire_n01ii1Oi_dataout <= wire_n01ii0ii_dataout OR niOliO11l; + wire_n01ii1Ol_dataout <= wire_n01ii0il_dataout OR niOliO11l; + wire_n01ii1OO_dataout <= wire_n01ii0iO_dataout AND NOT(niOliO11i); + wire_n01iii0i_dataout <= n010O0lO WHEN niOlilOOi = '1' ELSE wire_n01iiiOi_dataout; + wire_n01iii0l_dataout <= n010O0Oi WHEN niOlilOOi = '1' ELSE wire_n01iiiOl_dataout; + wire_n01iii0O_dataout <= n010O0Ol WHEN niOlilOOi = '1' ELSE wire_n01iiiOO_dataout; + wire_n01iii1i_dataout <= wire_n01iiili_dataout AND NOT(niOlilOOO); + wire_n01iii1l_dataout <= wire_n01iiill_dataout AND NOT(niOlilOOO); + wire_n01iii1O_dataout <= n010lOOO WHEN niOlilOOi = '1' ELSE wire_n01iiilO_dataout; + wire_n01iiii_dataout <= wire_n01Ol1l_dataout WHEN n1O0liO = '1' ELSE n1Ol1lO; + wire_n01iiiii_dataout <= n010O0OO WHEN niOlilOOi = '1' ELSE wire_n01iil1i_dataout; + wire_n01iiiil_dataout <= n010Oi1i WHEN niOlilOOi = '1' ELSE wire_n01iil1l_dataout; + wire_n01iiiiO_dataout <= n010Oi1l WHEN niOlilOOi = '1' ELSE wire_n01iil1O_dataout; + wire_n01iiil_dataout <= wire_n01Ol1O_dataout WHEN n1O0liO = '1' ELSE n1Ol1Oi; + wire_n01iiili_dataout <= n011i00l WHEN niOlilOOi = '1' ELSE wire_n01iil0i_dataout; + wire_n01iiill_dataout <= wire_n01iil0l_dataout AND NOT(niOlilOOi); + wire_n01iiilO_dataout <= n010OOil WHEN niOlilOOl = '1' ELSE wire_n1OOl0Oi_dataout; + wire_n01iiiO_dataout <= wire_n01Ol0i_dataout WHEN n1O0liO = '1' ELSE n1Ol1Ol; + wire_n01iiiOi_dataout <= n010OOiO WHEN niOlilOOl = '1' ELSE wire_n1OOl0ll_dataout; + wire_n01iiiOl_dataout <= n010OOli WHEN niOlilOOl = '1' ELSE wire_n1OOl0iO_dataout; + wire_n01iiiOO_dataout <= n010OOll WHEN niOlilOOl = '1' ELSE wire_n1OOl0ii_dataout; + wire_n01iil0i_dataout <= n010OOOO WHEN niOlilOOl = '1' ELSE wire_n1OOl1lO_dataout; + wire_n01iil0l_dataout <= n01iOiii AND NOT(niOlilOOl); + wire_n01iil1i_dataout <= n010OOlO WHEN niOlilOOl = '1' ELSE wire_n1OOl00l_dataout; + wire_n01iil1l_dataout <= n010OOOi WHEN niOlilOOl = '1' ELSE wire_n1OOl01l_dataout; + wire_n01iil1O_dataout <= n010OOOl WHEN niOlilOOl = '1' ELSE wire_n1OOl1OO_dataout; + wire_n01iili_dataout <= wire_n01Ol0l_dataout WHEN n1O0liO = '1' ELSE n1Ol1OO; + wire_n01iill_dataout <= wire_n01Ol0O_dataout WHEN n1O0liO = '1' ELSE n1Ol01i; + wire_n01iilO_dataout <= wire_n01Olii_dataout WHEN n1O0liO = '1' ELSE n1Ol01l; + wire_n01iilOl_dataout <= wire_n01iiOil_dataout AND NOT(niOliO11O); + wire_n01iilOO_dataout <= wire_n01iiOiO_dataout AND NOT(niOliO11O); + wire_n01iiO0i_dataout <= wire_n01iiOOi_dataout OR niOliO11O; + wire_n01iiO0l_dataout <= wire_n01iiOOl_dataout AND NOT(niOliO11O); + wire_n01iiO0O_dataout <= wire_n01iiOOO_dataout OR niOliO11O; + wire_n01iiO1i_dataout <= wire_n01iiOli_dataout OR niOliO11O; + wire_n01iiO1l_dataout <= wire_n01iiOll_dataout OR niOliO11O; + wire_n01iiO1O_dataout <= wire_n01iiOlO_dataout OR niOliO11O; + wire_n01iiOi_dataout <= wire_n01Olil_dataout WHEN n1O0liO = '1' ELSE n1Ol01O; + wire_n01iiOii_dataout <= wire_n01il11i_dataout OR niOliO11O; + wire_n01iiOil_dataout <= wire_n01il11l_dataout AND NOT(niOliO10i); + wire_n01iiOiO_dataout <= wire_n01il11O_dataout AND NOT(niOliO10i); + wire_n01iiOl_dataout <= wire_n01OliO_dataout WHEN n1O0liO = '1' ELSE n1Ol00i; + wire_n01iiOli_dataout <= wire_n01il10i_dataout OR niOliO10i; + wire_n01iiOll_dataout <= wire_n01il10l_dataout OR niOliO10i; + wire_n01iiOlO_dataout <= wire_n01il10O_dataout OR niOliO10i; + wire_n01iiOO_dataout <= wire_n01Olli_dataout WHEN n1O0liO = '1' ELSE n1Ol00l; + wire_n01iiOOi_dataout <= wire_n01il1ii_dataout OR niOliO10i; + wire_n01iiOOl_dataout <= wire_n01il1il_dataout AND NOT(niOliO10i); + wire_n01iiOOO_dataout <= wire_n01il1iO_dataout OR niOliO10i; + wire_n01il00i_dataout <= wire_n01il0Oi_dataout OR niOliO10O; + wire_n01il00l_dataout <= wire_n01il0Ol_dataout AND NOT(niOliO1ii); + wire_n01il00O_dataout <= wire_n01il0OO_dataout OR niOliO1ii; + wire_n01il01i_dataout <= wire_n01il0li_dataout OR niOliO10O; + wire_n01il01l_dataout <= wire_n01il0ll_dataout AND NOT(niOliO10O); + wire_n01il01O_dataout <= wire_n01il0lO_dataout OR niOliO10O; + wire_n01il0i_dataout <= wire_n01OlOl_dataout WHEN n1O0liO = '1' ELSE n1Ol0iO; + wire_n01il0ii_dataout <= wire_n01ili1i_dataout AND NOT(niOliO1ii); + wire_n01il0il_dataout <= wire_n01ili1l_dataout OR niOliO1ii; + wire_n01il0iO_dataout <= wire_n01ili1O_dataout AND NOT(niOliO1ii); + wire_n01il0l_dataout <= wire_n01OlOO_dataout WHEN n1O0liO = '1' ELSE n1Ol0li; + wire_n01il0li_dataout <= wire_n01ili0i_dataout AND NOT(niOliO1ii); + wire_n01il0ll_dataout <= wire_n01ili0l_dataout OR niOliO1ii; + wire_n01il0lO_dataout <= wire_n01ili0O_dataout AND NOT(niOliO1ii); + wire_n01il0O_dataout <= wire_n01OO1i_dataout WHEN n1O0liO = '1' ELSE n1Ol0ll; + wire_n01il0Oi_dataout <= wire_n01iliii_dataout AND NOT(niOliO1ii); + wire_n01il0Ol_dataout <= n010lOOO WHEN niOliO1il = '1' ELSE wire_n01iliil_dataout; + wire_n01il0OO_dataout <= n010O0lO WHEN niOliO1il = '1' ELSE wire_n01iliiO_dataout; + wire_n01il10i_dataout <= wire_n01il1Oi_dataout OR niOliO10l; + wire_n01il10l_dataout <= wire_n01il1Ol_dataout AND NOT(niOliO10l); + wire_n01il10O_dataout <= wire_n01il1OO_dataout OR niOliO10l; + wire_n01il11i_dataout <= wire_n01il1li_dataout OR niOliO10i; + wire_n01il11l_dataout <= wire_n01il1ll_dataout OR niOliO10l; + wire_n01il11O_dataout <= wire_n01il1lO_dataout AND NOT(niOliO10l); + wire_n01il1i_dataout <= wire_n01Olll_dataout WHEN n1O0liO = '1' ELSE n1Ol00O; + wire_n01il1ii_dataout <= wire_n01il01i_dataout OR niOliO10l; + wire_n01il1il_dataout <= wire_n01il01l_dataout AND NOT(niOliO10l); + wire_n01il1iO_dataout <= wire_n01il01O_dataout OR niOliO10l; + wire_n01il1l_dataout <= wire_n01OllO_dataout WHEN n1O0liO = '1' ELSE n1Ol0ii; + wire_n01il1li_dataout <= wire_n01il00i_dataout AND NOT(niOliO10l); + wire_n01il1ll_dataout <= wire_n01il00l_dataout AND NOT(niOliO10O); + wire_n01il1lO_dataout <= wire_n01il00O_dataout AND NOT(niOliO10O); + wire_n01il1O_dataout <= wire_n01OlOi_dataout WHEN n1O0liO = '1' ELSE n1Ol0il; + wire_n01il1Oi_dataout <= wire_n01il0ii_dataout OR niOliO10O; + wire_n01il1Ol_dataout <= wire_n01il0il_dataout OR niOliO10O; + wire_n01il1OO_dataout <= wire_n01il0iO_dataout OR niOliO10O; + wire_n01ili0i_dataout <= n010Oi1i WHEN niOliO1il = '1' ELSE wire_n01iliOi_dataout; + wire_n01ili0l_dataout <= n010Oi1l WHEN niOliO1il = '1' ELSE wire_n01iliOl_dataout; + wire_n01ili0O_dataout <= n011i00l WHEN niOliO1il = '1' ELSE wire_n01iliOO_dataout; + wire_n01ili1i_dataout <= n010O0Oi WHEN niOliO1il = '1' ELSE wire_n01ilili_dataout; + wire_n01ili1l_dataout <= n010O0Ol WHEN niOliO1il = '1' ELSE wire_n01ilill_dataout; + wire_n01ili1O_dataout <= n010O0OO WHEN niOliO1il = '1' ELSE wire_n01ililO_dataout; + wire_n01ilii_dataout <= wire_n01OO1l_dataout WHEN n1O0liO = '1' ELSE n1Ol0lO; + wire_n01iliii_dataout <= wire_n01ill1i_dataout AND NOT(niOliO1il); + wire_n01iliil_dataout <= n010OOil WHEN niOliO1iO = '1' ELSE wire_n01ill1l_dataout; + wire_n01iliiO_dataout <= n010OOiO WHEN niOliO1iO = '1' ELSE wire_n01ill1O_dataout; + wire_n01ilil_dataout <= wire_n01OO1O_dataout WHEN n1O0liO = '1' ELSE n1Ol0Oi; + wire_n01ilili_dataout <= n010OOli WHEN niOliO1iO = '1' ELSE wire_n01ill0i_dataout; + wire_n01ilill_dataout <= n010OOll WHEN niOliO1iO = '1' ELSE wire_n01ill0l_dataout; + wire_n01ililO_dataout <= n010OOlO WHEN niOliO1iO = '1' ELSE wire_n01ill0O_dataout; + wire_n01iliO_dataout <= wire_n01OO0i_dataout WHEN n1O0liO = '1' ELSE n1Ol0Ol; + wire_n01iliOi_dataout <= n010OOOi WHEN niOliO1iO = '1' ELSE wire_n01illii_dataout; + wire_n01iliOl_dataout <= n010OOOl WHEN niOliO1iO = '1' ELSE wire_n01illil_dataout; + wire_n01iliOO_dataout <= n010OOOO WHEN niOliO1iO = '1' ELSE wire_n01illiO_dataout; + wire_n01ill0i_dataout <= wire_n01illOi_dataout OR niOliO1li; + wire_n01ill0l_dataout <= wire_n01illOl_dataout OR niOliO1li; + wire_n01ill0O_dataout <= wire_n01illOO_dataout OR niOliO1li; + wire_n01ill1i_dataout <= wire_n01illli_dataout AND NOT(niOliO1iO); + wire_n01ill1l_dataout <= wire_n01illll_dataout AND NOT(niOliO1li); + wire_n01ill1O_dataout <= wire_n01illlO_dataout AND NOT(niOliO1li); + wire_n01illi_dataout <= wire_n01OO0l_dataout WHEN n1O0liO = '1' ELSE n1Ol0OO; + wire_n01illii_dataout <= wire_n01ilO1i_dataout OR niOliO1li; + wire_n01illil_dataout <= wire_n01ilO1l_dataout AND NOT(niOliO1li); + wire_n01illiO_dataout <= wire_n01ilO1O_dataout OR niOliO1li; + wire_n01illl_dataout <= wire_n01OO0O_dataout WHEN n1O0liO = '1' ELSE n1Oli1i; + wire_n01illli_dataout <= wire_n01ilO0i_dataout OR niOliO1li; + wire_n01illll_dataout <= n010OOil AND NOT(niOliO1ll); + wire_n01illlO_dataout <= n010OOiO AND NOT(niOliO1ll); + wire_n01illO_dataout <= wire_n01OOii_dataout WHEN n1O0liO = '1' ELSE n1Oli1l; + wire_n01illOi_dataout <= n010OOli OR niOliO1ll; + wire_n01illOl_dataout <= n010OOll OR niOliO1ll; + wire_n01illOO_dataout <= n010OOlO OR niOliO1ll; + wire_n01ilO0i_dataout <= n01i111i OR niOliO1ll; + wire_n01ilO1i_dataout <= n010OOOi OR niOliO1ll; + wire_n01ilO1l_dataout <= n010OOOl OR niOliO1ll; + wire_n01ilO1O_dataout <= n010OOOO OR niOliO1ll; + wire_n01ilOi_dataout <= wire_n01OOil_dataout WHEN n1O0liO = '1' ELSE n1Oli1O; + wire_n01ilOl_dataout <= wire_n01OOiO_dataout WHEN n1O0liO = '1' ELSE n1Oli0i; + wire_n01ilOO_dataout <= wire_n01OOli_dataout WHEN n1O0liO = '1' ELSE n1Oli0l; + wire_n01iO00i_dataout <= wire_n01iO00l_o(5) WHEN niOliO0ii = '1' ELSE n01i11OO; + wire_n01iO01i_dataout <= wire_n01iO00l_o(2) WHEN niOliO0ii = '1' ELSE n01i11lO; + wire_n01iO01l_dataout <= wire_n01iO00l_o(3) WHEN niOliO0ii = '1' ELSE n01i11Oi; + wire_n01iO01O_dataout <= wire_n01iO00l_o(4) WHEN niOliO0ii = '1' ELSE n01i11Ol; + wire_n01iO0i_dataout <= wire_n01OOOl_dataout WHEN n1O0liO = '1' ELSE n1OliiO; + wire_n01iO0l_dataout <= wire_n01OOOO_dataout WHEN n1O0liO = '1' ELSE n1Olili; + wire_n01iO0li_dataout <= wire_n01iO0ll_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17000w(0) AND wire_w_lg_niOliO0ll17001w(0)); + wire_n01iO0ll_dataout <= n01i101i AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOliO0lO17009w(0))); + wire_n01iO0O_dataout <= wire_n00111i_dataout WHEN n1O0liO = '1' ELSE n1Olill; + wire_n01iO10i_dataout <= wire_n01iO1li_dataout AND NOT(niOliO0il); + wire_n01iO10l_dataout <= wire_n01iO1ll_dataout AND NOT(niOliO0il); + wire_n01iO10O_dataout <= wire_n01iO1lO_dataout AND NOT(niOliO0il); + wire_n01iO11l_dataout <= wire_n01iO1il_dataout AND NOT(niOliO0il); + wire_n01iO11O_dataout <= wire_n01iO1iO_dataout AND NOT(niOliO0il); + wire_n01iO1i_dataout <= wire_n01OOll_dataout WHEN n1O0liO = '1' ELSE n1Oli0O; + wire_n01iO1ii_dataout <= wire_n01iO1Oi_dataout AND NOT(niOliO0il); + wire_n01iO1il_dataout <= wire_n01iO1Ol_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11li; + wire_n01iO1iO_dataout <= wire_n01iO1OO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11ll; + wire_n01iO1l_dataout <= wire_n01OOlO_dataout WHEN n1O0liO = '1' ELSE n1Oliii; + wire_n01iO1li_dataout <= wire_n01iO01i_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11lO; + wire_n01iO1ll_dataout <= wire_n01iO01l_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11Oi; + wire_n01iO1lO_dataout <= wire_n01iO01O_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11Ol; + wire_n01iO1O_dataout <= wire_n01OOOi_dataout WHEN n1O0liO = '1' ELSE n1Oliil; + wire_n01iO1Oi_dataout <= wire_n01iO00i_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n01i11OO; + wire_n01iO1Ol_dataout <= wire_n01iO00l_o(0) WHEN niOliO0ii = '1' ELSE n01i11li; + wire_n01iO1OO_dataout <= wire_n01iO00l_o(1) WHEN niOliO0ii = '1' ELSE n01i11ll; + wire_n01iOii_dataout <= wire_n00111l_dataout WHEN n1O0liO = '1' ELSE n1OlilO; + wire_n01iOil_dataout <= wire_n00111O_dataout WHEN n1O0liO = '1' ELSE n1OliOi; + wire_n01iOiO_dataout <= wire_n00110i_dataout WHEN n1O0liO = '1' ELSE n1OliOl; + wire_n01iOl0i_dataout <= wire_n01iOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOl0l_dataout <= n01iOi0i AND NOT(wire_niO01lOO_dataout); + wire_n01iOl0O_dataout <= nlOllOliO AND NOT(wire_niO01lOO_dataout); + wire_n01iOl1i_dataout <= wire_n01iOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOl1l_dataout <= wire_n01iOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOl1O_dataout <= wire_n01iOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOli_dataout <= wire_n00110l_dataout WHEN n1O0liO = '1' ELSE n1OliOO; + wire_n01iOlii_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17005w(0) AND wire_w_lg_niOliO0iO17006w(0)) AND wire_niO01ill_w_lg_n01iOi1l17003w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n01iOlil_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17000w(0) AND wire_w_lg_niOliO0ll17001w(0)) AND wire_niO01ill_w_lg_n01iOi1l17003w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n01iOliO_dataout <= wire_n01iOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOll_dataout <= wire_n00110O_dataout WHEN n1O0liO = '1' ELSE n1Oll1i; + wire_n01iOlli_dataout <= wire_n01l111i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOlll_dataout <= wire_n01l111l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOllO_dataout <= wire_n01l111O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOlO_dataout <= wire_n0011ii_dataout WHEN n1O0liO = '1' ELSE n1Oll1l; + wire_n01iOlOi_dataout <= wire_n01l110i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOlOl_dataout <= wire_n01l110l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOlOO_dataout <= wire_n01l110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOO1i_dataout <= wire_n01l11ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOO1l_dataout <= wire_n01l11il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01iOOi_dataout <= wire_n0011il_dataout WHEN n1O0liO = '1' ELSE n1Oll1O; + wire_n01iOOiO_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n01iOi1l; + wire_n01iOOl_dataout <= wire_n0011iO_dataout WHEN n1O0liO = '1' ELSE n1Oll0i; + wire_n01iOOli_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n01i1OOl; + wire_n01iOOll_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n01iO0OO; + wire_n01iOOlO_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n01iOi1i; + wire_n01iOOO_dataout <= wire_n0011li_dataout WHEN n1O0liO = '1' ELSE n1Oll0l; + wire_n01iOOOi_dataout <= wire_n1lllOll_dataout WHEN n1lO0lOi = '1' ELSE wire_n01iOOOl_dataout; + wire_n01iOOOl_dataout <= wire_n01iOOOO_dataout AND NOT(niOliO0Ol); + wire_n01iOOOO_dataout <= n1l001OO AND NOT(niOliO0Oi); + wire_n01l000l_dataout <= wire_n01l0i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l000O_dataout <= wire_n01l0iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00i_dataout <= wire_n1llO0O_q(148) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0OiO; + wire_n01l00ii_dataout <= wire_n01l0iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00il_dataout <= wire_n01l0iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00iO_dataout <= wire_n01l0ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00l_dataout <= wire_n1llO0O_q(149) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0Oli; + wire_n01l00li_dataout <= wire_n01l0ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00ll_dataout <= wire_n01l0ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00lO_dataout <= wire_n01l0iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00O_dataout <= wire_n1llO0O_q(150) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0Oll; + wire_n01l00Oi_dataout <= wire_n01l0iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00Ol_dataout <= wire_n01l0iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l00OO_dataout <= wire_n01l0l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l011l_dataout <= n000i1lO WHEN niOliO0OO = '1' ELSE (n000i1lO XOR n01l001O); + wire_n01l01i_dataout <= wire_n1llO0O_q(145) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0O0O; + wire_n01l01l_dataout <= wire_n1llO0O_q(146) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0Oii; + wire_n01l01O_dataout <= wire_n1llO0O_q(147) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0Oil; + wire_n01l0i0i_dataout <= wire_n01l0l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l0i0l_dataout <= wire_n01l0l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l0i0O_dataout <= wire_n01l0lii_dataout OR niOliOi1l; + wire_n01l0i1i_dataout <= wire_n01l0l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l0i1l_dataout <= wire_n01l0l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l0i1O_dataout <= wire_n01l0l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l0ii_dataout <= wire_n1llO0O_q(151) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0OlO; + wire_n01l0iii_dataout <= wire_n01l0lil_dataout OR niOliOi1l; + wire_n01l0iil_dataout <= wire_n01l0liO_dataout OR niOliOi1l; + wire_n01l0iiO_dataout <= wire_n01l0lli_dataout OR niOliOi1l; + wire_n01l0il_dataout <= wire_n1llO0O_q(152) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0OOi; + wire_n01l0ili_dataout <= wire_n01l0lll_dataout OR niOliOi1l; + wire_n01l0ill_dataout <= wire_n01l0llO_dataout OR niOliOi1l; + wire_n01l0ilO_dataout <= wire_n01l0lOi_dataout OR niOliOi1l; + wire_n01l0iO_dataout <= wire_n1llO0O_q(153) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0OOl; + wire_n01l0iOi_dataout <= wire_n01l0lOl_dataout OR niOliOi1l; + wire_n01l0iOl_dataout <= wire_n01l0lOO_dataout OR niOliOi1l; + wire_n01l0iOO_dataout <= wire_n01l0O1i_dataout OR niOliOi1l; + wire_n01l0l0i_dataout <= wire_n01l0O0l_dataout OR niOliOi1l; + wire_n01l0l0l_dataout <= wire_n01l0O0O_dataout OR niOliOi1l; + wire_n01l0l0O_dataout <= wire_n01l0Oii_dataout OR niOliOi1l; + wire_n01l0l1i_dataout <= wire_n01l0O1l_dataout OR niOliOi1l; + wire_n01l0l1l_dataout <= wire_n01l0O1O_dataout OR niOliOi1l; + wire_n01l0l1O_dataout <= wire_n01l0O0i_dataout OR niOliOi1l; + wire_n01l0li_dataout <= wire_n1llO0O_q(154) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0OOO; + wire_n01l0lii_dataout <= n01l1Oil WHEN niOliOi1i = '1' ELSE n01l01ll; + wire_n01l0lil_dataout <= n01l010i WHEN niOliOi1i = '1' ELSE n01l01lO; + wire_n01l0liO_dataout <= n01l010l WHEN niOliOi1i = '1' ELSE n01l01Oi; + wire_n01l0ll_dataout <= wire_n1llO0O_q(155) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi11i; + wire_n01l0lli_dataout <= n01l010O WHEN niOliOi1i = '1' ELSE (n01l01Ol XOR n01l01ll); + wire_n01l0lll_dataout <= n01l01ii WHEN niOliOi1i = '1' ELSE (n01l01ll XOR (n01l01OO XOR n01l01lO)); + wire_n01l0llO_dataout <= n01l01il WHEN niOliOi1i = '1' ELSE (n01l01ll XOR (n01l01lO XOR (n01l001i XOR n01l01Oi))); + wire_n01l0lO_dataout <= wire_n1llO0O_q(156) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi11l; + wire_n01l0lOi_dataout <= n01l01iO WHEN niOliOi1i = '1' ELSE (n01l01lO XOR (n01l01Oi XOR (n01l001l XOR n01l01Ol))); + wire_n01l0lOl_dataout <= n01l01li WHEN niOliOi1i = '1' ELSE (n01l01Oi XOR (n01l01Ol XOR (n01l001O XOR n01l01OO))); + wire_n01l0lOO_dataout <= n01l01ll WHEN niOliOi1i = '1' ELSE (n01l01Ol XOR (n01l01OO XOR (n01l001i XOR n01l1Oil))); + wire_n01l0O0i_dataout <= n01l01OO WHEN niOliOi1i = '1' ELSE (n01l001O XOR n01l01ii); + wire_n01l0O0l_dataout <= n01l001i WHEN niOliOi1i = '1' ELSE n01l01il; + wire_n01l0O0O_dataout <= n01l001l WHEN niOliOi1i = '1' ELSE n01l01iO; + wire_n01l0O1i_dataout <= n01l01lO WHEN niOliOi1i = '1' ELSE (n01l01OO XOR (n01l001i XOR (n01l001l XOR n01l010i))); + wire_n01l0O1l_dataout <= n01l01Oi WHEN niOliOi1i = '1' ELSE (n01l001i XOR (n01l001l XOR (n01l001O XOR n01l010l))); + wire_n01l0O1O_dataout <= n01l01Ol WHEN niOliOi1i = '1' ELSE (n01l001l XOR (n01l001O XOR n01l010O)); + wire_n01l0Oi_dataout <= wire_n1llO0O_q(133) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ollll; + wire_n01l0Oii_dataout <= n01l001O WHEN niOliOi1i = '1' ELSE n01l01li; + wire_n01l0OiO_dataout <= wire_n01l0Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01l0Ol_dataout <= wire_n1llO0O_q(134) WHEN wire_n1O0lli_dataout = '1' ELSE n1OlllO; + wire_n01l0Oli_dataout <= wire_n01l0Oll_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n01l000i) AND niOliOi1l)); + wire_n01l0Oll_dataout <= n01l000i OR n111i10i; + wire_n01l0OO_dataout <= wire_n1llO0O_q(135) WHEN wire_n1O0lli_dataout = '1' ELSE n1OllOi; + wire_n01l100i_dataout <= n1101l1i WHEN niOliO0Oi = '1' ELSE n1l001iO; + wire_n01l100l_dataout <= n1l001li AND NOT(niOliO0Oi); + wire_n01l100O_dataout <= n1l001ll AND NOT(niOliO0Oi); + wire_n01l101i_dataout <= wire_nlOO1i10l_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l10iO_dataout; + wire_n01l101l_dataout <= wire_niili01O_dataout WHEN niOliO0Oi = '1' ELSE n1l001ii; + wire_n01l101O_dataout <= wire_niili00i_dataout WHEN niOliO0Oi = '1' ELSE n1l001il; + wire_n01l10i_dataout <= wire_n0011Ol_dataout WHEN n1O0liO = '1' ELSE n1OlliO; + wire_n01l10ii_dataout <= n1l001lO AND NOT(niOliO0Oi); + wire_n01l10il_dataout <= n1l001Oi AND NOT(niOliO0Oi); + wire_n01l10iO_dataout <= n1l001Ol AND NOT(niOliO0Oi); + wire_n01l10l_dataout <= wire_n0011OO_dataout WHEN n1O0liO = '1' ELSE n1Ollli; + wire_n01l10lO_dataout <= k_cnt(57) AND NOT(wire_n01l1i1O_o); + wire_n01l10O_dataout <= wire_n00100l_dataout WHEN n1O0liO = '1' ELSE n1O0l0O; + wire_n01l10Oi_dataout <= k_cnt(58) AND NOT(wire_n01l1i1O_o); + wire_n01l10Ol_dataout <= k_cnt(59) OR wire_n01l1i1O_o; + wire_n01l10OO_dataout <= k_cnt(60) AND NOT(wire_n01l1i1O_o); + wire_n01l110i_dataout <= wire_n1llOO0O_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l11lO_dataout; + wire_n01l110l_dataout <= wire_n1llOOii_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l11Oi_dataout; + wire_n01l110O_dataout <= wire_n1llOOil_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l11Ol_dataout; + wire_n01l111i_dataout <= wire_n1llOO1O_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l11iO_dataout; + wire_n01l111l_dataout <= wire_n1llOO0i_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l11li_dataout; + wire_n01l111O_dataout <= wire_n1llOO0l_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l11ll_dataout; + wire_n01l11i_dataout <= wire_n0011ll_dataout WHEN n1O0liO = '1' ELSE n1Oll0O; + wire_n01l11ii_dataout <= wire_n1llOOiO_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l11OO_dataout; + wire_n01l11il_dataout <= wire_n1llOOli_dataout WHEN n1lO0lOi = '1' ELSE wire_n01l101i_dataout; + wire_n01l11iO_dataout <= wire_nlOO10OOi_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l101l_dataout; + wire_n01l11l_dataout <= wire_n0011lO_dataout WHEN n1O0liO = '1' ELSE n1Ollii; + wire_n01l11li_dataout <= wire_nlOO10OOl_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l101O_dataout; + wire_n01l11ll_dataout <= wire_nlOO10OOO_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l100i_dataout; + wire_n01l11lO_dataout <= wire_nlOO1i11i_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l100l_dataout; + wire_n01l11O_dataout <= wire_n0011Oi_dataout WHEN n1O0liO = '1' ELSE n1Ollil; + wire_n01l11Oi_dataout <= wire_nlOO1i11l_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l100O_dataout; + wire_n01l11Ol_dataout <= wire_nlOO1i11O_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l10ii_dataout; + wire_n01l11OO_dataout <= wire_nlOO1i10i_dataout WHEN niOliO0Ol = '1' ELSE wire_n01l10il_dataout; + wire_n01l1i1i_dataout <= k_cnt(61) AND NOT(wire_n01l1i1O_o); + wire_n01l1i1l_dataout <= k_cnt(62) AND NOT(wire_n01l1i1O_o); + wire_n01l1ii_dataout <= wire_n01li0O_dataout WHEN n1O0liO = '1' ELSE n1O0O1i; + wire_n01l1il_dataout <= wire_n00101i_dataout WHEN n1O0liO = '1' ELSE n1OlO0i; + wire_n01l1iO_dataout <= wire_n00101l_dataout WHEN n1O0liO = '1' ELSE n1OlO0l; + wire_n01l1li_dataout <= wire_n00101O_dataout WHEN n1O0liO = '1' ELSE n1OlO0O; + wire_n01l1ll_dataout <= wire_n00100i_dataout WHEN n1O0liO = '1' ELSE n1OlOii; + wire_n01l1lO_dataout <= wire_n1llO0O_q(141) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0O1l; + wire_n01l1O0i_dataout <= n000i01O WHEN niOliO0OO = '1' ELSE (n000i01O XOR n01l01lO); + wire_n01l1O0O_dataout <= n000i01l WHEN niOliO0OO = '1' ELSE (n000i01l XOR n01l01Oi); + wire_n01l1O1i_dataout <= n000i00i WHEN niOliO0OO = '1' ELSE (n000i00i XOR n01l01ll); + wire_n01l1Oi_dataout <= wire_n1llO0O_q(142) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0O1O; + wire_n01l1OiO_dataout <= n000i01i WHEN niOliO0OO = '1' ELSE (n000i01i XOR n01l01Ol); + wire_n01l1Ol_dataout <= wire_n1llO0O_q(143) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0O0i; + wire_n01l1Oll_dataout <= n000i1OO WHEN niOliO0OO = '1' ELSE (n000i1OO XOR n01l01OO); + wire_n01l1OO_dataout <= wire_n1llO0O_q(144) WHEN wire_n1O0lli_dataout = '1' ELSE n1O0O0l; + wire_n01l1OOi_dataout <= n000i1Ol WHEN niOliO0OO = '1' ELSE (n000i1Ol XOR n01l001i); + wire_n01l1OOO_dataout <= n000i1Oi WHEN niOliO0OO = '1' ELSE (n000i1Oi XOR n01l001l); + wire_n01li0i_dataout <= wire_n1llO0O_q(139) WHEN wire_n1O0lli_dataout = '1' ELSE n1OlO1l; + wire_n01li0l_dataout <= wire_n1llO0O_q(140) WHEN wire_n1O0lli_dataout = '1' ELSE n1OlO1O; + wire_n01li0li_dataout <= wire_niO10ill_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10ill_dataout XOR n01lil0l); + wire_n01li0li_w_lg_dataout16735w(0) <= NOT wire_n01li0li_dataout; + wire_n01li0O_dataout <= wire_n1llO0O_q(157) AND wire_n1O0lli_dataout; + wire_n01li0Oi_dataout <= wire_niO10ili_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10ili_dataout XOR n01lil0O); + wire_n01li0Oi_w_lg_dataout16733w(0) <= NOT wire_n01li0Oi_dataout; + wire_n01li0OO_dataout <= wire_niO10iiO_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10iiO_dataout XOR n01lilii); + wire_n01li0OO_w_lg_dataout16731w(0) <= NOT wire_n01li0OO_dataout; + wire_n01li1i_dataout <= wire_n1llO0O_q(136) WHEN wire_n1O0lli_dataout = '1' ELSE n1OllOl; + wire_n01li1l_dataout <= wire_n1llO0O_q(137) WHEN wire_n1O0lli_dataout = '1' ELSE n1OllOO; + wire_n01li1O_dataout <= wire_n1llO0O_q(138) WHEN wire_n1O0lli_dataout = '1' ELSE n1OlO1i; + wire_n01lii0l_dataout <= wire_niO10iii_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10iii_dataout XOR n01liliO); + wire_n01lii0l_w_lg_dataout16727w(0) <= NOT wire_n01lii0l_dataout; + wire_n01lii1O_dataout <= wire_niO10iil_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10iil_dataout XOR n01lilil); + wire_n01lii1O_w_lg_dataout16729w(0) <= NOT wire_n01lii1O_dataout; + wire_n01liii_dataout <= wire_n1llO0O_q(132) AND wire_n1O0lli_dataout; + wire_n01liiii_dataout <= wire_niO10i0O_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10i0O_dataout XOR n01lilli); + wire_n01liiii_w_lg_dataout16725w(0) <= NOT wire_n01liiii_dataout; + wire_n01liiiO_dataout <= wire_niO10i0l_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10i0l_dataout XOR n01lilll); + wire_n01liiiO_w_lg_dataout16723w(0) <= NOT wire_n01liiiO_dataout; + wire_n01liil_dataout <= wire_n1llO0O_q(0) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi11O; + wire_n01liill_dataout <= wire_niO10i0i_dataout WHEN niOliOi1O = '1' ELSE (wire_niO10i0i_dataout XOR n01lillO); + wire_n01liill_w_lg_dataout16721w(0) <= NOT wire_n01liill_dataout; + wire_n01liiO_dataout <= wire_n1llO0O_q(1) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi10i; + wire_n01lili_dataout <= wire_n1llO0O_q(2) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi10l; + wire_n01lill_dataout <= wire_n1llO0O_q(3) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi10O; + wire_n01lilO_dataout <= wire_n1llO0O_q(4) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1ii; + wire_n01lilOi_dataout <= wire_n01liOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01lilOl_dataout <= wire_n01liOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01lilOO_dataout <= wire_n01ll11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liO0i_dataout <= wire_n01ll10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liO0l_dataout <= wire_n01ll10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liO0O_dataout <= wire_n01ll1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liO1i_dataout <= wire_n01ll11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liO1l_dataout <= wire_n01ll11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liO1O_dataout <= wire_n01ll10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOi_dataout <= wire_n1llO0O_q(5) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1il; + wire_n01liOii_dataout <= wire_n01ll1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOil_dataout <= wire_n01ll1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOiO_dataout <= wire_n01ll1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOl_dataout <= wire_n1llO0O_q(6) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1iO; + wire_n01liOli_dataout <= wire_n01ll1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOll_dataout <= wire_n01ll1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOlO_dataout <= wire_n01ll1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOO_dataout <= wire_n1llO0O_q(7) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1li; + wire_n01liOOi_dataout <= wire_n01ll1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01liOOl_dataout <= wire_n01ll1OO_dataout OR niOliOi0i; + wire_n01liOOO_dataout <= wire_n01ll01i_dataout OR niOliOi0i; + wire_n01ll00i_dataout <= n01lil1i WHEN niOliOi0l = '1' ELSE (n01lil0l XOR (n01liliO XOR n01lil0O)); + wire_n01ll00l_dataout <= n01lil1l WHEN niOliOi0l = '1' ELSE (n01lil0l XOR (n01lil0O XOR (n01lilli XOR n01lilii))); + wire_n01ll00O_dataout <= n01lil1O WHEN niOliOi0l = '1' ELSE (n01lil0O XOR (n01lilii XOR (n01lilll XOR n01lilil))); + wire_n01ll01i_dataout <= n01liiOi WHEN niOliOi0l = '1' ELSE n01lil0O; + wire_n01ll01l_dataout <= n01liiOl WHEN niOliOi0l = '1' ELSE n01lilii; + wire_n01ll01O_dataout <= n01liiOO WHEN niOliOi0l = '1' ELSE (n01lilil XOR n01lil0l); + wire_n01ll0i_dataout <= wire_n1llO0O_q(11) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1Ol; + wire_n01ll0ii_dataout <= n01lil0i WHEN niOliOi0l = '1' ELSE (n01lilii XOR (n01lilil XOR (n01lillO XOR n01liliO))); + wire_n01ll0il_dataout <= n01lil0l WHEN niOliOi0l = '1' ELSE (n01lilil XOR (n01liliO XOR (n01lilli XOR n01lii1l))); + wire_n01ll0iO_dataout <= n01lil0O WHEN niOliOi0l = '1' ELSE (n01liliO XOR (n01lilli XOR (n01lilll XOR n01liiOi))); + wire_n01ll0l_dataout <= wire_n1llO0O_q(12) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1OO; + wire_n01ll0li_dataout <= n01lilii WHEN niOliOi0l = '1' ELSE (n01lilli XOR (n01lilll XOR (n01lillO XOR n01liiOl))); + wire_n01ll0ll_dataout <= n01lilil WHEN niOliOi0l = '1' ELSE (n01lilll XOR (n01lillO XOR n01liiOO)); + wire_n01ll0lO_dataout <= n01liliO WHEN niOliOi0l = '1' ELSE (n01lillO XOR n01lil1i); + wire_n01ll0O_dataout <= wire_n1llO0O_q(13) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi01i; + wire_n01ll0Oi_dataout <= n01lilli WHEN niOliOi0l = '1' ELSE n01lil1l; + wire_n01ll0Ol_dataout <= n01lilll WHEN niOliOi0l = '1' ELSE n01lil1O; + wire_n01ll0OO_dataout <= n01lillO WHEN niOliOi0l = '1' ELSE n01lil0i; + wire_n01ll10i_dataout <= wire_n01ll00l_dataout OR niOliOi0i; + wire_n01ll10l_dataout <= wire_n01ll00O_dataout OR niOliOi0i; + wire_n01ll10O_dataout <= wire_n01ll0ii_dataout OR niOliOi0i; + wire_n01ll11i_dataout <= wire_n01ll01l_dataout OR niOliOi0i; + wire_n01ll11l_dataout <= wire_n01ll01O_dataout OR niOliOi0i; + wire_n01ll11O_dataout <= wire_n01ll00i_dataout OR niOliOi0i; + wire_n01ll1i_dataout <= wire_n1llO0O_q(8) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1ll; + wire_n01ll1ii_dataout <= wire_n01ll0il_dataout OR niOliOi0i; + wire_n01ll1il_dataout <= wire_n01ll0iO_dataout OR niOliOi0i; + wire_n01ll1iO_dataout <= wire_n01ll0li_dataout OR niOliOi0i; + wire_n01ll1l_dataout <= wire_n1llO0O_q(9) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1lO; + wire_n01ll1li_dataout <= wire_n01ll0ll_dataout OR niOliOi0i; + wire_n01ll1ll_dataout <= wire_n01ll0lO_dataout OR niOliOi0i; + wire_n01ll1lO_dataout <= wire_n01ll0Oi_dataout OR niOliOi0i; + wire_n01ll1O_dataout <= wire_n1llO0O_q(10) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi1Oi; + wire_n01ll1Oi_dataout <= wire_n01ll0Ol_dataout OR niOliOi0i; + wire_n01ll1Ol_dataout <= wire_n01ll0OO_dataout OR niOliOi0i; + wire_n01ll1OO_dataout <= n01lii1l WHEN niOliOi0l = '1' ELSE n01lil0l; + wire_n01llii_dataout <= wire_n1llO0O_q(14) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi01l; + wire_n01llil_dataout <= wire_n1llO0O_q(15) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi01O; + wire_n01lliO_dataout <= wire_n1llO0O_q(16) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi00i; + wire_n01llli_dataout <= wire_n1llO0O_q(17) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi00l; + wire_n01llll_dataout <= wire_n1llO0O_q(18) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi00O; + wire_n01lllO_dataout <= wire_n1llO0O_q(19) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0ii; + wire_n01llOi_dataout <= wire_n1llO0O_q(20) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0il; + wire_n01llOl_dataout <= wire_n1llO0O_q(21) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0iO; + wire_n01llOO_dataout <= wire_n1llO0O_q(22) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0li; + wire_n01lO0i_dataout <= wire_n1llO0O_q(26) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0Ol; + wire_n01lO0l_dataout <= wire_n1llO0O_q(27) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0OO; + wire_n01lO0O_dataout <= wire_n1llO0O_q(28) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oii1i; + wire_n01lO1i_dataout <= wire_n1llO0O_q(23) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0ll; + wire_n01lO1l_dataout <= wire_n1llO0O_q(24) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0lO; + wire_n01lO1O_dataout <= wire_n1llO0O_q(25) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oi0Oi; + wire_n01lOii_dataout <= wire_n1llO0O_q(29) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oii1l; + wire_n01lOil_dataout <= wire_n1llO0O_q(30) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oii1O; + wire_n01lOiO_dataout <= wire_n1llO0O_q(31) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oii0i; + wire_n01lOl0i_dataout <= wire_niO10i1O_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOl0l_dataout <= wire_n01liill_dataout AND wire_niO100Ol_w_lg_dataout16630w(0); + wire_n01lOl0O_dataout <= wire_n01liiiO_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOli_dataout <= wire_n1llO0O_q(32) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oii0l; + wire_n01lOlii_dataout <= wire_n01liiii_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOlil_dataout <= wire_n01lii0l_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOliO_dataout <= wire_n01lii1O_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOll_dataout <= wire_n1llO0O_q(33) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oii0O; + wire_n01lOlli_dataout <= wire_n01li0OO_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOlll_dataout <= wire_n01li0Oi_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOllO_dataout <= wire_n01li0li_dataout OR NOT(wire_niO100Ol_w_lg_dataout16630w(0)); + wire_n01lOlO_dataout <= wire_n1llO0O_q(34) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oiiii; + wire_n01lOO0i_dataout <= wire_n01lOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01lOO0l_dataout <= wire_n01lOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01lOO0O_dataout <= wire_n01lOOii_dataout AND n001ilOi; + wire_n01lOO1l_dataout <= wire_n01lOO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01lOO1O_dataout <= wire_n01lOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01lOOi_dataout <= wire_n1llO0O_q(35) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oiiil; + wire_n01lOOii_dataout <= n01lOOiO OR (n001ilOi AND n01lOlOi); + wire_n01lOOl_dataout <= wire_n1llO0O_q(36) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiiiO; + wire_n01lOOli_dataout <= ((wire_niO10i1l_dataout AND niOliOO0i) AND n01lOlOl) AND n001ilOi; + wire_n01lOOll_dataout <= (niOll110l AND n01lOlOO) AND n001ilOi; + wire_n01lOOlO_dataout <= (n0010l1O AND (wire_niO10i1l_dataout AND niOliOO0l)) AND n001ilOi; + wire_n01lOOO_dataout <= wire_n1llO0O_q(37) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oiili; + wire_n01O00i_dataout <= wire_n1llO0O_q(56) WHEN wire_n1O0lli_dataout = '1' ELSE n1OilOl; + wire_n01O00l_dataout <= wire_n1llO0O_q(57) WHEN wire_n1O0lli_dataout = '1' ELSE n1OilOO; + wire_n01O00O_dataout <= wire_n1llO0O_q(58) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiO1i; + wire_n01O01i_dataout <= wire_n1llO0O_q(53) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oilll; + wire_n01O01l_dataout <= wire_n1llO0O_q(54) WHEN wire_n1O0lli_dataout = '1' ELSE n1OillO; + wire_n01O01O_dataout <= wire_n1llO0O_q(55) WHEN wire_n1O0lli_dataout = '1' ELSE n1OilOi; + wire_n01O0ii_dataout <= wire_n1llO0O_q(59) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiO1l; + wire_n01O0il_dataout <= wire_n1llO0O_q(60) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiO1O; + wire_n01O0iO_dataout <= wire_n1llO0O_q(61) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiO0i; + wire_n01O0iOi_dataout <= wire_n01OillO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0iOl_dataout <= wire_n01OilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0iOO_dataout <= wire_n01OilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0l0i_dataout <= wire_n01Oi1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0l0l_dataout <= wire_n01Oi01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0l0O_dataout <= wire_n01Oi01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0l1i_dataout <= ((niOliOOlO OR niOliOOll) OR niOliOOli) AND NOT(wire_niO01lOO_dataout); + wire_n01O0l1l_dataout <= (n0010l1O AND (niOll110l OR niOll111i)) AND NOT(wire_niO01lOO_dataout); + wire_n01O0l1O_dataout <= wire_n01Oi1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0li_dataout <= wire_n1llO0O_q(62) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiO0l; + wire_n01O0lii_dataout <= wire_n01Oi01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0lil_dataout <= wire_n01Oi00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0liO_dataout <= wire_n01Oi00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0ll_dataout <= wire_n1llO0O_q(63) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiO0O; + wire_n01O0lli_dataout <= wire_n01Oi00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0lll_dataout <= wire_n01OilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0llO_dataout <= wire_n01OiO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0lO_dataout <= wire_n1llO0O_q(64) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOii; + wire_n01O0lOi_dataout <= wire_n01OiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0lOl_dataout <= wire_n01OiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0lOO_dataout <= wire_n01OiO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0O0i_dataout <= wire_n01OiOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0O0l_dataout <= wire_n01OiOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0O0O_dataout <= wire_n01OiOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0O1i_dataout <= wire_n01OiO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0O1l_dataout <= wire_n01OiO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0O1O_dataout <= wire_n01OiOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0Oi_dataout <= wire_n1llO0O_q(65) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOil; + wire_n01O0Oii_dataout <= wire_n01OiOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0Oil_dataout <= wire_n01OiOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0OiO_dataout <= wire_n01OiOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0Ol_dataout <= wire_n1llO0O_q(66) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOiO; + wire_n01O0Oli_dataout <= wire_n01OiOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0Oll_dataout <= wire_n01OiOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0OlO_dataout <= wire_n01Ol11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0OO_dataout <= wire_n1llO0O_q(67) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOli; + wire_n01O0OOi_dataout <= wire_n01Ol11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0OOl_dataout <= wire_n01OiiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O0OOO_dataout <= wire_n01OiiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O100i_dataout <= wire_n01O10Oi_dataout WHEN niOliOOlO = '1' ELSE n01lOO1i; + wire_n01O100l_dataout <= n01O110i AND NOT(niOliOiil); + wire_n01O100O_dataout <= n01O110l AND NOT(niOliOiil); + wire_n01O101i_dataout <= wire_n01O100O_dataout WHEN wire_niO01ill_w_lg_n01O111O16623w(0) = '1' ELSE wire_n01O101O_dataout; + wire_n01O101l_dataout <= wire_n01O10ll_dataout WHEN niOliOOlO = '1' ELSE wire_n01O100l_dataout; + wire_n01O101O_dataout <= wire_n01O10lO_dataout WHEN niOliOOlO = '1' ELSE wire_n01O100O_dataout; + wire_n01O10i_dataout <= wire_n1llO0O_q(41) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiiOl; + wire_n01O10l_dataout <= wire_n1llO0O_q(42) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiiOO; + wire_n01O10ll_dataout <= n01O110i WHEN niOliOiii = '1' ELSE wire_n01O10Ol_o(0); + wire_n01O10lO_dataout <= n01O110l WHEN niOliOiii = '1' ELSE wire_n01O10Ol_o(1); + wire_n01O10O_dataout <= wire_n1llO0O_q(43) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oil1i; + wire_n01O10Oi_dataout <= n01lOO1i OR niOliOiii; + wire_n01O10OO_dataout <= n01O110i OR niOliOOlO; + wire_n01O11i_dataout <= wire_n1llO0O_q(38) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oiill; + wire_n01O11ii_dataout <= wire_n01O11ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O11il_dataout <= wire_n01O1i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O11iO_dataout <= wire_n01O11lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O11l_dataout <= wire_n1llO0O_q(39) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiilO; + wire_n01O11li_dataout <= wire_n01O11Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O11ll_dataout <= wire_n01O11Ol_dataout AND NOT(niOliOi0O); + wire_n01O11lO_dataout <= wire_n01O10OO_dataout WHEN niOliOi0O = '1' ELSE wire_n01O11OO_dataout; + wire_n01O11O_dataout <= wire_n1llO0O_q(40) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiiOi; + wire_n01O11Oi_dataout <= wire_n01O1i1i_dataout WHEN niOliOi0O = '1' ELSE wire_n01O101i_dataout; + wire_n01O11Ol_dataout <= n01lOO1i WHEN wire_niO01ill_w_lg_n01O111O16623w(0) = '1' ELSE wire_n01O100i_dataout; + wire_n01O11OO_dataout <= wire_n01O100l_dataout WHEN wire_niO01ill_w_lg_n01O111O16623w(0) = '1' ELSE wire_n01O101l_dataout; + wire_n01O1i1i_dataout <= n01O110l AND NOT(niOliOOlO); + wire_n01O1i1l_dataout <= wire_n01O1i1O_dataout OR (niOll111O AND (n0010ili OR n00100li)); + wire_n01O1i1O_dataout <= n01O111O AND NOT(niOliOiil); + wire_n01O1ii_dataout <= wire_n1llO0O_q(44) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oil1l; + wire_n01O1il_dataout <= wire_n1llO0O_q(45) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oil1O; + wire_n01O1ilO_dataout <= wire_n01O1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O1iO_dataout <= wire_n1llO0O_q(46) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oil0i; + wire_n01O1iOi_dataout <= wire_n01O1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01O1iOl_dataout <= wire_n01O1l0l_dataout OR wire_niO01lOO_dataout; + wire_n01O1iOO_dataout <= wire_n01O1l0O_dataout OR wire_niO01lOO_dataout; + wire_n01O1l0i_dataout <= wire_n01O1lli_dataout AND NOT(niOliOlii); + wire_n01O1l0l_dataout <= wire_n01O1lll_dataout OR niOliOlii; + wire_n01O1l0O_dataout <= wire_n01O1llO_dataout AND NOT(niOliOlii); + wire_n01O1l1i_dataout <= wire_n01O1lii_dataout OR wire_niO01lOO_dataout; + wire_n01O1l1l_dataout <= wire_n01O1lil_dataout OR wire_niO01lOO_dataout; + wire_n01O1l1O_dataout <= wire_n01O1liO_dataout OR niOliOlii; + wire_n01O1li_dataout <= wire_n1llO0O_q(47) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oil0l; + wire_n01O1lii_dataout <= wire_n01O1lOi_dataout OR niOliOlii; + wire_n01O1lil_dataout <= wire_n01O1lOl_dataout OR niOliOlii; + wire_n01O1liO_dataout <= wire_n01O1lOO_dataout AND n01O110O; + wire_n01O1ll_dataout <= wire_n1llO0O_q(48) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oil0O; + wire_n01O1lli_dataout <= wire_n01O1O1i_dataout AND n01O110O; + wire_n01O1lll_dataout <= wire_n01O1O1l_dataout OR NOT(n01O110O); + wire_n01O1llO_dataout <= wire_n01O1O1O_dataout OR NOT(n01O110O); + wire_n01O1lO_dataout <= wire_n1llO0O_q(49) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oilii; + wire_n01O1lOi_dataout <= wire_n01O1O0i_dataout OR NOT(n01O110O); + wire_n01O1lOl_dataout <= wire_n01O1O0l_dataout OR NOT(n01O110O); + wire_n01O1lOO_dataout <= n01O110O WHEN niOliOili = '1' ELSE wire_n01O1O0O_dataout; + wire_n01O1O0i_dataout <= wire_n01O1Oil_o(3) OR NOT(niOliOili); + wire_n01O1O0l_dataout <= wire_n01O1Oil_o(4) OR NOT(niOliOili); + wire_n01O1O0O_dataout <= n01O110O AND niOliOiiO; + wire_n01O1O1i_dataout <= niOliOiiO AND NOT(niOliOili); + wire_n01O1O1l_dataout <= wire_n01O1Oil_o(1) OR NOT(niOliOili); + wire_n01O1O1O_dataout <= wire_n01O1Oil_o(2) OR NOT(niOliOili); + wire_n01O1Oi_dataout <= wire_n1llO0O_q(50) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oilil; + wire_n01O1Ol_dataout <= wire_n1llO0O_q(51) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiliO; + wire_n01O1OO_dataout <= wire_n1llO0O_q(52) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oilli; + wire_n01Oi00i_dataout <= wire_n01Oi0lO_dataout AND NOT(niOliOl1l); + wire_n01Oi00l_dataout <= wire_n01Oi0Oi_dataout AND NOT(niOliOl1l); + wire_n01Oi00O_dataout <= wire_n01Oi0Ol_dataout AND NOT(niOliOl1l); + wire_n01Oi01i_dataout <= wire_n01Oi0iO_dataout AND NOT(niOliOl1l); + wire_n01Oi01l_dataout <= wire_n01Oi0li_dataout AND NOT(niOliOl1l); + wire_n01Oi01O_dataout <= wire_n01Oi0ll_dataout AND NOT(niOliOl1l); + wire_n01Oi0i_dataout <= wire_n1llO0O_q(71) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOOl; + wire_n01Oi0ii_dataout <= wire_n01Oi0OO_dataout OR niOliOl1i; + wire_n01Oi0il_dataout <= wire_n01Oii1i_dataout AND NOT(niOliOl1i); + wire_n01Oi0iO_dataout <= wire_n01Oii1l_dataout AND NOT(niOliOl1i); + wire_n01Oi0l_dataout <= wire_n1llO0O_q(72) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOOO; + wire_n01Oi0li_dataout <= wire_n01Oii1O_dataout AND NOT(niOliOl1i); + wire_n01Oi0ll_dataout <= wire_n01Oii0i_dataout AND NOT(niOliOl1i); + wire_n01Oi0lO_dataout <= wire_n01Oii0l_dataout AND NOT(niOliOl1i); + wire_n01Oi0O_dataout <= wire_n1llO0O_q(73) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol11i; + wire_n01Oi0Oi_dataout <= wire_n01Oii0O_dataout AND NOT(niOliOl1i); + wire_n01Oi0Ol_dataout <= wire_n01Oiiii_dataout AND NOT(niOliOl1i); + wire_n01Oi0OO_dataout <= wire_n01Oiiil_o(0) WHEN niOliOiOl = '1' ELSE n01O011i; + wire_n01Oi10i_dataout <= wire_n01Ol11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi10l_dataout <= wire_n01Oil0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi10O_dataout <= wire_n01Oil0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi11i_dataout <= wire_n01Oil1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi11l_dataout <= wire_n01Oil1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi11O_dataout <= wire_n01Oil1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1i_dataout <= wire_n1llO0O_q(68) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOll; + wire_n01Oi1ii_dataout <= wire_n01Oil0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1il_dataout <= wire_n01Oilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1iO_dataout <= wire_n01Oilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1l_dataout <= wire_n1llO0O_q(69) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOlO; + wire_n01Oi1li_dataout <= wire_n01OiliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1ll_dataout <= wire_n01Oilli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1lO_dataout <= wire_n01Oilll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1O_dataout <= wire_n1llO0O_q(70) WHEN wire_n1O0lli_dataout = '1' ELSE n1OiOOi; + wire_n01Oi1Oi_dataout <= wire_n01Ol10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01Oi1Ol_dataout <= wire_n01Oi0ii_dataout AND NOT(niOliOl1l); + wire_n01Oi1OO_dataout <= wire_n01Oi0il_dataout AND NOT(niOliOl1l); + wire_n01Oii0i_dataout <= wire_n01Oiiil_o(4) WHEN niOliOiOl = '1' ELSE n01O010l; + wire_n01Oii0l_dataout <= wire_n01Oiiil_o(5) WHEN niOliOiOl = '1' ELSE n01O010O; + wire_n01Oii0O_dataout <= wire_n01Oiiil_o(6) WHEN niOliOiOl = '1' ELSE n01O01ii; + wire_n01Oii1i_dataout <= wire_n01Oiiil_o(1) WHEN niOliOiOl = '1' ELSE n01O011l; + wire_n01Oii1l_dataout <= wire_n01Oiiil_o(2) WHEN niOliOiOl = '1' ELSE n01O011O; + wire_n01Oii1O_dataout <= wire_n01Oiiil_o(3) WHEN niOliOiOl = '1' ELSE n01O010i; + wire_n01Oiii_dataout <= wire_n1llO0O_q(74) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol11l; + wire_n01Oiiii_dataout <= wire_n01Oiiil_o(7) WHEN niOliOiOl = '1' ELSE n01O01il; + wire_n01Oiil_dataout <= wire_n1llO0O_q(75) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol11O; + wire_n01OiiO_dataout <= wire_n1llO0O_q(76) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol10i; + wire_n01OiiOl_dataout <= n01O00lO WHEN niOlO1O0i = '1' ELSE wire_n01Ol0ll_dataout; + wire_n01OiiOO_dataout <= n01O00Oi WHEN niOlO1O0i = '1' ELSE wire_n01Ol0lO_dataout; + wire_n01Oil0i_dataout <= n01O0i1O WHEN niOlO1O0i = '1' ELSE wire_n01Oli1l_dataout; + wire_n01Oil0l_dataout <= n01O0i0i WHEN niOlO1O0i = '1' ELSE wire_n01Oli1O_dataout; + wire_n01Oil0O_dataout <= n01O0i0l WHEN niOlO1O0i = '1' ELSE wire_n01Oli0i_dataout; + wire_n01Oil1i_dataout <= n01O00Ol WHEN niOlO1O0i = '1' ELSE wire_n01Ol0Oi_dataout; + wire_n01Oil1l_dataout <= n01O00OO WHEN niOlO1O0i = '1' ELSE wire_n01Ol0Ol_dataout; + wire_n01Oil1O_dataout <= n01O0i1i WHEN niOlO1O0i = '1' ELSE wire_n01Ol0OO_dataout; + wire_n01Oili_dataout <= wire_n1llO0O_q(77) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol10l; + wire_n01Oilii_dataout <= n01O0i0O WHEN niOlO1O0i = '1' ELSE wire_n01Oli0l_dataout; + wire_n01Oilil_dataout <= n01O0iii WHEN niOlO1O0i = '1' ELSE wire_n01Oli0O_dataout; + wire_n01OiliO_dataout <= n01O0iil WHEN niOlO1O0i = '1' ELSE wire_n01Oliii_dataout; + wire_n01Oill_dataout <= wire_n1llO0O_q(78) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol10O; + wire_n01Oilli_dataout <= n01O0iiO WHEN niOlO1O0i = '1' ELSE wire_n01Oliil_dataout; + wire_n01Oilll_dataout <= n01O0ili WHEN niOlO1O0i = '1' ELSE wire_n01OliiO_dataout; + wire_n01OillO_dataout <= wire_n01Ol10l_dataout AND NOT(niOlO1O0i); + wire_n01OilO_dataout <= wire_n1llO0O_q(79) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1ii; + wire_n01OilOi_dataout <= wire_n01Ol10O_dataout AND NOT(niOlO1O0i); + wire_n01OilOl_dataout <= wire_n01Ol1ii_dataout AND NOT(niOlO1O0i); + wire_n01OilOO_dataout <= wire_n01Ol1il_dataout AND NOT(niOlO1O0i); + wire_n01OiO0i_dataout <= wire_n01Ol1lO_dataout AND NOT(niOlO1O0i); + wire_n01OiO0l_dataout <= wire_n01Ol1Oi_dataout AND NOT(niOlO1O0i); + wire_n01OiO0O_dataout <= wire_n01Ol1Ol_dataout AND NOT(niOlO1O0i); + wire_n01OiO1i_dataout <= wire_n01Ol1iO_dataout AND NOT(niOlO1O0i); + wire_n01OiO1l_dataout <= wire_n01Ol1li_dataout AND NOT(niOlO1O0i); + wire_n01OiO1O_dataout <= wire_n01Ol1ll_dataout AND NOT(niOlO1O0i); + wire_n01OiOi_dataout <= wire_n1llO0O_q(80) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1il; + wire_n01OiOii_dataout <= wire_n01Ol1OO_dataout AND NOT(niOlO1O0i); + wire_n01OiOil_dataout <= wire_n01Ol01i_dataout AND NOT(niOlO1O0i); + wire_n01OiOiO_dataout <= wire_n01Ol01l_dataout AND NOT(niOlO1O0i); + wire_n01OiOl_dataout <= wire_n1llO0O_q(81) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1iO; + wire_n01OiOli_dataout <= wire_n01Ol01O_dataout AND NOT(niOlO1O0i); + wire_n01OiOll_dataout <= wire_n01Ol00i_dataout AND NOT(niOlO1O0i); + wire_n01OiOlO_dataout <= wire_n01Ol00l_dataout AND NOT(niOlO1O0i); + wire_n01OiOO_dataout <= wire_n1llO0O_q(82) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1li; + wire_n01OiOOi_dataout <= wire_n01Ol00O_dataout AND NOT(niOlO1O0i); + wire_n01OiOOl_dataout <= wire_n01Ol0ii_dataout AND NOT(niOlO1O0i); + wire_n01OiOOO_dataout <= wire_n01Ol0il_dataout AND NOT(niOlO1O0i); + wire_n01Ol00i_dataout <= n01OlOOi WHEN n01OllOO = '1' ELSE n01O000l; + wire_n01Ol00l_dataout <= n01OlOOl WHEN n01OllOO = '1' ELSE n01O000O; + wire_n01Ol00O_dataout <= n01OlOOO WHEN n01OllOO = '1' ELSE n01O00ii; + wire_n01Ol01i_dataout <= n01OlOli WHEN n01OllOO = '1' ELSE n01O001l; + wire_n01Ol01l_dataout <= n01OlOll WHEN n01OllOO = '1' ELSE n01O001O; + wire_n01Ol01O_dataout <= n01OlOlO WHEN n01OllOO = '1' ELSE n01O000i; + wire_n01Ol0i_dataout <= wire_n1llO0O_q(86) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1Ol; + wire_n01Ol0ii_dataout <= n01OO11i WHEN n01OllOO = '1' ELSE n01O00il; + wire_n01Ol0il_dataout <= n01OO11l WHEN n01OllOO = '1' ELSE n01O00iO; + wire_n01Ol0iO_dataout <= n01OO11O WHEN n01OllOO = '1' ELSE n01O00li; + wire_n01Ol0l_dataout <= wire_n1llO0O_q(87) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1OO; + wire_n01Ol0li_dataout <= n01OO10i WHEN n01OllOO = '1' ELSE n01O00ll; + wire_n01Ol0ll_dataout <= n01OO10l WHEN n01OllOO = '1' ELSE n01O00lO; + wire_n01Ol0lO_dataout <= n01OO10O WHEN n01OllOO = '1' ELSE n01O00Oi; + wire_n01Ol0O_dataout <= wire_n1llO0O_q(88) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol01i; + wire_n01Ol0Oi_dataout <= n01OO1ii WHEN n01OllOO = '1' ELSE n01O00Ol; + wire_n01Ol0Ol_dataout <= n01OO1il WHEN n01OllOO = '1' ELSE n01O00OO; + wire_n01Ol0OO_dataout <= n01OO1iO WHEN n01OllOO = '1' ELSE n01O0i1i; + wire_n01Ol10i_dataout <= wire_n01Olili_dataout AND NOT(niOlO1O0i); + wire_n01Ol10l_dataout <= n01O0ilO WHEN n01OllOO = '1' ELSE n01O1ill; + wire_n01Ol10O_dataout <= n01OlllO WHEN n01OllOO = '1' ELSE n01O1OlO; + wire_n01Ol11i_dataout <= wire_n01Ol0iO_dataout AND NOT(niOlO1O0i); + wire_n01Ol11l_dataout <= wire_n01Ol0li_dataout AND NOT(niOlO1O0i); + wire_n01Ol11O_dataout <= wire_n01Oli1i_dataout AND NOT(niOlO1O0i); + wire_n01Ol1i_dataout <= wire_n1llO0O_q(83) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1ll; + wire_n01Ol1ii_dataout <= n01OllOi WHEN n01OllOO = '1' ELSE n01O1OOi; + wire_n01Ol1il_dataout <= n01OlO1l WHEN n01OllOO = '1' ELSE n01O01iO; + wire_n01Ol1iO_dataout <= n01OlO1O WHEN n01OllOO = '1' ELSE n01O01li; + wire_n01Ol1l_dataout <= wire_n1llO0O_q(84) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1lO; + wire_n01Ol1li_dataout <= n01OlO0i WHEN n01OllOO = '1' ELSE n01O01ll; + wire_n01Ol1ll_dataout <= n01OlO0l WHEN n01OllOO = '1' ELSE n01O01lO; + wire_n01Ol1lO_dataout <= n01OlO0O WHEN n01OllOO = '1' ELSE n01O01Oi; + wire_n01Ol1O_dataout <= wire_n1llO0O_q(85) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol1Oi; + wire_n01Ol1Oi_dataout <= n01OlOii WHEN n01OllOO = '1' ELSE n01O01Ol; + wire_n01Ol1Ol_dataout <= n01OlOil WHEN n01OllOO = '1' ELSE n01O01OO; + wire_n01Ol1OO_dataout <= n01OlOiO WHEN n01OllOO = '1' ELSE n01O001i; + wire_n01Oli0i_dataout <= n01OO1Oi WHEN n01OllOO = '1' ELSE n01O0i0l; + wire_n01Oli0l_dataout <= n01OO1Ol WHEN n01OllOO = '1' ELSE n01O0i0O; + wire_n01Oli0O_dataout <= n01OO1OO WHEN n01OllOO = '1' ELSE n01O0iii; + wire_n01Oli1i_dataout <= n01OO1li WHEN n01OllOO = '1' ELSE n01O0i1l; + wire_n01Oli1l_dataout <= n01OO1ll WHEN n01OllOO = '1' ELSE n01O0i1O; + wire_n01Oli1O_dataout <= n01OO1lO WHEN n01OllOO = '1' ELSE n01O0i0i; + wire_n01Olii_dataout <= wire_n1llO0O_q(89) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol01l; + wire_n01Oliii_dataout <= n01OO01i WHEN n01OllOO = '1' ELSE n01O0iil; + wire_n01Oliil_dataout <= n01OO01l WHEN n01OllOO = '1' ELSE n01O0iiO; + wire_n01OliiO_dataout <= n01OO01O WHEN n01OllOO = '1' ELSE n01O0ili; + wire_n01Olil_dataout <= wire_n1llO0O_q(90) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol01O; + wire_n01Olili_dataout <= n01OO00i WHEN n01OllOO = '1' ELSE n01O0ill; + wire_n01OliO_dataout <= wire_n1llO0O_q(91) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol00i; + wire_n01Olli_dataout <= wire_n1llO0O_q(92) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol00l; + wire_n01Olll_dataout <= wire_n1llO0O_q(93) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol00O; + wire_n01OllO_dataout <= wire_n1llO0O_q(94) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0ii; + wire_n01OlOi_dataout <= wire_n1llO0O_q(95) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0il; + wire_n01OlOl_dataout <= wire_n1llO0O_q(96) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0iO; + wire_n01OlOO_dataout <= wire_n1llO0O_q(97) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0li; + wire_n01OO0i_dataout <= wire_n1llO0O_q(101) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0Ol; + wire_n01OO0l_dataout <= wire_n1llO0O_q(102) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0OO; + wire_n01OO0li_dataout <= wire_n0011i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OO0ll_dataout <= wire_n00110Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OO0lO_dataout <= wire_n0011i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OO0O_dataout <= wire_n1llO0O_q(103) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oli1i; + wire_n01OO0Oi_dataout <= ((wire_w_lg_niOll111i16481w(0) AND (wire_w_lg_niOliOO0O16482w(0) AND wire_w_lg_w_lg_niOll110l16345w16483w(0))) AND (wire_w_lg_w_lg_w_lg_niOliOlii16486w16490w16491w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n01OO0Ol_dataout <= (wire_w_lg_w_lg_w_lg_niOliOO1O16475w16477w16478w(0) AND wire_niO01ill_w_lg_n01OlO1i16479w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n01OO0OO_dataout <= wire_n001110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OO1i_dataout <= wire_n1llO0O_q(98) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0ll; + wire_n01OO1l_dataout <= wire_n1llO0O_q(99) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0lO; + wire_n01OO1O_dataout <= wire_n1llO0O_q(100) WHEN wire_n1O0lli_dataout = '1' ELSE n1Ol0Oi; + wire_n01OOi0i_dataout <= wire_n00110OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOi0l_dataout <= wire_n0011i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOi0O_dataout <= wire_n0011i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOi1i_dataout <= wire_n00110li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOi1l_dataout <= wire_n00110ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOi1O_dataout <= wire_n00110lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOii_dataout <= wire_n1llO0O_q(104) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oli1l; + wire_n01OOiii_dataout <= wire_n0011i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOiil_dataout <= wire_n0011iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOiiO_dataout <= wire_n0011ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOil_dataout <= wire_n1llO0O_q(105) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oli1O; + wire_n01OOili_dataout <= wire_n0011ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOill_dataout <= wire_n0011ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOilO_dataout <= wire_n0011iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOiO_dataout <= wire_n1llO0O_q(106) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oli0i; + wire_n01OOiOi_dataout <= wire_n0011iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOiOl_dataout <= wire_n0011iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOiOO_dataout <= wire_n0011l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOl0i_dataout <= wire_n0011l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOl0l_dataout <= wire_n0011l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOl0O_dataout <= wire_n0011l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOl1i_dataout <= wire_n0011i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOl1l_dataout <= wire_n0011iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOl1O_dataout <= wire_n0011iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOli_dataout <= wire_n1llO0O_q(107) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oli0l; + wire_n01OOlii_dataout <= wire_n0011l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOlil_dataout <= wire_n0011l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOliO_dataout <= wire_n0011lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOll_dataout <= wire_n1llO0O_q(108) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oli0O; + wire_n01OOlli_dataout <= wire_n0011lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOlll_dataout <= wire_n0011liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOllO_dataout <= wire_n0011lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOlO_dataout <= wire_n1llO0O_q(109) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oliii; + wire_n01OOlOi_dataout <= wire_n0011lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOlOl_dataout <= wire_n0011llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOlOO_dataout <= wire_n0011lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOO0i_dataout <= wire_n0011O1l_dataout OR wire_niO01lOO_dataout; + wire_n01OOO0l_dataout <= wire_n0011O1O_dataout OR wire_niO01lOO_dataout; + wire_n01OOO0O_dataout <= wire_n0011O0i_dataout OR wire_niO01lOO_dataout; + wire_n01OOO1i_dataout <= wire_n0011lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOO1l_dataout <= wire_n0011lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOO1O_dataout <= wire_n0011O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n01OOOi_dataout <= wire_n1llO0O_q(110) WHEN wire_n1O0lli_dataout = '1' ELSE n1Oliil; + wire_n01OOOii_dataout <= wire_n0011O0l_dataout OR wire_niO01lOO_dataout; + wire_n01OOOl_dataout <= wire_n1llO0O_q(111) WHEN wire_n1O0lli_dataout = '1' ELSE n1OliiO; + wire_n01OOOO_dataout <= wire_n1llO0O_q(112) WHEN wire_n1O0lli_dataout = '1' ELSE n1Olili; + wire_n0i000i_dataout <= n0iO10O WHEN niOO0i0lO = '1' ELSE n0iOOli; + wire_n0i000l_dataout <= n0iO1ii WHEN niOO0i0lO = '1' ELSE n0iOOll; + wire_n0i000O_dataout <= n0iO1il WHEN niOO0i0lO = '1' ELSE n0iOOlO; + wire_n0i0010i_dataout <= wire_n0i001li_dataout OR NOT(n0i010Ol); + wire_n0i0010l_dataout <= wire_n0i001ll_dataout OR NOT(n0i010Ol); + wire_n0i0010O_dataout <= wire_n0i001lO_dataout OR NOT(n0i010Ol); + wire_n0i0011i_dataout <= wire_n0i001ii_dataout OR niOlli10l; + wire_n0i0011l_dataout <= wire_n0i001il_dataout AND n0i010Ol; + wire_n0i0011O_dataout <= wire_n0i001iO_dataout AND n0i010Ol; + wire_n0i001i_dataout <= n0iO11O WHEN niOO0i0lO = '1' ELSE n0iOOii; + wire_n0i001ii_dataout <= wire_n0i001Oi_dataout OR NOT(n0i010Ol); + wire_n0i001il_dataout <= n0i010Ol WHEN niOll0Oil = '1' ELSE wire_n0i001Ol_dataout; + wire_n0i001iO_dataout <= niOll0Oii AND NOT(niOll0Oil); + wire_n0i001l_dataout <= n0iO10i WHEN niOO0i0lO = '1' ELSE n0iOOil; + wire_n0i001li_dataout <= wire_n0i0001i_o(1) OR NOT(niOll0Oil); + wire_n0i001ll_dataout <= wire_n0i0001i_o(2) OR NOT(niOll0Oil); + wire_n0i001lO_dataout <= wire_n0i0001i_o(3) OR NOT(niOll0Oil); + wire_n0i001O_dataout <= n0iO10l WHEN niOO0i0lO = '1' ELSE n0iOOiO; + wire_n0i001Oi_dataout <= wire_n0i0001i_o(4) OR NOT(niOll0Oil); + wire_n0i001Ol_dataout <= n0i010Ol AND niOll0Oii; + wire_n0i00ii_dataout <= n0iO1iO WHEN niOO0i0lO = '1' ELSE n0iOOOi; + wire_n0i00il_dataout <= n0iO1li WHEN niOO0i0lO = '1' ELSE n0iOOOl; + wire_n0i00iO_dataout <= n0iO1ll WHEN niOO0i0lO = '1' ELSE n0iOOOO; + wire_n0i00li_dataout <= n0iO1lO WHEN niOO0i0lO = '1' ELSE n0l111i; + wire_n0i00ll_dataout <= n0iO1Oi WHEN niOO0i0lO = '1' ELSE n0l111l; + wire_n0i00lO_dataout <= n0iO1Ol WHEN niOO0i0lO = '1' ELSE n0l111O; + wire_n0i00O0O_dataout <= wire_n0i0l10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i00Oi_dataout <= n0iO1OO WHEN niOO0i0lO = '1' ELSE n0l110i; + wire_n0i00Oii_dataout <= wire_n0i0l10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i00Oil_dataout <= wire_n0i0l1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i00OiO_dataout <= ((niOlli0li OR niOlli0iO) OR niOlli0il) AND NOT(wire_niO01lOO_dataout); + wire_n0i00Ol_dataout <= n0iO01i WHEN niOO0i0lO = '1' ELSE n0l110l; + wire_n0i00Oli_dataout <= (n0ii0Oll AND (niOllii1O OR niOlli0Ol)) AND NOT(wire_niO01lOO_dataout); + wire_n0i00Oll_dataout <= wire_n0i0iiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i00OlO_dataout <= wire_n0i0iiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i00OO_dataout <= n0iO01l WHEN niOO0i0lO = '1' ELSE n0l110O; + wire_n0i00OOi_dataout <= wire_n0i0iiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i00OOl_dataout <= wire_n0i0iili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i00OOO_dataout <= wire_n0i0iill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0100i_dataout <= (niOllii1O AND n0i011il) AND n0iil10O; + wire_n0i0100l_dataout <= (n0ii0Oll AND (wire_niO1011l_dataout AND niOlli01O)) AND n0iil10O; + wire_n0i0101O_dataout <= ((wire_niO1011l_dataout AND niOlli01l) AND n0i011ii) AND n0iil10O; + wire_n0i010i_dataout <= n0ilO0O WHEN niOO0i0lO = '1' ELSE n0iOlli; + wire_n0i010l_dataout <= n0ilOii WHEN niOO0i0lO = '1' ELSE n0iOlll; + wire_n0i010O_dataout <= n0ilOil WHEN niOO0i0lO = '1' ELSE n0iOllO; + wire_n0i010OO_dataout <= wire_n0i01i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0110i_dataout <= wire_n0i1il0O_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0i0110l_dataout <= wire_n0i1il1O_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0i0111i_dataout <= wire_n0i1ilOi_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0i0111l_dataout <= wire_n0i1illl_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0i0111O_dataout <= wire_n0i1ilil_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0i011i_dataout <= n0ilO1O WHEN niOO0i0lO = '1' ELSE n0iOlii; + wire_n0i011l_dataout <= n0ilO0i WHEN niOO0i0lO = '1' ELSE n0iOlil; + wire_n0i011li_dataout <= wire_n0i011Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i011ll_dataout <= wire_n0i0101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i011lO_dataout <= wire_n0i0100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i011O_dataout <= n0ilO0l WHEN niOO0i0lO = '1' ELSE n0iOliO; + wire_n0i011Oi_dataout <= wire_n0i0100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i011Ol_dataout <= wire_n0i011OO_dataout AND n0iil10O; + wire_n0i011OO_dataout <= n0i0101l OR (n0iil10O AND n0i0110O); + wire_n0i01i0i_dataout <= wire_n0i01iii_dataout AND NOT(niOll0O0i); + wire_n0i01i0l_dataout <= wire_n0i01lil_dataout WHEN niOll0O0i = '1' ELSE wire_n0i01iil_dataout; + wire_n0i01i0O_dataout <= wire_n0i01liO_dataout WHEN niOll0O0i = '1' ELSE wire_n0i01iiO_dataout; + wire_n0i01i1i_dataout <= wire_n0i01lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i01i1l_dataout <= wire_n0i01i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i01i1O_dataout <= wire_n0i01i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i01ii_dataout <= n0ilOiO WHEN niOO0i0lO = '1' ELSE n0iOlOi; + wire_n0i01iii_dataout <= n0i011iO WHEN wire_niO01ill_w_lg_n0i010ll14809w(0) = '1' ELSE wire_n0i01ilO_dataout; + wire_n0i01iil_dataout <= wire_n0i01iOi_dataout WHEN wire_niO01ill_w_lg_n0i010ll14809w(0) = '1' ELSE wire_n0i01ili_dataout; + wire_n0i01iiO_dataout <= wire_n0i01iOl_dataout WHEN wire_niO01ill_w_lg_n0i010ll14809w(0) = '1' ELSE wire_n0i01ill_dataout; + wire_n0i01il_dataout <= n0ilOli WHEN niOO0i0lO = '1' ELSE n0iOlOl; + wire_n0i01ili_dataout <= wire_n0i01l0i_dataout WHEN niOlli0li = '1' ELSE wire_n0i01iOi_dataout; + wire_n0i01ill_dataout <= wire_n0i01l0l_dataout WHEN niOlli0li = '1' ELSE wire_n0i01iOl_dataout; + wire_n0i01ilO_dataout <= wire_n0i01l0O_dataout WHEN niOlli0li = '1' ELSE n0i011iO; + wire_n0i01iO_dataout <= n0ilOll WHEN niOO0i0lO = '1' ELSE n0iOlOO; + wire_n0i01iOi_dataout <= n0i010lO AND NOT(niOll0O0O); + wire_n0i01iOl_dataout <= n0i010Oi AND NOT(niOll0O0O); + wire_n0i01l0i_dataout <= n0i010lO WHEN niOll0O0l = '1' ELSE wire_n0i01lii_o(0); + wire_n0i01l0l_dataout <= n0i010Oi WHEN niOll0O0l = '1' ELSE wire_n0i01lii_o(1); + wire_n0i01l0O_dataout <= n0i011iO OR niOll0O0l; + wire_n0i01li_dataout <= n0ilOlO WHEN niOO0i0lO = '1' ELSE n0iOO1i; + wire_n0i01lil_dataout <= n0i010lO OR niOlli0li; + wire_n0i01liO_dataout <= n0i010Oi AND NOT(niOlli0li); + wire_n0i01ll_dataout <= n0ilOOi WHEN niOO0i0lO = '1' ELSE n0iOO1l; + wire_n0i01lli_dataout <= wire_n0i01lll_dataout OR (niOllii1i AND (n0ii0O1O OR n0ii0l1O)); + wire_n0i01lll_dataout <= n0i010ll AND NOT(niOll0O0O); + wire_n0i01lO_dataout <= n0ilOOl WHEN niOO0i0lO = '1' ELSE n0iOO1O; + wire_n0i01O0l_dataout <= wire_n0i01Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i01O0O_dataout <= wire_n0i01OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i01Oi_dataout <= n0ilOOO WHEN niOO0i0lO = '1' ELSE n0iOO0i; + wire_n0i01Oii_dataout <= wire_n0i01OOi_dataout OR wire_niO01lOO_dataout; + wire_n0i01Oil_dataout <= wire_n0i01OOl_dataout OR wire_niO01lOO_dataout; + wire_n0i01OiO_dataout <= wire_n0i01OOO_dataout OR wire_niO01lOO_dataout; + wire_n0i01Ol_dataout <= n0iO11i WHEN niOO0i0lO = '1' ELSE n0iOO0l; + wire_n0i01Oli_dataout <= wire_n0i0011i_dataout OR wire_niO01lOO_dataout; + wire_n0i01Oll_dataout <= wire_n0i0011l_dataout OR niOlli10l; + wire_n0i01OlO_dataout <= wire_n0i0011O_dataout AND NOT(niOlli10l); + wire_n0i01OO_dataout <= n0iO11l WHEN niOO0i0lO = '1' ELSE n0iOO0O; + wire_n0i01OOi_dataout <= wire_n0i0010i_dataout OR niOlli10l; + wire_n0i01OOl_dataout <= wire_n0i0010l_dataout AND NOT(niOlli10l); + wire_n0i01OOO_dataout <= wire_n0i0010O_dataout OR niOlli10l; + wire_n0i0i00i_dataout <= wire_n0i0l0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i00l_dataout <= wire_n0i0l0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i00O_dataout <= wire_n0i0l0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i01i_dataout <= wire_n0i0l00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i01l_dataout <= wire_n0i0l00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i01O_dataout <= wire_n0i0l0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0i_dataout <= n0iO00O WHEN niOO0i0lO = '1' ELSE n0l11li; + wire_n0i0i0ii_dataout <= wire_n0i0iOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0il_dataout <= wire_n0i0iOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0iO_dataout <= wire_n0i0iOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0l_dataout <= n0iO0ii WHEN niOO0i0lO = '1' ELSE n0l11ll; + wire_n0i0i0li_dataout <= wire_n0i0iOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0ll_dataout <= wire_n0i0iOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0lO_dataout <= wire_n0i0l0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0O_dataout <= n0iO0il WHEN niOO0i0lO = '1' ELSE n0l11lO; + wire_n0i0i0Oi_dataout <= wire_n0i0iOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0Ol_dataout <= wire_n0i0iOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i0OO_dataout <= wire_n0i0iOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i10i_dataout <= wire_n0i0l1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i10l_dataout <= wire_n0i0l1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i10O_dataout <= wire_n0i0l1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i11i_dataout <= wire_n0i0iilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i11l_dataout <= wire_n0i0iiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i11O_dataout <= wire_n0i0iiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1i_dataout <= n0iO01O WHEN niOO0i0lO = '1' ELSE n0l11ii; + wire_n0i0i1ii_dataout <= wire_n0i0l1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1il_dataout <= wire_n0i0l1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1iO_dataout <= wire_n0i0l1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1l_dataout <= n0iO00i WHEN niOO0i0lO = '1' ELSE n0l11il; + wire_n0i0i1li_dataout <= wire_n0i0l1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1ll_dataout <= wire_n0i0l1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1lO_dataout <= wire_n0i0l01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1O_dataout <= n0iO00l WHEN niOO0i0lO = '1' ELSE n0l11iO; + wire_n0i0i1Oi_dataout <= wire_n0i0l01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1Ol_dataout <= wire_n0i0l01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0i1OO_dataout <= wire_n0i0l00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0ii0i_dataout <= wire_n0i0l11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0ii0l_dataout <= wire_n0i0l10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0ii0O_dataout <= wire_n0i0l0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0ii1i_dataout <= wire_n0i0iOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0ii1l_dataout <= wire_n0i0l11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0ii1O_dataout <= wire_n0i0l11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0iiii_dataout <= wire_n0i0iiOO_dataout AND NOT(niOll0OOO); + wire_n0i0iiil_dataout <= wire_n0i0il1i_dataout AND NOT(niOll0OOO); + wire_n0i0iiiO_dataout <= wire_n0i0il1l_dataout AND NOT(niOll0OOO); + wire_n0i0iil_dataout <= wire_n0i0l1i_dataout OR niOO0iili; + wire_n0i0iili_dataout <= wire_n0i0il1O_dataout AND NOT(niOll0OOO); + wire_n0i0iill_dataout <= wire_n0i0il0i_dataout AND NOT(niOll0OOO); + wire_n0i0iilO_dataout <= wire_n0i0il0l_dataout AND NOT(niOll0OOO); + wire_n0i0iiO_dataout <= wire_n0i0l1l_dataout OR niOO0iili; + wire_n0i0iiOi_dataout <= wire_n0i0il0O_dataout AND NOT(niOll0OOO); + wire_n0i0iiOl_dataout <= wire_n0i0ilii_dataout AND NOT(niOll0OOO); + wire_n0i0iiOO_dataout <= wire_n0i0ilil_dataout OR niOll0OOl; + wire_n0i0il0i_dataout <= wire_n0i0illO_dataout AND NOT(niOll0OOl); + wire_n0i0il0l_dataout <= wire_n0i0ilOi_dataout AND NOT(niOll0OOl); + wire_n0i0il0O_dataout <= wire_n0i0ilOl_dataout AND NOT(niOll0OOl); + wire_n0i0il1i_dataout <= wire_n0i0iliO_dataout AND NOT(niOll0OOl); + wire_n0i0il1l_dataout <= wire_n0i0illi_dataout AND NOT(niOll0OOl); + wire_n0i0il1O_dataout <= wire_n0i0illl_dataout AND NOT(niOll0OOl); + wire_n0i0ili_dataout <= wire_n0i0l1O_dataout OR niOO0iili; + wire_n0i0ilii_dataout <= wire_n0i0ilOO_dataout AND NOT(niOll0OOl); + wire_n0i0ilil_dataout <= wire_n0i0iO1i_o(0) WHEN niOll0OlO = '1' ELSE n0i000iO; + wire_n0i0iliO_dataout <= wire_n0i0iO1i_o(1) WHEN niOll0OlO = '1' ELSE n0i000li; + wire_n0i0ill_dataout <= wire_n0i0l0i_dataout OR niOO0iili; + wire_n0i0illi_dataout <= wire_n0i0iO1i_o(2) WHEN niOll0OlO = '1' ELSE n0i000ll; + wire_n0i0illl_dataout <= wire_n0i0iO1i_o(3) WHEN niOll0OlO = '1' ELSE n0i000lO; + wire_n0i0illO_dataout <= wire_n0i0iO1i_o(4) WHEN niOll0OlO = '1' ELSE n0i000Oi; + wire_n0i0ilO_dataout <= wire_n0i0l0l_dataout OR niOO0iili; + wire_n0i0ilOi_dataout <= wire_n0i0iO1i_o(5) WHEN niOll0OlO = '1' ELSE n0i000Ol; + wire_n0i0ilOl_dataout <= wire_n0i0iO1i_o(6) WHEN niOll0OlO = '1' ELSE n0i000OO; + wire_n0i0ilOO_dataout <= wire_n0i0iO1i_o(7) WHEN niOll0OlO = '1' ELSE n0i00i1i; + wire_n0i0iOi_dataout <= wire_n0i0l0O_dataout OR niOO0iili; + wire_n0i0iOii_dataout <= n0i00l0l WHEN niOlO1O0i = '1' ELSE wire_n0i0ll0i_dataout; + wire_n0i0iOil_dataout <= n0i00l0O WHEN niOlO1O0i = '1' ELSE wire_n0i0ll0l_dataout; + wire_n0i0iOiO_dataout <= n0i00lii WHEN niOlO1O0i = '1' ELSE wire_n0i0ll0O_dataout; + wire_n0i0iOl_dataout <= wire_n0i0lii_dataout OR niOO0iili; + wire_n0i0iOli_dataout <= n0i00lil WHEN niOlO1O0i = '1' ELSE wire_n0i0llii_dataout; + wire_n0i0iOll_dataout <= n0i00liO WHEN niOlO1O0i = '1' ELSE wire_n0i0llil_dataout; + wire_n0i0iOlO_dataout <= n0i00lll WHEN niOlO1O0i = '1' ELSE wire_n0i0llli_dataout; + wire_n0i0iOO_dataout <= wire_n0i0lil_dataout OR niOO0iili; + wire_n0i0iOOi_dataout <= n0i00llO WHEN niOlO1O0i = '1' ELSE wire_n0i0llll_dataout; + wire_n0i0iOOl_dataout <= n0i00lOi WHEN niOlO1O0i = '1' ELSE wire_n0i0lllO_dataout; + wire_n0i0iOOO_dataout <= n0i00lOl WHEN niOlO1O0i = '1' ELSE wire_n0i0llOi_dataout; + wire_n0i0l00i_dataout <= wire_n0i0lilO_dataout AND NOT(niOlO1O0i); + wire_n0i0l00l_dataout <= wire_n0i0liOi_dataout AND NOT(niOlO1O0i); + wire_n0i0l00O_dataout <= wire_n0i0liOl_dataout AND NOT(niOlO1O0i); + wire_n0i0l01i_dataout <= wire_n0i0liiO_dataout AND NOT(niOlO1O0i); + wire_n0i0l01l_dataout <= wire_n0i0lili_dataout AND NOT(niOlO1O0i); + wire_n0i0l01O_dataout <= wire_n0i0lill_dataout AND NOT(niOlO1O0i); + wire_n0i0l0i_dataout <= wire_n0i0llO_dataout OR niOO0iiiO; + wire_n0i0l0ii_dataout <= wire_n0i0liOO_dataout AND NOT(niOlO1O0i); + wire_n0i0l0il_dataout <= wire_n0i0ll1i_dataout AND NOT(niOlO1O0i); + wire_n0i0l0iO_dataout <= wire_n0i0ll1l_dataout AND NOT(niOlO1O0i); + wire_n0i0l0l_dataout <= wire_n0i0lOi_dataout OR niOO0iiiO; + wire_n0i0l0li_dataout <= wire_n0i0ll1O_dataout AND NOT(niOlO1O0i); + wire_n0i0l0ll_dataout <= wire_n0i0lliO_dataout AND NOT(niOlO1O0i); + wire_n0i0l0lO_dataout <= wire_n0i0lO1O_dataout AND NOT(niOlO1O0i); + wire_n0i0l0O_dataout <= wire_n0i0lOl_dataout OR niOO0iiiO; + wire_n0i0l0Oi_dataout <= n0i00O0l WHEN n0i0O1il = '1' ELSE n0i01O0i; + wire_n0i0l0Ol_dataout <= n0i0O10l WHEN n0i0O1il = '1' ELSE n0i0000l; + wire_n0i0l0OO_dataout <= n0i0O10O WHEN n0i0O1il = '1' ELSE n0i0000O; + wire_n0i0l10i_dataout <= n0i00O1O WHEN niOlO1O0i = '1' ELSE wire_n0i0lO1l_dataout; + wire_n0i0l10l_dataout <= wire_n0i0l0Oi_dataout AND NOT(niOlO1O0i); + wire_n0i0l10O_dataout <= wire_n0i0l0Ol_dataout AND NOT(niOlO1O0i); + wire_n0i0l11i_dataout <= n0i00lOO WHEN niOlO1O0i = '1' ELSE wire_n0i0llOl_dataout; + wire_n0i0l11l_dataout <= n0i00O1i WHEN niOlO1O0i = '1' ELSE wire_n0i0llOO_dataout; + wire_n0i0l11O_dataout <= n0i00O1l WHEN niOlO1O0i = '1' ELSE wire_n0i0lO1i_dataout; + wire_n0i0l1i_dataout <= wire_n0i0liO_dataout OR niOO0iiiO; + wire_n0i0l1ii_dataout <= wire_n0i0l0OO_dataout AND NOT(niOlO1O0i); + wire_n0i0l1il_dataout <= wire_n0i0li1i_dataout AND NOT(niOlO1O0i); + wire_n0i0l1iO_dataout <= wire_n0i0li1l_dataout AND NOT(niOlO1O0i); + wire_n0i0l1l_dataout <= wire_n0i0lli_dataout OR niOO0iiiO; + wire_n0i0l1li_dataout <= wire_n0i0li1O_dataout AND NOT(niOlO1O0i); + wire_n0i0l1ll_dataout <= wire_n0i0li0i_dataout AND NOT(niOlO1O0i); + wire_n0i0l1lO_dataout <= wire_n0i0li0l_dataout AND NOT(niOlO1O0i); + wire_n0i0l1O_dataout <= wire_n0i0lll_dataout OR niOO0iiiO; + wire_n0i0l1Oi_dataout <= wire_n0i0li0O_dataout AND NOT(niOlO1O0i); + wire_n0i0l1Ol_dataout <= wire_n0i0liii_dataout AND NOT(niOlO1O0i); + wire_n0i0l1OO_dataout <= wire_n0i0liil_dataout AND NOT(niOlO1O0i); + wire_n0i0li0i_dataout <= n0i0O1Oi WHEN n0i0O1il = '1' ELSE n0i00i0l; + wire_n0i0li0l_dataout <= n0i0O1Ol WHEN n0i0O1il = '1' ELSE n0i00i0O; + wire_n0i0li0O_dataout <= n0i0O1OO WHEN n0i0O1il = '1' ELSE n0i00iii; + wire_n0i0li1i_dataout <= n0i0O1li WHEN n0i0O1il = '1' ELSE n0i00i1l; + wire_n0i0li1l_dataout <= n0i0O1ll WHEN n0i0O1il = '1' ELSE n0i00i1O; + wire_n0i0li1O_dataout <= n0i0O1lO WHEN n0i0O1il = '1' ELSE n0i00i0i; + wire_n0i0lii_dataout <= wire_n0i0lOO_dataout OR niOO0iiiO; + wire_n0i0liii_dataout <= n0i0O01i WHEN n0i0O1il = '1' ELSE n0i00iil; + wire_n0i0liil_dataout <= n0i0O01l WHEN n0i0O1il = '1' ELSE n0i00iiO; + wire_n0i0liiO_dataout <= n0i0O01O WHEN n0i0O1il = '1' ELSE n0i00ili; + wire_n0i0lil_dataout <= wire_n0i0O1i_dataout OR niOO0iiiO; + wire_n0i0lili_dataout <= n0i0O00i WHEN n0i0O1il = '1' ELSE n0i00ill; + wire_n0i0lill_dataout <= n0i0O00l WHEN n0i0O1il = '1' ELSE n0i00ilO; + wire_n0i0lilO_dataout <= n0i0O00O WHEN n0i0O1il = '1' ELSE n0i00iOi; + wire_n0i0liO_dataout <= wire_n0i0O1l_dataout OR niOO0iiil; + wire_n0i0liOi_dataout <= n0i0O0ii WHEN n0i0O1il = '1' ELSE n0i00iOl; + wire_n0i0liOl_dataout <= n0i0O0il WHEN n0i0O1il = '1' ELSE n0i00iOO; + wire_n0i0liOO_dataout <= n0i0O0iO WHEN n0i0O1il = '1' ELSE n0i00l1i; + wire_n0i0ll0i_dataout <= n0i0O0Oi WHEN n0i0O1il = '1' ELSE n0i00l0l; + wire_n0i0ll0l_dataout <= n0i0O0Ol WHEN n0i0O1il = '1' ELSE n0i00l0O; + wire_n0i0ll0O_dataout <= n0i0O0OO WHEN n0i0O1il = '1' ELSE n0i00lii; + wire_n0i0ll1i_dataout <= n0i0O0li WHEN n0i0O1il = '1' ELSE n0i00l1l; + wire_n0i0ll1l_dataout <= n0i0O0ll WHEN n0i0O1il = '1' ELSE n0i00l1O; + wire_n0i0ll1O_dataout <= n0i0O0lO WHEN n0i0O1il = '1' ELSE n0i00l0i; + wire_n0i0lli_dataout <= wire_n0i0O1O_dataout OR niOO0iiil; + wire_n0i0llii_dataout <= n0i0Oi1i WHEN n0i0O1il = '1' ELSE n0i00lil; + wire_n0i0llil_dataout <= n0i0Oi1l WHEN n0i0O1il = '1' ELSE n0i00liO; + wire_n0i0lliO_dataout <= n0i0Oi1O WHEN n0i0O1il = '1' ELSE n0i00lli; + wire_n0i0lll_dataout <= wire_n0i0O0i_dataout OR niOO0iiil; + wire_n0i0llli_dataout <= n0i0Oi0i WHEN n0i0O1il = '1' ELSE n0i00lll; + wire_n0i0llll_dataout <= n0i0Oi0l WHEN n0i0O1il = '1' ELSE n0i00llO; + wire_n0i0lllO_dataout <= n0i0Oi0O WHEN n0i0O1il = '1' ELSE n0i00lOi; + wire_n0i0llO_dataout <= wire_n0i0O0l_dataout OR niOO0iiil; + wire_n0i0llOi_dataout <= n0i0Oiii WHEN n0i0O1il = '1' ELSE n0i00lOl; + wire_n0i0llOl_dataout <= n0i0Oiil WHEN n0i0O1il = '1' ELSE n0i00lOO; + wire_n0i0llOO_dataout <= n0i0OiiO WHEN n0i0O1il = '1' ELSE n0i00O1i; + wire_n0i0lO1i_dataout <= n0i0Oili WHEN n0i0O1il = '1' ELSE n0i00O1l; + wire_n0i0lO1l_dataout <= n0i0Oill WHEN n0i0O1il = '1' ELSE n0i00O1O; + wire_n0i0lO1O_dataout <= n0i0OilO WHEN n0i0O1il = '1' ELSE n0i00O0i; + wire_n0i0lOi_dataout <= wire_n0i0O0O_dataout AND NOT(niOO0iiil); + wire_n0i0lOl_dataout <= wire_n0i0Oii_dataout AND NOT(niOO0iiil); + wire_n0i0lOO_dataout <= wire_n0i0Oil_dataout AND NOT(niOO0iiil); + wire_n0i0O0i_dataout <= wire_n0i0OlO_dataout OR niOO0iiil; + wire_n0i0O0l_dataout <= wire_n0i0OOi_dataout OR niOO0iiil; + wire_n0i0O0O_dataout <= wire_n0i0OOl_dataout AND NOT(niOO0iiil); + wire_n0i0O1i_dataout <= wire_n0i0OiO_dataout AND NOT(niOO0iiil); + wire_n0i0O1l_dataout <= wire_n0i0Oli_dataout OR niOO0iiil; + wire_n0i0O1O_dataout <= wire_n0i0Oll_dataout OR niOO0iiil; + wire_n0i0Oii_dataout <= wire_n0i0OOO_dataout AND NOT(niOO0iiil); + wire_n0i0Oil_dataout <= wire_n0ii11i_dataout AND NOT(niOO0iiil); + wire_n0i0OiO_dataout <= wire_n0ii11l_dataout AND NOT(niOO0iiil); + wire_n0i0Ol0i_dataout <= wire_n0ii1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0Ol0l_dataout <= wire_n0ii1llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0Ol0O_dataout <= ((wire_w_lg_niOlli0Ol14667w(0) AND (wire_w_lg_niOlli00i14668w(0) AND wire_w_lg_w_lg_niOllii1O14531w14669w(0))) AND (wire_w_lg_w_lg_w_lg_niOlli10l14672w14676w14677w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n0i0Ol1O_dataout <= wire_n0ii1lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0Oli_dataout <= n0il00i WHEN niOO0iiii = '1' ELSE wire_n0ii11O_dataout; + wire_n0i0Olii_dataout <= (wire_w_lg_w_lg_w_lg_niOlli01i14661w14663w14664w(0) AND wire_niO01ill_w_lg_n0i0O1iO14665w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0i0Olil_dataout <= wire_n0ii10Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OliO_dataout <= wire_n0ii1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0Oll_dataout <= n0il00l WHEN niOO0iiii = '1' ELSE wire_n0ii10i_dataout; + wire_n0i0Olli_dataout <= wire_n0ii1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0Olll_dataout <= wire_n0ii1l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OllO_dataout <= wire_n0ii1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OlO_dataout <= n0il00O WHEN niOO0iiii = '1' ELSE wire_n0ii10l_dataout; + wire_n0i0OlOi_dataout <= wire_n0ii1liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OlOl_dataout <= wire_n0ii1lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OlOO_dataout <= wire_n0ii1lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OO0i_dataout <= wire_n0ii1O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OO0l_dataout <= wire_n0ii1O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OO0O_dataout <= wire_n0ii1Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OO1i_dataout <= wire_n0ii1O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OO1l_dataout <= wire_n0ii1O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OO1O_dataout <= wire_n0ii1O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOi_dataout <= n0il0ii WHEN niOO0iiii = '1' ELSE wire_n0ii10O_dataout; + wire_n0i0OOii_dataout <= wire_n0ii1Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOil_dataout <= wire_n0ii1OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOiO_dataout <= wire_n0ii1lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOl_dataout <= n0il0il WHEN niOO0iiii = '1' ELSE wire_n0ii1ii_dataout; + wire_n0i0OOli_dataout <= wire_n0ii1lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOll_dataout <= wire_n0ii1O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOlO_dataout <= wire_n0ii1Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOO_dataout <= n0il0iO WHEN niOO0iiii = '1' ELSE wire_n0ii1il_dataout; + wire_n0i0OOOi_dataout <= wire_n0ii1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOOl_dataout <= wire_n0ii1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i0OOOO_dataout <= wire_n0ii1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1000i_dataout <= n0iliiil WHEN niOll0lOi = '1' ELSE (n0iliiil XOR n0i10iil); + wire_n0i1000O_dataout <= n0iliiii WHEN niOll0lOi = '1' ELSE (n0iliiii XOR n0i10iiO); + wire_n0i1001l_dataout <= n0iliiiO WHEN niOll0lOi = '1' ELSE (n0iliiiO XOR n0i10iii); + wire_n0i100i_dataout <= n0l111i AND niOO0i0ii; + wire_n0i100il_dataout <= n0ilii0O WHEN niOll0lOi = '1' ELSE (n0ilii0O XOR n0i10ili); + wire_n0i100l_dataout <= n0l111l AND niOO0i0ii; + wire_n0i100li_dataout <= n0ilii0l WHEN niOll0lOi = '1' ELSE (n0ilii0l XOR n0i10ill); + wire_n0i100O_dataout <= n0l111O AND niOO0i0ii; + wire_n0i101i_dataout <= n0iOOOi AND niOO0i0ii; + wire_n0i101iO_dataout <= n0iliilO WHEN niOll0lOi = '1' ELSE (n0iliilO XOR n0i10i0i); + wire_n0i101l_dataout <= n0iOOOl AND niOO0i0ii; + wire_n0i101lO_dataout <= n0iliill WHEN niOll0lOi = '1' ELSE (n0iliill XOR n0i10i0l); + wire_n0i101O_dataout <= n0iOOOO AND niOO0i0ii; + wire_n0i101Ol_dataout <= n0iliili WHEN niOll0lOi = '1' ELSE (n0iliili XOR n0i10i0O); + wire_n0i10ii_dataout <= n0l110i AND niOO0i0ii; + wire_n0i10il_dataout <= n0l110l AND niOO0i0ii; + wire_n0i10iO_dataout <= n0l110O AND niOO0i0ii; + wire_n0i10iOi_dataout <= wire_n0i10lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10iOl_dataout <= wire_n0i10lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10iOO_dataout <= wire_n0i10O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10l0i_dataout <= wire_n0i10O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10l0l_dataout <= wire_n0i10O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10l0O_dataout <= wire_n0i10Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10l1i_dataout <= wire_n0i10O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10l1l_dataout <= wire_n0i10O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10l1O_dataout <= wire_n0i10O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10li_dataout <= n0l11ii AND niOO0i0ii; + wire_n0i10lii_dataout <= wire_n0i10Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10lil_dataout <= wire_n0i10OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10liO_dataout <= wire_n0i10Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10ll_dataout <= n0l11il AND niOO0i0ii; + wire_n0i10lli_dataout <= wire_n0i10Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10lll_dataout <= wire_n0i10OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10llO_dataout <= wire_n0i10OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10lO_dataout <= n0l11iO AND niOO0i0ii; + wire_n0i10lOi_dataout <= wire_n0i10OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i10lOl_dataout <= wire_n0i10OOO_dataout OR niOll0lOO; + wire_n0i10lOO_dataout <= wire_n0i1i11i_dataout OR niOll0lOO; + wire_n0i10O0i_dataout <= wire_n0i1i10l_dataout OR niOll0lOO; + wire_n0i10O0l_dataout <= wire_n0i1i10O_dataout OR niOll0lOO; + wire_n0i10O0O_dataout <= wire_n0i1i1ii_dataout OR niOll0lOO; + wire_n0i10O1i_dataout <= wire_n0i1i11l_dataout OR niOll0lOO; + wire_n0i10O1l_dataout <= wire_n0i1i11O_dataout OR niOll0lOO; + wire_n0i10O1O_dataout <= wire_n0i1i10i_dataout OR niOll0lOO; + wire_n0i10Oi_dataout <= n0l11li AND niOO0i0ii; + wire_n0i10Oii_dataout <= wire_n0i1i1il_dataout OR niOll0lOO; + wire_n0i10Oil_dataout <= wire_n0i1i1iO_dataout OR niOll0lOO; + wire_n0i10OiO_dataout <= wire_n0i1i1li_dataout OR niOll0lOO; + wire_n0i10Ol_dataout <= n0l11ll AND niOO0i0ii; + wire_n0i10Oli_dataout <= wire_n0i1i1ll_dataout OR niOll0lOO; + wire_n0i10Oll_dataout <= wire_n0i1i1lO_dataout OR niOll0lOO; + wire_n0i10OlO_dataout <= wire_n0i1i1Oi_dataout OR niOll0lOO; + wire_n0i10OO_dataout <= n0l11lO AND niOO0i0ii; + wire_n0i10OOi_dataout <= wire_n0i1i1Ol_dataout OR niOll0lOO; + wire_n0i10OOl_dataout <= wire_n0i1i1OO_dataout OR niOll0lOO; + wire_n0i10OOO_dataout <= n0i1001i WHEN niOll0lOl = '1' ELSE n0i10i0i; + wire_n0i1100i_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n00OOlil; + wire_n0i1100l_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n00OOliO; + wire_n0i1100O_dataout <= wire_n1lllOiO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i110ii_dataout; + wire_n0i1101l_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n00OOlli; + wire_n0i1101O_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n00O00ii; + wire_n0i110i_dataout <= n0iOO1i AND niOO0i0ii; + wire_n0i110ii_dataout <= wire_n0i110il_dataout AND NOT(niOll0llO); + wire_n0i110il_dataout <= n1l001OO AND NOT(niOll0lll); + wire_n0i110iO_dataout <= wire_n1llOl1l_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11i1l_dataout; + wire_n0i110l_dataout <= n0iOO1l AND niOO0i0ii; + wire_n0i110li_dataout <= wire_n1llOl1O_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11i1O_dataout; + wire_n0i110ll_dataout <= wire_n1llOl0i_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11i0i_dataout; + wire_n0i110lO_dataout <= wire_n1llOl0l_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11i0l_dataout; + wire_n0i110O_dataout <= n0iOO1O AND niOO0i0ii; + wire_n0i110Oi_dataout <= wire_n1llOl0O_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11i0O_dataout; + wire_n0i110Ol_dataout <= wire_n1llOlii_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11iii_dataout; + wire_n0i110OO_dataout <= wire_n1llOlil_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11iil_dataout; + wire_n0i1110i_dataout <= wire_n0i110li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1110l_dataout <= wire_n0i110ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1110O_dataout <= wire_n0i110lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1111i_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w15186w(0) AND wire_w_lg_niOll0liO15187w(0)) AND wire_niO01ill_w_lg_n00OOlli15189w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0i1111l_dataout <= wire_n0i1100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1111O_dataout <= wire_n0i110iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i111i_dataout <= n0iOlOi AND niOO0i0ii; + wire_n0i111ii_dataout <= wire_n0i110Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i111il_dataout <= wire_n0i110Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i111iO_dataout <= wire_n0i110OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i111l_dataout <= n0iOlOl AND niOO0i0ii; + wire_n0i111li_dataout <= wire_n0i11i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i111O_dataout <= n0iOlOO AND niOO0i0ii; + wire_n0i11i0i_dataout <= wire_nlOO10OOO_dataout WHEN niOll0llO = '1' ELSE wire_n0i11ilO_dataout; + wire_n0i11i0l_dataout <= wire_nlOO1i11i_dataout WHEN niOll0llO = '1' ELSE wire_n0i11iOi_dataout; + wire_n0i11i0O_dataout <= wire_nlOO1i11l_dataout WHEN niOll0llO = '1' ELSE wire_n0i11iOl_dataout; + wire_n0i11i1i_dataout <= wire_n1llOliO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0i11iiO_dataout; + wire_n0i11i1l_dataout <= wire_nlOO10OOi_dataout WHEN niOll0llO = '1' ELSE wire_n0i11ili_dataout; + wire_n0i11i1O_dataout <= wire_nlOO10OOl_dataout WHEN niOll0llO = '1' ELSE wire_n0i11ill_dataout; + wire_n0i11ii_dataout <= n0iOO0i AND niOO0i0ii; + wire_n0i11iii_dataout <= wire_nlOO1i11O_dataout WHEN niOll0llO = '1' ELSE wire_n0i11iOO_dataout; + wire_n0i11iil_dataout <= wire_nlOO1i10i_dataout WHEN niOll0llO = '1' ELSE wire_n0i11l1i_dataout; + wire_n0i11iiO_dataout <= wire_nlOO1i10l_dataout WHEN niOll0llO = '1' ELSE wire_n0i11l1l_dataout; + wire_n0i11il_dataout <= n0iOO0l AND niOO0i0ii; + wire_n0i11ili_dataout <= wire_niili1Ol_dataout WHEN niOll0lll = '1' ELSE n1l001ii; + wire_n0i11ill_dataout <= wire_niili1OO_dataout WHEN niOll0lll = '1' ELSE n1l001il; + wire_n0i11ilO_dataout <= n1101l1i WHEN niOll0lll = '1' ELSE n1l001iO; + wire_n0i11iO_dataout <= n0iOO0O AND niOO0i0ii; + wire_n0i11iOi_dataout <= n1l001li AND NOT(niOll0lll); + wire_n0i11iOl_dataout <= n1l001ll AND NOT(niOll0lll); + wire_n0i11iOO_dataout <= n1l001lO AND NOT(niOll0lll); + wire_n0i11l0l_dataout <= k_cnt(57) AND NOT(wire_n0i11lll_o); + wire_n0i11l0O_dataout <= k_cnt(58) AND NOT(wire_n0i11lll_o); + wire_n0i11l1i_dataout <= n1l001Oi AND NOT(niOll0lll); + wire_n0i11l1l_dataout <= n1l001Ol AND NOT(niOll0lll); + wire_n0i11li_dataout <= n0iOOii AND niOO0i0ii; + wire_n0i11lii_dataout <= k_cnt(59) OR wire_n0i11lll_o; + wire_n0i11lil_dataout <= k_cnt(60) AND NOT(wire_n0i11lll_o); + wire_n0i11liO_dataout <= k_cnt(61) AND NOT(wire_n0i11lll_o); + wire_n0i11ll_dataout <= n0iOOil AND niOO0i0ii; + wire_n0i11lli_dataout <= k_cnt(62) AND NOT(wire_n0i11lll_o); + wire_n0i11lO_dataout <= n0iOOiO AND niOO0i0ii; + wire_n0i11Oi_dataout <= n0iOOli AND niOO0i0ii; + wire_n0i11Ol_dataout <= n0iOOll AND niOO0i0ii; + wire_n0i11OO_dataout <= n0iOOlO AND niOO0i0ii; + wire_n0i1i00i_dataout <= n0i10ilO OR n111i10i; + wire_n0i1i01l_dataout <= wire_n0i1i01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1i01O_dataout <= wire_n0i1i00i_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n0i10ilO) AND niOll0lOO)); + wire_n0i1i10i_dataout <= n0i100OO WHEN niOll0lOl = '1' ELSE (n0i10i0i XOR (n0i10iil XOR n0i10i0l)); + wire_n0i1i10l_dataout <= n0i10i1i WHEN niOll0lOl = '1' ELSE (n0i10i0i XOR (n0i10i0l XOR (n0i10iiO XOR n0i10i0O))); + wire_n0i1i10O_dataout <= n0i10i1l WHEN niOll0lOl = '1' ELSE (n0i10i0l XOR (n0i10i0O XOR (n0i10ili XOR n0i10iii))); + wire_n0i1i11i_dataout <= n0i100lO WHEN niOll0lOl = '1' ELSE n0i10i0l; + wire_n0i1i11l_dataout <= n0i100Oi WHEN niOll0lOl = '1' ELSE n0i10i0O; + wire_n0i1i11O_dataout <= n0i100Ol WHEN niOll0lOl = '1' ELSE (n0i10iii XOR n0i10i0i); + wire_n0i1i1ii_dataout <= n0i10i1O WHEN niOll0lOl = '1' ELSE (n0i10i0O XOR (n0i10iii XOR (n0i10ill XOR n0i10iil))); + wire_n0i1i1il_dataout <= n0i10i0i WHEN niOll0lOl = '1' ELSE (n0i10iii XOR (n0i10iil XOR (n0i10iiO XOR n0i1001i))); + wire_n0i1i1iO_dataout <= n0i10i0l WHEN niOll0lOl = '1' ELSE (n0i10iil XOR (n0i10iiO XOR (n0i10ili XOR n0i100lO))); + wire_n0i1i1li_dataout <= n0i10i0O WHEN niOll0lOl = '1' ELSE (n0i10iiO XOR (n0i10ili XOR (n0i10ill XOR n0i100Oi))); + wire_n0i1i1ll_dataout <= n0i10iii WHEN niOll0lOl = '1' ELSE (n0i10ili XOR (n0i10ill XOR n0i100Ol)); + wire_n0i1i1lO_dataout <= n0i10iil WHEN niOll0lOl = '1' ELSE (n0i10ill XOR n0i100OO); + wire_n0i1i1Oi_dataout <= n0i10iiO WHEN niOll0lOl = '1' ELSE n0i10i1i; + wire_n0i1i1Ol_dataout <= n0i10ili WHEN niOll0lOl = '1' ELSE n0i10i1l; + wire_n0i1i1OO_dataout <= n0i10ill WHEN niOll0lOl = '1' ELSE n0i10i1O; + wire_n0i1il0O_dataout <= wire_niO101li_dataout WHEN niOll0O1i = '1' ELSE (wire_niO101li_dataout XOR n0i1iOOl); + wire_n0i1il0O_w_lg_dataout14919w(0) <= NOT wire_n0i1il0O_dataout; + wire_n0i1il1O_dataout <= wire_niO101ll_dataout WHEN niOll0O1i = '1' ELSE (wire_niO101ll_dataout XOR n0i1iOOi); + wire_n0i1il1O_w_lg_dataout14921w(0) <= NOT wire_n0i1il1O_dataout; + wire_n0i1ilil_dataout <= wire_niO101iO_dataout WHEN niOll0O1i = '1' ELSE (wire_niO101iO_dataout XOR n0i1iOOO); + wire_n0i1ilil_w_lg_dataout14917w(0) <= NOT wire_n0i1ilil_dataout; + wire_n0i1illl_dataout <= wire_niO101il_dataout WHEN niOll0O1i = '1' ELSE (wire_niO101il_dataout XOR n0i1l11i); + wire_n0i1illl_w_lg_dataout14915w(0) <= NOT wire_n0i1illl_dataout; + wire_n0i1ilOi_dataout <= wire_niO101ii_dataout WHEN niOll0O1i = '1' ELSE (wire_niO101ii_dataout XOR n0i1l11l); + wire_n0i1ilOi_w_lg_dataout14913w(0) <= NOT wire_n0i1ilOi_dataout; + wire_n0i1ilOO_dataout <= wire_niO1010O_dataout WHEN niOll0O1i = '1' ELSE (wire_niO1010O_dataout XOR n0i1l11O); + wire_n0i1ilOO_w_lg_dataout14911w(0) <= NOT wire_n0i1ilOO_dataout; + wire_n0i1iO0i_dataout <= wire_niO1010i_dataout WHEN niOll0O1i = '1' ELSE (wire_niO1010i_dataout XOR n0i1l10l); + wire_n0i1iO0i_w_lg_dataout14907w(0) <= NOT wire_n0i1iO0i_dataout; + wire_n0i1iO1l_dataout <= wire_niO1010l_dataout WHEN niOll0O1i = '1' ELSE (wire_niO1010l_dataout XOR n0i1l10i); + wire_n0i1iO1l_w_lg_dataout14909w(0) <= NOT wire_n0i1iO1l_dataout; + wire_n0i1l00i_dataout <= wire_n0i1li0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l00l_dataout <= wire_n0i1li0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l00O_dataout <= wire_n0i1liii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l01i_dataout <= wire_n0i1li1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l01l_dataout <= wire_n0i1li1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l01O_dataout <= wire_n0i1li0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l0i_dataout <= n0ili0O WHEN niOO0i0lO = '1' ELSE n0iO0li; + wire_n0i1l0ii_dataout <= wire_n0i1liil_dataout OR niOll0O1l; + wire_n0i1l0il_dataout <= wire_n0i1liiO_dataout OR niOll0O1l; + wire_n0i1l0iO_dataout <= wire_n0i1lili_dataout OR niOll0O1l; + wire_n0i1l0l_dataout <= n0iliii WHEN niOO0i0lO = '1' ELSE n0iO0ll; + wire_n0i1l0li_dataout <= wire_n0i1lill_dataout OR niOll0O1l; + wire_n0i1l0ll_dataout <= wire_n0i1lilO_dataout OR niOll0O1l; + wire_n0i1l0lO_dataout <= wire_n0i1liOi_dataout OR niOll0O1l; + wire_n0i1l0O_dataout <= n0iliil WHEN niOO0i0lO = '1' ELSE n0iO0lO; + wire_n0i1l0Oi_dataout <= wire_n0i1liOl_dataout OR niOll0O1l; + wire_n0i1l0Ol_dataout <= wire_n0i1liOO_dataout OR niOll0O1l; + wire_n0i1l0OO_dataout <= wire_n0i1ll1i_dataout OR niOll0O1l; + wire_n0i1l10O_dataout <= wire_n0i1l0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1ii_dataout <= wire_n0i1l0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1il_dataout <= wire_n0i1l0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1iO_dataout <= wire_n0i1l0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1li_dataout <= wire_n0i1l0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1ll_dataout <= wire_n0i1l0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1lO_dataout <= wire_n0i1l0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1O_dataout <= n0ili0l WHEN niOO0i0lO = '1' ELSE n0iO0iO; + wire_n0i1l1Oi_dataout <= wire_n0i1l0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1Ol_dataout <= wire_n0i1l0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1l1OO_dataout <= wire_n0i1li1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0i1li0i_dataout <= wire_n0i1ll0l_dataout OR niOll0O1l; + wire_n0i1li0l_dataout <= wire_n0i1ll0O_dataout OR niOll0O1l; + wire_n0i1li0O_dataout <= wire_n0i1llii_dataout OR niOll0O1l; + wire_n0i1li1i_dataout <= wire_n0i1ll1l_dataout OR niOll0O1l; + wire_n0i1li1l_dataout <= wire_n0i1ll1O_dataout OR niOll0O1l; + wire_n0i1li1O_dataout <= wire_n0i1ll0i_dataout OR niOll0O1l; + wire_n0i1lii_dataout <= n0iliiO WHEN niOO0i0lO = '1' ELSE n0iO0Oi; + wire_n0i1liii_dataout <= wire_n0i1llil_dataout OR niOll0O1l; + wire_n0i1liil_dataout <= n0i1illi WHEN niOll0O1O = '1' ELSE n0i1iOOi; + wire_n0i1liiO_dataout <= n0i1iO0O WHEN niOll0O1O = '1' ELSE n0i1iOOl; + wire_n0i1lil_dataout <= n0ilili WHEN niOO0i0lO = '1' ELSE n0iO0Ol; + wire_n0i1lili_dataout <= n0i1iOii WHEN niOll0O1O = '1' ELSE n0i1iOOO; + wire_n0i1lill_dataout <= n0i1iOil WHEN niOll0O1O = '1' ELSE (n0i1l11i XOR n0i1iOOi); + wire_n0i1lilO_dataout <= n0i1iOiO WHEN niOll0O1O = '1' ELSE (n0i1iOOi XOR (n0i1l11l XOR n0i1iOOl)); + wire_n0i1liO_dataout <= n0ilill WHEN niOO0i0lO = '1' ELSE n0iO0OO; + wire_n0i1liOi_dataout <= n0i1iOli WHEN niOll0O1O = '1' ELSE (n0i1iOOi XOR (n0i1iOOl XOR (n0i1l11O XOR n0i1iOOO))); + wire_n0i1liOl_dataout <= n0i1iOll WHEN niOll0O1O = '1' ELSE (n0i1iOOl XOR (n0i1iOOO XOR (n0i1l10i XOR n0i1l11i))); + wire_n0i1liOO_dataout <= n0i1iOlO WHEN niOll0O1O = '1' ELSE (n0i1iOOO XOR (n0i1l11i XOR (n0i1l10l XOR n0i1l11l))); + wire_n0i1ll0i_dataout <= n0i1l11i WHEN niOll0O1O = '1' ELSE (n0i1l10i XOR (n0i1l10l XOR n0i1iOil)); + wire_n0i1ll0l_dataout <= n0i1l11l WHEN niOll0O1O = '1' ELSE (n0i1l10l XOR n0i1iOiO); + wire_n0i1ll0O_dataout <= n0i1l11O WHEN niOll0O1O = '1' ELSE n0i1iOli; + wire_n0i1ll1i_dataout <= n0i1iOOi WHEN niOll0O1O = '1' ELSE (n0i1l11i XOR (n0i1l11l XOR (n0i1l11O XOR n0i1illi))); + wire_n0i1ll1l_dataout <= n0i1iOOl WHEN niOll0O1O = '1' ELSE (n0i1l11l XOR (n0i1l11O XOR (n0i1l10i XOR n0i1iO0O))); + wire_n0i1ll1O_dataout <= n0i1iOOO WHEN niOll0O1O = '1' ELSE (n0i1l11O XOR (n0i1l10i XOR (n0i1l10l XOR n0i1iOii))); + wire_n0i1lli_dataout <= n0ililO WHEN niOO0i0lO = '1' ELSE n0iOi1i; + wire_n0i1llii_dataout <= n0i1l10i WHEN niOll0O1O = '1' ELSE n0i1iOll; + wire_n0i1llil_dataout <= n0i1l10l WHEN niOll0O1O = '1' ELSE n0i1iOlO; + wire_n0i1lll_dataout <= n0iliOi WHEN niOO0i0lO = '1' ELSE n0iOi1l; + wire_n0i1llO_dataout <= n0iliOl WHEN niOO0i0lO = '1' ELSE n0iOi1O; + wire_n0i1lOi_dataout <= n0iliOO WHEN niOO0i0lO = '1' ELSE n0iOi0i; + wire_n0i1lOl_dataout <= n0ill1i WHEN niOO0i0lO = '1' ELSE n0iOi0l; + wire_n0i1lOO_dataout <= n0ill1l WHEN niOO0i0lO = '1' ELSE n0iOi0O; + wire_n0i1O0i_dataout <= n0ill0O WHEN niOO0i0lO = '1' ELSE n0iOili; + wire_n0i1O0l_dataout <= n0illii WHEN niOO0i0lO = '1' ELSE n0iOill; + wire_n0i1O0O_dataout <= n0illil WHEN niOO0i0lO = '1' ELSE n0iOilO; + wire_n0i1O1i_dataout <= n0ill1O WHEN niOO0i0lO = '1' ELSE n0iOiii; + wire_n0i1O1l_dataout <= n0ill0i WHEN niOO0i0lO = '1' ELSE n0iOiil; + wire_n0i1O1O_dataout <= n0ill0l WHEN niOO0i0lO = '1' ELSE n0iOiiO; + wire_n0i1Oii_dataout <= n0illiO WHEN niOO0i0lO = '1' ELSE n0iOiOi; + wire_n0i1Oil_dataout <= n0illli WHEN niOO0i0lO = '1' ELSE n0iOiOl; + wire_n0i1OiO_dataout <= n0illll WHEN niOO0i0lO = '1' ELSE n0iOiOO; + wire_n0i1Oli_dataout <= n0illlO WHEN niOO0i0lO = '1' ELSE n0iOl1i; + wire_n0i1Oll_dataout <= n0illOi WHEN niOO0i0lO = '1' ELSE n0iOl1l; + wire_n0i1OlO_dataout <= n0illOl WHEN niOO0i0lO = '1' ELSE n0iOl1O; + wire_n0i1OOi_dataout <= n0illOO WHEN niOO0i0lO = '1' ELSE n0iOl0i; + wire_n0i1OOl_dataout <= n0ilO1i WHEN niOO0i0lO = '1' ELSE n0iOl0l; + wire_n0i1OOlO_dataout <= wire_niO1011O_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0i1OOO_dataout <= n0ilO1l WHEN niOO0i0lO = '1' ELSE n0iOl0O; + wire_n0i1OOOi_dataout <= wire_n0i1iO0i_dataout AND wire_niO11OOl_w_lg_dataout14816w(0); + wire_n0i1OOOl_dataout <= wire_n0i1iO1l_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0i1OOOO_dataout <= wire_n0i1ilOO_dataout OR NOT(wire_niO11OOl_w_lg_dataout14816w(0)); + wire_n0ii000i_dataout <= wire_n0ii00ii_o(2) AND niOlli1li; + wire_n0ii000l_dataout <= wire_n0ii00ii_o(3) AND niOlli1li; + wire_n0ii000O_dataout <= wire_n0ii00ii_o(4) AND niOlli1li; + wire_n0ii001i_dataout <= wire_n0ii000l_dataout WHEN wire_w_lg_niOlli1iO14601w(0) = '1' ELSE n0i0OiOO; + wire_n0ii001l_dataout <= wire_n0ii000O_dataout WHEN wire_w_lg_niOlli1iO14601w(0) = '1' ELSE n0i0Ol1i; + wire_n0ii001O_dataout <= wire_n0ii00ii_o(1) AND niOlli1li; + wire_n0ii00i_dataout <= n0il1li WHEN niOO0ii1l = '1' ELSE wire_n0ii0lO_dataout; + wire_n0ii00l_dataout <= n0il1ll WHEN niOO0ii1l = '1' ELSE wire_n0ii0Oi_dataout; + wire_n0ii00O_dataout <= n0il1lO WHEN niOO0ii1l = '1' ELSE wire_n0ii0Ol_dataout; + wire_n0ii010i_dataout <= wire_niO101ii_dataout WHEN niOlli00i = '1' ELSE n0i0Oiii; + wire_n0ii010l_dataout <= wire_niO101il_dataout WHEN niOlli00i = '1' ELSE n0i0Oiil; + wire_n0ii010O_dataout <= wire_niO101iO_dataout WHEN niOlli00i = '1' ELSE n0i0OiiO; + wire_n0ii011i_dataout <= wire_niO1010i_dataout WHEN niOlli00i = '1' ELSE n0i0Oi0i; + wire_n0ii011l_dataout <= wire_niO1010l_dataout WHEN niOlli00i = '1' ELSE n0i0Oi0l; + wire_n0ii011O_dataout <= wire_niO1010O_dataout WHEN niOlli00i = '1' ELSE n0i0Oi0O; + wire_n0ii01i_dataout <= wire_n0ii0iO_dataout AND NOT(niOO0ii0i); + wire_n0ii01ii_dataout <= wire_niO101li_dataout WHEN niOlli00i = '1' ELSE n0i0Oili; + wire_n0ii01il_dataout <= wire_niO101ll_dataout WHEN niOlli00i = '1' ELSE n0i0Oill; + wire_n0ii01iO_dataout <= niOlli0lO WHEN niOlli00i = '1' ELSE n0i0OilO; + wire_n0ii01l_dataout <= wire_n0ii0li_dataout AND NOT(niOO0ii0i); + wire_n0ii01li_dataout <= wire_n0ii01Ol_dataout OR niOlli00i; + wire_n0ii01ll_dataout <= wire_n0ii01OO_dataout AND NOT(niOlli00i); + wire_n0ii01lO_dataout <= wire_n0ii001i_dataout OR niOlli00i; + wire_n0ii01O_dataout <= wire_n0ii0ll_dataout AND NOT(niOO0ii0i); + wire_n0ii01Oi_dataout <= wire_n0ii001l_dataout OR niOlli00i; + wire_n0ii01Ol_dataout <= wire_n0ii001O_dataout WHEN wire_w_lg_niOlli1iO14601w(0) = '1' ELSE n0i0OiOi; + wire_n0ii01OO_dataout <= wire_n0ii000i_dataout WHEN wire_w_lg_niOlli1iO14601w(0) = '1' ELSE n0i0OiOl; + wire_n0ii0ii_dataout <= n0il1Oi WHEN niOO0ii1l = '1' ELSE wire_n0ii0OO_dataout; + wire_n0ii0il_dataout <= n0il1Ol WHEN niOO0ii1l = '1' ELSE wire_n0iii1i_dataout; + wire_n0ii0iO_dataout <= n0il1OO WHEN niOO0ii1l = '1' ELSE wire_n0iii1l_dataout; + wire_n0ii0l0i_dataout <= wire_n0ii0lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii0l0l_dataout <= wire_n0ii0liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii0l0O_dataout <= wire_n0ii0lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii0li_dataout <= n0il01i WHEN niOO0ii1l = '1' ELSE wire_n0iii1O_dataout; + wire_n0ii0lii_dataout <= wire_n0ii0lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii0lil_dataout <= wire_n0ii0llO_dataout AND NOT(niOlli00l); + wire_n0ii0liO_dataout <= wire_n0ii0lOi_dataout AND NOT(niOlli00l); + wire_n0ii0ll_dataout <= n0il01l WHEN niOO0ii1l = '1' ELSE wire_n0iii0i_dataout; + wire_n0ii0lli_dataout <= wire_n0ii0lOl_dataout AND NOT(niOlli00l); + wire_n0ii0lll_dataout <= wire_n0ii0lOO_dataout AND NOT(niOlli00l); + wire_n0ii0llO_dataout <= wire_n0ii0O1i_o(0) WHEN wire_niO01ill_w_lg_n0ii0l1l14557w(0) = '1' ELSE n0i0Ol1l; + wire_n0ii0lO_dataout <= wire_n0iii0l_dataout AND NOT(niOO0ii1O); + wire_n0ii0lOi_dataout <= wire_n0ii0O1i_o(1) WHEN wire_niO01ill_w_lg_n0ii0l1l14557w(0) = '1' ELSE n0ii0iOO; + wire_n0ii0lOl_dataout <= wire_n0ii0O1i_o(2) WHEN wire_niO01ill_w_lg_n0ii0l1l14557w(0) = '1' ELSE n0ii0l1i; + wire_n0ii0lOO_dataout <= wire_n0ii0O1i_o(3) OR NOT(wire_niO01ill_w_lg_n0ii0l1l14557w(0)); + wire_n0ii0Oi_dataout <= wire_n0iii0O_dataout AND NOT(niOO0ii1O); + wire_n0ii0Ol_dataout <= wire_n0iiiii_dataout AND NOT(niOO0ii1O); + wire_n0ii0OO_dataout <= wire_n0iiiil_dataout AND NOT(niOO0ii1O); + wire_n0ii0OOi_dataout <= (niOllii1O AND n0ii0O0i) AND NOT(wire_niO01lOO_dataout); + wire_n0ii0OOl_dataout <= (niOllii1O AND n0ii0O0l) AND NOT(wire_niO01lOO_dataout); + wire_n0ii0OOO_dataout <= (wire_w_lg_w_lg_w_lg_niOllii1i14528w14529w14530w(0) OR (wire_w_lg_niOllii1O14531w(0) AND (wire_w_lg_niOllii1i14532w(0) AND (n0ii0Oil AND niOlli0ii)))) AND NOT(wire_niO01lOO_dataout); + wire_n0ii10i_dataout <= wire_n0ii1lO_dataout AND NOT(niOO0ii0l); + wire_n0ii10l_dataout <= wire_n0ii1Oi_dataout AND NOT(niOO0ii0l); + wire_n0ii10O_dataout <= wire_n0ii1Ol_dataout AND NOT(niOO0ii0l); + wire_n0ii10Ol_dataout <= wire_n0ii10OO_dataout AND NOT(niOlli00i); + wire_n0ii10OO_dataout <= wire_n0ii1i1i_dataout OR (wire_w_lg_niOlli0lO14650w(0) AND wire_w_lg_w_lg_niOlli0ll14639w14651w(0)); + wire_n0ii110i_dataout <= wire_n0ii011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii110l_dataout <= wire_n0ii011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii110O_dataout <= wire_n0ii010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii111i_dataout <= wire_n0ii1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii111l_dataout <= wire_n0ii1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii111O_dataout <= wire_n0ii011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii11i_dataout <= n0il0li WHEN niOO0iiii = '1' ELSE wire_n0ii1iO_dataout; + wire_n0ii11ii_dataout <= wire_n0ii010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii11il_dataout <= wire_n0ii010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii11iO_dataout <= wire_n0ii01ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii11l_dataout <= n0il0ll WHEN niOO0iiii = '1' ELSE wire_n0ii1li_dataout; + wire_n0ii11li_dataout <= wire_n0ii01il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii11ll_dataout <= wire_n0ii01iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ii11lO_dataout <= wire_n0ii01li_dataout OR wire_niO01lOO_dataout; + wire_n0ii11O_dataout <= wire_n0ii1ll_dataout AND NOT(niOO0ii0l); + wire_n0ii11Oi_dataout <= wire_n0ii01ll_dataout OR wire_niO01lOO_dataout; + wire_n0ii11Ol_dataout <= wire_n0ii01lO_dataout OR wire_niO01lOO_dataout; + wire_n0ii11OO_dataout <= wire_n0ii01Oi_dataout OR wire_niO01lOO_dataout; + wire_n0ii1i1i_dataout <= wire_n0ii1i1l_dataout OR (wire_w_lg_niOlli0ll14639w(0) AND (wire_w_lg_w_lg_niOlli1il14641w14642w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n0i0Ol1i14644w14646w14647w(0))); + wire_n0ii1i1l_dataout <= wire_n0ii1i1O_dataout OR (wire_w_lg_niOlli0ll14639w(0) AND niOlli1ii); + wire_n0ii1i1O_dataout <= n0i0O1iO OR (wire_n0ii1ili_o AND (((niOlli01i XOR n0i0O1ll) OR (niOlli1Oi XOR n0i0O1li)) OR (NOT (n0i0O1ll XOR n0i0O1li)))); + wire_n0ii1ii_dataout <= wire_n0ii1OO_dataout OR niOO0ii0l; + wire_n0ii1il_dataout <= wire_n0ii01i_dataout OR niOO0ii0l; + wire_n0ii1iO_dataout <= wire_n0ii01l_dataout OR niOO0ii0l; + wire_n0ii1l0i_dataout <= niOlli01i WHEN wire_n0ii1l0O_o = '1' ELSE n0i0O1ll; + wire_n0ii1l0l_dataout <= (wire_niO1011l_dataout AND (niOlli1OO OR niOlli01O)) WHEN wire_n0ii1l0O_o = '1' ELSE n0i0O1lO; + wire_n0ii1l1O_dataout <= niOlli1Oi WHEN wire_n0ii1l0O_o = '1' ELSE n0i0O1li; + wire_n0ii1li_dataout <= wire_n0ii01O_dataout OR niOO0ii0l; + wire_n0ii1lii_dataout <= wire_niO101il_dataout WHEN niOlli10O = '1' ELSE n0i0O10l; + wire_n0ii1lil_dataout <= wire_niO1010i_dataout WHEN niOlli10O = '1' ELSE n0i0O1Oi; + wire_n0ii1liO_dataout <= wire_niO1010l_dataout WHEN niOlli10O = '1' ELSE n0i0O1Ol; + wire_n0ii1ll_dataout <= wire_n0ii00i_dataout OR niOO0ii0i; + wire_n0ii1lli_dataout <= wire_niO1010O_dataout WHEN niOlli10O = '1' ELSE n0i0O1OO; + wire_n0ii1lll_dataout <= wire_niO101ii_dataout WHEN niOlli10O = '1' ELSE n0i0O01i; + wire_n0ii1llO_dataout <= wire_niO101ll_dataout WHEN niOlli1ii = '1' ELSE n0i0O10O; + wire_n0ii1lO_dataout <= wire_n0ii00l_dataout OR niOO0ii0i; + wire_n0ii1lOi_dataout <= wire_niO101li_dataout WHEN niOlli1ii = '1' ELSE n0i00O0l; + wire_n0ii1lOl_dataout <= wire_niO1010l_dataout WHEN niOlli1ii = '1' ELSE n0i0O0li; + wire_n0ii1lOO_dataout <= wire_niO1010O_dataout WHEN niOlli1ii = '1' ELSE n0i0O0ll; + wire_n0ii1O0i_dataout <= wire_niO1010O_dataout WHEN niOlli1il = '1' ELSE n0i0O00i; + wire_n0ii1O0l_dataout <= wire_niO101ii_dataout WHEN niOlli1il = '1' ELSE n0i0O00l; + wire_n0ii1O0O_dataout <= wire_niO101il_dataout WHEN niOlli1il = '1' ELSE n0i0O00O; + wire_n0ii1O1i_dataout <= n0i0O0lO AND NOT(niOlli1ii); + wire_n0ii1O1l_dataout <= wire_niO1010i_dataout WHEN niOlli1il = '1' ELSE n0i0O01l; + wire_n0ii1O1O_dataout <= wire_niO1010l_dataout WHEN niOlli1il = '1' ELSE n0i0O01O; + wire_n0ii1Oi_dataout <= wire_n0ii00O_dataout OR niOO0ii0i; + wire_n0ii1Oii_dataout <= wire_niO101iO_dataout WHEN niOlli1il = '1' ELSE n0i0O0ii; + wire_n0ii1Oil_dataout <= wire_niO101li_dataout WHEN niOlli1il = '1' ELSE n0i0O0il; + wire_n0ii1OiO_dataout <= wire_niO101ll_dataout WHEN niOlli1il = '1' ELSE n0i0O0iO; + wire_n0ii1Ol_dataout <= wire_n0ii0ii_dataout OR niOO0ii0i; + wire_n0ii1Oli_dataout <= wire_niO1010i_dataout WHEN niOlli1ll = '1' ELSE n0i0O0Oi; + wire_n0ii1Oll_dataout <= wire_niO1010l_dataout WHEN niOlli1ll = '1' ELSE n0i0O0Ol; + wire_n0ii1OlO_dataout <= wire_niO1010O_dataout WHEN niOlli1ll = '1' ELSE n0i0O0OO; + wire_n0ii1OO_dataout <= wire_n0ii0il_dataout AND NOT(niOO0ii0i); + wire_n0ii1OOi_dataout <= wire_niO101ii_dataout WHEN niOlli1ll = '1' ELSE n0i0Oi1i; + wire_n0ii1OOl_dataout <= wire_niO101il_dataout WHEN niOlli1ll = '1' ELSE n0i0Oi1l; + wire_n0ii1OOO_dataout <= niOlli0lO WHEN niOlli1ll = '1' ELSE n0i0Oi1O; + wire_n0iii0i_dataout <= wire_n0iiilO_dataout AND NOT(niOO0ii1O); + wire_n0iii0l_dataout <= n0il00i WHEN niOO0i0OO = '1' ELSE wire_n0iiiOi_dataout; + wire_n0iii0O_dataout <= n0il00l WHEN niOO0i0OO = '1' ELSE wire_n0iiiOl_dataout; + wire_n0iii10i_dataout <= niOllii1i AND NOT(wire_niO01lOO_dataout); + wire_n0iii10l_dataout <= n0ii0Oli AND NOT(wire_niO01lOO_dataout); + wire_n0iii10O_dataout <= n0ii0Oll AND NOT(wire_niO01lOO_dataout); + wire_n0iii11i_dataout <= niOlli0li AND NOT(wire_niO01lOO_dataout); + wire_n0iii11l_dataout <= (niOllii1i AND n0ii0Oll) AND NOT(wire_niO01lOO_dataout); + wire_n0iii11O_dataout <= n0ii0Oil AND NOT(wire_niO01lOO_dataout); + wire_n0iii1i_dataout <= wire_n0iiiiO_dataout AND NOT(niOO0ii1O); + wire_n0iii1ii_dataout <= niOllii1O AND NOT(wire_niO01lOO_dataout); + wire_n0iii1l_dataout <= wire_n0iiili_dataout AND NOT(niOO0ii1O); + wire_n0iii1O_dataout <= wire_n0iiill_dataout AND NOT(niOO0ii1O); + wire_n0iiii0i_dataout <= wire_n0iiiill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiii0l_dataout <= wire_n0iiiilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiii0O_dataout <= wire_n0iiiiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiii1i_dataout <= wire_n0iiiiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiii1l_dataout <= wire_n0iiiiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiii1O_dataout <= wire_n0iiiili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiiii_dataout <= n0il00O WHEN niOO0i0OO = '1' ELSE wire_n0iiiOO_dataout; + wire_n0iiiiii_dataout <= wire_n0iiiiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiiiil_dataout <= wire_n0iiiiOO_dataout AND NOT(niOlliiii); + wire_n0iiiiiO_dataout <= wire_n0iiil1i_dataout AND NOT(niOlliiii); + wire_n0iiiil_dataout <= n0il0ii WHEN niOO0i0OO = '1' ELSE wire_n0iil1i_dataout; + wire_n0iiiili_dataout <= wire_n0iiil1l_dataout AND NOT(niOlliiii); + wire_n0iiiill_dataout <= wire_n0iiil1O_dataout AND NOT(niOlliiii); + wire_n0iiiilO_dataout <= wire_n0iiil0i_dataout AND NOT(niOlliiii); + wire_n0iiiiO_dataout <= n0il0il WHEN niOO0i0OO = '1' ELSE wire_n0iil1l_dataout; + wire_n0iiiiOi_dataout <= wire_n0iiil0l_dataout AND NOT(niOlliiii); + wire_n0iiiiOl_dataout <= wire_n0iiil0O_dataout AND NOT(niOlliiii); + wire_n0iiiiOO_dataout <= wire_n0iiilii_o(0) WHEN niOllii0l = '1' ELSE n0ii0OlO; + wire_n0iiil0i_dataout <= wire_n0iiilii_o(4) WHEN niOllii0l = '1' ELSE n0iii0lO; + wire_n0iiil0l_dataout <= wire_n0iiilii_o(5) WHEN niOllii0l = '1' ELSE n0iii0Oi; + wire_n0iiil0O_dataout <= wire_n0iiilii_o(6) WHEN niOllii0l = '1' ELSE n0iii0Ol; + wire_n0iiil1i_dataout <= wire_n0iiilii_o(1) WHEN niOllii0l = '1' ELSE n0iii0iO; + wire_n0iiil1l_dataout <= wire_n0iiilii_o(2) WHEN niOllii0l = '1' ELSE n0iii0li; + wire_n0iiil1O_dataout <= wire_n0iiilii_o(3) WHEN niOllii0l = '1' ELSE n0iii0ll; + wire_n0iiili_dataout <= n0il0iO WHEN niOO0i0OO = '1' ELSE wire_n0iil1O_dataout; + wire_n0iiill_dataout <= n0il0li WHEN niOO0i0OO = '1' ELSE wire_n0iil0i_dataout; + wire_n0iiillO_dataout <= n0iil10O AND (((NOT (n1101l1i XOR n0iil11O)) AND (NOT (n1101l1i XOR n0iil10i))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0iil10l))); + wire_n0iiillO_w_lg_w_lg_w_lg_dataout14412w14418w14419w(0) <= wire_n0iiillO_w_lg_w_lg_dataout14412w14418w(0) AND n0iil10O; + wire_n0iiillO_w_lg_w_lg_dataout14412w14418w(0) <= wire_n0iiillO_w_lg_dataout14412w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n0iil11i14413w14415w14417w(0); + wire_n0iiillO_w_lg_dataout14425w(0) <= wire_n0iiillO_dataout AND wire_niO01ill_w14424w(0); + wire_n0iiillO_w_lg_dataout14412w(0) <= NOT wire_n0iiillO_dataout; + wire_n0iiilO_dataout <= n0il0ll WHEN niOO0i0OO = '1' ELSE wire_n0iil0l_dataout; + wire_n0iiilOi_dataout <= n0iil1Oi AND (n0iil1ii AND niOlliiil); + wire_n0iiilOO_dataout <= n0iil1Oi AND ((NOT (n0iil1iO XOR n0iil1il)) AND niOlliiil); + wire_n0iiiO1O_dataout <= n0iii0OO AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllOllO); + wire_n0iiiOi_dataout <= wire_n0iil0O_dataout AND NOT(niOO0i0Ol); + wire_n0iiiOl_dataout <= wire_n0iilii_dataout AND NOT(niOO0i0Ol); + wire_n0iiiOO_dataout <= wire_n0iilil_dataout AND NOT(niOO0i0Ol); + wire_n0iil00i_dataout <= wire_n0iiO01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil00l_dataout <= wire_n0iiO01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil00O_dataout <= wire_n0iiO00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil01i_dataout <= wire_n0iiO1iO_dataout OR wire_niO01lOO_dataout; + wire_n0iil01l_dataout <= wire_n0iiO1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil01O_dataout <= wire_n0iiO01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0i_dataout <= wire_n0iillO_dataout AND NOT(niOO0i0Ol); + wire_n0iil0ii_dataout <= wire_n0iiO00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0il_dataout <= wire_n0iiO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0iO_dataout <= wire_n0iiO0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0l_dataout <= wire_n0iilOi_dataout AND NOT(niOO0i0Ol); + wire_n0iil0li_dataout <= wire_n0iiO0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0ll_dataout <= wire_n0iiliOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0lO_dataout <= wire_n0iiliOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0O_dataout <= n0il00i OR NOT(niOO0i0Oi); + wire_n0iil0Oi_dataout <= wire_n0iiliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0Ol_dataout <= wire_n0iill1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil0OO_dataout <= wire_n0iill1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iil1i_dataout <= wire_n0iiliO_dataout AND NOT(niOO0i0Ol); + wire_n0iil1l_dataout <= wire_n0iilli_dataout AND NOT(niOO0i0Ol); + wire_n0iil1O_dataout <= wire_n0iilll_dataout AND NOT(niOO0i0Ol); + wire_n0iili0i_dataout <= wire_n0il0OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iili0l_dataout <= wire_n0il0OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iili0O_dataout <= wire_n0ili11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iili1i_dataout <= wire_n0iill1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iili1l_dataout <= wire_n0iill0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iili1O_dataout <= wire_n0iilO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iilii_dataout <= n0il00l OR NOT(niOO0i0Oi); + wire_n0iiliii_dataout <= wire_n0ili11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiliil_dataout <= wire_n0ili11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiliiO_dataout <= wire_n0ili10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iilil_dataout <= n0il00O OR NOT(niOO0i0Oi); + wire_n0iilili_dataout <= wire_n0ili0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iilill_dataout <= wire_n0iilOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iililO_dataout <= wire_n0iilO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iiliO_dataout <= n0il0ii OR NOT(niOO0i0Oi); + wire_n0iiliOi_dataout <= wire_n0iill0l_dataout AND NOT(niOlliiiO); + wire_n0iiliOl_dataout <= wire_n0iill0O_dataout AND NOT(niOlliiiO); + wire_n0iiliOO_dataout <= wire_n0iillii_dataout AND NOT(niOlliiiO); + wire_n0iill0i_dataout <= wire_n0iillll_dataout AND NOT(niOlliiiO); + wire_n0iill0l_dataout <= wire_n0iilllO_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iiiOOl; + wire_n0iill0O_dataout <= wire_n0iilllO_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iiiOOO; + wire_n0iill1i_dataout <= wire_n0iillil_dataout AND NOT(niOlliiiO); + wire_n0iill1l_dataout <= wire_n0iilliO_dataout AND NOT(niOlliiiO); + wire_n0iill1O_dataout <= wire_n0iillli_dataout AND NOT(niOlliiiO); + wire_n0iilli_dataout <= n0il0il OR NOT(niOO0i0Oi); + wire_n0iillii_dataout <= wire_n0iilllO_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil11i; + wire_n0iillil_dataout <= wire_n0iilllO_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil11l; + wire_n0iilliO_dataout <= wire_n0iilllO_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil11O; + wire_n0iilll_dataout <= n0il0iO OR NOT(niOO0i0Oi); + wire_n0iillli_dataout <= wire_n0iilllO_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil10i; + wire_n0iillll_dataout <= wire_n0iilllO_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil10l; + wire_n0iillO_dataout <= n0il0li OR NOT(niOO0i0Oi); + wire_n0iilO0O_dataout <= n0iil1Ol WHEN nlOllOllO = '1' ELSE wire_n0iilOii_dataout; + wire_n0iilO1i_dataout <= wire_n0iilO1l_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14284w(0) AND wire_w_lg_niOlliO0O14285w(0)); + wire_n0iilO1l_dataout <= n0iil10O AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlliOii14431w(0))); + wire_n0iilOi_dataout <= n0il0ll OR NOT(niOO0i0Oi); + wire_n0iilOii_dataout <= wire_n0iilOil_dataout OR niOllilOl; + wire_n0iilOil_dataout <= wire_n0iilOiO_dataout OR n0ilii1l; + wire_n0iilOiO_dataout <= wire_n0iilOli_dataout OR (wire_niO01ill_w_lg_n0ili0Ol14282w(0) AND (wire_n0iiillO_dataout AND niOllilil)); + wire_n0iilOli_dataout <= wire_n0iilOlO_dataout OR (wire_niO01ill_w_lg_n0ili0Ol14282w(0) AND (wire_n0iiillO_dataout AND niOllil1i)); + wire_n0iilOlO_dataout <= wire_n0iilOOi_dataout OR (wire_niO01ill_w_lg_n0ili0Ol14282w(0) AND wire_n0iiillO_w_lg_dataout14425w(0)); + wire_n0iilOOi_dataout <= wire_n0iilOOl_dataout OR (wire_niO01ill_w_lg_n0ili0Ol14282w(0) AND wire_n0iiillO_w_lg_w_lg_w_lg_dataout14412w14418w14419w(0)); + wire_n0iilOOl_dataout <= n0iil1OO AND nlOllOllO; + wire_n0iiO00i_dataout <= wire_n0i1001l_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiO0Oi_dataout; + wire_n0iiO00l_dataout <= wire_n0i101Ol_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiO0Ol_dataout; + wire_n0iiO00O_dataout <= wire_n0i101lO_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiO0OO_dataout; + wire_n0iiO01i_dataout <= wire_n0i100il_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiO0li_dataout; + wire_n0iiO01l_dataout <= wire_n0i1000O_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiO0ll_dataout; + wire_n0iiO01O_dataout <= wire_n0i1000i_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiO0lO_dataout; + wire_n0iiO0ii_dataout <= wire_n0i101iO_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiOi1i_dataout; + wire_n0iiO0il_dataout <= n0ilii0i WHEN niOlliO1O = '1' ELSE wire_n0iiOi1l_dataout; + wire_n0iiO0iO_dataout <= wire_n0iiOi0i_dataout AND NOT(niOlliO1i); + wire_n0iiO0li_dataout <= wire_n0iiOi0l_dataout AND NOT(niOlliO1i); + wire_n0iiO0ll_dataout <= wire_n0iiOi0O_dataout OR niOlliO1i; + wire_n0iiO0lO_dataout <= wire_n0iiOiii_dataout OR niOlliO1i; + wire_n0iiO0Oi_dataout <= wire_n0iiOiil_dataout OR niOlliO1i; + wire_n0iiO0Ol_dataout <= wire_n0iiOiiO_dataout OR niOlliO1i; + wire_n0iiO0OO_dataout <= wire_n0iiOili_dataout AND NOT(niOlliO1i); + wire_n0iiO1iO_dataout <= wire_n0iiO1li_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n0ilii1i AND n0iil1iO)) OR (n0ilii1i AND n0iil11i)); + wire_n0iiO1li_dataout <= n0iii0OO AND nlOllOllO; + wire_n0iiO1OO_dataout <= wire_n0i100li_dataout WHEN niOlliO1O = '1' ELSE wire_n0iiO0iO_dataout; + wire_n0iiOi0i_dataout <= wire_n0iiOilO_dataout AND NOT(niOllilOi); + wire_n0iiOi0l_dataout <= wire_n0iiOiOi_dataout AND NOT(niOllilOi); + wire_n0iiOi0O_dataout <= wire_n0iiOiOl_dataout AND NOT(niOllilOi); + wire_n0iiOi1i_dataout <= wire_n0iiOill_dataout OR niOlliO1i; + wire_n0iiOi1l_dataout <= wire_n0iiOi1O_dataout OR niOlliO1i; + wire_n0iiOi1O_dataout <= wire_n0iiOl0l_dataout AND NOT(niOllilOi); + wire_n0iiOiii_dataout <= wire_n0iiOiOO_dataout AND NOT(niOllilOi); + wire_n0iiOiil_dataout <= wire_n0iiOl1i_dataout AND NOT(niOllilOi); + wire_n0iiOiiO_dataout <= wire_n0iiOl1l_dataout AND NOT(niOllilOi); + wire_n0iiOili_dataout <= wire_n0iiOl1O_dataout AND NOT(niOllilOi); + wire_n0iiOill_dataout <= wire_n0iiOl0i_dataout AND NOT(niOllilOi); + wire_n0iiOilO_dataout <= wire_n0iiOl0O_dataout AND NOT(niOllilll); + wire_n0iiOiOi_dataout <= wire_n0iiOlii_dataout AND NOT(niOllilll); + wire_n0iiOiOl_dataout <= wire_n0iiOlil_dataout OR niOllilll; + wire_n0iiOiOO_dataout <= wire_n0iiOliO_dataout OR niOllilll; + wire_n0iiOl0i_dataout <= wire_n0iiOlOi_dataout AND NOT(niOllilll); + wire_n0iiOl0l_dataout <= wire_n0iiOlOl_dataout OR niOllilll; + wire_n0iiOl0O_dataout <= wire_n0iiOlOO_dataout OR niOllilli; + wire_n0iiOl1i_dataout <= wire_n0iiOlli_dataout OR niOllilll; + wire_n0iiOl1l_dataout <= wire_n0iiOlll_dataout OR niOllilll; + wire_n0iiOl1O_dataout <= wire_n0iiOllO_dataout OR niOllilll; + wire_n0iiOlii_dataout <= wire_n0iiOO1i_dataout AND NOT(niOllilli); + wire_n0iiOlil_dataout <= wire_n0iiOO1l_dataout OR niOllilli; + wire_n0iiOliO_dataout <= wire_n0iiOO1O_dataout AND NOT(niOllilli); + wire_n0iiOlli_dataout <= wire_n0iiOO0i_dataout OR niOllilli; + wire_n0iiOlll_dataout <= wire_n0iiOO0l_dataout OR niOllilli; + wire_n0iiOllO_dataout <= wire_n0iiOO0O_dataout AND NOT(niOllilli); + wire_n0iiOlOi_dataout <= wire_n0iiOOii_dataout OR niOllilli; + wire_n0iiOlOl_dataout <= wire_n0iiOOil_dataout AND NOT(niOllilli); + wire_n0iiOlOO_dataout <= wire_n0iiOOiO_dataout AND NOT(niOlliliO); + wire_n0iiOO0i_dataout <= wire_n0iiOOOi_dataout AND NOT(niOlliliO); + wire_n0iiOO0l_dataout <= wire_n0iiOOOl_dataout AND NOT(niOlliliO); + wire_n0iiOO0O_dataout <= wire_n0iiOOOO_dataout OR niOlliliO; + wire_n0iiOO1i_dataout <= wire_n0iiOOli_dataout OR niOlliliO; + wire_n0iiOO1l_dataout <= wire_n0iiOOll_dataout AND NOT(niOlliliO); + wire_n0iiOO1O_dataout <= wire_n0iiOOlO_dataout OR niOlliliO; + wire_n0iiOOii_dataout <= wire_n0il111i_dataout AND NOT(niOlliliO); + wire_n0iiOOil_dataout <= wire_n0il111l_dataout AND NOT(niOlliliO); + wire_n0iiOOiO_dataout <= wire_n0il1lll_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il111O_dataout; + wire_n0iiOOli_dataout <= wire_n0il1llO_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il110i_dataout; + wire_n0iiOOll_dataout <= wire_n0il1lOi_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il110l_dataout; + wire_n0iiOOlO_dataout <= wire_n0il1lOl_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il110O_dataout; + wire_n0iiOOOi_dataout <= wire_n0il1lOO_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il11ii_dataout; + wire_n0iiOOOl_dataout <= wire_n0il1O1i_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il11il_dataout; + wire_n0iiOOOO_dataout <= wire_n0il1O1l_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il11iO_dataout; + wire_n0il000i_dataout <= wire_n0il00Oi_dataout AND NOT(niOllil0i); + wire_n0il000l_dataout <= wire_n0il00Ol_dataout OR niOllil0i; + wire_n0il000O_dataout <= wire_n0il00OO_dataout AND NOT(niOllil0i); + wire_n0il001i_dataout <= wire_n0il00li_dataout OR niOllil1O; + wire_n0il001l_dataout <= wire_n0il00ll_dataout AND NOT(niOllil0i); + wire_n0il001O_dataout <= wire_n0il00lO_dataout OR niOllil0i; + wire_n0il00ii_dataout <= wire_n0il0i1i_dataout AND NOT(niOllil0i); + wire_n0il00il_dataout <= wire_n0il0i1l_dataout OR niOllil0i; + wire_n0il00iO_dataout <= wire_n0il0i1O_dataout AND NOT(niOllil0i); + wire_n0il00li_dataout <= wire_n0il0i0i_dataout AND NOT(niOllil0i); + wire_n0il00ll_dataout <= n0ii0OlO WHEN niOllil0l = '1' ELSE wire_n0il0i0l_dataout; + wire_n0il00lO_dataout <= n0iii0iO WHEN niOllil0l = '1' ELSE wire_n0il0i0O_dataout; + wire_n0il00Oi_dataout <= n0iii0li WHEN niOllil0l = '1' ELSE wire_n0il0iii_dataout; + wire_n0il00Ol_dataout <= n0iii0ll WHEN niOllil0l = '1' ELSE wire_n0il0iil_dataout; + wire_n0il00OO_dataout <= n0iii0lO WHEN niOllil0l = '1' ELSE wire_n0il0iiO_dataout; + wire_n0il010i_dataout <= wire_n0il01Oi_dataout OR niOllil1l; + wire_n0il010l_dataout <= wire_n0il01Ol_dataout AND NOT(niOllil1l); + wire_n0il010O_dataout <= wire_n0il01OO_dataout OR niOllil1l; + wire_n0il011i_dataout <= wire_n0il01li_dataout OR niOllil1l; + wire_n0il011l_dataout <= wire_n0il01ll_dataout AND NOT(niOllil1l); + wire_n0il011O_dataout <= wire_n0il01lO_dataout OR niOllil1l; + wire_n0il01ii_dataout <= wire_n0il001i_dataout AND NOT(niOllil1l); + wire_n0il01il_dataout <= wire_n0il001l_dataout AND NOT(niOllil1O); + wire_n0il01iO_dataout <= wire_n0il001O_dataout AND NOT(niOllil1O); + wire_n0il01li_dataout <= wire_n0il000i_dataout OR niOllil1O; + wire_n0il01ll_dataout <= wire_n0il000l_dataout OR niOllil1O; + wire_n0il01lO_dataout <= wire_n0il000O_dataout OR niOllil1O; + wire_n0il01Oi_dataout <= wire_n0il00ii_dataout OR niOllil1O; + wire_n0il01Ol_dataout <= wire_n0il00il_dataout AND NOT(niOllil1O); + wire_n0il01OO_dataout <= wire_n0il00iO_dataout OR niOllil1O; + wire_n0il0i0i_dataout <= wire_n0il0iOi_dataout AND NOT(niOllil0l); + wire_n0il0i0l_dataout <= n0iiiO0l WHEN niOllil0O = '1' ELSE wire_n0il0iOl_dataout; + wire_n0il0i0O_dataout <= n0iiiO0O WHEN niOllil0O = '1' ELSE wire_n0il0iOO_dataout; + wire_n0il0i1i_dataout <= n0iii0Oi WHEN niOllil0l = '1' ELSE wire_n0il0ili_dataout; + wire_n0il0i1l_dataout <= n0iii0Ol WHEN niOllil0l = '1' ELSE wire_n0il0ill_dataout; + wire_n0il0i1O_dataout <= n0i0101l WHEN niOllil0l = '1' ELSE wire_n0il0ilO_dataout; + wire_n0il0iii_dataout <= n0iiiOii WHEN niOllil0O = '1' ELSE wire_n0il0l1i_dataout; + wire_n0il0iil_dataout <= n0iiiOil WHEN niOllil0O = '1' ELSE wire_n0il0l1l_dataout; + wire_n0il0iiO_dataout <= n0iiiOiO WHEN niOllil0O = '1' ELSE wire_n0il0l1O_dataout; + wire_n0il0ili_dataout <= n0iiiOli WHEN niOllil0O = '1' ELSE wire_n0il0l0i_dataout; + wire_n0il0ill_dataout <= n0iiiOll WHEN niOllil0O = '1' ELSE wire_n0il0l0l_dataout; + wire_n0il0ilO_dataout <= n0iiiOlO WHEN niOllil0O = '1' ELSE wire_n0il0l0O_dataout; + wire_n0il0iOi_dataout <= wire_n0il0lii_dataout AND NOT(niOllil0O); + wire_n0il0iOl_dataout <= wire_n0il0lil_dataout AND NOT(niOllilii); + wire_n0il0iOO_dataout <= wire_n0il0liO_dataout AND NOT(niOllilii); + wire_n0il0l0i_dataout <= wire_n0il0lOi_dataout OR niOllilii; + wire_n0il0l0l_dataout <= wire_n0il0lOl_dataout AND NOT(niOllilii); + wire_n0il0l0O_dataout <= wire_n0il0lOO_dataout OR niOllilii; + wire_n0il0l1i_dataout <= wire_n0il0lli_dataout OR niOllilii; + wire_n0il0l1l_dataout <= wire_n0il0lll_dataout OR niOllilii; + wire_n0il0l1O_dataout <= wire_n0il0llO_dataout OR niOllilii; + wire_n0il0lii_dataout <= wire_n0il0O1i_dataout OR niOllilii; + wire_n0il0lil_dataout <= n0iiiO0l AND NOT(niOllilil); + wire_n0il0liO_dataout <= n0iiiO0O AND NOT(niOllilil); + wire_n0il0lli_dataout <= n0iiiOii OR niOllilil; + wire_n0il0lll_dataout <= n0iiiOil OR niOllilil; + wire_n0il0llO_dataout <= n0iiiOiO OR niOllilil; + wire_n0il0lOi_dataout <= n0iiiOli OR niOllilil; + wire_n0il0lOl_dataout <= n0iiiOll OR niOllilil; + wire_n0il0lOO_dataout <= n0iiiOlO OR niOllilil; + wire_n0il0O1i_dataout <= n0iiiOOi OR niOllilil; + wire_n0il0OOl_dataout <= wire_n0ili10l_dataout AND NOT(niOlliO0l); + wire_n0il0OOO_dataout <= wire_n0ili10O_dataout AND NOT(niOlliO0l); + wire_n0il100i_dataout <= wire_n0il10Oi_dataout AND NOT(niOlliiOi); + wire_n0il100l_dataout <= wire_n0il10Ol_dataout OR niOlliiOi; + wire_n0il100O_dataout <= wire_n0il10OO_dataout AND NOT(niOlliilO); + wire_n0il101i_dataout <= wire_n0il10li_dataout OR niOlliiOi; + wire_n0il101l_dataout <= wire_n0il10ll_dataout OR niOlliiOi; + wire_n0il101O_dataout <= wire_n0il10lO_dataout OR niOlliiOi; + wire_n0il10ii_dataout <= wire_n0il1i1i_dataout AND NOT(niOlliilO); + wire_n0il10il_dataout <= wire_n0il1i1l_dataout AND NOT(niOlliilO); + wire_n0il10iO_dataout <= wire_n0il1i1O_dataout AND NOT(niOlliilO); + wire_n0il10li_dataout <= wire_n0il1i0i_dataout AND NOT(niOlliilO); + wire_n0il10ll_dataout <= wire_n0il1i0l_dataout AND NOT(niOlliilO); + wire_n0il10lO_dataout <= wire_n0il1i0O_dataout AND NOT(niOlliilO); + wire_n0il10Oi_dataout <= wire_n0il1iii_dataout AND NOT(niOlliilO); + wire_n0il10Ol_dataout <= wire_n0il1iil_dataout AND NOT(niOlliilO); + wire_n0il10OO_dataout <= n0ii0OlO WHEN niOlliili = '1' ELSE wire_n0il1iiO_dataout; + wire_n0il110i_dataout <= wire_n0il11Oi_dataout AND NOT(niOlliiOl); + wire_n0il110l_dataout <= wire_n0il11Ol_dataout OR niOlliiOl; + wire_n0il110O_dataout <= wire_n0il11OO_dataout OR niOlliiOl; + wire_n0il111i_dataout <= wire_n0il1O1O_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il11li_dataout; + wire_n0il111l_dataout <= wire_n0il1O0i_dataout WHEN wire_n0iiillO_dataout = '1' ELSE wire_n0il11ll_dataout; + wire_n0il111O_dataout <= wire_n0il11lO_dataout AND NOT(niOlliiOl); + wire_n0il11ii_dataout <= wire_n0il101i_dataout OR niOlliiOl; + wire_n0il11il_dataout <= wire_n0il101l_dataout OR niOlliiOl; + wire_n0il11iO_dataout <= wire_n0il101O_dataout AND NOT(niOlliiOl); + wire_n0il11li_dataout <= wire_n0il100i_dataout OR niOlliiOl; + wire_n0il11ll_dataout <= wire_n0il100l_dataout OR niOlliiOl; + wire_n0il11lO_dataout <= wire_n0il100O_dataout AND NOT(niOlliiOi); + wire_n0il11Oi_dataout <= wire_n0il10ii_dataout AND NOT(niOlliiOi); + wire_n0il11Ol_dataout <= wire_n0il10il_dataout OR niOlliiOi; + wire_n0il11OO_dataout <= wire_n0il10iO_dataout OR niOlliiOi; + wire_n0il1i0i_dataout <= n0iii0lO WHEN niOlliili = '1' ELSE wire_n0il1iOi_dataout; + wire_n0il1i0l_dataout <= n0iii0Oi WHEN niOlliili = '1' ELSE wire_n0il1iOl_dataout; + wire_n0il1i0O_dataout <= n0iii0Ol WHEN niOlliili = '1' ELSE wire_n0il1iOO_dataout; + wire_n0il1i1i_dataout <= n0iii0iO WHEN niOlliili = '1' ELSE wire_n0il1ili_dataout; + wire_n0il1i1l_dataout <= n0iii0li WHEN niOlliili = '1' ELSE wire_n0il1ill_dataout; + wire_n0il1i1O_dataout <= n0iii0ll WHEN niOlliili = '1' ELSE wire_n0il1ilO_dataout; + wire_n0il1iii_dataout <= n0i0101l WHEN niOlliili = '1' ELSE wire_n0il1l1i_dataout; + wire_n0il1iil_dataout <= wire_n0il1l1l_dataout AND NOT(niOlliili); + wire_n0il1iiO_dataout <= n0iiiO0l WHEN niOlliill = '1' ELSE wire_n0i100li_dataout; + wire_n0il1ili_dataout <= n0iiiO0O WHEN niOlliill = '1' ELSE wire_n0i100il_dataout; + wire_n0il1ill_dataout <= n0iiiOii WHEN niOlliill = '1' ELSE wire_n0i1000O_dataout; + wire_n0il1ilO_dataout <= n0iiiOil WHEN niOlliill = '1' ELSE wire_n0i1000i_dataout; + wire_n0il1iOi_dataout <= n0iiiOiO WHEN niOlliill = '1' ELSE wire_n0i1001l_dataout; + wire_n0il1iOl_dataout <= n0iiiOli WHEN niOlliill = '1' ELSE wire_n0i101Ol_dataout; + wire_n0il1iOO_dataout <= n0iiiOll WHEN niOlliill = '1' ELSE wire_n0i101lO_dataout; + wire_n0il1l1i_dataout <= n0iiiOlO WHEN niOlliill = '1' ELSE wire_n0i101iO_dataout; + wire_n0il1l1l_dataout <= n0ilii0i AND NOT(niOlliill); + wire_n0il1lll_dataout <= wire_n0il1O0l_dataout AND NOT(niOlliiOO); + wire_n0il1llO_dataout <= wire_n0il1O0O_dataout AND NOT(niOlliiOO); + wire_n0il1lOi_dataout <= wire_n0il1Oii_dataout OR niOlliiOO; + wire_n0il1lOl_dataout <= wire_n0il1Oil_dataout OR niOlliiOO; + wire_n0il1lOO_dataout <= wire_n0il1OiO_dataout OR niOlliiOO; + wire_n0il1O0i_dataout <= wire_n0il1OOi_dataout OR niOlliiOO; + wire_n0il1O0l_dataout <= wire_n0il1OOl_dataout AND NOT(niOllil1i); + wire_n0il1O0O_dataout <= wire_n0il1OOO_dataout AND NOT(niOllil1i); + wire_n0il1O1i_dataout <= wire_n0il1Oli_dataout OR niOlliiOO; + wire_n0il1O1l_dataout <= wire_n0il1Oll_dataout AND NOT(niOlliiOO); + wire_n0il1O1O_dataout <= wire_n0il1OlO_dataout OR niOlliiOO; + wire_n0il1Oii_dataout <= wire_n0il011i_dataout OR niOllil1i; + wire_n0il1Oil_dataout <= wire_n0il011l_dataout OR niOllil1i; + wire_n0il1OiO_dataout <= wire_n0il011O_dataout OR niOllil1i; + wire_n0il1Oli_dataout <= wire_n0il010i_dataout OR niOllil1i; + wire_n0il1Oll_dataout <= wire_n0il010l_dataout AND NOT(niOllil1i); + wire_n0il1OlO_dataout <= wire_n0il010O_dataout OR niOllil1i; + wire_n0il1OOi_dataout <= wire_n0il01ii_dataout OR niOllil1i; + wire_n0il1OOl_dataout <= wire_n0il01il_dataout OR niOllil1l; + wire_n0il1OOO_dataout <= wire_n0il01iO_dataout AND NOT(niOllil1l); + wire_n0ili01i_dataout <= wire_n0ili01l_o(5) WHEN niOlliO0i = '1' ELSE n0iil1lO; + wire_n0ili0ii_dataout <= wire_n0ili0il_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14279w(0) AND wire_w_lg_niOlliOil14280w(0)); + wire_n0ili0il_dataout <= n0iil1Oi AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlliOiO14288w(0))); + wire_n0ili10i_dataout <= wire_n0ili1li_dataout AND NOT(niOlliO0l); + wire_n0ili10l_dataout <= wire_n0ili1ll_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil1ii; + wire_n0ili10O_dataout <= wire_n0ili1lO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil1il; + wire_n0ili11i_dataout <= wire_n0ili1ii_dataout AND NOT(niOlliO0l); + wire_n0ili11l_dataout <= wire_n0ili1il_dataout AND NOT(niOlliO0l); + wire_n0ili11O_dataout <= wire_n0ili1iO_dataout AND NOT(niOlliO0l); + wire_n0ili1ii_dataout <= wire_n0ili1Oi_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil1iO; + wire_n0ili1il_dataout <= wire_n0ili1Ol_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil1li; + wire_n0ili1iO_dataout <= wire_n0ili1OO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil1ll; + wire_n0ili1li_dataout <= wire_n0ili01i_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0iil1lO; + wire_n0ili1ll_dataout <= wire_n0ili01l_o(0) WHEN niOlliO0i = '1' ELSE n0iil1ii; + wire_n0ili1lO_dataout <= wire_n0ili01l_o(1) WHEN niOlliO0i = '1' ELSE n0iil1il; + wire_n0ili1Oi_dataout <= wire_n0ili01l_o(2) WHEN niOlliO0i = '1' ELSE n0iil1iO; + wire_n0ili1Ol_dataout <= wire_n0ili01l_o(3) WHEN niOlliO0i = '1' ELSE n0iil1li; + wire_n0ili1OO_dataout <= wire_n0ili01l_o(4) WHEN niOlliO0i = '1' ELSE n0iil1ll; + wire_n0iliiOi_dataout <= wire_n0iliOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iliiOl_dataout <= wire_n0iliOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iliiOO_dataout <= wire_n0iliOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilil0i_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14284w(0) AND wire_w_lg_niOlliO0O14285w(0)) AND wire_niO01ill_w_lg_n0ili0Ol14282w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0ilil0l_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w14279w(0) AND wire_w_lg_niOlliOil14280w(0)) AND wire_niO01ill_w_lg_n0ili0Ol14282w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0ilil0O_dataout <= wire_n0iliOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilil1i_dataout <= wire_n0iliO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilil1l_dataout <= n0ilii1i AND NOT(wire_niO01lOO_dataout); + wire_n0ilil1O_dataout <= nlOllOllO AND NOT(wire_niO01lOO_dataout); + wire_n0ililii_dataout <= wire_n0iliOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ililil_dataout <= wire_n0iliOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ililiO_dataout <= wire_n0iliOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ililli_dataout <= wire_n0ill11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ililll_dataout <= wire_n0ill11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilillO_dataout <= wire_n0ill11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ililOi_dataout <= wire_n0ill10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ililOl_dataout <= wire_n0ill10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iliO0O_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0ili0Ol; + wire_n0iliOii_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0iilOll; + wire_n0iliOil_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0ili0lO; + wire_n0iliOiO_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0ili0Oi; + wire_n0iliOli_dataout <= wire_n1lllOil_dataout WHEN n1lO0lOi = '1' ELSE wire_n0iliOll_dataout; + wire_n0iliOll_dataout <= wire_n0iliOlO_dataout AND NOT(niOlliOll); + wire_n0iliOlO_dataout <= n1l001OO AND NOT(niOlliOli); + wire_n0iliOOi_dataout <= wire_n1llOiiO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill10O_dataout; + wire_n0iliOOl_dataout <= wire_n1llOili_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill1ii_dataout; + wire_n0iliOOO_dataout <= wire_n1llOill_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill1il_dataout; + wire_n0ill00i_dataout <= n1l001lO AND NOT(niOlliOli); + wire_n0ill00l_dataout <= n1l001Oi AND NOT(niOlliOli); + wire_n0ill00O_dataout <= n1l001Ol AND NOT(niOlliOli); + wire_n0ill01i_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOlliOli = '1' ELSE n1l001iO; + wire_n0ill01l_dataout <= n1l001li AND NOT(niOlliOli); + wire_n0ill01O_dataout <= n1l001ll AND NOT(niOlliOli); + wire_n0ill0iO_dataout <= k_cnt(57) AND NOT(wire_n0ill0OO_o); + wire_n0ill0li_dataout <= k_cnt(58) AND NOT(wire_n0ill0OO_o); + wire_n0ill0ll_dataout <= k_cnt(59) OR wire_n0ill0OO_o; + wire_n0ill0lO_dataout <= k_cnt(60) AND NOT(wire_n0ill0OO_o); + wire_n0ill0Oi_dataout <= k_cnt(61) AND NOT(wire_n0ill0OO_o); + wire_n0ill0Ol_dataout <= k_cnt(62) AND NOT(wire_n0ill0OO_o); + wire_n0ill10i_dataout <= wire_n1llOiOO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill1lO_dataout; + wire_n0ill10l_dataout <= wire_n1llOl1i_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill1Oi_dataout; + wire_n0ill10O_dataout <= wire_nlOO10OOi_dataout WHEN niOlliOll = '1' ELSE wire_n0ill1Ol_dataout; + wire_n0ill11i_dataout <= wire_n1llOilO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill1iO_dataout; + wire_n0ill11l_dataout <= wire_n1llOiOi_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill1li_dataout; + wire_n0ill11O_dataout <= wire_n1llOiOl_dataout WHEN n1lO0lOi = '1' ELSE wire_n0ill1ll_dataout; + wire_n0ill1ii_dataout <= wire_nlOO10OOl_dataout WHEN niOlliOll = '1' ELSE wire_n0ill1OO_dataout; + wire_n0ill1il_dataout <= wire_nlOO10OOO_dataout WHEN niOlliOll = '1' ELSE wire_n0ill01i_dataout; + wire_n0ill1iO_dataout <= wire_nlOO1i11i_dataout WHEN niOlliOll = '1' ELSE wire_n0ill01l_dataout; + wire_n0ill1li_dataout <= wire_nlOO1i11l_dataout WHEN niOlliOll = '1' ELSE wire_n0ill01O_dataout; + wire_n0ill1ll_dataout <= wire_nlOO1i11O_dataout WHEN niOlliOll = '1' ELSE wire_n0ill00i_dataout; + wire_n0ill1lO_dataout <= wire_nlOO1i10i_dataout WHEN niOlliOll = '1' ELSE wire_n0ill00l_dataout; + wire_n0ill1Oi_dataout <= wire_nlOO1i10l_dataout WHEN niOlliOll = '1' ELSE wire_n0ill00O_dataout; + wire_n0ill1Ol_dataout <= n1101l1i WHEN niOlliOli = '1' ELSE n1l001ii; + wire_n0ill1OO_dataout <= n1101l1i WHEN niOlliOli = '1' ELSE n1l001il; + wire_n0illlOi_dataout <= n0li101i WHEN niOlliOlO = '1' ELSE (n0li101i XOR n0ilO1il); + wire_n0illO0O_dataout <= n0li11Oi WHEN niOlliOlO = '1' ELSE (n0li11Oi XOR n0ilO1ll); + wire_n0illO1i_dataout <= n0li11OO WHEN niOlliOlO = '1' ELSE (n0li11OO XOR n0ilO1iO); + wire_n0illO1O_dataout <= n0li11Ol WHEN niOlliOlO = '1' ELSE (n0li11Ol XOR n0ilO1li); + wire_n0illOil_dataout <= n0li11lO WHEN niOlliOlO = '1' ELSE (n0li11lO XOR n0ilO1lO); + wire_n0illOli_dataout <= n0li11ll WHEN niOlliOlO = '1' ELSE (n0li11ll XOR n0ilO1Oi); + wire_n0illOlO_dataout <= n0li11li WHEN niOlliOlO = '1' ELSE (n0li11li XOR n0ilO1Ol); + wire_n0illOOl_dataout <= n0li11iO WHEN niOlliOlO = '1' ELSE (n0li11iO XOR n0ilO1OO); + wire_n0ilO00i_dataout <= wire_n0ilOi0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO00l_dataout <= wire_n0ilOi0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO00O_dataout <= wire_n0ilOiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO01l_dataout <= wire_n0ilOi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO01O_dataout <= wire_n0ilOi0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0ii_dataout <= wire_n0ilOiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0il_dataout <= wire_n0ilOiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0iO_dataout <= wire_n0ilOili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0li_dataout <= wire_n0ilOill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0ll_dataout <= wire_n0ilOilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0lO_dataout <= wire_n0ilOiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0Oi_dataout <= wire_n0ilOiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0Ol_dataout <= wire_n0ilOiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilO0OO_dataout <= wire_n0ilOl1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilOi0i_dataout <= wire_n0ilOl0l_dataout OR niOlliOOl; + wire_n0ilOi0l_dataout <= wire_n0ilOl0O_dataout OR niOlliOOl; + wire_n0ilOi0O_dataout <= wire_n0ilOlii_dataout OR niOlliOOl; + wire_n0ilOi1i_dataout <= wire_n0ilOl1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilOi1l_dataout <= wire_n0ilOl1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilOi1O_dataout <= wire_n0ilOl0i_dataout OR niOlliOOl; + wire_n0ilOiii_dataout <= wire_n0ilOlil_dataout OR niOlliOOl; + wire_n0ilOiil_dataout <= wire_n0ilOliO_dataout OR niOlliOOl; + wire_n0ilOiiO_dataout <= wire_n0ilOlli_dataout OR niOlliOOl; + wire_n0ilOili_dataout <= wire_n0ilOlll_dataout OR niOlliOOl; + wire_n0ilOill_dataout <= wire_n0ilOllO_dataout OR niOlliOOl; + wire_n0ilOilO_dataout <= wire_n0ilOlOi_dataout OR niOlliOOl; + wire_n0ilOiOi_dataout <= wire_n0ilOlOl_dataout OR niOlliOOl; + wire_n0ilOiOl_dataout <= wire_n0ilOlOO_dataout OR niOlliOOl; + wire_n0ilOiOO_dataout <= wire_n0ilOO1i_dataout OR niOlliOOl; + wire_n0ilOl0i_dataout <= n0illO0l WHEN niOlliOOi = '1' ELSE n0ilO1il; + wire_n0ilOl0l_dataout <= n0ilO11i WHEN niOlliOOi = '1' ELSE n0ilO1iO; + wire_n0ilOl0O_dataout <= n0ilO11l WHEN niOlliOOi = '1' ELSE n0ilO1li; + wire_n0ilOl1i_dataout <= wire_n0ilOO1l_dataout OR niOlliOOl; + wire_n0ilOl1l_dataout <= wire_n0ilOO1O_dataout OR niOlliOOl; + wire_n0ilOl1O_dataout <= wire_n0ilOO0i_dataout OR niOlliOOl; + wire_n0ilOlii_dataout <= n0ilO11O WHEN niOlliOOi = '1' ELSE (n0ilO1ll XOR n0ilO1il); + wire_n0ilOlil_dataout <= n0ilO10i WHEN niOlliOOi = '1' ELSE (n0ilO1il XOR (n0ilO1lO XOR n0ilO1iO)); + wire_n0ilOliO_dataout <= n0ilO10l WHEN niOlliOOi = '1' ELSE (n0ilO1il XOR (n0ilO1iO XOR (n0ilO1Oi XOR n0ilO1li))); + wire_n0ilOlli_dataout <= n0ilO10O WHEN niOlliOOi = '1' ELSE (n0ilO1iO XOR (n0ilO1li XOR (n0ilO1Ol XOR n0ilO1ll))); + wire_n0ilOlll_dataout <= n0ilO1ii WHEN niOlliOOi = '1' ELSE (n0ilO1li XOR (n0ilO1ll XOR (n0ilO1OO XOR n0ilO1lO))); + wire_n0ilOllO_dataout <= n0ilO1il WHEN niOlliOOi = '1' ELSE (n0ilO1ll XOR (n0ilO1lO XOR (n0ilO1Oi XOR n0illO0l))); + wire_n0ilOlOi_dataout <= n0ilO1iO WHEN niOlliOOi = '1' ELSE (n0ilO1lO XOR (n0ilO1Oi XOR (n0ilO1Ol XOR n0ilO11i))); + wire_n0ilOlOl_dataout <= n0ilO1li WHEN niOlliOOi = '1' ELSE (n0ilO1Oi XOR (n0ilO1Ol XOR (n0ilO1OO XOR n0ilO11l))); + wire_n0ilOlOO_dataout <= n0ilO1ll WHEN niOlliOOi = '1' ELSE (n0ilO1Ol XOR (n0ilO1OO XOR n0ilO11O)); + wire_n0ilOO0i_dataout <= n0ilO1OO WHEN niOlliOOi = '1' ELSE n0ilO1ii; + wire_n0ilOO0O_dataout <= wire_n0ilOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ilOO1i_dataout <= n0ilO1lO WHEN niOlliOOi = '1' ELSE (n0ilO1OO XOR n0ilO10i); + wire_n0ilOO1l_dataout <= n0ilO1Oi WHEN niOlliOOi = '1' ELSE n0ilO10l; + wire_n0ilOO1O_dataout <= n0ilO1Ol WHEN niOlliOOi = '1' ELSE n0ilO10O; + wire_n0ilOOii_dataout <= wire_n0ilOOil_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n0ilO01i) AND niOlliOOl)); + wire_n0ilOOil_dataout <= n0ilO01i OR n111i10i; + wire_n0iO000i_dataout <= n0iO1l1i WHEN niOlll11l = '1' ELSE (n0iO1l0i XOR (n0iO1l0l XOR (n0iO1liO XOR n0iO1l0O))); + wire_n0iO000l_dataout <= n0iO1l1l WHEN niOlll11l = '1' ELSE (n0iO1l0l XOR (n0iO1l0O XOR (n0iO1lii XOR n0iO10Ol))); + wire_n0iO000O_dataout <= n0iO1l1O WHEN niOlll11l = '1' ELSE (n0iO1l0O XOR (n0iO1lii XOR (n0iO1lil XOR n0iO1ili))); + wire_n0iO001i_dataout <= n0iO1iOi WHEN niOlll11l = '1' ELSE (n0iO1l1l XOR (n0iO1l0O XOR n0iO1l1O)); + wire_n0iO001l_dataout <= n0iO1iOl WHEN niOlll11l = '1' ELSE (n0iO1l1l XOR (n0iO1l1O XOR (n0iO1lii XOR n0iO1l0i))); + wire_n0iO001O_dataout <= n0iO1iOO WHEN niOlll11l = '1' ELSE (n0iO1l1O XOR (n0iO1l0i XOR (n0iO1lil XOR n0iO1l0l))); + wire_n0iO00ii_dataout <= n0iO1l0i WHEN niOlll11l = '1' ELSE (n0iO1lii XOR (n0iO1lil XOR (n0iO1liO XOR n0iO1ill))); + wire_n0iO00il_dataout <= n0iO1l0l WHEN niOlll11l = '1' ELSE (n0iO1lil XOR (n0iO1liO XOR n0iO1ilO)); + wire_n0iO00iO_dataout <= n0iO1l0O WHEN niOlll11l = '1' ELSE (n0iO1liO XOR n0iO1iOi); + wire_n0iO00li_dataout <= n0iO1lii WHEN niOlll11l = '1' ELSE n0iO1iOl; + wire_n0iO00ll_dataout <= n0iO1lil WHEN niOlll11l = '1' ELSE n0iO1iOO; + wire_n0iO00lO_dataout <= n0iO1liO WHEN niOlll11l = '1' ELSE n0iO1l1i; + wire_n0iO010i_dataout <= wire_n0iO000l_dataout OR niOlll11i; + wire_n0iO010l_dataout <= wire_n0iO000O_dataout OR niOlll11i; + wire_n0iO010O_dataout <= wire_n0iO00ii_dataout OR niOlll11i; + wire_n0iO011i_dataout <= wire_n0iO001l_dataout OR niOlll11i; + wire_n0iO011l_dataout <= wire_n0iO001O_dataout OR niOlll11i; + wire_n0iO011O_dataout <= wire_n0iO000i_dataout OR niOlll11i; + wire_n0iO01ii_dataout <= wire_n0iO00il_dataout OR niOlll11i; + wire_n0iO01il_dataout <= wire_n0iO00iO_dataout OR niOlll11i; + wire_n0iO01iO_dataout <= wire_n0iO00li_dataout OR niOlll11i; + wire_n0iO01li_dataout <= wire_n0iO00ll_dataout OR niOlll11i; + wire_n0iO01ll_dataout <= wire_n0iO00lO_dataout OR niOlll11i; + wire_n0iO01lO_dataout <= n0iO10Ol WHEN niOlll11l = '1' ELSE n0iO1l1l; + wire_n0iO01Oi_dataout <= n0iO1ili WHEN niOlll11l = '1' ELSE n0iO1l1O; + wire_n0iO01Ol_dataout <= n0iO1ill WHEN niOlll11l = '1' ELSE n0iO1l0i; + wire_n0iO01OO_dataout <= n0iO1ilO WHEN niOlll11l = '1' ELSE (n0iO1l0l XOR n0iO1l1l); + wire_n0iO10ii_dataout <= wire_niO11Oll_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11Oll_dataout XOR n0iO1l1l); + wire_n0iO10ii_w_lg_dataout14014w(0) <= NOT wire_n0iO10ii_dataout; + wire_n0iO10li_dataout <= wire_niO11Oli_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11Oli_dataout XOR n0iO1l1O); + wire_n0iO10li_w_lg_dataout14012w(0) <= NOT wire_n0iO10li_dataout; + wire_n0iO10lO_dataout <= wire_niO11OiO_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11OiO_dataout XOR n0iO1l0i); + wire_n0iO10lO_w_lg_dataout14010w(0) <= NOT wire_n0iO10lO_dataout; + wire_n0iO10OO_dataout <= wire_niO11Oil_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11Oil_dataout XOR n0iO1l0l); + wire_n0iO10OO_w_lg_dataout14008w(0) <= NOT wire_n0iO10OO_dataout; + wire_n0iO1i0i_dataout <= wire_niO11O0O_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11O0O_dataout XOR n0iO1lii); + wire_n0iO1i0i_w_lg_dataout14004w(0) <= NOT wire_n0iO1i0i_dataout; + wire_n0iO1i0O_dataout <= wire_niO11O0l_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11O0l_dataout XOR n0iO1lil); + wire_n0iO1i0O_w_lg_dataout14002w(0) <= NOT wire_n0iO1i0O_dataout; + wire_n0iO1i1l_dataout <= wire_niO11Oii_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11Oii_dataout XOR n0iO1l0O); + wire_n0iO1i1l_w_lg_dataout14006w(0) <= NOT wire_n0iO1i1l_dataout; + wire_n0iO1iil_dataout <= wire_niO11O0i_dataout WHEN niOlliOOO = '1' ELSE (wire_niO11O0i_dataout XOR n0iO1liO); + wire_n0iO1iil_w_lg_dataout14000w(0) <= NOT wire_n0iO1iil_dataout; + wire_n0iO1lli_dataout <= wire_n0iO1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1lll_dataout <= wire_n0iO1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1llO_dataout <= wire_n0iO1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1lOi_dataout <= wire_n0iO1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1lOl_dataout <= wire_n0iO1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1lOO_dataout <= wire_n0iO011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1O0i_dataout <= wire_n0iO010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1O0l_dataout <= wire_n0iO010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1O0O_dataout <= wire_n0iO01ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1O1i_dataout <= wire_n0iO011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1O1l_dataout <= wire_n0iO011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1O1O_dataout <= wire_n0iO010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1Oii_dataout <= wire_n0iO01il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1Oil_dataout <= wire_n0iO01iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1OiO_dataout <= wire_n0iO01li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1Oli_dataout <= wire_n0iO01ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iO1Oll_dataout <= wire_n0iO01lO_dataout OR niOlll11i; + wire_n0iO1OlO_dataout <= wire_n0iO01Oi_dataout OR niOlll11i; + wire_n0iO1OOi_dataout <= wire_n0iO01Ol_dataout OR niOlll11i; + wire_n0iO1OOl_dataout <= wire_n0iO01OO_dataout OR niOlll11i; + wire_n0iO1OOO_dataout <= wire_n0iO001i_dataout OR niOlll11i; + wire_n0iOil0i_dataout <= wire_n0iO1i0i_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOil0l_dataout <= wire_n0iO1i1l_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOil0O_dataout <= wire_n0iO10OO_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOil1i_dataout <= wire_niO11O1O_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOil1l_dataout <= wire_n0iO1iil_dataout AND wire_niO11lOl_w_lg_dataout13909w(0); + wire_n0iOil1O_dataout <= wire_n0iO1i0O_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOilii_dataout <= wire_n0iO10lO_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOilil_dataout <= wire_n0iO10li_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOiliO_dataout <= wire_n0iO10ii_dataout OR NOT(wire_niO11lOl_w_lg_dataout13909w(0)); + wire_n0iOilOl_dataout <= wire_n0iOiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOilOO_dataout <= wire_n0iOiOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOiO0i_dataout <= n0iOiO0O OR (n0l01lli AND n0iOilli); + wire_n0iOiO1i_dataout <= wire_n0iOiOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOiO1l_dataout <= wire_n0iOiOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOiO1O_dataout <= wire_n0iOiO0i_dataout AND n0l01lli; + wire_n0iOiOii_dataout <= ((wire_niO11O1l_dataout AND niOllli1i) AND n0iOilll) AND n0l01lli; + wire_n0iOiOil_dataout <= (niOllll1l AND n0iOillO) AND n0l01lli; + wire_n0iOiOiO_dataout <= (n0l1OiOO AND (wire_niO11O1l_dataout AND niOllli1l)) AND n0l01lli; + wire_n0iOl01i_dataout <= wire_n0iOl0li_dataout WHEN niOllliiO = '1' ELSE n0iOilOi; + wire_n0iOl01l_dataout <= n0iOl11i AND NOT(niOlll10l); + wire_n0iOl01O_dataout <= n0iOl11l AND NOT(niOlll10l); + wire_n0iOl0il_dataout <= n0iOl11i WHEN niOlll10i = '1' ELSE wire_n0iOl0ll_o(0); + wire_n0iOl0iO_dataout <= n0iOl11l WHEN niOlll10i = '1' ELSE wire_n0iOl0ll_o(1); + wire_n0iOl0li_dataout <= n0iOilOi OR niOlll10i; + wire_n0iOl0lO_dataout <= n0iOl11i OR niOllliiO; + wire_n0iOl0Oi_dataout <= n0iOl11l AND NOT(niOllliiO); + wire_n0iOl0Ol_dataout <= wire_n0iOl0OO_dataout OR (niOllliOO AND (n0l1Oiii OR n0l1O0ii)); + wire_n0iOl0OO_dataout <= n0iOiOOO AND NOT(niOlll10l); + wire_n0iOl10i_dataout <= wire_n0iOl1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOl10l_dataout <= wire_n0iOl0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOl10O_dataout <= wire_n0iOl1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOl1ii_dataout <= wire_n0iOl1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOl1il_dataout <= wire_n0iOl1ll_dataout AND NOT(niOlll11O); + wire_n0iOl1iO_dataout <= wire_n0iOl0lO_dataout WHEN niOlll11O = '1' ELSE wire_n0iOl1lO_dataout; + wire_n0iOl1li_dataout <= wire_n0iOl0Oi_dataout WHEN niOlll11O = '1' ELSE wire_n0iOl1Oi_dataout; + wire_n0iOl1ll_dataout <= n0iOilOi WHEN wire_niO01ill_w_lg_n0iOiOOO13902w(0) = '1' ELSE wire_n0iOl01i_dataout; + wire_n0iOl1lO_dataout <= wire_n0iOl01l_dataout WHEN wire_niO01ill_w_lg_n0iOiOOO13902w(0) = '1' ELSE wire_n0iOl1Ol_dataout; + wire_n0iOl1Oi_dataout <= wire_n0iOl01O_dataout WHEN wire_niO01ill_w_lg_n0iOiOOO13902w(0) = '1' ELSE wire_n0iOl1OO_dataout; + wire_n0iOl1Ol_dataout <= wire_n0iOl0il_dataout WHEN niOllliiO = '1' ELSE wire_n0iOl01l_dataout; + wire_n0iOl1OO_dataout <= wire_n0iOl0iO_dataout WHEN niOllliiO = '1' ELSE wire_n0iOl01O_dataout; + wire_n0iOliiO_dataout <= wire_n0iOliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOlili_dataout <= wire_n0iOll1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOlill_dataout <= wire_n0iOll1l_dataout OR wire_niO01lOO_dataout; + wire_n0iOlilO_dataout <= wire_n0iOll1O_dataout OR wire_niO01lOO_dataout; + wire_n0iOliOi_dataout <= wire_n0iOll0i_dataout OR wire_niO01lOO_dataout; + wire_n0iOliOl_dataout <= wire_n0iOll0l_dataout OR wire_niO01lOO_dataout; + wire_n0iOliOO_dataout <= wire_n0iOll0O_dataout OR niOlll00i; + wire_n0iOll0i_dataout <= wire_n0iOllli_dataout OR niOlll00i; + wire_n0iOll0l_dataout <= wire_n0iOllll_dataout OR niOlll00i; + wire_n0iOll0O_dataout <= wire_n0iOlllO_dataout AND n0iOl11O; + wire_n0iOll1i_dataout <= wire_n0iOllii_dataout AND NOT(niOlll00i); + wire_n0iOll1l_dataout <= wire_n0iOllil_dataout OR niOlll00i; + wire_n0iOll1O_dataout <= wire_n0iOlliO_dataout AND NOT(niOlll00i); + wire_n0iOllii_dataout <= wire_n0iOllOi_dataout AND n0iOl11O; + wire_n0iOllil_dataout <= wire_n0iOllOl_dataout OR NOT(n0iOl11O); + wire_n0iOlliO_dataout <= wire_n0iOllOO_dataout OR NOT(n0iOl11O); + wire_n0iOllli_dataout <= wire_n0iOlO1i_dataout OR NOT(n0iOl11O); + wire_n0iOllll_dataout <= wire_n0iOlO1l_dataout OR NOT(n0iOl11O); + wire_n0iOlllO_dataout <= n0iOl11O WHEN niOlll1ii = '1' ELSE wire_n0iOlO1O_dataout; + wire_n0iOllOi_dataout <= niOlll10O AND NOT(niOlll1ii); + wire_n0iOllOl_dataout <= wire_n0iOlO0l_o(1) OR NOT(niOlll1ii); + wire_n0iOllOO_dataout <= wire_n0iOlO0l_o(2) OR NOT(niOlll1ii); + wire_n0iOlO1i_dataout <= wire_n0iOlO0l_o(3) OR NOT(niOlll1ii); + wire_n0iOlO1l_dataout <= wire_n0iOlO0l_o(4) OR NOT(niOlll1ii); + wire_n0iOlO1O_dataout <= n0iOl11O AND niOlll10O; + wire_n0iOOili_dataout <= wire_n0l11liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOill_dataout <= wire_n0l11lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOilO_dataout <= wire_n0l11lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOiOi_dataout <= ((niOllliiO OR niOllliil) OR niOllliii) AND NOT(wire_niO01lOO_dataout); + wire_n0iOOiOl_dataout <= (n0l1OiOO AND (niOllll1l OR niOllliOi)) AND NOT(wire_niO01lOO_dataout); + wire_n0iOOiOO_dataout <= wire_n0l111ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOl0i_dataout <= wire_n0l111OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOl0l_dataout <= wire_n0l1101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOl0O_dataout <= wire_n0l1101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOl1i_dataout <= wire_n0l111lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOl1l_dataout <= wire_n0l111Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOl1O_dataout <= wire_n0l111Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOlii_dataout <= wire_n0l1101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOlil_dataout <= wire_n0l11llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOliO_dataout <= wire_n0l11lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOlli_dataout <= wire_n0l11lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOlll_dataout <= wire_n0l11lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOllO_dataout <= wire_n0l11O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOlOi_dataout <= wire_n0l11O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOlOl_dataout <= wire_n0l11O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOlOO_dataout <= wire_n0l11O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOO0i_dataout <= wire_n0l11Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOO0l_dataout <= wire_n0l11OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOO0O_dataout <= wire_n0l11Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOO1i_dataout <= wire_n0l11O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOO1l_dataout <= wire_n0l11O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOO1O_dataout <= wire_n0l11Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOii_dataout <= wire_n0l11Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOil_dataout <= wire_n0l11OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOiO_dataout <= wire_n0l11OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOli_dataout <= wire_n0l11OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOll_dataout <= wire_n0l11ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOlO_dataout <= wire_n0l11ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOOi_dataout <= wire_n0l11iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOOl_dataout <= wire_n0l11iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0iOOOOO_dataout <= wire_n0l11iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0000i_dataout <= wire_n0l000ll_dataout AND NOT(niOllllil); + wire_n0l0000l_dataout <= wire_n0l000lO_dataout AND NOT(niOllllil); + wire_n0l0000O_dataout <= wire_n0l000Oi_dataout AND NOT(niOllllil); + wire_n0l0001i_dataout <= wire_n0l00ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0001l_dataout <= wire_n0l000iO_dataout AND NOT(niOllllil); + wire_n0l0001O_dataout <= wire_n0l000li_dataout AND NOT(niOllllil); + wire_n0l000i_dataout <= wire_n0llO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l000ii_dataout <= wire_n0l000Ol_dataout AND NOT(niOllllil); + wire_n0l000il_dataout <= wire_n0l000OO_dataout AND NOT(niOllllil); + wire_n0l000iO_dataout <= wire_n0l00i1i_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01l1O; + wire_n0l000l_dataout <= wire_n0llO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l000li_dataout <= wire_n0l00i1i_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01l0i; + wire_n0l000ll_dataout <= wire_n0l00i1i_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01l0l; + wire_n0l000lO_dataout <= wire_n0l00i1i_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01l0O; + wire_n0l000O_dataout <= wire_n0llO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l000Oi_dataout <= wire_n0l00i1i_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01lii; + wire_n0l000Ol_dataout <= wire_n0l00i1i_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01lil; + wire_n0l000OO_dataout <= wire_n0l00i1i_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01liO; + wire_n0l0010i_dataout <= wire_n0l0000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0010l_dataout <= wire_n0l000ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0010O_dataout <= wire_n0l000il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0011i_dataout <= wire_n0l0001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0011l_dataout <= wire_n0l0000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0011O_dataout <= wire_n0l0000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001i_dataout <= wire_n0lllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l001ii_dataout <= wire_n0l00i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001il_dataout <= wire_n0l0Ol1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001iO_dataout <= wire_n0l0Ol0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001l_dataout <= wire_n0lllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l001li_dataout <= wire_n0l0Ol0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001ll_dataout <= wire_n0l0Ol0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001lO_dataout <= wire_n0l0Olii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001O_dataout <= wire_n0lllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l001Oi_dataout <= wire_n0l0Olil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001Ol_dataout <= wire_n0l0OOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l001OO_dataout <= wire_n0l00ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l00i0l_dataout <= wire_n0l00i0O_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13377w(0) AND wire_w_lg_niOllO10l13378w(0)); + wire_n0l00i0O_dataout <= n0l01lli AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOllO10O13524w(0))); + wire_n0l00ii_dataout <= wire_n0llO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00il_dataout <= wire_n0llO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00ili_dataout <= n0l01O1O WHEN nlOllOlOi = '1' ELSE wire_n0l00ill_dataout; + wire_n0l00ill_dataout <= wire_n0l00ilO_dataout OR niOlllOOi; + wire_n0l00ilO_dataout <= wire_n0l00iOi_dataout OR n0li110O; + wire_n0l00iO_dataout <= wire_n0llO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00iOi_dataout <= wire_n0l00iOl_dataout OR (wire_niO01ill_w_lg_n0li111O13375w(0) AND (wire_n0l01i1i_dataout AND niOlllOii)); + wire_n0l00iOl_dataout <= wire_n0l00l1i_dataout OR (wire_niO01ill_w_lg_n0li111O13375w(0) AND (wire_n0l01i1i_dataout AND niOllllOO)); + wire_n0l00l1i_dataout <= wire_n0l00l1l_dataout OR (wire_niO01ill_w_lg_n0li111O13375w(0) AND wire_n0l01i1i_w_lg_dataout13518w(0)); + wire_n0l00l1l_dataout <= wire_n0l00l1O_dataout OR (wire_niO01ill_w_lg_n0li111O13375w(0) AND wire_n0l01i1i_w_lg_w_lg_w_lg_dataout13505w13511w13512w(0)); + wire_n0l00l1O_dataout <= n0l01O0i AND nlOllOlOi; + wire_n0l00li_dataout <= wire_n0llOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00ll_dataout <= wire_n0llOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00lO_dataout <= wire_n0llOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00lOi_dataout <= wire_n0l00lOl_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n0li110l AND n0l01lOi)) OR (n0li110l AND n0l01l0l)); + wire_n0l00lOl_dataout <= n0l0110i AND nlOllOlOi; + wire_n0l00O0i_dataout <= wire_n0illOOl_dataout WHEN niOllO11l = '1' ELSE wire_n0l00OOi_dataout; + wire_n0l00O0l_dataout <= wire_n0illOlO_dataout WHEN niOllO11l = '1' ELSE wire_n0l00OOl_dataout; + wire_n0l00O0O_dataout <= wire_n0illOli_dataout WHEN niOllO11l = '1' ELSE wire_n0l00OOO_dataout; + wire_n0l00Oi_dataout <= wire_n0llOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00Oii_dataout <= wire_n0illOil_dataout WHEN niOllO11l = '1' ELSE wire_n0l0i11i_dataout; + wire_n0l00Oil_dataout <= wire_n0illO0O_dataout WHEN niOllO11l = '1' ELSE wire_n0l0i11l_dataout; + wire_n0l00OiO_dataout <= wire_n0illO1O_dataout WHEN niOllO11l = '1' ELSE wire_n0l0i11O_dataout; + wire_n0l00Ol_dataout <= wire_n0llOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00Oli_dataout <= wire_n0illO1i_dataout WHEN niOllO11l = '1' ELSE wire_n0l0i10i_dataout; + wire_n0l00Oll_dataout <= wire_n0illlOi_dataout WHEN niOllO11l = '1' ELSE wire_n0l0i10l_dataout; + wire_n0l00OlO_dataout <= n0li11il WHEN niOllO11l = '1' ELSE wire_n0l0i10O_dataout; + wire_n0l00OO_dataout <= wire_n0llOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l00OOi_dataout <= wire_n0l0i1il_dataout AND NOT(niOlllOOO); + wire_n0l00OOl_dataout <= wire_n0l0i1iO_dataout AND NOT(niOlllOOO); + wire_n0l00OOO_dataout <= wire_n0l0i1li_dataout OR niOlllOOO; + wire_n0l0100i_dataout <= wire_n0l010ll_o(0) WHEN niOllll0i = '1' ELSE n0l1Ol1i; + wire_n0l0100l_dataout <= wire_n0l010ll_o(1) WHEN niOllll0i = '1' ELSE n0l1OOOi; + wire_n0l0100O_dataout <= wire_n0l010ll_o(2) WHEN niOllll0i = '1' ELSE n0l1OOOl; + wire_n0l0101i_dataout <= wire_n0l010il_dataout AND NOT(niOllll0O); + wire_n0l0101l_dataout <= wire_n0l010iO_dataout AND NOT(niOllll0O); + wire_n0l0101O_dataout <= wire_n0l010li_dataout AND NOT(niOllll0O); + wire_n0l010i_dataout <= wire_n0lll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l010ii_dataout <= wire_n0l010ll_o(3) WHEN niOllll0i = '1' ELSE n0l1OOOO; + wire_n0l010il_dataout <= wire_n0l010ll_o(4) WHEN niOllll0i = '1' ELSE n0l0111i; + wire_n0l010iO_dataout <= wire_n0l010ll_o(5) WHEN niOllll0i = '1' ELSE n0l0111l; + wire_n0l010l_dataout <= wire_n0lll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l010li_dataout <= wire_n0l010ll_o(6) WHEN niOllll0i = '1' ELSE n0l0111O; + wire_n0l010O_dataout <= wire_n0lll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0110l_dataout <= wire_n0l011lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0110O_dataout <= wire_n0l011Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l011i_dataout <= wire_n0lliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l011ii_dataout <= wire_n0l011Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l011il_dataout <= wire_n0l011OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l011iO_dataout <= wire_n0l0101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l011l_dataout <= wire_n0lliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l011li_dataout <= wire_n0l0101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l011ll_dataout <= wire_n0l0101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l011lO_dataout <= wire_n0l0100i_dataout AND NOT(niOllll0O); + wire_n0l011O_dataout <= wire_n0lliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l011Oi_dataout <= wire_n0l0100l_dataout AND NOT(niOllll0O); + wire_n0l011Ol_dataout <= wire_n0l0100O_dataout AND NOT(niOllll0O); + wire_n0l011OO_dataout <= wire_n0l010ii_dataout AND NOT(niOllll0O); + wire_n0l01i0i_dataout <= n0l01O1l AND ((NOT (n0l01lOi XOR n0l01llO)) AND niOllllii); + wire_n0l01i1i_dataout <= n0l01lli AND (((NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0l01lii)) AND (NOT (n1101l1i XOR n0l01lil))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0l01liO))); + wire_n0l01i1i_w_lg_w_lg_w_lg_dataout13505w13511w13512w(0) <= wire_n0l01i1i_w_lg_w_lg_dataout13505w13511w(0) AND n0l01lli; + wire_n0l01i1i_w_lg_w_lg_dataout13505w13511w(0) <= wire_n0l01i1i_w_lg_dataout13505w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n0l01l0l13506w13508w13510w(0); + wire_n0l01i1i_w_lg_dataout13518w(0) <= wire_n0l01i1i_dataout AND wire_niO01ill_w13517w(0); + wire_n0l01i1i_w_lg_dataout13505w(0) <= NOT wire_n0l01i1i_dataout; + wire_n0l01i1l_dataout <= n0l01O1l AND (n0l01lll AND niOllllii); + wire_n0l01ii_dataout <= wire_n0lll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01iii_dataout <= n0l0110i AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllOlOi); + wire_n0l01il_dataout <= wire_n0lll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01iO_dataout <= wire_n0lll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01li_dataout <= wire_n0lllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01ll_dataout <= wire_n0lllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01lO_dataout <= wire_n0llliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01O0l_dataout <= wire_n0l00lOi_dataout OR wire_niO01lOO_dataout; + wire_n0l01O0O_dataout <= wire_n0l00O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01Oi_dataout <= wire_n0lllli_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01Oii_dataout <= wire_n0l00O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01Oil_dataout <= wire_n0l00O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01OiO_dataout <= wire_n0l00Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01Ol_dataout <= wire_n0lllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01Oli_dataout <= wire_n0l00Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01Oll_dataout <= wire_n0l00OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01OlO_dataout <= wire_n0l00Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01OO_dataout <= wire_n0llllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l01OOi_dataout <= wire_n0l00Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01OOl_dataout <= wire_n0l00OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l01OOO_dataout <= wire_n0l0001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l0i00i_dataout <= wire_n0l0i0Oi_dataout OR niOlllOli; + wire_n0l0i00l_dataout <= wire_n0l0i0Ol_dataout OR niOlllOli; + wire_n0l0i00O_dataout <= wire_n0l0i0OO_dataout OR niOlllOli; + wire_n0l0i01i_dataout <= wire_n0l0i0li_dataout AND NOT(niOlllOli); + wire_n0l0i01l_dataout <= wire_n0l0i0ll_dataout AND NOT(niOlllOli); + wire_n0l0i01O_dataout <= wire_n0l0i0lO_dataout OR niOlllOli; + wire_n0l0i0i_dataout <= wire_n0li0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0i0ii_dataout <= wire_n0l0ii1i_dataout OR niOlllOli; + wire_n0l0i0il_dataout <= wire_n0l0ii1l_dataout AND NOT(niOlllOli); + wire_n0l0i0iO_dataout <= wire_n0l0ii1O_dataout OR niOlllOli; + wire_n0l0i0l_dataout <= wire_n0li0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0i0li_dataout <= wire_n0l0ii0i_dataout OR niOlllOiO; + wire_n0l0i0ll_dataout <= wire_n0l0ii0l_dataout AND NOT(niOlllOiO); + wire_n0l0i0lO_dataout <= wire_n0l0ii0O_dataout OR niOlllOiO; + wire_n0l0i0O_dataout <= wire_n0li0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0i0Oi_dataout <= wire_n0l0iiii_dataout AND NOT(niOlllOiO); + wire_n0l0i0Ol_dataout <= wire_n0l0iiil_dataout OR niOlllOiO; + wire_n0l0i0OO_dataout <= wire_n0l0iiiO_dataout OR niOlllOiO; + wire_n0l0i10i_dataout <= wire_n0l0i1Ol_dataout AND NOT(niOlllOOO); + wire_n0l0i10l_dataout <= wire_n0l0i1OO_dataout OR niOlllOOO; + wire_n0l0i10O_dataout <= wire_n0l0i1ii_dataout OR niOlllOOO; + wire_n0l0i11i_dataout <= wire_n0l0i1ll_dataout OR niOlllOOO; + wire_n0l0i11l_dataout <= wire_n0l0i1lO_dataout OR niOlllOOO; + wire_n0l0i11O_dataout <= wire_n0l0i1Oi_dataout OR niOlllOOO; + wire_n0l0i1i_dataout <= wire_n0li00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0i1ii_dataout <= wire_n0l0i0iO_dataout AND NOT(niOlllOlO); + wire_n0l0i1il_dataout <= wire_n0l0i01i_dataout AND NOT(niOlllOlO); + wire_n0l0i1iO_dataout <= wire_n0l0i01l_dataout AND NOT(niOlllOlO); + wire_n0l0i1l_dataout <= wire_n0li00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0i1li_dataout <= wire_n0l0i01O_dataout AND NOT(niOlllOlO); + wire_n0l0i1ll_dataout <= wire_n0l0i00i_dataout AND NOT(niOlllOlO); + wire_n0l0i1lO_dataout <= wire_n0l0i00l_dataout AND NOT(niOlllOlO); + wire_n0l0i1O_dataout <= wire_n0li0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0i1Oi_dataout <= wire_n0l0i00O_dataout AND NOT(niOlllOlO); + wire_n0l0i1Ol_dataout <= wire_n0l0i0ii_dataout AND NOT(niOlllOlO); + wire_n0l0i1OO_dataout <= wire_n0l0i0il_dataout AND NOT(niOlllOlO); + wire_n0l0ii0i_dataout <= wire_n0l0iiOi_dataout AND NOT(niOlllOil); + wire_n0l0ii0l_dataout <= wire_n0l0iiOl_dataout OR niOlllOil; + wire_n0l0ii0O_dataout <= wire_n0l0iiOO_dataout AND NOT(niOlllOil); + wire_n0l0ii1i_dataout <= wire_n0l0iili_dataout AND NOT(niOlllOiO); + wire_n0l0ii1l_dataout <= wire_n0l0iill_dataout OR niOlllOiO; + wire_n0l0ii1O_dataout <= wire_n0l0iilO_dataout AND NOT(niOlllOiO); + wire_n0l0iii_dataout <= wire_n0li0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0iiii_dataout <= wire_n0l0il1i_dataout OR niOlllOil; + wire_n0l0iiil_dataout <= wire_n0l0il1l_dataout AND NOT(niOlllOil); + wire_n0l0iiiO_dataout <= wire_n0l0il1O_dataout AND NOT(niOlllOil); + wire_n0l0iil_dataout <= wire_n0li0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0iili_dataout <= wire_n0l0il0i_dataout OR niOlllOil; + wire_n0l0iill_dataout <= wire_n0l0il0l_dataout AND NOT(niOlllOil); + wire_n0l0iilO_dataout <= wire_n0l0il0O_dataout AND NOT(niOlllOil); + wire_n0l0iiO_dataout <= wire_n0li0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0iiOi_dataout <= wire_n0l0l0OO_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0ilii_dataout; + wire_n0l0iiOl_dataout <= wire_n0l0li1i_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0ilil_dataout; + wire_n0l0iiOO_dataout <= wire_n0l0li1l_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0iliO_dataout; + wire_n0l0il0i_dataout <= wire_n0l0li0O_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0ilOi_dataout; + wire_n0l0il0l_dataout <= wire_n0l0liii_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0ilOl_dataout; + wire_n0l0il0O_dataout <= wire_n0l0liil_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0ilOO_dataout; + wire_n0l0il1i_dataout <= wire_n0l0li1O_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0illi_dataout; + wire_n0l0il1l_dataout <= wire_n0l0li0i_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0illl_dataout; + wire_n0l0il1O_dataout <= wire_n0l0li0l_dataout WHEN wire_n0l01i1i_dataout = '1' ELSE wire_n0l0illO_dataout; + wire_n0l0ili_dataout <= wire_n0li0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0ilii_dataout <= wire_n0l0iO1i_dataout AND NOT(niOllllOi); + wire_n0l0ilil_dataout <= wire_n0l0iO1l_dataout AND NOT(niOllllOi); + wire_n0l0iliO_dataout <= wire_n0l0iO1O_dataout OR niOllllOi; + wire_n0l0ill_dataout <= wire_n0li0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0illi_dataout <= wire_n0l0iO0i_dataout OR niOllllOi; + wire_n0l0illl_dataout <= wire_n0l0iO0l_dataout OR niOllllOi; + wire_n0l0illO_dataout <= wire_n0l0iO0O_dataout OR niOllllOi; + wire_n0l0ilO_dataout <= wire_n0lii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0ilOi_dataout <= wire_n0l0iOii_dataout AND NOT(niOllllOi); + wire_n0l0ilOl_dataout <= wire_n0l0iOil_dataout OR niOllllOi; + wire_n0l0ilOO_dataout <= wire_n0l0iOiO_dataout OR niOllllOi; + wire_n0l0iO0i_dataout <= wire_n0l0iOOi_dataout OR niOlllllO; + wire_n0l0iO0l_dataout <= wire_n0l0iOOl_dataout OR niOlllllO; + wire_n0l0iO0O_dataout <= wire_n0l0iOOO_dataout OR niOlllllO; + wire_n0l0iO1i_dataout <= wire_n0l0iOli_dataout AND NOT(niOlllllO); + wire_n0l0iO1l_dataout <= wire_n0l0iOll_dataout AND NOT(niOlllllO); + wire_n0l0iO1O_dataout <= wire_n0l0iOlO_dataout OR niOlllllO; + wire_n0l0iOi_dataout <= wire_n0lii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0iOii_dataout <= wire_n0l0l11i_dataout OR niOlllllO; + wire_n0l0iOil_dataout <= wire_n0l0l11l_dataout AND NOT(niOlllllO); + wire_n0l0iOiO_dataout <= wire_n0l0l11O_dataout OR niOlllllO; + wire_n0l0iOl_dataout <= wire_n0lii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0iOli_dataout <= wire_n0l0l10i_dataout AND NOT(niOllllll); + wire_n0l0iOll_dataout <= wire_n0l0l10l_dataout AND NOT(niOllllll); + wire_n0l0iOlO_dataout <= wire_n0l0l10O_dataout AND NOT(niOllllll); + wire_n0l0iOO_dataout <= wire_n0lii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0iOOi_dataout <= wire_n0l0l1ii_dataout AND NOT(niOllllll); + wire_n0l0iOOl_dataout <= wire_n0l0l1il_dataout AND NOT(niOllllll); + wire_n0l0iOOO_dataout <= wire_n0l0l1iO_dataout AND NOT(niOllllll); + wire_n0l0l00i_dataout <= n0l01iOO WHEN niOllllli = '1' ELSE wire_n0illO1i_dataout; + wire_n0l0l00l_dataout <= n0l01l1i WHEN niOllllli = '1' ELSE wire_n0illlOi_dataout; + wire_n0l0l00O_dataout <= n0li11il AND NOT(niOllllli); + wire_n0l0l01i_dataout <= n0l01ilO WHEN niOllllli = '1' ELSE wire_n0illOil_dataout; + wire_n0l0l01l_dataout <= n0l01iOi WHEN niOllllli = '1' ELSE wire_n0illO0O_dataout; + wire_n0l0l01O_dataout <= n0l01iOl WHEN niOllllli = '1' ELSE wire_n0illO1O_dataout; + wire_n0l0l0i_dataout <= wire_n0liiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0l0l_dataout <= wire_n0liiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0l0O_dataout <= wire_n0liili_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0l0OO_dataout <= wire_n0l0liiO_dataout AND NOT(niOllllOl); + wire_n0l0l10i_dataout <= n0l1Ol1i WHEN niOlllliO = '1' ELSE wire_n0l0l1Oi_dataout; + wire_n0l0l10l_dataout <= n0l1OOOi WHEN niOlllliO = '1' ELSE wire_n0l0l1Ol_dataout; + wire_n0l0l10O_dataout <= n0l1OOOl WHEN niOlllliO = '1' ELSE wire_n0l0l1OO_dataout; + wire_n0l0l11i_dataout <= wire_n0l0l1li_dataout AND NOT(niOllllll); + wire_n0l0l11l_dataout <= wire_n0l0l1ll_dataout AND NOT(niOllllll); + wire_n0l0l11O_dataout <= wire_n0l0l1lO_dataout AND NOT(niOllllll); + wire_n0l0l1i_dataout <= wire_n0lii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0l1ii_dataout <= n0l1OOOO WHEN niOlllliO = '1' ELSE wire_n0l0l01i_dataout; + wire_n0l0l1il_dataout <= n0l0111i WHEN niOlllliO = '1' ELSE wire_n0l0l01l_dataout; + wire_n0l0l1iO_dataout <= n0l0111l WHEN niOlllliO = '1' ELSE wire_n0l0l01O_dataout; + wire_n0l0l1l_dataout <= wire_n0lii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0l1li_dataout <= n0l0111O WHEN niOlllliO = '1' ELSE wire_n0l0l00i_dataout; + wire_n0l0l1ll_dataout <= n0iOiO0O WHEN niOlllliO = '1' ELSE wire_n0l0l00l_dataout; + wire_n0l0l1lO_dataout <= wire_n0l0l00O_dataout AND NOT(niOlllliO); + wire_n0l0l1O_dataout <= wire_n0liiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0l1Oi_dataout <= n0l01iiO WHEN niOllllli = '1' ELSE wire_n0illOOl_dataout; + wire_n0l0l1Ol_dataout <= n0l01ili WHEN niOllllli = '1' ELSE wire_n0illOlO_dataout; + wire_n0l0l1OO_dataout <= n0l01ill WHEN niOllllli = '1' ELSE wire_n0illOli_dataout; + wire_n0l0li0i_dataout <= wire_n0l0liOi_dataout OR niOllllOl; + wire_n0l0li0l_dataout <= wire_n0l0liOl_dataout OR niOllllOl; + wire_n0l0li0O_dataout <= wire_n0l0liOO_dataout AND NOT(niOllllOl); + wire_n0l0li1i_dataout <= wire_n0l0lili_dataout AND NOT(niOllllOl); + wire_n0l0li1l_dataout <= wire_n0l0lill_dataout OR niOllllOl; + wire_n0l0li1O_dataout <= wire_n0l0lilO_dataout OR niOllllOl; + wire_n0l0lii_dataout <= wire_n0liill_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0liii_dataout <= wire_n0l0ll1i_dataout OR niOllllOl; + wire_n0l0liil_dataout <= wire_n0l0ll1l_dataout OR niOllllOl; + wire_n0l0liiO_dataout <= wire_n0l0ll1O_dataout AND NOT(niOllllOO); + wire_n0l0lil_dataout <= wire_n0liilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0lili_dataout <= wire_n0l0ll0i_dataout AND NOT(niOllllOO); + wire_n0l0lill_dataout <= wire_n0l0ll0l_dataout OR niOllllOO; + wire_n0l0lilO_dataout <= wire_n0l0ll0O_dataout OR niOllllOO; + wire_n0l0liO_dataout <= wire_n0liiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0liOi_dataout <= wire_n0l0llii_dataout OR niOllllOO; + wire_n0l0liOl_dataout <= wire_n0l0llil_dataout OR niOllllOO; + wire_n0l0liOO_dataout <= wire_n0l0lliO_dataout AND NOT(niOllllOO); + wire_n0l0ll0i_dataout <= wire_n0l0llOi_dataout AND NOT(niOlllO1i); + wire_n0l0ll0l_dataout <= wire_n0l0llOl_dataout OR niOlllO1i; + wire_n0l0ll0O_dataout <= wire_n0l0llOO_dataout AND NOT(niOlllO1i); + wire_n0l0ll1i_dataout <= wire_n0l0llli_dataout OR niOllllOO; + wire_n0l0ll1l_dataout <= wire_n0l0llll_dataout OR niOllllOO; + wire_n0l0ll1O_dataout <= wire_n0l0lllO_dataout OR niOlllO1i; + wire_n0l0lli_dataout <= wire_n0liiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0llii_dataout <= wire_n0l0lO1i_dataout OR niOlllO1i; + wire_n0l0llil_dataout <= wire_n0l0lO1l_dataout OR niOlllO1i; + wire_n0l0lliO_dataout <= wire_n0l0lO1O_dataout AND NOT(niOlllO1i); + wire_n0l0lll_dataout <= wire_n0liiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0llli_dataout <= wire_n0l0lO0i_dataout OR niOlllO1i; + wire_n0l0llll_dataout <= wire_n0l0lO0l_dataout AND NOT(niOlllO1i); + wire_n0l0lllO_dataout <= wire_n0l0lO0O_dataout AND NOT(niOlllO1l); + wire_n0l0llO_dataout <= wire_n0lil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0llOi_dataout <= wire_n0l0lOii_dataout AND NOT(niOlllO1l); + wire_n0l0llOl_dataout <= wire_n0l0lOil_dataout OR niOlllO1l; + wire_n0l0llOO_dataout <= wire_n0l0lOiO_dataout OR niOlllO1l; + wire_n0l0lO0i_dataout <= wire_n0l0lOOi_dataout OR niOlllO1l; + wire_n0l0lO0l_dataout <= wire_n0l0lOOl_dataout OR niOlllO1l; + wire_n0l0lO0O_dataout <= wire_n0l0lOOO_dataout AND NOT(niOlllO1O); + wire_n0l0lO1i_dataout <= wire_n0l0lOli_dataout OR niOlllO1l; + wire_n0l0lO1l_dataout <= wire_n0l0lOll_dataout OR niOlllO1l; + wire_n0l0lO1O_dataout <= wire_n0l0lOlO_dataout AND NOT(niOlllO1l); + wire_n0l0lOi_dataout <= wire_n0lil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0lOii_dataout <= wire_n0l0O11i_dataout OR niOlllO1O; + wire_n0l0lOil_dataout <= wire_n0l0O11l_dataout AND NOT(niOlllO1O); + wire_n0l0lOiO_dataout <= wire_n0l0O11O_dataout OR niOlllO1O; + wire_n0l0lOl_dataout <= wire_n0lil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0lOli_dataout <= wire_n0l0O10i_dataout AND NOT(niOlllO1O); + wire_n0l0lOll_dataout <= wire_n0l0O10l_dataout AND NOT(niOlllO1O); + wire_n0l0lOlO_dataout <= wire_n0l0O10O_dataout OR niOlllO1O; + wire_n0l0lOO_dataout <= wire_n0lil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0lOOi_dataout <= wire_n0l0O1ii_dataout AND NOT(niOlllO1O); + wire_n0l0lOOl_dataout <= wire_n0l0O1il_dataout AND NOT(niOlllO1O); + wire_n0l0lOOO_dataout <= n0l1Ol1i WHEN niOlllO0i = '1' ELSE wire_n0l0O1iO_dataout; + wire_n0l0O00i_dataout <= wire_n0l0O0Oi_dataout AND NOT(niOlllO0O); + wire_n0l0O00l_dataout <= wire_n0l0O0Ol_dataout OR niOlllO0O; + wire_n0l0O00O_dataout <= wire_n0l0O0OO_dataout OR niOlllO0O; + wire_n0l0O01i_dataout <= n0l01l1i WHEN niOlllO0l = '1' ELSE wire_n0l0O0li_dataout; + wire_n0l0O01l_dataout <= wire_n0l0O0ll_dataout AND NOT(niOlllO0l); + wire_n0l0O01O_dataout <= wire_n0l0O0lO_dataout AND NOT(niOlllO0O); + wire_n0l0O0i_dataout <= wire_n0lilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0O0ii_dataout <= wire_n0l0Oi1i_dataout OR niOlllO0O; + wire_n0l0O0il_dataout <= wire_n0l0Oi1l_dataout OR niOlllO0O; + wire_n0l0O0iO_dataout <= wire_n0l0Oi1O_dataout AND NOT(niOlllO0O); + wire_n0l0O0l_dataout <= wire_n0liliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0O0li_dataout <= wire_n0l0Oi0i_dataout OR niOlllO0O; + wire_n0l0O0ll_dataout <= wire_n0l0Oi0l_dataout OR niOlllO0O; + wire_n0l0O0lO_dataout <= n0l01iiO AND NOT(niOlllOii); + wire_n0l0O0O_dataout <= wire_n0lilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0O0Oi_dataout <= n0l01ili AND NOT(niOlllOii); + wire_n0l0O0Ol_dataout <= n0l01ill OR niOlllOii; + wire_n0l0O0OO_dataout <= n0l01ilO OR niOlllOii; + wire_n0l0O10i_dataout <= n0l0111i WHEN niOlllO0i = '1' ELSE wire_n0l0O1Oi_dataout; + wire_n0l0O10l_dataout <= n0l0111l WHEN niOlllO0i = '1' ELSE wire_n0l0O1Ol_dataout; + wire_n0l0O10O_dataout <= n0l0111O WHEN niOlllO0i = '1' ELSE wire_n0l0O1OO_dataout; + wire_n0l0O11i_dataout <= n0l1OOOi WHEN niOlllO0i = '1' ELSE wire_n0l0O1li_dataout; + wire_n0l0O11l_dataout <= n0l1OOOl WHEN niOlllO0i = '1' ELSE wire_n0l0O1ll_dataout; + wire_n0l0O11O_dataout <= n0l1OOOO WHEN niOlllO0i = '1' ELSE wire_n0l0O1lO_dataout; + wire_n0l0O1i_dataout <= wire_n0lil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0O1ii_dataout <= n0iOiO0O WHEN niOlllO0i = '1' ELSE wire_n0l0O01i_dataout; + wire_n0l0O1il_dataout <= wire_n0l0O01l_dataout AND NOT(niOlllO0i); + wire_n0l0O1iO_dataout <= n0l01iiO WHEN niOlllO0l = '1' ELSE wire_n0l0O01O_dataout; + wire_n0l0O1l_dataout <= wire_n0lil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0O1li_dataout <= n0l01ili WHEN niOlllO0l = '1' ELSE wire_n0l0O00i_dataout; + wire_n0l0O1ll_dataout <= n0l01ill WHEN niOlllO0l = '1' ELSE wire_n0l0O00l_dataout; + wire_n0l0O1lO_dataout <= n0l01ilO WHEN niOlllO0l = '1' ELSE wire_n0l0O00O_dataout; + wire_n0l0O1O_dataout <= wire_n0lilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0O1Oi_dataout <= n0l01iOi WHEN niOlllO0l = '1' ELSE wire_n0l0O0ii_dataout; + wire_n0l0O1Ol_dataout <= n0l01iOl WHEN niOlllO0l = '1' ELSE wire_n0l0O0il_dataout; + wire_n0l0O1OO_dataout <= n0l01iOO WHEN niOlllO0l = '1' ELSE wire_n0l0O0iO_dataout; + wire_n0l0Oi0i_dataout <= n0l01l1i OR niOlllOii; + wire_n0l0Oi0l_dataout <= n0l01l1l OR niOlllOii; + wire_n0l0Oi1i_dataout <= n0l01iOi OR niOlllOii; + wire_n0l0Oi1l_dataout <= n0l01iOl OR niOlllOii; + wire_n0l0Oi1O_dataout <= n0l01iOO OR niOlllOii; + wire_n0l0Oii_dataout <= wire_n0lilll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0Oil_dataout <= wire_n0lillO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0OiO_dataout <= wire_n0lilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0Ol0i_dataout <= wire_n0l0Olli_dataout AND NOT(niOllO10i); + wire_n0l0Ol0l_dataout <= wire_n0l0Olll_dataout AND NOT(niOllO10i); + wire_n0l0Ol0O_dataout <= wire_n0l0OllO_dataout AND NOT(niOllO10i); + wire_n0l0Ol1O_dataout <= wire_n0l0OliO_dataout AND NOT(niOllO10i); + wire_n0l0Oli_dataout <= wire_n0lilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0Olii_dataout <= wire_n0l0OlOi_dataout AND NOT(niOllO10i); + wire_n0l0Olil_dataout <= wire_n0l0OlOl_dataout AND NOT(niOllO10i); + wire_n0l0OliO_dataout <= wire_n0l0OlOO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01lll; + wire_n0l0Oll_dataout <= wire_n0lilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0Olli_dataout <= wire_n0l0OO1i_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01llO; + wire_n0l0Olll_dataout <= wire_n0l0OO1l_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01lOi; + wire_n0l0OllO_dataout <= wire_n0l0OO1O_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01lOl; + wire_n0l0OlO_dataout <= wire_n0liO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0OlOi_dataout <= wire_n0l0OO0i_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01lOO; + wire_n0l0OlOl_dataout <= wire_n0l0OO0l_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0l01O1i; + wire_n0l0OlOO_dataout <= wire_n0l0OO0O_o(0) WHEN niOllO11O = '1' ELSE n0l01lll; + wire_n0l0OO0i_dataout <= wire_n0l0OO0O_o(4) WHEN niOllO11O = '1' ELSE n0l01lOO; + wire_n0l0OO0l_dataout <= wire_n0l0OO0O_o(5) WHEN niOllO11O = '1' ELSE n0l01O1i; + wire_n0l0OO1i_dataout <= wire_n0l0OO0O_o(1) WHEN niOllO11O = '1' ELSE n0l01llO; + wire_n0l0OO1l_dataout <= wire_n0l0OO0O_o(2) WHEN niOllO11O = '1' ELSE n0l01lOi; + wire_n0l0OO1O_dataout <= wire_n0l0OO0O_o(3) WHEN niOllO11O = '1' ELSE n0l01lOl; + wire_n0l0OOi_dataout <= wire_n0liO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0OOl_dataout <= wire_n0liO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l0OOll_dataout <= wire_n0l0OOlO_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13372w(0) AND wire_w_lg_niOllO1ii13373w(0)); + wire_n0l0OOlO_dataout <= n0l01O1l AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOllO1il13381w(0))); + wire_n0l0OOO_dataout <= wire_n0liO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1000i_dataout <= n0l10OOi WHEN n0l10llO = '1' ELSE n0iOO00l; + wire_n0l1000l_dataout <= n0l10OOl WHEN n0l10llO = '1' ELSE n0iOO00O; + wire_n0l1000O_dataout <= n0l10OOO WHEN n0l10llO = '1' ELSE n0iOO0ii; + wire_n0l1001i_dataout <= n0l10Oli WHEN n0l10llO = '1' ELSE n0iOO01l; + wire_n0l1001l_dataout <= n0l10Oll WHEN n0l10llO = '1' ELSE n0iOO01O; + wire_n0l1001O_dataout <= n0l10OlO WHEN n0l10llO = '1' ELSE n0iOO00i; + wire_n0l100i_dataout <= n0il1lO AND NOT(wire_niO01O0O_dataout); + wire_n0l100ii_dataout <= n0l1i11i WHEN n0l10llO = '1' ELSE n0iOO0il; + wire_n0l100il_dataout <= n0l1i11l WHEN n0l10llO = '1' ELSE n0iOO0iO; + wire_n0l100iO_dataout <= n0l1i11O WHEN n0l10llO = '1' ELSE n0iOO0li; + wire_n0l100l_dataout <= n0il1Oi AND NOT(wire_niO01O0O_dataout); + wire_n0l100li_dataout <= n0l1i10i WHEN n0l10llO = '1' ELSE n0iOO0ll; + wire_n0l100ll_dataout <= n0l1i10l WHEN n0l10llO = '1' ELSE n0iOO0lO; + wire_n0l100lO_dataout <= n0l1i10O WHEN n0l10llO = '1' ELSE n0iOO0Oi; + wire_n0l100O_dataout <= n0il1Ol AND NOT(wire_niO01O0O_dataout); + wire_n0l100Oi_dataout <= n0l1i1ii WHEN n0l10llO = '1' ELSE n0iOO0Ol; + wire_n0l100Ol_dataout <= n0l1i1il WHEN n0l10llO = '1' ELSE n0iOO0OO; + wire_n0l100OO_dataout <= n0l1i1iO WHEN n0l10llO = '1' ELSE n0iOOi1i; + wire_n0l1010i_dataout <= n0l10lli WHEN n0l10llO = '1' ELSE n0iOlOli; + wire_n0l1010l_dataout <= n0l10lOl WHEN n0l10llO = '1' ELSE n0iOO10O; + wire_n0l1010O_dataout <= n0l10lOO WHEN n0l10llO = '1' ELSE n0iOO1ii; + wire_n0l1011i_dataout <= wire_n0l10iii_dataout AND NOT(niOlO1O0i); + wire_n0l1011l_dataout <= n0iOOiiO WHEN n0l10llO = '1' ELSE n0iOliil; + wire_n0l1011O_dataout <= n0l10liO WHEN n0l10llO = '1' ELSE n0iOlOiO; + wire_n0l101i_dataout <= wire_n0lO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l101ii_dataout <= n0l10O1i WHEN n0l10llO = '1' ELSE n0iOO1il; + wire_n0l101il_dataout <= n0l10O1l WHEN n0l10llO = '1' ELSE n0iOO1iO; + wire_n0l101iO_dataout <= n0l10O1O WHEN n0l10llO = '1' ELSE n0iOO1li; + wire_n0l101l_dataout <= n0il1li AND NOT(wire_niO01O0O_dataout); + wire_n0l101li_dataout <= n0l10O0i WHEN n0l10llO = '1' ELSE n0iOO1ll; + wire_n0l101ll_dataout <= n0l10O0l WHEN n0l10llO = '1' ELSE n0iOO1lO; + wire_n0l101lO_dataout <= n0l10O0O WHEN n0l10llO = '1' ELSE n0iOO1Oi; + wire_n0l101O_dataout <= n0il1ll AND NOT(wire_niO01O0O_dataout); + wire_n0l101Oi_dataout <= n0l10Oii WHEN n0l10llO = '1' ELSE n0iOO1Ol; + wire_n0l101Ol_dataout <= n0l10Oil WHEN n0l10llO = '1' ELSE n0iOO1OO; + wire_n0l101OO_dataout <= n0l10OiO WHEN n0l10llO = '1' ELSE n0iOO01i; + wire_n0l10i0i_dataout <= n0l1i1Oi WHEN n0l10llO = '1' ELSE n0iOOi0l; + wire_n0l10i0l_dataout <= n0l1i1Ol WHEN n0l10llO = '1' ELSE n0iOOi0O; + wire_n0l10i0O_dataout <= n0l1i1OO WHEN n0l10llO = '1' ELSE n0iOOiii; + wire_n0l10i1i_dataout <= n0l1i1li WHEN n0l10llO = '1' ELSE n0iOOi1l; + wire_n0l10i1l_dataout <= n0l1i1ll WHEN n0l10llO = '1' ELSE n0iOOi1O; + wire_n0l10i1O_dataout <= n0l1i1lO WHEN n0l10llO = '1' ELSE n0iOOi0i; + wire_n0l10ii_dataout <= n0il1OO AND NOT(wire_niO01O0O_dataout); + wire_n0l10iii_dataout <= n0l1i01i WHEN n0l10llO = '1' ELSE n0iOOiil; + wire_n0l10il_dataout <= n0il01i AND NOT(wire_niO01O0O_dataout); + wire_n0l10iO_dataout <= n0il01l AND NOT(wire_niO01O0O_dataout); + wire_n0l10li_dataout <= n0il01O AND NOT(wire_niO01O0O_dataout); + wire_n0l10ll_dataout <= wire_n0lO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l10lO_dataout <= wire_n0lO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l10Oi_dataout <= wire_n0lO1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l10Ol_dataout <= wire_n0lO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l10OO_dataout <= wire_n0lO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1100i_dataout <= wire_n0l110lO_dataout OR niOlll1Oi; + wire_n0l1100l_dataout <= wire_n0l110Oi_dataout AND NOT(niOlll1Oi); + wire_n0l1100O_dataout <= wire_n0l110Ol_dataout AND NOT(niOlll1Oi); + wire_n0l1101i_dataout <= wire_n0l110iO_dataout AND NOT(niOlll1Ol); + wire_n0l1101l_dataout <= wire_n0l110li_dataout AND NOT(niOlll1Ol); + wire_n0l1101O_dataout <= wire_n0l110ll_dataout AND NOT(niOlll1Ol); + wire_n0l110ii_dataout <= wire_n0l110OO_dataout AND NOT(niOlll1Oi); + wire_n0l110il_dataout <= wire_n0l11i1i_dataout AND NOT(niOlll1Oi); + wire_n0l110iO_dataout <= wire_n0l11i1l_dataout AND NOT(niOlll1Oi); + wire_n0l110li_dataout <= wire_n0l11i1O_dataout AND NOT(niOlll1Oi); + wire_n0l110ll_dataout <= wire_n0l11i0i_dataout AND NOT(niOlll1Oi); + wire_n0l110lO_dataout <= wire_n0l11i0l_o(0) WHEN niOlll1ll = '1' ELSE n0iOlOOi; + wire_n0l110Oi_dataout <= wire_n0l11i0l_o(1) WHEN niOlll1ll = '1' ELSE n0iOlOOl; + wire_n0l110Ol_dataout <= wire_n0l11i0l_o(2) WHEN niOlll1ll = '1' ELSE n0iOlOOO; + wire_n0l110OO_dataout <= wire_n0l11i0l_o(3) WHEN niOlll1ll = '1' ELSE n0iOO11i; + wire_n0l1110i_dataout <= wire_n0l11l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1110l_dataout <= wire_n0l11l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1110O_dataout <= wire_n0l11l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1111i_dataout <= wire_n0l11OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1111l_dataout <= wire_n0l11l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1111O_dataout <= wire_n0l11l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l111ii_dataout <= wire_n0l11l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l111il_dataout <= wire_n0l11lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l111iO_dataout <= wire_n0l11lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l111li_dataout <= wire_n0l1011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l111ll_dataout <= wire_n0l1100i_dataout AND NOT(niOlll1Ol); + wire_n0l111lO_dataout <= wire_n0l1100l_dataout AND NOT(niOlll1Ol); + wire_n0l111Oi_dataout <= wire_n0l1100O_dataout AND NOT(niOlll1Ol); + wire_n0l111Ol_dataout <= wire_n0l110ii_dataout AND NOT(niOlll1Ol); + wire_n0l111OO_dataout <= wire_n0l110il_dataout AND NOT(niOlll1Ol); + wire_n0l11i0i_dataout <= wire_n0l11i0l_o(7) WHEN niOlll1ll = '1' ELSE n0iOO10l; + wire_n0l11i1i_dataout <= wire_n0l11i0l_o(4) WHEN niOlll1ll = '1' ELSE n0iOO11l; + wire_n0l11i1l_dataout <= wire_n0l11i0l_o(5) WHEN niOlll1ll = '1' ELSE n0iOO11O; + wire_n0l11i1O_dataout <= wire_n0l11i0l_o(6) WHEN niOlll1ll = '1' ELSE n0iOO10i; + wire_n0l11ill_dataout <= n0iOO0iO WHEN niOlO1O0i = '1' ELSE wire_n0l100il_dataout; + wire_n0l11ilO_dataout <= n0iOO0li WHEN niOlO1O0i = '1' ELSE wire_n0l100iO_dataout; + wire_n0l11iOi_dataout <= n0iOO0ll WHEN niOlO1O0i = '1' ELSE wire_n0l100li_dataout; + wire_n0l11iOl_dataout <= n0iOO0lO WHEN niOlO1O0i = '1' ELSE wire_n0l100ll_dataout; + wire_n0l11iOO_dataout <= n0iOO0Oi WHEN niOlO1O0i = '1' ELSE wire_n0l100lO_dataout; + wire_n0l11l0i_dataout <= n0iOOi1O WHEN niOlO1O0i = '1' ELSE wire_n0l10i1l_dataout; + wire_n0l11l0l_dataout <= n0iOOi0i WHEN niOlO1O0i = '1' ELSE wire_n0l10i1O_dataout; + wire_n0l11l0O_dataout <= n0iOOi0l WHEN niOlO1O0i = '1' ELSE wire_n0l10i0i_dataout; + wire_n0l11l1i_dataout <= n0iOO0OO WHEN niOlO1O0i = '1' ELSE wire_n0l100Ol_dataout; + wire_n0l11l1l_dataout <= n0iOOi1i WHEN niOlO1O0i = '1' ELSE wire_n0l100OO_dataout; + wire_n0l11l1O_dataout <= n0iOOi1l WHEN niOlO1O0i = '1' ELSE wire_n0l10i1i_dataout; + wire_n0l11lii_dataout <= n0iOOi0O WHEN niOlO1O0i = '1' ELSE wire_n0l10i0l_dataout; + wire_n0l11lil_dataout <= n0iOOiii WHEN niOlO1O0i = '1' ELSE wire_n0l10i0O_dataout; + wire_n0l11liO_dataout <= wire_n0l1011l_dataout AND NOT(niOlO1O0i); + wire_n0l11lli_dataout <= wire_n0l1011O_dataout AND NOT(niOlO1O0i); + wire_n0l11lll_dataout <= wire_n0l1010i_dataout AND NOT(niOlO1O0i); + wire_n0l11llO_dataout <= wire_n0l1010l_dataout AND NOT(niOlO1O0i); + wire_n0l11lOi_dataout <= wire_n0l1010O_dataout AND NOT(niOlO1O0i); + wire_n0l11lOl_dataout <= wire_n0l101ii_dataout AND NOT(niOlO1O0i); + wire_n0l11lOO_dataout <= wire_n0l101il_dataout AND NOT(niOlO1O0i); + wire_n0l11O0i_dataout <= wire_n0l101lO_dataout AND NOT(niOlO1O0i); + wire_n0l11O0l_dataout <= wire_n0l101Oi_dataout AND NOT(niOlO1O0i); + wire_n0l11O0O_dataout <= wire_n0l101Ol_dataout AND NOT(niOlO1O0i); + wire_n0l11O1i_dataout <= wire_n0l101iO_dataout AND NOT(niOlO1O0i); + wire_n0l11O1l_dataout <= wire_n0l101li_dataout AND NOT(niOlO1O0i); + wire_n0l11O1O_dataout <= wire_n0l101ll_dataout AND NOT(niOlO1O0i); + wire_n0l11Oi_dataout <= n0il10O AND NOT(wire_niO01O0O_dataout); + wire_n0l11Oii_dataout <= wire_n0l101OO_dataout AND NOT(niOlO1O0i); + wire_n0l11Oil_dataout <= wire_n0l1001i_dataout AND NOT(niOlO1O0i); + wire_n0l11OiO_dataout <= wire_n0l1001l_dataout AND NOT(niOlO1O0i); + wire_n0l11Ol_dataout <= n0il1ii AND NOT(wire_niO01O0O_dataout); + wire_n0l11Oli_dataout <= wire_n0l1001O_dataout AND NOT(niOlO1O0i); + wire_n0l11Oll_dataout <= wire_n0l1000i_dataout AND NOT(niOlO1O0i); + wire_n0l11OlO_dataout <= wire_n0l1000l_dataout AND NOT(niOlO1O0i); + wire_n0l11OO_dataout <= n0il1il AND NOT(wire_niO01O0O_dataout); + wire_n0l11OOi_dataout <= wire_n0l1000O_dataout AND NOT(niOlO1O0i); + wire_n0l11OOl_dataout <= wire_n0l100ii_dataout AND NOT(niOlO1O0i); + wire_n0l11OOO_dataout <= wire_n0l100Oi_dataout AND NOT(niOlO1O0i); + wire_n0l1i0i_dataout <= wire_n0llOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1i0ii_dataout <= wire_n0l1li1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0il_dataout <= wire_n0l1l0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0iO_dataout <= wire_n0l1li1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0l_dataout <= wire_n0llOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1i0li_dataout <= ((wire_w_lg_niOllliOi13760w(0) AND (wire_w_lg_niOllli1O13761w(0) AND wire_w_lg_w_lg_niOllll1l13624w13762w(0))) AND (wire_w_lg_w_lg_w_lg_niOlll00i13765w13769w13770w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0ll_dataout <= (wire_w_lg_w_lg_w_lg_niOlll0OO13754w13756w13757w(0) AND wire_niO01ill_w_lg_n0l10lOi13758w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0lO_dataout <= wire_n0l1l11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0O_dataout <= wire_n0llOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1i0Oi_dataout <= wire_n0l1l0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0Ol_dataout <= wire_n0l1l0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1i0OO_dataout <= wire_n0l1l0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1i1i_dataout <= wire_n0lO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1i1l_dataout <= wire_n0lO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1i1O_dataout <= wire_n0lO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1ii0i_dataout <= wire_n0l1l0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ii0l_dataout <= wire_n0l1li0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ii0O_dataout <= wire_n0l1liii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ii1i_dataout <= wire_n0l1l0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ii1l_dataout <= wire_n0l1l0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ii1O_dataout <= wire_n0l1l0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iii_dataout <= wire_n0lO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1iiii_dataout <= wire_n0l1liil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iiil_dataout <= wire_n0l1liiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iiiO_dataout <= wire_n0l1lili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iil_dataout <= wire_n0lO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1iili_dataout <= wire_n0l1lill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iill_dataout <= wire_n0l1lilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iilO_dataout <= wire_n0l1liOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iiO_dataout <= wire_n0lO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1iiOi_dataout <= wire_n0l1li1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iiOl_dataout <= wire_n0l1li0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iiOO_dataout <= wire_n0l1li0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1il0i_dataout <= wire_n0l1ll1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1il0l_dataout <= wire_n0l1ll1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1il0O_dataout <= wire_n0l1ll0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1il1i_dataout <= wire_n0l1liOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1il1l_dataout <= wire_n0l1liOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1il1O_dataout <= wire_n0l1ll1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ili_dataout <= wire_n0lO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1ilii_dataout <= wire_n0l1ll0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ilil_dataout <= wire_n0l1ll0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iliO_dataout <= wire_n0l1llii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ill_dataout <= wire_n0lO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1illi_dataout <= wire_n0l1llil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1illl_dataout <= wire_n0l1lliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1illO_dataout <= wire_n0l1llli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ilO_dataout <= wire_n0ll1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1ilOi_dataout <= wire_n0l1llll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ilOl_dataout <= wire_n0l1lllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1ilOO_dataout <= wire_n0l1llOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1iO0i_dataout <= wire_n0l1lO1l_dataout OR wire_niO01lOO_dataout; + wire_n0l1iO1i_dataout <= wire_n0l1llOl_dataout OR wire_niO01lOO_dataout; + wire_n0l1iO1l_dataout <= wire_n0l1llOO_dataout OR wire_niO01lOO_dataout; + wire_n0l1iO1O_dataout <= wire_n0l1lO1i_dataout OR wire_niO01lOO_dataout; + wire_n0l1iOi_dataout <= wire_n0ll1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1iOl_dataout <= wire_n0ll1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1iOO_dataout <= wire_n0ll1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1l0i_dataout <= wire_n0ll01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1l0ii_dataout <= niOlll0lO WHEN wire_n0l1l0li_o = '1' ELSE n0l10lOl; + wire_n0l1l0il_dataout <= niOlll0OO WHEN wire_n0l1l0li_o = '1' ELSE n0l10lOO; + wire_n0l1l0iO_dataout <= (wire_niO11O1l_dataout AND (niOlll0Ol OR niOllli1l)) WHEN wire_n0l1l0li_o = '1' ELSE n0l10O1i; + wire_n0l1l0l_dataout <= wire_n0ll01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1l0ll_dataout <= wire_niO11Oil_dataout WHEN niOlll00l = '1' ELSE n0l10liO; + wire_n0l1l0lO_dataout <= wire_niO11O0i_dataout WHEN niOlll00l = '1' ELSE n0l10O1l; + wire_n0l1l0O_dataout <= wire_n0ll01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1l0Oi_dataout <= wire_niO11O0l_dataout WHEN niOlll00l = '1' ELSE n0l10O1O; + wire_n0l1l0Ol_dataout <= wire_niO11O0O_dataout WHEN niOlll00l = '1' ELSE n0l10O0i; + wire_n0l1l0OO_dataout <= wire_niO11Oii_dataout WHEN niOlll00l = '1' ELSE n0l10O0l; + wire_n0l1l10i_dataout <= wire_n0l1l10l_dataout OR (wire_w_lg_niOlllill13743w(0) AND wire_w_lg_w_lg_niOlllili13732w13744w(0)); + wire_n0l1l10l_dataout <= wire_n0l1l10O_dataout OR (wire_w_lg_niOlllili13732w(0) AND (wire_w_lg_w_lg_niOlll0ii13734w13735w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n0l1i00l13737w13739w13740w(0))); + wire_n0l1l10O_dataout <= wire_n0l1l1ii_dataout OR (wire_w_lg_niOlllili13732w(0) AND niOlll00O); + wire_n0l1l11O_dataout <= wire_n0l1l10i_dataout AND NOT(niOllli1O); + wire_n0l1l1i_dataout <= wire_n0ll1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1l1ii_dataout <= n0l10lOi OR (wire_n0l1l1Ol_o AND (((niOlll0OO XOR n0l10lOO) OR (niOlll0lO XOR n0l10lOl)) OR (NOT (n0l10lOO XOR n0l10lOl)))); + wire_n0l1l1l_dataout <= wire_n0ll1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1l1O_dataout <= wire_n0ll1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1li0i_dataout <= wire_niO11O0O_dataout WHEN niOlll00O = '1' ELSE n0l10OOO; + wire_n0l1li0l_dataout <= n0l1i11i AND NOT(niOlll00O); + wire_n0l1li0O_dataout <= wire_niO11O0i_dataout WHEN niOlll0ii = '1' ELSE n0l10O0O; + wire_n0l1li1i_dataout <= wire_niO11Oll_dataout WHEN niOlll00O = '1' ELSE n0l10lli; + wire_n0l1li1l_dataout <= wire_niO11Oli_dataout WHEN niOlll00O = '1' ELSE n0iOOiiO; + wire_n0l1li1O_dataout <= wire_niO11O0l_dataout WHEN niOlll00O = '1' ELSE n0l10OOl; + wire_n0l1lii_dataout <= wire_n0ll00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1liii_dataout <= wire_niO11O0l_dataout WHEN niOlll0ii = '1' ELSE n0l10Oii; + wire_n0l1liil_dataout <= wire_niO11O0O_dataout WHEN niOlll0ii = '1' ELSE n0l10Oil; + wire_n0l1liiO_dataout <= wire_niO11Oii_dataout WHEN niOlll0ii = '1' ELSE n0l10OiO; + wire_n0l1lil_dataout <= wire_n0ll00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1lili_dataout <= wire_niO11Oil_dataout WHEN niOlll0ii = '1' ELSE n0l10Oli; + wire_n0l1lill_dataout <= wire_niO11OiO_dataout WHEN niOlll0ii = '1' ELSE n0l10Oll; + wire_n0l1lilO_dataout <= wire_niO11Oli_dataout WHEN niOlll0ii = '1' ELSE n0l10OlO; + wire_n0l1liO_dataout <= wire_n0ll00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1liOi_dataout <= wire_niO11Oll_dataout WHEN niOlll0ii = '1' ELSE n0l10OOi; + wire_n0l1liOl_dataout <= wire_niO11O0i_dataout WHEN niOlll0li = '1' ELSE n0l1i11l; + wire_n0l1liOO_dataout <= wire_niO11O0l_dataout WHEN niOlll0li = '1' ELSE n0l1i11O; + wire_n0l1ll0i_dataout <= niOlllill WHEN niOlll0li = '1' ELSE n0l1i1ii; + wire_n0l1ll0l_dataout <= wire_niO11O0i_dataout WHEN niOllli1O = '1' ELSE n0l1i1il; + wire_n0l1ll0O_dataout <= wire_niO11O0l_dataout WHEN niOllli1O = '1' ELSE n0l1i1iO; + wire_n0l1ll1i_dataout <= wire_niO11O0O_dataout WHEN niOlll0li = '1' ELSE n0l1i10i; + wire_n0l1ll1l_dataout <= wire_niO11Oii_dataout WHEN niOlll0li = '1' ELSE n0l1i10l; + wire_n0l1ll1O_dataout <= wire_niO11Oil_dataout WHEN niOlll0li = '1' ELSE n0l1i10O; + wire_n0l1lli_dataout <= wire_n0ll0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1llii_dataout <= wire_niO11O0O_dataout WHEN niOllli1O = '1' ELSE n0l1i1li; + wire_n0l1llil_dataout <= wire_niO11Oii_dataout WHEN niOllli1O = '1' ELSE n0l1i1ll; + wire_n0l1lliO_dataout <= wire_niO11Oil_dataout WHEN niOllli1O = '1' ELSE n0l1i1lO; + wire_n0l1lll_dataout <= wire_n0ll0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1llli_dataout <= wire_niO11OiO_dataout WHEN niOllli1O = '1' ELSE n0l1i1Oi; + wire_n0l1llll_dataout <= wire_niO11Oli_dataout WHEN niOllli1O = '1' ELSE n0l1i1Ol; + wire_n0l1lllO_dataout <= wire_niO11Oll_dataout WHEN niOllli1O = '1' ELSE n0l1i1OO; + wire_n0l1llO_dataout <= wire_n0ll0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1llOi_dataout <= niOlllill WHEN niOllli1O = '1' ELSE n0l1i01i; + wire_n0l1llOl_dataout <= wire_n0l1lO1O_dataout OR niOllli1O; + wire_n0l1llOO_dataout <= wire_n0l1lO0i_dataout AND NOT(niOllli1O); + wire_n0l1lO0i_dataout <= wire_n0l1lOil_dataout WHEN wire_w_lg_niOlll0il13694w(0) = '1' ELSE n0l1i01O; + wire_n0l1lO0l_dataout <= wire_n0l1lOiO_dataout WHEN wire_w_lg_niOlll0il13694w(0) = '1' ELSE n0l1i00i; + wire_n0l1lO0O_dataout <= wire_n0l1lOli_dataout WHEN wire_w_lg_niOlll0il13694w(0) = '1' ELSE n0l1i00l; + wire_n0l1lO1i_dataout <= wire_n0l1lO0l_dataout OR niOllli1O; + wire_n0l1lO1l_dataout <= wire_n0l1lO0O_dataout OR niOllli1O; + wire_n0l1lO1O_dataout <= wire_n0l1lOii_dataout WHEN wire_w_lg_niOlll0il13694w(0) = '1' ELSE n0l1i01l; + wire_n0l1lOi_dataout <= wire_n0ll0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1lOii_dataout <= wire_n0l1lOll_o(1) AND niOlll0iO; + wire_n0l1lOil_dataout <= wire_n0l1lOll_o(2) AND niOlll0iO; + wire_n0l1lOiO_dataout <= wire_n0l1lOll_o(3) AND niOlll0iO; + wire_n0l1lOl_dataout <= wire_n0ll0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1lOli_dataout <= wire_n0l1lOll_o(4) AND niOlll0iO; + wire_n0l1lOO_dataout <= wire_n0ll0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1O0i_dataout <= wire_n0lli1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1O0il_dataout <= wire_n0l1O0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1O0iO_dataout <= wire_n0l1O0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1O0l_dataout <= wire_n0lli1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1O0li_dataout <= wire_n0l1O0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1O0ll_dataout <= wire_n0l1O0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0l1O0lO_dataout <= wire_n0l1Oi1i_dataout AND NOT(niOllli0i); + wire_n0l1O0O_dataout <= wire_n0lli1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1O0Oi_dataout <= wire_n0l1Oi1l_dataout AND NOT(niOllli0i); + wire_n0l1O0Ol_dataout <= wire_n0l1Oi1O_dataout AND NOT(niOllli0i); + wire_n0l1O0OO_dataout <= wire_n0l1Oi0i_dataout AND NOT(niOllli0i); + wire_n0l1O1i_dataout <= wire_n0ll0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1O1l_dataout <= wire_n0ll0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1O1O_dataout <= wire_n0ll0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1Oi0i_dataout <= wire_n0l1Oi0l_o(3) OR NOT(wire_niO01ill_w_lg_n0l1O00O13650w(0)); + wire_n0l1Oi1i_dataout <= wire_n0l1Oi0l_o(0) WHEN wire_niO01ill_w_lg_n0l1O00O13650w(0) = '1' ELSE n0l1i00O; + wire_n0l1Oi1l_dataout <= wire_n0l1Oi0l_o(1) WHEN wire_niO01ill_w_lg_n0l1O00O13650w(0) = '1' ELSE n0l1O00i; + wire_n0l1Oi1O_dataout <= wire_n0l1Oi0l_o(2) WHEN wire_niO01ill_w_lg_n0l1O00O13650w(0) = '1' ELSE n0l1O00l; + wire_n0l1Oii_dataout <= wire_n0lli0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1Oil_dataout <= wire_n0lli0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1OiO_dataout <= wire_n0lli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1Ol0i_dataout <= (wire_w_lg_w_lg_w_lg_niOllliOO13621w13622w13623w(0) OR (wire_w_lg_niOllll1l13624w(0) AND (wire_w_lg_niOllliOO13625w(0) AND (n0l1OilO AND niOllli0O)))) AND NOT(wire_niO01lOO_dataout); + wire_n0l1Ol0l_dataout <= niOllliiO AND NOT(wire_niO01lOO_dataout); + wire_n0l1Ol0O_dataout <= (niOllliOO AND n0l1OiOO) AND NOT(wire_niO01lOO_dataout); + wire_n0l1Ol1l_dataout <= (niOllll1l AND n0l1Oiil) AND NOT(wire_niO01lOO_dataout); + wire_n0l1Ol1O_dataout <= (niOllll1l AND n0l1OiiO) AND NOT(wire_niO01lOO_dataout); + wire_n0l1Oli_dataout <= wire_n0lliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1Olii_dataout <= n0l1OilO AND NOT(wire_niO01lOO_dataout); + wire_n0l1Olil_dataout <= niOllliOO AND NOT(wire_niO01lOO_dataout); + wire_n0l1OliO_dataout <= n0l1OiOl AND NOT(wire_niO01lOO_dataout); + wire_n0l1Oll_dataout <= wire_n0lliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1Olli_dataout <= n0l1OiOO AND NOT(wire_niO01lOO_dataout); + wire_n0l1Olll_dataout <= niOllll1l AND NOT(wire_niO01lOO_dataout); + wire_n0l1OlO_dataout <= wire_n0lliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1OOi_dataout <= wire_n0llili_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1OOl_dataout <= wire_n0llill_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0l1OOO_dataout <= wire_n0llilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li00i_dataout <= wire_n0ll1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li00l_dataout <= wire_n0lO1OO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iO0iO; + wire_n0li00O_dataout <= wire_n0lO01i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iO0li; + wire_n0li011i_dataout <= k_cnt(60) AND NOT(wire_n0li010i_o); + wire_n0li011l_dataout <= k_cnt(61) AND NOT(wire_n0li010i_o); + wire_n0li011O_dataout <= k_cnt(62) AND NOT(wire_n0li010i_o); + wire_n0li01i_dataout <= wire_n0ll10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li01l_dataout <= wire_n0ll10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li01O_dataout <= wire_n0ll1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li0i0l_dataout <= n0O1iO0i WHEN niOllO1ll = '1' ELSE (n0O1iO0i XOR n0li0lOi); + wire_n0li0i1l_dataout <= n0O1iO0l WHEN niOllO1ll = '1' ELSE (n0O1iO0l XOR n0li0llO); + wire_n0li0ii_dataout <= wire_n0lO01l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iO0ll; + wire_n0li0iii_dataout <= n0O1iO1O WHEN niOllO1ll = '1' ELSE (n0O1iO1O XOR n0li0lOl); + wire_n0li0il_dataout <= wire_n0lO01O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iO0lO; + wire_n0li0ili_dataout <= n0O1iO1l WHEN niOllO1ll = '1' ELSE (n0O1iO1l XOR n0li0lOO); + wire_n0li0ilO_dataout <= n0O1iO1i WHEN niOllO1ll = '1' ELSE (n0O1iO1i XOR n0li0O1i); + wire_n0li0iO_dataout <= wire_n0lO00i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iO0Oi; + wire_n0li0iOl_dataout <= n0O1ilOO WHEN niOllO1ll = '1' ELSE (n0O1ilOO XOR n0li0O1l); + wire_n0li0l1i_dataout <= n0O1ilOl WHEN niOllO1ll = '1' ELSE (n0O1ilOl XOR n0li0O1O); + wire_n0li0l1O_dataout <= n0O1ilOi WHEN niOllO1ll = '1' ELSE (n0O1ilOi XOR n0li0O0i); + wire_n0li0li_dataout <= wire_n0lO00l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iO0Ol; + wire_n0li0ll_dataout <= wire_n0lO00O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iO0OO; + wire_n0li0lO_dataout <= wire_n0lO0ii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOi1i; + wire_n0li0O0O_dataout <= wire_n0lii1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0Oi_dataout <= wire_n0lO0il_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOi1l; + wire_n0li0Oii_dataout <= wire_n0lii1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0Oil_dataout <= wire_n0lii1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0OiO_dataout <= wire_n0lii1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0Ol_dataout <= wire_n0lO0iO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOi1O; + wire_n0li0Oli_dataout <= wire_n0lii1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0Oll_dataout <= wire_n0lii1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0OlO_dataout <= wire_n0lii1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0OO_dataout <= wire_n0lO0li_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOi0i; + wire_n0li0OOi_dataout <= wire_n0lii1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0OOl_dataout <= wire_n0lii1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li0OOO_dataout <= wire_n0lii01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li100i_dataout <= wire_n0li1iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li100l_dataout <= wire_n0li1ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li100O_dataout <= n0li110l AND NOT(wire_niO01lOO_dataout); + wire_n0li101l_dataout <= wire_n0li1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li101O_dataout <= wire_n0li1ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li10i_dataout <= wire_n0liOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li10ii_dataout <= nlOllOlOi AND NOT(wire_niO01lOO_dataout); + wire_n0li10il_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13377w(0) AND wire_w_lg_niOllO10l13378w(0)) AND wire_niO01ill_w_lg_n0li111O13375w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0li10iO_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w13372w(0) AND wire_w_lg_niOllO1ii13373w(0)) AND wire_niO01ill_w_lg_n0li111O13375w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0li10l_dataout <= wire_n0liOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li10li_dataout <= wire_n0li1iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li10ll_dataout <= wire_n0li1l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li10lO_dataout <= wire_n0li1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li10O_dataout <= wire_n0liOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li10Oi_dataout <= wire_n0li1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li10Ol_dataout <= wire_n0li1l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li10OO_dataout <= wire_n0li1l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li11i_dataout <= wire_n0liO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li11l_dataout <= wire_n0liO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li11O_dataout <= wire_n0liOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1i1i_dataout <= wire_n0li1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li1i1l_dataout <= wire_n0li1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li1i1O_dataout <= wire_n0li1liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0li1ii_dataout <= wire_n0liOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1il_dataout <= wire_n0liOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1ili_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0li111O; + wire_n0li1ill_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0l00iOO; + wire_n0li1ilO_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0li111i; + wire_n0li1iO_dataout <= wire_n0liOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1iOi_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0li111l; + wire_n0li1iOl_dataout <= wire_n1lllOii_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1iOO_dataout; + wire_n0li1iOO_dataout <= wire_n0li1l1i_dataout AND NOT(niOllO1li); + wire_n0li1l0i_dataout <= wire_n1llOi1O_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1llO_dataout; + wire_n0li1l0l_dataout <= wire_n1llOi0i_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1lOi_dataout; + wire_n0li1l0O_dataout <= wire_n1llOi0l_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1lOl_dataout; + wire_n0li1l1i_dataout <= n1l001OO AND NOT(niOllO1iO); + wire_n0li1l1l_dataout <= wire_n1llOi1i_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1lli_dataout; + wire_n0li1l1O_dataout <= wire_n1llOi1l_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1lll_dataout; + wire_n0li1li_dataout <= wire_n0liOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1lii_dataout <= wire_n1llOi0O_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1lOO_dataout; + wire_n0li1lil_dataout <= wire_n1llOiii_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1O1i_dataout; + wire_n0li1liO_dataout <= wire_n1llOiil_dataout WHEN n1lO0lOi = '1' ELSE wire_n0li1O1l_dataout; + wire_n0li1ll_dataout <= wire_n0liOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1lli_dataout <= wire_nlOO10OOi_dataout WHEN niOllO1li = '1' ELSE wire_n0li1O1O_dataout; + wire_n0li1lll_dataout <= wire_nlOO10OOl_dataout WHEN niOllO1li = '1' ELSE wire_n0li1O0i_dataout; + wire_n0li1llO_dataout <= wire_nlOO10OOO_dataout WHEN niOllO1li = '1' ELSE wire_n0li1O0l_dataout; + wire_n0li1lO_dataout <= wire_n0ll11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1lOi_dataout <= wire_nlOO1i11i_dataout WHEN niOllO1li = '1' ELSE wire_n0li1O0O_dataout; + wire_n0li1lOl_dataout <= wire_nlOO1i11l_dataout WHEN niOllO1li = '1' ELSE wire_n0li1Oii_dataout; + wire_n0li1lOO_dataout <= wire_nlOO1i11O_dataout WHEN niOllO1li = '1' ELSE wire_n0li1Oil_dataout; + wire_n0li1O0i_dataout <= n1101l1i WHEN niOllO1iO = '1' ELSE n1l001il; + wire_n0li1O0l_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOllO1iO = '1' ELSE n1l001iO; + wire_n0li1O0O_dataout <= n1l001li AND NOT(niOllO1iO); + wire_n0li1O1i_dataout <= wire_nlOO1i10i_dataout WHEN niOllO1li = '1' ELSE wire_n0li1OiO_dataout; + wire_n0li1O1l_dataout <= wire_nlOO1i10l_dataout WHEN niOllO1li = '1' ELSE wire_n0li1Oli_dataout; + wire_n0li1O1O_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOllO1iO = '1' ELSE n1l001ii; + wire_n0li1Oi_dataout <= wire_n0ll11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1Oii_dataout <= n1l001ll AND NOT(niOllO1iO); + wire_n0li1Oil_dataout <= n1l001lO AND NOT(niOllO1iO); + wire_n0li1OiO_dataout <= n1l001Oi AND NOT(niOllO1iO); + wire_n0li1Ol_dataout <= wire_n0ll11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1Oli_dataout <= n1l001Ol AND NOT(niOllO1iO); + wire_n0li1OO_dataout <= wire_n0ll10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n0li1OOi_dataout <= k_cnt(57) AND NOT(wire_n0li010i_o); + wire_n0li1OOl_dataout <= k_cnt(58) AND NOT(wire_n0li010i_o); + wire_n0li1OOO_dataout <= k_cnt(59) OR wire_n0li010i_o; + wire_n0lii00i_dataout <= wire_n0liii0l_dataout OR niOllO1Oi; + wire_n0lii00l_dataout <= wire_n0liii0O_dataout OR niOllO1Oi; + wire_n0lii00O_dataout <= wire_n0liiiii_dataout OR niOllO1Oi; + wire_n0lii01i_dataout <= wire_n0liii1l_dataout OR niOllO1Oi; + wire_n0lii01l_dataout <= wire_n0liii1O_dataout OR niOllO1Oi; + wire_n0lii01O_dataout <= wire_n0liii0i_dataout OR niOllO1Oi; + wire_n0lii0i_dataout <= wire_n0lO0Ol_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOiil; + wire_n0lii0ii_dataout <= wire_n0liiiil_dataout OR niOllO1Oi; + wire_n0lii0il_dataout <= n0li0iiO WHEN niOllO1lO = '1' ELSE n0li0llO; + wire_n0lii0iO_dataout <= n0li0l0l WHEN niOllO1lO = '1' ELSE n0li0lOi; + wire_n0lii0l_dataout <= wire_n0lO0OO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOiiO; + wire_n0lii0li_dataout <= n0li0l0O WHEN niOllO1lO = '1' ELSE n0li0lOl; + wire_n0lii0ll_dataout <= n0li0lii WHEN niOllO1lO = '1' ELSE (n0li0lOO XOR n0li0llO); + wire_n0lii0lO_dataout <= n0li0lil WHEN niOllO1lO = '1' ELSE (n0li0llO XOR (n0li0O1i XOR n0li0lOi)); + wire_n0lii0O_dataout <= wire_n0lOi1i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOili; + wire_n0lii0Oi_dataout <= n0li0liO WHEN niOllO1lO = '1' ELSE (n0li0llO XOR (n0li0lOi XOR (n0li0O1l XOR n0li0lOl))); + wire_n0lii0Ol_dataout <= n0li0lli WHEN niOllO1lO = '1' ELSE (n0li0lOi XOR (n0li0lOl XOR (n0li0O1O XOR n0li0lOO))); + wire_n0lii0OO_dataout <= n0li0lll WHEN niOllO1lO = '1' ELSE (n0li0lOl XOR (n0li0lOO XOR (n0li0O0i XOR n0li0O1i))); + wire_n0lii10i_dataout <= wire_n0lii00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lii10l_dataout <= wire_n0lii00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lii10O_dataout <= wire_n0lii0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lii11i_dataout <= wire_n0lii01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lii11l_dataout <= wire_n0lii01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lii11O_dataout <= wire_n0lii00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lii1i_dataout <= wire_n0lO0ll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOi0l; + wire_n0lii1ii_dataout <= wire_n0lii0il_dataout OR niOllO1Oi; + wire_n0lii1il_dataout <= wire_n0lii0iO_dataout OR niOllO1Oi; + wire_n0lii1iO_dataout <= wire_n0lii0li_dataout OR niOllO1Oi; + wire_n0lii1l_dataout <= wire_n0lO0lO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOi0O; + wire_n0lii1li_dataout <= wire_n0lii0ll_dataout OR niOllO1Oi; + wire_n0lii1ll_dataout <= wire_n0lii0lO_dataout OR niOllO1Oi; + wire_n0lii1lO_dataout <= wire_n0lii0Oi_dataout OR niOllO1Oi; + wire_n0lii1O_dataout <= wire_n0lO0Oi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOiii; + wire_n0lii1Oi_dataout <= wire_n0lii0Ol_dataout OR niOllO1Oi; + wire_n0lii1Ol_dataout <= wire_n0lii0OO_dataout OR niOllO1Oi; + wire_n0lii1OO_dataout <= wire_n0liii1i_dataout OR niOllO1Oi; + wire_n0liii0i_dataout <= n0li0lOO WHEN niOllO1lO = '1' ELSE (n0li0O1O XOR (n0li0O0i XOR n0li0lii)); + wire_n0liii0l_dataout <= n0li0O1i WHEN niOllO1lO = '1' ELSE (n0li0O0i XOR n0li0lil); + wire_n0liii0O_dataout <= n0li0O1l WHEN niOllO1lO = '1' ELSE n0li0liO; + wire_n0liii1i_dataout <= n0li0llO WHEN niOllO1lO = '1' ELSE (n0li0lOO XOR (n0li0O1i XOR (n0li0O1l XOR n0li0iiO))); + wire_n0liii1l_dataout <= n0li0lOi WHEN niOllO1lO = '1' ELSE (n0li0O1i XOR (n0li0O1l XOR (n0li0O1O XOR n0li0l0l))); + wire_n0liii1O_dataout <= n0li0lOl WHEN niOllO1lO = '1' ELSE (n0li0O1l XOR (n0li0O1O XOR (n0li0O0i XOR n0li0l0O))); + wire_n0liiii_dataout <= wire_n0lOi1l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOill; + wire_n0liiiii_dataout <= n0li0O1O WHEN niOllO1lO = '1' ELSE n0li0lli; + wire_n0liiiil_dataout <= n0li0O0i WHEN niOllO1lO = '1' ELSE n0li0lll; + wire_n0liiil_dataout <= wire_n0lOi1O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOilO; + wire_n0liiili_dataout <= wire_n0liiill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0liiill_dataout <= wire_n0liiilO_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n0li0O0l) AND niOllO1Oi)); + wire_n0liiilO_dataout <= n0li0O0l OR n111i10i; + wire_n0liiiO_dataout <= wire_n0lOi0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOiOi; + wire_n0liili_dataout <= wire_n0lOi0l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOiOl; + wire_n0liill_dataout <= wire_n0lOi0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOiOO; + wire_n0liilO_dataout <= wire_n0lOiii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOl1i; + wire_n0liiOi_dataout <= wire_n0lOiil_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOl1l; + wire_n0liiOl_dataout <= wire_n0lOiiO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOl1O; + wire_n0liiOll_dataout <= wire_niO11lll_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11lll_dataout XOR n0lil00O); + wire_n0liiOll_w_lg_dataout13107w(0) <= NOT wire_n0liiOll_dataout; + wire_n0liiOO_dataout <= wire_n0lOili_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOl0i; + wire_n0liiOOl_dataout <= wire_niO11lli_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11lli_dataout XOR n0lil0ii); + wire_n0liiOOl_w_lg_dataout13105w(0) <= NOT wire_n0liiOOl_dataout; + wire_n0lil0i_dataout <= wire_n0lOiOl_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOlil; + wire_n0lil0l_dataout <= wire_n0lOiOO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOliO; + wire_n0lil0O_dataout <= wire_n0lOl1i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOlli; + wire_n0lil0Ol_dataout <= wire_n0liliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lil0OO_dataout <= wire_n0lill1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lil10i_dataout <= wire_niO11lil_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11lil_dataout XOR n0lil0iO); + wire_n0lil10i_w_lg_dataout13101w(0) <= NOT wire_n0lil10i_dataout; + wire_n0lil10O_dataout <= wire_niO11lii_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11lii_dataout XOR n0lil0li); + wire_n0lil10O_w_lg_dataout13099w(0) <= NOT wire_n0lil10O_dataout; + wire_n0lil11i_dataout <= wire_niO11liO_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11liO_dataout XOR n0lil0il); + wire_n0lil11i_w_lg_dataout13103w(0) <= NOT wire_n0lil11i_dataout; + wire_n0lil1i_dataout <= wire_n0lOill_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOl0l; + wire_n0lil1il_dataout <= wire_niO11l0O_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11l0O_dataout XOR n0lil0ll); + wire_n0lil1il_w_lg_dataout13097w(0) <= NOT wire_n0lil1il_dataout; + wire_n0lil1l_dataout <= wire_n0lOilO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOl0O; + wire_n0lil1li_dataout <= wire_niO11l0l_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11l0l_dataout XOR n0lil0lO); + wire_n0lil1li_w_lg_dataout13095w(0) <= NOT wire_n0lil1li_dataout; + wire_n0lil1lO_dataout <= wire_niO11l0i_dataout WHEN niOllO1Ol = '1' ELSE (wire_niO11l0i_dataout XOR n0lil0Oi); + wire_n0lil1lO_w_lg_dataout13093w(0) <= NOT wire_n0lil1lO_dataout; + wire_n0lil1O_dataout <= wire_n0lOiOi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOlii; + wire_n0lili0i_dataout <= wire_n0lill0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lili0l_dataout <= wire_n0lill0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lili0O_dataout <= wire_n0lillii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lili1i_dataout <= wire_n0lill1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lili1l_dataout <= wire_n0lill1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lili1O_dataout <= wire_n0lill0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lilii_dataout <= wire_n0lOl1l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOlll; + wire_n0liliii_dataout <= wire_n0lillil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0liliil_dataout <= wire_n0lilliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0liliiO_dataout <= wire_n0lillli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lilil_dataout <= wire_n0lOl1O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOllO; + wire_n0lilili_dataout <= wire_n0lillll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lilill_dataout <= wire_n0lilllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lililO_dataout <= wire_n0lillOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0liliO_dataout <= wire_n0lOl0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOlOi; + wire_n0liliOi_dataout <= wire_n0lillOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0liliOl_dataout <= wire_n0lillOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0liliOO_dataout <= wire_n0lilO1i_dataout OR niOllO1OO; + wire_n0lill0i_dataout <= wire_n0lilO0l_dataout OR niOllO1OO; + wire_n0lill0l_dataout <= wire_n0lilO0O_dataout OR niOllO1OO; + wire_n0lill0O_dataout <= wire_n0lilOii_dataout OR niOllO1OO; + wire_n0lill1i_dataout <= wire_n0lilO1l_dataout OR niOllO1OO; + wire_n0lill1l_dataout <= wire_n0lilO1O_dataout OR niOllO1OO; + wire_n0lill1O_dataout <= wire_n0lilO0i_dataout OR niOllO1OO; + wire_n0lilli_dataout <= wire_n0lOl0l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOlOl; + wire_n0lillii_dataout <= wire_n0lilOil_dataout OR niOllO1OO; + wire_n0lillil_dataout <= wire_n0lilOiO_dataout OR niOllO1OO; + wire_n0lilliO_dataout <= wire_n0lilOli_dataout OR niOllO1OO; + wire_n0lilll_dataout <= wire_n0lOl0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOlOO; + wire_n0lillli_dataout <= wire_n0lilOll_dataout OR niOllO1OO; + wire_n0lillll_dataout <= wire_n0lilOlO_dataout OR niOllO1OO; + wire_n0lilllO_dataout <= wire_n0lilOOi_dataout OR niOllO1OO; + wire_n0lillO_dataout <= wire_n0lOlii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOO1i; + wire_n0lillOi_dataout <= wire_n0lilOOl_dataout OR niOllO1OO; + wire_n0lillOl_dataout <= wire_n0lilOOO_dataout OR niOllO1OO; + wire_n0lillOO_dataout <= wire_n0liO11i_dataout OR niOllO1OO; + wire_n0lilO0i_dataout <= n0lil01i WHEN niOllO01i = '1' ELSE (n0lil0iO XOR n0lil00O); + wire_n0lilO0l_dataout <= n0lil01l WHEN niOllO01i = '1' ELSE (n0lil00O XOR (n0lil0li XOR n0lil0ii)); + wire_n0lilO0O_dataout <= n0lil01O WHEN niOllO01i = '1' ELSE (n0lil00O XOR (n0lil0ii XOR (n0lil0ll XOR n0lil0il))); + wire_n0lilO1i_dataout <= n0lil11O WHEN niOllO01i = '1' ELSE n0lil00O; + wire_n0lilO1l_dataout <= n0lil1Ol WHEN niOllO01i = '1' ELSE n0lil0ii; + wire_n0lilO1O_dataout <= n0lil1OO WHEN niOllO01i = '1' ELSE n0lil0il; + wire_n0lilOi_dataout <= wire_n0lOlil_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOO1l; + wire_n0lilOii_dataout <= n0lil00i WHEN niOllO01i = '1' ELSE (n0lil0ii XOR (n0lil0il XOR (n0lil0lO XOR n0lil0iO))); + wire_n0lilOil_dataout <= n0lil00l WHEN niOllO01i = '1' ELSE (n0lil0il XOR (n0lil0iO XOR (n0lil0Oi XOR n0lil0li))); + wire_n0lilOiO_dataout <= n0lil00O WHEN niOllO01i = '1' ELSE (n0lil0iO XOR (n0lil0li XOR (n0lil0ll XOR n0lil11O))); + wire_n0lilOl_dataout <= wire_n0lOliO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOO1O; + wire_n0lilOli_dataout <= n0lil0ii WHEN niOllO01i = '1' ELSE (n0lil0li XOR (n0lil0ll XOR (n0lil0lO XOR n0lil1Ol))); + wire_n0lilOll_dataout <= n0lil0il WHEN niOllO01i = '1' ELSE (n0lil0ll XOR (n0lil0lO XOR (n0lil0Oi XOR n0lil1OO))); + wire_n0lilOlO_dataout <= n0lil0iO WHEN niOllO01i = '1' ELSE (n0lil0lO XOR (n0lil0Oi XOR n0lil01i)); + wire_n0lilOO_dataout <= wire_n0lOlli_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOO0i; + wire_n0lilOOi_dataout <= n0lil0li WHEN niOllO01i = '1' ELSE (n0lil0Oi XOR n0lil01l); + wire_n0lilOOl_dataout <= n0lil0ll WHEN niOllO01i = '1' ELSE n0lil01O; + wire_n0lilOOO_dataout <= n0lil0lO WHEN niOllO01i = '1' ELSE n0lil00i; + wire_n0liO0i_dataout <= wire_n0lOlOl_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOil; + wire_n0liO0l_dataout <= wire_n0lOlOO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOiO; + wire_n0liO0O_dataout <= wire_n0lOO1i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOli; + wire_n0liO11i_dataout <= n0lil0Oi WHEN niOllO01i = '1' ELSE n0lil00l; + wire_n0liO1i_dataout <= wire_n0lOlll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOO0l; + wire_n0liO1l_dataout <= wire_n0lOllO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOO0O; + wire_n0liO1O_dataout <= wire_n0lOlOi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOii; + wire_n0liOii_dataout <= wire_n0lOO1l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOll; + wire_n0liOil_dataout <= wire_n0lOO1O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOlO; + wire_n0liOiO_dataout <= wire_n0lOO0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOOi; + wire_n0liOli_dataout <= wire_n0lOO0l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOOl; + wire_n0liOll_dataout <= wire_n0lOO0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0iOOOO; + wire_n0liOlO_dataout <= wire_n0lOOii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l111i; + wire_n0liOOi_dataout <= wire_n0lOOil_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l111l; + wire_n0liOOl_dataout <= wire_n0lOOiO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l111O; + wire_n0liOOO_dataout <= wire_n0lOOli_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l110i; + wire_n0ll000i_dataout <= wire_n0ll00li_dataout OR niOllOi1O; + wire_n0ll000l_dataout <= wire_n0ll00ll_dataout AND NOT(niOllOi1O); + wire_n0ll000O_dataout <= wire_n0ll00lO_dataout OR niOllOi1O; + wire_n0ll001i_dataout <= wire_n0ll00ii_dataout OR wire_niO01lOO_dataout; + wire_n0ll001l_dataout <= wire_n0ll00il_dataout OR wire_niO01lOO_dataout; + wire_n0ll001O_dataout <= wire_n0ll00iO_dataout OR wire_niO01lOO_dataout; + wire_n0ll00i_dataout <= n0iliOO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll00ii_dataout <= wire_n0ll00Oi_dataout AND NOT(niOllOi1O); + wire_n0ll00il_dataout <= wire_n0ll00Ol_dataout OR niOllOi1O; + wire_n0ll00iO_dataout <= wire_n0ll00OO_dataout OR niOllOi1O; + wire_n0ll00l_dataout <= n0ill1i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll00li_dataout <= wire_n0ll0i1i_dataout AND n0ll1lii; + wire_n0ll00ll_dataout <= wire_n0ll0i1l_dataout AND n0ll1lii; + wire_n0ll00lO_dataout <= wire_n0ll0i1O_dataout OR NOT(n0ll1lii); + wire_n0ll00O_dataout <= n0ill1l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll00Oi_dataout <= wire_n0ll0i0i_dataout OR NOT(n0ll1lii); + wire_n0ll00Ol_dataout <= wire_n0ll0i0l_dataout OR NOT(n0ll1lii); + wire_n0ll00OO_dataout <= wire_n0ll0i0O_dataout OR NOT(n0ll1lii); + wire_n0ll010i_dataout <= n0ll1l0i AND NOT(niOllO00i); + wire_n0ll011i_dataout <= n0ll1l0l OR niOllOlil; + wire_n0ll011l_dataout <= n0ll1l0O AND NOT(niOllOlil); + wire_n0ll011O_dataout <= wire_n0ll010i_dataout OR (niOllOlOl AND (n0lOi1ll OR n0lO0Oll)); + wire_n0ll01i_dataout <= n0ililO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll01l_dataout <= n0iliOi AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll01O_dataout <= n0iliOl AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll01Oi_dataout <= wire_n0ll000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll01Ol_dataout <= wire_n0ll000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll01OO_dataout <= wire_n0ll000O_dataout OR wire_niO01lOO_dataout; + wire_n0ll0i0i_dataout <= wire_n0ll0iiO_o(2) OR NOT(niOllO00O); + wire_n0ll0i0l_dataout <= wire_n0ll0iiO_o(3) OR NOT(niOllO00O); + wire_n0ll0i0O_dataout <= wire_n0ll0iiO_o(4) OR NOT(niOllO00O); + wire_n0ll0i1i_dataout <= n0ll1lii WHEN niOllO00O = '1' ELSE wire_n0ll0iii_dataout; + wire_n0ll0i1l_dataout <= niOllO00l AND NOT(niOllO00O); + wire_n0ll0i1O_dataout <= wire_n0ll0iiO_o(1) OR NOT(niOllO00O); + wire_n0ll0ii_dataout <= n0ill1O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0iii_dataout <= n0ll1lii AND niOllO00l; + wire_n0ll0il_dataout <= n0ill0i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0iO_dataout <= n0ill0l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0li_dataout <= n0ill0O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0ll_dataout <= n0illii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0lO_dataout <= n0illil AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0Oi_dataout <= n0illiO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0Ol_dataout <= n0illli AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll0OO_dataout <= n0illll AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll100l_dataout <= wire_niO11l1O_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll100O_dataout <= wire_n0lil1lO_dataout AND wire_niO11iOl_w_lg_dataout13002w(0); + wire_n0ll10i_dataout <= wire_n0lOOOl_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l11il; + wire_n0ll10ii_dataout <= wire_n0lil1li_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll10il_dataout <= wire_n0lil1il_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll10iO_dataout <= wire_n0lil10O_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll10l_dataout <= wire_n0lOOOO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l11iO; + wire_n0ll10li_dataout <= wire_n0lil10i_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll10ll_dataout <= wire_n0lil11i_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll10lO_dataout <= wire_n0liiOOl_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll10O_dataout <= wire_n0O111i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l11li; + wire_n0ll10Oi_dataout <= wire_n0liiOll_dataout OR NOT(wire_niO11iOl_w_lg_dataout13002w(0)); + wire_n0ll11i_dataout <= wire_n0lOOll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l110l; + wire_n0ll11l_dataout <= wire_n0lOOlO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l110O; + wire_n0ll11O_dataout <= wire_n0lOOOi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l11ii; + wire_n0ll1i0i_dataout <= wire_n0ll1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1i0l_dataout <= wire_n0ll1ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1i0O_dataout <= wire_n0ll1iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1i1O_dataout <= wire_n0ll1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1ii_dataout <= wire_n0O111l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l11ll; + wire_n0ll1iii_dataout <= wire_n0ll1iil_dataout AND n0lOl0Ol; + wire_n0ll1iil_dataout <= n0ll1ili OR (n0lOl0Ol AND n0ll10Ol); + wire_n0ll1il_dataout <= wire_n0O111O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0l11lO; + wire_n0ll1ill_dataout <= ((wire_niO11l1l_dataout AND niOllOiOO) AND n0ll10OO) AND n0lOl0Ol; + wire_n0ll1ilO_dataout <= (niOllOO1i AND n0ll1i1i) AND n0lOl0Ol; + wire_n0ll1iO_dataout <= n0ili0l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll1iOi_dataout <= (n0lOi00i AND (wire_niO11l1l_dataout AND niOllOl1i)) AND n0lOl0Ol; + wire_n0ll1li_dataout <= n0ili0O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll1lil_dataout <= wire_n0ll1llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1liO_dataout <= wire_n0ll011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1ll_dataout <= n0iliii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll1lli_dataout <= wire_n0ll1lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1lll_dataout <= wire_n0ll1lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0ll1llO_dataout <= wire_n0ll1lOO_dataout AND NOT(niOllO01l); + wire_n0ll1lO_dataout <= n0iliil AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll1lOi_dataout <= wire_n0ll011i_dataout WHEN niOllO01l = '1' ELSE wire_n0ll1O1i_dataout; + wire_n0ll1lOl_dataout <= wire_n0ll011l_dataout WHEN niOllO01l = '1' ELSE wire_n0ll1O1l_dataout; + wire_n0ll1lOO_dataout <= n0ll1i1l WHEN wire_niO01ill_w_lg_n0ll1l0i12995w(0) = '1' ELSE wire_n0ll1O0l_dataout; + wire_n0ll1O0i_dataout <= wire_n0ll1OOi_dataout WHEN niOllOlil = '1' ELSE wire_n0ll1Oii_dataout; + wire_n0ll1O0l_dataout <= wire_n0ll1OOl_dataout WHEN niOllOlil = '1' ELSE n0ll1i1l; + wire_n0ll1O0O_dataout <= n0ll1l0l AND NOT(niOllO00i); + wire_n0ll1O1i_dataout <= wire_n0ll1O0O_dataout WHEN wire_niO01ill_w_lg_n0ll1l0i12995w(0) = '1' ELSE wire_n0ll1O1O_dataout; + wire_n0ll1O1l_dataout <= wire_n0ll1Oii_dataout WHEN wire_niO01ill_w_lg_n0ll1l0i12995w(0) = '1' ELSE wire_n0ll1O0i_dataout; + wire_n0ll1O1O_dataout <= wire_n0ll1OlO_dataout WHEN niOllOlil = '1' ELSE wire_n0ll1O0O_dataout; + wire_n0ll1Oi_dataout <= n0iliiO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll1Oii_dataout <= n0ll1l0O AND NOT(niOllO00i); + wire_n0ll1Ol_dataout <= n0ilili AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll1OlO_dataout <= n0ll1l0l WHEN niOllO01O = '1' ELSE wire_n0ll1OOO_o(0); + wire_n0ll1OO_dataout <= n0ilill AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0ll1OOi_dataout <= n0ll1l0O WHEN niOllO01O = '1' ELSE wire_n0ll1OOO_o(1); + wire_n0ll1OOl_dataout <= n0ll1i1l OR niOllO01O; + wire_n0lli00i_dataout <= wire_n0llilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli00l_dataout <= wire_n0lliO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli00O_dataout <= wire_n0lliO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli01i_dataout <= wire_n0lll0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli01l_dataout <= ((niOllOlil OR niOllOlii) OR niOllOl0O) AND NOT(wire_niO01lOO_dataout); + wire_n0lli01O_dataout <= (n0lOi00i AND (niOllOO1i OR niOllOllO)) AND NOT(wire_niO01lOO_dataout); + wire_n0lli0i_dataout <= n0illOO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lli0ii_dataout <= wire_n0lliO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0il_dataout <= wire_n0lliO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0iO_dataout <= wire_n0lliO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0l_dataout <= n0ilO1i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lli0li_dataout <= wire_n0lliO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0ll_dataout <= wire_n0lliOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0lO_dataout <= wire_n0llli1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0O_dataout <= n0ilO1l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lli0Oi_dataout <= wire_n0llli1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0Ol_dataout <= wire_n0llli1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli0OO_dataout <= wire_n0llli0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli1i_dataout <= n0illlO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lli1l_dataout <= n0illOi AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lli1O_dataout <= n0illOl AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lli1Ol_dataout <= wire_n0lll0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lli1OO_dataout <= wire_n0lll0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llii0i_dataout <= wire_n0llliil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llii0l_dataout <= wire_n0llliiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llii0O_dataout <= wire_n0lllili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llii1i_dataout <= wire_n0llli0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llii1l_dataout <= wire_n0llli0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llii1O_dataout <= wire_n0llliii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliii_dataout <= n0ilO1O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lliiii_dataout <= wire_n0lllill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliiil_dataout <= wire_n0lllilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliiiO_dataout <= wire_n0llliOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliil_dataout <= n0ilO0i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lliili_dataout <= wire_n0llliOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliill_dataout <= wire_n0llliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliilO_dataout <= wire_n0llll1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliiO_dataout <= n0ilO0l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lliiOi_dataout <= wire_n0llll1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliiOl_dataout <= wire_n0llll1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliiOO_dataout <= wire_n0lll1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llil0i_dataout <= wire_n0lll00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llil0l_dataout <= wire_n0llll0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llil0O_dataout <= wire_n0lll00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llil1i_dataout <= wire_n0lll01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llil1l_dataout <= wire_n0lll01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llil1O_dataout <= wire_n0lll01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llili_dataout <= n0ilO0O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llilii_dataout <= wire_n0lll00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llilil_dataout <= wire_n0lll0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lliliO_dataout <= wire_n0lll0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llill_dataout <= n0ilOii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llilli_dataout <= wire_n0lll0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llilll_dataout <= wire_n0lll0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llillO_dataout <= wire_n0lll0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llilO_dataout <= n0ilOil AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llilOi_dataout <= wire_n0lll0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llilOl_dataout <= wire_n0llll0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llilOO_dataout <= wire_n0lliOil_dataout AND NOT(niOllO0Oi); + wire_n0lliO0i_dataout <= wire_n0lliOlO_dataout AND NOT(niOllO0Oi); + wire_n0lliO0l_dataout <= wire_n0lliOOi_dataout AND NOT(niOllO0Oi); + wire_n0lliO0O_dataout <= wire_n0lliOOl_dataout AND NOT(niOllO0Oi); + wire_n0lliO1i_dataout <= wire_n0lliOiO_dataout AND NOT(niOllO0Oi); + wire_n0lliO1l_dataout <= wire_n0lliOli_dataout AND NOT(niOllO0Oi); + wire_n0lliO1O_dataout <= wire_n0lliOll_dataout AND NOT(niOllO0Oi); + wire_n0lliOi_dataout <= n0ilOiO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lliOii_dataout <= wire_n0lliOOO_dataout AND NOT(niOllO0Oi); + wire_n0lliOil_dataout <= wire_n0lll11i_dataout OR niOllO0lO; + wire_n0lliOiO_dataout <= wire_n0lll11l_dataout AND NOT(niOllO0lO); + wire_n0lliOl_dataout <= n0ilOli AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lliOli_dataout <= wire_n0lll11O_dataout AND NOT(niOllO0lO); + wire_n0lliOll_dataout <= wire_n0lll10i_dataout AND NOT(niOllO0lO); + wire_n0lliOlO_dataout <= wire_n0lll10l_dataout AND NOT(niOllO0lO); + wire_n0lliOO_dataout <= n0ilOll AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lliOOi_dataout <= wire_n0lll10O_dataout AND NOT(niOllO0lO); + wire_n0lliOOl_dataout <= wire_n0lll1ii_dataout AND NOT(niOllO0lO); + wire_n0lliOOO_dataout <= wire_n0lll1il_dataout AND NOT(niOllO0lO); + wire_n0lll00i_dataout <= n0lli11l WHEN niOlO1O0i = '1' ELSE wire_n0llO11i_dataout; + wire_n0lll00l_dataout <= n0lli10i WHEN niOlO1O0i = '1' ELSE wire_n0llO11O_dataout; + wire_n0lll00O_dataout <= n0lli10l WHEN niOlO1O0i = '1' ELSE wire_n0llO10i_dataout; + wire_n0lll01i_dataout <= n0ll0OOl WHEN niOlO1O0i = '1' ELSE wire_n0lllOOi_dataout; + wire_n0lll01l_dataout <= n0ll0OOO WHEN niOlO1O0i = '1' ELSE wire_n0lllOOl_dataout; + wire_n0lll01O_dataout <= n0lli11i WHEN niOlO1O0i = '1' ELSE wire_n0lllOOO_dataout; + wire_n0lll0i_dataout <= n0ilOOO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lll0ii_dataout <= n0lli10O WHEN niOlO1O0i = '1' ELSE wire_n0llO10l_dataout; + wire_n0lll0il_dataout <= n0lli1ii WHEN niOlO1O0i = '1' ELSE wire_n0llO10O_dataout; + wire_n0lll0iO_dataout <= n0lli1il WHEN niOlO1O0i = '1' ELSE wire_n0llO1ii_dataout; + wire_n0lll0l_dataout <= n0iO11i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lll0li_dataout <= n0lli1iO WHEN niOlO1O0i = '1' ELSE wire_n0llO1il_dataout; + wire_n0lll0ll_dataout <= n0lli1li WHEN niOlO1O0i = '1' ELSE wire_n0llO1iO_dataout; + wire_n0lll0lO_dataout <= n0lli1ll WHEN niOlO1O0i = '1' ELSE wire_n0llO1li_dataout; + wire_n0lll0O_dataout <= n0iO11l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lll0Oi_dataout <= wire_n0llll0O_dataout AND NOT(niOlO1O0i); + wire_n0lll0Ol_dataout <= wire_n0llllii_dataout AND NOT(niOlO1O0i); + wire_n0lll0OO_dataout <= wire_n0llllil_dataout AND NOT(niOlO1O0i); + wire_n0lll10i_dataout <= wire_n0lll1iO_o(3) WHEN niOllO0li = '1' ELSE n0ll0l0l; + wire_n0lll10l_dataout <= wire_n0lll1iO_o(4) WHEN niOllO0li = '1' ELSE n0ll0l0O; + wire_n0lll10O_dataout <= wire_n0lll1iO_o(5) WHEN niOllO0li = '1' ELSE n0ll0lii; + wire_n0lll11i_dataout <= wire_n0lll1iO_o(0) WHEN niOllO0li = '1' ELSE n0ll0l1l; + wire_n0lll11l_dataout <= wire_n0lll1iO_o(1) WHEN niOllO0li = '1' ELSE n0ll0l1O; + wire_n0lll11O_dataout <= wire_n0lll1iO_o(2) WHEN niOllO0li = '1' ELSE n0ll0l0i; + wire_n0lll1i_dataout <= n0ilOlO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lll1ii_dataout <= wire_n0lll1iO_o(6) WHEN niOllO0li = '1' ELSE n0ll0lil; + wire_n0lll1il_dataout <= wire_n0lll1iO_o(7) WHEN niOllO0li = '1' ELSE n0ll0liO; + wire_n0lll1l_dataout <= n0ilOOi AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lll1O_dataout <= n0ilOOl AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lll1OO_dataout <= n0ll0OOi WHEN niOlO1O0i = '1' ELSE wire_n0lllOlO_dataout; + wire_n0llli0i_dataout <= wire_n0lllllO_dataout AND NOT(niOlO1O0i); + wire_n0llli0l_dataout <= wire_n0llllOi_dataout AND NOT(niOlO1O0i); + wire_n0llli0O_dataout <= wire_n0llllOl_dataout AND NOT(niOlO1O0i); + wire_n0llli1i_dataout <= wire_n0lllliO_dataout AND NOT(niOlO1O0i); + wire_n0llli1l_dataout <= wire_n0llllli_dataout AND NOT(niOlO1O0i); + wire_n0llli1O_dataout <= wire_n0llllll_dataout AND NOT(niOlO1O0i); + wire_n0lllii_dataout <= n0iO11O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llliii_dataout <= wire_n0llllOO_dataout AND NOT(niOlO1O0i); + wire_n0llliil_dataout <= wire_n0lllO1i_dataout AND NOT(niOlO1O0i); + wire_n0llliiO_dataout <= wire_n0lllO1l_dataout AND NOT(niOlO1O0i); + wire_n0lllil_dataout <= n0iO10i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lllili_dataout <= wire_n0lllO1O_dataout AND NOT(niOlO1O0i); + wire_n0lllill_dataout <= wire_n0lllO0i_dataout AND NOT(niOlO1O0i); + wire_n0lllilO_dataout <= wire_n0lllO0l_dataout AND NOT(niOlO1O0i); + wire_n0llliO_dataout <= n0iO10l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llliOi_dataout <= wire_n0lllO0O_dataout AND NOT(niOlO1O0i); + wire_n0llliOl_dataout <= wire_n0lllOii_dataout AND NOT(niOlO1O0i); + wire_n0llliOO_dataout <= wire_n0lllOil_dataout AND NOT(niOlO1O0i); + wire_n0llll0i_dataout <= wire_n0llO11l_dataout AND NOT(niOlO1O0i); + wire_n0llll0l_dataout <= wire_n0llO1ll_dataout AND NOT(niOlO1O0i); + wire_n0llll0O_dataout <= n0lli1Oi WHEN n0llOi1i = '1' ELSE n0ll01lO; + wire_n0llll1i_dataout <= wire_n0lllOiO_dataout AND NOT(niOlO1O0i); + wire_n0llll1l_dataout <= wire_n0lllOli_dataout AND NOT(niOlO1O0i); + wire_n0llll1O_dataout <= wire_n0lllOll_dataout AND NOT(niOlO1O0i); + wire_n0lllli_dataout <= n0iO10O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llllii_dataout <= n0llO0Oi WHEN n0llOi1i = '1' ELSE n0ll0iOi; + wire_n0llllil_dataout <= n0llO0Ol WHEN n0llOi1i = '1' ELSE n0ll0iOl; + wire_n0lllliO_dataout <= n0llOi1O WHEN n0llOi1i = '1' ELSE n0ll0lli; + wire_n0lllll_dataout <= n0iO1ii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llllli_dataout <= n0llOi0i WHEN n0llOi1i = '1' ELSE n0ll0lll; + wire_n0llllll_dataout <= n0llOi0l WHEN n0llOi1i = '1' ELSE n0ll0llO; + wire_n0lllllO_dataout <= n0llOi0O WHEN n0llOi1i = '1' ELSE n0ll0lOi; + wire_n0llllO_dataout <= n0iO1il AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llllOi_dataout <= n0llOiii WHEN n0llOi1i = '1' ELSE n0ll0lOl; + wire_n0llllOl_dataout <= n0llOiil WHEN n0llOi1i = '1' ELSE n0ll0lOO; + wire_n0llllOO_dataout <= n0llOiiO WHEN n0llOi1i = '1' ELSE n0ll0O1i; + wire_n0lllO0i_dataout <= n0llOiOi WHEN n0llOi1i = '1' ELSE n0ll0O0l; + wire_n0lllO0l_dataout <= n0llOiOl WHEN n0llOi1i = '1' ELSE n0ll0O0O; + wire_n0lllO0O_dataout <= n0llOiOO WHEN n0llOi1i = '1' ELSE n0ll0Oii; + wire_n0lllO1i_dataout <= n0llOili WHEN n0llOi1i = '1' ELSE n0ll0O1l; + wire_n0lllO1l_dataout <= n0llOill WHEN n0llOi1i = '1' ELSE n0ll0O1O; + wire_n0lllO1O_dataout <= n0llOilO WHEN n0llOi1i = '1' ELSE n0ll0O0i; + wire_n0lllOi_dataout <= n0iO1iO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lllOii_dataout <= n0llOl1i WHEN n0llOi1i = '1' ELSE n0ll0Oil; + wire_n0lllOil_dataout <= n0llOl1l WHEN n0llOi1i = '1' ELSE n0ll0OiO; + wire_n0lllOiO_dataout <= n0llOl1O WHEN n0llOi1i = '1' ELSE n0ll0Oli; + wire_n0lllOl_dataout <= n0iO1li AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lllOli_dataout <= n0llOl0i WHEN n0llOi1i = '1' ELSE n0ll0Oll; + wire_n0lllOll_dataout <= n0llOl0l WHEN n0llOi1i = '1' ELSE n0ll0OlO; + wire_n0lllOlO_dataout <= n0llOl0O WHEN n0llOi1i = '1' ELSE n0ll0OOi; + wire_n0lllOO_dataout <= n0iO1ll AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lllOOi_dataout <= n0llOlii WHEN n0llOi1i = '1' ELSE n0ll0OOl; + wire_n0lllOOl_dataout <= n0llOlil WHEN n0llOi1i = '1' ELSE n0ll0OOO; + wire_n0lllOOO_dataout <= n0llOliO WHEN n0llOi1i = '1' ELSE n0lli11i; + wire_n0llO0i_dataout <= n0iO1OO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llO0l_dataout <= n0iO01i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llO0O_dataout <= n0iO01l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llO10i_dataout <= n0llOlOi WHEN n0llOi1i = '1' ELSE n0lli10l; + wire_n0llO10l_dataout <= n0llOlOl WHEN n0llOi1i = '1' ELSE n0lli10O; + wire_n0llO10O_dataout <= n0llOlOO WHEN n0llOi1i = '1' ELSE n0lli1ii; + wire_n0llO11i_dataout <= n0llOlli WHEN n0llOi1i = '1' ELSE n0lli11l; + wire_n0llO11l_dataout <= n0llOlll WHEN n0llOi1i = '1' ELSE n0lli11O; + wire_n0llO11O_dataout <= n0llOllO WHEN n0llOi1i = '1' ELSE n0lli10i; + wire_n0llO1i_dataout <= n0iO1lO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llO1ii_dataout <= n0llOO1i WHEN n0llOi1i = '1' ELSE n0lli1il; + wire_n0llO1il_dataout <= n0llOO1l WHEN n0llOi1i = '1' ELSE n0lli1iO; + wire_n0llO1iO_dataout <= n0llOO1O WHEN n0llOi1i = '1' ELSE n0lli1li; + wire_n0llO1l_dataout <= n0iO1Oi AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llO1li_dataout <= n0llOO0i WHEN n0llOi1i = '1' ELSE n0lli1ll; + wire_n0llO1ll_dataout <= n0llOO0l WHEN n0llOi1i = '1' ELSE n0lli1lO; + wire_n0llO1O_dataout <= n0iO1Ol AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llOii_dataout <= n0iO01O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llOil_dataout <= n0iO00i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llOiO_dataout <= n0iO00l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llOli_dataout <= n0iO00O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llOll_dataout <= n0iO0ii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llOlO_dataout <= n0iO0il AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0llOOi_dataout <= wire_n0O0llO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0lO; + wire_n0llOOl_dataout <= wire_n0O0lOi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0Oi; + wire_n0llOOll_dataout <= wire_n0lO010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llOOlO_dataout <= wire_n0lO1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llOOO_dataout <= wire_n0O0lOl_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0Ol; + wire_n0llOOOi_dataout <= wire_n0lO010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0llOOOl_dataout <= ((wire_w_lg_niOllOllO12853w(0) AND (wire_w_lg_niOllOl1l12854w(0) AND wire_w_lg_w_lg_niOllOO1i12717w12855w(0))) AND (wire_w_lg_w_lg_w_lg_niOllOi1O12858w12862w12863w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n0llOOOO_dataout <= (wire_w_lg_w_lg_w_lg_niOllOiOl12847w12849w12850w(0) AND wire_niO01ill_w_lg_n0llOi1l12851w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0lO000i_dataout <= wire_niO11l0l_dataout WHEN niOllOiiO = '1' ELSE n0llOlii; + wire_n0lO000l_dataout <= wire_niO11l0O_dataout WHEN niOllOiiO = '1' ELSE n0llOlil; + wire_n0lO000O_dataout <= wire_niO11lii_dataout WHEN niOllOiiO = '1' ELSE n0llOliO; + wire_n0lO001i_dataout <= wire_niO11lli_dataout WHEN niOllOi0O = '1' ELSE n0llOl1i; + wire_n0lO001l_dataout <= wire_niO11lll_dataout WHEN niOllOi0O = '1' ELSE n0llOl1l; + wire_n0lO001O_dataout <= wire_niO11l0i_dataout WHEN niOllOiiO = '1' ELSE n0llOl0O; + wire_n0lO00i_dataout <= wire_n0O11il_dataout AND NOT(n0Oli1i); + wire_n0lO00ii_dataout <= wire_niO11lil_dataout WHEN niOllOiiO = '1' ELSE n0llOlli; + wire_n0lO00il_dataout <= niOllOlli WHEN niOllOiiO = '1' ELSE n0llOlll; + wire_n0lO00iO_dataout <= wire_niO11l0i_dataout WHEN niOllOl1l = '1' ELSE n0llOllO; + wire_n0lO00l_dataout <= wire_n0O11iO_dataout AND NOT(n0Oli1i); + wire_n0lO00li_dataout <= wire_niO11l0l_dataout WHEN niOllOl1l = '1' ELSE n0llOlOi; + wire_n0lO00ll_dataout <= wire_niO11l0O_dataout WHEN niOllOl1l = '1' ELSE n0llOlOl; + wire_n0lO00lO_dataout <= wire_niO11lii_dataout WHEN niOllOl1l = '1' ELSE n0llOlOO; + wire_n0lO00O_dataout <= wire_n0O11li_dataout AND NOT(n0Oli1i); + wire_n0lO00Oi_dataout <= wire_niO11lil_dataout WHEN niOllOl1l = '1' ELSE n0llOO1i; + wire_n0lO00Ol_dataout <= wire_niO11liO_dataout WHEN niOllOl1l = '1' ELSE n0llOO1l; + wire_n0lO00OO_dataout <= wire_niO11lli_dataout WHEN niOllOl1l = '1' ELSE n0llOO1O; + wire_n0lO010i_dataout <= wire_niO11lii_dataout WHEN niOllOi0i = '1' ELSE n0llOiiO; + wire_n0lO010l_dataout <= wire_niO11lll_dataout WHEN niOllOi0l = '1' ELSE n0llO0Ol; + wire_n0lO010O_dataout <= wire_niO11lli_dataout WHEN niOllOi0l = '1' ELSE n0lli1Oi; + wire_n0lO011i_dataout <= wire_niO11l0i_dataout WHEN niOllOi0i = '1' ELSE n0llOi0O; + wire_n0lO011l_dataout <= wire_niO11l0l_dataout WHEN niOllOi0i = '1' ELSE n0llOiii; + wire_n0lO011O_dataout <= wire_niO11l0O_dataout WHEN niOllOi0i = '1' ELSE n0llOiil; + wire_n0lO01i_dataout <= wire_n0O110l_dataout AND NOT(n0Oli1i); + wire_n0lO01ii_dataout <= wire_niO11l0l_dataout WHEN niOllOi0l = '1' ELSE n0llOl1O; + wire_n0lO01il_dataout <= wire_niO11l0O_dataout WHEN niOllOi0l = '1' ELSE n0llOl0i; + wire_n0lO01iO_dataout <= n0llOl0l AND NOT(niOllOi0l); + wire_n0lO01l_dataout <= wire_n0O110O_dataout AND NOT(n0Oli1i); + wire_n0lO01li_dataout <= wire_niO11l0i_dataout WHEN niOllOi0O = '1' ELSE n0llOili; + wire_n0lO01ll_dataout <= wire_niO11l0l_dataout WHEN niOllOi0O = '1' ELSE n0llOill; + wire_n0lO01lO_dataout <= wire_niO11l0O_dataout WHEN niOllOi0O = '1' ELSE n0llOilO; + wire_n0lO01O_dataout <= wire_n0O11ii_dataout AND NOT(n0Oli1i); + wire_n0lO01Oi_dataout <= wire_niO11lii_dataout WHEN niOllOi0O = '1' ELSE n0llOiOi; + wire_n0lO01Ol_dataout <= wire_niO11lil_dataout WHEN niOllOi0O = '1' ELSE n0llOiOl; + wire_n0lO01OO_dataout <= wire_niO11liO_dataout WHEN niOllOi0O = '1' ELSE n0llOiOO; + wire_n0lO0i0i_dataout <= wire_n0lO0iil_dataout AND NOT(niOllOl1l); + wire_n0lO0i0l_dataout <= wire_n0lO0iiO_dataout OR niOllOl1l; + wire_n0lO0i0O_dataout <= wire_n0lO0ili_dataout OR niOllOl1l; + wire_n0lO0i1i_dataout <= wire_niO11lll_dataout WHEN niOllOl1l = '1' ELSE n0llOO0i; + wire_n0lO0i1l_dataout <= niOllOlli WHEN niOllOl1l = '1' ELSE n0llOO0l; + wire_n0lO0i1O_dataout <= wire_n0lO0iii_dataout OR niOllOl1l; + wire_n0lO0ii_dataout <= wire_n0O11ll_dataout AND NOT(n0Oli1i); + wire_n0lO0iii_dataout <= wire_n0lO0ill_dataout WHEN wire_w_lg_niOllOiii12787w(0) = '1' ELSE n0llOO0O; + wire_n0lO0iil_dataout <= wire_n0lO0ilO_dataout WHEN wire_w_lg_niOllOiii12787w(0) = '1' ELSE n0llOOii; + wire_n0lO0iiO_dataout <= wire_n0lO0iOi_dataout WHEN wire_w_lg_niOllOiii12787w(0) = '1' ELSE n0llOOil; + wire_n0lO0il_dataout <= wire_n0O11lO_dataout AND NOT(n0Oli1i); + wire_n0lO0ili_dataout <= wire_n0lO0iOl_dataout WHEN wire_w_lg_niOllOiii12787w(0) = '1' ELSE n0llOOiO; + wire_n0lO0ill_dataout <= wire_n0lO0iOO_o(1) AND niOllOiil; + wire_n0lO0ilO_dataout <= wire_n0lO0iOO_o(2) AND niOllOiil; + wire_n0lO0iO_dataout <= wire_n0O11Oi_dataout AND NOT(n0Oli1i); + wire_n0lO0iOi_dataout <= wire_n0lO0iOO_o(3) AND niOllOiil; + wire_n0lO0iOl_dataout <= wire_n0lO0iOO_o(4) AND niOllOiil; + wire_n0lO0li_dataout <= wire_n0O11Ol_dataout AND NOT(n0Oli1i); + wire_n0lO0ll_dataout <= wire_n0O11OO_dataout AND NOT(n0Oli1i); + wire_n0lO0lO_dataout <= wire_n0O101i_dataout AND NOT(n0Oli1i); + wire_n0lO0Oi_dataout <= wire_n0O101l_dataout AND NOT(n0Oli1i); + wire_n0lO0Ol_dataout <= wire_n0O101O_dataout AND NOT(n0Oli1i); + wire_n0lO0OlO_dataout <= wire_n0lOi11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO0OO_dataout <= wire_n0O100i_dataout AND NOT(n0Oli1i); + wire_n0lO0OOi_dataout <= wire_n0lOi11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO0OOl_dataout <= wire_n0lOi11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO0OOO_dataout <= wire_n0lOi10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO100i_dataout <= wire_n0lO01iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO100l_dataout <= wire_n0lO001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO100O_dataout <= wire_n0lO000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO101i_dataout <= wire_n0lO001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO101l_dataout <= wire_n0lO01ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO101O_dataout <= wire_n0lO01il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10i_dataout <= wire_n0O0O1O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0ili1O; + wire_n0lO10ii_dataout <= wire_n0lO000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10il_dataout <= wire_n0lO000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10iO_dataout <= wire_n0lO00ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10l_dataout <= wire_n0O0O0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0ili0i; + wire_n0lO10li_dataout <= wire_n0lO00il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10ll_dataout <= wire_n0lO00iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10lO_dataout <= wire_n0lO00li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10O_dataout <= wire_n0O0OOl_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il00i; + wire_n0lO10Oi_dataout <= wire_n0lO00ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10Ol_dataout <= wire_n0lO00lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO10OO_dataout <= wire_n0lO00Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO110i_dataout <= wire_n0lO1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO110l_dataout <= wire_n0lO011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO110O_dataout <= wire_n0lO011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO111i_dataout <= wire_n0lO1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO111l_dataout <= wire_n0lO1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO111O_dataout <= wire_n0lO1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11i_dataout <= wire_n0O0lOO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0OO; + wire_n0lO11ii_dataout <= wire_n0lO011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11il_dataout <= wire_n0lO010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11iO_dataout <= wire_n0lO01li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11l_dataout <= wire_n0O0O1i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0ili1i; + wire_n0lO11li_dataout <= wire_n0lO01ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11ll_dataout <= wire_n0lO01lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11lO_dataout <= wire_n0lO01Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11O_dataout <= wire_n0O0O1l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0ili1l; + wire_n0lO11Oi_dataout <= wire_n0lO01Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11Ol_dataout <= wire_n0lO01OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO11OO_dataout <= wire_n0lO001i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO1i0i_dataout <= wire_n0lO0i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO1i0l_dataout <= wire_n0lO0i1O_dataout OR wire_niO01lOO_dataout; + wire_n0lO1i0O_dataout <= wire_n0lO0i0i_dataout OR wire_niO01lOO_dataout; + wire_n0lO1i1i_dataout <= wire_n0lO00Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO1i1l_dataout <= wire_n0lO00OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO1i1O_dataout <= wire_n0lO0i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lO1ii_dataout <= wire_n0O0OOO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il00l; + wire_n0lO1iii_dataout <= wire_n0lO0i0l_dataout OR wire_niO01lOO_dataout; + wire_n0lO1iil_dataout <= wire_n0lO0i0O_dataout OR wire_niO01lOO_dataout; + wire_n0lO1il_dataout <= wire_n0Oi11i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il00O; + wire_n0lO1iO_dataout <= wire_n0Oi11l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0ii; + wire_n0lO1li_dataout <= wire_n0Oi11O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0il; + wire_n0lO1lii_dataout <= wire_n0lO1lil_dataout AND NOT(niOllOl1l); + wire_n0lO1lil_dataout <= wire_n0lO1liO_dataout OR (wire_w_lg_niOllOlli12836w(0) AND wire_w_lg_w_lg_niOllOliO12825w12837w(0)); + wire_n0lO1liO_dataout <= wire_n0lO1lli_dataout OR (wire_w_lg_niOllOliO12825w(0) AND (wire_w_lg_w_lg_niOllOi0O12827w12828w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n0llOOiO12830w12832w12833w(0))); + wire_n0lO1ll_dataout <= wire_n0Oi10i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0iO; + wire_n0lO1lli_dataout <= wire_n0lO1lll_dataout OR (wire_w_lg_niOllOliO12825w(0) AND niOllOi0l); + wire_n0lO1lll_dataout <= n0llOi1l OR (wire_n0lO1O1O_o AND (((niOllOiOl XOR n0llOi0i) OR (niOllOill XOR n0llOi1O)) OR (NOT (n0llOi0i XOR n0llOi1O)))); + wire_n0lO1lO_dataout <= wire_n0Oi10l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0li; + wire_n0lO1Oi_dataout <= wire_n0Oi10O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE n0il0ll; + wire_n0lO1Ol_dataout <= n0il1iO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_n0lO1Oll_dataout <= niOllOill WHEN wire_n0lO1OOl_o = '1' ELSE n0llOi1O; + wire_n0lO1OlO_dataout <= niOllOiOl WHEN wire_n0lO1OOl_o = '1' ELSE n0llOi0i; + wire_n0lO1OO_dataout <= wire_n0O110i_dataout AND NOT(n0Oli1i); + wire_n0lO1OOi_dataout <= (wire_niO11l1l_dataout AND (niOllOiOi OR niOllOl1i)) WHEN wire_n0lO1OOl_o = '1' ELSE n0llOi0l; + wire_n0lO1OOO_dataout <= wire_niO11lil_dataout WHEN niOllOi0i = '1' ELSE n0llO0Oi; + wire_n0lOi00O_dataout <= (niOllOO1i AND n0lOi1lO) AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0i_dataout <= wire_n0O10il_dataout AND NOT(n0Oli1i); + wire_n0lOi0ii_dataout <= (niOllOO1i AND n0lOi1Oi) AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0il_dataout <= (wire_w_lg_w_lg_w_lg_niOllOlOl12714w12715w12716w(0) OR (wire_w_lg_niOllOO1i12717w(0) AND (wire_w_lg_niOllOlOl12718w(0) AND (n0lOi01i AND niOllOl0l)))) AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0iO_dataout <= niOllOlil AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0l_dataout <= wire_n0O10iO_dataout AND NOT(n0Oli1i); + wire_n0lOi0li_dataout <= (niOllOlOl AND n0lOi00i) AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0ll_dataout <= n0lOi01i AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0lO_dataout <= niOllOlOl AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0O_dataout <= wire_n0O10li_dataout AND NOT(n0Oli1i); + wire_n0lOi0Oi_dataout <= n0lOi01O AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0Ol_dataout <= n0lOi00i AND NOT(wire_niO01lOO_dataout); + wire_n0lOi0OO_dataout <= niOllOO1i AND NOT(wire_niO01lOO_dataout); + wire_n0lOi10i_dataout <= wire_n0lOi1il_dataout AND NOT(niOllOl1O); + wire_n0lOi10l_dataout <= wire_n0lOi1iO_o(0) WHEN wire_niO01ill_w_lg_n0lO0Oli12743w(0) = '1' ELSE n0llOOli; + wire_n0lOi10O_dataout <= wire_n0lOi1iO_o(1) WHEN wire_niO01ill_w_lg_n0lO0Oli12743w(0) = '1' ELSE n0lO0Oil; + wire_n0lOi11i_dataout <= wire_n0lOi10l_dataout AND NOT(niOllOl1O); + wire_n0lOi11l_dataout <= wire_n0lOi10O_dataout AND NOT(niOllOl1O); + wire_n0lOi11O_dataout <= wire_n0lOi1ii_dataout AND NOT(niOllOl1O); + wire_n0lOi1i_dataout <= wire_n0O100l_dataout AND NOT(n0Oli1i); + wire_n0lOi1ii_dataout <= wire_n0lOi1iO_o(2) WHEN wire_niO01ill_w_lg_n0lO0Oli12743w(0) = '1' ELSE n0lO0OiO; + wire_n0lOi1il_dataout <= wire_n0lOi1iO_o(3) OR NOT(wire_niO01ill_w_lg_n0lO0Oli12743w(0)); + wire_n0lOi1l_dataout <= wire_n0O100O_dataout AND NOT(n0Oli1i); + wire_n0lOi1O_dataout <= wire_n0O10ii_dataout AND NOT(n0Oli1i); + wire_n0lOiii_dataout <= wire_n0O10ll_dataout AND NOT(n0Oli1i); + wire_n0lOiil_dataout <= wire_n0O10lO_dataout AND NOT(n0Oli1i); + wire_n0lOiiO_dataout <= wire_n0O10Oi_dataout AND NOT(n0Oli1i); + wire_n0lOili_dataout <= wire_n0O10Ol_dataout AND NOT(n0Oli1i); + wire_n0lOiliO_dataout <= wire_n0lOiO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOill_dataout <= wire_n0O10OO_dataout AND NOT(n0Oli1i); + wire_n0lOilli_dataout <= wire_n0lOiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOilll_dataout <= wire_n0lOiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOillO_dataout <= wire_n0lOiO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOilO_dataout <= wire_n0O1i1i_dataout AND NOT(n0Oli1i); + wire_n0lOilOi_dataout <= wire_n0lOiO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOilOl_dataout <= wire_n0lOiO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOilOO_dataout <= wire_n0lOiOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOiO0i_dataout <= wire_n0lOiOll_dataout AND NOT(niOllOO0l); + wire_n0lOiO0l_dataout <= wire_n0lOiOlO_dataout AND NOT(niOllOO0l); + wire_n0lOiO0O_dataout <= wire_n0lOiOOi_dataout AND NOT(niOllOO0l); + wire_n0lOiO1i_dataout <= wire_n0lOiOil_dataout AND NOT(niOllOO0l); + wire_n0lOiO1l_dataout <= wire_n0lOiOiO_dataout AND NOT(niOllOO0l); + wire_n0lOiO1O_dataout <= wire_n0lOiOli_dataout AND NOT(niOllOO0l); + wire_n0lOiOi_dataout <= wire_n0O1i1l_dataout AND NOT(n0Oli1i); + wire_n0lOiOii_dataout <= wire_n0lOiOOl_dataout AND NOT(niOllOO0l); + wire_n0lOiOil_dataout <= wire_n0lOiOOO_o(0) WHEN niOllOO1O = '1' ELSE n0lOi00l; + wire_n0lOiOiO_dataout <= wire_n0lOiOOO_o(1) WHEN niOllOO1O = '1' ELSE n0lOil1l; + wire_n0lOiOl_dataout <= wire_n0O1i1O_dataout AND NOT(n0Oli1i); + wire_n0lOiOli_dataout <= wire_n0lOiOOO_o(2) WHEN niOllOO1O = '1' ELSE n0lOil1O; + wire_n0lOiOll_dataout <= wire_n0lOiOOO_o(3) WHEN niOllOO1O = '1' ELSE n0lOil0i; + wire_n0lOiOlO_dataout <= wire_n0lOiOOO_o(4) WHEN niOllOO1O = '1' ELSE n0lOil0l; + wire_n0lOiOO_dataout <= wire_n0O1i0i_dataout AND NOT(n0Oli1i); + wire_n0lOiOOi_dataout <= wire_n0lOiOOO_o(5) WHEN niOllOO1O = '1' ELSE n0lOil0O; + wire_n0lOiOOl_dataout <= wire_n0lOiOOO_o(6) WHEN niOllOO1O = '1' ELSE n0lOilii; + wire_n0lOl0i_dataout <= wire_n0O1iil_dataout AND NOT(n0Oli1i); + wire_n0lOl0l_dataout <= wire_n0O1iiO_dataout AND NOT(n0Oli1i); + wire_n0lOl0O_dataout <= wire_n0O1ili_dataout AND NOT(n0Oli1i); + wire_n0lOl10l_dataout <= n0lOl0Ol AND (((NOT (n1101l1i XOR n0lOl0ll)) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0lOl0lO))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0lOl0Oi))); + wire_n0lOl10l_w_lg_w_lg_w_lg_dataout12598w12604w12605w(0) <= wire_n0lOl10l_w_lg_w_lg_dataout12598w12604w(0) AND n0lOl0Ol; + wire_n0lOl10l_w_lg_w_lg_dataout12598w12604w(0) <= wire_n0lOl10l_w_lg_dataout12598w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n0lOl0iO12599w12601w12603w(0); + wire_n0lOl10l_w_lg_dataout12611w(0) <= wire_n0lOl10l_dataout AND wire_niO01ill_w12610w(0); + wire_n0lOl10l_w_lg_dataout12598w(0) <= NOT wire_n0lOl10l_dataout; + wire_n0lOl10O_dataout <= n0lOli0O AND (n0lOl0OO AND niOllOO0O); + wire_n0lOl1i_dataout <= wire_n0O1i0l_dataout AND NOT(n0Oli1i); + wire_n0lOl1il_dataout <= n0lOli0O AND ((NOT (n0lOli1l XOR n0lOli1i)) AND niOllOO0O); + wire_n0lOl1l_dataout <= wire_n0O1i0O_dataout AND NOT(n0Oli1i); + wire_n0lOl1ll_dataout <= n0lOilil AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllOlOl); + wire_n0lOl1O_dataout <= wire_n0O1iii_dataout AND NOT(n0Oli1i); + wire_n0lOlii_dataout <= wire_n0O1ill_dataout AND NOT(n0Oli1i); + wire_n0lOliiO_dataout <= wire_n0lOOi1l_dataout OR wire_niO01lOO_dataout; + wire_n0lOlil_dataout <= wire_n0O1ilO_dataout AND NOT(n0Oli1i); + wire_n0lOlili_dataout <= wire_n0lOOiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlill_dataout <= wire_n0lOOiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlilO_dataout <= wire_n0lOOili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOliO_dataout <= wire_n0O1iOi_dataout AND NOT(n0Oli1i); + wire_n0lOliOi_dataout <= wire_n0lOOill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOliOl_dataout <= wire_n0lOOilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOliOO_dataout <= wire_n0lOOiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOll0i_dataout <= wire_n0lOlO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOll0l_dataout <= wire_n0lOlOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOll0O_dataout <= wire_n0lOlOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOll1i_dataout <= wire_n0lOOiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOll1l_dataout <= wire_n0lOOiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOll1O_dataout <= wire_n0lOOl1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlli_dataout <= wire_n0O1iOl_dataout AND NOT(n0Oli1i); + wire_n0lOllii_dataout <= wire_n0lOlOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOllil_dataout <= wire_n0lOlOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlliO_dataout <= wire_n0lOlOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlll_dataout <= wire_n0O1iOO_dataout AND NOT(n0Oli1i); + wire_n0lOllli_dataout <= wire_n0lOlOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOllll_dataout <= wire_n0lOO1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlllO_dataout <= wire_n0O1i0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOllO_dataout <= wire_n0O1l1i_dataout AND NOT(n0Oli1i); + wire_n0lOllOi_dataout <= wire_n0O1i0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOllOl_dataout <= wire_n0O1i0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOllOO_dataout <= wire_n0O1i0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlO0i_dataout <= wire_n0lOO1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlO0l_dataout <= wire_n0lOO1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlO0O_dataout <= wire_n0lOlOOi_dataout AND NOT(niOllOOii); + wire_n0lOlO1i_dataout <= wire_n0O1i0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlO1l_dataout <= wire_n0O1i0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlO1O_dataout <= wire_n0O1iiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0lOlOi_dataout <= wire_n0O1l1l_dataout AND NOT(n0Oli1i); + wire_n0lOlOii_dataout <= wire_n0lOlOOl_dataout AND NOT(niOllOOii); + wire_n0lOlOil_dataout <= wire_n0lOlOOO_dataout AND NOT(niOllOOii); + wire_n0lOlOiO_dataout <= wire_n0lOO11i_dataout AND NOT(niOllOOii); + wire_n0lOlOl_dataout <= wire_n0O1l1O_dataout AND NOT(n0Oli1i); + wire_n0lOlOli_dataout <= wire_n0lOO11l_dataout AND NOT(niOllOOii); + wire_n0lOlOll_dataout <= wire_n0lOO11O_dataout AND NOT(niOllOOii); + wire_n0lOlOlO_dataout <= wire_n0lOO10i_dataout AND NOT(niOllOOii); + wire_n0lOlOO_dataout <= wire_n0O1l0i_dataout AND NOT(n0Oli1i); + wire_n0lOlOOi_dataout <= wire_n0lOO10l_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0ii; + wire_n0lOlOOl_dataout <= wire_n0lOO10l_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0il; + wire_n0lOlOOO_dataout <= wire_n0lOO10l_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0iO; + wire_n0lOO00l_dataout <= wire_n0lOO00O_dataout OR (wire_niO01ill_w_lg_n0O1ilii12468w(0) AND wire_n0lOl10l_w_lg_dataout12611w(0)); + wire_n0lOO00O_dataout <= wire_n0lOO0ii_dataout OR (wire_niO01ill_w_lg_n0O1ilii12468w(0) AND wire_n0lOl10l_w_lg_w_lg_w_lg_dataout12598w12604w12605w(0)); + wire_n0lOO01i_dataout <= wire_n0lOO01l_dataout OR n0O1illi; + wire_n0lOO01l_dataout <= wire_n0lOO01O_dataout OR (wire_niO01ill_w_lg_n0O1ilii12468w(0) AND (wire_n0lOl10l_dataout AND niOlO110O)); + wire_n0lOO01O_dataout <= wire_n0lOO00l_dataout OR (wire_niO01ill_w_lg_n0O1ilii12468w(0) AND (wire_n0lOl10l_dataout AND niOllOOOl)); + wire_n0lOO0i_dataout <= wire_n0O1lil_dataout AND NOT(n0Oli1i); + wire_n0lOO0ii_dataout <= n0lOliil AND nlOllOlOl; + wire_n0lOO0l_dataout <= wire_n0O1liO_dataout AND NOT(n0Oli1i); + wire_n0lOO0O_dataout <= wire_n0O1lli_dataout AND NOT(n0Oli1i); + wire_n0lOO10i_dataout <= wire_n0lOO10l_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0Oi; + wire_n0lOO11i_dataout <= wire_n0lOO10l_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0li; + wire_n0lOO11l_dataout <= wire_n0lOO10l_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0ll; + wire_n0lOO11O_dataout <= wire_n0lOO10l_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0lO; + wire_n0lOO1i_dataout <= wire_n0O1l0l_dataout AND NOT(n0Oli1i); + wire_n0lOO1iO_dataout <= wire_n0lOO1li_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12470w(0) AND wire_w_lg_niOlO100i12471w(0)); + wire_n0lOO1l_dataout <= wire_n0O1l0O_dataout AND NOT(n0Oli1i); + wire_n0lOO1li_dataout <= n0lOl0Ol AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlO100l12617w(0))); + wire_n0lOO1O_dataout <= wire_n0O1lii_dataout AND NOT(n0Oli1i); + wire_n0lOO1Ol_dataout <= n0lOliii WHEN nlOllOlOl = '1' ELSE wire_n0lOO1OO_dataout; + wire_n0lOO1OO_dataout <= wire_n0lOO01i_dataout OR niOlO11lO; + wire_n0lOOi1l_dataout <= wire_n0lOOi1O_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n0O1iliO AND n0lOli1l)) OR (n0O1iliO AND n0lOl0iO)); + wire_n0lOOi1O_dataout <= n0lOilil AND nlOllOlOl; + wire_n0lOOii_dataout <= wire_n0O1lll_dataout AND NOT(n0Oli1i); + wire_n0lOOiil_dataout <= wire_n0li0l1O_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOl1l_dataout; + wire_n0lOOiiO_dataout <= wire_n0li0l1i_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOl1O_dataout; + wire_n0lOOil_dataout <= wire_n0O1llO_dataout AND NOT(n0Oli1i); + wire_n0lOOili_dataout <= wire_n0li0iOl_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOl0i_dataout; + wire_n0lOOill_dataout <= wire_n0li0ilO_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOl0l_dataout; + wire_n0lOOilO_dataout <= wire_n0li0ili_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOl0O_dataout; + wire_n0lOOiO_dataout <= wire_n0O1lOi_dataout AND NOT(n0Oli1i); + wire_n0lOOiOi_dataout <= wire_n0li0iii_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOlii_dataout; + wire_n0lOOiOl_dataout <= wire_n0li0i0l_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOlil_dataout; + wire_n0lOOiOO_dataout <= wire_n0li0i1l_dataout WHEN niOlO101i = '1' ELSE wire_n0lOOliO_dataout; + wire_n0lOOl0i_dataout <= wire_n0lOOlOl_dataout OR niOlO11Ol; + wire_n0lOOl0l_dataout <= wire_n0lOOlOO_dataout OR niOlO11Ol; + wire_n0lOOl0O_dataout <= wire_n0lOOO1i_dataout OR niOlO11Ol; + wire_n0lOOl1i_dataout <= n0O1illO WHEN niOlO101i = '1' ELSE wire_n0lOOlli_dataout; + wire_n0lOOl1l_dataout <= wire_n0lOOllO_dataout AND NOT(niOlO11Ol); + wire_n0lOOl1O_dataout <= wire_n0lOOlOi_dataout AND NOT(niOlO11Ol); + wire_n0lOOli_dataout <= wire_n0O1lOl_dataout AND NOT(n0Oli1i); + wire_n0lOOlii_dataout <= wire_n0lOOO1l_dataout OR niOlO11Ol; + wire_n0lOOlil_dataout <= wire_n0lOOO1O_dataout AND NOT(niOlO11Ol); + wire_n0lOOliO_dataout <= wire_n0lOOO0i_dataout OR niOlO11Ol; + wire_n0lOOll_dataout <= wire_n0O1lOO_dataout AND NOT(n0Oli1i); + wire_n0lOOlli_dataout <= wire_n0lOOlll_dataout OR niOlO11Ol; + wire_n0lOOlll_dataout <= wire_n0lOOOOi_dataout AND NOT(niOlO11ll); + wire_n0lOOllO_dataout <= wire_n0lOOO0l_dataout AND NOT(niOlO11ll); + wire_n0lOOlO_dataout <= wire_n0O1O1i_dataout AND NOT(n0Oli1i); + wire_n0lOOlOi_dataout <= wire_n0lOOO0O_dataout AND NOT(niOlO11ll); + wire_n0lOOlOl_dataout <= wire_n0lOOOii_dataout AND NOT(niOlO11ll); + wire_n0lOOlOO_dataout <= wire_n0lOOOil_dataout AND NOT(niOlO11ll); + wire_n0lOOO0i_dataout <= wire_n0lOOOlO_dataout AND NOT(niOlO11ll); + wire_n0lOOO0l_dataout <= wire_n0lOOOOl_dataout AND NOT(niOlO11iO); + wire_n0lOOO0O_dataout <= wire_n0lOOOOO_dataout AND NOT(niOlO11iO); + wire_n0lOOO1i_dataout <= wire_n0lOOOiO_dataout AND NOT(niOlO11ll); + wire_n0lOOO1l_dataout <= wire_n0lOOOli_dataout AND NOT(niOlO11ll); + wire_n0lOOO1O_dataout <= wire_n0lOOOll_dataout AND NOT(niOlO11ll); + wire_n0lOOOi_dataout <= wire_n0O1O1l_dataout AND NOT(n0Oli1i); + wire_n0lOOOii_dataout <= wire_n0O1111i_dataout OR niOlO11iO; + wire_n0lOOOil_dataout <= wire_n0O1111l_dataout OR niOlO11iO; + wire_n0lOOOiO_dataout <= wire_n0O1111O_dataout OR niOlO11iO; + wire_n0lOOOl_dataout <= wire_n0O1O1O_dataout AND NOT(n0Oli1i); + wire_n0lOOOli_dataout <= wire_n0O1110i_dataout OR niOlO11iO; + wire_n0lOOOll_dataout <= wire_n0O1110l_dataout OR niOlO11iO; + wire_n0lOOOlO_dataout <= wire_n0O1110O_dataout AND NOT(niOlO11iO); + wire_n0lOOOO_dataout <= wire_n0O1O0i_dataout AND NOT(n0Oli1i); + wire_n0lOOOOi_dataout <= wire_n0O111ii_dataout OR niOlO11iO; + wire_n0lOOOOl_dataout <= wire_n0O111il_dataout OR niOlO11il; + wire_n0lOOOOO_dataout <= wire_n0O111iO_dataout AND NOT(niOlO11il); + wire_n0O0000i_dataout <= wire_n0O00i0l_dataout OR niOlO10Ol; + wire_n0O0000l_dataout <= wire_n0O00i0O_dataout OR niOlO10Ol; + wire_n0O0000O_dataout <= wire_n0O00iii_dataout OR niOlO10Ol; + wire_n0O0001i_dataout <= wire_n0O00i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0001l_dataout <= wire_n0O00i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0001O_dataout <= wire_n0O00i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O000i_dataout <= n0iOl0l AND NOT(n0Ol0Ol); + wire_n0O000ii_dataout <= wire_n0O00iil_dataout OR niOlO10Ol; + wire_n0O000il_dataout <= wire_n0O00iiO_dataout OR niOlO10Ol; + wire_n0O000iO_dataout <= wire_n0O00ili_dataout OR niOlO10Ol; + wire_n0O000l_dataout <= n0iOl0O AND NOT(n0Ol0Ol); + wire_n0O000li_dataout <= wire_n0O00ill_dataout OR niOlO10Ol; + wire_n0O000ll_dataout <= wire_n0O00ilO_dataout OR niOlO10Ol; + wire_n0O000lO_dataout <= wire_n0O00iOi_dataout OR niOlO10Ol; + wire_n0O000O_dataout <= n0iOlii AND NOT(n0Ol0Ol); + wire_n0O000Oi_dataout <= wire_n0O00iOl_dataout OR niOlO10Ol; + wire_n0O000Ol_dataout <= wire_n0O00iOO_dataout OR niOlO10Ol; + wire_n0O000OO_dataout <= wire_n0O00l1i_dataout OR niOlO10Ol; + wire_n0O0010i_dataout <= wire_n0O0000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0010l_dataout <= wire_n0O0000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0010O_dataout <= wire_n0O000ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0011O_dataout <= wire_n0O0000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001i_dataout <= n0iOl1l AND NOT(n0Ol0Ol); + wire_n0O001ii_dataout <= wire_n0O000il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001il_dataout <= wire_n0O000iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001iO_dataout <= wire_n0O000li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001l_dataout <= n0iOl1O AND NOT(n0Ol0Ol); + wire_n0O001li_dataout <= wire_n0O000ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001ll_dataout <= wire_n0O000lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001lO_dataout <= wire_n0O000Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001O_dataout <= n0iOl0i AND NOT(n0Ol0Ol); + wire_n0O001Oi_dataout <= wire_n0O000Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001Ol_dataout <= wire_n0O000OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O001OO_dataout <= wire_n0O00i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O00i0i_dataout <= wire_n0O00l0l_dataout OR niOlO10Ol; + wire_n0O00i0l_dataout <= n0O01lii WHEN niOlO10OO = '1' ELSE n0O01Oli; + wire_n0O00i0O_dataout <= n0O01O1O WHEN niOlO10OO = '1' ELSE n0O01Oll; + wire_n0O00i1i_dataout <= wire_n0O00l1l_dataout OR niOlO10Ol; + wire_n0O00i1l_dataout <= wire_n0O00l1O_dataout OR niOlO10Ol; + wire_n0O00i1O_dataout <= wire_n0O00l0i_dataout OR niOlO10Ol; + wire_n0O00ii_dataout <= n0iOlil AND NOT(n0Ol0Ol); + wire_n0O00iii_dataout <= n0O01O0i WHEN niOlO10OO = '1' ELSE n0O01OlO; + wire_n0O00iil_dataout <= n0O01O0l WHEN niOlO10OO = '1' ELSE (n0O01OOi XOR n0O01Oli); + wire_n0O00iiO_dataout <= n0O01O0O WHEN niOlO10OO = '1' ELSE (n0O01Oli XOR (n0O01OOl XOR n0O01Oll)); + wire_n0O00il_dataout <= n0iOliO AND NOT(n0Ol0Ol); + wire_n0O00ili_dataout <= n0O01Oii WHEN niOlO10OO = '1' ELSE (n0O01Oli XOR (n0O01Oll XOR (n0O01OOO XOR n0O01OlO))); + wire_n0O00ill_dataout <= n0O01Oil WHEN niOlO10OO = '1' ELSE (n0O01Oll XOR (n0O01OlO XOR (n0O0011i XOR n0O01OOi))); + wire_n0O00ilO_dataout <= n0O01OiO WHEN niOlO10OO = '1' ELSE (n0O01OlO XOR (n0O01OOi XOR (n0O0011l XOR n0O01OOl))); + wire_n0O00iO_dataout <= n0iOlli AND NOT(n0Ol0Ol); + wire_n0O00iOi_dataout <= n0O01Oli WHEN niOlO10OO = '1' ELSE (n0O01OOi XOR (n0O01OOl XOR (n0O01OOO XOR n0O01lii))); + wire_n0O00iOl_dataout <= n0O01Oll WHEN niOlO10OO = '1' ELSE (n0O01OOl XOR (n0O01OOO XOR (n0O0011i XOR n0O01O1O))); + wire_n0O00iOO_dataout <= n0O01OlO WHEN niOlO10OO = '1' ELSE (n0O01OOO XOR (n0O0011i XOR (n0O0011l XOR n0O01O0i))); + wire_n0O00l0i_dataout <= n0O0011i WHEN niOlO10OO = '1' ELSE n0O01Oil; + wire_n0O00l0l_dataout <= n0O0011l WHEN niOlO10OO = '1' ELSE n0O01OiO; + wire_n0O00l1i_dataout <= n0O01OOi WHEN niOlO10OO = '1' ELSE (n0O0011i XOR (n0O0011l XOR n0O01O0l)); + wire_n0O00l1l_dataout <= n0O01OOl WHEN niOlO10OO = '1' ELSE (n0O0011l XOR n0O01O0O); + wire_n0O00l1O_dataout <= n0O01OOO WHEN niOlO10OO = '1' ELSE n0O01Oii; + wire_n0O00li_dataout <= n0iOlll AND NOT(n0Ol0Ol); + wire_n0O00ll_dataout <= n0iOllO AND NOT(n0Ol0Ol); + wire_n0O00lO_dataout <= n0iOlOi AND NOT(n0Ol0Ol); + wire_n0O00Oi_dataout <= n0iOlOl AND NOT(n0Ol0Ol); + wire_n0O00Ol_dataout <= n0iOlOO AND NOT(n0Ol0Ol); + wire_n0O00OO_dataout <= n0iOO1i AND NOT(n0Ol0Ol); + wire_n0O0101i_dataout <= n0O1OiiO OR n111i10i; + wire_n0O010i_dataout <= n0iOi0l AND NOT(n0Ol0Ol); + wire_n0O010l_dataout <= n0iOi0O AND NOT(n0Ol0Ol); + wire_n0O010O_dataout <= n0iOiii AND NOT(n0Ol0Ol); + wire_n0O0110i_dataout <= n0O1O0OO WHEN niOlO10ll = '1' ELSE (n0O1Oi1O XOR (n0O1Oi0i XOR (n0O1Oiil XOR n0O1Oi0l))); + wire_n0O0110l_dataout <= n0O1Oi1i WHEN niOlO10ll = '1' ELSE (n0O1Oi0i XOR (n0O1Oi0l XOR (n0O1Oi0O XOR n0O1O1Oi))); + wire_n0O0110O_dataout <= n0O1Oi1l WHEN niOlO10ll = '1' ELSE (n0O1Oi0l XOR (n0O1Oi0O XOR (n0O1Oiii XOR n0O1O0iO))); + wire_n0O0111i_dataout <= n0O1O0lO WHEN niOlO10ll = '1' ELSE (n0O1Oi1i XOR (n0O1Oi0l XOR n0O1Oi1l)); + wire_n0O0111l_dataout <= n0O1O0Oi WHEN niOlO10ll = '1' ELSE (n0O1Oi1i XOR (n0O1Oi1l XOR (n0O1Oi0O XOR n0O1Oi1O))); + wire_n0O0111O_dataout <= n0O1O0Ol WHEN niOlO10ll = '1' ELSE (n0O1Oi1l XOR (n0O1Oi1O XOR (n0O1Oiii XOR n0O1Oi0i))); + wire_n0O011i_dataout <= n0iOi1l AND NOT(n0Ol0Ol); + wire_n0O011ii_dataout <= n0O1Oi1O WHEN niOlO10ll = '1' ELSE (n0O1Oi0O XOR (n0O1Oiii XOR (n0O1Oiil XOR n0O1O0li))); + wire_n0O011il_dataout <= n0O1Oi0i WHEN niOlO10ll = '1' ELSE (n0O1Oiii XOR (n0O1Oiil XOR n0O1O0ll)); + wire_n0O011iO_dataout <= n0O1Oi0l WHEN niOlO10ll = '1' ELSE (n0O1Oiil XOR n0O1O0lO); + wire_n0O011l_dataout <= n0iOi1O AND NOT(n0Ol0Ol); + wire_n0O011li_dataout <= n0O1Oi0O WHEN niOlO10ll = '1' ELSE n0O1O0Oi; + wire_n0O011ll_dataout <= n0O1Oiii WHEN niOlO10ll = '1' ELSE n0O1O0Ol; + wire_n0O011lO_dataout <= n0O1Oiil WHEN niOlO10ll = '1' ELSE n0O1O0OO; + wire_n0O011O_dataout <= n0iOi0i AND NOT(n0Ol0Ol); + wire_n0O011Ol_dataout <= wire_n0O011OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O011OO_dataout <= wire_n0O0101i_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n0O1OiiO) AND niOlO10lO)); + wire_n0O01ii_dataout <= n0iOiil AND NOT(n0Ol0Ol); + wire_n0O01il_dataout <= n0iOiiO AND NOT(n0Ol0Ol); + wire_n0O01iO_dataout <= n0iOili AND NOT(n0Ol0Ol); + wire_n0O01iOO_dataout <= wire_niO11ill_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11ill_dataout XOR n0O01Oli); + wire_n0O01iOO_w_lg_dataout12199w(0) <= NOT wire_n0O01iOO_dataout; + wire_n0O01l0l_dataout <= wire_niO11iiO_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11iiO_dataout XOR n0O01OlO); + wire_n0O01l0l_w_lg_dataout12195w(0) <= NOT wire_n0O01l0l_dataout; + wire_n0O01l1O_dataout <= wire_niO11ili_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11ili_dataout XOR n0O01Oll); + wire_n0O01l1O_w_lg_dataout12197w(0) <= NOT wire_n0O01l1O_dataout; + wire_n0O01li_dataout <= n0iOill AND NOT(n0Ol0Ol); + wire_n0O01lil_dataout <= wire_niO11iil_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11iil_dataout XOR n0O01OOi); + wire_n0O01lil_w_lg_dataout12193w(0) <= NOT wire_n0O01lil_dataout; + wire_n0O01ll_dataout <= n0iOilO AND NOT(n0Ol0Ol); + wire_n0O01lli_dataout <= wire_niO11iii_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11iii_dataout XOR n0O01OOl); + wire_n0O01lli_w_lg_dataout12191w(0) <= NOT wire_n0O01lli_dataout; + wire_n0O01llO_dataout <= wire_niO11i0O_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11i0O_dataout XOR n0O01OOO); + wire_n0O01llO_w_lg_dataout12189w(0) <= NOT wire_n0O01llO_dataout; + wire_n0O01lO_dataout <= n0iOiOi AND NOT(n0Ol0Ol); + wire_n0O01lOl_dataout <= wire_niO11i0l_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11i0l_dataout XOR n0O0011i); + wire_n0O01lOl_w_lg_dataout12187w(0) <= NOT wire_n0O01lOl_dataout; + wire_n0O01O1i_dataout <= wire_niO11i0i_dataout WHEN niOlO10Oi = '1' ELSE (wire_niO11i0i_dataout XOR n0O0011l); + wire_n0O01O1i_w_lg_dataout12185w(0) <= NOT wire_n0O01O1i_dataout; + wire_n0O01Oi_dataout <= n0iOiOl AND NOT(n0Ol0Ol); + wire_n0O01Ol_dataout <= n0iOiOO AND NOT(n0Ol0Ol); + wire_n0O01OO_dataout <= n0iOl1i AND NOT(n0Ol0Ol); + wire_n0O0i0i_dataout <= n0iOO0l AND NOT(n0Ol0Ol); + wire_n0O0i0l_dataout <= n0iOO0O AND NOT(n0Ol0Ol); + wire_n0O0i0O_dataout <= n0iOOii AND NOT(n0Ol0Ol); + wire_n0O0i1i_dataout <= n0iOO1l AND NOT(n0Ol0Ol); + wire_n0O0i1l_dataout <= n0iOO1O AND NOT(n0Ol0Ol); + wire_n0O0i1O_dataout <= n0iOO0i AND NOT(n0Ol0Ol); + wire_n0O0iii_dataout <= n0iOOil AND NOT(n0Ol0Ol); + wire_n0O0iil_dataout <= n0iOOiO AND NOT(n0Ol0Ol); + wire_n0O0iiO_dataout <= n0iOOli AND NOT(n0Ol0Ol); + wire_n0O0ili_dataout <= n0iOOll AND NOT(n0Ol0Ol); + wire_n0O0ill_dataout <= n0iOOlO AND NOT(n0Ol0Ol); + wire_n0O0ilO_dataout <= n0iOOOi AND NOT(n0Ol0Ol); + wire_n0O0iOi_dataout <= n0iOOOl AND NOT(n0Ol0Ol); + wire_n0O0iOiO_dataout <= wire_niO11i1O_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0iOl_dataout <= n0iOOOO AND NOT(n0Ol0Ol); + wire_n0O0iOli_dataout <= wire_n0O01O1i_dataout AND wire_niO110Ol_w_lg_dataout12091w(0); + wire_n0O0iOll_dataout <= wire_n0O01lOl_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0iOlO_dataout <= wire_n0O01llO_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0iOO_dataout <= n0l111i AND NOT(n0Ol0Ol); + wire_n0O0iOOi_dataout <= wire_n0O01lli_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0iOOl_dataout <= wire_n0O01lil_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0iOOO_dataout <= wire_n0O01l0l_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0l01i_dataout <= (niOlO011i AND n0O0l10l) AND n0Ol011O; + wire_n0O0l01l_dataout <= (n0OiOOil AND (wire_niO11i1l_dataout AND niOlO1lOO)) AND n0Ol011O; + wire_n0O0l0i_dataout <= n0l110l AND NOT(n0Ol0Ol); + wire_n0O0l0l_dataout <= n0l110O AND NOT(n0Ol0Ol); + wire_n0O0l0lO_dataout <= wire_n0O0li1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l0O_dataout <= n0l11ii AND NOT(n0Ol0Ol); + wire_n0O0l0Oi_dataout <= wire_n0O0llii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l0Ol_dataout <= wire_n0O0li1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l0OO_dataout <= wire_n0O0li1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l11i_dataout <= wire_n0O01l1O_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0l11l_dataout <= wire_n0O01iOO_dataout OR NOT(wire_niO110Ol_w_lg_dataout12091w(0)); + wire_n0O0l1i_dataout <= n0l111l AND NOT(n0Ol0Ol); + wire_n0O0l1ii_dataout <= wire_n0O0l1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l1il_dataout <= wire_n0O0l1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l1iO_dataout <= wire_n0O0l01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l1l_dataout <= n0l111O AND NOT(n0Ol0Ol); + wire_n0O0l1li_dataout <= wire_n0O0l01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0l1ll_dataout <= wire_n0O0l1lO_dataout AND n0Ol011O; + wire_n0O0l1lO_dataout <= n0O0l1Ol OR (n0Ol011O AND n0O0l11O); + wire_n0O0l1O_dataout <= n0l110i AND NOT(n0Ol0Ol); + wire_n0O0l1OO_dataout <= ((wire_niO11i1l_dataout AND niOlO1lOl) AND n0O0l10i) AND n0Ol011O; + wire_n0O0li0i_dataout <= n0O0l10O WHEN wire_niO01ill_w_lg_n0O0l0il12084w(0) = '1' ELSE wire_n0O0liiO_dataout; + wire_n0O0li0l_dataout <= wire_n0O0lili_dataout WHEN wire_niO01ill_w_lg_n0O0l0il12084w(0) = '1' ELSE wire_n0O0liii_dataout; + wire_n0O0li0O_dataout <= wire_n0O0lill_dataout WHEN wire_niO01ill_w_lg_n0O0l0il12084w(0) = '1' ELSE wire_n0O0liil_dataout; + wire_n0O0li1i_dataout <= wire_n0O0li0i_dataout AND NOT(niOlO1i1i); + wire_n0O0li1l_dataout <= wire_n0O0ll0l_dataout WHEN niOlO1i1i = '1' ELSE wire_n0O0li0l_dataout; + wire_n0O0li1O_dataout <= wire_n0O0ll0O_dataout WHEN niOlO1i1i = '1' ELSE wire_n0O0li0O_dataout; + wire_n0O0lii_dataout <= n0l11il AND NOT(n0Ol0Ol); + wire_n0O0liii_dataout <= wire_n0O0ll1i_dataout WHEN niOlO1Oil = '1' ELSE wire_n0O0lili_dataout; + wire_n0O0liil_dataout <= wire_n0O0ll1l_dataout WHEN niOlO1Oil = '1' ELSE wire_n0O0lill_dataout; + wire_n0O0liiO_dataout <= wire_n0O0ll1O_dataout WHEN niOlO1Oil = '1' ELSE n0O0l10O; + wire_n0O0lil_dataout <= n0l11iO AND NOT(n0Ol0Ol); + wire_n0O0lili_dataout <= n0O0l0iO AND NOT(niOlO1i1O); + wire_n0O0lill_dataout <= n0O0l0li AND NOT(niOlO1i1O); + wire_n0O0liO_dataout <= n0l11li AND NOT(n0Ol0Ol); + wire_n0O0ll0l_dataout <= n0O0l0iO OR niOlO1Oil; + wire_n0O0ll0O_dataout <= n0O0l0li AND NOT(niOlO1Oil); + wire_n0O0ll1i_dataout <= n0O0l0iO WHEN niOlO1i1l = '1' ELSE wire_n0O0ll0i_o(0); + wire_n0O0ll1l_dataout <= n0O0l0li WHEN niOlO1i1l = '1' ELSE wire_n0O0ll0i_o(1); + wire_n0O0ll1O_dataout <= n0O0l10O OR niOlO1i1l; + wire_n0O0lli_dataout <= n0l11ll AND NOT(n0Ol0Ol); + wire_n0O0llii_dataout <= wire_n0O0llil_dataout OR (niOlO1OOl AND (n0OiOlOO OR n0OiOiOO)); + wire_n0O0llil_dataout <= n0O0l0il AND NOT(niOlO1i1O); + wire_n0O0lll_dataout <= n0l11lO AND NOT(n0Ol0Ol); + wire_n0O0llO_dataout <= wire_n0O0O0l_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0il0lO; + wire_n0O0lO0i_dataout <= wire_n0O0lOli_dataout OR wire_niO01lOO_dataout; + wire_n0O0lO0l_dataout <= wire_n0O0lOll_dataout OR wire_niO01lOO_dataout; + wire_n0O0lO0O_dataout <= wire_n0O0lOlO_dataout OR wire_niO01lOO_dataout; + wire_n0O0lO1l_dataout <= wire_n0O0lOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0lO1O_dataout <= wire_n0O0lOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0lOi_dataout <= wire_n0O0O0O_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0il0Oi; + wire_n0O0lOii_dataout <= wire_n0O0lOOi_dataout OR wire_niO01lOO_dataout; + wire_n0O0lOil_dataout <= wire_n0O0lOOl_dataout OR niOlO1l1l; + wire_n0O0lOiO_dataout <= wire_n0O0lOOO_dataout AND NOT(niOlO1l1l); + wire_n0O0lOl_dataout <= wire_n0O0Oii_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0il0Ol; + wire_n0O0lOli_dataout <= wire_n0O0O11i_dataout OR niOlO1l1l; + wire_n0O0lOll_dataout <= wire_n0O0O11l_dataout AND NOT(niOlO1l1l); + wire_n0O0lOlO_dataout <= wire_n0O0O11O_dataout OR niOlO1l1l; + wire_n0O0lOO_dataout <= wire_n0O0Oil_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0il0OO; + wire_n0O0lOOi_dataout <= wire_n0O0O10i_dataout OR niOlO1l1l; + wire_n0O0lOOl_dataout <= wire_n0O0O10l_dataout AND n0O0l0ll; + wire_n0O0lOOO_dataout <= wire_n0O0O10O_dataout AND n0O0l0ll; + wire_n0O0O0i_dataout <= wire_n0O0OlO_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0ili0i; + wire_n0O0O0l_dataout <= wire_n0i0iil_dataout OR niOO0iill; + wire_n0O0O0O_dataout <= wire_n0i0iiO_dataout OR niOO0iill; + wire_n0O0O10i_dataout <= wire_n0O0O1li_dataout OR NOT(n0O0l0ll); + wire_n0O0O10l_dataout <= n0O0l0ll WHEN niOlO1i0l = '1' ELSE wire_n0O0O1ll_dataout; + wire_n0O0O10O_dataout <= niOlO1i0i AND NOT(niOlO1i0l); + wire_n0O0O11i_dataout <= wire_n0O0O1ii_dataout OR NOT(n0O0l0ll); + wire_n0O0O11l_dataout <= wire_n0O0O1il_dataout OR NOT(n0O0l0ll); + wire_n0O0O11O_dataout <= wire_n0O0O1iO_dataout OR NOT(n0O0l0ll); + wire_n0O0O1i_dataout <= wire_n0O0OiO_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0ili1i; + wire_n0O0O1ii_dataout <= wire_n0O0O1Oi_o(1) OR NOT(niOlO1i0l); + wire_n0O0O1il_dataout <= wire_n0O0O1Oi_o(2) OR NOT(niOlO1i0l); + wire_n0O0O1iO_dataout <= wire_n0O0O1Oi_o(3) OR NOT(niOlO1i0l); + wire_n0O0O1l_dataout <= wire_n0O0Oli_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0ili1l; + wire_n0O0O1li_dataout <= wire_n0O0O1Oi_o(4) OR NOT(niOlO1i0l); + wire_n0O0O1ll_dataout <= n0O0l0ll AND niOlO1i0i; + wire_n0O0O1O_dataout <= wire_n0O0Oll_dataout WHEN wire_ni1lOlO_w_lg_n0OiOOl3328w(0) = '1' ELSE n0ili1O; + wire_n0O0Oii_dataout <= wire_n0i0ili_dataout OR niOO0iill; + wire_n0O0Oil_dataout <= wire_n0i0ill_dataout OR niOO0iill; + wire_n0O0OiO_dataout <= wire_n0i0ilO_dataout OR niOO0iill; + wire_n0O0Oli_dataout <= wire_n0i0iOi_dataout OR niOO0iill; + wire_n0O0Oll_dataout <= wire_n0i0iOl_dataout OR niOO0iill; + wire_n0O0OlO_dataout <= wire_n0i0iOO_dataout OR niOO0iill; + wire_n0O0OO0i_dataout <= wire_n0Oi011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OO0l_dataout <= wire_n0Oi010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OO0O_dataout <= ((niOlO1Oil OR niOlO1Oii) OR niOlO1O0O) AND NOT(wire_niO01lOO_dataout); + wire_n0O0OO1O_dataout <= wire_n0Oi011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOii_dataout <= (n0OiOOil AND (niOlO011i OR niOlO1OlO)) AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOil_dataout <= wire_n0Oi1i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOiO_dataout <= wire_n0Oi1i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOl_dataout <= n0il00i AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0O0OOli_dataout <= wire_n0Oi1i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOll_dataout <= wire_n0Oi1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOlO_dataout <= wire_n0Oi1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOO_dataout <= n0il00l AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0O0OOOi_dataout <= wire_n0Oi1iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOOl_dataout <= wire_n0Oi1ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O0OOOO_dataout <= wire_n0Oi1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1000i_dataout <= wire_n0O100Oi_dataout AND NOT(niOllOOOl); + wire_n0O1000l_dataout <= wire_n0O100Ol_dataout OR niOllOOOl; + wire_n0O1000O_dataout <= wire_n0O100OO_dataout OR niOllOOOl; + wire_n0O1001i_dataout <= wire_n0O100li_dataout OR niOllOOOl; + wire_n0O1001l_dataout <= wire_n0O100ll_dataout OR niOllOOOl; + wire_n0O1001O_dataout <= wire_n0O100lO_dataout OR niOllOOOl; + wire_n0O100i_dataout <= wire_n0O01il_dataout AND NOT(n0Ol0OO); + wire_n0O100ii_dataout <= wire_n0O10i1i_dataout OR niOllOOOO; + wire_n0O100il_dataout <= wire_n0O10i1l_dataout AND NOT(niOllOOOO); + wire_n0O100iO_dataout <= wire_n0O10i1O_dataout OR niOllOOOO; + wire_n0O100l_dataout <= wire_n0O01iO_dataout AND NOT(n0Ol0OO); + wire_n0O100li_dataout <= wire_n0O10i0i_dataout AND NOT(niOllOOOO); + wire_n0O100ll_dataout <= wire_n0O10i0l_dataout OR niOllOOOO; + wire_n0O100lO_dataout <= wire_n0O10i0O_dataout OR niOllOOOO; + wire_n0O100O_dataout <= wire_n0O01li_dataout AND NOT(n0Ol0OO); + wire_n0O100Oi_dataout <= wire_n0O10iii_dataout AND NOT(niOllOOOO); + wire_n0O100Ol_dataout <= wire_n0O10iil_dataout OR niOllOOOO; + wire_n0O100OO_dataout <= wire_n0O10iiO_dataout AND NOT(niOllOOOO); + wire_n0O1010i_dataout <= wire_n0O101Oi_dataout AND NOT(niOllOOOi); + wire_n0O1010l_dataout <= wire_n0O101Ol_dataout AND NOT(niOllOOOi); + wire_n0O1010O_dataout <= wire_n0O101OO_dataout OR niOllOOOi; + wire_n0O101i_dataout <= wire_n0O010l_dataout AND NOT(n0Ol0OO); + wire_n0O101ii_dataout <= wire_n0O1001i_dataout OR niOllOOOi; + wire_n0O101il_dataout <= wire_n0O1001l_dataout OR niOllOOOi; + wire_n0O101iO_dataout <= wire_n0O1001O_dataout OR niOllOOOi; + wire_n0O101l_dataout <= wire_n0O010O_dataout AND NOT(n0Ol0OO); + wire_n0O101li_dataout <= wire_n0O1000i_dataout AND NOT(niOllOOOi); + wire_n0O101ll_dataout <= wire_n0O1000l_dataout OR niOllOOOi; + wire_n0O101lO_dataout <= wire_n0O1000O_dataout OR niOllOOOi; + wire_n0O101O_dataout <= wire_n0O01ii_dataout AND NOT(n0Ol0OO); + wire_n0O101Oi_dataout <= wire_n0O100ii_dataout AND NOT(niOllOOOl); + wire_n0O101Ol_dataout <= wire_n0O100il_dataout AND NOT(niOllOOOl); + wire_n0O101OO_dataout <= wire_n0O100iO_dataout OR niOllOOOl; + wire_n0O10i0i_dataout <= wire_n0O10iOi_dataout OR niOlO111i; + wire_n0O10i0l_dataout <= wire_n0O10iOl_dataout OR niOlO111i; + wire_n0O10i0O_dataout <= wire_n0O10iOO_dataout OR niOlO111i; + wire_n0O10i1i_dataout <= wire_n0O10ili_dataout AND NOT(niOlO111i); + wire_n0O10i1l_dataout <= wire_n0O10ill_dataout AND NOT(niOlO111i); + wire_n0O10i1O_dataout <= wire_n0O10ilO_dataout OR niOlO111i; + wire_n0O10ii_dataout <= wire_n0O01ll_dataout AND NOT(n0Ol0OO); + wire_n0O10iii_dataout <= wire_n0O10l1i_dataout AND NOT(niOlO111i); + wire_n0O10iil_dataout <= wire_n0O10l1l_dataout OR niOlO111i; + wire_n0O10iiO_dataout <= wire_n0O10l1O_dataout OR niOlO111i; + wire_n0O10il_dataout <= wire_n0O01lO_dataout AND NOT(n0Ol0OO); + wire_n0O10ili_dataout <= wire_n0O10l0i_dataout AND NOT(niOlO111l); + wire_n0O10ill_dataout <= wire_n0O10l0l_dataout OR niOlO111l; + wire_n0O10ilO_dataout <= wire_n0O10l0O_dataout AND NOT(niOlO111l); + wire_n0O10iO_dataout <= wire_n0O01Oi_dataout AND NOT(n0Ol0OO); + wire_n0O10iOi_dataout <= wire_n0O10lii_dataout OR niOlO111l; + wire_n0O10iOl_dataout <= wire_n0O10lil_dataout AND NOT(niOlO111l); + wire_n0O10iOO_dataout <= wire_n0O10liO_dataout AND NOT(niOlO111l); + wire_n0O10l0i_dataout <= n0lOi00l WHEN niOlO111O = '1' ELSE wire_n0O10lOi_dataout; + wire_n0O10l0l_dataout <= n0lOil1l WHEN niOlO111O = '1' ELSE wire_n0O10lOl_dataout; + wire_n0O10l0O_dataout <= n0lOil1O WHEN niOlO111O = '1' ELSE wire_n0O10lOO_dataout; + wire_n0O10l1i_dataout <= wire_n0O10lli_dataout OR niOlO111l; + wire_n0O10l1l_dataout <= wire_n0O10lll_dataout AND NOT(niOlO111l); + wire_n0O10l1O_dataout <= wire_n0O10llO_dataout AND NOT(niOlO111l); + wire_n0O10li_dataout <= wire_n0O01Ol_dataout AND NOT(n0Ol0OO); + wire_n0O10lii_dataout <= n0lOil0i WHEN niOlO111O = '1' ELSE wire_n0O10O1i_dataout; + wire_n0O10lil_dataout <= n0lOil0l WHEN niOlO111O = '1' ELSE wire_n0O10O1l_dataout; + wire_n0O10liO_dataout <= n0lOil0O WHEN niOlO111O = '1' ELSE wire_n0O10O1O_dataout; + wire_n0O10ll_dataout <= wire_n0O01OO_dataout AND NOT(n0Ol0OO); + wire_n0O10lli_dataout <= n0lOilii WHEN niOlO111O = '1' ELSE wire_n0O10O0i_dataout; + wire_n0O10lll_dataout <= n0ll1ili WHEN niOlO111O = '1' ELSE wire_n0O10O0l_dataout; + wire_n0O10llO_dataout <= wire_n0O10O0O_dataout AND NOT(niOlO111O); + wire_n0O10lO_dataout <= wire_n0O001i_dataout AND NOT(n0Ol0OO); + wire_n0O10lOi_dataout <= n0lOl1Oi WHEN niOlO110i = '1' ELSE wire_n0O10Oii_dataout; + wire_n0O10lOl_dataout <= n0lOl1Ol WHEN niOlO110i = '1' ELSE wire_n0O10Oil_dataout; + wire_n0O10lOO_dataout <= n0lOl1OO WHEN niOlO110i = '1' ELSE wire_n0O10OiO_dataout; + wire_n0O10O0i_dataout <= n0lOl00i WHEN niOlO110i = '1' ELSE wire_n0O10OOi_dataout; + wire_n0O10O0l_dataout <= n0lOl00l WHEN niOlO110i = '1' ELSE wire_n0O10OOl_dataout; + wire_n0O10O0O_dataout <= wire_n0O10OOO_dataout AND NOT(niOlO110i); + wire_n0O10O1i_dataout <= n0lOl01i WHEN niOlO110i = '1' ELSE wire_n0O10Oli_dataout; + wire_n0O10O1l_dataout <= n0lOl01l WHEN niOlO110i = '1' ELSE wire_n0O10Oll_dataout; + wire_n0O10O1O_dataout <= n0lOl01O WHEN niOlO110i = '1' ELSE wire_n0O10OlO_dataout; + wire_n0O10Oi_dataout <= wire_n0O001l_dataout AND NOT(n0Ol0OO); + wire_n0O10Oii_dataout <= wire_n0O1i11i_dataout AND NOT(niOlO110l); + wire_n0O10Oil_dataout <= wire_n0O1i11l_dataout AND NOT(niOlO110l); + wire_n0O10OiO_dataout <= wire_n0O1i11O_dataout OR niOlO110l; + wire_n0O10Ol_dataout <= wire_n0O001O_dataout AND NOT(n0Ol0OO); + wire_n0O10Oli_dataout <= wire_n0O1i10i_dataout OR niOlO110l; + wire_n0O10Oll_dataout <= wire_n0O1i10l_dataout OR niOlO110l; + wire_n0O10OlO_dataout <= wire_n0O1i10O_dataout OR niOlO110l; + wire_n0O10OO_dataout <= wire_n0O000i_dataout AND NOT(n0Ol0OO); + wire_n0O10OOi_dataout <= wire_n0O1i1ii_dataout AND NOT(niOlO110l); + wire_n0O10OOl_dataout <= wire_n0O1i1il_dataout OR niOlO110l; + wire_n0O10OOO_dataout <= wire_n0O1i1iO_dataout OR niOlO110l; + wire_n0O1100i_dataout <= wire_n0O1010O_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O110Oi_dataout; + wire_n0O1100l_dataout <= wire_n0O101ii_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O110Ol_dataout; + wire_n0O1100O_dataout <= wire_n0O101il_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O110OO_dataout; + wire_n0O1101i_dataout <= wire_n0O110li_dataout AND NOT(niOlO11ii); + wire_n0O1101l_dataout <= wire_n0O1010i_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O110ll_dataout; + wire_n0O1101O_dataout <= wire_n0O1010l_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O110lO_dataout; + wire_n0O110i_dataout <= wire_n0O1Oil_dataout AND NOT(n0Ol0OO); + wire_n0O110ii_dataout <= wire_n0O101iO_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O11i1i_dataout; + wire_n0O110il_dataout <= wire_n0O101li_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O11i1l_dataout; + wire_n0O110iO_dataout <= wire_n0O101ll_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O11i1O_dataout; + wire_n0O110l_dataout <= wire_n0O1OiO_dataout AND NOT(n0Ol0OO); + wire_n0O110li_dataout <= wire_n0O101lO_dataout WHEN wire_n0lOl10l_dataout = '1' ELSE wire_n0O11i0i_dataout; + wire_n0O110ll_dataout <= wire_n0O11i0l_dataout AND NOT(niOllOOlO); + wire_n0O110lO_dataout <= wire_n0O11i0O_dataout AND NOT(niOllOOlO); + wire_n0O110O_dataout <= wire_n0O1Oli_dataout AND NOT(n0Ol0OO); + wire_n0O110Oi_dataout <= wire_n0O11iii_dataout OR niOllOOlO; + wire_n0O110Ol_dataout <= wire_n0O11iil_dataout OR niOllOOlO; + wire_n0O110OO_dataout <= wire_n0O11iiO_dataout OR niOllOOlO; + wire_n0O1110i_dataout <= wire_n0O111Oi_dataout OR niOlO11il; + wire_n0O1110l_dataout <= wire_n0O111Ol_dataout AND NOT(niOlO11il); + wire_n0O1110O_dataout <= wire_n0O111OO_dataout OR niOlO11il; + wire_n0O1111i_dataout <= wire_n0O111li_dataout OR niOlO11il; + wire_n0O1111l_dataout <= wire_n0O111ll_dataout AND NOT(niOlO11il); + wire_n0O1111O_dataout <= wire_n0O111lO_dataout OR niOlO11il; + wire_n0O111i_dataout <= wire_n0O1O0l_dataout AND NOT(n0Oli1i); + wire_n0O111ii_dataout <= wire_n0O1101i_dataout AND NOT(niOlO11il); + wire_n0O111il_dataout <= wire_n0O1101l_dataout AND NOT(niOlO11ii); + wire_n0O111iO_dataout <= wire_n0O1101O_dataout OR niOlO11ii; + wire_n0O111l_dataout <= wire_n0O1O0O_dataout AND NOT(n0Oli1i); + wire_n0O111li_dataout <= wire_n0O1100i_dataout AND NOT(niOlO11ii); + wire_n0O111ll_dataout <= wire_n0O1100l_dataout OR niOlO11ii; + wire_n0O111lO_dataout <= wire_n0O1100O_dataout AND NOT(niOlO11ii); + wire_n0O111O_dataout <= wire_n0O1Oii_dataout AND NOT(n0Oli1i); + wire_n0O111Oi_dataout <= wire_n0O110ii_dataout AND NOT(niOlO11ii); + wire_n0O111Ol_dataout <= wire_n0O110il_dataout OR niOlO11ii; + wire_n0O111OO_dataout <= wire_n0O110iO_dataout AND NOT(niOlO11ii); + wire_n0O11i0i_dataout <= wire_n0O11iOi_dataout OR niOllOOlO; + wire_n0O11i0l_dataout <= wire_n0O11iOl_dataout AND NOT(niOllOOll); + wire_n0O11i0O_dataout <= wire_n0O11iOO_dataout AND NOT(niOllOOll); + wire_n0O11i1i_dataout <= wire_n0O11ili_dataout OR niOllOOlO; + wire_n0O11i1l_dataout <= wire_n0O11ill_dataout AND NOT(niOllOOlO); + wire_n0O11i1O_dataout <= wire_n0O11ilO_dataout OR niOllOOlO; + wire_n0O11ii_dataout <= wire_n0O1Oll_dataout AND NOT(n0Ol0OO); + wire_n0O11iii_dataout <= wire_n0O11l1i_dataout OR niOllOOll; + wire_n0O11iil_dataout <= wire_n0O11l1l_dataout OR niOllOOll; + wire_n0O11iiO_dataout <= wire_n0O11l1O_dataout OR niOllOOll; + wire_n0O11il_dataout <= wire_n0O1OlO_dataout AND NOT(n0Ol0OO); + wire_n0O11ili_dataout <= wire_n0O11l0i_dataout OR niOllOOll; + wire_n0O11ill_dataout <= wire_n0O11l0l_dataout OR niOllOOll; + wire_n0O11ilO_dataout <= wire_n0O11l0O_dataout AND NOT(niOllOOll); + wire_n0O11iO_dataout <= wire_n0O1OOi_dataout AND NOT(n0Ol0OO); + wire_n0O11iOi_dataout <= wire_n0O11lii_dataout OR niOllOOll; + wire_n0O11iOl_dataout <= wire_n0O11lil_dataout AND NOT(niOllOOli); + wire_n0O11iOO_dataout <= wire_n0O11liO_dataout AND NOT(niOllOOli); + wire_n0O11l0i_dataout <= wire_n0O11lOi_dataout AND NOT(niOllOOli); + wire_n0O11l0l_dataout <= wire_n0O11lOl_dataout AND NOT(niOllOOli); + wire_n0O11l0O_dataout <= wire_n0O11lOO_dataout AND NOT(niOllOOli); + wire_n0O11l1i_dataout <= wire_n0O11lli_dataout AND NOT(niOllOOli); + wire_n0O11l1l_dataout <= wire_n0O11lll_dataout AND NOT(niOllOOli); + wire_n0O11l1O_dataout <= wire_n0O11llO_dataout AND NOT(niOllOOli); + wire_n0O11li_dataout <= wire_n0O1OOl_dataout AND NOT(n0Ol0OO); + wire_n0O11lii_dataout <= wire_n0O11O1i_dataout AND NOT(niOllOOli); + wire_n0O11lil_dataout <= n0lOi00l WHEN niOllOOil = '1' ELSE wire_n0O11O1l_dataout; + wire_n0O11liO_dataout <= n0lOil1l WHEN niOllOOil = '1' ELSE wire_n0O11O1O_dataout; + wire_n0O11ll_dataout <= wire_n0O1OOO_dataout AND NOT(n0Ol0OO); + wire_n0O11lli_dataout <= n0lOil1O WHEN niOllOOil = '1' ELSE wire_n0O11O0i_dataout; + wire_n0O11lll_dataout <= n0lOil0i WHEN niOllOOil = '1' ELSE wire_n0O11O0l_dataout; + wire_n0O11llO_dataout <= n0lOil0l WHEN niOllOOil = '1' ELSE wire_n0O11O0O_dataout; + wire_n0O11lO_dataout <= wire_n0O011i_dataout AND NOT(n0Ol0OO); + wire_n0O11lOi_dataout <= n0lOil0O WHEN niOllOOil = '1' ELSE wire_n0O11Oii_dataout; + wire_n0O11lOl_dataout <= n0lOilii WHEN niOllOOil = '1' ELSE wire_n0O11Oil_dataout; + wire_n0O11lOO_dataout <= n0ll1ili WHEN niOllOOil = '1' ELSE wire_n0O11OiO_dataout; + wire_n0O11O0i_dataout <= n0lOl1OO WHEN niOllOOiO = '1' ELSE wire_n0li0iOl_dataout; + wire_n0O11O0l_dataout <= n0lOl01i WHEN niOllOOiO = '1' ELSE wire_n0li0ilO_dataout; + wire_n0O11O0O_dataout <= n0lOl01l WHEN niOllOOiO = '1' ELSE wire_n0li0ili_dataout; + wire_n0O11O1i_dataout <= wire_n0O11Oli_dataout AND NOT(niOllOOil); + wire_n0O11O1l_dataout <= n0lOl1Oi WHEN niOllOOiO = '1' ELSE wire_n0li0l1O_dataout; + wire_n0O11O1O_dataout <= n0lOl1Ol WHEN niOllOOiO = '1' ELSE wire_n0li0l1i_dataout; + wire_n0O11Oi_dataout <= wire_n0O011l_dataout AND NOT(n0Ol0OO); + wire_n0O11Oii_dataout <= n0lOl01O WHEN niOllOOiO = '1' ELSE wire_n0li0iii_dataout; + wire_n0O11Oil_dataout <= n0lOl00i WHEN niOllOOiO = '1' ELSE wire_n0li0i0l_dataout; + wire_n0O11OiO_dataout <= n0lOl00l WHEN niOllOOiO = '1' ELSE wire_n0li0i1l_dataout; + wire_n0O11Ol_dataout <= wire_n0O011O_dataout AND NOT(n0Ol0OO); + wire_n0O11Oli_dataout <= n0O1illO AND NOT(niOllOOiO); + wire_n0O11OO_dataout <= wire_n0O010i_dataout AND NOT(n0Ol0OO); + wire_n0O1i0i_dataout <= wire_n0O00il_dataout AND NOT(n0Ol0OO); + wire_n0O1i0ii_dataout <= wire_n0O1i0Oi_dataout AND NOT(niOlO101O); + wire_n0O1i0il_dataout <= wire_n0O1i0Ol_dataout AND NOT(niOlO101O); + wire_n0O1i0iO_dataout <= wire_n0O1i0OO_dataout AND NOT(niOlO101O); + wire_n0O1i0l_dataout <= wire_n0O00iO_dataout AND NOT(n0Ol0OO); + wire_n0O1i0li_dataout <= wire_n0O1ii1i_dataout AND NOT(niOlO101O); + wire_n0O1i0ll_dataout <= wire_n0O1ii1l_dataout AND NOT(niOlO101O); + wire_n0O1i0lO_dataout <= wire_n0O1ii1O_dataout AND NOT(niOlO101O); + wire_n0O1i0O_dataout <= wire_n0O00li_dataout AND NOT(n0Ol0OO); + wire_n0O1i0Oi_dataout <= wire_n0O1ii0i_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOl0OO; + wire_n0O1i0Ol_dataout <= wire_n0O1ii0l_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOli1i; + wire_n0O1i0OO_dataout <= wire_n0O1ii0O_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOli1l; + wire_n0O1i10i_dataout <= n0lOl01i OR niOlO110O; + wire_n0O1i10l_dataout <= n0lOl01l OR niOlO110O; + wire_n0O1i10O_dataout <= n0lOl01O OR niOlO110O; + wire_n0O1i11i_dataout <= n0lOl1Oi AND NOT(niOlO110O); + wire_n0O1i11l_dataout <= n0lOl1Ol AND NOT(niOlO110O); + wire_n0O1i11O_dataout <= n0lOl1OO OR niOlO110O; + wire_n0O1i1i_dataout <= wire_n0O000l_dataout AND NOT(n0Ol0OO); + wire_n0O1i1ii_dataout <= n0lOl00i OR niOlO110O; + wire_n0O1i1il_dataout <= n0lOl00l OR niOlO110O; + wire_n0O1i1iO_dataout <= n0lOl00O OR niOlO110O; + wire_n0O1i1l_dataout <= wire_n0O000O_dataout AND NOT(n0Ol0OO); + wire_n0O1i1O_dataout <= wire_n0O00ii_dataout AND NOT(n0Ol0OO); + wire_n0O1ii0i_dataout <= wire_n0O1iili_o(0) WHEN niOlO101l = '1' ELSE n0lOl0OO; + wire_n0O1ii0l_dataout <= wire_n0O1iili_o(1) WHEN niOlO101l = '1' ELSE n0lOli1i; + wire_n0O1ii0O_dataout <= wire_n0O1iili_o(2) WHEN niOlO101l = '1' ELSE n0lOli1l; + wire_n0O1ii1i_dataout <= wire_n0O1iiii_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOli1O; + wire_n0O1ii1l_dataout <= wire_n0O1iiil_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOli0i; + wire_n0O1ii1O_dataout <= wire_n0O1iiiO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0lOli0l; + wire_n0O1iii_dataout <= wire_n0O00ll_dataout AND NOT(n0Ol0OO); + wire_n0O1iiii_dataout <= wire_n0O1iili_o(3) WHEN niOlO101l = '1' ELSE n0lOli1O; + wire_n0O1iiil_dataout <= wire_n0O1iili_o(4) WHEN niOlO101l = '1' ELSE n0lOli0i; + wire_n0O1iiiO_dataout <= wire_n0O1iili_o(5) WHEN niOlO101l = '1' ELSE n0lOli0l; + wire_n0O1iil_dataout <= wire_n0O00lO_dataout AND NOT(n0Ol0OO); + wire_n0O1iiO_dataout <= wire_n0O00Oi_dataout AND NOT(n0Ol0OO); + wire_n0O1iiOO_dataout <= wire_n0O1il1i_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12465w(0) AND wire_w_lg_niOlO100O12466w(0)); + wire_n0O1il1i_dataout <= n0lOli0O AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlO10ii12474w(0))); + wire_n0O1ili_dataout <= wire_n0O00Ol_dataout AND NOT(n0Ol0OO); + wire_n0O1ill_dataout <= wire_n0O00OO_dataout AND NOT(n0Ol0OO); + wire_n0O1ilO_dataout <= wire_n0O0i1i_dataout AND NOT(n0Ol0OO); + wire_n0O1iO0O_dataout <= wire_n0O1l1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOi_dataout <= wire_n0O0i1l_dataout AND NOT(n0Ol0OO); + wire_n0O1iOii_dataout <= wire_n0O1l01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOil_dataout <= wire_n0O1l01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOiO_dataout <= wire_n0O1l1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOl_dataout <= wire_n0O0i1O_dataout AND NOT(n0Ol0OO); + wire_n0O1iOli_dataout <= n0O1iliO AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOll_dataout <= nlOllOlOl AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOlO_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12470w(0) AND wire_w_lg_niOlO100i12471w(0)) AND wire_niO01ill_w_lg_n0O1ilii12468w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOO_dataout <= wire_n0O0i0i_dataout AND NOT(n0Ol0OO); + wire_n0O1iOOi_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w12465w(0) AND wire_w_lg_niOlO100O12466w(0)) AND wire_niO01ill_w_lg_n0O1ilii12468w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOOl_dataout <= wire_n0O1l01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1iOOO_dataout <= wire_n0O1l00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l00i_dataout <= wire_n0O1l00l_dataout AND NOT(niOlO10iO); + wire_n0O1l00l_dataout <= n1l001OO AND NOT(niOlO10il); + wire_n0O1l00O_dataout <= wire_n1llO0il_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1l0Ol_dataout; + wire_n0O1l01i_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0O1il0l; + wire_n0O1l01l_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0O1il0O; + wire_n0O1l01O_dataout <= wire_n1lllO0O_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1l00i_dataout; + wire_n0O1l0i_dataout <= wire_n0O0iil_dataout AND NOT(n0Ol0OO); + wire_n0O1l0ii_dataout <= wire_n1llO0iO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1l0OO_dataout; + wire_n0O1l0il_dataout <= wire_n1llO0li_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1li1i_dataout; + wire_n0O1l0iO_dataout <= wire_n1llO0ll_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1li1l_dataout; + wire_n0O1l0l_dataout <= wire_n0O0iiO_dataout AND NOT(n0Ol0OO); + wire_n0O1l0li_dataout <= wire_n1llO0lO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1li1O_dataout; + wire_n0O1l0ll_dataout <= wire_n1llO0Oi_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1li0i_dataout; + wire_n0O1l0lO_dataout <= wire_n1llO0Ol_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1li0l_dataout; + wire_n0O1l0O_dataout <= wire_n0O0ili_dataout AND NOT(n0Ol0OO); + wire_n0O1l0Oi_dataout <= wire_n1llO0OO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0O1li0O_dataout; + wire_n0O1l0Ol_dataout <= wire_nlOO10OOi_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1liii_dataout; + wire_n0O1l0OO_dataout <= wire_nlOO10OOl_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1liil_dataout; + wire_n0O1l10i_dataout <= wire_n0O1l0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l10l_dataout <= wire_n0O1l0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l10O_dataout <= wire_n0O1l0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l11i_dataout <= wire_n0O1l0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l11l_dataout <= wire_n0O1l0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l11O_dataout <= wire_n0O1l0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l1i_dataout <= wire_n0O0i0l_dataout AND NOT(n0Ol0OO); + wire_n0O1l1ii_dataout <= wire_n0O1l0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1l1l_dataout <= wire_n0O0i0O_dataout AND NOT(n0Ol0OO); + wire_n0O1l1O_dataout <= wire_n0O0iii_dataout AND NOT(n0Ol0OO); + wire_n0O1l1Ol_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0O1ilii; + wire_n0O1l1OO_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0lOO00i; + wire_n0O1li0i_dataout <= wire_nlOO1i11O_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1lilO_dataout; + wire_n0O1li0l_dataout <= wire_nlOO1i10i_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1liOi_dataout; + wire_n0O1li0O_dataout <= wire_nlOO1i10l_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1liOl_dataout; + wire_n0O1li1i_dataout <= wire_nlOO10OOO_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1liiO_dataout; + wire_n0O1li1l_dataout <= wire_nlOO1i11i_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1lili_dataout; + wire_n0O1li1O_dataout <= wire_nlOO1i11l_dataout WHEN niOlO10iO = '1' ELSE wire_n0O1lill_dataout; + wire_n0O1lii_dataout <= wire_n0O0ill_dataout AND NOT(n0Ol0OO); + wire_n0O1liii_dataout <= n1101l1i WHEN niOlO10il = '1' ELSE n1l001ii; + wire_n0O1liil_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOlO10il = '1' ELSE n1l001il; + wire_n0O1liiO_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOlO10il = '1' ELSE n1l001iO; + wire_n0O1lil_dataout <= wire_n0O0ilO_dataout AND NOT(n0Ol0OO); + wire_n0O1lili_dataout <= n1l001li AND NOT(niOlO10il); + wire_n0O1lill_dataout <= n1l001ll AND NOT(niOlO10il); + wire_n0O1lilO_dataout <= n1l001lO AND NOT(niOlO10il); + wire_n0O1liO_dataout <= wire_n0O0iOi_dataout AND NOT(n0Ol0OO); + wire_n0O1liOi_dataout <= n1l001Oi AND NOT(niOlO10il); + wire_n0O1liOl_dataout <= n1l001Ol AND NOT(niOlO10il); + wire_n0O1ll0i_dataout <= k_cnt(59) OR wire_n0O1llil_o; + wire_n0O1ll0l_dataout <= k_cnt(60) AND NOT(wire_n0O1llil_o); + wire_n0O1ll0O_dataout <= k_cnt(61) AND NOT(wire_n0O1llil_o); + wire_n0O1ll1l_dataout <= k_cnt(57) AND NOT(wire_n0O1llil_o); + wire_n0O1ll1O_dataout <= k_cnt(58) AND NOT(wire_n0O1llil_o); + wire_n0O1lli_dataout <= wire_n0O0iOl_dataout AND NOT(n0Ol0OO); + wire_n0O1llii_dataout <= k_cnt(62) AND NOT(wire_n0O1llil_o); + wire_n0O1lll_dataout <= wire_n0O0iOO_dataout AND NOT(n0Ol0OO); + wire_n0O1llO_dataout <= wire_n0O0l1i_dataout AND NOT(n0Ol0OO); + wire_n0O1lOi_dataout <= wire_n0O0l1l_dataout AND NOT(n0Ol0OO); + wire_n0O1lOl_dataout <= wire_n0O0l1O_dataout AND NOT(n0Ol0OO); + wire_n0O1lOO_dataout <= wire_n0O0l0i_dataout AND NOT(n0Ol0OO); + wire_n0O1O00l_dataout <= n0OO1i1O WHEN niOlO10li = '1' ELSE (n0OO1i1O XOR n0O1Oiii); + wire_n0O1O01i_dataout <= n0OO1i0l WHEN niOlO10li = '1' ELSE (n0OO1i0l XOR n0O1Oi0l); + wire_n0O1O01O_dataout <= n0OO1i0i WHEN niOlO10li = '1' ELSE (n0OO1i0i XOR n0O1Oi0O); + wire_n0O1O0i_dataout <= wire_n0O0lil_dataout AND NOT(n0Ol0OO); + wire_n0O1O0ii_dataout <= n0OO1i1l WHEN niOlO10li = '1' ELSE (n0OO1i1l XOR n0O1Oiil); + wire_n0O1O0l_dataout <= wire_n0O0liO_dataout AND NOT(n0Ol0OO); + wire_n0O1O0O_dataout <= wire_n0O0lli_dataout AND NOT(n0Ol0OO); + wire_n0O1O10O_dataout <= n0OO1iiO WHEN niOlO10li = '1' ELSE (n0OO1iiO XOR n0O1Oi1i); + wire_n0O1O1i_dataout <= wire_n0O0l0l_dataout AND NOT(n0Ol0OO); + wire_n0O1O1iO_dataout <= n0OO1iil WHEN niOlO10li = '1' ELSE (n0OO1iil XOR n0O1Oi1l); + wire_n0O1O1l_dataout <= wire_n0O0l0O_dataout AND NOT(n0Ol0OO); + wire_n0O1O1ll_dataout <= n0OO1iii WHEN niOlO10li = '1' ELSE (n0OO1iii XOR n0O1Oi1O); + wire_n0O1O1O_dataout <= wire_n0O0lii_dataout AND NOT(n0Ol0OO); + wire_n0O1O1Ol_dataout <= n0OO1i0O WHEN niOlO10li = '1' ELSE (n0OO1i0O XOR n0O1Oi0i); + wire_n0O1Oii_dataout <= wire_n0O0lll_dataout AND NOT(n0Ol0OO); + wire_n0O1Oil_dataout <= n0iO0iO AND NOT(n0Ol0Ol); + wire_n0O1Oili_dataout <= wire_n0O1Olll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Oill_dataout <= wire_n0O1OllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1OilO_dataout <= wire_n0O1OlOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1OiO_dataout <= n0iO0li AND NOT(n0Ol0Ol); + wire_n0O1OiOi_dataout <= wire_n0O1OlOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1OiOl_dataout <= wire_n0O1OlOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1OiOO_dataout <= wire_n0O1OO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Ol0i_dataout <= wire_n0O1OO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Ol0l_dataout <= wire_n0O1OO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Ol0O_dataout <= wire_n0O1OOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Ol1i_dataout <= wire_n0O1OO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Ol1l_dataout <= wire_n0O1OO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Ol1O_dataout <= wire_n0O1OO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Oli_dataout <= n0iO0ll AND NOT(n0Ol0Ol); + wire_n0O1Olii_dataout <= wire_n0O1OOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Olil_dataout <= wire_n0O1OOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1OliO_dataout <= wire_n0O1OOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Oll_dataout <= n0iO0lO AND NOT(n0Ol0Ol); + wire_n0O1Olli_dataout <= wire_n0O1OOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0O1Olll_dataout <= wire_n0O1OOlO_dataout OR niOlO10lO; + wire_n0O1OllO_dataout <= wire_n0O1OOOi_dataout OR niOlO10lO; + wire_n0O1OlO_dataout <= n0iO0Oi AND NOT(n0Ol0Ol); + wire_n0O1OlOi_dataout <= wire_n0O1OOOl_dataout OR niOlO10lO; + wire_n0O1OlOl_dataout <= wire_n0O1OOOO_dataout OR niOlO10lO; + wire_n0O1OlOO_dataout <= wire_n0O0111i_dataout OR niOlO10lO; + wire_n0O1OO0i_dataout <= wire_n0O0110l_dataout OR niOlO10lO; + wire_n0O1OO0l_dataout <= wire_n0O0110O_dataout OR niOlO10lO; + wire_n0O1OO0O_dataout <= wire_n0O011ii_dataout OR niOlO10lO; + wire_n0O1OO1i_dataout <= wire_n0O0111l_dataout OR niOlO10lO; + wire_n0O1OO1l_dataout <= wire_n0O0111O_dataout OR niOlO10lO; + wire_n0O1OO1O_dataout <= wire_n0O0110i_dataout OR niOlO10lO; + wire_n0O1OOi_dataout <= n0iO0Ol AND NOT(n0Ol0Ol); + wire_n0O1OOii_dataout <= wire_n0O011il_dataout OR niOlO10lO; + wire_n0O1OOil_dataout <= wire_n0O011iO_dataout OR niOlO10lO; + wire_n0O1OOiO_dataout <= wire_n0O011li_dataout OR niOlO10lO; + wire_n0O1OOl_dataout <= n0iO0OO AND NOT(n0Ol0Ol); + wire_n0O1OOli_dataout <= wire_n0O011ll_dataout OR niOlO10lO; + wire_n0O1OOll_dataout <= wire_n0O011lO_dataout OR niOlO10lO; + wire_n0O1OOlO_dataout <= n0O1O1Oi WHEN niOlO10ll = '1' ELSE n0O1Oi1i; + wire_n0O1OOO_dataout <= n0iOi1i AND NOT(n0Ol0Ol); + wire_n0O1OOOi_dataout <= n0O1O0iO WHEN niOlO10ll = '1' ELSE n0O1Oi1l; + wire_n0O1OOOl_dataout <= n0O1O0li WHEN niOlO10ll = '1' ELSE n0O1Oi1O; + wire_n0O1OOOO_dataout <= n0O1O0ll WHEN niOlO10ll = '1' ELSE (n0O1Oi0i XOR n0O1Oi1i); + wire_n0Oi000i_dataout <= wire_n0Oi0ilO_dataout AND NOT(niOlO1O0i); + wire_n0Oi000l_dataout <= wire_n0Oi0iOi_dataout AND NOT(niOlO1O0i); + wire_n0Oi000O_dataout <= wire_n0Oi0iOl_dataout AND NOT(niOlO1O0i); + wire_n0Oi001i_dataout <= wire_n0Oi0iiO_dataout AND NOT(niOlO1O0i); + wire_n0Oi001l_dataout <= wire_n0Oi0ili_dataout AND NOT(niOlO1O0i); + wire_n0Oi001O_dataout <= wire_n0Oi0ill_dataout AND NOT(niOlO1O0i); + wire_n0Oi00ii_dataout <= wire_n0Oi0iOO_dataout AND NOT(niOlO1O0i); + wire_n0Oi00il_dataout <= wire_n0Oi0l0O_dataout AND NOT(niOlO1O0i); + wire_n0Oi00iO_dataout <= wire_n0Oi0lOO_dataout AND NOT(niOlO1O0i); + wire_n0Oi00li_dataout <= n0O0OO1l WHEN n0Oii10l = '1' ELSE n0O0lO1i; + wire_n0Oi00ll_dataout <= n0Oii11l WHEN n0Oii10l = '1' ELSE n0O0O01l; + wire_n0Oi00lO_dataout <= n0Oii11O WHEN n0Oii10l = '1' ELSE n0O0O01O; + wire_n0Oi00Oi_dataout <= n0Oii1ii WHEN n0Oii10l = '1' ELSE n0O0O0Ol; + wire_n0Oi00Ol_dataout <= n0Oii1il WHEN n0Oii10l = '1' ELSE n0O0O0OO; + wire_n0Oi00OO_dataout <= n0Oii1iO WHEN n0Oii10l = '1' ELSE n0O0Oi1i; + wire_n0Oi010i_dataout <= wire_n0Oi00lO_dataout AND NOT(niOlO1O0i); + wire_n0Oi010l_dataout <= wire_n0Oi00Oi_dataout AND NOT(niOlO1O0i); + wire_n0Oi010O_dataout <= wire_n0Oi00Ol_dataout AND NOT(niOlO1O0i); + wire_n0Oi011i_dataout <= n0O0OlOO WHEN niOlO1O0i = '1' ELSE wire_n0Oi0lOl_dataout; + wire_n0Oi011l_dataout <= wire_n0Oi00li_dataout AND NOT(niOlO1O0i); + wire_n0Oi011O_dataout <= wire_n0Oi00ll_dataout AND NOT(niOlO1O0i); + wire_n0Oi01ii_dataout <= wire_n0Oi00OO_dataout AND NOT(niOlO1O0i); + wire_n0Oi01il_dataout <= wire_n0Oi0i1i_dataout AND NOT(niOlO1O0i); + wire_n0Oi01iO_dataout <= wire_n0Oi0i1l_dataout AND NOT(niOlO1O0i); + wire_n0Oi01li_dataout <= wire_n0Oi0i1O_dataout AND NOT(niOlO1O0i); + wire_n0Oi01ll_dataout <= wire_n0Oi0i0i_dataout AND NOT(niOlO1O0i); + wire_n0Oi01lO_dataout <= wire_n0Oi0i0l_dataout AND NOT(niOlO1O0i); + wire_n0Oi01Oi_dataout <= wire_n0Oi0i0O_dataout AND NOT(niOlO1O0i); + wire_n0Oi01Ol_dataout <= wire_n0Oi0iii_dataout AND NOT(niOlO1O0i); + wire_n0Oi01OO_dataout <= wire_n0Oi0iil_dataout AND NOT(niOlO1O0i); + wire_n0Oi0i0i_dataout <= n0Oii1Oi WHEN n0Oii10l = '1' ELSE n0O0Oi0l; + wire_n0Oi0i0l_dataout <= n0Oii1Ol WHEN n0Oii10l = '1' ELSE n0O0Oi0O; + wire_n0Oi0i0O_dataout <= n0Oii1OO WHEN n0Oii10l = '1' ELSE n0O0Oiii; + wire_n0Oi0i1i_dataout <= n0Oii1li WHEN n0Oii10l = '1' ELSE n0O0Oi1l; + wire_n0Oi0i1l_dataout <= n0Oii1ll WHEN n0Oii10l = '1' ELSE n0O0Oi1O; + wire_n0Oi0i1O_dataout <= n0Oii1lO WHEN n0Oii10l = '1' ELSE n0O0Oi0i; + wire_n0Oi0iii_dataout <= n0Oii01i WHEN n0Oii10l = '1' ELSE n0O0Oiil; + wire_n0Oi0iil_dataout <= n0Oii01l WHEN n0Oii10l = '1' ELSE n0O0OiiO; + wire_n0Oi0iiO_dataout <= n0Oii01O WHEN n0Oii10l = '1' ELSE n0O0Oili; + wire_n0Oi0ili_dataout <= n0Oii00i WHEN n0Oii10l = '1' ELSE n0O0Oill; + wire_n0Oi0ill_dataout <= n0Oii00l WHEN n0Oii10l = '1' ELSE n0O0OilO; + wire_n0Oi0ilO_dataout <= n0Oii00O WHEN n0Oii10l = '1' ELSE n0O0OiOi; + wire_n0Oi0iOi_dataout <= n0Oii0ii WHEN n0Oii10l = '1' ELSE n0O0OiOl; + wire_n0Oi0iOl_dataout <= n0Oii0il WHEN n0Oii10l = '1' ELSE n0O0OiOO; + wire_n0Oi0iOO_dataout <= n0Oii0iO WHEN n0Oii10l = '1' ELSE n0O0Ol1i; + wire_n0Oi0l0i_dataout <= n0Oii0Oi WHEN n0Oii10l = '1' ELSE n0O0Ol0l; + wire_n0Oi0l0l_dataout <= n0Oii0Ol WHEN n0Oii10l = '1' ELSE n0O0Ol0O; + wire_n0Oi0l0O_dataout <= n0Oii0OO WHEN n0Oii10l = '1' ELSE n0O0Olii; + wire_n0Oi0l1i_dataout <= n0Oii0li WHEN n0Oii10l = '1' ELSE n0O0Ol1l; + wire_n0Oi0l1l_dataout <= n0Oii0ll WHEN n0Oii10l = '1' ELSE n0O0Ol1O; + wire_n0Oi0l1O_dataout <= n0Oii0lO WHEN n0Oii10l = '1' ELSE n0O0Ol0i; + wire_n0Oi0lii_dataout <= n0Oiii1i WHEN n0Oii10l = '1' ELSE n0O0Olil; + wire_n0Oi0lil_dataout <= n0Oiii1l WHEN n0Oii10l = '1' ELSE n0O0OliO; + wire_n0Oi0liO_dataout <= n0Oiii1O WHEN n0Oii10l = '1' ELSE n0O0Olli; + wire_n0Oi0lli_dataout <= n0Oiii0i WHEN n0Oii10l = '1' ELSE n0O0Olll; + wire_n0Oi0lll_dataout <= n0Oiii0l WHEN n0Oii10l = '1' ELSE n0O0OllO; + wire_n0Oi0llO_dataout <= n0Oiii0O WHEN n0Oii10l = '1' ELSE n0O0OlOi; + wire_n0Oi0lOi_dataout <= n0Oiiiii WHEN n0Oii10l = '1' ELSE n0O0OlOl; + wire_n0Oi0lOl_dataout <= n0Oiiiil WHEN n0Oii10l = '1' ELSE n0O0OlOO; + wire_n0Oi0lOO_dataout <= n0OiiiiO WHEN n0Oii10l = '1' ELSE n0O0OO1i; + wire_n0Oi100i_dataout <= wire_n0Oi1O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi100l_dataout <= wire_n0Oi1O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi100O_dataout <= wire_n0Oi1O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi101i_dataout <= wire_n0Oi000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi101l_dataout <= wire_n0Oi000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi101O_dataout <= wire_n0Oi00ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10i_dataout <= n0il0iO AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0Oi10ii_dataout <= wire_n0Oi1Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10il_dataout <= wire_n0Oi1Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10iO_dataout <= wire_n0Oi00il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10l_dataout <= n0il0li AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0Oi10li_dataout <= wire_n0Oi1OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10ll_dataout <= wire_n0Oi1Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10lO_dataout <= wire_n0Oi1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10O_dataout <= n0il0ll AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0Oi10Oi_dataout <= wire_n0Oi1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10Ol_dataout <= wire_n0Oi1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi10OO_dataout <= wire_n0Oi1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi110i_dataout <= wire_n0Oi01il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi110l_dataout <= wire_n0Oi01iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi110O_dataout <= wire_n0Oi01li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi111i_dataout <= wire_n0Oi010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi111l_dataout <= wire_n0Oi010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi111O_dataout <= wire_n0Oi01ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11i_dataout <= n0il00O AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0Oi11ii_dataout <= wire_n0Oi01ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11il_dataout <= wire_n0Oi01lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11iO_dataout <= wire_n0Oi01Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11l_dataout <= n0il0ii AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0Oi11li_dataout <= wire_n0Oi01Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11ll_dataout <= wire_n0Oi01OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11lO_dataout <= wire_n0Oi001i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11O_dataout <= n0il0il AND NOT(wire_ni1lOlO_w_lg_n0OiOOl3328w(0)); + wire_n0Oi11Oi_dataout <= wire_n0Oi001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11Ol_dataout <= wire_n0Oi001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi11OO_dataout <= wire_n0Oi000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi1i0i_dataout <= wire_n0Oi1ilO_dataout AND NOT(niOlO1ilO); + wire_n0Oi1i0l_dataout <= wire_n0Oi1iOi_dataout AND NOT(niOlO1ilO); + wire_n0Oi1i0O_dataout <= wire_n0Oi1iOl_dataout AND NOT(niOlO1ilO); + wire_n0Oi1i1i_dataout <= wire_n0Oi1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi1i1l_dataout <= wire_n0Oi011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi1i1O_dataout <= wire_n0Oi00iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oi1iii_dataout <= wire_n0Oi1iOO_dataout AND NOT(niOlO1ilO); + wire_n0Oi1iil_dataout <= wire_n0Oi1l1i_dataout AND NOT(niOlO1ilO); + wire_n0Oi1iiO_dataout <= wire_n0Oi1l1l_dataout AND NOT(niOlO1ilO); + wire_n0Oi1ili_dataout <= wire_n0Oi1l1O_dataout AND NOT(niOlO1ilO); + wire_n0Oi1ill_dataout <= wire_n0Oi1l0i_dataout AND NOT(niOlO1ilO); + wire_n0Oi1ilO_dataout <= wire_n0Oi1l0l_dataout OR niOlO1ill; + wire_n0Oi1iOi_dataout <= wire_n0Oi1l0O_dataout AND NOT(niOlO1ill); + wire_n0Oi1iOl_dataout <= wire_n0Oi1lii_dataout AND NOT(niOlO1ill); + wire_n0Oi1iOO_dataout <= wire_n0Oi1lil_dataout AND NOT(niOlO1ill); + wire_n0Oi1l0i_dataout <= wire_n0Oi1llO_dataout AND NOT(niOlO1ill); + wire_n0Oi1l0l_dataout <= wire_n0Oi1lOi_o(0) WHEN niOlO1iiO = '1' ELSE n0O0O00O; + wire_n0Oi1l0O_dataout <= wire_n0Oi1lOi_o(1) WHEN niOlO1iiO = '1' ELSE n0O0O0ii; + wire_n0Oi1l1i_dataout <= wire_n0Oi1liO_dataout AND NOT(niOlO1ill); + wire_n0Oi1l1l_dataout <= wire_n0Oi1lli_dataout AND NOT(niOlO1ill); + wire_n0Oi1l1O_dataout <= wire_n0Oi1lll_dataout AND NOT(niOlO1ill); + wire_n0Oi1lii_dataout <= wire_n0Oi1lOi_o(2) WHEN niOlO1iiO = '1' ELSE n0O0O0il; + wire_n0Oi1lil_dataout <= wire_n0Oi1lOi_o(3) WHEN niOlO1iiO = '1' ELSE n0O0O0iO; + wire_n0Oi1liO_dataout <= wire_n0Oi1lOi_o(4) WHEN niOlO1iiO = '1' ELSE n0O0O0li; + wire_n0Oi1lli_dataout <= wire_n0Oi1lOi_o(5) WHEN niOlO1iiO = '1' ELSE n0O0O0ll; + wire_n0Oi1lll_dataout <= wire_n0Oi1lOi_o(6) WHEN niOlO1iiO = '1' ELSE n0O0O0lO; + wire_n0Oi1llO_dataout <= wire_n0Oi1lOi_o(7) WHEN niOlO1iiO = '1' ELSE n0O0O0Oi; + wire_n0Oi1O0i_dataout <= n0O0Ol1l WHEN niOlO1O0i = '1' ELSE wire_n0Oi0l1i_dataout; + wire_n0Oi1O0l_dataout <= n0O0Ol1O WHEN niOlO1O0i = '1' ELSE wire_n0Oi0l1l_dataout; + wire_n0Oi1O0O_dataout <= n0O0Ol0i WHEN niOlO1O0i = '1' ELSE wire_n0Oi0l1O_dataout; + wire_n0Oi1Oii_dataout <= n0O0Ol0l WHEN niOlO1O0i = '1' ELSE wire_n0Oi0l0i_dataout; + wire_n0Oi1Oil_dataout <= n0O0Ol0O WHEN niOlO1O0i = '1' ELSE wire_n0Oi0l0l_dataout; + wire_n0Oi1OiO_dataout <= n0O0Olil WHEN niOlO1O0i = '1' ELSE wire_n0Oi0lii_dataout; + wire_n0Oi1Oli_dataout <= n0O0OliO WHEN niOlO1O0i = '1' ELSE wire_n0Oi0lil_dataout; + wire_n0Oi1Oll_dataout <= n0O0Olli WHEN niOlO1O0i = '1' ELSE wire_n0Oi0liO_dataout; + wire_n0Oi1OlO_dataout <= n0O0Olll WHEN niOlO1O0i = '1' ELSE wire_n0Oi0lli_dataout; + wire_n0Oi1OOi_dataout <= n0O0OllO WHEN niOlO1O0i = '1' ELSE wire_n0Oi0lll_dataout; + wire_n0Oi1OOl_dataout <= n0O0OlOi WHEN niOlO1O0i = '1' ELSE wire_n0Oi0llO_dataout; + wire_n0Oi1OOO_dataout <= n0O0OlOl WHEN niOlO1O0i = '1' ELSE wire_n0Oi0lOi_dataout; + wire_n0OiiiOO_dataout <= wire_n0Oillli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiil0i_dataout <= (wire_w_lg_w_lg_w_lg_niOlO1lOi11936w11938w11939w(0) AND wire_niO01ill_w_lg_n0Oii10O11940w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0Oiil0l_dataout <= wire_n0Oil0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiil0O_dataout <= wire_n0OiliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiil1i_dataout <= wire_n0Oill0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiil1l_dataout <= wire_n0OilliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiil1O_dataout <= ((wire_w_lg_niOlO1OlO11942w(0) AND (wire_w_lg_niOlO1O1i11943w(0) AND wire_w_lg_w_lg_niOlO011i11806w11944w(0))) AND (wire_w_lg_w_lg_w_lg_niOlO1l1l11947w11951w11952w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n0Oiilii_dataout <= wire_n0Oill1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiilil_dataout <= wire_n0Oill1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiliO_dataout <= wire_n0Oill0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiilli_dataout <= wire_n0Oill0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oiilll_dataout <= wire_n0Oillii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiillO_dataout <= wire_n0Oillil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiilO_dataout <= n0Oi0il AND NOT(niOO0iiOl); + wire_n0OiilOi_dataout <= wire_n0OillOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiilOl_dataout <= wire_n0OillOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiilOO_dataout <= wire_n0OilO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiO0i_dataout <= wire_n0OilO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiO0l_dataout <= wire_n0OilO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiO0O_dataout <= wire_n0Oillll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiO1i_dataout <= wire_n0OilO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiO1l_dataout <= wire_n0OilO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiO1O_dataout <= wire_n0OilO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOi_dataout <= n0Oi0iO AND NOT(niOO0iiOl); + wire_n0OiiOii_dataout <= wire_n0OilllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOil_dataout <= wire_n0OillOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOiO_dataout <= wire_n0OilOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOl_dataout <= n0Oi0li AND NOT(niOO0iiOl); + wire_n0OiiOli_dataout <= wire_n0OilOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOll_dataout <= wire_n0OilOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOlO_dataout <= wire_n0OilOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOO_dataout <= n0Oi0ll AND NOT(niOO0iiOl); + wire_n0OiiOOi_dataout <= wire_n0OilOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOOl_dataout <= wire_n0OilOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiiOOO_dataout <= wire_n0OilOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil0i_dataout <= n0Oi0OO AND NOT(niOO0iiOl); + wire_n0Oil0l_dataout <= n0Oii1i AND NOT(niOO0iiOl); + wire_n0Oil0ll_dataout <= wire_n0Oil0lO_dataout AND NOT(niOlO1O1i); + wire_n0Oil0lO_dataout <= wire_n0Oil0Oi_dataout OR (wire_w_lg_niOlO1Oli11925w(0) AND wire_w_lg_w_lg_niOlO1OiO11914w11926w(0)); + wire_n0Oil0O_dataout <= n0Oii1l AND NOT(niOO0iiOl); + wire_n0Oil0Oi_dataout <= wire_n0Oil0Ol_dataout OR (wire_w_lg_niOlO1OiO11914w(0) AND (wire_w_lg_w_lg_niOlO1l0l11916w11917w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n0OiiiOi11919w11921w11922w(0))); + wire_n0Oil0Ol_dataout <= wire_n0Oil0OO_dataout OR (wire_w_lg_niOlO1OiO11914w(0) AND niOlO1l0i); + wire_n0Oil0OO_dataout <= n0Oii10O OR (wire_n0Oiliii_o AND (((niOlO1lOi XOR n0Oii1il) OR (niOlO1lli XOR n0Oii1ii)) OR (NOT (n0Oii1il XOR n0Oii1ii)))); + wire_n0Oil10i_dataout <= wire_n0OiO11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil10l_dataout <= wire_n0OiO11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil10O_dataout <= wire_n0OiO10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil11i_dataout <= wire_n0OilOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil11l_dataout <= wire_n0OilOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil11O_dataout <= wire_n0OiO11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil1i_dataout <= n0Oi0lO AND NOT(niOO0iiOl); + wire_n0Oil1ii_dataout <= wire_n0OiO10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil1il_dataout <= wire_n0OiO10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Oil1iO_dataout <= wire_n0OiO1ii_dataout OR wire_niO01lOO_dataout; + wire_n0Oil1l_dataout <= n0Oi0Oi AND NOT(niOO0iiOl); + wire_n0Oil1li_dataout <= wire_n0OiO1il_dataout OR wire_niO01lOO_dataout; + wire_n0Oil1ll_dataout <= wire_n0OiO1iO_dataout OR wire_niO01lOO_dataout; + wire_n0Oil1lO_dataout <= wire_n0OiO1li_dataout OR wire_niO01lOO_dataout; + wire_n0Oil1O_dataout <= n0Oi0Ol AND NOT(niOO0iiOl); + wire_n0Oilii_dataout <= n0Oii1O AND NOT(niOO0iiOl); + wire_n0Oilil_dataout <= n0Oii0i AND NOT(niOO0iiOl); + wire_n0OiliO_dataout <= n0Oii0l AND NOT(niOO0iiOl); + wire_n0OiliOO_dataout <= niOlO1lli WHEN wire_n0Oill1O_o = '1' ELSE n0Oii1ii; + wire_n0Oill0i_dataout <= wire_niO11iil_dataout WHEN niOlO1l1O = '1' ELSE n0Oii11l; + wire_n0Oill0l_dataout <= wire_niO11i0i_dataout WHEN niOlO1l1O = '1' ELSE n0Oii1li; + wire_n0Oill0O_dataout <= wire_niO11i0l_dataout WHEN niOlO1l1O = '1' ELSE n0Oii1ll; + wire_n0Oill1i_dataout <= niOlO1lOi WHEN wire_n0Oill1O_o = '1' ELSE n0Oii1il; + wire_n0Oill1l_dataout <= (wire_niO11i1l_dataout AND (niOlO1llO OR niOlO1lOO)) WHEN wire_n0Oill1O_o = '1' ELSE n0Oii1iO; + wire_n0Oilli_dataout <= n0Oii0O AND NOT(niOO0iiOl); + wire_n0Oillii_dataout <= wire_niO11i0O_dataout WHEN niOlO1l1O = '1' ELSE n0Oii1lO; + wire_n0Oillil_dataout <= wire_niO11iii_dataout WHEN niOlO1l1O = '1' ELSE n0Oii1Oi; + wire_n0OilliO_dataout <= wire_niO11ill_dataout WHEN niOlO1l0i = '1' ELSE n0Oii11O; + wire_n0Oilll_dataout <= n0Oiiii AND NOT(niOO0iiOl); + wire_n0Oillli_dataout <= wire_niO11ili_dataout WHEN niOlO1l0i = '1' ELSE n0O0OO1l; + wire_n0Oillll_dataout <= wire_niO11i0l_dataout WHEN niOlO1l0i = '1' ELSE n0Oii0ii; + wire_n0OilllO_dataout <= wire_niO11i0O_dataout WHEN niOlO1l0i = '1' ELSE n0Oii0il; + wire_n0OillO_dataout <= n0Oiiil AND NOT(niOO0iiOl); + wire_n0OillOi_dataout <= n0Oii0iO AND NOT(niOlO1l0i); + wire_n0OillOl_dataout <= wire_niO11i0i_dataout WHEN niOlO1l0l = '1' ELSE n0Oii1Ol; + wire_n0OillOO_dataout <= wire_niO11i0l_dataout WHEN niOlO1l0l = '1' ELSE n0Oii1OO; + wire_n0OilO0i_dataout <= wire_niO11iiO_dataout WHEN niOlO1l0l = '1' ELSE n0Oii00i; + wire_n0OilO0l_dataout <= wire_niO11ili_dataout WHEN niOlO1l0l = '1' ELSE n0Oii00l; + wire_n0OilO0O_dataout <= wire_niO11ill_dataout WHEN niOlO1l0l = '1' ELSE n0Oii00O; + wire_n0OilO1i_dataout <= wire_niO11i0O_dataout WHEN niOlO1l0l = '1' ELSE n0Oii01i; + wire_n0OilO1l_dataout <= wire_niO11iii_dataout WHEN niOlO1l0l = '1' ELSE n0Oii01l; + wire_n0OilO1O_dataout <= wire_niO11iil_dataout WHEN niOlO1l0l = '1' ELSE n0Oii01O; + wire_n0OilOi_dataout <= n0OiiiO AND NOT(niOO0iiOl); + wire_n0OilOii_dataout <= wire_niO11i0i_dataout WHEN niOlO1lil = '1' ELSE n0Oii0li; + wire_n0OilOil_dataout <= wire_niO11i0l_dataout WHEN niOlO1lil = '1' ELSE n0Oii0ll; + wire_n0OilOiO_dataout <= wire_niO11i0O_dataout WHEN niOlO1lil = '1' ELSE n0Oii0lO; + wire_n0OilOl_dataout <= n0Oiili AND NOT(niOO0iiOl); + wire_n0OilOli_dataout <= wire_niO11iii_dataout WHEN niOlO1lil = '1' ELSE n0Oii0Oi; + wire_n0OilOll_dataout <= wire_niO11iil_dataout WHEN niOlO1lil = '1' ELSE n0Oii0Ol; + wire_n0OilOlO_dataout <= niOlO1Oli WHEN niOlO1lil = '1' ELSE n0Oii0OO; + wire_n0OilOOi_dataout <= wire_niO11i0i_dataout WHEN niOlO1O1i = '1' ELSE n0Oiii1i; + wire_n0OilOOl_dataout <= wire_niO11i0l_dataout WHEN niOlO1O1i = '1' ELSE n0Oiii1l; + wire_n0OilOOO_dataout <= wire_niO11i0O_dataout WHEN niOlO1O1i = '1' ELSE n0Oiii1O; + wire_n0OiO01i_dataout <= wire_n0OiO00i_o(2) AND niOlO1lii; + wire_n0OiO01l_dataout <= wire_n0OiO00i_o(3) AND niOlO1lii; + wire_n0OiO01O_dataout <= wire_n0OiO00i_o(4) AND niOlO1lii; + wire_n0OiO10i_dataout <= wire_niO11ili_dataout WHEN niOlO1O1i = '1' ELSE n0Oiiiii; + wire_n0OiO10l_dataout <= wire_niO11ill_dataout WHEN niOlO1O1i = '1' ELSE n0Oiiiil; + wire_n0OiO10O_dataout <= niOlO1Oli WHEN niOlO1O1i = '1' ELSE n0OiiiiO; + wire_n0OiO11i_dataout <= wire_niO11iii_dataout WHEN niOlO1O1i = '1' ELSE n0Oiii0i; + wire_n0OiO11l_dataout <= wire_niO11iil_dataout WHEN niOlO1O1i = '1' ELSE n0Oiii0l; + wire_n0OiO11O_dataout <= wire_niO11iiO_dataout WHEN niOlO1O1i = '1' ELSE n0Oiii0O; + wire_n0OiO1ii_dataout <= wire_n0OiO1ll_dataout OR niOlO1O1i; + wire_n0OiO1il_dataout <= wire_n0OiO1lO_dataout AND NOT(niOlO1O1i); + wire_n0OiO1iO_dataout <= wire_n0OiO1Oi_dataout OR niOlO1O1i; + wire_n0OiO1li_dataout <= wire_n0OiO1Ol_dataout OR niOlO1O1i; + wire_n0OiO1ll_dataout <= wire_n0OiO1OO_dataout WHEN wire_w_lg_niOlO1l0O11876w(0) = '1' ELSE n0Oiiili; + wire_n0OiO1lO_dataout <= wire_n0OiO01i_dataout WHEN wire_w_lg_niOlO1l0O11876w(0) = '1' ELSE n0Oiiill; + wire_n0OiO1Oi_dataout <= wire_n0OiO01l_dataout WHEN wire_w_lg_niOlO1l0O11876w(0) = '1' ELSE n0OiiilO; + wire_n0OiO1Ol_dataout <= wire_n0OiO01O_dataout WHEN wire_w_lg_niOlO1l0O11876w(0) = '1' ELSE n0OiiiOi; + wire_n0OiO1OO_dataout <= wire_n0OiO00i_o(1) AND niOlO1lii; + wire_n0OiOl0i_dataout <= wire_n0OiOlil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiOl0l_dataout <= wire_n0OiOliO_dataout AND NOT(niOlO1O1l); + wire_n0OiOl0O_dataout <= wire_n0OiOlli_dataout AND NOT(niOlO1O1l); + wire_n0OiOl1i_dataout <= wire_n0OiOl0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiOl1l_dataout <= wire_n0OiOl0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiOl1O_dataout <= wire_n0OiOlii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OiOlii_dataout <= wire_n0OiOlll_dataout AND NOT(niOlO1O1l); + wire_n0OiOlil_dataout <= wire_n0OiOllO_dataout AND NOT(niOlO1O1l); + wire_n0OiOliO_dataout <= wire_n0OiOlOi_o(0) WHEN wire_niO01ill_w_lg_n0OiOiOl11832w(0) = '1' ELSE n0OiiiOl; + wire_n0OiOlli_dataout <= wire_n0OiOlOi_o(1) WHEN wire_niO01ill_w_lg_n0OiOiOl11832w(0) = '1' ELSE n0OiOilO; + wire_n0OiOlll_dataout <= wire_n0OiOlOi_o(2) WHEN wire_niO01ill_w_lg_n0OiOiOl11832w(0) = '1' ELSE n0OiOiOi; + wire_n0OiOllO_dataout <= wire_n0OiOlOi_o(3) OR NOT(wire_niO01ill_w_lg_n0OiOiOl11832w(0)); + wire_n0OiOOli_dataout <= (niOlO011i AND n0OiOO1i) AND NOT(wire_niO01lOO_dataout); + wire_n0OiOOll_dataout <= (niOlO011i AND n0OiOO1l) AND NOT(wire_niO01lOO_dataout); + wire_n0OiOOlO_dataout <= (wire_w_lg_w_lg_w_lg_niOlO1OOl11803w11804w11805w(0) OR (wire_w_lg_niOlO011i11806w(0) AND (wire_w_lg_niOlO1OOl11807w(0) AND (n0OiOO0l AND niOlO1O0l)))) AND NOT(wire_niO01lOO_dataout); + wire_n0OiOOOi_dataout <= niOlO1Oil AND NOT(wire_niO01lOO_dataout); + wire_n0OiOOOl_dataout <= (niOlO1OOl AND n0OiOOil) AND NOT(wire_niO01lOO_dataout); + wire_n0OiOOOO_dataout <= n0OiOO0l AND NOT(wire_niO01lOO_dataout); + wire_n0Ol000i_dataout <= wire_n0Oli01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol000l_dataout <= wire_n0Oli01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol000O_dataout <= wire_n0Oli00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol001i_dataout <= wire_n0Oli1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol001l_dataout <= wire_n0Oli1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol001O_dataout <= wire_n0Oli01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00ii_dataout <= wire_n0Oli00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00il_dataout <= wire_n0Ol0ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00iO_dataout <= wire_n0Ol0ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00li_dataout <= wire_n0Ol0ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00ll_dataout <= wire_n0Ol0iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00lO_dataout <= wire_n0Ol0iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00Oi_dataout <= wire_n0Ol0iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00Ol_dataout <= wire_n0Ol0l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol00OO_dataout <= wire_n0Ol0lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol01Oi_dataout <= wire_n0Oli10O_dataout OR wire_niO01lOO_dataout; + wire_n0Ol01Ol_dataout <= wire_n0Oli1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol01OO_dataout <= wire_n0Oli1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0i0i_dataout <= wire_n0OlOOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0i0l_dataout <= wire_n0OlOOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0i0O_dataout <= wire_n0OO111i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0i1i_dataout <= wire_n0OlOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0i1l_dataout <= wire_n0OlOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0i1O_dataout <= wire_n0OlOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0iii_dataout <= wire_n0OO100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0iil_dataout <= wire_n0Ol0O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0iiO_dataout <= wire_n0Ol0O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol0ili_dataout <= wire_n0Ol0l1l_dataout AND NOT(niOlO01ii); + wire_n0Ol0ill_dataout <= wire_n0Ol0l1O_dataout AND NOT(niOlO01ii); + wire_n0Ol0ilO_dataout <= wire_n0Ol0l0i_dataout AND NOT(niOlO01ii); + wire_n0Ol0iOi_dataout <= wire_n0Ol0l0l_dataout AND NOT(niOlO01ii); + wire_n0Ol0iOl_dataout <= wire_n0Ol0l0O_dataout AND NOT(niOlO01ii); + wire_n0Ol0iOO_dataout <= wire_n0Ol0lii_dataout AND NOT(niOlO01ii); + wire_n0Ol0l0i_dataout <= wire_n0Ol0liO_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol1OOi; + wire_n0Ol0l0l_dataout <= wire_n0Ol0liO_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol1OOl; + wire_n0Ol0l0O_dataout <= wire_n0Ol0liO_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol1OOO; + wire_n0Ol0l1i_dataout <= wire_n0Ol0lil_dataout AND NOT(niOlO01ii); + wire_n0Ol0l1l_dataout <= wire_n0Ol0liO_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol1Oll; + wire_n0Ol0l1O_dataout <= wire_n0Ol0liO_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol1OlO; + wire_n0Ol0lii_dataout <= wire_n0Ol0liO_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol011i; + wire_n0Ol0lil_dataout <= wire_n0Ol0liO_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol011l; + wire_n0Ol0lOi_dataout <= wire_n0Ol0lOl_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11557w(0) AND wire_w_lg_niOlO0i0i11558w(0)); + wire_n0Ol0lOl_dataout <= n0Ol011O AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlO0i0l11706w(0))); + wire_n0Ol0O0i_dataout <= wire_n0Ol0O0l_dataout OR niOlO00lO; + wire_n0Ol0O0l_dataout <= wire_n0Ol0O0O_dataout OR n0OO10Ol; + wire_n0Ol0O0O_dataout <= wire_n0Ol0Oii_dataout OR (wire_niO01ill_w_lg_n0OO10ll11555w(0) AND (wire_n0Ol1liO_dataout AND niOlO000O)); + wire_n0Ol0O1O_dataout <= n0Ol01ll WHEN nlOllOlOO = '1' ELSE wire_n0Ol0O0i_dataout; + wire_n0Ol0Oii_dataout <= wire_n0Ol0OiO_dataout OR (wire_niO01ill_w_lg_n0OO10ll11555w(0) AND (wire_n0Ol1liO_dataout AND niOlO01Ol)); + wire_n0Ol0OiO_dataout <= wire_n0Ol0Oli_dataout OR (wire_niO01ill_w_lg_n0OO10ll11555w(0) AND wire_n0Ol1liO_w_lg_dataout11700w(0)); + wire_n0Ol0Oli_dataout <= wire_n0Ol0Oll_dataout OR (wire_niO01ill_w_lg_n0OO10ll11555w(0) AND wire_n0Ol1liO_w_lg_w_lg_w_lg_dataout11687w11693w11694w(0)); + wire_n0Ol0Oll_dataout <= n0Ol01lO AND nlOllOlOO; + wire_n0Ol10Oi_dataout <= wire_n0Ol1i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol10Ol_dataout <= wire_n0Ol1i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol10OO_dataout <= wire_n0Ol1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol110i_dataout <= niOlO011i AND NOT(wire_niO01lOO_dataout); + wire_n0Ol111i_dataout <= niOlO1OOl AND NOT(wire_niO01lOO_dataout); + wire_n0Ol111l_dataout <= n0OiOOii AND NOT(wire_niO01lOO_dataout); + wire_n0Ol111O_dataout <= n0OiOOil AND NOT(wire_niO01lOO_dataout); + wire_n0Ol1i0i_dataout <= wire_n0Ol1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol1i0l_dataout <= wire_n0Ol1ilO_dataout AND NOT(niOlO010l); + wire_n0Ol1i0O_dataout <= wire_n0Ol1iOi_dataout AND NOT(niOlO010l); + wire_n0Ol1i1i_dataout <= wire_n0Ol1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol1i1l_dataout <= wire_n0Ol1iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol1i1O_dataout <= wire_n0Ol1ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0Ol1iii_dataout <= wire_n0Ol1iOl_dataout AND NOT(niOlO010l); + wire_n0Ol1iil_dataout <= wire_n0Ol1iOO_dataout AND NOT(niOlO010l); + wire_n0Ol1iiO_dataout <= wire_n0Ol1l1i_dataout AND NOT(niOlO010l); + wire_n0Ol1ili_dataout <= wire_n0Ol1l1l_dataout AND NOT(niOlO010l); + wire_n0Ol1ill_dataout <= wire_n0Ol1l1O_dataout AND NOT(niOlO010l); + wire_n0Ol1ilO_dataout <= wire_n0Ol1l0i_o(0) WHEN niOlO011O = '1' ELSE n0OiOOiO; + wire_n0Ol1iOi_dataout <= wire_n0Ol1l0i_o(1) WHEN niOlO011O = '1' ELSE n0Ol100O; + wire_n0Ol1iOl_dataout <= wire_n0Ol1l0i_o(2) WHEN niOlO011O = '1' ELSE n0Ol10ii; + wire_n0Ol1iOO_dataout <= wire_n0Ol1l0i_o(3) WHEN niOlO011O = '1' ELSE n0Ol10il; + wire_n0Ol1l1i_dataout <= wire_n0Ol1l0i_o(4) WHEN niOlO011O = '1' ELSE n0Ol10iO; + wire_n0Ol1l1l_dataout <= wire_n0Ol1l0i_o(5) WHEN niOlO011O = '1' ELSE n0Ol10li; + wire_n0Ol1l1O_dataout <= wire_n0Ol1l0i_o(6) WHEN niOlO011O = '1' ELSE n0Ol10ll; + wire_n0Ol1liO_dataout <= n0Ol011O AND (((NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0Ol1OOO)) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0Ol011i))) AND (NOT (wire_niO01ill_w_lg_n1101l1i11551w(0) XOR n0Ol011l))); + wire_n0Ol1liO_w_lg_w_lg_w_lg_dataout11687w11693w11694w(0) <= wire_n0Ol1liO_w_lg_w_lg_dataout11687w11693w(0) AND n0Ol011O; + wire_n0Ol1liO_w_lg_w_lg_dataout11687w11693w(0) <= wire_n0Ol1liO_w_lg_dataout11687w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n0Ol1OOi11688w11690w11692w(0); + wire_n0Ol1liO_w_lg_dataout11700w(0) <= wire_n0Ol1liO_dataout AND wire_niO01ill_w11699w(0); + wire_n0Ol1liO_w_lg_dataout11687w(0) <= NOT wire_n0Ol1liO_dataout; + wire_n0Ol1lli_dataout <= n0Ol01li AND (n0Ol010i AND niOlO010O); + wire_n0Ol1llO_dataout <= n0Ol01li AND ((NOT (n0Ol010O XOR n0Ol010l)) AND niOlO010O); + wire_n0Ol1lOO_dataout <= n0Ol10lO AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllOlOO); + wire_n0Oli00i_dataout <= wire_n0O1O10O_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli0Oi_dataout; + wire_n0Oli00l_dataout <= n0OO1i1i WHEN niOlO0i1i = '1' ELSE wire_n0Oli0Ol_dataout; + wire_n0Oli00O_dataout <= wire_n0Olii1i_dataout AND NOT(niOlO00Ol); + wire_n0Oli01i_dataout <= wire_n0O1O1Ol_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli0li_dataout; + wire_n0Oli01l_dataout <= wire_n0O1O1ll_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli0ll_dataout; + wire_n0Oli01O_dataout <= wire_n0O1O1iO_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli0lO_dataout; + wire_n0Oli0i_dataout <= wire_n0OO10O_dataout AND NOT(niOO0il0O); + wire_n0Oli0ii_dataout <= wire_n0Olii1l_dataout AND NOT(niOlO00Ol); + wire_n0Oli0il_dataout <= wire_n0Olii1O_dataout OR niOlO00Ol; + wire_n0Oli0iO_dataout <= wire_n0Olii0i_dataout OR niOlO00Ol; + wire_n0Oli0l_dataout <= wire_n0OO1lO_dataout AND NOT(niOO0il0O); + wire_n0Oli0li_dataout <= wire_n0Olii0l_dataout OR niOlO00Ol; + wire_n0Oli0ll_dataout <= wire_n0Olii0O_dataout OR niOlO00Ol; + wire_n0Oli0lO_dataout <= wire_n0Oliiii_dataout AND NOT(niOlO00Ol); + wire_n0Oli0O_dataout <= n0Ol11i AND NOT(niOO0il0O); + wire_n0Oli0Oi_dataout <= wire_n0Oliiil_dataout OR niOlO00Ol; + wire_n0Oli0Ol_dataout <= wire_n0Oli0OO_dataout OR niOlO00Ol; + wire_n0Oli0OO_dataout <= wire_n0Olil1l_dataout AND NOT(niOlO00ll); + wire_n0Oli10O_dataout <= wire_n0Oli1ii_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n0OO10Oi AND n0Ol010O)) OR (n0OO10Oi AND n0Ol1OOi)); + wire_n0Oli1ii_dataout <= n0Ol10lO AND nlOllOlOO; + wire_n0Oli1l_dataout <= n0Oiill AND NOT(niOO0il0O); + wire_n0Oli1lO_dataout <= wire_n0O1O0ii_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli00O_dataout; + wire_n0Oli1O_dataout <= wire_n0OO10l_dataout AND NOT(niOO0il0O); + wire_n0Oli1Oi_dataout <= wire_n0O1O00l_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli0ii_dataout; + wire_n0Oli1Ol_dataout <= wire_n0O1O01O_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli0il_dataout; + wire_n0Oli1OO_dataout <= wire_n0O1O01i_dataout WHEN niOlO0i1i = '1' ELSE wire_n0Oli0iO_dataout; + wire_n0Olii0i_dataout <= wire_n0OliilO_dataout AND NOT(niOlO00ll); + wire_n0Olii0l_dataout <= wire_n0OliiOi_dataout AND NOT(niOlO00ll); + wire_n0Olii0O_dataout <= wire_n0OliiOl_dataout AND NOT(niOlO00ll); + wire_n0Olii1i_dataout <= wire_n0OliiiO_dataout AND NOT(niOlO00ll); + wire_n0Olii1l_dataout <= wire_n0Oliili_dataout AND NOT(niOlO00ll); + wire_n0Olii1O_dataout <= wire_n0Oliill_dataout AND NOT(niOlO00ll); + wire_n0Oliii_dataout <= wire_n0OO1ll_dataout AND NOT(niOO0il0O); + wire_n0Oliiii_dataout <= wire_n0OliiOO_dataout AND NOT(niOlO00ll); + wire_n0Oliiil_dataout <= wire_n0Olil1i_dataout AND NOT(niOlO00ll); + wire_n0OliiiO_dataout <= wire_n0Olil1O_dataout AND NOT(niOlO00iO); + wire_n0Oliil_dataout <= wire_n0OO1il_dataout AND NOT(niOO0il0O); + wire_n0Oliili_dataout <= wire_n0Olil0i_dataout AND NOT(niOlO00iO); + wire_n0Oliill_dataout <= wire_n0Olil0l_dataout OR niOlO00iO; + wire_n0OliilO_dataout <= wire_n0Olil0O_dataout OR niOlO00iO; + wire_n0OliiO_dataout <= wire_n0OO1iO_dataout AND NOT(niOO0il0O); + wire_n0OliiOi_dataout <= wire_n0Olilii_dataout OR niOlO00iO; + wire_n0OliiOl_dataout <= wire_n0Olilil_dataout OR niOlO00iO; + wire_n0OliiOO_dataout <= wire_n0OliliO_dataout OR niOlO00iO; + wire_n0Olil0i_dataout <= wire_n0OlilOi_dataout AND NOT(niOlO00il); + wire_n0Olil0l_dataout <= wire_n0OlilOl_dataout OR niOlO00il; + wire_n0Olil0O_dataout <= wire_n0OlilOO_dataout AND NOT(niOlO00il); + wire_n0Olil1i_dataout <= wire_n0Olilli_dataout AND NOT(niOlO00iO); + wire_n0Olil1l_dataout <= wire_n0Olilll_dataout OR niOlO00iO; + wire_n0Olil1O_dataout <= wire_n0OlillO_dataout OR niOlO00il; + wire_n0Olili_dataout <= wire_n0OO1li_dataout AND NOT(niOO0il0O); + wire_n0Olilii_dataout <= wire_n0OliO1i_dataout OR niOlO00il; + wire_n0Olilil_dataout <= wire_n0OliO1l_dataout OR niOlO00il; + wire_n0OliliO_dataout <= wire_n0OliO1O_dataout AND NOT(niOlO00il); + wire_n0Olill_dataout <= n0Ol10O AND NOT(niOO0il0O); + wire_n0Olilli_dataout <= wire_n0OliO0i_dataout OR niOlO00il; + wire_n0Olilll_dataout <= wire_n0OliO0l_dataout AND NOT(niOlO00il); + wire_n0OlillO_dataout <= wire_n0OliO0O_dataout AND NOT(niOlO00ii); + wire_n0OlilO_dataout <= n0Ol1ii AND NOT(niOO0il0O); + wire_n0OlilOi_dataout <= wire_n0OliOii_dataout OR niOlO00ii; + wire_n0OlilOl_dataout <= wire_n0OliOil_dataout AND NOT(niOlO00ii); + wire_n0OlilOO_dataout <= wire_n0OliOiO_dataout OR niOlO00ii; + wire_n0OliO0i_dataout <= wire_n0OliOOi_dataout AND NOT(niOlO00ii); + wire_n0OliO0l_dataout <= wire_n0OliOOl_dataout AND NOT(niOlO00ii); + wire_n0OliO0O_dataout <= wire_n0Olllil_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0OliOOO_dataout; + wire_n0OliO1i_dataout <= wire_n0OliOli_dataout AND NOT(niOlO00ii); + wire_n0OliO1l_dataout <= wire_n0OliOll_dataout AND NOT(niOlO00ii); + wire_n0OliO1O_dataout <= wire_n0OliOlO_dataout OR niOlO00ii; + wire_n0OliOi_dataout <= n0Ol1il AND NOT(niOO0il0O); + wire_n0OliOii_dataout <= wire_n0OllliO_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll11i_dataout; + wire_n0OliOil_dataout <= wire_n0Olllli_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll11l_dataout; + wire_n0OliOiO_dataout <= wire_n0Olllll_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll11O_dataout; + wire_n0OliOl_dataout <= n0Ol1iO AND NOT(niOO0il0O); + wire_n0OliOli_dataout <= wire_n0OllllO_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll10i_dataout; + wire_n0OliOll_dataout <= wire_n0OlllOi_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll10l_dataout; + wire_n0OliOlO_dataout <= wire_n0OlllOl_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll10O_dataout; + wire_n0OliOO_dataout <= n0Ol1li AND NOT(niOO0il0O); + wire_n0OliOOi_dataout <= wire_n0OlllOO_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll1ii_dataout; + wire_n0OliOOl_dataout <= wire_n0OllO1i_dataout WHEN wire_n0Ol1liO_dataout = '1' ELSE wire_n0Oll1il_dataout; + wire_n0OliOOO_dataout <= wire_n0Oll1iO_dataout AND NOT(niOlO01lO); + wire_n0Oll00i_dataout <= wire_n0Oll0Oi_dataout AND NOT(niOlO01li); + wire_n0Oll00l_dataout <= wire_n0Oll0Ol_dataout AND NOT(niOlO01li); + wire_n0Oll00O_dataout <= wire_n0Oll0OO_dataout AND NOT(niOlO01li); + wire_n0Oll01i_dataout <= wire_n0Oll0li_dataout AND NOT(niOlO01ll); + wire_n0Oll01l_dataout <= wire_n0Oll0ll_dataout OR niOlO01ll; + wire_n0Oll01O_dataout <= wire_n0Oll0lO_dataout AND NOT(niOlO01li); + wire_n0Oll0i_dataout <= n0Ol1Ol AND NOT(niOO0il0O); + wire_n0Oll0ii_dataout <= wire_n0Olli1i_dataout AND NOT(niOlO01li); + wire_n0Oll0il_dataout <= wire_n0Olli1l_dataout AND NOT(niOlO01li); + wire_n0Oll0iO_dataout <= wire_n0Olli1O_dataout AND NOT(niOlO01li); + wire_n0Oll0l_dataout <= n0Ol1OO AND NOT(niOO0il0O); + wire_n0Oll0li_dataout <= wire_n0Olli0i_dataout AND NOT(niOlO01li); + wire_n0Oll0ll_dataout <= wire_n0Olli0l_dataout AND NOT(niOlO01li); + wire_n0Oll0lO_dataout <= n0OiOOiO WHEN niOlO01il = '1' ELSE wire_n0Olli0O_dataout; + wire_n0Oll0O_dataout <= n0Ol01i AND NOT(niOO0il0O); + wire_n0Oll0Oi_dataout <= n0Ol100O WHEN niOlO01il = '1' ELSE wire_n0Olliii_dataout; + wire_n0Oll0Ol_dataout <= n0Ol10ii WHEN niOlO01il = '1' ELSE wire_n0Olliil_dataout; + wire_n0Oll0OO_dataout <= n0Ol10il WHEN niOlO01il = '1' ELSE wire_n0OlliiO_dataout; + wire_n0Oll10i_dataout <= wire_n0Oll1Oi_dataout OR niOlO01lO; + wire_n0Oll10l_dataout <= wire_n0Oll1Ol_dataout OR niOlO01lO; + wire_n0Oll10O_dataout <= wire_n0Oll1OO_dataout AND NOT(niOlO01lO); + wire_n0Oll11i_dataout <= wire_n0Oll1li_dataout AND NOT(niOlO01lO); + wire_n0Oll11l_dataout <= wire_n0Oll1ll_dataout OR niOlO01lO; + wire_n0Oll11O_dataout <= wire_n0Oll1lO_dataout OR niOlO01lO; + wire_n0Oll1i_dataout <= n0Ol1ll AND NOT(niOO0il0O); + wire_n0Oll1ii_dataout <= wire_n0Oll01i_dataout OR niOlO01lO; + wire_n0Oll1il_dataout <= wire_n0Oll01l_dataout OR niOlO01lO; + wire_n0Oll1iO_dataout <= wire_n0Oll01O_dataout AND NOT(niOlO01ll); + wire_n0Oll1l_dataout <= n0Ol1lO AND NOT(niOO0il0O); + wire_n0Oll1li_dataout <= wire_n0Oll00i_dataout AND NOT(niOlO01ll); + wire_n0Oll1ll_dataout <= wire_n0Oll00l_dataout OR niOlO01ll; + wire_n0Oll1lO_dataout <= wire_n0Oll00O_dataout OR niOlO01ll; + wire_n0Oll1O_dataout <= n0Ol1Oi AND NOT(niOO0il0O); + wire_n0Oll1Oi_dataout <= wire_n0Oll0ii_dataout OR niOlO01ll; + wire_n0Oll1Ol_dataout <= wire_n0Oll0il_dataout OR niOlO01ll; + wire_n0Oll1OO_dataout <= wire_n0Oll0iO_dataout OR niOlO01ll; + wire_n0Olli0i_dataout <= n0O0l1Ol WHEN niOlO01il = '1' ELSE wire_n0OlliOi_dataout; + wire_n0Olli0l_dataout <= wire_n0OlliOl_dataout AND NOT(niOlO01il); + wire_n0Olli0O_dataout <= n0Ol1O1l WHEN niOlO01iO = '1' ELSE wire_n0O1O0ii_dataout; + wire_n0Olli1i_dataout <= n0Ol10iO WHEN niOlO01il = '1' ELSE wire_n0Ollili_dataout; + wire_n0Olli1l_dataout <= n0Ol10li WHEN niOlO01il = '1' ELSE wire_n0Ollill_dataout; + wire_n0Olli1O_dataout <= n0Ol10ll WHEN niOlO01il = '1' ELSE wire_n0OllilO_dataout; + wire_n0Ollii_dataout <= n0Ol01l AND NOT(niOO0il0O); + wire_n0Olliii_dataout <= n0Ol1O1O WHEN niOlO01iO = '1' ELSE wire_n0O1O00l_dataout; + wire_n0Olliil_dataout <= n0Ol1O0i WHEN niOlO01iO = '1' ELSE wire_n0O1O01O_dataout; + wire_n0OlliiO_dataout <= n0Ol1O0l WHEN niOlO01iO = '1' ELSE wire_n0O1O01i_dataout; + wire_n0Ollil_dataout <= wire_n0OlOii_dataout AND NOT(niOO0il0O); + wire_n0Ollili_dataout <= n0Ol1O0O WHEN niOlO01iO = '1' ELSE wire_n0O1O1Ol_dataout; + wire_n0Ollill_dataout <= n0Ol1Oii WHEN niOlO01iO = '1' ELSE wire_n0O1O1ll_dataout; + wire_n0OllilO_dataout <= n0Ol1Oil WHEN niOlO01iO = '1' ELSE wire_n0O1O1iO_dataout; + wire_n0OlliO_dataout <= wire_n0OO1ii_dataout AND NOT(niOO0il0O); + wire_n0OlliOi_dataout <= n0Ol1OiO WHEN niOlO01iO = '1' ELSE wire_n0O1O10O_dataout; + wire_n0OlliOl_dataout <= n0OO1i1i AND NOT(niOlO01iO); + wire_n0Ollli_dataout <= wire_n0OlOil_dataout AND NOT(niOO0il0O); + wire_n0Olllil_dataout <= wire_n0OllO1l_dataout AND NOT(niOlO01Oi); + wire_n0OllliO_dataout <= wire_n0OllO1O_dataout AND NOT(niOlO01Oi); + wire_n0Ollll_dataout <= wire_n0OlOiO_dataout AND NOT(niOO0il0O); + wire_n0Olllli_dataout <= wire_n0OllO0i_dataout OR niOlO01Oi; + wire_n0Olllll_dataout <= wire_n0OllO0l_dataout OR niOlO01Oi; + wire_n0OllllO_dataout <= wire_n0OllO0O_dataout OR niOlO01Oi; + wire_n0OlllO_dataout <= wire_n0OlOli_dataout AND NOT(niOO0il0O); + wire_n0OlllOi_dataout <= wire_n0OllOii_dataout OR niOlO01Oi; + wire_n0OlllOl_dataout <= wire_n0OllOil_dataout AND NOT(niOlO01Oi); + wire_n0OlllOO_dataout <= wire_n0OllOiO_dataout OR niOlO01Oi; + wire_n0OllO0i_dataout <= wire_n0OllOOi_dataout OR niOlO01Ol; + wire_n0OllO0l_dataout <= wire_n0OllOOl_dataout OR niOlO01Ol; + wire_n0OllO0O_dataout <= wire_n0OllOOO_dataout OR niOlO01Ol; + wire_n0OllO1i_dataout <= wire_n0OllOli_dataout OR niOlO01Oi; + wire_n0OllO1l_dataout <= wire_n0OllOll_dataout AND NOT(niOlO01Ol); + wire_n0OllO1O_dataout <= wire_n0OllOlO_dataout AND NOT(niOlO01Ol); + wire_n0OllOi_dataout <= wire_n0OlOll_dataout AND NOT(niOO0il0O); + wire_n0OllOii_dataout <= wire_n0OlO11i_dataout OR niOlO01Ol; + wire_n0OllOil_dataout <= wire_n0OlO11l_dataout AND NOT(niOlO01Ol); + wire_n0OllOiO_dataout <= wire_n0OlO11O_dataout OR niOlO01Ol; + wire_n0OllOl_dataout <= wire_n0OlOlO_dataout AND NOT(niOO0il0O); + wire_n0OllOli_dataout <= wire_n0OlO10i_dataout OR niOlO01Ol; + wire_n0OllOll_dataout <= wire_n0OlO10l_dataout OR niOlO01OO; + wire_n0OllOlO_dataout <= wire_n0OlO10O_dataout AND NOT(niOlO01OO); + wire_n0OllOO_dataout <= wire_n0OlOOi_dataout AND NOT(niOO0il0O); + wire_n0OllOOi_dataout <= wire_n0OlO1ii_dataout OR niOlO01OO; + wire_n0OllOOl_dataout <= wire_n0OlO1il_dataout AND NOT(niOlO01OO); + wire_n0OllOOO_dataout <= wire_n0OlO1iO_dataout OR niOlO01OO; + wire_n0OlO00i_dataout <= wire_n0OlO0Oi_dataout AND NOT(niOlO001l); + wire_n0OlO00l_dataout <= wire_n0OlO0Ol_dataout OR niOlO001l; + wire_n0OlO00O_dataout <= wire_n0OlO0OO_dataout AND NOT(niOlO001l); + wire_n0OlO01i_dataout <= wire_n0OlO0li_dataout AND NOT(niOlO001l); + wire_n0OlO01l_dataout <= wire_n0OlO0ll_dataout OR niOlO001l; + wire_n0OlO01O_dataout <= wire_n0OlO0lO_dataout AND NOT(niOlO001l); + wire_n0OlO0i_dataout <= wire_n0OO11l_dataout AND NOT(niOO0il0O); + wire_n0OlO0ii_dataout <= wire_n0OlOi1i_dataout AND NOT(niOlO001l); + wire_n0OlO0il_dataout <= n0OiOOiO WHEN niOlO001O = '1' ELSE wire_n0OlOi1l_dataout; + wire_n0OlO0iO_dataout <= n0Ol100O WHEN niOlO001O = '1' ELSE wire_n0OlOi1O_dataout; + wire_n0OlO0l_dataout <= wire_n0OO11O_dataout AND NOT(niOO0il0O); + wire_n0OlO0li_dataout <= n0Ol10ii WHEN niOlO001O = '1' ELSE wire_n0OlOi0i_dataout; + wire_n0OlO0ll_dataout <= n0Ol10il WHEN niOlO001O = '1' ELSE wire_n0OlOi0l_dataout; + wire_n0OlO0lO_dataout <= n0Ol10iO WHEN niOlO001O = '1' ELSE wire_n0OlOi0O_dataout; + wire_n0OlO0O_dataout <= wire_n0OO10i_dataout OR niOO0il0O; + wire_n0OlO0Oi_dataout <= n0Ol10li WHEN niOlO001O = '1' ELSE wire_n0OlOiii_dataout; + wire_n0OlO0Ol_dataout <= n0Ol10ll WHEN niOlO001O = '1' ELSE wire_n0OlOiil_dataout; + wire_n0OlO0OO_dataout <= n0O0l1Ol WHEN niOlO001O = '1' ELSE wire_n0OlOiiO_dataout; + wire_n0OlO10i_dataout <= wire_n0OlO1Oi_dataout AND NOT(niOlO01OO); + wire_n0OlO10l_dataout <= wire_n0OlO1Ol_dataout AND NOT(niOlO001i); + wire_n0OlO10O_dataout <= wire_n0OlO1OO_dataout AND NOT(niOlO001i); + wire_n0OlO11i_dataout <= wire_n0OlO1li_dataout OR niOlO01OO; + wire_n0OlO11l_dataout <= wire_n0OlO1ll_dataout AND NOT(niOlO01OO); + wire_n0OlO11O_dataout <= wire_n0OlO1lO_dataout OR niOlO01OO; + wire_n0OlO1i_dataout <= wire_n0OlOOl_dataout AND NOT(niOO0il0O); + wire_n0OlO1ii_dataout <= wire_n0OlO01i_dataout OR niOlO001i; + wire_n0OlO1il_dataout <= wire_n0OlO01l_dataout OR niOlO001i; + wire_n0OlO1iO_dataout <= wire_n0OlO01O_dataout OR niOlO001i; + wire_n0OlO1l_dataout <= wire_n0OlOOO_dataout AND NOT(niOO0il0O); + wire_n0OlO1li_dataout <= wire_n0OlO00i_dataout OR niOlO001i; + wire_n0OlO1ll_dataout <= wire_n0OlO00l_dataout AND NOT(niOlO001i); + wire_n0OlO1lO_dataout <= wire_n0OlO00O_dataout OR niOlO001i; + wire_n0OlO1O_dataout <= wire_n0OO11i_dataout AND NOT(niOO0il0O); + wire_n0OlO1Oi_dataout <= wire_n0OlO0ii_dataout OR niOlO001i; + wire_n0OlO1Ol_dataout <= wire_n0OlO0il_dataout AND NOT(niOlO001l); + wire_n0OlO1OO_dataout <= wire_n0OlO0iO_dataout OR niOlO001l; + wire_n0OlOi0i_dataout <= n0Ol1O0i WHEN niOlO000i = '1' ELSE wire_n0OlOiOi_dataout; + wire_n0OlOi0l_dataout <= n0Ol1O0l WHEN niOlO000i = '1' ELSE wire_n0OlOiOl_dataout; + wire_n0OlOi0O_dataout <= n0Ol1O0O WHEN niOlO000i = '1' ELSE wire_n0OlOiOO_dataout; + wire_n0OlOi1i_dataout <= wire_n0OlOili_dataout AND NOT(niOlO001O); + wire_n0OlOi1l_dataout <= n0Ol1O1l WHEN niOlO000i = '1' ELSE wire_n0OlOill_dataout; + wire_n0OlOi1O_dataout <= n0Ol1O1O WHEN niOlO000i = '1' ELSE wire_n0OlOilO_dataout; + wire_n0OlOii_dataout <= wire_n0OO01i_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol01O; + wire_n0OlOiii_dataout <= n0Ol1Oii WHEN niOlO000i = '1' ELSE wire_n0OlOl1i_dataout; + wire_n0OlOiil_dataout <= n0Ol1Oil WHEN niOlO000i = '1' ELSE wire_n0OlOl1l_dataout; + wire_n0OlOiiO_dataout <= n0Ol1OiO WHEN niOlO000i = '1' ELSE wire_n0OlOl1O_dataout; + wire_n0OlOil_dataout <= wire_n0OO01l_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol00l; + wire_n0OlOili_dataout <= wire_n0OlOl0i_dataout AND NOT(niOlO000i); + wire_n0OlOill_dataout <= wire_n0OlOl0l_dataout AND NOT(niOlO000l); + wire_n0OlOilO_dataout <= wire_n0OlOl0O_dataout AND NOT(niOlO000l); + wire_n0OlOiO_dataout <= wire_n0OO01O_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol00O; + wire_n0OlOiOi_dataout <= wire_n0OlOlii_dataout OR niOlO000l; + wire_n0OlOiOl_dataout <= wire_n0OlOlil_dataout OR niOlO000l; + wire_n0OlOiOO_dataout <= wire_n0OlOliO_dataout OR niOlO000l; + wire_n0OlOl0i_dataout <= wire_n0OlOlOi_dataout OR niOlO000l; + wire_n0OlOl0l_dataout <= n0Ol1O1l AND NOT(niOlO000O); + wire_n0OlOl0O_dataout <= n0Ol1O1O AND NOT(niOlO000O); + wire_n0OlOl1i_dataout <= wire_n0OlOlli_dataout OR niOlO000l; + wire_n0OlOl1l_dataout <= wire_n0OlOlll_dataout AND NOT(niOlO000l); + wire_n0OlOl1O_dataout <= wire_n0OlOllO_dataout OR niOlO000l; + wire_n0OlOli_dataout <= wire_n0OO00i_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0ii; + wire_n0OlOlii_dataout <= n0Ol1O0i OR niOlO000O; + wire_n0OlOlil_dataout <= n0Ol1O0l OR niOlO000O; + wire_n0OlOliO_dataout <= n0Ol1O0O OR niOlO000O; + wire_n0OlOll_dataout <= wire_n0OO00l_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0il; + wire_n0OlOlli_dataout <= n0Ol1Oii OR niOlO000O; + wire_n0OlOlll_dataout <= n0Ol1Oil OR niOlO000O; + wire_n0OlOllO_dataout <= n0Ol1OiO OR niOlO000O; + wire_n0OlOlO_dataout <= wire_n0OO00O_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0iO; + wire_n0OlOlOi_dataout <= n0Ol1Oli OR niOlO000O; + wire_n0OlOOi_dataout <= wire_n0OO0ii_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0li; + wire_n0OlOOl_dataout <= wire_n0OO0il_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0ll; + wire_n0OlOOll_dataout <= wire_n0OO111l_dataout AND NOT(niOlO0i1O); + wire_n0OlOOlO_dataout <= wire_n0OO111O_dataout AND NOT(niOlO0i1O); + wire_n0OlOOO_dataout <= wire_n0OO0iO_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0lO; + wire_n0OlOOOi_dataout <= wire_n0OO110i_dataout AND NOT(niOlO0i1O); + wire_n0OlOOOl_dataout <= wire_n0OO110l_dataout AND NOT(niOlO0i1O); + wire_n0OlOOOO_dataout <= wire_n0OO110O_dataout AND NOT(niOlO0i1O); + wire_n0OO000O_dataout <= k_cnt(57) AND NOT(wire_n0OO00lO_o); + wire_n0OO001i_dataout <= n1l001lO AND NOT(niOlO0iil); + wire_n0OO001l_dataout <= n1l001Oi AND NOT(niOlO0iil); + wire_n0OO001O_dataout <= n1l001Ol AND NOT(niOlO0iil); + wire_n0OO00i_dataout <= n0Ol0ii AND NOT(n0Ol0OO); + wire_n0OO00ii_dataout <= k_cnt(58) AND NOT(wire_n0OO00lO_o); + wire_n0OO00il_dataout <= k_cnt(59) OR wire_n0OO00lO_o; + wire_n0OO00iO_dataout <= k_cnt(60) AND NOT(wire_n0OO00lO_o); + wire_n0OO00l_dataout <= n0Ol0il AND NOT(n0Ol0OO); + wire_n0OO00li_dataout <= k_cnt(61) AND NOT(wire_n0OO00lO_o); + wire_n0OO00ll_dataout <= k_cnt(62) AND NOT(wire_n0OO00lO_o); + wire_n0OO00O_dataout <= n0Ol0iO AND NOT(n0Ol0OO); + wire_n0OO010i_dataout <= wire_nlOO10OOl_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO01lO_dataout; + wire_n0OO010l_dataout <= wire_nlOO10OOO_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO01Oi_dataout; + wire_n0OO010O_dataout <= wire_nlOO1i11i_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO01Ol_dataout; + wire_n0OO011i_dataout <= wire_n1llO00O_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO01iO_dataout; + wire_n0OO011l_dataout <= wire_n1llO0ii_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO01li_dataout; + wire_n0OO011O_dataout <= wire_nlOO10OOi_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO01ll_dataout; + wire_n0OO01i_dataout <= n0Ol01O AND NOT(n0Ol0OO); + wire_n0OO01ii_dataout <= wire_nlOO1i11l_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO01OO_dataout; + wire_n0OO01il_dataout <= wire_nlOO1i11O_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO001i_dataout; + wire_n0OO01iO_dataout <= wire_nlOO1i10i_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO001l_dataout; + wire_n0OO01l_dataout <= n0Ol00l AND NOT(n0Ol0OO); + wire_n0OO01li_dataout <= wire_nlOO1i10l_dataout WHEN niOlO0iiO = '1' ELSE wire_n0OO001O_dataout; + wire_n0OO01ll_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOlO0iil = '1' ELSE n1l001ii; + wire_n0OO01lO_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOlO0iil = '1' ELSE n1l001il; + wire_n0OO01O_dataout <= n0Ol00O AND NOT(n0Ol0OO); + wire_n0OO01Oi_dataout <= wire_niO01ill_w_lg_n1101l1i11551w(0) WHEN niOlO0iil = '1' ELSE n1l001iO; + wire_n0OO01Ol_dataout <= n1l001li AND NOT(niOlO0iil); + wire_n0OO01OO_dataout <= n1l001ll AND NOT(niOlO0iil); + wire_n0OO0ii_dataout <= n0Ol0li AND NOT(n0Ol0OO); + wire_n0OO0il_dataout <= n0Ol0ll AND NOT(n0Ol0OO); + wire_n0OO0iO_dataout <= n0Ol0lO AND NOT(n0Ol0OO); + wire_n0OO0l0i_dataout <= wire_n0OO0lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0l0l_dataout <= wire_n0OO0lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0l0O_dataout <= wire_n0OO0lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0l1i_dataout <= wire_n0OO0lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0l1l_dataout <= wire_n0OO0lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0l1O_dataout <= wire_n0OO0llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0lii_dataout <= wire_n0OO0O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0lil_dataout <= wire_n0OO0O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0liO_dataout <= wire_n0OO0O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO0lli_dataout <= wire_niii1ili_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0O0i_dataout; + wire_n0OO0lll_dataout <= wire_niii1ill_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0O0l_dataout; + wire_n0OO0llO_dataout <= wire_niii1ilO_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0O0O_dataout; + wire_n0OO0lOi_dataout <= wire_niii1iOi_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0Oii_dataout; + wire_n0OO0lOl_dataout <= wire_niii1iOl_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0Oil_dataout; + wire_n0OO0lOO_dataout <= wire_niii1iOO_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0OiO_dataout; + wire_n0OO0O0i_dataout <= n0OO0OOi AND NOT(niOlOl0Ol); + wire_n0OO0O0l_dataout <= n0OO0iii AND NOT(niOlOl0Ol); + wire_n0OO0O0O_dataout <= n0OO0iil AND NOT(niOlOl0Ol); + wire_n0OO0O1i_dataout <= wire_niii1l1i_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0Oli_dataout; + wire_n0OO0O1l_dataout <= wire_niii1l1l_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0Oll_dataout; + wire_n0OO0O1O_dataout <= wire_niii1l1O_dataout WHEN niOlO0lii = '1' ELSE wire_n0OO0OlO_dataout; + wire_n0OO0Oii_dataout <= n0OO0iiO AND NOT(niOlOl0Ol); + wire_n0OO0Oil_dataout <= n0OO0ili AND NOT(niOlOl0Ol); + wire_n0OO0OiO_dataout <= n0OO0ill AND NOT(niOlOl0Ol); + wire_n0OO0Oli_dataout <= n0OO0ilO AND NOT(niOlOl0Ol); + wire_n0OO0Oll_dataout <= n0OO0iOi AND NOT(niOlOl0Ol); + wire_n0OO0OlO_dataout <= n0OO0iOl AND NOT(niOlOl0Ol); + wire_n0OO100i_dataout <= wire_n0OO100l_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11552w(0) AND wire_w_lg_niOlO0i0O11553w(0)); + wire_n0OO100l_dataout <= n0Ol01li AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlO0iii11562w(0))); + wire_n0OO10i_dataout <= wire_n0OO0Oi_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Oli1i; + wire_n0OO10l_dataout <= wire_n0OO0Ol_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0OiOOi; + wire_n0OO10O_dataout <= wire_n0OO0OO_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0OiOOl; + wire_n0OO110i_dataout <= wire_n0OO11li_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol010O; + wire_n0OO110l_dataout <= wire_n0OO11ll_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol01ii; + wire_n0OO110O_dataout <= wire_n0OO11lO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol01il; + wire_n0OO111i_dataout <= wire_n0OO11ii_dataout AND NOT(niOlO0i1O); + wire_n0OO111l_dataout <= wire_n0OO11il_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol010i; + wire_n0OO111O_dataout <= wire_n0OO11iO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol010l; + wire_n0OO11i_dataout <= wire_n0OO0li_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0Oi; + wire_n0OO11ii_dataout <= wire_n0OO11Oi_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n0Ol01iO; + wire_n0OO11il_dataout <= wire_n0OO11Ol_o(0) WHEN niOlO0i1l = '1' ELSE n0Ol010i; + wire_n0OO11iO_dataout <= wire_n0OO11Ol_o(1) WHEN niOlO0i1l = '1' ELSE n0Ol010l; + wire_n0OO11l_dataout <= wire_n0OO0ll_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0Ol; + wire_n0OO11li_dataout <= wire_n0OO11Ol_o(2) WHEN niOlO0i1l = '1' ELSE n0Ol010O; + wire_n0OO11ll_dataout <= wire_n0OO11Ol_o(3) WHEN niOlO0i1l = '1' ELSE n0Ol01ii; + wire_n0OO11lO_dataout <= wire_n0OO11Ol_o(4) WHEN niOlO0i1l = '1' ELSE n0Ol01il; + wire_n0OO11O_dataout <= wire_n0OO0lO_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol0OO; + wire_n0OO11Oi_dataout <= wire_n0OO11Ol_o(5) WHEN niOlO0i1l = '1' ELSE n0Ol01iO; + wire_n0OO1ii_dataout <= wire_n0OOi1i_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol00i; + wire_n0OO1il_dataout <= wire_n0OO1Oi_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol11O; + wire_n0OO1ili_dataout <= wire_n0OO1O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1ill_dataout <= wire_n0OO1O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1ilO_dataout <= wire_n0OO1O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1iO_dataout <= wire_n0OO1Ol_o WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol10i; + wire_n0OO1iOi_dataout <= wire_n0OO1O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1iOl_dataout <= n0OO10Oi AND NOT(wire_niO01lOO_dataout); + wire_n0OO1iOO_dataout <= nlOllOlOO AND NOT(wire_niO01lOO_dataout); + wire_n0OO1l0i_dataout <= wire_n0OO1Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1l0l_dataout <= wire_n0OO1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1l0O_dataout <= wire_n0OO1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1l1i_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11557w(0) AND wire_w_lg_niOlO0i0i11558w(0)) AND wire_niO01ill_w_lg_n0OO10ll11555w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0OO1l1l_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w11552w(0) AND wire_w_lg_niOlO0i0O11553w(0)) AND wire_niO01ill_w_lg_n0OO10ll11555w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n0OO1l1O_dataout <= wire_n0OO1Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1li_dataout <= n0Ol10l AND NOT(wire_w_lg_niOO0il0l3327w(0)); + wire_n0OO1lii_dataout <= wire_n0OO1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1lil_dataout <= wire_n0OO1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1liO_dataout <= wire_n0OO1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1ll_dataout <= wire_n0OOlOl_dataout WHEN wire_w_lg_niOO0il0l3327w(0) = '1' ELSE n0Ol11l; + wire_n0OO1lli_dataout <= wire_n0OO011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1lll_dataout <= wire_n0OO011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OO1lO_dataout <= n0OiOOO AND NOT(wire_w_lg_niOO0il0l3327w(0)); + wire_n0OO1O0i_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0Ol0Oil; + wire_n0OO1O0l_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0OO10iO; + wire_n0OO1O0O_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0OO10li; + wire_n0OO1O1O_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n0OO10ll; + wire_n0OO1Oii_dataout <= wire_n1lllO0l_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO1Oil_dataout; + wire_n0OO1Oil_dataout <= wire_n0OO1OiO_dataout AND NOT(niOlO0iiO); + wire_n0OO1OiO_dataout <= n1l001OO AND NOT(niOlO0iil); + wire_n0OO1Oli_dataout <= wire_n1llO1OO_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO011O_dataout; + wire_n0OO1Oll_dataout <= wire_n1llO01i_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO010i_dataout; + wire_n0OO1OlO_dataout <= wire_n1llO01l_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO010l_dataout; + wire_n0OO1OOi_dataout <= wire_n1llO01O_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO010O_dataout; + wire_n0OO1OOl_dataout <= wire_n1llO00i_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO01ii_dataout; + wire_n0OO1OOO_dataout <= wire_n1llO00l_dataout WHEN n1lO0lOi = '1' ELSE wire_n0OO01il_dataout; + wire_n0OOi00i_dataout <= wire_niii1ilO_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOi0Oi_dataout; + wire_n0OOi00l_dataout <= wire_niii1iOi_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOi0Ol_dataout; + wire_n0OOi00O_dataout <= wire_niii1iOl_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOi0OO_dataout; + wire_n0OOi01i_dataout <= wire_n0OOi0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi01l_dataout <= wire_niii1ili_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOi0ll_dataout; + wire_n0OOi01O_dataout <= wire_niii1ill_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOi0lO_dataout; + wire_n0OOi0i_dataout <= n0Ol0OO AND NOT(wire_ni1lOlO_w_lg_n1O1lli3233w(0)); + wire_n0OOi0ii_dataout <= wire_niii1iOO_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOii1i_dataout; + wire_n0OOi0il_dataout <= wire_niii1l1i_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOii1l_dataout; + wire_n0OOi0iO_dataout <= wire_niii1l1l_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOii1O_dataout; + wire_n0OOi0l_dataout <= n0Oli1i AND NOT(wire_ni1lOlO_w_lg_n1O1lli3233w(0)); + wire_n0OOi0li_dataout <= wire_niii1l1O_dataout WHEN niOlO0ili = '1' ELSE wire_n0OOii0i_dataout; + wire_n0OOi0ll_dataout <= n0OO0OOi WHEN niOlOl0Ol = '1' ELSE n0OO0iOO; + wire_n0OOi0lO_dataout <= n0OO0iii WHEN niOlOl0Ol = '1' ELSE n0OO0OOl; + wire_n0OOi0O_dataout <= n1O1lli WHEN niOO0iiOO = '1' ELSE n0OiOOi; + wire_n0OOi0Oi_dataout <= n0OO0iil WHEN niOlOl0Ol = '1' ELSE n0OO0OOO; + wire_n0OOi0Ol_dataout <= n0OO0iiO WHEN niOlOl0Ol = '1' ELSE n0OOi11i; + wire_n0OOi0OO_dataout <= n0OO0ili WHEN niOlOl0Ol = '1' ELSE n0OOi11l; + wire_n0OOi1i_dataout <= n0Ol00i AND NOT(n0Oli1i); + wire_n0OOi1il_dataout <= wire_n0OOi01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi1iO_dataout <= wire_n0OOi01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi1l_dataout <= n0Ol0Oi AND NOT(wire_ni1lOlO_w_lg_n1O1lli3233w(0)); + wire_n0OOi1li_dataout <= wire_n0OOi00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi1ll_dataout <= wire_n0OOi00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi1lO_dataout <= wire_n0OOi00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi1O_dataout <= n0Ol0Ol OR wire_ni1lOlO_w_lg_n1O1lli3233w(0); + wire_n0OOi1Oi_dataout <= wire_n0OOi0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi1Ol_dataout <= wire_n0OOi0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOi1OO_dataout <= wire_n0OOi0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOii0i_dataout <= n0OO0iOl WHEN niOlOl0Ol = '1' ELSE n0OOi10O; + wire_n0OOii1i_dataout <= n0OO0ill WHEN niOlOl0Ol = '1' ELSE n0OOi11O; + wire_n0OOii1l_dataout <= n0OO0ilO WHEN niOlOl0Ol = '1' ELSE n0OOi10i; + wire_n0OOii1O_dataout <= n0OO0iOi WHEN niOlOl0Ol = '1' ELSE n0OOi10l; + wire_n0OOiii_dataout <= n0Ol0Oi AND NOT(niOO0iiOO); + wire_n0OOiil_dataout <= n0Ol0Ol AND NOT(niOO0iiOO); + wire_n0OOiiO_dataout <= n0Ol0OO AND NOT(niOO0iiOO); + wire_n0OOil0i_dataout <= wire_n0OOilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOil0l_dataout <= wire_n0OOilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOil0O_dataout <= wire_n0OOilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOil1O_dataout <= wire_n0OOillO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOili_dataout <= n0Oli1i OR niOO0iiOO; + wire_n0OOilii_dataout <= wire_n0OOiO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOilil_dataout <= wire_n0OOiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOiliO_dataout <= wire_n0OOiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOilli_dataout <= wire_n0OOiO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOilll_dataout <= wire_n0OOiO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOillO_dataout <= wire_niii1ili_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiO0O_dataout; + wire_n0OOilOi_dataout <= wire_niii1ill_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOii_dataout; + wire_n0OOilOl_dataout <= wire_niii1ilO_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOil_dataout; + wire_n0OOilOO_dataout <= wire_niii1iOi_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOiO_dataout; + wire_n0OOiO0i_dataout <= wire_niii1l1l_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOOi_dataout; + wire_n0OOiO0l_dataout <= wire_niii1l1O_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOOl_dataout; + wire_n0OOiO0O_dataout <= n0OO0iOO WHEN niOlOl0Ol = '1' ELSE n0OOi1ii; + wire_n0OOiO1i_dataout <= wire_niii1iOl_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOli_dataout; + wire_n0OOiO1l_dataout <= wire_niii1iOO_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOll_dataout; + wire_n0OOiO1O_dataout <= wire_niii1l1i_dataout WHEN niOlO0ill = '1' ELSE wire_n0OOiOlO_dataout; + wire_n0OOiOii_dataout <= n0OO0OOl WHEN niOlOl0Ol = '1' ELSE n0OOiiiO; + wire_n0OOiOil_dataout <= n0OO0OOO WHEN niOlOl0Ol = '1' ELSE n0OOiili; + wire_n0OOiOiO_dataout <= n0OOi11i WHEN niOlOl0Ol = '1' ELSE n0OOiill; + wire_n0OOiOli_dataout <= n0OOi11l WHEN niOlOl0Ol = '1' ELSE n0OOiilO; + wire_n0OOiOll_dataout <= n0OOi11O WHEN niOlOl0Ol = '1' ELSE n0OOiiOi; + wire_n0OOiOlO_dataout <= n0OOi10i WHEN niOlOl0Ol = '1' ELSE n0OOiiOl; + wire_n0OOiOOi_dataout <= n0OOi10l WHEN niOlOl0Ol = '1' ELSE n0OOiiOO; + wire_n0OOiOOl_dataout <= n0OOi10O WHEN niOlOl0Ol = '1' ELSE n0OOil1i; + wire_n0OOl00i_dataout <= wire_n0OOl0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl00l_dataout <= wire_n0OOl0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl00O_dataout <= wire_n0OOl0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl01i_dataout <= wire_n0OOl0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl01l_dataout <= wire_n0OOl0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl01O_dataout <= wire_n0OOl0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl0ii_dataout <= wire_niii1ili_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOli1i_dataout; + wire_n0OOl0il_dataout <= wire_niii1ill_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOli1l_dataout; + wire_n0OOl0iO_dataout <= wire_niii1ilO_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOli1O_dataout; + wire_n0OOl0li_dataout <= wire_niii1iOi_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOli0i_dataout; + wire_n0OOl0ll_dataout <= wire_niii1iOl_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOli0l_dataout; + wire_n0OOl0lO_dataout <= wire_niii1iOO_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOli0O_dataout; + wire_n0OOl0Oi_dataout <= wire_niii1l1i_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOliii_dataout; + wire_n0OOl0Ol_dataout <= wire_niii1l1l_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOliil_dataout; + wire_n0OOl0OO_dataout <= wire_niii1l1O_dataout WHEN niOlO0iOi = '1' ELSE wire_n0OOliiO_dataout; + wire_n0OOl1Oi_dataout <= wire_n0OOl0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl1Ol_dataout <= wire_n0OOl0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOl1OO_dataout <= wire_n0OOl0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOli0i_dataout <= n0OOiill WHEN niOlOl0Ol = '1' ELSE n0OOl10O; + wire_n0OOli0l_dataout <= n0OOiilO WHEN niOlOl0Ol = '1' ELSE n0OOl1ii; + wire_n0OOli0O_dataout <= n0OOiiOi WHEN niOlOl0Ol = '1' ELSE n0OOl1il; + wire_n0OOli1i_dataout <= n0OOi1ii WHEN niOlOl0Ol = '1' ELSE n0OOil1l; + wire_n0OOli1l_dataout <= n0OOiiiO WHEN niOlOl0Ol = '1' ELSE n0OOl10i; + wire_n0OOli1O_dataout <= n0OOiili WHEN niOlOl0Ol = '1' ELSE n0OOl10l; + wire_n0OOlii_dataout <= k_hip(0) AND NOT(niOO0il1O); + wire_n0OOliii_dataout <= n0OOiiOl WHEN niOlOl0Ol = '1' ELSE n0OOl1iO; + wire_n0OOliil_dataout <= n0OOiiOO WHEN niOlOl0Ol = '1' ELSE n0OOl1li; + wire_n0OOliiO_dataout <= n0OOil1i WHEN niOlOl0Ol = '1' ELSE n0OOl1ll; + wire_n0OOlil_dataout <= wire_w_lg_w_k_hip_range2413w2429w(0) AND NOT(niOO0il1O); + wire_n0OOliO_dataout <= n0OiOOi WHEN niOO0il1O = '1' ELSE n1O1lli; + wire_n0OOllil_dataout <= wire_n0OOlO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOlliO_dataout <= wire_n0OOlO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOlll_dataout <= n0OiOOi AND n0OiOOl; + wire_n0OOllli_dataout <= wire_n0OOlO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOllll_dataout <= wire_n0OOlO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOlllO_dataout <= wire_n0OOlO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOllO_dataout <= wire_n0OOlOi_dataout AND NOT(n0OiOOl); + wire_n0OOllOi_dataout <= wire_n0OOlOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOllOl_dataout <= wire_n0OOlOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOllOO_dataout <= wire_n0OOlOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOlO0i_dataout <= wire_niii1ilO_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOlOOi_dataout; + wire_n0OOlO0l_dataout <= wire_niii1iOi_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOlOOl_dataout; + wire_n0OOlO0O_dataout <= wire_niii1iOl_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOlOOO_dataout; + wire_n0OOlO1i_dataout <= wire_n0OOlOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOlO1l_dataout <= wire_niii1ili_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOlOll_dataout; + wire_n0OOlO1O_dataout <= wire_niii1ill_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOlOlO_dataout; + wire_n0OOlOi_dataout <= n0OiOOi WHEN n1O1lli = '1' ELSE n0OiOOl; + wire_n0OOlOii_dataout <= wire_niii1iOO_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOO11i_dataout; + wire_n0OOlOil_dataout <= wire_niii1l1i_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOO11l_dataout; + wire_n0OOlOiO_dataout <= wire_niii1l1l_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOO11O_dataout; + wire_n0OOlOl_dataout <= niOO0il0i AND NOT(n0Oli1i); + wire_n0OOlOli_dataout <= wire_niii1l1O_dataout WHEN niOlO0iOO = '1' ELSE wire_n0OOO10i_dataout; + wire_n0OOlOll_dataout <= n0OOil1l WHEN niOlOl0Ol = '1' ELSE n0OOl1lO; + wire_n0OOlOlO_dataout <= n0OOl10i WHEN niOlOl0Ol = '1' ELSE n0OOliOl; + wire_n0OOlOOi_dataout <= n0OOl10l WHEN niOlOl0Ol = '1' ELSE n0OOliOO; + wire_n0OOlOOl_dataout <= n0OOl10O WHEN niOlOl0Ol = '1' ELSE n0OOll1i; + wire_n0OOlOOO_dataout <= n0OOl1ii WHEN niOlOl0Ol = '1' ELSE n0OOll1l; + wire_n0OOO00i_dataout <= wire_n0OOO0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO00l_dataout <= wire_n0OOO0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO00O_dataout <= wire_n0OOO0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO01O_dataout <= wire_n0OOO0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO0i_dataout <= k_hip(10) AND NOT(niOO0ilii); + wire_n0OOO0ii_dataout <= wire_n0OOOi1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO0il_dataout <= wire_n0OOOi1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO0iO_dataout <= wire_n0OOOi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO0l_dataout <= k_hip(11) OR niOO0ilii; + wire_n0OOO0li_dataout <= wire_n0OOOi0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO0ll_dataout <= wire_n0OOOi0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOO0lO_dataout <= wire_niii1ili_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOi0O_dataout; + wire_n0OOO0Oi_dataout <= wire_niii1ill_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOiii_dataout; + wire_n0OOO0Ol_dataout <= wire_niii1ilO_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOiil_dataout; + wire_n0OOO0OO_dataout <= wire_niii1iOi_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOiiO_dataout; + wire_n0OOO10i_dataout <= n0OOl1ll WHEN niOlOl0Ol = '1' ELSE n0OOll0O; + wire_n0OOO11i_dataout <= n0OOl1il WHEN niOlOl0Ol = '1' ELSE n0OOll1O; + wire_n0OOO11l_dataout <= n0OOl1iO WHEN niOlOl0Ol = '1' ELSE n0OOll0i; + wire_n0OOO11O_dataout <= n0OOl1li WHEN niOlOl0Ol = '1' ELSE n0OOll0l; + wire_n0OOO1l_dataout <= k_hip(8) OR niOO0ilii; + wire_n0OOO1O_dataout <= k_hip(9) AND NOT(niOO0ilii); + wire_n0OOOi0i_dataout <= wire_niii1l1l_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOiOi_dataout; + wire_n0OOOi0l_dataout <= wire_niii1l1O_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOiOl_dataout; + wire_n0OOOi0O_dataout <= n0OOl1lO WHEN niOlOl0Ol = '1' ELSE n0OOllii; + wire_n0OOOi1i_dataout <= wire_niii1iOl_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOili_dataout; + wire_n0OOOi1l_dataout <= wire_niii1iOO_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOill_dataout; + wire_n0OOOi1O_dataout <= wire_niii1l1i_dataout WHEN niOlO0l1l = '1' ELSE wire_n0OOOilO_dataout; + wire_n0OOOiii_dataout <= n0OOliOl WHEN niOlOl0Ol = '1' ELSE n0OOO1iO; + wire_n0OOOiil_dataout <= n0OOliOO WHEN niOlOl0Ol = '1' ELSE n0OOO1li; + wire_n0OOOiiO_dataout <= n0OOll1i WHEN niOlOl0Ol = '1' ELSE n0OOO1ll; + wire_n0OOOili_dataout <= n0OOll1l WHEN niOlOl0Ol = '1' ELSE n0OOO1lO; + wire_n0OOOill_dataout <= n0OOll1O WHEN niOlOl0Ol = '1' ELSE n0OOO1Oi; + wire_n0OOOilO_dataout <= n0OOll0i WHEN niOlOl0Ol = '1' ELSE n0OOO1Ol; + wire_n0OOOiOi_dataout <= n0OOll0l WHEN niOlOl0Ol = '1' ELSE n0OOO1OO; + wire_n0OOOiOl_dataout <= n0OOll0O WHEN niOlOl0Ol = '1' ELSE n0OOO01i; + wire_n0OOOlOi_dataout <= wire_n0OOOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOlOl_dataout <= wire_n0OOOOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOlOO_dataout <= wire_n0OOOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOO0i_dataout <= wire_n0OOOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOO0l_dataout <= wire_n0OOOOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOO0O_dataout <= wire_n0OOOOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOO1i_dataout <= wire_n0OOOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOO1l_dataout <= wire_n0OOOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOO1O_dataout <= wire_n0OOOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n0OOOOii_dataout <= wire_niii1ili_dataout WHEN niOlO0l0i = '1' ELSE wire_ni11111i_dataout; + wire_n0OOOOil_dataout <= wire_niii1ill_dataout WHEN niOlO0l0i = '1' ELSE wire_ni11111l_dataout; + wire_n0OOOOiO_dataout <= wire_niii1ilO_dataout WHEN niOlO0l0i = '1' ELSE wire_ni11111O_dataout; + wire_n0OOOOli_dataout <= wire_niii1iOi_dataout WHEN niOlO0l0i = '1' ELSE wire_ni11110i_dataout; + wire_n0OOOOll_dataout <= wire_niii1iOl_dataout WHEN niOlO0l0i = '1' ELSE wire_ni11110l_dataout; + wire_n0OOOOlO_dataout <= wire_niii1iOO_dataout WHEN niOlO0l0i = '1' ELSE wire_ni11110O_dataout; + wire_n0OOOOOi_dataout <= wire_niii1l1i_dataout WHEN niOlO0l0i = '1' ELSE wire_ni1111ii_dataout; + wire_n0OOOOOl_dataout <= wire_niii1l1l_dataout WHEN niOlO0l0i = '1' ELSE wire_ni1111il_dataout; + wire_n0OOOOOO_dataout <= wire_niii1l1O_dataout WHEN niOlO0l0i = '1' ELSE wire_ni1111iO_dataout; + wire_n100000i_dataout <= wire_n1i1lllO_dataout AND NOT(niOl00l1l); + wire_n100000l_dataout <= wire_n1i1llOi_dataout AND NOT(niOl00l1l); + wire_n100000O_dataout <= wire_n10iOiOl_dataout AND NOT(niOl00l1l); + wire_n100001i_dataout <= wire_n1i1lliO_dataout AND NOT(niOl00l1l); + wire_n100001l_dataout <= wire_n1i1llli_dataout AND NOT(niOl00l1l); + wire_n100001O_dataout <= wire_n1i1llll_dataout AND NOT(niOl00l1l); + wire_n10000i_dataout <= nlOi1lOl WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(122); + wire_n10000ii_dataout <= wire_n1i1llOO_dataout AND NOT(niOl00l1l); + wire_n10000il_dataout <= wire_n1i1lO1i_dataout AND NOT(niOl00l1l); + wire_n10000l_dataout <= nlOi1lOO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(123); + wire_n10000O_dataout <= nlOi1O1i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(124); + wire_n100010i_dataout <= wire_n100101O_dataout AND NOT(niOl00l1l); + wire_n100010l_dataout <= wire_n1i1liOi_dataout OR niOl00l1l; + wire_n100010O_dataout <= wire_n1i1liOl_dataout AND NOT(niOl00l1l); + wire_n100011i_dataout <= wire_n1i1liiO_dataout AND NOT(niOl00l1l); + wire_n100011l_dataout <= wire_n1i1lili_dataout AND NOT(niOl00l1l); + wire_n100011O_dataout <= wire_n1i1lill_dataout AND NOT(niOl00l1l); + wire_n10001i_dataout <= nlOi1lll WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(119); + wire_n10001ii_dataout <= wire_n1i1liOO_dataout AND NOT(niOl00l1l); + wire_n10001il_dataout <= wire_n1i1ll1i_dataout AND NOT(niOl00l1l); + wire_n10001iO_dataout <= wire_n1i1ll1l_dataout AND NOT(niOl00l1l); + wire_n10001l_dataout <= nlOi1llO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(120); + wire_n10001li_dataout <= wire_n1i1ll1O_dataout AND NOT(niOl00l1l); + wire_n10001ll_dataout <= wire_n1i1ll0i_dataout AND NOT(niOl00l1l); + wire_n10001lO_dataout <= wire_n1i1ll0l_dataout AND NOT(niOl00l1l); + wire_n10001O_dataout <= nlOi1lOi WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(121); + wire_n10001Oi_dataout <= wire_n1i1ll0O_dataout AND NOT(niOl00l1l); + wire_n10001Ol_dataout <= wire_n1i1llii_dataout AND NOT(niOl00l1l); + wire_n10001OO_dataout <= wire_n1i1llil_dataout AND NOT(niOl00l1l); + wire_n1000i0i_dataout <= wire_n1000lOl_dataout AND NOT(niOl00liO); + wire_n1000i0l_dataout <= wire_n1000lOO_dataout AND NOT(niOl00liO); + wire_n1000i0O_dataout <= wire_n1000O1i_dataout AND NOT(niOl00liO); + wire_n1000i1i_dataout <= n11O1O0i OR n1lillil; + wire_n1000i1l_dataout <= wire_n1000llO_dataout AND NOT(niOl00liO); + wire_n1000i1O_dataout <= wire_n1000lOi_dataout AND NOT(niOl00liO); + wire_n1000ii_dataout <= nlOi1O1l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(125); + wire_n1000iii_dataout <= wire_n1000O1l_dataout AND NOT(niOl00liO); + wire_n1000iil_dataout <= wire_n1000O1O_dataout AND NOT(niOl00liO); + wire_n1000iiO_dataout <= wire_n1000O0i_dataout AND NOT(niOl00liO); + wire_n1000il_dataout <= nlOi1O1O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(126); + wire_n1000ili_dataout <= wire_n1000O0l_dataout AND NOT(niOl00liO); + wire_n1000ill_dataout <= wire_n1000O0O_dataout AND NOT(niOl00liO); + wire_n1000ilO_dataout <= wire_n1000Oii_dataout AND NOT(niOl00liO); + wire_n1000iO_dataout <= nlOi1O0i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(127); + wire_n1000iOi_dataout <= wire_n1000Oil_dataout AND NOT(niOl00liO); + wire_n1000iOl_dataout <= wire_n1000OiO_dataout AND NOT(niOl00liO); + wire_n1000iOO_dataout <= wire_n1000Oli_dataout AND NOT(niOl00liO); + wire_n1000l0i_dataout <= wire_n1000OOl_dataout AND NOT(niOl00liO); + wire_n1000l0l_dataout <= wire_n1000OOO_dataout AND NOT(niOl00liO); + wire_n1000l0O_dataout <= wire_n100i11i_dataout AND NOT(niOl00liO); + wire_n1000l1i_dataout <= wire_n1000Oll_dataout AND NOT(niOl00liO); + wire_n1000l1l_dataout <= wire_n1000OlO_dataout AND NOT(niOl00liO); + wire_n1000l1O_dataout <= wire_n1000OOi_dataout AND NOT(niOl00liO); + wire_n1000li_dataout <= nlOi1O0l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(132); + wire_n1000lii_dataout <= wire_n100i11l_dataout AND NOT(niOl00liO); + wire_n1000lil_dataout <= wire_n100i11O_dataout AND NOT(niOl00liO); + wire_n1000liO_dataout <= wire_n100i10i_dataout AND NOT(niOl00liO); + wire_n1000lli_dataout <= wire_n100i10l_dataout AND NOT(niOl00liO); + wire_n1000lll_dataout <= wire_n100i10O_dataout OR niOl00liO; + wire_n1000llO_dataout <= wire_n100i1ii_dataout AND NOT(niOl00lii); + wire_n1000lOi_dataout <= wire_n100i1il_dataout AND NOT(niOl00lii); + wire_n1000lOl_dataout <= wire_n100i1iO_dataout AND NOT(niOl00lii); + wire_n1000lOO_dataout <= wire_n100i1li_dataout AND NOT(niOl00lii); + wire_n1000O0i_dataout <= wire_n100i1Ol_dataout AND NOT(niOl00lii); + wire_n1000O0l_dataout <= wire_n100i1OO_dataout AND NOT(niOl00lii); + wire_n1000O0O_dataout <= wire_n100i01i_dataout AND NOT(niOl00lii); + wire_n1000O1i_dataout <= wire_n100i1ll_dataout AND NOT(niOl00lii); + wire_n1000O1l_dataout <= wire_n100i1lO_dataout AND NOT(niOl00lii); + wire_n1000O1O_dataout <= wire_n100i1Oi_dataout AND NOT(niOl00lii); + wire_n1000Oi_dataout <= nlOi0lll WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(96); + wire_n1000Oii_dataout <= wire_n100i01l_dataout AND NOT(niOl00lii); + wire_n1000Oil_dataout <= wire_n100i01O_dataout AND NOT(niOl00lii); + wire_n1000OiO_dataout <= wire_n100i00i_dataout AND NOT(niOl00lii); + wire_n1000Ol_dataout <= nlOi0llO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(97); + wire_n1000Oli_dataout <= wire_n100i00l_dataout AND NOT(niOl00lii); + wire_n1000Oll_dataout <= wire_n100i00O_dataout AND NOT(niOl00lii); + wire_n1000OlO_dataout <= wire_n100i0ii_dataout AND NOT(niOl00lii); + wire_n1000OO_dataout <= nlOi0lOi WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(98); + wire_n1000OOi_dataout <= wire_n100i0il_dataout AND NOT(niOl00lii); + wire_n1000OOl_dataout <= wire_n100i0iO_dataout AND NOT(niOl00lii); + wire_n1000OOO_dataout <= wire_n100i0li_dataout AND NOT(niOl00lii); + wire_n100100i_dataout <= wire_n1001OOi_dataout WHEN niOl00l1O = '1' ELSE wire_n1001iOO_dataout; + wire_n100100l_dataout <= wire_n1001OOl_dataout WHEN niOl00l1O = '1' ELSE wire_n1001l1i_dataout; + wire_n100100O_dataout <= wire_n1001OOO_dataout WHEN niOl00l1O = '1' ELSE wire_n1001l1l_dataout; + wire_n100101i_dataout <= wire_n1001iOi_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1llOO_dataout; + wire_n100101l_dataout <= wire_n1001iOl_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1lO1i_dataout; + wire_n100101O_dataout <= n11O0l0i OR n1iO0l0O; + wire_n10010i_dataout <= nlOi1iOl WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(107); + wire_n10010ii_dataout <= wire_n100011i_dataout WHEN niOl00l1O = '1' ELSE wire_n1001l1O_dataout; + wire_n10010il_dataout <= wire_n100011l_dataout WHEN niOl00l1O = '1' ELSE wire_n1001l0i_dataout; + wire_n10010iO_dataout <= wire_n100011O_dataout WHEN niOl00l1O = '1' ELSE wire_n1001l0l_dataout; + wire_n10010l_dataout <= nlOi1iOO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(108); + wire_n10010li_dataout <= wire_n100010i_dataout WHEN niOl00l1O = '1' ELSE wire_n1001l0O_dataout; + wire_n10010ll_dataout <= wire_n100010l_dataout WHEN niOl00l1O = '1' ELSE wire_n1001lii_dataout; + wire_n10010lO_dataout <= wire_n100010O_dataout WHEN niOl00l1O = '1' ELSE wire_n1001lil_dataout; + wire_n10010O_dataout <= nlOi1l1i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(109); + wire_n10010Oi_dataout <= wire_n10001ii_dataout WHEN niOl00l1O = '1' ELSE wire_n1001liO_dataout; + wire_n10010Ol_dataout <= wire_n10001il_dataout WHEN niOl00l1O = '1' ELSE wire_n1001lli_dataout; + wire_n10010OO_dataout <= wire_n10001iO_dataout WHEN niOl00l1O = '1' ELSE wire_n1001lll_dataout; + wire_n100110i_dataout <= wire_n1001i1i_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1ll1O_dataout; + wire_n100110l_dataout <= wire_n1001i1l_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1ll0i_dataout; + wire_n100110O_dataout <= wire_n1001i1O_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1ll0l_dataout; + wire_n100111i_dataout <= wire_n10010Oi_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1liOO_dataout; + wire_n100111l_dataout <= wire_n10010Ol_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1ll1i_dataout; + wire_n100111O_dataout <= wire_n10010OO_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1ll1l_dataout; + wire_n10011i_dataout <= nlOi1ill WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(104); + wire_n10011ii_dataout <= wire_n1001i0i_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1ll0O_dataout; + wire_n10011il_dataout <= wire_n1001i0l_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1llii_dataout; + wire_n10011iO_dataout <= wire_n1001i0O_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1llil_dataout; + wire_n10011l_dataout <= nlOi1ilO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(105); + wire_n10011li_dataout <= wire_n1001iii_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1lliO_dataout; + wire_n10011ll_dataout <= wire_n1001iil_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1llli_dataout; + wire_n10011lO_dataout <= wire_n1001iiO_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1llll_dataout; + wire_n10011O_dataout <= nlOi1iOi WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(106); + wire_n10011Oi_dataout <= wire_n1001ili_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1lllO_dataout; + wire_n10011Ol_dataout <= wire_n1001ill_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1llOi_dataout; + wire_n10011OO_dataout <= wire_n1001ilO_dataout WHEN niOl00l0i = '1' ELSE wire_n10iOiOl_dataout; + wire_n1001i0i_dataout <= wire_n10001Oi_dataout WHEN niOl00l1O = '1' ELSE wire_n1001lOO_dataout; + wire_n1001i0l_dataout <= wire_n10001Ol_dataout WHEN niOl00l1O = '1' ELSE wire_n1001O1i_dataout; + wire_n1001i0O_dataout <= wire_n10001OO_dataout WHEN niOl00l1O = '1' ELSE wire_n1001O1l_dataout; + wire_n1001i1i_dataout <= wire_n10001li_dataout WHEN niOl00l1O = '1' ELSE wire_n1001llO_dataout; + wire_n1001i1l_dataout <= wire_n10001ll_dataout WHEN niOl00l1O = '1' ELSE wire_n1001lOi_dataout; + wire_n1001i1O_dataout <= wire_n10001lO_dataout WHEN niOl00l1O = '1' ELSE wire_n1001lOl_dataout; + wire_n1001ii_dataout <= nlOi1l1l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(110); + wire_n1001iii_dataout <= wire_n100001i_dataout WHEN niOl00l1O = '1' ELSE wire_n1001O1O_dataout; + wire_n1001iil_dataout <= wire_n100001l_dataout WHEN niOl00l1O = '1' ELSE wire_n1001O0i_dataout; + wire_n1001iiO_dataout <= wire_n100001O_dataout WHEN niOl00l1O = '1' ELSE wire_n1001O0l_dataout; + wire_n1001il_dataout <= nlOi1l1O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(111); + wire_n1001ili_dataout <= wire_n100000i_dataout WHEN niOl00l1O = '1' ELSE wire_n1001O0O_dataout; + wire_n1001ill_dataout <= wire_n100000l_dataout WHEN niOl00l1O = '1' ELSE wire_n1001Oii_dataout; + wire_n1001ilO_dataout <= wire_n100000O_dataout WHEN niOl00l1O = '1' ELSE wire_n1001Oil_dataout; + wire_n1001iO_dataout <= nlOi1l0i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(112); + wire_n1001iOi_dataout <= wire_n10000ii_dataout WHEN niOl00l1O = '1' ELSE wire_n1001OiO_dataout; + wire_n1001iOl_dataout <= wire_n10000il_dataout WHEN niOl00l1O = '1' ELSE wire_n1001Oli_dataout; + wire_n1001iOO_dataout <= wire_n1i1lO0l_dataout AND NOT(niOl00l1i); + wire_n1001l0i_dataout <= wire_n1i1lili_dataout AND NOT(niOl00l1i); + wire_n1001l0l_dataout <= wire_n1i1lill_dataout AND NOT(niOl00l1i); + wire_n1001l0O_dataout <= wire_n100101O_dataout AND NOT(niOl00l1i); + wire_n1001l1i_dataout <= wire_n1i1liii_dataout AND NOT(niOl00l1i); + wire_n1001l1l_dataout <= wire_n1i1liil_dataout AND NOT(niOl00l1i); + wire_n1001l1O_dataout <= wire_n1i1liiO_dataout AND NOT(niOl00l1i); + wire_n1001li_dataout <= nlOi1l0l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(113); + wire_n1001lii_dataout <= wire_n1i1liOi_dataout OR niOl00l1i; + wire_n1001lil_dataout <= wire_n1i1liOl_dataout AND NOT(niOl00l1i); + wire_n1001liO_dataout <= wire_n1i1liOO_dataout AND NOT(niOl00l1i); + wire_n1001ll_dataout <= nlOi1l0O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(114); + wire_n1001lli_dataout <= wire_n1i1ll1i_dataout AND NOT(niOl00l1i); + wire_n1001lll_dataout <= wire_n1i1ll1l_dataout AND NOT(niOl00l1i); + wire_n1001llO_dataout <= wire_n1i1ll1O_dataout AND NOT(niOl00l1i); + wire_n1001lO_dataout <= nlOi1lii WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(115); + wire_n1001lOi_dataout <= wire_n1i1ll0i_dataout AND NOT(niOl00l1i); + wire_n1001lOl_dataout <= wire_n1i1ll0l_dataout AND NOT(niOl00l1i); + wire_n1001lOO_dataout <= wire_n1i1ll0O_dataout AND NOT(niOl00l1i); + wire_n1001O0i_dataout <= wire_n1i1llli_dataout AND NOT(niOl00l1i); + wire_n1001O0l_dataout <= wire_n1i1llll_dataout AND NOT(niOl00l1i); + wire_n1001O0O_dataout <= wire_n1i1lllO_dataout AND NOT(niOl00l1i); + wire_n1001O1i_dataout <= wire_n1i1llii_dataout AND NOT(niOl00l1i); + wire_n1001O1l_dataout <= wire_n1i1llil_dataout AND NOT(niOl00l1i); + wire_n1001O1O_dataout <= wire_n1i1lliO_dataout AND NOT(niOl00l1i); + wire_n1001Oi_dataout <= nlOi1lil WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(116); + wire_n1001Oii_dataout <= wire_n1i1llOi_dataout AND NOT(niOl00l1i); + wire_n1001Oil_dataout <= wire_n10iOiOl_dataout AND NOT(niOl00l1i); + wire_n1001OiO_dataout <= wire_n1i1llOO_dataout AND NOT(niOl00l1i); + wire_n1001Ol_dataout <= nlOi1liO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(117); + wire_n1001Oli_dataout <= wire_n1i1lO1i_dataout AND NOT(niOl00l1i); + wire_n1001OO_dataout <= nlOi1lli WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(118); + wire_n1001OOi_dataout <= wire_n1i1lO0l_dataout AND NOT(niOl00l1l); + wire_n1001OOl_dataout <= wire_n1i1liii_dataout AND NOT(niOl00l1l); + wire_n1001OOO_dataout <= wire_n1i1liil_dataout AND NOT(niOl00l1l); + wire_n100i00i_dataout <= n11O0lll AND NOT(niOl00l0l); + wire_n100i00l_dataout <= n11O0llO AND NOT(niOl00l0l); + wire_n100i00O_dataout <= n11O0lOi AND NOT(niOl00l0l); + wire_n100i01i_dataout <= n11O0lil AND NOT(niOl00l0l); + wire_n100i01l_dataout <= n11O0liO AND NOT(niOl00l0l); + wire_n100i01O_dataout <= n11O0lli AND NOT(niOl00l0l); + wire_n100i0i_dataout <= nlOi0O1l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(102); + wire_n100i0ii_dataout <= n11O0lOl AND NOT(niOl00l0l); + wire_n100i0il_dataout <= n11O0lOO AND NOT(niOl00l0l); + wire_n100i0iO_dataout <= n11O0O1i AND NOT(niOl00l0l); + wire_n100i0l_dataout <= nlOi0O1O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(103); + wire_n100i0li_dataout <= n11O0O1l AND NOT(niOl00l0l); + wire_n100i0ll_dataout <= n11O0O1O AND NOT(niOl00l0l); + wire_n100i0lO_dataout <= n11O0O0i AND NOT(niOl00l0l); + wire_n100i0O_dataout <= nlOi0O0i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(104); + wire_n100i0Oi_dataout <= n11O0O0l AND NOT(niOl00l0l); + wire_n100i0Ol_dataout <= n11O0O0O AND NOT(niOl00l0l); + wire_n100i0OO_dataout <= n11O0Oii AND NOT(niOl00l0l); + wire_n100i10i_dataout <= wire_n100i0Ol_dataout AND NOT(niOl00lii); + wire_n100i10l_dataout <= wire_n100i0OO_dataout AND NOT(niOl00lii); + wire_n100i10O_dataout <= wire_n100ii1i_dataout OR niOl00lii; + wire_n100i11i_dataout <= wire_n100i0ll_dataout AND NOT(niOl00lii); + wire_n100i11l_dataout <= wire_n100i0lO_dataout AND NOT(niOl00lii); + wire_n100i11O_dataout <= wire_n100i0Oi_dataout AND NOT(niOl00lii); + wire_n100i1i_dataout <= nlOi0lOl WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(99); + wire_n100i1ii_dataout <= n11O0iOl AND NOT(niOl00l0l); + wire_n100i1il_dataout <= n11O0iOO AND NOT(niOl00l0l); + wire_n100i1iO_dataout <= n11O0l1i AND NOT(niOl00l0l); + wire_n100i1l_dataout <= nlOi0lOO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(100); + wire_n100i1li_dataout <= n11O0l1l AND NOT(niOl00l0l); + wire_n100i1ll_dataout <= n11O0l1O AND NOT(niOl00l0l); + wire_n100i1lO_dataout <= n11O0l0i AND NOT(niOl00l0l); + wire_n100i1O_dataout <= nlOi0O1i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(101); + wire_n100i1Oi_dataout <= n11O0l0l AND NOT(niOl00l0l); + wire_n100i1Ol_dataout <= n11O0l0O AND NOT(niOl00l0l); + wire_n100i1OO_dataout <= n11O0lii AND NOT(niOl00l0l); + wire_n100ii1i_dataout <= n11O0Oil OR niOl00l0l; + wire_n100iii_dataout <= nlOi0O0l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(105); + wire_n100iiil_dataout <= n11O0iOl AND NOT(niOli10Ol); + wire_n100iiiO_dataout <= n11O0iOO AND NOT(niOli10Ol); + wire_n100iil_dataout <= nlOi0O0O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(106); + wire_n100iili_dataout <= n11O0l1i AND NOT(niOli10Ol); + wire_n100iill_dataout <= n11O0l1l AND NOT(niOli10Ol); + wire_n100iilO_dataout <= n11O0l1O AND NOT(niOli10Ol); + wire_n100iiO_dataout <= nlOi0Oii WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(107); + wire_n100iiOi_dataout <= n11O0l0i AND NOT(niOli10Ol); + wire_n100iiOl_dataout <= n11O0l0l AND NOT(niOli10Ol); + wire_n100iiOO_dataout <= n11O0l0O AND NOT(niOli10Ol); + wire_n100il0i_dataout <= n11O0lli AND NOT(niOli10Ol); + wire_n100il0l_dataout <= n11O0lll AND NOT(niOli10Ol); + wire_n100il0O_dataout <= n11O0llO AND NOT(niOli10Ol); + wire_n100il1i_dataout <= n11O0lii AND NOT(niOli10Ol); + wire_n100il1l_dataout <= n11O0lil AND NOT(niOli10Ol); + wire_n100il1O_dataout <= n11O0liO AND NOT(niOli10Ol); + wire_n100ili_dataout <= nlOi0Oil WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(108); + wire_n100ilii_dataout <= n11O0lOi AND NOT(niOli10Ol); + wire_n100ilil_dataout <= n11O0lOl AND NOT(niOli10Ol); + wire_n100iliO_dataout <= n11O0lOO AND NOT(niOli10Ol); + wire_n100ill_dataout <= nlOi0OiO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(109); + wire_n100illi_dataout <= n11O0O1i AND NOT(niOli10Ol); + wire_n100illl_dataout <= n11O0O1l AND NOT(niOli10Ol); + wire_n100illO_dataout <= n11O0O1O AND NOT(niOli10Ol); + wire_n100ilO_dataout <= nlOi0Oli WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(110); + wire_n100ilOi_dataout <= n11O0O0i AND NOT(niOli10Ol); + wire_n100ilOl_dataout <= n11O0O0l AND NOT(niOli10Ol); + wire_n100ilOO_dataout <= n11O0O0O AND NOT(niOli10Ol); + wire_n100iO0i_dataout <= n11O00il WHEN niOl0iOiO = '1' ELSE wire_n100l00i_dataout; + wire_n100iO0l_dataout <= n11O1O0i WHEN niOl0iOiO = '1' ELSE wire_n100l00l_dataout; + wire_n100iO0O_dataout <= n11O00iO WHEN niOl0iOiO = '1' ELSE wire_n100l00O_dataout; + wire_n100iO1i_dataout <= n11O0Oii AND NOT(niOli10Ol); + wire_n100iO1l_dataout <= n11O0Oil OR niOli10Ol; + wire_n100iO1O_dataout <= n11O0i0l WHEN niOl0iOiO = '1' ELSE wire_n100l01O_dataout; + wire_n100iOi_dataout <= nlOi0Oll WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(111); + wire_n100iOii_dataout <= n11O0i0O WHEN niOl0iOiO = '1' ELSE wire_n100l0ii_dataout; + wire_n100iOil_dataout <= wire_n100l0il_dataout AND NOT(niOl0iOiO); + wire_n100iOiO_dataout <= wire_n100l0iO_dataout AND NOT(niOl0iOiO); + wire_n100iOl_dataout <= nlOi0OlO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(112); + wire_n100iOli_dataout <= wire_n100l0li_dataout AND NOT(niOl0iOiO); + wire_n100iOll_dataout <= wire_n100l0ll_dataout AND NOT(niOl0iOiO); + wire_n100iOlO_dataout <= wire_n100l0lO_dataout AND NOT(niOl0iOiO); + wire_n100iOO_dataout <= nlOi0OOi WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(113); + wire_n100iOOi_dataout <= wire_n100l0Oi_dataout AND NOT(niOl0iOiO); + wire_n100iOOl_dataout <= wire_n100l0Ol_dataout AND NOT(niOl0iOiO); + wire_n100iOOO_dataout <= wire_n100l0OO_dataout AND NOT(niOl0iOiO); + wire_n100l00i_dataout <= n11O00il WHEN niOl00lOl = '1' ELSE wire_n100ll0i_dataout; + wire_n100l00l_dataout <= n11O1O0i WHEN niOl00lOl = '1' ELSE wire_n100ll0l_dataout; + wire_n100l00O_dataout <= n11O00iO WHEN niOl00lOl = '1' ELSE wire_n100O11i_dataout; + wire_n100l01i_dataout <= wire_n100ll1i_dataout AND NOT(niOl0iOiO); + wire_n100l01l_dataout <= wire_n100ll1l_dataout AND NOT(niOl0iOiO); + wire_n100l01O_dataout <= n11O0i0l WHEN niOl00lOl = '1' ELSE wire_n100ll1O_dataout; + wire_n100l0i_dataout <= nlOii11l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(117); + wire_n100l0ii_dataout <= n11O0i0O WHEN niOl00lOl = '1' ELSE wire_n100O11l_dataout; + wire_n100l0il_dataout <= wire_n100ll0O_dataout AND NOT(niOl00lOl); + wire_n100l0iO_dataout <= wire_n100llii_dataout AND NOT(niOl00lOl); + wire_n100l0l_dataout <= nlOii11O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(118); + wire_n100l0li_dataout <= wire_n100llil_dataout AND NOT(niOl00lOl); + wire_n100l0ll_dataout <= wire_n100lliO_dataout AND NOT(niOl00lOl); + wire_n100l0lO_dataout <= wire_n100llli_dataout OR niOl00lOl; + wire_n100l0O_dataout <= nlOii10i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(119); + wire_n100l0Oi_dataout <= wire_n100llll_dataout AND NOT(niOl00lOl); + wire_n100l0Ol_dataout <= wire_n100lllO_dataout AND NOT(niOl00lOl); + wire_n100l0OO_dataout <= wire_n100llOi_dataout AND NOT(niOl00lOl); + wire_n100l10i_dataout <= wire_n100li0i_dataout AND NOT(niOl0iOiO); + wire_n100l10l_dataout <= wire_n100li0l_dataout AND NOT(niOl0iOiO); + wire_n100l10O_dataout <= wire_n100li0O_dataout AND NOT(niOl0iOiO); + wire_n100l11i_dataout <= wire_n100li1i_dataout OR niOl0iOiO; + wire_n100l11l_dataout <= wire_n100li1l_dataout AND NOT(niOl0iOiO); + wire_n100l11O_dataout <= wire_n100li1O_dataout AND NOT(niOl0iOiO); + wire_n100l1i_dataout <= nlOi0OOl WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(114); + wire_n100l1ii_dataout <= wire_n100liii_dataout AND NOT(niOl0iOiO); + wire_n100l1il_dataout <= wire_n100liil_dataout AND NOT(niOl0iOiO); + wire_n100l1iO_dataout <= wire_n100liiO_dataout AND NOT(niOl0iOiO); + wire_n100l1l_dataout <= nlOi0OOO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(115); + wire_n100l1li_dataout <= wire_n100lili_dataout AND NOT(niOl0iOiO); + wire_n100l1ll_dataout <= wire_n100lill_dataout AND NOT(niOl0iOiO); + wire_n100l1lO_dataout <= wire_n100lilO_dataout AND NOT(niOl0iOiO); + wire_n100l1O_dataout <= nlOii11i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(116); + wire_n100l1Oi_dataout <= wire_n100liOi_dataout AND NOT(niOl0iOiO); + wire_n100l1Ol_dataout <= wire_n100liOl_dataout AND NOT(niOl0iOiO); + wire_n100l1OO_dataout <= wire_n100liOO_dataout AND NOT(niOl0iOiO); + wire_n100li0i_dataout <= wire_n100lO1l_dataout AND NOT(niOl00lOl); + wire_n100li0l_dataout <= wire_n100lO1O_dataout AND NOT(niOl00lOl); + wire_n100li0O_dataout <= wire_n100lO0i_dataout AND NOT(niOl00lOl); + wire_n100li1i_dataout <= wire_n100llOl_dataout AND NOT(niOl00lOl); + wire_n100li1l_dataout <= wire_n100llOO_dataout AND NOT(niOl00lOl); + wire_n100li1O_dataout <= wire_n100lO1i_dataout AND NOT(niOl00lOl); + wire_n100lii_dataout <= nlOii10l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(120); + wire_n100liii_dataout <= wire_n100lO0l_dataout AND NOT(niOl00lOl); + wire_n100liil_dataout <= wire_n100lO0O_dataout AND NOT(niOl00lOl); + wire_n100liiO_dataout <= wire_n100lOii_dataout AND NOT(niOl00lOl); + wire_n100lil_dataout <= nlOii10O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(121); + wire_n100lili_dataout <= wire_n100lOil_dataout AND NOT(niOl00lOl); + wire_n100lill_dataout <= wire_n100lOiO_dataout AND NOT(niOl00lOl); + wire_n100lilO_dataout <= wire_n100lOli_dataout AND NOT(niOl00lOl); + wire_n100liO_dataout <= nlOii1ii WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(122); + wire_n100liOi_dataout <= wire_n100lOll_dataout AND NOT(niOl00lOl); + wire_n100liOl_dataout <= wire_n100lOlO_dataout AND NOT(niOl00lOl); + wire_n100liOO_dataout <= wire_n100lOOi_dataout AND NOT(niOl00lOl); + wire_n100ll0i_dataout <= n11O00il WHEN wire_w_lg_niOl00lli21189w(0) = '1' ELSE wire_n100O10l_dataout; + wire_n100ll0l_dataout <= n11O1O0i WHEN wire_w_lg_niOl00lli21189w(0) = '1' ELSE wire_n100O10O_dataout; + wire_n100ll0O_dataout <= wire_n100O1ii_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100ll1i_dataout <= wire_n100lOOl_dataout AND NOT(niOl00lOl); + wire_n100ll1l_dataout <= wire_n100lOOO_dataout AND NOT(niOl00lOl); + wire_n100ll1O_dataout <= n11O0i0l WHEN wire_w_lg_niOl00lli21189w(0) = '1' ELSE wire_n100O10i_dataout; + wire_n100lli_dataout <= nlOii1il WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(123); + wire_n100llii_dataout <= wire_n100O1il_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100llil_dataout <= wire_n100O1iO_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lliO_dataout <= wire_n100O1li_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lll_dataout <= nlOii1iO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(124); + wire_n100llli_dataout <= wire_n100O1ll_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100llll_dataout <= wire_n100O1lO_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lllO_dataout <= wire_n100O1Oi_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100llO_dataout <= nlOii1li WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(125); + wire_n100llOi_dataout <= wire_n100O1Ol_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100llOl_dataout <= wire_n100O1OO_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100llOO_dataout <= wire_n100O01i_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lO0i_dataout <= wire_n100O00l_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lO0l_dataout <= wire_n100O00O_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lO0O_dataout <= wire_n100O0ii_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lO1i_dataout <= wire_n100O01l_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lO1l_dataout <= wire_n100O01O_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lO1O_dataout <= wire_n100O00i_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOi_dataout <= nlOii1ll WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(126); + wire_n100lOii_dataout <= wire_n100O0il_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOil_dataout <= wire_n100O0iO_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOiO_dataout <= wire_n100O0li_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOl_dataout <= nlOii1lO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(127); + wire_n100lOli_dataout <= wire_n100O0ll_dataout OR wire_w_lg_niOl00lli21189w(0); + wire_n100lOll_dataout <= wire_n100O0lO_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOlO_dataout <= wire_n100O0Oi_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOO_dataout <= nlOii1Oi WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(64); + wire_n100lOOi_dataout <= wire_n100O0Ol_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOOl_dataout <= wire_n100O0OO_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100lOOO_dataout <= wire_n100Oi1i_dataout AND NOT(wire_w_lg_niOl00lli21189w(0)); + wire_n100O00i_dataout <= wire_n100Ol1i_dataout AND NOT(niOl00llO); + wire_n100O00l_dataout <= wire_n100Ol1l_dataout AND NOT(niOl00llO); + wire_n100O00O_dataout <= wire_n100Ol1O_dataout AND NOT(niOl00llO); + wire_n100O01i_dataout <= wire_n100OiOi_dataout AND NOT(niOl00llO); + wire_n100O01l_dataout <= wire_n100OiOl_dataout AND NOT(niOl00llO); + wire_n100O01O_dataout <= wire_n100OiOO_dataout AND NOT(niOl00llO); + wire_n100O0i_dataout <= nlOii01l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(68); + wire_n100O0ii_dataout <= wire_n100Ol0i_dataout AND NOT(niOl00llO); + wire_n100O0il_dataout <= wire_n100Ol0l_dataout AND NOT(niOl00llO); + wire_n100O0iO_dataout <= wire_n100Ol0O_dataout AND NOT(niOl00llO); + wire_n100O0l_dataout <= nlOii01O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(69); + wire_n100O0li_dataout <= wire_n100Olii_dataout AND NOT(niOl00llO); + wire_n100O0ll_dataout <= wire_n100Olil_dataout AND NOT(niOl00llO); + wire_n100O0lO_dataout <= wire_n100OliO_dataout AND NOT(niOl00llO); + wire_n100O0O_dataout <= nlOii00i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(70); + wire_n100O0Oi_dataout <= wire_n100Olli_dataout AND NOT(niOl00llO); + wire_n100O0Ol_dataout <= wire_n100Olll_dataout AND NOT(niOl00llO); + wire_n100O0OO_dataout <= wire_n100OllO_dataout AND NOT(niOl00llO); + wire_n100O10i_dataout <= n11O0i0l WHEN niOl00llO = '1' ELSE wire_n100Oi1O_dataout; + wire_n100O10l_dataout <= n11O00il WHEN niOl00llO = '1' ELSE wire_n100OlOl_dataout; + wire_n100O10O_dataout <= n11O1O0i OR niOl00llO; + wire_n100O11i_dataout <= n11O00iO OR wire_w_lg_niOl00lli21189w(0); + wire_n100O11l_dataout <= wire_n10lii1i_dataout WHEN wire_w_lg_niOl00lli21189w(0) = '1' ELSE wire_n100O11O_dataout; + wire_n100O11O_dataout <= n11O0i0O WHEN niOl00llO = '1' ELSE wire_n100Oi1l_dataout; + wire_n100O1i_dataout <= nlOii1Ol WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(65); + wire_n100O1ii_dataout <= wire_n100Oi0i_dataout AND NOT(niOl00llO); + wire_n100O1il_dataout <= wire_n100Oi0l_dataout AND NOT(niOl00llO); + wire_n100O1iO_dataout <= wire_n100Oi0O_dataout AND NOT(niOl00llO); + wire_n100O1l_dataout <= nlOii1OO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(66); + wire_n100O1li_dataout <= wire_n100Oiii_dataout AND NOT(niOl00llO); + wire_n100O1ll_dataout <= wire_n100Oiil_dataout AND NOT(niOl00llO); + wire_n100O1lO_dataout <= wire_n100OiiO_dataout AND NOT(niOl00llO); + wire_n100O1O_dataout <= nlOii01i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(67); + wire_n100O1Oi_dataout <= wire_n100Oili_dataout AND NOT(niOl00llO); + wire_n100O1Ol_dataout <= wire_n100Oill_dataout OR niOl00llO; + wire_n100O1OO_dataout <= wire_n100OilO_dataout AND NOT(niOl00llO); + wire_n100Oi0i_dataout <= wire_n100OlOO_dataout AND NOT(niOl00lll); + wire_n100Oi0l_dataout <= wire_n100OO1i_dataout AND NOT(niOl00lll); + wire_n100Oi0O_dataout <= wire_n100OO1l_dataout AND NOT(niOl00lll); + wire_n100Oi1i_dataout <= wire_n100OlOi_dataout AND NOT(niOl00llO); + wire_n100Oi1l_dataout <= n11O0i0O WHEN niOl00lll = '1' ELSE wire_n10i11li_dataout; + wire_n100Oi1O_dataout <= n11O0i0l WHEN niOl00lll = '1' ELSE wire_n10i11ll_dataout; + wire_n100Oii_dataout <= nlOii00l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(71); + wire_n100Oiii_dataout <= wire_n100OO1O_dataout AND NOT(niOl00lll); + wire_n100Oiil_dataout <= wire_n100OO0i_dataout AND NOT(niOl00lll); + wire_n100OiiO_dataout <= wire_n100OO0l_dataout AND NOT(niOl00lll); + wire_n100Oil_dataout <= nlOii00O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(72); + wire_n100Oili_dataout <= wire_n100OO0O_dataout AND NOT(niOl00lll); + wire_n100Oill_dataout <= wire_n100OOii_dataout AND NOT(niOl00lll); + wire_n100OilO_dataout <= wire_n100OOil_dataout AND NOT(niOl00lll); + wire_n100OiO_dataout <= nlOii0ii WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(73); + wire_n100OiOi_dataout <= wire_n100OOiO_dataout OR niOl00lll; + wire_n100OiOl_dataout <= wire_n100OOli_dataout AND NOT(niOl00lll); + wire_n100OiOO_dataout <= wire_n100OOll_dataout AND NOT(niOl00lll); + wire_n100Ol0i_dataout <= wire_n100OOOO_dataout AND NOT(niOl00lll); + wire_n100Ol0l_dataout <= wire_n10i111i_dataout AND NOT(niOl00lll); + wire_n100Ol0O_dataout <= wire_n10i111l_dataout AND NOT(niOl00lll); + wire_n100Ol1i_dataout <= wire_n100OOlO_dataout AND NOT(niOl00lll); + wire_n100Ol1l_dataout <= wire_n100OOOi_dataout AND NOT(niOl00lll); + wire_n100Ol1O_dataout <= wire_n100OOOl_dataout AND NOT(niOl00lll); + wire_n100Oli_dataout <= nlOii0il WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(74); + wire_n100Olii_dataout <= wire_n10i111O_dataout AND NOT(niOl00lll); + wire_n100Olil_dataout <= wire_n10i110i_dataout AND NOT(niOl00lll); + wire_n100OliO_dataout <= wire_n10i110l_dataout AND NOT(niOl00lll); + wire_n100Oll_dataout <= nlOii0iO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(75); + wire_n100Olli_dataout <= wire_n10i110O_dataout AND NOT(niOl00lll); + wire_n100Olll_dataout <= wire_n10i11ii_dataout AND NOT(niOl00lll); + wire_n100OllO_dataout <= wire_n10i11il_dataout AND NOT(niOl00lll); + wire_n100OlO_dataout <= nlOii0li WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(76); + wire_n100OlOi_dataout <= wire_n10i11iO_dataout AND NOT(niOl00lll); + wire_n100OlOl_dataout <= wire_n10i11Ol_dataout WHEN niOl00lll = '1' ELSE n11O00il; + wire_n100OlOO_dataout <= n11O0iOl AND NOT(niOl0iO0i); + wire_n100OO0i_dataout <= n11O0l1O AND NOT(niOl0iO0i); + wire_n100OO0l_dataout <= n11O0l0i AND NOT(niOl0iO0i); + wire_n100OO0O_dataout <= n11O0l0l AND NOT(niOl0iO0i); + wire_n100OO1i_dataout <= n11O0iOO AND NOT(niOl0iO0i); + wire_n100OO1l_dataout <= n11O0l1i AND NOT(niOl0iO0i); + wire_n100OO1O_dataout <= n11O0l1l AND NOT(niOl0iO0i); + wire_n100OOi_dataout <= nlOii0ll WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(77); + wire_n100OOii_dataout <= n11O0l0O AND NOT(niOl0iO0i); + wire_n100OOil_dataout <= n11O0lii AND NOT(niOl0iO0i); + wire_n100OOiO_dataout <= n11O0lil AND NOT(niOl0iO0i); + wire_n100OOl_dataout <= nlOii0lO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(78); + wire_n100OOli_dataout <= n11O0liO AND NOT(niOl0iO0i); + wire_n100OOll_dataout <= n11O0lli AND NOT(niOl0iO0i); + wire_n100OOlO_dataout <= n11O0lll AND NOT(niOl0iO0i); + wire_n100OOO_dataout <= nlOii0Oi WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(79); + wire_n100OOOi_dataout <= wire_niO01iOi_w_lg_n11O0i0l21009w(0) WHEN niOl0iO0i = '1' ELSE n11O0llO; + wire_n100OOOl_dataout <= n11O0lOi AND NOT(niOl0iO0i); + wire_n100OOOO_dataout <= n11O0lOl AND NOT(niOl0iO0i); + wire_n101000i_dataout <= wire_n1010iOO_dataout AND NOT(niOl00iiO); + wire_n101000l_dataout <= wire_n1010l1i_dataout AND NOT(niOl00iiO); + wire_n101000O_dataout <= wire_n1010l1l_dataout AND NOT(niOl00iiO); + wire_n101001i_dataout <= wire_n1010ilO_dataout AND NOT(niOl00iiO); + wire_n101001l_dataout <= wire_n1010iOi_dataout AND NOT(niOl00iiO); + wire_n101001O_dataout <= wire_n1010iOl_dataout OR niOl00iiO; + wire_n10100i_dataout <= wire_nlll0lli_q(111) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(47); + wire_n10100ii_dataout <= wire_n1010l1O_dataout AND NOT(niOl00iiO); + wire_n10100il_dataout <= wire_n1010l0i_dataout AND NOT(niOl00iiO); + wire_n10100iO_dataout <= wire_n1010l0l_dataout AND NOT(niOl00iiO); + wire_n10100l_dataout <= wire_nlll0lli_q(112) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(48); + wire_n10100li_dataout <= wire_n1010l0O_dataout AND NOT(niOl00iiO); + wire_n10100ll_dataout <= wire_n1010lii_dataout AND NOT(niOl00iiO); + wire_n10100lO_dataout <= wire_n1010lil_dataout AND NOT(niOl00iiO); + wire_n10100O_dataout <= wire_nlll0lli_q(113) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(49); + wire_n10100Oi_dataout <= wire_n1010liO_dataout AND NOT(niOl00iiO); + wire_n10100Ol_dataout <= wire_n1010lli_dataout AND NOT(niOl00iiO); + wire_n10100OO_dataout <= n11O0ill AND NOT(niOl00iiO); + wire_n101010l_dataout <= wire_n1010i1i_dataout AND NOT(niOl00iiO); + wire_n101010O_dataout <= wire_n1010i1l_dataout AND NOT(niOl00iiO); + wire_n10101i_dataout <= wire_nlll0lli_q(108) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(44); + wire_n10101ii_dataout <= wire_n1010i1O_dataout AND NOT(niOl00iiO); + wire_n10101il_dataout <= wire_n1010i0i_dataout AND NOT(niOl00iiO); + wire_n10101iO_dataout <= wire_n1010i0l_dataout AND NOT(niOl00iiO); + wire_n10101l_dataout <= wire_nlll0lli_q(109) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(45); + wire_n10101li_dataout <= wire_n1010i0O_dataout AND NOT(niOl00iiO); + wire_n10101ll_dataout <= wire_n1010iii_dataout AND NOT(niOl00iiO); + wire_n10101lO_dataout <= wire_n1010iil_dataout AND NOT(niOl00iiO); + wire_n10101O_dataout <= wire_nlll0lli_q(110) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(46); + wire_n10101Oi_dataout <= wire_n1010iiO_dataout AND NOT(niOl00iiO); + wire_n10101Ol_dataout <= wire_n1010ili_dataout AND NOT(niOl00iiO); + wire_n10101OO_dataout <= wire_n1010ill_dataout AND NOT(niOl00iiO); + wire_n1010i0i_dataout <= n11O0l1l AND NOT(nlOll000O); + wire_n1010i0l_dataout <= n11O0l1O AND NOT(nlOll000O); + wire_n1010i0O_dataout <= n11O0l0i AND NOT(nlOll000O); + wire_n1010i1i_dataout <= n11O0iOl AND NOT(nlOll000O); + wire_n1010i1l_dataout <= n11O0iOO AND NOT(nlOll000O); + wire_n1010i1O_dataout <= n11O0l1i AND NOT(nlOll000O); + wire_n1010ii_dataout <= wire_nlll0lli_q(114) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(50); + wire_n1010iii_dataout <= n11O0l0l AND NOT(nlOll000O); + wire_n1010iil_dataout <= n11O0l0O AND NOT(nlOll000O); + wire_n1010iiO_dataout <= n11O0lii AND NOT(nlOll000O); + wire_n1010il_dataout <= wire_nlll0lli_q(115) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(51); + wire_n1010ili_dataout <= n11O0lil OR nlOll000O; + wire_n1010ill_dataout <= n11O0liO AND NOT(nlOll000O); + wire_n1010ilO_dataout <= n11O0lli AND NOT(nlOll000O); + wire_n1010iO_dataout <= wire_nlll0lli_q(116) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(52); + wire_n1010iOi_dataout <= n11O0lll AND NOT(nlOll000O); + wire_n1010iOl_dataout <= n11O0llO AND NOT(nlOll000O); + wire_n1010iOO_dataout <= n11O0lOi AND NOT(nlOll000O); + wire_n1010l0i_dataout <= n11O0O1l AND NOT(nlOll000O); + wire_n1010l0l_dataout <= n11O0O1O AND NOT(nlOll000O); + wire_n1010l0O_dataout <= n11O0O0i AND NOT(nlOll000O); + wire_n1010l1i_dataout <= n11O0lOl AND NOT(nlOll000O); + wire_n1010l1l_dataout <= n11O0lOO AND NOT(nlOll000O); + wire_n1010l1O_dataout <= n11O0O1i AND NOT(nlOll000O); + wire_n1010li_dataout <= wire_nlll0lli_q(117) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(53); + wire_n1010lii_dataout <= n11O0O0l AND NOT(nlOll000O); + wire_n1010lil_dataout <= n11O0O0O AND NOT(nlOll000O); + wire_n1010liO_dataout <= n11O0Oii AND NOT(nlOll000O); + wire_n1010ll_dataout <= wire_nlll0lli_q(118) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(54); + wire_n1010lli_dataout <= n11O0Oil AND NOT(nlOll000O); + wire_n1010lO_dataout <= wire_nlll0lli_q(119) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(55); + wire_n1010lOl_dataout <= wire_n101i1iO_dataout AND NOT(niOl00ili); + wire_n1010lOO_dataout <= wire_n101i1li_dataout AND NOT(niOl00ili); + wire_n1010O0i_dataout <= wire_n101i1Ol_dataout AND NOT(niOl00ili); + wire_n1010O0l_dataout <= wire_n101i1OO_dataout AND NOT(niOl00ili); + wire_n1010O0O_dataout <= wire_n101i01i_dataout AND NOT(niOl00ili); + wire_n1010O1i_dataout <= wire_n101i1ll_dataout AND NOT(niOl00ili); + wire_n1010O1l_dataout <= wire_n101i1lO_dataout AND NOT(niOl00ili); + wire_n1010O1O_dataout <= wire_n101i1Oi_dataout AND NOT(niOl00ili); + wire_n1010Oi_dataout <= wire_nlll0lli_q(120) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(56); + wire_n1010Oii_dataout <= wire_n101i01l_dataout AND NOT(niOl00ili); + wire_n1010Oil_dataout <= wire_n101i01O_dataout AND NOT(niOl00ili); + wire_n1010OiO_dataout <= wire_n101i00i_dataout AND NOT(niOl00ili); + wire_n1010Ol_dataout <= wire_nlll0lli_q(121) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(57); + wire_n1010Oli_dataout <= wire_n101i00l_dataout AND NOT(niOl00ili); + wire_n1010Oll_dataout <= wire_n101i00O_dataout AND NOT(niOl00ili); + wire_n1010OlO_dataout <= wire_n101i0ii_dataout AND NOT(niOl00ili); + wire_n1010OO_dataout <= wire_nlll0lli_q(122) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(58); + wire_n1010OOi_dataout <= wire_n101i0il_dataout AND NOT(niOl00ili); + wire_n1010OOl_dataout <= wire_n101i0iO_dataout AND NOT(niOl00ili); + wire_n1010OOO_dataout <= wire_n101i0li_dataout AND NOT(niOl00ili); + wire_n101100i_dataout <= wire_n1i0001O_dataout WHEN n11O0O0O = '1' ELSE n11O00Oi; + wire_n101100l_dataout <= wire_nlOi0iili_dataout WHEN n11O0O0O = '1' ELSE n11O00Ol; + wire_n10110i_dataout <= wire_nlll0lli_q(96) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(32); + wire_n10110l_dataout <= wire_nlll0lli_q(97) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(33); + wire_n10110O_dataout <= wire_nlll0lli_q(98) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(34); + wire_n101110l_dataout <= wire_n10OllOl_dataout WHEN n11O0O1O = '1' ELSE n11O00OO; + wire_n10111i_dataout <= wire_nlll0lli_q(93) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(29); + wire_n10111il_dataout <= wire_n10Ollll_dataout WHEN n11O0O1O = '1' ELSE n11O1lil; + wire_n10111iO_dataout <= wire_n1i101OO_dataout WHEN n11O0O0l = '1' ELSE n11O00li; + wire_n10111l_dataout <= wire_nlll0lli_q(94) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(30); + wire_n10111O_dataout <= wire_nlll0lli_q(95) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(31); + wire_n1011ii_dataout <= wire_nlll0lli_q(99) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(35); + wire_n1011il_dataout <= wire_nlll0lli_q(100) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(36); + wire_n1011iO_dataout <= wire_nlll0lli_q(101) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(37); + wire_n1011li_dataout <= wire_nlll0lli_q(102) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(38); + wire_n1011ll_dataout <= wire_nlll0lli_q(103) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(39); + wire_n1011lO_dataout <= wire_nlll0lli_q(104) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(40); + wire_n1011Oi_dataout <= wire_nlll0lli_q(105) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(41); + wire_n1011Ol_dataout <= wire_nlll0lli_q(106) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(42); + wire_n1011OO_dataout <= wire_nlll0lli_q(107) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(43); + wire_n101i00i_dataout <= wire_n101iiOl_dataout WHEN niOO10lOO = '1' ELSE n11O0liO; + wire_n101i00l_dataout <= wire_n101iiOO_dataout WHEN niOO10lOO = '1' ELSE n11O0lli; + wire_n101i00O_dataout <= wire_n101il1i_dataout WHEN niOO10lOO = '1' ELSE n11O0lll; + wire_n101i01i_dataout <= wire_n101iill_dataout WHEN niOO10lOO = '1' ELSE n11O0l0O; + wire_n101i01l_dataout <= wire_n101iilO_dataout WHEN niOO10lOO = '1' ELSE n11O0lii; + wire_n101i01O_dataout <= wire_n101iiOi_dataout WHEN niOO10lOO = '1' ELSE n11O0lil; + wire_n101i0i_dataout <= wire_nlll0lli_q(126) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(62); + wire_n101i0ii_dataout <= wire_n101il1l_dataout WHEN niOO10lOO = '1' ELSE n11O0llO; + wire_n101i0il_dataout <= wire_n101il1O_dataout WHEN niOO10lOO = '1' ELSE n11O0lOi; + wire_n101i0iO_dataout <= wire_n101il0i_dataout WHEN niOO10lOO = '1' ELSE n11O0lOl; + wire_n101i0l_dataout <= wire_nlll0lli_q(127) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(63); + wire_n101i0li_dataout <= wire_n101il0l_dataout WHEN niOO10lOO = '1' ELSE n11O0lOO; + wire_n101i0ll_dataout <= wire_n101il0O_dataout WHEN niOO10lOO = '1' ELSE n11O0O1i; + wire_n101i0lO_dataout <= wire_n101ilii_dataout WHEN niOO10lOO = '1' ELSE n11O0O1l; + wire_n101i0O_dataout <= nlOi111i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(64); + wire_n101i0Oi_dataout <= wire_n101ilil_dataout WHEN niOO10lOO = '1' ELSE n11O0O1O; + wire_n101i0Ol_dataout <= wire_n101iliO_dataout WHEN niOO10lOO = '1' ELSE n11O0O0i; + wire_n101i0OO_dataout <= wire_n101illi_dataout WHEN niOO10lOO = '1' ELSE n11O0O0l; + wire_n101i10i_dataout <= wire_n101i0Ol_dataout AND NOT(niOl00ili); + wire_n101i10l_dataout <= wire_n101i0OO_dataout AND NOT(niOl00ili); + wire_n101i10O_dataout <= wire_n101ii1i_dataout AND NOT(niOl00ili); + wire_n101i11i_dataout <= wire_n101i0ll_dataout AND NOT(niOl00ili); + wire_n101i11l_dataout <= wire_n101i0lO_dataout AND NOT(niOl00ili); + wire_n101i11O_dataout <= wire_n101i0Oi_dataout AND NOT(niOl00ili); + wire_n101i1i_dataout <= wire_nlll0lli_q(123) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(59); + wire_n101i1ii_dataout <= wire_n101ii1l_dataout AND NOT(niOl00ili); + wire_n101i1il_dataout <= wire_n101ii1O_dataout OR niOl00ili; + wire_n101i1iO_dataout <= wire_n101ii0i_dataout WHEN niOO10lOO = '1' ELSE n11O0iOl; + wire_n101i1l_dataout <= wire_nlll0lli_q(124) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(60); + wire_n101i1li_dataout <= wire_n101ii0l_dataout WHEN niOO10lOO = '1' ELSE n11O0iOO; + wire_n101i1ll_dataout <= wire_n101ii0O_dataout WHEN niOO10lOO = '1' ELSE n11O0l1i; + wire_n101i1lO_dataout <= wire_n101iiii_dataout WHEN niOO10lOO = '1' ELSE n11O0l1l; + wire_n101i1O_dataout <= wire_nlll0lli_q(125) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(61); + wire_n101i1Oi_dataout <= wire_n101iiil_dataout WHEN niOO10lOO = '1' ELSE n11O0l1O; + wire_n101i1Ol_dataout <= wire_n101iiiO_dataout WHEN niOO10lOO = '1' ELSE n11O0l0i; + wire_n101i1OO_dataout <= wire_n101iili_dataout WHEN niOO10lOO = '1' ELSE n11O0l0l; + wire_n101ii0i_dataout <= n11O0iOl AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101ii0l_dataout <= n11O0iOO AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101ii0O_dataout <= n11O0l1i AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101ii1i_dataout <= wire_n101illl_dataout WHEN niOO10lOO = '1' ELSE n11O0O0O; + wire_n101ii1l_dataout <= wire_n101illO_dataout WHEN niOO10lOO = '1' ELSE n11O0Oii; + wire_n101ii1O_dataout <= wire_n101ilOi_dataout WHEN niOO10lOO = '1' ELSE n11O0Oil; + wire_n101iii_dataout <= nlOi111l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(65); + wire_n101iiii_dataout <= n11O0l1l AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iiil_dataout <= n11O0l1O AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iiiO_dataout <= n11O0l0i AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iil_dataout <= nlOi111O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(66); + wire_n101iili_dataout <= n11O0l0l AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iill_dataout <= n11O0l0O AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iilO_dataout <= n11O0lii AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iiO_dataout <= nlOi110i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(67); + wire_n101iiOi_dataout <= n11O0lil AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iiOl_dataout <= n11O0liO AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iiOO_dataout <= n11O0lli AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101il0i_dataout <= n11O0lOl AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101il0l_dataout <= n11O0lOO AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101il0O_dataout <= n11O0O1i AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101il1i_dataout <= n11O0lll AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101il1l_dataout <= n11O0llO AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101il1O_dataout <= n11O0lOi AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101ili_dataout <= nlOi110l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(68); + wire_n101ilii_dataout <= n11O0O1l AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101ilil_dataout <= n11O0O1O AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101iliO_dataout <= n11O0O0i AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101ill_dataout <= nlOi110O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(69); + wire_n101illi_dataout <= n11O0O0l AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101illl_dataout <= n11O0O0O AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101illO_dataout <= n11O0Oii AND NOT(wire_w_lg_niOl00lil21194w(0)); + wire_n101ilO_dataout <= nlOi11ii WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(70); + wire_n101ilOi_dataout <= n11O0Oil OR wire_w_lg_niOl00lil21194w(0); + wire_n101iO0i_dataout <= n11O0iOO AND NOT(niOl00ill); + wire_n101iO0l_dataout <= n11O0l1i AND NOT(niOl00ill); + wire_n101iO0O_dataout <= n11O0l1l AND NOT(niOl00ill); + wire_n101iO1l_dataout <= wire_n10lii1i_dataout WHEN niOl00ill = '1' ELSE n11O0i0O; + wire_n101iO1O_dataout <= n11O0iOl AND NOT(niOl00ill); + wire_n101iOi_dataout <= nlOi11il WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(71); + wire_n101iOii_dataout <= n11O0l1O AND NOT(niOl00ill); + wire_n101iOil_dataout <= n11O0l0i AND NOT(niOl00ill); + wire_n101iOiO_dataout <= n11O0l0l AND NOT(niOl00ill); + wire_n101iOl_dataout <= nlOi11iO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(72); + wire_n101iOli_dataout <= n11O0l0O AND NOT(niOl00ill); + wire_n101iOll_dataout <= n11O0lii AND NOT(niOl00ill); + wire_n101iOlO_dataout <= n11O0lil AND NOT(niOl00ill); + wire_n101iOO_dataout <= nlOi11li WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(73); + wire_n101iOOi_dataout <= n11O0liO AND NOT(niOl00ill); + wire_n101iOOl_dataout <= n11O0lli AND NOT(niOl00ill); + wire_n101iOOO_dataout <= n11O0lll AND NOT(niOl00ill); + wire_n101l00i_dataout <= n11O0iOi OR niOl00ilO; + wire_n101l01O_dataout <= n11O0ilO AND NOT(niOl00ilO); + wire_n101l0i_dataout <= nlOi11Ol WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(77); + wire_n101l0il_dataout <= n11O0iOl AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101l0iO_dataout <= n11O0iOO OR wire_niO01ill_w_lg_nlOlOiliO21217w(0); + wire_n101l0l_dataout <= nlOi11OO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(78); + wire_n101l0li_dataout <= n11O0l1i AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101l0ll_dataout <= n11O0l1l AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101l0lO_dataout <= n11O0l1O AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101l0O_dataout <= nlOi101i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(79); + wire_n101l0Oi_dataout <= n11O0l0i AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101l0Ol_dataout <= n11O0l0l AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101l0OO_dataout <= n11O0l0O AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101l10i_dataout <= n11O0lOO AND NOT(niOl00ill); + wire_n101l10l_dataout <= n11O0O1i AND NOT(niOl00ill); + wire_n101l10O_dataout <= n11O0O1l AND NOT(niOl00ill); + wire_n101l11i_dataout <= n11O0llO OR niOl00ill; + wire_n101l11l_dataout <= n11O0lOi AND NOT(niOl00ill); + wire_n101l11O_dataout <= n11O0lOl AND NOT(niOl00ill); + wire_n101l1i_dataout <= nlOi11ll WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(74); + wire_n101l1ii_dataout <= n11O0O1O AND NOT(niOl00ill); + wire_n101l1il_dataout <= n11O0O0i AND NOT(niOl00ill); + wire_n101l1iO_dataout <= n11O0O0l AND NOT(niOl00ill); + wire_n101l1l_dataout <= nlOi11lO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(75); + wire_n101l1li_dataout <= n11O0O0O AND NOT(niOl00ill); + wire_n101l1ll_dataout <= n11O0Oii AND NOT(niOl00ill); + wire_n101l1lO_dataout <= n11O0Oil AND NOT(niOl00ill); + wire_n101l1O_dataout <= nlOi11Oi WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(76); + wire_n101l1Oi_dataout <= n11li1iO WHEN niOl00ill = '1' ELSE n11O0iiO; + wire_n101l1Ol_dataout <= n11li1li WHEN niOl00ill = '1' ELSE n11O0ili; + wire_n101l1OO_dataout <= n11O0ill AND NOT(niOl00ill); + wire_n101li0i_dataout <= n11O0lli AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101li0l_dataout <= n11O0lll AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101li0O_dataout <= n11O0llO AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101li1i_dataout <= n11O0lii AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101li1l_dataout <= n11O0lil AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101li1O_dataout <= n11O0liO AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101lii_dataout <= nlOi101l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(80); + wire_n101liii_dataout <= n11O0lOi AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101liil_dataout <= n11O0lOl AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101liiO_dataout <= n11O0lOO AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101lil_dataout <= nlOi101O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(81); + wire_n101lili_dataout <= n11O0O1i AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101lill_dataout <= n11O0O1l AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101lilO_dataout <= n11O0O1O AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101liO_dataout <= nlOi100i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(82); + wire_n101liOi_dataout <= n11O0O0i AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101liOl_dataout <= n11O0O0l AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101liOO_dataout <= n11O0O0O AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101ll0i_dataout <= wire_n101OilO_dataout WHEN n1110Oii = '1' ELSE wire_n101lOOl_dataout; + wire_n101ll0l_dataout <= wire_n101OiOi_dataout WHEN n1110Oii = '1' ELSE wire_n101lOOO_dataout; + wire_n101ll0O_dataout <= wire_n101OiOl_dataout WHEN n1110Oii = '1' ELSE wire_n101O11i_dataout; + wire_n101ll1i_dataout <= n11O0Oii AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101ll1l_dataout <= n11O0Oil AND NOT(wire_niO01ill_w_lg_nlOlOiliO21217w(0)); + wire_n101ll1O_dataout <= n11O0Oil OR n1iO0l0O; + wire_n101lli_dataout <= nlOi100l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(83); + wire_n101llii_dataout <= wire_n101OiOO_dataout WHEN n1110Oii = '1' ELSE wire_n101O11l_dataout; + wire_n101llil_dataout <= wire_n101Ol1i_dataout WHEN n1110Oii = '1' ELSE wire_n101O11O_dataout; + wire_n101lliO_dataout <= wire_n101Ol1l_dataout WHEN n1110Oii = '1' ELSE wire_n101O10i_dataout; + wire_n101lll_dataout <= nlOi100O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(84); + wire_n101llli_dataout <= wire_n101Ol1O_dataout WHEN n1110Oii = '1' ELSE wire_n101O10l_dataout; + wire_n101llll_dataout <= wire_n101Ol0i_dataout WHEN n1110Oii = '1' ELSE wire_n101O10O_dataout; + wire_n101lllO_dataout <= wire_n101Ol0l_dataout WHEN n1110Oii = '1' ELSE wire_n101O1ii_dataout; + wire_n101llO_dataout <= nlOi10ii WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(85); + wire_n101llOi_dataout <= wire_n101Ol0O_dataout WHEN n1110Oii = '1' ELSE wire_n101O1il_dataout; + wire_n101llOl_dataout <= wire_n101Olii_dataout WHEN n1110Oii = '1' ELSE wire_n101O1iO_dataout; + wire_n101llOO_dataout <= wire_n101Olil_dataout WHEN n1110Oii = '1' ELSE wire_n101O1li_dataout; + wire_n101lO0i_dataout <= wire_n101OllO_dataout WHEN n1110Oii = '1' ELSE wire_n101O1Ol_dataout; + wire_n101lO0l_dataout <= wire_n101OlOi_dataout WHEN n1110Oii = '1' ELSE wire_n101O1OO_dataout; + wire_n101lO0O_dataout <= wire_n101OlOl_dataout WHEN n1110Oii = '1' ELSE wire_n101O01i_dataout; + wire_n101lO1i_dataout <= wire_n101OliO_dataout WHEN n1110Oii = '1' ELSE wire_n101O1ll_dataout; + wire_n101lO1l_dataout <= wire_n101Olli_dataout WHEN n1110Oii = '1' ELSE wire_n101O1lO_dataout; + wire_n101lO1O_dataout <= wire_n101Olll_dataout WHEN n1110Oii = '1' ELSE wire_n101O1Oi_dataout; + wire_n101lOi_dataout <= nlOi10il WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(86); + wire_n101lOii_dataout <= wire_n101OlOO_dataout WHEN n1110Oii = '1' ELSE wire_n101O01l_dataout; + wire_n101lOil_dataout <= wire_n101OO1i_dataout WHEN n1110Oii = '1' ELSE wire_n101O01O_dataout; + wire_n101lOiO_dataout <= wire_n101OO1l_dataout WHEN n1110Oii = '1' ELSE wire_n101O00i_dataout; + wire_n101lOl_dataout <= nlOi10iO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(87); + wire_n101lOli_dataout <= wire_n101OO1O_dataout WHEN n1110Oii = '1' ELSE wire_n101O00l_dataout; + wire_n101lOll_dataout <= wire_n101OO0i_dataout WHEN n1110Oii = '1' ELSE wire_n101O00O_dataout; + wire_n101lOlO_dataout <= wire_n101OO0l_dataout WHEN n1110Oii = '1' ELSE wire_n101O0ii_dataout; + wire_n101lOO_dataout <= nlOi10li WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(88); + wire_n101lOOi_dataout <= wire_n101OO0O_dataout WHEN n1110Oii = '1' ELSE wire_n101O0il_dataout; + wire_n101lOOl_dataout <= n11O0iOl AND NOT(niOl00iOi); + wire_n101lOOO_dataout <= n11O0iOO AND NOT(niOl00iOi); + wire_n101O00i_dataout <= n11O0O0i AND NOT(niOl00iOi); + wire_n101O00l_dataout <= n11O0O0l AND NOT(niOl00iOi); + wire_n101O00O_dataout <= n11O0O0O AND NOT(niOl00iOi); + wire_n101O01i_dataout <= n11O0O1i AND NOT(niOl00iOi); + wire_n101O01l_dataout <= n11O0O1l AND NOT(niOl00iOi); + wire_n101O01O_dataout <= n11O0O1O AND NOT(niOl00iOi); + wire_n101O0i_dataout <= nlOi10Ol WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(92); + wire_n101O0ii_dataout <= n11O0Oii AND NOT(niOl00iOi); + wire_n101O0il_dataout <= n11O0Oil AND NOT(niOl00iOi); + wire_n101O0l_dataout <= nlOi10OO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(93); + wire_n101O0O_dataout <= nlOi1i1i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(94); + wire_n101O10i_dataout <= n11O0l0i OR niOl00iOi; + wire_n101O10l_dataout <= n11O0l0l AND NOT(niOl00iOi); + wire_n101O10O_dataout <= n11O0l0O AND NOT(niOl00iOi); + wire_n101O11i_dataout <= n11O0l1i AND NOT(niOl00iOi); + wire_n101O11l_dataout <= n11O0l1l AND NOT(niOl00iOi); + wire_n101O11O_dataout <= n11O0l1O AND NOT(niOl00iOi); + wire_n101O1i_dataout <= nlOi10ll WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(89); + wire_n101O1ii_dataout <= n11O0lii AND NOT(niOl00iOi); + wire_n101O1il_dataout <= n11O0lil AND NOT(niOl00iOi); + wire_n101O1iO_dataout <= n11O0liO AND NOT(niOl00iOi); + wire_n101O1l_dataout <= nlOi10lO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(90); + wire_n101O1li_dataout <= n11O0lli AND NOT(niOl00iOi); + wire_n101O1ll_dataout <= n11O0lll AND NOT(niOl00iOi); + wire_n101O1lO_dataout <= n11O0llO AND NOT(niOl00iOi); + wire_n101O1O_dataout <= nlOi10Oi WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(91); + wire_n101O1Oi_dataout <= n11O0lOi AND NOT(niOl00iOi); + wire_n101O1Ol_dataout <= n11O0lOl AND NOT(niOl00iOi); + wire_n101O1OO_dataout <= n11O0lOO AND NOT(niOl00iOi); + wire_n101Oii_dataout <= nlOi1i1l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(95); + wire_n101Oil_dataout <= nlOi1i1O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(96); + wire_n101OilO_dataout <= n11O0iOl AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OiO_dataout <= nlOi1i0i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(97); + wire_n101OiOi_dataout <= n11O0iOO AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OiOl_dataout <= n11O0l1i AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OiOO_dataout <= n11O0l1l AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Ol0i_dataout <= n11O0l0O AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Ol0l_dataout <= n11O0lii AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Ol0O_dataout <= n11O0lil AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Ol1i_dataout <= n11O0l1O AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Ol1l_dataout <= n11O0l0i OR wire_n1l10lli_w_lg_dataout21212w(0); + wire_n101Ol1O_dataout <= n11O0l0l AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Oli_dataout <= nlOi1i0l WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(98); + wire_n101Olii_dataout <= n11O0liO AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Olil_dataout <= n11O0lli AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OliO_dataout <= n11O0lll AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Oll_dataout <= nlOi1i0O WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(99); + wire_n101Olli_dataout <= n11O0llO AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101Olll_dataout <= n11O0lOi AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OllO_dataout <= n11O0lOl AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OlO_dataout <= nlOi1iii WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(100); + wire_n101OlOi_dataout <= n11O0lOO AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OlOl_dataout <= n11O0O1i AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OlOO_dataout <= n11O0O1l AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OO0i_dataout <= n11O0O0O AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OO0l_dataout <= n11O0Oii AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OO0O_dataout <= n11O0Oil AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OO1i_dataout <= n11O0O1O AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OO1l_dataout <= n11O0O0i AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OO1O_dataout <= n11O0O0l AND NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n101OOi_dataout <= nlOi1iil WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(101); + wire_n101OOii_dataout <= wire_n100100i_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1lO0l_dataout; + wire_n101OOil_dataout <= wire_n100100l_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1liii_dataout; + wire_n101OOiO_dataout <= wire_n100100O_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1liil_dataout; + wire_n101OOl_dataout <= nlOi1iiO WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(102); + wire_n101OOli_dataout <= wire_n10010ii_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1liiO_dataout; + wire_n101OOll_dataout <= wire_n10010il_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1lili_dataout; + wire_n101OOlO_dataout <= wire_n10010iO_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1lill_dataout; + wire_n101OOO_dataout <= nlOi1ili WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(103); + wire_n101OOOi_dataout <= wire_n10010li_dataout WHEN niOl00l0i = '1' ELSE wire_n100101O_dataout; + wire_n101OOOl_dataout <= wire_n10010ll_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1liOi_dataout; + wire_n101OOOO_dataout <= wire_n10010lO_dataout WHEN niOl00l0i = '1' ELSE wire_n1i1liOl_dataout; + wire_n10i000i_dataout <= wire_n10i00il_dataout WHEN niOl00OlO = '1' ELSE n11O00il; + wire_n10i000l_dataout <= wire_n10i00iO_dataout WHEN niOl00OlO = '1' ELSE n11O00ii; + wire_n10i000O_dataout <= n11O0ilO AND NOT(niOl0l1li); + wire_n10i001i_dataout <= wire_n1i0llil_dataout AND NOT(niOl00OlO); + wire_n10i001l_dataout <= wire_n1i0lliO_dataout AND NOT(niOl00OlO); + wire_n10i001O_dataout <= n11O0ill WHEN niOl00OlO = '1' ELSE wire_n10i000O_dataout; + wire_n10i00i_dataout <= wire_n10OOil_dataout WHEN k_hip(0) = '1' ELSE wire_n10lOOO_dataout; + wire_n10i00ii_dataout <= n11O0i0O OR n11l0OiO; + wire_n10i00il_dataout <= wire_n10i00ll_dataout WHEN n11O0ill = '1' ELSE wire_n10i00li_dataout; + wire_n10i00iO_dataout <= wire_n10i00lO_dataout WHEN n11O0ill = '1' ELSE n11O00ii; + wire_n10i00l_dataout <= wire_n10OOiO_dataout WHEN k_hip(0) = '1' ELSE wire_n10O11i_dataout; + wire_n10i00li_dataout <= n11O00il OR NOT(niOO10lOO); + wire_n10i00ll_dataout <= n11O00il WHEN niOl00Oli = '1' ELSE wire_n10i00li_dataout; + wire_n10i00lO_dataout <= n11O00ii OR niOl00Oli; + wire_n10i00O_dataout <= wire_n10OOli_dataout WHEN k_hip(0) = '1' ELSE wire_n10O11l_dataout; + wire_n10i010i_dataout <= wire_n1i0lill_dataout AND NOT(niOl00OlO); + wire_n10i010l_dataout <= wire_n1i0lilO_dataout AND NOT(niOl00OlO); + wire_n10i010O_dataout <= wire_n1i0liOi_dataout OR niOl00OlO; + wire_n10i011i_dataout <= wire_n1i0liil_dataout AND NOT(niOl00OlO); + wire_n10i011l_dataout <= wire_n1i0liiO_dataout AND NOT(niOl00OlO); + wire_n10i011O_dataout <= wire_n1i0lili_dataout AND NOT(niOl00OlO); + wire_n10i01i_dataout <= nlOiiiOl WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(95); + wire_n10i01ii_dataout <= wire_n1i0liOl_dataout AND NOT(niOl00OlO); + wire_n10i01il_dataout <= wire_n1i0liOO_dataout AND NOT(niOl00OlO); + wire_n10i01iO_dataout <= wire_n1i0ll1i_dataout AND NOT(niOl00OlO); + wire_n10i01l_dataout <= wire_n10OO0O_dataout WHEN k_hip(0) = '1' ELSE wire_n10lOOi_dataout; + wire_n10i01li_dataout <= wire_n1i0ll1l_dataout AND NOT(niOl00OlO); + wire_n10i01ll_dataout <= wire_n1i0ll1O_dataout AND NOT(niOl00OlO); + wire_n10i01lO_dataout <= wire_n1i0ll0i_dataout AND NOT(niOl00OlO); + wire_n10i01O_dataout <= wire_n10OOii_dataout WHEN k_hip(0) = '1' ELSE wire_n10lOOl_dataout; + wire_n10i01Oi_dataout <= wire_n1i0ll0l_dataout AND NOT(niOl00OlO); + wire_n10i01Ol_dataout <= wire_n1i0ll0O_dataout AND NOT(niOl00OlO); + wire_n10i01OO_dataout <= wire_n1i0llii_dataout AND NOT(niOl00OlO); + wire_n10i0ii_dataout <= wire_n10OOll_dataout WHEN k_hip(0) = '1' ELSE wire_n10O11O_dataout; + wire_n10i0iiO_dataout <= wire_n10iO11i_dataout WHEN niOl0i01i = '1' ELSE wire_n10ii1ii_dataout; + wire_n10i0il_dataout <= wire_n10OOlO_dataout WHEN k_hip(0) = '1' ELSE wire_n10O10i_dataout; + wire_n10i0ili_dataout <= n11O00iO WHEN niOl0i01i = '1' ELSE wire_n10ii1il_dataout; + wire_n10i0ill_dataout <= n11O0i0O WHEN niOl0i01i = '1' ELSE wire_n10ii1iO_dataout; + wire_n10i0ilO_dataout <= n11O0iOi WHEN niOl0i01i = '1' ELSE wire_n10iii0l_dataout; + wire_n10i0iO_dataout <= wire_n10OOOi_dataout WHEN k_hip(0) = '1' ELSE wire_n10O10l_dataout; + wire_n10i0iOi_dataout <= n11O0ilO WHEN niOl0i01i = '1' ELSE wire_n10iii0O_dataout; + wire_n10i0iOl_dataout <= wire_n10ii1li_dataout AND NOT(niOl0i01i); + wire_n10i0iOO_dataout <= wire_n10ii1ll_dataout AND NOT(niOl0i01i); + wire_n10i0l0i_dataout <= wire_n10ii1OO_dataout AND NOT(niOl0i01i); + wire_n10i0l0l_dataout <= wire_n10ii01i_dataout AND NOT(niOl0i01i); + wire_n10i0l0O_dataout <= wire_n10ii01l_dataout AND NOT(niOl0i01i); + wire_n10i0l1i_dataout <= wire_n10ii1lO_dataout AND NOT(niOl0i01i); + wire_n10i0l1l_dataout <= wire_n10ii1Oi_dataout AND NOT(niOl0i01i); + wire_n10i0l1O_dataout <= wire_n10ii1Ol_dataout AND NOT(niOl0i01i); + wire_n10i0li_dataout <= wire_n10OOOl_dataout WHEN k_hip(0) = '1' ELSE wire_n10O10O_dataout; + wire_n10i0lii_dataout <= wire_n10ii01O_dataout AND NOT(niOl0i01i); + wire_n10i0lil_dataout <= wire_n10ii00i_dataout AND NOT(niOl0i01i); + wire_n10i0liO_dataout <= wire_n10ii00l_dataout AND NOT(niOl0i01i); + wire_n10i0ll_dataout <= wire_n10OOOO_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1ii_dataout; + wire_n10i0lli_dataout <= wire_n10ii00O_dataout OR niOl0i01i; + wire_n10i0lll_dataout <= wire_n10ii0ii_dataout AND NOT(niOl0i01i); + wire_n10i0llO_dataout <= wire_n10ii0il_dataout AND NOT(niOl0i01i); + wire_n10i0lO_dataout <= wire_n1i111i_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1il_dataout; + wire_n10i0lOi_dataout <= wire_n10ii0iO_dataout AND NOT(niOl0i01i); + wire_n10i0lOl_dataout <= wire_n10ii0li_dataout AND NOT(niOl0i01i); + wire_n10i0lOO_dataout <= wire_n10ii0ll_dataout AND NOT(niOl0i01i); + wire_n10i0O0i_dataout <= wire_n10ii0OO_dataout AND NOT(niOl0i01i); + wire_n10i0O0l_dataout <= wire_n10iii1i_dataout AND NOT(niOl0i01i); + wire_n10i0O0O_dataout <= wire_n10iii1l_dataout AND NOT(niOl0i01i); + wire_n10i0O1i_dataout <= wire_n10ii0lO_dataout AND NOT(niOl0i01i); + wire_n10i0O1l_dataout <= wire_n10ii0Oi_dataout AND NOT(niOl0i01i); + wire_n10i0O1O_dataout <= wire_n10ii0Ol_dataout AND NOT(niOl0i01i); + wire_n10i0Oi_dataout <= wire_n1i111l_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1iO_dataout; + wire_n10i0Oii_dataout <= wire_n10iii1O_dataout AND NOT(niOl0i01i); + wire_n10i0Oil_dataout <= wire_n10iii0i_dataout AND NOT(niOl0i01i); + wire_n10i0OiO_dataout <= n1Oi101O WHEN niOl0i01i = '1' ELSE n11O01Ol; + wire_n10i0Ol_dataout <= wire_n1i111O_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1li_dataout; + wire_n10i0Oli_dataout <= n011iOii WHEN niOl0i01i = '1' ELSE n11O01OO; + wire_n10i0Oll_dataout <= n01O1ill WHEN niOl0i01i = '1' ELSE n11O001i; + wire_n10i0OlO_dataout <= n00il1OO WHEN niOl0i01i = '1' ELSE n11O001l; + wire_n10i0OO_dataout <= wire_n1i110i_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1ll_dataout; + wire_n10i0OOi_dataout <= n0i01O0i WHEN niOl0i01i = '1' ELSE n11O001O; + wire_n10i0OOl_dataout <= n0iOliil WHEN niOl0i01i = '1' ELSE n11O000i; + wire_n10i0OOO_dataout <= n0ll01lO WHEN niOl0i01i = '1' ELSE n11O000l; + wire_n10i10i_dataout <= nlOiii1l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(83); + wire_n10i10l_dataout <= nlOiii1O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(84); + wire_n10i10O_dataout <= nlOiii0i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(85); + wire_n10i110i_dataout <= n11O0O1O AND NOT(niOl0iO0i); + wire_n10i110l_dataout <= n11O0O0i AND NOT(niOl0iO0i); + wire_n10i110O_dataout <= n11O0O0l AND NOT(niOl0iO0i); + wire_n10i111i_dataout <= n11O0lOO AND NOT(niOl0iO0i); + wire_n10i111l_dataout <= n11O0O1i AND NOT(niOl0iO0i); + wire_n10i111O_dataout <= n11O0O1l AND NOT(niOl0iO0i); + wire_n10i11i_dataout <= nlOii0Ol WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(80); + wire_n10i11ii_dataout <= n11O0O0O AND NOT(niOl0iO0i); + wire_n10i11il_dataout <= n11O0Oii AND NOT(niOl0iO0i); + wire_n10i11iO_dataout <= n11O0i0l WHEN niOl0iO0i = '1' ELSE n11O0Oil; + wire_n10i11l_dataout <= nlOii0OO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(81); + wire_n10i11li_dataout <= wire_n10i11lO_dataout WHEN niOl0iO0i = '1' ELSE n11O0i0O; + wire_n10i11ll_dataout <= n11O0i0l OR niOl0iO0i; + wire_n10i11lO_dataout <= wire_n10lii1i_dataout WHEN wire_niO01iOi_w_lg_n11O0i0l21009w(0) = '1' ELSE n11O0i0O; + wire_n10i11O_dataout <= nlOiii1i WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(82); + wire_n10i11Ol_dataout <= n11O00il OR (wire_w_lg_niOO10lOO8902w(0) AND (wire_nlOi00l1O_dataout XOR nlOOOl00i)); + wire_n10i1ii_dataout <= nlOiii0l WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(86); + wire_n10i1il_dataout <= nlOiii0O WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(87); + wire_n10i1iO_dataout <= nlOiiiii WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(88); + wire_n10i1li_dataout <= nlOiiiil WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(89); + wire_n10i1ll_dataout <= nlOiiiiO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(90); + wire_n10i1lO_dataout <= nlOiiili WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(91); + wire_n10i1O0O_dataout <= n11O0ill AND NOT(niOl00OlO); + wire_n10i1Oi_dataout <= nlOiiill WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(92); + wire_n10i1Oii_dataout <= wire_n10i00ii_dataout WHEN niOl00OlO = '1' ELSE n11O0i0O; + wire_n10i1Oil_dataout <= wire_n1i0l0OO_dataout AND NOT(niOl00OlO); + wire_n10i1OiO_dataout <= wire_n1i0li1i_dataout AND NOT(niOl00OlO); + wire_n10i1Ol_dataout <= nlOiiilO WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(93); + wire_n10i1Oli_dataout <= wire_n1i0li1l_dataout AND NOT(niOl00OlO); + wire_n10i1Oll_dataout <= wire_n1i0li1O_dataout AND NOT(niOl00OlO); + wire_n10i1OlO_dataout <= wire_n1i0li0i_dataout AND NOT(niOl00OlO); + wire_n10i1OO_dataout <= nlOiiiOi WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(94); + wire_n10i1OOi_dataout <= wire_n1i0li0l_dataout AND NOT(niOl00OlO); + wire_n10i1OOl_dataout <= wire_n1i0li0O_dataout AND NOT(niOl00OlO); + wire_n10i1OOO_dataout <= wire_n1i0liii_dataout AND NOT(niOl00OlO); + wire_n10ii00i_dataout <= wire_n10iil1O_dataout AND NOT(niOl0i10O); + wire_n10ii00l_dataout <= wire_n10iil0i_dataout OR niOl0i10O; + wire_n10ii00O_dataout <= wire_n10iil0l_dataout AND NOT(niOl0i10O); + wire_n10ii01i_dataout <= wire_n10iiiOO_dataout AND NOT(niOl0i10O); + wire_n10ii01l_dataout <= wire_n10iil1i_dataout AND NOT(niOl0i10O); + wire_n10ii01O_dataout <= wire_n10iil1l_dataout AND NOT(niOl0i10O); + wire_n10ii0i_dataout <= wire_n1i11il_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1OO_dataout; + wire_n10ii0ii_dataout <= wire_n10iil0O_dataout AND NOT(niOl0i10O); + wire_n10ii0il_dataout <= wire_n10iilii_dataout AND NOT(niOl0i10O); + wire_n10ii0iO_dataout <= wire_n10iilil_dataout AND NOT(niOl0i10O); + wire_n10ii0l_dataout <= wire_n1i11iO_dataout WHEN k_hip(0) = '1' ELSE wire_n10O01i_dataout; + wire_n10ii0li_dataout <= wire_n10iiliO_dataout AND NOT(niOl0i10O); + wire_n10ii0ll_dataout <= wire_n10iilli_dataout AND NOT(niOl0i10O); + wire_n10ii0lO_dataout <= wire_n10iilll_dataout AND NOT(niOl0i10O); + wire_n10ii0O_dataout <= wire_n1i11li_dataout WHEN k_hip(0) = '1' ELSE wire_n10O01l_dataout; + wire_n10ii0Oi_dataout <= wire_n10iillO_dataout AND NOT(niOl0i10O); + wire_n10ii0Ol_dataout <= wire_n10iilOi_dataout AND NOT(niOl0i10O); + wire_n10ii0OO_dataout <= wire_n10iilOl_dataout AND NOT(niOl0i10O); + wire_n10ii10i_dataout <= n11O0ill OR niOl0i01i; + wire_n10ii10l_dataout <= n11O0iii WHEN niOl0i10O = '1' ELSE wire_n10iiiii_dataout; + wire_n10ii10O_dataout <= n11O0iil WHEN niOl0i10O = '1' ELSE wire_n10iiiil_dataout; + wire_n10ii11i_dataout <= n0O0lO1i WHEN niOl0i01i = '1' ELSE n11O000O; + wire_n10ii11l_dataout <= wire_w_lg_niOl0i1ii21161w(0) WHEN niOl0i01i = '1' ELSE wire_n10ii10l_dataout; + wire_n10ii11O_dataout <= niOl0i1ii WHEN niOl0i01i = '1' ELSE wire_n10ii10O_dataout; + wire_n10ii1i_dataout <= wire_n1i110l_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1lO_dataout; + wire_n10ii1ii_dataout <= wire_n10iO11i_dataout WHEN niOl0i10O = '1' ELSE wire_n10iiO0l_dataout; + wire_n10ii1il_dataout <= n11O00iO WHEN niOl0i10O = '1' ELSE wire_n10iiO0O_dataout; + wire_n10ii1iO_dataout <= n11O0i0O WHEN niOl0i10O = '1' ELSE wire_n10iiOii_dataout; + wire_n10ii1l_dataout <= wire_n1i110O_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1Oi_dataout; + wire_n10ii1li_dataout <= wire_n10iiiiO_dataout AND NOT(niOl0i10O); + wire_n10ii1ll_dataout <= wire_n10iiili_dataout AND NOT(niOl0i10O); + wire_n10ii1lO_dataout <= wire_n10iiill_dataout AND NOT(niOl0i10O); + wire_n10ii1O_dataout <= wire_n1i11ii_dataout WHEN k_hip(0) = '1' ELSE wire_n10O1Ol_dataout; + wire_n10ii1Oi_dataout <= wire_n10iiilO_dataout AND NOT(niOl0i10O); + wire_n10ii1Ol_dataout <= wire_n10iiiOi_dataout AND NOT(niOl0i10O); + wire_n10ii1OO_dataout <= wire_n10iiiOl_dataout AND NOT(niOl0i10O); + wire_n10iii0i_dataout <= wire_n10iiO1O_dataout AND NOT(niOl0i10O); + wire_n10iii0l_dataout <= wire_n10iiO0i_dataout AND NOT(niOl0i10O); + wire_n10iii0O_dataout <= wire_n10iiOil_dataout AND NOT(niOl0i10O); + wire_n10iii1i_dataout <= wire_n10iilOO_dataout AND NOT(niOl0i10O); + wire_n10iii1l_dataout <= wire_n10iiO1i_dataout AND NOT(niOl0i10O); + wire_n10iii1O_dataout <= wire_n10iiO1l_dataout AND NOT(niOl0i10O); + wire_n10iiii_dataout <= wire_n1i11ll_dataout WHEN k_hip(0) = '1' ELSE wire_n10O01O_dataout; + wire_n10iiiii_dataout <= n11O0iii WHEN niOl0i10i = '1' ELSE wire_n10il00i_dataout; + wire_n10iiiil_dataout <= n11O0iil WHEN niOl0i10i = '1' ELSE wire_n10il00l_dataout; + wire_n10iiiiO_dataout <= wire_n10iiOiO_dataout AND NOT(niOl0i10i); + wire_n10iiil_dataout <= wire_n1i11lO_dataout WHEN k_hip(0) = '1' ELSE wire_n10O00i_dataout; + wire_n10iiili_dataout <= wire_n10iiOli_dataout AND NOT(niOl0i10i); + wire_n10iiill_dataout <= wire_n10iiOll_dataout AND NOT(niOl0i10i); + wire_n10iiilO_dataout <= wire_n10iiOlO_dataout AND NOT(niOl0i10i); + wire_n10iiiO_dataout <= wire_n1i11Oi_dataout WHEN k_hip(0) = '1' ELSE wire_n10O00l_dataout; + wire_n10iiiOi_dataout <= wire_n10iiOOi_dataout AND NOT(niOl0i10i); + wire_n10iiiOl_dataout <= wire_n10iiOOl_dataout AND NOT(niOl0i10i); + wire_n10iiiOO_dataout <= wire_n10iiOOO_dataout AND NOT(niOl0i10i); + wire_n10iil0i_dataout <= wire_n10il10i_dataout AND NOT(niOl0i10i); + wire_n10iil0l_dataout <= wire_n10il10l_dataout AND NOT(niOl0i10i); + wire_n10iil0O_dataout <= wire_n10il10O_dataout AND NOT(niOl0i10i); + wire_n10iil1i_dataout <= wire_n10il11i_dataout AND NOT(niOl0i10i); + wire_n10iil1l_dataout <= wire_n10il11l_dataout AND NOT(niOl0i10i); + wire_n10iil1O_dataout <= wire_n10il11O_dataout AND NOT(niOl0i10i); + wire_n10iili_dataout <= wire_n1i11Ol_dataout WHEN k_hip(0) = '1' ELSE wire_n10O00O_dataout; + wire_n10iilii_dataout <= wire_n10il1ii_dataout AND NOT(niOl0i10i); + wire_n10iilil_dataout <= wire_n10il1il_dataout AND NOT(niOl0i10i); + wire_n10iiliO_dataout <= wire_n10il1iO_dataout AND NOT(niOl0i10i); + wire_n10iill_dataout <= wire_n1i11OO_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0ii_dataout; + wire_n10iilli_dataout <= wire_n10il1li_dataout AND NOT(niOl0i10i); + wire_n10iilll_dataout <= wire_n10il1ll_dataout AND NOT(niOl0i10i); + wire_n10iillO_dataout <= wire_n10il1lO_dataout AND NOT(niOl0i10i); + wire_n10iilO_dataout <= wire_n1i101i_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0il_dataout; + wire_n10iilOi_dataout <= wire_n10il1Oi_dataout OR niOl0i10i; + wire_n10iilOl_dataout <= wire_n10il1Ol_dataout AND NOT(niOl0i10i); + wire_n10iilOO_dataout <= wire_n10il1OO_dataout AND NOT(niOl0i10i); + wire_n10iiO0i_dataout <= n11O0iOi AND NOT(niOl0i10i); + wire_n10iiO0l_dataout <= n11O00ii WHEN niOl0i10i = '1' ELSE wire_n10iO11i_dataout; + wire_n10iiO0O_dataout <= n11O00iO OR niOl0i10i; + wire_n10iiO1i_dataout <= wire_n10il01i_dataout AND NOT(niOl0i10i); + wire_n10iiO1l_dataout <= wire_n10il01l_dataout AND NOT(niOl0i10i); + wire_n10iiO1O_dataout <= wire_n10il01O_dataout AND NOT(niOl0i10i); + wire_n10iiOi_dataout <= wire_n1i101l_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0iO_dataout; + wire_n10iiOii_dataout <= wire_n10lii1i_dataout WHEN niOl0i10i = '1' ELSE n11O0i0O; + wire_n10iiOil_dataout <= n11O0ilO AND NOT(niOl0i10i); + wire_n10iiOiO_dataout <= wire_n10il00O_dataout AND NOT(niOl0i11i); + wire_n10iiOl_dataout <= wire_n1i101O_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0li_dataout; + wire_n10iiOli_dataout <= wire_n10il0ii_dataout AND NOT(niOl0i11i); + wire_n10iiOll_dataout <= wire_n10il0il_dataout AND NOT(niOl0i11i); + wire_n10iiOlO_dataout <= wire_n10il0iO_dataout AND NOT(niOl0i11i); + wire_n10iiOO_dataout <= wire_n1i100i_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0ll_dataout; + wire_n10iiOOi_dataout <= wire_n10il0li_dataout AND NOT(niOl0i11i); + wire_n10iiOOl_dataout <= wire_n10il0ll_dataout AND NOT(niOl0i11i); + wire_n10iiOOO_dataout <= wire_n10il0lO_dataout AND NOT(niOl0i11i); + wire_n10il00i_dataout <= n11O0iiO WHEN niOl0i11i = '1' ELSE wire_n10ill1i_dataout; + wire_n10il00l_dataout <= n11O0ili WHEN niOl0i11i = '1' ELSE wire_n10ill1l_dataout; + wire_n10il00O_dataout <= wire_n1i0l0OO_dataout AND NOT(niOl00OOO); + wire_n10il01i_dataout <= wire_n10iliOi_dataout AND NOT(niOl0i11i); + wire_n10il01l_dataout <= wire_n10iliOl_dataout AND NOT(niOl0i11i); + wire_n10il01O_dataout <= wire_n10iliOO_dataout AND NOT(niOl0i11i); + wire_n10il0i_dataout <= wire_n1i10il_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0OO_dataout; + wire_n10il0ii_dataout <= wire_n1i0li1i_dataout AND NOT(niOl00OOO); + wire_n10il0il_dataout <= wire_n1i0li1l_dataout AND NOT(niOl00OOO); + wire_n10il0iO_dataout <= wire_n1i0li1O_dataout AND NOT(niOl00OOO); + wire_n10il0l_dataout <= wire_n1i10iO_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oi1i_dataout; + wire_n10il0li_dataout <= wire_n1i0li0i_dataout AND NOT(niOl00OOO); + wire_n10il0ll_dataout <= wire_n1i0li0l_dataout AND NOT(niOl00OOO); + wire_n10il0lO_dataout <= wire_n1i0li0O_dataout AND NOT(niOl00OOO); + wire_n10il0O_dataout <= wire_n1i10li_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oi1l_dataout; + wire_n10il0Oi_dataout <= wire_n1i0liii_dataout AND NOT(niOl00OOO); + wire_n10il0Ol_dataout <= wire_n1i0liil_dataout AND NOT(niOl00OOO); + wire_n10il0OO_dataout <= wire_n1i0liiO_dataout AND NOT(niOl00OOO); + wire_n10il10i_dataout <= wire_n10ili1i_dataout AND NOT(niOl0i11i); + wire_n10il10l_dataout <= wire_n10ili1l_dataout OR niOl0i11i; + wire_n10il10O_dataout <= wire_n10ili1O_dataout AND NOT(niOl0i11i); + wire_n10il11i_dataout <= wire_n10il0Oi_dataout AND NOT(niOl0i11i); + wire_n10il11l_dataout <= wire_n10il0Ol_dataout AND NOT(niOl0i11i); + wire_n10il11O_dataout <= wire_n10il0OO_dataout AND NOT(niOl0i11i); + wire_n10il1i_dataout <= wire_n1i100l_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0lO_dataout; + wire_n10il1ii_dataout <= wire_n10ili0i_dataout AND NOT(niOl0i11i); + wire_n10il1il_dataout <= wire_n10ili0l_dataout AND NOT(niOl0i11i); + wire_n10il1iO_dataout <= wire_n10ili0O_dataout AND NOT(niOl0i11i); + wire_n10il1l_dataout <= wire_n1i100O_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0Oi_dataout; + wire_n10il1li_dataout <= wire_n10iliii_dataout AND NOT(niOl0i11i); + wire_n10il1ll_dataout <= wire_n10iliil_dataout AND NOT(niOl0i11i); + wire_n10il1lO_dataout <= wire_n10iliiO_dataout AND NOT(niOl0i11i); + wire_n10il1O_dataout <= wire_n1i10ii_dataout WHEN k_hip(0) = '1' ELSE wire_n10O0Ol_dataout; + wire_n10il1Oi_dataout <= wire_n10ilili_dataout AND NOT(niOl0i11i); + wire_n10il1Ol_dataout <= wire_n10ilill_dataout AND NOT(niOl0i11i); + wire_n10il1OO_dataout <= wire_n10ililO_dataout AND NOT(niOl0i11i); + wire_n10ili0i_dataout <= wire_n1i0liOi_dataout AND NOT(niOl00OOO); + wire_n10ili0l_dataout <= wire_n1i0liOl_dataout AND NOT(niOl00OOO); + wire_n10ili0O_dataout <= wire_n1i0liOO_dataout AND NOT(niOl00OOO); + wire_n10ili1i_dataout <= wire_n1i0lili_dataout AND NOT(niOl00OOO); + wire_n10ili1l_dataout <= wire_n1i0lill_dataout OR niOl00OOO; + wire_n10ili1O_dataout <= wire_n1i0lilO_dataout AND NOT(niOl00OOO); + wire_n10ilii_dataout <= wire_n1i10ll_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oi1O_dataout; + wire_n10iliii_dataout <= wire_n1i0ll1i_dataout AND NOT(niOl00OOO); + wire_n10iliil_dataout <= wire_n1i0ll1l_dataout AND NOT(niOl00OOO); + wire_n10iliiO_dataout <= wire_n1i0ll1O_dataout AND NOT(niOl00OOO); + wire_n10ilil_dataout <= wire_n1i10lO_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oi0i_dataout; + wire_n10ilili_dataout <= wire_n1i0ll0i_dataout AND NOT(niOl00OOO); + wire_n10ilill_dataout <= wire_n1i0ll0l_dataout AND NOT(niOl00OOO); + wire_n10ililO_dataout <= wire_n1i0ll0O_dataout AND NOT(niOl00OOO); + wire_n10iliO_dataout <= wire_n1i10Oi_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oi0l_dataout; + wire_n10iliOi_dataout <= wire_n1i0llii_dataout AND NOT(niOl00OOO); + wire_n10iliOl_dataout <= wire_n1i0llil_dataout AND NOT(niOl00OOO); + wire_n10iliOO_dataout <= wire_n1i0lliO_dataout AND NOT(niOl00OOO); + wire_n10ill1i_dataout <= n11O0iii OR niOl00OOO; + wire_n10ill1l_dataout <= n11O0iil AND NOT(niOl00OOO); + wire_n10illi_dataout <= wire_n1i10Ol_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oi0O_dataout; + wire_n10illl_dataout <= wire_n1i10OO_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oiii_dataout; + wire_n10illO_dataout <= wire_n1i1i1i_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oiil_dataout; + wire_n10ilOi_dataout <= wire_n1i1i1l_dataout WHEN k_hip(0) = '1' ELSE wire_n10OiiO_dataout; + wire_n10ilOl_dataout <= wire_n1i1i1O_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oili_dataout; + wire_n10ilOO_dataout <= wire_n1i1i0i_dataout WHEN k_hip(0) = '1' ELSE wire_n10Oill_dataout; + wire_n10iO00i_dataout <= wire_n1i1ll1i_dataout AND NOT(niOl0i00O); + wire_n10iO00l_dataout <= wire_n1i1ll1l_dataout AND NOT(niOl0i00O); + wire_n10iO00O_dataout <= wire_n10iOill_dataout AND NOT(niOl0i00O); + wire_n10iO01i_dataout <= wire_n1i1liOi_dataout AND NOT(niOl0i00O); + wire_n10iO01l_dataout <= wire_n1i1liOl_dataout AND NOT(niOl0i00O); + wire_n10iO01O_dataout <= wire_n1i1liOO_dataout AND NOT(niOl0i00O); + wire_n10iO0i_dataout <= wire_n1i1iil_dataout WHEN k_hip(0) = '1' ELSE wire_n10OiOO_dataout; + wire_n10iO0ii_dataout <= wire_n10iOilO_dataout OR niOl0i00O; + wire_n10iO0il_dataout <= wire_n1i1ll0l_dataout AND NOT(niOl0i00O); + wire_n10iO0iO_dataout <= wire_n1i1ll0O_dataout AND NOT(niOl0i00O); + wire_n10iO0l_dataout <= wire_n1i1iiO_dataout WHEN k_hip(0) = '1' ELSE wire_n10Ol1i_dataout; + wire_n10iO0li_dataout <= wire_n1i1llii_dataout AND NOT(niOl0i00O); + wire_n10iO0ll_dataout <= wire_n1i1llil_dataout AND NOT(niOl0i00O); + wire_n10iO0lO_dataout <= wire_n1i1lliO_dataout AND NOT(niOl0i00O); + wire_n10iO0O_dataout <= wire_n1i1ili_dataout WHEN k_hip(0) = '1' ELSE wire_n10Ol1l_dataout; + wire_n10iO0Oi_dataout <= wire_n1i1llli_dataout AND NOT(niOl0i00O); + wire_n10iO0Ol_dataout <= wire_n10iOiOi_dataout AND NOT(niOl0i00O); + wire_n10iO0OO_dataout <= wire_n1i1lllO_dataout AND NOT(niOl0i00O); + wire_n10iO10i_dataout <= wire_nlOi0iill_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE n11O0i0i; + wire_n10iO10l_dataout <= wire_n10l1l1l_dataout WHEN niOl0i00O = '1' ELSE wire_n10iOi0O_dataout; + wire_n10iO10O_dataout <= n11O00iO WHEN niOl0i00O = '1' ELSE wire_n10iOiii_dataout; + wire_n10iO11i_dataout <= wire_n10iO11O_dataout WHEN wire_niO01ill_w_lg_n11O0OiO21115w(0) = '1' ELSE n11O01li; + wire_n10iO11l_dataout <= wire_n10iO10i_dataout WHEN wire_niO01ill_w_lg_n11O0OiO21115w(0) = '1' ELSE n11O0i0i; + wire_n10iO11O_dataout <= k_conf(360) AND wire_w_lg_niOO10lOO8902w(0); + wire_n10iO1i_dataout <= wire_n1i1i0l_dataout WHEN k_hip(0) = '1' ELSE wire_n10OilO_dataout; + wire_n10iO1ii_dataout <= wire_n10iOiil_dataout AND NOT(niOl0i00O); + wire_n10iO1il_dataout <= n11O0iii WHEN niOl0i00O = '1' ELSE wire_n10iOiiO_dataout; + wire_n10iO1iO_dataout <= n11O0iil WHEN niOl0i00O = '1' ELSE wire_n10iOili_dataout; + wire_n10iO1l_dataout <= wire_n1i1i0O_dataout WHEN k_hip(0) = '1' ELSE wire_n10OiOi_dataout; + wire_n10iO1li_dataout <= wire_n1i1liii_dataout AND NOT(niOl0i00O); + wire_n10iO1ll_dataout <= wire_n1i1liil_dataout AND NOT(niOl0i00O); + wire_n10iO1lO_dataout <= wire_n1i1liiO_dataout AND NOT(niOl0i00O); + wire_n10iO1O_dataout <= wire_n1i1iii_dataout WHEN k_hip(0) = '1' ELSE wire_n10OiOl_dataout; + wire_n10iO1Oi_dataout <= wire_n1i1lili_dataout AND NOT(niOl0i00O); + wire_n10iO1Ol_dataout <= wire_n1i1lill_dataout AND NOT(niOl0i00O); + wire_n10iO1OO_dataout <= wire_n1i1lilO_dataout AND NOT(niOl0i00O); + wire_n10iOi0i_dataout <= wire_n10iOiOO_dataout AND NOT(niOl0i00O); + wire_n10iOi0l_dataout <= wire_n10l111l_dataout WHEN niOl0i00O = '1' ELSE wire_n10iOl1i_dataout; + wire_n10iOi0O_dataout <= wire_n10iOl1l_dataout WHEN n1iO0l0O = '1' ELSE wire_n10l1l1l_dataout; + wire_n10iOi1i_dataout <= wire_n1i1llOi_dataout AND NOT(niOl0i00O); + wire_n10iOi1l_dataout <= wire_n10iOiOl_dataout AND NOT(niOl0i00O); + wire_n10iOi1O_dataout <= wire_n1i1llOO_dataout AND NOT(niOl0i00O); + wire_n10iOii_dataout <= wire_n1i1ill_dataout WHEN k_hip(0) = '1' ELSE wire_n10Ol1O_dataout; + wire_n10iOiii_dataout <= wire_n10iOl1O_dataout WHEN n1iO0l0O = '1' ELSE n11O00iO; + wire_n10iOiil_dataout <= wire_n10iOl0i_dataout AND n1iO0l0O; + wire_n10iOiiO_dataout <= wire_n10iOl0l_dataout WHEN n1iO0l0O = '1' ELSE n11O0iii; + wire_n10iOil_dataout <= wire_n1i1ilO_dataout WHEN k_hip(0) = '1' ELSE wire_n10Ol0i_dataout; + wire_n10iOili_dataout <= wire_n10iOl0O_dataout WHEN n1iO0l0O = '1' ELSE n11O0iil; + wire_n10iOill_dataout <= wire_n10iOlii_dataout WHEN n1iO0l0O = '1' ELSE n11O0lli; + wire_n10iOilO_dataout <= niOl0i00l WHEN n1iO0l0O = '1' ELSE n11O0lll; + wire_n10iOiO_dataout <= wire_n1i1iOi_dataout WHEN k_hip(0) = '1' ELSE wire_n10Ol0l_dataout; + wire_n10iOiOi_dataout <= wire_n10iOlil_dataout WHEN n1iO0l0O = '1' ELSE n11O0O1O; + wire_n10iOiOl_dataout <= n11O0O0O AND NOT(n1iO0l0O); + wire_n10iOiOO_dataout <= wire_n10iOliO_dataout WHEN n1iO0l0O = '1' ELSE n11O0Oil; + wire_n10iOl0i_dataout <= wire_n10iOlOi_dataout AND NOT(niOl0i00l); + wire_n10iOl0l_dataout <= n11O0iii WHEN niOl0i00l = '1' ELSE wire_n10iOlOl_dataout; + wire_n10iOl0O_dataout <= n11O0iil WHEN niOl0i00l = '1' ELSE wire_n10iOlOO_dataout; + wire_n10iOl1i_dataout <= wire_n10iOlli_dataout WHEN n1iO0l0O = '1' ELSE n11O0i0i; + wire_n10iOl1l_dataout <= wire_n10l1l1l_dataout WHEN niOl0i00l = '1' ELSE wire_n10iOlll_dataout; + wire_n10iOl1O_dataout <= n11O00iO WHEN niOl0i00l = '1' ELSE wire_n10iOllO_dataout; + wire_n10iOli_dataout <= wire_n1i1iOl_dataout WHEN k_hip(0) = '1' ELSE wire_n10Ol0O_dataout; + wire_n10iOlii_dataout <= wire_n10iOO1i_dataout AND NOT(niOl0i00l); + wire_n10iOlil_dataout <= wire_n10iOO1l_dataout AND NOT(niOl0i00l); + wire_n10iOliO_dataout <= wire_n10iOO1O_dataout AND NOT(niOl0i00l); + wire_n10iOll_dataout <= wire_n1i1iOO_dataout WHEN k_hip(0) = '1' ELSE wire_n10Olii_dataout; + wire_n10iOlli_dataout <= wire_n10l111l_dataout WHEN niOl0i00l = '1' ELSE wire_n10iOO0i_dataout; + wire_n10iOlll_dataout <= wire_n10l1l1l_dataout WHEN niOl0i00i = '1' ELSE wire_n10iOO0l_dataout; + wire_n10iOllO_dataout <= n11O00iO WHEN niOl0i00i = '1' ELSE wire_n10iOO0O_dataout; + wire_n10iOlO_dataout <= wire_n1i1l1i_dataout WHEN k_hip(0) = '1' ELSE wire_n10Olil_dataout; + wire_n10iOlOi_dataout <= wire_n10iOOii_dataout AND NOT(niOl0i00i); + wire_n10iOlOl_dataout <= wire_n10iOOil_dataout OR niOl0i00i; + wire_n10iOlOO_dataout <= wire_n10iOOiO_dataout AND NOT(niOl0i00i); + wire_n10iOO0i_dataout <= wire_n10l111l_dataout WHEN niOl0i00i = '1' ELSE wire_n10iOOlO_dataout; + wire_n10iOO0l_dataout <= wire_n10l1l1l_dataout WHEN n11O0ilO = '1' ELSE wire_n10iOOOl_dataout; + wire_n10iOO0O_dataout <= n11O00iO WHEN n11O0ilO = '1' ELSE wire_n10iOOOO_dataout; + wire_n10iOO1i_dataout <= n11O0ilO OR niOl0i00i; + wire_n10iOO1l_dataout <= wire_n10iOOli_dataout AND NOT(niOl0i00i); + wire_n10iOO1O_dataout <= wire_n10iOOll_dataout AND NOT(niOl0i00i); + wire_n10iOOi_dataout <= wire_n1i1l1l_dataout WHEN k_hip(0) = '1' ELSE wire_n10OliO_dataout; + wire_n10iOOii_dataout <= wire_n10l111i_dataout AND NOT(n11O0ilO); + wire_n10iOOil_dataout <= n11O0iiO WHEN n11O0ilO = '1' ELSE n11O0iii; + wire_n10iOOiO_dataout <= n11O0ili WHEN n11O0ilO = '1' ELSE n11O0iil; + wire_n10iOOl_dataout <= wire_n1i1l1O_dataout WHEN k_hip(0) = '1' ELSE wire_n10Olli_dataout; + wire_n10iOOli_dataout <= niOl0i01l AND NOT(n11O0ilO); + wire_n10iOOll_dataout <= wire_w_lg_niOl0i01l21114w(0) AND NOT(n11O0ilO); + wire_n10iOOlO_dataout <= wire_n10l111l_dataout WHEN n11O0ilO = '1' ELSE wire_n10iOOOi_dataout; + wire_n10iOOO_dataout <= wire_n1i1l0i_dataout WHEN k_hip(0) = '1' ELSE wire_n10Olll_dataout; + wire_n10iOOOi_dataout <= wire_n10l111l_dataout WHEN niOl0i01l = '1' ELSE n11O0i0i; + wire_n10iOOOl_dataout <= wire_n10l1l1l_dataout AND NOT(niOl0i01l); + wire_n10iOOOO_dataout <= n11O00iO OR niOl0i01l; + wire_n10l000i_dataout <= wire_n10l0l0l_dataout AND NOT(niOl0i0ll); + wire_n10l000l_dataout <= wire_n10l0l0O_dataout AND NOT(niOl0i0ll); + wire_n10l000O_dataout <= wire_n10l0lii_dataout AND NOT(niOl0i0ll); + wire_n10l001i_dataout <= wire_n10l0l1l_dataout AND NOT(niOl0i0ll); + wire_n10l001l_dataout <= wire_n10l0l1O_dataout AND NOT(niOl0i0ll); + wire_n10l001O_dataout <= wire_n10l0l0i_dataout AND NOT(niOl0i0ll); + wire_n10l00i_dataout <= wire_n1i1Oii_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(75); + wire_n10l00ii_dataout <= wire_n10l0lil_dataout AND NOT(niOl0i0ll); + wire_n10l00il_dataout <= wire_n10l0liO_dataout AND NOT(niOl0i0ll); + wire_n10l00iO_dataout <= wire_n10l0lli_dataout AND NOT(niOl0i0ll); + wire_n10l00l_dataout <= wire_n1i1Oil_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(76); + wire_n10l00li_dataout <= wire_n10l0lll_dataout AND NOT(niOl0i0ll); + wire_n10l00ll_dataout <= wire_n10l0llO_dataout AND NOT(niOl0i0ll); + wire_n10l00lO_dataout <= wire_n10l0lOi_dataout AND NOT(niOl0i0ll); + wire_n10l00O_dataout <= wire_n1i1OiO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(77); + wire_n10l00Oi_dataout <= wire_n10l0lOl_dataout AND NOT(niOl0i0ll); + wire_n10l00Ol_dataout <= wire_n10l0lOO_dataout AND NOT(niOl0i0ll); + wire_n10l00OO_dataout <= wire_n10l0O1i_dataout AND NOT(niOl0i0ll); + wire_n10l010i_dataout <= wire_n10l0iii_dataout AND NOT(niOl0i0Oi); + wire_n10l010l_dataout <= wire_n10l0iil_dataout AND NOT(niOl0i0Oi); + wire_n10l010O_dataout <= wire_n10l0iiO_dataout AND NOT(niOl0i0Oi); + wire_n10l011i_dataout <= wire_n10l0i0i_dataout AND NOT(niOl0i0Oi); + wire_n10l011l_dataout <= wire_n10l0i0l_dataout AND NOT(niOl0i0Oi); + wire_n10l011O_dataout <= wire_n10l0i0O_dataout AND NOT(niOl0i0Oi); + wire_n10l01i_dataout <= wire_n1i1O0i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(72); + wire_n10l01ii_dataout <= wire_n10l01ll_dataout AND NOT(niOl0i0Oi); + wire_n10l01il_dataout <= n11O0ilO AND NOT(niOl0i0Oi); + wire_n10l01iO_dataout <= n11O0iiO WHEN niOl0i0ll = '1' ELSE wire_n10l0ili_dataout; + wire_n10l01l_dataout <= wire_n1i1O0l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(73); + wire_n10l01li_dataout <= n11O0ili WHEN niOl0i0ll = '1' ELSE wire_n10l0ill_dataout; + wire_n10l01ll_dataout <= n11O0ill WHEN niOl0i0ll = '1' ELSE wire_n10l0ilO_dataout; + wire_n10l01lO_dataout <= n11O0i0O WHEN niOl0i0ll = '1' ELSE wire_n10l0iOi_dataout; + wire_n10l01O_dataout <= wire_n1i1O0O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(74); + wire_n10l01Oi_dataout <= wire_n10l0iOl_dataout AND NOT(niOl0i0ll); + wire_n10l01Ol_dataout <= wire_n10l0iOO_dataout AND NOT(niOl0i0ll); + wire_n10l01OO_dataout <= wire_n10l0l1i_dataout OR niOl0i0ll; + wire_n10l0i0i_dataout <= wire_n10l0O0l_dataout AND NOT(niOl0i0ll); + wire_n10l0i0l_dataout <= wire_n10l0O0O_dataout AND NOT(niOl0i0ll); + wire_n10l0i0O_dataout <= wire_n10l0Oii_dataout AND NOT(niOl0i0ll); + wire_n10l0i1i_dataout <= wire_n10l0O1l_dataout AND NOT(niOl0i0ll); + wire_n10l0i1l_dataout <= wire_n10l0O1O_dataout AND NOT(niOl0i0ll); + wire_n10l0i1O_dataout <= wire_n10l0O0i_dataout AND NOT(niOl0i0ll); + wire_n10l0ii_dataout <= wire_n1i1Oli_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(78); + wire_n10l0iii_dataout <= wire_n10l0Oil_dataout AND NOT(niOl0i0ll); + wire_n10l0iil_dataout <= wire_n10l0OiO_dataout AND NOT(niOl0i0ll); + wire_n10l0iiO_dataout <= wire_n10l0Oli_dataout AND NOT(niOl0i0ll); + wire_n10l0il_dataout <= wire_n1i1Oll_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(79); + wire_n10l0ili_dataout <= n11O0iiO WHEN niOl0i0iO = '1' ELSE wire_n10l0Oll_dataout; + wire_n10l0ill_dataout <= n11O0ili WHEN niOl0i0iO = '1' ELSE wire_n10l0OlO_dataout; + wire_n10l0ilO_dataout <= n11O0ill WHEN niOl0i0iO = '1' ELSE wire_n10l0OOi_dataout; + wire_n10l0iO_dataout <= wire_n1i1OlO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(80); + wire_n10l0iOi_dataout <= n11O0i0O WHEN niOl0i0iO = '1' ELSE wire_n10l0OOl_dataout; + wire_n10l0iOl_dataout <= wire_n10l0OOO_dataout OR niOl0i0iO; + wire_n10l0iOO_dataout <= wire_n10li11i_dataout AND NOT(niOl0i0iO); + wire_n10l0l0i_dataout <= wire_n10li10l_dataout AND NOT(niOl0i0iO); + wire_n10l0l0l_dataout <= wire_n10li10O_dataout AND NOT(niOl0i0iO); + wire_n10l0l0O_dataout <= wire_n10li1ii_dataout AND NOT(niOl0i0iO); + wire_n10l0l1i_dataout <= wire_n10li11l_dataout AND NOT(niOl0i0iO); + wire_n10l0l1l_dataout <= wire_n10li11O_dataout AND NOT(niOl0i0iO); + wire_n10l0l1O_dataout <= wire_n10li10i_dataout AND NOT(niOl0i0iO); + wire_n10l0li_dataout <= wire_n1i1OOi_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(81); + wire_n10l0lii_dataout <= wire_n10li1il_dataout AND NOT(niOl0i0iO); + wire_n10l0lil_dataout <= wire_n10li1iO_dataout AND NOT(niOl0i0iO); + wire_n10l0liO_dataout <= wire_n10li1li_dataout AND NOT(niOl0i0iO); + wire_n10l0ll_dataout <= wire_n1i1OOl_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(82); + wire_n10l0lli_dataout <= wire_n10li1ll_dataout AND NOT(niOl0i0iO); + wire_n10l0lll_dataout <= wire_n10li1lO_dataout AND NOT(niOl0i0iO); + wire_n10l0llO_dataout <= wire_n10li1Oi_dataout AND NOT(niOl0i0iO); + wire_n10l0lO_dataout <= wire_n1i1OOO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(83); + wire_n10l0lOi_dataout <= wire_n10li1Ol_dataout AND NOT(niOl0i0iO); + wire_n10l0lOl_dataout <= wire_n10li1OO_dataout AND NOT(niOl0i0iO); + wire_n10l0lOO_dataout <= wire_n10li01i_dataout AND NOT(niOl0i0iO); + wire_n10l0O0i_dataout <= wire_n10li00l_dataout AND NOT(niOl0i0iO); + wire_n10l0O0l_dataout <= wire_n10li00O_dataout AND NOT(niOl0i0iO); + wire_n10l0O0O_dataout <= wire_n10li0ii_dataout AND NOT(niOl0i0iO); + wire_n10l0O1i_dataout <= wire_n10li01l_dataout AND NOT(niOl0i0iO); + wire_n10l0O1l_dataout <= wire_n10li01O_dataout AND NOT(niOl0i0iO); + wire_n10l0O1O_dataout <= wire_n10li00i_dataout AND NOT(niOl0i0iO); + wire_n10l0Oi_dataout <= wire_n1i011i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(84); + wire_n10l0Oii_dataout <= wire_n10li0il_dataout AND NOT(niOl0i0iO); + wire_n10l0Oil_dataout <= wire_n10li0iO_dataout AND NOT(niOl0i0iO); + wire_n10l0OiO_dataout <= wire_n10li0li_dataout AND NOT(niOl0i0iO); + wire_n10l0Ol_dataout <= wire_n1i011l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(85); + wire_n10l0Oli_dataout <= wire_n10li0ll_dataout AND NOT(niOl0i0iO); + wire_n10l0Oll_dataout <= wire_n10li0lO_dataout WHEN niOl0i0il = '1' ELSE n11O0iiO; + wire_n10l0OlO_dataout <= wire_n10li0Oi_dataout WHEN niOl0i0il = '1' ELSE n11O0ili; + wire_n10l0OO_dataout <= wire_n1i011O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(86); + wire_n10l0OOi_dataout <= wire_n10li0Ol_dataout WHEN niOl0i0il = '1' ELSE n11O0ill; + wire_n10l0OOl_dataout <= wire_n10li0OO_dataout WHEN niOl0i0il = '1' ELSE n11O0i0O; + wire_n10l0OOO_dataout <= n11O0iOl AND NOT(niOl0i0il); + wire_n10l10i_dataout <= wire_n1i1lil_dataout WHEN k_hip(0) = '1' ELSE wire_n10OlOO_dataout; + wire_n10l10l_dataout <= wire_n1i1liO_dataout WHEN k_hip(0) = '1' ELSE wire_n10OO1i_dataout; + wire_n10l10O_dataout <= wire_n1i1lli_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(132); + wire_n10l111i_dataout <= niOli1iOO AND niOl0i01l; + wire_n10l111l_dataout <= n11O0i0i WHEN niOO10lOO = '1' ELSE n1iiii1i; + wire_n10l11i_dataout <= wire_n1i1l0l_dataout WHEN k_hip(0) = '1' ELSE wire_n10OllO_dataout; + wire_n10l11l_dataout <= wire_n1i1l0O_dataout WHEN k_hip(0) = '1' ELSE wire_n10OlOi_dataout; + wire_n10l11O_dataout <= wire_n1i1lii_dataout WHEN k_hip(0) = '1' ELSE wire_n10OlOl_dataout; + wire_n10l1ii_dataout <= nlO0llOi OR k_hip(0); + wire_n10l1il_dataout <= wire_n1i1lll_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(64); + wire_n10l1iO_dataout <= wire_n1i1llO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(65); + wire_n10l1l0i_dataout <= wire_nlOi0iilO_dataout WHEN wire_niO01ill_w_lg_n11O0Oli21040w(0) = '1' ELSE n11O01ll; + wire_n10l1l0l_dataout <= wire_nlOi0iiOi_dataout WHEN wire_niO01ill_w_lg_n11O0Oli21040w(0) = '1' ELSE n11O01lO; + wire_n10l1l0O_dataout <= wire_nlOi0iiOl_dataout WHEN wire_niO01ill_w_lg_n11O0Oli21040w(0) = '1' ELSE n11O01Oi; + wire_n10l1l1l_dataout <= n11O0iOi OR (n11l0OOl AND niOl0Oiii); + wire_n10l1li_dataout <= wire_n1i1lOi_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(66); + wire_n10l1lii_dataout <= n11li1iO WHEN niOl0i0Oi = '1' ELSE wire_n10l01iO_dataout; + wire_n10l1lil_dataout <= n11li1li WHEN niOl0i0Oi = '1' ELSE wire_n10l01li_dataout; + wire_n10l1liO_dataout <= wire_n10lii1i_dataout WHEN niOl0i0Oi = '1' ELSE wire_n10l01lO_dataout; + wire_n10l1ll_dataout <= wire_n1i1lOl_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(67); + wire_n10l1lli_dataout <= wire_n10l01Oi_dataout AND NOT(niOl0i0Oi); + wire_n10l1lll_dataout <= wire_n10l01Ol_dataout AND NOT(niOl0i0Oi); + wire_n10l1llO_dataout <= wire_n10l01OO_dataout AND NOT(niOl0i0Oi); + wire_n10l1lO_dataout <= wire_n1i1lOO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(68); + wire_n10l1lOi_dataout <= wire_n10l001i_dataout AND NOT(niOl0i0Oi); + wire_n10l1lOl_dataout <= wire_n10l001l_dataout AND NOT(niOl0i0Oi); + wire_n10l1lOO_dataout <= wire_n10l001O_dataout AND NOT(niOl0i0Oi); + wire_n10l1O0i_dataout <= wire_n10l00ii_dataout AND NOT(niOl0i0Oi); + wire_n10l1O0l_dataout <= wire_n10l00il_dataout AND NOT(niOl0i0Oi); + wire_n10l1O0O_dataout <= wire_n10l00iO_dataout AND NOT(niOl0i0Oi); + wire_n10l1O1i_dataout <= wire_n10l000i_dataout AND NOT(niOl0i0Oi); + wire_n10l1O1l_dataout <= wire_n10l000l_dataout AND NOT(niOl0i0Oi); + wire_n10l1O1O_dataout <= wire_n10l000O_dataout AND NOT(niOl0i0Oi); + wire_n10l1Oi_dataout <= wire_n1i1O1i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(69); + wire_n10l1Oii_dataout <= wire_n10l00li_dataout AND NOT(niOl0i0Oi); + wire_n10l1Oil_dataout <= wire_n10l00ll_dataout OR niOl0i0Oi; + wire_n10l1OiO_dataout <= wire_n10l00lO_dataout AND NOT(niOl0i0Oi); + wire_n10l1Ol_dataout <= wire_n1i1O1l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(70); + wire_n10l1Oli_dataout <= wire_n10l00Oi_dataout AND NOT(niOl0i0Oi); + wire_n10l1Oll_dataout <= wire_n10l00Ol_dataout AND NOT(niOl0i0Oi); + wire_n10l1OlO_dataout <= wire_n10l00OO_dataout AND NOT(niOl0i0Oi); + wire_n10l1OO_dataout <= wire_n1i1O1O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(71); + wire_n10l1OOi_dataout <= wire_n10l0i1i_dataout AND NOT(niOl0i0Oi); + wire_n10l1OOl_dataout <= wire_n10l0i1l_dataout AND NOT(niOl0i0Oi); + wire_n10l1OOO_dataout <= wire_n10l0i1O_dataout AND NOT(niOl0i0Oi); + wire_n10li00i_dataout <= n11O0O1O AND NOT(niOl0i0il); + wire_n10li00l_dataout <= n11O0O0i AND NOT(niOl0i0il); + wire_n10li00O_dataout <= n11O0O0l AND NOT(niOl0i0il); + wire_n10li01i_dataout <= n11O0lOO AND NOT(niOl0i0il); + wire_n10li01l_dataout <= n11O0O1i AND NOT(niOl0i0il); + wire_n10li01O_dataout <= n11O0O1l AND NOT(niOl0i0il); + wire_n10li0i_dataout <= wire_n1i01ii_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(90); + wire_n10li0ii_dataout <= n11O0O0O AND NOT(niOl0i0il); + wire_n10li0il_dataout <= n11O0Oii AND NOT(niOl0i0il); + wire_n10li0iO_dataout <= n11O0Oil AND NOT(niOl0i0il); + wire_n10li0l_dataout <= wire_n1i01il_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(91); + wire_n10li0li_dataout <= n11O00ii AND NOT(niOl0i0il); + wire_n10li0ll_dataout <= n11O00il AND NOT(niOl0i0il); + wire_n10li0lO_dataout <= n11O0iiO WHEN nlOll0O0O = '1' ELSE n11li1iO; + wire_n10li0O_dataout <= wire_n1i01iO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(92); + wire_n10li0Oi_dataout <= n11O0ili WHEN nlOll0O0O = '1' ELSE n11li1li; + wire_n10li0Ol_dataout <= n11O0ill AND nlOll0O0O; + wire_n10li0OO_dataout <= n11O0i0O WHEN nlOll0O0O = '1' ELSE wire_n10lii1i_dataout; + wire_n10li10i_dataout <= n11O0l1O AND NOT(niOl0i0il); + wire_n10li10l_dataout <= n11O0l0i AND NOT(niOl0i0il); + wire_n10li10O_dataout <= n11O0l0l AND NOT(niOl0i0il); + wire_n10li11i_dataout <= n11O0iOO AND NOT(niOl0i0il); + wire_n10li11l_dataout <= n11O0l1i AND NOT(niOl0i0il); + wire_n10li11O_dataout <= nlOll0O0O WHEN niOl0i0il = '1' ELSE n11O0l1l; + wire_n10li1i_dataout <= wire_n1i010i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(87); + wire_n10li1ii_dataout <= n11O0l0O AND NOT(niOl0i0il); + wire_n10li1il_dataout <= n11O0lii AND NOT(niOl0i0il); + wire_n10li1iO_dataout <= n11O0lil AND NOT(niOl0i0il); + wire_n10li1l_dataout <= wire_n1i010l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(88); + wire_n10li1li_dataout <= n11O0liO AND NOT(niOl0i0il); + wire_n10li1ll_dataout <= n11O0lli AND NOT(niOl0i0il); + wire_n10li1lO_dataout <= n11O0lll AND NOT(niOl0i0il); + wire_n10li1O_dataout <= wire_n1i010O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(89); + wire_n10li1Oi_dataout <= wire_niO01ill_w_lg_nlOll0O0O21039w(0) WHEN niOl0i0il = '1' ELSE n11O0llO; + wire_n10li1Ol_dataout <= n11O0lOi AND NOT(niOl0i0il); + wire_n10li1OO_dataout <= n11O0lOl AND NOT(niOl0i0il); + wire_n10lii1i_dataout <= n11O0i0O OR niOli1iOO; + wire_n10liii_dataout <= wire_n1i01li_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(93); + wire_n10liil_dataout <= wire_n1i01ll_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(94); + wire_n10liiO_dataout <= wire_n1i01lO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(95); + wire_n10lili_dataout <= wire_n1i01Oi_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(96); + wire_n10lill_dataout <= wire_n1i01Ol_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(97); + wire_n10lilO_dataout <= wire_n1i01OO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(98); + wire_n10lilOO_dataout <= n11O0iOi OR niOl0ii1i; + wire_n10liO0i_dataout <= n11O0i0l WHEN niOl0ii1l = '1' ELSE wire_n10ll00i_dataout; + wire_n10liO0l_dataout <= wire_n1i0l0OO_dataout AND NOT(niOl0ii1l); + wire_n10liO0O_dataout <= wire_n1i0li1i_dataout AND NOT(niOl0ii1l); + wire_n10liO1i_dataout <= wire_n10liO1l_dataout WHEN niOl0Oiii = '1' ELSE n11O0i0l; + wire_n10liO1l_dataout <= n11O0i0l AND NOT((n1110OlO AND niOlOll0O)); + wire_n10liOi_dataout <= wire_n1i001i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(99); + wire_n10liOii_dataout <= wire_n1i0li1l_dataout AND NOT(niOl0ii1l); + wire_n10liOil_dataout <= wire_n1i0li1O_dataout AND NOT(niOl0ii1l); + wire_n10liOiO_dataout <= wire_n1i0li0i_dataout AND NOT(niOl0ii1l); + wire_n10liOl_dataout <= wire_n1i001l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(100); + wire_n10liOli_dataout <= wire_n1i0li0l_dataout AND NOT(niOl0ii1l); + wire_n10liOll_dataout <= wire_n1i0li0O_dataout AND NOT(niOl0ii1l); + wire_n10liOlO_dataout <= wire_n1i0liii_dataout AND NOT(niOl0ii1l); + wire_n10liOO_dataout <= wire_n1i001O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(101); + wire_n10liOOi_dataout <= wire_n1i0liil_dataout AND NOT(niOl0ii1l); + wire_n10liOOl_dataout <= wire_n1i0liiO_dataout OR niOl0ii1l; + wire_n10liOOO_dataout <= wire_n1i0lili_dataout AND NOT(niOl0ii1l); + wire_n10ll00i_dataout <= n11O0i0l OR niOl0l1li; + wire_n10ll00O_dataout <= n11O00il OR (wire_nlOi00l1O_dataout AND wire_niO01ill_w_lg_nlOOOl00i21006w(0)); + wire_n10ll01i_dataout <= n11O0ilO AND NOT(niOl0ii1l); + wire_n10ll01l_dataout <= wire_niO01iOi_w_lg_n11O0i0l21009w(0) WHEN niOl0l1li = '1' ELSE n11O0llO; + wire_n10ll01O_dataout <= n11O0i0l WHEN niOl0l1li = '1' ELSE n11O0Oil; + wire_n10ll0i_dataout <= wire_n1i00ii_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(105); + wire_n10ll0l_dataout <= wire_n1i00il_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(106); + wire_n10ll0O_dataout <= wire_n1i00iO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(107); + wire_n10ll10i_dataout <= wire_n1i0liOl_dataout AND NOT(niOl0ii1l); + wire_n10ll10l_dataout <= wire_n1i0liOO_dataout AND NOT(niOl0ii1l); + wire_n10ll10O_dataout <= wire_n1i0ll1i_dataout AND NOT(niOl0ii1l); + wire_n10ll11i_dataout <= wire_n1i0lill_dataout AND NOT(niOl0ii1l); + wire_n10ll11l_dataout <= wire_n1i0lilO_dataout AND NOT(niOl0ii1l); + wire_n10ll11O_dataout <= wire_n10ll01l_dataout AND NOT(niOl0ii1l); + wire_n10ll1i_dataout <= wire_n1i000i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(102); + wire_n10ll1ii_dataout <= wire_n1i0ll1l_dataout AND NOT(niOl0ii1l); + wire_n10ll1il_dataout <= wire_n1i0ll1O_dataout AND NOT(niOl0ii1l); + wire_n10ll1iO_dataout <= wire_n1i0ll0i_dataout AND NOT(niOl0ii1l); + wire_n10ll1l_dataout <= wire_n1i000l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(103); + wire_n10ll1li_dataout <= wire_n1i0ll0l_dataout AND NOT(niOl0ii1l); + wire_n10ll1ll_dataout <= wire_n1i0ll0O_dataout AND NOT(niOl0ii1l); + wire_n10ll1lO_dataout <= wire_n1i0llii_dataout AND NOT(niOl0ii1l); + wire_n10ll1O_dataout <= wire_n1i000O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(104); + wire_n10ll1Oi_dataout <= wire_n1i0llil_dataout AND NOT(niOl0ii1l); + wire_n10ll1Ol_dataout <= wire_n10ll01O_dataout AND NOT(niOl0ii1l); + wire_n10ll1OO_dataout <= wire_n10ll00O_dataout WHEN niOl0ii1l = '1' ELSE n11O00il; + wire_n10lli0i_dataout <= wire_n1i0li1l_dataout AND NOT(niOl0ii0i); + wire_n10lli0l_dataout <= wire_n1i0li1O_dataout AND NOT(niOl0ii0i); + wire_n10lli0O_dataout <= wire_n1i0li0i_dataout AND NOT(niOl0ii0i); + wire_n10lli1l_dataout <= wire_n1i0l0OO_dataout AND NOT(niOl0ii0i); + wire_n10lli1O_dataout <= wire_n1i0li1i_dataout AND NOT(niOl0ii0i); + wire_n10llii_dataout <= wire_n1i00li_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(108); + wire_n10lliii_dataout <= wire_n1i0li0l_dataout AND NOT(niOl0ii0i); + wire_n10lliil_dataout <= wire_n1i0li0O_dataout AND NOT(niOl0ii0i); + wire_n10lliiO_dataout <= wire_n1i0liii_dataout AND NOT(niOl0ii0i); + wire_n10llil_dataout <= wire_n1i00ll_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(109); + wire_n10llili_dataout <= wire_n1i0liil_dataout AND NOT(niOl0ii0i); + wire_n10llill_dataout <= wire_n1i0liiO_dataout AND NOT(niOl0ii0i); + wire_n10llilO_dataout <= wire_n1i0lili_dataout AND NOT(niOl0ii0i); + wire_n10lliO_dataout <= wire_n1i00lO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(110); + wire_n10lliOi_dataout <= wire_n1i0lill_dataout AND NOT(niOl0ii0i); + wire_n10lliOl_dataout <= wire_n1i0lilO_dataout AND NOT(niOl0ii0i); + wire_n10lliOO_dataout <= wire_n1i0liOi_dataout AND NOT(niOl0ii0i); + wire_n10lll0i_dataout <= wire_n1i0ll1l_dataout AND NOT(niOl0ii0i); + wire_n10lll0l_dataout <= wire_n1i0ll1O_dataout AND NOT(niOl0ii0i); + wire_n10lll0O_dataout <= wire_n1i0ll0i_dataout AND NOT(niOl0ii0i); + wire_n10lll1i_dataout <= wire_n1i0liOl_dataout OR niOl0ii0i; + wire_n10lll1l_dataout <= wire_n1i0liOO_dataout AND NOT(niOl0ii0i); + wire_n10lll1O_dataout <= wire_n1i0ll1i_dataout AND NOT(niOl0ii0i); + wire_n10llli_dataout <= wire_n1i00Oi_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(111); + wire_n10lllii_dataout <= wire_n1i0ll0l_dataout AND NOT(niOl0ii0i); + wire_n10lllil_dataout <= wire_n1i0ll0O_dataout AND NOT(niOl0ii0i); + wire_n10llliO_dataout <= wire_n1i0llii_dataout AND NOT(niOl0ii0i); + wire_n10llll_dataout <= wire_n1i00Ol_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(112); + wire_n10lllli_dataout <= wire_n1i0llil_dataout AND NOT(niOl0ii0i); + wire_n10lllll_dataout <= wire_n1i0lliO_dataout AND NOT(niOl0ii0i); + wire_n10llllO_dataout <= k_conf(360) WHEN niOl0ii0i = '1' ELSE wire_n10lllOi_dataout; + wire_n10lllO_dataout <= wire_n1i00OO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(113); + wire_n10lllOi_dataout <= k_conf(360) WHEN niOl0l1li = '1' ELSE n11O01li; + wire_n10lllOl_dataout <= wire_n10lOO0l_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO1ll_dataout; + wire_n10lllOO_dataout <= wire_n10lOO0O_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO1lO_dataout; + wire_n10llO0i_dataout <= wire_n10lOOli_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO01i_dataout; + wire_n10llO0l_dataout <= wire_n10lOOll_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO01l_dataout; + wire_n10llO0O_dataout <= wire_n10lOOlO_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO01O_dataout; + wire_n10llO1i_dataout <= wire_n10lOOii_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO1Oi_dataout; + wire_n10llO1l_dataout <= wire_n10lOOil_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO1Ol_dataout; + wire_n10llO1O_dataout <= wire_n10lOOiO_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO1OO_dataout; + wire_n10llOi_dataout <= wire_n1i0i1i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(114); + wire_n10llOii_dataout <= wire_n10lOOOi_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO00i_dataout; + wire_n10llOil_dataout <= wire_n10lOOOl_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO00l_dataout; + wire_n10llOiO_dataout <= wire_n10lOOOO_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO00O_dataout; + wire_n10llOl_dataout <= wire_n1i0i1l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(115); + wire_n10llOli_dataout <= wire_n10O111i_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0ii_dataout; + wire_n10llOll_dataout <= wire_n10O111l_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0il_dataout; + wire_n10llOlO_dataout <= wire_n10O111O_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0iO_dataout; + wire_n10llOO_dataout <= wire_n1i0i1O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(116); + wire_n10llOOi_dataout <= wire_n10O110i_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0li_dataout; + wire_n10llOOl_dataout <= wire_n10O110l_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0ll_dataout; + wire_n10llOOO_dataout <= wire_n10O110O_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0lO_dataout; + wire_n10lO00i_dataout <= wire_n10lOiOl_dataout AND NOT(niOl0iilO); + wire_n10lO00l_dataout <= wire_n10lOiOO_dataout AND NOT(niOl0iilO); + wire_n10lO00O_dataout <= wire_n10lOl1i_dataout AND NOT(niOl0iilO); + wire_n10lO01i_dataout <= wire_n10lOill_dataout AND NOT(niOl0iilO); + wire_n10lO01l_dataout <= wire_n10lOilO_dataout AND NOT(niOl0iilO); + wire_n10lO01O_dataout <= wire_n10lOiOi_dataout AND NOT(niOl0iilO); + wire_n10lO0i_dataout <= wire_n1i0iii_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(120); + wire_n10lO0ii_dataout <= wire_n10lOl1l_dataout AND NOT(niOl0iilO); + wire_n10lO0il_dataout <= wire_n10lOl1O_dataout AND NOT(niOl0iilO); + wire_n10lO0iO_dataout <= wire_n10lOl0i_dataout AND NOT(niOl0iilO); + wire_n10lO0l_dataout <= wire_n1i0iil_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(121); + wire_n10lO0li_dataout <= wire_n10lOl0l_dataout AND NOT(niOl0iilO); + wire_n10lO0ll_dataout <= wire_n10lOl0O_dataout AND NOT(niOl0iilO); + wire_n10lO0lO_dataout <= wire_n10lOlii_dataout AND NOT(niOl0iilO); + wire_n10lO0O_dataout <= wire_n1i0iiO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(122); + wire_n10lO0Oi_dataout <= wire_n10lOlil_dataout OR niOl0iilO; + wire_n10lO0Ol_dataout <= wire_n10lOliO_dataout AND NOT(niOl0iilO); + wire_n10lO0OO_dataout <= wire_n10lOlli_dataout AND NOT(niOl0iilO); + wire_n10lO10i_dataout <= wire_n10O11li_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lOi1i_dataout; + wire_n10lO10l_dataout <= wire_n10O11ll_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lOi1l_dataout; + wire_n10lO10O_dataout <= wire_n10O11lO_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lOi1O_dataout; + wire_n10lO11i_dataout <= wire_n10O11ii_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0Oi_dataout; + wire_n10lO11l_dataout <= wire_n10O11il_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0Ol_dataout; + wire_n10lO11O_dataout <= wire_n10O11iO_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lO0OO_dataout; + wire_n10lO1i_dataout <= wire_n1i0i0i_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(117); + wire_n10lO1ii_dataout <= wire_n10O11Oi_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lOi0i_dataout; + wire_n10lO1il_dataout <= wire_n10O11Ol_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lOi0l_dataout; + wire_n10lO1iO_dataout <= wire_n10O11OO_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n10lOi0O_dataout; + wire_n10lO1l_dataout <= wire_n1i0i0l_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(118); + wire_n10lO1li_dataout <= wire_n10O101i_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE n11O1O1O; + wire_n10lO1ll_dataout <= n11O01li WHEN niOl0iilO = '1' ELSE wire_n10lOO1l_dataout; + wire_n10lO1lO_dataout <= wire_n10lOiii_dataout AND NOT(niOl0iilO); + wire_n10lO1O_dataout <= wire_n1i0i0O_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(119); + wire_n10lO1Oi_dataout <= wire_n10lOiil_dataout AND NOT(niOl0iilO); + wire_n10lO1Ol_dataout <= wire_n10lOiiO_dataout AND NOT(niOl0iilO); + wire_n10lO1OO_dataout <= wire_n10lOili_dataout AND NOT(niOl0iilO); + wire_n10lOi0i_dataout <= wire_n10lOlOl_dataout AND NOT(niOl0iilO); + wire_n10lOi0l_dataout <= wire_n10lOlOO_dataout AND NOT(niOl0iilO); + wire_n10lOi0O_dataout <= wire_n10lOO1i_dataout AND NOT(niOl0iilO); + wire_n10lOi1i_dataout <= wire_n10lOlll_dataout AND NOT(niOl0iilO); + wire_n10lOi1l_dataout <= wire_n10lOllO_dataout AND NOT(niOl0iilO); + wire_n10lOi1O_dataout <= wire_n10lOlOi_dataout AND NOT(niOl0iilO); + wire_n10lOii_dataout <= wire_n1i0ili_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(123); + wire_n10lOiii_dataout <= wire_n10O0iOl_dataout AND NOT(niOl0ii0l); + wire_n10lOiil_dataout <= wire_n10O0iOO_dataout AND NOT(niOl0ii0l); + wire_n10lOiiO_dataout <= wire_n10O0l1i_dataout AND NOT(niOl0ii0l); + wire_n10lOil_dataout <= wire_n1i0ill_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(124); + wire_n10lOili_dataout <= wire_n10O0l1l_dataout AND NOT(niOl0ii0l); + wire_n10lOill_dataout <= wire_n10O0l1O_dataout AND NOT(niOl0ii0l); + wire_n10lOilO_dataout <= wire_n10O0l0i_dataout AND NOT(niOl0ii0l); + wire_n10lOiO_dataout <= wire_n1i0ilO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(125); + wire_n10lOiOi_dataout <= wire_n10O0l0l_dataout AND NOT(niOl0ii0l); + wire_n10lOiOl_dataout <= wire_n10O0l0O_dataout AND NOT(niOl0ii0l); + wire_n10lOiOO_dataout <= wire_n10O0lii_dataout AND NOT(niOl0ii0l); + wire_n10lOl0i_dataout <= wire_n10O0lll_dataout AND NOT(niOl0ii0l); + wire_n10lOl0l_dataout <= wire_n10O0llO_dataout AND NOT(niOl0ii0l); + wire_n10lOl0O_dataout <= wire_n10O0lOi_dataout AND NOT(niOl0ii0l); + wire_n10lOl1i_dataout <= wire_n10O0lil_dataout AND NOT(niOl0ii0l); + wire_n10lOl1l_dataout <= wire_n10O0liO_dataout AND NOT(niOl0ii0l); + wire_n10lOl1O_dataout <= wire_n10O0lli_dataout AND NOT(niOl0ii0l); + wire_n10lOli_dataout <= wire_n1i0iOi_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(126); + wire_n10lOlii_dataout <= wire_n10O0lOl_dataout OR niOl0ii0l; + wire_n10lOlil_dataout <= wire_n10O0lOO_dataout AND NOT(niOl0ii0l); + wire_n10lOliO_dataout <= wire_n10O0O1i_dataout AND NOT(niOl0ii0l); + wire_n10lOll_dataout <= wire_n1i0iOl_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(127); + wire_n10lOlli_dataout <= wire_n10O0O1l_dataout AND NOT(niOl0ii0l); + wire_n10lOlll_dataout <= wire_n10O0O1O_dataout AND NOT(niOl0ii0l); + wire_n10lOllO_dataout <= wire_n10O0O0i_dataout AND NOT(niOl0ii0l); + wire_n10lOlO_dataout <= wire_n1i0iOO_dataout WHEN k_hip(0) = '1' ELSE wire_nlll0lli_q(132); + wire_n10lOlOi_dataout <= wire_n10O0O0l_dataout AND NOT(niOl0ii0l); + wire_n10lOlOl_dataout <= wire_n10O0O0O_dataout AND NOT(niOl0ii0l); + wire_n10lOlOO_dataout <= wire_n10O0Oii_dataout AND NOT(niOl0ii0l); + wire_n10lOO0l_dataout <= n11O01li WHEN niOl0iili = '1' ELSE wire_n10O1ilO_dataout; + wire_n10lOO0O_dataout <= wire_n10O101l_dataout AND NOT(niOl0iili); + wire_n10lOO1i_dataout <= wire_n10O0Oil_dataout AND NOT(niOl0ii0l); + wire_n10lOO1l_dataout <= n11O01li AND NOT(niOl0ii0l); + wire_n10lOOi_dataout <= wire_nlll0lli_q(96) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(64); + wire_n10lOOii_dataout <= wire_n10O101O_dataout AND NOT(niOl0iili); + wire_n10lOOil_dataout <= wire_n10O100i_dataout AND NOT(niOl0iili); + wire_n10lOOiO_dataout <= wire_n10O100l_dataout AND NOT(niOl0iili); + wire_n10lOOl_dataout <= wire_nlll0lli_q(97) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(65); + wire_n10lOOli_dataout <= wire_n10O100O_dataout AND NOT(niOl0iili); + wire_n10lOOll_dataout <= wire_n10O10ii_dataout AND NOT(niOl0iili); + wire_n10lOOlO_dataout <= wire_n10O10il_dataout AND NOT(niOl0iili); + wire_n10lOOO_dataout <= wire_nlll0lli_q(98) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(66); + wire_n10lOOOi_dataout <= wire_n10O10iO_dataout AND NOT(niOl0iili); + wire_n10lOOOl_dataout <= wire_n10O10li_dataout AND NOT(niOl0iili); + wire_n10lOOOO_dataout <= wire_n10O10ll_dataout AND NOT(niOl0iili); + wire_n10O000i_dataout <= wire_n10O0iOO_dataout AND NOT(niOl0il1i); + wire_n10O000l_dataout <= wire_n10O0l1i_dataout AND NOT(niOl0il1i); + wire_n10O000O_dataout <= wire_n10O0l1l_dataout AND NOT(niOl0il1i); + wire_n10O001i_dataout <= wire_n10O0ilO_dataout AND NOT(niOl0il0l); + wire_n10O001l_dataout <= wire_n10O0iOi_dataout AND NOT(niOl0il1i); + wire_n10O001O_dataout <= wire_n10O0iOl_dataout AND NOT(niOl0il1i); + wire_n10O00i_dataout <= wire_nlll0lli_q(117) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(85); + wire_n10O00ii_dataout <= wire_n10O0l1O_dataout AND NOT(niOl0il1i); + wire_n10O00il_dataout <= wire_n10O0l0i_dataout AND NOT(niOl0il1i); + wire_n10O00iO_dataout <= wire_n10O0l0l_dataout AND NOT(niOl0il1i); + wire_n10O00l_dataout <= wire_nlll0lli_q(118) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(86); + wire_n10O00li_dataout <= wire_n10O0l0O_dataout AND NOT(niOl0il1i); + wire_n10O00ll_dataout <= wire_n10O0lii_dataout AND NOT(niOl0il1i); + wire_n10O00lO_dataout <= wire_n10O0lil_dataout AND NOT(niOl0il1i); + wire_n10O00O_dataout <= wire_nlll0lli_q(119) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(87); + wire_n10O00Oi_dataout <= wire_n10O0liO_dataout AND NOT(niOl0il1i); + wire_n10O00Ol_dataout <= wire_n10O0lli_dataout AND NOT(niOl0il1i); + wire_n10O00OO_dataout <= wire_n10O0lll_dataout AND NOT(niOl0il1i); + wire_n10O010i_dataout <= wire_n10O00OO_dataout AND NOT(niOl0il0l); + wire_n10O010l_dataout <= wire_n10O0i1i_dataout AND NOT(niOl0il0l); + wire_n10O010O_dataout <= wire_n10O0i1l_dataout AND NOT(niOl0il0l); + wire_n10O011i_dataout <= wire_n10O00lO_dataout AND NOT(niOl0il0l); + wire_n10O011l_dataout <= wire_n10O00Oi_dataout AND NOT(niOl0il0l); + wire_n10O011O_dataout <= wire_n10O00Ol_dataout AND NOT(niOl0il0l); + wire_n10O01i_dataout <= wire_nlll0lli_q(114) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(82); + wire_n10O01ii_dataout <= wire_n10O0i1O_dataout AND NOT(niOl0il0l); + wire_n10O01il_dataout <= wire_n10O0i0i_dataout AND NOT(niOl0il0l); + wire_n10O01iO_dataout <= wire_n10O0i0l_dataout OR niOl0il0l; + wire_n10O01l_dataout <= wire_nlll0lli_q(115) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(83); + wire_n10O01li_dataout <= wire_n10O0i0O_dataout AND NOT(niOl0il0l); + wire_n10O01ll_dataout <= wire_n10O0iii_dataout AND NOT(niOl0il0l); + wire_n10O01lO_dataout <= wire_n10O0iil_dataout AND NOT(niOl0il0l); + wire_n10O01O_dataout <= wire_nlll0lli_q(116) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(84); + wire_n10O01Oi_dataout <= wire_n10O0iiO_dataout AND NOT(niOl0il0l); + wire_n10O01Ol_dataout <= wire_n10O0ili_dataout AND NOT(niOl0il0l); + wire_n10O01OO_dataout <= wire_n10O0ill_dataout AND NOT(niOl0il0l); + wire_n10O0i0i_dataout <= wire_n10O0lOO_dataout AND NOT(niOl0il1i); + wire_n10O0i0l_dataout <= wire_n10O0O1i_dataout OR niOl0il1i; + wire_n10O0i0O_dataout <= wire_n10O0O1l_dataout AND NOT(niOl0il1i); + wire_n10O0i1i_dataout <= wire_n10O0llO_dataout AND NOT(niOl0il1i); + wire_n10O0i1l_dataout <= wire_n10O0lOi_dataout AND NOT(niOl0il1i); + wire_n10O0i1O_dataout <= wire_n10O0lOl_dataout AND NOT(niOl0il1i); + wire_n10O0ii_dataout <= wire_nlll0lli_q(120) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(88); + wire_n10O0iii_dataout <= wire_n10O0O1O_dataout AND NOT(niOl0il1i); + wire_n10O0iil_dataout <= wire_n10O0O0i_dataout AND NOT(niOl0il1i); + wire_n10O0iiO_dataout <= wire_n10O0O0l_dataout AND NOT(niOl0il1i); + wire_n10O0il_dataout <= wire_nlll0lli_q(121) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(89); + wire_n10O0ili_dataout <= wire_n10O0O0O_dataout AND NOT(niOl0il1i); + wire_n10O0ill_dataout <= wire_n10O0Oii_dataout AND NOT(niOl0il1i); + wire_n10O0ilO_dataout <= wire_n10O0Oil_dataout AND NOT(niOl0il1i); + wire_n10O0iO_dataout <= wire_nlll0lli_q(122) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(90); + wire_n10O0iOi_dataout <= n11O1O1O AND NOT(niOl0iiOO); + wire_n10O0iOl_dataout <= n11O0iOl AND NOT(niOl0iiOO); + wire_n10O0iOO_dataout <= n11O0iOO AND NOT(niOl0iiOO); + wire_n10O0l0i_dataout <= n11O0l0i AND NOT(niOl0iiOO); + wire_n10O0l0l_dataout <= n11O0l0l AND NOT(niOl0iiOO); + wire_n10O0l0O_dataout <= n11O0l0O AND NOT(niOl0iiOO); + wire_n10O0l1i_dataout <= n11O0l1i AND NOT(niOl0iiOO); + wire_n10O0l1l_dataout <= n11O0l1l AND NOT(niOl0iiOO); + wire_n10O0l1O_dataout <= n11O0l1O AND NOT(niOl0iiOO); + wire_n10O0li_dataout <= wire_nlll0lli_q(123) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(91); + wire_n10O0lii_dataout <= n11O0lii AND NOT(niOl0iiOO); + wire_n10O0lil_dataout <= n11O0lil AND NOT(niOl0iiOO); + wire_n10O0liO_dataout <= n11O0liO AND NOT(niOl0iiOO); + wire_n10O0ll_dataout <= wire_nlll0lli_q(124) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(92); + wire_n10O0lli_dataout <= n11O0lli AND NOT(niOl0iiOO); + wire_n10O0lll_dataout <= n11O0lll AND NOT(niOl0iiOO); + wire_n10O0llO_dataout <= n11O0llO AND NOT(niOl0iiOO); + wire_n10O0lO_dataout <= wire_nlll0lli_q(125) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(93); + wire_n10O0lOi_dataout <= n11O0lOi AND NOT(niOl0iiOO); + wire_n10O0lOl_dataout <= n11O0lOl AND NOT(niOl0iiOO); + wire_n10O0lOO_dataout <= n11O0lOO AND NOT(niOl0iiOO); + wire_n10O0O0i_dataout <= n11O0O0i AND NOT(niOl0iiOO); + wire_n10O0O0l_dataout <= n11O0O0l AND NOT(niOl0iiOO); + wire_n10O0O0O_dataout <= n11O0O0O AND NOT(niOl0iiOO); + wire_n10O0O1i_dataout <= n11O0O1i AND NOT(niOl0iiOO); + wire_n10O0O1l_dataout <= n11O0O1l AND NOT(niOl0iiOO); + wire_n10O0O1O_dataout <= n11O0O1O AND NOT(niOl0iiOO); + wire_n10O0Oi_dataout <= wire_nlll0lli_q(126) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(94); + wire_n10O0Oii_dataout <= n11O0Oii AND NOT(niOl0iiOO); + wire_n10O0Oil_dataout <= n11O0Oil OR niOl0iiOO; + wire_n10O0Ol_dataout <= wire_nlll0lli_q(127) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(95); + wire_n10O0OO_dataout <= wire_nlll0lli_q(64) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(96); + wire_n10O100i_dataout <= wire_n10O0l1i_dataout AND NOT(niOl0iiii); + wire_n10O100l_dataout <= wire_n10O0l1l_dataout AND NOT(niOl0iiii); + wire_n10O100O_dataout <= wire_n10O0l1O_dataout AND NOT(niOl0iiii); + wire_n10O101i_dataout <= n11O1O1O OR niOl0iili; + wire_n10O101l_dataout <= wire_n10O0iOl_dataout AND NOT(niOl0iiii); + wire_n10O101O_dataout <= wire_n10O0iOO_dataout AND NOT(niOl0iiii); + wire_n10O10i_dataout <= wire_nlll0lli_q(102) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(70); + wire_n10O10ii_dataout <= wire_n10O0l0i_dataout AND NOT(niOl0iiii); + wire_n10O10il_dataout <= wire_n10O0l0l_dataout AND NOT(niOl0iiii); + wire_n10O10iO_dataout <= wire_n10O0l0O_dataout AND NOT(niOl0iiii); + wire_n10O10l_dataout <= wire_nlll0lli_q(103) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(71); + wire_n10O10li_dataout <= wire_n10O0lii_dataout AND NOT(niOl0iiii); + wire_n10O10ll_dataout <= wire_n10O0lil_dataout AND NOT(niOl0iiii); + wire_n10O10lO_dataout <= wire_n10O0liO_dataout AND NOT(niOl0iiii); + wire_n10O10O_dataout <= wire_nlll0lli_q(104) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(72); + wire_n10O10Oi_dataout <= wire_n10O0lli_dataout AND NOT(niOl0iiii); + wire_n10O10Ol_dataout <= wire_n10O0lll_dataout AND NOT(niOl0iiii); + wire_n10O10OO_dataout <= wire_n10O0llO_dataout AND NOT(niOl0iiii); + wire_n10O110i_dataout <= wire_n10O10OO_dataout AND NOT(niOl0iili); + wire_n10O110l_dataout <= wire_n10O1i1i_dataout AND NOT(niOl0iili); + wire_n10O110O_dataout <= wire_n10O1i1l_dataout AND NOT(niOl0iili); + wire_n10O111i_dataout <= wire_n10O10lO_dataout AND NOT(niOl0iili); + wire_n10O111l_dataout <= wire_n10O10Oi_dataout AND NOT(niOl0iili); + wire_n10O111O_dataout <= wire_n10O10Ol_dataout AND NOT(niOl0iili); + wire_n10O11i_dataout <= wire_nlll0lli_q(99) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(67); + wire_n10O11ii_dataout <= wire_n10O1i1O_dataout OR niOl0iili; + wire_n10O11il_dataout <= wire_n10O1i0i_dataout AND NOT(niOl0iili); + wire_n10O11iO_dataout <= wire_n10O1i0l_dataout AND NOT(niOl0iili); + wire_n10O11l_dataout <= wire_nlll0lli_q(100) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(68); + wire_n10O11li_dataout <= wire_n10O1i0O_dataout AND NOT(niOl0iili); + wire_n10O11ll_dataout <= wire_n10O1iii_dataout AND NOT(niOl0iili); + wire_n10O11lO_dataout <= wire_n10O1iil_dataout AND NOT(niOl0iili); + wire_n10O11O_dataout <= wire_nlll0lli_q(101) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(69); + wire_n10O11Oi_dataout <= wire_n10O1iiO_dataout AND NOT(niOl0iili); + wire_n10O11Ol_dataout <= wire_n10O1ili_dataout AND NOT(niOl0iili); + wire_n10O11OO_dataout <= wire_n10O1ill_dataout AND NOT(niOl0iili); + wire_n10O1i0i_dataout <= wire_n10O0O1i_dataout AND NOT(niOl0iiii); + wire_n10O1i0l_dataout <= wire_n10O0O1l_dataout AND NOT(niOl0iiii); + wire_n10O1i0O_dataout <= wire_n10O0O1O_dataout AND NOT(niOl0iiii); + wire_n10O1i1i_dataout <= wire_n10O0lOi_dataout AND NOT(niOl0iiii); + wire_n10O1i1l_dataout <= wire_n10O0lOl_dataout OR niOl0iiii; + wire_n10O1i1O_dataout <= wire_n10O0lOO_dataout AND NOT(niOl0iiii); + wire_n10O1ii_dataout <= wire_nlll0lli_q(105) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(73); + wire_n10O1iii_dataout <= wire_n10O0O0i_dataout AND NOT(niOl0iiii); + wire_n10O1iil_dataout <= wire_n10O0O0l_dataout AND NOT(niOl0iiii); + wire_n10O1iiO_dataout <= wire_n10O0O0O_dataout AND NOT(niOl0iiii); + wire_n10O1il_dataout <= wire_nlll0lli_q(106) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(74); + wire_n10O1ili_dataout <= wire_n10O0Oii_dataout AND NOT(niOl0iiii); + wire_n10O1ill_dataout <= wire_n10O0Oil_dataout AND NOT(niOl0iiii); + wire_n10O1ilO_dataout <= n11O01li AND NOT(niOl0iiii); + wire_n10O1iO_dataout <= wire_nlll0lli_q(107) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(75); + wire_n10O1li_dataout <= wire_nlll0lli_q(108) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(76); + wire_n10O1ll_dataout <= wire_nlll0lli_q(109) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(77); + wire_n10O1lO_dataout <= wire_nlll0lli_q(110) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(78); + wire_n10O1O0i_dataout <= n11O00ii OR wire_w_lg_niOl0iiOi20998w(0); + wire_n10O1O0O_dataout <= wire_n10O001l_dataout AND NOT(niOl0il0l); + wire_n10O1O1i_dataout <= wire_n10O1O1O_dataout WHEN niOl0iiOl = '1' ELSE n11O00il; + wire_n10O1O1l_dataout <= wire_n10O1O0i_dataout WHEN niOl0iiOl = '1' ELSE n11O00ii; + wire_n10O1O1O_dataout <= n11O00il OR NOT(wire_w_lg_niOl0iiOi20998w(0)); + wire_n10O1Oi_dataout <= wire_nlll0lli_q(111) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(79); + wire_n10O1Oii_dataout <= wire_n10O001O_dataout AND NOT(niOl0il0l); + wire_n10O1Oil_dataout <= wire_n10O000i_dataout AND NOT(niOl0il0l); + wire_n10O1OiO_dataout <= wire_n10O000l_dataout AND NOT(niOl0il0l); + wire_n10O1Ol_dataout <= wire_nlll0lli_q(112) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(80); + wire_n10O1Oli_dataout <= wire_n10O000O_dataout AND NOT(niOl0il0l); + wire_n10O1Oll_dataout <= wire_n10O00ii_dataout AND NOT(niOl0il0l); + wire_n10O1OlO_dataout <= wire_n10O00il_dataout AND NOT(niOl0il0l); + wire_n10O1OO_dataout <= wire_nlll0lli_q(113) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(81); + wire_n10O1OOi_dataout <= wire_n10O00iO_dataout AND NOT(niOl0il0l); + wire_n10O1OOl_dataout <= wire_n10O00li_dataout AND NOT(niOl0il0l); + wire_n10O1OOO_dataout <= wire_n10O00ll_dataout AND NOT(niOl0il0l); + wire_n10Oi0i_dataout <= wire_nlll0lli_q(68) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(100); + wire_n10Oi0l_dataout <= wire_nlll0lli_q(69) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(101); + wire_n10Oi0O_dataout <= wire_nlll0lli_q(70) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(102); + wire_n10Oi1i_dataout <= wire_nlll0lli_q(65) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(97); + wire_n10Oi1l_dataout <= wire_nlll0lli_q(66) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(98); + wire_n10Oi1O_dataout <= wire_nlll0lli_q(67) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(99); + wire_n10Oii0i_dataout <= wire_n10OilOl_dataout AND NOT(niOl0ilOO); + wire_n10Oii0l_dataout <= wire_n10OilOO_dataout AND NOT(niOl0ilOO); + wire_n10Oii0O_dataout <= wire_n10OiO1i_dataout AND NOT(niOl0ilOO); + wire_n10Oiii_dataout <= wire_nlll0lli_q(71) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(103); + wire_n10Oiiii_dataout <= wire_n10OiO1l_dataout AND NOT(niOl0ilOO); + wire_n10Oiiil_dataout <= wire_n10OiO1O_dataout AND NOT(niOl0ilOO); + wire_n10OiiiO_dataout <= wire_n10OiO0i_dataout AND NOT(niOl0ilOO); + wire_n10Oiil_dataout <= wire_nlll0lli_q(72) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(104); + wire_n10Oiili_dataout <= wire_n10OiO0l_dataout AND NOT(niOl0ilOO); + wire_n10Oiill_dataout <= wire_n10OiO0O_dataout AND NOT(niOl0ilOO); + wire_n10OiilO_dataout <= wire_n10OiOii_dataout AND NOT(niOl0ilOO); + wire_n10OiiO_dataout <= wire_nlll0lli_q(73) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(105); + wire_n10OiiOi_dataout <= wire_n10OiOil_dataout AND NOT(niOl0ilOO); + wire_n10OiiOl_dataout <= wire_n10OiOiO_dataout AND NOT(niOl0ilOO); + wire_n10OiiOO_dataout <= wire_n10OiOli_dataout AND NOT(niOl0ilOO); + wire_n10Oil0i_dataout <= wire_n10OiOOl_dataout AND NOT(niOl0ilOO); + wire_n10Oil0l_dataout <= wire_n10OiOOO_dataout OR niOl0ilOO; + wire_n10Oil0O_dataout <= wire_n10Ol11i_dataout AND NOT(niOl0ilOO); + wire_n10Oil1i_dataout <= wire_n10OiOll_dataout AND NOT(niOl0ilOO); + wire_n10Oil1l_dataout <= wire_n10OiOlO_dataout AND NOT(niOl0ilOO); + wire_n10Oil1O_dataout <= wire_n10OiOOi_dataout AND NOT(niOl0ilOO); + wire_n10Oili_dataout <= wire_nlll0lli_q(74) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(106); + wire_n10Oilii_dataout <= wire_n10Ol11l_dataout AND NOT(niOl0ilOO); + wire_n10Oilil_dataout <= wire_n10Ol11O_dataout AND NOT(niOl0ilOO); + wire_n10OiliO_dataout <= wire_n10Ol10i_dataout AND NOT(niOl0ilOO); + wire_n10Oill_dataout <= wire_nlll0lli_q(75) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(107); + wire_n10Oilli_dataout <= wire_n10Ol10l_dataout AND NOT(niOl0ilOO); + wire_n10Oilll_dataout <= wire_n10Ol10O_dataout AND NOT(niOl0ilOO); + wire_n10OillO_dataout <= wire_n10Ol1ii_dataout AND NOT(niOl0ilOO); + wire_n10OilO_dataout <= wire_nlll0lli_q(76) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(108); + wire_n10OilOi_dataout <= wire_n10Ol1il_dataout AND NOT(niOl0ilOO); + wire_n10OilOl_dataout <= wire_n10Ol1iO_dataout AND NOT(niOl0illi); + wire_n10OilOO_dataout <= wire_n10Ol1li_dataout AND NOT(niOl0illi); + wire_n10OiO0i_dataout <= wire_n10Ol1Ol_dataout AND NOT(niOl0illi); + wire_n10OiO0l_dataout <= wire_n10Ol1OO_dataout AND NOT(niOl0illi); + wire_n10OiO0O_dataout <= wire_n10Ol01i_dataout AND NOT(niOl0illi); + wire_n10OiO1i_dataout <= wire_n10Ol1ll_dataout AND NOT(niOl0illi); + wire_n10OiO1l_dataout <= wire_n10Ol1lO_dataout AND NOT(niOl0illi); + wire_n10OiO1O_dataout <= wire_n10Ol1Oi_dataout AND NOT(niOl0illi); + wire_n10OiOi_dataout <= wire_nlll0lli_q(77) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(109); + wire_n10OiOii_dataout <= wire_n10Ol01l_dataout AND NOT(niOl0illi); + wire_n10OiOil_dataout <= wire_n10Ol01O_dataout AND NOT(niOl0illi); + wire_n10OiOiO_dataout <= wire_n10Ol00i_dataout AND NOT(niOl0illi); + wire_n10OiOl_dataout <= wire_nlll0lli_q(78) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(110); + wire_n10OiOli_dataout <= wire_n10Ol00l_dataout AND NOT(niOl0illi); + wire_n10OiOll_dataout <= wire_n10Ol00O_dataout AND NOT(niOl0illi); + wire_n10OiOlO_dataout <= wire_n10Ol0ii_dataout AND NOT(niOl0illi); + wire_n10OiOO_dataout <= wire_nlll0lli_q(79) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(111); + wire_n10OiOOi_dataout <= wire_n10Ol0il_dataout AND NOT(niOl0illi); + wire_n10OiOOl_dataout <= wire_n10Ol0iO_dataout AND NOT(niOl0illi); + wire_n10OiOOO_dataout <= wire_n10Ol0li_dataout OR niOl0illi; + wire_n10Ol00i_dataout <= n11O0liO AND NOT(niOl0ilil); + wire_n10Ol00l_dataout <= n11O0lli AND NOT(niOl0ilil); + wire_n10Ol00O_dataout <= n11O0lll AND NOT(niOl0ilil); + wire_n10Ol01i_dataout <= n11O0l0O AND NOT(niOl0ilil); + wire_n10Ol01l_dataout <= n11O0lii AND NOT(niOl0ilil); + wire_n10Ol01O_dataout <= n11O0lil AND NOT(niOl0ilil); + wire_n10Ol0i_dataout <= wire_nlll0lli_q(83) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(115); + wire_n10Ol0ii_dataout <= n11O0llO AND NOT(niOl0ilil); + wire_n10Ol0il_dataout <= n11O0lOi AND NOT(niOl0ilil); + wire_n10Ol0iO_dataout <= n11O0lOl AND NOT(niOl0ilil); + wire_n10Ol0l_dataout <= wire_nlll0lli_q(84) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(116); + wire_n10Ol0li_dataout <= n11O0lOO AND NOT(niOl0ilil); + wire_n10Ol0ll_dataout <= n11O0O1i AND NOT(niOl0ilil); + wire_n10Ol0lO_dataout <= n11O0O1l AND NOT(niOl0ilil); + wire_n10Ol0O_dataout <= wire_nlll0lli_q(85) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(117); + wire_n10Ol0Oi_dataout <= n11O0O1O AND NOT(niOl0ilil); + wire_n10Ol0Ol_dataout <= n11O0O0i AND NOT(niOl0ilil); + wire_n10Ol0OO_dataout <= n11O0O0l AND NOT(niOl0ilil); + wire_n10Ol10i_dataout <= wire_n10Ol0Ol_dataout AND NOT(niOl0illi); + wire_n10Ol10l_dataout <= wire_n10Ol0OO_dataout AND NOT(niOl0illi); + wire_n10Ol10O_dataout <= wire_n10Oli1i_dataout AND NOT(niOl0illi); + wire_n10Ol11i_dataout <= wire_n10Ol0ll_dataout AND NOT(niOl0illi); + wire_n10Ol11l_dataout <= wire_n10Ol0lO_dataout AND NOT(niOl0illi); + wire_n10Ol11O_dataout <= wire_n10Ol0Oi_dataout AND NOT(niOl0illi); + wire_n10Ol1i_dataout <= wire_nlll0lli_q(80) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(112); + wire_n10Ol1ii_dataout <= wire_n10Oli1l_dataout AND NOT(niOl0illi); + wire_n10Ol1il_dataout <= wire_n10Oli1O_dataout AND NOT(niOl0illi); + wire_n10Ol1iO_dataout <= n11O0iOl AND NOT(niOl0ilil); + wire_n10Ol1l_dataout <= wire_nlll0lli_q(81) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(113); + wire_n10Ol1li_dataout <= n11O0iOO AND NOT(niOl0ilil); + wire_n10Ol1ll_dataout <= n11O0l1i AND NOT(niOl0ilil); + wire_n10Ol1lO_dataout <= n11O0l1l AND NOT(niOl0ilil); + wire_n10Ol1O_dataout <= wire_nlll0lli_q(82) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(114); + wire_n10Ol1Oi_dataout <= n11O0l1O AND NOT(niOl0ilil); + wire_n10Ol1Ol_dataout <= n11O0l0i AND NOT(niOl0ilil); + wire_n10Ol1OO_dataout <= n11O0l0l AND NOT(niOl0ilil); + wire_n10Oli1i_dataout <= n11O0O0O AND NOT(niOl0ilil); + wire_n10Oli1l_dataout <= n11O0Oii AND NOT(niOl0ilil); + wire_n10Oli1O_dataout <= n11O0Oil OR niOl0ilil; + wire_n10Olii_dataout <= wire_nlll0lli_q(86) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(118); + wire_n10Olil_dataout <= wire_nlll0lli_q(87) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(119); + wire_n10OliO_dataout <= wire_nlll0lli_q(88) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(120); + wire_n10Olli_dataout <= wire_nlll0lli_q(89) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(121); + wire_n10Olll_dataout <= wire_nlll0lli_q(90) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(122); + wire_n10Ollli_dataout <= n11O1O0i WHEN niOl0iOil = '1' ELSE wire_n10OO1lO_dataout; + wire_n10Ollll_dataout <= niOl0iO0l AND NOT(niOl0iOil); + wire_n10OlllO_dataout <= n11O0i1i WHEN niOl0iOil = '1' ELSE wire_n10OOiil_dataout; + wire_n10OllO_dataout <= wire_nlll0lli_q(91) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(123); + wire_n10OllOi_dataout <= n11O0i0i WHEN niOl0iOil = '1' ELSE wire_n10OOiiO_dataout; + wire_n10OllOl_dataout <= n11O00OO WHEN niOl0iOil = '1' ELSE wire_n10OOili_dataout; + wire_n10OllOO_dataout <= n11O0i1l WHEN niOl0iOil = '1' ELSE wire_n10OOill_dataout; + wire_n10OlO0i_dataout <= wire_n10OO1OO_dataout AND NOT(niOl0iOil); + wire_n10OlO0l_dataout <= wire_n10OO01i_dataout AND NOT(niOl0iOil); + wire_n10OlO0O_dataout <= wire_n10OO01l_dataout AND NOT(niOl0iOil); + wire_n10OlO1i_dataout <= n11O0i1O WHEN niOl0iOil = '1' ELSE wire_n10OOilO_dataout; + wire_n10OlO1l_dataout <= wire_n10OO1Oi_dataout AND NOT(niOl0iOil); + wire_n10OlO1O_dataout <= wire_n10OO1Ol_dataout AND NOT(niOl0iOil); + wire_n10OlOi_dataout <= wire_nlll0lli_q(92) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(124); + wire_n10OlOii_dataout <= wire_n10OO01O_dataout AND NOT(niOl0iOil); + wire_n10OlOil_dataout <= wire_n10OO00i_dataout AND NOT(niOl0iOil); + wire_n10OlOiO_dataout <= wire_n10OO00l_dataout AND NOT(niOl0iOil); + wire_n10OlOl_dataout <= wire_nlll0lli_q(93) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(125); + wire_n10OlOli_dataout <= wire_n10OO00O_dataout OR niOl0iOil; + wire_n10OlOll_dataout <= wire_n10OO0ii_dataout AND NOT(niOl0iOil); + wire_n10OlOlO_dataout <= wire_n10OO0il_dataout AND NOT(niOl0iOil); + wire_n10OlOO_dataout <= wire_nlll0lli_q(94) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(126); + wire_n10OlOOi_dataout <= wire_n10OO0iO_dataout AND NOT(niOl0iOil); + wire_n10OlOOl_dataout <= wire_n10OO0li_dataout AND NOT(niOl0iOil); + wire_n10OlOOO_dataout <= wire_n10OO0ll_dataout AND NOT(niOl0iOil); + wire_n10OO00i_dataout <= wire_n10OOl0i_dataout AND NOT(niOl0iO0l); + wire_n10OO00l_dataout <= wire_n10OOl0l_dataout OR niOl0iO0l; + wire_n10OO00O_dataout <= wire_n10OOl0O_dataout AND NOT(niOl0iO0l); + wire_n10OO01i_dataout <= wire_n10OOl1i_dataout AND NOT(niOl0iO0l); + wire_n10OO01l_dataout <= wire_n10OOl1l_dataout AND NOT(niOl0iO0l); + wire_n10OO01O_dataout <= wire_n10OOl1O_dataout AND NOT(niOl0iO0l); + wire_n10OO0ii_dataout <= wire_n10OOlii_dataout AND NOT(niOl0iO0l); + wire_n10OO0il_dataout <= wire_n10OOlil_dataout AND NOT(niOl0iO0l); + wire_n10OO0iO_dataout <= wire_n10OOliO_dataout AND NOT(niOl0iO0l); + wire_n10OO0li_dataout <= wire_n10OOlli_dataout AND NOT(niOl0iO0l); + wire_n10OO0ll_dataout <= wire_n10OOlll_dataout AND NOT(niOl0iO0l); + wire_n10OO0lO_dataout <= wire_n10OOllO_dataout AND NOT(niOl0iO0l); + wire_n10OO0O_dataout <= wire_n1i0l1i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1Oii; + wire_n10OO0Oi_dataout <= wire_n10OOlOi_dataout AND NOT(niOl0iO0l); + wire_n10OO0Ol_dataout <= wire_n10OOlOl_dataout AND NOT(niOl0iO0l); + wire_n10OO0OO_dataout <= wire_n10OOlOO_dataout AND NOT(niOl0iO0l); + wire_n10OO10i_dataout <= wire_n10OO0OO_dataout AND NOT(niOl0iOil); + wire_n10OO10l_dataout <= wire_n10OOi1i_dataout AND NOT(niOl0iOil); + wire_n10OO10O_dataout <= wire_n10OOi1l_dataout AND NOT(niOl0iOil); + wire_n10OO11i_dataout <= wire_n10OO0lO_dataout AND NOT(niOl0iOil); + wire_n10OO11l_dataout <= wire_n10OO0Oi_dataout AND NOT(niOl0iOil); + wire_n10OO11O_dataout <= wire_n10OO0Ol_dataout AND NOT(niOl0iOil); + wire_n10OO1i_dataout <= wire_nlll0lli_q(95) WHEN niOO00ilO = '1' ELSE wire_nlll0lli_q(127); + wire_n10OO1ii_dataout <= wire_n10OOi1O_dataout AND NOT(niOl0iOil); + wire_n10OO1il_dataout <= wire_n10OOi0i_dataout AND NOT(niOl0iOil); + wire_n10OO1iO_dataout <= wire_n10OOi0l_dataout AND NOT(niOl0iOil); + wire_n10OO1li_dataout <= wire_n10OOi0O_dataout AND NOT(niOl0iOil); + wire_n10OO1ll_dataout <= wire_n10OOiii_dataout AND NOT(niOl0iOil); + wire_n10OO1lO_dataout <= wire_n1l10lli_dataout WHEN niOl0iO0l = '1' ELSE n11O1O0i; + wire_n10OO1Oi_dataout <= wire_n10OOiOi_dataout AND NOT(niOl0iO0l); + wire_n10OO1Ol_dataout <= wire_n10OOiOl_dataout AND NOT(niOl0iO0l); + wire_n10OO1OO_dataout <= wire_n10OOiOO_dataout AND NOT(niOl0iO0l); + wire_n10OOi0i_dataout <= wire_n10OOO0i_dataout AND NOT(niOl0iO0l); + wire_n10OOi0l_dataout <= wire_n10OOO0l_dataout AND NOT(niOl0iO0l); + wire_n10OOi0O_dataout <= wire_n10OOO0O_dataout AND NOT(niOl0iO0l); + wire_n10OOi1i_dataout <= wire_n10OOO1i_dataout AND NOT(niOl0iO0l); + wire_n10OOi1l_dataout <= wire_n10OOO1l_dataout AND NOT(niOl0iO0l); + wire_n10OOi1O_dataout <= wire_n10OOO1O_dataout AND NOT(niOl0iO0l); + wire_n10OOii_dataout <= wire_n1i0l1l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1Oil; + wire_n10OOiii_dataout <= wire_n10OOOii_dataout AND NOT(niOl0iO0l); + wire_n10OOiil_dataout <= wire_n1i1100i_dataout WHEN niOl0iO0l = '1' ELSE n11O0i1i; + wire_n10OOiiO_dataout <= wire_n1i1100l_dataout WHEN niOl0iO0l = '1' ELSE n11O0i0i; + wire_n10OOil_dataout <= wire_n1i0l1O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1OiO; + wire_n10OOili_dataout <= nlOliiO0i WHEN niOl0iO0l = '1' ELSE n11O00OO; + wire_n10OOill_dataout <= nlOliO0iO WHEN niOl0iO0l = '1' ELSE n11O0i1l; + wire_n10OOilO_dataout <= nlOliO0li WHEN niOl0iO0l = '1' ELSE n11O0i1O; + wire_n10OOiO_dataout <= wire_n1i0l0i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1Oli; + wire_n10OOiOi_dataout <= wire_n10OOOil_dataout AND NOT(niOl0iO1l); + wire_n10OOiOl_dataout <= wire_n10OOOiO_dataout AND NOT(niOl0iO1l); + wire_n10OOiOO_dataout <= wire_n10OOOli_dataout AND NOT(niOl0iO1l); + wire_n10OOl0i_dataout <= wire_n10OOOOl_dataout AND NOT(niOl0iO1l); + wire_n10OOl0l_dataout <= wire_n10OOOOO_dataout AND NOT(niOl0iO1l); + wire_n10OOl0O_dataout <= wire_n1i1111i_dataout AND NOT(niOl0iO1l); + wire_n10OOl1i_dataout <= wire_n10OOOll_dataout AND NOT(niOl0iO1l); + wire_n10OOl1l_dataout <= wire_n10OOOlO_dataout AND NOT(niOl0iO1l); + wire_n10OOl1O_dataout <= wire_n10OOOOi_dataout AND NOT(niOl0iO1l); + wire_n10OOli_dataout <= wire_n1i0l0l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1Oll; + wire_n10OOlii_dataout <= wire_n1i1111l_dataout AND NOT(niOl0iO1l); + wire_n10OOlil_dataout <= wire_n1i1111O_dataout AND NOT(niOl0iO1l); + wire_n10OOliO_dataout <= wire_n1i1110i_dataout AND NOT(niOl0iO1l); + wire_n10OOll_dataout <= wire_n1i0l0O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1OlO; + wire_n10OOlli_dataout <= wire_n1i1110l_dataout AND NOT(niOl0iO1l); + wire_n10OOlll_dataout <= wire_n1i1110O_dataout AND NOT(niOl0iO1l); + wire_n10OOllO_dataout <= wire_n1i111ii_dataout AND NOT(niOl0iO1l); + wire_n10OOlO_dataout <= wire_n1i0lii_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1OOi; + wire_n10OOlOi_dataout <= wire_n1i111il_dataout AND NOT(niOl0iO1l); + wire_n10OOlOl_dataout <= wire_n1i111iO_dataout AND NOT(niOl0iO1l); + wire_n10OOlOO_dataout <= wire_n1i111li_dataout AND NOT(niOl0iO1l); + wire_n10OOO0i_dataout <= wire_n1i111Ol_dataout AND NOT(niOl0iO1l); + wire_n10OOO0l_dataout <= wire_n1i111OO_dataout AND NOT(niOl0iO1l); + wire_n10OOO0O_dataout <= wire_n1i1101i_dataout AND NOT(niOl0iO1l); + wire_n10OOO1i_dataout <= wire_n1i111ll_dataout OR niOl0iO1l; + wire_n10OOO1l_dataout <= wire_n1i111lO_dataout AND NOT(niOl0iO1l); + wire_n10OOO1O_dataout <= wire_n1i111Oi_dataout AND NOT(niOl0iO1l); + wire_n10OOOi_dataout <= wire_n1i0lil_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1OOl; + wire_n10OOOii_dataout <= wire_n1i1101l_dataout AND NOT(niOl0iO1l); + wire_n10OOOil_dataout <= n11O0iOl AND NOT(niOl0iO1O); + wire_n10OOOiO_dataout <= n11O0iOO AND NOT(niOl0iO1O); + wire_n10OOOl_dataout <= wire_n1i0liO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1OOO; + wire_n10OOOli_dataout <= n11O0l1i AND NOT(niOl0iO1O); + wire_n10OOOll_dataout <= n11O0l1l AND NOT(niOl0iO1O); + wire_n10OOOlO_dataout <= n11O0l1O AND NOT(niOl0iO1O); + wire_n10OOOO_dataout <= wire_n1i0lli_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi011i; + wire_n10OOOOi_dataout <= n11O0l0i AND NOT(niOl0iO1O); + wire_n10OOOOl_dataout <= n11O0l0l AND NOT(niOl0iO1O); + wire_n10OOOOO_dataout <= n11O0l0O AND NOT(niOl0iO1O); + wire_n110000i_dataout <= wire_n110Olll_dataout WHEN n11O0O1O = '1' ELSE wire_n11000OO_dataout; + wire_n110000l_dataout <= wire_n110OllO_dataout WHEN n11O0O1O = '1' ELSE wire_n1100i1i_dataout; + wire_n110000O_dataout <= wire_n110OlOi_dataout WHEN n11O0O1O = '1' ELSE wire_n1100i1l_dataout; + wire_n110001i_dataout <= wire_n1100ili_dataout AND NOT(n11O0O1O); + wire_n110001l_dataout <= wire_n1100ill_dataout AND NOT(n11O0O1O); + wire_n110001O_dataout <= wire_n1100ilO_dataout AND NOT(n11O0O1O); + wire_n11000i_dataout <= nlOi11lO WHEN niOO00iil = '1' ELSE nlOi011O; + wire_n11000ii_dataout <= wire_n110OlOl_dataout WHEN n11O0O1O = '1' ELSE wire_n1100i1O_dataout; + wire_n11000il_dataout <= wire_n110OlOO_dataout WHEN n11O0O1O = '1' ELSE wire_n1100i0i_dataout; + wire_n11000iO_dataout <= wire_n110OO1i_dataout WHEN n11O0O1O = '1' ELSE wire_n1100i0l_dataout; + wire_n11000l_dataout <= nlOi11Oi WHEN niOO00iil = '1' ELSE nlOi010i; + wire_n11000li_dataout <= wire_n110OO1l_dataout WHEN n11O0O1O = '1' ELSE wire_n1100i0O_dataout; + wire_n11000ll_dataout <= wire_n110OO1O_dataout WHEN n11O0O1O = '1' ELSE wire_n1100iii_dataout; + wire_n11000lO_dataout <= wire_nlOO1iO1O_dataout WHEN n11O0O1O = '1' ELSE wire_n1100iOi_dataout; + wire_n11000O_dataout <= nlOi11Ol WHEN niOO00iil = '1' ELSE nlOi010l; + wire_n11000Oi_dataout <= wire_nlOO1iO0i_dataout WHEN n11O0O1O = '1' ELSE wire_n1100iOl_dataout; + wire_n11000Ol_dataout <= wire_nlOO1iO0l_dataout WHEN n11O0O1O = '1' ELSE wire_n1100iOO_dataout; + wire_n11000OO_dataout <= wire_n110l1lO_dataout WHEN niOl010ll = '1' ELSE wire_n1100l1i_dataout; + wire_n110010i_dataout <= wire_n110001l_dataout AND NOT(n11O0Oii); + wire_n110010l_dataout <= wire_n110001O_dataout AND NOT(n11O0Oii); + wire_n110010O_dataout <= wire_n110000i_dataout OR n11O0Oii; + wire_n110011i_dataout <= wire_n11001Ol_dataout AND NOT(n11O0Oii); + wire_n110011l_dataout <= wire_n11001OO_dataout AND NOT(n11O0Oii); + wire_n110011O_dataout <= wire_n110001i_dataout AND NOT(n11O0Oii); + wire_n11001i_dataout <= nlOi11iO WHEN niOO00iil = '1' ELSE nlOi1OOO; + wire_n11001ii_dataout <= wire_n110000l_dataout OR n11O0Oii; + wire_n11001il_dataout <= wire_n110000O_dataout OR n11O0Oii; + wire_n11001iO_dataout <= wire_n11000ii_dataout OR n11O0Oii; + wire_n11001l_dataout <= nlOi11li WHEN niOO00iil = '1' ELSE nlOi011i; + wire_n11001li_dataout <= wire_n11000il_dataout OR n11O0Oii; + wire_n11001ll_dataout <= wire_n11000iO_dataout OR n11O0Oii; + wire_n11001lO_dataout <= wire_n11000li_dataout OR n11O0Oii; + wire_n11001O_dataout <= nlOi11ll WHEN niOO00iil = '1' ELSE nlOi011l; + wire_n11001Oi_dataout <= wire_n11000ll_dataout OR n11O0Oii; + wire_n11001Ol_dataout <= wire_n1100iil_dataout AND NOT(n11O0O1O); + wire_n11001OO_dataout <= wire_n1100iiO_dataout AND NOT(n11O0O1O); + wire_n1100i0i_dataout <= wire_n110l01i_dataout WHEN niOl010ll = '1' ELSE wire_n1100l0l_dataout; + wire_n1100i0l_dataout <= wire_n110l01l_dataout WHEN niOl010ll = '1' ELSE wire_n1100l0O_dataout; + wire_n1100i0O_dataout <= wire_n110l01O_dataout WHEN niOl010ll = '1' ELSE wire_n1100lii_dataout; + wire_n1100i1i_dataout <= wire_n110l1Oi_dataout WHEN niOl010ll = '1' ELSE wire_n1100l1l_dataout; + wire_n1100i1l_dataout <= wire_n110l1Ol_dataout WHEN niOl010ll = '1' ELSE wire_n1100l1O_dataout; + wire_n1100i1O_dataout <= wire_n110l1OO_dataout WHEN niOl010ll = '1' ELSE wire_n1100l0i_dataout; + wire_n1100ii_dataout <= nlOi11OO WHEN niOO00iil = '1' ELSE nlOi010O; + wire_n1100iii_dataout <= wire_n110l00i_dataout WHEN niOl010ll = '1' ELSE wire_n1100lil_dataout; + wire_n1100iil_dataout <= wire_n110l00l_dataout WHEN niOl010ll = '1' ELSE wire_n1100liO_dataout; + wire_n1100iiO_dataout <= wire_n110l00O_dataout WHEN niOl010ll = '1' ELSE wire_n1100lOi_dataout; + wire_n1100il_dataout <= nlOi101i WHEN niOO00iil = '1' ELSE nlOi01ii; + wire_n1100ili_dataout <= wire_n110l0ii_dataout WHEN niOl010ll = '1' ELSE wire_n1100lOl_dataout; + wire_n1100ill_dataout <= wire_n110l0il_dataout WHEN niOl010ll = '1' ELSE wire_n1100lOO_dataout; + wire_n1100ilO_dataout <= wire_n110l0iO_dataout WHEN niOl010ll = '1' ELSE wire_n1100O1i_dataout; + wire_n1100iO_dataout <= nlOi101l WHEN niOO00iil = '1' ELSE nlOi01il; + wire_n1100iOi_dataout <= wire_nlOO1iO1O_dataout WHEN niOl010ll = '1' ELSE wire_n1100lli_dataout; + wire_n1100iOl_dataout <= wire_nlOO1iO0i_dataout WHEN niOl010ll = '1' ELSE wire_n1100lll_dataout; + wire_n1100iOO_dataout <= wire_nlOO1iO0l_dataout WHEN niOl010ll = '1' ELSE wire_n1100llO_dataout; + wire_n1100l0i_dataout <= wire_n1100O0l_dataout WHEN niOl011lO = '1' ELSE n1101l0l; + wire_n1100l0l_dataout <= wire_n1100O0O_dataout WHEN niOl011lO = '1' ELSE n1101l0O; + wire_n1100l0O_dataout <= wire_n1100Oii_dataout WHEN niOl011lO = '1' ELSE n1101lii; + wire_n1100l1i_dataout <= wire_n1100O1l_dataout WHEN niOl011lO = '1' ELSE n1101l1l; + wire_n1100l1l_dataout <= wire_n1100O1O_dataout WHEN niOl011lO = '1' ELSE n1101l1O; + wire_n1100l1O_dataout <= wire_n1100O0i_dataout WHEN niOl011lO = '1' ELSE n1101l0i; + wire_n1100li_dataout <= nlOi101O WHEN niOO00iil = '1' ELSE nlOi01iO; + wire_n1100lii_dataout <= wire_n1100Oil_dataout WHEN niOl011lO = '1' ELSE n1101lil; + wire_n1100lil_dataout <= wire_n1100OiO_dataout WHEN niOl011lO = '1' ELSE n1101liO; + wire_n1100liO_dataout <= wire_w_lg_niOl011Oi23591w(0) WHEN niOl011lO = '1' ELSE n1101iiO; + wire_n1100ll_dataout <= nlOi100i WHEN niOO00iil = '1' ELSE nlOi01li; + wire_n1100lli_dataout <= wire_nlOO1iO1O_dataout WHEN niOl011lO = '1' ELSE n1101ili; + wire_n1100lll_dataout <= wire_nlOO1iO0i_dataout WHEN niOl011lO = '1' ELSE n1101ill; + wire_n1100llO_dataout <= wire_nlOO1iO0l_dataout WHEN niOl011lO = '1' ELSE n1101ilO; + wire_n1100lO_dataout <= nlOi100l WHEN niOO00iil = '1' ELSE nlOi01ll; + wire_n1100lOi_dataout <= niOl011Ol WHEN niOl011lO = '1' ELSE n1101iOi; + wire_n1100lOl_dataout <= wire_nlOO1iO1O_dataout WHEN niOl011lO = '1' ELSE n1101iOl; + wire_n1100lOO_dataout <= wire_nlOO1iO0i_dataout WHEN niOl011lO = '1' ELSE n1101iOO; + wire_n1100O0i_dataout <= wire_n110illi_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100OlO_dataout; + wire_n1100O0l_dataout <= wire_n110illl_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100OOi_dataout; + wire_n1100O0O_dataout <= wire_n110illO_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100OOl_dataout; + wire_n1100O1i_dataout <= wire_nlOO1iO0l_dataout WHEN niOl011lO = '1' ELSE n1101l1i; + wire_n1100O1l_dataout <= wire_n110ilil_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100Oli_dataout; + wire_n1100O1O_dataout <= wire_n110iliO_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100Oll_dataout; + wire_n1100Oi_dataout <= nlOi100O WHEN niOO00iil = '1' ELSE nlOi01lO; + wire_n1100Oii_dataout <= wire_n110ilOi_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100OOO_dataout; + wire_n1100Oil_dataout <= wire_n110ilOl_dataout WHEN niOl0ilOl = '1' ELSE wire_n110i11i_dataout; + wire_n1100OiO_dataout <= wire_n110ilOO_dataout WHEN niOl0ilOl = '1' ELSE wire_n110i11l_dataout; + wire_n1100Ol_dataout <= nlOi10ii WHEN niOO00iil = '1' ELSE nlOi01Oi; + wire_n1100Oli_dataout <= wire_w_lg_w_k_gbl_hip_range23582w23621w(0) WHEN niOl0ilOi = '1' ELSE wire_n110i11O_dataout; + wire_n1100Oll_dataout <= wire_n110i10i_dataout AND NOT(niOl0ilOi); + wire_n1100OlO_dataout <= wire_n110i10l_dataout OR niOl0ilOi; + wire_n1100OO_dataout <= nlOi10il WHEN niOO00iil = '1' ELSE nlOi01Ol; + wire_n1100OOi_dataout <= wire_n110i10O_dataout OR niOl0ilOi; + wire_n1100OOl_dataout <= wire_n110i1ii_dataout OR niOl0ilOi; + wire_n1100OOO_dataout <= wire_n110i1il_dataout OR niOl0ilOi; + wire_n11010i_dataout <= wire_n11iO1l_dataout WHEN niOO00iiO = '1' ELSE wire_n110OiO_dataout; + wire_n11010l_dataout <= wire_n11iO1O_dataout WHEN niOO00iiO = '1' ELSE wire_n110Oli_dataout; + wire_n11010O_dataout <= wire_n11iO0i_dataout WHEN niOO00iiO = '1' ELSE wire_n110Oll_dataout; + wire_n11011i_dataout <= wire_n11ilOl_dataout WHEN niOO00iiO = '1' ELSE wire_n110O0O_dataout; + wire_n11011ii_dataout <= ((n11O0l1l AND niOl0111l) AND nlOll0O0i) OR (niOl01i1l AND (((wire_n11010iO_w_lg_w_lg_o23823w23824w(0) OR wire_n110100l_w_lg_w_lg_o23825w23826w(0)) OR (niOl011ii AND niOli1iOO)) OR niOl0110i)); + wire_n11011l_dataout <= wire_n11ilOO_dataout WHEN niOO00iiO = '1' ELSE wire_n110Oii_dataout; + wire_n11011O_dataout <= wire_n11iO1i_dataout WHEN niOO00iiO = '1' ELSE wire_n110Oil_dataout; + wire_n1101i0l_dataout <= (wire_nlOi00l1O_dataout OR nlOOOl00i) AND NOT((n11O0lil AND (n11Oi1ll OR n11Oi1ii))); + wire_n1101ii_dataout <= nlOi1O0l WHEN niOO00iil = '1' ELSE wire_n1l1OOl_dataout; + wire_n1101il_dataout <= nlOi111i WHEN niOO00iil = '1' ELSE nlOi1Oii; + wire_n1101iO_dataout <= nlOi111l WHEN niOO00iil = '1' ELSE nlOi1Oil; + wire_n1101li_dataout <= nlOi111O WHEN niOO00iil = '1' ELSE nlOi1OiO; + wire_n1101ll_dataout <= nlOi110i WHEN niOO00iil = '1' ELSE nlOi1Oli; + wire_n1101lll_dataout <= wire_n110OO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101llO_dataout <= wire_n110011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101lO_dataout <= nlOi110l WHEN niOO00iil = '1' ELSE nlOi1Oll; + wire_n1101lOi_dataout <= wire_n1101OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101lOl_dataout <= wire_n1101OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101lOO_dataout <= wire_n1101OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101O0i_dataout <= wire_n110010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101O0l_dataout <= wire_n110010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101O0O_dataout <= wire_n11001ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101O1i_dataout <= wire_n110011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101O1l_dataout <= wire_n110011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101O1O_dataout <= wire_n110010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101Oi_dataout <= nlOi110O WHEN niOO00iil = '1' ELSE nlOi1OlO; + wire_n1101Oii_dataout <= wire_n11001il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101Oil_dataout <= wire_n11001iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101OiO_dataout <= wire_n11001li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101Ol_dataout <= nlOi11ii WHEN niOO00iil = '1' ELSE nlOi1OOi; + wire_n1101Oli_dataout <= wire_n11001ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101Oll_dataout <= wire_n11001lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101OlO_dataout <= wire_n11001Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1101OO_dataout <= nlOi11il WHEN niOO00iil = '1' ELSE nlOi1OOl; + wire_n1101OOi_dataout <= wire_nlOO1iO1O_dataout WHEN n11O0Oii = '1' ELSE wire_n11000lO_dataout; + wire_n1101OOl_dataout <= wire_nlOO1iO0i_dataout WHEN n11O0Oii = '1' ELSE wire_n11000Oi_dataout; + wire_n1101OOO_dataout <= wire_nlOO1iO0l_dataout WHEN n11O0Oii = '1' ELSE wire_n11000Ol_dataout; + wire_n110i00i_dataout <= wire_n110i0lO_dataout OR niOl011OO; + wire_n110i00l_dataout <= wire_n110i0Oi_dataout OR niOl011OO; + wire_n110i00O_dataout <= wire_n110i0Ol_dataout OR niOl011OO; + wire_n110i01i_dataout <= wire_n110i0iO_dataout WHEN niOl0illl = '1' ELSE n1101lii; + wire_n110i01l_dataout <= wire_n110i0li_dataout WHEN niOl0illl = '1' ELSE n1101lil; + wire_n110i01O_dataout <= wire_n110i0ll_dataout WHEN niOl0illl = '1' ELSE n1101liO; + wire_n110i0i_dataout <= nlOi10lO WHEN niOO00iil = '1' ELSE nlOi001O; + wire_n110i0ii_dataout <= wire_n110i0OO_dataout OR niOl011OO; + wire_n110i0il_dataout <= wire_n110ii1i_dataout OR niOl011OO; + wire_n110i0iO_dataout <= wire_n110ii1l_dataout OR niOl011OO; + wire_n110i0l_dataout <= nlOi10Oi WHEN niOO00iil = '1' ELSE nlOi000i; + wire_n110i0li_dataout <= wire_n110ii1O_dataout OR niOl011OO; + wire_n110i0ll_dataout <= wire_n110ii0i_dataout AND NOT(niOl011OO); + wire_n110i0lO_dataout <= wire_n110ii0l_dataout OR niOl0101i; + wire_n110i0O_dataout <= nlOi10Ol WHEN niOO00iil = '1' ELSE nlOi000l; + wire_n110i0Oi_dataout <= wire_n110ii0O_dataout OR niOl0101i; + wire_n110i0Ol_dataout <= wire_n110iiii_dataout OR niOl0101i; + wire_n110i0OO_dataout <= wire_n110iiil_dataout OR niOl0101i; + wire_n110i10i_dataout <= wire_n110il1l_dataout WHEN niOl0illO = '1' ELSE wire_n110i1lO_dataout; + wire_n110i10l_dataout <= wire_n110il1O_dataout WHEN niOl0illO = '1' ELSE wire_n110i1Oi_dataout; + wire_n110i10O_dataout <= wire_n110i1Ol_dataout AND NOT(niOl0illO); + wire_n110i11i_dataout <= wire_n110i1iO_dataout OR niOl0ilOi; + wire_n110i11l_dataout <= wire_n110i1li_dataout OR niOl0ilOi; + wire_n110i11O_dataout <= wire_n110il1l_dataout WHEN niOl0illO = '1' ELSE wire_n110i1ll_dataout; + wire_n110i1i_dataout <= nlOi10iO WHEN niOO00iil = '1' ELSE nlOi01OO; + wire_n110i1ii_dataout <= wire_n110i1OO_dataout OR niOl0illO; + wire_n110i1il_dataout <= wire_n110i01i_dataout OR niOl0illO; + wire_n110i1iO_dataout <= wire_n110i01l_dataout OR niOl0illO; + wire_n110i1l_dataout <= nlOi10li WHEN niOO00iil = '1' ELSE nlOi001i; + wire_n110i1li_dataout <= wire_n110i01O_dataout OR niOl0illO; + wire_n110i1ll_dataout <= wire_n110i00i_dataout WHEN niOl0illl = '1' ELSE n1101l1l; + wire_n110i1lO_dataout <= wire_n110i00l_dataout WHEN niOl0illl = '1' ELSE n1101l1O; + wire_n110i1O_dataout <= nlOi10ll WHEN niOO00iil = '1' ELSE nlOi001l; + wire_n110i1Oi_dataout <= wire_n110i00O_dataout WHEN niOl0illl = '1' ELSE n1101l0i; + wire_n110i1Ol_dataout <= wire_n110i0ii_dataout WHEN niOl0illl = '1' ELSE n1101l0l; + wire_n110i1OO_dataout <= wire_n110i0il_dataout WHEN niOl0illl = '1' ELSE n1101l0O; + wire_n110ii0i_dataout <= wire_n110iilO_dataout AND NOT(niOl0101i); + wire_n110ii0l_dataout <= n1101l1l OR niOl011li; + wire_n110ii0O_dataout <= n1101l1O OR niOl011li; + wire_n110ii1i_dataout <= wire_n110iiiO_dataout OR niOl0101i; + wire_n110ii1l_dataout <= wire_n110iili_dataout OR niOl0101i; + wire_n110ii1O_dataout <= k_gbl_hip(43) WHEN niOl0101i = '1' ELSE wire_n110iill_dataout; + wire_n110iii_dataout <= nlOi10OO WHEN niOO00iil = '1' ELSE nlOi000O; + wire_n110iiii_dataout <= n1101l0i OR niOl011li; + wire_n110iiil_dataout <= n1101l0l OR niOl011li; + wire_n110iiiO_dataout <= n1101l0O AND NOT(niOl011li); + wire_n110iil_dataout <= nlOi1i1i WHEN niOO00iil = '1' ELSE nlOi00ii; + wire_n110iili_dataout <= n1101lii AND NOT(niOl011li); + wire_n110iill_dataout <= n1101lil AND NOT(niOl011li); + wire_n110iilO_dataout <= n1101liO AND NOT(niOl011li); + wire_n110iiO_dataout <= nlOi1i1l WHEN niOO00iil = '1' ELSE nlOi00il; + wire_n110il0i_dataout <= k_gbl_hip(43) AND niOl0101l; + wire_n110il1l_dataout <= niOl0101l OR niOl0100l; + wire_n110il1O_dataout <= wire_n110il0i_dataout OR niOl0100l; + wire_n110ili_dataout <= nlOi1i1O WHEN niOO00iil = '1' ELSE nlOi00iO; + wire_n110ilil_dataout <= wire_n110iO1i_dataout AND NOT(niOl0101l); + wire_n110iliO_dataout <= wire_n110iO1l_dataout OR niOl0101l; + wire_n110ill_dataout <= nlOi1i0i WHEN niOO00iil = '1' ELSE nlOi00li; + wire_n110illi_dataout <= wire_n110iO1O_dataout OR niOl0101l; + wire_n110illl_dataout <= wire_n110iO0i_dataout OR niOl0101l; + wire_n110illO_dataout <= wire_n110iO0l_dataout OR niOl0101l; + wire_n110ilO_dataout <= nlOi1i0l WHEN niOO00iil = '1' ELSE nlOi00ll; + wire_n110ilOi_dataout <= wire_n110iO0O_dataout OR niOl0101l; + wire_n110ilOl_dataout <= wire_n110iOii_dataout OR niOl0101l; + wire_n110ilOO_dataout <= wire_n110iOil_dataout OR niOl0101l; + wire_n110iO0i_dataout <= wire_n110iOlO_dataout OR niOl0100l; + wire_n110iO0l_dataout <= wire_n110iOOi_dataout OR niOl0100l; + wire_n110iO0O_dataout <= wire_n110iOOl_dataout OR niOl0100l; + wire_n110iO1i_dataout <= wire_n110iOiO_dataout AND NOT(niOl0100l); + wire_n110iO1l_dataout <= k_gbl_hip(43) WHEN niOl0100l = '1' ELSE wire_n110iOli_dataout; + wire_n110iO1O_dataout <= wire_n110iOll_dataout OR niOl0100l; + wire_n110iOi_dataout <= nlOi1i0O WHEN niOO00iil = '1' ELSE nlOi00lO; + wire_n110iOii_dataout <= wire_n110iOOO_dataout OR niOl0100l; + wire_n110iOil_dataout <= wire_n110l11i_dataout OR niOl0100l; + wire_n110iOiO_dataout <= n1101l1l AND NOT(niOl011ll); + wire_n110iOl_dataout <= nlOi1iii WHEN niOO00iil = '1' ELSE nlOi00Oi; + wire_n110iOli_dataout <= n1101l1O AND NOT(niOl011ll); + wire_n110iOll_dataout <= n1101l0i AND NOT(niOl011ll); + wire_n110iOlO_dataout <= n1101l0l AND NOT(niOl011ll); + wire_n110iOO_dataout <= nlOi1iil WHEN niOO00iil = '1' ELSE nlOi00Ol; + wire_n110iOOi_dataout <= n1101l0O OR niOl011ll; + wire_n110iOOl_dataout <= n1101lii OR niOl011ll; + wire_n110iOOO_dataout <= n1101lil OR niOl011ll; + wire_n110l00i_dataout <= wire_n110O10l_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110li1l_dataout; + wire_n110l00l_dataout <= wire_n110Oi0i_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_w_lg_niOl011Oi23591w(0); + wire_n110l00O_dataout <= wire_n110Oi0l_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE niOl011Ol; + wire_n110l01i_dataout <= wire_n110O11l_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110l0Ol_dataout; + wire_n110l01l_dataout <= wire_n110O11O_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110l0OO_dataout; + wire_n110l01O_dataout <= wire_n110O10i_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110li1i_dataout; + wire_n110l0i_dataout <= nlOi1ilO WHEN niOO00iil = '1' ELSE nlOi0i1O; + wire_n110l0ii_dataout <= wire_n110Oi0O_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_nlOO1iO1O_dataout; + wire_n110l0il_dataout <= wire_n110Oiii_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_nlOO1iO0i_dataout; + wire_n110l0iO_dataout <= wire_n110Oiil_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_nlOO1iO0l_dataout; + wire_n110l0l_dataout <= nlOi1iOi WHEN niOO00iil = '1' ELSE nlOi0i0i; + wire_n110l0li_dataout <= wire_n110liOl_dataout WHEN niOl0ilOl = '1' ELSE wire_n110li1O_dataout; + wire_n110l0ll_dataout <= wire_n110liOO_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100Oll_dataout; + wire_n110l0lO_dataout <= wire_n110ll1i_dataout WHEN niOl0ilOl = '1' ELSE wire_n110li0i_dataout; + wire_n110l0O_dataout <= nlOi1iOl WHEN niOO00iil = '1' ELSE nlOi0i0l; + wire_n110l0Oi_dataout <= wire_n110ll1l_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100OOi_dataout; + wire_n110l0Ol_dataout <= wire_n110ll1O_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100OOl_dataout; + wire_n110l0OO_dataout <= wire_n110ll0i_dataout WHEN niOl0ilOl = '1' ELSE wire_n1100OOO_dataout; + wire_n110l11i_dataout <= n1101liO OR niOl011ll; + wire_n110l1i_dataout <= nlOi1iiO WHEN niOO00iil = '1' ELSE nlOi00OO; + wire_n110l1l_dataout <= nlOi1ili WHEN niOO00iil = '1' ELSE nlOi0i1i; + wire_n110l1lO_dataout <= wire_n110lOOi_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110l0li_dataout; + wire_n110l1O_dataout <= nlOi1ill WHEN niOO00iil = '1' ELSE nlOi0i1l; + wire_n110l1Oi_dataout <= wire_n110lOOl_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110l0ll_dataout; + wire_n110l1Ol_dataout <= wire_n110lOOO_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110l0lO_dataout; + wire_n110l1OO_dataout <= wire_n110O11i_dataout WHEN wire_w_lg_niOO10lOO8902w(0) = '1' ELSE wire_n110l0Oi_dataout; + wire_n110li0i_dataout <= wire_n110li0O_dataout OR niOl0ilOi; + wire_n110li0l_dataout <= wire_n110liii_dataout OR niOl0ilOi; + wire_n110li0O_dataout <= wire_n110lill_dataout WHEN niOl0illO = '1' ELSE wire_n110i1Oi_dataout; + wire_n110li1i_dataout <= wire_n110ll0l_dataout WHEN niOl0ilOl = '1' ELSE wire_n110li0l_dataout; + wire_n110li1l_dataout <= wire_n110ll0O_dataout WHEN niOl0ilOl = '1' ELSE wire_n110i11l_dataout; + wire_n110li1O_dataout <= wire_n110liOi_dataout WHEN niOl0ilOi = '1' ELSE wire_n110i11O_dataout; + wire_n110lii_dataout <= nlOi1iOO WHEN niOO00iil = '1' ELSE nlOi0i0O; + wire_n110liii_dataout <= wire_n110liil_dataout OR niOl0illO; + wire_n110liil_dataout <= wire_n110liiO_dataout WHEN niOl0illl = '1' ELSE n1101lil; + wire_n110liiO_dataout <= wire_n110lili_dataout OR niOl011OO; + wire_n110lil_dataout <= nlOi1l1i WHEN niOO00iil = '1' ELSE nlOi0iii; + wire_n110lili_dataout <= wire_w_lg_niOl0100O23590w(0) WHEN niOl0101i = '1' ELSE wire_n110iill_dataout; + wire_n110lill_dataout <= wire_n110lilO_dataout OR niOl0100l; + wire_n110lilO_dataout <= wire_w_lg_niOl0100O23590w(0) AND niOl0101l; + wire_n110liO_dataout <= nlOi1l1l WHEN niOO00iil = '1' ELSE nlOi0iil; + wire_n110liOi_dataout <= wire_w_lg_niOl0100O23590w(0) OR NOT(nlOO0iilO); + wire_n110liOl_dataout <= wire_n110llii_dataout AND NOT(niOl0101l); + wire_n110liOO_dataout <= wire_n110llil_dataout OR niOl0101l; + wire_n110ll0i_dataout <= wire_n110lllO_dataout OR niOl0101l; + wire_n110ll0l_dataout <= wire_n110llOi_dataout OR niOl0101l; + wire_n110ll0O_dataout <= wire_n110llOl_dataout OR niOl0101l; + wire_n110ll1i_dataout <= wire_n110lliO_dataout OR niOl0101l; + wire_n110ll1l_dataout <= wire_n110llli_dataout OR niOl0101l; + wire_n110ll1O_dataout <= wire_n110llll_dataout OR niOl0101l; + wire_n110lli_dataout <= nlOi1l1O WHEN niOO00iil = '1' ELSE nlOi0iiO; + wire_n110llii_dataout <= wire_n110llOO_dataout AND NOT(niOl0100i); + wire_n110llil_dataout <= wire_n110lO1i_dataout AND NOT(niOl0100i); + wire_n110lliO_dataout <= wire_n110lO1l_dataout OR niOl0100i; + wire_n110lll_dataout <= nlOi1l0i WHEN niOO00iil = '1' ELSE nlOi0ili; + wire_n110llli_dataout <= wire_n110lO1O_dataout OR niOl0100i; + wire_n110llll_dataout <= wire_n110lO0i_dataout OR niOl0100i; + wire_n110lllO_dataout <= wire_n110lO0l_dataout OR niOl0100i; + wire_n110llO_dataout <= nlOi1l0l WHEN niOO00iil = '1' ELSE nlOi0ill; + wire_n110llOi_dataout <= wire_n110lO0O_dataout OR niOl0100i; + wire_n110llOl_dataout <= wire_n110lOii_dataout OR niOl0100i; + wire_n110llOO_dataout <= wire_n110iOiO_dataout AND NOT(niOl0101O); + wire_n110lO0i_dataout <= wire_n110iOOi_dataout OR niOl0101O; + wire_n110lO0l_dataout <= wire_n110iOOl_dataout OR niOl0101O; + wire_n110lO0O_dataout <= wire_n110iOOO_dataout OR niOl0101O; + wire_n110lO1i_dataout <= wire_n110iOli_dataout OR niOl0101O; + wire_n110lO1l_dataout <= wire_n110iOll_dataout OR niOl0101O; + wire_n110lO1O_dataout <= wire_n110iOlO_dataout OR niOl0101O; + wire_n110lOi_dataout <= nlOi1l0O WHEN niOO00iil = '1' ELSE nlOi0ilO; + wire_n110lOii_dataout <= wire_n110l11i_dataout OR niOl0101O; + wire_n110lOl_dataout <= nlOi1lii WHEN niOO00iil = '1' ELSE nlOi0iOi; + wire_n110lOO_dataout <= nlOi1lil WHEN niOO00iil = '1' ELSE nlOi0iOl; + wire_n110lOOi_dataout <= wire_n110O10O_dataout AND NOT(nlOO0iilO); + wire_n110lOOl_dataout <= wire_n110Oi1i_dataout WHEN nlOO0iilO = '1' ELSE wire_n110O1ii_dataout; + wire_n110lOOO_dataout <= wire_n110Oi1l_dataout WHEN nlOO0iilO = '1' ELSE wire_n110O1il_dataout; + wire_n110O00i_dataout <= wire_n110O0lO_dataout OR nlOO0iiOO; + wire_n110O00l_dataout <= wire_n110O0Oi_dataout OR nlOO0iiOO; + wire_n110O00O_dataout <= wire_n110O0Ol_dataout OR nlOO0iiOO; + wire_n110O01i_dataout <= (NOT (nlOOOl1Ol AND nlOOOl1Oi)) WHEN nlOO0iiOO = '1' ELSE wire_n110O0iO_dataout; + wire_n110O01l_dataout <= wire_n110O0li_dataout AND NOT(nlOO0iiOO); + wire_n110O01O_dataout <= wire_n110O0ll_dataout OR nlOO0iiOO; + wire_n110O0i_dataout <= nlOi1llO WHEN niOO00iil = '1' ELSE nlOi0l1O; + wire_n110O0ii_dataout <= n1101l1l OR nlOO0iiOi; + wire_n110O0il_dataout <= n1101l1O AND NOT(nlOO0iiOi); + wire_n110O0iO_dataout <= n1101l0i OR nlOO0iiOi; + wire_n110O0l_dataout <= nlOi1lOi WHEN niOO00iil = '1' ELSE nlOi0l0i; + wire_n110O0li_dataout <= n1101l0l OR nlOO0iiOi; + wire_n110O0ll_dataout <= n1101l0O OR nlOO0iiOi; + wire_n110O0lO_dataout <= n1101lii OR nlOO0iiOi; + wire_n110O0O_dataout <= nlOi1lOl WHEN niOO00iil = '1' ELSE nlOi0l0l; + wire_n110O0Oi_dataout <= n1101lil OR nlOO0iiOi; + wire_n110O0Ol_dataout <= n1101liO OR nlOO0iiOi; + wire_n110O0OO_dataout <= wire_w_lg_niOl010il23577w(0) AND NOT(niOl010ii); + wire_n110O10i_dataout <= wire_w_lg_niOl010iO23581w(0) WHEN nlOO0iilO = '1' ELSE wire_n110O1lO_dataout; + wire_n110O10l_dataout <= wire_w_lg_niOl010iO23581w(0) WHEN nlOO0iilO = '1' ELSE wire_n110O1Oi_dataout; + wire_n110O10O_dataout <= wire_n110O1Ol_dataout OR nlOO0il0i; + wire_n110O11i_dataout <= wire_n110Oi1l_dataout WHEN nlOO0iilO = '1' ELSE wire_n110O1iO_dataout; + wire_n110O11l_dataout <= wire_w_lg_niOl010iO23581w(0) WHEN nlOO0iilO = '1' ELSE wire_n110O1li_dataout; + wire_n110O11O_dataout <= wire_w_lg_niOl010iO23581w(0) WHEN nlOO0iilO = '1' ELSE wire_n110O1ll_dataout; + wire_n110O1i_dataout <= nlOi1liO WHEN niOO00iil = '1' ELSE nlOi0iOO; + wire_n110O1ii_dataout <= wire_n110O1OO_dataout OR nlOO0il0i; + wire_n110O1il_dataout <= wire_n110O01i_dataout OR nlOO0il0i; + wire_n110O1iO_dataout <= wire_n110O01l_dataout OR nlOO0il0i; + wire_n110O1l_dataout <= nlOi1lli WHEN niOO00iil = '1' ELSE nlOi0l1i; + wire_n110O1li_dataout <= wire_w_lg_niOl010ii23580w(0) WHEN nlOO0il0i = '1' ELSE wire_n110O01O_dataout; + wire_n110O1ll_dataout <= wire_w_lg_niOl010ii23580w(0) WHEN nlOO0il0i = '1' ELSE wire_n110O00i_dataout; + wire_n110O1lO_dataout <= wire_n110O0OO_dataout WHEN nlOO0il0i = '1' ELSE wire_n110O00l_dataout; + wire_n110O1O_dataout <= nlOi1lll WHEN niOO00iil = '1' ELSE nlOi0l1l; + wire_n110O1Oi_dataout <= wire_n110O00O_dataout AND NOT(nlOO0il0i); + wire_n110O1Ol_dataout <= wire_n110O0ii_dataout OR nlOO0iiOO; + wire_n110O1OO_dataout <= wire_n110O0il_dataout OR nlOO0iiOO; + wire_n110Oi0i_dataout <= wire_n110OiiO_dataout AND NOT(nlOO0iilO); + wire_n110Oi0l_dataout <= wire_n110Oili_dataout AND NOT(nlOO0iilO); + wire_n110Oi0O_dataout <= wire_n110Oill_dataout AND NOT(nlOO0iilO); + wire_n110Oi1i_dataout <= wire_n110Oi1O_dataout AND NOT(niOl010iO); + wire_n110Oi1l_dataout <= wire_w_lg_niOl010li23576w(0) AND NOT(niOl010iO); + wire_n110Oi1O_dataout <= (NOT (nlOOOl1lO AND nlOOOl1ll)) AND NOT(niOl010li); + wire_n110Oii_dataout <= nlOi1lOO WHEN niOO00iil = '1' ELSE nlOi0l0O; + wire_n110Oiii_dataout <= wire_n110OilO_dataout AND NOT(nlOO0iilO); + wire_n110Oiil_dataout <= wire_n110OiOi_dataout AND NOT(nlOO0iilO); + wire_n110OiiO_dataout <= wire_n110OiOl_dataout OR nlOO0il0i; + wire_n110Oil_dataout <= nlOi1O1i WHEN niOO00iil = '1' ELSE nlOi0lii; + wire_n110Oili_dataout <= wire_n110OiOO_dataout AND NOT(nlOO0il0i); + wire_n110Oill_dataout <= wire_n110Ol1i_dataout AND NOT(nlOO0il0i); + wire_n110OilO_dataout <= wire_n110Ol1l_dataout AND NOT(nlOO0il0i); + wire_n110OiO_dataout <= nlOi1O1l WHEN niOO00iil = '1' ELSE nlOi0lil; + wire_n110OiOi_dataout <= wire_n110Ol1O_dataout OR nlOO0il0i; + wire_n110OiOl_dataout <= wire_n110Ol0i_dataout OR nlOO0iiOO; + wire_n110OiOO_dataout <= wire_n110Ol0l_dataout AND NOT(nlOO0iiOO); + wire_n110Ol0i_dataout <= n1101iiO OR nlOO0iiOi; + wire_n110Ol0l_dataout <= n1101iOi AND NOT(nlOO0iiOi); + wire_n110Ol0O_dataout <= n1101iOl OR nlOO0iiOi; + wire_n110Ol1i_dataout <= wire_n110Ol0O_dataout AND NOT(nlOO0iiOO); + wire_n110Ol1l_dataout <= wire_n110Olii_dataout OR nlOO0iiOO; + wire_n110Ol1O_dataout <= wire_n110Olil_dataout AND NOT(nlOO0iiOO); + wire_n110Oli_dataout <= nlOi1O1O WHEN niOO00iil = '1' ELSE nlOi0liO; + wire_n110Olii_dataout <= n1101iOO AND NOT(nlOO0iiOi); + wire_n110Olil_dataout <= n1101l1i AND NOT(nlOO0iiOi); + wire_n110Oll_dataout <= nlOi1O0i WHEN niOO00iil = '1' ELSE nlOi0lli; + wire_n110Olll_dataout <= wire_w_lg_niOl0O0lO23571w(0) AND niOl010lO; + wire_n110OllO_dataout <= wire_w_lg_niOl0O0ll23570w(0) AND niOl010lO; + wire_n110OlOi_dataout <= wire_w_lg_niOl0O0li23569w(0) AND niOl010lO; + wire_n110OlOl_dataout <= wire_w_lg_niOl0O0iO23568w(0) AND niOl010lO; + wire_n110OlOO_dataout <= wire_w_lg_niOl0O0il23567w(0) AND niOl010lO; + wire_n110OO0O_dataout <= n111i0il OR n11O0lil; + wire_n110OO1i_dataout <= wire_w_lg_niOl0O0ii23566w(0) AND niOl010lO; + wire_n110OO1l_dataout <= wire_w_lg_niOl0O00O23565w(0) AND niOl010lO; + wire_n110OO1O_dataout <= wire_w_lg_niOl0O00l23564w(0) AND niOl010lO; + wire_n110OOO_dataout <= nlOi1O0l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(132); + wire_n111000O_dataout <= ((NOT k_gbl_hip(41)) AND wire_niO11iOl_w_lg_w_lg_w_lg_dataout13002w23941w23942w(0)) WHEN niOl1Oi0O = '1' ELSE nlOOOl01l; + wire_n111001l_dataout <= ((NOT k_gbl_hip(42)) AND wire_niO110Ol_w_lg_w_lg_w_lg_dataout12091w23945w23946w(0)) WHEN niOl1Oi0l = '1' ELSE nlOOOl01O; + wire_n111001O_dataout <= nlOOOl01O WHEN niOl1Oi0l = '1' ELSE nlOOOl1li; + wire_n11100i_dataout <= wire_n11i11l_dataout WHEN niOO00iiO = '1' ELSE wire_n1101iO_dataout; + wire_n11100ii_dataout <= nlOOOl01l WHEN niOl1Oi0O = '1' ELSE nlOOOl1iO; + wire_n11100l_dataout <= wire_n11i11O_dataout WHEN niOO00iiO = '1' ELSE wire_n1101li_dataout; + wire_n11100li_dataout <= ((NOT k_gbl_hip(40)) AND wire_niO11lOl_w_lg_w_lg_w_lg_dataout13909w23937w23938w(0)) WHEN niOl1Oiii = '1' ELSE nlOOOl01i; + wire_n11100ll_dataout <= nlOOOl01i WHEN niOl1Oiii = '1' ELSE nlOOOl1il; + wire_n11100O_dataout <= wire_n11i10i_dataout WHEN niOO00iiO = '1' ELSE wire_n1101ll_dataout; + wire_n11100Ol_dataout <= ((NOT k_gbl_hip(39)) AND wire_niO11OOl_w_lg_w_lg_w_lg_dataout14816w23933w23934w(0)) WHEN niOl1Oiil = '1' ELSE nlOOOl1OO; + wire_n11100OO_dataout <= nlOOOl1OO WHEN niOl1Oiil = '1' ELSE nlOOOl1ii; + wire_n11101i_dataout <= wire_n11Ol1i_dataout WHEN niOO00ili = '1' ELSE wire_n11101l_dataout; + wire_n11101il_dataout <= niil01il OR n11O0lli; + wire_n11101iO_dataout <= niil01ii OR n11O0lli; + wire_n11101l_dataout <= wire_n110OOO_dataout WHEN niOO00iiO = '1' ELSE wire_n1101ii_dataout; + wire_n11101li_dataout <= niil0iOO OR n11O0lli; + wire_n11101ll_dataout <= niil0l1l OR n11O0lli; + wire_n11101lO_dataout <= niil0l1O OR n11O0lli; + wire_n11101O_dataout <= wire_n11i11i_dataout WHEN niOO00iiO = '1' ELSE wire_n1101il_dataout; + wire_n11101Oi_dataout <= niil0l0i OR n11O0lli; + wire_n11101Ol_dataout <= niil0l0l OR n11O0lli; + wire_n11101OO_dataout <= niil0liO OR n11O0lli; + wire_n1110i0i_dataout <= nlOOOl1Ol WHEN niOl1OiiO = '1' ELSE nlOOOl10O; + wire_n1110i1O_dataout <= ((NOT k_gbl_hip(38)) AND wire_niO101Ol_w_lg_w_lg_w_lg_dataout15723w23929w23930w(0)) WHEN niOl1OiiO = '1' ELSE nlOOOl1Ol; + wire_n1110ii_dataout <= wire_n11i10l_dataout WHEN niOO00iiO = '1' ELSE wire_n1101lO_dataout; + wire_n1110iii_dataout <= ((NOT k_gbl_hip(37)) AND wire_niO100Ol_w_lg_w_lg_w_lg_dataout16630w23925w23926w(0)) WHEN niOl1Oili = '1' ELSE nlOOOl1Oi; + wire_n1110iil_dataout <= nlOOOl1Oi WHEN niOl1Oili = '1' ELSE nlOOOl10l; + wire_n1110il_dataout <= wire_n11i10O_dataout WHEN niOO00iiO = '1' ELSE wire_n1101Oi_dataout; + wire_n1110ill_dataout <= ((NOT k_gbl_hip(36)) AND wire_niO10iOl_w_lg_w_lg_w_lg_dataout17537w23921w23922w(0)) WHEN niOl1Oill = '1' ELSE nlOOOl1lO; + wire_n1110ilO_dataout <= nlOOOl1lO WHEN niOl1Oill = '1' ELSE nlOOOl10i; + wire_n1110iO_dataout <= wire_n11i1ii_dataout WHEN niOO00iiO = '1' ELSE wire_n1101Ol_dataout; + wire_n1110iOO_dataout <= ((NOT k_gbl_hip(35)) AND wire_niO10lOl_w_lg_w_lg_w_lg_dataout18444w23917w23918w(0)) WHEN niOl1OilO = '1' ELSE nlOOOl1ll; + wire_n1110l0i_dataout <= wire_niO10O1i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO10O1i_dataout OR nlOO0ilOi); + wire_n1110l0l_dataout <= wire_niO10l1i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO10l1i_dataout OR nlOOO0OlO); + wire_n1110l0O_dataout <= wire_niO10i1i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO10i1i_dataout OR nlOOO0OOi); + wire_n1110l1i_dataout <= nlOOOl1ll WHEN niOl1OilO = '1' ELSE nlOOOl11O; + wire_n1110li_dataout <= wire_n11i1il_dataout WHEN niOO00iiO = '1' ELSE wire_n1101OO_dataout; + wire_n1110lii_dataout <= wire_niO1001i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO1001i_dataout OR nlOOO0OOl); + wire_n1110lil_dataout <= wire_niO1011i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO1011i_dataout OR nlOOO0OOO); + wire_n1110liO_dataout <= wire_niO11O1i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO11O1i_dataout OR nlOOOi11i); + wire_n1110ll_dataout <= wire_n11i1iO_dataout WHEN niOO00iiO = '1' ELSE wire_n11001i_dataout; + wire_n1110lli_dataout <= wire_niO11l1i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO11l1i_dataout OR nlOOOi11l); + wire_n1110lll_dataout <= wire_niO11i1i_dataout WHEN niOlO1O0i = '1' ELSE (wire_niO11i1i_dataout OR nlOOOi11O); + wire_n1110lO_dataout <= wire_n11i1li_dataout WHEN niOO00iiO = '1' ELSE wire_n11001l_dataout; + wire_n1110Oi_dataout <= wire_n11i1ll_dataout WHEN niOO00iiO = '1' ELSE wire_n11001O_dataout; + wire_n1110Ol_dataout <= wire_n11i1lO_dataout WHEN niOO00iiO = '1' ELSE wire_n11000i_dataout; + wire_n1110OO_dataout <= wire_n11i1Oi_dataout WHEN niOO00iiO = '1' ELSE wire_n11000l_dataout; + wire_n111100i_dataout <= n011llli WHEN niOl1O0li = '1' ELSE nlOOOil1i; + wire_n111100l_dataout <= n011llll WHEN niOl1O0li = '1' ELSE nlOOOil1l; + wire_n111100O_dataout <= n011lllO WHEN niOl1O0li = '1' ELSE nlOOOil1O; + wire_n111101i_dataout <= n01O0i1i WHEN niOl1O0li = '1' ELSE nlOOOiiOi; + wire_n111101l_dataout <= n011llil WHEN niOl1O0li = '1' ELSE nlOOOiiOl; + wire_n111101O_dataout <= n011lliO WHEN niOl1O0li = '1' ELSE nlOOOiiOO; + wire_n11110i_dataout <= wire_n11Oi0i_dataout WHEN niOO00ili = '1' ELSE wire_n111Oll_dataout; + wire_n11110ii_dataout <= n1Oi010i WHEN niOl1O0li = '1' ELSE nlOOOil0i; + wire_n11110il_dataout <= n1Oi010l WHEN niOl1O0li = '1' ELSE nlOOOil0l; + wire_n11110iO_dataout <= n1Oi010O WHEN niOl1O0li = '1' ELSE nlOOOil0O; + wire_n11110l_dataout <= wire_n11Oi0l_dataout WHEN niOO00ili = '1' ELSE wire_n111OlO_dataout; + wire_n11110li_dataout <= n1Oi01ii WHEN niOl1O0li = '1' ELSE nlOOOilii; + wire_n11110ll_dataout <= n1Oi01il WHEN niOl1O0li = '1' ELSE nlOOOilil; + wire_n11110O_dataout <= wire_n11Oi0O_dataout WHEN niOO00ili = '1' ELSE wire_n111OOi_dataout; + wire_n111110i_dataout <= n0i00lii WHEN niOl1O0li = '1' ELSE nlOOOii1i; + wire_n111110l_dataout <= n0i00lil WHEN niOl1O0li = '1' ELSE nlOOOii1l; + wire_n111110O_dataout <= n0i00liO WHEN niOl1O0li = '1' ELSE nlOOOii1O; + wire_n111111i_dataout <= n0iOO0Oi WHEN niOl1O0li = '1' ELSE nlOOOi0Oi; + wire_n111111l_dataout <= n0i00l0l WHEN niOl1O0li = '1' ELSE nlOOOi0Ol; + wire_n111111O_dataout <= n0i00l0O WHEN niOl1O0li = '1' ELSE nlOOOi0OO; + wire_n11111i_dataout <= wire_n11Oi1i_dataout WHEN niOO00ili = '1' ELSE wire_n111Oil_dataout; + wire_n11111ii_dataout <= n00iO11i WHEN niOl1O0li = '1' ELSE nlOOOii0i; + wire_n11111il_dataout <= n00iO11l WHEN niOl1O0li = '1' ELSE nlOOOii0l; + wire_n11111iO_dataout <= n00iO11O WHEN niOl1O0li = '1' ELSE nlOOOii0O; + wire_n11111l_dataout <= wire_n11Oi1l_dataout WHEN niOO00ili = '1' ELSE wire_n111OiO_dataout; + wire_n11111li_dataout <= n00iO10i WHEN niOl1O0li = '1' ELSE nlOOOiiii; + wire_n11111ll_dataout <= n00iO10l WHEN niOl1O0li = '1' ELSE nlOOOiiil; + wire_n11111lO_dataout <= n01O00lO WHEN niOl1O0li = '1' ELSE nlOOOiiiO; + wire_n11111O_dataout <= wire_n11Oi1O_dataout WHEN niOO00ili = '1' ELSE wire_n111Oli_dataout; + wire_n11111Oi_dataout <= n01O00Oi WHEN niOl1O0li = '1' ELSE nlOOOiili; + wire_n11111Ol_dataout <= n01O00Ol WHEN niOl1O0li = '1' ELSE nlOOOiill; + wire_n11111OO_dataout <= n01O00OO WHEN niOl1O0li = '1' ELSE nlOOOiilO; + wire_n1111i0l_dataout <= (wire_niO01llO_w_lg_niil01il23950w(0) OR nlOOOiliO) AND NOT(niOlO1O0i); + wire_n1111i0O_dataout <= (wire_niO01llO_w_lg_niil01ii23952w(0) OR nlOOOilli) AND NOT(niOlO1O0i); + wire_n1111ii_dataout <= wire_n11Oiii_dataout WHEN niOO00ili = '1' ELSE wire_n111OOl_dataout; + wire_n1111iii_dataout <= (wire_niO01llO_w_lg_niil0iOO23954w(0) OR nlOOOilll) AND NOT(niOlO1O0i); + wire_n1111iil_dataout <= (wire_niO01llO_w_lg_niil0l1l23956w(0) OR nlOOOillO) AND NOT(niOlO1O0i); + wire_n1111iiO_dataout <= (wire_niO01llO_w_lg_niil0l1O23958w(0) OR nlOOOilOi) AND NOT(niOlO1O0i); + wire_n1111il_dataout <= wire_n11Oiil_dataout WHEN niOO00ili = '1' ELSE wire_n111OOO_dataout; + wire_n1111ili_dataout <= (wire_niO01llO_w_lg_niil0l0i23960w(0) OR nlOOOilOl) AND NOT(niOlO1O0i); + wire_n1111ill_dataout <= (wire_niO01llO_w_lg_niil0l0l23962w(0) OR nlOOOilOO) AND NOT(niOlO1O0i); + wire_n1111ilO_dataout <= (wire_niO01llO_w_lg_niil0liO23964w(0) OR nlOOOiO1i) AND NOT(niOlO1O0i); + wire_n1111iO_dataout <= wire_n11OiiO_dataout WHEN niOO00ili = '1' ELSE wire_n11011i_dataout; + wire_n1111l0O_dataout <= wire_n11101il_dataout WHEN niOl1Oi0i = '1' ELSE niil01il; + wire_n1111li_dataout <= wire_n11Oili_dataout WHEN niOO00ili = '1' ELSE wire_n11011l_dataout; + wire_n1111lii_dataout <= wire_n11101iO_dataout WHEN niOl1Oi0i = '1' ELSE niil01ii; + wire_n1111lil_dataout <= wire_n11101li_dataout WHEN niOl1Oi0i = '1' ELSE niil0iOO; + wire_n1111liO_dataout <= wire_n11101ll_dataout WHEN niOl1Oi0i = '1' ELSE niil0l1l; + wire_n1111ll_dataout <= wire_n11Oill_dataout WHEN niOO00ili = '1' ELSE wire_n11011O_dataout; + wire_n1111lli_dataout <= wire_n11101lO_dataout WHEN niOl1Oi0i = '1' ELSE niil0l1O; + wire_n1111lll_dataout <= wire_n11101Oi_dataout WHEN niOl1Oi0i = '1' ELSE niil0l0i; + wire_n1111llO_dataout <= wire_n11101Ol_dataout WHEN niOl1Oi0i = '1' ELSE niil0l0l; + wire_n1111lO_dataout <= wire_n11OilO_dataout WHEN niOO00ili = '1' ELSE wire_n11010i_dataout; + wire_n1111lOi_dataout <= wire_n11101OO_dataout WHEN niOl1Oi0i = '1' ELSE niil0liO; + wire_n1111lOl_dataout <= (niOl1Oi1O OR nlOOOiO1l) AND NOT(niOl1Oi0i); + wire_n1111lOO_dataout <= (niOl1Oi1l OR nlOOOiO1O) AND NOT(niOl1Oi0i); + wire_n1111O0i_dataout <= (niOl1O0Oi OR nlOOOiOii) AND NOT(niOl1Oi0i); + wire_n1111O0l_dataout <= (niOl1O0lO OR nlOOOiOil) AND NOT(niOl1Oi0i); + wire_n1111O0O_dataout <= (niOl1O0ll OR nlOOOiOiO) AND NOT(niOl1Oi0i); + wire_n1111O1i_dataout <= (niOl1Oi1i OR nlOOOiO0i) AND NOT(niOl1Oi0i); + wire_n1111O1l_dataout <= (niOl1O0OO OR nlOOOiO0l) AND NOT(niOl1Oi0i); + wire_n1111O1O_dataout <= (niOl1O0Ol OR nlOOOiO0O) AND NOT(niOl1Oi0i); + wire_n1111Oi_dataout <= wire_n11OiOi_dataout WHEN niOO00ili = '1' ELSE wire_n11010l_dataout; + wire_n1111Ol_dataout <= wire_n11OiOl_dataout WHEN niOO00ili = '1' ELSE wire_n11010O_dataout; + wire_n1111OO_dataout <= wire_n11OiOO_dataout WHEN niOO00ili = '1' ELSE nlOi1O0l; + wire_n111i0i_dataout <= wire_n11i01l_dataout WHEN niOO00iiO = '1' ELSE wire_n1100iO_dataout; + wire_n111i0iO_dataout <= wire_n1101i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111i0l_dataout <= wire_n11i01O_dataout WHEN niOO00iiO = '1' ELSE wire_n1100li_dataout; + wire_n111i0li_dataout <= wire_n111l1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111i0ll_dataout <= wire_n111llii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111i0lO_dataout <= wire_n111ilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111i0O_dataout <= wire_n11i00i_dataout WHEN niOO00iiO = '1' ELSE wire_n1100ll_dataout; + wire_n111i0Oi_dataout <= wire_n111iO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111i0Ol_dataout <= n1110Oli AND NOT(wire_niO01lOO_dataout); + wire_n111i0OO_dataout <= wire_n11011ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111i1i_dataout <= wire_n11i1Ol_dataout WHEN niOO00iiO = '1' ELSE wire_n11000O_dataout; + wire_n111i1l_dataout <= wire_n11i1OO_dataout WHEN niOO00iiO = '1' ELSE wire_n1100ii_dataout; + wire_n111i1O_dataout <= wire_n11i01i_dataout WHEN niOO00iiO = '1' ELSE wire_n1100il_dataout; + wire_n111ii0i_dataout <= n11O0lil AND NOT(wire_niO01lOO_dataout); + wire_n111ii0l_dataout <= n111i11i AND NOT(wire_niO01lOO_dataout); + wire_n111ii0O_dataout <= n111i11l AND NOT(wire_niO01lOO_dataout); + wire_n111ii1i_dataout <= (n11O0lli OR (n11O0liO OR (n11O0lll OR (n11O0llO OR (n11O0lOi OR (n11O0lOl OR (n11O0lOO OR (n11O0O1i OR (n11O0O1O OR n11O0O1l))))))))) AND NOT(wire_niO01lOO_dataout); + wire_n111ii1l_dataout <= wire_n111lliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111ii1O_dataout <= niOl1Olli AND NOT(wire_niO01lOO_dataout); + wire_n111iii_dataout <= wire_n11i00l_dataout WHEN niOO00iiO = '1' ELSE wire_n1100lO_dataout; + wire_n111iiii_dataout <= n1lillil AND NOT(wire_niO01lOO_dataout); + wire_n111iiil_dataout <= wire_n111iO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111iiiO_dataout <= n111i11O AND NOT(wire_niO01lOO_dataout); + wire_n111iil_dataout <= wire_n11i00O_dataout WHEN niOO00iiO = '1' ELSE wire_n1100Oi_dataout; + wire_n111iili_dataout <= wire_n111l11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111iill_dataout <= wire_n111OlOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111iilO_dataout <= wire_n111lOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111iiO_dataout <= wire_n11i0ii_dataout WHEN niOO00iiO = '1' ELSE wire_n1100Ol_dataout; + wire_n111iiOi_dataout <= wire_n111lOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111iiOl_dataout <= wire_n111lOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111iiOO_dataout <= wire_n111lOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111il0i_dataout <= wire_n111O10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111il0l_dataout <= wire_n111lO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111il0O_dataout <= wire_n111lO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111il1i_dataout <= wire_n111O11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111il1l_dataout <= wire_n111O11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111il1O_dataout <= wire_n111O11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111ili_dataout <= wire_n11i0il_dataout WHEN niOO00iiO = '1' ELSE wire_n1100OO_dataout; + wire_n111ilii_dataout <= wire_n111lO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111ilil_dataout <= wire_n111lOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111iliO_dataout <= wire_n111lOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111ill_dataout <= wire_n11i0iO_dataout WHEN niOO00iiO = '1' ELSE wire_n110i1i_dataout; + wire_n111illi_dataout <= wire_n111lOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111illl_dataout <= wire_n111lOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111illO_dataout <= wire_n111lOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n111ilO_dataout <= wire_n11i0li_dataout WHEN niOO00iiO = '1' ELSE wire_n110i1l_dataout; + wire_n111ilOi_dataout <= wire_n1l10lli_dataout WHEN (wire_niO01ill_w_lg_n11Oi10i23897w(0) AND n11O0l0O) = '1' ELSE wire_n111ilOl_dataout; + wire_n111ilOl_dataout <= n1110Oii AND NOT(n11O0Oil); + wire_n111iO1i_dataout <= n1110Oil WHEN n11O0lii = '1' ELSE wire_nlOii0l0O_dataout; + wire_n111iO1l_dataout <= wire_niO01ill_w_lg_n111i10l23888w(0) WHEN (wire_niO01ill_w_lg_w_lg_n11Oi1ll23889w23890w(0) OR (wire_n1l10lli_w_lg_dataout21212w(0) AND (wire_w_lg_niOl01l0i23892w(0) AND wire_w_lg_niOO10lOO23893w(0)))) = '1' ELSE wire_n111iO1O_dataout; + wire_n111iO1O_dataout <= n111i11O AND NOT((n11O0O1O OR (n11O0l1O OR (n11O0l0O OR (n11O0lii OR (n11O0Oil OR n11O0llO)))))); + wire_n111iOi_dataout <= wire_n11i0ll_dataout WHEN niOO00iiO = '1' ELSE wire_n110i1O_dataout; + wire_n111iOl_dataout <= wire_n11i0lO_dataout WHEN niOO00iiO = '1' ELSE wire_n110i0i_dataout; + wire_n111iOO_dataout <= wire_n11i0Oi_dataout WHEN niOO00iiO = '1' ELSE wire_n110i0l_dataout; + wire_n111l01i_dataout <= n1110O0l OR (wire_nlOii0lOl_w_lg_dataout23877w(0) OR wire_niO01iOi_w_lg_w_lg_nlOllllii23878w23879w(0)); + wire_n111l0i_dataout <= wire_n11ii1l_dataout WHEN niOO00iiO = '1' ELSE wire_n110iiO_dataout; + wire_n111l0l_dataout <= wire_n11ii1O_dataout WHEN niOO00iiO = '1' ELSE wire_n110ili_dataout; + wire_n111l0O_dataout <= wire_n11ii0i_dataout WHEN niOO00iiO = '1' ELSE wire_n110ill_dataout; + wire_n111l11i_dataout <= (wire_n1l10l0l_dataout OR niOl1OiOi) WHEN n11O0lOl = '1' ELSE n111i10l; + wire_n111l1i_dataout <= wire_n11i0Ol_dataout WHEN niOO00iiO = '1' ELSE wire_n110i0O_dataout; + wire_n111l1l_dataout <= wire_n11i0OO_dataout WHEN niOO00iiO = '1' ELSE wire_n110iii_dataout; + wire_n111l1ll_dataout <= wire_n111l1OO_dataout WHEN n11O0lil = '1' ELSE wire_n111l1lO_dataout; + wire_n111l1lO_dataout <= wire_n111l1Oi_dataout OR (n11O0l1l AND nlOlliOOO); + wire_n111l1O_dataout <= wire_n11ii1i_dataout WHEN niOO00iiO = '1' ELSE wire_n110iil_dataout; + wire_n111l1Oi_dataout <= n1110O0l AND n11O0llO; + wire_n111l1OO_dataout <= wire_n111l01i_dataout WHEN n1lillil = '1' ELSE n1110O0l; + wire_n111lii_dataout <= wire_n11ii0l_dataout WHEN niOO00iiO = '1' ELSE wire_n110ilO_dataout; + wire_n111lil_dataout <= wire_n11ii0O_dataout WHEN niOO00iiO = '1' ELSE wire_n110iOi_dataout; + wire_n111liO_dataout <= wire_n11iiii_dataout WHEN niOO00iiO = '1' ELSE wire_n110iOl_dataout; + wire_n111lli_dataout <= wire_n11iiil_dataout WHEN niOO00iiO = '1' ELSE wire_n110iOO_dataout; + wire_n111llii_dataout <= wire_n111llil_dataout AND n11O0lil; + wire_n111llil_dataout <= n1110O0O OR n1lillil; + wire_n111lliO_dataout <= wire_n111lO1l_dataout WHEN n11O0lOi = '1' ELSE wire_n111llli_dataout; + wire_n111lll_dataout <= wire_n11iiiO_dataout WHEN niOO00iiO = '1' ELSE wire_n110l1i_dataout; + wire_n111llli_dataout <= n1110OlO AND NOT((n11O0l0O OR (wire_niO01iOi_w_lg_n11O0Oil23855w(0) OR ((n11O0lii AND niOli10Ol) AND wire_w_lg_niOl00l0O23857w(0))))); + wire_n111llO_dataout <= wire_n11iili_dataout WHEN niOO00iiO = '1' ELSE wire_n110l1l_dataout; + wire_n111lO0i_dataout <= wire_n111O00O_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O1Oi_dataout; + wire_n111lO0l_dataout <= wire_n111O0ii_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O1Ol_dataout; + wire_n111lO0O_dataout <= wire_n111O0il_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O1OO_dataout; + wire_n111lO1l_dataout <= n1110OlO OR n1lillil; + wire_n111lOi_dataout <= wire_n11iill_dataout WHEN niOO00iiO = '1' ELSE wire_n110l1O_dataout; + wire_n111lOii_dataout <= wire_n111O0iO_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O01i_dataout; + wire_n111lOil_dataout <= wire_n111O0li_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O01l_dataout; + wire_n111lOiO_dataout <= wire_n111O0ll_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O01O_dataout; + wire_n111lOl_dataout <= wire_n11iilO_dataout WHEN niOO00iiO = '1' ELSE wire_n110l0i_dataout; + wire_n111lOli_dataout <= wire_n111O0lO_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O00i_dataout; + wire_n111lOll_dataout <= wire_n111O0Oi_dataout WHEN niOl1OOiO = '1' ELSE wire_n111O00l_dataout; + wire_n111lOlO_dataout <= wire_niO01ill_w_lg_n1101l1l17904w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O10l_dataout; + wire_n111lOO_dataout <= wire_n11iiOi_dataout WHEN niOO00iiO = '1' ELSE wire_n110l0l_dataout; + wire_n111lOOi_dataout <= wire_niO01ill_w_lg_n1101l1O16997w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O10O_dataout; + wire_n111lOOl_dataout <= wire_niO01ill_w_lg_n1101l0i16090w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O1ii_dataout; + wire_n111lOOO_dataout <= wire_niO01ill_w_lg_n1101l0l15183w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O1il_dataout; + wire_n111O00i_dataout <= n111i00O AND NOT(n11O0Oil); + wire_n111O00l_dataout <= n111i0ii AND NOT(n11O0Oil); + wire_n111O00O_dataout <= wire_n111O0Ol_dataout OR niOl1Olll; + wire_n111O01i_dataout <= n111i01O AND NOT(n11O0Oil); + wire_n111O01l_dataout <= n111i00i AND NOT(n11O0Oil); + wire_n111O01O_dataout <= n111i00l AND NOT(n11O0Oil); + wire_n111O0i_dataout <= wire_n11il1l_dataout WHEN niOO00iiO = '1' ELSE wire_n110liO_dataout; + wire_n111O0ii_dataout <= wire_n111O0OO_dataout OR niOl1Olll; + wire_n111O0il_dataout <= wire_n111Oi1i_dataout OR niOl1Olll; + wire_n111O0iO_dataout <= wire_n111Oi1l_dataout OR niOl1Olll; + wire_n111O0l_dataout <= wire_n11il1O_dataout WHEN niOO00iiO = '1' ELSE wire_n110lli_dataout; + wire_n111O0li_dataout <= wire_n111Oi1O_dataout OR niOl1Olll; + wire_n111O0ll_dataout <= wire_n111Oi0i_dataout OR niOl1Olll; + wire_n111O0lO_dataout <= wire_n111Oi0l_dataout OR niOl1Olll; + wire_n111O0O_dataout <= wire_n11il0i_dataout WHEN niOO00iiO = '1' ELSE wire_n110lll_dataout; + wire_n111O0Oi_dataout <= wire_n111Oi0O_dataout OR niOl1Olll; + wire_n111O0Ol_dataout <= wire_n111Oiii_dataout OR niOl1OO0O; + wire_n111O0OO_dataout <= wire_n111Oiil_dataout OR niOl1OO0O; + wire_n111O10i_dataout <= wire_niO01ill_w_lg_n1101liO11541w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O1lO_dataout; + wire_n111O10l_dataout <= n111i1ii AND NOT(n11O0Oil); + wire_n111O10O_dataout <= n111i1il AND NOT(n11O0Oil); + wire_n111O11i_dataout <= wire_niO01ill_w_lg_n1101l0O14276w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O1iO_dataout; + wire_n111O11l_dataout <= wire_niO01ill_w_lg_n1101lii13369w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O1li_dataout; + wire_n111O11O_dataout <= wire_niO01ill_w_lg_n1101lil12462w(0) WHEN niOl1OOiO = '1' ELSE wire_n111O1ll_dataout; + wire_n111O1i_dataout <= wire_n11iiOl_dataout WHEN niOO00iiO = '1' ELSE wire_n110l0O_dataout; + wire_n111O1ii_dataout <= n111i1iO AND NOT(n11O0Oil); + wire_n111O1il_dataout <= n111i1li AND NOT(n11O0Oil); + wire_n111O1iO_dataout <= n111i1ll AND NOT(n11O0Oil); + wire_n111O1l_dataout <= wire_n11iiOO_dataout WHEN niOO00iiO = '1' ELSE wire_n110lii_dataout; + wire_n111O1li_dataout <= n111i1lO AND NOT(n11O0Oil); + wire_n111O1ll_dataout <= n111i1Oi AND NOT(n11O0Oil); + wire_n111O1lO_dataout <= n111i1Ol AND NOT(n11O0Oil); + wire_n111O1O_dataout <= wire_n11il1i_dataout WHEN niOO00iiO = '1' ELSE wire_n110lil_dataout; + wire_n111O1Oi_dataout <= n111i1OO AND NOT(n11O0Oil); + wire_n111O1Ol_dataout <= n111i01i AND NOT(n11O0Oil); + wire_n111O1OO_dataout <= n111i01l AND NOT(n11O0Oil); + wire_n111Oi0i_dataout <= wire_n111OilO_dataout AND NOT(niOl1OO0O); + wire_n111Oi0l_dataout <= wire_n111OiOi_dataout AND NOT(niOl1OO0O); + wire_n111Oi0O_dataout <= wire_n111OiOl_dataout AND NOT(niOl1OO0O); + wire_n111Oi1i_dataout <= wire_n111OiiO_dataout OR niOl1OO0O; + wire_n111Oi1l_dataout <= wire_n111Oili_dataout OR niOl1OO0O; + wire_n111Oi1O_dataout <= wire_n111Oill_dataout AND NOT(niOl1OO0O); + wire_n111Oii_dataout <= wire_n11il0l_dataout WHEN niOO00iiO = '1' ELSE wire_n110llO_dataout; + wire_n111Oiii_dataout <= wire_n111OiOO_dataout OR niOl1OO1l; + wire_n111Oiil_dataout <= wire_n111Ol1i_dataout OR niOl1OO1l; + wire_n111OiiO_dataout <= wire_n111Ol1l_dataout AND NOT(niOl1OO1l); + wire_n111Oil_dataout <= wire_n11il0O_dataout WHEN niOO00iiO = '1' ELSE wire_n110lOi_dataout; + wire_n111Oili_dataout <= wire_n111Ol1O_dataout AND NOT(niOl1OO1l); + wire_n111Oill_dataout <= wire_n111Ol0i_dataout AND NOT(niOl1OO1l); + wire_n111OilO_dataout <= wire_n111Ol0l_dataout AND NOT(niOl1OO1l); + wire_n111OiO_dataout <= wire_n11ilii_dataout WHEN niOO00iiO = '1' ELSE wire_n110lOl_dataout; + wire_n111OiOi_dataout <= wire_n111Ol0O_dataout AND NOT(niOl1OO1l); + wire_n111OiOl_dataout <= wire_n111Olii_dataout AND NOT(niOl1OO1l); + wire_n111OiOO_dataout <= n111i1OO OR niOl1OllO; + wire_n111Ol0i_dataout <= n111i00i AND NOT(niOl1OllO); + wire_n111Ol0l_dataout <= n111i00l AND NOT(niOl1OllO); + wire_n111Ol0O_dataout <= n111i00O AND NOT(niOl1OllO); + wire_n111Ol1i_dataout <= n111i01i AND NOT(niOl1OllO); + wire_n111Ol1l_dataout <= n111i01l AND NOT(niOl1OllO); + wire_n111Ol1O_dataout <= n111i01O AND NOT(niOl1OllO); + wire_n111Oli_dataout <= wire_n11ilil_dataout WHEN niOO00iiO = '1' ELSE wire_n110lOO_dataout; + wire_n111Olii_dataout <= n111i0ii AND NOT(niOl1OllO); + wire_n111Oll_dataout <= wire_n11iliO_dataout WHEN niOO00iiO = '1' ELSE wire_n110O1i_dataout; + wire_n111OlO_dataout <= wire_n11illi_dataout WHEN niOO00iiO = '1' ELSE wire_n110O1l_dataout; + wire_n111OlOO_dataout <= wire_n111OO1i_dataout OR (((nlOO1O1Oi AND nlOllll0O) AND wire_niO01ill_w_lg_n111i10O9993w(0)) OR niOl001OO); + wire_n111OO1i_dataout <= n111i10O AND NOT((wire_niO01ill_w_lg_n11O0iOl23838w(0) OR wire_niO01ill_w_lg_n11O0llO23840w(0))); + wire_n111OOi_dataout <= wire_n11illl_dataout WHEN niOO00iiO = '1' ELSE wire_n110O1O_dataout; + wire_n111OOl_dataout <= wire_n11illO_dataout WHEN niOO00iiO = '1' ELSE wire_n110O0i_dataout; + wire_n111OOO_dataout <= wire_n11ilOi_dataout WHEN niOO00iiO = '1' ELSE wire_n110O0l_dataout; + wire_n11i000i_dataout <= n110OOil WHEN n11O0O1O = '1' ELSE wire_n11i00OO_dataout; + wire_n11i000l_dataout <= n110OOiO WHEN n11O0O1O = '1' ELSE wire_n11i0i1i_dataout; + wire_n11i000O_dataout <= n110OOli WHEN n11O0O1O = '1' ELSE wire_n11i0i1l_dataout; + wire_n11i001i_dataout <= wire_n11l1Oll_dataout WHEN n11O0O0l = '1' ELSE wire_n11i00ll_dataout; + wire_n11i001l_dataout <= n110OOii WHEN n11O0O1O = '1' ELSE wire_n11i00Oi_dataout; + wire_n11i001O_dataout <= n110OOlO WHEN n11O0O1O = '1' ELSE wire_n11i00Ol_dataout; + wire_n11i00i_dataout <= nlOi100i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(18); + wire_n11i00ii_dataout <= n110OOll WHEN n11O0O1O = '1' ELSE wire_n11i0i1O_dataout; + wire_n11i00il_dataout <= wire_n11i0i0i_dataout AND NOT(n11O0O1O); + wire_n11i00iO_dataout <= wire_n11l1lll_dataout WHEN n11O0O1O = '1' ELSE wire_n11i0i0l_dataout; + wire_n11i00l_dataout <= nlOi100l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(19); + wire_n11i00li_dataout <= wire_n11i0i0O_dataout AND NOT(n11O0O1O); + wire_n11i00ll_dataout <= wire_n11l1llO_dataout WHEN n11O0O1O = '1' ELSE wire_n11i0iii_dataout; + wire_n11i00lO_dataout <= wire_n11i0iil_dataout AND NOT(n11O0O1O); + wire_n11i00O_dataout <= nlOi100O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(20); + wire_n11i00Oi_dataout <= n110OOii WHEN n11O0lOl = '1' ELSE wire_n11i0iiO_dataout; + wire_n11i00Ol_dataout <= n110OOlO WHEN n11O0lOl = '1' ELSE wire_n11i0ili_dataout; + wire_n11i00OO_dataout <= n110OOil WHEN n11O0lOl = '1' ELSE wire_n11i0ill_dataout; + wire_n11i010i_dataout <= wire_n11i001i_dataout AND NOT(n11O0O0i); + wire_n11i010l_dataout <= wire_n11i01il_dataout AND NOT(n11O0O0i); + wire_n11i010O_dataout <= n110OOii WHEN n11O0O0l = '1' ELSE wire_n11i001l_dataout; + wire_n11i011i_dataout <= wire_n11i01Oi_dataout OR n11O0O0i; + wire_n11i011l_dataout <= wire_n11i01Ol_dataout OR n11O0O0i; + wire_n11i011O_dataout <= wire_n11i01OO_dataout AND NOT(n11O0O0i); + wire_n11i01i_dataout <= nlOi101i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(15); + wire_n11i01ii_dataout <= n110OOlO WHEN n11O0O0l = '1' ELSE wire_n11i001O_dataout; + wire_n11i01il_dataout <= wire_n11l1O1O_dataout WHEN n11O0O0l = '1' ELSE wire_n11i00lO_dataout; + wire_n11i01iO_dataout <= wire_n11l1O0i_dataout WHEN n11O0O0l = '1' ELSE wire_n11i000i_dataout; + wire_n11i01l_dataout <= nlOi101l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(16); + wire_n11i01li_dataout <= wire_n11l1O0l_dataout WHEN n11O0O0l = '1' ELSE wire_n11i000l_dataout; + wire_n11i01ll_dataout <= wire_n11l1O0O_dataout WHEN n11O0O0l = '1' ELSE wire_n11i000O_dataout; + wire_n11i01lO_dataout <= wire_n11l1Oii_dataout WHEN n11O0O0l = '1' ELSE wire_n11i00ii_dataout; + wire_n11i01O_dataout <= nlOi101O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(17); + wire_n11i01Oi_dataout <= wire_n11l1Oil_dataout WHEN n11O0O0l = '1' ELSE wire_n11i00il_dataout; + wire_n11i01Ol_dataout <= wire_n11l1OiO_dataout WHEN n11O0O0l = '1' ELSE wire_n11i00iO_dataout; + wire_n11i01OO_dataout <= wire_n11l1Oli_dataout WHEN n11O0O0l = '1' ELSE wire_n11i00li_dataout; + wire_n11i0i0i_dataout <= wire_w_lg_niOl01lii23553w(0) WHEN n11O0lOl = '1' ELSE wire_n11i0iOO_dataout; + wire_n11i0i0l_dataout <= wire_w_lg_niOl01lii23553w(0) WHEN n11O0lOl = '1' ELSE wire_n11i0l1i_dataout; + wire_n11i0i0O_dataout <= niOl01lii WHEN n11O0lOl = '1' ELSE wire_n11i0l1l_dataout; + wire_n11i0i1i_dataout <= n110OOiO WHEN n11O0lOl = '1' ELSE wire_n11i0ilO_dataout; + wire_n11i0i1l_dataout <= n110OOli WHEN n11O0lOl = '1' ELSE wire_n11i0iOi_dataout; + wire_n11i0i1O_dataout <= n110OOll WHEN n11O0lOl = '1' ELSE wire_n11i0iOl_dataout; + wire_n11i0ii_dataout <= nlOi10ii WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(21); + wire_n11i0iii_dataout <= wire_n11i0l1O_dataout AND NOT(n11O0lOl); + wire_n11i0iil_dataout <= wire_n11i0l0i_dataout AND NOT(n11O0lOl); + wire_n11i0iiO_dataout <= n110OOii WHEN n11O0lOi = '1' ELSE wire_n11i0l0l_dataout; + wire_n11i0il_dataout <= nlOi10il WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(22); + wire_n11i0ili_dataout <= n110OOlO WHEN n11O0lOi = '1' ELSE wire_n11i0l0O_dataout; + wire_n11i0ill_dataout <= n110OOil WHEN n11O0lOi = '1' ELSE wire_n11i0lll_dataout; + wire_n11i0ilO_dataout <= n110OOiO WHEN n11O0lOi = '1' ELSE wire_n11i0llO_dataout; + wire_n11i0iO_dataout <= nlOi10iO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(23); + wire_n11i0iOi_dataout <= n110OOli WHEN n11O0lOi = '1' ELSE wire_n11i0lOi_dataout; + wire_n11i0iOl_dataout <= n110OOll WHEN n11O0lOi = '1' ELSE wire_n11i0lOl_dataout; + wire_n11i0iOO_dataout <= wire_n11i0lii_dataout AND NOT(n11O0lOi); + wire_n11i0l0i_dataout <= wire_n11i0lOO_dataout AND NOT(n11O0lOi); + wire_n11i0l0l_dataout <= n110OOii WHEN n11O0lil = '1' ELSE wire_n11i0O1i_dataout; + wire_n11i0l0O_dataout <= n110OOlO WHEN n11O0lil = '1' ELSE wire_n11i0O0O_dataout; + wire_n11i0l1i_dataout <= wire_n11i0lil_dataout AND NOT(n11O0lOi); + wire_n11i0l1l_dataout <= wire_n11i0liO_dataout OR n11O0lOi; + wire_n11i0l1O_dataout <= wire_n11i0lli_dataout AND NOT(n11O0lOi); + wire_n11i0li_dataout <= nlOi10li WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(24); + wire_n11i0lii_dataout <= wire_n11l1iOl_dataout WHEN n11O0lil = '1' ELSE wire_n11i0Oii_dataout; + wire_n11i0lil_dataout <= wire_n11l1iOO_dataout WHEN n11O0lil = '1' ELSE wire_n11i0Oil_dataout; + wire_n11i0liO_dataout <= wire_n11l1l1i_dataout WHEN n11O0lil = '1' ELSE wire_n11i0OiO_dataout; + wire_n11i0ll_dataout <= nlOi10ll WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(25); + wire_n11i0lli_dataout <= wire_n11l1l1l_dataout WHEN n11O0lil = '1' ELSE wire_n11i0Oli_dataout; + wire_n11i0lll_dataout <= k_conf(340) WHEN n11O0lil = '1' ELSE wire_n11i0O1l_dataout; + wire_n11i0llO_dataout <= k_conf(341) WHEN n11O0lil = '1' ELSE wire_n11i0O1O_dataout; + wire_n11i0lO_dataout <= nlOi10lO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(26); + wire_n11i0lOi_dataout <= k_conf(342) WHEN n11O0lil = '1' ELSE wire_n11i0O0i_dataout; + wire_n11i0lOl_dataout <= k_conf(343) WHEN n11O0lil = '1' ELSE wire_n11i0O0l_dataout; + wire_n11i0lOO_dataout <= wire_n11i0Oll_dataout AND NOT(n11O0lil); + wire_n11i0O0i_dataout <= n110OOli WHEN n11O0llO = '1' ELSE wire_n11i0OOO_dataout; + wire_n11i0O0l_dataout <= n110OOll WHEN n11O0llO = '1' ELSE wire_n11ii11i_dataout; + wire_n11i0O0O_dataout <= wire_n11ii11l_dataout AND NOT(n11O0llO); + wire_n11i0O1i_dataout <= n110OOii WHEN n11O0llO = '1' ELSE wire_n11i0OlO_dataout; + wire_n11i0O1l_dataout <= n110OOil WHEN n11O0llO = '1' ELSE wire_n11i0OOi_dataout; + wire_n11i0O1O_dataout <= n110OOiO WHEN n11O0llO = '1' ELSE wire_n11i0OOl_dataout; + wire_n11i0Oi_dataout <= nlOi10Oi WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(27); + wire_n11i0Oii_dataout <= wire_n11ii11O_dataout AND NOT(n11O0llO); + wire_n11i0Oil_dataout <= wire_n11l1iil_dataout WHEN n11O0llO = '1' ELSE wire_n11ii10i_dataout; + wire_n11i0OiO_dataout <= wire_n11ii10l_dataout AND NOT(n11O0llO); + wire_n11i0Ol_dataout <= nlOi10Ol WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(28); + wire_n11i0Oli_dataout <= wire_n11l1iiO_dataout WHEN n11O0llO = '1' ELSE wire_n11ii10O_dataout; + wire_n11i0Oll_dataout <= wire_n11ii1ii_dataout AND NOT(n11O0llO); + wire_n11i0OlO_dataout <= n110OOii WHEN n11O0lll = '1' ELSE wire_n11ii1il_dataout; + wire_n11i0OO_dataout <= nlOi10OO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(29); + wire_n11i0OOi_dataout <= n110OOil WHEN n11O0lll = '1' ELSE wire_n11ii1iO_dataout; + wire_n11i0OOl_dataout <= n110OOiO WHEN n11O0lll = '1' ELSE wire_n11ii1li_dataout; + wire_n11i0OOO_dataout <= n110OOli WHEN n11O0lll = '1' ELSE wire_n11ii1ll_dataout; + wire_n11i100i_dataout <= wire_n11i100O_dataout WHEN n11O0O1O = '1' ELSE wire_n11i100l_dataout; + wire_n11i100l_dataout <= n110OOOi OR niOl010Oi; + wire_n11i100O_dataout <= wire_n11i10ii_dataout OR NOT(niOli1iOO); + wire_n11i101i_dataout <= wire_n11i1iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i101l_dataout <= wire_n11i1l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i101O_dataout <= wire_n11i100i_dataout AND NOT((((n11O0O1l AND n1lillil) AND nlOO0ii1i) AND niOl0iO1i)); + wire_n11i10i_dataout <= nlOi110i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(3); + wire_n11i10ii_dataout <= n110OOOi OR niOl010Ol; + wire_n11i10l_dataout <= nlOi110l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(4); + wire_n11i10ll_dataout <= wire_n11i10OO_dataout WHEN n11O0O1O = '1' ELSE wire_n11i10lO_dataout; + wire_n11i10lO_dataout <= n110OOOl OR niOl010Oi; + wire_n11i10O_dataout <= nlOi110O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(5); + wire_n11i10OO_dataout <= wire_n11i1i1i_dataout AND niOO10lOO; + wire_n11i110l_dataout <= wire_n11i1l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i110O_dataout <= wire_n11i1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11i_dataout <= nlOi111i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(0); + wire_n11i11ii_dataout <= wire_n11i1iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11il_dataout <= wire_n11i1ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11iO_dataout <= wire_n11i1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11l_dataout <= nlOi111l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(1); + wire_n11i11li_dataout <= wire_n11i1ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11ll_dataout <= wire_n11i1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11lO_dataout <= wire_n11i101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11O_dataout <= nlOi111O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(2); + wire_n11i11Oi_dataout <= wire_n11i10ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11Ol_dataout <= wire_n11i1iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i11OO_dataout <= wire_n11i1iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11i1i1i_dataout <= wire_n11i1i1l_dataout AND NOT(niOl0iO1l); + wire_n11i1i1l_dataout <= wire_n11i1i1O_dataout OR NOT(niOli1iOO); + wire_n11i1i1O_dataout <= n110OOOl OR niOl010Ol; + wire_n11i1ii_dataout <= nlOi11ii WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(6); + wire_n11i1iii_dataout <= n110OOii WHEN n11O0Oil = '1' ELSE wire_n11i1l1O_dataout; + wire_n11i1iil_dataout <= n110OOlO WHEN n11O0Oil = '1' ELSE wire_n11i1l0i_dataout; + wire_n11i1iiO_dataout <= n110OOil WHEN n11O0Oil = '1' ELSE wire_n11i1l0l_dataout; + wire_n11i1il_dataout <= nlOi11il WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(7); + wire_n11i1ili_dataout <= n110OOiO WHEN n11O0Oil = '1' ELSE wire_n11i1l0O_dataout; + wire_n11i1ill_dataout <= n110OOli WHEN n11O0Oil = '1' ELSE wire_n11i1lii_dataout; + wire_n11i1ilO_dataout <= n110OOll WHEN n11O0Oil = '1' ELSE wire_n11i1lil_dataout; + wire_n11i1iO_dataout <= nlOi11iO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(8); + wire_n11i1iOi_dataout <= wire_n11l0iOO_dataout WHEN n11O0Oil = '1' ELSE wire_n11i1liO_dataout; + wire_n11i1iOl_dataout <= wire_n11l0l1i_dataout WHEN n11O0Oil = '1' ELSE wire_n11i1lli_dataout; + wire_n11i1iOO_dataout <= wire_n11l0l1l_dataout WHEN n11O0Oil = '1' ELSE wire_n11i1lll_dataout; + wire_n11i1l0i_dataout <= n110OOlO WHEN n11O0Oii = '1' ELSE wire_n11i1lOO_dataout; + wire_n11i1l0l_dataout <= n110OOil WHEN n11O0Oii = '1' ELSE wire_n11i1O1l_dataout; + wire_n11i1l0O_dataout <= n110OOiO WHEN n11O0Oii = '1' ELSE wire_n11i1O1O_dataout; + wire_n11i1l1i_dataout <= wire_n11l0l1O_dataout WHEN n11O0Oil = '1' ELSE wire_n11i1llO_dataout; + wire_n11i1l1l_dataout <= wire_n11i1lOi_dataout AND NOT(n11O0Oil); + wire_n11i1l1O_dataout <= n110OOii WHEN n11O0Oii = '1' ELSE wire_n11i1lOl_dataout; + wire_n11i1li_dataout <= nlOi11li WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(9); + wire_n11i1lii_dataout <= n110OOli WHEN n11O0Oii = '1' ELSE wire_n11i1O0i_dataout; + wire_n11i1lil_dataout <= n110OOll WHEN n11O0Oii = '1' ELSE wire_n11i1O0l_dataout; + wire_n11i1liO_dataout <= wire_n11l0i0O_dataout WHEN n11O0Oii = '1' ELSE wire_n11i1O0O_dataout; + wire_n11i1ll_dataout <= nlOi11ll WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(10); + wire_n11i1lli_dataout <= wire_n11l0iii_dataout WHEN n11O0Oii = '1' ELSE wire_n11i1Oii_dataout; + wire_n11i1lll_dataout <= wire_n11l0iil_dataout WHEN n11O0Oii = '1' ELSE wire_n11i1Oil_dataout; + wire_n11i1llO_dataout <= wire_n11l0iiO_dataout WHEN n11O0Oii = '1' ELSE wire_n11i1OiO_dataout; + wire_n11i1lO_dataout <= nlOi11lO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(11); + wire_n11i1lOi_dataout <= wire_n11i1O1i_dataout AND NOT(n11O0Oii); + wire_n11i1lOl_dataout <= n110OOii WHEN n11O0O0O = '1' ELSE wire_n11i1Oli_dataout; + wire_n11i1lOO_dataout <= n110OOlO WHEN n11O0O0O = '1' ELSE wire_n11i1Oll_dataout; + wire_n11i1O0i_dataout <= wire_n11i1OOl_dataout AND NOT(n11O0O0O); + wire_n11i1O0l_dataout <= wire_n11i1OOO_dataout OR n11O0O0O; + wire_n11i1O0O_dataout <= wire_n11l00OO_dataout WHEN n11O0O0O = '1' ELSE wire_n11i011i_dataout; + wire_n11i1O1i_dataout <= wire_n11i010l_dataout AND NOT(n11O0O0O); + wire_n11i1O1l_dataout <= wire_n11i1OlO_dataout AND NOT(n11O0O0O); + wire_n11i1O1O_dataout <= wire_n11i1OOi_dataout AND NOT(n11O0O0O); + wire_n11i1Oi_dataout <= nlOi11Oi WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(12); + wire_n11i1Oii_dataout <= wire_n11l0i1i_dataout WHEN n11O0O0O = '1' ELSE wire_n11i011l_dataout; + wire_n11i1Oil_dataout <= wire_n11l0i1l_dataout WHEN n11O0O0O = '1' ELSE wire_n11i011O_dataout; + wire_n11i1OiO_dataout <= wire_n11l0i1O_dataout WHEN n11O0O0O = '1' ELSE wire_n11i010i_dataout; + wire_n11i1Ol_dataout <= nlOi11Ol WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(13); + wire_n11i1Oli_dataout <= n110OOii WHEN n11O0O0i = '1' ELSE wire_n11i010O_dataout; + wire_n11i1Oll_dataout <= n110OOlO WHEN n11O0O0i = '1' ELSE wire_n11i01ii_dataout; + wire_n11i1OlO_dataout <= n110OOil WHEN n11O0O0i = '1' ELSE wire_n11i01iO_dataout; + wire_n11i1OO_dataout <= nlOi11OO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(14); + wire_n11i1OOi_dataout <= n110OOiO WHEN n11O0O0i = '1' ELSE wire_n11i01li_dataout; + wire_n11i1OOl_dataout <= n110OOli WHEN n11O0O0i = '1' ELSE wire_n11i01ll_dataout; + wire_n11i1OOO_dataout <= n110OOll WHEN n11O0O0i = '1' ELSE wire_n11i01lO_dataout; + wire_n11ii00i_dataout <= n110OOii WHEN niOl01l0i = '1' ELSE wire_n11ii0Ol_dataout; + wire_n11ii00l_dataout <= n110OOil WHEN niOl01l0i = '1' ELSE wire_n11ii0OO_dataout; + wire_n11ii00O_dataout <= n110OOiO WHEN niOl01l0i = '1' ELSE wire_n11iii1i_dataout; + wire_n11ii01i_dataout <= wire_n11l11iO_dataout WHEN n11O0lli = '1' ELSE wire_n11ii0ll_dataout; + wire_n11ii01l_dataout <= wire_n11l11li_dataout WHEN n11O0lli = '1' ELSE wire_n11ii0lO_dataout; + wire_n11ii01O_dataout <= wire_n11ii0Oi_dataout AND NOT(n11O0lli); + wire_n11ii0i_dataout <= nlOi1i0i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(33); + wire_n11ii0ii_dataout <= n110OOli WHEN niOl01l0i = '1' ELSE wire_n11iii1l_dataout; + wire_n11ii0il_dataout <= n110OOll WHEN niOl01l0i = '1' ELSE wire_n11iii1O_dataout; + wire_n11ii0iO_dataout <= wire_n11iii0i_dataout AND NOT(niOl01l0i); + wire_n11ii0l_dataout <= nlOi1i0l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(34); + wire_n11ii0li_dataout <= niOl01l0l WHEN niOl01l0i = '1' ELSE wire_n11iii0l_dataout; + wire_n11ii0ll_dataout <= wire_w_lg_niOl01l0l23485w(0) WHEN niOl01l0i = '1' ELSE wire_n11iii0O_dataout; + wire_n11ii0lO_dataout <= wire_n11iiiii_dataout AND NOT(niOl01l0i); + wire_n11ii0O_dataout <= nlOi1i0O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(35); + wire_n11ii0Oi_dataout <= wire_n11iiiil_dataout AND NOT(niOl01l0i); + wire_n11ii0Ol_dataout <= n110OOii WHEN n11O0lii = '1' ELSE wire_n11iiiiO_dataout; + wire_n11ii0OO_dataout <= n110OOil WHEN n11O0lii = '1' ELSE wire_n11iiili_dataout; + wire_n11ii10i_dataout <= wire_n11l100l_dataout WHEN n11O0lll = '1' ELSE wire_n11ii1OO_dataout; + wire_n11ii10l_dataout <= wire_n11l100O_dataout WHEN n11O0lll = '1' ELSE wire_n11ii01i_dataout; + wire_n11ii10O_dataout <= wire_n11l10ii_dataout WHEN n11O0lll = '1' ELSE wire_n11ii01l_dataout; + wire_n11ii11i_dataout <= n110OOll WHEN n11O0lll = '1' ELSE wire_n11ii1lO_dataout; + wire_n11ii11l_dataout <= wire_n11ii1Oi_dataout AND NOT(n11O0lll); + wire_n11ii11O_dataout <= wire_n11l100i_dataout WHEN n11O0lll = '1' ELSE wire_n11ii1Ol_dataout; + wire_n11ii1i_dataout <= nlOi1i1i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(30); + wire_n11ii1ii_dataout <= wire_n11ii01O_dataout AND NOT(n11O0lll); + wire_n11ii1il_dataout <= n110OOii WHEN n11O0lli = '1' ELSE wire_n11ii00i_dataout; + wire_n11ii1iO_dataout <= n110OOil WHEN n11O0lli = '1' ELSE wire_n11ii00l_dataout; + wire_n11ii1l_dataout <= nlOi1i1l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(31); + wire_n11ii1li_dataout <= n110OOiO WHEN n11O0lli = '1' ELSE wire_n11ii00O_dataout; + wire_n11ii1ll_dataout <= n110OOli WHEN n11O0lli = '1' ELSE wire_n11ii0ii_dataout; + wire_n11ii1lO_dataout <= n110OOll WHEN n11O0lli = '1' ELSE wire_n11ii0il_dataout; + wire_n11ii1O_dataout <= nlOi1i1O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(32); + wire_n11ii1Oi_dataout <= wire_n11l110O_dataout WHEN n11O0lli = '1' ELSE n110OOlO; + wire_n11ii1Ol_dataout <= wire_n11l11ii_dataout WHEN n11O0lli = '1' ELSE wire_n11ii0iO_dataout; + wire_n11ii1OO_dataout <= wire_n11l11il_dataout WHEN n11O0lli = '1' ELSE wire_n11ii0li_dataout; + wire_n11iii0i_dataout <= wire_n11iOO1l_dataout WHEN n11O0lii = '1' ELSE wire_n11iiiOl_dataout; + wire_n11iii0l_dataout <= wire_n11iOO1O_dataout WHEN n11O0lii = '1' ELSE wire_n11iiiOO_dataout; + wire_n11iii0O_dataout <= wire_n11iOO0i_dataout WHEN n11O0lii = '1' ELSE wire_n11iil1i_dataout; + wire_n11iii1i_dataout <= n110OOiO WHEN n11O0lii = '1' ELSE wire_n11iiill_dataout; + wire_n11iii1l_dataout <= n110OOli WHEN n11O0lii = '1' ELSE wire_n11iiilO_dataout; + wire_n11iii1O_dataout <= n110OOll WHEN n11O0lii = '1' ELSE wire_n11iiiOi_dataout; + wire_n11iiii_dataout <= nlOi1iii WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(36); + wire_n11iiiii_dataout <= wire_n11iOO0l_dataout WHEN n11O0lii = '1' ELSE wire_n11iil1l_dataout; + wire_n11iiiil_dataout <= wire_n11iil1O_dataout AND NOT(n11O0lii); + wire_n11iiiiO_dataout <= n110OOii WHEN n11O0l1O = '1' ELSE wire_n11iil0i_dataout; + wire_n11iiil_dataout <= nlOi1iil WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(37); + wire_n11iiili_dataout <= n110OOil WHEN n11O0l1O = '1' ELSE wire_n11iiliO_dataout; + wire_n11iiill_dataout <= n110OOiO WHEN n11O0l1O = '1' ELSE wire_n11iilli_dataout; + wire_n11iiilO_dataout <= n110OOli WHEN n11O0l1O = '1' ELSE wire_n11iilll_dataout; + wire_n11iiiO_dataout <= nlOi1iiO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(38); + wire_n11iiiOi_dataout <= n110OOll WHEN n11O0l1O = '1' ELSE wire_n11iillO_dataout; + wire_n11iiiOl_dataout <= wire_n11iOl1i_dataout WHEN n11O0l1O = '1' ELSE wire_n11iil0l_dataout; + wire_n11iiiOO_dataout <= wire_n11iOl1l_dataout WHEN n11O0l1O = '1' ELSE wire_n11iil0O_dataout; + wire_n11iil0i_dataout <= n110OOii WHEN n11O0l0O = '1' ELSE wire_n11iilOl_dataout; + wire_n11iil0l_dataout <= wire_n11iO10i_dataout WHEN n11O0l0O = '1' ELSE wire_n11iiO0l_dataout; + wire_n11iil0O_dataout <= wire_n11iO10l_dataout WHEN n11O0l0O = '1' ELSE wire_n11iiO0O_dataout; + wire_n11iil1i_dataout <= wire_n11iOl1O_dataout WHEN n11O0l1O = '1' ELSE wire_n11iilii_dataout; + wire_n11iil1l_dataout <= wire_n11iOl0i_dataout WHEN n11O0l1O = '1' ELSE wire_n11iilil_dataout; + wire_n11iil1O_dataout <= wire_n11iilOi_dataout AND NOT(n11O0l1O); + wire_n11iili_dataout <= nlOi1ili WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(39); + wire_n11iilii_dataout <= wire_n11iO10O_dataout WHEN n11O0l0O = '1' ELSE wire_n11iiOii_dataout; + wire_n11iilil_dataout <= wire_n11iO1ii_dataout WHEN n11O0l0O = '1' ELSE wire_n11iiOil_dataout; + wire_n11iiliO_dataout <= wire_n11iilOO_dataout AND NOT(n11O0l0O); + wire_n11iill_dataout <= nlOi1ill WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(40); + wire_n11iilli_dataout <= wire_n11iiO1i_dataout AND NOT(n11O0l0O); + wire_n11iilll_dataout <= wire_n11iiO1l_dataout AND NOT(n11O0l0O); + wire_n11iillO_dataout <= wire_n11iiO1O_dataout OR n11O0l0O; + wire_n11iilO_dataout <= nlOi1ilO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(41); + wire_n11iilOi_dataout <= wire_n11iiO0i_dataout AND NOT(n11O0l0O); + wire_n11iilOl_dataout <= n110OOii WHEN n11O0l0l = '1' ELSE wire_n11iiOiO_dataout; + wire_n11iilOO_dataout <= wire_n11iiOli_dataout AND NOT(n11O0l0l); + wire_n11iiO0i_dataout <= wire_n11il11O_dataout AND NOT(n11O0l0l); + wire_n11iiO0l_dataout <= wire_n11ilOOO_dataout WHEN n11O0l0l = '1' ELSE wire_n11iiOOl_dataout; + wire_n11iiO0O_dataout <= wire_n11iO11i_dataout WHEN n11O0l0l = '1' ELSE wire_n11iiOOO_dataout; + wire_n11iiO1i_dataout <= wire_n11iiOll_dataout AND NOT(n11O0l0l); + wire_n11iiO1l_dataout <= wire_n11iiOlO_dataout AND NOT(n11O0l0l); + wire_n11iiO1O_dataout <= wire_n11iiOOi_dataout OR n11O0l0l; + wire_n11iiOi_dataout <= nlOi1iOi WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(42); + wire_n11iiOii_dataout <= wire_n11iO11l_dataout WHEN n11O0l0l = '1' ELSE wire_n11il11i_dataout; + wire_n11iiOil_dataout <= wire_n11iO11O_dataout WHEN n11O0l0l = '1' ELSE wire_n11il11l_dataout; + wire_n11iiOiO_dataout <= n110OOii WHEN n11O0l0i = '1' ELSE wire_n11il1il_dataout; + wire_n11iiOl_dataout <= nlOi1iOl WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(43); + wire_n11iiOli_dataout <= wire_n11ililO_dataout WHEN n11O0l0i = '1' ELSE n110OOil; + wire_n11iiOll_dataout <= wire_n11iliOi_dataout WHEN n11O0l0i = '1' ELSE n110OOiO; + wire_n11iiOlO_dataout <= wire_n11iliOl_dataout WHEN n11O0l0i = '1' ELSE n110OOli; + wire_n11iiOO_dataout <= nlOi1iOO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(44); + wire_n11iiOOi_dataout <= wire_n11iliOO_dataout WHEN n11O0l0i = '1' ELSE n110OOll; + wire_n11iiOOl_dataout <= wire_n11ill1i_dataout WHEN n11O0l0i = '1' ELSE wire_n11il10i_dataout; + wire_n11iiOOO_dataout <= wire_n11ill1l_dataout WHEN n11O0l0i = '1' ELSE wire_n11il10l_dataout; + wire_n11il00i_dataout <= wire_w_lg_niOl00iiO23552w(0) WHEN niOl010OO = '1' ELSE n11i111l; + wire_n11il00l_dataout <= n11i111O AND NOT(niOl010OO); + wire_n11il01i_dataout <= n1101lli AND NOT(niOl010OO); + wire_n11il01l_dataout <= n110OOOO AND NOT(niOl010OO); + wire_n11il01O_dataout <= niOl00iiO WHEN niOl010OO = '1' ELSE n11i111i; + wire_n11il0i_dataout <= nlOi1l0i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(48); + wire_n11il0l_dataout <= nlOi1l0l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(49); + wire_n11il0li_dataout <= n110OOii OR wire_w_lg_niOli1iOl20954w(0); + wire_n11il0ll_dataout <= n110OOii OR NOT(wire_w_lg_niOli1iOl20954w(0)); + wire_n11il0lO_dataout <= wire_niO01ill_w_lg_n110OOii23546w(0) AND wire_w_lg_niOli1iOl20954w(0); + wire_n11il0O_dataout <= nlOi1l0O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(50); + wire_n11il10i_dataout <= wire_n11ili1i_dataout WHEN niOl01i0i = '1' ELSE wire_n11il1ll_dataout; + wire_n11il10l_dataout <= wire_n11ili1l_dataout WHEN niOl01i0i = '1' ELSE wire_n11il1lO_dataout; + wire_n11il10O_dataout <= wire_n11ili1O_dataout WHEN niOl01i0i = '1' ELSE wire_n11il1Oi_dataout; + wire_n11il11i_dataout <= wire_n11ill1O_dataout WHEN n11O0l0i = '1' ELSE wire_n11il10O_dataout; + wire_n11il11l_dataout <= wire_n11ill0i_dataout WHEN n11O0l0i = '1' ELSE wire_n11il1ii_dataout; + wire_n11il11O_dataout <= wire_n11ill0l_dataout WHEN n11O0l0i = '1' ELSE wire_n11il1iO_dataout; + wire_n11il1i_dataout <= nlOi1l1i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(45); + wire_n11il1ii_dataout <= wire_n11ili0i_dataout WHEN niOl01i0i = '1' ELSE wire_n11il1Ol_dataout; + wire_n11il1il_dataout <= wire_n11il1li_dataout AND NOT(niOl01i0i); + wire_n11il1iO_dataout <= wire_n11il1OO_dataout AND NOT(niOl01i0i); + wire_n11il1l_dataout <= nlOi1l1l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(46); + wire_n11il1li_dataout <= wire_n11il0li_dataout WHEN niOl01i1i = '1' ELSE n110OOii; + wire_n11il1ll_dataout <= wire_n11il01l_dataout OR niOl01i1i; + wire_n11il1lO_dataout <= wire_n11il01O_dataout AND NOT(niOl01i1i); + wire_n11il1O_dataout <= nlOi1l1O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(47); + wire_n11il1Oi_dataout <= wire_n11il0ll_dataout WHEN niOl01i1i = '1' ELSE wire_n11il00i_dataout; + wire_n11il1Ol_dataout <= wire_n11il0lO_dataout WHEN niOl01i1i = '1' ELSE wire_n11il00l_dataout; + wire_n11il1OO_dataout <= wire_n11il01i_dataout AND NOT(niOl01i1i); + wire_n11ili0i_dataout <= n11li1li WHEN niOl01i1O = '1' ELSE wire_n11iliil_dataout; + wire_n11ili0l_dataout <= n110OOOO AND NOT(niOl01i0l); + wire_n11ili0O_dataout <= n11i111i AND NOT(niOl01i0l); + wire_n11ili1i_dataout <= wire_n11ili0l_dataout AND NOT(niOl01i1O); + wire_n11ili1l_dataout <= wire_n11ili0O_dataout OR niOl01i1O; + wire_n11ili1O_dataout <= wire_n11iliii_dataout OR niOl01i1O; + wire_n11ilii_dataout <= nlOi1lii WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(51); + wire_n11iliii_dataout <= n11i111l AND NOT(niOl01i0l); + wire_n11iliil_dataout <= n11i111O AND NOT(niOl01i0l); + wire_n11ilil_dataout <= nlOi1lil WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(52); + wire_n11ililO_dataout <= wire_n11ilO0l_dataout WHEN niOl01iii = '1' ELSE wire_n11illll_dataout; + wire_n11iliO_dataout <= nlOi1liO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(53); + wire_n11iliOi_dataout <= wire_n11ilO0O_dataout WHEN niOl01iii = '1' ELSE wire_n11illlO_dataout; + wire_n11iliOl_dataout <= wire_n11ilOii_dataout WHEN niOl01iii = '1' ELSE wire_n11illOi_dataout; + wire_n11iliOO_dataout <= wire_n11ilOil_dataout WHEN niOl01iii = '1' ELSE wire_n11illOl_dataout; + wire_n11ill0i_dataout <= wire_n11ilOlO_dataout WHEN niOl01iii = '1' ELSE wire_n11illiO_dataout; + wire_n11ill0l_dataout <= wire_n11illli_dataout OR niOl01iii; + wire_n11ill0O_dataout <= n110OOOO WHEN niOl01i0O = '1' ELSE wire_n11ili0l_dataout; + wire_n11ill1i_dataout <= wire_n11ilOiO_dataout WHEN niOl01iii = '1' ELSE wire_n11ill0O_dataout; + wire_n11ill1l_dataout <= wire_n11ilOli_dataout WHEN niOl01iii = '1' ELSE wire_n11illii_dataout; + wire_n11ill1O_dataout <= wire_n11ilOll_dataout WHEN niOl01iii = '1' ELSE wire_n11illil_dataout; + wire_n11illi_dataout <= nlOi1lli WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(54); + wire_n11illii_dataout <= n11i111i WHEN niOl01i0O = '1' ELSE wire_n11ili0O_dataout; + wire_n11illil_dataout <= n11i111l WHEN niOl01i0O = '1' ELSE wire_n11iliii_dataout; + wire_n11illiO_dataout <= n11i111O WHEN niOl01i0O = '1' ELSE wire_n11iliil_dataout; + wire_n11illl_dataout <= nlOi1lll WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(55); + wire_n11illli_dataout <= n1101lli WHEN niOl01i0O = '1' ELSE wire_n11illOO_dataout; + wire_n11illll_dataout <= wire_n11ilO1i_o(1) WHEN niOl01i0O = '1' ELSE n110OOil; + wire_n11illlO_dataout <= wire_n11ilO1i_o(2) WHEN niOl01i0O = '1' ELSE n110OOiO; + wire_n11illO_dataout <= nlOi1llO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(56); + wire_n11illOi_dataout <= wire_n11ilO1i_o(3) WHEN niOl01i0O = '1' ELSE n110OOli; + wire_n11illOl_dataout <= wire_n11ilO1i_o(4) WHEN niOl01i0O = '1' ELSE n110OOll; + wire_n11illOO_dataout <= n1101lli AND NOT(niOl01i0l); + wire_n11ilO0l_dataout <= wire_n11ilO1i_o(1) WHEN wire_w_lg_niOl01lll23467w(0) = '1' ELSE n110OOil; + wire_n11ilO0O_dataout <= wire_n11ilO1i_o(2) WHEN wire_w_lg_niOl01lll23467w(0) = '1' ELSE n110OOiO; + wire_n11ilOi_dataout <= nlOi1lOi WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(57); + wire_n11ilOii_dataout <= wire_n11ilO1i_o(3) WHEN wire_w_lg_niOl01lll23467w(0) = '1' ELSE n110OOli; + wire_n11ilOil_dataout <= wire_n11ilO1i_o(4) WHEN wire_w_lg_niOl01lll23467w(0) = '1' ELSE n110OOll; + wire_n11ilOiO_dataout <= n110OOOO AND NOT(wire_w_lg_niOl01lll23467w(0)); + wire_n11ilOl_dataout <= nlOi1lOl WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(58); + wire_n11ilOli_dataout <= n11i111i OR wire_w_lg_niOl01lll23467w(0); + wire_n11ilOll_dataout <= n11i111l OR wire_w_lg_niOl01lll23467w(0); + wire_n11ilOlO_dataout <= n11i111O AND NOT(wire_w_lg_niOl01lll23467w(0)); + wire_n11ilOO_dataout <= nlOi1lOO WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(59); + wire_n11ilOOO_dataout <= n110OOOO AND NOT(n1lillil); + wire_n11iO00l_dataout <= wire_n11iO0iO_dataout AND NOT(niOli11il); + wire_n11iO00O_dataout <= wire_n11iO0li_dataout OR niOli11il; + wire_n11iO0i_dataout <= nlOi1O0i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(63); + wire_n11iO0ii_dataout <= wire_n11iO0ll_dataout AND NOT(niOli11il); + wire_n11iO0il_dataout <= wire_n11iO0lO_dataout AND NOT(niOli11il); + wire_n11iO0iO_dataout <= wire_n11iO0Oi_dataout AND NOT(niOl01ilO); + wire_n11iO0li_dataout <= wire_n11iO0Ol_dataout OR niOl01ilO; + wire_n11iO0ll_dataout <= wire_n11iO0OO_dataout AND NOT(niOl01ilO); + wire_n11iO0lO_dataout <= wire_n11iOi1i_dataout AND NOT(niOl01ilO); + wire_n11iO0Oi_dataout <= wire_n11iOi1l_dataout AND NOT(niOl01ill); + wire_n11iO0Ol_dataout <= wire_n11iOi1O_dataout OR niOl01ill; + wire_n11iO0OO_dataout <= wire_n11iOi0i_dataout OR niOl01ill; + wire_n11iO10i_dataout <= wire_n11iO00l_dataout WHEN n1110Oii = '1' ELSE wire_n11iO1il_dataout; + wire_n11iO10l_dataout <= wire_n11iO00O_dataout WHEN n1110Oii = '1' ELSE wire_n11iO1iO_dataout; + wire_n11iO10O_dataout <= wire_n11iO0ii_dataout WHEN n1110Oii = '1' ELSE wire_n11iO1li_dataout; + wire_n11iO11i_dataout <= n11i111i OR n1lillil; + wire_n11iO11l_dataout <= n11i111l AND NOT(n1lillil); + wire_n11iO11O_dataout <= n1110Oii WHEN n1lillil = '1' ELSE n11i111O; + wire_n11iO1i_dataout <= nlOi1O1i WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(60); + wire_n11iO1ii_dataout <= wire_n11iO0il_dataout WHEN n1110Oii = '1' ELSE wire_n11iO1ll_dataout; + wire_n11iO1il_dataout <= wire_n11iO1lO_dataout AND NOT(niOl01iil); + wire_n11iO1iO_dataout <= wire_n11iO1Oi_dataout OR niOl01iil; + wire_n11iO1l_dataout <= nlOi1O1l WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(61); + wire_n11iO1li_dataout <= wire_n11iO1Ol_dataout OR niOl01iil; + wire_n11iO1ll_dataout <= n11li1li WHEN niOl01iil = '1' ELSE wire_n11iO1OO_dataout; + wire_n11iO1lO_dataout <= n110OOOO AND NOT(niOl01l1i); + wire_n11iO1O_dataout <= nlOi1O1O WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(62); + wire_n11iO1Oi_dataout <= n11i111i AND NOT(niOl01l1i); + wire_n11iO1Ol_dataout <= n11i111l AND NOT(niOl01l1i); + wire_n11iO1OO_dataout <= n11i111O AND NOT(niOl01l1i); + wire_n11iOi0i_dataout <= wire_n11iOiil_dataout AND NOT(niOl01ili); + wire_n11iOi0l_dataout <= wire_n11iOiiO_dataout AND NOT(niOl01ili); + wire_n11iOi0O_dataout <= n110OOOO AND NOT(niOl01iiO); + wire_n11iOi1i_dataout <= n11li1li WHEN niOl01ill = '1' ELSE wire_n11iOi0l_dataout; + wire_n11iOi1l_dataout <= wire_n11iOi0O_dataout AND NOT(niOl01ili); + wire_n11iOi1O_dataout <= wire_n11iOiii_dataout AND NOT(niOl01ili); + wire_n11iOii_dataout <= wire_n11Ol1l_dataout WHEN niOO00l0i = '1' ELSE nlOi111i; + wire_n11iOiii_dataout <= n11i111i OR niOl01iiO; + wire_n11iOiil_dataout <= n11i111l AND NOT(niOl01iiO); + wire_n11iOiiO_dataout <= n11i111O AND NOT(niOl01iiO); + wire_n11iOil_dataout <= wire_n11Ol1O_dataout WHEN niOO00l0i = '1' ELSE nlOi111l; + wire_n11iOiO_dataout <= wire_n11Ol0i_dataout WHEN niOO00l0i = '1' ELSE nlOi111O; + wire_n11iOl0i_dataout <= n11li1li WHEN niOl01iOl = '1' ELSE wire_n11iOlil_dataout; + wire_n11iOl0l_dataout <= wire_n11ilOOO_dataout AND NOT(niOl01iOi); + wire_n11iOl0O_dataout <= wire_n11iO11i_dataout AND NOT(niOl01iOi); + wire_n11iOl1i_dataout <= wire_n11iOl0l_dataout AND NOT(niOl01iOl); + wire_n11iOl1l_dataout <= wire_n11iOl0O_dataout OR niOl01iOl; + wire_n11iOl1O_dataout <= wire_n11iOlii_dataout OR niOl01iOl; + wire_n11iOli_dataout <= wire_n11Ol0l_dataout WHEN niOO00l0i = '1' ELSE nlOi110i; + wire_n11iOlii_dataout <= wire_n11iO11l_dataout AND NOT(niOl01iOi); + wire_n11iOlil_dataout <= wire_n11iOliO_dataout AND NOT(niOl01iOi); + wire_n11iOliO_dataout <= n11i111O AND NOT(n1lillil); + wire_n11iOll_dataout <= wire_n11Ol0O_dataout WHEN niOO00l0i = '1' ELSE nlOi110l; + wire_n11iOlO_dataout <= wire_n11Olii_dataout WHEN niOO00l0i = '1' ELSE nlOi110O; + wire_n11iOO0i_dataout <= wire_n11iOOil_dataout AND NOT(wire_niO01ill_w_lg_n11Oi10l20175w(0)); + wire_n11iOO0l_dataout <= wire_n11iOOiO_dataout AND NOT(wire_niO01ill_w_lg_n11Oi10l20175w(0)); + wire_n11iOO0O_dataout <= wire_n11iOOli_dataout AND NOT(niOl01l1l); + wire_n11iOO1l_dataout <= wire_n11iOO0O_dataout AND NOT(wire_niO01ill_w_lg_n11Oi10l20175w(0)); + wire_n11iOO1O_dataout <= wire_n11iOOii_dataout OR wire_niO01ill_w_lg_n11Oi10l20175w(0); + wire_n11iOOi_dataout <= wire_n11Olil_dataout WHEN niOO00l0i = '1' ELSE nlOi11ii; + wire_n11iOOii_dataout <= wire_n11iOOll_dataout OR niOl01l1l; + wire_n11iOOil_dataout <= wire_n11iOOlO_dataout OR niOl01l1l; + wire_n11iOOiO_dataout <= n11li1li WHEN niOl01l1l = '1' ELSE wire_n11iOOOi_dataout; + wire_n11iOOl_dataout <= wire_n11OliO_dataout WHEN niOO00l0i = '1' ELSE nlOi11il; + wire_n11iOOli_dataout <= n110OOOO AND NOT(niOl01iOO); + wire_n11iOOll_dataout <= n11i111i AND NOT(niOl01iOO); + wire_n11iOOlO_dataout <= n11i111l AND NOT(niOl01iOO); + wire_n11iOOO_dataout <= wire_n11Olli_dataout WHEN niOO00l0i = '1' ELSE nlOi11iO; + wire_n11iOOOi_dataout <= n11i111O AND NOT(niOl01iOO); + wire_n11l000i_dataout <= wire_n11l00il_dataout OR niOl01llO; + wire_n11l000l_dataout <= n110OOOO OR wire_w_lg_niOl0l10O23466w(0); + wire_n11l000O_dataout <= n11i111i OR wire_w_lg_niOl0l10O23466w(0); + wire_n11l001i_dataout <= wire_n11l000l_dataout OR niOl01llO; + wire_n11l001l_dataout <= wire_n11l000O_dataout OR niOl01llO; + wire_n11l001O_dataout <= wire_n11l00ii_dataout OR niOl01llO; + wire_n11l00i_dataout <= wire_n11OOOl_dataout WHEN niOO00l0i = '1' ELSE nlOi10Oi; + wire_n11l00ii_dataout <= n11i111l OR wire_w_lg_niOl0l10O23466w(0); + wire_n11l00il_dataout <= n11i111O AND NOT(wire_w_lg_niOl0l10O23466w(0)); + wire_n11l00l_dataout <= wire_n11OOOO_dataout WHEN niOO00l0i = '1' ELSE nlOi10Ol; + wire_n11l00O_dataout <= wire_n10111i_dataout WHEN niOO00l0i = '1' ELSE nlOi10OO; + wire_n11l00Oi_dataout <= n11li1li AND n11O00lO; + wire_n11l00OO_dataout <= n110OOOO AND NOT(niOl01lOO); + wire_n11l010i_dataout <= wire_w_lg_niOl01lll23467w(0) WHEN niOl01lOl = '1' ELSE wire_n11l01il_dataout; + wire_n11l010l_dataout <= wire_n11l01iO_dataout AND NOT(niOl01lOl); + wire_n11l010O_dataout <= wire_n11l01ll_dataout AND NOT(wire_niO01iOi_w_lg_n1il11Ol20649w(0)); + wire_n11l011i_dataout <= wire_n11ilOil_dataout WHEN niOl01lOl = '1' ELSE n110OOll; + wire_n11l011l_dataout <= wire_n11l010O_dataout AND NOT(niOl01lOl); + wire_n11l011O_dataout <= wire_w_lg_niOl01lll23467w(0) WHEN niOl01lOl = '1' ELSE wire_n11l01ii_dataout; + wire_n11l01i_dataout <= wire_n11OOll_dataout WHEN niOO00l0i = '1' ELSE nlOi10li; + wire_n11l01ii_dataout <= n11O00lO WHEN wire_niO01iOi_w_lg_n1il11Ol20649w(0) = '1' ELSE wire_n11l01lO_dataout; + wire_n11l01il_dataout <= n11O00lO WHEN wire_niO01iOi_w_lg_n1il11Ol20649w(0) = '1' ELSE wire_n11l01Oi_dataout; + wire_n11l01iO_dataout <= wire_n11l00Oi_dataout WHEN wire_niO01iOi_w_lg_n1il11Ol20649w(0) = '1' ELSE wire_n11l01Ol_dataout; + wire_n11l01l_dataout <= wire_n11OOlO_dataout WHEN niOO00l0i = '1' ELSE nlOi10ll; + wire_n11l01li_dataout <= wire_n11l01OO_dataout AND NOT(wire_niO01iOi_w_lg_n1il11Ol20649w(0)); + wire_n11l01ll_dataout <= wire_n11l001i_dataout WHEN niOl01lOi = '1' ELSE n110OOOO; + wire_n11l01lO_dataout <= wire_n11l001l_dataout WHEN niOl01lOi = '1' ELSE n11i111i; + wire_n11l01O_dataout <= wire_n11OOOi_dataout WHEN niOO00l0i = '1' ELSE nlOi10lO; + wire_n11l01Oi_dataout <= wire_n11l001O_dataout WHEN niOl01lOi = '1' ELSE n11i111l; + wire_n11l01Ol_dataout <= wire_n11l000i_dataout WHEN niOl01lOi = '1' ELSE n11i111O; + wire_n11l01OO_dataout <= n1101lli AND NOT(niOl01lOi); + wire_n11l0i0O_dataout <= wire_n11l0ili_dataout AND NOT(niOl01O1i); + wire_n11l0i1i_dataout <= n11i111i OR niOl01lOO; + wire_n11l0i1l_dataout <= n11i111l AND NOT(niOl01lOO); + wire_n11l0i1O_dataout <= n11i111O AND NOT(niOl01lOO); + wire_n11l0ii_dataout <= wire_n10111l_dataout WHEN niOO00l0i = '1' ELSE nlOi1i1i; + wire_n11l0iii_dataout <= wire_n11l0ill_dataout AND NOT(niOl01O1i); + wire_n11l0iil_dataout <= wire_n11l0ilO_dataout AND NOT(niOl01O1i); + wire_n11l0iiO_dataout <= wire_n11l0iOi_dataout AND NOT(niOl01O1i); + wire_n11l0il_dataout <= wire_n10111O_dataout WHEN niOO00l0i = '1' ELSE nlOi1i1l; + wire_n11l0ili_dataout <= n110OOOO OR niOl0iO0i; + wire_n11l0ill_dataout <= n11i111i AND NOT(niOl0iO0i); + wire_n11l0ilO_dataout <= n11i111l AND NOT(niOl0iO0i); + wire_n11l0iO_dataout <= wire_n10110i_dataout WHEN niOO00l0i = '1' ELSE nlOi1i1O; + wire_n11l0iOi_dataout <= n11i111O AND NOT(niOl0iO0i); + wire_n11l0iOO_dataout <= wire_n11l0l0i_dataout AND NOT(niOl01O0i); + wire_n11l0l0i_dataout <= wire_n11l0lil_dataout OR niOl01O1O; + wire_n11l0l0l_dataout <= wire_n11l0liO_dataout AND NOT(niOl01O1O); + wire_n11l0l0O_dataout <= wire_n11l0lli_dataout AND NOT(niOl01O1O); + wire_n11l0l1i_dataout <= wire_n11l0l0l_dataout OR niOl01O0i; + wire_n11l0l1l_dataout <= wire_n11l0l0O_dataout OR niOl01O0i; + wire_n11l0l1O_dataout <= n11li1li WHEN niOl01O0i = '1' ELSE wire_n11l0lii_dataout; + wire_n11l0li_dataout <= wire_n10110l_dataout WHEN niOO00l0i = '1' ELSE nlOi1i0i; + wire_n11l0lii_dataout <= wire_n11l0lll_dataout AND NOT(niOl01O1O); + wire_n11l0lil_dataout <= n110OOOO AND NOT(niOl01O1l); + wire_n11l0liO_dataout <= n11i111i AND NOT(niOl01O1l); + wire_n11l0ll_dataout <= wire_n10110O_dataout WHEN niOO00l0i = '1' ELSE nlOi1i0l; + wire_n11l0lli_dataout <= n11i111l AND NOT(niOl01O1l); + wire_n11l0lll_dataout <= n11i111O AND NOT(niOl01O1l); + wire_n11l0lO_dataout <= wire_n1011ii_dataout WHEN niOO00l0i = '1' ELSE nlOi1i0O; + wire_n11l0Oi_dataout <= wire_n1011il_dataout WHEN niOO00l0i = '1' ELSE nlOi1iii; + wire_n11l0Ol_dataout <= wire_n1011iO_dataout WHEN niOO00l0i = '1' ELSE nlOi1iil; + wire_n11l0OO_dataout <= wire_n1011li_dataout WHEN niOO00l0i = '1' ELSE nlOi1iiO; + wire_n11l100i_dataout <= wire_n11l10il_dataout AND NOT(niOl01l0O); + wire_n11l100l_dataout <= wire_n11l1i1l_dataout WHEN niOl01l0O = '1' ELSE wire_n11l10iO_dataout; + wire_n11l100O_dataout <= wire_w_lg_niOl01l0l23485w(0) WHEN niOl01l0O = '1' ELSE wire_n11l10li_dataout; + wire_n11l101i_dataout <= n11i111i AND NOT(n110OOlO); + wire_n11l101l_dataout <= n11i111l AND NOT(n110OOlO); + wire_n11l101O_dataout <= n11i111O AND NOT(n110OOlO); + wire_n11l10i_dataout <= wire_n11OlOl_dataout WHEN niOO00l0i = '1' ELSE nlOi11Oi; + wire_n11l10ii_dataout <= wire_n11l1i1O_dataout WHEN niOl01l0O = '1' ELSE wire_n11l10ll_dataout; + wire_n11l10il_dataout <= wire_n11l10lO_dataout AND NOT(niOl0iO0i); + wire_n11l10iO_dataout <= wire_n11l10Oi_dataout OR niOl0iO0i; + wire_n11l10l_dataout <= wire_n11OlOO_dataout WHEN niOO00l0i = '1' ELSE nlOi11Ol; + wire_n11l10li_dataout <= wire_n11iO11l_dataout OR niOl0iO0i; + wire_n11l10ll_dataout <= n11li1li WHEN niOl0iO0i = '1' ELSE wire_n11l10Ol_dataout; + wire_n11l10lO_dataout <= wire_n11l10OO_dataout WHEN n1lillil = '1' ELSE n110OOOO; + wire_n11l10O_dataout <= wire_n11OO1i_dataout WHEN niOO00l0i = '1' ELSE nlOi11OO; + wire_n11l10Oi_dataout <= wire_n11l10OO_dataout WHEN n1lillil = '1' ELSE n11i111i; + wire_n11l10Ol_dataout <= wire_n11l1i1i_dataout WHEN n1lillil = '1' ELSE n11i111O; + wire_n11l10OO_dataout <= wire_w_lg_niOli111l20301w(0) OR niOli101l; + wire_n11l110O_dataout <= n110OOlO OR n1lillil; + wire_n11l11i_dataout <= wire_n11Olll_dataout WHEN niOO00l0i = '1' ELSE nlOi11li; + wire_n11l11ii_dataout <= wire_n11l11ll_dataout WHEN n1lillil = '1' ELSE n110OOOO; + wire_n11l11il_dataout <= wire_n11l11lO_dataout WHEN n1lillil = '1' ELSE n11i111i; + wire_n11l11iO_dataout <= wire_n11l11Oi_dataout WHEN n1lillil = '1' ELSE n11i111l; + wire_n11l11l_dataout <= wire_n11OllO_dataout WHEN niOO00l0i = '1' ELSE nlOi11ll; + wire_n11l11li_dataout <= wire_n11l11Ol_dataout WHEN n1lillil = '1' ELSE n11i111O; + wire_n11l11ll_dataout <= wire_n11l11OO_dataout AND NOT(wire_niO01ill_w_lg_n110OOlO23486w(0)); + wire_n11l11lO_dataout <= wire_n11l101i_dataout OR wire_niO01ill_w_lg_n110OOlO23486w(0); + wire_n11l11O_dataout <= wire_n11OlOi_dataout WHEN niOO00l0i = '1' ELSE nlOi11lO; + wire_n11l11Oi_dataout <= wire_n11l101l_dataout OR wire_niO01ill_w_lg_n110OOlO23486w(0); + wire_n11l11Ol_dataout <= n11li1li WHEN wire_niO01ill_w_lg_n110OOlO23486w(0) = '1' ELSE wire_n11l101O_dataout; + wire_n11l11OO_dataout <= n110OOOO AND NOT(n110OOlO); + wire_n11l1i1i_dataout <= niOli111l AND NOT(niOli101l); + wire_n11l1i1l_dataout <= wire_n11l10OO_dataout AND niOl01l0l; + wire_n11l1i1O_dataout <= wire_n11l1i1i_dataout AND niOl01l0l; + wire_n11l1ii_dataout <= wire_n11OO1l_dataout WHEN niOO00l0i = '1' ELSE nlOi101i; + wire_n11l1iil_dataout <= wire_n11l1ili_dataout OR niOl01lil; + wire_n11l1iiO_dataout <= wire_n11l1ill_dataout AND NOT(niOl01lil); + wire_n11l1il_dataout <= wire_n11OO1O_dataout WHEN niOO00l0i = '1' ELSE nlOi101l; + wire_n11l1ili_dataout <= wire_w_lg_niOl01lli23469w(0) AND NOT(n11O0i0O); + wire_n11l1ill_dataout <= niOl01lli OR n11O0i0O; + wire_n11l1iO_dataout <= wire_n11OO0i_dataout WHEN niOO00l0i = '1' ELSE nlOi101O; + wire_n11l1iOl_dataout <= wire_n11iOOli_dataout AND NOT(niOl01liO); + wire_n11l1iOO_dataout <= wire_n11iOOll_dataout OR niOl01liO; + wire_n11l1l1i_dataout <= wire_n11iOOlO_dataout OR niOl01liO; + wire_n11l1l1l_dataout <= n11li1li WHEN niOl01liO = '1' ELSE wire_n11iOOOi_dataout; + wire_n11l1li_dataout <= wire_n11OO0l_dataout WHEN niOO00l0i = '1' ELSE nlOi100i; + wire_n11l1ll_dataout <= wire_n11OO0O_dataout WHEN niOO00l0i = '1' ELSE nlOi100l; + wire_n11l1lll_dataout <= wire_n11l1lOi_dataout OR NOT(wire_n1l10lli_w_lg_dataout21212w(0)); + wire_n11l1llO_dataout <= wire_n11l1lOl_dataout AND wire_n1l10lli_w_lg_dataout21212w(0); + wire_n11l1lO_dataout <= wire_n11OOii_dataout WHEN niOO00l0i = '1' ELSE nlOi100O; + wire_n11l1lOi_dataout <= wire_n11l1lOO_dataout AND NOT(n11O0i0O); + wire_n11l1lOl_dataout <= wire_n11l1O1i_dataout OR n11O0i0O; + wire_n11l1lOO_dataout <= wire_w_lg_niOl01lli23469w(0) OR niOli110O; + wire_n11l1O0i_dataout <= wire_n11l1OOi_dataout WHEN n1lillil = '1' ELSE n110OOil; + wire_n11l1O0l_dataout <= wire_n11l1OOl_dataout WHEN n1lillil = '1' ELSE n110OOiO; + wire_n11l1O0O_dataout <= wire_n11l1OOO_dataout WHEN n1lillil = '1' ELSE n110OOli; + wire_n11l1O1i_dataout <= niOl01lli AND NOT(niOli110O); + wire_n11l1O1O_dataout <= wire_n11l1OlO_dataout WHEN n1lillil = '1' ELSE n1101lli; + wire_n11l1Oi_dataout <= wire_n11OOil_dataout WHEN niOO00l0i = '1' ELSE nlOi10ii; + wire_n11l1Oii_dataout <= wire_n11l011i_dataout WHEN n1lillil = '1' ELSE n110OOll; + wire_n11l1Oil_dataout <= wire_n11l011l_dataout WHEN n1lillil = '1' ELSE n110OOOO; + wire_n11l1OiO_dataout <= wire_n11l011O_dataout WHEN n1lillil = '1' ELSE n11i111i; + wire_n11l1Ol_dataout <= wire_n11OOiO_dataout WHEN niOO00l0i = '1' ELSE nlOi10il; + wire_n11l1Oli_dataout <= wire_n11l010i_dataout WHEN n1lillil = '1' ELSE n11i111l; + wire_n11l1Oll_dataout <= wire_n11l010l_dataout WHEN n1lillil = '1' ELSE n11i111O; + wire_n11l1OlO_dataout <= wire_w_lg_niOl01lll23467w(0) WHEN niOl01lOl = '1' ELSE wire_n11l01li_dataout; + wire_n11l1OO_dataout <= wire_n11OOli_dataout WHEN niOO00l0i = '1' ELSE nlOi10iO; + wire_n11l1OOi_dataout <= wire_n11ilO0l_dataout WHEN niOl01lOl = '1' ELSE n110OOil; + wire_n11l1OOl_dataout <= wire_n11ilO0O_dataout WHEN niOl01lOl = '1' ELSE n110OOiO; + wire_n11l1OOO_dataout <= wire_n11ilOii_dataout WHEN niOl01lOl = '1' ELSE n110OOli; + wire_n11li00i_dataout <= wire_n11liiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li00l_dataout <= wire_n11liiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li00O_dataout <= wire_n11liiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li01i_dataout <= wire_n11lii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li01l_dataout <= wire_n11lii0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li01O_dataout <= wire_n11lii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0i_dataout <= wire_n1011Ol_dataout WHEN niOO00l0i = '1' ELSE nlOi1iOi; + wire_n11li0ii_dataout <= wire_n11liili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0il_dataout <= wire_n11liill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0iO_dataout <= wire_n11O1i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0l_dataout <= wire_n1011OO_dataout WHEN niOO00l0i = '1' ELSE nlOi1iOl; + wire_n11li0li_dataout <= wire_n11lOi1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0ll_dataout <= wire_n11lOi1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0lO_dataout <= wire_n11lOi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0O_dataout <= wire_n10101i_dataout WHEN niOO00l0i = '1' ELSE nlOi1iOO; + wire_n11li0Oi_dataout <= wire_n11lOi0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0Ol_dataout <= wire_n11ll0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li0OO_dataout <= wire_n11lli1O_dataout OR wire_niO01lOO_dataout; + wire_n11li1i_dataout <= wire_n1011ll_dataout WHEN niOO00l0i = '1' ELSE nlOi1ili; + wire_n11li1l_dataout <= wire_n1011lO_dataout WHEN niOO00l0i = '1' ELSE nlOi1ill; + wire_n11li1ll_dataout <= wire_n11lii1l_dataout OR wire_niO01lOO_dataout; + wire_n11li1lO_dataout <= wire_n11lii1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11li1O_dataout <= wire_n1011Oi_dataout WHEN niOO00l0i = '1' ELSE nlOi1ilO; + wire_n11li1Oi_dataout <= wire_n11lli0l_dataout OR wire_niO01lOO_dataout; + wire_n11li1Ol_dataout <= n11O00ll AND NOT(wire_niO01lOO_dataout); + wire_n11li1OO_dataout <= wire_n11lli0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11lii0i_dataout <= wire_n11liilO_dataout WHEN n1lillil = '1' ELSE n11l0Oli; + wire_n11lii0l_dataout <= wire_n11liiOi_dataout WHEN n1lillil = '1' ELSE n11l0Oll; + wire_n11lii0O_dataout <= wire_n11liiOl_dataout WHEN n1lillil = '1' ELSE n11l0OlO; + wire_n11lii1i_dataout <= wire_n11lli0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11lii1l_dataout <= n11l0O0O WHEN wire_niO01ill_w_lg_nlOlOiliO21217w(0) = '1' ELSE n11i110i; + wire_n11lii1O_dataout <= n11l0OiO WHEN wire_niO01ill_w_lg_nlOlOiliO21217w(0) = '1' ELSE n11l0Oil; + wire_n11liii_dataout <= wire_n10101l_dataout WHEN niOO00l0i = '1' ELSE nlOi1l1i; + wire_n11liiii_dataout <= wire_n11liiOO_dataout WHEN n1lillil = '1' ELSE n11l0OOi; + wire_n11liiil_dataout <= wire_n11lil1i_dataout WHEN n1lillil = '1' ELSE n11l0OOl; + wire_n11liiiO_dataout <= wire_n11lil1l_dataout WHEN n1lillil = '1' ELSE n11l0OOO; + wire_n11liil_dataout <= wire_n10101O_dataout WHEN niOO00l0i = '1' ELSE nlOi1l1l; + wire_n11liili_dataout <= wire_n11lil1O_dataout WHEN n1lillil = '1' ELSE n11li11i; + wire_n11liill_dataout <= wire_n11lil0i_dataout WHEN n1lillil = '1' ELSE n11li11l; + wire_n11liilO_dataout <= wire_n11lil0l_dataout AND n11O0llO; + wire_n11liiO_dataout <= wire_n10100i_dataout WHEN niOO00l0i = '1' ELSE nlOi1l1O; + wire_n11liiOi_dataout <= wire_n11lil0O_dataout OR NOT(n11O0llO); + wire_n11liiOl_dataout <= wire_n11lilii_dataout OR NOT(n11O0llO); + wire_n11liiOO_dataout <= wire_n11lilil_dataout OR NOT(n11O0llO); + wire_n11lil0i_dataout <= wire_n11ll1il_dataout OR NOT(n11O0llO); + wire_n11lil0l_dataout <= wire_n11liliO_dataout OR NOT(wire_niO01ill_w_lg_n11l0Oli23446w(0)); + wire_n11lil0O_dataout <= wire_n11lilli_dataout WHEN wire_niO01ill_w_lg_n11l0Oli23446w(0) = '1' ELSE n11l0Oll; + wire_n11lil1i_dataout <= wire_n11ll10l_dataout AND n11O0llO; + wire_n11lil1l_dataout <= wire_n11ll10O_dataout OR NOT(n11O0llO); + wire_n11lil1O_dataout <= wire_n11ll1ii_dataout OR NOT(n11O0llO); + wire_n11lili_dataout <= wire_n10100l_dataout WHEN niOO00l0i = '1' ELSE nlOi1l0i; + wire_n11lilii_dataout <= wire_n11lilll_dataout WHEN wire_niO01ill_w_lg_n11l0Oli23446w(0) = '1' ELSE n11l0OlO; + wire_n11lilil_dataout <= wire_n11lillO_dataout WHEN wire_niO01ill_w_lg_n11l0Oli23446w(0) = '1' ELSE n11l0OOi; + wire_n11liliO_dataout <= wire_n11lilOi_dataout WHEN niOl01Oil = '1' ELSE n11l0Oli; + wire_n11lill_dataout <= wire_n10100O_dataout WHEN niOO00l0i = '1' ELSE nlOi1l0l; + wire_n11lilli_dataout <= wire_n11lilOl_dataout OR NOT(niOl01Oil); + wire_n11lilll_dataout <= wire_n11lilOO_dataout OR NOT(niOl01Oil); + wire_n11lillO_dataout <= wire_n11liO1i_dataout OR NOT(niOl01Oil); + wire_n11lilO_dataout <= wire_n1010ii_dataout WHEN niOO00l0i = '1' ELSE nlOi1l0O; + wire_n11lilOi_dataout <= n11l0Oli WHEN wire_w_lg_niOl01Oii23445w(0) = '1' ELSE wire_n11liO1l_dataout; + wire_n11lilOl_dataout <= wire_n11ll01O_o(1) WHEN wire_w_lg_niOl01Oii23445w(0) = '1' ELSE n11l0Oll; + wire_n11lilOO_dataout <= wire_n11ll01O_o(2) WHEN wire_w_lg_niOl01Oii23445w(0) = '1' ELSE n11l0OlO; + wire_n11liO1i_dataout <= wire_n11ll01O_o(3) WHEN wire_w_lg_niOl01Oii23445w(0) = '1' ELSE n11l0OOi; + wire_n11liO1l_dataout <= n11l0Oli OR niOl01Oii; + wire_n11liOi_dataout <= wire_n1010il_dataout WHEN niOO00l0i = '1' ELSE nlOi1lii; + wire_n11liOl_dataout <= wire_n1010iO_dataout WHEN niOO00l0i = '1' ELSE nlOi1lil; + wire_n11liOO_dataout <= wire_n1010li_dataout WHEN niOO00l0i = '1' ELSE nlOi1liO; + wire_n11ll01i_dataout <= wire_n11ll01O_o(3) WHEN wire_w_lg_niOl01Oll23438w(0) = '1' ELSE n11li11l; + wire_n11ll01l_dataout <= n11l0OOl OR niOl01Oll; + wire_n11ll0i_dataout <= wire_n1010Ol_dataout WHEN niOO00l0i = '1' ELSE nlOi1lOi; + wire_n11ll0l_dataout <= wire_n1010OO_dataout WHEN niOO00l0i = '1' ELSE nlOi1lOl; + wire_n11ll0lO_dataout <= wire_n11lli1i_dataout WHEN n11O0llO = '1' ELSE wire_n11ll0Oi_dataout; + wire_n11ll0O_dataout <= wire_n101i1i_dataout WHEN niOO00l0i = '1' ELSE nlOi1lOO; + wire_n11ll0Oi_dataout <= n11O0iOi WHEN n11O0lll = '1' ELSE wire_n11ll0Ol_dataout; + wire_n11ll0Ol_dataout <= wire_n11ll0OO_dataout AND n11O0lli; + wire_n11ll0OO_dataout <= n11li1il AND NOT(niOl0l1iO); + wire_n11ll10l_dataout <= wire_n11ll1iO_dataout OR NOT(wire_niO01ill_w_lg_n11l0OOl23442w(0)); + wire_n11ll10O_dataout <= wire_n11ll1li_dataout WHEN wire_niO01ill_w_lg_n11l0OOl23442w(0) = '1' ELSE n11l0OOO; + wire_n11ll1i_dataout <= wire_n1010ll_dataout WHEN niOO00l0i = '1' ELSE nlOi1lli; + wire_n11ll1ii_dataout <= wire_n11ll1ll_dataout WHEN wire_niO01ill_w_lg_n11l0OOl23442w(0) = '1' ELSE n11li11i; + wire_n11ll1il_dataout <= wire_n11ll1lO_dataout WHEN wire_niO01ill_w_lg_n11l0OOl23442w(0) = '1' ELSE n11li11l; + wire_n11ll1iO_dataout <= wire_n11ll1Oi_dataout WHEN wire_w_lg_niOl01Oli23441w(0) = '1' ELSE n11l0OOl; + wire_n11ll1l_dataout <= wire_n1010lO_dataout WHEN niOO00l0i = '1' ELSE nlOi1lll; + wire_n11ll1li_dataout <= wire_n11ll1Ol_dataout OR NOT(wire_w_lg_niOl01Oli23441w(0)); + wire_n11ll1ll_dataout <= wire_n11ll1OO_dataout OR NOT(wire_w_lg_niOl01Oli23441w(0)); + wire_n11ll1lO_dataout <= wire_n11ll01i_dataout OR NOT(wire_w_lg_niOl01Oli23441w(0)); + wire_n11ll1O_dataout <= wire_n1010Oi_dataout WHEN niOO00l0i = '1' ELSE nlOi1llO; + wire_n11ll1Oi_dataout <= n11l0OOl WHEN wire_w_lg_niOl01Oll23438w(0) = '1' ELSE wire_n11ll01l_dataout; + wire_n11ll1Ol_dataout <= wire_n11ll01O_o(1) WHEN wire_w_lg_niOl01Oll23438w(0) = '1' ELSE n11l0OOO; + wire_n11ll1OO_dataout <= wire_n11ll01O_o(2) WHEN wire_w_lg_niOl01Oll23438w(0) = '1' ELSE n11li11i; + wire_n11lli0i_dataout <= wire_n11lO00l_dataout WHEN n11O0lli = '1' ELSE wire_n11lliil_dataout; + wire_n11lli0l_dataout <= wire_n11lO00O_dataout WHEN n11O0lli = '1' ELSE wire_n11lliiO_dataout; + wire_n11lli0O_dataout <= wire_n11lO0ii_dataout WHEN n11O0lli = '1' ELSE wire_n11llili_dataout; + wire_n11lli1i_dataout <= wire_n11lli1l_dataout AND NOT(n11Oi1il); + wire_n11lli1l_dataout <= n11li1il OR n11O0iOi; + wire_n11lli1O_dataout <= wire_n11lO00i_dataout WHEN n11O0lli = '1' ELSE wire_n11lliii_dataout; + wire_n11llii_dataout <= wire_n101i1l_dataout WHEN niOO00l0i = '1' ELSE nlOi1O1i; + wire_n11lliii_dataout <= wire_n11lO1li_dataout WHEN n11O0Oil = '1' ELSE wire_n11llill_dataout; + wire_n11lliil_dataout <= wire_n11lO1ll_dataout WHEN n11O0Oil = '1' ELSE wire_n11llilO_dataout; + wire_n11lliiO_dataout <= wire_n11lO1OO_dataout WHEN n11O0Oil = '1' ELSE wire_n11lliOi_dataout; + wire_n11llil_dataout <= wire_n101i1O_dataout WHEN niOO00l0i = '1' ELSE nlOi1O1l; + wire_n11llili_dataout <= wire_n11lO01i_dataout WHEN n11O0Oil = '1' ELSE wire_n11lliOl_dataout; + wire_n11llill_dataout <= wire_n11llOOi_dataout WHEN n11O0l0O = '1' ELSE wire_n11lliOO_dataout; + wire_n11llilO_dataout <= wire_n11llOOl_dataout WHEN n11O0l0O = '1' ELSE wire_n11lll1i_dataout; + wire_n11lliO_dataout <= wire_n101i0i_dataout WHEN niOO00l0i = '1' ELSE nlOi1O1O; + wire_n11lliOi_dataout <= wire_n11lO10i_dataout WHEN n11O0l0O = '1' ELSE wire_n11lll1O_dataout; + wire_n11lliOl_dataout <= wire_n11lO10l_dataout WHEN n11O0l0O = '1' ELSE wire_n11lll1l_dataout; + wire_n11lliOO_dataout <= wire_n11lll0i_dataout WHEN n11O0O0l = '1' ELSE n11li1iO; + wire_n11lll0i_dataout <= wire_n11llOii_dataout WHEN n11l0Oii = '1' ELSE wire_n11lllil_dataout; + wire_n11lll0l_dataout <= wire_n11llOil_dataout WHEN n11l0Oii = '1' ELSE wire_n11llliO_dataout; + wire_n11lll0O_dataout <= wire_n11llOll_dataout WHEN n11l0Oii = '1' ELSE wire_n11lllli_dataout; + wire_n11lll1i_dataout <= wire_n11lll0l_dataout WHEN n11O0O0l = '1' ELSE n11li1li; + wire_n11lll1l_dataout <= wire_n11lll0O_dataout WHEN n11O0O0l = '1' ELSE n11l0OiO; + wire_n11lll1O_dataout <= wire_n11lllii_dataout WHEN n11O0O0l = '1' ELSE n11l0O0O; + wire_n11llli_dataout <= wire_n101i0l_dataout WHEN niOO00l0i = '1' ELSE nlOi1O0i; + wire_n11lllii_dataout <= wire_n11llOlO_dataout WHEN n11l0Oii = '1' ELSE wire_n11lllll_dataout; + wire_n11lllil_dataout <= wire_n11llllO_dataout WHEN niOl01OlO = '1' ELSE n11li1iO; + wire_n11llliO_dataout <= wire_n11lllOi_dataout WHEN niOl01OlO = '1' ELSE n11li1li; + wire_n11llll_dataout <= wire_n101i0O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(64); + wire_n11lllli_dataout <= wire_n11llO1O_dataout WHEN niOl01OlO = '1' ELSE n11l0OiO; + wire_n11lllll_dataout <= wire_n11llO0i_dataout WHEN niOl01OlO = '1' ELSE n11l0O0O; + wire_n11llllO_dataout <= wire_n11lllOl_dataout AND NOT(niOl01OOi); + wire_n11lllO_dataout <= wire_n101iii_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(65); + wire_n11lllOi_dataout <= wire_n11lllOO_dataout OR niOl01OOi; + wire_n11lllOl_dataout <= n11li1iO AND NOT(n1il11ll); + wire_n11lllOO_dataout <= n11li1li OR n1il11ll; + wire_n11llO0i_dataout <= n11O0i0i WHEN niOl01OOl = '1' ELSE n11l0O0O; + wire_n11llO1O_dataout <= n11l0OiO OR niOl01OOl; + wire_n11llOi_dataout <= wire_n101iil_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(66); + wire_n11llOii_dataout <= wire_n11llOiO_dataout OR niOl01OOi; + wire_n11llOil_dataout <= wire_n11llOli_dataout AND NOT(niOl01OOi); + wire_n11llOiO_dataout <= n11li1iO OR n1il11ll; + wire_n11llOl_dataout <= wire_n101iiO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(67); + wire_n11llOli_dataout <= n11li1li AND NOT(n1il11ll); + wire_n11llOll_dataout <= n11l0OiO AND NOT(niOl01OOl); + wire_n11llOlO_dataout <= n11l0O0O OR niOl01OOl; + wire_n11llOO_dataout <= wire_n101ili_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(68); + wire_n11llOOi_dataout <= wire_niO01ill_w_lg_n11l0OiO23413w(0) WHEN niOl00OOl = '1' ELSE wire_n11llOOO_dataout; + wire_n11llOOl_dataout <= n11l0OiO WHEN niOl00OOl = '1' ELSE wire_n11lO11i_dataout; + wire_n11llOOO_dataout <= wire_niO01ill_w_lg_n11l0OiO23413w(0) WHEN n1il11Ol = '1' ELSE wire_n11lO11l_dataout; + wire_n11lO00i_dataout <= wire_niO01ill_w_lg_n11l0OiO23413w(0) WHEN niOl00OOi = '1' ELSE wire_n11llOOO_dataout; + wire_n11lO00l_dataout <= n11l0OiO WHEN niOl00OOi = '1' ELSE wire_n11lO11i_dataout; + wire_n11lO00O_dataout <= wire_n11lO0li_dataout WHEN n1il11OO = '1' ELSE wire_n11lO0il_dataout; + wire_n11lO01i_dataout <= wire_n11llOll_dataout WHEN niOl0010i = '1' ELSE n11l0OiO; + wire_n11lO0i_dataout <= wire_n101iOl_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(72); + wire_n11lO0ii_dataout <= wire_n11lO0ll_dataout WHEN n1il11OO = '1' ELSE wire_n11lO0iO_dataout; + wire_n11lO0il_dataout <= n11l0O0O OR niOl0l1li; + wire_n11lO0iO_dataout <= n11l0OiO AND NOT(niOl0l1li); + wire_n11lO0l_dataout <= wire_n101iOO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(73); + wire_n11lO0li_dataout <= wire_n11lO0OO_dataout WHEN n11O0ill = '1' ELSE wire_n11lO0lO_dataout; + wire_n11lO0ll_dataout <= niOl0010O WHEN n11O0ill = '1' ELSE wire_n11lO0Oi_dataout; + wire_n11lO0lO_dataout <= wire_n11lO0Ol_dataout OR NOT(n11O0ilO); + wire_n11lO0O_dataout <= wire_n101l1i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(74); + wire_n11lO0Oi_dataout <= niOl0010l AND n11O0ilO; + wire_n11lO0Ol_dataout <= n11O0i0i OR NOT(niOl0010l); + wire_n11lO0OO_dataout <= n11O0i0i OR NOT(niOl0010O); + wire_n11lO10i_dataout <= wire_n11lO10O_dataout WHEN niOl01OOl = '1' ELSE n11l0O0O; + wire_n11lO10l_dataout <= wire_n11lO1ii_dataout WHEN niOl01OOl = '1' ELSE n11l0OiO; + wire_n11lO10O_dataout <= wire_n11lO1il_dataout OR niOl01OOO; + wire_n11lO11i_dataout <= n11l0OiO WHEN n1il11Ol = '1' ELSE wire_n11lO11O_dataout; + wire_n11lO11l_dataout <= n11li1iO OR niOl0l1li; + wire_n11lO11O_dataout <= n11li1li AND NOT(niOl0l1li); + wire_n11lO1i_dataout <= wire_n101ill_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(69); + wire_n11lO1ii_dataout <= wire_n11lO1iO_dataout AND NOT(niOl01OOO); + wire_n11lO1il_dataout <= n11O0i0i WHEN niOl0011i = '1' ELSE n11l0O0O; + wire_n11lO1iO_dataout <= n11l0OiO OR niOl0011i; + wire_n11lO1l_dataout <= wire_n101ilO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(70); + wire_n11lO1li_dataout <= wire_n11lO1lO_dataout OR niOl0011l; + wire_n11lO1ll_dataout <= wire_n11lO1Oi_dataout AND NOT(niOl0011l); + wire_n11lO1lO_dataout <= n11li1iO OR n1il11Ol; + wire_n11lO1O_dataout <= wire_n101iOi_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(71); + wire_n11lO1Oi_dataout <= n11li1li AND NOT(n1il11Ol); + wire_n11lO1OO_dataout <= wire_n11llOlO_dataout WHEN niOl0010i = '1' ELSE n11l0O0O; + wire_n11lOi0i_dataout <= wire_n11O11il_dataout AND n11O0lll; + wire_n11lOi0l_dataout <= n11li10i OR ((((((((n1Oi1O1i AND n1Oi1l0l) OR (n011li0l AND n011l0iO)) OR (n01O01iO AND n01O1OOi)) OR (n00illOi AND n00ill1l)) OR (n0i00i1l AND n0i0000O)) OR (n0iOO10O AND n0iOlOli)) OR (n0ll0lli AND n0ll0iOl)) OR (n0O0O0Ol AND n0O0O01O)); + wire_n11lOi1i_dataout <= wire_n11lOi0l_dataout AND n11O0lll; + wire_n11lOi1l_dataout <= wire_n11lOl0O_dataout AND n11O0lll; + wire_n11lOi1O_dataout <= wire_n11lOOii_dataout AND n11O0lll; + wire_n11lOii_dataout <= wire_n101l1l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(75); + wire_n11lOil_dataout <= wire_n101l1O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(76); + wire_n11lOiO_dataout <= wire_n101l0i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(77); + wire_n11lOl0O_dataout <= n11li10l OR (((((((niOl001Ol OR niOl001Oi) OR niOl001lO) OR niOl001ll) OR niOl001li) OR niOl001iO) OR niOl001il) OR niOl001ii); + wire_n11lOli_dataout <= wire_n101l0l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(78); + wire_n11lOll_dataout <= wire_n101l0O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(79); + wire_n11lOlO_dataout <= wire_n101lii_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(80); + wire_n11lOOi_dataout <= wire_n101lil_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(81); + wire_n11lOOii_dataout <= n11li10O OR ((((((((wire_n11O1i1i_o AND n1Oi1O1i) OR (wire_n11O10Ol_o AND n011li0l)) OR (wire_n11O10ll_o AND n01O01iO)) OR (wire_n11O10il_o AND n00illOi)) OR (wire_n11O100l_o AND n0i00i1l)) OR (wire_n11O101l_o AND n0iOO10O)) OR (wire_n11O11Ol_o AND n0ll0lli)) OR (wire_n11O11ll_o AND n0O0O0Ol)); + wire_n11lOOl_dataout <= wire_n101liO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(82); + wire_n11lOOO_dataout <= wire_n101lli_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(83); + wire_n11O00i_dataout <= wire_n101OOl_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(102); + wire_n11O00l_dataout <= wire_n101OOO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(103); + wire_n11O00O_dataout <= wire_n10011i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(104); + wire_n11O01i_dataout <= wire_n101Oll_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(99); + wire_n11O01l_dataout <= wire_n101OlO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(100); + wire_n11O01O_dataout <= wire_n101OOi_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(101); + wire_n11O0ii_dataout <= wire_n10011l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(105); + wire_n11O0il_dataout <= wire_n10011O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(106); + wire_n11O0iO_dataout <= wire_n10010i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(107); + wire_n11O0li_dataout <= wire_n10010l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(108); + wire_n11O0ll_dataout <= wire_n10010O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(109); + wire_n11O0lO_dataout <= wire_n1001ii_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(110); + wire_n11O0Oi_dataout <= wire_n1001il_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(111); + wire_n11O0Ol_dataout <= wire_n1001iO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(112); + wire_n11O0OO_dataout <= wire_n1001li_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(113); + wire_n11O10i_dataout <= wire_n101lOl_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(87); + wire_n11O10l_dataout <= wire_n101lOO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(88); + wire_n11O10O_dataout <= wire_n101O1i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(89); + wire_n11O11i_dataout <= wire_n101lll_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(84); + wire_n11O11il_dataout <= n11li1ii OR ((((((((wire_n11O1i1i_o AND n1Oi1O1l) OR (wire_n11O10Ol_o AND n011li0O)) OR (wire_n11O10ll_o AND n01O01li)) OR (wire_n11O10il_o AND n00illOl)) OR (wire_n11O100l_o AND n0i00i1O)) OR (wire_n11O101l_o AND n0iOO1ii)) OR (wire_n11O11Ol_o AND n0ll0lll)) OR (wire_n11O11ll_o AND n0O0O0OO)); + wire_n11O11l_dataout <= wire_n101llO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(85); + wire_n11O11O_dataout <= wire_n101lOi_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(86); + wire_n11O1i0i_dataout <= n11li11O OR ((((((((nlOOOl1ll AND niOl0i1OO) OR (nlOOOl1lO AND niOl0i1Ol)) OR (nlOOOl1Oi AND niOl0i1Oi)) OR (nlOOOl1Ol AND niOl0i1lO)) OR (nlOOOl1OO AND niOl0i1ll)) OR (nlOOOl01i AND niOl0i1li)) OR (nlOOOl01l AND niOl0i1iO)) OR (nlOOOl01O AND niOl0i1il)); + wire_n11O1i1l_dataout <= wire_n11O1i1O_dataout AND NOT((niOlO1O0i AND n11Oi00l)); + wire_n11O1i1O_dataout <= wire_n11O1i0i_dataout WHEN niOl001OO = '1' ELSE n11li11O; + wire_n11O1ii_dataout <= wire_n101O1l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(90); + wire_n11O1il_dataout <= wire_n101O1O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(91); + wire_n11O1iO_dataout <= wire_n101O0i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(92); + wire_n11O1li_dataout <= wire_n101O0l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(93); + wire_n11O1liO_dataout <= (niOO10lOO AND (wire_nlOii0lli_dataout OR ((n11O0lii OR n11O0l1O) OR nlOlO011l))) AND NOT(wire_niO01lOO_dataout); + wire_n11O1ll_dataout <= wire_n101O0O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(94); + wire_n11O1lli_dataout <= (wire_w_lg_w_lg_w_lg_niOO10lOO8902w23242w23243w(0) AND wire_nlOlO0Oii_w_lg_dataout21224w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n11O1lO_dataout <= wire_n101Oii_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(95); + wire_n11O1Oi_dataout <= wire_n101Oil_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(96); + wire_n11O1Ol_dataout <= wire_n101OiO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(97); + wire_n11O1OO_dataout <= wire_n101Oli_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(98); + wire_n11Oi0i_dataout <= wire_n1001Ol_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(117); + wire_n11Oi0il_dataout <= wire_n11OlOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi0iO_dataout <= wire_n11OOlil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi0l_dataout <= wire_n1001OO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(118); + wire_n11Oi0li_dataout <= wire_n11OlOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi0ll_dataout <= wire_n11OOl0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi0lO_dataout <= wire_n11OOlii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi0O_dataout <= wire_n10001i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(119); + wire_n11Oi0Oi_dataout <= wire_n11OOl1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi0Ol_dataout <= wire_n11OOl1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi0OO_dataout <= wire_n1iiii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oi1i_dataout <= wire_n1001ll_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(114); + wire_n11Oi1l_dataout <= wire_n1001lO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(115); + wire_n11Oi1O_dataout <= wire_n1001Oi_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(116); + wire_n11Oii0i_dataout <= wire_n1iiiili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oii0l_dataout <= wire_n1iiiill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oii0O_dataout <= wire_n1iiiilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oii1i_dataout <= wire_n1iiiiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oii1l_dataout <= wire_n1iiiiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oii1O_dataout <= wire_n1iiiiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oiii_dataout <= wire_n10001l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(120); + wire_n11Oiiii_dataout <= wire_n1iiiiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oiiil_dataout <= wire_n11OOiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiiiO_dataout <= wire_n11OOiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oiil_dataout <= wire_n10001O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(121); + wire_n11Oiili_dataout <= wire_n11OOiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oiill_dataout <= wire_n11OOl1i_dataout OR wire_niO01lOO_dataout; + wire_n11OiilO_dataout <= wire_n11OO1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiiO_dataout <= wire_n10000i_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(122); + wire_n11OiiOi_dataout <= wire_n11OO11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiiOl_dataout <= wire_n1iiilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiiOO_dataout <= wire_n1iiilll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oil0i_dataout <= wire_n11OO1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oil0l_dataout <= wire_n11OlllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oil0O_dataout <= wire_n11OllOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oil1i_dataout <= wire_n11OO1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oil1l_dataout <= wire_n11OO10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oil1O_dataout <= wire_n11OO10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oili_dataout <= wire_n10000l_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(123); + wire_n11Oilii_dataout <= wire_n11OllOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oilil_dataout <= wire_n11OllOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiliO_dataout <= wire_n11OlO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oill_dataout <= wire_n10000O_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(124); + wire_n11Oilli_dataout <= wire_n11OlO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oilll_dataout <= wire_n11OlO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OillO_dataout <= wire_n11OlO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OilO_dataout <= wire_n1000ii_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(125); + wire_n11OilOi_dataout <= wire_n11OOl0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OilOl_dataout <= wire_n11OOl0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OilOO_dataout <= wire_n11OlO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiO0i_dataout <= wire_n11OO1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiO0l_dataout <= wire_n11OO1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiO0O_dataout <= wire_n11OlOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiO1i_dataout <= wire_n11OO11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiO1l_dataout <= wire_n11OO1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiO1O_dataout <= wire_n11OO10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiOi_dataout <= wire_n1000il_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(126); + wire_n11OiOii_dataout <= wire_n11OO11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiOil_dataout <= wire_n11OOiiO_dataout OR wire_niO01lOO_dataout; + wire_n11OiOiO_dataout <= wire_n11OOili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiOl_dataout <= wire_n1000iO_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(127); + wire_n11OiOli_dataout <= wire_n11OOiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiOll_dataout <= wire_n11OOill_dataout OR wire_niO01lOO_dataout; + wire_n11OiOlO_dataout <= wire_n11OlOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiOO_dataout <= wire_nlll0lli_q(132) WHEN niOO00l0i = '1' ELSE nlOi1O0l; + wire_n11OiOOi_dataout <= wire_n11OlO0O_dataout OR wire_niO01lOO_dataout; + wire_n11OiOOl_dataout <= wire_n11OlOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11OiOOO_dataout <= wire_n11OlOil_dataout OR wire_niO01lOO_dataout; + wire_n11Ol00i_dataout <= wire_n11OO0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol00l_dataout <= wire_n11OO0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol00O_dataout <= wire_n11OO0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol01i_dataout <= wire_n11OO0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol01l_dataout <= wire_n11OO0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol01O_dataout <= wire_n11OO0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0i_dataout <= wire_nlll0lli_q(66) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(2); + wire_n11Ol0ii_dataout <= wire_n11OO0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0il_dataout <= wire_n11OOi1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0iO_dataout <= wire_n11OOi1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0l_dataout <= wire_nlll0lli_q(67) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(3); + wire_n11Ol0li_dataout <= wire_n11OOi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0ll_dataout <= wire_n11OOi0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0lO_dataout <= wire_n11OOi0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0O_dataout <= wire_nlll0lli_q(68) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(4); + wire_n11Ol0Oi_dataout <= wire_n11OOi0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol0Ol_dataout <= wire_n11OOiii_dataout OR wire_niO01lOO_dataout; + wire_n11Ol0OO_dataout <= wire_n11OOliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol10i_dataout <= wire_n11OOilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol10l_dataout <= wire_n11OO1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol10O_dataout <= wire_n11OO1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol11i_dataout <= wire_n11OlOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol11l_dataout <= wire_n11OlOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol11O_dataout <= wire_n11OlOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1i_dataout <= wire_n1000li_dataout WHEN niOO00l0i = '1' ELSE wire_nlll0lli_q(132); + wire_n11Ol1ii_dataout <= wire_n11OO1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1il_dataout <= wire_n11OO01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1iO_dataout <= wire_n11OO01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1l_dataout <= wire_nlll0lli_q(64) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(0); + wire_n11Ol1li_dataout <= wire_n11OO01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1ll_dataout <= wire_n11OO00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1lO_dataout <= wire_n11OO00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1O_dataout <= wire_nlll0lli_q(65) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(1); + wire_n11Ol1Oi_dataout <= wire_n11OO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1Ol_dataout <= wire_n11OO0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Ol1OO_dataout <= wire_n11OO0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oli0i_dataout <= n11O0iOO AND NOT(wire_niO01lOO_dataout); + wire_n11Oli0l_dataout <= n11O0l1i AND NOT(wire_niO01lOO_dataout); + wire_n11Oli0O_dataout <= n11O0l1l AND NOT(wire_niO01lOO_dataout); + wire_n11Oli1i_dataout <= wire_n11OOlli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oli1l_dataout <= wire_n11OOlll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n11Oli1O_dataout <= n11O0iOl AND NOT(wire_niO01lOO_dataout); + wire_n11Olii_dataout <= wire_nlll0lli_q(69) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(5); + wire_n11Oliii_dataout <= n11O0l1O AND NOT(wire_niO01lOO_dataout); + wire_n11Oliil_dataout <= n11O0l0i AND NOT(wire_niO01lOO_dataout); + wire_n11OliiO_dataout <= n11O0l0l AND NOT(wire_niO01lOO_dataout); + wire_n11Olil_dataout <= wire_nlll0lli_q(70) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(6); + wire_n11Olili_dataout <= n11O0l0O AND NOT(wire_niO01lOO_dataout); + wire_n11Olill_dataout <= n11O0lii AND NOT(wire_niO01lOO_dataout); + wire_n11OlilO_dataout <= n11O0liO AND NOT(wire_niO01lOO_dataout); + wire_n11OliO_dataout <= wire_nlll0lli_q(71) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(7); + wire_n11OliOi_dataout <= n11O0lli AND NOT(wire_niO01lOO_dataout); + wire_n11OliOl_dataout <= n11O0lll AND NOT(wire_niO01lOO_dataout); + wire_n11OliOO_dataout <= n11O0llO AND NOT(wire_niO01lOO_dataout); + wire_n11Oll0i_dataout <= n11O0O1i AND NOT(wire_niO01lOO_dataout); + wire_n11Oll0l_dataout <= n11O0O1l AND NOT(wire_niO01lOO_dataout); + wire_n11Oll0O_dataout <= n11O0O1O AND NOT(wire_niO01lOO_dataout); + wire_n11Oll1i_dataout <= n11O0lOi AND NOT(wire_niO01lOO_dataout); + wire_n11Oll1l_dataout <= n11O0lOl AND NOT(wire_niO01lOO_dataout); + wire_n11Oll1O_dataout <= n11O0lOO AND NOT(wire_niO01lOO_dataout); + wire_n11Olli_dataout <= wire_nlll0lli_q(72) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(8); + wire_n11Ollii_dataout <= n11O0O0i AND NOT(wire_niO01lOO_dataout); + wire_n11Ollil_dataout <= n11O0O0l AND NOT(wire_niO01lOO_dataout); + wire_n11OlliO_dataout <= n11O0O0O AND NOT(wire_niO01lOO_dataout); + wire_n11Olll_dataout <= wire_nlll0lli_q(73) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(9); + wire_n11Ollli_dataout <= n11O0Oii AND NOT(wire_niO01lOO_dataout); + wire_n11Ollll_dataout <= n11O0Oil OR wire_niO01lOO_dataout; + wire_n11OlllO_dataout <= wire_n11OOllO_dataout WHEN niOl0Oiil = '1' ELSE n11O01Ol; + wire_n11OllO_dataout <= wire_nlll0lli_q(74) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(10); + wire_n11OllOi_dataout <= wire_n11OOlOi_dataout WHEN niOl0Oiil = '1' ELSE n11O01OO; + wire_n11OllOl_dataout <= wire_n11OOlOl_dataout WHEN niOl0Oiil = '1' ELSE n11O001i; + wire_n11OllOO_dataout <= wire_n11OOlOO_dataout WHEN niOl0Oiil = '1' ELSE n11O001l; + wire_n11OlO0i_dataout <= wire_n11OOO0i_dataout WHEN niOl0Oiil = '1' ELSE n11O000O; + wire_n11OlO0l_dataout <= wire_n11OOO0l_o WHEN niOl0Oiil = '1' ELSE n11O00iO; + wire_n11OlO0O_dataout <= wire_n11OOOii_o WHEN niOl0Oiil = '1' ELSE n11O0iii; + wire_n11OlO1i_dataout <= wire_n11OOO1i_dataout WHEN niOl0Oiil = '1' ELSE n11O001O; + wire_n11OlO1l_dataout <= wire_n11OOO1l_dataout WHEN niOl0Oiil = '1' ELSE n11O000i; + wire_n11OlO1O_dataout <= wire_n11OOO1O_dataout WHEN niOl0Oiil = '1' ELSE n11O000l; + wire_n11OlOi_dataout <= wire_nlll0lli_q(75) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(11); + wire_n11OlOii_dataout <= wire_n11OOOil_o WHEN niOl0Oiil = '1' ELSE n11O0iil; + wire_n11OlOil_dataout <= wire_n11OOOli_o WHEN niOl0Oiil = '1' ELSE n11O0iiO; + wire_n11OlOiO_dataout <= wire_n11OOOll_o WHEN niOl0Oiil = '1' ELSE n11O0ili; + wire_n11OlOl_dataout <= wire_nlll0lli_q(76) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(12); + wire_n11OlOli_dataout <= wire_n11OOOOi_o WHEN niOl0Oiil = '1' ELSE n11O0ill; + wire_n11OlOll_dataout <= wire_n11OOOOO_o WHEN niOl0Oiil = '1' ELSE n11O0ilO; + wire_n11OlOlO_dataout <= wire_n101111l_o WHEN niOl0Oiil = '1' ELSE n11O1O0i; + wire_n11OlOO_dataout <= wire_nlll0lli_q(77) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(13); + wire_n11OlOOi_dataout <= wire_n101110l_dataout WHEN niOl0Oiil = '1' ELSE n11O00OO; + wire_n11OlOOl_dataout <= wire_n101110O_o WHEN niOl0Oiil = '1' ELSE n11O0i0O; + wire_n11OlOOO_dataout <= wire_n10111il_dataout WHEN niOl0Oiil = '1' ELSE n11O1lil; + wire_n11OO00i_dataout <= wire_n1011i1O_o WHEN niOl0Oiil = '1' ELSE n11O0l0l; + wire_n11OO00l_dataout <= wire_n1011i0i_o WHEN niOl0Oiil = '1' ELSE n11O0l0O; + wire_n11OO00O_dataout <= wire_n1011i0l_o WHEN niOl0Oiil = '1' ELSE n11O0lii; + wire_n11OO01i_dataout <= wire_n10110OO_o WHEN niOl0Oiil = '1' ELSE n11O0l1l; + wire_n11OO01l_dataout <= wire_n1011i1i_o WHEN niOl0Oiil = '1' ELSE n11O0l1O; + wire_n11OO01O_dataout <= wire_n1011i1l_o WHEN niOl0Oiil = '1' ELSE n11O0l0i; + wire_n11OO0i_dataout <= wire_nlll0lli_q(81) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(17); + wire_n11OO0ii_dataout <= wire_n1011i0O_o WHEN niOl0Oiil = '1' ELSE n11O0lil; + wire_n11OO0il_dataout <= wire_n1011iii_o WHEN niOl0Oiil = '1' ELSE n11O0liO; + wire_n11OO0iO_dataout <= wire_n1011iil_o WHEN niOl0Oiil = '1' ELSE n11O0lli; + wire_n11OO0l_dataout <= wire_nlll0lli_q(82) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(18); + wire_n11OO0li_dataout <= wire_n1011iiO_o WHEN niOl0Oiil = '1' ELSE n11O0lll; + wire_n11OO0ll_dataout <= wire_n1011ili_o WHEN niOl0Oiil = '1' ELSE n11O0llO; + wire_n11OO0lO_dataout <= wire_n1011ill_o WHEN niOl0Oiil = '1' ELSE n11O0lOi; + wire_n11OO0O_dataout <= wire_nlll0lli_q(83) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(19); + wire_n11OO0Oi_dataout <= wire_n1011ilO_o WHEN niOl0Oiil = '1' ELSE n11O0lOl; + wire_n11OO0Ol_dataout <= wire_n1011iOi_o WHEN niOl0Oiil = '1' ELSE n11O0lOO; + wire_n11OO0OO_dataout <= wire_n1011iOl_o WHEN niOl0Oiil = '1' ELSE n11O0O1i; + wire_n11OO10i_dataout <= wire_n10111Ol_o WHEN niOl0Oiil = '1' ELSE n11O00lO; + wire_n11OO10l_dataout <= wire_n10111OO_o WHEN niOl0Oiil = '1' ELSE n11O01ll; + wire_n11OO10O_dataout <= wire_n101101i_o WHEN niOl0Oiil = '1' ELSE n11O01lO; + wire_n11OO11i_dataout <= wire_n10111iO_dataout WHEN niOl0Oiil = '1' ELSE n11O00li; + wire_n11OO11l_dataout <= wire_n10111li_o WHEN niOl0Oiil = '1' ELSE n11O01ii; + wire_n11OO11O_dataout <= wire_n10111lO_o WHEN niOl0Oiil = '1' ELSE n11O0i1i; + wire_n11OO1i_dataout <= wire_nlll0lli_q(78) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(14); + wire_n11OO1ii_dataout <= wire_n101101l_o WHEN niOl0Oiil = '1' ELSE n11O01Oi; + wire_n11OO1il_dataout <= wire_n101100i_dataout WHEN niOl0Oiil = '1' ELSE n11O00Oi; + wire_n11OO1iO_dataout <= wire_n101100l_dataout WHEN niOl0Oiil = '1' ELSE n11O00Ol; + wire_n11OO1l_dataout <= wire_nlll0lli_q(79) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(15); + wire_n11OO1li_dataout <= wire_n101100O_o WHEN niOl0Oiil = '1' ELSE n11O00ll; + wire_n11OO1ll_dataout <= wire_n10110ii_o WHEN niOl0Oiil = '1' ELSE n11O010O; + wire_n11OO1lO_dataout <= wire_n10110iO_o WHEN niOl0Oiil = '1' ELSE n11O01li; + wire_n11OO1O_dataout <= wire_nlll0lli_q(80) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(16); + wire_n11OO1Oi_dataout <= wire_n10110lO_o WHEN niOl0Oiil = '1' ELSE n11O0iOl; + wire_n11OO1Ol_dataout <= wire_n10110Oi_o WHEN niOl0Oiil = '1' ELSE n11O0iOO; + wire_n11OO1OO_dataout <= wire_n10110Ol_o WHEN niOl0Oiil = '1' ELSE n11O0l1i; + wire_n11OOi0i_dataout <= wire_n1011l1O_o WHEN niOl0Oiil = '1' ELSE n11O0O0l; + wire_n11OOi0l_dataout <= wire_n1011l0i_o WHEN niOl0Oiil = '1' ELSE n11O0O0O; + wire_n11OOi0O_dataout <= wire_n1011l0l_o WHEN niOl0Oiil = '1' ELSE n11O0Oii; + wire_n11OOi1i_dataout <= wire_n1011iOO_o WHEN niOl0Oiil = '1' ELSE n11O0O1l; + wire_n11OOi1l_dataout <= wire_n1011l1i_o WHEN niOl0Oiil = '1' ELSE n11O0O1O; + wire_n11OOi1O_dataout <= wire_n1011l1l_o WHEN niOl0Oiil = '1' ELSE n11O0O0i; + wire_n11OOii_dataout <= wire_nlll0lli_q(84) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(20); + wire_n11OOiii_dataout <= wire_n1011l0O_o WHEN niOl0Oiil = '1' ELSE n11O0Oil; + wire_n11OOiil_dataout <= wire_n1011lii_o WHEN niOl0Oiil = '1' ELSE n11O0i0i; + wire_n11OOiiO_dataout <= wire_n1011liO_o WHEN niOl0Oiil = '1' ELSE n11O0i1l; + wire_n11OOil_dataout <= wire_nlll0lli_q(85) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(21); + wire_n11OOili_dataout <= wire_n1011lli_o WHEN niOl0Oiil = '1' ELSE n11O0i1O; + wire_n11OOill_dataout <= wire_n1011llO_o WHEN niOl0Oiil = '1' ELSE n11O0i0l; + wire_n11OOilO_dataout <= wire_n1011lOl_o WHEN niOl0Oiil = '1' ELSE n11O0iOi; + wire_n11OOiO_dataout <= wire_nlll0lli_q(86) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(22); + wire_n11OOiOi_dataout <= wire_n1011O1l_o WHEN niOl0Oiil = '1' ELSE n11O011l; + wire_n11OOiOl_dataout <= wire_n1011O1O_o WHEN niOl0Oiil = '1' ELSE n11O011O; + wire_n11OOiOO_dataout <= wire_n1011O0i_o WHEN niOl0Oiil = '1' ELSE n11O010i; + wire_n11OOl0i_dataout <= wire_n1011Oli_o WHEN niOl0Oiil = '1' ELSE n11O00ii; + wire_n11OOl0l_dataout <= wire_n1011OlO_o WHEN niOl0Oiil = '1' ELSE n11O00il; + wire_n11OOl0O_dataout <= wire_n1011OOl_o WHEN niOl0Oiil = '1' ELSE n11O1O0l; + wire_n11OOl1i_dataout <= wire_n1011O0l_o WHEN niOl0Oiil = '1' ELSE n11O010l; + wire_n11OOl1l_dataout <= wire_n1011Oii_o WHEN niOl0Oiil = '1' ELSE n11O1Oil; + wire_n11OOl1O_dataout <= wire_n1011OiO_o WHEN niOl0Oiil = '1' ELSE n11O1Oii; + wire_n11OOli_dataout <= wire_nlll0lli_q(87) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(23); + wire_n11OOlii_dataout <= wire_n101011i_o WHEN niOl0Oiil = '1' ELSE n11O1O0O; + wire_n11OOlil_dataout <= wire_n101011l_o WHEN niOl0Oiil = '1' ELSE n11O1O1O; + wire_n11OOliO_dataout <= n11O0lll WHEN niOl0Oiil = '1' ELSE n11O0OiO; + wire_n11OOll_dataout <= wire_nlll0lli_q(88) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(24); + wire_n11OOlli_dataout <= n11O0llO WHEN niOl0Oiil = '1' ELSE n11O0Oli; + wire_n11OOlll_dataout <= n11O0O0l WHEN niOl0Oiil = '1' ELSE n11O0Oll; + wire_n11OOllO_dataout <= wire_n10i0OiO_dataout WHEN n11O0lll = '1' ELSE n11O01Ol; + wire_n11OOlO_dataout <= wire_nlll0lli_q(89) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(25); + wire_n11OOlOi_dataout <= wire_n10i0Oli_dataout WHEN n11O0lll = '1' ELSE n11O01OO; + wire_n11OOlOl_dataout <= wire_n10i0Oll_dataout WHEN n11O0lll = '1' ELSE n11O001i; + wire_n11OOlOO_dataout <= wire_n10i0OlO_dataout WHEN n11O0lll = '1' ELSE n11O001l; + wire_n11OOO0i_dataout <= wire_n10ii11i_dataout WHEN n11O0lll = '1' ELSE n11O000O; + wire_n11OOO1i_dataout <= wire_n10i0OOi_dataout WHEN n11O0lll = '1' ELSE n11O001O; + wire_n11OOO1l_dataout <= wire_n10i0OOl_dataout WHEN n11O0lll = '1' ELSE n11O000i; + wire_n11OOO1O_dataout <= wire_n10i0OOO_dataout WHEN n11O0lll = '1' ELSE n11O000l; + wire_n11OOOi_dataout <= wire_nlll0lli_q(90) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(26); + wire_n11OOOl_dataout <= wire_nlll0lli_q(91) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(27); + wire_n11OOOO_dataout <= wire_nlll0lli_q(92) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nlll0lli_q(28); + wire_n1i0000i_dataout <= n11O01ii WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i0i10O_dataout; + wire_n1i0000l_dataout <= wire_n1ii1l1l_dataout WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i00lil_dataout; + wire_n1i0000O_dataout <= wire_n1i00lll_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i0001i_dataout <= n11O010i WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i00l0l_dataout; + wire_n1i0001l_dataout <= n11O010l WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i00l0O_dataout; + wire_n1i0001O_dataout <= wire_n1i00lli_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000i_dataout <= wire_nlll0lli_q(38) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1iiO; + wire_n1i000ii_dataout <= wire_n1i00llO_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000il_dataout <= wire_n1i00lOi_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000iO_dataout <= wire_n1i00lOl_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000l_dataout <= wire_nlll0lli_q(39) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1ili; + wire_n1i000li_dataout <= wire_n1i00lOO_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000ll_dataout <= wire_n1i00O1i_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000lO_dataout <= wire_n1i00O1l_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000O_dataout <= wire_nlll0lli_q(40) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1ill; + wire_n1i000Oi_dataout <= wire_n1i00O1O_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000Ol_dataout <= wire_n1i00O0i_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i000OO_dataout <= wire_n1i00O0l_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i0010i_dataout <= n11O1Oii OR niOl0l10i; + wire_n1i0010l_dataout <= wire_n1i1li0O_dataout OR niOl0l10i; + wire_n1i0011i_dataout <= n11O00ll OR NOT(niOli1iOl); + wire_n1i0011l_dataout <= wire_n1i0010i_dataout WHEN niOli1iOl = '1' ELSE n11O1Oii; + wire_n1i0011O_dataout <= wire_n1i0010l_dataout WHEN niOli1iOl = '1' ELSE n11O1Oil; + wire_n1i001i_dataout <= wire_nlll0lli_q(35) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1i0O; + wire_n1i001iO_dataout <= wire_nlOi0iili_dataout WHEN wire_niO01ill_w_lg_n11O0Oll20924w(0) = '1' ELSE n11O00li; + wire_n1i001l_dataout <= wire_nlll0lli_q(36) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1iii; + wire_n1i001li_dataout <= wire_nlOi0iilO_dataout WHEN wire_niO01ill_w_lg_n11O0Oll20924w(0) = '1' ELSE n11O01ll; + wire_n1i001ll_dataout <= wire_nlOi0iiOi_dataout WHEN wire_niO01ill_w_lg_n11O0Oll20924w(0) = '1' ELSE n11O01lO; + wire_n1i001lO_dataout <= wire_nlOi0iiOl_dataout WHEN wire_niO01ill_w_lg_n11O0Oll20924w(0) = '1' ELSE n11O01Oi; + wire_n1i001O_dataout <= wire_nlll0lli_q(37) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1iil; + wire_n1i001Oi_dataout <= n11O00lO AND NOT(niOl0l1iO); + wire_n1i001Ol_dataout <= n11O011l WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i00l1O_dataout; + wire_n1i001OO_dataout <= n11O011O WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i00l0i_dataout; + wire_n1i00i0i_dataout <= wire_n1i00OiO_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00i0l_dataout <= wire_n1i00Oli_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00i0O_dataout <= wire_n1i00Oll_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00i1i_dataout <= wire_n1i00O0O_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00i1l_dataout <= wire_n1i00Oii_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00i1O_dataout <= wire_n1i00Oil_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00ii_dataout <= wire_nlll0lli_q(41) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1ilO; + wire_n1i00iii_dataout <= wire_n1i00OlO_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00iil_dataout <= wire_n1i00OOi_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00iiO_dataout <= wire_n1i00OOl_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00il_dataout <= wire_nlll0lli_q(42) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1iOi; + wire_n1i00ili_dataout <= wire_n1i00OOO_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00ill_dataout <= wire_n1i0i11i_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00ilO_dataout <= wire_n1i0i11l_dataout OR wire_nlOi0iili_dataout; + wire_n1i00iO_dataout <= wire_nlll0lli_q(43) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1iOl; + wire_n1i00iOi_dataout <= wire_n1i0i11O_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00iOl_dataout <= wire_n1i0i10i_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00iOO_dataout <= wire_n1i0i10l_dataout AND NOT(wire_nlOi0iili_dataout); + wire_n1i00l0i_dataout <= n11O011O WHEN niOl0O1ii = '1' ELSE wire_n1i0i1il_dataout; + wire_n1i00l0l_dataout <= n11O010i WHEN niOl0O1ii = '1' ELSE wire_n1i0i1iO_dataout; + wire_n1i00l0O_dataout <= n11O010l WHEN niOl0O1ii = '1' ELSE wire_n1i0i1li_dataout; + wire_n1i00l1i_dataout <= wire_nlOi0il1l_dataout WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i00liO_dataout; + wire_n1i00l1l_dataout <= wire_n1ii1l1O_dataout WHEN wire_nlOi0iili_dataout = '1' ELSE wire_n1i00lii_dataout; + wire_n1i00l1O_dataout <= n11O011l WHEN niOl0O1ii = '1' ELSE wire_n1i0i1ii_dataout; + wire_n1i00li_dataout <= wire_nlll0lli_q(44) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1iOO; + wire_n1i00lii_dataout <= n11O00lO WHEN niOl0O1ii = '1' ELSE wire_n1i0i1ll_dataout; + wire_n1i00lil_dataout <= n11O0i1i WHEN niOl0O1ii = '1' ELSE wire_n1i0i1lO_dataout; + wire_n1i00liO_dataout <= n11O0i0i WHEN niOl0O1ii = '1' ELSE wire_n1i0i1Oi_dataout; + wire_n1i00ll_dataout <= wire_nlll0lli_q(45) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1l1i; + wire_n1i00lli_dataout <= wire_n1i0i1Ol_dataout AND NOT(niOl0O1ii); + wire_n1i00lll_dataout <= wire_n1i0i1OO_dataout AND NOT(niOl0O1ii); + wire_n1i00llO_dataout <= wire_n1i0i01i_dataout AND NOT(niOl0O1ii); + wire_n1i00lO_dataout <= wire_nlll0lli_q(46) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1l1l; + wire_n1i00lOi_dataout <= wire_n1i0i01l_dataout AND NOT(niOl0O1ii); + wire_n1i00lOl_dataout <= wire_n1i0i01O_dataout AND NOT(niOl0O1ii); + wire_n1i00lOO_dataout <= wire_n1i0i00i_dataout AND NOT(niOl0O1ii); + wire_n1i00O0i_dataout <= wire_n1i0i0il_dataout AND NOT(niOl0O1ii); + wire_n1i00O0l_dataout <= wire_n1i0i0iO_dataout AND NOT(niOl0O1ii); + wire_n1i00O0O_dataout <= wire_n1i0i0li_dataout AND NOT(niOl0O1ii); + wire_n1i00O1i_dataout <= wire_n1i0i00l_dataout AND NOT(niOl0O1ii); + wire_n1i00O1l_dataout <= wire_n1i0i00O_dataout AND NOT(niOl0O1ii); + wire_n1i00O1O_dataout <= wire_n1i0i0ii_dataout AND NOT(niOl0O1ii); + wire_n1i00Oi_dataout <= wire_nlll0lli_q(47) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1l1O; + wire_n1i00Oii_dataout <= wire_n1i0i0ll_dataout AND NOT(niOl0O1ii); + wire_n1i00Oil_dataout <= wire_n1i0i0lO_dataout AND NOT(niOl0O1ii); + wire_n1i00OiO_dataout <= wire_n1i0i0Oi_dataout AND NOT(niOl0O1ii); + wire_n1i00Ol_dataout <= wire_nlll0lli_q(48) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1l0i; + wire_n1i00Oli_dataout <= wire_n1i0i0Ol_dataout AND NOT(niOl0O1ii); + wire_n1i00Oll_dataout <= wire_n1i0i0OO_dataout AND NOT(niOl0O1ii); + wire_n1i00OlO_dataout <= wire_n1i0ii1i_dataout AND NOT(niOl0O1ii); + wire_n1i00OO_dataout <= wire_nlll0lli_q(49) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1l0l; + wire_n1i00OOi_dataout <= wire_n1i0ii1l_dataout AND NOT(niOl0O1ii); + wire_n1i00OOl_dataout <= wire_n1i0ii1O_dataout AND NOT(niOl0O1ii); + wire_n1i00OOO_dataout <= wire_n1i0ii0i_dataout AND NOT(niOl0O1ii); + wire_n1i0100i_dataout <= n11O0iOO AND n11O1Oii; + wire_n1i0100l_dataout <= n11O0l1i AND n11O1Oii; + wire_n1i0100O_dataout <= n11O0l1l AND n11O1Oii; + wire_n1i0101i_dataout <= wire_n1i001iO_dataout WHEN niOl0l10i = '1' ELSE wire_n1i01l1O_dataout; + wire_n1i0101l_dataout <= n11O1Oii OR niOl0l10i; + wire_n1i0101O_dataout <= n11O0iOl AND n11O1Oii; + wire_n1i010i_dataout <= wire_nlll0lli_q(23) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10iO; + wire_n1i010ii_dataout <= n11O0l1O AND n11O1Oii; + wire_n1i010il_dataout <= n11O0l0i AND n11O1Oii; + wire_n1i010iO_dataout <= n11O0l0l AND n11O1Oii; + wire_n1i010l_dataout <= wire_nlll0lli_q(24) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10li; + wire_n1i010li_dataout <= n11O0l0O AND n11O1Oii; + wire_n1i010ll_dataout <= n11O0lii AND n11O1Oii; + wire_n1i010lO_dataout <= n11O0lil AND n11O1Oii; + wire_n1i010O_dataout <= wire_nlll0lli_q(25) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10ll; + wire_n1i010Oi_dataout <= n11O0liO AND n11O1Oii; + wire_n1i010Ol_dataout <= n11O0lli AND n11O1Oii; + wire_n1i010OO_dataout <= n11O0lll AND n11O1Oii; + wire_n1i0110i_dataout <= n11O0O1l WHEN niOl0l10i = '1' ELSE wire_n1i01i0O_dataout; + wire_n1i0110l_dataout <= n11O0O1O WHEN niOl0l10i = '1' ELSE wire_n1i01iii_dataout; + wire_n1i0110O_dataout <= n11O0O0i WHEN niOl0l10i = '1' ELSE wire_n1i01iil_dataout; + wire_n1i0111i_dataout <= n11O0lOl WHEN niOl0l10i = '1' ELSE wire_n1i01i1O_dataout; + wire_n1i0111l_dataout <= n11O0lOO WHEN niOl0l10i = '1' ELSE wire_n1i01i0i_dataout; + wire_n1i0111O_dataout <= n11O0O1i WHEN niOl0l10i = '1' ELSE wire_n1i01i0l_dataout; + wire_n1i011i_dataout <= wire_nlll0lli_q(20) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi100O; + wire_n1i011ii_dataout <= n11O0O0l WHEN niOl0l10i = '1' ELSE wire_n1i01iiO_dataout; + wire_n1i011il_dataout <= n11O0O0O WHEN niOl0l10i = '1' ELSE wire_n1i01ili_dataout; + wire_n1i011iO_dataout <= n11O0Oii WHEN niOl0l10i = '1' ELSE wire_n1i01ill_dataout; + wire_n1i011l_dataout <= wire_nlll0lli_q(21) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10ii; + wire_n1i011li_dataout <= n11O0Oil WHEN niOl0l10i = '1' ELSE wire_n1i01ilO_dataout; + wire_n1i011ll_dataout <= wire_n1i001li_dataout WHEN niOl0l10i = '1' ELSE wire_n1i01iOi_dataout; + wire_n1i011lO_dataout <= wire_n1i001ll_dataout WHEN niOl0l10i = '1' ELSE wire_n1i01iOl_dataout; + wire_n1i011O_dataout <= wire_nlll0lli_q(22) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10il; + wire_n1i011Oi_dataout <= wire_n1i001lO_dataout WHEN niOl0l10i = '1' ELSE wire_n1i01iOO_dataout; + wire_n1i011Ol_dataout <= n11O0i1i WHEN niOl0l10i = '1' ELSE wire_n1i01l1i_dataout; + wire_n1i011OO_dataout <= n11O00ll WHEN niOl0l10i = '1' ELSE wire_n1i01l1l_dataout; + wire_n1i01i0i_dataout <= n11O0lOO AND n11O1Oii; + wire_n1i01i0l_dataout <= n11O0O1i AND n11O1Oii; + wire_n1i01i0O_dataout <= n11O0O1l AND n11O1Oii; + wire_n1i01i1i_dataout <= n11O0llO AND n11O1Oii; + wire_n1i01i1l_dataout <= n11O0lOi AND n11O1Oii; + wire_n1i01i1O_dataout <= n11O0lOl AND n11O1Oii; + wire_n1i01ii_dataout <= wire_nlll0lli_q(26) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10lO; + wire_n1i01iii_dataout <= n11O0O1O AND n11O1Oii; + wire_n1i01iil_dataout <= n11O0O0i AND n11O1Oii; + wire_n1i01iiO_dataout <= n11O0O0l AND n11O1Oii; + wire_n1i01il_dataout <= wire_nlll0lli_q(27) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10Oi; + wire_n1i01ili_dataout <= n11O0O0O OR NOT(n11O1Oii); + wire_n1i01ill_dataout <= n11O0Oii AND n11O1Oii; + wire_n1i01ilO_dataout <= n11O0Oil AND n11O1Oii; + wire_n1i01iO_dataout <= wire_nlll0lli_q(28) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10Ol; + wire_n1i01iOi_dataout <= wire_n1i001li_dataout AND n11O1Oii; + wire_n1i01iOl_dataout <= wire_n1i001ll_dataout AND n11O1Oii; + wire_n1i01iOO_dataout <= wire_n1i001lO_dataout AND n11O1Oii; + wire_n1i01l0l_dataout <= n11O010O OR (niOO10lOO AND (wire_nlOi0iili_dataout AND wire_w_lg_niOl0iOlO20945w(0))); + wire_n1i01l1i_dataout <= n11O0i1i AND n11O1Oii; + wire_n1i01l1l_dataout <= n11O00ll AND n11O1Oii; + wire_n1i01l1O_dataout <= wire_n1i001iO_dataout AND n11O1Oii; + wire_n1i01li_dataout <= wire_nlll0lli_q(29) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi10OO; + wire_n1i01ll_dataout <= wire_nlll0lli_q(30) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1i1i; + wire_n1i01lO_dataout <= wire_nlll0lli_q(31) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1i1l; + wire_n1i01Oi_dataout <= wire_nlll0lli_q(32) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1i1O; + wire_n1i01Ol_dataout <= wire_nlll0lli_q(33) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1i0i; + wire_n1i01OlO_dataout <= n11O0O0O AND NOT(niOli1iOl); + wire_n1i01OO_dataout <= wire_nlll0lli_q(34) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1i0l; + wire_n1i01OOi_dataout <= n11O0Oil OR niOli1iOl; + wire_n1i0i00i_dataout <= wire_n1i0ilii_dataout AND NOT(niOl0l0ii); + wire_n1i0i00l_dataout <= wire_n1i0ilil_dataout AND NOT(niOl0l0ii); + wire_n1i0i00O_dataout <= wire_n1i0iliO_dataout AND NOT(niOl0l0ii); + wire_n1i0i01i_dataout <= wire_n1i0il0i_dataout AND NOT(niOl0l0ii); + wire_n1i0i01l_dataout <= wire_n1i0il0l_dataout AND NOT(niOl0l0ii); + wire_n1i0i01O_dataout <= wire_n1i0il0O_dataout AND NOT(niOl0l0ii); + wire_n1i0i0i_dataout <= wire_nlll0lli_q(53) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1liO; + wire_n1i0i0ii_dataout <= wire_n1i0illi_dataout AND NOT(niOl0l0ii); + wire_n1i0i0il_dataout <= wire_n1i0illl_dataout AND NOT(niOl0l0ii); + wire_n1i0i0iO_dataout <= wire_n1i0illO_dataout AND NOT(niOl0l0ii); + wire_n1i0i0l_dataout <= wire_nlll0lli_q(54) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1lli; + wire_n1i0i0li_dataout <= wire_n1i0ilOi_dataout AND NOT(niOl0l0ii); + wire_n1i0i0ll_dataout <= wire_n1i0ilOl_dataout AND NOT(niOl0l0ii); + wire_n1i0i0lO_dataout <= wire_n1i0ilOO_dataout AND NOT(niOl0l0ii); + wire_n1i0i0O_dataout <= wire_nlll0lli_q(55) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1lll; + wire_n1i0i0Oi_dataout <= wire_n1i0iO1i_dataout AND NOT(niOl0l0ii); + wire_n1i0i0Ol_dataout <= wire_n1i0iO1l_dataout AND NOT(niOl0l0ii); + wire_n1i0i0OO_dataout <= wire_n1i0iO1O_dataout AND NOT(niOl0l0ii); + wire_n1i0i10i_dataout <= wire_n1i0iiil_dataout AND NOT(niOl0O1ii); + wire_n1i0i10l_dataout <= wire_n1i0iiiO_dataout AND NOT(niOl0O1ii); + wire_n1i0i10O_dataout <= wire_n1i0iili_dataout OR niOl0O1ii; + wire_n1i0i11i_dataout <= wire_n1i0ii0l_dataout OR niOl0O1ii; + wire_n1i0i11l_dataout <= wire_n1i0ii0O_dataout AND NOT(niOl0O1ii); + wire_n1i0i11O_dataout <= wire_n1i0iiii_dataout AND NOT(niOl0O1ii); + wire_n1i0i1i_dataout <= wire_nlll0lli_q(50) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1l0O; + wire_n1i0i1ii_dataout <= n11O011l WHEN niOl0l0ii = '1' ELSE wire_n1i0iill_dataout; + wire_n1i0i1il_dataout <= n11O011O WHEN niOl0l0ii = '1' ELSE wire_n1i0iilO_dataout; + wire_n1i0i1iO_dataout <= n11O010i WHEN niOl0l0ii = '1' ELSE wire_n1i0iiOi_dataout; + wire_n1i0i1l_dataout <= wire_nlll0lli_q(51) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1lii; + wire_n1i0i1li_dataout <= n11O010l WHEN niOl0l0ii = '1' ELSE wire_n1i0iiOl_dataout; + wire_n1i0i1ll_dataout <= n11O00lO WHEN niOl0l0ii = '1' ELSE wire_n1i0iiOO_dataout; + wire_n1i0i1lO_dataout <= n11O0i1i WHEN niOl0l0ii = '1' ELSE wire_n1i0il1i_dataout; + wire_n1i0i1O_dataout <= wire_nlll0lli_q(52) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1lil; + wire_n1i0i1Oi_dataout <= n11O0i0i WHEN niOl0l0ii = '1' ELSE wire_n1i0il1l_dataout; + wire_n1i0i1Ol_dataout <= niOl0l00i AND NOT(niOl0l0ii); + wire_n1i0i1OO_dataout <= wire_n1i0il1O_dataout AND NOT(niOl0l0ii); + wire_n1i0ii0i_dataout <= wire_n1i0iOii_dataout AND NOT(niOl0l0ii); + wire_n1i0ii0l_dataout <= wire_n1i0iOil_dataout OR niOl0l0ii; + wire_n1i0ii0O_dataout <= wire_n1i0iOiO_dataout AND NOT(niOl0l0ii); + wire_n1i0ii1i_dataout <= wire_n1i0iO0i_dataout AND NOT(niOl0l0ii); + wire_n1i0ii1l_dataout <= wire_n1i0iO0l_dataout AND NOT(niOl0l0ii); + wire_n1i0ii1O_dataout <= wire_n1i0iO0O_dataout AND NOT(niOl0l0ii); + wire_n1i0iii_dataout <= wire_nlll0lli_q(56) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1llO; + wire_n1i0iiii_dataout <= wire_n1i0iOli_dataout AND NOT(niOl0l0ii); + wire_n1i0iiil_dataout <= wire_n1i0iOll_dataout AND NOT(niOl0l0ii); + wire_n1i0iiiO_dataout <= wire_n1i0iOlO_dataout AND NOT(niOl0l0ii); + wire_n1i0iil_dataout <= wire_nlll0lli_q(57) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1lOi; + wire_n1i0iili_dataout <= n11O01ii OR niOl0l0ii; + wire_n1i0iill_dataout <= n11O011l WHEN niOl0l00i = '1' ELSE wire_n1i0l0ll_dataout; + wire_n1i0iilO_dataout <= n11O011O WHEN niOl0l00i = '1' ELSE wire_n1i0l0lO_dataout; + wire_n1i0iiO_dataout <= wire_nlll0lli_q(58) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1lOl; + wire_n1i0iiOi_dataout <= n11O010i WHEN niOl0l00i = '1' ELSE wire_n1i0l0Oi_dataout; + wire_n1i0iiOl_dataout <= n11O010l WHEN niOl0l00i = '1' ELSE wire_n1i0l0Ol_dataout; + wire_n1i0iiOO_dataout <= wire_n1i0Oill_dataout WHEN niOl0l00i = '1' ELSE wire_n1i0l0iO_dataout; + wire_n1i0il0i_dataout <= wire_n1i0iOOl_dataout AND NOT(niOl0l00i); + wire_n1i0il0l_dataout <= wire_n1i0iOOO_dataout AND NOT(niOl0l00i); + wire_n1i0il0O_dataout <= wire_n1i0l11i_dataout AND NOT(niOl0l00i); + wire_n1i0il1i_dataout <= wire_n1i0OilO_dataout WHEN niOl0l00i = '1' ELSE wire_n1i0l0il_dataout; + wire_n1i0il1l_dataout <= wire_n1i0OiOi_dataout WHEN niOl0l00i = '1' ELSE wire_n1i0l0li_dataout; + wire_n1i0il1O_dataout <= wire_n1i0iOOi_dataout AND NOT(niOl0l00i); + wire_n1i0ili_dataout <= wire_nlll0lli_q(59) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1lOO; + wire_n1i0ilii_dataout <= wire_n1i0l11l_dataout AND NOT(niOl0l00i); + wire_n1i0ilil_dataout <= wire_n1i0l11O_dataout AND NOT(niOl0l00i); + wire_n1i0iliO_dataout <= wire_n1i0l10i_dataout AND NOT(niOl0l00i); + wire_n1i0ill_dataout <= wire_nlll0lli_q(60) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1O1i; + wire_n1i0illi_dataout <= wire_n1i0l10l_dataout AND NOT(niOl0l00i); + wire_n1i0illl_dataout <= wire_n1i0l10O_dataout AND NOT(niOl0l00i); + wire_n1i0illO_dataout <= wire_n1i0l1ii_dataout AND NOT(niOl0l00i); + wire_n1i0ilO_dataout <= wire_nlll0lli_q(61) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1O1l; + wire_n1i0ilOi_dataout <= wire_n1i0l1il_dataout AND NOT(niOl0l00i); + wire_n1i0ilOl_dataout <= wire_n1i0l1iO_dataout AND NOT(niOl0l00i); + wire_n1i0ilOO_dataout <= wire_n1i0l1li_dataout AND NOT(niOl0l00i); + wire_n1i0iO0i_dataout <= wire_n1i0l1Ol_dataout AND NOT(niOl0l00i); + wire_n1i0iO0l_dataout <= wire_n1i0l1OO_dataout AND NOT(niOl0l00i); + wire_n1i0iO0O_dataout <= wire_n1i0l01i_dataout AND NOT(niOl0l00i); + wire_n1i0iO1i_dataout <= wire_n1i0l1ll_dataout AND NOT(niOl0l00i); + wire_n1i0iO1l_dataout <= wire_n1i0l1lO_dataout AND NOT(niOl0l00i); + wire_n1i0iO1O_dataout <= wire_n1i0l1Oi_dataout AND NOT(niOl0l00i); + wire_n1i0iOi_dataout <= wire_nlll0lli_q(62) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1O1O; + wire_n1i0iOii_dataout <= wire_n1i0l01l_dataout AND NOT(niOl0l00i); + wire_n1i0iOil_dataout <= wire_n1i0l01O_dataout AND NOT(niOl0l00i); + wire_n1i0iOiO_dataout <= wire_n1i0l00i_dataout OR niOl0l00i; + wire_n1i0iOl_dataout <= wire_nlll0lli_q(63) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1O0i; + wire_n1i0iOli_dataout <= wire_n1i0l00l_dataout AND NOT(niOl0l00i); + wire_n1i0iOll_dataout <= wire_n1i0l00O_dataout AND NOT(niOl0l00i); + wire_n1i0iOlO_dataout <= wire_n1i0l0ii_dataout AND NOT(niOl0l00i); + wire_n1i0iOO_dataout <= wire_nlll0lli_q(132) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi1O0l; + wire_n1i0iOOi_dataout <= wire_n1i0l0OO_dataout AND NOT(niOl0l1ll); + wire_n1i0iOOl_dataout <= wire_n1i0li1i_dataout AND NOT(niOl0l1ll); + wire_n1i0iOOO_dataout <= wire_n1i0li1l_dataout AND NOT(niOl0l1ll); + wire_n1i0l00i_dataout <= wire_n1i0ll0O_dataout OR niOl0l1ll; + wire_n1i0l00l_dataout <= wire_n1i0llii_dataout AND NOT(niOl0l1ll); + wire_n1i0l00O_dataout <= wire_n1i0llil_dataout AND NOT(niOl0l1ll); + wire_n1i0l01i_dataout <= wire_n1i0ll1O_dataout AND NOT(niOl0l1ll); + wire_n1i0l01l_dataout <= wire_n1i0ll0i_dataout AND NOT(niOl0l1ll); + wire_n1i0l01O_dataout <= wire_n1i0ll0l_dataout AND NOT(niOl0l1ll); + wire_n1i0l0i_dataout <= wire_n1iiiiO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(67); + wire_n1i0l0ii_dataout <= wire_n1i0lliO_dataout AND NOT(niOl0l1ll); + wire_n1i0l0il_dataout <= wire_n1i0llli_dataout WHEN niOl0l1ll = '1' ELSE n11O0i1i; + wire_n1i0l0iO_dataout <= wire_n1i0llll_dataout WHEN niOl0l1ll = '1' ELSE n11O00lO; + wire_n1i0l0l_dataout <= wire_n1iiili_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(68); + wire_n1i0l0li_dataout <= wire_n1i0lllO_dataout WHEN niOl0l1ll = '1' ELSE n11O0i0i; + wire_n1i0l0ll_dataout <= wire_n1i0llOi_dataout WHEN niOl0l1ll = '1' ELSE n11O011l; + wire_n1i0l0lO_dataout <= wire_n1i0llOl_dataout WHEN niOl0l1ll = '1' ELSE n11O011O; + wire_n1i0l0O_dataout <= wire_n1iiill_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(69); + wire_n1i0l0Oi_dataout <= wire_n1i0llOO_dataout WHEN niOl0l1ll = '1' ELSE n11O010i; + wire_n1i0l0Ol_dataout <= wire_n1i0lO1i_dataout WHEN niOl0l1ll = '1' ELSE n11O010l; + wire_n1i0l0OO_dataout <= n11O0iOl AND NOT(niOl0l1li); + wire_n1i0l10i_dataout <= wire_n1i0li0O_dataout AND NOT(niOl0l1ll); + wire_n1i0l10l_dataout <= wire_n1i0liii_dataout AND NOT(niOl0l1ll); + wire_n1i0l10O_dataout <= wire_n1i0liil_dataout AND NOT(niOl0l1ll); + wire_n1i0l11i_dataout <= wire_n1i0li1O_dataout AND NOT(niOl0l1ll); + wire_n1i0l11l_dataout <= wire_n1i0li0i_dataout AND NOT(niOl0l1ll); + wire_n1i0l11O_dataout <= wire_n1i0li0l_dataout AND NOT(niOl0l1ll); + wire_n1i0l1i_dataout <= wire_n1iii0O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(64); + wire_n1i0l1ii_dataout <= wire_n1i0liiO_dataout AND NOT(niOl0l1ll); + wire_n1i0l1il_dataout <= wire_n1i0lili_dataout AND NOT(niOl0l1ll); + wire_n1i0l1iO_dataout <= wire_n1i0lill_dataout AND NOT(niOl0l1ll); + wire_n1i0l1l_dataout <= wire_n1iiiii_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(65); + wire_n1i0l1li_dataout <= wire_n1i0lilO_dataout AND NOT(niOl0l1ll); + wire_n1i0l1ll_dataout <= wire_n1i0liOi_dataout AND NOT(niOl0l1ll); + wire_n1i0l1lO_dataout <= wire_n1i0liOl_dataout AND NOT(niOl0l1ll); + wire_n1i0l1O_dataout <= wire_n1iiiil_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(66); + wire_n1i0l1Oi_dataout <= wire_n1i0liOO_dataout AND NOT(niOl0l1ll); + wire_n1i0l1Ol_dataout <= wire_n1i0ll1i_dataout AND NOT(niOl0l1ll); + wire_n1i0l1OO_dataout <= wire_n1i0ll1l_dataout AND NOT(niOl0l1ll); + wire_n1i0li0i_dataout <= n11O0l1O AND NOT(niOl0l1li); + wire_n1i0li0l_dataout <= n11O0l0i AND NOT(niOl0l1li); + wire_n1i0li0O_dataout <= n11O0l0l AND NOT(niOl0l1li); + wire_n1i0li1i_dataout <= n11O0iOO AND NOT(niOl0l1li); + wire_n1i0li1l_dataout <= n11O0l1i AND NOT(niOl0l1li); + wire_n1i0li1O_dataout <= n11O0l1l AND NOT(niOl0l1li); + wire_n1i0lii_dataout <= wire_n1iiilO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(70); + wire_n1i0liii_dataout <= n11O0l0O AND NOT(niOl0l1li); + wire_n1i0liil_dataout <= n11O0lii AND NOT(niOl0l1li); + wire_n1i0liiO_dataout <= n11O0lil AND NOT(niOl0l1li); + wire_n1i0lil_dataout <= wire_n1iiiOi_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(71); + wire_n1i0lili_dataout <= n11O0liO AND NOT(niOl0l1li); + wire_n1i0lill_dataout <= n11O0lli AND NOT(niOl0l1li); + wire_n1i0lilO_dataout <= n11O0lll AND NOT(niOl0l1li); + wire_n1i0liO_dataout <= wire_n1iiiOl_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(72); + wire_n1i0liOi_dataout <= n11O0llO AND NOT(niOl0l1li); + wire_n1i0liOl_dataout <= n11O0lOi AND NOT(niOl0l1li); + wire_n1i0liOO_dataout <= n11O0lOl AND NOT(niOl0l1li); + wire_n1i0ll0i_dataout <= n11O0O1O AND NOT(niOl0l1li); + wire_n1i0ll0l_dataout <= n11O0O0i AND NOT(niOl0l1li); + wire_n1i0ll0O_dataout <= n11O0O0l AND NOT(niOl0l1li); + wire_n1i0ll1i_dataout <= n11O0lOO AND NOT(niOl0l1li); + wire_n1i0ll1l_dataout <= n11O0O1i AND NOT(niOl0l1li); + wire_n1i0ll1O_dataout <= n11O0O1l AND NOT(niOl0l1li); + wire_n1i0lli_dataout <= wire_n1iiiOO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(73); + wire_n1i0llii_dataout <= n11O0O0O AND NOT(niOl0l1li); + wire_n1i0llil_dataout <= n11O0Oii AND NOT(niOl0l1li); + wire_n1i0lliO_dataout <= n11O0Oil OR niOl0l1li; + wire_n1i0lll_dataout <= wire_n1iil1i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(74); + wire_n1i0llli_dataout <= n11O0i1i WHEN n11O010l = '1' ELSE wire_n1i0lOii_dataout; + wire_n1i0llll_dataout <= n11O00lO WHEN n11O010l = '1' ELSE wire_n1i0lOil_dataout; + wire_n1i0lllO_dataout <= wire_n1i0lO1l_dataout OR n11O010l; + wire_n1i0llO_dataout <= wire_n1iil1l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(75); + wire_n1i0llOi_dataout <= wire_n1i0lO1O_dataout AND NOT(n11O010l); + wire_n1i0llOl_dataout <= wire_n1i0lO0i_dataout AND NOT(n11O010l); + wire_n1i0llOO_dataout <= wire_n1i0lO0l_dataout OR n11O010l; + wire_n1i0lO0i_dataout <= wire_n1i0lOli_dataout OR n11O010i; + wire_n1i0lO0l_dataout <= wire_n1i0lOll_dataout AND NOT(n11O010i); + wire_n1i0lO0O_dataout <= wire_n1i0lOlO_dataout AND NOT(n11O010i); + wire_n1i0lO1i_dataout <= wire_n1i0lO0O_dataout AND NOT(n11O010l); + wire_n1i0lO1l_dataout <= wire_n1i0lOiO_dataout OR n11O010i; + wire_n1i0lO1O_dataout <= n11O011O AND NOT(n11O010i); + wire_n1i0lOi_dataout <= wire_n1iil1O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(76); + wire_n1i0lOii_dataout <= wire_n1i0lOOi_dataout OR n11O010i; + wire_n1i0lOil_dataout <= wire_n1i0lOOl_dataout OR n11O010i; + wire_n1i0lOiO_dataout <= wire_n1i0lOOO_dataout AND NOT(n11O011O); + wire_n1i0lOl_dataout <= wire_n1iil0i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(77); + wire_n1i0lOli_dataout <= wire_n1i0O11i_dataout AND NOT(n11O011O); + wire_n1i0lOll_dataout <= wire_n1i0O11l_dataout AND NOT(n11O011O); + wire_n1i0lOlO_dataout <= wire_n1i0O11O_dataout AND NOT(n11O011O); + wire_n1i0lOO_dataout <= wire_n1iil0l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(78); + wire_n1i0lOOi_dataout <= n11O0i1i OR n11O011O; + wire_n1i0lOOl_dataout <= n11O00lO OR n11O011O; + wire_n1i0lOOO_dataout <= n11O0i0i OR n11O011l; + wire_n1i0O0i_dataout <= wire_n1iiliO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(82); + wire_n1i0O0l_dataout <= wire_n1iilli_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(83); + wire_n1i0O0O_dataout <= wire_n1iilll_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(84); + wire_n1i0O11i_dataout <= n11O011O AND NOT(n11O011l); + wire_n1i0O11l_dataout <= n11O010i OR n11O011l; + wire_n1i0O11O_dataout <= n11O010l AND NOT(n11O011l); + wire_n1i0O1i_dataout <= wire_n1iil0O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(79); + wire_n1i0O1l_dataout <= wire_n1iilii_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(80); + wire_n1i0O1O_dataout <= wire_n1iilil_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(81); + wire_n1i0Oii_dataout <= wire_n1iillO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(85); + wire_n1i0Oil_dataout <= wire_n1iilOi_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(86); + wire_n1i0Oill_dataout <= n11O00lO WHEN wire_w_lg_niOO10l1i20908w(0) = '1' ELSE wire_n1i0OiOl_dataout; + wire_n1i0OilO_dataout <= n11O0i1i WHEN wire_w_lg_niOO10l1i20908w(0) = '1' ELSE wire_n1i0OiOO_dataout; + wire_n1i0OiO_dataout <= wire_n1iilOl_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(87); + wire_n1i0OiOi_dataout <= wire_w_lg_niOl0l01l20907w(0) OR wire_w_lg_niOO10l1i20908w(0); + wire_n1i0OiOl_dataout <= wire_n1i0Ol1O_dataout WHEN wire_w_lg_niOl0l01O20906w(0) = '1' ELSE wire_n1i0Ol1i_dataout; + wire_n1i0OiOO_dataout <= wire_n1i0Ol0i_dataout WHEN wire_w_lg_niOl0l01O20906w(0) = '1' ELSE wire_n1i0Ol1l_dataout; + wire_n1i0Ol0i_dataout <= n11O0i1i OR niOli1iOl; + wire_n1i0Ol1i_dataout <= n11O00lO OR niOli1iOO; + wire_n1i0Ol1l_dataout <= n11O0i1i OR niOli1iOO; + wire_n1i0Ol1O_dataout <= n11O00lO OR niOli1iOl; + wire_n1i0Oli_dataout <= wire_n1iilOO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(88); + wire_n1i0Oll_dataout <= wire_n1iiO1i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(89); + wire_n1i0OlO_dataout <= wire_n1iiO1l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(90); + wire_n1i0OOi_dataout <= wire_n1iiO1O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(91); + wire_n1i0OOl_dataout <= wire_n1iiO0i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(92); + wire_n1i0OOO_dataout <= wire_n1iiO0l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(93); + wire_n1i1000i_dataout <= wire_n1i01l0l_dataout WHEN niOl0l10l = '1' ELSE wire_n1i100ii_dataout; + wire_n1i1000l_dataout <= n11O1Oii WHEN niOl0l11l = '1' ELSE wire_n1i1i1li_dataout; + wire_n1i1000O_dataout <= n11O1Oil WHEN niOl0l11l = '1' ELSE wire_n1i1i1ll_dataout; + wire_n1i1001i_dataout <= wire_n1i0011i_dataout WHEN niOl0l10l = '1' ELSE wire_n1i10lii_dataout; + wire_n1i1001l_dataout <= wire_n1i0011l_dataout WHEN niOl0l10l = '1' ELSE wire_n1i1000l_dataout; + wire_n1i1001O_dataout <= wire_n1i0011O_dataout WHEN niOl0l10l = '1' ELSE wire_n1i1000O_dataout; + wire_n1i100i_dataout <= wire_n1i0OOl_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi000l; + wire_n1i100ii_dataout <= n11O010O WHEN niOl0l11l = '1' ELSE wire_n1i1i1lO_dataout; + wire_n1i100il_dataout <= wire_n1i1lOiO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10liO_dataout; + wire_n1i100iO_dataout <= wire_n1i1lOli_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10lli_dataout; + wire_n1i100l_dataout <= wire_n1i0OOO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi000O; + wire_n1i100li_dataout <= wire_n1i1lOll_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10lll_dataout; + wire_n1i100ll_dataout <= wire_n1i1lOlO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10llO_dataout; + wire_n1i100lO_dataout <= wire_n1i1lOOi_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10lOi_dataout; + wire_n1i100O_dataout <= wire_n1ii11i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00ii; + wire_n1i100Oi_dataout <= wire_n1i1lOOl_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10lOl_dataout; + wire_n1i100Ol_dataout <= wire_n1i1lOOO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10lOO_dataout; + wire_n1i100OO_dataout <= wire_n1i1O11i_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10O1i_dataout; + wire_n1i1010i_dataout <= n11O0O1l WHEN niOl0l10l = '1' ELSE wire_n1i10ill_dataout; + wire_n1i1010l_dataout <= n11O0O1O WHEN niOl0l10l = '1' ELSE wire_n1i10ilO_dataout; + wire_n1i1010O_dataout <= n11O0O0i WHEN niOl0l10l = '1' ELSE wire_n1i10iOi_dataout; + wire_n1i1011i_dataout <= n11O0lOl WHEN niOl0l10l = '1' ELSE wire_n1i10iil_dataout; + wire_n1i1011l_dataout <= n11O0lOO WHEN niOl0l10l = '1' ELSE wire_n1i10iiO_dataout; + wire_n1i1011O_dataout <= n11O0O1i WHEN niOl0l10l = '1' ELSE wire_n1i10ili_dataout; + wire_n1i101i_dataout <= wire_n1i0Oll_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi001l; + wire_n1i101ii_dataout <= n11O0O0l WHEN niOl0l10l = '1' ELSE wire_n1i10iOl_dataout; + wire_n1i101il_dataout <= n11O0O0O WHEN niOl0l10l = '1' ELSE wire_n1i10iOO_dataout; + wire_n1i101iO_dataout <= n11O0Oii WHEN niOl0l10l = '1' ELSE wire_n1i10l1i_dataout; + wire_n1i101l_dataout <= wire_n1i0OlO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi001O; + wire_n1i101li_dataout <= n11O0Oil WHEN niOl0l10l = '1' ELSE wire_n1i10l1l_dataout; + wire_n1i101ll_dataout <= wire_n1i001li_dataout WHEN niOl0l10l = '1' ELSE wire_n1i10l1O_dataout; + wire_n1i101lO_dataout <= wire_n1i001ll_dataout WHEN niOl0l10l = '1' ELSE wire_n1i10l0i_dataout; + wire_n1i101O_dataout <= wire_n1i0OOi_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi000i; + wire_n1i101Oi_dataout <= wire_n1i001lO_dataout WHEN niOl0l10l = '1' ELSE wire_n1i10l0l_dataout; + wire_n1i101Ol_dataout <= n11O0i1i WHEN niOl0l10l = '1' ELSE wire_n1i10l0O_dataout; + wire_n1i101OO_dataout <= wire_n1i001iO_dataout WHEN niOl0l10l = '1' ELSE wire_n1i10lil_dataout; + wire_n1i10i0i_dataout <= wire_n1i1O10l_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10O0l_dataout; + wire_n1i10i0l_dataout <= wire_n1i1O10O_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10O0O_dataout; + wire_n1i10i0O_dataout <= wire_n1i1O1ii_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10Oii_dataout; + wire_n1i10i1i_dataout <= wire_n1i1O11l_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10O1l_dataout; + wire_n1i10i1l_dataout <= wire_n1i1O11O_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10O1O_dataout; + wire_n1i10i1O_dataout <= wire_n1i1O10i_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10O0i_dataout; + wire_n1i10ii_dataout <= wire_n1ii11l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00il; + wire_n1i10iii_dataout <= wire_n1i1O1il_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10Oil_dataout; + wire_n1i10iil_dataout <= wire_n1i1O1iO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10OiO_dataout; + wire_n1i10iiO_dataout <= wire_n1i1O1li_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10Oli_dataout; + wire_n1i10il_dataout <= wire_n1ii11O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00iO; + wire_n1i10ili_dataout <= wire_n1i1O1ll_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10Oll_dataout; + wire_n1i10ill_dataout <= wire_n1i1O1lO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10OlO_dataout; + wire_n1i10ilO_dataout <= wire_n1i1O1Oi_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10OOi_dataout; + wire_n1i10iO_dataout <= wire_n1ii10i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00li; + wire_n1i10iOi_dataout <= wire_n1i1O1Ol_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10OOl_dataout; + wire_n1i10iOl_dataout <= wire_n1i1O1OO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i10OOO_dataout; + wire_n1i10iOO_dataout <= wire_n1i01OlO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i11i_dataout; + wire_n1i10l0i_dataout <= wire_n1i1O00l_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i10l_dataout; + wire_n1i10l0l_dataout <= wire_n1i1O00O_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i10O_dataout; + wire_n1i10l0O_dataout <= wire_n1i1O0ii_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i1ii_dataout; + wire_n1i10l1i_dataout <= wire_n1i1O01l_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i11l_dataout; + wire_n1i10l1l_dataout <= wire_n1i01OOi_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i11O_dataout; + wire_n1i10l1O_dataout <= wire_n1i1O00i_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i10i_dataout; + wire_n1i10li_dataout <= wire_n1ii10l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00ll; + wire_n1i10lii_dataout <= wire_w_lg_niOli1iOl20954w(0) WHEN niOl0l11l = '1' ELSE wire_n1i1i1il_dataout; + wire_n1i10lil_dataout <= wire_n1i1O0iO_dataout WHEN niOl0l11l = '1' ELSE wire_n1i1i1iO_dataout; + wire_n1i10liO_dataout <= wire_n1i1O0Oi_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i1OO_dataout; + wire_n1i10ll_dataout <= wire_n1ii10O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00lO; + wire_n1i10lli_dataout <= wire_n1i1O0Ol_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i01i_dataout; + wire_n1i10lll_dataout <= wire_n1i1O0OO_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i01l_dataout; + wire_n1i10llO_dataout <= wire_n1i1Oi1i_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i01O_dataout; + wire_n1i10lO_dataout <= wire_n1ii1ii_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00Oi; + wire_n1i10lOi_dataout <= wire_n1i1Oi1l_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i00i_dataout; + wire_n1i10lOl_dataout <= wire_n1i1Oi1O_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i00l_dataout; + wire_n1i10lOO_dataout <= wire_n1i1Oi0i_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i00O_dataout; + wire_n1i10O0i_dataout <= wire_n1i1Oiil_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0li_dataout; + wire_n1i10O0l_dataout <= wire_n1i1OiiO_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0ll_dataout; + wire_n1i10O0O_dataout <= wire_n1i1Oili_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0lO_dataout; + wire_n1i10O1i_dataout <= wire_n1i1Oi0l_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0ii_dataout; + wire_n1i10O1l_dataout <= wire_n1i1Oi0O_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0il_dataout; + wire_n1i10O1O_dataout <= wire_n1i1Oiii_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0iO_dataout; + wire_n1i10Oi_dataout <= wire_n1ii1il_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00Ol; + wire_n1i10Oii_dataout <= wire_n1i1Oill_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0Oi_dataout; + wire_n1i10Oil_dataout <= wire_n1i1OilO_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0Ol_dataout; + wire_n1i10OiO_dataout <= wire_n1i1OiOi_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i0OO_dataout; + wire_n1i10Ol_dataout <= wire_n1ii1iO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi00OO; + wire_n1i10Oli_dataout <= wire_n1i1OiOl_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1ii1i_dataout; + wire_n1i10Oll_dataout <= wire_n1i1OiOO_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1ii1l_dataout; + wire_n1i10OlO_dataout <= wire_n1i1Ol1i_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1ii1O_dataout; + wire_n1i10OO_dataout <= wire_n1ii1li_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0i1i; + wire_n1i10OOi_dataout <= wire_n1i1Ol1l_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1ii0i_dataout; + wire_n1i10OOl_dataout <= wire_n1i1Ol1O_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1ii0l_dataout; + wire_n1i10OOO_dataout <= wire_n1i1Ol0i_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1ii0O_dataout; + wire_n1i1100i_dataout <= n11O0i1i OR NOT(((NOT (n11li1iO XOR nlOliO0iO)) AND (NOT (n11li1li XOR nlOliO0li)))); + wire_n1i1100l_dataout <= wire_nlOi0iill_dataout WHEN wire_n1l10lli_dataout = '1' ELSE n1iiii1i; + wire_n1i1101i_dataout <= n11O0Oii AND NOT(niOl0iO1O); + wire_n1i1101l_dataout <= n11O0Oil OR niOl0iO1O; + wire_n1i110i_dataout <= wire_n1i0lOl_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi010l; + wire_n1i110l_dataout <= wire_n1i0lOO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi010O; + wire_n1i110O_dataout <= wire_n1i0O1i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01ii; + wire_n1i1110i_dataout <= n11O0lli AND NOT(niOl0iO1O); + wire_n1i1110l_dataout <= n11O0lll AND NOT(niOl0iO1O); + wire_n1i1110O_dataout <= n11O0llO AND NOT(niOl0iO1O); + wire_n1i1111i_dataout <= n11O0lii AND NOT(niOl0iO1O); + wire_n1i1111l_dataout <= n11O0lil AND NOT(niOl0iO1O); + wire_n1i1111O_dataout <= n11O0liO AND NOT(niOl0iO1O); + wire_n1i111i_dataout <= wire_n1i0lll_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi011l; + wire_n1i111ii_dataout <= n11O0lOi AND NOT(niOl0iO1O); + wire_n1i111il_dataout <= n11O0lOl AND NOT(niOl0iO1O); + wire_n1i111iO_dataout <= n11O0lOO AND NOT(niOl0iO1O); + wire_n1i111l_dataout <= wire_n1i0llO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi011O; + wire_n1i111li_dataout <= n11O0O1i AND NOT(niOl0iO1O); + wire_n1i111ll_dataout <= n11O0O1l AND NOT(niOl0iO1O); + wire_n1i111lO_dataout <= n11O0O1O AND NOT(niOl0iO1O); + wire_n1i111O_dataout <= wire_n1i0lOi_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi010i; + wire_n1i111Oi_dataout <= n11O0O0i AND NOT(niOl0iO1O); + wire_n1i111Ol_dataout <= n11O0O0l AND NOT(niOl0iO1O); + wire_n1i111OO_dataout <= n11O0O0O AND NOT(niOl0iO1O); + wire_n1i11i0i_dataout <= k_conf(360) WHEN n1lillil = '1' ELSE n11O01li; + wire_n1i11i0l_dataout <= wire_n1i0l0OO_dataout AND NOT(niOl0iOli); + wire_n1i11i0O_dataout <= wire_n1i0li1i_dataout AND NOT(niOl0iOli); + wire_n1i11i1O_dataout <= n11O0i0O AND NOT(n1lillil); + wire_n1i11ii_dataout <= wire_n1i0O1l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01il; + wire_n1i11iii_dataout <= wire_n1i0li1l_dataout AND NOT(niOl0iOli); + wire_n1i11iil_dataout <= wire_n1i0li1O_dataout AND NOT(niOl0iOli); + wire_n1i11iiO_dataout <= wire_n1i0li0i_dataout AND NOT(niOl0iOli); + wire_n1i11il_dataout <= wire_n1i0O1O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01iO; + wire_n1i11ili_dataout <= wire_n1i0li0l_dataout AND NOT(niOl0iOli); + wire_n1i11ill_dataout <= wire_n1i0li0O_dataout AND NOT(niOl0iOli); + wire_n1i11ilO_dataout <= wire_n1i0liii_dataout AND NOT(niOl0iOli); + wire_n1i11iO_dataout <= wire_n1i0O0i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01li; + wire_n1i11iOi_dataout <= wire_n1i0liil_dataout AND NOT(niOl0iOli); + wire_n1i11iOl_dataout <= wire_n1i0liiO_dataout AND NOT(niOl0iOli); + wire_n1i11iOO_dataout <= wire_n1i0lili_dataout AND NOT(niOl0iOli); + wire_n1i11l0i_dataout <= wire_n1i0liOl_dataout AND NOT(niOl0iOli); + wire_n1i11l0l_dataout <= wire_n1i0liOO_dataout AND NOT(niOl0iOli); + wire_n1i11l0O_dataout <= wire_n1i0ll1i_dataout AND NOT(niOl0iOli); + wire_n1i11l1i_dataout <= wire_n1i0lill_dataout AND NOT(niOl0iOli); + wire_n1i11l1l_dataout <= wire_n1i0lilO_dataout AND NOT(niOl0iOli); + wire_n1i11l1O_dataout <= wire_n1i0liOi_dataout AND NOT(niOl0iOli); + wire_n1i11li_dataout <= wire_n1i0O0l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01ll; + wire_n1i11lii_dataout <= wire_n1i0ll1l_dataout AND NOT(niOl0iOli); + wire_n1i11lil_dataout <= wire_n1i0ll1O_dataout AND NOT(niOl0iOli); + wire_n1i11liO_dataout <= wire_n1i0ll0i_dataout OR niOl0iOli; + wire_n1i11ll_dataout <= wire_n1i0O0O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01lO; + wire_n1i11lli_dataout <= wire_n1i0ll0l_dataout AND NOT(niOl0iOli); + wire_n1i11lll_dataout <= wire_n1i0ll0O_dataout AND NOT(niOl0iOli); + wire_n1i11llO_dataout <= wire_n1i0llii_dataout AND NOT(niOl0iOli); + wire_n1i11lO_dataout <= wire_n1i0Oii_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01Oi; + wire_n1i11lOi_dataout <= wire_n1i0llil_dataout AND NOT(niOl0iOli); + wire_n1i11lOl_dataout <= wire_n1i0lliO_dataout AND NOT(niOl0iOli); + wire_n1i11O0i_dataout <= n11O0l1l WHEN niOl0l10l = '1' ELSE wire_n1i100ll_dataout; + wire_n1i11O0l_dataout <= n11O0l1O WHEN niOl0l10l = '1' ELSE wire_n1i100lO_dataout; + wire_n1i11O0O_dataout <= n11O0l0i WHEN niOl0l10l = '1' ELSE wire_n1i100Oi_dataout; + wire_n1i11O1i_dataout <= n11O0iOl WHEN niOl0l10l = '1' ELSE wire_n1i100il_dataout; + wire_n1i11O1l_dataout <= n11O0iOO WHEN niOl0l10l = '1' ELSE wire_n1i100iO_dataout; + wire_n1i11O1O_dataout <= n11O0l1i WHEN niOl0l10l = '1' ELSE wire_n1i100li_dataout; + wire_n1i11Oi_dataout <= wire_n1i0Oil_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01Ol; + wire_n1i11Oii_dataout <= n11O0l0l WHEN niOl0l10l = '1' ELSE wire_n1i100Ol_dataout; + wire_n1i11Oil_dataout <= n11O0l0O WHEN niOl0l10l = '1' ELSE wire_n1i100OO_dataout; + wire_n1i11OiO_dataout <= n11O0lii WHEN niOl0l10l = '1' ELSE wire_n1i10i1i_dataout; + wire_n1i11Ol_dataout <= wire_n1i0OiO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi01OO; + wire_n1i11Oli_dataout <= n11O0lil WHEN niOl0l10l = '1' ELSE wire_n1i10i1l_dataout; + wire_n1i11Oll_dataout <= n11O0liO WHEN niOl0l10l = '1' ELSE wire_n1i10i1O_dataout; + wire_n1i11OlO_dataout <= n11O0lli WHEN niOl0l10l = '1' ELSE wire_n1i10i0i_dataout; + wire_n1i11OO_dataout <= wire_n1i0Oli_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi001i; + wire_n1i11OOi_dataout <= n11O0lll WHEN niOl0l10l = '1' ELSE wire_n1i10i0l_dataout; + wire_n1i11OOl_dataout <= n11O0llO WHEN niOl0l10l = '1' ELSE wire_n1i10i0O_dataout; + wire_n1i11OOO_dataout <= n11O0lOi WHEN niOl0l10l = '1' ELSE wire_n1i10iii_dataout; + wire_n1i1i00i_dataout <= wire_n1i1lOOi_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1ilii_dataout; + wire_n1i1i00l_dataout <= wire_n1i1lOOl_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1ilil_dataout; + wire_n1i1i00O_dataout <= wire_n1i1lOOO_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iliO_dataout; + wire_n1i1i01i_dataout <= wire_n1i1lOli_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1il0i_dataout; + wire_n1i1i01l_dataout <= wire_n1i1lOll_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1il0l_dataout; + wire_n1i1i01O_dataout <= wire_n1i1lOlO_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1il0O_dataout; + wire_n1i1i0i_dataout <= wire_n1ii1Ol_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0i0l; + wire_n1i1i0ii_dataout <= wire_n1i1O11i_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1illi_dataout; + wire_n1i1i0il_dataout <= wire_n1i1O11l_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1illl_dataout; + wire_n1i1i0iO_dataout <= wire_n1i1O11O_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1illO_dataout; + wire_n1i1i0l_dataout <= wire_n1ii1OO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0i0O; + wire_n1i1i0li_dataout <= wire_n1i1O10i_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1ilOi_dataout; + wire_n1i1i0ll_dataout <= wire_n1i1O10l_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1ilOl_dataout; + wire_n1i1i0lO_dataout <= wire_n1i1O10O_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1ilOO_dataout; + wire_n1i1i0O_dataout <= wire_n1ii01i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0iii; + wire_n1i1i0Oi_dataout <= wire_n1i1O1ii_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iO1i_dataout; + wire_n1i1i0Ol_dataout <= wire_n1i1O1il_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iO1l_dataout; + wire_n1i1i0OO_dataout <= wire_n1i1O1iO_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iO1O_dataout; + wire_n1i1i10i_dataout <= wire_n1i1Olil_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iili_dataout; + wire_n1i1i10l_dataout <= wire_n1i1OliO_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iill_dataout; + wire_n1i1i10O_dataout <= wire_n1i1Olli_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iilO_dataout; + wire_n1i1i11i_dataout <= wire_n1i1Ol0l_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iiii_dataout; + wire_n1i1i11l_dataout <= wire_n1i1Ol0O_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iiil_dataout; + wire_n1i1i11O_dataout <= wire_n1i1Olii_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iiiO_dataout; + wire_n1i1i1i_dataout <= wire_n1ii1ll_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0i1l; + wire_n1i1i1ii_dataout <= wire_n1i1Olll_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iiOi_dataout; + wire_n1i1i1il_dataout <= wire_n1i1OllO_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iiOl_dataout; + wire_n1i1i1iO_dataout <= wire_n1i1OlOi_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1iiOO_dataout; + wire_n1i1i1l_dataout <= wire_n1ii1lO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0i1O; + wire_n1i1i1li_dataout <= wire_n1i1OlOl_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i1Oi_dataout; + wire_n1i1i1ll_dataout <= wire_n1i1OlOO_dataout WHEN niOl0iOOi = '1' ELSE wire_n1i1i1Ol_dataout; + wire_n1i1i1lO_dataout <= wire_n1i01l0l_dataout WHEN niOl0iOOi = '1' ELSE n11O010O; + wire_n1i1i1O_dataout <= wire_n1ii1Oi_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0i0i; + wire_n1i1i1Oi_dataout <= n11O1Oii WHEN niOl0iOll = '1' ELSE wire_n1i1il1i_dataout; + wire_n1i1i1Ol_dataout <= n11O1Oil WHEN niOl0iOll = '1' ELSE wire_n1i1il1l_dataout; + wire_n1i1i1OO_dataout <= wire_n1i1lOiO_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1il1O_dataout; + wire_n1i1ii0i_dataout <= wire_n1i1O1Oi_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOii_dataout; + wire_n1i1ii0l_dataout <= wire_n1i1O1Ol_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOil_dataout; + wire_n1i1ii0O_dataout <= wire_n1i1O1OO_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOiO_dataout; + wire_n1i1ii1i_dataout <= wire_n1i1O1li_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iO0i_dataout; + wire_n1i1ii1l_dataout <= wire_n1i1O1ll_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iO0l_dataout; + wire_n1i1ii1O_dataout <= wire_n1i1O1lO_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iO0O_dataout; + wire_n1i1iii_dataout <= wire_n1ii01l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0iil; + wire_n1i1iiii_dataout <= wire_n1i1O01i_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOli_dataout; + wire_n1i1iiil_dataout <= wire_n1i1O01l_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOll_dataout; + wire_n1i1iiiO_dataout <= wire_n1i1O01O_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOlO_dataout; + wire_n1i1iil_dataout <= wire_n1ii01O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0iiO; + wire_n1i1iili_dataout <= wire_n1i1O00i_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOOi_dataout; + wire_n1i1iill_dataout <= wire_n1i1O00l_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOOl_dataout; + wire_n1i1iilO_dataout <= wire_n1i1O00O_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1iOOO_dataout; + wire_n1i1iiO_dataout <= wire_n1ii00i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0ili; + wire_n1i1iiOi_dataout <= wire_n1i1O0ii_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1l11i_dataout; + wire_n1i1iiOl_dataout <= wire_w_lg_niOli1iOl20954w(0) WHEN niOl0iOll = '1' ELSE wire_n1i1l11l_dataout; + wire_n1i1iiOO_dataout <= wire_n1i1O0iO_dataout WHEN niOl0iOll = '1' ELSE wire_n1i1l11O_dataout; + wire_n1i1il0i_dataout <= wire_n1i1lOli_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l10l_dataout; + wire_n1i1il0l_dataout <= wire_n1i1lOll_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l10O_dataout; + wire_n1i1il0O_dataout <= wire_n1i1lOlO_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1ii_dataout; + wire_n1i1il1i_dataout <= n11O1Oii WHEN n11O00ll = '1' ELSE wire_n1i1li0l_dataout; + wire_n1i1il1l_dataout <= n11O1Oil WHEN n11O00ll = '1' ELSE wire_n1i1li0O_dataout; + wire_n1i1il1O_dataout <= wire_n1i1lOiO_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l10i_dataout; + wire_n1i1ili_dataout <= wire_n1ii00l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0ill; + wire_n1i1ilii_dataout <= wire_n1i1lOOi_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1il_dataout; + wire_n1i1ilil_dataout <= wire_n1i1lOOl_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1iO_dataout; + wire_n1i1iliO_dataout <= wire_n1i1lOOO_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1li_dataout; + wire_n1i1ill_dataout <= wire_n1ii00O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0ilO; + wire_n1i1illi_dataout <= wire_n1i1O11i_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1ll_dataout; + wire_n1i1illl_dataout <= wire_n1i1O11l_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1lO_dataout; + wire_n1i1illO_dataout <= wire_n1i1O11O_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1Oi_dataout; + wire_n1i1ilO_dataout <= wire_n1ii0ii_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0iOi; + wire_n1i1ilOi_dataout <= wire_n1i1O10i_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1Ol_dataout; + wire_n1i1ilOl_dataout <= wire_n1i1O10l_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l1OO_dataout; + wire_n1i1ilOO_dataout <= wire_n1i1O10O_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l01i_dataout; + wire_n1i1iO0i_dataout <= wire_n1i1O1li_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l00l_dataout; + wire_n1i1iO0l_dataout <= wire_n1i1O1ll_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l00O_dataout; + wire_n1i1iO0O_dataout <= wire_n1i1O1lO_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0ii_dataout; + wire_n1i1iO1i_dataout <= wire_n1i1O1ii_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l01l_dataout; + wire_n1i1iO1l_dataout <= wire_n1i1O1il_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l01O_dataout; + wire_n1i1iO1O_dataout <= wire_n1i1O1iO_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l00i_dataout; + wire_n1i1iOi_dataout <= wire_n1ii0il_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0iOl; + wire_n1i1iOii_dataout <= wire_n1i1O1Oi_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0il_dataout; + wire_n1i1iOil_dataout <= wire_n1i1O1Ol_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0iO_dataout; + wire_n1i1iOiO_dataout <= wire_n1i1O1OO_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0li_dataout; + wire_n1i1iOl_dataout <= wire_n1ii0iO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0iOO; + wire_n1i1iOli_dataout <= wire_n1i1O01i_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0ll_dataout; + wire_n1i1iOll_dataout <= wire_n1i1O01l_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0lO_dataout; + wire_n1i1iOlO_dataout <= wire_n1i1O01O_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0Oi_dataout; + wire_n1i1iOO_dataout <= wire_n1ii0li_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0l1i; + wire_n1i1iOOi_dataout <= wire_n1i1O00i_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0Ol_dataout; + wire_n1i1iOOl_dataout <= wire_n1i1O00l_dataout WHEN n11O00ll = '1' ELSE wire_n1i1l0OO_dataout; + wire_n1i1iOOO_dataout <= wire_n1i1O00O_dataout WHEN n11O00ll = '1' ELSE wire_n1i1li1i_dataout; + wire_n1i1l00i_dataout <= wire_n1i1llii_dataout WHEN n11O1Oii = '1' ELSE n11O0lOl; + wire_n1i1l00l_dataout <= wire_n1i1llil_dataout WHEN n11O1Oii = '1' ELSE n11O0lOO; + wire_n1i1l00O_dataout <= wire_n1i1lliO_dataout WHEN n11O1Oii = '1' ELSE n11O0O1i; + wire_n1i1l01i_dataout <= wire_n1i1ll0i_dataout WHEN n11O1Oii = '1' ELSE n11O0lll; + wire_n1i1l01l_dataout <= wire_n1i1ll0l_dataout WHEN n11O1Oii = '1' ELSE n11O0llO; + wire_n1i1l01O_dataout <= wire_n1i1ll0O_dataout WHEN n11O1Oii = '1' ELSE n11O0lOi; + wire_n1i1l0i_dataout <= wire_n1ii0Ol_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0l0l; + wire_n1i1l0ii_dataout <= wire_n1i1llli_dataout WHEN n11O1Oii = '1' ELSE n11O0O1l; + wire_n1i1l0il_dataout <= wire_n1i1llll_dataout WHEN n11O1Oii = '1' ELSE n11O0O1O; + wire_n1i1l0iO_dataout <= wire_n1i1lllO_dataout WHEN n11O1Oii = '1' ELSE n11O0O0i; + wire_n1i1l0l_dataout <= wire_n1ii0OO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0l0O; + wire_n1i1l0li_dataout <= wire_n1i1llOi_dataout WHEN n11O1Oii = '1' ELSE n11O0O0l; + wire_n1i1l0ll_dataout <= wire_n1i1llOl_dataout WHEN n11O1Oii = '1' ELSE n11O0O0O; + wire_n1i1l0lO_dataout <= wire_n1i1llOO_dataout WHEN n11O1Oii = '1' ELSE n11O0Oii; + wire_n1i1l0O_dataout <= wire_n1iii1i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0lii; + wire_n1i1l0Oi_dataout <= wire_n1i1lO1i_dataout WHEN n11O1Oii = '1' ELSE n11O0Oil; + wire_n1i1l0Ol_dataout <= wire_n1i1lO1l_dataout WHEN n11O1Oii = '1' ELSE wire_n1i001li_dataout; + wire_n1i1l0OO_dataout <= wire_n1i1lO1O_dataout WHEN n11O1Oii = '1' ELSE wire_n1i001ll_dataout; + wire_n1i1l10i_dataout <= wire_n1i1liii_dataout WHEN n11O1Oii = '1' ELSE n11O0iOl; + wire_n1i1l10l_dataout <= wire_n1i1liil_dataout WHEN n11O1Oii = '1' ELSE n11O0iOO; + wire_n1i1l10O_dataout <= wire_n1i1liiO_dataout WHEN n11O1Oii = '1' ELSE n11O0l1i; + wire_n1i1l11i_dataout <= wire_n1i1O0ii_dataout WHEN n11O00ll = '1' ELSE wire_n1i1li1l_dataout; + wire_n1i1l11l_dataout <= wire_n1i1O0il_dataout WHEN n11O00ll = '1' ELSE wire_n1i1li1O_dataout; + wire_n1i1l11O_dataout <= wire_n1i1O0iO_dataout WHEN n11O00ll = '1' ELSE wire_n1i1li0i_dataout; + wire_n1i1l1i_dataout <= wire_n1ii0ll_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0l1l; + wire_n1i1l1ii_dataout <= wire_n1i1lili_dataout WHEN n11O1Oii = '1' ELSE n11O0l1l; + wire_n1i1l1il_dataout <= wire_n1i1lill_dataout WHEN n11O1Oii = '1' ELSE n11O0l1O; + wire_n1i1l1iO_dataout <= wire_n1i1lilO_dataout WHEN n11O1Oii = '1' ELSE n11O0l0i; + wire_n1i1l1l_dataout <= wire_n1ii0lO_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0l1O; + wire_n1i1l1li_dataout <= wire_n1i1liOi_dataout WHEN n11O1Oii = '1' ELSE n11O0l0l; + wire_n1i1l1ll_dataout <= wire_n1i1liOl_dataout WHEN n11O1Oii = '1' ELSE n11O0l0O; + wire_n1i1l1lO_dataout <= wire_n1i1liOO_dataout WHEN n11O1Oii = '1' ELSE n11O0lii; + wire_n1i1l1O_dataout <= wire_n1ii0Oi_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0l0i; + wire_n1i1l1Oi_dataout <= wire_n1i1ll1i_dataout WHEN n11O1Oii = '1' ELSE n11O0lil; + wire_n1i1l1Ol_dataout <= wire_n1i1ll1l_dataout WHEN n11O1Oii = '1' ELSE n11O0liO; + wire_n1i1l1OO_dataout <= wire_n1i1ll1O_dataout WHEN n11O1Oii = '1' ELSE n11O0lli; + wire_n1i1li0i_dataout <= wire_n1i1lOii_dataout WHEN n11O1Oii = '1' ELSE wire_n1i001iO_dataout; + wire_n1i1li0l_dataout <= wire_n1i1lOil_dataout AND n11O1Oii; + wire_n1i1li0O_dataout <= n11O1Oil AND NOT(n11O1Oii); + wire_n1i1li1i_dataout <= wire_n1i1lO0i_dataout WHEN n11O1Oii = '1' ELSE wire_n1i001lO_dataout; + wire_n1i1li1l_dataout <= wire_n1i1lO0l_dataout WHEN n11O1Oii = '1' ELSE n11O0i1i; + wire_n1i1li1O_dataout <= wire_n1i1lO0O_dataout WHEN n11O1Oii = '1' ELSE n11O00ll; + wire_n1i1lii_dataout <= wire_n1iii1l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0lil; + wire_n1i1liii_dataout <= n11O0iOl AND NOT(n1iO0l0O); + wire_n1i1liil_dataout <= n11O0iOO AND NOT(n1iO0l0O); + wire_n1i1liiO_dataout <= n11O0l1i AND NOT(n1iO0l0O); + wire_n1i1lil_dataout <= wire_n1iii1O_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0liO; + wire_n1i1lili_dataout <= n11O0l1l AND NOT(n1iO0l0O); + wire_n1i1lill_dataout <= n11O0l1O AND NOT(n1iO0l0O); + wire_n1i1lilO_dataout <= n11O0l0i AND NOT(n1iO0l0O); + wire_n1i1liO_dataout <= wire_n1iii0i_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi0lli; + wire_n1i1liOi_dataout <= n11O0l0l AND NOT(n1iO0l0O); + wire_n1i1liOl_dataout <= n11O0l0O AND NOT(n1iO0l0O); + wire_n1i1liOO_dataout <= n11O0lii AND NOT(n1iO0l0O); + wire_n1i1ll0i_dataout <= n11O0lll AND NOT(n1iO0l0O); + wire_n1i1ll0l_dataout <= n11O0llO AND NOT(n1iO0l0O); + wire_n1i1ll0O_dataout <= n11O0lOi AND NOT(n1iO0l0O); + wire_n1i1ll1i_dataout <= n11O0lil AND NOT(n1iO0l0O); + wire_n1i1ll1l_dataout <= n11O0liO AND NOT(n1iO0l0O); + wire_n1i1ll1O_dataout <= n11O0lli AND NOT(n1iO0l0O); + wire_n1i1lli_dataout <= wire_n1iii0l_dataout WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE wire_n1l1OOl_dataout; + wire_n1i1llii_dataout <= n11O0lOl AND NOT(n1iO0l0O); + wire_n1i1llil_dataout <= n11O0lOO AND NOT(n1iO0l0O); + wire_n1i1lliO_dataout <= n11O0O1i AND NOT(n1iO0l0O); + wire_n1i1lll_dataout <= wire_nlll0lli_q(0) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi111i; + wire_n1i1llli_dataout <= n11O0O1l AND NOT(n1iO0l0O); + wire_n1i1llll_dataout <= n11O0O1O AND NOT(n1iO0l0O); + wire_n1i1lllO_dataout <= n11O0O0i AND NOT(n1iO0l0O); + wire_n1i1llO_dataout <= wire_nlll0lli_q(1) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi111l; + wire_n1i1llOi_dataout <= n11O0O0l AND NOT(n1iO0l0O); + wire_n1i1llOl_dataout <= n11O0O0O OR n1iO0l0O; + wire_n1i1llOO_dataout <= n11O0Oii AND NOT(n1iO0l0O); + wire_n1i1lO0i_dataout <= wire_n1i001lO_dataout AND NOT(n1iO0l0O); + wire_n1i1lO0l_dataout <= n11O0i1i AND NOT(n1iO0l0O); + wire_n1i1lO0O_dataout <= n11O00ll AND NOT(n1iO0l0O); + wire_n1i1lO1i_dataout <= n11O0Oil AND NOT(n1iO0l0O); + wire_n1i1lO1l_dataout <= wire_n1i001li_dataout AND NOT(n1iO0l0O); + wire_n1i1lO1O_dataout <= wire_n1i001ll_dataout AND NOT(n1iO0l0O); + wire_n1i1lOi_dataout <= wire_nlll0lli_q(2) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi111O; + wire_n1i1lOii_dataout <= wire_n1i001iO_dataout AND NOT(n1iO0l0O); + wire_n1i1lOil_dataout <= n11O1Oii AND NOT(n1iO0l0O); + wire_n1i1lOiO_dataout <= n11O0iOl AND NOT(niOli1iOl); + wire_n1i1lOl_dataout <= wire_nlll0lli_q(3) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi110i; + wire_n1i1lOli_dataout <= n11O0iOO AND NOT(niOli1iOl); + wire_n1i1lOll_dataout <= n11O0l1i AND NOT(niOli1iOl); + wire_n1i1lOlO_dataout <= n11O0l1l AND NOT(niOli1iOl); + wire_n1i1lOO_dataout <= wire_nlll0lli_q(4) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi110l; + wire_n1i1lOOi_dataout <= n11O0l1O AND NOT(niOli1iOl); + wire_n1i1lOOl_dataout <= n11O0l0i AND NOT(niOli1iOl); + wire_n1i1lOOO_dataout <= n11O0l0l AND NOT(niOli1iOl); + wire_n1i1O00i_dataout <= wire_n1i001li_dataout AND NOT(niOli1iOl); + wire_n1i1O00l_dataout <= wire_n1i001ll_dataout AND NOT(niOli1iOl); + wire_n1i1O00O_dataout <= wire_n1i001lO_dataout AND NOT(niOli1iOl); + wire_n1i1O01i_dataout <= n11O0O0O OR niOli1iOl; + wire_n1i1O01l_dataout <= n11O0Oii AND NOT(niOli1iOl); + wire_n1i1O01O_dataout <= n11O0Oil AND NOT(niOli1iOl); + wire_n1i1O0i_dataout <= wire_nlll0lli_q(8) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11iO; + wire_n1i1O0ii_dataout <= n11O0i1i AND NOT(niOli1iOl); + wire_n1i1O0il_dataout <= n11O00ll AND NOT(niOli1iOl); + wire_n1i1O0iO_dataout <= wire_n1i001iO_dataout AND NOT(niOli1iOl); + wire_n1i1O0l_dataout <= wire_nlll0lli_q(9) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11li; + wire_n1i1O0O_dataout <= wire_nlll0lli_q(10) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11ll; + wire_n1i1O0Oi_dataout <= wire_n1i1OO1i_dataout WHEN niOli1iOl = '1' ELSE n11O0iOl; + wire_n1i1O0Ol_dataout <= wire_n1i1OO1l_dataout WHEN niOli1iOl = '1' ELSE n11O0iOO; + wire_n1i1O0OO_dataout <= wire_n1i1OO1O_dataout WHEN niOli1iOl = '1' ELSE n11O0l1i; + wire_n1i1O10i_dataout <= n11O0liO AND NOT(niOli1iOl); + wire_n1i1O10l_dataout <= n11O0lli AND NOT(niOli1iOl); + wire_n1i1O10O_dataout <= n11O0lll AND NOT(niOli1iOl); + wire_n1i1O11i_dataout <= n11O0l0O AND NOT(niOli1iOl); + wire_n1i1O11l_dataout <= n11O0lii AND NOT(niOli1iOl); + wire_n1i1O11O_dataout <= n11O0lil AND NOT(niOli1iOl); + wire_n1i1O1i_dataout <= wire_nlll0lli_q(5) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi110O; + wire_n1i1O1ii_dataout <= n11O0llO AND NOT(niOli1iOl); + wire_n1i1O1il_dataout <= n11O0lOi AND NOT(niOli1iOl); + wire_n1i1O1iO_dataout <= n11O0lOl AND NOT(niOli1iOl); + wire_n1i1O1l_dataout <= wire_nlll0lli_q(6) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11ii; + wire_n1i1O1li_dataout <= n11O0lOO AND NOT(niOli1iOl); + wire_n1i1O1ll_dataout <= n11O0O1i AND NOT(niOli1iOl); + wire_n1i1O1lO_dataout <= n11O0O1l AND NOT(niOli1iOl); + wire_n1i1O1O_dataout <= wire_nlll0lli_q(7) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11il; + wire_n1i1O1Oi_dataout <= n11O0O1O AND NOT(niOli1iOl); + wire_n1i1O1Ol_dataout <= n11O0O0i AND NOT(niOli1iOl); + wire_n1i1O1OO_dataout <= n11O0O0l AND NOT(niOli1iOl); + wire_n1i1Oi0i_dataout <= wire_n1i1OOii_dataout WHEN niOli1iOl = '1' ELSE n11O0l0l; + wire_n1i1Oi0l_dataout <= wire_n1i1OOil_dataout WHEN niOli1iOl = '1' ELSE n11O0l0O; + wire_n1i1Oi0O_dataout <= wire_n1i1OOiO_dataout WHEN niOli1iOl = '1' ELSE n11O0lii; + wire_n1i1Oi1i_dataout <= wire_n1i1OO0i_dataout WHEN niOli1iOl = '1' ELSE n11O0l1l; + wire_n1i1Oi1l_dataout <= wire_n1i1OO0l_dataout WHEN niOli1iOl = '1' ELSE n11O0l1O; + wire_n1i1Oi1O_dataout <= wire_n1i1OO0O_dataout WHEN niOli1iOl = '1' ELSE n11O0l0i; + wire_n1i1Oii_dataout <= wire_nlll0lli_q(11) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11lO; + wire_n1i1Oiii_dataout <= wire_n1i1OOli_dataout WHEN niOli1iOl = '1' ELSE n11O0lil; + wire_n1i1Oiil_dataout <= wire_n1i1OOll_dataout WHEN niOli1iOl = '1' ELSE n11O0liO; + wire_n1i1OiiO_dataout <= wire_n1i1OOlO_dataout WHEN niOli1iOl = '1' ELSE n11O0lli; + wire_n1i1Oil_dataout <= wire_nlll0lli_q(12) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11Oi; + wire_n1i1Oili_dataout <= wire_n1i1OOOi_dataout WHEN niOli1iOl = '1' ELSE n11O0lll; + wire_n1i1Oill_dataout <= wire_n1i1OOOl_dataout WHEN niOli1iOl = '1' ELSE n11O0llO; + wire_n1i1OilO_dataout <= wire_n1i1OOOO_dataout WHEN niOli1iOl = '1' ELSE n11O0lOi; + wire_n1i1OiO_dataout <= wire_nlll0lli_q(13) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11Ol; + wire_n1i1OiOi_dataout <= wire_n1i0111i_dataout WHEN niOli1iOl = '1' ELSE n11O0lOl; + wire_n1i1OiOl_dataout <= wire_n1i0111l_dataout WHEN niOli1iOl = '1' ELSE n11O0lOO; + wire_n1i1OiOO_dataout <= wire_n1i0111O_dataout WHEN niOli1iOl = '1' ELSE n11O0O1i; + wire_n1i1Ol0i_dataout <= wire_n1i011ii_dataout WHEN niOli1iOl = '1' ELSE n11O0O0l; + wire_n1i1Ol0l_dataout <= wire_n1i011il_dataout WHEN niOli1iOl = '1' ELSE n11O0O0O; + wire_n1i1Ol0O_dataout <= wire_n1i011iO_dataout WHEN niOli1iOl = '1' ELSE n11O0Oii; + wire_n1i1Ol1i_dataout <= wire_n1i0110i_dataout WHEN niOli1iOl = '1' ELSE n11O0O1l; + wire_n1i1Ol1l_dataout <= wire_n1i0110l_dataout WHEN niOli1iOl = '1' ELSE n11O0O1O; + wire_n1i1Ol1O_dataout <= wire_n1i0110O_dataout WHEN niOli1iOl = '1' ELSE n11O0O0i; + wire_n1i1Oli_dataout <= wire_nlll0lli_q(14) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi11OO; + wire_n1i1Olii_dataout <= wire_n1i011li_dataout WHEN niOli1iOl = '1' ELSE n11O0Oil; + wire_n1i1Olil_dataout <= wire_n1i011ll_dataout WHEN niOli1iOl = '1' ELSE wire_n1i001li_dataout; + wire_n1i1OliO_dataout <= wire_n1i011lO_dataout WHEN niOli1iOl = '1' ELSE wire_n1i001ll_dataout; + wire_n1i1Oll_dataout <= wire_nlll0lli_q(15) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi101i; + wire_n1i1Olli_dataout <= wire_n1i011Oi_dataout WHEN niOli1iOl = '1' ELSE wire_n1i001lO_dataout; + wire_n1i1Olll_dataout <= wire_n1i011Ol_dataout WHEN niOli1iOl = '1' ELSE n11O0i1i; + wire_n1i1OllO_dataout <= wire_n1i011OO_dataout OR NOT(niOli1iOl); + wire_n1i1OlO_dataout <= wire_nlll0lli_q(16) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi101l; + wire_n1i1OlOi_dataout <= wire_n1i0101i_dataout WHEN niOli1iOl = '1' ELSE wire_n1i001iO_dataout; + wire_n1i1OlOl_dataout <= wire_n1i0101l_dataout WHEN niOli1iOl = '1' ELSE n11O1Oii; + wire_n1i1OlOO_dataout <= niOl0l10i WHEN niOli1iOl = '1' ELSE n11O1Oil; + wire_n1i1OO0i_dataout <= n11O0l1l WHEN niOl0l10i = '1' ELSE wire_n1i0100O_dataout; + wire_n1i1OO0l_dataout <= n11O0l1O WHEN niOl0l10i = '1' ELSE wire_n1i010ii_dataout; + wire_n1i1OO0O_dataout <= n11O0l0i WHEN niOl0l10i = '1' ELSE wire_n1i010il_dataout; + wire_n1i1OO1i_dataout <= n11O0iOl WHEN niOl0l10i = '1' ELSE wire_n1i0101O_dataout; + wire_n1i1OO1l_dataout <= n11O0iOO WHEN niOl0l10i = '1' ELSE wire_n1i0100i_dataout; + wire_n1i1OO1O_dataout <= n11O0l1i WHEN niOl0l10i = '1' ELSE wire_n1i0100l_dataout; + wire_n1i1OOi_dataout <= wire_nlll0lli_q(17) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi101O; + wire_n1i1OOii_dataout <= n11O0l0l WHEN niOl0l10i = '1' ELSE wire_n1i010iO_dataout; + wire_n1i1OOil_dataout <= n11O0l0O WHEN niOl0l10i = '1' ELSE wire_n1i010li_dataout; + wire_n1i1OOiO_dataout <= n11O0lii WHEN niOl0l10i = '1' ELSE wire_n1i010ll_dataout; + wire_n1i1OOl_dataout <= wire_nlll0lli_q(18) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi100i; + wire_n1i1OOli_dataout <= n11O0lil WHEN niOl0l10i = '1' ELSE wire_n1i010lO_dataout; + wire_n1i1OOll_dataout <= n11O0liO WHEN niOl0l10i = '1' ELSE wire_n1i010Oi_dataout; + wire_n1i1OOlO_dataout <= n11O0lli WHEN niOl0l10i = '1' ELSE wire_n1i010Ol_dataout; + wire_n1i1OOO_dataout <= wire_nlll0lli_q(19) WHEN wire_nl1000i_w_lg_nlO0llOi4286w(0) = '1' ELSE nlOi100l; + wire_n1i1OOOi_dataout <= n11O0lll WHEN niOl0l10i = '1' ELSE wire_n1i010OO_dataout; + wire_n1i1OOOl_dataout <= n11O0llO WHEN niOl0l10i = '1' ELSE wire_n1i01i1i_dataout; + wire_n1i1OOOO_dataout <= n11O0lOi WHEN niOl0l10i = '1' ELSE wire_n1i01i1l_dataout; + wire_n1ii000i_dataout <= wire_n1ii0iOl_dataout AND NOT(niOl0O0OO); + wire_n1ii000l_dataout <= wire_n1ii0iOO_dataout AND NOT(niOl0O0OO); + wire_n1ii000O_dataout <= wire_n1ii0l1i_dataout AND NOT(niOl0O0OO); + wire_n1ii001i_dataout <= wire_n1ii0ill_dataout AND NOT(niOl0O0OO); + wire_n1ii001l_dataout <= wire_n1ii0ilO_dataout AND NOT(niOl0O0OO); + wire_n1ii001O_dataout <= wire_n1ii0iOi_dataout AND NOT(niOl0O0OO); + wire_n1ii00i_dataout <= wire_n1il1iO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(112); + wire_n1ii00ii_dataout <= wire_n1ii0l1l_dataout AND NOT(niOl0O0OO); + wire_n1ii00il_dataout <= wire_n1ii0l1O_dataout AND NOT(niOl0O0OO); + wire_n1ii00iO_dataout <= wire_n1ii0l0i_dataout AND NOT(niOl0O0OO); + wire_n1ii00l_dataout <= wire_n1il1li_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(113); + wire_n1ii00li_dataout <= wire_n1ii0l0l_dataout OR niOl0O0OO; + wire_n1ii00ll_dataout <= wire_n1ii0l0O_dataout AND NOT(niOl0Oi1l); + wire_n1ii00lO_dataout <= wire_n1ii0lii_dataout AND NOT(niOl0Oi1l); + wire_n1ii00O_dataout <= wire_n1il1ll_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(114); + wire_n1ii00Oi_dataout <= wire_n1ii0lil_dataout AND NOT(niOl0Oi1l); + wire_n1ii00Ol_dataout <= wire_n1ii0liO_dataout AND NOT(niOl0Oi1l); + wire_n1ii00OO_dataout <= wire_n1ii0lli_dataout AND NOT(niOl0Oi1l); + wire_n1ii010i_dataout <= wire_n1ii00Ol_dataout AND NOT(niOl0O0OO); + wire_n1ii010l_dataout <= wire_n1ii00OO_dataout AND NOT(niOl0O0OO); + wire_n1ii010O_dataout <= wire_n1ii0i1i_dataout AND NOT(niOl0O0OO); + wire_n1ii011i_dataout <= wire_n1ii00ll_dataout AND NOT(niOl0O0OO); + wire_n1ii011l_dataout <= wire_n1ii00lO_dataout AND NOT(niOl0O0OO); + wire_n1ii011O_dataout <= wire_n1ii00Oi_dataout AND NOT(niOl0O0OO); + wire_n1ii01i_dataout <= wire_n1il10O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(109); + wire_n1ii01ii_dataout <= wire_n1ii0i1l_dataout AND NOT(niOl0O0OO); + wire_n1ii01il_dataout <= wire_n1ii0i1O_dataout AND NOT(niOl0O0OO); + wire_n1ii01iO_dataout <= wire_n1ii0i0i_dataout AND NOT(niOl0O0OO); + wire_n1ii01l_dataout <= wire_n1il1ii_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(110); + wire_n1ii01li_dataout <= wire_n1ii0i0l_dataout AND NOT(niOl0O0OO); + wire_n1ii01ll_dataout <= wire_n1ii0i0O_dataout AND NOT(niOl0O0OO); + wire_n1ii01lO_dataout <= wire_n1ii0iii_dataout AND NOT(niOl0O0OO); + wire_n1ii01O_dataout <= wire_n1il1il_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(111); + wire_n1ii01Oi_dataout <= wire_n1ii0iil_dataout AND NOT(niOl0O0OO); + wire_n1ii01Ol_dataout <= wire_n1ii0iiO_dataout AND NOT(niOl0O0OO); + wire_n1ii01OO_dataout <= wire_n1ii0ili_dataout AND NOT(niOl0O0OO); + wire_n1ii0i0i_dataout <= wire_n1ii0lOl_dataout AND NOT(niOl0Oi1l); + wire_n1ii0i0l_dataout <= wire_n1ii0lOO_dataout AND NOT(niOl0Oi1l); + wire_n1ii0i0O_dataout <= wire_n1ii0O1i_dataout AND NOT(niOl0Oi1l); + wire_n1ii0i1i_dataout <= wire_n1ii0lll_dataout AND NOT(niOl0Oi1l); + wire_n1ii0i1l_dataout <= wire_n1ii0llO_dataout AND NOT(niOl0Oi1l); + wire_n1ii0i1O_dataout <= wire_n1ii0lOi_dataout AND NOT(niOl0Oi1l); + wire_n1ii0ii_dataout <= wire_n1il1lO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(115); + wire_n1ii0iii_dataout <= wire_n1ii0O1l_dataout AND NOT(niOl0Oi1l); + wire_n1ii0iil_dataout <= wire_n1ii0O1O_dataout AND NOT(niOl0Oi1l); + wire_n1ii0iiO_dataout <= wire_n1ii0O0i_dataout AND NOT(niOl0Oi1l); + wire_n1ii0il_dataout <= wire_n1il1Oi_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(116); + wire_n1ii0ili_dataout <= wire_n1ii0O0l_dataout AND NOT(niOl0Oi1l); + wire_n1ii0ill_dataout <= wire_n1ii0O0O_dataout AND NOT(niOl0Oi1l); + wire_n1ii0ilO_dataout <= wire_n1ii0Oii_dataout AND NOT(niOl0Oi1l); + wire_n1ii0iO_dataout <= wire_n1il1Ol_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(117); + wire_n1ii0iOi_dataout <= wire_n1ii0Oil_dataout AND NOT(niOl0Oi1l); + wire_n1ii0iOl_dataout <= wire_n1ii0OiO_dataout AND NOT(niOl0Oi1l); + wire_n1ii0iOO_dataout <= wire_n1ii0Oli_dataout AND NOT(niOl0Oi1l); + wire_n1ii0l0i_dataout <= wire_n1ii0OOl_dataout AND NOT(niOl0Oi1l); + wire_n1ii0l0l_dataout <= wire_n1ii0OOO_dataout AND NOT(niOl0Oi1l); + wire_n1ii0l0O_dataout <= n11O0iOl AND NOT(niOl0Oi0i); + wire_n1ii0l1i_dataout <= wire_n1ii0Oll_dataout AND NOT(niOl0Oi1l); + wire_n1ii0l1l_dataout <= wire_n1ii0OlO_dataout AND NOT(niOl0Oi1l); + wire_n1ii0l1O_dataout <= wire_n1ii0OOi_dataout OR niOl0Oi1l; + wire_n1ii0li_dataout <= wire_n1il1OO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(118); + wire_n1ii0lii_dataout <= n11O0iOO AND NOT(niOl0Oi0i); + wire_n1ii0lil_dataout <= n11O0l1i AND NOT(niOl0Oi0i); + wire_n1ii0liO_dataout <= n11O0l1l AND NOT(niOl0Oi0i); + wire_n1ii0ll_dataout <= wire_n1il01i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(119); + wire_n1ii0lli_dataout <= n11O0l1O AND NOT(niOl0Oi0i); + wire_n1ii0lll_dataout <= n11O0l0i AND NOT(niOl0Oi0i); + wire_n1ii0llO_dataout <= n11O0l0l AND NOT(niOl0Oi0i); + wire_n1ii0lO_dataout <= wire_n1il01l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(120); + wire_n1ii0lOi_dataout <= n11O0l0O AND NOT(niOl0Oi0i); + wire_n1ii0lOl_dataout <= n11O0lii AND NOT(niOl0Oi0i); + wire_n1ii0lOO_dataout <= n11O0lil AND NOT(niOl0Oi0i); + wire_n1ii0O0i_dataout <= n11O0llO AND NOT(niOl0Oi0i); + wire_n1ii0O0l_dataout <= n11O0lOi AND NOT(niOl0Oi0i); + wire_n1ii0O0O_dataout <= n11O0lOl AND NOT(niOl0Oi0i); + wire_n1ii0O1i_dataout <= n11O0liO AND NOT(niOl0Oi0i); + wire_n1ii0O1l_dataout <= n11O0lli AND NOT(niOl0Oi0i); + wire_n1ii0O1O_dataout <= n11O0lll AND NOT(niOl0Oi0i); + wire_n1ii0Oi_dataout <= wire_n1il01O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(121); + wire_n1ii0Oii_dataout <= n11O0lOO AND NOT(niOl0Oi0i); + wire_n1ii0Oil_dataout <= n11O0O1i AND NOT(niOl0Oi0i); + wire_n1ii0OiO_dataout <= n11O0O1l AND NOT(niOl0Oi0i); + wire_n1ii0Ol_dataout <= wire_n1il00i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(122); + wire_n1ii0Oli_dataout <= n11O0O1O AND NOT(niOl0Oi0i); + wire_n1ii0Oll_dataout <= n11O0O0i AND NOT(niOl0Oi0i); + wire_n1ii0OlO_dataout <= n11O0O0l AND NOT(niOl0Oi0i); + wire_n1ii0OO_dataout <= wire_n1il00l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(123); + wire_n1ii0OOi_dataout <= n11O0O0O AND NOT(niOl0Oi0i); + wire_n1ii0OOl_dataout <= n11O0Oii AND NOT(niOl0Oi0i); + wire_n1ii0OOO_dataout <= n11O0Oil OR niOl0Oi0i; + wire_n1ii10i_dataout <= wire_n1iiOiO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(97); + wire_n1ii10l_dataout <= wire_n1iiOli_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(98); + wire_n1ii10O_dataout <= wire_n1iiOll_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(99); + wire_n1ii11i_dataout <= wire_n1iiO0O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(94); + wire_n1ii11l_dataout <= wire_n1iiOii_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(95); + wire_n1ii11O_dataout <= wire_n1iiOil_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(96); + wire_n1ii1ii_dataout <= wire_n1iiOlO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(100); + wire_n1ii1il_dataout <= wire_n1iiOOi_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(101); + wire_n1ii1iO_dataout <= wire_n1iiOOl_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(102); + wire_n1ii1l0i_dataout <= wire_n1ii1l0l_dataout OR niOli111O; + wire_n1ii1l0l_dataout <= n11O00lO AND NOT(niOO10l1i); + wire_n1ii1l0O_dataout <= wire_n1ii011i_dataout AND NOT(niOl0O0Ol); + wire_n1ii1l1l_dataout <= n11O0i1i OR wire_w_lg_niOl0O0Oi20806w(0); + wire_n1ii1l1O_dataout <= wire_n1ii1l0i_dataout WHEN wire_w_lg_niOl0O0Oi20806w(0) = '1' ELSE wire_n1ii1l0l_dataout; + wire_n1ii1li_dataout <= wire_n1iiOOO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(103); + wire_n1ii1lii_dataout <= wire_n1ii011l_dataout AND NOT(niOl0O0Ol); + wire_n1ii1lil_dataout <= wire_n1ii011O_dataout AND NOT(niOl0O0Ol); + wire_n1ii1liO_dataout <= wire_n1ii010i_dataout AND NOT(niOl0O0Ol); + wire_n1ii1ll_dataout <= wire_n1il11i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(104); + wire_n1ii1lli_dataout <= wire_n1ii010l_dataout AND NOT(niOl0O0Ol); + wire_n1ii1lll_dataout <= wire_n1ii010O_dataout AND NOT(niOl0O0Ol); + wire_n1ii1llO_dataout <= wire_n1ii01ii_dataout AND NOT(niOl0O0Ol); + wire_n1ii1lO_dataout <= wire_n1il11l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(105); + wire_n1ii1lOi_dataout <= wire_n1ii01il_dataout AND NOT(niOl0O0Ol); + wire_n1ii1lOl_dataout <= wire_n1ii01iO_dataout AND NOT(niOl0O0Ol); + wire_n1ii1lOO_dataout <= wire_n1ii01li_dataout AND NOT(niOl0O0Ol); + wire_n1ii1O0i_dataout <= wire_n1ii01Ol_dataout AND NOT(niOl0O0Ol); + wire_n1ii1O0l_dataout <= wire_n1ii01OO_dataout AND NOT(niOl0O0Ol); + wire_n1ii1O0O_dataout <= wire_n1ii001i_dataout AND NOT(niOl0O0Ol); + wire_n1ii1O1i_dataout <= wire_n1ii01ll_dataout AND NOT(niOl0O0Ol); + wire_n1ii1O1l_dataout <= wire_n1ii01lO_dataout AND NOT(niOl0O0Ol); + wire_n1ii1O1O_dataout <= wire_n1ii01Oi_dataout AND NOT(niOl0O0Ol); + wire_n1ii1Oi_dataout <= wire_n1il11O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(106); + wire_n1ii1Oii_dataout <= wire_n1ii001l_dataout AND NOT(niOl0O0Ol); + wire_n1ii1Oil_dataout <= wire_n1ii001O_dataout AND NOT(niOl0O0Ol); + wire_n1ii1OiO_dataout <= wire_n1ii000i_dataout AND NOT(niOl0O0Ol); + wire_n1ii1Ol_dataout <= wire_n1il10i_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(107); + wire_n1ii1Oli_dataout <= wire_n1ii000l_dataout AND NOT(niOl0O0Ol); + wire_n1ii1Oll_dataout <= wire_n1ii000O_dataout AND NOT(niOl0O0Ol); + wire_n1ii1OlO_dataout <= wire_n1ii00ii_dataout AND NOT(niOl0O0Ol); + wire_n1ii1OO_dataout <= wire_n1il10l_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(108); + wire_n1ii1OOi_dataout <= wire_n1ii00il_dataout OR niOl0O0Ol; + wire_n1ii1OOl_dataout <= wire_n1ii00iO_dataout AND NOT(niOl0O0Ol); + wire_n1ii1OOO_dataout <= wire_n1ii00li_dataout AND NOT(niOl0O0Ol); + wire_n1iii00i_dataout <= n11O0lOO AND NOT(niOl0Oi0l); + wire_n1iii00l_dataout <= n11O0O1i AND NOT(niOl0Oi0l); + wire_n1iii00O_dataout <= n11O0O1l AND NOT(niOl0Oi0l); + wire_n1iii01i_dataout <= n11O0llO AND NOT(niOl0Oi0l); + wire_n1iii01l_dataout <= n11O0lOi AND NOT(niOl0Oi0l); + wire_n1iii01O_dataout <= n11O0lOl AND NOT(niOl0Oi0l); + wire_n1iii0i_dataout <= wire_n1il0iO_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(127); + wire_n1iii0ii_dataout <= n11O0O1O AND NOT(niOl0Oi0l); + wire_n1iii0il_dataout <= n11O0O0i AND NOT(niOl0Oi0l); + wire_n1iii0iO_dataout <= n11O0O0l AND NOT(niOl0Oi0l); + wire_n1iii0l_dataout <= nlOi1O0l WHEN n1l000O = '1' ELSE wire_nlll0lli_q(132); + wire_n1iii0li_dataout <= n11O0O0O AND NOT(niOl0Oi0l); + wire_n1iii0ll_dataout <= n11O0Oii OR niOl0Oi0l; + wire_n1iii0lO_dataout <= n11O0Oil AND NOT(niOl0Oi0l); + wire_n1iii0O_dataout <= nlOi111i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1i1O; + wire_n1iii10i_dataout <= n11O0iOO AND NOT(niOl0Oi0l); + wire_n1iii10l_dataout <= n11O0l1i AND NOT(niOl0Oi0l); + wire_n1iii10O_dataout <= n11O0l1l AND NOT(niOl0Oi0l); + wire_n1iii11O_dataout <= n11O0iOl AND NOT(niOl0Oi0l); + wire_n1iii1i_dataout <= wire_n1il00O_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(124); + wire_n1iii1ii_dataout <= n11O0l1O AND NOT(niOl0Oi0l); + wire_n1iii1il_dataout <= n11O0l0i AND NOT(niOl0Oi0l); + wire_n1iii1iO_dataout <= n11O0l0l AND NOT(niOl0Oi0l); + wire_n1iii1l_dataout <= wire_n1il0ii_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(125); + wire_n1iii1li_dataout <= n11O0l0O AND NOT(niOl0Oi0l); + wire_n1iii1ll_dataout <= n11O0lii AND NOT(niOl0Oi0l); + wire_n1iii1lO_dataout <= n11O0lil AND NOT(niOl0Oi0l); + wire_n1iii1O_dataout <= wire_n1il0il_dataout WHEN n1l000O = '1' ELSE wire_nlll0lli_q(126); + wire_n1iii1Oi_dataout <= n11O0liO AND NOT(niOl0Oi0l); + wire_n1iii1Ol_dataout <= n11O0lli AND NOT(niOl0Oi0l); + wire_n1iii1OO_dataout <= n11O0lll AND NOT(niOl0Oi0l); + wire_n1iiii0O_dataout <= (n11O1OiO OR n1Oi1l0O) AND NOT(n1lillil); + wire_n1iiii1l_dataout <= n11O0i0l AND NOT(niOl0Oiii); + wire_n1iiiii_dataout <= nlOi111l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1i0i; + wire_n1iiiiii_dataout <= (n11O1Oli OR n011l0li) AND NOT(n1lillil); + wire_n1iiiiil_dataout <= (n11O1Oll OR n01O1OOl) AND NOT(n1lillil); + wire_n1iiiiiO_dataout <= (n11O1OlO OR n00ill1O) AND NOT(n1lillil); + wire_n1iiiil_dataout <= nlOi111O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1i0l; + wire_n1iiiili_dataout <= (n11O1OOi OR n0i000ii) AND NOT(n1lillil); + wire_n1iiiill_dataout <= (n11O1OOl OR n0iOlOll) AND NOT(n1lillil); + wire_n1iiiilO_dataout <= (n11O1OOO OR n0ll0iOO) AND NOT(n1lillil); + wire_n1iiiiO_dataout <= nlOi110i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1i0O; + wire_n1iiiiOi_dataout <= (n11O011i OR n0O0O00i) AND NOT(n1lillil); + wire_n1iiili_dataout <= nlOi110l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1iii; + wire_n1iiilii_dataout <= wire_n1iiilil_dataout OR (wire_nlOi0OO0l_w_lg_dataout20783w(0) AND (wire_nlOii10ll_dataout AND niOl0OiiO)); + wire_n1iiilil_dataout <= n11O01il AND wire_nlOii10ll_dataout; + wire_n1iiill_dataout <= nlOi110O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1iil; + wire_n1iiilll_dataout <= wire_n1iiillO_dataout OR (wire_nlOii10ii_dataout AND niOl0OiiO); + wire_n1iiillO_dataout <= n11O01iO AND wire_nlOii10ii_dataout; + wire_n1iiilO_dataout <= nlOi11ii WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1iiO; + wire_n1iiilOl_dataout <= wire_n1iiiOii_dataout OR niOl0Oili; + wire_n1iiilOO_dataout <= wire_n1iiiOil_dataout OR niOl0Oili; + wire_n1iiiO0i_dataout <= wire_n1iiiOll_dataout AND NOT(niOl0Oili); + wire_n1iiiO0l_dataout <= wire_n1iiiOlO_dataout AND NOT(niOl0Oili); + wire_n1iiiO0O_dataout <= wire_n1iiiOOi_dataout AND NOT(niOl0Oili); + wire_n1iiiO1i_dataout <= wire_n1iiiOiO_dataout OR niOl0Oili; + wire_n1iiiO1l_dataout <= wire_n1iiiOli_dataout OR niOl0Oili; + wire_n1iiiO1O_dataout <= wire_n1iiiOll_dataout AND NOT(niOl0Oili); + wire_n1iiiOi_dataout <= nlOi11il WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1ili; + wire_n1iiiOii_dataout <= wire_n1iiiOOl_dataout OR niOl0Oill; + wire_n1iiiOil_dataout <= wire_n1iiiOOO_dataout OR niOl0Oill; + wire_n1iiiOiO_dataout <= wire_n1iil11i_dataout AND NOT(niOl0Oill); + wire_n1iiiOl_dataout <= nlOi11iO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1ill; + wire_n1iiiOli_dataout <= wire_n1iil11l_dataout AND NOT(niOl0Oill); + wire_n1iiiOll_dataout <= wire_n1iil11O_dataout AND NOT(niOl0Oill); + wire_n1iiiOlO_dataout <= wire_n1iil10i_dataout AND NOT(niOl0Oill); + wire_n1iiiOO_dataout <= nlOi11li WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1ilO; + wire_n1iiiOOi_dataout <= wire_n1iil10l_dataout AND NOT(niOl0Oill); + wire_n1iiiOOl_dataout <= wire_n1iil10O_dataout OR niOl0OilO; + wire_n1iiiOOO_dataout <= wire_n1iil1ii_dataout AND NOT(niOl0OilO); + wire_n1iil00i_dataout <= wire_n1iil0iO_dataout AND NOT(niOl0OiOO); + wire_n1iil00l_dataout <= wire_n1iil0li_dataout AND NOT(niOl0OiOO); + wire_n1iil00O_dataout <= wire_n1iil0ll_dataout AND NOT(niOl0OiOO); + wire_n1iil01i_dataout <= wire_n1iil0ii_dataout AND NOT(niOl0OiOl); + wire_n1iil01l_dataout <= wire_n1iil0ii_dataout OR niOl0OiOl; + wire_n1iil01O_dataout <= wire_n1iil0il_dataout OR niOl0OiOl; + wire_n1iil0i_dataout <= nlOi11Ol WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1l1i; + wire_n1iil0ii_dataout <= wire_n1iil0lO_dataout AND NOT(niOl0OiOO); + wire_n1iil0il_dataout <= wire_n1iil0lO_dataout OR niOl0OiOO; + wire_n1iil0iO_dataout <= wire_w_lg_niOl0Ol1l20786w(0) AND NOT(niOl0Ol1i); + wire_n1iil0l_dataout <= nlOi11OO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1l1l; + wire_n1iil0li_dataout <= wire_n1iil0Ol_dataout OR niOl0Ol1i; + wire_n1iil0ll_dataout <= wire_n1iil0Oi_dataout OR niOl0Ol1i; + wire_n1iil0lO_dataout <= wire_n1iil0Ol_dataout AND NOT(niOl0Ol1i); + wire_n1iil0O_dataout <= nlOi101i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1l1O; + wire_n1iil0Oi_dataout <= wire_w_lg_niOl0Ol1O20785w(0) OR niOl0Ol1l; + wire_n1iil0Ol_dataout <= wire_w_lg_niOl0Ol1O20785w(0) AND NOT(niOl0Ol1l); + wire_n1iil10i_dataout <= wire_n1iil1ll_dataout AND NOT(niOl0OilO); + wire_n1iil10l_dataout <= wire_n1iil1lO_dataout AND NOT(niOl0OilO); + wire_n1iil10O_dataout <= wire_n1iil01i_dataout AND NOT(niOl0OiOi); + wire_n1iil11i_dataout <= wire_n1iil1il_dataout AND NOT(niOl0OilO); + wire_n1iil11l_dataout <= wire_n1iil1iO_dataout AND NOT(niOl0OilO); + wire_n1iil11O_dataout <= wire_n1iil1li_dataout AND NOT(niOl0OilO); + wire_n1iil1i_dataout <= nlOi11ll WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1iOi; + wire_n1iil1ii_dataout <= wire_n1iil1Oi_dataout AND NOT(niOl0OiOi); + wire_n1iil1il_dataout <= wire_n1iil1Ol_dataout AND NOT(niOl0OiOi); + wire_n1iil1iO_dataout <= wire_n1iil1OO_dataout AND NOT(niOl0OiOi); + wire_n1iil1l_dataout <= nlOi11lO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1iOl; + wire_n1iil1li_dataout <= wire_n1iil01i_dataout OR niOl0OiOi; + wire_n1iil1ll_dataout <= wire_n1iil01l_dataout OR niOl0OiOi; + wire_n1iil1lO_dataout <= wire_n1iil01O_dataout OR niOl0OiOi; + wire_n1iil1O_dataout <= nlOi11Oi WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1iOO; + wire_n1iil1Oi_dataout <= wire_n1iil00i_dataout AND NOT(niOl0OiOl); + wire_n1iil1Ol_dataout <= wire_n1iil00l_dataout AND NOT(niOl0OiOl); + wire_n1iil1OO_dataout <= wire_n1iil00O_dataout AND NOT(niOl0OiOl); + wire_n1iilii_dataout <= nlOi101l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1l0i; + wire_n1iilil_dataout <= nlOi101O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1l0l; + wire_n1iiliO_dataout <= nlOi100i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1l0O; + wire_n1iilli_dataout <= nlOi100l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1lii; + wire_n1iilll_dataout <= nlOi100O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1lil; + wire_n1iillll_dataout <= wire_n1iiO11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilllO_dataout <= wire_n1iiO10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iillO_dataout <= nlOi10ii WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1liO; + wire_n1iillOi_dataout <= wire_n1iiO10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iillOl_dataout <= wire_n1iiO10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iillOO_dataout <= wire_n1iiO1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilO0i_dataout <= wire_n1iiO1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilO0l_dataout <= wire_n1iiO1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilO0O_dataout <= wire_n1iiO1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilO1i_dataout <= wire_n1iiO1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilO1l_dataout <= wire_n1iiO1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilO1O_dataout <= wire_n1iiO1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOi_dataout <= nlOi10il WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1lli; + wire_n1iilOii_dataout <= wire_n1iiO1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOil_dataout <= wire_n1iiO1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOiO_dataout <= wire_n1iiO01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOl_dataout <= nlOi10iO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1lll; + wire_n1iilOli_dataout <= wire_n1iiO01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOll_dataout <= wire_n1iiO01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOlO_dataout <= wire_n1iiO00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOO_dataout <= nlOi10li WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1llO; + wire_n1iilOOi_dataout <= wire_n1iiO00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOOl_dataout <= wire_n1iiO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iilOOO_dataout <= wire_n1iiO0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiO00i_dataout <= wire_n1iiOl1i_dataout WHEN niOl0Olii = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1iiO00l_dataout <= wire_n1iiOl1l_dataout WHEN niOl0Olii = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1iiO00O_dataout <= wire_n1iiOl1O_dataout WHEN niOl0Olii = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1iiO01i_dataout <= wire_n1iiOiOi_dataout WHEN niOl0Olii = '1' ELSE wire_n1iiO0li_dataout; + wire_n1iiO01l_dataout <= wire_n1iiOiOl_dataout WHEN niOl0Olii = '1' ELSE wire_n1iiO0ll_dataout; + wire_n1iiO01O_dataout <= wire_n1iiOiOO_dataout WHEN niOl0Olii = '1' ELSE wire_n1iiO0lO_dataout; + wire_n1iiO0i_dataout <= nlOi10Ol WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1O1i; + wire_n1iiO0ii_dataout <= wire_n1iiOl0i_dataout WHEN niOl0Olii = '1' ELSE wire_n1iiO0Oi_dataout; + wire_n1iiO0il_dataout <= niOO0Olii OR niOli1iOO; + wire_n1iiO0iO_dataout <= niOO0Olii AND niOli1iOO; + wire_n1iiO0l_dataout <= nlOi10OO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1O1l; + wire_n1iiO0li_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) AND NOT(niOli1iOO); + wire_n1iiO0ll_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) AND niOli1iOO; + wire_n1iiO0lO_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) AND NOT(niOli1iOO); + wire_n1iiO0O_dataout <= nlOi1i1i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1O1O; + wire_n1iiO0Oi_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) AND niOli1iOO; + wire_n1iiO0Ol_dataout <= n1iilliO OR NOT(wire_w_lg_niOl0Ol0O20757w(0)); + wire_n1iiO0OO_dataout <= wire_n1iiOl0l_o(1) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n11Oi0ii; + wire_n1iiO10i_dataout <= wire_n1iiOi1i_dataout WHEN niOl0Olii = '1' ELSE wire_w_lg_niOli1iOO20777w(0); + wire_n1iiO10l_dataout <= wire_n1iiOi1l_dataout OR NOT(niOl0Olii); + wire_n1iiO10O_dataout <= wire_n1iiOi1O_dataout OR NOT(niOl0Olii); + wire_n1iiO11i_dataout <= wire_n1iiO11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiO11l_dataout <= wire_n1iiO0Ol_dataout AND niOl0Olii; + wire_n1iiO11O_dataout <= wire_n1iiO0OO_dataout AND niOl0Olii; + wire_n1iiO1i_dataout <= nlOi10ll WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1lOi; + wire_n1iiO1ii_dataout <= wire_n1iiOi0i_dataout OR NOT(niOl0Olii); + wire_n1iiO1il_dataout <= wire_n1iiOi0l_dataout WHEN niOl0Olii = '1' ELSE niOli1iOO; + wire_n1iiO1iO_dataout <= wire_n1iiOi0O_dataout AND niOl0Olii; + wire_n1iiO1l_dataout <= nlOi10lO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1lOl; + wire_n1iiO1li_dataout <= wire_n1iiOiii_dataout AND niOl0Olii; + wire_n1iiO1ll_dataout <= wire_n1iiOiil_dataout WHEN niOl0Olii = '1' ELSE wire_w_lg_niOli1iOO20777w(0); + wire_n1iiO1lO_dataout <= wire_n1iiOiiO_dataout WHEN niOl0Olii = '1' ELSE wire_n1iiO0il_dataout; + wire_n1iiO1O_dataout <= nlOi10Oi WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1lOO; + wire_n1iiO1Oi_dataout <= wire_n1iiOili_dataout WHEN niOl0Olii = '1' ELSE wire_n1iiO0iO_dataout; + wire_n1iiO1Ol_dataout <= wire_n1iiOill_dataout AND niOl0Olii; + wire_n1iiO1OO_dataout <= wire_n1iiOilO_dataout AND niOl0Olii; + wire_n1iiOi0i_dataout <= wire_n1iiOl0l_o(5) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iiliil; + wire_n1iiOi0l_dataout <= wire_n1iiOl0l_o(6) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iiliiO; + wire_n1iiOi0O_dataout <= wire_n1iiOl0l_o(7) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iilili; + wire_n1iiOi1i_dataout <= wire_n1iiOl0l_o(2) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iili0l; + wire_n1iiOi1l_dataout <= wire_n1iiOl0l_o(3) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iili0O; + wire_n1iiOi1O_dataout <= wire_n1iiOl0l_o(4) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iiliii; + wire_n1iiOii_dataout <= nlOi1i1l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1O0i; + wire_n1iiOiii_dataout <= wire_n1iiOl0l_o(8) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iilill; + wire_n1iiOiil_dataout <= wire_n1iiOl0l_o(9) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iililO; + wire_n1iiOiiO_dataout <= wire_n1iiOl0l_o(10) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iiliOi; + wire_n1iiOil_dataout <= nlOi1i1O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi111i; + wire_n1iiOili_dataout <= wire_n1iiOl0l_o(11) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iiliOl; + wire_n1iiOill_dataout <= wire_n1iiOl0l_o(12) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iiliOO; + wire_n1iiOilO_dataout <= wire_n1iiOl0l_o(13) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iill1i; + wire_n1iiOiO_dataout <= nlOi1i0i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi111l; + wire_n1iiOiOi_dataout <= wire_n1iiOl0l_o(14) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iill1l; + wire_n1iiOiOl_dataout <= wire_n1iiOl0l_o(15) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iill1O; + wire_n1iiOiOO_dataout <= wire_n1iiOl0l_o(16) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iill0i; + wire_n1iiOl0i_dataout <= wire_n1iiOl0l_o(20) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iillil; + wire_n1iiOl1i_dataout <= wire_n1iiOl0l_o(17) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iill0l; + wire_n1iiOl1l_dataout <= wire_n1iiOl0l_o(18) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iill0O; + wire_n1iiOl1O_dataout <= wire_n1iiOl0l_o(19) WHEN wire_w_lg_niOl0Ol0O20757w(0) = '1' ELSE n1iillii; + wire_n1iiOli_dataout <= nlOi1i0l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi111O; + wire_n1iiOll_dataout <= nlOi1i0O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi110i; + wire_n1iiOlO_dataout <= nlOi1iii WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi110l; + wire_n1iiOlOi_dataout <= wire_n1iiOO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiOlOl_dataout <= wire_n1iiOO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiOlOO_dataout <= wire_n1iiOO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiOO0i_dataout <= wire_n1iiOOll_dataout OR niOli1iOl; + wire_n1iiOO0l_dataout <= wire_n1iiOOlO_dataout OR niOli1iOl; + wire_n1iiOO0O_dataout <= wire_n1iiOOOi_dataout AND NOT(niOli1iOl); + wire_n1iiOO1i_dataout <= wire_n1iiOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiOO1l_dataout <= wire_n1iiOOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiOO1O_dataout <= wire_n1iiOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iiOOi_dataout <= nlOi1iil WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi110O; + wire_n1iiOOii_dataout <= wire_n1iiOOOl_dataout AND NOT(niOli1iOl); + wire_n1iiOOil_dataout <= wire_n1iiOOOO_dataout OR niOli1iOl; + wire_n1iiOOiO_dataout <= wire_n1iiOOli_dataout OR niOli1iOl; + wire_n1iiOOl_dataout <= nlOi1iiO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11ii; + wire_n1iiOOli_dataout <= wire_n1il111i_dataout AND n11O0iOO; + wire_n1iiOOll_dataout <= wire_n1il111l_dataout OR NOT(n11O0iOO); + wire_n1iiOOlO_dataout <= wire_n1il111O_dataout OR NOT(n11O0iOO); + wire_n1iiOOO_dataout <= nlOi1ili WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11il; + wire_n1iiOOOi_dataout <= wire_n1il110i_dataout AND n11O0iOO; + wire_n1iiOOOl_dataout <= wire_n1il110l_dataout AND n11O0iOO; + wire_n1iiOOOO_dataout <= wire_n1il110O_dataout OR NOT(n11O0iOO); + wire_n1il000i_dataout <= wire_n1il000O_dataout OR wire_niO01ill_w_lg_n11O0i1i20661w(0); + wire_n1il000l_dataout <= wire_n1il00ii_dataout OR wire_niO01ill_w_lg_n11O0i1i20661w(0); + wire_n1il000O_dataout <= wire_n1il00Ol_dataout WHEN wire_niO01ill_w_lg_n11O00ll20660w(0) = '1' ELSE wire_n1il00ll_dataout; + wire_n1il001i_dataout <= wire_n1il000l_dataout AND n11O0O0l; + wire_n1il001l_dataout <= n1il11li WHEN wire_niO01ill_w_lg_n11O0i1i20661w(0) = '1' ELSE wire_n1il00il_dataout; + wire_n1il001O_dataout <= n1il11lO WHEN wire_niO01ill_w_lg_n11O0i1i20661w(0) = '1' ELSE wire_n1il00iO_dataout; + wire_n1il00i_dataout <= nlOi1lOl WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10lO; + wire_n1il00ii_dataout <= wire_n1il00OO_dataout WHEN wire_niO01ill_w_lg_n11O00ll20660w(0) = '1' ELSE wire_n1il00lO_dataout; + wire_n1il00il_dataout <= wire_n1il0i1i_dataout WHEN wire_niO01ill_w_lg_n11O00ll20660w(0) = '1' ELSE wire_n1il00li_dataout; + wire_n1il00iO_dataout <= wire_n1il0i1l_dataout WHEN wire_niO01ill_w_lg_n11O00ll20660w(0) = '1' ELSE wire_n1il00Oi_dataout; + wire_n1il00l_dataout <= nlOi1lOO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10Oi; + wire_n1il00li_dataout <= wire_n1il0i1i_dataout AND NOT(wire_niO01ill_w_lg_n11l0Oii20659w(0)); + wire_n1il00ll_dataout <= wire_n1il00Ol_dataout AND NOT(wire_niO01ill_w_lg_n11l0Oii20659w(0)); + wire_n1il00lO_dataout <= wire_n1il00OO_dataout AND NOT(wire_niO01ill_w_lg_n11l0Oii20659w(0)); + wire_n1il00O_dataout <= nlOi1O1i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10Ol; + wire_n1il00Oi_dataout <= wire_n1il0i1l_dataout OR wire_niO01ill_w_lg_n11l0Oii20659w(0); + wire_n1il00Ol_dataout <= n1il11ll WHEN niOl0OlOi = '1' ELSE wire_n1il0i1O_dataout; + wire_n1il00OO_dataout <= n1il11Ol WHEN niOl0OlOi = '1' ELSE wire_n1il0i0l_dataout; + wire_n1il010i_dataout <= wire_n1ili01i_dataout WHEN n11O0lli = '1' ELSE n1il1i1O; + wire_n1il010l_dataout <= wire_n1ili01l_dataout WHEN n11O0lli = '1' ELSE n1il1i0i; + wire_n1il010O_dataout <= wire_n1ili01O_dataout WHEN n11O0lli = '1' ELSE n1il1i0l; + wire_n1il011i_dataout <= wire_n1ili1Oi_dataout WHEN n11O0lli = '1' ELSE n1il10OO; + wire_n1il011l_dataout <= wire_n1ili1Ol_dataout WHEN n11O0lli = '1' ELSE n1il1i1i; + wire_n1il011O_dataout <= wire_n1ili1OO_dataout WHEN n11O0lli = '1' ELSE n1il1i1l; + wire_n1il01i_dataout <= nlOi1lll WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10iO; + wire_n1il01ii_dataout <= n1il11OO WHEN n11O0Oil = '1' ELSE wire_n1il01li_dataout; + wire_n1il01il_dataout <= wire_n1il0llO_dataout WHEN n11O0Oil = '1' ELSE wire_n1il01iO_dataout; + wire_n1il01iO_dataout <= n1il11il WHEN n11O0l0O = '1' ELSE wire_n1il01ll_dataout; + wire_n1il01l_dataout <= nlOi1llO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10li; + wire_n1il01li_dataout <= n1il11OO WHEN n11O0l0O = '1' ELSE wire_n1il01lO_dataout; + wire_n1il01ll_dataout <= n1il11il AND n11O0O0l; + wire_n1il01lO_dataout <= n1il11OO AND n11O0O0l; + wire_n1il01O_dataout <= nlOi1lOi WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10ll; + wire_n1il01Oi_dataout <= wire_n1il001l_dataout AND n11O0O0l; + wire_n1il01Ol_dataout <= wire_n1il001O_dataout OR NOT(n11O0O0l); + wire_n1il01OO_dataout <= wire_n1il000i_dataout AND n11O0O0l; + wire_n1il0i0i_dataout <= n1il11lO WHEN niOl0OllO = '1' ELSE wire_n1il0iiO_dataout; + wire_n1il0i0l_dataout <= n1il11Ol WHEN niOl0OllO = '1' ELSE wire_n1il0ili_dataout; + wire_n1il0i0O_dataout <= wire_n1il0iil_dataout OR niOl0OllO; + wire_n1il0i1i_dataout <= n1il11li WHEN niOl0OlOi = '1' ELSE wire_n1il0i0O_dataout; + wire_n1il0i1l_dataout <= wire_n1il0i0i_dataout AND NOT(niOl0OlOi); + wire_n1il0i1O_dataout <= n1il11ll WHEN niOl0OllO = '1' ELSE wire_n1il0iii_dataout; + wire_n1il0ii_dataout <= nlOi1O1l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10OO; + wire_n1il0iii_dataout <= n1il11ll WHEN niOl0Olll = '1' ELSE wire_n1il0ill_dataout; + wire_n1il0iil_dataout <= wire_n1il0ilO_dataout AND NOT(niOl0Olll); + wire_n1il0iiO_dataout <= wire_n1il0iOi_dataout OR niOl0Olll; + wire_n1il0il_dataout <= nlOi1O1O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1i1i; + wire_n1il0ili_dataout <= n1il11Ol OR niOl0Olll; + wire_n1il0ill_dataout <= n1il11ll WHEN niOl0Olli = '1' ELSE wire_n1il0iOO_dataout; + wire_n1il0ilO_dataout <= wire_n1il0iOl_dataout OR niOl0Olli; + wire_n1il0iO_dataout <= nlOi1O0i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi1i1l; + wire_n1il0iOi_dataout <= n1il11lO AND NOT(niOl0Olli); + wire_n1il0iOl_dataout <= n1il11li AND NOT(niOl0OliO); + wire_n1il0iOO_dataout <= n1il11Oi WHEN niOl0OliO = '1' ELSE n1il11ll; + wire_n1il0liO_dataout <= n1il11Ol WHEN niOl0OlOO = '1' ELSE n1il11Oi; + wire_n1il0ll_dataout <= nlOi111i WHEN niOO00iOO = '1' ELSE nlOi1Oii; + wire_n1il0lli_dataout <= n1il11lO AND NOT(niOl0OlOO); + wire_n1il0lll_dataout <= n1il11lO WHEN niOl0OO1l = '1' ELSE wire_n1il0lOl_dataout; + wire_n1il0llO_dataout <= n1il11il WHEN niOl0OO1l = '1' ELSE wire_n1il0lOO_dataout; + wire_n1il0lO_dataout <= nlOi111l WHEN niOO00iOO = '1' ELSE nlOi1Oil; + wire_n1il0lOi_dataout <= wire_n1il0O1i_dataout OR niOl0OO1l; + wire_n1il0lOl_dataout <= n1il11lO WHEN niOl0OO1i = '1' ELSE wire_n1il0O0i_dataout; + wire_n1il0lOO_dataout <= wire_n1il0O1l_dataout OR niOl0OO1i; + wire_n1il0O0i_dataout <= wire_n1il0lli_dataout WHEN n1il11il = '1' ELSE n1il11lO; + wire_n1il0O0l_dataout <= n1il11il WHEN niOl0OlOO = '1' ELSE wire_n1il0O0O_dataout; + wire_n1il0O0O_dataout <= n1il11il AND NOT(n1il11Oi); + wire_n1il0O1i_dataout <= wire_n1il0O1O_dataout AND NOT(niOl0OO1i); + wire_n1il0O1l_dataout <= wire_n1il0O0l_dataout AND n1il11il; + wire_n1il0O1O_dataout <= wire_n1il0liO_dataout WHEN n1il11il = '1' ELSE n1il11Ol; + wire_n1il0Oi_dataout <= nlOi111O WHEN niOO00iOO = '1' ELSE nlOi1OiO; + wire_n1il0Ol_dataout <= nlOi110i WHEN niOO00iOO = '1' ELSE nlOi1Oli; + wire_n1il0Oll_dataout <= n1il11lO WHEN niOlO1O0i = '1' ELSE wire_n1ili00l_dataout; + wire_n1il0OlO_dataout <= wire_n1ill0OO_dataout AND NOT(niOlO1O0i); + wire_n1il0OO_dataout <= nlOi110l WHEN niOO00iOO = '1' ELSE nlOi1Oll; + wire_n1il0OOi_dataout <= wire_n1ili00i_dataout AND NOT(niOlO1O0i); + wire_n1il0OOl_dataout <= wire_n1ili00O_dataout AND NOT(niOlO1O0i); + wire_n1il0OOO_dataout <= wire_n1illili_dataout WHEN niOlO1O0i = '1' ELSE wire_n1ili0ii_dataout; + wire_n1il10i_dataout <= nlOi1iOl WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11lO; + wire_n1il10l_dataout <= nlOi1iOO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11Oi; + wire_n1il10O_dataout <= nlOi1l1i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11Ol; + wire_n1il110i_dataout <= wire_n1il11ii_o(3) WHEN wire_w_lg_niOl0Olil20684w(0) = '1' ELSE n1iiOlil; + wire_n1il110l_dataout <= wire_n1il11ii_o(4) WHEN wire_w_lg_niOl0Olil20684w(0) = '1' ELSE n1iiOliO; + wire_n1il110O_dataout <= wire_n1il11ii_o(5) WHEN wire_w_lg_niOl0Olil20684w(0) = '1' ELSE n1iiOlli; + wire_n1il111i_dataout <= n1iiOlll OR NOT(wire_w_lg_niOl0Olil20684w(0)); + wire_n1il111l_dataout <= wire_n1il11ii_o(1) WHEN wire_w_lg_niOl0Olil20684w(0) = '1' ELSE n1iillli; + wire_n1il111O_dataout <= wire_n1il11ii_o(2) WHEN wire_w_lg_niOl0Olil20684w(0) = '1' ELSE n1iiOlii; + wire_n1il11i_dataout <= nlOi1ill WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11iO; + wire_n1il11iO_dataout <= n1illl1i AND NOT(wire_niO01lOO_dataout); + wire_n1il11l_dataout <= nlOi1ilO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11li; + wire_n1il11O_dataout <= nlOi1iOi WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11ll; + wire_n1il1ii_dataout <= nlOi1l1l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi11OO; + wire_n1il1iii_dataout <= wire_n1il1lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1iil_dataout <= n1iiOllO AND NOT(wire_niO01lOO_dataout); + wire_n1il1iiO_dataout <= wire_n1il1O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1il_dataout <= nlOi1l1O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi101i; + wire_n1il1ili_dataout <= wire_n1il1O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1ill_dataout <= wire_n1il1O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1ilO_dataout <= wire_n1il1O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1iO_dataout <= nlOi1l0i WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi101l; + wire_n1il1iOi_dataout <= wire_n1il1O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1iOl_dataout <= wire_n1il1O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1iOO_dataout <= wire_n1il1Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1l0i_dataout <= wire_n1il1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1l0l_dataout <= wire_n1il1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1l0O_dataout <= wire_n1il1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1l1i_dataout <= wire_n1il1Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1l1l_dataout <= wire_n1il1OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1l1O_dataout <= wire_n1il1Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1li_dataout <= nlOi1l0l WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi101O; + wire_n1il1lii_dataout <= wire_n1il1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1lil_dataout <= wire_n1il1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1liO_dataout <= wire_n1il011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1ll_dataout <= nlOi1l0O WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi100i; + wire_n1il1lli_dataout <= wire_n1il011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1lll_dataout <= wire_n1il011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1llO_dataout <= wire_n1il010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1lO_dataout <= nlOi1lii WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi100l; + wire_n1il1lOi_dataout <= wire_n1il010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1lOl_dataout <= wire_n1il010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1il1lOO_dataout <= n1il11il WHEN n11O0lli = '1' ELSE wire_n1il01il_dataout; + wire_n1il1O0i_dataout <= wire_n1ili11i_dataout WHEN n11O0lli = '1' ELSE n1il101O; + wire_n1il1O0l_dataout <= wire_n1ili11l_dataout WHEN n11O0lli = '1' ELSE n1il100i; + wire_n1il1O0O_dataout <= wire_n1ili11O_dataout WHEN n11O0lli = '1' ELSE n1il100l; + wire_n1il1O1i_dataout <= wire_n1il0OlO_dataout WHEN n11O0lli = '1' ELSE n1il101i; + wire_n1il1O1l_dataout <= wire_n1il0OOl_dataout WHEN n11O0lli = '1' ELSE wire_n1il01ii_dataout; + wire_n1il1O1O_dataout <= wire_n1il0OOO_dataout WHEN n11O0lli = '1' ELSE n1il101l; + wire_n1il1Oi_dataout <= nlOi1lil WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi100O; + wire_n1il1Oii_dataout <= wire_n1ili10i_dataout WHEN n11O0lli = '1' ELSE n1il100O; + wire_n1il1Oil_dataout <= wire_n1ili10l_dataout WHEN n11O0lli = '1' ELSE n1il10ii; + wire_n1il1OiO_dataout <= wire_n1ili10O_dataout WHEN n11O0lli = '1' ELSE n1il10il; + wire_n1il1Ol_dataout <= nlOi1liO WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10ii; + wire_n1il1Oli_dataout <= wire_n1ili1ii_dataout WHEN n11O0lli = '1' ELSE n1il10iO; + wire_n1il1Oll_dataout <= wire_n1ili1il_dataout WHEN n11O0lli = '1' ELSE n1il10li; + wire_n1il1OlO_dataout <= wire_n1ili1iO_dataout WHEN n11O0lli = '1' ELSE n1il10ll; + wire_n1il1OO_dataout <= nlOi1lli WHEN wire_n1ll1Ol_w_lg_dataout4108w(0) = '1' ELSE nlOi10il; + wire_n1il1OOi_dataout <= wire_n1ili1li_dataout WHEN n11O0lli = '1' ELSE n1il10lO; + wire_n1il1OOl_dataout <= wire_n1ili1ll_dataout WHEN n11O0lli = '1' ELSE n1il10Oi; + wire_n1il1OOO_dataout <= wire_n1ili1lO_dataout WHEN n11O0lli = '1' ELSE n1il10Ol; + wire_n1ili00i_dataout <= wire_n1iliill_dataout WHEN niOl0OO0i = '1' ELSE n1il11Ol; + wire_n1ili00l_dataout <= wire_n1iliilO_dataout WHEN niOl0OO0i = '1' ELSE n1il11lO; + wire_n1ili00O_dataout <= wire_n1iliiOi_dataout WHEN niOl0OO0i = '1' ELSE n1il11OO; + wire_n1ili01i_dataout <= wire_n1iliiil_dataout AND NOT(niOlO1O0i); + wire_n1ili01l_dataout <= wire_n1iliiiO_dataout AND NOT(niOlO1O0i); + wire_n1ili01O_dataout <= wire_n1iliili_dataout AND NOT(niOlO1O0i); + wire_n1ili0i_dataout <= nlOi11iO WHEN niOO00iOO = '1' ELSE nlOi1OOO; + wire_n1ili0ii_dataout <= wire_n1iliiOl_dataout WHEN niOl0OO0i = '1' ELSE n1il101l; + wire_n1ili0il_dataout <= wire_n1iliiOO_dataout WHEN niOl0OO0i = '1' ELSE n1il101O; + wire_n1ili0iO_dataout <= wire_n1ilil1i_dataout WHEN niOl0OO0i = '1' ELSE n1il100i; + wire_n1ili0l_dataout <= nlOi11li WHEN niOO00iOO = '1' ELSE nlOi011i; + wire_n1ili0li_dataout <= wire_n1ilil1l_dataout WHEN niOl0OO0i = '1' ELSE n1il100l; + wire_n1ili0ll_dataout <= wire_n1ilil1O_dataout WHEN niOl0OO0i = '1' ELSE n1il100O; + wire_n1ili0lO_dataout <= wire_n1ilil0i_dataout WHEN niOl0OO0i = '1' ELSE n1il10ii; + wire_n1ili0O_dataout <= nlOi11ll WHEN niOO00iOO = '1' ELSE nlOi011l; + wire_n1ili0Oi_dataout <= wire_n1ilil0l_dataout WHEN niOl0OO0i = '1' ELSE n1il10il; + wire_n1ili0Ol_dataout <= wire_n1ilil0O_dataout WHEN niOl0OO0i = '1' ELSE n1il10iO; + wire_n1ili0OO_dataout <= wire_n1ililii_dataout WHEN niOl0OO0i = '1' ELSE n1il10li; + wire_n1ili10i_dataout <= wire_niO01ill_w_lg_n11O0ill20641w(0) WHEN niOlO1O0i = '1' ELSE wire_n1ili0ll_dataout; + wire_n1ili10l_dataout <= wire_n1illilO_dataout WHEN niOlO1O0i = '1' ELSE wire_n1ili0lO_dataout; + wire_n1ili10O_dataout <= wire_n1illiOi_dataout WHEN niOlO1O0i = '1' ELSE wire_n1ili0Oi_dataout; + wire_n1ili11i_dataout <= wire_n1illill_dataout WHEN niOlO1O0i = '1' ELSE wire_n1ili0il_dataout; + wire_n1ili11l_dataout <= n11O0ill WHEN niOlO1O0i = '1' ELSE wire_n1ili0iO_dataout; + wire_n1ili11O_dataout <= wire_niO01ill_w_lg_n11O0ill20641w(0) WHEN niOlO1O0i = '1' ELSE wire_n1ili0li_dataout; + wire_n1ili1i_dataout <= nlOi110O WHEN niOO00iOO = '1' ELSE nlOi1OlO; + wire_n1ili1ii_dataout <= wire_n1ili0Ol_dataout OR niOlO1O0i; + wire_n1ili1il_dataout <= wire_n1illiOl_dataout WHEN niOlO1O0i = '1' ELSE wire_n1ili0OO_dataout; + wire_n1ili1iO_dataout <= wire_n1ilii1i_dataout AND NOT(niOlO1O0i); + wire_n1ili1l_dataout <= nlOi11ii WHEN niOO00iOO = '1' ELSE nlOi1OOi; + wire_n1ili1li_dataout <= wire_n1illiOO_dataout WHEN niOlO1O0i = '1' ELSE wire_n1ilii1l_dataout; + wire_n1ili1ll_dataout <= wire_n1ilii1O_dataout AND NOT(niOlO1O0i); + wire_n1ili1lO_dataout <= wire_n1ilii0i_dataout AND NOT(niOlO1O0i); + wire_n1ili1O_dataout <= nlOi11il WHEN niOO00iOO = '1' ELSE nlOi1OOl; + wire_n1ili1Oi_dataout <= wire_n1ilii0l_dataout AND NOT(niOlO1O0i); + wire_n1ili1Ol_dataout <= wire_n1ilii0O_dataout AND NOT(niOlO1O0i); + wire_n1ili1OO_dataout <= wire_n1iliiii_dataout AND NOT(niOlO1O0i); + wire_n1ilii0i_dataout <= wire_n1ililll_dataout WHEN niOl0OO0i = '1' ELSE n1il10Ol; + wire_n1ilii0l_dataout <= wire_n1ilillO_dataout WHEN niOl0OO0i = '1' ELSE n1il10OO; + wire_n1ilii0O_dataout <= wire_n1ililOi_dataout WHEN niOl0OO0i = '1' ELSE n1il1i1i; + wire_n1ilii1i_dataout <= wire_n1ililil_dataout WHEN niOl0OO0i = '1' ELSE n1il10ll; + wire_n1ilii1l_dataout <= wire_n1ililiO_dataout WHEN niOl0OO0i = '1' ELSE n1il10lO; + wire_n1ilii1O_dataout <= wire_n1ililli_dataout WHEN niOl0OO0i = '1' ELSE n1il10Oi; + wire_n1iliii_dataout <= nlOi11lO WHEN niOO00iOO = '1' ELSE nlOi011O; + wire_n1iliiii_dataout <= wire_n1ililOl_dataout WHEN niOl0OO0i = '1' ELSE n1il1i1l; + wire_n1iliiil_dataout <= wire_n1ililOO_dataout WHEN niOl0OO0i = '1' ELSE n1il1i1O; + wire_n1iliiiO_dataout <= wire_n1iliO1i_dataout WHEN niOl0OO0i = '1' ELSE n1il1i0i; + wire_n1iliil_dataout <= nlOi11Oi WHEN niOO00iOO = '1' ELSE nlOi010i; + wire_n1iliili_dataout <= wire_n1iliO1l_dataout WHEN niOl0OO0i = '1' ELSE n1il1i0l; + wire_n1iliill_dataout <= n1il11Ol WHEN n1il11lO = '1' ELSE n1il11Oi; + wire_n1iliilO_dataout <= wire_n1iliO1O_dataout AND n1il11lO; + wire_n1iliiO_dataout <= nlOi11Ol WHEN niOO00iOO = '1' ELSE nlOi010l; + wire_n1iliiOi_dataout <= wire_n1iliO0i_dataout WHEN n1il11lO = '1' ELSE n1il11OO; + wire_n1iliiOl_dataout <= wire_n1iliO0l_dataout WHEN n1il11lO = '1' ELSE n1il101l; + wire_n1iliiOO_dataout <= wire_n1iliO0O_dataout WHEN n1il11lO = '1' ELSE n1il101O; + wire_n1ilil0i_dataout <= wire_n1iliOli_dataout WHEN n1il11lO = '1' ELSE n1il10ii; + wire_n1ilil0l_dataout <= wire_n1iliOll_dataout WHEN n1il11lO = '1' ELSE n1il10il; + wire_n1ilil0O_dataout <= wire_n1iliOlO_dataout WHEN n1il11lO = '1' ELSE n1il10iO; + wire_n1ilil1i_dataout <= wire_n1iliOii_dataout WHEN n1il11lO = '1' ELSE n1il100i; + wire_n1ilil1l_dataout <= wire_n1iliOil_dataout WHEN n1il11lO = '1' ELSE n1il100l; + wire_n1ilil1O_dataout <= wire_n1iliOiO_dataout WHEN n1il11lO = '1' ELSE n1il100O; + wire_n1ilili_dataout <= nlOi11OO WHEN niOO00iOO = '1' ELSE nlOi010O; + wire_n1ililii_dataout <= wire_n1iliOOi_dataout WHEN n1il11lO = '1' ELSE n1il10li; + wire_n1ililil_dataout <= wire_n1iliOOl_dataout WHEN n1il11lO = '1' ELSE n1il10ll; + wire_n1ililiO_dataout <= wire_n1iliOOO_dataout WHEN n1il11lO = '1' ELSE n1il10lO; + wire_n1ilill_dataout <= nlOi101i WHEN niOO00iOO = '1' ELSE nlOi01ii; + wire_n1ililli_dataout <= wire_n1ill11i_dataout WHEN n1il11lO = '1' ELSE n1il10Oi; + wire_n1ililll_dataout <= wire_n1ill11l_dataout WHEN n1il11lO = '1' ELSE n1il10Ol; + wire_n1ilillO_dataout <= wire_n1ill11O_dataout WHEN n1il11lO = '1' ELSE n1il10OO; + wire_n1ililO_dataout <= nlOi101l WHEN niOO00iOO = '1' ELSE nlOi01il; + wire_n1ililOi_dataout <= wire_n1ill10i_dataout WHEN n1il11lO = '1' ELSE n1il1i1i; + wire_n1ililOl_dataout <= wire_n1ill10l_dataout WHEN n1il11lO = '1' ELSE n1il1i1l; + wire_n1ililOO_dataout <= wire_n1ill10O_dataout WHEN n1il11lO = '1' ELSE n1il1i1O; + wire_n1iliO0i_dataout <= n1il11OO OR NOT(wire_w_lg_niOl0OO1O20640w(0)); + wire_n1iliO0l_dataout <= wire_n1ill1iO_dataout OR NOT(wire_w_lg_niOl0OO1O20640w(0)); + wire_n1iliO0O_dataout <= wire_n1ill1li_dataout OR NOT(wire_w_lg_niOl0OO1O20640w(0)); + wire_n1iliO1i_dataout <= wire_n1ill1ii_dataout WHEN n1il11lO = '1' ELSE n1il1i0i; + wire_n1iliO1l_dataout <= wire_n1ill1il_dataout WHEN n1il11lO = '1' ELSE n1il1i0l; + wire_n1iliO1O_dataout <= n1il11lO AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1iliOi_dataout <= nlOi101O WHEN niOO00iOO = '1' ELSE nlOi01iO; + wire_n1iliOii_dataout <= wire_n1ill1ll_dataout OR NOT(wire_w_lg_niOl0OO1O20640w(0)); + wire_n1iliOil_dataout <= wire_n1ill1lO_dataout OR NOT(wire_w_lg_niOl0OO1O20640w(0)); + wire_n1iliOiO_dataout <= wire_n1ill1Oi_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1iliOl_dataout <= nlOi100i WHEN niOO00iOO = '1' ELSE nlOi01li; + wire_n1iliOli_dataout <= wire_n1ill1Ol_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1iliOll_dataout <= wire_n1ill1OO_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1iliOlO_dataout <= wire_n1ill01i_dataout OR NOT(wire_w_lg_niOl0OO1O20640w(0)); + wire_n1iliOO_dataout <= nlOi100l WHEN niOO00iOO = '1' ELSE nlOi01ll; + wire_n1iliOOi_dataout <= wire_n1ill01l_dataout WHEN wire_w_lg_niOl0OO1O20640w(0) = '1' ELSE niOO0Olii; + wire_n1iliOOl_dataout <= wire_n1ill01O_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1iliOOO_dataout <= wire_n1ill00i_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1ill00i_dataout <= wire_n1ill0Oi_o(11) WHEN n1l110iO = '1' ELSE n1il10lO; + wire_n1ill00l_dataout <= wire_n1ill0Oi_o(12) WHEN n1l110iO = '1' ELSE n1il10Oi; + wire_n1ill00O_dataout <= wire_n1ill0Oi_o(13) WHEN n1l110iO = '1' ELSE n1il10Ol; + wire_n1ill01i_dataout <= wire_n1ill0Oi_o(8) WHEN n1l110iO = '1' ELSE n1il10iO; + wire_n1ill01l_dataout <= wire_n1ill0Oi_o(9) WHEN n1l110iO = '1' ELSE n1il10li; + wire_n1ill01O_dataout <= wire_n1ill0Oi_o(10) WHEN n1l110iO = '1' ELSE n1il10ll; + wire_n1ill0i_dataout <= nlOi10iO WHEN niOO00iOO = '1' ELSE nlOi01OO; + wire_n1ill0ii_dataout <= wire_n1ill0Oi_o(14) WHEN n1l110iO = '1' ELSE n1il10OO; + wire_n1ill0il_dataout <= wire_n1ill0Oi_o(15) WHEN n1l110iO = '1' ELSE n1il1i1i; + wire_n1ill0iO_dataout <= wire_n1ill0Oi_o(16) WHEN n1l110iO = '1' ELSE n1il1i1l; + wire_n1ill0l_dataout <= nlOi10li WHEN niOO00iOO = '1' ELSE nlOi001i; + wire_n1ill0li_dataout <= wire_n1ill0Oi_o(17) WHEN n1l110iO = '1' ELSE n1il1i1O; + wire_n1ill0ll_dataout <= wire_n1ill0Oi_o(18) WHEN n1l110iO = '1' ELSE n1il1i0i; + wire_n1ill0lO_dataout <= wire_n1ill0Oi_o(19) WHEN n1l110iO = '1' ELSE n1il1i0l; + wire_n1ill0O_dataout <= nlOi10ll WHEN niOO00iOO = '1' ELSE nlOi001l; + wire_n1ill0OO_dataout <= n1il101i OR (wire_w_lg_niOl0OO0l20555w(0) AND n1lillil); + wire_n1ill10i_dataout <= wire_n1ill0il_dataout WHEN wire_w_lg_niOl0OO1O20640w(0) = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1ill10l_dataout <= wire_n1ill0iO_dataout WHEN wire_w_lg_niOl0OO1O20640w(0) = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1ill10O_dataout <= wire_n1ill0li_dataout WHEN wire_w_lg_niOl0OO1O20640w(0) = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1ill11i_dataout <= wire_n1ill00l_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1ill11l_dataout <= wire_n1ill00O_dataout WHEN wire_w_lg_niOl0OO1O20640w(0) = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1ill11O_dataout <= wire_n1ill0ii_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1ill1i_dataout <= nlOi100O WHEN niOO00iOO = '1' ELSE nlOi01lO; + wire_n1ill1ii_dataout <= wire_n1ill0ll_dataout WHEN wire_w_lg_niOl0OO1O20640w(0) = '1' ELSE wire_niO01ill_w_lg_niOO0Olii20546w(0); + wire_n1ill1il_dataout <= wire_n1ill0lO_dataout AND wire_w_lg_niOl0OO1O20640w(0); + wire_n1ill1iO_dataout <= wire_n1ill0Oi_o(1) WHEN n1l110iO = '1' ELSE n1il101l; + wire_n1ill1l_dataout <= nlOi10ii WHEN niOO00iOO = '1' ELSE nlOi01Oi; + wire_n1ill1li_dataout <= wire_n1ill0Oi_o(2) WHEN n1l110iO = '1' ELSE n1il101O; + wire_n1ill1ll_dataout <= wire_n1ill0Oi_o(3) WHEN n1l110iO = '1' ELSE n1il100i; + wire_n1ill1lO_dataout <= wire_n1ill0Oi_o(4) WHEN n1l110iO = '1' ELSE n1il100l; + wire_n1ill1O_dataout <= nlOi10il WHEN niOO00iOO = '1' ELSE nlOi01Ol; + wire_n1ill1Oi_dataout <= wire_n1ill0Oi_o(5) WHEN n1l110iO = '1' ELSE n1il100O; + wire_n1ill1Ol_dataout <= wire_n1ill0Oi_o(6) WHEN n1l110iO = '1' ELSE n1il10ii; + wire_n1ill1OO_dataout <= wire_n1ill0Oi_o(7) WHEN n1l110iO = '1' ELSE n1il10il; + wire_n1illii_dataout <= nlOi10lO WHEN niOO00iOO = '1' ELSE nlOi001O; + wire_n1illil_dataout <= nlOi10Oi WHEN niOO00iOO = '1' ELSE nlOi000i; + wire_n1illili_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) AND NOT(n11O0ill); + wire_n1illill_dataout <= niOO0Olii OR n11O0ill; + wire_n1illilO_dataout <= niOO0Olii AND NOT(n11O0ill); + wire_n1illiO_dataout <= nlOi10Ol WHEN niOO00iOO = '1' ELSE nlOi000l; + wire_n1illiOi_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) OR n11O0ill; + wire_n1illiOl_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) AND NOT(n11O0ill); + wire_n1illiOO_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) AND NOT(n11O0ill); + wire_n1illl1l_dataout <= n1il11lO AND NOT(wire_niO01O0O_dataout); + wire_n1illli_dataout <= nlOi10OO WHEN niOO00iOO = '1' ELSE nlOi000O; + wire_n1illll_dataout <= nlOi1i1i WHEN niOO00iOO = '1' ELSE nlOi00ii; + wire_n1illlO_dataout <= nlOi1i1l WHEN niOO00iOO = '1' ELSE nlOi00il; + wire_n1illOi_dataout <= nlOi1i1O WHEN niOO00iOO = '1' ELSE nlOi00iO; + wire_n1illOl_dataout <= nlOi1i0i WHEN niOO00iOO = '1' ELSE nlOi00li; + wire_n1illOli_dataout <= wire_n1ilO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1illOll_dataout <= wire_n1ilO01O_dataout OR wire_niO01O0O_dataout; + wire_n1illOlO_dataout <= wire_n1ilO00i_dataout OR wire_niO01O0O_dataout; + wire_n1illOO_dataout <= nlOi1i0l WHEN niOO00iOO = '1' ELSE nlOi00ll; + wire_n1illOOi_dataout <= wire_n1ilO00l_dataout OR wire_niO01O0O_dataout; + wire_n1illOOl_dataout <= wire_n1ilO00O_dataout OR wire_niO01O0O_dataout; + wire_n1illOOO_dataout <= wire_n1ilO0ii_dataout OR wire_niO01O0O_dataout; + wire_n1ilO00i_dataout <= wire_n1ilOlOO_o(2) WHEN n1illOil = '1' ELSE wire_n1ilOili_dataout; + wire_n1ilO00l_dataout <= wire_n1ilOlOO_o(3) WHEN n1illOil = '1' ELSE wire_n1ilOill_dataout; + wire_n1ilO00O_dataout <= wire_n1ilOlOO_o(4) WHEN n1illOil = '1' ELSE wire_n1ilOilO_dataout; + wire_n1ilO01i_dataout <= n1il1i0O AND NOT(wire_niO01O0O_dataout); + wire_n1ilO01l_dataout <= wire_n1ilOiil_dataout AND NOT(n1illOil); + wire_n1ilO01O_dataout <= wire_n1ilOlOO_o(1) WHEN n1illOil = '1' ELSE wire_n1ilOiiO_dataout; + wire_n1ilO0i_dataout <= nlOi1iiO WHEN niOO00iOO = '1' ELSE nlOi00OO; + wire_n1ilO0ii_dataout <= wire_n1ilOlOO_o(5) WHEN n1illOil = '1' ELSE wire_n1ilOiOi_dataout; + wire_n1ilO0il_dataout <= wire_n1ilOlOO_o(6) WHEN n1illOil = '1' ELSE wire_n1ilOiOl_dataout; + wire_n1ilO0iO_dataout <= wire_n1ilOlOO_o(7) WHEN n1illOil = '1' ELSE wire_n1ilOiOO_dataout; + wire_n1ilO0l_dataout <= nlOi1ili WHEN niOO00iOO = '1' ELSE nlOi0i1i; + wire_n1ilO0li_dataout <= wire_n1ilOlOO_o(8) WHEN n1illOil = '1' ELSE wire_n1ilOl1i_dataout; + wire_n1ilO0ll_dataout <= wire_n1ilOlOO_o(9) WHEN n1illOil = '1' ELSE wire_n1ilOl1l_dataout; + wire_n1ilO0lO_dataout <= wire_n1ilOlOO_o(10) WHEN n1illOil = '1' ELSE wire_n1ilOl1O_dataout; + wire_n1ilO0O_dataout <= nlOi1ill WHEN niOO00iOO = '1' ELSE nlOi0i1l; + wire_n1ilO0Oi_dataout <= wire_n1ilOlOO_o(11) WHEN n1illOil = '1' ELSE wire_n1ilOl0i_dataout; + wire_n1ilO0Ol_dataout <= wire_n1ilOlOO_o(12) WHEN n1illOil = '1' ELSE wire_n1ilOl0l_dataout; + wire_n1ilO0OO_dataout <= wire_n1ilOlOO_o(13) WHEN n1illOil = '1' ELSE wire_n1ilOl0O_dataout; + wire_n1ilO10i_dataout <= wire_n1ilO0ll_dataout OR wire_niO01O0O_dataout; + wire_n1ilO10l_dataout <= wire_n1ilO0lO_dataout OR wire_niO01O0O_dataout; + wire_n1ilO10O_dataout <= wire_n1ilO0Oi_dataout OR wire_niO01O0O_dataout; + wire_n1ilO11i_dataout <= wire_n1ilO0il_dataout OR wire_niO01O0O_dataout; + wire_n1ilO11l_dataout <= wire_n1ilO0iO_dataout OR wire_niO01O0O_dataout; + wire_n1ilO11O_dataout <= wire_n1ilO0li_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1i_dataout <= nlOi1i0O WHEN niOO00iOO = '1' ELSE nlOi00lO; + wire_n1ilO1ii_dataout <= wire_n1ilO0Ol_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1il_dataout <= wire_n1ilO0OO_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1iO_dataout <= wire_n1ilOi1i_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1l_dataout <= nlOi1iii WHEN niOO00iOO = '1' ELSE nlOi00Oi; + wire_n1ilO1li_dataout <= wire_n1ilOi1l_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1ll_dataout <= wire_n1ilOi1O_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1lO_dataout <= wire_n1ilOi0i_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1O_dataout <= nlOi1iil WHEN niOO00iOO = '1' ELSE nlOi00Ol; + wire_n1ilO1Oi_dataout <= wire_n1ilOi0l_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1Ol_dataout <= wire_n1ilOi0O_dataout OR wire_niO01O0O_dataout; + wire_n1ilO1OO_dataout <= wire_n1ilOiii_dataout OR wire_niO01O0O_dataout; + wire_n1ilOi0i_dataout <= wire_n1ilOlOO_o(17) WHEN n1illOil = '1' ELSE wire_n1ilOlli_dataout; + wire_n1ilOi0l_dataout <= wire_n1ilOlOO_o(18) WHEN n1illOil = '1' ELSE wire_n1ilOlll_dataout; + wire_n1ilOi0O_dataout <= wire_n1ilOlOO_o(19) WHEN n1illOil = '1' ELSE wire_n1ilOllO_dataout; + wire_n1ilOi1i_dataout <= wire_n1ilOlOO_o(14) WHEN n1illOil = '1' ELSE wire_n1ilOlii_dataout; + wire_n1ilOi1l_dataout <= wire_n1ilOlOO_o(15) WHEN n1illOil = '1' ELSE wire_n1ilOlil_dataout; + wire_n1ilOi1O_dataout <= wire_n1ilOlOO_o(16) WHEN n1illOil = '1' ELSE wire_n1ilOliO_dataout; + wire_n1ilOii_dataout <= nlOi1ilO WHEN niOO00iOO = '1' ELSE nlOi0i1O; + wire_n1ilOiii_dataout <= wire_n1ilOlOO_o(20) WHEN n1illOil = '1' ELSE wire_n1ilOlOi_dataout; + wire_n1ilOiil_dataout <= n1illl1i OR NOT(wire_w_lg_niOl0OOOl20506w(0)); + wire_n1ilOiiO_dataout <= wire_n1ilOlOl_o(1) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illl1O; + wire_n1ilOil_dataout <= nlOi1iOi WHEN niOO00iOO = '1' ELSE nlOi0i0i; + wire_n1ilOili_dataout <= wire_n1ilOlOl_o(2) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illl0i; + wire_n1ilOill_dataout <= wire_n1ilOlOl_o(3) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illl0l; + wire_n1ilOilO_dataout <= wire_n1ilOlOl_o(4) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illl0O; + wire_n1ilOiO_dataout <= nlOi1iOl WHEN niOO00iOO = '1' ELSE nlOi0i0l; + wire_n1ilOiOi_dataout <= wire_n1ilOlOl_o(5) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illlii; + wire_n1ilOiOl_dataout <= wire_n1ilOlOl_o(6) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illlil; + wire_n1ilOiOO_dataout <= wire_n1ilOlOl_o(7) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illliO; + wire_n1ilOl0i_dataout <= wire_n1ilOlOl_o(11) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illlOi; + wire_n1ilOl0l_dataout <= wire_n1ilOlOl_o(12) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illlOl; + wire_n1ilOl0O_dataout <= wire_n1ilOlOl_o(13) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illlOO; + wire_n1ilOl1i_dataout <= wire_n1ilOlOl_o(8) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illlli; + wire_n1ilOl1l_dataout <= wire_n1ilOlOl_o(9) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illlll; + wire_n1ilOl1O_dataout <= wire_n1ilOlOl_o(10) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illllO; + wire_n1ilOli_dataout <= nlOi1iOO WHEN niOO00iOO = '1' ELSE nlOi0i0O; + wire_n1ilOlii_dataout <= wire_n1ilOlOl_o(14) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illO1i; + wire_n1ilOlil_dataout <= wire_n1ilOlOl_o(15) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illO1l; + wire_n1ilOliO_dataout <= wire_n1ilOlOl_o(16) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illO1O; + wire_n1ilOll_dataout <= nlOi1l1i WHEN niOO00iOO = '1' ELSE nlOi0iii; + wire_n1ilOlli_dataout <= wire_n1ilOlOl_o(17) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illO0i; + wire_n1ilOlll_dataout <= wire_n1ilOlOl_o(18) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illO0l; + wire_n1ilOllO_dataout <= wire_n1ilOlOl_o(19) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illO0O; + wire_n1ilOlO_dataout <= nlOi1l1l WHEN niOO00iOO = '1' ELSE nlOi0iil; + wire_n1ilOlOi_dataout <= wire_n1ilOlOl_o(20) WHEN wire_w_lg_niOl0OOOl20506w(0) = '1' ELSE n1illOii; + wire_n1ilOOi_dataout <= nlOi1l1O WHEN niOO00iOO = '1' ELSE nlOi0iiO; + wire_n1ilOOl_dataout <= nlOi1l0i WHEN niOO00iOO = '1' ELSE nlOi0ili; + wire_n1ilOOO_dataout <= nlOi1l0l WHEN niOO00iOO = '1' ELSE nlOi0ill; + wire_n1iO000i_dataout <= wire_n1iO00iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO000l_dataout <= wire_n1iO00li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO000O_dataout <= wire_n1iO00ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO001O_dataout <= wire_n1iO00il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO00i_dataout <= wire_n1l11iO_dataout WHEN k_hip(0) = '1' ELSE nlOi111O; + wire_n1iO00ii_dataout <= wire_n1iO00lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO00il_dataout <= wire_n1iO00Oi_dataout OR niOli11li; + wire_n1iO00iO_dataout <= wire_n1iO00Ol_dataout OR niOli11li; + wire_n1iO00l_dataout <= wire_n1l11li_dataout WHEN k_hip(0) = '1' ELSE nlOi110i; + wire_n1iO00li_dataout <= wire_n1iO00OO_dataout OR niOli11li; + wire_n1iO00ll_dataout <= wire_n1iO0i1i_dataout OR niOli11li; + wire_n1iO00lO_dataout <= wire_n1iO0i1l_dataout OR niOli11li; + wire_n1iO00O_dataout <= wire_n1l11ll_dataout WHEN k_hip(0) = '1' ELSE nlOi110l; + wire_n1iO00Oi_dataout <= wire_n1iO0i1O_o(1) WHEN niOli11ii = '1' ELSE n1iO11iO; + wire_n1iO00Ol_dataout <= wire_n1iO0i1O_o(2) WHEN niOli11ii = '1' ELSE n1iO01Oi; + wire_n1iO00OO_dataout <= wire_n1iO0i1O_o(3) WHEN niOli11ii = '1' ELSE n1iO01Ol; + wire_n1iO011i_dataout <= (n1ilOOii OR n0O0O0Ol) AND NOT(niOlO1O0i); + wire_n1iO01l_dataout <= wire_n1l11ii_dataout WHEN k_hip(0) = '1' ELSE nlOi111i; + wire_n1iO01li_dataout <= wire_n1iO01ll_dataout AND n11Oi1iO; + wire_n1iO01ll_dataout <= wire_n1iO01lO_dataout OR niOli11lO; + wire_n1iO01lO_dataout <= n1ilOOiO AND NOT(n1lillil); + wire_n1iO01O_dataout <= wire_n1l11il_dataout WHEN k_hip(0) = '1' ELSE nlOi111l; + wire_n1iO0i1i_dataout <= wire_n1iO0i1O_o(4) WHEN niOli11ii = '1' ELSE n1iO01OO; + wire_n1iO0i1l_dataout <= wire_n1iO0i1O_o(5) WHEN niOli11ii = '1' ELSE n1iO001i; + wire_n1iO0ii_dataout <= wire_n1l11lO_dataout WHEN k_hip(0) = '1' ELSE nlOi110O; + wire_n1iO0il_dataout <= wire_n1l11Oi_dataout WHEN k_hip(0) = '1' ELSE nlOi11ii; + wire_n1iO0iO_dataout <= wire_n1l11Ol_dataout WHEN k_hip(0) = '1' ELSE nlOi11il; + wire_n1iO0li_dataout <= wire_n1l11OO_dataout WHEN k_hip(0) = '1' ELSE nlOi11iO; + wire_n1iO0lii_dataout <= wire_n1iO0O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0lil_dataout <= wire_n1iO0O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0liO_dataout <= wire_n1iO0O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0ll_dataout <= wire_n1l101i_dataout WHEN k_hip(0) = '1' ELSE nlOi11li; + wire_n1iO0lli_dataout <= wire_n1iO0Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0lll_dataout <= wire_n1iO0Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0llO_dataout <= wire_n1iO0OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0lO_dataout <= wire_n1l101l_dataout WHEN k_hip(0) = '1' ELSE nlOi11ll; + wire_n1iO0lOi_dataout <= wire_n1iO0Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0lOl_dataout <= wire_n1iO0Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0lOO_dataout <= wire_n1iO0OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0O0i_dataout <= wire_n1iOi11i_dataout AND NOT(wire_n1iOilOO_dataout); + wire_n1iO0O0l_dataout <= wire_n1iOi01i_dataout WHEN wire_n1iOilOO_dataout = '1' ELSE wire_n1iOi11l_dataout; + wire_n1iO0O0O_dataout <= wire_n1iOi01l_dataout WHEN wire_n1iOilOO_dataout = '1' ELSE wire_n1iOi11O_dataout; + wire_n1iO0O1i_dataout <= wire_n1iO0OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0O1l_dataout <= wire_n1iO0OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0O1O_dataout <= wire_n1iO0OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO0Oi_dataout <= wire_n1l101O_dataout WHEN k_hip(0) = '1' ELSE nlOi11lO; + wire_n1iO0Oii_dataout <= wire_n1iOi01O_dataout WHEN wire_n1iOilOO_dataout = '1' ELSE wire_n1iOi10i_dataout; + wire_n1iO0Oil_dataout <= wire_n1iOi00i_dataout WHEN wire_n1iOilOO_dataout = '1' ELSE wire_n1iOi10l_dataout; + wire_n1iO0OiO_dataout <= wire_n1iOi00l_dataout WHEN wire_n1iOilOO_dataout = '1' ELSE wire_n1iOi10O_dataout; + wire_n1iO0Ol_dataout <= wire_n1l100i_dataout WHEN k_hip(0) = '1' ELSE nlOi11Oi; + wire_n1iO0Oli_dataout <= wire_n1iOi1ii_dataout AND NOT(wire_n1iOilOO_dataout); + wire_n1iO0Oll_dataout <= wire_n1iOi1il_dataout AND NOT(wire_n1iOilOO_dataout); + wire_n1iO0OlO_dataout <= wire_n1iOi1iO_dataout AND NOT(wire_n1iOilOO_dataout); + wire_n1iO0OO_dataout <= wire_n1l100l_dataout WHEN k_hip(0) = '1' ELSE nlOi11Ol; + wire_n1iO0OOi_dataout <= wire_n1iOi1li_dataout AND NOT(wire_n1iOilOO_dataout); + wire_n1iO0OOl_dataout <= wire_n1iOi00O_dataout WHEN wire_n1iOilOO_dataout = '1' ELSE wire_n1iOi1ll_dataout; + wire_n1iO0OOO_dataout <= wire_n1iOi1lO_dataout AND NOT(wire_n1iOilOO_dataout); + wire_n1iO100i_dataout <= wire_n1iO01li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO100l_dataout <= n1Oi1O1i AND NOT(wire_niO01lOO_dataout); + wire_n1iO100O_dataout <= n011li0l AND NOT(wire_niO01lOO_dataout); + wire_n1iO101i_dataout <= wire_n1iO1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO101l_dataout <= wire_n1iO011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO101O_dataout <= n1ilOOiO AND NOT(wire_niO01lOO_dataout); + wire_n1iO10i_dataout <= nlOi1liO WHEN niOO00iOO = '1' ELSE nlOi0iOO; + wire_n1iO10ii_dataout <= n01O01iO AND NOT(wire_niO01lOO_dataout); + wire_n1iO10il_dataout <= n00illOi AND NOT(wire_niO01lOO_dataout); + wire_n1iO10iO_dataout <= n0i00i1l AND NOT(wire_niO01lOO_dataout); + wire_n1iO10l_dataout <= nlOi1lli WHEN niOO00iOO = '1' ELSE nlOi0l1i; + wire_n1iO10li_dataout <= n0iOO10O AND NOT(wire_niO01lOO_dataout); + wire_n1iO10ll_dataout <= n0ll0lli AND NOT(wire_niO01lOO_dataout); + wire_n1iO10lO_dataout <= n0O0O0Ol AND NOT(wire_niO01lOO_dataout); + wire_n1iO10O_dataout <= nlOi1lll WHEN niOO00iOO = '1' ELSE nlOi0l1l; + wire_n1iO10Oi_dataout <= wire_n1iO1i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO10Ol_dataout <= wire_n1iO1i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO10OO_dataout <= wire_n1iO1i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO11i_dataout <= nlOi1l0O WHEN niOO00iOO = '1' ELSE nlOi0ilO; + wire_n1iO11l_dataout <= nlOi1lii WHEN niOO00iOO = '1' ELSE nlOi0iOi; + wire_n1iO11li_dataout <= wire_n1iO1OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO11ll_dataout <= wire_n1iO1Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO11lO_dataout <= wire_n1iO1Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO11O_dataout <= nlOi1lil WHEN niOO00iOO = '1' ELSE nlOi0iOl; + wire_n1iO11Oi_dataout <= wire_n1iO1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO11Ol_dataout <= wire_n1iO1OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO11OO_dataout <= wire_n1iO1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO1i0i_dataout <= wire_n1iO1ili_dataout OR niOli110l; + wire_n1iO1i0l_dataout <= wire_n1iO1ill_dataout OR niOli110l; + wire_n1iO1i0O_dataout <= wire_n1iO1ilO_dataout OR niOli110l; + wire_n1iO1i1i_dataout <= wire_n1iO1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO1i1l_dataout <= wire_n1iO1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO1i1O_dataout <= wire_n1iO1iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iO1ii_dataout <= nlOi1llO WHEN niOO00iOO = '1' ELSE nlOi0l1O; + wire_n1iO1iii_dataout <= wire_n1iO1iOi_dataout OR niOli110l; + wire_n1iO1iil_dataout <= wire_n1iO1iOl_dataout OR niOli110l; + wire_n1iO1iiO_dataout <= wire_n1iO1iOO_dataout AND NOT(niOli110l); + wire_n1iO1il_dataout <= nlOi1lOi WHEN niOO00iOO = '1' ELSE nlOi0l0i; + wire_n1iO1ili_dataout <= wire_n1iO1l1i_dataout OR niOli110i; + wire_n1iO1ill_dataout <= wire_n1iO1l1l_dataout OR niOli110i; + wire_n1iO1ilO_dataout <= wire_n1iO1l1O_dataout OR niOli110i; + wire_n1iO1iO_dataout <= nlOi1lOl WHEN niOO00iOO = '1' ELSE nlOi0l0l; + wire_n1iO1iOi_dataout <= wire_n1iO1l0i_dataout OR niOli110i; + wire_n1iO1iOl_dataout <= wire_n1iO1l0l_dataout OR niOli110i; + wire_n1iO1iOO_dataout <= wire_n1iO1l0O_dataout AND NOT(niOli110i); + wire_n1iO1l0i_dataout <= wire_n1iO1lOl_o(4) WHEN niOli111i = '1' ELSE wire_n1iO1lli_dataout; + wire_n1iO1l0l_dataout <= wire_n1iO1lOl_o(5) WHEN niOli111i = '1' ELSE wire_n1iO1lll_dataout; + wire_n1iO1l0O_dataout <= wire_n1iO1lOl_o(6) WHEN niOli111i = '1' ELSE wire_n1iO1llO_dataout; + wire_n1iO1l1i_dataout <= wire_n1iO1lOl_o(1) WHEN niOli111i = '1' ELSE wire_n1iO1lii_dataout; + wire_n1iO1l1l_dataout <= wire_n1iO1lOl_o(2) WHEN niOli111i = '1' ELSE wire_n1iO1lil_dataout; + wire_n1iO1l1O_dataout <= wire_n1iO1lOl_o(3) WHEN niOli111i = '1' ELSE wire_n1iO1liO_dataout; + wire_n1iO1li_dataout <= nlOi1lOO WHEN niOO00iOO = '1' ELSE nlOi0l0O; + wire_n1iO1lii_dataout <= n1iO111O OR niOl0OOOO; + wire_n1iO1lil_dataout <= n1iO110i OR niOl0OOOO; + wire_n1iO1liO_dataout <= n1iO110l OR niOl0OOOO; + wire_n1iO1ll_dataout <= nlOi1O1i WHEN niOO00iOO = '1' ELSE nlOi0lii; + wire_n1iO1lli_dataout <= n1iO110O OR niOl0OOOO; + wire_n1iO1lll_dataout <= n1iO11ii OR niOl0OOOO; + wire_n1iO1llO_dataout <= n1iO11il AND NOT(niOl0OOOO); + wire_n1iO1lO_dataout <= nlOi1O1l WHEN niOO00iOO = '1' ELSE nlOi0lil; + wire_n1iO1Oi_dataout <= nlOi1O1O WHEN niOO00iOO = '1' ELSE nlOi0liO; + wire_n1iO1OiO_dataout <= (n1illOiO OR n1Oi1O1i) AND NOT(niOlO1O0i); + wire_n1iO1Ol_dataout <= nlOi1O0i WHEN niOO00iOO = '1' ELSE nlOi0lli; + wire_n1iO1Oli_dataout <= (n1ilOO1i OR n011li0l) AND NOT(niOlO1O0i); + wire_n1iO1Oll_dataout <= (n1ilOO1l OR n01O01iO) AND NOT(niOlO1O0i); + wire_n1iO1OlO_dataout <= (n1ilOO1O OR n00illOi) AND NOT(niOlO1O0i); + wire_n1iO1OO_dataout <= nlOi1O0l WHEN niOO00iOO = '1' ELSE wire_n1l1OOl_dataout; + wire_n1iO1OOi_dataout <= (n1ilOO0i OR n0i00i1l) AND NOT(niOlO1O0i); + wire_n1iO1OOl_dataout <= (n1ilOO0l OR n0iOO10O) AND NOT(niOlO1O0i); + wire_n1iO1OOO_dataout <= (n1ilOO0O OR n0ll0lli) AND NOT(niOlO1O0i); + wire_n1iOi00i_dataout <= wire_n1iOi0iO_dataout AND NOT(niOli100l); + wire_n1iOi00l_dataout <= wire_n1iOi0li_dataout OR niOli100l; + wire_n1iOi00O_dataout <= wire_n1iOi0ll_dataout AND NOT(niOli100l); + wire_n1iOi01i_dataout <= wire_n1iOi0ii_dataout AND NOT(niOli100l); + wire_n1iOi01l_dataout <= wire_n1iOi0il_dataout AND NOT(niOli100l); + wire_n1iOi01O_dataout <= wire_n1iOi0il_dataout AND NOT(niOli100l); + wire_n1iOi0i_dataout <= wire_n1l10iO_dataout WHEN k_hip(0) = '1' ELSE nlOi101O; + wire_n1iOi0ii_dataout <= wire_n1iOi0lO_dataout AND NOT(n11O0O0O); + wire_n1iOi0il_dataout <= wire_n1iOi0Oi_dataout AND NOT(n11O0O0O); + wire_n1iOi0iO_dataout <= wire_n1iOi0Ol_dataout AND NOT(n11O0O0O); + wire_n1iOi0l_dataout <= wire_n1l10li_dataout WHEN k_hip(0) = '1' ELSE nlOi100i; + wire_n1iOi0li_dataout <= wire_n1iOi0OO_dataout AND NOT(n11O0O0O); + wire_n1iOi0ll_dataout <= wire_n1iOii1i_dataout OR n11O0O0O; + wire_n1iOi0lO_dataout <= wire_n1iOii1l_dataout AND NOT(n11O0O0i); + wire_n1iOi0O_dataout <= wire_n1l10ll_dataout WHEN k_hip(0) = '1' ELSE nlOi100l; + wire_n1iOi0Oi_dataout <= wire_n1iOii1O_dataout AND NOT(n11O0O0i); + wire_n1iOi0Ol_dataout <= wire_n1iOii0i_dataout OR n11O0O0i; + wire_n1iOi0OO_dataout <= wire_n1iOii0l_dataout AND NOT(n11O0O0i); + wire_n1iOi10i_dataout <= wire_n1iOi1Oi_o(4) WHEN niOli11OO = '1' ELSE n1iO0ilO; + wire_n1iOi10l_dataout <= wire_n1iOi1Oi_o(5) WHEN niOli11OO = '1' ELSE n1iO0iOi; + wire_n1iOi10O_dataout <= wire_n1iOi1Oi_o(6) WHEN niOli11OO = '1' ELSE n1iO0iOl; + wire_n1iOi11i_dataout <= wire_n1iOi1Oi_o(1) WHEN niOli11OO = '1' ELSE n1iO001l; + wire_n1iOi11l_dataout <= wire_n1iOi1Oi_o(2) WHEN niOli11OO = '1' ELSE n1iO0ili; + wire_n1iOi11O_dataout <= wire_n1iOi1Oi_o(3) WHEN niOli11OO = '1' ELSE n1iO0ill; + wire_n1iOi1i_dataout <= wire_n1l100O_dataout WHEN k_hip(0) = '1' ELSE nlOi11OO; + wire_n1iOi1ii_dataout <= wire_n1iOi1Oi_o(7) WHEN niOli11OO = '1' ELSE n1iO0iOO; + wire_n1iOi1il_dataout <= wire_n1iOi1Oi_o(8) WHEN niOli11OO = '1' ELSE n1iO0l1i; + wire_n1iOi1iO_dataout <= wire_n1iOi1Oi_o(9) WHEN niOli11OO = '1' ELSE n1iO0l1l; + wire_n1iOi1l_dataout <= wire_n1l10ii_dataout WHEN k_hip(0) = '1' ELSE nlOi101i; + wire_n1iOi1li_dataout <= wire_n1iOi1Oi_o(10) WHEN niOli11OO = '1' ELSE n1iO0l1O; + wire_n1iOi1ll_dataout <= wire_n1iOi1Oi_o(11) WHEN niOli11OO = '1' ELSE n1iO0l0i; + wire_n1iOi1lO_dataout <= wire_n1iOi1Oi_o(12) WHEN niOli11OO = '1' ELSE n1iO0l0l; + wire_n1iOi1O_dataout <= wire_n1l10il_dataout WHEN k_hip(0) = '1' ELSE nlOi101l; + wire_n1iOii0i_dataout <= wire_n1iOiiiO_dataout OR n11O0lOl; + wire_n1iOii0l_dataout <= wire_n1iOiili_dataout AND NOT(n11O0lOl); + wire_n1iOii0O_dataout <= wire_n1iOiill_dataout AND NOT(n11O0lOl); + wire_n1iOii1i_dataout <= wire_n1iOii0O_dataout AND NOT(n11O0O0i); + wire_n1iOii1l_dataout <= wire_n1iOiiii_dataout AND NOT(n11O0lOl); + wire_n1iOii1O_dataout <= wire_n1iOiiil_dataout AND NOT(n11O0lOl); + wire_n1iOiii_dataout <= wire_n1l10lO_dataout WHEN k_hip(0) = '1' ELSE nlOi100O; + wire_n1iOiiii_dataout <= wire_n1iOiilO_dataout OR n11O0lOi; + wire_n1iOiiil_dataout <= wire_n1iOiiOi_dataout AND NOT(n11O0lOi); + wire_n1iOiiiO_dataout <= wire_n1iOiiOl_dataout AND NOT(n11O0lOi); + wire_n1iOiil_dataout <= wire_n1l10Oi_dataout WHEN k_hip(0) = '1' ELSE nlOi10ii; + wire_n1iOiili_dataout <= niOli100i AND NOT(n11O0lOi); + wire_n1iOiill_dataout <= wire_n1iOiiOO_dataout AND NOT(n11O0lOi); + wire_n1iOiilO_dataout <= wire_n1iOil1i_dataout AND NOT(niOli100i); + wire_n1iOiiO_dataout <= wire_n1l10Ol_dataout WHEN k_hip(0) = '1' ELSE nlOi10il; + wire_n1iOiiOi_dataout <= wire_n1iOil1l_dataout AND NOT(niOli100i); + wire_n1iOiiOl_dataout <= wire_n1iOil1O_dataout AND NOT(niOli100i); + wire_n1iOiiOO_dataout <= n11O0llO AND NOT(niOli100i); + wire_n1iOil0i_dataout <= wire_n1iOilii_dataout AND NOT(n11O0lll); + wire_n1iOil0l_dataout <= wire_n1iOilil_dataout AND NOT(n11O0lll); + wire_n1iOil0O_dataout <= wire_n1iOiliO_dataout OR n11O0lll; + wire_n1iOil1i_dataout <= wire_n1iOil0i_dataout AND NOT(n11O0llO); + wire_n1iOil1l_dataout <= wire_n1iOil0l_dataout AND NOT(n11O0llO); + wire_n1iOil1O_dataout <= wire_n1iOil0O_dataout AND NOT(n11O0llO); + wire_n1iOili_dataout <= wire_n1l10OO_dataout WHEN k_hip(0) = '1' ELSE nlOi10iO; + wire_n1iOilii_dataout <= wire_n1iOilli_dataout OR n11O0liO; + wire_n1iOilil_dataout <= wire_n1iOilli_dataout AND NOT(n11O0liO); + wire_n1iOiliO_dataout <= wire_n1iOilll_dataout AND NOT(n11O0liO); + wire_n1iOill_dataout <= wire_n1l1i1i_dataout WHEN k_hip(0) = '1' ELSE nlOi10li; + wire_n1iOilli_dataout <= niOli101O AND NOT(n11O0lii); + wire_n1iOilll_dataout <= wire_w_lg_niOli101O20189w(0) OR n11O0lii; + wire_n1iOilO_dataout <= wire_n1l1i1l_dataout WHEN k_hip(0) = '1' ELSE nlOi10ll; + wire_n1iOilOO_dataout <= wire_n1iOiO1i_dataout OR (n11O0O0O AND niOli100O); + wire_n1iOilOO_w_lg_dataout20251w(0) <= wire_n1iOilOO_dataout OR wire_niO01ill_w_lg_n11O0lll20250w(0); + wire_n1iOiO0i_dataout <= wire_n1iOiO0l_dataout OR (n11O0llO AND niOli10il); + wire_n1iOiO0l_dataout <= wire_n1iOiO0O_dataout OR (n11O0l0O AND niOli10il); + wire_n1iOiO0O_dataout <= wire_n1iOiOii_dataout OR ((n11O0lll AND niOli10il) AND niOli10ii); + wire_n1iOiO1i_dataout <= wire_n1iOiO1l_dataout OR (n11O0O0i AND niOli10il); + wire_n1iOiO1l_dataout <= wire_n1iOiO1O_dataout OR (n11O0lOl AND niOli10il); + wire_n1iOiO1O_dataout <= wire_n1iOiO0i_dataout OR (n11O0lOi AND niOli10iO); + wire_n1iOiOi_dataout <= wire_n1l1i1O_dataout WHEN k_hip(0) = '1' ELSE nlOi10lO; + wire_n1iOiOii_dataout <= wire_n1iOiOil_dataout OR (n11O0liO AND niOli10iO); + wire_n1iOiOil_dataout <= n11O0lli OR (wire_niO01ill_w_lg_n11Oi10l20175w(0) AND n11O0lii); + wire_n1iOiOl_dataout <= wire_n1l1i0i_dataout WHEN k_hip(0) = '1' ELSE nlOi10Oi; + wire_n1iOiOO_dataout <= wire_n1l1i0l_dataout WHEN k_hip(0) = '1' ELSE nlOi10Ol; + wire_n1iOl0i_dataout <= wire_n1l1iiO_dataout WHEN k_hip(0) = '1' ELSE nlOi1i1O; + wire_n1iOl0l_dataout <= wire_n1l1ili_dataout WHEN k_hip(0) = '1' ELSE nlOi1i0i; + wire_n1iOl0O_dataout <= wire_n1l1ill_dataout WHEN k_hip(0) = '1' ELSE nlOi1i0l; + wire_n1iOl0OO_dataout <= wire_n1iOllll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOl1i_dataout <= wire_n1l1i0O_dataout WHEN k_hip(0) = '1' ELSE nlOi10OO; + wire_n1iOl1l_dataout <= wire_n1l1iii_dataout WHEN k_hip(0) = '1' ELSE nlOi1i1i; + wire_n1iOl1O_dataout <= wire_n1l1iil_dataout WHEN k_hip(0) = '1' ELSE nlOi1i1l; + wire_n1iOli0i_dataout <= wire_n1iOlO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOli0l_dataout <= wire_n1iOlO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOli0O_dataout <= wire_n1iOlO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOli1i_dataout <= wire_n1iOlO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOli1l_dataout <= wire_n1iOlO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOli1O_dataout <= wire_n1iOlO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOlii_dataout <= wire_n1l1ilO_dataout WHEN k_hip(0) = '1' ELSE nlOi1i0O; + wire_n1iOliii_dataout <= wire_n1iOO1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOliil_dataout <= wire_n1iOO1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOliiO_dataout <= wire_n1iOO1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOlil_dataout <= wire_n1l1iOi_dataout WHEN k_hip(0) = '1' ELSE nlOi1iii; + wire_n1iOlili_dataout <= wire_n1iOO1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOlill_dataout <= wire_n1iOO1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOlilO_dataout <= wire_n1iOO01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOliO_dataout <= wire_n1l1iOl_dataout WHEN k_hip(0) = '1' ELSE nlOi1iil; + wire_n1iOliOi_dataout <= wire_n1iOO01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOliOl_dataout <= wire_n1iOO01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOliOO_dataout <= wire_n1iOO00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOll0i_dataout <= wire_n1iOO0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOll0l_dataout <= wire_n1iOO0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOll0O_dataout <= wire_n1iOO0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOll1i_dataout <= wire_n1iOO00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOll1l_dataout <= wire_n1iOO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOll1O_dataout <= wire_n1iOO0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOlli_dataout <= wire_n1l1iOO_dataout WHEN k_hip(0) = '1' ELSE nlOi1iiO; + wire_n1iOllii_dataout <= wire_n1iOO0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOllil_dataout <= wire_n1iOO0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOlliO_dataout <= wire_n1iOO0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOlll_dataout <= wire_n1l1l1i_dataout WHEN k_hip(0) = '1' ELSE nlOi1ili; + wire_n1iOllli_dataout <= wire_n1iOO0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1iOllll_dataout <= wire_n1iOlllO_dataout AND NOT((niOli10Oi OR (niOli10OO OR n11O1Oil))); + wire_n1iOlllO_dataout <= n1iO0l0O OR (niOli10ll AND niOli10li); + wire_n1iOllO_dataout <= wire_n1l1l1l_dataout WHEN k_hip(0) = '1' ELSE nlOi1ill; + wire_n1iOlO0i_dataout <= wire_n1iOlOli_dataout AND NOT(niOli10lO); + wire_n1iOlO0l_dataout <= wire_n1iOlOll_dataout AND NOT(niOli10lO); + wire_n1iOlO0O_dataout <= wire_n1iOlOlO_dataout AND NOT(niOli10lO); + wire_n1iOlO1i_dataout <= wire_n1iOlOii_dataout AND NOT(niOli10lO); + wire_n1iOlO1l_dataout <= wire_n1iOlOil_dataout AND NOT(niOli10lO); + wire_n1iOlO1O_dataout <= wire_n1iOlOiO_dataout AND NOT(niOli10lO); + wire_n1iOlOi_dataout <= wire_n1l1l1O_dataout WHEN k_hip(0) = '1' ELSE nlOi1ilO; + wire_n1iOlOii_dataout <= wire_n1iOlOOi_dataout AND NOT(n11O1Oil); + wire_n1iOlOil_dataout <= wire_n1iOlOOl_dataout AND NOT(n11O1Oil); + wire_n1iOlOiO_dataout <= wire_n1iOlOOO_dataout AND NOT(n11O1Oil); + wire_n1iOlOl_dataout <= wire_n1l1l0i_dataout WHEN k_hip(0) = '1' ELSE nlOi1iOi; + wire_n1iOlOli_dataout <= wire_n1iOO11i_dataout AND NOT(n11O1Oil); + wire_n1iOlOll_dataout <= wire_n1iOO11l_dataout AND NOT(n11O1Oil); + wire_n1iOlOlO_dataout <= wire_n1iOO11O_dataout AND NOT(n11O1Oil); + wire_n1iOlOO_dataout <= wire_n1l1l0l_dataout WHEN k_hip(0) = '1' ELSE nlOi1iOl; + wire_n1iOlOOi_dataout <= wire_n1iOO10i_dataout WHEN niOli10ll = '1' ELSE n1iOl10i; + wire_n1iOlOOl_dataout <= wire_n1iOO10l_dataout WHEN niOli10ll = '1' ELSE n1iOl10l; + wire_n1iOlOOO_dataout <= wire_n1iOO10O_dataout WHEN niOli10ll = '1' ELSE n1iOl10O; + wire_n1iOO00i_dataout <= wire_n1iOOiil_dataout AND NOT(niOli10lO); + wire_n1iOO00l_dataout <= wire_n1iOOiiO_dataout AND NOT(niOli10lO); + wire_n1iOO00O_dataout <= wire_n1iOOili_dataout AND NOT(niOli10lO); + wire_n1iOO01i_dataout <= wire_n1iOOi0l_dataout AND NOT(niOli10lO); + wire_n1iOO01l_dataout <= wire_n1iOOi0O_dataout AND NOT(niOli10lO); + wire_n1iOO01O_dataout <= wire_n1iOOiii_dataout AND NOT(niOli10lO); + wire_n1iOO0i_dataout <= wire_n1l1liO_dataout WHEN k_hip(0) = '1' ELSE nlOi1l1O; + wire_n1iOO0ii_dataout <= wire_n1iOOill_dataout AND NOT(niOli10lO); + wire_n1iOO0il_dataout <= wire_n1iOOilO_dataout AND NOT(niOli10lO); + wire_n1iOO0iO_dataout <= wire_n1iOOiOi_dataout AND NOT(niOli10lO); + wire_n1iOO0l_dataout <= wire_n1l1lli_dataout WHEN k_hip(0) = '1' ELSE nlOi1l0i; + wire_n1iOO0li_dataout <= wire_n1iOOiOl_dataout AND NOT(niOli10lO); + wire_n1iOO0ll_dataout <= wire_n1iOOiOO_dataout AND NOT(niOli10lO); + wire_n1iOO0lO_dataout <= wire_n1iOOl1i_dataout AND NOT(niOli10lO); + wire_n1iOO0O_dataout <= wire_n1l1lll_dataout WHEN k_hip(0) = '1' ELSE nlOi1l0l; + wire_n1iOO0Oi_dataout <= wire_n1iOOl1l_dataout AND NOT(niOli10lO); + wire_n1iOO0Ol_dataout <= wire_n1iOOl1O_dataout AND NOT(niOli10lO); + wire_n1iOO0OO_dataout <= wire_n1iOOOiO_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOl0i_dataout; + wire_n1iOO10i_dataout <= wire_n1iOO1li_o(0) WHEN n1l110iO = '1' ELSE n1iOl10i; + wire_n1iOO10l_dataout <= wire_n1iOO1li_o(1) WHEN n1l110iO = '1' ELSE n1iOl10l; + wire_n1iOO10O_dataout <= wire_n1iOO1li_o(2) WHEN n1l110iO = '1' ELSE n1iOl10O; + wire_n1iOO11i_dataout <= wire_n1iOO1ii_dataout WHEN niOli10ll = '1' ELSE n1iOl1ii; + wire_n1iOO11l_dataout <= wire_n1iOO1il_dataout WHEN niOli10ll = '1' ELSE n1iOl1il; + wire_n1iOO11O_dataout <= wire_n1iOO1iO_dataout WHEN niOli10ll = '1' ELSE n1iOl1iO; + wire_n1iOO1i_dataout <= wire_n1l1l0O_dataout WHEN k_hip(0) = '1' ELSE nlOi1iOO; + wire_n1iOO1ii_dataout <= wire_n1iOO1li_o(3) WHEN n1l110iO = '1' ELSE n1iOl1ii; + wire_n1iOO1il_dataout <= wire_n1iOO1li_o(4) WHEN n1l110iO = '1' ELSE n1iOl1il; + wire_n1iOO1iO_dataout <= wire_n1iOO1li_o(5) WHEN n1l110iO = '1' ELSE n1iOl1iO; + wire_n1iOO1l_dataout <= wire_n1l1lii_dataout WHEN k_hip(0) = '1' ELSE nlOi1l1i; + wire_n1iOO1ll_dataout <= wire_n1iOO0OO_dataout AND NOT(niOli10lO); + wire_n1iOO1lO_dataout <= wire_n1iOOi1i_dataout AND NOT(niOli10lO); + wire_n1iOO1O_dataout <= wire_n1l1lil_dataout WHEN k_hip(0) = '1' ELSE nlOi1l1l; + wire_n1iOO1Oi_dataout <= wire_n1iOOi1l_dataout AND NOT(niOli10lO); + wire_n1iOO1Ol_dataout <= wire_n1iOOi1O_dataout AND NOT(niOli10lO); + wire_n1iOO1OO_dataout <= wire_n1iOOi0i_dataout AND NOT(niOli10lO); + wire_n1iOOi0i_dataout <= wire_n1iOOOOi_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOlil_dataout; + wire_n1iOOi0l_dataout <= wire_n1iOOOOl_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOliO_dataout; + wire_n1iOOi0O_dataout <= wire_n1iOOOOO_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOlli_dataout; + wire_n1iOOi1i_dataout <= wire_n1iOOOli_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOl0l_dataout; + wire_n1iOOi1l_dataout <= wire_n1iOOOll_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOl0O_dataout; + wire_n1iOOi1O_dataout <= wire_n1iOOOlO_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOlii_dataout; + wire_n1iOOii_dataout <= wire_n1l1llO_dataout WHEN k_hip(0) = '1' ELSE nlOi1l0O; + wire_n1iOOiii_dataout <= wire_n1l1111i_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOlll_dataout; + wire_n1iOOiil_dataout <= wire_n1l1111l_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOllO_dataout; + wire_n1iOOiiO_dataout <= wire_n1l1111O_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOlOi_dataout; + wire_n1iOOil_dataout <= wire_n1l1lOi_dataout WHEN k_hip(0) = '1' ELSE nlOi1lii; + wire_n1iOOili_dataout <= wire_n1l1110i_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOlOl_dataout; + wire_n1iOOill_dataout <= wire_n1l1110l_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOlOO_dataout; + wire_n1iOOilO_dataout <= wire_n1l1110O_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOO1i_dataout; + wire_n1iOOiO_dataout <= wire_n1l1lOl_dataout WHEN k_hip(0) = '1' ELSE nlOi1lil; + wire_n1iOOiOi_dataout <= wire_n1l111ii_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOO1l_dataout; + wire_n1iOOiOl_dataout <= wire_n1l111il_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOO1O_dataout; + wire_n1iOOiOO_dataout <= wire_n1l111iO_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOO0i_dataout; + wire_n1iOOl0i_dataout <= wire_n1iOOOil_o(0) WHEN n1l110iO = '1' ELSE n1iOl1li; + wire_n1iOOl0l_dataout <= wire_n1iOOOil_o(1) WHEN n1l110iO = '1' ELSE n1iOl1ll; + wire_n1iOOl0O_dataout <= wire_n1iOOOil_o(2) WHEN n1l110iO = '1' ELSE n1iOl1lO; + wire_n1iOOl1i_dataout <= wire_n1l111li_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOO0l_dataout; + wire_n1iOOl1l_dataout <= wire_n1l111ll_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOO0O_dataout; + wire_n1iOOl1O_dataout <= wire_n1l111lO_dataout WHEN niOli10ll = '1' ELSE wire_n1iOOOii_dataout; + wire_n1iOOli_dataout <= wire_n1l1lOO_dataout WHEN k_hip(0) = '1' ELSE nlOi1liO; + wire_n1iOOlii_dataout <= wire_n1iOOOil_o(3) WHEN n1l110iO = '1' ELSE n1iOl1Oi; + wire_n1iOOlil_dataout <= wire_n1iOOOil_o(4) WHEN n1l110iO = '1' ELSE n1iOl1Ol; + wire_n1iOOliO_dataout <= wire_n1iOOOil_o(5) WHEN n1l110iO = '1' ELSE n1iOl1OO; + wire_n1iOOll_dataout <= wire_n1l1O1i_dataout WHEN k_hip(0) = '1' ELSE nlOi1lli; + wire_n1iOOlli_dataout <= wire_n1iOOOil_o(6) WHEN n1l110iO = '1' ELSE n1iOl01i; + wire_n1iOOlll_dataout <= wire_n1iOOOil_o(7) WHEN n1l110iO = '1' ELSE n1iOl01l; + wire_n1iOOllO_dataout <= wire_n1iOOOil_o(8) WHEN n1l110iO = '1' ELSE n1iOl01O; + wire_n1iOOlO_dataout <= wire_n1l1O1l_dataout WHEN k_hip(0) = '1' ELSE nlOi1lll; + wire_n1iOOlOi_dataout <= wire_n1iOOOil_o(9) WHEN n1l110iO = '1' ELSE n1iOl00i; + wire_n1iOOlOl_dataout <= wire_n1iOOOil_o(10) WHEN n1l110iO = '1' ELSE n1iOl00l; + wire_n1iOOlOO_dataout <= wire_n1iOOOil_o(11) WHEN n1l110iO = '1' ELSE n1iOl00O; + wire_n1iOOO0i_dataout <= wire_n1iOOOil_o(15) WHEN n1l110iO = '1' ELSE n1iOl0li; + wire_n1iOOO0l_dataout <= wire_n1iOOOil_o(16) WHEN n1l110iO = '1' ELSE n1iOl0ll; + wire_n1iOOO0O_dataout <= wire_n1iOOOil_o(17) WHEN n1l110iO = '1' ELSE n1iOl0lO; + wire_n1iOOO1i_dataout <= wire_n1iOOOil_o(12) WHEN n1l110iO = '1' ELSE n1iOl0ii; + wire_n1iOOO1l_dataout <= wire_n1iOOOil_o(13) WHEN n1l110iO = '1' ELSE n1iOl0il; + wire_n1iOOO1O_dataout <= wire_n1iOOOil_o(14) WHEN n1l110iO = '1' ELSE n1iOl0iO; + wire_n1iOOOi_dataout <= wire_n1l1O1O_dataout WHEN k_hip(0) = '1' ELSE nlOi1llO; + wire_n1iOOOii_dataout <= wire_n1iOOOil_o(18) WHEN n1l110iO = '1' ELSE n1iOl0Oi; + wire_n1iOOOiO_dataout <= n1iOl1li AND NOT(n1l110iO); + wire_n1iOOOl_dataout <= wire_n1l1O0i_dataout WHEN k_hip(0) = '1' ELSE nlOi1lOi; + wire_n1iOOOli_dataout <= n1iOl1ll AND NOT(n1l110iO); + wire_n1iOOOll_dataout <= n1iOl1lO AND NOT(n1l110iO); + wire_n1iOOOlO_dataout <= n1iOl1Oi AND NOT(n1l110iO); + wire_n1iOOOO_dataout <= wire_n1l1O0l_dataout WHEN k_hip(0) = '1' ELSE nlOi1lOl; + wire_n1iOOOOi_dataout <= n1iOl1Ol AND NOT(n1l110iO); + wire_n1iOOOOl_dataout <= n1iOl1OO AND NOT(n1l110iO); + wire_n1iOOOOO_dataout <= n1iOl01i AND NOT(n1l110iO); + wire_n1l00i0l_dataout <= wire_n1l00Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00i0O_dataout <= wire_n1lii0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00iii_dataout <= wire_n1lii0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00iil_dataout <= wire_n1l00OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00iiO_dataout <= wire_n1l00Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00ili_dataout <= wire_n1l00Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00ill_dataout <= wire_n1l0i0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00ilO_dataout <= wire_n1l0i0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00iO_dataout <= wire_n1l0l0l_dataout AND NOT(niOO00l1l); + wire_n1l00iOi_dataout <= wire_n1l0i0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00iOl_dataout <= wire_n1l0i0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00iOO_dataout <= wire_n1l0i0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00l0i_dataout <= wire_n1l0ii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00l0l_dataout <= n1l0001l AND NOT(wire_niO01lOO_dataout); + wire_n1l00l0O_dataout <= wire_n1lii01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00l1i_dataout <= wire_n1l0ii1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00l1l_dataout <= wire_n1l0ii1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00l1O_dataout <= wire_n1l0ii1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00li_dataout <= wire_n1l0l0O_dataout AND NOT(niOO00l1l); + wire_n1l00lii_dataout <= wire_n1liilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00lil_dataout <= wire_n1liiliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00liO_dataout <= wire_n1liil0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00ll_dataout <= wire_n1l0lii_dataout AND NOT(niOO00l1l); + wire_n1l00lli_dataout <= wire_n1liil1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00lll_dataout <= wire_n1liiilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00llO_dataout <= wire_n1liiiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00lO_dataout <= wire_n1l0lil_dataout OR niOO00l1l; + wire_n1l00lOi_dataout <= wire_n1liii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00lOl_dataout <= wire_n1lii0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00lOO_dataout <= wire_n1liiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00O0i_dataout <= wire_n1lil01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00O0l_dataout <= wire_n1lil01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00O0O_dataout <= wire_n1lil00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00O1i_dataout <= wire_n1liiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00O1l_dataout <= wire_n1liiO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00O1O_dataout <= wire_n1liiO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00Oi_dataout <= wire_n1liO0O_dataout AND NOT(niOO00l1l); + wire_n1l00Oii_dataout <= wire_n1lil00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l00Oil_dataout <= wire_n1l00OlO_dataout OR niOli1O0l; + wire_n1l00OiO_dataout <= wire_n1l00OOi_dataout AND NOT(niOli1O0l); + wire_n1l00Ol_dataout <= wire_n1l0l1O_dataout AND NOT(niOO00l1l); + wire_n1l00Oli_dataout <= wire_n1l00OOl_dataout AND NOT(niOli1O0l); + wire_n1l00Oll_dataout <= wire_n1l00OOO_dataout AND NOT(niOli1O0l); + wire_n1l00OlO_dataout <= wire_n1l0i11i_dataout AND NOT(niOli1O0i); + wire_n1l00OO_dataout <= wire_n1l0l0i_dataout AND NOT(niOO00l1l); + wire_n1l00OOi_dataout <= wire_n1l0i11l_dataout OR niOli1O0i; + wire_n1l00OOl_dataout <= wire_n1l0i11O_dataout OR niOli1O0i; + wire_n1l00OOO_dataout <= wire_n1l0i10i_dataout AND NOT(niOli1O0i); + wire_n1l0100i_dataout <= wire_n1l0100l_dataout OR (n1lilO0l AND (wire_niO01ill_w_lg_n1l1OlOi18773w(0) AND wire_n1l1Ol0O_dataout)); + wire_n1l0100l_dataout <= n1l1OlOi AND NOT(n1l1Olll); + wire_n1l0101i_dataout <= wire_n1l01lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l0101l_dataout <= wire_n1l01lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l0101O_dataout <= wire_n1l01lOO_dataout OR wire_niO01lOO_dataout; + wire_n1l010il_dataout <= wire_n1l01i0l_dataout WHEN niOli1lii = '1' ELSE wire_n1l010li_dataout; + wire_n1l010iO_dataout <= wire_n1l01i0O_dataout WHEN niOli1lii = '1' ELSE wire_n1l010ll_dataout; + wire_n1l010li_dataout <= wire_n1l01i1l_o(0) WHEN niOli1l0O = '1' ELSE wire_n1l010lO_dataout; + wire_n1l010ll_dataout <= wire_n1l01i1l_o(1) WHEN niOli1l0O = '1' ELSE wire_n1l010Oi_dataout; + wire_n1l010lO_dataout <= wire_n1l010Ol_o(1) WHEN niOli1l0l = '1' ELSE n1l1OO1i; + wire_n1l010Oi_dataout <= wire_n1l010Ol_o(2) WHEN niOli1l0l = '1' ELSE n1l1OO1l; + wire_n1l0110i_dataout <= wire_n1l01ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l0110l_dataout <= wire_n1l01ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l0110O_dataout <= wire_n1l010il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l0111i_dataout <= (n1lOi0ii OR n1lOi01O) AND NOT(wire_niO01lOO_dataout); + wire_n1l0111l_dataout <= wire_n1l01l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l0111O_dataout <= wire_n1l0100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l011ii_dataout <= wire_n1l010iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l011il_dataout <= wire_n1l01l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l011iO_dataout <= wire_n1l01l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l011li_dataout <= wire_n1l01lii_dataout OR wire_niO01lOO_dataout; + wire_n1l011ll_dataout <= wire_n1l01lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l011lO_dataout <= wire_n1l01liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l011Oi_dataout <= wire_n1l01lli_dataout OR wire_niO01lOO_dataout; + wire_n1l011Ol_dataout <= wire_n1l01lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l011OO_dataout <= wire_n1l01llO_dataout OR wire_niO01lOO_dataout; + wire_n1l01i0l_dataout <= wire_n1l01i1l_o(0) WHEN wire_w_lg_niOli0O1i19670w(0) = '1' ELSE n1l1OO1i; + wire_n1l01i0O_dataout <= wire_n1l01i1l_o(1) WHEN wire_w_lg_niOli0O1i19670w(0) = '1' ELSE wire_n1l01iii_o(0); + wire_n1l01ili_dataout <= wire_n1l01ilO_dataout OR niOli1lil; + wire_n1l01ill_dataout <= wire_n1l01iOi_dataout OR niOli1lil; + wire_n1l01ilO_dataout <= wire_n1l01iOl_dataout OR niOli1lll; + wire_n1l01iOi_dataout <= wire_n1l01iOO_dataout OR niOli1lll; + wire_n1l01iOl_dataout <= n1l1OlOl AND NOT(niOli1liO); + wire_n1l01iOO_dataout <= n1l1OlOO AND NOT(niOli1liO); + wire_n1l01l0i_dataout <= n1l1OllO AND NOT(niOli1lll); + wire_n1l01l0l_dataout <= wire_n1l01O1l_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(1); + wire_n1l01l0O_dataout <= wire_n1l01O1O_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(2); + wire_n1l01l1O_dataout <= wire_n1l01l0i_dataout OR n1110Oli; + wire_n1l01lii_dataout <= wire_n1l01O0i_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(3); + wire_n1l01lil_dataout <= wire_n1l01O0l_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(4); + wire_n1l01liO_dataout <= wire_n1l01O0O_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(5); + wire_n1l01lli_dataout <= wire_n1l01Oii_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(6); + wire_n1l01lll_dataout <= wire_n1l01Oil_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(7); + wire_n1l01llO_dataout <= wire_n1l01OiO_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(8); + wire_n1l01lOi_dataout <= wire_n1l01Oli_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(9); + wire_n1l01lOl_dataout <= wire_n1l01Oll_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(10); + wire_n1l01lOO_dataout <= wire_n1l01OlO_dataout WHEN niOli1lOi = '1' ELSE wire_n1l01O1i_o(11); + wire_n1l01O0i_dataout <= k_cnt(87) OR niOli1llO; + wire_n1l01O0l_dataout <= k_cnt(88) AND NOT(niOli1llO); + wire_n1l01O0O_dataout <= k_cnt(89) AND NOT(niOli1llO); + wire_n1l01O1l_dataout <= k_cnt(85) AND NOT(niOli1llO); + wire_n1l01O1O_dataout <= k_cnt(86) AND NOT(niOli1llO); + wire_n1l01Oii_dataout <= k_cnt(90) OR niOli1llO; + wire_n1l01Oil_dataout <= k_cnt(91) AND NOT(niOli1llO); + wire_n1l01OiO_dataout <= k_cnt(92) OR niOli1llO; + wire_n1l01Oli_dataout <= k_cnt(93) AND NOT(niOli1llO); + wire_n1l01Oll_dataout <= k_cnt(94) AND NOT(niOli1llO); + wire_n1l01OlO_dataout <= k_cnt(95) OR niOli1llO; + wire_n1l0i01i_dataout <= n1l0010O AND NOT(wire_w_lg_niOli0O1l19558w(0)); + wire_n1l0i0i_dataout <= wire_n1l0lll_dataout AND NOT(niOO00l1l); + wire_n1l0i0l_dataout <= wire_n1l0llO_dataout AND NOT(niOO00l1l); + wire_n1l0i0ll_dataout <= wire_n1l0ii0l_dataout AND NOT(niOli000l); + wire_n1l0i0lO_dataout <= wire_n1l0ii0O_dataout AND NOT(niOli000l); + wire_n1l0i0O_dataout <= wire_n1l0lOi_dataout AND NOT(niOO00l1l); + wire_n1l0i0Oi_dataout <= wire_n1l0iiii_dataout OR niOli000l; + wire_n1l0i0Ol_dataout <= wire_n1l0iiil_dataout OR niOli000l; + wire_n1l0i0OO_dataout <= wire_n1l0iiiO_dataout OR niOli000l; + wire_n1l0i10i_dataout <= wire_n1l0i1il_dataout OR niOli1O1O; + wire_n1l0i10l_dataout <= wire_n1l0i1iO_dataout AND NOT(niOli1O1l); + wire_n1l0i10O_dataout <= wire_niO01ill_w_lg_n110OOOl19590w(0) WHEN niOli1O1l = '1' ELSE wire_n1l0i1li_dataout; + wire_n1l0i11i_dataout <= wire_n1l0i10l_dataout AND NOT(niOli1O1O); + wire_n1l0i11l_dataout <= wire_n1l0i10O_dataout OR niOli1O1O; + wire_n1l0i11O_dataout <= wire_n1l0i1ii_dataout OR niOli1O1O; + wire_n1l0i1i_dataout <= wire_n1l0Oil_dataout AND NOT(niOO00l1l); + wire_n1l0i1ii_dataout <= wire_n1l0i1ll_dataout AND NOT(niOli1O1l); + wire_n1l0i1il_dataout <= wire_n1l0i1lO_dataout AND NOT(niOli1O1l); + wire_n1l0i1iO_dataout <= wire_n1l0i1Oi_dataout AND NOT(niOli1O1i); + wire_n1l0i1l_dataout <= wire_n1l0liO_dataout AND NOT(niOO00l1l); + wire_n1l0i1li_dataout <= wire_n1l0i1Ol_dataout AND NOT(niOli1O1i); + wire_n1l0i1ll_dataout <= wire_niO01ill_w_lg_n110OOOi19589w(0) WHEN niOli1O1i = '1' ELSE wire_n1l0i1OO_dataout; + wire_n1l0i1lO_dataout <= wire_n1l0i01i_dataout AND NOT(niOli1O1i); + wire_n1l0i1O_dataout <= wire_n1l0lli_dataout AND NOT(niOO00l1l); + wire_n1l0i1Oi_dataout <= n1l1OOOl AND NOT(wire_w_lg_niOli0O1l19558w(0)); + wire_n1l0i1Ol_dataout <= n1l0010i AND NOT(wire_w_lg_niOli0O1l19558w(0)); + wire_n1l0i1OO_dataout <= n1l0010l AND NOT(wire_w_lg_niOli0O1l19558w(0)); + wire_n1l0ii0i_dataout <= wire_n1l0iiOi_dataout OR niOli000l; + wire_n1l0ii0l_dataout <= wire_n1l0iiOl_dataout AND NOT(niOli001O); + wire_n1l0ii0O_dataout <= wire_n1l0iiOO_dataout AND NOT(niOli001O); + wire_n1l0ii1i_dataout <= wire_w_lg_niOli000i19580w(0) WHEN niOli000l = '1' ELSE wire_n1l0iili_dataout; + wire_n1l0ii1l_dataout <= wire_n1l0iill_dataout AND NOT(niOli000l); + wire_n1l0ii1O_dataout <= wire_w_lg_niOli000i19580w(0) WHEN niOli000l = '1' ELSE wire_n1l0iilO_dataout; + wire_n1l0iii_dataout <= wire_n1l0lOl_dataout AND NOT(niOO00l1l); + wire_n1l0iiii_dataout <= wire_n1l0il1i_dataout AND NOT(niOli001O); + wire_n1l0iiil_dataout <= wire_n1l0il1l_dataout AND NOT(niOli001O); + wire_n1l0iiiO_dataout <= wire_n1l0il1O_dataout AND NOT(niOli001O); + wire_n1l0iil_dataout <= wire_n1l0lOO_dataout AND NOT(niOO00l1l); + wire_n1l0iili_dataout <= wire_n1l0il0i_dataout AND NOT(niOli001O); + wire_n1l0iill_dataout <= wire_n1l0il0l_dataout AND NOT(niOli001O); + wire_n1l0iilO_dataout <= wire_n1l0il0O_dataout AND NOT(niOli001O); + wire_n1l0iiO_dataout <= wire_n1l0O1i_dataout AND NOT(niOO00l1l); + wire_n1l0iiOi_dataout <= wire_n1l0ilii_dataout AND NOT(niOli001O); + wire_n1l0iiOl_dataout <= wire_n1l0ilil_dataout AND NOT(niOli00ll); + wire_n1l0iiOO_dataout <= wire_n1l0iliO_dataout AND NOT(niOli00ll); + wire_n1l0il0i_dataout <= wire_n1l0ilOi_dataout OR niOli00ll; + wire_n1l0il0l_dataout <= wire_n1l0ilOl_dataout AND NOT(niOli00ll); + wire_n1l0il0O_dataout <= wire_n1l0ilOO_dataout OR niOli00ll; + wire_n1l0il1i_dataout <= wire_n1l0illi_dataout OR niOli00ll; + wire_n1l0il1l_dataout <= wire_n1l0illl_dataout OR niOli00ll; + wire_n1l0il1O_dataout <= wire_n1l0illO_dataout OR niOli00ll; + wire_n1l0ili_dataout <= wire_n1l0O1l_dataout AND NOT(niOO00l1l); + wire_n1l0ilii_dataout <= wire_n1l0iO1i_dataout OR niOli00ll; + wire_n1l0ilil_dataout <= wire_n1l0iO1l_dataout AND NOT(niOli001l); + wire_n1l0iliO_dataout <= wire_n1l0iO1O_dataout AND NOT(niOli001l); + wire_n1l0ill_dataout <= wire_n1l0O1O_dataout AND NOT(niOO00l1l); + wire_n1l0illi_dataout <= wire_n1l0iO0i_dataout OR niOli001l; + wire_n1l0illl_dataout <= wire_n1l0iO0l_dataout OR niOli001l; + wire_n1l0illO_dataout <= wire_n1l0iO0O_dataout OR niOli001l; + wire_n1l0ilO_dataout <= wire_n1l0Oii_dataout AND NOT(niOO00l1l); + wire_n1l0ilOi_dataout <= wire_n1l0iOii_dataout OR niOli001l; + wire_n1l0ilOl_dataout <= wire_n1l0iOil_dataout OR niOli001l; + wire_n1l0ilOO_dataout <= wire_n1l0iOiO_dataout OR niOli001l; + wire_n1l0iO0i_dataout <= wire_n1l0iOOi_dataout OR niOli001i; + wire_n1l0iO0l_dataout <= wire_n1l0iOOl_dataout OR niOli001i; + wire_n1l0iO0O_dataout <= wire_n1l0iOOO_dataout OR niOli001i; + wire_n1l0iO1i_dataout <= wire_n1l0iOli_dataout OR niOli001l; + wire_n1l0iO1l_dataout <= wire_n1l0iOll_dataout AND NOT(niOli001i); + wire_n1l0iO1O_dataout <= wire_n1l0iOlO_dataout AND NOT(niOli001i); + wire_n1l0iOi_dataout <= wire_n1l0O0O_dataout AND NOT(niOO00l1l); + wire_n1l0iOii_dataout <= wire_n1l0l11i_dataout OR niOli001i; + wire_n1l0iOil_dataout <= wire_n1l0l11l_dataout AND NOT(niOli001i); + wire_n1l0iOiO_dataout <= wire_n1l0l11O_dataout OR niOli001i; + wire_n1l0iOl_dataout <= wire_n1l0l1l_dataout AND NOT(niOO00l1l); + wire_n1l0iOli_dataout <= wire_n1l0l10i_dataout OR niOli001i; + wire_n1l0iOll_dataout <= wire_n1l0l10l_dataout AND NOT(niOli01Ol); + wire_n1l0iOlO_dataout <= wire_n1l0l10O_dataout AND NOT(niOli01Ol); + wire_n1l0iOO_dataout <= wire_n1l0O0i_dataout AND NOT(niOO00l1l); + wire_n1l0iOOi_dataout <= wire_n1l0l1ii_dataout OR niOli01Ol; + wire_n1l0iOOl_dataout <= wire_n1l0l1il_dataout OR niOli01Ol; + wire_n1l0iOOO_dataout <= wire_n1l0l1iO_dataout OR niOli01Ol; + wire_n1l0l00i_dataout <= wire_n1l0l0Oi_dataout OR n1lilllO; + wire_n1l0l00l_dataout <= wire_w_lg_niOli1O0O19579w(0) WHEN n1lilllO = '1' ELSE wire_n1l0l0Ol_dataout; + wire_n1l0l00O_dataout <= niOli1O0O WHEN n1lilllO = '1' ELSE wire_n1l0l0OO_dataout; + wire_n1l0l01i_dataout <= wire_n1l0l0li_dataout OR n1lilllO; + wire_n1l0l01l_dataout <= wire_n1l0l0ll_dataout OR n1lilllO; + wire_n1l0l01O_dataout <= wire_n1l0l0lO_dataout OR n1lilllO; + wire_n1l0l0i_dataout <= wire_n1l0OlO_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l010O; + wire_n1l0l0ii_dataout <= wire_n1l0li1i_dataout OR n1lilllO; + wire_n1l0l0il_dataout <= wire_n1l0li1l_dataout AND NOT(n1lillll); + wire_n1l0l0iO_dataout <= niOli0ill WHEN n1lillll = '1' ELSE wire_n1l0li1O_dataout; + wire_n1l0l0l_dataout <= wire_n1l0OOi_o WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE nlOiliii; + wire_n1l0l0li_dataout <= wire_w_lg_niOli0ill19512w(0) WHEN n1lillll = '1' ELSE wire_n1l0li0i_dataout; + wire_n1l0l0ll_dataout <= wire_n1l0li0l_dataout OR n1lillll; + wire_n1l0l0lO_dataout <= wire_w_lg_niOli0ill19512w(0) WHEN n1lillll = '1' ELSE wire_n1l0li0O_dataout; + wire_n1l0l0O_dataout <= wire_n1l0OOl_o WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l011i; + wire_n1l0l0Oi_dataout <= wire_w_lg_niOli0ill19512w(0) WHEN n1lillll = '1' ELSE wire_n1l0liii_dataout; + wire_n1l0l0Ol_dataout <= wire_n1l0liil_dataout OR n1lillll; + wire_n1l0l0OO_dataout <= wire_w_lg_niOli0ill19512w(0) WHEN n1lillll = '1' ELSE wire_n1l0liiO_dataout; + wire_n1l0l10i_dataout <= wire_n1l0l1Oi_dataout OR niOli01Ol; + wire_n1l0l10l_dataout <= wire_n1li0Oll_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l1Ol_dataout; + wire_n1l0l10O_dataout <= wire_n1li0OlO_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l1OO_dataout; + wire_n1l0l11i_dataout <= wire_n1l0l1li_dataout OR niOli01Ol; + wire_n1l0l11l_dataout <= wire_n1l0l1ll_dataout AND NOT(niOli01Ol); + wire_n1l0l11O_dataout <= wire_n1l0l1lO_dataout OR niOli01Ol; + wire_n1l0l1i_dataout <= wire_n1l0O0l_dataout AND NOT(niOO00l1l); + wire_n1l0l1ii_dataout <= wire_n1li0OOi_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l01i_dataout; + wire_n1l0l1il_dataout <= wire_n1li0OOl_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l01l_dataout; + wire_n1l0l1iO_dataout <= wire_n1li0OOO_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l01O_dataout; + wire_n1l0l1l_dataout <= wire_n1l0OiO_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l000l; + wire_n1l0l1li_dataout <= wire_n1lii11i_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l00i_dataout; + wire_n1l0l1ll_dataout <= wire_n1lii11l_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l00l_dataout; + wire_n1l0l1lO_dataout <= wire_n1lii11O_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l00O_dataout; + wire_n1l0l1O_dataout <= wire_n1l0Oli_o WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l010l; + wire_n1l0l1Oi_dataout <= wire_n1lii10i_dataout WHEN n1lilO0i = '1' ELSE wire_n1l0l0ii_dataout; + wire_n1l0l1Ol_dataout <= wire_n1l0l0il_dataout AND NOT(n1lilllO); + wire_n1l0l1OO_dataout <= wire_n1l0l0iO_dataout AND NOT(n1lilllO); + wire_n1l0li0i_dataout <= wire_n1l0liOi_dataout OR n1lilOil; + wire_n1l0li0l_dataout <= wire_n1l0liOl_dataout OR n1lilOil; + wire_n1l0li0O_dataout <= wire_n1l0liOO_dataout OR n1lilOil; + wire_n1l0li1i_dataout <= wire_w_lg_niOli0ill19512w(0) WHEN n1lillll = '1' ELSE wire_n1l0lili_dataout; + wire_n1l0li1l_dataout <= wire_n1l0lill_dataout AND NOT(n1lilOil); + wire_n1l0li1O_dataout <= wire_n1l0lilO_dataout AND NOT(n1lilOil); + wire_n1l0lii_dataout <= wire_n1l0OOO_o WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l011l; + wire_n1l0liii_dataout <= wire_n1l0ll1i_dataout OR n1lilOil; + wire_n1l0liil_dataout <= wire_n1l0ll1l_dataout OR n1lilOil; + wire_n1l0liiO_dataout <= wire_n1l0ll1O_dataout OR n1lilOil; + wire_n1l0lil_dataout <= wire_n1li11i_o WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l011O; + wire_n1l0lili_dataout <= wire_n1l0ll0i_dataout OR n1lilOil; + wire_n1l0lill_dataout <= wire_n1li0i0l_dataout WHEN n1lillli = '1' ELSE wire_n1l0ll0l_dataout; + wire_n1l0lilO_dataout <= wire_n1li0i0O_dataout WHEN n1lillli = '1' ELSE wire_n1l0ll0O_dataout; + wire_n1l0liO_dataout <= wire_n1li11l_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01il; + wire_n1l0liOi_dataout <= wire_n1li0iii_dataout WHEN n1lillli = '1' ELSE wire_n1l0llii_dataout; + wire_n1l0liOl_dataout <= wire_n1li0iil_dataout WHEN n1lillli = '1' ELSE wire_n1l0llil_dataout; + wire_n1l0liOO_dataout <= wire_n1li0iiO_dataout WHEN n1lillli = '1' ELSE wire_n1l0lliO_dataout; + wire_n1l0ll0i_dataout <= wire_n1li0iOi_dataout WHEN n1lillli = '1' ELSE wire_n1l0llOi_dataout; + wire_n1l0ll0l_dataout <= niOli01il WHEN n1lilliO = '1' ELSE wire_n1l0llOl_dataout; + wire_n1l0ll0O_dataout <= wire_n1li0i1l_dataout WHEN n1lilliO = '1' ELSE wire_n1l0llOO_dataout; + wire_n1l0ll1i_dataout <= wire_n1li0ili_dataout WHEN n1lillli = '1' ELSE wire_n1l0llli_dataout; + wire_n1l0ll1l_dataout <= wire_n1li0ill_dataout WHEN n1lillli = '1' ELSE wire_n1l0llll_dataout; + wire_n1l0ll1O_dataout <= wire_n1li0ilO_dataout WHEN n1lillli = '1' ELSE wire_n1l0lllO_dataout; + wire_n1l0lli_dataout <= wire_n1li11O_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01iO; + wire_n1l0llii_dataout <= wire_n1li0i1O_dataout WHEN n1lilliO = '1' ELSE wire_n1l0lO1i_dataout; + wire_n1l0llil_dataout <= wire_w_lg_niOli01il19578w(0) WHEN n1lilliO = '1' ELSE wire_n1l0lO1l_dataout; + wire_n1l0lliO_dataout <= wire_n1li0i1O_dataout WHEN n1lilliO = '1' ELSE wire_n1l0lO1O_dataout; + wire_n1l0lll_dataout <= wire_n1li10i_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01li; + wire_n1l0llli_dataout <= wire_n1li0i1O_dataout WHEN n1lilliO = '1' ELSE wire_n1l0lO0i_dataout; + wire_n1l0llll_dataout <= wire_n1li0i1l_dataout WHEN n1lilliO = '1' ELSE wire_n1l0lO0l_dataout; + wire_n1l0lllO_dataout <= wire_n1li0i1O_dataout WHEN n1lilliO = '1' ELSE wire_n1l0lO0O_dataout; + wire_n1l0llO_dataout <= wire_n1li10l_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01ll; + wire_n1l0llOi_dataout <= wire_n1li0i0i_dataout WHEN n1lilliO = '1' ELSE wire_n1l0lOii_dataout; + wire_n1l0llOl_dataout <= wire_n1l0lOil_dataout AND NOT(n1lillOl); + wire_n1l0llOO_dataout <= wire_n1l0lOiO_dataout AND NOT(n1lillOl); + wire_n1l0lO0i_dataout <= wire_n1l0lOOi_dataout AND NOT(n1lillOl); + wire_n1l0lO0l_dataout <= wire_n1l0lOOl_dataout AND NOT(n1lillOl); + wire_n1l0lO0O_dataout <= wire_n1l0lOOO_dataout AND NOT(n1lillOl); + wire_n1l0lO1i_dataout <= wire_n1l0lOli_dataout OR n1lillOl; + wire_n1l0lO1l_dataout <= wire_n1l0lOll_dataout OR n1lillOl; + wire_n1l0lO1O_dataout <= wire_n1l0lOlO_dataout OR n1lillOl; + wire_n1l0lOi_dataout <= wire_n1li10O_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01lO; + wire_n1l0lOii_dataout <= wire_n1l0O11i_dataout OR n1lillOl; + wire_n1l0lOil_dataout <= niOli0l0l WHEN n1lillOO = '1' ELSE wire_n1l0O11l_dataout; + wire_n1l0lOiO_dataout <= wire_n1l0O11O_dataout AND NOT(n1lillOO); + wire_n1l0lOl_dataout <= wire_n1li1ii_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01Oi; + wire_n1l0lOli_dataout <= wire_n1li00Oi_dataout WHEN n1lillOO = '1' ELSE wire_n1l0O10i_dataout; + wire_n1l0lOll_dataout <= wire_n1li00lO_dataout WHEN n1lillOO = '1' ELSE wire_n1l0O10l_dataout; + wire_n1l0lOlO_dataout <= wire_n1li00Oi_dataout WHEN n1lillOO = '1' ELSE wire_n1l0O10O_dataout; + wire_n1l0lOO_dataout <= wire_n1li1il_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01Ol; + wire_n1l0lOOi_dataout <= wire_n1li00Oi_dataout WHEN n1lillOO = '1' ELSE wire_n1l0O1ii_dataout; + wire_n1l0lOOl_dataout <= wire_n1li00Ol_dataout WHEN n1lillOO = '1' ELSE wire_n1l0O1il_dataout; + wire_n1l0lOOO_dataout <= niOli0l0l WHEN n1lillOO = '1' ELSE wire_n1l0O1iO_dataout; + wire_n1l0O00i_dataout <= wire_n1l0O0Oi_dataout AND n1lilO1O; + wire_n1l0O00l_dataout <= wire_n1l0O0Ol_dataout OR niOli1Oii; + wire_n1l0O00O_dataout <= wire_n1l0O0OO_dataout OR niOli1Oii; + wire_n1l0O01i_dataout <= wire_n1l0O0li_dataout AND n1lilO1O; + wire_n1l0O01l_dataout <= wire_n1l0O0ll_dataout AND n1lilO1O; + wire_n1l0O01O_dataout <= wire_n1l0O0lO_dataout AND n1lilO1O; + wire_n1l0O0i_dataout <= wire_n1li1lO_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l000O; + wire_n1l0O0ii_dataout <= wire_n1l0Oi1i_dataout OR niOli1Oii; + wire_n1l0O0il_dataout <= wire_n1l0Oi1l_dataout AND NOT(niOli1Oii); + wire_n1l0O0iO_dataout <= wire_n1l0Oi1O_dataout OR niOli1Oii; + wire_n1l0O0l_dataout <= wire_n1li1Oi_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l00ii; + wire_n1l0O0li_dataout <= wire_n1l0Oi0i_dataout OR niOli1Oii; + wire_n1l0O0ll_dataout <= wire_n1l0Oi0l_dataout OR niOli1Oii; + wire_n1l0O0lO_dataout <= wire_n1l0Oi0O_dataout OR niOli1Oii; + wire_n1l0O0O_dataout <= wire_n1liOli_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l000i; + wire_n1l0O0Oi_dataout <= wire_n1l0Oiii_dataout OR niOli1Oii; + wire_n1l0O0Ol_dataout <= wire_niilliOl_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0Oiil_dataout; + wire_n1l0O0OO_dataout <= wire_niilliOO_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0OiiO_dataout; + wire_n1l0O10i_dataout <= wire_n1li1lli_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O1Oi_dataout; + wire_n1l0O10l_dataout <= wire_n1li1lll_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O1Ol_dataout; + wire_n1l0O10O_dataout <= wire_n1li1llO_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O1OO_dataout; + wire_n1l0O11i_dataout <= wire_n1li00lO_dataout WHEN n1lillOO = '1' ELSE wire_n1l0O1li_dataout; + wire_n1l0O11l_dataout <= wire_n1li1lil_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O1ll_dataout; + wire_n1l0O11O_dataout <= wire_n1li1liO_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O1lO_dataout; + wire_n1l0O1i_dataout <= wire_n1li1iO_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01OO; + wire_n1l0O1ii_dataout <= wire_n1li1lOi_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O01i_dataout; + wire_n1l0O1il_dataout <= wire_n1li1lOl_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O01l_dataout; + wire_n1l0O1iO_dataout <= wire_n1li1lOO_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O01O_dataout; + wire_n1l0O1l_dataout <= wire_n1li1li_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l001i; + wire_n1l0O1li_dataout <= wire_n1li1O1i_dataout WHEN n1lillOi = '1' ELSE wire_n1l0O00i_dataout; + wire_n1l0O1ll_dataout <= wire_n1l0O00l_dataout AND n1lilO1O; + wire_n1l0O1lO_dataout <= wire_n1l0O00O_dataout AND n1lilO1O; + wire_n1l0O1O_dataout <= wire_n1li1ll_dataout WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l001l; + wire_n1l0O1Oi_dataout <= wire_n1l0O0ii_dataout AND n1lilO1O; + wire_n1l0O1Ol_dataout <= wire_n1l0O0il_dataout AND n1lilO1O; + wire_n1l0O1OO_dataout <= wire_n1l0O0iO_dataout AND n1lilO1O; + wire_n1l0Oi0i_dataout <= wire_niilll0i_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0OiOi_dataout; + wire_n1l0Oi0l_dataout <= wire_niilll0l_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0OiOl_dataout; + wire_n1l0Oi0O_dataout <= wire_niilll0O_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0OiOO_dataout; + wire_n1l0Oi1i_dataout <= wire_niilll1i_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0Oili_dataout; + wire_n1l0Oi1l_dataout <= wire_niilll1l_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0Oill_dataout; + wire_n1l0Oi1O_dataout <= wire_niilll1O_dataout WHEN niOli0l1i = '1' ELSE wire_n1l0OilO_dataout; + wire_n1l0Oii_dataout <= niOO00lil WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l001O; + wire_n1l0Oiii_dataout <= wire_n1l0Ol1i_dataout AND NOT(niOli0l1i); + wire_n1l0Oiil_dataout <= wire_n1l0Ol1l_dataout AND NOT(niOli1Oil); + wire_n1l0OiiO_dataout <= n1lililO WHEN niOli1Oil = '1' ELSE wire_n1l0Ol1O_dataout; + wire_n1l0Oil_dataout <= wire_nlll0lli_q(128) WHEN wire_w_lg_niOO00llO4046w(0) = '1' ELSE n1l01ii; + wire_n1l0Oili_dataout <= n1liliOi WHEN niOli1Oil = '1' ELSE wire_n1l0Ol0i_dataout; + wire_n1l0Oill_dataout <= n1liliOl WHEN niOli1Oil = '1' ELSE wire_n1l0Ol0l_dataout; + wire_n1l0OilO_dataout <= wire_n1l0Ol0O_dataout AND NOT(niOli1Oil); + wire_n1l0OiO_dataout <= wire_n1lil1i_dataout WHEN n1l011l = '1' ELSE n1l000l; + wire_n1l0OiOi_dataout <= wire_n1l0Olii_dataout AND NOT(niOli1Oil); + wire_n1l0OiOl_dataout <= n1lili0l WHEN niOli1Oil = '1' ELSE wire_n1l0Olil_dataout; + wire_n1l0OiOO_dataout <= n1liliOO WHEN niOli1Oil = '1' ELSE wire_n1l0OliO_dataout; + wire_n1l0Ol0i_dataout <= n11O1O0i WHEN niOli1Oli = '1' ELSE wire_n1l0OlOi_dataout; + wire_n1l0Ol0l_dataout <= wire_n1l10l0l_dataout WHEN niOli1Oli = '1' ELSE wire_n1l0OlOl_dataout; + wire_n1l0Ol0O_dataout <= niOO0Oi0l WHEN niOli1Oli = '1' ELSE wire_n1l0OlOO_dataout; + wire_n1l0Ol1i_dataout <= wire_n1l0Olli_dataout AND NOT(niOli1Oil); + wire_n1l0Ol1l_dataout <= (n11O0l1O OR (niOli1OiO AND n11O0liO)) WHEN niOli1Oli = '1' ELSE wire_n1l0Olll_dataout; + wire_n1l0Ol1O_dataout <= (n11O0lii OR ((wire_nlOii0l0O_dataout AND n11O0liO) OR (wire_nlOii0l0O_dataout AND n11O0O1O))) WHEN niOli1Oli = '1' ELSE wire_n1l0OllO_dataout; + wire_n1l0Olii_dataout <= wire_n1l0OO1i_dataout AND NOT(niOli1Oli); + wire_n1l0Olil_dataout <= wire_n1l0OO1l_dataout AND NOT(niOli1Oli); + wire_n1l0OliO_dataout <= wire_n1l0OO1O_dataout AND NOT(niOli1Oli); + wire_n1l0Olli_dataout <= wire_n1l0OO0i_dataout AND NOT(niOli1Oli); + wire_n1l0Olll_dataout <= wire_n1l0OO0l_dataout WHEN niOli1Oll = '1' ELSE n1l001ii; + wire_n1l0OllO_dataout <= wire_n1l0OO0O_dataout WHEN niOli1Oll = '1' ELSE n1l001il; + wire_n1l0OlO_dataout <= wire_n1lil1O_dataout WHEN n1l011O = '1' ELSE n1l010O; + wire_n1l0OlOi_dataout <= wire_n1l0OOii_dataout WHEN niOli1Oll = '1' ELSE n1l001iO; + wire_n1l0OlOl_dataout <= wire_n1l0OOil_dataout WHEN niOli1Oll = '1' ELSE n1l001li; + wire_n1l0OlOO_dataout <= wire_n1l0OOiO_dataout WHEN niOli1Oll = '1' ELSE n1l001ll; + wire_n1l0OO0i_dataout <= wire_n1l0OOOi_dataout WHEN niOli1Oll = '1' ELSE n1l001OO; + wire_n1l0OO0l_dataout <= wire_n1li10ll_dataout WHEN niOli0lli = '1' ELSE wire_n1l0OOOl_dataout; + wire_n1l0OO0O_dataout <= wire_n1li10lO_dataout WHEN niOli0lli = '1' ELSE wire_n1l0OOOO_dataout; + wire_n1l0OO1i_dataout <= wire_n1l0OOli_dataout WHEN niOli1Oll = '1' ELSE n1l001lO; + wire_n1l0OO1l_dataout <= wire_n1l0OOll_dataout WHEN niOli1Oll = '1' ELSE n1l001Oi; + wire_n1l0OO1O_dataout <= wire_n1l0OOlO_dataout WHEN niOli1Oll = '1' ELSE n1l001Ol; + wire_n1l0OOii_dataout <= wire_n1li10Oi_dataout WHEN niOli0lli = '1' ELSE wire_n1li111i_dataout; + wire_n1l0OOil_dataout <= wire_n1li10Ol_dataout WHEN niOli0lli = '1' ELSE wire_n1li111l_dataout; + wire_n1l0OOiO_dataout <= wire_n1li10OO_dataout WHEN niOli0lli = '1' ELSE wire_n1li111O_dataout; + wire_n1l0OOli_dataout <= wire_n1li1i1i_dataout WHEN niOli0lli = '1' ELSE wire_n1li110i_dataout; + wire_n1l0OOll_dataout <= wire_n1li1i1l_dataout WHEN niOli0lli = '1' ELSE wire_n1li110l_dataout; + wire_n1l0OOlO_dataout <= wire_n1li1i1O_dataout WHEN niOli0lli = '1' ELSE wire_n1li110O_dataout; + wire_n1l0OOOi_dataout <= wire_n1li1i0i_dataout WHEN niOli0lli = '1' ELSE wire_n1li11ii_dataout; + wire_n1l0OOOl_dataout <= wire_n1li11il_dataout AND NOT(niOli1OlO); + wire_n1l0OOOO_dataout <= wire_n1li11iO_dataout OR niOli1OlO; + wire_n1l100i_dataout <= wire_nlll0lli_q(44) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(12); + wire_n1l100l_dataout <= wire_nlll0lli_q(45) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(13); + wire_n1l100O_dataout <= wire_nlll0lli_q(46) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(14); + wire_n1l1010i_dataout <= n11O0l0O OR niOli1ili; + wire_n1l1010l_dataout <= wire_n1l101ii_dataout OR niOli1ili; + wire_n1l1010O_dataout <= n11O0l0O AND NOT(niOli1ili); + wire_n1l1011i_dataout <= wire_n1l1010i_dataout OR n11O0O0i; + wire_n1l1011l_dataout <= wire_n1l1010l_dataout AND NOT(n11O0O0i); + wire_n1l1011O_dataout <= wire_n1l1010O_dataout OR n11O0O0i; + wire_n1l101i_dataout <= wire_nlll0lli_q(41) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(9); + wire_n1l101ii_dataout <= n11O0O1O OR n11O0l0O; + wire_n1l101l_dataout <= wire_nlll0lli_q(42) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(10); + wire_n1l101O_dataout <= wire_nlll0lli_q(43) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(11); + wire_n1l10ii_dataout <= wire_nlll0lli_q(47) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(15); + wire_n1l10il_dataout <= wire_nlll0lli_q(48) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(16); + wire_n1l10ili_dataout <= wire_n1l10ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l10ill_dataout <= wire_n1l10ilO_dataout OR niOli1iOl; + wire_n1l10ilO_dataout <= wire_niO01ill_w_lg_n1l110iO20000w(0) WHEN niOli1iOO = '1' ELSE n1l110iO; + wire_n1l10iO_dataout <= wire_nlll0lli_q(49) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(17); + wire_n1l10l0l_dataout <= niOO0Oi1i AND (((wire_niO01ill_w_lg_w_lg_niOO0O0OO19990w19991w(0) AND wire_niO01ill_w_lg_n11O0lii19984w(0)) AND wire_niO01ill_w_lg_n11O0l1O19986w(0)) AND wire_niO01ill_w_lg_n1l10iiO19988w(0)); + wire_n1l10l1i_dataout <= wire_n1l10l1l_dataout AND NOT((wire_w_lg_niOli1l1O19995w(0) OR wire_niO01lOO_dataout)); + wire_n1l10l1l_dataout <= wire_n1l10l1O_dataout OR wire_nlOi0lOil_dataout; + wire_n1l10l1O_dataout <= n1l10iiO AND NOT(n11O0l1O); + wire_n1l10li_dataout <= wire_nlll0lli_q(50) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(18); + wire_n1l10ll_dataout <= wire_nlll0lli_q(51) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(19); + wire_n1l10lli_dataout <= niOO0O0OO AND ((wire_niO01ill_w_lg_w_lg_n11O0lii19984w19985w(0) AND wire_niO01ill_w_lg_n11O0l1O19986w(0)) AND wire_niO01ill_w_lg_n1l10iiO19988w(0)); + wire_n1l10lli_w_lg_dataout21212w(0) <= NOT wire_n1l10lli_dataout; + wire_n1l10lO_dataout <= wire_nlll0lli_q(52) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(20); + wire_n1l10lOl_dataout <= n1iO0l0O AND wire_niO01ill_w_lg_n11Oi10O19980w(0); + wire_n1l10lOO_dataout <= wire_n1l10O1O_dataout AND NOT(nlOll0Oii); + wire_n1l10O0i_dataout <= wire_n1l10Oii_dataout AND NOT(nlOll0O0O); + wire_n1l10O0l_dataout <= wire_n1l10Oil_dataout AND NOT(nlOll0O0O); + wire_n1l10O0O_dataout <= nlOll0O0i AND NOT(nlOll0O0l); + wire_n1l10O1i_dataout <= wire_n1l10O0i_dataout AND NOT(nlOll0Oii); + wire_n1l10O1l_dataout <= wire_n1l10O0l_dataout AND NOT(nlOll0Oii); + wire_n1l10O1O_dataout <= wire_n1l10O0O_dataout OR nlOll0O0O; + wire_n1l10Oi_dataout <= wire_nlll0lli_q(53) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(21); + wire_n1l10Oii_dataout <= nlOll0O0i OR nlOll0O0l; + wire_n1l10Oil_dataout <= wire_niO01ill_w_lg_nlOll0O0i19983w(0) AND NOT(nlOll0O0l); + wire_n1l10OiO_dataout <= wire_n1l10Oll_dataout AND NOT(nlOllllii); + wire_n1l10Ol_dataout <= wire_nlll0lli_q(54) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(22); + wire_n1l10Oli_dataout <= wire_niO01ill_w_lg_nlOllll0O19982w(0) AND NOT(nlOllllii); + wire_n1l10Oll_dataout <= wire_niO01ill_w_lg_nlOllll0l19981w(0) OR nlOllll0O; + wire_n1l10OlO_dataout <= wire_n1l1i11l_dataout AND NOT(n11Oi00O); + wire_n1l10OO_dataout <= wire_nlll0lli_q(55) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(23); + wire_n1l10OOi_dataout <= wire_n1l1i11O_dataout AND NOT(n11Oi00O); + wire_n1l10OOl_dataout <= wire_n1l1i10i_dataout AND NOT(n11Oi00O); + wire_n1l10OOO_dataout <= wire_n1l1i10l_dataout AND NOT(n11Oi00O); + wire_n1l110i_dataout <= wire_n1l1OiO_dataout WHEN k_hip(0) = '1' ELSE nlOi1O1O; + wire_n1l110l_dataout <= wire_n1l1Oli_dataout WHEN k_hip(0) = '1' ELSE nlOi1O0i; + wire_n1l110li_dataout <= (niOli1i1i AND n1Oi1O0i) AND NOT(wire_niO01lOO_dataout); + wire_n1l110ll_dataout <= (niOli1i1l AND n011liil) AND NOT(wire_niO01lOO_dataout); + wire_n1l110lO_dataout <= (niOli1i1O AND n01O01lO) AND NOT(wire_niO01lOO_dataout); + wire_n1l110O_dataout <= wire_nlll0lli_q(132) WHEN k_hip(0) = '1' ELSE nlOi1O0l; + wire_n1l110Oi_dataout <= (niOli1i0i AND n00ilO1i) AND NOT(wire_niO01lOO_dataout); + wire_n1l110Ol_dataout <= (niOli1i0l AND n0i00i0l) AND NOT(wire_niO01lOO_dataout); + wire_n1l110OO_dataout <= (niOli1i0O AND n0iOO1iO) AND NOT(wire_niO01lOO_dataout); + wire_n1l1110i_dataout <= n1iOl00l AND NOT(n1l110iO); + wire_n1l1110l_dataout <= n1iOl00O AND NOT(n1l110iO); + wire_n1l1110O_dataout <= n1iOl0ii AND NOT(n1l110iO); + wire_n1l1111i_dataout <= n1iOl01l AND NOT(n1l110iO); + wire_n1l1111l_dataout <= n1iOl01O AND NOT(n1l110iO); + wire_n1l1111O_dataout <= n1iOl00i AND NOT(n1l110iO); + wire_n1l111i_dataout <= wire_n1l1O0O_dataout WHEN k_hip(0) = '1' ELSE nlOi1lOO; + wire_n1l111ii_dataout <= n1iOl0il AND NOT(n1l110iO); + wire_n1l111il_dataout <= n1iOl0iO AND NOT(n1l110iO); + wire_n1l111iO_dataout <= n1iOl0li AND NOT(n1l110iO); + wire_n1l111l_dataout <= wire_n1l1Oii_dataout WHEN k_hip(0) = '1' ELSE nlOi1O1i; + wire_n1l111li_dataout <= n1iOl0ll AND NOT(n1l110iO); + wire_n1l111ll_dataout <= n1iOl0lO AND NOT(n1l110iO); + wire_n1l111lO_dataout <= n1iOl0Oi AND NOT(n1l110iO); + wire_n1l111O_dataout <= wire_n1l1Oil_dataout WHEN k_hip(0) = '1' ELSE nlOi1O1l; + wire_n1l11i0i_dataout <= wire_n1l11i0l_dataout AND n11O0l1O; + wire_n1l11i0l_dataout <= wire_w_lg_niOli1iiO20055w(0) WHEN niOO10lOO = '1' ELSE wire_n1l11i0O_dataout; + wire_n1l11i0O_dataout <= n1iOl0Ol OR NOT(niOli1iiO); + wire_n1l11i1i_dataout <= (niOli1iii AND n0ll0lOi) AND NOT(wire_niO01lOO_dataout); + wire_n1l11i1l_dataout <= (niOli1iil AND n0O0Oi1l) AND NOT(wire_niO01lOO_dataout); + wire_n1l11i1O_dataout <= wire_n1l11i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l11ii_dataout <= wire_nlll0lli_q(32) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(0); + wire_n1l11il_dataout <= wire_nlll0lli_q(33) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(1); + wire_n1l11iO_dataout <= wire_nlll0lli_q(34) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(2); + wire_n1l11iOO_dataout <= wire_n1l11l0l_dataout AND NOT(niOli1ilO); + wire_n1l11iOO_w_lg_w_lg_dataout25218w25219w(0) <= NOT wire_n1l11iOO_w_lg_dataout25218w(0); + wire_n1l11iOO_w_lg_dataout25218w(0) <= wire_n1l11iOO_dataout XOR n1iOl10l; + wire_n1l11l0i_dataout <= wire_n1l11liO_dataout AND NOT(niOli1ilO); + wire_n1l11l0l_dataout <= wire_n1l11lli_dataout OR niOli1iOi; + wire_n1l11l0O_dataout <= wire_n1l11lli_dataout AND NOT(niOli1iOi); + wire_n1l11l1i_dataout <= wire_n1l11l0O_dataout AND NOT(niOli1ilO); + wire_n1l11l1l_dataout <= wire_n1l11lii_dataout AND NOT(niOli1ilO); + wire_n1l11l1O_dataout <= wire_n1l11lil_dataout AND NOT(niOli1ilO); + wire_n1l11li_dataout <= wire_nlll0lli_q(35) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(3); + wire_n1l11lii_dataout <= wire_n1l11lll_dataout OR niOli1iOi; + wire_n1l11lil_dataout <= wire_n1l11llO_dataout AND NOT(niOli1iOi); + wire_n1l11liO_dataout <= wire_n1l11lOi_dataout AND NOT(niOli1iOi); + wire_n1l11ll_dataout <= wire_nlll0lli_q(36) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(4); + wire_n1l11lli_dataout <= wire_n1l11lOl_dataout OR niOli1ill; + wire_n1l11lll_dataout <= wire_n1l11lOO_dataout AND NOT(niOli1ill); + wire_n1l11llO_dataout <= wire_n1l11O1i_dataout AND NOT(niOli1ill); + wire_n1l11lO_dataout <= wire_nlll0lli_q(37) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(5); + wire_n1l11lOi_dataout <= wire_n1l11O1l_dataout AND NOT(niOli1ill); + wire_n1l11lOl_dataout <= wire_n1l11O1O_dataout OR n11O0O0O; + wire_n1l11lOO_dataout <= wire_n1l11O0i_dataout AND NOT(n11O0O0O); + wire_n1l11O0i_dataout <= wire_n1l11Oil_dataout AND NOT(n11O0llO); + wire_n1l11O0l_dataout <= wire_n1l11OiO_dataout OR n11O0llO; + wire_n1l11O0O_dataout <= wire_n1l11Oli_dataout AND NOT(n11O0llO); + wire_n1l11O1i_dataout <= wire_n1l11O0l_dataout OR n11O0O0O; + wire_n1l11O1l_dataout <= wire_n1l11O0O_dataout AND NOT(n11O0O0O); + wire_n1l11O1O_dataout <= wire_n1l11Oii_dataout OR n11O0llO; + wire_n1l11Oi_dataout <= wire_nlll0lli_q(38) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(6); + wire_n1l11Oii_dataout <= wire_n1l11Oll_dataout OR n11O0lll; + wire_n1l11Oil_dataout <= wire_n1l11OlO_dataout OR n11O0lll; + wire_n1l11OiO_dataout <= wire_n1l11OOi_dataout AND NOT(n11O0lll); + wire_n1l11Ol_dataout <= wire_nlll0lli_q(39) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(7); + wire_n1l11Oli_dataout <= wire_n1l11OOl_dataout OR n11O0lll; + wire_n1l11Oll_dataout <= wire_n1l11OOO_dataout OR n11O0lli; + wire_n1l11OlO_dataout <= wire_n1l1011i_dataout OR n11O0lli; + wire_n1l11OO_dataout <= wire_nlll0lli_q(40) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(8); + wire_n1l11OOi_dataout <= wire_n1l1011l_dataout AND NOT(n11O0lli); + wire_n1l11OOl_dataout <= wire_n1l1011O_dataout OR n11O0lli; + wire_n1l11OOO_dataout <= wire_n1l1010l_dataout OR n11O0O0i; + wire_n1l1i00i_dataout <= wire_n1l1i0iO_dataout OR n11Oi01l; + wire_n1l1i00l_dataout <= wire_n1l1i0li_dataout AND NOT(n11Oi01l); + wire_n1l1i00O_dataout <= wire_n1l1i0ll_dataout AND NOT(n11Oi01l); + wire_n1l1i01i_dataout <= wire_n1l1i00O_dataout AND NOT(n11Oi01O); + wire_n1l1i01l_dataout <= wire_n1l1i0ii_dataout AND NOT(n11Oi01l); + wire_n1l1i01O_dataout <= wire_n1l1i0il_dataout AND NOT(n11Oi01l); + wire_n1l1i0i_dataout <= wire_nlll0lli_q(59) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(27); + wire_n1l1i0ii_dataout <= wire_n1l1i0lO_dataout AND NOT(n11Oi01i); + wire_n1l1i0il_dataout <= wire_n1l1i0Oi_dataout OR n11Oi01i; + wire_n1l1i0iO_dataout <= wire_n1l1i0Ol_dataout OR n11Oi01i; + wire_n1l1i0l_dataout <= wire_nlll0lli_q(60) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(28); + wire_n1l1i0li_dataout <= wire_n1l1i0OO_dataout AND NOT(n11Oi01i); + wire_n1l1i0ll_dataout <= wire_n1l1ii1i_dataout AND NOT(n11Oi01i); + wire_n1l1i0lO_dataout <= wire_n1l1ii1l_dataout OR n11Oi1OO; + wire_n1l1i0O_dataout <= wire_nlll0lli_q(61) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(29); + wire_n1l1i0Oi_dataout <= wire_n1l1ii1O_dataout OR n11Oi1OO; + wire_n1l1i0Ol_dataout <= wire_n1l1ii0i_dataout OR n11Oi1OO; + wire_n1l1i0OO_dataout <= wire_n1l1ii0l_dataout AND NOT(n11Oi1OO); + wire_n1l1i10i_dataout <= wire_n1l1i1iO_dataout AND NOT(n11Oi00l); + wire_n1l1i10l_dataout <= wire_n1l1i1li_dataout AND NOT(n11Oi00l); + wire_n1l1i10O_dataout <= wire_n1l1i1ll_dataout AND NOT(n11Oi00l); + wire_n1l1i11i_dataout <= wire_n1l1i10O_dataout AND NOT(n11Oi00O); + wire_n1l1i11l_dataout <= wire_n1l1i1ii_dataout OR n11Oi00l; + wire_n1l1i11O_dataout <= wire_n1l1i1il_dataout AND NOT(n11Oi00l); + wire_n1l1i1i_dataout <= wire_nlll0lli_q(56) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(24); + wire_n1l1i1ii_dataout <= wire_n1l1i1lO_dataout AND NOT(n11Oi00i); + wire_n1l1i1il_dataout <= wire_n1l1i1Oi_dataout OR n11Oi00i; + wire_n1l1i1iO_dataout <= wire_n1l1i1Ol_dataout AND NOT(n11Oi00i); + wire_n1l1i1l_dataout <= wire_nlll0lli_q(57) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(25); + wire_n1l1i1li_dataout <= wire_n1l1i1OO_dataout AND NOT(n11Oi00i); + wire_n1l1i1ll_dataout <= wire_n1l1i01i_dataout AND NOT(n11Oi00i); + wire_n1l1i1lO_dataout <= wire_n1l1i01l_dataout OR n11Oi01O; + wire_n1l1i1O_dataout <= wire_nlll0lli_q(58) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(26); + wire_n1l1i1Oi_dataout <= wire_n1l1i01O_dataout OR n11Oi01O; + wire_n1l1i1Ol_dataout <= wire_n1l1i00i_dataout AND NOT(n11Oi01O); + wire_n1l1i1OO_dataout <= wire_n1l1i00l_dataout AND NOT(n11Oi01O); + wire_n1l1ii0i_dataout <= wire_n1l1iiiO_dataout AND NOT(n11Oi1Ol); + wire_n1l1ii0l_dataout <= wire_n1l1iili_dataout OR n11Oi1Ol; + wire_n1l1ii0O_dataout <= wire_n1l1iill_dataout AND NOT(n11Oi1Ol); + wire_n1l1ii1i_dataout <= wire_n1l1ii0O_dataout AND NOT(n11Oi1OO); + wire_n1l1ii1l_dataout <= wire_n1l1iiii_dataout AND NOT(n11Oi1Ol); + wire_n1l1ii1O_dataout <= wire_n1l1iiil_dataout AND NOT(n11Oi1Ol); + wire_n1l1iii_dataout <= wire_nlll0lli_q(62) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(30); + wire_n1l1iiii_dataout <= wire_n1l1iilO_dataout OR n11Oi1Oi; + wire_n1l1iiil_dataout <= wire_n1l1iiOi_dataout AND NOT(n11Oi1Oi); + wire_n1l1iiiO_dataout <= wire_n1l1iiOl_dataout AND NOT(n11Oi1Oi); + wire_n1l1iil_dataout <= wire_nlll0lli_q(63) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(31); + wire_n1l1iili_dataout <= wire_n1l1iiOO_dataout OR n11Oi1Oi; + wire_n1l1iill_dataout <= wire_n1l1il1i_dataout AND NOT(n11Oi1Oi); + wire_n1l1iilO_dataout <= wire_n1l1il1l_dataout AND NOT(n11Oi1lO); + wire_n1l1iiO_dataout <= wire_nlll0lli_q(0) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(32); + wire_n1l1iiOi_dataout <= wire_n1l1il1O_dataout OR n11Oi1lO; + wire_n1l1iiOl_dataout <= wire_n1l1il0i_dataout AND NOT(n11Oi1lO); + wire_n1l1iiOO_dataout <= wire_n1l1il0l_dataout OR n11Oi1lO; + wire_n1l1il0i_dataout <= wire_n1l1iliO_dataout AND NOT(n11Oi1ll); + wire_n1l1il0l_dataout <= wire_n1l1illi_dataout OR n11Oi1ll; + wire_n1l1il0O_dataout <= wire_n1l1illl_dataout AND NOT(n11Oi1ll); + wire_n1l1il1i_dataout <= wire_n1l1il0O_dataout AND NOT(n11Oi1lO); + wire_n1l1il1l_dataout <= wire_n1l1ilii_dataout OR n11Oi1ll; + wire_n1l1il1O_dataout <= wire_n1l1ilil_dataout OR n11Oi1ll; + wire_n1l1ili_dataout <= wire_nlll0lli_q(1) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(33); + wire_n1l1ilii_dataout <= wire_n1l1illO_dataout AND NOT(n11Oi1li); + wire_n1l1ilil_dataout <= wire_n1l1ilOi_dataout AND NOT(n11Oi1li); + wire_n1l1iliO_dataout <= wire_n1l1ilOl_dataout OR n11Oi1li; + wire_n1l1ill_dataout <= wire_nlll0lli_q(2) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(34); + wire_n1l1illi_dataout <= wire_n1l1ilOO_dataout OR n11Oi1li; + wire_n1l1illl_dataout <= wire_n1l1iO1i_dataout AND NOT(n11Oi1li); + wire_n1l1illO_dataout <= wire_n1l1iO1l_dataout OR n11Oi1iO; + wire_n1l1ilO_dataout <= wire_nlll0lli_q(3) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(35); + wire_n1l1ilOi_dataout <= wire_n1l1iO1O_dataout AND NOT(n11Oi1iO); + wire_n1l1ilOl_dataout <= wire_n1l1iO0i_dataout OR n11Oi1iO; + wire_n1l1ilOO_dataout <= wire_n1l1iO0l_dataout OR n11Oi1iO; + wire_n1l1iO0i_dataout <= wire_n1l1iOiO_dataout OR n11Oi1ii; + wire_n1l1iO0l_dataout <= wire_n1l1iOli_dataout OR n11Oi1ii; + wire_n1l1iO0O_dataout <= wire_niO01ill_w_lg_n11Oi10O19980w(0) AND NOT(n11Oi1ii); + wire_n1l1iO1i_dataout <= wire_n1l1iO0O_dataout AND NOT(n11Oi1iO); + wire_n1l1iO1l_dataout <= wire_n1l1iOii_dataout AND NOT(n11Oi1ii); + wire_n1l1iO1O_dataout <= wire_n1l1iOil_dataout OR n11Oi1ii; + wire_n1l1iOi_dataout <= wire_nlll0lli_q(4) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(36); + wire_n1l1iOii_dataout <= wire_n1l1iOll_dataout OR n11Oi10O; + wire_n1l1iOil_dataout <= wire_n1l1iOlO_dataout OR n11Oi10O; + wire_n1l1iOiO_dataout <= wire_n1l1iOOi_dataout OR n11Oi10O; + wire_n1l1iOl_dataout <= wire_nlll0lli_q(5) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(37); + wire_n1l1iOli_dataout <= wire_n1l1iOOl_dataout OR n11Oi10O; + wire_n1l1iOll_dataout <= wire_n1l1iOOO_dataout AND NOT(n11Oi10l); + wire_n1l1iOlO_dataout <= wire_n1l1l11i_dataout AND NOT(n11Oi10l); + wire_n1l1iOO_dataout <= wire_nlll0lli_q(6) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(38); + wire_n1l1iOOi_dataout <= wire_n1l1l11l_dataout AND NOT(n11Oi10l); + wire_n1l1iOOl_dataout <= wire_n1l1l11O_dataout AND NOT(n11Oi10l); + wire_n1l1iOOO_dataout <= wire_n1l1l10i_dataout OR n11Oi10i; + wire_n1l1l00i_dataout <= wire_n1l1l0il_dataout AND NOT(n11O0OOO); + wire_n1l1l00l_dataout <= wire_n1l1l0li_dataout AND NOT(n11O0OOl); + wire_n1l1l00O_dataout <= wire_n1l1l0iO_dataout OR n11O0OOl; + wire_n1l1l01i_dataout <= wire_n1l1l00l_dataout OR n11O0OOO; + wire_n1l1l01l_dataout <= wire_n1l1l00O_dataout AND NOT(n11O0OOO); + wire_n1l1l01O_dataout <= wire_n1l1l0ii_dataout OR n11O0OOO; + wire_n1l1l0i_dataout <= wire_nlll0lli_q(10) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(42); + wire_n1l1l0ii_dataout <= wire_n1l1l0li_dataout OR n11O0OOl; + wire_n1l1l0il_dataout <= wire_niO01ill_w_lg_n11O0OOi19979w(0) AND NOT(n11O0OOl); + wire_n1l1l0iO_dataout <= wire_niO01ill_w_lg_n11O0OlO19978w(0) OR n11O0OOi; + wire_n1l1l0l_dataout <= wire_nlll0lli_q(11) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(43); + wire_n1l1l0li_dataout <= wire_n1l1l0ll_dataout OR n11O0OOi; + wire_n1l1l0ll_dataout <= wire_niO01ill_w_lg_n11Oi1il19977w(0) AND NOT(n11O0OlO); + wire_n1l1l0O_dataout <= wire_nlll0lli_q(12) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(44); + wire_n1l1l10i_dataout <= wire_n1l1l1il_dataout AND NOT(n11Oi11O); + wire_n1l1l10l_dataout <= wire_n1l1l1iO_dataout OR n11Oi11O; + wire_n1l1l10O_dataout <= wire_n1l1l1li_dataout AND NOT(n11Oi11O); + wire_n1l1l11i_dataout <= wire_n1l1l10l_dataout AND NOT(n11Oi10i); + wire_n1l1l11l_dataout <= wire_n1l1l10O_dataout AND NOT(n11Oi10i); + wire_n1l1l11O_dataout <= wire_n1l1l1ii_dataout AND NOT(n11Oi10i); + wire_n1l1l1i_dataout <= wire_nlll0lli_q(7) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(39); + wire_n1l1l1ii_dataout <= wire_n1l1l1ll_dataout AND NOT(n11Oi11O); + wire_n1l1l1il_dataout <= wire_n1l1l1lO_dataout OR n11Oi11l; + wire_n1l1l1iO_dataout <= wire_n1l1l1Oi_dataout OR n11Oi11l; + wire_n1l1l1l_dataout <= wire_nlll0lli_q(8) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(40); + wire_n1l1l1li_dataout <= wire_n1l1l1Ol_dataout AND NOT(n11Oi11l); + wire_n1l1l1ll_dataout <= wire_n1l1l1OO_dataout AND NOT(n11Oi11l); + wire_n1l1l1lO_dataout <= wire_n1l1l01i_dataout AND NOT(n11Oi11i); + wire_n1l1l1O_dataout <= wire_nlll0lli_q(9) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(41); + wire_n1l1l1Oi_dataout <= wire_n1l1l01l_dataout AND NOT(n11Oi11i); + wire_n1l1l1Ol_dataout <= wire_n1l1l01O_dataout OR n11Oi11i; + wire_n1l1l1OO_dataout <= wire_n1l1l00i_dataout AND NOT(n11Oi11i); + wire_n1l1lii_dataout <= wire_nlll0lli_q(13) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(45); + wire_n1l1lil_dataout <= wire_nlll0lli_q(14) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(46); + wire_n1l1liO_dataout <= wire_nlll0lli_q(15) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(47); + wire_n1l1lli_dataout <= wire_nlll0lli_q(16) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(48); + wire_n1l1lll_dataout <= wire_nlll0lli_q(17) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(49); + wire_n1l1llO_dataout <= wire_nlll0lli_q(18) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(50); + wire_n1l1lOi_dataout <= wire_nlll0lli_q(19) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(51); + wire_n1l1lOl_dataout <= wire_nlll0lli_q(20) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(52); + wire_n1l1lOO_dataout <= wire_nlll0lli_q(21) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(53); + wire_n1l1O00i_dataout <= wire_n1l1O0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O00l_dataout <= wire_n1l1O0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O00O_dataout <= wire_n1l1O0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O01i_dataout <= wire_n1l1O0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O01l_dataout <= wire_n1l1O0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O01O_dataout <= wire_n1l1O0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O0i_dataout <= wire_nlll0lli_q(25) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(57); + wire_n1l1O0ii_dataout <= wire_n1l1O0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O0il_dataout <= wire_n1l1Oi1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1l1O0iO_dataout <= wire_n1l1Oi1l_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1O0l_dataout <= wire_nlll0lli_q(26) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(58); + wire_n1l1O0li_dataout <= wire_n1l1Oi1O_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1O0ll_dataout <= wire_n1l1Oi0i_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1O0lO_dataout <= wire_n1l1Oi0l_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1O0O_dataout <= wire_nlll0lli_q(27) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(59); + wire_n1l1O0Oi_dataout <= wire_n1l1Oi0O_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1O0Ol_dataout <= wire_n1l1Oiii_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1O0OO_dataout <= wire_n1l1Oiil_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1O1i_dataout <= wire_nlll0lli_q(22) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(54); + wire_n1l1O1l_dataout <= wire_nlll0lli_q(23) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(55); + wire_n1l1O1O_dataout <= wire_nlll0lli_q(24) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(56); + wire_n1l1Oi0i_dataout <= wire_n1l1OilO_dataout WHEN n1lilO0l = '1' ELSE n1l1O1iO; + wire_n1l1Oi0l_dataout <= wire_n1l1OiOi_dataout WHEN n1lilO0l = '1' ELSE n1l1O1li; + wire_n1l1Oi0O_dataout <= wire_n1l1OiOl_dataout WHEN n1lilO0l = '1' ELSE n1l1O1ll; + wire_n1l1Oi1i_dataout <= wire_n1l1OiiO_dataout AND NOT(wire_w_lg_niOli0llO18964w(0)); + wire_n1l1Oi1l_dataout <= wire_n1l1Oili_dataout WHEN n1lilO0l = '1' ELSE n1l1Ol0l; + wire_n1l1Oi1O_dataout <= wire_n1l1Oill_dataout WHEN n1lilO0l = '1' ELSE n1l1O1il; + wire_n1l1Oii_dataout <= wire_nlll0lli_q(28) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(60); + wire_n1l1Oiii_dataout <= wire_n1l1OiOO_dataout WHEN n1lilO0l = '1' ELSE n1l1O1lO; + wire_n1l1Oiil_dataout <= wire_n1l1Ol1i_dataout WHEN n1lilO0l = '1' ELSE n1l1O1Oi; + wire_n1l1OiiO_dataout <= wire_n1l1Ol1l_dataout WHEN n1lilO0l = '1' ELSE n1l1O1Ol; + wire_n1l1Oil_dataout <= wire_nlll0lli_q(29) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(61); + wire_n1l1Oili_dataout <= wire_n1l1Ol1O_o(0) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1Ol0l; + wire_n1l1Oill_dataout <= wire_n1l1Ol1O_o(1) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1O1il; + wire_n1l1OilO_dataout <= wire_n1l1Ol1O_o(2) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1O1iO; + wire_n1l1OiO_dataout <= wire_nlll0lli_q(30) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(62); + wire_n1l1OiOi_dataout <= wire_n1l1Ol1O_o(3) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1O1li; + wire_n1l1OiOl_dataout <= wire_n1l1Ol1O_o(4) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1O1ll; + wire_n1l1OiOO_dataout <= wire_n1l1Ol1O_o(5) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1O1lO; + wire_n1l1Ol0O_dataout <= wire_n1l1Olii_dataout OR (n1110Oli OR (n1l1OllO OR (n1lilOii AND n1l1OlOO))); + wire_n1l1Ol0O_w_lg_dataout18957w(0) <= wire_n1l1Ol0O_dataout AND wire_w_lg_niOli0lOO18956w(0); + wire_n1l1Ol0O_w_lg_dataout18951w(0) <= NOT wire_n1l1Ol0O_dataout; + wire_n1l1Ol1i_dataout <= wire_n1l1Ol1O_o(6) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1O1Oi; + wire_n1l1Ol1l_dataout <= wire_n1l1Ol1O_o(7) WHEN wire_n1l1Ol0i_o = '1' ELSE n1l1O1Ol; + wire_n1l1Oli_dataout <= wire_nlll0lli_q(31) WHEN (NOT wire_nlll0lli_q(93)) = '1' ELSE wire_nlll0lli_q(63); + wire_n1l1Olii_dataout <= n1l1O1OO AND n1l1OlOO; + wire_n1l1OOl_dataout <= nlOi1O0O AND niOO00llO; + wire_n1l1OOOO_dataout <= wire_n1l1Ol0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1li000i_dataout <= wire_n1l1Ol0O_dataout WHEN niOli011O = '1' ELSE n1l001lO; + wire_n1li000l_dataout <= n1l001Oi AND NOT(niOli011O); + wire_n1li000O_dataout <= wire_n1l1Ol0O_dataout WHEN niOli011O = '1' ELSE n1l001Ol; + wire_n1li001i_dataout <= wire_n1l1Ol0O_dataout WHEN niOli011O = '1' ELSE n1l001iO; + wire_n1li001l_dataout <= wire_n1l1Ol0O_dataout WHEN niOli011O = '1' ELSE n1l001li; + wire_n1li001O_dataout <= wire_n1l1Ol0O_dataout WHEN niOli011O = '1' ELSE n1l001ll; + wire_n1li00i_dataout <= n1l011i AND NOT(k_hip(0)); + wire_n1li00ii_dataout <= wire_n1l1Ol0O_dataout WHEN niOli011O = '1' ELSE n1l001OO; + wire_n1li00l_dataout <= n1l011l AND NOT(k_hip(0)); + wire_n1li00lO_dataout <= wire_n1li00OO_dataout AND NOT(niOli0l0l); + wire_n1li00O_dataout <= n1l011O AND NOT(k_hip(0)); + wire_n1li00Oi_dataout <= wire_n1li00OO_dataout OR niOli0l0l; + wire_n1li00Ol_dataout <= wire_n1li0i1i_dataout AND NOT(niOli0l0l); + wire_n1li00OO_dataout <= niOli0i1l OR niOli0llO; + wire_n1li010i_dataout <= wire_n1li01Oi_dataout WHEN niOli0l1i = '1' ELSE n1l001OO; + wire_n1li010l_dataout <= wire_n1li01Ol_dataout AND NOT(niOli010i); + wire_n1li010O_dataout <= wire_n1li01OO_dataout AND NOT(niOli010i); + wire_n1li011i_dataout <= wire_n1li01li_dataout WHEN niOli0l1i = '1' ELSE n1l001lO; + wire_n1li011l_dataout <= wire_n1li01ll_dataout WHEN niOli0l1i = '1' ELSE n1l001Oi; + wire_n1li011O_dataout <= wire_n1li01lO_dataout WHEN niOli0l1i = '1' ELSE n1l001Ol; + wire_n1li01i_dataout <= wire_n1li00l_dataout AND NOT(wire_n1liOli_dataout); + wire_n1li01ii_dataout <= wire_n1li001i_dataout OR niOli010i; + wire_n1li01il_dataout <= wire_n1li001l_dataout OR niOli010i; + wire_n1li01iO_dataout <= wire_n1li001O_dataout OR niOli010i; + wire_n1li01l_dataout <= wire_n1li00O_dataout OR wire_n1liOli_dataout; + wire_n1li01li_dataout <= wire_n1li000i_dataout AND NOT(niOli010i); + wire_n1li01ll_dataout <= wire_n1li000l_dataout AND NOT(niOli010i); + wire_n1li01lO_dataout <= wire_n1li000O_dataout AND NOT(niOli010i); + wire_n1li01O_dataout <= nlOiliii OR k_hip(0); + wire_n1li01Oi_dataout <= wire_n1li00ii_dataout OR niOli010i; + wire_n1li01Ol_dataout <= n1l001ii AND NOT(niOli011O); + wire_n1li01OO_dataout <= n1l001il AND NOT(niOli011O); + wire_n1li0i0i_dataout <= wire_w_lg_niOli01iO19565w(0) AND NOT(niOli01il); + wire_n1li0i0l_dataout <= wire_n1li0iOl_dataout OR niOli01li; + wire_n1li0i0O_dataout <= wire_n1li0iOO_dataout AND NOT(niOli01li); + wire_n1li0i1i_dataout <= niOli0i1l AND NOT(niOli0llO); + wire_n1li0i1l_dataout <= niOli01iO AND NOT(niOli01il); + wire_n1li0i1O_dataout <= wire_w_lg_niOli01iO19565w(0) OR niOli01il; + wire_n1li0ii_dataout <= wire_n1li0ll_dataout AND NOT(wire_n1liOli_dataout); + wire_n1li0iii_dataout <= wire_n1li0l1i_dataout OR niOli01li; + wire_n1li0iil_dataout <= wire_n1li0l1l_dataout AND NOT(niOli01li); + wire_n1li0iiO_dataout <= wire_n1li0l1O_dataout OR niOli01li; + wire_n1li0il_dataout <= wire_n1li0lO_dataout AND NOT(wire_n1liOli_dataout); + wire_n1li0ili_dataout <= wire_n1li0l0i_dataout OR niOli01li; + wire_n1li0ill_dataout <= wire_n1li0l0l_dataout AND NOT(niOli01li); + wire_n1li0ilO_dataout <= wire_n1li0l0O_dataout OR niOli01li; + wire_n1li0iO_dataout <= wire_n1li0Oi_dataout AND NOT(wire_n1liOli_dataout); + wire_n1li0iOi_dataout <= wire_n1li0lii_dataout AND NOT(niOli01li); + wire_n1li0iOl_dataout <= wire_n1li0lil_dataout AND NOT(niOli01ll); + wire_n1li0iOO_dataout <= wire_n1li0liO_dataout AND NOT(niOli01ll); + wire_n1li0l0i_dataout <= wire_n1li0lOi_dataout OR niOli01ll; + wire_n1li0l0l_dataout <= wire_n1li0lOl_dataout AND NOT(niOli01ll); + wire_n1li0l0O_dataout <= wire_n1li0lOO_dataout OR niOli01ll; + wire_n1li0l1i_dataout <= wire_n1li0lli_dataout OR niOli01ll; + wire_n1li0l1l_dataout <= wire_n1li0lll_dataout OR niOli01ll; + wire_n1li0l1O_dataout <= wire_n1li0llO_dataout OR niOli01ll; + wire_n1li0li_dataout <= wire_n1li0Ol_dataout OR wire_n1liOli_dataout; + wire_n1li0lii_dataout <= wire_n1li0O1i_dataout OR niOli01ll; + wire_n1li0lil_dataout <= wire_n1li0O1l_dataout AND NOT(niOli01lO); + wire_n1li0liO_dataout <= wire_n1li0O1O_dataout OR niOli01lO; + wire_n1li0ll_dataout <= wire_n1li0OO_dataout AND NOT(wire_w_lg_w_k_hip_range2413w2429w(0)); + wire_n1li0lli_dataout <= wire_n1li0O0i_dataout AND NOT(niOli01lO); + wire_n1li0lll_dataout <= wire_n1li0O0l_dataout OR niOli01lO; + wire_n1li0llO_dataout <= wire_n1li0O0O_dataout AND NOT(niOli01lO); + wire_n1li0lO_dataout <= wire_n1lii1i_dataout OR wire_w_lg_w_k_hip_range2413w2429w(0); + wire_n1li0lOi_dataout <= wire_n1li0Oii_dataout AND NOT(niOli01lO); + wire_n1li0lOl_dataout <= wire_n1li0Oil_dataout OR niOli01lO; + wire_n1li0lOO_dataout <= wire_n1li0OiO_dataout AND NOT(niOli01lO); + wire_n1li0O0i_dataout <= wire_w_lg_niOli0l0i19564w(0) OR NOT(niOli01Oi); + wire_n1li0O0l_dataout <= wire_w_lg_niOli0l0i19564w(0) OR NOT(niOli01Oi); + wire_n1li0O0O_dataout <= wire_w_lg_niOli0l0i19564w(0) OR NOT(niOli01Oi); + wire_n1li0O1i_dataout <= wire_n1li0Oli_dataout AND NOT(niOli01lO); + wire_n1li0O1l_dataout <= wire_w_lg_niOli0l0i19564w(0) AND niOli01Oi; + wire_n1li0O1O_dataout <= wire_w_lg_niOli0l0i19564w(0) AND niOli01Oi; + wire_n1li0Oi_dataout <= wire_n1lii1l_dataout AND NOT(wire_w_lg_w_k_hip_range2413w2429w(0)); + wire_n1li0Oii_dataout <= wire_w_lg_niOli0l0i19564w(0) OR NOT(niOli01Oi); + wire_n1li0Oil_dataout <= wire_w_lg_niOli0l0i19564w(0) AND niOli01Oi; + wire_n1li0OiO_dataout <= wire_w_lg_niOli0l0i19564w(0) OR NOT(niOli01Oi); + wire_n1li0Ol_dataout <= wire_n1lii1O_dataout AND NOT(wire_w_lg_w_k_hip_range2413w2429w(0)); + wire_n1li0Oli_dataout <= wire_w_lg_niOli0l0i19564w(0) OR NOT(niOli01Oi); + wire_n1li0Oll_dataout <= n1l001ii AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1li0OlO_dataout <= n1l001il AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1li0OO_dataout <= nlOiliii AND NOT(niOO00l1O); + wire_n1li0OOi_dataout <= n1l001iO OR wire_niO01ill_w_lg_n1lO0lOi9962w(0); + wire_n1li0OOl_dataout <= n1l001li OR wire_niO01ill_w_lg_n1lO0lOi9962w(0); + wire_n1li0OOO_dataout <= n1l001ll OR wire_niO01ill_w_lg_n1lO0lOi9962w(0); + wire_n1li100i_dataout <= n1l001iO AND NOT(niOli1OOl); + wire_n1li100l_dataout <= n1l001li AND NOT(niOli1OOl); + wire_n1li100O_dataout <= n1l001ll AND NOT(niOli1OOl); + wire_n1li101i_dataout <= wire_n1li10li_dataout AND NOT(niOli1OOi); + wire_n1li101l_dataout <= n1l001ii OR niOli1OOl; + wire_n1li101O_dataout <= n1l001il OR niOli1OOl; + wire_n1li10i_dataout <= wire_n1lilli_dataout WHEN n1l011O = '1' ELSE n1l01li; + wire_n1li10ii_dataout <= n1l001lO AND NOT(niOli1OOl); + wire_n1li10il_dataout <= n1l001Oi OR niOli1OOl; + wire_n1li10iO_dataout <= n1l001Ol OR niOli1OOl; + wire_n1li10l_dataout <= wire_n1lilll_dataout WHEN n1l011O = '1' ELSE n1l01ll; + wire_n1li10li_dataout <= n1l001OO AND NOT(niOli1OOl); + wire_n1li10ll_dataout <= wire_n1li1i0l_dataout AND NOT(niOli1OOO); + wire_n1li10lO_dataout <= wire_n1li1i0O_dataout OR niOli1OOO; + wire_n1li10O_dataout <= wire_n1lillO_dataout WHEN n1l011O = '1' ELSE n1l01lO; + wire_n1li10Oi_dataout <= wire_n1li1iii_dataout AND NOT(niOli1OOO); + wire_n1li10Ol_dataout <= wire_n1li1iil_dataout OR niOli1OOO; + wire_n1li10OO_dataout <= wire_n1li1iiO_dataout AND NOT(niOli1OOO); + wire_n1li110i_dataout <= wire_n1li11Oi_dataout AND NOT(niOli1OlO); + wire_n1li110l_dataout <= wire_n1li11Ol_dataout OR niOli1OlO; + wire_n1li110O_dataout <= wire_n1li11OO_dataout AND NOT(niOli1OlO); + wire_n1li111i_dataout <= wire_n1li11li_dataout AND NOT(niOli1OlO); + wire_n1li111l_dataout <= wire_n1li11ll_dataout OR niOli1OlO; + wire_n1li111O_dataout <= wire_n1li11lO_dataout AND NOT(niOli1OlO); + wire_n1li11ii_dataout <= wire_n1li101i_dataout AND NOT(niOli1OlO); + wire_n1li11il_dataout <= wire_n1li101l_dataout OR niOli1OOi; + wire_n1li11iO_dataout <= wire_n1li101O_dataout AND NOT(niOli1OOi); + wire_n1li11l_dataout <= wire_n1lilil_dataout WHEN n1l011O = '1' ELSE n1l01il; + wire_n1li11li_dataout <= wire_n1li100i_dataout OR niOli1OOi; + wire_n1li11ll_dataout <= wire_n1li100l_dataout AND NOT(niOli1OOi); + wire_n1li11lO_dataout <= wire_n1li100O_dataout AND NOT(niOli1OOi); + wire_n1li11O_dataout <= wire_n1liliO_dataout WHEN n1l011O = '1' ELSE n1l01iO; + wire_n1li11Oi_dataout <= wire_n1li10ii_dataout AND NOT(niOli1OOi); + wire_n1li11Ol_dataout <= wire_n1li10il_dataout OR niOli1OOi; + wire_n1li11OO_dataout <= wire_n1li10iO_dataout AND NOT(niOli1OOi); + wire_n1li1i0i_dataout <= wire_n1li1iOi_dataout AND NOT(niOli1OOO); + wire_n1li1i0l_dataout <= wire_n1li1iOl_dataout OR niOli011i; + wire_n1li1i0O_dataout <= wire_n1li1iOO_dataout AND NOT(niOli011i); + wire_n1li1i1i_dataout <= wire_n1li1ili_dataout AND NOT(niOli1OOO); + wire_n1li1i1l_dataout <= wire_n1li1ill_dataout OR niOli1OOO; + wire_n1li1i1O_dataout <= wire_n1li1ilO_dataout AND NOT(niOli1OOO); + wire_n1li1ii_dataout <= wire_n1lilOi_dataout WHEN n1l011O = '1' ELSE n1l01Oi; + wire_n1li1iii_dataout <= wire_n1li1l1i_dataout OR niOli011i; + wire_n1li1iil_dataout <= wire_n1li1l1l_dataout AND NOT(niOli011i); + wire_n1li1iiO_dataout <= wire_n1li1l1O_dataout AND NOT(niOli011i); + wire_n1li1il_dataout <= wire_n1lilOl_dataout WHEN n1l011O = '1' ELSE n1l01Ol; + wire_n1li1ili_dataout <= wire_n1li1l0i_dataout AND NOT(niOli011i); + wire_n1li1ill_dataout <= wire_n1li1l0l_dataout OR niOli011i; + wire_n1li1ilO_dataout <= wire_n1li1l0O_dataout AND NOT(niOli011i); + wire_n1li1iO_dataout <= wire_n1lilOO_dataout WHEN n1l011O = '1' ELSE n1l01OO; + wire_n1li1iOi_dataout <= wire_n1li1lii_dataout AND NOT(niOli011i); + wire_n1li1iOl_dataout <= n1l001ii OR niOli011l; + wire_n1li1iOO_dataout <= n1l001il OR niOli011l; + wire_n1li1l0i_dataout <= n1l001lO AND NOT(niOli011l); + wire_n1li1l0l_dataout <= n1l001Oi OR niOli011l; + wire_n1li1l0O_dataout <= n1l001Ol OR niOli011l; + wire_n1li1l1i_dataout <= n1l001iO AND NOT(niOli011l); + wire_n1li1l1l_dataout <= n1l001li AND NOT(niOli011l); + wire_n1li1l1O_dataout <= n1l001ll AND NOT(niOli011l); + wire_n1li1li_dataout <= wire_n1liO1i_dataout WHEN n1l011O = '1' ELSE n1l001i; + wire_n1li1lii_dataout <= n1l001OO AND NOT(niOli011l); + wire_n1li1lil_dataout <= wire_n1li1O1l_dataout AND NOT(niOli010O); + wire_n1li1liO_dataout <= wire_n1li1O1O_dataout AND NOT(niOli010O); + wire_n1li1ll_dataout <= wire_n1liO1l_dataout WHEN n1l011O = '1' ELSE n1l001l; + wire_n1li1lli_dataout <= wire_n1li1O0i_dataout OR niOli010O; + wire_n1li1lll_dataout <= wire_n1li1O0l_dataout OR niOli010O; + wire_n1li1llO_dataout <= wire_n1li1O0O_dataout OR niOli010O; + wire_n1li1lO_dataout <= wire_n1liO1O_dataout WHEN n1l011O = '1' ELSE n1l000O; + wire_n1li1lOi_dataout <= wire_n1li1Oii_dataout OR niOli010O; + wire_n1li1lOl_dataout <= wire_n1li1Oil_dataout AND NOT(niOli010O); + wire_n1li1lOO_dataout <= wire_n1li1OiO_dataout OR niOli010O; + wire_n1li1O0i_dataout <= wire_n1li1OOi_dataout AND NOT(niOli010l); + wire_n1li1O0l_dataout <= wire_n1li1OOl_dataout OR niOli010l; + wire_n1li1O0O_dataout <= wire_n1li1OOO_dataout AND NOT(niOli010l); + wire_n1li1O1i_dataout <= wire_n1li1Oli_dataout OR niOli010O; + wire_n1li1O1l_dataout <= wire_n1li1Oll_dataout AND NOT(niOli010l); + wire_n1li1O1O_dataout <= wire_n1li1OlO_dataout OR niOli010l; + wire_n1li1Oi_dataout <= wire_n1liO0i_dataout WHEN n1l011O = '1' ELSE n1l00ii; + wire_n1li1Oii_dataout <= wire_n1li011i_dataout AND NOT(niOli010l); + wire_n1li1Oil_dataout <= wire_n1li011l_dataout OR niOli010l; + wire_n1li1OiO_dataout <= wire_n1li011O_dataout AND NOT(niOli010l); + wire_n1li1Ol_dataout <= wire_n1li01O_dataout AND NOT(wire_n1liOli_dataout); + wire_n1li1Oli_dataout <= wire_n1li010i_dataout AND NOT(niOli010l); + wire_n1li1Oll_dataout <= wire_n1li010l_dataout WHEN niOli0l1i = '1' ELSE n1l001ii; + wire_n1li1OlO_dataout <= wire_n1li010O_dataout WHEN niOli0l1i = '1' ELSE n1l001il; + wire_n1li1OO_dataout <= wire_n1li00i_dataout AND NOT(wire_n1liOli_dataout); + wire_n1li1OOi_dataout <= wire_n1li01ii_dataout WHEN niOli0l1i = '1' ELSE n1l001iO; + wire_n1li1OOl_dataout <= wire_n1li01il_dataout WHEN niOli0l1i = '1' ELSE n1l001li; + wire_n1li1OOO_dataout <= wire_n1li01iO_dataout WHEN niOli0l1i = '1' ELSE n1l001ll; + wire_n1lii01i_dataout <= wire_n1lii01l_dataout AND NOT((n1lilO0O OR (n1lilO0l AND (niOli0lOl OR niOli0lOO)))); + wire_n1lii01l_dataout <= n1l0001l OR (n1lilO0l AND wire_w_lg_niOli0lOO18956w(0)); + wire_n1lii0ii_dataout <= wire_n1lii0ll_o(0) WHEN niOli000O = '1' ELSE wire_n1lii0iO_dataout; + wire_n1lii0il_dataout <= wire_n1lii0ll_o(1) WHEN niOli000O = '1' ELSE wire_n1lii0li_dataout; + wire_n1lii0iO_dataout <= n1l0011l AND NOT(niOli00ii); + wire_n1lii0li_dataout <= n1l0011O AND NOT(niOli00ii); + wire_n1lii0lO_dataout <= wire_niO01ill_w_lg_nlOllOlOO11619w(0) WHEN niOli00il = '1' ELSE wire_n1lii0Oi_dataout; + wire_n1lii0Oi_dataout <= (NOT k_gbl_hip(42)) WHEN niOli00iO = '1' ELSE wire_n1lii0Ol_dataout; + wire_n1lii0Ol_dataout <= wire_n1lii0OO_dataout AND NOT(wire_niO11i1i_dataout); + wire_n1lii0OO_dataout <= n1l000li AND NOT(niOli00li); + wire_n1lii10i_dataout <= n1l001OO OR wire_niO01ill_w_lg_n1lO0lOi9962w(0); + wire_n1lii11i_dataout <= n1l001lO AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1lii11l_dataout <= n1l001Oi AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1lii11O_dataout <= n1l001Ol AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1lii1i_dataout <= n1l011i OR niOO00l1O; + wire_n1lii1l_dataout <= n1l011l AND NOT(niOO00l1O); + wire_n1lii1O_dataout <= n1l011O AND NOT(niOO00l1O); + wire_n1liii0i_dataout <= wire_niO01ill_w_lg_nlOllOlOl12531w(0) WHEN niOli00il = '1' ELSE wire_n1liii0l_dataout; + wire_n1liii0l_dataout <= (NOT k_gbl_hip(41)) WHEN niOli00iO = '1' ELSE wire_n1liii0O_dataout; + wire_n1liii0O_dataout <= wire_n1liiiii_dataout AND NOT(wire_niO11l1i_dataout); + wire_n1liiiii_dataout <= n1l000iO AND NOT(niOli00li); + wire_n1liiiil_dataout <= wire_niO01ill_w_lg_nlOllOlOi13438w(0) WHEN niOli00il = '1' ELSE wire_n1liiiiO_dataout; + wire_n1liiiiO_dataout <= (NOT k_gbl_hip(40)) WHEN niOli00iO = '1' ELSE wire_n1liiili_dataout; + wire_n1liiili_dataout <= wire_n1liiill_dataout AND NOT(wire_niO11O1i_dataout); + wire_n1liiill_dataout <= n1l000il AND NOT(niOli00li); + wire_n1liiilO_dataout <= wire_niO01ill_w_lg_nlOllOllO14345w(0) WHEN niOli00il = '1' ELSE wire_n1liiiOi_dataout; + wire_n1liiiOi_dataout <= (NOT k_gbl_hip(39)) WHEN niOli00iO = '1' ELSE wire_n1liiiOl_dataout; + wire_n1liiiOl_dataout <= wire_n1liiiOO_dataout AND NOT(wire_niO1011i_dataout); + wire_n1liiiOO_dataout <= n1l000ii AND NOT(niOli00li); + wire_n1liil0i_dataout <= n1l0000O AND NOT(niOli00li); + wire_n1liil0l_dataout <= wire_niO01ill_w_lg_nlOllOlli16159w(0) WHEN niOli00il = '1' ELSE wire_n1liil0O_dataout; + wire_n1liil0O_dataout <= (NOT k_gbl_hip(37)) WHEN niOli00iO = '1' ELSE wire_n1liilii_dataout; + wire_n1liil1i_dataout <= wire_niO01ill_w_lg_nlOllOlll15252w(0) WHEN niOli00il = '1' ELSE wire_n1liil1l_dataout; + wire_n1liil1l_dataout <= (NOT k_gbl_hip(38)) WHEN niOli00iO = '1' ELSE wire_n1liil1O_dataout; + wire_n1liil1O_dataout <= wire_n1liil0i_dataout AND NOT(wire_niO1001i_dataout); + wire_n1liilii_dataout <= wire_n1liilil_dataout AND NOT(wire_niO10i1i_dataout); + wire_n1liilil_dataout <= n1l0000l AND NOT(niOli00li); + wire_n1liiliO_dataout <= wire_niO01ill_w_lg_nlOllOliO17066w(0) WHEN niOli00il = '1' ELSE wire_n1liilli_dataout; + wire_n1liilli_dataout <= (NOT k_gbl_hip(36)) WHEN niOli00iO = '1' ELSE wire_n1liilll_dataout; + wire_n1liilll_dataout <= wire_n1liillO_dataout AND NOT(wire_niO10l1i_dataout); + wire_n1liillO_dataout <= n1l0000i AND NOT(niOli00li); + wire_n1liilOi_dataout <= wire_niO01ill_w_lg_nlOllO0iO17973w(0) WHEN niOli00il = '1' ELSE wire_n1liilOl_dataout; + wire_n1liilOl_dataout <= (NOT k_gbl_hip(35)) WHEN niOli00iO = '1' ELSE wire_n1liilOO_dataout; + wire_n1liilOO_dataout <= wire_n1liiO1i_dataout AND NOT(wire_niO10O1i_dataout); + wire_n1liiO0i_dataout <= wire_n1liiOil_dataout OR niOli00OO; + wire_n1liiO0l_dataout <= wire_n1liiOiO_dataout AND NOT(niOli00OO); + wire_n1liiO0O_dataout <= wire_n1liiOli_dataout AND NOT(niOli00ll); + wire_n1liiO1i_dataout <= n1l0001O AND NOT(niOli00li); + wire_n1liiO1l_dataout <= wire_n1liiO0O_dataout AND NOT(niOli00OO); + wire_n1liiO1O_dataout <= wire_n1liiOii_dataout OR niOli00OO; + wire_n1liiOii_dataout <= wire_n1liiOll_dataout OR niOli00ll; + wire_n1liiOil_dataout <= wire_n1liiOlO_dataout OR niOli00ll; + wire_n1liiOiO_dataout <= wire_n1liiOOi_dataout OR niOli00ll; + wire_n1liiOli_dataout <= wire_n1liiOOl_dataout AND NOT(niOli00Ol); + wire_n1liiOll_dataout <= wire_n1liiOOO_dataout OR niOli00Ol; + wire_n1liiOlO_dataout <= wire_n1lil11i_dataout OR niOli00Ol; + wire_n1liiOOi_dataout <= wire_n1lil11l_dataout OR niOli00Ol; + wire_n1liiOOl_dataout <= wire_n1lil11O_dataout AND NOT(niOli00Oi); + wire_n1liiOOO_dataout <= wire_n1lil10i_dataout OR niOli00Oi; + wire_n1lil00i_dataout <= wire_n1lil0il_dataout OR niOli0i1i; + wire_n1lil00l_dataout <= wire_n1lil0iO_dataout OR niOli0i1i; + wire_n1lil00O_dataout <= wire_n1lil0li_o(1) WHEN wire_w_lg_niOli0iOi19465w(0) = '1' ELSE n1l000OO; + wire_n1lil01l_dataout <= wire_n1lil00O_dataout AND NOT(niOli0i1i); + wire_n1lil01O_dataout <= wire_n1lil0ii_dataout OR niOli0i1i; + wire_n1lil0i_dataout <= nlOiliii AND NOT(niOO00l0l); + wire_n1lil0ii_dataout <= wire_n1lil0li_o(2) WHEN wire_w_lg_niOli0iOi19465w(0) = '1' ELSE n1l00i1i; + wire_n1lil0il_dataout <= wire_n1lil0li_o(3) WHEN wire_w_lg_niOli0iOi19465w(0) = '1' ELSE n1l00i1l; + wire_n1lil0iO_dataout <= wire_n1lil0li_o(4) WHEN wire_w_lg_niOli0iOi19465w(0) = '1' ELSE n1l00i1O; + wire_n1lil0l_dataout <= n1l011i AND NOT(niOO00l0l); + wire_n1lil0O_dataout <= n1l011l OR niOO00l0l; + wire_n1lil0OO_dataout <= wire_n1lili1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lil10i_dataout <= wire_n1lil1lO_o(1) WHEN niOli00lO = '1' ELSE wire_n1lil1il_dataout; + wire_n1lil10l_dataout <= wire_n1lil1lO_o(2) WHEN niOli00lO = '1' ELSE wire_n1lil1iO_dataout; + wire_n1lil10O_dataout <= wire_n1lil1lO_o(3) WHEN niOli00lO = '1' ELSE wire_n1lil1li_dataout; + wire_n1lil11i_dataout <= wire_n1lil10l_dataout OR niOli00Oi; + wire_n1lil11l_dataout <= wire_n1lil10O_dataout AND NOT(niOli00Oi); + wire_n1lil11O_dataout <= k_conf(340) WHEN niOli00lO = '1' ELSE wire_n1lil1ii_dataout; + wire_n1lil1i_dataout <= wire_n1ll1Ol_dataout WHEN wire_nl1000i_w_lg_n1l010l4099w(0) = '1' ELSE n1l000l; + wire_n1lil1ii_dataout <= wire_n1lil1ll_o(1) WHEN wire_w_lg_niOli0ill19512w(0) = '1' ELSE n1l000ll; + wire_n1lil1il_dataout <= wire_n1lil1ll_o(2) WHEN wire_w_lg_niOli0ill19512w(0) = '1' ELSE n1l000lO; + wire_n1lil1iO_dataout <= wire_n1lil1ll_o(3) WHEN wire_w_lg_niOli0ill19512w(0) = '1' ELSE n1l000Oi; + wire_n1lil1l_dataout <= n1l010l AND NOT(niOO00l0l); + wire_n1lil1li_dataout <= wire_n1lil1ll_o(4) WHEN wire_w_lg_niOli0ill19512w(0) = '1' ELSE n1l000Ol; + wire_n1lil1O_dataout <= niOO00lli WHEN niOO00l0l = '1' ELSE n1l010O; + wire_n1lili0O_dataout <= wire_n1liliii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lili1i_dataout <= wire_n1lili1l_dataout AND NOT(n11O0lll); + wire_n1lili1l_dataout <= wire_n1lili1O_dataout OR (wire_n1l1Ol0O_dataout AND niOli0lli); + wire_n1lili1O_dataout <= n1l00i0i AND NOT(n1lillll); + wire_n1lilii_dataout <= n1l011O AND NOT(niOO00l0l); + wire_n1liliii_dataout <= wire_n1liliil_dataout OR (niOli0i1O AND niOli0i1l); + wire_n1liliil_dataout <= n1lil0Ol AND NOT((n1lillOi AND niOli0l1i)); + wire_n1lilil_dataout <= wire_nlll0lli_q(64) WHEN niOO00l0l = '1' ELSE n1l01il; + wire_n1liliO_dataout <= wire_nlll0lli_q(65) WHEN niOO00l0l = '1' ELSE n1l01iO; + wire_n1lilli_dataout <= wire_nlll0lli_q(66) WHEN niOO00l0l = '1' ELSE n1l01li; + wire_n1lilll_dataout <= wire_nlll0lli_q(67) WHEN niOO00l0l = '1' ELSE n1l01ll; + wire_n1lillO_dataout <= wire_nlll0lli_q(68) WHEN niOO00l0l = '1' ELSE n1l01lO; + wire_n1lilOi_dataout <= wire_nlll0lli_q(69) WHEN niOO00l0l = '1' ELSE n1l01Oi; + wire_n1lilOiO_dataout <= wire_n1liOi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lilOl_dataout <= wire_nlll0lli_q(70) WHEN niOO00l0l = '1' ELSE n1l01Ol; + wire_n1lilOli_dataout <= wire_n1lllllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lilOll_dataout <= wire_n1liOi0i_dataout OR wire_niO01lOO_dataout; + wire_n1lilOlO_dataout <= wire_n1liOi0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lilOO_dataout <= wire_nlll0lli_q(71) WHEN niOO00l0l = '1' ELSE n1l01OO; + wire_n1lilOOi_dataout <= wire_n1liOi0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lilOOl_dataout <= wire_n1liOiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lilOOO_dataout <= wire_n1liO0ll_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO00i_dataout <= wire_n1liOlii_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO00l_dataout <= wire_n1liOlil_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO00O_dataout <= wire_n1liOliO_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO01i_dataout <= wire_n1liOl0i_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO01l_dataout <= wire_n1liOl0l_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO01O_dataout <= wire_n1liOl0O_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO0i_dataout <= wire_nlll0lli_q(94) WHEN niOO00l0l = '1' ELSE n1l00ii; + wire_n1liO0ii_dataout <= wire_n1liOlll_o OR wire_niO01lOO_dataout; + wire_n1liO0O_dataout <= wire_n1liOii_dataout OR ((wire_n1liOli_dataout OR wire_nlll0lli_q(131)) AND n1l011l); + wire_n1liO0Ol_dataout <= wire_n1ll0llO_dataout WHEN n1lilO0l = '1' ELSE n1lill1O; + wire_n1liO0OO_dataout <= wire_n1ll0lOi_dataout WHEN n1lilO0l = '1' ELSE n1lill0i; + wire_n1liO10i_dataout <= wire_n1liOi1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1liO10l_dataout <= wire_n1liOi1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1liO10O_dataout <= wire_n1liOiil_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO11i_dataout <= wire_n1liO0lO_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO11l_dataout <= wire_n1liO0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1liO11O_dataout <= wire_n1liO0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1liO1i_dataout <= wire_nlll0lli_q(72) WHEN niOO00l0l = '1' ELSE n1l001i; + wire_n1liO1ii_dataout <= wire_n1liO0il_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO1il_dataout <= n1lilO0l AND NOT(wire_niO01lOO_dataout); + wire_n1liO1iO_dataout <= wire_n1liOili_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO1l_dataout <= wire_nlll0lli_q(73) WHEN niOO00l0l = '1' ELSE n1l001l; + wire_n1liO1li_dataout <= wire_n1liOill_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO1ll_dataout <= wire_n1liOilO_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO1lO_dataout <= wire_n1liOiOi_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO1O_dataout <= (NOT wire_nlll0lli_q(93)) WHEN niOO00l0l = '1' ELSE n1l000O; + wire_n1liO1Oi_dataout <= wire_n1liOiOl_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO1Ol_dataout <= wire_n1liOiOO_o AND NOT(wire_niO01lOO_dataout); + wire_n1liO1OO_dataout <= wire_n1liOl1O_o AND NOT(wire_niO01lOO_dataout); + wire_n1liOi0i_dataout <= wire_n1ll0O1l_dataout WHEN n1lilO0l = '1' ELSE n1lililO; + wire_n1liOi0l_dataout <= wire_n1ll0O1O_dataout WHEN n1lilO0l = '1' ELSE n1liliOi; + wire_n1liOi0O_dataout <= wire_n1ll0O0i_dataout WHEN n1lilO0l = '1' ELSE n1liliOl; + wire_n1liOi1i_dataout <= wire_n1ll0lOl_dataout WHEN n1lilO0l = '1' ELSE n1lill0l; + wire_n1liOi1l_dataout <= wire_n1ll0lOO_dataout WHEN n1lilO0l = '1' ELSE n1lill0O; + wire_n1liOi1O_dataout <= wire_n1ll0O1i_dataout WHEN n1lilO0l = '1' ELSE n1lili0l; + wire_n1liOii_dataout <= n1l010i AND niOO00llO; + wire_n1liOiii_dataout <= wire_n1ll0O0l_dataout WHEN n1lilO0l = '1' ELSE n1liliOO; + wire_n1liOli_dataout <= wire_n1liOll_dataout OR (wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_nl1000i_w_lg_n1l011i4082w(0)); + wire_n1liOli_w_lg_dataout4044w(0) <= NOT wire_n1liOli_dataout; + wire_n1liOll_dataout <= wire_n1liOlO_dataout OR wire_w_lg_w_k_hip_range2413w4081w(0); + wire_n1liOlO_dataout <= wire_n1liOOi_dataout OR wire_w_lg_w_k_hip_range2413w4079w(0); + wire_n1liOlOl_dataout <= n1lilOil AND NOT(niOli0iiO); + wire_n1liOlOO_dataout <= n1lilliO AND NOT(niOli0iiO); + wire_n1liOO0i_dataout <= n1lillOi AND NOT(niOli0iiO); + wire_n1liOO0l_dataout <= n1lillOl AND NOT(niOli0iiO); + wire_n1liOO0O_dataout <= n1lillOO AND NOT(niOli0iiO); + wire_n1liOO1i_dataout <= n1lillli AND NOT(niOli0iiO); + wire_n1liOO1l_dataout <= n1lillll AND NOT(niOli0iiO); + wire_n1liOO1O_dataout <= n1lilllO AND NOT(niOli0iiO); + wire_n1liOOi_dataout <= wire_n1liOOl_dataout OR wire_w_lg_w_k_hip_range2413w4077w(0); + wire_n1liOOii_dataout <= n1lilO1i AND NOT(niOli0iiO); + wire_n1liOOil_dataout <= n1lilO1l AND NOT(niOli0iiO); + wire_n1liOOiO_dataout <= n1lilO1O AND NOT(niOli0iiO); + wire_n1liOOl_dataout <= (wire_nlll0lli_q(131) AND wire_nlll0lli_q(128)) OR (wire_w_lg_w_k_hip_range2413w2429w(0) AND (wire_nl1000i_w_lg_nlOiliii4069w(0) AND wire_nlll0lli_q(129))); + wire_n1liOOli_dataout <= n1lilO0i AND NOT(niOli0iiO); + wire_n1liOOll_dataout <= n1lilO0l OR niOli0iiO; + wire_n1liOOlO_dataout <= n1lilO0O AND NOT(niOli0iiO); + wire_n1liOOOi_dataout <= n1lilOil WHEN niOli0ili = '1' ELSE wire_n1ll11Oi_dataout; + wire_n1liOOOl_dataout <= n1lilliO WHEN niOli0ili = '1' ELSE wire_n1ll11Ol_dataout; + wire_n1liOOOO_dataout <= n1lillli WHEN niOli0ili = '1' ELSE wire_n1ll11OO_dataout; + wire_n1ll000i_dataout <= n1lilO1l WHEN niOli0iOO = '1' ELSE wire_n1ll0i0O_dataout; + wire_n1ll000l_dataout <= n1lilO1O WHEN niOli0iOO = '1' ELSE wire_n1ll0iii_dataout; + wire_n1ll000O_dataout <= n1lilO0i WHEN niOli0iOO = '1' ELSE wire_n1ll0iil_dataout; + wire_n1ll001i_dataout <= n1lillOl WHEN niOli0iOO = '1' ELSE wire_n1ll0i1O_dataout; + wire_n1ll001l_dataout <= n1lillOO WHEN niOli0iOO = '1' ELSE wire_n1ll0i0i_dataout; + wire_n1ll001O_dataout <= n1lilO1i WHEN niOli0iOO = '1' ELSE wire_n1ll0i0l_dataout; + wire_n1ll00ii_dataout <= n1lilO0l WHEN niOli0iOO = '1' ELSE wire_n1ll0iiO_dataout; + wire_n1ll00il_dataout <= n1lilO0O WHEN niOli0iOO = '1' ELSE wire_n1ll0ili_dataout; + wire_n1ll00iO_dataout <= n1lillii AND NOT(niOli0iOO); + wire_n1ll00l_dataout <= wire_n1ll00O_dataout OR ((wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_w_lg_w_lg_niOO00llO4046w4048w(0)) AND (wire_nl11llO_w_lg_n1l011O4051w(0) OR wire_nl11llO_w_lg_n1l011O4055w(0))); + wire_n1ll00li_dataout <= wire_niO01ill_w_lg_n1lillii18973w(0) WHEN niOli0iOO = '1' ELSE wire_n1ll00ll_dataout; + wire_n1ll00ll_dataout <= n1lillil AND NOT(niOli0l1i); + wire_n1ll00lO_dataout <= n1lilOil AND NOT(niOli0l1i); + wire_n1ll00O_dataout <= ((wire_w_lg_niOO00llO4041w(0) AND wire_nl1000i_w_lg_n1l010i4042w(0)) AND wire_n1liOli_w_lg_dataout4044w(0)) OR (wire_w_lg_w_k_hip_range2413w4049w(0) AND wire_nl11llO_w_lg_w_lg_n1l011O4051w4052w(0)); + wire_n1ll00Oi_dataout <= n1lilliO AND NOT(niOli0l1i); + wire_n1ll00Ol_dataout <= n1lillli AND NOT(niOli0l1i); + wire_n1ll00OO_dataout <= n1lillll AND NOT(niOli0l1i); + wire_n1ll011i_dataout <= n1lilO0O AND NOT(niOli0iOl); + wire_n1ll01i_dataout <= nlOi111O WHEN wire_w_lg_w_k_hip_range2413w4061w(0) = '1' ELSE nlOi1i0l; + wire_n1ll01li_dataout <= n1lilOil WHEN niOli0iOO = '1' ELSE wire_n1ll00lO_dataout; + wire_n1ll01ll_dataout <= n1lilliO WHEN niOli0iOO = '1' ELSE wire_n1ll00Oi_dataout; + wire_n1ll01lO_dataout <= n1lillli WHEN niOli0iOO = '1' ELSE wire_n1ll00Ol_dataout; + wire_n1ll01Oi_dataout <= n1lillll WHEN niOli0iOO = '1' ELSE wire_n1ll00OO_dataout; + wire_n1ll01Ol_dataout <= n1lilllO WHEN niOli0iOO = '1' ELSE wire_n1ll0i1i_dataout; + wire_n1ll01OO_dataout <= n1lillOi WHEN niOli0iOO = '1' ELSE wire_n1ll0i1l_dataout; + wire_n1ll0i0i_dataout <= n1lillOO AND NOT(niOli0l1i); + wire_n1ll0i0l_dataout <= n1lilO1i AND NOT(niOli0l1i); + wire_n1ll0i0O_dataout <= n1lilO1l AND NOT(niOli0l1i); + wire_n1ll0i1i_dataout <= n1lilllO AND NOT(niOli0l1i); + wire_n1ll0i1l_dataout <= n1lillOi AND NOT(niOli0l1i); + wire_n1ll0i1O_dataout <= n1lillOl AND NOT(niOli0l1i); + wire_n1ll0iii_dataout <= n1lilO1O AND NOT(niOli0l1i); + wire_n1ll0iil_dataout <= n1lilO0i AND NOT(niOli0l1i); + wire_n1ll0iiO_dataout <= n1lilO0l OR niOli0l1i; + wire_n1ll0ili_dataout <= n1lilO0O AND NOT(niOli0l1i); + wire_n1ll0ill_dataout <= n1lilOil AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0ilO_dataout <= n1lilliO AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0iOi_dataout <= n1lillli AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0iOl_dataout <= n1lillll AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0iOO_dataout <= n1lilllO AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0l0i_dataout <= n1lilO1i AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0l0l_dataout <= n1lilO1l AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0l0O_dataout <= n1lilO1O AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0l1i_dataout <= n1lillOi OR wire_niO01ill_w_lg_n1lO0lOi9962w(0); + wire_n1ll0l1l_dataout <= n1lillOl AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0l1O_dataout <= n1lillOO AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0lii_dataout <= n1lilO0i AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0lil_dataout <= n1lilO0l AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0liO_dataout <= n1lilO0O AND NOT(wire_niO01ill_w_lg_n1lO0lOi9962w(0)); + wire_n1ll0lli_dataout <= n1lill1i WHEN niOli0lll = '1' ELSE wire_n1lli11l_dataout; + wire_n1ll0lll_dataout <= n1lill1l WHEN niOli0lll = '1' ELSE wire_n1lli11O_dataout; + wire_n1ll0llO_dataout <= n1lill1O WHEN niOli0lll = '1' ELSE wire_n1lli10i_dataout; + wire_n1ll0lOi_dataout <= n1lill0i WHEN niOli0lll = '1' ELSE wire_n1lli10l_dataout; + wire_n1ll0lOl_dataout <= n1lill0l WHEN niOli0lll = '1' ELSE wire_n1lli10O_dataout; + wire_n1ll0lOO_dataout <= n1lill0O WHEN niOli0lll = '1' ELSE wire_n1lli1ii_dataout; + wire_n1ll0O0i_dataout <= n1liliOl WHEN niOli0lll = '1' ELSE wire_n1lli00i_dataout; + wire_n1ll0O0l_dataout <= n1liliOO WHEN niOli0lll = '1' ELSE wire_n1lli00l_dataout; + wire_n1ll0O0O_dataout <= wire_n1llll1O_dataout WHEN niOli0lll = '1' ELSE n1lillii; + wire_n1ll0O1i_dataout <= n1lili0l WHEN niOli0lll = '1' ELSE wire_n1lli01i_dataout; + wire_n1ll0O1l_dataout <= n1lililO WHEN niOli0lll = '1' ELSE wire_n1lli01l_dataout; + wire_n1ll0O1O_dataout <= n1liliOi WHEN niOli0lll = '1' ELSE wire_n1lli01O_dataout; + wire_n1ll0Oii_dataout <= wire_n1lli1il_dataout AND NOT(niOli0lll); + wire_n1ll0Oil_dataout <= wire_n1lli1iO_dataout AND NOT(niOli0lll); + wire_n1ll0OiO_dataout <= wire_n1lli1li_dataout AND NOT(niOli0lll); + wire_n1ll0Oli_dataout <= wire_n1lli1ll_dataout AND NOT(niOli0lll); + wire_n1ll0Oll_dataout <= wire_n1lli1lO_dataout AND NOT(niOli0lll); + wire_n1ll0OlO_dataout <= wire_niO01ill_w_lg_n1lO0lOi9962w(0) AND niOli0lll; + wire_n1ll0OOi_dataout <= wire_n1lli1Oi_dataout AND NOT(niOli0lll); + wire_n1ll0OOl_dataout <= wire_n1lli1Ol_dataout AND NOT(niOli0lll); + wire_n1ll0OOO_dataout <= wire_n1lli1OO_dataout AND NOT(niOli0lll); + wire_n1ll100i_dataout <= n1lillOl AND NOT(niOli0ill); + wire_n1ll100l_dataout <= n1lillOO AND NOT(niOli0ill); + wire_n1ll100O_dataout <= n1lilO1i AND NOT(niOli0ill); + wire_n1ll101i_dataout <= n1lillll AND NOT(niOli0ill); + wire_n1ll101l_dataout <= n1lilllO AND NOT(niOli0ill); + wire_n1ll101O_dataout <= n1lillOi AND NOT(niOli0ill); + wire_n1ll10ii_dataout <= n1lilO1l AND NOT(niOli0ill); + wire_n1ll10il_dataout <= n1lilO1O AND NOT(niOli0ill); + wire_n1ll10iO_dataout <= n1lilO0i AND NOT(niOli0ill); + wire_n1ll10li_dataout <= n1lilO0l OR niOli0ill; + wire_n1ll10ll_dataout <= n1lilO0O AND NOT(niOli0ill); + wire_n1ll10lO_dataout <= n1lillil AND NOT(niOli0ill); + wire_n1ll10Oi_dataout <= n1lill1i WHEN niOli0ilO = '1' ELSE wire_n1ll1l1i_dataout; + wire_n1ll10Ol_dataout <= n1lill1l WHEN niOli0ilO = '1' ELSE wire_n1ll1l1l_dataout; + wire_n1ll10OO_dataout <= n1lilOil WHEN niOli0ilO = '1' ELSE wire_n1ll1l1O_dataout; + wire_n1ll110i_dataout <= n1lillOl WHEN niOli0ili = '1' ELSE wire_n1ll100i_dataout; + wire_n1ll110l_dataout <= n1lillOO WHEN niOli0ili = '1' ELSE wire_n1ll100l_dataout; + wire_n1ll110O_dataout <= n1lilO1i WHEN niOli0ili = '1' ELSE wire_n1ll100O_dataout; + wire_n1ll111i_dataout <= n1lillll WHEN niOli0ili = '1' ELSE wire_n1ll101i_dataout; + wire_n1ll111l_dataout <= n1lilllO WHEN niOli0ili = '1' ELSE wire_n1ll101l_dataout; + wire_n1ll111O_dataout <= n1lillOi WHEN niOli0ili = '1' ELSE wire_n1ll101O_dataout; + wire_n1ll11ii_dataout <= n1lilO1l WHEN niOli0ili = '1' ELSE wire_n1ll10ii_dataout; + wire_n1ll11il_dataout <= n1lilO1O WHEN niOli0ili = '1' ELSE wire_n1ll10il_dataout; + wire_n1ll11iO_dataout <= n1lilO0i WHEN niOli0ili = '1' ELSE wire_n1ll10iO_dataout; + wire_n1ll11li_dataout <= n1lilO0l WHEN niOli0ili = '1' ELSE wire_n1ll10li_dataout; + wire_n1ll11ll_dataout <= n1lilO0O WHEN niOli0ili = '1' ELSE wire_n1ll10ll_dataout; + wire_n1ll11lO_dataout <= wire_n1ll10lO_dataout OR niOli0ili; + wire_n1ll11Oi_dataout <= n1lilOil AND NOT(niOli0ill); + wire_n1ll11Ol_dataout <= n1lilliO AND NOT(niOli0ill); + wire_n1ll11OO_dataout <= n1lillli AND NOT(niOli0ill); + wire_n1ll1i0i_dataout <= n1lilllO WHEN niOli0ilO = '1' ELSE wire_n1ll1lii_dataout; + wire_n1ll1i0l_dataout <= n1lillOi WHEN niOli0ilO = '1' ELSE wire_n1ll1lil_dataout; + wire_n1ll1i0O_dataout <= n1lillOl WHEN niOli0ilO = '1' ELSE wire_n1ll1liO_dataout; + wire_n1ll1i1i_dataout <= n1lilliO WHEN niOli0ilO = '1' ELSE wire_n1ll1l0i_dataout; + wire_n1ll1i1l_dataout <= n1lillli WHEN niOli0ilO = '1' ELSE wire_n1ll1l0l_dataout; + wire_n1ll1i1O_dataout <= n1lillll WHEN niOli0ilO = '1' ELSE wire_n1ll1l0O_dataout; + wire_n1ll1iii_dataout <= n1lillOO WHEN niOli0ilO = '1' ELSE wire_n1ll1lli_dataout; + wire_n1ll1iil_dataout <= n1lilO1i WHEN niOli0ilO = '1' ELSE wire_n1ll1lll_dataout; + wire_n1ll1iiO_dataout <= n1lilO1l WHEN niOli0ilO = '1' ELSE wire_n1ll1llO_dataout; + wire_n1ll1ili_dataout <= n1lilO1O WHEN niOli0ilO = '1' ELSE wire_n1ll1lOi_dataout; + wire_n1ll1ill_dataout <= n1lilO0i WHEN niOli0ilO = '1' ELSE wire_n1ll1lOl_dataout; + wire_n1ll1ilO_dataout <= n1lilO0l WHEN niOli0ilO = '1' ELSE wire_n1ll1lOO_dataout; + wire_n1ll1iOi_dataout <= n1lilO0O WHEN niOli0ilO = '1' ELSE wire_n1ll1O1i_dataout; + wire_n1ll1iOl_dataout <= wire_n1ll1iOO_dataout OR niOli0ilO; + wire_n1ll1iOO_dataout <= n1lillil AND NOT(niOli0iOi); + wire_n1ll1l0i_dataout <= n1lilliO AND NOT(niOli0iOi); + wire_n1ll1l0l_dataout <= n1lillli AND NOT(niOli0iOi); + wire_n1ll1l0O_dataout <= n1lillll AND NOT(niOli0iOi); + wire_n1ll1l1i_dataout <= n11i111i WHEN niOli0iOi = '1' ELSE n1lill1i; + wire_n1ll1l1l_dataout <= n11i111l WHEN niOli0iOi = '1' ELSE n1lill1l; + wire_n1ll1l1O_dataout <= n1lilOil AND NOT(niOli0iOi); + wire_n1ll1lii_dataout <= n1lilllO AND NOT(niOli0iOi); + wire_n1ll1lil_dataout <= n1lillOi AND NOT(niOli0iOi); + wire_n1ll1liO_dataout <= n1lillOl AND NOT(niOli0iOi); + wire_n1ll1lli_dataout <= n1lillOO AND NOT(niOli0iOi); + wire_n1ll1lll_dataout <= n1lilO1i AND NOT(niOli0iOi); + wire_n1ll1llO_dataout <= n1lilO1l AND NOT(niOli0iOi); + wire_n1ll1lOi_dataout <= n1lilO1O AND NOT(niOli0iOi); + wire_n1ll1lOl_dataout <= n1lilO0i AND NOT(niOli0iOi); + wire_n1ll1lOO_dataout <= n1lilO0l OR niOli0iOi; + wire_n1ll1O0i_dataout <= n1lilliO AND NOT(niOli0iOl); + wire_n1ll1O0l_dataout <= n1lillli AND NOT(niOli0iOl); + wire_n1ll1O0O_dataout <= n1lillll AND NOT(niOli0iOl); + wire_n1ll1O1i_dataout <= n1lilO0O AND NOT(niOli0iOi); + wire_n1ll1O1l_dataout <= n1lillil OR niOli0iOl; + wire_n1ll1O1O_dataout <= n1lilOil AND NOT(niOli0iOl); + wire_n1ll1Oii_dataout <= n1lilllO AND NOT(niOli0iOl); + wire_n1ll1Oil_dataout <= n1lillOi AND NOT(niOli0iOl); + wire_n1ll1OiO_dataout <= n1lillOl AND NOT(niOli0iOl); + wire_n1ll1Ol_dataout <= wire_nlll0lli_q(66) WHEN niOO00liO = '1' ELSE wire_n1ll1OO_dataout; + wire_n1ll1Ol_w_lg_w_lg_dataout4106w4107w(0) <= wire_n1ll1Ol_w_lg_dataout4106w(0) AND nlOili0l; + wire_n1ll1Ol_w_lg_w_lg_dataout4108w4109w(0) <= wire_n1ll1Ol_w_lg_dataout4108w(0) AND n1l000O; + wire_n1ll1Ol_w_lg_dataout4106w(0) <= wire_n1ll1Ol_dataout AND n1l000O; + wire_n1ll1Ol_w_lg_dataout4108w(0) <= NOT wire_n1ll1Ol_dataout; + wire_n1ll1Oli_dataout <= n1lillOO AND NOT(niOli0iOl); + wire_n1ll1Oll_dataout <= n1lilO1i OR niOli0iOl; + wire_n1ll1OlO_dataout <= n1lilO1l AND NOT(niOli0iOl); + wire_n1ll1OO_dataout <= wire_nlll0lli_q(98) WHEN (wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_nl1000i_w_lg_n1l000O4060w(0)) = '1' ELSE wire_n1ll01i_dataout; + wire_n1ll1OOi_dataout <= n1lilO1O AND NOT(niOli0iOl); + wire_n1ll1OOl_dataout <= n1lilO0i AND NOT(niOli0iOl); + wire_n1ll1OOO_dataout <= n1lilO0l AND NOT(niOli0iOl); + wire_n1lli00i_dataout <= wire_n1lli0ll_dataout AND NOT(niOli0liO); + wire_n1lli00l_dataout <= n11li1il WHEN niOli0liO = '1' ELSE wire_n1lli0lO_dataout; + wire_n1lli00O_dataout <= n1lill1i WHEN niOli0lOl = '1' ELSE wire_n1lliiiO_dataout; + wire_n1lli01i_dataout <= n11O01li WHEN niOli0liO = '1' ELSE wire_n1lli0il_dataout; + wire_n1lli01l_dataout <= wire_n1lli0iO_dataout OR niOli0liO; + wire_n1lli01O_dataout <= niOO10l1i WHEN niOli0liO = '1' ELSE wire_n1lli0li_dataout; + wire_n1lli0ii_dataout <= n1lill1l WHEN niOli0lOl = '1' ELSE wire_n1lliili_dataout; + wire_n1lli0il_dataout <= n1lili0l WHEN niOli0lOl = '1' ELSE wire_n1lliill_dataout; + wire_n1lli0iO_dataout <= n1lililO WHEN niOli0lOl = '1' ELSE wire_n1lliilO_dataout; + wire_n1lli0li_dataout <= n1liliOi WHEN niOli0lOl = '1' ELSE wire_n1lliiOi_dataout; + wire_n1lli0ll_dataout <= n1liliOl WHEN niOli0lOl = '1' ELSE wire_n1lliiOl_dataout; + wire_n1lli0lO_dataout <= n1liliOO WHEN niOli0lOl = '1' ELSE wire_n1lliiOO_dataout; + wire_n1lli0Oi_dataout <= n1lill1O WHEN niOli0lOl = '1' ELSE wire_n1llil1i_dataout; + wire_n1lli0Ol_dataout <= n1lill0i WHEN niOli0lOl = '1' ELSE wire_n1llil1l_dataout; + wire_n1lli0OO_dataout <= n1lill0l WHEN niOli0lOl = '1' ELSE wire_n1llil1O_dataout; + wire_n1lli10i_dataout <= n1lill1O WHEN niOli0liO = '1' ELSE wire_n1lli0Oi_dataout; + wire_n1lli10l_dataout <= n1lill0i WHEN niOli0liO = '1' ELSE wire_n1lli0Ol_dataout; + wire_n1lli10O_dataout <= n1lill0l WHEN niOli0liO = '1' ELSE wire_n1lli0OO_dataout; + wire_n1lli11i_dataout <= n1lO0lOi AND niOli0lll; + wire_n1lli11l_dataout <= n1lill1i WHEN niOli0liO = '1' ELSE wire_n1lli00O_dataout; + wire_n1lli11O_dataout <= n1lill1l WHEN niOli0liO = '1' ELSE wire_n1lli0ii_dataout; + wire_n1lli1ii_dataout <= n1lill0O WHEN niOli0liO = '1' ELSE wire_n1llii1i_dataout; + wire_n1lli1il_dataout <= wire_n1llii1l_dataout AND NOT(niOli0liO); + wire_n1lli1iO_dataout <= wire_n1llii1O_dataout AND NOT(niOli0liO); + wire_n1lli1li_dataout <= wire_n1llii0i_dataout AND NOT(niOli0liO); + wire_n1lli1ll_dataout <= wire_n1llii0l_dataout AND NOT(niOli0liO); + wire_n1lli1lO_dataout <= wire_n1llii0O_dataout AND NOT(niOli0liO); + wire_n1lli1Oi_dataout <= wire_n1lliiii_dataout AND NOT(niOli0liO); + wire_n1lli1Ol_dataout <= niOli0lOl AND NOT(niOli0liO); + wire_n1lli1OO_dataout <= wire_n1lliiil_dataout OR niOli0liO; + wire_n1llii0i_dataout <= wire_n1llilii_dataout AND NOT(niOli0lOl); + wire_n1llii0l_dataout <= wire_n1llilil_dataout AND NOT(niOli0lOl); + wire_n1llii0O_dataout <= wire_n1lliliO_dataout AND NOT(niOli0lOl); + wire_n1llii1i_dataout <= n1lill0O WHEN niOli0lOl = '1' ELSE wire_n1llil0i_dataout; + wire_n1llii1l_dataout <= wire_n1llil0l_dataout AND NOT(niOli0lOl); + wire_n1llii1O_dataout <= wire_n1llil0O_dataout AND NOT(niOli0lOl); + wire_n1lliiii_dataout <= wire_n1llilli_dataout AND NOT(niOli0lOl); + wire_n1lliiil_dataout <= wire_n1llilll_dataout AND NOT(niOli0lOl); + wire_n1lliiiO_dataout <= n1lill1i WHEN niOli0lOO = '1' ELSE wire_n1llillO_dataout; + wire_n1lliili_dataout <= n1lill1l WHEN niOli0lOO = '1' ELSE wire_n1llilOi_dataout; + wire_n1lliill_dataout <= n1lili0l WHEN niOli0lOO = '1' ELSE wire_n1lliO0l_dataout; + wire_n1lliilO_dataout <= n1lililO WHEN niOli0lOO = '1' ELSE wire_n1lliO0O_dataout; + wire_n1lliiOi_dataout <= n1liliOi WHEN niOli0lOO = '1' ELSE wire_n1lliOii_dataout; + wire_n1lliiOl_dataout <= n1liliOl WHEN niOli0lOO = '1' ELSE wire_n1lliOil_dataout; + wire_n1lliiOO_dataout <= n1liliOO WHEN niOli0lOO = '1' ELSE wire_n1lliOiO_dataout; + wire_n1llil0i_dataout <= n1lill0O WHEN niOli0lOO = '1' ELSE wire_n1lliOOi_dataout; + wire_n1llil0l_dataout <= wire_n1llilOl_dataout AND NOT(niOli0lOO); + wire_n1llil0O_dataout <= wire_n1llilOO_dataout AND NOT(niOli0lOO); + wire_n1llil1i_dataout <= n1lill1O WHEN niOli0lOO = '1' ELSE wire_n1lliOli_dataout; + wire_n1llil1l_dataout <= n1lill0i WHEN niOli0lOO = '1' ELSE wire_n1lliOll_dataout; + wire_n1llil1O_dataout <= n1lill0l WHEN niOli0lOO = '1' ELSE wire_n1lliOlO_dataout; + wire_n1llilii_dataout <= wire_n1lliO1i_dataout AND NOT(niOli0lOO); + wire_n1llilil_dataout <= wire_n1lliO1l_dataout AND NOT(niOli0lOO); + wire_n1lliliO_dataout <= wire_n1lliO1O_dataout AND NOT(niOli0lOO); + wire_n1llill_dataout <= wire_n1lliOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1llilli_dataout <= wire_n1lliO0i_dataout OR niOli0lOO; + wire_n1llilll_dataout <= niOli0l1l AND NOT(niOli0lOO); + wire_n1llillO_dataout <= n1lill1i WHEN niOli0l1l = '1' ELSE wire_n1lll11O_dataout; + wire_n1llilO_dataout <= wire_n1lll1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1llilOi_dataout <= n1lill1l WHEN niOli0l1l = '1' ELSE wire_n1lll10i_dataout; + wire_n1llilOl_dataout <= wire_n1lll10l_dataout AND NOT(niOli0l1l); + wire_n1llilOO_dataout <= wire_n1lll10O_dataout AND NOT(niOli0l1l); + wire_n1lliO0i_dataout <= wire_n1lll1iO_dataout AND NOT(niOli0l1l); + wire_n1lliO0l_dataout <= n11O01li WHEN niOli0l1l = '1' ELSE n1lili0l; + wire_n1lliO0O_dataout <= n1lililO OR niOli0l1l; + wire_n1lliO1i_dataout <= wire_n1lll1ii_dataout AND NOT(niOli0l1l); + wire_n1lliO1l_dataout <= wire_n1lll1il_dataout AND NOT(niOli0l1l); + wire_n1lliO1O_dataout <= niOli0l1O AND NOT(niOli0l1l); + wire_n1lliOi_dataout <= wire_n1lllli_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1lliOii_dataout <= niOO10l1i WHEN niOli0l1l = '1' ELSE n1liliOi; + wire_n1lliOil_dataout <= n1liliOl AND NOT(niOli0l1l); + wire_n1lliOiO_dataout <= n11li1il WHEN niOli0l1l = '1' ELSE n1liliOO; + wire_n1lliOl_dataout <= wire_n1lllll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1lliOli_dataout <= n110OOOO WHEN niOli0l1l = '1' ELSE wire_n1lliOOl_dataout; + wire_n1lliOll_dataout <= n11i111i WHEN niOli0l1l = '1' ELSE wire_n1lliOOO_dataout; + wire_n1lliOlO_dataout <= n11i111l WHEN niOli0l1l = '1' ELSE wire_n1lll11i_dataout; + wire_n1lliOO_dataout <= niOO00O1l WHEN niOO00lOl = '1' ELSE wire_n1lll1l_dataout; + wire_n1lliOOi_dataout <= n11i111O WHEN niOli0l1l = '1' ELSE wire_n1lll11l_dataout; + wire_n1lliOOl_dataout <= n1lill1O WHEN niOli0l1O = '1' ELSE wire_n1lll1li_dataout; + wire_n1lliOOO_dataout <= n1lill0i WHEN niOli0l1O = '1' ELSE wire_n1lll1ll_dataout; + wire_n1lll00i_dataout <= wire_n1lll0Oi_dataout AND NOT(niOli0lli); + wire_n1lll00l_dataout <= n1lill1O WHEN niOli0l0i = '1' ELSE wire_n1lll0Ol_dataout; + wire_n1lll00O_dataout <= n1lill0i WHEN niOli0l0i = '1' ELSE wire_n1lll0OO_dataout; + wire_n1lll01i_dataout <= wire_n1lll0ll_dataout AND NOT(niOli0lli); + wire_n1lll01l_dataout <= wire_n1lll0lO_dataout AND NOT(niOli0lli); + wire_n1lll01O_dataout <= niOli0l0i AND NOT(niOli0lli); + wire_n1lll0ii_dataout <= n1lill0l WHEN niOli0l0i = '1' ELSE wire_n1llli1i_dataout; + wire_n1lll0il_dataout <= n1lill0O WHEN niOli0l0i = '1' ELSE wire_n1llli1l_dataout; + wire_n1lll0iO_dataout <= n1lill1i WHEN niOli0l0i = '1' ELSE wire_n1llli1O_dataout; + wire_n1lll0li_dataout <= n1lill1l WHEN niOli0l0i = '1' ELSE wire_n1llli0i_dataout; + wire_n1lll0ll_dataout <= wire_n1llli0l_dataout AND NOT(niOli0l0i); + wire_n1lll0lO_dataout <= niOli0l0l AND NOT(niOli0l0i); + wire_n1lll0Oi_dataout <= wire_n1llli0O_dataout AND NOT(niOli0l0i); + wire_n1lll0Ol_dataout <= n1lill1O WHEN niOli0l0l = '1' ELSE wire_n1llliii_dataout; + wire_n1lll0OO_dataout <= n1lill0i WHEN niOli0l0l = '1' ELSE wire_n1llliil_dataout; + wire_n1lll10i_dataout <= n1lill1l WHEN niOli0l1O = '1' ELSE wire_n1lll1OO_dataout; + wire_n1lll10l_dataout <= wire_n1lll01i_dataout AND NOT(niOli0l1O); + wire_n1lll10O_dataout <= wire_n1lll01l_dataout AND NOT(niOli0l1O); + wire_n1lll11i_dataout <= n1lill0l WHEN niOli0l1O = '1' ELSE wire_n1lll1lO_dataout; + wire_n1lll11l_dataout <= n1lill0O WHEN niOli0l1O = '1' ELSE wire_n1lll1Oi_dataout; + wire_n1lll11O_dataout <= n1lill1i WHEN niOli0l1O = '1' ELSE wire_n1lll1Ol_dataout; + wire_n1lll1i_dataout <= niOO00O0i WHEN niOO00lOl = '1' ELSE wire_n1lll1O_dataout; + wire_n1lll1ii_dataout <= wire_n1lll01O_dataout AND NOT(niOli0l1O); + wire_n1lll1il_dataout <= niOli0lli AND NOT(niOli0l1O); + wire_n1lll1iO_dataout <= wire_n1lll00i_dataout AND NOT(niOli0l1O); + wire_n1lll1l_dataout <= n1lliiO AND niOO00lOi; + wire_n1lll1li_dataout <= n1lill1O WHEN niOli0lli = '1' ELSE wire_n1lll00l_dataout; + wire_n1lll1ll_dataout <= n1lill0i WHEN niOli0lli = '1' ELSE wire_n1lll00O_dataout; + wire_n1lll1lO_dataout <= n1lill0l WHEN niOli0lli = '1' ELSE wire_n1lll0ii_dataout; + wire_n1lll1O_dataout <= n1llili AND niOO00lOi; + wire_n1lll1Oi_dataout <= n1lill0O WHEN niOli0lli = '1' ELSE wire_n1lll0il_dataout; + wire_n1lll1Ol_dataout <= n1lill1i WHEN niOli0lli = '1' ELSE wire_n1lll0iO_dataout; + wire_n1lll1OO_dataout <= n1lill1l WHEN niOli0lli = '1' ELSE wire_n1lll0li_dataout; + wire_n1llli0i_dataout <= n1lill1l WHEN niOli0l0l = '1' ELSE wire_n1lllilO_dataout; + wire_n1llli0l_dataout <= niOli0l0O AND NOT(niOli0l0l); + wire_n1llli0O_dataout <= wire_w_lg_niOli0l0O18972w(0) AND NOT(niOli0l0l); + wire_n1llli1i_dataout <= n1lill0l WHEN niOli0l0l = '1' ELSE wire_n1llliiO_dataout; + wire_n1llli1l_dataout <= n1lill0O WHEN niOli0l0l = '1' ELSE wire_n1lllili_dataout; + wire_n1llli1O_dataout <= n1lill1i WHEN niOli0l0l = '1' ELSE wire_n1lllill_dataout; + wire_n1llliii_dataout <= n1lill1O WHEN niOli0l0O = '1' ELSE n110OOOO; + wire_n1llliil_dataout <= n1lill0i WHEN niOli0l0O = '1' ELSE n11i111i; + wire_n1llliiO_dataout <= n1lill0l WHEN niOli0l0O = '1' ELSE n11i111l; + wire_n1lllili_dataout <= n1lill0O WHEN niOli0l0O = '1' ELSE n11i111O; + wire_n1lllill_dataout <= n1lill1i WHEN niOli0l0O = '1' ELSE wire_n1llliOi_dataout; + wire_n1lllilO_dataout <= n1lill1l WHEN niOli0l0O = '1' ELSE wire_n1llliOl_dataout; + wire_n1llliOi_dataout <= n1lill1i AND NOT(niOli0lii); + wire_n1llliOl_dataout <= n1lill1l AND NOT(niOli0lii); + wire_n1llll1O_dataout <= n1lillii OR n1l1OlOl; + wire_n1lllli_dataout <= wire_n1lllOi_dataout AND NOT(niOO00O1i); + wire_n1lllll_dataout <= wire_n1lllOl_dataout AND NOT(niOO00O1i); + wire_n1lllllO_dataout <= wire_n1llllOi_dataout AND niOli0O1l; + wire_n1llllOi_dataout <= wire_niO01ill_w_lg_n1lilill18949w(0) WHEN (((n1lilill AND wire_n1l1Ol0O_dataout) OR wire_n1l1Ol0O_w_lg_dataout18951w(0)) AND n1lilO0l) = '1' ELSE n1lilill; + wire_n1lllO0l_dataout <= n1lOOO0i WHEN n1101l1i = '1' ELSE wire_n1lllOOi_dataout; + wire_n1lllO0O_dataout <= n1lOOlli WHEN n1101l1i = '1' ELSE wire_n1lllOOl_dataout; + wire_n1lllOi_dataout <= niOO00O1l WHEN niOO00O1O = '1' ELSE n1lliiO; + wire_n1lllOii_dataout <= n1lOOl1i WHEN n1101l1i = '1' ELSE wire_n1lllOOO_dataout; + wire_n1lllOil_dataout <= n1lOOiii WHEN n1101l1i = '1' ELSE wire_n1llO11i_dataout; + wire_n1lllOiO_dataout <= n1lOO0Oi WHEN n1101l1i = '1' ELSE wire_n1llO11l_dataout; + wire_n1lllOl_dataout <= niOO00O0i WHEN niOO00O1O = '1' ELSE n1llili; + wire_n1lllOli_dataout <= n1lOO00i WHEN n1101l1i = '1' ELSE wire_n1llO11O_dataout; + wire_n1lllOll_dataout <= n1lOO1li WHEN n1101l1i = '1' ELSE wire_n1llO10i_dataout; + wire_n1lllOlO_dataout <= n1lOi0il WHEN n1101l1i = '1' ELSE wire_n1llO10l_dataout; + wire_n1lllOOi_dataout <= n1lOOO0i WHEN n1101iOO = '1' ELSE wire_n1llO10O_dataout; + wire_n1lllOOl_dataout <= n1lOOlli WHEN n1101iOO = '1' ELSE wire_n1llO1ii_dataout; + wire_n1lllOOO_dataout <= n1lOOl1i WHEN n1101iOO = '1' ELSE wire_n1llO1il_dataout; + wire_n1llO00i_dataout <= n1lOOOiO WHEN n1101l1i = '1' ELSE wire_n1lO11il_dataout; + wire_n1llO00l_dataout <= n1lOOOli WHEN n1101l1i = '1' ELSE wire_n1lO11iO_dataout; + wire_n1llO00O_dataout <= n1lOOOll WHEN n1101l1i = '1' ELSE wire_n1lO11li_dataout; + wire_n1llO01i_dataout <= n1lOOO0O WHEN n1101l1i = '1' ELSE wire_n1lO110l_dataout; + wire_n1llO01l_dataout <= n1lOOOii WHEN n1101l1i = '1' ELSE wire_n1lO110O_dataout; + wire_n1llO01O_dataout <= n1lOOOil WHEN n1101l1i = '1' ELSE wire_n1lO11ii_dataout; + wire_n1llO0ii_dataout <= n1lOOOlO WHEN n1101l1i = '1' ELSE wire_n1lO11ll_dataout; + wire_n1llO0il_dataout <= n1lOOlll WHEN n1101l1i = '1' ELSE wire_n1lO11lO_dataout; + wire_n1llO0iO_dataout <= n1lOOllO WHEN n1101l1i = '1' ELSE wire_n1lO11Oi_dataout; + wire_n1llO0li_dataout <= n1lOOlOi WHEN n1101l1i = '1' ELSE wire_n1lO11Ol_dataout; + wire_n1llO0ll_dataout <= n1lOOlOl WHEN n1101l1i = '1' ELSE wire_n1lO11OO_dataout; + wire_n1llO0lO_dataout <= n1lOOlOO WHEN n1101l1i = '1' ELSE wire_n1lO101i_dataout; + wire_n1llO0Oi_dataout <= n1lOOO1i WHEN n1101l1i = '1' ELSE wire_n1lO101l_dataout; + wire_n1llO0Ol_dataout <= n1lOOO1l WHEN n1101l1i = '1' ELSE wire_n1lO101O_dataout; + wire_n1llO0OO_dataout <= n1lOOO1O WHEN n1101l1i = '1' ELSE wire_n1lO100i_dataout; + wire_n1llO10i_dataout <= n1lOOl1i WHEN n1101iOO = '1' ELSE wire_n1llO1lO_dataout; + wire_n1llO10l_dataout <= n1lOOiii WHEN n1101iOO = '1' ELSE wire_n1llO1Oi_dataout; + wire_n1llO10O_dataout <= n1lOOO0i WHEN n1101iOl = '1' ELSE n1lOi0il; + wire_n1llO11i_dataout <= n1lOOiii WHEN n1101iOO = '1' ELSE wire_n1llO1iO_dataout; + wire_n1llO11l_dataout <= n1lOOO0i WHEN n1101iOO = '1' ELSE wire_n1llO1li_dataout; + wire_n1llO11O_dataout <= n1lOOlli WHEN n1101iOO = '1' ELSE wire_n1llO1ll_dataout; + wire_n1llO1ii_dataout <= n1lOOlli WHEN n1101iOl = '1' ELSE n1lOO1li; + wire_n1llO1il_dataout <= n1lOOO0i WHEN n1101iOl = '1' ELSE n1lOO00i; + wire_n1llO1iO_dataout <= n1lOOlli WHEN n1101iOl = '1' ELSE n1lOO0Oi; + wire_n1llO1li_dataout <= n1lOOO0i WHEN n1101iOl = '1' ELSE n1lOOiii; + wire_n1llO1ll_dataout <= n1lOOlli WHEN n1101iOl = '1' ELSE n1lOOl1i; + wire_n1llO1lO_dataout <= n1lOOO0i WHEN n1101iOl = '1' ELSE n1lOOlli; + wire_n1llO1Oi_dataout <= n1lOOlli WHEN n1101iOl = '1' ELSE n1lOOO0i; + wire_n1llO1OO_dataout <= n1lOOO0l WHEN n1101l1i = '1' ELSE wire_n1lO110i_dataout; + wire_n1llOi0i_dataout <= n1lOOl0l WHEN n1101l1i = '1' ELSE wire_n1lO10il_dataout; + wire_n1llOi0l_dataout <= n1lOOl0O WHEN n1101l1i = '1' ELSE wire_n1lO10iO_dataout; + wire_n1llOi0O_dataout <= n1lOOlii WHEN n1101l1i = '1' ELSE wire_n1lO10li_dataout; + wire_n1llOi1i_dataout <= n1lOOl1l WHEN n1101l1i = '1' ELSE wire_n1lO100l_dataout; + wire_n1llOi1l_dataout <= n1lOOl1O WHEN n1101l1i = '1' ELSE wire_n1lO100O_dataout; + wire_n1llOi1O_dataout <= n1lOOl0i WHEN n1101l1i = '1' ELSE wire_n1lO10ii_dataout; + wire_n1llOiii_dataout <= n1lOOlil WHEN n1101l1i = '1' ELSE wire_n1lO10ll_dataout; + wire_n1llOiil_dataout <= n1lOOliO WHEN n1101l1i = '1' ELSE wire_n1lO10lO_dataout; + wire_n1llOiiO_dataout <= n1lOOiil WHEN n1101l1i = '1' ELSE wire_n1lO10Oi_dataout; + wire_n1llOili_dataout <= n1lOOiiO WHEN n1101l1i = '1' ELSE wire_n1lO10Ol_dataout; + wire_n1llOill_dataout <= n1lOOili WHEN n1101l1i = '1' ELSE wire_n1lO10OO_dataout; + wire_n1llOilO_dataout <= n1lOOill WHEN n1101l1i = '1' ELSE wire_n1lO1i1i_dataout; + wire_n1llOiOi_dataout <= n1lOOilO WHEN n1101l1i = '1' ELSE wire_n1lO1i1l_dataout; + wire_n1llOiOl_dataout <= n1lOOiOi WHEN n1101l1i = '1' ELSE wire_n1lO1i1O_dataout; + wire_n1llOiOO_dataout <= n1lOOiOl WHEN n1101l1i = '1' ELSE wire_n1lO1i0i_dataout; + wire_n1llOl0i_dataout <= n1lOOi1i WHEN n1101l1i = '1' ELSE wire_n1lO1iil_dataout; + wire_n1llOl0l_dataout <= n1lOOi1l WHEN n1101l1i = '1' ELSE wire_n1lO1iiO_dataout; + wire_n1llOl0O_dataout <= n1lOOi1O WHEN n1101l1i = '1' ELSE wire_n1lO1ili_dataout; + wire_n1llOl1i_dataout <= n1lOOiOO WHEN n1101l1i = '1' ELSE wire_n1lO1i0l_dataout; + wire_n1llOl1l_dataout <= n1lOO0Ol WHEN n1101l1i = '1' ELSE wire_n1lO1i0O_dataout; + wire_n1llOl1O_dataout <= n1lOO0OO WHEN n1101l1i = '1' ELSE wire_n1lO1iii_dataout; + wire_n1llOlii_dataout <= n1lOOi0i WHEN n1101l1i = '1' ELSE wire_n1lO1ill_dataout; + wire_n1llOlil_dataout <= n1lOOi0l WHEN n1101l1i = '1' ELSE wire_n1lO1ilO_dataout; + wire_n1llOliO_dataout <= n1lOOi0O WHEN n1101l1i = '1' ELSE wire_n1lO1iOi_dataout; + wire_n1llOlli_dataout <= n1lOO00l WHEN n1101l1i = '1' ELSE wire_n1lO1iOl_dataout; + wire_n1llOlll_dataout <= n1lOO00O WHEN n1101l1i = '1' ELSE wire_n1lO1iOO_dataout; + wire_n1llOllO_dataout <= n1lOO0ii WHEN n1101l1i = '1' ELSE wire_n1lO1l1i_dataout; + wire_n1llOlOi_dataout <= n1lOO0il WHEN n1101l1i = '1' ELSE wire_n1lO1l1l_dataout; + wire_n1llOlOl_dataout <= n1lOO0iO WHEN n1101l1i = '1' ELSE wire_n1lO1l1O_dataout; + wire_n1llOlOO_dataout <= n1lOO0li WHEN n1101l1i = '1' ELSE wire_n1lO1l0i_dataout; + wire_n1llOO0i_dataout <= n1lOO1lO WHEN n1101l1i = '1' ELSE wire_n1lO1lil_dataout; + wire_n1llOO0l_dataout <= n1lOO1Oi WHEN n1101l1i = '1' ELSE wire_n1lO1liO_dataout; + wire_n1llOO0O_dataout <= n1lOO1Ol WHEN n1101l1i = '1' ELSE wire_n1lO1lli_dataout; + wire_n1llOO1i_dataout <= n1lOO0ll WHEN n1101l1i = '1' ELSE wire_n1lO1l0l_dataout; + wire_n1llOO1l_dataout <= n1lOO0lO WHEN n1101l1i = '1' ELSE wire_n1lO1l0O_dataout; + wire_n1llOO1O_dataout <= n1lOO1ll WHEN n1101l1i = '1' ELSE wire_n1lO1lii_dataout; + wire_n1llOOii_dataout <= n1lOO1OO WHEN n1101l1i = '1' ELSE wire_n1lO1lll_dataout; + wire_n1llOOil_dataout <= n1lOO01i WHEN n1101l1i = '1' ELSE wire_n1lO1llO_dataout; + wire_n1llOOiO_dataout <= n1lOO01l WHEN n1101l1i = '1' ELSE wire_n1lO1lOi_dataout; + wire_n1llOOli_dataout <= n1lOO01O WHEN n1101l1i = '1' ELSE wire_n1lO1lOl_dataout; + wire_n1llOOll_dataout <= n1lOO11l WHEN n1101l1i = '1' ELSE wire_n1lO1lOO_dataout; + wire_n1llOOlO_dataout <= n1lOO11O WHEN n1101l1i = '1' ELSE wire_n1lO1O1i_dataout; + wire_n1llOOOi_dataout <= n1lOO10i WHEN n1101l1i = '1' ELSE wire_n1lO1O1l_dataout; + wire_n1llOOOl_dataout <= n1lOO10l WHEN n1101l1i = '1' ELSE wire_n1lO1O1O_dataout; + wire_n1llOOOO_dataout <= n1lOO10O WHEN n1101l1i = '1' ELSE wire_n1lO1O0i_dataout; + wire_n1lO000i_dataout <= n1lOOlOi WHEN n1101iOl = '1' ELSE n1lOOi1i; + wire_n1lO000l_dataout <= n1lOOlOl WHEN n1101iOl = '1' ELSE n1lOOi1l; + wire_n1lO000O_dataout <= n1lOOlOO WHEN n1101iOl = '1' ELSE n1lOOi1O; + wire_n1lO001i_dataout <= n1lOOOlO WHEN n1101iOl = '1' ELSE n1lOO0lO; + wire_n1lO001l_dataout <= n1lOOlll WHEN n1101iOl = '1' ELSE n1lOO0Ol; + wire_n1lO001O_dataout <= n1lOOllO WHEN n1101iOl = '1' ELSE n1lOO0OO; + wire_n1lO00ii_dataout <= n1lOOO1i WHEN n1101iOl = '1' ELSE n1lOOi0i; + wire_n1lO00il_dataout <= n1lOOO1l WHEN n1101iOl = '1' ELSE n1lOOi0l; + wire_n1lO00iO_dataout <= n1lOOO1O WHEN n1101iOl = '1' ELSE n1lOOi0O; + wire_n1lO00li_dataout <= n1lOOO0l WHEN n1101iOl = '1' ELSE n1lOOiil; + wire_n1lO00ll_dataout <= n1lOOO0O WHEN n1101iOl = '1' ELSE n1lOOiiO; + wire_n1lO00lO_dataout <= n1lOOOii WHEN n1101iOl = '1' ELSE n1lOOili; + wire_n1lO00Oi_dataout <= n1lOOOil WHEN n1101iOl = '1' ELSE n1lOOill; + wire_n1lO00Ol_dataout <= n1lOOOiO WHEN n1101iOl = '1' ELSE n1lOOilO; + wire_n1lO00OO_dataout <= n1lOOOli WHEN n1101iOl = '1' ELSE n1lOOiOi; + wire_n1lO010i_dataout <= n1lOOlOl WHEN n1101iOl = '1' ELSE n1lOO1Ol; + wire_n1lO010l_dataout <= n1lOOlOO WHEN n1101iOl = '1' ELSE n1lOO1OO; + wire_n1lO010O_dataout <= n1lOOO1i WHEN n1101iOl = '1' ELSE n1lOO01i; + wire_n1lO011i_dataout <= n1lOOlll WHEN n1101iOl = '1' ELSE n1lOO1ll; + wire_n1lO011l_dataout <= n1lOOllO WHEN n1101iOl = '1' ELSE n1lOO1lO; + wire_n1lO011O_dataout <= n1lOOlOi WHEN n1101iOl = '1' ELSE n1lOO1Oi; + wire_n1lO01ii_dataout <= n1lOOO1l WHEN n1101iOl = '1' ELSE n1lOO01l; + wire_n1lO01il_dataout <= n1lOOO1O WHEN n1101iOl = '1' ELSE n1lOO01O; + wire_n1lO01iO_dataout <= n1lOOO0l WHEN n1101iOl = '1' ELSE n1lOO00l; + wire_n1lO01li_dataout <= n1lOOO0O WHEN n1101iOl = '1' ELSE n1lOO00O; + wire_n1lO01ll_dataout <= n1lOOOii WHEN n1101iOl = '1' ELSE n1lOO0ii; + wire_n1lO01lO_dataout <= n1lOOOil WHEN n1101iOl = '1' ELSE n1lOO0il; + wire_n1lO01Oi_dataout <= n1lOOOiO WHEN n1101iOl = '1' ELSE n1lOO0iO; + wire_n1lO01Ol_dataout <= n1lOOOli WHEN n1101iOl = '1' ELSE n1lOO0li; + wire_n1lO01OO_dataout <= n1lOOOll WHEN n1101iOl = '1' ELSE n1lOO0ll; + wire_n1lO0i0i_dataout <= n1lOOllO WHEN n1101iOl = '1' ELSE n1lOOl1O; + wire_n1lO0i0l_dataout <= n1lOOlOi WHEN n1101iOl = '1' ELSE n1lOOl0i; + wire_n1lO0i0O_dataout <= n1lOOlOl WHEN n1101iOl = '1' ELSE n1lOOl0l; + wire_n1lO0i1i_dataout <= n1lOOOll WHEN n1101iOl = '1' ELSE n1lOOiOl; + wire_n1lO0i1l_dataout <= n1lOOOlO WHEN n1101iOl = '1' ELSE n1lOOiOO; + wire_n1lO0i1O_dataout <= n1lOOlll WHEN n1101iOl = '1' ELSE n1lOOl1l; + wire_n1lO0ii_dataout <= (wire_w_lg_niOO0i1OO3830w(0) AND wire_n1lO0Ol_w_lg_dataout3833w(0)) AND NOT(wire_niO01l0O_dataout); + wire_n1lO0iii_dataout <= n1lOOlOO WHEN n1101iOl = '1' ELSE n1lOOl0O; + wire_n1lO0iil_dataout <= n1lOOO1i WHEN n1101iOl = '1' ELSE n1lOOlii; + wire_n1lO0iiO_dataout <= n1lOOO1l WHEN n1101iOl = '1' ELSE n1lOOlil; + wire_n1lO0il_dataout <= n1lO00i AND NOT(wire_niO01l0O_dataout); + wire_n1lO0ili_dataout <= n1lOOO1O WHEN n1101iOl = '1' ELSE n1lOOliO; + wire_n1lO0ill_dataout <= n1lOOO0l WHEN n1101iOl = '1' ELSE n1lOOlll; + wire_n1lO0ilO_dataout <= n1lOOO0O WHEN n1101iOl = '1' ELSE n1lOOllO; + wire_n1lO0iO_dataout <= (wire_w_lg_niOO0i1OO3830w(0) AND wire_n1lO0Ol_dataout) AND NOT(wire_niO01l0O_dataout); + wire_n1lO0iOi_dataout <= n1lOOOii WHEN n1101iOl = '1' ELSE n1lOOlOi; + wire_n1lO0iOl_dataout <= n1lOOOil WHEN n1101iOl = '1' ELSE n1lOOlOl; + wire_n1lO0iOO_dataout <= n1lOOOiO WHEN n1101iOl = '1' ELSE n1lOOlOO; + wire_n1lO0l0i_dataout <= n1lOOlll WHEN n1101iOl = '1' ELSE n1lOOO0l; + wire_n1lO0l0l_dataout <= n1lOOllO WHEN n1101iOl = '1' ELSE n1lOOO0O; + wire_n1lO0l0O_dataout <= n1lOOlOi WHEN n1101iOl = '1' ELSE n1lOOOii; + wire_n1lO0l1i_dataout <= n1lOOOli WHEN n1101iOl = '1' ELSE n1lOOO1i; + wire_n1lO0l1l_dataout <= n1lOOOll WHEN n1101iOl = '1' ELSE n1lOOO1l; + wire_n1lO0l1O_dataout <= n1lOOOlO WHEN n1101iOl = '1' ELSE n1lOOO1O; + wire_n1lO0lii_dataout <= n1lOOlOl WHEN n1101iOl = '1' ELSE n1lOOOil; + wire_n1lO0lil_dataout <= n1lOOlOO WHEN n1101iOl = '1' ELSE n1lOOOiO; + wire_n1lO0liO_dataout <= n1lOOO1i WHEN n1101iOl = '1' ELSE n1lOOOli; + wire_n1lO0lli_dataout <= n1lOOO1l WHEN n1101iOl = '1' ELSE n1lOOOll; + wire_n1lO0lll_dataout <= n1lOOO1O WHEN n1101iOl = '1' ELSE n1lOOOlO; + wire_n1lO0lOO_dataout <= wire_nlOiOi1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lO0O0i_dataout <= wire_n1lO0O0O_dataout AND NOT(niOli0O0l); + wire_n1lO0O0l_dataout <= wire_n1lO0OOl_dataout WHEN wire_nlOiOi1ll_dataout = '1' ELSE wire_n1lO0Oii_dataout; + wire_n1lO0O0O_dataout <= wire_n1lO0OOO_dataout WHEN wire_nlOiOi1ll_dataout = '1' ELSE wire_n1lO0Oil_dataout; + wire_n1lO0O1i_dataout <= wire_n1lO0O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lO0O1l_dataout <= wire_n1lO0O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lO0O1O_dataout <= wire_n1lO0O0l_dataout AND NOT(niOli0O0l); + wire_n1lO0Oii_dataout <= wire_n1lO0OiO_dataout OR niOli0O0i; + wire_n1lO0Oil_dataout <= wire_w_lg_niOli0O1O18941w(0) AND NOT(niOli0O0i); + wire_n1lO0OiO_dataout <= n1lO0llO AND niOli0O1O; + wire_n1lO0Ol_dataout <= (wire_ni01lOi_w_lg_n1lOi0i3805w(0) AND wire_w_lg_w_k_hip_range2413w3817w(0)) OR (wire_ni01lOi_w_lg_n1lOi0i3805w(0) AND (wire_w_lg_w_k_hip_range2413w2429w(0) AND ((((NOT (n1lOlOl XOR n1lOlli)) AND (NOT (n1lOlOO XOR n1lOlll))) AND (NOT (n1lOO1i XOR n1lOllO))) AND (NOT (n1lOO1l XOR n1lOlOi))))); + wire_n1lO0Ol_w_lg_dataout3833w(0) <= wire_n1lO0Ol_dataout AND wire_ni01lOi_w_lg_n1lO00i3832w(0); + wire_n1lO0Ol_w_lg_dataout3599w(0) <= NOT wire_n1lO0Ol_dataout; + wire_n1lO0OOl_dataout <= n1lO0llO AND NOT(n1lO0lOl); + wire_n1lO0OOO_dataout <= n1lO0lOi AND NOT(n1lO0lOl); + wire_n1lO100i_dataout <= n1lOOO1O WHEN n1101iOO = '1' ELSE wire_n1lO01il_dataout; + wire_n1lO100l_dataout <= n1lOOl1l WHEN n1101iOO = '1' ELSE wire_n1lO01iO_dataout; + wire_n1lO100O_dataout <= n1lOOl1O WHEN n1101iOO = '1' ELSE wire_n1lO01li_dataout; + wire_n1lO101i_dataout <= n1lOOlOO WHEN n1101iOO = '1' ELSE wire_n1lO010l_dataout; + wire_n1lO101l_dataout <= n1lOOO1i WHEN n1101iOO = '1' ELSE wire_n1lO010O_dataout; + wire_n1lO101O_dataout <= n1lOOO1l WHEN n1101iOO = '1' ELSE wire_n1lO01ii_dataout; + wire_n1lO10ii_dataout <= n1lOOl0i WHEN n1101iOO = '1' ELSE wire_n1lO01ll_dataout; + wire_n1lO10il_dataout <= n1lOOl0l WHEN n1101iOO = '1' ELSE wire_n1lO01lO_dataout; + wire_n1lO10iO_dataout <= n1lOOl0O WHEN n1101iOO = '1' ELSE wire_n1lO01Oi_dataout; + wire_n1lO10li_dataout <= n1lOOlii WHEN n1101iOO = '1' ELSE wire_n1lO01Ol_dataout; + wire_n1lO10ll_dataout <= n1lOOlil WHEN n1101iOO = '1' ELSE wire_n1lO01OO_dataout; + wire_n1lO10lO_dataout <= n1lOOliO WHEN n1101iOO = '1' ELSE wire_n1lO001i_dataout; + wire_n1lO10Oi_dataout <= n1lOOiil WHEN n1101iOO = '1' ELSE wire_n1lO001l_dataout; + wire_n1lO10Ol_dataout <= n1lOOiiO WHEN n1101iOO = '1' ELSE wire_n1lO001O_dataout; + wire_n1lO10OO_dataout <= n1lOOili WHEN n1101iOO = '1' ELSE wire_n1lO000i_dataout; + wire_n1lO110i_dataout <= n1lOOO0l WHEN n1101iOO = '1' ELSE wire_n1lO1Oil_dataout; + wire_n1lO110l_dataout <= n1lOOO0O WHEN n1101iOO = '1' ELSE wire_n1lO1OiO_dataout; + wire_n1lO110O_dataout <= n1lOOOii WHEN n1101iOO = '1' ELSE wire_n1lO1Oli_dataout; + wire_n1lO111i_dataout <= n1lOO1ii WHEN n1101l1i = '1' ELSE wire_n1lO1O0l_dataout; + wire_n1lO111l_dataout <= n1lOO1il WHEN n1101l1i = '1' ELSE wire_n1lO1O0O_dataout; + wire_n1lO111O_dataout <= n1lOO1iO WHEN n1101l1i = '1' ELSE wire_n1lO1Oii_dataout; + wire_n1lO11ii_dataout <= n1lOOOil WHEN n1101iOO = '1' ELSE wire_n1lO1Oll_dataout; + wire_n1lO11il_dataout <= n1lOOOiO WHEN n1101iOO = '1' ELSE wire_n1lO1OlO_dataout; + wire_n1lO11iO_dataout <= n1lOOOli WHEN n1101iOO = '1' ELSE wire_n1lO1OOi_dataout; + wire_n1lO11li_dataout <= n1lOOOll WHEN n1101iOO = '1' ELSE wire_n1lO1OOl_dataout; + wire_n1lO11ll_dataout <= n1lOOOlO WHEN n1101iOO = '1' ELSE wire_n1lO1OOO_dataout; + wire_n1lO11lO_dataout <= n1lOOlll WHEN n1101iOO = '1' ELSE wire_n1lO011i_dataout; + wire_n1lO11Oi_dataout <= n1lOOllO WHEN n1101iOO = '1' ELSE wire_n1lO011l_dataout; + wire_n1lO11Ol_dataout <= n1lOOlOi WHEN n1101iOO = '1' ELSE wire_n1lO011O_dataout; + wire_n1lO11OO_dataout <= n1lOOlOl WHEN n1101iOO = '1' ELSE wire_n1lO010i_dataout; + wire_n1lO1i0i_dataout <= n1lOOiOl WHEN n1101iOO = '1' ELSE wire_n1lO00il_dataout; + wire_n1lO1i0l_dataout <= n1lOOiOO WHEN n1101iOO = '1' ELSE wire_n1lO00iO_dataout; + wire_n1lO1i0O_dataout <= n1lOOO0l WHEN n1101iOO = '1' ELSE wire_n1lO00li_dataout; + wire_n1lO1i1i_dataout <= n1lOOill WHEN n1101iOO = '1' ELSE wire_n1lO000l_dataout; + wire_n1lO1i1l_dataout <= n1lOOilO WHEN n1101iOO = '1' ELSE wire_n1lO000O_dataout; + wire_n1lO1i1O_dataout <= n1lOOiOi WHEN n1101iOO = '1' ELSE wire_n1lO00ii_dataout; + wire_n1lO1iii_dataout <= n1lOOO0O WHEN n1101iOO = '1' ELSE wire_n1lO00ll_dataout; + wire_n1lO1iil_dataout <= n1lOOOii WHEN n1101iOO = '1' ELSE wire_n1lO00lO_dataout; + wire_n1lO1iiO_dataout <= n1lOOOil WHEN n1101iOO = '1' ELSE wire_n1lO00Oi_dataout; + wire_n1lO1ili_dataout <= n1lOOOiO WHEN n1101iOO = '1' ELSE wire_n1lO00Ol_dataout; + wire_n1lO1ill_dataout <= n1lOOOli WHEN n1101iOO = '1' ELSE wire_n1lO00OO_dataout; + wire_n1lO1ilO_dataout <= n1lOOOll WHEN n1101iOO = '1' ELSE wire_n1lO0i1i_dataout; + wire_n1lO1iOi_dataout <= n1lOOOlO WHEN n1101iOO = '1' ELSE wire_n1lO0i1l_dataout; + wire_n1lO1iOl_dataout <= n1lOOlll WHEN n1101iOO = '1' ELSE wire_n1lO0i1O_dataout; + wire_n1lO1iOO_dataout <= n1lOOllO WHEN n1101iOO = '1' ELSE wire_n1lO0i0i_dataout; + wire_n1lO1l0i_dataout <= n1lOOO1i WHEN n1101iOO = '1' ELSE wire_n1lO0iil_dataout; + wire_n1lO1l0l_dataout <= n1lOOO1l WHEN n1101iOO = '1' ELSE wire_n1lO0iiO_dataout; + wire_n1lO1l0O_dataout <= n1lOOO1O WHEN n1101iOO = '1' ELSE wire_n1lO0ili_dataout; + wire_n1lO1l1i_dataout <= n1lOOlOi WHEN n1101iOO = '1' ELSE wire_n1lO0i0l_dataout; + wire_n1lO1l1l_dataout <= n1lOOlOl WHEN n1101iOO = '1' ELSE wire_n1lO0i0O_dataout; + wire_n1lO1l1O_dataout <= n1lOOlOO WHEN n1101iOO = '1' ELSE wire_n1lO0iii_dataout; + wire_n1lO1lii_dataout <= n1lOOl1l WHEN n1101iOO = '1' ELSE wire_n1lO0ill_dataout; + wire_n1lO1lil_dataout <= n1lOOl1O WHEN n1101iOO = '1' ELSE wire_n1lO0ilO_dataout; + wire_n1lO1liO_dataout <= n1lOOl0i WHEN n1101iOO = '1' ELSE wire_n1lO0iOi_dataout; + wire_n1lO1lli_dataout <= n1lOOl0l WHEN n1101iOO = '1' ELSE wire_n1lO0iOl_dataout; + wire_n1lO1lll_dataout <= n1lOOl0O WHEN n1101iOO = '1' ELSE wire_n1lO0iOO_dataout; + wire_n1lO1llO_dataout <= n1lOOlii WHEN n1101iOO = '1' ELSE wire_n1lO0l1i_dataout; + wire_n1lO1lOi_dataout <= n1lOOlil WHEN n1101iOO = '1' ELSE wire_n1lO0l1l_dataout; + wire_n1lO1lOl_dataout <= n1lOOliO WHEN n1101iOO = '1' ELSE wire_n1lO0l1O_dataout; + wire_n1lO1lOO_dataout <= n1lOOiil WHEN n1101iOO = '1' ELSE wire_n1lO0l0i_dataout; + wire_n1lO1O0i_dataout <= n1lOOilO WHEN n1101iOO = '1' ELSE wire_n1lO0lil_dataout; + wire_n1lO1O0l_dataout <= n1lOOiOi WHEN n1101iOO = '1' ELSE wire_n1lO0liO_dataout; + wire_n1lO1O0O_dataout <= n1lOOiOl WHEN n1101iOO = '1' ELSE wire_n1lO0lli_dataout; + wire_n1lO1O1i_dataout <= n1lOOiiO WHEN n1101iOO = '1' ELSE wire_n1lO0l0l_dataout; + wire_n1lO1O1l_dataout <= n1lOOili WHEN n1101iOO = '1' ELSE wire_n1lO0l0O_dataout; + wire_n1lO1O1O_dataout <= n1lOOill WHEN n1101iOO = '1' ELSE wire_n1lO0lii_dataout; + wire_n1lO1Oii_dataout <= n1lOOiOO WHEN n1101iOO = '1' ELSE wire_n1lO0lll_dataout; + wire_n1lO1Oil_dataout <= n1lOOO0l WHEN n1101iOl = '1' ELSE n1lOO11l; + wire_n1lO1OiO_dataout <= n1lOOO0O WHEN n1101iOl = '1' ELSE n1lOO11O; + wire_n1lO1Oli_dataout <= n1lOOOii WHEN n1101iOl = '1' ELSE n1lOO10i; + wire_n1lO1Oll_dataout <= n1lOOOil WHEN n1101iOl = '1' ELSE n1lOO10l; + wire_n1lO1OlO_dataout <= n1lOOOiO WHEN n1101iOl = '1' ELSE n1lOO10O; + wire_n1lO1OOi_dataout <= n1lOOOli WHEN n1101iOl = '1' ELSE n1lOO1ii; + wire_n1lO1OOl_dataout <= n1lOOOll WHEN n1101iOl = '1' ELSE n1lOO1il; + wire_n1lO1OOO_dataout <= n1lOOOlO WHEN n1101iOl = '1' ELSE n1lOO1iO; + wire_n1lOi0iO_dataout <= wire_n1lOii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lOi0l_dataout <= n1O1Oil AND NOT(wire_niO01l0O_dataout); + wire_n1lOi0li_dataout <= wire_n1lOil0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lOi0ll_dataout <= wire_n1lOil0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lOi0lO_dataout <= wire_n1lOilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lOi0O_dataout <= n1O1OiO AND NOT(wire_niO01l0O_dataout); + wire_n1lOi0Oi_dataout <= wire_n1lOiO0O_o AND NOT(wire_niO01lOO_dataout); + wire_n1lOi0Ol_dataout <= wire_n1lOiOil_o AND NOT(wire_niO01lOO_dataout); + wire_n1lOi0OO_dataout <= wire_n1lOiOli_o AND NOT(wire_niO01lOO_dataout); + wire_n1lOi10l_dataout <= wire_n1lOi1il_dataout AND NOT(wire_w_lg_niOlii11i18931w(0)); + wire_n1lOi10O_dataout <= wire_n1lOi1iO_dataout AND NOT(wire_w_lg_niOlii11i18931w(0)); + wire_n1lOi1ii_dataout <= niOli0O0O AND NOT(wire_w_lg_niOlii11i18931w(0)); + wire_n1lOi1il_dataout <= wire_niO01ill_w_lg_niil010i18930w(0) AND NOT(niOli0O0O); + wire_n1lOi1iO_dataout <= niil010i AND NOT(niOli0O0O); + wire_n1lOii0i_dataout <= wire_n1lOl11i_o AND NOT(wire_niO01lOO_dataout); + wire_n1lOii0l_dataout <= wire_n1lOl11O_o OR wire_niO01lOO_dataout; + wire_n1lOii0O_dataout <= n1110O0O WHEN n1lOi0ii = '1' ELSE wire_n1lOiiii_dataout; + wire_n1lOii1i_dataout <= wire_n1lOiOlO_o AND NOT(wire_niO01lOO_dataout); + wire_n1lOii1l_dataout <= wire_n1lOiOOi_o AND NOT(wire_niO01lOO_dataout); + wire_n1lOii1O_dataout <= wire_n1lOiOOl_o AND NOT(wire_niO01lOO_dataout); + wire_n1lOiii_dataout <= n1O1Oli AND NOT(wire_niO01l0O_dataout); + wire_n1lOiiii_dataout <= wire_n1lOiiil_dataout AND NOT((((((n1l1OlOi AND (((wire_nlOiOl1lO_dataout OR (wire_nlOiOl1ll_w_lg_dataout18919w(0) AND n1lOi00O)) AND n1lO0lOl) OR n1lOi1OO)) OR n1lOi01O) OR n1lOi01l) OR n1lOi01i) OR n1lOi00i)); + wire_n1lOiiil_dataout <= wire_n1lOiiiO_dataout OR n1lOi1OO; + wire_n1lOiiiO_dataout <= niil010O WHEN n1lO0lOl = '1' ELSE wire_n1lOiili_dataout; + wire_n1lOiil_dataout <= n1O1Oll AND NOT(wire_niO01l0O_dataout); + wire_n1lOiili_dataout <= n1lO0lOl OR niOli0Oli; + wire_n1lOil0l_dataout <= wire_n1lOilil_dataout AND NOT(n1lOi0ii); + wire_n1lOil0O_dataout <= wire_n1lOiliO_dataout AND NOT(n1lOi0ii); + wire_n1lOilii_dataout <= wire_n1lOilli_dataout AND NOT(n1lOi0ii); + wire_n1lOilil_dataout <= wire_n1lOilll_dataout AND NOT(niOli0Oii); + wire_n1lOiliO_dataout <= wire_n1lOillO_dataout AND NOT(niOli0Oii); + wire_n1lOilli_dataout <= wire_n1lOilOi_dataout AND NOT(niOli0Oii); + wire_n1lOilll_dataout <= wire_n1lOilOO_dataout WHEN n1lO0lOl = '1' ELSE wire_n1lOilOl_o(1); + wire_n1lOillO_dataout <= wire_n1lOiO1i_dataout WHEN n1lO0lOl = '1' ELSE wire_n1lOilOl_o(2); + wire_n1lOilOi_dataout <= niil00Ol WHEN n1lO0lOl = '1' ELSE wire_n1lOilOl_o(3); + wire_n1lOilOO_dataout <= wire_n1lOiO1l_dataout OR niil00Ol; + wire_n1lOiO1i_dataout <= niil010i OR niil00Ol; + wire_n1lOiO1l_dataout <= niil010l OR niil010i; + wire_n1lOl00i_dataout <= n1lOi0ii AND NOT(niOli0Oli); + wire_n1lOl00l_dataout <= n1l1OlOi AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl00O_dataout <= wire_niO01ill_w_lg_n1l1OlOi18773w(0) AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl01i_dataout <= n1lOi00i AND NOT(niOli0Oli); + wire_n1lOl01l_dataout <= n1lOi00l AND NOT(niOli0Oli); + wire_n1lOl01O_dataout <= n1lOi00O AND NOT(niOli0Oli); + wire_n1lOl0ii_dataout <= wire_n1lOl0OO_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl0il_dataout <= wire_n1lOli1i_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl0iO_dataout <= wire_n1lOli1l_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl0li_dataout <= wire_n1lOli1O_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl0ll_dataout <= wire_n1lOli0i_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl0lO_dataout <= wire_n1lOli0l_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl0Oi_dataout <= wire_n1lOli0O_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl0Ol_dataout <= wire_n1lOliii_dataout OR wire_niO01ill_w_lg_n1110O0O18762w(0); + wire_n1lOl0OO_dataout <= n1lOi1OO AND NOT(niOli0Oll); + wire_n1lOl10i_dataout <= wire_n1lOl1lO_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl10l_dataout <= wire_n1lOl1Oi_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl10O_dataout <= wire_n1lOl1Ol_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl1ii_dataout <= wire_n1lOl1OO_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl1il_dataout <= wire_n1lOl01i_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl1iO_dataout <= wire_n1lOl01l_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl1li_dataout <= wire_n1lOl01O_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOl1ll_dataout <= wire_n1lOl00i_dataout OR wire_niO01ill_w_lg_n1110O0O18762w(0); + wire_n1lOl1lO_dataout <= n1lOi1OO AND NOT(niOli0Oli); + wire_n1lOl1Oi_dataout <= n1lOi01i AND NOT(niOli0Oli); + wire_n1lOl1Ol_dataout <= n1lOi01l AND NOT(niOli0Oli); + wire_n1lOl1OO_dataout <= n1lOi01O OR niOli0Oli; + wire_n1lOli0i_dataout <= wire_n1lOliiO_dataout WHEN niOli0Oll = '1' ELSE n1lOi00i; + wire_n1lOli0l_dataout <= n1lOi00l AND NOT(niOli0Oll); + wire_n1lOli0O_dataout <= wire_niO01ill_w_lg_n1l1OlOi18773w(0) WHEN niOli0Oll = '1' ELSE n1lOi00O; + wire_n1lOli1i_dataout <= n1lOi01i AND NOT(niOli0Oll); + wire_n1lOli1l_dataout <= n1lOi01l AND NOT(niOli0Oll); + wire_n1lOli1O_dataout <= wire_n1lOliil_dataout WHEN niOli0Oll = '1' ELSE n1lOi01O; + wire_n1lOliii_dataout <= n1lOi0ii AND NOT(niOli0Oll); + wire_n1lOliil_dataout <= niil010O AND n1l1OlOi; + wire_n1lOliiO_dataout <= wire_niO01ill_w_lg_niil010O18772w(0) AND n1l1OlOi; + wire_n1lOlill_dataout <= wire_n1lOll0i_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOlilO_dataout <= wire_n1lOll0l_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOliOi_dataout <= wire_n1lOll0O_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOliOl_dataout <= wire_n1lOllii_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOliOO_dataout <= wire_n1lOllil_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOll0i_dataout <= wire_n1lOlllO_dataout AND NOT(niOli0OOl); + wire_n1lOll0l_dataout <= wire_n1lOllOi_dataout AND NOT(niOli0OOl); + wire_n1lOll0O_dataout <= wire_n1lOllOl_dataout AND NOT(niOli0OOl); + wire_n1lOll1i_dataout <= wire_n1lOlliO_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOll1l_dataout <= wire_n1lOllli_dataout AND NOT(wire_niO01ill_w_lg_n1110O0O18762w(0)); + wire_n1lOll1O_dataout <= wire_n1lOllll_dataout OR wire_niO01ill_w_lg_n1110O0O18762w(0); + wire_n1lOllii_dataout <= wire_n1lOllOO_dataout AND NOT(niOli0OOl); + wire_n1lOllil_dataout <= wire_n1lOlO1i_dataout AND NOT(niOli0OOl); + wire_n1lOlliO_dataout <= wire_n1lOlO1l_dataout OR niOli0OOl; + wire_n1lOllli_dataout <= wire_n1lOlO1O_dataout AND NOT(niOli0OOl); + wire_n1lOllll_dataout <= wire_n1lOlO0i_dataout AND NOT(niOli0OOl); + wire_n1lOlllO_dataout <= n1lOi1OO AND NOT(niOli0OOi); + wire_n1lOllOi_dataout <= n1lOi01i AND NOT(niOli0OOi); + wire_n1lOllOl_dataout <= n1lOi01l AND NOT(niOli0OOi); + wire_n1lOllOO_dataout <= niOli0OlO WHEN niOli0OOi = '1' ELSE n1lOi01O; + wire_n1lOlO0i_dataout <= n1lOi0ii AND NOT(niOli0OOi); + wire_n1lOlO1i_dataout <= wire_w_lg_niOli0OlO18770w(0) WHEN niOli0OOi = '1' ELSE n1lOi00i; + wire_n1lOlO1l_dataout <= n1lOi00l AND NOT(niOli0OOi); + wire_n1lOlO1O_dataout <= n1lOi00O AND NOT(niOli0OOi); + wire_n1lOlOiO_dataout <= n1lOi1OO AND NOT(n1110O0O); + wire_n1lOlOli_dataout <= n1lOi01i AND NOT(n1110O0O); + wire_n1lOlOll_dataout <= n1lOi01l AND NOT(n1110O0O); + wire_n1lOlOlO_dataout <= n1lOi01O AND NOT(n1110O0O); + wire_n1lOlOOi_dataout <= n1lOi00i AND NOT(n1110O0O); + wire_n1lOlOOl_dataout <= n1lOi00l AND NOT(n1110O0O); + wire_n1lOlOOO_dataout <= n1lOi00O OR n1110O0O; + wire_n1lOO11i_dataout <= n1lOi0ii AND NOT(n1110O0O); + wire_n1lOOil_dataout <= wire_n1O101l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1lOOiO_dataout <= niOO00Oii AND NOT(wire_niO01l0O_dataout); + wire_n1lOOli_dataout <= niOO00Oil AND NOT(wire_niO01l0O_dataout); + wire_n1lOOll_dataout <= niOO00OOl AND NOT(wire_niO01l0O_dataout); + wire_n1lOOlO_dataout <= n1lOO1l AND NOT(wire_niO01l0O_dataout); + wire_n1lOOOi_dataout <= niOO00OiO AND NOT(wire_niO01l0O_dataout); + wire_n1lOOOl_dataout <= niOO00Oli AND NOT(wire_niO01l0O_dataout); + wire_n1lOOOO_dataout <= niOO00Oll AND NOT(wire_niO01l0O_dataout); + wire_n1lOOOOi_dataout <= wire_n1O11Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lOOOOl_dataout <= wire_n1O11Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1lOOOOO_dataout <= wire_n1O11OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0000i_dataout <= wire_n1O00i0l_dataout OR niOlii10i; + wire_n1O0000l_dataout <= wire_n1O00i0O_dataout OR niOlii10i; + wire_n1O0000O_dataout <= wire_n1O00iii_dataout OR niOlii10i; + wire_n1O0001i_dataout <= wire_n1O00i1l_dataout OR niOlii10i; + wire_n1O0001l_dataout <= wire_n1O00i1O_dataout OR niOlii10i; + wire_n1O0001O_dataout <= wire_n1O00i0i_dataout OR niOlii10i; + wire_n1O000ii_dataout <= wire_n1O00iil_dataout OR niOlii10i; + wire_n1O000il_dataout <= wire_n1O00iiO_dataout OR niOlii10i; + wire_n1O000iO_dataout <= wire_n1O00ili_dataout OR niOlii10i; + wire_n1O000l_dataout <= n1O1O0i WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1Oil; + wire_n1O000li_dataout <= wire_n1O00ill_dataout OR niOlii10i; + wire_n1O000ll_dataout <= wire_n1O00ilO_dataout OR niOlii10i; + wire_n1O000lO_dataout <= wire_n1O00iOi_dataout OR niOlii10i; + wire_n1O000O_dataout <= n1O1O0l WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1OiO; + wire_n1O000Oi_dataout <= wire_n1O00iOl_dataout OR niOlii10i; + wire_n1O000Ol_dataout <= n1O01iOO WHEN niOlii11O = '1' ELSE n1O01O1O; + wire_n1O000OO_dataout <= n1O01lll WHEN niOlii11O = '1' ELSE n1O01O0i; + wire_n1O0010i_dataout <= wire_n1O0000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0010l_dataout <= wire_n1O0000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0010O_dataout <= wire_n1O000ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0011i_dataout <= wire_n1O0001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0011l_dataout <= wire_n1O0001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0011O_dataout <= wire_n1O0000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O001ii_dataout <= wire_n1O000il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O001il_dataout <= wire_n1O000iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O001iO_dataout <= wire_n1O000li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O001li_dataout <= wire_n1O000ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O001ll_dataout <= wire_n1O000lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O001lO_dataout <= wire_n1O000Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O001Oi_dataout <= wire_n1O000Ol_dataout OR niOlii10i; + wire_n1O001Ol_dataout <= wire_n1O000OO_dataout OR niOlii10i; + wire_n1O001OO_dataout <= wire_n1O00i1i_dataout OR niOlii10i; + wire_n1O00i0i_dataout <= n1O01lOO WHEN niOlii11O = '1' ELSE (n1O01O1O XOR (n1O01O0i XOR (n1O01Oil XOR n1O01O0l))); + wire_n1O00i0l_dataout <= n1O01O1i WHEN niOlii11O = '1' ELSE (n1O01O0i XOR (n1O01O0l XOR (n1O01OiO XOR n1O01O0O))); + wire_n1O00i0O_dataout <= n1O01O1l WHEN niOlii11O = '1' ELSE (n1O01O0l XOR (n1O01O0O XOR (n1O01Oli XOR n1O01Oii))); + wire_n1O00i1i_dataout <= n1O01llO WHEN niOlii11O = '1' ELSE n1O01O0l; + wire_n1O00i1l_dataout <= n1O01lOi WHEN niOlii11O = '1' ELSE (n1O01O0O XOR n1O01O1O); + wire_n1O00i1O_dataout <= n1O01lOl WHEN niOlii11O = '1' ELSE (n1O01O1O XOR (n1O01Oii XOR n1O01O0i)); + wire_n1O00ii_dataout <= n1O1O0O WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1Oli; + wire_n1O00iii_dataout <= n1O01O1O WHEN niOlii11O = '1' ELSE (n1O01O0O XOR (n1O01Oii XOR (n1O01Oil XOR n1O01iOO))); + wire_n1O00iil_dataout <= n1O01O0i WHEN niOlii11O = '1' ELSE (n1O01Oii XOR (n1O01Oil XOR (n1O01OiO XOR n1O01lll))); + wire_n1O00iiO_dataout <= n1O01O0l WHEN niOlii11O = '1' ELSE (n1O01Oil XOR (n1O01OiO XOR (n1O01Oli XOR n1O01llO))); + wire_n1O00il_dataout <= n1O1Oii WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1Oll; + wire_n1O00ili_dataout <= n1O01O0O WHEN niOlii11O = '1' ELSE (n1O01OiO XOR (n1O01Oli XOR n1O01lOi)); + wire_n1O00ill_dataout <= n1O01Oii WHEN niOlii11O = '1' ELSE (n1O01Oli XOR n1O01lOl); + wire_n1O00ilO_dataout <= n1O01Oil WHEN niOlii11O = '1' ELSE n1O01lOO; + wire_n1O00iO_dataout <= n1O1lOO WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1O0i; + wire_n1O00iOi_dataout <= n1O01OiO WHEN niOlii11O = '1' ELSE n1O01O1i; + wire_n1O00iOl_dataout <= n1O01Oli WHEN niOlii11O = '1' ELSE n1O01O1l; + wire_n1O00l1i_dataout <= wire_n1O00l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O00l1l_dataout <= wire_n1O00l1O_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n1O01Oll) AND niOlii10i)); + wire_n1O00l1O_dataout <= n1O01Oll OR n111i10i; + wire_n1O00li_dataout <= n1O1O1i WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1O0l; + wire_n1O00ll_dataout <= n1O1O1l WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1O0O; + wire_n1O00lO_dataout <= n1O1O1O WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1Oii; + wire_n1O00Oi_dataout <= (wire_w_lg_niOO0i1Ol3636w(0) XOR n1O1lOO) WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1lOO; + wire_n1O00Ol_dataout <= ((niOO0i1Ol AND wire_w_lg_niOO0i1Oi3637w(0)) XOR n1O1O1i) WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1O1i; + wire_n1O00OO_dataout <= ((wire_w_lg_niOO0i1lO3644w(0) AND wire_w_lg_niOO0i1ll3640w(0)) XOR n1O1O1l) WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1O1l; + wire_n1O010i_dataout <= wire_n1O00Ol_dataout OR wire_niO01O0O_dataout; + wire_n1O010l_dataout <= wire_n1O00OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O010O_dataout <= wire_n1O0i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O0110i_dataout <= wire_nlOiOiOli_dataout WHEN niOlii11i = '1' ELSE n1lOO0Ol; + wire_n1O0110l_dataout <= wire_nlOiOiOll_dataout WHEN niOlii11i = '1' ELSE n1lOO0OO; + wire_n1O0110O_dataout <= wire_nlOiOiOlO_dataout WHEN niOlii11i = '1' ELSE n1lOOi1i; + wire_n1O0111i_dataout <= wire_nlOiOiiOl_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO0ll; + wire_n1O0111l_dataout <= wire_nlOiOiiOO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO0lO; + wire_n1O0111O_dataout <= wire_nlOiOl1li_dataout WHEN niOlii11i = '1' ELSE n1lOO0Oi; + wire_n1O011i_dataout <= n1lOO0l AND NOT(wire_niO01O0O_dataout); + wire_n1O011ii_dataout <= wire_nlOiOiOOi_dataout WHEN niOlii11i = '1' ELSE n1lOOi1l; + wire_n1O011il_dataout <= wire_nlOiOiOOl_dataout WHEN niOlii11i = '1' ELSE n1lOOi1O; + wire_n1O011iO_dataout <= wire_nlOiOiOOO_dataout WHEN niOlii11i = '1' ELSE n1lOOi0i; + wire_n1O011l_dataout <= n1lOO0O AND NOT(wire_niO01O0O_dataout); + wire_n1O011li_dataout <= wire_nlOiOl11i_dataout WHEN niOlii11i = '1' ELSE n1lOOi0l; + wire_n1O011ll_dataout <= wire_nlOiOl11l_dataout WHEN niOlii11i = '1' ELSE n1lOOi0O; + wire_n1O011O_dataout <= wire_n1O00Oi_dataout OR wire_niO01O0O_dataout; + wire_n1O01ii_dataout <= wire_n1O00iO_dataout OR wire_niO01O0O_dataout; + wire_n1O01iil_dataout <= n1OO0Oll WHEN niOlii11l = '1' ELSE (n1OO0Oll XOR n1O01O1O); + wire_n1O01il_dataout <= wire_n1O00li_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O01ill_dataout <= n1OO0Oli WHEN niOlii11l = '1' ELSE (n1OO0Oli XOR n1O01O0i); + wire_n1O01iO_dataout <= wire_n1O00ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O01iOi_dataout <= n1OO0OiO WHEN niOlii11l = '1' ELSE (n1OO0OiO XOR n1O01O0l); + wire_n1O01l0l_dataout <= n1OO0O0O WHEN niOlii11l = '1' ELSE (n1OO0O0O XOR n1O01Oil); + wire_n1O01l1i_dataout <= n1OO0Oil WHEN niOlii11l = '1' ELSE (n1OO0Oil XOR n1O01O0O); + wire_n1O01l1O_dataout <= n1OO0Oii WHEN niOlii11l = '1' ELSE (n1OO0Oii XOR n1O01Oii); + wire_n1O01li_dataout <= wire_n1O00lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O01lii_dataout <= n1OO0O0l WHEN niOlii11l = '1' ELSE (n1OO0O0l XOR n1O01OiO); + wire_n1O01liO_dataout <= n1OO0O0i WHEN niOlii11l = '1' ELSE (n1OO0O0i XOR n1O01Oli); + wire_n1O01ll_dataout <= wire_n1O000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O01lO_dataout <= wire_n1O000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O01Oi_dataout <= wire_n1O00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O01Ol_dataout <= wire_n1O00il_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O01OlO_dataout <= wire_n1O001Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O01OO_dataout <= n1O1l0l WHEN ((((NOT (niOO0i1li XOR niOO0i1iO)) AND (NOT (niOO0i1il XOR niOO0i1ii))) AND (NOT (niOO0i10O XOR niOO0i10l))) AND (NOT (n1O1Oll XOR n1O1lOl))) = '1' ELSE wire_n1O001i_o; + wire_n1O01OOi_dataout <= wire_n1O001Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O01OOl_dataout <= wire_n1O001OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O01OOO_dataout <= wire_n1O0001i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0i01i_dataout <= wire_niO10O0l_dataout WHEN niOlii10l = '1' ELSE (wire_niO10O0l_dataout XOR n1O0ii1O); + wire_n1O0i01i_w_lg_dataout18537w(0) <= NOT wire_n1O0i01i_dataout; + wire_n1O0i01O_dataout <= wire_niO10O0i_dataout WHEN niOlii10l = '1' ELSE (wire_niO10O0i_dataout XOR n1O0ii0i); + wire_n1O0i01O_w_lg_dataout18535w(0) <= NOT wire_n1O0i01O_dataout; + wire_n1O0i10l_dataout <= wire_niO10Oli_dataout WHEN niOlii10l = '1' ELSE (wire_niO10Oli_dataout XOR n1O0i0Oi); + wire_n1O0i10l_w_lg_dataout18547w(0) <= NOT wire_n1O0i10l_dataout; + wire_n1O0i11l_dataout <= wire_niO10Oll_dataout WHEN niOlii10l = '1' ELSE (wire_niO10Oll_dataout XOR n1O0i0lO); + wire_n1O0i11l_w_lg_dataout18549w(0) <= NOT wire_n1O0i11l_dataout; + wire_n1O0i1i_dataout <= ((NOT (niOO0i1lO OR wire_w_lg_niOO0i1ll3640w(0))) XOR n1O1O1O) WHEN wire_n1O0l0l_dataout = '1' ELSE n1O1O1O; + wire_n1O0i1ii_dataout <= wire_niO10OiO_dataout WHEN niOlii10l = '1' ELSE (wire_niO10OiO_dataout XOR n1O0i0Ol); + wire_n1O0i1ii_w_lg_dataout18545w(0) <= NOT wire_n1O0i1ii_dataout; + wire_n1O0i1li_dataout <= wire_niO10Oil_dataout WHEN niOlii10l = '1' ELSE (wire_niO10Oil_dataout XOR n1O0i0OO); + wire_n1O0i1li_w_lg_dataout18543w(0) <= NOT wire_n1O0i1li_dataout; + wire_n1O0i1lO_dataout <= wire_niO10Oii_dataout WHEN niOlii10l = '1' ELSE (wire_niO10Oii_dataout XOR n1O0ii1i); + wire_n1O0i1lO_w_lg_dataout18541w(0) <= NOT wire_n1O0i1lO_dataout; + wire_n1O0i1Ol_dataout <= wire_niO10O0O_dataout WHEN niOlii10l = '1' ELSE (wire_niO10O0O_dataout XOR n1O0ii1l); + wire_n1O0i1Ol_w_lg_dataout18539w(0) <= NOT wire_n1O0i1Ol_dataout; + wire_n1O0ii0l_dataout <= wire_n1O0il0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0ii0O_dataout <= wire_n1O0ilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iiii_dataout <= wire_n1O0ilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iiil_dataout <= wire_n1O0iliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iiiO_dataout <= wire_n1O0illi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iili_dataout <= wire_n1O0illl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iill_dataout <= wire_n1O0illO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iilO_dataout <= wire_n1O0ilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iiOi_dataout <= wire_n1O0ilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iiOl_dataout <= wire_n1O0ilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0iiOO_dataout <= wire_n1O0iO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0il0i_dataout <= wire_n1O0iO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0il0l_dataout <= wire_n1O0iO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0il0O_dataout <= wire_n1O0iOii_dataout OR niOlii10O; + wire_n1O0il1i_dataout <= wire_n1O0iO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0il1l_dataout <= wire_n1O0iO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0il1O_dataout <= wire_n1O0iO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0ilii_dataout <= wire_n1O0iOil_dataout OR niOlii10O; + wire_n1O0ilil_dataout <= wire_n1O0iOiO_dataout OR niOlii10O; + wire_n1O0iliO_dataout <= wire_n1O0iOli_dataout OR niOlii10O; + wire_n1O0illi_dataout <= wire_n1O0iOll_dataout OR niOlii10O; + wire_n1O0illl_dataout <= wire_n1O0iOlO_dataout OR niOlii10O; + wire_n1O0illO_dataout <= wire_n1O0iOOi_dataout OR niOlii10O; + wire_n1O0ilOi_dataout <= wire_n1O0iOOl_dataout OR niOlii10O; + wire_n1O0ilOl_dataout <= wire_n1O0iOOO_dataout OR niOlii10O; + wire_n1O0ilOO_dataout <= wire_n1O0l11i_dataout OR niOlii10O; + wire_n1O0iO0i_dataout <= wire_n1O0l10l_dataout OR niOlii10O; + wire_n1O0iO0l_dataout <= wire_n1O0l10O_dataout OR niOlii10O; + wire_n1O0iO0O_dataout <= wire_n1O0l1ii_dataout OR niOlii10O; + wire_n1O0iO1i_dataout <= wire_n1O0l11l_dataout OR niOlii10O; + wire_n1O0iO1l_dataout <= wire_n1O0l11O_dataout OR niOlii10O; + wire_n1O0iO1O_dataout <= wire_n1O0l10i_dataout OR niOlii10O; + wire_n1O0iOii_dataout <= n1O0i1iO WHEN niOlii1ii = '1' ELSE n1O0i0lO; + wire_n1O0iOil_dataout <= n1O0i00l WHEN niOlii1ii = '1' ELSE n1O0i0Oi; + wire_n1O0iOiO_dataout <= n1O0i00O WHEN niOlii1ii = '1' ELSE n1O0i0Ol; + wire_n1O0iOli_dataout <= n1O0i0ii WHEN niOlii1ii = '1' ELSE (n1O0i0OO XOR n1O0i0lO); + wire_n1O0iOll_dataout <= n1O0i0il WHEN niOlii1ii = '1' ELSE (n1O0i0lO XOR (n1O0ii1i XOR n1O0i0Oi)); + wire_n1O0iOlO_dataout <= n1O0i0iO WHEN niOlii1ii = '1' ELSE (n1O0i0lO XOR (n1O0i0Oi XOR (n1O0ii1l XOR n1O0i0Ol))); + wire_n1O0iOOi_dataout <= n1O0i0li WHEN niOlii1ii = '1' ELSE (n1O0i0Oi XOR (n1O0i0Ol XOR (n1O0ii1O XOR n1O0i0OO))); + wire_n1O0iOOl_dataout <= n1O0i0ll WHEN niOlii1ii = '1' ELSE (n1O0i0Ol XOR (n1O0i0OO XOR (n1O0ii0i XOR n1O0ii1i))); + wire_n1O0iOOO_dataout <= n1O0i0lO WHEN niOlii1ii = '1' ELSE (n1O0i0OO XOR (n1O0ii1i XOR (n1O0ii1l XOR n1O0i1iO))); + wire_n1O0l0l_dataout <= niOO0il0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_n1O0l10i_dataout <= n1O0ii1i WHEN niOlii1ii = '1' ELSE (n1O0ii0i XOR n1O0i0il); + wire_n1O0l10l_dataout <= n1O0ii1l WHEN niOlii1ii = '1' ELSE n1O0i0iO; + wire_n1O0l10O_dataout <= n1O0ii1O WHEN niOlii1ii = '1' ELSE n1O0i0li; + wire_n1O0l11i_dataout <= n1O0i0Oi WHEN niOlii1ii = '1' ELSE (n1O0ii1i XOR (n1O0ii1l XOR (n1O0ii1O XOR n1O0i00l))); + wire_n1O0l11l_dataout <= n1O0i0Ol WHEN niOlii1ii = '1' ELSE (n1O0ii1l XOR (n1O0ii1O XOR (n1O0ii0i XOR n1O0i00O))); + wire_n1O0l11O_dataout <= n1O0i0OO WHEN niOlii1ii = '1' ELSE (n1O0ii1O XOR (n1O0ii0i XOR n1O0i0ii)); + wire_n1O0l1ii_dataout <= n1O0ii0i WHEN niOlii1ii = '1' ELSE n1O0i0ll; + wire_n1O0lii_dataout <= rx_ready_vc1 AND NOT(wire_niO01l0O_dataout); + wire_n1O0lli_dataout <= wire_n1lO0Ol_w_lg_dataout3599w(0) WHEN (k_gbl_hip(33) OR k_hip(22)) = '1' ELSE wire_n1O0lll_dataout; + wire_n1O0lll_dataout <= wire_n1O0llO_dataout OR NOT(wire_n1lO0Ol_dataout); + wire_n1O0llO_dataout <= (n1O0l0O AND niOO0i01l) AND NOT(niOO0i01i); + wire_n1O0O0ll_dataout <= wire_niO10O1O_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0O0lO_dataout <= wire_n1O0i01O_dataout AND wire_niO10lOl_w_lg_dataout18444w(0); + wire_n1O0O0Oi_dataout <= wire_n1O0i01i_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0O0Ol_dataout <= wire_n1O0i1Ol_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0O0OO_dataout <= wire_n1O0i1lO_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0Oi0i_dataout <= wire_n1O0i11l_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0Oi1i_dataout <= wire_n1O0i1li_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0Oi1l_dataout <= wire_n1O0i1ii_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0Oi1O_dataout <= wire_n1O0i10l_dataout OR NOT(wire_niO10lOl_w_lg_dataout18444w(0)); + wire_n1O0OiiO_dataout <= wire_n1O0OiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0Oili_dataout <= wire_n1O0Ol1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0Oill_dataout <= wire_n1O0Ol1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0OilO_dataout <= wire_n1O0Ol0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0OiOi_dataout <= wire_n1O0OiOl_dataout AND n1Olii0l; + wire_n1O0OiOl_dataout <= n1O0Ol1i OR (n1Olii0l AND n1O0Oi0l); + wire_n1O0Ol0i_dataout <= (n1Ol00li AND (wire_niO10O1l_dataout AND niOliiiii)) AND n1Olii0l; + wire_n1O0Ol1l_dataout <= ((wire_niO10O1l_dataout AND niOliii0O) AND n1O0Oi0O) AND n1Olii0l; + wire_n1O0Ol1O_dataout <= (niOliilii AND n1O0Oiii) AND n1Olii0l; + wire_n1O0OlOl_dataout <= wire_n1O0OO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0OlOO_dataout <= wire_n1Oi11iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0OO0i_dataout <= wire_n1Oi11ii_dataout WHEN niOlii1il = '1' ELSE wire_n1O0OOii_dataout; + wire_n1O0OO0l_dataout <= wire_n1Oi11il_dataout WHEN niOlii1il = '1' ELSE wire_n1O0OOil_dataout; + wire_n1O0OO0O_dataout <= n1O0Oiil WHEN wire_niO01ill_w_lg_n1O0Olli18437w(0) = '1' ELSE wire_n1O0OOll_dataout; + wire_n1O0OO1i_dataout <= wire_n1O0OO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0OO1l_dataout <= wire_n1O0OO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O0OO1O_dataout <= wire_n1O0OO0O_dataout AND NOT(niOlii1il); + wire_n1O0OOii_dataout <= wire_n1O0OOlO_dataout WHEN wire_niO01ill_w_lg_n1O0Olli18437w(0) = '1' ELSE wire_n1O0OOiO_dataout; + wire_n1O0OOil_dataout <= wire_n1O0OOOi_dataout WHEN wire_niO01ill_w_lg_n1O0Olli18437w(0) = '1' ELSE wire_n1O0OOli_dataout; + wire_n1O0OOiO_dataout <= wire_n1Oi111O_dataout WHEN niOliiiOl = '1' ELSE wire_n1O0OOlO_dataout; + wire_n1O0OOli_dataout <= wire_n1Oi110i_dataout WHEN niOliiiOl = '1' ELSE wire_n1O0OOOi_dataout; + wire_n1O0OOll_dataout <= wire_n1Oi110l_dataout WHEN niOliiiOl = '1' ELSE n1O0Oiil; + wire_n1O0OOlO_dataout <= n1O0Olll AND NOT(niOlii1li); + wire_n1O0OOOi_dataout <= n1O0OllO AND NOT(niOlii1li); + wire_n1O1000i_dataout <= wire_n1O1i01i_dataout AND NOT(niOli0OOO); + wire_n1O1000l_dataout <= wire_n1O1i01l_dataout AND NOT(niOli0OOO); + wire_n1O1000O_dataout <= wire_n1O1i01O_dataout AND NOT(niOli0OOO); + wire_n1O1001i_dataout <= wire_n1O1i1Oi_dataout AND NOT(niOli0OOO); + wire_n1O1001l_dataout <= wire_n1O1i1Ol_dataout AND NOT(niOli0OOO); + wire_n1O1001O_dataout <= wire_n1O1i1OO_dataout AND NOT(niOli0OOO); + wire_n1O100ii_dataout <= wire_n1O1i00i_dataout AND NOT(niOli0OOO); + wire_n1O100il_dataout <= wire_n1O1i00l_dataout AND NOT(niOli0OOO); + wire_n1O100iO_dataout <= wire_n1O1i00O_dataout AND NOT(niOli0OOO); + wire_n1O100li_dataout <= wire_n1O1i0ii_dataout AND NOT(niOli0OOO); + wire_n1O100ll_dataout <= wire_n1O1i0il_dataout AND NOT(niOli0OOO); + wire_n1O100lO_dataout <= wire_n1O1i0iO_dataout AND NOT(niOli0OOO); + wire_n1O100Oi_dataout <= wire_n1O1i0li_dataout AND NOT(niOli0OOO); + wire_n1O100Ol_dataout <= wire_n1O1i0ll_dataout AND NOT(niOli0OOO); + wire_n1O100OO_dataout <= wire_n1O1i0lO_dataout AND NOT(niOli0OOO); + wire_n1O1010i_dataout <= wire_n1O1i11i_dataout AND NOT(niOli0OOO); + wire_n1O1010l_dataout <= wire_n1O1i11l_dataout AND NOT(niOli0OOO); + wire_n1O1010O_dataout <= wire_n1O1i11O_dataout AND NOT(niOli0OOO); + wire_n1O1011i_dataout <= wire_n1O10OOi_dataout AND NOT(niOli0OOO); + wire_n1O1011l_dataout <= wire_n1O10OOl_dataout AND NOT(niOli0OOO); + wire_n1O1011O_dataout <= wire_n1O10OOO_dataout AND NOT(niOli0OOO); + wire_n1O101i_dataout <= niOO00OlO AND NOT(wire_niO01l0O_dataout); + wire_n1O101ii_dataout <= wire_n1O1i10i_dataout AND NOT(niOli0OOO); + wire_n1O101il_dataout <= wire_n1O1i10l_dataout AND NOT(niOli0OOO); + wire_n1O101iO_dataout <= wire_n1O1i10O_dataout AND NOT(niOli0OOO); + wire_n1O101l_dataout <= n1lOi0i WHEN ((((NOT (niOO00OiO XOR niOO00Oii)) AND (NOT (niOO00Oli XOR niOO00Oil))) AND (NOT (niOO00OOl XOR niOO00Oll))) AND (NOT (n1lOO1l XOR n1lOlOi))) = '1' ELSE wire_n1O101O_o; + wire_n1O101li_dataout <= wire_n1O1i1ii_dataout AND NOT(niOli0OOO); + wire_n1O101ll_dataout <= wire_n1O1i1il_dataout AND NOT(niOli0OOO); + wire_n1O101lO_dataout <= wire_n1O1i1iO_dataout AND NOT(niOli0OOO); + wire_n1O101Oi_dataout <= wire_n1O1i1li_dataout AND NOT(niOli0OOO); + wire_n1O101Ol_dataout <= wire_n1O1i1ll_dataout AND NOT(niOli0OOO); + wire_n1O101OO_dataout <= wire_n1O1i1lO_dataout AND NOT(niOli0OOO); + wire_n1O10i0i_dataout <= wire_n1O1ii1i_dataout AND NOT(niOli0OOO); + wire_n1O10i0l_dataout <= wire_n1O1ii1l_dataout AND NOT(niOli0OOO); + wire_n1O10i0O_dataout <= wire_n1O1ii1O_dataout AND NOT(niOli0OOO); + wire_n1O10i1i_dataout <= wire_n1O1i0Oi_dataout AND NOT(niOli0OOO); + wire_n1O10i1l_dataout <= wire_n1O1i0Ol_dataout AND NOT(niOli0OOO); + wire_n1O10i1O_dataout <= wire_n1O1i0OO_dataout AND NOT(niOli0OOO); + wire_n1O10iii_dataout <= wire_n1O1ii0i_dataout AND NOT(niOli0OOO); + wire_n1O10iil_dataout <= wire_n1O1ii0l_dataout AND NOT(niOli0OOO); + wire_n1O10iiO_dataout <= wire_n1O1ii0O_dataout AND NOT(niOli0OOO); + wire_n1O10ili_dataout <= wire_n1O1iiii_dataout AND NOT(niOli0OOO); + wire_n1O10ill_dataout <= wire_n1O1iiil_dataout AND NOT(niOli0OOO); + wire_n1O10ilO_dataout <= wire_n1O1iiiO_dataout AND NOT(niOli0OOO); + wire_n1O10iOi_dataout <= wire_n1O1iili_dataout AND NOT(niOli0OOO); + wire_n1O10iOl_dataout <= wire_n1O1iill_dataout AND NOT(niOli0OOO); + wire_n1O10iOO_dataout <= wire_n1O1iilO_dataout AND NOT(niOli0OOO); + wire_n1O10l0i_dataout <= wire_n1O1il1i_dataout AND NOT(niOli0OOO); + wire_n1O10l0l_dataout <= wire_n1O1il1l_dataout AND NOT(niOli0OOO); + wire_n1O10l0O_dataout <= wire_n1O1il1O_dataout AND NOT(niOli0OOO); + wire_n1O10l1i_dataout <= wire_n1O1iiOi_dataout AND NOT(niOli0OOO); + wire_n1O10l1l_dataout <= wire_n1O1iiOl_dataout AND NOT(niOli0OOO); + wire_n1O10l1O_dataout <= wire_n1O1iiOO_dataout AND NOT(niOli0OOO); + wire_n1O10lii_dataout <= wire_n1O1il0i_dataout AND NOT(niOli0OOO); + wire_n1O10lil_dataout <= wire_n1O1il0l_dataout AND NOT(niOli0OOO); + wire_n1O10liO_dataout <= wire_n1O1il0O_dataout AND NOT(niOli0OOO); + wire_n1O10lli_dataout <= wire_n1O1ilii_dataout AND NOT(niOli0OOO); + wire_n1O10lll_dataout <= wire_n1O1ilil_dataout AND NOT(niOli0OOO); + wire_n1O10llO_dataout <= wire_n1O1iliO_dataout AND NOT(niOli0OOO); + wire_n1O10lOi_dataout <= wire_n1O1illi_dataout AND NOT(niOli0OOO); + wire_n1O10lOl_dataout <= wire_n1O1illl_dataout AND NOT(niOli0OOO); + wire_n1O10lOO_dataout <= wire_n1O1illO_dataout AND NOT(niOli0OOO); + wire_n1O10O0i_dataout <= wire_n1O1iO1i_dataout AND NOT(niOli0OOO); + wire_n1O10O0l_dataout <= wire_n1O1iO1l_dataout AND NOT(niOli0OOO); + wire_n1O10O0O_dataout <= wire_n1O1iO1O_dataout AND NOT(niOli0OOO); + wire_n1O10O1i_dataout <= wire_n1O1ilOi_dataout AND NOT(niOli0OOO); + wire_n1O10O1l_dataout <= wire_n1O1ilOl_dataout AND NOT(niOli0OOO); + wire_n1O10O1O_dataout <= wire_n1O1ilOO_dataout AND NOT(niOli0OOO); + wire_n1O10Oii_dataout <= wire_nlOiOl11O_dataout WHEN n1lO0lOi = '1' ELSE n1lOi0il; + wire_n1O10Oil_dataout <= wire_nlOiOi1Ol_dataout WHEN n1lO0lOi = '1' ELSE n1lOO11l; + wire_n1O10OiO_dataout <= wire_nlOiOi1OO_dataout WHEN n1lO0lOi = '1' ELSE n1lOO11O; + wire_n1O10Oli_dataout <= wire_nlOiOi01i_dataout WHEN n1lO0lOi = '1' ELSE n1lOO10i; + wire_n1O10Oll_dataout <= wire_nlOiOi01l_dataout WHEN n1lO0lOi = '1' ELSE n1lOO10l; + wire_n1O10OlO_dataout <= wire_nlOiOi01O_dataout WHEN n1lO0lOi = '1' ELSE n1lOO10O; + wire_n1O10OOi_dataout <= wire_nlOiOi00i_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1ii; + wire_n1O10OOl_dataout <= wire_nlOiOi00l_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1il; + wire_n1O10OOO_dataout <= wire_nlOiOi00O_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1iO; + wire_n1O1100i_dataout <= wire_n1O1001i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1100l_dataout <= wire_n1O1001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1100O_dataout <= wire_n1O1001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1101i_dataout <= wire_n1O101Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1101l_dataout <= wire_n1O101Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1101O_dataout <= wire_n1O101OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110i_dataout <= n1lOliO AND NOT(wire_niO01l0O_dataout); + wire_n1O110ii_dataout <= wire_n1O1000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110il_dataout <= wire_n1O1000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110iO_dataout <= wire_n1O1000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110l_dataout <= n1lOlli AND NOT(wire_niO01l0O_dataout); + wire_n1O110li_dataout <= wire_n1O100ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110ll_dataout <= wire_n1O100il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110lO_dataout <= wire_n1O100iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110O_dataout <= n1lOlll AND NOT(wire_niO01l0O_dataout); + wire_n1O110Oi_dataout <= wire_n1O100li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110Ol_dataout <= wire_n1O100ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O110OO_dataout <= wire_n1O100lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1110i_dataout <= wire_n1O1011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1110l_dataout <= wire_n1O1011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1110O_dataout <= wire_n1O1011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1111i_dataout <= wire_n1O11OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1111l_dataout <= wire_n1O11OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O1111O_dataout <= wire_n1O11OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111i_dataout <= n1lOl0O AND NOT(wire_niO01l0O_dataout); + wire_n1O111ii_dataout <= wire_n1O1010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111il_dataout <= wire_n1O1010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111iO_dataout <= wire_n1O1010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111l_dataout <= n1lOlii AND NOT(wire_niO01l0O_dataout); + wire_n1O111li_dataout <= wire_n1O101ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111ll_dataout <= wire_n1O101il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111lO_dataout <= wire_n1O101iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111O_dataout <= n1lOlil AND NOT(wire_niO01l0O_dataout); + wire_n1O111Oi_dataout <= wire_n1O101li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111Ol_dataout <= wire_n1O101ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O111OO_dataout <= wire_n1O101lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11i0i_dataout <= wire_n1O10i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11i0l_dataout <= wire_n1O10i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11i0O_dataout <= wire_n1O10i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11i1i_dataout <= wire_n1O100Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11i1l_dataout <= wire_n1O100Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11i1O_dataout <= wire_n1O100OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11ii_dataout <= n1lOllO AND NOT(wire_niO01l0O_dataout); + wire_n1O11iii_dataout <= wire_n1O10i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11iil_dataout <= wire_n1O10i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11iiO_dataout <= wire_n1O10i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11il_dataout <= n1lOlOi AND NOT(wire_niO01l0O_dataout); + wire_n1O11ili_dataout <= wire_n1O10iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11ill_dataout <= wire_n1O10iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11ilO_dataout <= wire_n1O10iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11iO_dataout <= n1lO00O AND NOT(wire_niO01l0O_dataout); + wire_n1O11iOi_dataout <= wire_n1O10ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11iOl_dataout <= wire_n1O10ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11iOO_dataout <= wire_n1O10ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11l0i_dataout <= wire_n1O10l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11l0l_dataout <= wire_n1O10l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11l0O_dataout <= wire_n1O10l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11l1i_dataout <= wire_n1O10iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11l1l_dataout <= wire_n1O10iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11l1O_dataout <= wire_n1O10iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11li_dataout <= n1lO00l AND NOT(wire_niO01l0O_dataout); + wire_n1O11lii_dataout <= wire_n1O10l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11lil_dataout <= wire_n1O10l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11liO_dataout <= wire_n1O10l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11ll_dataout <= n1lO01i AND NOT(wire_niO01l0O_dataout); + wire_n1O11lli_dataout <= wire_n1O10lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11lll_dataout <= wire_n1O10lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11llO_dataout <= wire_n1O10liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11lO_dataout <= n1lOO0i AND NOT(wire_niO01l0O_dataout); + wire_n1O11lOi_dataout <= wire_n1O10lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11lOl_dataout <= wire_n1O10lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11lOO_dataout <= wire_n1O10llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11O0i_dataout <= wire_n1O10O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11O0l_dataout <= wire_n1O10O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11O0O_dataout <= wire_n1O10O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11O1i_dataout <= wire_n1O10lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11O1l_dataout <= wire_n1O10lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11O1O_dataout <= wire_n1O10lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11Oi_dataout <= niOO0i11O AND NOT(wire_niO01l0O_dataout); + wire_n1O11Oii_dataout <= wire_n1O10O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11Oil_dataout <= wire_n1O10O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11OiO_dataout <= wire_n1O10O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1O11Ol_dataout <= niOO0i11i AND NOT(wire_niO01l0O_dataout); + wire_n1O11Oli_dataout <= wire_n1O10Oii_dataout AND NOT(niOli0OOO); + wire_n1O11Oll_dataout <= wire_n1O10Oil_dataout AND NOT(niOli0OOO); + wire_n1O11OlO_dataout <= wire_n1O10OiO_dataout AND NOT(niOli0OOO); + wire_n1O11OO_dataout <= niOO00OOi AND NOT(wire_niO01l0O_dataout); + wire_n1O11OOi_dataout <= wire_n1O10Oli_dataout AND NOT(niOli0OOO); + wire_n1O11OOl_dataout <= wire_n1O10Oll_dataout AND NOT(niOli0OOO); + wire_n1O11OOO_dataout <= wire_n1O10OlO_dataout AND NOT(niOli0OOO); + wire_n1O1i00i_dataout <= wire_n1O1liOO_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0Oi; + wire_n1O1i00l_dataout <= wire_n1O1ll1O_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0Ol; + wire_n1O1i00O_dataout <= wire_n1O1ll0i_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0OO; + wire_n1O1i01i_dataout <= wire_n1O1l0ll_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0li; + wire_n1O1i01l_dataout <= wire_n1O1l0lO_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0ll; + wire_n1O1i01O_dataout <= wire_n1O1l0Oi_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0lO; + wire_n1O1i0ii_dataout <= wire_n1O1ll0l_dataout WHEN n1lO0lOi = '1' ELSE n1lOOi1i; + wire_n1O1i0il_dataout <= wire_n1O1ll0O_dataout WHEN n1lO0lOi = '1' ELSE n1lOOi1l; + wire_n1O1i0iO_dataout <= wire_n1O1llii_dataout WHEN n1lO0lOi = '1' ELSE n1lOOi1O; + wire_n1O1i0li_dataout <= wire_n1O1llil_dataout WHEN n1lO0lOi = '1' ELSE n1lOOi0i; + wire_n1O1i0ll_dataout <= wire_n1O1lliO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOi0l; + wire_n1O1i0lO_dataout <= wire_n1O1llli_dataout WHEN n1lO0lOi = '1' ELSE n1lOOi0O; + wire_n1O1i0Oi_dataout <= wire_n1O1lOlO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOiii; + wire_n1O1i0Ol_dataout <= wire_n1O1lOOO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOiil; + wire_n1O1i0OO_dataout <= wire_n1O1O11i_dataout WHEN n1lO0lOi = '1' ELSE n1lOOiiO; + wire_n1O1i10i_dataout <= wire_n1O1iOll_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1Oi; + wire_n1O1i10l_dataout <= wire_n1O1iOlO_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1Ol; + wire_n1O1i10O_dataout <= wire_n1O1iOOi_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1OO; + wire_n1O1i11i_dataout <= wire_n1O1iO0O_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1li; + wire_n1O1i11l_dataout <= wire_n1O1iOiO_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1ll; + wire_n1O1i11O_dataout <= wire_n1O1iOli_dataout WHEN n1lO0lOi = '1' ELSE n1lOO1lO; + wire_n1O1i1ii_dataout <= wire_n1O1iOOl_dataout WHEN n1lO0lOi = '1' ELSE n1lOO01i; + wire_n1O1i1il_dataout <= wire_n1O1iOOO_dataout WHEN n1lO0lOi = '1' ELSE n1lOO01l; + wire_n1O1i1iO_dataout <= wire_n1O1l11i_dataout WHEN n1lO0lOi = '1' ELSE n1lOO01O; + wire_n1O1i1li_dataout <= wire_n1O1l01O_dataout WHEN n1lO0lOi = '1' ELSE n1lOO00i; + wire_n1O1i1ll_dataout <= wire_n1O1l00O_dataout WHEN n1lO0lOi = '1' ELSE n1lOO00l; + wire_n1O1i1lO_dataout <= wire_n1O1l0ii_dataout WHEN n1lO0lOi = '1' ELSE n1lOO00O; + wire_n1O1i1Oi_dataout <= wire_n1O1l0il_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0ii; + wire_n1O1i1Ol_dataout <= wire_n1O1l0iO_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0il; + wire_n1O1i1OO_dataout <= wire_n1O1l0li_dataout WHEN n1lO0lOi = '1' ELSE n1lOO0iO; + wire_n1O1ii0i_dataout <= wire_n1O1O10l_dataout WHEN n1lO0lOi = '1' ELSE n1lOOiOi; + wire_n1O1ii0l_dataout <= wire_n1O1O10O_dataout WHEN n1lO0lOi = '1' ELSE n1lOOiOl; + wire_n1O1ii0O_dataout <= wire_n1O1O1ii_dataout WHEN n1lO0lOi = '1' ELSE n1lOOiOO; + wire_n1O1ii1i_dataout <= wire_n1O1O11l_dataout WHEN n1lO0lOi = '1' ELSE n1lOOili; + wire_n1O1ii1l_dataout <= wire_n1O1O11O_dataout WHEN n1lO0lOi = '1' ELSE n1lOOill; + wire_n1O1ii1O_dataout <= wire_n1O1O10i_dataout WHEN n1lO0lOi = '1' ELSE n1lOOilO; + wire_n1O1iiii_dataout <= wire_n1O1O0iO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOl1i; + wire_n1O1iiil_dataout <= wire_n1O1O0lO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOl1l; + wire_n1O1iiiO_dataout <= wire_n1O1O0Oi_dataout WHEN n1lO0lOi = '1' ELSE n1lOOl1O; + wire_n1O1iili_dataout <= wire_n1O1O0Ol_dataout WHEN n1lO0lOi = '1' ELSE n1lOOl0i; + wire_n1O1iill_dataout <= wire_n1O1O0OO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOl0l; + wire_n1O1iilO_dataout <= wire_n1O1Oi1i_dataout WHEN n1lO0lOi = '1' ELSE n1lOOl0O; + wire_n1O1iiOi_dataout <= wire_n1O1Oi1l_dataout WHEN n1lO0lOi = '1' ELSE n1lOOlii; + wire_n1O1iiOl_dataout <= wire_n1O1Oi1O_dataout WHEN n1lO0lOi = '1' ELSE n1lOOlil; + wire_n1O1iiOO_dataout <= wire_n1O1Oi0i_dataout WHEN n1lO0lOi = '1' ELSE n1lOOliO; + wire_n1O1il0i_dataout <= wire_n1O1Olll_dataout WHEN n1lO0lOi = '1' ELSE n1lOOlOi; + wire_n1O1il0l_dataout <= wire_n1O1OllO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOlOl; + wire_n1O1il0O_dataout <= wire_n1O1OlOi_dataout WHEN n1lO0lOi = '1' ELSE n1lOOlOO; + wire_n1O1il1i_dataout <= wire_n1O1Ol0O_dataout WHEN n1lO0lOi = '1' ELSE n1lOOlli; + wire_n1O1il1l_dataout <= wire_n1O1OliO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOlll; + wire_n1O1il1O_dataout <= wire_n1O1Olli_dataout WHEN n1lO0lOi = '1' ELSE n1lOOllO; + wire_n1O1ilii_dataout <= wire_n1O1OlOl_dataout WHEN n1lO0lOi = '1' ELSE n1lOOO1i; + wire_n1O1ilil_dataout <= wire_n1O1OlOO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOO1l; + wire_n1O1iliO_dataout <= wire_n1O1OO1i_dataout WHEN n1lO0lOi = '1' ELSE n1lOOO1O; + wire_n1O1illi_dataout <= wire_n1O0111O_dataout WHEN n1lO0lOi = '1' ELSE n1lOOO0i; + wire_n1O1illl_dataout <= wire_n1O0110i_dataout WHEN n1lO0lOi = '1' ELSE n1lOOO0l; + wire_n1O1illO_dataout <= wire_n1O0110l_dataout WHEN n1lO0lOi = '1' ELSE n1lOOO0O; + wire_n1O1ilOi_dataout <= wire_n1O0110O_dataout WHEN n1lO0lOi = '1' ELSE n1lOOOii; + wire_n1O1ilOl_dataout <= wire_n1O011ii_dataout WHEN n1lO0lOi = '1' ELSE n1lOOOil; + wire_n1O1ilOO_dataout <= wire_n1O011il_dataout WHEN n1lO0lOi = '1' ELSE n1lOOOiO; + wire_n1O1iO0O_dataout <= wire_nlOiOl10i_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1iOii_dataout; + wire_n1O1iO1i_dataout <= wire_n1O011iO_dataout WHEN n1lO0lOi = '1' ELSE n1lOOOli; + wire_n1O1iO1l_dataout <= wire_n1O011li_dataout WHEN n1lO0lOi = '1' ELSE n1lOOOll; + wire_n1O1iO1O_dataout <= wire_n1O011ll_dataout WHEN n1lO0lOi = '1' ELSE n1lOOOlO; + wire_n1O1iOii_dataout <= wire_nlOiOl10i_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1iOil_dataout; + wire_n1O1iOil_dataout <= wire_nlOiOl1ii_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOlli; + wire_n1O1iOiO_dataout <= wire_nlOiOi0ii_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l11l_dataout; + wire_n1O1iOli_dataout <= wire_nlOiOi0il_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l11O_dataout; + wire_n1O1iOll_dataout <= wire_nlOiOi0iO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l10i_dataout; + wire_n1O1iOlO_dataout <= wire_nlOiOi0li_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l10l_dataout; + wire_n1O1iOOi_dataout <= wire_nlOiOi0ll_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l10O_dataout; + wire_n1O1iOOl_dataout <= wire_nlOiOi0lO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l1ii_dataout; + wire_n1O1iOOO_dataout <= wire_nlOiOi0Oi_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l1il_dataout; + wire_n1O1l00i_dataout <= wire_nlOiOl1ii_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l00l_dataout; + wire_n1O1l00l_dataout <= wire_nlOiOl10l_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOiii; + wire_n1O1l00O_dataout <= wire_nlOiOi0OO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l0Ol_dataout; + wire_n1O1l01i_dataout <= wire_nlOiOilii_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOO1l; + wire_n1O1l01l_dataout <= wire_nlOiOilil_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOO1O; + wire_n1O1l01O_dataout <= wire_nlOiOl10l_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l00i_dataout; + wire_n1O1l0ii_dataout <= wire_nlOiOii1i_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l0OO_dataout; + wire_n1O1l0il_dataout <= wire_nlOiOii1l_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1li1i_dataout; + wire_n1O1l0iO_dataout <= wire_nlOiOii1O_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1li1l_dataout; + wire_n1O1l0li_dataout <= wire_nlOiOii0i_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1li1O_dataout; + wire_n1O1l0ll_dataout <= wire_nlOiOii0l_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1li0i_dataout; + wire_n1O1l0lO_dataout <= wire_nlOiOii0O_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1li0l_dataout; + wire_n1O1l0O_dataout <= n1lOlOl AND NOT(wire_niO01O0O_dataout); + wire_n1O1l0Oi_dataout <= wire_nlOiOiiii_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1li0O_dataout; + wire_n1O1l0Ol_dataout <= wire_nlOiOil1i_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1liii_dataout; + wire_n1O1l0OO_dataout <= wire_nlOiOil1l_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1liil_dataout; + wire_n1O1l10i_dataout <= wire_nlOiOi0iO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l1lO_dataout; + wire_n1O1l10l_dataout <= wire_nlOiOi0li_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l1Oi_dataout; + wire_n1O1l10O_dataout <= wire_nlOiOi0ll_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l1Ol_dataout; + wire_n1O1l11i_dataout <= wire_nlOiOi0Ol_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1l1iO_dataout; + wire_n1O1l11l_dataout <= wire_nlOiOi0ii_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l1li_dataout; + wire_n1O1l11O_dataout <= wire_nlOiOi0il_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l1ll_dataout; + wire_n1O1l1ii_dataout <= wire_nlOiOi0lO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l1OO_dataout; + wire_n1O1l1il_dataout <= wire_nlOiOi0Oi_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l01i_dataout; + wire_n1O1l1iO_dataout <= wire_nlOiOi0Ol_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1l01l_dataout; + wire_n1O1l1li_dataout <= wire_nlOiOil1i_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOlll; + wire_n1O1l1ll_dataout <= wire_nlOiOil1l_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOllO; + wire_n1O1l1lO_dataout <= wire_nlOiOil1O_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOlOi; + wire_n1O1l1Oi_dataout <= wire_nlOiOil0i_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOlOl; + wire_n1O1l1Ol_dataout <= wire_nlOiOil0l_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOlOO; + wire_n1O1l1OO_dataout <= wire_nlOiOil0O_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOO1i; + wire_n1O1li0i_dataout <= wire_nlOiOil0O_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lilO_dataout; + wire_n1O1li0l_dataout <= wire_nlOiOilii_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1liOi_dataout; + wire_n1O1li0O_dataout <= wire_nlOiOilil_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1liOl_dataout; + wire_n1O1li1i_dataout <= wire_nlOiOil1O_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1liiO_dataout; + wire_n1O1li1l_dataout <= wire_nlOiOil0i_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lili_dataout; + wire_n1O1li1O_dataout <= wire_nlOiOil0l_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lill_dataout; + wire_n1O1lii_dataout <= n1lOlOO AND NOT(wire_niO01O0O_dataout); + wire_n1O1liii_dataout <= wire_nlOiOi0OO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOiil; + wire_n1O1liil_dataout <= wire_nlOiOii1i_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOiiO; + wire_n1O1liiO_dataout <= wire_nlOiOii1l_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOili; + wire_n1O1lil_dataout <= n1lOO1i AND NOT(wire_niO01O0O_dataout); + wire_n1O1lili_dataout <= wire_nlOiOii1O_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOill; + wire_n1O1lill_dataout <= wire_nlOiOii0i_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOilO; + wire_n1O1lilO_dataout <= wire_nlOiOii0l_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOiOi; + wire_n1O1liO_dataout <= n1lOO1l AND NOT(wire_niO01O0O_dataout); + wire_n1O1liOi_dataout <= wire_nlOiOii0O_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOiOl; + wire_n1O1liOl_dataout <= wire_nlOiOiiii_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOiOO; + wire_n1O1liOO_dataout <= wire_nlOiOl10O_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1ll1i_dataout; + wire_n1O1ll0i_dataout <= wire_nlOiOiiiO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1lllO_dataout; + wire_n1O1ll0l_dataout <= wire_nlOiOiili_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1llOi_dataout; + wire_n1O1ll0O_dataout <= wire_nlOiOiill_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1llOl_dataout; + wire_n1O1ll1i_dataout <= wire_nlOiOl1il_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1ll1l_dataout; + wire_n1O1ll1l_dataout <= wire_nlOiOl1iO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOl1i; + wire_n1O1ll1O_dataout <= wire_nlOiOiiil_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1llll_dataout; + wire_n1O1llii_dataout <= wire_nlOiOiilO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1llOO_dataout; + wire_n1O1llil_dataout <= wire_nlOiOiiOi_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1lO1i_dataout; + wire_n1O1lliO_dataout <= wire_nlOiOiiOl_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1lO1l_dataout; + wire_n1O1llli_dataout <= wire_nlOiOiiOO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1lO1O_dataout; + wire_n1O1llll_dataout <= wire_nlOiOiliO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lO0i_dataout; + wire_n1O1lllO_dataout <= wire_nlOiOilli_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lO0l_dataout; + wire_n1O1llOi_dataout <= wire_nlOiOilll_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lO0O_dataout; + wire_n1O1llOl_dataout <= wire_nlOiOillO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lOii_dataout; + wire_n1O1llOO_dataout <= wire_nlOiOilOi_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lOil_dataout; + wire_n1O1lO0i_dataout <= wire_nlOiOiO1l_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOl1l; + wire_n1O1lO0l_dataout <= wire_nlOiOiO1O_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOl1O; + wire_n1O1lO0O_dataout <= wire_nlOiOiO0i_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOl0i; + wire_n1O1lO1i_dataout <= wire_nlOiOilOl_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lOiO_dataout; + wire_n1O1lO1l_dataout <= wire_nlOiOilOO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lOli_dataout; + wire_n1O1lO1O_dataout <= wire_nlOiOiO1i_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lOll_dataout; + wire_n1O1lOii_dataout <= wire_nlOiOiO0l_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOl0l; + wire_n1O1lOil_dataout <= wire_nlOiOiO0O_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOl0O; + wire_n1O1lOiO_dataout <= wire_nlOiOiOii_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOlii; + wire_n1O1lOli_dataout <= wire_nlOiOiOil_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOlil; + wire_n1O1lOll_dataout <= wire_nlOiOiOiO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOOliO; + wire_n1O1lOlO_dataout <= wire_nlOiOl1ii_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1lOOi_dataout; + wire_n1O1lOOi_dataout <= wire_nlOiOl10l_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1lOOl_dataout; + wire_n1O1lOOl_dataout <= wire_nlOiOl10i_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOi0il; + wire_n1O1lOOO_dataout <= wire_nlOiOil1i_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1il_dataout; + wire_n1O1O00i_dataout <= wire_nlOiOi0li_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO10l; + wire_n1O1O00l_dataout <= wire_nlOiOi0ll_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO10O; + wire_n1O1O00O_dataout <= wire_nlOiOi0lO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1ii; + wire_n1O1O01i_dataout <= wire_nlOiOi0ii_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO11l; + wire_n1O1O01l_dataout <= wire_nlOiOi0il_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO11O; + wire_n1O1O01O_dataout <= wire_nlOiOi0iO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO10i; + wire_n1O1O0ii_dataout <= wire_nlOiOi0Oi_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1il; + wire_n1O1O0il_dataout <= wire_nlOiOi0Ol_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1iO; + wire_n1O1O0iO_dataout <= wire_nlOiOl1il_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O0li_dataout; + wire_n1O1O0li_dataout <= wire_nlOiOl10O_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O0ll_dataout; + wire_n1O1O0ll_dataout <= wire_nlOiOl1il_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1li; + wire_n1O1O0lO_dataout <= wire_nlOiOiliO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1Oi0l_dataout; + wire_n1O1O0Oi_dataout <= wire_nlOiOilli_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1Oi0O_dataout; + wire_n1O1O0Ol_dataout <= wire_nlOiOilll_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1Oiii_dataout; + wire_n1O1O0OO_dataout <= wire_nlOiOillO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1Oiil_dataout; + wire_n1O1O10i_dataout <= wire_nlOiOil0l_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1lO_dataout; + wire_n1O1O10l_dataout <= wire_nlOiOil0O_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1Oi_dataout; + wire_n1O1O10O_dataout <= wire_nlOiOilii_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1Ol_dataout; + wire_n1O1O11i_dataout <= wire_nlOiOil1l_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1iO_dataout; + wire_n1O1O11l_dataout <= wire_nlOiOil1O_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1li_dataout; + wire_n1O1O11O_dataout <= wire_nlOiOil0i_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1ll_dataout; + wire_n1O1O1ii_dataout <= wire_nlOiOilil_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1O1OO_dataout; + wire_n1O1O1il_dataout <= wire_nlOiOi0OO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O01i_dataout; + wire_n1O1O1iO_dataout <= wire_nlOiOii1i_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O01l_dataout; + wire_n1O1O1li_dataout <= wire_nlOiOii1l_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O01O_dataout; + wire_n1O1O1ll_dataout <= wire_nlOiOii1O_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O00i_dataout; + wire_n1O1O1lO_dataout <= wire_nlOiOii0i_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O00l_dataout; + wire_n1O1O1Oi_dataout <= wire_nlOiOii0l_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O00O_dataout; + wire_n1O1O1Ol_dataout <= wire_nlOiOii0O_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O0ii_dataout; + wire_n1O1O1OO_dataout <= wire_nlOiOiiii_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1O0il_dataout; + wire_n1O1Oi0i_dataout <= wire_nlOiOiO1i_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OilO_dataout; + wire_n1O1Oi0l_dataout <= wire_nlOiOiiil_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OiOi_dataout; + wire_n1O1Oi0O_dataout <= wire_nlOiOiiiO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OiOl_dataout; + wire_n1O1Oi1i_dataout <= wire_nlOiOilOi_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OiiO_dataout; + wire_n1O1Oi1l_dataout <= wire_nlOiOilOl_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1Oili_dataout; + wire_n1O1Oi1O_dataout <= wire_nlOiOilOO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1Oill_dataout; + wire_n1O1Oiii_dataout <= wire_nlOiOiili_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OiOO_dataout; + wire_n1O1Oiil_dataout <= wire_nlOiOiill_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1Ol1i_dataout; + wire_n1O1OiiO_dataout <= wire_nlOiOiilO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1Ol1l_dataout; + wire_n1O1Oili_dataout <= wire_nlOiOiiOi_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1Ol1O_dataout; + wire_n1O1Oill_dataout <= wire_nlOiOiiOl_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1Ol0i_dataout; + wire_n1O1OilO_dataout <= wire_nlOiOiiOO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1Ol0l_dataout; + wire_n1O1OiOi_dataout <= wire_nlOiOiliO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1ll; + wire_n1O1OiOl_dataout <= wire_nlOiOilli_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1lO; + wire_n1O1OiOO_dataout <= wire_nlOiOilll_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1Oi; + wire_n1O1Ol0i_dataout <= wire_nlOiOilOO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO01l; + wire_n1O1Ol0l_dataout <= wire_nlOiOiO1i_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO01O; + wire_n1O1Ol0O_dataout <= wire_nlOiOl1iO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1Olii_dataout; + wire_n1O1Ol1i_dataout <= wire_nlOiOillO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1Ol; + wire_n1O1Ol1l_dataout <= wire_nlOiOilOi_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO1OO; + wire_n1O1Ol1O_dataout <= wire_nlOiOilOl_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO01i; + wire_n1O1Olii_dataout <= wire_nlOiOl1iO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1Olil_dataout; + wire_n1O1Olil_dataout <= wire_nlOiOl10O_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO00i; + wire_n1O1OliO_dataout <= wire_nlOiOiO1l_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OO1l_dataout; + wire_n1O1Olli_dataout <= wire_nlOiOiO1O_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OO1O_dataout; + wire_n1O1Olll_dataout <= wire_nlOiOiO0i_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OO0i_dataout; + wire_n1O1OllO_dataout <= wire_nlOiOiO0l_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OO0l_dataout; + wire_n1O1OlO_dataout <= wire_n1O01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_n1O1OlOi_dataout <= wire_nlOiOiO0O_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OO0O_dataout; + wire_n1O1OlOl_dataout <= wire_nlOiOiOii_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OOii_dataout; + wire_n1O1OlOO_dataout <= wire_nlOiOiOil_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OOil_dataout; + wire_n1O1OO0i_dataout <= wire_nlOiOiO0i_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OOlO_dataout; + wire_n1O1OO0l_dataout <= wire_nlOiOiO0l_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OOOi_dataout; + wire_n1O1OO0O_dataout <= wire_nlOiOiO0O_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OOOl_dataout; + wire_n1O1OO1i_dataout <= wire_nlOiOiOiO_dataout WHEN wire_n1lOi1ii_dataout = '1' ELSE wire_n1O1OOiO_dataout; + wire_n1O1OO1l_dataout <= wire_nlOiOiO1l_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OOli_dataout; + wire_n1O1OO1O_dataout <= wire_nlOiOiO1O_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OOll_dataout; + wire_n1O1OOi_dataout <= (wire_n1O000i_o OR (n1O1l0l AND ((((NOT wire_n1O1iOi_o(4)) AND (NOT wire_n1O1iOi_o(3))) AND (NOT wire_n1O1iOi_o(2))) AND (NOT wire_n1O1iOi_o(1))))) AND NOT(wire_niO01O0O_dataout); + wire_n1O1OOii_dataout <= wire_nlOiOiOii_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O1OOOO_dataout; + wire_n1O1OOil_dataout <= wire_nlOiOiOil_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O0111i_dataout; + wire_n1O1OOiO_dataout <= wire_nlOiOiOiO_dataout WHEN wire_n1lOi10O_dataout = '1' ELSE wire_n1O0111l_dataout; + wire_n1O1OOl_dataout <= n1lOOii AND NOT(wire_niO01O0O_dataout); + wire_n1O1OOli_dataout <= wire_nlOiOiiil_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO00l; + wire_n1O1OOll_dataout <= wire_nlOiOiiiO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO00O; + wire_n1O1OOlO_dataout <= wire_nlOiOiili_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO0ii; + wire_n1O1OOO_dataout <= n1lOO1O AND NOT(wire_niO01O0O_dataout); + wire_n1O1OOOi_dataout <= wire_nlOiOiill_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO0il; + wire_n1O1OOOl_dataout <= wire_nlOiOiilO_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO0iO; + wire_n1O1OOOO_dataout <= wire_nlOiOiiOi_dataout WHEN wire_n1lOi10l_dataout = '1' ELSE n1lOO0li; + wire_n1Oi000l_dataout <= wire_n1Oiii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi000O_dataout <= wire_n1Oiii0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00ii_dataout <= wire_n1Oiii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00il_dataout <= ((niOliiiOl OR niOliiiOi) OR niOliiilO) AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00iO_dataout <= (n1Ol00li AND (niOliilii OR niOliil1O)) AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00li_dataout <= wire_n1Oi0O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00ll_dataout <= wire_n1Oi0Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00lO_dataout <= wire_n1Oi0Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00Oi_dataout <= wire_n1Oi0OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00Ol_dataout <= wire_n1Oi0Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi00OO_dataout <= wire_n1Oi0Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0i0i_dataout <= wire_n1Oiiiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0i0l_dataout <= wire_n1OiiiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0i0O_dataout <= wire_n1Oiiili_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0i1i_dataout <= wire_n1Oi0OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0i1l_dataout <= wire_n1Oi0OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0i1O_dataout <= wire_n1Oiiiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0iii_dataout <= wire_n1Oiiill_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0iil_dataout <= wire_n1OiiilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0iiO_dataout <= wire_n1OiiiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0ili_dataout <= wire_n1OiiiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0ill_dataout <= wire_n1OiiiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0ilO_dataout <= wire_n1Oiil1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0iOi_dataout <= wire_n1Oiil1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0iOl_dataout <= wire_n1Oiil1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0iOO_dataout <= wire_n1Oiil0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0l0i_dataout <= wire_n1Oiilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0l0l_dataout <= wire_n1OiiliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0l0O_dataout <= wire_n1Oii00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0l1i_dataout <= wire_n1Oiil0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0l1l_dataout <= wire_n1Oiil0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0l1O_dataout <= wire_n1Oiilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0lii_dataout <= wire_n1Oii0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0lil_dataout <= wire_n1Oii0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0liO_dataout <= wire_n1Oii0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0lli_dataout <= wire_n1Oii0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0lll_dataout <= wire_n1Oiilli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0llO_dataout <= wire_n1Oii0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0lOi_dataout <= wire_n1Oii0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0lOl_dataout <= wire_n1Oii0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0lOO_dataout <= wire_n1Oii0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0O0i_dataout <= wire_n1Oiii1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0O0l_dataout <= wire_n1Oiilll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0O0O_dataout <= wire_n1Oi0OOl_dataout AND NOT(niOlii00i); + wire_n1Oi0O1i_dataout <= wire_n1Oii0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0O1l_dataout <= wire_n1Oiii1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0O1O_dataout <= wire_n1Oiii1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi0Oii_dataout <= wire_n1Oi0OOO_dataout AND NOT(niOlii00i); + wire_n1Oi0Oil_dataout <= wire_n1Oii11i_dataout AND NOT(niOlii00i); + wire_n1Oi0OiO_dataout <= wire_n1Oii11l_dataout AND NOT(niOlii00i); + wire_n1Oi0Oli_dataout <= wire_n1Oii11O_dataout AND NOT(niOlii00i); + wire_n1Oi0Oll_dataout <= wire_n1Oii10i_dataout AND NOT(niOlii00i); + wire_n1Oi0OlO_dataout <= wire_n1Oii10l_dataout AND NOT(niOlii00i); + wire_n1Oi0OOi_dataout <= wire_n1Oii10O_dataout AND NOT(niOlii00i); + wire_n1Oi0OOl_dataout <= wire_n1Oii1ii_dataout OR niOlii01O; + wire_n1Oi0OOO_dataout <= wire_n1Oii1il_dataout AND NOT(niOlii01O); + wire_n1Oi100i_dataout <= wire_n1Oi10li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi100l_dataout <= wire_n1Oi10ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Oi100O_dataout <= wire_n1Oi10lO_dataout OR wire_niO01lOO_dataout; + wire_n1Oi10ii_dataout <= wire_n1Oi10Oi_dataout OR wire_niO01lOO_dataout; + wire_n1Oi10il_dataout <= wire_n1Oi10Ol_dataout OR wire_niO01lOO_dataout; + wire_n1Oi10iO_dataout <= wire_n1Oi10OO_dataout OR wire_niO01lOO_dataout; + wire_n1Oi10li_dataout <= wire_n1Oi1i1i_dataout OR niOlii0iO; + wire_n1Oi10ll_dataout <= wire_n1Oi1i1l_dataout AND NOT(niOlii0iO); + wire_n1Oi10lO_dataout <= wire_n1Oi1i1O_dataout OR niOlii0iO; + wire_n1Oi10Oi_dataout <= wire_n1Oi1i0i_dataout AND NOT(niOlii0iO); + wire_n1Oi10Ol_dataout <= wire_n1Oi1i0l_dataout OR niOlii0iO; + wire_n1Oi10OO_dataout <= wire_n1Oi1i0O_dataout OR niOlii0iO; + wire_n1Oi110i_dataout <= n1O0OllO WHEN niOlii1iO = '1' ELSE wire_n1Oi110O_o(1); + wire_n1Oi110l_dataout <= n1O0Oiil OR niOlii1iO; + wire_n1Oi111O_dataout <= n1O0Olll WHEN niOlii1iO = '1' ELSE wire_n1Oi110O_o(0); + wire_n1Oi11ii_dataout <= n1O0Olll OR niOliiiOl; + wire_n1Oi11il_dataout <= n1O0OllO AND NOT(niOliiiOl); + wire_n1Oi11iO_dataout <= wire_n1Oi11li_dataout OR (niOliil0l AND (n1Ol001l OR n1Ol011l)); + wire_n1Oi11li_dataout <= n1O0Olli AND NOT(niOlii1li); + wire_n1Oi1i0i_dataout <= wire_n1Oi1ili_dataout OR NOT(n1O0OlOi); + wire_n1Oi1i0l_dataout <= wire_n1Oi1ill_dataout OR NOT(n1O0OlOi); + wire_n1Oi1i0O_dataout <= wire_n1Oi1ilO_dataout OR NOT(n1O0OlOi); + wire_n1Oi1i1i_dataout <= wire_n1Oi1iii_dataout AND n1O0OlOi; + wire_n1Oi1i1l_dataout <= wire_n1Oi1iil_dataout AND n1O0OlOi; + wire_n1Oi1i1O_dataout <= wire_n1Oi1iiO_dataout OR NOT(n1O0OlOi); + wire_n1Oi1iii_dataout <= n1O0OlOi WHEN niOlii1lO = '1' ELSE wire_n1Oi1iOi_dataout; + wire_n1Oi1iil_dataout <= niOlii1ll AND NOT(niOlii1lO); + wire_n1Oi1iiO_dataout <= wire_n1Oi1iOO_o(1) OR NOT(niOlii1lO); + wire_n1Oi1ili_dataout <= wire_n1Oi1iOO_o(2) OR NOT(niOlii1lO); + wire_n1Oi1ill_dataout <= wire_n1Oi1iOO_o(3) OR NOT(niOlii1lO); + wire_n1Oi1ilO_dataout <= wire_n1Oi1iOO_o(4) OR NOT(niOlii1lO); + wire_n1Oi1iOi_dataout <= n1O0OlOi AND niOlii1ll; + wire_n1Oii00O_dataout <= n1Oi010i WHEN niOlO1O0i = '1' ELSE wire_n1Oil11O_dataout; + wire_n1Oii0ii_dataout <= n1Oi010l WHEN niOlO1O0i = '1' ELSE wire_n1Oil10i_dataout; + wire_n1Oii0il_dataout <= n1Oi010O WHEN niOlO1O0i = '1' ELSE wire_n1Oil10l_dataout; + wire_n1Oii0iO_dataout <= n1Oi01ii WHEN niOlO1O0i = '1' ELSE wire_n1Oil10O_dataout; + wire_n1Oii0li_dataout <= n1Oi01il WHEN niOlO1O0i = '1' ELSE wire_n1Oil1ii_dataout; + wire_n1Oii0ll_dataout <= n1Oi01li WHEN niOlO1O0i = '1' ELSE wire_n1Oil1iO_dataout; + wire_n1Oii0lO_dataout <= n1Oi01ll WHEN niOlO1O0i = '1' ELSE wire_n1Oil1li_dataout; + wire_n1Oii0Oi_dataout <= n1Oi01lO WHEN niOlO1O0i = '1' ELSE wire_n1Oil1ll_dataout; + wire_n1Oii0Ol_dataout <= n1Oi01Oi WHEN niOlO1O0i = '1' ELSE wire_n1Oil1lO_dataout; + wire_n1Oii0OO_dataout <= n1Oi01Ol WHEN niOlO1O0i = '1' ELSE wire_n1Oil1Oi_dataout; + wire_n1Oii10i_dataout <= wire_n1Oii1lO_dataout AND NOT(niOlii01O); + wire_n1Oii10l_dataout <= wire_n1Oii1Oi_dataout AND NOT(niOlii01O); + wire_n1Oii10O_dataout <= wire_n1Oii1Ol_dataout AND NOT(niOlii01O); + wire_n1Oii11i_dataout <= wire_n1Oii1iO_dataout AND NOT(niOlii01O); + wire_n1Oii11l_dataout <= wire_n1Oii1li_dataout AND NOT(niOlii01O); + wire_n1Oii11O_dataout <= wire_n1Oii1ll_dataout AND NOT(niOlii01O); + wire_n1Oii1ii_dataout <= wire_n1Oii1OO_o(0) WHEN niOlii01i = '1' ELSE n1Oi1lil; + wire_n1Oii1il_dataout <= wire_n1Oii1OO_o(1) WHEN niOlii01i = '1' ELSE n1Oi1liO; + wire_n1Oii1iO_dataout <= wire_n1Oii1OO_o(2) WHEN niOlii01i = '1' ELSE n1Oi1lli; + wire_n1Oii1li_dataout <= wire_n1Oii1OO_o(3) WHEN niOlii01i = '1' ELSE n1Oi1lll; + wire_n1Oii1ll_dataout <= wire_n1Oii1OO_o(4) WHEN niOlii01i = '1' ELSE n1Oi1llO; + wire_n1Oii1lO_dataout <= wire_n1Oii1OO_o(5) WHEN niOlii01i = '1' ELSE n1Oi1lOi; + wire_n1Oii1Oi_dataout <= wire_n1Oii1OO_o(6) WHEN niOlii01i = '1' ELSE n1Oi1lOl; + wire_n1Oii1Ol_dataout <= wire_n1Oii1OO_o(7) WHEN niOlii01i = '1' ELSE n1Oi1lOO; + wire_n1Oiii0i_dataout <= wire_n1OiillO_dataout AND NOT(niOlO1O0i); + wire_n1Oiii0l_dataout <= wire_n1OiilOi_dataout AND NOT(niOlO1O0i); + wire_n1Oiii0O_dataout <= wire_n1OiilOl_dataout AND NOT(niOlO1O0i); + wire_n1Oiii1i_dataout <= n1Oi01OO WHEN niOlO1O0i = '1' ELSE wire_n1Oil1Ol_dataout; + wire_n1Oiii1l_dataout <= n1Oi001i WHEN niOlO1O0i = '1' ELSE wire_n1Oil1OO_dataout; + wire_n1Oiii1O_dataout <= n1Oi001l WHEN niOlO1O0i = '1' ELSE wire_n1Oil01i_dataout; + wire_n1Oiiiii_dataout <= wire_n1OiilOO_dataout AND NOT(niOlO1O0i); + wire_n1Oiiiil_dataout <= wire_n1OiiO1i_dataout AND NOT(niOlO1O0i); + wire_n1OiiiiO_dataout <= wire_n1OiiO1l_dataout AND NOT(niOlO1O0i); + wire_n1Oiiili_dataout <= wire_n1OiiO1O_dataout AND NOT(niOlO1O0i); + wire_n1Oiiill_dataout <= wire_n1OiiO0i_dataout AND NOT(niOlO1O0i); + wire_n1OiiilO_dataout <= wire_n1OiiO0l_dataout AND NOT(niOlO1O0i); + wire_n1OiiiOi_dataout <= wire_n1OiiO0O_dataout AND NOT(niOlO1O0i); + wire_n1OiiiOl_dataout <= wire_n1OiiOii_dataout AND NOT(niOlO1O0i); + wire_n1OiiiOO_dataout <= wire_n1OiiOil_dataout AND NOT(niOlO1O0i); + wire_n1Oiil0i_dataout <= wire_n1OiiOlO_dataout AND NOT(niOlO1O0i); + wire_n1Oiil0l_dataout <= wire_n1OiiOOi_dataout AND NOT(niOlO1O0i); + wire_n1Oiil0O_dataout <= wire_n1OiiOOl_dataout AND NOT(niOlO1O0i); + wire_n1Oiil1i_dataout <= wire_n1OiiOiO_dataout AND NOT(niOlO1O0i); + wire_n1Oiil1l_dataout <= wire_n1OiiOli_dataout AND NOT(niOlO1O0i); + wire_n1Oiil1O_dataout <= wire_n1OiiOll_dataout AND NOT(niOlO1O0i); + wire_n1Oiilii_dataout <= wire_n1OiiOOO_dataout AND NOT(niOlO1O0i); + wire_n1Oiilil_dataout <= wire_n1Oil11i_dataout AND NOT(niOlO1O0i); + wire_n1OiiliO_dataout <= wire_n1Oil11l_dataout AND NOT(niOlO1O0i); + wire_n1Oiilli_dataout <= wire_n1Oil1il_dataout AND NOT(niOlO1O0i); + wire_n1Oiilll_dataout <= wire_n1Oil01l_dataout AND NOT(niOlO1O0i); + wire_n1OiillO_dataout <= n1Oi000i WHEN n1Oiliii = '1' ELSE n1Oi101O; + wire_n1OiilOi_dataout <= n1Oili0i WHEN n1Oiliii = '1' ELSE n1Oi1l0i; + wire_n1OiilOl_dataout <= n1Oili0l WHEN n1Oiliii = '1' ELSE n1Oi1l0l; + wire_n1OiilOO_dataout <= n1OiliiO WHEN n1Oiliii = '1' ELSE n1Oi1O1i; + wire_n1OiiO0i_dataout <= n1OiliOi WHEN n1Oiliii = '1' ELSE n1Oi1O0l; + wire_n1OiiO0l_dataout <= n1OiliOl WHEN n1Oiliii = '1' ELSE n1Oi1O0O; + wire_n1OiiO0O_dataout <= n1OiliOO WHEN n1Oiliii = '1' ELSE n1Oi1Oii; + wire_n1OiiO1i_dataout <= n1Oilili WHEN n1Oiliii = '1' ELSE n1Oi1O1l; + wire_n1OiiO1l_dataout <= n1Oilill WHEN n1Oiliii = '1' ELSE n1Oi1O1O; + wire_n1OiiO1O_dataout <= n1OililO WHEN n1Oiliii = '1' ELSE n1Oi1O0i; + wire_n1OiiOii_dataout <= n1Oill1i WHEN n1Oiliii = '1' ELSE n1Oi1Oil; + wire_n1OiiOil_dataout <= n1Oill1l WHEN n1Oiliii = '1' ELSE n1Oi1OiO; + wire_n1OiiOiO_dataout <= n1Oill1O WHEN n1Oiliii = '1' ELSE n1Oi1Oli; + wire_n1OiiOli_dataout <= n1Oill0i WHEN n1Oiliii = '1' ELSE n1Oi1Oll; + wire_n1OiiOll_dataout <= n1Oill0l WHEN n1Oiliii = '1' ELSE n1Oi1OlO; + wire_n1OiiOlO_dataout <= n1Oill0O WHEN n1Oiliii = '1' ELSE n1Oi1OOi; + wire_n1OiiOOi_dataout <= n1Oillii WHEN n1Oiliii = '1' ELSE n1Oi1OOl; + wire_n1OiiOOl_dataout <= n1Oillil WHEN n1Oiliii = '1' ELSE n1Oi1OOO; + wire_n1OiiOOO_dataout <= n1OilliO WHEN n1Oiliii = '1' ELSE n1Oi011i; + wire_n1Oil01i_dataout <= n1OilOli WHEN n1Oiliii = '1' ELSE n1Oi001l; + wire_n1Oil01l_dataout <= n1OilOll WHEN n1Oiliii = '1' ELSE n1Oi001O; + wire_n1Oil10i_dataout <= n1OillOi WHEN n1Oiliii = '1' ELSE n1Oi010l; + wire_n1Oil10l_dataout <= n1OillOl WHEN n1Oiliii = '1' ELSE n1Oi010O; + wire_n1Oil10O_dataout <= n1OillOO WHEN n1Oiliii = '1' ELSE n1Oi01ii; + wire_n1Oil11i_dataout <= n1Oillli WHEN n1Oiliii = '1' ELSE n1Oi011l; + wire_n1Oil11l_dataout <= n1Oillll WHEN n1Oiliii = '1' ELSE n1Oi011O; + wire_n1Oil11O_dataout <= n1OilllO WHEN n1Oiliii = '1' ELSE n1Oi010i; + wire_n1Oil1ii_dataout <= n1OilO1i WHEN n1Oiliii = '1' ELSE n1Oi01il; + wire_n1Oil1il_dataout <= n1OilO1l WHEN n1Oiliii = '1' ELSE n1Oi01iO; + wire_n1Oil1iO_dataout <= n1OilO1O WHEN n1Oiliii = '1' ELSE n1Oi01li; + wire_n1Oil1li_dataout <= n1OilO0i WHEN n1Oiliii = '1' ELSE n1Oi01ll; + wire_n1Oil1ll_dataout <= n1OilO0l WHEN n1Oiliii = '1' ELSE n1Oi01lO; + wire_n1Oil1lO_dataout <= n1OilO0O WHEN n1Oiliii = '1' ELSE n1Oi01Oi; + wire_n1Oil1Oi_dataout <= n1OilOii WHEN n1Oiliii = '1' ELSE n1Oi01Ol; + wire_n1Oil1Ol_dataout <= n1OilOil WHEN n1Oiliii = '1' ELSE n1Oi01OO; + wire_n1Oil1OO_dataout <= n1OilOiO WHEN n1Oiliii = '1' ELSE n1Oi001i; + wire_n1OiO00i_dataout <= wire_n1Ol100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO00l_dataout <= wire_n1Ol100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO00O_dataout <= wire_n1Ol10ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO01i_dataout <= wire_n1Ol101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO01l_dataout <= wire_n1Ol101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO01O_dataout <= wire_n1Ol100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0ii_dataout <= wire_n1Ol10il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0il_dataout <= wire_n1Ol11Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0iO_dataout <= wire_n1Ol11Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0li_dataout <= wire_n1Ol11OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0ll_dataout <= wire_n1Ol10iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0lO_dataout <= wire_n1Ol10li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0Oi_dataout <= wire_n1Ol10ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0Ol_dataout <= wire_n1Ol10lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO0OO_dataout <= wire_n1Ol10Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO10i_dataout <= wire_n1Ol11ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO10l_dataout <= ((wire_w_lg_niOliil1O18295w(0) AND (wire_w_lg_niOliiiil18296w(0) AND wire_w_lg_w_lg_niOliilii18159w18297w(0))) AND (wire_w_lg_w_lg_w_lg_niOlii0iO18300w18304w18305w(0) OR wire_niO01ill_w_lg_w_lg_n11li1li9830w9831w(0))) AND NOT(wire_niO01lOO_dataout); + wire_n1OiO10O_dataout <= (wire_w_lg_w_lg_w_lg_niOliii0l18289w18291w18292w(0) AND wire_niO01ill_w_lg_n1Oiliil18293w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n1OiO11l_dataout <= wire_n1Ol11lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO11O_dataout <= wire_n1Ol110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1ii_dataout <= wire_n1OiOlOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1il_dataout <= wire_n1Ol111l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1iO_dataout <= wire_n1Ol111O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1li_dataout <= wire_n1Ol110i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1ll_dataout <= wire_n1Ol11ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1lO_dataout <= wire_n1Ol11il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1Oi_dataout <= wire_n1Ol11iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1Ol_dataout <= wire_n1Ol11li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiO1OO_dataout <= wire_n1Ol101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOi0i_dataout <= wire_n1Ol1i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOi0l_dataout <= wire_n1Ol1i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOi0O_dataout <= wire_n1Ol1i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOi1i_dataout <= wire_n1Ol10Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOi1l_dataout <= wire_n1Ol10OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOi1O_dataout <= wire_n1Ol1i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOiii_dataout <= wire_n1Ol1i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOiil_dataout <= wire_n1Ol1i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOiiO_dataout <= wire_n1Ol1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOili_dataout <= wire_n1Ol1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OiOill_dataout <= wire_n1Ol1iiO_dataout OR wire_niO01lOO_dataout; + wire_n1OiOilO_dataout <= wire_n1Ol1ili_dataout OR wire_niO01lOO_dataout; + wire_n1OiOiOi_dataout <= wire_n1Ol1ill_dataout OR wire_niO01lOO_dataout; + wire_n1OiOiOl_dataout <= wire_n1Ol1ilO_dataout OR wire_niO01lOO_dataout; + wire_n1OiOlOi_dataout <= wire_n1OiOlOl_dataout AND NOT(niOliiiil); + wire_n1OiOlOl_dataout <= wire_n1OiOlOO_dataout OR (wire_w_lg_niOliil1i18278w(0) AND wire_w_lg_w_lg_niOliiiOO18267w18279w(0)); + wire_n1OiOlOO_dataout <= wire_n1OiOO1i_dataout OR (wire_w_lg_niOliiiOO18267w(0) AND (wire_w_lg_w_lg_niOlii0lO18269w18270w(0) OR wire_niO01iOi_w_lg_w_lg_w_lg_n1OilOOO18272w18274w18275w(0))); + wire_n1OiOO1i_dataout <= wire_n1OiOO1l_dataout OR (wire_w_lg_niOliiiOO18267w(0) AND niOlii0ll); + wire_n1OiOO1l_dataout <= n1Oiliil OR (wire_n1OiOOiO_o AND (((niOliii0l XOR n1Oilili) OR (niOliii1l XOR n1OiliiO)) OR (NOT (n1Oilili XOR n1OiliiO)))); + wire_n1Ol00lO_dataout <= (niOliilii AND n1Ol001O) AND NOT(wire_niO01lOO_dataout); + wire_n1Ol00Oi_dataout <= (niOliilii AND n1Ol000i) AND NOT(wire_niO01lOO_dataout); + wire_n1Ol00Ol_dataout <= (wire_w_lg_w_lg_w_lg_niOliil0l18156w18157w18158w(0) OR (wire_w_lg_niOliilii18159w(0) AND (wire_w_lg_niOliil0l18160w(0) AND (n1Ol00ii AND niOliiill)))) AND NOT(wire_niO01lOO_dataout); + wire_n1Ol00OO_dataout <= niOliiiOl AND NOT(wire_niO01lOO_dataout); + wire_n1Ol010i_dataout <= wire_n1Ol01il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol010l_dataout <= wire_n1Ol01iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol010O_dataout <= wire_n1Ol01li_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol011O_dataout <= wire_n1Ol01ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol01ii_dataout <= wire_n1Ol01ll_dataout AND NOT(niOliiiiO); + wire_n1Ol01il_dataout <= wire_n1Ol01lO_dataout AND NOT(niOliiiiO); + wire_n1Ol01iO_dataout <= wire_n1Ol01Oi_dataout AND NOT(niOliiiiO); + wire_n1Ol01li_dataout <= wire_n1Ol01Ol_dataout AND NOT(niOliiiiO); + wire_n1Ol01ll_dataout <= wire_n1Ol01OO_o(0) WHEN wire_niO01ill_w_lg_n1Ol011i18185w(0) = '1' ELSE n1OiO11i; + wire_n1Ol01lO_dataout <= wire_n1Ol01OO_o(1) WHEN wire_niO01ill_w_lg_n1Ol011i18185w(0) = '1' ELSE n1Ol1OOl; + wire_n1Ol01Oi_dataout <= wire_n1Ol01OO_o(2) WHEN wire_niO01ill_w_lg_n1Ol011i18185w(0) = '1' ELSE n1Ol1OOO; + wire_n1Ol01Ol_dataout <= wire_n1Ol01OO_o(3) OR NOT(wire_niO01ill_w_lg_n1Ol011i18185w(0)); + wire_n1Ol0i0i_dataout <= n1Ol00iO AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0i0l_dataout <= n1Ol00li AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0i0O_dataout <= niOliilii AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0i1i_dataout <= (niOliil0l AND n1Ol00li) AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0i1l_dataout <= n1Ol00ii AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0i1O_dataout <= niOliil0l AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0lOO_dataout <= wire_n1Ol0Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0O0i_dataout <= wire_n1Ol0Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0O0l_dataout <= wire_n1Ol0OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0O0O_dataout <= wire_n1Ol0OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0O1i_dataout <= wire_n1Ol0Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0O1l_dataout <= wire_n1Ol0OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0O1O_dataout <= wire_n1Ol0Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Ol0Oii_dataout <= wire_n1Ol0OOl_dataout AND NOT(niOliilll); + wire_n1Ol0Oil_dataout <= wire_n1Ol0OOO_dataout AND NOT(niOliilll); + wire_n1Ol0OiO_dataout <= wire_n1Oli11i_dataout AND NOT(niOliilll); + wire_n1Ol0Oli_dataout <= wire_n1Oli11l_dataout AND NOT(niOliilll); + wire_n1Ol0Oll_dataout <= wire_n1Oli11O_dataout AND NOT(niOliilll); + wire_n1Ol0OlO_dataout <= wire_n1Oli10i_dataout AND NOT(niOliilll); + wire_n1Ol0OOi_dataout <= wire_n1Oli10l_dataout AND NOT(niOliilll); + wire_n1Ol0OOl_dataout <= wire_n1Oli10O_o(0) WHEN niOliiliO = '1' ELSE n1Ol00ll; + wire_n1Ol0OOO_dataout <= wire_n1Oli10O_o(1) WHEN niOliiliO = '1' ELSE n1Ol0lil; + wire_n1Ol100i_dataout <= wire_niO10Oii_dataout WHEN niOlii0lO = '1' ELSE n1Oill0i; + wire_n1Ol100l_dataout <= wire_niO10Oil_dataout WHEN niOlii0lO = '1' ELSE n1Oill0l; + wire_n1Ol100O_dataout <= wire_niO10OiO_dataout WHEN niOlii0lO = '1' ELSE n1Oill0O; + wire_n1Ol101i_dataout <= wire_niO10O0i_dataout WHEN niOlii0lO = '1' ELSE n1Oill1i; + wire_n1Ol101l_dataout <= wire_niO10O0l_dataout WHEN niOlii0lO = '1' ELSE n1Oill1l; + wire_n1Ol101O_dataout <= wire_niO10O0O_dataout WHEN niOlii0lO = '1' ELSE n1Oill1O; + wire_n1Ol10ii_dataout <= wire_niO10Oli_dataout WHEN niOlii0lO = '1' ELSE n1Oillii; + wire_n1Ol10il_dataout <= wire_niO10Oll_dataout WHEN niOlii0lO = '1' ELSE n1Oillil; + wire_n1Ol10iO_dataout <= wire_niO10O0i_dataout WHEN niOlii0OO = '1' ELSE n1OilllO; + wire_n1Ol10li_dataout <= wire_niO10O0l_dataout WHEN niOlii0OO = '1' ELSE n1OillOi; + wire_n1Ol10ll_dataout <= wire_niO10O0O_dataout WHEN niOlii0OO = '1' ELSE n1OillOl; + wire_n1Ol10lO_dataout <= wire_niO10Oii_dataout WHEN niOlii0OO = '1' ELSE n1OillOO; + wire_n1Ol10Oi_dataout <= wire_niO10Oil_dataout WHEN niOlii0OO = '1' ELSE n1OilO1i; + wire_n1Ol10Ol_dataout <= niOliil1i WHEN niOlii0OO = '1' ELSE n1OilO1l; + wire_n1Ol10OO_dataout <= wire_niO10O0i_dataout WHEN niOliiiil = '1' ELSE n1OilO1O; + wire_n1Ol110i_dataout <= (wire_niO10O1l_dataout AND (niOliii0i OR niOliiiii)) WHEN wire_n1Ol110l_o = '1' ELSE n1Oilill; + wire_n1Ol110O_dataout <= wire_niO10Oil_dataout WHEN niOlii0li = '1' ELSE n1Oili0i; + wire_n1Ol111l_dataout <= niOliii1l WHEN wire_n1Ol110l_o = '1' ELSE n1OiliiO; + wire_n1Ol111O_dataout <= niOliii0l WHEN wire_n1Ol110l_o = '1' ELSE n1Oilili; + wire_n1Ol11ii_dataout <= wire_niO10O0i_dataout WHEN niOlii0li = '1' ELSE n1OililO; + wire_n1Ol11il_dataout <= wire_niO10O0l_dataout WHEN niOlii0li = '1' ELSE n1OiliOi; + wire_n1Ol11iO_dataout <= wire_niO10O0O_dataout WHEN niOlii0li = '1' ELSE n1OiliOl; + wire_n1Ol11li_dataout <= wire_niO10Oii_dataout WHEN niOlii0li = '1' ELSE n1OiliOO; + wire_n1Ol11ll_dataout <= wire_niO10Oll_dataout WHEN niOlii0ll = '1' ELSE n1Oili0l; + wire_n1Ol11lO_dataout <= wire_niO10Oli_dataout WHEN niOlii0ll = '1' ELSE n1Oi000i; + wire_n1Ol11Oi_dataout <= wire_niO10O0l_dataout WHEN niOlii0ll = '1' ELSE n1OilliO; + wire_n1Ol11Ol_dataout <= wire_niO10O0O_dataout WHEN niOlii0ll = '1' ELSE n1Oillli; + wire_n1Ol11OO_dataout <= n1Oillll AND NOT(niOlii0ll); + wire_n1Ol1i0i_dataout <= wire_niO10Oil_dataout WHEN niOliiiil = '1' ELSE n1OilOii; + wire_n1Ol1i0l_dataout <= wire_niO10OiO_dataout WHEN niOliiiil = '1' ELSE n1OilOil; + wire_n1Ol1i0O_dataout <= wire_niO10Oli_dataout WHEN niOliiiil = '1' ELSE n1OilOiO; + wire_n1Ol1i1i_dataout <= wire_niO10O0l_dataout WHEN niOliiiil = '1' ELSE n1OilO0i; + wire_n1Ol1i1l_dataout <= wire_niO10O0O_dataout WHEN niOliiiil = '1' ELSE n1OilO0l; + wire_n1Ol1i1O_dataout <= wire_niO10Oii_dataout WHEN niOliiiil = '1' ELSE n1OilO0O; + wire_n1Ol1iii_dataout <= wire_niO10Oll_dataout WHEN niOliiiil = '1' ELSE n1OilOli; + wire_n1Ol1iil_dataout <= niOliil1i WHEN niOliiiil = '1' ELSE n1OilOll; + wire_n1Ol1iiO_dataout <= wire_n1Ol1iOi_dataout OR niOliiiil; + wire_n1Ol1ili_dataout <= wire_n1Ol1iOl_dataout AND NOT(niOliiiil); + wire_n1Ol1ill_dataout <= wire_n1Ol1iOO_dataout OR niOliiiil; + wire_n1Ol1ilO_dataout <= wire_n1Ol1l1i_dataout OR niOliiiil; + wire_n1Ol1iOi_dataout <= wire_n1Ol1l1l_dataout WHEN wire_w_lg_niOlii0Oi18229w(0) = '1' ELSE n1OilOlO; + wire_n1Ol1iOl_dataout <= wire_n1Ol1l1O_dataout WHEN wire_w_lg_niOlii0Oi18229w(0) = '1' ELSE n1OilOOi; + wire_n1Ol1iOO_dataout <= wire_n1Ol1l0i_dataout WHEN wire_w_lg_niOlii0Oi18229w(0) = '1' ELSE n1OilOOl; + wire_n1Ol1l0i_dataout <= wire_n1Ol1l0O_o(3) AND niOlii0Ol; + wire_n1Ol1l0l_dataout <= wire_n1Ol1l0O_o(4) AND niOlii0Ol; + wire_n1Ol1l1i_dataout <= wire_n1Ol1l0l_dataout WHEN wire_w_lg_niOlii0Oi18229w(0) = '1' ELSE n1OilOOO; + wire_n1Ol1l1l_dataout <= wire_n1Ol1l0O_o(1) AND niOlii0Ol; + wire_n1Ol1l1O_dataout <= wire_n1Ol1l0O_o(2) AND niOlii0Ol; + wire_n1Oli01l_dataout <= n1Ol0lOl AND (wire_nilOO01l_w_lg_dataout295w(0) OR nlOllO0iO); + wire_n1Oli10i_dataout <= wire_n1Oli10O_o(5) WHEN niOliiliO = '1' ELSE n1Ol0llO; + wire_n1Oli10l_dataout <= wire_n1Oli10O_o(6) WHEN niOliiliO = '1' ELSE n1Ol0lOi; + wire_n1Oli11i_dataout <= wire_n1Oli10O_o(2) WHEN niOliiliO = '1' ELSE n1Ol0liO; + wire_n1Oli11l_dataout <= wire_n1Oli10O_o(3) WHEN niOliiliO = '1' ELSE n1Ol0lli; + wire_n1Oli11O_dataout <= wire_n1Oli10O_o(4) WHEN niOliiliO = '1' ELSE n1Ol0lll; + wire_n1Oli1ll_dataout <= n1Olii0l AND (((NOT (wire_niili00O_dataout XOR n1Olii1l)) AND (NOT (wire_niili0ii_dataout XOR n1Olii1O))) AND (NOT (n1101l1i XOR n1Olii0i))); + wire_n1Oli1ll_w_lg_w_lg_w_lg_dataout18040w18046w18047w(0) <= wire_n1Oli1ll_w_lg_w_lg_dataout18040w18046w(0) AND n1Olii0l; + wire_n1Oli1ll_w_lg_w_lg_dataout18040w18046w(0) <= wire_n1Oli1ll_w_lg_dataout18040w(0) AND wire_niO01ill_w_lg_w_lg_w_lg_n1Oli0OO18041w18043w18045w(0); + wire_n1Oli1ll_w_lg_dataout18053w(0) <= wire_n1Oli1ll_dataout AND wire_niO01ill_w18052w(0); + wire_n1Oli1ll_w_lg_dataout18040w(0) <= NOT wire_n1Oli1ll_dataout; + wire_n1Oli1lO_dataout <= n1OliilO AND (n1Olii0O AND niOliillO); + wire_n1Oli1Ol_dataout <= n1OliilO AND ((NOT (n1Oliiil XOR n1Oliiii)) AND niOliillO); + wire_n1OliiOO_dataout <= wire_n1Olliil_dataout OR wire_niO01lOO_dataout; + wire_n1Olil0i_dataout <= wire_n1Olll1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olil0l_dataout <= wire_n1Olll1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olil0O_dataout <= wire_n1Olll0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olil1i_dataout <= wire_n1OlliOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olil1l_dataout <= wire_n1OlliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olil1O_dataout <= wire_n1Olll1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olilii_dataout <= wire_n1Olll0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olilil_dataout <= wire_n1Olll0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliliO_dataout <= wire_n1Olllii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olilli_dataout <= wire_n1OliOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1Olilll_dataout <= wire_n1OliOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OlillO_dataout <= wire_n1OliOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OlilOi_dataout <= wire_n1OliOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OlilOl_dataout <= wire_n1Oll11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OlilOO_dataout <= wire_n1Oll11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliO0i_dataout <= wire_n1OO00Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliO0l_dataout <= wire_n1OO00OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliO0O_dataout <= wire_n1OO0i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliO1i_dataout <= wire_n1Oll11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliO1l_dataout <= wire_n1Oll1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliO1O_dataout <= wire_n1OO00Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliOii_dataout <= wire_n1OO0i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliOil_dataout <= wire_n1OO0i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliOiO_dataout <= wire_n1OO0l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliOli_dataout <= wire_n1Oll00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliOll_dataout <= wire_n1Oll00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OliOlO_dataout <= wire_n1Oll10i_dataout AND NOT(niOliilOi); + wire_n1OliOOi_dataout <= wire_n1Oll10l_dataout AND NOT(niOliilOi); + wire_n1OliOOl_dataout <= wire_n1Oll10O_dataout AND NOT(niOliilOi); + wire_n1OliOOO_dataout <= wire_n1Oll1ii_dataout AND NOT(niOliilOi); + wire_n1Oll00l_dataout <= n1OliiOi WHEN nlOllO0iO = '1' ELSE wire_n1Oll00O_dataout; + wire_n1Oll00O_dataout <= wire_n1Oll0ii_dataout OR niOlil11O; + wire_n1Oll01i_dataout <= n1Olii0l AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlil1ll18059w(0))); + wire_n1Oll0ii_dataout <= wire_n1Oll0il_dataout OR n1OO0O1i; + wire_n1Oll0il_dataout <= wire_n1Oll0iO_dataout OR (wire_niO01ill_w_lg_n1OO0lOi17910w(0) AND (wire_n1Oli1ll_dataout AND niOliiOlO)); + wire_n1Oll0iO_dataout <= wire_n1Oll0ll_dataout OR (wire_niO01ill_w_lg_n1OO0lOi17910w(0) AND (wire_n1Oli1ll_dataout AND niOliiO0l)); + wire_n1Oll0ll_dataout <= wire_n1Oll0lO_dataout OR (wire_niO01ill_w_lg_n1OO0lOi17910w(0) AND wire_n1Oli1ll_w_lg_dataout18053w(0)); + wire_n1Oll0lO_dataout <= wire_n1Oll0Oi_dataout OR (wire_niO01ill_w_lg_n1OO0lOi17910w(0) AND wire_n1Oli1ll_w_lg_w_lg_w_lg_dataout18040w18046w18047w(0)); + wire_n1Oll0Oi_dataout <= n1OliiOl AND nlOllO0iO; + wire_n1Oll10i_dataout <= wire_n1Oll1ll_o(0) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Oli0Oi; + wire_n1Oll10l_dataout <= wire_n1Oll1ll_o(1) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Oli0Ol; + wire_n1Oll10O_dataout <= wire_n1Oll1ll_o(2) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Oli0OO; + wire_n1Oll11i_dataout <= wire_n1Oll1il_dataout AND NOT(niOliilOi); + wire_n1Oll11l_dataout <= wire_n1Oll1iO_dataout AND NOT(niOliilOi); + wire_n1Oll11O_dataout <= wire_n1Oll1li_dataout AND NOT(niOliilOi); + wire_n1Oll1ii_dataout <= wire_n1Oll1ll_o(3) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Olii1i; + wire_n1Oll1il_dataout <= wire_n1Oll1ll_o(4) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Olii1l; + wire_n1Oll1iO_dataout <= wire_n1Oll1ll_o(5) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Olii1O; + wire_n1Oll1li_dataout <= wire_n1Oll1ll_o(6) WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Olii0i; + wire_n1Oll1OO_dataout <= wire_n1Oll01i_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17912w(0) AND wire_w_lg_niOlil1li17913w(0)); + wire_n1Olliil_dataout <= wire_n1OlliiO_dataout OR ((wire_niO01ill_w_lg_n1l0001i11682w(0) OR (n1OO0lOO AND n1Oliiil)) OR (n1OO0lOO AND n1Oli0OO)); + wire_n1OlliiO_dataout <= n1Ol0lOl AND nlOllO0iO; + wire_n1OlliOl_dataout <= wire_n1O01liO_dataout WHEN niOlil1ii = '1' ELSE wire_n1Olllil_dataout; + wire_n1OlliOO_dataout <= wire_n1O01lii_dataout WHEN niOlil1ii = '1' ELSE wire_n1OllliO_dataout; + wire_n1Olll0i_dataout <= wire_n1O01iOi_dataout WHEN niOlil1ii = '1' ELSE wire_n1OlllOi_dataout; + wire_n1Olll0l_dataout <= wire_n1O01ill_dataout WHEN niOlil1ii = '1' ELSE wire_n1OlllOl_dataout; + wire_n1Olll0O_dataout <= wire_n1O01iil_dataout WHEN niOlil1ii = '1' ELSE wire_n1OlllOO_dataout; + wire_n1Olll1i_dataout <= wire_n1O01l0l_dataout WHEN niOlil1ii = '1' ELSE wire_n1Olllli_dataout; + wire_n1Olll1l_dataout <= wire_n1O01l1O_dataout WHEN niOlil1ii = '1' ELSE wire_n1Olllll_dataout; + wire_n1Olll1O_dataout <= wire_n1O01l1i_dataout WHEN niOlil1ii = '1' ELSE wire_n1OllllO_dataout; + wire_n1Olllii_dataout <= n1OO0O1O WHEN niOlil1ii = '1' ELSE wire_n1OllO1i_dataout; + wire_n1Olllil_dataout <= wire_n1OllO1O_dataout AND NOT(niOlil10l); + wire_n1OllliO_dataout <= wire_n1OllO0i_dataout AND NOT(niOlil10l); + wire_n1Olllli_dataout <= wire_n1OllO0l_dataout OR niOlil10l; + wire_n1Olllll_dataout <= wire_n1OllO0O_dataout OR niOlil10l; + wire_n1OllllO_dataout <= wire_n1OllOii_dataout OR niOlil10l; + wire_n1OlllOi_dataout <= wire_n1OllOil_dataout OR niOlil10l; + wire_n1OlllOl_dataout <= wire_n1OllOiO_dataout AND NOT(niOlil10l); + wire_n1OlllOO_dataout <= wire_n1OllOli_dataout OR niOlil10l; + wire_n1OllO0i_dataout <= wire_n1OllOlO_dataout AND NOT(niOlil11l); + wire_n1OllO0l_dataout <= wire_n1OllOOi_dataout AND NOT(niOlil11l); + wire_n1OllO0O_dataout <= wire_n1OllOOl_dataout AND NOT(niOlil11l); + wire_n1OllO1i_dataout <= wire_n1OllO1l_dataout OR niOlil10l; + wire_n1OllO1l_dataout <= wire_n1OlO10i_dataout AND NOT(niOlil11l); + wire_n1OllO1O_dataout <= wire_n1OllOll_dataout AND NOT(niOlil11l); + wire_n1OllOii_dataout <= wire_n1OllOOO_dataout AND NOT(niOlil11l); + wire_n1OllOil_dataout <= wire_n1OlO11i_dataout AND NOT(niOlil11l); + wire_n1OllOiO_dataout <= wire_n1OlO11l_dataout AND NOT(niOlil11l); + wire_n1OllOli_dataout <= wire_n1OlO11O_dataout AND NOT(niOlil11l); + wire_n1OllOll_dataout <= wire_n1OlO10l_dataout AND NOT(niOliiOOO); + wire_n1OllOlO_dataout <= wire_n1OlO10O_dataout AND NOT(niOliiOOO); + wire_n1OllOOi_dataout <= wire_n1OlO1ii_dataout OR niOliiOOO; + wire_n1OllOOl_dataout <= wire_n1OlO1il_dataout OR niOliiOOO; + wire_n1OllOOO_dataout <= wire_n1OlO1iO_dataout OR niOliiOOO; + wire_n1OlO00i_dataout <= wire_n1OlO0Oi_dataout AND NOT(niOliiOOi); + wire_n1OlO00l_dataout <= wire_n1OlO0Ol_dataout OR niOliiOOi; + wire_n1OlO00O_dataout <= wire_n1OlO0OO_dataout AND NOT(niOliiOOi); + wire_n1OlO01i_dataout <= wire_n1OlO0li_dataout AND NOT(niOliiOOi); + wire_n1OlO01l_dataout <= wire_n1OlO0ll_dataout OR niOliiOOi; + wire_n1OlO01O_dataout <= wire_n1OlO0lO_dataout AND NOT(niOliiOOi); + wire_n1OlO0ii_dataout <= wire_n1OlOi1i_dataout AND NOT(niOliiOOi); + wire_n1OlO0il_dataout <= wire_n1OO11li_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOi1l_dataout; + wire_n1OlO0iO_dataout <= wire_n1OO11ll_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOi1O_dataout; + wire_n1OlO0li_dataout <= wire_n1OO11lO_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOi0i_dataout; + wire_n1OlO0ll_dataout <= wire_n1OO11Oi_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOi0l_dataout; + wire_n1OlO0lO_dataout <= wire_n1OO11Ol_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOi0O_dataout; + wire_n1OlO0Oi_dataout <= wire_n1OO11OO_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOiii_dataout; + wire_n1OlO0Ol_dataout <= wire_n1OO101i_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOiil_dataout; + wire_n1OlO0OO_dataout <= wire_n1OO101l_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOiiO_dataout; + wire_n1OlO10i_dataout <= wire_n1OlO1Oi_dataout OR niOliiOOO; + wire_n1OlO10l_dataout <= wire_n1OlO1Ol_dataout OR niOliiOOl; + wire_n1OlO10O_dataout <= wire_n1OlO1OO_dataout AND NOT(niOliiOOl); + wire_n1OlO11i_dataout <= wire_n1OlO1li_dataout OR niOliiOOO; + wire_n1OlO11l_dataout <= wire_n1OlO1ll_dataout OR niOliiOOO; + wire_n1OlO11O_dataout <= wire_n1OlO1lO_dataout AND NOT(niOliiOOO); + wire_n1OlO1ii_dataout <= wire_n1OlO01i_dataout OR niOliiOOl; + wire_n1OlO1il_dataout <= wire_n1OlO01l_dataout AND NOT(niOliiOOl); + wire_n1OlO1iO_dataout <= wire_n1OlO01O_dataout OR niOliiOOl; + wire_n1OlO1li_dataout <= wire_n1OlO00i_dataout OR niOliiOOl; + wire_n1OlO1ll_dataout <= wire_n1OlO00l_dataout AND NOT(niOliiOOl); + wire_n1OlO1lO_dataout <= wire_n1OlO00O_dataout OR niOliiOOl; + wire_n1OlO1Oi_dataout <= wire_n1OlO0ii_dataout AND NOT(niOliiOOl); + wire_n1OlO1Ol_dataout <= wire_n1OlO0il_dataout AND NOT(niOliiOOi); + wire_n1OlO1OO_dataout <= wire_n1OlO0iO_dataout OR niOliiOOi; + wire_n1OlOi0i_dataout <= wire_n1OlOiOi_dataout OR niOliiO1O; + wire_n1OlOi0l_dataout <= wire_n1OlOiOl_dataout OR niOliiO1O; + wire_n1OlOi0O_dataout <= wire_n1OlOiOO_dataout OR niOliiO1O; + wire_n1OlOi1i_dataout <= wire_n1OO101O_dataout WHEN wire_n1Oli1ll_dataout = '1' ELSE wire_n1OlOili_dataout; + wire_n1OlOi1l_dataout <= wire_n1OlOill_dataout AND NOT(niOliiO1O); + wire_n1OlOi1O_dataout <= wire_n1OlOilO_dataout AND NOT(niOliiO1O); + wire_n1OlOiii_dataout <= wire_n1OlOl1i_dataout OR niOliiO1O; + wire_n1OlOiil_dataout <= wire_n1OlOl1l_dataout AND NOT(niOliiO1O); + wire_n1OlOiiO_dataout <= wire_n1OlOl1O_dataout OR niOliiO1O; + wire_n1OlOili_dataout <= wire_n1OlOl0i_dataout OR niOliiO1O; + wire_n1OlOill_dataout <= wire_n1OlOl0l_dataout AND NOT(niOliiO1l); + wire_n1OlOilO_dataout <= wire_n1OlOl0O_dataout AND NOT(niOliiO1l); + wire_n1OlOiO_dataout <= wire_n01l10O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OlOiOi_dataout <= wire_n1OlOlii_dataout OR niOliiO1l; + wire_n1OlOiOl_dataout <= wire_n1OlOlil_dataout OR niOliiO1l; + wire_n1OlOiOO_dataout <= wire_n1OlOliO_dataout OR niOliiO1l; + wire_n1OlOl0i_dataout <= wire_n1OlOlOi_dataout OR niOliiO1l; + wire_n1OlOl0l_dataout <= wire_n1OlOlOl_dataout AND NOT(niOliiO1i); + wire_n1OlOl0O_dataout <= wire_n1OlOlOO_dataout AND NOT(niOliiO1i); + wire_n1OlOl1i_dataout <= wire_n1OlOlli_dataout OR niOliiO1l; + wire_n1OlOl1l_dataout <= wire_n1OlOlll_dataout OR niOliiO1l; + wire_n1OlOl1O_dataout <= wire_n1OlOllO_dataout AND NOT(niOliiO1l); + wire_n1OlOli_dataout <= wire_n01l1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OlOlii_dataout <= wire_n1OlOO1i_dataout AND NOT(niOliiO1i); + wire_n1OlOlil_dataout <= wire_n1OlOO1l_dataout AND NOT(niOliiO1i); + wire_n1OlOliO_dataout <= wire_n1OlOO1O_dataout AND NOT(niOliiO1i); + wire_n1OlOll_dataout <= wire_n01011O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OlOlli_dataout <= wire_n1OlOO0i_dataout AND NOT(niOliiO1i); + wire_n1OlOlll_dataout <= wire_n1OlOO0l_dataout AND NOT(niOliiO1i); + wire_n1OlOllO_dataout <= wire_n1OlOO0O_dataout AND NOT(niOliiO1i); + wire_n1OlOlO_dataout <= wire_n01010i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OlOlOi_dataout <= wire_n1OlOOii_dataout AND NOT(niOliiO1i); + wire_n1OlOlOl_dataout <= n1Ol00ll WHEN niOliilOl = '1' ELSE wire_n1OlOOil_dataout; + wire_n1OlOlOO_dataout <= n1Ol0lil WHEN niOliilOl = '1' ELSE wire_n1OlOOiO_dataout; + wire_n1OlOO0i_dataout <= n1Ol0llO WHEN niOliilOl = '1' ELSE wire_n1OlOOOi_dataout; + wire_n1OlOO0l_dataout <= n1Ol0lOi WHEN niOliilOl = '1' ELSE wire_n1OlOOOl_dataout; + wire_n1OlOO0O_dataout <= n1O0Ol1i WHEN niOliilOl = '1' ELSE wire_n1OlOOOO_dataout; + wire_n1OlOO1i_dataout <= n1Ol0liO WHEN niOliilOl = '1' ELSE wire_n1OlOOli_dataout; + wire_n1OlOO1l_dataout <= n1Ol0lli WHEN niOliilOl = '1' ELSE wire_n1OlOOll_dataout; + wire_n1OlOO1O_dataout <= n1Ol0lll WHEN niOliilOl = '1' ELSE wire_n1OlOOlO_dataout; + wire_n1OlOOi_dataout <= wire_n01010l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OlOOii_dataout <= wire_n1OO111i_dataout AND NOT(niOliilOl); + wire_n1OlOOil_dataout <= n1Oli00i WHEN niOliilOO = '1' ELSE wire_n1O01liO_dataout; + wire_n1OlOOiO_dataout <= n1Oli00l WHEN niOliilOO = '1' ELSE wire_n1O01lii_dataout; + wire_n1OlOOl_dataout <= wire_n01010O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OlOOli_dataout <= n1Oli00O WHEN niOliilOO = '1' ELSE wire_n1O01l0l_dataout; + wire_n1OlOOll_dataout <= n1Oli0ii WHEN niOliilOO = '1' ELSE wire_n1O01l1O_dataout; + wire_n1OlOOlO_dataout <= n1Oli0il WHEN niOliilOO = '1' ELSE wire_n1O01l1i_dataout; + wire_n1OlOOO_dataout <= wire_n0101ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OlOOOi_dataout <= n1Oli0iO WHEN niOliilOO = '1' ELSE wire_n1O01iOi_dataout; + wire_n1OlOOOl_dataout <= n1Oli0li WHEN niOliilOO = '1' ELSE wire_n1O01ill_dataout; + wire_n1OlOOOO_dataout <= n1Oli0ll WHEN niOliilOO = '1' ELSE wire_n1O01iil_dataout; + wire_n1OO00i_dataout <= wire_n0100ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO00l_dataout <= wire_n0100Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO00O_dataout <= wire_n0100Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO00Oi_dataout <= wire_n1OO0i0i_dataout AND NOT(niOlil1iO); + wire_n1OO00Ol_dataout <= wire_n1OO0i0l_dataout AND NOT(niOlil1iO); + wire_n1OO00OO_dataout <= wire_n1OO0i0O_dataout AND NOT(niOlil1iO); + wire_n1OO010i_dataout <= wire_n1OO01Oi_dataout AND NOT(niOliiOll); + wire_n1OO010l_dataout <= wire_n1OO01Ol_dataout OR niOliiOll; + wire_n1OO010O_dataout <= wire_n1OO01OO_dataout OR niOliiOll; + wire_n1OO011i_dataout <= wire_n1OO01li_dataout OR niOliiOll; + wire_n1OO011l_dataout <= wire_n1OO01ll_dataout OR niOliiOll; + wire_n1OO011O_dataout <= wire_n1OO01lO_dataout OR niOliiOll; + wire_n1OO01i_dataout <= wire_n0100il_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO01ii_dataout <= n1Oli00i AND NOT(niOliiOlO); + wire_n1OO01il_dataout <= n1Oli00l AND NOT(niOliiOlO); + wire_n1OO01iO_dataout <= n1Oli00O OR niOliiOlO; + wire_n1OO01l_dataout <= wire_n0100iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO01li_dataout <= n1Oli0ii OR niOliiOlO; + wire_n1OO01ll_dataout <= n1Oli0il OR niOliiOlO; + wire_n1OO01lO_dataout <= n1Oli0iO OR niOliiOlO; + wire_n1OO01O_dataout <= wire_n0100li_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO01Oi_dataout <= n1Oli0li OR niOliiOlO; + wire_n1OO01Ol_dataout <= n1Oli0ll OR niOliiOlO; + wire_n1OO01OO_dataout <= n1Oli0lO OR niOliiOlO; + wire_n1OO0i0i_dataout <= wire_n1OO0ili_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Olii0O; + wire_n1OO0i0l_dataout <= wire_n1OO0ill_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Oliiii; + wire_n1OO0i0O_dataout <= wire_n1OO0ilO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Oliiil; + wire_n1OO0i1i_dataout <= wire_n1OO0iii_dataout AND NOT(niOlil1iO); + wire_n1OO0i1l_dataout <= wire_n1OO0iil_dataout AND NOT(niOlil1iO); + wire_n1OO0i1O_dataout <= wire_n1OO0iiO_dataout AND NOT(niOlil1iO); + wire_n1OO0ii_dataout <= wire_n0100OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0iii_dataout <= wire_n1OO0iOi_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1OliiiO; + wire_n1OO0iil_dataout <= wire_n1OO0iOl_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Oliili; + wire_n1OO0iiO_dataout <= wire_n1OO0iOO_dataout WHEN wire_niO01ill_w_lg_n1l1OOOl11561w(0) = '1' ELSE n1Oliill; + wire_n1OO0il_dataout <= wire_n010i1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0ili_dataout <= wire_n1OO0l1i_o(0) WHEN niOlil1il = '1' ELSE n1Olii0O; + wire_n1OO0ill_dataout <= wire_n1OO0l1i_o(1) WHEN niOlil1il = '1' ELSE n1Oliiii; + wire_n1OO0ilO_dataout <= wire_n1OO0l1i_o(2) WHEN niOlil1il = '1' ELSE n1Oliiil; + wire_n1OO0iO_dataout <= wire_n010i1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0iOi_dataout <= wire_n1OO0l1i_o(3) WHEN niOlil1il = '1' ELSE n1OliiiO; + wire_n1OO0iOl_dataout <= wire_n1OO0l1i_o(4) WHEN niOlil1il = '1' ELSE n1Oliili; + wire_n1OO0iOO_dataout <= wire_n1OO0l1i_o(5) WHEN niOlil1il = '1' ELSE n1Oliill; + wire_n1OO0l0O_dataout <= wire_n1OO0lii_dataout OR (wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17907w(0) AND wire_w_lg_niOlil1lO17908w(0)); + wire_n1OO0li_dataout <= wire_n010i1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0lii_dataout <= n1OliilO AND NOT((wire_niO01ill_w_lg_n1l1OOOl11561w(0) AND wire_w_lg_niOlil1Oi17916w(0))); + wire_n1OO0ll_dataout <= wire_n010i0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0lO_dataout <= wire_n010i0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0Oi_dataout <= wire_n010i0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0Ol_dataout <= wire_n010iii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0OlO_dataout <= wire_n1OOi00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OO0OO_dataout <= wire_n010iil_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO0OOi_dataout <= wire_n1OOi0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OO0OOl_dataout <= wire_n1OOi0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OO0OOO_dataout <= wire_n1OOi00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OO100i_dataout <= wire_n1OO10Oi_dataout AND NOT(niOliiO0l); + wire_n1OO100l_dataout <= wire_n1OO10Ol_dataout AND NOT(niOliiO0l); + wire_n1OO100O_dataout <= wire_n1OO10OO_dataout OR niOliiO0l; + wire_n1OO101i_dataout <= wire_n1OO10li_dataout AND NOT(niOliiO0i); + wire_n1OO101l_dataout <= wire_n1OO10ll_dataout OR niOliiO0i; + wire_n1OO101O_dataout <= wire_n1OO10lO_dataout OR niOliiO0i; + wire_n1OO10i_dataout <= wire_n0101ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO10ii_dataout <= wire_n1OO1i1i_dataout OR niOliiO0l; + wire_n1OO10il_dataout <= wire_n1OO1i1l_dataout OR niOliiO0l; + wire_n1OO10iO_dataout <= wire_n1OO1i1O_dataout OR niOliiO0l; + wire_n1OO10l_dataout <= wire_n0101lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO10li_dataout <= wire_n1OO1i0i_dataout AND NOT(niOliiO0l); + wire_n1OO10ll_dataout <= wire_n1OO1i0l_dataout OR niOliiO0l; + wire_n1OO10lO_dataout <= wire_n1OO1i0O_dataout OR niOliiO0l; + wire_n1OO10O_dataout <= wire_n0101Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO10Oi_dataout <= wire_n1OO1iii_dataout OR niOliiO0O; + wire_n1OO10Ol_dataout <= wire_n1OO1iil_dataout AND NOT(niOliiO0O); + wire_n1OO10OO_dataout <= wire_n1OO1iiO_dataout OR niOliiO0O; + wire_n1OO111i_dataout <= n1OO0O1O AND NOT(niOliilOO); + wire_n1OO11i_dataout <= wire_n0101il_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO11l_dataout <= wire_n0101iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO11li_dataout <= wire_n1OO100i_dataout AND NOT(niOliiO0i); + wire_n1OO11ll_dataout <= wire_n1OO100l_dataout AND NOT(niOliiO0i); + wire_n1OO11lO_dataout <= wire_n1OO100O_dataout OR niOliiO0i; + wire_n1OO11O_dataout <= wire_n0101li_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO11Oi_dataout <= wire_n1OO10ii_dataout OR niOliiO0i; + wire_n1OO11Ol_dataout <= wire_n1OO10il_dataout OR niOliiO0i; + wire_n1OO11OO_dataout <= wire_n1OO10iO_dataout OR niOliiO0i; + wire_n1OO1i0i_dataout <= wire_n1OO1iOi_dataout AND NOT(niOliiO0O); + wire_n1OO1i0l_dataout <= wire_n1OO1iOl_dataout OR niOliiO0O; + wire_n1OO1i0O_dataout <= wire_n1OO1iOO_dataout AND NOT(niOliiO0O); + wire_n1OO1i1i_dataout <= wire_n1OO1ili_dataout AND NOT(niOliiO0O); + wire_n1OO1i1l_dataout <= wire_n1OO1ill_dataout OR niOliiO0O; + wire_n1OO1i1O_dataout <= wire_n1OO1ilO_dataout OR niOliiO0O; + wire_n1OO1ii_dataout <= wire_n0101Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1iii_dataout <= wire_n1OO1l1i_dataout AND NOT(niOliiOii); + wire_n1OO1iil_dataout <= wire_n1OO1l1l_dataout AND NOT(niOliiOii); + wire_n1OO1iiO_dataout <= wire_n1OO1l1O_dataout OR niOliiOii; + wire_n1OO1il_dataout <= wire_n0101OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1ili_dataout <= wire_n1OO1l0i_dataout OR niOliiOii; + wire_n1OO1ill_dataout <= wire_n1OO1l0l_dataout OR niOliiOii; + wire_n1OO1ilO_dataout <= wire_n1OO1l0O_dataout OR niOliiOii; + wire_n1OO1iO_dataout <= wire_n01001i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1iOi_dataout <= wire_n1OO1lii_dataout AND NOT(niOliiOii); + wire_n1OO1iOl_dataout <= wire_n1OO1lil_dataout OR niOliiOii; + wire_n1OO1iOO_dataout <= wire_n1OO1liO_dataout OR niOliiOii; + wire_n1OO1l0i_dataout <= wire_n1OO1lOi_dataout OR niOliiOil; + wire_n1OO1l0l_dataout <= wire_n1OO1lOl_dataout AND NOT(niOliiOil); + wire_n1OO1l0O_dataout <= wire_n1OO1lOO_dataout AND NOT(niOliiOil); + wire_n1OO1l1i_dataout <= wire_n1OO1lli_dataout AND NOT(niOliiOil); + wire_n1OO1l1l_dataout <= wire_n1OO1lll_dataout OR niOliiOil; + wire_n1OO1l1O_dataout <= wire_n1OO1llO_dataout AND NOT(niOliiOil); + wire_n1OO1li_dataout <= wire_n01001l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1lii_dataout <= wire_n1OO1O1i_dataout OR niOliiOil; + wire_n1OO1lil_dataout <= wire_n1OO1O1l_dataout AND NOT(niOliiOil); + wire_n1OO1liO_dataout <= wire_n1OO1O1O_dataout AND NOT(niOliiOil); + wire_n1OO1ll_dataout <= wire_n01001O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1lli_dataout <= n1Ol00ll WHEN niOliiOiO = '1' ELSE wire_n1OO1O0i_dataout; + wire_n1OO1lll_dataout <= n1Ol0lil WHEN niOliiOiO = '1' ELSE wire_n1OO1O0l_dataout; + wire_n1OO1llO_dataout <= n1Ol0liO WHEN niOliiOiO = '1' ELSE wire_n1OO1O0O_dataout; + wire_n1OO1lO_dataout <= wire_n01000i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1lOi_dataout <= n1Ol0lli WHEN niOliiOiO = '1' ELSE wire_n1OO1Oii_dataout; + wire_n1OO1lOl_dataout <= n1Ol0lll WHEN niOliiOiO = '1' ELSE wire_n1OO1Oil_dataout; + wire_n1OO1lOO_dataout <= n1Ol0llO WHEN niOliiOiO = '1' ELSE wire_n1OO1OiO_dataout; + wire_n1OO1O0i_dataout <= n1Oli00i WHEN niOliiOli = '1' ELSE wire_n1OO1OOi_dataout; + wire_n1OO1O0l_dataout <= n1Oli00l WHEN niOliiOli = '1' ELSE wire_n1OO1OOl_dataout; + wire_n1OO1O0O_dataout <= n1Oli00O WHEN niOliiOli = '1' ELSE wire_n1OO1OOO_dataout; + wire_n1OO1O1i_dataout <= n1Ol0lOi WHEN niOliiOiO = '1' ELSE wire_n1OO1Oli_dataout; + wire_n1OO1O1l_dataout <= n1O0Ol1i WHEN niOliiOiO = '1' ELSE wire_n1OO1Oll_dataout; + wire_n1OO1O1O_dataout <= wire_n1OO1OlO_dataout AND NOT(niOliiOiO); + wire_n1OO1Oi_dataout <= wire_n01000l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1Oii_dataout <= n1Oli0ii WHEN niOliiOli = '1' ELSE wire_n1OO011i_dataout; + wire_n1OO1Oil_dataout <= n1Oli0il WHEN niOliiOli = '1' ELSE wire_n1OO011l_dataout; + wire_n1OO1OiO_dataout <= n1Oli0iO WHEN niOliiOli = '1' ELSE wire_n1OO011O_dataout; + wire_n1OO1Ol_dataout <= wire_n01000O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1Oli_dataout <= n1Oli0li WHEN niOliiOli = '1' ELSE wire_n1OO010i_dataout; + wire_n1OO1Oll_dataout <= n1Oli0ll WHEN niOliiOli = '1' ELSE wire_n1OO010l_dataout; + wire_n1OO1OlO_dataout <= wire_n1OO010O_dataout AND NOT(niOliiOli); + wire_n1OO1OO_dataout <= wire_n0100ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OO1OOi_dataout <= wire_n1OO01ii_dataout AND NOT(niOliiOll); + wire_n1OO1OOl_dataout <= wire_n1OO01il_dataout AND NOT(niOliiOll); + wire_n1OO1OOO_dataout <= wire_n1OO01iO_dataout OR niOliiOll; + wire_n1OOi00l_dataout <= n1l1OOOl WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n1OO0lOi; + wire_n1OOi00O_dataout <= n1l0010i WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n1Oll0li; + wire_n1OOi0i_dataout <= wire_n010ilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOi0ii_dataout <= n1l0010l WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n1OO0lll; + wire_n1OOi0il_dataout <= n1l0010O WHEN wire_niO01ill_w_lg_n1lO0lOi9962w(0) = '1' ELSE n1OO0llO; + wire_n1OOi0iO_dataout <= wire_n1lllOlO_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOi0li_dataout; + wire_n1OOi0l_dataout <= wire_n010iOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOi0li_dataout <= wire_n1OOi0ll_dataout AND NOT(niOlil1OO); + wire_n1OOi0ll_dataout <= n1l001OO AND NOT(niOlil1Ol); + wire_n1OOi0lO_dataout <= wire_n1llOOll_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOii0l_dataout; + wire_n1OOi0O_dataout <= wire_n010iOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOi0Oi_dataout <= wire_n1llOOlO_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOii0O_dataout; + wire_n1OOi0Ol_dataout <= wire_n1llOOOi_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOiiii_dataout; + wire_n1OOi0OO_dataout <= wire_n1llOOOl_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOiiil_dataout; + wire_n1OOi10i_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17907w(0) AND wire_w_lg_niOlil1lO17908w(0)) AND wire_niO01ill_w_lg_n1OO0lOi17910w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n1OOi10l_dataout <= wire_n1OOi0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi10O_dataout <= wire_n1OOi0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi11i_dataout <= n1OO0lOO AND NOT(wire_niO01lOO_dataout); + wire_n1OOi11l_dataout <= nlOllO0iO AND NOT(wire_niO01lOO_dataout); + wire_n1OOi11O_dataout <= ((wire_niO01ill_w_lg_w_lg_n1lO0lOi9962w17912w(0) AND wire_w_lg_niOlil1li17913w(0)) AND wire_niO01ill_w_lg_n1OO0lOi17910w(0)) AND NOT(wire_niO01lOO_dataout); + wire_n1OOi1i_dataout <= wire_n010iiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOi1ii_dataout <= wire_n1OOi0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi1il_dataout <= wire_n1OOi0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi1iO_dataout <= wire_n1OOi0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi1l_dataout <= wire_n010ili_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOi1li_dataout <= wire_n1OOii1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi1ll_dataout <= wire_n1OOii1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi1lO_dataout <= wire_n1OOii1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOi1O_dataout <= wire_n010ill_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOi1Oi_dataout <= wire_n1OOii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOii0i_dataout <= wire_n1lO111O_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOiilO_dataout; + wire_n1OOii0l_dataout <= wire_nlOO10OOi_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOiiOi_dataout; + wire_n1OOii0O_dataout <= wire_nlOO10OOl_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOiiOl_dataout; + wire_n1OOii1i_dataout <= wire_n1llOOOO_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOiiiO_dataout; + wire_n1OOii1l_dataout <= wire_n1lO111i_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOiili_dataout; + wire_n1OOii1O_dataout <= wire_n1lO111l_dataout WHEN n1lO0lOi = '1' ELSE wire_n1OOiill_dataout; + wire_n1OOiii_dataout <= wire_n010iOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOiiii_dataout <= wire_nlOO10OOO_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOiiOO_dataout; + wire_n1OOiiil_dataout <= wire_nlOO1i11i_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOil1i_dataout; + wire_n1OOiiiO_dataout <= wire_nlOO1i11l_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOil1l_dataout; + wire_n1OOiil_dataout <= wire_n010l1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOiili_dataout <= wire_nlOO1i11O_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOil1O_dataout; + wire_n1OOiill_dataout <= wire_nlOO1i10i_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOil0i_dataout; + wire_n1OOiilO_dataout <= wire_nlOO1i10l_dataout WHEN niOlil1OO = '1' ELSE wire_n1OOil0l_dataout; + wire_n1OOiiO_dataout <= wire_n010l1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOiiOi_dataout <= wire_niili00O_dataout WHEN niOlil1Ol = '1' ELSE n1l001ii; + wire_n1OOiiOl_dataout <= wire_niili0ii_dataout WHEN niOlil1Ol = '1' ELSE n1l001il; + wire_n1OOiiOO_dataout <= n1101l1i WHEN niOlil1Ol = '1' ELSE n1l001iO; + wire_n1OOil0i_dataout <= n1l001Oi AND NOT(niOlil1Ol); + wire_n1OOil0l_dataout <= n1l001Ol AND NOT(niOlil1Ol); + wire_n1OOil1i_dataout <= n1l001li AND NOT(niOlil1Ol); + wire_n1OOil1l_dataout <= n1l001ll AND NOT(niOlil1Ol); + wire_n1OOil1O_dataout <= n1l001lO AND NOT(niOlil1Ol); + wire_n1OOili_dataout <= wire_n010l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOilil_dataout <= k_cnt(57) AND NOT(wire_n1OOilOl_o); + wire_n1OOiliO_dataout <= k_cnt(58) AND NOT(wire_n1OOilOl_o); + wire_n1OOill_dataout <= wire_n010l0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOilli_dataout <= k_cnt(59) OR wire_n1OOilOl_o; + wire_n1OOilll_dataout <= k_cnt(60) AND NOT(wire_n1OOilOl_o); + wire_n1OOillO_dataout <= k_cnt(61) AND NOT(wire_n1OOilOl_o); + wire_n1OOilO_dataout <= wire_n010l0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOilOi_dataout <= k_cnt(62) AND NOT(wire_n1OOilOl_o); + wire_n1OOiOi_dataout <= wire_n010l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOiOl_dataout <= wire_n010lii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOiOO_dataout <= wire_n010lil_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOl00l_dataout <= n01iOilO WHEN niOlil01i = '1' ELSE (n01iOilO XOR n1OOlili); + wire_n1OOl01l_dataout <= n01iOiOi WHEN niOlil01i = '1' ELSE (n01iOiOi XOR n1OOliiO); + wire_n1OOl0i_dataout <= wire_n010llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOl0ii_dataout <= n01iOill WHEN niOlil01i = '1' ELSE (n01iOill XOR n1OOlill); + wire_n1OOl0iO_dataout <= n01iOili WHEN niOlil01i = '1' ELSE (n01iOili XOR n1OOlilO); + wire_n1OOl0l_dataout <= wire_n010lOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOl0ll_dataout <= n01iOiiO WHEN niOlil01i = '1' ELSE (n01iOiiO XOR n1OOliOi); + wire_n1OOl0O_dataout <= wire_n010lOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOl0Oi_dataout <= n01iOiil WHEN niOlil01i = '1' ELSE (n01iOiil XOR n1OOliOl); + wire_n1OOl1i_dataout <= wire_n010liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOl1l_dataout <= wire_n010lli_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOl1lO_dataout <= n01iOiOO WHEN niOlil01i = '1' ELSE (n01iOiOO XOR n1OOliii); + wire_n1OOl1O_dataout <= wire_n010lll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOl1OO_dataout <= n01iOiOl WHEN niOlil01i = '1' ELSE (n01iOiOl XOR n1OOliil); + wire_n1OOlii_dataout <= wire_n010lOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOlil_dataout <= wire_n010O1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOliO_dataout <= wire_n010O1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOll0i_dataout <= wire_n1OOlO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOll0l_dataout <= wire_n1OOlO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOll0O_dataout <= wire_n1OOlOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOll1i_dataout <= wire_n1OOlO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOll1l_dataout <= wire_n1OOlO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOll1O_dataout <= wire_n1OOlO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOlli_dataout <= wire_n010O1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOllii_dataout <= wire_n1OOlOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOllil_dataout <= wire_n1OOlOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOlliO_dataout <= wire_n1OOlOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOlll_dataout <= wire_n010O0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOllli_dataout <= wire_n1OOlOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOllll_dataout <= wire_n1OOlOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOlllO_dataout <= wire_n1OOlOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOllO_dataout <= wire_n010O0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOllOi_dataout <= wire_n1OOlOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOllOl_dataout <= wire_n1OOlOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOllOO_dataout <= wire_n1OOO11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOlO0i_dataout <= wire_n1OOO10l_dataout OR niOlil01O; + wire_n1OOlO0l_dataout <= wire_n1OOO10O_dataout OR niOlil01O; + wire_n1OOlO0O_dataout <= wire_n1OOO1ii_dataout OR niOlil01O; + wire_n1OOlO1i_dataout <= wire_n1OOO11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOlO1l_dataout <= wire_n1OOO11O_dataout OR niOlil01O; + wire_n1OOlO1O_dataout <= wire_n1OOO10i_dataout OR niOlil01O; + wire_n1OOlOi_dataout <= wire_n010O0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOlOii_dataout <= wire_n1OOO1il_dataout OR niOlil01O; + wire_n1OOlOil_dataout <= wire_n1OOO1iO_dataout OR niOlil01O; + wire_n1OOlOiO_dataout <= wire_n1OOO1li_dataout OR niOlil01O; + wire_n1OOlOl_dataout <= wire_n010Oii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOlOli_dataout <= wire_n1OOO1ll_dataout OR niOlil01O; + wire_n1OOlOll_dataout <= wire_n1OOO1lO_dataout OR niOlil01O; + wire_n1OOlOlO_dataout <= wire_n1OOO1Oi_dataout OR niOlil01O; + wire_n1OOlOO_dataout <= wire_n010Oil_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOlOOi_dataout <= wire_n1OOO1Ol_dataout OR niOlil01O; + wire_n1OOlOOl_dataout <= wire_n1OOO1OO_dataout OR niOlil01O; + wire_n1OOlOOO_dataout <= wire_n1OOO01i_dataout OR niOlil01O; + wire_n1OOO00l_dataout <= wire_n1OOO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_n1OOO00O_dataout <= wire_n1OOO0ii_dataout AND NOT(((wire_niO01ill_w_lg_n111i10i12354w(0) AND n1OOliOO) AND niOlil01O)); + wire_n1OOO01i_dataout <= n1OOlilO WHEN niOlil01l = '1' ELSE n1OOli0i; + wire_n1OOO01l_dataout <= n1OOliOi WHEN niOlil01l = '1' ELSE n1OOli0l; + wire_n1OOO01O_dataout <= n1OOliOl WHEN niOlil01l = '1' ELSE n1OOli0O; + wire_n1OOO0i_dataout <= wire_n010OlO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOO0ii_dataout <= n1OOliOO OR n111i10i; + wire_n1OOO0l_dataout <= wire_n010OOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOO0O_dataout <= wire_n010OOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOO10i_dataout <= n1OOl0OO WHEN niOlil01l = '1' ELSE n1OOliil; + wire_n1OOO10l_dataout <= n1OOli1i WHEN niOlil01l = '1' ELSE n1OOliiO; + wire_n1OOO10O_dataout <= n1OOli1l WHEN niOlil01l = '1' ELSE (n1OOlili XOR n1OOliii); + wire_n1OOO11i_dataout <= wire_n1OOO01l_dataout OR niOlil01O; + wire_n1OOO11l_dataout <= wire_n1OOO01O_dataout OR niOlil01O; + wire_n1OOO11O_dataout <= n1OOl00i WHEN niOlil01l = '1' ELSE n1OOliii; + wire_n1OOO1i_dataout <= wire_n010OiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOO1ii_dataout <= n1OOli1O WHEN niOlil01l = '1' ELSE (n1OOliii XOR (n1OOlill XOR n1OOliil)); + wire_n1OOO1il_dataout <= n1OOli0i WHEN niOlil01l = '1' ELSE (n1OOliii XOR (n1OOliil XOR (n1OOlilO XOR n1OOliiO))); + wire_n1OOO1iO_dataout <= n1OOli0l WHEN niOlil01l = '1' ELSE (n1OOliil XOR (n1OOliiO XOR (n1OOliOi XOR n1OOlili))); + wire_n1OOO1l_dataout <= wire_n010Oli_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOO1li_dataout <= n1OOli0O WHEN niOlil01l = '1' ELSE (n1OOliiO XOR (n1OOlili XOR (n1OOliOl XOR n1OOlill))); + wire_n1OOO1ll_dataout <= n1OOliii WHEN niOlil01l = '1' ELSE (n1OOlili XOR (n1OOlill XOR (n1OOlilO XOR n1OOl00i))); + wire_n1OOO1lO_dataout <= n1OOliil WHEN niOlil01l = '1' ELSE (n1OOlill XOR (n1OOlilO XOR (n1OOliOi XOR n1OOl0OO))); + wire_n1OOO1O_dataout <= wire_n010Oll_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOO1Oi_dataout <= n1OOliiO WHEN niOlil01l = '1' ELSE (n1OOlilO XOR (n1OOliOi XOR (n1OOliOl XOR n1OOli1i))); + wire_n1OOO1Ol_dataout <= n1OOlili WHEN niOlil01l = '1' ELSE (n1OOliOi XOR (n1OOliOl XOR n1OOli1l)); + wire_n1OOO1OO_dataout <= n1OOlill WHEN niOlil01l = '1' ELSE (n1OOliOl XOR n1OOli1O); + wire_n1OOOii_dataout <= wire_n010OOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOil_dataout <= wire_n01i11i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOiO_dataout <= wire_n01i11l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOl0O_dataout <= wire_niO10lll_dataout WHEN niOlil00i = '1' ELSE (wire_niO10lll_dataout XOR n011111i); + wire_n1OOOl0O_w_lg_dataout17642w(0) <= NOT wire_n1OOOl0O_dataout; + wire_n1OOOli_dataout <= wire_n01i11O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOliO_dataout <= wire_niO10lli_dataout WHEN niOlil00i = '1' ELSE (wire_niO10lli_dataout XOR n011111l); + wire_n1OOOliO_w_lg_dataout17640w(0) <= NOT wire_n1OOOliO_dataout; + wire_n1OOOll_dataout <= wire_n01i10i_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOlll_dataout <= wire_niO10liO_dataout WHEN niOlil00i = '1' ELSE (wire_niO10liO_dataout XOR n011111O); + wire_n1OOOlll_w_lg_dataout17638w(0) <= NOT wire_n1OOOlll_dataout; + wire_n1OOOlO_dataout <= wire_n01i10l_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOlOl_dataout <= wire_niO10lil_dataout WHEN niOlil00i = '1' ELSE (wire_niO10lil_dataout XOR n011110i); + wire_n1OOOlOl_w_lg_dataout17636w(0) <= NOT wire_n1OOOlOl_dataout; + wire_n1OOOO0l_dataout <= wire_niO10l0l_dataout WHEN niOlil00i = '1' ELSE (wire_niO10l0l_dataout XOR n01111ii); + wire_n1OOOO0l_w_lg_dataout17630w(0) <= NOT wire_n1OOOO0l_dataout; + wire_n1OOOO1i_dataout <= wire_niO10lii_dataout WHEN niOlil00i = '1' ELSE (wire_niO10lii_dataout XOR n011110l); + wire_n1OOOO1i_w_lg_dataout17634w(0) <= NOT wire_n1OOOO1i_dataout; + wire_n1OOOO1O_dataout <= wire_niO10l0O_dataout WHEN niOlil00i = '1' ELSE (wire_niO10l0O_dataout XOR n011110O); + wire_n1OOOO1O_w_lg_dataout17632w(0) <= NOT wire_n1OOOO1O_dataout; + wire_n1OOOOi_dataout <= wire_n01i10O_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOOii_dataout <= wire_niO10l0i_dataout WHEN niOlil00i = '1' ELSE (wire_niO10l0i_dataout XOR n01111il); + wire_n1OOOOii_w_lg_dataout17628w(0) <= NOT wire_n1OOOOii_dataout; + wire_n1OOOOl_dataout <= wire_n01i1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_n1OOOOO_dataout <= wire_n01i1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni00000i_dataout <= wire_nii0l0il_dataout WHEN niOlOl1lO = '1' ELSE wire_ni0000Oi_dataout; + wire_ni00000l_dataout <= ni01OOll WHEN niOlOl0Ol = '1' ELSE ni001i0O; + wire_ni00000O_dataout <= ni0010Oi WHEN niOlOl0Ol = '1' ELSE ni001Oil; + wire_ni00001i_dataout <= wire_nii0l00l_dataout WHEN niOlOl1lO = '1' ELSE wire_ni0000li_dataout; + wire_ni00001l_dataout <= wire_nii0l00O_dataout WHEN niOlOl1lO = '1' ELSE wire_ni0000ll_dataout; + wire_ni00001O_dataout <= wire_nii0l0ii_dataout WHEN niOlOl1lO = '1' ELSE wire_ni0000lO_dataout; + wire_ni0000ii_dataout <= ni0010Ol WHEN niOlOl0Ol = '1' ELSE ni001OiO; + wire_ni0000il_dataout <= ni0010OO WHEN niOlOl0Ol = '1' ELSE ni001Oli; + wire_ni0000iO_dataout <= ni001i1i WHEN niOlOl0Ol = '1' ELSE ni001Oll; + wire_ni0000li_dataout <= ni001i1l WHEN niOlOl0Ol = '1' ELSE ni001OlO; + wire_ni0000ll_dataout <= ni001i1O WHEN niOlOl0Ol = '1' ELSE ni001OOi; + wire_ni0000lO_dataout <= ni001i0i WHEN niOlOl0Ol = '1' ELSE ni001OOl; + wire_ni0000Oi_dataout <= ni001i0l WHEN niOlOl0Ol = '1' ELSE ni001OOO; + wire_ni00010i_dataout <= wire_ni0001Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00010l_dataout <= wire_ni0001Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00010O_dataout <= wire_ni0001OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00011l_dataout <= wire_ni0001ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00011O_dataout <= wire_ni0001lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0001ii_dataout <= wire_ni00001i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0001il_dataout <= wire_ni00001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0001iO_dataout <= wire_ni00001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0001li_dataout <= wire_ni00000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0001ll_dataout <= wire_nii0l1OO_dataout WHEN niOlOl1lO = '1' ELSE wire_ni00000l_dataout; + wire_ni0001lO_dataout <= wire_nii0l01i_dataout WHEN niOlOl1lO = '1' ELSE wire_ni00000O_dataout; + wire_ni0001Oi_dataout <= wire_nii0l01l_dataout WHEN niOlOl1lO = '1' ELSE wire_ni0000ii_dataout; + wire_ni0001Ol_dataout <= wire_nii0l01O_dataout WHEN niOlOl1lO = '1' ELSE wire_ni0000il_dataout; + wire_ni0001OO_dataout <= wire_nii0l00i_dataout WHEN niOlOl1lO = '1' ELSE wire_ni0000iO_dataout; + wire_ni000ilO_dataout <= wire_ni000l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000iOi_dataout <= wire_ni000lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000iOl_dataout <= wire_ni000lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000iOO_dataout <= wire_ni000liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000l0i_dataout <= wire_ni000lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000l0l_dataout <= wire_ni000lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000l0O_dataout <= wire_nii0l1OO_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000lOO_dataout; + wire_ni000l1i_dataout <= wire_ni000lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000l1l_dataout <= wire_ni000lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000l1O_dataout <= wire_ni000llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni000lii_dataout <= wire_nii0l01i_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000O1i_dataout; + wire_ni000lil_dataout <= wire_nii0l01l_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000O1l_dataout; + wire_ni000liO_dataout <= wire_nii0l01O_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000O1O_dataout; + wire_ni000lli_dataout <= wire_nii0l00i_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000O0i_dataout; + wire_ni000lll_dataout <= wire_nii0l00l_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000O0l_dataout; + wire_ni000llO_dataout <= wire_nii0l00O_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000O0O_dataout; + wire_ni000lOi_dataout <= wire_nii0l0ii_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000Oii_dataout; + wire_ni000lOl_dataout <= wire_nii0l0il_dataout WHEN niOlOl1Ol = '1' ELSE wire_ni000Oil_dataout; + wire_ni000lOO_dataout <= ni001i0O WHEN niOlOl0Ol = '1' ELSE ni00011i; + wire_ni000O0i_dataout <= ni001Oll WHEN niOlOl0Ol = '1' ELSE ni000i0O; + wire_ni000O0l_dataout <= ni001OlO WHEN niOlOl0Ol = '1' ELSE ni000iii; + wire_ni000O0O_dataout <= ni001OOi WHEN niOlOl0Ol = '1' ELSE ni000iil; + wire_ni000O1i_dataout <= ni001Oil WHEN niOlOl0Ol = '1' ELSE ni000i1O; + wire_ni000O1l_dataout <= ni001OiO WHEN niOlOl0Ol = '1' ELSE ni000i0i; + wire_ni000O1O_dataout <= ni001Oli WHEN niOlOl0Ol = '1' ELSE ni000i0l; + wire_ni000Oii_dataout <= ni001OOl WHEN niOlOl0Ol = '1' ELSE ni000iiO; + wire_ni000Oil_dataout <= ni001OOO WHEN niOlOl0Ol = '1' ELSE ni000ili; + wire_ni00100i_dataout <= ni01O0Ol WHEN niOlOl0Ol = '1' ELSE ni01OO0O; + wire_ni00100l_dataout <= ni01O0OO WHEN niOlOl0Ol = '1' ELSE ni01OOii; + wire_ni00100O_dataout <= ni01Oi1i WHEN niOlOl0Ol = '1' ELSE ni01OOil; + wire_ni00101i_dataout <= ni01O0ll WHEN niOlOl0Ol = '1' ELSE ni01OO1O; + wire_ni00101l_dataout <= ni01O0lO WHEN niOlOl0Ol = '1' ELSE ni01OO0i; + wire_ni00101O_dataout <= ni01O0Oi WHEN niOlOl0Ol = '1' ELSE ni01OO0l; + wire_ni0010ii_dataout <= ni01Oi1l WHEN niOlOl0Ol = '1' ELSE ni01OOiO; + wire_ni0010il_dataout <= ni01Oi1O WHEN niOlOl0Ol = '1' ELSE ni01OOli; + wire_ni00110i_dataout <= wire_ni0011Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00110l_dataout <= wire_ni0011Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00110O_dataout <= wire_nii0l1OO_dataout WHEN niOlOl1iO = '1' ELSE wire_ni0011OO_dataout; + wire_ni00111i_dataout <= wire_ni0011li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00111l_dataout <= wire_ni0011ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00111O_dataout <= wire_ni0011lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0011ii_dataout <= wire_nii0l01i_dataout WHEN niOlOl1iO = '1' ELSE wire_ni00101i_dataout; + wire_ni0011il_dataout <= wire_nii0l01l_dataout WHEN niOlOl1iO = '1' ELSE wire_ni00101l_dataout; + wire_ni0011iO_dataout <= wire_nii0l01O_dataout WHEN niOlOl1iO = '1' ELSE wire_ni00101O_dataout; + wire_ni0011l_dataout <= niOO0l0lO WHEN niOO0l0Oi = '1' ELSE ni01llO; + wire_ni0011li_dataout <= wire_nii0l00i_dataout WHEN niOlOl1iO = '1' ELSE wire_ni00100i_dataout; + wire_ni0011ll_dataout <= wire_nii0l00l_dataout WHEN niOlOl1iO = '1' ELSE wire_ni00100l_dataout; + wire_ni0011lO_dataout <= wire_nii0l00O_dataout WHEN niOlOl1iO = '1' ELSE wire_ni00100O_dataout; + wire_ni0011O_dataout <= niOO0l0Ol WHEN niOO0l0Oi = '1' ELSE ni01lOl; + wire_ni0011Oi_dataout <= wire_nii0l0ii_dataout WHEN niOlOl1iO = '1' ELSE wire_ni0010ii_dataout; + wire_ni0011Ol_dataout <= wire_nii0l0il_dataout WHEN niOlOl1iO = '1' ELSE wire_ni0010il_dataout; + wire_ni0011OO_dataout <= ni01OO1l WHEN niOlOl0Ol = '1' ELSE ni01Oi0i; + wire_ni001iii_dataout <= wire_ni001l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001iil_dataout <= wire_ni001l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001iiO_dataout <= wire_ni001l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001ili_dataout <= wire_ni001l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001ill_dataout <= wire_ni001l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001ilO_dataout <= wire_ni001l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001iOi_dataout <= wire_ni001lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001iOl_dataout <= wire_ni001lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001iOO_dataout <= wire_ni001liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni001l0i_dataout <= wire_nii0l01O_dataout WHEN niOlOl1li = '1' ELSE wire_ni001lOi_dataout; + wire_ni001l0l_dataout <= wire_nii0l00i_dataout WHEN niOlOl1li = '1' ELSE wire_ni001lOl_dataout; + wire_ni001l0O_dataout <= wire_nii0l00l_dataout WHEN niOlOl1li = '1' ELSE wire_ni001lOO_dataout; + wire_ni001l1i_dataout <= wire_nii0l1OO_dataout WHEN niOlOl1li = '1' ELSE wire_ni001lli_dataout; + wire_ni001l1l_dataout <= wire_nii0l01i_dataout WHEN niOlOl1li = '1' ELSE wire_ni001lll_dataout; + wire_ni001l1O_dataout <= wire_nii0l01l_dataout WHEN niOlOl1li = '1' ELSE wire_ni001llO_dataout; + wire_ni001lii_dataout <= wire_nii0l00O_dataout WHEN niOlOl1li = '1' ELSE wire_ni001O1i_dataout; + wire_ni001lil_dataout <= wire_nii0l0ii_dataout WHEN niOlOl1li = '1' ELSE wire_ni001O1l_dataout; + wire_ni001liO_dataout <= wire_nii0l0il_dataout WHEN niOlOl1li = '1' ELSE wire_ni001O1O_dataout; + wire_ni001lli_dataout <= ni01Oi0i WHEN niOlOl0Ol = '1' ELSE ni01OOll; + wire_ni001lll_dataout <= ni01OO1O WHEN niOlOl0Ol = '1' ELSE ni0010Oi; + wire_ni001llO_dataout <= ni01OO0i WHEN niOlOl0Ol = '1' ELSE ni0010Ol; + wire_ni001lOi_dataout <= ni01OO0l WHEN niOlOl0Ol = '1' ELSE ni0010OO; + wire_ni001lOl_dataout <= ni01OO0O WHEN niOlOl0Ol = '1' ELSE ni001i1i; + wire_ni001lOO_dataout <= ni01OOii WHEN niOlOl0Ol = '1' ELSE ni001i1l; + wire_ni001O1i_dataout <= ni01OOil WHEN niOlOl0Ol = '1' ELSE ni001i1O; + wire_ni001O1l_dataout <= ni01OOiO WHEN niOlOl0Ol = '1' ELSE ni001i0i; + wire_ni001O1O_dataout <= ni01OOli WHEN niOlOl0Ol = '1' ELSE ni001i0l; + wire_ni00i00i_dataout <= wire_nii0l01O_dataout WHEN niOlOl01i = '1' ELSE wire_ni00i0Oi_dataout; + wire_ni00i00l_dataout <= wire_nii0l00i_dataout WHEN niOlOl01i = '1' ELSE wire_ni00i0Ol_dataout; + wire_ni00i00O_dataout <= wire_nii0l00l_dataout WHEN niOlOl01i = '1' ELSE wire_ni00i0OO_dataout; + wire_ni00i01i_dataout <= wire_nii0l1OO_dataout WHEN niOlOl01i = '1' ELSE wire_ni00i0li_dataout; + wire_ni00i01l_dataout <= wire_nii0l01i_dataout WHEN niOlOl01i = '1' ELSE wire_ni00i0ll_dataout; + wire_ni00i01O_dataout <= wire_nii0l01l_dataout WHEN niOlOl01i = '1' ELSE wire_ni00i0lO_dataout; + wire_ni00i0ii_dataout <= wire_nii0l00O_dataout WHEN niOlOl01i = '1' ELSE wire_ni00ii1i_dataout; + wire_ni00i0il_dataout <= wire_nii0l0ii_dataout WHEN niOlOl01i = '1' ELSE wire_ni00ii1l_dataout; + wire_ni00i0iO_dataout <= wire_nii0l0il_dataout WHEN niOlOl01i = '1' ELSE wire_ni00ii1O_dataout; + wire_ni00i0li_dataout <= ni00011i WHEN niOlOl0Ol = '1' ELSE ni000ill; + wire_ni00i0ll_dataout <= ni000i1O WHEN niOlOl0Ol = '1' ELSE ni000OOi; + wire_ni00i0lO_dataout <= ni000i0i WHEN niOlOl0Ol = '1' ELSE ni000OOl; + wire_ni00i0Oi_dataout <= ni000i0l WHEN niOlOl0Ol = '1' ELSE ni000OOO; + wire_ni00i0Ol_dataout <= ni000i0O WHEN niOlOl0Ol = '1' ELSE ni00i11i; + wire_ni00i0OO_dataout <= ni000iii WHEN niOlOl0Ol = '1' ELSE ni00i11l; + wire_ni00i1ii_dataout <= wire_ni00i01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1il_dataout <= wire_ni00i01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1iO_dataout <= wire_ni00i01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1li_dataout <= wire_ni00i00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1ll_dataout <= wire_ni00i00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1lO_dataout <= wire_ni00i00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1Oi_dataout <= wire_ni00i0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1Ol_dataout <= wire_ni00i0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00i1OO_dataout <= wire_ni00i0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00ii1i_dataout <= ni000iil WHEN niOlOl0Ol = '1' ELSE ni00i11O; + wire_ni00ii1l_dataout <= ni000iiO WHEN niOlOl0Ol = '1' ELSE ni00i10i; + wire_ni00ii1O_dataout <= ni000ili WHEN niOlOl0Ol = '1' ELSE ni00i10l; + wire_ni00il0i_dataout <= wire_ni00ilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00il0l_dataout <= wire_ni00ilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00il0O_dataout <= wire_ni00ilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00il1l_dataout <= wire_ni00illl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00il1O_dataout <= wire_ni00illO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00ilii_dataout <= wire_ni00iO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00ilil_dataout <= wire_ni00iO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00iliO_dataout <= wire_ni00iO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00illi_dataout <= wire_ni00iO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00illl_dataout <= wire_nii0l1OO_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iO0l_dataout; + wire_ni00illO_dataout <= wire_nii0l01i_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iO0O_dataout; + wire_ni00ilOi_dataout <= wire_nii0l01l_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iOii_dataout; + wire_ni00ilOl_dataout <= wire_nii0l01O_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iOil_dataout; + wire_ni00ilOO_dataout <= wire_nii0l00i_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iOiO_dataout; + wire_ni00iO0i_dataout <= wire_nii0l0il_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iOOi_dataout; + wire_ni00iO0l_dataout <= ni000ill WHEN niOlOl0Ol = '1' ELSE ni00i10O; + wire_ni00iO0O_dataout <= ni000OOi WHEN niOlOl0Ol = '1' ELSE ni00iiil; + wire_ni00iO1i_dataout <= wire_nii0l00l_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iOli_dataout; + wire_ni00iO1l_dataout <= wire_nii0l00O_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iOll_dataout; + wire_ni00iO1O_dataout <= wire_nii0l0ii_dataout WHEN niOlOl01O = '1' ELSE wire_ni00iOlO_dataout; + wire_ni00iOi_dataout <= wire_ni0l1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00iOii_dataout <= ni000OOl WHEN niOlOl0Ol = '1' ELSE ni00iiiO; + wire_ni00iOil_dataout <= ni000OOO WHEN niOlOl0Ol = '1' ELSE ni00iili; + wire_ni00iOiO_dataout <= ni00i11i WHEN niOlOl0Ol = '1' ELSE ni00iill; + wire_ni00iOl_dataout <= wire_ni0l1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00iOli_dataout <= ni00i11l WHEN niOlOl0Ol = '1' ELSE ni00iilO; + wire_ni00iOll_dataout <= ni00i11O WHEN niOlOl0Ol = '1' ELSE ni00iiOi; + wire_ni00iOlO_dataout <= ni00i10i WHEN niOlOl0Ol = '1' ELSE ni00iiOl; + wire_ni00iOO_dataout <= wire_ni00OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00iOOi_dataout <= ni00i10l WHEN niOlOl0Ol = '1' ELSE ni00iiOO; + wire_ni00l00i_dataout <= wire_ni00l0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l00l_dataout <= wire_ni00l0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l00O_dataout <= wire_nii0l1OO_dataout WHEN niOlOl00l = '1' ELSE wire_ni00l0OO_dataout; + wire_ni00l01i_dataout <= wire_ni00l0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l01l_dataout <= wire_ni00l0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l01O_dataout <= wire_ni00l0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l0i_dataout <= wire_ni0i11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00l0ii_dataout <= wire_nii0l01i_dataout WHEN niOlOl00l = '1' ELSE wire_ni00li1i_dataout; + wire_ni00l0il_dataout <= wire_nii0l01l_dataout WHEN niOlOl00l = '1' ELSE wire_ni00li1l_dataout; + wire_ni00l0iO_dataout <= wire_nii0l01O_dataout WHEN niOlOl00l = '1' ELSE wire_ni00li1O_dataout; + wire_ni00l0l_dataout <= wire_ni0i11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00l0li_dataout <= wire_nii0l00i_dataout WHEN niOlOl00l = '1' ELSE wire_ni00li0i_dataout; + wire_ni00l0ll_dataout <= wire_nii0l00l_dataout WHEN niOlOl00l = '1' ELSE wire_ni00li0l_dataout; + wire_ni00l0lO_dataout <= wire_nii0l00O_dataout WHEN niOlOl00l = '1' ELSE wire_ni00li0O_dataout; + wire_ni00l0O_dataout <= wire_ni0i11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00l0Oi_dataout <= wire_nii0l0ii_dataout WHEN niOlOl00l = '1' ELSE wire_ni00liii_dataout; + wire_ni00l0Ol_dataout <= wire_nii0l0il_dataout WHEN niOlOl00l = '1' ELSE wire_ni00liil_dataout; + wire_ni00l0OO_dataout <= ni00i10O WHEN niOlOl0Ol = '1' ELSE ni00il1i; + wire_ni00l1i_dataout <= wire_ni00OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00l1l_dataout <= wire_ni00OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00l1lO_dataout <= wire_ni00l00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l1O_dataout <= wire_ni00OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00l1Oi_dataout <= wire_ni00l0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l1Ol_dataout <= wire_ni00l0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00l1OO_dataout <= wire_ni00l0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00li0i_dataout <= ni00iill WHEN niOlOl0Ol = '1' ELSE ni00l10O; + wire_ni00li0l_dataout <= ni00iilO WHEN niOlOl0Ol = '1' ELSE ni00l1ii; + wire_ni00li0O_dataout <= ni00iiOi WHEN niOlOl0Ol = '1' ELSE ni00l1il; + wire_ni00li1i_dataout <= ni00iiil WHEN niOlOl0Ol = '1' ELSE ni00l11O; + wire_ni00li1l_dataout <= ni00iiiO WHEN niOlOl0Ol = '1' ELSE ni00l10i; + wire_ni00li1O_dataout <= ni00iili WHEN niOlOl0Ol = '1' ELSE ni00l10l; + wire_ni00lii_dataout <= wire_ni0i10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00liii_dataout <= ni00iiOl WHEN niOlOl0Ol = '1' ELSE ni00l1iO; + wire_ni00liil_dataout <= ni00iiOO WHEN niOlOl0Ol = '1' ELSE ni00l1li; + wire_ni00lil_dataout <= wire_ni0i10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00liO_dataout <= wire_ni0i10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00ll0i_dataout <= wire_ni00llli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00ll0l_dataout <= wire_ni00llll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00ll0O_dataout <= wire_ni00lllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00ll1l_dataout <= niOlOl00O AND NOT(wire_niO01lOO_dataout); + wire_ni00ll1O_dataout <= wire_ni00lliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni00lli_dataout <= wire_ni0i1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00lliO_dataout <= wire_ni00llOi_dataout AND NOT(niOlOllli); + wire_ni00lll_dataout <= wire_ni0i1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00llli_dataout <= wire_ni00llOl_dataout AND NOT(niOlOllli); + wire_ni00llll_dataout <= wire_ni00llOO_dataout AND NOT(niOlOllli); + wire_ni00lllO_dataout <= wire_ni00lO1i_dataout AND NOT(niOlOllli); + wire_ni00llO_dataout <= wire_ni0i1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00llOi_dataout <= wire_w_lg_niOlOl0il10873w(0) WHEN niOlOl0li = '1' ELSE wire_ni00lO1l_dataout; + wire_ni00llOl_dataout <= wire_ni00lOil_o(1) WHEN niOlOl0li = '1' ELSE wire_ni00lO1O_dataout; + wire_ni00llOO_dataout <= wire_ni00lOil_o(2) WHEN niOlOl0li = '1' ELSE wire_ni00lO0i_dataout; + wire_ni00lO0i_dataout <= wire_ni00lO0O_o(1) WHEN niOlOl0iO = '1' ELSE ni00liOO; + wire_ni00lO0l_dataout <= wire_ni00lO0O_o(2) WHEN niOlOl0iO = '1' ELSE ni00ll1i; + wire_ni00lO1i_dataout <= wire_ni00lOil_o(3) WHEN niOlOl0li = '1' ELSE wire_ni00lO0l_dataout; + wire_ni00lO1l_dataout <= ni00liOi OR niOlOl0iO; + wire_ni00lO1O_dataout <= wire_ni00lO0O_o(0) WHEN niOlOl0iO = '1' ELSE ni00liOl; + wire_ni00lOi_dataout <= wire_ni0i1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00lOl_dataout <= wire_ni0i1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00lOO_dataout <= wire_ni0i1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00O0i_dataout <= wire_ni0i01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00O0l_dataout <= wire_ni0i01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00O0O_dataout <= wire_ni0i01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00O1i_dataout <= wire_ni0i1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00O1l_dataout <= wire_ni0i1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00O1O_dataout <= wire_ni0i1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00Oii_dataout <= wire_ni0i00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00Oil_dataout <= wire_ni0i00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00OiO_dataout <= wire_ni0i00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00Oli_dataout <= wire_ni0i0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00Oll_dataout <= wire_ni0i0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni00OlO_dataout <= wire_ni0ii1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni001OO; + wire_ni00OOi_dataout <= wire_ni0ii1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni0001i; + wire_ni00OOl_dataout <= wire_ni0ii1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni0001l; + wire_ni00OOO_dataout <= wire_ni0ii0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni0001O; + wire_ni0100li_dataout <= wire_ni010i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0100ll_dataout <= wire_ni010i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0100lO_dataout <= wire_ni010i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0100Oi_dataout <= wire_ni010iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0100Ol_dataout <= wire_ni010iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0100OO_dataout <= wire_ni010iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01010i_dataout <= ni0111ll WHEN niOlOl0Ol = '1' ELSE ni011l0O; + wire_ni01010l_dataout <= ni0111lO WHEN niOlOl0Ol = '1' ELSE ni011lii; + wire_ni01010O_dataout <= ni0111Oi WHEN niOlOl0Ol = '1' ELSE ni011lil; + wire_ni01011i_dataout <= wire_nii0ll1l_dataout WHEN niOlOiOil = '1' ELSE wire_ni0101li_dataout; + wire_ni01011l_dataout <= wire_nii0ll1O_dataout WHEN niOlOiOil = '1' ELSE wire_ni0101ll_dataout; + wire_ni01011O_dataout <= ni1OOllO WHEN niOlOl0Ol = '1' ELSE ni01100i; + wire_ni0101i_dataout <= wire_n0OOO0O_q(73) WHEN niOO0l01O = '1' ELSE ni1lOii; + wire_ni0101ii_dataout <= ni0111Ol WHEN niOlOl0Ol = '1' ELSE ni011liO; + wire_ni0101il_dataout <= ni0111OO WHEN niOlOl0Ol = '1' ELSE ni011lli; + wire_ni0101iO_dataout <= ni01101i WHEN niOlOl0Ol = '1' ELSE ni011lll; + wire_ni0101l_dataout <= (NOT wire_n0OOO0O_q(93)) WHEN niOO0l01O = '1' ELSE ni1lOll; + wire_ni0101li_dataout <= ni01101l WHEN niOlOl0Ol = '1' ELSE ni011llO; + wire_ni0101ll_dataout <= ni01101O WHEN niOlOl0Ol = '1' ELSE ni011lOi; + wire_ni0101O_dataout <= wire_n0OOO0O_q(94) WHEN niOO0l01O = '1' ELSE ni1lOOi; + wire_ni010i0i_dataout <= wire_nii0lili_dataout WHEN niOlOiOli = '1' ELSE wire_ni010iOi_dataout; + wire_ni010i0l_dataout <= wire_nii0lill_dataout WHEN niOlOiOli = '1' ELSE wire_ni010iOl_dataout; + wire_ni010i0O_dataout <= wire_nii0lilO_dataout WHEN niOlOiOli = '1' ELSE wire_ni010iOO_dataout; + wire_ni010i1i_dataout <= wire_ni010ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010i1l_dataout <= wire_ni010ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010i1O_dataout <= wire_ni010ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010ii_dataout <= wire_ni010il_dataout OR (wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_ni1lOlO_w_lg_ni1ll0l2460w(0)); + wire_ni010ii_w_lg_dataout2517w(0) <= NOT wire_ni010ii_dataout; + wire_ni010iii_dataout <= wire_nii0liOi_dataout WHEN niOlOiOli = '1' ELSE wire_ni010l1i_dataout; + wire_ni010iil_dataout <= wire_nii0liOl_dataout WHEN niOlOiOli = '1' ELSE wire_ni010l1l_dataout; + wire_ni010iiO_dataout <= wire_nii0liOO_dataout WHEN niOlOiOli = '1' ELSE wire_ni010l1O_dataout; + wire_ni010il_dataout <= wire_ni010iO_dataout OR wire_w_lg_w_k_hip_range2413w2459w(0); + wire_ni010ili_dataout <= wire_nii0ll1i_dataout WHEN niOlOiOli = '1' ELSE wire_ni010l0i_dataout; + wire_ni010ill_dataout <= wire_nii0ll1l_dataout WHEN niOlOiOli = '1' ELSE wire_ni010l0l_dataout; + wire_ni010ilO_dataout <= wire_nii0ll1O_dataout WHEN niOlOiOli = '1' ELSE wire_ni010l0O_dataout; + wire_ni010iO_dataout <= wire_ni010li_dataout OR wire_w_lg_w_k_hip_range2413w2457w(0); + wire_ni010iOi_dataout <= ni01100i WHEN niOlOl0Ol = '1' ELSE ni011lOl; + wire_ni010iOl_dataout <= ni011l0O WHEN niOlOl0Ol = '1' ELSE ni01001i; + wire_ni010iOO_dataout <= ni011lii WHEN niOlOl0Ol = '1' ELSE ni01001l; + wire_ni010l0i_dataout <= ni011lll WHEN niOlOl0Ol = '1' ELSE ni01000O; + wire_ni010l0l_dataout <= ni011llO WHEN niOlOl0Ol = '1' ELSE ni0100ii; + wire_ni010l0O_dataout <= ni011lOi WHEN niOlOl0Ol = '1' ELSE ni0100il; + wire_ni010l1i_dataout <= ni011lil WHEN niOlOl0Ol = '1' ELSE ni01001O; + wire_ni010l1l_dataout <= ni011liO WHEN niOlOl0Ol = '1' ELSE ni01000i; + wire_ni010l1O_dataout <= ni011lli WHEN niOlOl0Ol = '1' ELSE ni01000l; + wire_ni010li_dataout <= wire_ni010ll_dataout OR wire_w_lg_w_k_hip_range2413w2455w(0); + wire_ni010ll_dataout <= (wire_n0OOO0O_q(131) AND wire_n0OOO0O_q(128)) OR (wire_w_lg_w_k_hip_range2413w2429w(0) AND (wire_ni1lOlO_w_lg_ni1l11l2447w(0) AND wire_n0OOO0O_q(129))); + wire_ni010O0l_dataout <= wire_ni010OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010O0O_dataout <= wire_ni010OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010Oii_dataout <= wire_ni01i11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010Oil_dataout <= wire_ni01i11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010OiO_dataout <= wire_ni01i11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010Oli_dataout <= wire_ni01i10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010Oll_dataout <= wire_ni01i10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010OlO_dataout <= wire_ni01i10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010OOi_dataout <= wire_ni01i1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni010OOl_dataout <= wire_nii0lili_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1il_dataout; + wire_ni010OOO_dataout <= wire_nii0lill_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1iO_dataout; + wire_ni01100l_dataout <= wire_ni0110Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01100O_dataout <= wire_ni0110OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110i_dataout <= ni1ll0l AND NOT(niOO0l01O); + wire_ni0110ii_dataout <= wire_ni011i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110il_dataout <= wire_ni011i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110iO_dataout <= wire_ni011i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110l_dataout <= ni1ll0O OR niOO0l01O; + wire_ni0110li_dataout <= wire_ni011i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110ll_dataout <= wire_ni011i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110lO_dataout <= wire_ni011i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110O_dataout <= ni1llil AND NOT(niOO0l01O); + wire_ni0110Oi_dataout <= wire_ni011iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0110Ol_dataout <= wire_nii0lili_dataout WHEN niOlOiOii = '1' ELSE wire_ni011iil_dataout; + wire_ni0110OO_dataout <= wire_nii0lill_dataout WHEN niOlOiOii = '1' ELSE wire_ni011iiO_dataout; + wire_ni01110i_dataout <= ni1OOl0O AND NOT(niOlOl0Ol); + wire_ni01110l_dataout <= ni1OOlii AND NOT(niOlOl0Ol); + wire_ni01110O_dataout <= ni1OOlil AND NOT(niOlOl0Ol); + wire_ni01111i_dataout <= ni0111li AND NOT(niOlOl0Ol); + wire_ni01111l_dataout <= ni1OOl0i AND NOT(niOlOl0Ol); + wire_ni01111O_dataout <= ni1OOl0l AND NOT(niOlOl0Ol); + wire_ni0111i_dataout <= ni1llli AND NOT(niOO0l01O); + wire_ni0111ii_dataout <= ni1OOliO AND NOT(niOlOl0Ol); + wire_ni0111il_dataout <= ni1OOlli AND NOT(niOlOl0Ol); + wire_ni0111iO_dataout <= ni1OOlll AND NOT(niOlOl0Ol); + wire_ni0111l_dataout <= niOO0l00O WHEN niOO0l01O = '1' ELSE ni1llll; + wire_ni0111O_dataout <= ni1l11l AND NOT(niOO0l01O); + wire_ni011i0i_dataout <= wire_nii0liOO_dataout WHEN niOlOiOii = '1' ELSE wire_ni011iOi_dataout; + wire_ni011i0l_dataout <= wire_nii0ll1i_dataout WHEN niOlOiOii = '1' ELSE wire_ni011iOl_dataout; + wire_ni011i0O_dataout <= wire_nii0ll1l_dataout WHEN niOlOiOii = '1' ELSE wire_ni011iOO_dataout; + wire_ni011i1i_dataout <= wire_nii0lilO_dataout WHEN niOlOiOii = '1' ELSE wire_ni011ili_dataout; + wire_ni011i1l_dataout <= wire_nii0liOi_dataout WHEN niOlOiOii = '1' ELSE wire_ni011ill_dataout; + wire_ni011i1O_dataout <= wire_nii0liOl_dataout WHEN niOlOiOii = '1' ELSE wire_ni011ilO_dataout; + wire_ni011ii_dataout <= wire_n0OOO0O_q(64) WHEN niOO0l01O = '1' ELSE ni1llOi; + wire_ni011iii_dataout <= wire_nii0ll1O_dataout WHEN niOlOiOii = '1' ELSE wire_ni011l1i_dataout; + wire_ni011iil_dataout <= ni0111li WHEN niOlOl0Ol = '1' ELSE ni1OOllO; + wire_ni011iiO_dataout <= ni1OOl0i WHEN niOlOl0Ol = '1' ELSE ni0111ll; + wire_ni011il_dataout <= wire_n0OOO0O_q(65) WHEN niOO0l01O = '1' ELSE ni1llOl; + wire_ni011ili_dataout <= ni1OOl0l WHEN niOlOl0Ol = '1' ELSE ni0111lO; + wire_ni011ill_dataout <= ni1OOl0O WHEN niOlOl0Ol = '1' ELSE ni0111Oi; + wire_ni011ilO_dataout <= ni1OOlii WHEN niOlOl0Ol = '1' ELSE ni0111Ol; + wire_ni011iO_dataout <= wire_n0OOO0O_q(66) WHEN niOO0l01O = '1' ELSE ni1llOO; + wire_ni011iOi_dataout <= ni1OOlil WHEN niOlOl0Ol = '1' ELSE ni0111OO; + wire_ni011iOl_dataout <= ni1OOliO WHEN niOlOl0Ol = '1' ELSE ni01101i; + wire_ni011iOO_dataout <= ni1OOlli WHEN niOlOl0Ol = '1' ELSE ni01101l; + wire_ni011l1i_dataout <= ni1OOlll WHEN niOlOl0Ol = '1' ELSE ni01101O; + wire_ni011li_dataout <= wire_n0OOO0O_q(67) WHEN niOO0l01O = '1' ELSE ni1lO1i; + wire_ni011ll_dataout <= wire_n0OOO0O_q(68) WHEN niOO0l01O = '1' ELSE ni1lO1l; + wire_ni011lO_dataout <= wire_n0OOO0O_q(69) WHEN niOO0l01O = '1' ELSE ni1lO1O; + wire_ni011lOO_dataout <= wire_ni011OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011O0i_dataout <= wire_ni011OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011O0l_dataout <= wire_ni011OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011O0O_dataout <= wire_ni011OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011O1i_dataout <= wire_ni011Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011O1l_dataout <= wire_ni011Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011O1O_dataout <= wire_ni011OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011Oi_dataout <= wire_n0OOO0O_q(70) WHEN niOO0l01O = '1' ELSE ni1lO0i; + wire_ni011Oii_dataout <= wire_ni01011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011Oil_dataout <= wire_ni01011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni011OiO_dataout <= wire_nii0lili_dataout WHEN niOlOiOil = '1' ELSE wire_ni01011O_dataout; + wire_ni011Ol_dataout <= wire_n0OOO0O_q(71) WHEN niOO0l01O = '1' ELSE ni1lO0l; + wire_ni011Oli_dataout <= wire_nii0lill_dataout WHEN niOlOiOil = '1' ELSE wire_ni01010i_dataout; + wire_ni011Oll_dataout <= wire_nii0lilO_dataout WHEN niOlOiOil = '1' ELSE wire_ni01010l_dataout; + wire_ni011OlO_dataout <= wire_nii0liOi_dataout WHEN niOlOiOil = '1' ELSE wire_ni01010O_dataout; + wire_ni011OO_dataout <= wire_n0OOO0O_q(72) WHEN niOO0l01O = '1' ELSE ni1lO0O; + wire_ni011OOi_dataout <= wire_nii0liOl_dataout WHEN niOlOiOil = '1' ELSE wire_ni0101ii_dataout; + wire_ni011OOl_dataout <= wire_nii0liOO_dataout WHEN niOlOiOil = '1' ELSE wire_ni0101il_dataout; + wire_ni011OOO_dataout <= wire_nii0ll1i_dataout WHEN niOlOiOil = '1' ELSE wire_ni0101iO_dataout; + wire_ni01i01i_dataout <= ni0100il WHEN niOlOl0Ol = '1' ELSE ni010O1O; + wire_ni01i0OO_dataout <= wire_ni01iiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01i10i_dataout <= wire_nii0liOO_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1Oi_dataout; + wire_ni01i10l_dataout <= wire_nii0ll1i_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1Ol_dataout; + wire_ni01i10O_dataout <= wire_nii0ll1l_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1OO_dataout; + wire_ni01i11i_dataout <= wire_nii0lilO_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1li_dataout; + wire_ni01i11l_dataout <= wire_nii0liOi_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1ll_dataout; + wire_ni01i11O_dataout <= wire_nii0liOl_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i1lO_dataout; + wire_ni01i1ii_dataout <= wire_nii0ll1O_dataout WHEN niOlOiOlO = '1' ELSE wire_ni01i01i_dataout; + wire_ni01i1il_dataout <= ni011lOl WHEN niOlOl0Ol = '1' ELSE ni0100iO; + wire_ni01i1iO_dataout <= ni01001i WHEN niOlOl0Ol = '1' ELSE ni010lll; + wire_ni01i1li_dataout <= ni01001l WHEN niOlOl0Ol = '1' ELSE ni010llO; + wire_ni01i1ll_dataout <= ni01001O WHEN niOlOl0Ol = '1' ELSE ni010lOi; + wire_ni01i1lO_dataout <= ni01000i WHEN niOlOl0Ol = '1' ELSE ni010lOl; + wire_ni01i1Oi_dataout <= ni01000l WHEN niOlOl0Ol = '1' ELSE ni010lOO; + wire_ni01i1Ol_dataout <= ni01000O WHEN niOlOl0Ol = '1' ELSE ni010O1i; + wire_ni01i1OO_dataout <= ni0100ii WHEN niOlOl0Ol = '1' ELSE ni010O1l; + wire_ni01ii0i_dataout <= wire_ni01iiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01ii0l_dataout <= wire_ni01iiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01ii0O_dataout <= wire_ni01iiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01ii1i_dataout <= wire_ni01iili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01ii1l_dataout <= wire_ni01iill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01ii1O_dataout <= wire_ni01iilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iiii_dataout <= wire_ni01il1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iiil_dataout <= wire_ni01il1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iiiO_dataout <= wire_nii0lili_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01il1O_dataout; + wire_ni01iili_dataout <= wire_nii0lill_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01il0i_dataout; + wire_ni01iill_dataout <= wire_nii0lilO_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01il0l_dataout; + wire_ni01iilO_dataout <= wire_nii0liOi_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01il0O_dataout; + wire_ni01iiOi_dataout <= wire_nii0liOl_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01ilii_dataout; + wire_ni01iiOl_dataout <= wire_nii0liOO_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01ilil_dataout; + wire_ni01iiOO_dataout <= wire_nii0ll1i_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01iliO_dataout; + wire_ni01il0i_dataout <= ni010lll WHEN niOlOl0Ol = '1' ELSE ni01i00O; + wire_ni01il0l_dataout <= ni010llO WHEN niOlOl0Ol = '1' ELSE ni01i0ii; + wire_ni01il0O_dataout <= ni010lOi WHEN niOlOl0Ol = '1' ELSE ni01i0il; + wire_ni01il1i_dataout <= wire_nii0ll1l_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01illi_dataout; + wire_ni01il1l_dataout <= wire_nii0ll1O_dataout WHEN niOlOiOOl = '1' ELSE wire_ni01illl_dataout; + wire_ni01il1O_dataout <= ni0100iO WHEN niOlOl0Ol = '1' ELSE ni010O0i; + wire_ni01ilii_dataout <= ni010lOl WHEN niOlOl0Ol = '1' ELSE ni01i0iO; + wire_ni01ilil_dataout <= ni010lOO WHEN niOlOl0Ol = '1' ELSE ni01i0li; + wire_ni01iliO_dataout <= ni010O1i WHEN niOlOl0Ol = '1' ELSE ni01i0ll; + wire_ni01ill_dataout <= wire_n0OOO0O_q(66) WHEN (wire_w_lg_w_k_hip_range2413w2429w(0) AND ni1lOll) = '1' ELSE wire_ni01ilO_dataout; + wire_ni01ill_w_lg_w_lg_dataout2483w2484w(0) <= wire_ni01ill_w_lg_dataout2483w(0) AND ni1iOOO; + wire_ni01ill_w_lg_w_lg_dataout2485w2486w(0) <= wire_ni01ill_w_lg_dataout2485w(0) AND ni1lOll; + wire_ni01ill_w_lg_dataout2483w(0) <= wire_ni01ill_dataout AND ni1lOll; + wire_ni01ill_w_lg_dataout2485w(0) <= NOT wire_ni01ill_dataout; + wire_ni01illi_dataout <= ni010O1l WHEN niOlOl0Ol = '1' ELSE ni01i0lO; + wire_ni01illl_dataout <= ni010O1O WHEN niOlOl0Ol = '1' ELSE ni01i0Oi; + wire_ni01ilO_dataout <= wire_n0OOO0O_q(98) WHEN (wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_ni1lOlO_w_lg_ni1lOll2437w(0)) = '1' ELSE wire_ni01iOi_dataout; + wire_ni01iOi_dataout <= ni1iOOi WHEN wire_w_lg_w_k_hip_range2413w2438w(0) = '1' ELSE ni1iOOl; + wire_ni01iOli_dataout <= wire_ni01l10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iOll_dataout <= wire_ni01l10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iOlO_dataout <= wire_ni01l10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iOOi_dataout <= wire_ni01l1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iOOl_dataout <= wire_ni01l1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01iOOO_dataout <= wire_ni01l1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01l00i_dataout <= ni01i0ll WHEN niOlOl0Ol = '1' ELSE ni01iO0O; + wire_ni01l00l_dataout <= ni01i0lO WHEN niOlOl0Ol = '1' ELSE ni01iOii; + wire_ni01l00O_dataout <= ni01i0Oi WHEN niOlOl0Ol = '1' ELSE ni01iOil; + wire_ni01l01i_dataout <= ni01i0il WHEN niOlOl0Ol = '1' ELSE ni01iO1O; + wire_ni01l01l_dataout <= ni01i0iO WHEN niOlOl0Ol = '1' ELSE ni01iO0i; + wire_ni01l01O_dataout <= ni01i0li WHEN niOlOl0Ol = '1' ELSE ni01iO0l; + wire_ni01l10i_dataout <= wire_nii0lili_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l1Oi_dataout; + wire_ni01l10l_dataout <= wire_nii0lill_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l1Ol_dataout; + wire_ni01l10O_dataout <= wire_nii0lilO_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l1OO_dataout; + wire_ni01l11i_dataout <= wire_ni01l1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01l11l_dataout <= wire_ni01l1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01l11O_dataout <= wire_ni01l1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01l1ii_dataout <= wire_nii0liOi_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l01i_dataout; + wire_ni01l1il_dataout <= wire_nii0liOl_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l01l_dataout; + wire_ni01l1iO_dataout <= wire_nii0liOO_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l01O_dataout; + wire_ni01l1l_dataout <= (wire_w_lg_w_k_hip_range2413w2424w(0) AND wire_ni1llii_w_lg_w_lg_ni1llil2426w2427w(0)) OR ((wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_ni1lOlO_w_lg_ni1lliO2423w(0)) AND (wire_ni1llii_w_lg_ni1llil2426w(0) OR wire_ni1llii_w_lg_ni1llil2431w(0))); + wire_ni01l1li_dataout <= wire_nii0ll1i_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l00i_dataout; + wire_ni01l1ll_dataout <= wire_nii0ll1l_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l00l_dataout; + wire_ni01l1lO_dataout <= wire_nii0ll1O_dataout WHEN niOlOl11i = '1' ELSE wire_ni01l00O_dataout; + wire_ni01l1Oi_dataout <= ni010O0i WHEN niOlOl0Ol = '1' ELSE ni01i0Ol; + wire_ni01l1Ol_dataout <= ni01i00O WHEN niOlOl0Ol = '1' ELSE ni01iO1i; + wire_ni01l1OO_dataout <= ni01i0ii WHEN niOlOl0Ol = '1' ELSE ni01iO1l; + wire_ni01li0l_dataout <= wire_ni01liOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01li0O_dataout <= wire_ni01liOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01liii_dataout <= wire_ni01ll1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01liil_dataout <= wire_ni01ll1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01liiO_dataout <= wire_ni01ll1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01lili_dataout <= wire_ni01ll0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01lill_dataout <= wire_ni01ll0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01lilO_dataout <= wire_ni01ll0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01liOi_dataout <= wire_ni01llii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01liOl_dataout <= wire_nii0lili_dataout WHEN niOlOl11O = '1' ELSE wire_ni01llil_dataout; + wire_ni01liOO_dataout <= wire_nii0lill_dataout WHEN niOlOl11O = '1' ELSE wire_ni01lliO_dataout; + wire_ni01ll0i_dataout <= wire_nii0liOO_dataout WHEN niOlOl11O = '1' ELSE wire_ni01llOi_dataout; + wire_ni01ll0l_dataout <= wire_nii0ll1i_dataout WHEN niOlOl11O = '1' ELSE wire_ni01llOl_dataout; + wire_ni01ll0O_dataout <= wire_nii0ll1l_dataout WHEN niOlOl11O = '1' ELSE wire_ni01llOO_dataout; + wire_ni01ll1i_dataout <= wire_nii0lilO_dataout WHEN niOlOl11O = '1' ELSE wire_ni01llli_dataout; + wire_ni01ll1l_dataout <= wire_nii0liOi_dataout WHEN niOlOl11O = '1' ELSE wire_ni01llll_dataout; + wire_ni01ll1O_dataout <= wire_nii0liOl_dataout WHEN niOlOl11O = '1' ELSE wire_ni01lllO_dataout; + wire_ni01llii_dataout <= wire_nii0ll1O_dataout WHEN niOlOl11O = '1' ELSE wire_ni01lO1i_dataout; + wire_ni01llil_dataout <= ni01i0Ol WHEN niOlOl0Ol = '1' ELSE ni01iOiO; + wire_ni01lliO_dataout <= ni01iO1i WHEN niOlOl0Ol = '1' ELSE ni01l0ll; + wire_ni01llli_dataout <= ni01iO1l WHEN niOlOl0Ol = '1' ELSE ni01l0lO; + wire_ni01llll_dataout <= ni01iO1O WHEN niOlOl0Ol = '1' ELSE ni01l0Oi; + wire_ni01lllO_dataout <= ni01iO0i WHEN niOlOl0Ol = '1' ELSE ni01l0Ol; + wire_ni01llOi_dataout <= ni01iO0l WHEN niOlOl0Ol = '1' ELSE ni01l0OO; + wire_ni01llOl_dataout <= ni01iO0O WHEN niOlOl0Ol = '1' ELSE ni01li1i; + wire_ni01llOO_dataout <= ni01iOii WHEN niOlOl0Ol = '1' ELSE ni01li1l; + wire_ni01lO1i_dataout <= ni01iOil WHEN niOlOl0Ol = '1' ELSE ni01li1O; + wire_ni01lOli_dataout <= niOlOl10i AND NOT(wire_niO01lOO_dataout); + wire_ni01lOll_dataout <= wire_ni01O11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01lOlO_dataout <= wire_ni01O11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01lOO_dataout <= wire_ni01O0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni01lOOi_dataout <= wire_ni01O10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01lOOl_dataout <= wire_ni01O10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01O0i_dataout <= niOO0l0lO WHEN niOO0l0iO = '1' ELSE wire_ni01O0O_dataout; + wire_ni01O0l_dataout <= niOO0l0Ol WHEN niOO0l0iO = '1' ELSE wire_ni01Oii_dataout; + wire_ni01O0O_dataout <= ni01llO AND niOO0l0il; + wire_ni01O10i_dataout <= wire_ni01O1il_dataout AND NOT(niOlOlO0i); + wire_ni01O10l_dataout <= wire_ni01O1iO_dataout AND NOT(niOlOlO0i); + wire_ni01O10O_dataout <= wire_w_lg_niOlOl10O10954w(0) WHEN niOlOl1il = '1' ELSE wire_ni01O1li_dataout; + wire_ni01O11l_dataout <= wire_ni01O10O_dataout AND NOT(niOlOlO0i); + wire_ni01O11O_dataout <= wire_ni01O1ii_dataout AND NOT(niOlOlO0i); + wire_ni01O1i_dataout <= wire_ni01O0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni01O1ii_dataout <= wire_ni01O01i_o(1) WHEN niOlOl1il = '1' ELSE wire_ni01O1ll_dataout; + wire_ni01O1il_dataout <= wire_ni01O01i_o(2) WHEN niOlOl1il = '1' ELSE wire_ni01O1lO_dataout; + wire_ni01O1iO_dataout <= wire_ni01O01i_o(3) WHEN niOlOl1il = '1' ELSE wire_ni01O1Oi_dataout; + wire_ni01O1l_dataout <= wire_ni01OOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni01O1li_dataout <= ni01lO0O OR niOlOl1ii; + wire_ni01O1ll_dataout <= wire_ni01O1Ol_o(0) WHEN niOlOl1ii = '1' ELSE ni01lOii; + wire_ni01O1lO_dataout <= wire_ni01O1Ol_o(1) WHEN niOlOl1ii = '1' ELSE ni01lOil; + wire_ni01O1O_dataout <= wire_ni01OOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni01O1Oi_dataout <= wire_ni01O1Ol_o(2) WHEN niOlOl1ii = '1' ELSE ni01lOiO; + wire_ni01Oi0l_dataout <= wire_ni01OiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01Oi0O_dataout <= wire_ni01OiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01Oii_dataout <= ni01lOl AND niOO0l0il; + wire_ni01Oiii_dataout <= wire_ni01Ol1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01Oiil_dataout <= wire_ni01Ol1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01OiiO_dataout <= wire_ni01Ol1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01Oili_dataout <= wire_ni01Ol0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01Oill_dataout <= wire_ni01Ol0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01OilO_dataout <= wire_ni01Ol0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01OiOi_dataout <= wire_ni01Olii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01OiOl_dataout <= wire_nii0l1OO_dataout WHEN niOlOl00O = '1' ELSE wire_ni01Olil_dataout; + wire_ni01OiOO_dataout <= wire_nii0l01i_dataout WHEN niOlOl00O = '1' ELSE wire_ni01OliO_dataout; + wire_ni01Ol0i_dataout <= wire_nii0l00l_dataout WHEN niOlOl00O = '1' ELSE wire_ni01OlOi_dataout; + wire_ni01Ol0l_dataout <= wire_nii0l00O_dataout WHEN niOlOl00O = '1' ELSE wire_ni01OlOl_dataout; + wire_ni01Ol0O_dataout <= wire_nii0l0ii_dataout WHEN niOlOl00O = '1' ELSE wire_ni01OlOO_dataout; + wire_ni01Ol1i_dataout <= wire_nii0l01l_dataout WHEN niOlOl00O = '1' ELSE wire_ni01Olli_dataout; + wire_ni01Ol1l_dataout <= wire_nii0l01O_dataout WHEN niOlOl00O = '1' ELSE wire_ni01Olll_dataout; + wire_ni01Ol1O_dataout <= wire_nii0l00i_dataout WHEN niOlOl00O = '1' ELSE wire_ni01OllO_dataout; + wire_ni01Olii_dataout <= wire_nii0l0il_dataout WHEN niOlOl00O = '1' ELSE wire_ni01OO1i_dataout; + wire_ni01Olil_dataout <= ni01OO1l AND NOT(niOlOl0Ol); + wire_ni01OliO_dataout <= ni01O0ll AND NOT(niOlOl0Ol); + wire_ni01Olli_dataout <= ni01O0lO AND NOT(niOlOl0Ol); + wire_ni01Olll_dataout <= ni01O0Oi AND NOT(niOlOl0Ol); + wire_ni01OllO_dataout <= ni01O0Ol AND NOT(niOlOl0Ol); + wire_ni01OlOi_dataout <= ni01O0OO AND NOT(niOlOl0Ol); + wire_ni01OlOl_dataout <= ni01Oi1i AND NOT(niOlOl0Ol); + wire_ni01OlOO_dataout <= ni01Oi1l AND NOT(niOlOl0Ol); + wire_ni01OO1i_dataout <= ni01Oi1O AND NOT(niOlOl0Ol); + wire_ni01OOl_dataout <= wire_ni0011l_dataout AND NOT(niOO0l0ll); + wire_ni01OOlO_dataout <= wire_ni00110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01OOO_dataout <= wire_ni0011O_dataout AND NOT(niOO0l0ll); + wire_ni01OOOi_dataout <= wire_ni0011ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01OOOl_dataout <= wire_ni0011il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni01OOOO_dataout <= wire_ni0011iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i00i_dataout <= wire_ni0ilil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00iii; + wire_ni0i00l_dataout <= wire_ni0iliO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00iil; + wire_ni0i00O_dataout <= wire_ni0illi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00iiO; + wire_ni0i01i_dataout <= wire_ni0il0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00i0i; + wire_ni0i01l_dataout <= wire_ni0il0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00i0l; + wire_ni0i01O_dataout <= wire_ni0ilii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00i0O; + wire_ni0i0ii_dataout <= wire_ni0i0iO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00ili; + wire_ni0i0iii_dataout <= wire_ni0illOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0iil_dataout <= wire_ni0illOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0iiO_dataout <= wire_ni0illOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0il_dataout <= wire_ni0i0lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00ill; + wire_ni0i0ili_dataout <= wire_ni0ilO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0ill_dataout <= wire_ni0ilO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0ilO_dataout <= wire_ni0ilO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0iO_dataout <= wire_ni0illl_dataout AND NOT(niOO0li0i); + wire_ni0i0iOi_dataout <= wire_ni0ilO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0iOl_dataout <= wire_ni0ilO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0iOO_dataout <= wire_ni0ilO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0l0i_dataout <= wire_ni0ilOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0l0l_dataout <= wire_ni0ilOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0l0O_dataout <= wire_ni0ilOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0l1i_dataout <= wire_ni0ilOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0l1l_dataout <= wire_ni0ilOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0l1O_dataout <= wire_ni0ilOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0lii_dataout <= wire_ni0ilOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0lil_dataout <= wire_ni0ilOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0liO_dataout <= wire_ni0ilOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0lli_dataout <= wire_ni0iO11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0lll_dataout <= wire_ni0iilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0llO_dataout <= wire_ni0iiO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0lO_dataout <= wire_ni0illO_dataout AND NOT(niOO0li0l); + wire_ni0i0lOi_dataout <= wire_ni0iiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0lOl_dataout <= wire_ni0iiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0lOO_dataout <= wire_ni0iiO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0O0i_dataout <= wire_ni0iiOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0O0l_dataout <= wire_ni0iiOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0O0O_dataout <= wire_ni0iiOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0O1i_dataout <= wire_ni0iiO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0O1l_dataout <= wire_ni0iiO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0O1O_dataout <= wire_ni0iiOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0Oii_dataout <= wire_ni0iiOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0Oil_dataout <= wire_ni0iiOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0OiO_dataout <= wire_ni0iiOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0Oli_dataout <= wire_ni0iiOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0Oll_dataout <= wire_ni0iiOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0OlO_dataout <= wire_ni0il11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0OOi_dataout <= wire_ni0il11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0OOl_dataout <= wire_ni0il11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i0OOO_dataout <= wire_ni0il10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i10i_dataout <= wire_ni0iiil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000ii; + wire_ni0i10l_dataout <= wire_ni0iiiO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000il; + wire_ni0i10O_dataout <= wire_ni0iili_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000iO; + wire_ni0i110O_dataout <= ni0i111l AND NOT(wire_niO01lOO_dataout); + wire_ni0i11i_dataout <= wire_ni0ii0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni0000i; + wire_ni0i11ii_dataout <= ((ni0i111O AND niOlOl0OO) AND wire_w_lg_niOlOl0Ol10165w(0)) AND NOT(wire_niO01lOO_dataout); + wire_ni0i11il_dataout <= wire_ni0i11lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0i11iO_dataout <= ni0i101i AND NOT(wire_niO01lOO_dataout); + wire_ni0i11l_dataout <= wire_ni0ii0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni0000l; + wire_ni0i11lO_dataout <= wire_ni0i11Oi_dataout OR (n111i10O AND ni0i1i0l); + wire_ni0i11O_dataout <= wire_ni0iiii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni0000O; + wire_ni0i11Oi_dataout <= ni0i111O AND NOT((wire_w_lg_niOlOl0Ol10165w(0) AND niOlOl0OO)); + wire_ni0i1ii_dataout <= wire_ni0iill_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000li; + wire_ni0i1il_dataout <= wire_ni0iilO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000ll; + wire_ni0i1iO_dataout <= wire_ni0iiOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000lO; + wire_ni0i1li_dataout <= wire_ni0iiOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000Oi; + wire_ni0i1ll_dataout <= wire_ni0iiOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000Ol; + wire_ni0i1lO_dataout <= wire_ni0il1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni000OO; + wire_ni0i1Oi_dataout <= wire_ni0il1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00i1i; + wire_ni0i1Ol_dataout <= wire_ni0il1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00i1l; + wire_ni0i1OO_dataout <= wire_ni0il0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE ni00i1O; + wire_ni0ii00i_dataout <= wire_ni0il0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii00l_dataout <= wire_ni0il0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii00O_dataout <= wire_ni0il0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii01i_dataout <= wire_ni0il00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii01l_dataout <= wire_ni0il00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii01O_dataout <= wire_ni0il0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0i_dataout <= nl1OOiOO WHEN niOO0li1l = '1' ELSE wire_ni0iO1l_dataout; + wire_ni0ii0ii_dataout <= wire_ni0il0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0il_dataout <= wire_ni0il0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0iO_dataout <= wire_ni0il0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0l_dataout <= nl1OOl1i WHEN niOO0li1l = '1' ELSE wire_ni0iO1O_dataout; + wire_ni0ii0li_dataout <= wire_ni0il0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0ll_dataout <= wire_ni0il0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0lO_dataout <= wire_ni0ili1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0O_dataout <= nl1OOl1l WHEN niOO0li1l = '1' ELSE wire_ni0iO0i_dataout; + wire_ni0ii0Oi_dataout <= wire_ni0ili1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0Ol_dataout <= wire_ni0ili1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii0OO_dataout <= wire_ni0ili0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii10i_dataout <= wire_ni0il1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii10l_dataout <= wire_ni0il1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii10O_dataout <= wire_ni0il1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii11i_dataout <= wire_ni0il10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii11l_dataout <= wire_ni0il10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii11O_dataout <= wire_ni0il1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1i_dataout <= nl011l0l WHEN niOO0li1l = '1' ELSE wire_ni0ilOl_dataout; + wire_ni0ii1ii_dataout <= wire_ni0il1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1il_dataout <= wire_ni0il1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1iO_dataout <= wire_ni0il1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1l_dataout <= nl1OOiOi WHEN niOO0li1l = '1' ELSE wire_ni0ilOO_dataout; + wire_ni0ii1li_dataout <= wire_ni0il1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1ll_dataout <= wire_ni0il1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1lO_dataout <= wire_ni0il01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1O_dataout <= nl1OOiOl WHEN niOO0li1l = '1' ELSE wire_ni0iO1i_dataout; + wire_ni0ii1Oi_dataout <= wire_ni0il01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1Ol_dataout <= wire_ni0il01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0ii1OO_dataout <= wire_ni0il00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iii0i_dataout <= wire_ni0iliil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iii0l_dataout <= wire_ni0iliiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iii0O_dataout <= wire_ni0ilili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iii1i_dataout <= wire_ni0ili0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iii1l_dataout <= wire_ni0ili0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iii1O_dataout <= wire_ni0iliii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiii_dataout <= nl1OOl1O WHEN niOO0li1l = '1' ELSE wire_ni0iO0l_dataout; + wire_ni0iiiii_dataout <= wire_ni0ilill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiiil_dataout <= wire_ni0ililO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiiiO_dataout <= wire_ni0iliOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiil_dataout <= nl1OOl0i WHEN niOO0li1l = '1' ELSE wire_ni0iO0O_dataout; + wire_ni0iiili_dataout <= wire_ni0iliOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiill_dataout <= wire_ni0iliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiilO_dataout <= wire_ni0ill1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiiO_dataout <= nl1OOl0l WHEN niOO0li1l = '1' ELSE wire_ni0iOii_dataout; + wire_ni0iiiOi_dataout <= wire_ni0ill1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiiOl_dataout <= wire_ni0ill1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiiOO_dataout <= wire_ni0ill0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iil0i_dataout <= wire_ni0illil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iil0l_dataout <= wire_ni0illiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iil0O_dataout <= wire_ni0illli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iil1i_dataout <= wire_ni0ill0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iil1l_dataout <= wire_ni0ill0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iil1O_dataout <= wire_ni0illii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iili_dataout <= nl1OOl0O WHEN niOO0li1l = '1' ELSE wire_ni0iOil_dataout; + wire_ni0iilii_dataout <= wire_ni0illll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iilil_dataout <= wire_ni0illlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iiliO_dataout <= wire_ni0iillO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iill_dataout <= nl1OOlii WHEN niOO0li1l = '1' ELSE wire_ni0iOiO_dataout; + wire_ni0iilli_dataout <= wire_ni0iilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iilll_dataout <= wire_ni0iilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni0iillO_dataout <= wire_ni0liOOl_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l101O_dataout; + wire_ni0iilO_dataout <= nl1OOlil WHEN niOO0li1l = '1' ELSE wire_ni0iOli_dataout; + wire_ni0iilOi_dataout <= wire_ni0liOOO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l100i_dataout; + wire_ni0iilOl_dataout <= wire_ni0ll11i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l100l_dataout; + wire_ni0iilOO_dataout <= wire_ni0ll11l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l100O_dataout; + wire_ni0iiO0i_dataout <= wire_ni0ll10O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0iO_dataout; + wire_ni0iiO0l_dataout <= wire_ni0ll1ii_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0li_dataout; + wire_ni0iiO0O_dataout <= wire_ni0ll1il_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0ll_dataout; + wire_ni0iiO1i_dataout <= wire_ni0ll11O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO00O_dataout; + wire_ni0iiO1l_dataout <= wire_ni0ll10i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0ii_dataout; + wire_ni0iiO1O_dataout <= wire_ni0ll10l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0il_dataout; + wire_ni0iiOi_dataout <= nl1OOliO WHEN niOO0li1l = '1' ELSE wire_ni0iOll_dataout; + wire_ni0iiOii_dataout <= wire_ni0ll1iO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0lO_dataout; + wire_ni0iiOil_dataout <= wire_ni0ll1li_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0Oi_dataout; + wire_ni0iiOiO_dataout <= wire_ni0ll1ll_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0Ol_dataout; + wire_ni0iiOl_dataout <= nl1OOlli WHEN niOO0li1l = '1' ELSE wire_ni0iOlO_dataout; + wire_ni0iiOli_dataout <= wire_ni0ll1lO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iO0OO_dataout; + wire_ni0iiOll_dataout <= wire_ni0ll1Oi_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOi1i_dataout; + wire_ni0iiOlO_dataout <= wire_ni0ll1Ol_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOi1l_dataout; + wire_ni0iiOO_dataout <= nl1OOlll WHEN niOO0li1l = '1' ELSE wire_ni0iOOi_dataout; + wire_ni0iiOOi_dataout <= wire_ni0ll1OO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOi1O_dataout; + wire_ni0iiOOl_dataout <= wire_ni0ll01i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOi0i_dataout; + wire_ni0iiOOO_dataout <= wire_ni0ll01l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOi0l_dataout; + wire_ni0il00i_dataout <= wire_ni0lli0O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOliO_dataout; + wire_ni0il00l_dataout <= wire_ni0lliii_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOlli_dataout; + wire_ni0il00O_dataout <= wire_ni0lliil_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOlll_dataout; + wire_ni0il01i_dataout <= wire_ni0lli1O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOl0O_dataout; + wire_ni0il01l_dataout <= wire_ni0lli0i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOlii_dataout; + wire_ni0il01O_dataout <= wire_ni0lli0l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOlil_dataout; + wire_ni0il0i_dataout <= nl1OOlOO WHEN niOO0li1l = '1' ELSE wire_ni0l11l_dataout; + wire_ni0il0ii_dataout <= wire_ni0lliiO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOllO_dataout; + wire_ni0il0il_dataout <= wire_ni0llili_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOlOi_dataout; + wire_ni0il0iO_dataout <= wire_ni0llill_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOlOl_dataout; + wire_ni0il0l_dataout <= nl1OOO1i WHEN niOO0li1l = '1' ELSE wire_ni0l11O_dataout; + wire_ni0il0li_dataout <= wire_ni0llilO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOlOO_dataout; + wire_ni0il0ll_dataout <= wire_ni0lliOi_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOO1i_dataout; + wire_ni0il0lO_dataout <= wire_ni0lliOl_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOO1l_dataout; + wire_ni0il0O_dataout <= nl1OOO1l WHEN niOO0li1l = '1' ELSE wire_ni0l10i_dataout; + wire_ni0il0Oi_dataout <= wire_ni0lliOO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOO1O_dataout; + wire_ni0il0Ol_dataout <= wire_ni0lll1i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOO0i_dataout; + wire_ni0il0OO_dataout <= wire_ni0lll1l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOO0l_dataout; + wire_ni0il10i_dataout <= wire_ni0ll00O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOiiO_dataout; + wire_ni0il10l_dataout <= wire_ni0ll0ii_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOili_dataout; + wire_ni0il10O_dataout <= wire_ni0ll0il_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOill_dataout; + wire_ni0il11i_dataout <= wire_ni0ll01O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOi0O_dataout; + wire_ni0il11l_dataout <= wire_ni0ll00i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOiii_dataout; + wire_ni0il11O_dataout <= wire_ni0ll00l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOiil_dataout; + wire_ni0il1i_dataout <= nl1OOllO WHEN niOO0li1l = '1' ELSE wire_ni0iOOl_dataout; + wire_ni0il1ii_dataout <= wire_ni0ll0iO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOilO_dataout; + wire_ni0il1il_dataout <= wire_ni0ll0li_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOiOi_dataout; + wire_ni0il1iO_dataout <= wire_ni0ll0ll_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOiOl_dataout; + wire_ni0il1l_dataout <= nl1OOlOi WHEN niOO0li1l = '1' ELSE wire_ni0iOOO_dataout; + wire_ni0il1li_dataout <= wire_ni0ll0lO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOiOO_dataout; + wire_ni0il1ll_dataout <= wire_ni0ll0Oi_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOl1i_dataout; + wire_ni0il1lO_dataout <= wire_ni0ll0Ol_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOl1l_dataout; + wire_ni0il1O_dataout <= nl1OOlOl WHEN niOO0li1l = '1' ELSE wire_ni0l11i_dataout; + wire_ni0il1Oi_dataout <= wire_ni0ll0OO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOl1O_dataout; + wire_ni0il1Ol_dataout <= wire_ni0lli1i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOl0i_dataout; + wire_ni0il1OO_dataout <= wire_ni0lli1l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOl0l_dataout; + wire_ni0ili0i_dataout <= wire_ni0lll0O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOiO_dataout; + wire_ni0ili0l_dataout <= wire_ni0lllii_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOli_dataout; + wire_ni0ili0O_dataout <= wire_ni0lllil_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOll_dataout; + wire_ni0ili1i_dataout <= wire_ni0lll1O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOO0O_dataout; + wire_ni0ili1l_dataout <= wire_ni0lll0i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOii_dataout; + wire_ni0ili1O_dataout <= wire_ni0lll0l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOil_dataout; + wire_ni0ilii_dataout <= nl1OOO1O WHEN niOO0li1l = '1' ELSE wire_ni0l10l_dataout; + wire_ni0iliii_dataout <= wire_ni0llliO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOlO_dataout; + wire_ni0iliil_dataout <= wire_ni0lllli_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOOi_dataout; + wire_ni0iliiO_dataout <= wire_ni0lllll_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOOl_dataout; + wire_ni0ilil_dataout <= nl1OOO0i WHEN niOO0li1l = '1' ELSE wire_ni0l10O_dataout; + wire_ni0ilili_dataout <= wire_ni0llllO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0iOOOO_dataout; + wire_ni0ilill_dataout <= wire_ni0lllOi_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l111i_dataout; + wire_ni0ililO_dataout <= wire_ni0lllOl_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l111l_dataout; + wire_ni0iliO_dataout <= nl1OOO0l WHEN niOO0li1l = '1' ELSE wire_ni0l1ii_dataout; + wire_ni0iliOi_dataout <= wire_ni0lllOO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l111O_dataout; + wire_ni0iliOl_dataout <= wire_ni0llO1i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l110i_dataout; + wire_ni0iliOO_dataout <= wire_ni0llO1l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l110l_dataout; + wire_ni0ill0i_dataout <= wire_ni0llO0O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11iO_dataout; + wire_ni0ill0l_dataout <= wire_ni0llOii_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11li_dataout; + wire_ni0ill0O_dataout <= wire_ni0llOil_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11ll_dataout; + wire_ni0ill1i_dataout <= wire_ni0llO1O_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l110O_dataout; + wire_ni0ill1l_dataout <= wire_ni0llO0i_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11ii_dataout; + wire_ni0ill1O_dataout <= wire_ni0llO0l_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11il_dataout; + wire_ni0illi_dataout <= nl1OOO0O WHEN niOO0li1l = '1' ELSE wire_ni0l1il_dataout; + wire_ni0illii_dataout <= wire_ni0llOiO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11lO_dataout; + wire_ni0illil_dataout <= wire_ni0llOli_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11Oi_dataout; + wire_ni0illiO_dataout <= wire_ni0llOll_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11Ol_dataout; + wire_ni0illl_dataout <= nl1OOOii WHEN niOO0li1l = '1' ELSE wire_ni0l1iO_dataout; + wire_ni0illli_dataout <= wire_ni0llOlO_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l11OO_dataout; + wire_ni0illll_dataout <= wire_ni0llOOi_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l101i_dataout; + wire_ni0illlO_dataout <= wire_ni0llOOl_dataout WHEN niOlOl0Ol = '1' ELSE wire_ni0l101l_dataout; + wire_ni0illO_dataout <= wire_ni0l1li_dataout AND NOT(niOO0li1l); + wire_ni0illOi_dataout <= ni11OOOi WHEN niOlOl0Ol = '1' ELSE wire_ni0iO11l_dataout; + wire_ni0illOl_dataout <= ni11100O WHEN niOlOl0Ol = '1' ELSE wire_ni0iO11O_dataout; + wire_ni0illOO_dataout <= ni11Oi0i WHEN niOlOl0Ol = '1' ELSE wire_ni0iO10i_dataout; + wire_ni0ilO0i_dataout <= ni11OOiO WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1il_dataout; + wire_ni0ilO0l_dataout <= ni11OOli WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1iO_dataout; + wire_ni0ilO0O_dataout <= ni11OOll WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1li_dataout; + wire_ni0ilO1i_dataout <= ni11OO0O WHEN niOlOl0Ol = '1' ELSE wire_ni0iO10l_dataout; + wire_ni0ilO1l_dataout <= ni11OOii WHEN niOlOl0Ol = '1' ELSE wire_ni0iO10O_dataout; + wire_ni0ilO1O_dataout <= ni11OOil WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1ii_dataout; + wire_ni0ilOii_dataout <= ni11OOlO WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1ll_dataout; + wire_ni0ilOil_dataout <= n0OOOllO WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1lO_dataout; + wire_ni0ilOiO_dataout <= ni1111Ol WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1Oi_dataout; + wire_ni0ilOl_dataout <= nl011l0l WHEN niOO0li1O = '1' ELSE ni001OO; + wire_ni0ilOli_dataout <= ni1111OO WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1Ol_dataout; + wire_ni0ilOll_dataout <= ni11101i WHEN niOlOl0Ol = '1' ELSE wire_ni0iO1OO_dataout; + wire_ni0ilOlO_dataout <= ni11101l WHEN niOlOl0Ol = '1' ELSE wire_ni0iO01i_dataout; + wire_ni0ilOO_dataout <= nl1OOiOi WHEN niOO0li1O = '1' ELSE ni0001i; + wire_ni0ilOOi_dataout <= ni11101O WHEN niOlOl0Ol = '1' ELSE wire_ni0iO01l_dataout; + wire_ni0ilOOl_dataout <= ni11100i WHEN niOlOl0Ol = '1' ELSE wire_ni0iO01O_dataout; + wire_ni0ilOOO_dataout <= ni11100l WHEN niOlOl0Ol = '1' ELSE wire_ni0iO00i_dataout; + wire_ni0iO00i_dataout <= ni0i1i1O WHEN niOlOl0Oi = '1' ELSE wire_ni0l1iiO_dataout; + wire_ni0iO00l_dataout <= ni0i1i0i WHEN niOlOl0Oi = '1' ELSE wire_ni0l1ili_dataout; + wire_ni0iO00O_dataout <= ni0i1i0O WHEN niOlOl0Oi = '1' ELSE wire_ni0l1ill_dataout; + wire_ni0iO01i_dataout <= ni0i10OO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1i0O_dataout; + wire_ni0iO01l_dataout <= ni0i1i1i WHEN niOlOl0Oi = '1' ELSE wire_ni0l1iii_dataout; + wire_ni0iO01O_dataout <= ni0i1i1l WHEN niOlOl0Oi = '1' ELSE wire_ni0l1iil_dataout; + wire_ni0iO0i_dataout <= nl1OOl1l WHEN niOO0li1O = '1' ELSE ni0000l; + wire_ni0iO0ii_dataout <= ni0i1iii WHEN niOlOl0Oi = '1' ELSE wire_ni0l1ilO_dataout; + wire_ni0iO0il_dataout <= ni0i1iil WHEN niOlOl0Oi = '1' ELSE wire_ni0l1iOi_dataout; + wire_ni0iO0iO_dataout <= ni0i1iiO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1iOl_dataout; + wire_ni0iO0l_dataout <= nl1OOl1O WHEN niOO0li1O = '1' ELSE ni0000O; + wire_ni0iO0li_dataout <= ni0i1ili WHEN niOlOl0Oi = '1' ELSE wire_ni0l1iOO_dataout; + wire_ni0iO0ll_dataout <= ni0i1ill WHEN niOlOl0Oi = '1' ELSE wire_ni0l1l1i_dataout; + wire_ni0iO0lO_dataout <= ni0i1ilO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1l1l_dataout; + wire_ni0iO0O_dataout <= nl1OOl0i WHEN niOO0li1O = '1' ELSE ni000ii; + wire_ni0iO0Oi_dataout <= ni0i1iOi WHEN niOlOl0Oi = '1' ELSE wire_ni0l1l1O_dataout; + wire_ni0iO0Ol_dataout <= ni0i1iOl WHEN niOlOl0Oi = '1' ELSE wire_ni0l1l0i_dataout; + wire_ni0iO0OO_dataout <= ni0i1iOO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1l0l_dataout; + wire_ni0iO10i_dataout <= ni0i101O WHEN niOlOl0Oi = '1' ELSE wire_ni0l10iO_dataout; + wire_ni0iO10l_dataout <= ni0i100i WHEN niOlOl0Oi = '1' ELSE wire_ni0l10li_dataout; + wire_ni0iO10O_dataout <= ni0i100l WHEN niOlOl0Oi = '1' ELSE wire_ni0l10ll_dataout; + wire_ni0iO11i_dataout <= niOlOll0O WHEN niOlOl0Ol = '1' ELSE wire_ni0iO00l_dataout; + wire_ni0iO11l_dataout <= ni0i110l WHEN niOlOl0Oi = '1' ELSE wire_ni0l10ii_dataout; + wire_ni0iO11O_dataout <= ni0i101l WHEN niOlOl0Oi = '1' ELSE wire_ni0l10il_dataout; + wire_ni0iO1i_dataout <= nl1OOiOl WHEN niOO0li1O = '1' ELSE ni0001l; + wire_ni0iO1ii_dataout <= ni0i100O WHEN niOlOl0Oi = '1' ELSE wire_ni0l10lO_dataout; + wire_ni0iO1il_dataout <= ni0i10ii WHEN niOlOl0Oi = '1' ELSE wire_ni0l10Oi_dataout; + wire_ni0iO1iO_dataout <= ni0i10il WHEN niOlOl0Oi = '1' ELSE wire_ni0l10Ol_dataout; + wire_ni0iO1l_dataout <= nl1OOiOO WHEN niOO0li1O = '1' ELSE ni0001O; + wire_ni0iO1li_dataout <= ni0i10iO WHEN niOlOl0Oi = '1' ELSE wire_ni0l10OO_dataout; + wire_ni0iO1ll_dataout <= ni0i10li WHEN niOlOl0Oi = '1' ELSE wire_ni0l1i1i_dataout; + wire_ni0iO1lO_dataout <= ni0i10ll WHEN niOlOl0Oi = '1' ELSE wire_ni0l1i1l_dataout; + wire_ni0iO1O_dataout <= nl1OOl1i WHEN niOO0li1O = '1' ELSE ni0000i; + wire_ni0iO1Oi_dataout <= ni0i10lO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1i1O_dataout; + wire_ni0iO1Ol_dataout <= ni0i10Oi WHEN niOlOl0Oi = '1' ELSE wire_ni0l1i0i_dataout; + wire_ni0iO1OO_dataout <= ni0i10Ol WHEN niOlOl0Oi = '1' ELSE wire_ni0l1i0l_dataout; + wire_ni0iOi0i_dataout <= ni0i1l0i WHEN niOlOl0Oi = '1' ELSE wire_ni0l1liO_dataout; + wire_ni0iOi0l_dataout <= ni0i1l0l WHEN niOlOl0Oi = '1' ELSE wire_ni0l1lli_dataout; + wire_ni0iOi0O_dataout <= ni0i1l0O WHEN niOlOl0Oi = '1' ELSE wire_ni0l1lll_dataout; + wire_ni0iOi1i_dataout <= ni0i1l1i WHEN niOlOl0Oi = '1' ELSE wire_ni0l1l0O_dataout; + wire_ni0iOi1l_dataout <= ni0i1l1l WHEN niOlOl0Oi = '1' ELSE wire_ni0l1lii_dataout; + wire_ni0iOi1O_dataout <= ni0i1l1O WHEN niOlOl0Oi = '1' ELSE wire_ni0l1lil_dataout; + wire_ni0iOii_dataout <= nl1OOl0l WHEN niOO0li1O = '1' ELSE ni000il; + wire_ni0iOiii_dataout <= ni0i1lii WHEN niOlOl0Oi = '1' ELSE wire_ni0l1llO_dataout; + wire_ni0iOiil_dataout <= ni0i1lil WHEN niOlOl0Oi = '1' ELSE wire_ni0l1lOi_dataout; + wire_ni0iOiiO_dataout <= ni0i1liO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1lOl_dataout; + wire_ni0iOil_dataout <= nl1OOl0O WHEN niOO0li1O = '1' ELSE ni000iO; + wire_ni0iOili_dataout <= ni0i1lli WHEN niOlOl0Oi = '1' ELSE wire_ni0l1lOO_dataout; + wire_ni0iOill_dataout <= ni0i1lll WHEN niOlOl0Oi = '1' ELSE wire_ni0l1O1i_dataout; + wire_ni0iOilO_dataout <= ni0i1llO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1O1l_dataout; + wire_ni0iOiO_dataout <= nl1OOlii WHEN niOO0li1O = '1' ELSE ni000li; + wire_ni0iOiOi_dataout <= ni0i1lOi WHEN niOlOl0Oi = '1' ELSE wire_ni0l1O1O_dataout; + wire_ni0iOiOl_dataout <= ni0i1lOl WHEN niOlOl0Oi = '1' ELSE wire_ni0l1O0i_dataout; + wire_ni0iOiOO_dataout <= ni0i1lOO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1O0l_dataout; + wire_ni0iOl0i_dataout <= ni0i1O0i WHEN niOlOl0Oi = '1' ELSE wire_ni0l1OiO_dataout; + wire_ni0iOl0l_dataout <= ni0i1O0l WHEN niOlOl0Oi = '1' ELSE wire_ni0l1Oli_dataout; + wire_ni0iOl0O_dataout <= ni0i1O0O WHEN niOlOl0Oi = '1' ELSE wire_ni0l1Oll_dataout; + wire_ni0iOl1i_dataout <= ni0i1O1i WHEN niOlOl0Oi = '1' ELSE wire_ni0l1O0O_dataout; + wire_ni0iOl1l_dataout <= ni0i1O1l WHEN niOlOl0Oi = '1' ELSE wire_ni0l1Oii_dataout; + wire_ni0iOl1O_dataout <= ni0i1O1O WHEN niOlOl0Oi = '1' ELSE wire_ni0l1Oil_dataout; + wire_ni0iOli_dataout <= nl1OOlil WHEN niOO0li1O = '1' ELSE ni000ll; + wire_ni0iOlii_dataout <= ni0i1Oii WHEN niOlOl0Oi = '1' ELSE wire_ni0l1OlO_dataout; + wire_ni0iOlil_dataout <= ni0i1Oil WHEN niOlOl0Oi = '1' ELSE wire_ni0l1OOi_dataout; + wire_ni0iOliO_dataout <= ni0i1OiO WHEN niOlOl0Oi = '1' ELSE wire_ni0l1OOl_dataout; + wire_ni0iOll_dataout <= nl1OOliO WHEN niOO0li1O = '1' ELSE ni000lO; + wire_ni0iOlli_dataout <= ni0i1Oli WHEN niOlOl0Oi = '1' ELSE wire_ni0l1OOO_dataout; + wire_ni0iOlll_dataout <= ni0i1Oll WHEN niOlOl0Oi = '1' ELSE wire_ni0l011i_dataout; + wire_ni0iOllO_dataout <= ni0i1OlO WHEN niOlOl0Oi = '1' ELSE wire_ni0l011l_dataout; + wire_ni0iOlO_dataout <= nl1OOlli WHEN niOO0li1O = '1' ELSE ni000Oi; + wire_ni0iOlOi_dataout <= ni0i1OOi WHEN niOlOl0Oi = '1' ELSE wire_ni0l011O_dataout; + wire_ni0iOlOl_dataout <= ni0i1OOl WHEN niOlOl0Oi = '1' ELSE wire_ni0l010i_dataout; + wire_ni0iOlOO_dataout <= ni0i1OOO WHEN niOlOl0Oi = '1' ELSE wire_ni0l010l_dataout; + wire_ni0iOO0i_dataout <= ni0i010i WHEN niOlOl0Oi = '1' ELSE wire_ni0l01iO_dataout; + wire_ni0iOO0l_dataout <= ni0i010l WHEN niOlOl0Oi = '1' ELSE wire_ni0l01li_dataout; + wire_ni0iOO0O_dataout <= ni0i010O WHEN niOlOl0Oi = '1' ELSE wire_ni0l01ll_dataout; + wire_ni0iOO1i_dataout <= ni0i011i WHEN niOlOl0Oi = '1' ELSE wire_ni0l010O_dataout; + wire_ni0iOO1l_dataout <= ni0i011l WHEN niOlOl0Oi = '1' ELSE wire_ni0l01ii_dataout; + wire_ni0iOO1O_dataout <= ni0i011O WHEN niOlOl0Oi = '1' ELSE wire_ni0l01il_dataout; + wire_ni0iOOi_dataout <= nl1OOlll WHEN niOO0li1O = '1' ELSE ni000Ol; + wire_ni0iOOii_dataout <= ni0i01ii WHEN niOlOl0Oi = '1' ELSE wire_ni0l01lO_dataout; + wire_ni0iOOil_dataout <= ni0i01il WHEN niOlOl0Oi = '1' ELSE wire_ni0l01Oi_dataout; + wire_ni0iOOiO_dataout <= ni0i01iO WHEN niOlOl0Oi = '1' ELSE wire_ni0l01Ol_dataout; + wire_ni0iOOl_dataout <= nl1OOllO WHEN niOO0li1O = '1' ELSE ni000OO; + wire_ni0iOOli_dataout <= ni0i01li WHEN niOlOl0Oi = '1' ELSE wire_ni0l01OO_dataout; + wire_ni0iOOll_dataout <= ni0i01ll WHEN niOlOl0Oi = '1' ELSE wire_ni0l001i_dataout; + wire_ni0iOOlO_dataout <= ni0i01lO WHEN niOlOl0Oi = '1' ELSE wire_ni0l001l_dataout; + wire_ni0iOOO_dataout <= nl1OOlOi WHEN niOO0li1O = '1' ELSE ni00i1i; + wire_ni0iOOOi_dataout <= ni0i01Oi WHEN niOlOl0Oi = '1' ELSE wire_ni0l001O_dataout; + wire_ni0iOOOl_dataout <= ni0i01Ol WHEN niOlOl0Oi = '1' ELSE wire_ni0l000i_dataout; + wire_ni0iOOOO_dataout <= ni0i01OO WHEN niOlOl0Oi = '1' ELSE wire_ni0l000l_dataout; + wire_ni0l000i_dataout <= ni0i01Ol WHEN niOlOl0ll = '1' ELSE wire_ni0liiiO_dataout; + wire_ni0l000l_dataout <= ni0i01OO WHEN niOlOl0ll = '1' ELSE wire_ni0liili_dataout; + wire_ni0l000O_dataout <= ni0i001i WHEN niOlOl0ll = '1' ELSE wire_ni0liill_dataout; + wire_ni0l001i_dataout <= ni0i01ll WHEN niOlOl0ll = '1' ELSE wire_ni0lii0O_dataout; + wire_ni0l001l_dataout <= ni0i01lO WHEN niOlOl0ll = '1' ELSE wire_ni0liiii_dataout; + wire_ni0l001O_dataout <= ni0i01Oi WHEN niOlOl0ll = '1' ELSE wire_ni0liiil_dataout; + wire_ni0l00ii_dataout <= ni0i001l WHEN niOlOl0ll = '1' ELSE wire_ni0liilO_dataout; + wire_ni0l00il_dataout <= ni0i001O WHEN niOlOl0ll = '1' ELSE wire_ni0liiOi_dataout; + wire_ni0l00iO_dataout <= ni0i000i WHEN niOlOl0ll = '1' ELSE wire_ni0liiOl_dataout; + wire_ni0l00li_dataout <= ni0i000l WHEN niOlOl0ll = '1' ELSE wire_ni0liiOO_dataout; + wire_ni0l00ll_dataout <= ni0i000O WHEN niOlOl0ll = '1' ELSE wire_ni0lil1i_dataout; + wire_ni0l00lO_dataout <= ni0i00ii WHEN niOlOl0ll = '1' ELSE wire_ni0lil1l_dataout; + wire_ni0l00Oi_dataout <= ni0i00il WHEN niOlOl0ll = '1' ELSE wire_ni0lil1O_dataout; + wire_ni0l00Ol_dataout <= ni0i00iO WHEN niOlOl0ll = '1' ELSE wire_ni0lil0i_dataout; + wire_ni0l00OO_dataout <= ni0i00li WHEN niOlOl0ll = '1' ELSE wire_ni0lil0l_dataout; + wire_ni0l010i_dataout <= ni0i1OOl WHEN niOlOl0ll = '1' ELSE wire_ni0li0iO_dataout; + wire_ni0l010l_dataout <= ni0i1OOO WHEN niOlOl0ll = '1' ELSE wire_ni0li0li_dataout; + wire_ni0l010O_dataout <= ni0i011i WHEN niOlOl0ll = '1' ELSE wire_ni0li0ll_dataout; + wire_ni0l011i_dataout <= ni0i1Oll WHEN niOlOl0ll = '1' ELSE wire_ni0li00O_dataout; + wire_ni0l011l_dataout <= ni0i1OlO WHEN niOlOl0ll = '1' ELSE wire_ni0li0ii_dataout; + wire_ni0l011O_dataout <= ni0i1OOi WHEN niOlOl0ll = '1' ELSE wire_ni0li0il_dataout; + wire_ni0l01i_dataout <= ni001Ol AND NOT(niOO0li0l); + wire_ni0l01ii_dataout <= ni0i011l WHEN niOlOl0ll = '1' ELSE wire_ni0li0lO_dataout; + wire_ni0l01il_dataout <= ni0i011O WHEN niOlOl0ll = '1' ELSE wire_ni0li0Oi_dataout; + wire_ni0l01iO_dataout <= ni0i010i WHEN niOlOl0ll = '1' ELSE wire_ni0li0Ol_dataout; + wire_ni0l01li_dataout <= ni0i010l WHEN niOlOl0ll = '1' ELSE wire_ni0li0OO_dataout; + wire_ni0l01ll_dataout <= ni0i010O WHEN niOlOl0ll = '1' ELSE wire_ni0lii1i_dataout; + wire_ni0l01lO_dataout <= ni0i01ii WHEN niOlOl0ll = '1' ELSE wire_ni0lii1l_dataout; + wire_ni0l01O_dataout <= wire_nlOi1Oi0O_dataout AND ni0l0ii; + wire_ni0l01Oi_dataout <= ni0i01il WHEN niOlOl0ll = '1' ELSE wire_ni0lii1O_dataout; + wire_ni0l01Ol_dataout <= ni0i01iO WHEN niOlOl0ll = '1' ELSE wire_ni0lii0i_dataout; + wire_ni0l01OO_dataout <= ni0i01li WHEN niOlOl0ll = '1' ELSE wire_ni0lii0l_dataout; + wire_ni0l0i0i_dataout <= ni0i00Ol WHEN niOlOl0ll = '1' ELSE wire_ni0liliO_dataout; + wire_ni0l0i0l_dataout <= ni0i00OO WHEN niOlOl0ll = '1' ELSE wire_ni0lilli_dataout; + wire_ni0l0i0O_dataout <= ni0i0i1i WHEN niOlOl0ll = '1' ELSE wire_ni0lilll_dataout; + wire_ni0l0i1i_dataout <= ni0i00ll WHEN niOlOl0ll = '1' ELSE wire_ni0lil0O_dataout; + wire_ni0l0i1l_dataout <= ni0i00lO WHEN niOlOl0ll = '1' ELSE wire_ni0lilii_dataout; + wire_ni0l0i1O_dataout <= ni0i00Oi WHEN niOlOl0ll = '1' ELSE wire_ni0lilil_dataout; + wire_ni0l0iii_dataout <= ni0i0i1l WHEN niOlOl0ll = '1' ELSE wire_ni0lillO_dataout; + wire_ni0l0iil_dataout <= wire_ni0lilOi_dataout AND NOT(niOlOl0ll); + wire_ni0l0iiO_dataout <= wire_ni0lilOl_dataout AND NOT(niOlOl0ll); + wire_ni0l0ili_dataout <= wire_ni0lilOO_dataout AND NOT(niOlOl0ll); + wire_ni0l0ill_dataout <= ni0i111l OR niOlOl0ll; + wire_ni0l0ilO_dataout <= ni0i110l AND NOT(ni0i111l); + wire_ni0l0iO_dataout <= nl1O10iO AND NOT(wire_niO01O0O_dataout); + wire_ni0l0iOi_dataout <= ni0i101l AND NOT(ni0i111l); + wire_ni0l0iOl_dataout <= ni0i101O AND NOT(ni0i111l); + wire_ni0l0iOO_dataout <= ni0i100i AND NOT(ni0i111l); + wire_ni0l0l0i_dataout <= ni0i10il AND NOT(ni0i111l); + wire_ni0l0l0l_dataout <= ni0i10iO AND NOT(ni0i111l); + wire_ni0l0l0O_dataout <= ni0i10li AND NOT(ni0i111l); + wire_ni0l0l1i_dataout <= ni0i100l AND NOT(ni0i111l); + wire_ni0l0l1l_dataout <= ni0i100O AND NOT(ni0i111l); + wire_ni0l0l1O_dataout <= ni0i10ii AND NOT(ni0i111l); + wire_ni0l0li_dataout <= nl1O1i0l AND NOT(wire_niO01O0O_dataout); + wire_ni0l0lii_dataout <= ni0i10ll AND NOT(ni0i111l); + wire_ni0l0lil_dataout <= ni0i10lO AND NOT(ni0i111l); + wire_ni0l0liO_dataout <= ni0i10Oi AND NOT(ni0i111l); + wire_ni0l0ll_dataout <= nl1O10ii AND NOT(wire_niO01O0O_dataout); + wire_ni0l0lli_dataout <= ni0i10Ol AND NOT(ni0i111l); + wire_ni0l0lll_dataout <= ni0i10OO AND NOT(ni0i111l); + wire_ni0l0llO_dataout <= ni0i1i1i AND NOT(ni0i111l); + wire_ni0l0lO_dataout <= nl1O10il AND NOT(wire_niO01O0O_dataout); + wire_ni0l0lOi_dataout <= ni0i1i1l AND NOT(ni0i111l); + wire_ni0l0lOl_dataout <= ni0i1i1O AND NOT(ni0i111l); + wire_ni0l0lOO_dataout <= ni0i1i0i AND NOT(ni0i111l); + wire_ni0l0O0i_dataout <= ni0i1iiO AND NOT(ni0i111l); + wire_ni0l0O0l_dataout <= ni0i1ili AND NOT(ni0i111l); + wire_ni0l0O0O_dataout <= ni0i1ill AND NOT(ni0i111l); + wire_ni0l0O1i_dataout <= ni0i1i0O AND NOT(ni0i111l); + wire_ni0l0O1l_dataout <= ni0i1iii AND NOT(ni0i111l); + wire_ni0l0O1O_dataout <= ni0i1iil AND NOT(ni0i111l); + wire_ni0l0Oi_dataout <= wire_ni0l0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0l0Oii_dataout <= ni0i1ilO AND NOT(ni0i111l); + wire_ni0l0Oil_dataout <= ni0i1iOi AND NOT(ni0i111l); + wire_ni0l0OiO_dataout <= ni0i1iOl AND NOT(ni0i111l); + wire_ni0l0Ol_dataout <= wire_ni0l0OO_dataout AND NOT(wire_nlOi1Oi0O_dataout); + wire_ni0l0Oli_dataout <= ni0i1iOO AND NOT(ni0i111l); + wire_ni0l0Oll_dataout <= ni0i1l1i AND NOT(ni0i111l); + wire_ni0l0OlO_dataout <= ni0i1l1l AND NOT(ni0i111l); + wire_ni0l0OO_dataout <= ni0l0ii OR (wire_nl1000i_w_lg_ni00ilO2338w(0) AND nl1O10iO); + wire_ni0l0OOi_dataout <= ni0i1l1O AND NOT(ni0i111l); + wire_ni0l0OOl_dataout <= ni0i1l0i AND NOT(ni0i111l); + wire_ni0l0OOO_dataout <= ni0i1l0l AND NOT(ni0i111l); + wire_ni0l100i_dataout <= ni0i0i0i WHEN niOlOl0Oi = '1' ELSE wire_ni0l0iiO_dataout; + wire_ni0l100l_dataout <= ni0i0i0l WHEN niOlOl0Oi = '1' ELSE wire_ni0l0ili_dataout; + wire_ni0l100O_dataout <= wire_ni0l0ill_dataout OR niOlOl0Oi; + wire_ni0l101i_dataout <= ni0i0i1i WHEN niOlOl0Oi = '1' ELSE wire_ni0l0i0O_dataout; + wire_ni0l101l_dataout <= ni0i0i1l WHEN niOlOl0Oi = '1' ELSE wire_ni0l0iii_dataout; + wire_ni0l101O_dataout <= ni0i0i1O WHEN niOlOl0Oi = '1' ELSE wire_ni0l0iil_dataout; + wire_ni0l10i_dataout <= nl1OOO1l WHEN niOO0li1O = '1' ELSE ni00i0l; + wire_ni0l10ii_dataout <= ni0i110l WHEN niOlOl0ll = '1' ELSE wire_ni0l0ilO_dataout; + wire_ni0l10il_dataout <= ni0i101l WHEN niOlOl0ll = '1' ELSE wire_ni0l0iOi_dataout; + wire_ni0l10iO_dataout <= ni0i101O WHEN niOlOl0ll = '1' ELSE wire_ni0l0iOl_dataout; + wire_ni0l10l_dataout <= nl1OOO1O WHEN niOO0li1O = '1' ELSE ni00i0O; + wire_ni0l10li_dataout <= ni0i100i WHEN niOlOl0ll = '1' ELSE wire_ni0l0iOO_dataout; + wire_ni0l10ll_dataout <= ni0i100l WHEN niOlOl0ll = '1' ELSE wire_ni0l0l1i_dataout; + wire_ni0l10lO_dataout <= ni0i100O WHEN niOlOl0ll = '1' ELSE wire_ni0l0l1l_dataout; + wire_ni0l10O_dataout <= nl1OOO0i WHEN niOO0li1O = '1' ELSE ni00iii; + wire_ni0l10Oi_dataout <= ni0i10ii WHEN niOlOl0ll = '1' ELSE wire_ni0l0l1O_dataout; + wire_ni0l10Ol_dataout <= ni0i10il WHEN niOlOl0ll = '1' ELSE wire_ni0l0l0i_dataout; + wire_ni0l10OO_dataout <= ni0i10iO WHEN niOlOl0ll = '1' ELSE wire_ni0l0l0l_dataout; + wire_ni0l110i_dataout <= ni0i000i WHEN niOlOl0Oi = '1' ELSE wire_ni0l00iO_dataout; + wire_ni0l110l_dataout <= ni0i000l WHEN niOlOl0Oi = '1' ELSE wire_ni0l00li_dataout; + wire_ni0l110O_dataout <= ni0i000O WHEN niOlOl0Oi = '1' ELSE wire_ni0l00ll_dataout; + wire_ni0l111i_dataout <= ni0i001i WHEN niOlOl0Oi = '1' ELSE wire_ni0l000O_dataout; + wire_ni0l111l_dataout <= ni0i001l WHEN niOlOl0Oi = '1' ELSE wire_ni0l00ii_dataout; + wire_ni0l111O_dataout <= ni0i001O WHEN niOlOl0Oi = '1' ELSE wire_ni0l00il_dataout; + wire_ni0l11i_dataout <= nl1OOlOl WHEN niOO0li1O = '1' ELSE ni00i1l; + wire_ni0l11ii_dataout <= ni0i00ii WHEN niOlOl0Oi = '1' ELSE wire_ni0l00lO_dataout; + wire_ni0l11il_dataout <= ni0i00il WHEN niOlOl0Oi = '1' ELSE wire_ni0l00Oi_dataout; + wire_ni0l11iO_dataout <= ni0i00iO WHEN niOlOl0Oi = '1' ELSE wire_ni0l00Ol_dataout; + wire_ni0l11l_dataout <= nl1OOlOO WHEN niOO0li1O = '1' ELSE ni00i1O; + wire_ni0l11li_dataout <= ni0i00li WHEN niOlOl0Oi = '1' ELSE wire_ni0l00OO_dataout; + wire_ni0l11ll_dataout <= ni0i00ll WHEN niOlOl0Oi = '1' ELSE wire_ni0l0i1i_dataout; + wire_ni0l11lO_dataout <= ni0i00lO WHEN niOlOl0Oi = '1' ELSE wire_ni0l0i1l_dataout; + wire_ni0l11O_dataout <= nl1OOO1i WHEN niOO0li1O = '1' ELSE ni00i0i; + wire_ni0l11Oi_dataout <= ni0i00Oi WHEN niOlOl0Oi = '1' ELSE wire_ni0l0i1O_dataout; + wire_ni0l11Ol_dataout <= ni0i00Ol WHEN niOlOl0Oi = '1' ELSE wire_ni0l0i0i_dataout; + wire_ni0l11OO_dataout <= ni0i00OO WHEN niOlOl0Oi = '1' ELSE wire_ni0l0i0l_dataout; + wire_ni0l1i0i_dataout <= ni0i10Oi WHEN niOlOl0ll = '1' ELSE wire_ni0l0liO_dataout; + wire_ni0l1i0l_dataout <= ni0i10Ol WHEN niOlOl0ll = '1' ELSE wire_ni0l0lli_dataout; + wire_ni0l1i0O_dataout <= ni0i10OO WHEN niOlOl0ll = '1' ELSE wire_ni0l0lll_dataout; + wire_ni0l1i1i_dataout <= ni0i10li WHEN niOlOl0ll = '1' ELSE wire_ni0l0l0O_dataout; + wire_ni0l1i1l_dataout <= ni0i10ll WHEN niOlOl0ll = '1' ELSE wire_ni0l0lii_dataout; + wire_ni0l1i1O_dataout <= ni0i10lO WHEN niOlOl0ll = '1' ELSE wire_ni0l0lil_dataout; + wire_ni0l1ii_dataout <= nl1OOO0l WHEN niOO0li1O = '1' ELSE ni00iil; + wire_ni0l1iii_dataout <= ni0i1i1i WHEN niOlOl0ll = '1' ELSE wire_ni0l0llO_dataout; + wire_ni0l1iil_dataout <= ni0i1i1l WHEN niOlOl0ll = '1' ELSE wire_ni0l0lOi_dataout; + wire_ni0l1iiO_dataout <= ni0i1i1O WHEN niOlOl0ll = '1' ELSE wire_ni0l0lOl_dataout; + wire_ni0l1il_dataout <= nl1OOO0O WHEN niOO0li1O = '1' ELSE ni00iiO; + wire_ni0l1ili_dataout <= ni0i1i0i WHEN niOlOl0ll = '1' ELSE wire_ni0l0lOO_dataout; + wire_ni0l1ill_dataout <= ni0i1i0O WHEN niOlOl0ll = '1' ELSE wire_ni0l0O1i_dataout; + wire_ni0l1ilO_dataout <= ni0i1iii WHEN niOlOl0ll = '1' ELSE wire_ni0l0O1l_dataout; + wire_ni0l1iO_dataout <= ni00ili AND NOT(niOO0li1O); + wire_ni0l1iOi_dataout <= ni0i1iil WHEN niOlOl0ll = '1' ELSE wire_ni0l0O1O_dataout; + wire_ni0l1iOl_dataout <= ni0i1iiO WHEN niOlOl0ll = '1' ELSE wire_ni0l0O0i_dataout; + wire_ni0l1iOO_dataout <= ni0i1ili WHEN niOlOl0ll = '1' ELSE wire_ni0l0O0l_dataout; + wire_ni0l1l0i_dataout <= ni0i1iOl WHEN niOlOl0ll = '1' ELSE wire_ni0l0OiO_dataout; + wire_ni0l1l0l_dataout <= ni0i1iOO WHEN niOlOl0ll = '1' ELSE wire_ni0l0Oli_dataout; + wire_ni0l1l0O_dataout <= ni0i1l1i WHEN niOlOl0ll = '1' ELSE wire_ni0l0Oll_dataout; + wire_ni0l1l1i_dataout <= ni0i1ill WHEN niOlOl0ll = '1' ELSE wire_ni0l0O0O_dataout; + wire_ni0l1l1l_dataout <= ni0i1ilO WHEN niOlOl0ll = '1' ELSE wire_ni0l0Oii_dataout; + wire_ni0l1l1O_dataout <= ni0i1iOi WHEN niOlOl0ll = '1' ELSE wire_ni0l0Oil_dataout; + wire_ni0l1li_dataout <= nl1OOOil WHEN niOO0li1O = '1' ELSE ni00ill; + wire_ni0l1lii_dataout <= ni0i1l1l WHEN niOlOl0ll = '1' ELSE wire_ni0l0OlO_dataout; + wire_ni0l1lil_dataout <= ni0i1l1O WHEN niOlOl0ll = '1' ELSE wire_ni0l0OOi_dataout; + wire_ni0l1liO_dataout <= ni0i1l0i WHEN niOlOl0ll = '1' ELSE wire_ni0l0OOl_dataout; + wire_ni0l1lli_dataout <= ni0i1l0l WHEN niOlOl0ll = '1' ELSE wire_ni0l0OOO_dataout; + wire_ni0l1lll_dataout <= ni0i1l0O WHEN niOlOl0ll = '1' ELSE wire_ni0li11i_dataout; + wire_ni0l1llO_dataout <= ni0i1lii WHEN niOlOl0ll = '1' ELSE wire_ni0li11l_dataout; + wire_ni0l1lO_dataout <= wire_ni0l1Oi_dataout OR (wire_nlOl1l0Ol_dataout AND nl1OOOii); + wire_ni0l1lOi_dataout <= ni0i1lil WHEN niOlOl0ll = '1' ELSE wire_ni0li11O_dataout; + wire_ni0l1lOl_dataout <= ni0i1liO WHEN niOlOl0ll = '1' ELSE wire_ni0li10i_dataout; + wire_ni0l1lOO_dataout <= ni0i1lli WHEN niOlOl0ll = '1' ELSE wire_ni0li10l_dataout; + wire_ni0l1O0i_dataout <= ni0i1lOl WHEN niOlOl0ll = '1' ELSE wire_ni0li1iO_dataout; + wire_ni0l1O0l_dataout <= ni0i1lOO WHEN niOlOl0ll = '1' ELSE wire_ni0li1li_dataout; + wire_ni0l1O0O_dataout <= ni0i1O1i WHEN niOlOl0ll = '1' ELSE wire_ni0li1ll_dataout; + wire_ni0l1O1i_dataout <= ni0i1lll WHEN niOlOl0ll = '1' ELSE wire_ni0li10O_dataout; + wire_ni0l1O1l_dataout <= ni0i1llO WHEN niOlOl0ll = '1' ELSE wire_ni0li1ii_dataout; + wire_ni0l1O1O_dataout <= ni0i1lOi WHEN niOlOl0ll = '1' ELSE wire_ni0li1il_dataout; + wire_ni0l1Oi_dataout <= ni0i0OO AND NOT(niOO0li0i); + wire_ni0l1Oii_dataout <= ni0i1O1l WHEN niOlOl0ll = '1' ELSE wire_ni0li1lO_dataout; + wire_ni0l1Oil_dataout <= ni0i1O1O WHEN niOlOl0ll = '1' ELSE wire_ni0li1Oi_dataout; + wire_ni0l1OiO_dataout <= ni0i1O0i WHEN niOlOl0ll = '1' ELSE wire_ni0li1Ol_dataout; + wire_ni0l1Oli_dataout <= ni0i1O0l WHEN niOlOl0ll = '1' ELSE wire_ni0li1OO_dataout; + wire_ni0l1Oll_dataout <= ni0i1O0O WHEN niOlOl0ll = '1' ELSE wire_ni0li01i_dataout; + wire_ni0l1OlO_dataout <= ni0i1Oii WHEN niOlOl0ll = '1' ELSE wire_ni0li01l_dataout; + wire_ni0l1OO_dataout <= wire_ni0l01i_dataout OR (wire_nlOl1l0Ol_dataout AND nl1OOOil); + wire_ni0l1OOi_dataout <= ni0i1Oil WHEN niOlOl0ll = '1' ELSE wire_ni0li01O_dataout; + wire_ni0l1OOl_dataout <= ni0i1OiO WHEN niOlOl0ll = '1' ELSE wire_ni0li00i_dataout; + wire_ni0l1OOO_dataout <= ni0i1Oli WHEN niOlOl0ll = '1' ELSE wire_ni0li00l_dataout; + wire_ni0li00i_dataout <= ni0i1OiO AND NOT(ni0i111l); + wire_ni0li00l_dataout <= ni0i1Oli AND NOT(ni0i111l); + wire_ni0li00O_dataout <= ni0i1Oll AND NOT(ni0i111l); + wire_ni0li01i_dataout <= ni0i1O0O AND NOT(ni0i111l); + wire_ni0li01l_dataout <= ni0i1Oii AND NOT(ni0i111l); + wire_ni0li01O_dataout <= ni0i1Oil AND NOT(ni0i111l); + wire_ni0li0ii_dataout <= ni0i1OlO AND NOT(ni0i111l); + wire_ni0li0il_dataout <= ni0i1OOi AND NOT(ni0i111l); + wire_ni0li0iO_dataout <= ni0i1OOl AND NOT(ni0i111l); + wire_ni0li0li_dataout <= ni0i1OOO AND NOT(ni0i111l); + wire_ni0li0ll_dataout <= ni0i011i AND NOT(ni0i111l); + wire_ni0li0lO_dataout <= ni0i011l AND NOT(ni0i111l); + wire_ni0li0Oi_dataout <= ni0i011O AND NOT(ni0i111l); + wire_ni0li0Ol_dataout <= ni0i010i AND NOT(ni0i111l); + wire_ni0li0OO_dataout <= ni0i010l AND NOT(ni0i111l); + wire_ni0li10i_dataout <= ni0i1liO AND NOT(ni0i111l); + wire_ni0li10l_dataout <= ni0i1lli AND NOT(ni0i111l); + wire_ni0li10O_dataout <= ni0i1lll AND NOT(ni0i111l); + wire_ni0li11i_dataout <= ni0i1l0O AND NOT(ni0i111l); + wire_ni0li11l_dataout <= ni0i1lii AND NOT(ni0i111l); + wire_ni0li11O_dataout <= ni0i1lil AND NOT(ni0i111l); + wire_ni0li1ii_dataout <= ni0i1llO AND NOT(ni0i111l); + wire_ni0li1il_dataout <= ni0i1lOi AND NOT(ni0i111l); + wire_ni0li1iO_dataout <= ni0i1lOl AND NOT(ni0i111l); + wire_ni0li1li_dataout <= ni0i1lOO AND NOT(ni0i111l); + wire_ni0li1ll_dataout <= ni0i1O1i AND NOT(ni0i111l); + wire_ni0li1lO_dataout <= ni0i1O1l AND NOT(ni0i111l); + wire_ni0li1O_dataout <= nlliiilli AND NOT(wire_niO01O0O_dataout); + wire_ni0li1Oi_dataout <= ni0i1O1O AND NOT(ni0i111l); + wire_ni0li1Ol_dataout <= ni0i1O0i AND NOT(ni0i111l); + wire_ni0li1OO_dataout <= ni0i1O0l AND NOT(ni0i111l); + wire_ni0lii0i_dataout <= ni0i01iO AND NOT(ni0i111l); + wire_ni0lii0l_dataout <= ni0i01li AND NOT(ni0i111l); + wire_ni0lii0O_dataout <= ni0i01ll AND NOT(ni0i111l); + wire_ni0lii1i_dataout <= ni0i010O AND NOT(ni0i111l); + wire_ni0lii1l_dataout <= ni0i01ii AND NOT(ni0i111l); + wire_ni0lii1O_dataout <= ni0i01il AND NOT(ni0i111l); + wire_ni0liiii_dataout <= ni0i01lO AND NOT(ni0i111l); + wire_ni0liiil_dataout <= ni0i01Oi AND NOT(ni0i111l); + wire_ni0liiiO_dataout <= ni0i01Ol AND NOT(ni0i111l); + wire_ni0liili_dataout <= ni0i01OO AND NOT(ni0i111l); + wire_ni0liill_dataout <= ni0i001i AND NOT(ni0i111l); + wire_ni0liilO_dataout <= ni0i001l AND NOT(ni0i111l); + wire_ni0liiOi_dataout <= ni0i001O AND NOT(ni0i111l); + wire_ni0liiOl_dataout <= ni0i000i AND NOT(ni0i111l); + wire_ni0liiOO_dataout <= ni0i000l AND NOT(ni0i111l); + wire_ni0lil0i_dataout <= ni0i00iO AND NOT(ni0i111l); + wire_ni0lil0l_dataout <= ni0i00li AND NOT(ni0i111l); + wire_ni0lil0O_dataout <= ni0i00ll AND NOT(ni0i111l); + wire_ni0lil1i_dataout <= ni0i000O AND NOT(ni0i111l); + wire_ni0lil1l_dataout <= ni0i00ii AND NOT(ni0i111l); + wire_ni0lil1O_dataout <= ni0i00il AND NOT(ni0i111l); + wire_ni0lilii_dataout <= ni0i00lO AND NOT(ni0i111l); + wire_ni0lilil_dataout <= ni0i00Oi AND NOT(ni0i111l); + wire_ni0liliO_dataout <= ni0i00Ol AND NOT(ni0i111l); + wire_ni0lilli_dataout <= ni0i00OO AND NOT(ni0i111l); + wire_ni0lilll_dataout <= ni0i0i1i AND NOT(ni0i111l); + wire_ni0lillO_dataout <= ni0i0i1l AND NOT(ni0i111l); + wire_ni0lilOi_dataout <= ni0i0i1O AND NOT(ni0i111l); + wire_ni0lilOl_dataout <= ni0i0i0i AND NOT(ni0i111l); + wire_ni0lilOO_dataout <= ni0i0i0l AND NOT(ni0i111l); + wire_ni0liOl_dataout <= tl_app_msi_num(0) AND NOT(wire_niO01l0O_dataout); + wire_ni0liOO_dataout <= tl_app_msi_num(1) AND NOT(wire_niO01l0O_dataout); + wire_ni0liOOl_dataout <= wire_ni0lOOOi_dataout AND NOT(niil010O); + wire_ni0liOOO_dataout <= wire_ni0lOOOl_dataout AND NOT(niil010O); + wire_ni0ll00i_dataout <= ni01iOiO WHEN niil010O = '1' ELSE wire_ni0lO01i_dataout; + wire_ni0ll00l_dataout <= ni01l0ll WHEN niil010O = '1' ELSE wire_ni0lO01l_dataout; + wire_ni0ll00O_dataout <= ni01l0lO WHEN niil010O = '1' ELSE wire_ni0lO01O_dataout; + wire_ni0ll01i_dataout <= ni00l1ii WHEN niil010O = '1' ELSE wire_ni0lO1Oi_dataout; + wire_ni0ll01l_dataout <= ni00l1il WHEN niil010O = '1' ELSE wire_ni0lO1Ol_dataout; + wire_ni0ll01O_dataout <= ni00l1iO WHEN niil010O = '1' ELSE wire_ni0lO1OO_dataout; + wire_ni0ll0i_dataout <= tl_app_msi_tc(0) AND NOT(wire_niO01l0O_dataout); + wire_ni0ll0ii_dataout <= ni01l0Oi WHEN niil010O = '1' ELSE wire_ni0lO00i_dataout; + wire_ni0ll0il_dataout <= ni01l0Ol WHEN niil010O = '1' ELSE wire_ni0lO00l_dataout; + wire_ni0ll0iO_dataout <= ni01l0OO WHEN niil010O = '1' ELSE wire_ni0lO00O_dataout; + wire_ni0ll0l_dataout <= tl_app_msi_tc(1) AND NOT(wire_niO01l0O_dataout); + wire_ni0ll0li_dataout <= ni01li1i WHEN niil010O = '1' ELSE wire_ni0lO0ii_dataout; + wire_ni0ll0ll_dataout <= ni01li1l WHEN niil010O = '1' ELSE wire_ni0lO0il_dataout; + wire_ni0ll0lO_dataout <= ni1Ol01l WHEN niil010O = '1' ELSE wire_ni0lO0iO_dataout; + wire_ni0ll0O_dataout <= tl_app_msi_tc(2) AND NOT(wire_niO01l0O_dataout); + wire_ni0ll0Oi_dataout <= ni1Oll0i WHEN niil010O = '1' ELSE wire_ni0lO0li_dataout; + wire_ni0ll0Ol_dataout <= ni1Oll0l WHEN niil010O = '1' ELSE wire_ni0lO0ll_dataout; + wire_ni0ll0OO_dataout <= ni1Oll0O WHEN niil010O = '1' ELSE wire_ni0lO0lO_dataout; + wire_ni0ll10i_dataout <= ni01li1O WHEN niil010O = '1' ELSE wire_ni0lO11i_dataout; + wire_ni0ll10l_dataout <= ni1Ollll WHEN niil010O = '1' ELSE wire_ni0lO11l_dataout; + wire_ni0ll10O_dataout <= ni1lO10i WHEN niil010O = '1' ELSE wire_ni0lO11O_dataout; + wire_ni0ll11i_dataout <= wire_ni0lOOOO_dataout AND NOT(niil010O); + wire_ni0ll11l_dataout <= wire_ni0lOOlO_dataout OR niil010O; + wire_ni0ll11O_dataout <= ni00l1li WHEN niil010O = '1' ELSE wire_ni0llOOO_dataout; + wire_ni0ll1i_dataout <= tl_app_msi_num(2) AND NOT(wire_niO01l0O_dataout); + wire_ni0ll1ii_dataout <= ni1iO0lO WHEN niil010O = '1' ELSE wire_ni0lO10i_dataout; + wire_ni0ll1il_dataout <= ni10Ol0l WHEN niil010O = '1' ELSE wire_ni0lO10l_dataout; + wire_ni0ll1iO_dataout <= ni11OOOi WHEN niil010O = '1' ELSE wire_ni0lO10O_dataout; + wire_ni0ll1l_dataout <= tl_app_msi_num(3) AND NOT(wire_niO01l0O_dataout); + wire_ni0ll1li_dataout <= ni11100O WHEN niil010O = '1' ELSE wire_ni0lO1ii_dataout; + wire_ni0ll1ll_dataout <= ni00il1i WHEN niil010O = '1' ELSE wire_ni0lO1il_dataout; + wire_ni0ll1lO_dataout <= ni00l11O WHEN niil010O = '1' ELSE wire_ni0lO1iO_dataout; + wire_ni0ll1O_dataout <= tl_app_msi_num(4) AND NOT(wire_niO01l0O_dataout); + wire_ni0ll1Oi_dataout <= ni00l10i WHEN niil010O = '1' ELSE wire_ni0lO1li_dataout; + wire_ni0ll1Ol_dataout <= ni00l10l WHEN niil010O = '1' ELSE wire_ni0lO1ll_dataout; + wire_ni0ll1OO_dataout <= ni00l10O WHEN niil010O = '1' ELSE wire_ni0lO1lO_dataout; + wire_ni0lli0i_dataout <= ni1Ollli WHEN niil010O = '1' ELSE wire_ni0lOi1i_dataout; + wire_ni0lli0l_dataout <= ni1llili WHEN niil010O = '1' ELSE wire_ni0lOi1l_dataout; + wire_ni0lli0O_dataout <= ni1llOlO WHEN niil010O = '1' ELSE wire_ni0lOi1O_dataout; + wire_ni0lli1i_dataout <= ni1Ollii WHEN niil010O = '1' ELSE wire_ni0lO0Oi_dataout; + wire_ni0lli1l_dataout <= ni1Ollil WHEN niil010O = '1' ELSE wire_ni0lO0Ol_dataout; + wire_ni0lli1O_dataout <= ni1OlliO WHEN niil010O = '1' ELSE wire_ni0lO0OO_dataout; + wire_ni0llii_dataout <= tl_app_msi_req AND NOT(wire_niO01l0O_dataout); + wire_ni0lliii_dataout <= ni1llOOi WHEN niil010O = '1' ELSE wire_ni0lOi0i_dataout; + wire_ni0lliil_dataout <= ni1llOOl WHEN niil010O = '1' ELSE wire_ni0lOi0l_dataout; + wire_ni0lliiO_dataout <= ni1llOOO WHEN niil010O = '1' ELSE wire_ni0lOi0O_dataout; + wire_ni0llili_dataout <= ni1lO11i WHEN niil010O = '1' ELSE wire_ni0lOiii_dataout; + wire_ni0llill_dataout <= ni1lO11l WHEN niil010O = '1' ELSE wire_ni0lOiil_dataout; + wire_ni0llilO_dataout <= ni1lO11O WHEN niil010O = '1' ELSE wire_ni0lOiiO_dataout; + wire_ni0lliOi_dataout <= ni1ilO1O WHEN niil010O = '1' ELSE wire_ni0lOili_dataout; + wire_ni0lliOl_dataout <= ni1iO00l WHEN niil010O = '1' ELSE wire_ni0lOill_dataout; + wire_ni0lliOO_dataout <= ni1iO00O WHEN niil010O = '1' ELSE wire_ni0lOilO_dataout; + wire_ni0lll0i_dataout <= ni1iO0li WHEN niil010O = '1' ELSE wire_ni0lOl1i_dataout; + wire_ni0lll0l_dataout <= ni1iO0ll WHEN niil010O = '1' ELSE wire_ni0lOl1l_dataout; + wire_ni0lll0O_dataout <= ni10O1ll WHEN niil010O = '1' ELSE wire_ni0lOl1O_dataout; + wire_ni0lll1i_dataout <= ni1iO0ii WHEN niil010O = '1' ELSE wire_ni0lOiOi_dataout; + wire_ni0lll1l_dataout <= ni1iO0il WHEN niil010O = '1' ELSE wire_ni0lOiOl_dataout; + wire_ni0lll1O_dataout <= ni1iO0iO WHEN niil010O = '1' ELSE wire_ni0lOiOO_dataout; + wire_ni0lllii_dataout <= ni10OiOi WHEN niil010O = '1' ELSE wire_ni0lOl0i_dataout; + wire_ni0lllil_dataout <= ni10OiOl WHEN niil010O = '1' ELSE wire_ni0lOl0l_dataout; + wire_ni0llliO_dataout <= ni10OiOO WHEN niil010O = '1' ELSE wire_ni0lOl0O_dataout; + wire_ni0lllli_dataout <= ni10Ol1i WHEN niil010O = '1' ELSE wire_ni0lOlii_dataout; + wire_ni0lllll_dataout <= ni10Ol1l WHEN niil010O = '1' ELSE wire_ni0lOlil_dataout; + wire_ni0llllO_dataout <= ni10Ol1O WHEN niil010O = '1' ELSE wire_ni0lOliO_dataout; + wire_ni0lllOi_dataout <= ni10Ol0i WHEN niil010O = '1' ELSE wire_ni0lOlli_dataout; + wire_ni0lllOl_dataout <= ni11Oi0i WHEN niil010O = '1' ELSE wire_ni0lOlll_dataout; + wire_ni0lllOO_dataout <= ni11OO0O WHEN niil010O = '1' ELSE wire_ni0lOllO_dataout; + wire_ni0llO0i_dataout <= ni11OOli WHEN niil010O = '1' ELSE wire_ni0lOO1i_dataout; + wire_ni0llO0l_dataout <= ni11OOll WHEN niil010O = '1' ELSE wire_ni0lOO1l_dataout; + wire_ni0llO0O_dataout <= ni11OOlO WHEN niil010O = '1' ELSE wire_ni0lOO1O_dataout; + wire_ni0llO1i_dataout <= ni11OOii WHEN niil010O = '1' ELSE wire_ni0lOlOi_dataout; + wire_ni0llO1l_dataout <= ni11OOil WHEN niil010O = '1' ELSE wire_ni0lOlOl_dataout; + wire_ni0llO1O_dataout <= ni11OOiO WHEN niil010O = '1' ELSE wire_ni0lOlOO_dataout; + wire_ni0llOii_dataout <= n0OOOllO WHEN niil010O = '1' ELSE wire_ni0lOO0i_dataout; + wire_ni0llOil_dataout <= ni1111Ol WHEN niil010O = '1' ELSE wire_ni0lOO0l_dataout; + wire_ni0llOiO_dataout <= ni1111OO WHEN niil010O = '1' ELSE wire_ni0lOO0O_dataout; + wire_ni0llOli_dataout <= ni11101i WHEN niil010O = '1' ELSE wire_ni0lOOii_dataout; + wire_ni0llOll_dataout <= ni11101l WHEN niil010O = '1' ELSE wire_ni0lOOil_dataout; + wire_ni0llOlO_dataout <= ni11101O WHEN niil010O = '1' ELSE wire_ni0lOOiO_dataout; + wire_ni0llOOi_dataout <= ni11100i WHEN niil010O = '1' ELSE wire_ni0lOOli_dataout; + wire_ni0llOOl_dataout <= ni11100l WHEN niil010O = '1' ELSE wire_ni0lOOll_dataout; + wire_ni0llOOO_dataout <= wire_nii0ii0l_dataout WHEN niil010l = '1' ELSE wire_ni0O111i_dataout; + wire_ni0lO00i_dataout <= wire_nii0ilii_dataout WHEN niil010l = '1' ELSE wire_ni0O100l_dataout; + wire_ni0lO00l_dataout <= wire_nii0ilil_dataout WHEN niil010l = '1' ELSE wire_ni0O100O_dataout; + wire_ni0lO00O_dataout <= wire_nii0iliO_dataout WHEN niil010l = '1' ELSE wire_ni0O10ii_dataout; + wire_ni0lO01i_dataout <= wire_nii0il0i_dataout WHEN niil010l = '1' ELSE wire_ni0O101l_dataout; + wire_ni0lO01l_dataout <= wire_nii0il0l_dataout WHEN niil010l = '1' ELSE wire_ni0O101O_dataout; + wire_ni0lO01O_dataout <= wire_nii0il0O_dataout WHEN niil010l = '1' ELSE wire_ni0O100i_dataout; + wire_ni0lO0i_dataout <= wire_ni0lOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lO0ii_dataout <= wire_nii0illi_dataout WHEN niil010l = '1' ELSE wire_ni0O10il_dataout; + wire_ni0lO0il_dataout <= wire_nii0illl_dataout WHEN niil010l = '1' ELSE wire_ni0O10iO_dataout; + wire_ni0lO0iO_dataout <= wire_nii0illO_dataout WHEN niil010l = '1' ELSE wire_ni0O10li_dataout; + wire_ni0lO0l_dataout <= wire_ni0lOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lO0li_dataout <= wire_nii0ilOi_dataout WHEN niil010l = '1' ELSE wire_ni0O10ll_dataout; + wire_ni0lO0ll_dataout <= wire_nii0ilOl_dataout WHEN niil010l = '1' ELSE wire_ni0O10lO_dataout; + wire_ni0lO0lO_dataout <= wire_nii0ilOO_dataout WHEN niil010l = '1' ELSE wire_ni0O10Oi_dataout; + wire_ni0lO0O_dataout <= wire_ni0O11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lO0Oi_dataout <= wire_nii0iO1i_dataout WHEN niil010l = '1' ELSE wire_ni0O10Ol_dataout; + wire_ni0lO0Ol_dataout <= wire_nii0iO1l_dataout WHEN niil010l = '1' ELSE wire_ni0O10OO_dataout; + wire_ni0lO0OO_dataout <= wire_nii0iO1O_dataout WHEN niil010l = '1' ELSE wire_ni0O1i1i_dataout; + wire_ni0lO10i_dataout <= wire_nii0iiiO_dataout WHEN niil010l = '1' ELSE wire_ni0O110l_dataout; + wire_ni0lO10l_dataout <= wire_nii0iili_dataout WHEN niil010l = '1' ELSE wire_ni0O110O_dataout; + wire_ni0lO10O_dataout <= wire_nii1O00l_dataout WHEN niil010l = '1' ELSE wire_ni0O11ii_dataout; + wire_ni0lO11i_dataout <= wire_nii0ii0O_dataout WHEN niil010l = '1' ELSE wire_ni0O111l_dataout; + wire_ni0lO11l_dataout <= wire_nii0iiii_dataout WHEN niil010l = '1' ELSE wire_ni0O111O_dataout; + wire_ni0lO11O_dataout <= wire_nii0iiil_dataout WHEN niil010l = '1' ELSE wire_ni0O110i_dataout; + wire_ni0lO1ii_dataout <= wire_ni0Ol1ll_dataout WHEN niil010l = '1' ELSE wire_ni0O11il_dataout; + wire_ni0lO1il_dataout <= wire_nii0iill_dataout WHEN niil010l = '1' ELSE wire_ni0O11iO_dataout; + wire_ni0lO1iO_dataout <= wire_nii0iilO_dataout WHEN niil010l = '1' ELSE wire_ni0O11li_dataout; + wire_ni0lO1li_dataout <= wire_nii0iiOi_dataout WHEN niil010l = '1' ELSE wire_ni0O11ll_dataout; + wire_ni0lO1ll_dataout <= wire_nii0iiOl_dataout WHEN niil010l = '1' ELSE wire_ni0O11lO_dataout; + wire_ni0lO1lO_dataout <= wire_nii0iiOO_dataout WHEN niil010l = '1' ELSE wire_ni0O11Oi_dataout; + wire_ni0lO1O_dataout <= wire_ni0lOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lO1Oi_dataout <= wire_nii0il1i_dataout WHEN niil010l = '1' ELSE wire_ni0O11Ol_dataout; + wire_ni0lO1Ol_dataout <= wire_nii0il1l_dataout WHEN niil010l = '1' ELSE wire_ni0O11OO_dataout; + wire_ni0lO1OO_dataout <= wire_nii0il1O_dataout WHEN niil010l = '1' ELSE wire_ni0O101i_dataout; + wire_ni0lOi0i_dataout <= wire_nii0iOii_dataout WHEN niil010l = '1' ELSE wire_ni0O1i0l_dataout; + wire_ni0lOi0l_dataout <= wire_nii0iOil_dataout WHEN niil010l = '1' ELSE wire_ni0O1i0O_dataout; + wire_ni0lOi0O_dataout <= wire_nii0iOiO_dataout WHEN niil010l = '1' ELSE wire_ni0O1iii_dataout; + wire_ni0lOi1i_dataout <= wire_nii0iO0i_dataout WHEN niil010l = '1' ELSE wire_ni0O1i1l_dataout; + wire_ni0lOi1l_dataout <= wire_nii0iO0l_dataout WHEN niil010l = '1' ELSE wire_ni0O1i1O_dataout; + wire_ni0lOi1O_dataout <= wire_nii0iO0O_dataout WHEN niil010l = '1' ELSE wire_ni0O1i0i_dataout; + wire_ni0lOii_dataout <= wire_ni0O11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lOiii_dataout <= wire_nii0iOli_dataout WHEN niil010l = '1' ELSE wire_ni0O1iil_dataout; + wire_ni0lOiil_dataout <= wire_nii0iOll_dataout WHEN niil010l = '1' ELSE wire_ni0O1iiO_dataout; + wire_ni0lOiiO_dataout <= wire_nii0iOlO_dataout WHEN niil010l = '1' ELSE wire_ni0O1ili_dataout; + wire_ni0lOil_dataout <= wire_ni0O11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lOili_dataout <= wire_nii0iOOi_dataout WHEN niil010l = '1' ELSE wire_ni0O1ill_dataout; + wire_ni0lOill_dataout <= wire_nii0iOOl_dataout WHEN niil010l = '1' ELSE wire_ni0O1ilO_dataout; + wire_ni0lOilO_dataout <= wire_nii0iOOO_dataout WHEN niil010l = '1' ELSE wire_ni0O1iOi_dataout; + wire_ni0lOiO_dataout <= wire_ni0O10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lOiOi_dataout <= wire_nii0l11i_dataout WHEN niil010l = '1' ELSE wire_ni0O1iOl_dataout; + wire_ni0lOiOl_dataout <= wire_nii0l11l_dataout WHEN niil010l = '1' ELSE wire_ni0O1iOO_dataout; + wire_ni0lOiOO_dataout <= wire_nii0l11O_dataout WHEN niil010l = '1' ELSE wire_ni0O1l1i_dataout; + wire_ni0lOl0i_dataout <= wire_nii0l1ii_dataout WHEN niil010l = '1' ELSE wire_ni0O1l0l_dataout; + wire_ni0lOl0l_dataout <= wire_nii0l1il_dataout WHEN niil010l = '1' ELSE wire_ni0O1l0O_dataout; + wire_ni0lOl0O_dataout <= wire_nii0l1iO_dataout WHEN niil010l = '1' ELSE wire_ni0O1lii_dataout; + wire_ni0lOl1i_dataout <= wire_nii0l10i_dataout WHEN niil010l = '1' ELSE wire_ni0O1l1l_dataout; + wire_ni0lOl1l_dataout <= wire_nii0l10l_dataout WHEN niil010l = '1' ELSE wire_ni0O1l1O_dataout; + wire_ni0lOl1O_dataout <= wire_nii0l10O_dataout WHEN niil010l = '1' ELSE wire_ni0O1l0i_dataout; + wire_ni0lOli_dataout <= wire_ni0O10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lOlii_dataout <= wire_nii0l1li_dataout WHEN niil010l = '1' ELSE wire_ni0O1lil_dataout; + wire_ni0lOlil_dataout <= wire_nii0l1ll_dataout WHEN niil010l = '1' ELSE wire_ni0O1liO_dataout; + wire_ni0lOliO_dataout <= wire_nii0l1lO_dataout WHEN niil010l = '1' ELSE wire_ni0O1lli_dataout; + wire_ni0lOll_dataout <= wire_ni0O10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0lOlli_dataout <= wire_nii0l1Oi_dataout WHEN niil010l = '1' ELSE wire_ni0O1lll_dataout; + wire_ni0lOlll_dataout <= wire_nii1OOiO_dataout WHEN niil010l = '1' ELSE wire_ni0O1llO_dataout; + wire_ni0lOllO_dataout <= wire_nii1OOli_dataout WHEN niil010l = '1' ELSE wire_ni0O1lOi_dataout; + wire_ni0lOlO_dataout <= nl101OiO AND NOT(wire_niO01O0O_dataout); + wire_ni0lOlOi_dataout <= wire_nii1OOll_dataout WHEN niil010l = '1' ELSE wire_ni0O1lOl_dataout; + wire_ni0lOlOl_dataout <= wire_nii1OOlO_dataout WHEN niil010l = '1' ELSE wire_ni0O1lOO_dataout; + wire_ni0lOlOO_dataout <= wire_nii1OOOi_dataout WHEN niil010l = '1' ELSE wire_ni0O1O1i_dataout; + wire_ni0lOO0i_dataout <= wire_ni0OlOil_dataout WHEN niil010l = '1' ELSE wire_ni0O1O0l_dataout; + wire_ni0lOO0l_dataout <= wire_ni0OlOiO_dataout WHEN niil010l = '1' ELSE wire_ni0O1O0O_dataout; + wire_ni0lOO0O_dataout <= wire_ni0OlOli_dataout WHEN niil010l = '1' ELSE wire_ni0O1Oii_dataout; + wire_ni0lOO1i_dataout <= wire_nii1OOOl_dataout WHEN niil010l = '1' ELSE wire_ni0O1O1l_dataout; + wire_ni0lOO1l_dataout <= wire_nii1OOOO_dataout WHEN niil010l = '1' ELSE wire_ni0O1O1O_dataout; + wire_ni0lOO1O_dataout <= wire_nii0111i_dataout WHEN niil010l = '1' ELSE wire_ni0O1O0i_dataout; + wire_ni0lOOi_dataout <= nl1001OO WHEN niOO0liil = '1' ELSE ni0liOi; + wire_ni0lOOii_dataout <= wire_ni0OlOll_dataout WHEN niil010l = '1' ELSE wire_ni0O1Oil_dataout; + wire_ni0lOOil_dataout <= wire_ni0OlOlO_dataout WHEN niil010l = '1' ELSE wire_ni0O1OiO_dataout; + wire_ni0lOOiO_dataout <= wire_ni0OlOOi_dataout WHEN niil010l = '1' ELSE wire_ni0O1Oli_dataout; + wire_ni0lOOl_dataout <= nl101O1l WHEN niOO0liil = '1' ELSE ni0llil; + wire_ni0lOOli_dataout <= wire_ni0OlOOl_dataout WHEN niil010l = '1' ELSE wire_ni0O1Oll_dataout; + wire_ni0lOOll_dataout <= wire_ni0OlOOO_dataout WHEN niil010l = '1' ELSE wire_ni0O1OlO_dataout; + wire_ni0lOOlO_dataout <= wire_w_lg_niOlOll0l10155w(0) WHEN niil010l = '1' ELSE wire_ni0O1OOi_dataout; + wire_ni0lOOO_dataout <= nl101O1O WHEN niOO0liil = '1' ELSE ni0lliO; + wire_ni0lOOOi_dataout <= niOlOll0l WHEN niil010l = '1' ELSE wire_ni0O1OOl_dataout; + wire_ni0lOOOl_dataout <= wire_ni0O1OOO_dataout AND NOT(niil010l); + wire_ni0lOOOO_dataout <= wire_ni0O011i_dataout AND NOT(niil010l); + wire_ni0O000i_dataout <= wire_ni0Oi00l_dataout WHEN niil00Ol = '1' ELSE ni0i1lil; + wire_ni0O000l_dataout <= wire_ni0Oi00O_dataout WHEN niil00Ol = '1' ELSE ni0i1liO; + wire_ni0O000O_dataout <= wire_ni0Oi0ii_dataout WHEN niil00Ol = '1' ELSE ni0i1lli; + wire_ni0O001i_dataout <= wire_ni0Oi01l_dataout WHEN niil00Ol = '1' ELSE ni0i1l0l; + wire_ni0O001l_dataout <= wire_ni0Oi01O_dataout WHEN niil00Ol = '1' ELSE ni0i1l0O; + wire_ni0O001O_dataout <= wire_ni0Oi00i_dataout WHEN niil00Ol = '1' ELSE ni0i1lii; + wire_ni0O00ii_dataout <= wire_ni0Oi0il_dataout WHEN niil00Ol = '1' ELSE ni0i1lll; + wire_ni0O00il_dataout <= wire_ni0Oi0iO_dataout WHEN niil00Ol = '1' ELSE ni0i1llO; + wire_ni0O00iO_dataout <= wire_ni0Oi0li_dataout WHEN niil00Ol = '1' ELSE ni0i1lOi; + wire_ni0O00li_dataout <= wire_ni0Oi0ll_dataout WHEN niil00Ol = '1' ELSE ni0i1lOl; + wire_ni0O00ll_dataout <= wire_ni0Oi0lO_dataout WHEN niil00Ol = '1' ELSE ni0i1lOO; + wire_ni0O00lO_dataout <= wire_ni0Oi0Oi_dataout WHEN niil00Ol = '1' ELSE ni0i1O1i; + wire_ni0O00Oi_dataout <= wire_ni0Oi0Ol_dataout WHEN niil00Ol = '1' ELSE ni0i1O1l; + wire_ni0O00Ol_dataout <= wire_ni0Oi0OO_dataout WHEN niil00Ol = '1' ELSE ni0i1O1O; + wire_ni0O00OO_dataout <= wire_ni0Oii1i_dataout WHEN niil00Ol = '1' ELSE ni0i1O0i; + wire_ni0O010i_dataout <= wire_ni0Oi10l_dataout WHEN niil00Ol = '1' ELSE ni0i1iil; + wire_ni0O010l_dataout <= wire_ni0Oi10O_dataout WHEN niil00Ol = '1' ELSE ni0i1iiO; + wire_ni0O010O_dataout <= wire_ni0Oi1ii_dataout WHEN niil00Ol = '1' ELSE ni0i1ili; + wire_ni0O011i_dataout <= wire_nii1O1Oi_dataout WHEN niil010i = '1' ELSE wire_ni0Oi11l_dataout; + wire_ni0O011l_dataout <= wire_ni0Oi11O_dataout WHEN niil00Ol = '1' ELSE ni0i1i0O; + wire_ni0O011O_dataout <= wire_ni0Oi10i_dataout WHEN niil00Ol = '1' ELSE ni0i1iii; + wire_ni0O01ii_dataout <= wire_ni0Oi1il_dataout WHEN niil00Ol = '1' ELSE ni0i1ill; + wire_ni0O01il_dataout <= wire_ni0Oi1iO_dataout WHEN niil00Ol = '1' ELSE ni0i1ilO; + wire_ni0O01iO_dataout <= wire_ni0Oi1li_dataout WHEN niil00Ol = '1' ELSE ni0i1iOi; + wire_ni0O01li_dataout <= wire_ni0Oi1ll_dataout WHEN niil00Ol = '1' ELSE ni0i1iOl; + wire_ni0O01ll_dataout <= wire_ni0Oi1lO_dataout WHEN niil00Ol = '1' ELSE ni0i1iOO; + wire_ni0O01lO_dataout <= wire_ni0Oi1Oi_dataout WHEN niil00Ol = '1' ELSE ni0i1l1i; + wire_ni0O01Oi_dataout <= wire_ni0Oi1Ol_dataout WHEN niil00Ol = '1' ELSE ni0i1l1l; + wire_ni0O01Ol_dataout <= wire_ni0Oi1OO_dataout WHEN niil00Ol = '1' ELSE ni0i1l1O; + wire_ni0O01OO_dataout <= wire_ni0Oi01i_dataout WHEN niil00Ol = '1' ELSE ni0i1l0i; + wire_ni0O0i0i_dataout <= wire_ni0Oii0l_dataout WHEN niil00Ol = '1' ELSE ni0i1Oil; + wire_ni0O0i0l_dataout <= wire_ni0Oii0O_dataout WHEN niil00Ol = '1' ELSE ni0i1OiO; + wire_ni0O0i0O_dataout <= wire_ni0Oiiii_dataout WHEN niil00Ol = '1' ELSE ni0i1Oli; + wire_ni0O0i1i_dataout <= wire_ni0Oii1l_dataout WHEN niil00Ol = '1' ELSE ni0i1O0l; + wire_ni0O0i1l_dataout <= wire_ni0Oii1O_dataout WHEN niil00Ol = '1' ELSE ni0i1O0O; + wire_ni0O0i1O_dataout <= wire_ni0Oii0i_dataout WHEN niil00Ol = '1' ELSE ni0i1Oii; + wire_ni0O0iii_dataout <= wire_ni0Oiiil_dataout WHEN niil00Ol = '1' ELSE ni0i1Oll; + wire_ni0O0iil_dataout <= wire_ni0OiiiO_dataout WHEN niil00Ol = '1' ELSE ni0i1OlO; + wire_ni0O0iiO_dataout <= wire_ni0Oiili_dataout WHEN niil00Ol = '1' ELSE ni0i1OOi; + wire_ni0O0ili_dataout <= wire_ni0Oiill_dataout WHEN niil00Ol = '1' ELSE ni0i1OOl; + wire_ni0O0ill_dataout <= wire_ni0OiilO_dataout WHEN niil00Ol = '1' ELSE ni0i1OOO; + wire_ni0O0ilO_dataout <= wire_ni0OiiOi_dataout WHEN niil00Ol = '1' ELSE ni0i011i; + wire_ni0O0iOi_dataout <= wire_ni0OiiOl_dataout WHEN niil00Ol = '1' ELSE ni0i011l; + wire_ni0O0iOl_dataout <= wire_ni0OiiOO_dataout WHEN niil00Ol = '1' ELSE ni0i011O; + wire_ni0O0iOO_dataout <= wire_ni0Oil1i_dataout WHEN niil00Ol = '1' ELSE ni0i010i; + wire_ni0O0l0i_dataout <= wire_ni0Oil0l_dataout WHEN niil00Ol = '1' ELSE ni0i01il; + wire_ni0O0l0l_dataout <= wire_ni0Oil0O_dataout WHEN niil00Ol = '1' ELSE ni0i01iO; + wire_ni0O0l0O_dataout <= wire_ni0Oilii_dataout WHEN niil00Ol = '1' ELSE ni0i01li; + wire_ni0O0l1i_dataout <= wire_ni0Oil1l_dataout WHEN niil00Ol = '1' ELSE ni0i010l; + wire_ni0O0l1l_dataout <= wire_ni0Oil1O_dataout WHEN niil00Ol = '1' ELSE ni0i010O; + wire_ni0O0l1O_dataout <= wire_ni0Oil0i_dataout WHEN niil00Ol = '1' ELSE ni0i01ii; + wire_ni0O0lii_dataout <= wire_ni0Oilil_dataout WHEN niil00Ol = '1' ELSE ni0i01ll; + wire_ni0O0lil_dataout <= wire_ni0OiliO_dataout WHEN niil00Ol = '1' ELSE ni0i01lO; + wire_ni0O0liO_dataout <= wire_ni0Oilli_dataout WHEN niil00Ol = '1' ELSE ni0i01Oi; + wire_ni0O0lli_dataout <= wire_ni0Oilll_dataout WHEN niil00Ol = '1' ELSE ni0i01Ol; + wire_ni0O0lll_dataout <= wire_ni0OillO_dataout WHEN niil00Ol = '1' ELSE ni0i01OO; + wire_ni0O0llO_dataout <= wire_ni0OilOi_dataout WHEN niil00Ol = '1' ELSE ni0i001i; + wire_ni0O0lOi_dataout <= wire_ni0OilOl_dataout WHEN niil00Ol = '1' ELSE ni0i001l; + wire_ni0O0lOl_dataout <= wire_ni0OilOO_dataout WHEN niil00Ol = '1' ELSE ni0i001O; + wire_ni0O0lOO_dataout <= wire_ni0OiO1i_dataout WHEN niil00Ol = '1' ELSE ni0i000i; + wire_ni0O0O0i_dataout <= wire_ni0OiO0l_dataout WHEN niil00Ol = '1' ELSE ni0i00il; + wire_ni0O0O0l_dataout <= wire_ni0OiO0O_dataout WHEN niil00Ol = '1' ELSE ni0i00iO; + wire_ni0O0O0O_dataout <= wire_ni0OiOii_dataout WHEN niil00Ol = '1' ELSE ni0i00li; + wire_ni0O0O1i_dataout <= wire_ni0OiO1l_dataout WHEN niil00Ol = '1' ELSE ni0i000l; + wire_ni0O0O1l_dataout <= wire_ni0OiO1O_dataout WHEN niil00Ol = '1' ELSE ni0i000O; + wire_ni0O0O1O_dataout <= wire_ni0OiO0i_dataout WHEN niil00Ol = '1' ELSE ni0i00ii; + wire_ni0O0Oii_dataout <= wire_ni0OiOil_dataout WHEN niil00Ol = '1' ELSE ni0i00ll; + wire_ni0O0Oil_dataout <= wire_ni0OiOiO_dataout WHEN niil00Ol = '1' ELSE ni0i00lO; + wire_ni0O0OiO_dataout <= wire_ni0OiOli_dataout WHEN niil00Ol = '1' ELSE ni0i00Oi; + wire_ni0O0Oli_dataout <= wire_ni0OiOll_dataout WHEN niil00Ol = '1' ELSE ni0i00Ol; + wire_ni0O0Oll_dataout <= wire_ni0OiOlO_dataout WHEN niil00Ol = '1' ELSE ni0i00OO; + wire_ni0O0OlO_dataout <= wire_ni0OiOOi_dataout WHEN niil00Ol = '1' ELSE ni0i0i1i; + wire_ni0O0OOi_dataout <= wire_ni0OiOOl_dataout WHEN niil00Ol = '1' ELSE ni0i0i1l; + wire_ni0O0OOl_dataout <= wire_ni0OiOOO_dataout WHEN niil00Ol = '1' ELSE ni0i1i0l; + wire_ni0O0OOO_dataout <= wire_ni0Ol11i_dataout AND niil00Ol; + wire_ni0O100i_dataout <= wire_nii1liiO_dataout WHEN niil010i = '1' ELSE wire_ni0O000l_dataout; + wire_ni0O100l_dataout <= wire_nii1lili_dataout WHEN niil010i = '1' ELSE wire_ni0O000O_dataout; + wire_ni0O100O_dataout <= wire_nii1lill_dataout WHEN niil010i = '1' ELSE wire_ni0O00ii_dataout; + wire_ni0O101i_dataout <= wire_nii1li0O_dataout WHEN niil010i = '1' ELSE wire_ni0O001l_dataout; + wire_ni0O101l_dataout <= wire_nii1liii_dataout WHEN niil010i = '1' ELSE wire_ni0O001O_dataout; + wire_ni0O101O_dataout <= wire_nii1liil_dataout WHEN niil010i = '1' ELSE wire_ni0O000i_dataout; + wire_ni0O10i_dataout <= nl101Oii WHEN niOO0liil = '1' ELSE ni0llOi; + wire_ni0O10ii_dataout <= wire_nii1lilO_dataout WHEN niil010i = '1' ELSE wire_ni0O00il_dataout; + wire_ni0O10il_dataout <= wire_nii1liOi_dataout WHEN niil010i = '1' ELSE wire_ni0O00iO_dataout; + wire_ni0O10iO_dataout <= wire_nii1liOl_dataout WHEN niil010i = '1' ELSE wire_ni0O00li_dataout; + wire_ni0O10l_dataout <= nl101Oil WHEN niOO0liil = '1' ELSE ni0llOl; + wire_ni0O10li_dataout <= wire_nii1liOO_dataout WHEN niil010i = '1' ELSE wire_ni0O00ll_dataout; + wire_ni0O10ll_dataout <= wire_nii1ll1i_dataout WHEN niil010i = '1' ELSE wire_ni0O00lO_dataout; + wire_ni0O10lO_dataout <= wire_nii1ll1l_dataout WHEN niil010i = '1' ELSE wire_ni0O00Oi_dataout; + wire_ni0O10O_dataout <= wire_ni0O1ii_dataout OR niOO0liil; + wire_ni0O10Oi_dataout <= wire_nii1ll1O_dataout WHEN niil010i = '1' ELSE wire_ni0O00Ol_dataout; + wire_ni0O10Ol_dataout <= wire_nii1ll0i_dataout WHEN niil010i = '1' ELSE wire_ni0O00OO_dataout; + wire_ni0O10OO_dataout <= wire_nii1ll0l_dataout WHEN niil010i = '1' ELSE wire_ni0O0i1i_dataout; + wire_ni0O110i_dataout <= wire_nii1l0li_dataout WHEN niil010i = '1' ELSE wire_ni0O010l_dataout; + wire_ni0O110l_dataout <= wire_nii1l0ll_dataout WHEN niil010i = '1' ELSE wire_ni0O010O_dataout; + wire_ni0O110O_dataout <= wire_nii1l0lO_dataout WHEN niil010i = '1' ELSE wire_ni0O01ii_dataout; + wire_ni0O111i_dataout <= wire_nii1l0ii_dataout WHEN niil010i = '1' ELSE wire_ni0O011l_dataout; + wire_ni0O111l_dataout <= wire_nii1l0il_dataout WHEN niil010i = '1' ELSE wire_ni0O011O_dataout; + wire_ni0O111O_dataout <= wire_nii1l0iO_dataout WHEN niil010i = '1' ELSE wire_ni0O010i_dataout; + wire_ni0O11i_dataout <= nl101O0i WHEN niOO0liil = '1' ELSE ni0llli; + wire_ni0O11ii_dataout <= wire_nii1l0Oi_dataout WHEN niil010i = '1' ELSE wire_ni0O01il_dataout; + wire_ni0O11il_dataout <= wire_ni0Oi1li_dataout WHEN niil010i = '1' ELSE wire_ni0O01iO_dataout; + wire_ni0O11iO_dataout <= wire_nii1l0Ol_dataout WHEN niil010i = '1' ELSE wire_ni0O01li_dataout; + wire_ni0O11l_dataout <= nl101O0l WHEN niOO0liil = '1' ELSE ni0llll; + wire_ni0O11li_dataout <= wire_nii1l0OO_dataout WHEN niil010i = '1' ELSE wire_ni0O01ll_dataout; + wire_ni0O11ll_dataout <= wire_nii1li1i_dataout WHEN niil010i = '1' ELSE wire_ni0O01lO_dataout; + wire_ni0O11lO_dataout <= wire_nii1li1l_dataout WHEN niil010i = '1' ELSE wire_ni0O01Oi_dataout; + wire_ni0O11O_dataout <= nl101O0O WHEN niOO0liil = '1' ELSE ni0lllO; + wire_ni0O11Oi_dataout <= wire_nii1li1O_dataout WHEN niil010i = '1' ELSE wire_ni0O01Ol_dataout; + wire_ni0O11Ol_dataout <= wire_nii1li0i_dataout WHEN niil010i = '1' ELSE wire_ni0O01OO_dataout; + wire_ni0O11OO_dataout <= wire_nii1li0l_dataout WHEN niil010i = '1' ELSE wire_ni0O001i_dataout; + wire_ni0O1i0i_dataout <= wire_nii1lliO_dataout WHEN niil010i = '1' ELSE wire_ni0O0i0l_dataout; + wire_ni0O1i0l_dataout <= wire_nii1llli_dataout WHEN niil010i = '1' ELSE wire_ni0O0i0O_dataout; + wire_ni0O1i0O_dataout <= wire_nii1llll_dataout WHEN niil010i = '1' ELSE wire_ni0O0iii_dataout; + wire_ni0O1i1i_dataout <= wire_nii1ll0O_dataout WHEN niil010i = '1' ELSE wire_ni0O0i1l_dataout; + wire_ni0O1i1l_dataout <= wire_nii1llii_dataout WHEN niil010i = '1' ELSE wire_ni0O0i1O_dataout; + wire_ni0O1i1O_dataout <= wire_nii1llil_dataout WHEN niil010i = '1' ELSE wire_ni0O0i0i_dataout; + wire_ni0O1ii_dataout <= ni0llOO AND NOT(niOO0liii); + wire_ni0O1iii_dataout <= wire_nii1lllO_dataout WHEN niil010i = '1' ELSE wire_ni0O0iil_dataout; + wire_ni0O1iil_dataout <= wire_nii1llOi_dataout WHEN niil010i = '1' ELSE wire_ni0O0iiO_dataout; + wire_ni0O1iiO_dataout <= wire_nii1llOl_dataout WHEN niil010i = '1' ELSE wire_ni0O0ili_dataout; + wire_ni0O1ili_dataout <= wire_nii1llOO_dataout WHEN niil010i = '1' ELSE wire_ni0O0ill_dataout; + wire_ni0O1ill_dataout <= wire_nii1lO1i_dataout WHEN niil010i = '1' ELSE wire_ni0O0ilO_dataout; + wire_ni0O1ilO_dataout <= wire_nii1lO1l_dataout WHEN niil010i = '1' ELSE wire_ni0O0iOi_dataout; + wire_ni0O1iOi_dataout <= wire_nii1lO1O_dataout WHEN niil010i = '1' ELSE wire_ni0O0iOl_dataout; + wire_ni0O1iOl_dataout <= wire_nii1lO0i_dataout WHEN niil010i = '1' ELSE wire_ni0O0iOO_dataout; + wire_ni0O1iOO_dataout <= wire_nii1lO0l_dataout WHEN niil010i = '1' ELSE wire_ni0O0l1i_dataout; + wire_ni0O1l0i_dataout <= wire_nii1lOiO_dataout WHEN niil010i = '1' ELSE wire_ni0O0l0l_dataout; + wire_ni0O1l0l_dataout <= wire_nii1lOli_dataout WHEN niil010i = '1' ELSE wire_ni0O0l0O_dataout; + wire_ni0O1l0O_dataout <= wire_nii1lOll_dataout WHEN niil010i = '1' ELSE wire_ni0O0lii_dataout; + wire_ni0O1l1i_dataout <= wire_nii1lO0O_dataout WHEN niil010i = '1' ELSE wire_ni0O0l1l_dataout; + wire_ni0O1l1l_dataout <= wire_nii1lOii_dataout WHEN niil010i = '1' ELSE wire_ni0O0l1O_dataout; + wire_ni0O1l1O_dataout <= wire_nii1lOil_dataout WHEN niil010i = '1' ELSE wire_ni0O0l0i_dataout; + wire_ni0O1lii_dataout <= wire_nii1lOlO_dataout WHEN niil010i = '1' ELSE wire_ni0O0lil_dataout; + wire_ni0O1lil_dataout <= wire_nii1lOOi_dataout WHEN niil010i = '1' ELSE wire_ni0O0liO_dataout; + wire_ni0O1liO_dataout <= wire_nii1lOOl_dataout WHEN niil010i = '1' ELSE wire_ni0O0lli_dataout; + wire_ni0O1ll_dataout <= wire_ni0O1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni0O1lli_dataout <= wire_nii1lOOO_dataout WHEN niil010i = '1' ELSE wire_ni0O0lll_dataout; + wire_ni0O1lll_dataout <= wire_nii1O11i_dataout WHEN niil010i = '1' ELSE wire_ni0O0llO_dataout; + wire_ni0O1llO_dataout <= wire_nii1O11l_dataout WHEN niil010i = '1' ELSE wire_ni0O0lOi_dataout; + wire_ni0O1lO_dataout <= niOOOi1i AND NOT(wire_niO01O0O_dataout); + wire_ni0O1lOi_dataout <= wire_nii1O11O_dataout WHEN niil010i = '1' ELSE wire_ni0O0lOl_dataout; + wire_ni0O1lOl_dataout <= wire_nii1O10i_dataout WHEN niil010i = '1' ELSE wire_ni0O0lOO_dataout; + wire_ni0O1lOO_dataout <= wire_nii1O10l_dataout WHEN niil010i = '1' ELSE wire_ni0O0O1i_dataout; + wire_ni0O1O0i_dataout <= wire_nii1O1iO_dataout WHEN niil010i = '1' ELSE wire_ni0O0O0l_dataout; + wire_ni0O1O0l_dataout <= wire_ni0OiOii_dataout WHEN niil010i = '1' ELSE wire_ni0O0O0O_dataout; + wire_ni0O1O0O_dataout <= wire_ni0OiOil_dataout WHEN niil010i = '1' ELSE wire_ni0O0Oii_dataout; + wire_ni0O1O1i_dataout <= wire_nii1O10O_dataout WHEN niil010i = '1' ELSE wire_ni0O0O1l_dataout; + wire_ni0O1O1l_dataout <= wire_nii1O1ii_dataout WHEN niil010i = '1' ELSE wire_ni0O0O1O_dataout; + wire_ni0O1O1O_dataout <= wire_nii1O1il_dataout WHEN niil010i = '1' ELSE wire_ni0O0O0i_dataout; + wire_ni0O1Oi_dataout <= wire_ni0O1Ol_dataout OR (wire_nl1000i_w_lg_ni0O1iO2324w(0) AND niOOOi1i); + wire_ni0O1Oii_dataout <= wire_ni0OiOiO_dataout WHEN niil010i = '1' ELSE wire_ni0O0Oil_dataout; + wire_ni0O1Oil_dataout <= wire_ni0OiOli_dataout WHEN niil010i = '1' ELSE wire_ni0O0OiO_dataout; + wire_ni0O1OiO_dataout <= wire_ni0OiOll_dataout WHEN niil010i = '1' ELSE wire_ni0O0Oli_dataout; + wire_ni0O1Ol_dataout <= ni0lO1l AND NOT(nlil1lO0O); + wire_ni0O1Oli_dataout <= wire_ni0OiOlO_dataout WHEN niil010i = '1' ELSE wire_ni0O0Oll_dataout; + wire_ni0O1Oll_dataout <= wire_ni0OiOOi_dataout WHEN niil010i = '1' ELSE wire_ni0O0OlO_dataout; + wire_ni0O1OlO_dataout <= wire_ni0OiOOl_dataout WHEN niil010i = '1' ELSE wire_ni0O0OOi_dataout; + wire_ni0O1OOi_dataout <= wire_nii1O1li_dataout WHEN niil010i = '1' ELSE wire_ni0O0OOl_dataout; + wire_ni0O1OOl_dataout <= wire_nii1O1ll_dataout WHEN niil010i = '1' ELSE wire_ni0O0OOO_dataout; + wire_ni0O1OOO_dataout <= wire_nii1O1lO_dataout WHEN niil010i = '1' ELSE wire_ni0Oi11i_dataout; + wire_ni0Oi00i_dataout <= wire_ni0Ol00l_dataout AND NOT(ni0i1i0i); + wire_ni0Oi00l_dataout <= wire_ni0Ol00O_dataout AND NOT(ni0i1i0i); + wire_ni0Oi00O_dataout <= wire_ni0Ol0ii_dataout AND NOT(ni0i1i0i); + wire_ni0Oi01i_dataout <= wire_ni0Ol01l_dataout AND NOT(ni0i1i0i); + wire_ni0Oi01l_dataout <= wire_ni0Ol01O_dataout AND NOT(ni0i1i0i); + wire_ni0Oi01O_dataout <= wire_ni0Ol00i_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0ii_dataout <= wire_ni0Ol0il_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0il_dataout <= wire_ni0Ol0iO_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0iO_dataout <= wire_ni0Ol0li_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0li_dataout <= wire_ni0Ol0ll_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0ll_dataout <= wire_ni0Ol0lO_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0lO_dataout <= wire_ni0Ol0Oi_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0Oi_dataout <= wire_ni0Ol0Ol_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0Ol_dataout <= wire_ni0Ol0OO_dataout AND NOT(ni0i1i0i); + wire_ni0Oi0OO_dataout <= wire_ni0Oli1i_dataout AND NOT(ni0i1i0i); + wire_ni0Oi10i_dataout <= wire_ni0Ol10l_dataout AND NOT(ni0i1i0i); + wire_ni0Oi10l_dataout <= wire_ni0Ol10O_dataout AND NOT(ni0i1i0i); + wire_ni0Oi10O_dataout <= wire_ni0Ol1ii_dataout AND NOT(ni0i1i0i); + wire_ni0Oi11i_dataout <= wire_ni0Ol11l_dataout AND niil00Ol; + wire_ni0Oi11l_dataout <= wire_ni0Ol11O_dataout AND niil00Ol; + wire_ni0Oi11O_dataout <= wire_ni0Ol10i_dataout AND NOT(ni0i1i0i); + wire_ni0Oi1ii_dataout <= wire_ni0Ol1il_dataout AND NOT(ni0i1i0i); + wire_ni0Oi1il_dataout <= wire_ni0Ol1iO_dataout AND NOT(ni0i1i0i); + wire_ni0Oi1iO_dataout <= ni11100O WHEN ni0i1i0i = '1' ELSE wire_ni0Ol1li_dataout; + wire_ni0Oi1li_dataout <= ni0i101l WHEN ni0i1i0i = '1' ELSE wire_ni0Ol1ll_dataout; + wire_ni0Oi1ll_dataout <= wire_ni0Ol1lO_dataout AND NOT(ni0i1i0i); + wire_ni0Oi1lO_dataout <= wire_ni0Ol1Oi_dataout AND NOT(ni0i1i0i); + wire_ni0Oi1Oi_dataout <= wire_ni0Ol1Ol_dataout AND NOT(ni0i1i0i); + wire_ni0Oi1Ol_dataout <= wire_ni0Ol1OO_dataout AND NOT(ni0i1i0i); + wire_ni0Oi1OO_dataout <= wire_ni0Ol01i_dataout AND NOT(ni0i1i0i); + wire_ni0Oii0i_dataout <= wire_ni0Oli0l_dataout AND NOT(ni0i1i0i); + wire_ni0Oii0l_dataout <= wire_ni0Oli0O_dataout AND NOT(ni0i1i0i); + wire_ni0Oii0O_dataout <= wire_ni0Oliii_dataout AND NOT(ni0i1i0i); + wire_ni0Oii1i_dataout <= wire_ni0Oli1l_dataout AND NOT(ni0i1i0i); + wire_ni0Oii1l_dataout <= wire_ni0Oli1O_dataout AND NOT(ni0i1i0i); + wire_ni0Oii1O_dataout <= wire_ni0Oli0i_dataout AND NOT(ni0i1i0i); + wire_ni0Oiiii_dataout <= wire_ni0Oliil_dataout AND NOT(ni0i1i0i); + wire_ni0Oiiil_dataout <= wire_ni0OliiO_dataout AND NOT(ni0i1i0i); + wire_ni0OiiiO_dataout <= wire_ni0Olili_dataout AND NOT(ni0i1i0i); + wire_ni0Oiili_dataout <= wire_ni0Olill_dataout AND NOT(ni0i1i0i); + wire_ni0Oiill_dataout <= wire_ni0OlilO_dataout AND NOT(ni0i1i0i); + wire_ni0OiilO_dataout <= wire_ni0OliOi_dataout AND NOT(ni0i1i0i); + wire_ni0OiiOi_dataout <= wire_ni0OliOl_dataout AND NOT(ni0i1i0i); + wire_ni0OiiOl_dataout <= wire_ni0OliOO_dataout AND NOT(ni0i1i0i); + wire_ni0OiiOO_dataout <= wire_ni0Oll1i_dataout AND NOT(ni0i1i0i); + wire_ni0Oil0i_dataout <= wire_ni0Oll0l_dataout AND NOT(ni0i1i0i); + wire_ni0Oil0l_dataout <= wire_ni0Oll0O_dataout AND NOT(ni0i1i0i); + wire_ni0Oil0O_dataout <= wire_ni0Ollii_dataout AND NOT(ni0i1i0i); + wire_ni0Oil1i_dataout <= wire_ni0Oll1l_dataout AND NOT(ni0i1i0i); + wire_ni0Oil1l_dataout <= wire_ni0Oll1O_dataout AND NOT(ni0i1i0i); + wire_ni0Oil1O_dataout <= wire_ni0Oll0i_dataout AND NOT(ni0i1i0i); + wire_ni0Oilii_dataout <= wire_ni0Ollil_dataout AND NOT(ni0i1i0i); + wire_ni0Oilil_dataout <= wire_ni0OlliO_dataout AND NOT(ni0i1i0i); + wire_ni0OiliO_dataout <= wire_ni0Ollli_dataout AND NOT(ni0i1i0i); + wire_ni0Oilli_dataout <= wire_ni0Ollll_dataout AND NOT(ni0i1i0i); + wire_ni0Oilll_dataout <= wire_ni0OlllO_dataout AND NOT(ni0i1i0i); + wire_ni0OillO_dataout <= wire_ni0OllOi_dataout AND NOT(ni0i1i0i); + wire_ni0OilOi_dataout <= wire_ni0OllOl_dataout AND NOT(ni0i1i0i); + wire_ni0OilOl_dataout <= n0OOOllO WHEN ni0i1i0i = '1' ELSE wire_ni0OllOO_dataout; + wire_ni0OilOO_dataout <= ni1111Ol WHEN ni0i1i0i = '1' ELSE wire_ni0OlO1i_dataout; + wire_ni0OiO0i_dataout <= ni11101O WHEN ni0i1i0i = '1' ELSE wire_ni0OlO0l_dataout; + wire_ni0OiO0l_dataout <= ni11100i WHEN ni0i1i0i = '1' ELSE wire_ni0OlO0O_dataout; + wire_ni0OiO0O_dataout <= ni11100l WHEN ni0i1i0i = '1' ELSE wire_ni0OlOii_dataout; + wire_ni0OiO1i_dataout <= ni1111OO WHEN ni0i1i0i = '1' ELSE wire_ni0OlO1l_dataout; + wire_ni0OiO1l_dataout <= ni11101i WHEN ni0i1i0i = '1' ELSE wire_ni0OlO1O_dataout; + wire_ni0OiO1O_dataout <= ni11101l WHEN ni0i1i0i = '1' ELSE wire_ni0OlO0i_dataout; + wire_ni0OiOii_dataout <= ni0i10ll WHEN ni0i1i0i = '1' ELSE wire_ni0OlOil_dataout; + wire_ni0OiOil_dataout <= ni0i10lO WHEN ni0i1i0i = '1' ELSE wire_ni0OlOiO_dataout; + wire_ni0OiOiO_dataout <= ni0i10Oi WHEN ni0i1i0i = '1' ELSE wire_ni0OlOli_dataout; + wire_ni0OiOli_dataout <= ni0i10Ol WHEN ni0i1i0i = '1' ELSE wire_ni0OlOll_dataout; + wire_ni0OiOll_dataout <= ni0i10OO WHEN ni0i1i0i = '1' ELSE wire_ni0OlOlO_dataout; + wire_ni0OiOlO_dataout <= ni0i1i1i WHEN ni0i1i0i = '1' ELSE wire_ni0OlOOi_dataout; + wire_ni0OiOOi_dataout <= ni0i1i1l WHEN ni0i1i0i = '1' ELSE wire_ni0OlOOl_dataout; + wire_ni0OiOOl_dataout <= ni0i1i1O WHEN ni0i1i0i = '1' ELSE wire_ni0OlOOO_dataout; + wire_ni0OiOOO_dataout <= wire_ni0OO11i_dataout AND NOT(ni0i1i0i); + wire_ni0Ol00i_dataout <= wire_ni0OO00i_dataout AND NOT(niOlOll0l); + wire_ni0Ol00l_dataout <= wire_ni0OO00l_dataout AND NOT(niOlOll0l); + wire_ni0Ol00O_dataout <= wire_ni0OO00O_dataout AND NOT(niOlOll0l); + wire_ni0Ol01i_dataout <= wire_ni0OO01i_dataout AND NOT(niOlOll0l); + wire_ni0Ol01l_dataout <= wire_ni0OO01l_dataout AND NOT(niOlOll0l); + wire_ni0Ol01O_dataout <= wire_ni0OO01O_dataout AND NOT(niOlOll0l); + wire_ni0Ol0ii_dataout <= wire_ni0OO0ii_dataout AND NOT(niOlOll0l); + wire_ni0Ol0il_dataout <= wire_ni0OO0il_dataout AND NOT(niOlOll0l); + wire_ni0Ol0iO_dataout <= wire_ni0OO0iO_dataout AND NOT(niOlOll0l); + wire_ni0Ol0li_dataout <= wire_ni0OO0li_dataout AND NOT(niOlOll0l); + wire_ni0Ol0ll_dataout <= wire_ni0OO0ll_dataout AND NOT(niOlOll0l); + wire_ni0Ol0lO_dataout <= wire_ni0OO0lO_dataout AND NOT(niOlOll0l); + wire_ni0Ol0Oi_dataout <= wire_ni0OO0Oi_dataout AND NOT(niOlOll0l); + wire_ni0Ol0Ol_dataout <= wire_ni0OO0Ol_dataout AND NOT(niOlOll0l); + wire_ni0Ol0OO_dataout <= wire_ni0OO0OO_dataout AND NOT(niOlOll0l); + wire_ni0Ol10i_dataout <= wire_ni0OO10l_dataout AND NOT(niOlOll0l); + wire_ni0Ol10l_dataout <= wire_ni0OO10O_dataout AND NOT(niOlOll0l); + wire_ni0Ol10O_dataout <= wire_ni0OO1ii_dataout AND NOT(niOlOll0l); + wire_ni0Ol11i_dataout <= wire_ni0OO11l_dataout AND NOT(ni0i1i0i); + wire_ni0Ol11l_dataout <= wire_ni0OO11O_dataout OR ni0i1i0i; + wire_ni0Ol11O_dataout <= wire_ni0OO10i_dataout OR ni0i1i0i; + wire_ni0Ol1ii_dataout <= wire_ni0OO1il_dataout AND NOT(niOlOll0l); + wire_ni0Ol1il_dataout <= wire_ni0OO1iO_dataout AND NOT(niOlOll0l); + wire_ni0Ol1iO_dataout <= wire_ni0OO1li_dataout AND NOT(niOlOll0l); + wire_ni0Ol1li_dataout <= wire_ni0OO1ll_dataout AND NOT(niOlOll0l); + wire_ni0Ol1ll_dataout <= ni11100O WHEN niOlOll0l = '1' ELSE ni0i1iOi; + wire_ni0Ol1lO_dataout <= wire_ni0OO1lO_dataout AND NOT(niOlOll0l); + wire_ni0Ol1Oi_dataout <= wire_ni0OO1Oi_dataout AND NOT(niOlOll0l); + wire_ni0Ol1Ol_dataout <= wire_ni0OO1Ol_dataout AND NOT(niOlOll0l); + wire_ni0Ol1OO_dataout <= wire_ni0OO1OO_dataout AND NOT(niOlOll0l); + wire_ni0Oli0i_dataout <= wire_ni0OOi0i_dataout AND NOT(niOlOll0l); + wire_ni0Oli0l_dataout <= wire_ni0OOi0l_dataout AND NOT(niOlOll0l); + wire_ni0Oli0O_dataout <= wire_ni0OOi0O_dataout AND NOT(niOlOll0l); + wire_ni0Oli1i_dataout <= wire_ni0OOi1i_dataout AND NOT(niOlOll0l); + wire_ni0Oli1l_dataout <= wire_ni0OOi1l_dataout AND NOT(niOlOll0l); + wire_ni0Oli1O_dataout <= wire_ni0OOi1O_dataout AND NOT(niOlOll0l); + wire_ni0Olii_dataout <= wire_nii11Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0Oliii_dataout <= wire_ni0OOiii_dataout AND NOT(niOlOll0l); + wire_ni0Oliil_dataout <= wire_ni0OOiil_dataout AND NOT(niOlOll0l); + wire_ni0OliiO_dataout <= wire_ni0OOiiO_dataout AND NOT(niOlOll0l); + wire_ni0Olil_dataout <= ni0O01l AND NOT(wire_niO01l0O_dataout); + wire_ni0Olili_dataout <= wire_ni0OOili_dataout AND NOT(niOlOll0l); + wire_ni0Olill_dataout <= wire_ni0OOill_dataout AND NOT(niOlOll0l); + wire_ni0OlilO_dataout <= wire_ni0OOilO_dataout AND NOT(niOlOll0l); + wire_ni0OliO_dataout <= niOliOii AND NOT(wire_niO01l0O_dataout); + wire_ni0OliOi_dataout <= wire_ni0OOiOi_dataout AND NOT(niOlOll0l); + wire_ni0OliOl_dataout <= wire_ni0OOiOl_dataout AND NOT(niOlOll0l); + wire_ni0OliOO_dataout <= wire_ni0OOiOO_dataout AND NOT(niOlOll0l); + wire_ni0Oll0i_dataout <= wire_ni0OOl0i_dataout AND NOT(niOlOll0l); + wire_ni0Oll0l_dataout <= wire_ni0OOl0l_dataout AND NOT(niOlOll0l); + wire_ni0Oll0O_dataout <= wire_ni0OOl0O_dataout AND NOT(niOlOll0l); + wire_ni0Oll1i_dataout <= wire_ni0OOl1i_dataout AND NOT(niOlOll0l); + wire_ni0Oll1l_dataout <= wire_ni0OOl1l_dataout AND NOT(niOlOll0l); + wire_ni0Oll1O_dataout <= wire_ni0OOl1O_dataout AND NOT(niOlOll0l); + wire_ni0Olli_dataout <= niOO0liiO AND NOT(wire_niO01l0O_dataout); + wire_ni0Ollii_dataout <= wire_ni0OOlii_dataout AND NOT(niOlOll0l); + wire_ni0Ollil_dataout <= wire_ni0OOlil_dataout AND NOT(niOlOll0l); + wire_ni0OlliO_dataout <= wire_ni0OOliO_dataout AND NOT(niOlOll0l); + wire_ni0Olll_dataout <= wire_nii11Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0Ollli_dataout <= wire_ni0OOlli_dataout AND NOT(niOlOll0l); + wire_ni0Ollll_dataout <= wire_ni0OOlll_dataout AND NOT(niOlOll0l); + wire_ni0OlllO_dataout <= wire_ni0OOllO_dataout AND NOT(niOlOll0l); + wire_ni0OllO_dataout <= wire_nii11OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OllOi_dataout <= wire_ni0OOlOi_dataout AND NOT(niOlOll0l); + wire_ni0OllOl_dataout <= wire_ni0OOlOl_dataout AND NOT(niOlOll0l); + wire_ni0OllOO_dataout <= wire_ni0OOlOO_dataout AND NOT(niOlOll0l); + wire_ni0OlO0i_dataout <= wire_ni0OOO0i_dataout AND NOT(niOlOll0l); + wire_ni0OlO0l_dataout <= wire_ni0OOO0l_dataout AND NOT(niOlOll0l); + wire_ni0OlO0O_dataout <= wire_ni0OOO0O_dataout AND NOT(niOlOll0l); + wire_ni0OlO1i_dataout <= wire_ni0OOO1i_dataout AND NOT(niOlOll0l); + wire_ni0OlO1l_dataout <= wire_ni0OOO1l_dataout AND NOT(niOlOll0l); + wire_ni0OlO1O_dataout <= wire_ni0OOO1O_dataout AND NOT(niOlOll0l); + wire_ni0OlOi_dataout <= wire_nii101i_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OlOii_dataout <= wire_ni0OOOii_dataout AND NOT(niOlOll0l); + wire_ni0OlOil_dataout <= n0OOOllO WHEN niOlOll0l = '1' ELSE ni0i00li; + wire_ni0OlOiO_dataout <= ni1111Ol WHEN niOlOll0l = '1' ELSE ni0i00ll; + wire_ni0OlOl_dataout <= wire_nii101l_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OlOli_dataout <= ni1111OO WHEN niOlOll0l = '1' ELSE ni0i00lO; + wire_ni0OlOll_dataout <= ni11101i WHEN niOlOll0l = '1' ELSE ni0i00Oi; + wire_ni0OlOlO_dataout <= ni11101l WHEN niOlOll0l = '1' ELSE ni0i00Ol; + wire_ni0OlOO_dataout <= wire_nii101O_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OlOOi_dataout <= ni11101O WHEN niOlOll0l = '1' ELSE ni0i00OO; + wire_ni0OlOOl_dataout <= ni11100i WHEN niOlOll0l = '1' ELSE ni0i0i1i; + wire_ni0OlOOO_dataout <= ni11100l WHEN niOlOll0l = '1' ELSE ni0i0i1l; + wire_ni0OO00i_dataout <= ni0i1l0O WHEN niOlOll0O = '1' ELSE wire_nii111ll_dataout; + wire_ni0OO00l_dataout <= ni0i1lii WHEN niOlOll0O = '1' ELSE wire_nii111lO_dataout; + wire_ni0OO00O_dataout <= ni0i1lil WHEN niOlOll0O = '1' ELSE wire_nii111Oi_dataout; + wire_ni0OO01i_dataout <= ni0i1l1O WHEN niOlOll0O = '1' ELSE wire_nii111il_dataout; + wire_ni0OO01l_dataout <= ni0i1l0i WHEN niOlOll0O = '1' ELSE wire_nii111iO_dataout; + wire_ni0OO01O_dataout <= ni0i1l0l WHEN niOlOll0O = '1' ELSE wire_nii111li_dataout; + wire_ni0OO0i_dataout <= wire_nii10ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OO0ii_dataout <= ni0i1liO WHEN niOlOll0O = '1' ELSE wire_nii111Ol_dataout; + wire_ni0OO0il_dataout <= ni0i1lli WHEN niOlOll0O = '1' ELSE wire_nii111OO_dataout; + wire_ni0OO0iO_dataout <= ni0i1lll WHEN niOlOll0O = '1' ELSE wire_nii1101i_dataout; + wire_ni0OO0l_dataout <= wire_nii10il_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OO0li_dataout <= ni0i1llO WHEN niOlOll0O = '1' ELSE wire_nii1101l_dataout; + wire_ni0OO0ll_dataout <= ni0i1lOi WHEN niOlOll0O = '1' ELSE wire_nii1101O_dataout; + wire_ni0OO0lO_dataout <= ni0i1lOl WHEN niOlOll0O = '1' ELSE wire_nii1100i_dataout; + wire_ni0OO0O_dataout <= wire_nii10iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OO0Oi_dataout <= ni0i1lOO WHEN niOlOll0O = '1' ELSE wire_nii1100l_dataout; + wire_ni0OO0Ol_dataout <= ni0i1O1i WHEN niOlOll0O = '1' ELSE wire_nii1100O_dataout; + wire_ni0OO0OO_dataout <= ni0i1O1l WHEN niOlOll0O = '1' ELSE wire_nii110ii_dataout; + wire_ni0OO10i_dataout <= wire_ni0OOOli_dataout OR niOlOll0l; + wire_ni0OO10l_dataout <= ni0i1i0O WHEN niOlOll0O = '1' ELSE wire_ni0OOOlO_dataout; + wire_ni0OO10O_dataout <= ni0i1iii WHEN niOlOll0O = '1' ELSE wire_ni0OOOOi_dataout; + wire_ni0OO11i_dataout <= wire_ni0OOOll_dataout AND NOT(niOlOll0l); + wire_ni0OO11l_dataout <= wire_ni0OOOil_dataout OR niOlOll0l; + wire_ni0OO11O_dataout <= wire_ni0OOOiO_dataout OR niOlOll0l; + wire_ni0OO1i_dataout <= wire_nii100i_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OO1ii_dataout <= ni0i1iil WHEN niOlOll0O = '1' ELSE wire_ni0OOOOl_dataout; + wire_ni0OO1il_dataout <= ni0i1iiO WHEN niOlOll0O = '1' ELSE wire_ni0OOOOO_dataout; + wire_ni0OO1iO_dataout <= ni0i1ili WHEN niOlOll0O = '1' ELSE wire_nii1111i_dataout; + wire_ni0OO1l_dataout <= wire_nii100l_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OO1li_dataout <= ni0i1ill WHEN niOlOll0O = '1' ELSE wire_nii1111l_dataout; + wire_ni0OO1ll_dataout <= ni0i1ilO WHEN niOlOll0O = '1' ELSE wire_nii1111O_dataout; + wire_ni0OO1lO_dataout <= ni0i1iOl WHEN niOlOll0O = '1' ELSE wire_nii1110i_dataout; + wire_ni0OO1O_dataout <= wire_nii100O_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OO1Oi_dataout <= ni0i1iOO WHEN niOlOll0O = '1' ELSE wire_nii1110l_dataout; + wire_ni0OO1Ol_dataout <= ni0i1l1i WHEN niOlOll0O = '1' ELSE wire_nii1110O_dataout; + wire_ni0OO1OO_dataout <= ni0i1l1l WHEN niOlOll0O = '1' ELSE wire_nii111ii_dataout; + wire_ni0OOi0i_dataout <= ni0i1O0O WHEN niOlOll0O = '1' ELSE wire_nii110ll_dataout; + wire_ni0OOi0l_dataout <= ni0i1Oii WHEN niOlOll0O = '1' ELSE wire_nii110lO_dataout; + wire_ni0OOi0O_dataout <= ni0i1Oil WHEN niOlOll0O = '1' ELSE wire_nii110Oi_dataout; + wire_ni0OOi1i_dataout <= ni0i1O1O WHEN niOlOll0O = '1' ELSE wire_nii110il_dataout; + wire_ni0OOi1l_dataout <= ni0i1O0i WHEN niOlOll0O = '1' ELSE wire_nii110iO_dataout; + wire_ni0OOi1O_dataout <= ni0i1O0l WHEN niOlOll0O = '1' ELSE wire_nii110li_dataout; + wire_ni0OOii_dataout <= wire_nii10li_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOiii_dataout <= ni0i1OiO WHEN niOlOll0O = '1' ELSE wire_nii110Ol_dataout; + wire_ni0OOiil_dataout <= ni0i1Oli WHEN niOlOll0O = '1' ELSE wire_nii110OO_dataout; + wire_ni0OOiiO_dataout <= ni0i1Oll WHEN niOlOll0O = '1' ELSE wire_nii11i1i_dataout; + wire_ni0OOil_dataout <= wire_nii10ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOili_dataout <= ni0i1OlO WHEN niOlOll0O = '1' ELSE wire_nii11i1l_dataout; + wire_ni0OOill_dataout <= ni0i1OOi WHEN niOlOll0O = '1' ELSE wire_nii11i1O_dataout; + wire_ni0OOilO_dataout <= ni0i1OOl WHEN niOlOll0O = '1' ELSE wire_nii11i0i_dataout; + wire_ni0OOiO_dataout <= wire_nii10lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOiOi_dataout <= ni0i1OOO WHEN niOlOll0O = '1' ELSE wire_nii11i0l_dataout; + wire_ni0OOiOl_dataout <= ni0i011i WHEN niOlOll0O = '1' ELSE wire_nii11i0O_dataout; + wire_ni0OOiOO_dataout <= ni0i011l WHEN niOlOll0O = '1' ELSE wire_nii11iii_dataout; + wire_ni0OOl0i_dataout <= ni0i010O WHEN niOlOll0O = '1' ELSE wire_nii11ill_dataout; + wire_ni0OOl0l_dataout <= ni0i01ii WHEN niOlOll0O = '1' ELSE wire_nii11ilO_dataout; + wire_ni0OOl0O_dataout <= ni0i01il WHEN niOlOll0O = '1' ELSE wire_nii11iOi_dataout; + wire_ni0OOl1i_dataout <= ni0i011O WHEN niOlOll0O = '1' ELSE wire_nii11iil_dataout; + wire_ni0OOl1l_dataout <= ni0i010i WHEN niOlOll0O = '1' ELSE wire_nii11iiO_dataout; + wire_ni0OOl1O_dataout <= ni0i010l WHEN niOlOll0O = '1' ELSE wire_nii11ili_dataout; + wire_ni0OOli_dataout <= wire_nii10Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOlii_dataout <= ni0i01iO WHEN niOlOll0O = '1' ELSE wire_nii11iOl_dataout; + wire_ni0OOlil_dataout <= ni0i01li WHEN niOlOll0O = '1' ELSE wire_nii11iOO_dataout; + wire_ni0OOliO_dataout <= ni0i01ll WHEN niOlOll0O = '1' ELSE wire_nii11l1i_dataout; + wire_ni0OOll_dataout <= wire_nii10Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOlli_dataout <= ni0i01lO WHEN niOlOll0O = '1' ELSE wire_nii11l1l_dataout; + wire_ni0OOlll_dataout <= ni0i01Oi WHEN niOlOll0O = '1' ELSE wire_nii11l1O_dataout; + wire_ni0OOllO_dataout <= ni0i01Ol WHEN niOlOll0O = '1' ELSE wire_nii11l0i_dataout; + wire_ni0OOlO_dataout <= wire_nii10OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOlOi_dataout <= ni0i01OO WHEN niOlOll0O = '1' ELSE wire_nii11l0l_dataout; + wire_ni0OOlOl_dataout <= ni0i001i WHEN niOlOll0O = '1' ELSE wire_nii11l0O_dataout; + wire_ni0OOlOO_dataout <= ni0i001l WHEN niOlOll0O = '1' ELSE wire_nii11lii_dataout; + wire_ni0OOO0i_dataout <= ni0i000O WHEN niOlOll0O = '1' ELSE wire_nii11lll_dataout; + wire_ni0OOO0l_dataout <= ni0i00ii WHEN niOlOll0O = '1' ELSE wire_nii11llO_dataout; + wire_ni0OOO0O_dataout <= ni0i00il WHEN niOlOll0O = '1' ELSE wire_nii11lOi_dataout; + wire_ni0OOO1i_dataout <= ni0i001O WHEN niOlOll0O = '1' ELSE wire_nii11lil_dataout; + wire_ni0OOO1l_dataout <= ni0i000i WHEN niOlOll0O = '1' ELSE wire_nii11liO_dataout; + wire_ni0OOO1O_dataout <= ni0i000l WHEN niOlOll0O = '1' ELSE wire_nii11lli_dataout; + wire_ni0OOOi_dataout <= wire_nii1i1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOOii_dataout <= ni0i00iO WHEN niOlOll0O = '1' ELSE wire_nii11lOl_dataout; + wire_ni0OOOil_dataout <= ni0i0i1O WHEN niOlOll0O = '1' ELSE wire_nii1l00l_o(1); + wire_ni0OOOiO_dataout <= ni0i0i0i WHEN niOlOll0O = '1' ELSE wire_nii1l00l_o(2); + wire_ni0OOOl_dataout <= wire_nii1i1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOOli_dataout <= ni0i0i0l WHEN niOlOll0O = '1' ELSE wire_nii1l00l_o(3); + wire_ni0OOOll_dataout <= wire_w_lg_niOlOll1i10154w(0) WHEN niOlOll0O = '1' ELSE wire_nii11lOO_dataout; + wire_ni0OOOlO_dataout <= ni0i1i0O WHEN niOlOlili = '1' ELSE wire_nii11O1i_dataout; + wire_ni0OOOO_dataout <= wire_nii1i1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni0OOOOi_dataout <= ni0i1iii WHEN niOlOlili = '1' ELSE wire_nii11O1l_dataout; + wire_ni0OOOOl_dataout <= ni0i1iil WHEN niOlOlili = '1' ELSE wire_nii11O1O_dataout; + wire_ni0OOOOO_dataout <= ni0i1iiO WHEN niOlOlili = '1' ELSE wire_nii11O0i_dataout; + wire_ni10000i_dataout <= ni101O0O AND NOT(niOlOl0Ol); + wire_ni10000l_dataout <= ni101Oii AND NOT(niOlOl0Ol); + wire_ni10000O_dataout <= ni101Oil AND NOT(niOlOl0Ol); + wire_ni10001i_dataout <= wire_nii0OOlO_dataout WHEN niOlOi1ll = '1' ELSE wire_ni1000li_dataout; + wire_ni10001l_dataout <= wire_nii0OOOi_dataout WHEN niOlOi1ll = '1' ELSE wire_ni1000ll_dataout; + wire_ni10001O_dataout <= ni1000lO AND NOT(niOlOl0Ol); + wire_ni1000ii_dataout <= ni101OiO AND NOT(niOlOl0Ol); + wire_ni1000il_dataout <= ni101Oli AND NOT(niOlOl0Ol); + wire_ni1000iO_dataout <= ni101Oll AND NOT(niOlOl0Ol); + wire_ni1000li_dataout <= ni101OlO AND NOT(niOlOl0Ol); + wire_ni1000ll_dataout <= ni101OOi AND NOT(niOlOl0Ol); + wire_ni10010i_dataout <= wire_ni1001Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10010l_dataout <= wire_ni1001Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10010O_dataout <= wire_ni1001OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10011i_dataout <= wire_ni1001li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10011l_dataout <= wire_ni1001ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10011O_dataout <= wire_ni1001lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1001ii_dataout <= wire_ni10001i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1001il_dataout <= wire_ni10001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1001iO_dataout <= wire_nii0OO0l_dataout WHEN niOlOi1ll = '1' ELSE wire_ni10001O_dataout; + wire_ni1001li_dataout <= wire_nii0OO0O_dataout WHEN niOlOi1ll = '1' ELSE wire_ni10000i_dataout; + wire_ni1001ll_dataout <= wire_nii0OOii_dataout WHEN niOlOi1ll = '1' ELSE wire_ni10000l_dataout; + wire_ni1001lO_dataout <= wire_nii0OOil_dataout WHEN niOlOi1ll = '1' ELSE wire_ni10000O_dataout; + wire_ni1001Oi_dataout <= wire_nii0OOiO_dataout WHEN niOlOi1ll = '1' ELSE wire_ni1000ii_dataout; + wire_ni1001Ol_dataout <= wire_nii0OOli_dataout WHEN niOlOi1ll = '1' ELSE wire_ni1000il_dataout; + wire_ni1001OO_dataout <= wire_nii0OOll_dataout WHEN niOlOi1ll = '1' ELSE wire_ni1000iO_dataout; + wire_ni100iii_dataout <= wire_ni100l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100iil_dataout <= wire_ni100l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100iiO_dataout <= wire_ni100l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100ili_dataout <= wire_ni100l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100ill_dataout <= wire_ni100l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100ilO_dataout <= wire_ni100l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100iOi_dataout <= wire_ni100lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100iOl_dataout <= wire_ni100lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100iOO_dataout <= wire_ni100liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni100l0i_dataout <= wire_nii0OOil_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100lOi_dataout; + wire_ni100l0l_dataout <= wire_nii0OOiO_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100lOl_dataout; + wire_ni100l0O_dataout <= wire_nii0OOli_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100lOO_dataout; + wire_ni100l1i_dataout <= wire_nii0OO0l_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100lli_dataout; + wire_ni100l1l_dataout <= wire_nii0OO0O_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100lll_dataout; + wire_ni100l1O_dataout <= wire_nii0OOii_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100llO_dataout; + wire_ni100lii_dataout <= wire_nii0OOll_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100O1i_dataout; + wire_ni100lil_dataout <= wire_nii0OOlO_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100O1l_dataout; + wire_ni100liO_dataout <= wire_nii0OOOi_dataout WHEN niOlO0OOl = '1' ELSE wire_ni100O1O_dataout; + wire_ni100lli_dataout <= ni1000lO WHEN niOlOl0Ol = '1' ELSE ni101OOl; + wire_ni100lll_dataout <= ni101O0O WHEN niOlOl0Ol = '1' ELSE ni1000Oi; + wire_ni100llO_dataout <= ni101Oii WHEN niOlOl0Ol = '1' ELSE ni1000Ol; + wire_ni100lOi_dataout <= ni101Oil WHEN niOlOl0Ol = '1' ELSE ni1000OO; + wire_ni100lOl_dataout <= ni101OiO WHEN niOlOl0Ol = '1' ELSE ni100i1i; + wire_ni100lOO_dataout <= ni101Oli WHEN niOlOl0Ol = '1' ELSE ni100i1l; + wire_ni100O1i_dataout <= ni101Oll WHEN niOlOl0Ol = '1' ELSE ni100i1O; + wire_ni100O1l_dataout <= ni101OlO WHEN niOlOl0Ol = '1' ELSE ni100i0i; + wire_ni100O1O_dataout <= ni101OOi WHEN niOlOl0Ol = '1' ELSE ni100i0l; + wire_ni10100i_dataout <= ni11O0ll WHEN niOlOl0Ol = '1' ELSE ni11OO0O; + wire_ni10100l_dataout <= ni11O0lO WHEN niOlOl0Ol = '1' ELSE ni11OOii; + wire_ni10100O_dataout <= ni11O0Oi WHEN niOlOl0Ol = '1' ELSE ni11OOil; + wire_ni10101i_dataout <= wire_niii10ii_dataout WHEN niOlO0Oil = '1' ELSE wire_ni1010li_dataout; + wire_ni10101l_dataout <= wire_niii10il_dataout WHEN niOlO0Oil = '1' ELSE wire_ni1010ll_dataout; + wire_ni10101O_dataout <= ni11lOiO WHEN niOlOl0Ol = '1' ELSE ni11Oi0i; + wire_ni1010i_dataout <= ni11i0i WHEN ((((NOT (niOO0ilOi XOR niOO0illl)) AND (NOT (niOO0ilOl XOR niOO0illO))) AND (NOT (niOO0iO1O XOR niOO0ilOO))) AND (NOT (ni11liO XOR ni11l0l))) = '1' ELSE wire_ni1010l_o; + wire_ni1010ii_dataout <= ni11O0Ol WHEN niOlOl0Ol = '1' ELSE ni11OOiO; + wire_ni1010il_dataout <= ni11O0OO WHEN niOlOl0Ol = '1' ELSE ni11OOli; + wire_ni1010iO_dataout <= ni11Oi1i WHEN niOlOl0Ol = '1' ELSE ni11OOll; + wire_ni1010li_dataout <= ni11Oi1l WHEN niOlOl0Ol = '1' ELSE ni11OOlO; + wire_ni1010ll_dataout <= ni11Oi1O WHEN niOlOl0Ol = '1' ELSE ni11OOOi; + wire_ni10110i_dataout <= wire_ni1011Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10110l_dataout <= wire_ni1011Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10110O_dataout <= wire_ni1011OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10111i_dataout <= wire_ni1011li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10111l_dataout <= wire_ni1011ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10111O_dataout <= wire_ni1011lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1011i_dataout <= niOO0iO0l AND NOT(wire_niO01O0O_dataout); + wire_ni1011ii_dataout <= wire_ni10101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1011il_dataout <= wire_ni10101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1011iO_dataout <= wire_niii11OO_dataout WHEN niOlO0Oil = '1' ELSE wire_ni10101O_dataout; + wire_ni1011l_dataout <= niOO0iO1l AND NOT(wire_niO01O0O_dataout); + wire_ni1011li_dataout <= wire_niii101i_dataout WHEN niOlO0Oil = '1' ELSE wire_ni10100i_dataout; + wire_ni1011ll_dataout <= wire_niii101l_dataout WHEN niOlO0Oil = '1' ELSE wire_ni10100l_dataout; + wire_ni1011lO_dataout <= wire_niii101O_dataout WHEN niOlO0Oil = '1' ELSE wire_ni10100O_dataout; + wire_ni1011O_dataout <= niOO0iO1i AND NOT(wire_niO01O0O_dataout); + wire_ni1011Oi_dataout <= wire_niii100i_dataout WHEN niOlO0Oil = '1' ELSE wire_ni1010ii_dataout; + wire_ni1011Ol_dataout <= wire_niii100l_dataout WHEN niOlO0Oil = '1' ELSE wire_ni1010il_dataout; + wire_ni1011OO_dataout <= wire_niii100O_dataout WHEN niOlO0Oil = '1' ELSE wire_ni1010iO_dataout; + wire_ni101i0l_dataout <= niOlO0OiO AND NOT(wire_niO01lOO_dataout); + wire_ni101i0O_dataout <= wire_ni101ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni101iii_dataout <= wire_ni101iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni101iil_dataout <= wire_ni101iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni101iiO_dataout <= wire_ni101iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni101ilO_dataout <= wire_ni101l1i_dataout AND NOT(niOlOOi0i); + wire_ni101iOi_dataout <= wire_ni101l1l_dataout AND NOT(niOlOOi0i); + wire_ni101iOl_dataout <= wire_ni101l1O_dataout AND NOT(niOlOOi0i); + wire_ni101iOO_dataout <= wire_ni101l0i_dataout AND NOT(niOlOOi0i); + wire_ni101l0i_dataout <= wire_ni101lll_o(3) WHEN niOlO0OOi = '1' ELSE wire_ni101lil_dataout; + wire_ni101l0l_dataout <= ni101i1i OR niOlO0OlO; + wire_ni101l0O_dataout <= wire_ni101liO_o(0) WHEN niOlO0OlO = '1' ELSE ni101i1l; + wire_ni101l1i_dataout <= wire_w_lg_niOlO0Oll11359w(0) WHEN niOlO0OOi = '1' ELSE wire_ni101l0l_dataout; + wire_ni101l1l_dataout <= wire_ni101lll_o(1) WHEN niOlO0OOi = '1' ELSE wire_ni101l0O_dataout; + wire_ni101l1O_dataout <= wire_ni101lll_o(2) WHEN niOlO0OOi = '1' ELSE wire_ni101lii_dataout; + wire_ni101lii_dataout <= wire_ni101liO_o(1) WHEN niOlO0OlO = '1' ELSE ni101i1O; + wire_ni101lil_dataout <= wire_ni101liO_o(2) WHEN niOlO0OlO = '1' ELSE ni101i0i; + wire_ni101OOO_dataout <= wire_ni1001iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i00i_dataout <= wire_nii0OOOi_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i0Oi_dataout; + wire_ni10i00l_dataout <= ni101OOl WHEN niOlOl0Ol = '1' ELSE ni100i0O; + wire_ni10i00O_dataout <= ni1000Oi WHEN niOlOl0Ol = '1' ELSE ni100Oil; + wire_ni10i01i_dataout <= wire_nii0OOli_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i0li_dataout; + wire_ni10i01l_dataout <= wire_nii0OOll_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i0ll_dataout; + wire_ni10i01O_dataout <= wire_nii0OOlO_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i0lO_dataout; + wire_ni10i0ii_dataout <= ni1000Ol WHEN niOlOl0Ol = '1' ELSE ni100OiO; + wire_ni10i0il_dataout <= ni1000OO WHEN niOlOl0Ol = '1' ELSE ni100Oli; + wire_ni10i0iO_dataout <= ni100i1i WHEN niOlOl0Ol = '1' ELSE ni100Oll; + wire_ni10i0li_dataout <= ni100i1l WHEN niOlOl0Ol = '1' ELSE ni100OlO; + wire_ni10i0ll_dataout <= ni100i1O WHEN niOlOl0Ol = '1' ELSE ni100OOi; + wire_ni10i0lO_dataout <= ni100i0i WHEN niOlOl0Ol = '1' ELSE ni100OOl; + wire_ni10i0Oi_dataout <= ni100i0l WHEN niOlOl0Ol = '1' ELSE ni100OOO; + wire_ni10i10i_dataout <= wire_ni10i1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i10l_dataout <= wire_ni10i1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i10O_dataout <= wire_ni10i1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i11l_dataout <= wire_ni10i1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i11O_dataout <= wire_ni10i1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i1ii_dataout <= wire_ni10i01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i1il_dataout <= wire_ni10i01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i1iO_dataout <= wire_ni10i01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i1li_dataout <= wire_ni10i00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10i1ll_dataout <= wire_nii0OO0l_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i00l_dataout; + wire_ni10i1lO_dataout <= wire_nii0OO0O_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i00O_dataout; + wire_ni10i1Oi_dataout <= wire_nii0OOii_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i0ii_dataout; + wire_ni10i1Ol_dataout <= wire_nii0OOil_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i0il_dataout; + wire_ni10i1OO_dataout <= wire_nii0OOiO_dataout WHEN niOlO0OOO = '1' ELSE wire_ni10i0iO_dataout; + wire_ni10iil_dataout <= ni11l0O AND NOT(wire_niO01l0O_dataout); + wire_ni10iilO_dataout <= wire_ni10il0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10iiO_dataout <= ni11lii AND NOT(wire_niO01l0O_dataout); + wire_ni10iiOi_dataout <= wire_ni10ilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10iiOl_dataout <= wire_ni10ilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10iiOO_dataout <= wire_ni10iliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10il0i_dataout <= wire_ni10ilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10il0l_dataout <= wire_ni10ilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10il0O_dataout <= wire_nii0OO0l_dataout WHEN niOlOi11l = '1' ELSE wire_ni10ilOO_dataout; + wire_ni10il1i_dataout <= wire_ni10illi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10il1l_dataout <= wire_ni10illl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10il1O_dataout <= wire_ni10illO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10ili_dataout <= ni11lil AND NOT(wire_niO01l0O_dataout); + wire_ni10ilii_dataout <= wire_nii0OO0O_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iO1i_dataout; + wire_ni10ilil_dataout <= wire_nii0OOii_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iO1l_dataout; + wire_ni10iliO_dataout <= wire_nii0OOil_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iO1O_dataout; + wire_ni10ill_dataout <= ni11liO AND NOT(wire_niO01l0O_dataout); + wire_ni10illi_dataout <= wire_nii0OOiO_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iO0i_dataout; + wire_ni10illl_dataout <= wire_nii0OOli_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iO0l_dataout; + wire_ni10illO_dataout <= wire_nii0OOll_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iO0O_dataout; + wire_ni10ilOi_dataout <= wire_nii0OOlO_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iOii_dataout; + wire_ni10ilOl_dataout <= wire_nii0OOOi_dataout WHEN niOlOi11l = '1' ELSE wire_ni10iOil_dataout; + wire_ni10ilOO_dataout <= ni100i0O WHEN niOlOl0Ol = '1' ELSE ni10i11i; + wire_ni10iO0i_dataout <= ni100Oll WHEN niOlOl0Ol = '1' ELSE ni10ii0O; + wire_ni10iO0l_dataout <= ni100OlO WHEN niOlOl0Ol = '1' ELSE ni10iiii; + wire_ni10iO0O_dataout <= ni100OOi WHEN niOlOl0Ol = '1' ELSE ni10iiil; + wire_ni10iO1i_dataout <= ni100Oil WHEN niOlOl0Ol = '1' ELSE ni10ii1O; + wire_ni10iO1l_dataout <= ni100OiO WHEN niOlOl0Ol = '1' ELSE ni10ii0i; + wire_ni10iO1O_dataout <= ni100Oli WHEN niOlOl0Ol = '1' ELSE ni10ii0l; + wire_ni10iOii_dataout <= ni100OOl WHEN niOlOl0Ol = '1' ELSE ni10iiiO; + wire_ni10iOil_dataout <= ni100OOO WHEN niOlOl0Ol = '1' ELSE ni10iili; + wire_ni10l00i_dataout <= wire_nii0OOil_dataout WHEN niOlOi10i = '1' ELSE wire_ni10l0Oi_dataout; + wire_ni10l00l_dataout <= wire_nii0OOiO_dataout WHEN niOlOi10i = '1' ELSE wire_ni10l0Ol_dataout; + wire_ni10l00O_dataout <= wire_nii0OOli_dataout WHEN niOlOi10i = '1' ELSE wire_ni10l0OO_dataout; + wire_ni10l01i_dataout <= wire_nii0OO0l_dataout WHEN niOlOi10i = '1' ELSE wire_ni10l0li_dataout; + wire_ni10l01l_dataout <= wire_nii0OO0O_dataout WHEN niOlOi10i = '1' ELSE wire_ni10l0ll_dataout; + wire_ni10l01O_dataout <= wire_nii0OOii_dataout WHEN niOlOi10i = '1' ELSE wire_ni10l0lO_dataout; + wire_ni10l0ii_dataout <= wire_nii0OOll_dataout WHEN niOlOi10i = '1' ELSE wire_ni10li1i_dataout; + wire_ni10l0il_dataout <= wire_nii0OOlO_dataout WHEN niOlOi10i = '1' ELSE wire_ni10li1l_dataout; + wire_ni10l0iO_dataout <= wire_nii0OOOi_dataout WHEN niOlOi10i = '1' ELSE wire_ni10li1O_dataout; + wire_ni10l0li_dataout <= ni10i11i WHEN niOlOl0Ol = '1' ELSE ni10iill; + wire_ni10l0ll_dataout <= ni10ii1O WHEN niOlOl0Ol = '1' ELSE ni10iOOi; + wire_ni10l0lO_dataout <= ni10ii0i WHEN niOlOl0Ol = '1' ELSE ni10iOOl; + wire_ni10l0Oi_dataout <= ni10ii0l WHEN niOlOl0Ol = '1' ELSE ni10iOOO; + wire_ni10l0Ol_dataout <= ni10ii0O WHEN niOlOl0Ol = '1' ELSE ni10l11i; + wire_ni10l0OO_dataout <= ni10iiii WHEN niOlOl0Ol = '1' ELSE ni10l11l; + wire_ni10l1ii_dataout <= wire_ni10l01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1il_dataout <= wire_ni10l01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1iO_dataout <= wire_ni10l01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1li_dataout <= wire_ni10l00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1ll_dataout <= wire_ni10l00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1lO_dataout <= wire_ni10l00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1Oi_dataout <= wire_ni10l0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1Ol_dataout <= wire_ni10l0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10l1OO_dataout <= wire_ni10l0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10li1i_dataout <= ni10iiil WHEN niOlOl0Ol = '1' ELSE ni10l11O; + wire_ni10li1l_dataout <= ni10iiiO WHEN niOlOl0Ol = '1' ELSE ni10l10i; + wire_ni10li1O_dataout <= ni10iili WHEN niOlOl0Ol = '1' ELSE ni10l10l; + wire_ni10ll0i_dataout <= wire_ni10llOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10ll0l_dataout <= wire_ni10llOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10ll0O_dataout <= wire_ni10llOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10ll1l_dataout <= wire_ni10llll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10ll1O_dataout <= wire_ni10lllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10llii_dataout <= wire_ni10lO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10llil_dataout <= wire_ni10lO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10lliO_dataout <= wire_ni10lO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10llli_dataout <= wire_ni10lO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10llll_dataout <= wire_nii0OO0l_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lO0l_dataout; + wire_ni10lllO_dataout <= wire_nii0OO0O_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lO0O_dataout; + wire_ni10llOi_dataout <= wire_nii0OOii_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lOii_dataout; + wire_ni10llOl_dataout <= wire_nii0OOil_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lOil_dataout; + wire_ni10llOO_dataout <= wire_nii0OOiO_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lOiO_dataout; + wire_ni10lO0i_dataout <= wire_nii0OOOi_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lOOi_dataout; + wire_ni10lO0l_dataout <= ni10iill WHEN niOlOl0Ol = '1' ELSE ni10l10O; + wire_ni10lO0O_dataout <= ni10iOOi WHEN niOlOl0Ol = '1' ELSE ni10liil; + wire_ni10lO1i_dataout <= wire_nii0OOli_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lOli_dataout; + wire_ni10lO1l_dataout <= wire_nii0OOll_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lOll_dataout; + wire_ni10lO1O_dataout <= wire_nii0OOlO_dataout WHEN niOlOi10O = '1' ELSE wire_ni10lOlO_dataout; + wire_ni10lOii_dataout <= ni10iOOl WHEN niOlOl0Ol = '1' ELSE ni10liiO; + wire_ni10lOil_dataout <= ni10iOOO WHEN niOlOl0Ol = '1' ELSE ni10lili; + wire_ni10lOiO_dataout <= ni10l11i WHEN niOlOl0Ol = '1' ELSE ni10lill; + wire_ni10lOli_dataout <= ni10l11l WHEN niOlOl0Ol = '1' ELSE ni10lilO; + wire_ni10lOll_dataout <= ni10l11O WHEN niOlOl0Ol = '1' ELSE ni10liOi; + wire_ni10lOlO_dataout <= ni10l10i WHEN niOlOl0Ol = '1' ELSE ni10liOl; + wire_ni10lOOi_dataout <= ni10l10l WHEN niOlOl0Ol = '1' ELSE ni10liOO; + wire_ni10O00i_dataout <= wire_ni10O0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O00l_dataout <= wire_ni10O0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O00O_dataout <= wire_nii0OO0l_dataout WHEN niOlOi1il = '1' ELSE wire_ni10O0OO_dataout; + wire_ni10O01i_dataout <= wire_ni10O0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O01l_dataout <= wire_ni10O0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O01O_dataout <= wire_ni10O0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O0ii_dataout <= wire_nii0OO0O_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oi1i_dataout; + wire_ni10O0il_dataout <= wire_nii0OOii_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oi1l_dataout; + wire_ni10O0iO_dataout <= wire_nii0OOil_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oi1O_dataout; + wire_ni10O0li_dataout <= wire_nii0OOiO_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oi0i_dataout; + wire_ni10O0ll_dataout <= wire_nii0OOli_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oi0l_dataout; + wire_ni10O0lO_dataout <= wire_nii0OOll_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oi0O_dataout; + wire_ni10O0Oi_dataout <= wire_nii0OOlO_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oiii_dataout; + wire_ni10O0Ol_dataout <= wire_nii0OOOi_dataout WHEN niOlOi1il = '1' ELSE wire_ni10Oiil_dataout; + wire_ni10O0OO_dataout <= ni10l10O WHEN niOlOl0Ol = '1' ELSE ni10ll1i; + wire_ni10O1lO_dataout <= wire_ni10O00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O1Oi_dataout <= wire_ni10O0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O1Ol_dataout <= wire_ni10O0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10O1OO_dataout <= wire_ni10O0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10Oi0i_dataout <= ni10lill WHEN niOlOl0Ol = '1' ELSE ni10O10O; + wire_ni10Oi0l_dataout <= ni10lilO WHEN niOlOl0Ol = '1' ELSE ni10O1ii; + wire_ni10Oi0O_dataout <= ni10liOi WHEN niOlOl0Ol = '1' ELSE ni10O1il; + wire_ni10Oi1i_dataout <= ni10liil WHEN niOlOl0Ol = '1' ELSE ni10O11O; + wire_ni10Oi1l_dataout <= ni10liiO WHEN niOlOl0Ol = '1' ELSE ni10O10i; + wire_ni10Oi1O_dataout <= ni10lili WHEN niOlOl0Ol = '1' ELSE ni10O10l; + wire_ni10Oiii_dataout <= ni10liOl WHEN niOlOl0Ol = '1' ELSE ni10O1iO; + wire_ni10Oiil_dataout <= ni10liOO WHEN niOlOl0Ol = '1' ELSE ni10O1li; + wire_ni10Oil_dataout <= wire_ni1i00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni10OiO_dataout <= niOO0l11i AND NOT(wire_niO01l0O_dataout); + wire_ni10Oli_dataout <= niOO0iOOl AND NOT(wire_niO01l0O_dataout); + wire_ni10Olii_dataout <= wire_ni10OO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10Olil_dataout <= wire_ni10OO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10OliO_dataout <= wire_ni10OO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10Oll_dataout <= niOO0iOlO AND NOT(wire_niO01l0O_dataout); + wire_ni10Olli_dataout <= wire_ni10OO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10Olll_dataout <= wire_ni10OO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10OllO_dataout <= wire_ni10OO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10OlO_dataout <= ni10Oii AND NOT(wire_niO01l0O_dataout); + wire_ni10OlOi_dataout <= wire_ni10OOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10OlOl_dataout <= wire_ni10OOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10OlOO_dataout <= wire_ni10OOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni10OO0i_dataout <= wire_nii0OOil_dataout WHEN niOlOi1li = '1' ELSE wire_ni10OOOi_dataout; + wire_ni10OO0l_dataout <= wire_nii0OOiO_dataout WHEN niOlOi1li = '1' ELSE wire_ni10OOOl_dataout; + wire_ni10OO0O_dataout <= wire_nii0OOli_dataout WHEN niOlOi1li = '1' ELSE wire_ni10OOOO_dataout; + wire_ni10OO1i_dataout <= wire_nii0OO0l_dataout WHEN niOlOi1li = '1' ELSE wire_ni10OOli_dataout; + wire_ni10OO1l_dataout <= wire_nii0OO0O_dataout WHEN niOlOi1li = '1' ELSE wire_ni10OOll_dataout; + wire_ni10OO1O_dataout <= wire_nii0OOii_dataout WHEN niOlOi1li = '1' ELSE wire_ni10OOlO_dataout; + wire_ni10OOi_dataout <= niOO0iOOO AND NOT(wire_niO01l0O_dataout); + wire_ni10OOii_dataout <= wire_nii0OOll_dataout WHEN niOlOi1li = '1' ELSE wire_ni1i111i_dataout; + wire_ni10OOil_dataout <= wire_nii0OOlO_dataout WHEN niOlOi1li = '1' ELSE wire_ni1i111l_dataout; + wire_ni10OOiO_dataout <= wire_nii0OOOi_dataout WHEN niOlOi1li = '1' ELSE wire_ni1i111O_dataout; + wire_ni10OOl_dataout <= niOO0iOOi AND NOT(wire_niO01l0O_dataout); + wire_ni10OOli_dataout <= ni10ll1i WHEN niOlOl0Ol = '1' ELSE ni10O1ll; + wire_ni10OOll_dataout <= ni10O11O WHEN niOlOl0Ol = '1' ELSE ni10OiOi; + wire_ni10OOlO_dataout <= ni10O10i WHEN niOlOl0Ol = '1' ELSE ni10OiOl; + wire_ni10OOO_dataout <= niOO0iOll AND NOT(wire_niO01l0O_dataout); + wire_ni10OOOi_dataout <= ni10O10l WHEN niOlOl0Ol = '1' ELSE ni10OiOO; + wire_ni10OOOl_dataout <= ni10O10O WHEN niOlOl0Ol = '1' ELSE ni10Ol1i; + wire_ni10OOOO_dataout <= ni10O1ii WHEN niOlOl0Ol = '1' ELSE ni10Ol1l; + wire_ni1100il_dataout <= wire_ni110i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1100iO_dataout <= wire_ni110i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1100li_dataout <= wire_ni110i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1100ll_dataout <= wire_ni110i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1100lO_dataout <= wire_ni110i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1100Oi_dataout <= wire_ni110iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1100Ol_dataout <= wire_ni110iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1100OO_dataout <= wire_ni110iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11011i_dataout <= wire_ni11011l_o(2) WHEN niOlO0lli = '1' ELSE ni111llO; + wire_ni110i0i_dataout <= wire_niii101l_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110iOi_dataout; + wire_ni110i0l_dataout <= wire_niii101O_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110iOl_dataout; + wire_ni110i0O_dataout <= wire_niii100i_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110iOO_dataout; + wire_ni110i1i_dataout <= wire_ni110ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110i1l_dataout <= wire_niii11OO_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110ill_dataout; + wire_ni110i1O_dataout <= wire_niii101i_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110ilO_dataout; + wire_ni110ii_dataout <= (wire_ni1ilOl_w_lg_dataout2826w(0) AND wire_ni110Ol_w_lg_dataout2829w(0)) AND NOT(wire_niO01O0O_dataout); + wire_ni110iii_dataout <= wire_niii100l_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110l1i_dataout; + wire_ni110iil_dataout <= wire_niii100O_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110l1l_dataout; + wire_ni110iiO_dataout <= wire_niii10ii_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110l1O_dataout; + wire_ni110il_dataout <= ni1100i AND NOT(wire_niO01O0O_dataout); + wire_ni110ili_dataout <= wire_niii10il_dataout WHEN niOlO0OiO = '1' ELSE wire_ni110l0i_dataout; + wire_ni110ill_dataout <= ni110l0l AND NOT(niOlOl0Ol); + wire_ni110ilO_dataout <= ni1101Ol AND NOT(niOlOl0Ol); + wire_ni110iO_dataout <= (wire_ni1ilOl_w_lg_dataout2826w(0) AND wire_ni110Ol_dataout) AND NOT(wire_niO01O0O_dataout); + wire_ni110iOi_dataout <= ni1101OO AND NOT(niOlOl0Ol); + wire_ni110iOl_dataout <= ni11001i AND NOT(niOlOl0Ol); + wire_ni110iOO_dataout <= ni11001l AND NOT(niOlOl0Ol); + wire_ni110l0i_dataout <= ni11000O AND NOT(niOlOl0Ol); + wire_ni110l1i_dataout <= ni11001O AND NOT(niOlOl0Ol); + wire_ni110l1l_dataout <= ni11000i AND NOT(niOlOl0Ol); + wire_ni110l1O_dataout <= ni11000l AND NOT(niOlOl0Ol); + wire_ni110lOO_dataout <= wire_ni110OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110O0i_dataout <= wire_ni110OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110O0l_dataout <= wire_ni110OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110O0O_dataout <= wire_ni110OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110O1i_dataout <= wire_ni110Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110O1l_dataout <= wire_ni110Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110O1O_dataout <= wire_ni110OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110Oii_dataout <= wire_ni11i11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110Oil_dataout <= wire_ni11i11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni110OiO_dataout <= wire_niii11OO_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i11O_dataout; + wire_ni110Ol_dataout <= (wire_ni1lOlO_w_lg_ni11i0i2801w(0) AND wire_w_lg_w_k_hip_range2413w2813w(0)) OR (wire_ni1lOlO_w_lg_ni11i0i2801w(0) AND (wire_w_lg_w_k_hip_range2413w2429w(0) AND ((((NOT (ni11l0O XOR ni11l1l)) AND (NOT (ni11lii XOR ni11l1O))) AND (NOT (ni11lil XOR ni11l0i))) AND (NOT (ni11liO XOR ni11l0l))))); + wire_ni110Ol_w_lg_dataout2829w(0) <= wire_ni110Ol_dataout AND wire_ni1lOlO_w_lg_ni1100i2828w(0); + wire_ni110Ol_w_lg_dataout2425w(0) <= NOT wire_ni110Ol_dataout; + wire_ni110Oli_dataout <= wire_niii101i_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i10i_dataout; + wire_ni110Oll_dataout <= wire_niii101l_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i10l_dataout; + wire_ni110OlO_dataout <= wire_niii101O_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i10O_dataout; + wire_ni110OOi_dataout <= wire_niii100i_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i1ii_dataout; + wire_ni110OOl_dataout <= wire_niii100l_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i1il_dataout; + wire_ni110OOO_dataout <= wire_niii100O_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i1iO_dataout; + wire_ni1110il_dataout <= wire_ni111i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1110iO_dataout <= wire_ni111i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1110li_dataout <= wire_ni111i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1110ll_dataout <= wire_ni111i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1110lO_dataout <= wire_ni111i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1110Oi_dataout <= wire_ni111iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1110Ol_dataout <= wire_ni111iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1110OO_dataout <= wire_ni111iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11110i_dataout <= n0OOO1ll WHEN niOlOl0Ol = '1' ELSE n0OOOl0O; + wire_ni11110l_dataout <= n0OOO1lO WHEN niOlOl0Ol = '1' ELSE n0OOOlii; + wire_ni11110O_dataout <= n0OOO1Oi WHEN niOlOl0Ol = '1' ELSE n0OOOlil; + wire_ni11111i_dataout <= n0OOllii WHEN niOlOl0Ol = '1' ELSE n0OOO01l; + wire_ni11111l_dataout <= n0OOO1iO WHEN niOlOl0Ol = '1' ELSE n0OOOl0i; + wire_ni11111O_dataout <= n0OOO1li WHEN niOlOl0Ol = '1' ELSE n0OOOl0l; + wire_ni1111ii_dataout <= n0OOO1Ol WHEN niOlOl0Ol = '1' ELSE n0OOOliO; + wire_ni1111il_dataout <= n0OOO1OO WHEN niOlOl0Ol = '1' ELSE n0OOOlli; + wire_ni1111iO_dataout <= n0OOO01i WHEN niOlOl0Ol = '1' ELSE n0OOOlll; + wire_ni111i0i_dataout <= wire_niii1ilO_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111iOi_dataout; + wire_ni111i0l_dataout <= wire_niii1iOi_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111iOl_dataout; + wire_ni111i0O_dataout <= wire_niii1iOl_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111iOO_dataout; + wire_ni111i1i_dataout <= wire_ni111ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni111i1l_dataout <= wire_niii1ili_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111ill_dataout; + wire_ni111i1O_dataout <= wire_niii1ill_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111ilO_dataout; + wire_ni111iii_dataout <= wire_niii1iOO_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111l1i_dataout; + wire_ni111iil_dataout <= wire_niii1l1i_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111l1l_dataout; + wire_ni111iiO_dataout <= wire_niii1l1l_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111l1O_dataout; + wire_ni111ili_dataout <= wire_niii1l1O_dataout WHEN niOlO0l0O = '1' ELSE wire_ni111l0i_dataout; + wire_ni111ill_dataout <= n0OOO01l WHEN niOlOl0Ol = '1' ELSE n0OOOllO; + wire_ni111ilO_dataout <= n0OOOl0i WHEN niOlOl0Ol = '1' ELSE ni1111Ol; + wire_ni111iOi_dataout <= n0OOOl0l WHEN niOlOl0Ol = '1' ELSE ni1111OO; + wire_ni111iOl_dataout <= n0OOOl0O WHEN niOlOl0Ol = '1' ELSE ni11101i; + wire_ni111iOO_dataout <= n0OOOlii WHEN niOlOl0Ol = '1' ELSE ni11101l; + wire_ni111l0i_dataout <= n0OOOlll WHEN niOlOl0Ol = '1' ELSE ni11100O; + wire_ni111l1i_dataout <= n0OOOlil WHEN niOlOl0Ol = '1' ELSE ni11101O; + wire_ni111l1l_dataout <= n0OOOliO WHEN niOlOl0Ol = '1' ELSE ni11100i; + wire_ni111l1O_dataout <= n0OOOlli WHEN niOlOl0Ol = '1' ELSE ni11100l; + wire_ni111lOi_dataout <= niOlO0lii AND NOT(wire_niO01lOO_dataout); + wire_ni111lOl_dataout <= wire_ni111O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni111lOO_dataout <= wire_ni111O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni111O0l_dataout <= wire_ni111OiO_dataout AND NOT(niOlOOiOi); + wire_ni111O0O_dataout <= wire_ni111Oli_dataout AND NOT(niOlOOiOi); + wire_ni111O1i_dataout <= wire_ni111Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni111O1l_dataout <= wire_ni111Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni111Oii_dataout <= wire_ni111Oll_dataout AND NOT(niOlOOiOi); + wire_ni111Oil_dataout <= wire_ni111OlO_dataout AND NOT(niOlOOiOi); + wire_ni111OiO_dataout <= wire_w_lg_niOlO0liO11440w(0) WHEN niOlO0lll = '1' ELSE wire_ni111OOi_dataout; + wire_ni111Oli_dataout <= wire_ni11010i_o(1) WHEN niOlO0lll = '1' ELSE wire_ni111OOl_dataout; + wire_ni111Oll_dataout <= wire_ni11010i_o(2) WHEN niOlO0lll = '1' ELSE wire_ni111OOO_dataout; + wire_ni111OlO_dataout <= wire_ni11010i_o(3) WHEN niOlO0lll = '1' ELSE wire_ni11011i_dataout; + wire_ni111OOi_dataout <= ni111liO OR niOlO0lli; + wire_ni111OOl_dataout <= wire_ni11011l_o(0) WHEN niOlO0lli = '1' ELSE ni111lli; + wire_ni111OOO_dataout <= wire_ni11011l_o(1) WHEN niOlO0lli = '1' ELSE ni111lll; + wire_ni11i0l_dataout <= ni10O0i AND NOT(wire_niO01O0O_dataout); + wire_ni11i0li_dataout <= wire_ni11ii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11i0ll_dataout <= wire_ni11ii0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11i0lO_dataout <= wire_ni11ii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11i0O_dataout <= ni10O0l AND NOT(wire_niO01O0O_dataout); + wire_ni11i0Oi_dataout <= wire_ni11iiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11i0Ol_dataout <= wire_ni11iiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11i0OO_dataout <= wire_ni11iiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11i10i_dataout <= ni1101Ol WHEN niOlOl0Ol = '1' ELSE ni110l0O; + wire_ni11i10l_dataout <= ni1101OO WHEN niOlOl0Ol = '1' ELSE ni110lii; + wire_ni11i10O_dataout <= ni11001i WHEN niOlOl0Ol = '1' ELSE ni110lil; + wire_ni11i11i_dataout <= wire_niii10ii_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i1li_dataout; + wire_ni11i11l_dataout <= wire_niii10il_dataout WHEN niOlO0llO = '1' ELSE wire_ni11i1ll_dataout; + wire_ni11i11O_dataout <= ni110l0l WHEN niOlOl0Ol = '1' ELSE ni1100ii; + wire_ni11i1ii_dataout <= ni11001l WHEN niOlOl0Ol = '1' ELSE ni110liO; + wire_ni11i1il_dataout <= ni11001O WHEN niOlOl0Ol = '1' ELSE ni110lli; + wire_ni11i1iO_dataout <= ni11000i WHEN niOlOl0Ol = '1' ELSE ni110lll; + wire_ni11i1li_dataout <= ni11000l WHEN niOlOl0Ol = '1' ELSE ni110llO; + wire_ni11i1ll_dataout <= ni11000O WHEN niOlOl0Ol = '1' ELSE ni110lOi; + wire_ni11ii0i_dataout <= wire_niii11OO_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11iiOi_dataout; + wire_ni11ii0l_dataout <= wire_niii101i_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11iiOl_dataout; + wire_ni11ii0O_dataout <= wire_niii101l_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11iiOO_dataout; + wire_ni11ii1i_dataout <= wire_ni11iili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11ii1l_dataout <= wire_ni11iill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11ii1O_dataout <= wire_ni11iilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iii_dataout <= ni10O0O AND NOT(wire_niO01O0O_dataout); + wire_ni11iiii_dataout <= wire_niii101O_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11il1i_dataout; + wire_ni11iiil_dataout <= wire_niii100i_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11il1l_dataout; + wire_ni11iiiO_dataout <= wire_niii100l_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11il1O_dataout; + wire_ni11iil_dataout <= ni10Oii AND NOT(wire_niO01O0O_dataout); + wire_ni11iili_dataout <= wire_niii100O_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11il0i_dataout; + wire_ni11iill_dataout <= wire_niii10ii_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11il0l_dataout; + wire_ni11iilO_dataout <= wire_niii10il_dataout WHEN niOlO0lOi = '1' ELSE wire_ni11il0O_dataout; + wire_ni11iiOi_dataout <= ni1100ii WHEN niOlOl0Ol = '1' ELSE ni110lOl; + wire_ni11iiOl_dataout <= ni110l0O WHEN niOlOl0Ol = '1' ELSE ni11i01i; + wire_ni11iiOO_dataout <= ni110lii WHEN niOlOl0Ol = '1' ELSE ni11i01l; + wire_ni11il0i_dataout <= ni110lll WHEN niOlOl0Ol = '1' ELSE ni11i00O; + wire_ni11il0l_dataout <= ni110llO WHEN niOlOl0Ol = '1' ELSE ni11i0ii; + wire_ni11il0O_dataout <= ni110lOi WHEN niOlOl0Ol = '1' ELSE ni11i0il; + wire_ni11il1i_dataout <= ni110lil WHEN niOlOl0Ol = '1' ELSE ni11i01O; + wire_ni11il1l_dataout <= ni110liO WHEN niOlOl0Ol = '1' ELSE ni11i00i; + wire_ni11il1O_dataout <= ni110lli WHEN niOlOl0Ol = '1' ELSE ni11i00l; + wire_ni11iO0l_dataout <= wire_ni11iOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iO0O_dataout <= wire_ni11iOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOii_dataout <= wire_ni11l11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOil_dataout <= wire_ni11l11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOiO_dataout <= wire_ni11l11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOli_dataout <= wire_ni11l10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOll_dataout <= wire_ni11l10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOlO_dataout <= wire_ni11l10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOOi_dataout <= wire_ni11l1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11iOOl_dataout <= wire_niii11OO_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1il_dataout; + wire_ni11iOOO_dataout <= wire_niii101i_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1iO_dataout; + wire_ni11l01i_dataout <= ni11i0il WHEN niOlOl0Ol = '1' ELSE ni11iO1O; + wire_ni11l0OO_dataout <= wire_ni11liiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11l10i_dataout <= wire_niii100l_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1Oi_dataout; + wire_ni11l10l_dataout <= wire_niii100O_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1Ol_dataout; + wire_ni11l10O_dataout <= wire_niii10ii_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1OO_dataout; + wire_ni11l11i_dataout <= wire_niii101l_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1li_dataout; + wire_ni11l11l_dataout <= wire_niii101O_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1ll_dataout; + wire_ni11l11O_dataout <= wire_niii100i_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l1lO_dataout; + wire_ni11l1ii_dataout <= wire_niii10il_dataout WHEN niOlO0lOO = '1' ELSE wire_ni11l01i_dataout; + wire_ni11l1il_dataout <= ni110lOl WHEN niOlOl0Ol = '1' ELSE ni11i0iO; + wire_ni11l1iO_dataout <= ni11i01i WHEN niOlOl0Ol = '1' ELSE ni11illl; + wire_ni11l1li_dataout <= ni11i01l WHEN niOlOl0Ol = '1' ELSE ni11illO; + wire_ni11l1ll_dataout <= ni11i01O WHEN niOlOl0Ol = '1' ELSE ni11ilOi; + wire_ni11l1lO_dataout <= ni11i00i WHEN niOlOl0Ol = '1' ELSE ni11ilOl; + wire_ni11l1Oi_dataout <= ni11i00l WHEN niOlOl0Ol = '1' ELSE ni11ilOO; + wire_ni11l1Ol_dataout <= ni11i00O WHEN niOlOl0Ol = '1' ELSE ni11iO1i; + wire_ni11l1OO_dataout <= ni11i0ii WHEN niOlOl0Ol = '1' ELSE ni11iO1l; + wire_ni11li0i_dataout <= wire_ni11liOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11li0l_dataout <= wire_ni11liOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11li0O_dataout <= wire_ni11liOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11li1i_dataout <= wire_ni11lili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11li1l_dataout <= wire_ni11lill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11li1O_dataout <= wire_ni11lilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11liii_dataout <= wire_ni11ll1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11liil_dataout <= wire_ni11ll1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11liiO_dataout <= wire_niii11OO_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11ll1O_dataout; + wire_ni11lili_dataout <= wire_niii101i_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11ll0i_dataout; + wire_ni11lill_dataout <= wire_niii101l_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11ll0l_dataout; + wire_ni11lilO_dataout <= wire_niii101O_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11ll0O_dataout; + wire_ni11liOi_dataout <= wire_niii100i_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11llii_dataout; + wire_ni11liOl_dataout <= wire_niii100l_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11llil_dataout; + wire_ni11liOO_dataout <= wire_niii100O_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11lliO_dataout; + wire_ni11ll0i_dataout <= ni11illl WHEN niOlOl0Ol = '1' ELSE ni11l00O; + wire_ni11ll0l_dataout <= ni11illO WHEN niOlOl0Ol = '1' ELSE ni11l0ii; + wire_ni11ll0O_dataout <= ni11ilOi WHEN niOlOl0Ol = '1' ELSE ni11l0il; + wire_ni11ll1i_dataout <= wire_niii10ii_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11llli_dataout; + wire_ni11ll1l_dataout <= wire_niii10il_dataout WHEN niOlO0O1l = '1' ELSE wire_ni11llll_dataout; + wire_ni11ll1O_dataout <= ni11i0iO WHEN niOlOl0Ol = '1' ELSE ni11iO0i; + wire_ni11llii_dataout <= ni11ilOl WHEN niOlOl0Ol = '1' ELSE ni11l0iO; + wire_ni11llil_dataout <= ni11ilOO WHEN niOlOl0Ol = '1' ELSE ni11l0li; + wire_ni11lliO_dataout <= ni11iO1i WHEN niOlOl0Ol = '1' ELSE ni11l0ll; + wire_ni11llli_dataout <= ni11iO1l WHEN niOlOl0Ol = '1' ELSE ni11l0lO; + wire_ni11llll_dataout <= ni11iO1O WHEN niOlOl0Ol = '1' ELSE ni11l0Oi; + wire_ni11lOli_dataout <= wire_ni11O10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11lOll_dataout <= wire_ni11O10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11lOlO_dataout <= wire_ni11O10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11lOOi_dataout <= wire_ni11O1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11lOOl_dataout <= wire_ni11O1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11lOOO_dataout <= wire_ni11O1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11O00i_dataout <= ni11l0ll WHEN niOlOl0Ol = '1' ELSE ni11lO0O; + wire_ni11O00l_dataout <= ni11l0lO WHEN niOlOl0Ol = '1' ELSE ni11lOii; + wire_ni11O00O_dataout <= ni11l0Oi WHEN niOlOl0Ol = '1' ELSE ni11lOil; + wire_ni11O01i_dataout <= ni11l0il WHEN niOlOl0Ol = '1' ELSE ni11lO1O; + wire_ni11O01l_dataout <= ni11l0iO WHEN niOlOl0Ol = '1' ELSE ni11lO0i; + wire_ni11O01O_dataout <= ni11l0li WHEN niOlOl0Ol = '1' ELSE ni11lO0l; + wire_ni11O0i_dataout <= ni11iOl AND NOT(wire_niO01O0O_dataout); + wire_ni11O0l_dataout <= ni11iOO AND NOT(wire_niO01O0O_dataout); + wire_ni11O0O_dataout <= ni11l1i AND NOT(wire_niO01O0O_dataout); + wire_ni11O10i_dataout <= wire_niii11OO_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O1Oi_dataout; + wire_ni11O10l_dataout <= wire_niii101i_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O1Ol_dataout; + wire_ni11O10O_dataout <= wire_niii101l_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O1OO_dataout; + wire_ni11O11i_dataout <= wire_ni11O1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11O11l_dataout <= wire_ni11O1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11O11O_dataout <= wire_ni11O1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11O1ii_dataout <= wire_niii101O_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O01i_dataout; + wire_ni11O1il_dataout <= wire_niii100i_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O01l_dataout; + wire_ni11O1iO_dataout <= wire_niii100l_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O01O_dataout; + wire_ni11O1l_dataout <= wire_ni1010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_ni11O1li_dataout <= wire_niii100O_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O00i_dataout; + wire_ni11O1ll_dataout <= wire_niii10ii_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O00l_dataout; + wire_ni11O1lO_dataout <= wire_niii10il_dataout WHEN niOlO0O0i = '1' ELSE wire_ni11O00O_dataout; + wire_ni11O1O_dataout <= ni11iOi AND NOT(wire_niO01O0O_dataout); + wire_ni11O1Oi_dataout <= ni11iO0i WHEN niOlOl0Ol = '1' ELSE ni11l0Ol; + wire_ni11O1Ol_dataout <= ni11l00O WHEN niOlOl0Ol = '1' ELSE ni11lO1i; + wire_ni11O1OO_dataout <= ni11l0ii WHEN niOlOl0Ol = '1' ELSE ni11lO1l; + wire_ni11Oi0l_dataout <= wire_ni11OiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11Oi0O_dataout <= wire_ni11OiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11Oii_dataout <= ni11l1l AND NOT(wire_niO01O0O_dataout); + wire_ni11Oiii_dataout <= wire_ni11Ol1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11Oiil_dataout <= wire_ni11Ol1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11OiiO_dataout <= wire_ni11Ol1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11Oil_dataout <= ni11l1O AND NOT(wire_niO01O0O_dataout); + wire_ni11Oili_dataout <= wire_ni11Ol0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11Oill_dataout <= wire_ni11Ol0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11OilO_dataout <= wire_ni11Ol0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11OiO_dataout <= ni11l0i AND NOT(wire_niO01O0O_dataout); + wire_ni11OiOi_dataout <= wire_ni11Olii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni11OiOl_dataout <= wire_niii11OO_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11Olil_dataout; + wire_ni11OiOO_dataout <= wire_niii101i_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11OliO_dataout; + wire_ni11Ol0i_dataout <= wire_niii100l_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11OlOi_dataout; + wire_ni11Ol0l_dataout <= wire_niii100O_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11OlOl_dataout; + wire_ni11Ol0O_dataout <= wire_niii10ii_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11OlOO_dataout; + wire_ni11Ol1i_dataout <= wire_niii101l_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11Olli_dataout; + wire_ni11Ol1l_dataout <= wire_niii101O_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11Olll_dataout; + wire_ni11Ol1O_dataout <= wire_niii100i_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11OllO_dataout; + wire_ni11Oli_dataout <= ni11l0l AND NOT(wire_niO01O0O_dataout); + wire_ni11Olii_dataout <= wire_niii10il_dataout WHEN niOlO0O0O = '1' ELSE wire_ni11OO1i_dataout; + wire_ni11Olil_dataout <= ni11l0Ol WHEN niOlOl0Ol = '1' ELSE ni11lOiO; + wire_ni11OliO_dataout <= ni11lO1i WHEN niOlOl0Ol = '1' ELSE ni11O0ll; + wire_ni11Oll_dataout <= ni1100O AND NOT(wire_niO01O0O_dataout); + wire_ni11Olli_dataout <= ni11lO1l WHEN niOlOl0Ol = '1' ELSE ni11O0lO; + wire_ni11Olll_dataout <= ni11lO1O WHEN niOlOl0Ol = '1' ELSE ni11O0Oi; + wire_ni11OllO_dataout <= ni11lO0i WHEN niOlOl0Ol = '1' ELSE ni11O0Ol; + wire_ni11OlO_dataout <= ni1100l AND NOT(wire_niO01O0O_dataout); + wire_ni11OlOi_dataout <= ni11lO0l WHEN niOlOl0Ol = '1' ELSE ni11O0OO; + wire_ni11OlOl_dataout <= ni11lO0O WHEN niOlOl0Ol = '1' ELSE ni11Oi1i; + wire_ni11OlOO_dataout <= ni11lOii WHEN niOlOl0Ol = '1' ELSE ni11Oi1l; + wire_ni11OO1i_dataout <= ni11lOil WHEN niOlOl0Ol = '1' ELSE ni11Oi1O; + wire_ni11OOi_dataout <= ni1101i AND NOT(wire_niO01O0O_dataout); + wire_ni11OOl_dataout <= ni11llO AND NOT(wire_niO01O0O_dataout); + wire_ni11OOO_dataout <= niOO0iOii AND NOT(wire_niO01O0O_dataout); + wire_ni11OOOO_dataout <= wire_ni1011iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i000i_dataout <= wire_ni1i00Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i000l_dataout <= wire_ni1i00Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i000O_dataout <= wire_ni1i00OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i001i_dataout <= wire_ni1i00li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i001l_dataout <= wire_ni1i00ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i001O_dataout <= wire_ni1i00lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i00i_dataout <= ni10iii WHEN ((((NOT (niOO0l11i XOR niOO0iOOO)) AND (NOT (niOO0iOOl XOR niOO0iOOi))) AND (NOT (niOO0iOlO XOR niOO0iOll))) AND (NOT (ni10Oii XOR ni10liO))) = '1' ELSE wire_ni1i00l_o; + wire_ni1i00ii_dataout <= wire_ni1i0i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i00il_dataout <= wire_nii0Oili_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0i1l_dataout; + wire_ni1i00iO_dataout <= wire_nii0Oill_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0i1O_dataout; + wire_ni1i00li_dataout <= wire_nii0OilO_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0i0i_dataout; + wire_ni1i00ll_dataout <= wire_nii0OiOi_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0i0l_dataout; + wire_ni1i00lO_dataout <= wire_nii0OiOl_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0i0O_dataout; + wire_ni1i00Oi_dataout <= wire_nii0OiOO_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0iii_dataout; + wire_ni1i00Ol_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0iil_dataout; + wire_ni1i00OO_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0iiO_dataout; + wire_ni1i011i_dataout <= ni1i1l1O AND NOT(niOlOl0Ol); + wire_ni1i011l_dataout <= ni1i1l0i AND NOT(niOlOl0Ol); + wire_ni1i011O_dataout <= ni1i1l0l AND NOT(niOlOl0Ol); + wire_ni1i01i_dataout <= wire_ni1i0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i01l_dataout <= wire_ni1i0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i01O_dataout <= wire_ni1i0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i01Ol_dataout <= wire_ni1i00il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i01OO_dataout <= wire_ni1i00iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0i0i_dataout <= ni1i1iOl WHEN niOlOl0Ol = '1' ELSE ni1i010O; + wire_ni1i0i0l_dataout <= ni1i1iOO WHEN niOlOl0Ol = '1' ELSE ni1i01ii; + wire_ni1i0i0O_dataout <= ni1i1l1i WHEN niOlOl0Ol = '1' ELSE ni1i01il; + wire_ni1i0i1i_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi01i = '1' ELSE wire_ni1i0ili_dataout; + wire_ni1i0i1l_dataout <= ni1i010i WHEN niOlOl0Ol = '1' ELSE ni1i1l0O; + wire_ni1i0i1O_dataout <= ni1i1iOi WHEN niOlOl0Ol = '1' ELSE ni1i010l; + wire_ni1i0iii_dataout <= ni1i1l1l WHEN niOlOl0Ol = '1' ELSE ni1i01iO; + wire_ni1i0iil_dataout <= ni1i1l1O WHEN niOlOl0Ol = '1' ELSE ni1i01li; + wire_ni1i0iiO_dataout <= ni1i1l0i WHEN niOlOl0Ol = '1' ELSE ni1i01ll; + wire_ni1i0ili_dataout <= ni1i1l0l WHEN niOlOl0Ol = '1' ELSE ni1i01lO; + wire_ni1i0iO_dataout <= ni10lOO WHEN tx_valid_vc1 = '1' ELSE ni10O0i; + wire_ni1i0li_dataout <= ni10O1i WHEN tx_valid_vc1 = '1' ELSE ni10O0l; + wire_ni1i0liO_dataout <= wire_ni1i0O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0ll_dataout <= ni10O1l WHEN tx_valid_vc1 = '1' ELSE ni10O0O; + wire_ni1i0lli_dataout <= wire_ni1i0O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0lll_dataout <= wire_ni1i0O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0llO_dataout <= wire_ni1i0O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0lO_dataout <= ni10O1O WHEN tx_valid_vc1 = '1' ELSE ni10Oii; + wire_ni1i0lOi_dataout <= wire_ni1i0Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0lOl_dataout <= wire_ni1i0Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0lOO_dataout <= wire_ni1i0OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0O0i_dataout <= wire_nii0Oill_dataout WHEN niOlOi01l = '1' ELSE wire_ni1i0OOi_dataout; + wire_ni1i0O0l_dataout <= wire_nii0OilO_dataout WHEN niOlOi01l = '1' ELSE wire_ni1i0OOl_dataout; + wire_ni1i0O0O_dataout <= wire_nii0OiOi_dataout WHEN niOlOi01l = '1' ELSE wire_ni1i0OOO_dataout; + wire_ni1i0O1i_dataout <= wire_ni1i0Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0O1l_dataout <= wire_ni1i0Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i0O1O_dataout <= wire_nii0Oili_dataout WHEN niOlOi01l = '1' ELSE wire_ni1i0OlO_dataout; + wire_ni1i0Oi_dataout <= ni10lli WHEN tx_valid_vc1 = '1' ELSE ni10lOO; + wire_ni1i0Oii_dataout <= wire_nii0OiOl_dataout WHEN niOlOi01l = '1' ELSE wire_ni1ii11i_dataout; + wire_ni1i0Oil_dataout <= wire_nii0OiOO_dataout WHEN niOlOi01l = '1' ELSE wire_ni1ii11l_dataout; + wire_ni1i0OiO_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi01l = '1' ELSE wire_ni1ii11O_dataout; + wire_ni1i0Ol_dataout <= ni10lll WHEN tx_valid_vc1 = '1' ELSE ni10O1i; + wire_ni1i0Oli_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi01l = '1' ELSE wire_ni1ii10i_dataout; + wire_ni1i0Oll_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi01l = '1' ELSE wire_ni1ii10l_dataout; + wire_ni1i0OlO_dataout <= ni1i1l0O WHEN niOlOl0Ol = '1' ELSE ni1i01Oi; + wire_ni1i0OO_dataout <= ni10llO WHEN tx_valid_vc1 = '1' ELSE ni10O1l; + wire_ni1i0OOi_dataout <= ni1i010l WHEN niOlOl0Ol = '1' ELSE ni1i0iOO; + wire_ni1i0OOl_dataout <= ni1i010O WHEN niOlOl0Ol = '1' ELSE ni1i0l1i; + wire_ni1i0OOO_dataout <= ni1i01ii WHEN niOlOl0Ol = '1' ELSE ni1i0l1l; + wire_ni1i100i_dataout <= wire_ni1i10il_dataout AND NOT(niOlOO0li); + wire_ni1i100l_dataout <= wire_ni1i10iO_dataout AND NOT(niOlOO0li); + wire_ni1i100O_dataout <= wire_ni1i10li_dataout AND NOT(niOlOO0li); + wire_ni1i101i_dataout <= wire_ni1i10ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i10i_dataout <= ni11lli AND NOT(wire_niO01l0O_dataout); + wire_ni1i10ii_dataout <= wire_ni1i10ll_dataout AND NOT(niOlOO0li); + wire_ni1i10il_dataout <= wire_w_lg_niOlOi1Oi11278w(0) WHEN niOlOi1OO = '1' ELSE wire_ni1i10lO_dataout; + wire_ni1i10iO_dataout <= wire_ni1i1i1O_o(1) WHEN niOlOi1OO = '1' ELSE wire_ni1i10Oi_dataout; + wire_ni1i10l_dataout <= ni11lOi AND NOT(wire_niO01l0O_dataout); + wire_ni1i10li_dataout <= wire_ni1i1i1O_o(2) WHEN niOlOi1OO = '1' ELSE wire_ni1i10Ol_dataout; + wire_ni1i10ll_dataout <= wire_ni1i1i1O_o(3) WHEN niOlOi1OO = '1' ELSE wire_ni1i10OO_dataout; + wire_ni1i10lO_dataout <= ni1i11il OR niOlOi1Ol; + wire_ni1i10O_dataout <= ni11lOl AND NOT(wire_niO01l0O_dataout); + wire_ni1i10Oi_dataout <= wire_ni1i1i1i_o(0) WHEN niOlOi1Ol = '1' ELSE ni1i11iO; + wire_ni1i10Ol_dataout <= wire_ni1i1i1i_o(1) WHEN niOlOi1Ol = '1' ELSE ni1i11li; + wire_ni1i10OO_dataout <= wire_ni1i1i1i_o(2) WHEN niOlOi1Ol = '1' ELSE ni1i11ll; + wire_ni1i111i_dataout <= ni10O1il WHEN niOlOl0Ol = '1' ELSE ni10Ol1O; + wire_ni1i111l_dataout <= ni10O1iO WHEN niOlOl0Ol = '1' ELSE ni10Ol0i; + wire_ni1i111O_dataout <= ni10O1li WHEN niOlOl0Ol = '1' ELSE ni10Ol0l; + wire_ni1i11i_dataout <= ni10liO AND NOT(wire_niO01l0O_dataout); + wire_ni1i11l_dataout <= (wire_ni1i0il_o OR (ni10iii AND ((((NOT wire_ni100OO_o(4)) AND (NOT wire_ni100OO_o(3))) AND (NOT wire_ni100OO_o(2))) AND (NOT wire_ni100OO_o(1))))) AND NOT(wire_niO01l0O_dataout); + wire_ni1i11lO_dataout <= niOlOi1ll AND NOT(wire_niO01lOO_dataout); + wire_ni1i11O_dataout <= ni11O1i AND NOT(wire_niO01l0O_dataout); + wire_ni1i11Oi_dataout <= wire_ni1i100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i11Ol_dataout <= wire_ni1i100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i11OO_dataout <= wire_ni1i100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1ii_dataout <= wire_ni1ii1l_dataout OR wire_niO01l0O_dataout; + wire_ni1i1il_dataout <= wire_ni1ii1O_dataout OR wire_niO01l0O_dataout; + wire_ni1i1iO_dataout <= wire_ni1ii0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i1li_dataout <= wire_ni1ii0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i1lii_dataout <= wire_ni1i1O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1lil_dataout <= wire_ni1i1O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1liO_dataout <= wire_ni1i1O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1ll_dataout <= wire_ni1i0Oi_dataout OR wire_niO01l0O_dataout; + wire_ni1i1lli_dataout <= wire_ni1i1O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1lll_dataout <= wire_ni1i1O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1llO_dataout <= wire_ni1i1O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1lO_dataout <= wire_ni1i0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i1lOi_dataout <= wire_ni1i1Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1lOl_dataout <= wire_ni1i1Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1lOO_dataout <= wire_ni1i1OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1i1O0i_dataout <= wire_nii0OiOi_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i1OOi_dataout; + wire_ni1i1O0l_dataout <= wire_nii0OiOl_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i1OOl_dataout; + wire_ni1i1O0O_dataout <= wire_nii0OiOO_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i1OOO_dataout; + wire_ni1i1O1i_dataout <= wire_nii0Oili_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i1Oli_dataout; + wire_ni1i1O1l_dataout <= wire_nii0Oill_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i1Oll_dataout; + wire_ni1i1O1O_dataout <= wire_nii0OilO_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i1OlO_dataout; + wire_ni1i1Oi_dataout <= wire_ni1i0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i1Oii_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i011i_dataout; + wire_ni1i1Oil_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i011l_dataout; + wire_ni1i1OiO_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi0Oi = '1' ELSE wire_ni1i011O_dataout; + wire_ni1i1Ol_dataout <= wire_ni1ii1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i1Oli_dataout <= ni1i010i AND NOT(niOlOl0Ol); + wire_ni1i1Oll_dataout <= ni1i1iOi AND NOT(niOlOl0Ol); + wire_ni1i1OlO_dataout <= ni1i1iOl AND NOT(niOlOl0Ol); + wire_ni1i1OO_dataout <= wire_ni1i0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_ni1i1OOi_dataout <= ni1i1iOO AND NOT(niOlOl0Ol); + wire_ni1i1OOl_dataout <= ni1i1l1i AND NOT(niOlOl0Ol); + wire_ni1i1OOO_dataout <= ni1i1l1l AND NOT(niOlOl0Ol); + wire_ni1ii00i_dataout <= wire_ni1ii0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii00l_dataout <= wire_ni1ii0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii00O_dataout <= wire_ni1ii0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii0i_dataout <= ((wire_w_lg_niOO0l11O2634w(0) AND wire_w_lg_niOO0l11l2630w(0)) XOR ni10llO) WHEN tx_valid_vc1 = '1' ELSE ni10llO; + wire_ni1ii0ii_dataout <= wire_ni1iii1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii0il_dataout <= wire_ni1iii1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii0iO_dataout <= wire_ni1iii1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii0l_dataout <= ((NOT (niOO0l11O OR wire_w_lg_niOO0l11l2630w(0))) XOR ni10lOi) WHEN tx_valid_vc1 = '1' ELSE ni10lOi; + wire_ni1ii0li_dataout <= wire_ni1iii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii0ll_dataout <= wire_ni1iii0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii0lO_dataout <= wire_ni1iii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ii0Oi_dataout <= wire_nii0Oili_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiiii_dataout; + wire_ni1ii0Ol_dataout <= wire_nii0Oill_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiiil_dataout; + wire_ni1ii0OO_dataout <= wire_nii0OilO_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiiiO_dataout; + wire_ni1ii10i_dataout <= ni1i01ll WHEN niOlOl0Ol = '1' ELSE ni1i0l0O; + wire_ni1ii10l_dataout <= ni1i01lO WHEN niOlOl0Ol = '1' ELSE ni1i0lii; + wire_ni1ii11i_dataout <= ni1i01il WHEN niOlOl0Ol = '1' ELSE ni1i0l1O; + wire_ni1ii11l_dataout <= ni1i01iO WHEN niOlOl0Ol = '1' ELSE ni1i0l0i; + wire_ni1ii11O_dataout <= ni1i01li WHEN niOlOl0Ol = '1' ELSE ni1i0l0l; + wire_ni1ii1i_dataout <= ni10lOi WHEN tx_valid_vc1 = '1' ELSE ni10O1O; + wire_ni1ii1l_dataout <= (wire_w_lg_niOO0l10l2626w(0) XOR ni10lli) WHEN tx_valid_vc1 = '1' ELSE ni10lli; + wire_ni1ii1O_dataout <= ((niOO0l10l AND wire_w_lg_niOO0l10i2627w(0)) XOR ni10lll) WHEN tx_valid_vc1 = '1' ELSE ni10lll; + wire_ni1iii0i_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiiOi_dataout; + wire_ni1iii0l_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiiOl_dataout; + wire_ni1iii0O_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiiOO_dataout; + wire_ni1iii1i_dataout <= wire_nii0OiOi_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiili_dataout; + wire_ni1iii1l_dataout <= wire_nii0OiOl_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiill_dataout; + wire_ni1iii1O_dataout <= wire_nii0OiOO_dataout WHEN niOlOi00i = '1' ELSE wire_ni1iiilO_dataout; + wire_ni1iiiii_dataout <= ni1i01Oi WHEN niOlOl0Ol = '1' ELSE ni1i0lil; + wire_ni1iiiil_dataout <= ni1i0iOO WHEN niOlOl0Ol = '1' ELSE ni1ii1li; + wire_ni1iiiiO_dataout <= ni1i0l1i WHEN niOlOl0Ol = '1' ELSE ni1ii1ll; + wire_ni1iiili_dataout <= ni1i0l1l WHEN niOlOl0Ol = '1' ELSE ni1ii1lO; + wire_ni1iiill_dataout <= ni1i0l1O WHEN niOlOl0Ol = '1' ELSE ni1ii1Oi; + wire_ni1iiilO_dataout <= ni1i0l0i WHEN niOlOl0Ol = '1' ELSE ni1ii1Ol; + wire_ni1iiiOi_dataout <= ni1i0l0l WHEN niOlOl0Ol = '1' ELSE ni1ii1OO; + wire_ni1iiiOl_dataout <= ni1i0l0O WHEN niOlOl0Ol = '1' ELSE ni1ii01i; + wire_ni1iiiOO_dataout <= ni1i0lii WHEN niOlOl0Ol = '1' ELSE ni1ii01l; + wire_ni1iilOl_dataout <= wire_ni1iiOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iilOO_dataout <= wire_ni1iiOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiO0i_dataout <= wire_ni1iiOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiO0l_dataout <= wire_ni1iiOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiO0O_dataout <= wire_ni1iiOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiO1i_dataout <= wire_ni1iiOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiO1l_dataout <= wire_ni1iiOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiO1O_dataout <= wire_ni1iiOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiOii_dataout <= wire_ni1il11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iiOil_dataout <= wire_nii0Oili_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il11l_dataout; + wire_ni1iiOiO_dataout <= wire_nii0Oill_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il11O_dataout; + wire_ni1iiOli_dataout <= wire_nii0OilO_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il10i_dataout; + wire_ni1iiOll_dataout <= wire_nii0OiOi_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il10l_dataout; + wire_ni1iiOlO_dataout <= wire_nii0OiOl_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il10O_dataout; + wire_ni1iiOOi_dataout <= wire_nii0OiOO_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il1ii_dataout; + wire_ni1iiOOl_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il1il_dataout; + wire_ni1iiOOO_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il1iO_dataout; + wire_ni1il0iO_dataout <= wire_ni1ili1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1il0li_dataout <= wire_ni1ili0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1il0ll_dataout <= wire_ni1ili0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1il0lO_dataout <= wire_ni1ili0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1il0Oi_dataout <= wire_ni1iliii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1il0Ol_dataout <= wire_ni1iliil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1il0OO_dataout <= wire_ni1iliiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1il10i_dataout <= ni1ii1ll WHEN niOlOl0Ol = '1' ELSE ni1iil0O; + wire_ni1il10l_dataout <= ni1ii1lO WHEN niOlOl0Ol = '1' ELSE ni1iilii; + wire_ni1il10O_dataout <= ni1ii1Oi WHEN niOlOl0Ol = '1' ELSE ni1iilil; + wire_ni1il11i_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi00O = '1' ELSE wire_ni1il1li_dataout; + wire_ni1il11l_dataout <= ni1i0lil WHEN niOlOl0Ol = '1' ELSE ni1ii01O; + wire_ni1il11O_dataout <= ni1ii1li WHEN niOlOl0Ol = '1' ELSE ni1iil0l; + wire_ni1il1ii_dataout <= ni1ii1Ol WHEN niOlOl0Ol = '1' ELSE ni1iiliO; + wire_ni1il1il_dataout <= ni1ii1OO WHEN niOlOl0Ol = '1' ELSE ni1iilli; + wire_ni1il1iO_dataout <= ni1ii01i WHEN niOlOl0Ol = '1' ELSE ni1iilll; + wire_ni1il1li_dataout <= ni1ii01l WHEN niOlOl0Ol = '1' ELSE ni1iillO; + wire_ni1ili0i_dataout <= wire_nii0Oill_dataout WHEN niOlOi0il = '1' ELSE wire_ni1iliOi_dataout; + wire_ni1ili0l_dataout <= wire_nii0OilO_dataout WHEN niOlOi0il = '1' ELSE wire_ni1iliOl_dataout; + wire_ni1ili0O_dataout <= wire_nii0OiOi_dataout WHEN niOlOi0il = '1' ELSE wire_ni1iliOO_dataout; + wire_ni1ili1i_dataout <= wire_ni1ilili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ili1l_dataout <= wire_ni1ilill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ili1O_dataout <= wire_nii0Oili_dataout WHEN niOlOi0il = '1' ELSE wire_ni1ililO_dataout; + wire_ni1iliii_dataout <= wire_nii0OiOl_dataout WHEN niOlOi0il = '1' ELSE wire_ni1ill1i_dataout; + wire_ni1iliil_dataout <= wire_nii0OiOO_dataout WHEN niOlOi0il = '1' ELSE wire_ni1ill1l_dataout; + wire_ni1iliiO_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi0il = '1' ELSE wire_ni1ill1O_dataout; + wire_ni1ilili_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi0il = '1' ELSE wire_ni1ill0i_dataout; + wire_ni1ilill_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi0il = '1' ELSE wire_ni1ill0l_dataout; + wire_ni1ililO_dataout <= ni1ii01O WHEN niOlOl0Ol = '1' ELSE ni1iilOi; + wire_ni1iliOi_dataout <= ni1iil0l WHEN niOlOl0Ol = '1' ELSE ni1il1OO; + wire_ni1iliOl_dataout <= ni1iil0O WHEN niOlOl0Ol = '1' ELSE ni1il01i; + wire_ni1iliOO_dataout <= ni1iilii WHEN niOlOl0Ol = '1' ELSE ni1il01l; + wire_ni1ill0i_dataout <= ni1iilll WHEN niOlOl0Ol = '1' ELSE ni1il00O; + wire_ni1ill0l_dataout <= ni1iillO WHEN niOlOl0Ol = '1' ELSE ni1il0ii; + wire_ni1ill1i_dataout <= ni1iilil WHEN niOlOl0Ol = '1' ELSE ni1il01O; + wire_ni1ill1l_dataout <= ni1iiliO WHEN niOlOl0Ol = '1' ELSE ni1il00i; + wire_ni1ill1O_dataout <= ni1iilli WHEN niOlOl0Ol = '1' ELSE ni1il00l; + wire_ni1ilO0i_dataout <= wire_ni1ilOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilO0l_dataout <= wire_ni1ilOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilO0O_dataout <= wire_ni1ilOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilOii_dataout <= wire_ni1iO11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilOil_dataout <= wire_ni1iO11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilOiO_dataout <= wire_ni1iO11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilOl_dataout <= wire_ni01l1l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_ni1ilOl_w_lg_dataout2737w(0) <= wire_ni1ilOl_dataout AND wire_w_lg_niOO0iO0i2736w(0); + wire_ni1ilOl_w_lg_dataout2826w(0) <= NOT wire_ni1ilOl_dataout; + wire_ni1ilOli_dataout <= wire_ni1iO10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilOll_dataout <= wire_ni1iO10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilOlO_dataout <= wire_ni1iO10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ilOO_dataout <= k_hip(17) AND NOT(niOO0l10O); + wire_ni1ilOOi_dataout <= wire_nii0Oili_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1ii_dataout; + wire_ni1ilOOl_dataout <= wire_nii0Oill_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1il_dataout; + wire_ni1ilOOO_dataout <= wire_nii0OilO_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1iO_dataout; + wire_ni1iO0l_dataout <= wire_ni010ii_dataout WHEN (wire_ni1lOlO_w_lg_ni1llll2574w(0) AND (niOO0l1il AND niOO0l1ii)) = '1' ELSE wire_ni1iO0O_dataout; + wire_ni1iO0O_dataout <= ni1lOiO WHEN (wire_w_lg_w_k_hip_range2413w2429w(0) AND (ni1lOli AND niOO0l1il)) = '1' ELSE wire_ni010ii_dataout; + wire_ni1iO0Ol_dataout <= wire_ni1iOiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iO0OO_dataout <= wire_ni1iOiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iO10i_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1Oi_dataout; + wire_ni1iO10l_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1Ol_dataout; + wire_ni1iO10O_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1OO_dataout; + wire_ni1iO11i_dataout <= wire_nii0OiOi_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1li_dataout; + wire_ni1iO11l_dataout <= wire_nii0OiOl_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1ll_dataout; + wire_ni1iO11O_dataout <= wire_nii0OiOO_dataout WHEN niOlOi0li = '1' ELSE wire_ni1iO1lO_dataout; + wire_ni1iO1i_dataout <= k_hip(18) AND NOT(niOO0l10O); + wire_ni1iO1ii_dataout <= ni1iilOi WHEN niOlOl0Ol = '1' ELSE ni1il0il; + wire_ni1iO1il_dataout <= ni1il1OO WHEN niOlOl0Ol = '1' ELSE ni1illli; + wire_ni1iO1iO_dataout <= ni1il01i WHEN niOlOl0Ol = '1' ELSE ni1illll; + wire_ni1iO1l_dataout <= k_hip(19) OR niOO0l10O; + wire_ni1iO1li_dataout <= ni1il01l WHEN niOlOl0Ol = '1' ELSE ni1illlO; + wire_ni1iO1ll_dataout <= ni1il01O WHEN niOlOl0Ol = '1' ELSE ni1illOi; + wire_ni1iO1lO_dataout <= ni1il00i WHEN niOlOl0Ol = '1' ELSE ni1illOl; + wire_ni1iO1O_dataout <= k_hip(20) OR niOO0l10O; + wire_ni1iO1Oi_dataout <= ni1il00l WHEN niOlOl0Ol = '1' ELSE ni1illOO; + wire_ni1iO1Ol_dataout <= ni1il00O WHEN niOlOl0Ol = '1' ELSE ni1ilO1i; + wire_ni1iO1OO_dataout <= ni1il0ii WHEN niOlOl0Ol = '1' ELSE ni1ilO1l; + wire_ni1iOi0i_dataout <= wire_ni1iOiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOi0l_dataout <= wire_ni1iOiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOi0O_dataout <= wire_ni1iOiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOi1i_dataout <= wire_ni1iOili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOi1l_dataout <= wire_ni1iOill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOi1O_dataout <= wire_ni1iOilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOiii_dataout <= wire_ni1iOl1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOiil_dataout <= wire_nii0Oili_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOl1l_dataout; + wire_ni1iOiiO_dataout <= wire_nii0Oill_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOl1O_dataout; + wire_ni1iOili_dataout <= wire_nii0OilO_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOl0i_dataout; + wire_ni1iOill_dataout <= wire_nii0OiOi_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOl0l_dataout; + wire_ni1iOilO_dataout <= wire_nii0OiOl_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOl0O_dataout; + wire_ni1iOiOi_dataout <= wire_nii0OiOO_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOlii_dataout; + wire_ni1iOiOl_dataout <= wire_nii0Ol1i_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOlil_dataout; + wire_ni1iOiOO_dataout <= wire_nii0Ol1l_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOliO_dataout; + wire_ni1iOl0i_dataout <= ni1illll WHEN niOlOl0Ol = '1' ELSE ni1iO00O; + wire_ni1iOl0l_dataout <= ni1illlO WHEN niOlOl0Ol = '1' ELSE ni1iO0ii; + wire_ni1iOl0O_dataout <= ni1illOi WHEN niOlOl0Ol = '1' ELSE ni1iO0il; + wire_ni1iOl1i_dataout <= wire_nii0Ol1O_dataout WHEN niOlOi0lO = '1' ELSE wire_ni1iOlli_dataout; + wire_ni1iOl1l_dataout <= ni1il0il WHEN niOlOl0Ol = '1' ELSE ni1ilO1O; + wire_ni1iOl1O_dataout <= ni1illli WHEN niOlOl0Ol = '1' ELSE ni1iO00l; + wire_ni1iOlii_dataout <= ni1illOl WHEN niOlOl0Ol = '1' ELSE ni1iO0iO; + wire_ni1iOlil_dataout <= ni1illOO WHEN niOlOl0Ol = '1' ELSE ni1iO0li; + wire_ni1iOliO_dataout <= ni1ilO1i WHEN niOlOl0Ol = '1' ELSE ni1iO0ll; + wire_ni1iOlli_dataout <= ni1ilO1l WHEN niOlOl0Ol = '1' ELSE ni1iO0lO; + wire_ni1iOO0i_dataout <= niOlOi0Oi AND NOT(wire_niO01lOO_dataout); + wire_ni1iOO0l_dataout <= wire_ni1iOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOO0O_dataout <= wire_ni1iOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOOii_dataout <= wire_ni1iOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOOil_dataout <= wire_ni1iOOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1iOOll_dataout <= wire_ni1iOOOO_dataout AND NOT(niOlOO01i); + wire_ni1iOOlO_dataout <= wire_ni1l111i_dataout AND NOT(niOlOO01i); + wire_ni1iOOOi_dataout <= wire_ni1l111l_dataout AND NOT(niOlOO01i); + wire_ni1iOOOl_dataout <= wire_ni1l111O_dataout AND NOT(niOlOO01i); + wire_ni1iOOOO_dataout <= wire_w_lg_niOlOi0OO11197w(0) WHEN niOlOii1l = '1' ELSE wire_ni1l110i_dataout; + wire_ni1l001i_dataout <= ni1l10ll WHEN niOlOl0Ol = '1' ELSE ni1l1O1O; + wire_ni1l001l_dataout <= ni1l10lO WHEN niOlOl0Ol = '1' ELSE ni1l1O0i; + wire_ni1l010i_dataout <= wire_nii0O00i_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l01Oi_dataout; + wire_ni1l010l_dataout <= wire_nii0O00l_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l01Ol_dataout; + wire_ni1l010O_dataout <= wire_nii0O00O_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l01OO_dataout; + wire_ni1l011i_dataout <= wire_nii0O01i_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l01li_dataout; + wire_ni1l011l_dataout <= wire_nii0O01l_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l01ll_dataout; + wire_ni1l011O_dataout <= wire_nii0O01O_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l01lO_dataout; + wire_ni1l01ii_dataout <= wire_nii0O0ii_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l001i_dataout; + wire_ni1l01il_dataout <= wire_nii0O0il_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l001l_dataout; + wire_ni1l01iO_dataout <= ni1l1lll WHEN niOlOl0Ol = '1' ELSE ni1l10Oi; + wire_ni1l01li_dataout <= ni1l100l WHEN niOlOl0Ol = '1' ELSE ni1l1llO; + wire_ni1l01ll_dataout <= ni1l100O WHEN niOlOl0Ol = '1' ELSE ni1l1lOi; + wire_ni1l01lO_dataout <= ni1l10ii WHEN niOlOl0Ol = '1' ELSE ni1l1lOl; + wire_ni1l01Oi_dataout <= ni1l10il WHEN niOlOl0Ol = '1' ELSE ni1l1lOO; + wire_ni1l01Ol_dataout <= ni1l10iO WHEN niOlOl0Ol = '1' ELSE ni1l1O1i; + wire_ni1l01OO_dataout <= ni1l10li WHEN niOlOl0Ol = '1' ELSE ni1l1O1l; + wire_ni1l0i0i_dataout <= wire_ni1l0iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0i0l_dataout <= wire_ni1l0iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0i0O_dataout <= wire_ni1l0iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0i1i_dataout <= wire_ni1l0ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0i1l_dataout <= wire_ni1l0ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0i1O_dataout <= wire_ni1l0ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0iii_dataout <= wire_ni1l0l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0iil_dataout <= wire_ni1l0l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0iiO_dataout <= wire_ni1l0l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0ili_dataout <= wire_nii0O1OO_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0l0i_dataout; + wire_ni1l0ill_dataout <= wire_nii0O01i_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0l0l_dataout; + wire_ni1l0ilO_dataout <= wire_nii0O01l_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0l0O_dataout; + wire_ni1l0iO_dataout <= wire_ni1liOi_dataout WHEN niOO0l1li = '1' ELSE wire_ni1l0Oi_dataout; + wire_ni1l0iOi_dataout <= wire_nii0O01O_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0lii_dataout; + wire_ni1l0iOl_dataout <= wire_nii0O00i_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0lil_dataout; + wire_ni1l0iOO_dataout <= wire_nii0O00l_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0liO_dataout; + wire_ni1l0l0i_dataout <= ni1l10Oi WHEN niOlOl0Ol = '1' ELSE ni1l1O0l; + wire_ni1l0l0l_dataout <= ni1l1llO WHEN niOlOl0Ol = '1' ELSE ni1l00ii; + wire_ni1l0l0O_dataout <= ni1l1lOi WHEN niOlOl0Ol = '1' ELSE ni1l00il; + wire_ni1l0l1i_dataout <= wire_nii0O00O_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0lli_dataout; + wire_ni1l0l1l_dataout <= wire_nii0O0ii_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0lll_dataout; + wire_ni1l0l1O_dataout <= wire_nii0O0il_dataout WHEN niOlOii0i = '1' ELSE wire_ni1l0llO_dataout; + wire_ni1l0li_dataout <= wire_ni1liOl_dataout WHEN niOO0l1li = '1' ELSE wire_ni1l0Ol_dataout; + wire_ni1l0lii_dataout <= ni1l1lOl WHEN niOlOl0Ol = '1' ELSE ni1l00iO; + wire_ni1l0lil_dataout <= ni1l1lOO WHEN niOlOl0Ol = '1' ELSE ni1l00li; + wire_ni1l0liO_dataout <= ni1l1O1i WHEN niOlOl0Ol = '1' ELSE ni1l00ll; + wire_ni1l0ll_dataout <= wire_ni1l0lO_dataout AND NOT(niOO0l1li); + wire_ni1l0lli_dataout <= ni1l1O1l WHEN niOlOl0Ol = '1' ELSE ni1l00lO; + wire_ni1l0lll_dataout <= ni1l1O1O WHEN niOlOl0Ol = '1' ELSE ni1l00Oi; + wire_ni1l0llO_dataout <= ni1l1O0i WHEN niOlOl0Ol = '1' ELSE ni1l00Ol; + wire_ni1l0lO_dataout <= wire_ni1liil_dataout WHEN ni1ll0O = '1' ELSE ni1iO0i; + wire_ni1l0Oi_dataout <= wire_ni1liiO_dataout WHEN ni1ll0O = '1' ELSE wire_ni1l0OO_dataout; + wire_ni1l0Ol_dataout <= wire_ni1lili_dataout WHEN ni1ll0O = '1' ELSE wire_ni1li1i_dataout; + wire_ni1l0Oll_dataout <= wire_ni1li10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0OlO_dataout <= wire_ni1li10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0OO_dataout <= wire_ni1li0i_dataout WHEN ni1ll0l = '1' ELSE ni1iOOi; + wire_ni1l0OOi_dataout <= wire_ni1li1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0OOl_dataout <= wire_ni1li1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l0OOO_dataout <= wire_ni1li1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l10i_dataout <= wire_ni1l1li_dataout AND NOT(niOO0l1OO); + wire_ni1l10l_dataout <= wire_ni1l0iO_dataout AND NOT(niOO0l1OO); + wire_ni1l10O_dataout <= wire_ni1l0li_dataout AND NOT(niOO0l1OO); + wire_ni1l10Ol_dataout <= wire_ni1l1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l10OO_dataout <= wire_ni1l1iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l110i_dataout <= ni1iOlOO OR niOlOii1i; + wire_ni1l110l_dataout <= wire_ni1l11il_o(0) WHEN niOlOii1i = '1' ELSE ni1iOO1i; + wire_ni1l110O_dataout <= wire_ni1l11il_o(1) WHEN niOlOii1i = '1' ELSE ni1iOO1l; + wire_ni1l111i_dataout <= wire_ni1l11li_o(1) WHEN niOlOii1l = '1' ELSE wire_ni1l110l_dataout; + wire_ni1l111l_dataout <= wire_ni1l11li_o(2) WHEN niOlOii1l = '1' ELSE wire_ni1l110O_dataout; + wire_ni1l111O_dataout <= wire_ni1l11li_o(3) WHEN niOlOii1l = '1' ELSE wire_ni1l11ii_dataout; + wire_ni1l11ii_dataout <= wire_ni1l11il_o(2) WHEN niOlOii1i = '1' ELSE ni1iOO1O; + wire_ni1l11O_dataout <= wire_ni1l0ll_dataout AND NOT(niOO0l1OO); + wire_ni1l1i0i_dataout <= wire_ni1l1iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1i0l_dataout <= wire_ni1l1iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1i0O_dataout <= wire_ni1l1iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1i1i_dataout <= wire_ni1l1ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1i1l_dataout <= wire_ni1l1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1i1O_dataout <= wire_ni1l1ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1ii_dataout <= wire_ni1l1ll_dataout AND NOT(niOO0l1OO); + wire_ni1l1iii_dataout <= wire_ni1l1l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1iil_dataout <= wire_nii0O1OO_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1l1l_dataout; + wire_ni1l1iiO_dataout <= wire_nii0O01i_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1l1O_dataout; + wire_ni1l1il_dataout <= wire_ni1l1iO_dataout AND NOT(niOO0l1OO); + wire_ni1l1ili_dataout <= wire_nii0O01l_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1l0i_dataout; + wire_ni1l1ill_dataout <= wire_nii0O01O_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1l0l_dataout; + wire_ni1l1ilO_dataout <= wire_nii0O00i_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1l0O_dataout; + wire_ni1l1iO_dataout <= wire_ni1l1OO_dataout WHEN niOO0l1iO = '1' ELSE wire_ni1l1lO_dataout; + wire_ni1l1iOi_dataout <= wire_nii0O00l_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1lii_dataout; + wire_ni1l1iOl_dataout <= wire_nii0O00O_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1lil_dataout; + wire_ni1l1iOO_dataout <= wire_nii0O0ii_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1liO_dataout; + wire_ni1l1l0i_dataout <= ni1l100O AND NOT(niOlOl0Ol); + wire_ni1l1l0l_dataout <= ni1l10ii AND NOT(niOlOl0Ol); + wire_ni1l1l0O_dataout <= ni1l10il AND NOT(niOlOl0Ol); + wire_ni1l1l1i_dataout <= wire_nii0O0il_dataout WHEN niOlOiiOO = '1' ELSE wire_ni1l1lli_dataout; + wire_ni1l1l1l_dataout <= ni1l1lll AND NOT(niOlOl0Ol); + wire_ni1l1l1O_dataout <= ni1l100l AND NOT(niOlOl0Ol); + wire_ni1l1li_dataout <= ni1iOlO OR niOO0l1iO; + wire_ni1l1lii_dataout <= ni1l10iO AND NOT(niOlOl0Ol); + wire_ni1l1lil_dataout <= ni1l10li AND NOT(niOlOl0Ol); + wire_ni1l1liO_dataout <= ni1l10ll AND NOT(niOlOl0Ol); + wire_ni1l1ll_dataout <= ni1iOOO OR niOO0l1iO; + wire_ni1l1lli_dataout <= ni1l10lO AND NOT(niOlOl0Ol); + wire_ni1l1lO_dataout <= ni1l11i AND NOT((ni1llil OR wire_ni1iO0l_dataout)); + wire_ni1l1O0O_dataout <= wire_ni1l1OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1Oii_dataout <= wire_ni1l011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1Oil_dataout <= wire_ni1l011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1OiO_dataout <= wire_ni1l011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1Oli_dataout <= wire_ni1l010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1Oll_dataout <= wire_ni1l010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1OlO_dataout <= wire_ni1l010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1OO_dataout <= ni1l11i OR (wire_ni1lOlO_w_lg_ni1ll0O2564w(0) OR wire_ni1llii_w_lg_ni1llil2568w(0)); + wire_ni1l1OOi_dataout <= wire_ni1l01ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1OOl_dataout <= wire_ni1l01il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1l1OOO_dataout <= wire_nii0O1OO_dataout WHEN niOlOii1O = '1' ELSE wire_ni1l01iO_dataout; + wire_ni1li00i_dataout <= ni1l00ll WHEN niOlOl0Ol = '1' ELSE ni1l0O0O; + wire_ni1li00l_dataout <= ni1l00lO WHEN niOlOl0Ol = '1' ELSE ni1l0Oii; + wire_ni1li00O_dataout <= ni1l00Oi WHEN niOlOl0Ol = '1' ELSE ni1l0Oil; + wire_ni1li01i_dataout <= ni1l00il WHEN niOlOl0Ol = '1' ELSE ni1l0O1O; + wire_ni1li01l_dataout <= ni1l00iO WHEN niOlOl0Ol = '1' ELSE ni1l0O0i; + wire_ni1li01O_dataout <= ni1l00li WHEN niOlOl0Ol = '1' ELSE ni1l0O0l; + wire_ni1li0i_dataout <= wire_ni1li0O_dataout WHEN niOO0l01l = '1' ELSE ni1iOOi; + wire_ni1li0ii_dataout <= ni1l00Ol WHEN niOlOl0Ol = '1' ELSE ni1l0OiO; + wire_ni1li0l_dataout <= wire_ni1liii_dataout WHEN niOO0l01l = '1' ELSE ni1iOOl; + wire_ni1li0O_dataout <= wire_n0OOO0O_q(66) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_n0OOO0O_q(2); + wire_ni1li10i_dataout <= wire_ni1li1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1li10l_dataout <= wire_nii0O1OO_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li1Ol_dataout; + wire_ni1li10O_dataout <= wire_nii0O01i_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li1OO_dataout; + wire_ni1li11i_dataout <= wire_ni1li1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1li11l_dataout <= wire_ni1li1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1li11O_dataout <= wire_ni1li1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1li1i_dataout <= wire_ni1li0l_dataout WHEN ni1ll0l = '1' ELSE ni1iOOl; + wire_ni1li1ii_dataout <= wire_nii0O01l_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li01i_dataout; + wire_ni1li1il_dataout <= wire_nii0O01O_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li01l_dataout; + wire_ni1li1iO_dataout <= wire_nii0O00i_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li01O_dataout; + wire_ni1li1li_dataout <= wire_nii0O00l_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li00i_dataout; + wire_ni1li1ll_dataout <= wire_nii0O00O_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li00l_dataout; + wire_ni1li1lO_dataout <= wire_nii0O0ii_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li00O_dataout; + wire_ni1li1Oi_dataout <= wire_nii0O0il_dataout WHEN niOlOii0O = '1' ELSE wire_ni1li0ii_dataout; + wire_ni1li1Ol_dataout <= ni1l1O0l WHEN niOlOl0Ol = '1' ELSE ni1l00OO; + wire_ni1li1OO_dataout <= ni1l00ii WHEN niOlOl0Ol = '1' ELSE ni1l0O1l; + wire_ni1lii0O_dataout <= wire_ni1liiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liii_dataout <= wire_n0OOO0O_q(98) WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_n0OOO0O_q(34); + wire_ni1liiii_dataout <= wire_ni1lil1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liiil_dataout <= wire_ni1lil1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liiiO_dataout <= wire_ni1lil1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liil_dataout <= ni1iO0i OR k_hip(0); + wire_ni1liili_dataout <= wire_ni1lil0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liill_dataout <= wire_ni1lil0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liilO_dataout <= wire_ni1lil0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liiO_dataout <= wire_ni1lill_dataout WHEN k_hip(0) = '1' ELSE wire_n0OOO0O_q(66); + wire_ni1liiOi_dataout <= wire_ni1lilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liiOl_dataout <= wire_ni1lilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1liiOO_dataout <= wire_nii0O1OO_dataout WHEN niOlOiiil = '1' ELSE wire_ni1liliO_dataout; + wire_ni1lil0i_dataout <= wire_nii0O00i_dataout WHEN niOlOiiil = '1' ELSE wire_ni1lilOi_dataout; + wire_ni1lil0l_dataout <= wire_nii0O00l_dataout WHEN niOlOiiil = '1' ELSE wire_ni1lilOl_dataout; + wire_ni1lil0O_dataout <= wire_nii0O00O_dataout WHEN niOlOiiil = '1' ELSE wire_ni1lilOO_dataout; + wire_ni1lil1i_dataout <= wire_nii0O01i_dataout WHEN niOlOiiil = '1' ELSE wire_ni1lilli_dataout; + wire_ni1lil1l_dataout <= wire_nii0O01l_dataout WHEN niOlOiiil = '1' ELSE wire_ni1lilll_dataout; + wire_ni1lil1O_dataout <= wire_nii0O01O_dataout WHEN niOlOiiil = '1' ELSE wire_ni1lillO_dataout; + wire_ni1lili_dataout <= wire_ni1lilO_dataout WHEN k_hip(0) = '1' ELSE wire_n0OOO0O_q(98); + wire_ni1lilii_dataout <= wire_nii0O0ii_dataout WHEN niOlOiiil = '1' ELSE wire_ni1liO1i_dataout; + wire_ni1lilil_dataout <= wire_nii0O0il_dataout WHEN niOlOiiil = '1' ELSE wire_ni1liO1l_dataout; + wire_ni1liliO_dataout <= ni1l00OO WHEN niOlOl0Ol = '1' ELSE ni1l0Oli; + wire_ni1lill_dataout <= wire_n0OOO0O_q(2) WHEN wire_ni1lOlO_w_lg_ni1iO0i2556w(0) = '1' ELSE ni1iOOi; + wire_ni1lilli_dataout <= ni1l0O1l WHEN niOlOl0Ol = '1' ELSE ni1li0lO; + wire_ni1lilll_dataout <= ni1l0O1O WHEN niOlOl0Ol = '1' ELSE ni1li0Oi; + wire_ni1lillO_dataout <= ni1l0O0i WHEN niOlOl0Ol = '1' ELSE ni1li0Ol; + wire_ni1lilO_dataout <= wire_n0OOO0O_q(34) WHEN wire_ni1lOlO_w_lg_ni1iO0i2556w(0) = '1' ELSE ni1iOOl; + wire_ni1lilOi_dataout <= ni1l0O0l WHEN niOlOl0Ol = '1' ELSE ni1li0OO; + wire_ni1lilOl_dataout <= ni1l0O0O WHEN niOlOl0Ol = '1' ELSE ni1lii1i; + wire_ni1lilOO_dataout <= ni1l0Oii WHEN niOlOl0Ol = '1' ELSE ni1lii1l; + wire_ni1liO1i_dataout <= ni1l0Oil WHEN niOlOl0Ol = '1' ELSE ni1lii1O; + wire_ni1liO1l_dataout <= ni1l0OiO WHEN niOlOl0Ol = '1' ELSE ni1lii0i; + wire_ni1liOi_dataout <= wire_ni1liOO_dataout WHEN k_hip(0) = '1' ELSE ni1iOOi; + wire_ni1liOl_dataout <= wire_ni1ll1i_dataout WHEN k_hip(0) = '1' ELSE ni1iOOl; + wire_ni1liOO_dataout <= wire_n0OOO0O_q(34) WHEN (NOT wire_n0OOO0O_q(93)) = '1' ELSE wire_n0OOO0O_q(2); + wire_ni1ll00i_dataout <= ni1l0Oli WHEN niOlOl0Ol = '1' ELSE ni1lii0l; + wire_ni1ll00l_dataout <= ni1li0lO WHEN niOlOl0Ol = '1' ELSE ni1liOii; + wire_ni1ll00O_dataout <= ni1li0Oi WHEN niOlOl0Ol = '1' ELSE ni1liOil; + wire_ni1ll01i_dataout <= wire_nii0O00O_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll0li_dataout; + wire_ni1ll01l_dataout <= wire_nii0O0ii_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll0ll_dataout; + wire_ni1ll01O_dataout <= wire_nii0O0il_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll0lO_dataout; + wire_ni1ll0ii_dataout <= ni1li0Ol WHEN niOlOl0Ol = '1' ELSE ni1liOiO; + wire_ni1ll0il_dataout <= ni1li0OO WHEN niOlOl0Ol = '1' ELSE ni1liOli; + wire_ni1ll0iO_dataout <= ni1lii1i WHEN niOlOl0Ol = '1' ELSE ni1liOll; + wire_ni1ll0li_dataout <= ni1lii1l WHEN niOlOl0Ol = '1' ELSE ni1liOlO; + wire_ni1ll0ll_dataout <= ni1lii1O WHEN niOlOl0Ol = '1' ELSE ni1liOOi; + wire_ni1ll0lO_dataout <= ni1lii0i WHEN niOlOl0Ol = '1' ELSE ni1liOOl; + wire_ni1ll10i_dataout <= wire_ni1ll1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll10l_dataout <= wire_ni1ll1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll10O_dataout <= wire_ni1ll1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll11i_dataout <= wire_ni1ll1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll11l_dataout <= wire_ni1ll1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll11O_dataout <= wire_ni1ll1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll1i_dataout <= wire_n0OOO0O_q(2) WHEN (NOT wire_n0OOO0O_q(93)) = '1' ELSE wire_n0OOO0O_q(34); + wire_ni1ll1ii_dataout <= wire_ni1ll01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll1il_dataout <= wire_ni1ll01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll1iO_dataout <= wire_ni1ll01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1ll1li_dataout <= wire_nii0O1OO_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll00i_dataout; + wire_ni1ll1ll_dataout <= wire_nii0O01i_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll00l_dataout; + wire_ni1ll1lO_dataout <= wire_nii0O01l_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll00O_dataout; + wire_ni1ll1Oi_dataout <= wire_nii0O01O_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll0ii_dataout; + wire_ni1ll1Ol_dataout <= wire_nii0O00i_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll0il_dataout; + wire_ni1ll1OO_dataout <= wire_nii0O00l_dataout WHEN niOlOiili = '1' ELSE wire_ni1ll0iO_dataout; + wire_ni1llill_dataout <= wire_ni1lll0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1llilO_dataout <= wire_ni1lll0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lliOi_dataout <= wire_ni1lllii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lliOl_dataout <= wire_ni1lllil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lliOO_dataout <= wire_ni1llliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lll0i_dataout <= wire_ni1lllOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lll0l_dataout <= wire_nii0O1OO_dataout WHEN niOlOiilO = '1' ELSE wire_ni1lllOl_dataout; + wire_ni1lll0O_dataout <= wire_nii0O01i_dataout WHEN niOlOiilO = '1' ELSE wire_ni1lllOO_dataout; + wire_ni1lll1i_dataout <= wire_ni1lllli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lll1l_dataout <= wire_ni1lllll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lll1O_dataout <= wire_ni1llllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lllii_dataout <= wire_nii0O01l_dataout WHEN niOlOiilO = '1' ELSE wire_ni1llO1i_dataout; + wire_ni1lllil_dataout <= wire_nii0O01O_dataout WHEN niOlOiilO = '1' ELSE wire_ni1llO1l_dataout; + wire_ni1llliO_dataout <= wire_nii0O00i_dataout WHEN niOlOiilO = '1' ELSE wire_ni1llO1O_dataout; + wire_ni1lllli_dataout <= wire_nii0O00l_dataout WHEN niOlOiilO = '1' ELSE wire_ni1llO0i_dataout; + wire_ni1lllll_dataout <= wire_nii0O00O_dataout WHEN niOlOiilO = '1' ELSE wire_ni1llO0l_dataout; + wire_ni1llllO_dataout <= wire_nii0O0ii_dataout WHEN niOlOiilO = '1' ELSE wire_ni1llO0O_dataout; + wire_ni1lllOi_dataout <= wire_nii0O0il_dataout WHEN niOlOiilO = '1' ELSE wire_ni1llOii_dataout; + wire_ni1lllOl_dataout <= ni1lii0l WHEN niOlOl0Ol = '1' ELSE ni1liOOO; + wire_ni1lllOO_dataout <= ni1liOii WHEN niOlOl0Ol = '1' ELSE ni1lli1l; + wire_ni1llO0i_dataout <= ni1liOll WHEN niOlOl0Ol = '1' ELSE ni1lli0O; + wire_ni1llO0l_dataout <= ni1liOlO WHEN niOlOl0Ol = '1' ELSE ni1lliii; + wire_ni1llO0O_dataout <= ni1liOOi WHEN niOlOl0Ol = '1' ELSE ni1lliil; + wire_ni1llO1i_dataout <= ni1liOil WHEN niOlOl0Ol = '1' ELSE ni1lli1O; + wire_ni1llO1l_dataout <= ni1liOiO WHEN niOlOl0Ol = '1' ELSE ni1lli0i; + wire_ni1llO1O_dataout <= ni1liOli WHEN niOlOl0Ol = '1' ELSE ni1lli0l; + wire_ni1llOii_dataout <= ni1liOOl WHEN niOlOl0Ol = '1' ELSE ni1lliiO; + wire_ni1lO00i_dataout <= wire_nii0O00i_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lO0Oi_dataout; + wire_ni1lO00l_dataout <= wire_nii0O00l_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lO0Ol_dataout; + wire_ni1lO00O_dataout <= wire_nii0O00O_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lO0OO_dataout; + wire_ni1lO01i_dataout <= wire_nii0O01i_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lO0li_dataout; + wire_ni1lO01l_dataout <= wire_nii0O01l_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lO0ll_dataout; + wire_ni1lO01O_dataout <= wire_nii0O01O_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lO0lO_dataout; + wire_ni1lO0ii_dataout <= wire_nii0O0ii_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lOi1i_dataout; + wire_ni1lO0il_dataout <= wire_nii0O0il_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lOi1l_dataout; + wire_ni1lO0iO_dataout <= ni1liOOO WHEN niOlOl0Ol = '1' ELSE ni1llili; + wire_ni1lO0li_dataout <= ni1lli1l WHEN niOlOl0Ol = '1' ELSE ni1llOlO; + wire_ni1lO0ll_dataout <= ni1lli1O WHEN niOlOl0Ol = '1' ELSE ni1llOOi; + wire_ni1lO0lO_dataout <= ni1lli0i WHEN niOlOl0Ol = '1' ELSE ni1llOOl; + wire_ni1lO0Oi_dataout <= ni1lli0l WHEN niOlOl0Ol = '1' ELSE ni1llOOO; + wire_ni1lO0Ol_dataout <= ni1lli0O WHEN niOlOl0Ol = '1' ELSE ni1lO11i; + wire_ni1lO0OO_dataout <= ni1lliii WHEN niOlOl0Ol = '1' ELSE ni1lO11l; + wire_ni1lO10O_dataout <= wire_ni1lO1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1ii_dataout <= wire_ni1lO01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1il_dataout <= wire_ni1lO01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1iO_dataout <= wire_ni1lO01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1li_dataout <= wire_ni1lO00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1ll_dataout <= wire_ni1lO00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1lO_dataout <= wire_ni1lO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1Oi_dataout <= wire_ni1lO0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1Ol_dataout <= wire_ni1lO0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lO1OO_dataout <= wire_nii0O1OO_dataout WHEN niOlOiiOl = '1' ELSE wire_ni1lO0iO_dataout; + wire_ni1lOi1i_dataout <= ni1lliil WHEN niOlOl0Ol = '1' ELSE ni1lO11O; + wire_ni1lOi1l_dataout <= ni1lliiO WHEN niOlOl0Ol = '1' ELSE ni1lO10i; + wire_ni1lOill_dataout <= niOlOiiOO AND NOT(wire_niO01lOO_dataout); + wire_ni1lOilO_dataout <= wire_ni1lOl1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lOiOi_dataout <= wire_ni1lOl0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lOiOl_dataout <= wire_ni1lOl0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lOiOO_dataout <= wire_ni1lOl0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1lOl0i_dataout <= wire_ni1lOlil_dataout AND NOT(niOlOO1ii); + wire_ni1lOl0l_dataout <= wire_ni1lOliO_dataout AND NOT(niOlOO1ii); + wire_ni1lOl0O_dataout <= wire_ni1lOlli_dataout AND NOT(niOlOO1ii); + wire_ni1lOl1O_dataout <= wire_ni1lOlii_dataout AND NOT(niOlOO1ii); + wire_ni1lOlii_dataout <= wire_w_lg_niOlOil1l11116w(0) WHEN niOlOil0i = '1' ELSE wire_ni1lOlll_dataout; + wire_ni1lOlil_dataout <= wire_ni1lOO1l_o(1) WHEN niOlOil0i = '1' ELSE wire_ni1lOllO_dataout; + wire_ni1lOliO_dataout <= wire_ni1lOO1l_o(2) WHEN niOlOil0i = '1' ELSE wire_ni1lOlOi_dataout; + wire_ni1lOlli_dataout <= wire_ni1lOO1l_o(3) WHEN niOlOil0i = '1' ELSE wire_ni1lOlOl_dataout; + wire_ni1lOlll_dataout <= ni1lOiii OR niOlOil1O; + wire_ni1lOllO_dataout <= wire_ni1lOlOO_o(0) WHEN niOlOil1O = '1' ELSE ni1lOiil; + wire_ni1lOlOi_dataout <= wire_ni1lOlOO_o(1) WHEN niOlOil1O = '1' ELSE ni1lOiiO; + wire_ni1lOlOl_dataout <= wire_ni1lOlOO_o(2) WHEN niOlOil1O = '1' ELSE ni1lOili; + wire_ni1lOOO_dataout <= wire_ni1O0lO_o AND NOT(niOO0l1OO); + wire_ni1O000i_dataout <= wire_nii0lOii_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O00Oi_dataout; + wire_ni1O000l_dataout <= wire_nii0lOil_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O00Ol_dataout; + wire_ni1O000O_dataout <= wire_nii0lOiO_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O00OO_dataout; + wire_ni1O001i_dataout <= wire_ni1O00li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O001l_dataout <= wire_nii0lO0l_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O00ll_dataout; + wire_ni1O001O_dataout <= wire_nii0lO0O_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O00lO_dataout; + wire_ni1O00i_dataout <= wire_ni010ii_dataout AND NOT(niOO0l1OO); + wire_ni1O00ii_dataout <= wire_nii0lOli_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O0i1i_dataout; + wire_ni1O00il_dataout <= wire_nii0lOll_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O0i1l_dataout; + wire_ni1O00iO_dataout <= wire_nii0lOlO_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O0i1O_dataout; + wire_ni1O00l_dataout <= wire_ni1O0il_dataout AND NOT(niOO0l1OO); + wire_ni1O00li_dataout <= wire_nii0lOOi_dataout WHEN niOlOil0O = '1' ELSE wire_ni1O0i0i_dataout; + wire_ni1O00ll_dataout <= ni1O110l WHEN niOlOl0Ol = '1' ELSE ni1O1ilO; + wire_ni1O00lO_dataout <= ni1O1i0i WHEN niOlOl0Ol = '1' ELSE ni1O1OOl; + wire_ni1O00O_dataout <= wire_ni1Oill_dataout AND NOT(niOO0l1OO); + wire_ni1O00Oi_dataout <= ni1O1i0l WHEN niOlOl0Ol = '1' ELSE ni1O1OOO; + wire_ni1O00Ol_dataout <= ni1O1i0O WHEN niOlOl0Ol = '1' ELSE ni1O011i; + wire_ni1O00OO_dataout <= ni1O1iii WHEN niOlOl0Ol = '1' ELSE ni1O011l; + wire_ni1O01i_dataout <= wire_ni1OiiO_dataout AND NOT(niOO0l1OO); + wire_ni1O01il_dataout <= wire_ni1O001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O01iO_dataout <= wire_ni1O001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O01l_dataout <= wire_ni1Oili_dataout AND NOT(niOO0l1OO); + wire_ni1O01li_dataout <= wire_ni1O000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O01ll_dataout <= wire_ni1O000l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O01lO_dataout <= wire_ni1O000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O01O_dataout <= niOO0l00l AND NOT(niOO0l1OO); + wire_ni1O01Oi_dataout <= wire_ni1O00ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O01Ol_dataout <= wire_ni1O00il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O01OO_dataout <= wire_ni1O00iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0i0i_dataout <= ni1O1ill WHEN niOlOl0Ol = '1' ELSE ni1O010O; + wire_ni1O0i1i_dataout <= ni1O1iil WHEN niOlOl0Ol = '1' ELSE ni1O011O; + wire_ni1O0i1l_dataout <= ni1O1iiO WHEN niOlOl0Ol = '1' ELSE ni1O010i; + wire_ni1O0i1O_dataout <= ni1O1ili WHEN niOlOl0Ol = '1' ELSE ni1O010l; + wire_ni1O0ii_dataout <= wire_ni1OilO_dataout AND NOT(niOO0l1OO); + wire_ni1O0il_dataout <= wire_ni1OOOO_dataout WHEN ni1ll0O = '1' ELSE ni1lOli; + wire_ni1O0l0i_dataout <= wire_ni1O0lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0l0l_dataout <= wire_ni1O0lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0l0O_dataout <= wire_ni1O0lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0l1O_dataout <= wire_ni1O0llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0lii_dataout <= wire_ni1O0O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0lil_dataout <= wire_ni1O0O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0liO_dataout <= wire_ni1O0O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0ll_dataout <= wire_ni0111l_dataout WHEN ni1llil = '1' ELSE ni1llll; + wire_ni1O0lli_dataout <= wire_ni1O0O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0lll_dataout <= wire_ni1O0O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O0llO_dataout <= wire_nii0lO0l_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0O0O_dataout; + wire_ni1O0lOi_dataout <= wire_nii0lO0O_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0Oii_dataout; + wire_ni1O0lOl_dataout <= wire_nii0lOii_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0Oil_dataout; + wire_ni1O0lOO_dataout <= wire_nii0lOil_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0OiO_dataout; + wire_ni1O0O0i_dataout <= wire_nii0lOlO_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0OOi_dataout; + wire_ni1O0O0l_dataout <= wire_nii0lOOi_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0OOl_dataout; + wire_ni1O0O0O_dataout <= ni1O1ilO WHEN niOlOl0Ol = '1' ELSE ni1O01ii; + wire_ni1O0O1i_dataout <= wire_nii0lOiO_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0Oli_dataout; + wire_ni1O0O1l_dataout <= wire_nii0lOli_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0Oll_dataout; + wire_ni1O0O1O_dataout <= wire_nii0lOll_dataout WHEN niOlOilil = '1' ELSE wire_ni1O0OlO_dataout; + wire_ni1O0Oii_dataout <= ni1O1OOl WHEN niOlOl0Ol = '1' ELSE ni1O0iiO; + wire_ni1O0Oil_dataout <= ni1O1OOO WHEN niOlOl0Ol = '1' ELSE ni1O0ili; + wire_ni1O0OiO_dataout <= ni1O011i WHEN niOlOl0Ol = '1' ELSE ni1O0ill; + wire_ni1O0Oli_dataout <= ni1O011l WHEN niOlOl0Ol = '1' ELSE ni1O0ilO; + wire_ni1O0Oll_dataout <= ni1O011O WHEN niOlOl0Ol = '1' ELSE ni1O0iOi; + wire_ni1O0OlO_dataout <= ni1O010i WHEN niOlOl0Ol = '1' ELSE ni1O0iOl; + wire_ni1O0OOi_dataout <= ni1O010l WHEN niOlOl0Ol = '1' ELSE ni1O0iOO; + wire_ni1O0OOl_dataout <= ni1O010O WHEN niOlOl0Ol = '1' ELSE ni1O0l1i; + wire_ni1O100i_dataout <= wire_nii0lOiO_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O10Oi_dataout; + wire_ni1O100l_dataout <= wire_nii0lOli_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O10Ol_dataout; + wire_ni1O100O_dataout <= wire_nii0lOll_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O10OO_dataout; + wire_ni1O101i_dataout <= wire_nii0lO0O_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O10li_dataout; + wire_ni1O101l_dataout <= wire_nii0lOii_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O10ll_dataout; + wire_ni1O101O_dataout <= wire_nii0lOil_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O10lO_dataout; + wire_ni1O10i_dataout <= ((wire_ni010ii_dataout OR wire_n0OOO0O_q(131)) AND ni1ll0O) AND NOT(niOO0l1OO); + wire_ni1O10ii_dataout <= wire_nii0lOlO_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O1i1i_dataout; + wire_ni1O10il_dataout <= wire_nii0lOOi_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O1i1l_dataout; + wire_ni1O10iO_dataout <= ni1O1i1O AND NOT(niOlOl0Ol); + wire_ni1O10l_dataout <= wire_ni1O0iO_o AND NOT(niOO0l1OO); + wire_ni1O10li_dataout <= ni1lOOlO AND NOT(niOlOl0Ol); + wire_ni1O10ll_dataout <= ni1lOOOi AND NOT(niOlOl0Ol); + wire_ni1O10lO_dataout <= ni1lOOOl AND NOT(niOlOl0Ol); + wire_ni1O10O_dataout <= wire_ni1O0ll_dataout AND NOT(niOO0l1OO); + wire_ni1O10Oi_dataout <= ni1lOOOO AND NOT(niOlOl0Ol); + wire_ni1O10Ol_dataout <= ni1O111i AND NOT(niOlOl0Ol); + wire_ni1O10OO_dataout <= ni1O111l AND NOT(niOlOl0Ol); + wire_ni1O110O_dataout <= wire_ni1O11OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11i_dataout <= wire_ni1O0Oi_o AND NOT(niOO0l1OO); + wire_ni1O11ii_dataout <= wire_ni1O101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11il_dataout <= wire_ni1O101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11iO_dataout <= wire_ni1O101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11l_dataout <= wire_ni1O0Ol_o AND NOT(niOO0l1OO); + wire_ni1O11li_dataout <= wire_ni1O100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11ll_dataout <= wire_ni1O100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11lO_dataout <= wire_ni1O100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11O_dataout <= wire_ni1O0OO_o OR niOO0l1OO; + wire_ni1O11Oi_dataout <= wire_ni1O10ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11Ol_dataout <= wire_ni1O10il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O11OO_dataout <= wire_nii0lO0l_dataout WHEN niOlOiO1l = '1' ELSE wire_ni1O10iO_dataout; + wire_ni1O1i1i_dataout <= ni1O111O AND NOT(niOlOl0Ol); + wire_ni1O1i1l_dataout <= ni1O110i AND NOT(niOlOl0Ol); + wire_ni1O1ii_dataout <= wire_n0OOO0O_q(128) AND NOT(niOO0l1OO); + wire_ni1O1il_dataout <= wire_ni1Oi1i_dataout AND NOT(niOO0l1OO); + wire_ni1O1iO_dataout <= wire_ni1Oi1l_dataout AND NOT(niOO0l1OO); + wire_ni1O1iOi_dataout <= wire_ni1O1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1iOl_dataout <= wire_ni1O1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1iOO_dataout <= wire_ni1O1liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1l0i_dataout <= wire_ni1O1lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1l0l_dataout <= wire_ni1O1lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1l0O_dataout <= wire_ni1O1lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1l1i_dataout <= wire_ni1O1lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1l1l_dataout <= wire_ni1O1lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1l1O_dataout <= wire_ni1O1llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1O1li_dataout <= wire_ni1Oi1O_dataout AND NOT(niOO0l1OO); + wire_ni1O1lii_dataout <= wire_nii0lO0l_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1O1i_dataout; + wire_ni1O1lil_dataout <= wire_nii0lO0O_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1O1l_dataout; + wire_ni1O1liO_dataout <= wire_nii0lOii_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1O1O_dataout; + wire_ni1O1ll_dataout <= wire_ni1Oi0i_dataout AND NOT(niOO0l1OO); + wire_ni1O1lli_dataout <= wire_nii0lOil_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1O0i_dataout; + wire_ni1O1lll_dataout <= wire_nii0lOiO_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1O0l_dataout; + wire_ni1O1llO_dataout <= wire_nii0lOli_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1O0O_dataout; + wire_ni1O1lO_dataout <= wire_ni1Oi0l_dataout AND NOT(niOO0l1OO); + wire_ni1O1lOi_dataout <= wire_nii0lOll_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1Oii_dataout; + wire_ni1O1lOl_dataout <= wire_nii0lOlO_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1Oil_dataout; + wire_ni1O1lOO_dataout <= wire_nii0lOOi_dataout WHEN niOlOil0l = '1' ELSE wire_ni1O1OiO_dataout; + wire_ni1O1O0i_dataout <= ni1lOOOl WHEN niOlOl0Ol = '1' ELSE ni1O1i0O; + wire_ni1O1O0l_dataout <= ni1lOOOO WHEN niOlOl0Ol = '1' ELSE ni1O1iii; + wire_ni1O1O0O_dataout <= ni1O111i WHEN niOlOl0Ol = '1' ELSE ni1O1iil; + wire_ni1O1O1i_dataout <= ni1O1i1O WHEN niOlOl0Ol = '1' ELSE ni1O110l; + wire_ni1O1O1l_dataout <= ni1lOOlO WHEN niOlOl0Ol = '1' ELSE ni1O1i0i; + wire_ni1O1O1O_dataout <= ni1lOOOi WHEN niOlOl0Ol = '1' ELSE ni1O1i0l; + wire_ni1O1Oi_dataout <= wire_ni1Oi0O_dataout AND NOT(niOO0l1OO); + wire_ni1O1Oii_dataout <= ni1O111l WHEN niOlOl0Ol = '1' ELSE ni1O1iiO; + wire_ni1O1Oil_dataout <= ni1O111O WHEN niOlOl0Ol = '1' ELSE ni1O1ili; + wire_ni1O1OiO_dataout <= ni1O110i WHEN niOlOl0Ol = '1' ELSE ni1O1ill; + wire_ni1O1Ol_dataout <= wire_ni1Oiii_dataout AND NOT(niOO0l1OO); + wire_ni1O1OO_dataout <= wire_ni1Oiil_dataout AND NOT(niOO0l1OO); + wire_ni1Oi00i_dataout <= wire_ni1Oi0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi00l_dataout <= wire_ni1Oi0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi00O_dataout <= wire_ni1Oi0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi01i_dataout <= wire_ni1Oi0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi01l_dataout <= wire_ni1Oi0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi01O_dataout <= wire_ni1Oi0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi0i_dataout <= wire_ni011li_dataout WHEN ni1llil = '1' ELSE ni1lO1i; + wire_ni1Oi0ii_dataout <= wire_nii0lO0l_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oii1i_dataout; + wire_ni1Oi0il_dataout <= wire_nii0lO0O_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oii1l_dataout; + wire_ni1Oi0iO_dataout <= wire_nii0lOii_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oii1O_dataout; + wire_ni1Oi0l_dataout <= wire_ni011ll_dataout WHEN ni1llil = '1' ELSE ni1lO1l; + wire_ni1Oi0li_dataout <= wire_nii0lOil_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oii0i_dataout; + wire_ni1Oi0ll_dataout <= wire_nii0lOiO_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oii0l_dataout; + wire_ni1Oi0lO_dataout <= wire_nii0lOli_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oii0O_dataout; + wire_ni1Oi0O_dataout <= wire_ni011lO_dataout WHEN ni1llil = '1' ELSE ni1lO1O; + wire_ni1Oi0Oi_dataout <= wire_nii0lOll_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oiiii_dataout; + wire_ni1Oi0Ol_dataout <= wire_nii0lOlO_dataout WHEN niOlOilli = '1' ELSE wire_ni1Oiiil_dataout; + wire_ni1Oi0OO_dataout <= wire_nii0lOOi_dataout WHEN niOlOilli = '1' ELSE wire_ni1OiiiO_dataout; + wire_ni1Oi1i_dataout <= wire_ni011ii_dataout WHEN ni1llil = '1' ELSE ni1llOi; + wire_ni1Oi1l_dataout <= wire_ni011il_dataout WHEN ni1llil = '1' ELSE ni1llOl; + wire_ni1Oi1O_dataout <= wire_ni011iO_dataout WHEN ni1llil = '1' ELSE ni1llOO; + wire_ni1Oi1Oi_dataout <= wire_ni1Oi0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi1Ol_dataout <= wire_ni1Oi0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oi1OO_dataout <= wire_ni1Oi0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oii0i_dataout <= ni1O0ill WHEN niOlOl0Ol = '1' ELSE ni1Oi10O; + wire_ni1Oii0l_dataout <= ni1O0ilO WHEN niOlOl0Ol = '1' ELSE ni1Oi1ii; + wire_ni1Oii0O_dataout <= ni1O0iOi WHEN niOlOl0Ol = '1' ELSE ni1Oi1il; + wire_ni1Oii1i_dataout <= ni1O01ii WHEN niOlOl0Ol = '1' ELSE ni1O0l1l; + wire_ni1Oii1l_dataout <= ni1O0iiO WHEN niOlOl0Ol = '1' ELSE ni1Oi10i; + wire_ni1Oii1O_dataout <= ni1O0ili WHEN niOlOl0Ol = '1' ELSE ni1Oi10l; + wire_ni1Oiii_dataout <= wire_ni011Oi_dataout WHEN ni1llil = '1' ELSE ni1lO0i; + wire_ni1Oiiii_dataout <= ni1O0iOl WHEN niOlOl0Ol = '1' ELSE ni1Oi1iO; + wire_ni1Oiiil_dataout <= ni1O0iOO WHEN niOlOl0Ol = '1' ELSE ni1Oi1li; + wire_ni1OiiiO_dataout <= ni1O0l1i WHEN niOlOl0Ol = '1' ELSE ni1Oi1ll; + wire_ni1Oiil_dataout <= wire_ni011Ol_dataout WHEN ni1llil = '1' ELSE ni1lO0l; + wire_ni1OiiO_dataout <= wire_ni011OO_dataout WHEN ni1llil = '1' ELSE ni1lO0O; + wire_ni1Oili_dataout <= wire_ni0101i_dataout WHEN ni1llil = '1' ELSE ni1lOii; + wire_ni1Oilil_dataout <= wire_ni1OiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OiliO_dataout <= wire_ni1OiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oill_dataout <= wire_ni0101l_dataout WHEN ni1llil = '1' ELSE ni1lOll; + wire_ni1Oilli_dataout <= wire_ni1OiO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Oilll_dataout <= wire_ni1OiO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OillO_dataout <= wire_ni1OiO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OilO_dataout <= wire_ni0101O_dataout WHEN ni1llil = '1' ELSE ni1lOOi; + wire_ni1OilOi_dataout <= wire_ni1OiOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OilOl_dataout <= wire_ni1OiOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OilOO_dataout <= wire_ni1OiOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OiO0i_dataout <= wire_nii0lOii_dataout WHEN niOlOillO = '1' ELSE wire_ni1OiOOi_dataout; + wire_ni1OiO0l_dataout <= wire_nii0lOil_dataout WHEN niOlOillO = '1' ELSE wire_ni1OiOOl_dataout; + wire_ni1OiO0O_dataout <= wire_nii0lOiO_dataout WHEN niOlOillO = '1' ELSE wire_ni1OiOOO_dataout; + wire_ni1OiO1i_dataout <= wire_ni1OiOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OiO1l_dataout <= wire_nii0lO0l_dataout WHEN niOlOillO = '1' ELSE wire_ni1OiOll_dataout; + wire_ni1OiO1O_dataout <= wire_nii0lO0O_dataout WHEN niOlOillO = '1' ELSE wire_ni1OiOlO_dataout; + wire_ni1OiOi_dataout <= wire_ni1Ol1l_dataout AND NOT(wire_ni010ii_dataout); + wire_ni1OiOii_dataout <= wire_nii0lOli_dataout WHEN niOlOillO = '1' ELSE wire_ni1Ol11i_dataout; + wire_ni1OiOil_dataout <= wire_nii0lOll_dataout WHEN niOlOillO = '1' ELSE wire_ni1Ol11l_dataout; + wire_ni1OiOiO_dataout <= wire_nii0lOlO_dataout WHEN niOlOillO = '1' ELSE wire_ni1Ol11O_dataout; + wire_ni1OiOl_dataout <= wire_ni1Ol1O_dataout AND NOT(wire_ni010ii_dataout); + wire_ni1OiOli_dataout <= wire_nii0lOOi_dataout WHEN niOlOillO = '1' ELSE wire_ni1Ol10i_dataout; + wire_ni1OiOll_dataout <= ni1O0l1l WHEN niOlOl0Ol = '1' ELSE ni1Oi1lO; + wire_ni1OiOlO_dataout <= ni1Oi10i WHEN niOlOl0Ol = '1' ELSE ni1OiiOl; + wire_ni1OiOO_dataout <= wire_ni1Ol0i_dataout AND NOT(wire_ni010ii_dataout); + wire_ni1OiOOi_dataout <= ni1Oi10l WHEN niOlOl0Ol = '1' ELSE ni1OiiOO; + wire_ni1OiOOl_dataout <= ni1Oi10O WHEN niOlOl0Ol = '1' ELSE ni1Oil1i; + wire_ni1OiOOO_dataout <= ni1Oi1ii WHEN niOlOl0Ol = '1' ELSE ni1Oil1l; + wire_ni1Ol00i_dataout <= wire_ni1Ol0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol00l_dataout <= wire_ni1Ol0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol00O_dataout <= wire_ni1Ol0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol01O_dataout <= wire_ni1Ol0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol0i_dataout <= ni1ll0O AND NOT(k_hip(0)); + wire_ni1Ol0ii_dataout <= wire_ni1Oli1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol0il_dataout <= wire_ni1Oli1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol0iO_dataout <= wire_ni1Oli1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol0l_dataout <= ni1llil AND NOT(k_hip(0)); + wire_ni1Ol0li_dataout <= wire_ni1Oli0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol0ll_dataout <= wire_ni1Oli0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1Ol0lO_dataout <= wire_nii0lO0l_dataout WHEN niOlOilOl = '1' ELSE wire_ni1Oli0O_dataout; + wire_ni1Ol0O_dataout <= wire_ni1Olli_dataout AND NOT(wire_ni010ii_dataout); + wire_ni1Ol0Oi_dataout <= wire_nii0lO0O_dataout WHEN niOlOilOl = '1' ELSE wire_ni1Oliii_dataout; + wire_ni1Ol0Ol_dataout <= wire_nii0lOii_dataout WHEN niOlOilOl = '1' ELSE wire_ni1Oliil_dataout; + wire_ni1Ol0OO_dataout <= wire_nii0lOil_dataout WHEN niOlOilOl = '1' ELSE wire_ni1OliiO_dataout; + wire_ni1Ol10i_dataout <= ni1Oi1ll WHEN niOlOl0Ol = '1' ELSE ni1Oil0O; + wire_ni1Ol11i_dataout <= ni1Oi1il WHEN niOlOl0Ol = '1' ELSE ni1Oil1O; + wire_ni1Ol11l_dataout <= ni1Oi1iO WHEN niOlOl0Ol = '1' ELSE ni1Oil0i; + wire_ni1Ol11O_dataout <= ni1Oi1li WHEN niOlOl0Ol = '1' ELSE ni1Oil0l; + wire_ni1Ol1i_dataout <= wire_ni1Ol0l_dataout OR wire_ni010ii_dataout; + wire_ni1Ol1l_dataout <= ni1l11l OR k_hip(0); + wire_ni1Ol1O_dataout <= ni1ll0l AND NOT(k_hip(0)); + wire_ni1Oli0i_dataout <= wire_nii0lOlO_dataout WHEN niOlOilOl = '1' ELSE wire_ni1OliOi_dataout; + wire_ni1Oli0l_dataout <= wire_nii0lOOi_dataout WHEN niOlOilOl = '1' ELSE wire_ni1OliOl_dataout; + wire_ni1Oli0O_dataout <= ni1Oi1lO WHEN niOlOl0Ol = '1' ELSE ni1Oilii; + wire_ni1Oli1i_dataout <= wire_nii0lOiO_dataout WHEN niOlOilOl = '1' ELSE wire_ni1Olili_dataout; + wire_ni1Oli1l_dataout <= wire_nii0lOli_dataout WHEN niOlOilOl = '1' ELSE wire_ni1Olill_dataout; + wire_ni1Oli1O_dataout <= wire_nii0lOll_dataout WHEN niOlOilOl = '1' ELSE wire_ni1OlilO_dataout; + wire_ni1Olii_dataout <= wire_ni1Olll_dataout AND NOT(wire_ni010ii_dataout); + wire_ni1Oliii_dataout <= ni1OiiOl WHEN niOlOl0Ol = '1' ELSE ni1Ol1iO; + wire_ni1Oliil_dataout <= ni1OiiOO WHEN niOlOl0Ol = '1' ELSE ni1Ol1li; + wire_ni1OliiO_dataout <= ni1Oil1i WHEN niOlOl0Ol = '1' ELSE ni1Ol1ll; + wire_ni1Olil_dataout <= wire_ni1OllO_dataout AND NOT(wire_ni010ii_dataout); + wire_ni1Olili_dataout <= ni1Oil1l WHEN niOlOl0Ol = '1' ELSE ni1Ol1lO; + wire_ni1Olill_dataout <= ni1Oil1O WHEN niOlOl0Ol = '1' ELSE ni1Ol1Oi; + wire_ni1OlilO_dataout <= ni1Oil0i WHEN niOlOl0Ol = '1' ELSE ni1Ol1Ol; + wire_ni1OliO_dataout <= wire_ni1OlOi_dataout OR wire_ni010ii_dataout; + wire_ni1OliOi_dataout <= ni1Oil0l WHEN niOlOl0Ol = '1' ELSE ni1Ol1OO; + wire_ni1OliOl_dataout <= ni1Oil0O WHEN niOlOl0Ol = '1' ELSE ni1Ol01i; + wire_ni1Olli_dataout <= wire_ni1OlOl_dataout AND NOT(wire_w_lg_w_k_hip_range2413w2429w(0)); + wire_ni1Olll_dataout <= wire_ni1OlOO_dataout OR wire_w_lg_w_k_hip_range2413w2429w(0); + wire_ni1OllO_dataout <= wire_ni1OO1i_dataout AND NOT(wire_w_lg_w_k_hip_range2413w2429w(0)); + wire_ni1OllOi_dataout <= wire_ni1OlOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OllOl_dataout <= wire_ni1OlOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OllOO_dataout <= wire_ni1OlOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OlO0i_dataout <= wire_ni1OlOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OlO0l_dataout <= wire_ni1OlOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OlO0O_dataout <= wire_ni1OlOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OlO1i_dataout <= wire_ni1OlOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OlO1l_dataout <= wire_ni1OlOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OlO1O_dataout <= wire_ni1OlOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OlOi_dataout <= wire_ni1OO1l_dataout AND NOT(wire_w_lg_w_k_hip_range2413w2429w(0)); + wire_ni1OlOii_dataout <= wire_nii0lO0l_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO11i_dataout; + wire_ni1OlOil_dataout <= wire_nii0lO0O_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO11l_dataout; + wire_ni1OlOiO_dataout <= wire_nii0lOii_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO11O_dataout; + wire_ni1OlOl_dataout <= ni1l11l AND NOT(niOO0l01i); + wire_ni1OlOli_dataout <= wire_nii0lOil_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO10i_dataout; + wire_ni1OlOll_dataout <= wire_nii0lOiO_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO10l_dataout; + wire_ni1OlOlO_dataout <= wire_nii0lOli_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO10O_dataout; + wire_ni1OlOO_dataout <= ni1ll0l OR niOO0l01i; + wire_ni1OlOOi_dataout <= wire_nii0lOll_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO1ii_dataout; + wire_ni1OlOOl_dataout <= wire_nii0lOlO_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO1il_dataout; + wire_ni1OlOOO_dataout <= wire_nii0lOOi_dataout WHEN niOlOiO1i = '1' ELSE wire_ni1OO1iO_dataout; + wire_ni1OO00i_dataout <= wire_ni1OO0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OO00l_dataout <= wire_ni1OO0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OO00O_dataout <= wire_ni1OO0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OO01O_dataout <= niOlOiO1l AND NOT(wire_niO01lOO_dataout); + wire_ni1OO0ii_dataout <= wire_ni1OO0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OO0li_dataout <= wire_ni1OO0Ol_dataout AND NOT(niOlOlOOi); + wire_ni1OO0ll_dataout <= wire_ni1OO0OO_dataout AND NOT(niOlOlOOi); + wire_ni1OO0lO_dataout <= wire_ni1OOi1i_dataout AND NOT(niOlOlOOi); + wire_ni1OO0Oi_dataout <= wire_ni1OOi1l_dataout AND NOT(niOlOlOOi); + wire_ni1OO0Ol_dataout <= wire_w_lg_niOlOiO0i11035w(0) WHEN niOlOiO0O = '1' ELSE wire_ni1OOi1O_dataout; + wire_ni1OO0OO_dataout <= wire_ni1OOiiO_o(1) WHEN niOlOiO0O = '1' ELSE wire_ni1OOi0i_dataout; + wire_ni1OO10i_dataout <= ni1Ol1ll WHEN niOlOl0Ol = '1' ELSE ni1Oll0O; + wire_ni1OO10l_dataout <= ni1Ol1lO WHEN niOlOl0Ol = '1' ELSE ni1Ollii; + wire_ni1OO10O_dataout <= ni1Ol1Oi WHEN niOlOl0Ol = '1' ELSE ni1Ollil; + wire_ni1OO11i_dataout <= ni1Oilii WHEN niOlOl0Ol = '1' ELSE ni1Ol01l; + wire_ni1OO11l_dataout <= ni1Ol1iO WHEN niOlOl0Ol = '1' ELSE ni1Oll0i; + wire_ni1OO11O_dataout <= ni1Ol1li WHEN niOlOl0Ol = '1' ELSE ni1Oll0l; + wire_ni1OO1i_dataout <= ni1ll0O AND NOT(niOO0l01i); + wire_ni1OO1ii_dataout <= ni1Ol1Ol WHEN niOlOl0Ol = '1' ELSE ni1OlliO; + wire_ni1OO1il_dataout <= ni1Ol1OO WHEN niOlOl0Ol = '1' ELSE ni1Ollli; + wire_ni1OO1iO_dataout <= ni1Ol01i WHEN niOlOl0Ol = '1' ELSE ni1Ollll; + wire_ni1OO1l_dataout <= ni1llil AND NOT(niOO0l01i); + wire_ni1OOi0i_dataout <= wire_ni1OOiii_o(0) WHEN niOlOiO0l = '1' ELSE ni1OO1OO; + wire_ni1OOi0l_dataout <= wire_ni1OOiii_o(1) WHEN niOlOiO0l = '1' ELSE ni1OO01i; + wire_ni1OOi0O_dataout <= wire_ni1OOiii_o(2) WHEN niOlOiO0l = '1' ELSE ni1OO01l; + wire_ni1OOi1i_dataout <= wire_ni1OOiiO_o(2) WHEN niOlOiO0O = '1' ELSE wire_ni1OOi0l_dataout; + wire_ni1OOi1l_dataout <= wire_ni1OOiiO_o(3) WHEN niOlOiO0O = '1' ELSE wire_ni1OOi0O_dataout; + wire_ni1OOi1O_dataout <= ni1OO1Ol OR niOlOiO0l; + wire_ni1OOlOi_dataout <= wire_ni1OOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOlOl_dataout <= wire_ni1OOOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOlOO_dataout <= wire_ni1OOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOO0i_dataout <= wire_ni1OOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOO0l_dataout <= wire_ni1OOOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOO0O_dataout <= wire_ni1OOOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOO1i_dataout <= wire_ni1OOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOO1l_dataout <= wire_ni1OOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOO1O_dataout <= wire_ni1OOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_ni1OOOii_dataout <= wire_nii0lili_dataout WHEN niOlOl10i = '1' ELSE wire_ni01111i_dataout; + wire_ni1OOOil_dataout <= wire_nii0lill_dataout WHEN niOlOl10i = '1' ELSE wire_ni01111l_dataout; + wire_ni1OOOiO_dataout <= wire_nii0lilO_dataout WHEN niOlOl10i = '1' ELSE wire_ni01111O_dataout; + wire_ni1OOOli_dataout <= wire_nii0liOi_dataout WHEN niOlOl10i = '1' ELSE wire_ni01110i_dataout; + wire_ni1OOOll_dataout <= wire_nii0liOl_dataout WHEN niOlOl10i = '1' ELSE wire_ni01110l_dataout; + wire_ni1OOOlO_dataout <= wire_nii0liOO_dataout WHEN niOlOl10i = '1' ELSE wire_ni01110O_dataout; + wire_ni1OOOO_dataout <= wire_ni01ill_dataout WHEN wire_ni1lOlO_w_lg_ni1llli2476w(0) = '1' ELSE ni1lOli; + wire_ni1OOOOi_dataout <= wire_nii0ll1i_dataout WHEN niOlOl10i = '1' ELSE wire_ni0111ii_dataout; + wire_ni1OOOOl_dataout <= wire_nii0ll1l_dataout WHEN niOlOl10i = '1' ELSE wire_ni0111il_dataout; + wire_ni1OOOOO_dataout <= wire_nii0ll1O_dataout WHEN niOlOl10i = '1' ELSE wire_ni0111iO_dataout; + wire_nii0000i_dataout <= ni0i1Oil WHEN niOlOll1l = '1' ELSE wire_nii00OOO_dataout; + wire_nii0000l_dataout <= ni0i1OiO WHEN niOlOll1l = '1' ELSE wire_nii0i11i_dataout; + wire_nii0000O_dataout <= ni0i1Oli WHEN niOlOll1l = '1' ELSE wire_nii0i11l_dataout; + wire_nii0001i_dataout <= ni0i1O0l WHEN niOlOll1l = '1' ELSE wire_nii00OlO_dataout; + wire_nii0001l_dataout <= ni0i1O0O WHEN niOlOll1l = '1' ELSE wire_nii00OOi_dataout; + wire_nii0001O_dataout <= ni0i1Oii WHEN niOlOll1l = '1' ELSE wire_nii00OOl_dataout; + wire_nii000ii_dataout <= ni0i1Oll WHEN niOlOll1l = '1' ELSE wire_nii0i11O_dataout; + wire_nii000il_dataout <= ni0i1OlO WHEN niOlOll1l = '1' ELSE wire_nii0i10i_dataout; + wire_nii000iO_dataout <= ni0i1OOi WHEN niOlOll1l = '1' ELSE wire_nii0i10l_dataout; + wire_nii000li_dataout <= ni0i1OOl WHEN niOlOll1l = '1' ELSE wire_nii0i10O_dataout; + wire_nii000ll_dataout <= ni0i1OOO WHEN niOlOll1l = '1' ELSE wire_nii0i1ii_dataout; + wire_nii000lO_dataout <= ni11Oi0i WHEN niOlOll1l = '1' ELSE ni0i011i; + wire_nii000Oi_dataout <= ni11OO0O WHEN niOlOll1l = '1' ELSE ni0i011l; + wire_nii000Ol_dataout <= ni11OOii WHEN niOlOll1l = '1' ELSE ni0i011O; + wire_nii000OO_dataout <= ni11OOil WHEN niOlOll1l = '1' ELSE ni0i010i; + wire_nii0010i_dataout <= ni0i1lil WHEN niOlOll1l = '1' ELSE wire_nii00lOO_dataout; + wire_nii0010l_dataout <= ni0i1liO WHEN niOlOll1l = '1' ELSE wire_nii00O1i_dataout; + wire_nii0010O_dataout <= ni0i1lli WHEN niOlOll1l = '1' ELSE wire_nii00O1l_dataout; + wire_nii0011i_dataout <= ni0i1l0l WHEN niOlOll1l = '1' ELSE wire_nii00llO_dataout; + wire_nii0011l_dataout <= ni0i1l0O WHEN niOlOll1l = '1' ELSE wire_nii00lOi_dataout; + wire_nii0011O_dataout <= ni0i1lii WHEN niOlOll1l = '1' ELSE wire_nii00lOl_dataout; + wire_nii001ii_dataout <= ni0i1lll WHEN niOlOll1l = '1' ELSE wire_nii00O1O_dataout; + wire_nii001il_dataout <= ni0i1llO WHEN niOlOll1l = '1' ELSE wire_nii00O0i_dataout; + wire_nii001iO_dataout <= ni0i1lOi WHEN niOlOll1l = '1' ELSE wire_nii00O0l_dataout; + wire_nii001li_dataout <= ni0i1lOl WHEN niOlOll1l = '1' ELSE wire_nii00O0O_dataout; + wire_nii001ll_dataout <= ni0i1lOO WHEN niOlOll1l = '1' ELSE wire_nii00Oii_dataout; + wire_nii001lO_dataout <= ni0i1O1i WHEN niOlOll1l = '1' ELSE wire_nii00Oil_dataout; + wire_nii001Oi_dataout <= ni0i1O1l WHEN niOlOll1l = '1' ELSE wire_nii00OiO_dataout; + wire_nii001Ol_dataout <= ni0i1O1O WHEN niOlOll1l = '1' ELSE wire_nii00Oli_dataout; + wire_nii001OO_dataout <= ni0i1O0i WHEN niOlOll1l = '1' ELSE wire_nii00Oll_dataout; + wire_nii00i0i_dataout <= ni11OOlO WHEN niOlOll1l = '1' ELSE ni0i01il; + wire_nii00i0l_dataout <= n0OOOllO WHEN niOlOll1l = '1' ELSE ni0i01iO; + wire_nii00i0O_dataout <= ni1111Ol WHEN niOlOll1l = '1' ELSE ni0i01li; + wire_nii00i1i_dataout <= ni11OOiO WHEN niOlOll1l = '1' ELSE ni0i010l; + wire_nii00i1l_dataout <= ni11OOli WHEN niOlOll1l = '1' ELSE ni0i010O; + wire_nii00i1O_dataout <= ni11OOll WHEN niOlOll1l = '1' ELSE ni0i01ii; + wire_nii00iii_dataout <= ni1111OO WHEN niOlOll1l = '1' ELSE ni0i01ll; + wire_nii00iil_dataout <= ni11101i WHEN niOlOll1l = '1' ELSE ni0i01lO; + wire_nii00iiO_dataout <= ni11101l WHEN niOlOll1l = '1' ELSE ni0i01Oi; + wire_nii00ili_dataout <= ni11101O WHEN niOlOll1l = '1' ELSE ni0i01Ol; + wire_nii00ill_dataout <= ni11100i WHEN niOlOll1l = '1' ELSE ni0i01OO; + wire_nii00ilO_dataout <= ni11100l WHEN niOlOll1l = '1' ELSE ni0i001i; + wire_nii00iOi_dataout <= wire_nii0i1il_dataout AND NOT(niOlOll1l); + wire_nii00iOl_dataout <= wire_nii1l00l_o(1) WHEN niOlOll1l = '1' ELSE wire_nii0i1iO_dataout; + wire_nii00iOO_dataout <= wire_nii1l00l_o(2) WHEN niOlOll1l = '1' ELSE wire_nii0i1li_dataout; + wire_nii00l0i_dataout <= ni11OOOi WHEN niOlOll1O = '1' ELSE ni0i1iil; + wire_nii00l0l_dataout <= ni11100O WHEN niOlOll1O = '1' ELSE ni0i1iiO; + wire_nii00l0O_dataout <= ni0i1iOl WHEN niOlOll1O = '1' ELSE wire_nii0i1Ol_dataout; + wire_nii00l1i_dataout <= wire_nii1l00l_o(3) WHEN niOlOll1l = '1' ELSE wire_nii0i1ll_dataout; + wire_nii00l1l_dataout <= ni0i1i0O WHEN niOlOll1O = '1' ELSE wire_nii0i1lO_dataout; + wire_nii00l1O_dataout <= ni0i1iii WHEN niOlOll1O = '1' ELSE wire_nii0i1Oi_dataout; + wire_nii00lii_dataout <= ni0i1iOO WHEN niOlOll1O = '1' ELSE wire_nii0i1OO_dataout; + wire_nii00lil_dataout <= ni0i1l1i WHEN niOlOll1O = '1' ELSE wire_nii0i01i_dataout; + wire_nii00liO_dataout <= ni0i1l1l WHEN niOlOll1O = '1' ELSE wire_nii0i01l_dataout; + wire_nii00lli_dataout <= ni0i1l1O WHEN niOlOll1O = '1' ELSE wire_nii0i01O_dataout; + wire_nii00lll_dataout <= ni0i1l0i WHEN niOlOll1O = '1' ELSE wire_nii0i00i_dataout; + wire_nii00llO_dataout <= ni0i1l0l WHEN niOlOll1O = '1' ELSE wire_nii0i00l_dataout; + wire_nii00lOi_dataout <= ni0i1l0O WHEN niOlOll1O = '1' ELSE wire_nii0i00O_dataout; + wire_nii00lOl_dataout <= ni0i1lii WHEN niOlOll1O = '1' ELSE wire_nii0i0ii_dataout; + wire_nii00lOO_dataout <= ni0i1lil WHEN niOlOll1O = '1' ELSE wire_nii0i0il_dataout; + wire_nii00O0i_dataout <= ni0i1llO WHEN niOlOll1O = '1' ELSE wire_nii0i0lO_dataout; + wire_nii00O0l_dataout <= ni0i1lOi WHEN niOlOll1O = '1' ELSE wire_nii0i0Oi_dataout; + wire_nii00O0O_dataout <= ni0i1lOl WHEN niOlOll1O = '1' ELSE wire_nii0i0Ol_dataout; + wire_nii00O1i_dataout <= ni0i1liO WHEN niOlOll1O = '1' ELSE wire_nii0i0iO_dataout; + wire_nii00O1l_dataout <= ni0i1lli WHEN niOlOll1O = '1' ELSE wire_nii0i0li_dataout; + wire_nii00O1O_dataout <= ni0i1lll WHEN niOlOll1O = '1' ELSE wire_nii0i0ll_dataout; + wire_nii00Oii_dataout <= ni11Oi0i WHEN niOlOll1O = '1' ELSE ni0i1lOO; + wire_nii00Oil_dataout <= ni11OO0O WHEN niOlOll1O = '1' ELSE ni0i1O1i; + wire_nii00OiO_dataout <= ni11OOii WHEN niOlOll1O = '1' ELSE ni0i1O1l; + wire_nii00Oli_dataout <= ni11OOil WHEN niOlOll1O = '1' ELSE ni0i1O1O; + wire_nii00Oll_dataout <= ni11OOiO WHEN niOlOll1O = '1' ELSE ni0i1O0i; + wire_nii00OlO_dataout <= ni11OOli WHEN niOlOll1O = '1' ELSE ni0i1O0l; + wire_nii00OOi_dataout <= ni11OOll WHEN niOlOll1O = '1' ELSE ni0i1O0O; + wire_nii00OOl_dataout <= ni11OOlO WHEN niOlOll1O = '1' ELSE ni0i1Oii; + wire_nii00OOO_dataout <= n0OOOllO WHEN niOlOll1O = '1' ELSE ni0i1Oil; + wire_nii0100i_dataout <= ni0i1l0O WHEN niOlOll0O = '1' ELSE wire_nii0011l_dataout; + wire_nii0100l_dataout <= ni0i1lii WHEN niOlOll0O = '1' ELSE wire_nii0011O_dataout; + wire_nii0100O_dataout <= ni0i1lil WHEN niOlOll0O = '1' ELSE wire_nii0010i_dataout; + wire_nii0101i_dataout <= ni0i1l1O WHEN niOlOll0O = '1' ELSE wire_nii01OOl_dataout; + wire_nii0101l_dataout <= ni0i1l0i WHEN niOlOll0O = '1' ELSE wire_nii01OOO_dataout; + wire_nii0101O_dataout <= ni0i1l0l WHEN niOlOll0O = '1' ELSE wire_nii0011i_dataout; + wire_nii010ii_dataout <= ni0i1liO WHEN niOlOll0O = '1' ELSE wire_nii0010l_dataout; + wire_nii010il_dataout <= ni0i1lli WHEN niOlOll0O = '1' ELSE wire_nii0010O_dataout; + wire_nii010iO_dataout <= ni0i1lll WHEN niOlOll0O = '1' ELSE wire_nii001ii_dataout; + wire_nii010li_dataout <= ni0i1llO WHEN niOlOll0O = '1' ELSE wire_nii001il_dataout; + wire_nii010ll_dataout <= ni0i1lOi WHEN niOlOll0O = '1' ELSE wire_nii001iO_dataout; + wire_nii010lO_dataout <= ni0i1lOl WHEN niOlOll0O = '1' ELSE wire_nii001li_dataout; + wire_nii010Oi_dataout <= ni0i1lOO WHEN niOlOll0O = '1' ELSE wire_nii001ll_dataout; + wire_nii010Ol_dataout <= ni0i1O1i WHEN niOlOll0O = '1' ELSE wire_nii001lO_dataout; + wire_nii010OO_dataout <= ni0i1O1l WHEN niOlOll0O = '1' ELSE wire_nii001Oi_dataout; + wire_nii0110i_dataout <= wire_nii01O1l_dataout OR niOlOll0l; + wire_nii0110l_dataout <= wire_nii01O1O_dataout AND NOT(niOlOll0l); + wire_nii0110O_dataout <= ni0i1i0O WHEN niOlOll0O = '1' ELSE wire_nii01O0i_dataout; + wire_nii0111i_dataout <= ni11OOlO WHEN niOlOll0l = '1' ELSE ni0i00iO; + wire_nii0111l_dataout <= wire_nii01lOO_dataout AND NOT(niOlOll0l); + wire_nii0111O_dataout <= wire_nii01O1i_dataout OR niOlOll0l; + wire_nii011ii_dataout <= ni0i1iii WHEN niOlOll0O = '1' ELSE wire_nii01O0l_dataout; + wire_nii011il_dataout <= ni0i1iil WHEN niOlOll0O = '1' ELSE wire_nii01O0O_dataout; + wire_nii011iO_dataout <= ni0i1iiO WHEN niOlOll0O = '1' ELSE wire_nii01Oii_dataout; + wire_nii011li_dataout <= ni0i1ili WHEN niOlOll0O = '1' ELSE wire_nii01Oil_dataout; + wire_nii011ll_dataout <= ni0i1ill WHEN niOlOll0O = '1' ELSE wire_nii01OiO_dataout; + wire_nii011lO_dataout <= ni0i1iOl WHEN niOlOll0O = '1' ELSE wire_nii01Oli_dataout; + wire_nii011Oi_dataout <= ni0i1iOO WHEN niOlOll0O = '1' ELSE wire_nii01Oll_dataout; + wire_nii011Ol_dataout <= ni0i1l1i WHEN niOlOll0O = '1' ELSE wire_nii01OlO_dataout; + wire_nii011OO_dataout <= ni0i1l1l WHEN niOlOll0O = '1' ELSE wire_nii01OOi_dataout; + wire_nii01i0i_dataout <= ni0i1O0O WHEN niOlOll0O = '1' ELSE wire_nii0001l_dataout; + wire_nii01i0l_dataout <= ni0i1Oii WHEN niOlOll0O = '1' ELSE wire_nii0001O_dataout; + wire_nii01i0O_dataout <= ni0i1Oil WHEN niOlOll0O = '1' ELSE wire_nii0000i_dataout; + wire_nii01i1i_dataout <= ni0i1O1O WHEN niOlOll0O = '1' ELSE wire_nii001Ol_dataout; + wire_nii01i1l_dataout <= ni0i1O0i WHEN niOlOll0O = '1' ELSE wire_nii001OO_dataout; + wire_nii01i1O_dataout <= ni0i1O0l WHEN niOlOll0O = '1' ELSE wire_nii0001i_dataout; + wire_nii01iii_dataout <= ni0i1OiO WHEN niOlOll0O = '1' ELSE wire_nii0000l_dataout; + wire_nii01iil_dataout <= ni0i1Oli WHEN niOlOll0O = '1' ELSE wire_nii0000O_dataout; + wire_nii01iiO_dataout <= ni0i1Oll WHEN niOlOll0O = '1' ELSE wire_nii000ii_dataout; + wire_nii01ili_dataout <= ni0i1OlO WHEN niOlOll0O = '1' ELSE wire_nii000il_dataout; + wire_nii01ill_dataout <= ni0i1OOi WHEN niOlOll0O = '1' ELSE wire_nii000iO_dataout; + wire_nii01ilO_dataout <= ni0i1OOl WHEN niOlOll0O = '1' ELSE wire_nii000li_dataout; + wire_nii01iOi_dataout <= ni0i1OOO WHEN niOlOll0O = '1' ELSE wire_nii000ll_dataout; + wire_nii01iOl_dataout <= ni0i011i WHEN niOlOll0O = '1' ELSE wire_nii000lO_dataout; + wire_nii01iOO_dataout <= ni0i011l WHEN niOlOll0O = '1' ELSE wire_nii000Oi_dataout; + wire_nii01l0i_dataout <= ni0i010O WHEN niOlOll0O = '1' ELSE wire_nii00i1l_dataout; + wire_nii01l0l_dataout <= ni0i01ii WHEN niOlOll0O = '1' ELSE wire_nii00i1O_dataout; + wire_nii01l0O_dataout <= ni0i01il WHEN niOlOll0O = '1' ELSE wire_nii00i0i_dataout; + wire_nii01l1i_dataout <= ni0i011O WHEN niOlOll0O = '1' ELSE wire_nii000Ol_dataout; + wire_nii01l1l_dataout <= ni0i010i WHEN niOlOll0O = '1' ELSE wire_nii000OO_dataout; + wire_nii01l1O_dataout <= ni0i010l WHEN niOlOll0O = '1' ELSE wire_nii00i1i_dataout; + wire_nii01lii_dataout <= ni0i01iO WHEN niOlOll0O = '1' ELSE wire_nii00i0l_dataout; + wire_nii01lil_dataout <= ni0i01li WHEN niOlOll0O = '1' ELSE wire_nii00i0O_dataout; + wire_nii01liO_dataout <= ni0i01ll WHEN niOlOll0O = '1' ELSE wire_nii00iii_dataout; + wire_nii01lli_dataout <= ni0i01lO WHEN niOlOll0O = '1' ELSE wire_nii00iil_dataout; + wire_nii01lll_dataout <= ni0i01Oi WHEN niOlOll0O = '1' ELSE wire_nii00iiO_dataout; + wire_nii01llO_dataout <= ni0i01Ol WHEN niOlOll0O = '1' ELSE wire_nii00ili_dataout; + wire_nii01lOi_dataout <= ni0i01OO WHEN niOlOll0O = '1' ELSE wire_nii00ill_dataout; + wire_nii01lOl_dataout <= ni0i001i WHEN niOlOll0O = '1' ELSE wire_nii00ilO_dataout; + wire_nii01lOO_dataout <= (NOT (niOlOll1i OR ni0i1i0l)) WHEN niOlOll0O = '1' ELSE wire_nii00iOi_dataout; + wire_nii01O0i_dataout <= ni0i1i0O WHEN niOlOll1l = '1' ELSE wire_nii00l1l_dataout; + wire_nii01O0l_dataout <= ni0i1iii WHEN niOlOll1l = '1' ELSE wire_nii00l1O_dataout; + wire_nii01O0O_dataout <= ni0i1iil WHEN niOlOll1l = '1' ELSE wire_nii00l0i_dataout; + wire_nii01O1i_dataout <= wire_nii1l00l_o(1) WHEN niOlOll0O = '1' ELSE wire_nii00iOl_dataout; + wire_nii01O1l_dataout <= wire_nii1l00l_o(2) WHEN niOlOll0O = '1' ELSE wire_nii00iOO_dataout; + wire_nii01O1O_dataout <= wire_nii1l00l_o(3) WHEN niOlOll0O = '1' ELSE wire_nii00l1i_dataout; + wire_nii01Oii_dataout <= ni0i1iiO WHEN niOlOll1l = '1' ELSE wire_nii00l0l_dataout; + wire_nii01Oil_dataout <= ni11OOOi WHEN niOlOll1l = '1' ELSE ni0i1ili; + wire_nii01OiO_dataout <= ni11100O WHEN niOlOll1l = '1' ELSE ni0i1ill; + wire_nii01Oli_dataout <= ni0i1iOl WHEN niOlOll1l = '1' ELSE wire_nii00l0O_dataout; + wire_nii01Oll_dataout <= ni0i1iOO WHEN niOlOll1l = '1' ELSE wire_nii00lii_dataout; + wire_nii01OlO_dataout <= ni0i1l1i WHEN niOlOll1l = '1' ELSE wire_nii00lil_dataout; + wire_nii01OOi_dataout <= ni0i1l1l WHEN niOlOll1l = '1' ELSE wire_nii00liO_dataout; + wire_nii01OOl_dataout <= ni0i1l1O WHEN niOlOll1l = '1' ELSE wire_nii00lli_dataout; + wire_nii01OOO_dataout <= ni0i1l0i WHEN niOlOll1l = '1' ELSE wire_nii00lll_dataout; + wire_nii0i00i_dataout <= ni11OOli WHEN niOlOll0i = '1' ELSE ni0i1l0i; + wire_nii0i00l_dataout <= ni11OOll WHEN niOlOll0i = '1' ELSE ni0i1l0l; + wire_nii0i00O_dataout <= ni11OOlO WHEN niOlOll0i = '1' ELSE ni0i1l0O; + wire_nii0i01i_dataout <= ni11OOii WHEN niOlOll0i = '1' ELSE ni0i1l1i; + wire_nii0i01l_dataout <= ni11OOil WHEN niOlOll0i = '1' ELSE ni0i1l1l; + wire_nii0i01O_dataout <= ni11OOiO WHEN niOlOll0i = '1' ELSE ni0i1l1O; + wire_nii0i0ii_dataout <= n0OOOllO WHEN niOlOll0i = '1' ELSE ni0i1lii; + wire_nii0i0il_dataout <= ni1111Ol WHEN niOlOll0i = '1' ELSE ni0i1lil; + wire_nii0i0iO_dataout <= ni1111OO WHEN niOlOll0i = '1' ELSE ni0i1liO; + wire_nii0i0li_dataout <= ni11101i WHEN niOlOll0i = '1' ELSE ni0i1lli; + wire_nii0i0ll_dataout <= ni11101l WHEN niOlOll0i = '1' ELSE ni0i1lll; + wire_nii0i0lO_dataout <= ni11101O WHEN niOlOll0i = '1' ELSE ni0i1llO; + wire_nii0i0Oi_dataout <= ni11100i WHEN niOlOll0i = '1' ELSE ni0i1lOi; + wire_nii0i0Ol_dataout <= ni11100l WHEN niOlOll0i = '1' ELSE ni0i1lOl; + wire_nii0i0OO_dataout <= ni0i1i0l OR niOlOll0i; + wire_nii0i10i_dataout <= ni11101l WHEN niOlOll1O = '1' ELSE ni0i1OlO; + wire_nii0i10l_dataout <= ni11101O WHEN niOlOll1O = '1' ELSE ni0i1OOi; + wire_nii0i10O_dataout <= ni11100i WHEN niOlOll1O = '1' ELSE ni0i1OOl; + wire_nii0i11i_dataout <= ni1111Ol WHEN niOlOll1O = '1' ELSE ni0i1OiO; + wire_nii0i11l_dataout <= ni1111OO WHEN niOlOll1O = '1' ELSE ni0i1Oli; + wire_nii0i11O_dataout <= ni11101i WHEN niOlOll1O = '1' ELSE ni0i1Oll; + wire_nii0i1ii_dataout <= ni11100l WHEN niOlOll1O = '1' ELSE ni0i1OOO; + wire_nii0i1il_dataout <= wire_nii0i0OO_dataout AND NOT(niOlOll1O); + wire_nii0i1iO_dataout <= wire_nii1l00l_o(1) WHEN niOlOll1O = '1' ELSE wire_nii0ii1i_dataout; + wire_nii0i1li_dataout <= wire_nii1l00l_o(2) WHEN niOlOll1O = '1' ELSE wire_nii0ii1l_dataout; + wire_nii0i1ll_dataout <= wire_nii1l00l_o(3) WHEN niOlOll1O = '1' ELSE wire_nii0ii1O_dataout; + wire_nii0i1lO_dataout <= ni11OOOi WHEN niOlOll0i = '1' ELSE ni0i1i0O; + wire_nii0i1Oi_dataout <= ni11100O WHEN niOlOll0i = '1' ELSE ni0i1iii; + wire_nii0i1Ol_dataout <= ni11Oi0i WHEN niOlOll0i = '1' ELSE ni0i1iOl; + wire_nii0i1OO_dataout <= ni11OO0O WHEN niOlOll0i = '1' ELSE ni0i1iOO; + wire_nii0ii0l_dataout <= ni1iO0lO AND NOT(niOlOll0l); + wire_nii0ii0O_dataout <= ni10Ol0l AND NOT(niOlOll0l); + wire_nii0ii1i_dataout <= wire_nii1l00l_o(1) WHEN niOlOll0i = '1' ELSE ni0i0i1O; + wire_nii0ii1l_dataout <= wire_nii1l00l_o(2) WHEN niOlOll0i = '1' ELSE ni0i0i0i; + wire_nii0ii1O_dataout <= wire_nii1l00l_o(3) WHEN niOlOll0i = '1' ELSE ni0i0i0l; + wire_nii0iiii_dataout <= ni11OOOi AND NOT(niOlOll0l); + wire_nii0iiil_dataout <= ni11100O AND NOT(niOlOll0l); + wire_nii0iiiO_dataout <= ni1iO0lO WHEN niOlOll0l = '1' ELSE ni0i1ili; + wire_nii0iili_dataout <= ni10Ol0l WHEN niOlOll0l = '1' ELSE ni0i1ill; + wire_nii0iill_dataout <= ni1ilO1O AND NOT(niOlOll0l); + wire_nii0iilO_dataout <= ni1iO00l AND NOT(niOlOll0l); + wire_nii0iiOi_dataout <= ni1iO00O AND NOT(niOlOll0l); + wire_nii0iiOl_dataout <= ni1iO0ii AND NOT(niOlOll0l); + wire_nii0iiOO_dataout <= ni1iO0il AND NOT(niOlOll0l); + wire_nii0il0i_dataout <= ni10O1ll AND NOT(niOlOll0l); + wire_nii0il0l_dataout <= ni10OiOi AND NOT(niOlOll0l); + wire_nii0il0O_dataout <= ni10OiOl AND NOT(niOlOll0l); + wire_nii0il1i_dataout <= ni1iO0iO AND NOT(niOlOll0l); + wire_nii0il1l_dataout <= ni1iO0li AND NOT(niOlOll0l); + wire_nii0il1O_dataout <= ni1iO0ll AND NOT(niOlOll0l); + wire_nii0ilii_dataout <= ni10OiOO AND NOT(niOlOll0l); + wire_nii0ilil_dataout <= ni10Ol1i AND NOT(niOlOll0l); + wire_nii0iliO_dataout <= ni10Ol1l AND NOT(niOlOll0l); + wire_nii0illi_dataout <= ni10Ol1O AND NOT(niOlOll0l); + wire_nii0illl_dataout <= ni10Ol0i AND NOT(niOlOll0l); + wire_nii0illO_dataout <= ni11Oi0i AND NOT(niOlOll0l); + wire_nii0ilOi_dataout <= ni11OO0O AND NOT(niOlOll0l); + wire_nii0ilOl_dataout <= ni11OOii AND NOT(niOlOll0l); + wire_nii0ilOO_dataout <= ni11OOil AND NOT(niOlOll0l); + wire_nii0iO0i_dataout <= ni11OOlO AND NOT(niOlOll0l); + wire_nii0iO0l_dataout <= n0OOOllO AND NOT(niOlOll0l); + wire_nii0iO0O_dataout <= ni1111Ol AND NOT(niOlOll0l); + wire_nii0iO1i_dataout <= ni11OOiO AND NOT(niOlOll0l); + wire_nii0iO1l_dataout <= ni11OOli AND NOT(niOlOll0l); + wire_nii0iO1O_dataout <= ni11OOll AND NOT(niOlOll0l); + wire_nii0iOii_dataout <= ni1111OO AND NOT(niOlOll0l); + wire_nii0iOil_dataout <= ni11101i AND NOT(niOlOll0l); + wire_nii0iOiO_dataout <= ni11101l AND NOT(niOlOll0l); + wire_nii0iOli_dataout <= ni11101O AND NOT(niOlOll0l); + wire_nii0iOll_dataout <= ni11100i AND NOT(niOlOll0l); + wire_nii0iOlO_dataout <= ni11100l AND NOT(niOlOll0l); + wire_nii0iOOi_dataout <= ni1ilO1O WHEN niOlOll0l = '1' ELSE ni0i011i; + wire_nii0iOOl_dataout <= ni1iO00l WHEN niOlOll0l = '1' ELSE ni0i011l; + wire_nii0iOOO_dataout <= ni1iO00O WHEN niOlOll0l = '1' ELSE ni0i011O; + wire_nii0l00i_dataout <= niiii11O AND NOT(niOlOlliO); + wire_nii0l00l_dataout <= niiii10i AND NOT(niOlOlliO); + wire_nii0l00O_dataout <= niiii10l AND NOT(niOlOlliO); + wire_nii0l01i_dataout <= niii0OOO AND NOT(niOlOlliO); + wire_nii0l01l_dataout <= niiii11i AND NOT(niOlOlliO); + wire_nii0l01O_dataout <= niiii11l AND NOT(niOlOlliO); + wire_nii0l0ii_dataout <= niiii10O AND NOT(niOlOlliO); + wire_nii0l0il_dataout <= niii0i1l AND NOT(niOlOlliO); + wire_nii0l10i_dataout <= ni1iO0li WHEN niOlOll0l = '1' ELSE ni0i01ii; + wire_nii0l10l_dataout <= ni1iO0ll WHEN niOlOll0l = '1' ELSE ni0i01il; + wire_nii0l10O_dataout <= ni10O1ll WHEN niOlOll0l = '1' ELSE ni0i01iO; + wire_nii0l11i_dataout <= ni1iO0ii WHEN niOlOll0l = '1' ELSE ni0i010i; + wire_nii0l11l_dataout <= ni1iO0il WHEN niOlOll0l = '1' ELSE ni0i010l; + wire_nii0l11O_dataout <= ni1iO0iO WHEN niOlOll0l = '1' ELSE ni0i010O; + wire_nii0l1ii_dataout <= ni10OiOi WHEN niOlOll0l = '1' ELSE ni0i01li; + wire_nii0l1il_dataout <= ni10OiOl WHEN niOlOll0l = '1' ELSE ni0i01ll; + wire_nii0l1iO_dataout <= ni10OiOO WHEN niOlOll0l = '1' ELSE ni0i01lO; + wire_nii0l1li_dataout <= ni10Ol1i WHEN niOlOll0l = '1' ELSE ni0i01Oi; + wire_nii0l1ll_dataout <= ni10Ol1l WHEN niOlOll0l = '1' ELSE ni0i01Ol; + wire_nii0l1lO_dataout <= ni10Ol1O WHEN niOlOll0l = '1' ELSE ni0i01OO; + wire_nii0l1Oi_dataout <= ni10Ol0i WHEN niOlOll0l = '1' ELSE ni0i001i; + wire_nii0l1OO_dataout <= niii0OOl AND NOT(niOlOlliO); + wire_nii0li0i_dataout <= wire_nii0li0l_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i0ii9973w10120w(0))); + wire_nii0li0l_dataout <= ni0i0i0O OR ((n111i10O AND niiiiOli) AND niOlOlO1l); + wire_nii0li1O_dataout <= wire_nii0li0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nii0lili_dataout <= niiii1il AND NOT(niOlOlO1O); + wire_nii0lill_dataout <= niiii1iO AND NOT(niOlOlO1O); + wire_nii0lilO_dataout <= niiii1li AND NOT(niOlOlO1O); + wire_nii0liOi_dataout <= niiii1ll AND NOT(niOlOlO1O); + wire_nii0liOl_dataout <= niiii1lO AND NOT(niOlOlO1O); + wire_nii0liOO_dataout <= niiii1Oi AND NOT(niOlOlO1O); + wire_nii0ll1i_dataout <= niiii1Ol AND NOT(niOlOlO1O); + wire_nii0ll1l_dataout <= niiii1OO AND NOT(niOlOlO1O); + wire_nii0ll1O_dataout <= niiii1ii AND NOT(niOlOlO1O); + wire_nii0llOi_dataout <= wire_nii0llOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nii0llOl_dataout <= wire_nii0llOO_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i00O9974w10107w(0))); + wire_nii0llOO_dataout <= nii0li1l OR ((n111i10O AND niiiiOll) AND niOlOlOll); + wire_nii0lO0l_dataout <= niiii01l AND NOT(niOlOlOlO); + wire_nii0lO0O_dataout <= niiii01O AND NOT(niOlOlOlO); + wire_nii0lOii_dataout <= niiii00i AND NOT(niOlOlOlO); + wire_nii0lOil_dataout <= niiii00l AND NOT(niOlOlOlO); + wire_nii0lOiO_dataout <= niiii00O AND NOT(niOlOlOlO); + wire_nii0lOli_dataout <= niiii0ii AND NOT(niOlOlOlO); + wire_nii0lOll_dataout <= niiii0il AND NOT(niOlOlOlO); + wire_nii0lOlO_dataout <= niiii0iO AND NOT(niOlOlOlO); + wire_nii0lOOi_dataout <= niiii01i AND NOT(niOlOlOlO); + wire_nii0O00i_dataout <= niiii0OO AND NOT(niOlOO10O); + wire_nii0O00l_dataout <= niiiii1i AND NOT(niOlOO10O); + wire_nii0O00O_dataout <= niiiii1l AND NOT(niOlOO10O); + wire_nii0O01i_dataout <= niiii0lO AND NOT(niOlOO10O); + wire_nii0O01l_dataout <= niiii0Oi AND NOT(niOlOO10O); + wire_nii0O01O_dataout <= niiii0Ol AND NOT(niOlOO10O); + wire_nii0O0ii_dataout <= niiiii1O AND NOT(niOlOO10O); + wire_nii0O0il_dataout <= niiii0li AND NOT(niOlOO10O); + wire_nii0O1il_dataout <= wire_nii0O1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nii0O1iO_dataout <= wire_nii0O1li_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i00l9976w10094w(0))); + wire_nii0O1li_dataout <= nii0lllO OR ((n111i10O AND niiiiOlO) AND niOlOO10l); + wire_nii0O1OO_dataout <= niiii0ll AND NOT(niOlOO10O); + wire_nii0Oi0i_dataout <= wire_nii0Oi0l_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i00i9978w10081w(0))); + wire_nii0Oi0l_dataout <= nii0O1ii OR ((n111i10O AND niiiiOOi) AND niOlOO1Ol); + wire_nii0Oi1O_dataout <= wire_nii0Oi0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nii0Oili_dataout <= niiiii0l AND NOT(niOlOO1OO); + wire_nii0Oill_dataout <= niiiii0O AND NOT(niOlOO1OO); + wire_nii0OilO_dataout <= niiiiiii AND NOT(niOlOO1OO); + wire_nii0OiOi_dataout <= niiiiiil AND NOT(niOlOO1OO); + wire_nii0OiOl_dataout <= niiiiiiO AND NOT(niOlOO1OO); + wire_nii0OiOO_dataout <= niiiiili AND NOT(niOlOO1OO); + wire_nii0Ol1i_dataout <= niiiiill AND NOT(niOlOO1OO); + wire_nii0Ol1l_dataout <= niiiiilO AND NOT(niOlOO1OO); + wire_nii0Ol1O_dataout <= niiiii0i AND NOT(niOlOO1OO); + wire_nii0OlOi_dataout <= wire_nii0OlOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nii0OlOl_dataout <= wire_nii0OlOO_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i01O9984w10068w(0))); + wire_nii0OlOO_dataout <= nii0Oi1l OR ((n111i10O AND niiiiOOl) AND niOlOO0il); + wire_nii0OO0l_dataout <= niiiiiOl AND NOT(niOlOO0iO); + wire_nii0OO0O_dataout <= niiiiiOO AND NOT(niOlOO0iO); + wire_nii0OOii_dataout <= niiiil1i AND NOT(niOlOO0iO); + wire_nii0OOil_dataout <= niiiil1l AND NOT(niOlOO0iO); + wire_nii0OOiO_dataout <= niiiil1O AND NOT(niOlOO0iO); + wire_nii0OOli_dataout <= niiiil0i AND NOT(niOlOO0iO); + wire_nii0OOll_dataout <= niiiil0l AND NOT(niOlOO0iO); + wire_nii0OOlO_dataout <= niiiil0O AND NOT(niOlOO0iO); + wire_nii0OOOi_dataout <= niiiiiOi AND NOT(niOlOO0iO); + wire_nii1000i_dataout <= ni0i1Oll WHEN niOlOlill = '1' ELSE wire_nii10OOi_dataout; + wire_nii1000l_dataout <= ni0i1OlO WHEN niOlOlill = '1' ELSE wire_nii10OOl_dataout; + wire_nii1000O_dataout <= ni0i1OOi WHEN niOlOlill = '1' ELSE wire_nii10OOO_dataout; + wire_nii1001i_dataout <= ni0i1Oil WHEN niOlOlill = '1' ELSE wire_nii10Oli_dataout; + wire_nii1001l_dataout <= ni0i1OiO WHEN niOlOlill = '1' ELSE wire_nii10Oll_dataout; + wire_nii1001O_dataout <= ni0i1Oli WHEN niOlOlill = '1' ELSE wire_nii10OlO_dataout; + wire_nii100i_dataout <= niOliili WHEN niOO0liiO = '1' ELSE ni0O0iO; + wire_nii100ii_dataout <= ni0i1OOl WHEN niOlOlill = '1' ELSE wire_nii1i11i_dataout; + wire_nii100il_dataout <= ni0i1OOO WHEN niOlOlill = '1' ELSE wire_nii1i11l_dataout; + wire_nii100iO_dataout <= ni0i011i WHEN niOlOlill = '1' ELSE wire_nii1i11O_dataout; + wire_nii100l_dataout <= niOliill WHEN niOO0liiO = '1' ELSE ni0O0li; + wire_nii100li_dataout <= ni0i011l WHEN niOlOlill = '1' ELSE wire_nii1i10i_dataout; + wire_nii100ll_dataout <= ni0i011O WHEN niOlOlill = '1' ELSE wire_nii1i10l_dataout; + wire_nii100lO_dataout <= ni0i010i WHEN niOlOlill = '1' ELSE wire_nii1i10O_dataout; + wire_nii100O_dataout <= niOliilO WHEN niOO0liiO = '1' ELSE ni0O0ll; + wire_nii100Oi_dataout <= ni0i010l WHEN niOlOlill = '1' ELSE wire_nii1i1ii_dataout; + wire_nii100Ol_dataout <= ni0i010O WHEN niOlOlill = '1' ELSE wire_nii1i1il_dataout; + wire_nii100OO_dataout <= ni0i01ii WHEN niOlOlill = '1' ELSE wire_nii1i1iO_dataout; + wire_nii1010i_dataout <= ni0i1lll WHEN niOlOlill = '1' ELSE wire_nii10lOi_dataout; + wire_nii1010l_dataout <= ni0i1llO WHEN niOlOlill = '1' ELSE wire_nii10lOl_dataout; + wire_nii1010O_dataout <= ni0i1lOi WHEN niOlOlill = '1' ELSE wire_nii10lOO_dataout; + wire_nii1011i_dataout <= ni0i1lil WHEN niOlOlill = '1' ELSE wire_nii10lli_dataout; + wire_nii1011l_dataout <= ni0i1liO WHEN niOlOlill = '1' ELSE wire_nii10lll_dataout; + wire_nii1011O_dataout <= ni0i1lli WHEN niOlOlill = '1' ELSE wire_nii10llO_dataout; + wire_nii101i_dataout <= niOliiii WHEN niOO0liiO = '1' ELSE ni0O00O; + wire_nii101ii_dataout <= ni0i1lOl WHEN niOlOlill = '1' ELSE wire_nii10O1i_dataout; + wire_nii101il_dataout <= ni0i1lOO WHEN niOlOlill = '1' ELSE wire_nii10O1l_dataout; + wire_nii101iO_dataout <= ni0i1O1i WHEN niOlOlill = '1' ELSE wire_nii10O1O_dataout; + wire_nii101l_dataout <= niOliiil WHEN niOO0liiO = '1' ELSE ni0O0ii; + wire_nii101li_dataout <= ni0i1O1l WHEN niOlOlill = '1' ELSE wire_nii10O0i_dataout; + wire_nii101ll_dataout <= ni0i1O1O WHEN niOlOlill = '1' ELSE wire_nii10O0l_dataout; + wire_nii101lO_dataout <= ni0i1O0i WHEN niOlOlill = '1' ELSE wire_nii10O0O_dataout; + wire_nii101O_dataout <= niOliiiO WHEN niOO0liiO = '1' ELSE ni0O0il; + wire_nii101Oi_dataout <= ni0i1O0l WHEN niOlOlill = '1' ELSE wire_nii10Oii_dataout; + wire_nii101Ol_dataout <= ni0i1O0O WHEN niOlOlill = '1' ELSE wire_nii10Oil_dataout; + wire_nii101OO_dataout <= ni0i1Oii WHEN niOlOlill = '1' ELSE wire_nii10OiO_dataout; + wire_nii10i0i_dataout <= ni1111OO WHEN niOlOlill = '1' ELSE ni0i01ll; + wire_nii10i0l_dataout <= ni11101i WHEN niOlOlill = '1' ELSE ni0i01lO; + wire_nii10i0O_dataout <= ni11101l WHEN niOlOlill = '1' ELSE ni0i01Oi; + wire_nii10i1i_dataout <= ni0i01il WHEN niOlOlill = '1' ELSE wire_nii1i1li_dataout; + wire_nii10i1l_dataout <= n0OOOllO WHEN niOlOlill = '1' ELSE ni0i01iO; + wire_nii10i1O_dataout <= ni1111Ol WHEN niOlOlill = '1' ELSE ni0i01li; + wire_nii10ii_dataout <= niOliiOi WHEN niOO0liiO = '1' ELSE ni0O0lO; + wire_nii10iii_dataout <= ni11101O WHEN niOlOlill = '1' ELSE ni0i01Ol; + wire_nii10iil_dataout <= ni11100i WHEN niOlOlill = '1' ELSE ni0i01OO; + wire_nii10iiO_dataout <= ni11100l WHEN niOlOlill = '1' ELSE ni0i001i; + wire_nii10il_dataout <= niOliiOl WHEN niOO0liiO = '1' ELSE ni0O0Oi; + wire_nii10ili_dataout <= wire_nii1i1ll_dataout AND NOT(niOlOlill); + wire_nii10ill_dataout <= ni0i1i0O WHEN niOlOlilO = '1' ELSE wire_nii1i1lO_dataout; + wire_nii10ilO_dataout <= ni0i1iii WHEN niOlOlilO = '1' ELSE wire_nii1i1Oi_dataout; + wire_nii10iO_dataout <= niOliiOO WHEN niOO0liiO = '1' ELSE ni0O0Ol; + wire_nii10iOi_dataout <= ni0i1iil WHEN niOlOlilO = '1' ELSE wire_nii1i1Ol_dataout; + wire_nii10iOl_dataout <= ni0i1iiO WHEN niOlOlilO = '1' ELSE wire_nii1i1OO_dataout; + wire_nii10iOO_dataout <= ni11100O WHEN niOlOlilO = '1' ELSE ni0i1ili; + wire_nii10l0i_dataout <= ni0i1l1l WHEN niOlOlilO = '1' ELSE wire_nii1i00i_dataout; + wire_nii10l0l_dataout <= ni0i1l1O WHEN niOlOlilO = '1' ELSE wire_nii1i00l_dataout; + wire_nii10l0O_dataout <= ni0i1l0i WHEN niOlOlilO = '1' ELSE wire_nii1i00O_dataout; + wire_nii10l1i_dataout <= ni0i1iOl WHEN niOlOlilO = '1' ELSE wire_nii1i01i_dataout; + wire_nii10l1l_dataout <= ni0i1iOO WHEN niOlOlilO = '1' ELSE wire_nii1i01l_dataout; + wire_nii10l1O_dataout <= ni0i1l1i WHEN niOlOlilO = '1' ELSE wire_nii1i01O_dataout; + wire_nii10li_dataout <= niOlil1i WHEN niOO0liiO = '1' ELSE ni0O0OO; + wire_nii10lii_dataout <= ni0i1l0l WHEN niOlOlilO = '1' ELSE wire_nii1i0ii_dataout; + wire_nii10lil_dataout <= ni0i1l0O WHEN niOlOlilO = '1' ELSE wire_nii1i0il_dataout; + wire_nii10liO_dataout <= ni0i1lii WHEN niOlOlilO = '1' ELSE wire_nii1i0iO_dataout; + wire_nii10ll_dataout <= niOlil1l WHEN niOO0liiO = '1' ELSE ni0Oi1i; + wire_nii10lli_dataout <= ni0i1lil WHEN niOlOlilO = '1' ELSE wire_nii1i0li_dataout; + wire_nii10lll_dataout <= ni0i1liO WHEN niOlOlilO = '1' ELSE wire_nii1i0ll_dataout; + wire_nii10llO_dataout <= ni0i1lli WHEN niOlOlilO = '1' ELSE wire_nii1i0lO_dataout; + wire_nii10lO_dataout <= niOlil1O WHEN niOO0liiO = '1' ELSE ni0Oi1l; + wire_nii10lOi_dataout <= ni0i1lll WHEN niOlOlilO = '1' ELSE wire_nii1i0Oi_dataout; + wire_nii10lOl_dataout <= ni0i1llO WHEN niOlOlilO = '1' ELSE wire_nii1i0Ol_dataout; + wire_nii10lOO_dataout <= ni0i1lOi WHEN niOlOlilO = '1' ELSE wire_nii1i0OO_dataout; + wire_nii10O0i_dataout <= ni0i1O1l WHEN niOlOlilO = '1' ELSE wire_nii1ii0i_dataout; + wire_nii10O0l_dataout <= ni0i1O1O WHEN niOlOlilO = '1' ELSE wire_nii1ii0l_dataout; + wire_nii10O0O_dataout <= ni0i1O0i WHEN niOlOlilO = '1' ELSE wire_nii1ii0O_dataout; + wire_nii10O1i_dataout <= ni0i1lOl WHEN niOlOlilO = '1' ELSE wire_nii1ii1i_dataout; + wire_nii10O1l_dataout <= ni0i1lOO WHEN niOlOlilO = '1' ELSE wire_nii1ii1l_dataout; + wire_nii10O1O_dataout <= ni0i1O1i WHEN niOlOlilO = '1' ELSE wire_nii1ii1O_dataout; + wire_nii10Oi_dataout <= niOlil0i WHEN niOO0liiO = '1' ELSE ni0Oi1O; + wire_nii10Oii_dataout <= ni0i1O0l WHEN niOlOlilO = '1' ELSE wire_nii1iiii_dataout; + wire_nii10Oil_dataout <= ni0i1O0O WHEN niOlOlilO = '1' ELSE wire_nii1iiil_dataout; + wire_nii10OiO_dataout <= ni0i1Oii WHEN niOlOlilO = '1' ELSE wire_nii1iiiO_dataout; + wire_nii10Ol_dataout <= niOlil0l WHEN niOO0liiO = '1' ELSE ni0Oi0i; + wire_nii10Oli_dataout <= ni0i1Oil WHEN niOlOlilO = '1' ELSE wire_nii1iili_dataout; + wire_nii10Oll_dataout <= ni0i1OiO WHEN niOlOlilO = '1' ELSE wire_nii1iill_dataout; + wire_nii10OlO_dataout <= ni0i1Oli WHEN niOlOlilO = '1' ELSE wire_nii1iilO_dataout; + wire_nii10OO_dataout <= niOlil0O WHEN niOO0liiO = '1' ELSE ni0Oi0l; + wire_nii10OOi_dataout <= ni0i1Oll WHEN niOlOlilO = '1' ELSE wire_nii1iiOi_dataout; + wire_nii10OOl_dataout <= ni0i1OlO WHEN niOlOlilO = '1' ELSE wire_nii1iiOl_dataout; + wire_nii10OOO_dataout <= ni0i1OOi WHEN niOlOlilO = '1' ELSE wire_nii1iiOO_dataout; + wire_nii1100i_dataout <= ni0i1lOl WHEN niOlOlili = '1' ELSE wire_nii101ii_dataout; + wire_nii1100l_dataout <= ni0i1lOO WHEN niOlOlili = '1' ELSE wire_nii101il_dataout; + wire_nii1100O_dataout <= ni0i1O1i WHEN niOlOlili = '1' ELSE wire_nii101iO_dataout; + wire_nii1101i_dataout <= ni0i1lll WHEN niOlOlili = '1' ELSE wire_nii1010i_dataout; + wire_nii1101l_dataout <= ni0i1llO WHEN niOlOlili = '1' ELSE wire_nii1010l_dataout; + wire_nii1101O_dataout <= ni0i1lOi WHEN niOlOlili = '1' ELSE wire_nii1010O_dataout; + wire_nii110i_dataout <= wire_nii1iii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii110ii_dataout <= ni0i1O1l WHEN niOlOlili = '1' ELSE wire_nii101li_dataout; + wire_nii110il_dataout <= ni0i1O1O WHEN niOlOlili = '1' ELSE wire_nii101ll_dataout; + wire_nii110iO_dataout <= ni0i1O0i WHEN niOlOlili = '1' ELSE wire_nii101lO_dataout; + wire_nii110l_dataout <= wire_nii1iil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii110li_dataout <= ni0i1O0l WHEN niOlOlili = '1' ELSE wire_nii101Oi_dataout; + wire_nii110ll_dataout <= ni0i1O0O WHEN niOlOlili = '1' ELSE wire_nii101Ol_dataout; + wire_nii110lO_dataout <= ni0i1Oii WHEN niOlOlili = '1' ELSE wire_nii101OO_dataout; + wire_nii110O_dataout <= wire_nii1iiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii110Oi_dataout <= ni0i1Oil WHEN niOlOlili = '1' ELSE wire_nii1001i_dataout; + wire_nii110Ol_dataout <= ni0i1OiO WHEN niOlOlili = '1' ELSE wire_nii1001l_dataout; + wire_nii110OO_dataout <= ni0i1Oli WHEN niOlOlili = '1' ELSE wire_nii1001O_dataout; + wire_nii1110i_dataout <= ni0i1iOl WHEN niOlOlili = '1' ELSE wire_nii11Oii_dataout; + wire_nii1110l_dataout <= ni0i1iOO WHEN niOlOlili = '1' ELSE wire_nii11Oil_dataout; + wire_nii1110O_dataout <= ni0i1l1i WHEN niOlOlili = '1' ELSE wire_nii11OiO_dataout; + wire_nii1111i_dataout <= ni0i1ili WHEN niOlOlili = '1' ELSE wire_nii11O0l_dataout; + wire_nii1111l_dataout <= ni0i1ill WHEN niOlOlili = '1' ELSE wire_nii11O0O_dataout; + wire_nii1111O_dataout <= ni11100O WHEN niOlOlili = '1' ELSE ni0i1ilO; + wire_nii111i_dataout <= wire_nii1i0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii111ii_dataout <= ni0i1l1l WHEN niOlOlili = '1' ELSE wire_nii11Oli_dataout; + wire_nii111il_dataout <= ni0i1l1O WHEN niOlOlili = '1' ELSE wire_nii11Oll_dataout; + wire_nii111iO_dataout <= ni0i1l0i WHEN niOlOlili = '1' ELSE wire_nii11OlO_dataout; + wire_nii111l_dataout <= wire_nii1i0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii111li_dataout <= ni0i1l0l WHEN niOlOlili = '1' ELSE wire_nii11OOi_dataout; + wire_nii111ll_dataout <= ni0i1l0O WHEN niOlOlili = '1' ELSE wire_nii11OOl_dataout; + wire_nii111lO_dataout <= ni0i1lii WHEN niOlOlili = '1' ELSE wire_nii11OOO_dataout; + wire_nii111O_dataout <= wire_nii1i0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii111Oi_dataout <= ni0i1lil WHEN niOlOlili = '1' ELSE wire_nii1011i_dataout; + wire_nii111Ol_dataout <= ni0i1liO WHEN niOlOlili = '1' ELSE wire_nii1011l_dataout; + wire_nii111OO_dataout <= ni0i1lli WHEN niOlOlili = '1' ELSE wire_nii1011O_dataout; + wire_nii11i0i_dataout <= ni0i1OOl WHEN niOlOlili = '1' ELSE wire_nii100ii_dataout; + wire_nii11i0l_dataout <= ni0i1OOO WHEN niOlOlili = '1' ELSE wire_nii100il_dataout; + wire_nii11i0O_dataout <= ni0i011i WHEN niOlOlili = '1' ELSE wire_nii100iO_dataout; + wire_nii11i1i_dataout <= ni0i1Oll WHEN niOlOlili = '1' ELSE wire_nii1000i_dataout; + wire_nii11i1l_dataout <= ni0i1OlO WHEN niOlOlili = '1' ELSE wire_nii1000l_dataout; + wire_nii11i1O_dataout <= ni0i1OOi WHEN niOlOlili = '1' ELSE wire_nii1000O_dataout; + wire_nii11ii_dataout <= wire_nii1ili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii11iii_dataout <= ni0i011l WHEN niOlOlili = '1' ELSE wire_nii100li_dataout; + wire_nii11iil_dataout <= ni0i011O WHEN niOlOlili = '1' ELSE wire_nii100ll_dataout; + wire_nii11iiO_dataout <= ni0i010i WHEN niOlOlili = '1' ELSE wire_nii100lO_dataout; + wire_nii11il_dataout <= wire_nii1ill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii11ili_dataout <= ni0i010l WHEN niOlOlili = '1' ELSE wire_nii100Oi_dataout; + wire_nii11ill_dataout <= ni0i010O WHEN niOlOlili = '1' ELSE wire_nii100Ol_dataout; + wire_nii11ilO_dataout <= ni0i01ii WHEN niOlOlili = '1' ELSE wire_nii100OO_dataout; + wire_nii11iO_dataout <= wire_nii1ilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii11iOi_dataout <= ni0i01il WHEN niOlOlili = '1' ELSE wire_nii10i1i_dataout; + wire_nii11iOl_dataout <= ni0i01iO WHEN niOlOlili = '1' ELSE wire_nii10i1l_dataout; + wire_nii11iOO_dataout <= ni0i01li WHEN niOlOlili = '1' ELSE wire_nii10i1O_dataout; + wire_nii11l0i_dataout <= ni0i01Ol WHEN niOlOlili = '1' ELSE wire_nii10iii_dataout; + wire_nii11l0l_dataout <= ni0i01OO WHEN niOlOlili = '1' ELSE wire_nii10iil_dataout; + wire_nii11l0O_dataout <= ni0i001i WHEN niOlOlili = '1' ELSE wire_nii10iiO_dataout; + wire_nii11l1i_dataout <= ni0i01ll WHEN niOlOlili = '1' ELSE wire_nii10i0i_dataout; + wire_nii11l1l_dataout <= ni0i01lO WHEN niOlOlili = '1' ELSE wire_nii10i0l_dataout; + wire_nii11l1O_dataout <= ni0i01Oi WHEN niOlOlili = '1' ELSE wire_nii10i0O_dataout; + wire_nii11li_dataout <= wire_nii1iOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii11lii_dataout <= n0OOOllO WHEN niOlOlili = '1' ELSE ni0i001l; + wire_nii11lil_dataout <= ni1111Ol WHEN niOlOlili = '1' ELSE ni0i001O; + wire_nii11liO_dataout <= ni1111OO WHEN niOlOlili = '1' ELSE ni0i000i; + wire_nii11ll_dataout <= wire_nii1iOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii11lli_dataout <= ni11101i WHEN niOlOlili = '1' ELSE ni0i000l; + wire_nii11lll_dataout <= ni11101l WHEN niOlOlili = '1' ELSE ni0i000O; + wire_nii11llO_dataout <= ni11101O WHEN niOlOlili = '1' ELSE ni0i00ii; + wire_nii11lO_dataout <= wire_nii1iOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nii11lOi_dataout <= ni11100i WHEN niOlOlili = '1' ELSE ni0i00il; + wire_nii11lOl_dataout <= ni11100l WHEN niOlOlili = '1' ELSE ni0i00iO; + wire_nii11lOO_dataout <= wire_nii10ili_dataout AND NOT(niOlOlili); + wire_nii11O0i_dataout <= ni0i1iiO WHEN niOlOlill = '1' ELSE wire_nii10iOl_dataout; + wire_nii11O0l_dataout <= ni0i1ili WHEN niOlOlill = '1' ELSE wire_nii10iOO_dataout; + wire_nii11O0O_dataout <= ni11100O WHEN niOlOlill = '1' ELSE ni0i1ill; + wire_nii11O1i_dataout <= ni0i1i0O WHEN niOlOlill = '1' ELSE wire_nii10ill_dataout; + wire_nii11O1l_dataout <= ni0i1iii WHEN niOlOlill = '1' ELSE wire_nii10ilO_dataout; + wire_nii11O1O_dataout <= ni0i1iil WHEN niOlOlill = '1' ELSE wire_nii10iOi_dataout; + wire_nii11Oi_dataout <= wire_nii1l1i_dataout OR niOO0liiO; + wire_nii11Oii_dataout <= ni0i1iOl WHEN niOlOlill = '1' ELSE wire_nii10l1i_dataout; + wire_nii11Oil_dataout <= ni0i1iOO WHEN niOlOlill = '1' ELSE wire_nii10l1l_dataout; + wire_nii11OiO_dataout <= ni0i1l1i WHEN niOlOlill = '1' ELSE wire_nii10l1O_dataout; + wire_nii11Ol_dataout <= niOlii0l WHEN niOO0liiO = '1' ELSE ni0O00i; + wire_nii11Oli_dataout <= ni0i1l1l WHEN niOlOlill = '1' ELSE wire_nii10l0i_dataout; + wire_nii11Oll_dataout <= ni0i1l1O WHEN niOlOlill = '1' ELSE wire_nii10l0l_dataout; + wire_nii11OlO_dataout <= ni0i1l0i WHEN niOlOlill = '1' ELSE wire_nii10l0O_dataout; + wire_nii11OO_dataout <= niOlii0O WHEN niOO0liiO = '1' ELSE ni0O00l; + wire_nii11OOi_dataout <= ni0i1l0l WHEN niOlOlill = '1' ELSE wire_nii10lii_dataout; + wire_nii11OOl_dataout <= ni0i1l0O WHEN niOlOlill = '1' ELSE wire_nii10lil_dataout; + wire_nii11OOO_dataout <= ni0i1lii WHEN niOlOlill = '1' ELSE wire_nii10liO_dataout; + wire_nii1i00i_dataout <= ni0i1l1l WHEN niOlOliOi = '1' ELSE wire_nii1illi_dataout; + wire_nii1i00l_dataout <= ni0i1l1O WHEN niOlOliOi = '1' ELSE wire_nii1illl_dataout; + wire_nii1i00O_dataout <= ni0i1l0i WHEN niOlOliOi = '1' ELSE wire_nii1illO_dataout; + wire_nii1i01i_dataout <= ni0i1iOl WHEN niOlOliOi = '1' ELSE wire_nii1ilii_dataout; + wire_nii1i01l_dataout <= ni0i1iOO WHEN niOlOliOi = '1' ELSE wire_nii1ilil_dataout; + wire_nii1i01O_dataout <= ni0i1l1i WHEN niOlOliOi = '1' ELSE wire_nii1iliO_dataout; + wire_nii1i0i_dataout <= niOlilli WHEN niOO0liiO = '1' ELSE ni0OiiO; + wire_nii1i0ii_dataout <= ni0i1l0l WHEN niOlOliOi = '1' ELSE wire_nii1ilOi_dataout; + wire_nii1i0il_dataout <= ni0i1l0O WHEN niOlOliOi = '1' ELSE wire_nii1ilOl_dataout; + wire_nii1i0iO_dataout <= ni0i1lii WHEN niOlOliOi = '1' ELSE wire_nii1ilOO_dataout; + wire_nii1i0l_dataout <= niOlilll WHEN niOO0liiO = '1' ELSE ni0Oili; + wire_nii1i0li_dataout <= ni0i1lil WHEN niOlOliOi = '1' ELSE wire_nii1iO1i_dataout; + wire_nii1i0ll_dataout <= ni0i1liO WHEN niOlOliOi = '1' ELSE wire_nii1iO1l_dataout; + wire_nii1i0lO_dataout <= ni0i1lli WHEN niOlOliOi = '1' ELSE wire_nii1iO1O_dataout; + wire_nii1i0O_dataout <= niOlillO WHEN niOO0liiO = '1' ELSE ni0Oill; + wire_nii1i0Oi_dataout <= ni0i1lll WHEN niOlOliOi = '1' ELSE wire_nii1iO0i_dataout; + wire_nii1i0Ol_dataout <= ni0i1llO WHEN niOlOliOi = '1' ELSE wire_nii1iO0l_dataout; + wire_nii1i0OO_dataout <= ni0i1lOi WHEN niOlOliOi = '1' ELSE wire_nii1iO0O_dataout; + wire_nii1i10i_dataout <= ni1111Ol WHEN niOlOlilO = '1' ELSE ni0i011l; + wire_nii1i10l_dataout <= ni1111OO WHEN niOlOlilO = '1' ELSE ni0i011O; + wire_nii1i10O_dataout <= ni11101i WHEN niOlOlilO = '1' ELSE ni0i010i; + wire_nii1i11i_dataout <= ni0i1OOl WHEN niOlOlilO = '1' ELSE wire_nii1il1i_dataout; + wire_nii1i11l_dataout <= ni0i1OOO WHEN niOlOlilO = '1' ELSE wire_nii1il1l_dataout; + wire_nii1i11O_dataout <= n0OOOllO WHEN niOlOlilO = '1' ELSE ni0i011i; + wire_nii1i1i_dataout <= niOlilii WHEN niOO0liiO = '1' ELSE ni0Oi0O; + wire_nii1i1ii_dataout <= ni11101l WHEN niOlOlilO = '1' ELSE ni0i010l; + wire_nii1i1il_dataout <= ni11101O WHEN niOlOlilO = '1' ELSE ni0i010O; + wire_nii1i1iO_dataout <= ni11100i WHEN niOlOlilO = '1' ELSE ni0i01ii; + wire_nii1i1l_dataout <= niOlilil WHEN niOO0liiO = '1' ELSE ni0Oiii; + wire_nii1i1li_dataout <= ni11100l WHEN niOlOlilO = '1' ELSE ni0i01il; + wire_nii1i1ll_dataout <= wire_nii1il1O_dataout AND NOT(niOlOlilO); + wire_nii1i1lO_dataout <= ni0i1i0O WHEN niOlOliOi = '1' ELSE wire_nii1il0i_dataout; + wire_nii1i1O_dataout <= niOliliO WHEN niOO0liiO = '1' ELSE ni0Oiil; + wire_nii1i1Oi_dataout <= ni0i1iii WHEN niOlOliOi = '1' ELSE wire_nii1il0l_dataout; + wire_nii1i1Ol_dataout <= ni0i1iil WHEN niOlOliOi = '1' ELSE wire_nii1il0O_dataout; + wire_nii1i1OO_dataout <= ni11100O WHEN niOlOliOi = '1' ELSE ni0i1iiO; + wire_nii1ii0i_dataout <= ni0i1O1l WHEN niOlOliOi = '1' ELSE wire_nii1iOli_dataout; + wire_nii1ii0l_dataout <= ni0i1O1O WHEN niOlOliOi = '1' ELSE wire_nii1iOll_dataout; + wire_nii1ii0O_dataout <= ni0i1O0i WHEN niOlOliOi = '1' ELSE wire_nii1iOlO_dataout; + wire_nii1ii1i_dataout <= ni0i1lOl WHEN niOlOliOi = '1' ELSE wire_nii1iOii_dataout; + wire_nii1ii1l_dataout <= ni0i1lOO WHEN niOlOliOi = '1' ELSE wire_nii1iOil_dataout; + wire_nii1ii1O_dataout <= ni0i1O1i WHEN niOlOliOi = '1' ELSE wire_nii1iOiO_dataout; + wire_nii1iii_dataout <= niOlilOi WHEN niOO0liiO = '1' ELSE ni0OilO; + wire_nii1iiii_dataout <= ni0i1O0l WHEN niOlOliOi = '1' ELSE wire_nii1iOOi_dataout; + wire_nii1iiil_dataout <= ni0i1O0O WHEN niOlOliOi = '1' ELSE wire_nii1iOOl_dataout; + wire_nii1iiiO_dataout <= ni0i1Oii WHEN niOlOliOi = '1' ELSE wire_nii1iOOO_dataout; + wire_nii1iil_dataout <= niOlilOl WHEN niOO0liiO = '1' ELSE ni0OiOi; + wire_nii1iili_dataout <= n0OOOllO WHEN niOlOliOi = '1' ELSE ni0i1Oil; + wire_nii1iill_dataout <= ni1111Ol WHEN niOlOliOi = '1' ELSE ni0i1OiO; + wire_nii1iilO_dataout <= ni1111OO WHEN niOlOliOi = '1' ELSE ni0i1Oli; + wire_nii1iiO_dataout <= niOlilOO WHEN niOO0liiO = '1' ELSE ni0OiOl; + wire_nii1iiOi_dataout <= ni11101i WHEN niOlOliOi = '1' ELSE ni0i1Oll; + wire_nii1iiOl_dataout <= ni11101l WHEN niOlOliOi = '1' ELSE ni0i1OlO; + wire_nii1iiOO_dataout <= ni11101O WHEN niOlOliOi = '1' ELSE ni0i1OOi; + wire_nii1il0i_dataout <= ni0i1i0O WHEN niOlOll1l = '1' ELSE wire_nii1l11l_dataout; + wire_nii1il0l_dataout <= ni0i1iii WHEN niOlOll1l = '1' ELSE wire_nii1l11O_dataout; + wire_nii1il0O_dataout <= ni11100O WHEN niOlOll1l = '1' ELSE ni0i1iil; + wire_nii1il1i_dataout <= ni11100i WHEN niOlOliOi = '1' ELSE ni0i1OOl; + wire_nii1il1l_dataout <= ni11100l WHEN niOlOliOi = '1' ELSE ni0i1OOO; + wire_nii1il1O_dataout <= wire_nii1l11i_dataout AND NOT(niOlOliOi); + wire_nii1ili_dataout <= niOliO1i WHEN niOO0liiO = '1' ELSE ni0OiOO; + wire_nii1ilii_dataout <= ni0i1iOl WHEN niOlOll1l = '1' ELSE wire_nii1l10i_dataout; + wire_nii1ilil_dataout <= ni0i1iOO WHEN niOlOll1l = '1' ELSE wire_nii1l10l_dataout; + wire_nii1iliO_dataout <= ni0i1l1i WHEN niOlOll1l = '1' ELSE wire_nii1l10O_dataout; + wire_nii1ill_dataout <= niOliO1l WHEN niOO0liiO = '1' ELSE ni0Ol1i; + wire_nii1illi_dataout <= ni0i1l1l WHEN niOlOll1l = '1' ELSE wire_nii1l1ii_dataout; + wire_nii1illl_dataout <= ni0i1l1O WHEN niOlOll1l = '1' ELSE wire_nii1l1il_dataout; + wire_nii1illO_dataout <= ni0i1l0i WHEN niOlOll1l = '1' ELSE wire_nii1l1iO_dataout; + wire_nii1ilO_dataout <= niOliO1O WHEN niOO0liiO = '1' ELSE ni0Ol1l; + wire_nii1ilOi_dataout <= ni0i1l0l WHEN niOlOll1l = '1' ELSE wire_nii1l1li_dataout; + wire_nii1ilOl_dataout <= ni0i1l0O WHEN niOlOll1l = '1' ELSE wire_nii1l1ll_dataout; + wire_nii1ilOO_dataout <= ni0i1lii WHEN niOlOll1l = '1' ELSE wire_nii1l1lO_dataout; + wire_nii1iO0i_dataout <= ni0i1lll WHEN niOlOll1l = '1' ELSE wire_nii1l01i_dataout; + wire_nii1iO0l_dataout <= ni0i1llO WHEN niOlOll1l = '1' ELSE wire_nii1l01l_dataout; + wire_nii1iO0O_dataout <= ni0i1lOi WHEN niOlOll1l = '1' ELSE wire_nii1l01O_dataout; + wire_nii1iO1i_dataout <= ni0i1lil WHEN niOlOll1l = '1' ELSE wire_nii1l1Oi_dataout; + wire_nii1iO1l_dataout <= ni0i1liO WHEN niOlOll1l = '1' ELSE wire_nii1l1Ol_dataout; + wire_nii1iO1O_dataout <= ni0i1lli WHEN niOlOll1l = '1' ELSE wire_nii1l1OO_dataout; + wire_nii1iOi_dataout <= niOliO0i WHEN niOO0liiO = '1' ELSE ni0Ol1O; + wire_nii1iOii_dataout <= ni0i1lOl WHEN niOlOll1l = '1' ELSE wire_nii1l00i_dataout; + wire_nii1iOil_dataout <= n0OOOllO WHEN niOlOll1l = '1' ELSE ni0i1lOO; + wire_nii1iOiO_dataout <= ni1111Ol WHEN niOlOll1l = '1' ELSE ni0i1O1i; + wire_nii1iOl_dataout <= niOliO0l WHEN niOO0liiO = '1' ELSE ni0Ol0i; + wire_nii1iOli_dataout <= ni1111OO WHEN niOlOll1l = '1' ELSE ni0i1O1l; + wire_nii1iOll_dataout <= ni11101i WHEN niOlOll1l = '1' ELSE ni0i1O1O; + wire_nii1iOlO_dataout <= ni11101l WHEN niOlOll1l = '1' ELSE ni0i1O0i; + wire_nii1iOO_dataout <= niOliO0O WHEN niOO0liiO = '1' ELSE ni0Ol0l; + wire_nii1iOOi_dataout <= ni11101O WHEN niOlOll1l = '1' ELSE ni0i1O0l; + wire_nii1iOOl_dataout <= ni11100i WHEN niOlOll1l = '1' ELSE ni0i1O0O; + wire_nii1iOOO_dataout <= ni11100l WHEN niOlOll1l = '1' ELSE ni0i1Oii; + wire_nii1l00i_dataout <= ni11100l WHEN niOlOll1O = '1' ELSE ni0i1lOl; + wire_nii1l01i_dataout <= ni11101l WHEN niOlOll1O = '1' ELSE ni0i1lll; + wire_nii1l01l_dataout <= ni11101O WHEN niOlOll1O = '1' ELSE ni0i1llO; + wire_nii1l01O_dataout <= ni11100i WHEN niOlOll1O = '1' ELSE ni0i1lOi; + wire_nii1l0ii_dataout <= wire_nii1O1Ol_dataout AND NOT(ni0i1i0i); + wire_nii1l0il_dataout <= wire_nii1O1OO_dataout AND NOT(ni0i1i0i); + wire_nii1l0iO_dataout <= wire_nii1O01i_dataout AND NOT(ni0i1i0i); + wire_nii1l0li_dataout <= wire_nii1O01l_dataout AND NOT(ni0i1i0i); + wire_nii1l0ll_dataout <= ni11OOOi WHEN ni0i1i0i = '1' ELSE wire_nii1O01O_dataout; + wire_nii1l0lO_dataout <= ni11100O WHEN ni0i1i0i = '1' ELSE wire_nii1O00i_dataout; + wire_nii1l0Oi_dataout <= ni0i110l WHEN ni0i1i0i = '1' ELSE wire_nii1O00l_dataout; + wire_nii1l0Ol_dataout <= wire_nii1O00O_dataout AND NOT(ni0i1i0i); + wire_nii1l0OO_dataout <= wire_nii1O0ii_dataout AND NOT(ni0i1i0i); + wire_nii1l10i_dataout <= ni0i1iOl WHEN niOlOll1O = '1' ELSE n0OOOllO; + wire_nii1l10l_dataout <= ni0i1iOO WHEN niOlOll1O = '1' ELSE ni1111Ol; + wire_nii1l10O_dataout <= ni0i1l1i WHEN niOlOll1O = '1' ELSE ni1111OO; + wire_nii1l11i_dataout <= wire_w_lg_niOlOll1O10153w(0) AND NOT(niOlOll1l); + wire_nii1l11l_dataout <= ni0i1i0O WHEN niOlOll1O = '1' ELSE ni11100O; + wire_nii1l11O_dataout <= ni11100O WHEN niOlOll1O = '1' ELSE ni0i1iii; + wire_nii1l1i_dataout <= ni0O1li AND ni0O01i; + wire_nii1l1ii_dataout <= ni0i1l1l WHEN niOlOll1O = '1' ELSE ni11101i; + wire_nii1l1il_dataout <= ni0i1l1O WHEN niOlOll1O = '1' ELSE ni11101l; + wire_nii1l1iO_dataout <= ni0i1l0i WHEN niOlOll1O = '1' ELSE ni11101O; + wire_nii1l1li_dataout <= ni0i1l0l WHEN niOlOll1O = '1' ELSE ni11100i; + wire_nii1l1ll_dataout <= ni0i1l0O WHEN niOlOll1O = '1' ELSE ni11100l; + wire_nii1l1lO_dataout <= n0OOOllO WHEN niOlOll1O = '1' ELSE ni0i1lii; + wire_nii1l1Oi_dataout <= ni1111Ol WHEN niOlOll1O = '1' ELSE ni0i1lil; + wire_nii1l1Ol_dataout <= ni1111OO WHEN niOlOll1O = '1' ELSE ni0i1liO; + wire_nii1l1OO_dataout <= ni11101i WHEN niOlOll1O = '1' ELSE ni0i1lli; + wire_nii1li0i_dataout <= wire_nii1O0ll_dataout AND NOT(ni0i1i0i); + wire_nii1li0l_dataout <= wire_nii1O0lO_dataout AND NOT(ni0i1i0i); + wire_nii1li0O_dataout <= wire_nii1O0Oi_dataout AND NOT(ni0i1i0i); + wire_nii1li1i_dataout <= wire_nii1O0il_dataout AND NOT(ni0i1i0i); + wire_nii1li1l_dataout <= wire_nii1O0iO_dataout AND NOT(ni0i1i0i); + wire_nii1li1O_dataout <= wire_nii1O0li_dataout AND NOT(ni0i1i0i); + wire_nii1liii_dataout <= wire_nii1O0Ol_dataout AND NOT(ni0i1i0i); + wire_nii1liil_dataout <= wire_nii1O0OO_dataout AND NOT(ni0i1i0i); + wire_nii1liiO_dataout <= wire_nii1Oi1i_dataout AND NOT(ni0i1i0i); + wire_nii1lili_dataout <= wire_nii1Oi1l_dataout AND NOT(ni0i1i0i); + wire_nii1lill_dataout <= wire_nii1Oi1O_dataout AND NOT(ni0i1i0i); + wire_nii1lilO_dataout <= wire_nii1Oi0i_dataout AND NOT(ni0i1i0i); + wire_nii1liOi_dataout <= wire_nii1Oi0l_dataout AND NOT(ni0i1i0i); + wire_nii1liOl_dataout <= wire_nii1Oi0O_dataout AND NOT(ni0i1i0i); + wire_nii1liOO_dataout <= wire_nii1Oiii_dataout AND NOT(ni0i1i0i); + wire_nii1ll0i_dataout <= wire_nii1Oill_dataout AND NOT(ni0i1i0i); + wire_nii1ll0l_dataout <= wire_nii1OilO_dataout AND NOT(ni0i1i0i); + wire_nii1ll0O_dataout <= wire_nii1OiOi_dataout AND NOT(ni0i1i0i); + wire_nii1ll1i_dataout <= wire_nii1Oiil_dataout AND NOT(ni0i1i0i); + wire_nii1ll1l_dataout <= wire_nii1OiiO_dataout AND NOT(ni0i1i0i); + wire_nii1ll1O_dataout <= wire_nii1Oili_dataout AND NOT(ni0i1i0i); + wire_nii1llii_dataout <= wire_nii1OiOl_dataout AND NOT(ni0i1i0i); + wire_nii1llil_dataout <= wire_nii1OiOO_dataout AND NOT(ni0i1i0i); + wire_nii1lliO_dataout <= wire_nii1Ol1i_dataout AND NOT(ni0i1i0i); + wire_nii1llli_dataout <= wire_nii1Ol1l_dataout AND NOT(ni0i1i0i); + wire_nii1llll_dataout <= wire_nii1Ol1O_dataout AND NOT(ni0i1i0i); + wire_nii1lllO_dataout <= wire_nii1Ol0i_dataout AND NOT(ni0i1i0i); + wire_nii1llOi_dataout <= wire_nii1Ol0l_dataout AND NOT(ni0i1i0i); + wire_nii1llOl_dataout <= wire_nii1Ol0O_dataout AND NOT(ni0i1i0i); + wire_nii1llOO_dataout <= wire_nii1Olii_dataout AND NOT(ni0i1i0i); + wire_nii1lO0i_dataout <= ni11OOil WHEN ni0i1i0i = '1' ELSE wire_nii1Olll_dataout; + wire_nii1lO0l_dataout <= ni11OOiO WHEN ni0i1i0i = '1' ELSE wire_nii1OllO_dataout; + wire_nii1lO0O_dataout <= ni11OOli WHEN ni0i1i0i = '1' ELSE wire_nii1OlOi_dataout; + wire_nii1lO1i_dataout <= ni11Oi0i WHEN ni0i1i0i = '1' ELSE wire_nii1Olil_dataout; + wire_nii1lO1l_dataout <= ni11OO0O WHEN ni0i1i0i = '1' ELSE wire_nii1OliO_dataout; + wire_nii1lO1O_dataout <= ni11OOii WHEN ni0i1i0i = '1' ELSE wire_nii1Olli_dataout; + wire_nii1lOii_dataout <= ni11OOll WHEN ni0i1i0i = '1' ELSE wire_nii1OlOl_dataout; + wire_nii1lOil_dataout <= ni11OOlO WHEN ni0i1i0i = '1' ELSE wire_nii1OlOO_dataout; + wire_nii1lOiO_dataout <= n0OOOllO WHEN ni0i1i0i = '1' ELSE wire_nii1OO1i_dataout; + wire_nii1lOli_dataout <= ni1111Ol WHEN ni0i1i0i = '1' ELSE wire_nii1OO1l_dataout; + wire_nii1lOll_dataout <= ni1111OO WHEN ni0i1i0i = '1' ELSE wire_nii1OO1O_dataout; + wire_nii1lOlO_dataout <= ni11101i WHEN ni0i1i0i = '1' ELSE wire_nii1OO0i_dataout; + wire_nii1lOOi_dataout <= ni11101l WHEN ni0i1i0i = '1' ELSE wire_nii1OO0l_dataout; + wire_nii1lOOl_dataout <= ni11101O WHEN ni0i1i0i = '1' ELSE wire_nii1OO0O_dataout; + wire_nii1lOOO_dataout <= ni11100i WHEN ni0i1i0i = '1' ELSE wire_nii1OOii_dataout; + wire_nii1O00i_dataout <= wire_nii011ll_dataout AND NOT(niOlOll0l); + wire_nii1O00l_dataout <= ni11OOOi WHEN niOlOll0l = '1' ELSE ni0i1ilO; + wire_nii1O00O_dataout <= wire_nii011lO_dataout AND NOT(niOlOll0l); + wire_nii1O01i_dataout <= wire_nii011il_dataout AND NOT(niOlOll0l); + wire_nii1O01l_dataout <= wire_nii011iO_dataout AND NOT(niOlOll0l); + wire_nii1O01O_dataout <= wire_nii011li_dataout AND NOT(niOlOll0l); + wire_nii1O0ii_dataout <= wire_nii011Oi_dataout AND NOT(niOlOll0l); + wire_nii1O0il_dataout <= wire_nii011Ol_dataout AND NOT(niOlOll0l); + wire_nii1O0iO_dataout <= wire_nii011OO_dataout AND NOT(niOlOll0l); + wire_nii1O0li_dataout <= wire_nii0101i_dataout AND NOT(niOlOll0l); + wire_nii1O0ll_dataout <= wire_nii0101l_dataout AND NOT(niOlOll0l); + wire_nii1O0lO_dataout <= wire_nii0101O_dataout AND NOT(niOlOll0l); + wire_nii1O0Oi_dataout <= wire_nii0100i_dataout AND NOT(niOlOll0l); + wire_nii1O0Ol_dataout <= wire_nii0100l_dataout AND NOT(niOlOll0l); + wire_nii1O0OO_dataout <= wire_nii0100O_dataout AND NOT(niOlOll0l); + wire_nii1O10i_dataout <= ni0i100l WHEN ni0i1i0i = '1' ELSE wire_nii1OOll_dataout; + wire_nii1O10l_dataout <= ni0i100O WHEN ni0i1i0i = '1' ELSE wire_nii1OOlO_dataout; + wire_nii1O10O_dataout <= ni0i10ii WHEN ni0i1i0i = '1' ELSE wire_nii1OOOi_dataout; + wire_nii1O11i_dataout <= ni11100l WHEN ni0i1i0i = '1' ELSE wire_nii1OOil_dataout; + wire_nii1O11l_dataout <= ni0i101O WHEN ni0i1i0i = '1' ELSE wire_nii1OOiO_dataout; + wire_nii1O11O_dataout <= ni0i100i WHEN ni0i1i0i = '1' ELSE wire_nii1OOli_dataout; + wire_nii1O1ii_dataout <= ni0i10il WHEN ni0i1i0i = '1' ELSE wire_nii1OOOl_dataout; + wire_nii1O1il_dataout <= ni0i10iO WHEN ni0i1i0i = '1' ELSE wire_nii1OOOO_dataout; + wire_nii1O1iO_dataout <= ni0i10li WHEN ni0i1i0i = '1' ELSE wire_nii0111i_dataout; + wire_nii1O1li_dataout <= wire_nii0111l_dataout AND NOT(ni0i1i0i); + wire_nii1O1ll_dataout <= wire_nii0111O_dataout AND NOT(ni0i1i0i); + wire_nii1O1lO_dataout <= wire_nii0110i_dataout OR ni0i1i0i; + wire_nii1O1Oi_dataout <= wire_nii0110l_dataout AND NOT(ni0i1i0i); + wire_nii1O1Ol_dataout <= wire_nii0110O_dataout AND NOT(niOlOll0l); + wire_nii1O1OO_dataout <= wire_nii011ii_dataout AND NOT(niOlOll0l); + wire_nii1Oi0i_dataout <= wire_nii010li_dataout AND NOT(niOlOll0l); + wire_nii1Oi0l_dataout <= wire_nii010ll_dataout AND NOT(niOlOll0l); + wire_nii1Oi0O_dataout <= wire_nii010lO_dataout AND NOT(niOlOll0l); + wire_nii1Oi1i_dataout <= wire_nii010ii_dataout AND NOT(niOlOll0l); + wire_nii1Oi1l_dataout <= wire_nii010il_dataout AND NOT(niOlOll0l); + wire_nii1Oi1O_dataout <= wire_nii010iO_dataout AND NOT(niOlOll0l); + wire_nii1Oiii_dataout <= wire_nii010Oi_dataout AND NOT(niOlOll0l); + wire_nii1Oiil_dataout <= wire_nii010Ol_dataout AND NOT(niOlOll0l); + wire_nii1OiiO_dataout <= wire_nii010OO_dataout AND NOT(niOlOll0l); + wire_nii1Oili_dataout <= wire_nii01i1i_dataout AND NOT(niOlOll0l); + wire_nii1Oill_dataout <= wire_nii01i1l_dataout AND NOT(niOlOll0l); + wire_nii1OilO_dataout <= wire_nii01i1O_dataout AND NOT(niOlOll0l); + wire_nii1OiOi_dataout <= wire_nii01i0i_dataout AND NOT(niOlOll0l); + wire_nii1OiOl_dataout <= wire_nii01i0l_dataout AND NOT(niOlOll0l); + wire_nii1OiOO_dataout <= wire_nii01i0O_dataout AND NOT(niOlOll0l); + wire_nii1Ol0i_dataout <= wire_nii01ili_dataout AND NOT(niOlOll0l); + wire_nii1Ol0l_dataout <= wire_nii01ill_dataout AND NOT(niOlOll0l); + wire_nii1Ol0O_dataout <= wire_nii01ilO_dataout AND NOT(niOlOll0l); + wire_nii1Ol1i_dataout <= wire_nii01iii_dataout AND NOT(niOlOll0l); + wire_nii1Ol1l_dataout <= wire_nii01iil_dataout AND NOT(niOlOll0l); + wire_nii1Ol1O_dataout <= wire_nii01iiO_dataout AND NOT(niOlOll0l); + wire_nii1Olii_dataout <= wire_nii01iOi_dataout AND NOT(niOlOll0l); + wire_nii1Olil_dataout <= wire_nii01iOl_dataout AND NOT(niOlOll0l); + wire_nii1OliO_dataout <= wire_nii01iOO_dataout AND NOT(niOlOll0l); + wire_nii1Olli_dataout <= wire_nii01l1i_dataout AND NOT(niOlOll0l); + wire_nii1Olll_dataout <= wire_nii01l1l_dataout AND NOT(niOlOll0l); + wire_nii1OllO_dataout <= wire_nii01l1O_dataout AND NOT(niOlOll0l); + wire_nii1OlOi_dataout <= wire_nii01l0i_dataout AND NOT(niOlOll0l); + wire_nii1OlOl_dataout <= wire_nii01l0l_dataout AND NOT(niOlOll0l); + wire_nii1OlOO_dataout <= wire_nii01l0O_dataout AND NOT(niOlOll0l); + wire_nii1OO0i_dataout <= wire_nii01lli_dataout AND NOT(niOlOll0l); + wire_nii1OO0l_dataout <= wire_nii01lll_dataout AND NOT(niOlOll0l); + wire_nii1OO0O_dataout <= wire_nii01llO_dataout AND NOT(niOlOll0l); + wire_nii1OO1i_dataout <= wire_nii01lii_dataout AND NOT(niOlOll0l); + wire_nii1OO1l_dataout <= wire_nii01lil_dataout AND NOT(niOlOll0l); + wire_nii1OO1O_dataout <= wire_nii01liO_dataout AND NOT(niOlOll0l); + wire_nii1OOii_dataout <= wire_nii01lOi_dataout AND NOT(niOlOll0l); + wire_nii1OOil_dataout <= wire_nii01lOl_dataout AND NOT(niOlOll0l); + wire_nii1OOiO_dataout <= ni11Oi0i WHEN niOlOll0l = '1' ELSE ni0i001l; + wire_nii1OOli_dataout <= ni11OO0O WHEN niOlOll0l = '1' ELSE ni0i001O; + wire_nii1OOll_dataout <= ni11OOii WHEN niOlOll0l = '1' ELSE ni0i000i; + wire_nii1OOlO_dataout <= ni11OOil WHEN niOlOll0l = '1' ELSE ni0i000l; + wire_nii1OOOi_dataout <= ni11OOiO WHEN niOlOll0l = '1' ELSE ni0i000O; + wire_nii1OOOl_dataout <= ni11OOli WHEN niOlOll0l = '1' ELSE ni0i00ii; + wire_nii1OOOO_dataout <= ni11OOll WHEN niOlOll0l = '1' ELSE ni0i00il; + wire_niii000i_dataout <= wire_niii000l_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiiiOOO10014w(0))); + wire_niii000l_dataout <= niii1O0O OR wire_niii0lii_dataout; + wire_niii001i_dataout <= niii1Oii OR wire_niii0lil_dataout; + wire_niii001O_dataout <= wire_niii000i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii00ii_dataout <= wire_niii00il_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii00il_dataout <= wire_niii00iO_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiil11i10012w(0))); + wire_niii00iO_dataout <= niii1O0l OR wire_niii0l0O_dataout; + wire_niii00ll_dataout <= wire_niii00lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii00lO_dataout <= wire_niii00Oi_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiil11l10010w(0))); + wire_niii00Oi_dataout <= niii1llO OR wire_niii0l0l_dataout; + wire_niii010i_dataout <= niii1Oli OR wire_niii0lll_dataout; + wire_niii010O_dataout <= wire_niii01ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii011l_dataout <= wire_niii011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii011O_dataout <= wire_niii010i_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiiiOll10022w(0))); + wire_niii01ii_dataout <= wire_niii01il_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiiiOlO10020w(0))); + wire_niii01il_dataout <= niii1OiO OR wire_niii0lli_dataout; + wire_niii01li_dataout <= wire_niii01ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii01ll_dataout <= wire_niii01lO_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiiiOOi10018w(0))); + wire_niii01lO_dataout <= niii1Oil OR wire_niii0liO_dataout; + wire_niii01Ol_dataout <= wire_niii01OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii01OO_dataout <= wire_niii001i_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiiiOOl10016w(0))); + wire_niii0i0i_dataout <= wire_niii0iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii0i0l_dataout <= wire_niii0iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii0i0O_dataout <= wire_niii0iiO_o(0) AND NOT(niOlOOlii); + wire_niii0i1O_dataout <= wire_niii0i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii0iii_dataout <= wire_niii0iiO_o(1) AND NOT(niOlOOlii); + wire_niii0iil_dataout <= wire_niii0iiO_o(2) AND NOT(niOlOOlii); + wire_niii0l0l_dataout <= n0O0O00i WHEN n1101l1i = '1' ELSE wire_niii0lOi_dataout; + wire_niii0l0O_dataout <= n0ll0iOO WHEN n1101l1i = '1' ELSE wire_niii0lOl_dataout; + wire_niii0lii_dataout <= n0iOlOll WHEN n1101l1i = '1' ELSE wire_niii0lOO_dataout; + wire_niii0lil_dataout <= n0i000ii WHEN n1101l1i = '1' ELSE wire_niii0O1i_dataout; + wire_niii0liO_dataout <= n00ill1O WHEN n1101l1i = '1' ELSE wire_niii0O1l_dataout; + wire_niii0lli_dataout <= n01O1OOl WHEN n1101l1i = '1' ELSE wire_niii0O1O_dataout; + wire_niii0lll_dataout <= n011l0li WHEN n1101l1i = '1' ELSE wire_niii0O0i_dataout; + wire_niii0llO_dataout <= n1Oi1l0O WHEN n1101l1i = '1' ELSE wire_niii0O0l_dataout; + wire_niii0lOi_dataout <= n00ill1O WHEN n1101iOO = '1' ELSE wire_niii0O0O_dataout; + wire_niii0lOl_dataout <= n01O1OOl WHEN n1101iOO = '1' ELSE wire_niii0Oii_dataout; + wire_niii0lOO_dataout <= n011l0li WHEN n1101iOO = '1' ELSE wire_niii0Oil_dataout; + wire_niii0O0i_dataout <= wire_niii0OlO_dataout AND NOT(n1101iOO); + wire_niii0O0l_dataout <= wire_niii0OOi_dataout AND NOT(n1101iOO); + wire_niii0O0O_dataout <= n011l0li WHEN n1101iOl = '1' ELSE n1Oi1l0O; + wire_niii0O1i_dataout <= n1Oi1l0O WHEN n1101iOO = '1' ELSE wire_niii0OiO_dataout; + wire_niii0O1l_dataout <= wire_niii0Oli_dataout AND NOT(n1101iOO); + wire_niii0O1O_dataout <= wire_niii0Oll_dataout AND NOT(n1101iOO); + wire_niii0Oii_dataout <= n1Oi1l0O WHEN n1101iOl = '1' ELSE n011l0li; + wire_niii0Oil_dataout <= n01O1OOl AND NOT(n1101iOl); + wire_niii0OiO_dataout <= n00ill1O AND NOT(n1101iOl); + wire_niii0Oli_dataout <= n0i000ii AND NOT(n1101iOl); + wire_niii0Oll_dataout <= n0iOlOll AND NOT(n1101iOl); + wire_niii0OlO_dataout <= n0ll0iOO AND NOT(n1101iOl); + wire_niii0OOi_dataout <= n0O0O00i AND NOT(n1101iOl); + wire_niii100i_dataout <= niiiillO AND NOT(niOlOOi1O); + wire_niii100l_dataout <= niiiilOi AND NOT(niOlOOi1O); + wire_niii100O_dataout <= niiiilOl AND NOT(niOlOOi1O); + wire_niii101i_dataout <= niiiiliO AND NOT(niOlOOi1O); + wire_niii101l_dataout <= niiiilli AND NOT(niOlOOi1O); + wire_niii101O_dataout <= niiiilll AND NOT(niOlOOi1O); + wire_niii10ii_dataout <= niiiilOO AND NOT(niOlOOi1O); + wire_niii10il_dataout <= niiiilii AND NOT(niOlOOi1O); + wire_niii11il_dataout <= wire_niii11iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii11iO_dataout <= wire_niii11li_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i01l9986w10055w(0))); + wire_niii11li_dataout <= nii0OllO OR ((n111i10O AND niiiiOOO) AND niOlOOi1l); + wire_niii11OO_dataout <= niiiilil AND NOT(niOlOOi1O); + wire_niii1i0i_dataout <= wire_niii1i0l_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i01i9990w10042w(0))); + wire_niii1i0l_dataout <= niii11ii OR ((n111i10O AND niiil11i) AND niOlOOill); + wire_niii1i1O_dataout <= wire_niii1i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii1ili_dataout <= niiiiO1l AND NOT(niOlOOilO); + wire_niii1ill_dataout <= niiiiO1O AND NOT(niOlOOilO); + wire_niii1ilO_dataout <= niiiiO0i AND NOT(niOlOOilO); + wire_niii1iOi_dataout <= niiiiO0l AND NOT(niOlOOilO); + wire_niii1iOl_dataout <= niiiiO0O AND NOT(niOlOOilO); + wire_niii1iOO_dataout <= niiiiOii AND NOT(niOlOOilO); + wire_niii1l1i_dataout <= niiiiOil AND NOT(niOlOOilO); + wire_niii1l1l_dataout <= niiiiOiO AND NOT(niOlOOilO); + wire_niii1l1O_dataout <= niiiiO1i AND NOT(niOlOOilO); + wire_niii1lOi_dataout <= wire_niii1lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii1lOl_dataout <= wire_niii1lOO_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_w_lg_n111i1OO10028w10029w(0))); + wire_niii1lOO_dataout <= niii1i1l OR ((n111i10O AND niiil11l) AND niOlOOl0O); + wire_niii1OOi_dataout <= wire_niii1OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_niii1OOl_dataout <= wire_niii1OOO_dataout AND NOT((wire_niO01ill_w_lg_n111i10O9993w(0) OR wire_niO01ill_w_lg_niiiiOli10024w(0))); + wire_niii1OOO_dataout <= niii1Oll OR wire_niii0llO_dataout; + wire_niiil00i_dataout <= wire_niiiO0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil00l_dataout <= wire_niiiO0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil00O_dataout <= wire_niiiO0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil01i_dataout <= wire_niiiO0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil01l_dataout <= wire_niiiO0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil01O_dataout <= wire_niiiO0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0ii_dataout <= wire_niiiO0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0il_dataout <= wire_niiiO0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0iO_dataout <= wire_niiiOi1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0li_dataout <= wire_niiiOi1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0ll_dataout <= wire_niiiOi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0lO_dataout <= wire_niiiOi0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0Oi_dataout <= wire_niiiOi0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0Ol_dataout <= wire_niiiOi0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil0OO_dataout <= wire_niiiOiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil10i_dataout <= wire_niiiO1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil10l_dataout <= wire_niiiO1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil10O_dataout <= wire_niiiO1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil11O_dataout <= wire_niiiO1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1ii_dataout <= wire_niiiO1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1il_dataout <= wire_niiiO1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1iO_dataout <= wire_niiiO1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1li_dataout <= wire_niiiO1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1ll_dataout <= wire_niiiO01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1lO_dataout <= wire_niiiO01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1Oi_dataout <= wire_niiiO00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1Ol_dataout <= wire_niiiO00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiil1OO_dataout <= wire_niiiO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiili0i_dataout <= wire_niiiOilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiili0l_dataout <= wire_niiiOiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiili0O_dataout <= wire_niiiOiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiili1i_dataout <= wire_niiiOiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiili1l_dataout <= wire_niiiOili_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiili1O_dataout <= wire_niiiOill_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiliii_dataout <= wire_niiiOiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiliil_dataout <= wire_niiiOl1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiliiO_dataout <= wire_niiiOl1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilili_dataout <= wire_niiiOl0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilill_dataout <= wire_niiiOl0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiililO_dataout <= wire_niiiOl0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiliOi_dataout <= wire_niiiOlii_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiliOl_dataout <= wire_niiiOlil_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiliOO_dataout <= wire_niiiOliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiill0i_dataout <= wire_niiiOlOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiill0l_dataout <= wire_niiiOlOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiill0O_dataout <= wire_niiiOO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiill1i_dataout <= wire_niiiOlli_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiill1l_dataout <= wire_niiiOlll_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiill1O_dataout <= wire_niiiOlOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiillii_dataout <= wire_niiiOO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiillil_dataout <= wire_niiiOO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilliO_dataout <= wire_niiiOO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiillli_dataout <= wire_niiiOO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiillll_dataout <= wire_niiiOO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilllO_dataout <= wire_niil11Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiillOi_dataout <= wire_niil11Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiillOl_dataout <= wire_niil11OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiillOO_dataout <= wire_niil101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilO0i_dataout <= wire_niil100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilO0l_dataout <= wire_niil100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilO0O_dataout <= wire_niil10il_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilO1i_dataout <= wire_niil101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilO1l_dataout <= wire_niil101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilO1O_dataout <= wire_niil100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOii_dataout <= wire_niil10iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOil_dataout <= wire_niil10li_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOiO_dataout <= wire_niil10ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOli_dataout <= wire_niil10lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOll_dataout <= wire_niil10Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOlO_dataout <= wire_niil10Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOOi_dataout <= wire_niil10OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOOl_dataout <= wire_niil1i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiilOOO_dataout <= wire_niiiO01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO00i_dataout <= wire_n011i11i_dataout WHEN n1101l1i = '1' ELSE wire_n0ll100O_dataout; + wire_niiiO00l_dataout <= wire_n011i11l_dataout WHEN n1101l1i = '1' ELSE wire_n0ll10ii_dataout; + wire_niiiO00O_dataout <= wire_n011i11O_dataout WHEN n1101l1i = '1' ELSE wire_n0ll10il_dataout; + wire_niiiO01i_dataout <= wire_n1O0Oi0i_dataout WHEN n1101l1i = '1' ELSE wire_n0O0l11l_dataout; + wire_niiiO01l_dataout <= wire_niO10O1l_dataout WHEN n1101l1i = '1' ELSE wire_niO11i1l_dataout; + wire_niiiO01O_dataout <= wire_n0110OOO_dataout WHEN n1101l1i = '1' ELSE wire_n0ll100l_dataout; + wire_niiiO0ii_dataout <= wire_n011i10i_dataout WHEN n1101l1i = '1' ELSE wire_n0ll10iO_dataout; + wire_niiiO0il_dataout <= wire_n011i10l_dataout WHEN n1101l1i = '1' ELSE wire_n0ll10li_dataout; + wire_niiiO0iO_dataout <= wire_n011i10O_dataout WHEN n1101l1i = '1' ELSE wire_n0ll10ll_dataout; + wire_niiiO0li_dataout <= wire_n011i1ii_dataout WHEN n1101l1i = '1' ELSE wire_n0ll10lO_dataout; + wire_niiiO0ll_dataout <= wire_n011i1il_dataout WHEN n1101l1i = '1' ELSE wire_n0ll10Oi_dataout; + wire_niiiO0lO_dataout <= wire_niO10l1l_dataout WHEN n1101l1i = '1' ELSE wire_niO11l1l_dataout; + wire_niiiO0Oi_dataout <= wire_n01lOl0i_dataout WHEN n1101l1i = '1' ELSE wire_n0iOil1i_dataout; + wire_niiiO0Ol_dataout <= wire_n01lOl0l_dataout WHEN n1101l1i = '1' ELSE wire_n0iOil1l_dataout; + wire_niiiO0OO_dataout <= wire_n01lOl0O_dataout WHEN n1101l1i = '1' ELSE wire_n0iOil1O_dataout; + wire_niiiO10i_dataout <= wire_niiiOllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO10l_dataout <= wire_niiiOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO10O_dataout <= wire_niil10ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO11i_dataout <= wire_niiiO0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO11l_dataout <= wire_niiiOiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO11O_dataout <= wire_niiiOl1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO1ii_dataout <= wire_niil1i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niiiO1il_dataout <= wire_n1O0O0ll_dataout WHEN n1101l1i = '1' ELSE wire_n0O0iOiO_dataout; + wire_niiiO1iO_dataout <= wire_n1O0O0lO_dataout WHEN n1101l1i = '1' ELSE wire_n0O0iOli_dataout; + wire_niiiO1li_dataout <= wire_n1O0O0Oi_dataout WHEN n1101l1i = '1' ELSE wire_n0O0iOll_dataout; + wire_niiiO1ll_dataout <= wire_n1O0O0Ol_dataout WHEN n1101l1i = '1' ELSE wire_n0O0iOlO_dataout; + wire_niiiO1lO_dataout <= wire_n1O0O0OO_dataout WHEN n1101l1i = '1' ELSE wire_n0O0iOOi_dataout; + wire_niiiO1Oi_dataout <= wire_n1O0Oi1i_dataout WHEN n1101l1i = '1' ELSE wire_n0O0iOOl_dataout; + wire_niiiO1Ol_dataout <= wire_n1O0Oi1l_dataout WHEN n1101l1i = '1' ELSE wire_n0O0iOOO_dataout; + wire_niiiO1OO_dataout <= wire_n1O0Oi1O_dataout WHEN n1101l1i = '1' ELSE wire_n0O0l11i_dataout; + wire_niiiOi0i_dataout <= wire_n01lOlli_dataout WHEN n1101l1i = '1' ELSE wire_n0iOilii_dataout; + wire_niiiOi0l_dataout <= wire_n01lOlll_dataout WHEN n1101l1i = '1' ELSE wire_n0iOilil_dataout; + wire_niiiOi0O_dataout <= wire_n01lOllO_dataout WHEN n1101l1i = '1' ELSE wire_n0iOiliO_dataout; + wire_niiiOi1i_dataout <= wire_n01lOlii_dataout WHEN n1101l1i = '1' ELSE wire_n0iOil0i_dataout; + wire_niiiOi1l_dataout <= wire_n01lOlil_dataout WHEN n1101l1i = '1' ELSE wire_n0iOil0l_dataout; + wire_niiiOi1O_dataout <= wire_n01lOliO_dataout WHEN n1101l1i = '1' ELSE wire_n0iOil0O_dataout; + wire_niiiOiii_dataout <= wire_niO10i1l_dataout WHEN n1101l1i = '1' ELSE wire_niO11O1l_dataout; + wire_niiiOiil_dataout <= wire_n00ii0il_dataout WHEN n1101l1i = '1' ELSE wire_n0i1OOlO_dataout; + wire_niiiOiiO_dataout <= wire_n00ii0iO_dataout WHEN n1101l1i = '1' ELSE wire_n0i1OOOi_dataout; + wire_niiiOili_dataout <= wire_n00ii0li_dataout WHEN n1101l1i = '1' ELSE wire_n0i1OOOl_dataout; + wire_niiiOill_dataout <= wire_n00ii0ll_dataout WHEN n1101l1i = '1' ELSE wire_n0i1OOOO_dataout; + wire_niiiOilO_dataout <= wire_n00ii0lO_dataout WHEN n1101l1i = '1' ELSE wire_n0i0111i_dataout; + wire_niiiOiOi_dataout <= wire_n00ii0Oi_dataout WHEN n1101l1i = '1' ELSE wire_n0i0111l_dataout; + wire_niiiOiOl_dataout <= wire_n00ii0Ol_dataout WHEN n1101l1i = '1' ELSE wire_n0i0111O_dataout; + wire_niiiOiOO_dataout <= wire_n00ii0OO_dataout WHEN n1101l1i = '1' ELSE wire_n0i0110i_dataout; + wire_niiiOl0i_dataout <= wire_n0i1OOOi_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOiO_dataout; + wire_niiiOl0l_dataout <= wire_n0i1OOOl_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOli_dataout; + wire_niiiOl0O_dataout <= wire_n0i1OOOO_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOll_dataout; + wire_niiiOl1i_dataout <= wire_n00iii1i_dataout WHEN n1101l1i = '1' ELSE wire_n0i0110l_dataout; + wire_niiiOl1l_dataout <= wire_niO1001l_dataout WHEN n1101l1i = '1' ELSE wire_niO1011l_dataout; + wire_niiiOl1O_dataout <= wire_n0i1OOlO_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOil_dataout; + wire_niiiOlii_dataout <= wire_n0i0111i_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOlO_dataout; + wire_niiiOlil_dataout <= wire_n0i0111l_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOOi_dataout; + wire_niiiOliO_dataout <= wire_n0i0111O_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOOl_dataout; + wire_niiiOlli_dataout <= wire_n0i0110i_dataout WHEN n1101l1i = '1' ELSE wire_niiiOOOO_dataout; + wire_niiiOlll_dataout <= wire_n0i0110l_dataout WHEN n1101l1i = '1' ELSE wire_niil111i_dataout; + wire_niiiOllO_dataout <= wire_niO1011l_dataout WHEN n1101l1i = '1' ELSE wire_niil111l_dataout; + wire_niiiOlOi_dataout <= wire_n0iOil1i_dataout WHEN n1101l1i = '1' ELSE wire_niil111O_dataout; + wire_niiiOlOl_dataout <= wire_n0iOil1l_dataout WHEN n1101l1i = '1' ELSE wire_niil110i_dataout; + wire_niiiOlOO_dataout <= wire_n0iOil1O_dataout WHEN n1101l1i = '1' ELSE wire_niil110l_dataout; + wire_niiiOO0i_dataout <= wire_n0iOilii_dataout WHEN n1101l1i = '1' ELSE wire_niil11iO_dataout; + wire_niiiOO0l_dataout <= wire_n0iOilil_dataout WHEN n1101l1i = '1' ELSE wire_niil11li_dataout; + wire_niiiOO0O_dataout <= wire_n0iOiliO_dataout WHEN n1101l1i = '1' ELSE wire_niil11ll_dataout; + wire_niiiOO1i_dataout <= wire_n0iOil0i_dataout WHEN n1101l1i = '1' ELSE wire_niil110O_dataout; + wire_niiiOO1l_dataout <= wire_n0iOil0l_dataout WHEN n1101l1i = '1' ELSE wire_niil11ii_dataout; + wire_niiiOO1O_dataout <= wire_n0iOil0O_dataout WHEN n1101l1i = '1' ELSE wire_niil11il_dataout; + wire_niiiOOii_dataout <= wire_niO11O1l_dataout WHEN n1101l1i = '1' ELSE wire_niil11lO_dataout; + wire_niiiOOil_dataout <= wire_n1O0O0ll_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0il_dataout; + wire_niiiOOiO_dataout <= wire_n1O0O0lO_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0iO_dataout; + wire_niiiOOli_dataout <= wire_n1O0O0Oi_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0li_dataout; + wire_niiiOOll_dataout <= wire_n1O0O0Ol_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0ll_dataout; + wire_niiiOOlO_dataout <= wire_n1O0O0OO_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0lO_dataout; + wire_niiiOOOi_dataout <= wire_n1O0Oi1i_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0Oi_dataout; + wire_niiiOOOl_dataout <= wire_n1O0Oi1l_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0Ol_dataout; + wire_niiiOOOO_dataout <= wire_n1O0Oi1O_dataout WHEN n1101iOO = '1' ELSE wire_n00ii0OO_dataout; + wire_niil000i_dataout <= wire_niil00il_dataout OR niOlOOlll; + wire_niil000l_dataout <= wire_niil00iO_dataout AND NOT(niOlOOlll); + wire_niil000O_dataout <= wire_niil00li_dataout AND NOT(niOlOOllO); + wire_niil001i_dataout <= wire_niil000l_dataout OR niOlOOlli; + wire_niil001l_dataout <= wire_niil000O_dataout AND NOT(niOlOOlll); + wire_niil001O_dataout <= wire_niil00ii_dataout AND NOT(niOlOOlll); + wire_niil00i_dataout <= wire_nil001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil00ii_dataout <= wire_niil00ll_dataout OR niOlOOllO; + wire_niil00il_dataout <= wire_niil00lO_dataout AND NOT(niOlOOllO); + wire_niil00iO_dataout <= wire_niil00Oi_dataout AND NOT(niOlOOllO); + wire_niil00l_dataout <= wire_nil000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil00li_dataout <= niil00Ol OR niOlOOlOi; + wire_niil00ll_dataout <= niil010i AND NOT(niOlOOlOi); + wire_niil00lO_dataout <= niil010l AND NOT(niOlOOlOi); + wire_niil00O_dataout <= wire_nil000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil00Oi_dataout <= niil010O AND NOT(niOlOOlOi); + wire_niil01i_dataout <= wire_nil01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil01iO_dataout <= wire_niil01Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_niil01l_dataout <= wire_nil001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil01li_dataout <= wire_niil01Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_niil01ll_dataout <= wire_niil01OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niil01lO_dataout <= wire_niil001i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niil01O_dataout <= wire_nil001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil01Oi_dataout <= wire_niil001l_dataout AND NOT(niOlOOlli); + wire_niil01Ol_dataout <= wire_niil001O_dataout AND NOT(niOlOOlli); + wire_niil01OO_dataout <= wire_niil000i_dataout AND NOT(niOlOOlli); + wire_niil0i0i_dataout <= wire_niO10iOO_dataout WHEN n1101iOl = '1' ELSE wire_niO10lOO_dataout; + wire_niil0i0l_dataout <= wire_w_lg_niOlOOO1l9961w(0) AND NOT(niOlOOlOO); + wire_niil0i0O_dataout <= wire_w_lg_niOlOOO1O9954w(0) OR niOlOOlOO; + wire_niil0i1l_dataout <= wire_niO110OO_dataout WHEN n1101l1i = '1' ELSE wire_niil0i1O_dataout; + wire_niil0i1l_w_lg_w_lg_dataout9952w9953w(0) <= wire_niil0i1l_w_lg_dataout9952w(0) AND niOlOOO0i; + wire_niil0i1l_w_lg_dataout9952w(0) <= NOT wire_niil0i1l_dataout; + wire_niil0i1l_w_lg_w_lg_w_lg_dataout9952w9953w9956w(0) <= wire_niil0i1l_w_lg_w_lg_dataout9952w9953w(0) OR wire_w_lg_w_lg_niOlOOO1O9954w9955w(0); + wire_niil0i1O_dataout <= wire_niO101OO_dataout WHEN n1101iOO = '1' ELSE wire_niil0i0i_dataout; + wire_niil0ii_dataout <= wire_nil000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0iiO_dataout <= wire_n0Ol1lOO_dataout OR niOlOOO1i; + wire_niil0il_dataout <= wire_nil00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0ili_dataout <= wire_n0lOl1ll_dataout OR niOlOOO1i; + wire_niil0ill_dataout <= wire_n0l01iii_dataout OR niOlOOO1i; + wire_niil0ilO_dataout <= wire_n0iiiO1O_dataout OR niOlOOO1i; + wire_niil0iO_dataout <= wire_nil00il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0iOi_dataout <= wire_n00O11Ol_dataout OR niOlOOO1i; + wire_niil0iOl_dataout <= wire_n001iili_dataout OR niOlOOO1i; + wire_niil0l0O_dataout <= wire_n1Oli01l_dataout OR niOlOOO1i; + wire_niil0l1i_dataout <= wire_n010OO0O_dataout OR niOlOOO1i; + wire_niil0li_dataout <= wire_nil00iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0ll_dataout <= wire_nil00li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0lO_dataout <= wire_nil00ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0lOO_dataout <= n0O0Oi0O WHEN n1101l1i = '1' ELSE wire_niil0Oil_dataout; + wire_niil0O0i_dataout <= n0O0Oili WHEN n1101l1i = '1' ELSE wire_niil0OlO_dataout; + wire_niil0O0l_dataout <= n0O0Oill WHEN n1101l1i = '1' ELSE wire_niil0OOi_dataout; + wire_niil0O0O_dataout <= n0O0OilO WHEN n1101l1i = '1' ELSE wire_niil0OOl_dataout; + wire_niil0O1i_dataout <= n0O0Oiii WHEN n1101l1i = '1' ELSE wire_niil0OiO_dataout; + wire_niil0O1l_dataout <= n0O0Oiil WHEN n1101l1i = '1' ELSE wire_niil0Oli_dataout; + wire_niil0O1O_dataout <= n0O0OiiO WHEN n1101l1i = '1' ELSE wire_niil0Oll_dataout; + wire_niil0Oi_dataout <= wire_nil00lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0Oii_dataout <= n0O0OiOi WHEN n1101l1i = '1' ELSE wire_niil0OOO_dataout; + wire_niil0Oil_dataout <= n00ilO0l WHEN n1101iOO = '1' ELSE wire_niili11i_dataout; + wire_niil0OiO_dataout <= n00ilO0O WHEN n1101iOO = '1' ELSE wire_niili11l_dataout; + wire_niil0Ol_dataout <= wire_nil00Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0Oli_dataout <= n00ilOii WHEN n1101iOO = '1' ELSE wire_niili11O_dataout; + wire_niil0Oll_dataout <= n00ilOil WHEN n1101iOO = '1' ELSE wire_niili10i_dataout; + wire_niil0OlO_dataout <= n00ilOiO WHEN n1101iOO = '1' ELSE wire_niili10l_dataout; + wire_niil0OO_dataout <= wire_nil00Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil0OOi_dataout <= n00ilOli WHEN n1101iOO = '1' ELSE wire_niili10O_dataout; + wire_niil0OOl_dataout <= n00ilOll WHEN n1101iOO = '1' ELSE wire_niili1ii_dataout; + wire_niil0OOO_dataout <= n00ilOlO WHEN n1101iOO = '1' ELSE wire_niili1il_dataout; + wire_niil100i_dataout <= wire_n0ll10ll_dataout WHEN n1101l1i = '1' ELSE wire_niil1iiO_dataout; + wire_niil100l_dataout <= wire_n0ll10lO_dataout WHEN n1101l1i = '1' ELSE wire_niil1ili_dataout; + wire_niil100O_dataout <= wire_n0ll10Oi_dataout WHEN n1101l1i = '1' ELSE wire_niil1ill_dataout; + wire_niil101i_dataout <= wire_n0ll10il_dataout WHEN n1101l1i = '1' ELSE wire_niil1i0O_dataout; + wire_niil101l_dataout <= wire_n0ll10iO_dataout WHEN n1101l1i = '1' ELSE wire_niil1iii_dataout; + wire_niil101O_dataout <= wire_n0ll10li_dataout WHEN n1101l1i = '1' ELSE wire_niil1iil_dataout; + wire_niil10i_dataout <= wire_nil011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil10ii_dataout <= wire_niO11l1l_dataout WHEN n1101l1i = '1' ELSE wire_niil1ilO_dataout; + wire_niil10il_dataout <= wire_n0O0iOiO_dataout WHEN n1101l1i = '1' ELSE wire_niil1iOi_dataout; + wire_niil10iO_dataout <= wire_n0O0iOli_dataout WHEN n1101l1i = '1' ELSE wire_niil1iOl_dataout; + wire_niil10l_dataout <= wire_nil010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil10li_dataout <= wire_n0O0iOll_dataout WHEN n1101l1i = '1' ELSE wire_niil1iOO_dataout; + wire_niil10ll_dataout <= wire_n0O0iOlO_dataout WHEN n1101l1i = '1' ELSE wire_niil1l1i_dataout; + wire_niil10lO_dataout <= wire_n0O0iOOi_dataout WHEN n1101l1i = '1' ELSE wire_niil1l1l_dataout; + wire_niil10O_dataout <= wire_nil010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil10Oi_dataout <= wire_n0O0iOOl_dataout WHEN n1101l1i = '1' ELSE wire_niil1l1O_dataout; + wire_niil10Ol_dataout <= wire_n0O0iOOO_dataout WHEN n1101l1i = '1' ELSE wire_niil1l0i_dataout; + wire_niil10OO_dataout <= wire_n0O0l11i_dataout WHEN n1101l1i = '1' ELSE wire_niil1l0l_dataout; + wire_niil110i_dataout <= wire_n011i11i_dataout WHEN n1101iOO = '1' ELSE wire_n01lOl0l_dataout; + wire_niil110l_dataout <= wire_n011i11l_dataout WHEN n1101iOO = '1' ELSE wire_n01lOl0O_dataout; + wire_niil110O_dataout <= wire_n011i11O_dataout WHEN n1101iOO = '1' ELSE wire_n01lOlii_dataout; + wire_niil111i_dataout <= wire_n1O0Oi0i_dataout WHEN n1101iOO = '1' ELSE wire_n00iii1i_dataout; + wire_niil111l_dataout <= wire_niO10O1l_dataout WHEN n1101iOO = '1' ELSE wire_niO1001l_dataout; + wire_niil111O_dataout <= wire_n0110OOO_dataout WHEN n1101iOO = '1' ELSE wire_n01lOl0i_dataout; + wire_niil11i_dataout <= wire_nil1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil11ii_dataout <= wire_n011i10i_dataout WHEN n1101iOO = '1' ELSE wire_n01lOlil_dataout; + wire_niil11il_dataout <= wire_n011i10l_dataout WHEN n1101iOO = '1' ELSE wire_n01lOliO_dataout; + wire_niil11iO_dataout <= wire_n011i10O_dataout WHEN n1101iOO = '1' ELSE wire_n01lOlli_dataout; + wire_niil11l_dataout <= wire_nil011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil11li_dataout <= wire_n011i1ii_dataout WHEN n1101iOO = '1' ELSE wire_n01lOlll_dataout; + wire_niil11ll_dataout <= wire_n011i1il_dataout WHEN n1101iOO = '1' ELSE wire_n01lOllO_dataout; + wire_niil11lO_dataout <= wire_niO10l1l_dataout WHEN n1101iOO = '1' ELSE wire_niO10i1l_dataout; + wire_niil11O_dataout <= wire_nil011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil11Oi_dataout <= wire_n0ll100l_dataout WHEN n1101l1i = '1' ELSE wire_niil1i1O_dataout; + wire_niil11Ol_dataout <= wire_n0ll100O_dataout WHEN n1101l1i = '1' ELSE wire_niil1i0i_dataout; + wire_niil11OO_dataout <= wire_n0ll10ii_dataout WHEN n1101l1i = '1' ELSE wire_niil1i0l_dataout; + wire_niil1i0i_dataout <= wire_n01lOl0l_dataout WHEN n1101iOO = '1' ELSE wire_niil1liO_dataout; + wire_niil1i0l_dataout <= wire_n01lOl0O_dataout WHEN n1101iOO = '1' ELSE wire_niil1lli_dataout; + wire_niil1i0O_dataout <= wire_n01lOlii_dataout WHEN n1101iOO = '1' ELSE wire_niil1lll_dataout; + wire_niil1i1i_dataout <= wire_n0O0l11l_dataout WHEN n1101l1i = '1' ELSE wire_niil1l0O_dataout; + wire_niil1i1l_dataout <= wire_niO11i1l_dataout WHEN n1101l1i = '1' ELSE wire_niil1lii_dataout; + wire_niil1i1O_dataout <= wire_n01lOl0i_dataout WHEN n1101iOO = '1' ELSE wire_niil1lil_dataout; + wire_niil1ii_dataout <= wire_nil010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1iii_dataout <= wire_n01lOlil_dataout WHEN n1101iOO = '1' ELSE wire_niil1llO_dataout; + wire_niil1iil_dataout <= wire_n01lOliO_dataout WHEN n1101iOO = '1' ELSE wire_niil1lOi_dataout; + wire_niil1iiO_dataout <= wire_n01lOlli_dataout WHEN n1101iOO = '1' ELSE wire_niil1lOl_dataout; + wire_niil1il_dataout <= wire_nil01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1ili_dataout <= wire_n01lOlll_dataout WHEN n1101iOO = '1' ELSE wire_niil1lOO_dataout; + wire_niil1ill_dataout <= wire_n01lOllO_dataout WHEN n1101iOO = '1' ELSE wire_niil1O1i_dataout; + wire_niil1ilO_dataout <= wire_niO10i1l_dataout WHEN n1101iOO = '1' ELSE wire_niil1O1l_dataout; + wire_niil1iO_dataout <= wire_nil01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1iOi_dataout <= wire_n00ii0il_dataout WHEN n1101iOO = '1' ELSE wire_niil1O1O_dataout; + wire_niil1iOl_dataout <= wire_n00ii0iO_dataout WHEN n1101iOO = '1' ELSE wire_niil1O0i_dataout; + wire_niil1iOO_dataout <= wire_n00ii0li_dataout WHEN n1101iOO = '1' ELSE wire_niil1O0l_dataout; + wire_niil1l0i_dataout <= wire_n00ii0Ol_dataout WHEN n1101iOO = '1' ELSE wire_niil1OiO_dataout; + wire_niil1l0l_dataout <= wire_n00ii0OO_dataout WHEN n1101iOO = '1' ELSE wire_niil1Oli_dataout; + wire_niil1l0O_dataout <= wire_n00iii1i_dataout WHEN n1101iOO = '1' ELSE wire_niil1Oll_dataout; + wire_niil1l1i_dataout <= wire_n00ii0ll_dataout WHEN n1101iOO = '1' ELSE wire_niil1O0O_dataout; + wire_niil1l1l_dataout <= wire_n00ii0lO_dataout WHEN n1101iOO = '1' ELSE wire_niil1Oii_dataout; + wire_niil1l1O_dataout <= wire_n00ii0Oi_dataout WHEN n1101iOO = '1' ELSE wire_niil1Oil_dataout; + wire_niil1li_dataout <= wire_nil01iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1lii_dataout <= wire_niO1001l_dataout WHEN n1101iOO = '1' ELSE wire_niil1OlO_dataout; + wire_niil1lil_dataout <= wire_n1O0O0ll_dataout WHEN n1101iOl = '1' ELSE wire_n0110OOO_dataout; + wire_niil1liO_dataout <= wire_n1O0O0lO_dataout WHEN n1101iOl = '1' ELSE wire_n011i11i_dataout; + wire_niil1ll_dataout <= wire_nil01li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1lli_dataout <= wire_n1O0O0Oi_dataout WHEN n1101iOl = '1' ELSE wire_n011i11l_dataout; + wire_niil1lll_dataout <= wire_n1O0O0Ol_dataout WHEN n1101iOl = '1' ELSE wire_n011i11O_dataout; + wire_niil1llO_dataout <= wire_n1O0O0OO_dataout WHEN n1101iOl = '1' ELSE wire_n011i10i_dataout; + wire_niil1lO_dataout <= wire_nil01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1lOi_dataout <= wire_n1O0Oi1i_dataout WHEN n1101iOl = '1' ELSE wire_n011i10l_dataout; + wire_niil1lOl_dataout <= wire_n1O0Oi1l_dataout WHEN n1101iOl = '1' ELSE wire_n011i10O_dataout; + wire_niil1lOO_dataout <= wire_n1O0Oi1O_dataout WHEN n1101iOl = '1' ELSE wire_n011i1ii_dataout; + wire_niil1O0i_dataout <= wire_n011i11i_dataout WHEN n1101iOl = '1' ELSE wire_n1O0O0lO_dataout; + wire_niil1O0l_dataout <= wire_n011i11l_dataout WHEN n1101iOl = '1' ELSE wire_n1O0O0Oi_dataout; + wire_niil1O0O_dataout <= wire_n011i11O_dataout WHEN n1101iOl = '1' ELSE wire_n1O0O0Ol_dataout; + wire_niil1O1i_dataout <= wire_n1O0Oi0i_dataout WHEN n1101iOl = '1' ELSE wire_n011i1il_dataout; + wire_niil1O1l_dataout <= wire_niO10O1l_dataout WHEN n1101iOl = '1' ELSE wire_niO10l1l_dataout; + wire_niil1O1O_dataout <= wire_n0110OOO_dataout WHEN n1101iOl = '1' ELSE wire_n1O0O0ll_dataout; + wire_niil1Oi_dataout <= wire_nil01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1Oii_dataout <= wire_n011i10i_dataout WHEN n1101iOl = '1' ELSE wire_n1O0O0OO_dataout; + wire_niil1Oil_dataout <= wire_n011i10l_dataout WHEN n1101iOl = '1' ELSE wire_n1O0Oi1i_dataout; + wire_niil1OiO_dataout <= wire_n011i10O_dataout WHEN n1101iOl = '1' ELSE wire_n1O0Oi1l_dataout; + wire_niil1Ol_dataout <= wire_nil01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niil1Oli_dataout <= wire_n011i1ii_dataout WHEN n1101iOl = '1' ELSE wire_n1O0Oi1O_dataout; + wire_niil1Oll_dataout <= wire_n011i1il_dataout WHEN n1101iOl = '1' ELSE wire_n1O0Oi0i_dataout; + wire_niil1OlO_dataout <= wire_niO10l1l_dataout WHEN n1101iOl = '1' ELSE wire_niO10O1l_dataout; + wire_niil1OO_dataout <= wire_nil01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niili00i_dataout <= n1101iOO OR n1101l1i; + wire_niili00l_dataout <= wire_niO01ill_w_lg_n1101iOl9948w(0) AND NOT(n1101iOO); + wire_niili00O_dataout <= wire_niili0il_dataout OR n1101l1i; + wire_niili01i_dataout <= n1101iOO OR n1101l1i; + wire_niili01l_dataout <= wire_niO01ill_w_lg_n1101iOO9949w(0) AND NOT(n1101l1i); + wire_niili01O_dataout <= wire_niili00l_dataout AND NOT(n1101l1i); + wire_niili0i_dataout <= wire_nil0i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niili0ii_dataout <= n1101iOO OR n1101l1i; + wire_niili0il_dataout <= n1101iOl OR n1101iOO; + wire_niili0iO_dataout <= n0O0O00O WHEN n1101l1i = '1' ELSE wire_niilii1l_dataout; + wire_niili0l_dataout <= wire_nil0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niili0li_dataout <= n0O0O0ii WHEN n1101l1i = '1' ELSE wire_niilii1O_dataout; + wire_niili0ll_dataout <= n0O0O0il WHEN n1101l1i = '1' ELSE wire_niilii0i_dataout; + wire_niili0lO_dataout <= n0O0O0iO WHEN n1101l1i = '1' ELSE wire_niilii0l_dataout; + wire_niili0O_dataout <= wire_nil0i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niili0Oi_dataout <= n0O0O0li WHEN n1101l1i = '1' ELSE wire_niilii0O_dataout; + wire_niili0Ol_dataout <= n0O0O0ll WHEN n1101l1i = '1' ELSE wire_niiliiii_dataout; + wire_niili0OO_dataout <= n0O0O0lO WHEN n1101l1i = '1' ELSE wire_niiliiil_dataout; + wire_niili10i_dataout <= n011liOO WHEN n1101iOl = '1' ELSE n1Oi1Oll; + wire_niili10l_dataout <= n011ll1i WHEN n1101iOl = '1' ELSE n1Oi1OlO; + wire_niili10O_dataout <= n011ll1l WHEN n1101iOl = '1' ELSE n1Oi1OOi; + wire_niili11i_dataout <= n011lilO WHEN n1101iOl = '1' ELSE n1Oi1Oil; + wire_niili11l_dataout <= n011liOi WHEN n1101iOl = '1' ELSE n1Oi1OiO; + wire_niili11O_dataout <= n011liOl WHEN n1101iOl = '1' ELSE n1Oi1Oli; + wire_niili1i_dataout <= wire_nil00OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niili1ii_dataout <= n011ll1O WHEN n1101iOl = '1' ELSE n1Oi1OOl; + wire_niili1il_dataout <= n011ll0i WHEN n1101iOl = '1' ELSE n1Oi1OOO; + wire_niili1l_dataout <= wire_nil0i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niili1O_dataout <= wire_nil0i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niili1Ol_dataout <= wire_niO01ill_w_lg_n1101iOO9949w(0) AND NOT(n1101l1i); + wire_niili1OO_dataout <= wire_niO01ill_w_lg_n1101iOO9949w(0) AND NOT(n1101l1i); + wire_niilii0i_dataout <= n00illii WHEN n1101iOO = '1' ELSE wire_niiliilO_dataout; + wire_niilii0l_dataout <= n00illil WHEN n1101iOO = '1' ELSE wire_niiliiOi_dataout; + wire_niilii0O_dataout <= n00illiO WHEN n1101iOO = '1' ELSE wire_niiliiOl_dataout; + wire_niilii1i_dataout <= n0O0O0Oi WHEN n1101l1i = '1' ELSE wire_niiliiiO_dataout; + wire_niilii1l_dataout <= n00ill0l WHEN n1101iOO = '1' ELSE wire_niiliili_dataout; + wire_niilii1O_dataout <= n00ill0O WHEN n1101iOO = '1' ELSE wire_niiliill_dataout; + wire_niiliii_dataout <= wire_nil0i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiliiii_dataout <= n00illli WHEN n1101iOO = '1' ELSE wire_niiliiOO_dataout; + wire_niiliiil_dataout <= n00illll WHEN n1101iOO = '1' ELSE wire_niilil1i_dataout; + wire_niiliiiO_dataout <= n00illlO WHEN n1101iOO = '1' ELSE wire_niilil1l_dataout; + wire_niiliil_dataout <= wire_nil0iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiliili_dataout <= n011l0lO WHEN n1101iOl = '1' ELSE n1Oi1lil; + wire_niiliill_dataout <= n011l0Oi WHEN n1101iOl = '1' ELSE n1Oi1liO; + wire_niiliilO_dataout <= n011l0Ol WHEN n1101iOl = '1' ELSE n1Oi1lli; + wire_niiliiO_dataout <= wire_nil0iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiliiOi_dataout <= n011l0OO WHEN n1101iOl = '1' ELSE n1Oi1lll; + wire_niiliiOl_dataout <= n011li1i WHEN n1101iOl = '1' ELSE n1Oi1llO; + wire_niiliiOO_dataout <= n011li1l WHEN n1101iOl = '1' ELSE n1Oi1lOi; + wire_niilil1i_dataout <= n011li1O WHEN n1101iOl = '1' ELSE n1Oi1lOl; + wire_niilil1l_dataout <= n011li0i WHEN n1101iOl = '1' ELSE n1Oi1lOO; + wire_niilili_dataout <= wire_nil0iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilill_dataout <= wire_nil0ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_niililO_dataout <= wire_nil0ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiliOi_dataout <= wire_nil0ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiliOl_dataout <= wire_nil0iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiliOO_dataout <= wire_nil0iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niill0i_dataout <= wire_nil0l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niill0l_dataout <= wire_nil0l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niill0O_dataout <= wire_nil0l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niill1i_dataout <= wire_nil0iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niill1l_dataout <= wire_nil0l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niill1O_dataout <= wire_nil0l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niillii_dataout <= wire_nil0l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niillil_dataout <= wire_nil0lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilliO_dataout <= wire_nil0lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilliOl_dataout <= k_conf(200) WHEN niOlOOOii = '1' ELSE wire_niilllii_dataout; + wire_niilliOO_dataout <= k_conf(201) WHEN niOlOOOii = '1' ELSE wire_niilllil_dataout; + wire_niilll0i_dataout <= k_conf(205) WHEN niOlOOOii = '1' ELSE wire_niillllO_dataout; + wire_niilll0l_dataout <= k_conf(206) WHEN niOlOOOii = '1' ELSE wire_niilllOi_dataout; + wire_niilll0O_dataout <= k_conf(207) WHEN niOlOOOii = '1' ELSE wire_niilllOl_dataout; + wire_niilll1i_dataout <= k_conf(202) WHEN niOlOOOii = '1' ELSE wire_niillliO_dataout; + wire_niilll1l_dataout <= k_conf(203) WHEN niOlOOOii = '1' ELSE wire_niilllli_dataout; + wire_niilll1O_dataout <= k_conf(204) WHEN niOlOOOii = '1' ELSE wire_niilllll_dataout; + wire_niillli_dataout <= wire_nil0liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilllii_dataout <= k_conf(192) WHEN niOlOOO0O = '1' ELSE wire_niilllOO_dataout; + wire_niilllil_dataout <= k_conf(193) WHEN niOlOOO0O = '1' ELSE wire_niillO1i_dataout; + wire_niillliO_dataout <= k_conf(194) WHEN niOlOOO0O = '1' ELSE wire_niillO1l_dataout; + wire_niillll_dataout <= wire_nil0lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilllli_dataout <= k_conf(195) WHEN niOlOOO0O = '1' ELSE wire_niillO1O_dataout; + wire_niilllll_dataout <= k_conf(196) WHEN niOlOOO0O = '1' ELSE wire_niillO0i_dataout; + wire_niillllO_dataout <= k_conf(197) WHEN niOlOOO0O = '1' ELSE wire_niillO0l_dataout; + wire_niilllO_dataout <= wire_nil0lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilllOi_dataout <= k_conf(198) WHEN niOlOOO0O = '1' ELSE wire_niillO0O_dataout; + wire_niilllOl_dataout <= k_conf(199) WHEN niOlOOO0O = '1' ELSE wire_niillOii_dataout; + wire_niilllOO_dataout <= k_conf(352) WHEN niOlOOO0l = '1' ELSE k_conf(344); + wire_niillO0i_dataout <= k_conf(356) WHEN niOlOOO0l = '1' ELSE k_conf(348); + wire_niillO0l_dataout <= k_conf(357) WHEN niOlOOO0l = '1' ELSE k_conf(349); + wire_niillO0O_dataout <= k_conf(358) WHEN niOlOOO0l = '1' ELSE k_conf(350); + wire_niillO1i_dataout <= k_conf(353) WHEN niOlOOO0l = '1' ELSE k_conf(345); + wire_niillO1l_dataout <= k_conf(354) WHEN niOlOOO0l = '1' ELSE k_conf(346); + wire_niillO1O_dataout <= k_conf(355) WHEN niOlOOO0l = '1' ELSE k_conf(347); + wire_niillOi_dataout <= wire_nil0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niillOii_dataout <= k_conf(359) WHEN niOlOOO0l = '1' ELSE k_conf(351); + wire_niillOl_dataout <= wire_nil0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niillOll_dataout <= k_cnt(36) AND NOT(niOlOOOil); + wire_niillOlO_dataout <= k_cnt(37) AND NOT(niOlOOOil); + wire_niillOO_dataout <= wire_nil0lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niillOOi_dataout <= k_cnt(38) OR niOlOOOil; + wire_niillOOl_dataout <= k_cnt(39) OR niOlOOOil; + wire_niillOOO_dataout <= k_cnt(40) AND NOT(niOlOOOiO); + wire_niilO00i_dataout <= k_vc7(18) WHEN niOlOOOll = '1' ELSE wire_niilOi1i_dataout; + wire_niilO00l_dataout <= k_vc7(19) WHEN niOlOOOll = '1' ELSE wire_niilOi1l_dataout; + wire_niilO00O_dataout <= k_vc7(28) WHEN niOlOOOlO = '1' ELSE wire_niilOi1O_dataout; + wire_niilO01i_dataout <= k_vc7(15) WHEN niOlOOOll = '1' ELSE wire_niilO0Oi_dataout; + wire_niilO01l_dataout <= k_vc7(16) WHEN niOlOOOll = '1' ELSE wire_niilO0Ol_dataout; + wire_niilO01O_dataout <= k_vc7(17) WHEN niOlOOOll = '1' ELSE wire_niilO0OO_dataout; + wire_niilO0i_dataout <= wire_nil0O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilO0ii_dataout <= k_vc7(29) WHEN niOlOOOlO = '1' ELSE wire_niilOi0i_dataout; + wire_niilO0il_dataout <= k_vc7(30) WHEN niOlOOOlO = '1' ELSE wire_niilOi0l_dataout; + wire_niilO0iO_dataout <= k_vc7(31) WHEN niOlOOOlO = '1' ELSE wire_niilOi0O_dataout; + wire_niilO0l_dataout <= wire_nil0O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilO0li_dataout <= k_vc7(32) WHEN niOlOOOlO = '1' ELSE wire_niilOiii_dataout; + wire_niilO0ll_dataout <= k_vc7(33) WHEN niOlOOOlO = '1' ELSE wire_niilOiil_dataout; + wire_niilO0lO_dataout <= k_vc7(34) WHEN niOlOOOlO = '1' ELSE wire_niilOiiO_dataout; + wire_niilO0O_dataout <= wire_nil0O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilO0Oi_dataout <= k_vc7(35) WHEN niOlOOOlO = '1' ELSE wire_niilOili_dataout; + wire_niilO0Ol_dataout <= wire_niilOill_dataout AND NOT(niOlOOOlO); + wire_niilO0OO_dataout <= wire_niilOilO_dataout AND NOT(niOlOOOlO); + wire_niilO10i_dataout <= k_cnt(53) OR niOlOOOli; + wire_niilO10l_dataout <= k_cnt(54) OR niOlOOOli; + wire_niilO10O_dataout <= k_cnt(55) AND NOT(niOlOOOli); + wire_niilO11i_dataout <= k_cnt(41) AND NOT(niOlOOOiO); + wire_niilO11l_dataout <= k_cnt(42) OR niOlOOOiO; + wire_niilO11O_dataout <= k_cnt(43) OR niOlOOOiO; + wire_niilO1i_dataout <= wire_nil0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilO1ii_dataout <= k_cnt(56) OR niOlOOOli; + wire_niilO1iO_dataout <= k_vc7(8) WHEN niOlOOOll = '1' ELSE wire_niilO00O_dataout; + wire_niilO1l_dataout <= wire_nil0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilO1li_dataout <= k_vc7(9) WHEN niOlOOOll = '1' ELSE wire_niilO0ii_dataout; + wire_niilO1ll_dataout <= k_vc7(10) WHEN niOlOOOll = '1' ELSE wire_niilO0il_dataout; + wire_niilO1lO_dataout <= k_vc7(11) WHEN niOlOOOll = '1' ELSE wire_niilO0iO_dataout; + wire_niilO1O_dataout <= wire_nil0O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilO1Oi_dataout <= k_vc7(12) WHEN niOlOOOll = '1' ELSE wire_niilO0li_dataout; + wire_niilO1Ol_dataout <= k_vc7(13) WHEN niOlOOOll = '1' ELSE wire_niilO0ll_dataout; + wire_niilO1OO_dataout <= k_vc7(14) WHEN niOlOOOll = '1' ELSE wire_niilO0lO_dataout; + wire_niilOi0i_dataout <= k_vc7(45) WHEN niOlOOOOi = '1' ELSE wire_niilOl1i_dataout; + wire_niilOi0l_dataout <= k_vc7(46) WHEN niOlOOOOi = '1' ELSE wire_niilOl1l_dataout; + wire_niilOi0O_dataout <= k_vc7(47) WHEN niOlOOOOi = '1' ELSE wire_niilOl1O_dataout; + wire_niilOi1i_dataout <= wire_niilOiOi_dataout AND NOT(niOlOOOlO); + wire_niilOi1l_dataout <= wire_niilOiOl_dataout AND NOT(niOlOOOlO); + wire_niilOi1O_dataout <= k_vc7(44) WHEN niOlOOOOi = '1' ELSE wire_niilOiOO_dataout; + wire_niilOii_dataout <= wire_nil0O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOiii_dataout <= k_vc7(48) WHEN niOlOOOOi = '1' ELSE wire_niilOl0i_dataout; + wire_niilOiil_dataout <= k_vc7(49) WHEN niOlOOOOi = '1' ELSE wire_niilOl0l_dataout; + wire_niilOiiO_dataout <= k_vc7(50) WHEN niOlOOOOi = '1' ELSE wire_niilOl0O_dataout; + wire_niilOil_dataout <= wire_nil0Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOili_dataout <= k_vc7(51) WHEN niOlOOOOi = '1' ELSE wire_niilOlii_dataout; + wire_niilOill_dataout <= k_vc7(52) WHEN niOlOOOOi = '1' ELSE wire_niilOlil_dataout; + wire_niilOilO_dataout <= k_vc7(53) WHEN niOlOOOOi = '1' ELSE wire_niilOliO_dataout; + wire_niilOiO_dataout <= wire_nil0Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOiOi_dataout <= k_vc7(54) WHEN niOlOOOOi = '1' ELSE wire_niilOlli_dataout; + wire_niilOiOl_dataout <= k_vc7(55) WHEN niOlOOOOi = '1' ELSE wire_niilOlll_dataout; + wire_niilOiOO_dataout <= k_vc6(8) WHEN niOlOOOOl = '1' ELSE wire_niilOllO_dataout; + wire_niilOl0i_dataout <= k_vc6(12) WHEN niOlOOOOl = '1' ELSE wire_niilOO1i_dataout; + wire_niilOl0l_dataout <= k_vc6(13) WHEN niOlOOOOl = '1' ELSE wire_niilOO1l_dataout; + wire_niilOl0O_dataout <= k_vc6(14) WHEN niOlOOOOl = '1' ELSE wire_niilOO1O_dataout; + wire_niilOl1i_dataout <= k_vc6(9) WHEN niOlOOOOl = '1' ELSE wire_niilOlOi_dataout; + wire_niilOl1l_dataout <= k_vc6(10) WHEN niOlOOOOl = '1' ELSE wire_niilOlOl_dataout; + wire_niilOl1O_dataout <= k_vc6(11) WHEN niOlOOOOl = '1' ELSE wire_niilOlOO_dataout; + wire_niilOli_dataout <= wire_nil0OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOlii_dataout <= k_vc6(15) WHEN niOlOOOOl = '1' ELSE wire_niilOO0i_dataout; + wire_niilOlil_dataout <= k_vc6(16) WHEN niOlOOOOl = '1' ELSE wire_niilOO0l_dataout; + wire_niilOliO_dataout <= k_vc6(17) WHEN niOlOOOOl = '1' ELSE wire_niilOO0O_dataout; + wire_niilOll_dataout <= wire_nil0Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOlli_dataout <= k_vc6(18) WHEN niOlOOOOl = '1' ELSE wire_niilOOii_dataout; + wire_niilOlll_dataout <= k_vc6(19) WHEN niOlOOOOl = '1' ELSE wire_niilOOil_dataout; + wire_niilOllO_dataout <= k_vc6(28) WHEN niOlOOOOO = '1' ELSE wire_niilOOiO_dataout; + wire_niilOlO_dataout <= wire_nil0Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOlOi_dataout <= k_vc6(29) WHEN niOlOOOOO = '1' ELSE wire_niilOOli_dataout; + wire_niilOlOl_dataout <= k_vc6(30) WHEN niOlOOOOO = '1' ELSE wire_niilOOll_dataout; + wire_niilOlOO_dataout <= k_vc6(31) WHEN niOlOOOOO = '1' ELSE wire_niilOOlO_dataout; + wire_niilOO0i_dataout <= k_vc6(35) WHEN niOlOOOOO = '1' ELSE wire_niiO111i_dataout; + wire_niilOO0l_dataout <= wire_niiO111l_dataout AND NOT(niOlOOOOO); + wire_niilOO0O_dataout <= wire_niiO111O_dataout AND NOT(niOlOOOOO); + wire_niilOO1i_dataout <= k_vc6(32) WHEN niOlOOOOO = '1' ELSE wire_niilOOOi_dataout; + wire_niilOO1l_dataout <= k_vc6(33) WHEN niOlOOOOO = '1' ELSE wire_niilOOOl_dataout; + wire_niilOO1O_dataout <= k_vc6(34) WHEN niOlOOOOO = '1' ELSE wire_niilOOOO_dataout; + wire_niilOOi_dataout <= wire_nil0OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOOii_dataout <= wire_niiO110i_dataout AND NOT(niOlOOOOO); + wire_niilOOil_dataout <= wire_niiO110l_dataout AND NOT(niOlOOOOO); + wire_niilOOiO_dataout <= k_vc6(44) WHEN niOO1111i = '1' ELSE wire_niiO110O_dataout; + wire_niilOOl_dataout <= wire_nil0OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOOli_dataout <= k_vc6(45) WHEN niOO1111i = '1' ELSE wire_niiO11ii_dataout; + wire_niilOOll_dataout <= k_vc6(46) WHEN niOO1111i = '1' ELSE wire_niiO11il_dataout; + wire_niilOOlO_dataout <= k_vc6(47) WHEN niOO1111i = '1' ELSE wire_niiO11iO_dataout; + wire_niilOOO_dataout <= wire_nil0OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niilOOOi_dataout <= k_vc6(48) WHEN niOO1111i = '1' ELSE wire_niiO11li_dataout; + wire_niilOOOl_dataout <= k_vc6(49) WHEN niOO1111i = '1' ELSE wire_niiO11ll_dataout; + wire_niilOOOO_dataout <= k_vc6(50) WHEN niOO1111i = '1' ELSE wire_niiO11lO_dataout; + wire_niiO000i_dataout <= k_vc3(32) WHEN niOO111iO = '1' ELSE wire_niiO0i1i_dataout; + wire_niiO000l_dataout <= k_vc3(33) WHEN niOO111iO = '1' ELSE wire_niiO0i1l_dataout; + wire_niiO000O_dataout <= k_vc3(34) WHEN niOO111iO = '1' ELSE wire_niiO0i1O_dataout; + wire_niiO001i_dataout <= k_vc3(29) WHEN niOO111iO = '1' ELSE wire_niiO00Oi_dataout; + wire_niiO001l_dataout <= k_vc3(30) WHEN niOO111iO = '1' ELSE wire_niiO00Ol_dataout; + wire_niiO001O_dataout <= k_vc3(31) WHEN niOO111iO = '1' ELSE wire_niiO00OO_dataout; + wire_niiO00i_dataout <= wire_nili01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO00ii_dataout <= k_vc3(35) WHEN niOO111iO = '1' ELSE wire_niiO0i0i_dataout; + wire_niiO00il_dataout <= wire_niiO0i0l_dataout AND NOT(niOO111iO); + wire_niiO00iO_dataout <= wire_niiO0i0O_dataout AND NOT(niOO111iO); + wire_niiO00l_dataout <= wire_nili00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO00li_dataout <= wire_niiO0iii_dataout AND NOT(niOO111iO); + wire_niiO00ll_dataout <= wire_niiO0iil_dataout AND NOT(niOO111iO); + wire_niiO00lO_dataout <= k_vc3(44) WHEN niOO111li = '1' ELSE wire_niiO0iiO_dataout; + wire_niiO00O_dataout <= wire_nili00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO00Oi_dataout <= k_vc3(45) WHEN niOO111li = '1' ELSE wire_niiO0ili_dataout; + wire_niiO00Ol_dataout <= k_vc3(46) WHEN niOO111li = '1' ELSE wire_niiO0ill_dataout; + wire_niiO00OO_dataout <= k_vc3(47) WHEN niOO111li = '1' ELSE wire_niiO0ilO_dataout; + wire_niiO010i_dataout <= k_vc3(9) WHEN niOO111il = '1' ELSE wire_niiO001i_dataout; + wire_niiO010l_dataout <= k_vc3(10) WHEN niOO111il = '1' ELSE wire_niiO001l_dataout; + wire_niiO010O_dataout <= k_vc3(11) WHEN niOO111il = '1' ELSE wire_niiO001O_dataout; + wire_niiO011i_dataout <= k_vc4(54) WHEN niOO111ii = '1' ELSE wire_niiO01Oi_dataout; + wire_niiO011l_dataout <= k_vc4(55) WHEN niOO111ii = '1' ELSE wire_niiO01Ol_dataout; + wire_niiO011O_dataout <= k_vc3(8) WHEN niOO111il = '1' ELSE wire_niiO01OO_dataout; + wire_niiO01i_dataout <= wire_nili1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO01ii_dataout <= k_vc3(12) WHEN niOO111il = '1' ELSE wire_niiO000i_dataout; + wire_niiO01il_dataout <= k_vc3(13) WHEN niOO111il = '1' ELSE wire_niiO000l_dataout; + wire_niiO01iO_dataout <= k_vc3(14) WHEN niOO111il = '1' ELSE wire_niiO000O_dataout; + wire_niiO01l_dataout <= wire_nili01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO01li_dataout <= k_vc3(15) WHEN niOO111il = '1' ELSE wire_niiO00ii_dataout; + wire_niiO01ll_dataout <= k_vc3(16) WHEN niOO111il = '1' ELSE wire_niiO00il_dataout; + wire_niiO01lO_dataout <= k_vc3(17) WHEN niOO111il = '1' ELSE wire_niiO00iO_dataout; + wire_niiO01O_dataout <= wire_nili01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO01Oi_dataout <= k_vc3(18) WHEN niOO111il = '1' ELSE wire_niiO00li_dataout; + wire_niiO01Ol_dataout <= k_vc3(19) WHEN niOO111il = '1' ELSE wire_niiO00ll_dataout; + wire_niiO01OO_dataout <= k_vc3(28) WHEN niOO111iO = '1' ELSE wire_niiO00lO_dataout; + wire_niiO0i0i_dataout <= k_vc3(51) WHEN niOO111li = '1' ELSE wire_niiO0l1i_dataout; + wire_niiO0i0l_dataout <= k_vc3(52) WHEN niOO111li = '1' ELSE wire_niiO0l1l_dataout; + wire_niiO0i0O_dataout <= k_vc3(53) WHEN niOO111li = '1' ELSE wire_niiO0l1O_dataout; + wire_niiO0i1i_dataout <= k_vc3(48) WHEN niOO111li = '1' ELSE wire_niiO0iOi_dataout; + wire_niiO0i1l_dataout <= k_vc3(49) WHEN niOO111li = '1' ELSE wire_niiO0iOl_dataout; + wire_niiO0i1O_dataout <= k_vc3(50) WHEN niOO111li = '1' ELSE wire_niiO0iOO_dataout; + wire_niiO0ii_dataout <= wire_nili00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0iii_dataout <= k_vc3(54) WHEN niOO111li = '1' ELSE wire_niiO0l0i_dataout; + wire_niiO0iil_dataout <= k_vc3(55) WHEN niOO111li = '1' ELSE wire_niiO0l0l_dataout; + wire_niiO0iiO_dataout <= k_vc2(8) WHEN niOO111ll = '1' ELSE wire_niiO0l0O_dataout; + wire_niiO0il_dataout <= wire_nili0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0ili_dataout <= k_vc2(9) WHEN niOO111ll = '1' ELSE wire_niiO0lii_dataout; + wire_niiO0ill_dataout <= k_vc2(10) WHEN niOO111ll = '1' ELSE wire_niiO0lil_dataout; + wire_niiO0ilO_dataout <= k_vc2(11) WHEN niOO111ll = '1' ELSE wire_niiO0liO_dataout; + wire_niiO0iO_dataout <= wire_nili0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0iOi_dataout <= k_vc2(12) WHEN niOO111ll = '1' ELSE wire_niiO0lli_dataout; + wire_niiO0iOl_dataout <= k_vc2(13) WHEN niOO111ll = '1' ELSE wire_niiO0lll_dataout; + wire_niiO0iOO_dataout <= k_vc2(14) WHEN niOO111ll = '1' ELSE wire_niiO0llO_dataout; + wire_niiO0l0i_dataout <= k_vc2(18) WHEN niOO111ll = '1' ELSE wire_niiO0O1i_dataout; + wire_niiO0l0l_dataout <= k_vc2(19) WHEN niOO111ll = '1' ELSE wire_niiO0O1l_dataout; + wire_niiO0l0O_dataout <= k_vc2(28) WHEN niOO111lO = '1' ELSE wire_niiO0O1O_dataout; + wire_niiO0l1i_dataout <= k_vc2(15) WHEN niOO111ll = '1' ELSE wire_niiO0lOi_dataout; + wire_niiO0l1l_dataout <= k_vc2(16) WHEN niOO111ll = '1' ELSE wire_niiO0lOl_dataout; + wire_niiO0l1O_dataout <= k_vc2(17) WHEN niOO111ll = '1' ELSE wire_niiO0lOO_dataout; + wire_niiO0li_dataout <= wire_nili0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0lii_dataout <= k_vc2(29) WHEN niOO111lO = '1' ELSE wire_niiO0O0i_dataout; + wire_niiO0lil_dataout <= k_vc2(30) WHEN niOO111lO = '1' ELSE wire_niiO0O0l_dataout; + wire_niiO0liO_dataout <= k_vc2(31) WHEN niOO111lO = '1' ELSE wire_niiO0O0O_dataout; + wire_niiO0ll_dataout <= wire_nili0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0lli_dataout <= k_vc2(32) WHEN niOO111lO = '1' ELSE wire_niiO0Oii_dataout; + wire_niiO0lll_dataout <= k_vc2(33) WHEN niOO111lO = '1' ELSE wire_niiO0Oil_dataout; + wire_niiO0llO_dataout <= k_vc2(34) WHEN niOO111lO = '1' ELSE wire_niiO0OiO_dataout; + wire_niiO0lO_dataout <= wire_nili0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0lOi_dataout <= k_vc2(35) WHEN niOO111lO = '1' ELSE wire_niiO0Oli_dataout; + wire_niiO0lOl_dataout <= wire_niiO0Oll_dataout AND NOT(niOO111lO); + wire_niiO0lOO_dataout <= wire_niiO0OlO_dataout AND NOT(niOO111lO); + wire_niiO0O0i_dataout <= k_vc2(45) WHEN niOO111Oi = '1' ELSE wire_niiOi11i_dataout; + wire_niiO0O0l_dataout <= k_vc2(46) WHEN niOO111Oi = '1' ELSE wire_niiOi11l_dataout; + wire_niiO0O0O_dataout <= k_vc2(47) WHEN niOO111Oi = '1' ELSE wire_niiOi11O_dataout; + wire_niiO0O1i_dataout <= wire_niiO0OOi_dataout AND NOT(niOO111lO); + wire_niiO0O1l_dataout <= wire_niiO0OOl_dataout AND NOT(niOO111lO); + wire_niiO0O1O_dataout <= k_vc2(44) WHEN niOO111Oi = '1' ELSE wire_niiO0OOO_dataout; + wire_niiO0Oi_dataout <= wire_nili0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0Oii_dataout <= k_vc2(48) WHEN niOO111Oi = '1' ELSE wire_niiOi10i_dataout; + wire_niiO0Oil_dataout <= k_vc2(49) WHEN niOO111Oi = '1' ELSE wire_niiOi10l_dataout; + wire_niiO0OiO_dataout <= k_vc2(50) WHEN niOO111Oi = '1' ELSE wire_niiOi10O_dataout; + wire_niiO0Ol_dataout <= wire_nili0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0Oli_dataout <= k_vc2(51) WHEN niOO111Oi = '1' ELSE wire_niiOi1ii_dataout; + wire_niiO0Oll_dataout <= k_vc2(52) WHEN niOO111Oi = '1' ELSE wire_niiOi1il_dataout; + wire_niiO0OlO_dataout <= k_vc2(53) WHEN niOO111Oi = '1' ELSE wire_niiOi1iO_dataout; + wire_niiO0OO_dataout <= wire_nili0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO0OOi_dataout <= k_vc2(54) WHEN niOO111Oi = '1' ELSE wire_niiOi1li_dataout; + wire_niiO0OOl_dataout <= k_vc2(55) WHEN niOO111Oi = '1' ELSE wire_niiOi1ll_dataout; + wire_niiO0OOO_dataout <= k_vc1(8) WHEN niOO111Ol = '1' ELSE wire_niiOi1lO_dataout; + wire_niiO100i_dataout <= k_vc5(29) WHEN niOO1111O = '1' ELSE wire_niiO1i1i_dataout; + wire_niiO100l_dataout <= k_vc5(30) WHEN niOO1111O = '1' ELSE wire_niiO1i1l_dataout; + wire_niiO100O_dataout <= k_vc5(31) WHEN niOO1111O = '1' ELSE wire_niiO1i1O_dataout; + wire_niiO101i_dataout <= k_vc5(18) WHEN niOO1111l = '1' ELSE wire_niiO10Oi_dataout; + wire_niiO101l_dataout <= k_vc5(19) WHEN niOO1111l = '1' ELSE wire_niiO10Ol_dataout; + wire_niiO101O_dataout <= k_vc5(28) WHEN niOO1111O = '1' ELSE wire_niiO10OO_dataout; + wire_niiO10i_dataout <= wire_nili11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO10ii_dataout <= k_vc5(32) WHEN niOO1111O = '1' ELSE wire_niiO1i0i_dataout; + wire_niiO10il_dataout <= k_vc5(33) WHEN niOO1111O = '1' ELSE wire_niiO1i0l_dataout; + wire_niiO10iO_dataout <= k_vc5(34) WHEN niOO1111O = '1' ELSE wire_niiO1i0O_dataout; + wire_niiO10l_dataout <= wire_nili10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO10li_dataout <= k_vc5(35) WHEN niOO1111O = '1' ELSE wire_niiO1iii_dataout; + wire_niiO10ll_dataout <= wire_niiO1iil_dataout AND NOT(niOO1111O); + wire_niiO10lO_dataout <= wire_niiO1iiO_dataout AND NOT(niOO1111O); + wire_niiO10O_dataout <= wire_nili10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO10Oi_dataout <= wire_niiO1ili_dataout AND NOT(niOO1111O); + wire_niiO10Ol_dataout <= wire_niiO1ill_dataout AND NOT(niOO1111O); + wire_niiO10OO_dataout <= k_vc5(44) WHEN niOO1110i = '1' ELSE wire_niiO1ilO_dataout; + wire_niiO110i_dataout <= k_vc6(54) WHEN niOO1111i = '1' ELSE wire_niiO101i_dataout; + wire_niiO110l_dataout <= k_vc6(55) WHEN niOO1111i = '1' ELSE wire_niiO101l_dataout; + wire_niiO110O_dataout <= k_vc5(8) WHEN niOO1111l = '1' ELSE wire_niiO101O_dataout; + wire_niiO111i_dataout <= k_vc6(51) WHEN niOO1111i = '1' ELSE wire_niiO11Oi_dataout; + wire_niiO111l_dataout <= k_vc6(52) WHEN niOO1111i = '1' ELSE wire_niiO11Ol_dataout; + wire_niiO111O_dataout <= k_vc6(53) WHEN niOO1111i = '1' ELSE wire_niiO11OO_dataout; + wire_niiO11i_dataout <= wire_nil0OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO11ii_dataout <= k_vc5(9) WHEN niOO1111l = '1' ELSE wire_niiO100i_dataout; + wire_niiO11il_dataout <= k_vc5(10) WHEN niOO1111l = '1' ELSE wire_niiO100l_dataout; + wire_niiO11iO_dataout <= k_vc5(11) WHEN niOO1111l = '1' ELSE wire_niiO100O_dataout; + wire_niiO11l_dataout <= wire_nili11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO11li_dataout <= k_vc5(12) WHEN niOO1111l = '1' ELSE wire_niiO10ii_dataout; + wire_niiO11ll_dataout <= k_vc5(13) WHEN niOO1111l = '1' ELSE wire_niiO10il_dataout; + wire_niiO11lO_dataout <= k_vc5(14) WHEN niOO1111l = '1' ELSE wire_niiO10iO_dataout; + wire_niiO11O_dataout <= wire_nili11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO11Oi_dataout <= k_vc5(15) WHEN niOO1111l = '1' ELSE wire_niiO10li_dataout; + wire_niiO11Ol_dataout <= k_vc5(16) WHEN niOO1111l = '1' ELSE wire_niiO10ll_dataout; + wire_niiO11OO_dataout <= k_vc5(17) WHEN niOO1111l = '1' ELSE wire_niiO10lO_dataout; + wire_niiO1i0i_dataout <= k_vc5(48) WHEN niOO1110i = '1' ELSE wire_niiO1l1i_dataout; + wire_niiO1i0l_dataout <= k_vc5(49) WHEN niOO1110i = '1' ELSE wire_niiO1l1l_dataout; + wire_niiO1i0O_dataout <= k_vc5(50) WHEN niOO1110i = '1' ELSE wire_niiO1l1O_dataout; + wire_niiO1i1i_dataout <= k_vc5(45) WHEN niOO1110i = '1' ELSE wire_niiO1iOi_dataout; + wire_niiO1i1l_dataout <= k_vc5(46) WHEN niOO1110i = '1' ELSE wire_niiO1iOl_dataout; + wire_niiO1i1O_dataout <= k_vc5(47) WHEN niOO1110i = '1' ELSE wire_niiO1iOO_dataout; + wire_niiO1ii_dataout <= wire_nili10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1iii_dataout <= k_vc5(51) WHEN niOO1110i = '1' ELSE wire_niiO1l0i_dataout; + wire_niiO1iil_dataout <= k_vc5(52) WHEN niOO1110i = '1' ELSE wire_niiO1l0l_dataout; + wire_niiO1iiO_dataout <= k_vc5(53) WHEN niOO1110i = '1' ELSE wire_niiO1l0O_dataout; + wire_niiO1il_dataout <= wire_nili1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1ili_dataout <= k_vc5(54) WHEN niOO1110i = '1' ELSE wire_niiO1lii_dataout; + wire_niiO1ill_dataout <= k_vc5(55) WHEN niOO1110i = '1' ELSE wire_niiO1lil_dataout; + wire_niiO1ilO_dataout <= k_vc4(8) WHEN niOO1110l = '1' ELSE wire_niiO1liO_dataout; + wire_niiO1iO_dataout <= wire_nili1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1iOi_dataout <= k_vc4(9) WHEN niOO1110l = '1' ELSE wire_niiO1lli_dataout; + wire_niiO1iOl_dataout <= k_vc4(10) WHEN niOO1110l = '1' ELSE wire_niiO1lll_dataout; + wire_niiO1iOO_dataout <= k_vc4(11) WHEN niOO1110l = '1' ELSE wire_niiO1llO_dataout; + wire_niiO1l0i_dataout <= k_vc4(15) WHEN niOO1110l = '1' ELSE wire_niiO1O1i_dataout; + wire_niiO1l0l_dataout <= k_vc4(16) WHEN niOO1110l = '1' ELSE wire_niiO1O1l_dataout; + wire_niiO1l0O_dataout <= k_vc4(17) WHEN niOO1110l = '1' ELSE wire_niiO1O1O_dataout; + wire_niiO1l1i_dataout <= k_vc4(12) WHEN niOO1110l = '1' ELSE wire_niiO1lOi_dataout; + wire_niiO1l1l_dataout <= k_vc4(13) WHEN niOO1110l = '1' ELSE wire_niiO1lOl_dataout; + wire_niiO1l1O_dataout <= k_vc4(14) WHEN niOO1110l = '1' ELSE wire_niiO1lOO_dataout; + wire_niiO1li_dataout <= wire_nili1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1lii_dataout <= k_vc4(18) WHEN niOO1110l = '1' ELSE wire_niiO1O0i_dataout; + wire_niiO1lil_dataout <= k_vc4(19) WHEN niOO1110l = '1' ELSE wire_niiO1O0l_dataout; + wire_niiO1liO_dataout <= k_vc4(28) WHEN niOO1110O = '1' ELSE wire_niiO1O0O_dataout; + wire_niiO1ll_dataout <= wire_nili1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1lli_dataout <= k_vc4(29) WHEN niOO1110O = '1' ELSE wire_niiO1Oii_dataout; + wire_niiO1lll_dataout <= k_vc4(30) WHEN niOO1110O = '1' ELSE wire_niiO1Oil_dataout; + wire_niiO1llO_dataout <= k_vc4(31) WHEN niOO1110O = '1' ELSE wire_niiO1OiO_dataout; + wire_niiO1lO_dataout <= wire_nili1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1lOi_dataout <= k_vc4(32) WHEN niOO1110O = '1' ELSE wire_niiO1Oli_dataout; + wire_niiO1lOl_dataout <= k_vc4(33) WHEN niOO1110O = '1' ELSE wire_niiO1Oll_dataout; + wire_niiO1lOO_dataout <= k_vc4(34) WHEN niOO1110O = '1' ELSE wire_niiO1OlO_dataout; + wire_niiO1O0i_dataout <= wire_niiO011i_dataout AND NOT(niOO1110O); + wire_niiO1O0l_dataout <= wire_niiO011l_dataout AND NOT(niOO1110O); + wire_niiO1O0O_dataout <= k_vc4(44) WHEN niOO111ii = '1' ELSE wire_niiO011O_dataout; + wire_niiO1O1i_dataout <= k_vc4(35) WHEN niOO1110O = '1' ELSE wire_niiO1OOi_dataout; + wire_niiO1O1l_dataout <= wire_niiO1OOl_dataout AND NOT(niOO1110O); + wire_niiO1O1O_dataout <= wire_niiO1OOO_dataout AND NOT(niOO1110O); + wire_niiO1Oi_dataout <= wire_nili1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1Oii_dataout <= k_vc4(45) WHEN niOO111ii = '1' ELSE wire_niiO010i_dataout; + wire_niiO1Oil_dataout <= k_vc4(46) WHEN niOO111ii = '1' ELSE wire_niiO010l_dataout; + wire_niiO1OiO_dataout <= k_vc4(47) WHEN niOO111ii = '1' ELSE wire_niiO010O_dataout; + wire_niiO1Ol_dataout <= wire_nili1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1Oli_dataout <= k_vc4(48) WHEN niOO111ii = '1' ELSE wire_niiO01ii_dataout; + wire_niiO1Oll_dataout <= k_vc4(49) WHEN niOO111ii = '1' ELSE wire_niiO01il_dataout; + wire_niiO1OlO_dataout <= k_vc4(50) WHEN niOO111ii = '1' ELSE wire_niiO01iO_dataout; + wire_niiO1OO_dataout <= wire_nili1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiO1OOi_dataout <= k_vc4(51) WHEN niOO111ii = '1' ELSE wire_niiO01li_dataout; + wire_niiO1OOl_dataout <= k_vc4(52) WHEN niOO111ii = '1' ELSE wire_niiO01ll_dataout; + wire_niiO1OOO_dataout <= k_vc4(53) WHEN niOO111ii = '1' ELSE wire_niiO01lO_dataout; + wire_niiOi00i_dataout <= k_vc1(35) WHEN niOO111OO = '1' ELSE wire_niiOii1i_dataout; + wire_niiOi00l_dataout <= wire_niiOii1l_dataout AND NOT(niOO111OO); + wire_niiOi00O_dataout <= wire_niiOii1O_dataout AND NOT(niOO111OO); + wire_niiOi01i_dataout <= k_vc1(32) WHEN niOO111OO = '1' ELSE wire_niiOi0Oi_dataout; + wire_niiOi01l_dataout <= k_vc1(33) WHEN niOO111OO = '1' ELSE wire_niiOi0Ol_dataout; + wire_niiOi01O_dataout <= k_vc1(34) WHEN niOO111OO = '1' ELSE wire_niiOi0OO_dataout; + wire_niiOi0i_dataout <= wire_nilii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOi0ii_dataout <= wire_niiOii0i_dataout AND NOT(niOO111OO); + wire_niiOi0il_dataout <= wire_niiOii0l_dataout AND NOT(niOO111OO); + wire_niiOi0iO_dataout <= k_vc1(44) WHEN niOO1101i = '1' ELSE wire_niiOii0O_dataout; + wire_niiOi0l_dataout <= wire_nilii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOi0li_dataout <= k_vc1(45) WHEN niOO1101i = '1' ELSE wire_niiOiiii_dataout; + wire_niiOi0ll_dataout <= k_vc1(46) WHEN niOO1101i = '1' ELSE wire_niiOiiil_dataout; + wire_niiOi0lO_dataout <= k_vc1(47) WHEN niOO1101i = '1' ELSE wire_niiOiiiO_dataout; + wire_niiOi0O_dataout <= wire_nilii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOi0Oi_dataout <= k_vc1(48) WHEN niOO1101i = '1' ELSE wire_niiOiili_dataout; + wire_niiOi0Ol_dataout <= k_vc1(49) WHEN niOO1101i = '1' ELSE wire_niiOiill_dataout; + wire_niiOi0OO_dataout <= k_vc1(50) WHEN niOO1101i = '1' ELSE wire_niiOiilO_dataout; + wire_niiOi10i_dataout <= k_vc1(12) WHEN niOO111Ol = '1' ELSE wire_niiOi01i_dataout; + wire_niiOi10l_dataout <= k_vc1(13) WHEN niOO111Ol = '1' ELSE wire_niiOi01l_dataout; + wire_niiOi10O_dataout <= k_vc1(14) WHEN niOO111Ol = '1' ELSE wire_niiOi01O_dataout; + wire_niiOi11i_dataout <= k_vc1(9) WHEN niOO111Ol = '1' ELSE wire_niiOi1Oi_dataout; + wire_niiOi11l_dataout <= k_vc1(10) WHEN niOO111Ol = '1' ELSE wire_niiOi1Ol_dataout; + wire_niiOi11O_dataout <= k_vc1(11) WHEN niOO111Ol = '1' ELSE wire_niiOi1OO_dataout; + wire_niiOi1i_dataout <= wire_nili0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOi1ii_dataout <= k_vc1(15) WHEN niOO111Ol = '1' ELSE wire_niiOi00i_dataout; + wire_niiOi1il_dataout <= k_vc1(16) WHEN niOO111Ol = '1' ELSE wire_niiOi00l_dataout; + wire_niiOi1iO_dataout <= k_vc1(17) WHEN niOO111Ol = '1' ELSE wire_niiOi00O_dataout; + wire_niiOi1l_dataout <= wire_nilii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOi1li_dataout <= k_vc1(18) WHEN niOO111Ol = '1' ELSE wire_niiOi0ii_dataout; + wire_niiOi1ll_dataout <= k_vc1(19) WHEN niOO111Ol = '1' ELSE wire_niiOi0il_dataout; + wire_niiOi1lO_dataout <= k_vc1(28) WHEN niOO111OO = '1' ELSE wire_niiOi0iO_dataout; + wire_niiOi1O_dataout <= wire_nilii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOi1Oi_dataout <= k_vc1(29) WHEN niOO111OO = '1' ELSE wire_niiOi0li_dataout; + wire_niiOi1Ol_dataout <= k_vc1(30) WHEN niOO111OO = '1' ELSE wire_niiOi0ll_dataout; + wire_niiOi1OO_dataout <= k_vc1(31) WHEN niOO111OO = '1' ELSE wire_niiOi0lO_dataout; + wire_niiOii0i_dataout <= k_vc1(54) WHEN niOO1101i = '1' ELSE wire_niiOil1i_dataout; + wire_niiOii0l_dataout <= k_vc1(55) WHEN niOO1101i = '1' ELSE wire_niiOil1l_dataout; + wire_niiOii0O_dataout <= k_vc0(8) WHEN niOO1101l = '1' ELSE wire_niiOil1O_dataout; + wire_niiOii1i_dataout <= k_vc1(51) WHEN niOO1101i = '1' ELSE wire_niiOiiOi_dataout; + wire_niiOii1l_dataout <= k_vc1(52) WHEN niOO1101i = '1' ELSE wire_niiOiiOl_dataout; + wire_niiOii1O_dataout <= k_vc1(53) WHEN niOO1101i = '1' ELSE wire_niiOiiOO_dataout; + wire_niiOiii_dataout <= wire_nilii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOiiii_dataout <= k_vc0(9) WHEN niOO1101l = '1' ELSE wire_niiOil0i_dataout; + wire_niiOiiil_dataout <= k_vc0(10) WHEN niOO1101l = '1' ELSE wire_niiOil0l_dataout; + wire_niiOiiiO_dataout <= k_vc0(11) WHEN niOO1101l = '1' ELSE wire_niiOil0O_dataout; + wire_niiOiil_dataout <= wire_niliiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOiili_dataout <= k_vc0(12) WHEN niOO1101l = '1' ELSE wire_niiOilii_dataout; + wire_niiOiill_dataout <= k_vc0(13) WHEN niOO1101l = '1' ELSE wire_niiOilil_dataout; + wire_niiOiilO_dataout <= k_vc0(14) WHEN niOO1101l = '1' ELSE wire_niiOiliO_dataout; + wire_niiOiiO_dataout <= wire_niliiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOiiOi_dataout <= k_vc0(15) WHEN niOO1101l = '1' ELSE wire_niiOilli_dataout; + wire_niiOiiOl_dataout <= k_vc0(16) WHEN niOO1101l = '1' ELSE wire_niiOilll_dataout; + wire_niiOiiOO_dataout <= k_vc0(17) WHEN niOO1101l = '1' ELSE wire_niiOillO_dataout; + wire_niiOil0i_dataout <= k_vc0(29) WHEN niOO1101O = '1' ELSE k_vc0(45); + wire_niiOil0l_dataout <= k_vc0(30) WHEN niOO1101O = '1' ELSE k_vc0(46); + wire_niiOil0O_dataout <= k_vc0(31) WHEN niOO1101O = '1' ELSE k_vc0(47); + wire_niiOil1i_dataout <= k_vc0(18) WHEN niOO1101l = '1' ELSE wire_niiOilOi_dataout; + wire_niiOil1l_dataout <= k_vc0(19) WHEN niOO1101l = '1' ELSE wire_niiOilOl_dataout; + wire_niiOil1O_dataout <= k_vc0(28) WHEN niOO1101O = '1' ELSE k_vc0(44); + wire_niiOili_dataout <= wire_niliiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOilii_dataout <= k_vc0(32) WHEN niOO1101O = '1' ELSE k_vc0(48); + wire_niiOilil_dataout <= k_vc0(33) WHEN niOO1101O = '1' ELSE k_vc0(49); + wire_niiOiliO_dataout <= k_vc0(34) WHEN niOO1101O = '1' ELSE k_vc0(50); + wire_niiOill_dataout <= wire_niliili_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOilli_dataout <= k_vc0(35) WHEN niOO1101O = '1' ELSE k_vc0(51); + wire_niiOilll_dataout <= k_vc0(52) AND NOT(niOO1101O); + wire_niiOillO_dataout <= k_vc0(53) AND NOT(niOO1101O); + wire_niiOilO_dataout <= wire_niliill_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOilOi_dataout <= k_vc0(54) AND NOT(niOO1101O); + wire_niiOilOl_dataout <= k_vc0(55) AND NOT(niOO1101O); + wire_niiOilOO_dataout <= k_vc7(0) WHEN niOO1100i = '1' ELSE wire_niiOiOil_dataout; + wire_niiOiO0i_dataout <= k_vc7(4) WHEN niOO1100i = '1' ELSE wire_niiOiOlO_dataout; + wire_niiOiO0l_dataout <= k_vc7(5) WHEN niOO1100i = '1' ELSE wire_niiOiOOi_dataout; + wire_niiOiO0O_dataout <= k_vc7(6) WHEN niOO1100i = '1' ELSE wire_niiOiOOl_dataout; + wire_niiOiO1i_dataout <= k_vc7(1) WHEN niOO1100i = '1' ELSE wire_niiOiOiO_dataout; + wire_niiOiO1l_dataout <= k_vc7(2) WHEN niOO1100i = '1' ELSE wire_niiOiOli_dataout; + wire_niiOiO1O_dataout <= k_vc7(3) WHEN niOO1100i = '1' ELSE wire_niiOiOll_dataout; + wire_niiOiOi_dataout <= wire_niliilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOiOii_dataout <= k_vc7(7) WHEN niOO1100i = '1' ELSE wire_niiOiOOO_dataout; + wire_niiOiOil_dataout <= k_vc7(20) WHEN niOO1100l = '1' ELSE wire_niiOl11i_dataout; + wire_niiOiOiO_dataout <= k_vc7(21) WHEN niOO1100l = '1' ELSE wire_niiOl11l_dataout; + wire_niiOiOl_dataout <= wire_niliiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOiOli_dataout <= k_vc7(22) WHEN niOO1100l = '1' ELSE wire_niiOl11O_dataout; + wire_niiOiOll_dataout <= k_vc7(23) WHEN niOO1100l = '1' ELSE wire_niiOl10i_dataout; + wire_niiOiOlO_dataout <= k_vc7(24) WHEN niOO1100l = '1' ELSE wire_niiOl10l_dataout; + wire_niiOiOO_dataout <= wire_niliiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOiOOi_dataout <= k_vc7(25) WHEN niOO1100l = '1' ELSE wire_niiOl10O_dataout; + wire_niiOiOOl_dataout <= k_vc7(26) WHEN niOO1100l = '1' ELSE wire_niiOl1ii_dataout; + wire_niiOiOOO_dataout <= k_vc7(27) WHEN niOO1100l = '1' ELSE wire_niiOl1il_dataout; + wire_niiOl00i_dataout <= k_vc6(22) WHEN niOO110il = '1' ELSE wire_niiOl0lO_dataout; + wire_niiOl00l_dataout <= k_vc6(23) WHEN niOO110il = '1' ELSE wire_niiOl0Oi_dataout; + wire_niiOl00O_dataout <= k_vc6(24) WHEN niOO110il = '1' ELSE wire_niiOl0Ol_dataout; + wire_niiOl01i_dataout <= k_vc6(7) WHEN niOO110ii = '1' ELSE wire_niiOl0iO_dataout; + wire_niiOl01l_dataout <= k_vc6(20) WHEN niOO110il = '1' ELSE wire_niiOl0li_dataout; + wire_niiOl01O_dataout <= k_vc6(21) WHEN niOO110il = '1' ELSE wire_niiOl0ll_dataout; + wire_niiOl0i_dataout <= wire_nilil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOl0ii_dataout <= k_vc6(25) WHEN niOO110il = '1' ELSE wire_niiOl0OO_dataout; + wire_niiOl0il_dataout <= k_vc6(26) WHEN niOO110il = '1' ELSE wire_niiOli1i_dataout; + wire_niiOl0iO_dataout <= k_vc6(27) WHEN niOO110il = '1' ELSE wire_niiOli1l_dataout; + wire_niiOl0l_dataout <= wire_nilil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOl0li_dataout <= k_vc6(36) WHEN niOO110iO = '1' ELSE wire_niiOli1O_dataout; + wire_niiOl0ll_dataout <= k_vc6(37) WHEN niOO110iO = '1' ELSE wire_niiOli0i_dataout; + wire_niiOl0lO_dataout <= k_vc6(38) WHEN niOO110iO = '1' ELSE wire_niiOli0l_dataout; + wire_niiOl0O_dataout <= wire_nilil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOl0Oi_dataout <= k_vc6(39) WHEN niOO110iO = '1' ELSE wire_niiOli0O_dataout; + wire_niiOl0Ol_dataout <= k_vc6(40) WHEN niOO110iO = '1' ELSE wire_niiOliii_dataout; + wire_niiOl0OO_dataout <= k_vc6(41) WHEN niOO110iO = '1' ELSE wire_niiOliil_dataout; + wire_niiOl10i_dataout <= k_vc7(39) WHEN niOO1100O = '1' ELSE wire_niiOl1lO_dataout; + wire_niiOl10l_dataout <= k_vc7(40) WHEN niOO1100O = '1' ELSE wire_niiOl1Oi_dataout; + wire_niiOl10O_dataout <= k_vc7(41) WHEN niOO1100O = '1' ELSE wire_niiOl1Ol_dataout; + wire_niiOl11i_dataout <= k_vc7(36) WHEN niOO1100O = '1' ELSE wire_niiOl1iO_dataout; + wire_niiOl11l_dataout <= k_vc7(37) WHEN niOO1100O = '1' ELSE wire_niiOl1li_dataout; + wire_niiOl11O_dataout <= k_vc7(38) WHEN niOO1100O = '1' ELSE wire_niiOl1ll_dataout; + wire_niiOl1i_dataout <= wire_niliiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOl1ii_dataout <= k_vc7(42) WHEN niOO1100O = '1' ELSE wire_niiOl1OO_dataout; + wire_niiOl1il_dataout <= k_vc7(43) WHEN niOO1100O = '1' ELSE wire_niiOl01i_dataout; + wire_niiOl1iO_dataout <= k_vc6(0) WHEN niOO110ii = '1' ELSE wire_niiOl01l_dataout; + wire_niiOl1l_dataout <= wire_nilil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOl1li_dataout <= k_vc6(1) WHEN niOO110ii = '1' ELSE wire_niiOl01O_dataout; + wire_niiOl1ll_dataout <= k_vc6(2) WHEN niOO110ii = '1' ELSE wire_niiOl00i_dataout; + wire_niiOl1lO_dataout <= k_vc6(3) WHEN niOO110ii = '1' ELSE wire_niiOl00l_dataout; + wire_niiOl1O_dataout <= wire_nilil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOl1Oi_dataout <= k_vc6(4) WHEN niOO110ii = '1' ELSE wire_niiOl00O_dataout; + wire_niiOl1Ol_dataout <= k_vc6(5) WHEN niOO110ii = '1' ELSE wire_niiOl0ii_dataout; + wire_niiOl1OO_dataout <= k_vc6(6) WHEN niOO110ii = '1' ELSE wire_niiOl0il_dataout; + wire_niiOli0i_dataout <= k_vc5(1) WHEN niOO110li = '1' ELSE wire_niiOlilO_dataout; + wire_niiOli0l_dataout <= k_vc5(2) WHEN niOO110li = '1' ELSE wire_niiOliOi_dataout; + wire_niiOli0O_dataout <= k_vc5(3) WHEN niOO110li = '1' ELSE wire_niiOliOl_dataout; + wire_niiOli1i_dataout <= k_vc6(42) WHEN niOO110iO = '1' ELSE wire_niiOliiO_dataout; + wire_niiOli1l_dataout <= k_vc6(43) WHEN niOO110iO = '1' ELSE wire_niiOlili_dataout; + wire_niiOli1O_dataout <= k_vc5(0) WHEN niOO110li = '1' ELSE wire_niiOlill_dataout; + wire_niiOlii_dataout <= wire_nilil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOliii_dataout <= k_vc5(4) WHEN niOO110li = '1' ELSE wire_niiOliOO_dataout; + wire_niiOliil_dataout <= k_vc5(5) WHEN niOO110li = '1' ELSE wire_niiOll1i_dataout; + wire_niiOliiO_dataout <= k_vc5(6) WHEN niOO110li = '1' ELSE wire_niiOll1l_dataout; + wire_niiOlil_dataout <= wire_nililii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOlili_dataout <= k_vc5(7) WHEN niOO110li = '1' ELSE wire_niiOll1O_dataout; + wire_niiOlill_dataout <= k_vc5(20) WHEN niOO110ll = '1' ELSE wire_niiOll0i_dataout; + wire_niiOlilO_dataout <= k_vc5(21) WHEN niOO110ll = '1' ELSE wire_niiOll0l_dataout; + wire_niiOliO_dataout <= wire_nil1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOliOi_dataout <= k_vc5(22) WHEN niOO110ll = '1' ELSE wire_niiOll0O_dataout; + wire_niiOliOl_dataout <= k_vc5(23) WHEN niOO110ll = '1' ELSE wire_niiOllii_dataout; + wire_niiOliOO_dataout <= k_vc5(24) WHEN niOO110ll = '1' ELSE wire_niiOllil_dataout; + wire_niiOll0i_dataout <= k_vc5(36) WHEN niOO110lO = '1' ELSE wire_niiOlllO_dataout; + wire_niiOll0l_dataout <= k_vc5(37) WHEN niOO110lO = '1' ELSE wire_niiOllOi_dataout; + wire_niiOll0O_dataout <= k_vc5(38) WHEN niOO110lO = '1' ELSE wire_niiOllOl_dataout; + wire_niiOll1i_dataout <= k_vc5(25) WHEN niOO110ll = '1' ELSE wire_niiOlliO_dataout; + wire_niiOll1l_dataout <= k_vc5(26) WHEN niOO110ll = '1' ELSE wire_niiOllli_dataout; + wire_niiOll1O_dataout <= k_vc5(27) WHEN niOO110ll = '1' ELSE wire_niiOllll_dataout; + wire_niiOlli_dataout <= wire_nil10lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOllii_dataout <= k_vc5(39) WHEN niOO110lO = '1' ELSE wire_niiOllOO_dataout; + wire_niiOllil_dataout <= k_vc5(40) WHEN niOO110lO = '1' ELSE wire_niiOlO1i_dataout; + wire_niiOlliO_dataout <= k_vc5(41) WHEN niOO110lO = '1' ELSE wire_niiOlO1l_dataout; + wire_niiOlll_dataout <= wire_nil10Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOllli_dataout <= k_vc5(42) WHEN niOO110lO = '1' ELSE wire_niiOlO1O_dataout; + wire_niiOllll_dataout <= k_vc5(43) WHEN niOO110lO = '1' ELSE wire_niiOlO0i_dataout; + wire_niiOlllO_dataout <= k_vc4(0) WHEN niOO110Oi = '1' ELSE wire_niiOlO0l_dataout; + wire_niiOllO_dataout <= wire_nil10Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOllOi_dataout <= k_vc4(1) WHEN niOO110Oi = '1' ELSE wire_niiOlO0O_dataout; + wire_niiOllOl_dataout <= k_vc4(2) WHEN niOO110Oi = '1' ELSE wire_niiOlOii_dataout; + wire_niiOllOO_dataout <= k_vc4(3) WHEN niOO110Oi = '1' ELSE wire_niiOlOil_dataout; + wire_niiOlO0i_dataout <= k_vc4(7) WHEN niOO110Oi = '1' ELSE wire_niiOlOlO_dataout; + wire_niiOlO0l_dataout <= k_vc4(20) WHEN niOO110Ol = '1' ELSE wire_niiOlOOi_dataout; + wire_niiOlO0O_dataout <= k_vc4(21) WHEN niOO110Ol = '1' ELSE wire_niiOlOOl_dataout; + wire_niiOlO1i_dataout <= k_vc4(4) WHEN niOO110Oi = '1' ELSE wire_niiOlOiO_dataout; + wire_niiOlO1l_dataout <= k_vc4(5) WHEN niOO110Oi = '1' ELSE wire_niiOlOli_dataout; + wire_niiOlO1O_dataout <= k_vc4(6) WHEN niOO110Oi = '1' ELSE wire_niiOlOll_dataout; + wire_niiOlOi_dataout <= wire_nil10OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOlOii_dataout <= k_vc4(22) WHEN niOO110Ol = '1' ELSE wire_niiOlOOO_dataout; + wire_niiOlOil_dataout <= k_vc4(23) WHEN niOO110Ol = '1' ELSE wire_niiOO11i_dataout; + wire_niiOlOiO_dataout <= k_vc4(24) WHEN niOO110Ol = '1' ELSE wire_niiOO11l_dataout; + wire_niiOlOl_dataout <= wire_nil1i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOlOli_dataout <= k_vc4(25) WHEN niOO110Ol = '1' ELSE wire_niiOO11O_dataout; + wire_niiOlOll_dataout <= k_vc4(26) WHEN niOO110Ol = '1' ELSE wire_niiOO10i_dataout; + wire_niiOlOlO_dataout <= k_vc4(27) WHEN niOO110Ol = '1' ELSE wire_niiOO10l_dataout; + wire_niiOlOO_dataout <= wire_nil1i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOlOOi_dataout <= k_vc4(36) WHEN niOO110OO = '1' ELSE wire_niiOO10O_dataout; + wire_niiOlOOl_dataout <= k_vc4(37) WHEN niOO110OO = '1' ELSE wire_niiOO1ii_dataout; + wire_niiOlOOO_dataout <= k_vc4(38) WHEN niOO110OO = '1' ELSE wire_niiOO1il_dataout; + wire_niiOO00i_dataout <= k_vc3(25) WHEN niOO11i1l = '1' ELSE wire_niiOO0lO_dataout; + wire_niiOO00l_dataout <= k_vc3(26) WHEN niOO11i1l = '1' ELSE wire_niiOO0Oi_dataout; + wire_niiOO00O_dataout <= k_vc3(27) WHEN niOO11i1l = '1' ELSE wire_niiOO0Ol_dataout; + wire_niiOO01i_dataout <= k_vc3(22) WHEN niOO11i1l = '1' ELSE wire_niiOO0iO_dataout; + wire_niiOO01l_dataout <= k_vc3(23) WHEN niOO11i1l = '1' ELSE wire_niiOO0li_dataout; + wire_niiOO01O_dataout <= k_vc3(24) WHEN niOO11i1l = '1' ELSE wire_niiOO0ll_dataout; + wire_niiOO0i_dataout <= wire_nil1i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOO0ii_dataout <= k_vc3(36) WHEN niOO11i1O = '1' ELSE wire_niiOO0OO_dataout; + wire_niiOO0il_dataout <= k_vc3(37) WHEN niOO11i1O = '1' ELSE wire_niiOOi1i_dataout; + wire_niiOO0iO_dataout <= k_vc3(38) WHEN niOO11i1O = '1' ELSE wire_niiOOi1l_dataout; + wire_niiOO0l_dataout <= wire_nil1iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOO0li_dataout <= k_vc3(39) WHEN niOO11i1O = '1' ELSE wire_niiOOi1O_dataout; + wire_niiOO0ll_dataout <= k_vc3(40) WHEN niOO11i1O = '1' ELSE wire_niiOOi0i_dataout; + wire_niiOO0lO_dataout <= k_vc3(41) WHEN niOO11i1O = '1' ELSE wire_niiOOi0l_dataout; + wire_niiOO0O_dataout <= wire_nil1iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOO0Oi_dataout <= k_vc3(42) WHEN niOO11i1O = '1' ELSE wire_niiOOi0O_dataout; + wire_niiOO0Ol_dataout <= k_vc3(43) WHEN niOO11i1O = '1' ELSE wire_niiOOiii_dataout; + wire_niiOO0OO_dataout <= k_vc2(0) WHEN niOO11i0i = '1' ELSE wire_niiOOiil_dataout; + wire_niiOO10i_dataout <= k_vc4(42) WHEN niOO110OO = '1' ELSE wire_niiOO1lO_dataout; + wire_niiOO10l_dataout <= k_vc4(43) WHEN niOO110OO = '1' ELSE wire_niiOO1Oi_dataout; + wire_niiOO10O_dataout <= k_vc3(0) WHEN niOO11i1i = '1' ELSE wire_niiOO1Ol_dataout; + wire_niiOO11i_dataout <= k_vc4(39) WHEN niOO110OO = '1' ELSE wire_niiOO1iO_dataout; + wire_niiOO11l_dataout <= k_vc4(40) WHEN niOO110OO = '1' ELSE wire_niiOO1li_dataout; + wire_niiOO11O_dataout <= k_vc4(41) WHEN niOO110OO = '1' ELSE wire_niiOO1ll_dataout; + wire_niiOO1i_dataout <= wire_nil1i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOO1ii_dataout <= k_vc3(1) WHEN niOO11i1i = '1' ELSE wire_niiOO1OO_dataout; + wire_niiOO1il_dataout <= k_vc3(2) WHEN niOO11i1i = '1' ELSE wire_niiOO01i_dataout; + wire_niiOO1iO_dataout <= k_vc3(3) WHEN niOO11i1i = '1' ELSE wire_niiOO01l_dataout; + wire_niiOO1l_dataout <= wire_nil1i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOO1li_dataout <= k_vc3(4) WHEN niOO11i1i = '1' ELSE wire_niiOO01O_dataout; + wire_niiOO1ll_dataout <= k_vc3(5) WHEN niOO11i1i = '1' ELSE wire_niiOO00i_dataout; + wire_niiOO1lO_dataout <= k_vc3(6) WHEN niOO11i1i = '1' ELSE wire_niiOO00l_dataout; + wire_niiOO1O_dataout <= wire_nil1i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOO1Oi_dataout <= k_vc3(7) WHEN niOO11i1i = '1' ELSE wire_niiOO00O_dataout; + wire_niiOO1Ol_dataout <= k_vc3(20) WHEN niOO11i1l = '1' ELSE wire_niiOO0ii_dataout; + wire_niiOO1OO_dataout <= k_vc3(21) WHEN niOO11i1l = '1' ELSE wire_niiOO0il_dataout; + wire_niiOOi0i_dataout <= k_vc2(4) WHEN niOO11i0i = '1' ELSE wire_niiOOilO_dataout; + wire_niiOOi0l_dataout <= k_vc2(5) WHEN niOO11i0i = '1' ELSE wire_niiOOiOi_dataout; + wire_niiOOi0O_dataout <= k_vc2(6) WHEN niOO11i0i = '1' ELSE wire_niiOOiOl_dataout; + wire_niiOOi1i_dataout <= k_vc2(1) WHEN niOO11i0i = '1' ELSE wire_niiOOiiO_dataout; + wire_niiOOi1l_dataout <= k_vc2(2) WHEN niOO11i0i = '1' ELSE wire_niiOOili_dataout; + wire_niiOOi1O_dataout <= k_vc2(3) WHEN niOO11i0i = '1' ELSE wire_niiOOill_dataout; + wire_niiOOii_dataout <= wire_nil1iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOiii_dataout <= k_vc2(7) WHEN niOO11i0i = '1' ELSE wire_niiOOiOO_dataout; + wire_niiOOiil_dataout <= k_vc2(20) WHEN niOO11i0l = '1' ELSE wire_niiOOl1i_dataout; + wire_niiOOiiO_dataout <= k_vc2(21) WHEN niOO11i0l = '1' ELSE wire_niiOOl1l_dataout; + wire_niiOOil_dataout <= wire_nil1ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOili_dataout <= k_vc2(22) WHEN niOO11i0l = '1' ELSE wire_niiOOl1O_dataout; + wire_niiOOill_dataout <= k_vc2(23) WHEN niOO11i0l = '1' ELSE wire_niiOOl0i_dataout; + wire_niiOOilO_dataout <= k_vc2(24) WHEN niOO11i0l = '1' ELSE wire_niiOOl0l_dataout; + wire_niiOOiO_dataout <= wire_nil1ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOiOi_dataout <= k_vc2(25) WHEN niOO11i0l = '1' ELSE wire_niiOOl0O_dataout; + wire_niiOOiOl_dataout <= k_vc2(26) WHEN niOO11i0l = '1' ELSE wire_niiOOlii_dataout; + wire_niiOOiOO_dataout <= k_vc2(27) WHEN niOO11i0l = '1' ELSE wire_niiOOlil_dataout; + wire_niiOOl0i_dataout <= k_vc2(39) WHEN niOO11i0O = '1' ELSE wire_niiOOllO_dataout; + wire_niiOOl0l_dataout <= k_vc2(40) WHEN niOO11i0O = '1' ELSE wire_niiOOlOi_dataout; + wire_niiOOl0O_dataout <= k_vc2(41) WHEN niOO11i0O = '1' ELSE wire_niiOOlOl_dataout; + wire_niiOOl1i_dataout <= k_vc2(36) WHEN niOO11i0O = '1' ELSE wire_niiOOliO_dataout; + wire_niiOOl1l_dataout <= k_vc2(37) WHEN niOO11i0O = '1' ELSE wire_niiOOlli_dataout; + wire_niiOOl1O_dataout <= k_vc2(38) WHEN niOO11i0O = '1' ELSE wire_niiOOlll_dataout; + wire_niiOOli_dataout <= wire_nil1ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOlii_dataout <= k_vc2(42) WHEN niOO11i0O = '1' ELSE wire_niiOOlOO_dataout; + wire_niiOOlil_dataout <= k_vc2(43) WHEN niOO11i0O = '1' ELSE wire_niiOOO1i_dataout; + wire_niiOOliO_dataout <= k_vc1(0) WHEN niOO11iii = '1' ELSE wire_niiOOO1l_dataout; + wire_niiOOll_dataout <= wire_nil1iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOlli_dataout <= k_vc1(1) WHEN niOO11iii = '1' ELSE wire_niiOOO1O_dataout; + wire_niiOOlll_dataout <= k_vc1(2) WHEN niOO11iii = '1' ELSE wire_niiOOO0i_dataout; + wire_niiOOllO_dataout <= k_vc1(3) WHEN niOO11iii = '1' ELSE wire_niiOOO0l_dataout; + wire_niiOOlO_dataout <= wire_nil1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOlOi_dataout <= k_vc1(4) WHEN niOO11iii = '1' ELSE wire_niiOOO0O_dataout; + wire_niiOOlOl_dataout <= k_vc1(5) WHEN niOO11iii = '1' ELSE wire_niiOOOii_dataout; + wire_niiOOlOO_dataout <= k_vc1(6) WHEN niOO11iii = '1' ELSE wire_niiOOOil_dataout; + wire_niiOOO0i_dataout <= k_vc1(22) WHEN niOO11iil = '1' ELSE wire_niiOOOlO_dataout; + wire_niiOOO0l_dataout <= k_vc1(23) WHEN niOO11iil = '1' ELSE wire_niiOOOOi_dataout; + wire_niiOOO0O_dataout <= k_vc1(24) WHEN niOO11iil = '1' ELSE wire_niiOOOOl_dataout; + wire_niiOOO1i_dataout <= k_vc1(7) WHEN niOO11iii = '1' ELSE wire_niiOOOiO_dataout; + wire_niiOOO1l_dataout <= k_vc1(20) WHEN niOO11iil = '1' ELSE wire_niiOOOli_dataout; + wire_niiOOO1O_dataout <= k_vc1(21) WHEN niOO11iil = '1' ELSE wire_niiOOOll_dataout; + wire_niiOOOi_dataout <= wire_nil1iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOOii_dataout <= k_vc1(25) WHEN niOO11iil = '1' ELSE wire_niiOOOOO_dataout; + wire_niiOOOil_dataout <= k_vc1(26) WHEN niOO11iil = '1' ELSE wire_nil1111i_dataout; + wire_niiOOOiO_dataout <= k_vc1(27) WHEN niOO11iil = '1' ELSE wire_nil1111l_dataout; + wire_niiOOOl_dataout <= wire_nil1l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOOli_dataout <= k_vc1(36) WHEN niOO11iiO = '1' ELSE wire_nil1111O_dataout; + wire_niiOOOll_dataout <= k_vc1(37) WHEN niOO11iiO = '1' ELSE wire_nil1110i_dataout; + wire_niiOOOlO_dataout <= k_vc1(38) WHEN niOO11iiO = '1' ELSE wire_nil1110l_dataout; + wire_niiOOOO_dataout <= wire_nil1l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niiOOOOi_dataout <= k_vc1(39) WHEN niOO11iiO = '1' ELSE wire_nil1110O_dataout; + wire_niiOOOOl_dataout <= k_vc1(40) WHEN niOO11iiO = '1' ELSE wire_nil111ii_dataout; + wire_niiOOOOO_dataout <= k_vc1(41) WHEN niOO11iiO = '1' ELSE wire_nil111il_dataout; + wire_nil0000i_dataout <= wire_nil00i1l_dataout OR niOO100ii; + wire_nil0000l_dataout <= wire_nil00i1O_dataout AND NOT(niOO100ii); + wire_nil0000O_dataout <= wire_nil00i0i_dataout AND NOT(niOO100ii); + wire_nil0001i_dataout <= wire_nil000Ol_dataout AND NOT(niOO1000O); + wire_nil0001l_dataout <= wire_nil000OO_dataout AND NOT(niOO1000O); + wire_nil0001O_dataout <= wire_nil00i1i_dataout AND NOT(niOO1000O); + wire_nil000i_dataout <= nii1Oil WHEN niOO0ll1l = '1' ELSE wire_nilliOO_dataout; + wire_nil000ii_dataout <= wire_nil00i0l_dataout OR niOO100ii; + wire_nil000il_dataout <= wire_nil00i0O_dataout AND NOT(niOO100ii); + wire_nil000iO_dataout <= wire_nil00iii_dataout AND NOT(niOO100ii); + wire_nil000l_dataout <= nii1OiO WHEN niOO0ll1l = '1' ELSE wire_nilll1i_dataout; + wire_nil000li_dataout <= wire_nil00iil_dataout OR niOO100ii; + wire_nil000ll_dataout <= wire_nil00iiO_dataout AND NOT(niOO100ii); + wire_nil000lO_dataout <= wire_nil00ili_dataout AND NOT(niOO100ii); + wire_nil000O_dataout <= nii1Oli WHEN niOO0ll1l = '1' ELSE wire_nilll1l_dataout; + wire_nil000Oi_dataout <= wire_nil00ill_dataout AND NOT(niOO100ii); + wire_nil000Ol_dataout <= wire_nil00ilO_dataout AND NOT(niOO100ii); + wire_nil000OO_dataout <= wire_nil00iOi_dataout AND NOT(niOO100ii); + wire_nil0010i_dataout <= wire_nil0001l_dataout AND NOT(niOO1000l); + wire_nil0010l_dataout <= wire_nil0001O_dataout AND NOT(niOO1000l); + wire_nil0010O_dataout <= wire_nil0000i_dataout AND NOT(niOO1000O); + wire_nil0011i_dataout <= wire_nil001Ol_dataout AND NOT(niOO1000l); + wire_nil0011l_dataout <= wire_nil001OO_dataout AND NOT(niOO1000l); + wire_nil0011O_dataout <= wire_nil0001i_dataout AND NOT(niOO1000l); + wire_nil001i_dataout <= nii1O0l WHEN niOO0ll1l = '1' ELSE wire_nillilO_dataout; + wire_nil001ii_dataout <= wire_nil0000l_dataout AND NOT(niOO1000O); + wire_nil001il_dataout <= wire_nil0000O_dataout AND NOT(niOO1000O); + wire_nil001iO_dataout <= wire_nil000ii_dataout AND NOT(niOO1000O); + wire_nil001l_dataout <= nii1O0O WHEN niOO0ll1l = '1' ELSE wire_nilliOi_dataout; + wire_nil001li_dataout <= wire_nil000il_dataout AND NOT(niOO1000O); + wire_nil001ll_dataout <= wire_nil000iO_dataout AND NOT(niOO1000O); + wire_nil001lO_dataout <= wire_nil000li_dataout AND NOT(niOO1000O); + wire_nil001O_dataout <= nii1Oii WHEN niOO0ll1l = '1' ELSE wire_nilliOl_dataout; + wire_nil001Oi_dataout <= wire_nil000ll_dataout OR niOO1000O; + wire_nil001Ol_dataout <= wire_nil000lO_dataout AND NOT(niOO1000O); + wire_nil001OO_dataout <= wire_nil000Oi_dataout AND NOT(niOO1000O); + wire_nil00i0i_dataout <= wire_nil00l1l_dataout AND NOT(niOO10l0O); + wire_nil00i0l_dataout <= wire_nil00l1O_dataout AND NOT(niOO10l0O); + wire_nil00i0O_dataout <= wire_nil00l0i_dataout AND NOT(niOO10l0O); + wire_nil00i1i_dataout <= wire_nil00iOl_dataout AND NOT(niOO100ii); + wire_nil00i1l_dataout <= wire_nil00iOO_dataout OR niOO10l0O; + wire_nil00i1O_dataout <= wire_nil00l1i_dataout OR niOO10l0O; + wire_nil00ii_dataout <= nii1Oll WHEN niOO0ll1l = '1' ELSE wire_nilll1O_dataout; + wire_nil00iii_dataout <= wire_nil00l0l_dataout AND NOT(niOO10l0O); + wire_nil00iil_dataout <= wire_nil00l0O_dataout OR niOO10l0O; + wire_nil00iiO_dataout <= wire_nil00lii_dataout AND NOT(niOO10l0O); + wire_nil00il_dataout <= nii1OlO WHEN niOO0ll1l = '1' ELSE wire_nilll0i_dataout; + wire_nil00ili_dataout <= wire_nil00lil_dataout AND NOT(niOO10l0O); + wire_nil00ill_dataout <= wire_nil00liO_dataout AND NOT(niOO10l0O); + wire_nil00ilO_dataout <= wire_nil00lli_dataout AND NOT(niOO10l0O); + wire_nil00iO_dataout <= nii1OOi WHEN niOO0ll1l = '1' ELSE wire_nilll0l_dataout; + wire_nil00iOi_dataout <= wire_nil00lll_dataout AND NOT(niOO10l0O); + wire_nil00iOl_dataout <= niOO100il AND NOT(niOO10l0O); + wire_nil00iOO_dataout <= wire_nil00llO_dataout AND NOT(niOO100il); + wire_nil00l0i_dataout <= wire_nil00O1i_dataout AND NOT(niOO100il); + wire_nil00l0l_dataout <= wire_nil00O1l_dataout OR niOO100il; + wire_nil00l0O_dataout <= wire_nil00O1O_dataout OR niOO100il; + wire_nil00l1i_dataout <= wire_nil00lOi_dataout OR niOO100il; + wire_nil00l1l_dataout <= wire_nil00lOl_dataout AND NOT(niOO100il); + wire_nil00l1O_dataout <= wire_nil00lOO_dataout AND NOT(niOO100il); + wire_nil00li_dataout <= nii1OOl WHEN niOO0ll1l = '1' ELSE wire_nilll0O_dataout; + wire_nil00lii_dataout <= wire_nil00O0i_dataout AND NOT(niOO100il); + wire_nil00lil_dataout <= wire_nil00O0l_dataout AND NOT(niOO100il); + wire_nil00liO_dataout <= wire_nil00O0O_dataout AND NOT(niOO100il); + wire_nil00ll_dataout <= nii1OOO WHEN niOO0ll1l = '1' ELSE wire_nilllii_dataout; + wire_nil00lli_dataout <= wire_nil00Oii_dataout AND NOT(niOO100il); + wire_nil00lll_dataout <= wire_nil00Oil_dataout AND NOT(niOO100il); + wire_nil00llO_dataout <= wire_nil00OiO_dataout AND NOT(niOO100iO); + wire_nil00lO_dataout <= nii011i WHEN niOO0ll1l = '1' ELSE wire_nilllil_dataout; + wire_nil00lOi_dataout <= wire_nil00Oli_dataout AND NOT(niOO100iO); + wire_nil00lOl_dataout <= wire_nil00Oll_dataout OR niOO100iO; + wire_nil00lOO_dataout <= wire_nil00OlO_dataout AND NOT(niOO100iO); + wire_nil00O0i_dataout <= wire_nil0i11i_dataout AND NOT(niOO100iO); + wire_nil00O0l_dataout <= wire_nil0i11l_dataout AND NOT(niOO100iO); + wire_nil00O0O_dataout <= wire_nil0i11O_dataout AND NOT(niOO100iO); + wire_nil00O1i_dataout <= wire_nil00OOi_dataout OR niOO100iO; + wire_nil00O1l_dataout <= wire_nil00OOl_dataout AND NOT(niOO100iO); + wire_nil00O1O_dataout <= wire_nil00OOO_dataout OR niOO100iO; + wire_nil00Oi_dataout <= nii011l WHEN niOO0ll1l = '1' ELSE wire_nillliO_dataout; + wire_nil00Oii_dataout <= wire_nil0i10i_dataout AND NOT(niOO100iO); + wire_nil00Oil_dataout <= wire_nil0i10l_dataout OR niOO100iO; + wire_nil00OiO_dataout <= wire_nil0i10O_dataout OR niOO100li; + wire_nil00Ol_dataout <= nii011O WHEN niOO0ll1l = '1' ELSE wire_nilllli_dataout; + wire_nil00Oli_dataout <= wire_nil0i1ii_dataout AND NOT(niOO100li); + wire_nil00Oll_dataout <= wire_nil0i1il_dataout OR niOO100li; + wire_nil00OlO_dataout <= wire_nil0i1iO_dataout OR niOO100li; + wire_nil00OO_dataout <= nii010i WHEN niOO0ll1l = '1' ELSE wire_nilllll_dataout; + wire_nil00OOi_dataout <= wire_nil0i1li_dataout AND NOT(niOO100li); + wire_nil00OOl_dataout <= wire_nil0i1ll_dataout AND NOT(niOO100li); + wire_nil00OOO_dataout <= wire_nil0i1lO_dataout OR niOO100li; + wire_nil0100i_dataout <= wire_nil01i1l_dataout AND NOT(niOO1001i); + wire_nil0100l_dataout <= wire_nil01i1O_dataout AND NOT(niOO1001i); + wire_nil0100O_dataout <= wire_nil01i0i_dataout OR niOO1001i; + wire_nil0101i_dataout <= wire_nil010Ol_dataout AND NOT(niOO1001i); + wire_nil0101l_dataout <= wire_nil010OO_dataout AND NOT(niOO1001i); + wire_nil0101O_dataout <= wire_nil01i1i_dataout AND NOT(niOO1001i); + wire_nil010i_dataout <= nii1lil WHEN niOO0ll1l = '1' ELSE wire_nill0OO_dataout; + wire_nil010ii_dataout <= wire_nil01i0l_dataout AND NOT(niOO1001i); + wire_nil010il_dataout <= wire_nil01i0O_dataout OR niOO1001i; + wire_nil010iO_dataout <= wire_nil01iii_dataout OR niOO1001i; + wire_nil010l_dataout <= nii1liO WHEN niOO0ll1l = '1' ELSE wire_nilli1i_dataout; + wire_nil010li_dataout <= wire_nil01iil_dataout AND NOT(niOO1001i); + wire_nil010ll_dataout <= wire_nil01iiO_dataout AND NOT(niOO1001i); + wire_nil010lO_dataout <= wire_nil01ili_dataout AND NOT(niOO1001i); + wire_nil010O_dataout <= nii1lli WHEN niOO0ll1l = '1' ELSE wire_nilli1l_dataout; + wire_nil010Oi_dataout <= wire_nil01ill_dataout AND NOT(niOO1001i); + wire_nil010Ol_dataout <= wire_nil01ilO_dataout OR niOO1001l; + wire_nil010OO_dataout <= wire_nil01iOi_dataout AND NOT(niOO1001l); + wire_nil0110i_dataout <= wire_nil0101l_dataout OR niOO101OO; + wire_nil0110l_dataout <= wire_nil0101O_dataout OR niOO101OO; + wire_nil0110O_dataout <= wire_nil0100i_dataout AND NOT(niOO101OO); + wire_nil0111i_dataout <= wire_nil011Ol_dataout AND NOT(niOO101Ol); + wire_nil0111l_dataout <= wire_nil011OO_dataout AND NOT(niOO101Ol); + wire_nil0111O_dataout <= wire_nil0101i_dataout AND NOT(niOO101OO); + wire_nil011i_dataout <= nii1l0l WHEN niOO0ll1l = '1' ELSE wire_nill0lO_dataout; + wire_nil011ii_dataout <= wire_nil0100l_dataout OR niOO101OO; + wire_nil011il_dataout <= wire_nil0100O_dataout AND NOT(niOO101OO); + wire_nil011iO_dataout <= wire_nil010ii_dataout OR niOO101OO; + wire_nil011l_dataout <= nii1l0O WHEN niOO0ll1l = '1' ELSE wire_nill0Oi_dataout; + wire_nil011li_dataout <= wire_nil010il_dataout AND NOT(niOO101OO); + wire_nil011ll_dataout <= wire_nil010iO_dataout AND NOT(niOO101OO); + wire_nil011lO_dataout <= wire_nil010li_dataout AND NOT(niOO101OO); + wire_nil011O_dataout <= nii1lii WHEN niOO0ll1l = '1' ELSE wire_nill0Ol_dataout; + wire_nil011Oi_dataout <= wire_nil010ll_dataout AND NOT(niOO101OO); + wire_nil011Ol_dataout <= wire_nil010lO_dataout AND NOT(niOO101OO); + wire_nil011OO_dataout <= wire_nil010Oi_dataout AND NOT(niOO101OO); + wire_nil01i0i_dataout <= wire_nil01l1l_dataout AND NOT(niOO1001l); + wire_nil01i0l_dataout <= wire_nil01l1O_dataout OR niOO1001l; + wire_nil01i0O_dataout <= wire_nil01l0i_dataout OR niOO1001l; + wire_nil01i1i_dataout <= wire_nil01iOl_dataout AND NOT(niOO1001l); + wire_nil01i1l_dataout <= wire_nil01iOO_dataout OR niOO1001l; + wire_nil01i1O_dataout <= wire_nil01l1i_dataout OR niOO1001l; + wire_nil01ii_dataout <= nii1lll WHEN niOO0ll1l = '1' ELSE wire_nilli1O_dataout; + wire_nil01iii_dataout <= wire_nil01l0l_dataout AND NOT(niOO1001l); + wire_nil01iil_dataout <= wire_nil01l0O_dataout AND NOT(niOO1001l); + wire_nil01iiO_dataout <= wire_nil01lii_dataout AND NOT(niOO1001l); + wire_nil01il_dataout <= nii1llO WHEN niOO0ll1l = '1' ELSE wire_nilli0i_dataout; + wire_nil01ili_dataout <= wire_nil01lil_dataout AND NOT(niOO1001l); + wire_nil01ill_dataout <= wire_nil01liO_dataout AND NOT(niOO1001l); + wire_nil01ilO_dataout <= wire_nil01lli_dataout AND NOT(niOO1001O); + wire_nil01iO_dataout <= nii1lOi WHEN niOO0ll1l = '1' ELSE wire_nilli0l_dataout; + wire_nil01iOi_dataout <= wire_nil01lll_dataout OR niOO1001O; + wire_nil01iOl_dataout <= wire_nil01llO_dataout OR niOO1001O; + wire_nil01iOO_dataout <= wire_nil01lOi_dataout AND NOT(niOO1001O); + wire_nil01l0i_dataout <= wire_nil01O1l_dataout AND NOT(niOO1001O); + wire_nil01l0l_dataout <= wire_nil01O1O_dataout AND NOT(niOO1001O); + wire_nil01l0O_dataout <= wire_nil01O0i_dataout AND NOT(niOO1001O); + wire_nil01l1i_dataout <= wire_nil01lOl_dataout OR niOO1001O; + wire_nil01l1l_dataout <= wire_nil01lOO_dataout OR niOO1001O; + wire_nil01l1O_dataout <= wire_nil01O1i_dataout OR niOO1001O; + wire_nil01li_dataout <= nii1lOl WHEN niOO0ll1l = '1' ELSE wire_nilli0O_dataout; + wire_nil01lii_dataout <= wire_nil01O0l_dataout AND NOT(niOO1001O); + wire_nil01lil_dataout <= wire_nil01O0O_dataout AND NOT(niOO1001O); + wire_nil01liO_dataout <= wire_nil01Oii_dataout AND NOT(niOO1001O); + wire_nil01ll_dataout <= nii1lOO WHEN niOO0ll1l = '1' ELSE wire_nilliii_dataout; + wire_nil01lli_dataout <= wire_nil01Oil_dataout OR niOO1000i; + wire_nil01lll_dataout <= wire_nil01OiO_dataout OR niOO1000i; + wire_nil01llO_dataout <= wire_nil01Oli_dataout AND NOT(niOO1000i); + wire_nil01lO_dataout <= nii1O1i WHEN niOO0ll1l = '1' ELSE wire_nilliil_dataout; + wire_nil01lOi_dataout <= wire_nil01Oll_dataout OR niOO1000i; + wire_nil01lOl_dataout <= wire_nil01OlO_dataout AND NOT(niOO1000i); + wire_nil01lOO_dataout <= wire_nil01OOi_dataout OR niOO1000i; + wire_nil01O0i_dataout <= wire_nil0011l_dataout AND NOT(niOO1000i); + wire_nil01O0l_dataout <= wire_nil0011O_dataout AND NOT(niOO1000i); + wire_nil01O0O_dataout <= wire_nil0010i_dataout AND NOT(niOO1000i); + wire_nil01O1i_dataout <= wire_nil01OOl_dataout OR niOO1000i; + wire_nil01O1l_dataout <= wire_nil01OOO_dataout AND NOT(niOO1000i); + wire_nil01O1O_dataout <= wire_nil0011i_dataout AND NOT(niOO1000i); + wire_nil01Oi_dataout <= nii1O1l WHEN niOO0ll1l = '1' ELSE wire_nilliiO_dataout; + wire_nil01Oii_dataout <= wire_nil0010l_dataout AND NOT(niOO1000i); + wire_nil01Oil_dataout <= wire_nil0010O_dataout OR niOO1000l; + wire_nil01OiO_dataout <= wire_nil001ii_dataout AND NOT(niOO1000l); + wire_nil01Ol_dataout <= nii1O1O WHEN niOO0ll1l = '1' ELSE wire_nillili_dataout; + wire_nil01Oli_dataout <= wire_nil001il_dataout OR niOO1000l; + wire_nil01Oll_dataout <= wire_nil001iO_dataout OR niOO1000l; + wire_nil01OlO_dataout <= wire_nil001li_dataout AND NOT(niOO1000l); + wire_nil01OO_dataout <= nii1O0i WHEN niOO0ll1l = '1' ELSE wire_nillill_dataout; + wire_nil01OOi_dataout <= wire_nil001ll_dataout OR niOO1000l; + wire_nil01OOl_dataout <= wire_nil001lO_dataout OR niOO1000l; + wire_nil01OOO_dataout <= wire_nil001Oi_dataout OR niOO1000l; + wire_nil0i00i_dataout <= wire_nil0i0OO_dataout OR niOO100lO; + wire_nil0i00l_dataout <= wire_nil0ii1i_dataout AND NOT(niOO100lO); + wire_nil0i00O_dataout <= wire_nil0ii1l_dataout AND NOT(niOO100lO); + wire_nil0i01i_dataout <= wire_nil0i0Oi_dataout AND NOT(niOO100ll); + wire_nil0i01l_dataout <= niOO100lO AND NOT(niOO100ll); + wire_nil0i01O_dataout <= wire_nil0i0Ol_dataout AND NOT(niOO100lO); + wire_nil0i0i_dataout <= nii01il WHEN niOO0ll1l = '1' ELSE wire_nilllOO_dataout; + wire_nil0i0ii_dataout <= wire_nil0ii1O_dataout AND NOT(niOO100lO); + wire_nil0i0il_dataout <= wire_nil0ii0i_dataout OR niOO100lO; + wire_nil0i0iO_dataout <= wire_nil0ii0l_dataout OR niOO100lO; + wire_nil0i0l_dataout <= nii01iO WHEN niOO0ll1l = '1' ELSE wire_nillO1i_dataout; + wire_nil0i0li_dataout <= wire_nil0ii0O_dataout AND NOT(niOO100lO); + wire_nil0i0ll_dataout <= wire_nil0iiii_dataout AND NOT(niOO100lO); + wire_nil0i0lO_dataout <= wire_nil0iiil_dataout AND NOT(niOO100lO); + wire_nil0i0O_dataout <= nii01li WHEN niOO0ll1l = '1' ELSE wire_nillO1l_dataout; + wire_nil0i0Oi_dataout <= wire_nil0iiiO_dataout AND NOT(niOO100lO); + wire_nil0i0Ol_dataout <= wire_nil0iili_dataout AND NOT(niOO100Oi); + wire_nil0i0OO_dataout <= wire_nil0iill_dataout AND NOT(niOO100Oi); + wire_nil0i10i_dataout <= wire_nil0i01i_dataout OR niOO100li; + wire_nil0i10l_dataout <= wire_nil0i01l_dataout AND NOT(niOO100li); + wire_nil0i10O_dataout <= wire_nil0i01O_dataout OR niOO100ll; + wire_nil0i11i_dataout <= wire_nil0i1Oi_dataout AND NOT(niOO100li); + wire_nil0i11l_dataout <= wire_nil0i1Ol_dataout AND NOT(niOO100li); + wire_nil0i11O_dataout <= wire_nil0i1OO_dataout AND NOT(niOO100li); + wire_nil0i1i_dataout <= nii010l WHEN niOO0ll1l = '1' ELSE wire_nillllO_dataout; + wire_nil0i1ii_dataout <= wire_nil0i00i_dataout AND NOT(niOO100ll); + wire_nil0i1il_dataout <= wire_nil0i00l_dataout AND NOT(niOO100ll); + wire_nil0i1iO_dataout <= wire_nil0i00O_dataout OR niOO100ll; + wire_nil0i1l_dataout <= nii010O WHEN niOO0ll1l = '1' ELSE wire_nilllOi_dataout; + wire_nil0i1li_dataout <= wire_nil0i0ii_dataout AND NOT(niOO100ll); + wire_nil0i1ll_dataout <= wire_nil0i0il_dataout AND NOT(niOO100ll); + wire_nil0i1lO_dataout <= wire_nil0i0iO_dataout OR niOO100ll; + wire_nil0i1O_dataout <= nii01ii WHEN niOO0ll1l = '1' ELSE wire_nilllOl_dataout; + wire_nil0i1Oi_dataout <= wire_nil0i0li_dataout AND NOT(niOO100ll); + wire_nil0i1Ol_dataout <= wire_nil0i0ll_dataout AND NOT(niOO100ll); + wire_nil0i1OO_dataout <= wire_nil0i0lO_dataout OR niOO100ll; + wire_nil0ii0i_dataout <= wire_nil0iiOO_dataout AND NOT(niOO100Oi); + wire_nil0ii0l_dataout <= wire_nil0il1i_dataout OR niOO100Oi; + wire_nil0ii0O_dataout <= wire_nil0il1l_dataout AND NOT(niOO100Oi); + wire_nil0ii1i_dataout <= wire_nil0iilO_dataout OR niOO100Oi; + wire_nil0ii1l_dataout <= wire_nil0iiOi_dataout AND NOT(niOO100Oi); + wire_nil0ii1O_dataout <= wire_nil0iiOl_dataout OR niOO100Oi; + wire_nil0iii_dataout <= nii01ll WHEN niOO0ll1l = '1' ELSE wire_nillO1O_dataout; + wire_nil0iiii_dataout <= wire_nil0il1O_dataout AND NOT(niOO100Oi); + wire_nil0iiil_dataout <= wire_nil0il0i_dataout AND NOT(niOO100Oi); + wire_nil0iiiO_dataout <= wire_nil0il0l_dataout OR niOO100Oi; + wire_nil0iil_dataout <= nii01lO WHEN niOO0ll1l = '1' ELSE wire_nillO0i_dataout; + wire_nil0iili_dataout <= wire_nil0il0O_dataout OR niOO100Ol; + wire_nil0iill_dataout <= wire_nil0ilii_dataout AND NOT(niOO100Ol); + wire_nil0iilO_dataout <= wire_nil0ilil_dataout OR niOO100Ol; + wire_nil0iiO_dataout <= nii01Oi WHEN niOO0ll1l = '1' ELSE wire_nillO0l_dataout; + wire_nil0iiOi_dataout <= wire_nil0iliO_dataout OR niOO100Ol; + wire_nil0iiOl_dataout <= wire_nil0illi_dataout AND NOT(niOO100Ol); + wire_nil0iiOO_dataout <= wire_nil0illl_dataout AND NOT(niOO100Ol); + wire_nil0il0i_dataout <= wire_nil0ilOO_dataout OR niOO100Ol; + wire_nil0il0l_dataout <= wire_nil0iO1i_dataout AND NOT(niOO100Ol); + wire_nil0il0O_dataout <= wire_nil0iO1l_dataout OR niOO100OO; + wire_nil0il1i_dataout <= wire_nil0illO_dataout OR niOO100Ol; + wire_nil0il1l_dataout <= wire_nil0ilOi_dataout AND NOT(niOO100Ol); + wire_nil0il1O_dataout <= wire_nil0ilOl_dataout AND NOT(niOO100Ol); + wire_nil0ili_dataout <= nii01Ol WHEN niOO0ll1l = '1' ELSE wire_nillO0O_dataout; + wire_nil0ilii_dataout <= wire_nil0iO1O_dataout AND NOT(niOO100OO); + wire_nil0ilil_dataout <= wire_nil0iO0i_dataout AND NOT(niOO100OO); + wire_nil0iliO_dataout <= wire_nil0iO0l_dataout OR niOO100OO; + wire_nil0ill_dataout <= nii01OO WHEN niOO0ll1l = '1' ELSE wire_nillOii_dataout; + wire_nil0illi_dataout <= wire_nil0iO0O_dataout AND NOT(niOO100OO); + wire_nil0illl_dataout <= wire_nil0iOii_dataout AND NOT(niOO100OO); + wire_nil0illO_dataout <= wire_nil0iOil_dataout OR niOO100OO; + wire_nil0ilO_dataout <= nii001i WHEN niOO0ll1l = '1' ELSE wire_nillOil_dataout; + wire_nil0ilOi_dataout <= wire_nil0iOiO_dataout AND NOT(niOO100OO); + wire_nil0ilOl_dataout <= wire_nil0iOli_dataout OR niOO100OO; + wire_nil0ilOO_dataout <= wire_nil0iOll_dataout AND NOT(niOO100OO); + wire_nil0iO0i_dataout <= wire_nil0iOOl_dataout AND NOT(niOO10i1i); + wire_nil0iO0l_dataout <= wire_nil0iOOO_dataout AND NOT(niOO10i1i); + wire_nil0iO0O_dataout <= wire_nil0l11i_dataout AND NOT(niOO10i1i); + wire_nil0iO1i_dataout <= niOO10i1i AND NOT(niOO100OO); + wire_nil0iO1l_dataout <= wire_nil0iOlO_dataout AND NOT(niOO10i1i); + wire_nil0iO1O_dataout <= wire_nil0iOOi_dataout OR niOO10i1i; + wire_nil0iOi_dataout <= nii001l WHEN niOO0ll1l = '1' ELSE wire_nillOiO_dataout; + wire_nil0iOii_dataout <= wire_nil0l11l_dataout OR niOO10i1i; + wire_nil0iOil_dataout <= wire_nil0l11O_dataout OR niOO10i1i; + wire_nil0iOiO_dataout <= wire_nil0l10i_dataout AND NOT(niOO10i1i); + wire_nil0iOl_dataout <= nii001O WHEN niOO0ll1l = '1' ELSE wire_nillOli_dataout; + wire_nil0iOli_dataout <= wire_nil0l10l_dataout AND NOT(niOO10i1i); + wire_nil0iOll_dataout <= wire_nil0l10O_dataout AND NOT(niOO10i1i); + wire_nil0iOlO_dataout <= wire_nil0l1ii_dataout AND NOT(niOO10i1l); + wire_nil0iOO_dataout <= nii000i WHEN niOO0ll1l = '1' ELSE wire_nillOll_dataout; + wire_nil0iOOi_dataout <= wire_nil0l1il_dataout AND NOT(niOO10i1l); + wire_nil0iOOl_dataout <= wire_nil0l1iO_dataout OR niOO10i1l; + wire_nil0iOOO_dataout <= wire_nil0l1li_dataout AND NOT(niOO10i1l); + wire_nil0l00i_dataout <= wire_nil0l0Ol_dataout AND NOT(niOO10i0i); + wire_nil0l00l_dataout <= wire_nil0l0OO_dataout OR niOO10i0i; + wire_nil0l00O_dataout <= wire_nil0li1i_dataout AND NOT(niOO10i0i); + wire_nil0l01i_dataout <= wire_nil0l0ll_dataout AND NOT(niOO10i1O); + wire_nil0l01l_dataout <= wire_nil0l0lO_dataout OR niOO10i0i; + wire_nil0l01O_dataout <= wire_nil0l0Oi_dataout AND NOT(niOO10i0i); + wire_nil0l0i_dataout <= nii00il WHEN niOO0ll1l = '1' ELSE wire_nillOOO_dataout; + wire_nil0l0ii_dataout <= wire_nil0li1l_dataout AND NOT(niOO10i0i); + wire_nil0l0il_dataout <= wire_nil0li1O_dataout OR niOO10i0i; + wire_nil0l0iO_dataout <= wire_nil0li0i_dataout OR niOO10i0i; + wire_nil0l0l_dataout <= nii00iO WHEN niOO0ll1l = '1' ELSE wire_nilO11i_dataout; + wire_nil0l0li_dataout <= wire_nil0li0l_dataout AND NOT(niOO10i0i); + wire_nil0l0ll_dataout <= niOO10i0l AND NOT(niOO10i0i); + wire_nil0l0lO_dataout <= wire_nil0li0O_dataout AND NOT(niOO10i0l); + wire_nil0l0O_dataout <= nii00li WHEN niOO0ll1l = '1' ELSE wire_nilO11l_dataout; + wire_nil0l0Oi_dataout <= wire_nil0liii_dataout OR niOO10i0l; + wire_nil0l0Ol_dataout <= wire_nil0liil_dataout AND NOT(niOO10i0l); + wire_nil0l0OO_dataout <= wire_nil0liiO_dataout AND NOT(niOO10i0l); + wire_nil0l10i_dataout <= wire_nil0l1Ol_dataout AND NOT(niOO10i1l); + wire_nil0l10l_dataout <= wire_nil0l1OO_dataout AND NOT(niOO10i1l); + wire_nil0l10O_dataout <= wire_nil0l01i_dataout OR niOO10i1l; + wire_nil0l11i_dataout <= wire_nil0l1ll_dataout OR niOO10i1l; + wire_nil0l11l_dataout <= wire_nil0l1lO_dataout AND NOT(niOO10i1l); + wire_nil0l11O_dataout <= wire_nil0l1Oi_dataout OR niOO10i1l; + wire_nil0l1i_dataout <= nii000l WHEN niOO0ll1l = '1' ELSE wire_nillOlO_dataout; + wire_nil0l1ii_dataout <= wire_nil0l01l_dataout OR niOO10i1O; + wire_nil0l1il_dataout <= wire_nil0l01O_dataout AND NOT(niOO10i1O); + wire_nil0l1iO_dataout <= wire_nil0l00i_dataout OR niOO10i1O; + wire_nil0l1l_dataout <= nii000O WHEN niOO0ll1l = '1' ELSE wire_nillOOi_dataout; + wire_nil0l1li_dataout <= wire_nil0l00l_dataout OR niOO10i1O; + wire_nil0l1ll_dataout <= wire_nil0l00O_dataout AND NOT(niOO10i1O); + wire_nil0l1lO_dataout <= wire_nil0l0ii_dataout AND NOT(niOO10i1O); + wire_nil0l1O_dataout <= nii00ii WHEN niOO0ll1l = '1' ELSE wire_nillOOl_dataout; + wire_nil0l1Oi_dataout <= wire_nil0l0il_dataout OR niOO10i1O; + wire_nil0l1Ol_dataout <= wire_nil0l0iO_dataout AND NOT(niOO10i1O); + wire_nil0l1OO_dataout <= wire_nil0l0li_dataout OR niOO10i1O; + wire_nil0li0i_dataout <= wire_nil0liOi_dataout AND NOT(niOO10i0l); + wire_nil0li0l_dataout <= wire_nil0liOl_dataout AND NOT(niOO10i0l); + wire_nil0li0O_dataout <= wire_nil0liOO_dataout AND NOT(niOO10i0O); + wire_nil0li1i_dataout <= wire_nil0lili_dataout AND NOT(niOO10i0l); + wire_nil0li1l_dataout <= wire_nil0lill_dataout OR niOO10i0l; + wire_nil0li1O_dataout <= wire_nil0lilO_dataout OR niOO10i0l; + wire_nil0lii_dataout <= nii00ll WHEN niOO0ll1l = '1' ELSE wire_nilO11O_dataout; + wire_nil0liii_dataout <= wire_nil0ll1i_dataout AND NOT(niOO10i0O); + wire_nil0liil_dataout <= wire_nil0ll1l_dataout OR niOO10i0O; + wire_nil0liiO_dataout <= wire_nil0ll1O_dataout AND NOT(niOO10i0O); + wire_nil0lil_dataout <= nii00lO WHEN niOO0ll1l = '1' ELSE wire_nilO10i_dataout; + wire_nil0lili_dataout <= wire_nil0ll0i_dataout OR niOO10i0O; + wire_nil0lill_dataout <= wire_nil0ll0l_dataout AND NOT(niOO10i0O); + wire_nil0lilO_dataout <= wire_nil0ll0O_dataout OR niOO10i0O; + wire_nil0liO_dataout <= nii00Oi WHEN niOO0ll1l = '1' ELSE wire_nilO10l_dataout; + wire_nil0liOi_dataout <= wire_nil0llii_dataout AND NOT(niOO10i0O); + wire_nil0liOl_dataout <= wire_nil0llil_dataout OR niOO10i0O; + wire_nil0liOO_dataout <= wire_nil0lliO_dataout OR niOO10iii; + wire_nil0ll0i_dataout <= wire_nil0llOi_dataout AND NOT(niOO10iii); + wire_nil0ll0l_dataout <= wire_nil0llOl_dataout AND NOT(niOO10iii); + wire_nil0ll0O_dataout <= wire_nil0llOO_dataout OR niOO10iii; + wire_nil0ll1i_dataout <= wire_nil0llli_dataout AND NOT(niOO10iii); + wire_nil0ll1l_dataout <= wire_nil0llll_dataout OR niOO10iii; + wire_nil0ll1O_dataout <= wire_nil0lllO_dataout OR niOO10iii; + wire_nil0lli_dataout <= nii00Ol WHEN niOO0ll1l = '1' ELSE wire_nilO10O_dataout; + wire_nil0llii_dataout <= wire_nil0lO1i_dataout OR niOO10iii; + wire_nil0llil_dataout <= wire_nil0lO1l_dataout AND NOT(niOO10iii); + wire_nil0lliO_dataout <= wire_nil0lO1O_dataout OR niOO10iil; + wire_nil0lll_dataout <= nii00OO WHEN niOO0ll1l = '1' ELSE wire_nilO1ii_dataout; + wire_nil0llli_dataout <= wire_nil0lO0i_dataout AND NOT(niOO10iil); + wire_nil0llll_dataout <= wire_nil0lO0l_dataout AND NOT(niOO10iil); + wire_nil0lllO_dataout <= wire_nil0lO0O_dataout OR niOO10iil; + wire_nil0llO_dataout <= nii0i1i WHEN niOO0ll1l = '1' ELSE wire_nilO1il_dataout; + wire_nil0llOi_dataout <= wire_nil0lOii_dataout AND NOT(niOO10iil); + wire_nil0llOl_dataout <= wire_nil0lOil_dataout AND NOT(niOO10iil); + wire_nil0llOO_dataout <= wire_nil0lOiO_dataout AND NOT(niOO10iil); + wire_nil0lO0i_dataout <= wire_nil0lOOi_dataout OR niOO10iiO; + wire_nil0lO0l_dataout <= wire_nil0lOOl_dataout AND NOT(niOO10iiO); + wire_nil0lO0O_dataout <= wire_nil0lOOO_dataout AND NOT(niOO10iiO); + wire_nil0lO1i_dataout <= wire_nil0lOli_dataout OR niOO10iil; + wire_nil0lO1l_dataout <= wire_nil0lOll_dataout AND NOT(niOO10iil); + wire_nil0lO1O_dataout <= wire_nil0lOlO_dataout OR niOO10iiO; + wire_nil0lOi_dataout <= nii0i1l WHEN niOO0ll1l = '1' ELSE wire_nilO1iO_dataout; + wire_nil0lOii_dataout <= wire_nil0O11i_dataout OR niOO10iiO; + wire_nil0lOil_dataout <= wire_nil0O11l_dataout AND NOT(niOO10iiO); + wire_nil0lOiO_dataout <= wire_nil0O11O_dataout OR niOO10iiO; + wire_nil0lOl_dataout <= nii0i1O WHEN niOO0ll1l = '1' ELSE wire_nilO1li_dataout; + wire_nil0lOli_dataout <= wire_nil0O10i_dataout OR niOO10iiO; + wire_nil0lOll_dataout <= wire_nil0O10l_dataout OR niOO10iiO; + wire_nil0lOlO_dataout <= wire_nil0O10O_dataout AND NOT(niOO10ili); + wire_nil0lOO_dataout <= nii0i0i WHEN niOO0ll1l = '1' ELSE wire_nilO1ll_dataout; + wire_nil0lOOi_dataout <= wire_nil0O1ii_dataout AND NOT(niOO10ili); + wire_nil0lOOl_dataout <= wire_nil0O1il_dataout OR niOO10ili; + wire_nil0lOOO_dataout <= wire_nil0O1iO_dataout OR niOO10ili; + wire_nil0O00i_dataout <= wire_w_lg_niOO10iOi9182w(0) OR niOO10ilO; + wire_nil0O00l_dataout <= wire_nil0O0li_dataout AND NOT(niOO10ilO); + wire_nil0O00O_dataout <= wire_nil0O0ll_dataout OR niOO10ilO; + wire_nil0O01i_dataout <= wire_nil0O0il_dataout OR niOO10ilO; + wire_nil0O01l_dataout <= wire_nil0O0li_dataout OR niOO10ilO; + wire_nil0O01O_dataout <= wire_nil0O0iO_dataout OR niOO10ilO; + wire_nil0O0i_dataout <= nii0iil WHEN niOO0ll1l = '1' ELSE wire_nilO1OO_dataout; + wire_nil0O0ii_dataout <= niOO10iOi AND NOT(niOO10ilO); + wire_nil0O0il_dataout <= wire_nil0O0lO_dataout AND NOT(niOO10iOi); + wire_nil0O0iO_dataout <= wire_nil0O0Oi_dataout AND NOT(niOO10iOi); + wire_nil0O0l_dataout <= nii0iiO WHEN niOO0ll1l = '1' ELSE wire_nilO01i_dataout; + wire_nil0O0li_dataout <= wire_w_lg_niOO10iOl9024w(0) AND NOT(niOO10iOi); + wire_nil0O0ll_dataout <= niOO10iOl AND NOT(niOO10iOi); + wire_nil0O0lO_dataout <= wire_w_lg_niOO10iOO9023w(0) OR niOO10iOl; + wire_nil0O0O_dataout <= nii0ili WHEN niOO0ll1l = '1' ELSE wire_nilO01l_dataout; + wire_nil0O0Oi_dataout <= niOO10iOO AND NOT(niOO10iOl); + wire_nil0O10i_dataout <= wire_nil0O1Oi_dataout AND NOT(niOO10ili); + wire_nil0O10l_dataout <= wire_nil0O1Ol_dataout OR niOO10ili; + wire_nil0O10O_dataout <= wire_nil0O1OO_dataout OR niOO10ill; + wire_nil0O11i_dataout <= wire_nil0O1li_dataout AND NOT(niOO10ili); + wire_nil0O11l_dataout <= wire_nil0O1ll_dataout AND NOT(niOO10ili); + wire_nil0O11O_dataout <= wire_nil0O1lO_dataout AND NOT(niOO10ili); + wire_nil0O1i_dataout <= nii0i0l WHEN niOO0ll1l = '1' ELSE wire_nilO1lO_dataout; + wire_nil0O1ii_dataout <= wire_nil0O01i_dataout AND NOT(niOO10ill); + wire_nil0O1il_dataout <= wire_nil0O01l_dataout AND NOT(niOO10ill); + wire_nil0O1iO_dataout <= wire_nil0O01O_dataout OR niOO10ill; + wire_nil0O1l_dataout <= nii0i0O WHEN niOO0ll1l = '1' ELSE wire_nilO1Oi_dataout; + wire_nil0O1li_dataout <= wire_nil0O00i_dataout AND NOT(niOO10ill); + wire_nil0O1ll_dataout <= wire_w_lg_niOO10ilO9183w(0) OR niOO10ill; + wire_nil0O1lO_dataout <= wire_nil0O00l_dataout AND NOT(niOO10ill); + wire_nil0O1O_dataout <= nii0iii WHEN niOO0ll1l = '1' ELSE wire_nilO1Ol_dataout; + wire_nil0O1Oi_dataout <= wire_nil0O00O_dataout OR niOO10ill; + wire_nil0O1Ol_dataout <= wire_nil0O0ii_dataout AND NOT(niOO10ill); + wire_nil0O1OO_dataout <= wire_nil0O0ll_dataout AND NOT(niOO10ilO); + wire_nil0Oii_dataout <= nii0ill WHEN niOO0ll1l = '1' ELSE wire_nilO01O_dataout; + wire_nil0Oil_dataout <= nii0ilO WHEN niOO0ll1l = '1' ELSE wire_nilO00i_dataout; + wire_nil0OiO_dataout <= nii0iOi WHEN niOO0ll1l = '1' ELSE wire_nilO00l_dataout; + wire_nil0Oli_dataout <= nii0iOl WHEN niOO0ll1l = '1' ELSE wire_nilO00O_dataout; + wire_nil0Oll_dataout <= nii0iOO WHEN niOO0ll1l = '1' ELSE wire_nilO0ii_dataout; + wire_nil0OlO_dataout <= nii0l1i WHEN niOO0ll1l = '1' ELSE wire_nilO0il_dataout; + wire_nil0OOi_dataout <= nii0l1l WHEN niOO0ll1l = '1' ELSE wire_nilO0iO_dataout; + wire_nil0OOl_dataout <= nii0l1O WHEN niOO0ll1l = '1' ELSE wire_nilO0li_dataout; + wire_nil0OOO_dataout <= nii0l0i WHEN niOO0ll1l = '1' ELSE wire_nilO0ll_dataout; + wire_nil1000i_dataout <= wire_nil100lO_o(10) WHEN niOO10l1O = '1' ELSE nil11i1O; + wire_nil1000l_dataout <= wire_nil100lO_o(11) WHEN niOO10l1O = '1' ELSE nil11i0i; + wire_nil1000O_dataout <= wire_nil100lO_o(12) WHEN niOO10l1O = '1' ELSE nil11i0l; + wire_nil1001i_dataout <= wire_nil100lO_o(7) WHEN niOO10l1O = '1' ELSE nil110OO; + wire_nil1001l_dataout <= wire_nil100lO_o(8) WHEN niOO10l1O = '1' ELSE nil11i1i; + wire_nil1001O_dataout <= wire_nil100lO_o(9) WHEN niOO10l1O = '1' ELSE nil11i1l; + wire_nil100i_dataout <= wire_nil1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil100ii_dataout <= wire_nil100lO_o(13) WHEN niOO10l1O = '1' ELSE nil11i0O; + wire_nil100il_dataout <= wire_nil100lO_o(14) WHEN niOO10l1O = '1' ELSE nil11iii; + wire_nil100iO_dataout <= nil11iil AND NOT(niOO10l1O); + wire_nil100l_dataout <= wire_nil1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil100O_dataout <= wire_nil1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil100Oi_dataout <= wire_nil10iii_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil100Ol_dataout <= wire_nil10iil_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil100OO_dataout <= wire_nil10iiO_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil1010i_dataout <= wire_nil100lO_o(14) WHEN niOO10l0O = '1' ELSE wire_nil100iO_dataout; + wire_nil1010l_dataout <= wire_nil100li_o(6) WHEN niOO10l1O = '1' ELSE nil1100i; + wire_nil1010O_dataout <= wire_nil100li_o(7) WHEN niOO10l1O = '1' ELSE nil1100l; + wire_nil1011i_dataout <= wire_nil100lO_o(11) WHEN niOO10l0O = '1' ELSE wire_nil1000O_dataout; + wire_nil1011l_dataout <= wire_nil100lO_o(12) WHEN niOO10l0O = '1' ELSE wire_nil100ii_dataout; + wire_nil1011O_dataout <= wire_nil100lO_o(13) WHEN niOO10l0O = '1' ELSE wire_nil100il_dataout; + wire_nil101i_dataout <= wire_nil1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil101ii_dataout <= wire_nil100li_o(8) WHEN niOO10l1O = '1' ELSE nil1100O; + wire_nil101il_dataout <= wire_nil100li_o(9) WHEN niOO10l1O = '1' ELSE nil110ii; + wire_nil101iO_dataout <= wire_nil100li_o(10) WHEN niOO10l1O = '1' ELSE nil110il; + wire_nil101l_dataout <= wire_nil1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil101li_dataout <= wire_nil100li_o(11) WHEN niOO10l1O = '1' ELSE nil110iO; + wire_nil101ll_dataout <= wire_nil100li_o(12) WHEN niOO10l1O = '1' ELSE nil110li; + wire_nil101lO_dataout <= wire_nil100li_o(13) WHEN niOO10l1O = '1' ELSE nil110ll; + wire_nil101O_dataout <= wire_nil1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil101Oi_dataout <= wire_nil100li_o(14) WHEN niOO10l1O = '1' ELSE nil110lO; + wire_nil101Ol_dataout <= nil110Oi AND NOT(niOO10l1O); + wire_nil101OO_dataout <= wire_nil100lO_o(6) WHEN niOO10l1O = '1' ELSE nil110Ol; + wire_nil10i0i_dataout <= wire_nil10iOi_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil10i0l_dataout <= wire_nil10iOl_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil10i0O_dataout <= wire_nilOO01i_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil10i1i_dataout <= wire_nil10ili_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil10i1l_dataout <= wire_nil10ill_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil10i1O_dataout <= wire_nil10ilO_dataout AND NOT(wire_niO111il_w_lg_dataout9224w(0)); + wire_nil10ii_dataout <= wire_nil1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil10iii_dataout <= wire_nlOiiillO_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10iil_dataout <= wire_nlOiiilOi_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10iiO_dataout <= wire_nlOiiilOl_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10il_dataout <= wire_nil1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil10ili_dataout <= wire_nlOiiilOO_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10ill_dataout <= wire_nlOiiiO1i_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10ilO_dataout <= wire_nlOiiiO1l_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10iO_dataout <= wire_nil1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil10iOi_dataout <= wire_nlOiiiO1O_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10iOl_dataout <= wire_nlOiiiO0i_dataout AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10iOO_dataout <= wire_nil10liO_o(0) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10l0i_dataout <= wire_nil10liO_o(4) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10l0l_dataout <= wire_nil10liO_o(5) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10l0O_dataout <= wire_nil10liO_o(6) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10l1i_dataout <= wire_nil10liO_o(1) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10l1l_dataout <= wire_nil10liO_o(2) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10l1O_dataout <= wire_nil10liO_o(3) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10li_dataout <= wire_nil1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil10lii_dataout <= wire_nil10liO_o(7) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10lil_dataout <= wire_nil10liO_o(8) AND wire_nilOO01i_w_lg_dataout9215w(0); + wire_nil10ll_dataout <= wire_nil1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil10lO_dataout <= niii0Oi WHEN niOO0ll1l = '1' ELSE wire_nililil_dataout; + wire_nil10Oi_dataout <= niii0Ol WHEN niOO0ll1l = '1' ELSE wire_nililiO_dataout; + wire_nil10Ol_dataout <= niii0OO WHEN niOO0ll1l = '1' ELSE wire_nililli_dataout; + wire_nil10OO_dataout <= niiii1i WHEN niOO0ll1l = '1' ELSE wire_nililll_dataout; + wire_nil1101i_dataout <= k_vc0(25) WHEN niOO11ill = '1' ELSE k_vc0(41); + wire_nil1101l_dataout <= k_vc0(26) WHEN niOO11ill = '1' ELSE k_vc0(42); + wire_nil1101O_dataout <= k_vc0(27) WHEN niOO11ill = '1' ELSE k_vc0(43); + wire_nil110i_dataout <= wire_nil1l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil110l_dataout <= wire_nil1lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil110O_dataout <= wire_nil1lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil1110i_dataout <= k_vc0(1) WHEN niOO11ili = '1' ELSE wire_nil111lO_dataout; + wire_nil1110l_dataout <= k_vc0(2) WHEN niOO11ili = '1' ELSE wire_nil111Oi_dataout; + wire_nil1110O_dataout <= k_vc0(3) WHEN niOO11ili = '1' ELSE wire_nil111Ol_dataout; + wire_nil1111i_dataout <= k_vc1(42) WHEN niOO11iiO = '1' ELSE wire_nil111iO_dataout; + wire_nil1111l_dataout <= k_vc1(43) WHEN niOO11iiO = '1' ELSE wire_nil111li_dataout; + wire_nil1111O_dataout <= k_vc0(0) WHEN niOO11ili = '1' ELSE wire_nil111ll_dataout; + wire_nil111i_dataout <= wire_nil1l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil111ii_dataout <= k_vc0(4) WHEN niOO11ili = '1' ELSE wire_nil111OO_dataout; + wire_nil111il_dataout <= k_vc0(5) WHEN niOO11ili = '1' ELSE wire_nil1101i_dataout; + wire_nil111iO_dataout <= k_vc0(6) WHEN niOO11ili = '1' ELSE wire_nil1101l_dataout; + wire_nil111l_dataout <= wire_nil1l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil111li_dataout <= k_vc0(7) WHEN niOO11ili = '1' ELSE wire_nil1101O_dataout; + wire_nil111ll_dataout <= k_vc0(20) WHEN niOO11ill = '1' ELSE k_vc0(36); + wire_nil111lO_dataout <= k_vc0(21) WHEN niOO11ill = '1' ELSE k_vc0(37); + wire_nil111O_dataout <= wire_nil1l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil111Oi_dataout <= k_vc0(22) WHEN niOO11ill = '1' ELSE k_vc0(38); + wire_nil111Ol_dataout <= k_vc0(23) WHEN niOO11ill = '1' ELSE k_vc0(39); + wire_nil111OO_dataout <= k_vc0(24) WHEN niOO11ill = '1' ELSE k_vc0(40); + wire_nil11ii_dataout <= wire_nil1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11il_dataout <= wire_nil1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11ili_dataout <= wire_nil11lOO_dataout OR wire_niO01O0O_dataout; + wire_nil11ill_dataout <= wire_nil11O1i_dataout OR wire_niO01O0O_dataout; + wire_nil11ilO_dataout <= wire_nil11O1l_dataout OR wire_niO01O0O_dataout; + wire_nil11iO_dataout <= wire_nil1lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11iOi_dataout <= wire_nil11O1O_dataout OR wire_niO01O0O_dataout; + wire_nil11iOl_dataout <= wire_nil11O0i_dataout OR wire_niO01O0O_dataout; + wire_nil11iOO_dataout <= wire_nil11O0l_dataout OR wire_niO01O0O_dataout; + wire_nil11l0i_dataout <= wire_nil11OiO_dataout OR wire_niO01O0O_dataout; + wire_nil11l0l_dataout <= wire_nil11Oli_dataout OR wire_niO01O0O_dataout; + wire_nil11l0O_dataout <= wire_nil11Oll_dataout OR wire_niO01O0O_dataout; + wire_nil11l1i_dataout <= wire_nil11O0O_dataout OR wire_niO01O0O_dataout; + wire_nil11l1l_dataout <= wire_nil11Oii_dataout OR wire_niO01O0O_dataout; + wire_nil11l1O_dataout <= wire_nil11Oil_dataout OR wire_niO01O0O_dataout; + wire_nil11li_dataout <= wire_nil1llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11lii_dataout <= wire_nil11OlO_dataout OR wire_niO01O0O_dataout; + wire_nil11lil_dataout <= wire_nil11OOi_dataout OR wire_niO01O0O_dataout; + wire_nil11liO_dataout <= wire_nil11OOl_dataout OR wire_niO01O0O_dataout; + wire_nil11ll_dataout <= wire_nil1lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11lli_dataout <= wire_nil11OOO_dataout OR wire_niO01O0O_dataout; + wire_nil11lll_dataout <= wire_nil1011i_dataout OR wire_niO01O0O_dataout; + wire_nil11llO_dataout <= wire_nil1011l_dataout OR wire_niO01O0O_dataout; + wire_nil11lO_dataout <= wire_nil1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11lOi_dataout <= wire_nil1011O_dataout OR wire_niO01O0O_dataout; + wire_nil11lOl_dataout <= wire_nil1010i_dataout OR wire_niO01O0O_dataout; + wire_nil11lOO_dataout <= wire_nil100li_o(5) WHEN niOO10l0O = '1' ELSE wire_nil1010l_dataout; + wire_nil11O0i_dataout <= wire_nil100li_o(9) WHEN niOO10l0O = '1' ELSE wire_nil101iO_dataout; + wire_nil11O0l_dataout <= wire_nil100li_o(10) WHEN niOO10l0O = '1' ELSE wire_nil101li_dataout; + wire_nil11O0O_dataout <= wire_nil100li_o(11) WHEN niOO10l0O = '1' ELSE wire_nil101ll_dataout; + wire_nil11O1i_dataout <= wire_nil100li_o(6) WHEN niOO10l0O = '1' ELSE wire_nil1010O_dataout; + wire_nil11O1l_dataout <= wire_nil100li_o(7) WHEN niOO10l0O = '1' ELSE wire_nil101ii_dataout; + wire_nil11O1O_dataout <= wire_nil100li_o(8) WHEN niOO10l0O = '1' ELSE wire_nil101il_dataout; + wire_nil11Oi_dataout <= wire_nil1lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11Oii_dataout <= wire_nil100li_o(12) WHEN niOO10l0O = '1' ELSE wire_nil101lO_dataout; + wire_nil11Oil_dataout <= wire_nil100li_o(13) WHEN niOO10l0O = '1' ELSE wire_nil101Oi_dataout; + wire_nil11OiO_dataout <= wire_nil100li_o(14) WHEN niOO10l0O = '1' ELSE wire_nil101Ol_dataout; + wire_nil11Ol_dataout <= wire_nil1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11Oli_dataout <= wire_nil100lO_o(5) WHEN niOO10l0O = '1' ELSE wire_nil101OO_dataout; + wire_nil11Oll_dataout <= wire_nil100lO_o(6) WHEN niOO10l0O = '1' ELSE wire_nil1001i_dataout; + wire_nil11OlO_dataout <= wire_nil100lO_o(7) WHEN niOO10l0O = '1' ELSE wire_nil1001l_dataout; + wire_nil11OO_dataout <= wire_nil1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nil11OOi_dataout <= wire_nil100lO_o(8) WHEN niOO10l0O = '1' ELSE wire_nil1001O_dataout; + wire_nil11OOl_dataout <= wire_nil100lO_o(9) WHEN niOO10l0O = '1' ELSE wire_nil1000i_dataout; + wire_nil11OOO_dataout <= wire_nil100lO_o(10) WHEN niOO10l0O = '1' ELSE wire_nil1000l_dataout; + wire_nil1i00i_dataout <= wire_nili1O1i_dataout OR wire_niO01O0O_dataout; + wire_nil1i00l_dataout <= wire_nil1ii1O_dataout OR wire_niO01O0O_dataout; + wire_nil1i00O_dataout <= wire_nil1ii0i_dataout OR wire_niO01O0O_dataout; + wire_nil1i01i_dataout <= wire_nili1lOi_dataout OR wire_niO01O0O_dataout; + wire_nil1i01l_dataout <= wire_nili1lOl_dataout OR wire_niO01O0O_dataout; + wire_nil1i01O_dataout <= wire_nili1lOO_dataout OR wire_niO01O0O_dataout; + wire_nil1i0i_dataout <= niiii0l WHEN niOO0ll1l = '1' ELSE wire_nililOO_dataout; + wire_nil1i0ii_dataout <= wire_nil1ii0l_dataout OR wire_niO01O0O_dataout; + wire_nil1i0il_dataout <= wire_nil1ii0O_dataout OR wire_niO01O0O_dataout; + wire_nil1i0iO_dataout <= wire_nil1iiii_dataout OR wire_niO01O0O_dataout; + wire_nil1i0l_dataout <= niiii0O WHEN niOO0ll1l = '1' ELSE wire_niliO1i_dataout; + wire_nil1i0li_dataout <= wire_nil1iiil_dataout OR wire_niO01O0O_dataout; + wire_nil1i0ll_dataout <= wire_nil1iiiO_dataout OR wire_niO01O0O_dataout; + wire_nil1i0lO_dataout <= wire_nil1iili_dataout OR wire_niO01O0O_dataout; + wire_nil1i0O_dataout <= niiiiii WHEN niOO0ll1l = '1' ELSE wire_niliO1l_dataout; + wire_nil1i0Oi_dataout <= wire_nil1iill_dataout OR wire_niO01O0O_dataout; + wire_nil1i0Ol_dataout <= wire_nil1iilO_dataout OR wire_niO01O0O_dataout; + wire_nil1i0OO_dataout <= wire_nil1iiOi_dataout OR wire_niO01O0O_dataout; + wire_nil1i10O_dataout <= wire_nili1l1O_dataout OR wire_niO01O0O_dataout; + wire_nil1i1i_dataout <= niiii1l WHEN niOO0ll1l = '1' ELSE wire_nilillO_dataout; + wire_nil1i1ii_dataout <= wire_nili1l0i_dataout OR wire_niO01O0O_dataout; + wire_nil1i1il_dataout <= wire_nili1l0l_dataout OR wire_niO01O0O_dataout; + wire_nil1i1iO_dataout <= wire_nili1l0O_dataout OR wire_niO01O0O_dataout; + wire_nil1i1l_dataout <= niiii1O WHEN niOO0ll1l = '1' ELSE wire_nililOi_dataout; + wire_nil1i1li_dataout <= wire_nili1lii_dataout OR wire_niO01O0O_dataout; + wire_nil1i1ll_dataout <= wire_nili1lil_dataout OR wire_niO01O0O_dataout; + wire_nil1i1lO_dataout <= wire_nili1liO_dataout OR wire_niO01O0O_dataout; + wire_nil1i1O_dataout <= niiii0i WHEN niOO0ll1l = '1' ELSE wire_nililOl_dataout; + wire_nil1i1Oi_dataout <= wire_nili1lli_dataout OR wire_niO01O0O_dataout; + wire_nil1i1Ol_dataout <= wire_nili1lll_dataout OR wire_niO01O0O_dataout; + wire_nil1i1OO_dataout <= wire_nili1llO_dataout OR wire_niO01O0O_dataout; + wire_nil1ii0i_dataout <= wire_nil1il1l_dataout OR niOO11OOO; + wire_nil1ii0l_dataout <= wire_nil1il1O_dataout OR niOO11OOO; + wire_nil1ii0O_dataout <= wire_nil1il0i_dataout OR niOO11OOO; + wire_nil1ii1i_dataout <= wire_nil1iiOl_dataout OR wire_niO01O0O_dataout; + wire_nil1ii1l_dataout <= wire_nil1iiOO_dataout OR wire_niO01O0O_dataout; + wire_nil1ii1O_dataout <= wire_nil1il1i_dataout OR niOO11OOO; + wire_nil1iii_dataout <= niiiiil WHEN niOO0ll1l = '1' ELSE wire_niliO1O_dataout; + wire_nil1iiii_dataout <= wire_nil1il0l_dataout AND NOT(niOO11OOO); + wire_nil1iiil_dataout <= wire_nil1il0O_dataout OR niOO11OOO; + wire_nil1iiiO_dataout <= wire_nil1ilii_dataout AND NOT(niOO11OOO); + wire_nil1iil_dataout <= niiiiiO WHEN niOO0ll1l = '1' ELSE wire_niliO0i_dataout; + wire_nil1iili_dataout <= wire_nil1ilil_dataout AND NOT(niOO11OOO); + wire_nil1iill_dataout <= wire_nil1iliO_dataout AND NOT(niOO11OOO); + wire_nil1iilO_dataout <= wire_nil1illi_dataout AND NOT(niOO11OOO); + wire_nil1iiO_dataout <= niiiili WHEN niOO0ll1l = '1' ELSE wire_niliO0l_dataout; + wire_nil1iiOi_dataout <= wire_nil1illl_dataout AND NOT(niOO11OOO); + wire_nil1iiOl_dataout <= wire_nil1illO_dataout AND NOT(niOO11OOO); + wire_nil1iiOO_dataout <= wire_nil1ilOi_dataout OR niOO11OOO; + wire_nil1il0i_dataout <= wire_nil1iO1l_dataout AND NOT(niOO1011i); + wire_nil1il0l_dataout <= wire_nil1iO1O_dataout AND NOT(niOO1011i); + wire_nil1il0O_dataout <= wire_nil1iO0i_dataout OR niOO1011i; + wire_nil1il1i_dataout <= wire_nil1ilOl_dataout OR niOO1011i; + wire_nil1il1l_dataout <= wire_nil1ilOO_dataout AND NOT(niOO1011i); + wire_nil1il1O_dataout <= wire_nil1iO1i_dataout AND NOT(niOO1011i); + wire_nil1ili_dataout <= niiiill WHEN niOO0ll1l = '1' ELSE wire_niliO0O_dataout; + wire_nil1ilii_dataout <= wire_nil1iO0l_dataout AND NOT(niOO1011i); + wire_nil1ilil_dataout <= wire_nil1iO0O_dataout AND NOT(niOO1011i); + wire_nil1iliO_dataout <= wire_nil1iOii_dataout AND NOT(niOO1011i); + wire_nil1ill_dataout <= niiiilO WHEN niOO0ll1l = '1' ELSE wire_niliOii_dataout; + wire_nil1illi_dataout <= wire_nil1iOil_dataout AND NOT(niOO1011i); + wire_nil1illl_dataout <= wire_nil1iOiO_dataout AND NOT(niOO1011i); + wire_nil1illO_dataout <= wire_nil1iOli_dataout OR niOO1011i; + wire_nil1ilO_dataout <= niiiiOi WHEN niOO0ll1l = '1' ELSE wire_niliOil_dataout; + wire_nil1ilOi_dataout <= wire_nil1iOll_dataout AND NOT(niOO1011i); + wire_nil1ilOl_dataout <= wire_nil1iOlO_dataout AND NOT(niOO1011l); + wire_nil1ilOO_dataout <= wire_nil1iOOi_dataout OR niOO1011l; + wire_nil1iO0i_dataout <= wire_nil1l11l_dataout AND NOT(niOO1011l); + wire_nil1iO0l_dataout <= wire_nil1l11O_dataout AND NOT(niOO1011l); + wire_nil1iO0O_dataout <= wire_nil1l10i_dataout AND NOT(niOO1011l); + wire_nil1iO1i_dataout <= wire_nil1iOOl_dataout AND NOT(niOO1011l); + wire_nil1iO1l_dataout <= wire_nil1iOOO_dataout OR niOO1011l; + wire_nil1iO1O_dataout <= wire_nil1l11i_dataout OR niOO1011l; + wire_nil1iOi_dataout <= niiiiOl WHEN niOO0ll1l = '1' ELSE wire_niliOiO_dataout; + wire_nil1iOii_dataout <= wire_nil1l10l_dataout AND NOT(niOO1011l); + wire_nil1iOil_dataout <= wire_nil1l10O_dataout AND NOT(niOO1011l); + wire_nil1iOiO_dataout <= wire_nil1l1ii_dataout OR niOO1011l; + wire_nil1iOl_dataout <= niiiiOO WHEN niOO0ll1l = '1' ELSE wire_niliOli_dataout; + wire_nil1iOli_dataout <= wire_nil1l1il_dataout AND NOT(niOO1011l); + wire_nil1iOll_dataout <= wire_nil1l1iO_dataout AND NOT(niOO1011l); + wire_nil1iOlO_dataout <= wire_nil1l1li_dataout AND NOT(niOO1011O); + wire_nil1iOO_dataout <= niiil1i WHEN niOO0ll1l = '1' ELSE wire_niliOll_dataout; + wire_nil1iOOi_dataout <= wire_nil1l1ll_dataout OR niOO1011O; + wire_nil1iOOl_dataout <= wire_nil1l1lO_dataout OR niOO1011O; + wire_nil1iOOO_dataout <= wire_nil1l1Oi_dataout AND NOT(niOO1011O); + wire_nil1l00i_dataout <= wire_nil1li1l_dataout AND NOT(niOO1010i); + wire_nil1l00l_dataout <= wire_nil1li1O_dataout AND NOT(niOO1010i); + wire_nil1l00O_dataout <= wire_nil1li0i_dataout OR niOO1010i; + wire_nil1l01i_dataout <= wire_nil1l0Ol_dataout AND NOT(niOO1010i); + wire_nil1l01l_dataout <= wire_nil1l0OO_dataout AND NOT(niOO1010i); + wire_nil1l01O_dataout <= wire_nil1li1i_dataout AND NOT(niOO1010i); + wire_nil1l0i_dataout <= niiil0l WHEN niOO0ll1l = '1' ELSE wire_niliOOO_dataout; + wire_nil1l0ii_dataout <= wire_nil1li0l_dataout AND NOT(niOO1010i); + wire_nil1l0il_dataout <= wire_nil1li0O_dataout OR niOO1010l; + wire_nil1l0iO_dataout <= wire_nil1liii_dataout AND NOT(niOO1010l); + wire_nil1l0l_dataout <= niiil0O WHEN niOO0ll1l = '1' ELSE wire_nill11i_dataout; + wire_nil1l0li_dataout <= wire_nil1liil_dataout AND NOT(niOO1010l); + wire_nil1l0ll_dataout <= wire_nil1liiO_dataout AND NOT(niOO1010l); + wire_nil1l0lO_dataout <= wire_nil1lili_dataout AND NOT(niOO1010l); + wire_nil1l0O_dataout <= niiilii WHEN niOO0ll1l = '1' ELSE wire_nill11l_dataout; + wire_nil1l0Oi_dataout <= wire_nil1lill_dataout OR niOO1010l; + wire_nil1l0Ol_dataout <= wire_nil1lilO_dataout AND NOT(niOO1010l); + wire_nil1l0OO_dataout <= wire_nil1liOi_dataout AND NOT(niOO1010l); + wire_nil1l10i_dataout <= wire_nil1l01l_dataout AND NOT(niOO1011O); + wire_nil1l10l_dataout <= wire_nil1l01O_dataout AND NOT(niOO1011O); + wire_nil1l10O_dataout <= wire_nil1l00i_dataout OR niOO1011O; + wire_nil1l11i_dataout <= wire_nil1l1Ol_dataout OR niOO1011O; + wire_nil1l11l_dataout <= wire_nil1l1OO_dataout AND NOT(niOO1011O); + wire_nil1l11O_dataout <= wire_nil1l01i_dataout AND NOT(niOO1011O); + wire_nil1l1i_dataout <= niiil1l WHEN niOO0ll1l = '1' ELSE wire_niliOlO_dataout; + wire_nil1l1ii_dataout <= wire_nil1l00l_dataout AND NOT(niOO1011O); + wire_nil1l1il_dataout <= wire_nil1l00O_dataout AND NOT(niOO1011O); + wire_nil1l1iO_dataout <= wire_nil1l0ii_dataout AND NOT(niOO1011O); + wire_nil1l1l_dataout <= niiil1O WHEN niOO0ll1l = '1' ELSE wire_niliOOi_dataout; + wire_nil1l1li_dataout <= wire_nil1l0il_dataout OR niOO1010i; + wire_nil1l1ll_dataout <= wire_nil1l0iO_dataout OR niOO1010i; + wire_nil1l1lO_dataout <= wire_nil1l0li_dataout OR niOO1010i; + wire_nil1l1O_dataout <= niiil0i WHEN niOO0ll1l = '1' ELSE wire_niliOOl_dataout; + wire_nil1l1Oi_dataout <= wire_nil1l0ll_dataout OR niOO1010i; + wire_nil1l1Ol_dataout <= wire_nil1l0lO_dataout AND NOT(niOO1010i); + wire_nil1l1OO_dataout <= wire_nil1l0Oi_dataout OR niOO1010i; + wire_nil1li0i_dataout <= wire_nil1ll1l_dataout AND NOT(niOO1010l); + wire_nil1li0l_dataout <= wire_nil1ll1O_dataout AND NOT(niOO1010l); + wire_nil1li0O_dataout <= wire_nil1ll0i_dataout AND NOT(niOO1010O); + wire_nil1li1i_dataout <= wire_nil1liOl_dataout AND NOT(niOO1010l); + wire_nil1li1l_dataout <= wire_nil1liOO_dataout AND NOT(niOO1010l); + wire_nil1li1O_dataout <= wire_nil1ll1i_dataout OR niOO1010l; + wire_nil1lii_dataout <= niiilil WHEN niOO0ll1l = '1' ELSE wire_nill11O_dataout; + wire_nil1liii_dataout <= wire_nil1ll0l_dataout OR niOO1010O; + wire_nil1liil_dataout <= wire_nil1ll0O_dataout AND NOT(niOO1010O); + wire_nil1liiO_dataout <= wire_nil1llii_dataout OR niOO1010O; + wire_nil1lil_dataout <= niiiliO WHEN niOO0ll1l = '1' ELSE wire_nill10i_dataout; + wire_nil1lili_dataout <= wire_nil1llil_dataout OR niOO1010O; + wire_nil1lill_dataout <= wire_nil1lliO_dataout AND NOT(niOO1010O); + wire_nil1lilO_dataout <= wire_nil1llli_dataout AND NOT(niOO1010O); + wire_nil1liO_dataout <= niiilli WHEN niOO0ll1l = '1' ELSE wire_nill10l_dataout; + wire_nil1liOi_dataout <= wire_nil1llll_dataout AND NOT(niOO1010O); + wire_nil1liOl_dataout <= wire_nil1lllO_dataout AND NOT(niOO1010O); + wire_nil1liOO_dataout <= wire_nil1llOi_dataout OR niOO1010O; + wire_nil1ll0i_dataout <= wire_nil1lO1l_dataout AND NOT(niOO101ii); + wire_nil1ll0l_dataout <= wire_nil1lO1O_dataout OR niOO101ii; + wire_nil1ll0O_dataout <= wire_nil1lO0i_dataout OR niOO101ii; + wire_nil1ll1i_dataout <= wire_nil1llOl_dataout AND NOT(niOO1010O); + wire_nil1ll1l_dataout <= wire_nil1llOO_dataout AND NOT(niOO1010O); + wire_nil1ll1O_dataout <= wire_nil1lO1i_dataout AND NOT(niOO1010O); + wire_nil1lli_dataout <= niiilll WHEN niOO0ll1l = '1' ELSE wire_nill10O_dataout; + wire_nil1llii_dataout <= wire_nil1lO0l_dataout AND NOT(niOO101ii); + wire_nil1llil_dataout <= wire_nil1lO0O_dataout OR niOO101ii; + wire_nil1lliO_dataout <= wire_nil1lOii_dataout AND NOT(niOO101ii); + wire_nil1lll_dataout <= niiillO WHEN niOO0ll1l = '1' ELSE wire_nill1ii_dataout; + wire_nil1llli_dataout <= wire_nil1lOil_dataout AND NOT(niOO101ii); + wire_nil1llll_dataout <= wire_nil1lOiO_dataout AND NOT(niOO101ii); + wire_nil1lllO_dataout <= wire_nil1lOli_dataout OR niOO101ii; + wire_nil1llO_dataout <= niiilOi WHEN niOO0ll1l = '1' ELSE wire_nill1il_dataout; + wire_nil1llOi_dataout <= wire_nil1lOll_dataout AND NOT(niOO101ii); + wire_nil1llOl_dataout <= wire_nil1lOlO_dataout AND NOT(niOO101ii); + wire_nil1llOO_dataout <= wire_nil1lOOi_dataout AND NOT(niOO101ii); + wire_nil1lO0i_dataout <= wire_nil1O11l_dataout OR niOO101il; + wire_nil1lO0l_dataout <= wire_nil1O11O_dataout OR niOO101il; + wire_nil1lO0O_dataout <= wire_nil1O10i_dataout AND NOT(niOO101il); + wire_nil1lO1i_dataout <= wire_nil1lOOl_dataout AND NOT(niOO101ii); + wire_nil1lO1l_dataout <= wire_nil1lOOO_dataout OR niOO101il; + wire_nil1lO1O_dataout <= wire_nil1O11i_dataout OR niOO101il; + wire_nil1lOi_dataout <= niiilOl WHEN niOO0ll1l = '1' ELSE wire_nill1iO_dataout; + wire_nil1lOii_dataout <= wire_nil1O10l_dataout OR niOO101il; + wire_nil1lOil_dataout <= wire_nil1O10O_dataout AND NOT(niOO101il); + wire_nil1lOiO_dataout <= wire_nil1O1ii_dataout AND NOT(niOO101il); + wire_nil1lOl_dataout <= niiilOO WHEN niOO0ll1l = '1' ELSE wire_nill1li_dataout; + wire_nil1lOli_dataout <= wire_nil1O1il_dataout AND NOT(niOO101il); + wire_nil1lOll_dataout <= wire_nil1O1iO_dataout AND NOT(niOO101il); + wire_nil1lOlO_dataout <= wire_nil1O1li_dataout OR niOO101il; + wire_nil1lOO_dataout <= niiiO1i WHEN niOO0ll1l = '1' ELSE wire_nill1ll_dataout; + wire_nil1lOOi_dataout <= wire_nil1O1ll_dataout AND NOT(niOO101il); + wire_nil1lOOl_dataout <= wire_nil1O1lO_dataout AND NOT(niOO101il); + wire_nil1lOOO_dataout <= wire_nil1O1Oi_dataout OR niOO101iO; + wire_nil1O00i_dataout <= wire_nil1Oi1l_dataout AND NOT(niOO101li); + wire_nil1O00l_dataout <= wire_nil1Oi1O_dataout AND NOT(niOO101li); + wire_nil1O00O_dataout <= wire_nil1Oi0i_dataout OR niOO101li; + wire_nil1O01i_dataout <= wire_nil1O0Ol_dataout OR niOO101li; + wire_nil1O01l_dataout <= wire_nil1O0OO_dataout OR niOO101li; + wire_nil1O01O_dataout <= wire_nil1Oi1i_dataout AND NOT(niOO101li); + wire_nil1O0i_dataout <= niiiO0l WHEN niOO0ll1l = '1' ELSE wire_nill1OO_dataout; + wire_nil1O0ii_dataout <= wire_nil1Oi0l_dataout AND NOT(niOO101li); + wire_nil1O0il_dataout <= wire_nil1Oi0O_dataout AND NOT(niOO101li); + wire_nil1O0iO_dataout <= wire_nil1Oiii_dataout AND NOT(niOO101li); + wire_nil1O0l_dataout <= niiiO0O WHEN niOO0ll1l = '1' ELSE wire_nill01i_dataout; + wire_nil1O0li_dataout <= wire_nil1Oiil_dataout AND NOT(niOO101li); + wire_nil1O0ll_dataout <= wire_nil1OiiO_dataout AND NOT(niOO101ll); + wire_nil1O0lO_dataout <= wire_nil1Oili_dataout OR niOO101ll; + wire_nil1O0O_dataout <= niiiOii WHEN niOO0ll1l = '1' ELSE wire_nill01l_dataout; + wire_nil1O0Oi_dataout <= wire_nil1Oill_dataout OR niOO101ll; + wire_nil1O0Ol_dataout <= wire_nil1OilO_dataout AND NOT(niOO101ll); + wire_nil1O0OO_dataout <= wire_nil1OiOi_dataout OR niOO101ll; + wire_nil1O10i_dataout <= wire_nil1O01l_dataout AND NOT(niOO101iO); + wire_nil1O10l_dataout <= wire_nil1O01O_dataout OR niOO101iO; + wire_nil1O10O_dataout <= wire_nil1O00i_dataout AND NOT(niOO101iO); + wire_nil1O11i_dataout <= wire_nil1O1Ol_dataout AND NOT(niOO101iO); + wire_nil1O11l_dataout <= wire_nil1O1OO_dataout AND NOT(niOO101iO); + wire_nil1O11O_dataout <= wire_nil1O01i_dataout AND NOT(niOO101iO); + wire_nil1O1i_dataout <= niiiO1l WHEN niOO0ll1l = '1' ELSE wire_nill1lO_dataout; + wire_nil1O1ii_dataout <= wire_nil1O00l_dataout AND NOT(niOO101iO); + wire_nil1O1il_dataout <= wire_nil1O00O_dataout AND NOT(niOO101iO); + wire_nil1O1iO_dataout <= wire_nil1O0ii_dataout OR niOO101iO; + wire_nil1O1l_dataout <= niiiO1O WHEN niOO0ll1l = '1' ELSE wire_nill1Oi_dataout; + wire_nil1O1li_dataout <= wire_nil1O0il_dataout AND NOT(niOO101iO); + wire_nil1O1ll_dataout <= wire_nil1O0iO_dataout AND NOT(niOO101iO); + wire_nil1O1lO_dataout <= wire_nil1O0li_dataout AND NOT(niOO101iO); + wire_nil1O1O_dataout <= niiiO0i WHEN niOO0ll1l = '1' ELSE wire_nill1Ol_dataout; + wire_nil1O1Oi_dataout <= wire_nil1O0ll_dataout AND NOT(niOO101li); + wire_nil1O1Ol_dataout <= wire_nil1O0lO_dataout OR niOO101li; + wire_nil1O1OO_dataout <= wire_nil1O0Oi_dataout AND NOT(niOO101li); + wire_nil1Oi0i_dataout <= wire_nil1Ol1l_dataout AND NOT(niOO101ll); + wire_nil1Oi0l_dataout <= wire_nil1Ol1O_dataout AND NOT(niOO101ll); + wire_nil1Oi0O_dataout <= wire_nil1Ol0i_dataout AND NOT(niOO101ll); + wire_nil1Oi1i_dataout <= wire_nil1OiOl_dataout AND NOT(niOO101ll); + wire_nil1Oi1l_dataout <= wire_nil1OiOO_dataout AND NOT(niOO101ll); + wire_nil1Oi1O_dataout <= wire_nil1Ol1i_dataout OR niOO101ll; + wire_nil1Oii_dataout <= niiiOil WHEN niOO0ll1l = '1' ELSE wire_nill01O_dataout; + wire_nil1Oiii_dataout <= wire_nil1Ol0l_dataout AND NOT(niOO101ll); + wire_nil1Oiil_dataout <= wire_nil1Ol0O_dataout AND NOT(niOO101ll); + wire_nil1OiiO_dataout <= wire_nil1Olii_dataout OR niOO101lO; + wire_nil1Oil_dataout <= niiiOiO WHEN niOO0ll1l = '1' ELSE wire_nill00i_dataout; + wire_nil1Oili_dataout <= wire_nil1Olil_dataout OR niOO101lO; + wire_nil1Oill_dataout <= wire_nil1OliO_dataout OR niOO101lO; + wire_nil1OilO_dataout <= wire_nil1Olli_dataout OR niOO101lO; + wire_nil1OiO_dataout <= niiiOli WHEN niOO0ll1l = '1' ELSE wire_nill00l_dataout; + wire_nil1OiOi_dataout <= wire_nil1Olll_dataout AND NOT(niOO101lO); + wire_nil1OiOl_dataout <= wire_nil1OllO_dataout OR niOO101lO; + wire_nil1OiOO_dataout <= wire_nil1OlOi_dataout AND NOT(niOO101lO); + wire_nil1Ol0i_dataout <= wire_nil1OO1l_dataout AND NOT(niOO101lO); + wire_nil1Ol0l_dataout <= wire_nil1OO1O_dataout AND NOT(niOO101lO); + wire_nil1Ol0O_dataout <= wire_nil1OO0i_dataout AND NOT(niOO101lO); + wire_nil1Ol1i_dataout <= wire_nil1OlOl_dataout AND NOT(niOO101lO); + wire_nil1Ol1l_dataout <= wire_nil1OlOO_dataout AND NOT(niOO101lO); + wire_nil1Ol1O_dataout <= wire_nil1OO1i_dataout OR niOO101lO; + wire_nil1Oli_dataout <= niiiOll WHEN niOO0ll1l = '1' ELSE wire_nill00O_dataout; + wire_nil1Olii_dataout <= wire_nil1OO0l_dataout OR niOO101Oi; + wire_nil1Olil_dataout <= wire_nil1OO0O_dataout AND NOT(niOO101Oi); + wire_nil1OliO_dataout <= wire_nil1OOii_dataout AND NOT(niOO101Oi); + wire_nil1Oll_dataout <= niiiOlO WHEN niOO0ll1l = '1' ELSE wire_nill0ii_dataout; + wire_nil1Olli_dataout <= wire_nil1OOil_dataout AND NOT(niOO101Oi); + wire_nil1Olll_dataout <= wire_nil1OOiO_dataout AND NOT(niOO101Oi); + wire_nil1OllO_dataout <= wire_nil1OOli_dataout OR niOO101Oi; + wire_nil1OlO_dataout <= niiiOOi WHEN niOO0ll1l = '1' ELSE wire_nill0il_dataout; + wire_nil1OlOi_dataout <= wire_nil1OOll_dataout AND NOT(niOO101Oi); + wire_nil1OlOl_dataout <= wire_nil1OOlO_dataout AND NOT(niOO101Oi); + wire_nil1OlOO_dataout <= wire_nil1OOOi_dataout OR niOO101Oi; + wire_nil1OO0i_dataout <= wire_nil0111l_dataout AND NOT(niOO101Oi); + wire_nil1OO0l_dataout <= wire_nil0111O_dataout AND NOT(niOO101Ol); + wire_nil1OO0O_dataout <= wire_nil0110i_dataout OR niOO101Ol; + wire_nil1OO1i_dataout <= wire_nil1OOOl_dataout AND NOT(niOO101Oi); + wire_nil1OO1l_dataout <= wire_nil1OOOO_dataout AND NOT(niOO101Oi); + wire_nil1OO1O_dataout <= wire_nil0111i_dataout AND NOT(niOO101Oi); + wire_nil1OOi_dataout <= niiiOOl WHEN niOO0ll1l = '1' ELSE wire_nill0iO_dataout; + wire_nil1OOii_dataout <= wire_nil0110l_dataout AND NOT(niOO101Ol); + wire_nil1OOil_dataout <= wire_nil0110O_dataout OR niOO101Ol; + wire_nil1OOiO_dataout <= wire_nil011ii_dataout OR niOO101Ol; + wire_nil1OOl_dataout <= wire_nill0li_dataout OR niOO0ll1l; + wire_nil1OOli_dataout <= wire_nil011il_dataout AND NOT(niOO101Ol); + wire_nil1OOll_dataout <= wire_nil011iO_dataout AND NOT(niOO101Ol); + wire_nil1OOlO_dataout <= wire_nil011li_dataout OR niOO101Ol; + wire_nil1OOO_dataout <= ni0Ol0O WHEN niOO0ll1l = '1' ELSE wire_nill0ll_dataout; + wire_nil1OOOi_dataout <= wire_nil011ll_dataout AND NOT(niOO101Ol); + wire_nil1OOOl_dataout <= wire_nil011lO_dataout AND NOT(niOO101Ol); + wire_nil1OOOO_dataout <= wire_nil011Oi_dataout AND NOT(niOO101Ol); + wire_nili000i_dataout <= wire_nili0i1l_dataout OR niOO1011O; + wire_nili000l_dataout <= wire_nili0i1O_dataout AND NOT(niOO1011O); + wire_nili000O_dataout <= wire_nili0i0i_dataout AND NOT(niOO1011O); + wire_nili001i_dataout <= wire_nili00Ol_dataout AND NOT(niOO1011O); + wire_nili001l_dataout <= wire_nili00OO_dataout AND NOT(niOO1011O); + wire_nili001O_dataout <= wire_nili0i1i_dataout AND NOT(niOO1011O); + wire_nili00i_dataout <= nii0Oil WHEN niOO0ll1l = '1' ELSE wire_nilOiOO_dataout; + wire_nili00ii_dataout <= wire_nili0i0l_dataout OR niOO1011O; + wire_nili00il_dataout <= wire_nili0i0O_dataout OR niOO1011O; + wire_nili00iO_dataout <= wire_nili0iii_dataout AND NOT(niOO1011O); + wire_nili00l_dataout <= nii0OiO WHEN niOO0ll1l = '1' ELSE wire_nilOl1i_dataout; + wire_nili00li_dataout <= wire_nili0iil_dataout AND NOT(niOO1011O); + wire_nili00ll_dataout <= wire_nili0iiO_dataout OR niOO1010i; + wire_nili00lO_dataout <= wire_nili0ili_dataout AND NOT(niOO1010i); + wire_nili00O_dataout <= niOi01O WHEN niOO0ll1l = '1' ELSE nii0Oli; + wire_nili00Oi_dataout <= wire_nili0ill_dataout OR niOO1010i; + wire_nili00Ol_dataout <= wire_nili0ilO_dataout OR niOO1010i; + wire_nili00OO_dataout <= wire_nili0iOi_dataout AND NOT(niOO1010i); + wire_nili010i_dataout <= wire_nili001l_dataout AND NOT(niOO1011l); + wire_nili010l_dataout <= wire_nili001O_dataout AND NOT(niOO1011l); + wire_nili010O_dataout <= wire_nili000i_dataout OR niOO1011l; + wire_nili011i_dataout <= wire_nili01Ol_dataout OR niOO1011l; + wire_nili011l_dataout <= wire_nili01OO_dataout OR niOO1011l; + wire_nili011O_dataout <= wire_nili001i_dataout OR niOO1011l; + wire_nili01i_dataout <= nii0O0l WHEN niOO0ll1l = '1' ELSE wire_nilOilO_dataout; + wire_nili01ii_dataout <= wire_nili000l_dataout AND NOT(niOO1011l); + wire_nili01il_dataout <= wire_nili000O_dataout AND NOT(niOO1011l); + wire_nili01iO_dataout <= wire_nili00ii_dataout AND NOT(niOO1011l); + wire_nili01l_dataout <= nii0O0O WHEN niOO0ll1l = '1' ELSE wire_nilOiOi_dataout; + wire_nili01li_dataout <= wire_nili00il_dataout OR niOO1011l; + wire_nili01ll_dataout <= wire_nili00iO_dataout OR niOO1011l; + wire_nili01lO_dataout <= wire_nili00li_dataout AND NOT(niOO1011l); + wire_nili01O_dataout <= nii0Oii WHEN niOO0ll1l = '1' ELSE wire_nilOiOl_dataout; + wire_nili01Oi_dataout <= wire_nili00ll_dataout AND NOT(niOO1011O); + wire_nili01Ol_dataout <= wire_nili00lO_dataout OR niOO1011O; + wire_nili01OO_dataout <= wire_nili00Oi_dataout AND NOT(niOO1011O); + wire_nili0i0i_dataout <= wire_nili0l1l_dataout AND NOT(niOO1010i); + wire_nili0i0l_dataout <= wire_nili0l1O_dataout AND NOT(niOO1010i); + wire_nili0i0O_dataout <= wire_nili0l0i_dataout AND NOT(niOO1010i); + wire_nili0i1i_dataout <= wire_nili0iOl_dataout AND NOT(niOO1010i); + wire_nili0i1l_dataout <= wire_nili0iOO_dataout AND NOT(niOO1010i); + wire_nili0i1O_dataout <= wire_nili0l1i_dataout OR niOO1010i; + wire_nili0ii_dataout <= niOi00i WHEN niOO0ll1l = '1' ELSE nii0Oll; + wire_nili0iii_dataout <= wire_nili0l0l_dataout OR niOO1010i; + wire_nili0iil_dataout <= wire_nili0l0O_dataout OR niOO1010i; + wire_nili0iiO_dataout <= wire_nili0lii_dataout OR niOO1010l; + wire_nili0il_dataout <= niOi00l WHEN niOO0ll1l = '1' ELSE nii0OlO; + wire_nili0ili_dataout <= wire_nili0lil_dataout OR niOO1010l; + wire_nili0ill_dataout <= wire_nili0liO_dataout AND NOT(niOO1010l); + wire_nili0ilO_dataout <= wire_nili0lli_dataout AND NOT(niOO1010l); + wire_nili0iO_dataout <= niOi00O WHEN niOO0ll1l = '1' ELSE nii0OOi; + wire_nili0iOi_dataout <= wire_nili0lll_dataout AND NOT(niOO1010l); + wire_nili0iOl_dataout <= wire_nili0llO_dataout OR niOO1010l; + wire_nili0iOO_dataout <= wire_nili0lOi_dataout OR niOO1010l; + wire_nili0l0i_dataout <= wire_nili0O1l_dataout OR niOO1010l; + wire_nili0l0l_dataout <= wire_nili0O1O_dataout OR niOO1010l; + wire_nili0l0O_dataout <= wire_nili0O0i_dataout AND NOT(niOO1010l); + wire_nili0l1i_dataout <= wire_nili0lOl_dataout AND NOT(niOO1010l); + wire_nili0l1l_dataout <= wire_nili0lOO_dataout AND NOT(niOO1010l); + wire_nili0l1O_dataout <= wire_nili0O1i_dataout AND NOT(niOO1010l); + wire_nili0li_dataout <= niOi0ii WHEN niOO0ll1l = '1' ELSE nii0OOl; + wire_nili0lii_dataout <= wire_nili0O0l_dataout AND NOT(niOO1010O); + wire_nili0lil_dataout <= wire_nili0O0O_dataout OR niOO1010O; + wire_nili0liO_dataout <= wire_nili0Oii_dataout OR niOO1010O; + wire_nili0ll_dataout <= niOi0il WHEN niOO0ll1l = '1' ELSE nii0OOO; + wire_nili0lli_dataout <= wire_nili0Oil_dataout OR niOO1010O; + wire_nili0lll_dataout <= wire_nili0OiO_dataout AND NOT(niOO1010O); + wire_nili0llO_dataout <= wire_nili0Oli_dataout AND NOT(niOO1010O); + wire_nili0lO_dataout <= niOi0iO WHEN niOO0ll1l = '1' ELSE niii11i; + wire_nili0lOi_dataout <= wire_nili0Oll_dataout OR niOO1010O; + wire_nili0lOl_dataout <= wire_nili0OlO_dataout AND NOT(niOO1010O); + wire_nili0lOO_dataout <= wire_nili0OOi_dataout AND NOT(niOO1010O); + wire_nili0O0i_dataout <= wire_nilii11l_dataout AND NOT(niOO1010O); + wire_nili0O0l_dataout <= wire_nilii11O_dataout AND NOT(niOO101ii); + wire_nili0O0O_dataout <= wire_nilii10i_dataout OR niOO101ii; + wire_nili0O1i_dataout <= wire_nili0OOl_dataout OR niOO1010O; + wire_nili0O1l_dataout <= wire_nili0OOO_dataout OR niOO1010O; + wire_nili0O1O_dataout <= wire_nilii11i_dataout AND NOT(niOO1010O); + wire_nili0Oi_dataout <= niOi0li WHEN niOO0ll1l = '1' ELSE niii11l; + wire_nili0Oii_dataout <= wire_nilii10l_dataout AND NOT(niOO101ii); + wire_nili0Oil_dataout <= wire_nilii10O_dataout AND NOT(niOO101ii); + wire_nili0OiO_dataout <= wire_nilii1ii_dataout AND NOT(niOO101ii); + wire_nili0Ol_dataout <= niOi0ll WHEN niOO0ll1l = '1' ELSE niii11O; + wire_nili0Oli_dataout <= wire_nilii1il_dataout AND NOT(niOO101ii); + wire_nili0Oll_dataout <= wire_nilii1iO_dataout OR niOO101ii; + wire_nili0OlO_dataout <= wire_nilii1li_dataout AND NOT(niOO101ii); + wire_nili0OO_dataout <= niOi0lO WHEN niOO0ll1l = '1' ELSE niii10i; + wire_nili0OOi_dataout <= wire_nilii1ll_dataout OR niOO101ii; + wire_nili0OOl_dataout <= wire_nilii1lO_dataout OR niOO101ii; + wire_nili0OOO_dataout <= wire_nilii1Oi_dataout AND NOT(niOO101ii); + wire_nili10i_dataout <= nii0lil WHEN niOO0ll1l = '1' ELSE wire_nilO0OO_dataout; + wire_nili10l_dataout <= nii0liO WHEN niOO0ll1l = '1' ELSE wire_nilOi1i_dataout; + wire_nili10O_dataout <= nii0lli WHEN niOO0ll1l = '1' ELSE wire_nilOi1l_dataout; + wire_nili11i_dataout <= nii0l0l WHEN niOO0ll1l = '1' ELSE wire_nilO0lO_dataout; + wire_nili11l_dataout <= nii0l0O WHEN niOO0ll1l = '1' ELSE wire_nilO0Oi_dataout; + wire_nili11O_dataout <= nii0lii WHEN niOO0ll1l = '1' ELSE wire_nilO0Ol_dataout; + wire_nili1ii_dataout <= nii0lll WHEN niOO0ll1l = '1' ELSE wire_nilOi1O_dataout; + wire_nili1il_dataout <= nii0llO WHEN niOO0ll1l = '1' ELSE wire_nilOi0i_dataout; + wire_nili1iO_dataout <= nii0lOi WHEN niOO0ll1l = '1' ELSE wire_nilOi0l_dataout; + wire_nili1l0i_dataout <= wire_nili1O1O_dataout AND NOT(niOO11OOO); + wire_nili1l0l_dataout <= wire_nili1O0i_dataout OR niOO11OOO; + wire_nili1l0O_dataout <= wire_nili1O0l_dataout OR niOO11OOO; + wire_nili1l1O_dataout <= wire_nili1O1l_dataout OR niOO11OOO; + wire_nili1li_dataout <= nii0lOl WHEN niOO0ll1l = '1' ELSE wire_nilOi0O_dataout; + wire_nili1lii_dataout <= wire_nili1O0O_dataout AND NOT(niOO11OOO); + wire_nili1lil_dataout <= wire_nili1Oii_dataout AND NOT(niOO11OOO); + wire_nili1liO_dataout <= wire_nili1Oil_dataout AND NOT(niOO11OOO); + wire_nili1ll_dataout <= nii0lOO WHEN niOO0ll1l = '1' ELSE wire_nilOiii_dataout; + wire_nili1lli_dataout <= wire_nili1OiO_dataout OR niOO11OOO; + wire_nili1lll_dataout <= wire_nili1Oli_dataout AND NOT(niOO11OOO); + wire_nili1llO_dataout <= wire_nili1Oll_dataout AND NOT(niOO11OOO); + wire_nili1lO_dataout <= nii0O1i WHEN niOO0ll1l = '1' ELSE wire_nilOiil_dataout; + wire_nili1lOi_dataout <= wire_nili1OlO_dataout AND NOT(niOO11OOO); + wire_nili1lOl_dataout <= wire_nili1OOi_dataout AND NOT(niOO11OOO); + wire_nili1lOO_dataout <= wire_nili1OOl_dataout OR niOO11OOO; + wire_nili1O0i_dataout <= wire_nili011l_dataout AND NOT(niOO1011i); + wire_nili1O0l_dataout <= wire_nili011O_dataout AND NOT(niOO1011i); + wire_nili1O0O_dataout <= wire_nili010i_dataout AND NOT(niOO1011i); + wire_nili1O1i_dataout <= wire_nil1ilOi_dataout OR niOO11OOO; + wire_nili1O1l_dataout <= wire_nili1OOO_dataout OR niOO1011i; + wire_nili1O1O_dataout <= wire_nili011i_dataout OR niOO1011i; + wire_nili1Oi_dataout <= nii0O1l WHEN niOO0ll1l = '1' ELSE wire_nilOiiO_dataout; + wire_nili1Oii_dataout <= wire_nili010l_dataout OR niOO1011i; + wire_nili1Oil_dataout <= wire_nili010O_dataout OR niOO1011i; + wire_nili1OiO_dataout <= wire_nili01ii_dataout AND NOT(niOO1011i); + wire_nili1Ol_dataout <= nii0O1O WHEN niOO0ll1l = '1' ELSE wire_nilOili_dataout; + wire_nili1Oli_dataout <= wire_nili01il_dataout AND NOT(niOO1011i); + wire_nili1Oll_dataout <= wire_nili01iO_dataout AND NOT(niOO1011i); + wire_nili1OlO_dataout <= wire_nili01li_dataout AND NOT(niOO1011i); + wire_nili1OO_dataout <= nii0O0i WHEN niOO0ll1l = '1' ELSE wire_nilOill_dataout; + wire_nili1OOi_dataout <= wire_nili01ll_dataout OR niOO1011i; + wire_nili1OOl_dataout <= wire_nili01lO_dataout OR niOO1011i; + wire_nili1OOO_dataout <= wire_nili01Oi_dataout AND NOT(niOO1011l); + wire_nilii00i_dataout <= wire_niliii1l_dataout AND NOT(niOO101iO); + wire_nilii00l_dataout <= wire_niliii1O_dataout AND NOT(niOO101iO); + wire_nilii00O_dataout <= wire_niliii0i_dataout OR niOO101iO; + wire_nilii01i_dataout <= wire_nilii0Ol_dataout OR niOO101iO; + wire_nilii01l_dataout <= wire_nilii0OO_dataout OR niOO101iO; + wire_nilii01O_dataout <= wire_niliii1i_dataout AND NOT(niOO101iO); + wire_nilii0i_dataout <= niOii1i WHEN niOO0ll1l = '1' ELSE niii1il; + wire_nilii0ii_dataout <= wire_niliii0l_dataout OR niOO101iO; + wire_nilii0il_dataout <= wire_niliii0O_dataout AND NOT(niOO101iO); + wire_nilii0iO_dataout <= wire_niliiiii_dataout AND NOT(niOO101iO); + wire_nilii0l_dataout <= niOii1l WHEN niOO0ll1l = '1' ELSE niii1iO; + wire_nilii0li_dataout <= wire_niliiiil_dataout OR niOO101iO; + wire_nilii0ll_dataout <= wire_niliiiiO_dataout OR niOO101iO; + wire_nilii0lO_dataout <= wire_niliiili_dataout AND NOT(niOO101iO); + wire_nilii0O_dataout <= niOii1O WHEN niOO0ll1l = '1' ELSE niii1li; + wire_nilii0Oi_dataout <= wire_niliiill_dataout AND NOT(niOO101iO); + wire_nilii0Ol_dataout <= wire_niliiilO_dataout AND NOT(niOO101li); + wire_nilii0OO_dataout <= wire_niliiiOi_dataout OR niOO101li; + wire_nilii10i_dataout <= wire_nilii01l_dataout AND NOT(niOO101il); + wire_nilii10l_dataout <= wire_nilii01O_dataout OR niOO101il; + wire_nilii10O_dataout <= wire_nilii00i_dataout OR niOO101il; + wire_nilii11i_dataout <= wire_nilii1Ol_dataout AND NOT(niOO101ii); + wire_nilii11l_dataout <= wire_nilii1OO_dataout AND NOT(niOO101ii); + wire_nilii11O_dataout <= wire_nilii01i_dataout OR niOO101il; + wire_nilii1i_dataout <= niOi0Oi WHEN niOO0ll1l = '1' ELSE niii10l; + wire_nilii1ii_dataout <= wire_nilii00l_dataout AND NOT(niOO101il); + wire_nilii1il_dataout <= wire_nilii00O_dataout AND NOT(niOO101il); + wire_nilii1iO_dataout <= wire_nilii0ii_dataout AND NOT(niOO101il); + wire_nilii1l_dataout <= niOi0Ol WHEN niOO0ll1l = '1' ELSE niii10O; + wire_nilii1li_dataout <= wire_nilii0il_dataout OR niOO101il; + wire_nilii1ll_dataout <= wire_nilii0iO_dataout AND NOT(niOO101il); + wire_nilii1lO_dataout <= wire_nilii0li_dataout AND NOT(niOO101il); + wire_nilii1O_dataout <= niOi0OO WHEN niOO0ll1l = '1' ELSE niii1ii; + wire_nilii1Oi_dataout <= wire_nilii0ll_dataout OR niOO101il; + wire_nilii1Ol_dataout <= wire_nilii0lO_dataout OR niOO101il; + wire_nilii1OO_dataout <= wire_nilii0Oi_dataout AND NOT(niOO101il); + wire_niliii0i_dataout <= wire_niliil1l_dataout AND NOT(niOO101li); + wire_niliii0l_dataout <= wire_niliil1O_dataout OR niOO101li; + wire_niliii0O_dataout <= wire_niliil0i_dataout AND NOT(niOO101li); + wire_niliii1i_dataout <= wire_niliiiOl_dataout OR niOO101li; + wire_niliii1l_dataout <= wire_niliiiOO_dataout OR niOO101li; + wire_niliii1O_dataout <= wire_niliil1i_dataout AND NOT(niOO101li); + wire_niliiii_dataout <= niOii0i WHEN niOO0ll1l = '1' ELSE niii1ll; + wire_niliiiii_dataout <= wire_niliil0l_dataout OR niOO101li; + wire_niliiiil_dataout <= wire_niliil0O_dataout OR niOO101li; + wire_niliiiiO_dataout <= wire_niliilii_dataout AND NOT(niOO101li); + wire_niliiil_dataout <= niOii0l WHEN niOO0ll1l = '1' ELSE niii1lO; + wire_niliiili_dataout <= wire_niliilil_dataout AND NOT(niOO101li); + wire_niliiill_dataout <= wire_niliiliO_dataout AND NOT(niOO101li); + wire_niliiilO_dataout <= wire_niliilli_dataout AND NOT(niOO101ll); + wire_niliiiO_dataout <= niOii0O WHEN niOO0ll1l = '1' ELSE niii1Oi; + wire_niliiiOi_dataout <= wire_niliilll_dataout OR niOO101ll; + wire_niliiiOl_dataout <= wire_niliillO_dataout AND NOT(niOO101ll); + wire_niliiiOO_dataout <= wire_niliilOi_dataout AND NOT(niOO101ll); + wire_niliil0i_dataout <= wire_niliiO1l_dataout OR niOO101ll; + wire_niliil0l_dataout <= wire_niliiO1O_dataout OR niOO101ll; + wire_niliil0O_dataout <= wire_niliiO0i_dataout AND NOT(niOO101ll); + wire_niliil1i_dataout <= wire_niliilOl_dataout AND NOT(niOO101ll); + wire_niliil1l_dataout <= wire_niliilOO_dataout AND NOT(niOO101ll); + wire_niliil1O_dataout <= wire_niliiO1i_dataout OR niOO101ll; + wire_niliili_dataout <= niOiiii WHEN niOO0ll1l = '1' ELSE niii1Ol; + wire_niliilii_dataout <= wire_niliiO0l_dataout AND NOT(niOO101ll); + wire_niliilil_dataout <= wire_niliiO0O_dataout AND NOT(niOO101ll); + wire_niliiliO_dataout <= wire_niliiOii_dataout AND NOT(niOO101ll); + wire_niliill_dataout <= niOiiil WHEN niOO0ll1l = '1' ELSE niii1OO; + wire_niliilli_dataout <= wire_niliiOil_dataout OR niOO101lO; + wire_niliilll_dataout <= wire_niliiOiO_dataout AND NOT(niOO101lO); + wire_niliillO_dataout <= wire_niliiOli_dataout OR niOO101lO; + wire_niliilO_dataout <= niOiiiO WHEN niOO0ll1l = '1' ELSE niii01i; + wire_niliilOi_dataout <= wire_niliiOll_dataout OR niOO101lO; + wire_niliilOl_dataout <= wire_niliiOlO_dataout AND NOT(niOO101lO); + wire_niliilOO_dataout <= wire_niliiOOi_dataout AND NOT(niOO101lO); + wire_niliiO0i_dataout <= wire_nilil11l_dataout OR niOO101lO; + wire_niliiO0l_dataout <= wire_nilil11O_dataout OR niOO101lO; + wire_niliiO0O_dataout <= wire_nilil10i_dataout AND NOT(niOO101lO); + wire_niliiO1i_dataout <= wire_niliiOOl_dataout AND NOT(niOO101lO); + wire_niliiO1l_dataout <= wire_niliiOOO_dataout OR niOO101lO; + wire_niliiO1O_dataout <= wire_nilil11i_dataout AND NOT(niOO101lO); + wire_niliiOi_dataout <= niOiili WHEN niOO0ll1l = '1' ELSE niii01l; + wire_niliiOii_dataout <= wire_nilil10l_dataout AND NOT(niOO101lO); + wire_niliiOil_dataout <= wire_nilil10O_dataout OR niOO101Oi; + wire_niliiOiO_dataout <= wire_nilil1ii_dataout OR niOO101Oi; + wire_niliiOl_dataout <= niOiill WHEN niOO0ll1l = '1' ELSE niii01O; + wire_niliiOli_dataout <= wire_nilil1il_dataout AND NOT(niOO101Oi); + wire_niliiOll_dataout <= wire_nilil1iO_dataout AND NOT(niOO101Oi); + wire_niliiOlO_dataout <= wire_nilil1li_dataout AND NOT(niOO101Oi); + wire_niliiOO_dataout <= niOiilO WHEN niOO0ll1l = '1' ELSE niii00i; + wire_niliiOOi_dataout <= wire_nilil1ll_dataout OR niOO101Oi; + wire_niliiOOl_dataout <= wire_nilil1lO_dataout OR niOO101Oi; + wire_niliiOOO_dataout <= wire_nilil1Oi_dataout AND NOT(niOO101Oi); + wire_nilil00i_dataout <= wire_nilili1l_dataout AND NOT(niOO101OO); + wire_nilil00l_dataout <= wire_nilili1O_dataout OR niOO101OO; + wire_nilil00O_dataout <= wire_nilili0i_dataout AND NOT(niOO101OO); + wire_nilil01i_dataout <= wire_nilil0Ol_dataout AND NOT(niOO101Ol); + wire_nilil01l_dataout <= wire_nilil0OO_dataout AND NOT(niOO101Ol); + wire_nilil01O_dataout <= wire_nilili1i_dataout AND NOT(niOO101Ol); + wire_nilil0i_dataout <= niOil1i WHEN niOO0ll1l = '1' ELSE niii0il; + wire_nilil0ii_dataout <= wire_nilili0l_dataout AND NOT(niOO101OO); + wire_nilil0il_dataout <= wire_nilili0O_dataout AND NOT(niOO101OO); + wire_nilil0iO_dataout <= wire_nililiii_dataout AND NOT(niOO101OO); + wire_nilil0l_dataout <= niOil1l WHEN niOO0ll1l = '1' ELSE niii0iO; + wire_nilil0li_dataout <= wire_nililiil_dataout AND NOT(niOO101OO); + wire_nilil0ll_dataout <= wire_nililiiO_dataout AND NOT(niOO101OO); + wire_nilil0lO_dataout <= wire_nililili_dataout OR niOO101OO; + wire_nilil0O_dataout <= niOil1O WHEN niOO0ll1l = '1' ELSE niii0li; + wire_nilil0Oi_dataout <= wire_nililill_dataout AND NOT(niOO101OO); + wire_nilil0Ol_dataout <= wire_nilililO_dataout AND NOT(niOO101OO); + wire_nilil0OO_dataout <= wire_nililiOi_dataout AND NOT(niOO101OO); + wire_nilil10i_dataout <= wire_nilil01l_dataout AND NOT(niOO101Oi); + wire_nilil10l_dataout <= wire_nilil01O_dataout AND NOT(niOO101Oi); + wire_nilil10O_dataout <= wire_nilil00i_dataout AND NOT(niOO101Ol); + wire_nilil11i_dataout <= wire_nilil1Ol_dataout OR niOO101Oi; + wire_nilil11l_dataout <= wire_nilil1OO_dataout OR niOO101Oi; + wire_nilil11O_dataout <= wire_nilil01i_dataout AND NOT(niOO101Oi); + wire_nilil1i_dataout <= niOiiOi WHEN niOO0ll1l = '1' ELSE niii00l; + wire_nilil1ii_dataout <= wire_nilil00l_dataout OR niOO101Ol; + wire_nilil1il_dataout <= wire_nilil00O_dataout OR niOO101Ol; + wire_nilil1iO_dataout <= wire_nilil0ii_dataout OR niOO101Ol; + wire_nilil1l_dataout <= niOiiOl WHEN niOO0ll1l = '1' ELSE niii00O; + wire_nilil1li_dataout <= wire_nilil0il_dataout AND NOT(niOO101Ol); + wire_nilil1ll_dataout <= wire_nilil0iO_dataout AND NOT(niOO101Ol); + wire_nilil1lO_dataout <= wire_nilil0li_dataout OR niOO101Ol; + wire_nilil1O_dataout <= niOiiOO WHEN niOO0ll1l = '1' ELSE niii0ii; + wire_nilil1Oi_dataout <= wire_nilil0ll_dataout OR niOO101Ol; + wire_nilil1Ol_dataout <= wire_nilil0lO_dataout OR niOO101Ol; + wire_nilil1OO_dataout <= wire_nilil0Oi_dataout AND NOT(niOO101Ol); + wire_nilili0i_dataout <= wire_nilill1l_dataout AND NOT(niOO1001i); + wire_nilili0l_dataout <= wire_nilill1O_dataout AND NOT(niOO1001i); + wire_nilili0O_dataout <= wire_nilill0i_dataout AND NOT(niOO1001i); + wire_nilili1i_dataout <= wire_nililiOl_dataout AND NOT(niOO101OO); + wire_nilili1l_dataout <= wire_nililiOO_dataout AND NOT(niOO1001i); + wire_nilili1O_dataout <= wire_nilill1i_dataout AND NOT(niOO1001i); + wire_nililii_dataout <= niOil0i WHEN niOO0ll1l = '1' ELSE niii0ll; + wire_nililiii_dataout <= wire_nilill0l_dataout OR niOO1001i; + wire_nililiil_dataout <= wire_nilill0O_dataout OR niOO1001i; + wire_nililiiO_dataout <= wire_nilillii_dataout OR niOO1001i; + wire_nililil_dataout <= niii0Oi WHEN niOO0liOO = '1' ELSE wire_nilOl1l_dataout; + wire_nililili_dataout <= wire_nilillil_dataout AND NOT(niOO1001i); + wire_nililill_dataout <= wire_nililliO_dataout AND NOT(niOO1001i); + wire_nilililO_dataout <= wire_nilillli_dataout OR niOO1001i; + wire_nililiO_dataout <= niii0Ol WHEN niOO0liOO = '1' ELSE wire_nilOl1O_dataout; + wire_nililiOi_dataout <= wire_nilillll_dataout AND NOT(niOO1001i); + wire_nililiOl_dataout <= wire_nililllO_dataout AND NOT(niOO1001i); + wire_nililiOO_dataout <= wire_nilillOi_dataout OR niOO1001l; + wire_nilill0i_dataout <= wire_nililO1l_dataout AND NOT(niOO1001l); + wire_nilill0l_dataout <= wire_nililO1O_dataout AND NOT(niOO1001l); + wire_nilill0O_dataout <= wire_nililO0i_dataout AND NOT(niOO1001l); + wire_nilill1i_dataout <= wire_nilillOl_dataout OR niOO1001l; + wire_nilill1l_dataout <= wire_nilillOO_dataout AND NOT(niOO1001l); + wire_nilill1O_dataout <= wire_nililO1i_dataout OR niOO1001l; + wire_nililli_dataout <= niii0OO WHEN niOO0liOO = '1' ELSE wire_nilOl0i_dataout; + wire_nilillii_dataout <= wire_nililO0l_dataout OR niOO1001l; + wire_nilillil_dataout <= wire_nililO0O_dataout AND NOT(niOO1001l); + wire_nililliO_dataout <= wire_nililOii_dataout OR niOO1001l; + wire_nililll_dataout <= niiii1i WHEN niOO0liOO = '1' ELSE wire_nilOl0l_dataout; + wire_nilillli_dataout <= wire_nililOil_dataout AND NOT(niOO1001l); + wire_nilillll_dataout <= wire_nililOiO_dataout AND NOT(niOO1001l); + wire_nililllO_dataout <= wire_nililOli_dataout AND NOT(niOO1001l); + wire_nilillO_dataout <= niiii1l WHEN niOO0liOO = '1' ELSE wire_nilOl0O_dataout; + wire_nilillOi_dataout <= wire_nililOll_dataout AND NOT(niOO1001O); + wire_nilillOl_dataout <= wire_nililOlO_dataout OR niOO1001O; + wire_nilillOO_dataout <= wire_nililOOi_dataout AND NOT(niOO1001O); + wire_nililO0i_dataout <= wire_niliO11l_dataout OR niOO1001O; + wire_nililO0l_dataout <= wire_niliO11O_dataout AND NOT(niOO1001O); + wire_nililO0O_dataout <= wire_niliO10i_dataout OR niOO1001O; + wire_nililO1i_dataout <= wire_nililOOl_dataout AND NOT(niOO1001O); + wire_nililO1l_dataout <= wire_nililOOO_dataout AND NOT(niOO1001O); + wire_nililO1O_dataout <= wire_niliO11i_dataout OR niOO1001O; + wire_nililOi_dataout <= niiii1O WHEN niOO0liOO = '1' ELSE wire_nilOlii_dataout; + wire_nililOii_dataout <= wire_niliO10l_dataout AND NOT(niOO1001O); + wire_nililOil_dataout <= wire_niliO10O_dataout AND NOT(niOO1001O); + wire_nililOiO_dataout <= wire_niliO1ii_dataout AND NOT(niOO1001O); + wire_nililOl_dataout <= niiii0i WHEN niOO0liOO = '1' ELSE wire_nilOlil_dataout; + wire_nililOli_dataout <= wire_niliO1il_dataout AND NOT(niOO1001O); + wire_nililOll_dataout <= wire_niliO1iO_dataout OR niOO1000i; + wire_nililOlO_dataout <= wire_niliO1li_dataout AND NOT(niOO1000i); + wire_nililOO_dataout <= niiii0l WHEN niOO0liOO = '1' ELSE wire_nilOliO_dataout; + wire_nililOOi_dataout <= wire_niliO1ll_dataout AND NOT(niOO1000i); + wire_nililOOl_dataout <= wire_niliO1lO_dataout AND NOT(niOO1000i); + wire_nililOOO_dataout <= wire_niliO1Oi_dataout AND NOT(niOO1000i); + wire_niliO00i_dataout <= wire_niliOi1l_dataout AND NOT(niOO1000l); + wire_niliO00l_dataout <= wire_niliOi1O_dataout AND NOT(niOO1000l); + wire_niliO00O_dataout <= wire_niliOi0i_dataout AND NOT(niOO1000l); + wire_niliO01i_dataout <= wire_niliO0Ol_dataout OR niOO1000l; + wire_niliO01l_dataout <= wire_niliO0OO_dataout AND NOT(niOO1000l); + wire_niliO01O_dataout <= wire_niliOi1i_dataout OR niOO1000l; + wire_niliO0i_dataout <= niiiiiO WHEN niOO0liOO = '1' ELSE wire_nilOlOi_dataout; + wire_niliO0ii_dataout <= wire_niliOi0l_dataout AND NOT(niOO1000O); + wire_niliO0il_dataout <= wire_niliOi0O_dataout AND NOT(niOO1000O); + wire_niliO0iO_dataout <= wire_niliOiii_dataout AND NOT(niOO1000O); + wire_niliO0l_dataout <= niiiili WHEN niOO0liOO = '1' ELSE wire_nilOlOl_dataout; + wire_niliO0li_dataout <= wire_niliOiil_dataout AND NOT(niOO1000O); + wire_niliO0ll_dataout <= wire_niliOiiO_dataout AND NOT(niOO1000O); + wire_niliO0lO_dataout <= wire_niliOili_dataout AND NOT(niOO1000O); + wire_niliO0O_dataout <= niiiill WHEN niOO0liOO = '1' ELSE wire_nilOlOO_dataout; + wire_niliO0Oi_dataout <= wire_niliOill_dataout AND NOT(niOO1000O); + wire_niliO0Ol_dataout <= wire_niliOilO_dataout OR niOO1000O; + wire_niliO0OO_dataout <= wire_niliOiOi_dataout OR niOO1000O; + wire_niliO10i_dataout <= wire_niliO01l_dataout OR niOO1000i; + wire_niliO10l_dataout <= wire_niliO01O_dataout AND NOT(niOO1000i); + wire_niliO10O_dataout <= wire_niliO00i_dataout AND NOT(niOO1000i); + wire_niliO11i_dataout <= wire_niliO1Ol_dataout AND NOT(niOO1000i); + wire_niliO11l_dataout <= wire_niliO1OO_dataout OR niOO1000i; + wire_niliO11O_dataout <= wire_niliO01i_dataout AND NOT(niOO1000i); + wire_niliO1i_dataout <= niiii0O WHEN niOO0liOO = '1' ELSE wire_nilOlli_dataout; + wire_niliO1ii_dataout <= wire_niliO00l_dataout AND NOT(niOO1000i); + wire_niliO1il_dataout <= wire_niliO00O_dataout AND NOT(niOO1000i); + wire_niliO1iO_dataout <= wire_niliO0ii_dataout OR niOO1000l; + wire_niliO1l_dataout <= niiiiii WHEN niOO0liOO = '1' ELSE wire_nilOlll_dataout; + wire_niliO1li_dataout <= wire_niliO0il_dataout OR niOO1000l; + wire_niliO1ll_dataout <= wire_niliO0iO_dataout OR niOO1000l; + wire_niliO1lO_dataout <= wire_niliO0li_dataout AND NOT(niOO1000l); + wire_niliO1O_dataout <= niiiiil WHEN niOO0liOO = '1' ELSE wire_nilOllO_dataout; + wire_niliO1Oi_dataout <= wire_niliO0ll_dataout AND NOT(niOO1000l); + wire_niliO1Ol_dataout <= wire_niliO0lO_dataout AND NOT(niOO1000l); + wire_niliO1OO_dataout <= wire_niliO0Oi_dataout OR niOO1000l; + wire_niliOi0i_dataout <= wire_niliOl1l_dataout AND NOT(niOO1000O); + wire_niliOi0l_dataout <= wire_niliOl1O_dataout OR niOO100ii; + wire_niliOi0O_dataout <= wire_niliOl0i_dataout OR niOO100ii; + wire_niliOi1i_dataout <= wire_niliOiOl_dataout AND NOT(niOO1000O); + wire_niliOi1l_dataout <= wire_niliOiOO_dataout AND NOT(niOO1000O); + wire_niliOi1O_dataout <= wire_niliOl1i_dataout AND NOT(niOO1000O); + wire_niliOii_dataout <= niiiilO WHEN niOO0liOO = '1' ELSE wire_nilOO1i_dataout; + wire_niliOiii_dataout <= wire_niliOl0l_dataout AND NOT(niOO100ii); + wire_niliOiil_dataout <= wire_niliOl0O_dataout OR niOO100ii; + wire_niliOiiO_dataout <= wire_niliOlii_dataout OR niOO100ii; + wire_niliOil_dataout <= niiiiOi WHEN niOO0liOO = '1' ELSE wire_nilOO1l_dataout; + wire_niliOili_dataout <= wire_niliOlil_dataout AND NOT(niOO100ii); + wire_niliOill_dataout <= wire_niliOliO_dataout OR niOO100ii; + wire_niliOilO_dataout <= wire_niliOlli_dataout OR niOO100ii; + wire_niliOiO_dataout <= niiiiOl WHEN niOO0liOO = '1' ELSE wire_nilOO1O_dataout; + wire_niliOiOi_dataout <= wire_niliOlll_dataout AND NOT(niOO100ii); + wire_niliOiOl_dataout <= wire_niliOllO_dataout AND NOT(niOO100ii); + wire_niliOiOO_dataout <= wire_niliOlOi_dataout AND NOT(niOO100ii); + wire_niliOl0i_dataout <= wire_niliOO1l_dataout AND NOT(niOO10l0O); + wire_niliOl0l_dataout <= wire_niliOO1O_dataout AND NOT(niOO10l0O); + wire_niliOl0O_dataout <= wire_niliOO0i_dataout OR niOO10l0O; + wire_niliOl1i_dataout <= wire_niliOlOl_dataout AND NOT(niOO100ii); + wire_niliOl1l_dataout <= wire_niliOlOO_dataout AND NOT(niOO100ii); + wire_niliOl1O_dataout <= wire_niliOO1i_dataout OR niOO10l0O; + wire_niliOli_dataout <= niiiiOO WHEN niOO0liOO = '1' ELSE wire_nilOO0i_dataout; + wire_niliOlii_dataout <= wire_niliOO0l_dataout AND NOT(niOO10l0O); + wire_niliOlil_dataout <= wire_niliOO0O_dataout AND NOT(niOO10l0O); + wire_niliOliO_dataout <= wire_niliOOii_dataout OR niOO10l0O; + wire_niliOll_dataout <= niiil1i WHEN niOO0liOO = '1' ELSE wire_nilOO0l_dataout; + wire_niliOlli_dataout <= wire_niliOOil_dataout OR niOO10l0O; + wire_niliOlll_dataout <= wire_niliOOiO_dataout AND NOT(niOO10l0O); + wire_niliOllO_dataout <= wire_niliOOli_dataout AND NOT(niOO10l0O); + wire_niliOlO_dataout <= niiil1l WHEN niOO0liOO = '1' ELSE wire_nilOO0O_dataout; + wire_niliOlOi_dataout <= wire_niliOOll_dataout AND NOT(niOO10l0O); + wire_niliOlOl_dataout <= wire_niliOOlO_dataout AND NOT(niOO10l0O); + wire_niliOlOO_dataout <= wire_niliOOOi_dataout AND NOT(niOO10l0O); + wire_niliOO0i_dataout <= wire_nill111l_dataout AND NOT(niOO100il); + wire_niliOO0l_dataout <= wire_nill111O_dataout AND NOT(niOO100il); + wire_niliOO0O_dataout <= wire_nill110i_dataout OR niOO100il; + wire_niliOO1i_dataout <= wire_niliOOOl_dataout AND NOT(niOO100il); + wire_niliOO1l_dataout <= wire_niliOOOO_dataout OR niOO100il; + wire_niliOO1O_dataout <= wire_nill111i_dataout OR niOO100il; + wire_niliOOi_dataout <= niiil1O WHEN niOO0liOO = '1' ELSE wire_nilOOii_dataout; + wire_niliOOii_dataout <= wire_nill110l_dataout AND NOT(niOO100il); + wire_niliOOil_dataout <= wire_nill110O_dataout AND NOT(niOO100il); + wire_niliOOiO_dataout <= wire_nill11ii_dataout OR niOO100il; + wire_niliOOl_dataout <= niiil0i WHEN niOO0liOO = '1' ELSE wire_nilOOil_dataout; + wire_niliOOli_dataout <= wire_nill11il_dataout AND NOT(niOO100il); + wire_niliOOll_dataout <= wire_nill11iO_dataout AND NOT(niOO100il); + wire_niliOOlO_dataout <= wire_nill11li_dataout AND NOT(niOO100il); + wire_niliOOO_dataout <= niiil0l WHEN niOO0liOO = '1' ELSE wire_nilOOiO_dataout; + wire_niliOOOi_dataout <= wire_nil00Oil_dataout OR niOO100il; + wire_niliOOOl_dataout <= wire_nill11ll_dataout AND NOT(niOO100iO); + wire_niliOOOO_dataout <= wire_nill11lO_dataout AND NOT(niOO100iO); + wire_nill000i_dataout <= wire_nill00OO_dataout OR niOO10i1l; + wire_nill000l_dataout <= wire_nill0i1i_dataout OR niOO10i1l; + wire_nill000O_dataout <= wire_nill0i1l_dataout OR niOO10i1l; + wire_nill001i_dataout <= wire_nill00lO_dataout AND NOT(niOO10i1l); + wire_nill001l_dataout <= wire_nill00Oi_dataout AND NOT(niOO10i1l); + wire_nill001O_dataout <= wire_nill00Ol_dataout OR niOO10i1l; + wire_nill00i_dataout <= niiiOiO WHEN niOO0liOO = '1' ELSE wire_niO11Oi_dataout; + wire_nill00ii_dataout <= wire_nill0i1O_dataout OR niOO10i1l; + wire_nill00il_dataout <= wire_nill0i0i_dataout OR niOO10i1l; + wire_nill00iO_dataout <= wire_nill0i0l_dataout AND NOT(niOO10i1l); + wire_nill00l_dataout <= niiiOli WHEN niOO0liOO = '1' ELSE wire_niO11Ol_dataout; + wire_nill00li_dataout <= wire_nill0i0O_dataout OR niOO10i1l; + wire_nill00ll_dataout <= wire_nill0iii_dataout OR niOO10i1l; + wire_nill00lO_dataout <= wire_nill0iil_dataout OR niOO10i1O; + wire_nill00O_dataout <= niiiOll WHEN niOO0liOO = '1' ELSE wire_niO11OO_dataout; + wire_nill00Oi_dataout <= wire_nill0iiO_dataout OR niOO10i1O; + wire_nill00Ol_dataout <= wire_nill0ili_dataout OR niOO10i1O; + wire_nill00OO_dataout <= wire_nill0ill_dataout AND NOT(niOO10i1O); + wire_nill010i_dataout <= wire_nill01OO_dataout AND NOT(niOO100OO); + wire_nill010l_dataout <= wire_nill001i_dataout AND NOT(niOO10i1i); + wire_nill010O_dataout <= wire_nill001l_dataout OR niOO10i1i; + wire_nill011i_dataout <= wire_nill01lO_dataout OR niOO100OO; + wire_nill011l_dataout <= wire_nill01Oi_dataout OR niOO100OO; + wire_nill011O_dataout <= wire_nill01Ol_dataout OR niOO100OO; + wire_nill01i_dataout <= niiiO0O WHEN niOO0liOO = '1' ELSE wire_niO11li_dataout; + wire_nill01ii_dataout <= wire_nill001O_dataout OR niOO10i1i; + wire_nill01il_dataout <= wire_nill000i_dataout AND NOT(niOO10i1i); + wire_nill01iO_dataout <= wire_nill000l_dataout AND NOT(niOO10i1i); + wire_nill01l_dataout <= niiiOii WHEN niOO0liOO = '1' ELSE wire_niO11ll_dataout; + wire_nill01li_dataout <= wire_nill000O_dataout OR niOO10i1i; + wire_nill01ll_dataout <= wire_nill00ii_dataout AND NOT(niOO10i1i); + wire_nill01lO_dataout <= wire_nill00il_dataout AND NOT(niOO10i1i); + wire_nill01O_dataout <= niiiOil WHEN niOO0liOO = '1' ELSE wire_niO11lO_dataout; + wire_nill01Oi_dataout <= wire_nill00iO_dataout OR niOO10i1i; + wire_nill01Ol_dataout <= wire_nill00li_dataout AND NOT(niOO10i1i); + wire_nill01OO_dataout <= wire_nill00ll_dataout OR niOO10i1i; + wire_nill0i0i_dataout <= wire_nill0iOO_dataout OR niOO10i1O; + wire_nill0i0l_dataout <= wire_nill0l1i_dataout OR niOO10i1O; + wire_nill0i0O_dataout <= wire_nill0l1l_dataout OR niOO10i1O; + wire_nill0i1i_dataout <= wire_nill0ilO_dataout AND NOT(niOO10i1O); + wire_nill0i1l_dataout <= wire_nill0iOi_dataout OR niOO10i1O; + wire_nill0i1O_dataout <= wire_nill0iOl_dataout OR niOO10i1O; + wire_nill0ii_dataout <= niiiOlO WHEN niOO0liOO = '1' ELSE wire_niO101i_dataout; + wire_nill0iii_dataout <= wire_nill0l1O_dataout AND NOT(niOO10i1O); + wire_nill0iil_dataout <= wire_nill0l0i_dataout OR niOO10i0i; + wire_nill0iiO_dataout <= wire_nill0l0l_dataout OR niOO10i0i; + wire_nill0il_dataout <= niiiOOi WHEN niOO0liOO = '1' ELSE wire_niO101l_dataout; + wire_nill0ili_dataout <= wire_nill0l0O_dataout AND NOT(niOO10i0i); + wire_nill0ill_dataout <= wire_nill0lii_dataout OR niOO10i0i; + wire_nill0ilO_dataout <= wire_nill0lil_dataout OR niOO10i0i; + wire_nill0iO_dataout <= niiiOOl WHEN niOO0liOO = '1' ELSE wire_niO101O_dataout; + wire_nill0iOi_dataout <= wire_nill0liO_dataout AND NOT(niOO10i0i); + wire_nill0iOl_dataout <= wire_nill0lli_dataout OR niOO10i0i; + wire_nill0iOO_dataout <= wire_nill0lll_dataout AND NOT(niOO10i0i); + wire_nill0l0i_dataout <= wire_nill0lOO_dataout AND NOT(niOO10i0l); + wire_nill0l0l_dataout <= wire_nill0O1i_dataout OR niOO10i0l; + wire_nill0l0O_dataout <= wire_nill0O1l_dataout OR niOO10i0l; + wire_nill0l1i_dataout <= wire_nill0llO_dataout AND NOT(niOO10i0i); + wire_nill0l1l_dataout <= wire_nill0lOi_dataout OR niOO10i0i; + wire_nill0l1O_dataout <= wire_nill0lOl_dataout AND NOT(niOO10i0i); + wire_nill0li_dataout <= wire_niO100i_dataout OR niOO0liOO; + wire_nill0lii_dataout <= wire_nill0O1O_dataout AND NOT(niOO10i0l); + wire_nill0lil_dataout <= wire_nill0O0i_dataout AND NOT(niOO10i0l); + wire_nill0liO_dataout <= wire_nill0O0l_dataout OR niOO10i0l; + wire_nill0ll_dataout <= ni0Ol0O WHEN niOO0liOO = '1' ELSE wire_niO100l_dataout; + wire_nill0lli_dataout <= wire_nill0O0O_dataout AND NOT(niOO10i0l); + wire_nill0lll_dataout <= wire_nill0Oii_dataout AND NOT(niOO10i0l); + wire_nill0llO_dataout <= wire_nill0Oil_dataout OR niOO10i0l; + wire_nill0lO_dataout <= nii1l0l WHEN niOO0liOO = '1' ELSE wire_niO100O_dataout; + wire_nill0lOi_dataout <= wire_nill0OiO_dataout OR niOO10i0l; + wire_nill0lOl_dataout <= wire_nill0Oli_dataout OR niOO10i0l; + wire_nill0lOO_dataout <= wire_nill0Oll_dataout AND NOT(niOO10i0O); + wire_nill0O0i_dataout <= wire_nill0OOO_dataout OR niOO10i0O; + wire_nill0O0l_dataout <= wire_nilli11i_dataout OR niOO10i0O; + wire_nill0O0O_dataout <= wire_nilli11l_dataout OR niOO10i0O; + wire_nill0O1i_dataout <= wire_nill0OlO_dataout AND NOT(niOO10i0O); + wire_nill0O1l_dataout <= wire_nill0OOi_dataout OR niOO10i0O; + wire_nill0O1O_dataout <= wire_nill0OOl_dataout OR niOO10i0O; + wire_nill0Oi_dataout <= nii1l0O WHEN niOO0liOO = '1' ELSE wire_niO10ii_dataout; + wire_nill0Oii_dataout <= wire_nilli11O_dataout OR niOO10i0O; + wire_nill0Oil_dataout <= wire_nilli10i_dataout OR niOO10i0O; + wire_nill0OiO_dataout <= wire_nilli10l_dataout OR niOO10i0O; + wire_nill0Ol_dataout <= nii1lii WHEN niOO0liOO = '1' ELSE wire_niO10il_dataout; + wire_nill0Oli_dataout <= wire_nilli10O_dataout AND NOT(niOO10i0O); + wire_nill0Oll_dataout <= wire_nilli1ii_dataout OR niOO10iii; + wire_nill0OlO_dataout <= wire_nilli1il_dataout OR niOO10iii; + wire_nill0OO_dataout <= nii1lil WHEN niOO0liOO = '1' ELSE wire_niO10iO_dataout; + wire_nill0OOi_dataout <= wire_nilli1iO_dataout OR niOO10iii; + wire_nill0OOl_dataout <= wire_nilli1li_dataout AND NOT(niOO10iii); + wire_nill0OOO_dataout <= wire_nilli1ll_dataout AND NOT(niOO10iii); + wire_nill100i_dataout <= wire_nill1i1i_dataout AND NOT(niOO100li); + wire_nill100l_dataout <= wire_nill1i1l_dataout AND NOT(niOO100li); + wire_nill100O_dataout <= wire_nill1i1O_dataout OR niOO100li; + wire_nill101i_dataout <= wire_nill10Oi_dataout OR niOO100li; + wire_nill101l_dataout <= wire_nill10Ol_dataout OR niOO100li; + wire_nill101O_dataout <= wire_nill10OO_dataout OR niOO100li; + wire_nill10i_dataout <= niiiliO WHEN niOO0liOO = '1' ELSE wire_nilOOOi_dataout; + wire_nill10ii_dataout <= wire_nill1i0i_dataout OR niOO100li; + wire_nill10il_dataout <= wire_nill1i0l_dataout OR niOO100ll; + wire_nill10iO_dataout <= wire_nill1i0O_dataout OR niOO100ll; + wire_nill10l_dataout <= niiilli WHEN niOO0liOO = '1' ELSE wire_nilOOOl_dataout; + wire_nill10li_dataout <= wire_nill1iii_dataout AND NOT(niOO100ll); + wire_nill10ll_dataout <= wire_nill1iil_dataout OR niOO100ll; + wire_nill10lO_dataout <= wire_nill1iiO_dataout OR niOO100ll; + wire_nill10O_dataout <= niiilll WHEN niOO0liOO = '1' ELSE wire_nilOOOO_dataout; + wire_nill10Oi_dataout <= wire_nill1ili_dataout AND NOT(niOO100ll); + wire_nill10Ol_dataout <= wire_nill1ill_dataout OR niOO100ll; + wire_nill10OO_dataout <= wire_nill1ilO_dataout OR niOO100ll; + wire_nill110i_dataout <= wire_nill101i_dataout OR niOO100iO; + wire_nill110l_dataout <= wire_nill101l_dataout OR niOO100iO; + wire_nill110O_dataout <= wire_nill101O_dataout OR niOO100iO; + wire_nill111i_dataout <= wire_nill11Oi_dataout OR niOO100iO; + wire_nill111l_dataout <= wire_nill11Ol_dataout OR niOO100iO; + wire_nill111O_dataout <= wire_nill11OO_dataout OR niOO100iO; + wire_nill11i_dataout <= niiil0O WHEN niOO0liOO = '1' ELSE wire_nilOOli_dataout; + wire_nill11ii_dataout <= wire_nill100i_dataout AND NOT(niOO100iO); + wire_nill11il_dataout <= wire_nill100l_dataout AND NOT(niOO100iO); + wire_nill11iO_dataout <= wire_nill100O_dataout AND NOT(niOO100iO); + wire_nill11l_dataout <= niiilii WHEN niOO0liOO = '1' ELSE wire_nilOOll_dataout; + wire_nill11li_dataout <= wire_nill10ii_dataout OR niOO100iO; + wire_nill11ll_dataout <= wire_nill10il_dataout OR niOO100li; + wire_nill11lO_dataout <= wire_nill10iO_dataout OR niOO100li; + wire_nill11O_dataout <= niiilil WHEN niOO0liOO = '1' ELSE wire_nilOOlO_dataout; + wire_nill11Oi_dataout <= wire_nill10li_dataout OR niOO100li; + wire_nill11Ol_dataout <= wire_nill10ll_dataout AND NOT(niOO100li); + wire_nill11OO_dataout <= wire_nill10lO_dataout AND NOT(niOO100li); + wire_nill1i0i_dataout <= wire_nill1l1i_dataout AND NOT(niOO100ll); + wire_nill1i0l_dataout <= wire_nill1l1l_dataout AND NOT(niOO100lO); + wire_nill1i0O_dataout <= wire_nill1l1O_dataout OR niOO100lO; + wire_nill1i1i_dataout <= wire_nill1iOi_dataout AND NOT(niOO100ll); + wire_nill1i1l_dataout <= wire_nill1iOl_dataout OR niOO100ll; + wire_nill1i1O_dataout <= wire_nill1iOO_dataout OR niOO100ll; + wire_nill1ii_dataout <= niiillO WHEN niOO0liOO = '1' ELSE wire_niO111i_dataout; + wire_nill1iii_dataout <= wire_nill1l0i_dataout OR niOO100lO; + wire_nill1iil_dataout <= wire_nill1l0l_dataout AND NOT(niOO100lO); + wire_nill1iiO_dataout <= wire_nill1l0O_dataout AND NOT(niOO100lO); + wire_nill1il_dataout <= niiilOi WHEN niOO0liOO = '1' ELSE wire_niO111l_dataout; + wire_nill1ili_dataout <= wire_nill1lii_dataout OR niOO100lO; + wire_nill1ill_dataout <= wire_nill1lil_dataout AND NOT(niOO100lO); + wire_nill1ilO_dataout <= wire_nill1liO_dataout AND NOT(niOO100lO); + wire_nill1iO_dataout <= niiilOl WHEN niOO0liOO = '1' ELSE wire_niO111O_dataout; + wire_nill1iOi_dataout <= wire_nill1lli_dataout OR niOO100lO; + wire_nill1iOl_dataout <= wire_nill1lll_dataout AND NOT(niOO100lO); + wire_nill1iOO_dataout <= wire_nill1llO_dataout AND NOT(niOO100lO); + wire_nill1l0i_dataout <= wire_nill1lOO_dataout OR niOO100Oi; + wire_nill1l0l_dataout <= wire_nill1O1i_dataout OR niOO100Oi; + wire_nill1l0O_dataout <= wire_nill1O1l_dataout OR niOO100Oi; + wire_nill1l1i_dataout <= wire_nil0iiiO_dataout OR niOO100lO; + wire_nill1l1l_dataout <= wire_nill1lOi_dataout AND NOT(niOO100Oi); + wire_nill1l1O_dataout <= wire_nill1lOl_dataout AND NOT(niOO100Oi); + wire_nill1li_dataout <= niiilOO WHEN niOO0liOO = '1' ELSE wire_niO110i_dataout; + wire_nill1lii_dataout <= wire_nill1O1O_dataout OR niOO100Oi; + wire_nill1lil_dataout <= wire_nill1O0i_dataout OR niOO100Oi; + wire_nill1liO_dataout <= wire_nill1O0l_dataout OR niOO100Oi; + wire_nill1ll_dataout <= niiiO1i WHEN niOO0liOO = '1' ELSE wire_niO110l_dataout; + wire_nill1lli_dataout <= wire_nill1O0O_dataout AND NOT(niOO100Oi); + wire_nill1lll_dataout <= wire_nill1Oii_dataout AND NOT(niOO100Oi); + wire_nill1llO_dataout <= wire_nill1Oil_dataout OR niOO100Oi; + wire_nill1lO_dataout <= niiiO1l WHEN niOO0liOO = '1' ELSE wire_niO110O_dataout; + wire_nill1lOi_dataout <= wire_nill1OiO_dataout OR niOO100Ol; + wire_nill1lOl_dataout <= wire_nill1Oli_dataout OR niOO100Ol; + wire_nill1lOO_dataout <= wire_nill1Oll_dataout OR niOO100Ol; + wire_nill1O0i_dataout <= wire_nill1OOO_dataout OR niOO100Ol; + wire_nill1O0l_dataout <= wire_nill011i_dataout OR niOO100Ol; + wire_nill1O0O_dataout <= wire_nill011l_dataout AND NOT(niOO100Ol); + wire_nill1O1i_dataout <= wire_nill1OlO_dataout AND NOT(niOO100Ol); + wire_nill1O1l_dataout <= wire_nill1OOi_dataout AND NOT(niOO100Ol); + wire_nill1O1O_dataout <= wire_nill1OOl_dataout OR niOO100Ol; + wire_nill1Oi_dataout <= niiiO1O WHEN niOO0liOO = '1' ELSE wire_niO11ii_dataout; + wire_nill1Oii_dataout <= wire_nill011O_dataout OR niOO100Ol; + wire_nill1Oil_dataout <= wire_nill010i_dataout OR niOO100Ol; + wire_nill1OiO_dataout <= wire_nill010l_dataout OR niOO100OO; + wire_nill1Ol_dataout <= niiiO0i WHEN niOO0liOO = '1' ELSE wire_niO11il_dataout; + wire_nill1Oli_dataout <= wire_nill010O_dataout OR niOO100OO; + wire_nill1Oll_dataout <= wire_nill01ii_dataout AND NOT(niOO100OO); + wire_nill1OlO_dataout <= wire_nill01il_dataout OR niOO100OO; + wire_nill1OO_dataout <= niiiO0l WHEN niOO0liOO = '1' ELSE wire_niO11iO_dataout; + wire_nill1OOi_dataout <= wire_nill01iO_dataout OR niOO100OO; + wire_nill1OOl_dataout <= wire_nill01li_dataout AND NOT(niOO100OO); + wire_nill1OOO_dataout <= wire_nill01ll_dataout OR niOO100OO; + wire_nilli00i_dataout <= wire_nilli0Ol_dataout AND NOT(niOO10iiO); + wire_nilli00l_dataout <= wire_nilli0OO_dataout AND NOT(niOO10iiO); + wire_nilli00O_dataout <= wire_nillii1i_dataout OR niOO10iiO; + wire_nilli01i_dataout <= wire_nilli0lO_dataout AND NOT(niOO10iil); + wire_nilli01l_dataout <= niOO10iiO AND NOT(niOO10iil); + wire_nilli01O_dataout <= wire_nilli0Oi_dataout OR niOO10iiO; + wire_nilli0i_dataout <= nii1llO WHEN niOO0liOO = '1' ELSE wire_niO10Oi_dataout; + wire_nilli0ii_dataout <= wire_nillii1l_dataout OR niOO10iiO; + wire_nilli0il_dataout <= wire_nillii1O_dataout OR niOO10iiO; + wire_nilli0iO_dataout <= wire_nillii0i_dataout OR niOO10iiO; + wire_nilli0l_dataout <= nii1lOi WHEN niOO0liOO = '1' ELSE wire_niO10Ol_dataout; + wire_nilli0li_dataout <= wire_nillii0l_dataout AND NOT(niOO10iiO); + wire_nilli0ll_dataout <= wire_nillii0O_dataout OR niOO10iiO; + wire_nilli0lO_dataout <= wire_nilliiii_dataout AND NOT(niOO10iiO); + wire_nilli0O_dataout <= nii1lOl WHEN niOO0liOO = '1' ELSE wire_niO10OO_dataout; + wire_nilli0Oi_dataout <= wire_nilliiil_dataout AND NOT(niOO10ili); + wire_nilli0Ol_dataout <= wire_nilliiiO_dataout AND NOT(niOO10ili); + wire_nilli0OO_dataout <= wire_nilliili_dataout OR niOO10ili; + wire_nilli10i_dataout <= wire_nilli1OO_dataout AND NOT(niOO10iii); + wire_nilli10l_dataout <= wire_nilli01i_dataout OR niOO10iii; + wire_nilli10O_dataout <= wire_nilli01l_dataout AND NOT(niOO10iii); + wire_nilli11i_dataout <= wire_nilli1lO_dataout OR niOO10iii; + wire_nilli11l_dataout <= wire_nilli1Oi_dataout OR niOO10iii; + wire_nilli11O_dataout <= wire_nilli1Ol_dataout AND NOT(niOO10iii); + wire_nilli1i_dataout <= nii1liO WHEN niOO0liOO = '1' ELSE wire_niO10li_dataout; + wire_nilli1ii_dataout <= wire_nilli01O_dataout OR niOO10iil; + wire_nilli1il_dataout <= wire_nilli00i_dataout OR niOO10iil; + wire_nilli1iO_dataout <= wire_nilli00l_dataout AND NOT(niOO10iil); + wire_nilli1l_dataout <= nii1lli WHEN niOO0liOO = '1' ELSE wire_niO10ll_dataout; + wire_nilli1li_dataout <= wire_nilli00O_dataout OR niOO10iil; + wire_nilli1ll_dataout <= wire_nilli0ii_dataout OR niOO10iil; + wire_nilli1lO_dataout <= wire_nilli0il_dataout AND NOT(niOO10iil); + wire_nilli1O_dataout <= nii1lll WHEN niOO0liOO = '1' ELSE wire_niO10lO_dataout; + wire_nilli1Oi_dataout <= wire_nilli0iO_dataout AND NOT(niOO10iil); + wire_nilli1Ol_dataout <= wire_nilli0li_dataout OR niOO10iil; + wire_nilli1OO_dataout <= wire_nilli0ll_dataout OR niOO10iil; + wire_nillii0i_dataout <= wire_nilliiOO_dataout AND NOT(niOO10ili); + wire_nillii0l_dataout <= wire_nilliiOl_dataout AND NOT(niOO10ili); + wire_nillii0O_dataout <= wire_nilliiOO_dataout OR niOO10ili; + wire_nillii1i_dataout <= wire_nilliill_dataout AND NOT(niOO10ili); + wire_nillii1l_dataout <= wire_nilliilO_dataout AND NOT(niOO10ili); + wire_nillii1O_dataout <= wire_nilliiOi_dataout OR niOO10ili; + wire_nilliii_dataout <= nii1lOO WHEN niOO0liOO = '1' ELSE wire_niO1i1i_dataout; + wire_nilliiii_dataout <= wire_nillil1i_dataout OR niOO10ili; + wire_nilliiil_dataout <= wire_nillil1l_dataout OR niOO10ill; + wire_nilliiiO_dataout <= wire_nillil1O_dataout OR niOO10ill; + wire_nilliil_dataout <= nii1O1i WHEN niOO0liOO = '1' ELSE wire_niO1i1l_dataout; + wire_nilliili_dataout <= wire_nillil0i_dataout AND NOT(niOO10ill); + wire_nilliill_dataout <= wire_nillil0l_dataout OR niOO10ill; + wire_nilliilO_dataout <= wire_nillil0O_dataout OR niOO10ill; + wire_nilliiO_dataout <= nii1O1l WHEN niOO0liOO = '1' ELSE wire_niO1i1O_dataout; + wire_nilliiOi_dataout <= wire_nillilii_dataout OR niOO10ill; + wire_nilliiOl_dataout <= niOO10ilO OR niOO10ill; + wire_nilliiOO_dataout <= wire_nillilil_dataout OR niOO10ill; + wire_nillil0i_dataout <= wire_nillilll_dataout AND NOT(niOO10ilO); + wire_nillil0l_dataout <= wire_nillillO_dataout OR niOO10ilO; + wire_nillil0O_dataout <= wire_nillilOi_dataout OR niOO10ilO; + wire_nillil1i_dataout <= wire_nilliliO_dataout AND NOT(niOO10ill); + wire_nillil1l_dataout <= wire_nillillO_dataout AND NOT(niOO10ilO); + wire_nillil1O_dataout <= wire_nillilli_dataout OR niOO10ilO; + wire_nillili_dataout <= nii1O1O WHEN niOO0liOO = '1' ELSE wire_niO1i0i_dataout; + wire_nillilii_dataout <= wire_nillilOl_dataout AND NOT(niOO10ilO); + wire_nillilil_dataout <= wire_nillilOl_dataout OR niOO10ilO; + wire_nilliliO_dataout <= wire_nillilOO_dataout AND NOT(niOO10ilO); + wire_nillill_dataout <= nii1O0i WHEN niOO0liOO = '1' ELSE wire_niO1i0l_dataout; + wire_nillilli_dataout <= wire_nilliO1i_dataout AND NOT(niOO10iOi); + wire_nillilll_dataout <= wire_nilliO1l_dataout AND NOT(niOO10iOi); + wire_nillillO_dataout <= niOO10iOl AND NOT(niOO10iOi); + wire_nillilO_dataout <= nii1O0l WHEN niOO0liOO = '1' ELSE wire_niO1i0O_dataout; + wire_nillilOi_dataout <= wire_nilliO1O_dataout AND NOT(niOO10iOi); + wire_nillilOl_dataout <= wire_w_lg_niOO10iOl9024w(0) OR niOO10iOi; + wire_nillilOO_dataout <= niOO10iOl OR niOO10iOi; + wire_nilliO0l_dataout <= k_conf(200) WHEN niOO10l0l = '1' ELSE wire_nilliOOi_dataout; + wire_nilliO0O_dataout <= k_conf(201) WHEN niOO10l0l = '1' ELSE wire_nilliOOl_dataout; + wire_nilliO1i_dataout <= wire_w_lg_niOO10iOO9023w(0) AND NOT(niOO10iOl); + wire_nilliO1l_dataout <= niOO10iOO AND NOT(niOO10iOl); + wire_nilliO1O_dataout <= niOO10iOO OR niOO10iOl; + wire_nilliOi_dataout <= nii1O0O WHEN niOO0liOO = '1' ELSE wire_niO1iii_dataout; + wire_nilliOii_dataout <= k_conf(202) WHEN niOO10l0l = '1' ELSE wire_nilliOOO_dataout; + wire_nilliOil_dataout <= k_conf(203) WHEN niOO10l0l = '1' ELSE wire_nilll11i_dataout; + wire_nilliOiO_dataout <= k_conf(204) WHEN niOO10l0l = '1' ELSE wire_nilll11l_dataout; + wire_nilliOl_dataout <= nii1Oii WHEN niOO0liOO = '1' ELSE wire_niO1iil_dataout; + wire_nilliOli_dataout <= k_conf(205) WHEN niOO10l0l = '1' ELSE wire_nilll11O_dataout; + wire_nilliOll_dataout <= k_conf(206) WHEN niOO10l0l = '1' ELSE wire_nilll10i_dataout; + wire_nilliOlO_dataout <= k_conf(207) WHEN niOO10l0l = '1' ELSE wire_nilll10l_dataout; + wire_nilliOO_dataout <= nii1Oil WHEN niOO0liOO = '1' ELSE wire_niO1iiO_dataout; + wire_nilliOOi_dataout <= k_conf(192) WHEN niOO10l0i = '1' ELSE wire_nilll10O_dataout; + wire_nilliOOl_dataout <= k_conf(193) WHEN niOO10l0i = '1' ELSE wire_nilll1ii_dataout; + wire_nilliOOO_dataout <= k_conf(194) WHEN niOO10l0i = '1' ELSE wire_nilll1il_dataout; + wire_nilll00i_dataout <= wire_nilOi0li_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll00l_dataout <= wire_nilOi0iO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll00O_dataout <= wire_nilOi0ll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0i_dataout <= nii1OlO WHEN niOO0liOO = '1' ELSE wire_niO1iOi_dataout; + wire_nilll0ii_dataout <= wire_nilOi00i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0il_dataout <= wire_nilOi00O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0iO_dataout <= wire_nilOi0il_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0l_dataout <= nii1OOi WHEN niOO0liOO = '1' ELSE wire_niO1iOl_dataout; + wire_nilll0li_dataout <= nl01ii1Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0ll_dataout <= nl01ii1Ol AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0lO_dataout <= wire_nilOi0ii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0O_dataout <= nii1OOl WHEN niOO0liOO = '1' ELSE wire_niO1iOO_dataout; + wire_nilll0Oi_dataout <= nl01ii1lO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0Ol_dataout <= nl01ii1li AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll0OO_dataout <= nl0100O1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilll10i_dataout <= k_conf(198) WHEN niOO10l0i = '1' ELSE wire_nilll1lO_dataout; + wire_nilll10l_dataout <= k_conf(199) WHEN niOO10l0i = '1' ELSE wire_nilll1Oi_dataout; + wire_nilll10O_dataout <= k_conf(352) WHEN niOO10l1l = '1' ELSE k_conf(344); + wire_nilll11i_dataout <= k_conf(195) WHEN niOO10l0i = '1' ELSE wire_nilll1iO_dataout; + wire_nilll11l_dataout <= k_conf(196) WHEN niOO10l0i = '1' ELSE wire_nilll1li_dataout; + wire_nilll11O_dataout <= k_conf(197) WHEN niOO10l0i = '1' ELSE wire_nilll1ll_dataout; + wire_nilll1i_dataout <= nii1OiO WHEN niOO0liOO = '1' ELSE wire_niO1ili_dataout; + wire_nilll1ii_dataout <= k_conf(353) WHEN niOO10l1l = '1' ELSE k_conf(345); + wire_nilll1il_dataout <= k_conf(354) WHEN niOO10l1l = '1' ELSE k_conf(346); + wire_nilll1iO_dataout <= k_conf(355) WHEN niOO10l1l = '1' ELSE k_conf(347); + wire_nilll1l_dataout <= nii1Oli WHEN niOO0liOO = '1' ELSE wire_niO1ill_dataout; + wire_nilll1li_dataout <= k_conf(356) WHEN niOO10l1l = '1' ELSE k_conf(348); + wire_nilll1ll_dataout <= k_conf(357) WHEN niOO10l1l = '1' ELSE k_conf(349); + wire_nilll1lO_dataout <= k_conf(358) WHEN niOO10l1l = '1' ELSE k_conf(350); + wire_nilll1O_dataout <= nii1Oll WHEN niOO0liOO = '1' ELSE wire_niO1ilO_dataout; + wire_nilll1Oi_dataout <= k_conf(359) WHEN niOO10l1l = '1' ELSE k_conf(351); + wire_nillli0i_dataout <= wire_nilOiOli_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillli0l_dataout <= wire_nilOiOll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillli0O_dataout <= wire_nilOiOlO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillli1i_dataout <= wire_nilOiOii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillli1l_dataout <= wire_nilOiOil_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillli1O_dataout <= wire_nilOiOiO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllii_dataout <= nii1OOO WHEN niOO0liOO = '1' ELSE wire_niO1l1i_dataout; + wire_nillliii_dataout <= wire_nilOiOOi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillliil_dataout <= wire_nilOiOOl_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillliiO_dataout <= wire_nilOiOOO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllil_dataout <= nii011i WHEN niOO0liOO = '1' ELSE wire_niO1l1l_dataout; + wire_nilllili_dataout <= wire_nilOl11i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllill_dataout <= wire_nilOl11l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllilO_dataout <= wire_nilOl11O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillliO_dataout <= nii011l WHEN niOO0liOO = '1' ELSE wire_niO1l1O_dataout; + wire_nillliOi_dataout <= wire_nilOl10i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillliOl_dataout <= wire_nilOl10l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillliOO_dataout <= wire_nilOl10O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillll0i_dataout <= wire_nilOl1li_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillll0l_dataout <= wire_nilOl1ll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillll0O_dataout <= wire_nilOl1lO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillll1i_dataout <= wire_nilOl1ii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillll1l_dataout <= wire_nilOl1il_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillll1O_dataout <= wire_nilOl1iO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllli_dataout <= nii011O WHEN niOO0liOO = '1' ELSE wire_niO1l0i_dataout; + wire_nillllii_dataout <= wire_nilOl1Oi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillllil_dataout <= wire_nilOl1Ol_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllliO_dataout <= wire_nilOl1OO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllll_dataout <= nii010i WHEN niOO0liOO = '1' ELSE wire_niO1l0l_dataout; + wire_nillllli_dataout <= wire_nilOi00l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillllll_dataout <= niOO10O0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllllO_dataout <= wire_nilOi11l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillllO_dataout <= nii010l WHEN niOO0liOO = '1' ELSE wire_niO1l0O_dataout; + wire_nillllOi_dataout <= wire_nilOi11i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillllOl_dataout <= wire_nl11Oilii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillllOO_dataout <= nl10ilOOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllO0i_dataout <= wire_nliliilOl_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllO0l_dataout <= wire_nliliilOO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllO0O_dataout <= wire_nliliiO1i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllO1i_dataout <= nl10iOO1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllO1l_dataout <= wire_nilOO01O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllO1O_dataout <= wire_nliliilOi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOi_dataout <= nii010O WHEN niOO0liOO = '1' ELSE wire_niO1lii_dataout; + wire_nilllOii_dataout <= nlil01i0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOil_dataout <= nlil01i1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOiO_dataout <= nlil1llOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOl_dataout <= nii01ii WHEN niOO0liOO = '1' ELSE wire_niO1lil_dataout; + wire_nilllOli_dataout <= nlil1i01i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOll_dataout <= nlil1i01l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOlO_dataout <= nlil1i01O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOO_dataout <= nii01il WHEN niOO0liOO = '1' ELSE wire_niO1liO_dataout; + wire_nilllOOi_dataout <= nlil1i00i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOOl_dataout <= wire_nilOO1il_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilllOOO_dataout <= wire_nilOO1iO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO00i_dataout <= niOO10llO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO00l_dataout <= nl10iO1li AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO00O_dataout <= niOO10lOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO01i_dataout <= (niOO10lli OR niOO10liO) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO01l_dataout <= niOO1i0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO01O_dataout <= niOO10lll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0i_dataout <= nii01lO WHEN niOO0liOO = '1' ELSE wire_niO1lOi_dataout; + wire_nillO0ii_dataout <= niOO10lOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0il_dataout <= nl1Ol011O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0iO_dataout <= (wire_nl011Ol1O_w_lg_dataout8960w(0) AND wire_nliliO10i_w_lg_w_lg_w_lg_w_lg_nl1OOii1O8962w8964w8965w8966w(0)) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0l_dataout <= nii01Oi WHEN niOO0liOO = '1' ELSE wire_niO1lOl_dataout; + wire_nillO0li_dataout <= wire_nlill0Oll_w_lg_nl10lliil8959w(0) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0ll_dataout <= wire_nl011i1iO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0lO_dataout <= wire_nl011i1li_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0O_dataout <= nii01Ol WHEN niOO0liOO = '1' ELSE wire_niO1lOO_dataout; + wire_nillO0Oi_dataout <= wire_nl011i1ll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0Ol_dataout <= nl1OilllO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO0OO_dataout <= wire_nl011i10O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO10i_dataout <= wire_nilOOO0i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO10l_dataout <= wire_nilOOO0l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO10O_dataout <= wire_nilOOi0O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO11i_dataout <= (nl0l010iO AND nli11OOOO) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO11l_dataout <= wire_nilOO00O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO11O_dataout <= wire_niO1110l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1i_dataout <= nii01iO WHEN niOO0liOO = '1' ELSE wire_niO1lli_dataout; + wire_nillO1ii_dataout <= wire_nilOOiii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1il_dataout <= wire_nilOOiil_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1iO_dataout <= wire_nilOOiiO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1l_dataout <= nii01li WHEN niOO0liOO = '1' ELSE wire_niO1lll_dataout; + wire_nillO1li_dataout <= wire_nilOOili_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1ll_dataout <= wire_nilOOill_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1lO_dataout <= wire_nilOOilO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1O_dataout <= nii01ll WHEN niOO0liOO = '1' ELSE wire_niO1llO_dataout; + wire_nillO1Oi_dataout <= nlii11i0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1Ol_dataout <= niOO10lii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillO1OO_dataout <= niOO10lil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOi0i_dataout <= nl1OOii1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOi0l_dataout <= wire_nl10il1ll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOi0O_dataout <= wire_nl10il1lO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOi1i_dataout <= wire_nl011i1ii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOi1l_dataout <= nl1OO010i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOi1O_dataout <= nl1OOii1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOii_dataout <= nii01OO WHEN niOO0liOO = '1' ELSE wire_niO1O1i_dataout; + wire_nillOiii_dataout <= wire_nl10il1Oi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOiil_dataout <= wire_nl10il1Ol_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOiiO_dataout <= wire_nl1i11lOi_o(1) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOil_dataout <= nii001i WHEN niOO0liOO = '1' ELSE wire_niO1O1l_dataout; + wire_nillOili_dataout <= wire_nl1i11lOi_o(2) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOill_dataout <= wire_nl1i11lOi_o(3) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOilO_dataout <= wire_nl1i11lOi_o(4) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOiO_dataout <= nii001l WHEN niOO0liOO = '1' ELSE wire_niO1O1O_dataout; + wire_nillOiOi_dataout <= wire_nl1i11lOi_o(5) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOiOl_dataout <= wire_nl1i11lOi_o(6) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOiOO_dataout <= wire_nl1i11lOi_o(7) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOl0i_dataout <= wire_nl1i11llO_o(3) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOl0l_dataout <= wire_nl1i11llO_o(4) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOl0O_dataout <= wire_nl1i11llO_o(5) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOl1i_dataout <= wire_nl1i11lOi_o(8) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOl1l_dataout <= wire_nl1i11llO_o(1) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOl1O_dataout <= wire_nl1i11llO_o(2) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOli_dataout <= nii001O WHEN niOO0liOO = '1' ELSE wire_niO1O0i_dataout; + wire_nillOlii_dataout <= wire_nl1i11llO_o(6) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOlil_dataout <= wire_nl1i11llO_o(7) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOliO_dataout <= wire_nl1i11llO_o(8) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOll_dataout <= nii000i WHEN niOO0liOO = '1' ELSE wire_niO1O0l_dataout; + wire_nillOlli_dataout <= wire_nl1i11llO_o(9) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOlll_dataout <= wire_nl1i11llO_o(10) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOllO_dataout <= wire_nl1i11llO_o(11) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOlO_dataout <= nii000l WHEN niOO0liOO = '1' ELSE wire_niO1O0O_dataout; + wire_nillOlOi_dataout <= wire_nl1i11llO_o(12) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOlOl_dataout <= wire_nl1i11lll_o(1) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOlOO_dataout <= wire_nl1i11lll_o(2) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOO0i_dataout <= wire_nl1i11lll_o(6) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOO0l_dataout <= wire_nl1i11lll_o(7) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOO0O_dataout <= wire_nl1i11lll_o(8) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOO1i_dataout <= wire_nl1i11lll_o(3) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOO1l_dataout <= wire_nl1i11lll_o(4) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOO1O_dataout <= wire_nl1i11lll_o(5) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOi_dataout <= nii000O WHEN niOO0liOO = '1' ELSE wire_niO1Oii_dataout; + wire_nillOOii_dataout <= wire_nl1i11lli_o(1) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOil_dataout <= wire_nl1i11lli_o(2) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOiO_dataout <= wire_nl1i11lli_o(3) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOl_dataout <= nii00ii WHEN niOO0liOO = '1' ELSE wire_niO1Oil_dataout; + wire_nillOOli_dataout <= wire_nl1i11lli_o(4) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOll_dataout <= wire_nl1i11lli_o(5) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOlO_dataout <= wire_nl1i11lli_o(6) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOO_dataout <= nii00il WHEN niOO0liOO = '1' ELSE wire_niO1OiO_dataout; + wire_nillOOOi_dataout <= wire_nl1i11lli_o(7) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOOl_dataout <= wire_nl1i11lli_o(8) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nillOOOO_dataout <= wire_nl1i11liO_o(1) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO000i_dataout <= nl11lO1il WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1lii; + wire_nilO000l_dataout <= nl11lO1iO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1lil; + wire_nilO000O_dataout <= nl11lO1li WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1liO; + wire_nilO001i_dataout <= nl11lO10l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1l0i; + wire_nilO001l_dataout <= nl11lO10O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1l0l; + wire_nilO001O_dataout <= nl11lO1ii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1l0O; + wire_nilO00i_dataout <= niOi0ii WHEN niOO0liOO = '1' ELSE nii0ilO; + wire_nilO00ii_dataout <= nl11lO1ll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1lli; + wire_nilO00il_dataout <= nl11lO1lO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1lll; + wire_nilO00iO_dataout <= nl11lO1Oi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1llO; + wire_nilO00l_dataout <= niOi0il WHEN niOO0liOO = '1' ELSE nii0iOi; + wire_nilO00li_dataout <= nl11lO1Ol WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1lOi; + wire_nilO00ll_dataout <= nl11lO1OO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1lOl; + wire_nilO00lO_dataout <= nl11lO01i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1lOO; + wire_nilO00O_dataout <= niOi0iO WHEN niOO0liOO = '1' ELSE nii0iOl; + wire_nilO00Oi_dataout <= nl11lO01l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1O1i; + wire_nilO00Ol_dataout <= nl11lO01O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1O1l; + wire_nilO00OO_dataout <= nl11lO00i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1O1O; + wire_nilO010i_dataout <= wire_nilO01ii_dataout AND NOT(niOO10O1i); + wire_nilO010i_w_lg_w_lg_dataout25163w53440w(0) <= wire_nilO010i_w_lg_dataout25163w(0) AND nl01l0lOO; + wire_nilO010i_w_lg_dataout25163w(0) <= NOT wire_nilO010i_dataout; + wire_nilO010l_dataout <= wire_nilO01il_dataout AND NOT(niOO10O1i); + wire_nilO010l_w_lg_dataout8971w(0) <= NOT wire_nilO010l_dataout; + wire_nilO010O_dataout <= wire_w_lg_niOO10O1l8900w(0) AND NOT(niOO10O1i); + wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w43350w(0) <= wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) AND wire_nilO010i_dataout; + wire_nilO010O_w_lg_w_lg_dataout8973w8974w(0) <= wire_nilO010O_w_lg_dataout8973w(0) AND wire_nilO010i_dataout; + wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0) <= wire_nilO010O_w_lg_dataout8976w(0) AND wire_nilO010i_dataout; + wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) <= wire_nilO010O_w_lg_dataout8970w(0) AND wire_nilO010l_w_lg_dataout8971w(0); + wire_nilO010O_w_lg_dataout8973w(0) <= wire_nilO010O_dataout AND wire_nilO010l_w_lg_dataout8971w(0); + wire_nilO010O_w_lg_dataout8976w(0) <= wire_nilO010O_dataout AND wire_nilO010l_dataout; + wire_nilO010O_w_lg_dataout8970w(0) <= NOT wire_nilO010O_dataout; + wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w54849w(0) <= wire_nilO010O_w_lg_w_lg_dataout8970w8972w(0) OR niOi01iii; + wire_nilO011i_dataout <= nl11iOOl WHEN niOO10lOO = '1' ELSE nl111ili; + wire_nilO011l_dataout <= nl11il0O WHEN niOO10lOO = '1' ELSE nl11101l; + wire_nilO011l_w_lg_dataout43407w(0) <= NOT wire_nilO011l_dataout; + wire_nilO011O_dataout <= k_gbl_hip(9) AND wire_w_lg_niOO10lOO8902w(0); + wire_nilO01i_dataout <= niOi00i WHEN niOO0liOO = '1' ELSE nii0iiO; + wire_nilO01ii_dataout <= wire_nilO01iO_dataout OR niOO10O1l; + wire_nilO01il_dataout <= niOO10O1O AND NOT(niOO10O1l); + wire_nilO01iO_dataout <= (NOT k_gbl_hip(12)) AND NOT(niOO10O1O); + wire_nilO01l_dataout <= niOi00l WHEN niOO0liOO = '1' ELSE nii0ili; + wire_nilO01ll_dataout <= nl11l0i1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1iOl; + wire_nilO01lO_dataout <= nl11lO11i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1iOO; + wire_nilO01O_dataout <= niOi00O WHEN niOO0liOO = '1' ELSE nii0ill; + wire_nilO01Oi_dataout <= nl11lO11l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1l1i; + wire_nilO01Ol_dataout <= nl11lO11O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1l1l; + wire_nilO01OO_dataout <= nl11lO10i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1l1O; + wire_nilO0i0i_dataout <= nl11lO0il WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1Oii; + wire_nilO0i0l_dataout <= nl11lO0iO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1Oil; + wire_nilO0i0O_dataout <= nl11lO0li WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1OiO; + wire_nilO0i1i_dataout <= nl11lO00l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1O0i; + wire_nilO0i1l_dataout <= nl11lO00O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1O0l; + wire_nilO0i1O_dataout <= nl11lO0ii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1O0O; + wire_nilO0ii_dataout <= niOi0li WHEN niOO0liOO = '1' ELSE nii0iOO; + wire_nilO0iii_dataout <= nl11lO0ll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1Oli; + wire_nilO0iil_dataout <= nl11lO0lO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1Oll; + wire_nilO0iiO_dataout <= nl11lO0Oi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1OlO; + wire_nilO0il_dataout <= niOi0ll WHEN niOO0liOO = '1' ELSE nii0l1i; + wire_nilO0ili_dataout <= nl11lO0Ol WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1OOi; + wire_nilO0ill_dataout <= nl11lO0OO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1OOl; + wire_nilO0ilO_dataout <= nl11lOi1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO1OOO; + wire_nilO0iO_dataout <= niOi0lO WHEN niOO0liOO = '1' ELSE nii0l1l; + wire_nilO0iOi_dataout <= nl11lOi1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO011i; + wire_nilO0iOl_dataout <= nl11lOi1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO011l; + wire_nilO0iOO_dataout <= nl11lOi0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO011O; + wire_nilO0l0i_dataout <= nl11lOiil WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01ii; + wire_nilO0l0l_dataout <= nl11lOiiO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01il; + wire_nilO0l0O_dataout <= nl11lOili WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01iO; + wire_nilO0l1i_dataout <= nl11lOi0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO010i; + wire_nilO0l1l_dataout <= nl11lOi0O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO010l; + wire_nilO0l1O_dataout <= nl11lOiii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO010O; + wire_nilO0li_dataout <= niOi0Oi WHEN niOO0liOO = '1' ELSE nii0l1O; + wire_nilO0lii_dataout <= nl11lOill WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01li; + wire_nilO0lil_dataout <= nl11lOilO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01ll; + wire_nilO0liO_dataout <= nl11lOiOi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01lO; + wire_nilO0ll_dataout <= niOi0Ol WHEN niOO0liOO = '1' ELSE nii0l0i; + wire_nilO0lli_dataout <= nl11lOiOl WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01Oi; + wire_nilO0lll_dataout <= nl11lOiOO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01Ol; + wire_nilO0llO_dataout <= nl11lOl1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO01OO; + wire_nilO0lO_dataout <= niOi0OO WHEN niOO0liOO = '1' ELSE nii0l0l; + wire_nilO0lOi_dataout <= nl11lOl1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO001i; + wire_nilO0lOl_dataout <= nl11lOl1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO001l; + wire_nilO0lOO_dataout <= nl11lOl0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO001O; + wire_nilO0O0i_dataout <= nl11lOlil WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00ii; + wire_nilO0O0l_dataout <= nl11lOliO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00il; + wire_nilO0O0O_dataout <= nl11lOlli WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00iO; + wire_nilO0O1i_dataout <= nl11lOl0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO000i; + wire_nilO0O1l_dataout <= nl11lOl0O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO000l; + wire_nilO0O1O_dataout <= nl11lOlii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO000O; + wire_nilO0Oi_dataout <= niOii1i WHEN niOO0liOO = '1' ELSE nii0l0O; + wire_nilO0Oii_dataout <= nl11lOlll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00li; + wire_nilO0Oil_dataout <= nl11lOllO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00ll; + wire_nilO0OiO_dataout <= nl11lOlOi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00lO; + wire_nilO0Ol_dataout <= niOii1l WHEN niOO0liOO = '1' ELSE nii0lii; + wire_nilO0Oli_dataout <= nl11lOlOl WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00Oi; + wire_nilO0Oll_dataout <= nl11lOlOO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00Ol; + wire_nilO0OlO_dataout <= nl11lOO1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO00OO; + wire_nilO0OO_dataout <= niOii1O WHEN niOO0liOO = '1' ELSE nii0lil; + wire_nilO0OOi_dataout <= nl11lOO1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO0i1i; + wire_nilO0OOl_dataout <= nl11lOO1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO0i1l; + wire_nilO0OOO_dataout <= wire_nl11Oilii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO0i1O; + wire_nilO0OOO_w_lg_w_lg_dataout34724w34725w(0) <= wire_nilO0OOO_w_lg_dataout34724w(0) AND nlll1iliO; + wire_nilO0OOO_w_lg_dataout34724w(0) <= NOT wire_nilO0OOO_dataout; + wire_nilO100i_dataout <= wire_nl1i11lil_o(12) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO100l_dataout <= wire_nl11i0O1i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO100O_dataout <= wire_nl11i0O1l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO101i_dataout <= wire_nl1i11lil_o(9) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO101l_dataout <= wire_nl1i11lil_o(10) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO101O_dataout <= wire_nl1i11lil_o(11) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10i_dataout <= nii00lO WHEN niOO0liOO = '1' ELSE wire_niO1OOi_dataout; + wire_nilO10ii_dataout <= wire_nl11i0O1O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10il_dataout <= wire_nl11i0O0i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10iO_dataout <= wire_nl11i0O0l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10l_dataout <= nii00Oi WHEN niOO0liOO = '1' ELSE wire_niO1OOl_dataout; + wire_nilO10li_dataout <= wire_nl11i0O0O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10ll_dataout <= wire_nl11i0Oii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10lO_dataout <= wire_nl11i0Oil_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10O_dataout <= nii00Ol WHEN niOO0liOO = '1' ELSE wire_niO1OOO_dataout; + wire_nilO10Oi_dataout <= wire_nl11i0OiO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10Ol_dataout <= wire_nl11i0Oli_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO10OO_dataout <= wire_nl11i0Oll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO110i_dataout <= wire_nl1i11liO_o(5) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO110l_dataout <= wire_nl1i11liO_o(6) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO110O_dataout <= wire_nl1i11liO_o(7) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO111i_dataout <= wire_nl1i11liO_o(2) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO111l_dataout <= wire_nl1i11liO_o(3) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO111O_dataout <= wire_nl1i11liO_o(4) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11i_dataout <= nii00iO WHEN niOO0liOO = '1' ELSE wire_niO1Oli_dataout; + wire_nilO11ii_dataout <= wire_nl1i11liO_o(8) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11il_dataout <= wire_nl1i11lil_o(1) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11iO_dataout <= wire_nl1i11lil_o(2) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11l_dataout <= nii00li WHEN niOO0liOO = '1' ELSE wire_niO1Oll_dataout; + wire_nilO11li_dataout <= wire_nl1i11lil_o(3) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11ll_dataout <= wire_nl1i11lil_o(4) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11lO_dataout <= wire_nl1i11lil_o(5) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11O_dataout <= nii00ll WHEN niOO0liOO = '1' ELSE wire_niO1OlO_dataout; + wire_nilO11Oi_dataout <= wire_nl1i11lil_o(6) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11Ol_dataout <= wire_nl1i11lil_o(7) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO11OO_dataout <= wire_nl1i11lil_o(8) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1i0i_dataout <= wire_nl11i0OOO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1i0l_dataout <= wire_nl11ii11i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1i0O_dataout <= wire_nl11ii11l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1i1i_dataout <= wire_nl11i0OlO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1i1l_dataout <= wire_nl11i0OOi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1i1O_dataout <= wire_nl11i0OOl_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1ii_dataout <= nii00OO WHEN niOO0liOO = '1' ELSE wire_niO011i_dataout; + wire_nilO1iii_dataout <= wire_nl11ii11O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1iil_dataout <= wire_nl11ii10i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1iiO_dataout <= wire_nl11ii10l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1il_dataout <= nii0i1i WHEN niOO0liOO = '1' ELSE wire_niO011l_dataout; + wire_nilO1ili_dataout <= wire_nl11ii10O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1ill_dataout <= wire_nl11ii1ii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1ilO_dataout <= wire_nl11ii1il_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1iO_dataout <= nii0i1l WHEN niOO0liOO = '1' ELSE wire_niO011O_dataout; + wire_nilO1iOi_dataout <= wire_nl11ii1iO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1iOl_dataout <= wire_nl11ii1li_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1iOO_dataout <= wire_nl11ii1ll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1l0i_dataout <= wire_nl11ii1OO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1l0l_dataout <= wire_nl11ii01i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1l0O_dataout <= wire_nl11ii01l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1l1i_dataout <= wire_nl11ii1lO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1l1l_dataout <= wire_nl11ii1Oi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1l1O_dataout <= wire_nl11ii1Ol_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1li_dataout <= nii0i1O WHEN niOO0liOO = '1' ELSE wire_niO010i_dataout; + wire_nilO1lii_dataout <= wire_nl11ii01O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1lil_dataout <= wire_nl11ii00i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1liO_dataout <= wire_nl11ii00l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1ll_dataout <= nii0i0i WHEN niOO0liOO = '1' ELSE wire_niO010l_dataout; + wire_nilO1lli_dataout <= wire_nl11ii00O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1lll_dataout <= wire_nl11ii0il_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1llO_dataout <= wire_nl11ii0iO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1lO_dataout <= nii0i0l WHEN niOO0liOO = '1' ELSE wire_niO010O_dataout; + wire_nilO1lOi_dataout <= wire_nl11ii0li_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1lOl_dataout <= wire_nl11ii0ll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1lOO_dataout <= wire_nl11ii0lO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1O0i_dataout <= wire_nl11iii1i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1O0l_dataout <= wire_nl11iii1l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1O0O_dataout <= wire_nl11iii1O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1O1i_dataout <= wire_nl11ii0Oi_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1O1l_dataout <= wire_nl11ii0Ol_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1O1O_dataout <= wire_nl11ii0OO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1Oi_dataout <= nii0i0O WHEN niOO0liOO = '1' ELSE wire_niO01ii_dataout; + wire_nilO1Oii_dataout <= wire_nl11iii0i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1Oil_dataout <= wire_nl11iii0l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1OiO_dataout <= wire_nl11iii0O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1Ol_dataout <= nii0iii WHEN niOO0liOO = '1' ELSE wire_niO01il_dataout; + wire_nilO1Oli_dataout <= wire_nl11iiiii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1Oll_dataout <= wire_nl11iiiil_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1OlO_dataout <= wire_nl11iiiiO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1OO_dataout <= niOi01O WHEN niOO0liOO = '1' ELSE nii0iil; + wire_nilO1OOi_dataout <= wire_nl11iiili_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1OOl_dataout <= wire_nl11iiill_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilO1OOO_dataout <= wire_nl11iiilO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi00i_dataout <= niOO01i1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi00i_w_lg_dataout54077w(0) <= wire_nilOi00i_dataout AND wire_nl011OlOO_w_lg_dataout8890w(0); + wire_nilOi00l_dataout <= nll0O0iOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi00O_dataout <= niOO01l1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi00O_w_lg_w_lg_dataout45023w52928w(0) <= wire_nilOi00O_w_lg_dataout45023w(0) AND wire_nlill0Oll_w_lg_nl01ii1Oi44963w(0); + wire_nilOi00O_w_lg_dataout45023w(0) <= NOT wire_nilOi00O_dataout; + wire_nilOi01i_dataout <= nlliOl01l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi01l_dataout <= wire_nlOi01Oll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi01O_dataout <= wire_nlOi0000l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0i_dataout <= niOiiii WHEN niOO0liOO = '1' ELSE nii0llO; + wire_nilOi0ii_dataout <= nll0OOOOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0ii_w_lg_w_lg_w_lg_dataout52927w52932w52933w(0) <= wire_nilOi0ii_w_lg_w_lg_dataout52927w52932w(0) AND nl01lll1i; + wire_nilOi0ii_w_lg_w_lg_dataout52927w52932w(0) <= wire_nilOi0ii_w_lg_dataout52927w(0) AND wire_nilOi0il_w_lg_w_lg_w_lg_dataout44964w52929w52931w(0); + wire_nilOi0ii_w_lg_dataout52927w(0) <= NOT wire_nilOi0ii_dataout; + wire_nilOi0il_dataout <= nlli101ll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0il_w_lg_w_lg_w_lg_dataout44964w52929w52931w(0) <= wire_nilOi0il_w_lg_w_lg_dataout44964w52929w(0) AND wire_nlill0Oll_w_lg_nl01ii1Ol52930w(0); + wire_nilOi0il_w_lg_w_lg_dataout44964w52929w(0) <= wire_nilOi0il_w_lg_dataout44964w(0) AND wire_nilOi00O_w_lg_w_lg_dataout45023w52928w(0); + wire_nilOi0il_w_lg_w_lg_dataout44964w44965w(0) <= wire_nilOi0il_w_lg_dataout44964w(0) AND niOililOl; + wire_nilOi0il_w_lg_dataout44964w(0) <= NOT wire_nilOi0il_dataout; + wire_nilOi0iO_dataout <= nlli0ilOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0iO_w_lg_dataout42932w(0) <= NOT wire_nilOi0iO_dataout; + wire_nilOi0l_dataout <= niOiiil WHEN niOO0liOO = '1' ELSE nii0lOi; + wire_nilOi0li_dataout <= nlli0ilOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0li_w_lg_dataout42931w(0) <= NOT wire_nilOi0li_dataout; + wire_nilOi0li_w_lg_dataout54063w(0) <= wire_nilOi0li_dataout OR wire_nilOi0iO_dataout; + wire_nilOi0ll_dataout <= nll0O0iOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0ll_w_lg_dataout54064w(0) <= wire_nilOi0ll_dataout OR wire_nilOi0li_w_lg_dataout54063w(0); + wire_nilOi0lO_dataout <= nll0O0iOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0lO_w_lg_dataout53094w(0) <= NOT wire_nilOi0lO_dataout; + wire_nilOi0O_dataout <= niOiiiO WHEN niOO0liOO = '1' ELSE nii0lOl; + wire_nilOi0Oi_dataout <= nll0O0l1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0Oi_w_lg_dataout53096w(0) <= NOT wire_nilOi0Oi_dataout; + wire_nilOi0Ol_dataout <= nll0O0l1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0Ol_w_lg_dataout45180w(0) <= NOT wire_nilOi0Ol_dataout; + wire_nilOi0OO_dataout <= nll0O0l1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi0OO_w_lg_dataout45178w(0) <= NOT wire_nilOi0OO_dataout; + wire_nilOi10i_dataout <= wire_nlliOl1ii_o(1) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi10l_dataout <= wire_nlliOl1ii_o(2) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi10O_dataout <= wire_nlliOl1ii_o(3) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi11i_dataout <= niOO000ll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi11i_w_lg_dataout59400w(0) <= NOT wire_nilOi11i_dataout; + wire_nilOi11l_dataout <= niOO000Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi11l_w_lg_w_lg_w_lg_dataout43384w43387w43388w(0) <= wire_nilOi11l_w_lg_w_lg_dataout43384w43387w(0) AND niOilOiOO; + wire_nilOi11l_w_lg_w_lg_dataout43384w43387w(0) <= wire_nilOi11l_w_lg_dataout43384w(0) AND wire_nlill0Oll_w_lg_nl11lOlOO43386w(0); + wire_nilOi11l_w_lg_dataout43384w(0) <= wire_nilOi11l_dataout AND nl11lOO1i; + wire_nilOi11O_dataout <= niOO10O0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nllO0i0l; + wire_nilOi1i_dataout <= niOii0i WHEN niOO0liOO = '1' ELSE nii0liO; + wire_nilOi1ii_dataout <= wire_nlliOl1ii_o(4) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1il_dataout <= wire_nlliOl1ii_o(5) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1iO_dataout <= nlliOl1li AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1l_dataout <= niOii0l WHEN niOO0liOO = '1' ELSE nii0lli; + wire_nilOi1li_dataout <= nlliOl1ll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1ll_dataout <= nlliOl1lO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1lO_dataout <= nlliOl1Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1O_dataout <= niOii0O WHEN niOO0liOO = '1' ELSE nii0lll; + wire_nilOi1Oi_dataout <= nlliOl1Ol AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1Ol_dataout <= nlliOl1OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOi1OO_dataout <= nlliOl01i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOii0i_dataout <= nll0O0lii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOii0i_w_lg_w_lg_w53765w53766w53767w(0) <= wire_nilOii0i_w_lg_w53765w53766w(0) AND wire_nilOi0Ol_dataout; + wire_nilOii0i_w_lg_w_lg_w53887w53888w53895w(0) <= wire_nilOii0i_w_lg_w53887w53888w(0) AND wire_nilOi0Ol_dataout; + wire_nilOii0i_w_lg_w53765w53766w(0) <= wire_nilOii0i_w53765w(0) AND wire_nilOi0OO_w_lg_dataout45178w(0); + wire_nilOii0i_w_lg_w53765w53770w(0) <= wire_nilOii0i_w53765w(0) AND wire_nilOi0OO_dataout; + wire_nilOii0i_w_lg_w53887w53888w(0) <= wire_nilOii0i_w53887w(0) AND wire_nilOi0OO_w_lg_dataout45178w(0); + wire_nilOii0i_w_lg_w53887w53901w(0) <= wire_nilOii0i_w53887w(0) AND wire_nilOi0OO_dataout; + wire_nilOii0i_w53765w(0) <= wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w53764w(0) AND wire_nilOii1i_dataout; + wire_nilOii0i_w45177w(0) <= wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w45176w(0) AND wire_nilOii1i_dataout; + wire_nilOii0i_w53887w(0) <= wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w53875w53876w(0) AND wire_nilOii1i_w_lg_dataout53100w(0); + wire_nilOii0i_w53877w(0) <= wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w53875w53876w(0) AND wire_nilOii1i_dataout; + wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w53764w(0) <= wire_nilOii0i_w_lg_w_lg_dataout45173w45175w(0) AND wire_nilOii1l_w_lg_dataout53102w(0); + wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w45175w45176w(0) <= wire_nilOii0i_w_lg_w_lg_dataout45173w45175w(0) AND wire_nilOii1l_dataout; + wire_nilOii0i_w_lg_w_lg_w_lg_dataout45173w53875w53876w(0) <= wire_nilOii0i_w_lg_w_lg_dataout45173w53875w(0) AND wire_nilOii1l_w_lg_dataout53102w(0); + wire_nilOii0i_w_lg_w_lg_dataout45173w45175w(0) <= wire_nilOii0i_w_lg_dataout45173w(0) AND wire_nilOii1O_w_lg_dataout45174w(0); + wire_nilOii0i_w_lg_w_lg_dataout45173w53875w(0) <= wire_nilOii0i_w_lg_dataout45173w(0) AND wire_nilOii1O_dataout; + wire_nilOii0i_w_lg_dataout45173w(0) <= NOT wire_nilOii0i_dataout; + wire_nilOii0l_dataout <= nll0O0lil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOii0l_w_lg_dataout53106w(0) <= NOT wire_nilOii0l_dataout; + wire_nilOii0O_dataout <= nll0O0liO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOii0O_w_lg_dataout53108w(0) <= NOT wire_nilOii0O_dataout; + wire_nilOii1i_dataout <= nll0O0l0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOii1i_w_lg_dataout53100w(0) <= NOT wire_nilOii1i_dataout; + wire_nilOii1l_dataout <= nll0O0l0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOii1l_w_lg_dataout53102w(0) <= NOT wire_nilOii1l_dataout; + wire_nilOii1O_dataout <= nll0O0l0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOii1O_w_lg_dataout45174w(0) <= NOT wire_nilOii1O_dataout; + wire_nilOiii_dataout <= niOiili WHEN niOO0liOO = '1' ELSE nii0lOO; + wire_nilOiiii_dataout <= nll0O0lli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiiii_w_lg_dataout53110w(0) <= NOT wire_nilOiiii_dataout; + wire_nilOiiil_dataout <= nll0O0lll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiiil_w_lg_dataout53112w(0) <= NOT wire_nilOiiil_dataout; + wire_nilOiiiO_dataout <= nll0O0llO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiiiO_w_lg_dataout53114w(0) <= NOT wire_nilOiiiO_dataout; + wire_nilOiil_dataout <= niOiill WHEN niOO0liOO = '1' ELSE nii0O1i; + wire_nilOiili_dataout <= nll0O0lOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiili_w_lg_dataout53908w(0) <= NOT wire_nilOiili_dataout; + wire_nilOiill_dataout <= nll0O0lOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiill_w_lg_dataout53906w(0) <= NOT wire_nilOiill_dataout; + wire_nilOiilO_dataout <= nll0O0lOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiilO_w_lg_dataout53905w(0) <= NOT wire_nilOiilO_dataout; + wire_nilOiiO_dataout <= niOiilO WHEN niOO0liOO = '1' ELSE nii0O1l; + wire_nilOiiOi_dataout <= nll0O0O1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiiOl_dataout <= nll0O0O1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiiOO_dataout <= nll0O0O1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOil0i_dataout <= nll0O0Oii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOil0l_dataout <= nll0O0Oil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOil0O_dataout <= nll0O0OiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOil1i_dataout <= nll0O0O0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOil1l_dataout <= nll0O0O0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOil1O_dataout <= nll0O0O0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOili_dataout <= niOiiOi WHEN niOO0liOO = '1' ELSE nii0O1O; + wire_nilOilii_dataout <= nll0O0Oli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOilil_dataout <= nll0O0Oll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiliO_dataout <= nll0O0OlO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOill_dataout <= niOiiOl WHEN niOO0liOO = '1' ELSE nii0O0i; + wire_nilOilli_dataout <= nll0O0OOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOilll_dataout <= nll0O0OOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOillO_dataout <= nll0O0OOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOilO_dataout <= niOiiOO WHEN niOO0liOO = '1' ELSE nii0O0l; + wire_nilOilOi_dataout <= nll0Oi11i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOilOl_dataout <= nll0Oi11l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOilOl_w_lg_dataout53154w(0) <= NOT wire_nilOilOl_dataout; + wire_nilOilOO_dataout <= nll0Oi11O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOilOO_w_lg_dataout53156w(0) <= NOT wire_nilOilOO_dataout; + wire_nilOiO0i_dataout <= nll0Oi1ii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiO0i_w_lg_dataout53730w(0) <= NOT wire_nilOiO0i_dataout; + wire_nilOiO0l_dataout <= nll0Oi1il AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiO0l_w_lg_dataout53728w(0) <= NOT wire_nilOiO0l_dataout; + wire_nilOiO0O_dataout <= nll0Oi1iO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiO0O_w_lg_dataout53726w(0) <= NOT wire_nilOiO0O_dataout; + wire_nilOiO1i_dataout <= nll0Oi10i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiO1i_w_lg_dataout53736w(0) <= NOT wire_nilOiO1i_dataout; + wire_nilOiO1l_dataout <= nll0Oi10l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiO1l_w_lg_dataout53734w(0) <= NOT wire_nilOiO1l_dataout; + wire_nilOiO1O_dataout <= nll0Oi10O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiO1O_w_lg_dataout53732w(0) <= NOT wire_nilOiO1O_dataout; + wire_nilOiOi_dataout <= niOil1i WHEN niOO0liOO = '1' ELSE nii0O0O; + wire_nilOiOii_dataout <= nll0Oi1li AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOii_w_lg_dataout53724w(0) <= NOT wire_nilOiOii_dataout; + wire_nilOiOil_dataout <= nll0Oi1ll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOil_w_lg_dataout53723w(0) <= NOT wire_nilOiOil_dataout; + wire_nilOiOiO_dataout <= nll0Oi1lO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOiO_w_lg_dataout49194w(0) <= NOT wire_nilOiOiO_dataout; + wire_nilOiOl_dataout <= niOil1l WHEN niOO0liOO = '1' ELSE nii0Oii; + wire_nilOiOli_dataout <= nll0Oi1Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOli_w_lg_dataout49192w(0) <= NOT wire_nilOiOli_dataout; + wire_nilOiOll_dataout <= nll0Oi1Ol AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOll_w_lg_dataout49190w(0) <= NOT wire_nilOiOll_dataout; + wire_nilOiOlO_dataout <= nll0Oi1OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOlO_w_lg_w_lg_dataout49188w53619w(0) <= wire_nilOiOlO_w_lg_dataout49188w(0) AND wire_nilOiOll_w_lg_dataout49190w(0); + wire_nilOiOlO_w_lg_w_lg_w_lg_dataout49188w53619w53620w(0) <= NOT wire_nilOiOlO_w_lg_w_lg_dataout49188w53619w(0); + wire_nilOiOlO_w_lg_dataout49188w(0) <= NOT wire_nilOiOlO_dataout; + wire_nilOiOO_dataout <= niOil1O WHEN niOO0liOO = '1' ELSE nii0Oil; + wire_nilOiOOi_dataout <= nll0Oi01i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOOi_w_lg_dataout49186w(0) <= NOT wire_nilOiOOi_dataout; + wire_nilOiOOl_dataout <= nll0Oi01l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOOl_w_lg_dataout49185w(0) <= NOT wire_nilOiOOl_dataout; + wire_nilOiOOO_dataout <= nll0Oi01O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOiOOO_w_lg_dataout49183w(0) <= NOT wire_nilOiOOO_dataout; + wire_nilOl00i_dataout <= (wire_nl011OlOO_w_lg_dataout8890w(0) AND (wire_nilOi00l_dataout AND wire_nilOi00i_dataout)) WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ((niOO01i1O AND nll0O0iOi) AND wire_nllil0lO_w_lg_dataout8888w(0)); + wire_nilOl00i_w_lg_dataout42840w(0) <= wire_nilOl00i_dataout AND wire_nilOl01i_w42839w(0); + wire_nilOl00l_dataout <= nllii0OlO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl00l_w_lg_dataout61592w(0) <= NOT wire_nilOl00l_dataout; + wire_nilOl00O_dataout <= nlliii0Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl00O_w_lg_dataout61590w(0) <= NOT wire_nilOl00O_dataout; + wire_nilOl01i_dataout <= nl0100O1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nll0Ol1l; + wire_nilOl01i_w42839w(0) <= wire_nilOl01i_w_lg_w_lg_w_lg_dataout42832w42833w42836w(0) AND wire_nilOl01O_w_lg_w_lg_dataout42837w42838w(0); + wire_nilOl01i_w_lg_w_lg_w_lg_dataout42832w42833w42836w(0) <= wire_nilOl01i_w_lg_w_lg_dataout42832w42833w(0) AND wire_nilOl01l_w_lg_w_lg_dataout42834w42835w(0); + wire_nilOl01i_w_lg_w_lg_dataout42832w42833w(0) <= NOT wire_nilOl01i_w_lg_dataout42832w(0); + wire_nilOl01i_w_lg_dataout42832w(0) <= wire_nilOl01i_dataout XOR nlillOl1i; + wire_nilOl01l_dataout <= nl0100O0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nll0Ol1O; + wire_nilOl01l_w_lg_w_lg_dataout42834w42835w(0) <= NOT wire_nilOl01l_w_lg_dataout42834w(0); + wire_nilOl01l_w_lg_dataout42834w(0) <= wire_nilOl01l_dataout XOR nlillOl1l; + wire_nilOl01O_dataout <= nl0100O0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nll0Ol0i; + wire_nilOl01O_w_lg_w_lg_dataout42837w42838w(0) <= NOT wire_nilOl01O_w_lg_dataout42837w(0); + wire_nilOl01O_w_lg_dataout42837w(0) <= wire_nilOl01O_dataout XOR nlillOl1O; + wire_nilOl0i_dataout <= niii0OO WHEN niOO0liOi = '1' ELSE wire_niO01ll_dataout; + wire_nilOl0ii_dataout <= nlliii0Ol AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0ii_w_lg_dataout61588w(0) <= NOT wire_nilOl0ii_dataout; + wire_nilOl0il_dataout <= nlliii0OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0il_w_lg_dataout61586w(0) <= NOT wire_nilOl0il_dataout; + wire_nilOl0iO_dataout <= nlliiii1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0iO_w_lg_dataout61584w(0) <= NOT wire_nilOl0iO_dataout; + wire_nilOl0l_dataout <= niiii1i WHEN niOO0liOi = '1' ELSE wire_niO01lO_dataout; + wire_nilOl0li_dataout <= nlliiii1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0li_w_lg_dataout61582w(0) <= NOT wire_nilOl0li_dataout; + wire_nilOl0ll_dataout <= nlliiii1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0ll_w_lg_dataout61580w(0) <= NOT wire_nilOl0ll_dataout; + wire_nilOl0lO_dataout <= nlliiii0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0lO_w_lg_dataout61578w(0) <= NOT wire_nilOl0lO_dataout; + wire_nilOl0O_dataout <= niiii1l WHEN niOO0liOi = '1' ELSE wire_niO01Oi_dataout; + wire_nilOl0Oi_dataout <= nlliiii0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0Oi_w_lg_dataout61576w(0) <= NOT wire_nilOl0Oi_dataout; + wire_nilOl0Ol_dataout <= nlliiii0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0Ol_w_lg_dataout61574w(0) <= NOT wire_nilOl0Ol_dataout; + wire_nilOl0OO_dataout <= nlliiiiii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl0OO_w_lg_dataout61572w(0) <= NOT wire_nilOl0OO_dataout; + wire_nilOl10i_dataout <= nll0Oi0ii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl10i_w_lg_dataout49172w(0) <= NOT wire_nilOl10i_dataout; + wire_nilOl10l_dataout <= nll0Oi0il AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl10l_w_lg_dataout49170w(0) <= NOT wire_nilOl10l_dataout; + wire_nilOl10O_dataout <= nll0Oi0iO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl10O_w_lg_w_lg_dataout49168w54114w(0) <= wire_nilOl10O_w_lg_dataout49168w(0) AND wire_nilOl10l_dataout; + wire_nilOl10O_w_lg_dataout54117w(0) <= wire_nilOl10O_dataout AND wire_nilOl10l_w_lg_dataout49170w(0); + wire_nilOl10O_w_lg_dataout49168w(0) <= NOT wire_nilOl10O_dataout; + wire_nilOl11i_dataout <= nll0Oi00i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl11i_w_lg_dataout49181w(0) <= NOT wire_nilOl11i_dataout; + wire_nilOl11l_dataout <= nll0Oi00l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl11l_w_lg_dataout49175w(0) <= NOT wire_nilOl11l_dataout; + wire_nilOl11O_dataout <= nll0Oi00O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl11O_w_lg_dataout49178w(0) <= NOT wire_nilOl11O_dataout; + wire_nilOl1i_dataout <= niOil0i WHEN niOO0liOO = '1' ELSE nii0OiO; + wire_nilOl1ii_dataout <= nll0Oi0li AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1ii_w_lg_dataout49166w(0) <= NOT wire_nilOl1ii_dataout; + wire_nilOl1il_dataout <= nll0Oi0ll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1il_w_lg_dataout43280w(0) <= NOT wire_nilOl1il_dataout; + wire_nilOl1iO_dataout <= nll0Oi0lO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1iO_w_lg_dataout43278w(0) <= NOT wire_nilOl1iO_dataout; + wire_nilOl1l_dataout <= niii0Oi WHEN niOO0liOi = '1' ELSE wire_niO01iO_dataout; + wire_nilOl1li_dataout <= nll0Oi0Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1li_w_lg_dataout43291w(0) <= NOT wire_nilOl1li_dataout; + wire_nilOl1ll_dataout <= nll0Oi0Ol AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1ll_w_lg_dataout43266w(0) <= NOT wire_nilOl1ll_dataout; + wire_nilOl1lO_dataout <= nll0Oi0OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1lO_w53755w(0) <= wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53201w(0) AND wire_nilOl1iO_dataout; + wire_nilOl1lO_w44969w(0) <= wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w44967w44968w(0) AND wire_nilOl1iO_dataout; + wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53201w(0) <= wire_nilOl1lO_w_lg_w_lg_dataout43274w53200w(0) AND wire_nilOl1li_w_lg_dataout43291w(0); + wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w53200w53757w(0) <= wire_nilOl1lO_w_lg_w_lg_dataout43274w53200w(0) AND wire_nilOl1li_dataout; + wire_nilOl1lO_w_lg_w_lg_w_lg_dataout43274w44967w44968w(0) <= wire_nilOl1lO_w_lg_w_lg_dataout43274w44967w(0) AND wire_nilOl1li_w_lg_dataout43291w(0); + wire_nilOl1lO_w_lg_w_lg_dataout43274w53200w(0) <= wire_nilOl1lO_w_lg_dataout43274w(0) AND wire_nilOl1ll_w_lg_dataout43266w(0); + wire_nilOl1lO_w_lg_w_lg_dataout43274w44967w(0) <= wire_nilOl1lO_w_lg_dataout43274w(0) AND wire_nilOl1ll_dataout; + wire_nilOl1lO_w_lg_dataout53761w(0) <= wire_nilOl1lO_dataout AND wire_nilOl1ll_w_lg_dataout43266w(0); + wire_nilOl1lO_w_lg_dataout43274w(0) <= NOT wire_nilOl1lO_dataout; + wire_nilOl1O_dataout <= niii0Ol WHEN niOO0liOi = '1' ELSE wire_niO01li_dataout; + wire_nilOl1Oi_dataout <= nll0Oii1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1Oi_w_lg_w_lg_w53632w53637w53638w(0) <= wire_nilOl1Oi_w_lg_w53632w53637w(0) AND niOi00O0l; + wire_nilOl1Oi_w_lg_w_lg_dataout53615w53616w(0) <= wire_nilOl1Oi_w_lg_dataout53615w(0) AND niOi00O0i; + wire_nilOl1Oi_w_lg_dataout53937w(0) <= wire_nilOl1Oi_dataout AND wire_nilOl1lO_w_lg_dataout53761w(0); + wire_nilOl1Oi_w_lg_dataout43272w(0) <= NOT wire_nilOl1Oi_dataout; + wire_nilOl1Oi_w_lg_w_lg_dataout43272w53625w(0) <= wire_nilOl1Oi_w_lg_dataout43272w(0) OR wire_w_lg_niOi0lOOi53624w(0); + wire_nilOl1Oi_w_lg_w_lg_w_lg_dataout43272w53625w53630w(0) <= wire_nilOl1Oi_w_lg_w_lg_dataout43272w53625w(0) OR wire_w_lg_w_lg_w_lg_niOi0010l53612w53627w53629w(0); + wire_nilOl1Oi_w53632w(0) <= wire_nilOl1Oi_w_lg_w_lg_w_lg_dataout43272w53625w53630w(0) OR wire_nilOl1Ol_w_lg_w_lg_dataout43262w53631w(0); + wire_nilOl1Oi_w_lg_w53632w53637w(0) <= wire_nilOl1Oi_w53632w(0) OR wire_nilOl1Ol_w_lg_w_lg_w_lg_dataout53633w53635w53636w(0); + wire_nilOl1Oi_w_lg_dataout53615w(0) <= wire_nilOl1Oi_dataout OR wire_nilOl1Ol_w_lg_dataout53614w(0); + wire_nilOl1Oi_w_lg_dataout53622w(0) <= wire_nilOl1Oi_dataout OR wire_w_lg_w_lg_niOi0010l53612w53621w(0); + wire_nilOl1Ol_dataout <= nll0Oii1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1Ol_w_lg_w_lg_w_lg_dataout53633w53635w53636w(0) <= wire_nilOl1Ol_w_lg_w_lg_dataout53633w53635w(0) AND wire_w_lg_niOi00lil53626w(0); + wire_nilOl1Ol_w_lg_w_lg_w_lg_dataout43262w45182w45183w(0) <= wire_nilOl1Ol_w_lg_w_lg_dataout43262w45182w(0) AND wire_nilOl1lO_dataout; + wire_nilOl1Ol_w_lg_w_lg_dataout53633w53635w(0) <= wire_nilOl1Ol_w_lg_dataout53633w(0) AND wire_w_lg_niOi00liO53634w(0); + wire_nilOl1Ol_w_lg_w_lg_dataout43262w45182w(0) <= wire_nilOl1Ol_w_lg_dataout43262w(0) AND wire_nilOl1Oi_dataout; + wire_nilOl1Ol_w_lg_w_lg_dataout43262w53611w(0) <= wire_nilOl1Ol_w_lg_dataout43262w(0) AND niOi0010O; + wire_nilOl1Ol_w_lg_w_lg_dataout43262w53631w(0) <= wire_nilOl1Ol_w_lg_dataout43262w(0) AND niOi00liO; + wire_nilOl1Ol_w_lg_dataout53614w(0) <= wire_nilOl1Ol_dataout AND wire_w_lg_niOi0i11l53116w(0); + wire_nilOl1Ol_w_lg_dataout53633w(0) <= wire_nilOl1Ol_dataout AND niOi00lii; + wire_nilOl1Ol_w_lg_dataout43262w(0) <= NOT wire_nilOl1Ol_dataout; + wire_nilOl1OO_dataout <= nll0Oii1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOl1OO_w_lg_w49173w49174w(0) <= wire_nilOl1OO_w49173w(0) AND wire_nilOl11O_dataout; + wire_nilOl1OO_w49173w(0) <= wire_nilOl1OO_w_lg_w_lg_w_lg_w43303w49167w49169w49171w(0) AND wire_nilOl10i_w_lg_dataout49172w(0); + wire_nilOl1OO_w_lg_w_lg_w_lg_w43303w49167w49169w49171w(0) <= wire_nilOl1OO_w_lg_w_lg_w43303w49167w49169w(0) AND wire_nilOl10l_w_lg_dataout49170w(0); + wire_nilOl1OO_w_lg_w_lg_w43303w49167w49169w(0) <= wire_nilOl1OO_w_lg_w43303w49167w(0) AND wire_nilOl10O_w_lg_dataout49168w(0); + wire_nilOl1OO_w_lg_w43303w49167w(0) <= wire_nilOl1OO_w43303w(0) AND wire_nilOl1ii_w_lg_dataout49166w(0); + wire_nilOl1OO_w43303w(0) <= wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43276w43301w43302w(0) AND wire_nilOl1il_w_lg_dataout43280w(0); + wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43276w43301w43302w(0) <= wire_nilOl1OO_w_lg_w_lg_w43275w43276w43301w(0) AND wire_nilOl1iO_w_lg_dataout43278w(0); + wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43276w43301w43311w(0) <= wire_nilOl1OO_w_lg_w_lg_w43275w43276w43301w(0) AND wire_nilOl1iO_dataout; + wire_nilOl1OO_w_lg_w_lg_w_lg_w43275w43296w43297w43298w(0) <= wire_nilOl1OO_w_lg_w_lg_w43275w43296w43297w(0) AND wire_nilOl1iO_dataout; + wire_nilOl1OO_w_lg_w_lg_w_lg_w43284w43285w43313w43321w(0) <= wire_nilOl1OO_w_lg_w_lg_w43284w43285w43313w(0) AND wire_nilOl1iO_dataout; + wire_nilOl1OO_w_lg_w_lg_w_lg_w43284w43290w43292w43293w(0) <= wire_nilOl1OO_w_lg_w_lg_w43284w43290w43292w(0) AND wire_nilOl1iO_dataout; + wire_nilOl1OO_w_lg_w_lg_w43275w43276w43301w(0) <= wire_nilOl1OO_w_lg_w43275w43276w(0) AND wire_nilOl1li_w_lg_dataout43291w(0); + wire_nilOl1OO_w_lg_w_lg_w43275w43276w43277w(0) <= wire_nilOl1OO_w_lg_w43275w43276w(0) AND wire_nilOl1li_dataout; + wire_nilOl1OO_w_lg_w_lg_w43275w43296w43297w(0) <= wire_nilOl1OO_w_lg_w43275w43296w(0) AND wire_nilOl1li_w_lg_dataout43291w(0); + wire_nilOl1OO_w_lg_w_lg_w43284w43285w43313w(0) <= wire_nilOl1OO_w_lg_w43284w43285w(0) AND wire_nilOl1li_w_lg_dataout43291w(0); + wire_nilOl1OO_w_lg_w_lg_w43284w43285w43286w(0) <= wire_nilOl1OO_w_lg_w43284w43285w(0) AND wire_nilOl1li_dataout; + wire_nilOl1OO_w_lg_w_lg_w43284w43290w43292w(0) <= wire_nilOl1OO_w_lg_w43284w43290w(0) AND wire_nilOl1li_w_lg_dataout43291w(0); + wire_nilOl1OO_w_lg_w43275w43276w(0) <= wire_nilOl1OO_w43275w(0) AND wire_nilOl1ll_w_lg_dataout43266w(0); + wire_nilOl1OO_w_lg_w43275w43296w(0) <= wire_nilOl1OO_w43275w(0) AND wire_nilOl1ll_dataout; + wire_nilOl1OO_w_lg_w43284w43285w(0) <= wire_nilOl1OO_w43284w(0) AND wire_nilOl1ll_w_lg_dataout43266w(0); + wire_nilOl1OO_w_lg_w43284w43290w(0) <= wire_nilOl1OO_w43284w(0) AND wire_nilOl1ll_dataout; + wire_nilOl1OO_w43275w(0) <= wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43273w(0) AND wire_nilOl1lO_w_lg_dataout43274w(0); + wire_nilOl1OO_w43265w(0) <= wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43264w(0) AND wire_nilOl1lO_dataout; + wire_nilOl1OO_w43284w(0) <= wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43268w43283w(0) AND wire_nilOl1lO_w_lg_dataout43274w(0); + wire_nilOl1OO_w43270w(0) <= wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43268w43269w(0) AND wire_nilOl1lO_dataout; + wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43273w(0) <= wire_nilOl1OO_w_lg_w_lg_dataout43261w43263w(0) AND wire_nilOl1Oi_w_lg_dataout43272w(0); + wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43263w43264w(0) <= wire_nilOl1OO_w_lg_w_lg_dataout43261w43263w(0) AND wire_nilOl1Oi_dataout; + wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43268w43283w(0) <= wire_nilOl1OO_w_lg_w_lg_dataout43261w43268w(0) AND wire_nilOl1Oi_w_lg_dataout43272w(0); + wire_nilOl1OO_w_lg_w_lg_w_lg_dataout43261w43268w43269w(0) <= wire_nilOl1OO_w_lg_w_lg_dataout43261w43268w(0) AND wire_nilOl1Oi_dataout; + wire_nilOl1OO_w_lg_w_lg_dataout43261w43263w(0) <= wire_nilOl1OO_w_lg_dataout43261w(0) AND wire_nilOl1Ol_w_lg_dataout43262w(0); + wire_nilOl1OO_w_lg_w_lg_dataout43261w43268w(0) <= wire_nilOl1OO_w_lg_dataout43261w(0) AND wire_nilOl1Ol_dataout; + wire_nilOl1OO_w_lg_dataout43261w(0) <= NOT wire_nilOl1OO_dataout; + wire_nilOli0i_dataout <= nlliiiill AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOli0i_w_lg_dataout61565w(0) <= NOT wire_nilOli0i_dataout; + wire_nilOli0l_dataout <= nlliiiilO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOli0l_w_lg_dataout61563w(0) <= NOT wire_nilOli0l_dataout; + wire_nilOli0O_dataout <= nlliiiiOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOli0O_w_lg_dataout61561w(0) <= NOT wire_nilOli0O_dataout; + wire_nilOli1i_dataout <= nlliiiiil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOli1i_w_lg_dataout61571w(0) <= NOT wire_nilOli1i_dataout; + wire_nilOli1l_dataout <= nlliiiiiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOli1l_w_lg_dataout61569w(0) <= NOT wire_nilOli1l_dataout; + wire_nilOli1O_dataout <= nlliiiili AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOli1O_w_lg_dataout61567w(0) <= NOT wire_nilOli1O_dataout; + wire_nilOlii_dataout <= niiii1O WHEN niOO0liOi = '1' ELSE wire_niO01Ol_dataout; + wire_nilOliii_dataout <= nlliiiiOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOliii_w_lg_dataout61559w(0) <= NOT wire_nilOliii_dataout; + wire_nilOliil_dataout <= nlliiiiOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOliil_w_lg_dataout61557w(0) <= NOT wire_nilOliil_dataout; + wire_nilOliiO_dataout <= nlliiil1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOliiO_w_lg_dataout61556w(0) <= NOT wire_nilOliiO_dataout; + wire_nilOlil_dataout <= niiii0i WHEN niOO0liOi = '1' ELSE wire_niO01OO_dataout; + wire_nilOlili_dataout <= nlliiil1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOlili_w_lg_dataout42893w(0) <= NOT wire_nilOlili_dataout; + wire_nilOlill_dataout <= nlliiil1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOlill_w_lg_dataout42891w(0) <= NOT wire_nilOlill_dataout; + wire_nilOlilO_dataout <= nlliiil0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOlilO_w_lg_dataout42890w(0) <= NOT wire_nilOlilO_dataout; + wire_nilOliO_dataout <= niiii0l WHEN niOO0liOi = '1' ELSE wire_niO001i_dataout; + wire_nilOliOi_dataout <= nlliiil0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOliOi_w_lg_dataout61595w(0) <= NOT wire_nilOliOi_dataout; + wire_nilOliOl_dataout <= nlliiil0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOliOl_w_lg_dataout61594w(0) <= NOT wire_nilOliOl_dataout; + wire_nilOliOO_dataout <= niOO10O0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOll0i_dataout <= nli1iOilO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1i0OOi; + wire_nilOll0i_w_lg_w_lg_dataout9845w9846w(0) <= wire_nilOll0i_w_lg_dataout9845w(0) AND wire_nilOll1O_dataout; + wire_nilOll0i_w_lg_dataout9842w(0) <= wire_nilOll0i_dataout AND wire_nilOll1O_w_lg_dataout9841w(0); + wire_nilOll0i_w_lg_dataout9845w(0) <= NOT wire_nilOll0i_dataout; + wire_nilOll0l_dataout <= (wire_nlOi1Oiii_dataout OR wire_nlOi1Oi0l_dataout) AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOll0l_w_lg_dataout54086w(0) <= wire_nilOll0l_dataout OR wire_nilOOO0i_w_lg_w_lg_dataout54084w54085w(0); + wire_nilOll0O_dataout <= nl011l1il WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni001OO; + wire_nilOll1i_dataout <= wire_nlOi01Oil_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOll1l_dataout <= nli1iOili WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ii1ii; + wire_nilOll1l_w_lg_dataout9843w(0) <= NOT wire_nilOll1l_dataout; + wire_nilOll1O_dataout <= nli1iOill WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1i0OlO; + wire_nilOll1O_w_lg_dataout9841w(0) <= NOT wire_nilOll1O_dataout; + wire_nilOlli_dataout <= niiii0O WHEN niOO0liOi = '1' ELSE wire_niO001l_dataout; + wire_nilOllii_dataout <= nl011l0iO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0001i; + wire_nilOllil_dataout <= nl011l0li WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0001l; + wire_nilOlliO_dataout <= nl011l0ll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0001O; + wire_nilOlll_dataout <= niiiiii WHEN niOO0liOi = '1' ELSE wire_niO001O_dataout; + wire_nilOllli_dataout <= nl011l0lO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0000i; + wire_nilOllll_dataout <= nl011l0Oi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0000l; + wire_nilOlllO_dataout <= nl011l0Ol WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0000O; + wire_nilOllO_dataout <= niiiiil WHEN niOO0liOi = '1' ELSE wire_niO000i_dataout; + wire_nilOllOi_dataout <= nl011l0OO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000ii; + wire_nilOllOl_dataout <= nl011li1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000il; + wire_nilOllOO_dataout <= nl011li1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000iO; + wire_nilOlO0i_dataout <= nl011li0O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000Oi; + wire_nilOlO0l_dataout <= nl011liii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000Ol; + wire_nilOlO0O_dataout <= nl011liil WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000OO; + wire_nilOlO1i_dataout <= nl011li1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000li; + wire_nilOlO1l_dataout <= nl011li0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000ll; + wire_nilOlO1O_dataout <= nl011li0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni000lO; + wire_nilOlOi_dataout <= niiiiiO WHEN niOO0liOi = '1' ELSE wire_niO000l_dataout; + wire_nilOlOii_dataout <= nl011liiO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00i1i; + wire_nilOlOil_dataout <= nl011lili WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00i1l; + wire_nilOlOiO_dataout <= nl011lill WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00i1O; + wire_nilOlOl_dataout <= niiiili WHEN niOO0liOi = '1' ELSE wire_niO000O_dataout; + wire_nilOlOli_dataout <= nl011lilO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00i0i; + wire_nilOlOll_dataout <= ni00i0l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOlOlO_dataout <= ni00i0O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOlOO_dataout <= niiiill WHEN niOO0liOi = '1' ELSE wire_niO00ii_dataout; + wire_nilOlOOi_dataout <= ni00iii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOlOOl_dataout <= nl011liOi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00iil; + wire_nilOlOOO_dataout <= nl011liOl WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00iiO; + wire_nilOO00i_dataout <= wire_nlOilO1OO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO00l_dataout <= wire_nlOii0OOO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO00O_dataout <= wire_nlOii0Oll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO00O_w_lg_dataout47986w(0) <= NOT wire_nilOO00O_dataout; + wire_nilOO01i_dataout <= nli1iiOOO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ll00i; + wire_nilOO01i_w_lg_dataout9215w(0) <= NOT wire_nilOO01i_dataout; + wire_nilOO01l_dataout <= niOO10O0O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1l0O0O; + wire_nilOO01l_w_lg_dataout295w(0) <= NOT wire_nilOO01l_dataout; + wire_nilOO01O_dataout <= wire_nlOl1l0Ol_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO01O_w_lg_dataout60235w(0) <= wire_nilOO01O_dataout AND wire_w_lg_w_lg_niOi1i1Ol60233w60234w(0); + wire_nilOO0i_dataout <= niiiiOO WHEN niOO0liOi = '1' ELSE wire_niO00ll_dataout; + wire_nilOO0ii_dataout <= wire_nlOiii1il_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO0ii_w_lg_dataout44003w(0) <= wire_nilOO0ii_dataout AND wire_w_lg_w_lg_niOilOO0l44001w44002w(0); + wire_nilOO0ii_w_lg_dataout43998w(0) <= wire_nilOO0ii_dataout AND wire_nlill0Oll_w_lg_nlil00ill43997w(0); + wire_nilOO0ii_w_lg_dataout43403w(0) <= NOT wire_nilOO0ii_dataout; + wire_nilOO0il_dataout <= wire_nlOiii10i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO0il_w_lg_dataout44112w(0) <= NOT wire_nilOO0il_dataout; + wire_nilOO0iO_dataout <= nlil1lO1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0l00i; + wire_nilOO0l_dataout <= niiil1i WHEN niOO0liOi = '1' ELSE wire_niO00lO_dataout; + wire_nilOO0li_dataout <= nlil1lO1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0l00l; + wire_nilOO0ll_dataout <= nlil1lO0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0l00O; + wire_nilOO0lO_dataout <= wire_nlOi1Oi0O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO0O_dataout <= niiil1l WHEN niOO0liOi = '1' ELSE wire_niO00Oi_dataout; + wire_nilOO0Oi_dataout <= nlil1lO0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni0l0ii; + wire_nilOO0Oi_w_lg_w_lg_w_lg_dataout29675w29678w29679w(0) <= wire_nilOO0Oi_w_lg_w_lg_dataout29675w29678w(0) AND niOl101ii; + wire_nilOO0Oi_w_lg_w_lg_dataout29675w29678w(0) <= wire_nilOO0Oi_w_lg_dataout29675w(0) AND wire_nilOOi1O_w_lg_w_lg_dataout29676w29677w(0); + wire_nilOO0Oi_w_lg_dataout29675w(0) <= NOT wire_nilOO0Oi_dataout; + wire_nilOO0Ol_dataout <= nlliiil1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO0Ol_w_lg_dataout43358w(0) <= NOT wire_nilOO0Ol_dataout; + wire_nilOO0OO_dataout <= nlliiil1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO0OO_w_lg_dataout43356w(0) <= NOT wire_nilOO0OO_dataout; + wire_nilOO10i_dataout <= wire_nlilillii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1Ol11l; + wire_nilOO10l_dataout <= wire_nlilill0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1Ol0li; + wire_nilOO10O_dataout <= wire_nlilill0l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE (nl1Oll1O OR nl1OlOll); + wire_nilOO11i_dataout <= nl011ll1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00ili; + wire_nilOO11i_w_lg_dataout29686w(0) <= NOT wire_nilOO11i_dataout; + wire_nilOO11l_dataout <= nl011ll1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE ni00ill; + wire_nilOO11l_w_lg_dataout29684w(0) <= NOT wire_nilOO11l_dataout; + wire_nilOO11O_dataout <= wire_nlilill0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1OlOll; + wire_nilOO1i_dataout <= niiiilO WHEN niOO0liOi = '1' ELSE wire_niO00il_dataout; + wire_nilOO1il_dataout <= wire_nlOii10OO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO1iO_dataout <= wire_nlOii1liO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO1l_dataout <= niiiiOi WHEN niOO0liOi = '1' ELSE wire_niO00iO_dataout; + wire_nilOO1li_dataout <= wire_nlOii011O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO1li_w_lg_dataout43976w(0) <= NOT wire_nilOO1li_dataout; + wire_nilOO1ll_dataout <= wire_nlOii00lO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOO1ll_w_lg_dataout43968w(0) <= NOT wire_nilOO1ll_dataout; + wire_nilOO1lO_dataout <= nlil01i0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1O01Ol; + wire_nilOO1O_dataout <= niiiiOl WHEN niOO0liOi = '1' ELSE wire_niO00li_dataout; + wire_nilOO1Oi_dataout <= wire_nlil1i1lO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1O0iii; + wire_nilOO1Ol_dataout <= wire_nlil1i1Oi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1O0lOO; + wire_nilOO1OO_dataout <= wire_nlil1i1Ol_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1Oi1il; + wire_nilOOi0i_dataout <= niOO1li0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOi0i_w_lg_dataout44011w(0) <= NOT wire_nilOOi0i_dataout; + wire_nilOOi0l_dataout <= niOO1li0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOi0l_w_lg_dataout43900w(0) <= NOT wire_nilOOi0l_dataout; + wire_nilOOi0O_dataout <= niOO1l0lO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOi0O_w_lg_dataout45195w(0) <= NOT wire_nilOOi0O_dataout; + wire_nilOOi1i_dataout <= nlliiil0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOi1i_w_lg_dataout43363w(0) <= wire_nilOOi1i_dataout AND wire_nilOO0OO_w_lg_dataout43356w(0); + wire_nilOOi1i_w_lg_dataout43355w(0) <= NOT wire_nilOOi1i_dataout; + wire_nilOOi1l_dataout <= nlliiilli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOi1O_dataout <= nlil1llOO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ll0ii; + wire_nilOOi1O_w_lg_w_lg_dataout29676w29677w(0) <= wire_nilOOi1O_w_lg_dataout29676w(0) AND wire_nlOl1l0Ol_dataout; + wire_nilOOi1O_w_lg_dataout29667w(0) <= NOT wire_nilOOi1O_dataout; + wire_nilOOi1O_w_lg_dataout29676w(0) <= wire_nilOOi1O_dataout OR wire_nlOi0lO0i_dataout; + wire_nilOOii_dataout <= niiil1O WHEN niOO0liOi = '1' ELSE wire_niO00Ol_dataout; + wire_nilOOiii_dataout <= wire_nlOiiii0O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOiii_w_lg_dataout45038w(0) <= wire_nilOOiii_dataout AND wire_nliiOiilO_w_lg_nliiOi11i44502w(0); + wire_nilOOiii_w_lg_dataout45502w(0) <= NOT wire_nilOOiii_dataout; + wire_nilOOiil_dataout <= niOO010il AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOiil_w_lg_dataout45193w(0) <= NOT wire_nilOOiil_dataout; + wire_nilOOiiO_dataout <= nlliiillO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOiiO_w_lg_dataout45191w(0) <= NOT wire_nilOOiiO_dataout; + wire_nilOOil_dataout <= niiil0i WHEN niOO0liOi = '1' ELSE wire_niO00OO_dataout; + wire_nilOOili_dataout <= nlll0101i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOili_w_lg_dataout45189w(0) <= NOT wire_nilOOili_dataout; + wire_nilOOill_dataout <= nlll011OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOill_w_lg_dataout45188w(0) <= NOT wire_nilOOill_dataout; + wire_nilOOill_w_lg_dataout43255w(0) <= wire_nilOOill_dataout OR wire_nilOOi0O_dataout; + wire_nilOOilO_dataout <= nlll0ilOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOilO_w_lg_dataout45039w(0) <= wire_nilOOilO_dataout AND wire_nliiOiilO_w_lg_nliiO0OOO44501w(0); + wire_nilOOilO_w_lg_dataout45501w(0) <= NOT wire_nilOOilO_dataout; + wire_nilOOiO_dataout <= niiil0l WHEN niOO0liOi = '1' ELSE wire_niO0i1i_dataout; + wire_nilOOiOi_dataout <= nl10OOii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOiOl_dataout <= nl10OOil AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOiOO_dataout <= nl10OOiO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOl0i_dataout <= nl10OOOi AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOl0l_dataout <= nl10OOOl AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOl0O_dataout <= nl10OOOO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOl1i_dataout <= nl10OOli AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOl1l_dataout <= nl10OOll AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOl1O_dataout <= nl10OOlO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOli_dataout <= niiil0O WHEN niOO0liOi = '1' ELSE wire_niO0i1l_dataout; + wire_nilOOlii_dataout <= nl1i111i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOlil_dataout <= nl1i111l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOliO_dataout <= nl1i111O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOll_dataout <= niiilii WHEN niOO0liOi = '1' ELSE wire_niO0i1O_dataout; + wire_nilOOlli_dataout <= nl1i110i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOlll_dataout <= nl1i110l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOllO_dataout <= nl1i110O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOlO_dataout <= niiilil WHEN niOO0liOi = '1' ELSE wire_niO0i0i_dataout; + wire_nilOOlOi_dataout <= nl1i11ii AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOlOl_dataout <= nl1i11il AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOlOO_dataout <= nl1i11iO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOO0i_dataout <= nlillii0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOO0i_w_lg_dataout60194w(0) <= wire_nilOOO0i_dataout AND wire_w_lg_niOi10l0O60193w(0); + wire_nilOOO0i_w_lg_dataout54084w(0) <= wire_nilOOO0i_dataout AND wire_nlill0Oll_w_lg_nl10lliOO54083w(0); + wire_nilOOO0i_w_lg_w_lg_dataout54084w54085w(0) <= NOT wire_nilOOO0i_w_lg_dataout54084w(0); + wire_nilOOO0i_w_lg_dataout47830w(0) <= NOT wire_nilOOO0i_dataout; + wire_nilOOO0l_dataout <= nlillii0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOO0l_w_lg_dataout59507w(0) <= NOT wire_nilOOO0l_dataout; + wire_nilOOO0O_dataout <= nlilliiii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOO0O_w_lg_dataout59505w(0) <= NOT wire_nilOOO0O_dataout; + wire_nilOOO1i_dataout <= nl1i11li AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOO1l_dataout <= nl1i11ll AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOO1O_dataout <= nl1i11lO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOOi_dataout <= niiiliO WHEN niOO0liOi = '1' ELSE wire_niO0i0l_dataout; + wire_nilOOOii_dataout <= nlilliiil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOOii_w_lg_dataout59503w(0) <= NOT wire_nilOOOii_dataout; + wire_nilOOOil_dataout <= nlilliiiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOOil_w_lg_dataout59501w(0) <= NOT wire_nilOOOil_dataout; + wire_nilOOOiO_dataout <= nlilliili AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOOiO_w_lg_dataout59499w(0) <= NOT wire_nilOOOiO_dataout; + wire_nilOOOl_dataout <= niiilli WHEN niOO0liOi = '1' ELSE wire_niO0i0O_dataout; + wire_nilOOOli_dataout <= nlilliill AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOOli_w_lg_dataout59497w(0) <= NOT wire_nilOOOli_dataout; + wire_nilOOOll_dataout <= nlilliilO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOOll_w_lg_dataout59496w(0) <= NOT wire_nilOOOll_dataout; + wire_nilOOOlO_dataout <= nl10lliO OR wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nilOOOlO_w_lg_dataout42845w(0) <= NOT wire_nilOOOlO_dataout; + wire_nilOOOO_dataout <= niiilll WHEN niOO0liOi = '1' ELSE wire_niO0iii_dataout; + wire_nilOOOOi_dataout <= nl10l0Ol AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOOOi_w_lg_dataout42849w(0) <= NOT wire_nilOOOOi_dataout; + wire_nilOOOOl_dataout <= nl10l0OO AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOOOl_w_lg_dataout42853w(0) <= NOT wire_nilOOOOl_dataout; + wire_nilOOOOO_dataout <= nl10li1i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nilOOOOO_w_lg_dataout42857w(0) <= NOT wire_nilOOOOO_dataout; + wire_niO000i_dataout <= niiiiil WHEN niOO0lill = '1' ELSE niOilOO; + wire_niO000l_dataout <= niiiiiO WHEN niOO0lill = '1' ELSE niOiO1i; + wire_niO000O_dataout <= niiiili WHEN niOO0lill = '1' ELSE niOiO1l; + wire_niO0010l_dataout <= core_rstn WHEN scan_mode = '1' ELSE niO01OOl; + wire_niO0011l_dataout <= core_clk AND niOO10OlO; + wire_niO0011O_dataout <= core_clk AND (k_hip(1) OR scan_mode); + wire_niO001i_dataout <= niiii0l WHEN niOO0lill = '1' ELSE niOillO; + wire_niO001iO_dataout <= phy_rstn WHEN scan_mode = '1' ELSE niO001il; + wire_niO001l_dataout <= niiii0O WHEN niOO0lill = '1' ELSE niOilOi; + wire_niO001O_dataout <= niiiiii WHEN niOO0lill = '1' ELSE niOilOl; + wire_niO00ii_dataout <= niiiill WHEN niOO0lill = '1' ELSE niOiO1O; + wire_niO00il_dataout <= niiiilO WHEN niOO0lill = '1' ELSE niOiO0i; + wire_niO00iO_dataout <= niiiiOi WHEN niOO0lill = '1' ELSE niOi01O; + wire_niO00li_dataout <= niiiiOl WHEN niOO0lill = '1' ELSE niOi00i; + wire_niO00ll_dataout <= niiiiOO WHEN niOO0lill = '1' ELSE niOi00l; + wire_niO00lO_dataout <= niiil1i WHEN niOO0lill = '1' ELSE niOi00O; + wire_niO00Oi_dataout <= niiil1l WHEN niOO0lill = '1' ELSE niOi0ii; + wire_niO00Oii_dataout <= wire_niO0il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00Oil_dataout <= wire_niO0il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00OiO_dataout <= wire_niO0il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00Ol_dataout <= niiil1O WHEN niOO0lill = '1' ELSE niOi0il; + wire_niO00Oli_dataout <= wire_niO0il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00Oll_dataout <= wire_niO0il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00OlO_dataout <= wire_niO0il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00OO_dataout <= niiil0i WHEN niOO0lill = '1' ELSE niOi0iO; + wire_niO00OOi_dataout <= wire_niO0ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00OOl_dataout <= wire_niO0ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO00OOO_dataout <= wire_niO0iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0101l_dataout <= niO011lO WHEN niOO10Oii = '1' ELSE wire_niO01ill_w_lg_nlOlO010l8783w(0); + wire_niO010i_dataout <= niOiiOO WHEN niOO0liOi = '1' ELSE nii0i1O; + wire_niO010l_dataout <= niOil1i WHEN niOO0liOi = '1' ELSE nii0i0i; + wire_niO010O_dataout <= niOil1l WHEN niOO0liOi = '1' ELSE nii0i0l; + wire_niO010Oi_dataout <= wire_niO01ill_w_lg_niO010ll8775w(0) WHEN (wire_niO01ill_w_lg_nlOlO010i8774w(0) AND (wire_w_lg_niOO10Oil8776w(0) AND wire_niO01ill_w_lg_w_lg_nlOlO010i8774w8777w(0))) = '1' ELSE niO010ll; + wire_niO011i_dataout <= niOiilO WHEN niOO0liOi = '1' ELSE nii00OO; + wire_niO011l_dataout <= niOiiOi WHEN niOO0liOi = '1' ELSE nii0i1i; + wire_niO011O_dataout <= niOiiOl WHEN niOO0liOi = '1' ELSE nii0i1l; + wire_niO011Oi_dataout <= wire_niO01ill_w_lg_niO011ll8784w(0) WHEN (wire_niO01ill_w_lg_nlOlO010l8783w(0) AND (wire_w_lg_niOO10Oii8785w(0) AND wire_niO01ill_w_lg_w_lg_nlOlO010l8783w8786w(0))) = '1' ELSE niO011ll; + wire_niO01i1l_dataout <= niO010lO WHEN niOO10Oil = '1' ELSE wire_niO01ill_w_lg_nlOlO010i8774w(0); + wire_niO01ii_dataout <= niOil1O WHEN niOO0liOi = '1' ELSE nii0i0O; + wire_niO01il_dataout <= niOil0i WHEN niOO0liOi = '1' ELSE nii0iii; + wire_niO01iO_dataout <= niii0Oi WHEN niOO0lill = '1' ELSE niOiO0l; + wire_niO01iOO_dataout <= wire_niO01ill_w_lg_niO01ilO8766w(0) WHEN (wire_niO01ill_w_lg_nlOlO011i8765w(0) AND (wire_w_lg_niOO10OiO8767w(0) AND wire_niO01ill_w_lg_w_lg_nlOlO011i8765w8768w(0))) = '1' ELSE niO01ilO; + wire_niO01l0i_dataout <= niO01iOl WHEN niOO10OiO = '1' ELSE wire_niO01ill_w_lg_nlOlO011i8765w(0); + wire_niO01l0O_dataout <= pld_srst WHEN scan_mode = '1' ELSE niO01lOl; + wire_niO01li_dataout <= niii0Ol WHEN niOO0lill = '1' ELSE niOiO0O; + wire_niO01lil_dataout <= pld_rstn WHEN scan_mode = '1' ELSE niO01lii; + wire_niO01ll_dataout <= niii0OO WHEN niOO0lill = '1' ELSE niOilii; + wire_niO01lO_dataout <= niiii1i WHEN niOO0lill = '1' ELSE niOilil; + wire_niO01lOO_dataout <= phy_srst WHEN scan_mode = '1' ELSE niO01lOi; + wire_niO01O0O_dataout <= core_srst WHEN scan_mode = '1' ELSE niO01Oii; + wire_niO01Oi_dataout <= niiii1l WHEN niOO0lill = '1' ELSE niOiliO; + wire_niO01Oil_dataout <= core_crst WHEN scan_mode = '1' ELSE niO01O1l; + wire_niO01Ol_dataout <= niiii1O WHEN niOO0lill = '1' ELSE niOilli; + wire_niO01Oli_dataout <= core_npor WHEN scan_mode = '1' ELSE niO01Oll; + wire_niO01OO_dataout <= niiii0i WHEN niOO0lill = '1' ELSE niOilll; + wire_niO01OOO_dataout <= pld_clk AND niOO10OlO; + wire_niO0i00i_dataout <= wire_niO0iOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i00l_dataout <= wire_niO0iOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i00O_dataout <= wire_niO0iOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i01i_dataout <= wire_niO0iOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i01l_dataout <= wire_niO0iOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i01O_dataout <= wire_niO0iOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0i_dataout <= niiilil WHEN niOO0lill = '1' ELSE niOi0Oi; + wire_niO0i0ii_dataout <= wire_niO0l11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0il_dataout <= wire_niO0l11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0iO_dataout <= wire_niO0l11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0l_dataout <= niiiliO WHEN niOO0lill = '1' ELSE niOi0Ol; + wire_niO0i0li_dataout <= wire_niO0l10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0ll_dataout <= wire_niO0l10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0lO_dataout <= wire_niO0l10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0O_dataout <= niiilli WHEN niOO0lill = '1' ELSE niOi0OO; + wire_niO0i0Oi_dataout <= wire_niO0l1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0Ol_dataout <= wire_niO0l1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i0OO_dataout <= wire_niO0l1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i10i_dataout <= wire_niO0ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i10l_dataout <= wire_niO0ilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i10O_dataout <= wire_niO0ilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i11i_dataout <= wire_niO0illi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i11l_dataout <= wire_niO0illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i11O_dataout <= wire_niO0illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1i_dataout <= niiil0l WHEN niOO0lill = '1' ELSE niOi0li; + wire_niO0i1ii_dataout <= wire_niO0iO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1il_dataout <= wire_niO0iO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1iO_dataout <= wire_niO0iO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1l_dataout <= niiil0O WHEN niOO0lill = '1' ELSE niOi0ll; + wire_niO0i1li_dataout <= wire_niO0iO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1ll_dataout <= wire_niO0iO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1lO_dataout <= wire_niO0iO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1O_dataout <= niiilii WHEN niOO0lill = '1' ELSE niOi0lO; + wire_niO0i1Oi_dataout <= wire_niO0iOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1Ol_dataout <= wire_niO0iOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0i1OO_dataout <= wire_niO0iOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0ii0i_dataout <= wire_niO0l1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0ii0l_dataout <= wire_niO0l1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0ii0O_dataout <= wire_niO0l1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0ii1i_dataout <= wire_niO0l1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0ii1l_dataout <= wire_niO0l1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0ii1O_dataout <= wire_niO0l1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iii_dataout <= niiilll WHEN niOO0lill = '1' ELSE niOii1i; + wire_niO0iiii_dataout <= wire_niO0l01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iiil_dataout <= wire_niO0l01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iiiO_dataout <= wire_niO0l01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iil_dataout <= niiillO WHEN niOO0lill = '1' ELSE niOii1l; + wire_niO0iili_dataout <= wire_niO0l00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iill_dataout <= wire_niO0l00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iilO_dataout <= wire_niO0l00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iiO_dataout <= niiilOi WHEN niOO0lill = '1' ELSE niOii1O; + wire_niO0iiOi_dataout <= wire_niO0l0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iiOl_dataout <= wire_niO0l0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0iiOO_dataout <= wire_niO0l0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0il0i_dataout <= nl0OiO1li WHEN niO0l0Oi = '1' ELSE niO001OO; + wire_niO0il0l_dataout <= nl0OiO1iO WHEN niO0l0Oi = '1' ELSE niO0001i; + wire_niO0il0O_dataout <= nl0OiO1il WHEN niO0l0Oi = '1' ELSE niO0001l; + wire_niO0il1i_dataout <= wire_nl1000i_w_lg_niO0l0li8755w(0) WHEN niO0l0Oi = '1' ELSE niO0l0li; + wire_niO0il1l_dataout <= nl0OiO1lO WHEN niO0l0Oi = '1' ELSE niO001Oi; + wire_niO0il1O_dataout <= nl0OiO1ll WHEN niO0l0Oi = '1' ELSE niO001Ol; + wire_niO0ili_dataout <= niiilOl WHEN niOO0lill = '1' ELSE niOii0i; + wire_niO0ilii_dataout <= nl0OiO0li WHEN niO0l0Oi = '1' ELSE niO0001O; + wire_niO0ilil_dataout <= wire_nli1011ii_dataout WHEN niO0l0Oi = '1' ELSE niO0000i; + wire_niO0iliO_dataout <= wire_nli1011il_dataout WHEN niO0l0Oi = '1' ELSE niO0000l; + wire_niO0ill_dataout <= niiilOO WHEN niOO0lill = '1' ELSE niOii0l; + wire_niO0illi_dataout <= wire_nli1011iO_dataout WHEN niO0l0Oi = '1' ELSE niO0000O; + wire_niO0illl_dataout <= wire_nli1011li_dataout WHEN niO0l0Oi = '1' ELSE niO000ii; + wire_niO0illO_dataout <= wire_nli1011ll_dataout WHEN niO0l0Oi = '1' ELSE niO000il; + wire_niO0ilO_dataout <= niiiO1i WHEN niOO0lill = '1' ELSE niOii0O; + wire_niO0ilOi_dataout <= wire_nli1011lO_dataout WHEN niO0l0Oi = '1' ELSE niO000iO; + wire_niO0ilOl_dataout <= wire_nli1011Oi_dataout WHEN niO0l0Oi = '1' ELSE niO000li; + wire_niO0ilOO_dataout <= wire_nli1011Ol_dataout WHEN niO0l0Oi = '1' ELSE niO000ll; + wire_niO0iO0i_dataout <= wire_nli10101O_dataout WHEN niO0l0Oi = '1' ELSE niO000OO; + wire_niO0iO0l_dataout <= wire_nli10100i_dataout WHEN niO0l0Oi = '1' ELSE niO00i1i; + wire_niO0iO0O_dataout <= wire_nli10100l_dataout WHEN niO0l0Oi = '1' ELSE niO00i1l; + wire_niO0iO1i_dataout <= wire_nli1011OO_dataout WHEN niO0l0Oi = '1' ELSE niO000lO; + wire_niO0iO1l_dataout <= wire_nli10101i_dataout WHEN niO0l0Oi = '1' ELSE niO000Oi; + wire_niO0iO1O_dataout <= wire_nli10101l_dataout WHEN niO0l0Oi = '1' ELSE niO000Ol; + wire_niO0iOi_dataout <= niiiO1l WHEN niOO0lill = '1' ELSE niOiiii; + wire_niO0iOii_dataout <= wire_nli10100O_dataout WHEN niO0l0Oi = '1' ELSE niO00i1O; + wire_niO0iOil_dataout <= wire_nli1010ii_dataout WHEN niO0l0Oi = '1' ELSE niO00i0i; + wire_niO0iOiO_dataout <= wire_nli10110O_dataout WHEN niO0l0Oi = '1' ELSE niO00i0l; + wire_niO0iOl_dataout <= niiiO1O WHEN niOO0lill = '1' ELSE niOiiil; + wire_niO0iOli_dataout <= niOO10OOi WHEN niO0l0Oi = '1' ELSE niO00i0O; + wire_niO0iOll_dataout <= nl0l001Oi WHEN niO0l0Oi = '1' ELSE niO00iii; + wire_niO0iOlO_dataout <= nl0l001lO WHEN niO0l0Oi = '1' ELSE niO00iil; + wire_niO0iOO_dataout <= niiiO0i WHEN niOO0lill = '1' ELSE niOiiiO; + wire_niO0iOOi_dataout <= nl0l001ll WHEN niO0l0Oi = '1' ELSE niO00iiO; + wire_niO0iOOl_dataout <= nl0l001li WHEN niO0l0Oi = '1' ELSE niO00ili; + wire_niO0iOOO_dataout <= nl0l001iO WHEN niO0l0Oi = '1' ELSE niO00ill; + wire_niO0l00i_dataout <= nli10Olli WHEN niO0l0Oi = '1' ELSE niO00lOO; + wire_niO0l00l_dataout <= nli10Olil WHEN niO0l0Oi = '1' ELSE niO00O1i; + wire_niO0l00O_dataout <= nli1ilO1l WHEN niO0l0Oi = '1' ELSE niO00O1l; + wire_niO0l01i_dataout <= wire_nli1iii0O_dataout WHEN niO0l0Oi = '1' ELSE niO00llO; + wire_niO0l01l_dataout <= nli1iiili WHEN niO0l0Oi = '1' ELSE niO00lOi; + wire_niO0l01O_dataout <= nli1iiill WHEN niO0l0Oi = '1' ELSE niO00lOl; + wire_niO0l0i_dataout <= niiiOil WHEN niOO0lill = '1' ELSE niOiiOi; + wire_niO0l0ii_dataout <= nli1ilO1i WHEN niO0l0Oi = '1' ELSE niO00O1O; + wire_niO0l0il_dataout <= nli1illOO WHEN niO0l0Oi = '1' ELSE niO00O0i; + wire_niO0l0iO_dataout <= nli1illOl WHEN niO0l0Oi = '1' ELSE niO00O0l; + wire_niO0l0l_dataout <= niiiOiO WHEN niOO0lill = '1' ELSE niOiiOl; + wire_niO0l0O_dataout <= niiiOli WHEN niOO0lill = '1' ELSE niOiiOO; + wire_niO0l0Ol_dataout <= wire_niO0li1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0l0OO_dataout <= wire_niO0li0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0l10i_dataout <= wire_nlOi00O0i_dataout WHEN niO0l0Oi = '1' ELSE niO00iOO; + wire_niO0l10l_dataout <= niO00l1i AND NOT(niO0l0Oi); + wire_niO0l10O_dataout <= niO00l1l AND NOT(niO0l0Oi); + wire_niO0l11i_dataout <= nl0l000ll WHEN niO0l0Oi = '1' ELSE niO00ilO; + wire_niO0l11l_dataout <= wire_nlOi0i01O_dataout WHEN niO0l0Oi = '1' ELSE niO00iOi; + wire_niO0l11O_dataout <= wire_nlOi00O1O_dataout WHEN niO0l0Oi = '1' ELSE niO00iOl; + wire_niO0l1i_dataout <= niiiO0l WHEN niOO0lill = '1' ELSE niOiili; + wire_niO0l1ii_dataout <= wire_nlOiillOl_dataout WHEN niO0l0Oi = '1' ELSE niO00l1O; + wire_niO0l1il_dataout <= wire_nlOiillOO_dataout WHEN niO0l0Oi = '1' ELSE niO00l0i; + wire_niO0l1iO_dataout <= wire_nlOiilO1i_dataout WHEN niO0l0Oi = '1' ELSE niO00l0l; + wire_niO0l1l_dataout <= niiiO0O WHEN niOO0lill = '1' ELSE niOiill; + wire_niO0l1li_dataout <= wire_nlOiilO1l_dataout WHEN niO0l0Oi = '1' ELSE niO00l0O; + wire_niO0l1ll_dataout <= niO00lii AND NOT(niO0l0Oi); + wire_niO0l1lO_dataout <= niO00lil AND NOT(niO0l0Oi); + wire_niO0l1O_dataout <= niiiOii WHEN niOO0lill = '1' ELSE niOiilO; + wire_niO0l1Oi_dataout <= wire_nli1iiiil_dataout WHEN niO0l0Oi = '1' ELSE niO00liO; + wire_niO0l1Ol_dataout <= wire_nli1iiiii_dataout WHEN niO0l0Oi = '1' ELSE niO00lli; + wire_niO0l1OO_dataout <= niOO0ili WHEN niO0l0Oi = '1' ELSE niO00lll; + wire_niO0li0i_dataout <= wire_niO0li0O_o(1) AND NOT(niOO10OOl); + wire_niO0li0l_dataout <= wire_niO0li0O_o(2) AND NOT(niOO10OOl); + wire_niO0li1i_dataout <= wire_niO0li0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0li1l_dataout <= niOO10OOl AND NOT(wire_niO01O0O_dataout); + wire_niO0li1O_dataout <= wire_niO0li0O_o(0) AND NOT(niOO10OOl); + wire_niO0lii_dataout <= niiiOll WHEN niOO0lill = '1' ELSE niOil1i; + wire_niO0lil_dataout <= niiiOlO WHEN niOO0lill = '1' ELSE niOil1l; + wire_niO0liO_dataout <= niiiOOi WHEN niOO0lill = '1' ELSE niOil1O; + wire_niO0lli_dataout <= niiiOOl WHEN niOO0lill = '1' ELSE niOil0i; + wire_niO0lll_dataout <= niOi01O WHEN niOO0lill = '1' ELSE ni0Ol0O; + wire_niO0llO_dataout <= niOi00i WHEN niOO0lill = '1' ELSE nii1l0l; + wire_niO0lOi_dataout <= niOi00l WHEN niOO0lill = '1' ELSE nii1l0O; + wire_niO0lOl_dataout <= niOi00O WHEN niOO0lill = '1' ELSE nii1lii; + wire_niO0lOO_dataout <= niOi0ii WHEN niOO0lill = '1' ELSE nii1lil; + wire_niO0lOOO_dataout <= wire_niO0Oiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O00i_dataout <= wire_niO0Olll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O00l_dataout <= wire_niO0OllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O00O_dataout <= wire_niO0OlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O01i_dataout <= wire_niO0Olil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O01l_dataout <= wire_niO0OliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O01O_dataout <= wire_niO0Olli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0i_dataout <= niOi0ll WHEN niOO0lill = '1' ELSE nii1llO; + wire_niO0O0ii_dataout <= wire_niO0OlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0il_dataout <= wire_niO0OlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0iO_dataout <= wire_niO0OO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0l_dataout <= niOi0lO WHEN niOO0lill = '1' ELSE nii1lOi; + wire_niO0O0li_dataout <= wire_niO0OO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0ll_dataout <= wire_niO0OO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0lO_dataout <= wire_niO0OO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0O_dataout <= niOi0Oi WHEN niOO0lill = '1' ELSE nii1lOl; + wire_niO0O0Oi_dataout <= wire_niO0OO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0Ol_dataout <= wire_niO0OO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O0OO_dataout <= wire_niO0OOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O10i_dataout <= wire_niO0Oill_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O10l_dataout <= wire_niO0OilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O10O_dataout <= wire_niO0OiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O11i_dataout <= wire_niO0Oiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O11l_dataout <= wire_niO0OiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O11O_dataout <= wire_niO0Oili_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1i_dataout <= niOi0il WHEN niOO0lill = '1' ELSE nii1liO; + wire_niO0O1ii_dataout <= wire_niO0OiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1il_dataout <= wire_niO0OiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1iO_dataout <= wire_niO0Ol1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1l_dataout <= niOi0iO WHEN niOO0lill = '1' ELSE nii1lli; + wire_niO0O1li_dataout <= wire_niO0Ol1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1ll_dataout <= wire_niO0Ol1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1lO_dataout <= wire_niO0Ol0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1O_dataout <= niOi0li WHEN niOO0lill = '1' ELSE nii1lll; + wire_niO0O1Oi_dataout <= wire_niO0Ol0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1Ol_dataout <= wire_niO0Ol0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0O1OO_dataout <= wire_niO0Olii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0Oi0i_dataout <= wire_niO0OOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0Oi0l_dataout <= wire_niO0OOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0Oi0O_dataout <= wire_niO0OOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0Oi1i_dataout <= wire_niO0OOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0Oi1l_dataout <= wire_niO0OOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0Oi1O_dataout <= wire_niO0OOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niO0Oii_dataout <= niOi0Ol WHEN niOO0lill = '1' ELSE nii1lOO; + wire_niO0Oiii_dataout <= wire_nl1000i_w_lg_niO0OOOl1060w(0) WHEN niOi111l = '1' ELSE niO0OOOl; + wire_niO0Oiil_dataout <= nl11lOl WHEN niOi111l = '1' ELSE niO0liil; + wire_niO0OiiO_dataout <= nl11lOO WHEN niOi111l = '1' ELSE niO0liiO; + wire_niO0Oil_dataout <= niOi0OO WHEN niOO0lill = '1' ELSE nii1O1i; + wire_niO0Oili_dataout <= nl11O1i WHEN niOi111l = '1' ELSE niO0lili; + wire_niO0Oill_dataout <= nl11O1l WHEN niOi111l = '1' ELSE niO0lill; + wire_niO0OilO_dataout <= nl11O1O WHEN niOi111l = '1' ELSE niO0lilO; + wire_niO0OiO_dataout <= niOii1i WHEN niOO0lill = '1' ELSE nii1O1l; + wire_niO0OiOi_dataout <= nl11O0i WHEN niOi111l = '1' ELSE niO0liOi; + wire_niO0OiOl_dataout <= nl11O0l WHEN niOi111l = '1' ELSE niO0liOl; + wire_niO0OiOO_dataout <= nl11O0O WHEN niOi111l = '1' ELSE niO0liOO; + wire_niO0Ol0i_dataout <= nl11Oli WHEN niOi111l = '1' ELSE niO0ll0i; + wire_niO0Ol0l_dataout <= nl11Oll WHEN niOi111l = '1' ELSE niO0ll0l; + wire_niO0Ol0O_dataout <= nl11OlO WHEN niOi111l = '1' ELSE niO0ll0O; + wire_niO0Ol1i_dataout <= nl11Oii WHEN niOi111l = '1' ELSE niO0ll1i; + wire_niO0Ol1l_dataout <= nl11Oil WHEN niOi111l = '1' ELSE niO0ll1l; + wire_niO0Ol1O_dataout <= nl11OiO WHEN niOi111l = '1' ELSE niO0ll1O; + wire_niO0Oli_dataout <= niOii1l WHEN niOO0lill = '1' ELSE nii1O1O; + wire_niO0Olii_dataout <= nl11OOi WHEN niOi111l = '1' ELSE niO0llii; + wire_niO0Olil_dataout <= nl11OOl WHEN niOi111l = '1' ELSE niO0llil; + wire_niO0OliO_dataout <= nl11OOO WHEN niOi111l = '1' ELSE niO0lliO; + wire_niO0Oll_dataout <= niOii1O WHEN niOO0lill = '1' ELSE nii1O0i; + wire_niO0Olli_dataout <= nl1011i WHEN niOi111l = '1' ELSE niO0llli; + wire_niO0Olll_dataout <= nl1011l WHEN niOi111l = '1' ELSE niO0llll; + wire_niO0OllO_dataout <= nl1011O WHEN niOi111l = '1' ELSE niO0lllO; + wire_niO0OlO_dataout <= niOii0i WHEN niOO0lill = '1' ELSE nii1O0l; + wire_niO0OlOi_dataout <= nl1010i WHEN niOi111l = '1' ELSE niO0llOi; + wire_niO0OlOl_dataout <= nl1010l WHEN niOi111l = '1' ELSE niO0llOl; + wire_niO0OlOO_dataout <= nl1010O WHEN niOi111l = '1' ELSE niO0llOO; + wire_niO0OO0i_dataout <= nl101li WHEN niOi111l = '1' ELSE niO0lO0i; + wire_niO0OO0l_dataout <= nl101ll WHEN niOi111l = '1' ELSE niO0lO0l; + wire_niO0OO0O_dataout <= nl101lO WHEN niOi111l = '1' ELSE niO0lO0O; + wire_niO0OO1i_dataout <= nl101ii WHEN niOi111l = '1' ELSE niO0lO1i; + wire_niO0OO1l_dataout <= nl101il WHEN niOi111l = '1' ELSE niO0lO1l; + wire_niO0OO1O_dataout <= nl101iO WHEN niOi111l = '1' ELSE niO0lO1O; + wire_niO0OOi_dataout <= niOii0l WHEN niOO0lill = '1' ELSE nii1O0O; + wire_niO0OOii_dataout <= nl101Oi WHEN niOi111l = '1' ELSE niO0lOii; + wire_niO0OOil_dataout <= nl101Ol WHEN niOi111l = '1' ELSE niO0lOil; + wire_niO0OOiO_dataout <= nl101OO WHEN niOi111l = '1' ELSE niO0lOiO; + wire_niO0OOl_dataout <= niOii0O WHEN niOO0lill = '1' ELSE nii1Oii; + wire_niO0OOli_dataout <= nl1001i WHEN niOi111l = '1' ELSE niO0lOli; + wire_niO0OOll_dataout <= nl1001l WHEN niOi111l = '1' ELSE niO0lOll; + wire_niO0OOlO_dataout <= nl1001O WHEN niOi111l = '1' ELSE niO0lOlO; + wire_niO0OOO_dataout <= niOiiii WHEN niOO0lill = '1' ELSE nii1Oil; + wire_niO0OOOi_dataout <= nl1000l WHEN niOi111l = '1' ELSE niO0lOOi; + wire_niO1000i_dataout <= niO1ilOi WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(0); + wire_niO1000i_w_lg_dataout15784w(0) <= NOT wire_niO1000i_dataout; + wire_niO1000l_dataout <= niO1ilOl WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(1); + wire_niO1000l_w_lg_dataout15782w(0) <= NOT wire_niO1000l_dataout; + wire_niO1000O_dataout <= niO1ilOO WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(2); + wire_niO1000O_w_lg_dataout15830w(0) <= NOT wire_niO1000O_dataout; + wire_niO1001i_dataout <= niO1illi WHEN (NOT k_hip(3)) = '1' ELSE phystatus3; + wire_niO1001i_w_lg_dataout19798w(0) <= NOT wire_niO1001i_dataout; + wire_niO1001l_dataout <= niO1illl WHEN (NOT k_hip(3)) = '1' ELSE rxvalid3; + wire_niO1001l_w_lg_dataout27506w(0) <= NOT wire_niO1001l_dataout; + wire_niO1001O_dataout <= niO1illO WHEN (NOT k_hip(3)) = '1' ELSE rxdatak3; + wire_niO1001O_w_lg_dataout15432w(0) <= NOT wire_niO1001O_dataout; + wire_niO100i_dataout <= niOO0lill OR niOO0liOi; + wire_niO100ii_dataout <= niO1iO1i WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(3); + wire_niO100ii_w_lg_dataout15808w(0) <= NOT wire_niO100ii_dataout; + wire_niO100il_dataout <= niO1iO1l WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(4); + wire_niO100il_w_lg_dataout15841w(0) <= NOT wire_niO100il_dataout; + wire_niO100iO_dataout <= niO1iO1O WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(5); + wire_niO100iO_w_lg_dataout15797w(0) <= NOT wire_niO100iO_dataout; + wire_niO100l_dataout <= ni0Ol0O WHEN niOO0liOi = '1' ELSE wire_niO0lll_dataout; + wire_niO100li_dataout <= niO1iO0i WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(6); + wire_niO100li_w_lg_dataout15776w(0) <= NOT wire_niO100li_dataout; + wire_niO100ll_dataout <= niO1iO0l WHEN (NOT k_hip(3)) = '1' ELSE rxdata3(7); + wire_niO100ll_w15851w(0) <= wire_niO100ll_w_lg_w_lg_w_lg_w15842w15848w15849w15850w(0) AND wire_niO1000i_dataout; + wire_niO100ll_w_lg_w_lg_w_lg_w15835w15836w15837w15838w(0) <= wire_niO100ll_w_lg_w_lg_w15835w15836w15837w(0) AND wire_niO1000i_dataout; + wire_niO100ll_w_lg_w_lg_w_lg_w15842w15848w15849w15850w(0) <= wire_niO100ll_w_lg_w_lg_w15842w15848w15849w(0) AND wire_niO1000l_w_lg_dataout15782w(0); + wire_niO100ll_w_lg_w_lg_w_lg_w15842w15843w15844w15845w(0) <= wire_niO100ll_w_lg_w_lg_w15842w15843w15844w(0) AND wire_niO1000l_dataout; + wire_niO100ll_w_lg_w_lg_w15835w15836w15837w(0) <= wire_niO100ll_w_lg_w15835w15836w(0) AND wire_niO1000l_w_lg_dataout15782w(0); + wire_niO100ll_w_lg_w_lg_w15780w15831w15832w(0) <= wire_niO100ll_w_lg_w15780w15831w(0) AND wire_niO1000l_dataout; + wire_niO100ll_w_lg_w_lg_w15799w15800w15801w(0) <= wire_niO100ll_w_lg_w15799w15800w(0) AND wire_niO1000O_dataout; + wire_niO100ll_w_lg_w_lg_w15842w15848w15849w(0) <= wire_niO100ll_w_lg_w15842w15848w(0) AND wire_niO1000O_dataout; + wire_niO100ll_w_lg_w_lg_w15842w15843w15844w(0) <= wire_niO100ll_w_lg_w15842w15843w(0) AND wire_niO1000O_w_lg_dataout15830w(0); + wire_niO100ll_w_lg_w_lg_w15790w15791w15792w(0) <= wire_niO100ll_w_lg_w15790w15791w(0) AND wire_niO1000O_dataout; + wire_niO100ll_w_lg_w15835w15836w(0) <= wire_niO100ll_w15835w(0) AND wire_niO1000O_dataout; + wire_niO100ll_w_lg_w15780w15831w(0) <= wire_niO100ll_w15780w(0) AND wire_niO1000O_w_lg_dataout15830w(0); + wire_niO100ll_w_lg_w15780w15781w(0) <= wire_niO100ll_w15780w(0) AND wire_niO1000O_dataout; + wire_niO100ll_w_lg_w15934w15935w(0) <= wire_niO100ll_w15934w(0) AND wire_niO1000O_dataout; + wire_niO100ll_w_lg_w15799w15800w(0) <= wire_niO100ll_w15799w(0) AND wire_niO100ii_dataout; + wire_niO100ll_w_lg_w15842w15848w(0) <= wire_niO100ll_w15842w(0) AND wire_niO100ii_w_lg_dataout15808w(0); + wire_niO100ll_w_lg_w15842w15843w(0) <= wire_niO100ll_w15842w(0) AND wire_niO100ii_dataout; + wire_niO100ll_w_lg_w15790w15791w(0) <= wire_niO100ll_w15790w(0) AND wire_niO100ii_dataout; + wire_niO100ll_w15835w(0) <= wire_niO100ll_w_lg_w_lg_w_lg_dataout15777w15778w15779w(0) AND wire_niO100ii_w_lg_dataout15808w(0); + wire_niO100ll_w15780w(0) <= wire_niO100ll_w_lg_w_lg_w_lg_dataout15777w15778w15779w(0) AND wire_niO100ii_dataout; + wire_niO100ll_w15934w(0) <= wire_niO100ll_w_lg_w_lg_w_lg_dataout15805w15806w15807w(0) AND wire_niO100ii_dataout; + wire_niO100ll_w15799w(0) <= wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15796w15798w(0) AND wire_niO100il_dataout; + wire_niO100ll_w15842w(0) <= wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15788w15840w(0) AND wire_niO100il_w_lg_dataout15841w(0); + wire_niO100ll_w15790w(0) <= wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15788w15789w(0) AND wire_niO100il_dataout; + wire_niO100ll_w_lg_w_lg_w_lg_dataout15777w15778w15779w(0) <= wire_niO100ll_w_lg_w_lg_dataout15777w15778w(0) AND wire_niO100il_dataout; + wire_niO100ll_w_lg_w_lg_w_lg_dataout15805w15806w15807w(0) <= wire_niO100ll_w_lg_w_lg_dataout15805w15806w(0) AND wire_niO100il_dataout; + wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15796w15798w(0) <= wire_niO100ll_w_lg_w_lg_dataout15787w15796w(0) AND wire_niO100iO_w_lg_dataout15797w(0); + wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15788w15840w(0) <= wire_niO100ll_w_lg_w_lg_dataout15787w15788w(0) AND wire_niO100iO_w_lg_dataout15797w(0); + wire_niO100ll_w_lg_w_lg_w_lg_dataout15787w15788w15789w(0) <= wire_niO100ll_w_lg_w_lg_dataout15787w15788w(0) AND wire_niO100iO_dataout; + wire_niO100ll_w_lg_w_lg_dataout15777w15778w(0) <= wire_niO100ll_w_lg_dataout15777w(0) AND wire_niO100iO_dataout; + wire_niO100ll_w_lg_w_lg_dataout15805w15806w(0) <= wire_niO100ll_w_lg_dataout15805w(0) AND wire_niO100iO_dataout; + wire_niO100ll_w_lg_w_lg_dataout15787w15796w(0) <= wire_niO100ll_w_lg_dataout15787w(0) AND wire_niO100li_w_lg_dataout15776w(0); + wire_niO100ll_w_lg_w_lg_dataout15787w15788w(0) <= wire_niO100ll_w_lg_dataout15787w(0) AND wire_niO100li_dataout; + wire_niO100ll_w_lg_dataout15777w(0) <= wire_niO100ll_dataout AND wire_niO100li_w_lg_dataout15776w(0); + wire_niO100ll_w_lg_dataout15805w(0) <= wire_niO100ll_dataout AND wire_niO100li_dataout; + wire_niO100ll_w_lg_dataout15787w(0) <= NOT wire_niO100ll_dataout; + wire_niO100lO_dataout <= niO1iO0O WHEN (NOT k_hip(3)) = '1' ELSE rxstatus2(0); + wire_niO100lO_w_lg_dataout16298w(0) <= NOT wire_niO100lO_dataout; + wire_niO100O_dataout <= nii1l0l WHEN niOO0liOi = '1' ELSE wire_niO0llO_dataout; + wire_niO100Oi_dataout <= niO1iOii WHEN (NOT k_hip(3)) = '1' ELSE rxstatus2(1); + wire_niO100Oi_w_lg_dataout16296w(0) <= NOT wire_niO100Oi_dataout; + wire_niO100Ol_dataout <= niO1iOil WHEN (NOT k_hip(3)) = '1' ELSE rxstatus2(2); + wire_niO100Ol_w_lg_w_lg_w_lg_dataout16630w23925w23926w(0) <= wire_niO100Ol_w_lg_w_lg_dataout16630w23925w(0) AND wire_niO100lO_dataout; + wire_niO100Ol_w_lg_w_lg_dataout16300w16301w(0) <= wire_niO100Ol_w_lg_dataout16300w(0) AND wire_niO100lO_dataout; + wire_niO100Ol_w_lg_w_lg_dataout16630w23925w(0) <= wire_niO100Ol_w_lg_dataout16630w(0) AND wire_niO100Oi_dataout; + wire_niO100Ol_w_lg_dataout16297w(0) <= wire_niO100Ol_dataout AND wire_niO100Oi_w_lg_dataout16296w(0); + wire_niO100Ol_w_lg_dataout16300w(0) <= wire_niO100Ol_dataout AND wire_niO100Oi_dataout; + wire_niO100Ol_w_lg_dataout16630w(0) <= NOT wire_niO100Ol_dataout; + wire_niO100OO_dataout <= niO110iO WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle2; + wire_niO1010i_dataout <= niO1iiOl WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(0); + wire_niO1010i_w_lg_dataout14877w(0) <= NOT wire_niO1010i_dataout; + wire_niO1010l_dataout <= niO1iiOO WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(1); + wire_niO1010l_w_lg_dataout14875w(0) <= NOT wire_niO1010l_dataout; + wire_niO1010O_dataout <= niO1il1i WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(2); + wire_niO1010O_w_lg_dataout14923w(0) <= NOT wire_niO1010O_dataout; + wire_niO1011i_dataout <= niO1iill WHEN (NOT k_hip(3)) = '1' ELSE phystatus4; + wire_niO1011i_w_lg_dataout19802w(0) <= NOT wire_niO1011i_dataout; + wire_niO1011l_dataout <= niO1iilO WHEN (NOT k_hip(3)) = '1' ELSE rxvalid4; + wire_niO1011l_w_lg_dataout27511w(0) <= NOT wire_niO1011l_dataout; + wire_niO1011O_dataout <= niO1iiOi WHEN (NOT k_hip(3)) = '1' ELSE rxdatak4; + wire_niO1011O_w_lg_dataout14525w(0) <= NOT wire_niO1011O_dataout; + wire_niO101i_dataout <= niiiOlO WHEN niOO0liOi = '1' ELSE wire_niO0lil_dataout; + wire_niO101ii_dataout <= niO1il1l WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(3); + wire_niO101ii_w_lg_dataout14901w(0) <= NOT wire_niO101ii_dataout; + wire_niO101il_dataout <= niO1il1O WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(4); + wire_niO101il_w_lg_dataout14934w(0) <= NOT wire_niO101il_dataout; + wire_niO101iO_dataout <= niO1il0i WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(5); + wire_niO101iO_w_lg_dataout14890w(0) <= NOT wire_niO101iO_dataout; + wire_niO101l_dataout <= niiiOOi WHEN niOO0liOi = '1' ELSE wire_niO0liO_dataout; + wire_niO101li_dataout <= niO1il0l WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(6); + wire_niO101li_w_lg_dataout14869w(0) <= NOT wire_niO101li_dataout; + wire_niO101ll_dataout <= niO1il0O WHEN (NOT k_hip(3)) = '1' ELSE rxdata4(7); + wire_niO101ll_w14944w(0) <= wire_niO101ll_w_lg_w_lg_w_lg_w14935w14941w14942w14943w(0) AND wire_niO1010i_dataout; + wire_niO101ll_w_lg_w_lg_w_lg_w14928w14929w14930w14931w(0) <= wire_niO101ll_w_lg_w_lg_w14928w14929w14930w(0) AND wire_niO1010i_dataout; + wire_niO101ll_w_lg_w_lg_w_lg_w14935w14941w14942w14943w(0) <= wire_niO101ll_w_lg_w_lg_w14935w14941w14942w(0) AND wire_niO1010l_w_lg_dataout14875w(0); + wire_niO101ll_w_lg_w_lg_w_lg_w14935w14936w14937w14938w(0) <= wire_niO101ll_w_lg_w_lg_w14935w14936w14937w(0) AND wire_niO1010l_dataout; + wire_niO101ll_w_lg_w_lg_w14928w14929w14930w(0) <= wire_niO101ll_w_lg_w14928w14929w(0) AND wire_niO1010l_w_lg_dataout14875w(0); + wire_niO101ll_w_lg_w_lg_w14873w14924w14925w(0) <= wire_niO101ll_w_lg_w14873w14924w(0) AND wire_niO1010l_dataout; + wire_niO101ll_w_lg_w_lg_w14892w14893w14894w(0) <= wire_niO101ll_w_lg_w14892w14893w(0) AND wire_niO1010O_dataout; + wire_niO101ll_w_lg_w_lg_w14935w14941w14942w(0) <= wire_niO101ll_w_lg_w14935w14941w(0) AND wire_niO1010O_dataout; + wire_niO101ll_w_lg_w_lg_w14935w14936w14937w(0) <= wire_niO101ll_w_lg_w14935w14936w(0) AND wire_niO1010O_w_lg_dataout14923w(0); + wire_niO101ll_w_lg_w_lg_w14883w14884w14885w(0) <= wire_niO101ll_w_lg_w14883w14884w(0) AND wire_niO1010O_dataout; + wire_niO101ll_w_lg_w14928w14929w(0) <= wire_niO101ll_w14928w(0) AND wire_niO1010O_dataout; + wire_niO101ll_w_lg_w14873w14924w(0) <= wire_niO101ll_w14873w(0) AND wire_niO1010O_w_lg_dataout14923w(0); + wire_niO101ll_w_lg_w14873w14874w(0) <= wire_niO101ll_w14873w(0) AND wire_niO1010O_dataout; + wire_niO101ll_w_lg_w15027w15028w(0) <= wire_niO101ll_w15027w(0) AND wire_niO1010O_dataout; + wire_niO101ll_w_lg_w14892w14893w(0) <= wire_niO101ll_w14892w(0) AND wire_niO101ii_dataout; + wire_niO101ll_w_lg_w14935w14941w(0) <= wire_niO101ll_w14935w(0) AND wire_niO101ii_w_lg_dataout14901w(0); + wire_niO101ll_w_lg_w14935w14936w(0) <= wire_niO101ll_w14935w(0) AND wire_niO101ii_dataout; + wire_niO101ll_w_lg_w14883w14884w(0) <= wire_niO101ll_w14883w(0) AND wire_niO101ii_dataout; + wire_niO101ll_w14928w(0) <= wire_niO101ll_w_lg_w_lg_w_lg_dataout14870w14871w14872w(0) AND wire_niO101ii_w_lg_dataout14901w(0); + wire_niO101ll_w14873w(0) <= wire_niO101ll_w_lg_w_lg_w_lg_dataout14870w14871w14872w(0) AND wire_niO101ii_dataout; + wire_niO101ll_w15027w(0) <= wire_niO101ll_w_lg_w_lg_w_lg_dataout14898w14899w14900w(0) AND wire_niO101ii_dataout; + wire_niO101ll_w14892w(0) <= wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14889w14891w(0) AND wire_niO101il_dataout; + wire_niO101ll_w14935w(0) <= wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14881w14933w(0) AND wire_niO101il_w_lg_dataout14934w(0); + wire_niO101ll_w14883w(0) <= wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14881w14882w(0) AND wire_niO101il_dataout; + wire_niO101ll_w_lg_w_lg_w_lg_dataout14870w14871w14872w(0) <= wire_niO101ll_w_lg_w_lg_dataout14870w14871w(0) AND wire_niO101il_dataout; + wire_niO101ll_w_lg_w_lg_w_lg_dataout14898w14899w14900w(0) <= wire_niO101ll_w_lg_w_lg_dataout14898w14899w(0) AND wire_niO101il_dataout; + wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14889w14891w(0) <= wire_niO101ll_w_lg_w_lg_dataout14880w14889w(0) AND wire_niO101iO_w_lg_dataout14890w(0); + wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14881w14933w(0) <= wire_niO101ll_w_lg_w_lg_dataout14880w14881w(0) AND wire_niO101iO_w_lg_dataout14890w(0); + wire_niO101ll_w_lg_w_lg_w_lg_dataout14880w14881w14882w(0) <= wire_niO101ll_w_lg_w_lg_dataout14880w14881w(0) AND wire_niO101iO_dataout; + wire_niO101ll_w_lg_w_lg_dataout14870w14871w(0) <= wire_niO101ll_w_lg_dataout14870w(0) AND wire_niO101iO_dataout; + wire_niO101ll_w_lg_w_lg_dataout14898w14899w(0) <= wire_niO101ll_w_lg_dataout14898w(0) AND wire_niO101iO_dataout; + wire_niO101ll_w_lg_w_lg_dataout14880w14889w(0) <= wire_niO101ll_w_lg_dataout14880w(0) AND wire_niO101li_w_lg_dataout14869w(0); + wire_niO101ll_w_lg_w_lg_dataout14880w14881w(0) <= wire_niO101ll_w_lg_dataout14880w(0) AND wire_niO101li_dataout; + wire_niO101ll_w_lg_dataout14870w(0) <= wire_niO101ll_dataout AND wire_niO101li_w_lg_dataout14869w(0); + wire_niO101ll_w_lg_dataout14898w(0) <= wire_niO101ll_dataout AND wire_niO101li_dataout; + wire_niO101ll_w_lg_dataout14880w(0) <= NOT wire_niO101ll_dataout; + wire_niO101lO_dataout <= niO1ilii WHEN (NOT k_hip(3)) = '1' ELSE rxstatus3(0); + wire_niO101lO_w_lg_dataout15391w(0) <= NOT wire_niO101lO_dataout; + wire_niO101O_dataout <= niiiOOl WHEN niOO0liOi = '1' ELSE wire_niO0lli_dataout; + wire_niO101Oi_dataout <= niO1ilil WHEN (NOT k_hip(3)) = '1' ELSE rxstatus3(1); + wire_niO101Oi_w_lg_dataout15389w(0) <= NOT wire_niO101Oi_dataout; + wire_niO101Ol_dataout <= niO1iliO WHEN (NOT k_hip(3)) = '1' ELSE rxstatus3(2); + wire_niO101Ol_w_lg_w_lg_w_lg_dataout15723w23929w23930w(0) <= wire_niO101Ol_w_lg_w_lg_dataout15723w23929w(0) AND wire_niO101lO_dataout; + wire_niO101Ol_w_lg_w_lg_dataout15393w15394w(0) <= wire_niO101Ol_w_lg_dataout15393w(0) AND wire_niO101lO_dataout; + wire_niO101Ol_w_lg_w_lg_dataout15723w23929w(0) <= wire_niO101Ol_w_lg_dataout15723w(0) AND wire_niO101Oi_dataout; + wire_niO101Ol_w_lg_dataout15390w(0) <= wire_niO101Ol_dataout AND wire_niO101Oi_w_lg_dataout15389w(0); + wire_niO101Ol_w_lg_dataout15393w(0) <= wire_niO101Ol_dataout AND wire_niO101Oi_dataout; + wire_niO101Ol_w_lg_dataout15723w(0) <= NOT wire_niO101Ol_dataout; + wire_niO101OO_dataout <= niO110li WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle3; + wire_niO10i0i_dataout <= niO1iOlO WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(0); + wire_niO10i0i_w_lg_dataout16691w(0) <= NOT wire_niO10i0i_dataout; + wire_niO10i0l_dataout <= niO1iOOi WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(1); + wire_niO10i0l_w_lg_dataout16689w(0) <= NOT wire_niO10i0l_dataout; + wire_niO10i0O_dataout <= niO1iOOl WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(2); + wire_niO10i0O_w_lg_dataout16737w(0) <= NOT wire_niO10i0O_dataout; + wire_niO10i1i_dataout <= niO1iOiO WHEN (NOT k_hip(3)) = '1' ELSE phystatus2; + wire_niO10i1i_w_lg_dataout19794w(0) <= NOT wire_niO10i1i_dataout; + wire_niO10i1l_dataout <= niO1iOli WHEN (NOT k_hip(3)) = '1' ELSE rxvalid2; + wire_niO10i1l_w_lg_dataout27501w(0) <= NOT wire_niO10i1l_dataout; + wire_niO10i1O_dataout <= niO1iOll WHEN (NOT k_hip(3)) = '1' ELSE rxdatak2; + wire_niO10i1O_w_lg_dataout16339w(0) <= NOT wire_niO10i1O_dataout; + wire_niO10ii_dataout <= nii1l0O WHEN niOO0liOi = '1' ELSE wire_niO0lOi_dataout; + wire_niO10iii_dataout <= niO1iOOO WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(3); + wire_niO10iii_w_lg_dataout16715w(0) <= NOT wire_niO10iii_dataout; + wire_niO10iil_dataout <= niO1l11i WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(4); + wire_niO10iil_w_lg_dataout16748w(0) <= NOT wire_niO10iil_dataout; + wire_niO10iiO_dataout <= niO1l11l WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(5); + wire_niO10iiO_w_lg_dataout16704w(0) <= NOT wire_niO10iiO_dataout; + wire_niO10il_dataout <= nii1lii WHEN niOO0liOi = '1' ELSE wire_niO0lOl_dataout; + wire_niO10ili_dataout <= niO1l11O WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(6); + wire_niO10ili_w_lg_dataout16683w(0) <= NOT wire_niO10ili_dataout; + wire_niO10ill_dataout <= niO1l10i WHEN (NOT k_hip(3)) = '1' ELSE rxdata2(7); + wire_niO10ill_w16758w(0) <= wire_niO10ill_w_lg_w_lg_w_lg_w16749w16755w16756w16757w(0) AND wire_niO10i0i_dataout; + wire_niO10ill_w_lg_w_lg_w_lg_w16742w16743w16744w16745w(0) <= wire_niO10ill_w_lg_w_lg_w16742w16743w16744w(0) AND wire_niO10i0i_dataout; + wire_niO10ill_w_lg_w_lg_w_lg_w16749w16755w16756w16757w(0) <= wire_niO10ill_w_lg_w_lg_w16749w16755w16756w(0) AND wire_niO10i0l_w_lg_dataout16689w(0); + wire_niO10ill_w_lg_w_lg_w_lg_w16749w16750w16751w16752w(0) <= wire_niO10ill_w_lg_w_lg_w16749w16750w16751w(0) AND wire_niO10i0l_dataout; + wire_niO10ill_w_lg_w_lg_w16742w16743w16744w(0) <= wire_niO10ill_w_lg_w16742w16743w(0) AND wire_niO10i0l_w_lg_dataout16689w(0); + wire_niO10ill_w_lg_w_lg_w16687w16738w16739w(0) <= wire_niO10ill_w_lg_w16687w16738w(0) AND wire_niO10i0l_dataout; + wire_niO10ill_w_lg_w_lg_w16706w16707w16708w(0) <= wire_niO10ill_w_lg_w16706w16707w(0) AND wire_niO10i0O_dataout; + wire_niO10ill_w_lg_w_lg_w16749w16755w16756w(0) <= wire_niO10ill_w_lg_w16749w16755w(0) AND wire_niO10i0O_dataout; + wire_niO10ill_w_lg_w_lg_w16749w16750w16751w(0) <= wire_niO10ill_w_lg_w16749w16750w(0) AND wire_niO10i0O_w_lg_dataout16737w(0); + wire_niO10ill_w_lg_w_lg_w16697w16698w16699w(0) <= wire_niO10ill_w_lg_w16697w16698w(0) AND wire_niO10i0O_dataout; + wire_niO10ill_w_lg_w16742w16743w(0) <= wire_niO10ill_w16742w(0) AND wire_niO10i0O_dataout; + wire_niO10ill_w_lg_w16687w16738w(0) <= wire_niO10ill_w16687w(0) AND wire_niO10i0O_w_lg_dataout16737w(0); + wire_niO10ill_w_lg_w16687w16688w(0) <= wire_niO10ill_w16687w(0) AND wire_niO10i0O_dataout; + wire_niO10ill_w_lg_w16841w16842w(0) <= wire_niO10ill_w16841w(0) AND wire_niO10i0O_dataout; + wire_niO10ill_w_lg_w16706w16707w(0) <= wire_niO10ill_w16706w(0) AND wire_niO10iii_dataout; + wire_niO10ill_w_lg_w16749w16755w(0) <= wire_niO10ill_w16749w(0) AND wire_niO10iii_w_lg_dataout16715w(0); + wire_niO10ill_w_lg_w16749w16750w(0) <= wire_niO10ill_w16749w(0) AND wire_niO10iii_dataout; + wire_niO10ill_w_lg_w16697w16698w(0) <= wire_niO10ill_w16697w(0) AND wire_niO10iii_dataout; + wire_niO10ill_w16742w(0) <= wire_niO10ill_w_lg_w_lg_w_lg_dataout16684w16685w16686w(0) AND wire_niO10iii_w_lg_dataout16715w(0); + wire_niO10ill_w16687w(0) <= wire_niO10ill_w_lg_w_lg_w_lg_dataout16684w16685w16686w(0) AND wire_niO10iii_dataout; + wire_niO10ill_w16841w(0) <= wire_niO10ill_w_lg_w_lg_w_lg_dataout16712w16713w16714w(0) AND wire_niO10iii_dataout; + wire_niO10ill_w16706w(0) <= wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16703w16705w(0) AND wire_niO10iil_dataout; + wire_niO10ill_w16749w(0) <= wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16695w16747w(0) AND wire_niO10iil_w_lg_dataout16748w(0); + wire_niO10ill_w16697w(0) <= wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16695w16696w(0) AND wire_niO10iil_dataout; + wire_niO10ill_w_lg_w_lg_w_lg_dataout16684w16685w16686w(0) <= wire_niO10ill_w_lg_w_lg_dataout16684w16685w(0) AND wire_niO10iil_dataout; + wire_niO10ill_w_lg_w_lg_w_lg_dataout16712w16713w16714w(0) <= wire_niO10ill_w_lg_w_lg_dataout16712w16713w(0) AND wire_niO10iil_dataout; + wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16703w16705w(0) <= wire_niO10ill_w_lg_w_lg_dataout16694w16703w(0) AND wire_niO10iiO_w_lg_dataout16704w(0); + wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16695w16747w(0) <= wire_niO10ill_w_lg_w_lg_dataout16694w16695w(0) AND wire_niO10iiO_w_lg_dataout16704w(0); + wire_niO10ill_w_lg_w_lg_w_lg_dataout16694w16695w16696w(0) <= wire_niO10ill_w_lg_w_lg_dataout16694w16695w(0) AND wire_niO10iiO_dataout; + wire_niO10ill_w_lg_w_lg_dataout16684w16685w(0) <= wire_niO10ill_w_lg_dataout16684w(0) AND wire_niO10iiO_dataout; + wire_niO10ill_w_lg_w_lg_dataout16712w16713w(0) <= wire_niO10ill_w_lg_dataout16712w(0) AND wire_niO10iiO_dataout; + wire_niO10ill_w_lg_w_lg_dataout16694w16703w(0) <= wire_niO10ill_w_lg_dataout16694w(0) AND wire_niO10ili_w_lg_dataout16683w(0); + wire_niO10ill_w_lg_w_lg_dataout16694w16695w(0) <= wire_niO10ill_w_lg_dataout16694w(0) AND wire_niO10ili_dataout; + wire_niO10ill_w_lg_dataout16684w(0) <= wire_niO10ill_dataout AND wire_niO10ili_w_lg_dataout16683w(0); + wire_niO10ill_w_lg_dataout16712w(0) <= wire_niO10ill_dataout AND wire_niO10ili_dataout; + wire_niO10ill_w_lg_dataout16694w(0) <= NOT wire_niO10ill_dataout; + wire_niO10ilO_dataout <= niO1l10l WHEN (NOT k_hip(3)) = '1' ELSE rxstatus1(0); + wire_niO10ilO_w_lg_dataout17205w(0) <= NOT wire_niO10ilO_dataout; + wire_niO10iO_dataout <= nii1lil WHEN niOO0liOi = '1' ELSE wire_niO0lOO_dataout; + wire_niO10iOi_dataout <= niO1l10O WHEN (NOT k_hip(3)) = '1' ELSE rxstatus1(1); + wire_niO10iOi_w_lg_dataout17203w(0) <= NOT wire_niO10iOi_dataout; + wire_niO10iOl_dataout <= niO1l1ii WHEN (NOT k_hip(3)) = '1' ELSE rxstatus1(2); + wire_niO10iOl_w_lg_w_lg_w_lg_dataout17537w23921w23922w(0) <= wire_niO10iOl_w_lg_w_lg_dataout17537w23921w(0) AND wire_niO10ilO_dataout; + wire_niO10iOl_w_lg_w_lg_dataout17207w17208w(0) <= wire_niO10iOl_w_lg_dataout17207w(0) AND wire_niO10ilO_dataout; + wire_niO10iOl_w_lg_w_lg_dataout17537w23921w(0) <= wire_niO10iOl_w_lg_dataout17537w(0) AND wire_niO10iOi_dataout; + wire_niO10iOl_w_lg_dataout17204w(0) <= wire_niO10iOl_dataout AND wire_niO10iOi_w_lg_dataout17203w(0); + wire_niO10iOl_w_lg_dataout17207w(0) <= wire_niO10iOl_dataout AND wire_niO10iOi_dataout; + wire_niO10iOl_w_lg_dataout17537w(0) <= NOT wire_niO10iOl_dataout; + wire_niO10iOO_dataout <= niO110il WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle1; + wire_niO10l0i_dataout <= niO1l1ll WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(0); + wire_niO10l0i_w_lg_dataout17598w(0) <= NOT wire_niO10l0i_dataout; + wire_niO10l0l_dataout <= niO1l1lO WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(1); + wire_niO10l0l_w_lg_dataout17596w(0) <= NOT wire_niO10l0l_dataout; + wire_niO10l0O_dataout <= niO1l1Oi WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(2); + wire_niO10l0O_w_lg_dataout17644w(0) <= NOT wire_niO10l0O_dataout; + wire_niO10l1i_dataout <= niO1l1il WHEN (NOT k_hip(3)) = '1' ELSE phystatus1; + wire_niO10l1i_w_lg_dataout19790w(0) <= NOT wire_niO10l1i_dataout; + wire_niO10l1l_dataout <= niO1l1iO WHEN (NOT k_hip(3)) = '1' ELSE rxvalid1; + wire_niO10l1l_w_lg_dataout27496w(0) <= NOT wire_niO10l1l_dataout; + wire_niO10l1O_dataout <= niO1l1li WHEN (NOT k_hip(3)) = '1' ELSE rxdatak1; + wire_niO10l1O_w_lg_dataout17246w(0) <= NOT wire_niO10l1O_dataout; + wire_niO10li_dataout <= nii1liO WHEN niOO0liOi = '1' ELSE wire_niO0O1i_dataout; + wire_niO10lii_dataout <= niO1l1Ol WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(3); + wire_niO10lii_w_lg_dataout17622w(0) <= NOT wire_niO10lii_dataout; + wire_niO10lil_dataout <= niO1l1OO WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(4); + wire_niO10lil_w_lg_dataout17655w(0) <= NOT wire_niO10lil_dataout; + wire_niO10liO_dataout <= niO1l01i WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(5); + wire_niO10liO_w_lg_dataout17611w(0) <= NOT wire_niO10liO_dataout; + wire_niO10ll_dataout <= nii1lli WHEN niOO0liOi = '1' ELSE wire_niO0O1l_dataout; + wire_niO10lli_dataout <= niO1l01l WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(6); + wire_niO10lli_w_lg_dataout17590w(0) <= NOT wire_niO10lli_dataout; + wire_niO10lll_dataout <= niO1l01O WHEN (NOT k_hip(3)) = '1' ELSE rxdata1(7); + wire_niO10lll_w17665w(0) <= wire_niO10lll_w_lg_w_lg_w_lg_w17656w17662w17663w17664w(0) AND wire_niO10l0i_dataout; + wire_niO10lll_w_lg_w_lg_w_lg_w17649w17650w17651w17652w(0) <= wire_niO10lll_w_lg_w_lg_w17649w17650w17651w(0) AND wire_niO10l0i_dataout; + wire_niO10lll_w_lg_w_lg_w_lg_w17656w17662w17663w17664w(0) <= wire_niO10lll_w_lg_w_lg_w17656w17662w17663w(0) AND wire_niO10l0l_w_lg_dataout17596w(0); + wire_niO10lll_w_lg_w_lg_w_lg_w17656w17657w17658w17659w(0) <= wire_niO10lll_w_lg_w_lg_w17656w17657w17658w(0) AND wire_niO10l0l_dataout; + wire_niO10lll_w_lg_w_lg_w17649w17650w17651w(0) <= wire_niO10lll_w_lg_w17649w17650w(0) AND wire_niO10l0l_w_lg_dataout17596w(0); + wire_niO10lll_w_lg_w_lg_w17594w17645w17646w(0) <= wire_niO10lll_w_lg_w17594w17645w(0) AND wire_niO10l0l_dataout; + wire_niO10lll_w_lg_w_lg_w17613w17614w17615w(0) <= wire_niO10lll_w_lg_w17613w17614w(0) AND wire_niO10l0O_dataout; + wire_niO10lll_w_lg_w_lg_w17656w17662w17663w(0) <= wire_niO10lll_w_lg_w17656w17662w(0) AND wire_niO10l0O_dataout; + wire_niO10lll_w_lg_w_lg_w17656w17657w17658w(0) <= wire_niO10lll_w_lg_w17656w17657w(0) AND wire_niO10l0O_w_lg_dataout17644w(0); + wire_niO10lll_w_lg_w_lg_w17604w17605w17606w(0) <= wire_niO10lll_w_lg_w17604w17605w(0) AND wire_niO10l0O_dataout; + wire_niO10lll_w_lg_w17649w17650w(0) <= wire_niO10lll_w17649w(0) AND wire_niO10l0O_dataout; + wire_niO10lll_w_lg_w17594w17645w(0) <= wire_niO10lll_w17594w(0) AND wire_niO10l0O_w_lg_dataout17644w(0); + wire_niO10lll_w_lg_w17594w17595w(0) <= wire_niO10lll_w17594w(0) AND wire_niO10l0O_dataout; + wire_niO10lll_w_lg_w17748w17749w(0) <= wire_niO10lll_w17748w(0) AND wire_niO10l0O_dataout; + wire_niO10lll_w_lg_w17613w17614w(0) <= wire_niO10lll_w17613w(0) AND wire_niO10lii_dataout; + wire_niO10lll_w_lg_w17656w17662w(0) <= wire_niO10lll_w17656w(0) AND wire_niO10lii_w_lg_dataout17622w(0); + wire_niO10lll_w_lg_w17656w17657w(0) <= wire_niO10lll_w17656w(0) AND wire_niO10lii_dataout; + wire_niO10lll_w_lg_w17604w17605w(0) <= wire_niO10lll_w17604w(0) AND wire_niO10lii_dataout; + wire_niO10lll_w17649w(0) <= wire_niO10lll_w_lg_w_lg_w_lg_dataout17591w17592w17593w(0) AND wire_niO10lii_w_lg_dataout17622w(0); + wire_niO10lll_w17594w(0) <= wire_niO10lll_w_lg_w_lg_w_lg_dataout17591w17592w17593w(0) AND wire_niO10lii_dataout; + wire_niO10lll_w17748w(0) <= wire_niO10lll_w_lg_w_lg_w_lg_dataout17619w17620w17621w(0) AND wire_niO10lii_dataout; + wire_niO10lll_w17613w(0) <= wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17610w17612w(0) AND wire_niO10lil_dataout; + wire_niO10lll_w17656w(0) <= wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17602w17654w(0) AND wire_niO10lil_w_lg_dataout17655w(0); + wire_niO10lll_w17604w(0) <= wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17602w17603w(0) AND wire_niO10lil_dataout; + wire_niO10lll_w_lg_w_lg_w_lg_dataout17591w17592w17593w(0) <= wire_niO10lll_w_lg_w_lg_dataout17591w17592w(0) AND wire_niO10lil_dataout; + wire_niO10lll_w_lg_w_lg_w_lg_dataout17619w17620w17621w(0) <= wire_niO10lll_w_lg_w_lg_dataout17619w17620w(0) AND wire_niO10lil_dataout; + wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17610w17612w(0) <= wire_niO10lll_w_lg_w_lg_dataout17601w17610w(0) AND wire_niO10liO_w_lg_dataout17611w(0); + wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17602w17654w(0) <= wire_niO10lll_w_lg_w_lg_dataout17601w17602w(0) AND wire_niO10liO_w_lg_dataout17611w(0); + wire_niO10lll_w_lg_w_lg_w_lg_dataout17601w17602w17603w(0) <= wire_niO10lll_w_lg_w_lg_dataout17601w17602w(0) AND wire_niO10liO_dataout; + wire_niO10lll_w_lg_w_lg_dataout17591w17592w(0) <= wire_niO10lll_w_lg_dataout17591w(0) AND wire_niO10liO_dataout; + wire_niO10lll_w_lg_w_lg_dataout17619w17620w(0) <= wire_niO10lll_w_lg_dataout17619w(0) AND wire_niO10liO_dataout; + wire_niO10lll_w_lg_w_lg_dataout17601w17610w(0) <= wire_niO10lll_w_lg_dataout17601w(0) AND wire_niO10lli_w_lg_dataout17590w(0); + wire_niO10lll_w_lg_w_lg_dataout17601w17602w(0) <= wire_niO10lll_w_lg_dataout17601w(0) AND wire_niO10lli_dataout; + wire_niO10lll_w_lg_dataout17591w(0) <= wire_niO10lll_dataout AND wire_niO10lli_w_lg_dataout17590w(0); + wire_niO10lll_w_lg_dataout17619w(0) <= wire_niO10lll_dataout AND wire_niO10lli_dataout; + wire_niO10lll_w_lg_dataout17601w(0) <= NOT wire_niO10lll_dataout; + wire_niO10llO_dataout <= niO1l00i WHEN (NOT k_hip(3)) = '1' ELSE rxstatus0(0); + wire_niO10llO_w_lg_dataout18112w(0) <= NOT wire_niO10llO_dataout; + wire_niO10lO_dataout <= nii1lll WHEN niOO0liOi = '1' ELSE wire_niO0O1O_dataout; + wire_niO10lOi_dataout <= niO1l00l WHEN (NOT k_hip(3)) = '1' ELSE rxstatus0(1); + wire_niO10lOi_w_lg_dataout18110w(0) <= NOT wire_niO10lOi_dataout; + wire_niO10lOl_dataout <= niO1l00O WHEN (NOT k_hip(3)) = '1' ELSE rxstatus0(2); + wire_niO10lOl_w_lg_w_lg_w_lg_dataout18444w23917w23918w(0) <= wire_niO10lOl_w_lg_w_lg_dataout18444w23917w(0) AND wire_niO10llO_dataout; + wire_niO10lOl_w_lg_w_lg_dataout18114w18115w(0) <= wire_niO10lOl_w_lg_dataout18114w(0) AND wire_niO10llO_dataout; + wire_niO10lOl_w_lg_w_lg_dataout18444w23917w(0) <= wire_niO10lOl_w_lg_dataout18444w(0) AND wire_niO10lOi_dataout; + wire_niO10lOl_w_lg_dataout18111w(0) <= wire_niO10lOl_dataout AND wire_niO10lOi_w_lg_dataout18110w(0); + wire_niO10lOl_w_lg_dataout18114w(0) <= wire_niO10lOl_dataout AND wire_niO10lOi_dataout; + wire_niO10lOl_w_lg_dataout18444w(0) <= NOT wire_niO10lOl_dataout; + wire_niO10lOO_dataout <= niO110ii WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle0; + wire_niO10O0i_dataout <= niO1l0li WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(0); + wire_niO10O0i_w_lg_dataout18505w(0) <= NOT wire_niO10O0i_dataout; + wire_niO10O0l_dataout <= niO1l0ll WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(1); + wire_niO10O0l_w_lg_dataout18503w(0) <= NOT wire_niO10O0l_dataout; + wire_niO10O0O_dataout <= niO1l0lO WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(2); + wire_niO10O0O_w_lg_dataout18551w(0) <= NOT wire_niO10O0O_dataout; + wire_niO10O1i_dataout <= niO1l0ii WHEN (NOT k_hip(3)) = '1' ELSE phystatus0; + wire_niO10O1i_w_lg_dataout19787w(0) <= NOT wire_niO10O1i_dataout; + wire_niO10O1l_dataout <= niO1l0il WHEN (NOT k_hip(3)) = '1' ELSE rxvalid0; + wire_niO10O1l_w_lg_dataout27492w(0) <= NOT wire_niO10O1l_dataout; + wire_niO10O1O_dataout <= niO1l0iO WHEN (NOT k_hip(3)) = '1' ELSE rxdatak0; + wire_niO10O1O_w_lg_dataout18153w(0) <= NOT wire_niO10O1O_dataout; + wire_niO10Oi_dataout <= nii1llO WHEN niOO0liOi = '1' ELSE wire_niO0O0i_dataout; + wire_niO10Oii_dataout <= niO1l0Oi WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(3); + wire_niO10Oii_w_lg_dataout18529w(0) <= NOT wire_niO10Oii_dataout; + wire_niO10Oil_dataout <= niO1l0Ol WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(4); + wire_niO10Oil_w_lg_dataout18562w(0) <= NOT wire_niO10Oil_dataout; + wire_niO10OiO_dataout <= niO1l0OO WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(5); + wire_niO10OiO_w_lg_dataout18518w(0) <= NOT wire_niO10OiO_dataout; + wire_niO10Ol_dataout <= nii1lOi WHEN niOO0liOi = '1' ELSE wire_niO0O0l_dataout; + wire_niO10Oli_dataout <= niO1li1i WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(6); + wire_niO10Oli_w_lg_dataout18497w(0) <= NOT wire_niO10Oli_dataout; + wire_niO10Oll_dataout <= niO1li1l WHEN (NOT k_hip(3)) = '1' ELSE rxdata0(7); + wire_niO10Oll_w18572w(0) <= wire_niO10Oll_w_lg_w_lg_w_lg_w18563w18569w18570w18571w(0) AND wire_niO10O0i_dataout; + wire_niO10Oll_w_lg_w_lg_w_lg_w18556w18557w18558w18559w(0) <= wire_niO10Oll_w_lg_w_lg_w18556w18557w18558w(0) AND wire_niO10O0i_dataout; + wire_niO10Oll_w_lg_w_lg_w_lg_w18563w18569w18570w18571w(0) <= wire_niO10Oll_w_lg_w_lg_w18563w18569w18570w(0) AND wire_niO10O0l_w_lg_dataout18503w(0); + wire_niO10Oll_w_lg_w_lg_w_lg_w18563w18564w18565w18566w(0) <= wire_niO10Oll_w_lg_w_lg_w18563w18564w18565w(0) AND wire_niO10O0l_dataout; + wire_niO10Oll_w_lg_w_lg_w18556w18557w18558w(0) <= wire_niO10Oll_w_lg_w18556w18557w(0) AND wire_niO10O0l_w_lg_dataout18503w(0); + wire_niO10Oll_w_lg_w_lg_w18501w18552w18553w(0) <= wire_niO10Oll_w_lg_w18501w18552w(0) AND wire_niO10O0l_dataout; + wire_niO10Oll_w_lg_w_lg_w18520w18521w18522w(0) <= wire_niO10Oll_w_lg_w18520w18521w(0) AND wire_niO10O0O_dataout; + wire_niO10Oll_w_lg_w_lg_w18563w18569w18570w(0) <= wire_niO10Oll_w_lg_w18563w18569w(0) AND wire_niO10O0O_dataout; + wire_niO10Oll_w_lg_w_lg_w18563w18564w18565w(0) <= wire_niO10Oll_w_lg_w18563w18564w(0) AND wire_niO10O0O_w_lg_dataout18551w(0); + wire_niO10Oll_w_lg_w_lg_w18511w18512w18513w(0) <= wire_niO10Oll_w_lg_w18511w18512w(0) AND wire_niO10O0O_dataout; + wire_niO10Oll_w_lg_w18556w18557w(0) <= wire_niO10Oll_w18556w(0) AND wire_niO10O0O_dataout; + wire_niO10Oll_w_lg_w18501w18552w(0) <= wire_niO10Oll_w18501w(0) AND wire_niO10O0O_w_lg_dataout18551w(0); + wire_niO10Oll_w_lg_w18501w18502w(0) <= wire_niO10Oll_w18501w(0) AND wire_niO10O0O_dataout; + wire_niO10Oll_w_lg_w18655w18656w(0) <= wire_niO10Oll_w18655w(0) AND wire_niO10O0O_dataout; + wire_niO10Oll_w_lg_w18520w18521w(0) <= wire_niO10Oll_w18520w(0) AND wire_niO10Oii_dataout; + wire_niO10Oll_w_lg_w18563w18569w(0) <= wire_niO10Oll_w18563w(0) AND wire_niO10Oii_w_lg_dataout18529w(0); + wire_niO10Oll_w_lg_w18563w18564w(0) <= wire_niO10Oll_w18563w(0) AND wire_niO10Oii_dataout; + wire_niO10Oll_w_lg_w18511w18512w(0) <= wire_niO10Oll_w18511w(0) AND wire_niO10Oii_dataout; + wire_niO10Oll_w18556w(0) <= wire_niO10Oll_w_lg_w_lg_w_lg_dataout18498w18499w18500w(0) AND wire_niO10Oii_w_lg_dataout18529w(0); + wire_niO10Oll_w18501w(0) <= wire_niO10Oll_w_lg_w_lg_w_lg_dataout18498w18499w18500w(0) AND wire_niO10Oii_dataout; + wire_niO10Oll_w18655w(0) <= wire_niO10Oll_w_lg_w_lg_w_lg_dataout18526w18527w18528w(0) AND wire_niO10Oii_dataout; + wire_niO10Oll_w18520w(0) <= wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18517w18519w(0) AND wire_niO10Oil_dataout; + wire_niO10Oll_w18563w(0) <= wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18509w18561w(0) AND wire_niO10Oil_w_lg_dataout18562w(0); + wire_niO10Oll_w18511w(0) <= wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18509w18510w(0) AND wire_niO10Oil_dataout; + wire_niO10Oll_w_lg_w_lg_w_lg_dataout18498w18499w18500w(0) <= wire_niO10Oll_w_lg_w_lg_dataout18498w18499w(0) AND wire_niO10Oil_dataout; + wire_niO10Oll_w_lg_w_lg_w_lg_dataout18526w18527w18528w(0) <= wire_niO10Oll_w_lg_w_lg_dataout18526w18527w(0) AND wire_niO10Oil_dataout; + wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18517w18519w(0) <= wire_niO10Oll_w_lg_w_lg_dataout18508w18517w(0) AND wire_niO10OiO_w_lg_dataout18518w(0); + wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18509w18561w(0) <= wire_niO10Oll_w_lg_w_lg_dataout18508w18509w(0) AND wire_niO10OiO_w_lg_dataout18518w(0); + wire_niO10Oll_w_lg_w_lg_w_lg_dataout18508w18509w18510w(0) <= wire_niO10Oll_w_lg_w_lg_dataout18508w18509w(0) AND wire_niO10OiO_dataout; + wire_niO10Oll_w_lg_w_lg_dataout18498w18499w(0) <= wire_niO10Oll_w_lg_dataout18498w(0) AND wire_niO10OiO_dataout; + wire_niO10Oll_w_lg_w_lg_dataout18526w18527w(0) <= wire_niO10Oll_w_lg_dataout18526w(0) AND wire_niO10OiO_dataout; + wire_niO10Oll_w_lg_w_lg_dataout18508w18517w(0) <= wire_niO10Oll_w_lg_dataout18508w(0) AND wire_niO10Oli_w_lg_dataout18497w(0); + wire_niO10Oll_w_lg_w_lg_dataout18508w18509w(0) <= wire_niO10Oll_w_lg_dataout18508w(0) AND wire_niO10Oli_dataout; + wire_niO10Oll_w_lg_dataout18498w(0) <= wire_niO10Oll_dataout AND wire_niO10Oli_w_lg_dataout18497w(0); + wire_niO10Oll_w_lg_dataout18526w(0) <= wire_niO10Oll_dataout AND wire_niO10Oli_dataout; + wire_niO10Oll_w_lg_dataout18508w(0) <= NOT wire_niO10Oll_dataout; + wire_niO10OO_dataout <= nii1lOl WHEN niOO0liOi = '1' ELSE wire_niO0O0O_dataout; + wire_niO1100i_dataout <= nli11O1iO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1illll; + wire_niO1100l_dataout <= nli11O1il WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1illlO; + wire_niO1100O_dataout <= nli11li1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1illOi; + wire_niO1101i_dataout <= nli11O1li WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1illil; + wire_niO1101l_dataout <= nli11O1ll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1illiO; + wire_niO1101O_dataout <= nli11O1lO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1illli; + wire_niO110i_dataout <= niiilOO WHEN niOO0liOi = '1' ELSE wire_niO0ill_dataout; + wire_niO110l_dataout <= niiiO1i WHEN niOO0liOi = '1' ELSE wire_niO0ilO_dataout; + wire_niO110lO_dataout <= niO1OOlO WHEN (NOT k_hip(3)) = '1' ELSE rxstatus7(0); + wire_niO110lO_w_lg_dataout11759w(0) <= NOT wire_niO110lO_dataout; + wire_niO110O_dataout <= niiiO1l WHEN niOO0liOi = '1' ELSE wire_niO0iOi_dataout; + wire_niO110Oi_dataout <= niO10OlO WHEN (NOT k_hip(3)) = '1' ELSE rxstatus7(1); + wire_niO110Oi_w_lg_dataout11757w(0) <= NOT wire_niO110Oi_dataout; + wire_niO110Ol_dataout <= niO10OOi WHEN (NOT k_hip(3)) = '1' ELSE rxstatus7(2); + wire_niO110Ol_w_lg_w_lg_w_lg_dataout12091w23945w23946w(0) <= wire_niO110Ol_w_lg_w_lg_dataout12091w23945w(0) AND wire_niO110lO_dataout; + wire_niO110Ol_w_lg_w_lg_dataout11761w11762w(0) <= wire_niO110Ol_w_lg_dataout11761w(0) AND wire_niO110lO_dataout; + wire_niO110Ol_w_lg_w_lg_dataout12091w23945w(0) <= wire_niO110Ol_w_lg_dataout12091w(0) AND wire_niO110Oi_dataout; + wire_niO110Ol_w_lg_dataout11758w(0) <= wire_niO110Ol_dataout AND wire_niO110Oi_w_lg_dataout11757w(0); + wire_niO110Ol_w_lg_dataout11761w(0) <= wire_niO110Ol_dataout AND wire_niO110Oi_dataout; + wire_niO110Ol_w_lg_dataout12091w(0) <= NOT wire_niO110Ol_dataout; + wire_niO110OO_dataout <= niO1li0i WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle7; + wire_niO1110i_dataout <= nl10li0l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_niO1110i_w_lg_dataout42248w(0) <= wire_niO1110i_dataout AND wire_nl1000i_w_lg_nlillii0i42247w(0); + wire_niO1110i_w_lg_dataout42873w(0) <= NOT wire_niO1110i_dataout; + wire_niO1110l_dataout <= nlilOO0iO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_niO1110l_w_lg_dataout44125w(0) <= NOT wire_niO1110l_dataout; + wire_niO1110O_dataout <= nliiill0O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl10l1ll; + wire_niO1110O_w_lg_dataout36183w(0) <= wire_niO1110O_dataout AND nlli1Oi0i; + wire_niO1111i_dataout <= nl10li1l AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_niO1111i_w_lg_dataout42861w(0) <= NOT wire_niO1111i_dataout; + wire_niO1111l_dataout <= nl10li1O AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_niO1111l_w_lg_dataout42865w(0) <= NOT wire_niO1111l_dataout; + wire_niO1111O_dataout <= nl10li0i AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_niO1111O_w_lg_dataout42869w(0) <= NOT wire_niO1111O_dataout; + wire_niO111i_dataout <= niiillO WHEN niOO0liOi = '1' ELSE wire_niO0iil_dataout; + wire_niO111ii_dataout <= nli1il11i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl10l01l; + wire_niO111ii_w_lg_dataout8980w(0) <= NOT wire_niO111ii_dataout; + wire_niO111il_dataout <= nli1il10l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl10l1Ol; + wire_niO111il_w_lg_dataout9224w(0) <= NOT wire_niO111il_dataout; + wire_niO111iO_dataout <= wire_nli11O11i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1iO1lO; + wire_niO111l_dataout <= niiilOi WHEN niOO0liOi = '1' ELSE wire_niO0iiO_dataout; + wire_niO111li_dataout <= wire_nli11O11l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ill1l; + wire_niO111ll_dataout <= wire_nli11O11O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ill1O; + wire_niO111lO_dataout <= wire_nli11O10i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ill0i; + wire_niO111O_dataout <= niiilOl WHEN niOO0liOi = '1' ELSE wire_niO0ili_dataout; + wire_niO111Oi_dataout <= nli11O1Oi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ill0l; + wire_niO111Ol_dataout <= nli11O0ii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1ill0O; + wire_niO111OO_dataout <= wire_nli11O10O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl1illii; + wire_niO11i0i_dataout <= niO1i11l WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(0); + wire_niO11i0i_w_lg_dataout12155w(0) <= NOT wire_niO11i0i_dataout; + wire_niO11i0l_dataout <= niO1i11O WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(1); + wire_niO11i0l_w_lg_dataout12153w(0) <= NOT wire_niO11i0l_dataout; + wire_niO11i0O_dataout <= niO1i10i WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(2); + wire_niO11i0O_w_lg_dataout12201w(0) <= NOT wire_niO11i0O_dataout; + wire_niO11i1i_dataout <= niO10OOl WHEN (NOT k_hip(3)) = '1' ELSE phystatus7; + wire_niO11i1i_w_lg_dataout19814w(0) <= NOT wire_niO11i1i_dataout; + wire_niO11i1l_dataout <= niO10OOO WHEN (NOT k_hip(3)) = '1' ELSE rxvalid7; + wire_niO11i1l_w_lg_dataout27526w(0) <= NOT wire_niO11i1l_dataout; + wire_niO11i1O_dataout <= niO1i11i WHEN (NOT k_hip(3)) = '1' ELSE rxdatak7; + wire_niO11i1O_w_lg_dataout11800w(0) <= NOT wire_niO11i1O_dataout; + wire_niO11ii_dataout <= niiiO1O WHEN niOO0liOi = '1' ELSE wire_niO0iOl_dataout; + wire_niO11iii_dataout <= niO1i10l WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(3); + wire_niO11iii_w_lg_dataout12179w(0) <= NOT wire_niO11iii_dataout; + wire_niO11iil_dataout <= niO1i10O WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(4); + wire_niO11iil_w_lg_dataout12212w(0) <= NOT wire_niO11iil_dataout; + wire_niO11iiO_dataout <= niO1i1ii WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(5); + wire_niO11iiO_w_lg_dataout12168w(0) <= NOT wire_niO11iiO_dataout; + wire_niO11il_dataout <= niiiO0i WHEN niOO0liOi = '1' ELSE wire_niO0iOO_dataout; + wire_niO11ili_dataout <= niO1i1il WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(6); + wire_niO11ili_w_lg_dataout12147w(0) <= NOT wire_niO11ili_dataout; + wire_niO11ill_dataout <= niO1i1iO WHEN (NOT k_hip(3)) = '1' ELSE rxdata7(7); + wire_niO11ill_w12222w(0) <= wire_niO11ill_w_lg_w_lg_w_lg_w12213w12219w12220w12221w(0) AND wire_niO11i0i_dataout; + wire_niO11ill_w_lg_w_lg_w_lg_w12206w12207w12208w12209w(0) <= wire_niO11ill_w_lg_w_lg_w12206w12207w12208w(0) AND wire_niO11i0i_dataout; + wire_niO11ill_w_lg_w_lg_w_lg_w12213w12219w12220w12221w(0) <= wire_niO11ill_w_lg_w_lg_w12213w12219w12220w(0) AND wire_niO11i0l_w_lg_dataout12153w(0); + wire_niO11ill_w_lg_w_lg_w_lg_w12213w12214w12215w12216w(0) <= wire_niO11ill_w_lg_w_lg_w12213w12214w12215w(0) AND wire_niO11i0l_dataout; + wire_niO11ill_w_lg_w_lg_w12206w12207w12208w(0) <= wire_niO11ill_w_lg_w12206w12207w(0) AND wire_niO11i0l_w_lg_dataout12153w(0); + wire_niO11ill_w_lg_w_lg_w12151w12202w12203w(0) <= wire_niO11ill_w_lg_w12151w12202w(0) AND wire_niO11i0l_dataout; + wire_niO11ill_w_lg_w_lg_w12170w12171w12172w(0) <= wire_niO11ill_w_lg_w12170w12171w(0) AND wire_niO11i0O_dataout; + wire_niO11ill_w_lg_w_lg_w12213w12219w12220w(0) <= wire_niO11ill_w_lg_w12213w12219w(0) AND wire_niO11i0O_dataout; + wire_niO11ill_w_lg_w_lg_w12213w12214w12215w(0) <= wire_niO11ill_w_lg_w12213w12214w(0) AND wire_niO11i0O_w_lg_dataout12201w(0); + wire_niO11ill_w_lg_w_lg_w12161w12162w12163w(0) <= wire_niO11ill_w_lg_w12161w12162w(0) AND wire_niO11i0O_dataout; + wire_niO11ill_w_lg_w12206w12207w(0) <= wire_niO11ill_w12206w(0) AND wire_niO11i0O_dataout; + wire_niO11ill_w_lg_w12151w12202w(0) <= wire_niO11ill_w12151w(0) AND wire_niO11i0O_w_lg_dataout12201w(0); + wire_niO11ill_w_lg_w12151w12152w(0) <= wire_niO11ill_w12151w(0) AND wire_niO11i0O_dataout; + wire_niO11ill_w_lg_w12305w12306w(0) <= wire_niO11ill_w12305w(0) AND wire_niO11i0O_dataout; + wire_niO11ill_w_lg_w12170w12171w(0) <= wire_niO11ill_w12170w(0) AND wire_niO11iii_dataout; + wire_niO11ill_w_lg_w12213w12219w(0) <= wire_niO11ill_w12213w(0) AND wire_niO11iii_w_lg_dataout12179w(0); + wire_niO11ill_w_lg_w12213w12214w(0) <= wire_niO11ill_w12213w(0) AND wire_niO11iii_dataout; + wire_niO11ill_w_lg_w12161w12162w(0) <= wire_niO11ill_w12161w(0) AND wire_niO11iii_dataout; + wire_niO11ill_w12206w(0) <= wire_niO11ill_w_lg_w_lg_w_lg_dataout12148w12149w12150w(0) AND wire_niO11iii_w_lg_dataout12179w(0); + wire_niO11ill_w12151w(0) <= wire_niO11ill_w_lg_w_lg_w_lg_dataout12148w12149w12150w(0) AND wire_niO11iii_dataout; + wire_niO11ill_w12305w(0) <= wire_niO11ill_w_lg_w_lg_w_lg_dataout12176w12177w12178w(0) AND wire_niO11iii_dataout; + wire_niO11ill_w12170w(0) <= wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12167w12169w(0) AND wire_niO11iil_dataout; + wire_niO11ill_w12213w(0) <= wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12159w12211w(0) AND wire_niO11iil_w_lg_dataout12212w(0); + wire_niO11ill_w12161w(0) <= wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12159w12160w(0) AND wire_niO11iil_dataout; + wire_niO11ill_w_lg_w_lg_w_lg_dataout12148w12149w12150w(0) <= wire_niO11ill_w_lg_w_lg_dataout12148w12149w(0) AND wire_niO11iil_dataout; + wire_niO11ill_w_lg_w_lg_w_lg_dataout12176w12177w12178w(0) <= wire_niO11ill_w_lg_w_lg_dataout12176w12177w(0) AND wire_niO11iil_dataout; + wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12167w12169w(0) <= wire_niO11ill_w_lg_w_lg_dataout12158w12167w(0) AND wire_niO11iiO_w_lg_dataout12168w(0); + wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12159w12211w(0) <= wire_niO11ill_w_lg_w_lg_dataout12158w12159w(0) AND wire_niO11iiO_w_lg_dataout12168w(0); + wire_niO11ill_w_lg_w_lg_w_lg_dataout12158w12159w12160w(0) <= wire_niO11ill_w_lg_w_lg_dataout12158w12159w(0) AND wire_niO11iiO_dataout; + wire_niO11ill_w_lg_w_lg_dataout12148w12149w(0) <= wire_niO11ill_w_lg_dataout12148w(0) AND wire_niO11iiO_dataout; + wire_niO11ill_w_lg_w_lg_dataout12176w12177w(0) <= wire_niO11ill_w_lg_dataout12176w(0) AND wire_niO11iiO_dataout; + wire_niO11ill_w_lg_w_lg_dataout12158w12167w(0) <= wire_niO11ill_w_lg_dataout12158w(0) AND wire_niO11ili_w_lg_dataout12147w(0); + wire_niO11ill_w_lg_w_lg_dataout12158w12159w(0) <= wire_niO11ill_w_lg_dataout12158w(0) AND wire_niO11ili_dataout; + wire_niO11ill_w_lg_dataout12148w(0) <= wire_niO11ill_dataout AND wire_niO11ili_w_lg_dataout12147w(0); + wire_niO11ill_w_lg_dataout12176w(0) <= wire_niO11ill_dataout AND wire_niO11ili_dataout; + wire_niO11ill_w_lg_dataout12158w(0) <= NOT wire_niO11ill_dataout; + wire_niO11ilO_dataout <= niO1i1li WHEN (NOT k_hip(3)) = '1' ELSE rxstatus6(0); + wire_niO11ilO_w_lg_dataout12670w(0) <= NOT wire_niO11ilO_dataout; + wire_niO11iO_dataout <= niiiO0l WHEN niOO0liOi = '1' ELSE wire_niO0l1i_dataout; + wire_niO11iOi_dataout <= niO1i1ll WHEN (NOT k_hip(3)) = '1' ELSE rxstatus6(1); + wire_niO11iOi_w_lg_dataout12668w(0) <= NOT wire_niO11iOi_dataout; + wire_niO11iOl_dataout <= niO1i1lO WHEN (NOT k_hip(3)) = '1' ELSE rxstatus6(2); + wire_niO11iOl_w_lg_w_lg_w_lg_dataout13002w23941w23942w(0) <= wire_niO11iOl_w_lg_w_lg_dataout13002w23941w(0) AND wire_niO11ilO_dataout; + wire_niO11iOl_w_lg_w_lg_dataout12672w12673w(0) <= wire_niO11iOl_w_lg_dataout12672w(0) AND wire_niO11ilO_dataout; + wire_niO11iOl_w_lg_w_lg_dataout13002w23941w(0) <= wire_niO11iOl_w_lg_dataout13002w(0) AND wire_niO11iOi_dataout; + wire_niO11iOl_w_lg_dataout12669w(0) <= wire_niO11iOl_dataout AND wire_niO11iOi_w_lg_dataout12668w(0); + wire_niO11iOl_w_lg_dataout12672w(0) <= wire_niO11iOl_dataout AND wire_niO11iOi_dataout; + wire_niO11iOl_w_lg_dataout13002w(0) <= NOT wire_niO11iOl_dataout; + wire_niO11iOO_dataout <= niO1li1O WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle6; + wire_niO11l0i_dataout <= niO1i01i WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(0); + wire_niO11l0i_w_lg_dataout13063w(0) <= NOT wire_niO11l0i_dataout; + wire_niO11l0l_dataout <= niO1i01l WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(1); + wire_niO11l0l_w_lg_dataout13061w(0) <= NOT wire_niO11l0l_dataout; + wire_niO11l0O_dataout <= niO1i01O WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(2); + wire_niO11l0O_w_lg_dataout13109w(0) <= NOT wire_niO11l0O_dataout; + wire_niO11l1i_dataout <= niO1i1Oi WHEN (NOT k_hip(3)) = '1' ELSE phystatus6; + wire_niO11l1i_w_lg_dataout19810w(0) <= NOT wire_niO11l1i_dataout; + wire_niO11l1l_dataout <= niO1i1Ol WHEN (NOT k_hip(3)) = '1' ELSE rxvalid6; + wire_niO11l1l_w_lg_dataout27521w(0) <= NOT wire_niO11l1l_dataout; + wire_niO11l1O_dataout <= niO1i1OO WHEN (NOT k_hip(3)) = '1' ELSE rxdatak6; + wire_niO11l1O_w_lg_dataout12711w(0) <= NOT wire_niO11l1O_dataout; + wire_niO11li_dataout <= niiiO0O WHEN niOO0liOi = '1' ELSE wire_niO0l1l_dataout; + wire_niO11lii_dataout <= niO1i00i WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(3); + wire_niO11lii_w_lg_dataout13087w(0) <= NOT wire_niO11lii_dataout; + wire_niO11lil_dataout <= niO1i00l WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(4); + wire_niO11lil_w_lg_dataout13120w(0) <= NOT wire_niO11lil_dataout; + wire_niO11liO_dataout <= niO1i00O WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(5); + wire_niO11liO_w_lg_dataout13076w(0) <= NOT wire_niO11liO_dataout; + wire_niO11ll_dataout <= niiiOii WHEN niOO0liOi = '1' ELSE wire_niO0l1O_dataout; + wire_niO11lli_dataout <= niO1i0ii WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(6); + wire_niO11lli_w_lg_dataout13055w(0) <= NOT wire_niO11lli_dataout; + wire_niO11lll_dataout <= niO1i0il WHEN (NOT k_hip(3)) = '1' ELSE rxdata6(7); + wire_niO11lll_w13130w(0) <= wire_niO11lll_w_lg_w_lg_w_lg_w13121w13127w13128w13129w(0) AND wire_niO11l0i_dataout; + wire_niO11lll_w_lg_w_lg_w_lg_w13114w13115w13116w13117w(0) <= wire_niO11lll_w_lg_w_lg_w13114w13115w13116w(0) AND wire_niO11l0i_dataout; + wire_niO11lll_w_lg_w_lg_w_lg_w13121w13127w13128w13129w(0) <= wire_niO11lll_w_lg_w_lg_w13121w13127w13128w(0) AND wire_niO11l0l_w_lg_dataout13061w(0); + wire_niO11lll_w_lg_w_lg_w_lg_w13121w13122w13123w13124w(0) <= wire_niO11lll_w_lg_w_lg_w13121w13122w13123w(0) AND wire_niO11l0l_dataout; + wire_niO11lll_w_lg_w_lg_w13114w13115w13116w(0) <= wire_niO11lll_w_lg_w13114w13115w(0) AND wire_niO11l0l_w_lg_dataout13061w(0); + wire_niO11lll_w_lg_w_lg_w13059w13110w13111w(0) <= wire_niO11lll_w_lg_w13059w13110w(0) AND wire_niO11l0l_dataout; + wire_niO11lll_w_lg_w_lg_w13078w13079w13080w(0) <= wire_niO11lll_w_lg_w13078w13079w(0) AND wire_niO11l0O_dataout; + wire_niO11lll_w_lg_w_lg_w13121w13127w13128w(0) <= wire_niO11lll_w_lg_w13121w13127w(0) AND wire_niO11l0O_dataout; + wire_niO11lll_w_lg_w_lg_w13121w13122w13123w(0) <= wire_niO11lll_w_lg_w13121w13122w(0) AND wire_niO11l0O_w_lg_dataout13109w(0); + wire_niO11lll_w_lg_w_lg_w13069w13070w13071w(0) <= wire_niO11lll_w_lg_w13069w13070w(0) AND wire_niO11l0O_dataout; + wire_niO11lll_w_lg_w13114w13115w(0) <= wire_niO11lll_w13114w(0) AND wire_niO11l0O_dataout; + wire_niO11lll_w_lg_w13059w13110w(0) <= wire_niO11lll_w13059w(0) AND wire_niO11l0O_w_lg_dataout13109w(0); + wire_niO11lll_w_lg_w13059w13060w(0) <= wire_niO11lll_w13059w(0) AND wire_niO11l0O_dataout; + wire_niO11lll_w_lg_w13213w13214w(0) <= wire_niO11lll_w13213w(0) AND wire_niO11l0O_dataout; + wire_niO11lll_w_lg_w13078w13079w(0) <= wire_niO11lll_w13078w(0) AND wire_niO11lii_dataout; + wire_niO11lll_w_lg_w13121w13127w(0) <= wire_niO11lll_w13121w(0) AND wire_niO11lii_w_lg_dataout13087w(0); + wire_niO11lll_w_lg_w13121w13122w(0) <= wire_niO11lll_w13121w(0) AND wire_niO11lii_dataout; + wire_niO11lll_w_lg_w13069w13070w(0) <= wire_niO11lll_w13069w(0) AND wire_niO11lii_dataout; + wire_niO11lll_w13114w(0) <= wire_niO11lll_w_lg_w_lg_w_lg_dataout13056w13057w13058w(0) AND wire_niO11lii_w_lg_dataout13087w(0); + wire_niO11lll_w13059w(0) <= wire_niO11lll_w_lg_w_lg_w_lg_dataout13056w13057w13058w(0) AND wire_niO11lii_dataout; + wire_niO11lll_w13213w(0) <= wire_niO11lll_w_lg_w_lg_w_lg_dataout13084w13085w13086w(0) AND wire_niO11lii_dataout; + wire_niO11lll_w13078w(0) <= wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13075w13077w(0) AND wire_niO11lil_dataout; + wire_niO11lll_w13121w(0) <= wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13067w13119w(0) AND wire_niO11lil_w_lg_dataout13120w(0); + wire_niO11lll_w13069w(0) <= wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13067w13068w(0) AND wire_niO11lil_dataout; + wire_niO11lll_w_lg_w_lg_w_lg_dataout13056w13057w13058w(0) <= wire_niO11lll_w_lg_w_lg_dataout13056w13057w(0) AND wire_niO11lil_dataout; + wire_niO11lll_w_lg_w_lg_w_lg_dataout13084w13085w13086w(0) <= wire_niO11lll_w_lg_w_lg_dataout13084w13085w(0) AND wire_niO11lil_dataout; + wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13075w13077w(0) <= wire_niO11lll_w_lg_w_lg_dataout13066w13075w(0) AND wire_niO11liO_w_lg_dataout13076w(0); + wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13067w13119w(0) <= wire_niO11lll_w_lg_w_lg_dataout13066w13067w(0) AND wire_niO11liO_w_lg_dataout13076w(0); + wire_niO11lll_w_lg_w_lg_w_lg_dataout13066w13067w13068w(0) <= wire_niO11lll_w_lg_w_lg_dataout13066w13067w(0) AND wire_niO11liO_dataout; + wire_niO11lll_w_lg_w_lg_dataout13056w13057w(0) <= wire_niO11lll_w_lg_dataout13056w(0) AND wire_niO11liO_dataout; + wire_niO11lll_w_lg_w_lg_dataout13084w13085w(0) <= wire_niO11lll_w_lg_dataout13084w(0) AND wire_niO11liO_dataout; + wire_niO11lll_w_lg_w_lg_dataout13066w13075w(0) <= wire_niO11lll_w_lg_dataout13066w(0) AND wire_niO11lli_w_lg_dataout13055w(0); + wire_niO11lll_w_lg_w_lg_dataout13066w13067w(0) <= wire_niO11lll_w_lg_dataout13066w(0) AND wire_niO11lli_dataout; + wire_niO11lll_w_lg_dataout13056w(0) <= wire_niO11lll_dataout AND wire_niO11lli_w_lg_dataout13055w(0); + wire_niO11lll_w_lg_dataout13084w(0) <= wire_niO11lll_dataout AND wire_niO11lli_dataout; + wire_niO11lll_w_lg_dataout13066w(0) <= NOT wire_niO11lll_dataout; + wire_niO11llO_dataout <= niO1i0iO WHEN (NOT k_hip(3)) = '1' ELSE rxstatus5(0); + wire_niO11llO_w_lg_dataout13577w(0) <= NOT wire_niO11llO_dataout; + wire_niO11lO_dataout <= niiiOil WHEN niOO0liOi = '1' ELSE wire_niO0l0i_dataout; + wire_niO11lOi_dataout <= niO1i0li WHEN (NOT k_hip(3)) = '1' ELSE rxstatus5(1); + wire_niO11lOi_w_lg_dataout13575w(0) <= NOT wire_niO11lOi_dataout; + wire_niO11lOl_dataout <= niO1i0ll WHEN (NOT k_hip(3)) = '1' ELSE rxstatus5(2); + wire_niO11lOl_w_lg_w_lg_w_lg_dataout13909w23937w23938w(0) <= wire_niO11lOl_w_lg_w_lg_dataout13909w23937w(0) AND wire_niO11llO_dataout; + wire_niO11lOl_w_lg_w_lg_dataout13579w13580w(0) <= wire_niO11lOl_w_lg_dataout13579w(0) AND wire_niO11llO_dataout; + wire_niO11lOl_w_lg_w_lg_dataout13909w23937w(0) <= wire_niO11lOl_w_lg_dataout13909w(0) AND wire_niO11lOi_dataout; + wire_niO11lOl_w_lg_dataout13576w(0) <= wire_niO11lOl_dataout AND wire_niO11lOi_w_lg_dataout13575w(0); + wire_niO11lOl_w_lg_dataout13579w(0) <= wire_niO11lOl_dataout AND wire_niO11lOi_dataout; + wire_niO11lOl_w_lg_dataout13909w(0) <= NOT wire_niO11lOl_dataout; + wire_niO11lOO_dataout <= niO1OOOi WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle5; + wire_niO11O0i_dataout <= niO1i0OO WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(0); + wire_niO11O0i_w_lg_dataout13970w(0) <= NOT wire_niO11O0i_dataout; + wire_niO11O0l_dataout <= niO1ii1i WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(1); + wire_niO11O0l_w_lg_dataout13968w(0) <= NOT wire_niO11O0l_dataout; + wire_niO11O0O_dataout <= niO1ii1l WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(2); + wire_niO11O0O_w_lg_dataout14016w(0) <= NOT wire_niO11O0O_dataout; + wire_niO11O1i_dataout <= niO1i0lO WHEN (NOT k_hip(3)) = '1' ELSE phystatus5; + wire_niO11O1i_w_lg_dataout19806w(0) <= NOT wire_niO11O1i_dataout; + wire_niO11O1l_dataout <= niO1i0Oi WHEN (NOT k_hip(3)) = '1' ELSE rxvalid5; + wire_niO11O1l_w_lg_dataout27516w(0) <= NOT wire_niO11O1l_dataout; + wire_niO11O1O_dataout <= niO1i0Ol WHEN (NOT k_hip(3)) = '1' ELSE rxdatak5; + wire_niO11O1O_w_lg_dataout13618w(0) <= NOT wire_niO11O1O_dataout; + wire_niO11Oi_dataout <= niiiOiO WHEN niOO0liOi = '1' ELSE wire_niO0l0l_dataout; + wire_niO11Oii_dataout <= niO1ii1O WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(3); + wire_niO11Oii_w_lg_dataout13994w(0) <= NOT wire_niO11Oii_dataout; + wire_niO11Oil_dataout <= niO1ii0i WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(4); + wire_niO11Oil_w_lg_dataout14027w(0) <= NOT wire_niO11Oil_dataout; + wire_niO11OiO_dataout <= niO1ii0l WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(5); + wire_niO11OiO_w_lg_dataout13983w(0) <= NOT wire_niO11OiO_dataout; + wire_niO11Ol_dataout <= niiiOli WHEN niOO0liOi = '1' ELSE wire_niO0l0O_dataout; + wire_niO11Oli_dataout <= niO1ii0O WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(6); + wire_niO11Oli_w_lg_dataout13962w(0) <= NOT wire_niO11Oli_dataout; + wire_niO11Oll_dataout <= niO1iiii WHEN (NOT k_hip(3)) = '1' ELSE rxdata5(7); + wire_niO11Oll_w14037w(0) <= wire_niO11Oll_w_lg_w_lg_w_lg_w14028w14034w14035w14036w(0) AND wire_niO11O0i_dataout; + wire_niO11Oll_w_lg_w_lg_w_lg_w14021w14022w14023w14024w(0) <= wire_niO11Oll_w_lg_w_lg_w14021w14022w14023w(0) AND wire_niO11O0i_dataout; + wire_niO11Oll_w_lg_w_lg_w_lg_w14028w14034w14035w14036w(0) <= wire_niO11Oll_w_lg_w_lg_w14028w14034w14035w(0) AND wire_niO11O0l_w_lg_dataout13968w(0); + wire_niO11Oll_w_lg_w_lg_w_lg_w14028w14029w14030w14031w(0) <= wire_niO11Oll_w_lg_w_lg_w14028w14029w14030w(0) AND wire_niO11O0l_dataout; + wire_niO11Oll_w_lg_w_lg_w14021w14022w14023w(0) <= wire_niO11Oll_w_lg_w14021w14022w(0) AND wire_niO11O0l_w_lg_dataout13968w(0); + wire_niO11Oll_w_lg_w_lg_w13966w14017w14018w(0) <= wire_niO11Oll_w_lg_w13966w14017w(0) AND wire_niO11O0l_dataout; + wire_niO11Oll_w_lg_w_lg_w13985w13986w13987w(0) <= wire_niO11Oll_w_lg_w13985w13986w(0) AND wire_niO11O0O_dataout; + wire_niO11Oll_w_lg_w_lg_w14028w14034w14035w(0) <= wire_niO11Oll_w_lg_w14028w14034w(0) AND wire_niO11O0O_dataout; + wire_niO11Oll_w_lg_w_lg_w14028w14029w14030w(0) <= wire_niO11Oll_w_lg_w14028w14029w(0) AND wire_niO11O0O_w_lg_dataout14016w(0); + wire_niO11Oll_w_lg_w_lg_w13976w13977w13978w(0) <= wire_niO11Oll_w_lg_w13976w13977w(0) AND wire_niO11O0O_dataout; + wire_niO11Oll_w_lg_w14021w14022w(0) <= wire_niO11Oll_w14021w(0) AND wire_niO11O0O_dataout; + wire_niO11Oll_w_lg_w13966w14017w(0) <= wire_niO11Oll_w13966w(0) AND wire_niO11O0O_w_lg_dataout14016w(0); + wire_niO11Oll_w_lg_w13966w13967w(0) <= wire_niO11Oll_w13966w(0) AND wire_niO11O0O_dataout; + wire_niO11Oll_w_lg_w14120w14121w(0) <= wire_niO11Oll_w14120w(0) AND wire_niO11O0O_dataout; + wire_niO11Oll_w_lg_w13985w13986w(0) <= wire_niO11Oll_w13985w(0) AND wire_niO11Oii_dataout; + wire_niO11Oll_w_lg_w14028w14034w(0) <= wire_niO11Oll_w14028w(0) AND wire_niO11Oii_w_lg_dataout13994w(0); + wire_niO11Oll_w_lg_w14028w14029w(0) <= wire_niO11Oll_w14028w(0) AND wire_niO11Oii_dataout; + wire_niO11Oll_w_lg_w13976w13977w(0) <= wire_niO11Oll_w13976w(0) AND wire_niO11Oii_dataout; + wire_niO11Oll_w14021w(0) <= wire_niO11Oll_w_lg_w_lg_w_lg_dataout13963w13964w13965w(0) AND wire_niO11Oii_w_lg_dataout13994w(0); + wire_niO11Oll_w13966w(0) <= wire_niO11Oll_w_lg_w_lg_w_lg_dataout13963w13964w13965w(0) AND wire_niO11Oii_dataout; + wire_niO11Oll_w14120w(0) <= wire_niO11Oll_w_lg_w_lg_w_lg_dataout13991w13992w13993w(0) AND wire_niO11Oii_dataout; + wire_niO11Oll_w13985w(0) <= wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13982w13984w(0) AND wire_niO11Oil_dataout; + wire_niO11Oll_w14028w(0) <= wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13974w14026w(0) AND wire_niO11Oil_w_lg_dataout14027w(0); + wire_niO11Oll_w13976w(0) <= wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13974w13975w(0) AND wire_niO11Oil_dataout; + wire_niO11Oll_w_lg_w_lg_w_lg_dataout13963w13964w13965w(0) <= wire_niO11Oll_w_lg_w_lg_dataout13963w13964w(0) AND wire_niO11Oil_dataout; + wire_niO11Oll_w_lg_w_lg_w_lg_dataout13991w13992w13993w(0) <= wire_niO11Oll_w_lg_w_lg_dataout13991w13992w(0) AND wire_niO11Oil_dataout; + wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13982w13984w(0) <= wire_niO11Oll_w_lg_w_lg_dataout13973w13982w(0) AND wire_niO11OiO_w_lg_dataout13983w(0); + wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13974w14026w(0) <= wire_niO11Oll_w_lg_w_lg_dataout13973w13974w(0) AND wire_niO11OiO_w_lg_dataout13983w(0); + wire_niO11Oll_w_lg_w_lg_w_lg_dataout13973w13974w13975w(0) <= wire_niO11Oll_w_lg_w_lg_dataout13973w13974w(0) AND wire_niO11OiO_dataout; + wire_niO11Oll_w_lg_w_lg_dataout13963w13964w(0) <= wire_niO11Oll_w_lg_dataout13963w(0) AND wire_niO11OiO_dataout; + wire_niO11Oll_w_lg_w_lg_dataout13991w13992w(0) <= wire_niO11Oll_w_lg_dataout13991w(0) AND wire_niO11OiO_dataout; + wire_niO11Oll_w_lg_w_lg_dataout13973w13982w(0) <= wire_niO11Oll_w_lg_dataout13973w(0) AND wire_niO11Oli_w_lg_dataout13962w(0); + wire_niO11Oll_w_lg_w_lg_dataout13973w13974w(0) <= wire_niO11Oll_w_lg_dataout13973w(0) AND wire_niO11Oli_dataout; + wire_niO11Oll_w_lg_dataout13963w(0) <= wire_niO11Oll_dataout AND wire_niO11Oli_w_lg_dataout13962w(0); + wire_niO11Oll_w_lg_dataout13991w(0) <= wire_niO11Oll_dataout AND wire_niO11Oli_dataout; + wire_niO11Oll_w_lg_dataout13973w(0) <= NOT wire_niO11Oll_dataout; + wire_niO11OlO_dataout <= niO1iiil WHEN (NOT k_hip(3)) = '1' ELSE rxstatus4(0); + wire_niO11OlO_w_lg_dataout14484w(0) <= NOT wire_niO11OlO_dataout; + wire_niO11OO_dataout <= niiiOll WHEN niOO0liOi = '1' ELSE wire_niO0lii_dataout; + wire_niO11OOi_dataout <= niO1iiiO WHEN (NOT k_hip(3)) = '1' ELSE rxstatus4(1); + wire_niO11OOi_w_lg_dataout14482w(0) <= NOT wire_niO11OOi_dataout; + wire_niO11OOl_dataout <= niO1iili WHEN (NOT k_hip(3)) = '1' ELSE rxstatus4(2); + wire_niO11OOl_w_lg_w_lg_w_lg_dataout14816w23933w23934w(0) <= wire_niO11OOl_w_lg_w_lg_dataout14816w23933w(0) AND wire_niO11OlO_dataout; + wire_niO11OOl_w_lg_w_lg_dataout14486w14487w(0) <= wire_niO11OOl_w_lg_dataout14486w(0) AND wire_niO11OlO_dataout; + wire_niO11OOl_w_lg_w_lg_dataout14816w23933w(0) <= wire_niO11OOl_w_lg_dataout14816w(0) AND wire_niO11OOi_dataout; + wire_niO11OOl_w_lg_dataout14483w(0) <= wire_niO11OOl_dataout AND wire_niO11OOi_w_lg_dataout14482w(0); + wire_niO11OOl_w_lg_dataout14486w(0) <= wire_niO11OOl_dataout AND wire_niO11OOi_dataout; + wire_niO11OOl_w_lg_dataout14816w(0) <= NOT wire_niO11OOl_dataout; + wire_niO11OOO_dataout <= niO110ll WHEN (NOT k_hip(3)) = '1' ELSE rxelecidle4; + wire_niO1i0i_dataout <= nii1O1O WHEN niOO0liOi = '1' ELSE wire_niO0Oli_dataout; + wire_niO1i0l_dataout <= nii1O0i WHEN niOO0liOi = '1' ELSE wire_niO0Oll_dataout; + wire_niO1i0O_dataout <= nii1O0l WHEN niOO0liOi = '1' ELSE wire_niO0OlO_dataout; + wire_niO1i1i_dataout <= nii1lOO WHEN niOO0liOi = '1' ELSE wire_niO0Oii_dataout; + wire_niO1i1l_dataout <= nii1O1i WHEN niOO0liOi = '1' ELSE wire_niO0Oil_dataout; + wire_niO1i1O_dataout <= nii1O1l WHEN niOO0liOi = '1' ELSE wire_niO0OiO_dataout; + wire_niO1iii_dataout <= nii1O0O WHEN niOO0liOi = '1' ELSE wire_niO0OOi_dataout; + wire_niO1iil_dataout <= nii1Oii WHEN niOO0liOi = '1' ELSE wire_niO0OOl_dataout; + wire_niO1iiO_dataout <= nii1Oil WHEN niOO0liOi = '1' ELSE wire_niO0OOO_dataout; + wire_niO1ili_dataout <= nii1OiO WHEN niOO0liOi = '1' ELSE wire_niOi11i_dataout; + wire_niO1ill_dataout <= nii1Oli WHEN niOO0liOi = '1' ELSE wire_niOi11l_dataout; + wire_niO1ilO_dataout <= nii1Oll WHEN niOO0liOi = '1' ELSE wire_niOi11O_dataout; + wire_niO1iOi_dataout <= nii1OlO WHEN niOO0liOi = '1' ELSE wire_niOi10i_dataout; + wire_niO1iOl_dataout <= nii1OOi WHEN niOO0liOi = '1' ELSE wire_niOi10l_dataout; + wire_niO1iOO_dataout <= nii1OOl WHEN niOO0liOi = '1' ELSE wire_niOi10O_dataout; + wire_niO1l0i_dataout <= nii011O WHEN niOO0liOi = '1' ELSE wire_niOi1li_dataout; + wire_niO1l0l_dataout <= nii010i WHEN niOO0liOi = '1' ELSE wire_niOi1ll_dataout; + wire_niO1l0O_dataout <= nii010l WHEN niOO0liOi = '1' ELSE wire_niOi1lO_dataout; + wire_niO1l1i_dataout <= nii1OOO WHEN niOO0liOi = '1' ELSE wire_niOi1ii_dataout; + wire_niO1l1l_dataout <= nii011i WHEN niOO0liOi = '1' ELSE wire_niOi1il_dataout; + wire_niO1l1O_dataout <= nii011l WHEN niOO0liOi = '1' ELSE wire_niOi1iO_dataout; + wire_niO1li0l_dataout <= rxstatus7(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1li0O_dataout <= rxstatus7(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1lii_dataout <= niOi01O WHEN niOO0liOi = '1' ELSE nii010O; + wire_niO1liii_dataout <= rxstatus7(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1liil_dataout <= phystatus7 AND NOT(wire_niO01lOO_dataout); + wire_niO1liiO_dataout <= rxvalid7 AND NOT(wire_niO01lOO_dataout); + wire_niO1lil_dataout <= niOi00i WHEN niOO0liOi = '1' ELSE nii01ii; + wire_niO1lili_dataout <= rxdatak7 AND NOT(wire_niO01lOO_dataout); + wire_niO1lill_dataout <= rxdata7(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1lilO_dataout <= rxdata7(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1liO_dataout <= niOi00l WHEN niOO0liOi = '1' ELSE nii01il; + wire_niO1liOi_dataout <= rxdata7(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1liOl_dataout <= rxdata7(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1liOO_dataout <= rxdata7(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1ll0i_dataout <= rxstatus6(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1ll0l_dataout <= rxstatus6(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1ll0O_dataout <= rxstatus6(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1ll1i_dataout <= rxdata7(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1ll1l_dataout <= rxdata7(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1ll1O_dataout <= rxdata7(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1lli_dataout <= niOi00O WHEN niOO0liOi = '1' ELSE nii01iO; + wire_niO1llii_dataout <= phystatus6 AND NOT(wire_niO01lOO_dataout); + wire_niO1llil_dataout <= rxvalid6 AND NOT(wire_niO01lOO_dataout); + wire_niO1lliO_dataout <= rxdatak6 AND NOT(wire_niO01lOO_dataout); + wire_niO1lll_dataout <= niOi0ii WHEN niOO0liOi = '1' ELSE nii01li; + wire_niO1llli_dataout <= rxdata6(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1llll_dataout <= rxdata6(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1lllO_dataout <= rxdata6(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1llO_dataout <= niOi0il WHEN niOO0liOi = '1' ELSE nii01ll; + wire_niO1llOi_dataout <= rxdata6(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1llOl_dataout <= rxdata6(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1llOO_dataout <= rxdata6(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1lO0i_dataout <= rxstatus5(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1lO0l_dataout <= rxstatus5(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1lO0O_dataout <= phystatus5 AND NOT(wire_niO01lOO_dataout); + wire_niO1lO1i_dataout <= rxdata6(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1lO1l_dataout <= rxdata6(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1lO1O_dataout <= rxstatus5(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1lOi_dataout <= niOi0iO WHEN niOO0liOi = '1' ELSE nii01lO; + wire_niO1lOii_dataout <= rxvalid5 AND NOT(wire_niO01lOO_dataout); + wire_niO1lOil_dataout <= rxdatak5 AND NOT(wire_niO01lOO_dataout); + wire_niO1lOiO_dataout <= rxdata5(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1lOl_dataout <= niOi0li WHEN niOO0liOi = '1' ELSE nii01Oi; + wire_niO1lOli_dataout <= rxdata5(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1lOll_dataout <= rxdata5(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1lOlO_dataout <= rxdata5(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1lOO_dataout <= niOi0ll WHEN niOO0liOi = '1' ELSE nii01Ol; + wire_niO1lOOi_dataout <= rxdata5(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1lOOl_dataout <= rxdata5(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1lOOO_dataout <= rxdata5(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1O00i_dataout <= phystatus3 AND NOT(wire_niO01lOO_dataout); + wire_niO1O00l_dataout <= rxvalid3 AND NOT(wire_niO01lOO_dataout); + wire_niO1O00O_dataout <= rxdatak3 AND NOT(wire_niO01lOO_dataout); + wire_niO1O01i_dataout <= rxstatus3(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1O01l_dataout <= rxstatus3(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1O01O_dataout <= rxstatus3(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0i_dataout <= niOi0OO WHEN niOO0liOi = '1' ELSE nii001O; + wire_niO1O0ii_dataout <= rxdata3(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0il_dataout <= rxdata3(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0iO_dataout <= rxdata3(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0l_dataout <= niOii1i WHEN niOO0liOi = '1' ELSE nii000i; + wire_niO1O0li_dataout <= rxdata3(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0ll_dataout <= rxdata3(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0lO_dataout <= rxdata3(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0O_dataout <= niOii1l WHEN niOO0liOi = '1' ELSE nii000l; + wire_niO1O0Oi_dataout <= rxdata3(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0Ol_dataout <= rxdata3(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1O0OO_dataout <= rxstatus2(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1O10i_dataout <= rxstatus4(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1O10l_dataout <= phystatus4 AND NOT(wire_niO01lOO_dataout); + wire_niO1O10O_dataout <= rxvalid4 AND NOT(wire_niO01lOO_dataout); + wire_niO1O11i_dataout <= rxdata5(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1O11l_dataout <= rxstatus4(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1O11O_dataout <= rxstatus4(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1i_dataout <= niOi0lO WHEN niOO0liOi = '1' ELSE nii01OO; + wire_niO1O1ii_dataout <= rxdatak4 AND NOT(wire_niO01lOO_dataout); + wire_niO1O1il_dataout <= rxdata4(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1iO_dataout <= rxdata4(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1l_dataout <= niOi0Oi WHEN niOO0liOi = '1' ELSE nii001i; + wire_niO1O1li_dataout <= rxdata4(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1ll_dataout <= rxdata4(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1lO_dataout <= rxdata4(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1O_dataout <= niOi0Ol WHEN niOO0liOi = '1' ELSE nii001l; + wire_niO1O1Oi_dataout <= rxdata4(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1Ol_dataout <= rxdata4(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1O1OO_dataout <= rxdata4(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oi0i_dataout <= rxvalid2 AND NOT(wire_niO01lOO_dataout); + wire_niO1Oi0l_dataout <= rxdatak2 AND NOT(wire_niO01lOO_dataout); + wire_niO1Oi0O_dataout <= rxdata2(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oi1i_dataout <= rxstatus2(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oi1l_dataout <= rxstatus2(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oi1O_dataout <= phystatus2 AND NOT(wire_niO01lOO_dataout); + wire_niO1Oii_dataout <= niOii1O WHEN niOO0liOi = '1' ELSE nii000O; + wire_niO1Oiii_dataout <= rxdata2(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oiil_dataout <= rxdata2(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1OiiO_dataout <= rxdata2(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oil_dataout <= niOii0i WHEN niOO0liOi = '1' ELSE nii00ii; + wire_niO1Oili_dataout <= rxdata2(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oill_dataout <= rxdata2(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1OilO_dataout <= rxdata2(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1OiO_dataout <= niOii0l WHEN niOO0liOi = '1' ELSE nii00il; + wire_niO1OiOi_dataout <= rxdata2(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1OiOl_dataout <= rxstatus1(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1OiOO_dataout <= rxstatus1(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1Ol0i_dataout <= rxdatak1 AND NOT(wire_niO01lOO_dataout); + wire_niO1Ol0l_dataout <= rxdata1(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1Ol0O_dataout <= rxdata1(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1Ol1i_dataout <= rxstatus1(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1Ol1l_dataout <= phystatus1 AND NOT(wire_niO01lOO_dataout); + wire_niO1Ol1O_dataout <= rxvalid1 AND NOT(wire_niO01lOO_dataout); + wire_niO1Oli_dataout <= niOii0O WHEN niOO0liOi = '1' ELSE nii00iO; + wire_niO1Olii_dataout <= rxdata1(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1Olil_dataout <= rxdata1(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1OliO_dataout <= rxdata1(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1Oll_dataout <= niOiiii WHEN niOO0liOi = '1' ELSE nii00li; + wire_niO1Olli_dataout <= rxdata1(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1Olll_dataout <= rxdata1(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1OllO_dataout <= rxdata1(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1OlO_dataout <= niOiiil WHEN niOO0liOi = '1' ELSE nii00ll; + wire_niO1OlOi_dataout <= rxstatus0(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1OlOl_dataout <= rxstatus0(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1OlOO_dataout <= rxstatus0(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1OO0i_dataout <= rxdata0(0) AND NOT(wire_niO01lOO_dataout); + wire_niO1OO0l_dataout <= rxdata0(1) AND NOT(wire_niO01lOO_dataout); + wire_niO1OO0O_dataout <= rxdata0(2) AND NOT(wire_niO01lOO_dataout); + wire_niO1OO1i_dataout <= phystatus0 AND NOT(wire_niO01lOO_dataout); + wire_niO1OO1l_dataout <= rxvalid0 AND NOT(wire_niO01lOO_dataout); + wire_niO1OO1O_dataout <= rxdatak0 AND NOT(wire_niO01lOO_dataout); + wire_niO1OOi_dataout <= niOiiiO WHEN niOO0liOi = '1' ELSE nii00lO; + wire_niO1OOii_dataout <= rxdata0(3) AND NOT(wire_niO01lOO_dataout); + wire_niO1OOil_dataout <= rxdata0(4) AND NOT(wire_niO01lOO_dataout); + wire_niO1OOiO_dataout <= rxdata0(5) AND NOT(wire_niO01lOO_dataout); + wire_niO1OOl_dataout <= niOiili WHEN niOO0liOi = '1' ELSE nii00Oi; + wire_niO1OOli_dataout <= rxdata0(6) AND NOT(wire_niO01lOO_dataout); + wire_niO1OOll_dataout <= rxdata0(7) AND NOT(wire_niO01lOO_dataout); + wire_niO1OOO_dataout <= niOiill WHEN niOO0liOi = '1' ELSE nii00Ol; + wire_niOi00OO_dataout <= wire_niOii11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0i0i_dataout <= wire_niOii10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0i0l_dataout <= wire_niOii10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0i0O_dataout <= wire_niOii1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0i1i_dataout <= wire_niOii11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0i1l_dataout <= wire_niOii11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0i1O_dataout <= wire_niOii10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0iii_dataout <= wire_niOii1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0iil_dataout <= wire_niOii1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0iiO_dataout <= wire_niOii1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0ili_dataout <= wire_niOii1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0ill_dataout <= wire_niOii1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0ilO_dataout <= wire_niOii1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0iOi_dataout <= wire_niOii1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0iOl_dataout <= wire_niOii1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0iOO_dataout <= wire_niOii01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0l0i_dataout <= wire_niOii00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0l0l_dataout <= wire_niOii00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0l0O_dataout <= wire_niOii0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0l1i_dataout <= wire_niOii01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0l1l_dataout <= wire_niOii01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0l1O_dataout <= wire_niOii00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0lii_dataout <= wire_niOii0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0lil_dataout <= wire_niOii0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0liO_dataout <= wire_niOii0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0lli_dataout <= wire_niOii0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0lll_dataout <= wire_niOii0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0llO_dataout <= wire_niOii0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0lOi_dataout <= wire_niOii0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0lOl_dataout <= wire_niOii0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0lOO_dataout <= wire_niOiii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0O0i_dataout <= wire_niOiii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0O0l_dataout <= wire_niOiii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0O0O_dataout <= wire_niOiiiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0O1i_dataout <= wire_niOiii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0O1l_dataout <= wire_niOiii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0O1O_dataout <= wire_niOiii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0Oii_dataout <= wire_niOiiiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0Oil_dataout <= wire_niOiiiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0OiO_dataout <= wire_niOiiili_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0Oli_dataout <= wire_niOiiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0Oll_dataout <= wire_niOiiilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0OlO_dataout <= wire_niOiiiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0OOi_dataout <= wire_niOiiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0OOl_dataout <= wire_niOiiiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi0OOO_dataout <= wire_niOiil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi10i_dataout <= niOiill WHEN niOO0lill = '1' ELSE nii1OlO; + wire_niOi10l_dataout <= niOiilO WHEN niOO0lill = '1' ELSE nii1OOi; + wire_niOi10O_dataout <= niOiiOi WHEN niOO0lill = '1' ELSE nii1OOl; + wire_niOi110i_dataout <= wire_niOi11il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi110l_dataout <= wire_niOi11iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi110O_dataout <= niOO10OOO AND NOT(wire_niO01O0O_dataout); + wire_niOi111O_dataout <= wire_niOi11ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOi11i_dataout <= niOiiil WHEN niOO0lill = '1' ELSE nii1OiO; + wire_niOi11ii_dataout <= wire_niOi11li_o(0) AND NOT(niOO10OOO); + wire_niOi11il_dataout <= wire_niOi11li_o(1) AND NOT(niOO10OOO); + wire_niOi11iO_dataout <= wire_niOi11li_o(2) AND NOT(niOO10OOO); + wire_niOi11l_dataout <= niOiiiO WHEN niOO0lill = '1' ELSE nii1Oli; + wire_niOi11O_dataout <= niOiili WHEN niOO0lill = '1' ELSE nii1Oll; + wire_niOi1ii_dataout <= niOiiOl WHEN niOO0lill = '1' ELSE nii1OOO; + wire_niOi1il_dataout <= niOiiOO WHEN niOO0lill = '1' ELSE nii011i; + wire_niOi1iO_dataout <= niOil1i WHEN niOO0lill = '1' ELSE nii011l; + wire_niOi1li_dataout <= niOil1l WHEN niOO0lill = '1' ELSE nii011O; + wire_niOi1ll_dataout <= niOil1O WHEN niOO0lill = '1' ELSE nii010i; + wire_niOi1lO_dataout <= niOil0i WHEN niOO0lill = '1' ELSE nii010l; + wire_niOii00i_dataout <= niOil11l WHEN niOO1i11i = '1' ELSE niOi011i; + wire_niOii00l_dataout <= niOil11O WHEN niOO1i11i = '1' ELSE niOi011l; + wire_niOii00O_dataout <= niOil10i WHEN niOO1i11i = '1' ELSE niOi011O; + wire_niOii01i_dataout <= niOiiOOl WHEN niOO1i11i = '1' ELSE niOi1OOi; + wire_niOii01l_dataout <= niOiiOOO WHEN niOO1i11i = '1' ELSE niOi1OOl; + wire_niOii01O_dataout <= niOil11i WHEN niOO1i11i = '1' ELSE niOi1OOO; + wire_niOii0ii_dataout <= niOil10l WHEN niOO1i11i = '1' ELSE niOi010i; + wire_niOii0il_dataout <= niOil10O WHEN niOO1i11i = '1' ELSE niOi010l; + wire_niOii0iO_dataout <= niOil1ii WHEN niOO1i11i = '1' ELSE niOi010O; + wire_niOii0li_dataout <= niOil1il WHEN niOO1i11i = '1' ELSE niOi01ii; + wire_niOii0ll_dataout <= niOil1iO WHEN niOO1i11i = '1' ELSE niOi01il; + wire_niOii0lO_dataout <= niOil1li WHEN niOO1i11i = '1' ELSE niOi01iO; + wire_niOii0Oi_dataout <= niOil1ll WHEN niOO1i11i = '1' ELSE niOi01li; + wire_niOii0Ol_dataout <= niOil1lO WHEN niOO1i11i = '1' ELSE niOi01ll; + wire_niOii0OO_dataout <= niOil1Oi WHEN niOO1i11i = '1' ELSE niOi01lO; + wire_niOii10i_dataout <= niOiiO1l WHEN niOO1i11i = '1' ELSE niOi1O1i; + wire_niOii10l_dataout <= niOiiO1O WHEN niOO1i11i = '1' ELSE niOi1O1l; + wire_niOii10O_dataout <= niOiiO0i WHEN niOO1i11i = '1' ELSE niOi1O1O; + wire_niOii11i_dataout <= niOiilOl WHEN niOO1i11i = '1' ELSE niOiil1O; + wire_niOii11l_dataout <= niOiilOO WHEN niOO1i11i = '1' ELSE niOi1lOl; + wire_niOii11O_dataout <= niOiiO1i WHEN niOO1i11i = '1' ELSE niOi1lOO; + wire_niOii1ii_dataout <= niOiiO0l WHEN niOO1i11i = '1' ELSE niOi1O0i; + wire_niOii1il_dataout <= niOiiO0O WHEN niOO1i11i = '1' ELSE niOi1O0l; + wire_niOii1iO_dataout <= niOiiOii WHEN niOO1i11i = '1' ELSE niOi1O0O; + wire_niOii1li_dataout <= niOiiOil WHEN niOO1i11i = '1' ELSE niOi1Oii; + wire_niOii1ll_dataout <= niOiiOiO WHEN niOO1i11i = '1' ELSE niOi1Oil; + wire_niOii1lO_dataout <= niOiiOli WHEN niOO1i11i = '1' ELSE niOi1OiO; + wire_niOii1Oi_dataout <= niOiiOll WHEN niOO1i11i = '1' ELSE niOi1Oli; + wire_niOii1Ol_dataout <= niOiiOlO WHEN niOO1i11i = '1' ELSE niOi1Oll; + wire_niOii1OO_dataout <= niOiiOOi WHEN niOO1i11i = '1' ELSE niOi1OlO; + wire_niOiii0i_dataout <= niOil01l WHEN niOO1i11i = '1' ELSE niOi001i; + wire_niOiii0l_dataout <= niOil01O WHEN niOO1i11i = '1' ELSE niOi001l; + wire_niOiii0O_dataout <= niOil00i WHEN niOO1i11i = '1' ELSE niOi001O; + wire_niOiii1i_dataout <= niOil1Ol WHEN niOO1i11i = '1' ELSE niOi01Oi; + wire_niOiii1l_dataout <= niOil1OO WHEN niOO1i11i = '1' ELSE niOi01Ol; + wire_niOiii1O_dataout <= niOil01i WHEN niOO1i11i = '1' ELSE niOi01OO; + wire_niOiiiii_dataout <= niOil00l WHEN niOO1i11i = '1' ELSE niOi000i; + wire_niOiiiil_dataout <= niOil00O WHEN niOO1i11i = '1' ELSE niOi000l; + wire_niOiiiiO_dataout <= niOil0ii WHEN niOO1i11i = '1' ELSE niOi000O; + wire_niOiiili_dataout <= niOil0il WHEN niOO1i11i = '1' ELSE niOi00ii; + wire_niOiiill_dataout <= niOil0iO WHEN niOO1i11i = '1' ELSE niOi00il; + wire_niOiiilO_dataout <= niOil0li WHEN niOO1i11i = '1' ELSE niOi00iO; + wire_niOiiiOi_dataout <= niOil0ll WHEN niOO1i11i = '1' ELSE niOi00li; + wire_niOiiiOl_dataout <= niOil0lO WHEN niOO1i11i = '1' ELSE niOi00ll; + wire_niOiiiOO_dataout <= niOil0Oi WHEN niOO1i11i = '1' ELSE niOi00lO; + wire_niOiil0l_dataout <= niOiilil AND NOT(wire_niO01l0O_dataout); + wire_niOiil1i_dataout <= niOil0Ol WHEN niOO1i11i = '1' ELSE niOi00Oi; + wire_niOiilii_dataout <= niOi00Ol AND NOT(wire_niO01l0O_dataout); + wire_niOiiliO_dataout <= niOiilll AND NOT(wire_niO01O0O_dataout); + wire_niOiillO_dataout <= niOiilli AND NOT(wire_niO01O0O_dataout); + wire_niOiilOi_dataout <= niOiil0O AND NOT(wire_niO01O0O_dataout); + wire_niOili0i_dataout <= wire_niOiO1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOili0l_dataout <= wire_niOiO1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOili0O_dataout <= wire_niOiO1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOili1i_dataout <= wire_niOiO10i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOili1l_dataout <= wire_niOiO10O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOili1O_dataout <= wire_niOiO1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiliii_dataout <= wire_niOiO1ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiliil_dataout <= wire_niOiO1lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiliiO_dataout <= wire_niOiO1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilili_dataout <= wire_niOiO1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilill_dataout <= wire_niOiO1OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOililO_dataout <= wire_niOiO01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiliOi_dataout <= wire_niOiO01l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiliOl_dataout <= wire_niOiO01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiliOO_dataout <= wire_niOiO00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOill0i_dataout <= wire_niOiO0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOill0l_dataout <= wire_niOiO0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOill0O_dataout <= wire_niOiO0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOill1i_dataout <= wire_niOiO00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOill1l_dataout <= wire_niOiO00O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOill1O_dataout <= wire_niOiO0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOillii_dataout <= wire_niOiO0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOillil_dataout <= wire_niOiO0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilliO_dataout <= wire_niOiO0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOillli_dataout <= wire_niOiO0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOillll_dataout <= wire_niOiO0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilllO_dataout <= wire_niOiOi1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOillOi_dataout <= wire_niOiOi1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOillOl_dataout <= wire_niOiOi1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOillOO_dataout <= wire_niOiOi0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilO0i_dataout <= wire_niOiOiil_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilO0l_dataout <= wire_niOiOiiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilO0O_dataout <= wire_niOiOili_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilO1i_dataout <= wire_niOiOi0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilO1l_dataout <= wire_niOiOi0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilO1O_dataout <= wire_niOiOiii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOii_dataout <= wire_niOiOill_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOil_dataout <= wire_niOiOilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOiO_dataout <= wire_niOiOiOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOli_dataout <= wire_niOiOiOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOll_dataout <= wire_niOiOiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOlO_dataout <= wire_niOiOl1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOOi_dataout <= wire_niOiOl1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOOl_dataout <= wire_niOiOl1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOilOOO_dataout <= wire_niOiOl0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiO00i_dataout <= niOiOOil WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOlO; + wire_niOiO00l_dataout <= niOiOOiO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOOi; + wire_niOiO00O_dataout <= niOiOOli WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOOl; + wire_niOiO01i_dataout <= niOiOO0l WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOiO; + wire_niOiO01l_dataout <= niOiOO0O WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOli; + wire_niOiO01O_dataout <= niOiOOii WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOll; + wire_niOiO0ii_dataout <= niOiOOll WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOOO; + wire_niOiO0il_dataout <= niOiOOlO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil11i; + wire_niOiO0iO_dataout <= niOiOOOi WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil11l; + wire_niOiO0li_dataout <= niOiOOOl WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil11O; + wire_niOiO0ll_dataout <= niOiOOOO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil10i; + wire_niOiO0lO_dataout <= niOl111i WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil10l; + wire_niOiO0Oi_dataout <= niOl111l WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil10O; + wire_niOiO0Ol_dataout <= niOl111O WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1ii; + wire_niOiO0OO_dataout <= niOl110i WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1il; + wire_niOiO10i_dataout <= wire_niOOO0O_w_lg_niOiilll8581w(0) WHEN (wire_w_lg_niOO1i11O8580w(0) AND wire_w_lg_niOO1i11l8582w(0)) = '1' ELSE niOiilll; + wire_niOiO10O_dataout <= niOiOlli WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiilOl; + wire_niOiO11i_dataout <= wire_niOiOl0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiO11l_dataout <= wire_niOiOl0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiO11O_dataout <= wire_niOiOlii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOiO1ii_dataout <= niOiOlll WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiilOO; + wire_niOiO1il_dataout <= niOiOllO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiO1i; + wire_niOiO1iO_dataout <= niOiOlOi WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiO1l; + wire_niOiO1li_dataout <= niOiOlOl WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiO1O; + wire_niOiO1ll_dataout <= niOiOlOO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiO0i; + wire_niOiO1lO_dataout <= niOiOO1i WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiO0l; + wire_niOiO1Oi_dataout <= niOiOO1l WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiO0O; + wire_niOiO1Ol_dataout <= niOiOO1O WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOii; + wire_niOiO1OO_dataout <= niOiOO0i WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOiiOil; + wire_niOiOi0i_dataout <= niOl11il WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1lO; + wire_niOiOi0l_dataout <= niOl11iO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1Oi; + wire_niOiOi0O_dataout <= niOl11li WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1Ol; + wire_niOiOi1i_dataout <= niOl110l WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1iO; + wire_niOiOi1l_dataout <= niOl110O WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1li; + wire_niOiOi1O_dataout <= niOl11ii WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1ll; + wire_niOiOiii_dataout <= niOl11ll WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil1OO; + wire_niOiOiil_dataout <= niOl11lO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil01i; + wire_niOiOiiO_dataout <= niOl11Oi WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil01l; + wire_niOiOil_dataout <= niOi00lO AND NOT(wire_niO01O0O_dataout); + wire_niOiOili_dataout <= niOl11Ol WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil01O; + wire_niOiOill_dataout <= niOl11OO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil00i; + wire_niOiOilO_dataout <= niOl101i WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil00l; + wire_niOiOiO_dataout <= niOi00Oi AND NOT(wire_niO01O0O_dataout); + wire_niOiOiOi_dataout <= niOl101l WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil00O; + wire_niOiOiOl_dataout <= niOl101O WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0ii; + wire_niOiOiOO_dataout <= niOl100i WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0il; + wire_niOiOl0i_dataout <= niOl10il WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0lO; + wire_niOiOl0l_dataout <= niOl10iO WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0Oi; + wire_niOiOl0O_dataout <= niOl10li WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0Ol; + wire_niOiOl1i_dataout <= niOl100l WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0iO; + wire_niOiOl1l_dataout <= niOl100O WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0li; + wire_niOiOl1O_dataout <= niOl10ii WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0ll; + wire_niOiOli_dataout <= wire_niOliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOiOlii_dataout <= niOlii1O WHEN wire_w_lg_niOO1i11O8580w(0) = '1' ELSE niOil0OO; + wire_niOiOll_dataout <= wire_niOliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOiOlO_dataout <= wire_niOll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOiOOi_dataout <= wire_niOll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOiOOl_dataout <= wire_niOll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOiOOO_dataout <= wire_niOll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl000i_dataout <= niOOi0O WHEN niOiOii = '1' ELSE wire_niOl0OlO_dataout; + wire_niOl000l_dataout <= niOOiii WHEN niOiOii = '1' ELSE wire_niOl0OOi_dataout; + wire_niOl000O_dataout <= niOOiil WHEN niOiOii = '1' ELSE wire_niOl0OOl_dataout; + wire_niOl001i_dataout <= niOOi1O WHEN niOiOii = '1' ELSE wire_niOl0OiO_dataout; + wire_niOl001l_dataout <= niOOi0i WHEN niOiOii = '1' ELSE wire_niOl0Oli_dataout; + wire_niOl001O_dataout <= niOOi0l WHEN niOiOii = '1' ELSE wire_niOl0Oll_dataout; + wire_niOl00i_dataout <= wire_niOlOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl00ii_dataout <= niOOiiO WHEN niOiOii = '1' ELSE wire_niOl0OOO_dataout; + wire_niOl00il_dataout <= niOOili WHEN niOiOii = '1' ELSE wire_niOli11i_dataout; + wire_niOl00iO_dataout <= niOOill WHEN niOiOii = '1' ELSE wire_niOli11l_dataout; + wire_niOl00l_dataout <= wire_niOlOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl00li_dataout <= niOOilO WHEN niOiOii = '1' ELSE wire_niOli11O_dataout; + wire_niOl00ll_dataout <= niOOiOi WHEN niOiOii = '1' ELSE wire_niOli10i_dataout; + wire_niOl00lO_dataout <= niOOiOl WHEN niOiOii = '1' ELSE wire_niOli10l_dataout; + wire_niOl00O_dataout <= wire_niOlOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl00Oi_dataout <= niOOiOO WHEN niOiOii = '1' ELSE wire_niOli10O_dataout; + wire_niOl00Ol_dataout <= niOOl1i WHEN niOiOii = '1' ELSE wire_niOli1ii_dataout; + wire_niOl00OO_dataout <= niOOl1l WHEN niOiOii = '1' ELSE wire_niOli1il_dataout; + wire_niOl010i_dataout <= niOO00O WHEN niOiOii = '1' ELSE wire_niOl0llO_dataout; + wire_niOl010l_dataout <= niOO0ii WHEN niOiOii = '1' ELSE wire_niOl0lOi_dataout; + wire_niOl010O_dataout <= niOO0il WHEN niOiOii = '1' ELSE wire_niOl0lOl_dataout; + wire_niOl011i_dataout <= wire_niOl0l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl011l_dataout <= wire_niOl0lii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl011O_dataout <= wire_niOl0lil_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl01i_dataout <= wire_niOlO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl01ii_dataout <= niOO0iO WHEN niOiOii = '1' ELSE wire_niOl0lOO_dataout; + wire_niOl01il_dataout <= niOO0li WHEN niOiOii = '1' ELSE wire_niOl0O1i_dataout; + wire_niOl01iO_dataout <= niOO0ll WHEN niOiOii = '1' ELSE wire_niOl0O1l_dataout; + wire_niOl01l_dataout <= wire_niOlO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl01li_dataout <= niOO0lO WHEN niOiOii = '1' ELSE wire_niOl0O1O_dataout; + wire_niOl01ll_dataout <= niOO0Oi WHEN niOiOii = '1' ELSE wire_niOl0O0i_dataout; + wire_niOl01lO_dataout <= niOO0Ol WHEN niOiOii = '1' ELSE wire_niOl0O0l_dataout; + wire_niOl01O_dataout <= wire_niOlOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl01Oi_dataout <= niOO0OO WHEN niOiOii = '1' ELSE wire_niOl0O0O_dataout; + wire_niOl01Ol_dataout <= niOOi1i WHEN niOiOii = '1' ELSE wire_niOl0Oii_dataout; + wire_niOl01OO_dataout <= niOOi1l WHEN niOiOii = '1' ELSE wire_niOl0Oil_dataout; + wire_niOl0i0i_dataout <= niOOl0O WHEN niOiOii = '1' ELSE wire_niOli1lO_dataout; + wire_niOl0i0l_dataout <= niOOlii WHEN niOiOii = '1' ELSE wire_niOli1Oi_dataout; + wire_niOl0i0O_dataout <= niOOlil WHEN niOiOii = '1' ELSE wire_niOli1Ol_dataout; + wire_niOl0i1i_dataout <= niOOl1O WHEN niOiOii = '1' ELSE wire_niOli1iO_dataout; + wire_niOl0i1l_dataout <= niOOl0i WHEN niOiOii = '1' ELSE wire_niOli1li_dataout; + wire_niOl0i1O_dataout <= niOOl0l WHEN niOiOii = '1' ELSE wire_niOli1ll_dataout; + wire_niOl0ii_dataout <= wire_niOlOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0iii_dataout <= niOOliO WHEN niOiOii = '1' ELSE wire_niOli1OO_dataout; + wire_niOl0iil_dataout <= niOOlli WHEN niOiOii = '1' ELSE wire_niOli01i_dataout; + wire_niOl0iiO_dataout <= niOOlll WHEN niOiOii = '1' ELSE wire_niOli01l_dataout; + wire_niOl0il_dataout <= wire_niOlOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0ili_dataout <= niOOllO WHEN niOiOii = '1' ELSE wire_niOli01O_dataout; + wire_niOl0ill_dataout <= niOOlOi WHEN niOiOii = '1' ELSE wire_niOli00i_dataout; + wire_niOl0ilO_dataout <= niOOlOl WHEN niOiOii = '1' ELSE wire_niOli00l_dataout; + wire_niOl0iO_dataout <= wire_niOlOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0iOi_dataout <= niOOlOO WHEN niOiOii = '1' ELSE wire_niOli00O_dataout; + wire_niOl0iOl_dataout <= niOOO1i WHEN niOiOii = '1' ELSE wire_niOli0ii_dataout; + wire_niOl0iOO_dataout <= niOOO1l WHEN niOiOii = '1' ELSE wire_niOli0il_dataout; + wire_niOl0l0i_dataout <= niOOOii WHEN niOiOii = '1' ELSE wire_niOli0lO_dataout; + wire_niOl0l0l_dataout <= wire_niOli0Oi_dataout OR niOiOii; + wire_niOl0l0O_dataout <= wire_niOl0liO_dataout AND NOT(niOiOii); + wire_niOl0l1i_dataout <= niOOO1O WHEN niOiOii = '1' ELSE wire_niOli0iO_dataout; + wire_niOl0l1l_dataout <= niOOO0i WHEN niOiOii = '1' ELSE wire_niOli0li_dataout; + wire_niOl0l1O_dataout <= niOOO0l WHEN niOiOii = '1' ELSE wire_niOli0ll_dataout; + wire_niOl0li_dataout <= wire_niOlOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0lii_dataout <= wire_niOl0lli_dataout AND NOT(niOiOii); + wire_niOl0lil_dataout <= wire_niOl0lll_dataout AND NOT(niOiOii); + wire_niOl0liO_dataout <= niOl10ll WHEN niOO1i10i = '1' ELSE wire_niOli0Ol_dataout; + wire_niOl0ll_dataout <= wire_niOlOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0lli_dataout <= niOl10lO WHEN niOO1i10i = '1' ELSE wire_niOli0OO_dataout; + wire_niOl0lll_dataout <= niOl10Oi WHEN niOO1i10i = '1' ELSE wire_niOlii1i_dataout; + wire_niOl0llO_dataout <= niOiOlli AND NOT(niOO1i10i); + wire_niOl0lO_dataout <= wire_niOO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0lOi_dataout <= niOiOlll AND NOT(niOO1i10i); + wire_niOl0lOl_dataout <= niOiOllO AND NOT(niOO1i10i); + wire_niOl0lOO_dataout <= niOiOlOi AND NOT(niOO1i10i); + wire_niOl0O0i_dataout <= niOiOO1l AND NOT(niOO1i10i); + wire_niOl0O0l_dataout <= niOiOO1O AND NOT(niOO1i10i); + wire_niOl0O0O_dataout <= niOiOO0i AND NOT(niOO1i10i); + wire_niOl0O1i_dataout <= niOiOlOl AND NOT(niOO1i10i); + wire_niOl0O1l_dataout <= niOiOlOO AND NOT(niOO1i10i); + wire_niOl0O1O_dataout <= niOiOO1i AND NOT(niOO1i10i); + wire_niOl0Oi_dataout <= wire_niOO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0Oii_dataout <= niOiOO0l AND NOT(niOO1i10i); + wire_niOl0Oil_dataout <= niOiOO0O AND NOT(niOO1i10i); + wire_niOl0OiO_dataout <= niOiOOii AND NOT(niOO1i10i); + wire_niOl0Ol_dataout <= wire_niOO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0Oli_dataout <= niOiOOil AND NOT(niOO1i10i); + wire_niOl0Oll_dataout <= niOiOOiO AND NOT(niOO1i10i); + wire_niOl0OlO_dataout <= niOiOOli AND NOT(niOO1i10i); + wire_niOl0OO_dataout <= wire_niOO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl0OOi_dataout <= niOiOOll AND NOT(niOO1i10i); + wire_niOl0OOl_dataout <= niOiOOlO AND NOT(niOO1i10i); + wire_niOl0OOO_dataout <= niOiOOOi AND NOT(niOO1i10i); + wire_niOl10i_dataout <= wire_niOllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl10l_dataout <= wire_niOlliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl10O_dataout <= wire_niOllli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl10Ol_dataout <= wire_niOl0l0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl10OO_dataout <= wire_niOl010i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl11i_dataout <= wire_niOll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl11l_dataout <= wire_niOll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl11O_dataout <= wire_niOllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1i0i_dataout <= wire_niOl01il_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1i0l_dataout <= wire_niOl01iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1i0O_dataout <= wire_niOl01li_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1i1i_dataout <= wire_niOl010l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1i1l_dataout <= wire_niOl010O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1i1O_dataout <= wire_niOl01ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1ii_dataout <= wire_niOllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1iii_dataout <= wire_niOl01ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1iil_dataout <= wire_niOl01lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1iiO_dataout <= wire_niOl01Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1il_dataout <= wire_niOlllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1ili_dataout <= wire_niOl01Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1ill_dataout <= wire_niOl01OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1ilO_dataout <= wire_niOl001i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1iO_dataout <= wire_niOllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1iOi_dataout <= wire_niOl001l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1iOl_dataout <= wire_niOl001O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1iOO_dataout <= wire_niOl000i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1l0i_dataout <= wire_niOl00il_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1l0l_dataout <= wire_niOl00iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1l0O_dataout <= wire_niOl00li_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1l1i_dataout <= wire_niOl000l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1l1l_dataout <= wire_niOl000O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1l1O_dataout <= wire_niOl00ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1li_dataout <= wire_niOllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1lii_dataout <= wire_niOl00ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1lil_dataout <= wire_niOl00lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1liO_dataout <= wire_niOl00Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1ll_dataout <= wire_niOllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1lli_dataout <= wire_niOl00Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1lll_dataout <= wire_niOl00OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1llO_dataout <= wire_niOl0i1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1lO_dataout <= wire_niOlO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1lOi_dataout <= wire_niOl0i1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1lOl_dataout <= wire_niOl0i1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1lOO_dataout <= wire_niOl0i0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1O0i_dataout <= wire_niOl0iil_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1O0l_dataout <= wire_niOl0iiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1O0O_dataout <= wire_niOl0ili_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1O1i_dataout <= wire_niOl0i0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1O1l_dataout <= wire_niOl0i0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1O1O_dataout <= wire_niOl0iii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1Oi_dataout <= wire_niOlO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1Oii_dataout <= wire_niOl0ill_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1Oil_dataout <= wire_niOl0ilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1OiO_dataout <= wire_niOl0iOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1Ol_dataout <= wire_niOlO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1Oli_dataout <= wire_niOl0iOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1Oll_dataout <= wire_niOl0iOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1OlO_dataout <= wire_niOl0l1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1OO_dataout <= wire_niOlO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOl1OOi_dataout <= wire_niOl0l1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1OOl_dataout <= wire_niOl0l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOl1OOO_dataout <= wire_niOl0l0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOli00i_dataout <= niOl101l AND NOT(niOO1i10i); + wire_niOli00l_dataout <= niOl101O AND NOT(niOO1i10i); + wire_niOli00O_dataout <= niOl100i AND NOT(niOO1i10i); + wire_niOli01i_dataout <= niOl11Ol AND NOT(niOO1i10i); + wire_niOli01l_dataout <= niOl11OO AND NOT(niOO1i10i); + wire_niOli01O_dataout <= niOl101i AND NOT(niOO1i10i); + wire_niOli0i_dataout <= wire_niOO1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOli0ii_dataout <= niOl100l AND NOT(niOO1i10i); + wire_niOli0il_dataout <= niOl100O AND NOT(niOO1i10i); + wire_niOli0iO_dataout <= niOl10ii AND NOT(niOO1i10i); + wire_niOli0l_dataout <= wire_niOO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOli0li_dataout <= niOl10il AND NOT(niOO1i10i); + wire_niOli0ll_dataout <= niOl10iO AND NOT(niOO1i10i); + wire_niOli0lO_dataout <= niOl10li AND NOT(niOO1i10i); + wire_niOli0O_dataout <= wire_niOO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOli0Oi_dataout <= niOlii1O AND NOT(niOO1i10i); + wire_niOli0Ol_dataout <= wire_niOlii1l_o(0) WHEN niOlii1O = '1' ELSE niOl10ll; + wire_niOli0OO_dataout <= wire_niOlii1l_o(1) WHEN niOlii1O = '1' ELSE niOl10lO; + wire_niOli10i_dataout <= niOl111l AND NOT(niOO1i10i); + wire_niOli10l_dataout <= niOl111O AND NOT(niOO1i10i); + wire_niOli10O_dataout <= niOl110i AND NOT(niOO1i10i); + wire_niOli11i_dataout <= niOiOOOl AND NOT(niOO1i10i); + wire_niOli11l_dataout <= niOiOOOO AND NOT(niOO1i10i); + wire_niOli11O_dataout <= niOl111i AND NOT(niOO1i10i); + wire_niOli1i_dataout <= wire_niOO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOli1ii_dataout <= niOl110l AND NOT(niOO1i10i); + wire_niOli1il_dataout <= niOl110O AND NOT(niOO1i10i); + wire_niOli1iO_dataout <= niOl11ii AND NOT(niOO1i10i); + wire_niOli1l_dataout <= wire_niOO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOli1li_dataout <= niOl11il AND NOT(niOO1i10i); + wire_niOli1ll_dataout <= niOl11iO AND NOT(niOO1i10i); + wire_niOli1lO_dataout <= niOl11li AND NOT(niOO1i10i); + wire_niOli1O_dataout <= wire_niOO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOli1Oi_dataout <= niOl11ll AND NOT(niOO1i10i); + wire_niOli1Ol_dataout <= niOl11lO AND NOT(niOO1i10i); + wire_niOli1OO_dataout <= niOl11Oi AND NOT(niOO1i10i); + wire_niOlii1i_dataout <= wire_niOlii1l_o(2) WHEN niOlii1O = '1' ELSE niOl10Oi; + wire_niOliii_dataout <= wire_niOO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliil_dataout <= wire_niOO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliiO_dataout <= wire_niOO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOlili_dataout <= wire_niOO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOlill_dataout <= wire_niOO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOlilO_dataout <= wire_niOO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliOi_dataout <= wire_niOO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliOl_dataout <= niOiil1O WHEN niOO0ll0i = '1' ELSE niOi01O; + wire_niOliOll_dataout <= wire_niOllO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliOlO_dataout <= wire_niOlli1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliOO_dataout <= niOi1lOl WHEN niOO0ll0i = '1' ELSE niOi00i; + wire_niOliOOi_dataout <= wire_niOlli0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliOOl_dataout <= wire_niOlli0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOliOOO_dataout <= wire_niOlli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll00i_dataout <= wire_niOlllli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll00l_dataout <= wire_niOlllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll00O_dataout <= wire_niOllllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll01i_dataout <= wire_niOlllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll01l_dataout <= wire_niOlllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll01O_dataout <= wire_niOllliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0i_dataout <= niOi1O1O WHEN niOO0ll0i = '1' ELSE niOi0il; + wire_niOll0ii_dataout <= wire_niOlllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0il_dataout <= wire_niOlllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0iO_dataout <= wire_niOlllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0l_dataout <= niOi1O0i WHEN niOO0ll0i = '1' ELSE niOi0iO; + wire_niOll0li_dataout <= wire_niOllO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0ll_dataout <= wire_niOllO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0lO_dataout <= wire_niOllO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0O_dataout <= niOi1O0l WHEN niOO0ll0i = '1' ELSE niOi0li; + wire_niOll0Oi_dataout <= wire_niOllO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0Ol_dataout <= wire_niOllO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll0OO_dataout <= wire_niOllOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll10i_dataout <= wire_niOllili_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll10l_dataout <= wire_niOllill_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll10O_dataout <= wire_niOllilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll11i_dataout <= wire_niOlliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll11l_dataout <= wire_niOlliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll11O_dataout <= wire_niOlliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1i_dataout <= niOi1lOO WHEN niOO0ll0i = '1' ELSE niOi00l; + wire_niOll1ii_dataout <= wire_niOlliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1il_dataout <= wire_niOlliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1iO_dataout <= wire_niOlliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1l_dataout <= niOi1O1i WHEN niOO0ll0i = '1' ELSE niOi00O; + wire_niOll1li_dataout <= wire_niOlll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1ll_dataout <= wire_niOlll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1lO_dataout <= wire_niOlll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1O_dataout <= niOi1O1l WHEN niOO0ll0i = '1' ELSE niOi0ii; + wire_niOll1Oi_dataout <= wire_niOlll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1Ol_dataout <= wire_niOlll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOll1OO_dataout <= wire_niOlll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOlli0i_dataout <= niOO1i10O WHEN niOO0lili = '1' ELSE wire_niOllOOl_dataout; + wire_niOlli0l_dataout <= niOO1i1ii WHEN niOO0lili = '1' ELSE wire_niOllOOO_dataout; + wire_niOlli0O_dataout <= niOO1i1il WHEN niOO0lili = '1' ELSE wire_niOlO11i_dataout; + wire_niOlli1i_dataout <= wire_niOllOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOlli1l_dataout <= wire_niOllOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOlli1O_dataout <= niOO1i10l WHEN niOO0lili = '1' ELSE wire_niOllOOi_dataout; + wire_niOllii_dataout <= niOi1O0O WHEN niOO0ll0i = '1' ELSE niOi0ll; + wire_niOlliii_dataout <= niOO1i1iO WHEN niOO0lili = '1' ELSE wire_niOlO11l_dataout; + wire_niOlliil_dataout <= niOO1i1li WHEN niOO0lili = '1' ELSE wire_niOlO11O_dataout; + wire_niOlliiO_dataout <= niOO1i1ll WHEN niOO0lili = '1' ELSE wire_niOlO10i_dataout; + wire_niOllil_dataout <= niOi1Oii WHEN niOO0ll0i = '1' ELSE niOi0lO; + wire_niOllili_dataout <= niOO1i1lO WHEN niOO0lili = '1' ELSE wire_niOlO10l_dataout; + wire_niOllill_dataout <= niOO1i1Oi WHEN niOO0lili = '1' ELSE wire_niOlO10O_dataout; + wire_niOllilO_dataout <= niOO1i1Ol WHEN niOO0lili = '1' ELSE wire_niOlO1ii_dataout; + wire_niOlliO_dataout <= niOi1Oil WHEN niOO0ll0i = '1' ELSE niOi0Oi; + wire_niOlliOi_dataout <= niOO1i1OO WHEN niOO0lili = '1' ELSE wire_niOlO1il_dataout; + wire_niOlliOl_dataout <= niOO1i01i WHEN niOO0lili = '1' ELSE wire_niOlO1iO_dataout; + wire_niOlliOO_dataout <= niOO1i01l WHEN niOO0lili = '1' ELSE wire_niOlO1li_dataout; + wire_niOlll0i_dataout <= niOO1i00O WHEN niOO0lili = '1' ELSE wire_niOlO1Ol_dataout; + wire_niOlll0l_dataout <= niOO1i0ii WHEN niOO0lili = '1' ELSE wire_niOlO1OO_dataout; + wire_niOlll0O_dataout <= niOO1i0il WHEN niOO0lili = '1' ELSE wire_niOlO01i_dataout; + wire_niOlll1i_dataout <= niOO1i01O WHEN niOO0lili = '1' ELSE wire_niOlO1ll_dataout; + wire_niOlll1l_dataout <= niOO1i00i WHEN niOO0lili = '1' ELSE wire_niOlO1lO_dataout; + wire_niOlll1O_dataout <= niOO1i00l WHEN niOO0lili = '1' ELSE wire_niOlO1Oi_dataout; + wire_niOllli_dataout <= niOi1OiO WHEN niOO0ll0i = '1' ELSE niOi0Ol; + wire_niOlllii_dataout <= niOO1i0iO WHEN niOO0lili = '1' ELSE wire_niOlO01l_dataout; + wire_niOlllil_dataout <= niOO1i0li WHEN niOO0lili = '1' ELSE wire_niOlO01O_dataout; + wire_niOllliO_dataout <= niOO1i0ll WHEN niOO0lili = '1' ELSE wire_niOlO00i_dataout; + wire_niOllll_dataout <= niOi1Oli WHEN niOO0ll0i = '1' ELSE niOi0OO; + wire_niOlllli_dataout <= niOO1i0lO WHEN niOO0lili = '1' ELSE wire_niOlO00l_dataout; + wire_niOlllll_dataout <= niOO1i0Oi WHEN niOO0lili = '1' ELSE wire_niOlO00O_dataout; + wire_niOllllO_dataout <= niOO1i0Ol WHEN niOO0lili = '1' ELSE wire_niOlO0ii_dataout; + wire_niOlllO_dataout <= niOi1Oll WHEN niOO0ll0i = '1' ELSE niOii1i; + wire_niOlllOi_dataout <= niOO1i0OO WHEN niOO0lili = '1' ELSE wire_niOlO0il_dataout; + wire_niOlllOl_dataout <= niOO1ii1i WHEN niOO0lili = '1' ELSE wire_niOlO0iO_dataout; + wire_niOlllOO_dataout <= niOO1ii1l WHEN niOO0lili = '1' ELSE wire_niOlO0li_dataout; + wire_niOllO0i_dataout <= niOO1ii0O WHEN niOO0lili = '1' ELSE wire_niOlO0Ol_dataout; + wire_niOllO0l_dataout <= wire_niOlO0OO_dataout OR niOO0lili; + wire_niOllO0O_dataout <= wire_niOlOi1i_dataout OR niOO0lili; + wire_niOllO1i_dataout <= niOO1ii1O WHEN niOO0lili = '1' ELSE wire_niOlO0ll_dataout; + wire_niOllO1l_dataout <= niOO1ii0i WHEN niOO0lili = '1' ELSE wire_niOlO0lO_dataout; + wire_niOllO1O_dataout <= niOO1ii0l WHEN niOO0lili = '1' ELSE wire_niOlO0Oi_dataout; + wire_niOllOi_dataout <= niOi1OlO WHEN niOO0ll0i = '1' ELSE niOii1l; + wire_niOllOii_dataout <= wire_niOllOli_dataout AND NOT(niOO0lili); + wire_niOllOil_dataout <= wire_niOllOll_dataout AND NOT(niOO0lili); + wire_niOllOiO_dataout <= wire_niOllOlO_dataout AND NOT(niOO0lili); + wire_niOllOl_dataout <= niOi1OOi WHEN niOO0ll0i = '1' ELSE niOii1O; + wire_niOllOli_dataout <= niOliOil WHEN niOO1iiii = '1' ELSE wire_niOlOi1l_dataout; + wire_niOllOll_dataout <= niOliOiO WHEN niOO1iiii = '1' ELSE wire_niOlOi1O_dataout; + wire_niOllOlO_dataout <= niOliOli WHEN niOO1iiii = '1' ELSE wire_niOlOi0i_dataout; + wire_niOllOO_dataout <= niOi1OOl WHEN niOO0ll0i = '1' ELSE niOii0i; + wire_niOllOOi_dataout <= niOlii0l AND NOT(niOO1iiii); + wire_niOllOOl_dataout <= niOlii0O AND NOT(niOO1iiii); + wire_niOllOOO_dataout <= niOliiii AND NOT(niOO1iiii); + wire_niOlO00i_dataout <= niOlilll AND NOT(niOO1iiii); + wire_niOlO00l_dataout <= niOlillO AND NOT(niOO1iiii); + wire_niOlO00O_dataout <= niOlilOi AND NOT(niOO1iiii); + wire_niOlO01i_dataout <= niOlilil AND NOT(niOO1iiii); + wire_niOlO01l_dataout <= niOliliO AND NOT(niOO1iiii); + wire_niOlO01O_dataout <= niOlilli AND NOT(niOO1iiii); + wire_niOlO0i_dataout <= niOi011O WHEN niOO0ll0i = '1' ELSE niOiiil; + wire_niOlO0ii_dataout <= niOlilOl AND NOT(niOO1iiii); + wire_niOlO0il_dataout <= niOlilOO AND NOT(niOO1iiii); + wire_niOlO0iO_dataout <= niOliO1i AND NOT(niOO1iiii); + wire_niOlO0l_dataout <= niOi010i WHEN niOO0ll0i = '1' ELSE niOiiiO; + wire_niOlO0li_dataout <= niOliO1l AND NOT(niOO1iiii); + wire_niOlO0ll_dataout <= niOliO1O AND NOT(niOO1iiii); + wire_niOlO0lO_dataout <= niOliO0i AND NOT(niOO1iiii); + wire_niOlO0O_dataout <= niOi010l WHEN niOO0ll0i = '1' ELSE niOiili; + wire_niOlO0Oi_dataout <= niOliO0l AND NOT(niOO1iiii); + wire_niOlO0Ol_dataout <= niOliO0O AND NOT(niOO1iiii); + wire_niOlO0OO_dataout <= niOliOii AND NOT(niOO1iiii); + wire_niOlO10i_dataout <= niOliill AND NOT(niOO1iiii); + wire_niOlO10l_dataout <= niOliilO AND NOT(niOO1iiii); + wire_niOlO10O_dataout <= niOliiOi AND NOT(niOO1iiii); + wire_niOlO11i_dataout <= niOliiil AND NOT(niOO1iiii); + wire_niOlO11l_dataout <= niOliiiO AND NOT(niOO1iiii); + wire_niOlO11O_dataout <= niOliili AND NOT(niOO1iiii); + wire_niOlO1i_dataout <= niOi1OOO WHEN niOO0ll0i = '1' ELSE niOii0l; + wire_niOlO1ii_dataout <= niOliiOl AND NOT(niOO1iiii); + wire_niOlO1il_dataout <= niOliiOO AND NOT(niOO1iiii); + wire_niOlO1iO_dataout <= niOlil1i AND NOT(niOO1iiii); + wire_niOlO1l_dataout <= niOi011i WHEN niOO0ll0i = '1' ELSE niOii0O; + wire_niOlO1li_dataout <= niOlil1l AND NOT(niOO1iiii); + wire_niOlO1ll_dataout <= niOlil1O AND NOT(niOO1iiii); + wire_niOlO1lO_dataout <= niOlil0i AND NOT(niOO1iiii); + wire_niOlO1O_dataout <= niOi011l WHEN niOO0ll0i = '1' ELSE niOiiii; + wire_niOlO1Oi_dataout <= niOlil0l AND NOT(niOO1iiii); + wire_niOlO1Ol_dataout <= niOlil0O AND NOT(niOO1iiii); + wire_niOlO1OO_dataout <= niOlilii AND NOT(niOO1iiii); + wire_niOlOi0i_dataout <= wire_niOlOi0l_o(2) WHEN niOlOi0O = '1' ELSE niOliOli; + wire_niOlOi1i_dataout <= niOlOi0O AND NOT(niOO1iiii); + wire_niOlOi1l_dataout <= wire_niOlOi0l_o(0) WHEN niOlOi0O = '1' ELSE niOliOil; + wire_niOlOi1O_dataout <= wire_niOlOi0l_o(1) WHEN niOlOi0O = '1' ELSE niOliOiO; + wire_niOlOii_dataout <= niOi010O WHEN niOO0ll0i = '1' ELSE niOiill; + wire_niOlOiil_dataout <= wire_niOlOiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOlOiiO_dataout <= wire_nl1000i_w_lg_niOlOill8545w(0) WHEN (niOlOl1O XOR niOlOl1i) = '1' ELSE niOlOill; + wire_niOlOil_dataout <= niOi01ii WHEN niOO0ll0i = '1' ELSE niOiilO; + wire_niOlOiO_dataout <= niOi01il WHEN niOO0ll0i = '1' ELSE niOiiOi; + wire_niOlOiOi_dataout <= niOlOl1i AND NOT(wire_niO01l0O_dataout); + wire_niOlOiOO_dataout <= niOlOiii AND NOT(wire_niO01l0O_dataout); + wire_niOlOl0l_dataout <= niOlOl1O AND NOT(wire_niO01O0O_dataout); + wire_niOlOl0O_dataout <= niOlOiOl AND NOT(wire_niO01O0O_dataout); + wire_niOlOl1l_dataout <= niOlOl0i AND NOT(wire_niO01O0O_dataout); + wire_niOlOli_dataout <= niOi01iO WHEN niOO0ll0i = '1' ELSE niOiiOl; + wire_niOlOlil_dataout <= wire_niOlOlli_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOlOliO_dataout <= wire_niOlOlOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOlOll_dataout <= niOi01li WHEN niOO0ll0i = '1' ELSE niOiiOO; + wire_niOlOlli_dataout <= wire_niOOO0O_w_lg_niOlOl0i8541w(0) WHEN (wire_w_lg_niOO1iiil8542w(0) AND (cpl_pending XOR niOlOlii)) = '1' ELSE niOlOl0i; + wire_niOlOlO_dataout <= niOi01ll WHEN niOO0ll0i = '1' ELSE niOil1i; + wire_niOlOlOi_dataout <= niOlOlii WHEN niOO1iiil = '1' ELSE cpl_pending; + wire_niOlOO0l_dataout <= niOlOOil AND NOT(wire_niO01l0O_dataout); + wire_niOlOO1i_dataout <= (niOlOOli XOR niOlOOil) AND NOT(wire_niO01O0O_dataout); + wire_niOlOOi_dataout <= niOi01lO WHEN niOO0ll0i = '1' ELSE niOil1l; + wire_niOlOOii_dataout <= niOlOlOO AND NOT(wire_niO01l0O_dataout); + wire_niOlOOiO_dataout <= niOlOOll AND NOT(wire_niO01O0O_dataout); + wire_niOlOOl_dataout <= niOi01Oi WHEN niOO0ll0i = '1' ELSE niOil1O; + wire_niOlOOlO_dataout <= niOlOOli AND NOT(wire_niO01O0O_dataout); + wire_niOlOOO_dataout <= niOi01Ol WHEN niOO0ll0i = '1' ELSE niOil0i; + wire_niOlOOOi_dataout <= niOlOO0O AND NOT(wire_niO01O0O_dataout); + wire_niOlOOOO_dataout <= wire_niOO111l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO000l_dataout <= niOO01il AND NOT(wire_niO01l0O_dataout); + wire_niOO001O_dataout <= niOO000O AND NOT(wire_niO01l0O_dataout); + wire_niOO00ii_dataout <= niOO00iO AND NOT(wire_niO01O0O_dataout); + wire_niOO00li_dataout <= niOO00il AND NOT(wire_niO01O0O_dataout); + wire_niOO00ll_dataout <= niOO000i AND NOT(wire_niO01O0O_dataout); + wire_niOO00OO_dataout <= wire_niOO0i0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO01i_dataout <= niOi00lO AND niOO0ll0i; + wire_niOO01iO_dataout <= wire_niOO01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOO01l_dataout <= niOi00Oi AND niOO0ll0i; + wire_niOO01li_dataout <= wire_niOO01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOO01ll_dataout <= wire_niOO01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOO01lO_dataout <= niOO00lO WHEN niOO1iiOi = '1' ELSE niOO001i; + wire_niOO01Oi_dataout <= niOO00Oi WHEN niOO1iiOi = '1' ELSE niOO010O; + wire_niOO01Ol_dataout <= niOO00Ol WHEN niOO1iiOi = '1' ELSE niOO01ii; + wire_niOO0i0i_dataout <= wire_niOOO0O_w_lg_niOO00iO8496w(0) WHEN (wire_w_lg_niOO1iiOl8493w(0) AND (NOT (((NOT (cpl_err(4) XOR niOO00lO)) AND (NOT (cpl_err(5) XOR niOO00Oi))) AND (NOT (cpl_err(6) XOR niOO00Ol))))) = '1' ELSE niOO00iO; + wire_niOO0i0O_dataout <= cpl_err(4) WHEN wire_w_lg_niOO1iiOl8493w(0) = '1' ELSE niOO00lO; + wire_niOO0i1i_dataout <= wire_niOO0i0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0i1l_dataout <= wire_niOO0iii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0i1O_dataout <= wire_niOO0iil_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0iii_dataout <= cpl_err(5) WHEN wire_w_lg_niOO1iiOl8493w(0) = '1' ELSE niOO00Oi; + wire_niOO0iil_dataout <= cpl_err(6) WHEN wire_w_lg_niOO1iiOl8493w(0) = '1' ELSE niOO00Ol; + wire_niOO0iOl_dataout <= (niOO0lil XOR niOO0l0O) AND NOT(wire_niO01l0O_dataout); + wire_niOO0l0l_dataout <= niOO0iOi AND NOT(wire_niO01O0O_dataout); + wire_niOO0l1O_dataout <= niOO0l0O AND NOT(wire_niO01O0O_dataout); + wire_niOO0lii_dataout <= niOO0liO AND NOT(wire_niO01l0O_dataout); + wire_niOO0lli_dataout <= niOO0lil AND NOT(wire_niO01l0O_dataout); + wire_niOO0lll_dataout <= niOO0l0i AND NOT(wire_niO01l0O_dataout); + wire_niOO0lOi_dataout <= wire_niOO0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOO0lOl_dataout <= wire_niOO0O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOO0lOO_dataout <= wire_nl1000i_w_lg_niOO0liO8485w(0) WHEN (wire_nlOilOO1O_dataout AND (wire_w_lg_niOO1iiOO8486w(0) AND (wire_nlOilOO1O_dataout XOR niOO0llO))) = '1' ELSE niOO0liO; + wire_niOO0O0i_dataout <= niOO0llO WHEN niOO1iiOO = '1' ELSE wire_nlOilOO1O_dataout; + wire_niOO0Oii_dataout <= (niOOi11i XOR niOO0OOl) AND NOT(wire_niO01l0O_dataout); + wire_niOO0Oiii_dataout <= wire_niOO0OiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_niOO0Oiil_dataout <= wire_niOO0OiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_niOO0OiiO_dataout <= wire_niOO0Ol1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niOO0Oili_dataout <= wire_niOO0Ol1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niOO0Oill_dataout <= wire_niOO0Ol1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_niOO0OilO_dataout <= wire_niOO0Ol0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_niOO0OiOi_dataout <= wire_niOO0Ol0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_niOO0OiOl_dataout <= niOO0OO1O WHEN niOi11ill = '1' ELSE niOO0Olii; + wire_niOO0OiOO_dataout <= niOO0OO0i WHEN niOi11ill = '1' ELSE niOO0O0OO; + wire_niOO0Ol0i_dataout <= niOO0OOil WHEN niOi11ill = '1' ELSE niOO0Oi0i; + wire_niOO0Ol0l_dataout <= niOO0OOiO WHEN niOi11ill = '1' ELSE niOO0Oi0l; + wire_niOO0Ol1i_dataout <= niOO0OO0l WHEN niOi11ill = '1' ELSE niOO0Oi1i; + wire_niOO0Ol1l_dataout <= niOO0OO0O WHEN niOi11ill = '1' ELSE niOO0Oi1l; + wire_niOO0Ol1O_dataout <= niOO0OOii WHEN niOi11ill = '1' ELSE niOO0Oi1O; + wire_niOO0OliO_dataout <= niOO0OllO AND NOT(wire_niO01l0O_dataout); + wire_niOO0Oll_dataout <= niOO0OOl AND NOT(wire_niO01O0O_dataout); + wire_niOO0Olll_dataout <= niOO0Oi0O AND NOT(wire_niO01l0O_dataout); + wire_niOO0OlOi_dataout <= niOO0OlOO AND NOT(wire_niO01lOO_dataout); + wire_niOO0OO1i_dataout <= niOO0OlOl AND NOT(wire_niO01lOO_dataout); + wire_niOO0OO1l_dataout <= niOO0Olli AND NOT(wire_niO01lOO_dataout); + wire_niOO0OOi_dataout <= niOO0O0O AND NOT(wire_niO01O0O_dataout); + wire_niOO0OOli_dataout <= wire_niOOi111O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0OOll_dataout <= wire_niOOi110l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0OOlO_dataout <= wire_niOOi110O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0OOO_dataout <= niOOi11l AND NOT(wire_niO01l0O_dataout); + wire_niOO0OOOi_dataout <= wire_niOOi11ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0OOOl_dataout <= wire_niOOi11il_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO0OOOO_dataout <= wire_niOOi11iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO100l_dataout <= niOO101O AND NOT(wire_niO01O0O_dataout); + wire_niOO100O_dataout <= niOO11Ol AND NOT(wire_niO01O0O_dataout); + wire_niOO101l_dataout <= niOO100i AND NOT(wire_niO01O0O_dataout); + wire_niOO10i_dataout <= niOi001O WHEN niOO0ll0i = '1' ELSE niOilil; + wire_niOO10il_dataout <= wire_niOO10li_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO10iO_dataout <= wire_niOO10Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO10l_dataout <= niOi000i WHEN niOO0ll0i = '1' ELSE niOiliO; + wire_niOO10li_dataout <= wire_niOOO0O_w_lg_niOO100i8526w(0) WHEN wire_w_lg_w_cpl_err_range8525w8530w(0) = '1' ELSE niOO100i; + wire_niOO10O_dataout <= niOi000l WHEN niOO0ll0i = '1' ELSE niOilli; + wire_niOO10Ol_dataout <= niOO10ii WHEN niOO1iili = '1' ELSE cpl_err(1); + wire_niOO110O_dataout <= niOlOOOl WHEN niOO1iiiO = '1' ELSE cpl_err(0); + wire_niOO111i_dataout <= wire_niOO110O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO111l_dataout <= wire_niOOO0O_w_lg_niOlOOll8534w(0) WHEN wire_w_lg_w_cpl_err_range8533w8538w(0) = '1' ELSE niOlOOll; + wire_niOO11i_dataout <= niOi01OO WHEN niOO0ll0i = '1' ELSE niOil0l; + wire_niOO11iO_dataout <= (niOO101O XOR niOO101i) AND NOT(wire_niO01O0O_dataout); + wire_niOO11l_dataout <= niOi001i WHEN niOO0ll0i = '1' ELSE niOil0O; + wire_niOO11O_dataout <= niOi001l WHEN niOO0ll0i = '1' ELSE niOilii; + wire_niOO11Oi_dataout <= niOO101i AND NOT(wire_niO01l0O_dataout); + wire_niOO11OO_dataout <= niOO11il AND NOT(wire_niO01l0O_dataout); + wire_niOO1i0O_dataout <= niOO1iiO AND NOT(wire_niO01l0O_dataout); + wire_niOO1i1l_dataout <= (niOO1ill XOR niOO1iiO) AND NOT(wire_niO01O0O_dataout); + wire_niOO1ii_dataout <= niOi000O WHEN niOO0ll0i = '1' ELSE niOilll; + wire_niOO1iil_dataout <= niOO1i1i AND NOT(wire_niO01l0O_dataout); + wire_niOO1il_dataout <= niOi00ii WHEN niOO0ll0i = '1' ELSE niOillO; + wire_niOO1ili_dataout <= niOO1ilO AND NOT(wire_niO01O0O_dataout); + wire_niOO1iO_dataout <= niOi00il WHEN niOO0ll0i = '1' ELSE niOilOi; + wire_niOO1iOi_dataout <= niOO1ill AND NOT(wire_niO01O0O_dataout); + wire_niOO1iOl_dataout <= niOO1iii AND NOT(wire_niO01O0O_dataout); + wire_niOO1l1i_dataout <= wire_niOO1l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO1l1l_dataout <= wire_niOO1lii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO1l1O_dataout <= wire_niOOO0O_w_lg_niOO1ilO8518w(0) WHEN wire_w_lg_w_cpl_err_range8517w8522w(0) = '1' ELSE niOO1ilO; + wire_niOO1li_dataout <= niOi00iO WHEN niOO0ll0i = '1' ELSE niOilOl; + wire_niOO1lii_dataout <= niOO1iOO WHEN niOO1iill = '1' ELSE cpl_err(2); + wire_niOO1ll_dataout <= niOi00li WHEN niOO0ll0i = '1' ELSE niOilOO; + wire_niOO1lli_dataout <= (niOO1O0i XOR niOO1O1l) AND NOT(wire_niO01O0O_dataout); + wire_niOO1lO_dataout <= niOi00ll WHEN niOO0ll0i = '1' ELSE niOiO1i; + wire_niOO1lOl_dataout <= niOO1O1l AND NOT(wire_niO01l0O_dataout); + wire_niOO1O0O_dataout <= niOO1O0i AND NOT(wire_niO01O0O_dataout); + wire_niOO1O1i_dataout <= niOO1liO AND NOT(wire_niO01l0O_dataout); + wire_niOO1O1O_dataout <= niOO1O0l AND NOT(wire_niO01O0O_dataout); + wire_niOO1Oi_dataout <= niOiO1l AND NOT(niOO0ll0i); + wire_niOO1Oii_dataout <= niOO1lOO AND NOT(wire_niO01O0O_dataout); + wire_niOO1OiO_dataout <= wire_niOO1Oll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO1Ol_dataout <= niOiO1O AND NOT(niOO0ll0i); + wire_niOO1Oli_dataout <= wire_niOO1OOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOO1Oll_dataout <= wire_niOOO0O_w_lg_niOO1O0l8510w(0) WHEN wire_w_lg_w_cpl_err_range8509w8514w(0) = '1' ELSE niOO1O0l; + wire_niOO1OO_dataout <= niOiO0i AND NOT(niOO0ll0i); + wire_niOO1OOO_dataout <= niOO1Oil WHEN niOO1iilO = '1' ELSE cpl_err(3); + wire_niOOi001l_dataout <= niOOi01OO AND NOT(wire_niO01O0O_dataout); + wire_niOOi001O_dataout <= niOOi01ll AND NOT(wire_niO01O0O_dataout); + wire_niOOi00i_dataout <= niOOi0ii AND NOT(wire_niO01O0O_dataout); + wire_niOOi00O_dataout <= niOOi1Ol AND NOT(wire_niO01O0O_dataout); + wire_niOOi010i_dataout <= niOOi0i1O WHEN niOi11iOl = '1' ELSE niOOi1iOl; + wire_niOOi010l_dataout <= niOOi0i0i WHEN niOi11iOl = '1' ELSE niOOi1iOO; + wire_niOOi010O_dataout <= niOOi0i0l WHEN niOi11iOl = '1' ELSE niOOi1l1i; + wire_niOOi011i_dataout <= niOOi00OO WHEN niOi11iOl = '1' ELSE niOOi1ill; + wire_niOOi011l_dataout <= niOOi0i1i WHEN niOi11iOl = '1' ELSE niOOi1ilO; + wire_niOOi011O_dataout <= niOOi0i1l WHEN niOi11iOl = '1' ELSE niOOi1iOi; + wire_niOOi01li_dataout <= niOOi01Oi AND NOT(wire_niO01l0O_dataout); + wire_niOOi01lO_dataout <= niOOi1l1l AND NOT(wire_niO01l0O_dataout); + wire_niOOi01Ol_dataout <= niOOi001i AND NOT(wire_niO01O0O_dataout); + wire_niOOi0i0O_dataout <= wire_niOOi0liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0iii_dataout <= wire_niOOi0lll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0iil_dataout <= wire_niOOi0llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0iiO_dataout <= wire_niOOi0lOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0il_dataout <= niOOi0li AND NOT(wire_niO01l0O_dataout); + wire_niOOi0ili_dataout <= wire_niOOi0lOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0ill_dataout <= wire_niOOi0lOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0ilO_dataout <= wire_niOOi0O1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0iOi_dataout <= wire_niOOi0O1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0iOl_dataout <= wire_niOOi0O1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0iOO_dataout <= wire_niOOi0O0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0l0i_dataout <= wire_niOOi0Oil_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0l0l_dataout <= wire_niOOi0OiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0l0O_dataout <= wire_niOOi0Oli_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0l1i_dataout <= wire_niOOi0O0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0l1l_dataout <= wire_niOOi0O0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0l1O_dataout <= wire_niOOi0Oii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0lii_dataout <= wire_niOOi0Oll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0lil_dataout <= wire_niOOi0OlO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi0liO_dataout <= wire_niOOO0O_w_lg_niOOi001i61782w(0) WHEN (wire_w_lg_niOi11l1i61765w(0) AND wire_w_lg_niOi11iOO61783w(0)) = '1' ELSE niOOi001i; + wire_niOOi0ll_dataout <= niOOi0iO AND NOT(wire_niO01l0O_dataout); + wire_niOOi0lll_dataout <= test_in_hip(4) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi000i; + wire_niOOi0llO_dataout <= test_in_hip(7) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi000l; + wire_niOOi0lO_dataout <= niOOi00l AND NOT(wire_niO01l0O_dataout); + wire_niOOi0lOi_dataout <= test_in_hip(16) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi000O; + wire_niOOi0lOl_dataout <= test_in_hip(17) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00ii; + wire_niOOi0lOO_dataout <= test_in_hip(18) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00il; + wire_niOOi0O0i_dataout <= test_in_hip(22) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00lO; + wire_niOOi0O0l_dataout <= test_in_hip(23) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00Oi; + wire_niOOi0O0O_dataout <= test_in_hip(24) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00Ol; + wire_niOOi0O1i_dataout <= test_in_hip(19) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00iO; + wire_niOOi0O1l_dataout <= test_in_hip(20) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00li; + wire_niOOi0O1O_dataout <= test_in_hip(21) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00ll; + wire_niOOi0Oii_dataout <= test_in_hip(25) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi00OO; + wire_niOOi0Oil_dataout <= test_in_hip(26) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi0i1i; + wire_niOOi0OiO_dataout <= test_in_hip(27) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi0i1l; + wire_niOOi0Ol_dataout <= wire_niOOii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi0Oli_dataout <= test_in_hip(28) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi0i1O; + wire_niOOi0Oll_dataout <= test_in_hip(29) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi0i0i; + wire_niOOi0OlO_dataout <= test_in_hip(30) WHEN wire_w_lg_niOi11l1i61765w(0) = '1' ELSE niOOi0i0l; + wire_niOOi0OO_dataout <= wire_niOOii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi10i_dataout <= niOO0OlO AND NOT(wire_niO01l0O_dataout); + wire_niOOi10O_dataout <= wire_niOOi1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi110l_dataout <= test_in_hip(0) WHEN wire_w_lg_niOi11iOi61838w(0) = '1' ELSE niOO0OO1O; + wire_niOOi110O_dataout <= test_in_hip(1) WHEN wire_w_lg_niOi11iOi61838w(0) = '1' ELSE niOO0OO0i; + wire_niOOi111i_dataout <= wire_niOOi11li_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi111l_dataout <= wire_niOOi11ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOi111O_dataout <= wire_niOOO0O_w_lg_niOO0OlOO61845w(0) WHEN (wire_w_lg_niOi11iOi61838w(0) AND wire_w_lg_niOi11ilO61846w(0)) = '1' ELSE niOO0OlOO; + wire_niOOi11ii_dataout <= test_in_hip(2) WHEN wire_w_lg_niOi11iOi61838w(0) = '1' ELSE niOO0OO0l; + wire_niOOi11il_dataout <= test_in_hip(3) WHEN wire_w_lg_niOi11iOi61838w(0) = '1' ELSE niOO0OO0O; + wire_niOOi11iO_dataout <= test_in_hip(5) WHEN wire_w_lg_niOi11iOi61838w(0) = '1' ELSE niOO0OOii; + wire_niOOi11li_dataout <= test_in_hip(6) WHEN wire_w_lg_niOi11iOi61838w(0) = '1' ELSE niOO0OOil; + wire_niOOi11ll_dataout <= test_in_hip(31) WHEN wire_w_lg_niOi11iOi61838w(0) = '1' ELSE niOO0OOiO; + wire_niOOi11O_dataout <= niOOi11i AND NOT(wire_niO01l0O_dataout); + wire_niOOi1ii_dataout <= wire_niOOi1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1il_dataout <= wire_nl1000i_w_lg_niOOi11l8478w(0) WHEN (wire_nlOilOiiO_dataout AND (wire_w_lg_niOO1il1i8479w(0) AND (wire_nlOilOiiO_dataout XOR niOOi10l))) = '1' ELSE niOOi11l; + wire_niOOi1l0i_dataout <= wire_niOOi1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1l0l_dataout <= wire_niOOi1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1l0O_dataout <= wire_niOOi1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1l1O_dataout <= wire_niOOi1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1lii_dataout <= wire_niOOi1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1lil_dataout <= wire_niOOi1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1liO_dataout <= wire_niOOi1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1lli_dataout <= wire_niOOi1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1lll_dataout <= wire_niOOi1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1llO_dataout <= wire_niOOi1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1lO_dataout <= niOOi10l WHEN niOO1il1i = '1' ELSE wire_nlOilOiiO_dataout; + wire_niOOi1lOi_dataout <= wire_niOOi1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1lOl_dataout <= wire_niOOi011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1lOO_dataout <= wire_niOOi011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1O0i_dataout <= wire_niOOi010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1O0l_dataout <= niOOi000i WHEN niOi11iOl = '1' ELSE niOOi01il; + wire_niOOi1O0O_dataout <= niOOi000l WHEN niOi11iOl = '1' ELSE niOOi1i1i; + wire_niOOi1O1i_dataout <= wire_niOOi011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1O1l_dataout <= wire_niOOi010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1O1O_dataout <= wire_niOOi010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOi1Oii_dataout <= niOOi000O WHEN niOi11iOl = '1' ELSE niOOi1i1l; + wire_niOOi1Oil_dataout <= niOOi00ii WHEN niOi11iOl = '1' ELSE niOOi1i1O; + wire_niOOi1OiO_dataout <= niOOi00il WHEN niOi11iOl = '1' ELSE niOOi1i0i; + wire_niOOi1Oli_dataout <= niOOi00iO WHEN niOi11iOl = '1' ELSE niOOi1i0l; + wire_niOOi1Oll_dataout <= niOOi00li WHEN niOi11iOl = '1' ELSE niOOi1i0O; + wire_niOOi1OlO_dataout <= niOOi00ll WHEN niOi11iOl = '1' ELSE niOOi1iii; + wire_niOOi1OO_dataout <= (niOOi0iO XOR niOOi0ii) AND NOT(wire_niO01l0O_dataout); + wire_niOOi1OOi_dataout <= niOOi00lO WHEN niOi11iOl = '1' ELSE niOOi1iil; + wire_niOOi1OOl_dataout <= niOOi00Oi WHEN niOi11iOl = '1' ELSE niOOi1iiO; + wire_niOOi1OOO_dataout <= niOOi00Ol WHEN niOi11iOl = '1' ELSE niOOi1ili; + wire_niOOii00i_dataout <= rxdata1(2) WHEN niOi11lil = '1' ELSE wire_niOOiiiii_dataout; + wire_niOOii00l_dataout <= rxdata1(3) WHEN niOi11lil = '1' ELSE wire_niOOiiiil_dataout; + wire_niOOii00O_dataout <= rxdata1(4) WHEN niOi11lil = '1' ELSE wire_niOOiiiiO_dataout; + wire_niOOii01l_dataout <= rxdata1(0) WHEN niOi11lil = '1' ELSE wire_niOOiii0l_dataout; + wire_niOOii01O_dataout <= rxdata1(1) WHEN niOi11lil = '1' ELSE wire_niOOiii0O_dataout; + wire_niOOii0ii_dataout <= rxdata1(5) WHEN niOi11lil = '1' ELSE wire_niOOiiili_dataout; + wire_niOOii0il_dataout <= rxdata1(6) WHEN niOi11lil = '1' ELSE wire_niOOiiill_dataout; + wire_niOOii0iO_dataout <= rxdata1(7) WHEN niOi11lil = '1' ELSE wire_niOOiiilO_dataout; + wire_niOOii0l_dataout <= niOOi0Oi WHEN niOO1il1l = '1' ELSE nli0Oi0OO; + wire_niOOii0li_dataout <= rxdatak1 WHEN niOi11lil = '1' ELSE wire_niOOiiiOi_dataout; + wire_niOOii0ll_dataout <= n010OOil WHEN niOi11lil = '1' ELSE wire_niOOiiiOl_dataout; + wire_niOOii0lO_dataout <= n010OOiO WHEN niOi11lil = '1' ELSE wire_niOOiiiOO_dataout; + wire_niOOii0Oi_dataout <= n010OOli WHEN niOi11lil = '1' ELSE wire_niOOiil1i_dataout; + wire_niOOii0Ol_dataout <= n010OOll WHEN niOi11lil = '1' ELSE wire_niOOiil1l_dataout; + wire_niOOii0OO_dataout <= n010OOlO WHEN niOi11lil = '1' ELSE wire_niOOiil1O_dataout; + wire_niOOii1i_dataout <= wire_nl1000i_w_lg_niOOi0li8471w(0) WHEN (nli0Oi0OO AND (wire_w_lg_niOO1il1l8472w(0) AND (nli0Oi0OO XOR niOOi0Oi))) = '1' ELSE niOOi0li; + wire_niOOiii0i_dataout <= n01i111i WHEN niOi11lil = '1' ELSE wire_niOOiilii_dataout; + wire_niOOiii0l_dataout <= rxdata2(0) WHEN niOi11lii = '1' ELSE wire_niOOiilil_dataout; + wire_niOOiii0O_dataout <= rxdata2(1) WHEN niOi11lii = '1' ELSE wire_niOOiiliO_dataout; + wire_niOOiii1i_dataout <= n010OOOi WHEN niOi11lil = '1' ELSE wire_niOOiil0i_dataout; + wire_niOOiii1l_dataout <= n010OOOl WHEN niOi11lil = '1' ELSE wire_niOOiil0l_dataout; + wire_niOOiii1O_dataout <= n010OOOO WHEN niOi11lil = '1' ELSE wire_niOOiil0O_dataout; + wire_niOOiiiii_dataout <= rxdata2(2) WHEN niOi11lii = '1' ELSE wire_niOOiilli_dataout; + wire_niOOiiiil_dataout <= rxdata2(3) WHEN niOi11lii = '1' ELSE wire_niOOiilll_dataout; + wire_niOOiiiiO_dataout <= rxdata2(4) WHEN niOi11lii = '1' ELSE wire_niOOiillO_dataout; + wire_niOOiiili_dataout <= rxdata2(5) WHEN niOi11lii = '1' ELSE wire_niOOiilOi_dataout; + wire_niOOiiill_dataout <= rxdata2(6) WHEN niOi11lii = '1' ELSE wire_niOOiilOl_dataout; + wire_niOOiiilO_dataout <= rxdata2(7) WHEN niOi11lii = '1' ELSE wire_niOOiilOO_dataout; + wire_niOOiiiOi_dataout <= rxdatak2 WHEN niOi11lii = '1' ELSE wire_niOOiiO1i_dataout; + wire_niOOiiiOl_dataout <= n001iilO WHEN niOi11lii = '1' ELSE wire_niOOiiO1l_dataout; + wire_niOOiiiOO_dataout <= n001iiOi WHEN niOi11lii = '1' ELSE wire_niOOiiO1O_dataout; + wire_niOOiil0i_dataout <= n001il1l WHEN niOi11lii = '1' ELSE wire_niOOiiOii_dataout; + wire_niOOiil0l_dataout <= n001il1O WHEN niOi11lii = '1' ELSE wire_niOOiiOil_dataout; + wire_niOOiil0O_dataout <= n001il0i WHEN niOi11lii = '1' ELSE wire_niOOiiOiO_dataout; + wire_niOOiil1i_dataout <= n001iiOl WHEN niOi11lii = '1' ELSE wire_niOOiiO0i_dataout; + wire_niOOiil1l_dataout <= n001iiOO WHEN niOi11lii = '1' ELSE wire_niOOiiO0l_dataout; + wire_niOOiil1O_dataout <= n001il1i WHEN niOi11lii = '1' ELSE wire_niOOiiO0O_dataout; + wire_niOOiilii_dataout <= n001il0l WHEN niOi11lii = '1' ELSE wire_niOOiiOli_dataout; + wire_niOOiilil_dataout <= rxdata3(0) WHEN niOi11l0O = '1' ELSE wire_niOOiiOll_dataout; + wire_niOOiiliO_dataout <= rxdata3(1) WHEN niOi11l0O = '1' ELSE wire_niOOiiOlO_dataout; + wire_niOOiilli_dataout <= rxdata3(2) WHEN niOi11l0O = '1' ELSE wire_niOOiiOOi_dataout; + wire_niOOiilll_dataout <= rxdata3(3) WHEN niOi11l0O = '1' ELSE wire_niOOiiOOl_dataout; + wire_niOOiillO_dataout <= rxdata3(4) WHEN niOi11l0O = '1' ELSE wire_niOOiiOOO_dataout; + wire_niOOiilOi_dataout <= rxdata3(5) WHEN niOi11l0O = '1' ELSE wire_niOOil11i_dataout; + wire_niOOiilOl_dataout <= rxdata3(6) WHEN niOi11l0O = '1' ELSE wire_niOOil11l_dataout; + wire_niOOiilOO_dataout <= rxdata3(7) WHEN niOi11l0O = '1' ELSE wire_niOOil11O_dataout; + wire_niOOiiO0i_dataout <= n00O101O WHEN niOi11l0O = '1' ELSE wire_niOOil1ii_dataout; + wire_niOOiiO0l_dataout <= n00O100i WHEN niOi11l0O = '1' ELSE wire_niOOil1il_dataout; + wire_niOOiiO0O_dataout <= n00O100l WHEN niOi11l0O = '1' ELSE wire_niOOil1iO_dataout; + wire_niOOiiO1i_dataout <= rxdatak3 WHEN niOi11l0O = '1' ELSE wire_niOOil10i_dataout; + wire_niOOiiO1l_dataout <= n00O101i WHEN niOi11l0O = '1' ELSE wire_niOOil10l_dataout; + wire_niOOiiO1O_dataout <= n00O101l WHEN niOi11l0O = '1' ELSE wire_niOOil10O_dataout; + wire_niOOiiOii_dataout <= n00O100O WHEN niOi11l0O = '1' ELSE wire_niOOil1li_dataout; + wire_niOOiiOil_dataout <= n00O10ii WHEN niOi11l0O = '1' ELSE wire_niOOil1ll_dataout; + wire_niOOiiOiO_dataout <= n00O10il WHEN niOi11l0O = '1' ELSE wire_niOOil1lO_dataout; + wire_niOOiiOli_dataout <= n00O10iO WHEN niOi11l0O = '1' ELSE wire_niOOil1Oi_dataout; + wire_niOOiiOll_dataout <= rxdata4(0) WHEN niOi11l0l = '1' ELSE wire_niOOil1Ol_dataout; + wire_niOOiiOlO_dataout <= rxdata4(1) WHEN niOi11l0l = '1' ELSE wire_niOOil1OO_dataout; + wire_niOOiiOOi_dataout <= rxdata4(2) WHEN niOi11l0l = '1' ELSE wire_niOOil01i_dataout; + wire_niOOiiOOl_dataout <= rxdata4(3) WHEN niOi11l0l = '1' ELSE wire_niOOil01l_dataout; + wire_niOOiiOOO_dataout <= rxdata4(4) WHEN niOi11l0l = '1' ELSE wire_niOOil01O_dataout; + wire_niOOil00i_dataout <= rxdata5(5) WHEN niOi11l0i = '1' ELSE wire_niOOiliii_dataout; + wire_niOOil00l_dataout <= rxdata5(6) WHEN niOi11l0i = '1' ELSE wire_niOOiliil_dataout; + wire_niOOil00O_dataout <= rxdata5(7) WHEN niOi11l0i = '1' ELSE wire_niOOiliiO_dataout; + wire_niOOil01i_dataout <= rxdata5(2) WHEN niOi11l0i = '1' ELSE wire_niOOili0i_dataout; + wire_niOOil01l_dataout <= rxdata5(3) WHEN niOi11l0i = '1' ELSE wire_niOOili0l_dataout; + wire_niOOil01O_dataout <= rxdata5(4) WHEN niOi11l0i = '1' ELSE wire_niOOili0O_dataout; + wire_niOOil0ii_dataout <= rxdatak5 WHEN niOi11l0i = '1' ELSE wire_niOOilili_dataout; + wire_niOOil0il_dataout <= n0l01iiO WHEN niOi11l0i = '1' ELSE wire_niOOilill_dataout; + wire_niOOil0iO_dataout <= n0l01ili WHEN niOi11l0i = '1' ELSE wire_niOOililO_dataout; + wire_niOOil0li_dataout <= n0l01ill WHEN niOi11l0i = '1' ELSE wire_niOOiliOi_dataout; + wire_niOOil0ll_dataout <= n0l01ilO WHEN niOi11l0i = '1' ELSE wire_niOOiliOl_dataout; + wire_niOOil0lO_dataout <= n0l01iOi WHEN niOi11l0i = '1' ELSE wire_niOOiliOO_dataout; + wire_niOOil0Oi_dataout <= n0l01iOl WHEN niOi11l0i = '1' ELSE wire_niOOill1i_dataout; + wire_niOOil0Ol_dataout <= n0l01iOO WHEN niOi11l0i = '1' ELSE wire_niOOill1l_dataout; + wire_niOOil0OO_dataout <= n0l01l1i WHEN niOi11l0i = '1' ELSE wire_niOOill1O_dataout; + wire_niOOil10i_dataout <= rxdatak4 WHEN niOi11l0l = '1' ELSE wire_niOOil0ii_dataout; + wire_niOOil10l_dataout <= n0iiiO0l WHEN niOi11l0l = '1' ELSE wire_niOOil0il_dataout; + wire_niOOil10O_dataout <= n0iiiO0O WHEN niOi11l0l = '1' ELSE wire_niOOil0iO_dataout; + wire_niOOil11i_dataout <= rxdata4(5) WHEN niOi11l0l = '1' ELSE wire_niOOil00i_dataout; + wire_niOOil11l_dataout <= rxdata4(6) WHEN niOi11l0l = '1' ELSE wire_niOOil00l_dataout; + wire_niOOil11O_dataout <= rxdata4(7) WHEN niOi11l0l = '1' ELSE wire_niOOil00O_dataout; + wire_niOOil1ii_dataout <= n0iiiOii WHEN niOi11l0l = '1' ELSE wire_niOOil0li_dataout; + wire_niOOil1il_dataout <= n0iiiOil WHEN niOi11l0l = '1' ELSE wire_niOOil0ll_dataout; + wire_niOOil1iO_dataout <= n0iiiOiO WHEN niOi11l0l = '1' ELSE wire_niOOil0lO_dataout; + wire_niOOil1li_dataout <= n0iiiOli WHEN niOi11l0l = '1' ELSE wire_niOOil0Oi_dataout; + wire_niOOil1ll_dataout <= n0iiiOll WHEN niOi11l0l = '1' ELSE wire_niOOil0Ol_dataout; + wire_niOOil1lO_dataout <= n0iiiOlO WHEN niOi11l0l = '1' ELSE wire_niOOil0OO_dataout; + wire_niOOil1Oi_dataout <= n0iiiOOi WHEN niOi11l0l = '1' ELSE wire_niOOili1i_dataout; + wire_niOOil1Ol_dataout <= rxdata5(0) WHEN niOi11l0i = '1' ELSE wire_niOOili1l_dataout; + wire_niOOil1OO_dataout <= rxdata5(1) WHEN niOi11l0i = '1' ELSE wire_niOOili1O_dataout; + wire_niOOili0i_dataout <= rxdata6(2) WHEN niOi11l1O = '1' ELSE wire_niOOillii_dataout; + wire_niOOili0l_dataout <= rxdata6(3) WHEN niOi11l1O = '1' ELSE wire_niOOillil_dataout; + wire_niOOili0O_dataout <= rxdata6(4) WHEN niOi11l1O = '1' ELSE wire_niOOilliO_dataout; + wire_niOOili1i_dataout <= n0l01l1l WHEN niOi11l0i = '1' ELSE wire_niOOill0i_dataout; + wire_niOOili1l_dataout <= rxdata6(0) WHEN niOi11l1O = '1' ELSE wire_niOOill0l_dataout; + wire_niOOili1O_dataout <= rxdata6(1) WHEN niOi11l1O = '1' ELSE wire_niOOill0O_dataout; + wire_niOOiliii_dataout <= rxdata6(5) WHEN niOi11l1O = '1' ELSE wire_niOOillli_dataout; + wire_niOOiliil_dataout <= rxdata6(6) WHEN niOi11l1O = '1' ELSE wire_niOOillll_dataout; + wire_niOOiliiO_dataout <= rxdata6(7) WHEN niOi11l1O = '1' ELSE wire_niOOilllO_dataout; + wire_niOOilili_dataout <= rxdatak6 WHEN niOi11l1O = '1' ELSE wire_niOOillOi_dataout; + wire_niOOilill_dataout <= n0lOl1Oi WHEN niOi11l1O = '1' ELSE wire_niOOillOl_dataout; + wire_niOOililO_dataout <= n0lOl1Ol WHEN niOi11l1O = '1' ELSE wire_niOOillOO_dataout; + wire_niOOiliOi_dataout <= n0lOl1OO WHEN niOi11l1O = '1' ELSE wire_niOOilO1i_dataout; + wire_niOOiliOl_dataout <= n0lOl01i WHEN niOi11l1O = '1' ELSE wire_niOOilO1l_dataout; + wire_niOOiliOO_dataout <= n0lOl01l WHEN niOi11l1O = '1' ELSE wire_niOOilO1O_dataout; + wire_niOOill0i_dataout <= n0lOl00O WHEN niOi11l1O = '1' ELSE wire_niOOilOii_dataout; + wire_niOOill0l_dataout <= rxdata7(0) WHEN niOi11l1l = '1' ELSE rxdata0(0); + wire_niOOill0O_dataout <= rxdata7(1) WHEN niOi11l1l = '1' ELSE rxdata0(1); + wire_niOOill1i_dataout <= n0lOl01O WHEN niOi11l1O = '1' ELSE wire_niOOilO0i_dataout; + wire_niOOill1l_dataout <= n0lOl00i WHEN niOi11l1O = '1' ELSE wire_niOOilO0l_dataout; + wire_niOOill1O_dataout <= n0lOl00l WHEN niOi11l1O = '1' ELSE wire_niOOilO0O_dataout; + wire_niOOillii_dataout <= rxdata7(2) WHEN niOi11l1l = '1' ELSE rxdata0(2); + wire_niOOillil_dataout <= rxdata7(3) WHEN niOi11l1l = '1' ELSE rxdata0(3); + wire_niOOilliO_dataout <= rxdata7(4) WHEN niOi11l1l = '1' ELSE rxdata0(4); + wire_niOOillli_dataout <= rxdata7(5) WHEN niOi11l1l = '1' ELSE rxdata0(5); + wire_niOOillll_dataout <= rxdata7(6) WHEN niOi11l1l = '1' ELSE rxdata0(6); + wire_niOOilllO_dataout <= rxdata7(7) WHEN niOi11l1l = '1' ELSE rxdata0(7); + wire_niOOillOi_dataout <= rxdatak7 WHEN niOi11l1l = '1' ELSE rxdatak0; + wire_niOOillOl_dataout <= n0Ol1O1l WHEN niOi11l1l = '1' ELSE n1Oli00i; + wire_niOOillOO_dataout <= n0Ol1O1O WHEN niOi11l1l = '1' ELSE n1Oli00l; + wire_niOOilO0i_dataout <= n0Ol1Oii WHEN niOi11l1l = '1' ELSE n1Oli0iO; + wire_niOOilO0l_dataout <= n0Ol1Oil WHEN niOi11l1l = '1' ELSE n1Oli0li; + wire_niOOilO0O_dataout <= n0Ol1OiO WHEN niOi11l1l = '1' ELSE n1Oli0ll; + wire_niOOilO1i_dataout <= n0Ol1O0i WHEN niOi11l1l = '1' ELSE n1Oli00O; + wire_niOOilO1l_dataout <= n0Ol1O0l WHEN niOi11l1l = '1' ELSE n1Oli0ii; + wire_niOOilO1O_dataout <= n0Ol1O0O WHEN niOi11l1l = '1' ELSE n1Oli0il; + wire_niOOilOii_dataout <= n0Ol1Oli WHEN niOi11l1l = '1' ELSE n1Oli0lO; + wire_niOOilOil_dataout <= n010OOil WHEN niOi11lil = '1' ELSE wire_niOOiiiOl_dataout; + wire_niOOilOiO_dataout <= n010OOiO WHEN niOi11lil = '1' ELSE wire_niOOiiiOO_dataout; + wire_niOOilOli_dataout <= n010OOli WHEN niOi11lil = '1' ELSE wire_niOOiil1i_dataout; + wire_niOOilOll_dataout <= n010OOll WHEN niOi11lil = '1' ELSE wire_niOOiil1l_dataout; + wire_niOOilOlO_dataout <= n010OOlO WHEN niOi11lil = '1' ELSE wire_niOOiil1O_dataout; + wire_niOOilOO_dataout <= wire_niOOiOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOilOOi_dataout <= n010OOOi WHEN niOi11lil = '1' ELSE wire_niOOiil0i_dataout; + wire_niOOilOOl_dataout <= n010OOOl WHEN niOi11lil = '1' ELSE wire_niOOiil0l_dataout; + wire_niOOilOOO_dataout <= n010OOOO WHEN niOi11lil = '1' ELSE wire_niOOiil0O_dataout; + wire_niOOiO00i_dataout <= rxstatus1(1) WHEN niOi11lil = '1' ELSE wire_niOOiO0Ol_dataout; + wire_niOOiO00l_dataout <= rxstatus1(2) WHEN niOi11lil = '1' ELSE wire_niOOiO0OO_dataout; + wire_niOOiO00O_dataout <= n1l0000l WHEN niOi11lii = '1' ELSE wire_niOOiOi1i_dataout; + wire_niOOiO01i_dataout <= phystatus1 WHEN niOi11lil = '1' ELSE wire_niOOiO0ll_dataout; + wire_niOOiO01l_dataout <= rxelecidle1 WHEN niOi11lil = '1' ELSE wire_niOOiO0lO_dataout; + wire_niOOiO01O_dataout <= rxstatus1(0) WHEN niOi11lil = '1' ELSE wire_niOOiO0Oi_dataout; + wire_niOOiO0i_dataout <= wire_niOOiOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiO0ii_dataout <= wire_niil0iOl_dataout WHEN niOi11lii = '1' ELSE wire_niOOiOi1l_dataout; + wire_niOOiO0il_dataout <= n001iO0O WHEN niOi11lii = '1' ELSE wire_niOOiOi1O_dataout; + wire_niOOiO0iO_dataout <= nlOlO1iOi WHEN niOi11lii = '1' ELSE wire_niOOiOi0i_dataout; + wire_niOOiO0l_dataout <= wire_niOOl11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiO0li_dataout <= rxvalid2 WHEN niOi11lii = '1' ELSE wire_niOOiOi0l_dataout; + wire_niOOiO0ll_dataout <= phystatus2 WHEN niOi11lii = '1' ELSE wire_niOOiOi0O_dataout; + wire_niOOiO0lO_dataout <= rxelecidle2 WHEN niOi11lii = '1' ELSE wire_niOOiOiii_dataout; + wire_niOOiO0O_dataout <= wire_niOOl11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiO0Oi_dataout <= rxstatus2(0) WHEN niOi11lii = '1' ELSE wire_niOOiOiil_dataout; + wire_niOOiO0Ol_dataout <= rxstatus2(1) WHEN niOi11lii = '1' ELSE wire_niOOiOiiO_dataout; + wire_niOOiO0OO_dataout <= rxstatus2(2) WHEN niOi11lii = '1' ELSE wire_niOOiOili_dataout; + wire_niOOiO10i_dataout <= n01i101l WHEN niOi11lil = '1' ELSE wire_niOOiO0il_dataout; + wire_niOOiO10l_dataout <= nlOlO1ilO WHEN niOi11lil = '1' ELSE wire_niOOiO0iO_dataout; + wire_niOOiO10O_dataout <= rxdata1(0) WHEN niOi11lil = '1' ELSE wire_niOOiii0l_dataout; + wire_niOOiO11i_dataout <= n01i111i WHEN niOi11lil = '1' ELSE wire_niOOiilii_dataout; + wire_niOOiO11l_dataout <= n1l0000i WHEN niOi11lil = '1' ELSE wire_niOOiO00O_dataout; + wire_niOOiO11O_dataout <= wire_niil0l1i_dataout WHEN niOi11lil = '1' ELSE wire_niOOiO0ii_dataout; + wire_niOOiO1i_dataout <= wire_niOOiOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiO1ii_dataout <= rxdata1(1) WHEN niOi11lil = '1' ELSE wire_niOOiii0O_dataout; + wire_niOOiO1il_dataout <= rxdata1(2) WHEN niOi11lil = '1' ELSE wire_niOOiiiii_dataout; + wire_niOOiO1iO_dataout <= rxdata1(3) WHEN niOi11lil = '1' ELSE wire_niOOiiiil_dataout; + wire_niOOiO1l_dataout <= wire_niOOiOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiO1li_dataout <= rxdata1(4) WHEN niOi11lil = '1' ELSE wire_niOOiiiiO_dataout; + wire_niOOiO1ll_dataout <= rxdata1(5) WHEN niOi11lil = '1' ELSE wire_niOOiiili_dataout; + wire_niOOiO1lO_dataout <= rxdata1(6) WHEN niOi11lil = '1' ELSE wire_niOOiiill_dataout; + wire_niOOiO1O_dataout <= wire_niOOiOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiO1Oi_dataout <= rxdata1(7) WHEN niOi11lil = '1' ELSE wire_niOOiiilO_dataout; + wire_niOOiO1Ol_dataout <= rxdatak1 WHEN niOi11lil = '1' ELSE wire_niOOiiiOi_dataout; + wire_niOOiO1OO_dataout <= rxvalid1 WHEN niOi11lil = '1' ELSE wire_niOOiO0li_dataout; + wire_niOOiOi0i_dataout <= nlOlO1iOl WHEN niOi11l0O = '1' ELSE wire_niOOiOiOl_dataout; + wire_niOOiOi0l_dataout <= rxvalid3 WHEN niOi11l0O = '1' ELSE wire_niOOiOiOO_dataout; + wire_niOOiOi0O_dataout <= phystatus3 WHEN niOi11l0O = '1' ELSE wire_niOOiOl1i_dataout; + wire_niOOiOi1i_dataout <= n1l0000O WHEN niOi11l0O = '1' ELSE wire_niOOiOill_dataout; + wire_niOOiOi1l_dataout <= wire_niil0iOi_dataout WHEN niOi11l0O = '1' ELSE wire_niOOiOilO_dataout; + wire_niOOiOi1O_dataout <= n00O1ili WHEN niOi11l0O = '1' ELSE wire_niOOiOiOi_dataout; + wire_niOOiOii_dataout <= wire_niOOl11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiOiii_dataout <= rxelecidle3 WHEN niOi11l0O = '1' ELSE wire_niOOiOl1l_dataout; + wire_niOOiOiil_dataout <= rxstatus3(0) WHEN niOi11l0O = '1' ELSE wire_niOOiOl1O_dataout; + wire_niOOiOiiO_dataout <= rxstatus3(1) WHEN niOi11l0O = '1' ELSE wire_niOOiOl0i_dataout; + wire_niOOiOil_dataout <= wire_niOOl10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiOili_dataout <= rxstatus3(2) WHEN niOi11l0O = '1' ELSE wire_niOOiOl0l_dataout; + wire_niOOiOill_dataout <= n1l000ii WHEN niOi11l0l = '1' ELSE wire_niOOiOl0O_dataout; + wire_niOOiOilO_dataout <= wire_niil0ilO_dataout WHEN niOi11l0l = '1' ELSE wire_niOOiOlii_dataout; + wire_niOOiOiO_dataout <= wire_niOOl10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiOiOi_dataout <= n0iil1Ol WHEN niOi11l0l = '1' ELSE wire_niOOiOlil_dataout; + wire_niOOiOiOl_dataout <= nlOlO1iOO WHEN niOi11l0l = '1' ELSE wire_niOOiOliO_dataout; + wire_niOOiOiOO_dataout <= rxvalid4 WHEN niOi11l0l = '1' ELSE wire_niOOiOlli_dataout; + wire_niOOiOl0i_dataout <= rxstatus4(1) WHEN niOi11l0l = '1' ELSE wire_niOOiOlOl_dataout; + wire_niOOiOl0l_dataout <= rxstatus4(2) WHEN niOi11l0l = '1' ELSE wire_niOOiOlOO_dataout; + wire_niOOiOl0O_dataout <= n1l000il WHEN niOi11l0i = '1' ELSE wire_niOOiOO1i_dataout; + wire_niOOiOl1i_dataout <= phystatus4 WHEN niOi11l0l = '1' ELSE wire_niOOiOlll_dataout; + wire_niOOiOl1l_dataout <= rxelecidle4 WHEN niOi11l0l = '1' ELSE wire_niOOiOllO_dataout; + wire_niOOiOl1O_dataout <= rxstatus4(0) WHEN niOi11l0l = '1' ELSE wire_niOOiOlOi_dataout; + wire_niOOiOli_dataout <= wire_niOOl10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOiOlii_dataout <= wire_niil0ill_dataout WHEN niOi11l0i = '1' ELSE wire_niOOiOO1l_dataout; + wire_niOOiOlil_dataout <= n0l01O1O WHEN niOi11l0i = '1' ELSE wire_niOOiOO1O_dataout; + wire_niOOiOliO_dataout <= nlOlO1l1i WHEN niOi11l0i = '1' ELSE wire_niOOiOO0i_dataout; + wire_niOOiOll_dataout <= niOOl00i WHEN niOO1il1O = '1' ELSE niOOl1il; + wire_niOOiOlli_dataout <= rxvalid5 WHEN niOi11l0i = '1' ELSE wire_niOOiOO0l_dataout; + wire_niOOiOlll_dataout <= phystatus5 WHEN niOi11l0i = '1' ELSE wire_niOOiOO0O_dataout; + wire_niOOiOllO_dataout <= rxelecidle5 WHEN niOi11l0i = '1' ELSE wire_niOOiOOii_dataout; + wire_niOOiOlO_dataout <= niOOl00l WHEN niOO1il1O = '1' ELSE niOOil0i; + wire_niOOiOlOi_dataout <= rxstatus5(0) WHEN niOi11l0i = '1' ELSE wire_niOOiOOil_dataout; + wire_niOOiOlOl_dataout <= rxstatus5(1) WHEN niOi11l0i = '1' ELSE wire_niOOiOOiO_dataout; + wire_niOOiOlOO_dataout <= rxstatus5(2) WHEN niOi11l0i = '1' ELSE wire_niOOiOOli_dataout; + wire_niOOiOO0i_dataout <= nlOlO1l1l WHEN niOi11l1O = '1' ELSE wire_niOOiOOOl_dataout; + wire_niOOiOO0l_dataout <= rxvalid6 WHEN niOi11l1O = '1' ELSE wire_niOOiOOOO_dataout; + wire_niOOiOO0O_dataout <= phystatus6 WHEN niOi11l1O = '1' ELSE wire_niOOl111i_dataout; + wire_niOOiOO1i_dataout <= n1l000iO WHEN niOi11l1O = '1' ELSE wire_niOOiOOll_dataout; + wire_niOOiOO1l_dataout <= wire_niil0ili_dataout WHEN niOi11l1O = '1' ELSE wire_niOOiOOlO_dataout; + wire_niOOiOO1O_dataout <= n0lOliii WHEN niOi11l1O = '1' ELSE wire_niOOiOOOi_dataout; + wire_niOOiOOi_dataout <= niOOl00O WHEN niOO1il1O = '1' ELSE niOOil0l; + wire_niOOiOOii_dataout <= rxelecidle6 WHEN niOi11l1O = '1' ELSE wire_niOOl111l_dataout; + wire_niOOiOOil_dataout <= rxstatus6(0) WHEN niOi11l1O = '1' ELSE wire_niOOl111O_dataout; + wire_niOOiOOiO_dataout <= rxstatus6(1) WHEN niOi11l1O = '1' ELSE wire_niOOl110i_dataout; + wire_niOOiOOl_dataout <= niOOl0ii WHEN niOO1il1O = '1' ELSE niOOil0O; + wire_niOOiOOli_dataout <= rxstatus6(2) WHEN niOi11l1O = '1' ELSE wire_niOOl110l_dataout; + wire_niOOiOOll_dataout <= n1l000li WHEN niOi11l1l = '1' ELSE n1l0001O; + wire_niOOiOOlO_dataout <= wire_niil0iiO_dataout WHEN niOi11l1l = '1' ELSE wire_niil0l0O_dataout; + wire_niOOiOOO_dataout <= niOOl0il WHEN niOO1il1O = '1' ELSE niOOilii; + wire_niOOiOOOi_dataout <= n0Ol01ll WHEN niOi11l1l = '1' ELSE n1OliiOi; + wire_niOOiOOOl_dataout <= nlOlO1l1O WHEN niOi11l1l = '1' ELSE nlOlO10iO; + wire_niOOiOOOO_dataout <= rxvalid7 WHEN niOi11l1l = '1' ELSE rxvalid0; + wire_niOOl000i_dataout <= n011lOii WHEN niOi11lil = '1' ELSE n1Oi001O; + wire_niOOl000l_dataout <= n011llOi WHEN niOi11lil = '1' ELSE n1Oi01iO; + wire_niOOl000O_dataout <= wire_niili0li_dataout WHEN niOi11lil = '1' ELSE wire_niili0iO_dataout; + wire_niOOl001i_dataout <= n011li0l WHEN niOi11lil = '1' ELSE n1Oi1O1i; + wire_niOOl001l_dataout <= n010ll0l WHEN niOi11lil = '1' ELSE n1Ol011i; + wire_niOOl001O_dataout <= n011l0li WHEN niOi11lil = '1' ELSE n1Oi1l0O; + wire_niOOl00ii_dataout <= ni101i1l WHEN niOi11lil = '1' ELSE ni111lli; + wire_niOOl00il_dataout <= ni101i1O WHEN niOi11lil = '1' ELSE ni111lll; + wire_niOOl00iO_dataout <= ni101i0i WHEN niOi11lil = '1' ELSE ni111llO; + wire_niOOl00li_dataout <= ni11OOOl WHEN niOi11lil = '1' ELSE ni1110ii; + wire_niOOl00ll_dataout <= wire_n1l10OlO_dataout WHEN niOi11liO = '1' ELSE wire_niOOli1OO_dataout; + wire_niOOl00lO_dataout <= wire_n1l10OOi_dataout WHEN niOi11liO = '1' ELSE wire_niOOli01i_dataout; + wire_niOOl00Oi_dataout <= wire_n1l10OOl_dataout WHEN niOi11liO = '1' ELSE wire_niOOli01l_dataout; + wire_niOOl00Ol_dataout <= wire_n1l10OOO_dataout WHEN niOi11liO = '1' ELSE wire_niOOli01O_dataout; + wire_niOOl00OO_dataout <= wire_n1l1i11i_dataout WHEN niOi11liO = '1' ELSE wire_niOOli00i_dataout; + wire_niOOl010i_dataout <= n00100iO WHEN niOi11lii = '1' ELSE wire_niOOl001l_dataout; + wire_niOOl010l_dataout <= n01O1OOl WHEN niOi11lii = '1' ELSE wire_niOOl001O_dataout; + wire_niOOl010O_dataout <= n01O0ill WHEN niOi11lii = '1' ELSE wire_niOOl000i_dataout; + wire_niOOl011i_dataout <= n1101l0i WHEN niOi11lii = '1' ELSE wire_niOOl01Ol_dataout; + wire_niOOl011l_dataout <= n01O01li WHEN niOi11lii = '1' ELSE wire_niOOl01OO_dataout; + wire_niOOl011O_dataout <= n01O01iO WHEN niOi11lii = '1' ELSE wire_niOOl001i_dataout; + wire_niOOl01ii_dataout <= n01O0i1l WHEN niOi11lii = '1' ELSE wire_niOOl000l_dataout; + wire_niOOl01il_dataout <= wire_niili0ll_dataout WHEN niOi11lii = '1' ELSE wire_niOOl000O_dataout; + wire_niOOl01iO_dataout <= ni1i11iO WHEN niOi11lii = '1' ELSE wire_niOOl00ii_dataout; + wire_niOOl01l_dataout <= niOOl1OO AND NOT(wire_niO01O0O_dataout); + wire_niOOl01li_dataout <= ni1i11li WHEN niOi11lii = '1' ELSE wire_niOOl00il_dataout; + wire_niOOl01ll_dataout <= ni1i11ll WHEN niOi11lii = '1' ELSE wire_niOOl00iO_dataout; + wire_niOOl01lO_dataout <= ni10Ol0O WHEN niOi11lii = '1' ELSE wire_niOOl00li_dataout; + wire_niOOl01O_dataout <= niOOl1ll AND NOT(wire_niO01O0O_dataout); + wire_niOOl01Oi_dataout <= nlOOOl1lO WHEN niOi11lil = '1' ELSE nlOOOl1ll; + wire_niOOl01Ol_dataout <= n1101l1O WHEN niOi11lil = '1' ELSE n1101l1l; + wire_niOOl01OO_dataout <= n011li0O WHEN niOi11lil = '1' ELSE n1Oi1O1l; + wire_niOOl0i0i_dataout <= wire_n1l10O1i_dataout WHEN niOi11liO = '1' ELSE wire_niOOli0il_dataout; + wire_niOOl0i0l_dataout <= wire_n1l10O1l_dataout WHEN niOi11liO = '1' ELSE wire_niOOli0iO_dataout; + wire_niOOl0i0O_dataout <= wire_n1l10lOl_dataout WHEN niOi11liO = '1' ELSE wire_niOOli0li_dataout; + wire_niOOl0i1i_dataout <= wire_n1l10OiO_dataout WHEN niOi11liO = '1' ELSE wire_niOOli00l_dataout; + wire_niOOl0i1l_dataout <= wire_n1l10Oli_dataout WHEN niOi11liO = '1' ELSE wire_niOOli00O_dataout; + wire_niOOl0i1O_dataout <= wire_n1l10lOO_dataout WHEN niOi11liO = '1' ELSE wire_niOOli0ii_dataout; + wire_niOOl0iii_dataout <= niOli101i WHEN niOi11liO = '1' ELSE wire_niOOli0ll_dataout; + wire_niOOl0iil_dataout <= n1lillil WHEN niOi11liO = '1' ELSE wire_niOOli0lO_dataout; + wire_niOOl0iiO_dataout <= n110OOOO WHEN niOi11liO = '1' ELSE wire_niOOli0Oi_dataout; + wire_niOOl0ili_dataout <= n11i111i WHEN niOi11liO = '1' ELSE wire_niOOli0Ol_dataout; + wire_niOOl0ill_dataout <= n11i111l WHEN niOi11liO = '1' ELSE wire_niOOli0OO_dataout; + wire_niOOl0ilO_dataout <= wire_niOOl11li_dataout WHEN niOi11liO = '1' ELSE wire_niOOlii1i_dataout; + wire_niOOl0iOi_dataout <= wire_niOOl11ll_dataout WHEN niOi11liO = '1' ELSE wire_niOOlii1l_dataout; + wire_niOOl0iOl_dataout <= wire_niOOl11lO_dataout WHEN niOi11liO = '1' ELSE wire_niOOlii1O_dataout; + wire_niOOl0iOO_dataout <= wire_niOOl11Oi_dataout WHEN niOi11liO = '1' ELSE wire_niOOlii0i_dataout; + wire_niOOl0l0i_dataout <= wire_niOOl101l_dataout WHEN niOi11liO = '1' ELSE wire_niOOliiil_dataout; + wire_niOOl0l0l_dataout <= wire_niOOl101O_dataout WHEN niOi11liO = '1' ELSE wire_niOOliiiO_dataout; + wire_niOOl0l0O_dataout <= niil00Ol WHEN niOi11liO = '1' ELSE wire_niOOliili_dataout; + wire_niOOl0l1i_dataout <= wire_niOOl11Ol_dataout WHEN niOi11liO = '1' ELSE wire_niOOlii0l_dataout; + wire_niOOl0l1l_dataout <= wire_niOOl11OO_dataout WHEN niOi11liO = '1' ELSE wire_niOOlii0O_dataout; + wire_niOOl0l1O_dataout <= wire_niOOl101i_dataout WHEN niOi11liO = '1' ELSE wire_niOOliiii_dataout; + wire_niOOl0lii_dataout <= niil010i WHEN niOi11liO = '1' ELSE wire_niOOliill_dataout; + wire_niOOl0lil_dataout <= niil010l WHEN niOi11liO = '1' ELSE wire_niOOliilO_dataout; + wire_niOOl0liO_dataout <= niil010O WHEN niOi11liO = '1' ELSE wire_niOOliiOi_dataout; + wire_niOOl0lli_dataout <= n1101iOi WHEN niOi11liO = '1' ELSE wire_niOOliiOl_dataout; + wire_niOOl0lll_dataout <= n1101iOl WHEN niOi11liO = '1' ELSE wire_niOOliiOO_dataout; + wire_niOOl0llO_dataout <= n1101iOO WHEN niOi11liO = '1' ELSE wire_niOOlil1i_dataout; + wire_niOOl0lOi_dataout <= n1101l1i WHEN niOi11liO = '1' ELSE wire_niOOlil1l_dataout; + wire_niOOl0lOl_dataout <= wire_niOOl100i_dataout WHEN niOi11liO = '1' ELSE wire_niOOlil1O_dataout; + wire_niOOl0lOO_dataout <= wire_niOOl100l_dataout WHEN niOi11liO = '1' ELSE wire_niOOlil0i_dataout; + wire_niOOl0O0i_dataout <= n11O0ill WHEN niOi11liO = '1' ELSE wire_niOOlilil_dataout; + wire_niOOl0O0l_dataout <= n11O0ilO WHEN niOi11liO = '1' ELSE wire_niOOliliO_dataout; + wire_niOOl0O0O_dataout <= n11O0i0i WHEN niOi11liO = '1' ELSE wire_niOOlilli_dataout; + wire_niOOl0O1i_dataout <= wire_niOOl100O_dataout WHEN niOi11liO = '1' ELSE wire_niOOlil0l_dataout; + wire_niOOl0O1l_dataout <= wire_niOOl10ii_dataout WHEN niOi11liO = '1' ELSE wire_niOOlil0O_dataout; + wire_niOOl0O1O_dataout <= n11O0iOi WHEN niOi11liO = '1' ELSE wire_niOOlilii_dataout; + wire_niOOl0Oii_dataout <= n11O0i0l WHEN niOi11liO = '1' ELSE wire_niOOlilll_dataout; + wire_niOOl0Oil_dataout <= n11li1il WHEN niOi11liO = '1' ELSE wire_niOOlillO_dataout; + wire_niOOl0OiO_dataout <= wire_niOOlilOi_dataout AND NOT(niOi11liO); + wire_niOOl0Oli_dataout <= wire_niOOlilOl_dataout AND NOT(niOi11liO); + wire_niOOl0Oll_dataout <= wire_niOOlilOO_dataout AND NOT(niOi11liO); + wire_niOOl0OlO_dataout <= wire_niOOliO1i_dataout AND NOT(niOi11liO); + wire_niOOl0OO_dataout <= wire_niOOlilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOl0OOi_dataout <= wire_niOOliO1l_dataout AND NOT(niOi11liO); + wire_niOOl0OOl_dataout <= wire_niOOliO1O_dataout AND NOT(niOi11liO); + wire_niOOl0OOO_dataout <= wire_niOOliO0i_dataout AND NOT(niOi11liO); + wire_niOOl100i_dataout <= ni00liOl WHEN niOi11l1l = '1' ELSE wire_niOOl1i1l_dataout; + wire_niOOl100l_dataout <= ni00liOO WHEN niOi11l1l = '1' ELSE wire_niOOl1i1O_dataout; + wire_niOOl100O_dataout <= ni00ll1i WHEN niOi11l1l = '1' ELSE wire_niOOl1i0i_dataout; + wire_niOOl101i_dataout <= n0O0OO1i WHEN niOi11l1l = '1' ELSE wire_niOOl10Ol_dataout; + wire_niOOl101l_dataout <= n0O0Olii WHEN niOi11l1l = '1' ELSE wire_niOOl10OO_dataout; + wire_niOOl101O_dataout <= wire_niilii1i_dataout WHEN niOi11l1l = '1' ELSE wire_niOOl1i1i_dataout; + wire_niOOl10i_dataout <= niOOl0lO WHEN niOO1il1O = '1' ELSE niOOilll; + wire_niOOl10ii_dataout <= ni00l1ll WHEN niOi11l1l = '1' ELSE wire_niOOl1i0l_dataout; + wire_niOOl10il_dataout <= nlOOOl01l WHEN niOi11l1O = '1' ELSE wire_niOOl1i0O_dataout; + wire_niOOl10iO_dataout <= n1101lil WHEN niOi11l1O = '1' ELSE wire_niOOl1iii_dataout; + wire_niOOl10l_dataout <= niOOl0Oi WHEN niOO1il1O = '1' ELSE niOOillO; + wire_niOOl10li_dataout <= n0ll0lll WHEN niOi11l1O = '1' ELSE wire_niOOl1iil_dataout; + wire_niOOl10ll_dataout <= n0ll0lli WHEN niOi11l1O = '1' ELSE wire_niOOl1iiO_dataout; + wire_niOOl10lO_dataout <= n0lO0Oli WHEN niOi11l1O = '1' ELSE wire_niOOl1ili_dataout; + wire_niOOl10O_dataout <= niOOl0Ol WHEN niOO1il1O = '1' ELSE niOOilOi; + wire_niOOl10Oi_dataout <= n0ll0iOO WHEN niOi11l1O = '1' ELSE wire_niOOl1ill_dataout; + wire_niOOl10Ol_dataout <= n0lli1lO WHEN niOi11l1O = '1' ELSE wire_niOOl1ilO_dataout; + wire_niOOl10OO_dataout <= n0lli11O WHEN niOi11l1O = '1' ELSE wire_niOOl1iOi_dataout; + wire_niOOl110i_dataout <= rxstatus7(1) WHEN niOi11l1l = '1' ELSE rxstatus0(1); + wire_niOOl110l_dataout <= rxstatus7(2) WHEN niOi11l1l = '1' ELSE rxstatus0(2); + wire_niOOl110O_dataout <= wire_nillO0ii_dataout AND NOT(test_in_hip(12)); + wire_niOOl111i_dataout <= phystatus7 WHEN niOi11l1l = '1' ELSE phystatus0; + wire_niOOl111l_dataout <= rxelecidle7 WHEN niOi11l1l = '1' ELSE rxelecidle0; + wire_niOOl111O_dataout <= rxstatus7(0) WHEN niOi11l1l = '1' ELSE rxstatus0(0); + wire_niOOl11i_dataout <= niOOl0iO WHEN niOO1il1O = '1' ELSE niOOilil; + wire_niOOl11ii_dataout <= wire_nillO0il_dataout AND NOT(test_in_hip(12)); + wire_niOOl11il_dataout <= wire_nillO0iO_dataout AND NOT(test_in_hip(12)); + wire_niOOl11iO_dataout <= wire_nillO0li_dataout AND NOT(test_in_hip(12)); + wire_niOOl11l_dataout <= niOOl0li WHEN niOO1il1O = '1' ELSE niOOiliO; + wire_niOOl11li_dataout <= nlOOOl01O WHEN niOi11l1l = '1' ELSE wire_niOOl10il_dataout; + wire_niOOl11ll_dataout <= n1101liO WHEN niOi11l1l = '1' ELSE wire_niOOl10iO_dataout; + wire_niOOl11lO_dataout <= n0O0O0OO WHEN niOi11l1l = '1' ELSE wire_niOOl10li_dataout; + wire_niOOl11O_dataout <= niOOl0ll WHEN niOO1il1O = '1' ELSE niOOilli; + wire_niOOl11Oi_dataout <= n0O0O0Ol WHEN niOi11l1l = '1' ELSE wire_niOOl10ll_dataout; + wire_niOOl11Ol_dataout <= n0OiOiOl WHEN niOi11l1l = '1' ELSE wire_niOOl10lO_dataout; + wire_niOOl11OO_dataout <= n0O0O00i WHEN niOi11l1l = '1' ELSE wire_niOOl10Oi_dataout; + wire_niOOl1i0i_dataout <= ni01lOiO WHEN niOi11l1O = '1' ELSE wire_niOOl1l1l_dataout; + wire_niOOl1i0l_dataout <= ni01li0i WHEN niOi11l1O = '1' ELSE wire_niOOl1l1O_dataout; + wire_niOOl1i0O_dataout <= nlOOOl01i WHEN niOi11l0i = '1' ELSE wire_niOOl1l0i_dataout; + wire_niOOl1i1i_dataout <= wire_niili0OO_dataout WHEN niOi11l1O = '1' ELSE wire_niOOl1iOl_dataout; + wire_niOOl1i1l_dataout <= ni01lOii WHEN niOi11l1O = '1' ELSE wire_niOOl1iOO_dataout; + wire_niOOl1i1O_dataout <= ni01lOil WHEN niOi11l1O = '1' ELSE wire_niOOl1l1i_dataout; + wire_niOOl1iii_dataout <= n1101lii WHEN niOi11l0i = '1' ELSE wire_niOOl1l0l_dataout; + wire_niOOl1iil_dataout <= n0iOO1ii WHEN niOi11l0i = '1' ELSE wire_niOOl1l0O_dataout; + wire_niOOl1iiO_dataout <= n0iOO10O WHEN niOi11l0i = '1' ELSE wire_niOOl1lii_dataout; + wire_niOOl1ili_dataout <= n0l1O00O WHEN niOi11l0i = '1' ELSE wire_niOOl1lil_dataout; + wire_niOOl1ill_dataout <= n0iOlOll WHEN niOi11l0i = '1' ELSE wire_niOOl1liO_dataout; + wire_niOOl1ilO_dataout <= n0iOOiil WHEN niOi11l0i = '1' ELSE wire_niOOl1lli_dataout; + wire_niOOl1iOi_dataout <= n0iOO0Ol WHEN niOi11l0i = '1' ELSE wire_niOOl1lll_dataout; + wire_niOOl1iOl_dataout <= wire_niili0Ol_dataout WHEN niOi11l0i = '1' ELSE wire_niOOl1llO_dataout; + wire_niOOl1iOO_dataout <= ni1OO1OO WHEN niOi11l0i = '1' ELSE wire_niOOl1lOi_dataout; + wire_niOOl1l0i_dataout <= nlOOOl1OO WHEN niOi11l0l = '1' ELSE wire_niOOl1O1l_dataout; + wire_niOOl1l0l_dataout <= n1101l0O WHEN niOi11l0l = '1' ELSE wire_niOOl1O1O_dataout; + wire_niOOl1l0O_dataout <= n0i00i1O WHEN niOi11l0l = '1' ELSE wire_niOOl1O0i_dataout; + wire_niOOl1l1i_dataout <= ni1OO01i WHEN niOi11l0i = '1' ELSE wire_niOOl1lOl_dataout; + wire_niOOl1l1l_dataout <= ni1OO01l WHEN niOi11l0i = '1' ELSE wire_niOOl1lOO_dataout; + wire_niOOl1l1O_dataout <= ni1OlllO WHEN niOi11l0i = '1' ELSE wire_niOOl1O1i_dataout; + wire_niOOl1li_dataout <= niOOl1Oi AND NOT(wire_niO01l0O_dataout); + wire_niOOl1lii_dataout <= n0i00i1l WHEN niOi11l0l = '1' ELSE wire_niOOl1O0l_dataout; + wire_niOOl1lil_dataout <= n0ii0l1l WHEN niOi11l0l = '1' ELSE wire_niOOl1O0O_dataout; + wire_niOOl1liO_dataout <= n0i000ii WHEN niOi11l0l = '1' ELSE wire_niOOl1Oii_dataout; + wire_niOOl1lli_dataout <= n0i00O0i WHEN niOi11l0l = '1' ELSE wire_niOOl1Oil_dataout; + wire_niOOl1lll_dataout <= n0i00lli WHEN niOi11l0l = '1' ELSE wire_niOOl1OiO_dataout; + wire_niOOl1llO_dataout <= wire_niili0Oi_dataout WHEN niOi11l0l = '1' ELSE wire_niOOl1Oli_dataout; + wire_niOOl1lO_dataout <= niOOilOl AND NOT(wire_niO01l0O_dataout); + wire_niOOl1lOi_dataout <= ni1lOiil WHEN niOi11l0l = '1' ELSE wire_niOOl1Oll_dataout; + wire_niOOl1lOl_dataout <= ni1lOiiO WHEN niOi11l0l = '1' ELSE wire_niOOl1OlO_dataout; + wire_niOOl1lOO_dataout <= ni1lOili WHEN niOi11l0l = '1' ELSE wire_niOOl1OOi_dataout; + wire_niOOl1O0i_dataout <= n00illOl WHEN niOi11l0O = '1' ELSE wire_niOOl011l_dataout; + wire_niOOl1O0l_dataout <= n00illOi WHEN niOi11l0O = '1' ELSE wire_niOOl011O_dataout; + wire_niOOl1O0O_dataout <= n00llOOi WHEN niOi11l0O = '1' ELSE wire_niOOl010i_dataout; + wire_niOOl1O1i_dataout <= ni1lO10l WHEN niOi11l0l = '1' ELSE wire_niOOl1OOl_dataout; + wire_niOOl1O1l_dataout <= nlOOOl1Ol WHEN niOi11l0O = '1' ELSE wire_niOOl1OOO_dataout; + wire_niOOl1O1O_dataout <= n1101l0l WHEN niOi11l0O = '1' ELSE wire_niOOl011i_dataout; + wire_niOOl1Oii_dataout <= n00ill1O WHEN niOi11l0O = '1' ELSE wire_niOOl010l_dataout; + wire_niOOl1Oil_dataout <= n00iO1OO WHEN niOi11l0O = '1' ELSE wire_niOOl010O_dataout; + wire_niOOl1OiO_dataout <= n00iO10O WHEN niOi11l0O = '1' ELSE wire_niOOl01ii_dataout; + wire_niOOl1Ol_dataout <= niOOl01i AND NOT(wire_niO01O0O_dataout); + wire_niOOl1Oli_dataout <= wire_niili0lO_dataout WHEN niOi11l0O = '1' ELSE wire_niOOl01il_dataout; + wire_niOOl1Oll_dataout <= ni1iOO1i WHEN niOi11l0O = '1' ELSE wire_niOOl01iO_dataout; + wire_niOOl1OlO_dataout <= ni1iOO1l WHEN niOi11l0O = '1' ELSE wire_niOOl01li_dataout; + wire_niOOl1OOi_dataout <= ni1iOO1O WHEN niOi11l0O = '1' ELSE wire_niOOl01ll_dataout; + wire_niOOl1OOl_dataout <= ni1iO0Oi WHEN niOi11l0O = '1' ELSE wire_niOOl01lO_dataout; + wire_niOOl1OOO_dataout <= nlOOOl1Oi WHEN niOi11lii = '1' ELSE wire_niOOl01Oi_dataout; + wire_niOOli00i_dataout <= wire_nlilOOO1O_dataout WHEN niOi11lli = '1' ELSE wire_niOOll1il_dataout; + wire_niOOli00l_dataout <= nlillil1i WHEN niOi11lli = '1' ELSE wire_niOOll1iO_dataout; + wire_niOOli00O_dataout <= nlilliiOO WHEN niOi11lli = '1' ELSE wire_niOOll1li_dataout; + wire_niOOli01i_dataout <= wire_nliO1111i_dataout WHEN niOi11lli = '1' ELSE wire_niOOll10l_dataout; + wire_niOOli01l_dataout <= wire_nlilOOO1i_dataout WHEN niOi11lli = '1' ELSE wire_niOOll10O_dataout; + wire_niOOli01O_dataout <= wire_nlilOOO1l_dataout WHEN niOi11lli = '1' ELSE wire_niOOll1ii_dataout; + wire_niOOli0i_dataout <= wire_niOOll1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOli0ii_dataout <= nlilliiOl WHEN niOi11lli = '1' ELSE wire_niOOll1ll_dataout; + wire_niOOli0il_dataout <= niOiO1llO WHEN niOi11lli = '1' ELSE wire_niOOll1lO_dataout; + wire_niOOli0iO_dataout <= nlilliiOi WHEN niOi11lli = '1' ELSE wire_niOOll1Oi_dataout; + wire_niOOli0l_dataout <= wire_niOOll1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOli0li_dataout <= wire_nlll0lOOl_dataout WHEN niOi11lli = '1' ELSE wire_niOOll1Ol_dataout; + wire_niOOli0ll_dataout <= wire_nlll0lOOO_dataout WHEN niOi11lli = '1' ELSE wire_niOOll1OO_dataout; + wire_niOOli0lO_dataout <= wire_nlll0O11i_dataout WHEN niOi11lli = '1' ELSE wire_niOOll01i_dataout; + wire_niOOli0O_dataout <= wire_niOOll0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOli0Oi_dataout <= wire_nlll0lOll_dataout WHEN niOi11lli = '1' ELSE wire_niOOll01l_dataout; + wire_niOOli0Ol_dataout <= wire_nlll0lOlO_dataout WHEN niOi11lli = '1' ELSE wire_niOOll01O_dataout; + wire_niOOli0OO_dataout <= nlll0101l WHEN niOi11lli = '1' ELSE wire_niOOll00i_dataout; + wire_niOOli10i_dataout <= wire_niOOliOil_dataout AND NOT(niOi11liO); + wire_niOOli10l_dataout <= wire_niOOliOiO_dataout AND NOT(niOi11liO); + wire_niOOli10O_dataout <= wire_niOOliOli_dataout AND NOT(niOi11liO); + wire_niOOli11i_dataout <= wire_niOOliO0l_dataout AND NOT(niOi11liO); + wire_niOOli11l_dataout <= wire_niOOliO0O_dataout AND NOT(niOi11liO); + wire_niOOli11O_dataout <= wire_niOOliOii_dataout AND NOT(niOi11liO); + wire_niOOli1i_dataout <= wire_niOOliOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOli1ii_dataout <= wire_niOOliOll_dataout AND NOT(niOi11liO); + wire_niOOli1il_dataout <= wire_niOOliOlO_dataout AND NOT(niOi11liO); + wire_niOOli1iO_dataout <= wire_niOOliOOi_dataout AND NOT(niOi11liO); + wire_niOOli1l_dataout <= wire_niOOliOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOli1li_dataout <= wire_niOOliOOl_dataout AND NOT(niOi11liO); + wire_niOOli1ll_dataout <= wire_niOOliOOO_dataout AND NOT(niOi11liO); + wire_niOOli1lO_dataout <= wire_niOOll11i_dataout AND NOT(niOi11liO); + wire_niOOli1O_dataout <= wire_niOOll1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOli1Oi_dataout <= wire_niOOll11l_dataout AND NOT(niOi11liO); + wire_niOOli1Ol_dataout <= wire_niOOll11O_dataout AND NOT(niOi11liO); + wire_niOOli1OO_dataout <= wire_nlilOOOOO_dataout WHEN niOi11lli = '1' ELSE wire_niOOll10i_dataout; + wire_niOOlii0i_dataout <= nlll0ilOO WHEN niOi11lli = '1' ELSE wire_niOOll0il_dataout; + wire_niOOlii0l_dataout <= nlll0iOOi WHEN niOi11lli = '1' ELSE wire_niOOll0iO_dataout; + wire_niOOlii0O_dataout <= nlll0iOOl WHEN niOi11lli = '1' ELSE wire_niOOll0li_dataout; + wire_niOOlii1i_dataout <= nlll00l1i WHEN niOi11lli = '1' ELSE wire_niOOll00l_dataout; + wire_niOOlii1l_dataout <= nlll010Ol WHEN niOi11lli = '1' ELSE wire_niOOll00O_dataout; + wire_niOOlii1O_dataout <= nlll010OO WHEN niOi11lli = '1' ELSE wire_niOOll0ii_dataout; + wire_niOOliii_dataout <= wire_niOOll0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOliiii_dataout <= nlll0iOOO WHEN niOi11lli = '1' ELSE wire_niOOll0ll_dataout; + wire_niOOliiil_dataout <= nlll0il1O WHEN niOi11lli = '1' ELSE wire_niOOll0lO_dataout; + wire_niOOliiiO_dataout <= wire_nlOi01lii_dataout WHEN niOi11lli = '1' ELSE wire_niOOll0Oi_dataout; + wire_niOOliil_dataout <= wire_niOOll0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOliili_dataout <= wire_nlOi01lil_dataout WHEN niOi11lli = '1' ELSE wire_niOOll0Ol_dataout; + wire_niOOliill_dataout <= wire_nlOi01liO_dataout WHEN niOi11lli = '1' ELSE wire_niOOll0OO_dataout; + wire_niOOliilO_dataout <= ((nlO00lOli OR nlO00lOiO) OR nlO1Ol1li) WHEN niOi11lli = '1' ELSE wire_niOOlli1i_dataout; + wire_niOOliiO_dataout <= wire_niOOllii_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOliiOi_dataout <= nlO00lOll WHEN niOi11lli = '1' ELSE wire_niOOlli1l_dataout; + wire_niOOliiOl_dataout <= nlOi1Oill WHEN niOi11lli = '1' ELSE wire_niOOlli1O_dataout; + wire_niOOliiOO_dataout <= nlOi1OilO WHEN niOi11lli = '1' ELSE wire_niOOlli0i_dataout; + wire_niOOlil0i_dataout <= nlOi1Ol1i WHEN niOi11lli = '1' ELSE wire_niOOlliil_dataout; + wire_niOOlil0l_dataout <= nlOi1Ol1l WHEN niOi11lli = '1' ELSE wire_niOOlliiO_dataout; + wire_niOOlil0O_dataout <= nlOi1Ol1O WHEN niOi11lli = '1' ELSE wire_niOOllili_dataout; + wire_niOOlil1i_dataout <= nlOi1OiOi WHEN niOi11lli = '1' ELSE wire_niOOlli0l_dataout; + wire_niOOlil1l_dataout <= nlOi1OiOl WHEN niOi11lli = '1' ELSE wire_niOOlli0O_dataout; + wire_niOOlil1O_dataout <= nlOi1OiOO WHEN niOi11lli = '1' ELSE wire_niOOlliii_dataout; + wire_niOOlili_dataout <= wire_niOOllil_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOlilii_dataout <= nlO1Oi1lO WHEN niOi11lli = '1' ELSE wire_niOOllill_dataout; + wire_niOOlilil_dataout <= nlO1Oi1ll WHEN niOi11lli = '1' ELSE wire_niOOllilO_dataout; + wire_niOOliliO_dataout <= nlO1Oi10i WHEN niOi11lli = '1' ELSE wire_niOOlliOi_dataout; + wire_niOOlill_dataout <= wire_niOOlliO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOlilli_dataout <= nll0lOi1l WHEN niOi11lli = '1' ELSE wire_niOOlliOl_dataout; + wire_niOOlilll_dataout <= nll0lO01i WHEN niOi11lli = '1' ELSE wire_niOOlliOO_dataout; + wire_niOOlillO_dataout <= (nll0liiOl OR nll0liiOi) WHEN niOi11lli = '1' ELSE wire_niOOlll1i_dataout; + wire_niOOlilO_dataout <= wire_niOOO0O_w_lg_niOOl01i8434w(0) WHEN (wire_w_lg_niOO1il0l8423w(0) AND wire_w_lg_niOO1il0i8435w(0)) = '1' ELSE niOOl01i; + wire_niOOlilOi_dataout <= nll0ll1OO WHEN niOi11lli = '1' ELSE wire_niOOlll1l_dataout; + wire_niOOlilOl_dataout <= nlliiilli WHEN niOi11lli = '1' ELSE wire_niOOlll1O_dataout; + wire_niOOlilOO_dataout <= nlliiiliO WHEN niOi11lli = '1' ELSE wire_niOOlll0i_dataout; + wire_niOOliO0i_dataout <= nlliiilil WHEN niOi11lli = '1' ELSE wire_niOOlllil_dataout; + wire_niOOliO0l_dataout <= nlliiil1l WHEN niOi11lli = '1' ELSE wire_niOOllliO_dataout; + wire_niOOliO0O_dataout <= nlliiil1O WHEN niOi11lli = '1' ELSE wire_niOOlllli_dataout; + wire_niOOliO1i_dataout <= nlliiil0l WHEN niOi11lli = '1' ELSE wire_niOOlll0l_dataout; + wire_niOOliO1l_dataout <= nlliiil0O WHEN niOi11lli = '1' ELSE wire_niOOlll0O_dataout; + wire_niOOliO1O_dataout <= nlliiilii WHEN niOi11lli = '1' ELSE wire_niOOlllii_dataout; + wire_niOOliOii_dataout <= nlliiil0i WHEN niOi11lli = '1' ELSE wire_niOOlllll_dataout; + wire_niOOliOil_dataout <= (nll0OOOll AND nll0O0i0i) WHEN niOi11lli = '1' ELSE wire_niOOllllO_dataout; + wire_niOOliOiO_dataout <= niOiOiOll WHEN niOi11lli = '1' ELSE wire_niOOlllOi_dataout; + wire_niOOliOl_dataout <= tl_pm_data(0) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl00i; + wire_niOOliOli_dataout <= (niOiOiOli AND nll0O0i0i) WHEN niOi11lli = '1' ELSE wire_niOOlllOl_dataout; + wire_niOOliOll_dataout <= ((niOiOiOiO AND nll0O10OO) AND nll0O0i0i) WHEN niOi11lli = '1' ELSE wire_niOOlllOO_dataout; + wire_niOOliOlO_dataout <= (niOiOiOil AND nll0O0i0i) WHEN niOi11lli = '1' ELSE wire_niOOllO1i_dataout; + wire_niOOliOO_dataout <= tl_pm_data(1) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl00l; + wire_niOOliOOi_dataout <= nllii0Oll WHEN niOi11lli = '1' ELSE wire_niOOllO1l_dataout; + wire_niOOliOOl_dataout <= wire_niOOllO1O_dataout AND NOT(niOi11lli); + wire_niOOliOOO_dataout <= wire_niOOllO0i_dataout AND NOT(niOi11lli); + wire_niOOll00i_dataout <= wire_niOOiO10O_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1il_dataout; + wire_niOOll00l_dataout <= wire_niOOiO1ii_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1iO_dataout; + wire_niOOll00O_dataout <= wire_niOOiO1il_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1li_dataout; + wire_niOOll01i_dataout <= wire_niOOiO10l_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO10l_dataout; + wire_niOOll01l_dataout <= wire_niil0i0l_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO10O_dataout; + wire_niOOll01O_dataout <= wire_niil0i0O_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1ii_dataout; + wire_niOOll0i_dataout <= tl_pm_data(5) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0iO; + wire_niOOll0ii_dataout <= wire_niOOiO1iO_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1ll_dataout; + wire_niOOll0il_dataout <= wire_niOOiO1li_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1lO_dataout; + wire_niOOll0iO_dataout <= wire_niOOiO1ll_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1Oi_dataout; + wire_niOOll0l_dataout <= tl_pm_data(6) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0li; + wire_niOOll0li_dataout <= wire_niOOiO1lO_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1Ol_dataout; + wire_niOOll0ll_dataout <= wire_niOOiO1Oi_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO1OO_dataout; + wire_niOOll0lO_dataout <= wire_niOOiO1Ol_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO01i_dataout; + wire_niOOll0O_dataout <= tl_pm_data(7) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0ll; + wire_niOOll0Oi_dataout <= wire_niOOiO1OO_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO01l_dataout; + wire_niOOll0Ol_dataout <= wire_niOOiO01i_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO01O_dataout; + wire_niOOll0OO_dataout <= wire_niOOiO01l_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO00i_dataout; + wire_niOOll10i_dataout <= wire_niOOilOil_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOil_dataout; + wire_niOOll10l_dataout <= wire_niOOilOiO_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOiO_dataout; + wire_niOOll10O_dataout <= wire_niOOilOli_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOli_dataout; + wire_niOOll11i_dataout <= wire_niOOllO0l_dataout AND NOT(niOi11lli); + wire_niOOll11l_dataout <= wire_niOOllO0O_dataout AND NOT(niOi11lli); + wire_niOOll11O_dataout <= wire_niOOllOii_dataout AND NOT(niOi11lli); + wire_niOOll1i_dataout <= tl_pm_data(2) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl00O; + wire_niOOll1ii_dataout <= wire_niOOilOll_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOll_dataout; + wire_niOOll1il_dataout <= wire_niOOilOlO_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOlO_dataout; + wire_niOOll1iO_dataout <= wire_niOOilOOi_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOOi_dataout; + wire_niOOll1l_dataout <= tl_pm_data(3) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0ii; + wire_niOOll1li_dataout <= wire_niOOilOOl_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOOl_dataout; + wire_niOOll1ll_dataout <= wire_niOOilOOO_dataout WHEN niOi11lll = '1' ELSE wire_niOOllOOO_dataout; + wire_niOOll1lO_dataout <= wire_niOOiO11i_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO11i_dataout; + wire_niOOll1O_dataout <= tl_pm_data(4) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0il; + wire_niOOll1Oi_dataout <= wire_niOOiO11l_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO11l_dataout; + wire_niOOll1Ol_dataout <= wire_niOOiO11O_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO11O_dataout; + wire_niOOll1OO_dataout <= wire_niOOiO10i_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO10i_dataout; + wire_niOOlli0i_dataout <= n11l0Oil WHEN niOi11lll = '1' ELSE wire_niOOlO0il_dataout; + wire_niOOlli0l_dataout <= n11O01ll WHEN niOi11lll = '1' ELSE wire_niOOlO0iO_dataout; + wire_niOOlli0O_dataout <= n11O01lO WHEN niOi11lll = '1' ELSE wire_niOOlO0li_dataout; + wire_niOOlli1i_dataout <= wire_niOOiO01O_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO00l_dataout; + wire_niOOlli1l_dataout <= wire_niOOiO00i_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO00O_dataout; + wire_niOOlli1O_dataout <= wire_niOOiO00l_dataout WHEN niOi11lll = '1' ELSE wire_niOOlO0ii_dataout; + wire_niOOllii_dataout <= tl_pm_data(8) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0lO; + wire_niOOlliii_dataout <= n11O01Oi WHEN niOi11lll = '1' ELSE wire_niOOlO0ll_dataout; + wire_niOOlliil_dataout <= n11i110i WHEN niOi11lll = '1' ELSE wire_niOOlO0lO_dataout; + wire_niOOlliiO_dataout <= nlOllOO1i WHEN niOi11lll = '1' ELSE wire_niOOlO0Oi_dataout; + wire_niOOllil_dataout <= tl_pm_data(9) WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0Oi; + wire_niOOllili_dataout <= nlOlO10ii WHEN niOi11lll = '1' ELSE wire_niOOlO0Ol_dataout; + wire_niOOllill_dataout <= nlOlO10il WHEN niOi11lll = '1' ELSE wire_niOOlO0OO_dataout; + wire_niOOllilO_dataout <= n1101iiO WHEN niOi11lll = '1' ELSE wire_niOOlOi1i_dataout; + wire_niOOlliO_dataout <= tl_pm_auxpwr WHEN wire_w_lg_niOO1il0l8423w(0) = '1' ELSE niOOl0Ol; + wire_niOOlliOi_dataout <= wire_niOOlOi1l_dataout AND NOT(niOi11lll); + wire_niOOlliOl_dataout <= wire_niOOlOi1O_dataout AND NOT(niOi11lll); + wire_niOOlliOO_dataout <= wire_niOOlOi0i_dataout AND NOT(niOi11lll); + wire_niOOlll0i_dataout <= wire_niOOlOiil_dataout AND NOT(niOi11lll); + wire_niOOlll0l_dataout <= wire_niOOlOiiO_dataout AND NOT(niOi11lll); + wire_niOOlll0O_dataout <= wire_niOOlOili_dataout AND NOT(niOi11lll); + wire_niOOlll1i_dataout <= wire_niOOlOi0l_dataout AND NOT(niOi11lll); + wire_niOOlll1l_dataout <= wire_niOOlOi0O_dataout AND NOT(niOi11lll); + wire_niOOlll1O_dataout <= wire_niOOlOiii_dataout AND NOT(niOi11lll); + wire_niOOlllii_dataout <= wire_niOOlOill_dataout AND NOT(niOi11lll); + wire_niOOlllil_dataout <= wire_niOOlOilO_dataout AND NOT(niOi11lll); + wire_niOOllliO_dataout <= wire_niOOlOiOi_dataout AND NOT(niOi11lll); + wire_niOOlllli_dataout <= wire_niOOlOiOl_dataout AND NOT(niOi11lll); + wire_niOOlllll_dataout <= wire_niOOlOiOO_dataout AND NOT(niOi11lll); + wire_niOOllllO_dataout <= wire_niOOlOl1i_dataout AND NOT(niOi11lll); + wire_niOOlllO_dataout <= wire_niOOllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOlllOi_dataout <= wire_niOOlOl1l_dataout AND NOT(niOi11lll); + wire_niOOlllOl_dataout <= wire_niOOlOl1O_dataout AND NOT(niOi11lll); + wire_niOOlllOO_dataout <= wire_niOOlOl0i_dataout AND NOT(niOi11lll); + wire_niOOllO0i_dataout <= wire_niOOlOlil_dataout AND NOT(niOi11lll); + wire_niOOllO0l_dataout <= wire_niOOlOliO_dataout AND NOT(niOi11lll); + wire_niOOllO0O_dataout <= wire_niOOlOlli_dataout AND NOT(niOi11lll); + wire_niOOllO1i_dataout <= wire_niOOlOl0l_dataout AND NOT(niOi11lll); + wire_niOOllO1l_dataout <= wire_niOOlOl0O_dataout AND NOT(niOi11lll); + wire_niOOllO1O_dataout <= wire_niOOlOlii_dataout AND NOT(niOi11lll); + wire_niOOllOi_dataout <= wire_nl1000i_w_lg_niOOllOO8420w(0) WHEN (niOOlOii XOR niOOlO0l) = '1' ELSE niOOllOO; + wire_niOOllOii_dataout <= wire_niOOlOlll_dataout AND NOT(niOi11lll); + wire_niOOllOil_dataout <= nlOil1O1O WHEN niOi11llO = '1' ELSE wire_niOOlOllO_dataout; + wire_niOOllOiO_dataout <= niOl1i1ii WHEN niOi11llO = '1' ELSE wire_niOOlOlOi_dataout; + wire_niOOllOli_dataout <= nlOil1Oil WHEN niOi11llO = '1' ELSE wire_niOOlOlOl_dataout; + wire_niOOllOll_dataout <= nlOil1OiO WHEN niOi11llO = '1' ELSE wire_niOOlOlOO_dataout; + wire_niOOllOlO_dataout <= nlOil1Oli WHEN niOi11llO = '1' ELSE wire_niOOlOO1i_dataout; + wire_niOOllOOi_dataout <= nlOil1Oll WHEN niOi11llO = '1' ELSE wire_niOOlOO1l_dataout; + wire_niOOllOOl_dataout <= nlOill11l WHEN niOi11llO = '1' ELSE wire_niOOlOO1O_dataout; + wire_niOOllOOO_dataout <= wire_niOOlOO0i_dataout AND NOT(niOi11llO); + wire_niOOlO00i_dataout <= wire_niOOO11il_dataout AND NOT(niOi11llO); + wire_niOOlO00l_dataout <= wire_niOOO11iO_dataout AND NOT(niOi11llO); + wire_niOOlO00O_dataout <= wire_niOOO11li_dataout AND NOT(niOi11llO); + wire_niOOlO01i_dataout <= wire_niOOO110l_dataout AND NOT(niOi11llO); + wire_niOOlO01l_dataout <= wire_niOOO110O_dataout AND NOT(niOi11llO); + wire_niOOlO01O_dataout <= wire_niOOO11ii_dataout AND NOT(niOi11llO); + wire_niOOlO0i_dataout <= niOOllll AND NOT(wire_niO01l0O_dataout); + wire_niOOlO0ii_dataout <= wire_niOOO11ll_dataout AND NOT(niOi11llO); + wire_niOOlO0il_dataout <= wire_niOOO11lO_dataout AND NOT(niOi11llO); + wire_niOOlO0iO_dataout <= wire_niOOO11Oi_dataout AND NOT(niOi11llO); + wire_niOOlO0li_dataout <= wire_niOOO11Ol_dataout AND NOT(niOi11llO); + wire_niOOlO0ll_dataout <= wire_niOOO11OO_dataout AND NOT(niOi11llO); + wire_niOOlO0lO_dataout <= wire_niOOO101i_dataout AND NOT(niOi11llO); + wire_niOOlO0O_dataout <= niOOlOil AND NOT(wire_niO01O0O_dataout); + wire_niOOlO0Oi_dataout <= wire_niOOO101l_dataout AND NOT(niOi11llO); + wire_niOOlO0Ol_dataout <= wire_niOOO101O_dataout AND NOT(niOi11llO); + wire_niOOlO0OO_dataout <= wire_niOOO100i_dataout AND NOT(niOi11llO); + wire_niOOlO10i_dataout <= nlOill1iO WHEN niOi11llO = '1' ELSE wire_niOOlOOil_dataout; + wire_niOOlO10l_dataout <= nlOill1li WHEN niOi11llO = '1' ELSE wire_niOOlOOiO_dataout; + wire_niOOlO10O_dataout <= wire_niOOlOOli_dataout AND NOT(niOi11llO); + wire_niOOlO11i_dataout <= niOl1i11O WHEN niOi11llO = '1' ELSE wire_niOOlOO0l_dataout; + wire_niOOlO11l_dataout <= nlOill1ii WHEN niOi11llO = '1' ELSE wire_niOOlOO0O_dataout; + wire_niOOlO11O_dataout <= nlOill1il WHEN niOi11llO = '1' ELSE wire_niOOlOOii_dataout; + wire_niOOlO1ii_dataout <= wire_niOOlOOll_dataout AND NOT(niOi11llO); + wire_niOOlO1il_dataout <= wire_niOOlOOlO_dataout AND NOT(niOi11llO); + wire_niOOlO1iO_dataout <= wire_niOOlOOOi_dataout AND NOT(niOi11llO); + wire_niOOlO1l_dataout <= niOOlO0l AND NOT(wire_niO01l0O_dataout); + wire_niOOlO1li_dataout <= wire_niOOlOOOl_dataout AND NOT(niOi11llO); + wire_niOOlO1ll_dataout <= wire_niOOlOOOO_dataout AND NOT(niOi11llO); + wire_niOOlO1lO_dataout <= wire_niOOO111i_dataout AND NOT(niOi11llO); + wire_niOOlO1Oi_dataout <= wire_niOOO111l_dataout AND NOT(niOi11llO); + wire_niOOlO1Ol_dataout <= wire_niOOO111O_dataout AND NOT(niOi11llO); + wire_niOOlO1OO_dataout <= wire_niOOO110i_dataout AND NOT(niOi11llO); + wire_niOOlOi0i_dataout <= wire_niOOO10il_dataout AND NOT(niOi11llO); + wire_niOOlOi0l_dataout <= wire_niOOO10iO_dataout AND NOT(niOi11llO); + wire_niOOlOi0O_dataout <= wire_niOOO10li_dataout AND NOT(niOi11llO); + wire_niOOlOi1i_dataout <= wire_niOOO100l_dataout AND NOT(niOi11llO); + wire_niOOlOi1l_dataout <= wire_niOOO100O_dataout AND NOT(niOi11llO); + wire_niOOlOi1O_dataout <= wire_niOOO10ii_dataout AND NOT(niOi11llO); + wire_niOOlOiii_dataout <= wire_niOOO10ll_dataout AND NOT(niOi11llO); + wire_niOOlOiil_dataout <= wire_niOOO10lO_dataout AND NOT(niOi11llO); + wire_niOOlOiiO_dataout <= wire_niOOO10Oi_dataout AND NOT(niOi11llO); + wire_niOOlOili_dataout <= wire_niOOO10Ol_dataout AND NOT(niOi11llO); + wire_niOOlOill_dataout <= wire_niOOO10OO_dataout AND NOT(niOi11llO); + wire_niOOlOilO_dataout <= wire_niOOO1i1i_dataout AND NOT(niOi11llO); + wire_niOOlOiO_dataout <= niOOlOii AND NOT(wire_niO01O0O_dataout); + wire_niOOlOiOi_dataout <= wire_niOOO1i1l_dataout AND NOT(niOi11llO); + wire_niOOlOiOl_dataout <= wire_niOOO1i1O_dataout AND NOT(niOi11llO); + wire_niOOlOiOO_dataout <= wire_niOOO1i0i_dataout AND NOT(niOi11llO); + wire_niOOlOl0i_dataout <= wire_niOOO1iil_dataout AND NOT(niOi11llO); + wire_niOOlOl0l_dataout <= wire_niOOO1iiO_dataout AND NOT(niOi11llO); + wire_niOOlOl0O_dataout <= wire_niOOO1ili_dataout AND NOT(niOi11llO); + wire_niOOlOl1i_dataout <= wire_niOOO1i0l_dataout AND NOT(niOi11llO); + wire_niOOlOl1l_dataout <= wire_niOOO1i0O_dataout AND NOT(niOi11llO); + wire_niOOlOl1O_dataout <= wire_niOOO1iii_dataout AND NOT(niOi11llO); + wire_niOOlOli_dataout <= niOOlO1O AND NOT(wire_niO01O0O_dataout); + wire_niOOlOlii_dataout <= wire_niOOO1ill_dataout AND NOT(niOi11llO); + wire_niOOlOlil_dataout <= wire_niOOO1ilO_dataout AND NOT(niOi11llO); + wire_niOOlOliO_dataout <= wire_niOOO1iOi_dataout AND NOT(niOi11llO); + wire_niOOlOlli_dataout <= wire_niOOO1iOl_dataout AND NOT(niOi11llO); + wire_niOOlOlll_dataout <= wire_niOOO1iOO_dataout AND NOT(niOi11llO); + wire_niOOlOllO_dataout <= wire_nillO0ll_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1l1i_dataout; + wire_niOOlOlO_dataout <= wire_niOOlOOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOlOlOi_dataout <= wire_nillO0lO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1l1l_dataout; + wire_niOOlOlOl_dataout <= wire_nillO0Oi_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1l1O_dataout; + wire_niOOlOlOO_dataout <= wire_nillO0OO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1l0i_dataout; + wire_niOOlOO0i_dataout <= wire_nillOiii_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1lil_dataout; + wire_niOOlOO0l_dataout <= wire_nillOiil_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1liO_dataout; + wire_niOOlOO0O_dataout <= wire_nilllO1O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1lli_dataout; + wire_niOOlOO1i_dataout <= wire_nillOi1i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1l0l_dataout; + wire_niOOlOO1l_dataout <= wire_nillOi0l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1l0O_dataout; + wire_niOOlOO1O_dataout <= wire_nillOi0O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1lii_dataout; + wire_niOOlOOi_dataout <= wire_niOOO11l_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOlOOii_dataout <= wire_nilllO0i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1lll_dataout; + wire_niOOlOOil_dataout <= wire_nilllO0l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1llO_dataout; + wire_niOOlOOiO_dataout <= wire_nilllO0O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1lOi_dataout; + wire_niOOlOOl_dataout <= wire_niOOO0O_w_lg_niOOlOil8416w(0) WHEN (wire_w_lg_niOO1il0O8417w(0) AND (tl_pm_event XOR niOOlOll)) = '1' ELSE niOOlOil; + wire_niOOlOOli_dataout <= wire_nillO11l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1lOl_dataout; + wire_niOOlOOll_dataout <= wire_nillO11O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1lOO_dataout; + wire_niOOlOOlO_dataout <= wire_nlilOOOOO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1O1i_dataout; + wire_niOOlOOOi_dataout <= wire_nliO1111i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1O1l_dataout; + wire_niOOlOOOl_dataout <= wire_nlilOOO1i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1O1O_dataout; + wire_niOOlOOOO_dataout <= wire_nlilOOO1l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1O0i_dataout; + wire_niOOO000i_dataout <= wire_nilllOOl_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1il_dataout; + wire_niOOO000l_dataout <= wire_nilllOOO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1iO_dataout; + wire_niOOO000O_dataout <= wire_nillO11i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1li_dataout; + wire_niOOO001i_dataout <= wire_nilllOll_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi10l_dataout; + wire_niOOO001l_dataout <= wire_nilllOlO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi10O_dataout; + wire_niOOO001O_dataout <= wire_nilllOOi_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1ii_dataout; + wire_niOOO00i_dataout <= wire_niOOO00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOO00ii_dataout <= wire_nillO11l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1ll_dataout; + wire_niOOO00il_dataout <= wire_nillO11O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1lO_dataout; + wire_niOOO00iO_dataout <= wire_niOOOi1Oi_dataout AND NOT(niOi11lOl); + wire_niOOO00l_dataout <= wire_niOOO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOO00li_dataout <= wire_nillO10i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1Ol_dataout; + wire_niOOO00ll_dataout <= wire_nillO10l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi1OO_dataout; + wire_niOOO00lO_dataout <= wire_nilOO10i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi01i_dataout; + wire_niOOO00O_dataout <= wire_nl1000i_w_lg_niOOO1OO8409w(0) WHEN (nlil1lO0O AND (wire_w_lg_niOO1ilii8410w(0) AND (nlil1lO0O XOR niOOO01O))) = '1' ELSE niOOO1OO; + wire_niOOO00Oi_dataout <= wire_nilOO10l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi01l_dataout; + wire_niOOO00Ol_dataout <= wire_nilOO10O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi01O_dataout; + wire_niOOO00OO_dataout <= wire_nilOO11O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi00i_dataout; + wire_niOOO010i_dataout <= wire_nillOi0l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0Oil_dataout; + wire_niOOO010l_dataout <= wire_nillOi0O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0OiO_dataout; + wire_niOOO010O_dataout <= wire_nillOiii_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0Oli_dataout; + wire_niOOO011i_dataout <= wire_nillllOO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0O0l_dataout; + wire_niOOO011l_dataout <= wire_nilllO1i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0O0O_dataout; + wire_niOOO011O_dataout <= wire_nilllO1l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0Oii_dataout; + wire_niOOO01i_dataout <= niOOO1Ol AND NOT(wire_niO01l0O_dataout); + wire_niOOO01ii_dataout <= wire_nillOiil_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0Oll_dataout; + wire_niOOO01il_dataout <= wire_nilllO1O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0OlO_dataout; + wire_niOOO01iO_dataout <= wire_nilllO0i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0OOi_dataout; + wire_niOOO01l_dataout <= niOOO1li AND NOT(wire_niO01l0O_dataout); + wire_niOOO01li_dataout <= wire_nilllO0l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0OOl_dataout; + wire_niOOO01ll_dataout <= wire_nilllO0O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0OOO_dataout; + wire_niOOO01lO_dataout <= wire_nilllOii_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi11i_dataout; + wire_niOOO01Oi_dataout <= wire_nilllOil_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi11l_dataout; + wire_niOOO01Ol_dataout <= wire_nilllOiO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi11O_dataout; + wire_niOOO01OO_dataout <= wire_nilllOli_dataout WHEN niOi11lOl = '1' ELSE wire_niOOOi10i_dataout; + wire_niOOO0i0i_dataout <= wire_niOOOi0il_dataout AND NOT(niOi11lOl); + wire_niOOO0i0l_dataout <= wire_nillOiiO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOi0iO_dataout; + wire_niOOO0i0O_dataout <= wire_nillOili_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOi0li_dataout; + wire_niOOO0i1i_dataout <= wire_niOOOi00l_dataout AND NOT(niOi11lOl); + wire_niOOO0i1l_dataout <= wire_niOOOi00O_dataout AND NOT(niOi11lOl); + wire_niOOO0i1O_dataout <= wire_niOOOi0ii_dataout AND NOT(niOi11lOl); + wire_niOOO0iii_dataout <= wire_nillOill_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOi0ll_dataout; + wire_niOOO0iil_dataout <= wire_nillOilO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOi0lO_dataout; + wire_niOOO0iiO_dataout <= wire_nillOiOi_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOi0Oi_dataout; + wire_niOOO0ili_dataout <= wire_nillOiOl_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOi0Ol_dataout; + wire_niOOO0ill_dataout <= wire_nillOiOO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOi0OO_dataout; + wire_niOOO0ilO_dataout <= wire_nillOl1i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOii1i_dataout; + wire_niOOO0iOi_dataout <= wire_nillOl1l_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOii1l_dataout; + wire_niOOO0iOl_dataout <= wire_nillOl1O_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOii1O_dataout; + wire_niOOO0iOO_dataout <= wire_nillOl0i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOii0i_dataout; + wire_niOOO0l0i_dataout <= wire_nillOlil_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiiil_dataout; + wire_niOOO0l0l_dataout <= wire_nillOliO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiiiO_dataout; + wire_niOOO0l0O_dataout <= wire_nillOlli_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiili_dataout; + wire_niOOO0l1i_dataout <= wire_nillOl0l_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOii0l_dataout; + wire_niOOO0l1l_dataout <= wire_nillOl0O_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOii0O_dataout; + wire_niOOO0l1O_dataout <= wire_nillOlii_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiiii_dataout; + wire_niOOO0li_dataout <= niOOO01O WHEN niOO1ilii = '1' ELSE nlil1lO0O; + wire_niOOO0lii_dataout <= wire_nillOlll_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiill_dataout; + wire_niOOO0lil_dataout <= wire_nillOllO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiilO_dataout; + wire_niOOO0liO_dataout <= wire_nillOlOi_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiiOi_dataout; + wire_niOOO0lli_dataout <= wire_nillOlOl_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiiOl_dataout; + wire_niOOO0lll_dataout <= wire_nillOlOO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiiOO_dataout; + wire_niOOO0llO_dataout <= wire_nillOO1i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOil1i_dataout; + wire_niOOO0lOi_dataout <= wire_nillOO1l_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOil1l_dataout; + wire_niOOO0lOl_dataout <= wire_nillOO1O_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOil1O_dataout; + wire_niOOO0lOO_dataout <= wire_nillOO0i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOil0i_dataout; + wire_niOOO0O0i_dataout <= wire_nillOOil_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOilil_dataout; + wire_niOOO0O0l_dataout <= wire_nillOOiO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiliO_dataout; + wire_niOOO0O0O_dataout <= wire_nillOOli_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOilli_dataout; + wire_niOOO0O1i_dataout <= wire_nillOO0l_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOil0l_dataout; + wire_niOOO0O1l_dataout <= wire_nillOO0O_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOil0O_dataout; + wire_niOOO0O1O_dataout <= wire_nillOOii_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOilii_dataout; + wire_niOOO0Oi_dataout <= wire_niOOO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOO0Oii_dataout <= wire_nillOOll_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOilll_dataout; + wire_niOOO0Oil_dataout <= wire_nillOOlO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOillO_dataout; + wire_niOOO0OiO_dataout <= wire_nillOOOi_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOilOi_dataout; + wire_niOOO0Ol_dataout <= wire_nl1000i_w_lg_niOOOi1i8406w(0) WHEN (niOOOiil XOR niOOOi0O) = '1' ELSE niOOOi1i; + wire_niOOO0Oli_dataout <= wire_nillOOOl_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOilOl_dataout; + wire_niOOO0Oll_dataout <= wire_nillOOOO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOilOO_dataout; + wire_niOOO0OlO_dataout <= wire_nilO111i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiO1i_dataout; + wire_niOOO0OOi_dataout <= wire_nilO111l_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiO1l_dataout; + wire_niOOO0OOl_dataout <= wire_nilO111O_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiO1O_dataout; + wire_niOOO0OOO_dataout <= wire_nilO110i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiO0i_dataout; + wire_niOOO100i_dataout <= wire_n1l10Oli_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01il_dataout; + wire_niOOO100l_dataout <= wire_n1l10lOO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01iO_dataout; + wire_niOOO100O_dataout <= wire_n1l10O1i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01li_dataout; + wire_niOOO101i_dataout <= wire_n1l10OOO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO010l_dataout; + wire_niOOO101l_dataout <= wire_n1l1i11i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO010O_dataout; + wire_niOOO101O_dataout <= wire_n1l10OiO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01ii_dataout; + wire_niOOO10ii_dataout <= wire_n1l10O1l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01ll_dataout; + wire_niOOO10il_dataout <= wire_niOOii01l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01lO_dataout; + wire_niOOO10iO_dataout <= wire_niOOii01O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01Oi_dataout; + wire_niOOO10l_dataout <= (niOOO1Ol XOR niOOO1lO) AND NOT(wire_niO01l0O_dataout); + wire_niOOO10li_dataout <= wire_niOOii00i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01Ol_dataout; + wire_niOOO10ll_dataout <= wire_niOOii00l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO01OO_dataout; + wire_niOOO10lO_dataout <= wire_niOOii00O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO001i_dataout; + wire_niOOO10Oi_dataout <= wire_niOOii0ii_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO001l_dataout; + wire_niOOO10Ol_dataout <= wire_niOOii0il_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO001O_dataout; + wire_niOOO10OO_dataout <= wire_niOOii0iO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO000i_dataout; + wire_niOOO110i_dataout <= nlilliiOl WHEN niOi11lOi = '1' ELSE wire_niOOO1Oil_dataout; + wire_niOOO110l_dataout <= wire_nlll0lOOl_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1OiO_dataout; + wire_niOOO110O_dataout <= wire_nlll0lOOO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1Oli_dataout; + wire_niOOO111i_dataout <= wire_nlilOOO1O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1O0l_dataout; + wire_niOOO111l_dataout <= nlillil1i WHEN niOi11lOi = '1' ELSE wire_niOOO1O0O_dataout; + wire_niOOO111O_dataout <= nlilliiOO WHEN niOi11lOi = '1' ELSE wire_niOOO1Oii_dataout; + wire_niOOO11ii_dataout <= wire_nlll0O11i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1Oll_dataout; + wire_niOOO11il_dataout <= wire_nlll0lOll_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1OlO_dataout; + wire_niOOO11iO_dataout <= wire_nlll0lOlO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1OOi_dataout; + wire_niOOO11l_dataout <= niOOlOll WHEN niOO1il0O = '1' ELSE tl_pm_event; + wire_niOOO11li_dataout <= wire_nlOi01lii_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1OOl_dataout; + wire_niOOO11ll_dataout <= wire_nlOi01lil_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO1OOO_dataout; + wire_niOOO11lO_dataout <= wire_nlOi01liO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO011i_dataout; + wire_niOOO11Oi_dataout <= wire_n1l10OlO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO011l_dataout; + wire_niOOO11Ol_dataout <= wire_n1l10OOi_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO011O_dataout; + wire_niOOO11OO_dataout <= wire_n1l10OOl_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO010i_dataout; + wire_niOOO1i0i_dataout <= wire_niOOii0Oi_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00il_dataout; + wire_niOOO1i0l_dataout <= wire_niOOii0Ol_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00iO_dataout; + wire_niOOO1i0O_dataout <= wire_niOOii0OO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00li_dataout; + wire_niOOO1i1i_dataout <= wire_niOOii0li_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO000l_dataout; + wire_niOOO1i1l_dataout <= wire_niOOii0ll_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO000O_dataout; + wire_niOOO1i1O_dataout <= wire_niOOii0lO_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00ii_dataout; + wire_niOOO1iii_dataout <= wire_niOOiii1i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00ll_dataout; + wire_niOOO1iil_dataout <= wire_niOOiii1l_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00lO_dataout; + wire_niOOO1iiO_dataout <= wire_niOOiii1O_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00Oi_dataout; + wire_niOOO1ili_dataout <= wire_niOOiii0i_dataout WHEN niOi11lOi = '1' ELSE wire_niOOO00Ol_dataout; + wire_niOOO1ill_dataout <= wire_niOOO00OO_dataout AND NOT(niOi11lOi); + wire_niOOO1ilO_dataout <= wire_niOOO0i1i_dataout AND NOT(niOi11lOi); + wire_niOOO1iO_dataout <= niOOO1lO AND NOT(wire_niO01O0O_dataout); + wire_niOOO1iOi_dataout <= wire_niOOO0i1l_dataout AND NOT(niOi11lOi); + wire_niOOO1iOl_dataout <= wire_niOOO0i1O_dataout AND NOT(niOi11lOi); + wire_niOOO1iOO_dataout <= wire_niOOO0i0i_dataout AND NOT(niOi11lOi); + wire_niOOO1l0i_dataout <= wire_nilll0ii_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0iil_dataout; + wire_niOOO1l0l_dataout <= wire_nilll0il_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0iiO_dataout; + wire_niOOO1l0O_dataout <= wire_nilll0iO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0ili_dataout; + wire_niOOO1l1i_dataout <= wire_nilll00i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0i0l_dataout; + wire_niOOO1l1l_dataout <= wire_nilll00l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0i0O_dataout; + wire_niOOO1l1O_dataout <= wire_nilll00O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0iii_dataout; + wire_niOOO1lii_dataout <= wire_nilll0li_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0ill_dataout; + wire_niOOO1lil_dataout <= wire_nilll0ll_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0ilO_dataout; + wire_niOOO1liO_dataout <= wire_nilll0lO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0iOi_dataout; + wire_niOOO1ll_dataout <= niOOO10i AND NOT(wire_niO01O0O_dataout); + wire_niOOO1lli_dataout <= wire_nilll0Oi_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0iOl_dataout; + wire_niOOO1lll_dataout <= wire_nilll0Ol_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0iOO_dataout; + wire_niOOO1llO_dataout <= wire_nilll0OO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0l1i_dataout; + wire_niOOO1lOi_dataout <= wire_nillllli_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0l1l_dataout; + wire_niOOO1lOl_dataout <= wire_nillO0ll_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0l1O_dataout; + wire_niOOO1lOO_dataout <= wire_nillO0lO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0l0i_dataout; + wire_niOOO1O0i_dataout <= wire_nillOi1i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0lil_dataout; + wire_niOOO1O0l_dataout <= wire_nillOi1l_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0liO_dataout; + wire_niOOO1O0O_dataout <= wire_nillOi1O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0lli_dataout; + wire_niOOO1O1i_dataout <= wire_nillO0Oi_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0l0l_dataout; + wire_niOOO1O1l_dataout <= wire_nillO0Ol_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0l0O_dataout; + wire_niOOO1O1O_dataout <= wire_nillO0OO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0lii_dataout; + wire_niOOO1Oi_dataout <= niOOO1OO AND NOT(wire_niO01l0O_dataout); + wire_niOOO1Oii_dataout <= wire_nillOi0i_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0lll_dataout; + wire_niOOO1Oil_dataout <= wire_niOOl110O_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0llO_dataout; + wire_niOOO1OiO_dataout <= wire_niOOl11ii_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0lOi_dataout; + wire_niOOO1Oli_dataout <= wire_niOOl11il_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0lOl_dataout; + wire_niOOO1Oll_dataout <= wire_niOOl11iO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0lOO_dataout; + wire_niOOO1OlO_dataout <= wire_nillllll_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0O1i_dataout; + wire_niOOO1OOi_dataout <= wire_nilllllO_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0O1l_dataout; + wire_niOOO1OOl_dataout <= wire_nillllOi_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0O1O_dataout; + wire_niOOO1OOO_dataout <= wire_nillllOl_dataout WHEN niOi11lOl = '1' ELSE wire_niOOO0O0i_dataout; + wire_niOOOi00i_dataout <= wire_niOOOl1il_dataout AND NOT(niOi11lOO); + wire_niOOOi00l_dataout <= wire_niOOOl1iO_dataout AND NOT(niOi11lOO); + wire_niOOOi00O_dataout <= wire_niOOOl1li_dataout AND NOT(niOi11lOO); + wire_niOOOi01i_dataout <= wire_niOOOl10l_dataout AND NOT(niOi11lOO); + wire_niOOOi01l_dataout <= wire_niOOOl10O_dataout AND NOT(niOi11lOO); + wire_niOOOi01O_dataout <= wire_niOOOl1ii_dataout AND NOT(niOi11lOO); + wire_niOOOi0ii_dataout <= wire_niOOOl1ll_dataout AND NOT(niOi11lOO); + wire_niOOOi0il_dataout <= wire_niOOOl1lO_dataout AND NOT(niOi11lOO); + wire_niOOOi0iO_dataout <= wire_nilO100l_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl1Oi_dataout; + wire_niOOOi0l_dataout <= niOOO0lO AND NOT(wire_niO01l0O_dataout); + wire_niOOOi0li_dataout <= wire_nilO100O_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl1Ol_dataout; + wire_niOOOi0ll_dataout <= wire_nilO10ii_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl1OO_dataout; + wire_niOOOi0lO_dataout <= wire_nilO10il_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl01i_dataout; + wire_niOOOi0Oi_dataout <= wire_nilO10iO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl01l_dataout; + wire_niOOOi0Ol_dataout <= wire_nilO10li_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl01O_dataout; + wire_niOOOi0OO_dataout <= wire_nilO10ll_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl00i_dataout; + wire_niOOOi10i_dataout <= wire_nilO11il_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOil_dataout; + wire_niOOOi10l_dataout <= wire_nilO11iO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOiO_dataout; + wire_niOOOi10O_dataout <= wire_nilO11li_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOli_dataout; + wire_niOOOi11i_dataout <= wire_nilO110l_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiO0l_dataout; + wire_niOOOi11l_dataout <= wire_nilO110O_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiO0O_dataout; + wire_niOOOi11O_dataout <= wire_nilO11ii_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOii_dataout; + wire_niOOOi1ii_dataout <= wire_nilO11ll_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOll_dataout; + wire_niOOOi1il_dataout <= wire_nilO11lO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOlO_dataout; + wire_niOOOi1iO_dataout <= wire_nilO11Oi_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOOi_dataout; + wire_niOOOi1li_dataout <= wire_nilO11Ol_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOOl_dataout; + wire_niOOOi1ll_dataout <= wire_nilO11OO_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOiOOO_dataout; + wire_niOOOi1lO_dataout <= wire_nilO101i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOl11i_dataout; + wire_niOOOi1O_dataout <= niOOOi0O AND NOT(wire_niO01l0O_dataout); + wire_niOOOi1Oi_dataout <= wire_nilO101l_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOl11l_dataout; + wire_niOOOi1Ol_dataout <= wire_nilO101O_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOl11O_dataout; + wire_niOOOi1OO_dataout <= wire_nilO100i_dataout WHEN niOi11lOO = '1' ELSE wire_niOOOl10i_dataout; + wire_niOOOii0i_dataout <= wire_nilO10OO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0il_dataout; + wire_niOOOii0l_dataout <= wire_nilO1i1i_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0iO_dataout; + wire_niOOOii0O_dataout <= wire_nilO1i1l_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0li_dataout; + wire_niOOOii1i_dataout <= wire_nilO10lO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl00l_dataout; + wire_niOOOii1l_dataout <= wire_nilO10Oi_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl00O_dataout; + wire_niOOOii1O_dataout <= wire_nilO10Ol_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0ii_dataout; + wire_niOOOiii_dataout <= niOOOiiO AND NOT(wire_niO01O0O_dataout); + wire_niOOOiiii_dataout <= wire_nilO1i1O_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0ll_dataout; + wire_niOOOiiil_dataout <= wire_nilO1i0i_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0lO_dataout; + wire_niOOOiiiO_dataout <= wire_nilO1i0l_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0Oi_dataout; + wire_niOOOiili_dataout <= wire_nilO1i0O_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0Ol_dataout; + wire_niOOOiill_dataout <= wire_nilO1iii_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOl0OO_dataout; + wire_niOOOiilO_dataout <= wire_nilO1iil_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOli1i_dataout; + wire_niOOOiiOi_dataout <= wire_nilO1iiO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOli1l_dataout; + wire_niOOOiiOl_dataout <= wire_nilO1ili_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOli1O_dataout; + wire_niOOOiiOO_dataout <= wire_nilO1ill_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOli0i_dataout; + wire_niOOOil0i_dataout <= wire_nilO1iOO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOliil_dataout; + wire_niOOOil0l_dataout <= wire_nilO1l1i_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOliiO_dataout; + wire_niOOOil0O_dataout <= wire_nilO1l1l_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlili_dataout; + wire_niOOOil1i_dataout <= wire_nilO1ilO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOli0l_dataout; + wire_niOOOil1l_dataout <= wire_nilO1iOi_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOli0O_dataout; + wire_niOOOil1O_dataout <= wire_nilO1iOl_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOliii_dataout; + wire_niOOOili_dataout <= niOOOiil AND NOT(wire_niO01O0O_dataout); + wire_niOOOilii_dataout <= wire_nilO1l1O_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlill_dataout; + wire_niOOOilil_dataout <= wire_nilO1l0i_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlilO_dataout; + wire_niOOOiliO_dataout <= wire_nilO1l0l_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOliOi_dataout; + wire_niOOOill_dataout <= niOOOi0i AND NOT(wire_niO01O0O_dataout); + wire_niOOOilli_dataout <= wire_nilO1l0O_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOliOl_dataout; + wire_niOOOilll_dataout <= wire_nilO1lii_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOliOO_dataout; + wire_niOOOillO_dataout <= wire_nilO1lil_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOll1i_dataout; + wire_niOOOilOi_dataout <= wire_nilO1liO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOll1l_dataout; + wire_niOOOilOl_dataout <= wire_nilO1lli_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOll1O_dataout; + wire_niOOOilOO_dataout <= wire_nilO1lll_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOll0i_dataout; + wire_niOOOiO_dataout <= (lmi_rden OR lmi_wren) AND NOT(wire_niO01l0O_dataout); + wire_niOOOiO0i_dataout <= wire_nilO1lOO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOllil_dataout; + wire_niOOOiO0l_dataout <= wire_nilO1O1i_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlliO_dataout; + wire_niOOOiO0O_dataout <= wire_nilO1O1l_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOllli_dataout; + wire_niOOOiO1i_dataout <= wire_nilO1llO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOll0l_dataout; + wire_niOOOiO1l_dataout <= wire_nilO1lOi_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOll0O_dataout; + wire_niOOOiO1O_dataout <= wire_nilO1lOl_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOllii_dataout; + wire_niOOOiOi_dataout <= wire_niOOOiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOOiOii_dataout <= wire_nilO1O1O_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOllll_dataout; + wire_niOOOiOil_dataout <= wire_nilO1O0i_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlllO_dataout; + wire_niOOOiOiO_dataout <= wire_nilO1O0l_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOllOi_dataout; + wire_niOOOiOl_dataout <= wire_niOOOl1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_niOOOiOli_dataout <= wire_nilO1O0O_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOllOl_dataout; + wire_niOOOiOll_dataout <= wire_nilO1Oii_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOllOO_dataout; + wire_niOOOiOlO_dataout <= wire_nilO1Oil_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlO1i_dataout; + wire_niOOOiOO_dataout <= wire_niOOO0O_w_lg_niOOOiiO8402w(0) WHEN (wire_w_lg_niOO1ilil8403w(0) AND (tl_pme_to_cr XOR niOOOilO)) = '1' ELSE niOOOiiO; + wire_niOOOiOOi_dataout <= wire_nilO1OiO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlO1l_dataout; + wire_niOOOiOOl_dataout <= wire_nilO1Oli_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlO1O_dataout; + wire_niOOOiOOO_dataout <= wire_nilO1Oll_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlO0i_dataout; + wire_niOOOl00i_dataout <= wire_nillO1ii_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1il_dataout; + wire_niOOOl00l_dataout <= wire_nillO1il_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1iO_dataout; + wire_niOOOl00O_dataout <= wire_nillO1iO_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1li_dataout; + wire_niOOOl01i_dataout <= nlll011OO WHEN niOi11O1l = '1' ELSE wire_niOOOO10l_dataout; + wire_niOOOl01l_dataout <= nlll0ilOl WHEN niOi11O1l = '1' ELSE wire_niOOOO10O_dataout; + wire_niOOOl01O_dataout <= wire_nillO10O_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1ii_dataout; + wire_niOOOl0ii_dataout <= wire_nillO1li_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1ll_dataout; + wire_niOOOl0il_dataout <= wire_nillO1ll_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1lO_dataout; + wire_niOOOl0iO_dataout <= wire_nillO1lO_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1Oi_dataout; + wire_niOOOl0li_dataout <= wire_nillO1Oi_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1Ol_dataout; + wire_niOOOl0ll_dataout <= wire_nillO1Ol_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO1OO_dataout; + wire_niOOOl0lO_dataout <= wire_nillO1OO_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO01i_dataout; + wire_niOOOl0Oi_dataout <= wire_nillO01i_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO01l_dataout; + wire_niOOOl0Ol_dataout <= wire_nillO01l_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO01O_dataout; + wire_niOOOl0OO_dataout <= wire_nillO01O_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO00i_dataout; + wire_niOOOl10i_dataout <= wire_nilO1OOO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlOil_dataout; + wire_niOOOl10l_dataout <= wire_niOOOlOiO_dataout AND NOT(niOi11O1i); + wire_niOOOl10O_dataout <= wire_niOOOlOli_dataout AND NOT(niOi11O1i); + wire_niOOOl11i_dataout <= wire_nilO1OlO_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlO0l_dataout; + wire_niOOOl11l_dataout <= wire_nilO1OOi_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlO0O_dataout; + wire_niOOOl11O_dataout <= wire_nilO1OOl_dataout WHEN niOi11O1i = '1' ELSE wire_niOOOlOii_dataout; + wire_niOOOl1ii_dataout <= wire_niOOOlOll_dataout AND NOT(niOi11O1i); + wire_niOOOl1il_dataout <= wire_niOOOlOlO_dataout AND NOT(niOi11O1i); + wire_niOOOl1iO_dataout <= wire_niOOOlOOi_dataout AND NOT(niOi11O1i); + wire_niOOOl1li_dataout <= wire_niOOOlOOl_dataout AND NOT(niOi11O1i); + wire_niOOOl1ll_dataout <= wire_niOOOlOOO_dataout AND NOT(niOi11O1i); + wire_niOOOl1lO_dataout <= wire_niOOOO11i_dataout AND NOT(niOi11O1i); + wire_niOOOl1O_dataout <= niOOOilO WHEN niOO1ilil = '1' ELSE tl_pme_to_cr; + wire_niOOOl1Oi_dataout <= niOO010il WHEN niOi11O1l = '1' ELSE wire_niOOOO11l_dataout; + wire_niOOOl1Ol_dataout <= nlliiillO WHEN niOi11O1l = '1' ELSE wire_niOOOO11O_dataout; + wire_niOOOl1OO_dataout <= nlll0101i WHEN niOi11O1l = '1' ELSE wire_niOOOO10i_dataout; + wire_niOOOli_dataout <= lmi_din(0) AND NOT(wire_niO01l0O_dataout); + wire_niOOOli0i_dataout <= wire_nillli1i_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0il_dataout; + wire_niOOOli0l_dataout <= wire_nillli1l_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0iO_dataout; + wire_niOOOli0O_dataout <= wire_nillli1O_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0li_dataout; + wire_niOOOli1i_dataout <= wire_nillO00i_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO00l_dataout; + wire_niOOOli1l_dataout <= wire_nillO00l_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO00O_dataout; + wire_niOOOli1O_dataout <= wire_nillO00O_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0ii_dataout; + wire_niOOOliii_dataout <= wire_nillli0i_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0ll_dataout; + wire_niOOOliil_dataout <= wire_nillli0l_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0lO_dataout; + wire_niOOOliiO_dataout <= wire_nillli0O_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0Oi_dataout; + wire_niOOOlili_dataout <= wire_nillliii_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0Ol_dataout; + wire_niOOOlill_dataout <= wire_nillliil_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOO0OO_dataout; + wire_niOOOlilO_dataout <= wire_nillliiO_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOi1i_dataout; + wire_niOOOliOi_dataout <= wire_nilllili_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOi1l_dataout; + wire_niOOOliOl_dataout <= wire_nilllill_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOi1O_dataout; + wire_niOOOliOO_dataout <= wire_nilllilO_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOi0i_dataout; + wire_niOOOll_dataout <= lmi_din(1) AND NOT(wire_niO01l0O_dataout); + wire_niOOOll0i_dataout <= wire_nillll1i_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOiil_dataout; + wire_niOOOll0l_dataout <= wire_nillll1l_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOiiO_dataout; + wire_niOOOll0O_dataout <= wire_nillll1O_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOili_dataout; + wire_niOOOll1i_dataout <= wire_nillliOi_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOi0l_dataout; + wire_niOOOll1l_dataout <= wire_nillliOl_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOi0O_dataout; + wire_niOOOll1O_dataout <= wire_nillliOO_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOiii_dataout; + wire_niOOOllii_dataout <= wire_nillll0i_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOill_dataout; + wire_niOOOllil_dataout <= wire_nillll0l_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOilO_dataout; + wire_niOOOlliO_dataout <= wire_nillll0O_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOiOi_dataout; + wire_niOOOllli_dataout <= wire_nillllii_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOiOl_dataout; + wire_niOOOllll_dataout <= wire_nillllil_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOiOO_dataout; + wire_niOOOlllO_dataout <= wire_nilllliO_dataout WHEN niOi11O1l = '1' ELSE wire_niOOOOl1i_dataout; + wire_niOOOllOi_dataout <= wire_niOOOOl1l_dataout AND NOT(niOi11O1l); + wire_niOOOllOl_dataout <= wire_niOOOOl1O_dataout AND NOT(niOi11O1l); + wire_niOOOllOO_dataout <= wire_niOOOOl0i_dataout AND NOT(niOi11O1l); + wire_niOOOlO_dataout <= lmi_din(2) AND NOT(wire_niO01l0O_dataout); + wire_niOOOlO0i_dataout <= wire_niOOOOlil_dataout AND NOT(niOi11O1l); + wire_niOOOlO0l_dataout <= wire_niOOOOliO_dataout AND NOT(niOi11O1l); + wire_niOOOlO0O_dataout <= wire_niOOOOlli_dataout AND NOT(niOi11O1l); + wire_niOOOlO1i_dataout <= wire_niOOOOl0l_dataout AND NOT(niOi11O1l); + wire_niOOOlO1l_dataout <= wire_niOOOOl0O_dataout AND NOT(niOi11O1l); + wire_niOOOlO1O_dataout <= wire_niOOOOlii_dataout AND NOT(niOi11O1l); + wire_niOOOlOii_dataout <= wire_niOOOOlll_dataout AND NOT(niOi11O1l); + wire_niOOOlOil_dataout <= wire_niOOOOllO_dataout AND NOT(niOi11O1l); + wire_niOOOlOiO_dataout <= wire_niOOOOlOi_dataout AND NOT(niOi11O1l); + wire_niOOOlOli_dataout <= wire_niOOOOlOl_dataout AND NOT(niOi11O1l); + wire_niOOOlOll_dataout <= wire_niOOOOlOO_dataout AND NOT(niOi11O1l); + wire_niOOOlOlO_dataout <= wire_niOOOOO1i_dataout AND NOT(niOi11O1l); + wire_niOOOlOOi_dataout <= wire_niOOOOO1l_dataout AND NOT(niOi11O1l); + wire_niOOOlOOl_dataout <= wire_niOOOOO1O_dataout AND NOT(niOi11O1l); + wire_niOOOlOOO_dataout <= wire_niOOOOO0i_dataout AND NOT(niOi11O1l); + wire_niOOOO00i_dataout <= wire_nlOiO00Ol_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111il_dataout; + wire_niOOOO00l_dataout <= wire_nlOiO00OO_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111iO_dataout; + wire_niOOOO00O_dataout <= wire_nlOiO0i1i_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111li_dataout; + wire_niOOOO01i_dataout <= wire_nlOiO00ll_dataout WHEN niOi11O1O = '1' ELSE wire_nl111110l_dataout; + wire_niOOOO01l_dataout <= wire_nlOiO00lO_dataout WHEN niOi11O1O = '1' ELSE wire_nl111110O_dataout; + wire_niOOOO01O_dataout <= wire_nlOiO00Oi_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111ii_dataout; + wire_niOOOO0ii_dataout <= wire_nlOiO0i1l_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111ll_dataout; + wire_niOOOO0il_dataout <= wire_nlOiO0i1O_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111lO_dataout; + wire_niOOOO0iO_dataout <= wire_nlOiO0i0i_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111Oi_dataout; + wire_niOOOO0li_dataout <= wire_nlOiO0i0l_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111Ol_dataout; + wire_niOOOO0ll_dataout <= wire_nlOiO0i0O_dataout WHEN niOi11O1O = '1' ELSE wire_nl11111OO_dataout; + wire_niOOOO0lO_dataout <= wire_nlOiO0iii_dataout WHEN niOi11O1O = '1' ELSE wire_nl111101i_dataout; + wire_niOOOO0O_dataout <= wire_niOOOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_niOOOO0Oi_dataout <= wire_nlOiO0iil_dataout WHEN niOi11O1O = '1' ELSE wire_nl111101l_dataout; + wire_niOOOO0Ol_dataout <= wire_nlOiO0iiO_dataout WHEN niOi11O1O = '1' ELSE wire_nl111101O_dataout; + wire_niOOOO0OO_dataout <= wire_nlOiO0ili_dataout WHEN niOi11O1O = '1' ELSE wire_nl111100i_dataout; + wire_niOOOO10i_dataout <= wire_nlOiO01Ol_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOil_dataout; + wire_niOOOO10l_dataout <= wire_nlOiO01OO_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOiO_dataout; + wire_niOOOO10O_dataout <= wire_nlOiO001i_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOli_dataout; + wire_niOOOO11i_dataout <= wire_niOOOOO0l_dataout AND NOT(niOi11O1l); + wire_niOOOO11l_dataout <= wire_nlOiO01lO_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOO0O_dataout; + wire_niOOOO11O_dataout <= wire_nlOiO01Oi_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOii_dataout; + wire_niOOOO1ii_dataout <= wire_nlOiO001l_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOll_dataout; + wire_niOOOO1il_dataout <= wire_nlOiO001O_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOlO_dataout; + wire_niOOOO1iO_dataout <= wire_nlOiO000i_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOOi_dataout; + wire_niOOOO1li_dataout <= wire_nlOiO000l_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOOl_dataout; + wire_niOOOO1ll_dataout <= wire_nlOiO000O_dataout WHEN niOi11O1O = '1' ELSE wire_niOOOOOOO_dataout; + wire_niOOOO1lO_dataout <= wire_nlOiO00ii_dataout WHEN niOi11O1O = '1' ELSE wire_nl111111i_dataout; + wire_niOOOO1Oi_dataout <= wire_nlOiO00il_dataout WHEN niOi11O1O = '1' ELSE wire_nl111111l_dataout; + wire_niOOOO1Ol_dataout <= wire_nlOiO00iO_dataout WHEN niOi11O1O = '1' ELSE wire_nl111111O_dataout; + wire_niOOOO1OO_dataout <= wire_nlOiO00li_dataout WHEN niOi11O1O = '1' ELSE wire_nl111110i_dataout; + wire_niOOOOi_dataout <= lmi_din(3) AND NOT(wire_niO01l0O_dataout); + wire_niOOOOi0i_dataout <= wire_nlOiO0iOl_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110il_dataout; + wire_niOOOOi0l_dataout <= wire_nlOiO0iOO_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110iO_dataout; + wire_niOOOOi0O_dataout <= wire_nlOiO0l1i_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110li_dataout; + wire_niOOOOi1i_dataout <= wire_nlOiO0ill_dataout WHEN niOi11O1O = '1' ELSE wire_nl111100l_dataout; + wire_niOOOOi1l_dataout <= wire_nlOiO0ilO_dataout WHEN niOi11O1O = '1' ELSE wire_nl111100O_dataout; + wire_niOOOOi1O_dataout <= wire_nlOiO0iOi_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110ii_dataout; + wire_niOOOOii_dataout <= wire_nl1000i_w_lg_niOOOOiO8394w(0) WHEN (nl11111i XOR niOOOOOl) = '1' ELSE niOOOOiO; + wire_niOOOOiii_dataout <= wire_nlOiO0l1l_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110ll_dataout; + wire_niOOOOiil_dataout <= wire_nlOiO0l1O_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110lO_dataout; + wire_niOOOOiiO_dataout <= wire_nlOiO0l0i_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110Oi_dataout; + wire_niOOOOili_dataout <= wire_nlOiO0l0l_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110Ol_dataout; + wire_niOOOOill_dataout <= wire_nlOiO0l0O_dataout WHEN niOi11O1O = '1' ELSE wire_nl11110OO_dataout; + wire_niOOOOilO_dataout <= wire_nlOiO0lii_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111i1i_dataout; + wire_niOOOOiOi_dataout <= wire_nlOiO0lil_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111i1l_dataout; + wire_niOOOOiOl_dataout <= wire_nlOiO0liO_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111i1O_dataout; + wire_niOOOOiOO_dataout <= wire_nlOiO0lli_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111i0i_dataout; + wire_niOOOOl_dataout <= lmi_din(4) AND NOT(wire_niO01l0O_dataout); + wire_niOOOOl0i_dataout <= wire_nlOiO0lOl_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111iil_dataout; + wire_niOOOOl0l_dataout <= wire_nlOiO0lOO_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111iiO_dataout; + wire_niOOOOl0O_dataout <= wire_nlOiO0O1i_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111ili_dataout; + wire_niOOOOl1i_dataout <= wire_nlOiO0lll_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111i0l_dataout; + wire_niOOOOl1l_dataout <= wire_nlOiO0llO_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111i0O_dataout; + wire_niOOOOl1O_dataout <= wire_nlOiO0lOi_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111iii_dataout; + wire_niOOOOlii_dataout <= wire_nlOiO0O1l_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111ill_dataout; + wire_niOOOOlil_dataout <= wire_nlOiO0O1O_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111ilO_dataout; + wire_niOOOOliO_dataout <= wire_nlOiO0O0i_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111iOi_dataout; + wire_niOOOOll_dataout <= niOOOOOl AND NOT(wire_niO01l0O_dataout); + wire_niOOOOlli_dataout <= wire_nlOiO0O0l_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111iOl_dataout; + wire_niOOOOlll_dataout <= wire_nlOiO0O0O_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111iOO_dataout; + wire_niOOOOllO_dataout <= wire_nlOiO0Oii_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111l1i_dataout; + wire_niOOOOlOi_dataout <= wire_nlOiO0Oil_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111l1l_dataout; + wire_niOOOOlOl_dataout <= wire_nlOiO0OiO_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111l1O_dataout; + wire_niOOOOlOO_dataout <= wire_nlOiO0Oli_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111l0i_dataout; + wire_niOOOOO_dataout <= lmi_din(5) AND NOT(wire_niO01l0O_dataout); + wire_niOOOOO0i_dataout <= wire_nlOiO0OOl_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111lil_dataout; + wire_niOOOOO0l_dataout <= wire_nlOiO0OOO_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111liO_dataout; + wire_niOOOOO0O_dataout <= nlO1Oi00O WHEN niOi11O0i = '1' ELSE nlOiOi11l; + wire_niOOOOO1i_dataout <= wire_nlOiO0Oll_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111l0l_dataout; + wire_niOOOOO1l_dataout <= wire_nlOiO0OlO_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111l0O_dataout; + wire_niOOOOO1O_dataout <= wire_nlOiO0OOi_dataout WHEN niOi11O1O = '1' ELSE wire_nl1111lii_dataout; + wire_niOOOOOi_dataout <= niOOOO0l AND NOT(wire_niO01l0O_dataout); + wire_niOOOOOii_dataout <= nlO1Oi0ii WHEN niOi11O0i = '1' ELSE n1110Oii; + wire_niOOOOOil_dataout <= nlO1Oi0il WHEN niOi11O0i = '1' ELSE wire_nlOl1l0Ol_dataout; + wire_niOOOOOiO_dataout <= nlO1Oi0iO WHEN niOi11O0i = '1' ELSE nlO1Oi1Oi; + wire_niOOOOOli_dataout <= nlO1Oi0li WHEN niOi11O0i = '1' ELSE nlO1Oi1Ol; + wire_niOOOOOll_dataout <= nlO1Oi0ll WHEN niOi11O0i = '1' ELSE nlO1Oi1OO; + wire_niOOOOOlO_dataout <= nlO1Oi0lO WHEN niOi11O0i = '1' ELSE nlO1Oi01i; + wire_niOOOOOO_dataout <= nl11111l AND NOT(wire_niO01O0O_dataout); + wire_niOOOOOOi_dataout <= nlO1Oi0Oi WHEN niOi11O0i = '1' ELSE nlO1Oi01l; + wire_niOOOOOOl_dataout <= nlO1Oi0Ol WHEN niOi11O0i = '1' ELSE nlO1Oi01O; + wire_niOOOOOOO_dataout <= nlO1Oi0OO WHEN niOi11O0i = '1' ELSE nlO1Oi00i; + wire_nl000000i_dataout <= wire_nl00ii1ii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOlO_dataout; + wire_nl000000l_dataout <= wire_nl00iO01l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOOi_dataout; + wire_nl000000O_dataout <= wire_nl00ii10i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOOl_dataout; + wire_nl000001i_dataout <= wire_nl00iO00O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOiO_dataout; + wire_nl000001l_dataout <= wire_nl00ii1li_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOli_dataout; + wire_nl000001O_dataout <= wire_nl00iO00i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOll_dataout; + wire_nl00000i_dataout <= nl000lOi WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00101l; + wire_nl00000ii_dataout <= wire_nl00iO1OO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOOO_dataout; + wire_nl00000il_dataout <= wire_nl00ii11i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l11i_dataout; + wire_nl00000iO_dataout <= wire_nl00iO1Oi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l11l_dataout; + wire_nl00000l_dataout <= nl000lOl WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00101O; + wire_nl00000li_dataout <= wire_nl00i0OOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l11O_dataout; + wire_nl00000ll_dataout <= wire_nl00iO1ll_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l10i_dataout; + wire_nl00000lO_dataout <= wire_nl00i0Oli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l10l_dataout; + wire_nl00000O_dataout <= nl00ilOO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00100i; + wire_nl00000Oi_dataout <= wire_nl00iO1iO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l10O_dataout; + wire_nl00000Ol_dataout <= wire_nl00i0Oii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1ii_dataout; + wire_nl00000OO_dataout <= wire_nl00iO1ii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1il_dataout; + wire_nl000010i_dataout <= wire_nl00iOi1O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000illO_dataout; + wire_nl000010l_dataout <= wire_nl00ii0Oi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ilOi_dataout; + wire_nl000010O_dataout <= wire_nl00iOi1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ilOl_dataout; + wire_nl000011i_dataout <= wire_nl00iii0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iliO_dataout; + wire_nl000011l_dataout <= wire_nl00iOi0l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000illi_dataout; + wire_nl000011O_dataout <= wire_nl00iii1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000illl_dataout; + wire_nl00001i_dataout <= nl000lli WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011Ol; + wire_nl00001ii_dataout <= wire_nl00ii0li_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ilOO_dataout; + wire_nl00001il_dataout <= wire_nl00iO0Ol_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iO1i_dataout; + wire_nl00001iO_dataout <= wire_nl00ii0ii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iO1l_dataout; + wire_nl00001l_dataout <= nl000lll WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011OO; + wire_nl00001li_dataout <= wire_nl00iO0lO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iO1O_dataout; + wire_nl00001ll_dataout <= wire_nl00ii00i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iO0i_dataout; + wire_nl00001lO_dataout <= wire_nl00iO0li_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iO0l_dataout; + wire_nl00001O_dataout <= nl000llO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00101i; + wire_nl00001Oi_dataout <= wire_nl00ii01i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iO0O_dataout; + wire_nl00001Ol_dataout <= wire_nl00iO0il_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOii_dataout; + wire_nl00001OO_dataout <= wire_nl00ii1Oi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iOil_dataout; + wire_nl0000i_dataout <= nl01lilO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oli0l; + wire_nl0000i0i_dataout <= wire_nl00iO11O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1lO_dataout; + wire_nl0000i0l_dataout <= wire_nl00i0lOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1Oi_dataout; + wire_nl0000i0O_dataout <= wire_nl00iO11i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1Ol_dataout; + wire_nl0000i1i_dataout <= wire_nl00i0O0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1iO_dataout; + wire_nl0000i1l_dataout <= wire_nl00iO10l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1li_dataout; + wire_nl0000i1O_dataout <= wire_nl00i0O1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1ll_dataout; + wire_nl0000iii_dataout <= wire_nl00i0lli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l1OO_dataout; + wire_nl0000iil_dataout <= wire_nl00ilOOl_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l01i_dataout; + wire_nl0000iiO_dataout <= wire_nl00i0lii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l01l_dataout; + wire_nl0000ili_dataout <= wire_nl00ilOlO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l01O_dataout; + wire_nl0000ill_dataout <= wire_nl00i0l0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l00i_dataout; + wire_nl0000ilO_dataout <= wire_nl00ilOli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l00l_dataout; + wire_nl0000iOi_dataout <= wire_nl00i0l1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l00O_dataout; + wire_nl0000iOl_dataout <= wire_nl00ilOil_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0ii_dataout; + wire_nl0000iOO_dataout <= wire_nl00i0iOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0il_dataout; + wire_nl0000l_dataout <= nl01liOi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oli0O; + wire_nl0000l0i_dataout <= wire_nl00i0iii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0lO_dataout; + wire_nl0000l0l_dataout <= wire_nl00ilO1l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0Oi_dataout; + wire_nl0000l0O_dataout <= wire_nl00i0i0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0Ol_dataout; + wire_nl0000l1i_dataout <= wire_nl00ilO0O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0iO_dataout; + wire_nl0000l1l_dataout <= wire_nl00i0ili_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0li_dataout; + wire_nl0000l1O_dataout <= wire_nl00ilO0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0ll_dataout; + wire_nl0000lii_dataout <= wire_nl00illOO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000l0OO_dataout; + wire_nl0000lil_dataout <= wire_nl00i0i1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000li1i_dataout; + wire_nl0000liO_dataout <= wire_nl00illOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000li1l_dataout; + wire_nl0000lli_dataout <= wire_nl00i00Oi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000li1O_dataout; + wire_nl0000lll_dataout <= wire_nl00illll_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000li0i_dataout; + wire_nl0000llO_dataout <= wire_nl00i00li_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000li0l_dataout; + wire_nl0000lOi_dataout <= wire_nl00illiO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000li0O_dataout; + wire_nl0000lOl_dataout <= wire_nl00i00ii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000liii_dataout; + wire_nl0000lOO_dataout <= wire_nl00illii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000liil_dataout; + wire_nl0000O_dataout <= nl01liOl WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oliii; + wire_nl0000O0i_dataout <= wire_nl00ill1O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lilO_dataout; + wire_nl0000O0l_dataout <= wire_nl00i01Oi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000liOi_dataout; + wire_nl0000O0O_dataout <= wire_nl00ill1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000liOl_dataout; + wire_nl0000O1i_dataout <= wire_nl00i000i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000liiO_dataout; + wire_nl0000O1l_dataout <= wire_nl00ill0l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lili_dataout; + wire_nl0000O1O_dataout <= wire_nl00i001i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lill_dataout; + wire_nl0000Oii_dataout <= wire_nl00i01li_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000liOO_dataout; + wire_nl0000Oil_dataout <= wire_nl00iliOl_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ll1i_dataout; + wire_nl0000OiO_dataout <= wire_nl00i01ii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ll1l_dataout; + wire_nl0000Oli_dataout <= wire_nl00ililO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ll1O_dataout; + wire_nl0000Oll_dataout <= wire_nl00i010i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ll0i_dataout; + wire_nl0000OlO_dataout <= wire_nl00ilili_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ll0l_dataout; + wire_nl0000OOi_dataout <= wire_nl00i011i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ll0O_dataout; + wire_nl0000OOl_dataout <= wire_nl00iliil_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000llii_dataout; + wire_nl0000OOO_dataout <= wire_nl00i1OOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000llil_dataout; + wire_nl000100i_dataout <= wire_nl0000OlO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1lll; + wire_nl000100l_dataout <= wire_nl0000OOi_dataout WHEN niOi0lO0i = '1' ELSE nl01O1llO; + wire_nl000100O_dataout <= wire_nl0000OOl_dataout WHEN niOi0lO0i = '1' ELSE nl01O1lOi; + wire_nl000101i_dataout <= wire_nl0000OiO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1lil; + wire_nl000101l_dataout <= wire_nl0000Oli_dataout WHEN niOi0lO0i = '1' ELSE nl01O1liO; + wire_nl000101O_dataout <= wire_nl0000Oll_dataout WHEN niOi0lO0i = '1' ELSE nl01O1lli; + wire_nl00010i_dataout <= nl000iOi WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00111l; + wire_nl00010ii_dataout <= wire_nl0000OOO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1lOl; + wire_nl00010il_dataout <= wire_nl000i11i_dataout WHEN niOi0lO0i = '1' ELSE nl01O1lOO; + wire_nl00010iO_dataout <= wire_nl000i11l_dataout WHEN niOi0lO0i = '1' ELSE nl01O1O1i; + wire_nl00010l_dataout <= nl000iOl WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00111O; + wire_nl00010li_dataout <= wire_nl000i11O_dataout WHEN niOi0lO0i = '1' ELSE nl01O1O1l; + wire_nl00010ll_dataout <= wire_nl000i10i_dataout WHEN niOi0lO0i = '1' ELSE nl01O1O1O; + wire_nl00010lO_dataout <= wire_nl000i10l_dataout WHEN niOi0lO0i = '1' ELSE nl01O1O0i; + wire_nl00010O_dataout <= nl000iOO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00110i; + wire_nl00010Oi_dataout <= wire_nl000i10O_dataout WHEN niOi0lO0i = '1' ELSE nl01O1O0l; + wire_nl00010Ol_dataout <= wire_nl000i1ii_dataout WHEN niOi0lO0i = '1' ELSE nl01O1O0O; + wire_nl00010OO_dataout <= wire_nl000i1il_dataout WHEN niOi0lO0i = '1' ELSE nl01O1Oii; + wire_nl000110i_dataout <= wire_nl0000llO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1ill; + wire_nl000110l_dataout <= wire_nl0000lOi_dataout WHEN niOi0lO0i = '1' ELSE nl01O1ilO; + wire_nl000110O_dataout <= wire_nl0000lOl_dataout WHEN niOi0lO0i = '1' ELSE nl01O1iOi; + wire_nl000111i_dataout <= wire_nl0000liO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1iil; + wire_nl000111l_dataout <= wire_nl0000lli_dataout WHEN niOi0lO0i = '1' ELSE nl01O1iiO; + wire_nl000111O_dataout <= wire_nl0000lll_dataout WHEN niOi0lO0i = '1' ELSE nl01O1ili; + wire_nl00011i_dataout <= nl000ili WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOOl; + wire_nl00011ii_dataout <= wire_nl0000lOO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1iOl; + wire_nl00011il_dataout <= wire_nl0000O1i_dataout WHEN niOi0lO0i = '1' ELSE nl01O1iOO; + wire_nl00011iO_dataout <= wire_nl0000O1l_dataout WHEN niOi0lO0i = '1' ELSE nl01O1l1i; + wire_nl00011l_dataout <= nl000ill WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOOO; + wire_nl00011li_dataout <= wire_nl0000O1O_dataout WHEN niOi0lO0i = '1' ELSE nl01O1l1l; + wire_nl00011ll_dataout <= wire_nl0000O0i_dataout WHEN niOi0lO0i = '1' ELSE nl01O1l1O; + wire_nl00011lO_dataout <= wire_nl0000O0l_dataout WHEN niOi0lO0i = '1' ELSE nl01O1l0i; + wire_nl00011O_dataout <= nl000ilO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00111i; + wire_nl00011Oi_dataout <= wire_nl0000O0O_dataout WHEN niOi0lO0i = '1' ELSE nl01O1l0l; + wire_nl00011Ol_dataout <= wire_nl0000Oii_dataout WHEN niOi0lO0i = '1' ELSE nl01O1l0O; + wire_nl00011OO_dataout <= wire_nl0000Oil_dataout WHEN niOi0lO0i = '1' ELSE nl01O1lii; + wire_nl0001i_dataout <= nl01liiO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oli1l; + wire_nl0001i0i_dataout <= wire_nl000i1lO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1Oll; + wire_nl0001i0l_dataout <= wire_nl000i1Oi_dataout WHEN niOi0lO0i = '1' ELSE nl01O1OlO; + wire_nl0001i0O_dataout <= wire_nl000i1Ol_dataout WHEN niOi0lO0i = '1' ELSE nl01O1OOi; + wire_nl0001i1i_dataout <= wire_nl000i1iO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1Oil; + wire_nl0001i1l_dataout <= wire_nl000i1li_dataout WHEN niOi0lO0i = '1' ELSE nl01O1OiO; + wire_nl0001i1O_dataout <= wire_nl000i1ll_dataout WHEN niOi0lO0i = '1' ELSE nl01O1Oli; + wire_nl0001ii_dataout <= nl000l1i WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00110l; + wire_nl0001iii_dataout <= wire_nl000i1OO_dataout WHEN niOi0lO0i = '1' ELSE nl01O1OOl; + wire_nl0001iil_dataout <= wire_nl000i01i_dataout WHEN niOi0lO0i = '1' ELSE nl01O1OOO; + wire_nl0001iiO_dataout <= wire_nl000i01l_dataout WHEN niOi0lO0i = '1' ELSE nl01O011i; + wire_nl0001il_dataout <= nl000l1l WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl00110O; + wire_nl0001ili_dataout <= wire_nl00il1Oi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i01O_dataout; + wire_nl0001ill_dataout <= wire_nl00iOOll_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i00i_dataout; + wire_nl0001ilO_dataout <= wire_nl00il1li_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i00l_dataout; + wire_nl0001iO_dataout <= nl000l1O WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011ii; + wire_nl0001iOi_dataout <= wire_nl00iOOiO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i00O_dataout; + wire_nl0001iOl_dataout <= wire_nl00il1ii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0ii_dataout; + wire_nl0001iOO_dataout <= wire_nl00iOOii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0il_dataout; + wire_nl0001l_dataout <= nl01lili WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oli1O; + wire_nl0001l0i_dataout <= wire_nl00iOO1O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0lO_dataout; + wire_nl0001l0l_dataout <= wire_nl00iiOOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0Oi_dataout; + wire_nl0001l0O_dataout <= wire_nl00iOO1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0Ol_dataout; + wire_nl0001l1i_dataout <= wire_nl00il10i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0iO_dataout; + wire_nl0001l1l_dataout <= wire_nl00iOO0l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0li_dataout; + wire_nl0001l1O_dataout <= wire_nl00il11i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0ll_dataout; + wire_nl0001li_dataout <= nl000l0i WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011il; + wire_nl0001lii_dataout <= wire_nl00iiOli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000i0OO_dataout; + wire_nl0001lil_dataout <= wire_nl00iOlOl_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ii1i_dataout; + wire_nl0001liO_dataout <= wire_nl00iiOii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ii1l_dataout; + wire_nl0001ll_dataout <= nl000l0l WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011iO; + wire_nl0001lli_dataout <= wire_nl00iOllO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ii1O_dataout; + wire_nl0001lll_dataout <= wire_nl00iiO0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ii0i_dataout; + wire_nl0001llO_dataout <= wire_nl00iOlli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ii0l_dataout; + wire_nl0001lO_dataout <= nl000l0O WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011li; + wire_nl0001lOi_dataout <= wire_nl00iiO1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ii0O_dataout; + wire_nl0001lOl_dataout <= wire_nl00iOlil_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iiii_dataout; + wire_nl0001lOO_dataout <= wire_nl00iilOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iiil_dataout; + wire_nl0001O_dataout <= nl01lill WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oli0i; + wire_nl0001O0i_dataout <= wire_nl00iilii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iilO_dataout; + wire_nl0001O0l_dataout <= wire_nl00iOl1l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iiOi_dataout; + wire_nl0001O0O_dataout <= wire_nl00iil0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iiOl_dataout; + wire_nl0001O1i_dataout <= wire_nl00iOl0O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iiiO_dataout; + wire_nl0001O1l_dataout <= wire_nl00iilli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iili_dataout; + wire_nl0001O1O_dataout <= wire_nl00iOl0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iill_dataout; + wire_nl0001Oi_dataout <= nl000lii WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011ll; + wire_nl0001Oii_dataout <= wire_nl00iOiOO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000iiOO_dataout; + wire_nl0001Oil_dataout <= wire_nl00iil1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000il1i_dataout; + wire_nl0001OiO_dataout <= wire_nl00iOiOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000il1l_dataout; + wire_nl0001Ol_dataout <= nl000lil WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011lO; + wire_nl0001Oli_dataout <= wire_nl00iiiOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000il1O_dataout; + wire_nl0001Oll_dataout <= wire_nl00iOill_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000il0i_dataout; + wire_nl0001OlO_dataout <= wire_nl00iiili_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000il0l_dataout; + wire_nl0001OO_dataout <= nl000liO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl0011Oi; + wire_nl0001OOi_dataout <= wire_nl00iOiiO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000il0O_dataout; + wire_nl0001OOl_dataout <= wire_nl00iiiii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ilii_dataout; + wire_nl0001OOO_dataout <= wire_nl00iOiii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000ilil_dataout; + wire_nl000i00i_dataout <= wire_nl00iOOll_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000lOlO_dataout; + wire_nl000i00l_dataout <= wire_nl00iOOil_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000lOOi_dataout; + wire_nl000i00O_dataout <= wire_nl00iOOiO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000lOOl_dataout; + wire_nl000i01i_dataout <= wire_nl00i1l0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lOiO_dataout; + wire_nl000i01l_dataout <= wire_nl00il00l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lOli_dataout; + wire_nl000i01O_dataout <= wire_nl00iOOli_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000lOll_dataout; + wire_nl000i0ii_dataout <= wire_nl00iOO0O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000lOOO_dataout; + wire_nl000i0il_dataout <= wire_nl00iOOii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O11i_dataout; + wire_nl000i0iO_dataout <= wire_nl00iOO0i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O11l_dataout; + wire_nl000i0li_dataout <= wire_nl00iOO0l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O11O_dataout; + wire_nl000i0ll_dataout <= wire_nl00iOO1l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O10i_dataout; + wire_nl000i0lO_dataout <= wire_nl00iOO1O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O10l_dataout; + wire_nl000i0Oi_dataout <= wire_nl00iOlOO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O10O_dataout; + wire_nl000i0Ol_dataout <= wire_nl00iOO1i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1ii_dataout; + wire_nl000i0OO_dataout <= wire_nl00iOlOi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1il_dataout; + wire_nl000i10i_dataout <= wire_nl00i1Oii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lllO_dataout; + wire_nl000i10l_dataout <= wire_nl00ili1l_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000llOi_dataout; + wire_nl000i10O_dataout <= wire_nl00i1O0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000llOl_dataout; + wire_nl000i11i_dataout <= wire_nl00ili0O_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lliO_dataout; + wire_nl000i11l_dataout <= wire_nl00i1Oli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000llli_dataout; + wire_nl000i11O_dataout <= wire_nl00ili0i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000llll_dataout; + wire_nl000i1ii_dataout <= wire_nl00il0OO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000llOO_dataout; + wire_nl000i1il_dataout <= wire_nl00i1O1i_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lO1i_dataout; + wire_nl000i1iO_dataout <= wire_nl00il0Oi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lO1l_dataout; + wire_nl000i1li_dataout <= wire_nl00i1lOi_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lO1O_dataout; + wire_nl000i1ll_dataout <= wire_nl00il0ll_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lO0i_dataout; + wire_nl000i1lO_dataout <= wire_nl00i1lli_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lO0l_dataout; + wire_nl000i1Oi_dataout <= wire_nl00il0iO_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lO0O_dataout; + wire_nl000i1Ol_dataout <= wire_nl00i1lii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lOii_dataout; + wire_nl000i1OO_dataout <= wire_nl00il0ii_dataout WHEN niOi0lO1O = '1' ELSE wire_nl000lOil_dataout; + wire_nl000ii_dataout <= nl0l0iii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oliil; + wire_nl000ii0i_dataout <= wire_nl00iOliO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1lO_dataout; + wire_nl000ii0l_dataout <= wire_nl00iOlli_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1Oi_dataout; + wire_nl000ii0O_dataout <= wire_nl00iOlii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1Ol_dataout; + wire_nl000ii1i_dataout <= wire_nl00iOlOl_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1iO_dataout; + wire_nl000ii1l_dataout <= wire_nl00iOlll_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1li_dataout; + wire_nl000ii1O_dataout <= wire_nl00iOllO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1ll_dataout; + wire_nl000iiii_dataout <= wire_nl00iOlil_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O1OO_dataout; + wire_nl000iiil_dataout <= wire_nl00iOl0l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O01i_dataout; + wire_nl000iiiO_dataout <= wire_nl00iOl0O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O01l_dataout; + wire_nl000iili_dataout <= wire_nl00iOl1O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O01O_dataout; + wire_nl000iill_dataout <= wire_nl00iOl0i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O00i_dataout; + wire_nl000iilO_dataout <= wire_nl00iOl1i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O00l_dataout; + wire_nl000iiOi_dataout <= wire_nl00iOl1l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O00O_dataout; + wire_nl000iiOl_dataout <= wire_nl00iOiOl_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0ii_dataout; + wire_nl000iiOO_dataout <= wire_nl00iOiOO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0il_dataout; + wire_nl000il_dataout <= nl0l0iil WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0OliiO; + wire_nl000il0i_dataout <= wire_nl00iOill_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0lO_dataout; + wire_nl000il0l_dataout <= wire_nl00iOiil_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0Oi_dataout; + wire_nl000il0O_dataout <= wire_nl00iOiiO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0Ol_dataout; + wire_nl000il1i_dataout <= wire_nl00iOilO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0iO_dataout; + wire_nl000il1l_dataout <= wire_nl00iOiOi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0li_dataout; + wire_nl000il1O_dataout <= wire_nl00iOili_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0ll_dataout; + wire_nl000ilii_dataout <= wire_nl00iOi0O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000O0OO_dataout; + wire_nl000ilil_dataout <= wire_nl00iOiii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oi1i_dataout; + wire_nl000iliO_dataout <= wire_nl00iOi0i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oi1l_dataout; + wire_nl000illi_dataout <= wire_nl00iOi0l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oi1O_dataout; + wire_nl000illl_dataout <= wire_nl00iOi1l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oi0i_dataout; + wire_nl000illO_dataout <= wire_nl00iOi1O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oi0l_dataout; + wire_nl000ilOi_dataout <= wire_nl00iO0OO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oi0O_dataout; + wire_nl000ilOl_dataout <= wire_nl00iOi1i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oiii_dataout; + wire_nl000ilOO_dataout <= wire_nl00iO0Oi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oiil_dataout; + wire_nl000iO_dataout <= nl0l0iiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl000iO0i_dataout <= wire_nl00iO0iO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OilO_dataout; + wire_nl000iO0l_dataout <= wire_nl00iO0li_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OiOi_dataout; + wire_nl000iO0O_dataout <= wire_nl00iO0ii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OiOl_dataout; + wire_nl000iO1i_dataout <= wire_nl00iO0Ol_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OiiO_dataout; + wire_nl000iO1l_dataout <= wire_nl00iO0ll_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oili_dataout; + wire_nl000iO1O_dataout <= wire_nl00iO0lO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Oill_dataout; + wire_nl000iOii_dataout <= wire_nl00iO0il_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OiOO_dataout; + wire_nl000iOil_dataout <= wire_nl00iO00l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Ol1i_dataout; + wire_nl000iOiO_dataout <= wire_nl00iO00O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Ol1l_dataout; + wire_nl000iOli_dataout <= wire_nl00iO01O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Ol1O_dataout; + wire_nl000iOll_dataout <= wire_nl00iO00i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Ol0i_dataout; + wire_nl000iOlO_dataout <= wire_nl00iO01i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Ol0l_dataout; + wire_nl000iOOi_dataout <= wire_nl00iO01l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Ol0O_dataout; + wire_nl000iOOl_dataout <= wire_nl00iO1Ol_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Olii_dataout; + wire_nl000iOOO_dataout <= wire_nl00iO1OO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Olil_dataout; + wire_nl000l00i_dataout <= wire_nl00ilOiO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOlO_dataout; + wire_nl000l00l_dataout <= wire_nl00ilOli_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOOi_dataout; + wire_nl000l00O_dataout <= wire_nl00ilOii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOOl_dataout; + wire_nl000l01i_dataout <= wire_nl00ilOOl_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOiO_dataout; + wire_nl000l01l_dataout <= wire_nl00ilOll_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOli_dataout; + wire_nl000l01O_dataout <= wire_nl00ilOlO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOll_dataout; + wire_nl000l0ii_dataout <= wire_nl00ilOil_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOOO_dataout; + wire_nl000l0il_dataout <= wire_nl00ilO0l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i111i_dataout; + wire_nl000l0iO_dataout <= wire_nl00ilO0O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i111l_dataout; + wire_nl000l0li_dataout <= wire_nl00ilO1O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i111O_dataout; + wire_nl000l0ll_dataout <= wire_nl00ilO0i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i110i_dataout; + wire_nl000l0lO_dataout <= wire_nl00ilO1i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i110l_dataout; + wire_nl000l0Oi_dataout <= wire_nl00ilO1l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i110O_dataout; + wire_nl000l0Ol_dataout <= wire_nl00illOl_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11ii_dataout; + wire_nl000l0OO_dataout <= wire_nl00illOO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11il_dataout; + wire_nl000l10i_dataout <= wire_nl00iO1ll_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OllO_dataout; + wire_nl000l10l_dataout <= wire_nl00iO1il_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OlOi_dataout; + wire_nl000l10O_dataout <= wire_nl00iO1iO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OlOl_dataout; + wire_nl000l11i_dataout <= wire_nl00iO1lO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OliO_dataout; + wire_nl000l11l_dataout <= wire_nl00iO1Oi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Olli_dataout; + wire_nl000l11O_dataout <= wire_nl00iO1li_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000Olll_dataout; + wire_nl000l1ii_dataout <= wire_nl00iO10O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OlOO_dataout; + wire_nl000l1il_dataout <= wire_nl00iO1ii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OO1i_dataout; + wire_nl000l1iO_dataout <= wire_nl00iO10i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OO1l_dataout; + wire_nl000l1li_dataout <= wire_nl00iO10l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OO1O_dataout; + wire_nl000l1ll_dataout <= wire_nl00iO11l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OO0i_dataout; + wire_nl000l1lO_dataout <= wire_nl00iO11O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OO0l_dataout; + wire_nl000l1Oi_dataout <= wire_nl00ilOOO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OO0O_dataout; + wire_nl000l1Ol_dataout <= wire_nl00iO11i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOii_dataout; + wire_nl000l1OO_dataout <= wire_nl00ilOOi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl000OOil_dataout; + wire_nl000li_dataout <= nl0iOl1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl000li0i_dataout <= wire_nl00illll_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11lO_dataout; + wire_nl000li0l_dataout <= wire_nl00illil_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11Oi_dataout; + wire_nl000li0O_dataout <= wire_nl00illiO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11Ol_dataout; + wire_nl000li1i_dataout <= wire_nl00illlO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11iO_dataout; + wire_nl000li1l_dataout <= wire_nl00illOi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11li_dataout; + wire_nl000li1O_dataout <= wire_nl00illli_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11ll_dataout; + wire_nl000liii_dataout <= wire_nl00ill0O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i11OO_dataout; + wire_nl000liil_dataout <= wire_nl00illii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i101i_dataout; + wire_nl000liiO_dataout <= wire_nl00ill0i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i101l_dataout; + wire_nl000lili_dataout <= wire_nl00ill0l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i101O_dataout; + wire_nl000lill_dataout <= wire_nl00ill1l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i100i_dataout; + wire_nl000lilO_dataout <= wire_nl00ill1O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i100l_dataout; + wire_nl000liOi_dataout <= wire_nl00iliOO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i100O_dataout; + wire_nl000liOl_dataout <= wire_nl00ill1i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10ii_dataout; + wire_nl000liOO_dataout <= wire_nl00iliOi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10il_dataout; + wire_nl000ll_dataout <= nl0l0i0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl000ll0i_dataout <= wire_nl00iliiO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10lO_dataout; + wire_nl000ll0l_dataout <= wire_nl00ilili_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10Oi_dataout; + wire_nl000ll0O_dataout <= wire_nl00iliii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10Ol_dataout; + wire_nl000ll1i_dataout <= wire_nl00iliOl_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10iO_dataout; + wire_nl000ll1l_dataout <= wire_nl00ilill_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10li_dataout; + wire_nl000ll1O_dataout <= wire_nl00ililO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10ll_dataout; + wire_nl000llii_dataout <= wire_nl00iliil_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i10OO_dataout; + wire_nl000llil_dataout <= wire_nl00ili0l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1i1i_dataout; + wire_nl000lliO_dataout <= wire_nl00ili0O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1i1l_dataout; + wire_nl000llli_dataout <= wire_nl00ili1O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1i1O_dataout; + wire_nl000llll_dataout <= wire_nl00ili0i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1i0i_dataout; + wire_nl000lllO_dataout <= wire_nl00ili1i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1i0l_dataout; + wire_nl000llOi_dataout <= wire_nl00ili1l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1i0O_dataout; + wire_nl000llOl_dataout <= wire_nl00il0Ol_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1iii_dataout; + wire_nl000llOO_dataout <= wire_nl00il0OO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1iil_dataout; + wire_nl000lO_dataout <= nl0l0i0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl000lO0i_dataout <= wire_nl00il0ll_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1ilO_dataout; + wire_nl000lO0l_dataout <= wire_nl00il0il_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1iOi_dataout; + wire_nl000lO0O_dataout <= wire_nl00il0iO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1iOl_dataout; + wire_nl000lO1i_dataout <= wire_nl00il0lO_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1iiO_dataout; + wire_nl000lO1l_dataout <= wire_nl00il0Oi_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1ili_dataout; + wire_nl000lO1O_dataout <= wire_nl00il0li_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1ill_dataout; + wire_nl000lOii_dataout <= wire_nl00il00O_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1iOO_dataout; + wire_nl000lOil_dataout <= wire_nl00il0ii_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1l1i_dataout; + wire_nl000lOiO_dataout <= wire_nl00il00i_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1l1l_dataout; + wire_nl000lOli_dataout <= wire_nl00il00l_dataout WHEN niOi0lO1i = '1' ELSE wire_nl00i1l1O_dataout; + wire_nl000lOll_dataout <= wire_nl00il1Oi_dataout WHEN niOi0iOll = '1' ELSE nl01lO0iO; + wire_nl000lOlO_dataout <= wire_nl00il1Ol_dataout WHEN niOi0iOll = '1' ELSE nl01lO0li; + wire_nl000lOOi_dataout <= wire_nl00il1li_dataout WHEN niOi0iOll = '1' ELSE nl01lO0ll; + wire_nl000lOOl_dataout <= wire_nl00il1ll_dataout WHEN niOi0iOll = '1' ELSE nl01lO0lO; + wire_nl000lOOO_dataout <= wire_nl00il1ii_dataout WHEN niOi0iOll = '1' ELSE nl01lO0Oi; + wire_nl000O00i_dataout <= wire_nl00iilll_dataout WHEN niOi0iOll = '1' ELSE nl01lOl1l; + wire_nl000O00l_dataout <= wire_nl00iilii_dataout WHEN niOi0iOll = '1' ELSE nl01lOl1O; + wire_nl000O00O_dataout <= wire_nl00iilil_dataout WHEN niOi0iOll = '1' ELSE nl01lOl0i; + wire_nl000O01i_dataout <= wire_nl00iilOi_dataout WHEN niOi0iOll = '1' ELSE nl01lOiOl; + wire_nl000O01l_dataout <= wire_nl00iilOl_dataout WHEN niOi0iOll = '1' ELSE nl01lOiOO; + wire_nl000O01O_dataout <= wire_nl00iilli_dataout WHEN niOi0iOll = '1' ELSE nl01lOl1i; + wire_nl000O0i_dataout <= wire_nl00i0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000O0ii_dataout <= wire_nl00iil0i_dataout WHEN niOi0iOll = '1' ELSE nl01lOl0l; + wire_nl000O0il_dataout <= wire_nl00iil0l_dataout WHEN niOi0iOll = '1' ELSE nl01lOl0O; + wire_nl000O0iO_dataout <= wire_nl00iil1i_dataout WHEN niOi0iOll = '1' ELSE nl01lOlii; + wire_nl000O0l_dataout <= wire_nl00i0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000O0li_dataout <= wire_nl00iil1l_dataout WHEN niOi0iOll = '1' ELSE nl01lOlil; + wire_nl000O0ll_dataout <= wire_nl00iiiOi_dataout WHEN niOi0iOll = '1' ELSE nl01lOliO; + wire_nl000O0lO_dataout <= wire_nl00iiiOl_dataout WHEN niOi0iOll = '1' ELSE nl01lOlli; + wire_nl000O0O_dataout <= wire_nl00i0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000O0Oi_dataout <= wire_nl00iiili_dataout WHEN niOi0iOll = '1' ELSE nl01lOlll; + wire_nl000O0Ol_dataout <= wire_nl00iiill_dataout WHEN niOi0iOll = '1' ELSE nl01lOllO; + wire_nl000O0OO_dataout <= wire_nl00iiiii_dataout WHEN niOi0iOll = '1' ELSE nl01lOlOi; + wire_nl000O10i_dataout <= wire_nl00il11i_dataout WHEN niOi0iOll = '1' ELSE nl01lOi1l; + wire_nl000O10l_dataout <= wire_nl00il11l_dataout WHEN niOi0iOll = '1' ELSE nl01lOi1O; + wire_nl000O10O_dataout <= wire_nl00iiOOi_dataout WHEN niOi0iOll = '1' ELSE nl01lOi0i; + wire_nl000O11i_dataout <= wire_nl00il1il_dataout WHEN niOi0iOll = '1' ELSE nl01lO0Ol; + wire_nl000O11l_dataout <= wire_nl00il10i_dataout WHEN niOi0iOll = '1' ELSE nl01lO0OO; + wire_nl000O11O_dataout <= wire_nl00il10l_dataout WHEN niOi0iOll = '1' ELSE nl01lOi1i; + wire_nl000O1i_dataout <= wire_nl00i0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000O1ii_dataout <= wire_nl00iiOOl_dataout WHEN niOi0iOll = '1' ELSE nl01lOi0l; + wire_nl000O1il_dataout <= wire_nl00iiOli_dataout WHEN niOi0iOll = '1' ELSE nl01lOi0O; + wire_nl000O1iO_dataout <= wire_nl00iiOll_dataout WHEN niOi0iOll = '1' ELSE nl01lOiii; + wire_nl000O1l_dataout <= wire_nl00i0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000O1li_dataout <= wire_nl00iiOii_dataout WHEN niOi0iOll = '1' ELSE nl01lOiil; + wire_nl000O1ll_dataout <= wire_nl00iiOil_dataout WHEN niOi0iOll = '1' ELSE nl01lOiiO; + wire_nl000O1lO_dataout <= wire_nl00iiO0i_dataout WHEN niOi0iOll = '1' ELSE nl01lOili; + wire_nl000O1O_dataout <= wire_nl00i0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000O1Oi_dataout <= wire_nl00iiO0l_dataout WHEN niOi0iOll = '1' ELSE nl01lOill; + wire_nl000O1Ol_dataout <= wire_nl00iiO1i_dataout WHEN niOi0iOll = '1' ELSE nl01lOilO; + wire_nl000O1OO_dataout <= wire_nl00iiO1l_dataout WHEN niOi0iOll = '1' ELSE nl01lOiOi; + wire_nl000Oi_dataout <= nl01liOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl000Oi0i_dataout <= wire_nl00iii1i_dataout WHEN niOi0iOll = '1' ELSE nl01lOO1l; + wire_nl000Oi0l_dataout <= wire_nl00iii1l_dataout WHEN niOi0iOll = '1' ELSE nl01lOO1O; + wire_nl000Oi0O_dataout <= wire_nl00ii0Oi_dataout WHEN niOi0iOll = '1' ELSE nl01lOO0i; + wire_nl000Oi1i_dataout <= wire_nl00iiiil_dataout WHEN niOi0iOll = '1' ELSE nl01lOlOl; + wire_nl000Oi1l_dataout <= wire_nl00iii0i_dataout WHEN niOi0iOll = '1' ELSE nl01lOlOO; + wire_nl000Oi1O_dataout <= wire_nl00iii0l_dataout WHEN niOi0iOll = '1' ELSE nl01lOO1i; + wire_nl000Oii_dataout <= wire_nl00i0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000Oiii_dataout <= wire_nl00ii0Ol_dataout WHEN niOi0iOll = '1' ELSE nl01lOO0l; + wire_nl000Oiil_dataout <= wire_nl00ii0li_dataout WHEN niOi0iOll = '1' ELSE nl01lOO0O; + wire_nl000OiiO_dataout <= wire_nl00ii0ll_dataout WHEN niOi0iOll = '1' ELSE nl01lOOii; + wire_nl000Oil_dataout <= wire_nl00i0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000Oili_dataout <= wire_nl00ii0ii_dataout WHEN niOi0iOll = '1' ELSE nl01lOOil; + wire_nl000Oill_dataout <= wire_nl00ii0il_dataout WHEN niOi0iOll = '1' ELSE nl01lOOiO; + wire_nl000OilO_dataout <= wire_nl00ii00i_dataout WHEN niOi0iOll = '1' ELSE nl01lOOli; + wire_nl000OiO_dataout <= wire_nl00ii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000OiOi_dataout <= wire_nl00ii00l_dataout WHEN niOi0iOll = '1' ELSE nl01lOOll; + wire_nl000OiOl_dataout <= wire_nl00ii01i_dataout WHEN niOi0iOll = '1' ELSE nl01lOOlO; + wire_nl000OiOO_dataout <= wire_nl00ii01l_dataout WHEN niOi0iOll = '1' ELSE nl01lOOOi; + wire_nl000Ol_dataout <= nl01ll1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl000Ol0i_dataout <= wire_nl00ii1ll_dataout WHEN niOi0iOll = '1' ELSE nl01O111l; + wire_nl000Ol0l_dataout <= wire_nl00ii1ii_dataout WHEN niOi0iOll = '1' ELSE nl01O111O; + wire_nl000Ol0O_dataout <= wire_nl00ii1il_dataout WHEN niOi0iOll = '1' ELSE nl01O110i; + wire_nl000Ol1i_dataout <= wire_nl00ii1Oi_dataout WHEN niOi0iOll = '1' ELSE nl01lOOOl; + wire_nl000Ol1l_dataout <= wire_nl00ii1Ol_dataout WHEN niOi0iOll = '1' ELSE nl01lOOOO; + wire_nl000Ol1O_dataout <= wire_nl00ii1li_dataout WHEN niOi0iOll = '1' ELSE nl01O111i; + wire_nl000Oli_dataout <= wire_nl00ii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000Olii_dataout <= wire_nl00ii10i_dataout WHEN niOi0iOll = '1' ELSE nl01O110l; + wire_nl000Olil_dataout <= wire_nl00ii10l_dataout WHEN niOi0iOll = '1' ELSE nl01O110O; + wire_nl000OliO_dataout <= wire_nl00ii11i_dataout WHEN niOi0iOll = '1' ELSE nl01O11ii; + wire_nl000Oll_dataout <= wire_nl00ii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000Olli_dataout <= wire_nl00ii11l_dataout WHEN niOi0iOll = '1' ELSE nl01O11il; + wire_nl000Olll_dataout <= wire_nl00i0OOi_dataout WHEN niOi0iOll = '1' ELSE nl01O11iO; + wire_nl000OllO_dataout <= wire_nl00i0OOl_dataout WHEN niOi0iOll = '1' ELSE nl01O11li; + wire_nl000OlO_dataout <= wire_nl00ii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000OlOi_dataout <= wire_nl00i0Oli_dataout WHEN niOi0iOll = '1' ELSE nl01O11ll; + wire_nl000OlOl_dataout <= wire_nl00i0Oll_dataout WHEN niOi0iOll = '1' ELSE nl01O11lO; + wire_nl000OlOO_dataout <= wire_nl00i0Oii_dataout WHEN niOi0iOll = '1' ELSE nl01O11Oi; + wire_nl000OO_dataout <= nl01ll1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl000OO0i_dataout <= wire_nl00i0O1i_dataout WHEN niOi0iOll = '1' ELSE nl01O101l; + wire_nl000OO0l_dataout <= wire_nl00i0O1l_dataout WHEN niOi0iOll = '1' ELSE nl01O101O; + wire_nl000OO0O_dataout <= wire_nl00i0lOi_dataout WHEN niOi0iOll = '1' ELSE nl01O100i; + wire_nl000OO1i_dataout <= wire_nl00i0Oil_dataout WHEN niOi0iOll = '1' ELSE nl01O11Ol; + wire_nl000OO1l_dataout <= wire_nl00i0O0i_dataout WHEN niOi0iOll = '1' ELSE nl01O11OO; + wire_nl000OO1O_dataout <= wire_nl00i0O0l_dataout WHEN niOi0iOll = '1' ELSE nl01O101i; + wire_nl000OOi_dataout <= wire_nl00ii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000OOii_dataout <= wire_nl00i0lOl_dataout WHEN niOi0iOll = '1' ELSE nl01O100l; + wire_nl000OOil_dataout <= wire_nl00i0lli_dataout WHEN niOi0iOll = '1' ELSE nl01O100O; + wire_nl000OOiO_dataout <= wire_nl00i0lll_dataout WHEN niOi0iOll = '1' ELSE nl01O10ii; + wire_nl000OOl_dataout <= wire_nl00ii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000OOli_dataout <= wire_nl00i0lii_dataout WHEN niOi0iOll = '1' ELSE nl01O10il; + wire_nl000OOll_dataout <= wire_nl00i0lil_dataout WHEN niOi0iOll = '1' ELSE nl01O10iO; + wire_nl000OOlO_dataout <= wire_nl00i0l0i_dataout WHEN niOi0iOll = '1' ELSE nl01O10li; + wire_nl000OOO_dataout <= wire_nl00iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl000OOOi_dataout <= wire_nl00i0l0l_dataout WHEN niOi0iOll = '1' ELSE nl01O10ll; + wire_nl000OOOl_dataout <= wire_nl00i0l1i_dataout WHEN niOi0iOll = '1' ELSE nl01O10lO; + wire_nl000OOOO_dataout <= wire_nl00i0l1l_dataout WHEN niOi0iOll = '1' ELSE nl01O10Oi; + wire_nl001000i_dataout <= wire_nl0001i0l_dataout AND NOT(niOi0i10O); + wire_nl001000O_dataout <= wire_nl0001i1l_dataout AND NOT(niOi0i1ii); + wire_nl001001i_dataout <= wire_nl0001iii_dataout AND NOT(niOi0i10l); + wire_nl001001O_dataout <= wire_nl0001i0i_dataout AND NOT(niOi0i10O); + wire_nl00100ii_dataout <= wire_nl0001i1O_dataout AND NOT(niOi0i1ii); + wire_nl00100iO_dataout <= wire_nl00010OO_dataout AND NOT(niOi0i1il); + wire_nl00100l_dataout <= wire_nl001lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00100li_dataout <= wire_nl0001i1i_dataout AND NOT(niOi0i1il); + wire_nl00100lO_dataout <= wire_nl00010Oi_dataout AND NOT(niOi0i1iO); + wire_nl00100O_dataout <= wire_nl001lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00100Oi_dataout <= wire_nl00010Ol_dataout AND NOT(niOi0i1iO); + wire_nl00100OO_dataout <= wire_nl00010ll_dataout AND NOT(niOi0i1li); + wire_nl001010i_dataout <= wire_nl001000O_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001i1l_dataout; + wire_nl001010l_dataout <= wire_nl00100ii_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001i1O_dataout; + wire_nl001010O_dataout <= wire_nl001001O_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001i0i_dataout; + wire_nl001011i_dataout <= wire_nl00100Oi_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010Ol_dataout; + wire_nl001011l_dataout <= wire_nl00100iO_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010OO_dataout; + wire_nl001011O_dataout <= wire_nl00100li_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001i1i_dataout; + wire_nl00101ii_dataout <= wire_nl001000i_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001i0l_dataout; + wire_nl00101il_dataout <= wire_nl00101OO_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001i0O_dataout; + wire_nl00101iO_dataout <= wire_nl001001i_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001iii_dataout; + wire_nl00101li_dataout <= wire_nl00101lO_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001iil_dataout; + wire_nl00101ll_dataout <= wire_nl00101Oi_dataout WHEN niOi0iOil = '1' ELSE wire_nl0001iiO_dataout; + wire_nl00101lO_dataout <= wire_nl0001iil_dataout AND NOT(niOi0i10i); + wire_nl00101Oi_dataout <= wire_nl0001iiO_dataout AND NOT(niOi0i10i); + wire_nl00101OO_dataout <= wire_nl0001i0O_dataout AND NOT(niOi0i10l); + wire_nl0010i_dataout <= nl00llOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0010i0i_dataout <= wire_nl00010li_dataout AND NOT(niOi0i1ll); + wire_nl0010i0O_dataout <= wire_nl00010ii_dataout AND NOT(niOi0i1lO); + wire_nl0010i1i_dataout <= wire_nl00010lO_dataout AND NOT(niOi0i1li); + wire_nl0010i1O_dataout <= wire_nl00010iO_dataout AND NOT(niOi0i1ll); + wire_nl0010ii_dataout <= wire_nl001O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010iii_dataout <= wire_nl00010il_dataout AND NOT(niOi0i1lO); + wire_nl0010iiO_dataout <= wire_nl000100l_dataout AND NOT(niOi0i1Oi); + wire_nl0010il_dataout <= wire_nl001O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010ili_dataout <= wire_nl000100O_dataout AND NOT(niOi0i1Oi); + wire_nl0010ilO_dataout <= wire_nl000101O_dataout AND NOT(niOi0i1Ol); + wire_nl0010iO_dataout <= wire_nl001O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010iOi_dataout <= wire_nl000100i_dataout AND NOT(niOi0i1Ol); + wire_nl0010iOO_dataout <= wire_nl000101i_dataout AND NOT(niOi0i1OO); + wire_nl0010l_dataout <= nl00llOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0010l0i_dataout <= wire_nl00011OO_dataout AND NOT(niOi0i01i); + wire_nl0010l0O_dataout <= wire_nl00011lO_dataout AND NOT(niOi0i01l); + wire_nl0010l1i_dataout <= wire_nl000101l_dataout AND NOT(niOi0i1OO); + wire_nl0010l1O_dataout <= wire_nl00011Ol_dataout AND NOT(niOi0i01i); + wire_nl0010li_dataout <= wire_nl001O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010lii_dataout <= wire_nl00011Oi_dataout AND NOT(niOi0i01l); + wire_nl0010liO_dataout <= wire_nl00011li_dataout AND NOT(niOi0i01O); + wire_nl0010ll_dataout <= wire_nl001O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010lli_dataout <= wire_nl00011ll_dataout AND NOT(niOi0i01O); + wire_nl0010llO_dataout <= wire_nl00011il_dataout AND NOT(niOi0i00i); + wire_nl0010lO_dataout <= wire_nl001O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010lOi_dataout <= wire_nl00011iO_dataout AND NOT(niOi0i00i); + wire_nl0010lOO_dataout <= wire_nl000110O_dataout AND NOT(niOi0i00l); + wire_nl0010O_dataout <= nl00llOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0010O0i_dataout <= wire_nl000110l_dataout AND NOT(niOi0i00O); + wire_nl0010O0O_dataout <= wire_nl000111l_dataout AND NOT(niOi0i0ii); + wire_nl0010O1i_dataout <= wire_nl00011ii_dataout AND NOT(niOi0i00l); + wire_nl0010O1O_dataout <= wire_nl000110i_dataout AND NOT(niOi0i00O); + wire_nl0010Oi_dataout <= wire_nl001Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010Oii_dataout <= wire_nl000111O_dataout AND NOT(niOi0i0ii); + wire_nl0010OiO_dataout <= wire_nl001OOOO_dataout AND NOT(niOi0i0il); + wire_nl0010Ol_dataout <= wire_nl001Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010Oli_dataout <= wire_nl000111i_dataout AND NOT(niOi0i0il); + wire_nl0010OlO_dataout <= wire_nl001OOOi_dataout AND NOT(niOi0i0iO); + wire_nl0010OO_dataout <= wire_nl001OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0010OOi_dataout <= wire_nl001OOOl_dataout AND NOT(niOi0i0iO); + wire_nl0010OOO_dataout <= wire_nl001OOll_dataout AND NOT(niOi0i0li); + wire_nl001100i_dataout <= wire_nl001ii0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Ol1l_dataout; + wire_nl001100l_dataout <= wire_nl001iiii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Ol1O_dataout; + wire_nl001100O_dataout <= wire_nl001ii1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Ol0i_dataout; + wire_nl001101i_dataout <= wire_nl001iiOi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OiOl_dataout; + wire_nl001101l_dataout <= wire_nl001iiiO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OiOO_dataout; + wire_nl001101O_dataout <= wire_nl001iili_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Ol1i_dataout; + wire_nl00110ii_dataout <= wire_nl001ii0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Ol0l_dataout; + wire_nl00110il_dataout <= wire_nl001i0OO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Ol0O_dataout; + wire_nl00110iO_dataout <= wire_nl001ii1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Olii_dataout; + wire_nl00110li_dataout <= wire_nl001i0lO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Olil_dataout; + wire_nl00110ll_dataout <= wire_nl001i0Oi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OliO_dataout; + wire_nl00110lO_dataout <= wire_nl001i0iO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Olli_dataout; + wire_nl00110Oi_dataout <= wire_nl001i0li_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Olll_dataout; + wire_nl00110Ol_dataout <= wire_nl001i00O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OllO_dataout; + wire_nl00110OO_dataout <= wire_nl001i0ii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OlOi_dataout; + wire_nl001110i_dataout <= wire_nl001iO1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oi1l_dataout; + wire_nl001110l_dataout <= wire_nl001illO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oi1O_dataout; + wire_nl001110O_dataout <= wire_nl001ilOi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oi0i_dataout; + wire_nl001111i_dataout <= wire_nl001iO1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0Ol_dataout; + wire_nl001111l_dataout <= wire_nl001iO0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0OO_dataout; + wire_nl001111O_dataout <= wire_nl001ilOO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oi1i_dataout; + wire_nl00111ii_dataout <= wire_nl001iliO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oi0l_dataout; + wire_nl00111il_dataout <= wire_nl001illi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oi0O_dataout; + wire_nl00111iO_dataout <= wire_nl001il0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oiii_dataout; + wire_nl00111li_dataout <= wire_nl001ilii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oiil_dataout; + wire_nl00111ll_dataout <= wire_nl001il1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OiiO_dataout; + wire_nl00111lO_dataout <= wire_nl001il0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oili_dataout; + wire_nl00111Oi_dataout <= wire_nl001iiOO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001Oill_dataout; + wire_nl00111Ol_dataout <= wire_nl001il1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OilO_dataout; + wire_nl00111OO_dataout <= wire_nl001iilO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OiOi_dataout; + wire_nl0011i_dataout <= nl00llli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0011i0i_dataout <= wire_nl001i01i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OO1l_dataout; + wire_nl0011i0l_dataout <= wire_nl001i1lO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OO1O_dataout; + wire_nl0011i0O_dataout <= wire_nl001i1Oi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OO0i_dataout; + wire_nl0011i1i_dataout <= wire_nl001i01O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OlOl_dataout; + wire_nl0011i1l_dataout <= wire_nl001i00i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OlOO_dataout; + wire_nl0011i1O_dataout <= wire_nl001i1OO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OO1i_dataout; + wire_nl0011iii_dataout <= wire_nl001i1iO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OO0l_dataout; + wire_nl0011iil_dataout <= wire_nl001i1li_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OO0O_dataout; + wire_nl0011iiO_dataout <= wire_nl001i10O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOii_dataout; + wire_nl0011ili_dataout <= wire_nl001i1ii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOil_dataout; + wire_nl0011ill_dataout <= wire_nl001i11O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOiO_dataout; + wire_nl0011ilO_dataout <= wire_nl001i10i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOli_dataout; + wire_nl0011iOi_dataout <= wire_nl0010OOO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOll_dataout; + wire_nl0011iOl_dataout <= wire_nl001i11i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOlO_dataout; + wire_nl0011iOO_dataout <= wire_nl0010OlO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOOi_dataout; + wire_nl0011l_dataout <= nl00llll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0011l0i_dataout <= wire_nl0010O0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl000111l_dataout; + wire_nl0011l0l_dataout <= wire_nl0010Oii_dataout WHEN niOi0iOil = '1' ELSE wire_nl000111O_dataout; + wire_nl0011l0O_dataout <= wire_nl0010O1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl000110i_dataout; + wire_nl0011l1i_dataout <= wire_nl0010OOi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOOl_dataout; + wire_nl0011l1l_dataout <= wire_nl0010OiO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001OOOO_dataout; + wire_nl0011l1O_dataout <= wire_nl0010Oli_dataout WHEN niOi0iOil = '1' ELSE wire_nl000111i_dataout; + wire_nl0011lii_dataout <= wire_nl0010O0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl000110l_dataout; + wire_nl0011lil_dataout <= wire_nl0010lOO_dataout WHEN niOi0iOil = '1' ELSE wire_nl000110O_dataout; + wire_nl0011liO_dataout <= wire_nl0010O1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011ii_dataout; + wire_nl0011lli_dataout <= wire_nl0010llO_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011il_dataout; + wire_nl0011lll_dataout <= wire_nl0010lOi_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011iO_dataout; + wire_nl0011llO_dataout <= wire_nl0010liO_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011li_dataout; + wire_nl0011lOi_dataout <= wire_nl0010lli_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011ll_dataout; + wire_nl0011lOl_dataout <= wire_nl0010l0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011lO_dataout; + wire_nl0011lOO_dataout <= wire_nl0010lii_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011Oi_dataout; + wire_nl0011O_dataout <= nl00lllO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0011O0i_dataout <= wire_nl0010l1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl000101l_dataout; + wire_nl0011O0l_dataout <= wire_nl0010ilO_dataout WHEN niOi0iOil = '1' ELSE wire_nl000101O_dataout; + wire_nl0011O0O_dataout <= wire_nl0010iOi_dataout WHEN niOi0iOil = '1' ELSE wire_nl000100i_dataout; + wire_nl0011O1i_dataout <= wire_nl0010l1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011Ol_dataout; + wire_nl0011O1l_dataout <= wire_nl0010l0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl00011OO_dataout; + wire_nl0011O1O_dataout <= wire_nl0010iOO_dataout WHEN niOi0iOil = '1' ELSE wire_nl000101i_dataout; + wire_nl0011Oii_dataout <= wire_nl0010iiO_dataout WHEN niOi0iOil = '1' ELSE wire_nl000100l_dataout; + wire_nl0011Oil_dataout <= wire_nl0010ili_dataout WHEN niOi0iOil = '1' ELSE wire_nl000100O_dataout; + wire_nl0011OiO_dataout <= wire_nl0010i0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010ii_dataout; + wire_nl0011Oli_dataout <= wire_nl0010iii_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010il_dataout; + wire_nl0011Oll_dataout <= wire_nl0010i1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010iO_dataout; + wire_nl0011OlO_dataout <= wire_nl0010i0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010li_dataout; + wire_nl0011OOi_dataout <= wire_nl00100OO_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010ll_dataout; + wire_nl0011OOl_dataout <= wire_nl0010i1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010lO_dataout; + wire_nl0011OOO_dataout <= wire_nl00100lO_dataout WHEN niOi0iOil = '1' ELSE wire_nl00010Oi_dataout; + wire_nl001i00i_dataout <= wire_nl001OlOO_dataout AND NOT(niOi0ii1i); + wire_nl001i00O_dataout <= wire_nl001OllO_dataout AND NOT(niOi0ii1l); + wire_nl001i01i_dataout <= wire_nl001OO1l_dataout AND NOT(niOi0i0OO); + wire_nl001i01O_dataout <= wire_nl001OlOl_dataout AND NOT(niOi0ii1i); + wire_nl001i0i_dataout <= wire_nl001OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001i0ii_dataout <= wire_nl001OlOi_dataout AND NOT(niOi0ii1l); + wire_nl001i0iO_dataout <= wire_nl001Olli_dataout AND NOT(niOi0ii1O); + wire_nl001i0l_dataout <= wire_nl001OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001i0li_dataout <= wire_nl001Olll_dataout AND NOT(niOi0ii1O); + wire_nl001i0lO_dataout <= wire_nl001Olil_dataout AND NOT(niOi0ii0i); + wire_nl001i0O_dataout <= wire_nl001OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001i0Oi_dataout <= wire_nl001OliO_dataout AND NOT(niOi0ii0i); + wire_nl001i0OO_dataout <= wire_nl001Ol0O_dataout AND NOT(niOi0ii0l); + wire_nl001i10i_dataout <= wire_nl001OOli_dataout AND NOT(niOi0i0ll); + wire_nl001i10O_dataout <= wire_nl001OOii_dataout AND NOT(niOi0i0lO); + wire_nl001i11i_dataout <= wire_nl001OOlO_dataout AND NOT(niOi0i0li); + wire_nl001i11O_dataout <= wire_nl001OOiO_dataout AND NOT(niOi0i0ll); + wire_nl001i1i_dataout <= wire_nl001Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001i1ii_dataout <= wire_nl001OOil_dataout AND NOT(niOi0i0lO); + wire_nl001i1iO_dataout <= wire_nl001OO0l_dataout AND NOT(niOi0i0Oi); + wire_nl001i1l_dataout <= wire_nl001Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001i1li_dataout <= wire_nl001OO0O_dataout AND NOT(niOi0i0Oi); + wire_nl001i1lO_dataout <= wire_nl001OO1O_dataout AND NOT(niOi0i0Ol); + wire_nl001i1O_dataout <= wire_nl001OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001i1Oi_dataout <= wire_nl001OO0i_dataout AND NOT(niOi0i0Ol); + wire_nl001i1OO_dataout <= wire_nl001OO1i_dataout AND NOT(niOi0i0OO); + wire_nl001ii_dataout <= nl01Ol1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0OOO0i; + wire_nl001ii0i_dataout <= wire_nl001Ol0l_dataout AND NOT(niOi0ii0O); + wire_nl001ii0O_dataout <= wire_nl001Ol1l_dataout AND NOT(niOi0iiii); + wire_nl001ii1i_dataout <= wire_nl001Olii_dataout AND NOT(niOi0ii0l); + wire_nl001ii1O_dataout <= wire_nl001Ol0i_dataout AND NOT(niOi0ii0O); + wire_nl001iii_dataout <= wire_nl00011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001iiii_dataout <= wire_nl001Ol1O_dataout AND NOT(niOi0iiii); + wire_nl001iiiO_dataout <= wire_nl001OiOO_dataout AND NOT(niOi0iiil); + wire_nl001iil_dataout <= wire_nl00011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001iili_dataout <= wire_nl001Ol1i_dataout AND NOT(niOi0iiil); + wire_nl001iilO_dataout <= wire_nl001OiOi_dataout AND NOT(niOi0iiiO); + wire_nl001iiO_dataout <= wire_nl00011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001iiOi_dataout <= wire_nl001OiOl_dataout AND NOT(niOi0iiiO); + wire_nl001iiOO_dataout <= wire_nl001Oill_dataout AND NOT(niOi0iili); + wire_nl001il_dataout <= nl01li1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0OOl1O; + wire_nl001il0i_dataout <= wire_nl001Oili_dataout AND NOT(niOi0iill); + wire_nl001il0O_dataout <= wire_nl001Oiii_dataout AND NOT(niOi0iilO); + wire_nl001il1i_dataout <= wire_nl001OilO_dataout AND NOT(niOi0iili); + wire_nl001il1O_dataout <= wire_nl001OiiO_dataout AND NOT(niOi0iill); + wire_nl001ili_dataout <= wire_nl00010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001ilii_dataout <= wire_nl001Oiil_dataout AND NOT(niOi0iilO); + wire_nl001iliO_dataout <= wire_nl001Oi0l_dataout AND NOT(niOi0iiOi); + wire_nl001ill_dataout <= wire_nl00010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001illi_dataout <= wire_nl001Oi0O_dataout AND NOT(niOi0iiOi); + wire_nl001illO_dataout <= wire_nl001Oi1O_dataout AND NOT(niOi0iiOl); + wire_nl001ilO_dataout <= wire_nl00010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001ilOi_dataout <= wire_nl001Oi0i_dataout AND NOT(niOi0iiOl); + wire_nl001ilOO_dataout <= wire_nl001Oi1i_dataout AND NOT(niOi0iiOO); + wire_nl001iO_dataout <= nl01li1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0OOl0i; + wire_nl001iO0i_dataout <= wire_nl001O0OO_dataout AND NOT(niOi0il1i); + wire_nl001iO0O_dataout <= wire_nl001O0lO_dataout AND NOT(niOi0il1l); + wire_nl001iO1i_dataout <= wire_nl001Oi1l_dataout AND NOT(niOi0iiOO); + wire_nl001iO1O_dataout <= wire_nl001O0Ol_dataout AND NOT(niOi0il1i); + wire_nl001iOi_dataout <= wire_nl0001ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001iOii_dataout <= wire_nl001O0Oi_dataout AND NOT(niOi0il1l); + wire_nl001iOiO_dataout <= wire_nl001O0li_dataout AND NOT(niOi0il1O); + wire_nl001iOl_dataout <= wire_nl0001il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001iOli_dataout <= wire_nl001O0ll_dataout AND NOT(niOi0il1O); + wire_nl001iOlO_dataout <= wire_nl001O0il_dataout AND NOT(niOi0il0i); + wire_nl001iOO_dataout <= wire_nl0001iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001iOOi_dataout <= wire_nl001O0iO_dataout AND NOT(niOi0il0i); + wire_nl001iOOO_dataout <= wire_nl001O00O_dataout AND NOT(niOi0il0l); + wire_nl001l00i_dataout <= wire_nl001O1li_dataout AND NOT(niOi0illl); + wire_nl001l00O_dataout <= wire_nl001O1ii_dataout AND NOT(niOi0illO); + wire_nl001l01i_dataout <= wire_nl001O1lO_dataout AND NOT(niOi0illi); + wire_nl001l01O_dataout <= wire_nl001O1iO_dataout AND NOT(niOi0illl); + wire_nl001l0i_dataout <= wire_nl0001Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001l0ii_dataout <= wire_nl001O1il_dataout AND NOT(niOi0illO); + wire_nl001l0iO_dataout <= wire_nl001O10l_dataout AND NOT(niOi0ilOi); + wire_nl001l0l_dataout <= wire_nl0001Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001l0li_dataout <= wire_nl001O10O_dataout AND NOT(niOi0ilOi); + wire_nl001l0lO_dataout <= wire_nl001O11O_dataout AND NOT(niOi0ilOl); + wire_nl001l0O_dataout <= wire_nl0001OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001l0Oi_dataout <= wire_nl001O10i_dataout AND NOT(niOi0ilOl); + wire_nl001l0OO_dataout <= wire_nl001O11i_dataout AND NOT(niOi0ilOO); + wire_nl001l10i_dataout <= wire_nl001O00l_dataout AND NOT(niOi0il0O); + wire_nl001l10O_dataout <= wire_nl001O01l_dataout AND NOT(niOi0ilii); + wire_nl001l11i_dataout <= wire_nl001O0ii_dataout AND NOT(niOi0il0l); + wire_nl001l11O_dataout <= wire_nl001O00i_dataout AND NOT(niOi0il0O); + wire_nl001l1i_dataout <= wire_nl0001li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001l1ii_dataout <= wire_nl001O01O_dataout AND NOT(niOi0ilii); + wire_nl001l1iO_dataout <= wire_nl001O1OO_dataout AND NOT(niOi0ilil); + wire_nl001l1l_dataout <= wire_nl0001ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001l1li_dataout <= wire_nl001O01i_dataout AND NOT(niOi0ilil); + wire_nl001l1lO_dataout <= wire_nl001O1Oi_dataout AND NOT(niOi0iliO); + wire_nl001l1O_dataout <= wire_nl0001lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001l1Oi_dataout <= wire_nl001O1Ol_dataout AND NOT(niOi0iliO); + wire_nl001l1OO_dataout <= wire_nl001O1ll_dataout AND NOT(niOi0illi); + wire_nl001li_dataout <= nl01li1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0OOl0l; + wire_nl001li0i_dataout <= wire_nl001lOOO_dataout AND NOT(niOi0iO1i); + wire_nl001li0O_dataout <= wire_nl001lOlO_dataout AND NOT(niOi0iO1l); + wire_nl001li1i_dataout <= wire_nl001O11l_dataout AND NOT(niOi0ilOO); + wire_nl001li1O_dataout <= wire_nl001lOOl_dataout AND NOT(niOi0iO1i); + wire_nl001lii_dataout <= wire_nl00001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001liii_dataout <= wire_nl001lOOi_dataout AND NOT(niOi0iO1l); + wire_nl001liiO_dataout <= wire_nl001lOli_dataout AND NOT(niOi0iO1O); + wire_nl001lil_dataout <= wire_nl00001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001lili_dataout <= wire_nl001lOll_dataout AND NOT(niOi0iO1O); + wire_nl001lilO_dataout <= wire_nl001lOil_dataout AND NOT(niOi0iO0i); + wire_nl001liO_dataout <= wire_nl00001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001liOi_dataout <= wire_nl001lOiO_dataout AND NOT(niOi0iO0i); + wire_nl001liOO_dataout <= wire_nl001lO0O_dataout AND NOT(niOi0iO0l); + wire_nl001ll_dataout <= nl01li0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0OOl0O; + wire_nl001ll0i_dataout <= wire_nl001lO0l_dataout AND NOT(niOi0iO0O); + wire_nl001ll0O_dataout <= wire_nl001lO1l_dataout AND NOT(niOi0iOii); + wire_nl001ll1i_dataout <= wire_nl001lOii_dataout AND NOT(niOi0iO0l); + wire_nl001ll1O_dataout <= wire_nl001lO0i_dataout AND NOT(niOi0iO0O); + wire_nl001lli_dataout <= wire_nl00000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001llii_dataout <= wire_nl001lO1O_dataout AND NOT(niOi0iOii); + wire_nl001lll_dataout <= wire_nl00000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001llO_dataout <= wire_nl00000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl001lO_dataout <= nl01li0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0OlO0O; + wire_nl001lO0i_dataout <= wire_nl0001ilO_dataout WHEN niOi0lO0i = '1' ELSE nl01lO0ll; + wire_nl001lO0l_dataout <= wire_nl0001iOi_dataout WHEN niOi0lO0i = '1' ELSE nl01lO0lO; + wire_nl001lO0O_dataout <= wire_nl0001iOl_dataout WHEN niOi0lO0i = '1' ELSE nl01lO0Oi; + wire_nl001lO1l_dataout <= wire_nl0001ili_dataout WHEN niOi0lO0i = '1' ELSE nl01lO0iO; + wire_nl001lO1O_dataout <= wire_nl0001ill_dataout WHEN niOi0lO0i = '1' ELSE nl01lO0li; + wire_nl001lOi_dataout <= wire_nl1000i_w_lg_nl01Olli7360w(0) WHEN (wire_w_lg_niOO1lOii7359w(0) AND wire_w_lg_niOO1lO0O7361w(0)) = '1' ELSE nl01Olli; + wire_nl001lOii_dataout <= wire_nl0001iOO_dataout WHEN niOi0lO0i = '1' ELSE nl01lO0Ol; + wire_nl001lOil_dataout <= wire_nl0001l1i_dataout WHEN niOi0lO0i = '1' ELSE nl01lO0OO; + wire_nl001lOiO_dataout <= wire_nl0001l1l_dataout WHEN niOi0lO0i = '1' ELSE nl01lOi1i; + wire_nl001lOli_dataout <= wire_nl0001l1O_dataout WHEN niOi0lO0i = '1' ELSE nl01lOi1l; + wire_nl001lOll_dataout <= wire_nl0001l0i_dataout WHEN niOi0lO0i = '1' ELSE nl01lOi1O; + wire_nl001lOlO_dataout <= wire_nl0001l0l_dataout WHEN niOi0lO0i = '1' ELSE nl01lOi0i; + wire_nl001lOO_dataout <= nl0000iO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OlOi; + wire_nl001lOOi_dataout <= wire_nl0001l0O_dataout WHEN niOi0lO0i = '1' ELSE nl01lOi0l; + wire_nl001lOOl_dataout <= wire_nl0001lii_dataout WHEN niOi0lO0i = '1' ELSE nl01lOi0O; + wire_nl001lOOO_dataout <= wire_nl0001lil_dataout WHEN niOi0lO0i = '1' ELSE nl01lOiii; + wire_nl001O00i_dataout <= wire_nl0001OlO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOlll; + wire_nl001O00l_dataout <= wire_nl0001OOi_dataout WHEN niOi0lO0i = '1' ELSE nl01lOllO; + wire_nl001O00O_dataout <= wire_nl0001OOl_dataout WHEN niOi0lO0i = '1' ELSE nl01lOlOi; + wire_nl001O01i_dataout <= wire_nl0001OiO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOlil; + wire_nl001O01l_dataout <= wire_nl0001Oli_dataout WHEN niOi0lO0i = '1' ELSE nl01lOliO; + wire_nl001O01O_dataout <= wire_nl0001Oll_dataout WHEN niOi0lO0i = '1' ELSE nl01lOlli; + wire_nl001O0i_dataout <= nl0000Oi WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OO1l; + wire_nl001O0ii_dataout <= wire_nl0001OOO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOlOl; + wire_nl001O0il_dataout <= wire_nl000011i_dataout WHEN niOi0lO0i = '1' ELSE nl01lOlOO; + wire_nl001O0iO_dataout <= wire_nl000011l_dataout WHEN niOi0lO0i = '1' ELSE nl01lOO1i; + wire_nl001O0l_dataout <= nl0000Ol WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OO1O; + wire_nl001O0li_dataout <= wire_nl000011O_dataout WHEN niOi0lO0i = '1' ELSE nl01lOO1l; + wire_nl001O0ll_dataout <= wire_nl000010i_dataout WHEN niOi0lO0i = '1' ELSE nl01lOO1O; + wire_nl001O0lO_dataout <= wire_nl000010l_dataout WHEN niOi0lO0i = '1' ELSE nl01lOO0i; + wire_nl001O0O_dataout <= nl0000OO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OO0i; + wire_nl001O0Oi_dataout <= wire_nl000010O_dataout WHEN niOi0lO0i = '1' ELSE nl01lOO0l; + wire_nl001O0Ol_dataout <= wire_nl00001ii_dataout WHEN niOi0lO0i = '1' ELSE nl01lOO0O; + wire_nl001O0OO_dataout <= wire_nl00001il_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOii; + wire_nl001O10i_dataout <= wire_nl0001llO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOill; + wire_nl001O10l_dataout <= wire_nl0001lOi_dataout WHEN niOi0lO0i = '1' ELSE nl01lOilO; + wire_nl001O10O_dataout <= wire_nl0001lOl_dataout WHEN niOi0lO0i = '1' ELSE nl01lOiOi; + wire_nl001O11i_dataout <= wire_nl0001liO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOiil; + wire_nl001O11l_dataout <= wire_nl0001lli_dataout WHEN niOi0lO0i = '1' ELSE nl01lOiiO; + wire_nl001O11O_dataout <= wire_nl0001lll_dataout WHEN niOi0lO0i = '1' ELSE nl01lOili; + wire_nl001O1i_dataout <= nl0000li WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OlOl; + wire_nl001O1ii_dataout <= wire_nl0001lOO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOiOl; + wire_nl001O1il_dataout <= wire_nl0001O1i_dataout WHEN niOi0lO0i = '1' ELSE nl01lOiOO; + wire_nl001O1iO_dataout <= wire_nl0001O1l_dataout WHEN niOi0lO0i = '1' ELSE nl01lOl1i; + wire_nl001O1l_dataout <= nl0000ll WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OlOO; + wire_nl001O1li_dataout <= wire_nl0001O1O_dataout WHEN niOi0lO0i = '1' ELSE nl01lOl1l; + wire_nl001O1ll_dataout <= wire_nl0001O0i_dataout WHEN niOi0lO0i = '1' ELSE nl01lOl1O; + wire_nl001O1lO_dataout <= wire_nl0001O0l_dataout WHEN niOi0lO0i = '1' ELSE nl01lOl0i; + wire_nl001O1O_dataout <= nl0000lO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OO1i; + wire_nl001O1Oi_dataout <= wire_nl0001O0O_dataout WHEN niOi0lO0i = '1' ELSE nl01lOl0l; + wire_nl001O1Ol_dataout <= wire_nl0001Oii_dataout WHEN niOi0lO0i = '1' ELSE nl01lOl0O; + wire_nl001O1OO_dataout <= wire_nl0001Oil_dataout WHEN niOi0lO0i = '1' ELSE nl01lOlii; + wire_nl001Oi_dataout <= nl01li0O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Ol0Ol; + wire_nl001Oi0i_dataout <= wire_nl00001lO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOll; + wire_nl001Oi0l_dataout <= wire_nl00001Oi_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOlO; + wire_nl001Oi0O_dataout <= wire_nl00001Ol_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOOi; + wire_nl001Oi1i_dataout <= wire_nl00001iO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOil; + wire_nl001Oi1l_dataout <= wire_nl00001li_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOiO; + wire_nl001Oi1O_dataout <= wire_nl00001ll_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOli; + wire_nl001Oii_dataout <= nl000i1i WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OO0l; + wire_nl001Oiii_dataout <= wire_nl00001OO_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOOl; + wire_nl001Oiil_dataout <= wire_nl000001i_dataout WHEN niOi0lO0i = '1' ELSE nl01lOOOO; + wire_nl001OiiO_dataout <= wire_nl000001l_dataout WHEN niOi0lO0i = '1' ELSE nl01O111i; + wire_nl001Oil_dataout <= nl000i1l WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OO0O; + wire_nl001Oili_dataout <= wire_nl000001O_dataout WHEN niOi0lO0i = '1' ELSE nl01O111l; + wire_nl001Oill_dataout <= wire_nl000000i_dataout WHEN niOi0lO0i = '1' ELSE nl01O111O; + wire_nl001OilO_dataout <= wire_nl000000l_dataout WHEN niOi0lO0i = '1' ELSE nl01O110i; + wire_nl001OiO_dataout <= nl000i1O WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOii; + wire_nl001OiOi_dataout <= wire_nl000000O_dataout WHEN niOi0lO0i = '1' ELSE nl01O110l; + wire_nl001OiOl_dataout <= wire_nl00000ii_dataout WHEN niOi0lO0i = '1' ELSE nl01O110O; + wire_nl001OiOO_dataout <= wire_nl00000il_dataout WHEN niOi0lO0i = '1' ELSE nl01O11ii; + wire_nl001Ol_dataout <= nl01liii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Ol0OO; + wire_nl001Ol0i_dataout <= wire_nl00000lO_dataout WHEN niOi0lO0i = '1' ELSE nl01O11ll; + wire_nl001Ol0l_dataout <= wire_nl00000Oi_dataout WHEN niOi0lO0i = '1' ELSE nl01O11lO; + wire_nl001Ol0O_dataout <= wire_nl00000Ol_dataout WHEN niOi0lO0i = '1' ELSE nl01O11Oi; + wire_nl001Ol1i_dataout <= wire_nl00000iO_dataout WHEN niOi0lO0i = '1' ELSE nl01O11il; + wire_nl001Ol1l_dataout <= wire_nl00000li_dataout WHEN niOi0lO0i = '1' ELSE nl01O11iO; + wire_nl001Ol1O_dataout <= wire_nl00000ll_dataout WHEN niOi0lO0i = '1' ELSE nl01O11li; + wire_nl001Oli_dataout <= nl000i0i WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOil; + wire_nl001Olii_dataout <= wire_nl00000OO_dataout WHEN niOi0lO0i = '1' ELSE nl01O11Ol; + wire_nl001Olil_dataout <= wire_nl0000i1i_dataout WHEN niOi0lO0i = '1' ELSE nl01O11OO; + wire_nl001OliO_dataout <= wire_nl0000i1l_dataout WHEN niOi0lO0i = '1' ELSE nl01O101i; + wire_nl001Oll_dataout <= nl000i0l WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOiO; + wire_nl001Olli_dataout <= wire_nl0000i1O_dataout WHEN niOi0lO0i = '1' ELSE nl01O101l; + wire_nl001Olll_dataout <= wire_nl0000i0i_dataout WHEN niOi0lO0i = '1' ELSE nl01O101O; + wire_nl001OllO_dataout <= wire_nl0000i0l_dataout WHEN niOi0lO0i = '1' ELSE nl01O100i; + wire_nl001OlO_dataout <= nl000i0O WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOli; + wire_nl001OlOi_dataout <= wire_nl0000i0O_dataout WHEN niOi0lO0i = '1' ELSE nl01O100l; + wire_nl001OlOl_dataout <= wire_nl0000iii_dataout WHEN niOi0lO0i = '1' ELSE nl01O100O; + wire_nl001OlOO_dataout <= wire_nl0000iil_dataout WHEN niOi0lO0i = '1' ELSE nl01O10ii; + wire_nl001OO_dataout <= nl01liil WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0Oli1i; + wire_nl001OO0i_dataout <= wire_nl0000ilO_dataout WHEN niOi0lO0i = '1' ELSE nl01O10ll; + wire_nl001OO0l_dataout <= wire_nl0000iOi_dataout WHEN niOi0lO0i = '1' ELSE nl01O10lO; + wire_nl001OO0O_dataout <= wire_nl0000iOl_dataout WHEN niOi0lO0i = '1' ELSE nl01O10Oi; + wire_nl001OO1i_dataout <= wire_nl0000iiO_dataout WHEN niOi0lO0i = '1' ELSE nl01O10il; + wire_nl001OO1l_dataout <= wire_nl0000ili_dataout WHEN niOi0lO0i = '1' ELSE nl01O10iO; + wire_nl001OO1O_dataout <= wire_nl0000ill_dataout WHEN niOi0lO0i = '1' ELSE nl01O10li; + wire_nl001OOi_dataout <= nl000iii WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOll; + wire_nl001OOii_dataout <= wire_nl0000iOO_dataout WHEN niOi0lO0i = '1' ELSE nl01O10Ol; + wire_nl001OOil_dataout <= wire_nl0000l1i_dataout WHEN niOi0lO0i = '1' ELSE nl01O10OO; + wire_nl001OOiO_dataout <= wire_nl0000l1l_dataout WHEN niOi0lO0i = '1' ELSE nl01O1i1i; + wire_nl001OOl_dataout <= nl000iil WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOlO; + wire_nl001OOli_dataout <= wire_nl0000l1O_dataout WHEN niOi0lO0i = '1' ELSE nl01O1i1l; + wire_nl001OOll_dataout <= wire_nl0000l0i_dataout WHEN niOi0lO0i = '1' ELSE nl01O1i1O; + wire_nl001OOlO_dataout <= wire_nl0000l0l_dataout WHEN niOi0lO0i = '1' ELSE nl01O1i0i; + wire_nl001OOO_dataout <= nl000iiO WHEN wire_w_lg_niOO1lOii7359w(0) = '1' ELSE nl01OOOi; + wire_nl001OOOi_dataout <= wire_nl0000l0O_dataout WHEN niOi0lO0i = '1' ELSE nl01O1i0l; + wire_nl001OOOl_dataout <= wire_nl0000lii_dataout WHEN niOi0lO0i = '1' ELSE nl01O1i0O; + wire_nl001OOOO_dataout <= wire_nl0000lil_dataout WHEN niOi0lO0i = '1' ELSE nl01O1iii; + wire_nl00i000i_dataout <= nl01O1iOO OR niOi0l1lO; + wire_nl00i000l_dataout <= nl01O1l1i AND NOT(niOi0l1lO); + wire_nl00i001i_dataout <= nl01O1l1l OR niOi0l1ll; + wire_nl00i001l_dataout <= nl01O1l1O AND NOT(niOi0l1ll); + wire_nl00i00i_dataout <= wire_nl00illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i00ii_dataout <= nl01O1iOi OR niOi0l1Oi; + wire_nl00i00il_dataout <= nl01O1iOl AND NOT(niOi0l1Oi); + wire_nl00i00l_dataout <= wire_nl00illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i00li_dataout <= nl01O1ill OR niOi0l1Ol; + wire_nl00i00ll_dataout <= nl01O1ilO AND NOT(niOi0l1Ol); + wire_nl00i00O_dataout <= wire_nl00ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i00Oi_dataout <= nl01O1iiO OR niOi0l1OO; + wire_nl00i00Ol_dataout <= nl01O1ili AND NOT(niOi0l1OO); + wire_nl00i010i_dataout <= nl01O1lli OR niOi0l1ii; + wire_nl00i010l_dataout <= nl01O1lll AND NOT(niOi0l1ii); + wire_nl00i011i_dataout <= nl01O1llO OR niOi0l10O; + wire_nl00i011l_dataout <= nl01O1lOi AND NOT(niOi0l10O); + wire_nl00i01i_dataout <= wire_nl00ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i01ii_dataout <= nl01O1lil OR niOi0l1il; + wire_nl00i01il_dataout <= nl01O1liO AND NOT(niOi0l1il); + wire_nl00i01l_dataout <= wire_nl00iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i01li_dataout <= nl01O1l0O OR niOi0l1iO; + wire_nl00i01ll_dataout <= nl01O1lii AND NOT(niOi0l1iO); + wire_nl00i01O_dataout <= wire_nl00illi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i01Oi_dataout <= nl01O1l0i OR niOi0l1li; + wire_nl00i01Ol_dataout <= nl01O1l0l AND NOT(niOi0l1li); + wire_nl00i0i_dataout <= nl01ll0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00i0i0i_dataout <= nl01O1i0l OR niOi0l01l; + wire_nl00i0i0l_dataout <= nl01O1i0O AND NOT(niOi0l01l); + wire_nl00i0i1i_dataout <= nl01O1iii OR niOi0l01i; + wire_nl00i0i1l_dataout <= nl01O1iil AND NOT(niOi0l01i); + wire_nl00i0ii_dataout <= wire_nl00ilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i0iii_dataout <= nl01O1i1O OR niOi0l01O; + wire_nl00i0iil_dataout <= nl01O1i0i AND NOT(niOi0l01O); + wire_nl00i0il_dataout <= wire_nl1000i_w_lg_nl00ilOO7356w(0) WHEN nl00iO1l = '1' ELSE nl00ilOO; + wire_nl00i0ili_dataout <= nl01O1i1i OR niOi0l00i; + wire_nl00i0ill_dataout <= nl01O1i1l AND NOT(niOi0l00i); + wire_nl00i0iO_dataout <= nl111liOl WHEN nl00iO1l = '1' ELSE nl0000iO; + wire_nl00i0iOi_dataout <= nl01O10Ol OR niOi0l00l; + wire_nl00i0iOl_dataout <= nl01O10OO AND NOT(niOi0l00l); + wire_nl00i0l_dataout <= nl01llii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00i0l0i_dataout <= nl01O10li OR niOi0l0ii; + wire_nl00i0l0l_dataout <= nl01O10ll AND NOT(niOi0l0ii); + wire_nl00i0l1i_dataout <= nl01O10lO OR niOi0l00O; + wire_nl00i0l1l_dataout <= nl01O10Oi AND NOT(niOi0l00O); + wire_nl00i0li_dataout <= nl111liOO WHEN nl00iO1l = '1' ELSE nl0000li; + wire_nl00i0lii_dataout <= nl01O10il OR niOi0l0il; + wire_nl00i0lil_dataout <= nl01O10iO AND NOT(niOi0l0il); + wire_nl00i0ll_dataout <= nl111ll1i WHEN nl00iO1l = '1' ELSE nl0000ll; + wire_nl00i0lli_dataout <= nl01O100O OR niOi0l0iO; + wire_nl00i0lll_dataout <= nl01O10ii AND NOT(niOi0l0iO); + wire_nl00i0lO_dataout <= nl111li1l WHEN nl00iO1l = '1' ELSE nl0000lO; + wire_nl00i0lOi_dataout <= nl01O100i OR niOi0l0li; + wire_nl00i0lOl_dataout <= nl01O100l AND NOT(niOi0l0li); + wire_nl00i0O_dataout <= nl01llil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00i0O0i_dataout <= nl01O11OO OR niOi0l0lO; + wire_nl00i0O0l_dataout <= nl01O101i AND NOT(niOi0l0lO); + wire_nl00i0O1i_dataout <= nl01O101l OR niOi0l0ll; + wire_nl00i0O1l_dataout <= nl01O101O AND NOT(niOi0l0ll); + wire_nl00i0Oi_dataout <= nl111li1O WHEN nl00iO1l = '1' ELSE nl0000Oi; + wire_nl00i0Oii_dataout <= nl01O11Oi OR niOi0l0Oi; + wire_nl00i0Oil_dataout <= nl01O11Ol AND NOT(niOi0l0Oi); + wire_nl00i0Ol_dataout <= nl111li0i WHEN nl00iO1l = '1' ELSE nl0000Ol; + wire_nl00i0Oli_dataout <= nl01O11ll OR niOi0l0Ol; + wire_nl00i0Oll_dataout <= nl01O11lO AND NOT(niOi0l0Ol); + wire_nl00i0OO_dataout <= nl111li0l WHEN nl00iO1l = '1' ELSE nl0000OO; + wire_nl00i0OOi_dataout <= nl01O11iO OR niOi0l0OO; + wire_nl00i0OOl_dataout <= nl01O11li AND NOT(niOi0l0OO); + wire_nl00i100i_dataout <= wire_nl00i001i_dataout WHEN niOi0iOll = '1' ELSE nl01O1l1l; + wire_nl00i100l_dataout <= wire_nl00i001l_dataout WHEN niOi0iOll = '1' ELSE nl01O1l1O; + wire_nl00i100O_dataout <= wire_nl00i01Oi_dataout WHEN niOi0iOll = '1' ELSE nl01O1l0i; + wire_nl00i101i_dataout <= wire_nl00i00il_dataout WHEN niOi0iOll = '1' ELSE nl01O1iOl; + wire_nl00i101l_dataout <= wire_nl00i000i_dataout WHEN niOi0iOll = '1' ELSE nl01O1iOO; + wire_nl00i101O_dataout <= wire_nl00i000l_dataout WHEN niOi0iOll = '1' ELSE nl01O1l1i; + wire_nl00i10i_dataout <= wire_nl00iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i10ii_dataout <= wire_nl00i01Ol_dataout WHEN niOi0iOll = '1' ELSE nl01O1l0l; + wire_nl00i10il_dataout <= wire_nl00i01li_dataout WHEN niOi0iOll = '1' ELSE nl01O1l0O; + wire_nl00i10iO_dataout <= wire_nl00i01ll_dataout WHEN niOi0iOll = '1' ELSE nl01O1lii; + wire_nl00i10l_dataout <= wire_nl00iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i10li_dataout <= wire_nl00i01ii_dataout WHEN niOi0iOll = '1' ELSE nl01O1lil; + wire_nl00i10ll_dataout <= wire_nl00i01il_dataout WHEN niOi0iOll = '1' ELSE nl01O1liO; + wire_nl00i10lO_dataout <= wire_nl00i010i_dataout WHEN niOi0iOll = '1' ELSE nl01O1lli; + wire_nl00i10O_dataout <= wire_nl00iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i10Oi_dataout <= wire_nl00i010l_dataout WHEN niOi0iOll = '1' ELSE nl01O1lll; + wire_nl00i10Ol_dataout <= wire_nl00i011i_dataout WHEN niOi0iOll = '1' ELSE nl01O1llO; + wire_nl00i10OO_dataout <= wire_nl00i011l_dataout WHEN niOi0iOll = '1' ELSE nl01O1lOi; + wire_nl00i110i_dataout <= wire_nl00i0ill_dataout WHEN niOi0iOll = '1' ELSE nl01O1i1l; + wire_nl00i110l_dataout <= wire_nl00i0iii_dataout WHEN niOi0iOll = '1' ELSE nl01O1i1O; + wire_nl00i110O_dataout <= wire_nl00i0iil_dataout WHEN niOi0iOll = '1' ELSE nl01O1i0i; + wire_nl00i111i_dataout <= wire_nl00i0iOi_dataout WHEN niOi0iOll = '1' ELSE nl01O10Ol; + wire_nl00i111l_dataout <= wire_nl00i0iOl_dataout WHEN niOi0iOll = '1' ELSE nl01O10OO; + wire_nl00i111O_dataout <= wire_nl00i0ili_dataout WHEN niOi0iOll = '1' ELSE nl01O1i1i; + wire_nl00i11i_dataout <= wire_nl00iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i11ii_dataout <= wire_nl00i0i0i_dataout WHEN niOi0iOll = '1' ELSE nl01O1i0l; + wire_nl00i11il_dataout <= wire_nl00i0i0l_dataout WHEN niOi0iOll = '1' ELSE nl01O1i0O; + wire_nl00i11iO_dataout <= wire_nl00i0i1i_dataout WHEN niOi0iOll = '1' ELSE nl01O1iii; + wire_nl00i11l_dataout <= wire_nl00iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i11li_dataout <= wire_nl00i0i1l_dataout WHEN niOi0iOll = '1' ELSE nl01O1iil; + wire_nl00i11ll_dataout <= wire_nl00i00Oi_dataout WHEN niOi0iOll = '1' ELSE nl01O1iiO; + wire_nl00i11lO_dataout <= wire_nl00i00Ol_dataout WHEN niOi0iOll = '1' ELSE nl01O1ili; + wire_nl00i11O_dataout <= wire_nl00iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i11Oi_dataout <= wire_nl00i00li_dataout WHEN niOi0iOll = '1' ELSE nl01O1ill; + wire_nl00i11Ol_dataout <= wire_nl00i00ll_dataout WHEN niOi0iOll = '1' ELSE nl01O1ilO; + wire_nl00i11OO_dataout <= wire_nl00i00ii_dataout WHEN niOi0iOll = '1' ELSE nl01O1iOi; + wire_nl00i1i_dataout <= nl01ll1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00i1i0i_dataout <= wire_nl00i1Oll_dataout WHEN niOi0iOll = '1' ELSE nl01O1O1l; + wire_nl00i1i0l_dataout <= wire_nl00i1Oii_dataout WHEN niOi0iOll = '1' ELSE nl01O1O1O; + wire_nl00i1i0O_dataout <= wire_nl00i1Oil_dataout WHEN niOi0iOll = '1' ELSE nl01O1O0i; + wire_nl00i1i1i_dataout <= wire_nl00i1OOi_dataout WHEN niOi0iOll = '1' ELSE nl01O1lOl; + wire_nl00i1i1l_dataout <= wire_nl00i1OOl_dataout WHEN niOi0iOll = '1' ELSE nl01O1lOO; + wire_nl00i1i1O_dataout <= wire_nl00i1Oli_dataout WHEN niOi0iOll = '1' ELSE nl01O1O1i; + wire_nl00i1ii_dataout <= wire_nl00iiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1iii_dataout <= wire_nl00i1O0i_dataout WHEN niOi0iOll = '1' ELSE nl01O1O0l; + wire_nl00i1iil_dataout <= wire_nl00i1O0l_dataout WHEN niOi0iOll = '1' ELSE nl01O1O0O; + wire_nl00i1iiO_dataout <= wire_nl00i1O1i_dataout WHEN niOi0iOll = '1' ELSE nl01O1Oii; + wire_nl00i1il_dataout <= wire_nl00iiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1ili_dataout <= wire_nl00i1O1l_dataout WHEN niOi0iOll = '1' ELSE nl01O1Oil; + wire_nl00i1ill_dataout <= wire_nl00i1lOi_dataout WHEN niOi0iOll = '1' ELSE nl01O1OiO; + wire_nl00i1ilO_dataout <= wire_nl00i1lOl_dataout WHEN niOi0iOll = '1' ELSE nl01O1Oli; + wire_nl00i1iO_dataout <= wire_nl00il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1iOi_dataout <= wire_nl00i1lli_dataout WHEN niOi0iOll = '1' ELSE nl01O1Oll; + wire_nl00i1iOl_dataout <= wire_nl00i1lll_dataout WHEN niOi0iOll = '1' ELSE nl01O1OlO; + wire_nl00i1iOO_dataout <= wire_nl00i1lii_dataout WHEN niOi0iOll = '1' ELSE nl01O1OOi; + wire_nl00i1l_dataout <= nl01ll0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00i1l0i_dataout <= nl01O1OOO OR niOi0iOlO; + wire_nl00i1l0l_dataout <= nl01O011i AND NOT(niOi0iOlO); + wire_nl00i1l1i_dataout <= wire_nl00i1lil_dataout WHEN niOi0iOll = '1' ELSE nl01O1OOl; + wire_nl00i1l1l_dataout <= wire_nl00i1l0i_dataout WHEN niOi0iOll = '1' ELSE nl01O1OOO; + wire_nl00i1l1O_dataout <= wire_nl00i1l0l_dataout WHEN niOi0iOll = '1' ELSE nl01O011i; + wire_nl00i1li_dataout <= wire_nl00il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1lii_dataout <= nl01O1OOi OR niOi0iOOi; + wire_nl00i1lil_dataout <= nl01O1OOl AND NOT(niOi0iOOi); + wire_nl00i1ll_dataout <= wire_nl00il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1lli_dataout <= nl01O1Oll OR niOi0iOOl; + wire_nl00i1lll_dataout <= nl01O1OlO AND NOT(niOi0iOOl); + wire_nl00i1lO_dataout <= wire_nl00il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1lOi_dataout <= nl01O1OiO OR niOi0iOOO; + wire_nl00i1lOl_dataout <= nl01O1Oli AND NOT(niOi0iOOO); + wire_nl00i1O_dataout <= nl01ll0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00i1O0i_dataout <= nl01O1O0l OR niOi0l11l; + wire_nl00i1O0l_dataout <= nl01O1O0O AND NOT(niOi0l11l); + wire_nl00i1O1i_dataout <= nl01O1Oii OR niOi0l11i; + wire_nl00i1O1l_dataout <= nl01O1Oil AND NOT(niOi0l11i); + wire_nl00i1Oi_dataout <= wire_nl00il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1Oii_dataout <= nl01O1O1O OR niOi0l11O; + wire_nl00i1Oil_dataout <= nl01O1O0i AND NOT(niOi0l11O); + wire_nl00i1Ol_dataout <= wire_nl00il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1Oli_dataout <= nl01O1O1i OR niOi0l10i; + wire_nl00i1Oll_dataout <= nl01O1O1l AND NOT(niOi0l10i); + wire_nl00i1OO_dataout <= wire_nl00ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00i1OOi_dataout <= nl01O1lOl OR niOi0l10l; + wire_nl00i1OOl_dataout <= nl01O1lOO AND NOT(niOi0l10l); + wire_nl00ii00i_dataout <= nl01lOOli OR niOi0liii; + wire_nl00ii00l_dataout <= nl01lOOll AND NOT(niOi0liii); + wire_nl00ii01i_dataout <= nl01lOOlO OR niOi0li0O; + wire_nl00ii01l_dataout <= nl01lOOOi AND NOT(niOi0li0O); + wire_nl00ii0i_dataout <= nl111liiO WHEN nl00iO1l = '1' ELSE nl000i0i; + wire_nl00ii0ii_dataout <= nl01lOOil OR niOi0liil; + wire_nl00ii0il_dataout <= nl01lOOiO AND NOT(niOi0liil); + wire_nl00ii0l_dataout <= nl111lili WHEN nl00iO1l = '1' ELSE nl000i0l; + wire_nl00ii0li_dataout <= nl01lOO0O OR niOi0liiO; + wire_nl00ii0ll_dataout <= nl01lOOii AND NOT(niOi0liiO); + wire_nl00ii0O_dataout <= nl111lill WHEN nl00iO1l = '1' ELSE nl000i0O; + wire_nl00ii0Oi_dataout <= nl01lOO0i OR niOi0lili; + wire_nl00ii0Ol_dataout <= nl01lOO0l AND NOT(niOi0lili); + wire_nl00ii10i_dataout <= nl01O110l OR niOi0li1l; + wire_nl00ii10l_dataout <= nl01O110O AND NOT(niOi0li1l); + wire_nl00ii11i_dataout <= nl01O11ii OR niOi0li1i; + wire_nl00ii11l_dataout <= nl01O11il AND NOT(niOi0li1i); + wire_nl00ii1i_dataout <= nl111li0O WHEN nl00iO1l = '1' ELSE nl000i1i; + wire_nl00ii1ii_dataout <= nl01O111O OR niOi0li1O; + wire_nl00ii1il_dataout <= nl01O110i AND NOT(niOi0li1O); + wire_nl00ii1l_dataout <= nl111liii WHEN nl00iO1l = '1' ELSE nl000i1l; + wire_nl00ii1li_dataout <= nl01O111i OR niOi0li0i; + wire_nl00ii1ll_dataout <= nl01O111l AND NOT(niOi0li0i); + wire_nl00ii1O_dataout <= nl111liil WHEN nl00iO1l = '1' ELSE nl000i1O; + wire_nl00ii1Oi_dataout <= nl01lOOOl OR niOi0li0l; + wire_nl00ii1Ol_dataout <= nl01lOOOO AND NOT(niOi0li0l); + wire_nl00iii_dataout <= nl01lliO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00iii0i_dataout <= nl01lOlOO OR niOi0lilO; + wire_nl00iii0l_dataout <= nl01lOO1i AND NOT(niOi0lilO); + wire_nl00iii1i_dataout <= nl01lOO1l OR niOi0lill; + wire_nl00iii1l_dataout <= nl01lOO1O AND NOT(niOi0lill); + wire_nl00iiii_dataout <= nl111lilO WHEN nl00iO1l = '1' ELSE nl000iii; + wire_nl00iiiii_dataout <= nl01lOlOi OR niOi0liOi; + wire_nl00iiiil_dataout <= nl01lOlOl AND NOT(niOi0liOi); + wire_nl00iiil_dataout <= nl111liOi WHEN nl00iO1l = '1' ELSE nl000iil; + wire_nl00iiili_dataout <= nl01lOlll OR niOi0liOl; + wire_nl00iiill_dataout <= nl01lOllO AND NOT(niOi0liOl); + wire_nl00iiiO_dataout <= nl111l0Ol WHEN nl00iO1l = '1' ELSE nl000iiO; + wire_nl00iiiOi_dataout <= nl01lOliO OR niOi0liOO; + wire_nl00iiiOl_dataout <= nl01lOlli AND NOT(niOi0liOO); + wire_nl00iil_dataout <= nl01llli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00iil0i_dataout <= nl01lOl0l OR niOi0ll1l; + wire_nl00iil0l_dataout <= nl01lOl0O AND NOT(niOi0ll1l); + wire_nl00iil1i_dataout <= nl01lOlii OR niOi0ll1i; + wire_nl00iil1l_dataout <= nl01lOlil AND NOT(niOi0ll1i); + wire_nl00iili_dataout <= nl111l0OO WHEN nl00iO1l = '1' ELSE nl000ili; + wire_nl00iilii_dataout <= nl01lOl1O OR niOi0ll1O; + wire_nl00iilil_dataout <= nl01lOl0i AND NOT(niOi0ll1O); + wire_nl00iill_dataout <= nl111li1i WHEN nl00iO1l = '1' ELSE nl000ill; + wire_nl00iilli_dataout <= nl01lOl1i OR niOi0ll0i; + wire_nl00iilll_dataout <= nl01lOl1l AND NOT(niOi0ll0i); + wire_nl00iilO_dataout <= nl111l0ll WHEN nl00iO1l = '1' ELSE nl000ilO; + wire_nl00iilOi_dataout <= nl01lOiOl OR niOi0ll0l; + wire_nl00iilOl_dataout <= nl01lOiOO AND NOT(niOi0ll0l); + wire_nl00iiO_dataout <= nl01llll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00iiO0i_dataout <= nl01lOili OR niOi0llii; + wire_nl00iiO0l_dataout <= nl01lOill AND NOT(niOi0llii); + wire_nl00iiO1i_dataout <= nl01lOilO OR niOi0ll0O; + wire_nl00iiO1l_dataout <= nl01lOiOi AND NOT(niOi0ll0O); + wire_nl00iiOi_dataout <= nl111l0lO WHEN nl00iO1l = '1' ELSE nl000iOi; + wire_nl00iiOii_dataout <= nl01lOiil OR niOi0llil; + wire_nl00iiOil_dataout <= nl01lOiiO AND NOT(niOi0llil); + wire_nl00iiOl_dataout <= nl111l0Oi WHEN nl00iO1l = '1' ELSE nl000iOl; + wire_nl00iiOli_dataout <= nl01lOi0O OR niOi0lliO; + wire_nl00iiOll_dataout <= nl01lOiii AND NOT(niOi0lliO); + wire_nl00iiOO_dataout <= nl111l0il WHEN nl00iO1l = '1' ELSE nl000iOO; + wire_nl00iiOOi_dataout <= nl01lOi0i OR niOi0llli; + wire_nl00iiOOl_dataout <= nl01lOi0l AND NOT(niOi0llli); + wire_nl00il00i_dataout <= nl01O1OOO AND NOT(niOi0iOlO); + wire_nl00il00l_dataout <= nl01O011i OR niOi0iOlO; + wire_nl00il00O_dataout <= nl01O1OOi AND NOT(niOi0iOOi); + wire_nl00il0i_dataout <= nl111l1lO WHEN nl00iO1l = '1' ELSE nl000l0i; + wire_nl00il0ii_dataout <= nl01O1OOl OR niOi0iOOi; + wire_nl00il0il_dataout <= nl01O1Oll AND NOT(niOi0iOOl); + wire_nl00il0iO_dataout <= nl01O1OlO OR niOi0iOOl; + wire_nl00il0l_dataout <= nl111l1Oi WHEN nl00iO1l = '1' ELSE nl000l0l; + wire_nl00il0li_dataout <= nl01O1OiO AND NOT(niOi0iOOO); + wire_nl00il0ll_dataout <= nl01O1Oli OR niOi0iOOO; + wire_nl00il0lO_dataout <= nl01O1Oii AND NOT(niOi0l11i); + wire_nl00il0O_dataout <= nl111l1Ol WHEN nl00iO1l = '1' ELSE nl000l0O; + wire_nl00il0Oi_dataout <= nl01O1Oil OR niOi0l11i; + wire_nl00il0Ol_dataout <= nl01O1O0l AND NOT(niOi0l11l); + wire_nl00il0OO_dataout <= nl01O1O0O OR niOi0l11l; + wire_nl00il10i_dataout <= nl01lO0OO OR niOi0lllO; + wire_nl00il10l_dataout <= nl01lOi1i AND NOT(niOi0lllO); + wire_nl00il11i_dataout <= nl01lOi1l OR niOi0llll; + wire_nl00il11l_dataout <= nl01lOi1O AND NOT(niOi0llll); + wire_nl00il1i_dataout <= nl111l0iO WHEN nl00iO1l = '1' ELSE nl000l1i; + wire_nl00il1ii_dataout <= nl01lO0Oi OR niOi0llOi; + wire_nl00il1il_dataout <= nl01lO0Ol AND NOT(niOi0llOi); + wire_nl00il1l_dataout <= nl111l0li WHEN nl00iO1l = '1' ELSE nl000l1l; + wire_nl00il1li_dataout <= nl01lO0ll OR niOi0llOl; + wire_nl00il1ll_dataout <= nl01lO0lO AND NOT(niOi0llOl); + wire_nl00il1O_dataout <= nl111iOli WHEN nl00iO1l = '1' ELSE nl000l1O; + wire_nl00il1Oi_dataout <= nl01lO0iO OR niOi0llOO; + wire_nl00il1Ol_dataout <= nl01lO0li AND NOT(niOi0llOO); + wire_nl00ili_dataout <= nl01lllO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00ili0i_dataout <= nl01O1O1l OR niOi0l10i; + wire_nl00ili0l_dataout <= nl01O1lOl AND NOT(niOi0l10l); + wire_nl00ili0O_dataout <= nl01O1lOO OR niOi0l10l; + wire_nl00ili1i_dataout <= nl01O1O1O AND NOT(niOi0l11O); + wire_nl00ili1l_dataout <= nl01O1O0i OR niOi0l11O; + wire_nl00ili1O_dataout <= nl01O1O1i AND NOT(niOi0l10i); + wire_nl00ilii_dataout <= nl111l1OO WHEN nl00iO1l = '1' ELSE nl000lii; + wire_nl00iliii_dataout <= nl01O1llO AND NOT(niOi0l10O); + wire_nl00iliil_dataout <= nl01O1lOi OR niOi0l10O; + wire_nl00iliiO_dataout <= nl01O1lli AND NOT(niOi0l1ii); + wire_nl00ilil_dataout <= nl111l01i WHEN nl00iO1l = '1' ELSE nl000lil; + wire_nl00ilili_dataout <= nl01O1lll OR niOi0l1ii; + wire_nl00ilill_dataout <= nl01O1lil AND NOT(niOi0l1il); + wire_nl00ililO_dataout <= nl01O1liO OR niOi0l1il; + wire_nl00iliO_dataout <= nl111l01l WHEN nl00iO1l = '1' ELSE nl000liO; + wire_nl00iliOi_dataout <= nl01O1l0O AND NOT(niOi0l1iO); + wire_nl00iliOl_dataout <= nl01O1lii OR niOi0l1iO; + wire_nl00iliOO_dataout <= nl01O1l0i AND NOT(niOi0l1li); + wire_nl00ill_dataout <= nl01llOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00ill0i_dataout <= nl01O1iOO AND NOT(niOi0l1lO); + wire_nl00ill0l_dataout <= nl01O1l1i OR niOi0l1lO; + wire_nl00ill0O_dataout <= nl01O1iOi AND NOT(niOi0l1Oi); + wire_nl00ill1i_dataout <= nl01O1l0l OR niOi0l1li; + wire_nl00ill1l_dataout <= nl01O1l1l AND NOT(niOi0l1ll); + wire_nl00ill1O_dataout <= nl01O1l1O OR niOi0l1ll; + wire_nl00illi_dataout <= nl111l01O WHEN nl00iO1l = '1' ELSE nl000lli; + wire_nl00illii_dataout <= nl01O1iOl OR niOi0l1Oi; + wire_nl00illil_dataout <= nl01O1ill AND NOT(niOi0l1Ol); + wire_nl00illiO_dataout <= nl01O1ilO OR niOi0l1Ol; + wire_nl00illl_dataout <= nl111l00i WHEN nl00iO1l = '1' ELSE nl000lll; + wire_nl00illli_dataout <= nl01O1iiO AND NOT(niOi0l1OO); + wire_nl00illll_dataout <= nl01O1ili OR niOi0l1OO; + wire_nl00illlO_dataout <= nl01O1iii AND NOT(niOi0l01i); + wire_nl00illO_dataout <= nl111l00l WHEN nl00iO1l = '1' ELSE nl000llO; + wire_nl00illOi_dataout <= nl01O1iil OR niOi0l01i; + wire_nl00illOl_dataout <= nl01O1i0l AND NOT(niOi0l01l); + wire_nl00illOO_dataout <= nl01O1i0O OR niOi0l01l; + wire_nl00ilO_dataout <= nl01llOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl00ilO0i_dataout <= nl01O1i1l OR niOi0l00i; + wire_nl00ilO0l_dataout <= nl01O10Ol AND NOT(niOi0l00l); + wire_nl00ilO0O_dataout <= nl01O10OO OR niOi0l00l; + wire_nl00ilO1i_dataout <= nl01O1i1O AND NOT(niOi0l01O); + wire_nl00ilO1l_dataout <= nl01O1i0i OR niOi0l01O; + wire_nl00ilO1O_dataout <= nl01O1i1i AND NOT(niOi0l00i); + wire_nl00ilOi_dataout <= nl111l00O WHEN nl00iO1l = '1' ELSE nl000lOi; + wire_nl00ilOii_dataout <= nl01O10lO AND NOT(niOi0l00O); + wire_nl00ilOil_dataout <= nl01O10Oi OR niOi0l00O; + wire_nl00ilOiO_dataout <= nl01O10li AND NOT(niOi0l0ii); + wire_nl00ilOl_dataout <= nl111l0ii WHEN nl00iO1l = '1' ELSE nl000lOl; + wire_nl00ilOli_dataout <= nl01O10ll OR niOi0l0ii; + wire_nl00ilOll_dataout <= nl01O10il AND NOT(niOi0l0il); + wire_nl00ilOlO_dataout <= nl01O10iO OR niOi0l0il; + wire_nl00ilOOi_dataout <= nl01O100O AND NOT(niOi0l0iO); + wire_nl00ilOOl_dataout <= nl01O10ii OR niOi0l0iO; + wire_nl00ilOOO_dataout <= nl01O100i AND NOT(niOi0l0li); + wire_nl00iO00i_dataout <= nl01O111l OR niOi0li0i; + wire_nl00iO00l_dataout <= nl01lOOOl AND NOT(niOi0li0l); + wire_nl00iO00O_dataout <= nl01lOOOO OR niOi0li0l; + wire_nl00iO01i_dataout <= nl01O111O AND NOT(niOi0li1O); + wire_nl00iO01l_dataout <= nl01O110i OR niOi0li1O; + wire_nl00iO01O_dataout <= nl01O111i AND NOT(niOi0li0i); + wire_nl00iO0i_dataout <= wire_nl00iOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00iO0ii_dataout <= nl01lOOlO AND NOT(niOi0li0O); + wire_nl00iO0il_dataout <= nl01lOOOi OR niOi0li0O; + wire_nl00iO0iO_dataout <= nl01lOOli AND NOT(niOi0liii); + wire_nl00iO0l_dataout <= niOO1lOil AND NOT(wire_niO01O0O_dataout); + wire_nl00iO0li_dataout <= nl01lOOll OR niOi0liii; + wire_nl00iO0ll_dataout <= nl01lOOil AND NOT(niOi0liil); + wire_nl00iO0lO_dataout <= nl01lOOiO OR niOi0liil; + wire_nl00iO0O_dataout <= wire_nl00iOil_o(0) AND NOT(niOO1lOil); + wire_nl00iO0Oi_dataout <= nl01lOO0O AND NOT(niOi0liiO); + wire_nl00iO0Ol_dataout <= nl01lOOii OR niOi0liiO; + wire_nl00iO0OO_dataout <= nl01lOO0i AND NOT(niOi0lili); + wire_nl00iO10i_dataout <= nl01O11OO AND NOT(niOi0l0lO); + wire_nl00iO10l_dataout <= nl01O101i OR niOi0l0lO; + wire_nl00iO10O_dataout <= nl01O11Oi AND NOT(niOi0l0Oi); + wire_nl00iO11i_dataout <= nl01O100l OR niOi0l0li; + wire_nl00iO11l_dataout <= nl01O101l AND NOT(niOi0l0ll); + wire_nl00iO11O_dataout <= nl01O101O OR niOi0l0ll; + wire_nl00iO1ii_dataout <= nl01O11Ol OR niOi0l0Oi; + wire_nl00iO1il_dataout <= nl01O11ll AND NOT(niOi0l0Ol); + wire_nl00iO1iO_dataout <= nl01O11lO OR niOi0l0Ol; + wire_nl00iO1li_dataout <= nl01O11iO AND NOT(niOi0l0OO); + wire_nl00iO1ll_dataout <= nl01O11li OR niOi0l0OO; + wire_nl00iO1lO_dataout <= nl01O11ii AND NOT(niOi0li1i); + wire_nl00iO1O_dataout <= wire_nl00iO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00iO1Oi_dataout <= nl01O11il OR niOi0li1i; + wire_nl00iO1Ol_dataout <= nl01O110l AND NOT(niOi0li1l); + wire_nl00iO1OO_dataout <= nl01O110O OR niOi0li1l; + wire_nl00iOi0i_dataout <= nl01lOlOO AND NOT(niOi0lilO); + wire_nl00iOi0l_dataout <= nl01lOO1i OR niOi0lilO; + wire_nl00iOi0O_dataout <= nl01lOlOi AND NOT(niOi0liOi); + wire_nl00iOi1i_dataout <= nl01lOO0l OR niOi0lili; + wire_nl00iOi1l_dataout <= nl01lOO1l AND NOT(niOi0lill); + wire_nl00iOi1O_dataout <= nl01lOO1O OR niOi0lill; + wire_nl00iOii_dataout <= wire_nl00iOil_o(1) AND NOT(niOO1lOil); + wire_nl00iOiii_dataout <= nl01lOlOl OR niOi0liOi; + wire_nl00iOiil_dataout <= nl01lOlll AND NOT(niOi0liOl); + wire_nl00iOiiO_dataout <= nl01lOllO OR niOi0liOl; + wire_nl00iOili_dataout <= nl01lOliO AND NOT(niOi0liOO); + wire_nl00iOill_dataout <= nl01lOlli OR niOi0liOO; + wire_nl00iOilO_dataout <= nl01lOlii AND NOT(niOi0ll1i); + wire_nl00iOiOi_dataout <= nl01lOlil OR niOi0ll1i; + wire_nl00iOiOl_dataout <= nl01lOl0l AND NOT(niOi0ll1l); + wire_nl00iOiOO_dataout <= nl01lOl0O OR niOi0ll1l; + wire_nl00iOl0i_dataout <= nl01lOl1l OR niOi0ll0i; + wire_nl00iOl0l_dataout <= nl01lOiOl AND NOT(niOi0ll0l); + wire_nl00iOl0O_dataout <= nl01lOiOO OR niOi0ll0l; + wire_nl00iOl1i_dataout <= nl01lOl1O AND NOT(niOi0ll1O); + wire_nl00iOl1l_dataout <= nl01lOl0i OR niOi0ll1O; + wire_nl00iOl1O_dataout <= nl01lOl1i AND NOT(niOi0ll0i); + wire_nl00iOlii_dataout <= nl01lOilO AND NOT(niOi0ll0O); + wire_nl00iOlil_dataout <= nl01lOiOi OR niOi0ll0O; + wire_nl00iOliO_dataout <= nl01lOili AND NOT(niOi0llii); + wire_nl00iOlli_dataout <= nl01lOill OR niOi0llii; + wire_nl00iOlll_dataout <= nl01lOiil AND NOT(niOi0llil); + wire_nl00iOllO_dataout <= nl01lOiiO OR niOi0llil; + wire_nl00iOlOi_dataout <= nl01lOi0O AND NOT(niOi0lliO); + wire_nl00iOlOl_dataout <= nl01lOiii OR niOi0lliO; + wire_nl00iOlOO_dataout <= nl01lOi0i AND NOT(niOi0llli); + wire_nl00iOO0i_dataout <= nl01lO0OO AND NOT(niOi0lllO); + wire_nl00iOO0l_dataout <= nl01lOi1i OR niOi0lllO; + wire_nl00iOO0O_dataout <= nl01lO0Oi AND NOT(niOi0llOi); + wire_nl00iOO1i_dataout <= nl01lOi0l OR niOi0llli; + wire_nl00iOO1l_dataout <= nl01lOi1l AND NOT(niOi0llll); + wire_nl00iOO1O_dataout <= nl01lOi1O OR niOi0llll; + wire_nl00iOOii_dataout <= nl01lO0Ol OR niOi0llOi; + wire_nl00iOOil_dataout <= nl01lO0ll AND NOT(niOi0llOl); + wire_nl00iOOiO_dataout <= nl01lO0lO OR niOi0llOl; + wire_nl00iOOli_dataout <= nl01lO0iO AND NOT(niOi0llOO); + wire_nl00iOOll_dataout <= nl01lO0li OR niOi0llOO; + wire_nl00l0O1O_dataout <= nl00li0li WHEN nl00lll0l = '1' ELSE nl00lillO; + wire_nl00l111i_dataout <= wire_nl00l111O_o AND NOT(wire_w_lg_niOi0lO0O52760w(0)); + wire_nl00l111i_w_lg_dataout53192w(0) <= NOT wire_nl00l111i_dataout; + wire_nl00l111l_dataout <= wire_nl00l110i_o AND NOT(wire_w_lg_niOi0lO0O52760w(0)); + wire_nl00l111l_w_lg_w_lg_dataout53191w53193w(0) <= wire_nl00l111l_w_lg_dataout53191w(0) AND wire_nl00l111i_w_lg_dataout53192w(0); + wire_nl00l111l_w_lg_dataout53191w(0) <= NOT wire_nl00l111l_dataout; + wire_nl00l11li_dataout <= wire_nl00l11Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00l11ll_dataout <= wire_nl00l11OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00l11lO_dataout <= wire_nl00l11Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00l11Oi_dataout <= nl00l11iO OR nl00l11il; + wire_nl00l11Ol_dataout <= (wire_nilOl1Ol_w_lg_dataout43262w(0) AND niOi0lOli) WHEN niOi0lOiO = '1' ELSE nl01O011l; + wire_nl00l11OO_dataout <= (wire_nilOl1Ol_dataout AND niOi0lOli) WHEN niOi0lOiO = '1' ELSE nl00l11il; + wire_nl00llliO_dataout <= wire_nl00O1iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lllli_dataout <= wire_nl00O1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lllll_dataout <= wire_nl00O1iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llllO_dataout <= wire_nl00O1l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lllOi_dataout <= wire_nl00O1l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lllOl_dataout <= wire_nl00O1l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lllOO_dataout <= wire_nl00O1l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llO0i_dataout <= wire_nl00O1lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llO0l_dataout <= wire_nl00O1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llO0O_dataout <= wire_nl00O1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llO1i_dataout <= wire_nl00O1l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llO1l_dataout <= wire_nl00O1l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llO1O_dataout <= wire_nl00O1lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOii_dataout <= wire_nl00O1lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOil_dataout <= wire_nl00O1llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOiO_dataout <= wire_nl00O1lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOli_dataout <= wire_nl00O1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOll_dataout <= wire_nl00O1lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOlO_dataout <= wire_nl00O1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOOi_dataout <= wire_nl00O1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOOl_dataout <= wire_nl00O1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00llOOO_dataout <= wire_nl00O1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO00i_dataout <= wire_nl00O0iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO00l_dataout <= wire_nl00O0iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO00O_dataout <= wire_nl00O0ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO01i_dataout <= wire_nl00O0i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO01l_dataout <= wire_nl00O0i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO01O_dataout <= wire_nl00O0iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0i_dataout <= wire_nl00O00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lO0ii_dataout <= wire_nl00O0ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0il_dataout <= wire_nl00O0ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0iO_dataout <= wire_nl00O0iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0l_dataout <= wire_nl00O00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lO0li_dataout <= wire_nl00O0iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0ll_dataout <= wire_nl00O0iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0lO_dataout <= wire_nl00O0l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0O_dataout <= wire_nl00O00O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lO0Oi_dataout <= wire_nl00O0l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0Ol_dataout <= wire_nl00O0l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO0OO_dataout <= wire_nl00O0l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO10i_dataout <= wire_nl00O1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO10l_dataout <= wire_nl00O1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO10O_dataout <= wire_nl00O1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO11i_dataout <= wire_nl00O1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO11l_dataout <= wire_nl00O1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO11O_dataout <= wire_nl00O1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1ii_dataout <= wire_nl00O1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1il_dataout <= wire_nl00O1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1iO_dataout <= wire_nl00O1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1l_dataout <= wire_nl00O01l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lO1li_dataout <= wire_nl00O1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1ll_dataout <= nl00lllil AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1lO_dataout <= nl0i1li1O AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1O_dataout <= wire_nl00O01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lO1Oi_dataout <= wire_nl00O0i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1Ol_dataout <= wire_nl00O0i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lO1OO_dataout <= wire_nl00O0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOi0i_dataout <= wire_nl00O0lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOi0l_dataout <= wire_nl00O0liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOi0O_dataout <= wire_nl00O0lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOi1i_dataout <= wire_nl00O0l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOi1l_dataout <= wire_nl00O0l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOi1O_dataout <= wire_nl00O0lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOii_dataout <= wire_nl00O0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOiii_dataout <= wire_nl00O0lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOiil_dataout <= wire_nl00O0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOiiO_dataout <= wire_nl00O0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOil_dataout <= wire_nl00O0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOili_dataout <= wire_nl00O0lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOill_dataout <= wire_nl00O0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOilO_dataout <= wire_nl00O0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOiO_dataout <= wire_nl00O0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOiOi_dataout <= wire_nl00O0O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOiOl_dataout <= wire_nl00O0O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOiOO_dataout <= wire_nl00O0O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOl0i_dataout <= wire_nl00O0Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOl0l_dataout <= wire_nl00O0OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOl0O_dataout <= wire_nl00O0Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOl1i_dataout <= wire_nl00O0O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOl1l_dataout <= wire_nl00O0O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOl1O_dataout <= wire_nl00O0Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOli_dataout <= wire_nl00O0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOlii_dataout <= wire_nl00O0Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOlil_dataout <= wire_nl00O0OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOliO_dataout <= wire_nl00O0OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOll_dataout <= wire_nl00O0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOlli_dataout <= wire_nl00O0OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOlll_dataout <= wire_nl00O0OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOllO_dataout <= wire_nl00Oi11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOlO_dataout <= wire_nl00O0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOlOi_dataout <= wire_nl00Oi11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOlOl_dataout <= wire_nl00Oi11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOlOO_dataout <= wire_nl00Oi10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOO0i_dataout <= wire_nl00Oi1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOO0l_dataout <= wire_nl00Oi1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOO0O_dataout <= wire_nl00Oi1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOO1i_dataout <= wire_nl00Oi10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOO1l_dataout <= wire_nl00Oi10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOO1O_dataout <= wire_nl00Oi1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOi_dataout <= wire_nl00O0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOOii_dataout <= wire_nl00Oi1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOil_dataout <= wire_nl00Oi1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOiO_dataout <= wire_nl00Oi1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOl_dataout <= wire_nl00O0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOOli_dataout <= wire_nl00Oi1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOll_dataout <= wire_nl00Oi1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOlO_dataout <= wire_nl00Oi01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOO_dataout <= wire_nl00O0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00lOOOi_dataout <= wire_nl00Oi01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOOl_dataout <= wire_nl00Oi01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00lOOOO_dataout <= wire_nl00Oi00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O000i_dataout <= nl00li1ii AND NOT(nl00li00O); + wire_nl00O000l_dataout <= nl00li1il AND NOT(nl00li00O); + wire_nl00O000O_dataout <= nl00li1iO AND NOT(nl00li00O); + wire_nl00O001i_dataout <= nl00li10i AND NOT(nl00li00O); + wire_nl00O001l_dataout <= nl00li10l AND NOT(nl00li00O); + wire_nl00O001O_dataout <= nl00li10O AND NOT(nl00li00O); + wire_nl00O00i_dataout <= nl00OO1i WHEN niOO1lOiO = '1' ELSE nl00li1O; + wire_nl00O00ii_dataout <= nl00li1li AND NOT(nl00li00O); + wire_nl00O00il_dataout <= nl00li1ll AND NOT(nl00li00O); + wire_nl00O00iO_dataout <= nl00li1lO AND NOT(nl00li00O); + wire_nl00O00l_dataout <= nl00OO1l WHEN niOO1lOiO = '1' ELSE nl00li0i; + wire_nl00O00li_dataout <= nl00li1Oi AND NOT(nl00li00O); + wire_nl00O00ll_dataout <= nl00li1Ol AND NOT(nl00li00O); + wire_nl00O00lO_dataout <= nl00li1OO AND NOT(nl00li00O); + wire_nl00O00O_dataout <= nl00OO1O WHEN niOO1lOiO = '1' ELSE nl00li0l; + wire_nl00O00Oi_dataout <= nl00li01i AND NOT(nl00li00O); + wire_nl00O00Ol_dataout <= nl00li01l AND NOT(nl00li00O); + wire_nl00O00OO_dataout <= nl00li01O AND NOT(nl00li00O); + wire_nl00O010i_dataout <= wire_nl0l0liil_dataout WHEN nl00li00O = '1' ELSE nl00l0Oii; + wire_nl00O010l_dataout <= nl0l0liOi WHEN nl00li00O = '1' ELSE nl00l0Oil; + wire_nl00O010O_dataout <= nl0l0liOl WHEN nl00li00O = '1' ELSE nl00l0OiO; + wire_nl00O011i_dataout <= wire_nl0l0li1l_dataout WHEN nl00li00O = '1' ELSE nl00l0O0i; + wire_nl00O011l_dataout <= wire_nl0l0li0i_dataout WHEN nl00li00O = '1' ELSE nl00l0O0l; + wire_nl00O011O_dataout <= wire_nl0l0li0O_dataout WHEN nl00li00O = '1' ELSE nl00l0O0O; + wire_nl00O01i_dataout <= wire_nl00Ol1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O01ii_dataout <= nl0l0liOO WHEN nl00li00O = '1' ELSE nl00l0Oli; + wire_nl00O01il_dataout <= nl0l0ll1i WHEN nl00li00O = '1' ELSE nl00l0Oll; + wire_nl00O01iO_dataout <= nl0l0ll1l WHEN nl00li00O = '1' ELSE nl00l0OlO; + wire_nl00O01l_dataout <= nl00OlOl WHEN niOO1lOiO = '1' ELSE nl00Ol1O; + wire_nl00O01li_dataout <= nl0l0ll1O WHEN nl00li00O = '1' ELSE nl00l0OOi; + wire_nl00O01ll_dataout <= nl0l0ll0i WHEN nl00li00O = '1' ELSE nl00l0OOl; + wire_nl00O01lO_dataout <= nl0l0ll0l WHEN nl00li00O = '1' ELSE nl00l0OOO; + wire_nl00O01O_dataout <= nl00OlOO WHEN niOO1lOiO = '1' ELSE nl00li1l; + wire_nl00O01Oi_dataout <= nl0l0ll0O WHEN nl00li00O = '1' ELSE nl00li11i; + wire_nl00O01Ol_dataout <= nl0l0llii WHEN nl00li00O = '1' ELSE nl00li11l; + wire_nl00O01OO_dataout <= nl0l0llil WHEN nl00li00O = '1' ELSE nl00li11O; + wire_nl00O0i0i_dataout <= wire_nl00OiO0i_dataout AND NOT(nl00lllil); + wire_nl00O0i0l_dataout <= wire_nl00OiO0l_dataout AND NOT(nl00lllil); + wire_nl00O0i0O_dataout <= wire_nl00OiO0O_dataout AND NOT(nl00lllil); + wire_nl00O0i1i_dataout <= nl00li00i AND NOT(nl00li00O); + wire_nl00O0i1l_dataout <= wire_nl00OiO1l_dataout AND NOT(nl00lllil); + wire_nl00O0i1O_dataout <= wire_nl00OiO1O_dataout AND NOT(nl00lllil); + wire_nl00O0ii_dataout <= nl00OO0i WHEN niOO1lOiO = '1' ELSE nl00li0O; + wire_nl00O0iii_dataout <= wire_nl00OiOii_dataout AND NOT(nl00lllil); + wire_nl00O0iil_dataout <= wire_nl00OiOil_dataout AND NOT(nl00lllil); + wire_nl00O0iiO_dataout <= wire_nl00OiOiO_dataout AND NOT(nl00lllil); + wire_nl00O0il_dataout <= nl00OO0l WHEN niOO1lOiO = '1' ELSE nl00liii; + wire_nl00O0ili_dataout <= wire_nl00OiOli_dataout AND NOT(nl00lllil); + wire_nl00O0ill_dataout <= wire_nl00OiOll_dataout AND NOT(nl00lllil); + wire_nl00O0ilO_dataout <= wire_nl00OiOlO_dataout AND NOT(nl00lllil); + wire_nl00O0iO_dataout <= nl00OO0O WHEN niOO1lOiO = '1' ELSE nl00liil; + wire_nl00O0iOi_dataout <= wire_nl00OiOOi_dataout AND NOT(nl00lllil); + wire_nl00O0iOl_dataout <= wire_nl00OiOOl_dataout AND NOT(nl00lllil); + wire_nl00O0iOO_dataout <= wire_nl00OiOOO_dataout AND NOT(nl00lllil); + wire_nl00O0l0i_dataout <= wire_nl00Ol10i_dataout AND NOT(nl00lllil); + wire_nl00O0l0l_dataout <= wire_nl00Ol10l_dataout AND NOT(nl00lllil); + wire_nl00O0l0O_dataout <= wire_nl00Ol10O_dataout AND NOT(nl00lllil); + wire_nl00O0l1i_dataout <= wire_nl00Ol11i_dataout AND NOT(nl00lllil); + wire_nl00O0l1l_dataout <= wire_nl00Ol11l_dataout AND NOT(nl00lllil); + wire_nl00O0l1O_dataout <= wire_nl00Ol11O_dataout AND NOT(nl00lllil); + wire_nl00O0li_dataout <= nl00OOii WHEN niOO1lOiO = '1' ELSE nl00liiO; + wire_nl00O0lii_dataout <= wire_nl00Ol1ii_dataout AND NOT(nl00lllil); + wire_nl00O0lil_dataout <= wire_nl00Ol1il_dataout AND NOT(nl00lllil); + wire_nl00O0liO_dataout <= wire_nl00Ol1iO_dataout AND NOT(nl00lllil); + wire_nl00O0ll_dataout <= nl00OOil WHEN niOO1lOiO = '1' ELSE nl00lili; + wire_nl00O0lli_dataout <= wire_nl00Ol1li_dataout AND NOT(nl00lllil); + wire_nl00O0lll_dataout <= wire_nl00Ol1ll_dataout AND NOT(nl00lllil); + wire_nl00O0llO_dataout <= wire_nl00Ol1lO_dataout AND NOT(nl00lllil); + wire_nl00O0lO_dataout <= nl00OOiO WHEN niOO1lOiO = '1' ELSE nl00lill; + wire_nl00O0lOi_dataout <= wire_nl00Ol1Oi_dataout AND NOT(nl00lllil); + wire_nl00O0lOl_dataout <= wire_nl00Ol1Ol_dataout AND NOT(nl00lllil); + wire_nl00O0lOO_dataout <= wire_nl00Ol1OO_dataout AND NOT(nl00lllil); + wire_nl00O0O0i_dataout <= wire_nl00Ol00i_dataout AND NOT(nl00lllil); + wire_nl00O0O0l_dataout <= wire_nl00Ol00l_dataout AND NOT(nl00lllil); + wire_nl00O0O0O_dataout <= wire_nl00Ol00O_dataout AND NOT(nl00lllil); + wire_nl00O0O1i_dataout <= wire_nl00Ol01i_dataout AND NOT(nl00lllil); + wire_nl00O0O1l_dataout <= wire_nl00Ol01l_dataout AND NOT(nl00lllil); + wire_nl00O0O1O_dataout <= wire_nl00Ol01O_dataout AND NOT(nl00lllil); + wire_nl00O0Oi_dataout <= nl00OOli WHEN niOO1lOiO = '1' ELSE nl00lilO; + wire_nl00O0Oii_dataout <= wire_nl00Ol0ii_dataout AND NOT(nl00lllil); + wire_nl00O0Oil_dataout <= wire_nl00Ol0il_dataout AND NOT(nl00lllil); + wire_nl00O0OiO_dataout <= wire_nl00Ol0iO_dataout AND NOT(nl00lllil); + wire_nl00O0Ol_dataout <= nl00OOll WHEN niOO1lOiO = '1' ELSE nl00liOi; + wire_nl00O0Oli_dataout <= wire_nl00Ol0li_dataout AND NOT(nl00lllil); + wire_nl00O0Oll_dataout <= wire_nl00Ol0ll_dataout AND NOT(nl00lllil); + wire_nl00O0OlO_dataout <= nlOiilil WHEN nl00lllil = '1' ELSE wire_nl00Ol0lO_dataout; + wire_nl00O0OO_dataout <= nl00OOlO WHEN niOO1lOiO = '1' ELSE nl00liOl; + wire_nl00O0OOi_dataout <= nlOiiliO WHEN nl00lllil = '1' ELSE wire_nl00Ol0Oi_dataout; + wire_nl00O0OOl_dataout <= nlOiilli WHEN nl00lllil = '1' ELSE wire_nl00Ol0Ol_dataout; + wire_nl00O0OOO_dataout <= nlOiilll WHEN nl00lllil = '1' ELSE wire_nl00Ol0OO_dataout; + wire_nl00O100i_dataout <= wire_nl00Oiiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O100l_dataout <= wire_nl00OiiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O100O_dataout <= wire_nl00Oiili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O101i_dataout <= wire_nl00Oii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O101l_dataout <= wire_nl00Oii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O101O_dataout <= wire_nl00Oiiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10i_dataout <= wire_nl00Oi0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O10ii_dataout <= wire_nl00Oiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10il_dataout <= wire_nl00OiilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10iO_dataout <= wire_nl00OiiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10l_dataout <= wire_nl00Oi0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O10li_dataout <= wire_nl00OiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10ll_dataout <= wire_nl00OiiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10lO_dataout <= wire_nl00Oil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10O_dataout <= wire_nl00Oi0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O10Oi_dataout <= wire_nl00Oil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10Ol_dataout <= wire_nl00Oil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O10OO_dataout <= wire_nl00Oil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O110i_dataout <= wire_nl00Oi0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O110l_dataout <= wire_nl00Oi0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O110O_dataout <= wire_nl00Oi0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O111i_dataout <= wire_nl00Oi00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O111l_dataout <= wire_nl00Oi00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O111O_dataout <= wire_nl00Oi0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11i_dataout <= wire_nl00Oi1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O11ii_dataout <= wire_nl00Oi0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11il_dataout <= wire_nl00Oi0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11iO_dataout <= wire_nl00Oi0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11l_dataout <= wire_nl00Oi1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O11li_dataout <= wire_nl00Oi0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11ll_dataout <= wire_nl00Oi0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11lO_dataout <= wire_nl00Oii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11O_dataout <= wire_nl00Oi1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O11Oi_dataout <= wire_nl00Oii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11Ol_dataout <= wire_nl00Oii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O11OO_dataout <= wire_nl00Oii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1i0i_dataout <= wire_nl00Oilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1i0l_dataout <= wire_nl00OiliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1i0O_dataout <= wire_nl00Oilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1i1i_dataout <= wire_nl00Oil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1i1l_dataout <= wire_nl00Oil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1i1O_dataout <= wire_nl00Oilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1ii_dataout <= wire_nl00Oiii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1iii_dataout <= wire_nl00Oilll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1iil_dataout <= wire_nl00OillO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1iiO_dataout <= wire_nl00OilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1il_dataout <= wire_nl00Oiil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1ili_dataout <= wire_nl00OilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1ill_dataout <= wire_nl00OilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1ilO_dataout <= wire_nl00OiO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl00O1iO_dataout <= wire_nl00OiiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1iOi_dataout <= niOO1i10l WHEN nl00li00l = '1' ELSE wire_nl00O1OOO_dataout; + wire_nl00O1iOl_dataout <= niOO1i10O WHEN nl00li00l = '1' ELSE wire_nl00O011i_dataout; + wire_nl00O1iOO_dataout <= niOO1i1ii WHEN nl00li00l = '1' ELSE wire_nl00O011l_dataout; + wire_nl00O1l0i_dataout <= niOO1i1ll WHEN nl00li00l = '1' ELSE wire_nl00O010O_dataout; + wire_nl00O1l0l_dataout <= niOO1i1lO WHEN nl00li00l = '1' ELSE wire_nl00O01ii_dataout; + wire_nl00O1l0O_dataout <= niOO1i1Oi WHEN nl00li00l = '1' ELSE wire_nl00O01il_dataout; + wire_nl00O1l1i_dataout <= niOO1i1il WHEN nl00li00l = '1' ELSE wire_nl00O011O_dataout; + wire_nl00O1l1l_dataout <= niOO1i1iO WHEN nl00li00l = '1' ELSE wire_nl00O010i_dataout; + wire_nl00O1l1O_dataout <= niOO1i1li WHEN nl00li00l = '1' ELSE wire_nl00O010l_dataout; + wire_nl00O1li_dataout <= wire_nl00Oili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1lii_dataout <= niOO1i1Ol WHEN nl00li00l = '1' ELSE wire_nl00O01iO_dataout; + wire_nl00O1lil_dataout <= niOO1i1OO WHEN nl00li00l = '1' ELSE wire_nl00O01li_dataout; + wire_nl00O1liO_dataout <= niOO1i01i WHEN nl00li00l = '1' ELSE wire_nl00O01ll_dataout; + wire_nl00O1ll_dataout <= wire_nl00Oill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1lli_dataout <= niOO1i01l WHEN nl00li00l = '1' ELSE wire_nl00O01lO_dataout; + wire_nl00O1lll_dataout <= niOO1i01O WHEN nl00li00l = '1' ELSE wire_nl00O01Oi_dataout; + wire_nl00O1llO_dataout <= niOO1i00i WHEN nl00li00l = '1' ELSE wire_nl00O01Ol_dataout; + wire_nl00O1lO_dataout <= wire_nl00OilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1lOi_dataout <= niOO1i00l WHEN nl00li00l = '1' ELSE wire_nl00O01OO_dataout; + wire_nl00O1lOl_dataout <= niOO1i00O WHEN nl00li00l = '1' ELSE wire_nl00O001i_dataout; + wire_nl00O1lOO_dataout <= niOO1i0ii WHEN nl00li00l = '1' ELSE wire_nl00O001l_dataout; + wire_nl00O1O0i_dataout <= niOO1i0ll WHEN nl00li00l = '1' ELSE wire_nl00O000O_dataout; + wire_nl00O1O0l_dataout <= niOO1i0lO WHEN nl00li00l = '1' ELSE wire_nl00O00ii_dataout; + wire_nl00O1O0O_dataout <= niOO1i0Oi WHEN nl00li00l = '1' ELSE wire_nl00O00il_dataout; + wire_nl00O1O1i_dataout <= niOO1i0il WHEN nl00li00l = '1' ELSE wire_nl00O001O_dataout; + wire_nl00O1O1l_dataout <= niOO1i0iO WHEN nl00li00l = '1' ELSE wire_nl00O000i_dataout; + wire_nl00O1O1O_dataout <= niOO1i0li WHEN nl00li00l = '1' ELSE wire_nl00O000l_dataout; + wire_nl00O1Oi_dataout <= wire_nl00OiOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1Oii_dataout <= niOO1i0Ol WHEN nl00li00l = '1' ELSE wire_nl00O00iO_dataout; + wire_nl00O1Oil_dataout <= niOO1i0OO WHEN nl00li00l = '1' ELSE wire_nl00O00li_dataout; + wire_nl00O1OiO_dataout <= niOO1ii1i WHEN nl00li00l = '1' ELSE wire_nl00O00ll_dataout; + wire_nl00O1Ol_dataout <= wire_nl00OiOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1Oli_dataout <= niOO1ii1l WHEN nl00li00l = '1' ELSE wire_nl00O00lO_dataout; + wire_nl00O1Oll_dataout <= niOO1ii1O WHEN nl00li00l = '1' ELSE wire_nl00O00Oi_dataout; + wire_nl00O1OlO_dataout <= niOO1ii0i WHEN nl00li00l = '1' ELSE wire_nl00O00Ol_dataout; + wire_nl00O1OO_dataout <= wire_nl00OiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl00O1OOi_dataout <= niOO1ii0l WHEN nl00li00l = '1' ELSE wire_nl00O00OO_dataout; + wire_nl00O1OOl_dataout <= niOO1ii0O WHEN nl00li00l = '1' ELSE wire_nl00O0i1i_dataout; + wire_nl00O1OOO_dataout <= wire_nl0l0l0OO_dataout WHEN nl00li00O = '1' ELSE nl00li0il; + wire_nl00Oi00i_dataout <= nlOiiOOO WHEN nl00lllil = '1' ELSE wire_nl00Oll0i_dataout; + wire_nl00Oi00l_dataout <= nlOil11i WHEN nl00lllil = '1' ELSE wire_nl00Oll0l_dataout; + wire_nl00Oi00O_dataout <= wire_nl00Oll0O_dataout AND NOT(nl00lllil); + wire_nl00Oi01i_dataout <= nlOiiOlO WHEN nl00lllil = '1' ELSE wire_nl00Oll1i_dataout; + wire_nl00Oi01l_dataout <= nlOiiOOi WHEN nl00lllil = '1' ELSE wire_nl00Oll1l_dataout; + wire_nl00Oi01O_dataout <= nlOiiOOl WHEN nl00lllil = '1' ELSE wire_nl00Oll1O_dataout; + wire_nl00Oi0i_dataout <= nl0i11ii WHEN niOO1lOiO = '1' ELSE nl00ll1O; + wire_nl00Oi0ii_dataout <= wire_nl00Ollii_dataout AND NOT(nl00lllil); + wire_nl00Oi0il_dataout <= wire_nl00Ollil_dataout OR nl00lllil; + wire_nl00Oi0iO_dataout <= wire_nl00OlliO_dataout AND NOT(nl00lllil); + wire_nl00Oi0l_dataout <= nl0i11il WHEN niOO1lOiO = '1' ELSE nl00ll0i; + wire_nl00Oi0li_dataout <= wire_nl00Ollli_dataout AND NOT(nl00lllil); + wire_nl00Oi0ll_dataout <= wire_nl00Ollll_dataout AND NOT(nl00lllil); + wire_nl00Oi0lO_dataout <= wire_nl00OlllO_dataout AND NOT(nl00lllil); + wire_nl00Oi0O_dataout <= nl0i11iO WHEN niOO1lOiO = '1' ELSE nl00ll0l; + wire_nl00Oi0Oi_dataout <= wire_nl00OllOi_dataout AND NOT(nl00lllil); + wire_nl00Oi0Ol_dataout <= wire_nl00OllOl_dataout AND NOT(nl00lllil); + wire_nl00Oi0OO_dataout <= wire_nl00OllOO_dataout AND NOT(nl00lllil); + wire_nl00Oi10i_dataout <= nlOiilOO WHEN nl00lllil = '1' ELSE wire_nl00Oli0i_dataout; + wire_nl00Oi10l_dataout <= nlOiiO1i WHEN nl00lllil = '1' ELSE wire_nl00Oli0l_dataout; + wire_nl00Oi10O_dataout <= nlOiiO1l WHEN nl00lllil = '1' ELSE wire_nl00Oli0O_dataout; + wire_nl00Oi11i_dataout <= nlOiillO WHEN nl00lllil = '1' ELSE wire_nl00Oli1i_dataout; + wire_nl00Oi11l_dataout <= nlOiilOi WHEN nl00lllil = '1' ELSE wire_nl00Oli1l_dataout; + wire_nl00Oi11O_dataout <= nlOiilOl WHEN nl00lllil = '1' ELSE wire_nl00Oli1O_dataout; + wire_nl00Oi1i_dataout <= nl00OOOi WHEN niOO1lOiO = '1' ELSE nl00liOO; + wire_nl00Oi1ii_dataout <= nlOiiO1O WHEN nl00lllil = '1' ELSE wire_nl00Oliii_dataout; + wire_nl00Oi1il_dataout <= nlOiiO0i WHEN nl00lllil = '1' ELSE wire_nl00Oliil_dataout; + wire_nl00Oi1iO_dataout <= nlOiiO0l WHEN nl00lllil = '1' ELSE wire_nl00OliiO_dataout; + wire_nl00Oi1l_dataout <= nl0i110l WHEN niOO1lOiO = '1' ELSE nl00ll1i; + wire_nl00Oi1li_dataout <= nlOiiO0O WHEN nl00lllil = '1' ELSE wire_nl00Olili_dataout; + wire_nl00Oi1ll_dataout <= nlOiiOii WHEN nl00lllil = '1' ELSE wire_nl00Olill_dataout; + wire_nl00Oi1lO_dataout <= nlOiiOil WHEN nl00lllil = '1' ELSE wire_nl00OlilO_dataout; + wire_nl00Oi1O_dataout <= nl0i110O WHEN niOO1lOiO = '1' ELSE nl00ll1l; + wire_nl00Oi1Oi_dataout <= nlOiiOiO WHEN nl00lllil = '1' ELSE wire_nl00OliOi_dataout; + wire_nl00Oi1Ol_dataout <= nlOiiOli WHEN nl00lllil = '1' ELSE wire_nl00OliOl_dataout; + wire_nl00Oi1OO_dataout <= nlOiiOll WHEN nl00lllil = '1' ELSE wire_nl00OliOO_dataout; + wire_nl00Oii0i_dataout <= nlOil01i WHEN nl00lllil = '1' ELSE wire_nl00OlO0i_dataout; + wire_nl00Oii0l_dataout <= wire_nl00OlO0l_dataout AND NOT(nl00lllil); + wire_nl00Oii0O_dataout <= wire_nl00OlO0O_dataout AND NOT(nl00lllil); + wire_nl00Oii1i_dataout <= wire_nl00OlO1i_dataout AND NOT(nl00lllil); + wire_nl00Oii1l_dataout <= wire_nl00OlO1l_dataout AND NOT(nl00lllil); + wire_nl00Oii1O_dataout <= wire_nl00OlO1O_dataout AND NOT(nl00lllil); + wire_nl00Oiii_dataout <= nl0i11li WHEN niOO1lOiO = '1' ELSE nl00ll0O; + wire_nl00Oiiii_dataout <= wire_w_lg_niOi0O11i52280w(0) WHEN nl00lllil = '1' ELSE wire_nl00OlOii_dataout; + wire_nl00Oiiil_dataout <= wire_nl00OlOil_dataout AND NOT(nl00lllil); + wire_nl00OiiiO_dataout <= wire_nl00OlOiO_dataout AND NOT(nl00lllil); + wire_nl00Oiil_dataout <= nl0i11ll WHEN niOO1lOiO = '1' ELSE nl00llii; + wire_nl00Oiili_dataout <= wire_nl00OlOli_dataout AND NOT(nl00lllil); + wire_nl00Oiill_dataout <= wire_nl00OlOll_dataout AND NOT(nl00lllil); + wire_nl00OiilO_dataout <= wire_nl00OlOlO_dataout AND NOT(nl00lllil); + wire_nl00OiiO_dataout <= nl0i11lO WHEN niOO1lOiO = '1' ELSE nl00llil; + wire_nl00OiiOi_dataout <= wire_nl00OlOOi_dataout AND NOT(nl00lllil); + wire_nl00OiiOl_dataout <= wire_nl00OlOOl_dataout AND NOT(nl00lllil); + wire_nl00OiiOO_dataout <= wire_nl00OlOOO_dataout AND NOT(nl00lllil); + wire_nl00Oil0i_dataout <= wire_nl00OO10i_dataout AND NOT(nl00lllil); + wire_nl00Oil0l_dataout <= wire_nl00OO10l_dataout AND NOT(nl00lllil); + wire_nl00Oil0O_dataout <= wire_nl00OO10O_dataout AND NOT(nl00lllil); + wire_nl00Oil1i_dataout <= wire_nl00OO11i_dataout AND NOT(nl00lllil); + wire_nl00Oil1l_dataout <= wire_nl00OO11l_dataout AND NOT(nl00lllil); + wire_nl00Oil1O_dataout <= wire_nl00OO11O_dataout AND NOT(nl00lllil); + wire_nl00Oili_dataout <= nl0i11Oi WHEN niOO1lOiO = '1' ELSE nl00lliO; + wire_nl00Oilii_dataout <= wire_nl00OO1ii_dataout AND NOT(nl00lllil); + wire_nl00Oilil_dataout <= wire_nl00OO1il_dataout AND NOT(nl00lllil); + wire_nl00OiliO_dataout <= wire_nl00OO1iO_dataout AND NOT(nl00lllil); + wire_nl00Oill_dataout <= nl0i11Ol WHEN niOO1lOiO = '1' ELSE nl00llli; + wire_nl00Oilli_dataout <= wire_nl00OO1li_dataout OR nl00lllil; + wire_nl00Oilll_dataout <= wire_nl00OO1ll_dataout AND NOT(nl00lllil); + wire_nl00OillO_dataout <= wire_nl00OO1lO_dataout OR nl00lllil; + wire_nl00OilO_dataout <= nl0i11OO WHEN niOO1lOiO = '1' ELSE nl00llll; + wire_nl00OilOi_dataout <= wire_nl00OO1Oi_dataout AND NOT(nl00lllil); + wire_nl00OilOl_dataout <= wire_nl00OO1Ol_dataout AND NOT(nl00lllil); + wire_nl00OilOO_dataout <= wire_w_lg_niOi0O11i52280w(0) WHEN nl00lllil = '1' ELSE wire_nl00OO1OO_dataout; + wire_nl00OiO0i_dataout <= wire_nl0il00iO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO00i_dataout; + wire_nl00OiO0l_dataout <= wire_nl0il00li_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO00l_dataout; + wire_nl00OiO0O_dataout <= wire_nl0il00ll_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO00O_dataout; + wire_nl00OiO1i_dataout <= wire_nl00OO01i_dataout AND NOT(nl00lllil); + wire_nl00OiO1l_dataout <= wire_nl00OO01l_dataout AND NOT(nl0i1li1O); + wire_nl00OiO1O_dataout <= wire_nl00OO01O_dataout AND NOT(nl0i1li1O); + wire_nl00OiOi_dataout <= nl0i101i WHEN niOO1lOiO = '1' ELSE nl00lllO; + wire_nl00OiOii_dataout <= wire_nl0il00lO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0ii_dataout; + wire_nl00OiOil_dataout <= wire_nl0il00Oi_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0il_dataout; + wire_nl00OiOiO_dataout <= wire_nl0il00Ol_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0iO_dataout; + wire_nl00OiOl_dataout <= nl0i101l WHEN niOO1lOiO = '1' ELSE nl00llOi; + wire_nl00OiOli_dataout <= wire_nl0il00OO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0li_dataout; + wire_nl00OiOll_dataout <= wire_nl0il0i1i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0ll_dataout; + wire_nl00OiOlO_dataout <= wire_nl0il0i1l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0lO_dataout; + wire_nl00OiOO_dataout <= nl0i101O WHEN niOO1lOiO = '1' ELSE nl00llOl; + wire_nl00OiOOi_dataout <= wire_nl0il0i1O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0Oi_dataout; + wire_nl00OiOOl_dataout <= wire_nl0il0i0i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0Ol_dataout; + wire_nl00OiOOO_dataout <= wire_nl0il0i0l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OO0OO_dataout; + wire_nl00Ol00i_dataout <= wire_nl0il0liO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOl0i_dataout; + wire_nl00Ol00l_dataout <= wire_nl0il0lli_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOl0l_dataout; + wire_nl00Ol00O_dataout <= wire_nl0il0lll_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOl0O_dataout; + wire_nl00Ol01i_dataout <= wire_nl0il0l0O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOl1i_dataout; + wire_nl00Ol01l_dataout <= wire_nl0il0lii_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOl1l_dataout; + wire_nl00Ol01O_dataout <= wire_nl0il0lil_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOl1O_dataout; + wire_nl00Ol0ii_dataout <= wire_nl0il0llO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOlii_dataout; + wire_nl00Ol0il_dataout <= wire_nl0il0lOi_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOlil_dataout; + wire_nl00Ol0iO_dataout <= wire_nl0il0lOl_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOliO_dataout; + wire_nl00Ol0l_dataout <= nl00Olil AND NOT(wire_niO01O0O_dataout); + wire_nl00Ol0li_dataout <= wire_nl0il0lOO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOlli_dataout; + wire_nl00Ol0ll_dataout <= wire_nl0il0O1i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOlll_dataout; + wire_nl00Ol0lO_dataout <= wire_nl0il0O1l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOllO_dataout; + wire_nl00Ol0Oi_dataout <= wire_nl0il0O1O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOlOi_dataout; + wire_nl00Ol0Ol_dataout <= wire_nl0il0O0i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOlOl_dataout; + wire_nl00Ol0OO_dataout <= wire_nl0il0O0l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOlOO_dataout; + wire_nl00Ol10i_dataout <= wire_nl0il0iiO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOi0i_dataout; + wire_nl00Ol10l_dataout <= wire_nl0il0ili_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOi0l_dataout; + wire_nl00Ol10O_dataout <= wire_nl0il0ill_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOi0O_dataout; + wire_nl00Ol11i_dataout <= wire_nl0il0i0O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOi1i_dataout; + wire_nl00Ol11l_dataout <= wire_nl0il0iii_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOi1l_dataout; + wire_nl00Ol11O_dataout <= wire_nl0il0iil_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOi1O_dataout; + wire_nl00Ol1i_dataout <= nl0i100i WHEN niOO1lOiO = '1' ELSE nl00llOO; + wire_nl00Ol1ii_dataout <= wire_nl0il0ilO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOiii_dataout; + wire_nl00Ol1il_dataout <= wire_nl0il0iOi_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOiil_dataout; + wire_nl00Ol1iO_dataout <= wire_nl0il0iOl_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOiiO_dataout; + wire_nl00Ol1li_dataout <= wire_nl0il0iOO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOili_dataout; + wire_nl00Ol1ll_dataout <= wire_nl0il0l1i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOill_dataout; + wire_nl00Ol1lO_dataout <= wire_nl0il0l1l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOilO_dataout; + wire_nl00Ol1Oi_dataout <= wire_nl0il0l1O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOiOi_dataout; + wire_nl00Ol1Ol_dataout <= wire_nl0il0l0i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOiOl_dataout; + wire_nl00Ol1OO_dataout <= wire_nl0il0l0l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOiOO_dataout; + wire_nl00Oli0i_dataout <= wire_nl0il0OiO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOO0i_dataout; + wire_nl00Oli0l_dataout <= wire_nl0il0Oli_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOO0l_dataout; + wire_nl00Oli0O_dataout <= wire_nl0il0Oll_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOO0O_dataout; + wire_nl00Oli1i_dataout <= wire_nl0il0O0O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOO1i_dataout; + wire_nl00Oli1l_dataout <= wire_nl0il0Oii_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOO1l_dataout; + wire_nl00Oli1O_dataout <= wire_nl0il0Oil_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOO1O_dataout; + wire_nl00Olii_dataout <= nl00lO1i AND NOT(wire_niO01O0O_dataout); + wire_nl00Oliii_dataout <= wire_nl0il0OlO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOii_dataout; + wire_nl00Oliil_dataout <= wire_nl0il0OOi_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOil_dataout; + wire_nl00OliiO_dataout <= wire_nl0il0OOl_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOiO_dataout; + wire_nl00Olili_dataout <= wire_nl0il0OOO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOli_dataout; + wire_nl00Olill_dataout <= wire_nl0ili11i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOll_dataout; + wire_nl00OlilO_dataout <= wire_nl0ili11l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOlO_dataout; + wire_nl00OliO_dataout <= nl00Olll AND NOT(wire_niO01l0O_dataout); + wire_nl00OliOi_dataout <= wire_nl0ili11O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOOi_dataout; + wire_nl00OliOl_dataout <= wire_nl0ili10i_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOOl_dataout; + wire_nl00OliOO_dataout <= wire_nl0ili10l_dataout WHEN nl0i1li1O = '1' ELSE wire_nl00OOOOO_dataout; + wire_nl00Oll0i_dataout <= wire_nl0ili1iO_dataout WHEN nl0i1li1O = '1' ELSE wire_nl0i1110i_dataout; + wire_nl00Oll0l_dataout <= wire_nl0ili1li_dataout WHEN nl0i1li1O = '1' ELSE wire_nl0i1110l_dataout; + wire_nl00Oll0O_dataout <= wire_nl0i1110O_dataout OR nl0i1li1O; + wire_nl00Oll1i_dataout <= wire_nl0ili10O_dataout WHEN nl0i1li1O = '1' ELSE wire_nl0i1111i_dataout; + wire_nl00Oll1l_dataout <= wire_nl0ili1ii_dataout WHEN nl0i1li1O = '1' ELSE wire_nl0i1111l_dataout; + wire_nl00Oll1O_dataout <= wire_nl0ili1il_dataout WHEN nl0i1li1O = '1' ELSE wire_nl0i1111O_dataout; + wire_nl00Ollii_dataout <= wire_nl0i111ii_dataout OR nl0i1li1O; + wire_nl00Ollil_dataout <= wire_nl0i111il_dataout OR nl0i1li1O; + wire_nl00OlliO_dataout <= wire_nl0i111iO_dataout OR nl0i1li1O; + wire_nl00Ollli_dataout <= wire_nl0i111li_dataout AND NOT(nl0i1li1O); + wire_nl00Ollll_dataout <= wire_nl0i111ll_dataout AND NOT(nl0i1li1O); + wire_nl00OlllO_dataout <= wire_nl0i111lO_dataout AND NOT(nl0i1li1O); + wire_nl00OllO_dataout <= nl00Olli AND NOT(wire_niO01l0O_dataout); + wire_nl00OllOi_dataout <= wire_nl0i111Oi_dataout AND NOT(nl0i1li1O); + wire_nl00OllOl_dataout <= wire_nl0i111Ol_dataout AND NOT(nl0i1li1O); + wire_nl00OllOO_dataout <= wire_nl0i111OO_dataout AND NOT(nl0i1li1O); + wire_nl00OlO0i_dataout <= wire_nl0i1100i_dataout AND NOT(nl0i1li1O); + wire_nl00OlO0l_dataout <= wire_nl0i1100l_dataout AND NOT(nl0i1li1O); + wire_nl00OlO0O_dataout <= wire_nl0i1100O_dataout AND NOT(nl0i1li1O); + wire_nl00OlO1i_dataout <= wire_nl0i1101i_dataout AND NOT(nl0i1li1O); + wire_nl00OlO1l_dataout <= wire_nl0i1101l_dataout AND NOT(nl0i1li1O); + wire_nl00OlO1O_dataout <= wire_nl0i1101O_dataout AND NOT(nl0i1li1O); + wire_nl00OlOi_dataout <= nl00Ol0O AND NOT(wire_niO01l0O_dataout); + wire_nl00OlOii_dataout <= wire_nl0i110ii_dataout OR nl0i1li1O; + wire_nl00OlOil_dataout <= wire_nl0i110il_dataout AND NOT(nl0i1li1O); + wire_nl00OlOiO_dataout <= wire_nl0i110iO_dataout AND NOT(nl0i1li1O); + wire_nl00OlOli_dataout <= wire_nl0i110li_dataout AND NOT(nl0i1li1O); + wire_nl00OlOll_dataout <= wire_nl0i110ll_dataout AND NOT(nl0i1li1O); + wire_nl00OlOlO_dataout <= wire_nl0i110lO_dataout AND NOT(nl0i1li1O); + wire_nl00OlOOi_dataout <= wire_nl0i110Oi_dataout AND NOT(nl0i1li1O); + wire_nl00OlOOl_dataout <= wire_nl0i110Ol_dataout AND NOT(nl0i1li1O); + wire_nl00OlOOO_dataout <= wire_nl0i110OO_dataout AND NOT(nl0i1li1O); + wire_nl00OO00i_dataout <= wire_nl0i11l0i_dataout AND NOT(nl0i1li0i); + wire_nl00OO00l_dataout <= wire_nl0i11l0l_dataout AND NOT(nl0i1li0i); + wire_nl00OO00O_dataout <= wire_nl0i11l0O_dataout AND NOT(nl0i1li0i); + wire_nl00OO01i_dataout <= nl0l0i1ii WHEN nl0i1li1O = '1' ELSE wire_nl0i11l1i_dataout; + wire_nl00OO01l_dataout <= wire_nl0i11l1l_dataout AND NOT(nl0i1li0i); + wire_nl00OO01O_dataout <= wire_nl0i11l1O_dataout AND NOT(nl0i1li0i); + wire_nl00OO0ii_dataout <= wire_nl0i11lii_dataout AND NOT(nl0i1li0i); + wire_nl00OO0il_dataout <= wire_nl0i11lil_dataout AND NOT(nl0i1li0i); + wire_nl00OO0iO_dataout <= wire_nl0i11liO_dataout AND NOT(nl0i1li0i); + wire_nl00OO0li_dataout <= wire_nl0i11lli_dataout AND NOT(nl0i1li0i); + wire_nl00OO0ll_dataout <= wire_nl0i11lll_dataout AND NOT(nl0i1li0i); + wire_nl00OO0lO_dataout <= wire_nl0i11llO_dataout AND NOT(nl0i1li0i); + wire_nl00OO0Oi_dataout <= wire_nl0i11lOi_dataout AND NOT(nl0i1li0i); + wire_nl00OO0Ol_dataout <= wire_nl0i11lOl_dataout AND NOT(nl0i1li0i); + wire_nl00OO0OO_dataout <= wire_nl0i11lOO_dataout AND NOT(nl0i1li0i); + wire_nl00OO10i_dataout <= wire_nl0i11i0i_dataout AND NOT(nl0i1li1O); + wire_nl00OO10l_dataout <= nliiO11OO WHEN nl0i1li1O = '1' ELSE wire_nl0i11i0l_dataout; + wire_nl00OO10O_dataout <= nl0l0i1Oi WHEN nl0i1li1O = '1' ELSE wire_nl0i11i0O_dataout; + wire_nl00OO11i_dataout <= wire_nl0i11i1i_dataout AND NOT(nl0i1li1O); + wire_nl00OO11l_dataout <= wire_nl0i11i1l_dataout AND NOT(nl0i1li1O); + wire_nl00OO11O_dataout <= wire_nl0i11i1O_dataout AND NOT(nl0i1li1O); + wire_nl00OO1ii_dataout <= nl0l0i1Ol WHEN nl0i1li1O = '1' ELSE wire_nl0i11iii_dataout; + wire_nl00OO1il_dataout <= nl0l0i1OO WHEN nl0i1li1O = '1' ELSE wire_nl0i11iil_dataout; + wire_nl00OO1iO_dataout <= wire_nl0i11iiO_dataout AND NOT(nl0i1li1O); + wire_nl00OO1li_dataout <= wire_nl0i11ili_dataout AND NOT(nl0i1li1O); + wire_nl00OO1ll_dataout <= wire_nl0i11ill_dataout AND NOT(nl0i1li1O); + wire_nl00OO1lO_dataout <= wire_nl0i11ilO_dataout AND NOT(nl0i1li1O); + wire_nl00OO1Oi_dataout <= wire_nl0i11iOi_dataout AND NOT(nl0i1li1O); + wire_nl00OO1Ol_dataout <= nl0i00iiO WHEN nl0i1li1O = '1' ELSE wire_nl0i11iOl_dataout; + wire_nl00OO1OO_dataout <= wire_nl0i11iOO_dataout OR nl0i1li1O; + wire_nl00OOi0i_dataout <= wire_nl0i11O0i_dataout AND NOT(nl0i1li0i); + wire_nl00OOi0l_dataout <= wire_nl0i11O0l_dataout AND NOT(nl0i1li0i); + wire_nl00OOi0O_dataout <= wire_nl0i11O0O_dataout AND NOT(nl0i1li0i); + wire_nl00OOi1i_dataout <= wire_nl0i11O1i_dataout AND NOT(nl0i1li0i); + wire_nl00OOi1l_dataout <= wire_nl0i11O1l_dataout AND NOT(nl0i1li0i); + wire_nl00OOi1O_dataout <= wire_nl0i11O1O_dataout AND NOT(nl0i1li0i); + wire_nl00OOiii_dataout <= wire_nl0i11Oii_dataout AND NOT(nl0i1li0i); + wire_nl00OOiil_dataout <= wire_nl0i11Oil_dataout AND NOT(nl0i1li0i); + wire_nl00OOiiO_dataout <= wire_nl0i11OiO_dataout AND NOT(nl0i1li0i); + wire_nl00OOili_dataout <= wire_nl0i11Oli_dataout AND NOT(nl0i1li0i); + wire_nl00OOill_dataout <= wire_nl0i11Oll_dataout AND NOT(nl0i1li0i); + wire_nl00OOilO_dataout <= wire_nl0i11OlO_dataout AND NOT(nl0i1li0i); + wire_nl00OOiOi_dataout <= wire_nl0i11OOi_dataout AND NOT(nl0i1li0i); + wire_nl00OOiOl_dataout <= wire_nl0i11OOl_dataout AND NOT(nl0i1li0i); + wire_nl00OOiOO_dataout <= wire_nl0i11OOO_dataout AND NOT(nl0i1li0i); + wire_nl00OOl0i_dataout <= wire_nl0i1010i_dataout AND NOT(nl0i1li0i); + wire_nl00OOl0l_dataout <= wire_nl0i1010l_dataout AND NOT(nl0i1li0i); + wire_nl00OOl0O_dataout <= wire_nl0i1010O_dataout AND NOT(nl0i1li0i); + wire_nl00OOl1i_dataout <= wire_nl0i1011i_dataout AND NOT(nl0i1li0i); + wire_nl00OOl1l_dataout <= wire_nl0i1011l_dataout AND NOT(nl0i1li0i); + wire_nl00OOl1O_dataout <= wire_nl0i1011O_dataout AND NOT(nl0i1li0i); + wire_nl00OOlii_dataout <= wire_nl0i101ii_dataout AND NOT(nl0i1li0i); + wire_nl00OOlil_dataout <= wire_nl0i101il_dataout AND NOT(nl0i1li0i); + wire_nl00OOliO_dataout <= wire_nl0i101iO_dataout AND NOT(nl0i1li0i); + wire_nl00OOlli_dataout <= wire_nl0i101li_dataout AND NOT(nl0i1li0i); + wire_nl00OOlll_dataout <= wire_nl0i101ll_dataout AND NOT(nl0i1li0i); + wire_nl00OOllO_dataout <= wire_nl0i101lO_dataout AND NOT(nl0i1li0i); + wire_nl00OOlOi_dataout <= wire_nl0i101Oi_dataout AND NOT(nl0i1li0i); + wire_nl00OOlOl_dataout <= wire_nl0i101Ol_dataout AND NOT(nl0i1li0i); + wire_nl00OOlOO_dataout <= wire_nl0i101OO_dataout AND NOT(nl0i1li0i); + wire_nl00OOO0i_dataout <= wire_nl0i1000i_dataout AND NOT(nl0i1li0i); + wire_nl00OOO0l_dataout <= wire_nl0i1000l_dataout AND NOT(nl0i1li0i); + wire_nl00OOO0O_dataout <= wire_nl0i1000O_dataout AND NOT(nl0i1li0i); + wire_nl00OOO1i_dataout <= wire_nl0i1001i_dataout AND NOT(nl0i1li0i); + wire_nl00OOO1l_dataout <= wire_nl0i1001l_dataout AND NOT(nl0i1li0i); + wire_nl00OOO1O_dataout <= wire_nl0i1001O_dataout AND NOT(nl0i1li0i); + wire_nl00OOOii_dataout <= wire_nl0i100ii_dataout AND NOT(nl0i1li0i); + wire_nl00OOOil_dataout <= wire_nl0i100il_dataout AND NOT(nl0i1li0i); + wire_nl00OOOiO_dataout <= wire_nl0i100iO_dataout AND NOT(nl0i1li0i); + wire_nl00OOOli_dataout <= wire_nl0i100li_dataout AND NOT(nl0i1li0i); + wire_nl00OOOll_dataout <= wire_nl0i100ll_dataout AND NOT(nl0i1li0i); + wire_nl00OOOlO_dataout <= wire_nl0i100lO_dataout AND NOT(nl0i1li0i); + wire_nl00OOOOi_dataout <= wire_nl0i100Oi_dataout AND NOT(nl0i1li0i); + wire_nl00OOOOl_dataout <= wire_nl0i100Ol_dataout AND NOT(nl0i1li0i); + wire_nl00OOOOO_dataout <= wire_nl0i100OO_dataout AND NOT(nl0i1li0i); + wire_nl01000i_dataout <= wire_nl010l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01000l_dataout <= wire_nl010l0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01000O_dataout <= wire_nl010l0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01001i_dataout <= wire_nl010iOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01001l_dataout <= wire_nl010l1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01001O_dataout <= wire_nl010l1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100i_dataout <= nli1liOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0100ii_dataout <= wire_nl010l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100il_dataout <= wire_nl010lii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100iO_dataout <= wire_nl010lil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100l_dataout <= nli1liOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0100li_dataout <= wire_nl010liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100ll_dataout <= wire_nl010lli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100lO_dataout <= wire_nl010lll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100O_dataout <= nli1liOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0100Oi_dataout <= wire_nl010llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100Oii_dataout <= wire_nl010O11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100Oil_dataout <= wire_nl010l11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100OiO_dataout <= wire_nl010l11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100Ol_dataout <= wire_nl010lOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100Oli_dataout <= wire_nl010l11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100Oll_dataout <= wire_nl010l10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100OlO_dataout <= wire_nl010l10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100OO_dataout <= wire_nl010lOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0100OOi_dataout <= wire_nl010l10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100OOl_dataout <= wire_nl010l1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0100OOO_dataout <= wire_nl010l1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010100i_dataout <= wire_nl01010ii_dataout AND NOT(nl01ii11O); + wire_nl010100l_dataout <= wire_nl01010il_dataout OR nl01ii10i; + wire_nl010100O_dataout <= wire_nl01010iO_dataout OR nl01ii10i; + wire_nl010101i_dataout <= wire_nl010100i_dataout AND NOT(nl01ii11l); + wire_nl010101l_dataout <= wire_nl010100l_dataout AND NOT(nl01ii11O); + wire_nl010101O_dataout <= wire_nl010100O_dataout OR nl01ii11O; + wire_nl01010ii_dataout <= wire_nl01010li_dataout AND NOT(nl01ii10i); + wire_nl01010il_dataout <= wire_nl01010ll_dataout AND NOT(nl01ii10l); + wire_nl01010iO_dataout <= wire_nl01010lO_dataout AND NOT(nl01ii10l); + wire_nl01010li_dataout <= wire_nl01010Oi_dataout OR nl01ii10l; + wire_nl01010ll_dataout <= wire_nl01010Ol_dataout OR nl01ii10O; + wire_nl01010lO_dataout <= wire_nl01010OO_dataout AND NOT(nl01ii10O); + wire_nl01010Oi_dataout <= wire_nl01010OO_dataout OR nl01ii10O; + wire_nl01010Ol_dataout <= nl01ii1il AND NOT(nl01ii1ii); + wire_nl01010OO_dataout <= nl01ii1il OR nl01ii1ii; + wire_nl010110i_dataout <= wire_nl0101i1i_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nl0100iiO; + wire_nl010110O_dataout <= wire_nl01011ll_dataout WHEN nl011ll0i = '1' ELSE nl0100iOi; + wire_nl010111i_dataout <= wire_nilOl1lO_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nl0100i1O; + wire_nl010111l_dataout <= wire_nilOl1Oi_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nl0100i0i; + wire_nl010111O_dataout <= wire_nilOl1Ol_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nl0100i0l; + wire_nl01011ii_dataout <= wire_nl01011lO_dataout WHEN nl011ll0i = '1' ELSE nl0100iOl; + wire_nl01011il_dataout <= wire_nl01011Oi_dataout WHEN nl011ll0i = '1' ELSE nl0100iOO; + wire_nl01011iO_dataout <= nl0100l1i AND NOT(nl011ll0i); + wire_nl01011li_dataout <= nl0100lOO WHEN wire_nilOi0iO_dataout = '1' ELSE nl0100l1l; + wire_nl01011ll_dataout <= wire_nl01011Ol_dataout AND NOT(nl01ii11i); + wire_nl01011lO_dataout <= wire_nl01011OO_dataout AND NOT(nl01ii11i); + wire_nl01011Oi_dataout <= wire_nl010101i_dataout AND NOT(nl01ii11i); + wire_nl01011Ol_dataout <= wire_nl010101l_dataout OR nl01ii11l; + wire_nl01011OO_dataout <= wire_nl010101O_dataout AND NOT(nl01ii11l); + wire_nl0101i_dataout <= nli1lili WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1ll0l; + wire_nl0101i0i_dataout <= wire_nl01i101l_dataout WHEN niOi01lii = '1' ELSE wire_nl0101iOi_dataout; + wire_nl0101i0l_dataout <= wire_nl01i101O_dataout WHEN niOi01lii = '1' ELSE wire_nl0101iOl_dataout; + wire_nl0101i0O_dataout <= wire_nl01i100i_dataout WHEN niOi01lii = '1' ELSE wire_nl0101iOO_dataout; + wire_nl0101i1i_dataout <= wire_nilOi0Ol_dataout WHEN nl0100iOO = '1' ELSE wire_nilOiO1i_dataout; + wire_nl0101iii_dataout <= wire_nl01i100l_dataout WHEN niOi01lii = '1' ELSE wire_nl0101l1i_dataout; + wire_nl0101iil_dataout <= wire_nl01i100O_dataout WHEN niOi01lii = '1' ELSE wire_nl0101l1l_dataout; + wire_nl0101iiO_dataout <= wire_nl01i10ii_dataout WHEN niOi01lii = '1' ELSE wire_nl0101l1O_dataout; + wire_nl0101ili_dataout <= wire_nl01i10il_dataout WHEN niOi01lii = '1' ELSE wire_nl0101l0i_dataout; + wire_nl0101ill_dataout <= wire_nl01i10iO_dataout WHEN niOi01lii = '1' ELSE wire_nl0101l0l_dataout; + wire_nl0101ilO_dataout <= niOi01OlO WHEN niOi01lii = '1' ELSE wire_nl0101l0O_dataout; + wire_nl0101iOi_dataout <= nl0100l1O AND NOT(niOi01l0O); + wire_nl0101iOl_dataout <= nl0100l0i AND NOT(niOi01l0O); + wire_nl0101iOO_dataout <= nl0100l0l AND NOT(niOi01l0O); + wire_nl0101l_dataout <= nli1lill WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1llii; + wire_nl0101l0i_dataout <= nl0100liO AND NOT(niOi01l0O); + wire_nl0101l0l_dataout <= nl0100lli AND NOT(niOi01l0O); + wire_nl0101l0O_dataout <= nl0100lll AND NOT(niOi01l0O); + wire_nl0101l1i_dataout <= nl0100l0O AND NOT(niOi01l0O); + wire_nl0101l1l_dataout <= nl0100lii AND NOT(niOi01l0O); + wire_nl0101l1O_dataout <= nl0100lil AND NOT(niOi01l0O); + wire_nl0101lll_dataout <= wire_nl01i1i1i_dataout WHEN niOi01lil = '1' ELSE nl0100llO; + wire_nl0101lll_w_lg_dataout59086w(0) <= NOT wire_nl0101lll_dataout; + wire_nl0101llO_dataout <= niOi0011l WHEN niOi01lil = '1' ELSE nl0100lOi; + wire_nl0101llO_w_lg_dataout59085w(0) <= NOT wire_nl0101llO_dataout; + wire_nl0101O_dataout <= nli1lilO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0101Oi_dataout <= wire_nl010ill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0101Ol_dataout <= wire_nl010iOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0101OO_dataout <= wire_nl010iOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010i00i_dataout <= wire_nl010l0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i00l_dataout <= wire_nl010l0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i00O_dataout <= wire_nl010l0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i01i_dataout <= wire_nl010l0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i01l_dataout <= wire_nl010l0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i01O_dataout <= wire_nl010l0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0i_dataout <= wire_nl010O1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010i0ii_dataout <= wire_nl010l0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0il_dataout <= wire_nl010li1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0iO_dataout <= wire_nl010li1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0l_dataout <= wire_nl010O0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010i0li_dataout <= wire_nl010li1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0ll_dataout <= wire_nl010li0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0lO_dataout <= wire_nl010li0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0O_dataout <= wire_nl010O0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010i0Oi_dataout <= wire_nl010li0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0Ol_dataout <= wire_nl010liii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i0OO_dataout <= wire_nl010liil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i10i_dataout <= wire_nl010l1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i10l_dataout <= wire_nl010l1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i10O_dataout <= wire_nl010l1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i11i_dataout <= wire_nl010l1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i11l_dataout <= wire_nl010l1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i11O_dataout <= wire_nl010l1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1i_dataout <= wire_nl010lOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010i1ii_dataout <= wire_nl010l1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1il_dataout <= wire_nl010l01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1iO_dataout <= wire_nl010l01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1l_dataout <= wire_nl010O1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010i1li_dataout <= wire_nl010l01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1ll_dataout <= wire_nl010l00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1lO_dataout <= wire_nl010l00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1O_dataout <= wire_nl010O1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010i1Oi_dataout <= wire_nl010l00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1Ol_dataout <= wire_nl010l0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010i1OO_dataout <= wire_nl010l0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ii_dataout <= nli1l0OO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1ll1l; + wire_nl010ii0i_dataout <= wire_nl010lilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ii0l_dataout <= wire_nl010liOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ii0O_dataout <= wire_nl010liOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ii1i_dataout <= wire_nl010liiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ii1l_dataout <= wire_nl010lili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ii1O_dataout <= wire_nl010lill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iii_dataout <= wire_nl010O0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010iiii_dataout <= wire_nl010liOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iiil_dataout <= wire_nl010ll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iiiO_dataout <= wire_nl010ll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iil_dataout <= wire_nl010Oii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010iili_dataout <= wire_nl010ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iill_dataout <= wire_nl010ll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iilO_dataout <= wire_nl010ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iiO_dataout <= wire_nl010Oil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010iiOi_dataout <= wire_nl010ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iiOl_dataout <= wire_nl010llii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iiOO_dataout <= wire_nl010llil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010il_dataout <= nli1li1i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1ll0i; + wire_nl010il0i_dataout <= wire_nl010lllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010il0l_dataout <= wire_nl010llOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010il0O_dataout <= wire_nl010llOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010il1i_dataout <= wire_nl010lliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010il1l_dataout <= wire_nl010llli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010il1O_dataout <= wire_nl010llll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ili_dataout <= wire_nl010OiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl010ilii_dataout <= wire_nl010llOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ilil_dataout <= wire_nl010lO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iliO_dataout <= wire_nl010lO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ill_dataout <= wire_niOOO0O_w_lg_nl011lOi7598w(0) WHEN (wire_w_lg_niOO1llOO7572w(0) AND wire_w_lg_niOO1llOl7599w(0)) = '1' ELSE nl011lOi; + wire_nl010illi_dataout <= wire_nl010lO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010illl_dataout <= wire_nl010lO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010illO_dataout <= wire_nl010lO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ilOi_dataout <= wire_nl010lO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ilOl_dataout <= wire_nl010lOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010ilOO_dataout <= wire_nl010lOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iO_dataout <= nli1li1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1ll0O; + wire_nl010iO0i_dataout <= wire_nl010lOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iO0l_dataout <= wire_nl010lOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iO0O_dataout <= wire_nl010lOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iO1i_dataout <= wire_nl010lOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iO1l_dataout <= wire_nl010lOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iO1O_dataout <= wire_nl010lOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOi_dataout <= dl_data_upfc(0) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011O1i; + wire_nl010iOii_dataout <= wire_nl010O11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOil_dataout <= wire_nl010lOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOiO_dataout <= wire_nl010O11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOl_dataout <= dl_data_upfc(1) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011O1l; + wire_nl010iOli_dataout <= wire_nl010O10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOll_dataout <= wire_nl010O10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOlO_dataout <= wire_nl010O10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOO_dataout <= dl_data_upfc(2) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011O1O; + wire_nl010iOOi_dataout <= wire_nl010O1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOOl_dataout <= wire_nl010O1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010iOOO_dataout <= wire_nl010O00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010l00i_dataout <= wire_nilOiiOO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010011l; + wire_nl010l00l_dataout <= wire_nilOil1i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010011O; + wire_nl010l00O_dataout <= wire_nilOil1l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010010i; + wire_nl010l01i_dataout <= wire_nilOiilO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101OOl; + wire_nl010l01l_dataout <= wire_nilOiiOi_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101OOO; + wire_nl010l01O_dataout <= wire_nilOiiOl_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010011i; + wire_nl010l0i_dataout <= dl_data_upfc(6) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011Oii; + wire_nl010l0ii_dataout <= wire_nilOil1O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010010l; + wire_nl010l0il_dataout <= wire_nilOil0i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010010O; + wire_nl010l0iO_dataout <= wire_nilOil0l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001ii; + wire_nl010l0l_dataout <= dl_data_upfc(7) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011Oil; + wire_nl010l0li_dataout <= wire_nilOil0O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001il; + wire_nl010l0ll_dataout <= wire_nilOilii_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001iO; + wire_nl010l0lO_dataout <= wire_nilOilil_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001li; + wire_nl010l0O_dataout <= dl_data_upfc(8) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011OiO; + wire_nl010l0Oi_dataout <= wire_nilOiliO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001ll; + wire_nl010l0Ol_dataout <= wire_nilOilli_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001lO; + wire_nl010l0OO_dataout <= wire_nilOilll_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001Oi; + wire_nl010l10i_dataout <= wire_nilOi0OO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101O1l; + wire_nl010l10l_dataout <= wire_nilOii1i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101O1O; + wire_nl010l10O_dataout <= wire_nilOii1l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101O0i; + wire_nl010l11i_dataout <= wire_nilOi0lO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101lOl; + wire_nl010l11l_dataout <= wire_nilOi0Oi_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101lOO; + wire_nl010l11O_dataout <= wire_nilOi0Ol_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101O1i; + wire_nl010l1i_dataout <= dl_data_upfc(3) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011O0i; + wire_nl010l1ii_dataout <= wire_nilOii1O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101O0l; + wire_nl010l1il_dataout <= wire_nilOii0i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101O0O; + wire_nl010l1iO_dataout <= wire_nilOii0l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101Oii; + wire_nl010l1l_dataout <= dl_data_upfc(4) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011O0l; + wire_nl010l1li_dataout <= wire_nilOii0O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101Oil; + wire_nl010l1ll_dataout <= wire_nilOiiii_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101OiO; + wire_nl010l1lO_dataout <= wire_nilOiiil_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101Oli; + wire_nl010l1O_dataout <= dl_data_upfc(5) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011O0O; + wire_nl010l1Oi_dataout <= wire_nilOiiiO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101Oll; + wire_nl010l1Ol_dataout <= wire_nilOiili_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101OlO; + wire_nl010l1OO_dataout <= wire_nilOiill_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0101OOi; + wire_nl010li_dataout <= nli1li1O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1llil; + wire_nl010li0i_dataout <= wire_nilOilOO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010001l; + wire_nl010li0l_dataout <= wire_nilOiO1i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010001O; + wire_nl010li0O_dataout <= wire_nilOiO1l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010000i; + wire_nl010li1i_dataout <= wire_nilOillO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001Ol; + wire_nl010li1l_dataout <= wire_nilOilOi_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01001OO; + wire_nl010li1O_dataout <= wire_nilOilOl_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010001i; + wire_nl010lii_dataout <= dl_data_upfc(9) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011Oli; + wire_nl010liii_dataout <= wire_nilOiO1O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010000l; + wire_nl010liil_dataout <= wire_nilOiO0i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl010000O; + wire_nl010liiO_dataout <= wire_nilOiO0l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000ii; + wire_nl010lil_dataout <= dl_data_upfc(10) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011Oll; + wire_nl010lili_dataout <= wire_nilOiO0O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000il; + wire_nl010lill_dataout <= wire_nilOiOii_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000iO; + wire_nl010lilO_dataout <= wire_nilOiOil_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000li; + wire_nl010liO_dataout <= dl_data_upfc(11) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011OlO; + wire_nl010liOi_dataout <= wire_nilOiOiO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000ll; + wire_nl010liOl_dataout <= wire_nilOiOli_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000lO; + wire_nl010liOO_dataout <= wire_nilOiOll_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000Oi; + wire_nl010ll_dataout <= nli1li0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl010ll0i_dataout <= wire_nilOiOOO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100i1l; + wire_nl010ll0l_dataout <= wire_nilOl11i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100i1O; + wire_nl010ll0O_dataout <= wire_nilOl11l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100i0i; + wire_nl010ll1i_dataout <= wire_nilOiOlO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000Ol; + wire_nl010ll1l_dataout <= wire_nilOiOOi_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl01000OO; + wire_nl010ll1O_dataout <= wire_nilOiOOl_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100i1i; + wire_nl010lli_dataout <= dl_hdr_upfc(0) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011OOi; + wire_nl010llii_dataout <= wire_nilOl11O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100i0l; + wire_nl010llil_dataout <= wire_nilOl10i_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100i0O; + wire_nl010lliO_dataout <= wire_nilOl10l_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100iii; + wire_nl010lll_dataout <= dl_hdr_upfc(1) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011OOl; + wire_nl010llli_dataout <= wire_nilOl10O_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100iil; + wire_nl010llll_dataout <= wire_nilOl1ii_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100iiO; + wire_nl010lllO_dataout <= wire_nilOl1il_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100ili; + wire_nl010llO_dataout <= dl_hdr_upfc(2) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl011OOO; + wire_nl010llOi_dataout <= wire_nilOl1iO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100ill; + wire_nl010llOl_dataout <= wire_nilOl1li_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100ilO; + wire_nl010llOO_dataout <= wire_nilOl1ll_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100iOi; + wire_nl010lO_dataout <= nli1li0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl010lO0i_dataout <= wire_nilOl1OO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100l1l; + wire_nl010lO0l_dataout <= wire_nl010O1iO_dataout WHEN niOi01lOO = '1' ELSE nl0100l1O; + wire_nl010lO0O_dataout <= wire_nl010O1li_dataout WHEN niOi01lOO = '1' ELSE nl0100l0i; + wire_nl010lO1i_dataout <= wire_nilOl1lO_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100iOl; + wire_nl010lO1l_dataout <= wire_nilOl1Oi_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100iOO; + wire_nl010lO1O_dataout <= wire_nilOl1Ol_dataout WHEN wire_nilOi00l_dataout = '1' ELSE nl0100l1i; + wire_nl010lOi_dataout <= dl_hdr_upfc(3) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl01011i; + wire_nl010lOii_dataout <= wire_nl010O1ll_dataout WHEN niOi01lOO = '1' ELSE nl0100l0l; + wire_nl010lOil_dataout <= wire_nl010O1lO_dataout WHEN niOi01lOO = '1' ELSE nl0100l0O; + wire_nl010lOiO_dataout <= wire_nl010O1Oi_dataout WHEN niOi01lOO = '1' ELSE nl0100lii; + wire_nl010lOl_dataout <= dl_hdr_upfc(4) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl01011l; + wire_nl010lOli_dataout <= wire_nl010O1Ol_dataout WHEN niOi01lOO = '1' ELSE nl0100lil; + wire_nl010lOll_dataout <= wire_nl010O1OO_dataout WHEN niOi01lOO = '1' ELSE nl0100liO; + wire_nl010lOlO_dataout <= wire_nl010O01i_dataout WHEN niOi01lOO = '1' ELSE nl0100lli; + wire_nl010lOO_dataout <= dl_hdr_upfc(5) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl01011O; + wire_nl010lOOi_dataout <= wire_nl010O01l_dataout WHEN niOi01lOO = '1' ELSE nl0100lll; + wire_nl010lOOl_dataout <= niOi01OOl WHEN niOi01lOO = '1' ELSE nl0100lOl; + wire_nl010lOOO_dataout <= wire_nl01i1i1i_dataout WHEN niOi01lOO = '1' ELSE nl0100llO; + wire_nl010O00i_dataout <= wire_nl010O00l_dataout OR (niOi01lOO AND niOi01lOl); + wire_nl010O00l_dataout <= nl0100O0O AND NOT((wire_nilOi0iO_dataout AND wire_nilOi00l_dataout)); + wire_nl010O01i_dataout <= wire_nl01i10iO_dataout AND wire_nilOl1Ol_dataout; + wire_nl010O01l_dataout <= niOi01OlO AND wire_nilOl1Ol_dataout; + wire_nl010O0i_dataout <= dl_vcid_upfc(1) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl0101ii; + wire_nl010O0l_dataout <= dl_vcid_upfc(2) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl0101il; + wire_nl010O0O_dataout <= dl_typ_upfc(0) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl0101iO; + wire_nl010O10i_dataout <= niOi01llO WHEN niOi01lOO = '1' ELSE nl0100O1i; + wire_nl010O10l_dataout <= niOi01lOi WHEN niOi01lOO = '1' ELSE nl0100O1l; + wire_nl010O10O_dataout <= wire_nl010Oi1l_dataout WHEN niOi01lOO = '1' ELSE nl0100O1O; + wire_nl010O11i_dataout <= niOi0011l WHEN niOi01lOO = '1' ELSE nl0100lOi; + wire_nl010O11l_dataout <= ((wire_nilOl1Ol_dataout AND wire_nilOl1Oi_w_lg_dataout43272w(0)) AND niOi01liO) WHEN niOi01lOO = '1' ELSE nl0100lOO; + wire_nl010O11O_dataout <= (niOi01llO AND (niOi01lll OR wire_w_lg_niOi01lli54052w(0))) WHEN niOi01lOO = '1' ELSE nl011OOlO; + wire_nl010O11O_w_lg_dataout54062w(0) <= NOT wire_nl010O11O_dataout; + wire_nl010O1i_dataout <= dl_hdr_upfc(6) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl01010i; + wire_nl010O1ii_dataout <= wire_nl010Oi1O_dataout WHEN niOi01lOO = '1' ELSE nl0100O0i; + wire_nl010O1il_dataout <= wire_nl010Oi0i_dataout WHEN niOi01lOO = '1' ELSE nl0100O0l; + wire_nl010O1iO_dataout <= wire_nl01i101l_dataout AND wire_nilOl1Ol_dataout; + wire_nl010O1l_dataout <= dl_hdr_upfc(7) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl01010l; + wire_nl010O1li_dataout <= wire_nl01i101O_dataout AND wire_nilOl1Ol_dataout; + wire_nl010O1ll_dataout <= wire_nl01i100i_dataout AND wire_nilOl1Ol_dataout; + wire_nl010O1lO_dataout <= wire_nl01i100l_dataout AND wire_nilOl1Ol_dataout; + wire_nl010O1O_dataout <= dl_vcid_upfc(0) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl01010O; + wire_nl010O1Oi_dataout <= wire_nl01i100O_dataout AND wire_nilOl1Ol_dataout; + wire_nl010O1Ol_dataout <= wire_nl01i10ii_dataout AND wire_nilOl1Ol_dataout; + wire_nl010O1OO_dataout <= wire_nl01i10il_dataout AND wire_nilOl1Ol_dataout; + wire_nl010Oi_dataout <= nli1li0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl010Oi0i_dataout <= wire_nl010Oiii_dataout AND NOT(niOi01O1i); + wire_nl010Oi0i_w_lg_w_lg_dataout54122w54133w(0) <= wire_nl010Oi0i_w_lg_dataout54122w(0) AND wire_nl010Oi1O_dataout; + wire_nl010Oi0i_w_lg_dataout54142w(0) <= wire_nl010Oi0i_dataout AND wire_nl010Oi1O_w_lg_dataout54123w(0); + wire_nl010Oi0i_w_lg_dataout54122w(0) <= NOT wire_nl010Oi0i_dataout; + wire_nl010Oi0l_dataout <= nli1l001O WHEN niOi01O1l = '1' ELSE wire_nl010Oiil_dataout; + wire_nl010Oi0O_dataout <= nli1l1l0O WHEN niOi01O1l = '1' ELSE wire_nl010OiiO_dataout; + wire_nl010Oi1l_dataout <= wire_nl010Oi0l_dataout AND NOT(niOi01O1i); + wire_nl010Oi1l_w_lg_dataout54125w(0) <= NOT wire_nl010Oi1l_dataout; + wire_nl010Oi1O_dataout <= wire_nl010Oi0O_dataout AND NOT(niOi01O1i); + wire_nl010Oi1O_w_lg_dataout54123w(0) <= NOT wire_nl010Oi1O_dataout; + wire_nl010Oii_dataout <= dl_typ_upfc(1) WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl0101li; + wire_nl010Oiii_dataout <= nli1l1lii WHEN niOi01O1l = '1' ELSE wire_nl010Oili_dataout; + wire_nl010Oiil_dataout <= nli1l1lil WHEN niOi01O1O = '1' ELSE wire_nl010Oill_dataout; + wire_nl010OiiO_dataout <= nli1l1liO WHEN niOi01O1O = '1' ELSE wire_nl010OilO_dataout; + wire_nl010Oil_dataout <= dl_snd_upfc WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl0101ll; + wire_nl010Oili_dataout <= nli1l1lli WHEN niOi01O1O = '1' ELSE wire_nl010OiOi_dataout; + wire_nl010Oill_dataout <= nli1l1lll WHEN niOi01O0i = '1' ELSE wire_nl010OiOl_dataout; + wire_nl010OilO_dataout <= nli1l1llO WHEN niOi01O0i = '1' ELSE wire_nl010OiOO_dataout; + wire_nl010OiO_dataout <= dl_req_upfc WHEN wire_w_lg_niOO1llOO7572w(0) = '1' ELSE nl0101lO; + wire_nl010OiOi_dataout <= nli1l1lOi WHEN niOi01O0i = '1' ELSE wire_nl010Ol1i_dataout; + wire_nl010OiOl_dataout <= nli1l1lOl WHEN niOi01O0l = '1' ELSE wire_nl010Ol1l_dataout; + wire_nl010OiOO_dataout <= nli1l1lOO WHEN niOi01O0l = '1' ELSE wire_nl010Ol1O_dataout; + wire_nl010Ol_dataout <= nli1liii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl010Ol0i_dataout <= nli1l1O0i WHEN niOi01O0O = '1' ELSE wire_nl010Olii_dataout; + wire_nl010Ol0l_dataout <= nli1l1O0l WHEN niOi01Oii = '1' ELSE nli1l1Oil; + wire_nl010Ol0O_dataout <= nli1l1O0O WHEN niOi01Oii = '1' ELSE nli1l1OiO; + wire_nl010Ol1i_dataout <= nli1l1O1i WHEN niOi01O0l = '1' ELSE wire_nl010Ol0i_dataout; + wire_nl010Ol1l_dataout <= nli1l1O1l WHEN niOi01O0O = '1' ELSE wire_nl010Ol0l_dataout; + wire_nl010Ol1O_dataout <= nli1l1O1O WHEN niOi01O0O = '1' ELSE wire_nl010Ol0O_dataout; + wire_nl010Olii_dataout <= nli1l1Oii WHEN niOi01Oii = '1' ELSE nli1l1Oli; + wire_nl010OlO_dataout <= (nl01i10O XOR nl01i10i) AND NOT(wire_niO01l0O_dataout); + wire_nl010OO_dataout <= n1Ollll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl010OO0i_dataout <= wire_nl010OOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OO0l_dataout <= wire_nl010OOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OO0O_dataout <= wire_nl010OOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OO1i_dataout <= wire_nl01i111O_dataout OR wire_niO01O0O_dataout; + wire_nl010OO1l_dataout <= wire_nl010OOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OO1O_dataout <= wire_nl010OOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OOii_dataout <= wire_nl010OOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OOil_dataout <= wire_nl01i111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OOiO_dataout <= wire_nl01i111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl010OOli_dataout <= wire_nl01i110i_dataout OR niOi01OiO; + wire_nl010OOll_dataout <= wire_nl01i110l_dataout OR niOi01OiO; + wire_nl010OOlO_dataout <= wire_nl01i110O_dataout OR niOi01OiO; + wire_nl010OOOi_dataout <= wire_nl01i11ii_dataout OR niOi01OiO; + wire_nl010OOOl_dataout <= wire_nl01i11il_dataout OR niOi01OiO; + wire_nl010OOOO_dataout <= wire_nl01i11iO_dataout OR niOi01OiO; + wire_nl011000i_dataout <= wire_nl0110lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011000l_dataout <= wire_nl0110lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011000O_dataout <= wire_nl0110lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011001i_dataout <= wire_nl0110lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011001l_dataout <= wire_nl0110lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011001O_dataout <= wire_nl0110llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100i_dataout <= wire_nl011l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100ii_dataout <= wire_nl0110O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100il_dataout <= wire_nl0110O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100iO_dataout <= wire_nl0110O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100l_dataout <= wire_nl011l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100li_dataout <= wire_nl0110i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100ll_dataout <= wire_nl0110i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100lO_dataout <= wire_nl0110i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100O_dataout <= wire_nl011l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100Oi_dataout <= wire_nl0110iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100Ol_dataout <= wire_nl0110iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01100OO_dataout <= wire_nl0110iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011010i_dataout <= wire_nl1OOOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011010l_dataout <= wire_nl1OOOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011010O_dataout <= wire_nl1OOOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011011i_dataout <= wire_nl1OOOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011011l_dataout <= wire_nl1OOOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011011O_dataout <= wire_nl1OOOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101i_dataout <= wire_nl011iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101ii_dataout <= wire_nl1OOO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101il_dataout <= wire_nl1OOO0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101iO_dataout <= wire_nl1OOO0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101l_dataout <= wire_nl011iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101li_dataout <= wire_nl1OOO0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101ll_dataout <= wire_nl1OOO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101lO_dataout <= wire_nl1OOO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101O_dataout <= wire_nl011iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101Oi_dataout <= wire_nl1OOOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101Ol_dataout <= wire_nl1OOOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01101OO_dataout <= wire_nl1OOOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0110i_dataout <= n1Oi11i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0110i0i_dataout <= k_ptr0(0) WHEN niOi01i0i = '1' ELSE wire_nl0110iOi_dataout; + wire_nl0110i0l_dataout <= k_ptr0(1) WHEN niOi01i0i = '1' ELSE wire_nl0110iOl_dataout; + wire_nl0110i0O_dataout <= k_ptr0(2) WHEN niOi01i0i = '1' ELSE wire_nl0110iOO_dataout; + wire_nl0110i1i_dataout <= wire_nl0110ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0110i1l_dataout <= wire_nl0110ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0110i1O_dataout <= wire_nl0110ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0110ii_dataout <= nl011O1i WHEN niOO1llOi = '1' ELSE nl011l0l; + wire_nl0110iii_dataout <= k_ptr0(3) WHEN niOi01i0i = '1' ELSE wire_nl0110l1i_dataout; + wire_nl0110iil_dataout <= k_ptr0(4) WHEN niOi01i0i = '1' ELSE wire_nl0110l1l_dataout; + wire_nl0110iiO_dataout <= k_ptr0(5) WHEN niOi01i0i = '1' ELSE wire_nl0110l1O_dataout; + wire_nl0110il_dataout <= nl011O1l WHEN niOO1llOi = '1' ELSE nl1OOiOi; + wire_nl0110ili_dataout <= k_ptr0(6) WHEN niOi01i0i = '1' ELSE wire_nl0110l0i_dataout; + wire_nl0110ill_dataout <= k_ptr0(7) WHEN niOi01i0i = '1' ELSE wire_nl0110l0l_dataout; + wire_nl0110ilO_dataout <= k_ptr0(8) WHEN niOi01i0i = '1' ELSE wire_nl0110l0O_dataout; + wire_nl0110iO_dataout <= nl011O1O WHEN niOO1llOi = '1' ELSE nl1OOiOl; + wire_nl0110iOi_dataout <= wire_nl1OOOl1l_dataout WHEN niOi010OO = '1' ELSE nl0111O0i; + wire_nl0110iOl_dataout <= wire_nl1OOOl1O_dataout WHEN niOi010OO = '1' ELSE nl0111O0l; + wire_nl0110iOO_dataout <= wire_nl1OOOl0i_dataout WHEN niOi010OO = '1' ELSE nl0111O0O; + wire_nl0110l_dataout <= n1Oi11l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0110l0i_dataout <= wire_nl1OOOlil_dataout WHEN niOi010OO = '1' ELSE nl0111Oli; + wire_nl0110l0l_dataout <= wire_nl1OOOliO_dataout WHEN niOi010OO = '1' ELSE nl0111Oll; + wire_nl0110l0O_dataout <= wire_nl1OOOlli_dataout WHEN niOi010OO = '1' ELSE nl0111OlO; + wire_nl0110l1i_dataout <= wire_nl1OOOl0l_dataout WHEN niOi010OO = '1' ELSE nl0111Oii; + wire_nl0110l1l_dataout <= wire_nl1OOOl0O_dataout WHEN niOi010OO = '1' ELSE nl0111Oil; + wire_nl0110l1O_dataout <= wire_nl1OOOlii_dataout WHEN niOi010OO = '1' ELSE nl0111OiO; + wire_nl0110li_dataout <= nl011O0i WHEN niOO1llOi = '1' ELSE nl1OOiOO; + wire_nl0110ll_dataout <= nl011O0l WHEN niOO1llOi = '1' ELSE nl1OOl1i; + wire_nl0110lli_dataout <= k_ptr0(18) WHEN niOi01i1O = '1' ELSE wire_nl0110O0i_dataout; + wire_nl0110lll_dataout <= k_ptr0(19) WHEN niOi01i1O = '1' ELSE wire_nl0110O0l_dataout; + wire_nl0110llO_dataout <= k_ptr0(20) WHEN niOi01i1O = '1' ELSE wire_nl0110O0O_dataout; + wire_nl0110lO_dataout <= nl011O0O WHEN niOO1llOi = '1' ELSE nl1OOl1l; + wire_nl0110lOi_dataout <= k_ptr0(21) WHEN niOi01i1O = '1' ELSE wire_nl0110Oii_dataout; + wire_nl0110lOl_dataout <= k_ptr0(22) WHEN niOi01i1O = '1' ELSE wire_nl0110Oil_dataout; + wire_nl0110lOO_dataout <= k_ptr0(23) WHEN niOi01i1O = '1' ELSE wire_nl0110OiO_dataout; + wire_nl0110O_dataout <= n1O0O1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0110O0i_dataout <= wire_nl1OOOl1l_dataout WHEN niOi01i1i = '1' ELSE nl0111lli; + wire_nl0110O0l_dataout <= wire_nl1OOOl1O_dataout WHEN niOi01i1i = '1' ELSE nl0111lll; + wire_nl0110O0O_dataout <= wire_nl1OOOl0i_dataout WHEN niOi01i1i = '1' ELSE nl0111llO; + wire_nl0110O1i_dataout <= k_ptr0(24) WHEN niOi01i1O = '1' ELSE wire_nl0110Oli_dataout; + wire_nl0110O1l_dataout <= k_ptr0(25) WHEN niOi01i1O = '1' ELSE wire_nl0110Oll_dataout; + wire_nl0110O1O_dataout <= k_ptr0(26) WHEN niOi01i1O = '1' ELSE wire_nl0110OlO_dataout; + wire_nl0110Oi_dataout <= nl011Oii WHEN niOO1llOi = '1' ELSE nl1OOl1O; + wire_nl0110Oii_dataout <= wire_nl1OOOl0l_dataout WHEN niOi01i1i = '1' ELSE nl0111lOi; + wire_nl0110Oil_dataout <= wire_nl1OOOl0O_dataout WHEN niOi01i1i = '1' ELSE nl0111lOl; + wire_nl0110OiO_dataout <= wire_nl1OOOlii_dataout WHEN niOi01i1i = '1' ELSE nl0111lOO; + wire_nl0110Ol_dataout <= nl011Oil WHEN niOO1llOi = '1' ELSE nl1OOl0i; + wire_nl0110Oli_dataout <= wire_nl1OOOlil_dataout WHEN niOi01i1i = '1' ELSE nl0111O1i; + wire_nl0110Oll_dataout <= wire_nl1OOOliO_dataout WHEN niOi01i1i = '1' ELSE nl0111O1l; + wire_nl0110OlO_dataout <= wire_nl1OOOlli_dataout WHEN niOi01i1i = '1' ELSE nl0111O1O; + wire_nl0110OO_dataout <= nl011OiO WHEN niOO1llOi = '1' ELSE nl1OOl0l; + wire_nl011100i_dataout <= wire_nl0111i0i_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111iOi; + wire_nl011100l_dataout <= wire_nl0111i0l_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111iOl; + wire_nl011100O_dataout <= wire_nl0111i0O_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111iOO; + wire_nl011101i_dataout <= wire_nl0111i1i_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111ili; + wire_nl011101l_dataout <= wire_nl0111i1l_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111ill; + wire_nl011101O_dataout <= wire_nl0111i1O_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111ilO; + wire_nl01110i_dataout <= wire_nl011i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01110ii_dataout <= wire_nl01110iO_dataout OR niOi010lO; + wire_nl01110il_dataout <= niOi010ll OR niOi010lO; + wire_nl01110iO_dataout <= nl01ii1li AND NOT(niOi010ll); + wire_nl01110l_dataout <= wire_nl011i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01110O_dataout <= wire_nl011i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01110Oi_dataout <= nl0111lli WHEN niOi010Ol = '1' ELSE nl0111O0i; + wire_nl01110Ol_dataout <= nl0111lll WHEN niOi010Ol = '1' ELSE nl0111O0l; + wire_nl01110OO_dataout <= nl0111llO WHEN niOi010Ol = '1' ELSE nl0111O0O; + wire_nl011110i_dataout <= nl0111O0i WHEN wire_nl011Olil_dataout = '1' ELSE nl0111l1i; + wire_nl011110l_dataout <= nl0111O0l WHEN wire_nl011Olil_dataout = '1' ELSE nl0111l1l; + wire_nl011110O_dataout <= nl0111O0O WHEN wire_nl011Olil_dataout = '1' ELSE nl0111l1O; + wire_nl01111i_dataout <= wire_nl0110Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01111ii_dataout <= nl0111Oii WHEN wire_nl011Olil_dataout = '1' ELSE nl0111l0i; + wire_nl01111il_dataout <= nl0111Oil WHEN wire_nl011Olil_dataout = '1' ELSE nl0111l0l; + wire_nl01111iO_dataout <= nl0111OiO WHEN wire_nl011Olil_dataout = '1' ELSE nl0111l0O; + wire_nl01111l_dataout <= wire_nl0110Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01111li_dataout <= nl0111Oli WHEN wire_nl011Olil_dataout = '1' ELSE nl0111lii; + wire_nl01111ll_dataout <= nl0111Oll WHEN wire_nl011Olil_dataout = '1' ELSE nl0111lil; + wire_nl01111lO_dataout <= nl0111OlO WHEN wire_nl011Olil_dataout = '1' ELSE nl0111liO; + wire_nl01111O_dataout <= wire_nl0110OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01111Oi_dataout <= wire_nl01110Oi_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl1OOil1O; + wire_nl01111Ol_dataout <= wire_nl01110Ol_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111iil; + wire_nl01111OO_dataout <= wire_nl01110OO_dataout WHEN wire_nl011Olil_dataout = '1' ELSE nl0111iiO; + wire_nl0111i_dataout <= n1O0OOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0111i0i_dataout <= nl0111O1i WHEN niOi010Ol = '1' ELSE nl0111Oli; + wire_nl0111i0l_dataout <= nl0111O1l WHEN niOi010Ol = '1' ELSE nl0111Oll; + wire_nl0111i0O_dataout <= nl0111O1O WHEN niOi010Ol = '1' ELSE nl0111OlO; + wire_nl0111i1i_dataout <= nl0111lOi WHEN niOi010Ol = '1' ELSE nl0111Oii; + wire_nl0111i1l_dataout <= nl0111lOl WHEN niOi010Ol = '1' ELSE nl0111Oil; + wire_nl0111i1O_dataout <= nl0111lOO WHEN niOi010Ol = '1' ELSE nl0111OiO; + wire_nl0111ii_dataout <= wire_nl011i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111il_dataout <= wire_nl011i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111iO_dataout <= wire_nl011i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111l_dataout <= n1O0OOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0111li_dataout <= wire_nl011iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111ll_dataout <= wire_nl011iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111lO_dataout <= wire_nl011iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111O_dataout <= n1O0OOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl0111Oi_dataout <= wire_nl011ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111Ol_dataout <= wire_nl011ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111OO_dataout <= wire_nl011ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111OOi_dataout <= wire_nl1OOOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111OOl_dataout <= wire_nl1OOOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0111OOO_dataout <= wire_nl1OOOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011i00i_dataout <= wire_nl011i00l_dataout OR nl1OilO1i; + wire_nl011i00l_dataout <= wire_nlill0Oll_w_lg_nl1OillOl54176w(0) AND NOT(nl1OillOO); + wire_nl011i01i_dataout <= wire_nl011i00i_dataout OR nl1OilO1l; + wire_nl011i01l_dataout <= wire_nlill0Oll_w_lg_nl1OilO1i54178w(0) AND NOT(nl1OilO1l); + wire_nl011i01O_dataout <= wire_nlill0Oll_w_lg_nl1OillOO54177w(0) OR nl1OilO1i; + wire_nl011i0i_dataout <= nl011OOi WHEN niOO1llOi = '1' ELSE nl1OOliO; + wire_nl011i0l_dataout <= nl011OOl WHEN niOO1llOi = '1' ELSE nl1OOlli; + wire_nl011i0O_dataout <= nl011OOO WHEN niOO1llOi = '1' ELSE nl1OOlll; + wire_nl011i10O_dataout <= wire_nl011i1il_dataout AND NOT(nl1ll0iOO); + wire_nl011i1i_dataout <= nl011Oli WHEN niOO1llOi = '1' ELSE nl1OOl0O; + wire_nl011i1ii_dataout <= wire_nlill0Oll_w_lg_nl1ll0iOl54180w(0) AND NOT(nl1ll0iOO); + wire_nl011i1il_dataout <= wire_nlill0Oll_w_lg_nl1ll0iOi54179w(0) OR nl1ll0iOl; + wire_nl011i1iO_dataout <= wire_nl011i1lO_dataout AND NOT(nl1OilO0i); + wire_nl011i1l_dataout <= nl011Oll WHEN niOO1llOi = '1' ELSE nl1OOlii; + wire_nl011i1li_dataout <= wire_nl011i1Oi_dataout AND NOT(nl1OilO0i); + wire_nl011i1ll_dataout <= wire_nl011i1Ol_dataout AND NOT(nl1OilO0i); + wire_nl011i1lO_dataout <= wire_nl011i1OO_dataout OR nl1OilO1O; + wire_nl011i1O_dataout <= nl011OlO WHEN niOO1llOi = '1' ELSE nl1OOlil; + wire_nl011i1Oi_dataout <= wire_nl011i01i_dataout AND NOT(nl1OilO1O); + wire_nl011i1Ol_dataout <= wire_nl011i01l_dataout AND NOT(nl1OilO1O); + wire_nl011i1OO_dataout <= wire_nl011i01O_dataout AND NOT(nl1OilO1l); + wire_nl011ii_dataout <= n1O0O1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl011iii_dataout <= nl01011i WHEN niOO1llOi = '1' ELSE nl1OOllO; + wire_nl011iil_dataout <= nl01011l WHEN niOO1llOi = '1' ELSE nl1OOlOi; + wire_nl011iiO_dataout <= nl01011O WHEN niOO1llOi = '1' ELSE nl1OOlOl; + wire_nl011il_dataout <= n1O0O0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl011ili_dataout <= nl01010i WHEN niOO1llOi = '1' ELSE nl1OOlOO; + wire_nl011ill_dataout <= nl01010l WHEN niOO1llOi = '1' ELSE nl1OOO1i; + wire_nl011ilO_dataout <= nl01010O WHEN niOO1llOi = '1' ELSE nl1OOO1l; + wire_nl011iO_dataout <= n1O0O0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl011iO0i_dataout <= nli1l001O WHEN niOi01iiO = '1' ELSE wire_nl011iOii_dataout; + wire_nl011iO0l_dataout <= nli1l1l0O WHEN niOi01iiO = '1' ELSE wire_nl011iOil_dataout; + wire_nl011iO0O_dataout <= nli1l1lii WHEN niOi01iiO = '1' ELSE wire_nl011iOiO_dataout; + wire_nl011iO1i_dataout <= wire_nl011iO0i_dataout AND NOT(niOi01iil); + wire_nl011iO1i_w_lg_dataout54846w(0) <= NOT wire_nl011iO1i_dataout; + wire_nl011iO1l_dataout <= wire_nl011iO0l_dataout AND NOT(niOi01iil); + wire_nl011iO1l_w_lg_dataout54844w(0) <= NOT wire_nl011iO1l_dataout; + wire_nl011iO1O_dataout <= wire_nl011iO0O_dataout AND NOT(niOi01iil); + wire_nl011iO1O_w54848w(0) <= wire_nl011iO1O_w_lg_w_lg_w_lg_dataout54843w54845w54847w(0) AND nl0i1liii; + wire_nl011iO1O_w_lg_w_lg_w_lg_dataout54843w54845w54847w(0) <= wire_nl011iO1O_w_lg_w_lg_dataout54843w54845w(0) AND wire_nl011iO1i_w_lg_dataout54846w(0); + wire_nl011iO1O_w_lg_w_lg_dataout54843w54845w(0) <= wire_nl011iO1O_w_lg_dataout54843w(0) AND wire_nl011iO1l_w_lg_dataout54844w(0); + wire_nl011iO1O_w_lg_dataout54843w(0) <= NOT wire_nl011iO1O_dataout; + wire_nl011iOi_dataout <= nl0101ii WHEN niOO1llOi = '1' ELSE nl1OOO1O; + wire_nl011iOii_dataout <= nli1l1lil WHEN niOi01ili = '1' ELSE wire_nl011iOli_dataout; + wire_nl011iOil_dataout <= nli1l1liO WHEN niOi01ili = '1' ELSE wire_nl011iOll_dataout; + wire_nl011iOiO_dataout <= nli1l1lli WHEN niOi01ili = '1' ELSE wire_nl011iOlO_dataout; + wire_nl011iOl_dataout <= nl0101il WHEN niOO1llOi = '1' ELSE nl1OOO0i; + wire_nl011iOli_dataout <= nli1l1lll WHEN niOi01ill = '1' ELSE wire_nl011iOOi_dataout; + wire_nl011iOll_dataout <= nli1l1llO WHEN niOi01ill = '1' ELSE wire_nl011iOOl_dataout; + wire_nl011iOlO_dataout <= nli1l1lOi WHEN niOi01ill = '1' ELSE wire_nl011iOOO_dataout; + wire_nl011iOO_dataout <= nl0101iO WHEN niOO1llOi = '1' ELSE nl1OOO0l; + wire_nl011iOOi_dataout <= nli1l1lOl WHEN niOi01ilO = '1' ELSE wire_nl011l11i_dataout; + wire_nl011iOOl_dataout <= nli1l1lOO WHEN niOi01ilO = '1' ELSE wire_nl011l11l_dataout; + wire_nl011iOOO_dataout <= nli1l1O1i WHEN niOi01ilO = '1' ELSE wire_nl011l11O_dataout; + wire_nl011l0il_dataout <= nl011liOO AND wire_nilOll0l_dataout; + wire_nl011l0il_w_lg_dataout58915w(0) <= NOT wire_nl011l0il_dataout; + wire_nl011l10i_dataout <= nli1l1O0l WHEN niOi01iOl = '1' ELSE nli1l1Oil; + wire_nl011l10l_dataout <= nli1l1O0O WHEN niOi01iOl = '1' ELSE nli1l1OiO; + wire_nl011l10O_dataout <= nli1l1Oii WHEN niOi01iOl = '1' ELSE nli1l1Oli; + wire_nl011l11i_dataout <= nli1l1O1l WHEN niOi01iOi = '1' ELSE wire_nl011l10i_dataout; + wire_nl011l11l_dataout <= nli1l1O1O WHEN niOi01iOi = '1' ELSE wire_nl011l10l_dataout; + wire_nl011l11O_dataout <= nli1l1O0i WHEN niOi01iOi = '1' ELSE wire_nl011l10O_dataout; + wire_nl011l1i_dataout <= nl0101li WHEN niOO1llOi = '1' ELSE nl1OOO0O; + wire_nl011l1iO_dataout <= wire_nl011l1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011l1l_dataout <= nl0101ll WHEN niOO1llOi = '1' ELSE nl1OOOii; + wire_nl011l1li_dataout <= wire_nl011l1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011l1ll_dataout <= wire_nl011l1Oi_dataout OR niOi01iOO; + wire_nl011l1lO_dataout <= wire_nl011l1Ol_dataout OR niOi01iOO; + wire_nl011l1O_dataout <= nl0101lO WHEN niOO1llOi = '1' ELSE nl1OOOil; + wire_nl011l1Oi_dataout <= nl011ilOl AND NOT(niOii1l0l); + wire_nl011l1Ol_dataout <= nl011l1ii AND NOT(niOii1l0l); + wire_nl011li_dataout <= n1O0O0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl011lii_dataout <= nl011lli AND NOT(wire_niO01l0O_dataout); + wire_nl011liO_dataout <= nl1OOOiO AND NOT(wire_niO01l0O_dataout); + wire_nl011ll_dataout <= n1O0Oii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl011ll0l_dataout <= wire_nl011O11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011ll0O_dataout <= wire_nl011O11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011llii_dataout <= wire_nl011O11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011llil_dataout <= wire_nl011O10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lliO_dataout <= wire_nl011O10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lll_dataout <= nl011lOi AND NOT(wire_niO01O0O_dataout); + wire_nl011llli_dataout <= wire_nl011O10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011llll_dataout <= wire_nl011O1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lllO_dataout <= wire_nl011O1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011llOi_dataout <= wire_nl011O1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011llOl_dataout <= wire_nl011O1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011llOO_dataout <= wire_nl011O1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lO_dataout <= n1O0Oil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl011lO0i_dataout <= wire_nl011O1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lO0l_dataout <= wire_nl011O01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lO0O_dataout <= wire_nl011O01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lO1i_dataout <= wire_nl011O1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lO1l_dataout <= wire_nl011O1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lO1O_dataout <= wire_nl011O1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOii_dataout <= wire_nl011O01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOil_dataout <= wire_nl011O00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOiO_dataout <= wire_nl011O00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOl_dataout <= nl011llO AND NOT(wire_niO01O0O_dataout); + wire_nl011lOli_dataout <= wire_nl011O00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOll_dataout <= wire_nl011O0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOlO_dataout <= wire_nl011O0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOO_dataout <= nl011lil AND NOT(wire_niO01O0O_dataout); + wire_nl011lOOi_dataout <= wire_nl011O0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOOl_dataout <= wire_nl011O0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011lOOO_dataout <= wire_nl011O0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011O00i_dataout <= wire_nl10ll0il_dataout WHEN niOi01l0i = '1' ELSE nl011lill; + wire_nl011O00l_dataout <= wire_nl10ll0iO_dataout WHEN niOi01l0i = '1' ELSE nl011lilO; + wire_nl011O00O_dataout <= wire_nl10lli0i_dataout WHEN niOi01l0i = '1' ELSE nl011liOi; + wire_nl011O01i_dataout <= wire_nl10ll00l_dataout WHEN niOi01l0i = '1' ELSE nl011liil; + wire_nl011O01l_dataout <= wire_nl10ll00O_dataout WHEN niOi01l0i = '1' ELSE nl011liiO; + wire_nl011O01O_dataout <= wire_nl10ll0ii_dataout WHEN niOi01l0i = '1' ELSE nl011lili; + wire_nl011O0ii_dataout <= wire_nl10lli1O_dataout WHEN niOi01l0i = '1' ELSE nl011liOl; + wire_nl011O0il_dataout <= wire_nl011O0iO_dataout OR niOi01l0i; + wire_nl011O0iO_dataout <= nl011liOO AND NOT(wire_nlill0Oll_w_lg_w_lg_nl011ll1l54087w54088w(0)); + wire_nl011O0ll_dataout <= wire_nlill0Oll_w_lg_nl10lliOO54079w(0) WHEN niOi01l0i = '1' ELSE wire_nl011O0Ol_dataout; + wire_nl011O0lO_dataout <= nl10lliOO WHEN niOi01l0i = '1' ELSE wire_nl011O0OO_dataout; + wire_nl011O0Oi_dataout <= wire_nl011Oi1i_dataout OR niOi01l0i; + wire_nl011O0Ol_dataout <= nl011ll1i AND NOT(niOi01l1O); + wire_nl011O0OO_dataout <= nl011ll1l AND NOT(niOi01l1O); + wire_nl011O10i_dataout <= wire_nl10liOll_dataout WHEN niOi01l0i = '1' ELSE nl011l0ll; + wire_nl011O10l_dataout <= wire_nl10liOlO_dataout WHEN niOi01l0i = '1' ELSE nl011l0lO; + wire_nl011O10O_dataout <= wire_nl10liOOi_dataout WHEN niOi01l0i = '1' ELSE nl011l0Oi; + wire_nl011O11i_dataout <= wire_nl10liOil_dataout WHEN niOi01l0i = '1' ELSE nl011l1il; + wire_nl011O11l_dataout <= wire_nl10liOiO_dataout WHEN niOi01l0i = '1' ELSE nl011l0iO; + wire_nl011O11O_dataout <= wire_nl10liOli_dataout WHEN niOi01l0i = '1' ELSE nl011l0li; + wire_nl011O1ii_dataout <= wire_nl10liOOl_dataout WHEN niOi01l0i = '1' ELSE nl011l0Ol; + wire_nl011O1il_dataout <= wire_nl10liOOO_dataout WHEN niOi01l0i = '1' ELSE nl011l0OO; + wire_nl011O1iO_dataout <= wire_nl10ll11i_dataout WHEN niOi01l0i = '1' ELSE nl011li1i; + wire_nl011O1li_dataout <= wire_nl10ll11l_dataout WHEN niOi01l0i = '1' ELSE nl011li1l; + wire_nl011O1ll_dataout <= wire_nl10ll11O_dataout WHEN niOi01l0i = '1' ELSE nl011li1O; + wire_nl011O1lO_dataout <= wire_nl10ll10i_dataout WHEN niOi01l0i = '1' ELSE nl011li0i; + wire_nl011O1Oi_dataout <= wire_nl10ll01l_dataout WHEN niOi01l0i = '1' ELSE nl011li0l; + wire_nl011O1Ol_dataout <= wire_nl10ll01O_dataout WHEN niOi01l0i = '1' ELSE nl011li0O; + wire_nl011O1OO_dataout <= wire_nl10ll00i_dataout WHEN niOi01l0i = '1' ELSE nl011liii; + wire_nl011Oi_dataout <= n1O0OiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl011Oi1i_dataout <= nl011ll1O AND NOT(niOi01l1O); + wire_nl011OiiO_dataout <= nl10lliil AND wire_nlill0Oll_w_lg_nl10lliOO54079w(0); + wire_nl011OilO_dataout <= nl0100O1i AND wire_nl011OiOi_dataout; + wire_nl011OiOi_dataout <= wire_nilOi00l_dataout AND (wire_nilOi00i_w_lg_dataout54077w(0) AND wire_w_lg_niOiO110i42934w(0)); + wire_nl011Ol_dataout <= nli1liil WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1ll1i; + wire_nl011Ol0i_dataout <= nl0100O1l AND niOi01l0l; + wire_nl011Ol0l_dataout <= nl0100O1i AND (wire_nl011OO1i_w_lg_dataout54065w(0) AND (wire_nilOi00l_dataout AND nl011ll0i)); + wire_nl011Ol0l_w_lg_dataout55199w(0) <= wire_nl011Ol0l_dataout AND wire_w_lg_niOi1OliO55198w(0); + wire_nl011Ol1i_dataout <= nl0100O1i AND (wire_nilOi00l_dataout AND wire_nilOi00i_dataout); + wire_nl011Ol1l_dataout <= nl0100O1i AND (wire_nlill0Oll_w_lg_nl011OOlO54073w(0) AND (wire_nl011OlOO_w_lg_dataout8890w(0) AND ((wire_nilOi00l_dataout AND wire_nilOi00i_dataout) AND wire_w_lg_niOiO110i42934w(0)))); + wire_nl011Ol1l_w_lg_w_lg_dataout54516w54517w(0) <= wire_nl011Ol1l_w_lg_dataout54516w(0) AND niOi011OO; + wire_nl011Ol1l_w_lg_dataout54829w(0) <= wire_nl011Ol1l_dataout AND wire_nlill0Oll_w_lg_nl1OOi01l54523w(0); + wire_nl011Ol1l_w_lg_dataout54183w(0) <= wire_nl011Ol1l_dataout AND niOi01i1l; + wire_nl011Ol1l_w_lg_dataout54516w(0) <= NOT wire_nl011Ol1l_dataout; + wire_nl011Ol1O_dataout <= nl0100O1i AND niOi01l0l; + wire_nl011Ol1O_w_lg_dataout54215w(0) <= wire_nl011Ol1O_dataout AND niOi010il; + wire_nl011Ol1O_w_lg_dataout8960w(0) <= NOT wire_nl011Ol1O_dataout; + wire_nl011Olil_dataout <= nl0100O1i AND (wire_nilOi00l_dataout AND nl011OO1l); + wire_nl011OlOO_dataout <= wire_nilOi00O_dataout OR wire_niO1110l_w_lg_dataout44125w(0); + wire_nl011OlOO_w_lg_dataout8890w(0) <= NOT wire_nl011OlOO_dataout; + wire_nl011OO_dataout <= nli1liiO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli1ll1O; + wire_nl011OO0i_dataout <= wire_nilOi0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011OO0l_dataout <= wire_nilOi0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl011OO0O_dataout <= (wire_nl010O11O_w_lg_dataout54062w(0) AND ((wire_nilOi0ll_w_lg_dataout54064w(0) AND wire_nl011OO1i_w_lg_dataout54065w(0)) AND wire_w_lg_niOi001li54067w(0))) AND NOT(wire_niO01O0O_dataout); + wire_nl011OO1i_dataout <= niOiO110i AND NOT(wire_nilOi0li_dataout); + wire_nl011OO1i_w_lg_dataout54065w(0) <= NOT wire_nl011OO1i_dataout; + wire_nl011OOOi_dataout <= wire_nilOilOl_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nl01000ll; + wire_nl011OOOl_dataout <= wire_nilOilOO_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nl01000lO; + wire_nl011OOOO_dataout <= wire_nilOl1ll_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nl0100i1l; + wire_nl01i00l_dataout <= (nl01i0Ol XOR nl01i0lO) AND NOT(wire_niO01l0O_dataout); + wire_nl01i01l_dataout <= nl01i1li WHEN niOO1lO1i = '1' ELSE wire_nlOi1Oi0l_dataout; + wire_nl01i0i_dataout <= n1OllOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01i0iO_dataout <= nl01i0lO AND NOT(wire_niO01O0O_dataout); + wire_nl01i0l_dataout <= n1OlO1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01i0ll_dataout <= nl01i00i AND NOT(wire_niO01O0O_dataout); + wire_nl01i0O_dataout <= n1OlO1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01i0Oi_dataout <= nl01i0OO AND NOT(wire_niO01l0O_dataout); + wire_nl01i100i_dataout <= wire_nl01i10li_o(2) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiO1O_dataout; + wire_nl01i100l_dataout <= wire_nl01i10li_o(3) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiO0i_dataout; + wire_nl01i100O_dataout <= wire_nl01i10li_o(4) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiO0l_dataout; + wire_nl01i101l_dataout <= wire_nl01i10li_o(0) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiO1i_dataout; + wire_nl01i101O_dataout <= wire_nl01i10li_o(1) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiO1l_dataout; + wire_nl01i10ii_dataout <= wire_nl01i10li_o(5) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiO0O_dataout; + wire_nl01i10il_dataout <= wire_nl01i10li_o(6) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiOii_dataout; + wire_nl01i10iO_dataout <= wire_nl01i10li_o(7) WHEN wire_w_lg_niOi01Oll54001w(0) = '1' ELSE wire_nilOiOil_dataout; + wire_nl01i10l_dataout <= nl01i1ii AND NOT(wire_niO01l0O_dataout); + wire_nl01i110i_dataout <= nl010Olil WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(1); + wire_nl01i110l_dataout <= nl010OliO WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(2); + wire_nl01i110O_dataout <= nl010Olli WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(3); + wire_nl01i111i_dataout <= wire_nl01i11li_dataout OR niOi01OiO; + wire_nl01i111l_dataout <= wire_nl01i11ll_dataout OR niOi01OiO; + wire_nl01i111O_dataout <= wire_nl01i11lO_dataout AND NOT(niOi01OiO); + wire_nl01i11i_dataout <= nl01i10i AND NOT(wire_niO01O0O_dataout); + wire_nl01i11ii_dataout <= nl010Olll WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(4); + wire_nl01i11il_dataout <= nl010OllO WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(5); + wire_nl01i11iO_dataout <= nl010OlOi WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(6); + wire_nl01i11li_dataout <= nl010OlOl WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(7); + wire_nl01i11ll_dataout <= nl010OlOO WHEN niOi01Oil = '1' ELSE wire_nl01i11Oi_o(8); + wire_nl01i11lO_dataout <= nl010Oi1i OR niOi01Oil; + wire_nl01i11O_dataout <= nl010Oll AND NOT(wire_niO01O0O_dataout); + wire_nl01i1i_dataout <= n1OlllO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01i1i1i_dataout <= (NOT ((wire_nilOl1Ol_dataout AND niOi0011i) OR wire_nilOl1Oi_w_lg_dataout53937w(0))) AND NOT(niOi0011l); + wire_nl01i1il_dataout <= nl01i10O AND NOT(wire_niO01l0O_dataout); + wire_nl01i1iO_dataout <= nl01i11l AND NOT(wire_niO01l0O_dataout); + wire_nl01i1l_dataout <= n1OllOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01i1ll_dataout <= wire_nl01i1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01i1lO_dataout <= wire_nl01i01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01i1O_dataout <= n1OllOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01i1Oi_dataout <= wire_nl1000i_w_lg_nl01i1ii7565w(0) WHEN (wire_nlOi1Oi0l_dataout AND (wire_w_lg_niOO1lO1i7566w(0) AND (wire_nlOi1Oi0l_dataout XOR nl01i1li))) = '1' ELSE nl01i1ii; + wire_nl01ii00i_dataout <= wire_nl01iiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii00l_dataout <= wire_nl01iiiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii00O_dataout <= wire_nl01iil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii01i_dataout <= wire_nl01iiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii01l_dataout <= wire_nl01iiilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii01O_dataout <= wire_nl01iiiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0i_dataout <= wire_nl01ii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0ii_dataout <= wire_nl01iil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0il_dataout <= wire_nl01iil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0iO_dataout <= wire_nl01iil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0l_dataout <= wire_nl01iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0li_dataout <= wire_nl01iil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0ll_dataout <= wire_nl01iil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0lO_dataout <= wire_nli1ll0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0O_dataout <= wire_nl1000i_w_lg_nl01i0OO7558w(0) WHEN (wire_nlOi1Oiii_dataout AND (wire_w_lg_niOO1lO1l7559w(0) AND (wire_nlOi1Oiii_dataout XOR nl01ii1O))) = '1' ELSE nl01i0OO; + wire_nl01ii0Oi_dataout <= wire_nli1lli1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0Ol_dataout <= wire_nli1lli1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii0OO_dataout <= wire_nli1lli1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ii1i_dataout <= nl01i0Ol AND NOT(wire_niO01l0O_dataout); + wire_nl01ii1l_dataout <= nl01i0li AND NOT(wire_niO01l0O_dataout); + wire_nl01iii_dataout <= n1OlO1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01iii0i_dataout <= wire_nli1lliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iii0l_dataout <= wire_nl01iilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iii0O_dataout <= wire_nl01iilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iii1i_dataout <= wire_nli1lli0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iii1l_dataout <= wire_nli1lli0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iii1O_dataout <= wire_nli1lli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iiiii_dataout <= wire_nl01iiliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iiiil_dataout <= wire_nl01iilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iiiiO_dataout <= wire_nl01iiOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iiili_dataout <= wire_nl01il1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iiill_dataout <= wire_nilOiOOO_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iilll_dataout; + wire_nl01iiilO_dataout <= wire_nilOl11i_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iillO_dataout; + wire_nl01iiiOi_dataout <= wire_nilOl11l_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iilOi_dataout; + wire_nl01iiiOl_dataout <= wire_nilOiOii_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iilOl_dataout; + wire_nl01iiiOO_dataout <= wire_nilOiOil_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iilOO_dataout; + wire_nl01iil_dataout <= nli01i1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01iil0i_dataout <= wire_nilOiOlO_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiO0i_dataout; + wire_nl01iil0l_dataout <= wire_nilOiOOi_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiO0l_dataout; + wire_nl01iil0O_dataout <= wire_nilOiOOl_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiO0O_dataout; + wire_nl01iil1i_dataout <= wire_nilOiOiO_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiO1i_dataout; + wire_nl01iil1l_dataout <= wire_nilOiOli_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiO1l_dataout; + wire_nl01iil1O_dataout <= wire_nilOiOll_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiO1O_dataout; + wire_nl01iili_dataout <= nl01ii1O WHEN niOO1lO1l = '1' ELSE wire_nlOi1Oiii_dataout; + wire_nl01iilii_dataout <= (wire_nl01lli1l_dataout OR wire_nl01iO00i_dataout) WHEN niOi00OOi = '1' ELSE wire_nl01iiOii_dataout; + wire_nl01iilil_dataout <= wire_nl01iOi0i_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiOil_dataout; + wire_nl01iiliO_dataout <= ((wire_nl1000i_w_lg_w_lg_niOOi01il42910w53644w(0) AND wire_w_lg_w_lg_niOi0010i53645w53646w(0)) AND niOi0lOOl) WHEN niOi00OOi = '1' ELSE wire_nl01iiOiO_dataout; + wire_nl01iilli_dataout <= wire_nl01iOi1i_dataout WHEN niOi00OOi = '1' ELSE wire_nl01iiOli_dataout; + wire_nl01iilll_dataout <= nl01i0O1i AND NOT(niOi00l0O); + wire_nl01iillO_dataout <= nl01i0O0O AND NOT(niOi00l0O); + wire_nl01iilOi_dataout <= nl01i0Oii AND NOT(niOi00l0O); + wire_nl01iilOl_dataout <= nl01i0Oil AND NOT(niOi00l0O); + wire_nl01iilOO_dataout <= nl01i0OiO AND NOT(niOi00l0O); + wire_nl01iiO_dataout <= nli01i1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01iiO0i_dataout <= nl01i0OOi AND NOT(niOi00l0O); + wire_nl01iiO0l_dataout <= nl01i0OOl AND NOT(niOi00l0O); + wire_nl01iiO0O_dataout <= nl01i0OOO AND NOT(niOi00l0O); + wire_nl01iiO1i_dataout <= nl01i0Oli AND NOT(niOi00l0O); + wire_nl01iiO1l_dataout <= nl01i0Oll AND NOT(niOi00l0O); + wire_nl01iiO1O_dataout <= nl01i0OlO AND NOT(niOi00l0O); + wire_nl01iiOii_dataout <= nl01ii1iO AND NOT(niOi00l0O); + wire_nl01iiOil_dataout <= nl01ii1li AND NOT(niOi00l0O); + wire_nl01iiOiO_dataout <= nl01ii1ll AND NOT(niOi00l0O); + wire_nl01iiOli_dataout <= nl01ii1lO AND NOT(niOi00l0O); + wire_nl01iiOOO_dataout <= (((((wire_w_lg_niOi00Oil53600w(0) AND (wire_w_lg_niOi00O0l53601w(0) AND wire_w_lg_niOi00O0i53602w(0))) AND wire_w_lg_niOi0lOli53605w(0)) AND wire_w_lg_niOi00O0O53607w(0)) AND wire_w_lg_niOi00Oii53609w(0)) OR ((wire_nilOl1Ol_w_lg_w_lg_dataout43262w53611w(0) AND wire_w_lg_niOi0010l53612w(0)) OR (wire_nilOl1Oi_w_lg_w_lg_dataout53615w53616w(0) OR ((wire_w_lg_w_lg_niOi00Oii53617w53618w(0) AND wire_nilOl1Oi_w_lg_dataout53622w(0)) OR wire_nilOl1Oi_w_lg_w_lg_w53632w53637w53638w(0))))) WHEN niOi0lOiO = '1' ELSE wire_nl01il11i_dataout; + wire_nl01il00l_dataout <= niOi001lO AND NOT(niOi001ll); + wire_nl01il00O_dataout <= wire_nl01il0li_dataout AND NOT(niOi001ll); + wire_nl01il0i_dataout <= wire_nl01il0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01il0ii_dataout <= wire_nl01il0ll_dataout AND NOT(niOi001ll); + wire_nl01il0il_dataout <= wire_nl01il0lO_dataout AND NOT(niOi001ll); + wire_nl01il0iO_dataout <= wire_nl01il0Oi_dataout AND NOT(niOi001ll); + wire_nl01il0l_dataout <= wire_nl01ilii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01il0li_dataout <= niOi001Oi AND NOT(niOi001lO); + wire_nl01il0ll_dataout <= wire_nl01il0Ol_dataout AND NOT(niOi001lO); + wire_nl01il0lO_dataout <= wire_nl01il0OO_dataout AND NOT(niOi001lO); + wire_nl01il0O_dataout <= wire_nl01ilil_dataout WHEN nl01iiOi = '1' ELSE nl01illl; + wire_nl01il0Oi_dataout <= wire_nl01ili1i_dataout AND NOT(niOi001lO); + wire_nl01il0Ol_dataout <= niOi001Ol AND NOT(niOi001Oi); + wire_nl01il0OO_dataout <= wire_nl01ili1l_dataout AND NOT(niOi001Oi); + wire_nl01il11i_dataout <= (wire_nl01lli1O_dataout OR (nl0100O0O OR (wire_w_lg_niOilllOi53566w(0) OR (wire_nlill0Oll_w_lg_w_lg_nl01l0l0l53569w53570w(0) OR wire_nlill0Oll_w_lg_w_lg_w_lg_nl01l0llO53572w53594w53595w(0))))) WHEN niOi00OOi = '1' ELSE wire_nl01il11l_dataout; + wire_nl01il11l_dataout <= nl01ii1Oi AND NOT(niOi00l0O); + wire_nl01il1Oi_dataout <= wire_nl01il1Ol_dataout OR niOi001li; + wire_nl01il1Ol_dataout <= nl01ii1Ol AND NOT(niOi00l0O); + wire_nl01ili_dataout <= nli01i0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01ili1i_dataout <= wire_nl01ili1O_dataout AND NOT(niOi001Oi); + wire_nl01ili1l_dataout <= niOi001OO AND NOT(niOi001Ol); + wire_nl01ili1O_dataout <= wire_w_lg_niOi001OO53534w(0) AND NOT(niOi001Ol); + wire_nl01ilii_dataout <= wire_nl01iliO_dataout WHEN nl01iiOi = '1' ELSE nl01il1l; + wire_nl01ilil_dataout <= wire_nl01illi_o(0) AND NOT(niOO1lO1O); + wire_nl01iliO_dataout <= wire_nl01illi_o(1) AND NOT(niOO1lO1O); + wire_nl01ill_dataout <= nli01i0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01ilO_dataout <= nli01i0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01ilOl_dataout <= wire_nl01iOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01ilOO_dataout <= wire_nl01iO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iO00i_dataout <= wire_nl1000i_w_lg_niOOi01il42910w(0) AND ((wire_nlill0Oll_w_lg_w_lg_nl01l0liO53445w53446w(0) OR wire_nlill0Oll_w_lg_w_lg_nl01l0liO53449w53450w(0)) OR (wire_nlill0Oll_w_lg_nl01l0liO53452w(0) AND (wire_w_lg_niOi0lOOl53453w(0) AND wire_w_lg_niOi000li53454w(0)))); + wire_nl01iO0i_dataout <= wire_nl01iO0O_o(0) AND NOT(niOO1lO0i); + wire_nl01iO0l_dataout <= wire_nl01iO0O_o(1) AND NOT(niOO1lO0i); + wire_nl01iO1i_dataout <= wire_nl01iO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01iO1l_dataout <= wire_nl01iO0i_dataout WHEN niOO1Oi1l = '1' ELSE nl01illO; + wire_nl01iO1O_dataout <= wire_nl01iO0l_dataout WHEN niOO1Oi1l = '1' ELSE nl01ilOi; + wire_nl01iOi_dataout <= nli01iii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01iOi0i_dataout <= (wire_nlill0Oll_w_lg_w_lg_nl01l0lll53411w53412w(0) OR (wire_nlill0Oll_w_lg_nl01l0lii53389w(0) AND (nl01l0lOi AND niOi000lO))) WHEN niOi0lOOl = '1' ELSE wire_nl01iOi0l_dataout; + wire_nl01iOi0l_dataout <= (((((((nl01l0lll AND niOi000ll) OR niOi00iOi) OR niOi00ill) OR niOi00iiO) OR niOi00iii) OR niOi00i0l) OR niOi00i1O) WHEN niOi000li = '1' ELSE wire_nl01iOi0O_dataout; + wire_nl01iOi0O_dataout <= (((((niOi00iOi OR niOi00ill) OR wire_w_lg_niOi00iiO53395w(0)) OR wire_w_lg_niOi00iii53398w(0)) OR wire_w_lg_niOi00i0l53401w(0)) OR niOi00i1O) WHEN niOi0lOlO = '1' ELSE (niOi000Oi OR (wire_nlill0Oll_w_lg_nl01l0lii53389w(0) AND (nl01l0lOi AND niOi000lO))); + wire_nl01iOi1i_dataout <= ((nl01l0lil OR (wire_nlill0Oll_w_lg_nl01l0llO53439w(0) OR wire_nilO010i_w_lg_w_lg_dataout25163w53440w(0))) OR niOi00l1O) WHEN niOi0lOOl = '1' ELSE wire_nl01iOi1l_dataout; + wire_nl01iOi1l_dataout <= niOi00iOO WHEN niOi000li = '1' ELSE wire_nl01iOi1O_dataout; + wire_nl01iOi1O_dataout <= niOi00iOO WHEN niOi0lOlO = '1' ELSE (((wire_nlill0Oll_w53422w(0) OR (wire_nl1000i_w_lg_niOOi01il42910w(0) AND wire_w_lg_niOi00l1l53424w(0))) OR (wire_nl1000i_w_lg_niOOi01il42910w(0) AND wire_w_lg_niOi00l1i53429w(0))) OR niOi00l0i); + wire_nl01iOii_dataout <= nl01il1O OR niOO1Oi1l; + wire_nl01iOl_dataout <= nli01iil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01iOO_dataout <= nli01iiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01l010i_dataout <= wire_nilOii0i_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiO0O_dataout; + wire_nl01l010l_dataout <= wire_nilOii0l_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiOii_dataout; + wire_nl01l010O_dataout <= wire_nilOii0O_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiOil_dataout; + wire_nl01l011i_dataout <= wire_nilOii1i_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiO1O_dataout; + wire_nl01l011l_dataout <= wire_nilOii1l_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiO0i_dataout; + wire_nl01l011O_dataout <= wire_nilOii1O_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiO0l_dataout; + wire_nl01l01ii_dataout <= wire_nilOiiii_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiOiO_dataout; + wire_nl01l01il_dataout <= wire_nilOiiil_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiOli_dataout; + wire_nl01l01iO_dataout <= wire_nilOiiiO_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiOll_dataout; + wire_nl01l01iO_w_lg_dataout53565w(0) <= wire_nl01l01iO_dataout XOR wire_nl01l1lii_w_o_range53564w(0); + wire_nl01l0i_dataout <= nl00li0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01l0l_dataout <= nl00li0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01l0O_dataout <= nl00li0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01l0O0l_dataout <= wire_nl01ll1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0O0O_dataout <= wire_nl01liiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0Oii_dataout <= wire_nl01liiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0Oil_dataout <= wire_nl01liiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0OiO_dataout <= wire_nl01lil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0Oli_dataout <= wire_nl01lil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0Oll_dataout <= wire_nl01lil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0OlO_dataout <= wire_nl01lil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0OOi_dataout <= wire_nl01lil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0OOl_dataout <= wire_nl01lil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l0OOO_dataout <= wire_nl01lilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l1i_dataout <= nl00Ol1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01l1l_dataout <= nl00li1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01l1liO_dataout <= wire_nl01l1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01l1lli_dataout <= wire_nl01l1lll_dataout OR (wire_w_lg_niOi00lii53229w(0) AND niOi0lOiO); + wire_nl01l1lll_dataout <= nl01ii1OO AND NOT(niOi00l0O); + wire_nl01l1O_dataout <= nl00li1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01l1OOl_dataout <= wire_nilOi0Ol_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiO1i_dataout; + wire_nl01l1OOl_w_lg_w_lg_dataout53587w53588w(0) <= wire_nl01l1OOl_w_lg_dataout53587w(0) AND wire_w_lg_niOi0001l53584w(0); + wire_nl01l1OOl_w_lg_dataout53587w(0) <= wire_nl01l1OOl_dataout AND niOi001ii; + wire_nl01l1OOO_dataout <= wire_nilOi0OO_dataout WHEN nl01l0O1O = '1' ELSE wire_nilOiO1l_dataout; + wire_nl01li00i_dataout <= wire_nl01liOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li00l_dataout <= wire_nl01liOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li00O_dataout <= wire_nl01liOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li01i_dataout <= wire_nl01liOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li01l_dataout <= wire_nl01liOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li01O_dataout <= wire_nl01liOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0ii_dataout <= wire_nl01liOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0il_dataout <= wire_nl01liOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0iO_dataout <= wire_nl01ll11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0li_dataout <= wire_nl01ll11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0ll_dataout <= wire_nl01ll11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0lO_dataout <= wire_nl01ll10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0Oi_dataout <= wire_nl01ll10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0Ol_dataout <= wire_nl01ll10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li0OO_dataout <= wire_nl01ll1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li10i_dataout <= wire_nl01lilll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li10l_dataout <= wire_nl01lillO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li10O_dataout <= wire_nl01lilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li11i_dataout <= wire_nl01lilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li11l_dataout <= wire_nl01liliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li11O_dataout <= wire_nl01lilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1ii_dataout <= wire_nl01lilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1il_dataout <= wire_nl01lilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1iO_dataout <= wire_nl01liO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1li_dataout <= wire_nl01liO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1ll_dataout <= wire_nl01liO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1lO_dataout <= wire_nl01liO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1Oi_dataout <= wire_nl01liO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1Ol_dataout <= wire_nl01liO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01li1OO_dataout <= wire_nl01liOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01lii_dataout <= nl00liii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01lii0i_dataout <= wire_nl01ll1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01lii0l_dataout <= wire_nl01ll1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01lii0O_dataout <= wire_nl01ll1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01lii1i_dataout <= wire_nl01ll1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01lii1l_dataout <= wire_nl01ll1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01lii1O_dataout <= wire_nl01ll1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01liiii_dataout <= wire_nl01ll1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01liiil_dataout <= wire_nl01ll01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01liiiO_dataout <= wire_nl01ll01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01liili_dataout <= wire_nl01ll01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01liill_dataout <= wire_nl01ll00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01liilO_dataout <= wire_nl01ll00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl01liiOi_dataout <= wire_nilOiili_dataout WHEN niOi0lOiO = '1' ELSE nl01l01ll; + wire_nl01liiOl_dataout <= wire_nilOiill_dataout WHEN niOi0lOiO = '1' ELSE nl01l01lO; + wire_nl01liiOO_dataout <= wire_nilOiilO_dataout WHEN niOi0lOiO = '1' ELSE nl01l01Oi; + wire_nl01lil_dataout <= nl00liil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01lil0i_dataout <= wire_nilOil1i_dataout WHEN niOi0lOiO = '1' ELSE nl01l001l; + wire_nl01lil0l_dataout <= wire_nilOil1l_dataout WHEN niOi0lOiO = '1' ELSE nl01l001O; + wire_nl01lil0O_dataout <= wire_nilOil1O_dataout WHEN niOi0lOiO = '1' ELSE nl01l000i; + wire_nl01lil1i_dataout <= wire_nilOiiOi_dataout WHEN niOi0lOiO = '1' ELSE nl01l01Ol; + wire_nl01lil1l_dataout <= wire_nilOiiOl_dataout WHEN niOi0lOiO = '1' ELSE nl01l01OO; + wire_nl01lil1O_dataout <= wire_nilOiiOO_dataout WHEN niOi0lOiO = '1' ELSE nl01l001i; + wire_nl01lilii_dataout <= wire_nilOil0i_dataout WHEN niOi0lOiO = '1' ELSE nl01l000l; + wire_nl01lilil_dataout <= wire_nilOil0l_dataout WHEN niOi0lOiO = '1' ELSE nl01l000O; + wire_nl01liliO_dataout <= wire_nilOil0O_dataout WHEN niOi0lOiO = '1' ELSE nl01l00ii; + wire_nl01lilli_dataout <= wire_nilOilii_dataout WHEN niOi0lOiO = '1' ELSE nl01l00il; + wire_nl01lilll_dataout <= wire_nilOilil_dataout WHEN niOi0lOiO = '1' ELSE nl01l00iO; + wire_nl01lillO_dataout <= wire_nilOiliO_dataout WHEN niOi0lOiO = '1' ELSE nl01l00li; + wire_nl01lilOi_dataout <= wire_nilOilli_dataout WHEN niOi0lOiO = '1' ELSE nl01l00ll; + wire_nl01lilOl_dataout <= wire_nilOilll_dataout WHEN niOi0lOiO = '1' ELSE nl01l00lO; + wire_nl01lilOO_dataout <= wire_nilOillO_dataout WHEN niOi0lOiO = '1' ELSE nl01l00Oi; + wire_nl01liO_dataout <= nl00liiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01liO0i_dataout <= wire_nilOiO1i_dataout WHEN niOi0lOiO = '1' ELSE nl01l0i1l; + wire_nl01liO0l_dataout <= wire_nilOiO1l_dataout WHEN niOi0lOiO = '1' ELSE nl01l0i1O; + wire_nl01liO0O_dataout <= wire_nilOiO1O_dataout WHEN niOi0lOiO = '1' ELSE nl01l0i0i; + wire_nl01liO1i_dataout <= wire_nilOilOi_dataout WHEN niOi0lOiO = '1' ELSE nl01l00Ol; + wire_nl01liO1l_dataout <= wire_nilOilOl_dataout WHEN niOi0lOiO = '1' ELSE nl01l00OO; + wire_nl01liO1O_dataout <= wire_nilOilOO_dataout WHEN niOi0lOiO = '1' ELSE nl01l0i1i; + wire_nl01liOii_dataout <= wire_nilOiO0i_dataout WHEN niOi0lOiO = '1' ELSE nl01l0i0l; + wire_nl01liOil_dataout <= wire_nilOiO0l_dataout WHEN niOi0lOiO = '1' ELSE nl01l0i0O; + wire_nl01liOiO_dataout <= wire_nilOiO0O_dataout WHEN niOi0lOiO = '1' ELSE nl01l0iii; + wire_nl01liOli_dataout <= wire_nilOiOii_dataout WHEN niOi0lOiO = '1' ELSE nl01l0iil; + wire_nl01liOll_dataout <= wire_nilOiOil_dataout WHEN niOi0lOiO = '1' ELSE nl01l0iiO; + wire_nl01liOlO_dataout <= niOi0i11O WHEN niOi0lOiO = '1' ELSE nl01l0ili; + wire_nl01liOOi_dataout <= niOi00O1O WHEN niOi0lOiO = '1' ELSE nl01l0ill; + wire_nl01liOOl_dataout <= wire_nilOi0lO_dataout WHEN niOi0lOiO = '1' ELSE nl01l0ilO; + wire_nl01liOOO_dataout <= wire_nilOi0Oi_dataout WHEN niOi0lOiO = '1' ELSE nl01l0iOi; + wire_nl01ll00i_dataout <= (wire_nilOl1Oi_w_lg_dataout43272w(0) AND niOi00Oil) WHEN niOi0lOiO = '1' ELSE nl01l0O1l; + wire_nl01ll00l_dataout <= wire_nilOl1Oi_dataout WHEN niOi0lOiO = '1' ELSE nl01l0O1O; + wire_nl01ll01i_dataout <= niOi00Oii WHEN niOi0lOiO = '1' ELSE nl01l0lOl; + wire_nl01ll01l_dataout <= (wire_nilOl1Ol_w_lg_dataout43262w(0) AND (wire_nilOl1il_dataout AND niOi00Oil)) WHEN niOi0lOiO = '1' ELSE nl01l0lOO; + wire_nl01ll01O_dataout <= (wire_nilOl1Oi_dataout AND niOi00Oil) WHEN niOi0lOiO = '1' ELSE nl01l0O1i; + wire_nl01ll10i_dataout <= wire_nilOii1l_dataout WHEN niOi0lOiO = '1' ELSE nl01l0l1l; + wire_nl01ll10l_dataout <= wire_nilOii1O_dataout WHEN niOi0lOiO = '1' ELSE nl01l0l1O; + wire_nl01ll10O_dataout <= wire_nilOii0i_dataout WHEN niOi0lOiO = '1' ELSE nl01l0l0i; + wire_nl01ll11i_dataout <= wire_nilOi0Ol_dataout WHEN niOi0lOiO = '1' ELSE nl01l0iOl; + wire_nl01ll11l_dataout <= wire_nilOi0OO_dataout WHEN niOi0lOiO = '1' ELSE nl01l0iOO; + wire_nl01ll11O_dataout <= wire_nilOii1i_dataout WHEN niOi0lOiO = '1' ELSE nl01l0l1i; + wire_nl01ll1ii_dataout <= wire_nilOl1Ol_dataout WHEN niOi0lOiO = '1' ELSE nl01l0l0l; + wire_nl01ll1il_dataout <= wire_nilOiOOl_dataout WHEN niOi0lOiO = '1' ELSE nl01l0l0O; + wire_nl01ll1iO_dataout <= wire_nilOiOOi_dataout WHEN niOi0lOiO = '1' ELSE nl01l0lii; + wire_nl01ll1li_dataout <= (wire_nilOl1il_dataout AND niOi00O0i) WHEN niOi0lOiO = '1' ELSE nl01l0lil; + wire_nl01ll1ll_dataout <= niOi00O0i WHEN niOi0lOiO = '1' ELSE nl01l0liO; + wire_nl01ll1lO_dataout <= (niOi00O0l AND (wire_nilOl1Ol_dataout AND wire_nilOl1Oi_dataout)) WHEN niOi0lOiO = '1' ELSE nl01l0lli; + wire_nl01ll1Oi_dataout <= niOi00O0l WHEN niOi0lOiO = '1' ELSE nl01l0lll; + wire_nl01ll1Ol_dataout <= niOi00O0O WHEN niOi0lOiO = '1' ELSE nl01l0llO; + wire_nl01ll1OO_dataout <= niOi0lOli WHEN niOi0lOiO = '1' ELSE nl01l0lOi; + wire_nl01lli_dataout <= nl00lili AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01lli1l_dataout <= ((wire_w_lg_niOi00Oll53194w(0) AND ((wire_nilOl11l_w_lg_dataout49175w(0) AND wire_nilOl11i_w_lg_dataout49181w(0)) AND wire_nilOiOOO_w_lg_dataout49183w(0))) AND wire_w_lg_niOi00Oli53198w(0)) AND wire_w_lg_niOi0lOll53190w(0); + wire_nl01lli1O_dataout <= (niOi00Oll AND (wire_w_lg_niOi00Oli53183w(0) OR (wire_w_lg_w_lg_niOi00OOO53184w53185w(0) AND wire_nlill0Oll_w_lg_nl01l0O0i53186w(0)))) AND wire_w_lg_niOi0lOll53190w(0); + wire_nl01lll_dataout <= nl00lill AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01llO_dataout <= nl00lilO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01llO0i_dataout <= wire_nl01lO1iO_dataout AND NOT(niOi0lO0l); + wire_nl01llO0l_dataout <= wire_nl01lO1li_dataout AND NOT(niOi0lO0l); + wire_nl01llO0O_dataout <= wire_nl01lO1ll_dataout AND NOT(niOi0lO0l); + wire_nl01llO1i_dataout <= wire_nl01lO11l_dataout AND NOT(niOi0lO0l); + wire_nl01llO1l_dataout <= wire_nl01lO11O_dataout AND NOT(niOi0lO0l); + wire_nl01llO1O_dataout <= wire_nl01lO1il_dataout AND NOT(niOi0lO0l); + wire_nl01llOii_dataout <= wire_nl01lO1lO_dataout AND NOT(niOi0lO0l); + wire_nl01llOil_dataout <= wire_nl01lO1Oi_dataout AND NOT(niOi0lO0l); + wire_nl01llOiO_dataout <= wire_nl01lO1Ol_dataout AND NOT(niOi0lO0l); + wire_nl01llOli_dataout <= wire_nl01lO1OO_dataout AND NOT(niOi0lO0l); + wire_nl01llOll_dataout <= wire_nl01lO01i_dataout AND NOT(niOi0lO0l); + wire_nl01llOlO_dataout <= wire_nl01lO01l_dataout AND NOT(niOi0lO0l); + wire_nl01llOOi_dataout <= wire_nl01lO01O_dataout AND NOT(niOi0lO0l); + wire_nl01llOOl_dataout <= wire_nl01lO00i_dataout AND NOT(niOi0lO0l); + wire_nl01llOOO_dataout <= wire_nl01lO00l_dataout AND NOT(niOi0lO0l); + wire_nl01lO00i_dataout <= wire_nl01lO0ii_o(12) WHEN niOi0lOiO = '1' ELSE nl01lllOi; + wire_nl01lO00l_dataout <= wire_nl01lO0ii_o(13) WHEN niOi0lOiO = '1' ELSE nl01lllOl; + wire_nl01lO00O_dataout <= (wire_nilOl1Ol_w_lg_dataout43262w(0) OR wire_w_lg_niOi0i11l53116w(0)) WHEN niOi0lOiO = '1' ELSE nl01lllOO; + wire_nl01lO01i_dataout <= wire_nl01lO0ii_o(9) WHEN niOi0lOiO = '1' ELSE nl01lllli; + wire_nl01lO01l_dataout <= wire_nl01lO0ii_o(10) WHEN niOi0lOiO = '1' ELSE nl01lllll; + wire_nl01lO01O_dataout <= wire_nl01lO0ii_o(11) WHEN niOi0lOiO = '1' ELSE nl01llllO; + wire_nl01lO0i_dataout <= wire_nl01O00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lO0l_dataout <= wire_nl01O00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lO0O_dataout <= wire_nl01O00O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lO11i_dataout <= wire_nl01lO00O_dataout AND NOT(niOi0lO0l); + wire_nl01lO11l_dataout <= niOi00OlO WHEN niOi0lOiO = '1' ELSE nl01l0O0i; + wire_nl01lO11O_dataout <= ((((nl01lllOO OR niOi0i11i) OR niOi00OOO) OR niOi00OOl) AND nl01l0liO) WHEN niOi00OOi = '1' ELSE nl01lll1i; + wire_nl01lO1i_dataout <= wire_nl01O01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lO1il_dataout <= wire_nl01lO0ii_o(1) WHEN niOi0lOiO = '1' ELSE nl01lll1l; + wire_nl01lO1iO_dataout <= wire_nl01lO0ii_o(2) WHEN niOi0lOiO = '1' ELSE nl01lll1O; + wire_nl01lO1l_dataout <= wire_nl01O01l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lO1li_dataout <= wire_nl01lO0ii_o(3) WHEN niOi0lOiO = '1' ELSE nl01lll0i; + wire_nl01lO1ll_dataout <= wire_nl01lO0ii_o(4) WHEN niOi0lOiO = '1' ELSE nl01lll0l; + wire_nl01lO1lO_dataout <= wire_nl01lO0ii_o(5) WHEN niOi0lOiO = '1' ELSE nl01lll0O; + wire_nl01lO1O_dataout <= wire_nl01O01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lO1Oi_dataout <= wire_nl01lO0ii_o(6) WHEN niOi0lOiO = '1' ELSE nl01lllii; + wire_nl01lO1Ol_dataout <= wire_nl01lO0ii_o(7) WHEN niOi0lOiO = '1' ELSE nl01lllil; + wire_nl01lO1OO_dataout <= wire_nl01lO0ii_o(8) WHEN niOi0lOiO = '1' ELSE nl01llliO; + wire_nl01lOi_dataout <= nl00liOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01lOii_dataout <= wire_nl01O0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOil_dataout <= wire_nl01O0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOiO_dataout <= wire_nl01O0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOl_dataout <= nl00liOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01lOli_dataout <= wire_nl01O0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOll_dataout <= wire_nl01O0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOlO_dataout <= wire_nl01O0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOO_dataout <= nl00liOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01lOOi_dataout <= wire_nl01O0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOOl_dataout <= wire_nl01O0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01lOOO_dataout <= wire_nl01O0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O000i_dataout <= wire_nl01OiOlO_dataout AND NOT(niOi0lO0l); + wire_nl01O000l_dataout <= wire_nl01OiOOi_dataout AND NOT(niOi0lO0l); + wire_nl01O000O_dataout <= wire_nl01OiOOl_dataout AND NOT(niOi0lO0l); + wire_nl01O001i_dataout <= wire_nl01OiOiO_dataout AND NOT(niOi0lO0l); + wire_nl01O001l_dataout <= wire_nl01OiOli_dataout AND NOT(niOi0lO0l); + wire_nl01O001O_dataout <= wire_nl01OiOll_dataout AND NOT(niOi0lO0l); + wire_nl01O00i_dataout <= nl01OO1i WHEN niOO1lO0l = '1' ELSE nl01li1O; + wire_nl01O00ii_dataout <= wire_nl01OiOOO_dataout AND NOT(niOi0lO0l); + wire_nl01O00il_dataout <= wire_nl01Ol11i_dataout AND NOT(niOi0lO0l); + wire_nl01O00iO_dataout <= wire_nl01Ol11l_dataout AND NOT(niOi0lO0l); + wire_nl01O00l_dataout <= nl01OO1l WHEN niOO1lO0l = '1' ELSE nl01li0i; + wire_nl01O00li_dataout <= wire_nl01Ol11O_dataout AND NOT(niOi0lO0l); + wire_nl01O00ll_dataout <= wire_nl01Ol10i_dataout AND NOT(niOi0lO0l); + wire_nl01O00lO_dataout <= wire_nl01Ol10l_dataout AND NOT(niOi0lO0l); + wire_nl01O00O_dataout <= nl01OO1O WHEN niOO1lO0l = '1' ELSE nl01li0l; + wire_nl01O00Oi_dataout <= wire_nl01Ol10O_dataout AND NOT(niOi0lO0l); + wire_nl01O00Ol_dataout <= wire_nl01Ol1ii_dataout AND NOT(niOi0lO0l); + wire_nl01O00OO_dataout <= wire_nl01Ol1il_dataout AND NOT(niOi0lO0l); + wire_nl01O010i_dataout <= wire_nl01OillO_dataout AND NOT(niOi0lO0l); + wire_nl01O010l_dataout <= wire_nl01OilOi_dataout AND NOT(niOi0lO0l); + wire_nl01O010O_dataout <= wire_nl01OilOl_dataout AND NOT(niOi0lO0l); + wire_nl01O011O_dataout <= wire_nl01Oilll_dataout AND NOT(niOi0lO0l); + wire_nl01O01i_dataout <= nl01OlOi WHEN niOO1lO0l = '1' ELSE nl01Ol1l; + wire_nl01O01ii_dataout <= wire_nl01OilOO_dataout AND NOT(niOi0lO0l); + wire_nl01O01il_dataout <= wire_nl01OiO1i_dataout AND NOT(niOi0lO0l); + wire_nl01O01iO_dataout <= wire_nl01OiO1l_dataout AND NOT(niOi0lO0l); + wire_nl01O01l_dataout <= nl01OlOl WHEN niOO1lO0l = '1' ELSE nl01li1i; + wire_nl01O01li_dataout <= wire_nl01OiO1O_dataout AND NOT(niOi0lO0l); + wire_nl01O01ll_dataout <= wire_nl01OiO0i_dataout AND NOT(niOi0lO0l); + wire_nl01O01lO_dataout <= wire_nl01OiO0l_dataout AND NOT(niOi0lO0l); + wire_nl01O01O_dataout <= nl01OlOO WHEN niOO1lO0l = '1' ELSE nl01li1l; + wire_nl01O01Oi_dataout <= wire_nl01OiO0O_dataout AND NOT(niOi0lO0l); + wire_nl01O01Ol_dataout <= wire_nl01OiOii_dataout AND NOT(niOi0lO0l); + wire_nl01O01OO_dataout <= wire_nl01OiOil_dataout AND NOT(niOi0lO0l); + wire_nl01O0i_dataout <= nl0iliii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01O0i0i_dataout <= wire_nl01Ol1lO_dataout AND NOT(niOi0lO0l); + wire_nl01O0i0l_dataout <= wire_nl01Ol1Oi_dataout AND NOT(niOi0lO0l); + wire_nl01O0i0O_dataout <= wire_nl01Ol1Ol_dataout AND NOT(niOi0lO0l); + wire_nl01O0i1i_dataout <= wire_nl01Ol1iO_dataout AND NOT(niOi0lO0l); + wire_nl01O0i1l_dataout <= wire_nl01Ol1li_dataout AND NOT(niOi0lO0l); + wire_nl01O0i1O_dataout <= wire_nl01Ol1ll_dataout AND NOT(niOi0lO0l); + wire_nl01O0ii_dataout <= nl01OO0i WHEN niOO1lO0l = '1' ELSE nl01li0O; + wire_nl01O0iii_dataout <= wire_nl01Ol1OO_dataout AND NOT(niOi0lO0l); + wire_nl01O0iil_dataout <= wire_nl01Ol01i_dataout AND NOT(niOi0lO0l); + wire_nl01O0iiO_dataout <= wire_nl01Ol01l_dataout AND NOT(niOi0lO0l); + wire_nl01O0il_dataout <= nl01OO0l WHEN niOO1lO0l = '1' ELSE nl01liii; + wire_nl01O0ili_dataout <= wire_nl01Ol01O_dataout AND NOT(niOi0lO0l); + wire_nl01O0ill_dataout <= wire_nl01Ol00i_dataout AND NOT(niOi0lO0l); + wire_nl01O0ilO_dataout <= wire_nl01Ol00l_dataout AND NOT(niOi0lO0l); + wire_nl01O0iO_dataout <= nl01OO0O WHEN niOO1lO0l = '1' ELSE nl01liil; + wire_nl01O0iOi_dataout <= wire_nl01Ol00O_dataout AND NOT(niOi0lO0l); + wire_nl01O0iOl_dataout <= wire_nl01Ol0ii_dataout AND NOT(niOi0lO0l); + wire_nl01O0iOO_dataout <= wire_nl01Ol0il_dataout AND NOT(niOi0lO0l); + wire_nl01O0l_dataout <= nl0il10l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01O0l0i_dataout <= wire_nl01Ol0lO_dataout AND NOT(niOi0lO0l); + wire_nl01O0l0l_dataout <= wire_nl01Ol0Oi_dataout AND NOT(niOi0lO0l); + wire_nl01O0l0O_dataout <= wire_nl01Ol0Ol_dataout AND NOT(niOi0lO0l); + wire_nl01O0l1i_dataout <= wire_nl01Ol0iO_dataout AND NOT(niOi0lO0l); + wire_nl01O0l1l_dataout <= wire_nl01Ol0li_dataout AND NOT(niOi0lO0l); + wire_nl01O0l1O_dataout <= wire_nl01Ol0ll_dataout AND NOT(niOi0lO0l); + wire_nl01O0li_dataout <= nl01OOii WHEN niOO1lO0l = '1' ELSE nl01liiO; + wire_nl01O0lii_dataout <= wire_nl01Ol0OO_dataout AND NOT(niOi0lO0l); + wire_nl01O0lil_dataout <= wire_nl01Oli1i_dataout AND NOT(niOi0lO0l); + wire_nl01O0liO_dataout <= wire_nl01Oli1l_dataout AND NOT(niOi0lO0l); + wire_nl01O0ll_dataout <= nl01OOil WHEN niOO1lO0l = '1' ELSE nl01lili; + wire_nl01O0lli_dataout <= wire_nl01Oli1O_dataout AND NOT(niOi0lO0l); + wire_nl01O0lll_dataout <= wire_nl01Oli0i_dataout AND NOT(niOi0lO0l); + wire_nl01O0llO_dataout <= wire_nl01Oli0l_dataout AND NOT(niOi0lO0l); + wire_nl01O0lO_dataout <= nl01OOiO WHEN niOO1lO0l = '1' ELSE nl01lill; + wire_nl01O0lOi_dataout <= wire_nl01Oli0O_dataout AND NOT(niOi0lO0l); + wire_nl01O0lOl_dataout <= wire_nl01Oliii_dataout AND NOT(niOi0lO0l); + wire_nl01O0lOO_dataout <= wire_nl01Oliil_dataout AND NOT(niOi0lO0l); + wire_nl01O0O_dataout <= nl0il10O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01O0O0i_dataout <= wire_nl01OlilO_dataout AND NOT(niOi0lO0l); + wire_nl01O0O0l_dataout <= wire_nl01OliOi_dataout AND NOT(niOi0lO0l); + wire_nl01O0O0O_dataout <= wire_nl01OliOl_dataout AND NOT(niOi0lO0l); + wire_nl01O0O1i_dataout <= wire_nl01OliiO_dataout AND NOT(niOi0lO0l); + wire_nl01O0O1l_dataout <= wire_nl01Olili_dataout AND NOT(niOi0lO0l); + wire_nl01O0O1O_dataout <= wire_nl01Olill_dataout AND NOT(niOi0lO0l); + wire_nl01O0Oi_dataout <= nl01OOli WHEN niOO1lO0l = '1' ELSE nl01lilO; + wire_nl01O0Oii_dataout <= wire_nl01OliOO_dataout AND NOT(niOi0lO0l); + wire_nl01O0Oil_dataout <= wire_nl01Oll1i_dataout AND NOT(niOi0lO0l); + wire_nl01O0OiO_dataout <= wire_nl01Oll1l_dataout AND NOT(niOi0lO0l); + wire_nl01O0Ol_dataout <= nl01OOll WHEN niOO1lO0l = '1' ELSE nl01liOi; + wire_nl01O0Oli_dataout <= wire_nl01Oll1O_dataout AND NOT(niOi0lO0l); + wire_nl01O0Oll_dataout <= wire_nl01Oll0i_dataout AND NOT(niOi0lO0l); + wire_nl01O0OlO_dataout <= wire_nl01Oll0l_dataout AND NOT(niOi0lO0l); + wire_nl01O0OO_dataout <= nl01OOlO WHEN niOO1lO0l = '1' ELSE nl01liOl; + wire_nl01O0OOi_dataout <= wire_nl01Oll0O_dataout AND NOT(niOi0lO0l); + wire_nl01O0OOl_dataout <= wire_nl01Ollii_dataout AND NOT(niOi0lO0l); + wire_nl01O0OOO_dataout <= wire_nl01Ollil_dataout AND NOT(niOi0lO0l); + wire_nl01O10i_dataout <= wire_nl01Oi0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O10l_dataout <= wire_nl01Oi0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O10O_dataout <= wire_nl01Oi0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O11i_dataout <= wire_nl01Oi1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O11l_dataout <= wire_nl01Oi1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O11O_dataout <= wire_nl01Oi1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1i_dataout <= nl0il1ii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01O1ii_dataout <= wire_nl01Oiii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1il_dataout <= wire_nl01Oiil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1iO_dataout <= wire_nl01OiiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1l_dataout <= nl0il1il AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01O1li_dataout <= wire_nl01Oili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1ll_dataout <= wire_nl01Oill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1lO_dataout <= wire_nl01OilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1O_dataout <= nl0il1iO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01O1Oi_dataout <= wire_nl01OiOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1Ol_dataout <= wire_nl01OiOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01O1OO_dataout <= wire_nl01OiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl01Oi00i_dataout <= wire_nl01OlOlO_dataout AND NOT(niOi0lO0l); + wire_nl01Oi00l_dataout <= wire_nl01OlOOi_dataout AND NOT(niOi0lO0l); + wire_nl01Oi00O_dataout <= wire_nl01OlOOl_dataout AND NOT(niOi0lO0l); + wire_nl01Oi01i_dataout <= wire_nl01OlOiO_dataout AND NOT(niOi0lO0l); + wire_nl01Oi01l_dataout <= wire_nl01OlOli_dataout AND NOT(niOi0lO0l); + wire_nl01Oi01O_dataout <= wire_nl01OlOll_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0i_dataout <= nl0011ii WHEN niOO1lO0l = '1' ELSE nl01ll1O; + wire_nl01Oi0ii_dataout <= wire_nl01OlOOO_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0il_dataout <= wire_nl01OO11i_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0iO_dataout <= wire_nl01OO11l_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0l_dataout <= nl0011il WHEN niOO1lO0l = '1' ELSE nl01ll0i; + wire_nl01Oi0li_dataout <= wire_nl01OO11O_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0ll_dataout <= wire_nl01OO10i_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0lO_dataout <= wire_nl01OO10l_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0O_dataout <= nl0011iO WHEN niOO1lO0l = '1' ELSE nl01ll0l; + wire_nl01Oi0Oi_dataout <= wire_nl01OO10O_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0Ol_dataout <= wire_nl01OO1ii_dataout AND NOT(niOi0lO0l); + wire_nl01Oi0OO_dataout <= wire_nl01OO1il_dataout AND NOT(niOi0lO0l); + wire_nl01Oi10i_dataout <= wire_nl01OlllO_dataout AND NOT(niOi0lO0l); + wire_nl01Oi10l_dataout <= wire_nl01OllOi_dataout AND NOT(niOi0lO0l); + wire_nl01Oi10O_dataout <= wire_nl01OllOl_dataout AND NOT(niOi0lO0l); + wire_nl01Oi11i_dataout <= wire_nl01OlliO_dataout AND NOT(niOi0lO0l); + wire_nl01Oi11l_dataout <= wire_nl01Ollli_dataout AND NOT(niOi0lO0l); + wire_nl01Oi11O_dataout <= wire_nl01Ollll_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1i_dataout <= nl00110i WHEN niOO1lO0l = '1' ELSE nl01liOO; + wire_nl01Oi1ii_dataout <= wire_nl01OllOO_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1il_dataout <= wire_nl01OlO1i_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1iO_dataout <= wire_nl01OlO1l_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1l_dataout <= nl00110l WHEN niOO1lO0l = '1' ELSE nl01ll1i; + wire_nl01Oi1li_dataout <= wire_nl01OlO1O_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1ll_dataout <= wire_nl01OlO0i_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1lO_dataout <= wire_nl01OlO0l_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1O_dataout <= nl00110O WHEN niOO1lO0l = '1' ELSE nl01ll1l; + wire_nl01Oi1Oi_dataout <= wire_nl01OlO0O_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1Ol_dataout <= wire_nl01OlOii_dataout AND NOT(niOi0lO0l); + wire_nl01Oi1OO_dataout <= wire_nl01OlOil_dataout AND NOT(niOi0lO0l); + wire_nl01Oii_dataout <= nl00ll1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01Oii0i_dataout <= wire_nl01OO1lO_dataout AND NOT(niOi0lO0l); + wire_nl01Oii0l_dataout <= wire_nl01OO1Oi_dataout AND NOT(niOi0lO0l); + wire_nl01Oii0O_dataout <= wire_nl01OO1Ol_dataout AND NOT(niOi0lO0l); + wire_nl01Oii1i_dataout <= wire_nl01OO1iO_dataout AND NOT(niOi0lO0l); + wire_nl01Oii1l_dataout <= wire_nl01OO1li_dataout AND NOT(niOi0lO0l); + wire_nl01Oii1O_dataout <= wire_nl01OO1ll_dataout AND NOT(niOi0lO0l); + wire_nl01Oiii_dataout <= nl0011li WHEN niOO1lO0l = '1' ELSE nl01ll0O; + wire_nl01Oiiii_dataout <= wire_nl01OO1OO_dataout AND NOT(niOi0lO0l); + wire_nl01Oiiil_dataout <= wire_nl01OO01i_dataout AND NOT(niOi0lO0l); + wire_nl01OiiiO_dataout <= wire_nl01OO01l_dataout AND NOT(niOi0lO0l); + wire_nl01Oiil_dataout <= nl0011ll WHEN niOO1lO0l = '1' ELSE nl01llii; + wire_nl01Oiili_dataout <= wire_nl01OO01O_dataout AND NOT(niOi0lO0l); + wire_nl01Oiill_dataout <= wire_nl01OO00i_dataout AND NOT(niOi0lO0l); + wire_nl01OiilO_dataout <= wire_nl01OO00l_dataout AND NOT(niOi0lO0l); + wire_nl01OiiO_dataout <= nl0011lO WHEN niOO1lO0l = '1' ELSE nl01llil; + wire_nl01OiiOi_dataout <= wire_nl01OO00O_dataout AND NOT(niOi0lO0l); + wire_nl01OiiOl_dataout <= wire_nl01OO0ii_dataout AND NOT(niOi0lO0l); + wire_nl01OiiOO_dataout <= wire_nl01OO0il_dataout AND NOT(niOi0lO0l); + wire_nl01Oil_dataout <= nl00ll1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01Oil0i_dataout <= wire_nl01OO0lO_dataout AND NOT(niOi0lO0l); + wire_nl01Oil0l_dataout <= wire_nl01OO0Oi_dataout AND NOT(niOi0lO0l); + wire_nl01Oil0O_dataout <= wire_nl01OO0Ol_dataout AND NOT(niOi0lO0l); + wire_nl01Oil1i_dataout <= wire_nl01OO0iO_dataout AND NOT(niOi0lO0l); + wire_nl01Oil1l_dataout <= wire_nl01OO0li_dataout AND NOT(niOi0lO0l); + wire_nl01Oil1O_dataout <= wire_nl01OO0ll_dataout AND NOT(niOi0lO0l); + wire_nl01Oili_dataout <= nl0011Oi WHEN niOO1lO0l = '1' ELSE nl01lliO; + wire_nl01Oilii_dataout <= wire_nl01OO0OO_dataout AND NOT(niOi0lO0l); + wire_nl01Oilil_dataout <= wire_nl01OOi1i_dataout AND NOT(niOi0lO0l); + wire_nl01OiliO_dataout <= wire_nl01OOi1l_dataout AND NOT(niOi0lO0l); + wire_nl01Oill_dataout <= nl0011Ol WHEN niOO1lO0l = '1' ELSE nl01llli; + wire_nl01Oilli_dataout <= wire_nl01OOi1O_dataout AND NOT(niOi0lO0l); + wire_nl01Oilll_dataout <= wire_nl01OOi0i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lO1l_dataout; + wire_nl01OillO_dataout <= wire_nl01OOi0l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lO1O_dataout; + wire_nl01OilO_dataout <= nl0011OO WHEN niOO1lO0l = '1' ELSE nl01llll; + wire_nl01OilOi_dataout <= wire_nl01OOi0O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lO0i_dataout; + wire_nl01OilOl_dataout <= wire_nl01OOiii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lO0l_dataout; + wire_nl01OilOO_dataout <= wire_nl01OOiil_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lO0O_dataout; + wire_nl01OiO_dataout <= nl00ll1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01OiO0i_dataout <= wire_nl01OOilO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOli_dataout; + wire_nl01OiO0l_dataout <= wire_nl01OOiOi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOll_dataout; + wire_nl01OiO0O_dataout <= wire_nl01OOiOl_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOlO_dataout; + wire_nl01OiO1i_dataout <= wire_nl01OOiiO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOii_dataout; + wire_nl01OiO1l_dataout <= wire_nl01OOili_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOil_dataout; + wire_nl01OiO1O_dataout <= wire_nl01OOill_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOiO_dataout; + wire_nl01OiOi_dataout <= nl00101i WHEN niOO1lO0l = '1' ELSE nl01lllO; + wire_nl01OiOii_dataout <= wire_nl01OOiOO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOOi_dataout; + wire_nl01OiOil_dataout <= wire_nl01OOl1i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOOl_dataout; + wire_nl01OiOiO_dataout <= wire_nl01OOl1l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001lOOO_dataout; + wire_nl01OiOl_dataout <= nl00101l WHEN niOO1lO0l = '1' ELSE nl01llOi; + wire_nl01OiOli_dataout <= wire_nl01OOl1O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O11i_dataout; + wire_nl01OiOll_dataout <= wire_nl01OOl0i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O11l_dataout; + wire_nl01OiOlO_dataout <= wire_nl01OOl0l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O11O_dataout; + wire_nl01OiOO_dataout <= nl00101O WHEN niOO1lO0l = '1' ELSE nl01llOl; + wire_nl01OiOOi_dataout <= wire_nl01OOl0O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O10i_dataout; + wire_nl01OiOOl_dataout <= wire_nl01OOlii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O10l_dataout; + wire_nl01OiOOO_dataout <= wire_nl01OOlil_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O10O_dataout; + wire_nl01Ol00i_dataout <= wire_nl01OOOlO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0li_dataout; + wire_nl01Ol00l_dataout <= wire_nl01OOOOi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0ll_dataout; + wire_nl01Ol00O_dataout <= wire_nl01OOOOl_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0lO_dataout; + wire_nl01Ol01i_dataout <= wire_nl01OOOiO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0ii_dataout; + wire_nl01Ol01l_dataout <= wire_nl01OOOli_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0il_dataout; + wire_nl01Ol01O_dataout <= wire_nl01OOOll_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0iO_dataout; + wire_nl01Ol0i_dataout <= nl01Olii AND NOT(wire_niO01O0O_dataout); + wire_nl01Ol0ii_dataout <= wire_nl01OOOOO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0Oi_dataout; + wire_nl01Ol0il_dataout <= wire_nl001111i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0Ol_dataout; + wire_nl01Ol0iO_dataout <= wire_nl001111l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O0OO_dataout; + wire_nl01Ol0li_dataout <= wire_nl001111O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oi1i_dataout; + wire_nl01Ol0ll_dataout <= wire_nl001110i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oi1l_dataout; + wire_nl01Ol0lO_dataout <= wire_nl001110l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oi1O_dataout; + wire_nl01Ol0O_dataout <= nl01llOO AND NOT(wire_niO01O0O_dataout); + wire_nl01Ol0Oi_dataout <= wire_nl001110O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oi0i_dataout; + wire_nl01Ol0Ol_dataout <= wire_nl00111ii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oi0l_dataout; + wire_nl01Ol0OO_dataout <= wire_nl00111il_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oi0O_dataout; + wire_nl01Ol10i_dataout <= wire_nl01OOllO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1li_dataout; + wire_nl01Ol10l_dataout <= wire_nl01OOlOi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1ll_dataout; + wire_nl01Ol10O_dataout <= wire_nl01OOlOl_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1lO_dataout; + wire_nl01Ol11i_dataout <= wire_nl01OOliO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1ii_dataout; + wire_nl01Ol11l_dataout <= wire_nl01OOlli_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1il_dataout; + wire_nl01Ol11O_dataout <= wire_nl01OOlll_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1iO_dataout; + wire_nl01Ol1ii_dataout <= wire_nl01OOlOO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1Oi_dataout; + wire_nl01Ol1il_dataout <= wire_nl01OOO1i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1Ol_dataout; + wire_nl01Ol1iO_dataout <= wire_nl01OOO1l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O1OO_dataout; + wire_nl01Ol1li_dataout <= wire_nl01OOO1O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O01i_dataout; + wire_nl01Ol1ll_dataout <= wire_nl01OOO0i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O01l_dataout; + wire_nl01Ol1lO_dataout <= wire_nl01OOO0l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O01O_dataout; + wire_nl01Ol1Oi_dataout <= wire_nl01OOO0O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O00i_dataout; + wire_nl01Ol1Ol_dataout <= wire_nl01OOOii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O00l_dataout; + wire_nl01Ol1OO_dataout <= wire_nl01OOOil_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001O00O_dataout; + wire_nl01Oli_dataout <= nl00ll0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01Oli0i_dataout <= wire_nl00111lO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oili_dataout; + wire_nl01Oli0l_dataout <= wire_nl00111Oi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oill_dataout; + wire_nl01Oli0O_dataout <= wire_nl00111Ol_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OilO_dataout; + wire_nl01Oli1i_dataout <= wire_nl00111iO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oiii_dataout; + wire_nl01Oli1l_dataout <= wire_nl00111li_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Oiil_dataout; + wire_nl01Oli1O_dataout <= wire_nl00111ll_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OiiO_dataout; + wire_nl01Oliii_dataout <= wire_nl00111OO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OiOi_dataout; + wire_nl01Oliil_dataout <= wire_nl001101i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OiOl_dataout; + wire_nl01OliiO_dataout <= wire_nl001101l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OiOO_dataout; + wire_nl01Olil_dataout <= nl01Olli AND NOT(wire_niO01l0O_dataout); + wire_nl01Olili_dataout <= wire_nl001101O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Ol1i_dataout; + wire_nl01Olill_dataout <= wire_nl001100i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Ol1l_dataout; + wire_nl01OlilO_dataout <= wire_nl001100l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Ol1O_dataout; + wire_nl01OliOi_dataout <= wire_nl001100O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Ol0i_dataout; + wire_nl01OliOl_dataout <= wire_nl00110ii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Ol0l_dataout; + wire_nl01OliOO_dataout <= wire_nl00110il_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Ol0O_dataout; + wire_nl01Oll_dataout <= nl00ll0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01Oll0i_dataout <= wire_nl00110lO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Olli_dataout; + wire_nl01Oll0l_dataout <= wire_nl00110Oi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Olll_dataout; + wire_nl01Oll0O_dataout <= wire_nl00110Ol_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OllO_dataout; + wire_nl01Oll1i_dataout <= wire_nl00110iO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Olii_dataout; + wire_nl01Oll1l_dataout <= wire_nl00110li_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001Olil_dataout; + wire_nl01Oll1O_dataout <= wire_nl00110ll_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OliO_dataout; + wire_nl01Ollii_dataout <= wire_nl00110OO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OlOi_dataout; + wire_nl01Ollil_dataout <= wire_nl0011i1i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OlOl_dataout; + wire_nl01OlliO_dataout <= wire_nl0011i1l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OlOO_dataout; + wire_nl01Olll_dataout <= nl01OliO AND NOT(wire_niO01l0O_dataout); + wire_nl01Ollli_dataout <= wire_nl0011i1O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OO1i_dataout; + wire_nl01Ollll_dataout <= wire_nl0011i0i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OO1l_dataout; + wire_nl01OlllO_dataout <= wire_nl0011i0l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OO1O_dataout; + wire_nl01OllO_dataout <= nl01Ol0l AND NOT(wire_niO01l0O_dataout); + wire_nl01OllOi_dataout <= wire_nl0011i0O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OO0i_dataout; + wire_nl01OllOl_dataout <= wire_nl0011iii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OO0l_dataout; + wire_nl01OllOO_dataout <= wire_nl0011iil_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OO0O_dataout; + wire_nl01OlO_dataout <= nl00ll0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01OlO0i_dataout <= wire_nl0011ilO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOli_dataout; + wire_nl01OlO0l_dataout <= wire_nl0011iOi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOll_dataout; + wire_nl01OlO0O_dataout <= wire_nl0011iOl_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOlO_dataout; + wire_nl01OlO1i_dataout <= wire_nl0011iiO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOii_dataout; + wire_nl01OlO1l_dataout <= wire_nl0011ili_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOil_dataout; + wire_nl01OlO1O_dataout <= wire_nl0011ill_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOiO_dataout; + wire_nl01OlOii_dataout <= wire_nl0011iOO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOOi_dataout; + wire_nl01OlOil_dataout <= wire_nl0011l1i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOOl_dataout; + wire_nl01OlOiO_dataout <= wire_nl0011l1l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl001OOOO_dataout; + wire_nl01OlOli_dataout <= wire_nl0011l1O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000111i_dataout; + wire_nl01OlOll_dataout <= wire_nl0011l0i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000111l_dataout; + wire_nl01OlOlO_dataout <= wire_nl0011l0l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000111O_dataout; + wire_nl01OlOOi_dataout <= wire_nl0011l0O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000110i_dataout; + wire_nl01OlOOl_dataout <= wire_nl0011lii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000110l_dataout; + wire_nl01OlOOO_dataout <= wire_nl0011lil_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000110O_dataout; + wire_nl01OO00i_dataout <= wire_nl0011OlO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010li_dataout; + wire_nl01OO00l_dataout <= wire_nl0011OOi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010ll_dataout; + wire_nl01OO00O_dataout <= wire_nl0011OOl_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010lO_dataout; + wire_nl01OO01i_dataout <= wire_nl0011OiO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010ii_dataout; + wire_nl01OO01l_dataout <= wire_nl0011Oli_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010il_dataout; + wire_nl01OO01O_dataout <= wire_nl0011Oll_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010iO_dataout; + wire_nl01OO0ii_dataout <= wire_nl0011OOO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010Oi_dataout; + wire_nl01OO0il_dataout <= wire_nl001011i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010Ol_dataout; + wire_nl01OO0iO_dataout <= wire_nl001011l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00010OO_dataout; + wire_nl01OO0li_dataout <= wire_nl001011O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001i1i_dataout; + wire_nl01OO0ll_dataout <= wire_nl001010i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001i1l_dataout; + wire_nl01OO0lO_dataout <= wire_nl001010l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001i1O_dataout; + wire_nl01OO0Oi_dataout <= wire_nl001010O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001i0i_dataout; + wire_nl01OO0Ol_dataout <= wire_nl00101ii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001i0l_dataout; + wire_nl01OO0OO_dataout <= wire_nl00101il_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001i0O_dataout; + wire_nl01OO10i_dataout <= wire_nl0011llO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011li_dataout; + wire_nl01OO10l_dataout <= wire_nl0011lOi_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011ll_dataout; + wire_nl01OO10O_dataout <= wire_nl0011lOl_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011lO_dataout; + wire_nl01OO11i_dataout <= wire_nl0011liO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011ii_dataout; + wire_nl01OO11l_dataout <= wire_nl0011lli_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011il_dataout; + wire_nl01OO11O_dataout <= wire_nl0011lll_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011iO_dataout; + wire_nl01OO1ii_dataout <= wire_nl0011lOO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011Oi_dataout; + wire_nl01OO1il_dataout <= wire_nl0011O1i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011Ol_dataout; + wire_nl01OO1iO_dataout <= wire_nl0011O1l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl00011OO_dataout; + wire_nl01OO1li_dataout <= wire_nl0011O1O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000101i_dataout; + wire_nl01OO1ll_dataout <= wire_nl0011O0i_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000101l_dataout; + wire_nl01OO1lO_dataout <= wire_nl0011O0l_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000101O_dataout; + wire_nl01OO1Oi_dataout <= wire_nl0011O0O_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000100i_dataout; + wire_nl01OO1Ol_dataout <= wire_nl0011Oii_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000100l_dataout; + wire_nl01OO1OO_dataout <= wire_nl0011Oil_dataout WHEN niOi0iOiO = '1' ELSE wire_nl000100O_dataout; + wire_nl01OOi_dataout <= nl00llii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01OOi0i_dataout <= wire_nl001ll0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lO1l_dataout; + wire_nl01OOi0l_dataout <= wire_nl001llii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lO1O_dataout; + wire_nl01OOi0O_dataout <= wire_nl001ll1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lO0i_dataout; + wire_nl01OOi1i_dataout <= wire_nl00101iO_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001iii_dataout; + wire_nl01OOi1l_dataout <= wire_nl00101li_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001iil_dataout; + wire_nl01OOi1O_dataout <= wire_nl00101ll_dataout WHEN niOi0iOiO = '1' ELSE wire_nl0001iiO_dataout; + wire_nl01OOiii_dataout <= wire_nl001ll0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lO0l_dataout; + wire_nl01OOiil_dataout <= wire_nl001liOO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lO0O_dataout; + wire_nl01OOiiO_dataout <= wire_nl001ll1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOii_dataout; + wire_nl01OOili_dataout <= wire_nl001lilO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOil_dataout; + wire_nl01OOill_dataout <= wire_nl001liOi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOiO_dataout; + wire_nl01OOilO_dataout <= wire_nl001liiO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOli_dataout; + wire_nl01OOiOi_dataout <= wire_nl001lili_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOll_dataout; + wire_nl01OOiOl_dataout <= wire_nl001li0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOlO_dataout; + wire_nl01OOiOO_dataout <= wire_nl001liii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOOi_dataout; + wire_nl01OOl_dataout <= nl00llil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01OOl0i_dataout <= wire_nl001li1i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O11l_dataout; + wire_nl01OOl0l_dataout <= wire_nl001l0lO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O11O_dataout; + wire_nl01OOl0O_dataout <= wire_nl001l0Oi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O10i_dataout; + wire_nl01OOl1i_dataout <= wire_nl001li1O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOOl_dataout; + wire_nl01OOl1l_dataout <= wire_nl001li0i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001lOOO_dataout; + wire_nl01OOl1O_dataout <= wire_nl001l0OO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O11i_dataout; + wire_nl01OOlii_dataout <= wire_nl001l0iO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O10l_dataout; + wire_nl01OOlil_dataout <= wire_nl001l0li_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O10O_dataout; + wire_nl01OOliO_dataout <= wire_nl001l00O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1ii_dataout; + wire_nl01OOlli_dataout <= wire_nl001l0ii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1il_dataout; + wire_nl01OOlll_dataout <= wire_nl001l01O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1iO_dataout; + wire_nl01OOllO_dataout <= wire_nl001l00i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1li_dataout; + wire_nl01OOlOi_dataout <= wire_nl001l1OO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1ll_dataout; + wire_nl01OOlOl_dataout <= wire_nl001l01i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1lO_dataout; + wire_nl01OOlOO_dataout <= wire_nl001l1lO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1Oi_dataout; + wire_nl01OOO_dataout <= nl00lliO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl01OOO0i_dataout <= wire_nl001l10O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O01l_dataout; + wire_nl01OOO0l_dataout <= wire_nl001l1ii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O01O_dataout; + wire_nl01OOO0O_dataout <= wire_nl001l11O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O00i_dataout; + wire_nl01OOO1i_dataout <= wire_nl001l1Oi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1Ol_dataout; + wire_nl01OOO1l_dataout <= wire_nl001l1iO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O1OO_dataout; + wire_nl01OOO1O_dataout <= wire_nl001l1li_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O01i_dataout; + wire_nl01OOOii_dataout <= wire_nl001l10i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O00l_dataout; + wire_nl01OOOil_dataout <= wire_nl001iOOO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O00O_dataout; + wire_nl01OOOiO_dataout <= wire_nl001l11i_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0ii_dataout; + wire_nl01OOOli_dataout <= wire_nl001iOlO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0il_dataout; + wire_nl01OOOll_dataout <= wire_nl001iOOi_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0iO_dataout; + wire_nl01OOOlO_dataout <= wire_nl001iOiO_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0li_dataout; + wire_nl01OOOOi_dataout <= wire_nl001iOli_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0ll_dataout; + wire_nl01OOOOl_dataout <= wire_nl001iO0O_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0lO_dataout; + wire_nl01OOOOO_dataout <= wire_nl001iOii_dataout WHEN niOi0iOil = '1' ELSE wire_nl001O0Oi_dataout; + wire_nl0i000i_dataout <= nl0i0lOi WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i101l; + wire_nl0i000l_dataout <= nl0i0lOl WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i101O; + wire_nl0i000O_dataout <= nl0i0lOO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i100i; + wire_nl0i001i_dataout <= nl0i0lli WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11Ol; + wire_nl0i001l_dataout <= nl0i0lll WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11OO; + wire_nl0i001O_dataout <= nl0i0llO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i101i; + wire_nl0i00ii_dataout <= nl0iiO1i WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i100l; + wire_nl0i00ili_dataout <= wire_nl0i0liii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00ill_dataout <= wire_nl0i0liil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00ilO_dataout <= wire_nl0i0liiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00iOi_dataout <= wire_nl0i0lili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00iOl_dataout <= wire_nl0i0lill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00iOO_dataout <= wire_nl0i0lilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00l0i_dataout <= wire_nl0i0ll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00l0l_dataout <= wire_nl0i0ll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00l0O_dataout <= wire_nl0i0ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00l1i_dataout <= wire_nl0i0liOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00l1l_dataout <= wire_nl0i0liOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00l1O_dataout <= wire_nl0i0liOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00lii_dataout <= wire_nl0i0ll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00lil_dataout <= wire_nl0i0ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00liO_dataout <= wire_nl0i0ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00lli_dataout <= wire_nl0i0llii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00lll_dataout <= wire_nl0i0llil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00llO_dataout <= wire_nl0i0lliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00lOi_dataout <= wire_nl0i0llli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00lOl_dataout <= wire_nl0i0llll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00lOO_dataout <= wire_nl0i0lllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00O0i_dataout <= wire_nl0i0lO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00O0l_dataout <= wire_nl0i0lO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00O0O_dataout <= wire_nl0i0lO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00O1i_dataout <= wire_nl0i0llOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00O1l_dataout <= wire_nl0i0llOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00O1O_dataout <= wire_nl0i0llOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00Oii_dataout <= wire_nl0i0lO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00Oil_dataout <= wire_nl0i0lO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00OiO_dataout <= wire_nl0i0lO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00Oli_dataout <= wire_nl0i0lOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00Oll_dataout <= wire_nl0i0lOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i00OlO_dataout <= nl0ili1ll AND NOT(wire_niO01O0O_dataout); + wire_nl0i00OOi_dataout <= nl0illl0i AND NOT(wire_niO01O0O_dataout); + wire_nl0i00OOl_dataout <= nl0illlli AND NOT(wire_niO01O0O_dataout); + wire_nl0i00OOO_dataout <= wire_nl0i0OlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i010i_dataout <= nl0i0iOi WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i111l; + wire_nl0i010l_dataout <= nl0i0iOl WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i111O; + wire_nl0i010O_dataout <= nl0i0iOO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i110i; + wire_nl0i011i_dataout <= nl0i0ili WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOOl; + wire_nl0i011l_dataout <= nl0i0ill WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOOO; + wire_nl0i011O_dataout <= nl0i0ilO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i111i; + wire_nl0i01ii_dataout <= nl0i0l1i WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i110l; + wire_nl0i01il_dataout <= nl0i0l1l WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i110O; + wire_nl0i01iO_dataout <= nl0i0l1O WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11ii; + wire_nl0i01li_dataout <= nl0i0l0i WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11il; + wire_nl0i01ll_dataout <= nl0i0l0l WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11iO; + wire_nl0i01lO_dataout <= nl0i0l0O WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11li; + wire_nl0i01Oi_dataout <= nl0i0lii WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11ll; + wire_nl0i01Ol_dataout <= nl0i0lil WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11lO; + wire_nl0i01OO_dataout <= nl0i0liO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl0i11Oi; + wire_nl0i0i00i_dataout <= wire_nl0ii111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i00l_dataout <= wire_nl0ii111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i00O_dataout <= wire_nl0ii110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i01i_dataout <= wire_nl0i0OOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i01l_dataout <= wire_nl0i0OOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i01O_dataout <= wire_nl0ii111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0ii_dataout <= wire_nl0ii110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0il_dataout <= wire_nl0ii110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0iO_dataout <= wire_nl0ii11ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0li_dataout <= wire_nl0ii11il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0ll_dataout <= wire_nl0ii11iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0lO_dataout <= wire_nl0ii11li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0Oi_dataout <= wire_nl0ii11ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0Ol_dataout <= wire_nl0ii11lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i0OO_dataout <= wire_nl0ii11Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i10i_dataout <= wire_nl0i0OO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i10l_dataout <= wire_nl0i0OO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i10O_dataout <= wire_nl0i0OO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i11i_dataout <= wire_nl0i0OlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i11l_dataout <= wire_nl0i0OlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i11O_dataout <= wire_nl0i0OO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1ii_dataout <= wire_nl0i0OO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1il_dataout <= wire_nl0i0OO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1iO_dataout <= wire_nl0i0OOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1li_dataout <= wire_nl0i0OOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1ll_dataout <= wire_nl0i0OOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1lO_dataout <= wire_nl0i0OOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1Oi_dataout <= wire_nl0i0OOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1Ol_dataout <= wire_nl0i0OOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0i1OO_dataout <= wire_nl0i0OOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ii0i_dataout <= wire_nl0ii010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ii0l_dataout <= wire_nl0ii01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ii0O_dataout <= wire_nl0ii01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ii1i_dataout <= wire_nl0ii11Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ii1l_dataout <= wire_nl0ii010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ii1O_dataout <= wire_nl0ii010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iiii_dataout <= wire_nl0ii01iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iiil_dataout <= wire_nl0ii01li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iiiO_dataout <= wire_nl0ii01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iili_dataout <= wire_nl0ii01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iill_dataout <= wire_nl0ii01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iilO_dataout <= wire_nl0ii01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iiOi_dataout <= wire_nl0ii01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iiOl_dataout <= wire_nl0ii001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iiOO_dataout <= wire_nl0ii001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0il0i_dataout <= wire_nl0ii000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0il0l_dataout <= wire_nl0ii00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0il0O_dataout <= wire_nl0ii00il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0il1i_dataout <= wire_nl0ii001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0il1l_dataout <= wire_nl0ii000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0il1O_dataout <= wire_nl0ii000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ilii_dataout <= wire_nl0ii00iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ilil_dataout <= wire_nl0ii00li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iliO_dataout <= wire_nl0ii00ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0illi_dataout <= wire_nl0ii00lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0illl_dataout <= wire_nl0ii00Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0illO_dataout <= wire_nl0ii00Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ilOi_dataout <= wire_nl0ii00OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ilOl_dataout <= wire_nl0ii0i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0ilOO_dataout <= wire_nl0ii0i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iO0i_dataout <= wire_nl0iii0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iO0l_dataout <= wire_nl0iii0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iO0O_dataout <= wire_nl0iii0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iO1i_dataout <= wire_nl0ii0i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iO1l_dataout <= wire_nl0ii0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iO1O_dataout <= wire_nl0ii0i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOii_dataout <= wire_nl0iii0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOil_dataout <= wire_nl0iii0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOiO_dataout <= wire_nl0iii0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOli_dataout <= wire_nl0iiii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOll_dataout <= wire_nl0iiii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOlO_dataout <= wire_nl0iiii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOOi_dataout <= wire_nl0iiii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOOl_dataout <= wire_nl0iiii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0iOOO_dataout <= wire_nl0iiii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l00i_dataout <= wire_nl0iiilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l00l_dataout <= wire_nl0iiilll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l00O_dataout <= wire_nl0iiillO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l01i_dataout <= wire_nl0iiilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l01l_dataout <= wire_nl0iiilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l01O_dataout <= wire_nl0iiiliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0ii_dataout <= wire_nl0iiilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0il_dataout <= wire_nl0iiilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0iO_dataout <= wire_nl0iiilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0li_dataout <= wire_nl0iiiO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0ll_dataout <= wire_nl0iiiO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0lO_dataout <= wire_nl0iiiO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0Oi_dataout <= wire_nl0iiiO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0Ol_dataout <= wire_nl0iiiO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l0OO_dataout <= wire_nl0iiiO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l10i_dataout <= wire_nl0iiiili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l10l_dataout <= wire_nl0iiiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l10O_dataout <= wire_nl0iiiilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l11i_dataout <= wire_nl0iiiiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l11l_dataout <= wire_nl0iiiiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l11O_dataout <= wire_nl0iiiiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1ii_dataout <= wire_nl0iiiiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1il_dataout <= wire_nl0iiiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1iO_dataout <= wire_nl0iiiiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1li_dataout <= wire_nl0iiil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1ll_dataout <= wire_nl0iiil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1lO_dataout <= wire_nl0iiil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1Oi_dataout <= wire_nl0iiil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1Ol_dataout <= wire_nl0iiil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0l1OO_dataout <= wire_nl0iiil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0li0i_dataout <= wire_nl0iiiOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0li0l_dataout <= wire_nl0iiiOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0li0O_dataout <= wire_nl0iiiOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0li1i_dataout <= wire_nl0iiiOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0li1l_dataout <= wire_nl0iiiOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0li1O_dataout <= wire_nl0iiiOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0liii_dataout <= niOO1i10l WHEN nl0i1OOOl = '1' ELSE wire_nl0i0lOiO_dataout; + wire_nl0i0liil_dataout <= niOO1i10O WHEN nl0i1OOOl = '1' ELSE wire_nl0i0lOli_dataout; + wire_nl0i0liiO_dataout <= niOO1i1ii WHEN nl0i1OOOl = '1' ELSE wire_nl0i0lOll_dataout; + wire_nl0i0lili_dataout <= niOO1i1il WHEN nl0i1OOOl = '1' ELSE wire_nl0i0lOlO_dataout; + wire_nl0i0lill_dataout <= niOO1i1iO WHEN nl0i1OOOl = '1' ELSE wire_nl0i0lOOi_dataout; + wire_nl0i0lilO_dataout <= niOO1i1li WHEN nl0i1OOOl = '1' ELSE wire_nl0i0lOOl_dataout; + wire_nl0i0liOi_dataout <= niOO1i1ll WHEN nl0i1OOOl = '1' ELSE wire_nl0i0lOOO_dataout; + wire_nl0i0liOl_dataout <= niOO1i1lO WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O11i_dataout; + wire_nl0i0liOO_dataout <= niOO1i1Oi WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O11l_dataout; + wire_nl0i0ll0i_dataout <= niOO1i01l WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O10O_dataout; + wire_nl0i0ll0l_dataout <= niOO1i01O WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1ii_dataout; + wire_nl0i0ll0O_dataout <= niOO1i00i WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1il_dataout; + wire_nl0i0ll1i_dataout <= niOO1i1Ol WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O11O_dataout; + wire_nl0i0ll1l_dataout <= niOO1i1OO WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O10i_dataout; + wire_nl0i0ll1O_dataout <= niOO1i01i WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O10l_dataout; + wire_nl0i0llii_dataout <= niOO1i00l WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1iO_dataout; + wire_nl0i0llil_dataout <= niOO1i00O WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1li_dataout; + wire_nl0i0lliO_dataout <= niOO1i0ii WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1ll_dataout; + wire_nl0i0llli_dataout <= niOO1i0il WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1lO_dataout; + wire_nl0i0llll_dataout <= niOO1i0iO WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1Oi_dataout; + wire_nl0i0lllO_dataout <= niOO1i0li WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1Ol_dataout; + wire_nl0i0llOi_dataout <= niOO1i0ll WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O1OO_dataout; + wire_nl0i0llOl_dataout <= niOO1i0lO WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O01i_dataout; + wire_nl0i0llOO_dataout <= niOO1i0Oi WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O01l_dataout; + wire_nl0i0lO0i_dataout <= niOO1ii1l WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O00O_dataout; + wire_nl0i0lO0l_dataout <= niOO1ii1O WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O0ii_dataout; + wire_nl0i0lO0O_dataout <= niOO1ii0i WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O0il_dataout; + wire_nl0i0lO1i_dataout <= niOO1i0Ol WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O01O_dataout; + wire_nl0i0lO1l_dataout <= niOO1i0OO WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O00i_dataout; + wire_nl0i0lO1O_dataout <= niOO1ii1i WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O00l_dataout; + wire_nl0i0lOii_dataout <= niOO1ii0l WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O0iO_dataout; + wire_nl0i0lOil_dataout <= niOO1ii0O WHEN nl0i1OOOl = '1' ELSE wire_nl0i0O0li_dataout; + wire_nl0i0lOiO_dataout <= wire_nl0l0l0OO_dataout WHEN nl0i1OOOO = '1' ELSE wire_nl0i0O0ll_dataout; + wire_nl0i0lOli_dataout <= wire_nl0l0li1l_dataout WHEN nl0i1OOOO = '1' ELSE wire_nl0i0O0lO_dataout; + wire_nl0i0lOll_dataout <= wire_nl0l0li0i_dataout WHEN nl0i1OOOO = '1' ELSE wire_nl0i0O0Oi_dataout; + wire_nl0i0lOlO_dataout <= wire_nl0l0li0O_dataout WHEN nl0i1OOOO = '1' ELSE wire_nl0i0O0Ol_dataout; + wire_nl0i0lOOi_dataout <= wire_nl0l0liil_dataout WHEN nl0i1OOOO = '1' ELSE wire_nl0i0O0OO_dataout; + wire_nl0i0lOOl_dataout <= nl0l0liOi WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oi1i_dataout; + wire_nl0i0lOOO_dataout <= nl0l0liOl WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oi1l_dataout; + wire_nl0i0O00i_dataout <= wire_nl0i0Ol0O_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O00l_dataout <= wire_nl0i0Olii_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O00O_dataout <= wire_nl0i0Olil_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O01i_dataout <= wire_nl0i0Ol1O_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O01l_dataout <= wire_nl0i0Ol0i_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O01O_dataout <= wire_nl0i0Ol0l_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O0i_dataout <= wire_nl0ii0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0O0ii_dataout <= wire_nl0i0OliO_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O0il_dataout <= wire_nl0i0Olli_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O0iO_dataout <= wire_nl0i0Olll_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O0l_dataout <= wire_nl0ii0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0O0li_dataout <= wire_nl0i0OllO_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O0ll_dataout <= wire_nli1ii1OO_dataout WHEN nl0i0111i = '1' ELSE nl0i1O1li; + wire_nl0i0O0lO_dataout <= wire_nli1ii01i_dataout WHEN nl0i0111i = '1' ELSE nl0i1OiOi; + wire_nl0i0O0O_dataout <= wire_nl0ii0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0O0Oi_dataout <= wire_nli1ii01l_dataout WHEN nl0i0111i = '1' ELSE nl0i1OiOl; + wire_nl0i0O0Ol_dataout <= wire_nli1ii01O_dataout WHEN nl0i0111i = '1' ELSE nl0i1OiOO; + wire_nl0i0O0OO_dataout <= wire_nli1ii00i_dataout WHEN nl0i0111i = '1' ELSE nl0i1Ol1i; + wire_nl0i0O10i_dataout <= nl0l0ll1O WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oi0O_dataout; + wire_nl0i0O10l_dataout <= nl0l0ll0i WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oiii_dataout; + wire_nl0i0O10O_dataout <= nl0l0ll0l WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oiil_dataout; + wire_nl0i0O11i_dataout <= nl0l0liOO WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oi1O_dataout; + wire_nl0i0O11l_dataout <= nl0l0ll1i WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oi0i_dataout; + wire_nl0i0O11O_dataout <= nl0l0ll1l WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oi0l_dataout; + wire_nl0i0O1ii_dataout <= nl0l0ll0O WHEN nl0i1OOOO = '1' ELSE wire_nl0i0OiiO_dataout; + wire_nl0i0O1il_dataout <= nl0l0llii WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oili_dataout; + wire_nl0i0O1iO_dataout <= nl0l0llil WHEN nl0i1OOOO = '1' ELSE wire_nl0i0Oill_dataout; + wire_nl0i0O1l_dataout <= wire_nl0ii0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0O1li_dataout <= wire_nl0i0OilO_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O1ll_dataout <= wire_nl0i0OiOi_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O1lO_dataout <= wire_nl0i0OiOl_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O1O_dataout <= wire_nl0ii0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0O1Oi_dataout <= wire_nl0i0OiOO_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O1Ol_dataout <= wire_nl0i0Ol1i_dataout AND NOT(nl0i1OOOO); + wire_nl0i0O1OO_dataout <= wire_nl0i0Ol1l_dataout AND NOT(nl0i1OOOO); + wire_nl0i0Oi0i_dataout <= wire_nli1ii0il_dataout WHEN nl0i0111i = '1' ELSE nl0i1Ol0l; + wire_nl0i0Oi0l_dataout <= wire_nli1ii0iO_dataout WHEN nl0i0111i = '1' ELSE nl0i1Ol0O; + wire_nl0i0Oi0O_dataout <= nl0i1Olii AND NOT(nl0i0111i); + wire_nl0i0Oi1i_dataout <= wire_nli1ii00l_dataout WHEN nl0i0111i = '1' ELSE nl0i1Ol1l; + wire_nl0i0Oi1l_dataout <= wire_nli1ii00O_dataout WHEN nl0i0111i = '1' ELSE nl0i1Ol1O; + wire_nl0i0Oi1O_dataout <= wire_nli1ii0ii_dataout WHEN nl0i0111i = '1' ELSE nl0i1Ol0i; + wire_nl0i0Oii_dataout <= wire_nl0ii0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0Oiii_dataout <= nl0i1Olil AND NOT(nl0i0111i); + wire_nl0i0Oiil_dataout <= nl0i1OliO AND NOT(nl0i0111i); + wire_nl0i0OiiO_dataout <= nl0i1Olli AND NOT(nl0i0111i); + wire_nl0i0Oil_dataout <= wire_nl0ii0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0Oili_dataout <= nl0i1Olll AND NOT(nl0i0111i); + wire_nl0i0Oill_dataout <= nl0i1OllO AND NOT(nl0i0111i); + wire_nl0i0OilO_dataout <= nl0i1OlOi AND NOT(nl0i0111i); + wire_nl0i0OiO_dataout <= wire_nl0iii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0OiOi_dataout <= nl0i1OlOl AND NOT(nl0i0111i); + wire_nl0i0OiOl_dataout <= nl0i1OlOO AND NOT(nl0i0111i); + wire_nl0i0OiOO_dataout <= nl0i1OO1i AND NOT(nl0i0111i); + wire_nl0i0Ol0i_dataout <= nl0i1OO0l AND NOT(nl0i0111i); + wire_nl0i0Ol0l_dataout <= nl0i1OO0O AND NOT(nl0i0111i); + wire_nl0i0Ol0O_dataout <= nl0i1OOii AND NOT(nl0i0111i); + wire_nl0i0Ol1i_dataout <= nl0i1OO1l AND NOT(nl0i0111i); + wire_nl0i0Ol1l_dataout <= nl0i1OO1O AND NOT(nl0i0111i); + wire_nl0i0Ol1O_dataout <= nl0i1OO0i AND NOT(nl0i0111i); + wire_nl0i0Oli_dataout <= wire_nl0iii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0Olii_dataout <= nl0i1OOil AND NOT(nl0i0111i); + wire_nl0i0Olil_dataout <= nl0i1OOiO AND NOT(nl0i0111i); + wire_nl0i0OliO_dataout <= nl0i1OOli AND NOT(nl0i0111i); + wire_nl0i0Oll_dataout <= wire_nl0iii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0Olli_dataout <= nl0i1OOll AND NOT(nl0i0111i); + wire_nl0i0Olll_dataout <= nl0i1OOlO AND NOT(nl0i0111i); + wire_nl0i0OllO_dataout <= nl0i1OOOi AND NOT(nl0i0111i); + wire_nl0i0OlO_dataout <= wire_nl0iii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0OlOi_dataout <= wire_nl0ii11OO_dataout AND NOT(nl0ili1ll); + wire_nl0i0OlOl_dataout <= wire_nl0ii101i_dataout AND NOT(nl0ili1ll); + wire_nl0i0OlOO_dataout <= wire_nl0ii101l_dataout AND NOT(nl0ili1ll); + wire_nl0i0OO0i_dataout <= wire_nl0ii100O_dataout AND NOT(nl0ili1ll); + wire_nl0i0OO0l_dataout <= wire_nl0ii10ii_dataout AND NOT(nl0ili1ll); + wire_nl0i0OO0O_dataout <= wire_nl0ii10il_dataout AND NOT(nl0ili1ll); + wire_nl0i0OO1i_dataout <= wire_nl0ii101O_dataout AND NOT(nl0ili1ll); + wire_nl0i0OO1l_dataout <= wire_nl0ii100i_dataout AND NOT(nl0ili1ll); + wire_nl0i0OO1O_dataout <= wire_nl0ii100l_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOi_dataout <= wire_nl0iii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0OOii_dataout <= wire_nl0ii10iO_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOil_dataout <= wire_nl0ii10li_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOiO_dataout <= wire_nl0ii10ll_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOl_dataout <= wire_nl0iii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0OOli_dataout <= wire_nl0ii10lO_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOll_dataout <= wire_nl0ii10Oi_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOlO_dataout <= wire_nl0ii10Ol_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOO_dataout <= wire_nl0iiiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i0OOOi_dataout <= wire_nl0ii10OO_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOOl_dataout <= wire_nl0ii1i1i_dataout AND NOT(nl0ili1ll); + wire_nl0i0OOOO_dataout <= wire_nl0ii1i1l_dataout AND NOT(nl0ili1ll); + wire_nl0i1000i_dataout <= wire_nl0i1il0i_dataout AND NOT(nl0i1li0l); + wire_nl0i1000l_dataout <= wire_nl0i1il0l_dataout AND NOT(nl0i1li0l); + wire_nl0i1000O_dataout <= wire_nl0i1il0O_dataout AND NOT(nl0i1li0l); + wire_nl0i1001i_dataout <= wire_nl0i1il1i_dataout AND NOT(nl0i1li0l); + wire_nl0i1001l_dataout <= wire_nl0i1il1l_dataout AND NOT(nl0i1li0l); + wire_nl0i1001O_dataout <= wire_nl0i1il1O_dataout AND NOT(nl0i1li0l); + wire_nl0i100ii_dataout <= wire_nl0i1ilii_dataout AND NOT(nl0i1li0l); + wire_nl0i100il_dataout <= wire_nl0i1ilil_dataout AND NOT(nl0i1li0l); + wire_nl0i100iO_dataout <= wire_nl0i1iliO_dataout AND NOT(nl0i1li0l); + wire_nl0i100li_dataout <= wire_nl0i1illi_dataout AND NOT(nl0i1li0l); + wire_nl0i100ll_dataout <= wire_nl0i1illl_dataout AND NOT(nl0i1li0l); + wire_nl0i100lO_dataout <= wire_nl0i1illO_dataout AND NOT(nl0i1li0l); + wire_nl0i100O_dataout <= wire_nl0i1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i100Oi_dataout <= wire_nl0i1ilOi_dataout AND NOT(nl0i1li0l); + wire_nl0i100Ol_dataout <= wire_nl0i1ilOl_dataout AND NOT(nl0i1li0l); + wire_nl0i100OO_dataout <= wire_nl0i1ilOO_dataout AND NOT(nl0i1li0l); + wire_nl0i1010i_dataout <= wire_nl0i1ii0i_dataout AND NOT(nl0i1li0l); + wire_nl0i1010l_dataout <= wire_nl0i1ii0l_dataout AND NOT(nl0i1li0l); + wire_nl0i1010O_dataout <= wire_nl0i1ii0O_dataout AND NOT(nl0i1li0l); + wire_nl0i1011i_dataout <= wire_nl0i1ii1i_dataout AND NOT(nl0i1li0l); + wire_nl0i1011l_dataout <= wire_nl0i1ii1l_dataout AND NOT(nl0i1li0l); + wire_nl0i1011O_dataout <= wire_nl0i1ii1O_dataout AND NOT(nl0i1li0l); + wire_nl0i101ii_dataout <= wire_nl0i1iiii_dataout AND NOT(nl0i1li0l); + wire_nl0i101il_dataout <= wire_nl0i1iiil_dataout AND NOT(nl0i1li0l); + wire_nl0i101iO_dataout <= wire_nl0i1iiiO_dataout AND NOT(nl0i1li0l); + wire_nl0i101li_dataout <= wire_nl0i1iili_dataout AND NOT(nl0i1li0l); + wire_nl0i101ll_dataout <= wire_nl0i1iill_dataout AND NOT(nl0i1li0l); + wire_nl0i101lO_dataout <= wire_nl0i1iilO_dataout AND NOT(nl0i1li0l); + wire_nl0i101Oi_dataout <= wire_nl0i1iiOi_dataout AND NOT(nl0i1li0l); + wire_nl0i101Ol_dataout <= wire_nl0i1iiOl_dataout AND NOT(nl0i1li0l); + wire_nl0i101OO_dataout <= wire_nl0i1iiOO_dataout AND NOT(nl0i1li0l); + wire_nl0i10i0i_dataout <= wire_nl0i1iO0i_dataout AND NOT(nl0i1li0l); + wire_nl0i10i0l_dataout <= wire_nl0i1iO0l_dataout AND NOT(nl0i1li0l); + wire_nl0i10i0O_dataout <= wire_nl0i1iO0O_dataout OR nl0i1li0l; + wire_nl0i10i1i_dataout <= wire_nl0i1iO1i_dataout AND NOT(nl0i1li0l); + wire_nl0i10i1l_dataout <= wire_nl0i1iO1l_dataout AND NOT(nl0i1li0l); + wire_nl0i10i1O_dataout <= wire_nl0i1iO1O_dataout AND NOT(nl0i1li0l); + wire_nl0i10ii_dataout <= wire_nl0i1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10iii_dataout <= wire_nl0i1iOii_dataout AND NOT(nl0i1li0l); + wire_nl0i10iil_dataout <= wire_nl0i1iOil_dataout AND NOT(nl0i1li0l); + wire_nl0i10iiO_dataout <= wire_nl0i1iOiO_dataout AND NOT(nl0i1li0l); + wire_nl0i10il_dataout <= wire_nl0i1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10ili_dataout <= wire_nl0i1iOli_dataout OR nl0i1li0l; + wire_nl0i10ill_dataout <= wire_nl0i1iOll_dataout OR nl0i1li0l; + wire_nl0i10ilO_dataout <= wire_nl0i1iOlO_dataout AND NOT(nl0i1li0l); + wire_nl0i10iO_dataout <= wire_nl0i1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10iOi_dataout <= wire_nl0i1iOOi_dataout AND NOT(nl0i1li0l); + wire_nl0i10iOl_dataout <= wire_nl0i1iOOl_dataout AND NOT(nl0i1li0l); + wire_nl0i10iOO_dataout <= wire_nl0i1iOOO_dataout AND NOT(nl0i1li0l); + wire_nl0i10l0i_dataout <= wire_nl0i1l10i_dataout AND NOT(nl0i1li0l); + wire_nl0i10l0l_dataout <= wire_nl0i1l10l_dataout AND NOT(nl0i1li0l); + wire_nl0i10l0O_dataout <= wire_nl0i1l10O_dataout AND NOT(nl0i1li0l); + wire_nl0i10l1i_dataout <= wire_nl0i1l11i_dataout AND NOT(nl0i1li0l); + wire_nl0i10l1l_dataout <= wire_nl0i1l11l_dataout AND NOT(nl0i1li0l); + wire_nl0i10l1O_dataout <= wire_nl0i1l11O_dataout AND NOT(nl0i1li0l); + wire_nl0i10li_dataout <= wire_nl0i1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10lii_dataout <= wire_nl0i1l1ii_dataout AND NOT(nl0i1li0l); + wire_nl0i10lil_dataout <= wire_nl0i1l1il_dataout AND NOT(nl0i1li0l); + wire_nl0i10liO_dataout <= wire_nl0i1l1iO_dataout AND NOT(nl0i1li0l); + wire_nl0i10ll_dataout <= wire_nl0i1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10lli_dataout <= wire_nl0i1l1li_dataout AND NOT(nl0i1li0l); + wire_nl0i10lll_dataout <= wire_nl0i1l1ll_dataout AND NOT(nl0i1li0l); + wire_nl0i10llO_dataout <= wire_nl0i1l1lO_dataout AND NOT(nl0i1li0l); + wire_nl0i10lO_dataout <= wire_nl0i1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10lOi_dataout <= wire_nl0i1l1Oi_dataout AND NOT(nl0i1li0l); + wire_nl0i10lOl_dataout <= wire_nl0i1l1Ol_dataout AND NOT(nl0i1li0l); + wire_nl0i10lOO_dataout <= wire_nl0i1l1OO_dataout AND NOT(nl0i1li0l); + wire_nl0i10O0i_dataout <= wire_nl0i1l00i_dataout AND NOT(nl0i1li0l); + wire_nl0i10O0l_dataout <= wire_nl0i1l00l_dataout AND NOT(nl0i1li0l); + wire_nl0i10O0O_dataout <= wire_nl0i1l00O_dataout AND NOT(nl0i1li0l); + wire_nl0i10O1i_dataout <= wire_nl0i1l01i_dataout AND NOT(nl0i1li0l); + wire_nl0i10O1l_dataout <= wire_nl0i1l01l_dataout AND NOT(nl0i1li0l); + wire_nl0i10O1O_dataout <= wire_nl0i1l01O_dataout AND NOT(nl0i1li0l); + wire_nl0i10Oi_dataout <= wire_nl0i1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10Oii_dataout <= wire_nl0i1l0ii_dataout AND NOT(nl0i1li0l); + wire_nl0i10Oil_dataout <= wire_nl0i1l0il_dataout AND NOT(nl0i1li0l); + wire_nl0i10OiO_dataout <= wire_nl0i1l0iO_dataout AND NOT(nl0i1li0l); + wire_nl0i10Ol_dataout <= wire_nl0i1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10Oli_dataout <= wire_nl0i1l0li_dataout AND NOT(nl0i1li0l); + wire_nl0i10Oll_dataout <= wire_nl0i1l0ll_dataout AND NOT(nl0i1li0l); + wire_nl0i10OlO_dataout <= wire_nl0i1l0lO_dataout AND NOT(nl0i1li0l); + wire_nl0i10OO_dataout <= wire_nl0i1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i10OOi_dataout <= wire_nl0i1l0Oi_dataout OR nl0i1li0l; + wire_nl0i10OOl_dataout <= wire_nl0i1l0Ol_dataout OR nl0i1li0l; + wire_nl0i10OOO_dataout <= wire_nl0i1l0OO_dataout AND NOT(nl0i1li0l); + wire_nl0i1100i_dataout <= wire_nl0i10l0i_dataout AND NOT(nl0i1li0i); + wire_nl0i1100l_dataout <= wire_nl0i10l0l_dataout AND NOT(nl0i1li0i); + wire_nl0i1100O_dataout <= wire_nl0i10l0O_dataout AND NOT(nl0i1li0i); + wire_nl0i1101i_dataout <= wire_nl0i10l1i_dataout AND NOT(nl0i1li0i); + wire_nl0i1101l_dataout <= wire_nl0i10l1l_dataout AND NOT(nl0i1li0i); + wire_nl0i1101O_dataout <= wire_nl0i10l1O_dataout AND NOT(nl0i1li0i); + wire_nl0i110ii_dataout <= wire_nl0i10lii_dataout AND NOT(nl0i1li0i); + wire_nl0i110il_dataout <= wire_nl0i10lil_dataout AND NOT(nl0i1li0i); + wire_nl0i110iO_dataout <= wire_nl0i10liO_dataout AND NOT(nl0i1li0i); + wire_nl0i110li_dataout <= wire_nl0i10lli_dataout AND NOT(nl0i1li0i); + wire_nl0i110ll_dataout <= wire_nl0i10lll_dataout AND NOT(nl0i1li0i); + wire_nl0i110lO_dataout <= wire_nl0i10llO_dataout AND NOT(nl0i1li0i); + wire_nl0i110Oi_dataout <= wire_nl0i10lOi_dataout AND NOT(nl0i1li0i); + wire_nl0i110Ol_dataout <= wire_nl0i10lOl_dataout AND NOT(nl0i1li0i); + wire_nl0i110OO_dataout <= wire_nl0i10lOO_dataout AND NOT(nl0i1li0i); + wire_nl0i1110i_dataout <= wire_nl0i10i0i_dataout AND NOT(nl0i1li0i); + wire_nl0i1110l_dataout <= wire_nl0i10i0l_dataout AND NOT(nl0i1li0i); + wire_nl0i1110O_dataout <= wire_nl0i10i0O_dataout OR nl0i1li0i; + wire_nl0i1111i_dataout <= wire_nl0i10i1i_dataout AND NOT(nl0i1li0i); + wire_nl0i1111l_dataout <= wire_nl0i10i1l_dataout AND NOT(nl0i1li0i); + wire_nl0i1111O_dataout <= wire_nl0i10i1O_dataout AND NOT(nl0i1li0i); + wire_nl0i111ii_dataout <= wire_nl0i10iii_dataout OR nl0i1li0i; + wire_nl0i111il_dataout <= wire_nl0i10iil_dataout AND NOT(nl0i1li0i); + wire_nl0i111iO_dataout <= wire_nl0i10iiO_dataout AND NOT(nl0i1li0i); + wire_nl0i111li_dataout <= wire_nl0i10ili_dataout OR nl0i1li0i; + wire_nl0i111ll_dataout <= wire_nl0i10ill_dataout OR nl0i1li0i; + wire_nl0i111lO_dataout <= wire_nl0i10ilO_dataout AND NOT(nl0i1li0i); + wire_nl0i111Oi_dataout <= wire_nl0i10iOi_dataout AND NOT(nl0i1li0i); + wire_nl0i111Ol_dataout <= wire_nl0i10iOl_dataout AND NOT(nl0i1li0i); + wire_nl0i111OO_dataout <= wire_nl0i10iOO_dataout AND NOT(nl0i1li0i); + wire_nl0i11i0i_dataout <= wire_nl0i10O0i_dataout AND NOT(nl0i1li0i); + wire_nl0i11i0l_dataout <= wire_nl0i10O0l_dataout AND NOT(nl0i1li0i); + wire_nl0i11i0O_dataout <= wire_nl0i10O0O_dataout AND NOT(nl0i1li0i); + wire_nl0i11i1i_dataout <= wire_nl0i10O1i_dataout AND NOT(nl0i1li0i); + wire_nl0i11i1l_dataout <= wire_nl0i10O1l_dataout AND NOT(nl0i1li0i); + wire_nl0i11i1O_dataout <= wire_nl0i10O1O_dataout AND NOT(nl0i1li0i); + wire_nl0i11iii_dataout <= wire_nl0i10Oii_dataout AND NOT(nl0i1li0i); + wire_nl0i11iil_dataout <= wire_nl0i10Oil_dataout AND NOT(nl0i1li0i); + wire_nl0i11iiO_dataout <= wire_nl0i10OiO_dataout AND NOT(nl0i1li0i); + wire_nl0i11ili_dataout <= wire_nl0i10Oli_dataout AND NOT(nl0i1li0i); + wire_nl0i11ill_dataout <= wire_nl0i10Oll_dataout AND NOT(nl0i1li0i); + wire_nl0i11ilO_dataout <= wire_nl0i10OlO_dataout AND NOT(nl0i1li0i); + wire_nl0i11iOi_dataout <= wire_nl0i10OOi_dataout OR nl0i1li0i; + wire_nl0i11iOl_dataout <= wire_nl0i10OOl_dataout OR nl0i1li0i; + wire_nl0i11iOO_dataout <= wire_nl0i10OOO_dataout AND NOT(nl0i1li0i); + wire_nl0i11l0i_dataout <= wire_nl0i1i10i_dataout AND NOT(nl0i1li0l); + wire_nl0i11l0l_dataout <= wire_nl0i1i10l_dataout AND NOT(nl0i1li0l); + wire_nl0i11l0O_dataout <= wire_nl0i1i10O_dataout AND NOT(nl0i1li0l); + wire_nl0i11l1i_dataout <= wire_nl0i1i11i_dataout AND NOT(nl0i1li0i); + wire_nl0i11l1l_dataout <= wire_nl0i1i11l_dataout AND NOT(nl0i1li0l); + wire_nl0i11l1O_dataout <= wire_nl0i1i11O_dataout AND NOT(nl0i1li0l); + wire_nl0i11lii_dataout <= wire_nl0i1i1ii_dataout AND NOT(nl0i1li0l); + wire_nl0i11lil_dataout <= wire_nl0i1i1il_dataout AND NOT(nl0i1li0l); + wire_nl0i11liO_dataout <= wire_nl0i1i1iO_dataout AND NOT(nl0i1li0l); + wire_nl0i11lli_dataout <= wire_nl0i1i1li_dataout AND NOT(nl0i1li0l); + wire_nl0i11lll_dataout <= wire_nl0i1i1ll_dataout AND NOT(nl0i1li0l); + wire_nl0i11llO_dataout <= wire_nl0i1i1lO_dataout AND NOT(nl0i1li0l); + wire_nl0i11lOi_dataout <= wire_nl0i1i1Oi_dataout AND NOT(nl0i1li0l); + wire_nl0i11lOl_dataout <= wire_nl0i1i1Ol_dataout AND NOT(nl0i1li0l); + wire_nl0i11lOO_dataout <= wire_nl0i1i1OO_dataout AND NOT(nl0i1li0l); + wire_nl0i11O0i_dataout <= wire_nl0i1i00i_dataout AND NOT(nl0i1li0l); + wire_nl0i11O0l_dataout <= wire_nl0i1i00l_dataout AND NOT(nl0i1li0l); + wire_nl0i11O0O_dataout <= wire_nl0i1i00O_dataout AND NOT(nl0i1li0l); + wire_nl0i11O1i_dataout <= wire_nl0i1i01i_dataout AND NOT(nl0i1li0l); + wire_nl0i11O1l_dataout <= wire_nl0i1i01l_dataout AND NOT(nl0i1li0l); + wire_nl0i11O1O_dataout <= wire_nl0i1i01O_dataout AND NOT(nl0i1li0l); + wire_nl0i11Oii_dataout <= wire_nl0i1i0ii_dataout AND NOT(nl0i1li0l); + wire_nl0i11Oil_dataout <= wire_nl0i1i0il_dataout AND NOT(nl0i1li0l); + wire_nl0i11OiO_dataout <= wire_nl0i1i0iO_dataout AND NOT(nl0i1li0l); + wire_nl0i11Oli_dataout <= wire_nl0i1i0li_dataout AND NOT(nl0i1li0l); + wire_nl0i11Oll_dataout <= wire_nl0i1i0ll_dataout AND NOT(nl0i1li0l); + wire_nl0i11OlO_dataout <= wire_nl0i1i0lO_dataout AND NOT(nl0i1li0l); + wire_nl0i11OOi_dataout <= wire_nl0i1i0Oi_dataout AND NOT(nl0i1li0l); + wire_nl0i11OOl_dataout <= wire_nl0i1i0Ol_dataout AND NOT(nl0i1li0l); + wire_nl0i11OOO_dataout <= wire_nl0i1i0OO_dataout AND NOT(nl0i1li0l); + wire_nl0i1i00i_dataout <= nl00liili AND NOT(nl0i1li0O); + wire_nl0i1i00l_dataout <= nl00liill AND NOT(nl0i1li0O); + wire_nl0i1i00O_dataout <= nl00liilO AND NOT(nl0i1li0O); + wire_nl0i1i01i_dataout <= nl00liiii AND NOT(nl0i1li0O); + wire_nl0i1i01l_dataout <= nl00liiil AND NOT(nl0i1li0O); + wire_nl0i1i01O_dataout <= nl00liiiO AND NOT(nl0i1li0O); + wire_nl0i1i0i_dataout <= wire_nl0i1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1i0ii_dataout <= nl00liiOi AND NOT(nl0i1li0O); + wire_nl0i1i0il_dataout <= nl00liiOl AND NOT(nl0i1li0O); + wire_nl0i1i0iO_dataout <= nl00liiOO AND NOT(nl0i1li0O); + wire_nl0i1i0l_dataout <= wire_nl0i1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1i0li_dataout <= nl00lil1i AND NOT(nl0i1li0O); + wire_nl0i1i0ll_dataout <= nl00lil1l AND NOT(nl0i1li0O); + wire_nl0i1i0lO_dataout <= nl00lil1O AND NOT(nl0i1li0O); + wire_nl0i1i0O_dataout <= wire_nl0i1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1i0Oi_dataout <= nl00lil0i AND NOT(nl0i1li0O); + wire_nl0i1i0Ol_dataout <= nl00lil0l AND NOT(nl0i1li0O); + wire_nl0i1i0OO_dataout <= nl00lil0O AND NOT(nl0i1li0O); + wire_nl0i1i10i_dataout <= nl00li0li AND NOT(nl0i1li0O); + wire_nl0i1i10l_dataout <= nl00li0ll AND NOT(nl0i1li0O); + wire_nl0i1i10O_dataout <= nl00li0lO AND NOT(nl0i1li0O); + wire_nl0i1i11i_dataout <= wire_nl0i1li1i_dataout AND NOT(nl0i1li0l); + wire_nl0i1i11l_dataout <= nl00li0ii AND NOT(nl0i1li0O); + wire_nl0i1i11O_dataout <= nl00li0iO AND NOT(nl0i1li0O); + wire_nl0i1i1i_dataout <= wire_nl0i1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1i1ii_dataout <= nl00li0Oi AND NOT(nl0i1li0O); + wire_nl0i1i1il_dataout <= nl00li0Ol AND NOT(nl0i1li0O); + wire_nl0i1i1iO_dataout <= nl00li0OO AND NOT(nl0i1li0O); + wire_nl0i1i1l_dataout <= wire_nl0i1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1i1li_dataout <= nl00lii1i AND NOT(nl0i1li0O); + wire_nl0i1i1ll_dataout <= nl00lii1l AND NOT(nl0i1li0O); + wire_nl0i1i1lO_dataout <= nl00lii1O AND NOT(nl0i1li0O); + wire_nl0i1i1O_dataout <= wire_nl0i1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1i1Oi_dataout <= nl00lii0i AND NOT(nl0i1li0O); + wire_nl0i1i1Ol_dataout <= nl00lii0l AND NOT(nl0i1li0O); + wire_nl0i1i1OO_dataout <= nl00lii0O AND NOT(nl0i1li0O); + wire_nl0i1ii0i_dataout <= nl00lilli AND NOT(nl0i1li0O); + wire_nl0i1ii0l_dataout <= nl00lilll AND NOT(nl0i1li0O); + wire_nl0i1ii0O_dataout <= nl00lillO AND NOT(nl0i1li0O); + wire_nl0i1ii1i_dataout <= nl00lilii AND NOT(nl0i1li0O); + wire_nl0i1ii1l_dataout <= nl00lilil AND NOT(nl0i1li0O); + wire_nl0i1ii1O_dataout <= nl00liliO AND NOT(nl0i1li0O); + wire_nl0i1iii_dataout <= wire_nl0i011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1iiii_dataout <= nl00lilOi AND NOT(nl0i1li0O); + wire_nl0i1iiil_dataout <= nl00lilOl AND NOT(nl0i1li0O); + wire_nl0i1iiiO_dataout <= nl00lilOO AND NOT(nl0i1li0O); + wire_nl0i1iil_dataout <= wire_nl0i011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1iili_dataout <= nl00liO1i AND NOT(nl0i1li0O); + wire_nl0i1iill_dataout <= nl00liO1l AND NOT(nl0i1li0O); + wire_nl0i1iilO_dataout <= nl00liO1O AND NOT(nl0i1li0O); + wire_nl0i1iiO_dataout <= wire_nl0i011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1iiOi_dataout <= nl00liO0i AND NOT(nl0i1li0O); + wire_nl0i1iiOl_dataout <= nl00liO0l AND NOT(nl0i1li0O); + wire_nl0i1iiOO_dataout <= nl00liO0O AND NOT(nl0i1li0O); + wire_nl0i1il0i_dataout <= nl00liOli AND NOT(nl0i1li0O); + wire_nl0i1il0l_dataout <= nl00liOll AND NOT(nl0i1li0O); + wire_nl0i1il0O_dataout <= nl00liOlO AND NOT(nl0i1li0O); + wire_nl0i1il1i_dataout <= nl00liOii AND NOT(nl0i1li0O); + wire_nl0i1il1l_dataout <= nl00liOil AND NOT(nl0i1li0O); + wire_nl0i1il1O_dataout <= nl00liOiO AND NOT(nl0i1li0O); + wire_nl0i1ili_dataout <= wire_nl0i010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1ilii_dataout <= nl00liOOi AND NOT(nl0i1li0O); + wire_nl0i1ilil_dataout <= nl00liOOl AND NOT(nl0i1li0O); + wire_nl0i1iliO_dataout <= nl00liOOO AND NOT(nl0i1li0O); + wire_nl0i1ill_dataout <= wire_nl0i010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1illi_dataout <= nl00ll11i AND NOT(nl0i1li0O); + wire_nl0i1illl_dataout <= nl00ll11l AND NOT(nl0i1li0O); + wire_nl0i1illO_dataout <= nl00ll11O AND NOT(nl0i1li0O); + wire_nl0i1ilO_dataout <= wire_nl0i010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1ilOi_dataout <= nl00ll10i AND NOT(nl0i1li0O); + wire_nl0i1ilOl_dataout <= nl00ll10l AND NOT(nl0i1li0O); + wire_nl0i1ilOO_dataout <= nl00ll10O AND NOT(nl0i1li0O); + wire_nl0i1iO0i_dataout <= nl00ll1li AND NOT(nl0i1li0O); + wire_nl0i1iO0l_dataout <= nl00ll1ll AND NOT(nl0i1li0O); + wire_nl0i1iO0O_dataout <= nl00ll1lO AND NOT(nl0i1li0O); + wire_nl0i1iO1i_dataout <= nl00ll1ii AND NOT(nl0i1li0O); + wire_nl0i1iO1l_dataout <= nl00ll1il AND NOT(nl0i1li0O); + wire_nl0i1iO1O_dataout <= nl00ll1iO AND NOT(nl0i1li0O); + wire_nl0i1iOi_dataout <= wire_nl0i01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1iOii_dataout <= nl00ll1Oi AND NOT(nl0i1li0O); + wire_nl0i1iOil_dataout <= nl00ll1Ol AND NOT(nl0i1li0O); + wire_nl0i1iOiO_dataout <= nl00ll1OO AND NOT(nl0i1li0O); + wire_nl0i1iOl_dataout <= wire_nl0i01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1iOli_dataout <= nl00ll01i OR nl0i1li0O; + wire_nl0i1iOll_dataout <= nl00ll01l OR nl0i1li0O; + wire_nl0i1iOlO_dataout <= nl00ll01O AND NOT(nl0i1li0O); + wire_nl0i1iOO_dataout <= wire_nl0i01iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1iOOi_dataout <= nl00ll00i AND NOT(nl0i1li0O); + wire_nl0i1iOOl_dataout <= nl00ll00l AND NOT(nl0i1li0O); + wire_nl0i1iOOO_dataout <= nl00ll00O AND NOT(nl0i1li0O); + wire_nl0i1l00i_dataout <= nl00llili AND NOT(nl0i1li0O); + wire_nl0i1l00l_dataout <= nl00llill AND NOT(nl0i1li0O); + wire_nl0i1l00O_dataout <= nl00llilO AND NOT(nl0i1li0O); + wire_nl0i1l01i_dataout <= nl00lliii AND NOT(nl0i1li0O); + wire_nl0i1l01l_dataout <= nl00lliil AND NOT(nl0i1li0O); + wire_nl0i1l01O_dataout <= nl00lliiO AND NOT(nl0i1li0O); + wire_nl0i1l0i_dataout <= wire_nl0i01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1l0ii_dataout <= nl00lliOi AND NOT(nl0i1li0O); + wire_nl0i1l0il_dataout <= nl00lliOl AND NOT(nl0i1li0O); + wire_nl0i1l0iO_dataout <= nl00lliOO AND NOT(nl0i1li0O); + wire_nl0i1l0l_dataout <= wire_nl0i01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1l0li_dataout <= nl00lll1i AND NOT(nl0i1li0O); + wire_nl0i1l0ll_dataout <= nl00lll1l AND NOT(nl0i1li0O); + wire_nl0i1l0lO_dataout <= nl00lll1O AND NOT(nl0i1li0O); + wire_nl0i1l0O_dataout <= wire_nl0i01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1l0Oi_dataout <= nl00lll0i OR nl0i1li0O; + wire_nl0i1l0Ol_dataout <= nl00lll0l OR nl0i1li0O; + wire_nl0i1l0OO_dataout <= nl00lll0O AND NOT(nl0i1li0O); + wire_nl0i1l10i_dataout <= nl00ll0li AND NOT(nl0i1li0O); + wire_nl0i1l10l_dataout <= nl00ll0ll AND NOT(nl0i1li0O); + wire_nl0i1l10O_dataout <= nl00ll0lO AND NOT(nl0i1li0O); + wire_nl0i1l11i_dataout <= nl00ll0ii AND NOT(nl0i1li0O); + wire_nl0i1l11l_dataout <= nl00ll0il AND NOT(nl0i1li0O); + wire_nl0i1l11O_dataout <= nl00ll0iO AND NOT(nl0i1li0O); + wire_nl0i1l1i_dataout <= wire_nl0i01li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1l1ii_dataout <= nl00ll0Oi AND NOT(nl0i1li0O); + wire_nl0i1l1il_dataout <= nl00ll0Ol AND NOT(nl0i1li0O); + wire_nl0i1l1iO_dataout <= nl00ll0OO AND NOT(nl0i1li0O); + wire_nl0i1l1l_dataout <= wire_nl0i01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1l1li_dataout <= nl00lli1i AND NOT(nl0i1li0O); + wire_nl0i1l1ll_dataout <= nl00lli1l AND NOT(nl0i1li0O); + wire_nl0i1l1lO_dataout <= nl00lli1O AND NOT(nl0i1li0O); + wire_nl0i1l1O_dataout <= wire_nl0i01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1l1Oi_dataout <= nl00lli0i AND NOT(nl0i1li0O); + wire_nl0i1l1Ol_dataout <= nl00lli0l AND NOT(nl0i1li0O); + wire_nl0i1l1OO_dataout <= nl00lli0O AND NOT(nl0i1li0O); + wire_nl0i1li1i_dataout <= nl00lllii AND NOT(nl0i1li0O); + wire_nl0i1lii_dataout <= wire_nl0i001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1lil_dataout <= wire_nl0i001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1lili_dataout <= wire_nl0i1ll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1lill_dataout <= wire_nl0i1ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1lilO_dataout <= wire_nl0i1ll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1liO_dataout <= wire_nl0i001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1liOi_dataout <= wire_nl0i1ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1liOl_dataout <= wire_nl0i1ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1liOO_dataout <= wire_nl0i1lO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1ll0i_dataout <= wire_nl0i1llil_dataout AND wire_nlill0Oll_w_lg_nl0i1liil52078w(0); + wire_nl0i1ll0l_dataout <= wire_nl0i1lliO_dataout AND wire_nlill0Oll_w_lg_nl0i1liil52078w(0); + wire_nl0i1ll0O_dataout <= wire_nl0i1llli_dataout AND wire_nlill0Oll_w_lg_nl0i1liil52078w(0); + wire_nl0i1ll1i_dataout <= wire_nl0i1lO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1ll1l_dataout <= wire_nl0i1lOlO_dataout AND wire_nlill0Oll_w_lg_nl0i1liil52078w(0); + wire_nl0i1ll1O_dataout <= wire_nl0i1llii_dataout AND wire_nlill0Oll_w_lg_nl0i1liil52078w(0); + wire_nl0i1lli_dataout <= wire_nl0i000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1llii_dataout <= wire_nl0i1lOll_dataout AND NOT(wire_nl0i1lOlO_dataout); + wire_nl0i1llil_dataout <= wire_nl0i1llll_dataout AND NOT(wire_nl0i1lOlO_dataout); + wire_nl0i1lliO_dataout <= wire_nl0i1lllO_dataout AND NOT(wire_nl0i1lOlO_dataout); + wire_nl0i1lll_dataout <= wire_nl0i000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1llli_dataout <= wire_nl0i1llOi_dataout AND NOT(wire_nl0i1lOlO_dataout); + wire_nl0i1llll_dataout <= wire_nl0i1lOli_dataout AND NOT(wire_nl0i1lOll_dataout); + wire_nl0i1lllO_dataout <= wire_nl0i1llOl_dataout AND NOT(wire_nl0i1lOll_dataout); + wire_nl0i1llO_dataout <= wire_nl0i000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1llOi_dataout <= wire_nl0i1llOO_dataout AND NOT(wire_nl0i1lOll_dataout); + wire_nl0i1llOl_dataout <= wire_nl0i1lOiO_dataout AND NOT(wire_nl0i1lOli_dataout); + wire_nl0i1llOO_dataout <= wire_nl0i1lO1i_dataout AND NOT(wire_nl0i1lOli_dataout); + wire_nl0i1lO0l_dataout <= wire_nl0i1lO0O_dataout OR (wire_nlill0Oll_w_lg_nl0i1liil52078w(0) AND wire_w_lg_niOi0O11l52275w(0)); + wire_nl0i1lO0O_dataout <= nl0i1liil AND NOT(nl1Ol011O); + wire_nl0i1lO1i_dataout <= wire_nl0i1lOil_dataout AND NOT(wire_nl0i1lOiO_dataout); + wire_nl0i1lO1l_dataout <= wire_nl0i1lO1O_dataout OR (nl0i1liil AND wire_nlill0Oll_w_lg_nl0i1liii52277w(0)); + wire_nl0i1lO1O_dataout <= nl0i1liii AND NOT(nl1Ol011O); + wire_nl0i1lOi_dataout <= wire_nl0i00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1lOil_dataout <= nlililOii AND niOi0Olii; + wire_nl0i1lOil_w_lg_dataout52607w(0) <= NOT wire_nl0i1lOil_dataout; + wire_nl0i1lOiO_dataout <= nlililOil AND niOi0Olii; + wire_nl0i1lOiO_w_lg_dataout52605w(0) <= NOT wire_nl0i1lOiO_dataout; + wire_nl0i1lOl_dataout <= wire_nl1000i_w_lg_nl00Olll7232w(0) WHEN (wire_w_lg_niOO1lOll7231w(0) AND wire_w_lg_niOO1lOli7233w(0)) = '1' ELSE nl00Olll; + wire_nl0i1lOli_dataout <= nlililOiO AND niOi0Olii; + wire_nl0i1lOli_w_lg_dataout52603w(0) <= NOT wire_nl0i1lOli_dataout; + wire_nl0i1lOll_dataout <= nl0l0i0li AND wire_w_lg_niOii1OOl52072w(0); + wire_nl0i1lOll_w_lg_dataout52601w(0) <= NOT wire_nl0i1lOll_dataout; + wire_nl0i1lOlO_dataout <= niOii1liO AND wire_w_lg_niOii1OOl52072w(0); + wire_nl0i1lOlO_w_lg_dataout52600w(0) <= NOT wire_nl0i1lOlO_dataout; + wire_nl0i1O00i_dataout <= wire_nl0i1O00l_dataout OR (wire_nlill0Oll_w_lg_nl0l0100i52257w(0) AND niOi0O11O); + wire_nl0i1O00l_dataout <= nl0i1O11i AND NOT((wire_niO1110l_w_lg_dataout44125w(0) OR (nl0l0100i AND niOi0O11O))); + wire_nl0i1O01i_dataout <= wire_nl0i1O0li_dataout WHEN wire_w_lg_niOii1OOl52072w(0) = '1' ELSE nl0i1O1ii; + wire_nl0i1O01l_dataout <= wire_nl0i1Oi1i_dataout WHEN wire_w_lg_niOii1OOl52072w(0) = '1' ELSE nl0i1O1il; + wire_nl0i1O01O_dataout <= wire_nl0i1Oiii_dataout WHEN wire_w_lg_niOii1OOl52072w(0) = '1' ELSE nl0i1O1iO; + wire_nl0i1O0i_dataout <= nl0i00Oi WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OO1l; + wire_nl0i1O0l_dataout <= nl0i00Ol WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OO1O; + wire_nl0i1O0li_dataout <= wire_nl0i1O0ll_dataout OR (wire_nlill0Oll_w_lg_nl0l0100i52257w(0) AND niOi0O10i); + wire_nl0i1O0ll_dataout <= nl0i1O1ii AND NOT((wire_niO1110l_w_lg_dataout44125w(0) OR (nl0l0100i AND niOi0O10i))); + wire_nl0i1O0O_dataout <= nl0i00OO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OO0i; + wire_nl0i1O10i_dataout <= nl0i1O1ii AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O10l_dataout <= nl0i1O11i AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O11l_dataout <= (nl0i1O1iO OR wire_nl0l0i1iO_dataout) AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O11O_dataout <= nl0i1O1il AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O1i_dataout <= nl0i00li WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OlOl; + wire_nl0i1O1l_dataout <= nl0i00ll WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OlOO; + wire_nl0i1O1ll_dataout <= wire_nl0i1O1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O1lO_dataout <= wire_nl0i1O01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O1O_dataout <= nl0i00lO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OO1i; + wire_nl0i1O1Oi_dataout <= wire_nl0i1O01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O1Ol_dataout <= wire_nl0i1O01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0i1O1OO_dataout <= wire_nl0i1O00i_dataout WHEN wire_w_lg_niOii1OOl52072w(0) = '1' ELSE nl0i1O11i; + wire_nl0i1Oi1i_dataout <= wire_nl0i1Oi1l_dataout OR (wire_nlill0Oll_w_lg_nl0l0100i52257w(0) AND niOi0O10l); + wire_nl0i1Oi1l_dataout <= nl0i1O1il AND NOT((wire_niO1110l_w_lg_dataout44125w(0) OR (nl0l0100i AND niOi0O10l))); + wire_nl0i1Oii_dataout <= nl0i0i1i WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OO0l; + wire_nl0i1Oiii_dataout <= wire_nl0i1Oiil_dataout OR (wire_nlill0Oll_w_lg_nl0l0100i52257w(0) AND niOi0O10O); + wire_nl0i1Oiil_dataout <= nl0i1O1iO AND NOT((wire_niO1110l_w_lg_dataout44125w(0) OR (nl0l0100i AND niOi0O10O))); + wire_nl0i1Oil_dataout <= nl0i0i1l WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OO0O; + wire_nl0i1OiO_dataout <= nl0i0i1O WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOii; + wire_nl0i1Oli_dataout <= nl0i0i0i WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOil; + wire_nl0i1Oll_dataout <= nl0i0i0l WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOiO; + wire_nl0i1OlO_dataout <= nl0i0i0O WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOli; + wire_nl0i1OOi_dataout <= nl0i0iii WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOll; + wire_nl0i1OOl_dataout <= nl0i0iil WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOlO; + wire_nl0i1OOO_dataout <= nl0i0iiO WHEN wire_w_lg_niOO1lOll7231w(0) = '1' ELSE nl00OOOi; + wire_nl0ii000i_dataout <= wire_nl1lOO01O_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0l0O_dataout; + wire_nl0ii000l_dataout <= wire_nl1lOO00i_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0lii_dataout; + wire_nl0ii000O_dataout <= wire_nl1lOO00l_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0lil_dataout; + wire_nl0ii001i_dataout <= wire_nl1lOO1OO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0l1O_dataout; + wire_nl0ii001l_dataout <= wire_nl1lOO01i_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0l0i_dataout; + wire_nl0ii001O_dataout <= wire_nl1lOO01l_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0l0l_dataout; + wire_nl0ii00i_dataout <= wire_nl0iilll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii00ii_dataout <= wire_nl1lOO00O_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0liO_dataout; + wire_nl0ii00il_dataout <= wire_nl1lOO0ii_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0lli_dataout; + wire_nl0ii00iO_dataout <= wire_nl1lOO0il_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0lll_dataout; + wire_nl0ii00l_dataout <= wire_nl0iillO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii00li_dataout <= wire_nl1lOO0iO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0llO_dataout; + wire_nl0ii00ll_dataout <= wire_nl1lOO0li_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0lOi_dataout; + wire_nl0ii00lO_dataout <= wire_nl1lOO0ll_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0lOl_dataout; + wire_nl0ii00O_dataout <= wire_nl0iilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii00Oi_dataout <= wire_nl1lOO0lO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0lOO_dataout; + wire_nl0ii00Ol_dataout <= wire_nl1lOO0Oi_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0O1i_dataout; + wire_nl0ii00OO_dataout <= wire_nl1lOO0Ol_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0O1l_dataout; + wire_nl0ii010i_dataout <= wire_nl0ili00l_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0i0O_dataout; + wire_nl0ii010l_dataout <= wire_nl0ili00O_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0iii_dataout; + wire_nl0ii010O_dataout <= wire_nl0ili0ii_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0iil_dataout; + wire_nl0ii011i_dataout <= nl0i01i1i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii011l_dataout <= nl0i01i1l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii011O_dataout <= nl0i01i1O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii01i_dataout <= wire_nl0iilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii01ii_dataout <= wire_nl0ili0il_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0iiO_dataout; + wire_nl0ii01il_dataout <= wire_nl0ili0iO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0ili_dataout; + wire_nl0ii01iO_dataout <= wire_nl0ili0li_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0ill_dataout; + wire_nl0ii01l_dataout <= wire_nl0iiliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii01li_dataout <= wire_nl0ili0ll_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0ilO_dataout; + wire_nl0ii01ll_dataout <= wire_nl0ii0iOi_dataout AND NOT(nl0ili1ll); + wire_nl0ii01lO_dataout <= wire_nl1lOO1ll_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0iOl_dataout; + wire_nl0ii01O_dataout <= wire_nl0iilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii01Oi_dataout <= wire_nl1lOO1lO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0iOO_dataout; + wire_nl0ii01Ol_dataout <= wire_nl1lOO1Oi_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0l1i_dataout; + wire_nl0ii01OO_dataout <= wire_nl1lOO1Ol_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0l1l_dataout; + wire_nl0ii0i0i_dataout <= wire_nl1lOOi1O_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0O0O_dataout; + wire_nl0ii0i0l_dataout <= wire_nl1lOOi0i_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0Oii_dataout; + wire_nl0ii0i0O_dataout <= wire_nl0il0liO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0Oil_dataout; + wire_nl0ii0i1i_dataout <= wire_nl1lOO0OO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0O1O_dataout; + wire_nl0ii0i1l_dataout <= wire_nl1lOOi1i_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0O0i_dataout; + wire_nl0ii0i1O_dataout <= wire_nl1lOOi1l_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0ii0O0l_dataout; + wire_nl0ii0ii_dataout <= wire_nl0iilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii0iii_dataout <= wire_nl0il0lli_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0OiO_dataout; + wire_nl0ii0iil_dataout <= wire_nl0il0lll_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0Oli_dataout; + wire_nl0ii0iiO_dataout <= wire_nl0il0llO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0Oll_dataout; + wire_nl0ii0il_dataout <= wire_nl0iilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii0ili_dataout <= wire_nl0il0lOi_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0OlO_dataout; + wire_nl0ii0ill_dataout <= wire_nl0il0lOl_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0OOi_dataout; + wire_nl0ii0ilO_dataout <= wire_nl0il0lOO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0OOl_dataout; + wire_nl0ii0iO_dataout <= wire_nl1000i_w_lg_nl0iiO1i7228w(0) WHEN nl0iiO1O = '1' ELSE nl0iiO1i; + wire_nl0ii0iOi_dataout <= wire_nl0il0O1i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii0OOO_dataout; + wire_nl0ii0iOl_dataout <= wire_nl0il0O1l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii11i_dataout; + wire_nl0ii0iOO_dataout <= wire_nl0il0O1O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii11l_dataout; + wire_nl0ii0l0i_dataout <= wire_nl0il0Oii_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii10O_dataout; + wire_nl0ii0l0l_dataout <= wire_nl0il0Oil_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1ii_dataout; + wire_nl0ii0l0O_dataout <= wire_nl0il0OiO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1il_dataout; + wire_nl0ii0l1i_dataout <= wire_nl0il0O0i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii11O_dataout; + wire_nl0ii0l1l_dataout <= wire_nl0il0O0l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii10i_dataout; + wire_nl0ii0l1O_dataout <= wire_nl0il0O0O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii10l_dataout; + wire_nl0ii0li_dataout <= nl0i00li AND NOT(nl0iiO1O); + wire_nl0ii0lii_dataout <= wire_nl0il0Oli_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1iO_dataout; + wire_nl0ii0lil_dataout <= wire_nl0il0Oll_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1li_dataout; + wire_nl0ii0liO_dataout <= wire_nl0il0OlO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1ll_dataout; + wire_nl0ii0ll_dataout <= nl0i00ll AND NOT(nl0iiO1O); + wire_nl0ii0lli_dataout <= wire_nl0il0OOi_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1lO_dataout; + wire_nl0ii0lll_dataout <= wire_nl0il0OOl_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1Oi_dataout; + wire_nl0ii0llO_dataout <= wire_nl0il0OOO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1Ol_dataout; + wire_nl0ii0lO_dataout <= nl0i00lO AND NOT(nl0iiO1O); + wire_nl0ii0lOi_dataout <= wire_nl0ili11i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii1OO_dataout; + wire_nl0ii0lOl_dataout <= wire_nl0ili11l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii01i_dataout; + wire_nl0ii0lOO_dataout <= wire_nl0ili11O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii01l_dataout; + wire_nl0ii0O0i_dataout <= wire_nl0ili1ii_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii00O_dataout; + wire_nl0ii0O0l_dataout <= wire_nl0ili1il_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii0ii_dataout; + wire_nl0ii0O0O_dataout <= wire_nl0ili1iO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii0il_dataout; + wire_nl0ii0O1i_dataout <= wire_nl0ili10i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii01O_dataout; + wire_nl0ii0O1l_dataout <= wire_nl0ili10l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii00i_dataout; + wire_nl0ii0O1O_dataout <= wire_nl0ili10O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii00l_dataout; + wire_nl0ii0Oi_dataout <= nl0i00Oi AND NOT(nl0iiO1O); + wire_nl0ii0Oii_dataout <= wire_nl0ili1li_dataout WHEN nl0illl0i = '1' ELSE wire_nl0iii0iO_dataout; + wire_nl0ii0Oil_dataout <= nl0i01i0i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii0OiO_dataout <= nl0i01i0l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii0Ol_dataout <= nl0i00Ol AND NOT(nl0iiO1O); + wire_nl0ii0Oli_dataout <= nl0i01i0O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii0Oll_dataout <= nl0i01iii AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii0OlO_dataout <= nl0i01iil AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii0OO_dataout <= nl0i00OO AND NOT(nl0iiO1O); + wire_nl0ii0OOi_dataout <= nl0i01iiO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii0OOl_dataout <= nl0i01ili AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii0OOO_dataout <= nl0i01ill AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii100i_dataout <= wire_nl0il00ll_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1l0O_dataout; + wire_nl0ii100l_dataout <= wire_nl0il00lO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1lii_dataout; + wire_nl0ii100O_dataout <= wire_nl0il00Oi_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1lil_dataout; + wire_nl0ii101i_dataout <= wire_nl0ii1l1O_dataout AND NOT(nl0illl0i); + wire_nl0ii101l_dataout <= wire_nl0il00iO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1l0i_dataout; + wire_nl0ii101O_dataout <= wire_nl0il00li_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1l0l_dataout; + wire_nl0ii10i_dataout <= wire_nl0iiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii10ii_dataout <= wire_nl0il00Ol_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1liO_dataout; + wire_nl0ii10il_dataout <= wire_nl0il00OO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1lli_dataout; + wire_nl0ii10iO_dataout <= wire_nl0il0i1i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1lll_dataout; + wire_nl0ii10l_dataout <= wire_nl0iiilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii10li_dataout <= wire_nl0il0i1l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1llO_dataout; + wire_nl0ii10ll_dataout <= wire_nl0il0i1O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1lOi_dataout; + wire_nl0ii10lO_dataout <= wire_nl0il0i0i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1lOl_dataout; + wire_nl0ii10O_dataout <= wire_nl0iiiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii10Oi_dataout <= wire_nl0il0i0l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1lOO_dataout; + wire_nl0ii10Ol_dataout <= wire_nl0il0i0O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1O1i_dataout; + wire_nl0ii10OO_dataout <= wire_nl0il0iii_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1O1l_dataout; + wire_nl0ii110i_dataout <= wire_nl0ii1i0O_dataout AND NOT(nl0ili1ll); + wire_nl0ii110l_dataout <= wire_nl0ii1iii_dataout AND NOT(nl0ili1ll); + wire_nl0ii110O_dataout <= wire_nl0ii1iil_dataout AND NOT(nl0ili1ll); + wire_nl0ii111i_dataout <= wire_nl0ii1i1O_dataout AND NOT(nl0ili1ll); + wire_nl0ii111l_dataout <= wire_nl0ii1i0i_dataout AND NOT(nl0ili1ll); + wire_nl0ii111O_dataout <= wire_nl0ii1i0l_dataout AND NOT(nl0ili1ll); + wire_nl0ii11i_dataout <= wire_nl0iiiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii11ii_dataout <= wire_nl0ii1iiO_dataout AND NOT(nl0ili1ll); + wire_nl0ii11il_dataout <= wire_nl0ii1ili_dataout AND NOT(nl0ili1ll); + wire_nl0ii11iO_dataout <= wire_nl0ii1ill_dataout AND NOT(nl0ili1ll); + wire_nl0ii11l_dataout <= wire_nl0iiiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii11li_dataout <= wire_nl0ii1ilO_dataout AND NOT(nl0ili1ll); + wire_nl0ii11ll_dataout <= wire_nl0ii1iOi_dataout AND NOT(nl0ili1ll); + wire_nl0ii11lO_dataout <= wire_nl0ii1iOl_dataout AND NOT(nl0ili1ll); + wire_nl0ii11O_dataout <= wire_nl0iiili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii11Oi_dataout <= wire_nl0ii1iOO_dataout AND NOT(nl0ili1ll); + wire_nl0ii11Ol_dataout <= wire_nl0ii1l1i_dataout AND NOT(nl0ili1ll); + wire_nl0ii11OO_dataout <= wire_nl0ii1l1l_dataout AND NOT(nl0illl0i); + wire_nl0ii1i0i_dataout <= wire_nl0il0ill_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1O0O_dataout; + wire_nl0ii1i0l_dataout <= wire_nl0il0ilO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1Oii_dataout; + wire_nl0ii1i0O_dataout <= wire_nl0il0iOi_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1Oil_dataout; + wire_nl0ii1i1i_dataout <= wire_nl0il0iil_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1O1O_dataout; + wire_nl0ii1i1l_dataout <= wire_nl0il0iiO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1O0i_dataout; + wire_nl0ii1i1O_dataout <= wire_nl0il0ili_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1O0l_dataout; + wire_nl0ii1ii_dataout <= wire_nl0iiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1iii_dataout <= wire_nl0il0iOl_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1OiO_dataout; + wire_nl0ii1iil_dataout <= wire_nl0il0iOO_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1Oli_dataout; + wire_nl0ii1iiO_dataout <= wire_nl0il0l1i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1Oll_dataout; + wire_nl0ii1il_dataout <= wire_nl0iiiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1ili_dataout <= wire_nl0il0l1l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1OlO_dataout; + wire_nl0ii1ill_dataout <= wire_nl0il0l1O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1OOi_dataout; + wire_nl0ii1ilO_dataout <= wire_nl0il0l0i_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1OOl_dataout; + wire_nl0ii1iO_dataout <= wire_nl0iil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1iOi_dataout <= wire_nl0il0l0l_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii1OOO_dataout; + wire_nl0ii1iOl_dataout <= wire_nl0il0l0O_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii011i_dataout; + wire_nl0ii1iOO_dataout <= wire_nl0il0lii_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii011l_dataout; + wire_nl0ii1l0i_dataout <= nl0i0110i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1l0l_dataout <= nl0i0110l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1l0O_dataout <= nl0i0110O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1l1i_dataout <= wire_nl0il0lil_dataout WHEN nl0illl0i = '1' ELSE wire_nl0ii011O_dataout; + wire_nl0ii1l1l_dataout <= nl0i0111l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1l1O_dataout <= nl0i0111O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1li_dataout <= wire_nl0iil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1lii_dataout <= nl0i011ii AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1lil_dataout <= nl0i011il AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1liO_dataout <= nl0i011iO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1ll_dataout <= wire_nl0iil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1lli_dataout <= nl0i011li AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1lll_dataout <= nl0i011ll AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1llO_dataout <= nl0i011lO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1lO_dataout <= wire_nl0iil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1lOi_dataout <= nl0i011Oi AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1lOl_dataout <= nl0i011Ol AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1lOO_dataout <= nl0i011OO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1O0i_dataout <= nl0i0100i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1O0l_dataout <= nl0i0100l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1O0O_dataout <= nl0i0100O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1O1i_dataout <= nl0i0101i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1O1l_dataout <= nl0i0101l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1O1O_dataout <= nl0i0101O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1Oi_dataout <= wire_nl0iil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1Oii_dataout <= nl0i010ii AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1Oil_dataout <= nl0i010il AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1OiO_dataout <= nl0i010iO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1Ol_dataout <= wire_nl0iil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1Oli_dataout <= nl0i010li AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1Oll_dataout <= nl0i010ll AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1OlO_dataout <= nl0i010lO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1OO_dataout <= wire_nl0iilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ii1OOi_dataout <= nl0i010Oi AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1OOl_dataout <= nl0i010Ol AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0ii1OOO_dataout <= nl0i010OO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii00i_dataout <= nl0i01lOO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii00l_dataout <= nl0i01O1i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii00O_dataout <= nl0i01O1l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii01i_dataout <= nl0i01llO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii01l_dataout <= nl0i01lOi AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii01O_dataout <= nl0i01lOl AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii0i_dataout <= nl0i0i0i AND NOT(nl0iiO1O); + wire_nl0iii0ii_dataout <= nl0i01O1O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii0il_dataout <= nl0i01O0i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii0iO_dataout <= nl0i01O0l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii0l_dataout <= nl0i0i0l AND NOT(nl0iiO1O); + wire_nl0iii0li_dataout <= wire_nl0iliiil_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iiiOOi_dataout; + wire_nl0iii0ll_dataout <= wire_nl0iliiiO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iiiOOl_dataout; + wire_nl0iii0lO_dataout <= wire_nl0iliili_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iiiOOO_dataout; + wire_nl0iii0O_dataout <= nl0i0i0O AND NOT(nl0iiO1O); + wire_nl0iii0Oi_dataout <= wire_nl0iliill_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil11i_dataout; + wire_nl0iii0Ol_dataout <= wire_nl0iliilO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil11l_dataout; + wire_nl0iii0OO_dataout <= wire_nl0iliiOi_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil11O_dataout; + wire_nl0iii10i_dataout <= nl0i01iOO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii10l_dataout <= nl0i01l1i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii10O_dataout <= nl0i01l1l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii11i_dataout <= nl0i01ilO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii11l_dataout <= nl0i01iOi AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii11O_dataout <= nl0i01iOl AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1i_dataout <= nl0i0i1i AND NOT(nl0iiO1O); + wire_nl0iii1ii_dataout <= nl0i01l1O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1il_dataout <= nl0i01l0i AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1iO_dataout <= nl0i01l0l AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1l_dataout <= nl0i0i1l AND NOT(nl0iiO1O); + wire_nl0iii1li_dataout <= nl0i01l0O AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1ll_dataout <= nl0i01lii AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1lO_dataout <= nl0i01lil AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1O_dataout <= nl0i0i1O AND NOT(nl0iiO1O); + wire_nl0iii1Oi_dataout <= nl0i01liO AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1Ol_dataout <= nl0i01lli AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iii1OO_dataout <= nl0i01lll AND NOT(wire_w_lg_niOi0O1ii52250w(0)); + wire_nl0iiii0i_dataout <= wire_nl0ilil1l_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil1ii_dataout; + wire_nl0iiii0l_dataout <= wire_nl0ilil1O_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil1il_dataout; + wire_nl0iiii0O_dataout <= wire_nl0ilil0i_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil1iO_dataout; + wire_nl0iiii1i_dataout <= wire_nl0iliiOl_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil10i_dataout; + wire_nl0iiii1l_dataout <= wire_nl0iliiOO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil10l_dataout; + wire_nl0iiii1O_dataout <= wire_nl0ilil1i_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil10O_dataout; + wire_nl0iiiii_dataout <= nl0i0iii AND NOT(nl0iiO1O); + wire_nl0iiiiii_dataout <= wire_nl0iil1li_dataout AND NOT(nl0ili1ll); + wire_nl0iiiiil_dataout <= wire_nl0ili01l_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil1ll_dataout; + wire_nl0iiiiiO_dataout <= wire_nl0iil1lO_dataout AND NOT(nl0ili1ll); + wire_nl0iiiil_dataout <= nl0i0iil AND NOT(nl0iiO1O); + wire_nl0iiiili_dataout <= niOi0O1Oi WHEN nl0ili1ll = '1' ELSE wire_nl0iil1Oi_dataout; + wire_nl0iiiill_dataout <= wire_w_lg_niOi0O1lO52249w(0) WHEN nl0ili1ll = '1' ELSE wire_nl0iil1Ol_dataout; + wire_nl0iiiilO_dataout <= wire_nl0iil1OO_dataout AND NOT(nl0ili1ll); + wire_nl0iiiiO_dataout <= nl0i0iiO AND NOT(nl0iiO1O); + wire_nl0iiiiOi_dataout <= wire_nl0iil01i_dataout AND NOT(nl0ili1ll); + wire_nl0iiiiOl_dataout <= wire_nl0iil01l_dataout AND NOT(nl0ili1ll); + wire_nl0iiiiOO_dataout <= wire_nl0iil01O_dataout AND NOT(nl0ili1ll); + wire_nl0iiil0i_dataout <= wire_nl0iil0ii_dataout AND NOT(nl0ili1ll); + wire_nl0iiil0l_dataout <= wire_nl0iil0il_dataout AND NOT(nl0ili1ll); + wire_nl0iiil0O_dataout <= wire_nl0iil0iO_dataout AND NOT(nl0ili1ll); + wire_nl0iiil1i_dataout <= wire_nl0iil00i_dataout AND NOT(nl0ili1ll); + wire_nl0iiil1l_dataout <= wire_nl0iil00l_dataout AND NOT(nl0ili1ll); + wire_nl0iiil1O_dataout <= wire_nl0iil00O_dataout AND NOT(nl0ili1ll); + wire_nl0iiili_dataout <= nl0i0ili AND NOT(nl0iiO1O); + wire_nl0iiilii_dataout <= wire_nl0iil0li_dataout AND NOT(nl0ili1ll); + wire_nl0iiilil_dataout <= wire_nl1lOOl1l_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil0ll_dataout; + wire_nl0iiiliO_dataout <= wire_nl1lOOl1O_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iil0lO_dataout; + wire_nl0iiill_dataout <= nl0i0ill AND NOT(nl0iiO1O); + wire_nl0iiilli_dataout <= wire_nl0iil0Oi_dataout AND NOT(nl0ili1ll); + wire_nl0iiilll_dataout <= nliiO11OO WHEN nl0ili1ll = '1' ELSE wire_nl0iil0Ol_dataout; + wire_nl0iiillO_dataout <= wire_nl0iil0OO_dataout AND NOT(nl0ili1ll); + wire_nl0iiilO_dataout <= nl0i0ilO AND NOT(nl0iiO1O); + wire_nl0iiilOi_dataout <= wire_nl0iili1i_dataout AND NOT(nl0ili1ll); + wire_nl0iiilOl_dataout <= wire_nl0iili1l_dataout AND NOT(nl0ili1ll); + wire_nl0iiilOO_dataout <= wire_nl0iili1O_dataout AND NOT(nl0ili1ll); + wire_nl0iiiO0i_dataout <= wire_nl0iiliii_dataout AND NOT(nl0ili1ll); + wire_nl0iiiO0l_dataout <= niOi0O1il WHEN nl0ili1ll = '1' ELSE wire_nl0iiliil_dataout; + wire_nl0iiiO0O_dataout <= wire_nl0iiliiO_dataout OR nl0ili1ll; + wire_nl0iiiO1i_dataout <= wire_nl1lOOlli_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iili0i_dataout; + wire_nl0iiiO1l_dataout <= wire_nl1lOOlll_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iili0l_dataout; + wire_nl0iiiO1O_dataout <= wire_nl1lOOllO_dataout WHEN nl0ili1ll = '1' ELSE wire_nl0iili0O_dataout; + wire_nl0iiiOi_dataout <= nl0i0iOi AND NOT(nl0iiO1O); + wire_nl0iiiOii_dataout <= wire_nl0iilili_dataout AND NOT(nl0ili1ll); + wire_nl0iiiOil_dataout <= wire_nl0iilill_dataout OR nl0ili1ll; + wire_nl0iiiOiO_dataout <= wire_nl0iililO_dataout AND NOT(nl0ili1ll); + wire_nl0iiiOl_dataout <= nl0i0iOl AND NOT(nl0iiO1O); + wire_nl0iiiOli_dataout <= wire_nl0iiliOi_dataout AND NOT(nl0ili1ll); + wire_nl0iiiOll_dataout <= wire_w_lg_niOi0O1lO52249w(0) WHEN nl0ili1ll = '1' ELSE wire_nl0iiliOl_dataout; + wire_nl0iiiOlO_dataout <= nliiO11OO WHEN nl0ili1ll = '1' ELSE wire_nl0iiliOO_dataout; + wire_nl0iiiOO_dataout <= nl0i0iOO AND NOT(nl0iiO1O); + wire_nl0iiiOOi_dataout <= wire_nl0iill1i_dataout OR nl0illl0i; + wire_nl0iiiOOl_dataout <= wire_nl0iill1l_dataout OR nl0illl0i; + wire_nl0iiiOOO_dataout <= wire_nl0iill1O_dataout OR nl0illl0i; + wire_nl0iil00i_dataout <= wire_nl0iilOii_dataout AND NOT(nl0illl0i); + wire_nl0iil00l_dataout <= wire_nl0iilOil_dataout AND NOT(nl0illl0i); + wire_nl0iil00O_dataout <= wire_nl0iilOiO_dataout AND NOT(nl0illl0i); + wire_nl0iil01i_dataout <= wire_nl0iilO0i_dataout AND NOT(nl0illl0i); + wire_nl0iil01l_dataout <= wire_nl0iilO0l_dataout AND NOT(nl0illl0i); + wire_nl0iil01O_dataout <= wire_nl0iilO0O_dataout AND NOT(nl0illl0i); + wire_nl0iil0i_dataout <= nl0i0l0i AND NOT(nl0iiO1O); + wire_nl0iil0ii_dataout <= wire_nl0iilOli_dataout AND NOT(nl0illl0i); + wire_nl0iil0il_dataout <= wire_nl0iilOll_dataout AND NOT(nl0illl0i); + wire_nl0iil0iO_dataout <= wire_nl0iilOlO_dataout AND NOT(nl0illl0i); + wire_nl0iil0l_dataout <= nl0i0l0l AND NOT(nl0iiO1O); + wire_nl0iil0li_dataout <= wire_nl0iilOOi_dataout AND NOT(nl0illl0i); + wire_nl0iil0ll_dataout <= wire_nl0iilOOl_dataout AND NOT(nl0illl0i); + wire_nl0iil0lO_dataout <= wire_nl0iilOOO_dataout AND NOT(nl0illl0i); + wire_nl0iil0O_dataout <= nl0i0l0O AND NOT(nl0iiO1O); + wire_nl0iil0Oi_dataout <= wire_nl0iiO11i_dataout AND NOT(nl0illl0i); + wire_nl0iil0Ol_dataout <= nliiO11OO WHEN nl0illl0i = '1' ELSE wire_nl0iiO11l_dataout; + wire_nl0iil0OO_dataout <= wire_nl0iiO11O_dataout AND NOT(nl0illl0i); + wire_nl0iil10i_dataout <= wire_nl0iillii_dataout AND NOT(nl0illl0i); + wire_nl0iil10l_dataout <= wire_nl0iillil_dataout AND NOT(nl0illl0i); + wire_nl0iil10O_dataout <= wire_nl0iilliO_dataout AND NOT(nl0illl0i); + wire_nl0iil11i_dataout <= wire_nl0iill0i_dataout OR nl0illl0i; + wire_nl0iil11l_dataout <= wire_nl0iill0l_dataout AND NOT(nl0illl0i); + wire_nl0iil11O_dataout <= wire_nl0iill0O_dataout AND NOT(nl0illl0i); + wire_nl0iil1i_dataout <= nl0i0l1i AND NOT(nl0iiO1O); + wire_nl0iil1ii_dataout <= wire_nl0iillli_dataout AND NOT(nl0illl0i); + wire_nl0iil1il_dataout <= wire_nl0iillll_dataout AND NOT(nl0illl0i); + wire_nl0iil1iO_dataout <= wire_nl0iilllO_dataout AND NOT(nl0illl0i); + wire_nl0iil1l_dataout <= nl0i0l1l AND NOT(nl0iiO1O); + wire_nl0iil1li_dataout <= wire_nl0iillOi_dataout AND NOT(nl0illl0i); + wire_nl0iil1ll_dataout <= wire_nl0iillOl_dataout AND NOT(nl0illl0i); + wire_nl0iil1lO_dataout <= wire_nl0iillOO_dataout AND NOT(nl0illl0i); + wire_nl0iil1O_dataout <= nl0i0l1O AND NOT(nl0iiO1O); + wire_nl0iil1Oi_dataout <= wire_nl0iilO1i_dataout AND NOT(nl0illl0i); + wire_nl0iil1Ol_dataout <= wire_nl0iilO1l_dataout OR nl0illl0i; + wire_nl0iil1OO_dataout <= wire_nl0iilO1O_dataout AND NOT(nl0illl0i); + wire_nl0iili0i_dataout <= nl0l0i1Oi WHEN nl0illl0i = '1' ELSE wire_nl0iiO1ii_dataout; + wire_nl0iili0l_dataout <= nl0l0i1Ol WHEN nl0illl0i = '1' ELSE wire_nl0iiO1il_dataout; + wire_nl0iili0O_dataout <= nl0l0i1OO WHEN nl0illl0i = '1' ELSE wire_nl0iiO1iO_dataout; + wire_nl0iili1i_dataout <= wire_nl0iiO10i_dataout AND NOT(nl0illl0i); + wire_nl0iili1l_dataout <= wire_nl0iiO10l_dataout AND NOT(nl0illl0i); + wire_nl0iili1O_dataout <= wire_nl0iiO10O_dataout AND NOT(nl0illl0i); + wire_nl0iilii_dataout <= nl0i0lii AND NOT(nl0iiO1O); + wire_nl0iiliii_dataout <= wire_nl0iiO1li_dataout AND NOT(nl0illl0i); + wire_nl0iiliil_dataout <= wire_nl0iiO1ll_dataout AND NOT(nl0illl0i); + wire_nl0iiliiO_dataout <= wire_nl0iiO1lO_dataout AND NOT(nl0illl0i); + wire_nl0iilil_dataout <= nl0i0lil AND NOT(nl0iiO1O); + wire_nl0iilili_dataout <= wire_nl0iiO1Oi_dataout AND NOT(nl0illl0i); + wire_nl0iilill_dataout <= wire_nl0iiO1Ol_dataout AND NOT(nl0illl0i); + wire_nl0iililO_dataout <= wire_nl0iiO1OO_dataout AND NOT(nl0illl0i); + wire_nl0iiliO_dataout <= nl0i0liO AND NOT(nl0iiO1O); + wire_nl0iiliOi_dataout <= nl0i00iiO WHEN nl0illl0i = '1' ELSE wire_nl0iiO01i_dataout; + wire_nl0iiliOl_dataout <= wire_nl0iiO01l_dataout OR nl0illl0i; + wire_nl0iiliOO_dataout <= nliiO11OO WHEN nl0illl0i = '1' ELSE wire_nl0iiO01O_dataout; + wire_nl0iill0i_dataout <= wire_nl0iiO0ii_dataout AND NOT(nl0illl0l); + wire_nl0iill0l_dataout <= wire_nl0iiO0il_dataout AND NOT(nl0illl0l); + wire_nl0iill0O_dataout <= wire_nl0iiO0iO_dataout OR nl0illl0l; + wire_nl0iill1i_dataout <= nl0ilOiOO WHEN nl0illl0l = '1' ELSE wire_nl0iiO00i_dataout; + wire_nl0iill1l_dataout <= nl0ilOl1i WHEN nl0illl0l = '1' ELSE wire_nl0iiO00l_dataout; + wire_nl0iill1O_dataout <= wire_nlill0Oll_w_lg_nl0ilOl1l52248w(0) WHEN nl0illl0l = '1' ELSE wire_nl0iiO00O_dataout; + wire_nl0iilli_dataout <= nl0i0lli AND NOT(nl0iiO1O); + wire_nl0iillii_dataout <= wire_nl0iiO0li_dataout AND NOT(nl0illl0l); + wire_nl0iillil_dataout <= wire_nl0iiO0ll_dataout AND NOT(nl0illl0l); + wire_nl0iilliO_dataout <= wire_nl0iiO0lO_dataout AND NOT(nl0illl0l); + wire_nl0iilll_dataout <= nl0i0lll AND NOT(nl0iiO1O); + wire_nl0iillli_dataout <= wire_nl0iiO0Oi_dataout AND NOT(nl0illl0l); + wire_nl0iillll_dataout <= wire_nl0iiO0Ol_dataout AND NOT(nl0illl0l); + wire_nl0iilllO_dataout <= wire_nl0iiO0OO_dataout AND NOT(nl0illl0l); + wire_nl0iillO_dataout <= nl0i0llO AND NOT(nl0iiO1O); + wire_nl0iillOi_dataout <= wire_nl0iiOi1i_dataout AND NOT(nl0illl0l); + wire_nl0iillOl_dataout <= wire_nl0iiOi1l_dataout AND NOT(nl0illl0l); + wire_nl0iillOO_dataout <= wire_nl0iiOi1O_dataout AND NOT(nl0illl0l); + wire_nl0iilO0i_dataout <= wire_nl0iiOiii_dataout AND NOT(nl0illl0l); + wire_nl0iilO0l_dataout <= wire_nl0iiOiil_dataout AND NOT(nl0illl0l); + wire_nl0iilO0O_dataout <= wire_nl0iiOiiO_dataout AND NOT(nl0illl0l); + wire_nl0iilO1i_dataout <= wire_nl0iiOi0i_dataout AND NOT(nl0illl0l); + wire_nl0iilO1l_dataout <= wire_nl0iiOi0l_dataout AND NOT(nl0illl0l); + wire_nl0iilO1O_dataout <= wire_nl0iiOi0O_dataout AND NOT(nl0illl0l); + wire_nl0iilOi_dataout <= nl0i0lOi AND NOT(nl0iiO1O); + wire_nl0iilOii_dataout <= wire_nl0iiOili_dataout AND NOT(nl0illl0l); + wire_nl0iilOil_dataout <= wire_nl0iiOill_dataout AND NOT(nl0illl0l); + wire_nl0iilOiO_dataout <= wire_nl0iiOilO_dataout AND NOT(nl0illl0l); + wire_nl0iilOl_dataout <= nl0i0lOl AND NOT(nl0iiO1O); + wire_nl0iilOli_dataout <= wire_nl0iiOiOi_dataout AND NOT(nl0illl0l); + wire_nl0iilOll_dataout <= wire_nl0iiOiOl_dataout AND NOT(nl0illl0l); + wire_nl0iilOlO_dataout <= wire_nl0iiOiOO_dataout AND NOT(nl0illl0l); + wire_nl0iilOO_dataout <= nl0i0lOO AND NOT(nl0iiO1O); + wire_nl0iilOOi_dataout <= wire_nl0iiOl1i_dataout AND NOT(nl0illl0l); + wire_nl0iilOOl_dataout <= wire_nl0iiOl1l_dataout AND NOT(nl0illl0l); + wire_nl0iilOOO_dataout <= wire_nl0iiOl1O_dataout AND NOT(nl0illl0l); + wire_nl0iiO00i_dataout <= wire_nl0il01Ol_dataout WHEN nl0illl0O = '1' ELSE wire_nl0iiOOii_dataout; + wire_nl0iiO00l_dataout <= niOi0O1li WHEN nl0illl0O = '1' ELSE wire_nl0iiOOil_dataout; + wire_nl0iiO00O_dataout <= wire_nl0il01OO_dataout WHEN nl0illl0O = '1' ELSE wire_nl0iiOOiO_dataout; + wire_nl0iiO01i_dataout <= wire_nl0iiOO0i_dataout OR nl0illl0l; + wire_nl0iiO01l_dataout <= wire_nl0iiOO0l_dataout AND NOT(nl0illl0l); + wire_nl0iiO01O_dataout <= nliiO11OO WHEN nl0illl0l = '1' ELSE wire_nl0iiOO0O_dataout; + wire_nl0iiO0i_dataout <= wire_nl0iiOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iiO0ii_dataout <= wire_nl0il001i_dataout WHEN nl0illl0O = '1' ELSE wire_nl0iiOOli_dataout; + wire_nl0iiO0il_dataout <= wire_nl0iiOOll_dataout OR nl0illl0O; + wire_nl0iiO0iO_dataout <= wire_nl0iiOOlO_dataout AND NOT(nl0illl0O); + wire_nl0iiO0l_dataout <= wire_nl0iiOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iiO0li_dataout <= wire_nl0iiOOOi_dataout AND NOT(nl0illl0O); + wire_nl0iiO0ll_dataout <= wire_nl0iiOOOl_dataout AND NOT(nl0illl0O); + wire_nl0iiO0lO_dataout <= wire_nl0iiOOOO_dataout AND NOT(nl0illl0O); + wire_nl0iiO0O_dataout <= niOO1lOlO AND NOT(wire_niO01O0O_dataout); + wire_nl0iiO0Oi_dataout <= wire_nl0il111i_dataout AND NOT(nl0illl0O); + wire_nl0iiO0Ol_dataout <= wire_nl0il111l_dataout AND NOT(nl0illl0O); + wire_nl0iiO0OO_dataout <= wire_nl0il111O_dataout AND NOT(nl0illl0O); + wire_nl0iiO10i_dataout <= wire_nl0iiOlii_dataout AND NOT(nl0illl0l); + wire_nl0iiO10l_dataout <= wire_nl0iiOlil_dataout AND NOT(nl0illl0l); + wire_nl0iiO10O_dataout <= wire_nl0iiOliO_dataout AND NOT(nl0illl0l); + wire_nl0iiO11i_dataout <= wire_nl0iiOl0i_dataout AND NOT(nl0illl0l); + wire_nl0iiO11l_dataout <= nliiO11OO WHEN nl0illl0l = '1' ELSE wire_nl0iiOl0l_dataout; + wire_nl0iiO11O_dataout <= wire_nl0iiOl0O_dataout AND NOT(nl0illl0l); + wire_nl0iiO1ii_dataout <= wire_nl0iiOlli_dataout AND NOT(nl0illl0l); + wire_nl0iiO1il_dataout <= wire_nl0iiOlll_dataout AND NOT(nl0illl0l); + wire_nl0iiO1iO_dataout <= wire_nl0iiOllO_dataout AND NOT(nl0illl0l); + wire_nl0iiO1li_dataout <= wire_nl0iiOlOi_dataout AND NOT(nl0illl0l); + wire_nl0iiO1ll_dataout <= wire_nl0iiOlOl_dataout AND NOT(nl0illl0l); + wire_nl0iiO1lO_dataout <= wire_nl0iiOlOO_dataout AND NOT(nl0illl0l); + wire_nl0iiO1Oi_dataout <= wire_nl0iiOO1i_dataout OR nl0illl0l; + wire_nl0iiO1Ol_dataout <= wire_nl0iiOO1l_dataout AND NOT(nl0illl0l); + wire_nl0iiO1OO_dataout <= wire_nl0iiOO1O_dataout OR nl0illl0l; + wire_nl0iiOi0i_dataout <= wire_nl0il11ii_dataout AND NOT(nl0illl0O); + wire_nl0iiOi0l_dataout <= wire_nl0il11il_dataout AND NOT(nl0illl0O); + wire_nl0iiOi0O_dataout <= wire_nl0il11iO_dataout AND NOT(nl0illl0O); + wire_nl0iiOi1i_dataout <= wire_nl0il110i_dataout AND NOT(nl0illl0O); + wire_nl0iiOi1l_dataout <= wire_nl0il110l_dataout AND NOT(nl0illl0O); + wire_nl0iiOi1O_dataout <= wire_nl0il110O_dataout AND NOT(nl0illl0O); + wire_nl0iiOii_dataout <= wire_nl0iiOiO_o(0) AND NOT(niOO1lOlO); + wire_nl0iiOiii_dataout <= wire_nl0il11li_dataout AND NOT(nl0illl0O); + wire_nl0iiOiil_dataout <= wire_nl0il11ll_dataout AND NOT(nl0illl0O); + wire_nl0iiOiiO_dataout <= wire_nl0il11lO_dataout AND NOT(nl0illl0O); + wire_nl0iiOil_dataout <= wire_nl0iiOiO_o(1) AND NOT(niOO1lOlO); + wire_nl0iiOili_dataout <= wire_nl0il11Oi_dataout AND NOT(nl0illl0O); + wire_nl0iiOill_dataout <= wire_nl0il11Ol_dataout AND NOT(nl0illl0O); + wire_nl0iiOilO_dataout <= wire_nl0il11OO_dataout AND NOT(nl0illl0O); + wire_nl0iiOiOi_dataout <= wire_nl0il101i_dataout AND NOT(nl0illl0O); + wire_nl0iiOiOl_dataout <= wire_nl0il101l_dataout AND NOT(nl0illl0O); + wire_nl0iiOiOO_dataout <= wire_nl0il101O_dataout AND NOT(nl0illl0O); + wire_nl0iiOl0i_dataout <= wire_nl0il10ii_dataout AND NOT(nl0illl0O); + wire_nl0iiOl0l_dataout <= nliiO11OO WHEN nl0illl0O = '1' ELSE wire_nl0il10il_dataout; + wire_nl0iiOl0O_dataout <= wire_nl0il10iO_dataout AND NOT(nl0illl0O); + wire_nl0iiOl1i_dataout <= wire_nl0il100i_dataout AND NOT(nl0illl0O); + wire_nl0iiOl1l_dataout <= wire_nl0il100l_dataout AND NOT(nl0illl0O); + wire_nl0iiOl1O_dataout <= wire_nl0il100O_dataout AND NOT(nl0illl0O); + wire_nl0iiOlii_dataout <= wire_nl0il10li_dataout AND NOT(nl0illl0O); + wire_nl0iiOlil_dataout <= wire_nl0il10ll_dataout AND NOT(nl0illl0O); + wire_nl0iiOliO_dataout <= wire_nl0il10lO_dataout AND NOT(nl0illl0O); + wire_nl0iiOlli_dataout <= wire_nl0il10Oi_dataout AND NOT(nl0illl0O); + wire_nl0iiOlll_dataout <= wire_nl0il10Ol_dataout AND NOT(nl0illl0O); + wire_nl0iiOllO_dataout <= wire_nl0il10OO_dataout AND NOT(nl0illl0O); + wire_nl0iiOlOi_dataout <= wire_nl0il1i1i_dataout AND NOT(nl0illl0O); + wire_nl0iiOlOl_dataout <= wire_nl0il001O_dataout WHEN nl0illl0O = '1' ELSE wire_nl0il1i1l_dataout; + wire_nl0iiOlOO_dataout <= wire_nl0il000i_dataout WHEN nl0illl0O = '1' ELSE wire_nl0il1i1O_dataout; + wire_nl0iiOO0i_dataout <= wire_nl0il1iii_dataout OR nl0illl0O; + wire_nl0iiOO0l_dataout <= wire_nl0il1iil_dataout AND NOT(nl0illl0O); + wire_nl0iiOO0O_dataout <= nliiO11OO WHEN nl0illl0O = '1' ELSE wire_nl0il1iiO_dataout; + wire_nl0iiOO1i_dataout <= wire_nl0il000l_dataout WHEN nl0illl0O = '1' ELSE wire_nl0il1i0i_dataout; + wire_nl0iiOO1l_dataout <= wire_nl0il1i0l_dataout AND NOT(nl0illl0O); + wire_nl0iiOO1O_dataout <= wire_nl0il1i0O_dataout OR nl0illl0O; + wire_nl0iiOOii_dataout <= wire_nl0il01Oi_dataout WHEN wire_w_lg_niOi0O1iO52247w(0) = '1' ELSE wire_nl0il1ili_dataout; + wire_nl0iiOOil_dataout <= wire_nl0ilOi0O_dataout WHEN wire_w_lg_niOi0O1iO52247w(0) = '1' ELSE wire_nl0il1ill_dataout; + wire_nl0iiOOiO_dataout <= wire_nl0il1ilO_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0iiOOli_dataout <= wire_nl0il1iOi_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0iiOOll_dataout <= wire_nl0il1iOl_dataout OR wire_w_lg_niOi0O1iO52247w(0); + wire_nl0iiOOlO_dataout <= wire_nl0il1iOO_dataout OR wire_w_lg_niOi0O1iO52247w(0); + wire_nl0iiOOOi_dataout <= wire_nl0il1l1i_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0iiOOOl_dataout <= wire_nl0il1l1l_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0iiOOOO_dataout <= wire_nl0il1l1O_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il000i_dataout <= wire_nl0il000O_dataout AND NOT(niOi0O1li); + wire_nl0il000l_dataout <= wire_nl0il00ii_dataout OR niOi0O1li; + wire_nl0il000O_dataout <= wire_nlill0Oll_w_lg_nlil1lOii52245w(0) AND NOT(niOii1OOl); + wire_nl0il001i_dataout <= wire_nl0il001l_dataout OR niOi0O1li; + wire_nl0il001l_dataout <= wire_nlill0Oll_w_lg_nlil1lOii52245w(0) OR niOii1OOl; + wire_nl0il001O_dataout <= wire_nl0il000O_dataout OR niOi0O1li; + wire_nl0il00i_dataout <= wire_nl0il0ii_dataout AND NOT(niOO1lOOl); + wire_nl0il00ii_dataout <= nlil1lOii AND NOT(niOii1OOl); + wire_nl0il00iO_dataout <= nl0l0lliO AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il00l_dataout <= wire_nl0iliil_o(1) OR niOO1lOOi; + wire_nl0il00li_dataout <= nl0l0llli AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il00ll_dataout <= nl0l0llll AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il00lO_dataout <= nl0l0lllO AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il00O_dataout <= wire_nl0iliil_o(2) OR niOO1lOOi; + wire_nl0il00Oi_dataout <= nl0l0llOi AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il00Ol_dataout <= nl0l0llOl AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il00OO_dataout <= nl0l0llOO AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il010i_dataout <= nl0i000OO AND NOT(nl0illlli); + wire_nl0il010l_dataout <= nl0i00i1i AND NOT(nl0illlli); + wire_nl0il010O_dataout <= nl0i00i1l AND NOT(nl0illlli); + wire_nl0il011i_dataout <= nl0i000lO AND NOT(nl0illlli); + wire_nl0il011l_dataout <= nl0i000Oi AND NOT(nl0illlli); + wire_nl0il011O_dataout <= nl0i000Ol AND NOT(nl0illlli); + wire_nl0il01i_dataout <= wire_nl0il0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0il01ii_dataout <= nl0i00i1O OR nl0illlli; + wire_nl0il01il_dataout <= nl0i00i0i AND NOT(nl0illlli); + wire_nl0il01iO_dataout <= nl0i00i0l OR nl0illlli; + wire_nl0il01l_dataout <= wire_nl0il00l_dataout AND NOT(niOO1lOOl); + wire_nl0il01li_dataout <= nl0i00i0O OR nl0illlli; + wire_nl0il01ll_dataout <= nl0i00iii OR nl0illlli; + wire_nl0il01lO_dataout <= nliiO11OO WHEN nl0illlli = '1' ELSE nl0i00iil; + wire_nl0il01O_dataout <= wire_nl0il00O_dataout AND NOT(niOO1lOOl); + wire_nl0il01Oi_dataout <= wire_nl0ilOiii_dataout OR wire_nl0ilOi0O_dataout; + wire_nl0il01Ol_dataout <= wire_nl0il000O_dataout OR niOi0O1li; + wire_nl0il01OO_dataout <= wire_nl0il00ii_dataout AND NOT(niOi0O1li); + wire_nl0il0i0i_dataout <= nl0l0lO0i AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0i0l_dataout <= nl0l0lO0l AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0i0O_dataout <= nl0l0lO0O AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0i1i_dataout <= nl0l0lO1i AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0i1l_dataout <= nl0l0lO1l AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0i1O_dataout <= nl0l0lO1O AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0ii_dataout <= wire_nl0iliil_o(3) OR niOO1lOOi; + wire_nl0il0iii_dataout <= nl0l0lOii AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0iil_dataout <= nl0l0ll1i WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOil; + wire_nl0il0iiO_dataout <= nl0l0ll1l WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOiO; + wire_nl0il0ili_dataout <= nl0l0ll1O WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOli; + wire_nl0il0ill_dataout <= nl0l0ll0i WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOll; + wire_nl0il0ilO_dataout <= nl0l0ll0l WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOlO; + wire_nl0il0iOi_dataout <= nl0l0ll0O WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOOi; + wire_nl0il0iOl_dataout <= nl0l0llii WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOOl; + wire_nl0il0iOO_dataout <= nl0l0llil WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0lOOO; + wire_nl0il0l0i_dataout <= wire_nl0l0li0O_dataout WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O10i; + wire_nl0il0l0l_dataout <= wire_nl0l0liil_dataout WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O10l; + wire_nl0il0l0O_dataout <= nl0l0liOi WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O10O; + wire_nl0il0l1i_dataout <= wire_nl0l0l0OO_dataout WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O11i; + wire_nl0il0l1l_dataout <= wire_nl0l0li1l_dataout WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O11l; + wire_nl0il0l1O_dataout <= wire_nl0l0li0i_dataout WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O11O; + wire_nl0il0lii_dataout <= nl0l0liOl WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O1ii; + wire_nl0il0lil_dataout <= nl0l0liOO WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O1il; + wire_nl0il0liO_dataout <= nl0l0O1iO AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0lli_dataout <= nl0l0O1li AND NOT(wire_nlill0Oll_w_lg_nl0i00iiO52244w(0)); + wire_nl0il0lll_dataout <= nl0l0lliO WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O1ll; + wire_nl0il0llO_dataout <= nl0l0llli WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O1lO; + wire_nl0il0lO_dataout <= wire_nl0il0OO_dataout AND NOT(niOO1O11i); + wire_nl0il0lOi_dataout <= nl0l0llll WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O1Oi; + wire_nl0il0lOl_dataout <= nl0l0lllO WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O1Ol; + wire_nl0il0lOO_dataout <= nl0l0llOi WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O1OO; + wire_nl0il0O0i_dataout <= nl0l0lO1l WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O00i; + wire_nl0il0O0l_dataout <= nl0l0lO1O WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O00l; + wire_nl0il0O0O_dataout <= nl0l0lO0i WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O00O; + wire_nl0il0O1i_dataout <= nl0l0llOl WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O01i; + wire_nl0il0O1l_dataout <= nl0l0llOO WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O01l; + wire_nl0il0O1O_dataout <= nl0l0lO1i WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O01O; + wire_nl0il0Oi_dataout <= wire_nl0ili1i_dataout AND NOT(niOO1O11i); + wire_nl0il0Oii_dataout <= nl0l0lO0l WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0ii; + wire_nl0il0Oil_dataout <= nl0l0lO0O WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0il; + wire_nl0il0OiO_dataout <= nl0l0lOii WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0iO; + wire_nl0il0Ol_dataout <= wire_nl0ili1l_dataout AND NOT(niOO1O11i); + wire_nl0il0Oli_dataout <= nl0l0lOil WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0li; + wire_nl0il0Oll_dataout <= nl0l0lOiO WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0ll; + wire_nl0il0OlO_dataout <= nl0l0lOli WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0lO; + wire_nl0il0OO_dataout <= wire_nl0iliiO_o(1) OR niOO1lOOO; + wire_nl0il0OOi_dataout <= nl0l0lOll WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0Oi; + wire_nl0il0OOl_dataout <= nl0l0lOlO WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0Ol; + wire_nl0il0OOO_dataout <= nl0l0lOOi WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0O0OO; + wire_nl0il100i_dataout <= wire_nl0il1Oii_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il100l_dataout <= wire_nl0il1Oil_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il100O_dataout <= wire_nl0il1OiO_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il101i_dataout <= wire_nl0il1O0i_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il101l_dataout <= wire_nl0il1O0l_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il101O_dataout <= wire_nl0il1O0O_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10ii_dataout <= wire_nl0il1Oli_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10il_dataout <= nliiO11OO WHEN wire_w_lg_niOi0O1iO52247w(0) = '1' ELSE wire_nl0il1Oll_dataout; + wire_nl0il10iO_dataout <= wire_nl0il1OlO_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10li_dataout <= wire_nl0il1OOi_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10ll_dataout <= wire_nl0il1OOl_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10lO_dataout <= wire_nl0il1OOO_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10Oi_dataout <= wire_nl0il011i_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10Ol_dataout <= wire_nl0il011l_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il10OO_dataout <= wire_nl0il011O_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il110i_dataout <= wire_nl0il1lii_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il110l_dataout <= wire_nl0il1lil_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il110O_dataout <= wire_nl0il1liO_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il111i_dataout <= wire_nl0il1l0i_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il111l_dataout <= wire_nl0il1l0l_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il111O_dataout <= wire_nl0il1l0O_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11ii_dataout <= wire_nl0il1lli_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11il_dataout <= wire_nl0il1lll_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11iO_dataout <= wire_nl0il1llO_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11li_dataout <= wire_nl0il1lOi_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11ll_dataout <= wire_nl0il1lOl_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11lO_dataout <= wire_nl0il1lOO_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11Oi_dataout <= wire_nl0il1O1i_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11Ol_dataout <= wire_nl0il1O1l_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il11OO_dataout <= wire_nl0il1O1O_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il1i0i_dataout <= wire_nl0il01ii_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il1i0l_dataout <= wire_nl0il01il_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il1i0O_dataout <= wire_nl0il01iO_dataout OR wire_w_lg_niOi0O1iO52247w(0); + wire_nl0il1i1i_dataout <= wire_nl0il010i_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il1i1l_dataout <= wire_nl0il010l_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il1i1O_dataout <= wire_nl0il010O_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il1iii_dataout <= wire_nl0il01li_dataout OR wire_w_lg_niOi0O1iO52247w(0); + wire_nl0il1iil_dataout <= wire_nl0il01ll_dataout AND NOT(wire_w_lg_niOi0O1iO52247w(0)); + wire_nl0il1iiO_dataout <= nliiO11OO WHEN wire_w_lg_niOi0O1iO52247w(0) = '1' ELSE wire_nl0il01lO_dataout; + wire_nl0il1ili_dataout <= nl0i01O0O AND NOT(nl0illlli); + wire_nl0il1ill_dataout <= nl0i01Oii AND NOT(nl0illlli); + wire_nl0il1ilO_dataout <= nl0i01Oil AND NOT(nl0illlli); + wire_nl0il1iOi_dataout <= nl0i01OiO AND NOT(nl0illlli); + wire_nl0il1iOl_dataout <= nl0i01Oli OR nl0illlli; + wire_nl0il1iOO_dataout <= nl0i01Oll AND NOT(nl0illlli); + wire_nl0il1l0i_dataout <= nl0i01OOO AND NOT(nl0illlli); + wire_nl0il1l0l_dataout <= nl0i0011i AND NOT(nl0illlli); + wire_nl0il1l0O_dataout <= nl0i0011l AND NOT(nl0illlli); + wire_nl0il1l1i_dataout <= nl0i01OlO OR nl0illlli; + wire_nl0il1l1l_dataout <= nl0i01OOi AND NOT(nl0illlli); + wire_nl0il1l1O_dataout <= nl0i01OOl AND NOT(nl0illlli); + wire_nl0il1lii_dataout <= nl0i0011O AND NOT(nl0illlli); + wire_nl0il1lil_dataout <= nl0i0010i AND NOT(nl0illlli); + wire_nl0il1liO_dataout <= nl0i0010l AND NOT(nl0illlli); + wire_nl0il1ll_dataout <= wire_nl0il01l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0il1lli_dataout <= nl0i0010O AND NOT(nl0illlli); + wire_nl0il1lll_dataout <= nl0i001ii OR nl0illlli; + wire_nl0il1llO_dataout <= nl0i001il AND NOT(nl0illlli); + wire_nl0il1lO_dataout <= wire_nl0il01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0il1lOi_dataout <= nl0i001iO AND NOT(nl0illlli); + wire_nl0il1lOl_dataout <= nl0i001li AND NOT(nl0illlli); + wire_nl0il1lOO_dataout <= nl0i001ll AND NOT(nl0illlli); + wire_nl0il1O0i_dataout <= nl0i001OO AND NOT(nl0illlli); + wire_nl0il1O0l_dataout <= nl0i0001i AND NOT(nl0illlli); + wire_nl0il1O0O_dataout <= nl0i0001l AND NOT(nl0illlli); + wire_nl0il1O1i_dataout <= nl0i001lO AND NOT(nl0illlli); + wire_nl0il1O1l_dataout <= nl0i001Oi AND NOT(nl0illlli); + wire_nl0il1O1O_dataout <= nl0i001Ol AND NOT(nl0illlli); + wire_nl0il1Oi_dataout <= wire_nl0il00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0il1Oii_dataout <= nl0i0001O AND NOT(nl0illlli); + wire_nl0il1Oil_dataout <= nl0i0000i AND NOT(nl0illlli); + wire_nl0il1OiO_dataout <= nl0i0000l AND NOT(nl0illlli); + wire_nl0il1Ol_dataout <= wire_nl0il0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0il1Oli_dataout <= nl0i0000O AND NOT(nl0illlli); + wire_nl0il1Oll_dataout <= nliiO11OO WHEN nl0illlli = '1' ELSE nl0i000ii; + wire_nl0il1OlO_dataout <= nl0i000il AND NOT(nl0illlli); + wire_nl0il1OO_dataout <= wire_nl0il0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0il1OOi_dataout <= nl0i000iO AND NOT(nl0illlli); + wire_nl0il1OOl_dataout <= nl0i000li AND NOT(nl0illlli); + wire_nl0il1OOO_dataout <= nl0i000ll AND NOT(nl0illlli); + wire_nl0ili00l_dataout <= wire_nl0ilii1l_dataout AND niOii1OOi; + wire_nl0ili00O_dataout <= wire_nl0ilii1O_dataout AND niOii1OOi; + wire_nl0ili01l_dataout <= (nl011l1ii AND niOi0Oiil) AND NOT(niOi0O1Oi); + wire_nl0ili0ii_dataout <= wire_nl0ili0lO_dataout AND niOii1OOi; + wire_nl0ili0il_dataout <= wire_nl0ili0Oi_dataout AND niOii1OOi; + wire_nl0ili0iO_dataout <= wire_nl0ili0Ol_dataout AND niOii1OOi; + wire_nl0ili0li_dataout <= wire_nl0ili0OO_dataout AND niOii1OOi; + wire_nl0ili0ll_dataout <= wire_nl0ilii1i_dataout AND niOii1OOi; + wire_nl0ili0lO_dataout <= wire_nl1lO1l0i_dataout WHEN wire_nl1lOOO0i_dataout = '1' ELSE wire_nl1lO010O_dataout; + wire_nl0ili0Oi_dataout <= wire_nl1lO1l0l_dataout WHEN wire_nl1lOOO0i_dataout = '1' ELSE wire_nl1lO01ii_dataout; + wire_nl0ili0Ol_dataout <= wire_nl1lO1l0O_dataout WHEN wire_nl1lOOO0i_dataout = '1' ELSE wire_nl1lO01il_dataout; + wire_nl0ili0OO_dataout <= wire_nl1lO1lii_dataout WHEN wire_nl1lOOO0i_dataout = '1' ELSE wire_nl1lO01iO_dataout; + wire_nl0ili10i_dataout <= nl0l0O11l WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oi0i; + wire_nl0ili10l_dataout <= nl0l0O11O WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oi0l; + wire_nl0ili10O_dataout <= nl0l0O10i WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oi0O; + wire_nl0ili11i_dataout <= nl0l0lOOl WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oi1i; + wire_nl0ili11l_dataout <= nl0l0lOOO WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oi1l; + wire_nl0ili11O_dataout <= nl0l0O11i WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oi1O; + wire_nl0ili1i_dataout <= wire_nl0iliiO_o(2) OR niOO1lOOO; + wire_nl0ili1ii_dataout <= nl0l0O10l WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oiii; + wire_nl0ili1il_dataout <= nl0l0O10O WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oiil; + wire_nl0ili1iO_dataout <= nl0l0O1ii WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0OiiO; + wire_nl0ili1l_dataout <= wire_nl0iliiO_o(3) OR niOO1lOOO; + wire_nl0ili1li_dataout <= nl0l0O1il WHEN wire_nlill0Oll_w_lg_nl0i00iiO52244w(0) = '1' ELSE nl0l0Oili; + wire_nl0ili1lO_dataout <= wire_w_lg_niOi0O1ll52243w(0) AND NOT(wire_niO01O0O_dataout); + wire_nl0ilii0i_dataout <= wire_nl0ilii0O_dataout OR wire_nl1lOO10i_dataout; + wire_nl0ilii0l_dataout <= wire_nl0iliiii_dataout AND NOT(wire_nl1lOO10i_dataout); + wire_nl0ilii0O_dataout <= wire_nl1lOO10O_dataout AND NOT(wire_nl1lOO10l_dataout); + wire_nl0ilii1i_dataout <= wire_nl1lO1lil_dataout WHEN wire_nl1lOOO0i_dataout = '1' ELSE wire_nl1lO01li_dataout; + wire_nl0ilii1l_dataout <= wire_nl0ilii0i_dataout AND NOT(wire_nl1lOO11O_dataout); + wire_nl0ilii1O_dataout <= wire_nl0ilii0l_dataout AND NOT(wire_nl1lOO11O_dataout); + wire_nl0iliiii_dataout <= wire_nl1lOO10O_dataout OR wire_nl1lOO10l_dataout; + wire_nl0iliiil_dataout <= wire_nl0illi1i_dataout WHEN niOi0O1OO = '1' ELSE wire_nl0ilil0l_o(1); + wire_nl0iliiiO_dataout <= wire_nl0illi1l_dataout WHEN niOi0O1OO = '1' ELSE wire_nl0ilil0l_o(2); + wire_nl0iliili_dataout <= wire_nl0illi1O_dataout WHEN niOi0O1OO = '1' ELSE wire_nl0ilil0l_o(3); + wire_nl0iliill_dataout <= wire_nl0ilil0l_o(4) AND NOT(niOi0O1OO); + wire_nl0iliilO_dataout <= wire_nl0ilil0l_o(5) AND NOT(niOi0O1OO); + wire_nl0iliiOi_dataout <= wire_nl0ilil0l_o(6) AND NOT(niOi0O1OO); + wire_nl0iliiOl_dataout <= wire_nl0ilil0l_o(7) AND NOT(niOi0O1OO); + wire_nl0iliiOO_dataout <= wire_nl0ilil0l_o(8) AND NOT(niOi0O1OO); + wire_nl0ilil0i_dataout <= wire_nl0ilil0l_o(12) AND NOT(niOi0O1OO); + wire_nl0ilil0O_dataout <= wire_nl0ililiO_dataout AND NOT(niOi0Oi1i); + wire_nl0ilil0O_w_lg_dataout52199w(0) <= NOT wire_nl0ilil0O_dataout; + wire_nl0ilil1i_dataout <= wire_nl0ilil0l_o(9) AND NOT(niOi0O1OO); + wire_nl0ilil1l_dataout <= wire_nl0ilil0l_o(10) AND NOT(niOi0O1OO); + wire_nl0ilil1O_dataout <= wire_nl0ilil0l_o(11) AND NOT(niOi0O1OO); + wire_nl0ililii_dataout <= wire_nl0ililli_dataout AND NOT(niOi0Oi1i); + wire_nl0ililii_w_lg_dataout52201w(0) <= NOT wire_nl0ililii_dataout; + wire_nl0ililil_dataout <= wire_nl0ililll_dataout AND NOT(niOi0Oi1i); + wire_nl0ililil_w_lg_dataout52203w(0) <= NOT wire_nl0ililil_dataout; + wire_nl0ililiO_dataout <= wire_nl0ilillO_dataout OR niOi0O0OO; + wire_nl0ililli_dataout <= wire_nl0ililOi_dataout AND NOT(niOi0O0OO); + wire_nl0ililll_dataout <= wire_nl0ililOl_dataout AND NOT(niOi0O0OO); + wire_nl0ilillO_dataout <= wire_nl0ililOO_dataout AND NOT(niOi0O0Ol); + wire_nl0ililOi_dataout <= wire_nl0iliO1i_dataout OR niOi0O0Ol; + wire_nl0ililOl_dataout <= wire_nl0iliO1l_dataout AND NOT(niOi0O0Ol); + wire_nl0ililOO_dataout <= wire_nl0iliO1O_dataout OR niOi0O0Oi; + wire_nl0iliO0i_dataout <= wire_nl0iliOii_dataout AND NOT(niOi0O0lO); + wire_nl0iliO0l_dataout <= wire_nl0iliOil_dataout AND NOT(niOi0O0lO); + wire_nl0iliO0O_dataout <= wire_nl0iliOiO_dataout AND NOT(niOi0O0ll); + wire_nl0iliO1i_dataout <= wire_nl0iliO0i_dataout OR niOi0O0Oi; + wire_nl0iliO1l_dataout <= wire_nl0iliO0l_dataout AND NOT(niOi0O0Oi); + wire_nl0iliO1O_dataout <= wire_nl0iliO0O_dataout OR niOi0O0lO; + wire_nl0iliOii_dataout <= wire_nl0iliOli_dataout OR niOi0O0ll; + wire_nl0iliOil_dataout <= wire_nl0iliOll_dataout AND NOT(niOi0O0ll); + wire_nl0iliOiO_dataout <= wire_nl0iliOlO_dataout OR niOi0O0li; + wire_nl0iliOli_dataout <= wire_nl0iliOOi_dataout OR niOi0O0li; + wire_nl0iliOll_dataout <= wire_nl0iliOOl_dataout AND NOT(niOi0O0li); + wire_nl0iliOlO_dataout <= wire_nl0iliOOO_dataout AND NOT(niOi0O0iO); + wire_nl0iliOOi_dataout <= wire_nl0ill11i_dataout AND NOT(niOi0O0iO); + wire_nl0iliOOl_dataout <= wire_nl0ill11l_dataout OR niOi0O0iO; + wire_nl0iliOOO_dataout <= wire_nl0ill11O_dataout AND NOT(niOi0O0il); + wire_nl0ill10i_dataout <= wire_nl0ill1ii_dataout OR niOi0O0ii; + wire_nl0ill10l_dataout <= wire_nl0ill1il_dataout AND NOT(niOi0O0ii); + wire_nl0ill10O_dataout <= wire_nl0ill1iO_dataout AND NOT(niOi0O00O); + wire_nl0ill11i_dataout <= wire_nl0ill10i_dataout OR niOi0O0il; + wire_nl0ill11l_dataout <= wire_nl0ill10l_dataout AND NOT(niOi0O0il); + wire_nl0ill11O_dataout <= wire_nl0ill10O_dataout OR niOi0O0ii; + wire_nl0ill1ii_dataout <= wire_nl0ill1li_dataout AND NOT(niOi0O00O); + wire_nl0ill1il_dataout <= wire_nl0ill1ll_dataout OR niOi0O00O; + wire_nl0ill1iO_dataout <= wire_nl0ill1lO_dataout OR niOi0O00l; + wire_nl0ill1li_dataout <= wire_nl0ill1Oi_dataout AND NOT(niOi0O00l); + wire_nl0ill1ll_dataout <= wire_w_lg_niOi0O00i52177w(0) OR niOi0O00l; + wire_nl0ill1lO_dataout <= wire_nl0ill1Ol_dataout OR niOi0O00i; + wire_nl0ill1Oi_dataout <= wire_nl0ill1OO_dataout OR niOi0O00i; + wire_nl0ill1Ol_dataout <= niOi0O01l AND NOT(niOi0O01O); + wire_nl0ill1OO_dataout <= wire_w_lg_niOi0O01l52176w(0) AND NOT(niOi0O01O); + wire_nl0illi0i_dataout <= wire_nl0illi0O_dataout AND NOT(niOi0Oi0l); + wire_nl0illi0l_dataout <= wire_nl0illiii_dataout AND NOT(niOi0Oi0l); + wire_nl0illi0O_dataout <= wire_nl0illiil_dataout OR niOi0Oi0i; + wire_nl0illi1i_dataout <= wire_nl0illi0i_dataout AND NOT(wire_w_lg_niOii1OOi52160w(0)); + wire_nl0illi1l_dataout <= wire_nl0illi0l_dataout AND NOT(wire_w_lg_niOii1OOi52160w(0)); + wire_nl0illi1O_dataout <= niOi0Oi0l OR wire_w_lg_niOii1OOi52160w(0); + wire_nl0illiii_dataout <= wire_nl0illiiO_dataout OR niOi0Oi0i; + wire_nl0illiil_dataout <= wire_w_lg_niOi0Oi1l52159w(0) OR niOi0Oi1O; + wire_nl0illiiO_dataout <= niOi0Oi1l OR niOi0Oi1O; + wire_nl0illiOO_dataout <= nl0illliO WHEN wire_w_lg_niOi0Olii52139w(0) = '1' ELSE nl0i1li0O; + wire_nl0illl1i_dataout <= nl0illlil WHEN wire_w_lg_niOi0Olii52139w(0) = '1' ELSE nl0i1li0l; + wire_nl0illl1l_dataout <= nl0illlii WHEN wire_w_lg_niOi0Olii52139w(0) = '1' ELSE nl0i1li0i; + wire_nl0illl1O_dataout <= nl0illl0i WHEN niOii1OOl = '1' ELSE nl0i1li1O; + wire_nl0illlOi_dataout <= wire_nl0illOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illlOl_dataout <= wire_nl0illOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illlOO_dataout <= wire_nl0illOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illO0i_dataout <= wire_nl0illOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illO0l_dataout <= wire_nl0illOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illO0O_dataout <= wire_nl0ilO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illO1i_dataout <= wire_nl0illOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illO1l_dataout <= wire_nl0illOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illO1O_dataout <= wire_nl0illOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illOii_dataout <= wire_nl0ilOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0illOil_dataout <= niOi0Oiii AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0illOiO_dataout <= wire_nl0ilO11i_dataout AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0illOli_dataout <= wire_nl0ilO11l_dataout AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0illOll_dataout <= wire_nl0ilO11O_dataout AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0illOlO_dataout <= wire_nl0ilO10i_dataout AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0illOO_dataout <= wire_nl0iO10l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0illOOi_dataout <= wire_nl0ilO10l_dataout AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0illOOl_dataout <= wire_nl0ilO10O_dataout AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0illOOO_dataout <= wire_nl0ilO1ii_dataout AND wire_nlill0Oll_w_lg_nl0illllO52075w(0); + wire_nl0ilO00i_dataout <= wire_nl0ilOi0O_dataout AND NOT(niOilO11i); + wire_nl0ilO00l_dataout <= wire_nl0ilO0il_dataout AND NOT(niOilO11i); + wire_nl0ilO00O_dataout <= wire_nl0ilO0iO_dataout AND NOT(niOilO11i); + wire_nl0ilO01i_dataout <= wire_nl0ilO00l_dataout AND NOT(wire_nl0ilOi0l_dataout); + wire_nl0ilO01l_dataout <= wire_nl0ilO00O_dataout AND NOT(wire_nl0ilOi0l_dataout); + wire_nl0ilO01O_dataout <= wire_nl0ilO0ii_dataout AND NOT(wire_nl0ilOi0l_dataout); + wire_nl0ilO0i_dataout <= wire_nl0iO1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilO0ii_dataout <= wire_nl0ilO0li_dataout AND NOT(niOilO11i); + wire_nl0ilO0il_dataout <= wire_nl0ilOiii_dataout AND NOT(wire_nl0ilOi0O_dataout); + wire_nl0ilO0iO_dataout <= wire_nl0ilO0ll_dataout AND NOT(wire_nl0ilOi0O_dataout); + wire_nl0ilO0l_dataout <= wire_nl0iO1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilO0li_dataout <= wire_nl0ilO0lO_dataout AND NOT(wire_nl0ilOi0O_dataout); + wire_nl0ilO0ll_dataout <= wire_nl0ilOiil_dataout AND NOT(wire_nl0ilOiii_dataout); + wire_nl0ilO0lO_dataout <= wire_nl0ilO0Oi_dataout AND NOT(wire_nl0ilOiii_dataout); + wire_nl0ilO0O_dataout <= wire_nl0iO1ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilO0Oi_dataout <= wire_nl0ilOiiO_dataout AND NOT(wire_nl0ilOiil_dataout); + wire_nl0ilO0Ol_dataout <= wire_nl0ilO0OO_dataout AND NOT(wire_nlill1l0l_dataout); + wire_nl0ilO0OO_dataout <= nl0illlll OR nl0illllO; + wire_nl0ilO10i_dataout <= wire_nl0ilO1li_dataout AND NOT(niOi0Oiii); + wire_nl0ilO10l_dataout <= wire_nl0ilO1ll_dataout AND NOT(niOi0Oiii); + wire_nl0ilO10O_dataout <= wire_nl0ilO1lO_dataout AND NOT(niOi0Oiii); + wire_nl0ilO11i_dataout <= wire_nl0ilOi0i_dataout AND NOT(niOi0Oiii); + wire_nl0ilO11l_dataout <= wire_nl0ilO1il_dataout AND NOT(niOi0Oiii); + wire_nl0ilO11O_dataout <= wire_nl0ilO1iO_dataout AND NOT(niOi0Oiii); + wire_nl0ilO1i_dataout <= wire_nl0iO10O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilO1ii_dataout <= wire_nl0ilO1Oi_dataout AND NOT(niOi0Oiii); + wire_nl0ilO1il_dataout <= wire_nl0ilOi0l_dataout AND NOT(wire_nl0ilOi0i_dataout); + wire_nl0ilO1iO_dataout <= wire_nl0ilO1Ol_dataout AND NOT(wire_nl0ilOi0i_dataout); + wire_nl0ilO1l_dataout <= wire_nl0iO1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilO1li_dataout <= wire_nl0ilO1OO_dataout AND NOT(wire_nl0ilOi0i_dataout); + wire_nl0ilO1ll_dataout <= wire_nl0ilO01i_dataout AND NOT(wire_nl0ilOi0i_dataout); + wire_nl0ilO1lO_dataout <= wire_nl0ilO01l_dataout AND NOT(wire_nl0ilOi0i_dataout); + wire_nl0ilO1O_dataout <= wire_nl0iO1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilO1Oi_dataout <= wire_nl0ilO01O_dataout AND NOT(wire_nl0ilOi0i_dataout); + wire_nl0ilO1Ol_dataout <= niOilO11i AND NOT(wire_nl0ilOi0l_dataout); + wire_nl0ilO1OO_dataout <= wire_nl0ilO00i_dataout AND NOT(wire_nl0ilOi0l_dataout); + wire_nl0ilOi0i_dataout <= nl0l0i0li AND niOii1OOl; + wire_nl0ilOi0i_w_lg_dataout52528w(0) <= NOT wire_nl0ilOi0i_dataout; + wire_nl0ilOi0l_dataout <= nl0ilOlll AND niOii1OOl; + wire_nl0ilOi0l_w_lg_dataout52526w(0) <= NOT wire_nl0ilOi0l_dataout; + wire_nl0ilOi0O_dataout <= nlililOiO AND niOii1OOl; + wire_nl0ilOi0O_w_lg_dataout52524w(0) <= NOT wire_nl0ilOi0O_dataout; + wire_nl0ilOi1i_dataout <= wire_nl0ilOi1l_dataout OR (wire_nlill0Oll_w_lg_nl0illllO52075w(0) AND wire_w_lg_niOi0Oi0O52137w(0)); + wire_nl0ilOi1l_dataout <= nl0illllO AND NOT(wire_nlill1l0l_dataout); + wire_nl0ilOii_dataout <= wire_nl0iO1lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOiii_dataout <= nlililOil AND niOii1OOl; + wire_nl0ilOiii_w_lg_dataout52522w(0) <= NOT wire_nl0ilOiii_dataout; + wire_nl0ilOiil_dataout <= nlililOii AND niOii1OOl; + wire_nl0ilOiil_w_lg_dataout52520w(0) <= NOT wire_nl0ilOiil_dataout; + wire_nl0ilOiiO_dataout <= nli1i001i AND NOT(niOii1OOl); + wire_nl0ilOiiO_w_lg_dataout52518w(0) <= NOT wire_nl0ilOiiO_dataout; + wire_nl0ilOil_dataout <= wire_nl0iO1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOiO_dataout <= wire_nl0iO1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOli_dataout <= wire_nl0iO1OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOll_dataout <= wire_nl0iO01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOlO_dataout <= wire_nl0iO01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOlOi_dataout <= wire_nl0ilOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOlOl_dataout <= wire_nl0ilOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOlOO_dataout <= wire_nl0ilOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOO0i_dataout <= wire_nl0iO111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOO0l_dataout <= wire_nl0iO110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOO0O_dataout <= wire_nl0iO110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOO1i_dataout <= wire_nl0ilOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOO1l_dataout <= wire_nl0iO111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOO1O_dataout <= wire_nl0iO111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOOi_dataout <= wire_nl0iO00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOOii_dataout <= wire_nl0iO110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOOil_dataout <= wire_nl0iO11ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOOiO_dataout <= wire_nl0iO11il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOOl_dataout <= wire_nl0iO00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOOli_dataout <= wire_nl0iO11iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOOll_dataout <= wire_nl0iO11li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0ilOOlO_dataout <= ((nl0ilOiOl AND nl0illl0l) AND (wire_nlill0Oll_w_lg_nl0ilOl1i52130w(0) AND wire_nlill0Oll_w_lg_nl0ilOiOO52131w(0))) AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0ilOOO_dataout <= wire_nl0iO00O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ilOOOi_dataout <= wire_nl0iO11Oi_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0ilOOOl_dataout <= wire_nl0iO11Ol_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0ilOOOO_dataout <= wire_nl0iO11OO_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO000i_dataout <= nl0ilOlll OR niOi0OiiO; + wire_nl0iO001i_dataout <= nl0ilOlli WHEN niOi0Oill = '1' ELSE wire_nl0iO00Ol_dataout; + wire_nl0iO001l_dataout <= wire_nl0iO0i1i_dataout WHEN niOi0Oill = '1' ELSE wire_nl0iO00Ol_dataout; + wire_nl0iO001O_dataout <= wire_nl0iO000i_dataout AND NOT((wire_niO1110l_w_lg_dataout44125w(0) OR nl0illl0l)); + wire_nl0iO00i_dataout <= wire_nl0iO0ll_o(1) WHEN ni01lll = '1' ELSE nl0illii; + wire_nl0iO00l_dataout <= wire_nl0iO0ll_o(2) WHEN ni01lll = '1' ELSE nl0illil; + wire_nl0iO00O_dataout <= wire_nl0iO0ll_o(3) WHEN ni01lll = '1' ELSE nl0illiO; + wire_nl0iO00Ol_dataout <= wire_nl0iO0iii_dataout AND niOi0Ol1O; + wire_nl0iO010i_dataout <= nl0ilOlil WHEN niOi0OiOi = '1' ELSE wire_nl0iO01li_dataout; + wire_nl0iO010l_dataout <= nl0ilOliO WHEN niOi0OiOi = '1' ELSE wire_nl0iO01ll_dataout; + wire_nl0iO010O_dataout <= nl0ilOlli WHEN niOi0OiOi = '1' ELSE wire_nl0iO01lO_dataout; + wire_nl0iO011i_dataout <= wire_nl0iO01il_dataout OR niOi0OiOl; + wire_nl0iO011l_dataout <= wire_nl0iO0i0i_dataout WHEN niOi0OiOl = '1' ELSE wire_nl0iO01iO_dataout; + wire_nl0iO011O_dataout <= wire_nl0iO0i1O_dataout WHEN niOi0OiOi = '1' ELSE nl0ilOlii; + wire_nl0iO01i_dataout <= wire_nl0iO01l_o(11) WHEN ni1lOOl = '1' ELSE nl0ill0l; + wire_nl0iO01ii_dataout <= wire_nl0iO01Oi_dataout AND NOT(niOi0OiOi); + wire_nl0iO01il_dataout <= wire_w_lg_niOi0OilO52128w(0) AND NOT(niOi0OiOi); + wire_nl0iO01iO_dataout <= wire_nl0iO0i1O_dataout WHEN niOi0OiOi = '1' ELSE wire_nl0iO01Ol_dataout; + wire_nl0iO01li_dataout <= wire_nl0iO0i1l_dataout WHEN niOi0OilO = '1' ELSE nl0ilOlil; + wire_nl0iO01ll_dataout <= nl0ilOliO WHEN niOi0OilO = '1' ELSE wire_nl0iO01OO_dataout; + wire_nl0iO01lO_dataout <= nl0ilOlli WHEN niOi0OilO = '1' ELSE wire_nl0iO001i_dataout; + wire_nl0iO01O_dataout <= wire_nl0iO0ll_o(0) WHEN ni01lll = '1' ELSE nl0ill0O; + wire_nl0iO01Oi_dataout <= wire_w_lg_niOi0Oill52127w(0) OR niOi0OilO; + wire_nl0iO01Ol_dataout <= wire_nl0iO0i1l_dataout WHEN niOi0OilO = '1' ELSE wire_nl0iO001l_dataout; + wire_nl0iO01OO_dataout <= wire_nl0iO0i1i_dataout WHEN niOi0Oill = '1' ELSE nl0ilOliO; + wire_nl0iO0i0i_dataout <= wire_nl0l0i10l_dataout AND niOii011l; + wire_nl0iO0i0l_dataout <= wire_nl0l0i10O_dataout AND niOii011l; + wire_nl0iO0i0O_dataout <= wire_nl0l0i1il_dataout AND niOii011l; + wire_nl0iO0i1i_dataout <= wire_nl0iO0ili_dataout AND niOi0Ol1O; + wire_nl0iO0i1l_dataout <= wire_nl0iO0iOi_dataout AND niOi0Ol1O; + wire_nl0iO0i1O_dataout <= wire_nl0iO0l1i_dataout AND niOi0Ol1O; + wire_nl0iO0ii_dataout <= wire_nl0iO0ll_o(4) WHEN ni01lll = '1' ELSE nl0illli; + wire_nl0iO0iii_dataout <= nl11i10l WHEN niOi0Ol0i = '1' ELSE wire_nl0iO0iil_dataout; + wire_nl0iO0iil_dataout <= nl110llO WHEN niOi0Ol0l = '1' ELSE wire_nl0iO0iiO_dataout; + wire_nl0iO0iiO_dataout <= nl110i0i WHEN niOi0Ol0O = '1' ELSE nl1101ll; + wire_nl0iO0il_dataout <= wire_nl0iO0ll_o(5) WHEN ni01lll = '1' ELSE nl0illll; + wire_nl0iO0ili_dataout <= nl110llO WHEN niOi0Ol0i = '1' ELSE wire_nl0iO0ill_dataout; + wire_nl0iO0ill_dataout <= nl110i0i WHEN niOi0Ol0l = '1' ELSE wire_nl0iO0ilO_dataout; + wire_nl0iO0ilO_dataout <= nl1101ll WHEN niOi0Ol0O = '1' ELSE nl11i10l; + wire_nl0iO0iO_dataout <= wire_nl0iO0ll_o(6) WHEN ni01lll = '1' ELSE nl0illlO; + wire_nl0iO0iOi_dataout <= nl110i0i WHEN niOi0Ol0i = '1' ELSE wire_nl0iO0iOl_dataout; + wire_nl0iO0iOl_dataout <= nl1101ll WHEN niOi0Ol0l = '1' ELSE wire_nl0iO0iOO_dataout; + wire_nl0iO0iOO_dataout <= nl11i10l WHEN niOi0Ol0O = '1' ELSE nl110llO; + wire_nl0iO0l0i_dataout <= nl0ilOllO WHEN niOii1OOO = '1' ELSE wire_nl0iO0O1l_dataout; + wire_nl0iO0l0l_dataout <= nl0iO0Oii WHEN niOii1OOO = '1' ELSE wire_nl0iO0O1O_dataout; + wire_nl0iO0l0O_dataout <= nl0iO0Oil WHEN niOii1OOO = '1' ELSE wire_nl0iO0O0i_dataout; + wire_nl0iO0l1i_dataout <= nl1101ll WHEN niOi0Ol0i = '1' ELSE wire_nl0iO0l1l_dataout; + wire_nl0iO0l1l_dataout <= nl11i10l WHEN niOi0Ol0l = '1' ELSE wire_nl0iO0l1O_dataout; + wire_nl0iO0l1O_dataout <= nl110llO WHEN niOi0Ol0O = '1' ELSE nl110i0i; + wire_nl0iO0li_dataout <= wire_nl0iO0ll_o(7) WHEN ni01lll = '1' ELSE nl0illOi; + wire_nl0iO0lii_dataout <= nl0iO0OiO WHEN niOii1OOO = '1' ELSE wire_nl0iO0O0l_dataout; + wire_nl0iO0lil_dataout <= nl0iO0Oli WHEN niOii1OOO = '1' ELSE wire_nl0iO0O0O_dataout; + wire_nl0iO0liO_dataout <= nl0OOO01l WHEN niOii1OOO = '1' ELSE nl0iO0Oll; + wire_nl0iO0lli_dataout <= nl0OOO01O WHEN niOii1OOO = '1' ELSE nl0iO0OlO; + wire_nl0iO0lll_dataout <= nl0OOO00i WHEN niOii1OOO = '1' ELSE nl0iO0OOi; + wire_nl0iO0llO_dataout <= nl0OOO00l WHEN niOii1OOO = '1' ELSE nl0iO0OOl; + wire_nl0iO0lOi_dataout <= nl0OOO00O WHEN niOii1OOO = '1' ELSE nl0iO0OOO; + wire_nl0iO0lOl_dataout <= nl0OOO0ii WHEN niOii1OOO = '1' ELSE nl0iOi11i; + wire_nl0iO0lOO_dataout <= nl0OOO0il WHEN niOii1OOO = '1' ELSE nl0iOi11l; + wire_nl0iO0O0i_dataout <= k_dev(2) WHEN niOi0Olii = '1' ELSE nl0iO0Oil; + wire_nl0iO0O0l_dataout <= k_dev(3) WHEN niOi0Olii = '1' ELSE nl0iO0OiO; + wire_nl0iO0O0O_dataout <= k_dev(4) WHEN niOi0Olii = '1' ELSE nl0iO0Oli; + wire_nl0iO0O1i_dataout <= nl0OOO0iO WHEN niOii1OOO = '1' ELSE nl0iOi11O; + wire_nl0iO0O1l_dataout <= k_dev(0) WHEN niOi0Olii = '1' ELSE nl0ilOllO; + wire_nl0iO0O1O_dataout <= k_dev(1) WHEN niOi0Olii = '1' ELSE nl0iO0Oii; + wire_nl0iO100i_dataout <= wire_nl0iO10lO_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO100l_dataout <= wire_nl0iO10Oi_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO100O_dataout <= wire_nl0iO10Ol_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO101i_dataout <= wire_nl0iO1i0l_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO101l_dataout <= wire_nl0iO10li_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO101O_dataout <= wire_nl0iO10ll_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO10i_dataout <= wire_nl0iO0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iO10ii_dataout <= wire_nl0iO10OO_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO10il_dataout <= wire_nl0iO1i1i_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO10iO_dataout <= wire_nl0iO1i1l_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO10l_dataout <= wire_nl0iO01l_o(0) WHEN ni1lOOl = '1' ELSE nl0il1li; + wire_nl0iO10li_dataout <= wire_nl0iO1iil_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOl1O; + wire_nl0iO10ll_dataout <= wire_nl0iO1iiO_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOl0i; + wire_nl0iO10lO_dataout <= wire_nl0iO1ili_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOl0l; + wire_nl0iO10O_dataout <= wire_nl0iO01l_o(1) WHEN ni1lOOl = '1' ELSE nl0ilili; + wire_nl0iO10Oi_dataout <= wire_nl0iO1ill_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOl0O; + wire_nl0iO10Ol_dataout <= wire_nl0iO1ilO_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOlii; + wire_nl0iO10OO_dataout <= wire_nl0iO1iOi_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOlil; + wire_nl0iO110i_dataout <= wire_nl0iO100i_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO110l_dataout <= wire_nl0iO100l_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO110O_dataout <= wire_nl0iO100O_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO111i_dataout <= wire_nl0iO101i_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO111l_dataout <= wire_nl0iO101l_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO111O_dataout <= wire_nl0iO101O_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO11i_dataout <= wire_nl0iO0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iO11ii_dataout <= wire_nl0iO10ii_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO11il_dataout <= wire_nl0iO10il_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO11iO_dataout <= wire_nl0iO10iO_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO11l_dataout <= wire_nl0iO0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iO11li_dataout <= wire_nl0iO001O_dataout AND NOT(wire_w_lg_niOii1OOl52072w(0)); + wire_nl0iO11O_dataout <= wire_nl0iO0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iO11Oi_dataout <= nl0ilOiOl WHEN wire_niO1110l_w_lg_dataout44125w(0) = '1' ELSE wire_nl0iO1i0O_dataout; + wire_nl0iO11Ol_dataout <= wire_nl0iO1i1O_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO11OO_dataout <= wire_nl0iO1i0i_dataout AND NOT(wire_niO1110l_w_lg_dataout44125w(0)); + wire_nl0iO1i0i_dataout <= wire_nl0iO1l1l_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOl1i; + wire_nl0iO1i0l_dataout <= wire_nl0iO1l1O_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOl1l; + wire_nl0iO1i0O_dataout <= wire_nl0iO1iii_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOiOl; + wire_nl0iO1i1i_dataout <= wire_nl0iO1iOl_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOliO; + wire_nl0iO1i1l_dataout <= wire_nl0iO1iOO_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOlli; + wire_nl0iO1i1O_dataout <= wire_nl0iO1l1i_dataout WHEN niOi0OiiO = '1' ELSE nl0ilOiOO; + wire_nl0iO1ii_dataout <= wire_nl0iO01l_o(2) WHEN ni1lOOl = '1' ELSE nl0ilill; + wire_nl0iO1iii_dataout <= wire_nl0iO1l0i_dataout OR niOi0Ol1l; + wire_nl0iO1iil_dataout <= wire_nl0l0i1iO_dataout WHEN niOi0Ol1l = '1' ELSE nl0ilOl1O; + wire_nl0iO1iiO_dataout <= nl0ilOl0i WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1l0l_dataout; + wire_nl0iO1il_dataout <= wire_nl0iO01l_o(3) WHEN ni1lOOl = '1' ELSE nl0ililO; + wire_nl0iO1ili_dataout <= nl0ilOl0l WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1l0O_dataout; + wire_nl0iO1ill_dataout <= nl0ilOl0O WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1lii_dataout; + wire_nl0iO1ilO_dataout <= nl0ilOlii WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1lil_dataout; + wire_nl0iO1iO_dataout <= wire_nl0iO01l_o(4) WHEN ni1lOOl = '1' ELSE nl0iliOi; + wire_nl0iO1iOi_dataout <= nl0ilOlil WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1liO_dataout; + wire_nl0iO1iOl_dataout <= nl0ilOliO WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1lli_dataout; + wire_nl0iO1iOO_dataout <= nl0ilOlli WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1lll_dataout; + wire_nl0iO1l0i_dataout <= wire_nl0iO1lOO_dataout OR niOi0Ol1i; + wire_nl0iO1l0l_dataout <= wire_nl0iO0i0O_dataout WHEN niOi0Ol1i = '1' ELSE nl0ilOl0i; + wire_nl0iO1l0O_dataout <= nl0ilOl0l WHEN niOi0Ol1i = '1' ELSE wire_nl0iO1O1i_dataout; + wire_nl0iO1l1i_dataout <= wire_nl0iO1llO_dataout AND NOT(niOi0Ol1l); + wire_nl0iO1l1l_dataout <= wire_nl0iO1lOi_dataout AND NOT(niOi0Ol1l); + wire_nl0iO1l1O_dataout <= wire_nl0l0i1iO_dataout WHEN niOi0Ol1l = '1' ELSE wire_nl0iO1lOl_dataout; + wire_nl0iO1li_dataout <= wire_nl0iO01l_o(5) WHEN ni1lOOl = '1' ELSE nl0iliOl; + wire_nl0iO1lii_dataout <= nl0ilOl0O WHEN niOi0Ol1i = '1' ELSE wire_nl0iO1O1l_dataout; + wire_nl0iO1lil_dataout <= nl0ilOlii WHEN niOi0Ol1i = '1' ELSE wire_nl0iO1O1O_dataout; + wire_nl0iO1liO_dataout <= nl0ilOlil WHEN niOi0Ol1i = '1' ELSE wire_nl0iO1O0i_dataout; + wire_nl0iO1ll_dataout <= wire_nl0iO01l_o(6) WHEN ni1lOOl = '1' ELSE nl0iliOO; + wire_nl0iO1lli_dataout <= nl0ilOliO WHEN niOi0Ol1i = '1' ELSE wire_nl0iO1O0l_dataout; + wire_nl0iO1lll_dataout <= nl0ilOlli WHEN niOi0Ol1i = '1' ELSE wire_nl0iO1O0O_dataout; + wire_nl0iO1llO_dataout <= wire_nl0iO1Oii_dataout OR niOi0Ol1i; + wire_nl0iO1lO_dataout <= wire_nl0iO01l_o(7) WHEN ni1lOOl = '1' ELSE nl0ill1i; + wire_nl0iO1lOi_dataout <= wire_nl0iO1Oil_dataout AND NOT(niOi0Ol1i); + wire_nl0iO1lOl_dataout <= wire_nl0iO0i0O_dataout WHEN niOi0Ol1i = '1' ELSE wire_nl0iO1OiO_dataout; + wire_nl0iO1lOO_dataout <= niOi0OiOl OR niOi0OiOO; + wire_nl0iO1O0i_dataout <= nl0ilOlil WHEN niOi0OiOO = '1' ELSE wire_nl0iO1OlO_dataout; + wire_nl0iO1O0l_dataout <= nl0ilOliO WHEN niOi0OiOO = '1' ELSE wire_nl0iO1OOi_dataout; + wire_nl0iO1O0O_dataout <= nl0ilOlli WHEN niOi0OiOO = '1' ELSE wire_nl0iO1OOl_dataout; + wire_nl0iO1O1i_dataout <= wire_nl0iO0i0l_dataout WHEN niOi0OiOO = '1' ELSE nl0ilOl0l; + wire_nl0iO1O1l_dataout <= nl0ilOl0O WHEN niOi0OiOO = '1' ELSE wire_nl0iO1Oli_dataout; + wire_nl0iO1O1O_dataout <= nl0ilOlii WHEN niOi0OiOO = '1' ELSE wire_nl0iO1Oll_dataout; + wire_nl0iO1Oi_dataout <= wire_nl0iO01l_o(8) WHEN ni1lOOl = '1' ELSE nl0ill1l; + wire_nl0iO1Oii_dataout <= wire_nl0iO1OOO_dataout AND NOT(niOi0OiOO); + wire_nl0iO1Oil_dataout <= wire_nl0iO011i_dataout OR niOi0OiOO; + wire_nl0iO1OiO_dataout <= wire_nl0iO0i0l_dataout WHEN niOi0OiOO = '1' ELSE wire_nl0iO011l_dataout; + wire_nl0iO1Ol_dataout <= wire_nl0iO01l_o(9) WHEN ni1lOOl = '1' ELSE nl0ill1O; + wire_nl0iO1Oli_dataout <= wire_nl0iO0i0i_dataout WHEN niOi0OiOl = '1' ELSE nl0ilOl0O; + wire_nl0iO1Oll_dataout <= nl0ilOlii WHEN niOi0OiOl = '1' ELSE wire_nl0iO011O_dataout; + wire_nl0iO1OlO_dataout <= nl0ilOlil WHEN niOi0OiOl = '1' ELSE wire_nl0iO010i_dataout; + wire_nl0iO1OO_dataout <= wire_nl0iO01l_o(10) WHEN ni1lOOl = '1' ELSE nl0ill0i; + wire_nl0iO1OOi_dataout <= nl0ilOliO WHEN niOi0OiOl = '1' ELSE wire_nl0iO010l_dataout; + wire_nl0iO1OOl_dataout <= nl0ilOlli WHEN niOi0OiOl = '1' ELSE wire_nl0iO010O_dataout; + wire_nl0iO1OOO_dataout <= wire_nl0iO01ii_dataout OR niOi0OiOl; + wire_nl0iOi00i_dataout <= wire_nl0l0110i_dataout WHEN niOi0Olil = '1' ELSE nl0iO0Oii; + wire_nl0iOi00l_dataout <= wire_nl0l0110l_dataout WHEN niOi0Olil = '1' ELSE nl0iO0Oil; + wire_nl0iOi00O_dataout <= wire_nl0l0110O_dataout WHEN niOi0Olil = '1' ELSE nl0iO0OiO; + wire_nl0iOi01i_dataout <= wire_nl0iOi0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi01l_dataout <= wire_nl0iOi0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi01O_dataout <= wire_nl0l0111O_dataout WHEN niOi0Olil = '1' ELSE nl0ilOllO; + wire_nl0iOi0ii_dataout <= wire_nl0l011ii_dataout WHEN niOi0Olil = '1' ELSE nl0iO0Oli; + wire_nl0iOi0il_dataout <= wire_nl0iOii1i_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iO0Oll; + wire_nl0iOi0iO_dataout <= wire_nl0iOii1l_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iO0OlO; + wire_nl0iOi0li_dataout <= wire_nl0iOii1O_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iO0OOi; + wire_nl0iOi0ll_dataout <= wire_nl0iOii0i_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iO0OOl; + wire_nl0iOi0lO_dataout <= wire_nl0iOii0l_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iO0OOO; + wire_nl0iOi0Oi_dataout <= wire_nl0iOii0O_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iOi11i; + wire_nl0iOi0Ol_dataout <= wire_nl0iOiiii_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iOi11l; + wire_nl0iOi0OO_dataout <= wire_nl0iOiiil_dataout WHEN wire_w_lg_niOii1OOO52111w(0) = '1' ELSE nl0iOi11O; + wire_nl0iOi10l_dataout <= wire_nl0iOi01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi10O_dataout <= wire_nl0iOi00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1ii_dataout <= wire_nl0iOi00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1il_dataout <= wire_nl0iOi00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1iO_dataout <= wire_nl0iOi0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1li_dataout <= wire_nl0iOi0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1ll_dataout <= wire_nl0iOi0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1lO_dataout <= wire_nl0iOi0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1Oi_dataout <= wire_nl0iOi0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1Ol_dataout <= wire_nl0iOi0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOi1OO_dataout <= wire_nl0iOi0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOii0i_dataout <= wire_nl0l011ll_dataout WHEN niOi0Olil = '1' ELSE nl0iO0OOl; + wire_nl0iOii0l_dataout <= wire_nl0l011lO_dataout WHEN niOi0Olil = '1' ELSE nl0iO0OOO; + wire_nl0iOii0O_dataout <= wire_nl0l011Oi_dataout WHEN niOi0Olil = '1' ELSE nl0iOi11i; + wire_nl0iOii1i_dataout <= wire_nl0l011il_dataout WHEN niOi0Olil = '1' ELSE nl0iO0Oll; + wire_nl0iOii1l_dataout <= wire_nl0l011iO_dataout WHEN niOi0Olil = '1' ELSE nl0iO0OlO; + wire_nl0iOii1O_dataout <= wire_nl0l011li_dataout WHEN niOi0Olil = '1' ELSE nl0iO0OOi; + wire_nl0iOiiii_dataout <= wire_nl0l011Ol_dataout WHEN niOi0Olil = '1' ELSE nl0iOi11l; + wire_nl0iOiiil_dataout <= wire_nl0l011OO_dataout WHEN niOi0Olil = '1' ELSE nl0iOi11O; + wire_nl0iOl00i_dataout <= wire_nl0iOlllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl00l_dataout <= wire_nl0iOllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl00O_dataout <= wire_nl0iOllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl01i_dataout <= wire_nl0iOlliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl01l_dataout <= wire_nl0iOllli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl01O_dataout <= wire_nl0iOllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0i_dataout <= wire_nl0l00li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOl0ii_dataout <= wire_nl0iOllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0il_dataout <= wire_nl0iOlO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0iO_dataout <= wire_nl0iOlO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0l_dataout <= wire_nl0l00Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOl0li_dataout <= wire_nl0iOlO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0ll_dataout <= wire_nl0iOlO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0lO_dataout <= wire_nl0iOlO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0O_dataout <= wire_nl0iOOll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOl0Oi_dataout <= wire_nl0iOlO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0Ol_dataout <= wire_nl0iOlOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl0OO_dataout <= wire_nl0iOlOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl10l_dataout <= wire_nl0iOliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl10O_dataout <= wire_nl0iOll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1ii_dataout <= wire_nl0iOll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1il_dataout <= wire_nl0iOll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1iO_dataout <= wire_nl0iOll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1li_dataout <= (wire_w_lg_niOii1l0i52104w(0) OR wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l1010l52106w52107w52108w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1ll_dataout <= ((niOii1l0i AND niOi0Olli) OR wire_nlill0Oll_w_lg_w_lg_w_lg_nl0l1010l52099w52100w52101w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1lO_dataout <= wire_nl0iOll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1Oi_dataout <= wire_nl0iOll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1Ol_dataout <= wire_nl0iOllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOl1OO_dataout <= wire_nl0iOllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOli0i_dataout <= wire_nl0iOlOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOli0l_dataout <= wire_nl0iOlOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOli0O_dataout <= wire_nl0iOlOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOli1i_dataout <= wire_nl0iOlOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOli1l_dataout <= wire_nl0iOlOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOli1O_dataout <= wire_nl0iOlOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOlii_dataout <= wire_nl0iOOlO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOliii_dataout <= wire_nl0iOlOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOliil_dataout <= wire_nl0iOO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOliiO_dataout <= wire_nl0iOO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOlil_dataout <= wire_nl0iOOOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOlili_dataout <= wire_nl0iOO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOlill_dataout <= wire_nl0iOO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOlilO_dataout <= wire_nl0iOO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOliO_dataout <= wire_nl0iOOOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOliOi_dataout <= wire_nl0iOO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOliOl_dataout <= wire_nl0iOO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0iOliOO_dataout <= niOii1l1l AND NOT(niOii1liO); + wire_nl0iOll0i_dataout <= niOi0OlOl WHEN niOii1liO = '1' ELSE wire_nl0iOO1ll_dataout; + wire_nl0iOll0l_dataout <= wire_nl0l1Oi1l_dataout WHEN niOii1liO = '1' ELSE wire_nl0iOO1lO_dataout; + wire_nl0iOll0O_dataout <= wire_nl0l1Oi1O_dataout WHEN niOii1liO = '1' ELSE wire_nl0iOO1Oi_dataout; + wire_nl0iOll1i_dataout <= niOi0Olll WHEN niOii1liO = '1' ELSE wire_nl0iOO1il_dataout; + wire_nl0iOll1l_dataout <= niOi0OllO WHEN niOii1liO = '1' ELSE wire_nl0iOO1iO_dataout; + wire_nl0iOll1O_dataout <= niOi0OlOi WHEN niOii1liO = '1' ELSE wire_nl0iOO1li_dataout; + wire_nl0iOlli_dataout <= wire_nl0iOOOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOllii_dataout <= wire_nl0l1Oi0i_dataout WHEN niOii1liO = '1' ELSE wire_nl0iOO1Ol_dataout; + wire_nl0iOllil_dataout <= wire_nl0l1Oi0l_dataout WHEN niOii1liO = '1' ELSE wire_nl0iOO1OO_dataout; + wire_nl0iOlliO_dataout <= niOi0OlOO WHEN niOii1liO = '1' ELSE wire_nl0iOO01i_dataout; + wire_nl0iOlll_dataout <= wire_nl0l111i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOllli_dataout <= niOi0OO1i WHEN niOii1liO = '1' ELSE wire_nl0iOO01l_dataout; + wire_nl0iOllll_dataout <= niOi0OO1l WHEN niOii1liO = '1' ELSE wire_nl0iOO01O_dataout; + wire_nl0iOlllO_dataout <= niOi0OO1O WHEN niOii1liO = '1' ELSE wire_nl0iOO00i_dataout; + wire_nl0iOllO_dataout <= wire_nl0l111l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOllOi_dataout <= niOi0OO0i WHEN niOii1liO = '1' ELSE wire_nl0iOO00l_dataout; + wire_nl0iOllOl_dataout <= niOi0OO0l WHEN niOii1liO = '1' ELSE wire_nl0iOO00O_dataout; + wire_nl0iOllOO_dataout <= niOi0OO0O WHEN niOii1liO = '1' ELSE wire_nl0iOO0ii_dataout; + wire_nl0iOlO0i_dataout <= niOi0OOli WHEN niOii1liO = '1' ELSE wire_nl0iOO0ll_dataout; + wire_nl0iOlO0l_dataout <= niOi0OOll WHEN niOii1liO = '1' ELSE wire_nl0iOO0lO_dataout; + wire_nl0iOlO0O_dataout <= niOi0OOlO WHEN niOii1liO = '1' ELSE wire_nl0iOO0Oi_dataout; + wire_nl0iOlO1i_dataout <= niOi0OOii WHEN niOii1liO = '1' ELSE wire_nl0iOO0il_dataout; + wire_nl0iOlO1l_dataout <= niOi0OOil WHEN niOii1liO = '1' ELSE wire_nl0iOO0iO_dataout; + wire_nl0iOlO1O_dataout <= niOi0OOiO WHEN niOii1liO = '1' ELSE wire_nl0iOO0li_dataout; + wire_nl0iOlOi_dataout <= wire_nl0l111O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOlOii_dataout <= niOi0OOOi WHEN niOii1liO = '1' ELSE wire_nl0iOO0Ol_dataout; + wire_nl0iOlOil_dataout <= niOi0OOOl WHEN niOii1liO = '1' ELSE wire_nl0iOO0OO_dataout; + wire_nl0iOlOiO_dataout <= niOi0OOOO WHEN niOii1liO = '1' ELSE wire_nl0iOOi1i_dataout; + wire_nl0iOlOl_dataout <= wire_nl0l110i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOlOli_dataout <= niOii111i WHEN niOii1liO = '1' ELSE wire_nl0iOOi1l_dataout; + wire_nl0iOlOll_dataout <= niOii111l WHEN niOii1liO = '1' ELSE wire_nl0iOOi1O_dataout; + wire_nl0iOlOlO_dataout <= niOii111O WHEN niOii1liO = '1' ELSE wire_nl0iOOi0i_dataout; + wire_nl0iOlOO_dataout <= wire_nl0l110l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOlOOi_dataout <= niOii110i WHEN niOii1liO = '1' ELSE wire_nl0iOOi0l_dataout; + wire_nl0iOlOOl_dataout <= niOii110l WHEN niOii1liO = '1' ELSE wire_nl0iOOi0O_dataout; + wire_nl0iOlOOO_dataout <= niOii110O WHEN niOii1liO = '1' ELSE wire_nl0iOOiii_dataout; + wire_nl0iOO00i_dataout <= niOii100O WHEN niOii1l1l = '1' ELSE nl0iOilil; + wire_nl0iOO00l_dataout <= niOii10ii WHEN niOii1l1l = '1' ELSE nl0iOiliO; + wire_nl0iOO00O_dataout <= niOii10il WHEN niOii1l1l = '1' ELSE nl0iOilli; + wire_nl0iOO01i_dataout <= niOii101O WHEN niOii1l1l = '1' ELSE nl0iOil0l; + wire_nl0iOO01l_dataout <= niOii100i WHEN niOii1l1l = '1' ELSE nl0iOil0O; + wire_nl0iOO01O_dataout <= niOii100l WHEN niOii1l1l = '1' ELSE nl0iOilii; + wire_nl0iOO0i_dataout <= wire_nl0l11iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOO0ii_dataout <= niOii10iO WHEN niOii1l1l = '1' ELSE nl0iOilll; + wire_nl0iOO0il_dataout <= niOii10li WHEN niOii1l1l = '1' ELSE nl0iOillO; + wire_nl0iOO0iO_dataout <= niOii10ll WHEN niOii1l1l = '1' ELSE nl0iOilOi; + wire_nl0iOO0l_dataout <= wire_nl0l11li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOO0li_dataout <= niOii10lO WHEN niOii1l1l = '1' ELSE nl0iOilOl; + wire_nl0iOO0ll_dataout <= niOii10Oi WHEN niOii1l1l = '1' ELSE nl0iOilOO; + wire_nl0iOO0lO_dataout <= niOii10Ol WHEN niOii1l1l = '1' ELSE nl0iOiO1i; + wire_nl0iOO0O_dataout <= wire_nl0l11ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOO0Oi_dataout <= niOii10OO WHEN niOii1l1l = '1' ELSE nl0iOiO1l; + wire_nl0iOO0Ol_dataout <= niOii1i1i WHEN niOii1l1l = '1' ELSE nl0iOiO1O; + wire_nl0iOO0OO_dataout <= niOii1i1l WHEN niOii1l1l = '1' ELSE nl0iOiO0i; + wire_nl0iOO10i_dataout <= niOii11li WHEN niOii1liO = '1' ELSE wire_nl0iOOill_dataout; + wire_nl0iOO10l_dataout <= niOii11ll WHEN niOii1liO = '1' ELSE wire_nl0iOOilO_dataout; + wire_nl0iOO10O_dataout <= niOii11lO WHEN niOii1liO = '1' ELSE wire_nl0iOOiOi_dataout; + wire_nl0iOO11i_dataout <= niOii11ii WHEN niOii1liO = '1' ELSE wire_nl0iOOiil_dataout; + wire_nl0iOO11l_dataout <= niOii11il WHEN niOii1liO = '1' ELSE wire_nl0iOOiiO_dataout; + wire_nl0iOO11O_dataout <= niOii11iO WHEN niOii1liO = '1' ELSE wire_nl0iOOili_dataout; + wire_nl0iOO1i_dataout <= wire_nl0l110O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOO1ii_dataout <= niOii11Oi WHEN niOii1liO = '1' ELSE wire_nl0iOOiOl_dataout; + wire_nl0iOO1il_dataout <= niOii11Ol WHEN niOii1l1l = '1' ELSE nl0iOiill; + wire_nl0iOO1iO_dataout <= niOii11OO WHEN niOii1l1l = '1' ELSE nl0iOiiOi; + wire_nl0iOO1l_dataout <= wire_nl0l11ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOO1li_dataout <= niOii101i WHEN niOii1l1l = '1' ELSE nl0iOiili; + wire_nl0iOO1ll_dataout <= niOii101l WHEN niOii1l1l = '1' ELSE nl0iOiilO; + wire_nl0iOO1lO_dataout <= nl0iOil1i OR niOii1l1l; + wire_nl0iOO1O_dataout <= wire_nl0l11il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOO1Oi_dataout <= nl0iOil1l OR niOii1l1l; + wire_nl0iOO1Ol_dataout <= nl0iOil1O OR niOii1l1l; + wire_nl0iOO1OO_dataout <= nl0iOil0i OR niOii1l1l; + wire_nl0iOOi0i_dataout <= niOii1i0O WHEN niOii1l1l = '1' ELSE nl0iOiOil; + wire_nl0iOOi0l_dataout <= niOii1iii WHEN niOii1l1l = '1' ELSE nl0iOiOiO; + wire_nl0iOOi0O_dataout <= niOii1iil WHEN niOii1l1l = '1' ELSE nl0iOiOli; + wire_nl0iOOi1i_dataout <= niOii1i1O WHEN niOii1l1l = '1' ELSE nl0iOiO0l; + wire_nl0iOOi1l_dataout <= niOii1i0i WHEN niOii1l1l = '1' ELSE nl0iOiO0O; + wire_nl0iOOi1O_dataout <= niOii1i0l WHEN niOii1l1l = '1' ELSE nl0iOiOii; + wire_nl0iOOii_dataout <= wire_nl0l11lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOOiii_dataout <= niOii1iiO WHEN niOii1l1l = '1' ELSE nl0iOiOll; + wire_nl0iOOiil_dataout <= niOii1ili WHEN niOii1l1l = '1' ELSE nl0iOiOlO; + wire_nl0iOOiiO_dataout <= niOii1ill WHEN niOii1l1l = '1' ELSE nl0iOiOOi; + wire_nl0iOOil_dataout <= wire_nl0l11Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOOili_dataout <= niOii1ilO WHEN niOii1l1l = '1' ELSE nl0iOiOOl; + wire_nl0iOOill_dataout <= niOii1iOi WHEN niOii1l1l = '1' ELSE nl0iOiOOO; + wire_nl0iOOilO_dataout <= niOii1iOl WHEN niOii1l1l = '1' ELSE nl0iOl11i; + wire_nl0iOOiO_dataout <= wire_nl0l11Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOOiOi_dataout <= niOii1iOO WHEN niOii1l1l = '1' ELSE nl0iOl11l; + wire_nl0iOOiOl_dataout <= niOii1l1i WHEN niOii1l1l = '1' ELSE nl0iOl11O; + wire_nl0iOOli_dataout <= wire_nl0l11OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0iOOll_dataout <= wire_nl0l010l_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l101i_dataout; + wire_nl0iOOlO_dataout <= wire_nl0l010O_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l101l_dataout; + wire_nl0iOOOi_dataout <= wire_nl0l01ii_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l101O_dataout; + wire_nl0iOOOl_dataout <= wire_nl0l01il_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l100i_dataout; + wire_nl0iOOOO_dataout <= wire_nl0l01iO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l100l_dataout; + wire_nl0l0000i_dataout <= wire_nl0l00iii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0000l_dataout <= wire_nl0l00ili_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0000O_dataout <= wire_nl0l000ii_dataout OR wire_nli0Ol10i_dataout; + wire_nl0l0001i_dataout <= wire_nl0l000lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0001l_dataout <= wire_nl0l00i1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0001O_dataout <= wire_nl0l00i0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l000i_dataout <= nl0O1iil WHEN niOO1O10i = '1' ELSE nl0iOilO; + wire_nl0l000ii_dataout <= nl0l000ll AND NOT((wire_nl0l1O01O_dataout AND niOii011O)); + wire_nl0l000l_dataout <= nl0O1iiO WHEN niOO1O10i = '1' ELSE nl0iOiOi; + wire_nl0l000lO_dataout <= wire_nl0l000Oi_dataout OR (nl0l00iOl AND wire_nli0Ol1il_dataout); + wire_nl0l000O_dataout <= nl0O1ili WHEN niOO1O10i = '1' ELSE nl0iOiOl; + wire_nl0l000Oi_dataout <= nl0l001iO AND NOT((wire_nl0l1O01l_dataout AND niOii011O)); + wire_nl0l001i_dataout <= nl0O1i0l WHEN niOO1O10i = '1' ELSE nl0iOiiO; + wire_nl0l001l_dataout <= nl0O1i0O WHEN niOO1O10i = '1' ELSE nl0iOili; + wire_nl0l001O_dataout <= nl0O1iii WHEN niOO1O10i = '1' ELSE nl0iOill; + wire_nl0l001OO_dataout <= wire_nl0l0000O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l00i0i_dataout <= wire_nl0l00i0l_dataout OR wire_nli0Ol0li_dataout; + wire_nl0l00i0l_dataout <= nl0l001ll AND NOT((wire_nl0l1O1OO_dataout AND niOii011O)); + wire_nl0l00i1i_dataout <= wire_nl0l00i1l_dataout OR wire_nli0Ol01O_dataout; + wire_nl0l00i1l_dataout <= nl0l001li AND NOT((wire_nl0l1O01i_dataout AND niOii011O)); + wire_nl0l00ii_dataout <= nl0O1ill WHEN niOO1O10i = '1' ELSE nl0iOiOO; + wire_nl0l00iii_dataout <= wire_nl0l00iil_dataout OR wire_nli0Ol0Ol_dataout; + wire_nl0l00iil_dataout <= nl0l001lO AND NOT((wire_nl0l1O1Ol_dataout AND niOii011O)); + wire_nl0l00il_dataout <= nl0O1ilO WHEN niOO1O10i = '1' ELSE nl0iOl1i; + wire_nl0l00ili_dataout <= wire_nl0l00ill_dataout OR (nl0l00iOO AND wire_nli0Oli0l_dataout); + wire_nl0l00ill_dataout <= nl0l001Oi AND NOT((wire_nl0l1O1ll_dataout AND niOii011O)); + wire_nl0l00iO_dataout <= nl0O1iOi WHEN niOO1O10i = '1' ELSE nl0iOl1l; + wire_nl0l00l0i_dataout <= wire_nl0l00lli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l00l0l_dataout <= wire_nl0l00lll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l00l0O_dataout <= wire_nl0l00lOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l00li_dataout <= nl0illOl OR ((niOO1O1ii AND niOO1O00l) OR (niOO1O10l AND niOO1O00i)); + wire_nl0l00lii_dataout <= wire_nl0l00lOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l00lil_dataout <= wire_nl0l00lOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l00liO_dataout <= wire_nl0l00O1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l00lli_dataout <= wire_nl0l1lOlO_dataout WHEN niOii010i = '1' ELSE nl0l001Ol; + wire_nl0l00lll_dataout <= wire_nl0l1lOli_dataout WHEN niOii010i = '1' ELSE nl0l00iOl; + wire_nl0l00lOi_dataout <= wire_nl0l1lOil_dataout WHEN niOii010l = '1' ELSE nl0l00iOO; + wire_nl0l00lOl_dataout <= wire_nl0l1lO0i_dataout WHEN niOii010l = '1' ELSE nl0l00l1i; + wire_nl0l00lOO_dataout <= wire_nl0l1lO1O_dataout WHEN niOii010l = '1' ELSE nl0l00l1l; + wire_nl0l00O1i_dataout <= (wire_nl0l1lO1l_dataout AND (((wire_w_lg_w_k_bar_range45915w51988w(0) OR wire_w_lg_w_k_bar_range47787w51990w(0)) OR wire_w_lg_w_k_bar_range48482w48878w(0)) OR (k_bar(224) AND k_bar(225)))) WHEN niOii010l = '1' ELSE nl0l00l1O; + wire_nl0l00Ol_dataout <= nl0iO0lO OR ((niOO1O1ii AND niOO1O0ii) OR (niOO1O10l AND niOO1O00O)); + wire_nl0l010l_dataout <= nl0O10iO WHEN niOO1O10i = '1' ELSE nl0iO0Oi; + wire_nl0l010O_dataout <= nl0O10li WHEN niOO1O10i = '1' ELSE nl0iO0Ol; + wire_nl0l0110i_dataout <= wire_nl1lO00iO_dataout WHEN niOii1lll = '1' ELSE nlOiii1O; + wire_nl0l0110l_dataout <= wire_nl1lO00li_dataout WHEN niOii1lll = '1' ELSE nlOiii0i; + wire_nl0l0110O_dataout <= wire_nl1lO00ll_dataout WHEN niOii1lll = '1' ELSE nlOiii0l; + wire_nl0l0111i_dataout <= wire_nl1lO01Ol_dataout WHEN niOii1lll = '1' ELSE nlOii0il; + wire_nl0l0111i_w_lg_dataout52336w(0) <= NOT wire_nl0l0111i_dataout; + wire_nl0l0111l_dataout <= wire_nl1lO01OO_dataout WHEN niOii1lll = '1' ELSE nlOii0iO; + wire_nl0l0111l_w52414w(0) <= wire_nl0l0111l_w_lg_w_lg_w_lg_dataout52335w52337w52339w(0) AND wire_nl0l1OOOl_dataout; + wire_nl0l0111l_w_lg_w_lg_w_lg_dataout52335w52337w52339w(0) <= wire_nl0l0111l_w_lg_w_lg_dataout52335w52337w(0) AND wire_nl0l1OOOO_w_lg_dataout52338w(0); + wire_nl0l0111l_w_lg_w_lg_dataout52335w52337w(0) <= wire_nl0l0111l_w_lg_dataout52335w(0) AND wire_nl0l0111i_w_lg_dataout52336w(0); + wire_nl0l0111l_w_lg_dataout52416w(0) <= wire_nl0l0111l_dataout AND wire_nl0l0111i_w_lg_dataout52336w(0); + wire_nl0l0111l_w_lg_dataout52335w(0) <= NOT wire_nl0l0111l_dataout; + wire_nl0l0111O_dataout <= wire_nl1lO00il_dataout WHEN niOii1lll = '1' ELSE nlOiii1l; + wire_nl0l011ii_dataout <= wire_nl1lO00lO_dataout WHEN niOii1lll = '1' ELSE nlOiii0O; + wire_nl0l011il_dataout <= wire_nl1lO00Oi_dataout WHEN niOii1lll = '1' ELSE nlOiiiii; + wire_nl0l011iO_dataout <= wire_nl1lO00Ol_dataout WHEN niOii1lll = '1' ELSE nlOiiiil; + wire_nl0l011li_dataout <= wire_nl1lO00OO_dataout WHEN niOii1lll = '1' ELSE nlOiiiiO; + wire_nl0l011ll_dataout <= wire_nl1lOOl0O_dataout WHEN niOii1lll = '1' ELSE nlOiiili; + wire_nl0l011lO_dataout <= wire_nl1lOOlii_dataout WHEN niOii1lll = '1' ELSE nlOiiill; + wire_nl0l011Oi_dataout <= wire_nl1lOOlil_dataout WHEN niOii1lll = '1' ELSE nlOiiilO; + wire_nl0l011Ol_dataout <= wire_nl1lOOliO_dataout WHEN niOii1lll = '1' ELSE nlOiiiOi; + wire_nl0l011OO_dataout <= wire_nl1lO0i0l_dataout WHEN niOii1lll = '1' ELSE nlOiiiOl; + wire_nl0l01i0i_dataout <= wire_nl1lOO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l01i0l_dataout <= (niOii1Oil AND niOii1lOi) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01i0O_dataout <= (niOii1Oil AND niOii1lOl) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01i1i_dataout <= (wire_nlill0Oll_w_lg_nl011l1ii52064w(0) AND wire_nlill0Oll_w_lg_nl0l101il52065w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01i1l_dataout <= wire_nl0l01l1i_o(0) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01i1O_dataout <= wire_nl0l01l1i_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01ii_dataout <= nl0O10ll WHEN niOO1O10i = '1' ELSE nl0iO0OO; + wire_nl0l01iii_dataout <= (niOii1Oil AND niOii1lOO) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01iil_dataout <= (niOii1Oil AND niOii1O1i) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01iiO_dataout <= (niOii1Oil AND niOii1O1l) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01il_dataout <= nl0O10lO WHEN niOO1O10i = '1' ELSE nl0iOi1i; + wire_nl0l01ili_dataout <= (niOii1Oil AND niOii1O1O) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01ill_dataout <= (niOii1Oil AND niOii1O0i) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01ilO_dataout <= (niOii1Oil AND niOii1O0l) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01iO_dataout <= nl0O10Oi WHEN niOO1O10i = '1' ELSE nl0iOi1l; + wire_nl0l01iOi_dataout <= ((wire_nl1lOOl0i_w_lg_dataout52050w(0) AND niOii1Oil) AND niOii1O0O) AND NOT(wire_niO01O0O_dataout); + wire_nl0l01iOl_dataout <= wire_nl0l01l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l01l1O_dataout <= nl0l010Ol AND (niOii1Oil AND niOii1Oii); + wire_nl0l01li_dataout <= nl0O10Ol WHEN niOO1O10i = '1' ELSE nl0iOi1O; + wire_nl0l01ll_dataout <= nl0O10OO WHEN niOO1O10i = '1' ELSE nl0iOi0i; + wire_nl0l01lO_dataout <= nl0O1i1i WHEN niOO1O10i = '1' ELSE nl0iOi0l; + wire_nl0l01O0i_dataout <= wire_nl0l01Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l01O0l_dataout <= wire_nl0l01Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l01O0O_dataout <= wire_nl0l01OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l01Oi_dataout <= nl0O1i1l WHEN niOO1O10i = '1' ELSE nl0iOi0O; + wire_nl0l01Oii_dataout <= wire_nl1lO000l_dataout WHEN niOii1Oli = '1' ELSE wire_nl0l01Oli_dataout; + wire_nl0l01Oil_dataout <= wire_nl1lO000O_dataout WHEN niOii1Oli = '1' ELSE wire_nl0l01Oll_dataout; + wire_nl0l01OiO_dataout <= wire_nl1lO00ii_dataout WHEN niOii1Oli = '1' ELSE wire_nl0l01OlO_dataout; + wire_nl0l01Ol_dataout <= nl0O1i1O WHEN niOO1O10i = '1' ELSE nl0iOiii; + wire_nl0l01Oli_dataout <= wire_nl1lO000l_dataout AND wire_nl0l01OOi_o; + wire_nl0l01Oll_dataout <= wire_nl1lO000O_dataout AND wire_nl0l01OOi_o; + wire_nl0l01OlO_dataout <= wire_nl1lO00ii_dataout AND wire_nl0l01OOi_o; + wire_nl0l01OO_dataout <= nl0O1i0i WHEN niOO1O10i = '1' ELSE nl0iOiil; + wire_nl0l0i0lO_dataout <= wire_nl0l0illi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0i0Oi_dataout <= wire_nl0l0il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0i0Ol_dataout <= wire_nl0l0il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0i0OO_dataout <= wire_nl0l0il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0i10l_dataout <= nl0l0i00O AND (((NOT k_conf(225)) AND wire_w_lg_w_k_conf_range46173w46174w(0)) AND k_conf(227)); + wire_nl0l0i10O_dataout <= nl0l0i00O AND ((k_conf(225) AND k_conf(226)) AND (NOT k_conf(227))); + wire_nl0l0i1il_dataout <= nl0l0i00O AND (((NOT k_conf(225)) AND k_conf(226)) AND (NOT k_conf(227))); + wire_nl0l0i1iO_dataout <= nl0l0i00O AND niOii01iO; + wire_nl0l0ii0i_dataout <= wire_nl0l0ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0ii0l_dataout <= wire_nl0l0iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0ii0O_dataout <= wire_nl0l0iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0ii1i_dataout <= wire_nl0l0il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0ii1l_dataout <= wire_nl0l0il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0ii1O_dataout <= wire_nl0l0ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0iiii_dataout <= wire_nl0l0illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0iiil_dataout <= wire_nl0l0illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0iiiO_dataout <= wire_nl0l0ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0iili_dataout <= wire_nl0l0ilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l0iill_dataout <= wire_nl0l0iilO_dataout AND NOT((wire_w_lg_niOii01il51966w(0) OR (wire_nli0O010i_dataout OR nlil1lO1i))); + wire_nl0l0iilO_dataout <= nl0l0i00O OR (wire_nlill0Oll_w_lg_nl0lil11i46544w(0) AND wire_nlill0Oll_w_lg_w_lg_nl0l0Oill46193w51964w(0)); + wire_nl0l0il0i_dataout <= nl0l0i1OO WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iO0i_dataout; + wire_nl0l0il0l_dataout <= nl0l0i01i WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iO0l_dataout; + wire_nl0l0il0O_dataout <= nl0l0i01l WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iO0O_dataout; + wire_nl0l0il1l_dataout <= nl0l0i1Oi WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iO1l_dataout; + wire_nl0l0il1O_dataout <= nl0l0i1Ol WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iO1O_dataout; + wire_nl0l0ilii_dataout <= nl0l0i01O WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iOii_dataout; + wire_nl0l0ilil_dataout <= nl0l0i00i WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iOil_dataout; + wire_nl0l0iliO_dataout <= nl0l0i00l WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iOiO_dataout; + wire_nl0l0ill_dataout <= wire_nl0l0l1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0l0illi_dataout <= nl0l0i1ii WHEN wire_nl0illl1O_dataout = '1' ELSE wire_nl0l0iOll_dataout; + wire_nl0l0illl_dataout <= wire_nl0l0ilOO_dataout AND NOT(wire_nl0illl1O_dataout); + wire_nl0l0illO_dataout <= wire_nl0l0iO1i_dataout AND NOT(wire_nl0illl1O_dataout); + wire_nl0l0ilO_dataout <= wire_nl0l0l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0l0ilOi_dataout <= wire_nl0l0iOli_dataout AND NOT(wire_nl0illl1O_dataout); + wire_nl0l0ilOl_dataout <= wire_nl0l0iOlO_dataout AND NOT(wire_nl0illl1O_dataout); + wire_nl0l0ilOO_dataout <= wire_nl0l0iOOl_dataout WHEN niOii01ii = '1' ELSE nl0l0i0ii; + wire_nl0l0iO0i_dataout <= wire_nl0l0l11O_dataout WHEN niOii01ii = '1' ELSE nl0l0i1OO; + wire_nl0l0iO0l_dataout <= wire_nl0l0l10i_dataout WHEN niOii01ii = '1' ELSE nl0l0i01i; + wire_nl0l0iO0O_dataout <= wire_nl0l0l10l_dataout WHEN niOii01ii = '1' ELSE nl0l0i01l; + wire_nl0l0iO1i_dataout <= wire_nl0l0iOOO_dataout WHEN niOii01ii = '1' ELSE nl0l0i0il; + wire_nl0l0iO1l_dataout <= wire_nl0l0l11i_dataout WHEN niOii01ii = '1' ELSE nl0l0i1Oi; + wire_nl0l0iO1O_dataout <= wire_nl0l0l11l_dataout WHEN niOii01ii = '1' ELSE nl0l0i1Ol; + wire_nl0l0iOi_dataout <= wire_nl0l0l0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0l0iOii_dataout <= wire_nl0l0l10O_dataout WHEN niOii01ii = '1' ELSE nl0l0i01O; + wire_nl0l0iOil_dataout <= wire_nl0l0l1ii_dataout WHEN niOii01ii = '1' ELSE nl0l0i00i; + wire_nl0l0iOiO_dataout <= wire_nl0l0l1il_dataout WHEN niOii01ii = '1' ELSE nl0l0i00l; + wire_nl0l0iOl_dataout <= wire_nl0l0llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0l0iOli_dataout <= wire_nl0l0l1iO_dataout WHEN niOii01ii = '1' ELSE nl0l0i0iO; + wire_nl0l0iOll_dataout <= wire_nl0l0iOOi_dataout WHEN niOii01ii = '1' ELSE nl0l0i1ii; + wire_nl0l0iOlO_dataout <= nl0l0i0li OR niOii01ii; + wire_nl0l0iOO_dataout <= wire_nl0l0lOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0l0iOOi_dataout <= wire_nl0l0l1li_dataout AND NOT(nli0Oi0lO); + wire_nl0l0iOOl_dataout <= nl0l0i0ii WHEN nli0Oi0lO = '1' ELSE wire_nl0l0l1ll_dataout; + wire_nl0l0iOOO_dataout <= nl0l0i0il WHEN nli0Oi0lO = '1' ELSE wire_nl0l0l00l_dataout; + wire_nl0l0l00i_dataout <= nl10iiOi WHEN nli11l0Ol = '1' ELSE ni0llll; + wire_nl0l0l00l_dataout <= nl0l0i0il OR nli11l0Ol; + wire_nl0l0l01i_dataout <= nl10iili WHEN nli11l0Ol = '1' ELSE ni0llil; + wire_nl0l0l01l_dataout <= nl10iill WHEN nli11l0Ol = '1' ELSE ni0lliO; + wire_nl0l0l01O_dataout <= nl10iilO WHEN nli11l0Ol = '1' ELSE ni0llli; + wire_nl0l0l0i_dataout <= wire_nl0l0lii_dataout AND NOT(niOO1O1li); + wire_nl0l0l0l_dataout <= wire_nl0l0Oii_o(1) OR niOO1O1iO; + wire_nl0l0l0O_dataout <= wire_nl0l0Oii_o(2) OR niOO1O1iO; + wire_nl0l0l0Oi_dataout <= nl1011li AND niOii01iO; + wire_nl0l0l0Ol_dataout <= (NOT k_conf(230)) OR k_conf(224); + wire_nl0l0l0Ol_w_lg_dataout46163w(0) <= NOT wire_nl0l0l0Ol_dataout; + wire_nl0l0l0OO_dataout <= nl0l0i01i WHEN wire_nl0l0li1i_o = '1' ELSE nl0l0i0ll; + wire_nl0l0l0OO_w_lg_dataout46242w(0) <= NOT wire_nl0l0l0OO_dataout; + wire_nl0l0l10i_dataout <= nl10i10i WHEN nli0Oi0lO = '1' ELSE wire_nl0l0l1OO_dataout; + wire_nl0l0l10l_dataout <= nl100O1O WHEN nli0Oi0lO = '1' ELSE wire_nl0l0l01i_dataout; + wire_nl0l0l10O_dataout <= nl100O0i WHEN nli0Oi0lO = '1' ELSE wire_nl0l0l01l_dataout; + wire_nl0l0l11i_dataout <= wire_nl0l0l1lO_dataout AND NOT(nli0Oi0lO); + wire_nl0l0l11l_dataout <= wire_nl0l0l1Oi_dataout AND NOT(nli0Oi0lO); + wire_nl0l0l11O_dataout <= wire_nl0l0l1Ol_dataout AND NOT(nli0Oi0lO); + wire_nl0l0l1i_dataout <= wire_nl0l0lOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0l0l1ii_dataout <= nl100O0l WHEN nli0Oi0lO = '1' ELSE wire_nl0l0l01O_dataout; + wire_nl0l0l1il_dataout <= nl100O0O WHEN nli0Oi0lO = '1' ELSE wire_nl0l0l00i_dataout; + wire_nl0l0l1iO_dataout <= nl0l0i0iO OR nli0Oi0lO; + wire_nl0l0l1l_dataout <= wire_nl0l0l0l_dataout AND NOT(niOO1O1li); + wire_nl0l0l1li_dataout <= (wire_nilO010O_w_lg_dataout8973w(0) AND wire_nilO010i_w_lg_dataout25163w(0)) AND NOT(nli11l0Ol); + wire_nl0l0l1ll_dataout <= nl0l0i0ii OR NOT(nli11l0Ol); + wire_nl0l0l1lO_dataout <= ni0lllO AND NOT(nli11l0Ol); + wire_nl0l0l1O_dataout <= wire_nl0l0l0O_dataout AND NOT(niOO1O1li); + wire_nl0l0l1Oi_dataout <= ni0llOi AND NOT(nli11l0Ol); + wire_nl0l0l1Ol_dataout <= ni0llOl AND NOT(nli11l0Ol); + wire_nl0l0l1OO_dataout <= nl10illl WHEN nli11l0Ol = '1' ELSE ni0liOi; + wire_nl0l0li0i_dataout <= nl0l0i01O WHEN wire_nl0l0li0l_o = '1' ELSE nl0l0lili; + wire_nl0l0li0i_w_lg_dataout46240w(0) <= NOT wire_nl0l0li0i_dataout; + wire_nl0l0li0O_dataout <= nl0l0i00i WHEN wire_nl0l0liii_o = '1' ELSE nl0l0lill; + wire_nl0l0li0O_w_lg_dataout46239w(0) <= NOT wire_nl0l0li0O_dataout; + wire_nl0l0li1l_dataout <= nl0l0i01l WHEN wire_nl0l0li1O_o = '1' ELSE nl0l0liiO; + wire_nl0l0li1l_w_lg_dataout46241w(0) <= NOT wire_nl0l0li1l_dataout; + wire_nl0l0lii_dataout <= wire_nl0l0Oii_o(3) OR niOO1O1iO; + wire_nl0l0liil_dataout <= nl0l0i00l WHEN ((nl0l0OiOl AND wire_nlill0Oll_w_lg_nl0l0OiOi46188w(0)) AND nl0l0OilO) = '1' ELSE nl0l0lilO; + wire_nl0l0liil_w_lg_dataout46238w(0) <= NOT wire_nl0l0liil_dataout; + wire_nl0l0llO_dataout <= wire_nl0l0lOO_dataout AND NOT(niOO1O1lO); + wire_nl0l0lOi_dataout <= wire_nl0l0O1i_dataout AND NOT(niOO1O1lO); + wire_nl0l0lOl_dataout <= wire_nl0l0O1l_dataout AND NOT(niOO1O1lO); + wire_nl0l0lOO_dataout <= wire_nl0l0Oil_o(1) OR niOO1O1ll; + wire_nl0l0O1i_dataout <= wire_nl0l0Oil_o(2) OR niOO1O1ll; + wire_nl0l0O1l_dataout <= wire_nl0l0Oil_o(3) OR niOO1O1ll; + wire_nl0l0Ol0i_dataout <= wire_nl0li1lll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Ol0l_dataout <= wire_nl0li1llO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Ol0O_dataout <= wire_nl0li1lOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Ol1i_dataout <= wire_nl0li1lil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Ol1l_dataout <= wire_nl0li1liO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Ol1O_dataout <= wire_nl0li1lli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Olii_dataout <= wire_nl0li1lOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Olil_dataout <= wire_nl0li1lOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OliO_dataout <= wire_nl0li1O1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Olli_dataout <= wire_nl0li1O1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0Olll_dataout <= wire_nl0li1O1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OllO_dataout <= wire_nl0li1O0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OlOi_dataout <= wire_nl0li1O0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OlOl_dataout <= wire_nl0li1O0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OlOO_dataout <= wire_nl0li1Oii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OO0i_dataout <= wire_nl0lii1iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OO0l_dataout <= wire_nl0lii1li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OO0O_dataout <= wire_nl0lii1ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OO1i_dataout <= wire_nl0li1Oil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OO1l_dataout <= wire_nl0lii1ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OO1O_dataout <= wire_nl0lii1il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOii_dataout <= wire_nl0lii1lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOil_dataout <= wire_nl0lii1Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOiO_dataout <= wire_nl0lii1Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOli_dataout <= wire_nl0lii1OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOll_dataout <= wire_nl0lii01i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOlO_dataout <= wire_nl0lii01l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOOi_dataout <= wire_nl0lii01O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOOl_dataout <= wire_nl0lii00i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l0OOOO_dataout <= wire_nl0lii00l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0l1000i_dataout <= wire_nl0l1l0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1000l_dataout <= wire_nl0l1l0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1000O_dataout <= wire_nl0l1l0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1001i_dataout <= wire_nl0l1l00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1001l_dataout <= wire_nl0l1l00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1001O_dataout <= wire_nl0l1l0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100i_dataout <= nl0lOOOO WHEN niOO1O11O = '1' ELSE wire_nl0l1iiO_dataout; + wire_nl0l100ii_dataout <= wire_nl0l1l0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100il_dataout <= wire_nl0l1l0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100iO_dataout <= wire_nl0l1l0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100l_dataout <= nl0O111i WHEN niOO1O11O = '1' ELSE wire_nl0l1ili_dataout; + wire_nl0l100li_dataout <= wire_nl0l1l0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100ll_dataout <= wire_nl0l1l0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100lO_dataout <= wire_nl0l1li1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100O_dataout <= nl0O111l WHEN niOO1O11O = '1' ELSE wire_nl0l1ill_dataout; + wire_nl0l100Oi_dataout <= wire_nl0l1li1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100Ol_dataout <= wire_nl0l1li1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l100OO_dataout <= wire_nl0l1li0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l101i_dataout <= nl0ll11l WHEN niOO1O11O = '1' ELSE wire_nl0l1i0O_dataout; + wire_nl0l101iO_dataout <= wire_nl0l1ii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l101l_dataout <= nl0lOOOi WHEN niOO1O11O = '1' ELSE wire_nl0l1iii_dataout; + wire_nl0l101li_dataout <= wire_nl0l1l1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l101ll_dataout <= wire_nl0l1l1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l101lO_dataout <= wire_nl0l1l01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l101O_dataout <= nl0lOOOl WHEN niOO1O11O = '1' ELSE wire_nl0l1iil_dataout; + wire_nl0l101Oi_dataout <= wire_nl0l1l01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l101Ol_dataout <= wire_nl0l1l01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l101OO_dataout <= wire_nl0l1l00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10i0i_dataout <= wire_nl0l1liil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10i0l_dataout <= wire_nl0l1liiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10i0O_dataout <= wire_nl0l1lili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10i1i_dataout <= wire_nl0l1li0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10i1l_dataout <= wire_nl0l1li0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10i1O_dataout <= wire_nl0l1liii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10ii_dataout <= nl0O111O WHEN niOO1O11O = '1' ELSE wire_nl0l1ilO_dataout; + wire_nl0l10iii_dataout <= wire_nl0l1lill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10iil_dataout <= wire_nl0l1lilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10iiO_dataout <= wire_nl0l1liOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10il_dataout <= nl0O110i WHEN niOO1O11O = '1' ELSE wire_nl0l1iOi_dataout; + wire_nl0l10ili_dataout <= wire_nl0l1liOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10ill_dataout <= wire_nl0l1liOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10ilO_dataout <= wire_nl0l1iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10iO_dataout <= nl0O110l WHEN niOO1O11O = '1' ELSE wire_nl0l1iOl_dataout; + wire_nl0l10iOi_dataout <= wire_nl0l1iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10iOl_dataout <= wire_nl0l1iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10iOO_dataout <= wire_nl0l1iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10l0i_dataout <= wire_nl0l1iiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10l0l_dataout <= wire_nl0l1iiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10l0O_dataout <= wire_nl0l1il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10l1i_dataout <= wire_nl0l1iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10l1l_dataout <= wire_nl0l1iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10l1O_dataout <= wire_nl0l1iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10li_dataout <= nl0O110O WHEN niOO1O11O = '1' ELSE wire_nl0l1iOO_dataout; + wire_nl0l10lii_dataout <= wire_nl0l1il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10lil_dataout <= wire_nl0l1il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10liO_dataout <= wire_nl0l1il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10ll_dataout <= nl0O11ii WHEN niOO1O11O = '1' ELSE wire_nl0l1l1i_dataout; + wire_nl0l10lli_dataout <= wire_nl0l1il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10lll_dataout <= wire_nl0l1il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10llO_dataout <= wire_nl0l1ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10lO_dataout <= nl0O11il WHEN niOO1O11O = '1' ELSE wire_nl0l1l1l_dataout; + wire_nl0l10lOi_dataout <= wire_nl0l1ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10lOl_dataout <= wire_nl0l1iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10lOO_dataout <= wire_nl0l1illi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10O0i_dataout <= wire_nl0l1ilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10O0l_dataout <= wire_nl0l1ilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10O0O_dataout <= wire_nl0l1iO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10O1i_dataout <= wire_nl0l1illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10O1l_dataout <= wire_nl0l1illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10O1O_dataout <= wire_nl0l1ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10Oi_dataout <= nl0O11iO WHEN niOO1O11O = '1' ELSE wire_nl0l1l1O_dataout; + wire_nl0l10Oii_dataout <= wire_nl0l1iO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10Oil_dataout <= wire_nl0l1iO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10OiO_dataout <= wire_nl0l1iO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10Ol_dataout <= nl0O11li WHEN niOO1O11O = '1' ELSE wire_nl0l1l0i_dataout; + wire_nl0l10Oli_dataout <= wire_nl0l1iO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10Oll_dataout <= wire_nl0l1iO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10OlO_dataout <= wire_nl0l1iOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10OO_dataout <= nl0O11ll WHEN niOO1O11O = '1' ELSE wire_nl0l1l0l_dataout; + wire_nl0l10OOi_dataout <= wire_nl0l1iOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l10OOl_dataout <= (nl0l11lii AND nl0iOi10i) AND NOT(wire_niO01O0O_dataout); + wire_nl0l10OOO_dataout <= nl0iOi10i AND NOT(wire_niO01O0O_dataout); + wire_nl0l110i_dataout <= wire_nl0l01Oi_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10iO_dataout; + wire_nl0l110l_dataout <= wire_nl0l01Ol_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10li_dataout; + wire_nl0l110O_dataout <= wire_nl0l01OO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10ll_dataout; + wire_nl0l111i_dataout <= wire_nl0l01li_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l100O_dataout; + wire_nl0l111l_dataout <= wire_nl0l01ll_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10ii_dataout; + wire_nl0l111O_dataout <= wire_nl0l01lO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10il_dataout; + wire_nl0l11ii_dataout <= wire_nl0l001i_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10lO_dataout; + wire_nl0l11il_dataout <= wire_nl0l001l_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10Oi_dataout; + wire_nl0l11iO_dataout <= wire_nl0l001O_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10Ol_dataout; + wire_nl0l11li_dataout <= wire_nl0l000i_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l10OO_dataout; + wire_nl0l11ll_dataout <= wire_nl0l000l_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l1i1i_dataout; + wire_nl0l11lO_dataout <= wire_nl0l000O_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l1i1l_dataout; + wire_nl0l11Oi_dataout <= wire_nl0l00ii_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l1i1O_dataout; + wire_nl0l11Ol_dataout <= wire_nl0l00il_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l1i0i_dataout; + wire_nl0l11OO_dataout <= wire_nl0l00iO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0l1i0l_dataout; + wire_nl0l1i00i_dataout <= wire_nl0l1iOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i00l_dataout <= wire_nl0l1iOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i00O_dataout <= wire_nl0l1l11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i01i_dataout <= wire_nl0l1iOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i01l_dataout <= wire_nl0l1iOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i01O_dataout <= wire_nl0l1iOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0i_dataout <= nl0O11OO WHEN niOO1O11O = '1' ELSE wire_nl0l1liO_dataout; + wire_nl0l1i0ii_dataout <= wire_nl0l1l11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0il_dataout <= wire_nl0l1l11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0iO_dataout <= wire_nl0l1l10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0l_dataout <= nl0O101i WHEN niOO1O11O = '1' ELSE wire_nl0l1lli_dataout; + wire_nl0l1i0li_dataout <= wire_nl0l1l10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0ll_dataout <= wire_nl0l1l10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0lO_dataout <= wire_nl0l1ii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0O_dataout <= nl0O10iO WHEN niOO1O10i = '1' ELSE wire_nl0l1lll_dataout; + wire_nl0l1i0Oi_dataout <= wire_nl0l1ii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0Ol_dataout <= wire_nl0l1ii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i0OO_dataout <= wire_nl0l1ii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i10i_dataout <= wire_nl0l1ll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i10l_dataout <= wire_nl0l1ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i10O_dataout <= wire_nl0l1ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i11i_dataout <= wire_nl0l1ll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i11l_dataout <= wire_nl0l1ll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i11O_dataout <= wire_nl0l1ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1i_dataout <= nl0O11lO WHEN niOO1O11O = '1' ELSE wire_nl0l1l0O_dataout; + wire_nl0l1i1ii_dataout <= wire_nl0l1llii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1il_dataout <= wire_nl0l1llil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1iO_dataout <= wire_nl0l1lliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1l_dataout <= nl0O11Oi WHEN niOO1O11O = '1' ELSE wire_nl0l1lii_dataout; + wire_nl0l1i1li_dataout <= wire_nl0l1llli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1ll_dataout <= wire_nl0l1llll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1lO_dataout <= wire_nl0l1lllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1O_dataout <= nl0O11Ol WHEN niOO1O11O = '1' ELSE wire_nl0l1lil_dataout; + wire_nl0l1i1Oi_dataout <= wire_nl0l1llOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1Ol_dataout <= wire_nl0l1iOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1i1OO_dataout <= wire_nl0l1iOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0l1ii0i_dataout <= wire_nl0l1l1il_dataout AND NOT(nl0iOi10i); + wire_nl0l1ii0l_dataout <= wire_nl0l1llOl_dataout AND NOT(niOii1l0O); + wire_nl0l1ii0O_dataout <= wire_nl0l1llOO_dataout AND NOT(niOii1l0O); + wire_nl0l1ii1l_dataout <= wire_nl0l1l1iO_dataout AND NOT(nl0iOi10i); + wire_nl0l1ii1O_dataout <= wire_nl0l1l1ii_dataout AND NOT(nl0iOi10i); + wire_nl0l1iii_dataout <= nl0O10li WHEN niOO1O10i = '1' ELSE wire_nl0l1llO_dataout; + wire_nl0l1iiii_dataout <= nl0iOOO1l WHEN niOii1l0O = '1' ELSE nl0l1100i; + wire_nl0l1iiil_dataout <= nl0iOOO1O WHEN niOii1l0O = '1' ELSE nl0l1100l; + wire_nl0l1iiiO_dataout <= nl0iOOO0i WHEN niOii1l0O = '1' ELSE nl0l1100O; + wire_nl0l1iil_dataout <= nl0O10ll WHEN niOO1O10i = '1' ELSE wire_nl0l1lOi_dataout; + wire_nl0l1iili_dataout <= nl0iOOO0l WHEN niOii1l0O = '1' ELSE nl0l110ii; + wire_nl0l1iill_dataout <= nl0iOOO0O WHEN niOii1l0O = '1' ELSE nl0l110il; + wire_nl0l1iilO_dataout <= nl0iOOOii WHEN niOii1l0O = '1' ELSE nl0l110iO; + wire_nl0l1iiO_dataout <= nl0O10lO WHEN niOO1O10i = '1' ELSE wire_nl0l1lOl_dataout; + wire_nl0l1iiOi_dataout <= nl0iOOOil WHEN niOii1l0O = '1' ELSE nl0l110li; + wire_nl0l1iiOl_dataout <= nl0iOOOiO WHEN niOii1l0O = '1' ELSE nl0l110ll; + wire_nl0l1iiOO_dataout <= nl0iOOOli WHEN niOii1l0O = '1' ELSE nl0l110lO; + wire_nl0l1il0i_dataout <= nl0iOOOOl WHEN niOii1l0O = '1' ELSE nl0l11i1i; + wire_nl0l1il0l_dataout <= nl0iOOOOO WHEN niOii1l0O = '1' ELSE nl0l11i1l; + wire_nl0l1il0O_dataout <= nl0l1111i WHEN niOii1l0O = '1' ELSE nl0l11i1O; + wire_nl0l1il1i_dataout <= nl0iOOOll WHEN niOii1l0O = '1' ELSE nl0l110Oi; + wire_nl0l1il1l_dataout <= nl0iOOOlO WHEN niOii1l0O = '1' ELSE nl0l110Ol; + wire_nl0l1il1O_dataout <= nl0iOOOOi WHEN niOii1l0O = '1' ELSE nl0l110OO; + wire_nl0l1ili_dataout <= nl0O10Oi WHEN niOO1O10i = '1' ELSE wire_nl0l1lOO_dataout; + wire_nl0l1ilii_dataout <= nl0l1111l WHEN niOii1l0O = '1' ELSE nl0l11i0i; + wire_nl0l1ilil_dataout <= nl0l1111O WHEN niOii1l0O = '1' ELSE nl0l11i0l; + wire_nl0l1iliO_dataout <= nl0l1110i WHEN niOii1l0O = '1' ELSE nl0l11i0O; + wire_nl0l1ill_dataout <= nl0O10Ol WHEN niOO1O10i = '1' ELSE wire_nl0l1O1i_dataout; + wire_nl0l1illi_dataout <= nl0l1110l WHEN niOii1l0O = '1' ELSE nl0l11iii; + wire_nl0l1illl_dataout <= nl0l1110O WHEN niOii1l0O = '1' ELSE nl0l11iil; + wire_nl0l1illO_dataout <= nl0l111ii WHEN niOii1l0O = '1' ELSE nl0l11iiO; + wire_nl0l1ilO_dataout <= nl0O10OO WHEN niOO1O10i = '1' ELSE wire_nl0l1O1l_dataout; + wire_nl0l1ilOi_dataout <= nl0l111il WHEN niOii1l0O = '1' ELSE nl0l11ili; + wire_nl0l1ilOl_dataout <= nl0l111iO WHEN niOii1l0O = '1' ELSE nl0l11ill; + wire_nl0l1ilOO_dataout <= nl0l111li WHEN niOii1l0O = '1' ELSE nl0l11ilO; + wire_nl0l1iO0i_dataout <= nl0l111Ol WHEN niOii1l0O = '1' ELSE nl0l11l1i; + wire_nl0l1iO0l_dataout <= nl0l111OO WHEN niOii1l0O = '1' ELSE nl0l11l1l; + wire_nl0l1iO0O_dataout <= nl0l1101i WHEN niOii1l0O = '1' ELSE nl0l11l1O; + wire_nl0l1iO1i_dataout <= nl0l111ll WHEN niOii1l0O = '1' ELSE nl0l11iOi; + wire_nl0l1iO1l_dataout <= nl0l111lO WHEN niOii1l0O = '1' ELSE nl0l11iOl; + wire_nl0l1iO1O_dataout <= nl0l111Oi WHEN niOii1l0O = '1' ELSE nl0l11iOO; + wire_nl0l1iOi_dataout <= nl0O1i1i WHEN niOO1O10i = '1' ELSE wire_nl0l1O1O_dataout; + wire_nl0l1iOii_dataout <= nl0l1101l WHEN niOii1l0O = '1' ELSE nl0l11l0i; + wire_nl0l1iOil_dataout <= nl0l1101O WHEN niOii1l0O = '1' ELSE nl0l11l0l; + wire_nl0l1iOiO_dataout <= nl0l11lil WHEN niOii1l0O = '1' ELSE nl0l11O0O; + wire_nl0l1iOl_dataout <= nl0O1i1l WHEN niOO1O10i = '1' ELSE wire_nl0l1O0i_dataout; + wire_nl0l1iOli_dataout <= nl0l11liO WHEN niOii1l0O = '1' ELSE nl0l11Oii; + wire_nl0l1iOll_dataout <= nl0l11lli WHEN niOii1l0O = '1' ELSE nl0l11Oil; + wire_nl0l1iOlO_dataout <= nl0l11lll WHEN niOii1l0O = '1' ELSE nl0l11OiO; + wire_nl0l1iOO_dataout <= nl0O1i1O WHEN niOO1O10i = '1' ELSE wire_nl0l1O0l_dataout; + wire_nl0l1iOOi_dataout <= nl0l11llO WHEN niOii1l0O = '1' ELSE nl0l11Oli; + wire_nl0l1iOOl_dataout <= nl0l11lOi WHEN niOii1l0O = '1' ELSE nl0l11Oll; + wire_nl0l1iOOO_dataout <= nl0l11lOl WHEN niOii1l0O = '1' ELSE nl0l11OlO; + wire_nl0l1l00i_dataout <= niiil1O WHEN niOii1lii = '1' ELSE nl0iOOOii; + wire_nl0l1l00l_dataout <= niiil0i WHEN niOii1lii = '1' ELSE nl0iOOOil; + wire_nl0l1l00O_dataout <= niiil0l WHEN niOii1lii = '1' ELSE nl0iOOOiO; + wire_nl0l1l01i_dataout <= niiiiOO WHEN niOii1lii = '1' ELSE nl0iOOO0i; + wire_nl0l1l01l_dataout <= niiil1i WHEN niOii1lii = '1' ELSE nl0iOOO0l; + wire_nl0l1l01O_dataout <= niiil1l WHEN niOii1lii = '1' ELSE nl0iOOO0O; + wire_nl0l1l0i_dataout <= nl0O1iii WHEN niOO1O10i = '1' ELSE wire_nl0l1OiO_dataout; + wire_nl0l1l0ii_dataout <= niiil0O WHEN niOii1lii = '1' ELSE nl0iOOOli; + wire_nl0l1l0il_dataout <= niiilii WHEN niOii1lii = '1' ELSE nl0iOOOll; + wire_nl0l1l0iO_dataout <= niiilil WHEN niOii1lii = '1' ELSE nl0iOOOlO; + wire_nl0l1l0l_dataout <= nl0O1iil WHEN niOO1O10i = '1' ELSE wire_nl0l1Oli_dataout; + wire_nl0l1l0li_dataout <= niiiliO WHEN niOii1lii = '1' ELSE nl0iOOOOi; + wire_nl0l1l0ll_dataout <= niiilli WHEN niOii1lii = '1' ELSE nl0iOOOOl; + wire_nl0l1l0lO_dataout <= niiilll WHEN niOii1lii = '1' ELSE nl0iOOOOO; + wire_nl0l1l0O_dataout <= nl0O1iiO WHEN niOO1O10i = '1' ELSE wire_nl0l1Oll_dataout; + wire_nl0l1l0Oi_dataout <= niiillO WHEN niOii1lii = '1' ELSE nl0l1111i; + wire_nl0l1l0Ol_dataout <= niiilOi WHEN niOii1lii = '1' ELSE nl0l1111l; + wire_nl0l1l0OO_dataout <= niiilOl WHEN niOii1lii = '1' ELSE nl0l1111O; + wire_nl0l1l10i_dataout <= nl0l11O1O WHEN niOii1l0O = '1' ELSE nl0l1011i; + wire_nl0l1l10l_dataout <= nl0l11O0i WHEN niOii1l0O = '1' ELSE nl0l1011l; + wire_nl0l1l10O_dataout <= nl0l11O0l WHEN niOii1l0O = '1' ELSE nl0l1011O; + wire_nl0l1l11i_dataout <= nl0l11lOO WHEN niOii1l0O = '1' ELSE nl0l11OOi; + wire_nl0l1l11l_dataout <= nl0l11O1i WHEN niOii1l0O = '1' ELSE nl0l11OOl; + wire_nl0l1l11O_dataout <= nl0l11O1l WHEN niOii1l0O = '1' ELSE nl0l11OOO; + wire_nl0l1l1i_dataout <= nl0O1i0i WHEN niOO1O10i = '1' ELSE wire_nl0l1O0O_dataout; + wire_nl0l1l1ii_dataout <= nl0l1010i WHEN niOii1l0O = '1' ELSE nl0l1010l; + wire_nl0l1l1il_dataout <= nl0l1010O WHEN niOii1l0O = '1' ELSE nl0l101ii; + wire_nl0l1l1iO_dataout <= nl0iOl10i OR niOii1l0O; + wire_nl0l1l1l_dataout <= nl0O1i0l WHEN niOO1O10i = '1' ELSE wire_nl0l1Oii_dataout; + wire_nl0l1l1O_dataout <= nl0O1i0O WHEN niOO1O10i = '1' ELSE wire_nl0l1Oil_dataout; + wire_nl0l1l1Ol_dataout <= niiiiOi WHEN niOii1lii = '1' ELSE nl0iOOO1l; + wire_nl0l1l1OO_dataout <= niiiiOl WHEN niOii1lii = '1' ELSE nl0iOOO1O; + wire_nl0l1li0i_dataout <= niiiO1O WHEN niOii1lii = '1' ELSE nl0l111ii; + wire_nl0l1li0l_dataout <= niiiO0i WHEN niOii1lii = '1' ELSE nl0l111il; + wire_nl0l1li0O_dataout <= niiiO0l WHEN niOii1lii = '1' ELSE nl0l111iO; + wire_nl0l1li1i_dataout <= niiilOO WHEN niOii1lii = '1' ELSE nl0l1110i; + wire_nl0l1li1l_dataout <= niiiO1i WHEN niOii1lii = '1' ELSE nl0l1110l; + wire_nl0l1li1O_dataout <= niiiO1l WHEN niOii1lii = '1' ELSE nl0l1110O; + wire_nl0l1lii_dataout <= nl0O1ili WHEN niOO1O10i = '1' ELSE wire_nl0l1OlO_dataout; + wire_nl0l1liii_dataout <= niiiO0O WHEN niOii1lii = '1' ELSE nl0l111li; + wire_nl0l1liil_dataout <= niiiOii WHEN niOii1lii = '1' ELSE nl0l111ll; + wire_nl0l1liiO_dataout <= niiiOil WHEN niOii1lii = '1' ELSE nl0l111lO; + wire_nl0l1lil_dataout <= nl0O1ill WHEN niOO1O10i = '1' ELSE wire_nl0l1OOi_dataout; + wire_nl0l1lili_dataout <= niiiOiO WHEN niOii1lii = '1' ELSE nl0l111Oi; + wire_nl0l1lill_dataout <= niiiOli WHEN niOii1lii = '1' ELSE nl0l111Ol; + wire_nl0l1lilO_dataout <= niiiOll WHEN niOii1lii = '1' ELSE nl0l111OO; + wire_nl0l1liO_dataout <= nl0O1ilO WHEN niOO1O10i = '1' ELSE wire_nl0l1OOl_dataout; + wire_nl0l1liOi_dataout <= niiiOlO WHEN niOii1lii = '1' ELSE nl0l1101i; + wire_nl0l1liOl_dataout <= niiiOOi WHEN niOii1lii = '1' ELSE nl0l1101l; + wire_nl0l1liOO_dataout <= niiiOOl WHEN niOii1lii = '1' ELSE nl0l1101O; + wire_nl0l1ll0i_dataout <= niiii1O WHEN niOii1lii = '1' ELSE nl0l11lll; + wire_nl0l1ll0l_dataout <= niiii0i WHEN niOii1lii = '1' ELSE nl0l11llO; + wire_nl0l1ll0O_dataout <= niiii0l WHEN niOii1lii = '1' ELSE nl0l11lOi; + wire_nl0l1ll1i_dataout <= niii0OO WHEN niOii1lii = '1' ELSE nl0l11lil; + wire_nl0l1ll1l_dataout <= niiii1i WHEN niOii1lii = '1' ELSE nl0l11liO; + wire_nl0l1ll1O_dataout <= niiii1l WHEN niOii1lii = '1' ELSE nl0l11lli; + wire_nl0l1lli_dataout <= nl0O1iOi WHEN niOO1O10i = '1' ELSE wire_nl0l1OOO_dataout; + wire_nl0l1llii_dataout <= niiii0O WHEN niOii1lii = '1' ELSE nl0l11lOl; + wire_nl0l1llil_dataout <= niiiiii WHEN niOii1lii = '1' ELSE nl0l11lOO; + wire_nl0l1lliO_dataout <= niiiiil WHEN niOii1lii = '1' ELSE nl0l11O1i; + wire_nl0l1lll_dataout <= nl0ll11l WHEN niOO1O11l = '1' ELSE nl0iO0Oi; + wire_nl0l1llli_dataout <= niiiiiO WHEN niOii1lii = '1' ELSE nl0l11O1l; + wire_nl0l1llll_dataout <= niiiili WHEN niOii1lii = '1' ELSE nl0l11O1O; + wire_nl0l1lllO_dataout <= niiiill WHEN niOii1lii = '1' ELSE nl0l11O0i; + wire_nl0l1llO_dataout <= nl0lOOOi WHEN niOO1O11l = '1' ELSE nl0iO0Ol; + wire_nl0l1llOi_dataout <= niiiilO WHEN niOii1lii = '1' ELSE nl0l11O0l; + wire_nl0l1llOl_dataout <= niii0Oi WHEN niOii1lii = '1' ELSE nl0l1010i; + wire_nl0l1llOO_dataout <= niii0Ol WHEN niOii1lii = '1' ELSE nl0l1010O; + wire_nl0l1lO0i_dataout <= wire_nl0l1Oiil_dataout WHEN niOii1liO = '1' ELSE nl0l1100O; + wire_nl0l1lO0l_dataout <= wire_nl0l1OiiO_dataout WHEN niOii1liO = '1' ELSE nl0l110ii; + wire_nl0l1lO0O_dataout <= wire_nl0l1Oili_dataout WHEN niOii1liO = '1' ELSE nl0l110il; + wire_nl0l1lO1l_dataout <= wire_nl0l1Oi0O_dataout WHEN niOii1liO = '1' ELSE nl0l1100i; + wire_nl0l1lO1l_w_lg_dataout48198w(0) <= NOT wire_nl0l1lO1l_dataout; + wire_nl0l1lO1O_dataout <= wire_nl0l1Oiii_dataout WHEN niOii1liO = '1' ELSE nl0l1100l; + wire_nl0l1lO1O_w_lg_w_lg_dataout48195w48196w(0) <= wire_nl0l1lO1O_w_lg_dataout48195w(0) AND wire_nl0l1lO1l_dataout; + wire_nl0l1lO1O_w_lg_dataout48199w(0) <= wire_nl0l1lO1O_dataout AND wire_nl0l1lO1l_w_lg_dataout48198w(0); + wire_nl0l1lO1O_w_lg_dataout48195w(0) <= NOT wire_nl0l1lO1O_dataout; + wire_nl0l1lOi_dataout <= nl0lOOOl WHEN niOO1O11l = '1' ELSE nl0iO0OO; + wire_nl0l1lOii_dataout <= wire_nl0l1Oill_dataout WHEN niOii1liO = '1' ELSE nl0l110iO; + wire_nl0l1lOil_dataout <= wire_nl0l1OilO_dataout WHEN niOii1liO = '1' ELSE nl0l110li; + wire_nl0l1lOiO_dataout <= wire_nl0l1OiOi_dataout WHEN niOii1liO = '1' ELSE nl0l110ll; + wire_nl0l1lOl_dataout <= nl0lOOOO WHEN niOO1O11l = '1' ELSE nl0iOi1i; + wire_nl0l1lOli_dataout <= wire_nl0l1OiOl_dataout WHEN niOii1liO = '1' ELSE nl0l110lO; + wire_nl0l1lOll_dataout <= wire_nl0l1OiOO_dataout WHEN niOii1liO = '1' ELSE nl0l110Oi; + wire_nl0l1lOlO_dataout <= wire_nl0l1Ol1i_dataout WHEN niOii1liO = '1' ELSE nl0l110Ol; + wire_nl0l1lOO_dataout <= nl0O111i WHEN niOO1O11l = '1' ELSE nl0iOi1l; + wire_nl0l1lOOi_dataout <= wire_nl0l1Ol1l_dataout WHEN niOii1liO = '1' ELSE nl0l110OO; + wire_nl0l1lOOl_dataout <= wire_nl0l1Ol1O_dataout WHEN niOii1liO = '1' ELSE nl0l11i1i; + wire_nl0l1lOOO_dataout <= wire_nl0l1Ol0i_dataout WHEN niOii1liO = '1' ELSE nl0l11i1l; + wire_nl0l1O01i_dataout <= wire_nl0l1OO0l_dataout WHEN niOii1liO = '1' ELSE nl0l11l1O; + wire_nl0l1O01l_dataout <= wire_nl0l1OO0O_dataout WHEN niOii1liO = '1' ELSE nl0l11l0i; + wire_nl0l1O01O_dataout <= wire_nl0l1OOii_dataout WHEN niOii1liO = '1' ELSE nl0l11l0l; + wire_nl0l1O0i_dataout <= nl0O110l WHEN niOO1O11l = '1' ELSE nl0iOi0O; + wire_nl0l1O0l_dataout <= nl0O110O WHEN niOO1O11l = '1' ELSE nl0iOiii; + wire_nl0l1O0O_dataout <= nl0O11ii WHEN niOO1O11l = '1' ELSE nl0iOiil; + wire_nl0l1O0OO_dataout <= wire_nl1lOOO0l_dataout WHEN niOii1lll = '1' ELSE nlOili1l; + wire_nl0l1O0OO_w_lg_dataout52093w(0) <= wire_nl0l1O0OO_dataout AND wire_w_lg_niOii1liO52092w(0); + wire_nl0l1O10i_dataout <= wire_nl0l1Olil_dataout WHEN niOii1liO = '1' ELSE nl0l11i0O; + wire_nl0l1O10l_dataout <= wire_nl0l1OliO_dataout WHEN niOii1liO = '1' ELSE nl0l11iii; + wire_nl0l1O10O_dataout <= wire_nl0l1Olli_dataout WHEN niOii1liO = '1' ELSE nl0l11iil; + wire_nl0l1O11i_dataout <= wire_nl0l1Ol0l_dataout WHEN niOii1liO = '1' ELSE nl0l11i1O; + wire_nl0l1O11l_dataout <= wire_nl0l1Ol0O_dataout WHEN niOii1liO = '1' ELSE nl0l11i0i; + wire_nl0l1O11O_dataout <= wire_nl0l1Olii_dataout WHEN niOii1liO = '1' ELSE nl0l11i0l; + wire_nl0l1O1i_dataout <= nl0O111l WHEN niOO1O11l = '1' ELSE nl0iOi1O; + wire_nl0l1O1ii_dataout <= wire_nl0l1Olll_dataout WHEN niOii1liO = '1' ELSE nl0l11iiO; + wire_nl0l1O1il_dataout <= wire_nl0l1OllO_dataout WHEN niOii1liO = '1' ELSE nl0l11ili; + wire_nl0l1O1iO_dataout <= wire_nl0l1OlOi_dataout WHEN niOii1liO = '1' ELSE nl0l11ill; + wire_nl0l1O1l_dataout <= nl0O111O WHEN niOO1O11l = '1' ELSE nl0iOi0i; + wire_nl0l1O1li_dataout <= wire_nl0l1OlOl_dataout WHEN niOii1liO = '1' ELSE nl0l11ilO; + wire_nl0l1O1ll_dataout <= wire_nl0l1OlOO_dataout WHEN niOii1liO = '1' ELSE nl0l11iOi; + wire_nl0l1O1lO_dataout <= wire_nl0l1OO1i_dataout WHEN niOii1liO = '1' ELSE nl0l11iOl; + wire_nl0l1O1O_dataout <= nl0O110i WHEN niOO1O11l = '1' ELSE nl0iOi0l; + wire_nl0l1O1Oi_dataout <= wire_nl0l1OO1l_dataout WHEN niOii1liO = '1' ELSE nl0l11iOO; + wire_nl0l1O1Ol_dataout <= wire_nl0l1OO1O_dataout WHEN niOii1liO = '1' ELSE nl0l11l1i; + wire_nl0l1O1OO_dataout <= wire_nl0l1OO0i_dataout WHEN niOii1liO = '1' ELSE nl0l11l1l; + wire_nl0l1Oi0i_dataout <= wire_nl1lOO10l_dataout WHEN niOii1lll = '1' ELSE nlOiil1l; + wire_nl0l1Oi0l_dataout <= wire_nl1lOO10O_dataout WHEN niOii1lll = '1' ELSE nlOiil1O; + wire_nl0l1Oi0O_dataout <= wire_nl1iliilO_dataout WHEN niOii1lll = '1' ELSE nl11OOi0l; + wire_nl0l1Oi1i_dataout <= wire_nl1lOOl0i_dataout WHEN niOii1lll = '1' ELSE nlOil01i; + wire_nl0l1Oi1i_w_lg_dataout52091w(0) <= NOT wire_nl0l1Oi1i_dataout; + wire_nl0l1Oi1l_dataout <= wire_nl1lOO11O_dataout WHEN niOii1lll = '1' ELSE nlOiiiOO; + wire_nl0l1Oi1O_dataout <= wire_nl1lOO10i_dataout WHEN niOii1lll = '1' ELSE nlOiil1i; + wire_nl0l1Oii_dataout <= nl0O11il WHEN niOO1O11l = '1' ELSE nl0iOiiO; + wire_nl0l1Oiii_dataout <= wire_nl1iliiOi_dataout WHEN niOii1lll = '1' ELSE nl11OOi0O; + wire_nl0l1Oiil_dataout <= wire_nl1iliiOl_dataout WHEN niOii1lll = '1' ELSE nl11OOiii; + wire_nl0l1OiiO_dataout <= wire_nl1iliiOO_dataout WHEN niOii1lll = '1' ELSE nl11OOiil; + wire_nl0l1Oil_dataout <= nl0O11iO WHEN niOO1O11l = '1' ELSE nl0iOili; + wire_nl0l1Oili_dataout <= wire_nl1ilil1i_dataout WHEN niOii1lll = '1' ELSE nl11OOiiO; + wire_nl0l1Oill_dataout <= wire_nl1ilil1l_dataout WHEN niOii1lll = '1' ELSE nl11OOili; + wire_nl0l1OilO_dataout <= wire_nl1ilil1O_dataout WHEN niOii1lll = '1' ELSE nl11OOill; + wire_nl0l1OiO_dataout <= nl0O11li WHEN niOO1O11l = '1' ELSE nl0iOill; + wire_nl0l1OiOi_dataout <= wire_nl1ilil0i_dataout WHEN niOii1lll = '1' ELSE nl11OOilO; + wire_nl0l1OiOl_dataout <= wire_nl1ilil0l_dataout WHEN niOii1lll = '1' ELSE nl11OOiOi; + wire_nl0l1OiOO_dataout <= wire_nl1ilil0O_dataout WHEN niOii1lll = '1' ELSE nl11OOiOl; + wire_nl0l1Ol0i_dataout <= wire_nl1ililli_dataout WHEN niOii1lll = '1' ELSE nl11OOl1O; + wire_nl0l1Ol0l_dataout <= wire_nl1ililll_dataout WHEN niOii1lll = '1' ELSE nl11OOl0i; + wire_nl0l1Ol0O_dataout <= wire_nl1ilillO_dataout WHEN niOii1lll = '1' ELSE nl11OOl0l; + wire_nl0l1Ol1i_dataout <= wire_nl1ililii_dataout WHEN niOii1lll = '1' ELSE nl11OOiOO; + wire_nl0l1Ol1l_dataout <= wire_nl1ililil_dataout WHEN niOii1lll = '1' ELSE nl11OOl1i; + wire_nl0l1Ol1O_dataout <= wire_nl1ililiO_dataout WHEN niOii1lll = '1' ELSE nl11OOl1l; + wire_nl0l1Oli_dataout <= nl0O11ll WHEN niOO1O11l = '1' ELSE nl0iOilO; + wire_nl0l1Olii_dataout <= wire_nl1ililOi_dataout WHEN niOii1lll = '1' ELSE nl11OOl0O; + wire_nl0l1Olil_dataout <= wire_nl1ililOl_dataout WHEN niOii1lll = '1' ELSE nl11OOlii; + wire_nl0l1OliO_dataout <= wire_nl1ililOO_dataout WHEN niOii1lll = '1' ELSE nl11OOlil; + wire_nl0l1Oll_dataout <= nl0O11lO WHEN niOO1O11l = '1' ELSE nl0iOiOi; + wire_nl0l1Olli_dataout <= wire_nl1iliO1i_dataout WHEN niOii1lll = '1' ELSE nl11OOliO; + wire_nl0l1Olll_dataout <= wire_nl1iliO1l_dataout WHEN niOii1lll = '1' ELSE nl11OOlli; + wire_nl0l1OllO_dataout <= wire_nl1iliO1O_dataout WHEN niOii1lll = '1' ELSE nl11OOlll; + wire_nl0l1OlO_dataout <= nl0O11Oi WHEN niOO1O11l = '1' ELSE nl0iOiOl; + wire_nl0l1OlOi_dataout <= wire_nl1iliO0i_dataout WHEN niOii1lll = '1' ELSE nl11OOllO; + wire_nl0l1OlOl_dataout <= wire_nl1iliO0l_dataout WHEN niOii1lll = '1' ELSE nl11OOlOi; + wire_nl0l1OlOO_dataout <= wire_nl1iliO0O_dataout WHEN niOii1lll = '1' ELSE nl11OOlOl; + wire_nl0l1OO0i_dataout <= wire_nl1iliOli_dataout WHEN niOii1lll = '1' ELSE nl11OOO1O; + wire_nl0l1OO0l_dataout <= wire_nl1iliOll_dataout WHEN niOii1lll = '1' ELSE nl11OOO0i; + wire_nl0l1OO0O_dataout <= wire_nl1iliOlO_dataout WHEN niOii1lll = '1' ELSE nl11OOO0l; + wire_nl0l1OO1i_dataout <= wire_nl1iliOii_dataout WHEN niOii1lll = '1' ELSE nl11OOlOO; + wire_nl0l1OO1l_dataout <= wire_nl1iliOil_dataout WHEN niOii1lll = '1' ELSE nl11OOO1i; + wire_nl0l1OO1O_dataout <= wire_nl1iliOiO_dataout WHEN niOii1lll = '1' ELSE nl11OOO1l; + wire_nl0l1OOi_dataout <= nl0O11Ol WHEN niOO1O11l = '1' ELSE nl0iOiOO; + wire_nl0l1OOii_dataout <= wire_nl1iliOOi_dataout WHEN niOii1lll = '1' ELSE nl11OOO0O; + wire_nl0l1OOil_dataout <= wire_nl1lO010O_dataout WHEN niOii1lll = '1' ELSE nlOii1OO; + wire_nl0l1OOil_w_lg_dataout52356w(0) <= NOT wire_nl0l1OOil_dataout; + wire_nl0l1OOiO_dataout <= wire_nl1lO01ii_dataout WHEN niOii1lll = '1' ELSE nlOii01i; + wire_nl0l1OOiO_w_lg_dataout52354w(0) <= NOT wire_nl0l1OOiO_dataout; + wire_nl0l1OOl_dataout <= nl0O11OO WHEN niOO1O11l = '1' ELSE nl0iOl1i; + wire_nl0l1OOli_dataout <= wire_nl1lO01il_dataout WHEN niOii1lll = '1' ELSE nlOii01l; + wire_nl0l1OOli_w_lg_dataout52352w(0) <= NOT wire_nl0l1OOli_dataout; + wire_nl0l1OOll_dataout <= wire_nl1lO01iO_dataout WHEN niOii1lll = '1' ELSE nlOii01O; + wire_nl0l1OOll_w_lg_dataout52350w(0) <= NOT wire_nl0l1OOll_dataout; + wire_nl0l1OOlO_dataout <= wire_nl1lO01li_dataout WHEN niOii1lll = '1' ELSE nlOii00i; + wire_nl0l1OOlO_w52359w(0) <= wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52353w(0) AND wire_nl0l1OOiO_dataout; + wire_nl0l1OOlO_w52366w(0) <= wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52362w(0) AND wire_nl0l1OOiO_dataout; + wire_nl0l1OOlO_w52374w(0) <= wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52370w(0) AND wire_nl0l1OOiO_dataout; + wire_nl0l1OOlO_w52381w(0) <= wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52377w(0) AND wire_nl0l1OOiO_dataout; + wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52384w52391w52395w(0) <= wire_nl0l1OOlO_w_lg_w_lg_dataout52384w52391w(0) AND wire_nl0l1OOiO_dataout; + wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52399w52402w(0) <= wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52399w(0) AND wire_nl0l1OOiO_dataout; + wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52398w52405w52408w(0) <= wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52405w(0) AND wire_nl0l1OOiO_dataout; + wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52353w(0) <= wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52351w(0) AND wire_nl0l1OOli_w_lg_dataout52352w(0); + wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52351w52362w(0) <= wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52351w(0) AND wire_nl0l1OOli_dataout; + wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52370w(0) <= wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52369w(0) AND wire_nl0l1OOli_w_lg_dataout52352w(0); + wire_nl0l1OOlO_w_lg_w_lg_w_lg_dataout52349w52369w52377w(0) <= wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52369w(0) AND wire_nl0l1OOli_dataout; + wire_nl0l1OOlO_w_lg_w_lg_dataout52384w52391w(0) <= wire_nl0l1OOlO_w_lg_dataout52384w(0) AND wire_nl0l1OOli_dataout; + wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52399w(0) <= wire_nl0l1OOlO_w_lg_dataout52398w(0) AND wire_nl0l1OOli_w_lg_dataout52352w(0); + wire_nl0l1OOlO_w_lg_w_lg_dataout52398w52405w(0) <= wire_nl0l1OOlO_w_lg_dataout52398w(0) AND wire_nl0l1OOli_dataout; + wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52351w(0) <= wire_nl0l1OOlO_w_lg_dataout52349w(0) AND wire_nl0l1OOll_w_lg_dataout52350w(0); + wire_nl0l1OOlO_w_lg_w_lg_dataout52349w52369w(0) <= wire_nl0l1OOlO_w_lg_dataout52349w(0) AND wire_nl0l1OOll_dataout; + wire_nl0l1OOlO_w_lg_dataout52384w(0) <= wire_nl0l1OOlO_dataout AND wire_nl0l1OOll_w_lg_dataout52350w(0); + wire_nl0l1OOlO_w_lg_dataout52398w(0) <= wire_nl0l1OOlO_dataout AND wire_nl0l1OOll_dataout; + wire_nl0l1OOlO_w_lg_dataout52349w(0) <= NOT wire_nl0l1OOlO_dataout; + wire_nl0l1OOO_dataout <= nl0O101i WHEN niOO1O11l = '1' ELSE nl0iOl1l; + wire_nl0l1OOOi_dataout <= wire_nl1lO01ll_dataout WHEN niOii1lll = '1' ELSE nlOii00l; + wire_nl0l1OOOi_w_lg_dataout52411w(0) <= NOT wire_nl0l1OOOi_dataout; + wire_nl0l1OOOl_dataout <= wire_nl1lO01lO_dataout WHEN niOii1lll = '1' ELSE nlOii00O; + wire_nl0l1OOOl_w_lg_dataout52340w(0) <= NOT wire_nl0l1OOOl_dataout; + wire_nl0l1OOOO_dataout <= wire_nl1lO01Oi_dataout WHEN niOii1lll = '1' ELSE nlOii0ii; + wire_nl0l1OOOO_w_lg_dataout52338w(0) <= NOT wire_nl0l1OOOO_dataout; + wire_nl0li000i_dataout <= wire_nl0li0OOl_dataout WHEN niOii01ll = '1' ELSE nl0l0O1Oi; + wire_nl0li000l_dataout <= wire_nl0li0OOi_dataout WHEN niOii01ll = '1' ELSE nl0l0O1Ol; + wire_nl0li000O_dataout <= wire_nl0li0OlO_dataout WHEN niOii01ll = '1' ELSE nl0l0O1OO; + wire_nl0li001i_dataout <= wire_nl0lii11l_dataout WHEN niOii01ll = '1' ELSE nl0l0O1li; + wire_nl0li001l_dataout <= wire_nl0lii11i_dataout WHEN niOii01ll = '1' ELSE nl0l0O1ll; + wire_nl0li001O_dataout <= wire_nl0li0OOO_dataout WHEN niOii01ll = '1' ELSE nl0l0O1lO; + wire_nl0li00i_dataout <= wire_nl0liiiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li00ii_dataout <= wire_nl0li0Oll_dataout WHEN niOii01ll = '1' ELSE nl0l0O01i; + wire_nl0li00il_dataout <= wire_nl0li0Oli_dataout WHEN niOii01ll = '1' ELSE nl0l0O01l; + wire_nl0li00iO_dataout <= wire_nl0li0OiO_dataout WHEN niOii01ll = '1' ELSE nl0l0O01O; + wire_nl0li00l_dataout <= wire_nl0liili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li00li_dataout <= wire_nl0li0Oil_dataout WHEN niOii01ll = '1' ELSE nl0l0O00i; + wire_nl0li00ll_dataout <= wire_nl0li0Oii_dataout WHEN niOii01ll = '1' ELSE nl0l0O00l; + wire_nl0li00lO_dataout <= wire_nl0li0O0O_dataout WHEN niOii01ll = '1' ELSE nl0l0O00O; + wire_nl0li00O_dataout <= wire_nl0liill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li00Oi_dataout <= wire_nl0li0O0l_dataout WHEN niOii01ll = '1' ELSE nl0l0O0ii; + wire_nl0li00Ol_dataout <= wire_nl0li0O0i_dataout WHEN niOii01ll = '1' ELSE nl0l0O0il; + wire_nl0li00OO_dataout <= wire_nl0li0O1O_dataout WHEN niOii01ll = '1' ELSE nl0l0O0iO; + wire_nl0li010i_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0l0liOi; + wire_nl0li010l_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0l0lilO; + wire_nl0li010O_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0l0lill; + wire_nl0li011i_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0l0ll1i; + wire_nl0li011l_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0l0liOO; + wire_nl0li011O_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0l0liOl; + wire_nl0li01i_dataout <= wire_nl0lii0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li01ii_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0l0lili; + wire_nl0li01il_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0l0liiO; + wire_nl0li01iO_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0l0i0ll; + wire_nl0li01l_dataout <= wire_nl0liiii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li01O_dataout <= wire_nl0liiil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li01OO_dataout <= wire_nl0lii11O_dataout WHEN niOii01ll = '1' ELSE nl0l0O1iO; + wire_nl0li0i0i_dataout <= wire_nl0li0lOl_dataout WHEN niOii01ll = '1' ELSE nl0l0O0Oi; + wire_nl0li0i0l_dataout <= wire_nl0li0lOi_dataout WHEN niOii01ll = '1' ELSE nl0l0O0Ol; + wire_nl0li0i0O_dataout <= wire_nl0li0llO_dataout WHEN niOii01ll = '1' ELSE nl0l0O0OO; + wire_nl0li0i1i_dataout <= wire_nl0li0O1l_dataout WHEN niOii01ll = '1' ELSE nl0l0O0li; + wire_nl0li0i1l_dataout <= wire_nl0li0O1i_dataout WHEN niOii01ll = '1' ELSE nl0l0O0ll; + wire_nl0li0i1O_dataout <= wire_nl0li0lOO_dataout WHEN niOii01ll = '1' ELSE nl0l0O0lO; + wire_nl0li0ii_dataout <= wire_nl0liilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0iii_dataout <= wire_nl0li0lll_dataout WHEN niOii01ll = '1' ELSE nl0l0Oi1i; + wire_nl0li0iil_dataout <= wire_nl0li0lli_dataout WHEN niOii01ll = '1' ELSE nl0l0Oi1l; + wire_nl0li0iiO_dataout <= wire_nl0li0liO_dataout WHEN niOii01ll = '1' ELSE nl0l0Oi1O; + wire_nl0li0il_dataout <= wire_nl0liiOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0ili_dataout <= wire_nl0li0lil_dataout WHEN niOii01ll = '1' ELSE nl0l0Oi0i; + wire_nl0li0ill_dataout <= wire_nl0li0lii_dataout WHEN niOii01ll = '1' ELSE nl0l0Oi0l; + wire_nl0li0ilO_dataout <= wire_nl0li0l0O_dataout WHEN niOii01ll = '1' ELSE nl0l0Oi0O; + wire_nl0li0iO_dataout <= wire_nl0liiOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0iOi_dataout <= wire_nl0li0l0l_dataout WHEN niOii01ll = '1' ELSE nl0l0Oiii; + wire_nl0li0iOl_dataout <= wire_nl0li0l0i_dataout WHEN niOii01ll = '1' ELSE nl0l0Oiil; + wire_nl0li0iOO_dataout <= wire_nl0li0l1O_dataout WHEN niOii01ll = '1' ELSE nl0l0OiiO; + wire_nl0li0l0i_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0l0Oiil; + wire_nl0li0l0l_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0l0Oiii; + wire_nl0li0l0O_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0l0Oi0O; + wire_nl0li0l1i_dataout <= wire_nl0li0l1l_dataout WHEN niOii01ll = '1' ELSE nl0l0Oili; + wire_nl0li0l1l_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0l0Oili; + wire_nl0li0l1O_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0l0OiiO; + wire_nl0li0li_dataout <= wire_nl0liiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0lii_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0l0Oi0l; + wire_nl0li0lil_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0l0Oi0i; + wire_nl0li0liO_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0l0Oi1O; + wire_nl0li0ll_dataout <= wire_nl0lil1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0lli_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0l0Oi1l; + wire_nl0li0lll_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0l0Oi1i; + wire_nl0li0llO_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0l0O0OO; + wire_nl0li0lO_dataout <= wire_nl0lil1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0lOi_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0l0O0Ol; + wire_nl0li0lOl_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0l0O0Oi; + wire_nl0li0lOO_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0l0O0lO; + wire_nl0li0O0i_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O0il; + wire_nl0li0O0l_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O0ii; + wire_nl0li0O0O_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O00O; + wire_nl0li0O1i_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0l0O0ll; + wire_nl0li0O1l_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0l0O0li; + wire_nl0li0O1O_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O0iO; + wire_nl0li0Oi_dataout <= wire_nl0lil0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0Oii_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O00l; + wire_nl0li0Oil_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O00i; + wire_nl0li0OiO_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O01O; + wire_nl0li0Ol_dataout <= wire_nl0lil0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0Oli_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0l0O01l; + wire_nl0li0Oll_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O01i; + wire_nl0li0OlO_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O1OO; + wire_nl0li0OO_dataout <= wire_nl0lil0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li0OOi_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O1Ol; + wire_nl0li0OOl_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O1Oi; + wire_nl0li0OOO_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O1lO; + wire_nl0li100i_dataout <= wire_nl0li001l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li100l_dataout <= wire_nl0li001O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li100O_dataout <= wire_nl0li000i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li101i_dataout <= wire_nl0liii0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li101l_dataout <= wire_nl0li01OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li101O_dataout <= wire_nl0li001i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10ii_dataout <= wire_nl0li000l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10il_dataout <= wire_nl0li000O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10iO_dataout <= wire_nl0li00ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10li_dataout <= wire_nl0li00il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10ll_dataout <= wire_nl0li00iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10lO_dataout <= wire_nl0li00li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10Oi_dataout <= wire_nl0li00ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10Ol_dataout <= wire_nl0li00lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li10OO_dataout <= wire_nl0li00Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li110i_dataout <= wire_nl0lii0iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li110l_dataout <= wire_nl0lii0li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li110O_dataout <= wire_nl0lii0ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li111i_dataout <= wire_nl0lii00O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li111l_dataout <= wire_nl0lii0ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li111O_dataout <= wire_nl0lii0il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11ii_dataout <= wire_nl0lii0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11il_dataout <= wire_nl0lii0Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11iO_dataout <= wire_nl0lii0Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11li_dataout <= wire_nl0lii0OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11ll_dataout <= wire_nl0liii1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11lO_dataout <= wire_nl0liii1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11Oi_dataout <= wire_nl0liii1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11Ol_dataout <= wire_nl0liii0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li11OO_dataout <= wire_nl0liii0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1i0i_dataout <= wire_nl0li0i1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1i0l_dataout <= wire_nl0li0i1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1i0O_dataout <= wire_nl0li0i0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1i1i_dataout <= wire_nl0li00Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1i1l_dataout <= wire_nl0li00OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1i1O_dataout <= wire_nl0li0i1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1iii_dataout <= wire_nl0li0i0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1iil_dataout <= wire_nl0li0i0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1iiO_dataout <= wire_nl0li0iii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1ili_dataout <= wire_nl0li0iil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1ill_dataout <= wire_nl0li0iiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1ilO_dataout <= wire_nl0li0ili_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1iOi_dataout <= wire_nl0li0ill_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1iOl_dataout <= wire_nl0li0ilO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1iOO_dataout <= wire_nl0li0iOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1l0i_dataout <= wire_nl0liiOOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1l0l_dataout <= wire_nl0liiOiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1l0O_dataout <= wire_nl0liiOli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1l1i_dataout <= wire_nl0li0iOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1l1l_dataout <= wire_nl0li0iOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1l1O_dataout <= wire_nl0li0l1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1lii_dataout <= wire_nl0liiOll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0li1lil_dataout <= wire_nl0li01iO_dataout WHEN niOii01li = '1' ELSE nl0l0i0ll; + wire_nl0li1liO_dataout <= wire_nl0li01il_dataout WHEN niOii01li = '1' ELSE nl0l0liiO; + wire_nl0li1lli_dataout <= wire_nl0li01ii_dataout WHEN niOii01li = '1' ELSE nl0l0lili; + wire_nl0li1lll_dataout <= wire_nl0li010O_dataout WHEN niOii01li = '1' ELSE nl0l0lill; + wire_nl0li1llO_dataout <= wire_nl0li010l_dataout WHEN niOii01li = '1' ELSE nl0l0lilO; + wire_nl0li1lOi_dataout <= wire_nl0li010i_dataout WHEN niOii01li = '1' ELSE nl0l0liOi; + wire_nl0li1lOl_dataout <= wire_nl0li011O_dataout WHEN niOii01li = '1' ELSE nl0l0liOl; + wire_nl0li1lOO_dataout <= wire_nl0li011l_dataout WHEN niOii01li = '1' ELSE nl0l0liOO; + wire_nl0li1O0i_dataout <= wire_nl0li1OOi_dataout WHEN niOii01li = '1' ELSE nl0l0ll0i; + wire_nl0li1O0l_dataout <= wire_nl0li1OlO_dataout WHEN niOii01li = '1' ELSE nl0l0ll0l; + wire_nl0li1O0O_dataout <= wire_nl0li1Oll_dataout WHEN niOii01li = '1' ELSE nl0l0ll0O; + wire_nl0li1O1i_dataout <= wire_nl0li011i_dataout WHEN niOii01li = '1' ELSE nl0l0ll1i; + wire_nl0li1O1l_dataout <= wire_nl0li1OOO_dataout WHEN niOii01li = '1' ELSE nl0l0ll1l; + wire_nl0li1O1O_dataout <= wire_nl0li1OOl_dataout WHEN niOii01li = '1' ELSE nl0l0ll1O; + wire_nl0li1Oii_dataout <= wire_nl0li1Oli_dataout WHEN niOii01li = '1' ELSE nl0l0llii; + wire_nl0li1Oil_dataout <= wire_nl0li1OiO_dataout WHEN niOii01li = '1' ELSE nl0l0llil; + wire_nl0li1OiO_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0l0llil; + wire_nl0li1Ol_dataout <= wire_nl0lii0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li1Oli_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0l0llii; + wire_nl0li1Oll_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0l0ll0O; + wire_nl0li1OlO_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0l0ll0l; + wire_nl0li1OO_dataout <= wire_nl0lii0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0li1OOi_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0l0ll0i; + wire_nl0li1OOl_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0l0ll1O; + wire_nl0li1OOO_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0l0ll1l; + wire_nl0lii00i_dataout <= wire_nl0liiliO_dataout WHEN niOii01lO = '1' ELSE nl0l0lO0O; + wire_nl0lii00l_dataout <= wire_nl0liilil_dataout WHEN niOii01lO = '1' ELSE nl0l0lOii; + wire_nl0lii00O_dataout <= wire_nl0liilii_dataout WHEN niOii01lO = '1' ELSE nl0l0lOil; + wire_nl0lii01i_dataout <= wire_nl0liillO_dataout WHEN niOii01lO = '1' ELSE nl0l0lO1O; + wire_nl0lii01l_dataout <= wire_nl0liilll_dataout WHEN niOii01lO = '1' ELSE nl0l0lO0i; + wire_nl0lii01O_dataout <= wire_nl0liilli_dataout WHEN niOii01lO = '1' ELSE nl0l0lO0l; + wire_nl0lii0i_dataout <= wire_nl0lil1i_o(0) WHEN n1l00il = '1' ELSE nl0l0ili; + wire_nl0lii0ii_dataout <= wire_nl0liil0O_dataout WHEN niOii01lO = '1' ELSE nl0l0lOiO; + wire_nl0lii0il_dataout <= wire_nl0liil0l_dataout WHEN niOii01lO = '1' ELSE nl0l0lOli; + wire_nl0lii0iO_dataout <= wire_nl0liil0i_dataout WHEN niOii01lO = '1' ELSE nl0l0lOll; + wire_nl0lii0l_dataout <= wire_nl0lil1i_o(1) WHEN n1l00il = '1' ELSE nl0l0OiO; + wire_nl0lii0li_dataout <= wire_nl0liil1O_dataout WHEN niOii01lO = '1' ELSE nl0l0lOlO; + wire_nl0lii0ll_dataout <= wire_nl0liil1l_dataout WHEN niOii01lO = '1' ELSE nl0l0lOOi; + wire_nl0lii0lO_dataout <= wire_nl0liil1i_dataout WHEN niOii01lO = '1' ELSE nl0l0lOOl; + wire_nl0lii0O_dataout <= wire_nl0lil1i_o(2) WHEN n1l00il = '1' ELSE nl0l0Oli; + wire_nl0lii0Oi_dataout <= wire_nl0liiiOO_dataout WHEN niOii01lO = '1' ELSE nl0l0lOOO; + wire_nl0lii0Ol_dataout <= wire_nl0liiiOl_dataout WHEN niOii01lO = '1' ELSE nl0l0O11i; + wire_nl0lii0OO_dataout <= wire_nl0liiiOi_dataout WHEN niOii01lO = '1' ELSE nl0l0O11l; + wire_nl0lii11i_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O1ll; + wire_nl0lii11l_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O1li; + wire_nl0lii11O_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0l0O1iO; + wire_nl0lii1i_dataout <= wire_nl0lilii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0lii1ii_dataout <= wire_nl0liiO0O_dataout WHEN niOii01lO = '1' ELSE nl0l0lliO; + wire_nl0lii1il_dataout <= wire_nl0liiO0l_dataout WHEN niOii01lO = '1' ELSE nl0l0llli; + wire_nl0lii1iO_dataout <= wire_nl0liiO0i_dataout WHEN niOii01lO = '1' ELSE nl0l0llll; + wire_nl0lii1l_dataout <= wire_nl0lilil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0lii1li_dataout <= wire_nl0liiO1O_dataout WHEN niOii01lO = '1' ELSE nl0l0lllO; + wire_nl0lii1ll_dataout <= wire_nl0liiO1l_dataout WHEN niOii01lO = '1' ELSE nl0l0llOi; + wire_nl0lii1lO_dataout <= wire_nl0liiO1i_dataout WHEN niOii01lO = '1' ELSE nl0l0llOl; + wire_nl0lii1O_dataout <= wire_nl0liliO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0lii1Oi_dataout <= wire_nl0liilOO_dataout WHEN niOii01lO = '1' ELSE nl0l0llOO; + wire_nl0lii1Ol_dataout <= wire_nl0liilOl_dataout WHEN niOii01lO = '1' ELSE nl0l0lO1i; + wire_nl0lii1OO_dataout <= wire_nl0liilOi_dataout WHEN niOii01lO = '1' ELSE nl0l0lO1l; + wire_nl0liii0i_dataout <= wire_nl0liiiiO_dataout WHEN niOii01lO = '1' ELSE nl0l0O10O; + wire_nl0liii0l_dataout <= wire_nl0liiiil_dataout WHEN niOii01lO = '1' ELSE nl0l0O1ii; + wire_nl0liii0O_dataout <= wire_nl0liiiii_dataout WHEN niOii01lO = '1' ELSE nl0l0O1il; + wire_nl0liii1i_dataout <= wire_nl0liiilO_dataout WHEN niOii01lO = '1' ELSE nl0l0O11O; + wire_nl0liii1l_dataout <= wire_nl0liiill_dataout WHEN niOii01lO = '1' ELSE nl0l0O10i; + wire_nl0liii1O_dataout <= wire_nl0liiili_dataout WHEN niOii01lO = '1' ELSE nl0l0O10l; + wire_nl0liiii_dataout <= wire_nl0lil1i_o(3) WHEN n1l00il = '1' ELSE nl0l0Oll; + wire_nl0liiiii_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O1il; + wire_nl0liiiil_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O1ii; + wire_nl0liiiiO_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O10O; + wire_nl0liiil_dataout <= wire_nl0lil1i_o(4) WHEN n1l00il = '1' ELSE nl0l0OlO; + wire_nl0liiili_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O10l; + wire_nl0liiill_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O10i; + wire_nl0liiilO_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O11O; + wire_nl0liiiO_dataout <= wire_nl0lil1i_o(5) WHEN n1l00il = '1' ELSE nl0l0OOi; + wire_nl0liiiOi_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O11l; + wire_nl0liiiOl_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0l0O11i; + wire_nl0liiiOO_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOOO; + wire_nl0liil0i_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOll; + wire_nl0liil0l_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOli; + wire_nl0liil0O_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOiO; + wire_nl0liil1i_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOOl; + wire_nl0liil1l_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOOi; + wire_nl0liil1O_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOlO; + wire_nl0liili_dataout <= wire_nl0lil1i_o(6) WHEN n1l00il = '1' ELSE nl0l0OOl; + wire_nl0liilii_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0l0lOil; + wire_nl0liilil_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0l0lOii; + wire_nl0liiliO_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0l0lO0O; + wire_nl0liill_dataout <= wire_nl0lil1i_o(7) WHEN n1l00il = '1' ELSE nl0l0OOO; + wire_nl0liilli_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0l0lO0l; + wire_nl0liilll_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0l0lO0i; + wire_nl0liillO_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0l0lO1O; + wire_nl0liilO_dataout <= wire_nl0lil1i_o(8) WHEN n1l00il = '1' ELSE nl0li11i; + wire_nl0liilOi_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0l0lO1l; + wire_nl0liilOl_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0l0lO1i; + wire_nl0liilOO_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0l0llOO; + wire_nl0liiO0i_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0l0llll; + wire_nl0liiO0l_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0l0llli; + wire_nl0liiO0O_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0l0lliO; + wire_nl0liiO1i_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0l0llOl; + wire_nl0liiO1l_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0l0llOi; + wire_nl0liiO1O_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0l0lllO; + wire_nl0liiOi_dataout <= wire_nl0lil1i_o(9) WHEN n1l00il = '1' ELSE nl0li11l; + wire_nl0liiOiO_dataout <= wire_nl0l1O1ii_dataout WHEN niOii01Oi = '1' ELSE nl0l0OilO; + wire_nl0liiOl_dataout <= wire_nl0lil1i_o(10) WHEN n1l00il = '1' ELSE nl0li11O; + wire_nl0liiOli_dataout <= wire_nl0l1O1il_dataout WHEN niOii01Oi = '1' ELSE nl0l0OiOi; + wire_nl0liiOll_dataout <= wire_nl0l1O1iO_dataout WHEN niOii01Oi = '1' ELSE nl0l0OiOl; + wire_nl0liiOO_dataout <= wire_nl0lil1i_o(11) WHEN n1l00il = '1' ELSE nl0li10i; + wire_nl0liiOOO_dataout <= wire_nl0l1O11O_dataout WHEN niOii01Oi = '1' ELSE nl0l0Oill; + wire_nl0lil01i_dataout <= nl0lil0il AND NOT(niOii01OO); + wire_nl0lil01i_w_lg_dataout46179w(0) <= NOT wire_nl0lil01i_dataout; + wire_nl0lil01l_dataout <= nl0lil0iO AND NOT(niOii01OO); + wire_nl0lil01l_w_lg_dataout46178w(0) <= NOT wire_nl0lil01l_dataout; + wire_nl0lil01O_dataout <= nl0lil0li AND NOT(niOii01OO); + wire_nl0lil01O_w_lg_dataout46177w(0) <= NOT wire_nl0lil01O_dataout; + wire_nl0lil0i_dataout <= wire_nl0lilli_o(2) WHEN n1lliil = '1' ELSE nl0li1ii; + wire_nl0lil0l_dataout <= wire_nl0lilli_o(3) WHEN n1lliil = '1' ELSE nl0li1il; + wire_nl0lil0lO_dataout <= wire_nl0lili0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lil0O_dataout <= wire_nl0lilli_o(4) WHEN n1lliil = '1' ELSE nl0li1iO; + wire_nl0lil0Oi_dataout <= wire_nl0lili0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lil0Ol_dataout <= wire_nl0liliii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lil0OO_dataout <= wire_nl0liliil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lil10i_dataout <= wire_nl0lil10O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lil10l_dataout <= wire_nl0l1O01l_dataout WHEN niOii01Ol = '1' ELSE nl0l0OiOO; + wire_nl0lil10O_dataout <= wire_nl0l1O01O_dataout WHEN niOii01Ol = '1' ELSE nl0lil11i; + wire_nl0lil11O_dataout <= wire_nl0lil10l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lil1l_dataout <= wire_nl0lilli_o(0) WHEN n1lliil = '1' ELSE nl0li10l; + wire_nl0lil1ll_dataout <= nl0lil11l AND NOT(niOii01OO); + wire_nl0lil1ll_w_lg_dataout46184w(0) <= NOT wire_nl0lil1ll_dataout; + wire_nl0lil1lO_dataout <= nl0lil00i AND NOT(niOii01OO); + wire_nl0lil1lO_w_lg_dataout46183w(0) <= NOT wire_nl0lil1lO_dataout; + wire_nl0lil1O_dataout <= wire_nl0lilli_o(1) WHEN n1lliil = '1' ELSE nl0li10O; + wire_nl0lil1Oi_dataout <= nl0lil00l AND NOT(niOii01OO); + wire_nl0lil1Oi_w_lg_dataout46182w(0) <= NOT wire_nl0lil1Oi_dataout; + wire_nl0lil1Ol_dataout <= nl0lil00O AND NOT(niOii01OO); + wire_nl0lil1Ol_w_lg_dataout46181w(0) <= NOT wire_nl0lil1Ol_dataout; + wire_nl0lil1OO_dataout <= nl0lil0ii AND NOT(niOii01OO); + wire_nl0lil1OO_w_lg_dataout46180w(0) <= NOT wire_nl0lil1OO_dataout; + wire_nl0lili0i_dataout <= wire_nl0lililO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lili0l_dataout <= wire_nl0l1lO1l_dataout WHEN niOii001i = '1' ELSE nl0lil11l; + wire_nl0lili0O_dataout <= wire_nl0l1lO1O_dataout WHEN niOii001i = '1' ELSE nl0lil00i; + wire_nl0lili1i_dataout <= wire_nl0liliiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lili1l_dataout <= wire_nl0lilili_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lili1O_dataout <= wire_nl0lilill_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lilii_dataout <= wire_nl0lilli_o(5) WHEN n1lliil = '1' ELSE nl0li1li; + wire_nl0liliii_dataout <= wire_nl0l1lO0i_dataout WHEN niOii001i = '1' ELSE nl0lil00l; + wire_nl0liliil_dataout <= wire_nl0l1lO0l_dataout WHEN niOii001i = '1' ELSE nl0lil00O; + wire_nl0liliiO_dataout <= wire_nl0l1lO0O_dataout WHEN niOii001i = '1' ELSE nl0lil0ii; + wire_nl0lilil_dataout <= wire_nl0lilli_o(6) WHEN n1lliil = '1' ELSE nl0li1ll; + wire_nl0lilili_dataout <= wire_nl0l1lOii_dataout WHEN niOii001i = '1' ELSE nl0lil0il; + wire_nl0lilill_dataout <= wire_nl0l1lOil_dataout WHEN niOii001i = '1' ELSE nl0lil0iO; + wire_nl0lililO_dataout <= wire_nl0l1lOiO_dataout WHEN niOii001i = '1' ELSE nl0lil0li; + wire_nl0liliO_dataout <= wire_nl0lilli_o(7) WHEN n1lliil = '1' ELSE nl0li1lO; + wire_nl0lillii_dataout <= wire_nl0lillOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lillil_dataout <= wire_nl0lilO1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lilliO_dataout <= wire_nl0lilO1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lillli_dataout <= wire_nl0lilO1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lillll_dataout <= wire_nl0lilO0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lilllO_dataout <= wire_nl0lilO0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lillOi_dataout <= wire_nl0lilO0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lillOl_dataout <= wire_nl0lilOii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0lillOO_dataout <= wire_nl0l1lO1l_dataout WHEN niOii001l = '1' ELSE nl0lil0ll; + wire_nl0lilO0i_dataout <= wire_nl0l1lO0O_dataout WHEN niOii001l = '1' ELSE nl0lill1O; + wire_nl0lilO0l_dataout <= wire_nl0l1lOii_dataout WHEN niOii001l = '1' ELSE nl0lill0i; + wire_nl0lilO0O_dataout <= wire_nl0l1lOil_dataout WHEN niOii001l = '1' ELSE nl0lill0l; + wire_nl0lilO1i_dataout <= wire_nl0l1lO1O_dataout WHEN niOii001l = '1' ELSE nl0liliOO; + wire_nl0lilO1l_dataout <= wire_nl0l1lO0i_dataout WHEN niOii001l = '1' ELSE nl0lill1i; + wire_nl0lilO1O_dataout <= wire_nl0l1lO0l_dataout WHEN niOii001l = '1' ELSE nl0lill1l; + wire_nl0lilOii_dataout <= wire_nl0l1lOiO_dataout WHEN niOii001l = '1' ELSE nl0lill0O; + wire_nl0ll00i_dataout <= wire_nl0lliiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll00l_dataout <= wire_nl0llili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll00O_dataout <= wire_nl0llill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll01i_dataout <= wire_nl0lli0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll01l_dataout <= wire_nl0lliii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll01ll_dataout <= (wire_nli0O1OOO_dataout AND (nl01l0O1i AND (nl0ll1O1l AND niOii00iO))) OR (((wire_nl0lli1li_o AND niOii00il) AND wire_w_lg_w_k_bar_range51061w51278w(0)) AND (wire_w_lg_w_lg_w_k_bar_range45712w45713w51280w(0) OR wire_w_lg_w_k_bar_range45712w51281w(0))); + wire_nl0ll01O_dataout <= wire_nl0lliil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll0ii_dataout <= wire_nl0llilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll0il_dataout <= wire_nl0lliOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll0iO_dataout <= wire_nl0lliOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll0li_dataout <= wire_nl0lOiiO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lliOO_dataout; + wire_nl0ll0ll_dataout <= wire_nl0lOili_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lll1i_dataout; + wire_nl0ll0lO_dataout <= wire_nl0lOill_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lll1l_dataout; + wire_nl0ll0Oi_dataout <= wire_nl0lOilO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lll1O_dataout; + wire_nl0ll0Ol_dataout <= wire_nl0lOiOi_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lll0i_dataout; + wire_nl0ll0OO_dataout <= wire_nl0lOiOl_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lll0l_dataout; + wire_nl0ll10i_dataout <= wire_nl0lOO1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll10l_dataout <= wire_nl0ll0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll10O_dataout <= wire_nl0ll0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll11O_dataout <= wire_nl0lOlOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1ii_dataout <= wire_nl0ll0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1il_dataout <= wire_nl0ll0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1iO_dataout <= wire_nl0ll0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1li_dataout <= wire_nl0ll0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1ll_dataout <= wire_nl0lli1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1lO_dataout <= wire_nl0lli1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1Oi_dataout <= wire_nl0lli1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1Ol_dataout <= wire_nl0lli0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0ll1OO_dataout <= wire_nl0lli0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0lli0i_dataout <= wire_nl0lOl1O_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0llliO_dataout; + wire_nl0lli0l_dataout <= wire_nl0lOl0i_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lllli_dataout; + wire_nl0lli0O_dataout <= wire_nl0lOl0l_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lllll_dataout; + wire_nl0lli1i_dataout <= wire_nl0lOiOO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lll0O_dataout; + wire_nl0lli1l_dataout <= wire_nl0lOl1i_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lllii_dataout; + wire_nl0lli1O_dataout <= wire_nl0lOl1l_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lllil_dataout; + wire_nl0lliii_dataout <= wire_nl0lOl0O_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0llllO_dataout; + wire_nl0lliil_dataout <= wire_nl0lOlii_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lllOi_dataout; + wire_nl0lliili_dataout <= (niOii0liO AND wire_w_lg_niOii0lil51127w(0)) AND NOT(wire_niO01Oil_dataout); + wire_nl0lliilO_dataout <= niOii0lOi WHEN niOii0liO = '1' ELSE k_bar(32); + wire_nl0lliilO_w_lg_dataout45745w(0) <= NOT wire_nl0lliilO_dataout; + wire_nl0lliiO_dataout <= wire_nl0lOlil_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lllOl_dataout; + wire_nl0lliiOi_dataout <= niOii0llO WHEN niOii0liO = '1' ELSE k_bar(33); + wire_nl0lliiOi_w_lg_dataout45744w(0) <= NOT wire_nl0lliiOi_dataout; + wire_nl0lliiOl_dataout <= niOii0lll WHEN niOii0liO = '1' ELSE k_bar(34); + wire_nl0lliiOl_w_lg_dataout45743w(0) <= NOT wire_nl0lliiOl_dataout; + wire_nl0lliiOO_dataout <= niOii0lli WHEN niOii0liO = '1' ELSE k_bar(35); + wire_nl0lliiOO_w_lg_dataout45742w(0) <= NOT wire_nl0lliiOO_dataout; + wire_nl0llili_dataout <= wire_nl0lOliO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0lllOO_dataout; + wire_nl0llill_dataout <= wire_nl0lOlli_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0llO1i_dataout; + wire_nl0llilO_dataout <= wire_nl0lOlll_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0llO1l_dataout; + wire_nl0lliOi_dataout <= wire_nl0lOllO_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0llO1O_dataout; + wire_nl0lliOl_dataout <= wire_nl0lOlOi_dataout WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE wire_nl0llO0i_dataout; + wire_nl0lliOO_dataout <= nl0ll11l WHEN niOO1O01i = '1' ELSE wire_nl0llO0l_dataout; + wire_nl0lll0i_dataout <= nl0O111i WHEN niOO1O01i = '1' ELSE wire_nl0llOiO_dataout; + wire_nl0lll0l_dataout <= nl0O111l WHEN niOO1O01i = '1' ELSE wire_nl0llOli_dataout; + wire_nl0lll0O_dataout <= nl0O111O WHEN niOO1O01i = '1' ELSE wire_nl0llOll_dataout; + wire_nl0lll1i_dataout <= nl0lOOOi WHEN niOO1O01i = '1' ELSE wire_nl0llO0O_dataout; + wire_nl0lll1l_dataout <= nl0lOOOl WHEN niOO1O01i = '1' ELSE wire_nl0llOii_dataout; + wire_nl0lll1O_dataout <= nl0lOOOO WHEN niOO1O01i = '1' ELSE wire_nl0llOil_dataout; + wire_nl0lllii_dataout <= nl0O110i WHEN niOO1O01i = '1' ELSE wire_nl0llOlO_dataout; + wire_nl0lllil_dataout <= nl0O110l WHEN niOO1O01i = '1' ELSE wire_nl0llOOi_dataout; + wire_nl0llliO_dataout <= nl0O110O WHEN niOO1O01i = '1' ELSE wire_nl0llOOl_dataout; + wire_nl0lllli_dataout <= nl0O11ii WHEN niOO1O01i = '1' ELSE wire_nl0llOOO_dataout; + wire_nl0lllll_dataout <= nl0O11il WHEN niOO1O01i = '1' ELSE wire_nl0lO11i_dataout; + wire_nl0llllO_dataout <= nl0O11iO WHEN niOO1O01i = '1' ELSE wire_nl0lO11l_dataout; + wire_nl0lllOi_dataout <= nl0O11li WHEN niOO1O01i = '1' ELSE wire_nl0lO11O_dataout; + wire_nl0lllOl_dataout <= nl0O11ll WHEN niOO1O01i = '1' ELSE wire_nl0lO10i_dataout; + wire_nl0lllOO_dataout <= nl0O11lO WHEN niOO1O01i = '1' ELSE wire_nl0lO10l_dataout; + wire_nl0llO00i_dataout <= wire_nl0llOl0O_dataout AND NOT(niOii0lOO); + wire_nl0llO00l_dataout <= wire_nl0llOlii_dataout AND NOT(niOii0lOO); + wire_nl0llO00O_dataout <= wire_nl0llOlil_dataout AND NOT(niOii0lOO); + wire_nl0llO01i_dataout <= wire_nl0llOl1O_dataout AND NOT(niOii0lOO); + wire_nl0llO01l_dataout <= wire_nl0llOl0i_dataout AND NOT(niOii0lOO); + wire_nl0llO01O_dataout <= wire_nl0llOl0l_dataout AND NOT(niOii0lOO); + wire_nl0llO0i_dataout <= nl0O101i WHEN niOO1O01i = '1' ELSE wire_nl0lO1iO_dataout; + wire_nl0llO0ii_dataout <= wire_nl0llOliO_dataout AND NOT(niOii0lOO); + wire_nl0llO0il_dataout <= wire_nl0llOlli_dataout AND NOT(niOii0lOO); + wire_nl0llO0iO_dataout <= wire_nl0llOlll_dataout AND NOT(niOii0lOO); + wire_nl0llO0l_dataout <= nl0O10iO WHEN niOO1O01O = '1' ELSE wire_nl0lO1li_dataout; + wire_nl0llO0li_dataout <= wire_nl0llOllO_dataout AND NOT(niOii0lOO); + wire_nl0llO0ll_dataout <= wire_nl0llOlOi_dataout AND NOT(niOii0lOO); + wire_nl0llO0lO_dataout <= wire_nl0llOlOl_dataout AND NOT(niOii0lOO); + wire_nl0llO0O_dataout <= nl0O10li WHEN niOO1O01O = '1' ELSE wire_nl0lO1ll_dataout; + wire_nl0llO0Oi_dataout <= wire_nl0llOlOO_dataout AND NOT(niOii0lOO); + wire_nl0llO0Ol_dataout <= wire_nl0llOO1i_dataout AND NOT(niOii0lOO); + wire_nl0llO0OO_dataout <= wire_nl0llOO1l_dataout AND NOT(niOii0lOO); + wire_nl0llO1i_dataout <= nl0O11Oi WHEN niOO1O01i = '1' ELSE wire_nl0lO10O_dataout; + wire_nl0llO1l_dataout <= nl0O11Ol WHEN niOO1O01i = '1' ELSE wire_nl0lO1ii_dataout; + wire_nl0llO1O_dataout <= nl0O11OO WHEN niOO1O01i = '1' ELSE wire_nl0lO1il_dataout; + wire_nl0llO1OO_dataout <= wire_nl0llOl1l_dataout AND NOT(niOii0lOO); + wire_nl0llOi0i_dataout <= wire_nl0llOO0O_dataout AND NOT(niOii0lOO); + wire_nl0llOi0l_dataout <= wire_nl0llOOii_dataout AND NOT(niOii0lOO); + wire_nl0llOi0O_dataout <= wire_nl0llOOil_dataout AND NOT(niOii0lOO); + wire_nl0llOi1i_dataout <= wire_nl0llOO1O_dataout AND NOT(niOii0lOO); + wire_nl0llOi1l_dataout <= wire_nl0llOO0i_dataout AND NOT(niOii0lOO); + wire_nl0llOi1O_dataout <= wire_nl0llOO0l_dataout AND NOT(niOii0lOO); + wire_nl0llOii_dataout <= nl0O10ll WHEN niOO1O01O = '1' ELSE wire_nl0lO1lO_dataout; + wire_nl0llOiii_dataout <= wire_nl0llOOiO_dataout AND NOT(niOii0lOO); + wire_nl0llOiil_dataout <= wire_nl0llOOli_dataout AND NOT(niOii0lOO); + wire_nl0llOiiO_dataout <= wire_nl0llOOll_dataout AND NOT(niOii0lOO); + wire_nl0llOil_dataout <= nl0O10lO WHEN niOO1O01O = '1' ELSE wire_nl0lO1Oi_dataout; + wire_nl0llOili_dataout <= wire_nl0llOOlO_dataout AND NOT(niOii0lOO); + wire_nl0llOill_dataout <= wire_nl0llOOOi_dataout AND NOT(niOii0lOO); + wire_nl0llOilO_dataout <= wire_nl0llOOOl_dataout AND NOT(niOii0lOO); + wire_nl0llOiO_dataout <= nl0O10Oi WHEN niOO1O01O = '1' ELSE wire_nl0lO1Ol_dataout; + wire_nl0llOiOi_dataout <= wire_nl0llOOOO_dataout AND NOT(niOii0lOO); + wire_nl0llOiOl_dataout <= wire_nl0lO111i_dataout AND NOT(niOii0lOO); + wire_nl0llOiOO_dataout <= wire_nl0lO111l_dataout AND NOT(niOii0lOO); + wire_nl0llOl0i_dataout <= wire_nl0lO1i1O_dataout WHEN niOii0lOl = '1' ELSE nl0llli1l; + wire_nl0llOl0l_dataout <= wire_nl0lO1i1l_dataout WHEN niOii0lOl = '1' ELSE nl0llli1O; + wire_nl0llOl0O_dataout <= wire_nl0lO1i1i_dataout WHEN niOii0lOl = '1' ELSE nl0llli0i; + wire_nl0llOl1i_dataout <= wire_nl0lO111O_dataout AND NOT(niOii0lOO); + wire_nl0llOl1l_dataout <= wire_nl0lO1i0l_dataout WHEN niOii0lOl = '1' ELSE nl0lliiiO; + wire_nl0llOl1O_dataout <= wire_nl0lO1i0i_dataout WHEN niOii0lOl = '1' ELSE nl0llli1i; + wire_nl0llOli_dataout <= nl0O10Ol WHEN niOO1O01O = '1' ELSE wire_nl0lO1OO_dataout; + wire_nl0llOlii_dataout <= wire_nl0lO10OO_dataout WHEN niOii0lOl = '1' ELSE nl0llli0l; + wire_nl0llOlil_dataout <= wire_nl0lO10Ol_dataout WHEN niOii0lOl = '1' ELSE nl0llli0O; + wire_nl0llOliO_dataout <= wire_nl0lO10Oi_dataout WHEN niOii0lOl = '1' ELSE nl0llliii; + wire_nl0llOll_dataout <= nl0O10OO WHEN niOO1O01O = '1' ELSE wire_nl0lO01i_dataout; + wire_nl0llOlli_dataout <= wire_nl0lO10lO_dataout WHEN niOii0lOl = '1' ELSE nl0llliil; + wire_nl0llOlll_dataout <= wire_nl0lO10ll_dataout WHEN niOii0lOl = '1' ELSE nl0llliiO; + wire_nl0llOllO_dataout <= wire_nl0lO10li_dataout WHEN niOii0lOl = '1' ELSE nl0lllili; + wire_nl0llOlO_dataout <= nl0O1i1i WHEN niOO1O01O = '1' ELSE wire_nl0lO01l_dataout; + wire_nl0llOlOi_dataout <= wire_nl0lO10iO_dataout WHEN niOii0lOl = '1' ELSE nl0lllill; + wire_nl0llOlOl_dataout <= wire_nl0lO10il_dataout WHEN niOii0lOl = '1' ELSE nl0lllilO; + wire_nl0llOlOO_dataout <= wire_nl0lO10ii_dataout WHEN niOii0lOl = '1' ELSE nl0llliOi; + wire_nl0llOO0i_dataout <= wire_nl0lO101O_dataout WHEN niOii0lOl = '1' ELSE nl0llll1l; + wire_nl0llOO0l_dataout <= wire_nl0lO101l_dataout WHEN niOii0lOl = '1' ELSE nl0llll1O; + wire_nl0llOO0O_dataout <= wire_nl0lO101i_dataout WHEN niOii0lOl = '1' ELSE nl0llll0i; + wire_nl0llOO1i_dataout <= wire_nl0lO100O_dataout WHEN niOii0lOl = '1' ELSE nl0llliOl; + wire_nl0llOO1l_dataout <= wire_nl0lO100l_dataout WHEN niOii0lOl = '1' ELSE nl0llliOO; + wire_nl0llOO1O_dataout <= wire_nl0lO100i_dataout WHEN niOii0lOl = '1' ELSE nl0llll1i; + wire_nl0llOOi_dataout <= nl0O1i1l WHEN niOO1O01O = '1' ELSE wire_nl0lO01O_dataout; + wire_nl0llOOii_dataout <= wire_nl0lO11OO_dataout WHEN niOii0lOl = '1' ELSE nl0llll0l; + wire_nl0llOOil_dataout <= wire_nl0lO11Ol_dataout WHEN niOii0lOl = '1' ELSE nl0llll0O; + wire_nl0llOOiO_dataout <= wire_nl0lO11Oi_dataout WHEN niOii0lOl = '1' ELSE nl0llllii; + wire_nl0llOOl_dataout <= nl0O1i1O WHEN niOO1O01O = '1' ELSE wire_nl0lO00i_dataout; + wire_nl0llOOli_dataout <= wire_nl0lO11lO_dataout WHEN niOii0lOl = '1' ELSE nl0llllil; + wire_nl0llOOll_dataout <= wire_nl0lO11ll_dataout WHEN niOii0lOl = '1' ELSE nl0lllliO; + wire_nl0llOOlO_dataout <= wire_nl0lO11li_dataout WHEN niOii0lOl = '1' ELSE nl0llllli; + wire_nl0llOOO_dataout <= nl0O1i0i WHEN niOO1O01O = '1' ELSE wire_nl0lO00l_dataout; + wire_nl0llOOOi_dataout <= wire_nl0lO11iO_dataout WHEN niOii0lOl = '1' ELSE nl0llllll; + wire_nl0llOOOl_dataout <= wire_nl0lO11il_dataout WHEN niOii0lOl = '1' ELSE nl0lllllO; + wire_nl0llOOOO_dataout <= wire_nl0lO11ii_dataout WHEN niOii0lOl = '1' ELSE nl0llllOi; + wire_nl0lO000i_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1Ol; + wire_nl0lO000l_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1Oi; + wire_nl0lO000O_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1lO; + wire_nl0lO001i_dataout <= wire_nl0lO000O_dataout WHEN niOii0O1l = '1' ELSE nl0llO1lO; + wire_nl0lO001l_dataout <= wire_nl0lO000l_dataout WHEN niOii0O1l = '1' ELSE nl0llO1Oi; + wire_nl0lO001O_dataout <= wire_nl0lO000i_dataout WHEN niOii0O1l = '1' ELSE nl0llO1Ol; + wire_nl0lO00i_dataout <= nl0O110O WHEN niOO1O1Oi = '1' ELSE nl0liO0O; + wire_nl0lO00ii_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1ll; + wire_nl0lO00il_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1li; + wire_nl0lO00iO_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1iO; + wire_nl0lO00l_dataout <= nl0O11ii WHEN niOO1O1Oi = '1' ELSE nl0liOii; + wire_nl0lO00li_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1il; + wire_nl0lO00ll_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0llO1ii; + wire_nl0lO00lO_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0llO10O; + wire_nl0lO00O_dataout <= nl0O11il WHEN niOO1O1Oi = '1' ELSE nl0liOil; + wire_nl0lO00Oi_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0llO10l; + wire_nl0lO00Ol_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0llO10i; + wire_nl0lO00OO_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0llO11O; + wire_nl0lO010i_dataout <= wire_nl0lO0i1O_dataout WHEN niOii0O1l = '1' ELSE nl0lllOOO; + wire_nl0lO010l_dataout <= wire_nl0lO0i1l_dataout WHEN niOii0O1l = '1' ELSE nl0llO11i; + wire_nl0lO010O_dataout <= wire_nl0lO0i1i_dataout WHEN niOii0O1l = '1' ELSE nl0llO11l; + wire_nl0lO011i_dataout <= wire_nl0lO0i0O_dataout WHEN niOii0O1l = '1' ELSE nl0lllOlO; + wire_nl0lO011l_dataout <= wire_nl0lO0i0l_dataout WHEN niOii0O1l = '1' ELSE nl0lllOOi; + wire_nl0lO011O_dataout <= wire_nl0lO0i0i_dataout WHEN niOii0O1l = '1' ELSE nl0lllOOl; + wire_nl0lO01i_dataout <= nl0O111O WHEN niOO1O1Oi = '1' ELSE nl0liO1O; + wire_nl0lO01ii_dataout <= wire_nl0lO00OO_dataout WHEN niOii0O1l = '1' ELSE nl0llO11O; + wire_nl0lO01il_dataout <= wire_nl0lO00Ol_dataout WHEN niOii0O1l = '1' ELSE nl0llO10i; + wire_nl0lO01iO_dataout <= wire_nl0lO00Oi_dataout WHEN niOii0O1l = '1' ELSE nl0llO10l; + wire_nl0lO01l_dataout <= nl0O110i WHEN niOO1O1Oi = '1' ELSE nl0liO0i; + wire_nl0lO01li_dataout <= wire_nl0lO00lO_dataout WHEN niOii0O1l = '1' ELSE nl0llO10O; + wire_nl0lO01ll_dataout <= wire_nl0lO00ll_dataout WHEN niOii0O1l = '1' ELSE nl0llO1ii; + wire_nl0lO01lO_dataout <= wire_nl0lO00li_dataout WHEN niOii0O1l = '1' ELSE nl0llO1il; + wire_nl0lO01O_dataout <= nl0O110l WHEN niOO1O1Oi = '1' ELSE nl0liO0l; + wire_nl0lO01Oi_dataout <= wire_nl0lO00iO_dataout WHEN niOii0O1l = '1' ELSE nl0llO1iO; + wire_nl0lO01Ol_dataout <= wire_nl0lO00il_dataout WHEN niOii0O1l = '1' ELSE nl0llO1li; + wire_nl0lO01OO_dataout <= wire_nl0lO00ii_dataout WHEN niOii0O1l = '1' ELSE nl0llO1ll; + wire_nl0lO0i0i_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0lllOOl; + wire_nl0lO0i0l_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0lllOOi; + wire_nl0lO0i0O_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0lllOlO; + wire_nl0lO0i1i_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0llO11l; + wire_nl0lO0i1l_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0llO11i; + wire_nl0lO0i1O_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0lllOOO; + wire_nl0lO0ii_dataout <= nl0O11iO WHEN niOO1O1Oi = '1' ELSE nl0liOiO; + wire_nl0lO0iii_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0lllOll; + wire_nl0lO0iil_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0lllOli; + wire_nl0lO0iiO_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0lllOiO; + wire_nl0lO0il_dataout <= nl0O11li WHEN niOO1O1Oi = '1' ELSE nl0liOli; + wire_nl0lO0ili_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0lllOil; + wire_nl0lO0ill_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0lllOii; + wire_nl0lO0ilO_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0lllO0O; + wire_nl0lO0iO_dataout <= nl0O11ll WHEN niOO1O1Oi = '1' ELSE nl0liOll; + wire_nl0lO0iOi_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0lllO0l; + wire_nl0lO0iOl_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0lllO0i; + wire_nl0lO0iOO_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0lllO1O; + wire_nl0lO0l1i_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0lllO1l; + wire_nl0lO0li_dataout <= nl0O11lO WHEN niOO1O1Oi = '1' ELSE nl0liOlO; + wire_nl0lO0ll_dataout <= nl0O11Oi WHEN niOO1O1Oi = '1' ELSE nl0liOOi; + wire_nl0lO0lO_dataout <= nl0O11Ol WHEN niOO1O1Oi = '1' ELSE nl0liOOl; + wire_nl0lO0Oi_dataout <= nl0O11OO WHEN niOO1O1Oi = '1' ELSE nl0liOOO; + wire_nl0lO0Ol_dataout <= nl0O101i WHEN niOO1O1Oi = '1' ELSE nl0ll11i; + wire_nl0lO100i_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0llll1i; + wire_nl0lO100l_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0llliOO; + wire_nl0lO100O_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0llliOl; + wire_nl0lO101i_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0llll0i; + wire_nl0lO101l_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0llll1O; + wire_nl0lO101O_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0llll1l; + wire_nl0lO10i_dataout <= nl0O1iil WHEN niOO1O01O = '1' ELSE wire_nl0lO0iO_dataout; + wire_nl0lO10ii_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0llliOi; + wire_nl0lO10il_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0lllilO; + wire_nl0lO10iO_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0lllill; + wire_nl0lO10l_dataout <= nl0O1iiO WHEN niOO1O01O = '1' ELSE wire_nl0lO0li_dataout; + wire_nl0lO10li_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0lllili; + wire_nl0lO10ll_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0llliiO; + wire_nl0lO10lO_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0llliil; + wire_nl0lO10O_dataout <= nl0O1ili WHEN niOO1O01O = '1' ELSE wire_nl0lO0ll_dataout; + wire_nl0lO10Oi_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0llliii; + wire_nl0lO10Ol_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0llli0O; + wire_nl0lO10OO_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0llli0l; + wire_nl0lO110i_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0lllO1i; + wire_nl0lO110l_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0llllOO; + wire_nl0lO110O_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0llllOl; + wire_nl0lO111i_dataout <= wire_nl0lO110O_dataout WHEN niOii0lOl = '1' ELSE nl0llllOl; + wire_nl0lO111l_dataout <= wire_nl0lO110l_dataout WHEN niOii0lOl = '1' ELSE nl0llllOO; + wire_nl0lO111O_dataout <= wire_nl0lO110i_dataout WHEN niOii0lOl = '1' ELSE nl0lllO1i; + wire_nl0lO11i_dataout <= nl0O1i0l WHEN niOO1O01O = '1' ELSE wire_nl0lO00O_dataout; + wire_nl0lO11ii_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0llllOi; + wire_nl0lO11il_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0lllllO; + wire_nl0lO11iO_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0llllll; + wire_nl0lO11l_dataout <= nl0O1i0O WHEN niOO1O01O = '1' ELSE wire_nl0lO0ii_dataout; + wire_nl0lO11li_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0llllli; + wire_nl0lO11ll_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0lllliO; + wire_nl0lO11lO_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0llllil; + wire_nl0lO11O_dataout <= nl0O1iii WHEN niOO1O01O = '1' ELSE wire_nl0lO0il_dataout; + wire_nl0lO11Oi_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0llllii; + wire_nl0lO11Ol_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0llll0O; + wire_nl0lO11OO_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0llll0l; + wire_nl0lO1i0i_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0llli1i; + wire_nl0lO1i0l_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0lliiiO; + wire_nl0lO1i1i_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0llli0i; + wire_nl0lO1i1l_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0llli1O; + wire_nl0lO1i1O_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0llli1l; + wire_nl0lO1ii_dataout <= nl0O1ill WHEN niOO1O01O = '1' ELSE wire_nl0lO0lO_dataout; + wire_nl0lO1iil_dataout <= wire_nl0lO1O0O_dataout AND NOT(niOii0O1O); + wire_nl0lO1iiO_dataout <= wire_nl0lO1Oii_dataout AND NOT(niOii0O1O); + wire_nl0lO1il_dataout <= nl0O1ilO WHEN niOO1O01O = '1' ELSE wire_nl0lO0Oi_dataout; + wire_nl0lO1ili_dataout <= wire_nl0lO1Oil_dataout AND NOT(niOii0O1O); + wire_nl0lO1ill_dataout <= wire_nl0lO1OiO_dataout AND NOT(niOii0O1O); + wire_nl0lO1ilO_dataout <= wire_nl0lO1Oli_dataout AND NOT(niOii0O1O); + wire_nl0lO1iO_dataout <= nl0O1iOi WHEN niOO1O01O = '1' ELSE wire_nl0lO0Ol_dataout; + wire_nl0lO1iOi_dataout <= wire_nl0lO1Oll_dataout AND NOT(niOii0O1O); + wire_nl0lO1iOl_dataout <= wire_nl0lO1OlO_dataout AND NOT(niOii0O1O); + wire_nl0lO1iOO_dataout <= wire_nl0lO1OOi_dataout AND NOT(niOii0O1O); + wire_nl0lO1l0i_dataout <= wire_nl0lO011l_dataout AND NOT(niOii0O1O); + wire_nl0lO1l0l_dataout <= wire_nl0lO011O_dataout AND NOT(niOii0O1O); + wire_nl0lO1l0O_dataout <= wire_nl0lO010i_dataout AND NOT(niOii0O1O); + wire_nl0lO1l1i_dataout <= wire_nl0lO1OOl_dataout AND NOT(niOii0O1O); + wire_nl0lO1l1l_dataout <= wire_nl0lO1OOO_dataout AND NOT(niOii0O1O); + wire_nl0lO1l1O_dataout <= wire_nl0lO011i_dataout AND NOT(niOii0O1O); + wire_nl0lO1li_dataout <= nl0ll11l WHEN niOO1O1Oi = '1' ELSE nl0lillO; + wire_nl0lO1lii_dataout <= wire_nl0lO010l_dataout AND NOT(niOii0O1O); + wire_nl0lO1lil_dataout <= wire_nl0lO010O_dataout AND NOT(niOii0O1O); + wire_nl0lO1liO_dataout <= wire_nl0lO01ii_dataout AND NOT(niOii0O1O); + wire_nl0lO1ll_dataout <= nl0lOOOi WHEN niOO1O1Oi = '1' ELSE nl0lilOi; + wire_nl0lO1lli_dataout <= wire_nl0lO01il_dataout AND NOT(niOii0O1O); + wire_nl0lO1lll_dataout <= wire_nl0lO01iO_dataout AND NOT(niOii0O1O); + wire_nl0lO1llO_dataout <= wire_nl0lO01li_dataout AND NOT(niOii0O1O); + wire_nl0lO1lO_dataout <= nl0lOOOl WHEN niOO1O1Oi = '1' ELSE nl0lilOl; + wire_nl0lO1lOi_dataout <= wire_nl0lO01ll_dataout AND NOT(niOii0O1O); + wire_nl0lO1lOl_dataout <= wire_nl0lO01lO_dataout AND NOT(niOii0O1O); + wire_nl0lO1lOO_dataout <= wire_nl0lO01Oi_dataout AND NOT(niOii0O1O); + wire_nl0lO1O0i_dataout <= wire_nl0lO001l_dataout AND NOT(niOii0O1O); + wire_nl0lO1O0l_dataout <= wire_nl0lO001O_dataout AND NOT(niOii0O1O); + wire_nl0lO1O0O_dataout <= wire_nl0lO0l1i_dataout WHEN niOii0O1l = '1' ELSE nl0lllO1l; + wire_nl0lO1O1i_dataout <= wire_nl0lO01Ol_dataout AND NOT(niOii0O1O); + wire_nl0lO1O1l_dataout <= wire_nl0lO01OO_dataout AND NOT(niOii0O1O); + wire_nl0lO1O1O_dataout <= wire_nl0lO001i_dataout AND NOT(niOii0O1O); + wire_nl0lO1Oi_dataout <= nl0lOOOO WHEN niOO1O1Oi = '1' ELSE nl0lilOO; + wire_nl0lO1Oii_dataout <= wire_nl0lO0iOO_dataout WHEN niOii0O1l = '1' ELSE nl0lllO1O; + wire_nl0lO1Oil_dataout <= wire_nl0lO0iOl_dataout WHEN niOii0O1l = '1' ELSE nl0lllO0i; + wire_nl0lO1OiO_dataout <= wire_nl0lO0iOi_dataout WHEN niOii0O1l = '1' ELSE nl0lllO0l; + wire_nl0lO1Ol_dataout <= nl0O111i WHEN niOO1O1Oi = '1' ELSE nl0liO1i; + wire_nl0lO1Oli_dataout <= wire_nl0lO0ilO_dataout WHEN niOii0O1l = '1' ELSE nl0lllO0O; + wire_nl0lO1Oll_dataout <= wire_nl0lO0ill_dataout WHEN niOii0O1l = '1' ELSE nl0lllOii; + wire_nl0lO1OlO_dataout <= wire_nl0lO0ili_dataout WHEN niOii0O1l = '1' ELSE nl0lllOil; + wire_nl0lO1OO_dataout <= nl0O111l WHEN niOO1O1Oi = '1' ELSE nl0liO1l; + wire_nl0lO1OOi_dataout <= wire_nl0lO0iiO_dataout WHEN niOii0O1l = '1' ELSE nl0lllOiO; + wire_nl0lO1OOl_dataout <= wire_nl0lO0iil_dataout WHEN niOii0O1l = '1' ELSE nl0lllOli; + wire_nl0lO1OOO_dataout <= wire_nl0lO0iii_dataout WHEN niOii0O1l = '1' ELSE nl0lllOll; + wire_nl0lOiiO_dataout <= nl0O10iO WHEN niOO1O01O = '1' ELSE nl0lillO; + wire_nl0lOili_dataout <= nl0O10li WHEN niOO1O01O = '1' ELSE nl0lilOi; + wire_nl0lOill_dataout <= nl0O10ll WHEN niOO1O01O = '1' ELSE nl0lilOl; + wire_nl0lOilO_dataout <= nl0O10lO WHEN niOO1O01O = '1' ELSE nl0lilOO; + wire_nl0lOiOi_dataout <= nl0O10Oi WHEN niOO1O01O = '1' ELSE nl0liO1i; + wire_nl0lOiOl_dataout <= nl0O10Ol WHEN niOO1O01O = '1' ELSE nl0liO1l; + wire_nl0lOiOO_dataout <= nl0O10OO WHEN niOO1O01O = '1' ELSE nl0liO1O; + wire_nl0lOl0i_dataout <= nl0O1i0i WHEN niOO1O01O = '1' ELSE nl0liOii; + wire_nl0lOl0l_dataout <= nl0O1i0l WHEN niOO1O01O = '1' ELSE nl0liOil; + wire_nl0lOl0O_dataout <= nl0O1i0O WHEN niOO1O01O = '1' ELSE nl0liOiO; + wire_nl0lOl1i_dataout <= nl0O1i1i WHEN niOO1O01O = '1' ELSE nl0liO0i; + wire_nl0lOl1l_dataout <= nl0O1i1l WHEN niOO1O01O = '1' ELSE nl0liO0l; + wire_nl0lOl1O_dataout <= nl0O1i1O WHEN niOO1O01O = '1' ELSE nl0liO0O; + wire_nl0lOlii_dataout <= nl0O1iii WHEN niOO1O01O = '1' ELSE nl0liOli; + wire_nl0lOlil_dataout <= nl0O1iil WHEN niOO1O01O = '1' ELSE nl0liOll; + wire_nl0lOliO_dataout <= nl0O1iiO WHEN niOO1O01O = '1' ELSE nl0liOlO; + wire_nl0lOlli_dataout <= nl0O1ili WHEN niOO1O01O = '1' ELSE nl0liOOi; + wire_nl0lOlll_dataout <= nl0O1ill WHEN niOO1O01O = '1' ELSE nl0liOOl; + wire_nl0lOllO_dataout <= nl0O1ilO WHEN niOO1O01O = '1' ELSE nl0liOOO; + wire_nl0lOlO0l_dataout <= (wire_nli0O1OOO_dataout AND (nl01l0O1i AND (nl0lOlill AND niOii0Oil))) OR (((wire_nl0lOOO0i_o AND niOii0Oii) AND wire_w_lg_w_k_bar_range50184w50400w(0)) AND (wire_w_lg_w_lg_w_k_bar_range45805w45806w50402w(0) OR wire_w_lg_w_k_bar_range45805w50403w(0))); + wire_nl0lOlOi_dataout <= nl0O1iOi WHEN niOO1O01O = '1' ELSE nl0ll11i; + wire_nl0lOlOl_dataout <= nl0li1Oi OR ((niOO1O0lO AND niOO1O00l) OR (niOO1O0il AND niOO1O00i)); + wire_nl0lOO1O_dataout <= nl0lilll OR ((niOO1O0lO AND niOO1O0ii) OR (niOO1O0il AND niOO1O00O)); + wire_nl0O000i_dataout <= wire_nl01iilO_q(15) AND NOT(wire_niO01l0O_dataout); + wire_nl0O000l_dataout <= wire_nl01iilO_q(16) AND NOT(wire_niO01l0O_dataout); + wire_nl0O000O_dataout <= wire_nl01iilO_q(17) AND NOT(wire_niO01l0O_dataout); + wire_nl0O001i_dataout <= wire_nl01iilO_q(12) AND NOT(wire_niO01l0O_dataout); + wire_nl0O001l_dataout <= wire_nl01iilO_q(13) AND NOT(wire_niO01l0O_dataout); + wire_nl0O001O_dataout <= wire_nl01iilO_q(14) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00ii_dataout <= wire_nl01iilO_q(18) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00il_dataout <= wire_nl01iilO_q(19) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00iO_dataout <= wire_nl01iilO_q(20) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00li_dataout <= wire_nl01iilO_q(21) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00ll_dataout <= wire_nl01iilO_q(22) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00lO_dataout <= wire_nl01iilO_q(23) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00Oi_dataout <= wire_nl01iilO_q(24) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00Ol_dataout <= wire_nl01iilO_q(25) AND NOT(wire_niO01l0O_dataout); + wire_nl0O00OO_dataout <= wire_nl01iilO_q(26) AND NOT(wire_niO01l0O_dataout); + wire_nl0O010i_dataout <= wire_nl01iilO_q(0) AND NOT(wire_niO01l0O_dataout); + wire_nl0O010l_dataout <= wire_nl01iilO_q(1) AND NOT(wire_niO01l0O_dataout); + wire_nl0O010O_dataout <= wire_nl01iilO_q(2) AND NOT(wire_niO01l0O_dataout); + wire_nl0O0110i_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0O1ii0i; + wire_nl0O0110l_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0O1ii1O; + wire_nl0O0110O_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0O1ii1l; + wire_nl0O0111i_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0O1iiii; + wire_nl0O0111l_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0O1ii0O; + wire_nl0O0111O_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0O1ii0l; + wire_nl0O011i_dataout <= wire_nl0O0lli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O011ii_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0O1ii1i; + wire_nl0O011il_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0O1i0OO; + wire_nl0O011iO_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0O1i0Ol; + wire_nl0O011l_dataout <= wire_nl0O0lll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O011li_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0O1i0Oi; + wire_nl0O011ll_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0O1i0lO; + wire_nl0O011O_dataout <= wire_nl0O0llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O01ii_dataout <= wire_nl01iilO_q(3) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01il_dataout <= wire_nl01iilO_q(4) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01iO_dataout <= wire_nl01iilO_q(5) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01li_dataout <= wire_nl01iilO_q(6) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01ll_dataout <= wire_nl01iilO_q(7) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01lO_dataout <= wire_nl01iilO_q(8) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01Oi_dataout <= wire_nl01iilO_q(9) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01Ol_dataout <= wire_nl01iilO_q(10) AND NOT(wire_niO01l0O_dataout); + wire_nl0O01OO_dataout <= wire_nl01iilO_q(11) AND NOT(wire_niO01l0O_dataout); + wire_nl0O0i0i_dataout <= wire_nl01iilO_q(30) AND k_hip(0); + wire_nl0O0i0l_dataout <= wire_nl01iilO_q(31) AND k_hip(0); + wire_nl0O0i0O_dataout <= wire_nl01iilO_q(32) AND k_hip(0); + wire_nl0O0i0OO_dataout <= (wire_nli0O1OOO_dataout AND (nl01l0O1i AND (nl0O0i10O AND niOiiii0O))) OR (((wire_nl0O0l0Ol_o AND niOiiii0l) AND wire_w_lg_w_k_bar_range49299w49515w(0)) AND (wire_w_lg_w_lg_w_k_bar_range45915w45916w49517w(0) OR wire_w_lg_w_k_bar_range45915w49518w(0))); + wire_nl0O0i1i_dataout <= wire_nl01iilO_q(27) AND k_hip(0); + wire_nl0O0i1l_dataout <= wire_nl01iilO_q(28) AND k_hip(0); + wire_nl0O0i1O_dataout <= wire_nl01iilO_q(29) AND k_hip(0); + wire_nl0O0iii_dataout <= wire_nl01iilO_q(33) AND k_hip(0); + wire_nl0O0iil_dataout <= wire_nl01iilO_q(34) AND k_hip(0); + wire_nl0O0iiO_dataout <= wire_nl01iilO_q(35) AND k_hip(0); + wire_nl0O0ili_dataout <= wire_nl01iilO_q(36) AND k_hip(0); + wire_nl0O0ill_dataout <= wire_nl01iilO_q(37) AND k_hip(0); + wire_nl0O0ilO_dataout <= wire_nl01iilO_q(38) AND k_hip(0); + wire_nl0O0iOi_dataout <= wire_nl01iilO_q(39) AND k_hip(0); + wire_nl0O0iOl_dataout <= wire_nl01iilO_q(40) AND k_hip(0); + wire_nl0O0iOO_dataout <= wire_nl01iilO_q(41) AND k_hip(0); + wire_nl0O0l0i_dataout <= wire_nl01iilO_q(45) AND k_hip(0); + wire_nl0O0l0l_dataout <= wire_nl01iilO_q(46) AND k_hip(0); + wire_nl0O0l0O_dataout <= wire_nl01iilO_q(47) AND k_hip(0); + wire_nl0O0l1i_dataout <= wire_nl01iilO_q(42) AND k_hip(0); + wire_nl0O0l1l_dataout <= wire_nl01iilO_q(43) AND k_hip(0); + wire_nl0O0l1O_dataout <= wire_nl01iilO_q(44) AND k_hip(0); + wire_nl0O0lii_dataout <= wire_nl01iilO_q(48) AND k_hip(0); + wire_nl0O0lil_dataout <= wire_nl01iilO_q(49) AND k_hip(0); + wire_nl0O0liO_dataout <= wire_nl01iilO_q(50) AND k_hip(0); + wire_nl0O0lli_dataout <= wire_nl01iilO_q(51) AND k_hip(0); + wire_nl0O0lll_dataout <= wire_nl01iilO_q(52) AND k_hip(0); + wire_nl0O0llO_dataout <= wire_nl01iilO_q(53) AND k_hip(0); + wire_nl0O0llOl_dataout <= (niOili1OO AND (niOiiO1li AND wire_w_lg_niOiiiO0l49363w(0))) AND NOT(wire_niO01Oil_dataout); + wire_nl0O0lO0i_dataout <= niOiiiOii WHEN niOiiO1li = '1' ELSE k_bar(162); + wire_nl0O0lO0i_w_lg_dataout45973w(0) <= NOT wire_nl0O0lO0i_dataout; + wire_nl0O0lO0l_dataout <= niOiiiO0O WHEN niOiiO1li = '1' ELSE k_bar(163); + wire_nl0O0lO0l_w_lg_dataout45972w(0) <= NOT wire_nl0O0lO0l_dataout; + wire_nl0O0lO1l_dataout <= niOiiiOiO WHEN niOiiO1li = '1' ELSE k_bar(160); + wire_nl0O0lO1l_w_lg_dataout45975w(0) <= NOT wire_nl0O0lO1l_dataout; + wire_nl0O0lO1O_dataout <= niOiiiOil WHEN niOiiO1li = '1' ELSE k_bar(161); + wire_nl0O0lO1O_w_lg_dataout45974w(0) <= NOT wire_nl0O0lO1O_dataout; + wire_nl0O0lOi_dataout <= nllii0OlO AND nl0OiO0O; + wire_nl0O0lOl_dataout <= nlliii0Oi AND nl0OiO0O; + wire_nl0O0lOO_dataout <= nlliii0Ol AND nl0OiO0O; + wire_nl0O0O0i_dataout <= nlliiii1O AND nl0OiO0O; + wire_nl0O0O0l_dataout <= nlliiii0i AND nl0OiO0O; + wire_nl0O0O0O_dataout <= nlliiii0l AND nl0OiO0O; + wire_nl0O0O1i_dataout <= nlliii0OO AND nl0OiO0O; + wire_nl0O0O1l_dataout <= nlliiii1i AND nl0OiO0O; + wire_nl0O0O1O_dataout <= nlliiii1l AND nl0OiO0O; + wire_nl0O0Oii_dataout <= nlliiii0O AND nl0OiO0O; + wire_nl0O0Oil_dataout <= nlliiiiii AND nl0OiO0O; + wire_nl0O0OiO_dataout <= nlliiiiil AND nl0OiO0O; + wire_nl0O0Ol0O_dataout <= nl0O0llOi AND niOili1OO; + wire_nl0O0Ol0O_w_lg_dataout49705w(0) <= NOT wire_nl0O0Ol0O_dataout; + wire_nl0O0Oli_dataout <= nlliiiiiO AND nl0OiO0O; + wire_nl0O0Olii_dataout <= nl0Oi1i0O AND niOili1OO; + wire_nl0O0Olii_w_lg_dataout49703w(0) <= NOT wire_nl0O0Olii_dataout; + wire_nl0O0Olil_dataout <= nl0Oi1iii AND niOili1OO; + wire_nl0O0Olil_w_lg_dataout49701w(0) <= NOT wire_nl0O0Olil_dataout; + wire_nl0O0OliO_dataout <= nl0Oi1iil AND niOili1OO; + wire_nl0O0OliO_w_lg_dataout49699w(0) <= NOT wire_nl0O0OliO_dataout; + wire_nl0O0Oll_dataout <= nlliiiili AND nl0OiO0O; + wire_nl0O0Olli_dataout <= nl0Oi1iiO AND niOili1OO; + wire_nl0O0Olli_w_lg_dataout49697w(0) <= NOT wire_nl0O0Olli_dataout; + wire_nl0O0Olll_dataout <= nl0Oi1ili AND niOili1OO; + wire_nl0O0Olll_w_lg_dataout49695w(0) <= NOT wire_nl0O0Olll_dataout; + wire_nl0O0OllO_dataout <= nl0Oi1ill AND niOili1OO; + wire_nl0O0OllO_w_lg_dataout49693w(0) <= NOT wire_nl0O0OllO_dataout; + wire_nl0O0OlO_dataout <= nlliiiill AND nl0OiO0O; + wire_nl0O0OlOi_dataout <= nl0Oi1ilO AND niOili1OO; + wire_nl0O0OlOi_w_lg_dataout49691w(0) <= NOT wire_nl0O0OlOi_dataout; + wire_nl0O0OlOl_dataout <= nl0Oi1iOi AND niOili1OO; + wire_nl0O0OlOl_w_lg_dataout49689w(0) <= NOT wire_nl0O0OlOl_dataout; + wire_nl0O0OlOO_dataout <= nl0Oi1iOl AND niOili1OO; + wire_nl0O0OlOO_w_lg_dataout49687w(0) <= NOT wire_nl0O0OlOO_dataout; + wire_nl0O0OO0i_dataout <= nl0Oi1l1O AND niOili1OO; + wire_nl0O0OO0i_w_lg_dataout49679w(0) <= NOT wire_nl0O0OO0i_dataout; + wire_nl0O0OO0l_dataout <= nl0Oi1l0i AND niOili1OO; + wire_nl0O0OO0l_w_lg_dataout49677w(0) <= NOT wire_nl0O0OO0l_dataout; + wire_nl0O0OO0O_dataout <= nl0Oi1l0l AND niOili1OO; + wire_nl0O0OO0O_w_lg_dataout49675w(0) <= NOT wire_nl0O0OO0O_dataout; + wire_nl0O0OO1i_dataout <= nl0Oi1iOO AND niOili1OO; + wire_nl0O0OO1i_w_lg_dataout49685w(0) <= NOT wire_nl0O0OO1i_dataout; + wire_nl0O0OO1l_dataout <= nl0Oi1l1i AND niOili1OO; + wire_nl0O0OO1l_w_lg_dataout49683w(0) <= NOT wire_nl0O0OO1l_dataout; + wire_nl0O0OO1O_dataout <= nl0Oi1l1l AND niOili1OO; + wire_nl0O0OO1O_w_lg_dataout49681w(0) <= NOT wire_nl0O0OO1O_dataout; + wire_nl0O0OOi_dataout <= nlliiiilO AND nl0OiO0O; + wire_nl0O0OOii_dataout <= nl0Oi1l0O AND niOili1OO; + wire_nl0O0OOii_w_lg_dataout49673w(0) <= NOT wire_nl0O0OOii_dataout; + wire_nl0O0OOil_dataout <= nl0Oi1lii AND niOili1OO; + wire_nl0O0OOil_w_lg_dataout49671w(0) <= NOT wire_nl0O0OOil_dataout; + wire_nl0O0OOiO_dataout <= nl0Oi1lil AND niOili1OO; + wire_nl0O0OOiO_w_lg_dataout49669w(0) <= NOT wire_nl0O0OOiO_dataout; + wire_nl0O0OOl_dataout <= nlliiiiOi AND nl0OiO0O; + wire_nl0O0OOli_dataout <= nl0Oi1liO AND niOili1OO; + wire_nl0O0OOli_w_lg_dataout49667w(0) <= NOT wire_nl0O0OOli_dataout; + wire_nl0O0OOll_dataout <= nl0Oi1lli AND niOili1OO; + wire_nl0O0OOll_w_lg_dataout49665w(0) <= NOT wire_nl0O0OOll_dataout; + wire_nl0O0OOlO_dataout <= nl0Oi1lll AND niOili1OO; + wire_nl0O0OOlO_w_lg_dataout49663w(0) <= NOT wire_nl0O0OOlO_dataout; + wire_nl0O0OOO_dataout <= nlliiiiOl AND nl0OiO0O; + wire_nl0O0OOOi_dataout <= nl0Oi1llO AND niOili1OO; + wire_nl0O0OOOi_w_lg_dataout49661w(0) <= NOT wire_nl0O0OOOi_dataout; + wire_nl0O0OOOl_dataout <= nl0Oi1lOi AND niOili1OO; + wire_nl0O0OOOl_w_lg_dataout49659w(0) <= NOT wire_nl0O0OOOl_dataout; + wire_nl0O0OOOO_dataout <= nl0Oi1lOl AND niOili1OO; + wire_nl0O0OOOO_w_lg_dataout49657w(0) <= NOT wire_nl0O0OOOO_dataout; + wire_nl0O1000i_dataout <= nl0O1i11O AND niOili1OO; + wire_nl0O1000i_w_lg_dataout50573w(0) <= NOT wire_nl0O1000i_dataout; + wire_nl0O1000l_dataout <= nl0O1i10i AND niOili1OO; + wire_nl0O1000l_w_lg_dataout50571w(0) <= NOT wire_nl0O1000l_dataout; + wire_nl0O1000O_dataout <= nl0O1i10l AND niOili1OO; + wire_nl0O1000O_w_lg_dataout50569w(0) <= NOT wire_nl0O1000O_dataout; + wire_nl0O1001i_dataout <= nl0O10OOO AND niOili1OO; + wire_nl0O1001i_w_lg_dataout50579w(0) <= NOT wire_nl0O1001i_dataout; + wire_nl0O1001l_dataout <= nl0O1i11i AND niOili1OO; + wire_nl0O1001l_w_lg_dataout50577w(0) <= NOT wire_nl0O1001l_dataout; + wire_nl0O1001O_dataout <= nl0O1i11l AND niOili1OO; + wire_nl0O1001O_w_lg_dataout50575w(0) <= NOT wire_nl0O1001O_dataout; + wire_nl0O100ii_dataout <= nl0O1i10O AND niOili1OO; + wire_nl0O100ii_w_lg_dataout50567w(0) <= NOT wire_nl0O100ii_dataout; + wire_nl0O100il_dataout <= nl0O1i1ii AND niOili1OO; + wire_nl0O100il_w_lg_dataout50565w(0) <= NOT wire_nl0O100il_dataout; + wire_nl0O100iO_dataout <= nl0O1i1il AND niOili1OO; + wire_nl0O100iO_w_lg_dataout50563w(0) <= NOT wire_nl0O100iO_dataout; + wire_nl0O100li_dataout <= nl0O1i1iO AND niOili1OO; + wire_nl0O100li_w_lg_dataout50561w(0) <= NOT wire_nl0O100li_dataout; + wire_nl0O100ll_dataout <= nl0O1i1li AND niOili1OO; + wire_nl0O100ll_w_lg_dataout50559w(0) <= NOT wire_nl0O100ll_dataout; + wire_nl0O100lO_dataout <= nl0O1i1ll AND niOili1OO; + wire_nl0O100lO_w_lg_dataout50557w(0) <= NOT wire_nl0O100lO_dataout; + wire_nl0O100Oi_dataout <= nl0O1i1lO AND niOili1OO; + wire_nl0O100Oi_w_lg_dataout50555w(0) <= NOT wire_nl0O100Oi_dataout; + wire_nl0O100Ol_dataout <= nl0O1i1Oi AND niOili1OO; + wire_nl0O100Ol_w_lg_dataout50553w(0) <= NOT wire_nl0O100Ol_dataout; + wire_nl0O100OO_dataout <= nl0O1i1Ol AND niOili1OO; + wire_nl0O100OO_w_lg_dataout50551w(0) <= NOT wire_nl0O100OO_dataout; + wire_nl0O101ll_dataout <= nl0O1101O AND niOili1OO; + wire_nl0O101ll_w_lg_dataout50589w(0) <= NOT wire_nl0O101ll_dataout; + wire_nl0O101lO_dataout <= nl0O10Oll AND niOili1OO; + wire_nl0O101lO_w_lg_dataout50587w(0) <= NOT wire_nl0O101lO_dataout; + wire_nl0O101Oi_dataout <= nl0O10OlO AND niOili1OO; + wire_nl0O101Oi_w_lg_dataout50585w(0) <= NOT wire_nl0O101Oi_dataout; + wire_nl0O101Ol_dataout <= nl0O10OOi AND niOili1OO; + wire_nl0O101Ol_w_lg_dataout50583w(0) <= NOT wire_nl0O101Ol_dataout; + wire_nl0O101OO_dataout <= nl0O10OOl AND niOili1OO; + wire_nl0O101OO_w_lg_dataout50581w(0) <= NOT wire_nl0O101OO_dataout; + wire_nl0O10i0i_dataout <= nl0O1i01O AND niOili1OO; + wire_nl0O10i0i_w_lg_dataout50543w(0) <= NOT wire_nl0O10i0i_dataout; + wire_nl0O10i0l_dataout <= nl0O1i00i AND niOili1OO; + wire_nl0O10i0l_w_lg_dataout50541w(0) <= NOT wire_nl0O10i0l_dataout; + wire_nl0O10i0O_dataout <= nl0O1i00l AND niOili1OO; + wire_nl0O10i0O_w_lg_dataout50539w(0) <= NOT wire_nl0O10i0O_dataout; + wire_nl0O10i1i_dataout <= nl0O1i1OO AND niOili1OO; + wire_nl0O10i1i_w_lg_dataout50549w(0) <= NOT wire_nl0O10i1i_dataout; + wire_nl0O10i1l_dataout <= nl0O1i01i AND niOili1OO; + wire_nl0O10i1l_w_lg_dataout50547w(0) <= NOT wire_nl0O10i1l_dataout; + wire_nl0O10i1O_dataout <= nl0O1i01l AND niOili1OO; + wire_nl0O10i1O_w_lg_dataout50545w(0) <= NOT wire_nl0O10i1O_dataout; + wire_nl0O10iii_dataout <= nl0O1i00O AND niOili1OO; + wire_nl0O10iii_w_lg_dataout50537w(0) <= NOT wire_nl0O10iii_dataout; + wire_nl0O10iil_dataout <= nl0O1i0ii AND niOili1OO; + wire_nl0O10iil_w_lg_dataout50535w(0) <= NOT wire_nl0O10iil_dataout; + wire_nl0O10iiO_dataout <= nl0O1i0il AND niOili1OO; + wire_nl0O10iiO_w_lg_dataout50533w(0) <= NOT wire_nl0O10iiO_dataout; + wire_nl0O10ili_dataout <= nl0O1i0iO AND niOili1OO; + wire_nl0O10ili_w_lg_dataout50531w(0) <= NOT wire_nl0O10ili_dataout; + wire_nl0O10ill_dataout <= nl0O1i0li AND niOili1OO; + wire_nl0O10ill_w_lg_dataout50529w(0) <= NOT wire_nl0O10ill_dataout; + wire_nl0O10ilO_dataout <= nl0O1i0ll AND niOili1OO; + wire_nl0O10ilO_w_lg_dataout50528w(0) <= NOT wire_nl0O10ilO_dataout; + wire_nl0O10iOi_dataout <= nl0O1i0lO AND niOili1OO; + wire_nl0O10iOl_dataout <= nl0O1i0Oi AND niOili1OO; + wire_nl0O10iOO_dataout <= nl0O1i0Ol AND niOili1OO; + wire_nl0O10l0i_dataout <= nl0O1ii1O AND niOili1OO; + wire_nl0O10l0l_dataout <= nl0O1ii0i AND niOili1OO; + wire_nl0O10l0O_dataout <= nl0O1ii0l AND niOili1OO; + wire_nl0O10l1i_dataout <= nl0O1i0OO AND niOili1OO; + wire_nl0O10l1l_dataout <= nl0O1ii1i AND niOili1OO; + wire_nl0O10l1O_dataout <= nl0O1ii1l AND niOili1OO; + wire_nl0O10lii_dataout <= nl0O1ii0O AND niOili1OO; + wire_nl0O10lil_dataout <= nl0O1iiii AND niOili1OO; + wire_nl0O10liO_dataout <= nl0O1iiil AND niOili1OO; + wire_nl0O10lli_dataout <= nl0O1iiiO AND niOili1OO; + wire_nl0O10lll_dataout <= nl0O1iili AND niOili1OO; + wire_nl0O10llO_dataout <= nl0O1iill AND niOili1OO; + wire_nl0O10lOi_dataout <= nl0O1iilO AND niOili1OO; + wire_nl0O10lOl_dataout <= nl0O1iiOi AND niOili1OO; + wire_nl0O10lOO_dataout <= nl0O1iiOl AND niOili1OO; + wire_nl0O10O0i_dataout <= nl0O1il1O AND niOili1OO; + wire_nl0O10O0l_dataout <= nl0O1il0i AND niOili1OO; + wire_nl0O10O0O_dataout <= nl0O1il0l AND niOili1OO; + wire_nl0O10O1i_dataout <= nl0O1iiOO AND niOili1OO; + wire_nl0O10O1l_dataout <= nl0O1il1i AND niOili1OO; + wire_nl0O10O1O_dataout <= nl0O1il1l AND niOili1OO; + wire_nl0O10Oii_dataout <= nl0O1il0O AND niOili1OO; + wire_nl0O10Oil_dataout <= nl0O1ilii AND niOili1OO; + wire_nl0O10OiO_dataout <= nl0O1ilil AND niOili1OO; + wire_nl0O10Oli_dataout <= nl0O1iliO AND niOili1OO; + wire_nl0O1100i_dataout <= (niOili1OO AND (niOiiO10O AND wire_w_lg_niOiii0ii50248w(0))) AND NOT(wire_niO01Oil_dataout); + wire_nl0O110ii_dataout <= niOiii0ll WHEN niOiiO10O = '1' ELSE k_bar(96); + wire_nl0O110ii_w_lg_dataout45855w(0) <= NOT wire_nl0O110ii_dataout; + wire_nl0O110il_dataout <= niOiii0li WHEN niOiiO10O = '1' ELSE k_bar(97); + wire_nl0O110il_w_lg_dataout45854w(0) <= NOT wire_nl0O110il_dataout; + wire_nl0O110iO_dataout <= niOiii0iO WHEN niOiiO10O = '1' ELSE k_bar(98); + wire_nl0O110iO_w_lg_dataout45853w(0) <= NOT wire_nl0O110iO_dataout; + wire_nl0O110li_dataout <= niOiii0il WHEN niOiiO10O = '1' ELSE k_bar(99); + wire_nl0O110li_w_lg_dataout45852w(0) <= NOT wire_nl0O110li_dataout; + wire_nl0O1illi_dataout <= wire_nl0O1l1lO_dataout AND NOT(niOiii0Oi); + wire_nl0O1illl_dataout <= wire_nl0O1l1Oi_dataout AND NOT(niOiii0Oi); + wire_nl0O1illO_dataout <= wire_nl0O1l1Ol_dataout AND NOT(niOiii0Oi); + wire_nl0O1ilOi_dataout <= wire_nl0O1l1OO_dataout AND NOT(niOiii0Oi); + wire_nl0O1ilOl_dataout <= wire_nl0O1l01i_dataout AND NOT(niOiii0Oi); + wire_nl0O1ilOO_dataout <= wire_nl0O1l01l_dataout AND NOT(niOiii0Oi); + wire_nl0O1iO0i_dataout <= wire_nl0O1l00O_dataout AND NOT(niOiii0Oi); + wire_nl0O1iO0l_dataout <= wire_nl0O1l0ii_dataout AND NOT(niOiii0Oi); + wire_nl0O1iO0O_dataout <= wire_nl0O1l0il_dataout AND NOT(niOiii0Oi); + wire_nl0O1iO1i_dataout <= wire_nl0O1l01O_dataout AND NOT(niOiii0Oi); + wire_nl0O1iO1l_dataout <= wire_nl0O1l00i_dataout AND NOT(niOiii0Oi); + wire_nl0O1iO1O_dataout <= wire_nl0O1l00l_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOii_dataout <= wire_nl0O1l0iO_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOil_dataout <= wire_nl0O1l0li_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOiO_dataout <= wire_nl0O1l0ll_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOli_dataout <= wire_nl0O1l0lO_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOll_dataout <= wire_nl0O1l0Oi_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOlO_dataout <= wire_nl0O1l0Ol_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOOi_dataout <= wire_nl0O1l0OO_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOOl_dataout <= wire_nl0O1li1i_dataout AND NOT(niOiii0Oi); + wire_nl0O1iOOO_dataout <= wire_nl0O1li1l_dataout AND NOT(niOiii0Oi); + wire_nl0O1l00i_dataout <= wire_nl0O1lOil_dataout WHEN niOiii0lO = '1' ELSE nl0O1i11l; + wire_nl0O1l00l_dataout <= wire_nl0O1lOii_dataout WHEN niOiii0lO = '1' ELSE nl0O1i11O; + wire_nl0O1l00O_dataout <= wire_nl0O1lO0O_dataout WHEN niOiii0lO = '1' ELSE nl0O1i10i; + wire_nl0O1l01i_dataout <= wire_nl0O1lOll_dataout WHEN niOiii0lO = '1' ELSE nl0O10OOl; + wire_nl0O1l01l_dataout <= wire_nl0O1lOli_dataout WHEN niOiii0lO = '1' ELSE nl0O10OOO; + wire_nl0O1l01O_dataout <= wire_nl0O1lOiO_dataout WHEN niOiii0lO = '1' ELSE nl0O1i11i; + wire_nl0O1l0ii_dataout <= wire_nl0O1lO0l_dataout WHEN niOiii0lO = '1' ELSE nl0O1i10l; + wire_nl0O1l0il_dataout <= wire_nl0O1lO0i_dataout WHEN niOiii0lO = '1' ELSE nl0O1i10O; + wire_nl0O1l0iO_dataout <= wire_nl0O1lO1O_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1ii; + wire_nl0O1l0li_dataout <= wire_nl0O1lO1l_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1il; + wire_nl0O1l0ll_dataout <= wire_nl0O1lO1i_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1iO; + wire_nl0O1l0lO_dataout <= wire_nl0O1llOO_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1li; + wire_nl0O1l0Oi_dataout <= wire_nl0O1llOl_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1ll; + wire_nl0O1l0Ol_dataout <= wire_nl0O1llOi_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1lO; + wire_nl0O1l0OO_dataout <= wire_nl0O1lllO_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1Oi; + wire_nl0O1l10i_dataout <= wire_nl0O1li0O_dataout AND NOT(niOiii0Oi); + wire_nl0O1l10l_dataout <= wire_nl0O1liii_dataout AND NOT(niOiii0Oi); + wire_nl0O1l10O_dataout <= wire_nl0O1liil_dataout AND NOT(niOiii0Oi); + wire_nl0O1l11i_dataout <= wire_nl0O1li1O_dataout AND NOT(niOiii0Oi); + wire_nl0O1l11l_dataout <= wire_nl0O1li0i_dataout AND NOT(niOiii0Oi); + wire_nl0O1l11O_dataout <= wire_nl0O1li0l_dataout AND NOT(niOiii0Oi); + wire_nl0O1l1ii_dataout <= wire_nl0O1liiO_dataout AND NOT(niOiii0Oi); + wire_nl0O1l1il_dataout <= wire_nl0O1lili_dataout AND NOT(niOiii0Oi); + wire_nl0O1l1iO_dataout <= wire_nl0O1lill_dataout AND NOT(niOiii0Oi); + wire_nl0O1l1li_dataout <= wire_nl0O1lilO_dataout AND NOT(niOiii0Oi); + wire_nl0O1l1ll_dataout <= wire_nl0O1liOi_dataout AND NOT(niOiii0Oi); + wire_nl0O1l1lO_dataout <= wire_nl0O1lOOO_dataout WHEN niOiii0lO = '1' ELSE nl0O1101O; + wire_nl0O1l1Oi_dataout <= wire_nl0O1lOOl_dataout WHEN niOiii0lO = '1' ELSE nl0O10Oll; + wire_nl0O1l1Ol_dataout <= wire_nl0O1lOOi_dataout WHEN niOiii0lO = '1' ELSE nl0O10OlO; + wire_nl0O1l1OO_dataout <= wire_nl0O1lOlO_dataout WHEN niOiii0lO = '1' ELSE nl0O10OOi; + wire_nl0O1li0i_dataout <= wire_nl0O1llil_dataout WHEN niOiii0lO = '1' ELSE nl0O1i01l; + wire_nl0O1li0l_dataout <= wire_nl0O1llii_dataout WHEN niOiii0lO = '1' ELSE nl0O1i01O; + wire_nl0O1li0O_dataout <= wire_nl0O1ll0O_dataout WHEN niOiii0lO = '1' ELSE nl0O1i00i; + wire_nl0O1li1i_dataout <= wire_nl0O1llll_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1Ol; + wire_nl0O1li1l_dataout <= wire_nl0O1llli_dataout WHEN niOiii0lO = '1' ELSE nl0O1i1OO; + wire_nl0O1li1O_dataout <= wire_nl0O1lliO_dataout WHEN niOiii0lO = '1' ELSE nl0O1i01i; + wire_nl0O1lii_dataout <= wire_nl0O0i1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1liii_dataout <= wire_nl0O1ll0l_dataout WHEN niOiii0lO = '1' ELSE nl0O1i00l; + wire_nl0O1liil_dataout <= wire_nl0O1ll0i_dataout WHEN niOiii0lO = '1' ELSE nl0O1i00O; + wire_nl0O1liiO_dataout <= wire_nl0O1ll1O_dataout WHEN niOiii0lO = '1' ELSE nl0O1i0ii; + wire_nl0O1lil_dataout <= wire_nl0O0i1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1lili_dataout <= wire_nl0O1ll1l_dataout WHEN niOiii0lO = '1' ELSE nl0O1i0il; + wire_nl0O1lill_dataout <= wire_nl0O1ll1i_dataout WHEN niOiii0lO = '1' ELSE nl0O1i0iO; + wire_nl0O1lilO_dataout <= wire_nl0O1liOO_dataout WHEN niOiii0lO = '1' ELSE nl0O1i0li; + wire_nl0O1liO_dataout <= wire_nl0O0i1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1liOi_dataout <= wire_nl0O1liOl_dataout WHEN niOiii0lO = '1' ELSE nl0O1i0ll; + wire_nl0O1liOl_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i0ll; + wire_nl0O1liOO_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i0li; + wire_nl0O1ll0i_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i00O; + wire_nl0O1ll0l_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i00l; + wire_nl0O1ll0O_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i00i; + wire_nl0O1ll1i_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i0iO; + wire_nl0O1ll1l_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i0il; + wire_nl0O1ll1O_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0O1i0ii; + wire_nl0O1lli_dataout <= wire_nl0O0i0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1llii_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i01O; + wire_nl0O1llil_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i01l; + wire_nl0O1lliO_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i01i; + wire_nl0O1lll_dataout <= wire_nl0O0i0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1llli_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i1OO; + wire_nl0O1llll_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i1Ol; + wire_nl0O1lllO_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i1Oi; + wire_nl0O1llO_dataout <= wire_nl0O0i0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1llOi_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i1lO; + wire_nl0O1llOl_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0O1i1ll; + wire_nl0O1llOO_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i1li; + wire_nl0O1lO0i_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i10O; + wire_nl0O1lO0l_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i10l; + wire_nl0O1lO0O_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i10i; + wire_nl0O1lO1i_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i1iO; + wire_nl0O1lO1l_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i1il; + wire_nl0O1lO1O_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i1ii; + wire_nl0O1lOi_dataout <= wire_nl0O0iii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1lOii_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0O1i11O; + wire_nl0O1lOil_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0O1i11l; + wire_nl0O1lOiO_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0O1i11i; + wire_nl0O1lOl_dataout <= wire_nl0O0iil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1lOli_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0O10OOO; + wire_nl0O1lOll_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0O10OOl; + wire_nl0O1lOlO_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0O10OOi; + wire_nl0O1lOO_dataout <= wire_nl0O0iiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1lOOi_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0O10OlO; + wire_nl0O1lOOl_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0O10Oll; + wire_nl0O1lOOO_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0O1101O; + wire_nl0O1O00i_dataout <= wire_nl0O1Ol1l_dataout AND NOT(niOiiii1i); + wire_nl0O1O00l_dataout <= wire_nl0O1Ol1O_dataout AND NOT(niOiiii1i); + wire_nl0O1O00O_dataout <= wire_nl0O1Ol0i_dataout AND NOT(niOiiii1i); + wire_nl0O1O01i_dataout <= wire_nl0O1OiOl_dataout AND NOT(niOiiii1i); + wire_nl0O1O01l_dataout <= wire_nl0O1OiOO_dataout AND NOT(niOiiii1i); + wire_nl0O1O01O_dataout <= wire_nl0O1Ol1i_dataout AND NOT(niOiiii1i); + wire_nl0O1O0i_dataout <= wire_nl0O0iOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1O0ii_dataout <= wire_nl0O1Ol0l_dataout AND NOT(niOiiii1i); + wire_nl0O1O0il_dataout <= wire_nl0O1Ol0O_dataout AND NOT(niOiiii1i); + wire_nl0O1O0iO_dataout <= wire_nl0O1Olii_dataout AND NOT(niOiiii1i); + wire_nl0O1O0l_dataout <= wire_nl0O0iOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1O0li_dataout <= wire_nl0O1Olil_dataout AND NOT(niOiiii1i); + wire_nl0O1O0ll_dataout <= wire_nl0O1OliO_dataout AND NOT(niOiiii1i); + wire_nl0O1O0lO_dataout <= wire_nl0O1Olli_dataout AND NOT(niOiiii1i); + wire_nl0O1O0O_dataout <= wire_nl0O0iOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1O0Oi_dataout <= wire_nl0O1Olll_dataout AND NOT(niOiiii1i); + wire_nl0O1O0Ol_dataout <= wire_nl0O1OllO_dataout AND NOT(niOiiii1i); + wire_nl0O1O0OO_dataout <= wire_nl0O1OlOi_dataout AND NOT(niOiiii1i); + wire_nl0O1O10i_dataout <= wire_nl0O1Oi1l_dataout AND NOT(niOiiii1i); + wire_nl0O1O10l_dataout <= wire_nl0O1Oi1O_dataout AND NOT(niOiiii1i); + wire_nl0O1O10O_dataout <= wire_nl0O1Oi0i_dataout AND NOT(niOiiii1i); + wire_nl0O1O11O_dataout <= wire_nl0O1Oi1i_dataout AND NOT(niOiiii1i); + wire_nl0O1O1i_dataout <= wire_nl0O0ili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1O1ii_dataout <= wire_nl0O1Oi0l_dataout AND NOT(niOiiii1i); + wire_nl0O1O1il_dataout <= wire_nl0O1Oi0O_dataout AND NOT(niOiiii1i); + wire_nl0O1O1iO_dataout <= wire_nl0O1Oiii_dataout AND NOT(niOiiii1i); + wire_nl0O1O1l_dataout <= wire_nl0O0ill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1O1li_dataout <= wire_nl0O1Oiil_dataout AND NOT(niOiiii1i); + wire_nl0O1O1ll_dataout <= wire_nl0O1OiiO_dataout AND NOT(niOiiii1i); + wire_nl0O1O1lO_dataout <= wire_nl0O1Oili_dataout AND NOT(niOiiii1i); + wire_nl0O1O1O_dataout <= wire_nl0O0ilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1O1Oi_dataout <= wire_nl0O1Oill_dataout AND NOT(niOiiii1i); + wire_nl0O1O1Ol_dataout <= wire_nl0O1OilO_dataout AND NOT(niOiiii1i); + wire_nl0O1O1OO_dataout <= wire_nl0O1OiOi_dataout AND NOT(niOiiii1i); + wire_nl0O1Oi0i_dataout <= wire_nl0O011il_dataout WHEN niOiii0OO = '1' ELSE nl0O1i0OO; + wire_nl0O1Oi0l_dataout <= wire_nl0O011ii_dataout WHEN niOiii0OO = '1' ELSE nl0O1ii1i; + wire_nl0O1Oi0O_dataout <= wire_nl0O0110O_dataout WHEN niOiii0OO = '1' ELSE nl0O1ii1l; + wire_nl0O1Oi1i_dataout <= wire_nl0O011ll_dataout WHEN niOiii0OO = '1' ELSE nl0O1i0lO; + wire_nl0O1Oi1l_dataout <= wire_nl0O011li_dataout WHEN niOiii0OO = '1' ELSE nl0O1i0Oi; + wire_nl0O1Oi1O_dataout <= wire_nl0O011iO_dataout WHEN niOiii0OO = '1' ELSE nl0O1i0Ol; + wire_nl0O1Oii_dataout <= wire_nl0O0l1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1Oiii_dataout <= wire_nl0O0110l_dataout WHEN niOiii0OO = '1' ELSE nl0O1ii1O; + wire_nl0O1Oiil_dataout <= wire_nl0O0110i_dataout WHEN niOiii0OO = '1' ELSE nl0O1ii0i; + wire_nl0O1OiiO_dataout <= wire_nl0O0111O_dataout WHEN niOiii0OO = '1' ELSE nl0O1ii0l; + wire_nl0O1Oil_dataout <= wire_nl0O0l1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1Oili_dataout <= wire_nl0O0111l_dataout WHEN niOiii0OO = '1' ELSE nl0O1ii0O; + wire_nl0O1Oill_dataout <= wire_nl0O0111i_dataout WHEN niOiii0OO = '1' ELSE nl0O1iiii; + wire_nl0O1OilO_dataout <= wire_nl0O1OOOO_dataout WHEN niOiii0OO = '1' ELSE nl0O1iiil; + wire_nl0O1OiO_dataout <= wire_nl0O0l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1OiOi_dataout <= wire_nl0O1OOOl_dataout WHEN niOiii0OO = '1' ELSE nl0O1iiiO; + wire_nl0O1OiOl_dataout <= wire_nl0O1OOOi_dataout WHEN niOiii0OO = '1' ELSE nl0O1iili; + wire_nl0O1OiOO_dataout <= wire_nl0O1OOlO_dataout WHEN niOiii0OO = '1' ELSE nl0O1iill; + wire_nl0O1Ol0i_dataout <= wire_nl0O1OOil_dataout WHEN niOiii0OO = '1' ELSE nl0O1iiOO; + wire_nl0O1Ol0l_dataout <= wire_nl0O1OOii_dataout WHEN niOiii0OO = '1' ELSE nl0O1il1i; + wire_nl0O1Ol0O_dataout <= wire_nl0O1OO0O_dataout WHEN niOiii0OO = '1' ELSE nl0O1il1l; + wire_nl0O1Ol1i_dataout <= wire_nl0O1OOll_dataout WHEN niOiii0OO = '1' ELSE nl0O1iilO; + wire_nl0O1Ol1l_dataout <= wire_nl0O1OOli_dataout WHEN niOiii0OO = '1' ELSE nl0O1iiOi; + wire_nl0O1Ol1O_dataout <= wire_nl0O1OOiO_dataout WHEN niOiii0OO = '1' ELSE nl0O1iiOl; + wire_nl0O1Oli_dataout <= wire_nl0O0l0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1Olii_dataout <= wire_nl0O1OO0l_dataout WHEN niOiii0OO = '1' ELSE nl0O1il1O; + wire_nl0O1Olil_dataout <= wire_nl0O1OO0i_dataout WHEN niOiii0OO = '1' ELSE nl0O1il0i; + wire_nl0O1OliO_dataout <= wire_nl0O1OO1O_dataout WHEN niOiii0OO = '1' ELSE nl0O1il0l; + wire_nl0O1Oll_dataout <= wire_nl0O0l0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1Olli_dataout <= wire_nl0O1OO1l_dataout WHEN niOiii0OO = '1' ELSE nl0O1il0O; + wire_nl0O1Olll_dataout <= wire_nl0O1OO1i_dataout WHEN niOiii0OO = '1' ELSE nl0O1ilii; + wire_nl0O1OllO_dataout <= wire_nl0O1OlOO_dataout WHEN niOiii0OO = '1' ELSE nl0O1ilil; + wire_nl0O1OlO_dataout <= wire_nl0O0l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1OlOi_dataout <= wire_nl0O1OlOl_dataout WHEN niOiii0OO = '1' ELSE nl0O1iliO; + wire_nl0O1OlOl_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0O1iliO; + wire_nl0O1OlOO_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0O1ilil; + wire_nl0O1OO0i_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0O1il0i; + wire_nl0O1OO0l_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0O1il1O; + wire_nl0O1OO0O_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0O1il1l; + wire_nl0O1OO1i_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0O1ilii; + wire_nl0O1OO1l_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0O1il0O; + wire_nl0O1OO1O_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0O1il0l; + wire_nl0O1OOi_dataout <= wire_nl0O0lii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1OOii_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0O1il1i; + wire_nl0O1OOil_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0O1iiOO; + wire_nl0O1OOiO_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0O1iiOl; + wire_nl0O1OOl_dataout <= wire_nl0O0lil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1OOli_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0O1iiOi; + wire_nl0O1OOll_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0O1iilO; + wire_nl0O1OOlO_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0O1iill; + wire_nl0O1OOO_dataout <= wire_nl0O0liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0O1OOOi_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0O1iili; + wire_nl0O1OOOl_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0O1iiiO; + wire_nl0O1OOOO_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0O1iiil; + wire_nl0Oi000l_dataout <= wire_nl0Oi0lii_dataout AND NOT(niOiiiOll); + wire_nl0Oi000O_dataout <= wire_nl0Oi0lil_dataout AND NOT(niOiiiOll); + wire_nl0Oi00i_dataout <= nlliiii0O AND niOO1Oi1i; + wire_nl0Oi00ii_dataout <= wire_nl0Oi0liO_dataout AND NOT(niOiiiOll); + wire_nl0Oi00il_dataout <= wire_nl0Oi0lli_dataout AND NOT(niOiiiOll); + wire_nl0Oi00iO_dataout <= wire_nl0Oi0lll_dataout AND NOT(niOiiiOll); + wire_nl0Oi00l_dataout <= nlliiiiii AND niOO1Oi1i; + wire_nl0Oi00li_dataout <= wire_nl0Oi0llO_dataout AND NOT(niOiiiOll); + wire_nl0Oi00ll_dataout <= wire_nl0Oi0lOi_dataout AND NOT(niOiiiOll); + wire_nl0Oi00lO_dataout <= wire_nl0Oi0lOl_dataout AND NOT(niOiiiOll); + wire_nl0Oi00O_dataout <= nlliiiiil AND niOO1Oi1i; + wire_nl0Oi00Oi_dataout <= wire_nl0Oi0lOO_dataout AND NOT(niOiiiOll); + wire_nl0Oi00Ol_dataout <= wire_nl0Oi0O1i_dataout AND NOT(niOiiiOll); + wire_nl0Oi00OO_dataout <= wire_nl0Oi0O1l_dataout AND NOT(niOiiiOll); + wire_nl0Oi01i_dataout <= nlliiii1O AND niOO1Oi1i; + wire_nl0Oi01l_dataout <= nlliiii0i AND niOO1Oi1i; + wire_nl0Oi01O_dataout <= nlliiii0l AND niOO1Oi1i; + wire_nl0Oi0i0i_dataout <= wire_nl0Oi0O0O_dataout AND NOT(niOiiiOll); + wire_nl0Oi0i0l_dataout <= wire_nl0Oi0Oii_dataout AND NOT(niOiiiOll); + wire_nl0Oi0i0O_dataout <= wire_nl0Oi0Oil_dataout AND NOT(niOiiiOll); + wire_nl0Oi0i1i_dataout <= wire_nl0Oi0O1O_dataout AND NOT(niOiiiOll); + wire_nl0Oi0i1l_dataout <= wire_nl0Oi0O0i_dataout AND NOT(niOiiiOll); + wire_nl0Oi0i1O_dataout <= wire_nl0Oi0O0l_dataout AND NOT(niOiiiOll); + wire_nl0Oi0ii_dataout <= nlliiiiiO AND niOO1Oi1i; + wire_nl0Oi0iii_dataout <= wire_nl0Oi0OiO_dataout AND NOT(niOiiiOll); + wire_nl0Oi0iil_dataout <= wire_nl0Oi0Oli_dataout AND NOT(niOiiiOll); + wire_nl0Oi0iiO_dataout <= wire_nl0Oi0Oll_dataout AND NOT(niOiiiOll); + wire_nl0Oi0il_dataout <= nlliiiili AND niOO1Oi1i; + wire_nl0Oi0ili_dataout <= wire_nl0Oi0OlO_dataout AND NOT(niOiiiOll); + wire_nl0Oi0ill_dataout <= wire_nl0Oi0OOi_dataout AND NOT(niOiiiOll); + wire_nl0Oi0ilO_dataout <= wire_nl0Oi0OOl_dataout AND NOT(niOiiiOll); + wire_nl0Oi0iO_dataout <= nlliiiill AND niOO1Oi1i; + wire_nl0Oi0iOi_dataout <= wire_nl0Oi0OOO_dataout AND NOT(niOiiiOll); + wire_nl0Oi0iOl_dataout <= wire_nl0Oii11i_dataout AND NOT(niOiiiOll); + wire_nl0Oi0iOO_dataout <= wire_nl0Oii11l_dataout AND NOT(niOiiiOll); + wire_nl0Oi0l0i_dataout <= wire_nl0Oii10O_dataout AND NOT(niOiiiOll); + wire_nl0Oi0l0l_dataout <= wire_nl0Oii1ii_dataout AND NOT(niOiiiOll); + wire_nl0Oi0l0O_dataout <= wire_nl0Oii1il_dataout AND NOT(niOiiiOll); + wire_nl0Oi0l1i_dataout <= wire_nl0Oii11O_dataout AND NOT(niOiiiOll); + wire_nl0Oi0l1l_dataout <= wire_nl0Oii10i_dataout AND NOT(niOiiiOll); + wire_nl0Oi0l1O_dataout <= wire_nl0Oii10l_dataout AND NOT(niOiiiOll); + wire_nl0Oi0li_dataout <= nlliiiilO AND niOO1Oi1i; + wire_nl0Oi0lii_dataout <= wire_nl0Oiiili_dataout WHEN niOiiiOli = '1' ELSE nl0O0llOi; + wire_nl0Oi0lil_dataout <= wire_nl0OiiiiO_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1i0O; + wire_nl0Oi0liO_dataout <= wire_nl0Oiiiil_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1iii; + wire_nl0Oi0ll_dataout <= nlliiiiOi AND niOO1Oi1i; + wire_nl0Oi0lli_dataout <= wire_nl0Oiiiii_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1iil; + wire_nl0Oi0lll_dataout <= wire_nl0Oiii0O_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1iiO; + wire_nl0Oi0llO_dataout <= wire_nl0Oiii0l_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1ili; + wire_nl0Oi0lO_dataout <= nlliiiiOl AND niOO1Oi1i; + wire_nl0Oi0lOi_dataout <= wire_nl0Oiii0i_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1ill; + wire_nl0Oi0lOl_dataout <= wire_nl0Oiii1O_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1ilO; + wire_nl0Oi0lOO_dataout <= wire_nl0Oiii1l_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1iOi; + wire_nl0Oi0O0i_dataout <= wire_nl0Oii0Oi_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1l1l; + wire_nl0Oi0O0l_dataout <= wire_nl0Oii0lO_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1l1O; + wire_nl0Oi0O0O_dataout <= wire_nl0Oii0ll_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1l0i; + wire_nl0Oi0O1i_dataout <= wire_nl0Oiii1i_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1iOl; + wire_nl0Oi0O1l_dataout <= wire_nl0Oii0OO_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1iOO; + wire_nl0Oi0O1O_dataout <= wire_nl0Oii0Ol_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1l1i; + wire_nl0Oi0Oi_dataout <= nlliiiiOO AND niOO1Oi1i; + wire_nl0Oi0Oii_dataout <= wire_nl0Oii0li_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1l0l; + wire_nl0Oi0Oil_dataout <= wire_nl0Oii0iO_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1l0O; + wire_nl0Oi0OiO_dataout <= wire_nl0Oii0il_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1lii; + wire_nl0Oi0Ol_dataout <= nlliiil1i AND niOO1Oi1i; + wire_nl0Oi0Oli_dataout <= wire_nl0Oii0ii_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1lil; + wire_nl0Oi0Oll_dataout <= wire_nl0Oii00O_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1liO; + wire_nl0Oi0OlO_dataout <= wire_nl0Oii00l_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1lli; + wire_nl0Oi0OO_dataout <= nlliiil1l AND niOO1Oi1i; + wire_nl0Oi0OOi_dataout <= wire_nl0Oii00i_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1lll; + wire_nl0Oi0OOl_dataout <= wire_nl0Oii01O_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1llO; + wire_nl0Oi0OOO_dataout <= wire_nl0Oii01l_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1lOi; + wire_nl0Oi100i_dataout <= nl0Oi011O AND niOili1OO; + wire_nl0Oi100l_dataout <= nl0Oi010i AND niOili1OO; + wire_nl0Oi100O_dataout <= nl0Oi010l AND niOili1OO; + wire_nl0Oi101i_dataout <= nl0Oi1OOO AND niOili1OO; + wire_nl0Oi101l_dataout <= nl0Oi011i AND niOili1OO; + wire_nl0Oi101O_dataout <= nl0Oi011l AND niOili1OO; + wire_nl0Oi10i_dataout <= nlliiil1O AND nl0OiO0O; + wire_nl0Oi10ii_dataout <= nl0Oi010O AND niOili1OO; + wire_nl0Oi10il_dataout <= nl0Oi01ii AND niOili1OO; + wire_nl0Oi10iO_dataout <= nl0Oi01il AND niOili1OO; + wire_nl0Oi10l_dataout <= nlliiil0i AND nl0OiO0O; + wire_nl0Oi10li_dataout <= nl0Oi01iO AND niOili1OO; + wire_nl0Oi10ll_dataout <= nl0Oi01li AND niOili1OO; + wire_nl0Oi10lO_dataout <= nl0Oi01ll AND niOili1OO; + wire_nl0Oi10O_dataout <= nlliiil0l AND nl0OiO0O; + wire_nl0Oi10Oi_dataout <= nl0Oi01lO AND niOili1OO; + wire_nl0Oi10Ol_dataout <= nl0Oi01Oi AND niOili1OO; + wire_nl0Oi10OO_dataout <= nl0Oi01Ol AND niOili1OO; + wire_nl0Oi110i_dataout <= nl0Oi1O1O AND niOili1OO; + wire_nl0Oi110i_w_lg_dataout49649w(0) <= NOT wire_nl0Oi110i_dataout; + wire_nl0Oi110l_dataout <= nl0Oi1O0i AND niOili1OO; + wire_nl0Oi110l_w_lg_dataout49647w(0) <= NOT wire_nl0Oi110l_dataout; + wire_nl0Oi110O_dataout <= nl0Oi1O0l AND niOili1OO; + wire_nl0Oi110O_w_lg_dataout49645w(0) <= NOT wire_nl0Oi110O_dataout; + wire_nl0Oi111i_dataout <= nl0Oi1lOO AND niOili1OO; + wire_nl0Oi111i_w_lg_dataout49655w(0) <= NOT wire_nl0Oi111i_dataout; + wire_nl0Oi111l_dataout <= nl0Oi1O1i AND niOili1OO; + wire_nl0Oi111l_w_lg_dataout49653w(0) <= NOT wire_nl0Oi111l_dataout; + wire_nl0Oi111O_dataout <= nl0Oi1O1l AND niOili1OO; + wire_nl0Oi111O_w_lg_dataout49651w(0) <= NOT wire_nl0Oi111O_dataout; + wire_nl0Oi11i_dataout <= nlliiiiOO AND nl0OiO0O; + wire_nl0Oi11ii_dataout <= nl0Oi1O0O AND niOili1OO; + wire_nl0Oi11ii_w_lg_dataout49644w(0) <= NOT wire_nl0Oi11ii_dataout; + wire_nl0Oi11il_dataout <= nl0Oi1Oii AND niOili1OO; + wire_nl0Oi11iO_dataout <= nl0Oi1Oil AND niOili1OO; + wire_nl0Oi11l_dataout <= nlliiil1i AND nl0OiO0O; + wire_nl0Oi11li_dataout <= nl0Oi1OiO AND niOili1OO; + wire_nl0Oi11ll_dataout <= nl0Oi1Oli AND niOili1OO; + wire_nl0Oi11lO_dataout <= nl0Oi1Oll AND niOili1OO; + wire_nl0Oi11O_dataout <= nlliiil1l AND nl0OiO0O; + wire_nl0Oi11Oi_dataout <= nl0Oi1OlO AND niOili1OO; + wire_nl0Oi11Ol_dataout <= nl0Oi1OOi AND niOili1OO; + wire_nl0Oi11OO_dataout <= nl0Oi1OOl AND niOili1OO; + wire_nl0Oi1i0i_dataout <= nl0Oi001O AND niOili1OO; + wire_nl0Oi1i0l_dataout <= nl0Oi000i AND niOili1OO; + wire_nl0Oi1i1i_dataout <= nl0Oi01OO AND niOili1OO; + wire_nl0Oi1i1l_dataout <= nl0Oi001i AND niOili1OO; + wire_nl0Oi1i1O_dataout <= nl0Oi001l AND niOili1OO; + wire_nl0Oi1ii_dataout <= nlliiil0O AND nl0OiO0O; + wire_nl0Oi1il_dataout <= nlliiilii AND nl0OiO0O; + wire_nl0Oi1iO_dataout <= wire_nlOi01O0O_dataout AND nl0OiO0O; + wire_nl0Oi1li_dataout <= nllii0OlO AND niOO1Oi1i; + wire_nl0Oi1ll_dataout <= nlliii0Oi AND niOO1Oi1i; + wire_nl0Oi1lO_dataout <= nlliii0Ol AND niOO1Oi1i; + wire_nl0Oi1Oi_dataout <= nlliii0OO AND niOO1Oi1i; + wire_nl0Oi1Ol_dataout <= nlliiii1i AND niOO1Oi1i; + wire_nl0Oi1OO_dataout <= nlliiii1l AND niOO1Oi1i; + wire_nl0Oii00i_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1lll; + wire_nl0Oii00l_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1lli; + wire_nl0Oii00O_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1liO; + wire_nl0Oii01i_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1lOl; + wire_nl0Oii01l_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1lOi; + wire_nl0Oii01O_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1llO; + wire_nl0Oii0i_dataout <= nlliiil0O AND niOO1Oi1i; + wire_nl0Oii0ii_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1lil; + wire_nl0Oii0il_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1lii; + wire_nl0Oii0iO_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi1l0O; + wire_nl0Oii0l_dataout <= nlliiilii AND niOO1Oi1i; + wire_nl0Oii0li_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1l0l; + wire_nl0Oii0ll_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1l0i; + wire_nl0Oii0lO_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1l1O; + wire_nl0Oii0O_dataout <= wire_nlOi01O0O_dataout AND niOO1Oi1i; + wire_nl0Oii0Oi_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1l1l; + wire_nl0Oii0Ol_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1l1i; + wire_nl0Oii0OO_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1iOO; + wire_nl0Oii10i_dataout <= wire_nl0Oii1Oi_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1O1l; + wire_nl0Oii10l_dataout <= wire_nl0Oii1lO_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1O1O; + wire_nl0Oii10O_dataout <= wire_nl0Oii1ll_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1O0i; + wire_nl0Oii11i_dataout <= wire_nl0Oii01i_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1lOl; + wire_nl0Oii11l_dataout <= wire_nl0Oii1OO_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1lOO; + wire_nl0Oii11O_dataout <= wire_nl0Oii1Ol_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1O1i; + wire_nl0Oii1i_dataout <= nlliiil1O AND niOO1Oi1i; + wire_nl0Oii1ii_dataout <= wire_nl0Oii1li_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1O0l; + wire_nl0Oii1il_dataout <= wire_nl0Oii1iO_dataout WHEN niOiiiOli = '1' ELSE nl0Oi1O0O; + wire_nl0Oii1iO_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1O0O; + wire_nl0Oii1l_dataout <= nlliiil0i AND niOO1Oi1i; + wire_nl0Oii1li_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1O0l; + wire_nl0Oii1ll_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1O0i; + wire_nl0Oii1lO_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1O1O; + wire_nl0Oii1O_dataout <= nlliiil0l AND niOO1Oi1i; + wire_nl0Oii1Oi_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1O1l; + wire_nl0Oii1Ol_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1O1i; + wire_nl0Oii1OO_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi1lOO; + wire_nl0Oiii0i_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1ill; + wire_nl0Oiii0l_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1ili; + wire_nl0Oiii0O_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1iiO; + wire_nl0Oiii1i_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1iOl; + wire_nl0Oiii1l_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1iOi; + wire_nl0Oiii1O_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1ilO; + wire_nl0Oiiiii_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1iil; + wire_nl0Oiiiil_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1iii; + wire_nl0OiiiiO_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1i0O; + wire_nl0Oiiili_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0O0llOi; + wire_nl0OiiiOi_dataout <= wire_nl0OiiOll_dataout AND NOT(niOiiiOOl); + wire_nl0OiiiOl_dataout <= wire_nl0OiiOlO_dataout AND NOT(niOiiiOOl); + wire_nl0OiiiOO_dataout <= wire_nl0OiiOOi_dataout AND NOT(niOiiiOOl); + wire_nl0Oiil0i_dataout <= wire_nl0Oil11l_dataout AND NOT(niOiiiOOl); + wire_nl0Oiil0l_dataout <= wire_nl0Oil11O_dataout AND NOT(niOiiiOOl); + wire_nl0Oiil0O_dataout <= wire_nl0Oil10i_dataout AND NOT(niOiiiOOl); + wire_nl0Oiil1i_dataout <= wire_nl0OiiOOl_dataout AND NOT(niOiiiOOl); + wire_nl0Oiil1l_dataout <= wire_nl0OiiOOO_dataout AND NOT(niOiiiOOl); + wire_nl0Oiil1O_dataout <= wire_nl0Oil11i_dataout AND NOT(niOiiiOOl); + wire_nl0Oiilii_dataout <= wire_nl0Oil10l_dataout AND NOT(niOiiiOOl); + wire_nl0Oiilil_dataout <= wire_nl0Oil10O_dataout AND NOT(niOiiiOOl); + wire_nl0OiiliO_dataout <= wire_nl0Oil1ii_dataout AND NOT(niOiiiOOl); + wire_nl0Oiilli_dataout <= wire_nl0Oil1il_dataout AND NOT(niOiiiOOl); + wire_nl0Oiilll_dataout <= wire_nl0Oil1iO_dataout AND NOT(niOiiiOOl); + wire_nl0OiillO_dataout <= wire_nl0Oil1li_dataout AND NOT(niOiiiOOl); + wire_nl0OiilOi_dataout <= wire_nl0Oil1ll_dataout AND NOT(niOiiiOOl); + wire_nl0OiilOl_dataout <= wire_nl0Oil1lO_dataout AND NOT(niOiiiOOl); + wire_nl0OiilOO_dataout <= wire_nl0Oil1Oi_dataout AND NOT(niOiiiOOl); + wire_nl0OiiO0i_dataout <= wire_nl0Oil01l_dataout AND NOT(niOiiiOOl); + wire_nl0OiiO0l_dataout <= wire_nl0Oil01O_dataout AND NOT(niOiiiOOl); + wire_nl0OiiO0O_dataout <= wire_nl0Oil00i_dataout AND NOT(niOiiiOOl); + wire_nl0OiiO1i_dataout <= wire_nl0Oil1Ol_dataout AND NOT(niOiiiOOl); + wire_nl0OiiO1l_dataout <= wire_nl0Oil1OO_dataout AND NOT(niOiiiOOl); + wire_nl0OiiO1O_dataout <= wire_nl0Oil01i_dataout AND NOT(niOiiiOOl); + wire_nl0OiiOii_dataout <= wire_nl0Oil00l_dataout AND NOT(niOiiiOOl); + wire_nl0OiiOil_dataout <= wire_nl0Oil00O_dataout AND NOT(niOiiiOOl); + wire_nl0OiiOiO_dataout <= wire_nl0Oil0ii_dataout AND NOT(niOiiiOOl); + wire_nl0OiiOli_dataout <= wire_nl0Oil0il_dataout AND NOT(niOiiiOOl); + wire_nl0OiiOll_dataout <= wire_nl0Oill0O_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1Oii; + wire_nl0OiiOlO_dataout <= wire_nl0Oill0l_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1Oil; + wire_nl0OiiOOi_dataout <= wire_nl0Oill0i_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1OiO; + wire_nl0OiiOOl_dataout <= wire_nl0Oill1O_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1Oli; + wire_nl0OiiOOO_dataout <= wire_nl0Oill1l_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1Oll; + wire_nl0Oil00i_dataout <= wire_nl0Oil0Oi_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01OO; + wire_nl0Oil00l_dataout <= wire_nl0Oil0lO_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi001i; + wire_nl0Oil00O_dataout <= wire_nl0Oil0ll_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi001l; + wire_nl0Oil01i_dataout <= wire_nl0Oili1i_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01lO; + wire_nl0Oil01l_dataout <= wire_nl0Oil0OO_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01Oi; + wire_nl0Oil01O_dataout <= wire_nl0Oil0Ol_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01Ol; + wire_nl0Oil0ii_dataout <= wire_nl0Oil0li_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi001O; + wire_nl0Oil0il_dataout <= wire_nl0Oil0iO_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi000i; + wire_nl0Oil0iO_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi000i; + wire_nl0Oil0li_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi001O; + wire_nl0Oil0ll_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi001l; + wire_nl0Oil0lO_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi001i; + wire_nl0Oil0Oi_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi01OO; + wire_nl0Oil0Ol_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi01Ol; + wire_nl0Oil0OO_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi01Oi; + wire_nl0Oil10i_dataout <= wire_nl0OiliOi_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1OOO; + wire_nl0Oil10l_dataout <= wire_nl0OililO_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi011i; + wire_nl0Oil10O_dataout <= wire_nl0Oilill_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi011l; + wire_nl0Oil11i_dataout <= wire_nl0Oill1i_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1OlO; + wire_nl0Oil11l_dataout <= wire_nl0OiliOO_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1OOi; + wire_nl0Oil11O_dataout <= wire_nl0OiliOl_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi1OOl; + wire_nl0Oil1ii_dataout <= wire_nl0Oilili_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi011O; + wire_nl0Oil1il_dataout <= wire_nl0OiliiO_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi010i; + wire_nl0Oil1iO_dataout <= wire_nl0Oiliil_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi010l; + wire_nl0Oil1li_dataout <= wire_nl0Oiliii_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi010O; + wire_nl0Oil1ll_dataout <= wire_nl0Oili0O_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01ii; + wire_nl0Oil1lO_dataout <= wire_nl0Oili0l_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01il; + wire_nl0Oil1Oi_dataout <= wire_nl0Oili0i_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01iO; + wire_nl0Oil1Ol_dataout <= wire_nl0Oili1O_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01li; + wire_nl0Oil1OO_dataout <= wire_nl0Oili1l_dataout WHEN niOiiiOOi = '1' ELSE nl0Oi01ll; + wire_nl0Oili0i_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi01iO; + wire_nl0Oili0l_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi01il; + wire_nl0Oili0O_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi01ii; + wire_nl0Oili1i_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0Oi01lO; + wire_nl0Oili1l_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi01ll; + wire_nl0Oili1O_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi01li; + wire_nl0Oiliii_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi010O; + wire_nl0Oiliil_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi010l; + wire_nl0OiliiO_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0Oi010i; + wire_nl0Oilili_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi011O; + wire_nl0Oilill_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi011l; + wire_nl0OililO_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi011i; + wire_nl0OiliOi_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1OOO; + wire_nl0OiliOl_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1OOl; + wire_nl0OiliOO_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1OOi; + wire_nl0Oill0i_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1OiO; + wire_nl0Oill0l_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1Oil; + wire_nl0Oill0O_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1Oii; + wire_nl0Oill1i_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1OlO; + wire_nl0Oill1l_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0Oi1Oll; + wire_nl0Oill1O_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0Oi1Oli; + wire_nl0OiO00i_dataout <= wire_nl0OiOiOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiO00l_dataout <= wire_nl0OiO00O_dataout OR (wire_w_lg_niOili1OO45976w(0) AND wire_nli0OilOi_dataout); + wire_nl0OiO00O_dataout <= nl0OiO0li AND NOT((wire_nl0l1O01O_dataout AND niOiil11i)); + wire_nl0OiO01i_dataout <= wire_nl0OiOi1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiO01l_dataout <= wire_nl0OiOi0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiO01O_dataout <= wire_nl0OiOili_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiO0lO_dataout <= wire_nl0OiO0Oi_dataout OR ((wire_w_lg_niOili1OO45976w(0) AND nl0OiOl0O) AND wire_nli0OilOO_dataout); + wire_nl0OiO0Oi_dataout <= nl0OiO1il AND NOT((wire_nl0l1O01l_dataout AND niOiil11i)); + wire_nl0OiO1Ol_dataout <= wire_nl0OiO00l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiO1OO_dataout <= wire_nl0OiO0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiOi0O_dataout <= wire_nl0OiOiii_dataout OR (wire_w_lg_niOili1OO45976w(0) AND wire_nli0OiOiO_dataout); + wire_nl0OiOi1l_dataout <= wire_nl0OiOi1O_dataout OR (wire_w_lg_niOili1OO45976w(0) AND wire_nli0OiO0i_dataout); + wire_nl0OiOi1O_dataout <= nl0OiO1iO AND NOT((wire_nl0l1O01i_dataout AND niOiil11i)); + wire_nl0OiOii_dataout <= wire_nl0O0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOiii_dataout <= nl0OiO1li AND NOT((wire_nl0l1O1OO_dataout AND niOiil11i)); + wire_nl0OiOil_dataout <= wire_nl0O0lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOili_dataout <= wire_nl0OiOill_dataout OR (wire_w_lg_niOili1OO45976w(0) AND wire_nli0OiOlO_dataout); + wire_nl0OiOill_dataout <= nl0OiO1ll AND NOT((wire_nl0l1O1Ol_dataout AND niOiil11i)); + wire_nl0OiOiO_dataout <= wire_nl0O0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOiOl_dataout <= wire_nl0OiOiOO_dataout AND NOT((niOili1OO OR wire_nlill0Oll_w_lg_nl0OiOlii46170w(0))); + wire_nl0OiOiOO_dataout <= wire_nl0OiOl1i_dataout OR wire_nli0Ol11l_dataout; + wire_nl0OiOl1i_dataout <= nl0OiO1lO AND NOT((wire_nl0l1O1ll_dataout AND niOiil11i)); + wire_nl0OiOli_dataout <= wire_nl0O0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOliO_dataout <= wire_nl0OiOlOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiOll_dataout <= wire_nl0O0O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOlli_dataout <= wire_nl0OiOlOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiOlll_dataout <= wire_nl0OiOO1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiOllO_dataout <= wire_nl0OiOO1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiOlO_dataout <= wire_nl0O0O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOlOi_dataout <= wire_nl0OiOO1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OiOlOl_dataout <= wire_nl0l1O1iO_dataout WHEN niOiil11O = '1' ELSE (nl0OiO1Oi AND wire_nl1000i_w_lg_niOOOOiO8394w(0)); + wire_nl0OiOlOO_dataout <= wire_nl0OiOO0i_dataout WHEN niOiil11O = '1' ELSE nl0OiOl0i; + wire_nl0OiOO0i_dataout <= wire_nl0l1O1ii_dataout AND niOiil11l; + wire_nl0OiOO0l_dataout <= wire_nl0l1O10O_dataout AND niOiil11l; + wire_nl0OiOO1i_dataout <= wire_nl0OiOO0l_dataout WHEN niOiil11O = '1' ELSE nl0OiOl0l; + wire_nl0OiOO1l_dataout <= wire_nl0l1O10i_dataout WHEN niOiil11O = '1' ELSE nl0OiOl0O; + wire_nl0OiOO1O_dataout <= wire_nl0l1O11O_dataout WHEN niOiil11O = '1' ELSE nl0OiOlii; + wire_nl0OiOOi_dataout <= wire_nl0O0O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOOl_dataout <= wire_nl0O0O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OiOOO_dataout <= wire_nl0O0O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol00i_dataout <= wire_nl1000i_w_lg_nl0OiO0O6419w(0) AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol01i_dataout <= wire_nl0Oi1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol01l_dataout <= wire_nl0Oi1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol01O_dataout <= wire_nl0Oi1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol0OlO_dataout <= niOiil10l AND NOT(wire_niO01Oil_dataout); + wire_nl0Ol0OOi_dataout <= niOiil10O AND NOT(wire_niO01Oil_dataout); + wire_nl0Ol0OOl_dataout <= wire_nl0Oll1lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Ol0OOO_dataout <= wire_nl0Oll1Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Ol10i_dataout <= wire_nl0O0Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol10l_dataout <= wire_nl0O0Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol10O_dataout <= wire_nl0O0OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol11i_dataout <= wire_nl0O0Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol11l_dataout <= wire_nl0O0Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol11O_dataout <= wire_nl0O0OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1ii_dataout <= wire_nl0O0OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1il_dataout <= wire_nl0O0OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1iO_dataout <= wire_nl0O0OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1li_dataout <= wire_nl0Oi11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1ll_dataout <= wire_nl0Oi11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1lO_dataout <= wire_nl0Oi11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1Oi_dataout <= wire_nl0Oi10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1Ol_dataout <= wire_nl0Oi10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Ol1OO_dataout <= wire_nl0Oi10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0Oli00i_dataout <= wire_nl0Olli1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli00l_dataout <= wire_nl0Olli1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli00O_dataout <= wire_nl0Olli0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli01i_dataout <= wire_nl0Oll0Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli01l_dataout <= wire_nl0Oll0OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli01O_dataout <= wire_nl0Olli1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0ii_dataout <= wire_nl0Olli0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0il_dataout <= wire_nl0Olli0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0iO_dataout <= wire_nl0Olliii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0li_dataout <= wire_nl0Olliil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0ll_dataout <= wire_nl0OlliiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0lO_dataout <= wire_nl0Ollili_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0Oi_dataout <= wire_nl0Ollill_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0Ol_dataout <= wire_nl0OllilO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli0OO_dataout <= wire_nl0OlliOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli10i_dataout <= wire_nl0Oll01l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli10l_dataout <= wire_nl0Oll01O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli10O_dataout <= wire_nl0Oll00i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli11i_dataout <= wire_nl0Oll1Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli11l_dataout <= wire_nl0Oll1OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli11O_dataout <= wire_nl0Oll01i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1ii_dataout <= wire_nl0Oll00l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1il_dataout <= wire_nl0Oll00O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1iO_dataout <= wire_nl0Oll0ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1li_dataout <= wire_nl0Oll0il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1ll_dataout <= wire_nl0Oll0iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1lO_dataout <= wire_nl0Oll0li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1Oi_dataout <= wire_nl0Oll0ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1Ol_dataout <= wire_nl0Oll0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oli1OO_dataout <= wire_nl0Oll0Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olii0i_dataout <= wire_nl0OlO10l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olii0l_dataout <= wire_nl0OlO10O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olii0O_dataout <= wire_nl0OlO1ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olii1i_dataout <= wire_nl0OlO11l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olii1l_dataout <= wire_nl0OlO11O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olii1O_dataout <= wire_nl0OlO10i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oliiii_dataout <= wire_nl0OlO1il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oliiil_dataout <= wire_nl0OlO1iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliiiO_dataout <= wire_nl0OlO1li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oliili_dataout <= wire_nl0OlO1ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oliill_dataout <= wire_nl0OlO1lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliilO_dataout <= wire_nl0OlO1Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliiOi_dataout <= wire_nl0OlO0Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliiOl_dataout <= wire_nl0OlO0OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliiOO_dataout <= wire_nl0OlOi1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olil0i_dataout <= wire_nl0OlOi0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olil0l_dataout <= wire_nl0OlOi0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olil0O_dataout <= wire_nl0OlOiii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olil1i_dataout <= wire_nl0OlOi1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olil1l_dataout <= wire_nl0OlOi1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olil1O_dataout <= wire_nl0OlOi0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olilii_dataout <= wire_nl0OlOiil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olilil_dataout <= wire_nl0OlOiiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliliO_dataout <= wire_nl0OlOili_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olill_dataout <= wire_nl0Ollil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Olilli_dataout <= wire_nl0OlOill_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Olilll_dataout <= wire_nl0OlOilO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OlillO_dataout <= wire_nl0OlOiOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OlilO_dataout <= wire_nl0OlliO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OlilOi_dataout <= wire_nl0OlOiOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OlilOl_dataout <= wire_nl0OlOiOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OlilOO_dataout <= wire_nl0OlOl1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliO0i_dataout <= wire_nl0OlOl0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliO0l_dataout <= wire_nl0OlOl0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliO0O_dataout <= wire_nl0OlOlii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliO1i_dataout <= wire_nl0OlOl1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliO1l_dataout <= wire_nl0OlOl1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliO1O_dataout <= wire_nl0OlOl0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOi_dataout <= wire_nl0Ollli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OliOii_dataout <= wire_nl0OlOlil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOil_dataout <= wire_nl0OlOliO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOiO_dataout <= wire_nl0OlOlli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOl_dataout <= wire_nl0Ollll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OliOli_dataout <= wire_nl0OlOlll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOll_dataout <= wire_nl0OlOllO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOlO_dataout <= wire_nl0OlOlOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOO_dataout <= wire_nl0OlllO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OliOOi_dataout <= wire_nl0OlOlOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOOl_dataout <= wire_nl0OlOlOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OliOOO_dataout <= wire_nl0OO100O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll00i_dataout <= wire_nl0OllOil_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1O0l; + wire_nl0Oll00l_dataout <= wire_nl0OllOii_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1O0O; + wire_nl0Oll00O_dataout <= wire_nl0OllO0O_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1Oii; + wire_nl0Oll01i_dataout <= wire_nl0OllOll_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1O1l; + wire_nl0Oll01l_dataout <= wire_nl0OllOli_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1O1O; + wire_nl0Oll01O_dataout <= wire_nl0OllOiO_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1O0i; + wire_nl0Oll0i_dataout <= wire_nl0OlO1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Oll0ii_dataout <= wire_nl0OllO0l_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1Oil; + wire_nl0Oll0il_dataout <= wire_nl0OllO0i_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1OiO; + wire_nl0Oll0iO_dataout <= wire_nl0OllO1O_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1Oli; + wire_nl0Oll0l_dataout <= wire_nl0OlO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Oll0li_dataout <= wire_nl0OllO1l_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1Oll; + wire_nl0Oll0ll_dataout <= wire_nl0OllO1i_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1OlO; + wire_nl0Oll0lO_dataout <= wire_nl0OlllOO_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1OOi; + wire_nl0Oll0O_dataout <= wire_nl0OlO1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Oll0Oi_dataout <= wire_nl0OlllOl_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1OOl; + wire_nl0Oll0Ol_dataout <= wire_nl0OlllOi_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1OOO; + wire_nl0Oll0OO_dataout <= wire_nl0OllllO_dataout WHEN niOiil1ii = '1' ELSE nl0Ol011i; + wire_nl0Oll10i_dataout <= wire_nl0OO10li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll10l_dataout <= wire_nl0OO10ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll10O_dataout <= wire_nl0OO10lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll11i_dataout <= wire_nl0OO10ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll11l_dataout <= wire_nl0OO10il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll11O_dataout <= wire_nl0OO10iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll1i_dataout <= wire_nl0OllOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Oll1ii_dataout <= wire_nl0OO10Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll1il_dataout <= wire_nl0OO10Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll1iO_dataout <= wire_nl0OO10OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll1l_dataout <= wire_nl0OllOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Oll1li_dataout <= wire_nl0OO1i1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll1ll_dataout <= wire_nl0OO1i1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0Oll1lO_dataout <= wire_nl0OllOOO_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1lOi; + wire_nl0Oll1O_dataout <= wire_nl0OllOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Oll1Oi_dataout <= wire_nl0OllOOl_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1lOl; + wire_nl0Oll1Ol_dataout <= wire_nl0OllOOi_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1lOO; + wire_nl0Oll1OO_dataout <= wire_nl0OllOlO_dataout WHEN niOiil1ii = '1' ELSE nl0Ol1O1i; + wire_nl0Olli0i_dataout <= wire_nl0Olllil_dataout WHEN niOiil1ii = '1' ELSE nl0Ol010l; + wire_nl0Olli0l_dataout <= wire_nl0Olllii_dataout WHEN niOiil1ii = '1' ELSE nl0Ol010O; + wire_nl0Olli0O_dataout <= wire_nl0Olll0O_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01ii; + wire_nl0Olli1i_dataout <= wire_nl0Olllll_dataout WHEN niOiil1ii = '1' ELSE nl0Ol011l; + wire_nl0Olli1l_dataout <= wire_nl0Olllli_dataout WHEN niOiil1ii = '1' ELSE nl0Ol011O; + wire_nl0Olli1O_dataout <= wire_nl0OllliO_dataout WHEN niOiil1ii = '1' ELSE nl0Ol010i; + wire_nl0Ollii_dataout <= wire_nl0OlO0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0Olliii_dataout <= wire_nl0Olll0l_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01il; + wire_nl0Olliil_dataout <= wire_nl0Olll0i_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01iO; + wire_nl0OlliiO_dataout <= wire_nl0Olll1O_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01li; + wire_nl0Ollil_dataout <= nl0OO11l WHEN niOO1Oi1O = '1' ELSE nl0OlO0O; + wire_nl0Ollili_dataout <= wire_nl0Olll1l_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01ll; + wire_nl0Ollill_dataout <= wire_nl0Olll1i_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01lO; + wire_nl0OllilO_dataout <= wire_nl0OlliOO_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01Oi; + wire_nl0OlliO_dataout <= nl0OO11O WHEN niOO1Oi1O = '1' ELSE nl0Ol0Ol; + wire_nl0OlliOi_dataout <= wire_nl0OlliOl_dataout WHEN niOiil1ii = '1' ELSE nl0Ol01Ol; + wire_nl0OlliOl_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01Ol; + wire_nl0OlliOO_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01Oi; + wire_nl0Olll0i_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01iO; + wire_nl0Olll0l_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01il; + wire_nl0Olll0O_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01ii; + wire_nl0Olll1i_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01lO; + wire_nl0Olll1l_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01ll; + wire_nl0Olll1O_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol01li; + wire_nl0Ollli_dataout <= nl0OO10i WHEN niOO1Oi1O = '1' ELSE nl0Ol0OO; + wire_nl0Olllii_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol010O; + wire_nl0Olllil_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol010l; + wire_nl0OllliO_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol010i; + wire_nl0Ollll_dataout <= nl0OO10l WHEN niOO1Oi1O = '1' ELSE nl0Oli1i; + wire_nl0Olllli_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol011O; + wire_nl0Olllll_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol011l; + wire_nl0OllllO_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol011i; + wire_nl0OlllO_dataout <= nl0OO10O WHEN niOO1Oi1O = '1' ELSE nl0Oli1l; + wire_nl0OlllOi_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol1OOO; + wire_nl0OlllOl_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol1OOl; + wire_nl0OlllOO_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1OOi; + wire_nl0OllO0i_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1OiO; + wire_nl0OllO0l_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1Oil; + wire_nl0OllO0O_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1Oii; + wire_nl0OllO1i_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1OlO; + wire_nl0OllO1l_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1Oll; + wire_nl0OllO1O_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1Oli; + wire_nl0OllOi_dataout <= nl0OO1ii WHEN niOO1Oi1O = '1' ELSE nl0Oli1O; + wire_nl0OllOii_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol1O0O; + wire_nl0OllOil_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1O0l; + wire_nl0OllOiO_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1O0i; + wire_nl0OllOl_dataout <= nl0OO1il WHEN niOO1Oi1O = '1' ELSE nl0Oli0i; + wire_nl0OllOli_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1O1O; + wire_nl0OllOll_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1O1l; + wire_nl0OllOlO_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1O1i; + wire_nl0OllOO_dataout <= nl0OO1iO WHEN niOO1Oi1O = '1' ELSE nl0Oli0l; + wire_nl0OllOOi_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1lOO; + wire_nl0OllOOl_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1lOl; + wire_nl0OllOOO_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol1lOi; + wire_nl0OlO00i_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol00iO; + wire_nl0OlO00l_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol00li; + wire_nl0OlO00O_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol00ll; + wire_nl0OlO01i_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol000O; + wire_nl0OlO01l_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol00ii; + wire_nl0OlO01O_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol00il; + wire_nl0OlO0i_dataout <= nl0OO1Oi WHEN niOO1Oi1O = '1' ELSE nl0OliiO; + wire_nl0OlO0ii_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol01OO; + wire_nl0OlO0il_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol001i; + wire_nl0OlO0iO_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol001l; + wire_nl0OlO0li_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol001O; + wire_nl0OlO0Ol_dataout <= wire_nl0OO101l_dataout WHEN niOiil1il = '1' ELSE nl0Ol00lO; + wire_nl0OlO0OO_dataout <= wire_nl0OO101i_dataout WHEN niOiil1il = '1' ELSE nl0Ol00Oi; + wire_nl0OlO10i_dataout <= wire_nl0OlO0iO_dataout WHEN niOiil1li = '1' ELSE nl0Ol001l; + wire_nl0OlO10l_dataout <= wire_nl0OlO0li_dataout WHEN niOiil1li = '1' ELSE nl0Ol001O; + wire_nl0OlO10O_dataout <= wire_nl0OlO1Ol_dataout WHEN niOiil1li = '1' ELSE nl0Ol000i; + wire_nl0OlO11l_dataout <= wire_nl0OlO0ii_dataout WHEN niOiil1li = '1' ELSE nl0Ol01OO; + wire_nl0OlO11O_dataout <= wire_nl0OlO0il_dataout WHEN niOiil1li = '1' ELSE nl0Ol001i; + wire_nl0OlO1i_dataout <= nl0OO1li WHEN niOO1Oi1O = '1' ELSE nl0Oli0O; + wire_nl0OlO1ii_dataout <= wire_nl0OlO1OO_dataout WHEN niOiil1li = '1' ELSE nl0Ol000l; + wire_nl0OlO1il_dataout <= wire_nl0OlO01i_dataout WHEN niOiil1li = '1' ELSE nl0Ol000O; + wire_nl0OlO1iO_dataout <= wire_nl0OlO01l_dataout WHEN niOiil1li = '1' ELSE nl0Ol00ii; + wire_nl0OlO1l_dataout <= nl0OO1ll WHEN niOO1Oi1O = '1' ELSE nl0Oliii; + wire_nl0OlO1li_dataout <= wire_nl0OlO01O_dataout WHEN niOiil1li = '1' ELSE nl0Ol00il; + wire_nl0OlO1ll_dataout <= wire_nl0OlO00i_dataout WHEN niOiil1li = '1' ELSE nl0Ol00iO; + wire_nl0OlO1lO_dataout <= wire_nl0OlO00l_dataout WHEN niOiil1li = '1' ELSE nl0Ol00li; + wire_nl0OlO1O_dataout <= nl0OO1lO WHEN niOO1Oi1O = '1' ELSE nl0Oliil; + wire_nl0OlO1Oi_dataout <= wire_nl0OlO00O_dataout WHEN niOiil1li = '1' ELSE nl0Ol00ll; + wire_nl0OlO1Ol_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol000i; + wire_nl0OlO1OO_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol000l; + wire_nl0OlOi0i_dataout <= wire_nl0OO11lO_dataout WHEN niOiil1il = '1' ELSE nl0Ol0i1l; + wire_nl0OlOi0l_dataout <= wire_nl0OO11ll_dataout WHEN niOiil1il = '1' ELSE nl0Ol0i1O; + wire_nl0OlOi0O_dataout <= wire_nl0OO11li_dataout WHEN niOiil1il = '1' ELSE nl0Ol0i0i; + wire_nl0OlOi1i_dataout <= wire_nl0OO11OO_dataout WHEN niOiil1il = '1' ELSE nl0Ol00Ol; + wire_nl0OlOi1l_dataout <= wire_nl0OO11Ol_dataout WHEN niOiil1il = '1' ELSE nl0Ol00OO; + wire_nl0OlOi1O_dataout <= wire_nl0OO11Oi_dataout WHEN niOiil1il = '1' ELSE nl0Ol0i1i; + wire_nl0OlOiii_dataout <= wire_nl0OO11iO_dataout WHEN niOiil1il = '1' ELSE nl0Ol0i0l; + wire_nl0OlOiil_dataout <= wire_nl0OO11il_dataout WHEN niOiil1il = '1' ELSE nl0Ol0i0O; + wire_nl0OlOiiO_dataout <= wire_nl0OO11ii_dataout WHEN niOiil1il = '1' ELSE nl0Ol0iii; + wire_nl0OlOil_dataout <= nl0OlOll AND NOT(wire_niO01O0O_dataout); + wire_nl0OlOili_dataout <= wire_nl0OO110O_dataout WHEN niOiil1il = '1' ELSE nl0Ol0iil; + wire_nl0OlOill_dataout <= wire_nl0OO110l_dataout WHEN niOiil1il = '1' ELSE nl0Ol0iiO; + wire_nl0OlOilO_dataout <= wire_nl0OO110i_dataout WHEN niOiil1il = '1' ELSE nl0Ol0ili; + wire_nl0OlOiOi_dataout <= wire_nl0OO111O_dataout WHEN niOiil1il = '1' ELSE nl0Ol0ill; + wire_nl0OlOiOl_dataout <= wire_nl0OO111l_dataout WHEN niOiil1il = '1' ELSE nl0Ol0ilO; + wire_nl0OlOiOO_dataout <= wire_nl0OO111i_dataout WHEN niOiil1il = '1' ELSE nl0Ol0iOi; + wire_nl0OlOl0i_dataout <= wire_nl0OlOOlO_dataout WHEN niOiil1il = '1' ELSE nl0Ol0l1l; + wire_nl0OlOl0l_dataout <= wire_nl0OlOOll_dataout WHEN niOiil1il = '1' ELSE nl0Ol0l1O; + wire_nl0OlOl0O_dataout <= wire_nl0OlOOli_dataout WHEN niOiil1il = '1' ELSE nl0Ol0l0i; + wire_nl0OlOl1i_dataout <= wire_nl0OlOOOO_dataout WHEN niOiil1il = '1' ELSE nl0Ol0iOl; + wire_nl0OlOl1l_dataout <= wire_nl0OlOOOl_dataout WHEN niOiil1il = '1' ELSE nl0Ol0iOO; + wire_nl0OlOl1O_dataout <= wire_nl0OlOOOi_dataout WHEN niOiil1il = '1' ELSE nl0Ol0l1i; + wire_nl0OlOli_dataout <= nl0Olili AND NOT(wire_niO01O0O_dataout); + wire_nl0OlOlii_dataout <= wire_nl0OlOOiO_dataout WHEN niOiil1il = '1' ELSE nl0Ol0l0l; + wire_nl0OlOlil_dataout <= wire_nl0OlOOil_dataout WHEN niOiil1il = '1' ELSE nl0Ol0l0O; + wire_nl0OlOliO_dataout <= wire_nl0OlOOii_dataout WHEN niOiil1il = '1' ELSE nl0Ol0lii; + wire_nl0OlOlli_dataout <= wire_nl0OlOO0O_dataout WHEN niOiil1il = '1' ELSE nl0Ol0lil; + wire_nl0OlOlll_dataout <= wire_nl0OlOO0l_dataout WHEN niOiil1il = '1' ELSE nl0Ol0liO; + wire_nl0OlOllO_dataout <= wire_nl0OlOO0i_dataout WHEN niOiil1il = '1' ELSE nl0Ol0lli; + wire_nl0OlOlO_dataout <= nl0OlOOl AND NOT(wire_niO01l0O_dataout); + wire_nl0OlOlOi_dataout <= wire_nl0OlOO1O_dataout WHEN niOiil1il = '1' ELSE nl0Ol0lll; + wire_nl0OlOlOl_dataout <= wire_nl0OlOO1l_dataout WHEN niOiil1il = '1' ELSE nl0Ol0llO; + wire_nl0OlOlOO_dataout <= wire_nl0OlOO1i_dataout WHEN niOiil1il = '1' ELSE nl0Ol0lOi; + wire_nl0OlOO0i_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0lli; + wire_nl0OlOO0l_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0liO; + wire_nl0OlOO0O_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0lil; + wire_nl0OlOO1i_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0lOi; + wire_nl0OlOO1l_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0llO; + wire_nl0OlOO1O_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0lll; + wire_nl0OlOOii_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0lii; + wire_nl0OlOOil_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0Ol0l0O; + wire_nl0OlOOiO_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0l0l; + wire_nl0OlOOli_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0l0i; + wire_nl0OlOOll_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0l1O; + wire_nl0OlOOlO_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0l1l; + wire_nl0OlOOO_dataout <= nl0OlOOi AND NOT(wire_niO01l0O_dataout); + wire_nl0OlOOOi_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0l1i; + wire_nl0OlOOOl_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0iOO; + wire_nl0OlOOOO_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0iOl; + wire_nl0OO000i_dataout <= wire_nl0OO0iiO_dataout WHEN niOiil1ll = '1' ELSE nl0OO1iOO; + wire_nl0OO000l_dataout <= wire_nl0OO0ili_dataout WHEN niOiil1ll = '1' ELSE nl0OO1l1i; + wire_nl0OO000O_dataout <= wire_nl0OO0ill_dataout WHEN niOiil1ll = '1' ELSE nl0OO1l1l; + wire_nl0OO001i_dataout <= wire_nl0OO0lil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO001l_dataout <= wire_nl0OO0liO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO001O_dataout <= wire_nl0OO0iil_dataout WHEN niOiil1ll = '1' ELSE nl0Ol0Oll; + wire_nl0OO00i_dataout <= wire_nl0OOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO00ii_dataout <= wire_nl0OO00OO_dataout WHEN niOiil1ll = '1' ELSE nl0OO1l1O; + wire_nl0OO00il_dataout <= wire_nl0OO0i1i_dataout WHEN niOiil1ll = '1' ELSE nl0OO1l0i; + wire_nl0OO00iO_dataout <= wire_nl0OO0i1l_dataout WHEN niOiil1ll = '1' ELSE nl0OO1l0l; + wire_nl0OO00l_dataout <= wire_nl0OOi0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO00li_dataout <= wire_nl0OO0i1O_dataout WHEN niOiil1ll = '1' ELSE nl0OO1l0O; + wire_nl0OO00ll_dataout <= wire_nl0OO0i0i_dataout WHEN niOiil1ll = '1' ELSE nl0OO1lii; + wire_nl0OO00lO_dataout <= wire_nl0OO0i0l_dataout WHEN niOiil1ll = '1' ELSE nl0OO1lil; + wire_nl0OO00O_dataout <= wire_nl0OOi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO00Oi_dataout <= wire_nl0OO0i0O_dataout WHEN niOiil1ll = '1' ELSE nl0OO1liO; + wire_nl0OO00Ol_dataout <= wire_nl0OO0iii_dataout WHEN niOiil1ll = '1' ELSE nl0OO1lli; + wire_nl0OO00OO_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1l1O; + wire_nl0OO010i_dataout <= wire_nl0OO00Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO010l_dataout <= wire_nl0OO00Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO010O_dataout <= wire_nl0OO0iOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO011i_dataout <= wire_nl0OO00li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO011l_dataout <= wire_nl0OO00ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO011O_dataout <= wire_nl0OO00lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01i_dataout <= wire_nl0OO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO01ii_dataout <= wire_nl0OO0iOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01il_dataout <= wire_nl0OO0iOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01iO_dataout <= wire_nl0OO0l1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01l_dataout <= wire_nl0OOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO01li_dataout <= wire_nl0OO0l1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01ll_dataout <= wire_nl0OO0l1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01lO_dataout <= wire_nl0OO0l0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01O_dataout <= wire_nl0OOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO01Oi_dataout <= wire_nl0OO0l0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01Ol_dataout <= wire_nl0OO0l0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO01OO_dataout <= wire_nl0OO0lii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO0i0i_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1lii; + wire_nl0OO0i0l_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1lil; + wire_nl0OO0i0O_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1liO; + wire_nl0OO0i1i_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1l0i; + wire_nl0OO0i1l_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1l0l; + wire_nl0OO0i1O_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1l0O; + wire_nl0OO0ii_dataout <= wire_nl0OOi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO0iii_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0OO1lli; + wire_nl0OO0iil_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0Oll; + wire_nl0OO0iiO_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0OO1iOO; + wire_nl0OO0il_dataout <= wire_nl0OOiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO0ili_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0OO1l1i; + wire_nl0OO0ill_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0OO1l1l; + wire_nl0OO0iO_dataout <= wire_nl0OOiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO0iOi_dataout <= wire_nl0OO0O1O_dataout WHEN niOiil1ll = '1' ELSE nl0OO1lll; + wire_nl0OO0iOl_dataout <= wire_nl0OO0O0i_dataout WHEN niOiil1ll = '1' ELSE nl0OO1llO; + wire_nl0OO0iOO_dataout <= wire_nl0OO0O0l_dataout WHEN niOiil1ll = '1' ELSE nl0OO1lOi; + wire_nl0OO0l0i_dataout <= wire_nl0OO0llO_dataout WHEN niOiil1ll = '1' ELSE nl0OO1O1l; + wire_nl0OO0l0l_dataout <= wire_nl0OO0lOi_dataout WHEN niOiil1ll = '1' ELSE nl0OO1O1O; + wire_nl0OO0l0O_dataout <= wire_nl0OO0lOl_dataout WHEN niOiil1ll = '1' ELSE nl0OO1O0i; + wire_nl0OO0l1i_dataout <= wire_nl0OO0O0O_dataout WHEN niOiil1ll = '1' ELSE nl0OO1lOl; + wire_nl0OO0l1l_dataout <= wire_nl0OO0lli_dataout WHEN niOiil1ll = '1' ELSE nl0OO1lOO; + wire_nl0OO0l1O_dataout <= wire_nl0OO0lll_dataout WHEN niOiil1ll = '1' ELSE nl0OO1O1i; + wire_nl0OO0li_dataout <= wire_nl0OOiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO0lii_dataout <= wire_nl0OO0lOO_dataout WHEN niOiil1ll = '1' ELSE nl0OO1O0l; + wire_nl0OO0lil_dataout <= wire_nl0OO0O1i_dataout WHEN niOiil1ll = '1' ELSE nl0OO1O0O; + wire_nl0OO0liO_dataout <= wire_nl0OO0O1l_dataout WHEN niOiil1ll = '1' ELSE nl0OO1Oii; + wire_nl0OO0ll_dataout <= wire_nl0OOili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO0lli_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1lOO; + wire_nl0OO0lll_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1O1i; + wire_nl0OO0llO_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1O1l; + wire_nl0OO0lO_dataout <= wire_nl1000i_w_lg_nl0OlOOl6384w(0) WHEN (wire_w_lg_niOO1Oi0l6383w(0) AND wire_w_lg_niOO1Oi0i6385w(0)) = '1' ELSE nl0OlOOl; + wire_nl0OO0lOi_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1O1O; + wire_nl0OO0lOl_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1O0i; + wire_nl0OO0lOO_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1O0l; + wire_nl0OO0O0i_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0OO1llO; + wire_nl0OO0O0l_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0OO1lOi; + wire_nl0OO0O0O_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0OO1lOl; + wire_nl0OO0O1i_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1O0O; + wire_nl0OO0O1l_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0OO1Oii; + wire_nl0OO0O1O_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0OO1lll; + wire_nl0OO0Ol_dataout <= nlliOl1li WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO11l; + wire_nl0OO0OO_dataout <= nlliOl1ll WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO11O; + wire_nl0OO100O_dataout <= wire_nl0OO1ill_dataout WHEN niOiil1li = '1' ELSE nl0Ol0lOl; + wire_nl0OO101i_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol00Oi; + wire_nl0OO101l_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol00lO; + wire_nl0OO10ii_dataout <= wire_nl0OO1ilO_dataout WHEN niOiil1li = '1' ELSE nl0Ol0lOO; + wire_nl0OO10il_dataout <= wire_nl0OO1iOi_dataout WHEN niOiil1li = '1' ELSE nl0Ol0O1i; + wire_nl0OO10iO_dataout <= wire_nl0OO1iOl_dataout WHEN niOiil1li = '1' ELSE nl0Ol0O1l; + wire_nl0OO10li_dataout <= wire_nl0OO1i1O_dataout WHEN niOiil1li = '1' ELSE nl0Ol0O1O; + wire_nl0OO10ll_dataout <= wire_nl0OO1i0i_dataout WHEN niOiil1li = '1' ELSE nl0Ol0O0i; + wire_nl0OO10lO_dataout <= wire_nl0OO1i0l_dataout WHEN niOiil1li = '1' ELSE nl0Ol0O0l; + wire_nl0OO10Oi_dataout <= wire_nl0OO1i0O_dataout WHEN niOiil1li = '1' ELSE nl0Ol0O0O; + wire_nl0OO10Ol_dataout <= wire_nl0OO1iii_dataout WHEN niOiil1li = '1' ELSE nl0Ol0Oii; + wire_nl0OO10OO_dataout <= wire_nl0OO1iil_dataout WHEN niOiil1li = '1' ELSE nl0Ol0Oil; + wire_nl0OO110i_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0ili; + wire_nl0OO110l_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0iiO; + wire_nl0OO110O_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0iil; + wire_nl0OO111i_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0Ol0iOi; + wire_nl0OO111l_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0ilO; + wire_nl0OO111O_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0ill; + wire_nl0OO11i_dataout <= nl0OlOiO AND NOT(wire_niO01l0O_dataout); + wire_nl0OO11ii_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0iii; + wire_nl0OO11il_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0i0O; + wire_nl0OO11iO_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0i0l; + wire_nl0OO11li_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0i0i; + wire_nl0OO11ll_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0i1O; + wire_nl0OO11lO_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0i1l; + wire_nl0OO11Oi_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0i1i; + wire_nl0OO11Ol_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol00OO; + wire_nl0OO11OO_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol00Ol; + wire_nl0OO1i0i_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0O0i; + wire_nl0OO1i0l_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0O0l; + wire_nl0OO1i0O_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0O0O; + wire_nl0OO1i1i_dataout <= wire_nl0OO1iiO_dataout WHEN niOiil1li = '1' ELSE nl0Ol0OiO; + wire_nl0OO1i1l_dataout <= wire_nl0OO1ili_dataout WHEN niOiil1li = '1' ELSE nl0Ol0Oli; + wire_nl0OO1i1O_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0O1O; + wire_nl0OO1iii_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0Oii; + wire_nl0OO1iil_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0Oil; + wire_nl0OO1iiO_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0OiO; + wire_nl0OO1ili_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0Ol0Oli; + wire_nl0OO1ill_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0lOl; + wire_nl0OO1ilO_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0lOO; + wire_nl0OO1iOi_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0O1i; + wire_nl0OO1iOl_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0Ol0O1l; + wire_nl0OO1OiO_dataout <= wire_nl0OO001O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO1Ol_dataout <= wire_nl0OO0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO1Oli_dataout <= wire_nl0OO000i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO1Oll_dataout <= wire_nl0OO000l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO1OlO_dataout <= wire_nl0OO000O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO1OO_dataout <= wire_nl0OO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl0OO1OOi_dataout <= wire_nl0OO00ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO1OOl_dataout <= wire_nl0OO00il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OO1OOO_dataout <= wire_nl0OO00iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOi0i_dataout <= nlliOl1OO WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO1ii; + wire_nl0OOi0l_dataout <= nlliOl01i WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO1il; + wire_nl0OOi0O_dataout <= nlliOl01l WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO1iO; + wire_nl0OOi1i_dataout <= nlliOl1lO WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO10i; + wire_nl0OOi1l_dataout <= nlliOl1Oi WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO10l; + wire_nl0OOi1O_dataout <= nlliOl1Ol WHEN wire_w_lg_niOO1Oi0l6383w(0) = '1' ELSE nl0OO10O; + wire_nl0OOii0i_dataout <= wire_nl0OOiOOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOii0l_dataout <= wire_nl0OOiOOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOii0O_dataout <= wire_nl0OOl11i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOii1l_dataout <= wire_nl0OOiOlO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOii1O_dataout <= wire_nl0OOiOOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiii_dataout <= nl0OO1li AND NOT(wire_w_lg_niOO1Oi0l6383w(0)); + wire_nl0OOiiii_dataout <= wire_nl0OOl11l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiiil_dataout <= wire_nl0OOl11O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiiiO_dataout <= wire_nl0OOl10i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiil_dataout <= nl0OO1ll AND NOT(wire_w_lg_niOO1Oi0l6383w(0)); + wire_nl0OOiili_dataout <= wire_nl0OOl10l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiill_dataout <= wire_nl0OOl10O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiilO_dataout <= wire_nl0OOl1ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiiO_dataout <= nl0OO1lO AND NOT(wire_w_lg_niOO1Oi0l6383w(0)); + wire_nl0OOiiOi_dataout <= wire_nl0OOl1il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiiOl_dataout <= wire_nl0OOl1iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiiOO_dataout <= wire_nl0OOl1li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOil0i_dataout <= wire_nl0OOli1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOil0l_dataout <= wire_nl0OOli0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOil0O_dataout <= wire_nl0OOli0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOil1i_dataout <= wire_nl0OOl1ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOil1l_dataout <= wire_nl0OOl1lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOil1O_dataout <= wire_nl0OOli1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOili_dataout <= nl0OO1Oi AND NOT(wire_w_lg_niOO1Oi0l6383w(0)); + wire_nl0OOilii_dataout <= wire_nl0OOlili_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOilil_dataout <= wire_nl0OOlill_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiliO_dataout <= wire_nl0OOlilO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOilli_dataout <= wire_nl0OOliOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOilll_dataout <= wire_nl0OOliOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOillO_dataout <= wire_nl0OOliOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOilOi_dataout <= wire_nl0OOll1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOilOl_dataout <= wire_nl0OOll1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOilOO_dataout <= wire_nl0OOll1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiO0i_dataout <= wire_nl0OOllii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiO0l_dataout <= wire_nl0OOllil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiO0O_dataout <= wire_nl0OOlliO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiO1i_dataout <= wire_nl0OOll0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiO1l_dataout <= wire_nl0OOll0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiO1O_dataout <= wire_nl0OOll0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiOii_dataout <= wire_nl0OOllli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiOil_dataout <= wire_nl0OOlOlO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiOiO_dataout <= wire_nl0OOlOOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiOli_dataout <= wire_nl0OOlOOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiOll_dataout <= wire_nl0OOlOOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOiOlO_dataout <= wire_nl0OOl00O_dataout WHEN niOiil1Oi = '1' ELSE nl0OO1Oil; + wire_nl0OOiOOi_dataout <= wire_nl0OOl0ii_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0Oii; + wire_nl0OOiOOl_dataout <= wire_nl0OOl0il_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0Oil; + wire_nl0OOiOOO_dataout <= wire_nl0OOl0iO_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0OiO; + wire_nl0OOl00i_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nl0OOi10l; + wire_nl0OOl00l_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nl0OOi10O; + wire_nl0OOl00O_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nl0OO1Oil; + wire_nl0OOl01i_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nl0OOi11l; + wire_nl0OOl01l_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nl0OOi11O; + wire_nl0OOl01O_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nl0OOi10i; + wire_nl0OOl0ii_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nl0OO0Oii; + wire_nl0OOl0il_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nl0OO0Oil; + wire_nl0OOl0iO_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nl0OO0OiO; + wire_nl0OOl0li_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nl0OO0Oli; + wire_nl0OOl0ll_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nl0OO0Oll; + wire_nl0OOl0lO_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nl0OO0OlO; + wire_nl0OOl0Oi_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nl0OO0OOi; + wire_nl0OOl10i_dataout <= wire_nl0OOl0Oi_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0OOi; + wire_nl0OOl10l_dataout <= wire_nl0OOl1Oi_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0OOl; + wire_nl0OOl10O_dataout <= wire_nl0OOl1Ol_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0OOO; + wire_nl0OOl11i_dataout <= wire_nl0OOl0li_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0Oli; + wire_nl0OOl11l_dataout <= wire_nl0OOl0ll_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0Oll; + wire_nl0OOl11O_dataout <= wire_nl0OOl0lO_dataout WHEN niOiil1Oi = '1' ELSE nl0OO0OlO; + wire_nl0OOl1ii_dataout <= wire_nl0OOl1OO_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi11i; + wire_nl0OOl1il_dataout <= wire_nl0OOl01i_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi11l; + wire_nl0OOl1iO_dataout <= wire_nl0OOl01l_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi11O; + wire_nl0OOl1li_dataout <= wire_nl0OOl01O_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi10i; + wire_nl0OOl1ll_dataout <= wire_nl0OOl00i_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi10l; + wire_nl0OOl1lO_dataout <= wire_nl0OOl00l_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi10O; + wire_nl0OOl1Oi_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nl0OO0OOl; + wire_nl0OOl1Ol_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nl0OO0OOO; + wire_nl0OOl1OO_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nl0OOi11i; + wire_nl0OOli0i_dataout <= wire_nl0l1O11i_dataout WHEN niOiil1lO = '1' ELSE nl0OOi1iO; + wire_nl0OOli0l_dataout <= wire_nl0l1O11l_dataout WHEN niOiil1lO = '1' ELSE nl0OOi1li; + wire_nl0OOli1l_dataout <= wire_nl0l1lOOl_dataout WHEN niOiil1lO = '1' ELSE nl0OOi1ii; + wire_nl0OOli1O_dataout <= wire_nl0l1lOOO_dataout WHEN niOiil1lO = '1' ELSE nl0OOi1il; + wire_nl0OOlil_dataout <= wire_nl0OOlOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OOlili_dataout <= wire_nl0OOlO0i_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi1ll; + wire_nl0OOlill_dataout <= wire_nl0OOlO0l_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi1lO; + wire_nl0OOlilO_dataout <= wire_nl0OOlO0O_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi1Oi; + wire_nl0OOliO_dataout <= wire_nl0OOlOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OOliOi_dataout <= wire_nl0OOlOii_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi1Ol; + wire_nl0OOliOl_dataout <= wire_nl0OOlOil_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi1OO; + wire_nl0OOliOO_dataout <= wire_nl0OOlOiO_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi01i; + wire_nl0OOll0i_dataout <= wire_nl0OOlllO_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi00l; + wire_nl0OOll0l_dataout <= wire_nl0OOllOi_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi00O; + wire_nl0OOll0O_dataout <= wire_nl0OOllOl_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi0ii; + wire_nl0OOll1i_dataout <= wire_nl0OOlOli_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi01l; + wire_nl0OOll1l_dataout <= wire_nl0OOlOll_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi01O; + wire_nl0OOll1O_dataout <= wire_nl0OOllll_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi00i; + wire_nl0OOlli_dataout <= wire_nl0OOlOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OOllii_dataout <= wire_nl0OOllOO_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi0il; + wire_nl0OOllil_dataout <= wire_nl0OOlO1i_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi0iO; + wire_nl0OOlliO_dataout <= wire_nl0OOlO1l_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi0li; + wire_nl0OOlll_dataout <= wire_nl0OOO1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OOllli_dataout <= wire_nl0OOlO1O_dataout WHEN niOiil1Oi = '1' ELSE nl0OOi0ll; + wire_nl0OOllll_dataout <= wire_nl0l1lOli_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi00i; + wire_nl0OOlllO_dataout <= wire_nl0l1lOll_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi00l; + wire_nl0OOllO_dataout <= wire_nl0OOO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl0OOllOi_dataout <= wire_nl0l1lOlO_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi00O; + wire_nl0OOllOl_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi0ii; + wire_nl0OOllOO_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi0il; + wire_nl0OOlO0i_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi1ll; + wire_nl0OOlO0l_dataout <= wire_nl0l1lO1O_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi1lO; + wire_nl0OOlO0O_dataout <= wire_nl0l1lO0i_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi1Oi; + wire_nl0OOlO1i_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi0iO; + wire_nl0OOlO1l_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi0li; + wire_nl0OOlO1O_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nl0OOi0ll; + wire_nl0OOlOi_dataout <= nl0OOOOO WHEN niOO1Oi0O = '1' ELSE nl0OOO0i; + wire_nl0OOlOii_dataout <= wire_nl0l1lO0l_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi1Ol; + wire_nl0OOlOil_dataout <= wire_nl0l1lO0O_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi1OO; + wire_nl0OOlOiO_dataout <= wire_nl0l1lOii_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi01i; + wire_nl0OOlOl_dataout <= nli1111i WHEN niOO1Oi0O = '1' ELSE nl0OOl1O; + wire_nl0OOlOli_dataout <= wire_nl0l1lOil_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi01l; + wire_nl0OOlOll_dataout <= wire_nl0l1lOiO_dataout WHEN nl0iOil1i = '1' ELSE nl0OOi01O; + wire_nl0OOlOlO_dataout <= wire_nl0l1lO0O_dataout WHEN niOiil1Ol = '1' ELSE nl0OOi0lO; + wire_nl0OOlOO_dataout <= nli1111l WHEN niOO1Oi0O = '1' ELSE nl0OOl0i; + wire_nl0OOlOOi_dataout <= wire_nl0l1lOii_dataout WHEN niOiil1Ol = '1' ELSE nl0OOi0Oi; + wire_nl0OOlOOl_dataout <= wire_nl0l1lOil_dataout WHEN niOiil1Ol = '1' ELSE nl0OOi0Ol; + wire_nl0OOlOOO_dataout <= wire_nl0l1lOiO_dataout WHEN niOiil1Ol = '1' ELSE nl0OOi0OO; + wire_nl0OOO0li_dataout <= wire_nl0OOOl0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOO0ll_dataout <= wire_nl0OOOl0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOO0lO_dataout <= wire_nl0OOOl0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOO0O_dataout <= nl0OOOiO AND NOT(wire_niO01O0O_dataout); + wire_nl0OOO0Oi_dataout <= wire_nl0OOOlii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOO0Ol_dataout <= wire_nl0OOOlil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOO0OO_dataout <= wire_nl0OOOliO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOO1i_dataout <= nli1111O WHEN niOO1Oi0O = '1' ELSE nl0OOl0l; + wire_nl0OOO1l_dataout <= nli1110i WHEN niOO1Oi0O = '1' ELSE nl0OOl0O; + wire_nl0OOOi0i_dataout <= wire_nl0OOOO1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOi0l_dataout <= wire_nl0OOOO1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOi0O_dataout <= wire_nl0OOOO1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOi1i_dataout <= wire_nl0OOOlli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOi1l_dataout <= wire_nl0OOOlll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOi1O_dataout <= wire_nl0OOOlOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOiii_dataout <= wire_nl0OOOO0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOiil_dataout <= wire_nl0OOOO0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOiiO_dataout <= wire_nl0OOOO0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOil_dataout <= nl0OOlii AND NOT(wire_niO01O0O_dataout); + wire_nl0OOOili_dataout <= wire_nl0OOOOii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOill_dataout <= wire_nl0OOOOiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOilO_dataout <= wire_nl0OOOOli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOiOi_dataout <= wire_nl0OOOOll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOiOl_dataout <= wire_nl0OOOOlO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOiOO_dataout <= wire_nl0OOOOOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOl0i_dataout <= wire_nl0l1O11O_dataout WHEN niOiil01i = '1' ELSE nl0OOii1i; + wire_nl0OOOl0l_dataout <= wire_nl0l1O10i_dataout WHEN niOiil01i = '1' ELSE nl0OOO11l; + wire_nl0OOOl0O_dataout <= wire_nl0l1O10l_dataout WHEN niOiil01i = '1' ELSE nl0OOO11O; + wire_nl0OOOl1i_dataout <= wire_nl0OOOOOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOl1l_dataout <= wire_nl0OOOOOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOl1O_dataout <= wire_nli11111i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nl0OOOli_dataout <= nl0OOOlO AND NOT(wire_niO01l0O_dataout); + wire_nl0OOOlii_dataout <= wire_nl0l1O10O_dataout WHEN niOiil01i = '1' ELSE nl0OOO10i; + wire_nl0OOOlil_dataout <= wire_nl0l1O1ii_dataout WHEN niOiil01i = '1' ELSE nl0OOO10l; + wire_nl0OOOliO_dataout <= wire_nl0l1O1il_dataout WHEN niOiil01i = '1' ELSE nl0OOO10O; + wire_nl0OOOlli_dataout <= wire_nl0l1O1iO_dataout WHEN niOiil01i = '1' ELSE nl0OOO1ii; + wire_nl0OOOlll_dataout <= wire_nl0l1O1li_dataout WHEN niOiil01i = '1' ELSE nl0OOO1il; + wire_nl0OOOlOO_dataout <= wire_nl0l1lOli_dataout WHEN niOiil01O = '1' ELSE nl0OOO1iO; + wire_nl0OOOO0i_dataout <= wire_nl0l1lOOl_dataout WHEN niOiil01O = '1' ELSE nl0OOO1Oi; + wire_nl0OOOO0l_dataout <= wire_nl0l1lOOO_dataout WHEN niOiil01O = '1' ELSE nl0OOO1Ol; + wire_nl0OOOO0O_dataout <= wire_nl0l1O11i_dataout WHEN niOiil01O = '1' ELSE nl0OOO1OO; + wire_nl0OOOO1i_dataout <= wire_nl0l1lOll_dataout WHEN niOiil01O = '1' ELSE nl0OOO1li; + wire_nl0OOOO1l_dataout <= wire_nl0l1lOlO_dataout WHEN niOiil01O = '1' ELSE nl0OOO1ll; + wire_nl0OOOO1O_dataout <= wire_nl0l1lOOi_dataout WHEN niOiil01O = '1' ELSE nl0OOO1lO; + wire_nl0OOOOi_dataout <= nl0OOOll AND NOT(wire_niO01l0O_dataout); + wire_nl0OOOOii_dataout <= wire_nl0l1O11l_dataout WHEN niOiil01O = '1' ELSE nl0OOO01i; + wire_nl0OOOOiO_dataout <= wire_nl0l1lO1l_dataout WHEN niOiil00i = '1' ELSE nl0OOO01l; + wire_nl0OOOOl_dataout <= nl0OOOii AND NOT(wire_niO01l0O_dataout); + wire_nl0OOOOli_dataout <= wire_nl0l1lO1O_dataout WHEN niOiil00i = '1' ELSE nl0OOO01O; + wire_nl0OOOOll_dataout <= wire_nl0l1lO0i_dataout WHEN niOiil00i = '1' ELSE nl0OOO00i; + wire_nl0OOOOlO_dataout <= wire_nl0l1lO0l_dataout WHEN niOiil00i = '1' ELSE nl0OOO00l; + wire_nl0OOOOOi_dataout <= wire_nl0l1lO0O_dataout WHEN niOiil00i = '1' ELSE nl0OOO00O; + wire_nl0OOOOOl_dataout <= wire_nl0l1lOii_dataout WHEN niOiil00i = '1' ELSE nl0OOO0ii; + wire_nl0OOOOOO_dataout <= wire_nl0l1lOil_dataout WHEN niOiil00i = '1' ELSE nl0OOO0il; + wire_nl100000i_dataout <= nl0i1OOOi WHEN nl11OO0ll = '1' ELSE wire_nl100i1il_dataout; + wire_nl100000l_dataout <= nl0i1OlOi WHEN nl11OO0ll = '1' ELSE wire_nl100i1iO_dataout; + wire_nl100000O_dataout <= nl0i1OlOl WHEN nl11OO0ll = '1' ELSE wire_nl100i1li_dataout; + wire_nl100001i_dataout <= nl0i1OOli WHEN nl11OO0ll = '1' ELSE wire_nl100i10l_dataout; + wire_nl100001l_dataout <= nl0i1OOll WHEN nl11OO0ll = '1' ELSE wire_nl100i10O_dataout; + wire_nl100001O_dataout <= nl0i1OOlO WHEN nl11OO0ll = '1' ELSE wire_nl100i1ii_dataout; + wire_nl10000i_dataout <= nl101Oli AND NOT(wire_niO01l0O_dataout); + wire_nl10000ii_dataout <= nl0i1OlOO WHEN nl11OO0ll = '1' ELSE wire_nl100i1ll_dataout; + wire_nl10000il_dataout <= nl0i1OO1i WHEN nl11OO0ll = '1' ELSE wire_nl100i1lO_dataout; + wire_nl10000iO_dataout <= nl0i1OO1l WHEN nl11OO0ll = '1' ELSE wire_nl100i1Oi_dataout; + wire_nl10000li_dataout <= nl0i1OO1O WHEN nl11OO0ll = '1' ELSE wire_nl100i1Ol_dataout; + wire_nl10000ll_dataout <= nl0i1OO0i WHEN nl11OO0ll = '1' ELSE wire_nl100i1OO_dataout; + wire_nl10000lO_dataout <= nl0i1OO0l WHEN nl11OO0ll = '1' ELSE wire_nl100i01i_dataout; + wire_nl10000O_dataout <= nl1000il AND NOT(wire_niO01O0O_dataout); + wire_nl10000Oi_dataout <= nl0i1Ol0l WHEN nl11OO0ll = '1' ELSE wire_nl100i01l_dataout; + wire_nl10000Ol_dataout <= nl0i1Ol0O WHEN nl11OO0ll = '1' ELSE wire_nl100i01O_dataout; + wire_nl10000OO_dataout <= nl0i1Olii WHEN nl11OO0ll = '1' ELSE wire_nl100i00i_dataout; + wire_nl100010i_dataout <= nl0i01lOi WHEN niOi10llO = '1' ELSE wire_nl1000Oil_dataout; + wire_nl100010l_dataout <= nl0i01lOl WHEN niOi10llO = '1' ELSE wire_nl1000OiO_dataout; + wire_nl100010O_dataout <= nl0i01lOO WHEN niOi10llO = '1' ELSE wire_nl1000Oli_dataout; + wire_nl100011i_dataout <= nl0i01lli WHEN niOi10llO = '1' ELSE wire_nl1000O0l_dataout; + wire_nl100011l_dataout <= nl0i01lll WHEN niOi10llO = '1' ELSE wire_nl1000O0O_dataout; + wire_nl100011O_dataout <= nl0i01llO WHEN niOi10llO = '1' ELSE wire_nl1000Oii_dataout; + wire_nl10001ii_dataout <= nl0i01O1i WHEN niOi10llO = '1' ELSE wire_nl1000Oll_dataout; + wire_nl10001il_dataout <= nl0i01O1l WHEN niOi10llO = '1' ELSE wire_nl1000OlO_dataout; + wire_nl10001iO_dataout <= nl0i01O1O WHEN niOi10llO = '1' ELSE wire_nl1000OOi_dataout; + wire_nl10001l_dataout <= nl10000l AND NOT(wire_niO01l0O_dataout); + wire_nl10001li_dataout <= nl0i01O0i WHEN niOi10llO = '1' ELSE wire_nl1000OOl_dataout; + wire_nl10001ll_dataout <= nl0i01O0l WHEN niOi10llO = '1' ELSE wire_nl1000OOO_dataout; + wire_nl10001lO_dataout <= nl0i1OO0O WHEN nl11OO0ll = '1' ELSE wire_nl100i11i_dataout; + wire_nl10001Oi_dataout <= nl0i1OOii WHEN nl11OO0ll = '1' ELSE wire_nl100i11l_dataout; + wire_nl10001Ol_dataout <= nl0i1OOil WHEN nl11OO0ll = '1' ELSE wire_nl100i11O_dataout; + wire_nl10001OO_dataout <= nl0i1OOiO WHEN nl11OO0ll = '1' ELSE wire_nl100i10i_dataout; + wire_nl1000i0i_dataout <= nl0i1Olll WHEN nl11OO0ll = '1' ELSE wire_nl100i0il_dataout; + wire_nl1000i0l_dataout <= nl0i1OllO WHEN nl11OO0ll = '1' ELSE wire_nl100i0iO_dataout; + wire_nl1000i0O_dataout <= nl0i1O1li WHEN nl11OO0ll = '1' ELSE wire_nl100i0li_dataout; + wire_nl1000i1i_dataout <= nl0i1Olil WHEN nl11OO0ll = '1' ELSE wire_nl100i00l_dataout; + wire_nl1000i1l_dataout <= nl0i1OliO WHEN nl11OO0ll = '1' ELSE wire_nl100i00O_dataout; + wire_nl1000i1O_dataout <= nl0i1Olli WHEN nl11OO0ll = '1' ELSE wire_nl100i0ii_dataout; + wire_nl1000iii_dataout <= nl0i1OiOi WHEN nl11OO0ll = '1' ELSE wire_nl100i0ll_dataout; + wire_nl1000iil_dataout <= nl0i1OiOl WHEN nl11OO0ll = '1' ELSE wire_nl100i0lO_dataout; + wire_nl1000iiO_dataout <= nl0i1OiOO WHEN nl11OO0ll = '1' ELSE wire_nl100i0Oi_dataout; + wire_nl1000ili_dataout <= nl0i1Ol1i WHEN nl11OO0ll = '1' ELSE wire_nl100i0Ol_dataout; + wire_nl1000ill_dataout <= nl0i1Ol1l WHEN nl11OO0ll = '1' ELSE wire_nl100i0OO_dataout; + wire_nl1000ilO_dataout <= nl0i1Ol1O WHEN nl11OO0ll = '1' ELSE wire_nl100ii1i_dataout; + wire_nl1000iO_dataout <= nl1000ii AND NOT(wire_niO01O0O_dataout); + wire_nl1000iOi_dataout <= nl0i1Ol0i WHEN nl11OO0ll = '1' ELSE wire_nl100ii1l_dataout; + wire_nl1000iOl_dataout <= nl0i01i0i WHEN nl11OO0ll = '1' ELSE wire_nl100ii1O_dataout; + wire_nl1000iOO_dataout <= nl0i01i0l WHEN nl11OO0ll = '1' ELSE wire_nl100ii0i_dataout; + wire_nl1000l0i_dataout <= nl0i01iiO WHEN nl11OO0ll = '1' ELSE wire_nl100iiil_dataout; + wire_nl1000l0l_dataout <= nl0i01ili WHEN nl11OO0ll = '1' ELSE wire_nl100iiiO_dataout; + wire_nl1000l0O_dataout <= nl0i01ill WHEN nl11OO0ll = '1' ELSE wire_nl100iili_dataout; + wire_nl1000l1i_dataout <= nl0i01i0O WHEN nl11OO0ll = '1' ELSE wire_nl100ii0l_dataout; + wire_nl1000l1l_dataout <= nl0i01iii WHEN nl11OO0ll = '1' ELSE wire_nl100ii0O_dataout; + wire_nl1000l1O_dataout <= nl0i01iil WHEN nl11OO0ll = '1' ELSE wire_nl100iiii_dataout; + wire_nl1000li_dataout <= nl10001O AND NOT(wire_niO01O0O_dataout); + wire_nl1000lii_dataout <= nl0i01ilO WHEN nl11OO0ll = '1' ELSE wire_nl100iill_dataout; + wire_nl1000lil_dataout <= nl0i01iOi WHEN nl11OO0ll = '1' ELSE wire_nl100iilO_dataout; + wire_nl1000liO_dataout <= nl0i01iOl WHEN nl11OO0ll = '1' ELSE wire_nl100iiOi_dataout; + wire_nl1000lli_dataout <= nl0i01iOO WHEN nl11OO0ll = '1' ELSE wire_nl100iiOl_dataout; + wire_nl1000lll_dataout <= nl0i01l1i WHEN nl11OO0ll = '1' ELSE wire_nl100iiOO_dataout; + wire_nl1000llO_dataout <= nl0i01l1l WHEN nl11OO0ll = '1' ELSE wire_nl100il1i_dataout; + wire_nl1000lOi_dataout <= nl0i01l1O WHEN nl11OO0ll = '1' ELSE wire_nl100il1l_dataout; + wire_nl1000lOl_dataout <= nl0i01l0i WHEN nl11OO0ll = '1' ELSE wire_nl100il1O_dataout; + wire_nl1000lOO_dataout <= nl0i01l0l WHEN nl11OO0ll = '1' ELSE wire_nl100il0i_dataout; + wire_nl1000O_dataout <= niO0OOOl AND NOT(wire_niO01O0O_dataout); + wire_nl1000O0i_dataout <= nl0i01liO WHEN nl11OO0ll = '1' ELSE wire_nl100ilil_dataout; + wire_nl1000O0l_dataout <= nl0i01lli WHEN nl11OO0ll = '1' ELSE wire_nl100iliO_dataout; + wire_nl1000O0O_dataout <= nl0i01lll WHEN nl11OO0ll = '1' ELSE wire_nl100illi_dataout; + wire_nl1000O1i_dataout <= nl0i01l0O WHEN nl11OO0ll = '1' ELSE wire_nl100il0l_dataout; + wire_nl1000O1l_dataout <= nl0i01lii WHEN nl11OO0ll = '1' ELSE wire_nl100il0O_dataout; + wire_nl1000O1O_dataout <= nl0i01lil WHEN nl11OO0ll = '1' ELSE wire_nl100ilii_dataout; + wire_nl1000Oii_dataout <= nl0i01llO WHEN nl11OO0ll = '1' ELSE wire_nl100illl_dataout; + wire_nl1000Oil_dataout <= nl0i01lOi WHEN nl11OO0ll = '1' ELSE wire_nl100illO_dataout; + wire_nl1000OiO_dataout <= nl0i01lOl WHEN nl11OO0ll = '1' ELSE wire_nl100ilOi_dataout; + wire_nl1000Oli_dataout <= nl0i01lOO WHEN nl11OO0ll = '1' ELSE wire_nl100ilOl_dataout; + wire_nl1000Oll_dataout <= nl0i01O1i WHEN nl11OO0ll = '1' ELSE wire_nl100ilOO_dataout; + wire_nl1000OlO_dataout <= nl0i01O1l WHEN nl11OO0ll = '1' ELSE wire_nl100iO1i_dataout; + wire_nl1000OOi_dataout <= nl0i01O1O WHEN nl11OO0ll = '1' ELSE wire_nl100iO1l_dataout; + wire_nl1000OOl_dataout <= nl0i01O0i WHEN nl11OO0ll = '1' ELSE wire_nl100iO1O_dataout; + wire_nl1000OOO_dataout <= nl0i01O0l WHEN nl11OO0ll = '1' ELSE wire_nl100iO0i_dataout; + wire_nl100100i_dataout <= nl0i00i0l WHEN niOi10lOi = '1' ELSE wire_nl10001il_dataout; + wire_nl100100l_dataout <= nl0i00i0O WHEN niOi10lOi = '1' ELSE wire_nl10001iO_dataout; + wire_nl100100O_dataout <= nl0i00iii WHEN niOi10lOi = '1' ELSE wire_nl10001li_dataout; + wire_nl100101i_dataout <= nl0i00i1l WHEN niOi10lOi = '1' ELSE wire_nl100010l_dataout; + wire_nl100101l_dataout <= nl0i00i1O WHEN niOi10lOi = '1' ELSE wire_nl100010O_dataout; + wire_nl100101O_dataout <= nl0i00i0i WHEN niOi10lOi = '1' ELSE wire_nl10001ii_dataout; + wire_nl10010i_dataout <= wire_nl1001Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10010ii_dataout <= nl0i00iil WHEN niOi10lOi = '1' ELSE wire_nl10001ll_dataout; + wire_nl10010il_dataout <= nl0i0111l WHEN niOi10llO = '1' ELSE wire_nl10001lO_dataout; + wire_nl10010iO_dataout <= nl0i0111O WHEN niOi10llO = '1' ELSE wire_nl10001Oi_dataout; + wire_nl10010l_dataout <= nl1000ll WHEN niOO1iOOi = '1' ELSE nl1001OO; + wire_nl10010li_dataout <= nl0i0110i WHEN niOi10llO = '1' ELSE wire_nl10001Ol_dataout; + wire_nl10010ll_dataout <= nl0i0110l WHEN niOi10llO = '1' ELSE wire_nl10001OO_dataout; + wire_nl10010lO_dataout <= nl0i0110O WHEN niOi10llO = '1' ELSE wire_nl100001i_dataout; + wire_nl10010O_dataout <= nl1000lO WHEN niOO1iOOi = '1' ELSE nl101O1l; + wire_nl10010Oi_dataout <= nl0i011ii WHEN niOi10llO = '1' ELSE wire_nl100001l_dataout; + wire_nl10010Ol_dataout <= nl0i011il WHEN niOi10llO = '1' ELSE wire_nl100001O_dataout; + wire_nl10010OO_dataout <= nl0i011iO WHEN niOi10llO = '1' ELSE wire_nl100000i_dataout; + wire_nl100110i_dataout <= nl0i0000l WHEN niOi10lOi = '1' ELSE wire_nl1001Oil_dataout; + wire_nl100110l_dataout <= nl0i0000O WHEN niOi10lOi = '1' ELSE wire_nl1001OiO_dataout; + wire_nl100110O_dataout <= nl0i000ii WHEN niOi10lOi = '1' ELSE wire_nl1001Oli_dataout; + wire_nl100111i_dataout <= nl0i0001l WHEN niOi10lOi = '1' ELSE wire_nl1001O0l_dataout; + wire_nl100111l_dataout <= nl0i0001O WHEN niOi10lOi = '1' ELSE wire_nl1001O0O_dataout; + wire_nl100111O_dataout <= nl0i0000i WHEN niOi10lOi = '1' ELSE wire_nl1001Oii_dataout; + wire_nl10011i_dataout <= wire_nl1001li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10011ii_dataout <= nl0i000il WHEN niOi10lOi = '1' ELSE wire_nl1001Oll_dataout; + wire_nl10011il_dataout <= nl0i000iO WHEN niOi10lOi = '1' ELSE wire_nl1001OlO_dataout; + wire_nl10011iO_dataout <= nl0i000li WHEN niOi10lOi = '1' ELSE wire_nl1001OOi_dataout; + wire_nl10011l_dataout <= wire_nl1001ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10011li_dataout <= nl0i000ll WHEN niOi10lOi = '1' ELSE wire_nl1001OOl_dataout; + wire_nl10011ll_dataout <= nl0i000lO WHEN niOi10lOi = '1' ELSE wire_nl1001OOO_dataout; + wire_nl10011lO_dataout <= nl0i000Oi WHEN niOi10lOi = '1' ELSE wire_nl100011i_dataout; + wire_nl10011O_dataout <= wire_nl1001lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10011Oi_dataout <= nl0i000Ol WHEN niOi10lOi = '1' ELSE wire_nl100011l_dataout; + wire_nl10011Ol_dataout <= nl0i000OO WHEN niOi10lOi = '1' ELSE wire_nl100011O_dataout; + wire_nl10011OO_dataout <= nl0i00i1i WHEN niOi10lOi = '1' ELSE wire_nl100010i_dataout; + wire_nl1001i0i_dataout <= nl0i011Oi WHEN niOi10llO = '1' ELSE wire_nl10000il_dataout; + wire_nl1001i0l_dataout <= nl0i011Ol WHEN niOi10llO = '1' ELSE wire_nl10000iO_dataout; + wire_nl1001i0O_dataout <= nl0i011OO WHEN niOi10llO = '1' ELSE wire_nl10000li_dataout; + wire_nl1001i1i_dataout <= nl0i011li WHEN niOi10llO = '1' ELSE wire_nl100000l_dataout; + wire_nl1001i1l_dataout <= nl0i011ll WHEN niOi10llO = '1' ELSE wire_nl100000O_dataout; + wire_nl1001i1O_dataout <= nl0i011lO WHEN niOi10llO = '1' ELSE wire_nl10000ii_dataout; + wire_nl1001ii_dataout <= nl1000Oi WHEN niOO1iOOi = '1' ELSE nl101O1O; + wire_nl1001iii_dataout <= nl0i0101i WHEN niOi10llO = '1' ELSE wire_nl10000ll_dataout; + wire_nl1001iil_dataout <= nl0i0101l WHEN niOi10llO = '1' ELSE wire_nl10000lO_dataout; + wire_nl1001iiO_dataout <= nl0i0101O WHEN niOi10llO = '1' ELSE wire_nl10000Oi_dataout; + wire_nl1001il_dataout <= nl1000Ol WHEN niOO1iOOi = '1' ELSE nl101O0i; + wire_nl1001ili_dataout <= nl0i0100i WHEN niOi10llO = '1' ELSE wire_nl10000Ol_dataout; + wire_nl1001ill_dataout <= nl0i0100l WHEN niOi10llO = '1' ELSE wire_nl10000OO_dataout; + wire_nl1001ilO_dataout <= nl0i0100O WHEN niOi10llO = '1' ELSE wire_nl1000i1i_dataout; + wire_nl1001iO_dataout <= nl1000OO WHEN niOO1iOOi = '1' ELSE nl101O0l; + wire_nl1001iOi_dataout <= nl0i010ii WHEN niOi10llO = '1' ELSE wire_nl1000i1l_dataout; + wire_nl1001iOl_dataout <= nl0i010il WHEN niOi10llO = '1' ELSE wire_nl1000i1O_dataout; + wire_nl1001iOO_dataout <= nl0i010iO WHEN niOi10llO = '1' ELSE wire_nl1000i0i_dataout; + wire_nl1001l0i_dataout <= nl0i010Oi WHEN niOi10llO = '1' ELSE wire_nl1000iil_dataout; + wire_nl1001l0l_dataout <= nl0i010Ol WHEN niOi10llO = '1' ELSE wire_nl1000iiO_dataout; + wire_nl1001l0O_dataout <= nl0i010OO WHEN niOi10llO = '1' ELSE wire_nl1000ili_dataout; + wire_nl1001l1i_dataout <= nl0i010li WHEN niOi10llO = '1' ELSE wire_nl1000i0l_dataout; + wire_nl1001l1l_dataout <= nl0i010ll WHEN niOi10llO = '1' ELSE wire_nl1000i0O_dataout; + wire_nl1001l1O_dataout <= nl0i010lO WHEN niOi10llO = '1' ELSE wire_nl1000iii_dataout; + wire_nl1001li_dataout <= nl100i1i WHEN niOO1iOOi = '1' ELSE nl101O0O; + wire_nl1001lii_dataout <= nl0i01i1i WHEN niOi10llO = '1' ELSE wire_nl1000ill_dataout; + wire_nl1001lil_dataout <= nl0i01i1l WHEN niOi10llO = '1' ELSE wire_nl1000ilO_dataout; + wire_nl1001liO_dataout <= nl0i01i1O WHEN niOi10llO = '1' ELSE wire_nl1000iOi_dataout; + wire_nl1001ll_dataout <= nl100i1l WHEN niOO1iOOi = '1' ELSE nl101Oii; + wire_nl1001lli_dataout <= nl0i01i0i WHEN niOi10llO = '1' ELSE wire_nl1000iOl_dataout; + wire_nl1001lll_dataout <= nl0i01i0l WHEN niOi10llO = '1' ELSE wire_nl1000iOO_dataout; + wire_nl1001llO_dataout <= nl0i01i0O WHEN niOi10llO = '1' ELSE wire_nl1000l1i_dataout; + wire_nl1001lO_dataout <= nl100i1O WHEN niOO1iOOi = '1' ELSE nl101Oil; + wire_nl1001lOi_dataout <= nl0i01iii WHEN niOi10llO = '1' ELSE wire_nl1000l1l_dataout; + wire_nl1001lOl_dataout <= nl0i01iil WHEN niOi10llO = '1' ELSE wire_nl1000l1O_dataout; + wire_nl1001lOO_dataout <= nl0i01iiO WHEN niOi10llO = '1' ELSE wire_nl1000l0i_dataout; + wire_nl1001O0i_dataout <= nl0i01iOi WHEN niOi10llO = '1' ELSE wire_nl1000lil_dataout; + wire_nl1001O0l_dataout <= nl0i01iOl WHEN niOi10llO = '1' ELSE wire_nl1000liO_dataout; + wire_nl1001O0O_dataout <= nl0i01iOO WHEN niOi10llO = '1' ELSE wire_nl1000lli_dataout; + wire_nl1001O1i_dataout <= nl0i01ili WHEN niOi10llO = '1' ELSE wire_nl1000l0l_dataout; + wire_nl1001O1l_dataout <= nl0i01ill WHEN niOi10llO = '1' ELSE wire_nl1000l0O_dataout; + wire_nl1001O1O_dataout <= nl0i01ilO WHEN niOi10llO = '1' ELSE wire_nl1000lii_dataout; + wire_nl1001Oi_dataout <= nl100i0i WHEN niOO1iOOi = '1' ELSE nl101OiO; + wire_nl1001Oii_dataout <= nl0i01l1i WHEN niOi10llO = '1' ELSE wire_nl1000lll_dataout; + wire_nl1001Oil_dataout <= nl0i01l1l WHEN niOi10llO = '1' ELSE wire_nl1000llO_dataout; + wire_nl1001OiO_dataout <= nl0i01l1O WHEN niOi10llO = '1' ELSE wire_nl1000lOi_dataout; + wire_nl1001Oli_dataout <= nl0i01l0i WHEN niOi10llO = '1' ELSE wire_nl1000lOl_dataout; + wire_nl1001Oll_dataout <= nl0i01l0l WHEN niOi10llO = '1' ELSE wire_nl1000lOO_dataout; + wire_nl1001OlO_dataout <= nl0i01l0O WHEN niOi10llO = '1' ELSE wire_nl1000O1i_dataout; + wire_nl1001OOi_dataout <= nl0i01lii WHEN niOi10llO = '1' ELSE wire_nl1000O1l_dataout; + wire_nl1001OOl_dataout <= nl0i01lil WHEN niOi10llO = '1' ELSE wire_nl1000O1O_dataout; + wire_nl1001OOO_dataout <= nl0i01liO WHEN niOi10llO = '1' ELSE wire_nl1000O0i_dataout; + wire_nl100i00i_dataout <= nl0i1Olii WHEN nl11OO0li = '1' ELSE wire_nl100l1il_dataout; + wire_nl100i00l_dataout <= nl0i1Olil WHEN nl11OO0li = '1' ELSE wire_nl100l1iO_dataout; + wire_nl100i00O_dataout <= nl0i1OliO WHEN nl11OO0li = '1' ELSE wire_nl100l1li_dataout; + wire_nl100i01i_dataout <= nl0i1OO0l WHEN nl11OO0li = '1' ELSE wire_nl100l10l_dataout; + wire_nl100i01l_dataout <= nl0i1Ol0l WHEN nl11OO0li = '1' ELSE wire_nl100l10O_dataout; + wire_nl100i01O_dataout <= nl0i1Ol0O WHEN nl11OO0li = '1' ELSE wire_nl100l1ii_dataout; + wire_nl100i0ii_dataout <= nl0i1Olli WHEN nl11OO0li = '1' ELSE wire_nl100l1ll_dataout; + wire_nl100i0il_dataout <= nl0i1Olll WHEN nl11OO0li = '1' ELSE wire_nl100l1lO_dataout; + wire_nl100i0iO_dataout <= nl0i1OllO WHEN nl11OO0li = '1' ELSE wire_nl100l1Oi_dataout; + wire_nl100i0l_dataout <= wire_nl100iOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100i0li_dataout <= nl0i1O1li WHEN nl11OO0li = '1' ELSE wire_nl100l1Ol_dataout; + wire_nl100i0ll_dataout <= nl0i1OiOi WHEN nl11OO0li = '1' ELSE wire_nl100l1OO_dataout; + wire_nl100i0lO_dataout <= nl0i1OiOl WHEN nl11OO0li = '1' ELSE wire_nl100l01i_dataout; + wire_nl100i0O_dataout <= wire_nl100l1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100i0Oi_dataout <= nl0i1OiOO WHEN nl11OO0li = '1' ELSE wire_nl100l01l_dataout; + wire_nl100i0Ol_dataout <= nl0i1Ol1i WHEN nl11OO0li = '1' ELSE wire_nl100l01O_dataout; + wire_nl100i0OO_dataout <= nl0i1Ol1l WHEN nl11OO0li = '1' ELSE wire_nl100l00i_dataout; + wire_nl100i10i_dataout <= nl0i1OOiO WHEN nl11OO0li = '1' ELSE wire_nl100iOil_dataout; + wire_nl100i10l_dataout <= nl0i1OOli WHEN nl11OO0li = '1' ELSE wire_nl100iOiO_dataout; + wire_nl100i10O_dataout <= nl0i1OOll WHEN nl11OO0li = '1' ELSE wire_nl100iOli_dataout; + wire_nl100i11i_dataout <= nl0i1OO0O WHEN nl11OO0li = '1' ELSE wire_nl100iO0l_dataout; + wire_nl100i11l_dataout <= nl0i1OOii WHEN nl11OO0li = '1' ELSE wire_nl100iO0O_dataout; + wire_nl100i11O_dataout <= nl0i1OOil WHEN nl11OO0li = '1' ELSE wire_nl100iOii_dataout; + wire_nl100i1ii_dataout <= nl0i1OOlO WHEN nl11OO0li = '1' ELSE wire_nl100iOll_dataout; + wire_nl100i1il_dataout <= nl0i1OOOi WHEN nl11OO0li = '1' ELSE wire_nl100iOlO_dataout; + wire_nl100i1iO_dataout <= nl0i1OlOi WHEN nl11OO0li = '1' ELSE wire_nl100iOOi_dataout; + wire_nl100i1li_dataout <= nl0i1OlOl WHEN nl11OO0li = '1' ELSE wire_nl100iOOl_dataout; + wire_nl100i1ll_dataout <= nl0i1OlOO WHEN nl11OO0li = '1' ELSE wire_nl100iOOO_dataout; + wire_nl100i1lO_dataout <= nl0i1OO1i WHEN nl11OO0li = '1' ELSE wire_nl100l11i_dataout; + wire_nl100i1Oi_dataout <= nl0i1OO1l WHEN nl11OO0li = '1' ELSE wire_nl100l11l_dataout; + wire_nl100i1Ol_dataout <= nl0i1OO1O WHEN nl11OO0li = '1' ELSE wire_nl100l11O_dataout; + wire_nl100i1OO_dataout <= nl0i1OO0i WHEN nl11OO0li = '1' ELSE wire_nl100l10i_dataout; + wire_nl100ii_dataout <= wire_nl10OOl_o AND NOT(wire_niO01O0O_dataout); + wire_nl100ii0i_dataout <= nl0i1OOii WHEN nl11OO0li = '1' ELSE wire_nl100l0il_dataout; + wire_nl100ii0l_dataout <= nl0i1OOil WHEN nl11OO0li = '1' ELSE wire_nl100l0iO_dataout; + wire_nl100ii0O_dataout <= nl0i1OOiO WHEN nl11OO0li = '1' ELSE wire_nl100l0li_dataout; + wire_nl100ii1i_dataout <= nl0i1Ol1O WHEN nl11OO0li = '1' ELSE wire_nl100l00l_dataout; + wire_nl100ii1l_dataout <= nl0i1Ol0i WHEN nl11OO0li = '1' ELSE wire_nl100l00O_dataout; + wire_nl100ii1O_dataout <= nl0i1OO0O WHEN nl11OO0li = '1' ELSE wire_nl100l0ii_dataout; + wire_nl100iii_dataout <= wire_nl100l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100iiii_dataout <= nl0i1OOli WHEN nl11OO0li = '1' ELSE wire_nl100l0ll_dataout; + wire_nl100iiil_dataout <= nl0i1OOll WHEN nl11OO0li = '1' ELSE wire_nl100l0lO_dataout; + wire_nl100iiiO_dataout <= nl0i1OOlO WHEN nl11OO0li = '1' ELSE wire_nl100l0Oi_dataout; + wire_nl100iil_dataout <= wire_nl100l0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100iili_dataout <= nl0i1OOOi WHEN nl11OO0li = '1' ELSE wire_nl100l0Ol_dataout; + wire_nl100iill_dataout <= nl0i1OlOi WHEN nl11OO0li = '1' ELSE wire_nl100l0OO_dataout; + wire_nl100iilO_dataout <= nl0i1OlOl WHEN nl11OO0li = '1' ELSE wire_nl100li1i_dataout; + wire_nl100iiO_dataout <= wire_nl100l0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100iiOi_dataout <= nl0i1OlOO WHEN nl11OO0li = '1' ELSE wire_nl100li1l_dataout; + wire_nl100iiOl_dataout <= nl0i1OO1i WHEN nl11OO0li = '1' ELSE wire_nl100li1O_dataout; + wire_nl100iiOO_dataout <= nl0i1OO1l WHEN nl11OO0li = '1' ELSE wire_nl100li0i_dataout; + wire_nl100il_dataout <= wire_nl10OOO_o AND NOT(wire_niO01O0O_dataout); + wire_nl100il0i_dataout <= nl0i1Ol0l WHEN nl11OO0li = '1' ELSE wire_nl100liil_dataout; + wire_nl100il0l_dataout <= nl0i1Ol0O WHEN nl11OO0li = '1' ELSE wire_nl100liiO_dataout; + wire_nl100il0O_dataout <= nl0i1Olii WHEN nl11OO0li = '1' ELSE wire_nl100lili_dataout; + wire_nl100il1i_dataout <= nl0i1OO1O WHEN nl11OO0li = '1' ELSE wire_nl100li0l_dataout; + wire_nl100il1l_dataout <= nl0i1OO0i WHEN nl11OO0li = '1' ELSE wire_nl100li0O_dataout; + wire_nl100il1O_dataout <= nl0i1OO0l WHEN nl11OO0li = '1' ELSE wire_nl100liii_dataout; + wire_nl100ili_dataout <= wire_nl100l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100ilii_dataout <= nl0i1Olil WHEN nl11OO0li = '1' ELSE wire_nl100lill_dataout; + wire_nl100ilil_dataout <= nl0i1OliO WHEN nl11OO0li = '1' ELSE wire_nl100lilO_dataout; + wire_nl100iliO_dataout <= nl0i1Olli WHEN nl11OO0li = '1' ELSE wire_nl100liOi_dataout; + wire_nl100ill_dataout <= wire_nl100lii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100illi_dataout <= nl0i1Olll WHEN nl11OO0li = '1' ELSE wire_nl100liOl_dataout; + wire_nl100illl_dataout <= nl0i1OllO WHEN nl11OO0li = '1' ELSE wire_nl100liOO_dataout; + wire_nl100illO_dataout <= nl0i1O1li WHEN nl11OO0li = '1' ELSE wire_nl100ll1i_dataout; + wire_nl100ilO_dataout <= wire_nl100lil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100ilOi_dataout <= nl0i1OiOi WHEN nl11OO0li = '1' ELSE wire_nl100ll1l_dataout; + wire_nl100ilOl_dataout <= nl0i1OiOl WHEN nl11OO0li = '1' ELSE wire_nl100ll1O_dataout; + wire_nl100ilOO_dataout <= nl0i1OiOO WHEN nl11OO0li = '1' ELSE wire_nl100ll0i_dataout; + wire_nl100iO_dataout <= wire_nl1i11i_o AND NOT(wire_niO01O0O_dataout); + wire_nl100iO0i_dataout <= nl0i1Ol0i WHEN nl11OO0li = '1' ELSE wire_nl100llil_dataout; + wire_nl100iO0l_dataout <= nlOiiiOO WHEN nl11OOi1O = '1' ELSE wire_nl100lliO_dataout; + wire_nl100iO0O_dataout <= nlOiil1i WHEN nl11OOi1O = '1' ELSE wire_nl100llli_dataout; + wire_nl100iO1i_dataout <= nl0i1Ol1i WHEN nl11OO0li = '1' ELSE wire_nl100ll0l_dataout; + wire_nl100iO1l_dataout <= nl0i1Ol1l WHEN nl11OO0li = '1' ELSE wire_nl100ll0O_dataout; + wire_nl100iO1O_dataout <= nl0i1Ol1O WHEN nl11OO0li = '1' ELSE wire_nl100llii_dataout; + wire_nl100iOi_dataout <= wire_nl100liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100iOii_dataout <= nlOiil1l WHEN nl11OOi1O = '1' ELSE wire_nl100llll_dataout; + wire_nl100iOil_dataout <= nlOiil1O WHEN nl11OOi1O = '1' ELSE wire_nl100lllO_dataout; + wire_nl100iOiO_dataout <= nlOiil0i WHEN nl11OOi1O = '1' ELSE wire_nl100llOi_dataout; + wire_nl100iOl_dataout <= wire_nl100lli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl100iOli_dataout <= nlOiil0l WHEN nl11OOi1O = '1' ELSE wire_nl100llOl_dataout; + wire_nl100iOll_dataout <= nlOiil0O WHEN nl11OOi1O = '1' ELSE wire_nl100llOO_dataout; + wire_nl100iOlO_dataout <= nlOiilii WHEN nl11OOi1O = '1' ELSE wire_nl100lO1i_dataout; + wire_nl100iOO_dataout <= wire_niOOO0O_w_lg_nl1000il8223w(0) WHEN (wire_w_lg_niOO1iOOO8222w(0) AND wire_w_lg_niOO1iOOl8224w(0)) = '1' ELSE nl1000il; + wire_nl100iOOi_dataout <= nlOiilil WHEN nl11OOi1O = '1' ELSE wire_nl100lO1l_dataout; + wire_nl100iOOl_dataout <= nlOiiliO WHEN nl11OOi1O = '1' ELSE wire_nl100lO1O_dataout; + wire_nl100iOOO_dataout <= nlOiilli WHEN nl11OOi1O = '1' ELSE wire_nl100lO0i_dataout; + wire_nl100l00i_dataout <= nlOiiOOl WHEN nl11OOi1O = '1' ELSE wire_nl100O1il_dataout; + wire_nl100l00l_dataout <= nlOiiOOO WHEN nl11OOi1O = '1' ELSE wire_nl100O1iO_dataout; + wire_nl100l00O_dataout <= nlOil11i WHEN nl11OOi1O = '1' ELSE wire_nl100O1li_dataout; + wire_nl100l01i_dataout <= nlOiiOll WHEN nl11OOi1O = '1' ELSE wire_nl100O10l_dataout; + wire_nl100l01l_dataout <= nlOiiOlO WHEN nl11OOi1O = '1' ELSE wire_nl100O10O_dataout; + wire_nl100l01O_dataout <= nlOiiOOi WHEN nl11OOi1O = '1' ELSE wire_nl100O1ii_dataout; + wire_nl100l0i_dataout <= ni0li0O WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl1000Oi; + wire_nl100l0ii_dataout <= nlOil11l WHEN nl11OOi1O = '1' ELSE wire_nl100O1ll_dataout; + wire_nl100l0il_dataout <= nlOil11O WHEN nl11OOi1O = '1' ELSE wire_nl100O1lO_dataout; + wire_nl100l0iO_dataout <= nlOil10i WHEN nl11OOi1O = '1' ELSE wire_nl100O1Oi_dataout; + wire_nl100l0l_dataout <= ni0liii WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl1000Ol; + wire_nl100l0li_dataout <= nlOil10l WHEN nl11OOi1O = '1' ELSE wire_nl100O1Ol_dataout; + wire_nl100l0ll_dataout <= nlOil10O WHEN nl11OOi1O = '1' ELSE wire_nl100O1OO_dataout; + wire_nl100l0lO_dataout <= nlOil1ii WHEN nl11OOi1O = '1' ELSE wire_nl100O01i_dataout; + wire_nl100l0O_dataout <= ni0liil WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl1000OO; + wire_nl100l0Oi_dataout <= nlOil1il WHEN nl11OOi1O = '1' ELSE wire_nl100O01l_dataout; + wire_nl100l0Ol_dataout <= nlOil1iO WHEN nl11OOi1O = '1' ELSE wire_nl100O01O_dataout; + wire_nl100l0OO_dataout <= nlOil1li WHEN nl11OOi1O = '1' ELSE wire_nl100O00i_dataout; + wire_nl100l10i_dataout <= nlOiilOl WHEN nl11OOi1O = '1' ELSE wire_nl100lOil_dataout; + wire_nl100l10l_dataout <= nlOiilOO WHEN nl11OOi1O = '1' ELSE wire_nl100lOiO_dataout; + wire_nl100l10O_dataout <= nlOiiO1i WHEN nl11OOi1O = '1' ELSE wire_nl100lOli_dataout; + wire_nl100l11i_dataout <= nlOiilll WHEN nl11OOi1O = '1' ELSE wire_nl100lO0l_dataout; + wire_nl100l11l_dataout <= nlOiillO WHEN nl11OOi1O = '1' ELSE wire_nl100lO0O_dataout; + wire_nl100l11O_dataout <= nlOiilOi WHEN nl11OOi1O = '1' ELSE wire_nl100lOii_dataout; + wire_nl100l1ii_dataout <= nlOiiO1l WHEN nl11OOi1O = '1' ELSE wire_nl100lOll_dataout; + wire_nl100l1il_dataout <= nlOiiO1O WHEN nl11OOi1O = '1' ELSE wire_nl100lOlO_dataout; + wire_nl100l1iO_dataout <= nlOiiO0i WHEN nl11OOi1O = '1' ELSE wire_nl100lOOi_dataout; + wire_nl100l1l_dataout <= ni0li1l WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl1000ll; + wire_nl100l1li_dataout <= nlOiiO0l WHEN nl11OOi1O = '1' ELSE wire_nl100lOOl_dataout; + wire_nl100l1ll_dataout <= nlOiiO0O WHEN nl11OOi1O = '1' ELSE wire_nl100lOOO_dataout; + wire_nl100l1lO_dataout <= nlOiiOii WHEN nl11OOi1O = '1' ELSE wire_nl100O11i_dataout; + wire_nl100l1O_dataout <= ni0li0l WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl1000lO; + wire_nl100l1Oi_dataout <= nlOiiOil WHEN nl11OOi1O = '1' ELSE wire_nl100O11l_dataout; + wire_nl100l1Ol_dataout <= nlOiiOiO WHEN nl11OOi1O = '1' ELSE wire_nl100O11O_dataout; + wire_nl100l1OO_dataout <= nlOiiOli WHEN nl11OOi1O = '1' ELSE wire_nl100O10i_dataout; + wire_nl100li_dataout <= wire_nl1i11l_o AND NOT(wire_niO01O0O_dataout); + wire_nl100li0i_dataout <= nlOil1Ol WHEN nl11OOi1O = '1' ELSE wire_nl100O0il_dataout; + wire_nl100li0l_dataout <= nlOil1OO WHEN nl11OOi1O = '1' ELSE wire_nl100O0iO_dataout; + wire_nl100li0O_dataout <= nlOil01i WHEN nl11OOi1O = '1' ELSE wire_nl100O0li_dataout; + wire_nl100li1i_dataout <= nlOil1ll WHEN nl11OOi1O = '1' ELSE wire_nl100O00l_dataout; + wire_nl100li1l_dataout <= nlOil1lO WHEN nl11OOi1O = '1' ELSE wire_nl100O00O_dataout; + wire_nl100li1O_dataout <= nlOil1Oi WHEN nl11OOi1O = '1' ELSE wire_nl100O0ii_dataout; + wire_nl100lii_dataout <= ni0liiO WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl100i1i; + wire_nl100liii_dataout <= wire_nl10ii01O_dataout WHEN nl11OOi1O = '1' ELSE wire_nl100O0ll_dataout; + wire_nl100liil_dataout <= nlOil01O WHEN nl11OOi1O = '1' ELSE wire_nl100O0lO_dataout; + wire_nl100liiO_dataout <= nlOil00i WHEN nl11OOi1O = '1' ELSE wire_nl100O0Oi_dataout; + wire_nl100lil_dataout <= ni0lili WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl100i1l; + wire_nl100lili_dataout <= nlOil00l WHEN nl11OOi1O = '1' ELSE wire_nl100O0Ol_dataout; + wire_nl100lill_dataout <= nlOil00O WHEN nl11OOi1O = '1' ELSE wire_nl100O0OO_dataout; + wire_nl100lilO_dataout <= nlOil0ii WHEN nl11OOi1O = '1' ELSE wire_nl100Oi1i_dataout; + wire_nl100liO_dataout <= ni0lill WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl100i1O; + wire_nl100liOi_dataout <= nlOil0il WHEN nl11OOi1O = '1' ELSE wire_nl100Oi1l_dataout; + wire_nl100liOl_dataout <= nlOil0iO WHEN nl11OOi1O = '1' ELSE wire_nl100Oi1O_dataout; + wire_nl100liOO_dataout <= nlOil0li WHEN nl11OOi1O = '1' ELSE wire_nl100Oi0i_dataout; + wire_nl100ll_dataout <= wire_nl1i11O_o AND NOT(wire_niO01O0O_dataout); + wire_nl100ll0i_dataout <= nlOil0Ol WHEN nl11OOi1O = '1' ELSE wire_nl100Oiil_dataout; + wire_nl100ll0l_dataout <= nlOil0OO WHEN nl11OOi1O = '1' ELSE wire_nl100OiiO_dataout; + wire_nl100ll0O_dataout <= nlOili1i WHEN nl11OOi1O = '1' ELSE wire_nl100Oili_dataout; + wire_nl100ll1i_dataout <= ((((wire_w_lg_niOi1i00O59724w(0) AND wire_nl1000i_w_lg_nlOili1i59697w(0)) AND niOi10lll) AND niOi10lli) XOR nlOil0ll) WHEN nl11OOi1O = '1' ELSE wire_nl100Oi0l_dataout; + wire_nl100ll1l_dataout <= nlOil0lO WHEN nl11OOi1O = '1' ELSE wire_nl100Oi0O_dataout; + wire_nl100ll1O_dataout <= nlOil0Oi WHEN nl11OOi1O = '1' ELSE wire_nl100Oiii_dataout; + wire_nl100lli_dataout <= ni0lilO WHEN wire_w_lg_niOO1iOOO8222w(0) = '1' ELSE nl100i0i; + wire_nl100llii_dataout <= nlOili1l WHEN nl11OOi1O = '1' ELSE wire_nl100Oill_dataout; + wire_nl100llil_dataout <= wire_nl10ii0ii_dataout WHEN nl11OOi1O = '1' ELSE wire_nl100OilO_dataout; + wire_nl100lliO_dataout <= nlOi0lll WHEN nl11OOi1l = '1' ELSE wire_nl100OiOi_dataout; + wire_nl100llli_dataout <= nlOi0llO WHEN nl11OOi1l = '1' ELSE wire_nl100OiOl_dataout; + wire_nl100llll_dataout <= nlOi0lOi WHEN nl11OOi1l = '1' ELSE wire_nl100OiOO_dataout; + wire_nl100lllO_dataout <= nlOi0lOl WHEN nl11OOi1l = '1' ELSE wire_nl100Ol1i_dataout; + wire_nl100llOi_dataout <= nlOi0lOO WHEN nl11OOi1l = '1' ELSE wire_nl100Ol1l_dataout; + wire_nl100llOl_dataout <= nlOi0O1i WHEN nl11OOi1l = '1' ELSE wire_nl100Ol1O_dataout; + wire_nl100llOO_dataout <= nlOi0O1l WHEN nl11OOi1l = '1' ELSE wire_nl100Ol0i_dataout; + wire_nl100lO_dataout <= wire_nl1i10i_o AND NOT(wire_niO01O0O_dataout); + wire_nl100lO0i_dataout <= nlOi0O0O WHEN nl11OOi1l = '1' ELSE wire_nl100Olil_dataout; + wire_nl100lO0l_dataout <= nlOi0Oii WHEN nl11OOi1l = '1' ELSE wire_nl100OliO_dataout; + wire_nl100lO0O_dataout <= nlOi0Oil WHEN nl11OOi1l = '1' ELSE wire_nl100Olli_dataout; + wire_nl100lO1i_dataout <= nlOi0O1O WHEN nl11OOi1l = '1' ELSE wire_nl100Ol0l_dataout; + wire_nl100lO1l_dataout <= nlOi0O0i WHEN nl11OOi1l = '1' ELSE wire_nl100Ol0O_dataout; + wire_nl100lO1O_dataout <= nlOi0O0l WHEN nl11OOi1l = '1' ELSE wire_nl100Olii_dataout; + wire_nl100lOii_dataout <= nlOi0OiO WHEN nl11OOi1l = '1' ELSE wire_nl100Olll_dataout; + wire_nl100lOil_dataout <= nlOi0Oli WHEN nl11OOi1l = '1' ELSE wire_nl100OllO_dataout; + wire_nl100lOiO_dataout <= nlOi0Oll WHEN nl11OOi1l = '1' ELSE wire_nl100OlOi_dataout; + wire_nl100lOli_dataout <= nlOi0OlO WHEN nl11OOi1l = '1' ELSE wire_nl100OlOl_dataout; + wire_nl100lOll_dataout <= nlOi0OOi WHEN nl11OOi1l = '1' ELSE wire_nl100OlOO_dataout; + wire_nl100lOlO_dataout <= nlOi0OOl WHEN nl11OOi1l = '1' ELSE wire_nl100OO1i_dataout; + wire_nl100lOOi_dataout <= nlOi0OOO WHEN nl11OOi1l = '1' ELSE wire_nl100OO1l_dataout; + wire_nl100lOOl_dataout <= nlOii11i WHEN nl11OOi1l = '1' ELSE wire_nl100OO1O_dataout; + wire_nl100lOOO_dataout <= nlOii11l WHEN nl11OOi1l = '1' ELSE wire_nl100OO0i_dataout; + wire_nl100O00i_dataout <= nlOii00O WHEN nl11OOi1l = '1' ELSE wire_nl10i11il_dataout; + wire_nl100O00l_dataout <= nlOii0ii WHEN nl11OOi1l = '1' ELSE wire_nl10i11iO_dataout; + wire_nl100O00O_dataout <= nlOii0il WHEN nl11OOi1l = '1' ELSE wire_nl10i11li_dataout; + wire_nl100O01i_dataout <= nlOii01O WHEN nl11OOi1l = '1' ELSE wire_nl10i110l_dataout; + wire_nl100O01l_dataout <= nlOii00i WHEN nl11OOi1l = '1' ELSE wire_nl10i110O_dataout; + wire_nl100O01O_dataout <= nlOii00l WHEN nl11OOi1l = '1' ELSE wire_nl10i11ii_dataout; + wire_nl100O0ii_dataout <= nlOii0iO WHEN nl11OOi1l = '1' ELSE wire_nl10i11ll_dataout; + wire_nl100O0il_dataout <= nlOii0li WHEN nl11OOi1l = '1' ELSE wire_nl10i11lO_dataout; + wire_nl100O0iO_dataout <= nlOii0ll WHEN nl11OOi1l = '1' ELSE wire_nl10i11Oi_dataout; + wire_nl100O0li_dataout <= nlOii0lO WHEN nl11OOi1l = '1' ELSE wire_nl10i11Ol_dataout; + wire_nl100O0ll_dataout <= nlOii0Oi WHEN nl11OOi1l = '1' ELSE wire_nl10i11OO_dataout; + wire_nl100O0lO_dataout <= nlOii0Ol WHEN nl11OOi1l = '1' ELSE wire_nl10i101i_dataout; + wire_nl100O0Oi_dataout <= nlOii0OO WHEN nl11OOi1l = '1' ELSE wire_nl10i101l_dataout; + wire_nl100O0Ol_dataout <= nlOiii1i WHEN nl11OOi1l = '1' ELSE wire_nl10i101O_dataout; + wire_nl100O0OO_dataout <= nlOiii1l WHEN nl11OOi1l = '1' ELSE wire_nl10i100i_dataout; + wire_nl100O10i_dataout <= nlOii10O WHEN nl11OOi1l = '1' ELSE wire_nl100OOil_dataout; + wire_nl100O10l_dataout <= nlOii1ii WHEN nl11OOi1l = '1' ELSE wire_nl100OOiO_dataout; + wire_nl100O10O_dataout <= nlOii1il WHEN nl11OOi1l = '1' ELSE wire_nl100OOli_dataout; + wire_nl100O11i_dataout <= nlOii11O WHEN nl11OOi1l = '1' ELSE wire_nl100OO0l_dataout; + wire_nl100O11l_dataout <= nlOii10i WHEN nl11OOi1l = '1' ELSE wire_nl100OO0O_dataout; + wire_nl100O11O_dataout <= nlOii10l WHEN nl11OOi1l = '1' ELSE wire_nl100OOii_dataout; + wire_nl100O1ii_dataout <= nlOii1iO WHEN nl11OOi1l = '1' ELSE wire_nl100OOll_dataout; + wire_nl100O1il_dataout <= nlOii1li WHEN nl11OOi1l = '1' ELSE wire_nl100OOlO_dataout; + wire_nl100O1iO_dataout <= nlOii1ll WHEN nl11OOi1l = '1' ELSE wire_nl100OOOi_dataout; + wire_nl100O1li_dataout <= nlOii1lO WHEN nl11OOi1l = '1' ELSE wire_nl100OOOl_dataout; + wire_nl100O1ll_dataout <= nlOii1Oi WHEN nl11OOi1l = '1' ELSE wire_nl100OOOO_dataout; + wire_nl100O1lO_dataout <= nlOii1Ol WHEN nl11OOi1l = '1' ELSE wire_nl10i111i_dataout; + wire_nl100O1Oi_dataout <= nlOii1OO WHEN nl11OOi1l = '1' ELSE wire_nl10i111l_dataout; + wire_nl100O1Ol_dataout <= nlOii01i WHEN nl11OOi1l = '1' ELSE wire_nl10i111O_dataout; + wire_nl100O1OO_dataout <= nlOii01l WHEN nl11OOi1l = '1' ELSE wire_nl10i110i_dataout; + wire_nl100Oi_dataout <= wire_nl1i10l_o AND NOT(wire_niO01O0O_dataout); + wire_nl100Oi0i_dataout <= nlOiii0O WHEN nl11OOi1l = '1' ELSE wire_nl10i10il_dataout; + wire_nl100Oi0l_dataout <= nlOiiiii WHEN nl11OOi1l = '1' ELSE wire_nl10i10iO_dataout; + wire_nl100Oi0O_dataout <= nlOiiiil WHEN nl11OOi1l = '1' ELSE wire_nl10i10li_dataout; + wire_nl100Oi1i_dataout <= nlOiii1O WHEN nl11OOi1l = '1' ELSE wire_nl10i100l_dataout; + wire_nl100Oi1l_dataout <= nlOiii0i WHEN nl11OOi1l = '1' ELSE wire_nl10i100O_dataout; + wire_nl100Oi1O_dataout <= nlOiii0l WHEN nl11OOi1l = '1' ELSE wire_nl10i10ii_dataout; + wire_nl100Oiii_dataout <= nlOiiiiO WHEN nl11OOi1l = '1' ELSE wire_nl10i10ll_dataout; + wire_nl100Oiil_dataout <= nlOiiili WHEN nl11OOi1l = '1' ELSE wire_nl10i10lO_dataout; + wire_nl100OiiO_dataout <= nlOiiill WHEN nl11OOi1l = '1' ELSE wire_nl10i10Oi_dataout; + wire_nl100Oil_dataout <= wire_nl100OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl100Oili_dataout <= nlOiiilO WHEN nl11OOi1l = '1' ELSE wire_nl10i10Ol_dataout; + wire_nl100Oill_dataout <= nlOiiiOi WHEN nl11OOi1l = '1' ELSE wire_nl10i10OO_dataout; + wire_nl100OilO_dataout <= nlOiiiOl WHEN nl11OOi1l = '1' ELSE wire_nl10i1i1i_dataout; + wire_nl100OiO_dataout <= wire_nl100OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl100OiOi_dataout <= nlOi0l1O WHEN nl11OOi1i = '1' ELSE wire_nl10i1i1l_dataout; + wire_nl100OiOl_dataout <= nlOi0l0i WHEN nl11OOi1i = '1' ELSE wire_nl10i1i1O_dataout; + wire_nl100OiOO_dataout <= nlOi0l0l WHEN nl11OOi1i = '1' ELSE wire_nl10i1i0i_dataout; + wire_nl100Ol_dataout <= wire_nl1i10O_o AND NOT(wire_niO01O0O_dataout); + wire_nl100Ol0i_dataout <= nlOi0liO WHEN nl11OOi1i = '1' ELSE wire_nl10i1iil_dataout; + wire_nl100Ol0l_dataout <= nlOi0lli WHEN nl11OOi1i = '1' ELSE wire_nl10i1iiO_dataout; + wire_nl100Ol0O_dataout <= nlOi0ili WHEN nl11OOi1i = '1' ELSE wire_nl10i1ili_dataout; + wire_nl100Ol1i_dataout <= nlOi0l0O WHEN nl11OOi1i = '1' ELSE wire_nl10i1i0l_dataout; + wire_nl100Ol1l_dataout <= nlOi0lii WHEN nl11OOi1i = '1' ELSE wire_nl10i1i0O_dataout; + wire_nl100Ol1O_dataout <= nlOi0lil WHEN nl11OOi1i = '1' ELSE wire_nl10i1iii_dataout; + wire_nl100Oli_dataout <= wire_nl100OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl100Olii_dataout <= nlOi0ill WHEN nl11OOi1i = '1' ELSE wire_nl10i1ill_dataout; + wire_nl100Olil_dataout <= nlOi0ilO WHEN nl11OOi1i = '1' ELSE wire_nl10i1ilO_dataout; + wire_nl100OliO_dataout <= nlOi0iOi WHEN nl11OOi1i = '1' ELSE wire_nl10i1iOi_dataout; + wire_nl100Oll_dataout <= wire_nl10i11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl100Olli_dataout <= nlOi0iOl WHEN nl11OOi1i = '1' ELSE wire_nl10i1iOl_dataout; + wire_nl100Olll_dataout <= nlOi0iOO WHEN nl11OOi1i = '1' ELSE wire_nl10i1iOO_dataout; + wire_nl100OllO_dataout <= nlOi0l1i WHEN nl11OOi1i = '1' ELSE wire_nl10i1l1i_dataout; + wire_nl100OlO_dataout <= wire_nl10i11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl100OlOi_dataout <= nlOi0l1l WHEN nl11OOi1i = '1' ELSE wire_nl10i1l1l_dataout; + wire_nl100OlOl_dataout <= nlOi0i1l WHEN nl11OOi1i = '1' ELSE wire_nl10i1l1O_dataout; + wire_nl100OlOO_dataout <= nlOi0i1O WHEN nl11OOi1i = '1' ELSE wire_nl10i1l0i_dataout; + wire_nl100OO_dataout <= wire_nl1i1ii_o AND NOT(wire_niO01O0O_dataout); + wire_nl100OO0i_dataout <= nlOi0iii WHEN nl11OOi1i = '1' ELSE wire_nl10i1lil_dataout; + wire_nl100OO0l_dataout <= nlOi0iil WHEN nl11OOi1i = '1' ELSE wire_nl10i1liO_dataout; + wire_nl100OO0O_dataout <= nlOi0iiO WHEN nl11OOi1i = '1' ELSE wire_nl10i1lli_dataout; + wire_nl100OO1i_dataout <= nlOi0i0i WHEN nl11OOi1i = '1' ELSE wire_nl10i1l0l_dataout; + wire_nl100OO1l_dataout <= nlOi0i0l WHEN nl11OOi1i = '1' ELSE wire_nl10i1l0O_dataout; + wire_nl100OO1O_dataout <= nlOi0i0O WHEN nl11OOi1i = '1' ELSE wire_nl10i1lii_dataout; + wire_nl100OOi_dataout <= nl10i1OO WHEN niOO1l11i = '1' ELSE nl10i10i; + wire_nl100OOii_dataout <= nlOi00iO WHEN nl11OOi1i = '1' ELSE wire_nl10i1lll_dataout; + wire_nl100OOil_dataout <= nlOi00li WHEN nl11OOi1i = '1' ELSE wire_nl10i1llO_dataout; + wire_nl100OOiO_dataout <= nlOi00ll WHEN nl11OOi1i = '1' ELSE wire_nl10i1lOi_dataout; + wire_nl100OOl_dataout <= nl10i01i WHEN niOO1l11i = '1' ELSE nl100O1O; + wire_nl100OOli_dataout <= nlOi00lO WHEN nl11OOi1i = '1' ELSE wire_nl10i1lOl_dataout; + wire_nl100OOll_dataout <= nlOi00Oi WHEN nl11OOi1i = '1' ELSE wire_nl10i1lOO_dataout; + wire_nl100OOlO_dataout <= nlOi00Ol WHEN nl11OOi1i = '1' ELSE wire_nl10i1O1i_dataout; + wire_nl100OOO_dataout <= nl10i01l WHEN niOO1l11i = '1' ELSE nl100O0i; + wire_nl100OOOi_dataout <= nlOi00OO WHEN nl11OOi1i = '1' ELSE wire_nl10i1O1l_dataout; + wire_nl100OOOl_dataout <= nlOi0i1i WHEN nl11OOi1i = '1' ELSE wire_nl10i1O1O_dataout; + wire_nl100OOOO_dataout <= nlOii1Oi WHEN nl11OOi1i = '1' ELSE wire_nl10i1O0i_dataout; + wire_nl101000i_dataout <= wire_nl10100ii_dataout AND NOT(niOi10iOl); + wire_nl101000l_dataout <= wire_nl10100il_dataout AND NOT(niOi10iOl); + wire_nl101000O_dataout <= wire_nl10100iO_dataout OR niOi10iOl; + wire_nl101001i_dataout <= wire_w_lg_niOi10ill59981w(0) OR niOi10iOl; + wire_nl101001O_dataout <= niOi10ilO AND NOT(niOi10iOl); + wire_nl10100i_dataout <= nl10101l AND NOT(wire_niO01O0O_dataout); + wire_nl10100ii_dataout <= wire_nl10100li_dataout AND NOT(niOi10ilO); + wire_nl10100il_dataout <= niOi10l1i AND NOT(niOi10ilO); + wire_nl10100iO_dataout <= wire_nl10100ll_dataout AND NOT(niOi10ilO); + wire_nl10100l_dataout <= nl1011Oi AND NOT(wire_niO01O0O_dataout); + wire_nl10100li_dataout <= niOi10lOl AND NOT(niOi10l1i); + wire_nl10100ll_dataout <= wire_w_lg_niOi10lOl59979w(0) AND NOT(niOi10l1i); + wire_nl101010i_dataout <= nl11OO0Ol AND NOT(niOi10ili); + wire_nl101010l_dataout <= nl11OO0OO AND NOT(niOi10ili); + wire_nl101010O_dataout <= nl11OOi1i AND NOT(niOi10ili); + wire_nl101011i_dataout <= nl11OO0ll AND NOT(niOi10ili); + wire_nl101011l_dataout <= nl11OO0lO AND NOT(niOi10ili); + wire_nl101011O_dataout <= nl11OO0Oi AND NOT(niOi10ili); + wire_nl10101i_dataout <= nl10101O AND NOT(wire_niO01O0O_dataout); + wire_nl10101ii_dataout <= nl11OOi1l AND NOT(niOi10ili); + wire_nl10101il_dataout <= nl11OOi1O OR niOi10ili; + wire_nl10101li_dataout <= wire_nl10101Oi_dataout AND NOT(niOi10iOl); + wire_nl10101ll_dataout <= nlOili0O AND NOT(niOi10iOl); + wire_nl10101lO_dataout <= wire_nl10101Ol_dataout OR niOi10iOl; + wire_nl10101Oi_dataout <= nl11OOi0i AND NOT(nlOili0O); + wire_nl10101Ol_dataout <= wire_nlill0Oll_w_lg_nl11OOi0i59982w(0) AND NOT(nlOili0O); + wire_nl10101OO_dataout <= niOi10ill AND NOT(niOi10iOl); + wire_nl1010i0i_dataout <= nl11OO0ll AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010i0l_dataout <= nl11OO0lO AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010i0O_dataout <= nl11OO0Oi AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010i1l_dataout <= nl11OO0iO AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010i1O_dataout <= nl11OO0li AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010ii_dataout <= wire_nl1010iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1010iii_dataout <= nl11OO0Ol AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010iil_dataout <= nl11OO0OO AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010iiO_dataout <= nl11OOi1i AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010il_dataout <= wire_nl1010lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1010ili_dataout <= nl11OOi1l AND NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1010ill_dataout <= nl11OOi1O OR wire_w_lg_niOi10iOO59973w(0); + wire_nl1010ilO_dataout <= nl11OO0il WHEN niOi10lil = '1' ELSE wire_nl1010O1O_dataout; + wire_nl1010iO_dataout <= wire_niOOO0O_w_lg_nl10101O8261w(0) WHEN (wire_w_lg_niOO1iOll8262w(0) AND (tl_app_inta_sts XOR nl10100O)) = '1' ELSE nl10101O; + wire_nl1010iOi_dataout <= wire_nl101i1ii_dataout WHEN niOi10lil = '1' ELSE wire_nl1010O0i_dataout; + wire_nl1010iOl_dataout <= wire_nl101i1il_dataout WHEN niOi10lil = '1' ELSE nl11OO0iO; + wire_nl1010iOO_dataout <= wire_nl1010liO_dataout AND NOT(niOi10lil); + wire_nl1010l0i_dataout <= wire_nl1010lOi_dataout AND NOT(niOi10lil); + wire_nl1010l0l_dataout <= wire_nl1010lOl_dataout AND NOT(niOi10lil); + wire_nl1010l0O_dataout <= wire_nl1010lOO_dataout AND NOT(niOi10lil); + wire_nl1010l1i_dataout <= wire_nl1010lli_dataout OR niOi10lil; + wire_nl1010l1l_dataout <= wire_nl1010lll_dataout AND NOT(niOi10lil); + wire_nl1010l1O_dataout <= wire_nl1010llO_dataout AND NOT(niOi10lil); + wire_nl1010lii_dataout <= wire_nl1010O1i_dataout AND NOT(niOi10lil); + wire_nl1010lil_dataout <= wire_nl1010O1l_dataout AND NOT(niOi10lil); + wire_nl1010liO_dataout <= nl11OO0li WHEN niOi10l1l = '1' ELSE wire_nl1010O0O_dataout; + wire_nl1010lli_dataout <= nl11OO0ll WHEN niOi10l1l = '1' ELSE wire_nl1010Oii_dataout; + wire_nl1010lll_dataout <= nl11OO0lO WHEN niOi10l1l = '1' ELSE wire_nl1010Oil_dataout; + wire_nl1010llO_dataout <= nl11OO0Oi WHEN niOi10l1l = '1' ELSE wire_nl1010OiO_dataout; + wire_nl1010lO_dataout <= nl10100O WHEN niOO1iOll = '1' ELSE tl_app_inta_sts; + wire_nl1010lOi_dataout <= nl11OO0Ol WHEN niOi10l1l = '1' ELSE wire_nl1010Oli_dataout; + wire_nl1010lOl_dataout <= nl11OO0OO WHEN niOi10l1l = '1' ELSE wire_nl1010Oll_dataout; + wire_nl1010lOO_dataout <= nl11OOi1i WHEN niOi10l1l = '1' ELSE wire_nl1010OlO_dataout; + wire_nl1010O0i_dataout <= wire_nl1010O0l_dataout OR niOi10l1l; + wire_nl1010O0l_dataout <= wire_nl101i11l_dataout WHEN niOi10lii = '1' ELSE niOi10l1O; + wire_nl1010O0O_dataout <= nl11OO0li AND NOT(niOi10lii); + wire_nl1010O1i_dataout <= nl11OOi1l WHEN niOi10l1l = '1' ELSE wire_nl1010OOi_dataout; + wire_nl1010O1l_dataout <= nl11OOi1O WHEN niOi10l1l = '1' ELSE wire_nl1010OOl_dataout; + wire_nl1010O1O_dataout <= nl11OO0il WHEN niOi10l1l = '1' ELSE wire_nl1010OOO_dataout; + wire_nl1010Oii_dataout <= nl11OO0ll AND NOT(niOi10lii); + wire_nl1010Oil_dataout <= nl11OO0lO AND NOT(niOi10lii); + wire_nl1010OiO_dataout <= nl11OO0Oi AND NOT(niOi10lii); + wire_nl1010Oli_dataout <= nl11OO0Ol AND NOT(niOi10lii); + wire_nl1010Oll_dataout <= wire_nl101i11O_dataout WHEN niOi10lii = '1' ELSE nl11OO0OO; + wire_nl1010OlO_dataout <= wire_nl101i10i_dataout WHEN niOi10lii = '1' ELSE nl11OOi1i; + wire_nl1010OO_dataout <= (nl101iiO XOR nl101iii) AND NOT(wire_niO01l0O_dataout); + wire_nl1010OOi_dataout <= nlOili1i WHEN niOi10lii = '1' ELSE nl11OOi1l; + wire_nl1010OOl_dataout <= nl11OOi1O AND NOT(niOi10lii); + wire_nl1010OOO_dataout <= nl11OO0il OR niOi10lii; + wire_nl101100i_dataout <= wire_nl101iiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101100l_dataout <= wire_nl101iiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101100O_dataout <= wire_nl101il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101101i_dataout <= wire_nl101iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101101l_dataout <= wire_nl101iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101101O_dataout <= wire_nl101iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110i_dataout <= nl11OOlO WHEN niOO1iOli = '1' ELSE nl0ilOiOi; + wire_nl10110ii_dataout <= wire_nl101il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110il_dataout <= wire_nl101il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110iO_dataout <= wire_nl101il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110li_dataout <= wire_nl101il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110ll_dataout <= wire_nl101il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110lO_dataout <= wire_nl101ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110Oi_dataout <= wire_nl101ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110Ol_dataout <= wire_nl101iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10110OO_dataout <= wire_nl101illi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101110i_dataout <= wire_nl1011lil_o AND NOT(wire_niO01O0O_dataout); + wire_nl101110l_dataout <= wire_nl1011lli_o AND NOT(wire_niO01O0O_dataout); + wire_nl101110O_dataout <= wire_nl1011lll_o AND NOT(wire_niO01O0O_dataout); + wire_nl101111i_dataout <= wire_nl1011l0i_o AND NOT(wire_niO01O0O_dataout); + wire_nl101111l_dataout <= wire_nl1011l0l_o AND NOT(wire_niO01O0O_dataout); + wire_nl101111O_dataout <= wire_nl1011l0O_o AND NOT(wire_niO01O0O_dataout); + wire_nl10111ii_dataout <= wire_nl1011llO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10111il_dataout <= wire_nl1011lOl_o OR wire_niO01O0O_dataout; + wire_nl10111iO_dataout <= wire_nl101i0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10111li_dataout <= wire_nl101ii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10111ll_dataout <= wire_nl101ii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10111lO_dataout <= wire_nl101iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10111Oi_dataout <= wire_nl101iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10111Ol_dataout <= wire_nl101iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10111OO_dataout <= wire_nl101iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011i0i_dataout <= wire_nl101ilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011i0l_dataout <= wire_nl101ilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011i0O_dataout <= wire_nl101iO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011i1i_dataout <= wire_nl101illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011i1l_dataout <= wire_nl101illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011i1O_dataout <= wire_nl101ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011ii_dataout <= wire_nl1011il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011iii_dataout <= wire_nl101iO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011iil_dataout <= wire_nl101iO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011iiO_dataout <= wire_nl101iO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011il_dataout <= wire_nl1000i_w_lg_nl1011li8265w(0) WHEN (nl10101l XOR nl1011OO) = '1' ELSE nl1011li; + wire_nl1011ili_dataout <= wire_nl101iO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011ill_dataout <= wire_nl101iO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1011lO_dataout <= nl1011OO AND NOT(wire_niO01l0O_dataout); + wire_nl1011lOO_dataout <= niOi10l1O OR NOT(wire_w_lg_niOi10iOO59973w(0)); + wire_nl1011O0i_dataout <= wire_nlill0Oll_w_lg_nl11OOi0i59982w(0) WHEN niOi10ili = '1' ELSE nl11OOi1O; + wire_nl1011O0O_dataout <= wire_nl1011OOO_dataout AND NOT(niOi10iOl); + wire_nl1011O1i_dataout <= wire_nl1011O1O_dataout AND NOT(niOi10iOl); + wire_nl1011O1l_dataout <= wire_nl1011O0i_dataout OR niOi10iOl; + wire_nl1011O1O_dataout <= nl11OOi0i WHEN niOi10ili = '1' ELSE nl11OO0lO; + wire_nl1011Oii_dataout <= wire_nl101011i_dataout AND NOT(niOi10iOl); + wire_nl1011Oil_dataout <= wire_nl101011l_dataout AND NOT(niOi10iOl); + wire_nl1011OiO_dataout <= wire_nl101011O_dataout AND NOT(niOi10iOl); + wire_nl1011Ol_dataout <= nl10110O AND NOT(wire_niO01l0O_dataout); + wire_nl1011Oli_dataout <= wire_nl101010i_dataout AND NOT(niOi10iOl); + wire_nl1011Oll_dataout <= wire_nl101010l_dataout AND NOT(niOi10iOl); + wire_nl1011OlO_dataout <= wire_nl101010O_dataout AND NOT(niOi10iOl); + wire_nl1011OOi_dataout <= wire_nl10101ii_dataout AND NOT(niOi10iOl); + wire_nl1011OOl_dataout <= wire_nl10101il_dataout OR niOi10iOl; + wire_nl1011OOO_dataout <= nl11OO0li AND NOT(niOi10ili); + wire_nl101i00i_dataout <= nl11OO00O AND NOT((wire_nilOOO0i_w_lg_dataout47830w(0) OR niOi1i1OO)); + wire_nl101i01O_dataout <= wire_nl101i00i_dataout OR niOi10l0O; + wire_nl101i0i_dataout <= nl101iii AND NOT(wire_niO01O0O_dataout); + wire_nl101i0lO_dataout <= (wire_nl10ii1lO_w_lg_dataout59872w(0) OR (wire_nl10ii1lO_w_lg_dataout59873w(0) AND wire_w_lg_niOi10lOl59875w(0))) WHEN nl11OOi1O = '1' ELSE nl11OOi0i; + wire_nl101i0O_dataout <= nl1010Ol AND NOT(wire_niO01O0O_dataout); + wire_nl101i10i_dataout <= wire_nl10ii1lO_dataout AND NOT(nlOili1i); + wire_nl101i11l_dataout <= niOi10l1i AND nlOili1i; + wire_nl101i11O_dataout <= wire_nl10ii1lO_w_lg_dataout59873w(0) AND NOT(nlOili1i); + wire_nl101i1ii_dataout <= nl11OO0ii OR niOi10l1O; + wire_nl101i1il_dataout <= nl11OO0iO OR NOT(niOi10l0i); + wire_nl101i1iO_dataout <= wire_nl101i1li_dataout OR (niOi10lOO AND (wire_nlill0Oll_w_lg_nl11Ol11i59967w(0) AND nlOili0l)); + wire_nl101i1li_dataout <= nl11Ol11i AND NOT(nl00lllil); + wire_nl101i1Oi_dataout <= wire_nl101i1Ol_dataout OR (niOi10lOO AND ((nl11OOi1O AND wire_nlill0Oll_w_lg_nl11OO00i59963w(0)) AND nlOili0l)); + wire_nl101i1Ol_dataout <= nl11OO00i AND NOT(nl00lllil); + wire_nl101ii0l_dataout <= wire_nl101l0li_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOii_dataout; + wire_nl101ii0O_dataout <= wire_nl101l0ll_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOil_dataout; + wire_nl101iiii_dataout <= wire_nl101l0lO_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOiO_dataout; + wire_nl101iiil_dataout <= wire_nl101l0Oi_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOli_dataout; + wire_nl101iiiO_dataout <= wire_nl101l0Ol_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOll_dataout; + wire_nl101iil_dataout <= nl101ili AND NOT(wire_niO01l0O_dataout); + wire_nl101iili_dataout <= wire_nl101l0OO_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOlO_dataout; + wire_nl101iill_dataout <= wire_nl101li1i_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOOi_dataout; + wire_nl101iilO_dataout <= wire_nl101li1l_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOOl_dataout; + wire_nl101iiOi_dataout <= wire_nl101li1O_dataout WHEN nl11OO00i = '1' ELSE wire_nl101iOOO_dataout; + wire_nl101iiOl_dataout <= wire_nl101li0i_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l11i_dataout; + wire_nl101iiOO_dataout <= wire_nl101li0l_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l11l_dataout; + wire_nl101il0i_dataout <= wire_nl101liiO_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l10O_dataout; + wire_nl101il0l_dataout <= wire_nl101lili_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1ii_dataout; + wire_nl101il0O_dataout <= wire_nl101lill_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1il_dataout; + wire_nl101il1i_dataout <= wire_nl101li0O_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l11O_dataout; + wire_nl101il1l_dataout <= wire_nl101liii_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l10i_dataout; + wire_nl101il1O_dataout <= wire_nl101liil_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l10l_dataout; + wire_nl101ilii_dataout <= wire_nl101lilO_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1iO_dataout; + wire_nl101ilil_dataout <= wire_nl101liOi_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1li_dataout; + wire_nl101iliO_dataout <= wire_nl101liOl_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1ll_dataout; + wire_nl101ill_dataout <= nl101iiO AND NOT(wire_niO01l0O_dataout); + wire_nl101illi_dataout <= wire_nl101liOO_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1lO_dataout; + wire_nl101illl_dataout <= wire_nl101ll1i_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1Oi_dataout; + wire_nl101illO_dataout <= wire_nl101ll1l_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1Ol_dataout; + wire_nl101ilO_dataout <= nl101i0l AND NOT(wire_niO01l0O_dataout); + wire_nl101ilOi_dataout <= wire_nl101ll1O_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l1OO_dataout; + wire_nl101ilOl_dataout <= wire_nl101ll0i_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l01i_dataout; + wire_nl101ilOO_dataout <= wire_nl101ll0l_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l01l_dataout; + wire_nl101iO0i_dataout <= wire_nl101lliO_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l00O_dataout; + wire_nl101iO0l_dataout <= wire_nl101llli_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l0ii_dataout; + wire_nl101iO0O_dataout <= wire_nl101llll_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l0il_dataout; + wire_nl101iO1i_dataout <= wire_nl101ll0O_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l01O_dataout; + wire_nl101iO1l_dataout <= wire_nl101llii_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l00i_dataout; + wire_nl101iO1O_dataout <= wire_nl101llil_dataout WHEN nl11OO00i = '1' ELSE wire_nl101l00l_dataout; + wire_nl101iOii_dataout <= nlOi0l1O WHEN niOi10l0l = '1' ELSE nl11OOi0l; + wire_nl101iOil_dataout <= nlOi0l0i WHEN niOi10l0l = '1' ELSE nl11OOi0O; + wire_nl101iOiO_dataout <= nlOi0l0l WHEN niOi10l0l = '1' ELSE nl11OOiii; + wire_nl101iOl_dataout <= wire_nl101l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101iOli_dataout <= nlOi0l0O WHEN niOi10l0l = '1' ELSE nl11OOiil; + wire_nl101iOll_dataout <= nlOi0lii WHEN niOi10l0l = '1' ELSE nl11OOiiO; + wire_nl101iOlO_dataout <= nlOi0lil WHEN niOi10l0l = '1' ELSE nl11OOili; + wire_nl101iOO_dataout <= wire_nl101l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101iOOi_dataout <= nlOi0liO WHEN niOi10l0l = '1' ELSE nl11OOill; + wire_nl101iOOl_dataout <= nlOi0lli WHEN niOi10l0l = '1' ELSE nl11OOilO; + wire_nl101iOOO_dataout <= nlOi0ili WHEN niOi10l0l = '1' ELSE nl11OOiOi; + wire_nl101l00i_dataout <= nlOi00lO WHEN niOi10l0l = '1' ELSE nl11OOO1l; + wire_nl101l00l_dataout <= nlOi00Oi WHEN niOi10l0l = '1' ELSE nl11OOO1O; + wire_nl101l00O_dataout <= nlOi00Ol WHEN niOi10l0l = '1' ELSE nl11OOO0i; + wire_nl101l01i_dataout <= nlOi00iO WHEN niOi10l0l = '1' ELSE nl11OOlOl; + wire_nl101l01l_dataout <= nlOi00li WHEN niOi10l0l = '1' ELSE nl11OOlOO; + wire_nl101l01O_dataout <= nlOi00ll WHEN niOi10l0l = '1' ELSE nl11OOO1i; + wire_nl101l0ii_dataout <= nlOi00OO WHEN niOi10l0l = '1' ELSE nl11OOO0l; + wire_nl101l0il_dataout <= nlOi0i1i WHEN niOi10l0l = '1' ELSE nl11OOO0O; + wire_nl101l0l_dataout <= nl101iOi WHEN niOO1iOlO = '1' ELSE niOO0liii; + wire_nl101l0li_dataout <= nlOii10l WHEN nlOili1O = '1' ELSE wire_nl101lllO_dataout; + wire_nl101l0ll_dataout <= nlOii10O WHEN nlOili1O = '1' ELSE wire_nl101llOi_dataout; + wire_nl101l0lO_dataout <= nlOii1ii WHEN nlOili1O = '1' ELSE wire_nl101llOl_dataout; + wire_nl101l0Oi_dataout <= nlOii1il WHEN nlOili1O = '1' ELSE wire_nl101llOO_dataout; + wire_nl101l0Ol_dataout <= nlOii1iO WHEN nlOili1O = '1' ELSE wire_nl101lO1i_dataout; + wire_nl101l0OO_dataout <= nlOii1li WHEN nlOili1O = '1' ELSE wire_nl101lO1l_dataout; + wire_nl101l10i_dataout <= nlOi0iOl WHEN niOi10l0l = '1' ELSE nl11OOl1l; + wire_nl101l10l_dataout <= nlOi0iOO WHEN niOi10l0l = '1' ELSE nl11OOl1O; + wire_nl101l10O_dataout <= nlOi0l1i WHEN niOi10l0l = '1' ELSE nl11OOl0i; + wire_nl101l11i_dataout <= nlOi0ill WHEN niOi10l0l = '1' ELSE nl11OOiOl; + wire_nl101l11l_dataout <= nlOi0ilO WHEN niOi10l0l = '1' ELSE nl11OOiOO; + wire_nl101l11O_dataout <= nlOi0iOi WHEN niOi10l0l = '1' ELSE nl11OOl1i; + wire_nl101l1i_dataout <= wire_nl1000i_w_lg_nl101ili8254w(0) WHEN (niOO0liii AND (wire_w_lg_niOO1iOlO8255w(0) AND (niOO0liii XOR nl101iOi))) = '1' ELSE nl101ili; + wire_nl101l1ii_dataout <= nlOi0l1l WHEN niOi10l0l = '1' ELSE nl11OOl0l; + wire_nl101l1il_dataout <= nlOi0i1l WHEN niOi10l0l = '1' ELSE nl11OOl0O; + wire_nl101l1iO_dataout <= nlOi0i1O WHEN niOi10l0l = '1' ELSE nl11OOlii; + wire_nl101l1li_dataout <= nlOi0i0i WHEN niOi10l0l = '1' ELSE nl11OOlil; + wire_nl101l1ll_dataout <= nlOi0i0l WHEN niOi10l0l = '1' ELSE nl11OOliO; + wire_nl101l1lO_dataout <= nlOi0i0O WHEN niOi10l0l = '1' ELSE nl11OOlli; + wire_nl101l1Oi_dataout <= nlOi0iii WHEN niOi10l0l = '1' ELSE nl11OOlll; + wire_nl101l1Ol_dataout <= nlOi0iil WHEN niOi10l0l = '1' ELSE nl11OOllO; + wire_nl101l1OO_dataout <= nlOi0iiO WHEN niOi10l0l = '1' ELSE nl11OOlOi; + wire_nl101li0i_dataout <= nlOi0OOi WHEN nlOili1O = '1' ELSE wire_nl101lO0O_dataout; + wire_nl101li0l_dataout <= nlOi0OOl WHEN nlOili1O = '1' ELSE wire_nl101lOii_dataout; + wire_nl101li0O_dataout <= nlOi0OOO WHEN nlOili1O = '1' ELSE wire_nl101lOil_dataout; + wire_nl101li1i_dataout <= nlOii1ll WHEN nlOili1O = '1' ELSE wire_nl101lO1O_dataout; + wire_nl101li1l_dataout <= nlOii1lO WHEN nlOili1O = '1' ELSE wire_nl101lO0i_dataout; + wire_nl101li1O_dataout <= nlOi0OlO WHEN nlOili1O = '1' ELSE wire_nl101lO0l_dataout; + wire_nl101liii_dataout <= nlOii11i WHEN nlOili1O = '1' ELSE wire_nl101lOiO_dataout; + wire_nl101liil_dataout <= nlOii11l WHEN nlOili1O = '1' ELSE wire_nl101lOli_dataout; + wire_nl101liiO_dataout <= nlOii11O WHEN nlOili1O = '1' ELSE wire_nl101lOll_dataout; + wire_nl101lili_dataout <= nlOii10i WHEN nlOili1O = '1' ELSE wire_nl101lOlO_dataout; + wire_nl101lill_dataout <= nlOi0O0i WHEN nlOili1O = '1' ELSE wire_nl101lOOi_dataout; + wire_nl101lilO_dataout <= nlOi0O0l WHEN nlOili1O = '1' ELSE wire_nl101lOOl_dataout; + wire_nl101liOi_dataout <= nlOi0O0O WHEN nlOili1O = '1' ELSE wire_nl101lOOO_dataout; + wire_nl101liOl_dataout <= nlOi0Oii WHEN nlOili1O = '1' ELSE wire_nl101O11i_dataout; + wire_nl101liOO_dataout <= nlOi0Oil WHEN nlOili1O = '1' ELSE wire_nl101O11l_dataout; + wire_nl101ll0i_dataout <= nlOi0lll WHEN nlOili1O = '1' ELSE wire_nl101O10O_dataout; + wire_nl101ll0l_dataout <= nlOi0llO WHEN nlOili1O = '1' ELSE wire_nl101O1ii_dataout; + wire_nl101ll0O_dataout <= nlOi0lOi WHEN nlOili1O = '1' ELSE wire_nl101O1il_dataout; + wire_nl101ll1i_dataout <= nlOi0OiO WHEN nlOili1O = '1' ELSE wire_nl101O11O_dataout; + wire_nl101ll1l_dataout <= nlOi0Oli WHEN nlOili1O = '1' ELSE wire_nl101O10i_dataout; + wire_nl101ll1O_dataout <= nlOi0Oll WHEN nlOili1O = '1' ELSE wire_nl101O10l_dataout; + wire_nl101llii_dataout <= nlOi0lOl WHEN nlOili1O = '1' ELSE wire_nl101O1iO_dataout; + wire_nl101llil_dataout <= nlOi0lOO WHEN nlOili1O = '1' ELSE wire_nl101O1li_dataout; + wire_nl101lliO_dataout <= nlOi0O1i WHEN nlOili1O = '1' ELSE wire_nl101O1ll_dataout; + wire_nl101llli_dataout <= nlOi0O1l WHEN nlOili1O = '1' ELSE wire_nl101O1lO_dataout; + wire_nl101llll_dataout <= nlOi0O1O WHEN nlOili1O = '1' ELSE wire_nl101O1Oi_dataout; + wire_nl101lllO_dataout <= nlOi00iO WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1Oii; + wire_nl101llOi_dataout <= nlOi00li WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1Oil; + wire_nl101llOl_dataout <= nlOi00ll WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1OiO; + wire_nl101llOO_dataout <= nlOi00lO WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1Oli; + wire_nl101lO0i_dataout <= nlOi0i1i WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1OOl; + wire_nl101lO0l_dataout <= nlOi0i1l WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1OOO; + wire_nl101lO0O_dataout <= nlOi0i1O WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi011i; + wire_nl101lO1i_dataout <= nlOi00Oi WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1Oll; + wire_nl101lO1l_dataout <= nlOi00Ol WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1OlO; + wire_nl101lO1O_dataout <= nlOi00OO WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi1OOi; + wire_nl101lOii_dataout <= nlOi0i0i WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi011l; + wire_nl101lOil_dataout <= nlOi0i0l WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi011O; + wire_nl101lOiO_dataout <= nlOi0i0O WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi010i; + wire_nl101lOli_dataout <= nlOi0iii WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi010l; + wire_nl101lOll_dataout <= nlOi0iil WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi010O; + wire_nl101lOlO_dataout <= nlOi0iiO WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01ii; + wire_nl101lOOi_dataout <= nlOi0ili WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01il; + wire_nl101lOOl_dataout <= nlOi0ill WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01iO; + wire_nl101lOOO_dataout <= nlOi0ilO WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01li; + wire_nl101O10i_dataout <= nlOi0l1i WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01Ol; + wire_nl101O10l_dataout <= nlOi0l1l WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01OO; + wire_nl101O10O_dataout <= nlOi0l1O WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi001i; + wire_nl101O11i_dataout <= nlOi0iOi WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01ll; + wire_nl101O11l_dataout <= nlOi0iOl WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01lO; + wire_nl101O11O_dataout <= nlOi0iOO WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi01Oi; + wire_nl101O1ii_dataout <= nlOi0l0i WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi001l; + wire_nl101O1il_dataout <= nlOi0l0l WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi001O; + wire_nl101O1iO_dataout <= nlOi0l0O WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi000i; + wire_nl101O1li_dataout <= nlOi0lii WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi000l; + wire_nl101O1ll_dataout <= nlOi0lil WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi000O; + wire_nl101O1lO_dataout <= nlOi0liO WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi00ii; + wire_nl101O1Oi_dataout <= nlOi0lli WHEN wire_nl10ii1lO_dataout = '1' ELSE nlOi00il; + wire_nl101Oi0i_dataout <= nl0i01O0O WHEN niOi10lOi = '1' ELSE wire_nl10010il_dataout; + wire_nl101Oi0l_dataout <= nl0i01Oii WHEN niOi10lOi = '1' ELSE wire_nl10010iO_dataout; + wire_nl101Oi0O_dataout <= nl0i01Oil WHEN niOi10lOi = '1' ELSE wire_nl10010li_dataout; + wire_nl101Oiii_dataout <= nl0i01OiO WHEN niOi10lOi = '1' ELSE wire_nl10010ll_dataout; + wire_nl101Oiil_dataout <= nl0i01Oli WHEN niOi10lOi = '1' ELSE wire_nl10010lO_dataout; + wire_nl101OiiO_dataout <= nl0i01Oll WHEN niOi10lOi = '1' ELSE wire_nl10010Oi_dataout; + wire_nl101Oili_dataout <= nl0i01OlO WHEN niOi10lOi = '1' ELSE wire_nl10010Ol_dataout; + wire_nl101Oill_dataout <= nl0i01OOi WHEN niOi10lOi = '1' ELSE wire_nl10010OO_dataout; + wire_nl101OilO_dataout <= nl0i01OOl WHEN niOi10lOi = '1' ELSE wire_nl1001i1i_dataout; + wire_nl101OiOi_dataout <= nl0i01OOO WHEN niOi10lOi = '1' ELSE wire_nl1001i1l_dataout; + wire_nl101OiOl_dataout <= nl0i0011i WHEN niOi10lOi = '1' ELSE wire_nl1001i1O_dataout; + wire_nl101OiOO_dataout <= nl0i0011l WHEN niOi10lOi = '1' ELSE wire_nl1001i0i_dataout; + wire_nl101Ol0i_dataout <= nl0i0010O WHEN niOi10lOi = '1' ELSE wire_nl1001iil_dataout; + wire_nl101Ol0l_dataout <= wire_nl1001iiO_dataout AND NOT(niOi10lOi); + wire_nl101Ol0O_dataout <= wire_nl1001ili_dataout AND NOT(niOi10lOi); + wire_nl101Ol1i_dataout <= nl0i0011O WHEN niOi10lOi = '1' ELSE wire_nl1001i0l_dataout; + wire_nl101Ol1l_dataout <= nl0i0010i WHEN niOi10lOi = '1' ELSE wire_nl1001i0O_dataout; + wire_nl101Ol1O_dataout <= nl0i0010l WHEN niOi10lOi = '1' ELSE wire_nl1001iii_dataout; + wire_nl101Olii_dataout <= wire_nl1001ill_dataout AND NOT(niOi10lOi); + wire_nl101Olil_dataout <= wire_nl0iO0l0i_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001ilO_dataout; + wire_nl101OliO_dataout <= wire_nl0iO0l0l_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001iOi_dataout; + wire_nl101Oll_dataout <= wire_nl10010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101Olli_dataout <= wire_nl0iO0l0O_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001iOl_dataout; + wire_nl101Olll_dataout <= wire_nl0iO0lii_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001iOO_dataout; + wire_nl101OllO_dataout <= wire_nl0iO0lil_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001l1i_dataout; + wire_nl101OlO_dataout <= wire_nl10010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101OlOi_dataout <= wire_nl0iO0liO_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001l1l_dataout; + wire_nl101OlOl_dataout <= wire_nl0iO0lli_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001l1O_dataout; + wire_nl101OlOO_dataout <= wire_nl0iO0lll_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001l0i_dataout; + wire_nl101OO0i_dataout <= wire_nl0iO0lOO_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001lil_dataout; + wire_nl101OO0l_dataout <= wire_nl0iO0O1i_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001liO_dataout; + wire_nl101OO0O_dataout <= nl0i001ii WHEN niOi10lOi = '1' ELSE wire_nl1001lli_dataout; + wire_nl101OO1i_dataout <= wire_nl0iO0llO_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001l0l_dataout; + wire_nl101OO1l_dataout <= wire_nl0iO0lOi_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001l0O_dataout; + wire_nl101OO1O_dataout <= wire_nl0iO0lOl_dataout WHEN niOi10lOi = '1' ELSE wire_nl1001lii_dataout; + wire_nl101OOi_dataout <= wire_nl1001ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101OOii_dataout <= nl0i001il WHEN niOi10lOi = '1' ELSE wire_nl1001lll_dataout; + wire_nl101OOil_dataout <= nl0i001iO WHEN niOi10lOi = '1' ELSE wire_nl1001llO_dataout; + wire_nl101OOiO_dataout <= nl0i001li WHEN niOi10lOi = '1' ELSE wire_nl1001lOi_dataout; + wire_nl101OOl_dataout <= wire_nl1001il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101OOli_dataout <= nl0i001ll WHEN niOi10lOi = '1' ELSE wire_nl1001lOl_dataout; + wire_nl101OOll_dataout <= nl0i001lO WHEN niOi10lOi = '1' ELSE wire_nl1001lOO_dataout; + wire_nl101OOlO_dataout <= nl0i001Oi WHEN niOi10lOi = '1' ELSE wire_nl1001O1i_dataout; + wire_nl101OOO_dataout <= wire_nl1001iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl101OOOi_dataout <= nl0i001Ol WHEN niOi10lOi = '1' ELSE wire_nl1001O1l_dataout; + wire_nl101OOOl_dataout <= nl0i001OO WHEN niOi10lOi = '1' ELSE wire_nl1001O1O_dataout; + wire_nl101OOOO_dataout <= nl0i0001i WHEN niOi10lOi = '1' ELSE wire_nl1001O0i_dataout; + wire_nl10i000i_dataout <= nlOiiiOi WHEN nl11OO0OO = '1' ELSE wire_nl10ii1il_dataout; + wire_nl10i000l_dataout <= nlOiiiOl WHEN nl11OO0OO = '1' ELSE wire_nl10ii1iO_dataout; + wire_nl10i000O_dataout <= nlOi0l1O WHEN nl11OO0Ol = '1' ELSE nlOi001i; + wire_nl10i001i_dataout <= nlOiiili WHEN nl11OO0OO = '1' ELSE wire_nl10ii10l_dataout; + wire_nl10i001l_dataout <= nlOiiill WHEN nl11OO0OO = '1' ELSE wire_nl10ii10O_dataout; + wire_nl10i001O_dataout <= nlOiiilO WHEN nl11OO0OO = '1' ELSE wire_nl10ii1ii_dataout; + wire_nl10i00ii_dataout <= nlOi0l0i WHEN nl11OO0Ol = '1' ELSE nlOi001l; + wire_nl10i00il_dataout <= nlOi0l0l WHEN nl11OO0Ol = '1' ELSE nlOi001O; + wire_nl10i00iO_dataout <= nlOi0l0O WHEN nl11OO0Ol = '1' ELSE nlOi000i; + wire_nl10i00l_dataout <= wire_nl10i0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10i00li_dataout <= nlOi0lii WHEN nl11OO0Ol = '1' ELSE nlOi000l; + wire_nl10i00ll_dataout <= nlOi0lil WHEN nl11OO0Ol = '1' ELSE nlOi000O; + wire_nl10i00lO_dataout <= nlOi0liO WHEN nl11OO0Ol = '1' ELSE nlOi00ii; + wire_nl10i00O_dataout <= wire_nl10i0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10i00Oi_dataout <= nlOi0lli WHEN nl11OO0Ol = '1' ELSE nlOi00il; + wire_nl10i00Ol_dataout <= nlOi0ili WHEN nl11OO0Ol = '1' ELSE nlOi01il; + wire_nl10i00OO_dataout <= nlOi0ill WHEN nl11OO0Ol = '1' ELSE nlOi01iO; + wire_nl10i010i_dataout <= nlOii0Oi WHEN nl11OO0OO = '1' ELSE wire_nl10i0Oil_dataout; + wire_nl10i010l_dataout <= nlOii0Ol WHEN nl11OO0OO = '1' ELSE wire_nl10i0OiO_dataout; + wire_nl10i010O_dataout <= nlOii0OO WHEN nl11OO0OO = '1' ELSE wire_nl10i0Oli_dataout; + wire_nl10i011i_dataout <= nlOii0li WHEN nl11OO0OO = '1' ELSE wire_nl10i0O0l_dataout; + wire_nl10i011l_dataout <= nlOii0ll WHEN nl11OO0OO = '1' ELSE wire_nl10i0O0O_dataout; + wire_nl10i011O_dataout <= nlOii0lO WHEN nl11OO0OO = '1' ELSE wire_nl10i0Oii_dataout; + wire_nl10i01ii_dataout <= nlOiii1i WHEN nl11OO0OO = '1' ELSE wire_nl10i0Oll_dataout; + wire_nl10i01il_dataout <= nlOiii1l WHEN nl11OO0OO = '1' ELSE wire_nl10i0OlO_dataout; + wire_nl10i01iO_dataout <= nlOiii1O WHEN nl11OO0OO = '1' ELSE wire_nl10i0OOi_dataout; + wire_nl10i01li_dataout <= nlOiii0i WHEN nl11OO0OO = '1' ELSE wire_nl10i0OOl_dataout; + wire_nl10i01ll_dataout <= nlOiii0l WHEN nl11OO0OO = '1' ELSE wire_nl10i0OOO_dataout; + wire_nl10i01lO_dataout <= nlOiii0O WHEN nl11OO0OO = '1' ELSE wire_nl10ii11i_dataout; + wire_nl10i01Oi_dataout <= nlOiiiii WHEN nl11OO0OO = '1' ELSE wire_nl10ii11l_dataout; + wire_nl10i01Ol_dataout <= nlOiiiil WHEN nl11OO0OO = '1' ELSE wire_nl10ii11O_dataout; + wire_nl10i01OO_dataout <= nlOiiiiO WHEN nl11OO0OO = '1' ELSE wire_nl10ii10i_dataout; + wire_nl10i0i_dataout <= wire_nl1i1ll_o AND NOT(wire_niO01O0O_dataout); + wire_nl10i0i0i_dataout <= nlOi0iOO WHEN nl11OO0Ol = '1' ELSE nlOi01Oi; + wire_nl10i0i0l_dataout <= nlOi0l1i WHEN nl11OO0Ol = '1' ELSE nlOi01Ol; + wire_nl10i0i0O_dataout <= nlOi0l1l WHEN nl11OO0Ol = '1' ELSE nlOi01OO; + wire_nl10i0i1i_dataout <= nlOi0ilO WHEN nl11OO0Ol = '1' ELSE nlOi01li; + wire_nl10i0i1l_dataout <= nlOi0iOi WHEN nl11OO0Ol = '1' ELSE nlOi01ll; + wire_nl10i0i1O_dataout <= nlOi0iOl WHEN nl11OO0Ol = '1' ELSE nlOi01lO; + wire_nl10i0ii_dataout <= wire_nl10i0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10i0iii_dataout <= nlOi0i1l WHEN nl11OO0Ol = '1' ELSE nlOi1OOO; + wire_nl10i0iil_dataout <= nlOi0i1O WHEN nl11OO0Ol = '1' ELSE nlOi011i; + wire_nl10i0iiO_dataout <= nlOi0i0i WHEN nl11OO0Ol = '1' ELSE nlOi011l; + wire_nl10i0il_dataout <= wire_nl10i0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10i0ili_dataout <= nlOi0i0l WHEN nl11OO0Ol = '1' ELSE nlOi011O; + wire_nl10i0ill_dataout <= nlOi0i0O WHEN nl11OO0Ol = '1' ELSE nlOi010i; + wire_nl10i0ilO_dataout <= nlOi0iii WHEN nl11OO0Ol = '1' ELSE nlOi010l; + wire_nl10i0iO_dataout <= wire_nl10ii1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10i0iOi_dataout <= nlOi0iil WHEN nl11OO0Ol = '1' ELSE nlOi010O; + wire_nl10i0iOl_dataout <= nlOi0iiO WHEN nl11OO0Ol = '1' ELSE nlOi01ii; + wire_nl10i0iOO_dataout <= nlOi00iO WHEN nl11OO0Ol = '1' ELSE nlOi1Oii; + wire_nl10i0l_dataout <= wire_nl1i1lO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10i0l0i_dataout <= nlOi00Oi WHEN nl11OO0Ol = '1' ELSE nlOi1Oll; + wire_nl10i0l0l_dataout <= nlOi00Ol WHEN nl11OO0Ol = '1' ELSE nlOi1OlO; + wire_nl10i0l0O_dataout <= nlOi00OO WHEN nl11OO0Ol = '1' ELSE nlOi1OOi; + wire_nl10i0l1i_dataout <= nlOi00li WHEN nl11OO0Ol = '1' ELSE nlOi1Oil; + wire_nl10i0l1l_dataout <= nlOi00ll WHEN nl11OO0Ol = '1' ELSE nlOi1OiO; + wire_nl10i0l1O_dataout <= nlOi00lO WHEN nl11OO0Ol = '1' ELSE nlOi1Oli; + wire_nl10i0li_dataout <= wire_nl10ii1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10i0lii_dataout <= nlOi0i1i WHEN nl11OO0Ol = '1' ELSE nlOi1OOl; + wire_nl10i0lil_dataout <= nlOi001i WHEN nl11OO0Ol = '1' ELSE nl11OOi0l; + wire_nl10i0liO_dataout <= nlOi001l WHEN nl11OO0Ol = '1' ELSE nl11OOi0O; + wire_nl10i0ll_dataout <= wire_niOOO0O_w_lg_nl10i1lO8203w(0) WHEN (wire_w_lg_niOO1l11O8198w(0) AND wire_w_lg_niOO1l11l8204w(0)) = '1' ELSE nl10i1lO; + wire_nl10i0lli_dataout <= nlOi001O WHEN nl11OO0Ol = '1' ELSE nl11OOiii; + wire_nl10i0lll_dataout <= nlOi000i WHEN nl11OO0Ol = '1' ELSE nl11OOiil; + wire_nl10i0llO_dataout <= nlOi000l WHEN nl11OO0Ol = '1' ELSE nl11OOiiO; + wire_nl10i0lOi_dataout <= nlOi000O WHEN nl11OO0Ol = '1' ELSE nl11OOili; + wire_nl10i0lOl_dataout <= nlOi00ii WHEN nl11OO0Ol = '1' ELSE nl11OOill; + wire_nl10i0lOO_dataout <= nlOi00il WHEN nl11OO0Ol = '1' ELSE nl11OOilO; + wire_nl10i0O_dataout <= wire_nl1i1Oi_o AND NOT(wire_niO01O0O_dataout); + wire_nl10i0O0i_dataout <= nlOi01ll WHEN nl11OO0Ol = '1' ELSE nl11OOl1i; + wire_nl10i0O0l_dataout <= nlOi01lO WHEN nl11OO0Ol = '1' ELSE nl11OOl1l; + wire_nl10i0O0O_dataout <= nlOi01Oi WHEN nl11OO0Ol = '1' ELSE nl11OOl1O; + wire_nl10i0O1i_dataout <= nlOi01il WHEN nl11OO0Ol = '1' ELSE nl11OOiOi; + wire_nl10i0O1l_dataout <= nlOi01iO WHEN nl11OO0Ol = '1' ELSE nl11OOiOl; + wire_nl10i0O1O_dataout <= nlOi01li WHEN nl11OO0Ol = '1' ELSE nl11OOiOO; + wire_nl10i0Oi_dataout <= tl_aer_msi_num(0) WHEN wire_w_lg_niOO1l11O8198w(0) = '1' ELSE nl10i1OO; + wire_nl10i0Oii_dataout <= nlOi01Ol WHEN nl11OO0Ol = '1' ELSE nl11OOl0i; + wire_nl10i0Oil_dataout <= nlOi01OO WHEN nl11OO0Ol = '1' ELSE nl11OOl0l; + wire_nl10i0OiO_dataout <= nlOi1OOO WHEN nl11OO0Ol = '1' ELSE nl11OOl0O; + wire_nl10i0Ol_dataout <= tl_aer_msi_num(1) WHEN wire_w_lg_niOO1l11O8198w(0) = '1' ELSE nl10i01i; + wire_nl10i0Oli_dataout <= nlOi011i WHEN nl11OO0Ol = '1' ELSE nl11OOlii; + wire_nl10i0Oll_dataout <= nlOi011l WHEN nl11OO0Ol = '1' ELSE nl11OOlil; + wire_nl10i0OlO_dataout <= nlOi011O WHEN nl11OO0Ol = '1' ELSE nl11OOliO; + wire_nl10i0OO_dataout <= tl_aer_msi_num(2) WHEN wire_w_lg_niOO1l11O8198w(0) = '1' ELSE nl10i01l; + wire_nl10i0OOi_dataout <= nlOi010i WHEN nl11OO0Ol = '1' ELSE nl11OOlli; + wire_nl10i0OOl_dataout <= nlOi010l WHEN nl11OO0Ol = '1' ELSE nl11OOlll; + wire_nl10i0OOO_dataout <= nlOi010O WHEN nl11OO0Ol = '1' ELSE nl11OOllO; + wire_nl10i100i_dataout <= nlOiii1l WHEN nl11OOi1i = '1' ELSE wire_nl10i01il_dataout; + wire_nl10i100l_dataout <= nlOiii1O WHEN nl11OOi1i = '1' ELSE wire_nl10i01iO_dataout; + wire_nl10i100O_dataout <= nlOiii0i WHEN nl11OOi1i = '1' ELSE wire_nl10i01li_dataout; + wire_nl10i101i_dataout <= nlOii0Ol WHEN nl11OOi1i = '1' ELSE wire_nl10i010l_dataout; + wire_nl10i101l_dataout <= nlOii0OO WHEN nl11OOi1i = '1' ELSE wire_nl10i010O_dataout; + wire_nl10i101O_dataout <= nlOiii1i WHEN nl11OOi1i = '1' ELSE wire_nl10i01ii_dataout; + wire_nl10i10ii_dataout <= nlOiii0l WHEN nl11OOi1i = '1' ELSE wire_nl10i01ll_dataout; + wire_nl10i10il_dataout <= nlOiii0O WHEN nl11OOi1i = '1' ELSE wire_nl10i01lO_dataout; + wire_nl10i10iO_dataout <= nlOiiiii WHEN nl11OOi1i = '1' ELSE wire_nl10i01Oi_dataout; + wire_nl10i10li_dataout <= nlOiiiil WHEN nl11OOi1i = '1' ELSE wire_nl10i01Ol_dataout; + wire_nl10i10ll_dataout <= nlOiiiiO WHEN nl11OOi1i = '1' ELSE wire_nl10i01OO_dataout; + wire_nl10i10lO_dataout <= nlOiiili WHEN nl11OOi1i = '1' ELSE wire_nl10i001i_dataout; + wire_nl10i10O_dataout <= nl10i1iO AND NOT(wire_niO01l0O_dataout); + wire_nl10i10Oi_dataout <= nlOiiill WHEN nl11OOi1i = '1' ELSE wire_nl10i001l_dataout; + wire_nl10i10Ol_dataout <= nlOiiilO WHEN nl11OOi1i = '1' ELSE wire_nl10i001O_dataout; + wire_nl10i10OO_dataout <= nlOiiiOi WHEN nl11OOi1i = '1' ELSE wire_nl10i000i_dataout; + wire_nl10i110i_dataout <= nlOii01l WHEN nl11OOi1i = '1' ELSE wire_nl10i1Oil_dataout; + wire_nl10i110l_dataout <= nlOii01O WHEN nl11OOi1i = '1' ELSE wire_nl10i1OiO_dataout; + wire_nl10i110O_dataout <= nlOii00i WHEN nl11OOi1i = '1' ELSE wire_nl10i1Oli_dataout; + wire_nl10i111i_dataout <= nlOii1Ol WHEN nl11OOi1i = '1' ELSE wire_nl10i1O0l_dataout; + wire_nl10i111l_dataout <= nlOii1OO WHEN nl11OOi1i = '1' ELSE wire_nl10i1O0O_dataout; + wire_nl10i111O_dataout <= nlOii01i WHEN nl11OOi1i = '1' ELSE wire_nl10i1Oii_dataout; + wire_nl10i11i_dataout <= nl10i01O WHEN niOO1l11i = '1' ELSE nl100O0l; + wire_nl10i11ii_dataout <= nlOii00l WHEN nl11OOi1i = '1' ELSE wire_nl10i1Oll_dataout; + wire_nl10i11il_dataout <= nlOii00O WHEN nl11OOi1i = '1' ELSE wire_nl10i1OlO_dataout; + wire_nl10i11iO_dataout <= nlOii0ii WHEN nl11OOi1i = '1' ELSE wire_nl10i1OOi_dataout; + wire_nl10i11l_dataout <= nl10i00i WHEN niOO1l11i = '1' ELSE nl100O0O; + wire_nl10i11li_dataout <= nlOii0il WHEN nl11OOi1i = '1' ELSE wire_nl10i1OOl_dataout; + wire_nl10i11ll_dataout <= nlOii0iO WHEN nl11OOi1i = '1' ELSE wire_nl10i1OOO_dataout; + wire_nl10i11lO_dataout <= nlOii0li WHEN nl11OOi1i = '1' ELSE wire_nl10i011i_dataout; + wire_nl10i11Oi_dataout <= nlOii0ll WHEN nl11OOi1i = '1' ELSE wire_nl10i011l_dataout; + wire_nl10i11Ol_dataout <= nlOii0lO WHEN nl11OOi1i = '1' ELSE wire_nl10i011O_dataout; + wire_nl10i11OO_dataout <= nlOii0Oi WHEN nl11OOi1i = '1' ELSE wire_nl10i010i_dataout; + wire_nl10i1i_dataout <= wire_nl1i1il_o AND NOT(wire_niO01O0O_dataout); + wire_nl10i1i0i_dataout <= nlOi001O WHEN nl11OO0OO = '1' ELSE wire_nl10i00il_dataout; + wire_nl10i1i0l_dataout <= nlOi000i WHEN nl11OO0OO = '1' ELSE wire_nl10i00iO_dataout; + wire_nl10i1i0O_dataout <= nlOi000l WHEN nl11OO0OO = '1' ELSE wire_nl10i00li_dataout; + wire_nl10i1i1i_dataout <= nlOiiiOl WHEN nl11OOi1i = '1' ELSE wire_nl10i000l_dataout; + wire_nl10i1i1l_dataout <= nlOi001i WHEN nl11OO0OO = '1' ELSE wire_nl10i000O_dataout; + wire_nl10i1i1O_dataout <= nlOi001l WHEN nl11OO0OO = '1' ELSE wire_nl10i00ii_dataout; + wire_nl10i1iii_dataout <= nlOi000O WHEN nl11OO0OO = '1' ELSE wire_nl10i00ll_dataout; + wire_nl10i1iil_dataout <= nlOi00ii WHEN nl11OO0OO = '1' ELSE wire_nl10i00lO_dataout; + wire_nl10i1iiO_dataout <= nlOi00il WHEN nl11OO0OO = '1' ELSE wire_nl10i00Oi_dataout; + wire_nl10i1il_dataout <= nl100Oii AND NOT(wire_niO01l0O_dataout); + wire_nl10i1ili_dataout <= nlOi01il WHEN nl11OO0OO = '1' ELSE wire_nl10i00Ol_dataout; + wire_nl10i1ill_dataout <= nlOi01iO WHEN nl11OO0OO = '1' ELSE wire_nl10i00OO_dataout; + wire_nl10i1ilO_dataout <= nlOi01li WHEN nl11OO0OO = '1' ELSE wire_nl10i0i1i_dataout; + wire_nl10i1iOi_dataout <= nlOi01ll WHEN nl11OO0OO = '1' ELSE wire_nl10i0i1l_dataout; + wire_nl10i1iOl_dataout <= nlOi01lO WHEN nl11OO0OO = '1' ELSE wire_nl10i0i1O_dataout; + wire_nl10i1iOO_dataout <= nlOi01Oi WHEN nl11OO0OO = '1' ELSE wire_nl10i0i0i_dataout; + wire_nl10i1l_dataout <= wire_nl1i1iO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10i1l0i_dataout <= nlOi011i WHEN nl11OO0OO = '1' ELSE wire_nl10i0iil_dataout; + wire_nl10i1l0l_dataout <= nlOi011l WHEN nl11OO0OO = '1' ELSE wire_nl10i0iiO_dataout; + wire_nl10i1l0O_dataout <= nlOi011O WHEN nl11OO0OO = '1' ELSE wire_nl10i0ili_dataout; + wire_nl10i1l1i_dataout <= nlOi01Ol WHEN nl11OO0OO = '1' ELSE wire_nl10i0i0l_dataout; + wire_nl10i1l1l_dataout <= nlOi01OO WHEN nl11OO0OO = '1' ELSE wire_nl10i0i0O_dataout; + wire_nl10i1l1O_dataout <= nlOi1OOO WHEN nl11OO0OO = '1' ELSE wire_nl10i0iii_dataout; + wire_nl10i1li_dataout <= nl10i1lO AND NOT(wire_niO01O0O_dataout); + wire_nl10i1lii_dataout <= nlOi010i WHEN nl11OO0OO = '1' ELSE wire_nl10i0ill_dataout; + wire_nl10i1lil_dataout <= nlOi010l WHEN nl11OO0OO = '1' ELSE wire_nl10i0ilO_dataout; + wire_nl10i1liO_dataout <= nlOi010O WHEN nl11OO0OO = '1' ELSE wire_nl10i0iOi_dataout; + wire_nl10i1lli_dataout <= nlOi01ii WHEN nl11OO0OO = '1' ELSE wire_nl10i0iOl_dataout; + wire_nl10i1lll_dataout <= nlOi1Oii WHEN nl11OO0OO = '1' ELSE wire_nl10i0iOO_dataout; + wire_nl10i1llO_dataout <= nlOi1Oil WHEN nl11OO0OO = '1' ELSE wire_nl10i0l1i_dataout; + wire_nl10i1lOi_dataout <= nlOi1OiO WHEN nl11OO0OO = '1' ELSE wire_nl10i0l1l_dataout; + wire_nl10i1lOl_dataout <= nlOi1Oli WHEN nl11OO0OO = '1' ELSE wire_nl10i0l1O_dataout; + wire_nl10i1lOO_dataout <= nlOi1Oll WHEN nl11OO0OO = '1' ELSE wire_nl10i0l0i_dataout; + wire_nl10i1O_dataout <= wire_nl1i1li_o AND NOT(wire_niO01O0O_dataout); + wire_nl10i1O0i_dataout <= nlOii1Oi WHEN nl11OO0OO = '1' ELSE wire_nl10i0lil_dataout; + wire_nl10i1O0l_dataout <= nlOii1Ol WHEN nl11OO0OO = '1' ELSE wire_nl10i0liO_dataout; + wire_nl10i1O0O_dataout <= nlOii1OO WHEN nl11OO0OO = '1' ELSE wire_nl10i0lli_dataout; + wire_nl10i1O1i_dataout <= nlOi1OlO WHEN nl11OO0OO = '1' ELSE wire_nl10i0l0l_dataout; + wire_nl10i1O1l_dataout <= nlOi1OOi WHEN nl11OO0OO = '1' ELSE wire_nl10i0l0O_dataout; + wire_nl10i1O1O_dataout <= nlOi1OOl WHEN nl11OO0OO = '1' ELSE wire_nl10i0lii_dataout; + wire_nl10i1Oi_dataout <= nl10i1ll AND NOT(wire_niO01O0O_dataout); + wire_nl10i1Oii_dataout <= nlOii01i WHEN nl11OO0OO = '1' ELSE wire_nl10i0lll_dataout; + wire_nl10i1Oil_dataout <= nlOii01l WHEN nl11OO0OO = '1' ELSE wire_nl10i0llO_dataout; + wire_nl10i1OiO_dataout <= nlOii01O WHEN nl11OO0OO = '1' ELSE wire_nl10i0lOi_dataout; + wire_nl10i1Ol_dataout <= nl10i1ii AND NOT(wire_niO01O0O_dataout); + wire_nl10i1Oli_dataout <= nlOii00i WHEN nl11OO0OO = '1' ELSE wire_nl10i0lOl_dataout; + wire_nl10i1Oll_dataout <= nlOii00l WHEN nl11OO0OO = '1' ELSE wire_nl10i0lOO_dataout; + wire_nl10i1OlO_dataout <= nlOii00O WHEN nl11OO0OO = '1' ELSE wire_nl10i0O1i_dataout; + wire_nl10i1OOi_dataout <= nlOii0ii WHEN nl11OO0OO = '1' ELSE wire_nl10i0O1l_dataout; + wire_nl10i1OOl_dataout <= nlOii0il WHEN nl11OO0OO = '1' ELSE wire_nl10i0O1O_dataout; + wire_nl10i1OOO_dataout <= nlOii0iO WHEN nl11OO0OO = '1' ELSE wire_nl10i0O0i_dataout; + wire_nl10ii01O_dataout <= nliiO11OO WHEN ((NOT k_gbl_hip(32)) OR wire_w_lg_w_k_gbl_hip_range2434w59722w(0)) = '1' ELSE wire_nlO0Olll_dataout; + wire_nl10ii0ii_dataout <= nlOili1O AND NOT(((NOT k_gbl_hip(32)) OR niOi10OOl)); + wire_nl10ii0lO_dataout <= (niOi10O0i AND wire_nlill0Oll_w_lg_nl11OOOii59718w(0)) AND NOT(niOi10O1O); + wire_nl10ii0Oi_dataout <= wire_nl10iii1i_dataout AND NOT(niOi10O1O); + wire_nl10ii0Ol_dataout <= wire_nl10iii1l_dataout AND NOT(niOi10O1O); + wire_nl10ii10i_dataout <= nlOi1OiO WHEN nl11OO0Ol = '1' ELSE nl11OOO1i; + wire_nl10ii10l_dataout <= nlOi1Oli WHEN nl11OO0Ol = '1' ELSE nl11OOO1l; + wire_nl10ii10O_dataout <= nlOi1Oll WHEN nl11OO0Ol = '1' ELSE nl11OOO1O; + wire_nl10ii11i_dataout <= nlOi01ii WHEN nl11OO0Ol = '1' ELSE nl11OOlOi; + wire_nl10ii11l_dataout <= nlOi1Oii WHEN nl11OO0Ol = '1' ELSE nl11OOlOl; + wire_nl10ii11O_dataout <= nlOi1Oil WHEN nl11OO0Ol = '1' ELSE nl11OOlOO; + wire_nl10ii1i_dataout <= tl_aer_msi_num(3) WHEN wire_w_lg_niOO1l11O8198w(0) = '1' ELSE nl10i01O; + wire_nl10ii1ii_dataout <= nlOi1OlO WHEN nl11OO0Ol = '1' ELSE nl11OOO0i; + wire_nl10ii1il_dataout <= nlOi1OOi WHEN nl11OO0Ol = '1' ELSE nl11OOO0l; + wire_nl10ii1iO_dataout <= nlOi1OOl WHEN nl11OO0Ol = '1' ELSE nl11OOO0O; + wire_nl10ii1l_dataout <= tl_aer_msi_num(4) WHEN wire_w_lg_niOO1l11O8198w(0) = '1' ELSE nl10i00i; + wire_nl10ii1lO_dataout <= nlOi0lOi WHEN nlOili1i = '1' ELSE nlOii1OO; + wire_nl10ii1lO_w_lg_dataout59872w(0) <= wire_nl10ii1lO_dataout AND wire_w_lg_niOi10lOl59871w(0); + wire_nl10ii1lO_w_lg_dataout59873w(0) <= NOT wire_nl10ii1lO_dataout; + wire_nl10iii_dataout <= wire_nl1i1Ol_o OR wire_niO01O0O_dataout; + wire_nl10iii1i_dataout <= niOi10Oil AND niOi10O1l; + wire_nl10iii1l_dataout <= niOi10O0O AND niOi10O1l; + wire_nl10iil_dataout <= wire_nl1i1OO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10iil1O_dataout <= (NOT ((niOi10Oll AND nlOili1l) OR wire_nl1000i_w_lg_w_lg_nlOil0OO59701w59702w(0))) AND NOT(niOi10OlO); + wire_nl10iil1O_w_lg_dataout61537w(0) <= NOT wire_nl10iil1O_dataout; + wire_nl10iilli_dataout <= wire_nl10iiOlO_o(0) AND nlOili1l; + wire_nl10iilli_w_lg_dataout61528w(0) <= NOT wire_nl10iilli_dataout; + wire_nl10iilll_dataout <= wire_nl10iiOlO_o(1) AND nlOili1l; + wire_nl10iillO_dataout <= wire_nl10iiOlO_o(2) AND nlOili1l; + wire_nl10iilOi_dataout <= wire_nl10iiOlO_o(3) AND nlOili1l; + wire_nl10iilOl_dataout <= wire_nl10iiOlO_o(4) AND nlOili1l; + wire_nl10iilOO_dataout <= wire_nl10iiOlO_o(5) AND nlOili1l; + wire_nl10iiO_dataout <= wire_nl1i01i_o AND NOT(wire_niO01O0O_dataout); + wire_nl10iiO0i_dataout <= wire_nl10iiOOi_o(1) AND nlOili1l; + wire_nl10iiO0l_dataout <= wire_nl10iiOOi_o(2) AND nlOili1l; + wire_nl10iiO0O_dataout <= wire_nl10iiOOi_o(3) AND nlOili1l; + wire_nl10iiO1i_dataout <= wire_nl10iiOlO_o(6) AND nlOili1l; + wire_nl10iiO1l_dataout <= wire_nl10iiOlO_o(7) AND nlOili1l; + wire_nl10iiO1O_dataout <= wire_nl10iiOOi_o(0) WHEN nlOili1l = '1' ELSE niOi10OOl; + wire_nl10iiOii_dataout <= wire_nl10iiOOi_o(4) AND nlOili1l; + wire_nl10iiOil_dataout <= wire_nl10iiOOi_o(5) AND nlOili1l; + wire_nl10iiOiO_dataout <= wire_nl10iiOOi_o(6) AND nlOili1l; + wire_nl10iiOli_dataout <= wire_nl10iiOOi_o(7) AND nlOili1l; + wire_nl10iiOO_dataout <= wire_nl10il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iiOOl_dataout <= nlOil11l WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(0); + wire_nl10iiOOl_w_lg_w_lg_dataout59597w59874w(0) <= wire_nl10iiOOl_w_lg_dataout59597w(0) AND wire_nl1000i_w_lg_nlOili1i59697w(0); + wire_nl10iiOOl_w_lg_dataout59870w(0) <= wire_nl10iiOOl_dataout AND nlOili1i; + wire_nl10iiOOl_w_lg_dataout59597w(0) <= NOT wire_nl10iiOOl_dataout; + wire_nl10iiOOO_dataout <= nlOil11O WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(1); + wire_nl10iiOOO_w_lg_w_lg_dataout59596w59598w(0) <= wire_nl10iiOOO_w_lg_dataout59596w(0) AND wire_nl10iiOOl_w_lg_dataout59597w(0); + wire_nl10iiOOO_w_lg_w_lg_w_lg_dataout59596w59598w59599w(0) <= NOT wire_nl10iiOOO_w_lg_w_lg_dataout59596w59598w(0); + wire_nl10iiOOO_w_lg_dataout59596w(0) <= NOT wire_nl10iiOOO_dataout; + wire_nl10il00i_dataout <= wire_nl10il0il_dataout AND NOT(nl11OOi1i); + wire_nl10il00l_dataout <= wire_nl10il0iO_dataout OR nl11OOi1i; + wire_nl10il00O_dataout <= wire_nl10il0li_dataout AND NOT(nl11OOi1i); + wire_nl10il01i_dataout <= wire_nl10il00l_dataout AND NOT(nl11OOi1l); + wire_nl10il01l_dataout <= wire_nl10il00O_dataout AND NOT(nl11OOi1l); + wire_nl10il01O_dataout <= wire_nl10il0ii_dataout AND NOT(nl11OOi1l); + wire_nl10il0i_dataout <= wire_nl10iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10il0ii_dataout <= wire_nl10il0ll_dataout AND NOT(nl11OOi1i); + wire_nl10il0il_dataout <= wire_nl10il0lO_dataout OR nl11OO0OO; + wire_nl10il0iO_dataout <= wire_nl10il0Oi_dataout OR nl11OO0OO; + wire_nl10il0l_dataout <= nl10iOii WHEN niOO1l10i = '1' ELSE nl10illl; + wire_nl10il0li_dataout <= wire_nl10il0Ol_dataout AND NOT(nl11OO0OO); + wire_nl10il0ll_dataout <= wire_nl10il0OO_dataout AND NOT(nl11OO0OO); + wire_nl10il0lO_dataout <= wire_nl10ili1i_dataout AND NOT(nl11OO0Ol); + wire_nl10il0O_dataout <= nl10iOil WHEN niOO1l10i = '1' ELSE nl10iili; + wire_nl10il0Oi_dataout <= wire_nl10ili1l_dataout AND NOT(nl11OO0Ol); + wire_nl10il0Ol_dataout <= wire_nl10ili1O_dataout OR nl11OO0Ol; + wire_nl10il0OO_dataout <= wire_nl10ili0i_dataout AND NOT(nl11OO0Ol); + wire_nl10il10i_dataout <= nlOil1ii WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(5); + wire_nl10il10i_w_lg_dataout60297w(0) <= NOT wire_nl10il10i_dataout; + wire_nl10il10l_dataout <= nlOil1il WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(6); + wire_nl10il10l_w_lg_dataout60295w(0) <= NOT wire_nl10il10l_dataout; + wire_nl10il10O_dataout <= nlOil1iO WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(7); + wire_nl10il10O_w_lg_dataout60293w(0) <= NOT wire_nl10il10O_dataout; + wire_nl10il11i_dataout <= nlOil10i WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(2); + wire_nl10il11i_w_lg_dataout60303w(0) <= NOT wire_nl10il11i_dataout; + wire_nl10il11l_dataout <= nlOil10l WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(3); + wire_nl10il11l_w_lg_dataout60301w(0) <= NOT wire_nl10il11l_dataout; + wire_nl10il11O_dataout <= nlOil10O WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(4); + wire_nl10il11O_w_lg_dataout60299w(0) <= NOT wire_nl10il11O_dataout; + wire_nl10il1i_dataout <= wire_nl10il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10il1ii_dataout <= nlOil1li WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(8); + wire_nl10il1ii_w_lg_dataout60291w(0) <= NOT wire_nl10il1ii_dataout; + wire_nl10il1il_dataout <= nlOil1ll WHEN niOi1i11i = '1' ELSE wire_nl10il1iO_o(9); + wire_nl10il1il_w_lg_dataout60290w(0) <= NOT wire_nl10il1il_dataout; + wire_nl10il1l_dataout <= wire_nl10ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10il1ll_dataout <= wire_nl10il1OO_dataout AND NOT(nl11OOi1O); + wire_nl10il1lO_dataout <= wire_nl10il01i_dataout AND NOT(nl11OOi1O); + wire_nl10il1O_dataout <= wire_nl10ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10il1Oi_dataout <= wire_nl10il01l_dataout AND NOT(nl11OOi1O); + wire_nl10il1Ol_dataout <= wire_nl10il01O_dataout AND NOT(nl11OOi1O); + wire_nl10il1OO_dataout <= wire_nl10il00i_dataout OR nl11OOi1l; + wire_nl10ili_dataout <= wire_nl1i01l_o AND NOT(wire_niO01O0O_dataout); + wire_nl10ili0i_dataout <= wire_nl10iliii_dataout AND NOT(nl11OO0Oi); + wire_nl10ili0l_dataout <= wire_nl10iliil_dataout AND NOT(nl11OO0lO); + wire_nl10ili0O_dataout <= wire_nl10iliil_dataout OR nl11OO0lO; + wire_nl10ili1i_dataout <= wire_nl10ili0l_dataout OR nl11OO0Oi; + wire_nl10ili1l_dataout <= wire_nl10ili0O_dataout AND NOT(nl11OO0Oi); + wire_nl10ili1O_dataout <= wire_nl10ili0O_dataout OR nl11OO0Oi; + wire_nl10ilii_dataout <= nl10iOiO WHEN niOO1l10i = '1' ELSE nl10iill; + wire_nl10iliii_dataout <= wire_nlill0Oll_w_lg_nl11OO0ll59542w(0) AND NOT(nl11OO0lO); + wire_nl10iliil_dataout <= wire_nlill0Oll_w_lg_nl11OO0li59541w(0) OR nl11OO0ll; + wire_nl10ilil_dataout <= nl10iOli WHEN niOO1l10i = '1' ELSE nl10iilO; + wire_nl10iliO_dataout <= nl10iOll WHEN niOO1l10i = '1' ELSE nl10iiOi; + wire_nl10ill_dataout <= wire_nl1i01O_o AND NOT(wire_niO01O0O_dataout); + wire_nl10ilO_dataout <= wire_nl1i00i_o AND NOT(wire_niO01O0O_dataout); + wire_nl10ilOi_dataout <= nl10iO1i AND NOT(wire_niO01l0O_dataout); + wire_nl10ilOO_dataout <= nl10iiOl AND NOT(wire_niO01l0O_dataout); + wire_nl10ilOOO_dataout <= (niOi1i11l AND niOi1i11O) AND NOT(wire_niO01O0O_dataout); + wire_nl10iO00i_dataout <= wire_nl10iO0lO_dataout WHEN niOi1i11l = '1' ELSE nl10ilO0O; + wire_nl10iO00l_dataout <= wire_nl10iO0Oi_dataout WHEN niOi1i11l = '1' ELSE nl10ilOii; + wire_nl10iO00O_dataout <= wire_nl10iO0Ol_dataout WHEN niOi1i11l = '1' ELSE nl10ilOil; + wire_nl10iO01i_dataout <= wire_nl10iO0iO_dataout AND NOT(niOi1i10i); + wire_nl10iO01l_dataout <= wire_nl10iO0li_dataout AND NOT(niOi1i10i); + wire_nl10iO01O_dataout <= wire_nl10iO0ll_dataout AND NOT(niOi1i10i); + wire_nl10iO0ii_dataout <= wire_nl10iO0OO_dataout WHEN niOi1i11l = '1' ELSE nl10ilOiO; + wire_nl10iO0il_dataout <= wire_nl10iOi1i_dataout WHEN niOi1i11l = '1' ELSE nl10ilOli; + wire_nl10iO0iO_dataout <= wire_nl10iOi1l_dataout WHEN niOi1i11l = '1' ELSE nl10ilOll; + wire_nl10iO0l_dataout <= nl10iO1O AND NOT(wire_niO01O0O_dataout); + wire_nl10iO0li_dataout <= wire_nl10iOi1O_dataout WHEN niOi1i11l = '1' ELSE nl10ilOlO; + wire_nl10iO0ll_dataout <= wire_nl10iOi0i_dataout WHEN niOi1i11l = '1' ELSE nl10ilOOi; + wire_nl10iO0lO_dataout <= wire_nl10iOi0l_o(0) AND NOT(niOi1i11O); + wire_nl10iO0O_dataout <= nl10ilOl AND NOT(wire_niO01O0O_dataout); + wire_nl10iO0Oi_dataout <= wire_nl10iOi0l_o(1) AND NOT(niOi1i11O); + wire_nl10iO0Ol_dataout <= wire_nl10iOi0l_o(2) AND NOT(niOi1i11O); + wire_nl10iO0OO_dataout <= wire_nl10iOi0l_o(3) AND NOT(niOi1i11O); + wire_nl10iO10i_dataout <= wire_nl10iO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO10l_dataout <= wire_nl10iO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO10O_dataout <= wire_nl10iO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO11i_dataout <= wire_nl10iO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO11l_dataout <= wire_nl10iO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO11O_dataout <= wire_nl10iO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO1ii_dataout <= wire_nl10iO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO1il_dataout <= wire_nl10iO01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iO1l_dataout <= nl10iO0i AND NOT(wire_niO01O0O_dataout); + wire_nl10iO1ll_dataout <= wire_nl10iO00i_dataout AND NOT(niOi1i10i); + wire_nl10iO1lO_dataout <= wire_nl10iO00l_dataout AND NOT(niOi1i10i); + wire_nl10iO1Oi_dataout <= wire_nl10iO00O_dataout AND NOT(niOi1i10i); + wire_nl10iO1Ol_dataout <= wire_nl10iO0ii_dataout AND NOT(niOi1i10i); + wire_nl10iO1OO_dataout <= wire_nl10iO0il_dataout AND NOT(niOi1i10i); + wire_nl10iOi_dataout <= wire_nl1i00l_o AND NOT(wire_niO01O0O_dataout); + wire_nl10iOi0i_dataout <= wire_nl10iOi0l_o(7) AND NOT(niOi1i11O); + wire_nl10iOi1i_dataout <= wire_nl10iOi0l_o(4) AND NOT(niOi1i11O); + wire_nl10iOi1l_dataout <= wire_nl10iOi0l_o(5) AND NOT(niOi1i11O); + wire_nl10iOi1O_dataout <= wire_nl10iOi0l_o(6) AND NOT(niOi1i11O); + wire_nl10iOili_dataout <= wire_nl10iOiOi_dataout AND NOT(niOi1i1ii); + wire_nl10iOili_w_lg_dataout59417w(0) <= NOT wire_nl10iOili_dataout; + wire_nl10iOill_dataout <= wire_nl10iOiOl_dataout AND NOT(niOi1i1ii); + wire_nl10iOill_w_lg_dataout59415w(0) <= NOT wire_nl10iOill_dataout; + wire_nl10iOilO_dataout <= wire_nl10iOiOO_dataout AND NOT(niOi1i1ii); + wire_nl10iOilO_w_lg_dataout59414w(0) <= NOT wire_nl10iOilO_dataout; + wire_nl10iOiOi_dataout <= nli1l001O WHEN niOi1i1il = '1' ELSE wire_nl10iOl1i_dataout; + wire_nl10iOiOl_dataout <= nli1l1l0O WHEN niOi1i1il = '1' ELSE wire_nl10iOl1l_dataout; + wire_nl10iOiOO_dataout <= nli1l1lii WHEN niOi1i1il = '1' ELSE wire_nl10iOl1O_dataout; + wire_nl10iOl_dataout <= wire_nl1i00O_o AND NOT(wire_niO01O0O_dataout); + wire_nl10iOl0i_dataout <= nli1l1lll WHEN niOi1i1li = '1' ELSE wire_nl10iOlii_dataout; + wire_nl10iOl0l_dataout <= nli1l1llO WHEN niOi1i1li = '1' ELSE wire_nl10iOlil_dataout; + wire_nl10iOl0O_dataout <= nli1l1lOi WHEN niOi1i1li = '1' ELSE wire_nl10iOliO_dataout; + wire_nl10iOl1i_dataout <= nli1l1lil WHEN niOi1i1iO = '1' ELSE wire_nl10iOl0i_dataout; + wire_nl10iOl1l_dataout <= nli1l1liO WHEN niOi1i1iO = '1' ELSE wire_nl10iOl0l_dataout; + wire_nl10iOl1O_dataout <= nli1l1lli WHEN niOi1i1iO = '1' ELSE wire_nl10iOl0O_dataout; + wire_nl10iOlii_dataout <= nli1l1lOl WHEN niOi1i1ll = '1' ELSE wire_nl10iOlli_dataout; + wire_nl10iOlil_dataout <= nli1l1lOO WHEN niOi1i1ll = '1' ELSE wire_nl10iOlll_dataout; + wire_nl10iOliO_dataout <= nli1l1O1i WHEN niOi1i1ll = '1' ELSE wire_nl10iOllO_dataout; + wire_nl10iOlli_dataout <= nli1l1O1l WHEN niOi1i1lO = '1' ELSE wire_nl10iOlOi_dataout; + wire_nl10iOlll_dataout <= nli1l1O1O WHEN niOi1i1lO = '1' ELSE wire_nl10iOlOl_dataout; + wire_nl10iOllO_dataout <= nli1l1O0i WHEN niOi1i1lO = '1' ELSE wire_nl10iOlOO_dataout; + wire_nl10iOlO_dataout <= wire_nl10l11O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10iOlOi_dataout <= nli1l1O0l WHEN niOi1i1Oi = '1' ELSE nli1l1Oil; + wire_nl10iOlOl_dataout <= nli1l1O0O WHEN niOi1i1Oi = '1' ELSE nli1l1OiO; + wire_nl10iOlOO_dataout <= nli1l1Oii WHEN niOi1i1Oi = '1' ELSE nli1l1Oli; + wire_nl10iOO_dataout <= wire_nl1i0ii_o AND NOT(wire_niO01O0O_dataout); + wire_nl10iOOi_dataout <= wire_nl10l10l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10iOOl_dataout <= wire_nl10l10O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10iOOlO_dataout <= wire_nl10l11ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iOOO_dataout <= wire_nl10l1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10iOOOi_dataout <= wire_nl10l11il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iOOOl_dataout <= wire_nl10l11iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10iOOOO_dataout <= wire_nl10l11li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10l0i_dataout <= wire_nl1i0ll_o AND NOT(wire_niO01O0O_dataout); + wire_nl10l0l_dataout <= wire_nl1i0lO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10l0O_dataout <= wire_nl1i0Ol_o AND NOT(wire_niO01O0O_dataout); + wire_nl10l100i_dataout <= wire_nl10l10ll_dataout AND NOT(nl10ilOOl); + wire_nl10l100l_dataout <= wire_nl10l10lO_dataout AND NOT(nl10ilOOl); + wire_nl10l100O_dataout <= wire_nl10l10Oi_dataout AND NOT(nl10ilOOl); + wire_nl10l101i_dataout <= wire_nl10l10il_dataout AND NOT(nl10ilOOl); + wire_nl10l101l_dataout <= wire_nl10l10iO_dataout AND NOT(nl10ilOOl); + wire_nl10l101O_dataout <= wire_nl10l10li_dataout AND NOT(nl10ilOOl); + wire_nl10l10ii_dataout <= wire_nl10l10Ol_dataout AND NOT(nl10ilOOl); + wire_nl10l10il_dataout <= wire_w_lg_niOO10O0i59411w(0) AND nl10iOO1O; + wire_nl10l10iO_dataout <= wire_nl10l10OO_dataout AND NOT(nl10iOO1O); + wire_nl10l10l_dataout <= tl_pex_msi_num(0) WHEN wire_w_lg_niOO1l10O8173w(0) = '1' ELSE nl10iOii; + wire_nl10l10li_dataout <= wire_nl10l1i1i_dataout AND NOT(nl10iOO1O); + wire_nl10l10ll_dataout <= wire_nl10l1i1l_dataout AND NOT(nl10iOO1O); + wire_nl10l10lO_dataout <= wire_nl10l1i1O_dataout AND NOT(nl10iOO1O); + wire_nl10l10O_dataout <= tl_pex_msi_num(1) WHEN wire_w_lg_niOO1l10O8173w(0) = '1' ELSE nl10iOil; + wire_nl10l10Oi_dataout <= wire_nl10l1i0i_dataout AND NOT(nl10iOO1O); + wire_nl10l10Ol_dataout <= wire_nl10l1i0l_dataout AND NOT(nl10iOO1O); + wire_nl10l10OO_dataout <= wire_w_lg_niOO10O0i59411w(0) AND nl10iOO0i; + wire_nl10l110i_dataout <= wire_nl10l11Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10l110l_dataout <= wire_nl10l1l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10l110O_dataout <= wire_nl10l1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10l111i_dataout <= wire_nl10l11ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10l111l_dataout <= wire_nl10l11lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10l111O_dataout <= wire_nl10l11Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10l11i_dataout <= wire_nl10l1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10l11ii_dataout <= wire_nl10l11OO_dataout WHEN niOi1i01i = '1' ELSE nl10ilOOl; + wire_nl10l11il_dataout <= wire_nl10l101i_dataout WHEN niOi1i01i = '1' ELSE nl10iOO1O; + wire_nl10l11iO_dataout <= wire_nl10l101l_dataout WHEN niOi1i01i = '1' ELSE nl10iOO0i; + wire_nl10l11l_dataout <= wire_nl10l1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10l11li_dataout <= wire_nl10l101O_dataout WHEN niOi1i01i = '1' ELSE nl10iOO0l; + wire_nl10l11ll_dataout <= wire_nl10l100i_dataout WHEN niOi1i01i = '1' ELSE nl10iOO0O; + wire_nl10l11lO_dataout <= wire_nl10l100l_dataout WHEN niOi1i01i = '1' ELSE nl10iOOii; + wire_nl10l11O_dataout <= wire_niOOO0O_w_lg_nl10iO0i8178w(0) WHEN (wire_w_lg_niOO1l10O8173w(0) AND wire_w_lg_niOO1l10l8179w(0)) = '1' ELSE nl10iO0i; + wire_nl10l11Oi_dataout <= wire_nl10l100O_dataout WHEN niOi1i01i = '1' ELSE nl10iOOil; + wire_nl10l11Ol_dataout <= wire_nl10l10ii_dataout WHEN niOi1i01i = '1' ELSE nl10iOOiO; + wire_nl10l11OO_dataout <= niOO10O0i OR nl10ilOOl; + wire_nl10l1i_dataout <= wire_nl1i0il_o AND NOT(wire_niO01O0O_dataout); + wire_nl10l1i0i_dataout <= wire_nl10l1iiO_dataout AND NOT(nl10iOO0i); + wire_nl10l1i0l_dataout <= wire_nl10l1ili_dataout AND NOT(nl10iOO0i); + wire_nl10l1i0O_dataout <= wire_w_lg_niOO10O0i59411w(0) AND nl10iOO0l; + wire_nl10l1i1i_dataout <= wire_nl10l1i0O_dataout AND NOT(nl10iOO0i); + wire_nl10l1i1l_dataout <= wire_nl10l1iii_dataout AND NOT(nl10iOO0i); + wire_nl10l1i1O_dataout <= wire_nl10l1iil_dataout AND NOT(nl10iOO0i); + wire_nl10l1ii_dataout <= tl_pex_msi_num(2) WHEN wire_w_lg_niOO1l10O8173w(0) = '1' ELSE nl10iOiO; + wire_nl10l1iii_dataout <= wire_nl10l1ill_dataout AND NOT(nl10iOO0l); + wire_nl10l1iil_dataout <= wire_nl10l1ilO_dataout AND NOT(nl10iOO0l); + wire_nl10l1iiO_dataout <= wire_nl10l1iOi_dataout AND NOT(nl10iOO0l); + wire_nl10l1il_dataout <= tl_pex_msi_num(3) WHEN wire_w_lg_niOO1l10O8173w(0) = '1' ELSE nl10iOli; + wire_nl10l1ili_dataout <= wire_nl10l1iOl_dataout AND NOT(nl10iOO0l); + wire_nl10l1ill_dataout <= wire_w_lg_niOO10O0i59411w(0) AND nl10iOO0O; + wire_nl10l1ilO_dataout <= wire_nl10l1iOO_dataout AND NOT(nl10iOO0O); + wire_nl10l1iO_dataout <= tl_pex_msi_num(4) WHEN wire_w_lg_niOO1l10O8173w(0) = '1' ELSE nl10iOll; + wire_nl10l1iOi_dataout <= wire_nl10l1l1i_dataout AND NOT(nl10iOO0O); + wire_nl10l1iOl_dataout <= wire_nl10l1l1l_dataout AND NOT(nl10iOO0O); + wire_nl10l1iOO_dataout <= wire_w_lg_niOO10O0i59411w(0) AND nl10iOOii; + wire_nl10l1l_dataout <= wire_nl1i0iO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10l1l0i_dataout <= wire_w_lg_niOO10O0i59411w(0) AND NOT(nl10iOOil); + wire_nl10l1l0O_dataout <= wire_nl10l1lii_dataout OR (wire_nilOi11l_dataout AND nl10iOOll); + wire_nl10l1l1i_dataout <= wire_nl10l1l1O_dataout AND NOT(nl10iOOii); + wire_nl10l1l1l_dataout <= wire_nl10l1l0i_dataout AND NOT(nl10iOOii); + wire_nl10l1l1O_dataout <= wire_w_lg_niOO10O0i59411w(0) AND nl10iOOil; + wire_nl10l1lii_dataout <= nl10iOOli AND NOT((niOi1i01O OR niOi1i01l)); + wire_nl10l1lli_dataout <= wire_nl10l1lll_dataout OR niOi1i01i; + wire_nl10l1lll_dataout <= nl10iOOll AND NOT((wire_nilOi11l_dataout OR niOi1i01l)); + wire_nl10l1O_dataout <= wire_nl1i0li_o AND NOT(wire_niO01O0O_dataout); + wire_nl10lii_dataout <= wire_nl1i0OO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10liii_dataout <= wire_nl10liOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10liil_dataout <= wire_nl10ll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10liiO_dataout <= wire_nl10ll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lil_dataout <= wire_nl1ii1i_o AND NOT(wire_niO01O0O_dataout); + wire_nl10lili_dataout <= wire_nl10ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lill_dataout <= wire_nl10ll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lilO_dataout <= wire_nl10ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10liO_dataout <= wire_nl1ii1O_o AND NOT(wire_niO01O0O_dataout); + wire_nl10liO0i_dataout <= (NOT (niOi1ii1l OR (niOi1iili OR niOi1ii0O))) OR NOT(wire_nilOOO0i_dataout); + wire_nl10liO1O_dataout <= wire_nl10liO0i_dataout OR wire_niO01O0O_dataout; + wire_nl10liOi_dataout <= wire_nl10ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10liOil_dataout <= nl1i011lO WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll10l_dataout; + wire_nl10liOiO_dataout <= nl1i011Oi WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll10O_dataout; + wire_nl10liOl_dataout <= wire_nl10llii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10liOli_dataout <= nl1i011Ol WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1ii_dataout; + wire_nl10liOll_dataout <= nl1i011OO WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1il_dataout; + wire_nl10liOlO_dataout <= nl1i0101i WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1iO_dataout; + wire_nl10liOO_dataout <= nl10lO0l WHEN niOO1l1ii = '1' ELSE nl10lliO; + wire_nl10liOOi_dataout <= nl1i0101l WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1li_dataout; + wire_nl10liOOl_dataout <= nl1i0101O WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1ll_dataout; + wire_nl10liOOO_dataout <= nl1i0100i WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1lO_dataout; + wire_nl10ll00i_dataout <= nl1i0110O WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll0lO_dataout; + wire_nl10ll00l_dataout <= nl1i011ii WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll0Oi_dataout; + wire_nl10ll00O_dataout <= nl1i011il WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll0Ol_dataout; + wire_nl10ll01i_dataout <= nl1i1OOli WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Ol0l; + wire_nl10ll01l_dataout <= nl1i0110i WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll0li_dataout; + wire_nl10ll01O_dataout <= nl1i0110l WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll0ll_dataout; + wire_nl10ll0i_dataout <= nl10lOiO WHEN niOO1l1ii = '1' ELSE nl10li1l; + wire_nl10ll0ii_dataout <= nl1i011iO WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll0OO_dataout; + wire_nl10ll0il_dataout <= nl1i011li WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10lli1i_dataout; + wire_nl10ll0iO_dataout <= nl1i011ll WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10lli1l_dataout; + wire_nl10ll0l_dataout <= nl10lOli WHEN niOO1l1ii = '1' ELSE nl10li1O; + wire_nl10ll0li_dataout <= nl1i1OOll WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Ol0O; + wire_nl10ll0ll_dataout <= nl1i1OOlO WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Olii; + wire_nl10ll0lO_dataout <= nl1i1OOOi WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Olil; + wire_nl10ll0O_dataout <= nl10lOll WHEN niOO1l1ii = '1' ELSE nl10li0i; + wire_nl10ll0Oi_dataout <= nl1i1OOOl WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1OliO; + wire_nl10ll0Ol_dataout <= nl1i1OOOO WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Olli; + wire_nl10ll0OO_dataout <= nl1i0111i WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Olll; + wire_nl10ll10i_dataout <= nl1i010il WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll01i_dataout; + wire_nl10ll10l_dataout <= nl1i1OlOl WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i10iOi; + wire_nl10ll10O_dataout <= nl1i1OlOO WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Oili; + wire_nl10ll11i_dataout <= nl1i0100l WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1Oi_dataout; + wire_nl10ll11l_dataout <= nl1i0100O WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1Ol_dataout; + wire_nl10ll11O_dataout <= nl1i010ii WHEN wire_nl10lli0l_dataout = '1' ELSE wire_nl10ll1OO_dataout; + wire_nl10ll1i_dataout <= nl10lO0O WHEN niOO1l1ii = '1' ELSE nl10l0Ol; + wire_nl10ll1ii_dataout <= nl1i1OO1i WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Oill; + wire_nl10ll1il_dataout <= nl1i1OO1l WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1OilO; + wire_nl10ll1iO_dataout <= nl1i1OO1O WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1OiOi; + wire_nl10ll1l_dataout <= nl10lOii WHEN niOO1l1ii = '1' ELSE nl10l0OO; + wire_nl10ll1li_dataout <= nl1i1OO0i WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1OiOl; + wire_nl10ll1ll_dataout <= nl1i1OO0l WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1OiOO; + wire_nl10ll1lO_dataout <= nl1i1OO0O WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Ol1i; + wire_nl10ll1O_dataout <= nl10lOil WHEN niOO1l1ii = '1' ELSE nl10li1i; + wire_nl10ll1Oi_dataout <= nl1i1OOii WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Ol1l; + wire_nl10ll1Ol_dataout <= nl1i1OOil WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Ol1O; + wire_nl10ll1OO_dataout <= nl1i1OOiO WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1Ol0i; + wire_nl10lli_dataout <= wire_nl1ii0i_o AND NOT(wire_niO01O0O_dataout); + wire_nl10lli0i_dataout <= nl10lliOi WHEN nl10lliOO = '1' ELSE nl10lli0O; + wire_nl10lli0i_w_lg_dataout58914w(0) <= NOT wire_nl10lli0i_dataout; + wire_nl10lli0l_dataout <= nl10lliOl WHEN nl10lliOO = '1' ELSE nl10lliii; + wire_nl10lli1i_dataout <= nl1i0111l WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1OllO; + wire_nl10lli1l_dataout <= nl1i0111O WHEN wire_nl10lli0i_dataout = '1' ELSE nl1i1OlOi; + wire_nl10lli1O_dataout <= nl10llilO WHEN nl10lliOO = '1' ELSE nl10liO1l; + wire_nl10llii_dataout <= nl10lOlO WHEN niOO1l1ii = '1' ELSE nl10li0l; + wire_nl10lll_dataout <= wire_nl1ii0l_o AND NOT(wire_niO01O0O_dataout); + wire_nl10lll0l_dataout <= wire_nl10llO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lll0O_dataout <= wire_nl10llO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lllii_dataout <= wire_nl10llO0O_dataout OR wire_niO01O0O_dataout; + wire_nl10lllil_dataout <= wire_nl10llOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10llliO_dataout <= wire_nl10lOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10llll_dataout <= nl10llOl AND NOT(wire_niO01l0O_dataout); + wire_nl10lllli_dataout <= wire_nl10lOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lllll_dataout <= wire_nl10lOi0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10llllO_dataout <= wire_nl10llOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lllOi_dataout <= wire_nl10llOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10lllOl_dataout <= wire_nl10llOOO_dataout OR wire_niO01O0O_dataout; + wire_nl10lllOO_dataout <= wire_nl10lO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10llO_dataout <= wire_nl1ii0O_o AND NOT(wire_niO01O0O_dataout); + wire_nl10llO0i_dataout <= wire_nl10llOii_dataout WHEN niOi1i0li = '1' ELSE nl10liO1l; + wire_nl10llO0l_dataout <= wire_nl10llOil_dataout WHEN niOi1i0li = '1' ELSE nl10lli0O; + wire_nl10llO0O_dataout <= nl10lliiO WHEN niOi1i0li = '1' ELSE nl10lliii; + wire_nl10llO1i_dataout <= wire_nl10lOill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10llO1l_dataout <= wire_nl10lOilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10llO1O_dataout <= wire_nl10lOiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10llOi_dataout <= nl10li0O AND NOT(wire_niO01l0O_dataout); + wire_nl10llOii_dataout <= wire_nlill0Oll_w_lg_nl10llili58950w(0) AND NOT(nl10lliiO); + wire_nl10llOil_dataout <= nl10llili AND NOT(nl10lliiO); + wire_nl10llOiO_dataout <= wire_nl10llOli_dataout OR niOi1i0li; + wire_nl10llOli_dataout <= nl10lliil AND NOT((niOi1i0ll AND nl10lliil)); + wire_nl10llOO_dataout <= nl10lO1l AND NOT(wire_niO01O0O_dataout); + wire_nl10llOOi_dataout <= wire_nl10lO11i_dataout WHEN niOi1i0lO = '1' ELSE nl10llilO; + wire_nl10llOOl_dataout <= wire_nl10lO11l_dataout WHEN niOi1i0lO = '1' ELSE nl10lliOi; + wire_nl10llOOO_dataout <= wire_nl10lO11O_dataout WHEN niOi1i0lO = '1' ELSE nl10lliOl; + wire_nl10lO00i_dataout <= wire_nl10lO0ii_dataout AND NOT(nl10lll1l); + wire_nl10lO00l_dataout <= wire_nl10lO0il_dataout OR nl10lll1l; + wire_nl10lO00O_dataout <= wire_nl10lO0iO_dataout AND NOT(nl10lll1l); + wire_nl10lO01i_dataout <= nl10llilO AND NOT(nl10lll1i); + wire_nl10lO01l_dataout <= nl10lliOi AND NOT(nl10lll1i); + wire_nl10lO01O_dataout <= nl10lliOl OR nl10lll1i; + wire_nl10lO0i_dataout <= nl10lllO AND NOT(wire_niO01O0O_dataout); + wire_nl10lO0ii_dataout <= nl10llilO OR nl10lll1O; + wire_nl10lO0il_dataout <= nl10lliOi AND NOT(nl10lll1O); + wire_nl10lO0iO_dataout <= nl10lliOl AND NOT(nl10lll1O); + wire_nl10lO0li_dataout <= wire_nl10lO0ll_dataout OR niOi1i0lO; + wire_nl10lO0ll_dataout <= nl10lliOO AND NOT((niOi1i0ll AND nl10lliOO)); + wire_nl10lO10i_dataout <= wire_nl10lO1Oi_dataout WHEN nl10lliOi = '1' ELSE wire_nl10lO1ii_dataout; + wire_nl10lO10l_dataout <= wire_nl10lO1Ol_dataout WHEN nl10lliOi = '1' ELSE wire_nl10lO1il_dataout; + wire_nl10lO10O_dataout <= wire_nl10lO1OO_dataout WHEN nl10lliOi = '1' ELSE wire_nl10lO1iO_dataout; + wire_nl10lO11i_dataout <= wire_nl10lO00i_dataout WHEN nl10lliOl = '1' ELSE wire_nl10lO10i_dataout; + wire_nl10lO11l_dataout <= wire_nl10lO00l_dataout WHEN nl10lliOl = '1' ELSE wire_nl10lO10l_dataout; + wire_nl10lO11O_dataout <= wire_nl10lO00O_dataout WHEN nl10lliOl = '1' ELSE wire_nl10lO10O_dataout; + wire_nl10lO1ii_dataout <= wire_nl10lO1li_dataout AND NOT(nl10lll1i); + wire_nl10lO1il_dataout <= wire_nl10lO1ll_dataout AND NOT(nl10lll1i); + wire_nl10lO1iO_dataout <= wire_nl10lO1lO_dataout OR nl10lll1i; + wire_nl10lO1li_dataout <= nl10llilO AND NOT(nl10lll1l); + wire_nl10lO1ll_dataout <= nl10lliOi OR nl10lll1l; + wire_nl10lO1lO_dataout <= nl10lliOl AND NOT(nl10lll1l); + wire_nl10lO1O_dataout <= nl10lO1i AND NOT(wire_niO01O0O_dataout); + wire_nl10lO1Oi_dataout <= wire_nl10lO01i_dataout OR nl10lll1O; + wire_nl10lO1Ol_dataout <= wire_nl10lO01l_dataout AND NOT(nl10lll1O); + wire_nl10lO1OO_dataout <= wire_nl10lO01O_dataout AND NOT(nl10lll1O); + wire_nl10lOi_dataout <= wire_nl1iiil_o AND NOT(wire_niO01O0O_dataout); + wire_nl10lOi0i_dataout <= (wire_nl10lOlii_w_lg_dataout58916w(0) AND wire_w_lg_w_lg_w_lg_niOi1ii1O58911w58926w58927w(0)) AND NOT(niOi1ii1i); + wire_nl10lOi1l_dataout <= (wire_nl10lOl0l_w_lg_dataout58922w(0) AND wire_w_lg_w_lg_w_lg_niOi1iill58695w58934w58935w(0)) AND NOT(niOi1ii1i); + wire_nl10lOi1O_dataout <= (wire_nl10lOl0O_w_lg_dataout58919w(0) AND wire_w_lg_w_lg_w_lg_niOi1iiii58803w58930w58931w(0)) AND NOT(niOi1ii1i); + wire_nl10lOill_dataout <= (wire_nl10lOl0l_w_lg_dataout58922w(0) AND (niOi1iili OR nl10lll1i)) AND NOT(niOi1ii1i); + wire_nl10lOilO_dataout <= (wire_nl10lOl0O_w_lg_dataout58919w(0) AND (niOi1ii0O OR nl10lll1l)) AND NOT(niOi1ii1i); + wire_nl10lOiOi_dataout <= (wire_nl10lOlii_w_lg_dataout58916w(0) AND (niOi1ii1l OR nl10lll1O)) AND NOT(niOi1ii1i); + wire_nl10lOl_dataout <= wire_nl1iiiO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10lOl0l_dataout <= wire_nl10lli0l_dataout AND NOT(wire_nl011l0il_w_lg_dataout58915w(0)); + wire_nl10lOl0l_w_lg_dataout58922w(0) <= NOT wire_nl10lOl0l_dataout; + wire_nl10lOl0O_dataout <= wire_nl10lOlil_dataout AND NOT(wire_nl011l0il_w_lg_dataout58915w(0)); + wire_nl10lOl0O_w_lg_dataout58919w(0) <= NOT wire_nl10lOl0O_dataout; + wire_nl10lOlii_dataout <= wire_nl10lOliO_dataout AND NOT(wire_nl011l0il_w_lg_dataout58915w(0)); + wire_nl10lOlii_w_lg_dataout58916w(0) <= NOT wire_nl10lOlii_dataout; + wire_nl10lOlil_dataout <= wire_nl10lli0i_dataout AND NOT(wire_nl10lli0l_dataout); + wire_nl10lOliO_dataout <= wire_nl10lli0i_w_lg_dataout58914w(0) AND NOT(wire_nl10lli0l_dataout); + wire_nl10lOO_dataout <= wire_nl1iili_o AND NOT(wire_niO01O0O_dataout); + wire_nl10lOOi_dataout <= wire_nl10O1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10lOOl_dataout <= wire_nl10O1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10lOOO_dataout <= wire_nl10O1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10O010i_dataout <= wire_nl10O01iO_dataout AND NOT(niOi1il1i); + wire_nl10O010l_dataout <= wire_nl10O01li_dataout AND NOT(niOi1il1i); + wire_nl10O010O_dataout <= wire_nl10O01ll_dataout AND NOT(niOi1il1i); + wire_nl10O011i_dataout <= wire_nl10O011l_o(4) WHEN niOi01l1i = '1' ELSE nl10O11Ol; + wire_nl10O011O_dataout <= wire_nl10O01il_dataout AND NOT(niOi1il1i); + wire_nl10O01i_dataout <= dl_vc_ctrl(7) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lOlO; + wire_nl10O01ii_dataout <= wire_nl10O01lO_dataout AND NOT(niOi1il1i); + wire_nl10O01il_dataout <= wire_nl10O01Oi_o(0) WHEN niOi01l1i = '1' ELSE nl10O11OO; + wire_nl10O01iO_dataout <= wire_nl10O01Oi_o(1) WHEN niOi01l1i = '1' ELSE nl10O101i; + wire_nl10O01li_dataout <= wire_nl10O01Oi_o(2) WHEN niOi01l1i = '1' ELSE nl10O101l; + wire_nl10O01ll_dataout <= wire_nl10O01Oi_o(3) WHEN niOi01l1i = '1' ELSE nl10O101O; + wire_nl10O01lO_dataout <= wire_nl10O01Oi_o(4) WHEN niOi01l1i = '1' ELSE nl10O100i; + wire_nl10O0i_dataout <= wire_nl1iiOO_o AND NOT(wire_niO01O0O_dataout); + wire_nl10O0l_dataout <= wire_nl1il1i_o AND NOT(wire_niO01O0O_dataout); + wire_nl10O0O_dataout <= wire_nl1il1l_o AND NOT(wire_niO01O0O_dataout); + wire_nl10O0OOl_dataout <= wire_nl10OilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O0OOO_dataout <= wire_nl10OilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O100O_dataout <= wire_nl10O1i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10i_dataout <= wire_nl10O1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10O10ii_dataout <= wire_nl10O1iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10il_dataout <= wire_nl10O1iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10iO_dataout <= wire_nl10O1iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10l_dataout <= wire_nl10O1OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10O10li_dataout <= wire_nl10O1ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10ll_dataout <= wire_nl10O1ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10lO_dataout <= wire_nl10O1ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10O_dataout <= wire_nl10O01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10O10Oi_dataout <= wire_nl10O1iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10Ol_dataout <= wire_nl10O1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O10OO_dataout <= wire_nl10O1iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O11i_dataout <= wire_nl10O1ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10O11l_dataout <= wire_nl10O1lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10O11O_dataout <= wire_nl10O1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl10O1i_dataout <= wire_nl1iill_o AND NOT(wire_niO01O0O_dataout); + wire_nl10O1i0i_dataout <= wire_nl10O1l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O1i0l_dataout <= wire_nl10O1l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O1i0O_dataout <= wire_nl10O1l0O_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1i1i_dataout <= wire_nl10O1l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O1i1l_dataout <= wire_nl10O1l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O1i1O_dataout <= wire_nl10O1l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10O1ii_dataout <= wire_niOOO0O_w_lg_nl10lO1l8144w(0) WHEN (wire_w_lg_niOO1l1iO8136w(0) AND wire_w_lg_niOO1l1il8145w(0)) = '1' ELSE nl10lO1l; + wire_nl10O1iii_dataout <= wire_nl10O1lii_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1iil_dataout <= wire_nl10O1lil_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1iiO_dataout <= wire_nl10O1liO_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1ili_dataout <= wire_nl10O1lli_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1ill_dataout <= wire_nl10O1Oii_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1ilO_dataout <= wire_nl10O1Oil_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1iO_dataout <= dl_vc_ctrl(0) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lO0l; + wire_nl10O1iOi_dataout <= wire_nl10O1OiO_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1iOl_dataout <= wire_nl10O1Oli_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1iOO_dataout <= wire_nl10O1Oll_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1l_dataout <= wire_nl1iiOi_o AND NOT(wire_niO01O0O_dataout); + wire_nl10O1l0i_dataout <= wire_nl10O010O_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1l0l_dataout <= wire_nl10O01ii_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1l0O_dataout <= wire_nl10O1lll_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10lll0i; + wire_nl10O1l1i_dataout <= wire_nl10O011O_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1l1l_dataout <= wire_nl10O010i_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1l1O_dataout <= wire_nl10O010l_dataout AND wire_nilOOO0i_dataout; + wire_nl10O1li_dataout <= dl_vc_ctrl(1) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lO0O; + wire_nl10O1lii_dataout <= wire_nl10O1llO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O110O; + wire_nl10O1lil_dataout <= wire_nl10O1lOi_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O11ii; + wire_nl10O1liO_dataout <= wire_nl10O1lOl_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O11il; + wire_nl10O1ll_dataout <= dl_vc_ctrl(2) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lOii; + wire_nl10O1lli_dataout <= wire_nl10O1lOO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O11iO; + wire_nl10O1lll_dataout <= wire_nl10O1O1i_dataout AND NOT(niOi1iiOl); + wire_nl10O1llO_dataout <= wire_nl10O1O1l_dataout AND NOT(niOi1iiOl); + wire_nl10O1lO_dataout <= dl_vc_ctrl(3) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lOil; + wire_nl10O1lOi_dataout <= wire_nl10O1O1O_dataout AND NOT(niOi1iiOl); + wire_nl10O1lOl_dataout <= wire_nl10O1O0i_dataout AND NOT(niOi1iiOl); + wire_nl10O1lOO_dataout <= wire_nl10O1O0l_dataout AND NOT(niOi1iiOl); + wire_nl10O1O_dataout <= wire_nl1iiOl_o AND NOT(wire_niO01O0O_dataout); + wire_nl10O1O0i_dataout <= wire_nl10O1O0O_o(3) WHEN niOi01l1i = '1' ELSE nl10O11il; + wire_nl10O1O0l_dataout <= wire_nl10O1O0O_o(4) WHEN niOi01l1i = '1' ELSE nl10O11iO; + wire_nl10O1O1i_dataout <= wire_nl10O1O0O_o(0) WHEN niOi01l1i = '1' ELSE nl10lll0i; + wire_nl10O1O1l_dataout <= wire_nl10O1O0O_o(1) WHEN niOi01l1i = '1' ELSE nl10O110O; + wire_nl10O1O1O_dataout <= wire_nl10O1O0O_o(2) WHEN niOi01l1i = '1' ELSE nl10O11ii; + wire_nl10O1Oi_dataout <= dl_vc_ctrl(4) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lOiO; + wire_nl10O1Oii_dataout <= wire_nl10O1OlO_dataout AND NOT(niOi1iiOO); + wire_nl10O1Oil_dataout <= wire_nl10O1OOi_dataout AND NOT(niOi1iiOO); + wire_nl10O1OiO_dataout <= wire_nl10O1OOl_dataout AND NOT(niOi1iiOO); + wire_nl10O1Ol_dataout <= dl_vc_ctrl(5) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lOli; + wire_nl10O1Oli_dataout <= wire_nl10O1OOO_dataout AND NOT(niOi1iiOO); + wire_nl10O1Oll_dataout <= wire_nl10O011i_dataout AND NOT(niOi1iiOO); + wire_nl10O1OlO_dataout <= wire_nl10O011l_o(0) WHEN niOi01l1i = '1' ELSE nl10O11li; + wire_nl10O1OO_dataout <= dl_vc_ctrl(6) WHEN wire_w_lg_niOO1l1iO8136w(0) = '1' ELSE nl10lOll; + wire_nl10O1OOi_dataout <= wire_nl10O011l_o(1) WHEN niOi01l1i = '1' ELSE nl10O11ll; + wire_nl10O1OOl_dataout <= wire_nl10O011l_o(2) WHEN niOi01l1i = '1' ELSE nl10O11lO; + wire_nl10O1OOO_dataout <= wire_nl10O011l_o(3) WHEN niOi01l1i = '1' ELSE nl10O11Oi; + wire_nl10Oi00i_dataout <= wire_nl10OliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi00l_dataout <= wire_nl10Oll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi00O_dataout <= wire_nl10Oll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi01i_dataout <= wire_nl10Ol11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi01l_dataout <= wire_nl10Ol11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi01O_dataout <= wire_nl10Ol11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0ii_dataout <= wire_nl10Oll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0il_dataout <= wire_nl10Oll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0iO_dataout <= wire_nl10Oll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0li_dataout <= wire_nl10Oll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0ll_dataout <= wire_nl10Ollii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0lO_dataout <= wire_nl10Ollil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0Oi_dataout <= wire_nl10OlliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0Ol_dataout <= wire_nl10Ollli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi0OO_dataout <= wire_nl10Ollll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi10i_dataout <= wire_nl10OiO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi10l_dataout <= wire_nl10OiO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi10O_dataout <= wire_nl10OiO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi11i_dataout <= wire_nl10OiO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi11l_dataout <= wire_nl10OiO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi11O_dataout <= wire_nl10OiO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1ii_dataout <= wire_nl10OiOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1il_dataout <= wire_nl10OiOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1iO_dataout <= wire_nl10OiOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1li_dataout <= wire_nl10OiOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1ll_dataout <= wire_nl10OiOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1lO_dataout <= wire_nl10OiOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1Oi_dataout <= wire_nl10OiOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1Ol_dataout <= wire_nl10OiOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oi1OO_dataout <= wire_nl10OiOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oii_dataout <= wire_nl1il1O_o AND NOT(wire_niO01O0O_dataout); + wire_nl10Oii0i_dataout <= wire_nl10OllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oii0l_dataout <= wire_nl10OlO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oii0O_dataout <= wire_nl10OlO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oii1i_dataout <= wire_nl10OlllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oii1l_dataout <= wire_nl10OllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oii1O_dataout <= wire_nl10OllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oiiii_dataout <= wire_nl10OlO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oiiil_dataout <= wire_nl10OlO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OiiiO_dataout <= wire_nl10OOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oiili_dataout <= wire_nl10OOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oiill_dataout <= wire_nl10OOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OiilO_dataout <= wire_nl10OOO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OiiOi_dataout <= wire_nl10OOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OiiOl_dataout <= wire_nl10OOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OiiOO_dataout <= wire_nl10OOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oil_dataout <= wire_nl1il0i_o AND NOT(wire_niO01O0O_dataout); + wire_nl10Oil0i_dataout <= wire_nl10OOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oil0l_dataout <= wire_nl10OOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oil0O_dataout <= wire_nl10OOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oil1i_dataout <= wire_nl10OOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oil1l_dataout <= wire_nl10OOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oil1O_dataout <= wire_nl10OOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oilii_dataout <= wire_nl10OOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oilil_dataout <= wire_nl10OOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OiliO_dataout <= wire_nl10OOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oilli_dataout <= wire_nl10OOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10Oilll_dataout <= wire_nl10OOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OillO_dataout <= wire_nl10OOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OilOi_dataout <= wire_nl10OOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl10OilOl_dataout <= wire_nl10Ol10i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O100l; + wire_nl10OilOO_dataout <= wire_nl10Ol10l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O01Ol; + wire_nl10OiO_dataout <= wire_nl1il0l_o AND NOT(wire_niO01O0O_dataout); + wire_nl10OiO0i_dataout <= wire_nl10Ol1iO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O001O; + wire_nl10OiO0l_dataout <= wire_nl10Ol1li_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O000i; + wire_nl10OiO0O_dataout <= wire_nl10Ol1ll_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O000l; + wire_nl10OiO1i_dataout <= wire_nl10Ol10O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O01OO; + wire_nl10OiO1l_dataout <= wire_nl10Ol1ii_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O001i; + wire_nl10OiO1O_dataout <= wire_nl10Ol1il_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O001l; + wire_nl10OiOii_dataout <= wire_nl10Ol1lO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O000O; + wire_nl10OiOil_dataout <= wire_nl10Ol1Oi_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00ii; + wire_nl10OiOiO_dataout <= wire_nl10Ol1Ol_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00il; + wire_nl10OiOli_dataout <= wire_nl10Ol1OO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00iO; + wire_nl10OiOll_dataout <= wire_nl10Ol01i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00li; + wire_nl10OiOlO_dataout <= wire_nl10Ol01l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00ll; + wire_nl10OiOOi_dataout <= wire_nl10Ol01O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00lO; + wire_nl10OiOOl_dataout <= wire_nl10Ol00i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00Oi; + wire_nl10OiOOO_dataout <= wire_nl10Ol00l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00Ol; + wire_nl10Ol00i_dataout <= k_vc0(39) WHEN niOi1iO1l = '1' ELSE wire_nl10OliiO_dataout; + wire_nl10Ol00l_dataout <= k_vc0(40) WHEN niOi1iO1l = '1' ELSE wire_nl10Olili_dataout; + wire_nl10Ol00O_dataout <= k_vc0(41) WHEN niOi1iO1l = '1' ELSE wire_nl10Olill_dataout; + wire_nl10Ol01i_dataout <= k_vc0(36) WHEN niOi1iO1l = '1' ELSE wire_nl10Oli0O_dataout; + wire_nl10Ol01l_dataout <= k_vc0(37) WHEN niOi1iO1l = '1' ELSE wire_nl10Oliii_dataout; + wire_nl10Ol01O_dataout <= k_vc0(38) WHEN niOi1iO1l = '1' ELSE wire_nl10Oliil_dataout; + wire_nl10Ol0ii_dataout <= k_vc0(42) WHEN niOi1iO1l = '1' ELSE wire_nl10OlilO_dataout; + wire_nl10Ol0il_dataout <= k_vc0(43) WHEN niOi1iO1l = '1' ELSE wire_nl10OliOi_dataout; + wire_nl10Ol0iO_dataout <= nl011l1il WHEN niOi1iiOl = '1' ELSE nl10O100l; + wire_nl10Ol0li_dataout <= nl011l0iO WHEN niOi1iiOl = '1' ELSE nl10O01Ol; + wire_nl10Ol0ll_dataout <= nl011l0li WHEN niOi1iiOl = '1' ELSE nl10O01OO; + wire_nl10Ol0lO_dataout <= nl011l0ll WHEN niOi1iiOl = '1' ELSE nl10O001i; + wire_nl10Ol0Oi_dataout <= nl011l0lO WHEN niOi1iiOl = '1' ELSE nl10O001l; + wire_nl10Ol0Ol_dataout <= nl011l0Oi WHEN niOi1iiOl = '1' ELSE nl10O001O; + wire_nl10Ol0OO_dataout <= nl011l0Ol WHEN niOi1iiOl = '1' ELSE nl10O000i; + wire_nl10Ol10i_dataout <= k_vc0(44) WHEN niOi1iO1l = '1' ELSE wire_nl10Ol0iO_dataout; + wire_nl10Ol10l_dataout <= k_vc0(45) WHEN niOi1iO1l = '1' ELSE wire_nl10Ol0li_dataout; + wire_nl10Ol10O_dataout <= k_vc0(46) WHEN niOi1iO1l = '1' ELSE wire_nl10Ol0ll_dataout; + wire_nl10Ol11i_dataout <= wire_nl10Ol00O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O00OO; + wire_nl10Ol11l_dataout <= wire_nl10Ol0ii_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O0i1i; + wire_nl10Ol11O_dataout <= wire_nl10Ol0il_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl10O0i1l; + wire_nl10Ol1ii_dataout <= k_vc0(47) WHEN niOi1iO1l = '1' ELSE wire_nl10Ol0lO_dataout; + wire_nl10Ol1il_dataout <= k_vc0(48) WHEN niOi1iO1l = '1' ELSE wire_nl10Ol0Oi_dataout; + wire_nl10Ol1iO_dataout <= k_vc0(49) WHEN niOi1iO1l = '1' ELSE wire_nl10Ol0Ol_dataout; + wire_nl10Ol1li_dataout <= k_vc0(50) WHEN niOi1iO1l = '1' ELSE wire_nl10Ol0OO_dataout; + wire_nl10Ol1ll_dataout <= k_vc0(51) WHEN niOi1iO1l = '1' ELSE wire_nl10Oli1i_dataout; + wire_nl10Ol1lO_dataout <= k_vc0(52) WHEN niOi1iO1l = '1' ELSE wire_nl10Oli1l_dataout; + wire_nl10Ol1Oi_dataout <= k_vc0(53) WHEN niOi1iO1l = '1' ELSE wire_nl10Oli1O_dataout; + wire_nl10Ol1Ol_dataout <= k_vc0(54) WHEN niOi1iO1l = '1' ELSE wire_nl10Oli0i_dataout; + wire_nl10Ol1OO_dataout <= k_vc0(55) WHEN niOi1iO1l = '1' ELSE wire_nl10Oli0l_dataout; + wire_nl10Oli_dataout <= wire_w_lg_niOO0lOOi2256w(0) AND NOT(wire_niO01O0O_dataout); + wire_nl10Oli0i_dataout <= nl011li1O WHEN niOi1iiOl = '1' ELSE nl10O00il; + wire_nl10Oli0l_dataout <= nl011li0i WHEN niOi1iiOl = '1' ELSE nl10O00iO; + wire_nl10Oli0O_dataout <= nl011li0l WHEN niOi1iiOl = '1' ELSE nl10O00li; + wire_nl10Oli1i_dataout <= nl011l0OO WHEN niOi1iiOl = '1' ELSE nl10O000l; + wire_nl10Oli1l_dataout <= nl011li1i WHEN niOi1iiOl = '1' ELSE nl10O000O; + wire_nl10Oli1O_dataout <= nl011li1l WHEN niOi1iiOl = '1' ELSE nl10O00ii; + wire_nl10Oliii_dataout <= nl011li0O WHEN niOi1iiOl = '1' ELSE nl10O00ll; + wire_nl10Oliil_dataout <= nl011liii WHEN niOi1iiOl = '1' ELSE nl10O00lO; + wire_nl10OliiO_dataout <= nl011liil WHEN niOi1iiOl = '1' ELSE nl10O00Oi; + wire_nl10Olili_dataout <= nl011liiO WHEN niOi1iiOl = '1' ELSE nl10O00Ol; + wire_nl10Olill_dataout <= nl011lili WHEN niOi1iiOl = '1' ELSE nl10O00OO; + wire_nl10OlilO_dataout <= nl011lill WHEN niOi1iiOl = '1' ELSE nl10O0i1i; + wire_nl10OliOi_dataout <= nl011lilO WHEN niOi1iiOl = '1' ELSE nl10O0i1l; + wire_nl10OliOO_dataout <= wire_nl10OlO0l_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0i1O; + wire_nl10Oll_dataout <= wire_w_lg_niOO0lOOl2255w(0) AND NOT(wire_niO01O0O_dataout); + wire_nl10Oll0i_dataout <= wire_nl10OlOiO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0iii; + wire_nl10Oll0l_dataout <= wire_nl10OlOli_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0iil; + wire_nl10Oll0O_dataout <= wire_nl10OlOll_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0iiO; + wire_nl10Oll1i_dataout <= wire_nl10OlO0O_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0i0i; + wire_nl10Oll1l_dataout <= wire_nl10OlOii_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0i0l; + wire_nl10Oll1O_dataout <= wire_nl10OlOil_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0i0O; + wire_nl10Ollii_dataout <= wire_nl10OlOlO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0ili; + wire_nl10Ollil_dataout <= wire_nl10OlOOi_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0ill; + wire_nl10OlliO_dataout <= wire_nl10OlOOl_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0ilO; + wire_nl10Ollli_dataout <= wire_nl10OlOOO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0iOi; + wire_nl10Ollll_dataout <= wire_nl10OO11i_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl10O0iOl; + wire_nl10OlllO_dataout <= wire_nl10OO11l_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OO0OO_dataout; + wire_nl10OllOi_dataout <= wire_nl10OO11O_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OOi1i_dataout; + wire_nl10OllOl_dataout <= wire_nl10OO10i_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OOi1l_dataout; + wire_nl10OllOO_dataout <= wire_nl10OO10l_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OOi1O_dataout; + wire_nl10OlO_dataout <= wire_w_lg_niOO0O11l2254w(0) AND NOT(wire_niO01O0O_dataout); + wire_nl10OlO0i_dataout <= wire_nl10OO1iO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OOiii_dataout; + wire_nl10OlO0l_dataout <= k_vc0(28) WHEN niOi1iO1l = '1' ELSE wire_nl10OO1li_dataout; + wire_nl10OlO0O_dataout <= k_vc0(29) WHEN niOi1iO1l = '1' ELSE wire_nl10OO1ll_dataout; + wire_nl10OlO1i_dataout <= wire_nl10OO10O_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OOi0i_dataout; + wire_nl10OlO1l_dataout <= wire_nl10OO1ii_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OOi0l_dataout; + wire_nl10OlO1O_dataout <= wire_nl10OO1il_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE wire_nl10OOi0O_dataout; + wire_nl10OlOii_dataout <= k_vc0(30) WHEN niOi1iO1l = '1' ELSE wire_nl10OO1lO_dataout; + wire_nl10OlOil_dataout <= k_vc0(31) WHEN niOi1iO1l = '1' ELSE wire_nl10OO1Oi_dataout; + wire_nl10OlOiO_dataout <= k_vc0(32) WHEN niOi1iO1l = '1' ELSE wire_nl10OO1Ol_dataout; + wire_nl10OlOli_dataout <= k_vc0(33) WHEN niOi1iO1l = '1' ELSE wire_nl10OO1OO_dataout; + wire_nl10OlOll_dataout <= k_vc0(34) WHEN niOi1iO1l = '1' ELSE wire_nl10OO01i_dataout; + wire_nl10OlOlO_dataout <= k_vc0(35) WHEN niOi1iO1l = '1' ELSE wire_nl10OO01l_dataout; + wire_nl10OlOOi_dataout <= wire_nl10OO01O_dataout AND NOT(niOi1iO1l); + wire_nl10OlOOl_dataout <= wire_nl10OO00i_dataout AND NOT(niOi1iO1l); + wire_nl10OlOOO_dataout <= wire_nl10OO00l_dataout AND NOT(niOi1iO1l); + wire_nl10OO00i_dataout <= nl011li1l WHEN niOi1iiOO = '1' ELSE nl10O0ilO; + wire_nl10OO00l_dataout <= nl011li1O WHEN niOi1iiOO = '1' ELSE nl10O0iOi; + wire_nl10OO00O_dataout <= nl011li0i WHEN niOi1iiOO = '1' ELSE nl10O0iOl; + wire_nl10OO01i_dataout <= nl011l0Ol WHEN niOi1iiOO = '1' ELSE nl10O0iiO; + wire_nl10OO01l_dataout <= nl011l0OO WHEN niOi1iiOO = '1' ELSE nl10O0ili; + wire_nl10OO01O_dataout <= nl011li1i WHEN niOi1iiOO = '1' ELSE nl10O0ill; + wire_nl10OO0ii_dataout <= nl011li0l WHEN niOi1iiOO = '1' ELSE wire_nl10OO0OO_dataout; + wire_nl10OO0il_dataout <= nl011li0O WHEN niOi1iiOO = '1' ELSE wire_nl10OOi1i_dataout; + wire_nl10OO0iO_dataout <= nl011liii WHEN niOi1iiOO = '1' ELSE wire_nl10OOi1l_dataout; + wire_nl10OO0li_dataout <= nl011liil WHEN niOi1iiOO = '1' ELSE wire_nl10OOi1O_dataout; + wire_nl10OO0ll_dataout <= nl011liiO WHEN niOi1iiOO = '1' ELSE wire_nl10OOi0i_dataout; + wire_nl10OO0lO_dataout <= nl011lili WHEN niOi1iiOO = '1' ELSE wire_nl10OOi0l_dataout; + wire_nl10OO0Oi_dataout <= nl011lill WHEN niOi1iiOO = '1' ELSE wire_nl10OOi0O_dataout; + wire_nl10OO0Ol_dataout <= nl011lilO WHEN niOi1iiOO = '1' ELSE wire_nl10OOiii_dataout; + wire_nl10OO0OO_dataout <= k_vc0(20) WHEN niOi1iO1l = '1' ELSE wire_nl10OOiil_dataout; + wire_nl10OO10i_dataout <= k_vc0(22) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0iO_dataout; + wire_nl10OO10l_dataout <= k_vc0(23) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0li_dataout; + wire_nl10OO10O_dataout <= k_vc0(24) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0ll_dataout; + wire_nl10OO11i_dataout <= wire_nl10OO00O_dataout AND NOT(niOi1iO1l); + wire_nl10OO11l_dataout <= k_vc0(20) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0ii_dataout; + wire_nl10OO11O_dataout <= k_vc0(21) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0il_dataout; + wire_nl10OO1ii_dataout <= k_vc0(25) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0lO_dataout; + wire_nl10OO1il_dataout <= k_vc0(26) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0Oi_dataout; + wire_nl10OO1iO_dataout <= k_vc0(27) WHEN niOi1iO1l = '1' ELSE wire_nl10OO0Ol_dataout; + wire_nl10OO1li_dataout <= nl011l1il WHEN niOi1iiOO = '1' ELSE nl10O0i1O; + wire_nl10OO1ll_dataout <= nl011l0iO WHEN niOi1iiOO = '1' ELSE nl10O0i0i; + wire_nl10OO1lO_dataout <= nl011l0li WHEN niOi1iiOO = '1' ELSE nl10O0i0l; + wire_nl10OO1Oi_dataout <= nl011l0ll WHEN niOi1iiOO = '1' ELSE nl10O0i0O; + wire_nl10OO1Ol_dataout <= nl011l0lO WHEN niOi1iiOO = '1' ELSE nl10O0iii; + wire_nl10OO1OO_dataout <= nl011l0Oi WHEN niOi1iiOO = '1' ELSE nl10O0iil; + wire_nl10OOi_dataout <= wire_w_lg_niOO0O11O2253w(0) AND NOT(wire_niO01O0O_dataout); + wire_nl10OOi0i_dataout <= k_vc0(24) WHEN niOi1iO1l = '1' ELSE wire_nl10OOilO_dataout; + wire_nl10OOi0l_dataout <= k_vc0(25) WHEN niOi1iO1l = '1' ELSE wire_nl10OOiOi_dataout; + wire_nl10OOi0O_dataout <= k_vc0(26) WHEN niOi1iO1l = '1' ELSE wire_nl10OOiOl_dataout; + wire_nl10OOi1i_dataout <= k_vc0(21) WHEN niOi1iO1l = '1' ELSE wire_nl10OOiiO_dataout; + wire_nl10OOi1l_dataout <= k_vc0(22) WHEN niOi1iO1l = '1' ELSE wire_nl10OOili_dataout; + wire_nl10OOi1O_dataout <= k_vc0(23) WHEN niOi1iO1l = '1' ELSE wire_nl10OOill_dataout; + wire_nl10OOiii_dataout <= k_vc0(27) WHEN niOi1iO1l = '1' ELSE wire_nl10OOiOO_dataout; + wire_nl10OOiil_dataout <= nl011li0l WHEN niOi1iiOO = '1' ELSE nl10O0iOO; + wire_nl10OOiiO_dataout <= nl011li0O WHEN niOi1iiOO = '1' ELSE nl10O0l1i; + wire_nl10OOili_dataout <= nl011liii WHEN niOi1iiOO = '1' ELSE nl10O0l1l; + wire_nl10OOill_dataout <= nl011liil WHEN niOi1iiOO = '1' ELSE nl10O0l1O; + wire_nl10OOilO_dataout <= nl011liiO WHEN niOi1iiOO = '1' ELSE nl10O0l0i; + wire_nl10OOiOi_dataout <= nl011lili WHEN niOi1iiOO = '1' ELSE nl10O0l0l; + wire_nl10OOiOl_dataout <= nl011lill WHEN niOi1iiOO = '1' ELSE nl10O0l0O; + wire_nl10OOiOO_dataout <= nl011lilO WHEN niOi1iiOO = '1' ELSE nl10O0lii; + wire_nl10OOl0i_dataout <= k_vc0(10) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOiO_dataout; + wire_nl10OOl0l_dataout <= k_vc0(11) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOli_dataout; + wire_nl10OOl0O_dataout <= k_vc0(12) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOll_dataout; + wire_nl10OOl1l_dataout <= k_vc0(8) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOii_dataout; + wire_nl10OOl1O_dataout <= k_vc0(9) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOil_dataout; + wire_nl10OOlii_dataout <= k_vc0(13) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOlO_dataout; + wire_nl10OOlil_dataout <= k_vc0(14) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOOi_dataout; + wire_nl10OOliO_dataout <= k_vc0(15) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOOl_dataout; + wire_nl10OOlli_dataout <= k_vc0(16) WHEN niOi1iO1l = '1' ELSE wire_nl10OOOOO_dataout; + wire_nl10OOlll_dataout <= k_vc0(17) WHEN niOi1iO1l = '1' ELSE wire_nl1i1111i_dataout; + wire_nl10OOllO_dataout <= k_vc0(18) WHEN niOi1iO1l = '1' ELSE wire_nl1i1111l_dataout; + wire_nl10OOlOi_dataout <= k_vc0(19) WHEN niOi1iO1l = '1' ELSE wire_nl1i1111O_dataout; + wire_nl10OOlOl_dataout <= k_vc0(0) WHEN niOi1iO1l = '1' ELSE wire_nl1i1110i_dataout; + wire_nl10OOlOO_dataout <= k_vc0(1) WHEN niOi1iO1l = '1' ELSE wire_nl1i1110l_dataout; + wire_nl10OOO0i_dataout <= k_vc0(5) WHEN niOi1iO1l = '1' ELSE wire_nl1i111iO_dataout; + wire_nl10OOO0l_dataout <= k_vc0(6) WHEN niOi1iO1l = '1' ELSE wire_nl1i111li_dataout; + wire_nl10OOO0O_dataout <= k_vc0(7) WHEN niOi1iO1l = '1' ELSE wire_nl1i111ll_dataout; + wire_nl10OOO1i_dataout <= k_vc0(2) WHEN niOi1iO1l = '1' ELSE wire_nl1i1110O_dataout; + wire_nl10OOO1l_dataout <= k_vc0(3) WHEN niOi1iO1l = '1' ELSE wire_nl1i111ii_dataout; + wire_nl10OOO1O_dataout <= k_vc0(4) WHEN niOi1iO1l = '1' ELSE wire_nl1i111il_dataout; + wire_nl10OOOii_dataout <= nl011l1il WHEN niOi1il1i = '1' ELSE nl10O0O1i; + wire_nl10OOOil_dataout <= nl011l0iO WHEN niOi1il1i = '1' ELSE nl10O0O1l; + wire_nl10OOOiO_dataout <= nl011l0li WHEN niOi1il1i = '1' ELSE nl10O0O1O; + wire_nl10OOOli_dataout <= nl011l0ll WHEN niOi1il1i = '1' ELSE nl10O0O0i; + wire_nl10OOOll_dataout <= nl011l0lO WHEN niOi1il1i = '1' ELSE nl10O0O0l; + wire_nl10OOOlO_dataout <= nl011l0Oi WHEN niOi1il1i = '1' ELSE nl10O0O0O; + wire_nl10OOOOi_dataout <= nl011l0Ol WHEN niOi1il1i = '1' ELSE nl10O0Oii; + wire_nl10OOOOl_dataout <= nl011l0OO WHEN niOi1il1i = '1' ELSE nl10O0Oil; + wire_nl10OOOOO_dataout <= nl011li1i WHEN niOi1il1i = '1' ELSE nl10O0OiO; + wire_nl110000i_dataout <= wire_nl110i01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110000l_dataout <= wire_nl110i00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110000O_dataout <= wire_nl110i00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110001i_dataout <= wire_nl110i1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110001l_dataout <= wire_nl110i01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110001O_dataout <= wire_nl110i01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000ii_dataout <= wire_nl110i00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000il_dataout <= wire_nl110ii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000iO_dataout <= wire_nl110iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000l_dataout <= nl11001O AND NOT(wire_niO01O0O_dataout); + wire_nl11000li_dataout <= wire_nl110iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000ll_dataout <= wire_nl110iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000lO_dataout <= wire_nl110iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000O_dataout <= nl1101Ol AND NOT(wire_niO01O0O_dataout); + wire_nl11000Oi_dataout <= wire_nl110iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000Ol_dataout <= wire_nl110iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11000OO_dataout <= wire_nl110iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110010i_dataout <= wire_nl110i11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110010l_dataout <= wire_nl110i10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110010O_dataout <= wire_nl110i10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110011i_dataout <= wire_nl1100OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110011l_dataout <= wire_nl1100OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110011O_dataout <= wire_nl110i11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001ii_dataout <= wire_nl110i10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001il_dataout <= wire_nl110i1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001iO_dataout <= wire_nl110i1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001l_dataout <= nl11000i AND NOT(wire_niO01O0O_dataout); + wire_nl11001li_dataout <= wire_nl110i1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001ll_dataout <= wire_nl110i1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001lO_dataout <= wire_nl110i1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001Oi_dataout <= wire_nl110i1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001Ol_dataout <= wire_nl110i1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11001OO_dataout <= wire_nl110i1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100i_dataout <= lmi_din(24) AND NOT(wire_niO01l0O_dataout); + wire_nl1100i0i_dataout <= wire_nl110i0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100i0l_dataout <= wire_nl110i0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100i0O_dataout <= wire_nl110i0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100i1i_dataout <= wire_nl110i0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100i1l_dataout <= wire_nl110i0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100i1O_dataout <= wire_nl110i0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100iii_dataout <= wire_nl110i0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100iil_dataout <= wire_nl110i0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100iiO_dataout <= wire_nl110ii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100il_dataout <= wire_nl1100li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1100ili_dataout <= wire_nl110ii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100ill_dataout <= wire_nl110ii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100ilO_dataout <= wire_nl110ii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1100iO_dataout <= wire_nl1100Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1100iOi_dataout <= wire_nl1100l0i_dataout WHEN niOi1010i = '1' ELSE nl111ll1l; + wire_nl1100iOl_dataout <= wire_nl1100l0l_dataout WHEN niOi1010i = '1' ELSE nl111OO1i; + wire_nl1100iOO_dataout <= wire_nl1100l0O_dataout WHEN niOi1010i = '1' ELSE nl111OO1l; + wire_nl1100l_dataout <= lmi_din(25) AND NOT(wire_niO01l0O_dataout); + wire_nl1100l0i_dataout <= niOi1011l WHEN niOi1010O = '1' ELSE nl111ll1l; + wire_nl1100l0l_dataout <= niOi1011O WHEN niOi1010O = '1' ELSE nl111OO1i; + wire_nl1100l0O_dataout <= niOi1011l WHEN niOi101il = '1' ELSE nl111OO1l; + wire_nl1100l1i_dataout <= wire_nl1100lii_dataout WHEN niOi1010i = '1' ELSE nl111OO1O; + wire_nl1100l1l_dataout <= wire_nl1100lil_dataout WHEN niOi1010i = '1' ELSE nl111OO0i; + wire_nl1100l1O_dataout <= wire_nl1100liO_dataout WHEN niOi1010i = '1' ELSE nl111OO0l; + wire_nl1100li_dataout <= wire_niOOO0O_w_lg_nl11000i8359w(0) WHEN (wire_w_lg_niOO1ilOi8360w(0) AND wire_w_lg_w_swup_in_range8358w8361w(0)) = '1' ELSE nl11000i; + wire_nl1100lii_dataout <= niOi1011O WHEN niOi101il = '1' ELSE nl111OO1O; + wire_nl1100lil_dataout <= niOi1011l WHEN niOi101iO = '1' ELSE nl111OO0i; + wire_nl1100liO_dataout <= niOi1011O WHEN niOi101iO = '1' ELSE nl111OO0l; + wire_nl1100lll_dataout <= wire_nilOl00l_dataout WHEN niOi1010l = '1' ELSE nl111OO0O; + wire_nl1100llO_dataout <= wire_nilOl00O_dataout WHEN niOi1010l = '1' ELSE nl111OOii; + wire_nl1100lOi_dataout <= wire_nilOl0ii_dataout WHEN niOi1010l = '1' ELSE nl111OOil; + wire_nl1100lOl_dataout <= wire_nilOl0il_dataout WHEN niOi1010l = '1' ELSE nl111OOiO; + wire_nl1100lOO_dataout <= wire_nilOl0iO_dataout WHEN niOi1010l = '1' ELSE nl111OOli; + wire_nl1100O_dataout <= lmi_din(26) AND NOT(wire_niO01l0O_dataout); + wire_nl1100O0i_dataout <= wire_nilOl0Oi_dataout WHEN niOi1010l = '1' ELSE nl111OOOl; + wire_nl1100O0l_dataout <= wire_nilOl0Ol_dataout WHEN niOi1010l = '1' ELSE nl111OOOO; + wire_nl1100O0O_dataout <= wire_nilOl0OO_dataout WHEN niOi1010l = '1' ELSE nl110111i; + wire_nl1100O1i_dataout <= wire_nilOl0li_dataout WHEN niOi1010l = '1' ELSE nl111OOll; + wire_nl1100O1l_dataout <= wire_nilOl0ll_dataout WHEN niOi1010l = '1' ELSE nl111OOlO; + wire_nl1100O1O_dataout <= wire_nilOl0lO_dataout WHEN niOi1010l = '1' ELSE nl111OOOi; + wire_nl1100Oi_dataout <= nl1100ii WHEN niOO1ilOi = '1' ELSE swup_in(0); + wire_nl1100Oii_dataout <= wire_nilOli1i_dataout WHEN niOi1010l = '1' ELSE nl110111l; + wire_nl1100Oil_dataout <= wire_nilOli1l_dataout WHEN niOi1010l = '1' ELSE nl110111O; + wire_nl1100OiO_dataout <= wire_nilOli1O_dataout WHEN niOi1010l = '1' ELSE nl110110i; + wire_nl1100Oli_dataout <= wire_nilOli0i_dataout WHEN niOi1010l = '1' ELSE nl110110l; + wire_nl1100Oll_dataout <= wire_nilOli0l_dataout WHEN niOi1010l = '1' ELSE nl110110O; + wire_nl1100OlO_dataout <= wire_nilOli0O_dataout WHEN niOi1010l = '1' ELSE nl11011ii; + wire_nl1100OOi_dataout <= wire_nilOliii_dataout WHEN niOi1010l = '1' ELSE nl11011il; + wire_nl1100OOl_dataout <= wire_nilOliil_dataout WHEN niOi1010l = '1' ELSE nl11011iO; + wire_nl1100OOO_dataout <= wire_nilOliiO_dataout WHEN niOi1010l = '1' ELSE nl11011li; + wire_nl11010l_dataout <= nl111OOl WHEN niOO1illO = '1' ELSE wire_nlOi0Oill_dataout; + wire_nl11011i_dataout <= wire_nl11010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11011l_dataout <= wire_nl1000i_w_lg_nl111Oll8366w(0) WHEN (wire_w_lg_niOO1illO8367w(0) AND (wire_nlOi0Oill_dataout XOR nl111OOl)) = '1' ELSE nl111Oll; + wire_nl1101i_dataout <= lmi_din(21) AND NOT(wire_niO01l0O_dataout); + wire_nl1101il_dataout <= wire_nl1101iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101iO_dataout <= wire_nl1000i_w_lg_nl1101ll8363w(0) WHEN (nl11001O XOR nl11001i) = '1' ELSE nl1101ll; + wire_nl1101l_dataout <= lmi_din(22) AND NOT(wire_niO01l0O_dataout); + wire_nl1101lii_dataout <= wire_nl1100iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101lil_dataout <= wire_nl1100iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101liO_dataout <= wire_nl1100iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101lli_dataout <= wire_nl1100l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101lll_dataout <= wire_nl1100l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101llO_dataout <= wire_nl1100l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101lOi_dataout <= wire_nl1100lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101lOl_dataout <= wire_nl1100llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101lOO_dataout <= wire_nl1100lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101O_dataout <= lmi_din(23) AND NOT(wire_niO01l0O_dataout); + wire_nl1101O0i_dataout <= wire_nl1100O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101O0l_dataout <= wire_nl1100O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101O0O_dataout <= wire_nl1100O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101O1i_dataout <= wire_nl1100lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101O1l_dataout <= wire_nl1100lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101O1O_dataout <= wire_nl1100O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101Oi_dataout <= nl11001i AND NOT(wire_niO01l0O_dataout); + wire_nl1101Oii_dataout <= wire_nl1100O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101Oil_dataout <= wire_nl1100O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101OiO_dataout <= wire_nl1100Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101Oli_dataout <= wire_nl1100Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101Oll_dataout <= wire_nl1100OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101OlO_dataout <= wire_nl1100Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101OO_dataout <= nl1101ii AND NOT(wire_niO01l0O_dataout); + wire_nl1101OOi_dataout <= wire_nl1100Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101OOl_dataout <= wire_nl1100OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1101OOO_dataout <= wire_nl1100OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110i00i_dataout <= wire_nilOliii_dataout WHEN niOi101ii = '1' ELSE nl11010Oi; + wire_nl110i00l_dataout <= wire_nilOliil_dataout WHEN niOi101ii = '1' ELSE nl11010Ol; + wire_nl110i00O_dataout <= wire_nilOliiO_dataout WHEN niOi101ii = '1' ELSE nl11010OO; + wire_nl110i01i_dataout <= wire_nilOli0i_dataout WHEN niOi101ii = '1' ELSE nl11010li; + wire_nl110i01l_dataout <= wire_nilOli0l_dataout WHEN niOi101ii = '1' ELSE nl11010ll; + wire_nl110i01O_dataout <= wire_nilOli0O_dataout WHEN niOi101ii = '1' ELSE nl11010lO; + wire_nl110i0il_dataout <= wire_nilOl00l_dataout WHEN niOi101li = '1' ELSE nl1101iiO; + wire_nl110i0iO_dataout <= wire_nilOl00O_dataout WHEN niOi101li = '1' ELSE nl1101ili; + wire_nl110i0li_dataout <= wire_nilOl0ii_dataout WHEN niOi101li = '1' ELSE nl1101ill; + wire_nl110i0ll_dataout <= wire_nilOl0il_dataout WHEN niOi101li = '1' ELSE nl1101ilO; + wire_nl110i0lO_dataout <= wire_nilOl0iO_dataout WHEN niOi101li = '1' ELSE nl1101iOi; + wire_nl110i0O_dataout <= nl110iiO AND NOT(wire_niO01l0O_dataout); + wire_nl110i0Oi_dataout <= wire_nilOl0li_dataout WHEN niOi101li = '1' ELSE nl1101iOl; + wire_nl110i0Ol_dataout <= wire_nilOl0ll_dataout WHEN niOi101li = '1' ELSE nl1101iOO; + wire_nl110i0OO_dataout <= wire_nilOl0lO_dataout WHEN niOi101li = '1' ELSE nl1101l1i; + wire_nl110i10i_dataout <= wire_nilOl0ii_dataout WHEN niOi101ii = '1' ELSE nl11011Oi; + wire_nl110i10l_dataout <= wire_nilOl0il_dataout WHEN niOi101ii = '1' ELSE nl11011Ol; + wire_nl110i10O_dataout <= wire_nilOl0iO_dataout WHEN niOi101ii = '1' ELSE nl11011OO; + wire_nl110i11l_dataout <= wire_nilOl00l_dataout WHEN niOi101ii = '1' ELSE nl11011ll; + wire_nl110i11O_dataout <= wire_nilOl00O_dataout WHEN niOi101ii = '1' ELSE nl11011lO; + wire_nl110i1i_dataout <= wire_nl110i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110i1ii_dataout <= wire_nilOl0li_dataout WHEN niOi101ii = '1' ELSE nl110101i; + wire_nl110i1il_dataout <= wire_nilOl0ll_dataout WHEN niOi101ii = '1' ELSE nl110101l; + wire_nl110i1iO_dataout <= wire_nilOl0lO_dataout WHEN niOi101ii = '1' ELSE nl110101O; + wire_nl110i1l_dataout <= wire_nl1000i_w_lg_nl110i0i8355w(0) WHEN (nl110ill XOR nl110iiO) = '1' ELSE nl110i0i; + wire_nl110i1li_dataout <= wire_nilOl0Oi_dataout WHEN niOi101ii = '1' ELSE nl110100i; + wire_nl110i1ll_dataout <= wire_nilOl0Ol_dataout WHEN niOi101ii = '1' ELSE nl110100l; + wire_nl110i1lO_dataout <= wire_nilOl0OO_dataout WHEN niOi101ii = '1' ELSE nl110100O; + wire_nl110i1Oi_dataout <= wire_nilOli1i_dataout WHEN niOi101ii = '1' ELSE nl11010ii; + wire_nl110i1Ol_dataout <= wire_nilOli1l_dataout WHEN niOi101ii = '1' ELSE nl11010il; + wire_nl110i1OO_dataout <= wire_nilOli1O_dataout WHEN niOi101ii = '1' ELSE nl11010iO; + wire_nl110ii_dataout <= lmi_din(27) AND NOT(wire_niO01l0O_dataout); + wire_nl110ii0i_dataout <= wire_nilOli1i_dataout WHEN niOi101li = '1' ELSE nl1101l0l; + wire_nl110ii0O_dataout <= wire_nilOli1l_dataout WHEN niOi101li = '1' ELSE nl1101i1i; + wire_nl110ii1i_dataout <= wire_nilOl0Oi_dataout WHEN niOi101li = '1' ELSE nl1101l1l; + wire_nl110ii1l_dataout <= wire_nilOl0Ol_dataout WHEN niOi101li = '1' ELSE nl1101l1O; + wire_nl110ii1O_dataout <= wire_nilOl0OO_dataout WHEN niOi101li = '1' ELSE nl1101l0i; + wire_nl110iiii_dataout <= wire_nilOli1O_dataout WHEN niOi101li = '1' ELSE nl1101i1l; + wire_nl110iiil_dataout <= wire_nilOli0i_dataout WHEN niOi101li = '1' ELSE nl1101i1O; + wire_nl110iiiO_dataout <= wire_nilOli0l_dataout WHEN niOi101li = '1' ELSE nl1101i0i; + wire_nl110iil_dataout <= nl1100OO AND NOT(wire_niO01l0O_dataout); + wire_nl110iili_dataout <= wire_nilOli0O_dataout WHEN niOi101li = '1' ELSE nl1101i0l; + wire_nl110iill_dataout <= wire_nilOliii_dataout WHEN niOi101li = '1' ELSE nl1101i0O; + wire_nl110iilO_dataout <= wire_nilOliil_dataout WHEN niOi101li = '1' ELSE nl1101iii; + wire_nl110iiOi_dataout <= wire_nilOliiO_dataout WHEN niOi101li = '1' ELSE nl1101iil; + wire_nl110iiOl_dataout <= wire_nl110iOli_o(0) WHEN niOi101lO = '1' ELSE wire_nl110illl_dataout; + wire_nl110iiOl_w_lg_dataout61343w(0) <= NOT wire_nl110iiOl_dataout; + wire_nl110iiOO_dataout <= wire_nl110iOli_o(1) WHEN niOi101lO = '1' ELSE wire_nl110illO_dataout; + wire_nl110iiOO_w_lg_dataout61345w(0) <= NOT wire_nl110iiOO_dataout; + wire_nl110il_dataout <= lmi_din(28) AND NOT(wire_niO01l0O_dataout); + wire_nl110il0i_dataout <= wire_nl110iOli_o(5) WHEN niOi101lO = '1' ELSE wire_nl110iO1i_dataout; + wire_nl110il0i_w_lg_dataout61353w(0) <= NOT wire_nl110il0i_dataout; + wire_nl110il0l_dataout <= wire_nl110iOli_o(6) WHEN niOi101lO = '1' ELSE wire_nl110iO1l_dataout; + wire_nl110il0l_w_lg_dataout61355w(0) <= NOT wire_nl110il0l_dataout; + wire_nl110il0O_dataout <= wire_nl110iOli_o(7) WHEN niOi101lO = '1' ELSE wire_nl110iO1O_dataout; + wire_nl110il0O_w_lg_dataout61357w(0) <= NOT wire_nl110il0O_dataout; + wire_nl110il1i_dataout <= wire_nl110iOli_o(2) WHEN niOi101lO = '1' ELSE wire_nl110ilOi_dataout; + wire_nl110il1i_w_lg_dataout61347w(0) <= NOT wire_nl110il1i_dataout; + wire_nl110il1l_dataout <= wire_nl110iOli_o(3) WHEN niOi101lO = '1' ELSE wire_nl110ilOl_dataout; + wire_nl110il1l_w_lg_dataout61349w(0) <= NOT wire_nl110il1l_dataout; + wire_nl110il1O_dataout <= wire_nl110iOli_o(4) WHEN niOi101lO = '1' ELSE wire_nl110ilOO_dataout; + wire_nl110il1O_w_lg_dataout61351w(0) <= NOT wire_nl110il1O_dataout; + wire_nl110ili_dataout <= nl110ilO AND NOT(wire_niO01O0O_dataout); + wire_nl110ilii_dataout <= wire_nl110iOli_o(8) WHEN niOi101lO = '1' ELSE wire_nl110iO0i_dataout; + wire_nl110ilii_w_lg_dataout61359w(0) <= NOT wire_nl110ilii_dataout; + wire_nl110ilil_dataout <= wire_nl110iOli_o(9) WHEN niOi101lO = '1' ELSE wire_nl110iO0l_dataout; + wire_nl110ilil_w_lg_dataout61361w(0) <= NOT wire_nl110ilil_dataout; + wire_nl110iliO_dataout <= wire_nl110iOli_o(10) WHEN niOi101lO = '1' ELSE wire_nl110iO0O_dataout; + wire_nl110iliO_w_lg_dataout61363w(0) <= NOT wire_nl110iliO_dataout; + wire_nl110illi_dataout <= wire_nl110iOli_o(11) WHEN niOi101lO = '1' ELSE wire_nl110iOii_dataout; + wire_nl110illi_w_lg_dataout61365w(0) <= NOT wire_nl110illi_dataout; + wire_nl110illl_dataout <= wire_nl110iOil_o(1) WHEN niOi101Oi = '1' ELSE nl1101l0O; + wire_nl110illO_dataout <= wire_nl110iOil_o(2) WHEN niOi101Oi = '1' ELSE nl110Oi1l; + wire_nl110ilOi_dataout <= wire_nl110iOil_o(3) WHEN niOi101Oi = '1' ELSE nl110Oi1O; + wire_nl110ilOl_dataout <= wire_nl110iOil_o(4) WHEN niOi101Oi = '1' ELSE nl110Oi0i; + wire_nl110ilOO_dataout <= wire_nl110iOil_o(5) WHEN niOi101Oi = '1' ELSE nl110Oi0l; + wire_nl110iO_dataout <= lmi_din(29) AND NOT(wire_niO01l0O_dataout); + wire_nl110iO0i_dataout <= wire_nl110iOil_o(9) WHEN niOi101Oi = '1' ELSE nl110OiiO; + wire_nl110iO0l_dataout <= wire_nl110iOil_o(10) WHEN niOi101Oi = '1' ELSE nl110Oili; + wire_nl110iO0O_dataout <= wire_nl110iOil_o(11) WHEN niOi101Oi = '1' ELSE nl110Oill; + wire_nl110iO1i_dataout <= wire_nl110iOil_o(6) WHEN niOi101Oi = '1' ELSE nl110Oi0O; + wire_nl110iO1l_dataout <= wire_nl110iOil_o(7) WHEN niOi101Oi = '1' ELSE nl110Oiii; + wire_nl110iO1O_dataout <= wire_nl110iOil_o(8) WHEN niOi101Oi = '1' ELSE nl110Oiil; + wire_nl110iOi_dataout <= nl110ill AND NOT(wire_niO01O0O_dataout); + wire_nl110iOii_dataout <= wire_nl110iOil_o(12) WHEN niOi101Oi = '1' ELSE nl110OilO; + wire_nl110iOl_dataout <= nl110iii AND NOT(wire_niO01O0O_dataout); + wire_nl110iOlO_dataout <= wire_nl110l1Ol_o(0) WHEN niOi101lO = '1' ELSE wire_nl110l10l_dataout; + wire_nl110iOlO_w_lg_dataout61198w(0) <= NOT wire_nl110iOlO_dataout; + wire_nl110iOOi_dataout <= wire_nl110l1Ol_o(1) WHEN niOi101lO = '1' ELSE wire_nl110l10O_dataout; + wire_nl110iOOi_w_lg_dataout61200w(0) <= NOT wire_nl110iOOi_dataout; + wire_nl110iOOl_dataout <= wire_nl110l1Ol_o(2) WHEN niOi101lO = '1' ELSE wire_nl110l1ii_dataout; + wire_nl110iOOl_w_lg_dataout61202w(0) <= NOT wire_nl110iOOl_dataout; + wire_nl110iOOO_dataout <= wire_nl110l1Ol_o(3) WHEN niOi101lO = '1' ELSE wire_nl110l1il_dataout; + wire_nl110iOOO_w_lg_dataout61204w(0) <= NOT wire_nl110iOOO_dataout; + wire_nl110l00i_dataout <= wire_nl110lill_o(4) WHEN niOi101OO = '1' ELSE wire_nl110li1i_dataout; + wire_nl110l00i_w_lg_dataout61091w(0) <= NOT wire_nl110l00i_dataout; + wire_nl110l00l_dataout <= wire_nl110lill_o(5) WHEN niOi101OO = '1' ELSE wire_nl110li1l_dataout; + wire_nl110l00l_w_lg_dataout61093w(0) <= NOT wire_nl110l00l_dataout; + wire_nl110l00O_dataout <= wire_nl110lill_o(6) WHEN niOi101OO = '1' ELSE wire_nl110li1O_dataout; + wire_nl110l00O_w_lg_dataout61095w(0) <= NOT wire_nl110l00O_dataout; + wire_nl110l01i_dataout <= wire_nl110lill_o(1) WHEN niOi101OO = '1' ELSE wire_nl110l0Oi_dataout; + wire_nl110l01i_w_lg_dataout61085w(0) <= NOT wire_nl110l01i_dataout; + wire_nl110l01l_dataout <= wire_nl110lill_o(2) WHEN niOi101OO = '1' ELSE wire_nl110l0Ol_dataout; + wire_nl110l01l_w_lg_dataout61087w(0) <= NOT wire_nl110l01l_dataout; + wire_nl110l01O_dataout <= wire_nl110lill_o(3) WHEN niOi101OO = '1' ELSE wire_nl110l0OO_dataout; + wire_nl110l01O_w_lg_dataout61089w(0) <= NOT wire_nl110l01O_dataout; + wire_nl110l0ii_dataout <= wire_nl110lill_o(7) WHEN niOi101OO = '1' ELSE wire_nl110li0i_dataout; + wire_nl110l0ii_w_lg_dataout61097w(0) <= NOT wire_nl110l0ii_dataout; + wire_nl110l0il_dataout <= wire_nl110lill_o(8) WHEN niOi101OO = '1' ELSE wire_nl110li0l_dataout; + wire_nl110l0il_w_lg_dataout61099w(0) <= NOT wire_nl110l0il_dataout; + wire_nl110l0iO_dataout <= wire_nl110lill_o(9) WHEN niOi101OO = '1' ELSE wire_nl110li0O_dataout; + wire_nl110l0iO_w_lg_dataout61101w(0) <= NOT wire_nl110l0iO_dataout; + wire_nl110l0li_dataout <= wire_nl110lill_o(10) WHEN niOi101OO = '1' ELSE wire_nl110liii_dataout; + wire_nl110l0li_w_lg_dataout61103w(0) <= NOT wire_nl110l0li_dataout; + wire_nl110l0ll_dataout <= wire_nl110lill_o(11) WHEN niOi101OO = '1' ELSE wire_nl110liil_dataout; + wire_nl110l0ll_w_lg_dataout61105w(0) <= NOT wire_nl110l0ll_dataout; + wire_nl110l0lO_dataout <= wire_nl110liiO_o(1) WHEN niOi1001i = '1' ELSE nl110Ol0O; + wire_nl110l0O_dataout <= nl110iOO WHEN niOO1ilOl = '1' ELSE swup_in(1); + wire_nl110l0Oi_dataout <= wire_nl110liiO_o(2) WHEN niOi1001i = '1' ELSE nl110Olii; + wire_nl110l0Ol_dataout <= wire_nl110liiO_o(3) WHEN niOi1001i = '1' ELSE nl110Olil; + wire_nl110l0OO_dataout <= wire_nl110liiO_o(4) WHEN niOi1001i = '1' ELSE nl110OliO; + wire_nl110l10i_dataout <= wire_nl110l1Ol_o(7) WHEN niOi101lO = '1' ELSE wire_nl110l1lO_dataout; + wire_nl110l10i_w_lg_dataout61212w(0) <= NOT wire_nl110l10i_dataout; + wire_nl110l10l_dataout <= wire_nl110l1Oi_o(1) WHEN niOi101Oi = '1' ELSE nl110OiOi; + wire_nl110l10O_dataout <= wire_nl110l1Oi_o(2) WHEN niOi101Oi = '1' ELSE nl110OiOl; + wire_nl110l11i_dataout <= wire_nl110l1Ol_o(4) WHEN niOi101lO = '1' ELSE wire_nl110l1iO_dataout; + wire_nl110l11i_w_lg_dataout61206w(0) <= NOT wire_nl110l11i_dataout; + wire_nl110l11l_dataout <= wire_nl110l1Ol_o(5) WHEN niOi101lO = '1' ELSE wire_nl110l1li_dataout; + wire_nl110l11l_w_lg_dataout61208w(0) <= NOT wire_nl110l11l_dataout; + wire_nl110l11O_dataout <= wire_nl110l1Ol_o(6) WHEN niOi101lO = '1' ELSE wire_nl110l1ll_dataout; + wire_nl110l11O_w_lg_dataout61210w(0) <= NOT wire_nl110l11O_dataout; + wire_nl110l1i_dataout <= wire_nl110l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl110l1ii_dataout <= wire_nl110l1Oi_o(3) WHEN niOi101Oi = '1' ELSE nl110OiOO; + wire_nl110l1il_dataout <= wire_nl110l1Oi_o(4) WHEN niOi101Oi = '1' ELSE nl110Ol1i; + wire_nl110l1iO_dataout <= wire_nl110l1Oi_o(5) WHEN niOi101Oi = '1' ELSE nl110Ol1l; + wire_nl110l1l_dataout <= wire_nl110l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl110l1li_dataout <= wire_nl110l1Oi_o(6) WHEN niOi101Oi = '1' ELSE nl110Ol1O; + wire_nl110l1ll_dataout <= wire_nl110l1Oi_o(7) WHEN niOi101Oi = '1' ELSE nl110Ol0i; + wire_nl110l1lO_dataout <= wire_nl110l1Oi_o(8) WHEN niOi101Oi = '1' ELSE nl110Ol0l; + wire_nl110l1O_dataout <= wire_niOOO0O_w_lg_nl110ilO8351w(0) WHEN (wire_w_lg_niOO1ilOl8352w(0) AND wire_w_lg_w_swup_in_range8350w8353w(0)) = '1' ELSE nl110ilO; + wire_nl110l1OO_dataout <= wire_nl110lill_o(0) WHEN niOi101OO = '1' ELSE wire_nl110l0lO_dataout; + wire_nl110l1OO_w_lg_dataout61083w(0) <= NOT wire_nl110l1OO_dataout; + wire_nl110li_dataout <= lmi_din(30) AND NOT(wire_niO01l0O_dataout); + wire_nl110li0i_dataout <= wire_nl110liiO_o(8) WHEN niOi1001i = '1' ELSE nl110OlOi; + wire_nl110li0l_dataout <= wire_nl110liiO_o(9) WHEN niOi1001i = '1' ELSE nl110OlOl; + wire_nl110li0O_dataout <= wire_nl110liiO_o(10) WHEN niOi1001i = '1' ELSE nl110OlOO; + wire_nl110li1i_dataout <= wire_nl110liiO_o(5) WHEN niOi1001i = '1' ELSE nl110Olli; + wire_nl110li1l_dataout <= wire_nl110liiO_o(6) WHEN niOi1001i = '1' ELSE nl110Olll; + wire_nl110li1O_dataout <= wire_nl110liiO_o(7) WHEN niOi1001i = '1' ELSE nl110OllO; + wire_nl110liii_dataout <= wire_nl110liiO_o(11) WHEN niOi1001i = '1' ELSE nl110OO1i; + wire_nl110liil_dataout <= wire_nl110liiO_o(12) WHEN niOi1001i = '1' ELSE nl110OO1l; + wire_nl110liO_dataout <= wire_nl110lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl110liOi_dataout <= wire_nl110llOO_o(0) WHEN niOi101OO = '1' ELSE wire_nl110ll0O_dataout; + wire_nl110liOi_w_lg_dataout60992w(0) <= NOT wire_nl110liOi_dataout; + wire_nl110liOl_dataout <= wire_nl110llOO_o(1) WHEN niOi101OO = '1' ELSE wire_nl110llii_dataout; + wire_nl110liOl_w_lg_dataout60994w(0) <= NOT wire_nl110liOl_dataout; + wire_nl110liOO_dataout <= wire_nl110llOO_o(2) WHEN niOi101OO = '1' ELSE wire_nl110llil_dataout; + wire_nl110liOO_w_lg_dataout60996w(0) <= NOT wire_nl110liOO_dataout; + wire_nl110ll_dataout <= lmi_din(31) AND NOT(wire_niO01l0O_dataout); + wire_nl110ll0i_dataout <= wire_nl110llOO_o(6) WHEN niOi101OO = '1' ELSE wire_nl110lllO_dataout; + wire_nl110ll0i_w_lg_dataout61004w(0) <= NOT wire_nl110ll0i_dataout; + wire_nl110ll0l_dataout <= wire_nl110llOO_o(7) WHEN niOi101OO = '1' ELSE wire_nl110llOi_dataout; + wire_nl110ll0l_w_lg_dataout61006w(0) <= NOT wire_nl110ll0l_dataout; + wire_nl110ll0O_dataout <= wire_nl110llOl_o(1) WHEN niOi1001i = '1' ELSE nl110OO1O; + wire_nl110ll1i_dataout <= wire_nl110llOO_o(3) WHEN niOi101OO = '1' ELSE wire_nl110lliO_dataout; + wire_nl110ll1i_w_lg_dataout60998w(0) <= NOT wire_nl110ll1i_dataout; + wire_nl110ll1l_dataout <= wire_nl110llOO_o(4) WHEN niOi101OO = '1' ELSE wire_nl110llli_dataout; + wire_nl110ll1l_w_lg_dataout61000w(0) <= NOT wire_nl110ll1l_dataout; + wire_nl110ll1O_dataout <= wire_nl110llOO_o(5) WHEN niOi101OO = '1' ELSE wire_nl110llll_dataout; + wire_nl110ll1O_w_lg_dataout61002w(0) <= NOT wire_nl110ll1O_dataout; + wire_nl110lli_dataout <= wire_nl1000i_w_lg_nl110llO8347w(0) WHEN (nl110O0i XOR nl110O1l) = '1' ELSE nl110llO; + wire_nl110llii_dataout <= wire_nl110llOl_o(2) WHEN niOi1001i = '1' ELSE nl110OO0i; + wire_nl110llil_dataout <= wire_nl110llOl_o(3) WHEN niOi1001i = '1' ELSE nl110OO0l; + wire_nl110lliO_dataout <= wire_nl110llOl_o(4) WHEN niOi1001i = '1' ELSE nl110OO0O; + wire_nl110llli_dataout <= wire_nl110llOl_o(5) WHEN niOi1001i = '1' ELSE nl110OOii; + wire_nl110llll_dataout <= wire_nl110llOl_o(6) WHEN niOi1001i = '1' ELSE nl110OOil; + wire_nl110lllO_dataout <= wire_nl110llOl_o(7) WHEN niOi1001i = '1' ELSE nl110OOiO; + wire_nl110llOi_dataout <= wire_nl110llOl_o(8) WHEN niOi1001i = '1' ELSE nl110OOli; + wire_nl110lO_dataout <= lmi_addr(0) AND NOT(wire_niO01l0O_dataout); + wire_nl110lO0i_dataout <= wire_nl110O1lO_o(3) WHEN niOi1001O = '1' ELSE wire_nl110O11i_dataout; + wire_nl110lO0i_w_lg_dataout61307w(0) <= NOT wire_nl110lO0i_dataout; + wire_nl110lO0l_dataout <= wire_nl110O1lO_o(4) WHEN niOi1001O = '1' ELSE wire_nl110O11l_dataout; + wire_nl110lO0l_w_lg_dataout61309w(0) <= NOT wire_nl110lO0l_dataout; + wire_nl110lO0O_dataout <= wire_nl110O1lO_o(5) WHEN niOi1001O = '1' ELSE wire_nl110O11O_dataout; + wire_nl110lO0O_w_lg_dataout61311w(0) <= NOT wire_nl110lO0O_dataout; + wire_nl110lO1i_dataout <= wire_nl110O1lO_o(0) WHEN niOi1001O = '1' ELSE wire_nl110lOOi_dataout; + wire_nl110lO1i_w_lg_dataout61301w(0) <= NOT wire_nl110lO1i_dataout; + wire_nl110lO1l_dataout <= wire_nl110O1lO_o(1) WHEN niOi1001O = '1' ELSE wire_nl110lOOl_dataout; + wire_nl110lO1l_w_lg_dataout61303w(0) <= NOT wire_nl110lO1l_dataout; + wire_nl110lO1O_dataout <= wire_nl110O1lO_o(2) WHEN niOi1001O = '1' ELSE wire_nl110lOOO_dataout; + wire_nl110lO1O_w_lg_dataout61305w(0) <= NOT wire_nl110lO1O_dataout; + wire_nl110lOii_dataout <= wire_nl110O1lO_o(6) WHEN niOi1001O = '1' ELSE wire_nl110O10i_dataout; + wire_nl110lOii_w_lg_dataout61313w(0) <= NOT wire_nl110lOii_dataout; + wire_nl110lOil_dataout <= wire_nl110O1lO_o(7) WHEN niOi1001O = '1' ELSE wire_nl110O10l_dataout; + wire_nl110lOil_w_lg_dataout61315w(0) <= NOT wire_nl110lOil_dataout; + wire_nl110lOiO_dataout <= wire_nl110O1lO_o(8) WHEN niOi1001O = '1' ELSE wire_nl110O10O_dataout; + wire_nl110lOiO_w_lg_dataout61317w(0) <= NOT wire_nl110lOiO_dataout; + wire_nl110lOl_dataout <= nl110O1l AND NOT(wire_niO01l0O_dataout); + wire_nl110lOli_dataout <= wire_nl110O1lO_o(9) WHEN niOi1001O = '1' ELSE wire_nl110O1ii_dataout; + wire_nl110lOli_w_lg_dataout61319w(0) <= NOT wire_nl110lOli_dataout; + wire_nl110lOll_dataout <= wire_nl110O1lO_o(10) WHEN niOi1001O = '1' ELSE wire_nl110O1il_dataout; + wire_nl110lOll_w_lg_dataout61321w(0) <= NOT wire_nl110lOll_dataout; + wire_nl110lOlO_dataout <= wire_nl110O1lO_o(11) WHEN niOi1001O = '1' ELSE wire_nl110O1iO_dataout; + wire_nl110lOlO_w_lg_dataout61323w(0) <= NOT wire_nl110lOlO_dataout; + wire_nl110lOOi_dataout <= wire_nl110O1li_o(1) WHEN niOi1000i = '1' ELSE nl11i110i; + wire_nl110lOOl_dataout <= wire_nl110O1li_o(2) WHEN niOi1000i = '1' ELSE nl11i110l; + wire_nl110lOOO_dataout <= wire_nl110O1li_o(3) WHEN niOi1000i = '1' ELSE nl11i110O; + wire_nl110O00i_dataout <= wire_nl110Oi1i_o(5) WHEN niOi1001O = '1' ELSE wire_nl110O0lO_dataout; + wire_nl110O00i_w_lg_dataout60903w(0) <= NOT wire_nl110O00i_dataout; + wire_nl110O00l_dataout <= wire_nl110Oi1i_o(6) WHEN niOi1001O = '1' ELSE wire_nl110O0Oi_dataout; + wire_nl110O00l_w_lg_dataout60905w(0) <= NOT wire_nl110O00l_dataout; + wire_nl110O00O_dataout <= wire_nl110Oi1i_o(7) WHEN niOi1001O = '1' ELSE wire_nl110O0Ol_dataout; + wire_nl110O00O_w_lg_dataout60907w(0) <= NOT wire_nl110O00O_dataout; + wire_nl110O01i_dataout <= wire_nl110Oi1i_o(2) WHEN niOi1001O = '1' ELSE wire_nl110O0iO_dataout; + wire_nl110O01i_w_lg_dataout60897w(0) <= NOT wire_nl110O01i_dataout; + wire_nl110O01l_dataout <= wire_nl110Oi1i_o(3) WHEN niOi1001O = '1' ELSE wire_nl110O0li_dataout; + wire_nl110O01l_w_lg_dataout60899w(0) <= NOT wire_nl110O01l_dataout; + wire_nl110O01O_dataout <= wire_nl110Oi1i_o(4) WHEN niOi1001O = '1' ELSE wire_nl110O0ll_dataout; + wire_nl110O01O_w_lg_dataout60901w(0) <= NOT wire_nl110O01O_dataout; + wire_nl110O0ii_dataout <= wire_nl110O0OO_o(1) WHEN niOi1000i = '1' ELSE nl110OOll; + wire_nl110O0il_dataout <= wire_nl110O0OO_o(2) WHEN niOi1000i = '1' ELSE nl110OOlO; + wire_nl110O0iO_dataout <= wire_nl110O0OO_o(3) WHEN niOi1000i = '1' ELSE nl110OOOi; + wire_nl110O0li_dataout <= wire_nl110O0OO_o(4) WHEN niOi1000i = '1' ELSE nl110OOOl; + wire_nl110O0ll_dataout <= wire_nl110O0OO_o(5) WHEN niOi1000i = '1' ELSE nl110OOOO; + wire_nl110O0lO_dataout <= wire_nl110O0OO_o(6) WHEN niOi1000i = '1' ELSE nl11i111i; + wire_nl110O0O_dataout <= nl110O0i AND NOT(wire_niO01O0O_dataout); + wire_nl110O0Oi_dataout <= wire_nl110O0OO_o(7) WHEN niOi1000i = '1' ELSE nl11i111l; + wire_nl110O0Ol_dataout <= wire_nl110O0OO_o(8) WHEN niOi1000i = '1' ELSE nl11i111O; + wire_nl110O10i_dataout <= wire_nl110O1li_o(7) WHEN niOi1000i = '1' ELSE nl11i11li; + wire_nl110O10l_dataout <= wire_nl110O1li_o(8) WHEN niOi1000i = '1' ELSE nl11i11ll; + wire_nl110O10O_dataout <= wire_nl110O1li_o(9) WHEN niOi1000i = '1' ELSE nl11i11lO; + wire_nl110O11i_dataout <= wire_nl110O1li_o(4) WHEN niOi1000i = '1' ELSE nl11i11ii; + wire_nl110O11l_dataout <= wire_nl110O1li_o(5) WHEN niOi1000i = '1' ELSE nl11i11il; + wire_nl110O11O_dataout <= wire_nl110O1li_o(6) WHEN niOi1000i = '1' ELSE nl11i11iO; + wire_nl110O1i_dataout <= nl110lil AND NOT(wire_niO01l0O_dataout); + wire_nl110O1ii_dataout <= wire_nl110O1li_o(10) WHEN niOi1000i = '1' ELSE nl11i11Oi; + wire_nl110O1il_dataout <= wire_nl110O1li_o(11) WHEN niOi1000i = '1' ELSE nl11i11Ol; + wire_nl110O1iO_dataout <= wire_nl110O1li_o(12) WHEN niOi1000i = '1' ELSE nl11i11OO; + wire_nl110O1O_dataout <= nl110O0l AND NOT(wire_niO01O0O_dataout); + wire_nl110O1Ol_dataout <= wire_nl110Oi1i_o(0) WHEN niOi1001O = '1' ELSE wire_nl110O0ii_dataout; + wire_nl110O1Ol_w_lg_dataout60893w(0) <= NOT wire_nl110O1Ol_dataout; + wire_nl110O1OO_dataout <= wire_nl110Oi1i_o(1) WHEN niOi1001O = '1' ELSE wire_nl110O0il_dataout; + wire_nl110O1OO_w_lg_dataout60895w(0) <= NOT wire_nl110O1OO_dataout; + wire_nl110Oi_dataout <= lmi_addr(1) AND NOT(wire_niO01l0O_dataout); + wire_nl110Oii_dataout <= nl110lOO AND NOT(wire_niO01O0O_dataout); + wire_nl110OiO_dataout <= wire_nl110Oll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl110Ol_dataout <= lmi_addr(2) AND NOT(wire_niO01l0O_dataout); + wire_nl110Oli_dataout <= wire_nl110OOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl110Oll_dataout <= wire_niOOO0O_w_lg_nl110O0l8343w(0) WHEN (wire_w_lg_niOO1ilOO8344w(0) AND wire_w_lg_w_swup_in_range8342w8345w(0)) = '1' ELSE nl110O0l; + wire_nl110OO_dataout <= lmi_addr(3) AND NOT(wire_niO01l0O_dataout); + wire_nl110OOl_dataout <= nl110Oil WHEN niOO1ilOO = '1' ELSE swup_in(2); + wire_nl11100i_dataout <= nl1110ii AND NOT(wire_niO01l0O_dataout); + wire_nl11100O_dataout <= nl1111Oi AND NOT(wire_niO01l0O_dataout); + wire_nl111011l_dataout <= (niOi11Oll AND (nl111OO0i OR (wire_w_lg_niOi11O0l61544w(0) OR wire_nlill0Oll_w_lg_nl0i00iii61540w(0)))) WHEN (wire_w_lg_niOi10i1i61548w(0) AND wire_nl11OlOOl_w_lg_dataout61549w(0)) = '1' ELSE (niOi11OiO AND (nl111ll1l OR (wire_w_lg_niOi11O0O61539w(0) OR wire_nlill0Oll_w_lg_nl0i00iii61540w(0)))); + wire_nl11101li_dataout <= (niOi11Oll AND (nl111OO0i OR wire_nl111000l_o)) WHEN (wire_w_lg_niOi10OlO61533w(0) AND wire_nl10iil1O_w_lg_dataout61537w(0)) = '1' ELSE wire_nl11101ll_dataout; + wire_nl11101ll_dataout <= (wire_nlill0Oll_w_lg_nl111OO1O61527w(0) AND (wire_nl10iilli_w_lg_dataout61528w(0) OR wire_nlill0Oll_w_lg_nl111OO1l61530w(0))) WHEN (wire_w_lg_niOi10OlO61533w(0) AND wire_nl10iil1O_dataout) = '1' ELSE (niOi11OiO AND (nl111ll1l OR wire_nl111001i_o)); + wire_nl1110i_dataout <= lmi_din(9) AND NOT(wire_niO01l0O_dataout); + wire_nl1110il_dataout <= nl1110li AND NOT(wire_niO01O0O_dataout); + wire_nl1110l_dataout <= lmi_din(10) AND NOT(wire_niO01l0O_dataout); + wire_nl1110ll_dataout <= nl1110iO AND NOT(wire_niO01O0O_dataout); + wire_nl1110lO_dataout <= nl11100l AND NOT(wire_niO01O0O_dataout); + wire_nl1110O_dataout <= lmi_din(11) AND NOT(wire_niO01l0O_dataout); + wire_nl1110Ol_dataout <= wire_nl111i1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1110OO_dataout <= wire_nl111i0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl111100i_dataout <= nlO1Oil0i AND niOi11O0i; + wire_nl111100l_dataout <= nlO1Oil0l AND niOi11O0i; + wire_nl111100O_dataout <= nlO1Oil0O AND niOi11O0i; + wire_nl111101i_dataout <= nlO1Oil1i AND niOi11O0i; + wire_nl111101l_dataout <= nlO1Oil1l AND niOi11O0i; + wire_nl111101O_dataout <= nlO1Oil1O AND niOi11O0i; + wire_nl11110i_dataout <= niOOOOlO AND NOT(wire_niO01O0O_dataout); + wire_nl11110ii_dataout <= nlO1Oilii AND niOi11O0i; + wire_nl11110il_dataout <= nlO1Oilil AND niOi11O0i; + wire_nl11110iO_dataout <= nlO1OiliO AND niOi11O0i; + wire_nl11110li_dataout <= nlO1Oilli AND niOi11O0i; + wire_nl11110ll_dataout <= nlO1Oilll AND niOi11O0i; + wire_nl11110lO_dataout <= nlO1OillO AND niOi11O0i; + wire_nl11110O_dataout <= wire_nl1111il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11110Oi_dataout <= nlO1OilOi AND niOi11O0i; + wire_nl11110Ol_dataout <= nlO1OilOl AND niOi11O0i; + wire_nl11110OO_dataout <= nlO1OilOO AND niOi11O0i; + wire_nl111110i_dataout <= nlO1Oii0i WHEN niOi11O0i = '1' ELSE wire_nlOiO010l_dataout; + wire_nl111110l_dataout <= nlO1Oii0l WHEN niOi11O0i = '1' ELSE wire_nlOiO010O_dataout; + wire_nl111110O_dataout <= nlO1Oii0O WHEN niOi11O0i = '1' ELSE wire_nlOiO01ii_dataout; + wire_nl111111i_dataout <= nlO1Oii1i WHEN niOi11O0i = '1' ELSE nlO1Oi00l; + wire_nl111111l_dataout <= nlO1Oii1l WHEN niOi11O0i = '1' ELSE wire_nlOiOi11i_dataout; + wire_nl111111O_dataout <= nlO1Oii1O WHEN niOi11O0i = '1' ELSE wire_nlOiO010i_dataout; + wire_nl11111ii_dataout <= nlO1Oiiii WHEN niOi11O0i = '1' ELSE wire_nlOiO01il_dataout; + wire_nl11111il_dataout <= nlO1Oiiil WHEN niOi11O0i = '1' ELSE wire_nlOiO01iO_dataout; + wire_nl11111iO_dataout <= nlO1OiiiO WHEN niOi11O0i = '1' ELSE wire_nlOiO01li_dataout; + wire_nl11111li_dataout <= nlO1Oiili WHEN niOi11O0i = '1' ELSE wire_nlOiO01ll_dataout; + wire_nl11111ll_dataout <= nlO1Oiill WHEN niOi11O0i = '1' ELSE niOO1li0O; + wire_nl11111lO_dataout <= nlO1OiilO AND niOi11O0i; + wire_nl11111O_dataout <= nl11111i AND NOT(wire_niO01O0O_dataout); + wire_nl11111Oi_dataout <= nlO1OiiOi AND niOi11O0i; + wire_nl11111Ol_dataout <= nlO1OiiOl AND niOi11O0i; + wire_nl11111OO_dataout <= nlO1OiiOO AND niOi11O0i; + wire_nl1111i_dataout <= lmi_din(6) AND NOT(wire_niO01l0O_dataout); + wire_nl1111i0i_dataout <= nlO1OiO0i AND niOi11O0i; + wire_nl1111i0l_dataout <= nlO1OiO0l AND niOi11O0i; + wire_nl1111i0O_dataout <= nlO1OiO0O AND niOi11O0i; + wire_nl1111i1i_dataout <= nlO1OiO1i AND niOi11O0i; + wire_nl1111i1l_dataout <= nlO1OiO1l AND niOi11O0i; + wire_nl1111i1O_dataout <= nlO1OiO1O AND niOi11O0i; + wire_nl1111ii_dataout <= wire_nl1111ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1111iii_dataout <= nlO1OiOii AND niOi11O0i; + wire_nl1111iil_dataout <= nlO1OiOil AND niOi11O0i; + wire_nl1111iiO_dataout <= nlO1OiOiO AND niOi11O0i; + wire_nl1111il_dataout <= wire_niOOO0O_w_lg_nl11111l8390w(0) WHEN (wire_w_lg_niOO1iliO8391w(0) AND wire_w_lg_w_swdn_in_range8389w8392w(0)) = '1' ELSE nl11111l; + wire_nl1111ili_dataout <= nlO1OiOli AND niOi11O0i; + wire_nl1111ill_dataout <= nlO1OiOll AND niOi11O0i; + wire_nl1111ilO_dataout <= nlO1OiOlO AND niOi11O0i; + wire_nl1111iOi_dataout <= nlO1OiOOi AND niOi11O0i; + wire_nl1111iOl_dataout <= nlO1OiOOl AND niOi11O0i; + wire_nl1111iOO_dataout <= nlO1OiOOO AND niOi11O0i; + wire_nl1111l_dataout <= lmi_din(7) AND NOT(wire_niO01l0O_dataout); + wire_nl1111l0i_dataout <= nlO1Ol10i AND niOi11O0i; + wire_nl1111l0l_dataout <= nlO1Ol10l AND niOi11O0i; + wire_nl1111l0O_dataout <= nlO1Ol10O AND niOi11O0i; + wire_nl1111l1i_dataout <= nlO1Ol11i AND niOi11O0i; + wire_nl1111l1l_dataout <= nlO1Ol11l AND niOi11O0i; + wire_nl1111l1O_dataout <= nlO1Ol11O AND niOi11O0i; + wire_nl1111lii_dataout <= nlO1Ol1ii AND niOi11O0i; + wire_nl1111lil_dataout <= nlO1Ol1il AND niOi11O0i; + wire_nl1111liO_dataout <= nlO1Ol1iO AND niOi11O0i; + wire_nl1111ll_dataout <= nl11110l WHEN niOO1iliO = '1' ELSE swdn_in(0); + wire_nl1111O_dataout <= lmi_din(8) AND NOT(wire_niO01l0O_dataout); + wire_nl1111Ol_dataout <= wire_nl1111OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1111OO_dataout <= wire_nl1000i_w_lg_nl11101l8386w(0) WHEN (nl1110iO XOR nl1110ii) = '1' ELSE nl11101l; + wire_nl111i00i_dataout <= wire_nl111l1li_o(11) AND NOT(wire_niO01O0O_dataout); + wire_nl111i00l_dataout <= wire_nl111l1li_o(12) AND NOT(wire_niO01O0O_dataout); + wire_nl111i00O_dataout <= wire_nl111O0lO_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nl111i01i_dataout <= wire_nl111l1li_o(8) AND NOT(wire_niO01O0O_dataout); + wire_nl111i01l_dataout <= wire_nl111l1li_o(9) AND NOT(wire_niO01O0O_dataout); + wire_nl111i01O_dataout <= wire_nl111l1li_o(10) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0i_dataout <= nl1110Oi WHEN niOO1illi = '1' ELSE swdn_in(1); + wire_nl111i0ii_dataout <= wire_nl111O0lO_o(2) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0il_dataout <= wire_nl111O0lO_o(3) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0iO_dataout <= wire_nl111O0lO_o(4) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0li_dataout <= wire_nl111O0lO_o(5) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0ll_dataout <= wire_nl111O0lO_o(6) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0lO_dataout <= wire_nl111O0lO_o(7) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0Oi_dataout <= wire_nl111O0lO_o(8) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0Ol_dataout <= wire_nl111Oi0i_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nl111i0OO_dataout <= wire_nl111Oi0i_o(2) AND NOT(wire_niO01O0O_dataout); + wire_nl111i1i_dataout <= wire_niOOO0O_w_lg_nl1110li8382w(0) WHEN (wire_w_lg_niOO1illi8383w(0) AND wire_w_lg_w_swdn_in_range8381w8384w(0)) = '1' ELSE nl1110li; + wire_nl111i1iO_dataout <= wire_nl111l1li_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nl111i1li_dataout <= wire_nl111l1li_o(2) AND NOT(wire_niO01O0O_dataout); + wire_nl111i1ll_dataout <= wire_nl111l1li_o(3) AND NOT(wire_niO01O0O_dataout); + wire_nl111i1lO_dataout <= wire_nl111l1li_o(4) AND NOT(wire_niO01O0O_dataout); + wire_nl111i1Oi_dataout <= wire_nl111l1li_o(5) AND NOT(wire_niO01O0O_dataout); + wire_nl111i1Ol_dataout <= wire_nl111l1li_o(6) AND NOT(wire_niO01O0O_dataout); + wire_nl111i1OO_dataout <= wire_nl111l1li_o(7) AND NOT(wire_niO01O0O_dataout); + wire_nl111ii_dataout <= lmi_din(12) AND NOT(wire_niO01l0O_dataout); + wire_nl111ii0i_dataout <= wire_nl111Oi0i_o(6) AND NOT(wire_niO01O0O_dataout); + wire_nl111ii0l_dataout <= wire_nl111Oi0i_o(7) AND NOT(wire_niO01O0O_dataout); + wire_nl111ii0O_dataout <= wire_nl111Oi0i_o(8) AND NOT(wire_niO01O0O_dataout); + wire_nl111ii1i_dataout <= wire_nl111Oi0i_o(3) AND NOT(wire_niO01O0O_dataout); + wire_nl111ii1l_dataout <= wire_nl111Oi0i_o(4) AND NOT(wire_niO01O0O_dataout); + wire_nl111ii1O_dataout <= wire_nl111Oi0i_o(5) AND NOT(wire_niO01O0O_dataout); + wire_nl111iii_dataout <= wire_nl111iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111iiii_dataout <= wire_nl111Oi0i_o(9) AND NOT(wire_niO01O0O_dataout); + wire_nl111iiil_dataout <= wire_nl111Oi0i_o(10) AND NOT(wire_niO01O0O_dataout); + wire_nl111iiiO_dataout <= wire_nl111Oi0i_o(11) AND NOT(wire_niO01O0O_dataout); + wire_nl111iil_dataout <= wire_nl1000i_w_lg_nl111ili8378w(0) WHEN (nl111l1l XOR nl111iOO) = '1' ELSE nl111ili; + wire_nl111iili_dataout <= wire_nl111Oi0i_o(12) AND NOT(wire_niO01O0O_dataout); + wire_nl111iill_dataout <= wire_nl111Oill_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nl111iilO_dataout <= wire_nl111Oill_o(2) AND NOT(wire_niO01O0O_dataout); + wire_nl111iiOi_dataout <= wire_nl111Oill_o(3) AND NOT(wire_niO01O0O_dataout); + wire_nl111iiOl_dataout <= wire_nl111Oill_o(4) AND NOT(wire_niO01O0O_dataout); + wire_nl111iiOO_dataout <= wire_nl111Oill_o(5) AND NOT(wire_niO01O0O_dataout); + wire_nl111il_dataout <= lmi_din(13) AND NOT(wire_niO01l0O_dataout); + wire_nl111il0i_dataout <= wire_nl111l1ll_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nl111il0l_dataout <= wire_nl111l1ll_o(2) AND NOT(wire_niO01O0O_dataout); + wire_nl111il0O_dataout <= wire_nl111l1ll_o(3) AND NOT(wire_niO01O0O_dataout); + wire_nl111il1i_dataout <= wire_nl111Oill_o(6) AND NOT(wire_niO01O0O_dataout); + wire_nl111il1l_dataout <= wire_nl111Oill_o(7) AND NOT(wire_niO01O0O_dataout); + wire_nl111il1O_dataout <= wire_nl111Oill_o(8) AND NOT(wire_niO01O0O_dataout); + wire_nl111ilii_dataout <= wire_nl111l1ll_o(4) AND NOT(wire_niO01O0O_dataout); + wire_nl111ilil_dataout <= wire_nl111l1ll_o(5) AND NOT(wire_niO01O0O_dataout); + wire_nl111iliO_dataout <= wire_nl111l1ll_o(6) AND NOT(wire_niO01O0O_dataout); + wire_nl111illi_dataout <= wire_nl111l1ll_o(7) AND NOT(wire_niO01O0O_dataout); + wire_nl111illl_dataout <= wire_nl111l1ll_o(8) AND NOT(wire_niO01O0O_dataout); + wire_nl111illO_dataout <= wire_nl111l1ll_o(9) AND NOT(wire_niO01O0O_dataout); + wire_nl111ilO_dataout <= nl111iOO AND NOT(wire_niO01l0O_dataout); + wire_nl111ilOi_dataout <= wire_nl111l1ll_o(10) AND NOT(wire_niO01O0O_dataout); + wire_nl111ilOl_dataout <= wire_nl111l1ll_o(11) AND NOT(wire_niO01O0O_dataout); + wire_nl111ilOO_dataout <= wire_nl111l1ll_o(12) AND NOT(wire_niO01O0O_dataout); + wire_nl111iO_dataout <= lmi_din(14) AND NOT(wire_niO01l0O_dataout); + wire_nl111iO0i_dataout <= wire_nl111OlOO_o(4) AND NOT(wire_niO01O0O_dataout); + wire_nl111iO0l_dataout <= wire_nl111OlOO_o(5) AND NOT(wire_niO01O0O_dataout); + wire_nl111iO0O_dataout <= wire_nl111OlOO_o(6) AND NOT(wire_niO01O0O_dataout); + wire_nl111iO1i_dataout <= wire_nl111OlOO_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nl111iO1l_dataout <= wire_nl111OlOO_o(2) AND NOT(wire_niO01O0O_dataout); + wire_nl111iO1O_dataout <= wire_nl111OlOO_o(3) AND NOT(wire_niO01O0O_dataout); + wire_nl111iOii_dataout <= wire_nl111OlOO_o(7) AND NOT(wire_niO01O0O_dataout); + wire_nl111iOil_dataout <= wire_nl111OlOO_o(8) AND NOT(wire_niO01O0O_dataout); + wire_nl111iOl_dataout <= nl111i0O AND NOT(wire_niO01l0O_dataout); + wire_nl111iOll_dataout <= (nl111ll1l AND (nl111OO1i AND (nl111OO1l AND (nl111OO1O AND (nl111OO0l AND nl111OO0i))))) OR wire_niO01O0O_dataout; + wire_nl111iOlO_dataout <= (NOT ((((wire_nl111l1iO_w_lg_o61436w(0) OR ((wire_nlill0Oll_w_lg_nl111li1i61437w(0) AND wire_nlill0Oll_w_lg_nl111l0OO61438w(0)) AND wire_nlill0Oll_w_lg_nl111l0Ol61440w(0))) OR ((wire_nlill0Oll_w_lg_nl111l0Oi61443w(0) AND wire_nlill0Oll_w_lg_nl111l0lO61444w(0)) AND wire_nlill0Oll_w_lg_nl111l0ll61446w(0))) OR ((wire_nlill0Oll_w_lg_nl111l0li61449w(0) AND wire_nlill0Oll_w_lg_nl111l0iO61450w(0)) AND wire_nlill0Oll_w_lg_nl111l0il61452w(0))) OR wire_nl111l10i_o)) OR wire_niO01O0O_dataout; + wire_nl111l0i_dataout <= nl111l1l AND NOT(wire_niO01O0O_dataout); + wire_nl111l0l_dataout <= nl111iOi AND NOT(wire_niO01O0O_dataout); + wire_nl111l1i_dataout <= nl111l1O AND NOT(wire_niO01O0O_dataout); + wire_nl111li_dataout <= lmi_din(15) AND NOT(wire_niO01l0O_dataout); + wire_nl111lii_dataout <= wire_nl111liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl111lil_dataout <= wire_nl111llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl111liO_dataout <= wire_niOOO0O_w_lg_nl111l1O8374w(0) WHEN (wire_w_lg_niOO1illl8375w(0) AND wire_w_lg_w_swdn_in_range8373w8376w(0)) = '1' ELSE nl111l1O; + wire_nl111ll_dataout <= lmi_din(16) AND NOT(wire_niO01l0O_dataout); + wire_nl111ll0i_dataout <= wire_nl111O1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111ll0l_dataout <= wire_nl111O1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111ll0O_dataout <= wire_nl111O1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111ll1O_dataout <= wire_nl111O1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111llii_dataout <= wire_nl111O1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111llil_dataout <= wire_nl111O1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lliO_dataout <= wire_nl111O1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111llli_dataout <= wire_nl111O01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111llll_dataout <= wire_nl111O01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lllO_dataout <= wire_nl111O01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111llO_dataout <= nl111l0O WHEN niOO1illl = '1' ELSE swdn_in(2); + wire_nl111llOi_dataout <= wire_nl111O00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111llOl_dataout <= wire_nl111O00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111llOO_dataout <= wire_nl111O00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lO_dataout <= lmi_din(17) AND NOT(wire_niO01l0O_dataout); + wire_nl111lO0i_dataout <= wire_nl111O0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lO0l_dataout <= wire_nl111O0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lO0O_dataout <= wire_nl111Oi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lO1i_dataout <= wire_nl111O0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lO1l_dataout <= wire_nl111O0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lO1O_dataout <= wire_nl111O0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOii_dataout <= wire_nl111Oi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOil_dataout <= wire_nl111Oiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOiO_dataout <= wire_nl111OilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOli_dataout <= wire_nl111OiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOll_dataout <= wire_nl111OiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOlO_dataout <= wire_nl111OiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOO_dataout <= wire_nl111O1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl111lOOi_dataout <= wire_nl111Ol1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOOl_dataout <= wire_nl111Ol1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111lOOO_dataout <= wire_nl111Ol1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O00i_dataout <= wire_nl111l1li_o(11) OR nl111ll1l; + wire_nl111O00l_dataout <= wire_nl111l1li_o(12) OR nl111ll1l; + wire_nl111O00O_dataout <= wire_nl111O0iO_o(1) OR niOi11OOi; + wire_nl111O01i_dataout <= wire_nl111l1li_o(8) OR nl111ll1l; + wire_nl111O01l_dataout <= wire_nl111l1li_o(9) OR nl111ll1l; + wire_nl111O01O_dataout <= wire_nl111l1li_o(10) OR nl111ll1l; + wire_nl111O0ii_dataout <= wire_nl111O0iO_o(2) OR niOi11OOi; + wire_nl111O0il_dataout <= wire_nl111O0iO_o(3) OR niOi11OOi; + wire_nl111O0l_dataout <= nl111Oil AND NOT(wire_niO01O0O_dataout); + wire_nl111O0Oi_dataout <= wire_nl111Oi1i_o(1) OR niOi11OOl; + wire_nl111O0Ol_dataout <= wire_nl111Oi1i_o(2) OR niOi11OOl; + wire_nl111O0OO_dataout <= wire_nl111Oi1i_o(3) OR niOi11OOl; + wire_nl111O10i_dataout <= wire_nl111Olii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O10l_dataout <= wire_nl111Olil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O10O_dataout <= wire_nl111OliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O11i_dataout <= wire_nl111Ol0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O11l_dataout <= wire_nl111Ol0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O11O_dataout <= wire_nl111Ol0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O1i_dataout <= wire_niOOO0O_w_lg_nl111O1O8370w(0) WHEN (nl111Oli XOR nl111Oil) = '1' ELSE nl111O1O; + wire_nl111O1ii_dataout <= wire_nl111Olli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O1il_dataout <= wire_nl111Olll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl111O1iO_dataout <= wire_nl111l1li_o(1) OR nl111ll1l; + wire_nl111O1li_dataout <= wire_nl111l1li_o(2) OR nl111ll1l; + wire_nl111O1ll_dataout <= wire_nl111l1li_o(3) OR nl111ll1l; + wire_nl111O1lO_dataout <= wire_nl111l1li_o(4) OR nl111ll1l; + wire_nl111O1Oi_dataout <= wire_nl111l1li_o(5) OR nl111ll1l; + wire_nl111O1Ol_dataout <= wire_nl111l1li_o(6) OR nl111ll1l; + wire_nl111O1OO_dataout <= wire_nl111l1li_o(7) OR nl111ll1l; + wire_nl111Oi_dataout <= lmi_din(18) AND NOT(wire_niO01l0O_dataout); + wire_nl111Oi0l_dataout <= wire_nl111Oiil_o(1) OR niOi11OOO; + wire_nl111Oi0O_dataout <= wire_nl111Oiil_o(2) OR niOi11OOO; + wire_nl111Oii_dataout <= nl111lOl AND NOT(wire_niO01O0O_dataout); + wire_nl111Oiii_dataout <= wire_nl111Oiil_o(3) OR niOi11OOO; + wire_nl111OilO_dataout <= wire_nl111l1ll_o(1) OR nl111OO0i; + wire_nl111OiO_dataout <= nl111Oll AND NOT(wire_niO01l0O_dataout); + wire_nl111OiOi_dataout <= wire_nl111l1ll_o(2) OR nl111OO0i; + wire_nl111OiOl_dataout <= wire_nl111l1ll_o(3) OR nl111OO0i; + wire_nl111OiOO_dataout <= wire_nl111l1ll_o(4) OR nl111OO0i; + wire_nl111Ol_dataout <= lmi_din(19) AND NOT(wire_niO01l0O_dataout); + wire_nl111Ol0i_dataout <= wire_nl111l1ll_o(8) OR nl111OO0i; + wire_nl111Ol0l_dataout <= wire_nl111l1ll_o(9) OR nl111OO0i; + wire_nl111Ol0O_dataout <= wire_nl111l1ll_o(10) OR nl111OO0i; + wire_nl111Ol1i_dataout <= wire_nl111l1ll_o(5) OR nl111OO0i; + wire_nl111Ol1l_dataout <= wire_nl111l1ll_o(6) OR nl111OO0i; + wire_nl111Ol1O_dataout <= wire_nl111l1ll_o(7) OR nl111OO0i; + wire_nl111Olii_dataout <= wire_nl111l1ll_o(11) OR nl111OO0i; + wire_nl111Olil_dataout <= wire_nl111l1ll_o(12) OR nl111OO0i; + wire_nl111OliO_dataout <= wire_nl111OllO_o(1) OR niOi1011i; + wire_nl111Olli_dataout <= wire_nl111OllO_o(2) OR niOi1011i; + wire_nl111Olll_dataout <= wire_nl111OllO_o(3) OR niOi1011i; + wire_nl111OlO_dataout <= nl111Oli AND NOT(wire_niO01l0O_dataout); + wire_nl111OO_dataout <= lmi_din(20) AND NOT(wire_niO01l0O_dataout); + wire_nl111OOi_dataout <= nl111O0O AND NOT(wire_niO01l0O_dataout); + wire_nl111OOO_dataout <= wire_nl11011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i000i_dataout <= wire_nl110l11O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i000l_dataout <= wire_nl110l10i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i000O_dataout <= wire_nl110l1OO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i001i_dataout <= wire_nl110iOOO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i001l_dataout <= wire_nl110l11i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i001O_dataout <= wire_nl110l11l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00i_dataout <= wire_niOOO0O_w_lg_nl11i1Oi8335w(0) WHEN (wire_w_lg_niOO1iO1i8336w(0) AND wire_w_lg_w_swup_in_range8334w8337w(0)) = '1' ELSE nl11i1Oi; + wire_nl11i00ii_dataout <= wire_nl110l01i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00il_dataout <= wire_nl110l01l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00iO_dataout <= wire_nl110l01O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00li_dataout <= wire_nl110l00i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00ll_dataout <= wire_nl110l00l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00lO_dataout <= wire_nl110l00O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00Oi_dataout <= wire_nl110l0ii_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00Ol_dataout <= wire_nl110l0il_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i00OO_dataout <= wire_nl110l0iO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i010i_dataout <= wire_nl110il1l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i010l_dataout <= wire_nl110il1O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i010O_dataout <= wire_nl110il0i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i011i_dataout <= wire_nl110iiOl_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i011l_dataout <= wire_nl110iiOO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i011O_dataout <= wire_nl110il1i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01ii_dataout <= wire_nl110il0l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01il_dataout <= wire_nl110il0O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01iO_dataout <= wire_nl110ilii_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01l_dataout <= wire_nl11i00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11i01li_dataout <= wire_nl110ilil_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01ll_dataout <= wire_nl110iliO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01lO_dataout <= wire_nl110illi_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01O_dataout <= wire_nl11i0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11i01Oi_dataout <= wire_nl110iOlO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01Ol_dataout <= wire_nl110iOOi_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i01OO_dataout <= wire_nl110iOOl_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0i_dataout <= lmi_addr(7) AND NOT(wire_niO01l0O_dataout); + wire_nl11i0i0i_dataout <= wire_nl110liOl_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0i0l_dataout <= wire_nl110liOO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0i0O_dataout <= wire_nl110ll1i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0i1i_dataout <= wire_nl110l0li_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0i1l_dataout <= wire_nl110l0ll_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0i1O_dataout <= wire_nl110liOi_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0ii_dataout <= nl11i01i WHEN niOO1iO1i = '1' ELSE swup_in(3); + wire_nl11i0iii_dataout <= wire_nl110ll1l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0iil_dataout <= wire_nl110ll1O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0iiO_dataout <= wire_nl110ll0i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0ili_dataout <= wire_nl110ll0l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0ill_dataout <= wire_nl110lO1i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0ilO_dataout <= wire_nl110lO1l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0iOi_dataout <= wire_nl110lO1O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0iOl_dataout <= wire_nl110lO0i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0iOO_dataout <= wire_nl110lO0l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0l_dataout <= lmi_addr(8) AND NOT(wire_niO01l0O_dataout); + wire_nl11i0l0i_dataout <= wire_nl110lOiO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0l0l_dataout <= wire_nl110lOli_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0l0O_dataout <= wire_nl110lOll_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0l1i_dataout <= wire_nl110lO0O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0l1l_dataout <= wire_nl110lOii_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0l1O_dataout <= wire_nl110lOil_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0li_dataout <= wire_nl11i0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i0lii_dataout <= wire_nl110lOlO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0lil_dataout <= wire_nl110O1Ol_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0liO_dataout <= wire_nl110O1OO_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0ll_dataout <= wire_nl1000i_w_lg_nl11i0Oi8331w(0) WHEN (nl11ii0l XOR nl11ii1O) = '1' ELSE nl11i0Oi; + wire_nl11i0lli_dataout <= wire_nl110O01i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0lll_dataout <= wire_nl110O01l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0llO_dataout <= wire_nl110O01O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0lOi_dataout <= wire_nl110O00i_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0lOl_dataout <= wire_nl110O00l_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0lOO_dataout <= wire_nl110O00O_dataout AND NOT(wire_nilOOO0i_w_lg_dataout47830w(0)); + wire_nl11i0O_dataout <= lmi_addr(9) AND NOT(wire_niO01l0O_dataout); + wire_nl11i0O0i_dataout <= nl111i11O OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0O0l_dataout <= nl111i10i OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0O0O_dataout <= nl111i10l OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0O1i_dataout <= nl1110OOO OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0O1l_dataout <= nl111i11i OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0O1O_dataout <= nl111i11l OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0Oii_dataout <= nl111i10O OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0Oil_dataout <= nl111i1ii OR NOT(wire_nlill0Oll_w_lg_nl111OO0l60385w(0)); + wire_nl11i0OiO_dataout <= nl1110O1O OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11i0Oli_dataout <= nl1110O0i OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11i0Oll_dataout <= nl1110O0l OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11i0OlO_dataout <= nl1110O0O OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11i0OO_dataout <= nl11ii1O AND NOT(wire_niO01l0O_dataout); + wire_nl11i0OOi_dataout <= nl1110Oii OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11i0OOl_dataout <= nl1110Oil OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11i0OOO_dataout <= nl1110OiO OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11i100i_dataout <= wire_nl11i010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i100l_dataout <= wire_nl11i010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i100O_dataout <= wire_nl11i010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i101i_dataout <= wire_nl11i011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i101l_dataout <= wire_nl11i011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i101O_dataout <= wire_nl11i011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10ii_dataout <= wire_nl11i01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10il_dataout <= wire_nl11i01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10iO_dataout <= wire_nl11i01iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10li_dataout <= wire_nl11i01li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10ll_dataout <= wire_nl11i01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10lO_dataout <= wire_nl11i01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10Oi_dataout <= wire_nl11i01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10Ol_dataout <= wire_nl11i01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i10OO_dataout <= wire_nl11i01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i11l_dataout <= wire_nl11i11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i11O_dataout <= wire_nl1000i_w_lg_nl11i10l8339w(0) WHEN (nl11i1lO XOR nl11i1li) = '1' ELSE nl11i10l; + wire_nl11i1i_dataout <= lmi_addr(4) AND NOT(wire_niO01l0O_dataout); + wire_nl11i1i0i_dataout <= wire_nl11i000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1i0l_dataout <= wire_nl11i000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1i0O_dataout <= wire_nl11i000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1i1i_dataout <= wire_nl11i001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1i1l_dataout <= wire_nl11i001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1i1O_dataout <= wire_nl11i001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1ii_dataout <= nl11i1li AND NOT(wire_niO01l0O_dataout); + wire_nl11i1iii_dataout <= wire_nl11i00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1iil_dataout <= wire_nl11i00il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1iiO_dataout <= wire_nl11i00iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1ili_dataout <= wire_nl11i00li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1ill_dataout <= wire_nl11i00ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1ilO_dataout <= wire_nl11i00lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1iO_dataout <= nl11i11i AND NOT(wire_niO01l0O_dataout); + wire_nl11i1iOi_dataout <= wire_nl11i00Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1iOl_dataout <= wire_nl11i00Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1iOO_dataout <= wire_nl11i00OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1l_dataout <= lmi_addr(5) AND NOT(wire_niO01l0O_dataout); + wire_nl11i1l0i_dataout <= wire_nl11i0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1l0l_dataout <= wire_nl11i0i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1l0O_dataout <= wire_nl11i0i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1l1i_dataout <= wire_nl11i0i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1l1l_dataout <= wire_nl11i0i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1l1O_dataout <= wire_nl11i0i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1lii_dataout <= wire_nl11i0iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1lil_dataout <= wire_nl11i0iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1liO_dataout <= wire_nl11i0iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1ll_dataout <= nl11i1Oi AND NOT(wire_niO01O0O_dataout); + wire_nl11i1lli_dataout <= wire_nl11i0ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1lll_dataout <= wire_nl11i0lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1llO_dataout <= wire_nl11i0liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1lOi_dataout <= wire_nl11i0lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1lOl_dataout <= wire_nl11i0lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1lOO_dataout <= wire_nl11i0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1O_dataout <= lmi_addr(6) AND NOT(wire_niO01l0O_dataout); + wire_nl11i1O0i_dataout <= wire_nl11i0ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1O0l_dataout <= wire_nl11i0ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1O0O_dataout <= wire_nl11i0iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1O1i_dataout <= wire_nl11i0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1O1l_dataout <= wire_nl11i0lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1O1O_dataout <= wire_nl11i0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1Oii_dataout <= wire_nl11i0iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1Oil_dataout <= wire_nl11i0iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1OiO_dataout <= wire_nl11i0l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1Ol_dataout <= nl11i1lO AND NOT(wire_niO01O0O_dataout); + wire_nl11i1Oli_dataout <= wire_nl11i0l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1Oll_dataout <= wire_nl11i0l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1OlO_dataout <= wire_nl11i0l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1OO_dataout <= nl11i1il AND NOT(wire_niO01O0O_dataout); + wire_nl11i1OOi_dataout <= wire_nl11i0l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1OOl_dataout <= wire_nl11i0l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11i1OOO_dataout <= wire_nl11i0lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ii00i_dataout <= nl1110l1O OR NOT(niOi1000l); + wire_nl11ii00l_dataout <= nl1110l0i OR NOT(niOi1000l); + wire_nl11ii00O_dataout <= nl1110l0l OR NOT(niOi1000l); + wire_nl11ii01i_dataout <= nl1110iOO OR NOT(niOi1000l); + wire_nl11ii01l_dataout <= nl1110l1i OR NOT(niOi1000l); + wire_nl11ii01O_dataout <= nl1110l1l OR NOT(niOi1000l); + wire_nl11ii0i_dataout <= nl11ii0O AND NOT(wire_niO01O0O_dataout); + wire_nl11ii0il_dataout <= nl1110i0l OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii0iO_dataout <= nl1110i0O OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii0li_dataout <= nl1110iii OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii0ll_dataout <= nl1110iil OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii0lO_dataout <= nl1110iiO OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii0Oi_dataout <= nl1110ili OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii0Ol_dataout <= nl1110ill OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii0OO_dataout <= nl1110ilO OR NOT(wire_nlill0Oll_w_lg_nl111OO1i60373w(0)); + wire_nl11ii10i_dataout <= nl1110OOi OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11ii10l_dataout <= nl1110OOl OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11ii10O_dataout <= nl1110lli OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii11i_dataout <= nl1110Oli OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11ii11l_dataout <= nl1110Oll OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11ii11O_dataout <= nl1110OlO OR NOT(wire_nlill0Oll_w_lg_nl111OO0i60384w(0)); + wire_nl11ii1ii_dataout <= nl1110lll OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii1il_dataout <= nl1110llO OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii1iO_dataout <= nl1110lOi OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii1l_dataout <= nl11i0iO AND NOT(wire_niO01l0O_dataout); + wire_nl11ii1li_dataout <= nl1110lOl OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii1ll_dataout <= nl1110lOO OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii1lO_dataout <= nl1110O1i OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii1Oi_dataout <= nl1110O1l OR NOT(wire_nlill0Oll_w_lg_nl111OO1O60383w(0)); + wire_nl11ii1Ol_dataout <= nl1110iOi OR NOT(niOi1000l); + wire_nl11ii1OO_dataout <= nl1110iOl OR NOT(niOi1000l); + wire_nl11iii_dataout <= lmi_addr(10) AND NOT(wire_niO01l0O_dataout); + wire_nl11iii0i_dataout <= nl11100ll OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iii0l_dataout <= nl11100lO OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iii0O_dataout <= nl11100Oi OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iii1i_dataout <= nl11101il OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iii1l_dataout <= nl11100iO OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iii1O_dataout <= nl11100li OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iiii_dataout <= nl11ii0l AND NOT(wire_niO01O0O_dataout); + wire_nl11iiiii_dataout <= nl11100Ol OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iiiil_dataout <= nl11100OO OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iiiiO_dataout <= nl1110i1i OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iiil_dataout <= nl11ii1i AND NOT(wire_niO01O0O_dataout); + wire_nl11iiili_dataout <= nl1110i1l OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iiill_dataout <= nl1110i1O OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iiilO_dataout <= nl1110i0i OR NOT(wire_nlill0Oll_w_lg_nl111ll1l60372w(0)); + wire_nl11iil_dataout <= lmi_addr(11) AND NOT(wire_niO01l0O_dataout); + wire_nl11iili_dataout <= wire_nl11iilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11iill_dataout <= wire_nl11iiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11iilO_dataout <= wire_niOOO0O_w_lg_nl11ii0O8327w(0) WHEN (wire_w_lg_niOO1iO1l8328w(0) AND wire_w_lg_w_swup_in_range8326w8329w(0)) = '1' ELSE nl11ii0O; + wire_nl11iiO_dataout <= lmi_wren AND NOT(wire_niO01l0O_dataout); + wire_nl11iiOO_dataout <= nl11iiiO WHEN niOO1iO1l = '1' ELSE swup_in(4); + wire_nl11il0i_dataout <= wire_nl1000i_w_lg_nl11il0O8323w(0) WHEN (nl11ilOi XOR nl11illl) = '1' ELSE nl11il0O; + wire_nl11il1O_dataout <= wire_nl11il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ili_dataout <= lmi_rden AND NOT(wire_niO01l0O_dataout); + wire_nl11ilil_dataout <= nl11illl AND NOT(wire_niO01l0O_dataout); + wire_nl11illi_dataout <= nl11il1l AND NOT(wire_niO01l0O_dataout); + wire_nl11illO_dataout <= nl11ilOl AND NOT(wire_niO01O0O_dataout); + wire_nl11ilO0i_dataout <= wire_nl11iOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilO0l_dataout <= wire_nl11iOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilO0O_dataout <= wire_nl11iOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilO1l_dataout <= wire_nl11iOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilO1O_dataout <= wire_nl11iOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOii_dataout <= wire_nl11iOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOil_dataout <= wire_nl11iOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOiO_dataout <= wire_nl11iOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOli_dataout <= wire_nl11iOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOll_dataout <= wire_nl11iOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOlO_dataout <= wire_nl11iOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOO_dataout <= nl11ilOi AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOOi_dataout <= wire_nl11iOO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOOl_dataout <= wire_nl11iOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11ilOOO_dataout <= wire_nl11iOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO00i_dataout <= wire_nl11l11il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO00l_dataout <= wire_nl11l11iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO00O_dataout <= wire_nl11l11li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO01i_dataout <= wire_nl11l110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO01l_dataout <= wire_nl11l110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO01O_dataout <= wire_nl11l11ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0i_dataout <= wire_nl11iOil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11iO0ii_dataout <= wire_nl11l11ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0il_dataout <= wire_nl11l11lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0iO_dataout <= wire_nl11l11Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0l_dataout <= wire_niOOO0O_w_lg_nl11ilOl8319w(0) WHEN (wire_w_lg_niOO1iO1O8320w(0) AND wire_w_lg_w_swup_in_range8318w8321w(0)) = '1' ELSE nl11ilOl; + wire_nl11iO0li_dataout <= wire_nl11l11Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0ll_dataout <= wire_nl11l11OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0lO_dataout <= wire_nl11l101i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0Oi_dataout <= wire_nl11l101l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0Ol_dataout <= wire_nl11l101O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO0OO_dataout <= wire_nl11l100i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO10i_dataout <= wire_nl11iOOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO10l_dataout <= wire_nl11iOOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO10O_dataout <= wire_nl11iOOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO11i_dataout <= wire_nl11iOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO11l_dataout <= wire_nl11iOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO11O_dataout <= wire_nl11iOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1i_dataout <= nl11iliO AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1ii_dataout <= wire_nl11iOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1il_dataout <= wire_nl11iOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1iO_dataout <= wire_nl11iOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1li_dataout <= wire_nl11iOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1ll_dataout <= wire_nl11iOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1lO_dataout <= wire_nl11l111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1O_dataout <= wire_nl11iO0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11iO1Oi_dataout <= wire_nl11l111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1Ol_dataout <= wire_nl11l111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iO1OO_dataout <= wire_nl11l110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOi0i_dataout <= wire_nl11l10il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOi0l_dataout <= wire_nl11l10iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOi0O_dataout <= wire_nl11l10li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOi1i_dataout <= wire_nl11l100l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOi1l_dataout <= wire_nl11l100O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOi1O_dataout <= wire_nl11l10ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOiii_dataout <= wire_nl11l10ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOiil_dataout <= wire_nl11l10lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOiiO_dataout <= wire_nl11l10Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOil_dataout <= nl11iO1l WHEN niOO1iO1O = '1' ELSE swup_in(5); + wire_nl11iOili_dataout <= wire_nl11l10Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOill_dataout <= wire_nl11l10OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOilO_dataout <= wire_nl11l1i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOiOi_dataout <= wire_nl11l1i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOiOl_dataout <= wire_nl11l1i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOiOO_dataout <= wire_nl11l1i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOl0i_dataout <= wire_nl11l1iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOl0l_dataout <= wire_nl11l1iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOl0O_dataout <= wire_nl101Oi0i_dataout WHEN niOi1000O = '1' ELSE nl11l1ili; + wire_nl11iOl1i_dataout <= wire_nl11l1i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOl1l_dataout <= wire_nl11l1i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOl1O_dataout <= wire_nl11l1iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOlii_dataout <= wire_nl101Oi0l_dataout WHEN niOi1000O = '1' ELSE nl11iiOOi; + wire_nl11iOlil_dataout <= wire_nl101Oi0O_dataout WHEN niOi1000O = '1' ELSE nl11iiOOl; + wire_nl11iOliO_dataout <= wire_nl101Oiii_dataout WHEN niOi1000O = '1' ELSE nl11iiOOO; + wire_nl11iOll_dataout <= wire_nl11iOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11iOlli_dataout <= wire_nl101Oiil_dataout WHEN niOi1000O = '1' ELSE nl11il11i; + wire_nl11iOlll_dataout <= wire_nl101OiiO_dataout WHEN niOi1000O = '1' ELSE nl11il11l; + wire_nl11iOllO_dataout <= wire_nl101Oili_dataout WHEN niOi1000O = '1' ELSE nl11il11O; + wire_nl11iOlO_dataout <= wire_nl1000i_w_lg_nl11iOOl8315w(0) WHEN (nl11l10O XOR nl11l10i) = '1' ELSE nl11iOOl; + wire_nl11iOlOi_dataout <= wire_nl101Oill_dataout WHEN niOi1000O = '1' ELSE nl11il10i; + wire_nl11iOlOl_dataout <= wire_nl101OilO_dataout WHEN niOi1000O = '1' ELSE nl11il10l; + wire_nl11iOlOO_dataout <= wire_nl101OiOi_dataout WHEN niOi1000O = '1' ELSE nl11il10O; + wire_nl11iOO0i_dataout <= wire_nl101Ol1l_dataout WHEN niOi1000O = '1' ELSE nl11il1li; + wire_nl11iOO0l_dataout <= wire_nl101Ol1O_dataout WHEN niOi1000O = '1' ELSE nl11il1ll; + wire_nl11iOO0O_dataout <= wire_nl101Ol0i_dataout WHEN niOi1000O = '1' ELSE nl11il1lO; + wire_nl11iOO1i_dataout <= wire_nl101OiOl_dataout WHEN niOi1000O = '1' ELSE nl11il1ii; + wire_nl11iOO1l_dataout <= wire_nl101OiOO_dataout WHEN niOi1000O = '1' ELSE nl11il1il; + wire_nl11iOO1O_dataout <= wire_nl101Ol1i_dataout WHEN niOi1000O = '1' ELSE nl11il1iO; + wire_nl11iOOii_dataout <= wire_nl101Ol0l_dataout WHEN niOi1000O = '1' ELSE nl11il1Oi; + wire_nl11iOOil_dataout <= wire_nl101Ol0O_dataout WHEN niOi1000O = '1' ELSE nl11il1Ol; + wire_nl11iOOiO_dataout <= wire_nl101Olii_dataout WHEN niOi1000O = '1' ELSE nl11il1OO; + wire_nl11iOOli_dataout <= wire_nl101Olil_dataout WHEN niOi1000O = '1' ELSE nl11il01i; + wire_nl11iOOll_dataout <= wire_nl101OliO_dataout WHEN niOi1000O = '1' ELSE nl11il01l; + wire_nl11iOOlO_dataout <= wire_nl101Olli_dataout WHEN niOi1000O = '1' ELSE nl11il01O; + wire_nl11iOOOi_dataout <= wire_nl101Olll_dataout WHEN niOi1000O = '1' ELSE nl11il00i; + wire_nl11iOOOl_dataout <= wire_nl101OllO_dataout WHEN niOi1000O = '1' ELSE nl11il00l; + wire_nl11iOOOO_dataout <= wire_nl101OlOi_dataout WHEN niOi1000O = '1' ELSE nl11il00O; + wire_nl11l00i_dataout <= wire_nl11l00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11l00l_dataout <= wire_niOOO0O_w_lg_nl11l0ii8307w(0) WHEN (nl11l0Ol XOR nl11l0lO) = '1' ELSE nl11l0ii; + wire_nl11l01i_dataout <= nl11l1li WHEN niOO1iO0i = '1' ELSE swup_in(6); + wire_nl11l0i0i_dataout <= wire_nl11li0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0i0l_dataout <= wire_nl11li0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0i0O_dataout <= wire_nl11li0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0i1l_dataout <= wire_nl11li00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0i1O_dataout <= wire_nl11li0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0iii_dataout <= wire_nl11li0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0iil_dataout <= wire_nl11li0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0iiO_dataout <= wire_nl11li0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0ili_dataout <= wire_nl11li0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0ill_dataout <= wire_nl11li0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0ilO_dataout <= wire_nl11lii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0iO_dataout <= nl11l0lO AND NOT(wire_niO01O0O_dataout); + wire_nl11l0iOi_dataout <= wire_nl11lii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0iOl_dataout <= wire_nl11lii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0iOO_dataout <= wire_nl11lii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0l0i_dataout <= wire_nl11liiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0l0l_dataout <= wire_nl11liiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0l0O_dataout <= wire_nl11liili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0l1i_dataout <= wire_nl11lii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0l1l_dataout <= wire_nl11lii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0l1O_dataout <= wire_nl11liiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0lii_dataout <= wire_nl11liill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0lil_dataout <= wire_nl11liilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0liO_dataout <= wire_nl11liiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0ll_dataout <= nl11l01O AND NOT(wire_niO01O0O_dataout); + wire_nl11l0lli_dataout <= wire_nl11liiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0lll_dataout <= wire_nl11liiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0llO_dataout <= wire_nl11lil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0lOi_dataout <= wire_nl11lil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0lOl_dataout <= wire_nl11lil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0lOO_dataout <= wire_nl11lil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0O0i_dataout <= wire_nl11lilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0O0l_dataout <= wire_nl11liliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0O0O_dataout <= wire_nl11lilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0O1i_dataout <= wire_nl11lil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0O1l_dataout <= wire_nl11lil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0O1O_dataout <= wire_nl11lilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0Oi_dataout <= nl11l0OO AND NOT(wire_niO01l0O_dataout); + wire_nl11l0Oii_dataout <= wire_nl11lilll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0Oil_dataout <= wire_nl11lillO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0OiO_dataout <= wire_nl11lilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0Oli_dataout <= wire_nl11lilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0Oll_dataout <= wire_nl11lilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0OlO_dataout <= wire_nl11liO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0OOi_dataout <= wire_nl11liO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0OOl_dataout <= wire_nl11liO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l0OOO_dataout <= wire_nl11liO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11l100i_dataout <= wire_nl100111l_dataout WHEN niOi1000O = '1' ELSE nl11ilili; + wire_nl11l100l_dataout <= wire_nl100111O_dataout WHEN niOi1000O = '1' ELSE nl11ilill; + wire_nl11l100O_dataout <= wire_nl100110i_dataout WHEN niOi1000O = '1' ELSE nl11ililO; + wire_nl11l101i_dataout <= wire_nl101OOOl_dataout WHEN niOi1000O = '1' ELSE nl11iliii; + wire_nl11l101l_dataout <= wire_nl101OOOO_dataout WHEN niOi1000O = '1' ELSE nl11iliil; + wire_nl11l101O_dataout <= wire_nl100111i_dataout WHEN niOi1000O = '1' ELSE nl11iliiO; + wire_nl11l10ii_dataout <= wire_nl100110l_dataout WHEN niOi1000O = '1' ELSE nl11iliOi; + wire_nl11l10il_dataout <= wire_nl100110O_dataout WHEN niOi1000O = '1' ELSE nl11iliOl; + wire_nl11l10iO_dataout <= wire_nl10011ii_dataout WHEN niOi1000O = '1' ELSE nl11iliOO; + wire_nl11l10l_dataout <= nl11l1ii AND NOT(wire_niO01O0O_dataout); + wire_nl11l10li_dataout <= wire_nl10011il_dataout WHEN niOi1000O = '1' ELSE nl11ill1i; + wire_nl11l10ll_dataout <= wire_nl10011iO_dataout WHEN niOi1000O = '1' ELSE nl11ill1l; + wire_nl11l10lO_dataout <= wire_nl10011li_dataout WHEN niOi1000O = '1' ELSE nl11ill1O; + wire_nl11l10Oi_dataout <= wire_nl10011ll_dataout WHEN niOi1000O = '1' ELSE nl11ill0i; + wire_nl11l10Ol_dataout <= wire_nl10011lO_dataout WHEN niOi1000O = '1' ELSE nl11ill0l; + wire_nl11l10OO_dataout <= wire_nl10011Oi_dataout WHEN niOi1000O = '1' ELSE nl11ill0O; + wire_nl11l110i_dataout <= wire_nl101OO1l_dataout WHEN niOi1000O = '1' ELSE nl11il0li; + wire_nl11l110l_dataout <= wire_nl101OO1O_dataout WHEN niOi1000O = '1' ELSE nl11il0ll; + wire_nl11l110O_dataout <= wire_nl101OO0i_dataout WHEN niOi1000O = '1' ELSE nl11il0lO; + wire_nl11l111i_dataout <= wire_nl101OlOl_dataout WHEN niOi1000O = '1' ELSE nl11il0ii; + wire_nl11l111l_dataout <= wire_nl101OlOO_dataout WHEN niOi1000O = '1' ELSE nl11il0il; + wire_nl11l111O_dataout <= wire_nl101OO1i_dataout WHEN niOi1000O = '1' ELSE nl11il0iO; + wire_nl11l11i_dataout <= nl11l10i AND NOT(wire_niO01l0O_dataout); + wire_nl11l11ii_dataout <= wire_nl101OO0l_dataout WHEN niOi1000O = '1' ELSE nl11il0Oi; + wire_nl11l11il_dataout <= wire_nl101OO0O_dataout WHEN niOi1000O = '1' ELSE nl11il0Ol; + wire_nl11l11iO_dataout <= wire_nl101OOii_dataout WHEN niOi1000O = '1' ELSE nl11il0OO; + wire_nl11l11li_dataout <= wire_nl101OOil_dataout WHEN niOi1000O = '1' ELSE nl11ili1i; + wire_nl11l11ll_dataout <= wire_nl101OOiO_dataout WHEN niOi1000O = '1' ELSE nl11ili1l; + wire_nl11l11lO_dataout <= wire_nl101OOli_dataout WHEN niOi1000O = '1' ELSE nl11ili1O; + wire_nl11l11O_dataout <= nl11iOli AND NOT(wire_niO01l0O_dataout); + wire_nl11l11Oi_dataout <= wire_nl101OOll_dataout WHEN niOi1000O = '1' ELSE nl11ili0i; + wire_nl11l11Ol_dataout <= wire_nl101OOlO_dataout WHEN niOi1000O = '1' ELSE nl11ili0l; + wire_nl11l11OO_dataout <= wire_nl101OOOi_dataout WHEN niOi1000O = '1' ELSE nl11ili0O; + wire_nl11l1i0i_dataout <= wire_nl100101l_dataout WHEN niOi1000O = '1' ELSE nl11illli; + wire_nl11l1i0l_dataout <= wire_nl100101O_dataout WHEN niOi1000O = '1' ELSE nl11illll; + wire_nl11l1i0O_dataout <= wire_nl100100i_dataout WHEN niOi1000O = '1' ELSE nl11illlO; + wire_nl11l1i1i_dataout <= wire_nl10011Ol_dataout WHEN niOi1000O = '1' ELSE nl11illii; + wire_nl11l1i1l_dataout <= wire_nl10011OO_dataout WHEN niOi1000O = '1' ELSE nl11illil; + wire_nl11l1i1O_dataout <= wire_nl100101i_dataout WHEN niOi1000O = '1' ELSE nl11illiO; + wire_nl11l1iii_dataout <= wire_nl100100l_dataout WHEN niOi1000O = '1' ELSE nl11illOi; + wire_nl11l1iil_dataout <= wire_nl100100O_dataout WHEN niOi1000O = '1' ELSE nl11illOl; + wire_nl11l1iiO_dataout <= wire_nl10010ii_dataout WHEN niOi1000O = '1' ELSE nl11illOO; + wire_nl11l1il_dataout <= nl11l10O AND NOT(wire_niO01O0O_dataout); + wire_nl11l1iO_dataout <= nl11l11l AND NOT(wire_niO01O0O_dataout); + wire_nl11l1ll_dataout <= wire_nl11l1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11l1lO_dataout <= wire_nl11l01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11l1Oi_dataout <= wire_niOOO0O_w_lg_nl11l1ii8311w(0) WHEN (wire_w_lg_niOO1iO0i8312w(0) AND wire_w_lg_w_swup_in_range8310w8313w(0)) = '1' ELSE nl11l1ii; + wire_nl11li00i_dataout <= wire_nl11ll1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li00l_dataout <= wire_nl11ll1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li00O_dataout <= wire_nl101Oi0i_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll1li_dataout; + wire_nl11li01i_dataout <= wire_nl11ll10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li01l_dataout <= wire_nl11ll10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li01O_dataout <= wire_nl11ll1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li0i_dataout <= wire_nl11li0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li0ii_dataout <= wire_nl101Oi0l_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll1ll_dataout; + wire_nl11li0il_dataout <= wire_nl101Oi0O_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll1lO_dataout; + wire_nl11li0iO_dataout <= wire_nl101Oiii_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll1Oi_dataout; + wire_nl11li0l_dataout <= wire_nl11liiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li0li_dataout <= wire_nl101Oiil_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll1Ol_dataout; + wire_nl11li0ll_dataout <= wire_nl101OiiO_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll1OO_dataout; + wire_nl11li0lO_dataout <= wire_nl101Oili_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll01i_dataout; + wire_nl11li0O_dataout <= wire_nl1000i_w_lg_nl11l0OO8303w(0) WHEN (wire_w_lg_niOO1iO0l8304w(0) AND (nl0i1liiO XOR nl11li1O)) = '1' ELSE nl11l0OO; + wire_nl11li0Oi_dataout <= wire_nl101Oill_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll01l_dataout; + wire_nl11li0Ol_dataout <= wire_nl101OilO_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll01O_dataout; + wire_nl11li0OO_dataout <= wire_nl101OiOi_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll00i_dataout; + wire_nl11li10i_dataout <= wire_nl11liOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li10l_dataout <= wire_nl11liOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li10O_dataout <= wire_nl11liOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li11i_dataout <= wire_nl11liO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li11l_dataout <= wire_nl11liO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li11O_dataout <= wire_nl11liOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1i_dataout <= nl11l0Ol AND NOT(wire_niO01l0O_dataout); + wire_nl11li1ii_dataout <= wire_nl11liOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1il_dataout <= wire_nl11liOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1iO_dataout <= wire_nl11liOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1l_dataout <= nl11l0li AND NOT(wire_niO01l0O_dataout); + wire_nl11li1li_dataout <= wire_nl11liOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1ll_dataout <= wire_nl11liOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1lO_dataout <= wire_nl11ll11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1Oi_dataout <= wire_nl11ll11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1Ol_dataout <= wire_nl11ll11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11li1OO_dataout <= wire_nl11ll10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lii0i_dataout <= wire_nl101Ol1l_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0il_dataout; + wire_nl11lii0l_dataout <= wire_nl101Ol1O_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0iO_dataout; + wire_nl11lii0O_dataout <= wire_nl101Ol0i_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0li_dataout; + wire_nl11lii1i_dataout <= wire_nl101OiOl_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll00l_dataout; + wire_nl11lii1l_dataout <= wire_nl101OiOO_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll00O_dataout; + wire_nl11lii1O_dataout <= wire_nl101Ol1i_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0ii_dataout; + wire_nl11liiii_dataout <= wire_nl101Ol0l_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0ll_dataout; + wire_nl11liiil_dataout <= wire_nl101Ol0O_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0lO_dataout; + wire_nl11liiiO_dataout <= wire_nl101Olii_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0Oi_dataout; + wire_nl11liili_dataout <= wire_nl101Olil_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0Ol_dataout; + wire_nl11liill_dataout <= wire_nl101OliO_dataout WHEN niOi100ii = '1' ELSE wire_nl11ll0OO_dataout; + wire_nl11liilO_dataout <= wire_nl101Olli_dataout WHEN niOi100ii = '1' ELSE wire_nl11lli1i_dataout; + wire_nl11liiO_dataout <= nl11li1O WHEN niOO1iO0l = '1' ELSE nl0i1liiO; + wire_nl11liiOi_dataout <= wire_nl101Olll_dataout WHEN niOi100ii = '1' ELSE wire_nl11lli1l_dataout; + wire_nl11liiOl_dataout <= wire_nl101OllO_dataout WHEN niOi100ii = '1' ELSE wire_nl11lli1O_dataout; + wire_nl11liiOO_dataout <= wire_nl101OlOi_dataout WHEN niOi100ii = '1' ELSE wire_nl11lli0i_dataout; + wire_nl11lil0i_dataout <= wire_nl101OO1l_dataout WHEN niOi100ii = '1' ELSE wire_nl11lliil_dataout; + wire_nl11lil0l_dataout <= wire_nl101OO1O_dataout WHEN niOi100ii = '1' ELSE wire_nl11lliiO_dataout; + wire_nl11lil0O_dataout <= wire_nl101OO0i_dataout WHEN niOi100ii = '1' ELSE wire_nl11llili_dataout; + wire_nl11lil1i_dataout <= wire_nl101OlOl_dataout WHEN niOi100ii = '1' ELSE wire_nl11lli0l_dataout; + wire_nl11lil1l_dataout <= wire_nl101OlOO_dataout WHEN niOi100ii = '1' ELSE wire_nl11lli0O_dataout; + wire_nl11lil1O_dataout <= wire_nl101OO1i_dataout WHEN niOi100ii = '1' ELSE wire_nl11lliii_dataout; + wire_nl11lilii_dataout <= wire_nl101OO0l_dataout WHEN niOi100ii = '1' ELSE wire_nl11llill_dataout; + wire_nl11lilil_dataout <= wire_nl101OO0O_dataout WHEN niOi100ii = '1' ELSE wire_nl11llilO_dataout; + wire_nl11liliO_dataout <= wire_nl101OOii_dataout WHEN niOi100ii = '1' ELSE wire_nl11lliOi_dataout; + wire_nl11lilli_dataout <= wire_nl101OOil_dataout WHEN niOi100ii = '1' ELSE wire_nl11lliOl_dataout; + wire_nl11lilll_dataout <= wire_nl101OOiO_dataout WHEN niOi100ii = '1' ELSE wire_nl11lliOO_dataout; + wire_nl11lillO_dataout <= wire_nl101OOli_dataout WHEN niOi100ii = '1' ELSE wire_nl11lll1i_dataout; + wire_nl11lilO_dataout <= wire_nl11liOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11lilOi_dataout <= wire_nl101OOll_dataout WHEN niOi100ii = '1' ELSE wire_nl11lll1l_dataout; + wire_nl11lilOl_dataout <= wire_nl101OOlO_dataout WHEN niOi100ii = '1' ELSE wire_nl11lll1O_dataout; + wire_nl11lilOO_dataout <= wire_nl101OOOi_dataout WHEN niOi100ii = '1' ELSE wire_nl11lll0i_dataout; + wire_nl11liO0i_dataout <= wire_nl100111l_dataout WHEN niOi100ii = '1' ELSE wire_nl11lllil_dataout; + wire_nl11liO0l_dataout <= wire_nl100111O_dataout WHEN niOi100ii = '1' ELSE wire_nl11llliO_dataout; + wire_nl11liO0O_dataout <= wire_nl100110i_dataout WHEN niOi100ii = '1' ELSE wire_nl11lllli_dataout; + wire_nl11liO1i_dataout <= wire_nl101OOOl_dataout WHEN niOi100ii = '1' ELSE wire_nl11lll0l_dataout; + wire_nl11liO1l_dataout <= wire_nl101OOOO_dataout WHEN niOi100ii = '1' ELSE wire_nl11lll0O_dataout; + wire_nl11liO1O_dataout <= wire_nl100111i_dataout WHEN niOi100ii = '1' ELSE wire_nl11lllii_dataout; + wire_nl11liOi_dataout <= wire_niOOO0O_w_lg_nl11liOO8300w(0) WHEN (nl11llii XOR nl11ll0l) = '1' ELSE nl11liOO; + wire_nl11liOii_dataout <= wire_nl100110l_dataout WHEN niOi100ii = '1' ELSE wire_nl11lllll_dataout; + wire_nl11liOil_dataout <= wire_nl100110O_dataout WHEN niOi100ii = '1' ELSE wire_nl11llllO_dataout; + wire_nl11liOiO_dataout <= wire_nl10011ii_dataout WHEN niOi100ii = '1' ELSE wire_nl11lllOi_dataout; + wire_nl11liOli_dataout <= wire_nl10011il_dataout WHEN niOi100ii = '1' ELSE wire_nl11lllOl_dataout; + wire_nl11liOll_dataout <= wire_nl10011iO_dataout WHEN niOi100ii = '1' ELSE wire_nl11lllOO_dataout; + wire_nl11liOlO_dataout <= wire_nl10011li_dataout WHEN niOi100ii = '1' ELSE wire_nl11llO1i_dataout; + wire_nl11liOOi_dataout <= wire_nl10011ll_dataout WHEN niOi100ii = '1' ELSE wire_nl11llO1l_dataout; + wire_nl11liOOl_dataout <= wire_nl10011lO_dataout WHEN niOi100ii = '1' ELSE wire_nl11llO1O_dataout; + wire_nl11liOOO_dataout <= wire_nl10011Oi_dataout WHEN niOi100ii = '1' ELSE wire_nl11llO0i_dataout; + wire_nl11ll00i_dataout <= nl11il10O WHEN niOi10iiO = '1' ELSE nl11l1l0O; + wire_nl11ll00l_dataout <= nl11il1ii WHEN niOi10iiO = '1' ELSE nl11l1lii; + wire_nl11ll00O_dataout <= nl11il1il WHEN niOi10iiO = '1' ELSE nl11l1lil; + wire_nl11ll01i_dataout <= nl11il11O WHEN niOi10iiO = '1' ELSE nl11l1l1O; + wire_nl11ll01l_dataout <= nl11il10i WHEN niOi10iiO = '1' ELSE nl11l1l0i; + wire_nl11ll01O_dataout <= nl11il10l WHEN niOi10iiO = '1' ELSE nl11l1l0l; + wire_nl11ll0i_dataout <= nl11lill AND NOT(wire_niO01O0O_dataout); + wire_nl11ll0ii_dataout <= nl11il1iO WHEN niOi10iiO = '1' ELSE nl11l1liO; + wire_nl11ll0il_dataout <= nl11il1li WHEN niOi10iiO = '1' ELSE nl11l1lli; + wire_nl11ll0iO_dataout <= nl11il1ll WHEN niOi10iiO = '1' ELSE nl11l1lll; + wire_nl11ll0li_dataout <= nl11il1lO WHEN niOi10iiO = '1' ELSE nl11l1llO; + wire_nl11ll0ll_dataout <= nl11il1Oi WHEN niOi10iiO = '1' ELSE nl11l1lOi; + wire_nl11ll0lO_dataout <= nl11il1Ol WHEN niOi10iiO = '1' ELSE nl11l1lOl; + wire_nl11ll0O_dataout <= nl11llil AND NOT(wire_niO01l0O_dataout); + wire_nl11ll0Oi_dataout <= nl11il1OO WHEN niOi10iiO = '1' ELSE nl11l1lOO; + wire_nl11ll0Ol_dataout <= nl11il01i WHEN niOi10iiO = '1' ELSE nl11l1O1i; + wire_nl11ll0OO_dataout <= nl11il01l WHEN niOi10iiO = '1' ELSE nl11l1O1l; + wire_nl11ll10i_dataout <= wire_nl100101l_dataout WHEN niOi100ii = '1' ELSE wire_nl11llOil_dataout; + wire_nl11ll10l_dataout <= wire_nl100101O_dataout WHEN niOi100ii = '1' ELSE wire_nl11llOiO_dataout; + wire_nl11ll10O_dataout <= wire_nl100100i_dataout WHEN niOi100ii = '1' ELSE wire_nl11llOli_dataout; + wire_nl11ll11i_dataout <= wire_nl10011Ol_dataout WHEN niOi100ii = '1' ELSE wire_nl11llO0l_dataout; + wire_nl11ll11l_dataout <= wire_nl10011OO_dataout WHEN niOi100ii = '1' ELSE wire_nl11llO0O_dataout; + wire_nl11ll11O_dataout <= wire_nl100101i_dataout WHEN niOi100ii = '1' ELSE wire_nl11llOii_dataout; + wire_nl11ll1ii_dataout <= wire_nl100100l_dataout WHEN niOi100ii = '1' ELSE wire_nl11llOll_dataout; + wire_nl11ll1il_dataout <= wire_nl100100O_dataout WHEN niOi100ii = '1' ELSE wire_nl11llOlO_dataout; + wire_nl11ll1iO_dataout <= wire_nl10010ii_dataout WHEN niOi100ii = '1' ELSE wire_nl11llOOi_dataout; + wire_nl11ll1l_dataout <= nl11ll0l AND NOT(wire_niO01O0O_dataout); + wire_nl11ll1li_dataout <= nl11l1ili WHEN niOi10iiO = '1' ELSE nl11ilO1i; + wire_nl11ll1ll_dataout <= nl11iiOOi WHEN niOi10iiO = '1' ELSE nl11l1iOi; + wire_nl11ll1lO_dataout <= nl11iiOOl WHEN niOi10iiO = '1' ELSE nl11l1iOl; + wire_nl11ll1Oi_dataout <= nl11iiOOO WHEN niOi10iiO = '1' ELSE nl11l1iOO; + wire_nl11ll1Ol_dataout <= nl11il11i WHEN niOi10iiO = '1' ELSE nl11l1l1i; + wire_nl11ll1OO_dataout <= nl11il11l WHEN niOi10iiO = '1' ELSE nl11l1l1l; + wire_nl11lli0i_dataout <= nl11il00O WHEN niOi10iiO = '1' ELSE nl11l1O0O; + wire_nl11lli0l_dataout <= nl11il0ii WHEN niOi10iiO = '1' ELSE nl11l1Oii; + wire_nl11lli0O_dataout <= nl11il0il WHEN niOi10iiO = '1' ELSE nl11l1Oil; + wire_nl11lli1i_dataout <= nl11il01O WHEN niOi10iiO = '1' ELSE nl11l1O1O; + wire_nl11lli1l_dataout <= nl11il00i WHEN niOi10iiO = '1' ELSE nl11l1O0i; + wire_nl11lli1O_dataout <= nl11il00l WHEN niOi10iiO = '1' ELSE nl11l1O0l; + wire_nl11lliii_dataout <= nl11il0iO WHEN niOi10iiO = '1' ELSE nl11l1OiO; + wire_nl11lliil_dataout <= nl11il0li WHEN niOi10iiO = '1' ELSE nl11l1Oli; + wire_nl11lliiO_dataout <= nl11il0ll WHEN niOi10iiO = '1' ELSE nl11l1Oll; + wire_nl11llili_dataout <= nl11il0lO WHEN niOi10iiO = '1' ELSE nl11l1OlO; + wire_nl11llill_dataout <= nl11il0Oi WHEN niOi10iiO = '1' ELSE nl11l1OOi; + wire_nl11llilO_dataout <= nl11il0Ol WHEN niOi10iiO = '1' ELSE nl11l1OOl; + wire_nl11lliO_dataout <= nl11llii AND NOT(wire_niO01l0O_dataout); + wire_nl11lliOi_dataout <= nl11il0OO WHEN niOi10iiO = '1' ELSE nl11l1OOO; + wire_nl11lliOl_dataout <= nl11ili1i WHEN niOi10iiO = '1' ELSE nl11l011i; + wire_nl11lliOO_dataout <= nl11ili1l WHEN niOi10iiO = '1' ELSE nl11l011l; + wire_nl11lll0i_dataout <= nl11ili0O WHEN niOi10iiO = '1' ELSE nl11l010O; + wire_nl11lll0l_dataout <= nl11iliii WHEN niOi10iiO = '1' ELSE nl11l01ii; + wire_nl11lll0O_dataout <= nl11iliil WHEN niOi10iiO = '1' ELSE nl11l01il; + wire_nl11lll1i_dataout <= nl11ili1O WHEN niOi10iiO = '1' ELSE nl11l011O; + wire_nl11lll1l_dataout <= nl11ili0i WHEN niOi10iiO = '1' ELSE nl11l010i; + wire_nl11lll1O_dataout <= nl11ili0l WHEN niOi10iiO = '1' ELSE nl11l010l; + wire_nl11llli_dataout <= nl11ll1O AND NOT(wire_niO01l0O_dataout); + wire_nl11lllii_dataout <= nl11iliiO WHEN niOi10iiO = '1' ELSE nl11l01iO; + wire_nl11lllil_dataout <= nl11ilili WHEN niOi10iiO = '1' ELSE nl11l01li; + wire_nl11llliO_dataout <= nl11ilill WHEN niOi10iiO = '1' ELSE nl11l01ll; + wire_nl11lllli_dataout <= nl11ililO WHEN niOi10iiO = '1' ELSE nl11l01lO; + wire_nl11lllll_dataout <= nl11iliOi WHEN niOi10iiO = '1' ELSE nl11l01Oi; + wire_nl11llllO_dataout <= nl11iliOl WHEN niOi10iiO = '1' ELSE nl11l01Ol; + wire_nl11lllO_dataout <= wire_nl11llOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lllOi_dataout <= nl11iliOO WHEN niOi10iiO = '1' ELSE nl11l01OO; + wire_nl11lllOl_dataout <= nl11ill1i WHEN niOi10iiO = '1' ELSE nl11l001i; + wire_nl11lllOO_dataout <= nl11ill1l WHEN niOi10iiO = '1' ELSE nl11l001l; + wire_nl11llO0i_dataout <= nl11ill0O WHEN niOi10iiO = '1' ELSE nl11l000O; + wire_nl11llO0l_dataout <= nl11illii WHEN niOi10iiO = '1' ELSE nl11l00ii; + wire_nl11llO0O_dataout <= nl11illil WHEN niOi10iiO = '1' ELSE nl11l00il; + wire_nl11llO1i_dataout <= nl11ill1O WHEN niOi10iiO = '1' ELSE nl11l001O; + wire_nl11llO1l_dataout <= nl11ill0i WHEN niOi10iiO = '1' ELSE nl11l000i; + wire_nl11llO1O_dataout <= nl11ill0l WHEN niOi10iiO = '1' ELSE nl11l000l; + wire_nl11llOi_dataout <= wire_nl11lO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11llOii_dataout <= nl11illiO WHEN niOi10iiO = '1' ELSE nl11l00iO; + wire_nl11llOil_dataout <= nl11illli WHEN niOi10iiO = '1' ELSE nl11l00li; + wire_nl11llOiO_dataout <= nl11illll WHEN niOi10iiO = '1' ELSE nl11l00ll; + wire_nl11llOl_dataout <= wire_nl1000i_w_lg_nl11llil8296w(0) WHEN (wire_w_lg_niOO1iO0O8297w(0) AND (nl0i1lOOi XOR nl11llll)) = '1' ELSE nl11llil; + wire_nl11llOli_dataout <= nl11illlO WHEN niOi10iiO = '1' ELSE nl11l00lO; + wire_nl11llOll_dataout <= nl11illOi WHEN niOi10iiO = '1' ELSE nl11l00Oi; + wire_nl11llOlO_dataout <= nl11illOl WHEN niOi10iiO = '1' ELSE nl11l00Ol; + wire_nl11llOOi_dataout <= nl11illOO WHEN niOi10iiO = '1' ELSE nl11l00OO; + wire_nl11lO0l_dataout <= wire_nl11lO0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11lO0O_dataout <= wire_niOOO0O_w_lg_nl11lOil8293w(0) WHEN (nl11lOOO XOR nl11lOOi) = '1' ELSE nl11lOil; + wire_nl11lO1l_dataout <= nl11llll WHEN niOO1iO0O = '1' ELSE nl0i1lOOi; + wire_nl11lOli_dataout <= nl11lOOi AND NOT(wire_niO01O0O_dataout); + wire_nl11lOlO_dataout <= nl11lO0i AND NOT(wire_niO01O0O_dataout); + wire_nl11lOO0l_dataout <= wire_nl11O1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOO0O_dataout <= wire_nl11O1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOii_dataout <= wire_nl11O1lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOil_dataout <= wire_nl11O1llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOiO_dataout <= wire_nl11O1lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOl_dataout <= nl11O11i AND NOT(wire_niO01l0O_dataout); + wire_nl11lOOli_dataout <= wire_nl11O1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOll_dataout <= wire_nl11O1lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOlO_dataout <= wire_nl11O1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOOi_dataout <= wire_nl11O1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOOl_dataout <= wire_nl11O1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11lOOOO_dataout <= wire_nl11O1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O000i_dataout <= wire_nl101OOOl_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1il_dataout; + wire_nl11O000l_dataout <= wire_nl101OOOO_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1iO_dataout; + wire_nl11O000O_dataout <= wire_nl100111i_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1li_dataout; + wire_nl11O001i_dataout <= wire_nl101OOll_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi10l_dataout; + wire_nl11O001l_dataout <= wire_nl101OOlO_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi10O_dataout; + wire_nl11O001O_dataout <= wire_nl101OOOi_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1ii_dataout; + wire_nl11O00ii_dataout <= wire_nl100111l_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1ll_dataout; + wire_nl11O00il_dataout <= wire_nl100111O_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1lO_dataout; + wire_nl11O00iO_dataout <= wire_nl100110i_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1Oi_dataout; + wire_nl11O00l_dataout <= nl11O1lO AND NOT(wire_niO01O0O_dataout); + wire_nl11O00li_dataout <= wire_nl100110l_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1Ol_dataout; + wire_nl11O00ll_dataout <= wire_nl100110O_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi1OO_dataout; + wire_nl11O00lO_dataout <= wire_nl10011ii_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi01i_dataout; + wire_nl11O00Oi_dataout <= wire_nl10011il_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi01l_dataout; + wire_nl11O00Ol_dataout <= wire_nl10011iO_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi01O_dataout; + wire_nl11O00OO_dataout <= wire_nl10011li_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi00i_dataout; + wire_nl11O010i_dataout <= wire_nl101OlOl_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0Oil_dataout; + wire_nl11O010l_dataout <= wire_nl101OlOO_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0OiO_dataout; + wire_nl11O010O_dataout <= wire_nl101OO1i_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0Oli_dataout; + wire_nl11O011i_dataout <= wire_nl101Olll_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0O0l_dataout; + wire_nl11O011l_dataout <= wire_nl101OllO_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0O0O_dataout; + wire_nl11O011O_dataout <= wire_nl101OlOi_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0Oii_dataout; + wire_nl11O01ii_dataout <= wire_nl101OO1l_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0Oll_dataout; + wire_nl11O01il_dataout <= wire_nl101OO1O_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0OlO_dataout; + wire_nl11O01iO_dataout <= wire_nl101OO0i_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0OOi_dataout; + wire_nl11O01li_dataout <= wire_nl101OO0l_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0OOl_dataout; + wire_nl11O01ll_dataout <= wire_nl101OO0O_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0OOO_dataout; + wire_nl11O01lO_dataout <= wire_nl101OOii_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi11i_dataout; + wire_nl11O01O_dataout <= nl11O00O AND NOT(wire_niO01O0O_dataout); + wire_nl11O01Oi_dataout <= wire_nl101OOil_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi11l_dataout; + wire_nl11O01Ol_dataout <= wire_nl101OOiO_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi11O_dataout; + wire_nl11O01OO_dataout <= wire_nl101OOli_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi10i_dataout; + wire_nl11O0i0i_dataout <= wire_nl10011Ol_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0il_dataout; + wire_nl11O0i0l_dataout <= wire_nl10011OO_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0iO_dataout; + wire_nl11O0i0O_dataout <= wire_nl100101i_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0li_dataout; + wire_nl11O0i1i_dataout <= wire_nl10011ll_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi00l_dataout; + wire_nl11O0i1l_dataout <= wire_nl10011lO_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi00O_dataout; + wire_nl11O0i1O_dataout <= wire_nl10011Oi_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0ii_dataout; + wire_nl11O0ii_dataout <= nl11O0iO AND NOT(wire_niO01l0O_dataout); + wire_nl11O0iii_dataout <= wire_nl100101l_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0ll_dataout; + wire_nl11O0iil_dataout <= wire_nl100101O_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0lO_dataout; + wire_nl11O0iiO_dataout <= wire_nl100100i_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0Oi_dataout; + wire_nl11O0ili_dataout <= wire_nl100100l_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0Ol_dataout; + wire_nl11O0ill_dataout <= wire_nl100100O_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oi0OO_dataout; + wire_nl11O0ilO_dataout <= wire_nl10010ii_dataout WHEN niOi100iO = '1' ELSE wire_nl11Oii1i_dataout; + wire_nl11O0iOi_dataout <= nl11ilO1i WHEN niOi10iiO = '1' ELSE nl11l0i1i; + wire_nl11O0iOl_dataout <= nl11l1iOi WHEN niOi10iiO = '1' ELSE nl11lO11i; + wire_nl11O0iOO_dataout <= nl11l1iOl WHEN niOi10iiO = '1' ELSE nl11lO11l; + wire_nl11O0l0i_dataout <= nl11l1l1O WHEN niOi10iiO = '1' ELSE nl11lO10O; + wire_nl11O0l0l_dataout <= nl11l1l0i WHEN niOi10iiO = '1' ELSE nl11lO1ii; + wire_nl11O0l0O_dataout <= nl11l1l0l WHEN niOi10iiO = '1' ELSE nl11lO1il; + wire_nl11O0l1i_dataout <= nl11l1iOO WHEN niOi10iiO = '1' ELSE nl11lO11O; + wire_nl11O0l1l_dataout <= nl11l1l1i WHEN niOi10iiO = '1' ELSE nl11lO10i; + wire_nl11O0l1O_dataout <= nl11l1l1l WHEN niOi10iiO = '1' ELSE nl11lO10l; + wire_nl11O0li_dataout <= nl11O0il AND NOT(wire_niO01l0O_dataout); + wire_nl11O0lii_dataout <= nl11l1l0O WHEN niOi10iiO = '1' ELSE nl11lO1iO; + wire_nl11O0lil_dataout <= nl11l1lii WHEN niOi10iiO = '1' ELSE nl11lO1li; + wire_nl11O0liO_dataout <= nl11l1lil WHEN niOi10iiO = '1' ELSE nl11lO1ll; + wire_nl11O0ll_dataout <= nl11O00i AND NOT(wire_niO01l0O_dataout); + wire_nl11O0lli_dataout <= nl11l1liO WHEN niOi10iiO = '1' ELSE nl11lO1lO; + wire_nl11O0lll_dataout <= nl11l1lli WHEN niOi10iiO = '1' ELSE nl11lO1Oi; + wire_nl11O0llO_dataout <= nl11l1lll WHEN niOi10iiO = '1' ELSE nl11lO1Ol; + wire_nl11O0lOi_dataout <= nl11l1llO WHEN niOi10iiO = '1' ELSE nl11lO1OO; + wire_nl11O0lOl_dataout <= nl11l1lOi WHEN niOi10iiO = '1' ELSE nl11lO01i; + wire_nl11O0lOO_dataout <= nl11l1lOl WHEN niOi10iiO = '1' ELSE nl11lO01l; + wire_nl11O0O0i_dataout <= nl11l1O1O WHEN niOi10iiO = '1' ELSE nl11lO00O; + wire_nl11O0O0l_dataout <= nl11l1O0i WHEN niOi10iiO = '1' ELSE nl11lO0ii; + wire_nl11O0O0O_dataout <= nl11l1O0l WHEN niOi10iiO = '1' ELSE nl11lO0il; + wire_nl11O0O1i_dataout <= nl11l1lOO WHEN niOi10iiO = '1' ELSE nl11lO01O; + wire_nl11O0O1l_dataout <= nl11l1O1i WHEN niOi10iiO = '1' ELSE nl11lO00i; + wire_nl11O0O1O_dataout <= nl11l1O1l WHEN niOi10iiO = '1' ELSE nl11lO00l; + wire_nl11O0Oi_dataout <= wire_nl11O0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O0Oii_dataout <= nl11l1O0O WHEN niOi10iiO = '1' ELSE nl11lO0iO; + wire_nl11O0Oil_dataout <= nl11l1Oii WHEN niOi10iiO = '1' ELSE nl11lO0li; + wire_nl11O0OiO_dataout <= nl11l1Oil WHEN niOi10iiO = '1' ELSE nl11lO0ll; + wire_nl11O0Ol_dataout <= wire_nl11Oi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O0Oli_dataout <= nl11l1OiO WHEN niOi10iiO = '1' ELSE nl11lO0lO; + wire_nl11O0Oll_dataout <= nl11l1Oli WHEN niOi10iiO = '1' ELSE nl11lO0Oi; + wire_nl11O0OlO_dataout <= nl11l1Oll WHEN niOi10iiO = '1' ELSE nl11lO0Ol; + wire_nl11O0OO_dataout <= wire_nl1000i_w_lg_nl11O0iO8282w(0) WHEN (wire_w_lg_niOO1iOil8283w(0) AND (nl0i1lOOO XOR nl11O0lO)) = '1' ELSE nl11O0iO; + wire_nl11O0OOi_dataout <= nl11l1OlO WHEN niOi10iiO = '1' ELSE nl11lO0OO; + wire_nl11O0OOl_dataout <= nl11l1OOi WHEN niOi10iiO = '1' ELSE nl11lOi1i; + wire_nl11O0OOO_dataout <= nl11l1OOl WHEN niOi10iiO = '1' ELSE nl11lOi1l; + wire_nl11O100i_dataout <= wire_nl11O01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O100l_dataout <= wire_nl11O01iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O100O_dataout <= wire_nl11O01li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O101i_dataout <= wire_nl11O010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O101l_dataout <= wire_nl11O010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O101O_dataout <= wire_nl11O01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10ii_dataout <= wire_nl11O01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10il_dataout <= wire_nl11O01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10iO_dataout <= wire_nl11O01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10l_dataout <= wire_nl11O1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10li_dataout <= wire_nl11O01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10ll_dataout <= wire_nl11O01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10lO_dataout <= wire_nl11O001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10O_dataout <= wire_nl11O1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10Oi_dataout <= wire_nl11O001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10Ol_dataout <= wire_nl11O001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O10OO_dataout <= wire_nl11O000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O110i_dataout <= wire_nl11O1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O110l_dataout <= wire_nl11O1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O110O_dataout <= wire_nl11O1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O111i_dataout <= wire_nl11O1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O111l_dataout <= wire_nl11O1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O111O_dataout <= wire_nl11O1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11ii_dataout <= wire_nl11O1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11il_dataout <= wire_nl11O1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11iO_dataout <= wire_nl11O1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11l_dataout <= nl11lOOO AND NOT(wire_niO01l0O_dataout); + wire_nl11O11li_dataout <= wire_nl11O1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11ll_dataout <= wire_nl11O1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11lO_dataout <= wire_nl11O011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11O_dataout <= nl11lOll AND NOT(wire_niO01l0O_dataout); + wire_nl11O11Oi_dataout <= wire_nl11O011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11Ol_dataout <= wire_nl11O011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O11OO_dataout <= wire_nl11O010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1i0i_dataout <= wire_nl11O00il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1i0l_dataout <= wire_nl11O00iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1i0O_dataout <= wire_nl11O00li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1i1i_dataout <= wire_nl11O000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1i1l_dataout <= wire_nl11O000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1i1O_dataout <= wire_nl11O00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1ii_dataout <= wire_nl1000i_w_lg_nl11O11i8289w(0) WHEN (wire_w_lg_niOO1iOii8290w(0) AND (nl0i1lOOl XOR nl11O10i)) = '1' ELSE nl11O11i; + wire_nl11O1iii_dataout <= wire_nl11O00ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1iil_dataout <= wire_nl11O00lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1iiO_dataout <= wire_nl11O00Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1ili_dataout <= wire_nl11O00Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1ill_dataout <= wire_nl11O00OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1ilO_dataout <= wire_nl11O0i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1iOi_dataout <= wire_nl11O0i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1iOl_dataout <= wire_nl11O0i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1iOO_dataout <= wire_nl11O0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1l0i_dataout <= wire_nl11O0iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1l0l_dataout <= wire_nl11O0iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1l0O_dataout <= wire_nl11O0ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1l1i_dataout <= wire_nl11O0i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1l1l_dataout <= wire_nl11O0i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1l1O_dataout <= wire_nl11O0iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1li_dataout <= nl11O10i WHEN niOO1iOii = '1' ELSE nl0i1lOOl; + wire_nl11O1lii_dataout <= wire_nl11O0ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1lil_dataout <= wire_nl11O0ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11O1liO_dataout <= wire_nl101Oi0i_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0iOi_dataout; + wire_nl11O1lli_dataout <= wire_nl101Oi0l_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0iOl_dataout; + wire_nl11O1lll_dataout <= wire_nl101Oi0O_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0iOO_dataout; + wire_nl11O1llO_dataout <= wire_nl101Oiii_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0l1i_dataout; + wire_nl11O1lOi_dataout <= wire_nl101Oiil_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0l1l_dataout; + wire_nl11O1lOl_dataout <= wire_nl101OiiO_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0l1O_dataout; + wire_nl11O1lOO_dataout <= wire_nl101Oili_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0l0i_dataout; + wire_nl11O1O0i_dataout <= wire_nl101OiOl_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0lil_dataout; + wire_nl11O1O0l_dataout <= wire_nl101OiOO_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0liO_dataout; + wire_nl11O1O0O_dataout <= wire_nl101Ol1i_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0lli_dataout; + wire_nl11O1O1i_dataout <= wire_nl101Oill_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0l0l_dataout; + wire_nl11O1O1l_dataout <= wire_nl101OilO_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0l0O_dataout; + wire_nl11O1O1O_dataout <= wire_nl101OiOi_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0lii_dataout; + wire_nl11O1Oi_dataout <= wire_nl11O1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11O1Oii_dataout <= wire_nl101Ol1l_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0lll_dataout; + wire_nl11O1Oil_dataout <= wire_nl101Ol1O_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0llO_dataout; + wire_nl11O1OiO_dataout <= wire_nl101Ol0i_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0lOi_dataout; + wire_nl11O1Ol_dataout <= wire_niOOO0O_w_lg_nl11O01i8286w(0) WHEN (nl11O0il XOR nl11O00O) = '1' ELSE nl11O01i; + wire_nl11O1Oli_dataout <= wire_nl101Ol0l_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0lOl_dataout; + wire_nl11O1Oll_dataout <= wire_nl101Ol0O_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0lOO_dataout; + wire_nl11O1OlO_dataout <= wire_nl101Olii_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0O1i_dataout; + wire_nl11O1OOi_dataout <= wire_nl101Olil_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0O1l_dataout; + wire_nl11O1OOl_dataout <= wire_nl101OliO_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0O1O_dataout; + wire_nl11O1OOO_dataout <= wire_nl101Olli_dataout WHEN niOi100iO = '1' ELSE wire_nl11O0O0i_dataout; + wire_nl11Oi00i_dataout <= nl11l001O WHEN niOi10iiO = '1' ELSE nl11lOl0O; + wire_nl11Oi00l_dataout <= nl11l000i WHEN niOi10iiO = '1' ELSE nl11lOlii; + wire_nl11Oi00O_dataout <= nl11l000l WHEN niOi10iiO = '1' ELSE nl11lOlil; + wire_nl11Oi01i_dataout <= nl11l01OO WHEN niOi10iiO = '1' ELSE nl11lOl1O; + wire_nl11Oi01l_dataout <= nl11l001i WHEN niOi10iiO = '1' ELSE nl11lOl0i; + wire_nl11Oi01O_dataout <= nl11l001l WHEN niOi10iiO = '1' ELSE nl11lOl0l; + wire_nl11Oi0ii_dataout <= nl11l000O WHEN niOi10iiO = '1' ELSE nl11lOliO; + wire_nl11Oi0il_dataout <= nl11l00ii WHEN niOi10iiO = '1' ELSE nl11lOlli; + wire_nl11Oi0iO_dataout <= nl11l00il WHEN niOi10iiO = '1' ELSE nl11lOlll; + wire_nl11Oi0li_dataout <= nl11l00iO WHEN niOi10iiO = '1' ELSE nl11lOllO; + wire_nl11Oi0ll_dataout <= nl11l00li WHEN niOi10iiO = '1' ELSE nl11lOlOi; + wire_nl11Oi0lO_dataout <= nl11l00ll WHEN niOi10iiO = '1' ELSE nl11lOlOl; + wire_nl11Oi0O_dataout <= wire_nl11Oiii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl11Oi0Oi_dataout <= nl11l00lO WHEN niOi10iiO = '1' ELSE nl11lOlOO; + wire_nl11Oi0Ol_dataout <= nl11l00Oi WHEN niOi10iiO = '1' ELSE nl11lOO1i; + wire_nl11Oi0OO_dataout <= nl11l00Ol WHEN niOi10iiO = '1' ELSE nl11lOO1l; + wire_nl11Oi10i_dataout <= nl11l011O WHEN niOi10iiO = '1' ELSE nl11lOi0O; + wire_nl11Oi10l_dataout <= nl11l010i WHEN niOi10iiO = '1' ELSE nl11lOiii; + wire_nl11Oi10O_dataout <= nl11l010l WHEN niOi10iiO = '1' ELSE nl11lOiil; + wire_nl11Oi11i_dataout <= nl11l1OOO WHEN niOi10iiO = '1' ELSE nl11lOi1O; + wire_nl11Oi11l_dataout <= nl11l011i WHEN niOi10iiO = '1' ELSE nl11lOi0i; + wire_nl11Oi11O_dataout <= nl11l011l WHEN niOi10iiO = '1' ELSE nl11lOi0l; + wire_nl11Oi1ii_dataout <= nl11l010O WHEN niOi10iiO = '1' ELSE nl11lOiiO; + wire_nl11Oi1il_dataout <= nl11l01ii WHEN niOi10iiO = '1' ELSE nl11lOili; + wire_nl11Oi1iO_dataout <= nl11l01il WHEN niOi10iiO = '1' ELSE nl11lOill; + wire_nl11Oi1li_dataout <= nl11l01iO WHEN niOi10iiO = '1' ELSE nl11lOilO; + wire_nl11Oi1ll_dataout <= nl11l01li WHEN niOi10iiO = '1' ELSE nl11lOiOi; + wire_nl11Oi1lO_dataout <= nl11l01ll WHEN niOi10iiO = '1' ELSE nl11lOiOl; + wire_nl11Oi1O_dataout <= nl11O0lO WHEN niOO1iOil = '1' ELSE nl0i1lOOO; + wire_nl11Oi1Oi_dataout <= nl11l01lO WHEN niOi10iiO = '1' ELSE nl11lOiOO; + wire_nl11Oi1Ol_dataout <= nl11l01Oi WHEN niOi10iiO = '1' ELSE nl11lOl1i; + wire_nl11Oi1OO_dataout <= nl11l01Ol WHEN niOi10iiO = '1' ELSE nl11lOl1l; + wire_nl11Oii1i_dataout <= nl11l00OO WHEN niOi10iiO = '1' ELSE nl11lOO1O; + wire_nl11Oiii_dataout <= wire_niOOO0O_w_lg_nl11OiiO8279w(0) WHEN (nl11Ol1i XOR nl11OiOl) = '1' ELSE nl11OiiO; + wire_nl11Oiiii_dataout <= wire_nl11Oil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Oiiil_dataout <= wire_nl11Oiili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11OiiiO_dataout <= wire_nl11Oiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Oiili_dataout <= wire_nl11OiilO_dataout AND NOT(niOi10iOl); + wire_nl11Oiill_dataout <= wire_nl11OiiOi_dataout AND NOT(niOi10iOl); + wire_nl11OiilO_dataout <= wire_nl11Oil1O_o(1) WHEN niOi100lO = '1' ELSE wire_nl11OiiOl_dataout; + wire_nl11OiiOi_dataout <= wire_nl11Oil1O_o(2) WHEN niOi100lO = '1' ELSE wire_nl11OiiOO_dataout; + wire_nl11OiiOl_dataout <= wire_nl11Oil1i_o(0) WHEN niOi100ll = '1' ELSE nl11Oii0i; + wire_nl11OiiOO_dataout <= wire_nl11Oil1i_o(1) WHEN niOi100ll = '1' ELSE nl11Oii0l; + wire_nl11Oil0l_dataout <= wire_nl11Oil0O_dataout AND NOT(niOi10iOl); + wire_nl11Oil0O_dataout <= niOi1i1Ol WHEN wire_nilOO01O_dataout = '1' ELSE nl11lOO0i; + wire_nl11Oilii_dataout <= nl11OiliO AND NOT((wire_w_lg_niOi1i1OO60237w(0) AND nl11OO00O)); + wire_nl11Oilii_w_lg_dataout59843w(0) <= NOT wire_nl11Oilii_dataout; + wire_nl11Oill_dataout <= nl11OiOl AND NOT(wire_niO01O0O_dataout); + wire_nl11OiOi_dataout <= nl11Oi0l AND NOT(wire_niO01O0O_dataout); + wire_nl11OiOO_dataout <= nl11Ol1l AND NOT(wire_niO01l0O_dataout); + wire_nl11Ol00i_dataout <= wire_nl11Oll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol00l_dataout <= wire_nl11Oll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol00O_dataout <= wire_nl11Oll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol01i_dataout <= wire_nl11OliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol01l_dataout <= wire_nl11Oll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol01O_dataout <= wire_nl11Oll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol0i_dataout <= nl11OilO AND NOT(wire_niO01l0O_dataout); + wire_nl11Ol0ii_dataout <= wire_nl11Oll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol0il_dataout <= wire_nl11Ollii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol0iO_dataout <= wire_nl11Ollil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol0li_dataout <= wire_nl11Ol0ll_dataout OR niOi100Oi; + wire_nl11Ol0ll_dataout <= nl11OiliO AND NOT((wire_nilOOO0i_w_lg_dataout47830w(0) OR wire_nilOO01O_w_lg_dataout60235w(0))); + wire_nl11Ol0O_dataout <= wire_nl11Olil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol10i_dataout <= niOi10l0O AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol10l_dataout <= wire_nl11Oli0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol10O_dataout <= wire_nl11Oli0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol11l_dataout <= niOi100Oi AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol11O_dataout <= wire_nl11Ol0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1ii_dataout <= wire_nl11Oli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1il_dataout <= wire_nl11Oliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1iO_dataout <= wire_nl11Oliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1li_dataout <= wire_nl11OliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1ll_dataout <= wire_nl11Olili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1lO_dataout <= wire_nl11Olill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1O_dataout <= nl11Ol1i AND NOT(wire_niO01l0O_dataout); + wire_nl11Ol1Oi_dataout <= wire_nl11OlilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1Ol_dataout <= wire_nl11OliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Ol1OO_dataout <= wire_nl11OliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Oli0i_dataout <= wire_nl11OlliO_dataout WHEN niOi10l0O = '1' ELSE nl11Oilll; + wire_nl11Oli0l_dataout <= wire_nl11Ollli_dataout WHEN niOi10l0O = '1' ELSE nl11OillO; + wire_nl11Oli0O_dataout <= wire_nl11Ollll_dataout WHEN niOi10l0O = '1' ELSE nl11OilOi; + wire_nl11Olii_dataout <= wire_nl11Olll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11Oliii_dataout <= wire_nl11OlllO_dataout WHEN niOi10l0O = '1' ELSE nl11OilOl; + wire_nl11Oliil_dataout <= wire_nl11OllOi_dataout WHEN niOi10l0O = '1' ELSE nl11OilOO; + wire_nl11OliiO_dataout <= wire_nl11OllOl_dataout WHEN niOi10l0O = '1' ELSE nl11OiO1i; + wire_nl11Olil_dataout <= wire_nl1000i_w_lg_nl11Ol1l8275w(0) WHEN (wire_w_lg_niOO1iOiO8276w(0) AND (wire_nlOi0O01l_dataout XOR nl11Ol0l)) = '1' ELSE nl11Ol1l; + wire_nl11Olili_dataout <= wire_nl11OllOO_dataout WHEN niOi10l0O = '1' ELSE nl11OiO1l; + wire_nl11Olill_dataout <= wire_nl11OlO1i_dataout WHEN niOi10l0O = '1' ELSE nl11OiO1O; + wire_nl11OlilO_dataout <= wire_nl11OlO1l_dataout WHEN niOi10l0O = '1' ELSE nl11OiO0i; + wire_nl11OliOi_dataout <= wire_nl11OlO1O_dataout WHEN niOi10l0O = '1' ELSE nl11OiO0l; + wire_nl11OliOl_dataout <= wire_nl11OlO0i_dataout WHEN niOi10l0O = '1' ELSE nl11OiO0O; + wire_nl11OliOO_dataout <= wire_nl11OlO0l_dataout WHEN niOi10l0O = '1' ELSE nl11OiOii; + wire_nl11Oll0i_dataout <= wire_nl11OlOiO_dataout WHEN niOi10l0O = '1' ELSE nl11OiOll; + wire_nl11Oll0l_dataout <= wire_nl11OlOli_dataout WHEN niOi10l0O = '1' ELSE nl11OiOlO; + wire_nl11Oll0O_dataout <= wire_nl11OlOll_dataout WHEN niOi10l0O = '1' ELSE nl11OiOOi; + wire_nl11Oll1i_dataout <= wire_nl11OlO0O_dataout WHEN niOi10l0O = '1' ELSE nl11OiOil; + wire_nl11Oll1l_dataout <= wire_nl11OlOii_dataout WHEN niOi10l0O = '1' ELSE nl11OiOiO; + wire_nl11Oll1O_dataout <= wire_nl11OlOil_dataout WHEN niOi10l0O = '1' ELSE nl11OiOli; + wire_nl11Ollii_dataout <= wire_nl11OlOlO_dataout WHEN niOi10l0O = '1' ELSE nl11OiOOl; + wire_nl11Ollil_dataout <= wire_nl11OlOOi_dataout WHEN niOi10l0O = '1' ELSE nl11OiOOO; + wire_nl11OlliO_dataout <= nl0i00iii WHEN niOi1i10O = '1' ELSE wire_nl10iilli_dataout; + wire_nl11Olll_dataout <= nl11Ol0l WHEN niOO1iOiO = '1' ELSE wire_nlOi0O01l_dataout; + wire_nl11Ollli_dataout <= wire_nl10iilll_dataout AND NOT(niOi1i10O); + wire_nl11Ollll_dataout <= wire_nl10iillO_dataout AND NOT(niOi1i10O); + wire_nl11OlllO_dataout <= wire_nl10iilOi_dataout AND NOT(niOi1i10O); + wire_nl11OllOi_dataout <= wire_nl10iilOl_dataout AND NOT(niOi1i10O); + wire_nl11OllOl_dataout <= wire_nl10iilOO_dataout AND NOT(niOi1i10O); + wire_nl11OllOO_dataout <= wire_nl10iiO1i_dataout AND NOT(niOi1i10O); + wire_nl11OlO0i_dataout <= wire_nl10iiO0i_dataout AND NOT(niOi1i10O); + wire_nl11OlO0l_dataout <= wire_nl10iiO0l_dataout AND NOT(niOi1i10O); + wire_nl11OlO0O_dataout <= wire_nl10iiO0O_dataout AND NOT(niOi1i10O); + wire_nl11OlO1i_dataout <= wire_nl10iiO1l_dataout AND NOT(niOi1i10O); + wire_nl11OlO1l_dataout <= niOi10OOO AND NOT(niOi1i10O); + wire_nl11OlO1O_dataout <= nl0i00iii WHEN niOi1i10O = '1' ELSE wire_nl10iiO1O_dataout; + wire_nl11OlOii_dataout <= wire_nl10iiOii_dataout AND NOT(niOi1i10O); + wire_nl11OlOil_dataout <= wire_nl10iiOil_dataout AND NOT(niOi1i10O); + wire_nl11OlOiO_dataout <= wire_nl10iiOiO_dataout AND NOT(niOi1i10O); + wire_nl11OlOl_dataout <= (nl11OOil XOR nl11OO0O) AND NOT(wire_niO01l0O_dataout); + wire_nl11OlOli_dataout <= wire_nl10iiOli_dataout AND NOT(niOi1i10O); + wire_nl11OlOll_dataout <= (niOi100Ol AND nlOili1l) AND NOT(niOi1i10O); + wire_nl11OlOlO_dataout <= wire_nl11OlOOl_dataout WHEN niOi1i10O = '1' ELSE wire_nl10iil1O_dataout; + wire_nl11OlOOi_dataout <= niOi10i1i WHEN niOi1i10O = '1' ELSE niOi10OlO; + wire_nl11OlOOl_dataout <= (NOT ((niOi100OO AND nl0i00iii) OR wire_nlill0Oll_w_lg_w_lg_nl0i00i0l60222w60223w(0))) AND NOT(niOi10i1i); + wire_nl11OlOOl_w_lg_dataout61549w(0) <= NOT wire_nl11OlOOl_dataout; + wire_nl11OO0l_dataout <= nl11OlOi AND NOT(wire_niO01O0O_dataout); + wire_nl11OO1O_dataout <= nl11OO0O AND NOT(wire_niO01O0O_dataout); + wire_nl11OOii_dataout <= nl11OOiO AND NOT(wire_niO01l0O_dataout); + wire_nl11OOli_dataout <= nl11OOil AND NOT(wire_niO01l0O_dataout); + wire_nl11OOll_dataout <= nl11OO0i AND NOT(wire_niO01l0O_dataout); + wire_nl11OOOi_dataout <= wire_nl11OOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOil_dataout <= wire_nl101i1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOiO_dataout <= wire_nl101i1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOl_dataout <= wire_nl10110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOli_dataout <= ((wire_nilOOO0i_w_lg_dataout60194w(0) AND (wire_nl101O0OO_o OR wire_nl101i0iO_o)) OR wire_nliliilll_dataout) AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOll_dataout <= wire_nl101i01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOlO_dataout <= wire_nl1011iOl_o OR wire_niO01O0O_dataout; + wire_nl11OOOO_dataout <= wire_nl1000i_w_lg_nl11OOiO8268w(0) WHEN (nl0ilOiOi AND (wire_w_lg_niOO1iOli8269w(0) AND (nl0ilOiOi XOR nl11OOlO))) = '1' ELSE nl11OOiO; + wire_nl11OOOOi_dataout <= wire_nl1011ilO_o AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOOl_dataout <= wire_nl1011iOO_o AND NOT(wire_niO01O0O_dataout); + wire_nl11OOOOO_dataout <= wire_nl1011l1l_o AND NOT(wire_niO01O0O_dataout); + wire_nl1i0000i_dataout <= wire_nl1i00iiO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Ol1l; + wire_nl1i0000l_dataout <= wire_nl1i00ili_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Ol1O; + wire_nl1i0000O_dataout <= wire_nl1i00ill_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Ol0i; + wire_nl1i0001i_dataout <= wire_nl1i00i0O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1OiOl; + wire_nl1i0001l_dataout <= wire_nl1i00iii_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1OiOO; + wire_nl1i0001O_dataout <= wire_nl1i00iil_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Ol1i; + wire_nl1i000i_dataout <= wire_nl1i0iOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i000ii_dataout <= wire_nl1i00ilO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Ol0l; + wire_nl1i000il_dataout <= wire_nl1i00lll_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Ol0O; + wire_nl1i000iO_dataout <= wire_nl1i00llO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Olii; + wire_nl1i000l_dataout <= wire_nl1i0l1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i000li_dataout <= wire_nl1i00lOi_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Olil; + wire_nl1i000ll_dataout <= wire_nl1i00lOl_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1OliO; + wire_nl1i000lO_dataout <= wire_nl1i00lOO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Olli; + wire_nl1i000O_dataout <= wire_nl1i0l1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i000Oi_dataout <= wire_nl1i00O1i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Olll; + wire_nl1i000Ol_dataout <= wire_nl1i00O1l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1OllO; + wire_nl1i000OO_dataout <= wire_nl1i00O1O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1OlOi; + wire_nl1i0010i_dataout <= wire_nl1i0iO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i0010l_dataout <= wire_nl1i0iO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i0010O_dataout <= wire_nl1i0iO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i0011i_dataout <= wire_nl1i0ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i0011l_dataout <= wire_nl1i0ilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i0011O_dataout <= wire_nl1i0ilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i001i_dataout <= wire_nl1i0ill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i001ii_dataout <= wire_nl1i0iO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i001il_dataout <= wire_nl1i0iO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i001iO_dataout <= wire_nl1i0iO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i001l_dataout <= wire_nl1i0iOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i001li_dataout <= wire_nilOOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i001ll_dataout <= wire_nl1i00i1i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i10iOi; + wire_nl1i001lO_dataout <= wire_nl1i00i1l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Oili; + wire_nl1i001O_dataout <= wire_nl1i0iOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i001Oi_dataout <= wire_nl1i00i1O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1Oill; + wire_nl1i001Ol_dataout <= wire_nl1i00i0i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1OilO; + wire_nl1i001OO_dataout <= wire_nl1i00i0l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1OiOi; + wire_nl1i00i0i_dataout <= k_vc0(47) WHEN niOi1iO1l = '1' ELSE wire_nl1i00l1i_dataout; + wire_nl1i00i0l_dataout <= k_vc0(48) WHEN niOi1iO1l = '1' ELSE wire_nl1i00l1l_dataout; + wire_nl1i00i0O_dataout <= k_vc0(49) WHEN niOi1iO1l = '1' ELSE wire_nl1i00l1O_dataout; + wire_nl1i00i1i_dataout <= k_vc0(44) WHEN niOi1iO1l = '1' ELSE wire_nl1i00iOi_dataout; + wire_nl1i00i1l_dataout <= k_vc0(45) WHEN niOi1iO1l = '1' ELSE wire_nl1i00iOl_dataout; + wire_nl1i00i1O_dataout <= k_vc0(46) WHEN niOi1iO1l = '1' ELSE wire_nl1i00iOO_dataout; + wire_nl1i00ii_dataout <= wire_nl1i0l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00iii_dataout <= k_vc0(50) WHEN niOi1iO1l = '1' ELSE wire_nl1i00l0i_dataout; + wire_nl1i00iil_dataout <= k_vc0(51) WHEN niOi1iO1l = '1' ELSE wire_nl1i00l0l_dataout; + wire_nl1i00iiO_dataout <= k_vc0(52) WHEN niOi1iO1l = '1' ELSE wire_nl1i00l0O_dataout; + wire_nl1i00il_dataout <= wire_nl1i0l0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00ili_dataout <= k_vc0(53) WHEN niOi1iO1l = '1' ELSE wire_nl1i00lii_dataout; + wire_nl1i00ill_dataout <= k_vc0(54) WHEN niOi1iO1l = '1' ELSE wire_nl1i00lil_dataout; + wire_nl1i00ilO_dataout <= k_vc0(55) WHEN niOi1iO1l = '1' ELSE wire_nl1i00liO_dataout; + wire_nl1i00iO_dataout <= wire_nl1i0l0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00iOi_dataout <= wire_nl1i00lli_o(0) WHEN niOi1ilOi = '1' ELSE nl1i10iOi; + wire_nl1i00iOl_dataout <= wire_nl1i00lli_o(1) WHEN niOi1ilOi = '1' ELSE nl1i1Oili; + wire_nl1i00iOO_dataout <= wire_nl1i00lli_o(2) WHEN niOi1ilOi = '1' ELSE nl1i1Oill; + wire_nl1i00l0i_dataout <= wire_nl1i00lli_o(6) WHEN niOi1ilOi = '1' ELSE nl1i1OiOO; + wire_nl1i00l0l_dataout <= wire_nl1i00lli_o(7) WHEN niOi1ilOi = '1' ELSE nl1i1Ol1i; + wire_nl1i00l0O_dataout <= wire_nl1i00lli_o(8) WHEN niOi1ilOi = '1' ELSE nl1i1Ol1l; + wire_nl1i00l1i_dataout <= wire_nl1i00lli_o(3) WHEN niOi1ilOi = '1' ELSE nl1i1OilO; + wire_nl1i00l1l_dataout <= wire_nl1i00lli_o(4) WHEN niOi1ilOi = '1' ELSE nl1i1OiOi; + wire_nl1i00l1O_dataout <= wire_nl1i00lli_o(5) WHEN niOi1ilOi = '1' ELSE nl1i1OiOl; + wire_nl1i00li_dataout <= wire_nl1i0l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00lii_dataout <= wire_nl1i00lli_o(9) WHEN niOi1ilOi = '1' ELSE nl1i1Ol1O; + wire_nl1i00lil_dataout <= wire_nl1i00lli_o(10) WHEN niOi1ilOi = '1' ELSE nl1i1Ol0i; + wire_nl1i00liO_dataout <= wire_nl1i00lli_o(11) WHEN niOi1ilOi = '1' ELSE nl1i1Ol0l; + wire_nl1i00ll_dataout <= wire_nl1i0lii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00lll_dataout <= k_vc0(36) WHEN niOi1iO1l = '1' ELSE wire_nl1i00O0i_dataout; + wire_nl1i00llO_dataout <= k_vc0(37) WHEN niOi1iO1l = '1' ELSE wire_nl1i00O0l_dataout; + wire_nl1i00lO_dataout <= wire_nl1i0lil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00lOi_dataout <= k_vc0(38) WHEN niOi1iO1l = '1' ELSE wire_nl1i00O0O_dataout; + wire_nl1i00lOl_dataout <= k_vc0(39) WHEN niOi1iO1l = '1' ELSE wire_nl1i00Oii_dataout; + wire_nl1i00lOO_dataout <= k_vc0(40) WHEN niOi1iO1l = '1' ELSE wire_nl1i00Oil_dataout; + wire_nl1i00O0i_dataout <= wire_nl1i00OlO_o(0) WHEN niOi1ilOi = '1' ELSE nl1i1Ol0O; + wire_nl1i00O0l_dataout <= wire_nl1i00OlO_o(1) WHEN niOi1ilOi = '1' ELSE nl1i1Olii; + wire_nl1i00O0O_dataout <= wire_nl1i00OlO_o(2) WHEN niOi1ilOi = '1' ELSE nl1i1Olil; + wire_nl1i00O1i_dataout <= k_vc0(41) WHEN niOi1iO1l = '1' ELSE wire_nl1i00OiO_dataout; + wire_nl1i00O1l_dataout <= k_vc0(42) WHEN niOi1iO1l = '1' ELSE wire_nl1i00Oli_dataout; + wire_nl1i00O1O_dataout <= k_vc0(43) WHEN niOi1iO1l = '1' ELSE wire_nl1i00Oll_dataout; + wire_nl1i00Oi_dataout <= wire_nl1i0liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00Oii_dataout <= wire_nl1i00OlO_o(3) WHEN niOi1ilOi = '1' ELSE nl1i1OliO; + wire_nl1i00Oil_dataout <= wire_nl1i00OlO_o(4) WHEN niOi1ilOi = '1' ELSE nl1i1Olli; + wire_nl1i00OiO_dataout <= wire_nl1i00OlO_o(5) WHEN niOi1ilOi = '1' ELSE nl1i1Olll; + wire_nl1i00Ol_dataout <= wire_nl1i0lli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00Oli_dataout <= wire_nl1i00OlO_o(6) WHEN niOi1ilOi = '1' ELSE nl1i1OllO; + wire_nl1i00Oll_dataout <= wire_nl1i00OlO_o(7) WHEN niOi1ilOi = '1' ELSE nl1i1OlOi; + wire_nl1i00OO_dataout <= wire_nl1i0lll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i00OOl_dataout <= wire_nl1i0i1ll_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OlOl; + wire_nl1i00OOO_dataout <= wire_nl1i0i1lO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OlOO; + wire_nl1i010li_dataout <= wire_nl1i001ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i010ll_dataout <= wire_nl1i001lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i010lO_dataout <= wire_nl1i001Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i010Oi_dataout <= wire_nl1i001Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i010Ol_dataout <= wire_nl1i001OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i010OO_dataout <= wire_nl1i0001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01i0i_dataout <= wire_nl1i0000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01i0l_dataout <= wire_nl1i0000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01i0O_dataout <= wire_nl1i000ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01i1i_dataout <= wire_nl1i0001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01i1l_dataout <= wire_nl1i0001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01i1O_dataout <= wire_nl1i0000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01iii_dataout <= wire_nl1i000il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01iil_dataout <= wire_nl1i000iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01iiO_dataout <= wire_nl1i000li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01ili_dataout <= wire_nl1i000ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01ill_dataout <= wire_nl1i000lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01ilO_dataout <= wire_nl1i000Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01iOi_dataout <= wire_nl1i000Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01iOl_dataout <= wire_nl1i000OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01iOO_dataout <= wire_nl1i00OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01l0i_dataout <= wire_nl1i0i11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01l0l_dataout <= wire_nl1i0i10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01l0O_dataout <= wire_nl1i0i10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01l1i_dataout <= wire_nl1i00OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01l1l_dataout <= wire_nl1i0i11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01l1O_dataout <= wire_nl1i0i11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01lii_dataout <= wire_nl1i0i10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01lil_dataout <= wire_nl1i0i1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01liO_dataout <= wire_nl1i0i1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01lli_dataout <= wire_nl1i0i1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01lll_dataout <= wire_nl1i0i1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01llO_dataout <= wire_nl1i0iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01lOi_dataout <= wire_nl1i0iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01lOl_dataout <= wire_nl1i0iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01lOO_dataout <= wire_nl1i0iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01O0i_dataout <= wire_nl1i0iiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01O0l_dataout <= wire_nl1i0l1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01O0O_dataout <= wire_nl1i0l1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01O1i_dataout <= wire_nl1i0iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01O1l_dataout <= wire_nl1i0iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01O1O_dataout <= wire_nl1i0iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01Oii_dataout <= wire_nl1i0l1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01Oil_dataout <= wire_nl1i0l1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01OiO_dataout <= wire_nl1i0l1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01Oli_dataout <= wire_nl1i0l1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01Oll_dataout <= wire_nl1i0l1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01OlO_dataout <= wire_nl1i0l1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01OOi_dataout <= wire_nl1i0illi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01OOl_dataout <= wire_nl1i0illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i01OOO_dataout <= wire_nl1i0illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i0i00i_dataout <= wire_nl1i0ii1i_dataout AND NOT(niOi1iO1l); + wire_nl1i0i00l_dataout <= wire_nl1i0ii1l_dataout AND NOT(niOi1iO1l); + wire_nl1i0i00O_dataout <= wire_nl1i0ii1O_dataout AND NOT(niOi1iO1l); + wire_nl1i0i01i_dataout <= k_vc0(33) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0Oi_dataout; + wire_nl1i0i01l_dataout <= k_vc0(34) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0Ol_dataout; + wire_nl1i0i01O_dataout <= k_vc0(35) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0OO_dataout; + wire_nl1i0i0i_dataout <= wire_nl1i0lOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0i0ii_dataout <= wire_nl1i0ii0i_dataout AND NOT(niOi1iO1l); + wire_nl1i0i0il_dataout <= wire_nl1i0ii0l_o(0) WHEN niOi1ilOO = '1' ELSE nl1i1OlOl; + wire_nl1i0i0iO_dataout <= wire_nl1i0ii0l_o(1) WHEN niOi1ilOO = '1' ELSE nl1i1OlOO; + wire_nl1i0i0l_dataout <= wire_nl1i0O1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0i0li_dataout <= wire_nl1i0ii0l_o(2) WHEN niOi1ilOO = '1' ELSE nl1i1OO1i; + wire_nl1i0i0ll_dataout <= wire_nl1i0ii0l_o(3) WHEN niOi1ilOO = '1' ELSE nl1i1OO1l; + wire_nl1i0i0lO_dataout <= wire_nl1i0ii0l_o(4) WHEN niOi1ilOO = '1' ELSE nl1i1OO1O; + wire_nl1i0i0O_dataout <= wire_nl1i0O1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0i0Oi_dataout <= wire_nl1i0ii0l_o(5) WHEN niOi1ilOO = '1' ELSE nl1i1OO0i; + wire_nl1i0i0Ol_dataout <= wire_nl1i0ii0l_o(6) WHEN niOi1ilOO = '1' ELSE nl1i1OO0l; + wire_nl1i0i0OO_dataout <= wire_nl1i0ii0l_o(7) WHEN niOi1ilOO = '1' ELSE nl1i1OO0O; + wire_nl1i0i10i_dataout <= wire_nl1i0i01i_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OO0i; + wire_nl1i0i10l_dataout <= wire_nl1i0i01l_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OO0l; + wire_nl1i0i10O_dataout <= wire_nl1i0i01O_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OO0O; + wire_nl1i0i11i_dataout <= wire_nl1i0i1Oi_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OO1i; + wire_nl1i0i11l_dataout <= wire_nl1i0i1Ol_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OO1l; + wire_nl1i0i11O_dataout <= wire_nl1i0i1OO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OO1O; + wire_nl1i0i1i_dataout <= wire_nl1i0llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0i1ii_dataout <= wire_nl1i0i00i_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OOii; + wire_nl1i0i1il_dataout <= wire_nl1i0i00l_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OOil; + wire_nl1i0i1iO_dataout <= wire_nl1i0i00O_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OOiO; + wire_nl1i0i1l_dataout <= wire_nl1i0lOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0i1li_dataout <= wire_nl1i0i0ii_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1OOli; + wire_nl1i0i1ll_dataout <= k_vc0(28) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0il_dataout; + wire_nl1i0i1lO_dataout <= k_vc0(29) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0iO_dataout; + wire_nl1i0i1O_dataout <= wire_nl1i0lOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0i1Oi_dataout <= k_vc0(30) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0li_dataout; + wire_nl1i0i1Ol_dataout <= k_vc0(31) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0ll_dataout; + wire_nl1i0i1OO_dataout <= k_vc0(32) WHEN niOi1iO1l = '1' ELSE wire_nl1i0i0lO_dataout; + wire_nl1i0ii0i_dataout <= wire_nl1i0ii0l_o(11) WHEN niOi1ilOO = '1' ELSE nl1i1OOli; + wire_nl1i0ii1i_dataout <= wire_nl1i0ii0l_o(8) WHEN niOi1ilOO = '1' ELSE nl1i1OOii; + wire_nl1i0ii1l_dataout <= wire_nl1i0ii0l_o(9) WHEN niOi1ilOO = '1' ELSE nl1i1OOil; + wire_nl1i0ii1O_dataout <= wire_nl1i0ii0l_o(10) WHEN niOi1ilOO = '1' ELSE nl1i1OOiO; + wire_nl1i0iii_dataout <= wire_nl1i0O1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0iiii_dataout <= k_vc0(20) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iiOO_dataout; + wire_nl1i0iiil_dataout <= k_vc0(21) WHEN niOi1iO1l = '1' ELSE wire_nl1i0il1i_dataout; + wire_nl1i0iiiO_dataout <= k_vc0(22) WHEN niOi1iO1l = '1' ELSE wire_nl1i0il1l_dataout; + wire_nl1i0iil_dataout <= wire_nl1i0O0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0iili_dataout <= k_vc0(23) WHEN niOi1iO1l = '1' ELSE wire_nl1i0il1O_dataout; + wire_nl1i0iill_dataout <= k_vc0(24) WHEN niOi1iO1l = '1' ELSE wire_nl1i0il0i_dataout; + wire_nl1i0iilO_dataout <= k_vc0(25) WHEN niOi1iO1l = '1' ELSE wire_nl1i0il0l_dataout; + wire_nl1i0iiO_dataout <= wire_nl1i0O0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0iiOi_dataout <= k_vc0(26) WHEN niOi1iO1l = '1' ELSE wire_nl1i0il0O_dataout; + wire_nl1i0iiOl_dataout <= k_vc0(27) WHEN niOi1iO1l = '1' ELSE wire_nl1i0ilii_dataout; + wire_nl1i0iiOO_dataout <= wire_nl1i0ilil_o(0) WHEN niOi1iO1i = '1' ELSE nl1i1OOll; + wire_nl1i0il0i_dataout <= wire_nl1i0ilil_o(4) WHEN niOi1iO1i = '1' ELSE nl1i1OOOO; + wire_nl1i0il0l_dataout <= wire_nl1i0ilil_o(5) WHEN niOi1iO1i = '1' ELSE nl1i0111i; + wire_nl1i0il0O_dataout <= wire_nl1i0ilil_o(6) WHEN niOi1iO1i = '1' ELSE nl1i0111l; + wire_nl1i0il1i_dataout <= wire_nl1i0ilil_o(1) WHEN niOi1iO1i = '1' ELSE nl1i1OOlO; + wire_nl1i0il1l_dataout <= wire_nl1i0ilil_o(2) WHEN niOi1iO1i = '1' ELSE nl1i1OOOi; + wire_nl1i0il1O_dataout <= wire_nl1i0ilil_o(3) WHEN niOi1iO1i = '1' ELSE nl1i1OOOl; + wire_nl1i0ili_dataout <= wire_nl1i0O0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1i0ilii_dataout <= wire_nl1i0ilil_o(7) WHEN niOi1iO1i = '1' ELSE nl1i0111O; + wire_nl1i0ill_dataout <= wire_niOOO0O_w_lg_nl1i1O0i8059w(0) WHEN (wire_w_lg_niOO1l1lO8035w(0) AND wire_w_lg_niOO1l1ll8060w(0)) = '1' ELSE nl1i1O0i; + wire_nl1i0illi_dataout <= k_vc0(8) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOii_dataout; + wire_nl1i0illl_dataout <= k_vc0(9) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOil_dataout; + wire_nl1i0illO_dataout <= k_vc0(10) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOiO_dataout; + wire_nl1i0ilOi_dataout <= k_vc0(11) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOli_dataout; + wire_nl1i0ilOl_dataout <= k_vc0(12) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOll_dataout; + wire_nl1i0ilOO_dataout <= k_vc0(13) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOlO_dataout; + wire_nl1i0iO0i_dataout <= k_vc0(17) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l11i_dataout; + wire_nl1i0iO0l_dataout <= k_vc0(18) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l11l_dataout; + wire_nl1i0iO0O_dataout <= k_vc0(19) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l11O_dataout; + wire_nl1i0iO1i_dataout <= k_vc0(14) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOOi_dataout; + wire_nl1i0iO1l_dataout <= k_vc0(15) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOOl_dataout; + wire_nl1i0iO1O_dataout <= k_vc0(16) WHEN niOi1iO1l = '1' ELSE wire_nl1i0iOOO_dataout; + wire_nl1i0iOi_dataout <= dl_vcid_map(0) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1Oii; + wire_nl1i0iOii_dataout <= wire_nl1i0l10i_o(0) WHEN niOi1iO1O = '1' ELSE nl1i011lO; + wire_nl1i0iOil_dataout <= wire_nl1i0l10i_o(1) WHEN niOi1iO1O = '1' ELSE nl1i011Oi; + wire_nl1i0iOiO_dataout <= wire_nl1i0l10i_o(2) WHEN niOi1iO1O = '1' ELSE nl1i011Ol; + wire_nl1i0iOl_dataout <= dl_vcid_map(1) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1Oil; + wire_nl1i0iOli_dataout <= wire_nl1i0l10i_o(3) WHEN niOi1iO1O = '1' ELSE nl1i011OO; + wire_nl1i0iOll_dataout <= wire_nl1i0l10i_o(4) WHEN niOi1iO1O = '1' ELSE nl1i0101i; + wire_nl1i0iOlO_dataout <= wire_nl1i0l10i_o(5) WHEN niOi1iO1O = '1' ELSE nl1i0101l; + wire_nl1i0iOO_dataout <= dl_vcid_map(2) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1OiO; + wire_nl1i0iOOi_dataout <= wire_nl1i0l10i_o(6) WHEN niOi1iO1O = '1' ELSE nl1i0101O; + wire_nl1i0iOOl_dataout <= wire_nl1i0l10i_o(7) WHEN niOi1iO1O = '1' ELSE nl1i0100i; + wire_nl1i0iOOO_dataout <= wire_nl1i0l10i_o(8) WHEN niOi1iO1O = '1' ELSE nl1i0100l; + wire_nl1i0l00i_dataout <= wire_nl1i0l0il_o(4) WHEN niOi1iO1O = '1' ELSE nl1i011il; + wire_nl1i0l00l_dataout <= wire_nl1i0l0il_o(5) WHEN niOi1iO1O = '1' ELSE nl1i011iO; + wire_nl1i0l00O_dataout <= wire_nl1i0l0il_o(6) WHEN niOi1iO1O = '1' ELSE nl1i011li; + wire_nl1i0l01i_dataout <= wire_nl1i0l0il_o(1) WHEN niOi1iO1O = '1' ELSE nl1i0110l; + wire_nl1i0l01l_dataout <= wire_nl1i0l0il_o(2) WHEN niOi1iO1O = '1' ELSE nl1i0110O; + wire_nl1i0l01O_dataout <= wire_nl1i0l0il_o(3) WHEN niOi1iO1O = '1' ELSE nl1i011ii; + wire_nl1i0l0i_dataout <= dl_vcid_map(6) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1OOi; + wire_nl1i0l0ii_dataout <= wire_nl1i0l0il_o(7) WHEN niOi1iO1O = '1' ELSE nl1i011ll; + wire_nl1i0l0iO_dataout <= wire_nl1i0ll0O_o(0) WHEN niOi1iO0O = '1' ELSE wire_nl1i0li0O_dataout; + wire_nl1i0l0l_dataout <= dl_vcid_map(7) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1OOl; + wire_nl1i0l0li_dataout <= wire_nl1i0ll0O_o(1) WHEN niOi1iO0O = '1' ELSE wire_nl1i0liii_dataout; + wire_nl1i0l0ll_dataout <= wire_nl1i0ll0O_o(2) WHEN niOi1iO0O = '1' ELSE wire_nl1i0liil_dataout; + wire_nl1i0l0lO_dataout <= wire_nl1i0ll0O_o(3) WHEN niOi1iO0O = '1' ELSE wire_nl1i0liiO_dataout; + wire_nl1i0l0O_dataout <= dl_vcid_map(8) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1OOO; + wire_nl1i0l0Oi_dataout <= wire_nl1i0ll0O_o(4) WHEN niOi1iO0O = '1' ELSE wire_nl1i0lili_dataout; + wire_nl1i0l0Ol_dataout <= wire_nl1i0ll0O_o(5) WHEN niOi1iO0O = '1' ELSE wire_nl1i0lill_dataout; + wire_nl1i0l0OO_dataout <= wire_nl1i0ll0O_o(6) WHEN niOi1iO0O = '1' ELSE wire_nl1i0lilO_dataout; + wire_nl1i0l11i_dataout <= wire_nl1i0l10i_o(9) WHEN niOi1iO1O = '1' ELSE nl1i0100O; + wire_nl1i0l11l_dataout <= wire_nl1i0l10i_o(10) WHEN niOi1iO1O = '1' ELSE nl1i010ii; + wire_nl1i0l11O_dataout <= wire_nl1i0l10i_o(11) WHEN niOi1iO1O = '1' ELSE nl1i010il; + wire_nl1i0l1i_dataout <= dl_vcid_map(3) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1Oli; + wire_nl1i0l1ii_dataout <= k_vc0(0) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l1OO_dataout; + wire_nl1i0l1il_dataout <= k_vc0(1) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l01i_dataout; + wire_nl1i0l1iO_dataout <= k_vc0(2) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l01l_dataout; + wire_nl1i0l1l_dataout <= dl_vcid_map(4) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1Oll; + wire_nl1i0l1li_dataout <= k_vc0(3) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l01O_dataout; + wire_nl1i0l1ll_dataout <= k_vc0(4) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l00i_dataout; + wire_nl1i0l1lO_dataout <= k_vc0(5) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l00l_dataout; + wire_nl1i0l1O_dataout <= dl_vcid_map(5) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i1OlO; + wire_nl1i0l1Oi_dataout <= k_vc0(6) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l00O_dataout; + wire_nl1i0l1Ol_dataout <= k_vc0(7) WHEN niOi1iO1l = '1' ELSE wire_nl1i0l0ii_dataout; + wire_nl1i0l1OO_dataout <= wire_nl1i0l0il_o(0) WHEN niOi1iO1O = '1' ELSE nl1i0110i; + wire_nl1i0li0i_dataout <= wire_nl1i0ll0O_o(10) WHEN niOi1iO0O = '1' ELSE wire_nl1i0ll1i_dataout; + wire_nl1i0li0l_dataout <= wire_nl1i0ll0O_o(11) WHEN niOi1iO0O = '1' ELSE wire_nl1i0ll1l_dataout; + wire_nl1i0li0O_dataout <= wire_nl1i0ll1O_o(1) WHEN niOi1iO0i = '1' ELSE nl1i10iOi; + wire_nl1i0li1i_dataout <= wire_nl1i0ll0O_o(7) WHEN niOi1iO0O = '1' ELSE wire_nl1i0liOi_dataout; + wire_nl1i0li1l_dataout <= wire_nl1i0ll0O_o(8) WHEN niOi1iO0O = '1' ELSE wire_nl1i0liOl_dataout; + wire_nl1i0li1O_dataout <= wire_nl1i0ll0O_o(9) WHEN niOi1iO0O = '1' ELSE wire_nl1i0liOO_dataout; + wire_nl1i0lii_dataout <= dl_vcid_map(9) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i011i; + wire_nl1i0liii_dataout <= wire_nl1i0ll1O_o(2) WHEN niOi1iO0i = '1' ELSE nl1i1Oili; + wire_nl1i0liil_dataout <= wire_nl1i0ll1O_o(3) WHEN niOi1iO0i = '1' ELSE nl1i1Oill; + wire_nl1i0liiO_dataout <= wire_nl1i0ll1O_o(4) WHEN niOi1iO0i = '1' ELSE nl1i1OilO; + wire_nl1i0lil_dataout <= dl_vcid_map(10) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i011l; + wire_nl1i0lili_dataout <= wire_nl1i0ll1O_o(5) WHEN niOi1iO0i = '1' ELSE nl1i1OiOi; + wire_nl1i0lill_dataout <= wire_nl1i0ll1O_o(6) WHEN niOi1iO0i = '1' ELSE nl1i1OiOl; + wire_nl1i0lilO_dataout <= wire_nl1i0ll1O_o(7) WHEN niOi1iO0i = '1' ELSE nl1i1OiOO; + wire_nl1i0liO_dataout <= dl_vcid_map(11) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i011O; + wire_nl1i0liOi_dataout <= wire_nl1i0ll1O_o(8) WHEN niOi1iO0i = '1' ELSE nl1i1Ol1i; + wire_nl1i0liOl_dataout <= wire_nl1i0ll1O_o(9) WHEN niOi1iO0i = '1' ELSE nl1i1Ol1l; + wire_nl1i0liOO_dataout <= wire_nl1i0ll1O_o(10) WHEN niOi1iO0i = '1' ELSE nl1i1Ol1O; + wire_nl1i0ll1i_dataout <= wire_nl1i0ll1O_o(11) WHEN niOi1iO0i = '1' ELSE nl1i1Ol0i; + wire_nl1i0ll1l_dataout <= wire_nl1i0ll1O_o(12) WHEN niOi1iO0i = '1' ELSE nl1i1Ol0l; + wire_nl1i0lli_dataout <= dl_vcid_map(12) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i010i; + wire_nl1i0lliO_dataout <= wire_nl1i0lOOi_o(0) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lO1l_dataout; + wire_nl1i0lll_dataout <= dl_vcid_map(13) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i010l; + wire_nl1i0llli_dataout <= wire_nl1i0lOOi_o(1) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lO1O_dataout; + wire_nl1i0llll_dataout <= wire_nl1i0lOOi_o(2) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lO0i_dataout; + wire_nl1i0lllO_dataout <= wire_nl1i0lOOi_o(3) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lO0l_dataout; + wire_nl1i0llO_dataout <= dl_vcid_map(14) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i010O; + wire_nl1i0llOi_dataout <= wire_nl1i0lOOi_o(4) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lO0O_dataout; + wire_nl1i0llOl_dataout <= wire_nl1i0lOOi_o(5) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lOii_dataout; + wire_nl1i0llOO_dataout <= wire_nl1i0lOOi_o(6) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lOil_dataout; + wire_nl1i0lO0i_dataout <= wire_nl1i0lOli_o(3) WHEN niOi1iOil = '1' ELSE nl1i1Olil; + wire_nl1i0lO0l_dataout <= wire_nl1i0lOli_o(4) WHEN niOi1iOil = '1' ELSE nl1i1OliO; + wire_nl1i0lO0O_dataout <= wire_nl1i0lOli_o(5) WHEN niOi1iOil = '1' ELSE nl1i1Olli; + wire_nl1i0lO1i_dataout <= wire_nl1i0lOOi_o(7) WHEN niOi1iOlO = '1' ELSE wire_nl1i0lOiO_dataout; + wire_nl1i0lO1l_dataout <= wire_nl1i0lOli_o(1) WHEN niOi1iOil = '1' ELSE nl1i1Ol0O; + wire_nl1i0lO1O_dataout <= wire_nl1i0lOli_o(2) WHEN niOi1iOil = '1' ELSE nl1i1Olii; + wire_nl1i0lOi_dataout <= dl_vcid_map(15) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01ii; + wire_nl1i0lOii_dataout <= wire_nl1i0lOli_o(6) WHEN niOi1iOil = '1' ELSE nl1i1Olll; + wire_nl1i0lOil_dataout <= wire_nl1i0lOli_o(7) WHEN niOi1iOil = '1' ELSE nl1i1OllO; + wire_nl1i0lOiO_dataout <= wire_nl1i0lOli_o(8) WHEN niOi1iOil = '1' ELSE nl1i1OlOi; + wire_nl1i0lOl_dataout <= dl_vcid_map(16) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01il; + wire_nl1i0lOO_dataout <= dl_vcid_map(17) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01iO; + wire_nl1i0O00i_dataout <= wire_nl1i0O0li_o(7) WHEN niOi1l11i = '1' ELSE nl1i1OO0l; + wire_nl1i0O00l_dataout <= wire_nl1i0O0li_o(8) WHEN niOi1l11i = '1' ELSE nl1i1OO0O; + wire_nl1i0O00O_dataout <= wire_nl1i0O0li_o(9) WHEN niOi1l11i = '1' ELSE nl1i1OOii; + wire_nl1i0O01i_dataout <= wire_nl1i0O0li_o(4) WHEN niOi1l11i = '1' ELSE nl1i1OO1l; + wire_nl1i0O01l_dataout <= wire_nl1i0O0li_o(5) WHEN niOi1l11i = '1' ELSE nl1i1OO1O; + wire_nl1i0O01O_dataout <= wire_nl1i0O0li_o(6) WHEN niOi1l11i = '1' ELSE nl1i1OO0i; + wire_nl1i0O0i_dataout <= dl_vcid_map(21) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01Oi; + wire_nl1i0O0ii_dataout <= wire_nl1i0O0li_o(10) WHEN niOi1l11i = '1' ELSE nl1i1OOil; + wire_nl1i0O0il_dataout <= wire_nl1i0O0li_o(11) WHEN niOi1l11i = '1' ELSE nl1i1OOiO; + wire_nl1i0O0iO_dataout <= wire_nl1i0O0li_o(12) WHEN niOi1l11i = '1' ELSE nl1i1OOli; + wire_nl1i0O0l_dataout <= dl_vcid_map(22) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01Ol; + wire_nl1i0O0O_dataout <= dl_vcid_map(23) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01OO; + wire_nl1i0O10i_dataout <= wire_nl1i0O0Oi_o(3) WHEN niOi1l11O = '1' ELSE wire_nl1i0O01i_dataout; + wire_nl1i0O10l_dataout <= wire_nl1i0O0Oi_o(4) WHEN niOi1l11O = '1' ELSE wire_nl1i0O01l_dataout; + wire_nl1i0O10O_dataout <= wire_nl1i0O0Oi_o(5) WHEN niOi1l11O = '1' ELSE wire_nl1i0O01O_dataout; + wire_nl1i0O11i_dataout <= wire_nl1i0O0Oi_o(0) WHEN niOi1l11O = '1' ELSE wire_nl1i0O1Oi_dataout; + wire_nl1i0O11l_dataout <= wire_nl1i0O0Oi_o(1) WHEN niOi1l11O = '1' ELSE wire_nl1i0O1Ol_dataout; + wire_nl1i0O11O_dataout <= wire_nl1i0O0Oi_o(2) WHEN niOi1l11O = '1' ELSE wire_nl1i0O1OO_dataout; + wire_nl1i0O1i_dataout <= dl_vcid_map(18) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01li; + wire_nl1i0O1ii_dataout <= wire_nl1i0O0Oi_o(6) WHEN niOi1l11O = '1' ELSE wire_nl1i0O00i_dataout; + wire_nl1i0O1il_dataout <= wire_nl1i0O0Oi_o(7) WHEN niOi1l11O = '1' ELSE wire_nl1i0O00l_dataout; + wire_nl1i0O1iO_dataout <= wire_nl1i0O0Oi_o(8) WHEN niOi1l11O = '1' ELSE wire_nl1i0O00O_dataout; + wire_nl1i0O1l_dataout <= dl_vcid_map(19) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01ll; + wire_nl1i0O1li_dataout <= wire_nl1i0O0Oi_o(9) WHEN niOi1l11O = '1' ELSE wire_nl1i0O0ii_dataout; + wire_nl1i0O1ll_dataout <= wire_nl1i0O0Oi_o(10) WHEN niOi1l11O = '1' ELSE wire_nl1i0O0il_dataout; + wire_nl1i0O1lO_dataout <= wire_nl1i0O0Oi_o(11) WHEN niOi1l11O = '1' ELSE wire_nl1i0O0iO_dataout; + wire_nl1i0O1O_dataout <= dl_vcid_map(20) WHEN wire_w_lg_niOO1l1lO8035w(0) = '1' ELSE nl1i01lO; + wire_nl1i0O1Oi_dataout <= wire_nl1i0O0li_o(1) WHEN niOi1l11i = '1' ELSE nl1i1OlOl; + wire_nl1i0O1Ol_dataout <= wire_nl1i0O0li_o(2) WHEN niOi1l11i = '1' ELSE nl1i1OlOO; + wire_nl1i0O1OO_dataout <= wire_nl1i0O0li_o(3) WHEN niOi1l11i = '1' ELSE nl1i1OO1i; + wire_nl1i0Oi0i_dataout <= wire_nl1i0Ol0l_o(3) WHEN niOi1l1iO = '1' ELSE wire_nl1i0OilO_dataout; + wire_nl1i0Oi0l_dataout <= wire_nl1i0Ol0l_o(4) WHEN niOi1l1iO = '1' ELSE wire_nl1i0OiOi_dataout; + wire_nl1i0Oi0O_dataout <= wire_nl1i0Ol0l_o(5) WHEN niOi1l1iO = '1' ELSE wire_nl1i0OiOl_dataout; + wire_nl1i0Oi1i_dataout <= wire_nl1i0Ol0l_o(0) WHEN niOi1l1iO = '1' ELSE wire_nl1i0OiiO_dataout; + wire_nl1i0Oi1l_dataout <= wire_nl1i0Ol0l_o(1) WHEN niOi1l1iO = '1' ELSE wire_nl1i0Oili_dataout; + wire_nl1i0Oi1O_dataout <= wire_nl1i0Ol0l_o(2) WHEN niOi1l1iO = '1' ELSE wire_nl1i0Oill_dataout; + wire_nl1i0Oiii_dataout <= wire_nl1i0Ol0l_o(6) WHEN niOi1l1iO = '1' ELSE wire_nl1i0OiOO_dataout; + wire_nl1i0Oiil_dataout <= wire_nl1i0Ol0l_o(7) WHEN niOi1l1iO = '1' ELSE wire_nl1i0Ol1i_dataout; + wire_nl1i0OiiO_dataout <= wire_nl1i0Ol1l_o(1) WHEN niOi1l10l = '1' ELSE nl1i1OOll; + wire_nl1i0Oili_dataout <= wire_nl1i0Ol1l_o(2) WHEN niOi1l10l = '1' ELSE nl1i1OOlO; + wire_nl1i0Oill_dataout <= wire_nl1i0Ol1l_o(3) WHEN niOi1l10l = '1' ELSE nl1i1OOOi; + wire_nl1i0OilO_dataout <= wire_nl1i0Ol1l_o(4) WHEN niOi1l10l = '1' ELSE nl1i1OOOl; + wire_nl1i0OiOi_dataout <= wire_nl1i0Ol1l_o(5) WHEN niOi1l10l = '1' ELSE nl1i1OOOO; + wire_nl1i0OiOl_dataout <= wire_nl1i0Ol1l_o(6) WHEN niOi1l10l = '1' ELSE nl1i0111i; + wire_nl1i0OiOO_dataout <= wire_nl1i0Ol1l_o(7) WHEN niOi1l10l = '1' ELSE nl1i0111l; + wire_nl1i0Ol1i_dataout <= wire_nl1i0Ol1l_o(8) WHEN niOi1l10l = '1' ELSE nl1i0111O; + wire_nl1i0Olil_dataout <= wire_nl1ii110l_o(0) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OO0l_dataout; + wire_nl1i0OliO_dataout <= wire_nl1ii110l_o(1) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OO0O_dataout; + wire_nl1i0Olli_dataout <= wire_nl1ii110l_o(2) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOii_dataout; + wire_nl1i0Olll_dataout <= wire_nl1ii110l_o(3) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOil_dataout; + wire_nl1i0OllO_dataout <= wire_nl1ii110l_o(4) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOiO_dataout; + wire_nl1i0OlOi_dataout <= wire_nl1ii110l_o(5) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOli_dataout; + wire_nl1i0OlOl_dataout <= wire_nl1ii110l_o(6) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOll_dataout; + wire_nl1i0OlOO_dataout <= wire_nl1ii110l_o(7) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOlO_dataout; + wire_nl1i0OO0i_dataout <= wire_nl1ii110l_o(11) WHEN niOi1l1OO = '1' ELSE wire_nl1ii111i_dataout; + wire_nl1i0OO0l_dataout <= wire_nl1ii111l_o(1) WHEN niOi1l1Oi = '1' ELSE nl1i011lO; + wire_nl1i0OO0O_dataout <= wire_nl1ii111l_o(2) WHEN niOi1l1Oi = '1' ELSE nl1i011Oi; + wire_nl1i0OO1i_dataout <= wire_nl1ii110l_o(8) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOOi_dataout; + wire_nl1i0OO1l_dataout <= wire_nl1ii110l_o(9) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOOl_dataout; + wire_nl1i0OO1O_dataout <= wire_nl1ii110l_o(10) WHEN niOi1l1OO = '1' ELSE wire_nl1i0OOOO_dataout; + wire_nl1i0OOii_dataout <= wire_nl1ii111l_o(3) WHEN niOi1l1Oi = '1' ELSE nl1i011Ol; + wire_nl1i0OOil_dataout <= wire_nl1ii111l_o(4) WHEN niOi1l1Oi = '1' ELSE nl1i011OO; + wire_nl1i0OOiO_dataout <= wire_nl1ii111l_o(5) WHEN niOi1l1Oi = '1' ELSE nl1i0101i; + wire_nl1i0OOli_dataout <= wire_nl1ii111l_o(6) WHEN niOi1l1Oi = '1' ELSE nl1i0101l; + wire_nl1i0OOll_dataout <= wire_nl1ii111l_o(7) WHEN niOi1l1Oi = '1' ELSE nl1i0101O; + wire_nl1i0OOlO_dataout <= wire_nl1ii111l_o(8) WHEN niOi1l1Oi = '1' ELSE nl1i0100i; + wire_nl1i0OOO_dataout <= wire_nl1ii11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i0OOOi_dataout <= wire_nl1ii111l_o(9) WHEN niOi1l1Oi = '1' ELSE nl1i0100l; + wire_nl1i0OOOl_dataout <= wire_nl1ii111l_o(10) WHEN niOi1l1Oi = '1' ELSE nl1i0100O; + wire_nl1i0OOOO_dataout <= wire_nl1ii111l_o(11) WHEN niOi1l1Oi = '1' ELSE nl1i010ii; + wire_nl1i100i_dataout <= wire_nl1i1ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i100l_dataout <= wire_nl1i1ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i100O_dataout <= wire_nl1i1ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i101i_dataout <= wire_nl1i1iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i101l_dataout <= wire_nl1i1iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i101O_dataout <= wire_nl1i1iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10ii_dataout <= wire_nl1i1iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10il_dataout <= wire_nl1i1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10iO_dataout <= wire_nl1i1iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10iOl_dataout <= wire_nl1i1i0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10iOO_dataout <= wire_nl1i1i0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10l0i_dataout <= wire_nl1i1ii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10l0l_dataout <= wire_nl1i1ii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10l0O_dataout <= wire_nl1i1ii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10l1i_dataout <= wire_nl1i1ii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10l1l_dataout <= wire_nl1i1ii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10l1O_dataout <= wire_nl1i1ii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10li_dataout <= wire_nl1i1l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lii_dataout <= wire_nl1i1iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lil_dataout <= wire_nl1i1iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10liO_dataout <= wire_nl1i1iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10ll_dataout <= wire_nl1i1l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lli_dataout <= wire_nl1i1iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lll_dataout <= wire_nl1i1iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10llO_dataout <= wire_nl1i1iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lO_dataout <= wire_nl1i1l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lOi_dataout <= wire_nl1i1iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lOl_dataout <= wire_nl1i1iiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10lOO_dataout <= wire_nl1i1iiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10O0i_dataout <= wire_nl1i1l01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10O0l_dataout <= wire_nl1i1l01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10O0O_dataout <= wire_nl1i1l00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10O1i_dataout <= wire_nl1i1il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10O1l_dataout <= wire_nl1i1il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10O1O_dataout <= wire_nl1i1il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10Oi_dataout <= wire_nl1i1l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10Oii_dataout <= wire_nl1i1l00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10Oil_dataout <= wire_nl1i1l00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10OiO_dataout <= wire_nl1i1l0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10Ol_dataout <= wire_nl1i1l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10Oli_dataout <= wire_nl1i1l0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10Oll_dataout <= wire_nl1i1l0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10OlO_dataout <= wire_nl1i1l0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10OO_dataout <= wire_nl1i1l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10OOi_dataout <= wire_nl1i1l0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10OOl_dataout <= wire_nl1i1l0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i10OOO_dataout <= wire_nl1i1l0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1100i_dataout <= ((wire_nl011OilO_dataout AND niOi1il1l) AND niOi1illi) AND NOT(wire_niO01O0O_dataout); + wire_nl1i1100l_dataout <= (niOi1illl AND wire_nl1i11iil_o) AND NOT(wire_niO01O0O_dataout); + wire_nl1i1100O_dataout <= ((wire_nl011OilO_dataout AND niOi1il1O) AND niOi1iliO) AND NOT(wire_niO01O0O_dataout); + wire_nl1i110ii_dataout <= (((wire_nl011OilO_dataout AND wire_w_lg_niOi1ilOl57737w(0)) AND wire_nl1i11i1O_o) AND niOi1iliO) AND NOT(wire_niO01O0O_dataout); + wire_nl1i110il_dataout <= ((niOi1il0l AND niOi1il0i) AND niOi1ilii) AND NOT(wire_niO01O0O_dataout); + wire_nl1i110iO_dataout <= ((niOi1il0l AND wire_nl1i110lO_o) AND niOi1ilii) AND NOT(wire_niO01O0O_dataout); + wire_nl1i1110i_dataout <= nl011li0l WHEN niOi1il1i = '1' ELSE nl10O0lil; + wire_nl1i1110l_dataout <= nl011li0O WHEN niOi1il1i = '1' ELSE nl10O0liO; + wire_nl1i1110O_dataout <= nl011liii WHEN niOi1il1i = '1' ELSE nl10O0lli; + wire_nl1i1111i_dataout <= nl011li1l WHEN niOi1il1i = '1' ELSE nl10O0Oli; + wire_nl1i1111l_dataout <= nl011li1O WHEN niOi1il1i = '1' ELSE nl10O0Oll; + wire_nl1i1111O_dataout <= nl011li0i WHEN niOi1il1i = '1' ELSE nl10O0OlO; + wire_nl1i111ii_dataout <= nl011liil WHEN niOi1il1i = '1' ELSE nl10O0lll; + wire_nl1i111il_dataout <= nl011liiO WHEN niOi1il1i = '1' ELSE nl10O0llO; + wire_nl1i111iO_dataout <= nl011lili WHEN niOi1il1i = '1' ELSE nl10O0lOi; + wire_nl1i111li_dataout <= nl011lill WHEN niOi1il1i = '1' ELSE nl10O0lOl; + wire_nl1i111ll_dataout <= nl011lilO WHEN niOi1il1i = '1' ELSE nl10O0lOO; + wire_nl1i11Ol_dataout <= wire_nl1i1i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i11OO_dataout <= wire_nl1i1i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i00i_dataout <= wire_nl1i1lOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i00l_dataout <= wire_nl1i1lOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i00O_dataout <= wire_nl1i1O11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i01i_dataout <= wire_nl1i1O0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i01l_dataout <= wire_nl1i1lOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i01O_dataout <= wire_nl1i1lOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0i_dataout <= wire_nl1i1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0ii_dataout <= wire_nl1i1O11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0il_dataout <= wire_nl1i1O11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0iO_dataout <= wire_nl1i1O10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0l_dataout <= nl1i1Oli WHEN niOO1l1li = '1' ELSE nl10OOii; + wire_nl1i1i0li_dataout <= wire_nl1i1O10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0ll_dataout <= wire_nl1i1O10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0lO_dataout <= wire_nl1i1O1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0O_dataout <= nl1i1Oll WHEN niOO1l1li = '1' ELSE nl10OOil; + wire_nl1i1i0Oi_dataout <= wire_nl1i1O1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i0Ol_dataout <= wire_nl1i1il0i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1101O; + wire_nl1i1i0OO_dataout <= wire_nl1i1il0l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11lOl; + wire_nl1i1i10i_dataout <= wire_nl1i1lllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i10l_dataout <= wire_nl1i1llOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i10O_dataout <= wire_nl1i1llOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i11i_dataout <= wire_nl1i1lliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i11l_dataout <= wire_nl1i1llli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i11O_dataout <= wire_nl1i1llll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1i_dataout <= wire_nl1i1lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1ii_dataout <= wire_nl1i1llOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1il_dataout <= wire_nl1i1lO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1iO_dataout <= wire_nl1i1O0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1l_dataout <= wire_nl1i1lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1li_dataout <= wire_nl1i1O0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1ll_dataout <= wire_nl1i1O0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1lO_dataout <= wire_nl1i1O0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1O_dataout <= wire_nl1i1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1Oi_dataout <= wire_nl1i1O0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1Ol_dataout <= wire_nl1i1O0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1i1OO_dataout <= wire_nl1i1O0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1i1ii0i_dataout <= wire_nl1i1iliO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11O1O; + wire_nl1i1ii0l_dataout <= wire_nl1i1illi_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11O0i; + wire_nl1i1ii0O_dataout <= wire_nl1i1illl_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11O0l; + wire_nl1i1ii1i_dataout <= wire_nl1i1il0O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11lOO; + wire_nl1i1ii1l_dataout <= wire_nl1i1ilii_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11O1i; + wire_nl1i1ii1O_dataout <= wire_nl1i1ilil_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11O1l; + wire_nl1i1iii_dataout <= nl1i1OlO WHEN niOO1l1li = '1' ELSE nl10OOiO; + wire_nl1i1iiii_dataout <= wire_nl1i1illO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11O0O; + wire_nl1i1iiil_dataout <= wire_nl1i1ilOi_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11Oii; + wire_nl1i1iiiO_dataout <= wire_nl1i1ilOl_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11Oil; + wire_nl1i1iil_dataout <= nl1i1OOi WHEN niOO1l1li = '1' ELSE nl10OOli; + wire_nl1i1iili_dataout <= wire_nl1i1ilOO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11OiO; + wire_nl1i1iill_dataout <= wire_nl1i1iOOl_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11Oli; + wire_nl1i1iilO_dataout <= wire_nl1i1iOOO_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11Oll; + wire_nl1i1iiO_dataout <= nl1i1OOl WHEN niOO1l1li = '1' ELSE nl10OOll; + wire_nl1i1iiOi_dataout <= wire_nl1i1l11i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11OlO; + wire_nl1i1iiOl_dataout <= wire_nl1i1l11l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11OOi; + wire_nl1i1iiOO_dataout <= wire_nl1i1l11O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11OOl; + wire_nl1i1il0i_dataout <= wire_nl1i1iO1i_dataout AND NOT(niOi1iO1l); + wire_nl1i1il0l_dataout <= wire_nl1i1iO1l_dataout AND NOT(niOi1iO1l); + wire_nl1i1il0O_dataout <= wire_nl1i1iO1O_dataout AND NOT(niOi1iO1l); + wire_nl1i1il1i_dataout <= wire_nl1i1l10i_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i11OOO; + wire_nl1i1il1l_dataout <= wire_nl1i1l10l_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1011i; + wire_nl1i1il1O_dataout <= wire_nl1i1l10O_dataout WHEN wire_w_lg_niOi1illO57815w(0) = '1' ELSE nl1i1011l; + wire_nl1i1ili_dataout <= nl1i1OOO WHEN niOO1l1li = '1' ELSE nl10OOlO; + wire_nl1i1ilii_dataout <= wire_nl1i1iO0i_dataout AND NOT(niOi1iO1l); + wire_nl1i1ilil_dataout <= wire_nl1i1iO0l_dataout AND NOT(niOi1iO1l); + wire_nl1i1iliO_dataout <= wire_nl1i1iO0O_dataout AND NOT(niOi1iO1l); + wire_nl1i1ill_dataout <= nl1i011i WHEN niOO1l1li = '1' ELSE nl10OOOi; + wire_nl1i1illi_dataout <= wire_nl1i1iOii_dataout AND NOT(niOi1iO1l); + wire_nl1i1illl_dataout <= wire_nl1i1iOil_dataout AND NOT(niOi1iO1l); + wire_nl1i1illO_dataout <= wire_nl1i1iOiO_dataout AND NOT(niOi1iO1l); + wire_nl1i1ilO_dataout <= nl1i011l WHEN niOO1l1li = '1' ELSE nl10OOOl; + wire_nl1i1ilOi_dataout <= wire_nl1i1iOli_dataout AND NOT(niOi1iO1l); + wire_nl1i1ilOl_dataout <= wire_nl1i1iOll_dataout AND NOT(niOi1iO1l); + wire_nl1i1ilOO_dataout <= wire_nl1i1iOlO_dataout AND NOT(niOi1iO1l); + wire_nl1i1iO0i_dataout <= wire_nl1i1iOOi_o(3) WHEN niOi1il0O = '1' ELSE nl1i11O1i; + wire_nl1i1iO0l_dataout <= wire_nl1i1iOOi_o(4) WHEN niOi1il0O = '1' ELSE nl1i11O1l; + wire_nl1i1iO0O_dataout <= wire_nl1i1iOOi_o(5) WHEN niOi1il0O = '1' ELSE nl1i11O1O; + wire_nl1i1iO1i_dataout <= wire_nl1i1iOOi_o(0) WHEN niOi1il0O = '1' ELSE nl1i1101O; + wire_nl1i1iO1l_dataout <= wire_nl1i1iOOi_o(1) WHEN niOi1il0O = '1' ELSE nl1i11lOl; + wire_nl1i1iO1O_dataout <= wire_nl1i1iOOi_o(2) WHEN niOi1il0O = '1' ELSE nl1i11lOO; + wire_nl1i1iOi_dataout <= nl1i011O WHEN niOO1l1li = '1' ELSE nl10OOOO; + wire_nl1i1iOii_dataout <= wire_nl1i1iOOi_o(6) WHEN niOi1il0O = '1' ELSE nl1i11O0i; + wire_nl1i1iOil_dataout <= wire_nl1i1iOOi_o(7) WHEN niOi1il0O = '1' ELSE nl1i11O0l; + wire_nl1i1iOiO_dataout <= wire_nl1i1iOOi_o(8) WHEN niOi1il0O = '1' ELSE nl1i11O0O; + wire_nl1i1iOl_dataout <= nl1i010i WHEN niOO1l1li = '1' ELSE nl1i111i; + wire_nl1i1iOli_dataout <= wire_nl1i1iOOi_o(9) WHEN niOi1il0O = '1' ELSE nl1i11Oii; + wire_nl1i1iOll_dataout <= wire_nl1i1iOOi_o(10) WHEN niOi1il0O = '1' ELSE nl1i11Oil; + wire_nl1i1iOlO_dataout <= wire_nl1i1iOOi_o(11) WHEN niOi1il0O = '1' ELSE nl1i11OiO; + wire_nl1i1iOO_dataout <= nl1i010l WHEN niOO1l1li = '1' ELSE nl1i111l; + wire_nl1i1iOOl_dataout <= wire_nl1i1l1ii_dataout AND NOT(niOi1iO1l); + wire_nl1i1iOOO_dataout <= wire_nl1i1l1il_dataout AND NOT(niOi1iO1l); + wire_nl1i1l00i_dataout <= wire_nl1i1li1i_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1010l; + wire_nl1i1l00l_dataout <= wire_nl1i1li1l_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1010O; + wire_nl1i1l00O_dataout <= wire_nl1i1li1O_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101ii; + wire_nl1i1l01l_dataout <= wire_nl1i1l0Ol_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1011O; + wire_nl1i1l01O_dataout <= wire_nl1i1l0OO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i1010i; + wire_nl1i1l0i_dataout <= nl1i01iO WHEN niOO1l1li = '1' ELSE nl1i110O; + wire_nl1i1l0ii_dataout <= wire_nl1i1li0i_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101il; + wire_nl1i1l0il_dataout <= wire_nl1i1li0l_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101iO; + wire_nl1i1l0iO_dataout <= wire_nl1i1li0O_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101li; + wire_nl1i1l0l_dataout <= nl1i01li WHEN niOO1l1li = '1' ELSE nl1i11ii; + wire_nl1i1l0li_dataout <= wire_nl1i1liii_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101ll; + wire_nl1i1l0ll_dataout <= wire_nl1i1liil_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101lO; + wire_nl1i1l0lO_dataout <= wire_nl1i1liiO_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101Oi; + wire_nl1i1l0O_dataout <= nl1i01ll WHEN niOO1l1li = '1' ELSE nl1i11il; + wire_nl1i1l0Oi_dataout <= wire_nl1i1lili_dataout WHEN wire_w_lg_niOi1ilOl57737w(0) = '1' ELSE nl1i101Ol; + wire_nl1i1l0Ol_dataout <= wire_nl1i1lill_dataout AND NOT(niOi1iO1l); + wire_nl1i1l0OO_dataout <= wire_nl1i1lilO_dataout AND NOT(niOi1iO1l); + wire_nl1i1l10i_dataout <= wire_nl1i1l1lO_dataout AND NOT(niOi1iO1l); + wire_nl1i1l10l_dataout <= wire_nl1i1l1Oi_dataout AND NOT(niOi1iO1l); + wire_nl1i1l10O_dataout <= wire_nl1i1l1Ol_dataout AND NOT(niOi1iO1l); + wire_nl1i1l11i_dataout <= wire_nl1i1l1iO_dataout AND NOT(niOi1iO1l); + wire_nl1i1l11l_dataout <= wire_nl1i1l1li_dataout AND NOT(niOi1iO1l); + wire_nl1i1l11O_dataout <= wire_nl1i1l1ll_dataout AND NOT(niOi1iO1l); + wire_nl1i1l1i_dataout <= nl1i010O WHEN niOO1l1li = '1' ELSE nl1i111O; + wire_nl1i1l1ii_dataout <= wire_nl1i1l1OO_o(0) WHEN niOi1il0O = '1' ELSE nl1i11Oli; + wire_nl1i1l1il_dataout <= wire_nl1i1l1OO_o(1) WHEN niOi1il0O = '1' ELSE nl1i11Oll; + wire_nl1i1l1iO_dataout <= wire_nl1i1l1OO_o(2) WHEN niOi1il0O = '1' ELSE nl1i11OlO; + wire_nl1i1l1l_dataout <= nl1i01ii WHEN niOO1l1li = '1' ELSE nl1i110i; + wire_nl1i1l1li_dataout <= wire_nl1i1l1OO_o(3) WHEN niOi1il0O = '1' ELSE nl1i11OOi; + wire_nl1i1l1ll_dataout <= wire_nl1i1l1OO_o(4) WHEN niOi1il0O = '1' ELSE nl1i11OOl; + wire_nl1i1l1lO_dataout <= wire_nl1i1l1OO_o(5) WHEN niOi1il0O = '1' ELSE nl1i11OOO; + wire_nl1i1l1O_dataout <= nl1i01il WHEN niOO1l1li = '1' ELSE nl1i110l; + wire_nl1i1l1Oi_dataout <= wire_nl1i1l1OO_o(6) WHEN niOi1il0O = '1' ELSE nl1i1011i; + wire_nl1i1l1Ol_dataout <= wire_nl1i1l1OO_o(7) WHEN niOi1il0O = '1' ELSE nl1i1011l; + wire_nl1i1li0i_dataout <= wire_nl1i1ll1i_dataout AND NOT(niOi1iO1l); + wire_nl1i1li0l_dataout <= wire_nl1i1ll1l_dataout AND NOT(niOi1iO1l); + wire_nl1i1li0O_dataout <= wire_nl1i1ll1O_dataout AND NOT(niOi1iO1l); + wire_nl1i1li1i_dataout <= wire_nl1i1liOi_dataout AND NOT(niOi1iO1l); + wire_nl1i1li1l_dataout <= wire_nl1i1liOl_dataout AND NOT(niOi1iO1l); + wire_nl1i1li1O_dataout <= wire_nl1i1liOO_dataout AND NOT(niOi1iO1l); + wire_nl1i1lii_dataout <= nl1i01lO WHEN niOO1l1li = '1' ELSE nl1i11iO; + wire_nl1i1liii_dataout <= wire_nl1i1ll0i_dataout AND NOT(niOi1iO1l); + wire_nl1i1liil_dataout <= wire_nl1i1ll0l_dataout AND NOT(niOi1iO1l); + wire_nl1i1liiO_dataout <= wire_nl1i1ll0O_dataout AND NOT(niOi1iO1l); + wire_nl1i1lil_dataout <= nl1i01Oi WHEN niOO1l1li = '1' ELSE nl1i11li; + wire_nl1i1lili_dataout <= wire_nl1i1llii_dataout AND NOT(niOi1iO1l); + wire_nl1i1lill_dataout <= wire_nl1i1llil_o(0) WHEN niOi1ilil = '1' ELSE nl1i1011O; + wire_nl1i1lilO_dataout <= wire_nl1i1llil_o(1) WHEN niOi1ilil = '1' ELSE nl1i1010i; + wire_nl1i1liO_dataout <= nl1i01Ol WHEN niOO1l1li = '1' ELSE nl1i11ll; + wire_nl1i1liOi_dataout <= wire_nl1i1llil_o(2) WHEN niOi1ilil = '1' ELSE nl1i1010l; + wire_nl1i1liOl_dataout <= wire_nl1i1llil_o(3) WHEN niOi1ilil = '1' ELSE nl1i1010O; + wire_nl1i1liOO_dataout <= wire_nl1i1llil_o(4) WHEN niOi1ilil = '1' ELSE nl1i101ii; + wire_nl1i1ll0i_dataout <= wire_nl1i1llil_o(8) WHEN niOi1ilil = '1' ELSE nl1i101ll; + wire_nl1i1ll0l_dataout <= wire_nl1i1llil_o(9) WHEN niOi1ilil = '1' ELSE nl1i101lO; + wire_nl1i1ll0O_dataout <= wire_nl1i1llil_o(10) WHEN niOi1ilil = '1' ELSE nl1i101Oi; + wire_nl1i1ll1i_dataout <= wire_nl1i1llil_o(5) WHEN niOi1ilil = '1' ELSE nl1i101il; + wire_nl1i1ll1l_dataout <= wire_nl1i1llil_o(6) WHEN niOi1ilil = '1' ELSE nl1i101iO; + wire_nl1i1ll1O_dataout <= wire_nl1i1llil_o(7) WHEN niOi1ilil = '1' ELSE nl1i101li; + wire_nl1i1lli_dataout <= nl1i01OO WHEN niOO1l1li = '1' ELSE nl1i11lO; + wire_nl1i1llii_dataout <= wire_nl1i1llil_o(11) WHEN niOi1ilil = '1' ELSE nl1i101Ol; + wire_nl1i1lliO_dataout <= wire_nl1i1lO1l_dataout AND NOT(niOi1iO1l); + wire_nl1i1llli_dataout <= wire_nl1i1lO1O_dataout AND NOT(niOi1iO1l); + wire_nl1i1llll_dataout <= wire_nl1i1lO0i_dataout AND NOT(niOi1iO1l); + wire_nl1i1lllO_dataout <= wire_nl1i1lO0l_dataout AND NOT(niOi1iO1l); + wire_nl1i1llOi_dataout <= wire_nl1i1lO0O_dataout AND NOT(niOi1iO1l); + wire_nl1i1llOl_dataout <= wire_nl1i1lOii_dataout AND NOT(niOi1iO1l); + wire_nl1i1llOO_dataout <= wire_nl1i1lOil_dataout AND NOT(niOi1iO1l); + wire_nl1i1lO0i_dataout <= wire_nl1i1lOli_o(2) WHEN niOi1ilil = '1' ELSE nl1i1001l; + wire_nl1i1lO0l_dataout <= wire_nl1i1lOli_o(3) WHEN niOi1ilil = '1' ELSE nl1i1001O; + wire_nl1i1lO0O_dataout <= wire_nl1i1lOli_o(4) WHEN niOi1ilil = '1' ELSE nl1i1000i; + wire_nl1i1lO1i_dataout <= wire_nl1i1lOiO_dataout AND NOT(niOi1iO1l); + wire_nl1i1lO1l_dataout <= wire_nl1i1lOli_o(0) WHEN niOi1ilil = '1' ELSE nl1i101OO; + wire_nl1i1lO1O_dataout <= wire_nl1i1lOli_o(1) WHEN niOi1ilil = '1' ELSE nl1i1001i; + wire_nl1i1lOi_dataout <= nl1i1O1i AND NOT(wire_niO01l0O_dataout); + wire_nl1i1lOii_dataout <= wire_nl1i1lOli_o(5) WHEN niOi1ilil = '1' ELSE nl1i1000l; + wire_nl1i1lOil_dataout <= wire_nl1i1lOli_o(6) WHEN niOi1ilil = '1' ELSE nl1i1000O; + wire_nl1i1lOiO_dataout <= wire_nl1i1lOli_o(7) WHEN niOi1ilil = '1' ELSE nl1i100ii; + wire_nl1i1lOlO_dataout <= wire_nl1i1O1iO_dataout AND NOT(niOi1iO1l); + wire_nl1i1lOO_dataout <= nl1i11Oi AND NOT(wire_niO01l0O_dataout); + wire_nl1i1lOOi_dataout <= wire_nl1i1O1li_dataout AND NOT(niOi1iO1l); + wire_nl1i1lOOl_dataout <= wire_nl1i1O1ll_dataout AND NOT(niOi1iO1l); + wire_nl1i1lOOO_dataout <= wire_nl1i1O1lO_dataout AND NOT(niOi1iO1l); + wire_nl1i1O00i_dataout <= wire_nl1i1O00O_o(10) WHEN niOi1illl = '1' ELSE nl1i10ill; + wire_nl1i1O00l_dataout <= wire_nl1i1O00O_o(11) WHEN niOi1illl = '1' ELSE nl1i10ilO; + wire_nl1i1O01i_dataout <= wire_nl1i1O00O_o(7) WHEN niOi1illl = '1' ELSE nl1i10iil; + wire_nl1i1O01l_dataout <= wire_nl1i1O00O_o(8) WHEN niOi1illl = '1' ELSE nl1i10iiO; + wire_nl1i1O01O_dataout <= wire_nl1i1O00O_o(9) WHEN niOi1illl = '1' ELSE nl1i10ili; + wire_nl1i1O0il_dataout <= wire_nl1i1Oi1i_dataout AND NOT(niOi1iO1l); + wire_nl1i1O0iO_dataout <= wire_nl1i1Oi1l_dataout AND NOT(niOi1iO1l); + wire_nl1i1O0l_dataout <= nl1i1O1O AND NOT(wire_niO01O0O_dataout); + wire_nl1i1O0li_dataout <= wire_nl1i1Oi1O_dataout AND NOT(niOi1iO1l); + wire_nl1i1O0ll_dataout <= wire_nl1i1Oi0i_dataout AND NOT(niOi1iO1l); + wire_nl1i1O0lO_dataout <= wire_nl1i1Oi0l_dataout AND NOT(niOi1iO1l); + wire_nl1i1O0O_dataout <= nl1i1lOl AND NOT(wire_niO01O0O_dataout); + wire_nl1i1O0Oi_dataout <= wire_nl1i1Oi0O_dataout AND NOT(niOi1iO1l); + wire_nl1i1O0Ol_dataout <= wire_nl1i1Oiii_dataout AND NOT(niOi1iO1l); + wire_nl1i1O0OO_dataout <= wire_nl1i1Oiil_dataout AND NOT(niOi1iO1l); + wire_nl1i1O10i_dataout <= wire_nl1i1O01i_dataout AND NOT(niOi1iO1l); + wire_nl1i1O10l_dataout <= wire_nl1i1O01l_dataout AND NOT(niOi1iO1l); + wire_nl1i1O10O_dataout <= wire_nl1i1O01O_dataout AND NOT(niOi1iO1l); + wire_nl1i1O11i_dataout <= wire_nl1i1O1Oi_dataout AND NOT(niOi1iO1l); + wire_nl1i1O11l_dataout <= wire_nl1i1O1Ol_dataout AND NOT(niOi1iO1l); + wire_nl1i1O11O_dataout <= wire_nl1i1O1OO_dataout AND NOT(niOi1iO1l); + wire_nl1i1O1ii_dataout <= wire_nl1i1O00i_dataout AND NOT(niOi1iO1l); + wire_nl1i1O1il_dataout <= wire_nl1i1O00l_dataout AND NOT(niOi1iO1l); + wire_nl1i1O1iO_dataout <= wire_nl1i1O00O_o(0) WHEN niOi1illl = '1' ELSE nl1i10i1i; + wire_nl1i1O1l_dataout <= nl1i1O0i AND NOT(wire_niO01O0O_dataout); + wire_nl1i1O1li_dataout <= wire_nl1i1O00O_o(1) WHEN niOi1illl = '1' ELSE nl1i10i1l; + wire_nl1i1O1ll_dataout <= wire_nl1i1O00O_o(2) WHEN niOi1illl = '1' ELSE nl1i10i1O; + wire_nl1i1O1lO_dataout <= wire_nl1i1O00O_o(3) WHEN niOi1illl = '1' ELSE nl1i10i0i; + wire_nl1i1O1Oi_dataout <= wire_nl1i1O00O_o(4) WHEN niOi1illl = '1' ELSE nl1i10i0l; + wire_nl1i1O1Ol_dataout <= wire_nl1i1O00O_o(5) WHEN niOi1illl = '1' ELSE nl1i10i0O; + wire_nl1i1O1OO_dataout <= wire_nl1i1O00O_o(6) WHEN niOi1illl = '1' ELSE nl1i10iii; + wire_nl1i1Oi0i_dataout <= wire_nl1i1OiiO_o(3) WHEN niOi1illl = '1' ELSE nl1i100ll; + wire_nl1i1Oi0l_dataout <= wire_nl1i1OiiO_o(4) WHEN niOi1illl = '1' ELSE nl1i100lO; + wire_nl1i1Oi0O_dataout <= wire_nl1i1OiiO_o(5) WHEN niOi1illl = '1' ELSE nl1i100Oi; + wire_nl1i1Oi1i_dataout <= wire_nl1i1OiiO_o(0) WHEN niOi1illl = '1' ELSE nl1i100il; + wire_nl1i1Oi1l_dataout <= wire_nl1i1OiiO_o(1) WHEN niOi1illl = '1' ELSE nl1i100iO; + wire_nl1i1Oi1O_dataout <= wire_nl1i1OiiO_o(2) WHEN niOi1illl = '1' ELSE nl1i100li; + wire_nl1i1Oiii_dataout <= wire_nl1i1OiiO_o(6) WHEN niOi1illl = '1' ELSE nl1i100Ol; + wire_nl1i1Oiil_dataout <= wire_nl1i1OiiO_o(7) WHEN niOi1illl = '1' ELSE nl1i100OO; + wire_nl1ii00O_dataout <= wire_nl1ii0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1ii01i_dataout <= nl1ii1Ol AND NOT(wire_niO01O0O_dataout); + wire_nl1ii01l_dataout <= nl1ii1li AND NOT(wire_niO01O0O_dataout); + wire_nl1ii0ii_dataout <= wire_nl1ii0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1ii0il_dataout <= wire_nl1ii0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1ii0iO_dataout <= wire_nl1ii0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1ii0li_dataout <= wire_niOOO0O_w_lg_nl1ii1OO8021w(0) WHEN (wire_w_lg_niOO1l1Ol8018w(0) AND (NOT (((NOT (dl_maxpload_dcr(0) XOR nl1ii01O)) AND (NOT (dl_maxpload_dcr(1) XOR nl1ii00i))) AND (NOT (dl_maxpload_dcr(2) XOR nl1ii00l))))) = '1' ELSE nl1ii1OO; + wire_nl1ii0lO_dataout <= dl_maxpload_dcr(0) WHEN wire_w_lg_niOO1l1Ol8018w(0) = '1' ELSE nl1ii01O; + wire_nl1ii0Oi_dataout <= dl_maxpload_dcr(1) WHEN wire_w_lg_niOO1l1Ol8018w(0) = '1' ELSE nl1ii00i; + wire_nl1ii0Ol_dataout <= dl_maxpload_dcr(2) WHEN wire_w_lg_niOO1l1Ol8018w(0) = '1' ELSE nl1ii00l; + wire_nl1ii100i_dataout <= wire_nl1ii10iO_o(4) WHEN niOi1l01l = '1' ELSE nl1i011ii; + wire_nl1ii100l_dataout <= wire_nl1ii10iO_o(5) WHEN niOi1l01l = '1' ELSE nl1i011il; + wire_nl1ii100O_dataout <= wire_nl1ii10iO_o(6) WHEN niOi1l01l = '1' ELSE nl1i011iO; + wire_nl1ii101i_dataout <= wire_nl1ii10iO_o(1) WHEN niOi1l01l = '1' ELSE nl1i0110i; + wire_nl1ii101l_dataout <= wire_nl1ii10iO_o(2) WHEN niOi1l01l = '1' ELSE nl1i0110l; + wire_nl1ii101O_dataout <= wire_nl1ii10iO_o(3) WHEN niOi1l01l = '1' ELSE nl1i0110O; + wire_nl1ii10i_dataout <= nl1ii00i WHEN niOO1l1Oi = '1' ELSE nl1i0OlO; + wire_nl1ii10ii_dataout <= wire_nl1ii10iO_o(7) WHEN niOi1l01l = '1' ELSE nl1i011li; + wire_nl1ii10il_dataout <= wire_nl1ii10iO_o(8) WHEN niOi1l01l = '1' ELSE nl1i011ll; + wire_nl1ii10l_dataout <= nl1ii00l WHEN niOO1l1Oi = '1' ELSE nl1i0OOi; + wire_nl1ii111i_dataout <= wire_nl1ii111l_o(12) WHEN niOi1l1Oi = '1' ELSE nl1i010il; + wire_nl1ii11i_dataout <= wire_nl1ii10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ii11il_dataout <= wire_nl1ii10lO_o(0) WHEN niOi1l00O = '1' ELSE wire_nl1ii101i_dataout; + wire_nl1ii11iO_dataout <= wire_nl1ii10lO_o(1) WHEN niOi1l00O = '1' ELSE wire_nl1ii101l_dataout; + wire_nl1ii11l_dataout <= wire_nl1ii10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ii11li_dataout <= wire_nl1ii10lO_o(2) WHEN niOi1l00O = '1' ELSE wire_nl1ii101O_dataout; + wire_nl1ii11ll_dataout <= wire_nl1ii10lO_o(3) WHEN niOi1l00O = '1' ELSE wire_nl1ii100i_dataout; + wire_nl1ii11lO_dataout <= wire_nl1ii10lO_o(4) WHEN niOi1l00O = '1' ELSE wire_nl1ii100l_dataout; + wire_nl1ii11O_dataout <= nl1ii01O WHEN niOO1l1Oi = '1' ELSE nl1ii1ii; + wire_nl1ii11Oi_dataout <= wire_nl1ii10lO_o(5) WHEN niOi1l00O = '1' ELSE wire_nl1ii100O_dataout; + wire_nl1ii11Ol_dataout <= wire_nl1ii10lO_o(6) WHEN niOi1l00O = '1' ELSE wire_nl1ii10ii_dataout; + wire_nl1ii11OO_dataout <= wire_nl1ii10lO_o(7) WHEN niOi1l00O = '1' ELSE wire_nl1ii10il_dataout; + wire_nl1ii1iO_dataout <= nl1ii1lO AND NOT(wire_niO01l0O_dataout); + wire_nl1ii1ll_dataout <= nl1i0OOl AND NOT(wire_niO01l0O_dataout); + wire_nl1ii1Oi_dataout <= nl1ii1OO AND NOT(wire_niO01O0O_dataout); + wire_nl1iii0O_dataout <= nl1iiiiO AND NOT(wire_niO01O0O_dataout); + wire_nl1iii1l_dataout <= (nl1iiill XOR nl1iiiiO) AND NOT(wire_niO01l0O_dataout); + wire_nl1iiiil_dataout <= nl1iii1i AND NOT(wire_niO01O0O_dataout); + wire_nl1iiili_dataout <= nl1iiilO AND NOT(wire_niO01l0O_dataout); + wire_nl1iiiOi_dataout <= nl1iiill AND NOT(wire_niO01l0O_dataout); + wire_nl1iiiOl_dataout <= nl1iiiii AND NOT(wire_niO01l0O_dataout); + wire_nl1iiiOOi_dataout <= wire_nl1ili1lO_dataout AND wire_nl1lOOO0l_dataout; + wire_nl1iiiOOl_dataout <= wire_nl1iiiOOi_dataout WHEN niOi1lili = '1' ELSE wire_nl1lOOO0l_dataout; + wire_nl1iiiOOO_dataout <= wire_nl1il0iOO_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1iiiOOl_dataout; + wire_nl1iil00i_dataout <= wire_nl1il0iOi_dataout WHEN niOi1liiO = '1' ELSE wire_nl1iil01O_dataout; + wire_nl1iil00l_dataout <= wire_nl1il0lOi_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1iil00i_dataout; + wire_nl1iil00O_dataout <= wire_nl1iil00l_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1O0l_dataout; + wire_nl1iil01i_dataout <= wire_nl1iil1OO_dataout WHEN niOi1lili = '1' ELSE wire_nl1lOOO0l_dataout; + wire_nl1iil01l_dataout <= wire_nl1il0iOi_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1iil01i_dataout; + wire_nl1iil01O_dataout <= wire_nl1il0l0l_dataout WHEN niOi1O11l = '1' ELSE wire_nl1iil01l_dataout; + wire_nl1iil0ii_dataout <= wire_nl1iil00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iil0il_dataout <= wire_nl1ili1iO_dataout AND wire_nl1lOOO0l_dataout; + wire_nl1iil0iO_dataout <= wire_nl1iil0il_dataout WHEN niOi1lili = '1' ELSE wire_nl1lOOO0l_dataout; + wire_nl1iil0li_dataout <= wire_nl1il0ilO_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1iil0iO_dataout; + wire_nl1iil0ll_dataout <= wire_nl1il0l0l_dataout WHEN niOi1O11l = '1' ELSE wire_nl1iil0li_dataout; + wire_nl1iil0lO_dataout <= wire_nl1il0ilO_dataout WHEN niOi1liiO = '1' ELSE wire_nl1iil0ll_dataout; + wire_nl1iil0Oi_dataout <= wire_nl1il0llO_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1iil0lO_dataout; + wire_nl1iil0OO_dataout <= wire_nl1iil0Oi_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1O0i_dataout; + wire_nl1iil10i_dataout <= wire_nl1iil11O_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1Oii_dataout; + wire_nl1iil10l_dataout <= wire_nl1iil10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iil11i_dataout <= wire_nl1il0l0l_dataout WHEN niOi1O11l = '1' ELSE wire_nl1iiiOOO_dataout; + wire_nl1iil11l_dataout <= wire_nl1il0iOO_dataout WHEN niOi1liiO = '1' ELSE wire_nl1iil11i_dataout; + wire_nl1iil11O_dataout <= wire_nl1il0lOO_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1iil11l_dataout; + wire_nl1iil1i_dataout <= wire_nl1iil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iil1ii_dataout <= wire_nl1ili1ll_dataout AND wire_nl1lOOO0l_dataout; + wire_nl1iil1il_dataout <= wire_nl1iil1ii_dataout WHEN niOi1lili = '1' ELSE wire_nl1lOOO0l_dataout; + wire_nl1iil1iO_dataout <= wire_nl1il0iOl_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1iil1il_dataout; + wire_nl1iil1l_dataout <= wire_nl1iilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iil1li_dataout <= wire_nl1il0l0l_dataout WHEN niOi1O11l = '1' ELSE wire_nl1iil1iO_dataout; + wire_nl1iil1ll_dataout <= wire_nl1il0iOl_dataout WHEN niOi1liiO = '1' ELSE wire_nl1iil1li_dataout; + wire_nl1iil1lO_dataout <= wire_nl1il0lOl_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1iil1ll_dataout; + wire_nl1iil1O_dataout <= wire_nl1000i_w_lg_nl1iiilO8010w(0) WHEN (wire_nlOi0000l_dataout AND (wire_w_lg_niOO1l1OO8011w(0) AND (wire_nlOi0000l_dataout XOR nl1iiiOO))) = '1' ELSE nl1iiilO; + wire_nl1iil1Oi_dataout <= wire_nl1iil1lO_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1O0O_dataout; + wire_nl1iil1Ol_dataout <= wire_nl1iil1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iil1OO_dataout <= wire_nl1ili1li_dataout AND wire_nl1lOOO0l_dataout; + wire_nl1iili0i_dataout <= wire_nl1il0l0i_dataout WHEN niOi1O11l = '1' ELSE wire_nl1iili1O_dataout; + wire_nl1iili0l_dataout <= wire_nl1iili0i_dataout AND NOT(niOi1liiO); + wire_nl1iili1i_dataout <= wire_nl1iil0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iili1O_dataout <= wire_nl1il0iOO_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1iilii_dataout <= nl1iiiOO WHEN niOO1l1OO = '1' ELSE wire_nlOi0000l_dataout; + wire_nl1iiliOl_dataout <= wire_nl1iiO1ii_o(0) WHEN niOi1l0li = '1' ELSE wire_nl1iillli_dataout; + wire_nl1iiliOO_dataout <= wire_nl1iiO1ii_o(1) WHEN niOi1l0li = '1' ELSE wire_nl1iillll_dataout; + wire_nl1iill0i_dataout <= wire_nl1iiO1ii_o(5) WHEN niOi1l0li = '1' ELSE wire_nl1iillOO_dataout; + wire_nl1iill0l_dataout <= wire_nl1iiO1ii_o(6) WHEN niOi1l0li = '1' ELSE wire_nl1iilO1i_dataout; + wire_nl1iill0O_dataout <= wire_nl1iiO1ii_o(7) WHEN niOi1l0li = '1' ELSE wire_nl1iilO1l_dataout; + wire_nl1iill1i_dataout <= wire_nl1iiO1ii_o(2) WHEN niOi1l0li = '1' ELSE wire_nl1iilllO_dataout; + wire_nl1iill1l_dataout <= wire_nl1iiO1ii_o(3) WHEN niOi1l0li = '1' ELSE wire_nl1iillOi_dataout; + wire_nl1iill1O_dataout <= wire_nl1iiO1ii_o(4) WHEN niOi1l0li = '1' ELSE wire_nl1iillOl_dataout; + wire_nl1iilli_dataout <= (nl1iiO0i XOR nl1iiO1l) AND NOT(wire_niO01l0O_dataout); + wire_nl1iillii_dataout <= wire_nl1iiO1ii_o(8) WHEN niOi1l0li = '1' ELSE wire_nl1iilO1O_dataout; + wire_nl1iillil_dataout <= wire_nl1iiO1ii_o(9) WHEN niOi1l0li = '1' ELSE wire_nl1iilO0i_dataout; + wire_nl1iilliO_dataout <= wire_nl1iiO1ii_o(10) WHEN niOi1l0li = '1' ELSE wire_nl1iilO0l_dataout; + wire_nl1iillli_dataout <= wire_nl1iilO0O_dataout AND NOT(niOi1l0ll); + wire_nl1iillll_dataout <= wire_nl1iilOii_dataout AND NOT(niOi1l0ll); + wire_nl1iilllO_dataout <= wire_nl1iiO10l_o(0) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOil_dataout; + wire_nl1iillOi_dataout <= wire_nl1iiO10l_o(1) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOiO_dataout; + wire_nl1iillOl_dataout <= wire_nl1iiO10l_o(2) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOli_dataout; + wire_nl1iillOO_dataout <= wire_nl1iiO10l_o(3) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOll_dataout; + wire_nl1iilO0i_dataout <= wire_nl1iiO10l_o(7) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOOO_dataout; + wire_nl1iilO0l_dataout <= wire_nl1iiO10l_o(8) WHEN niOi1l0ll = '1' ELSE wire_nl1iiO11i_dataout; + wire_nl1iilO0O_dataout <= wire_nl1iiO11O_o(0) AND niOi1l0lO; + wire_nl1iilO1i_dataout <= wire_nl1iiO10l_o(4) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOlO_dataout; + wire_nl1iilO1l_dataout <= wire_nl1iiO10l_o(5) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOOi_dataout; + wire_nl1iilO1O_dataout <= wire_nl1iiO10l_o(6) WHEN niOi1l0ll = '1' ELSE wire_nl1iilOOl_dataout; + wire_nl1iilOii_dataout <= wire_nl1iiO11O_o(1) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(0); + wire_nl1iilOil_dataout <= wire_nl1iiO11O_o(2) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(1); + wire_nl1iilOiO_dataout <= wire_nl1iiO11O_o(3) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(2); + wire_nl1iilOl_dataout <= nl1iiO1l AND NOT(wire_niO01O0O_dataout); + wire_nl1iilOli_dataout <= wire_nl1iiO11O_o(4) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(3); + wire_nl1iilOll_dataout <= wire_nl1iiO11O_o(5) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(4); + wire_nl1iilOlO_dataout <= wire_nl1iiO11O_o(6) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(5); + wire_nl1iilOOi_dataout <= wire_nl1iiO11O_o(7) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(6); + wire_nl1iilOOl_dataout <= wire_nl1iiO11O_o(8) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(7); + wire_nl1iilOOO_dataout <= wire_nl1iiO11O_o(9) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(8); + wire_nl1iiO00i_dataout <= wire_nl1il0l1O_dataout WHEN niOi1O11l = '1' ELSE wire_nl1iiO1OO_dataout; + wire_nl1iiO00O_dataout <= wire_nl1iiO00i_dataout AND NOT(niOi1liiO); + wire_nl1iiO0ii_dataout <= wire_nl1il0lli_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1iiO00O_dataout; + wire_nl1iiO0iO_dataout <= wire_nl1iiO0ii_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1O1l_dataout; + wire_nl1iiO0O_dataout <= nl1iiO0i AND NOT(wire_niO01l0O_dataout); + wire_nl1iiO10i_dataout <= wire_nl1il0lll_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1iili0l_dataout; + wire_nl1iiO10O_dataout <= wire_nl1iiO10i_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1O1O_dataout; + wire_nl1iiO11i_dataout <= wire_nl1iiO11O_o(10) WHEN niOi1l0lO = '1' ELSE wire_nl1iiO11l_o(9); + wire_nl1iiO1i_dataout <= nl1iiliO AND NOT(wire_niO01O0O_dataout); + wire_nl1iiO1il_dataout <= wire_nl1iiO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiO1O_dataout <= nl1iiO0l AND NOT(wire_niO01l0O_dataout); + wire_nl1iiO1OO_dataout <= wire_nl1il0iOl_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1iiOii_dataout <= nl1iilOO AND NOT(wire_niO01l0O_dataout); + wire_nl1iiOiil_dataout <= wire_nl1iiOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOiiO_dataout <= wire_nl1iiOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOili_dataout <= wire_nl1iiOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOill_dataout <= wire_nl1iiOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOilO_dataout <= wire_nl1iiOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOiO_dataout <= wire_nl1iiOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOiOi_dataout <= wire_nl1iiOOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOiOl_dataout <= wire_nl1iiOOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOiOO_dataout <= wire_nl1iiOOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOl0i_dataout <= wire_nl1iiOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOl0l_dataout <= wire_nl1iiOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOl0O_dataout <= wire_nl1iiOlii_dataout OR (wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND nl1ll0iOl); + wire_nl1iiOl1i_dataout <= wire_nl1iiOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOl1l_dataout <= wire_nl1iiOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOl1O_dataout <= wire_nl1iiOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOli_dataout <= wire_nl1iiOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOlii_dataout <= nl1iil0Ol AND NOT((niOi1Oi0i OR (wire_nlill0Oll_w_lg_nl1iiO0li56217w(0) AND niOi1Ol0i))); + wire_nl1iiOlil_dataout <= wire_nl1iiO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1iiOll_dataout <= wire_nl1000i_w_lg_nl1iiO0l8003w(0) WHEN (wire_nlOi01Oll_dataout AND (wire_w_lg_niOO1l01i8004w(0) AND (wire_nlOi01Oll_dataout XOR nl1iiOil))) = '1' ELSE nl1iiO0l; + wire_nl1iiOllO_dataout <= wire_nl1iiOlOi_dataout OR (wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND nl1OilO1i); + wire_nl1iiOlOi_dataout <= nl1iiO0li AND NOT((niOi1Oi0l OR niOi1Oi0i)); + wire_nl1iiOlOO_dataout <= wire_nl1il0iOi_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1iiOO0l_dataout <= wire_nl1il111O_dataout WHEN nl1OilO1i = '1' ELSE nl1iiO0ll; + wire_nl1iiOO0O_dataout <= niOi1li1i WHEN nl1OilO1i = '1' ELSE nl1iiO0lO; + wire_nl1iiOO1i_dataout <= wire_nl1il0l1l_dataout WHEN niOi1O11l = '1' ELSE wire_nl1iiOlOO_dataout; + wire_nl1iiOO1l_dataout <= wire_nl1iiOO1i_dataout AND NOT(niOi1liiO); + wire_nl1iiOO1O_dataout <= wire_nl1il0liO_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1iiOO1l_dataout; + wire_nl1iiOOii_dataout <= wire_nl1il11iO_dataout WHEN nl1OilO1i = '1' ELSE nl1iiO0Oi; + wire_nl1iiOOil_dataout <= wire_nl1il11li_dataout WHEN nl1OilO1i = '1' ELSE nl1iiO0Ol; + wire_nl1iiOOiO_dataout <= wire_nl1il11ll_dataout WHEN nl1OilO1i = '1' ELSE nl1iiO0OO; + wire_nl1iiOOli_dataout <= wire_nl1il11lO_dataout WHEN nl1OilO1i = '1' ELSE nl1iiOi1i; + wire_nl1iiOOll_dataout <= wire_nl1il11Oi_dataout WHEN nl1OilO1i = '1' ELSE nl1iiOi1l; + wire_nl1iiOOlO_dataout <= wire_nl1il11Ol_dataout WHEN nl1OilO1i = '1' ELSE nl1iiOi1O; + wire_nl1iiOOO_dataout <= nl1iiOil WHEN niOO1l01i = '1' ELSE wire_nlOi01Oll_dataout; + wire_nl1iiOOOi_dataout <= wire_nl1il11OO_dataout WHEN nl1OilO1i = '1' ELSE nl1iiOi0i; + wire_nl1iiOOOl_dataout <= wire_nl1il101i_dataout WHEN nl1OilO1i = '1' ELSE nl1iiOi0l; + wire_nl1iiOOOO_dataout <= (wire_nl1lOOO0l_dataout AND (wire_nl1il10OO_o OR niOi1O1ll)) WHEN nl1OilO1i = '1' ELSE nl1iiOi0O; + wire_nl1il000O_dataout <= wire_nl1il1i1i_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1lOO_dataout; + wire_nl1il001i_dataout <= nl1il1iii OR NOT(niOi1li1O); + wire_nl1il00il_dataout <= wire_nl1il000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il00li_dataout <= nl1il1i0i OR NOT(nl1il1i1O); + wire_nl1il00ll_dataout <= nl1il1i0l OR NOT(nl1il1i1O); + wire_nl1il00lO_dataout <= nl1il1i0O OR NOT(nl1il1i1O); + wire_nl1il00O_dataout <= nl1il00i AND NOT(wire_niO01l0O_dataout); + wire_nl1il00Oi_dataout <= nl1il1iii OR NOT(nl1il1i1O); + wire_nl1il010i_dataout <= nl1il1ill OR niOi1li0i; + wire_nl1il010l_dataout <= wire_nl1il01iO_dataout WHEN niOi1li0i = '1' ELSE nl1il1ilO; + wire_nl1il010O_dataout <= wire_nl1il01li_dataout WHEN niOi1li0i = '1' ELSE nl1il1iOi; + wire_nl1il011i_dataout <= nl1il1iil OR niOi1li0i; + wire_nl1il011l_dataout <= nl1il1iiO OR niOi1li0i; + wire_nl1il011O_dataout <= nl1il1ili OR niOi1li0i; + wire_nl1il01i_dataout <= nl1il10O AND NOT(wire_niO01O0O_dataout); + wire_nl1il01ii_dataout <= wire_nl1il01ll_dataout WHEN niOi1li0i = '1' ELSE nl1il1iOl; + wire_nl1il01il_dataout <= wire_nl1il01lO_dataout WHEN niOi1li0i = '1' ELSE nl1il1iOO; + wire_nl1il01iO_dataout <= wire_nl1il01Oi_dataout OR wire_nlill0Oll_w_lg_nl1iiOiii56091w(0); + wire_nl1il01li_dataout <= wire_nl1il01Ol_dataout OR wire_nlill0Oll_w_lg_nl1iiOiii56091w(0); + wire_nl1il01ll_dataout <= wire_nl1il01OO_dataout OR wire_nlill0Oll_w_lg_nl1iiOiii56091w(0); + wire_nl1il01lO_dataout <= wire_nl1il001i_dataout OR wire_nlill0Oll_w_lg_nl1iiOiii56091w(0); + wire_nl1il01O_dataout <= nl1il00l AND NOT(wire_niO01l0O_dataout); + wire_nl1il01Oi_dataout <= nl1il1i0i OR NOT(niOi1li1O); + wire_nl1il01Ol_dataout <= nl1il1i0l OR NOT(niOi1li1O); + wire_nl1il01OO_dataout <= nl1il1i0O OR NOT(niOi1li1O); + wire_nl1il0i0i_dataout <= nl1il1i0O AND NOT(nl1il1i1O); + wire_nl1il0i0l_dataout <= nl1il1iii AND NOT(nl1il1i1O); + wire_nl1il0i1l_dataout <= nl1il1i0i AND NOT(nl1il1i1O); + wire_nl1il0i1O_dataout <= nl1il1i0l AND NOT(nl1il1i1O); + wire_nl1il0ii_dataout <= nl1il1OO AND NOT(wire_niO01l0O_dataout); + wire_nl1il0iii_dataout <= niOi1liil WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE (wire_nl1lOOO0l_dataout AND niOi1liil); + wire_nl1il0iil_dataout <= wire_nl1il0lii_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1il0ill_dataout; + wire_nl1il0ill_dataout <= niOi1O11l AND NOT(niOi1liiO); + wire_nl1il0ilO_dataout <= wire_nl1ili1Oi_dataout OR NOT(wire_nl1lOOO0l_dataout); + wire_nl1il0iOi_dataout <= wire_nl1ili1Ol_dataout OR NOT(wire_nl1lOOO0l_dataout); + wire_nl1il0iOl_dataout <= wire_nl1ili1OO_dataout OR NOT(wire_nl1lOOO0l_dataout); + wire_nl1il0iOO_dataout <= wire_nl1ili01i_dataout OR NOT(wire_nl1lOOO0l_dataout); + wire_nl1il0l0i_dataout <= wire_nl1ili01i_dataout WHEN wire_nl1lOOO0l_dataout = '1' ELSE wire_nl1lOOlOi_w_lg_dataout55789w(0); + wire_nl1il0l0l_dataout <= wire_nl1lOOlOi_dataout OR wire_nl1lOOO0l_dataout; + wire_nl1il0l1i_dataout <= wire_nl1ili1Oi_dataout WHEN wire_nl1lOOO0l_dataout = '1' ELSE wire_nl1lOOlOi_w_lg_dataout55789w(0); + wire_nl1il0l1l_dataout <= wire_nl1ili1Ol_dataout WHEN wire_nl1lOOO0l_dataout = '1' ELSE wire_nl1lOOlOi_w_lg_dataout55789w(0); + wire_nl1il0l1O_dataout <= wire_nl1ili1OO_dataout WHEN wire_nl1lOOO0l_dataout = '1' ELSE wire_nl1lOOlOi_w_lg_dataout55789w(0); + wire_nl1il0li_dataout <= wire_nl1il0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il0lii_dataout <= wire_nl1il0O1i_dataout OR niOi1liiO; + wire_nl1il0lil_dataout <= wire_nl1il0O1l_dataout AND NOT(niOi1liiO); + wire_nl1il0liO_dataout <= wire_nl1il0O1O_dataout AND NOT(niOi1liiO); + wire_nl1il0ll_dataout <= wire_nl1il0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il0lli_dataout <= wire_nl1il0O0i_dataout AND NOT(niOi1liiO); + wire_nl1il0lll_dataout <= wire_nl1il0O0l_dataout AND NOT(niOi1liiO); + wire_nl1il0llO_dataout <= wire_nl1ili1Oi_dataout WHEN niOi1liiO = '1' ELSE wire_nl1il0O0O_dataout; + wire_nl1il0lO_dataout <= wire_nl1ili1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il0lOi_dataout <= wire_nl1ili1Ol_dataout WHEN niOi1liiO = '1' ELSE wire_nl1il0Oii_dataout; + wire_nl1il0lOl_dataout <= wire_nl1ili1OO_dataout WHEN niOi1liiO = '1' ELSE wire_nl1il0Oil_dataout; + wire_nl1il0lOO_dataout <= wire_nl1ili01i_dataout WHEN niOi1liiO = '1' ELSE wire_nl1il0OiO_dataout; + wire_nl1il0O0i_dataout <= wire_nl1ili1OO_dataout WHEN niOi1O11l = '1' ELSE wire_nl1il0OOi_dataout; + wire_nl1il0O0l_dataout <= wire_nl1ili01i_dataout WHEN niOi1O11l = '1' ELSE wire_nl1il0OOl_dataout; + wire_nl1il0O0O_dataout <= wire_nl1il0OOO_dataout AND NOT(niOi1O11l); + wire_nl1il0O1i_dataout <= wire_nl1il0Oli_dataout OR niOi1O11l; + wire_nl1il0O1l_dataout <= wire_nl1ili1Oi_dataout WHEN niOi1O11l = '1' ELSE wire_nl1il0Oll_dataout; + wire_nl1il0O1O_dataout <= wire_nl1ili1Ol_dataout WHEN niOi1O11l = '1' ELSE wire_nl1il0OlO_dataout; + wire_nl1il0Oi_dataout <= wire_nl1000i_w_lg_nl1il00l7993w(0) WHEN (wire_w_lg_niOO1l01O7992w(0) AND (NOT ((NOT (wire_nlOi00O1O_dataout XOR nl1il0il)) AND (NOT (wire_nlOi00O0i_dataout XOR nl1il0iO))))) = '1' ELSE nl1il00l; + wire_nl1il0Oii_dataout <= wire_nl1ili11i_dataout AND NOT(niOi1O11l); + wire_nl1il0Oil_dataout <= wire_nl1ili11l_dataout AND NOT(niOi1O11l); + wire_nl1il0OiO_dataout <= wire_nl1ili11O_dataout AND NOT(niOi1O11l); + wire_nl1il0Oli_dataout <= niOi1lili AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1il0Oll_dataout <= wire_nl1ili1Oi_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1il0OlO_dataout <= wire_nl1ili1Ol_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1il0OO_dataout <= wire_nlOi00O1O_dataout WHEN wire_w_lg_niOO1l01O7992w(0) = '1' ELSE nl1il0il; + wire_nl1il0OOi_dataout <= wire_nl1ili1OO_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1il0OOl_dataout <= wire_nl1ili01i_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1il0OOO_dataout <= wire_nl1ili1Oi_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1ili10i_dataout; + wire_nl1il100i_dataout <= wire_nl1il10lO_o(1) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOiil_dataout; + wire_nl1il100l_dataout <= wire_nl1il10lO_o(2) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOiiO_dataout; + wire_nl1il100O_dataout <= wire_nl1il10lO_o(3) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOili_dataout; + wire_nl1il101i_dataout <= wire_nl1il10li_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il101l_dataout <= wire_nl1il0l1i_dataout WHEN niOi1O11l = '1' ELSE wire_nl1il11il_dataout; + wire_nl1il101O_dataout <= wire_nl1il10lO_o(0) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOiii_dataout; + wire_nl1il10ii_dataout <= wire_nl1il10lO_o(4) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOill_dataout; + wire_nl1il10il_dataout <= wire_nl1il10lO_o(5) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOilO_dataout; + wire_nl1il10iO_dataout <= wire_nl1il10lO_o(6) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOiOi_dataout; + wire_nl1il10li_dataout <= wire_nl1il10lO_o(7) WHEN wire_w_lg_niOi1li1l56196w(0) = '1' ELSE wire_nl1lOOiOl_dataout; + wire_nl1il10ll_dataout <= wire_nl1il101l_dataout AND NOT(niOi1liiO); + wire_nl1il111i_dataout <= wire_nl1iiOO1O_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1il1O1i_dataout; + wire_nl1il111l_dataout <= wire_nl1il111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il111O_dataout <= (NOT ((wire_nl1lOOO0l_dataout AND niOi1l0OO) OR wire_nl1lOOO0i_w_lg_dataout56210w(0))) AND NOT(niOi1li1i); + wire_nl1il11il_dataout <= wire_nl1il0ilO_dataout AND NOT(wire_nl1lOOlOi_dataout); + wire_nl1il11iO_dataout <= wire_nl1il101O_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il11li_dataout <= wire_nl1il100i_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il11ll_dataout <= wire_nl1il100l_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il11lO_dataout <= wire_nl1il100O_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il11Oi_dataout <= wire_nl1il10ii_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il11Ol_dataout <= wire_nl1il10il_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il11OO_dataout <= wire_nl1il10iO_dataout AND NOT(wire_nl1lOOO0l_w_lg_dataout52008w(0)); + wire_nl1il1i1i_dataout <= wire_nl1il0lil_dataout WHEN wire_w_lg_niOi1O1li56089w(0) = '1' ELSE wire_nl1il10ll_dataout; + wire_nl1il1ii_dataout <= wire_nl1il1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1il1il_dataout <= wire_nl1il1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1il1iO_dataout <= nl1il0il WHEN niOO1l01l = '1' ELSE nl1il1lO; + wire_nl1il1l0i_dataout <= wire_nl1il1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il1l0l_dataout <= wire_nl1il1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il1l0O_dataout <= wire_nl1il1lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il1l1i_dataout <= wire_nl1il1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il1l1l_dataout <= wire_nl1il1lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il1l1O_dataout <= wire_nl1il1lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il1li_dataout <= nl1il0iO WHEN niOO1l01l = '1' ELSE nl1il10l; + wire_nl1il1lii_dataout <= wire_nl1il1llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1il1lil_dataout <= wire_nl1il0iii_dataout WHEN nl1ll0iOl = '1' ELSE nl1il1i1O; + wire_nl1il1liO_dataout <= wire_nl1ili1iO_dataout WHEN nl1ll0iOl = '1' ELSE nl1il1i0i; + wire_nl1il1lli_dataout <= wire_nl1ili1li_dataout WHEN nl1ll0iOl = '1' ELSE nl1il1i0l; + wire_nl1il1lll_dataout <= wire_nl1ili1ll_dataout WHEN nl1ll0iOl = '1' ELSE nl1il1i0O; + wire_nl1il1llO_dataout <= wire_nl1ili1lO_dataout WHEN nl1ll0iOl = '1' ELSE nl1il1iii; + wire_nl1il1lOi_dataout <= wire_nl1il0iil_dataout WHEN nl1ll0iOl = '1' ELSE nl1il1i1l; + wire_nl1il1lOl_dataout <= niOi1O1li WHEN nl1ll0iOl = '1' ELSE nl1iiOiii; + wire_nl1il1lOO_dataout <= wire_nl1il00li_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1Oil_dataout; + wire_nl1il1O0i_dataout <= wire_nl1il0i1l_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1OlO_dataout; + wire_nl1il1O0l_dataout <= wire_nl1il0i1O_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1OOi_dataout; + wire_nl1il1O0O_dataout <= wire_nl1il0i0i_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1OOl_dataout; + wire_nl1il1O1i_dataout <= wire_nl1il00ll_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1OiO_dataout; + wire_nl1il1O1l_dataout <= wire_nl1il00lO_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1Oli_dataout; + wire_nl1il1O1O_dataout <= wire_nl1il00Oi_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1Oll_dataout; + wire_nl1il1Oii_dataout <= wire_nl1il0i0l_dataout WHEN niOi1li0O = '1' ELSE wire_nl1il1OOO_dataout; + wire_nl1il1Oil_dataout <= wire_nl1il00li_dataout WHEN niOi1li0l = '1' ELSE wire_nl1il011i_dataout; + wire_nl1il1OiO_dataout <= wire_nl1il00ll_dataout WHEN niOi1li0l = '1' ELSE wire_nl1il011l_dataout; + wire_nl1il1Ol_dataout <= nl1il01l AND NOT(wire_niO01O0O_dataout); + wire_nl1il1Oli_dataout <= wire_nl1il00lO_dataout WHEN niOi1li0l = '1' ELSE wire_nl1il011O_dataout; + wire_nl1il1Oll_dataout <= wire_nl1il00Oi_dataout WHEN niOi1li0l = '1' ELSE wire_nl1il010i_dataout; + wire_nl1il1OlO_dataout <= nl1il1i1O WHEN niOi1li0l = '1' ELSE wire_nl1il010l_dataout; + wire_nl1il1OOi_dataout <= nl1il1i1O WHEN niOi1li0l = '1' ELSE wire_nl1il010O_dataout; + wire_nl1il1OOl_dataout <= nl1il1i1O WHEN niOi1li0l = '1' ELSE wire_nl1il01ii_dataout; + wire_nl1il1OOO_dataout <= nl1il1i1O WHEN niOi1li0l = '1' ELSE wire_nl1il01il_dataout; + wire_nl1ili00i_dataout <= (NOT wire_nl1iliill_w_lg_w_o_range56062w56066w(0)) AND NOT(niOi1ll1i); + wire_nl1ili01i_dataout <= (((((wire_nl1ilii1i_o AND niOi1liOO) OR (wire_nl1lOOl1i_dataout AND wire_nl1lOOiOO_dataout)) OR (wire_nl1ili0Oi_o AND niOi1liOl)) OR (wire_nl1ili0li_o AND niOi1liOi)) OR niOi1lilO) WHEN niOi1lill = '1' ELSE wire_nl1lOO10O_dataout; + wire_nl1ili01l_dataout <= wire_w_lg_niOi1ll1i56068w(0) OR niOi1ll1l; + wire_nl1ili01O_dataout <= wire_nl1ili00i_dataout OR niOi1ll1l; + wire_nl1ili10i_dataout <= wire_nl1ili1iO_dataout OR NOT(niOi1lili); + wire_nl1ili10l_dataout <= wire_nl1ili1li_dataout OR NOT(niOi1lili); + wire_nl1ili10O_dataout <= wire_nl1ili1ll_dataout OR NOT(niOi1lili); + wire_nl1ili11i_dataout <= wire_nl1ili1Ol_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1ili10l_dataout; + wire_nl1ili11l_dataout <= wire_nl1ili1OO_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1ili10O_dataout; + wire_nl1ili11O_dataout <= wire_nl1ili01i_dataout WHEN wire_nl1lOOlOi_dataout = '1' ELSE wire_nl1ili1ii_dataout; + wire_nl1ili1i_dataout <= wire_nlOi00O0i_dataout WHEN wire_w_lg_niOO1l01O7992w(0) = '1' ELSE nl1il0iO; + wire_nl1ili1ii_dataout <= wire_nl1ili1lO_dataout OR NOT(niOi1lili); + wire_nl1ili1iO_dataout <= wire_nl1lOO1ii_dataout OR niOi1lill; + wire_nl1ili1li_dataout <= wire_nl1ili01l_dataout WHEN niOi1lill = '1' ELSE wire_nl1lOO1il_dataout; + wire_nl1ili1ll_dataout <= wire_nl1ili01O_dataout WHEN niOi1lill = '1' ELSE wire_nl1lOO1iO_dataout; + wire_nl1ili1lO_dataout <= niOi1ll1l WHEN niOi1lill = '1' ELSE wire_nl1lOO1li_dataout; + wire_nl1ili1Oi_dataout <= (niOi1liOi OR niOi1lilO) WHEN niOi1lill = '1' ELSE wire_nl1lOO11O_dataout; + wire_nl1ili1Ol_dataout <= (((wire_nl1ilii1i_o AND niOi1liOi) OR niOi1liOl) OR niOi1lilO) WHEN niOi1lill = '1' ELSE wire_nl1lOO10i_dataout; + wire_nl1ili1OO_dataout <= ((wire_nl1ilii1i_w_lg_w_lg_o56077w56078w(0) OR (wire_nl1ili0Oi_o AND niOi1liOi)) OR niOi1lilO) WHEN niOi1lill = '1' ELSE wire_nl1lOO10l_dataout; + wire_nl1iliilO_dataout <= nl1l0il0i WHEN nl1l1iO0O = '1' ELSE wire_nl1illi1i_dataout; + wire_nl1iliiOi_dataout <= nl1l0il0l WHEN nl1l1iO0O = '1' ELSE wire_nl1illi1l_dataout; + wire_nl1iliiOl_dataout <= nl1l0il0O WHEN nl1l1iO0O = '1' ELSE wire_nl1illi1O_dataout; + wire_nl1iliiOO_dataout <= nl1l0ilii WHEN nl1l1iO0O = '1' ELSE wire_nl1illi0i_dataout; + wire_nl1ilil0i_dataout <= nl1l0illl WHEN nl1l1iO0O = '1' ELSE wire_nl1illiil_dataout; + wire_nl1ilil0l_dataout <= nl1l0illO WHEN nl1l1iO0O = '1' ELSE wire_nl1illiiO_dataout; + wire_nl1ilil0O_dataout <= nl1l0ilOi WHEN nl1l1iO0O = '1' ELSE wire_nl1illili_dataout; + wire_nl1ilil1i_dataout <= nl1l0ilil WHEN nl1l1iO0O = '1' ELSE wire_nl1illi0l_dataout; + wire_nl1ilil1l_dataout <= nl1l0iliO WHEN nl1l1iO0O = '1' ELSE wire_nl1illi0O_dataout; + wire_nl1ilil1O_dataout <= nl1l0illi WHEN nl1l1iO0O = '1' ELSE wire_nl1illiii_dataout; + wire_nl1ililii_dataout <= nl1l0ilOl WHEN nl1l1iO0O = '1' ELSE wire_nl1illill_dataout; + wire_nl1ililil_dataout <= nl1l0ilOO WHEN nl1l1iO0O = '1' ELSE wire_nl1illilO_dataout; + wire_nl1ililiO_dataout <= nl1l0iO1i WHEN nl1l1iO0O = '1' ELSE wire_nl1illiOi_dataout; + wire_nl1ililli_dataout <= nl1l0iO1l WHEN nl1l1iO0O = '1' ELSE wire_nl1illiOl_dataout; + wire_nl1ililll_dataout <= nl1l0iO1O WHEN nl1l1iO0O = '1' ELSE wire_nl1illiOO_dataout; + wire_nl1ilillO_dataout <= nl1l0iO0i WHEN nl1l1iO0O = '1' ELSE wire_nl1illl1i_dataout; + wire_nl1ililOi_dataout <= nl1l0iO0l WHEN nl1l1iO0O = '1' ELSE wire_nl1illl1l_dataout; + wire_nl1ililOl_dataout <= nl1l0iO0O WHEN nl1l1iO0O = '1' ELSE wire_nl1illl1O_dataout; + wire_nl1ililOO_dataout <= nl1l0iOii WHEN nl1l1iO0O = '1' ELSE wire_nl1illl0i_dataout; + wire_nl1iliO0i_dataout <= nl1l0iOll WHEN nl1l1iO0O = '1' ELSE wire_nl1illlil_dataout; + wire_nl1iliO0l_dataout <= nl1l0iOlO WHEN nl1l1iO0O = '1' ELSE wire_nl1illliO_dataout; + wire_nl1iliO0O_dataout <= nl1l0iOOi WHEN nl1l1iO0O = '1' ELSE wire_nl1illlli_dataout; + wire_nl1iliO1i_dataout <= nl1l0iOil WHEN nl1l1iO0O = '1' ELSE wire_nl1illl0l_dataout; + wire_nl1iliO1l_dataout <= nl1l0iOiO WHEN nl1l1iO0O = '1' ELSE wire_nl1illl0O_dataout; + wire_nl1iliO1O_dataout <= nl1l0iOli WHEN nl1l1iO0O = '1' ELSE wire_nl1illlii_dataout; + wire_nl1iliOii_dataout <= nl1l0iOOl WHEN nl1l1iO0O = '1' ELSE wire_nl1illlll_dataout; + wire_nl1iliOil_dataout <= nl1l0iOOO WHEN nl1l1iO0O = '1' ELSE wire_nl1illllO_dataout; + wire_nl1iliOiO_dataout <= nl1l0l11i WHEN nl1l1iO0O = '1' ELSE wire_nl1illlOi_dataout; + wire_nl1iliOli_dataout <= nl1l0l11l WHEN nl1l1iO0O = '1' ELSE wire_nl1illlOl_dataout; + wire_nl1iliOll_dataout <= nl1l0l11O WHEN nl1l1iO0O = '1' ELSE wire_nl1illlOO_dataout; + wire_nl1iliOlO_dataout <= nl1l0l10i WHEN nl1l1iO0O = '1' ELSE wire_nl1illO1i_dataout; + wire_nl1iliOOi_dataout <= nl1l0l10l WHEN nl1l1iO0O = '1' ELSE wire_nl1illO1l_dataout; + wire_nl1iliOOl_dataout <= nl1l0il0i WHEN nl1l1iO0O = '1' ELSE wire_nl1illO1O_dataout; + wire_nl1iliOOO_dataout <= nl1l0il0l WHEN nl1l1iO0O = '1' ELSE wire_nl1illO0i_dataout; + wire_nl1ill00i_dataout <= nl1l0iOiO WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1il_dataout; + wire_nl1ill00l_dataout <= nl1l0iOli WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1iO_dataout; + wire_nl1ill00O_dataout <= nl1l0iOll WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1li_dataout; + wire_nl1ill01i_dataout <= nl1l0iO0O WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO10l_dataout; + wire_nl1ill01l_dataout <= nl1l0iOii WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO10O_dataout; + wire_nl1ill01O_dataout <= nl1l0iOil WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1ii_dataout; + wire_nl1ill0ii_dataout <= nl1l0iOlO WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1ll_dataout; + wire_nl1ill0il_dataout <= nl1l0iOOi WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1lO_dataout; + wire_nl1ill0iO_dataout <= nl1l0iOOl WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1Oi_dataout; + wire_nl1ill0li_dataout <= nl1l0iOOO WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1Ol_dataout; + wire_nl1ill0ll_dataout <= nl1l0l11i WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO1OO_dataout; + wire_nl1ill0lO_dataout <= nl1l0l11l WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO01i_dataout; + wire_nl1ill0Oi_dataout <= nl1l0l11O WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO01l_dataout; + wire_nl1ill0Ol_dataout <= nl1l0l10i WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO01O_dataout; + wire_nl1ill0OO_dataout <= nl1l0l10l WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO00i_dataout; + wire_nl1ill10i_dataout <= nl1l0iliO WHEN nl1l1iO0O = '1' ELSE wire_nl1illOil_dataout; + wire_nl1ill10l_dataout <= nl1l0illi WHEN nl1l1iO0O = '1' ELSE wire_nl1illOiO_dataout; + wire_nl1ill10O_dataout <= nl1l0illl WHEN nl1l1iO0O = '1' ELSE wire_nl1illOli_dataout; + wire_nl1ill11i_dataout <= nl1l0il0O WHEN nl1l1iO0O = '1' ELSE wire_nl1illO0l_dataout; + wire_nl1ill11l_dataout <= nl1l0ilii WHEN nl1l1iO0O = '1' ELSE wire_nl1illO0O_dataout; + wire_nl1ill11O_dataout <= nl1l0ilil WHEN nl1l1iO0O = '1' ELSE wire_nl1illOii_dataout; + wire_nl1ill1ii_dataout <= nl1l0illO WHEN nl1l1iO0O = '1' ELSE wire_nl1illOll_dataout; + wire_nl1ill1il_dataout <= nl1l0ilOi WHEN nl1l1iO0O = '1' ELSE wire_nl1illOlO_dataout; + wire_nl1ill1iO_dataout <= nl1l0ilOl WHEN nl1l1iO0O = '1' ELSE wire_nl1illOOi_dataout; + wire_nl1ill1li_dataout <= nl1l0ilOO WHEN nl1l1iO0O = '1' ELSE wire_nl1illOOl_dataout; + wire_nl1ill1ll_dataout <= nl1l0iO1i WHEN nl1l1iO0O = '1' ELSE wire_nl1illOOO_dataout; + wire_nl1ill1lO_dataout <= nl1l0iO1l WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO11i_dataout; + wire_nl1ill1Oi_dataout <= nl1l0iO1O WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO11l_dataout; + wire_nl1ill1Ol_dataout <= nl1l0iO0i WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO11O_dataout; + wire_nl1ill1OO_dataout <= nl1l0iO0l WHEN nl1l1iO0O = '1' ELSE wire_nl1ilO10i_dataout; + wire_nl1illi0i_dataout <= nl1l0lill WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0il_dataout; + wire_nl1illi0l_dataout <= nl1l0lilO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0iO_dataout; + wire_nl1illi0O_dataout <= nl1l0liOi WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0li_dataout; + wire_nl1illi1i_dataout <= nl1l0liil WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO00l_dataout; + wire_nl1illi1l_dataout <= nl1l0liiO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO00O_dataout; + wire_nl1illi1O_dataout <= nl1l0lili WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0ii_dataout; + wire_nl1illiii_dataout <= nl1l0liOl WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0ll_dataout; + wire_nl1illiil_dataout <= nl1l0liOO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0lO_dataout; + wire_nl1illiiO_dataout <= nl1l0ll1i WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0Oi_dataout; + wire_nl1illili_dataout <= nl1l0ll1l WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0Ol_dataout; + wire_nl1illill_dataout <= nl1l0ll1O WHEN nl1l1iO0l = '1' ELSE wire_nl1ilO0OO_dataout; + wire_nl1illilO_dataout <= nl1l0ll0i WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOi1i_dataout; + wire_nl1illiOi_dataout <= nl1l0ll0l WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOi1l_dataout; + wire_nl1illiOl_dataout <= nl1l0ll0O WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOi1O_dataout; + wire_nl1illiOO_dataout <= nl1l0llii WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOi0i_dataout; + wire_nl1illl_dataout <= nl11lOi OR niOO0O10O; + wire_nl1illl0i_dataout <= nl1l0llll WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOiil_dataout; + wire_nl1illl0l_dataout <= nl1l0lllO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOiiO_dataout; + wire_nl1illl0O_dataout <= nl1l0llOi WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOili_dataout; + wire_nl1illl1i_dataout <= nl1l0llil WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOi0l_dataout; + wire_nl1illl1l_dataout <= nl1l0lliO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOi0O_dataout; + wire_nl1illl1O_dataout <= nl1l0llli WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOiii_dataout; + wire_nl1illlii_dataout <= nl1l0llOl WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOill_dataout; + wire_nl1illlil_dataout <= nl1l0llOO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOilO_dataout; + wire_nl1illliO_dataout <= nl1l0lO1i WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOiOi_dataout; + wire_nl1illlli_dataout <= nl1l0lO1l WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOiOl_dataout; + wire_nl1illlll_dataout <= nl1l0lO1O WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOiOO_dataout; + wire_nl1illllO_dataout <= nl1l0lO0i WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOl1i_dataout; + wire_nl1illlOi_dataout <= nl1l0lO0l WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOl1l_dataout; + wire_nl1illlOl_dataout <= nl1l0lO0O WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOl1O_dataout; + wire_nl1illlOO_dataout <= nl1l0lOii WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOl0i_dataout; + wire_nl1illO_dataout <= nl11ilO OR niOO0O10O; + wire_nl1illO0i_dataout <= nl1l0liiO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOlil_dataout; + wire_nl1illO0l_dataout <= nl1l0lili WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOliO_dataout; + wire_nl1illO0O_dataout <= nl1l0lill WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOlli_dataout; + wire_nl1illO1i_dataout <= nl1l0lOil WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOl0l_dataout; + wire_nl1illO1l_dataout <= nl1l0lOiO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOl0O_dataout; + wire_nl1illO1O_dataout <= nl1l0liil WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOlii_dataout; + wire_nl1illOii_dataout <= nl1l0lilO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOlll_dataout; + wire_nl1illOil_dataout <= nl1l0liOi WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOllO_dataout; + wire_nl1illOiO_dataout <= nl1l0liOl WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOlOi_dataout; + wire_nl1illOli_dataout <= nl1l0liOO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOlOl_dataout; + wire_nl1illOll_dataout <= nl1l0ll1i WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOlOO_dataout; + wire_nl1illOlO_dataout <= nl1l0ll1l WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOO1i_dataout; + wire_nl1illOO_dataout <= wire_nl1ilOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1illOOi_dataout <= nl1l0ll1O WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOO1l_dataout; + wire_nl1illOOl_dataout <= nl1l0ll0i WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOO1O_dataout; + wire_nl1illOOO_dataout <= nl1l0ll0l WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOO0i_dataout; + wire_nl1ilO00i_dataout <= nl1l0lOiO WHEN nl1l1iO0l = '1' ELSE wire_nl1iO11il_dataout; + wire_nl1ilO00l_dataout <= nl1l0l10O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO11iO_dataout; + wire_nl1ilO00O_dataout <= nl1l0l1ii WHEN nl1l1iO0i = '1' ELSE wire_nl1iO11li_dataout; + wire_nl1ilO01i_dataout <= nl1l0lO0O WHEN nl1l1iO0l = '1' ELSE wire_nl1iO110l_dataout; + wire_nl1ilO01l_dataout <= nl1l0lOii WHEN nl1l1iO0l = '1' ELSE wire_nl1iO110O_dataout; + wire_nl1ilO01O_dataout <= nl1l0lOil WHEN nl1l1iO0l = '1' ELSE wire_nl1iO11ii_dataout; + wire_nl1ilO0i_dataout <= wire_nl1iO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilO0ii_dataout <= nl1l0l1il WHEN nl1l1iO0i = '1' ELSE wire_nl1iO11ll_dataout; + wire_nl1ilO0il_dataout <= nl1l0l1iO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO11lO_dataout; + wire_nl1ilO0iO_dataout <= nl1l0l1li WHEN nl1l1iO0i = '1' ELSE wire_nl1iO11Oi_dataout; + wire_nl1ilO0l_dataout <= wire_nl1iO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilO0li_dataout <= nl1l0l1ll WHEN nl1l1iO0i = '1' ELSE wire_nl1iO11Ol_dataout; + wire_nl1ilO0ll_dataout <= nl1l0l1lO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO11OO_dataout; + wire_nl1ilO0lO_dataout <= nl1l0l1Oi WHEN nl1l1iO0i = '1' ELSE wire_nl1iO101i_dataout; + wire_nl1ilO0O_dataout <= wire_nl1iO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilO0Oi_dataout <= nl1l0l1Ol WHEN nl1l1iO0i = '1' ELSE wire_nl1iO101l_dataout; + wire_nl1ilO0Ol_dataout <= nl1l0l1OO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO101O_dataout; + wire_nl1ilO0OO_dataout <= nl1l0l01i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO100i_dataout; + wire_nl1ilO10i_dataout <= nl1l0lliO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOil_dataout; + wire_nl1ilO10l_dataout <= nl1l0llli WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOiO_dataout; + wire_nl1ilO10O_dataout <= nl1l0llll WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOli_dataout; + wire_nl1ilO11i_dataout <= nl1l0ll0O WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOO0l_dataout; + wire_nl1ilO11l_dataout <= nl1l0llii WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOO0O_dataout; + wire_nl1ilO11O_dataout <= nl1l0llil WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOii_dataout; + wire_nl1ilO1i_dataout <= wire_nl1ilOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilO1ii_dataout <= nl1l0lllO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOll_dataout; + wire_nl1ilO1il_dataout <= nl1l0llOi WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOlO_dataout; + wire_nl1ilO1iO_dataout <= nl1l0llOl WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOOi_dataout; + wire_nl1ilO1l_dataout <= wire_nl1ilOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilO1li_dataout <= nl1l0llOO WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOOl_dataout; + wire_nl1ilO1ll_dataout <= nl1l0lO1i WHEN nl1l1iO0l = '1' ELSE wire_nl1ilOOOO_dataout; + wire_nl1ilO1lO_dataout <= nl1l0lO1l WHEN nl1l1iO0l = '1' ELSE wire_nl1iO111i_dataout; + wire_nl1ilO1O_dataout <= wire_nl1iO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilO1Oi_dataout <= nl1l0lO1O WHEN nl1l1iO0l = '1' ELSE wire_nl1iO111l_dataout; + wire_nl1ilO1Ol_dataout <= nl1l0lO0i WHEN nl1l1iO0l = '1' ELSE wire_nl1iO111O_dataout; + wire_nl1ilO1OO_dataout <= nl1l0lO0l WHEN nl1l1iO0l = '1' ELSE wire_nl1iO110i_dataout; + wire_nl1ilOi_dataout <= nl11iOi OR niOO0O10O; + wire_nl1ilOi0i_dataout <= nl1l0l00l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10il_dataout; + wire_nl1ilOi0l_dataout <= nl1l0l00O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10iO_dataout; + wire_nl1ilOi0O_dataout <= nl1l0l0ii WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10li_dataout; + wire_nl1ilOi1i_dataout <= nl1l0l01l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO100l_dataout; + wire_nl1ilOi1l_dataout <= nl1l0l01O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO100O_dataout; + wire_nl1ilOi1O_dataout <= nl1l0l00i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10ii_dataout; + wire_nl1ilOii_dataout <= wire_nl1iO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilOiii_dataout <= nl1l0l0il WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10ll_dataout; + wire_nl1ilOiil_dataout <= nl1l0l0iO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10lO_dataout; + wire_nl1ilOiiO_dataout <= nl1l0l0li WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10Oi_dataout; + wire_nl1ilOil_dataout <= wire_nl1iO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilOili_dataout <= nl1l0l0ll WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10Ol_dataout; + wire_nl1ilOill_dataout <= nl1l0l0lO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO10OO_dataout; + wire_nl1ilOilO_dataout <= nl1l0l0Oi WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1i1i_dataout; + wire_nl1ilOiO_dataout <= wire_nl1iO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilOiOi_dataout <= nl1l0l0Ol WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1i1l_dataout; + wire_nl1ilOiOl_dataout <= nl1l0l0OO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1i1O_dataout; + wire_nl1ilOiOO_dataout <= nl1l0li1i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1i0i_dataout; + wire_nl1ilOl_dataout <= nl11iOl OR niOO0O10O; + wire_nl1ilOl0i_dataout <= nl1l0li0l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1iil_dataout; + wire_nl1ilOl0l_dataout <= nl1l0li0O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1iiO_dataout; + wire_nl1ilOl0O_dataout <= nl1l0liii WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1ili_dataout; + wire_nl1ilOl1i_dataout <= nl1l0li1l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1i0l_dataout; + wire_nl1ilOl1l_dataout <= nl1l0li1O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1i0O_dataout; + wire_nl1ilOl1O_dataout <= nl1l0li0i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1iii_dataout; + wire_nl1ilOli_dataout <= wire_nl1iO1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilOlii_dataout <= nl1l0liil WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1ill_dataout; + wire_nl1ilOlil_dataout <= nl1l0liiO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1ilO_dataout; + wire_nl1ilOliO_dataout <= nl1l0lili WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1iOi_dataout; + wire_nl1ilOll_dataout <= wire_nl1iO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilOlli_dataout <= nl1l0lill WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1iOl_dataout; + wire_nl1ilOlll_dataout <= nl1l0lilO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1iOO_dataout; + wire_nl1ilOllO_dataout <= nl1l0liOi WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1l1i_dataout; + wire_nl1ilOlO_dataout <= wire_nl1iO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ilOlOi_dataout <= nl1l0liOl WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1l1l_dataout; + wire_nl1ilOlOl_dataout <= nl1l0liOO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1l1O_dataout; + wire_nl1ilOlOO_dataout <= nl1l0ll1i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1l0i_dataout; + wire_nl1ilOO_dataout <= nl11iOO OR niOO0O10O; + wire_nl1ilOO0i_dataout <= nl1l0ll0l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1lil_dataout; + wire_nl1ilOO0l_dataout <= nl1l0ll0O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1liO_dataout; + wire_nl1ilOO0O_dataout <= nl1l0llii WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1lli_dataout; + wire_nl1ilOO1i_dataout <= nl1l0ll1l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1l0l_dataout; + wire_nl1ilOO1l_dataout <= nl1l0ll1O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1l0O_dataout; + wire_nl1ilOO1O_dataout <= nl1l0ll0i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1lii_dataout; + wire_nl1ilOOi_dataout <= nl1iO0il WHEN niOO1l00i = '1' ELSE nl1iO1lO; + wire_nl1ilOOii_dataout <= nl1l0llil WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1lll_dataout; + wire_nl1ilOOil_dataout <= nl1l0lliO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1llO_dataout; + wire_nl1ilOOiO_dataout <= nl1l0llli WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1lOi_dataout; + wire_nl1ilOOl_dataout <= nl1iO0iO WHEN niOO1l00i = '1' ELSE nl1ill1l; + wire_nl1ilOOli_dataout <= nl1l0llll WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1lOl_dataout; + wire_nl1ilOOll_dataout <= nl1l0lllO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1lOO_dataout; + wire_nl1ilOOlO_dataout <= nl1l0llOi WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1O1i_dataout; + wire_nl1ilOOO_dataout <= nl1iO0li WHEN niOO1l00i = '1' ELSE nl1ill1O; + wire_nl1ilOOOi_dataout <= nl1l0llOl WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1O1l_dataout; + wire_nl1ilOOOl_dataout <= nl1l0llOO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1O1O_dataout; + wire_nl1ilOOOO_dataout <= nl1l0lO1i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1O0i_dataout; + wire_nl1iO000i_dataout <= nl1l00l0i WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1il_dataout; + wire_nl1iO000l_dataout <= nl1l00l0l WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1iO_dataout; + wire_nl1iO000O_dataout <= nl1l00l0O WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1li_dataout; + wire_nl1iO001i_dataout <= nl1l00l1i WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi10l_dataout; + wire_nl1iO001l_dataout <= nl1l00l1l WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi10O_dataout; + wire_nl1iO001O_dataout <= nl1l00l1O WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1ii_dataout; + wire_nl1iO00ii_dataout <= nl1l00lii WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1ll_dataout; + wire_nl1iO00il_dataout <= nl1l00lil WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1lO_dataout; + wire_nl1iO00iO_dataout <= nl1l00liO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1Oi_dataout; + wire_nl1iO00li_dataout <= nl1l00lli WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1Ol_dataout; + wire_nl1iO00ll_dataout <= nl1l00lll WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi1OO_dataout; + wire_nl1iO00lO_dataout <= nl1l00llO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi01i_dataout; + wire_nl1iO00O_dataout <= nl1iO00i AND NOT(wire_niO01O0O_dataout); + wire_nl1iO00Oi_dataout <= nl1l00lOi WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi01l_dataout; + wire_nl1iO00Ol_dataout <= nl1l00lOl WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi01O_dataout; + wire_nl1iO00OO_dataout <= nl1l00lOO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi00i_dataout; + wire_nl1iO010i_dataout <= nl1l00i0i WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0Oil_dataout; + wire_nl1iO010l_dataout <= nl1l00i0l WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0OiO_dataout; + wire_nl1iO010O_dataout <= nl1l00i0O WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0Oli_dataout; + wire_nl1iO011i_dataout <= nl1l00i1i WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0O0l_dataout; + wire_nl1iO011l_dataout <= nl1l00i1l WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0O0O_dataout; + wire_nl1iO011O_dataout <= nl1l00i1O WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0Oii_dataout; + wire_nl1iO01i_dataout <= nl1illOl AND NOT(wire_niO01l0O_dataout); + wire_nl1iO01ii_dataout <= nl1l00iii WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0Oll_dataout; + wire_nl1iO01il_dataout <= nl1l00iil WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0OlO_dataout; + wire_nl1iO01iO_dataout <= nl1l00iiO WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0OOi_dataout; + wire_nl1iO01li_dataout <= nl1l00ili WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0OOl_dataout; + wire_nl1iO01ll_dataout <= nl1l00ill WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0OOO_dataout; + wire_nl1iO01lO_dataout <= nl1l00ilO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi11i_dataout; + wire_nl1iO01O_dataout <= nl1iO00l AND NOT(wire_niO01O0O_dataout); + wire_nl1iO01Oi_dataout <= nl1l00iOi WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi11l_dataout; + wire_nl1iO01Ol_dataout <= nl1l00iOl WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi11O_dataout; + wire_nl1iO01OO_dataout <= nl1l00iOO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi10i_dataout; + wire_nl1iO0i_dataout <= nl11l0i OR niOO0O10O; + wire_nl1iO0i0i_dataout <= nl1l00O0i WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0il_dataout; + wire_nl1iO0i0l_dataout <= nl1l00O0l WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0iO_dataout; + wire_nl1iO0i0O_dataout <= nl1l00O0O WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0li_dataout; + wire_nl1iO0i1i_dataout <= nl1l00O1i WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi00l_dataout; + wire_nl1iO0i1l_dataout <= nl1l00O1l WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi00O_dataout; + wire_nl1iO0i1O_dataout <= nl1l00O1O WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0ii_dataout; + wire_nl1iO0ii_dataout <= nl1iO1OO AND NOT(wire_niO01O0O_dataout); + wire_nl1iO0iii_dataout <= nl1l00Oii WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0ll_dataout; + wire_nl1iO0iil_dataout <= nl1l00Oil WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0lO_dataout; + wire_nl1iO0iiO_dataout <= nl1l00OiO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0Oi_dataout; + wire_nl1iO0ili_dataout <= nl1l00Oli WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0Ol_dataout; + wire_nl1iO0ill_dataout <= nl1l00Oll WHEN nl1l1iO1l = '1' ELSE wire_nl1iOi0OO_dataout; + wire_nl1iO0ilO_dataout <= nl1l00OlO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOii1i_dataout; + wire_nl1iO0iOi_dataout <= nl1l00OOi WHEN nl1l1iO1l = '1' ELSE wire_nl1iOii1l_dataout; + wire_nl1iO0iOl_dataout <= nl1l00OOl WHEN nl1l1iO1l = '1' ELSE wire_nl1iOii1O_dataout; + wire_nl1iO0iOO_dataout <= nl1l00OOO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOii0i_dataout; + wire_nl1iO0l_dataout <= nl11l0l OR niOO0O10O; + wire_nl1iO0l0i_dataout <= nl1l0i10i WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiiil_dataout; + wire_nl1iO0l0l_dataout <= nl1l0i10l WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiiiO_dataout; + wire_nl1iO0l0O_dataout <= nl1l0i10O WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiili_dataout; + wire_nl1iO0l1i_dataout <= nl1l0i11i WHEN nl1l1iO1l = '1' ELSE wire_nl1iOii0l_dataout; + wire_nl1iO0l1l_dataout <= nl1l0i11l WHEN nl1l1iO1l = '1' ELSE wire_nl1iOii0O_dataout; + wire_nl1iO0l1O_dataout <= nl1l0i11O WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiiii_dataout; + wire_nl1iO0lii_dataout <= nl1l0i1ii WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiill_dataout; + wire_nl1iO0lil_dataout <= nl1l0i1il WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiilO_dataout; + wire_nl1iO0liO_dataout <= nl1l0i1iO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiiOi_dataout; + wire_nl1iO0lli_dataout <= nl1l0i1li WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiiOl_dataout; + wire_nl1iO0lll_dataout <= nl1l0i1ll WHEN nl1l1iO1l = '1' ELSE wire_nl1iOiiOO_dataout; + wire_nl1iO0llO_dataout <= nl1l0i1lO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOil1i_dataout; + wire_nl1iO0lOi_dataout <= nl1l0i1Oi WHEN nl1l1iO1l = '1' ELSE wire_nl1iOil1l_dataout; + wire_nl1iO0lOl_dataout <= nl1l0i1Ol WHEN nl1l1iO1l = '1' ELSE wire_nl1iOil1O_dataout; + wire_nl1iO0lOO_dataout <= nl1l0i1OO WHEN nl1l1iO1l = '1' ELSE wire_nl1iOil0i_dataout; + wire_nl1iO0O_dataout <= nl11l0O OR niOO0O10O; + wire_nl1iO0O0i_dataout <= nl1l00O1l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOilil_dataout; + wire_nl1iO0O0l_dataout <= nl1l00O1O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiliO_dataout; + wire_nl1iO0O0O_dataout <= nl1l00O0i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOilli_dataout; + wire_nl1iO0O1i_dataout <= nl1l0i01i WHEN nl1l1iO1l = '1' ELSE wire_nl1iOil0l_dataout; + wire_nl1iO0O1l_dataout <= nl1l00lOO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOil0O_dataout; + wire_nl1iO0O1O_dataout <= nl1l00O1i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOilii_dataout; + wire_nl1iO0Oii_dataout <= nl1l00O0l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOilll_dataout; + wire_nl1iO0Oil_dataout <= nl1l00O0O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOillO_dataout; + wire_nl1iO0OiO_dataout <= nl1l00Oii WHEN nl1l1iO1i = '1' ELSE wire_nl1iOilOi_dataout; + wire_nl1iO0Oli_dataout <= nl1l00Oil WHEN nl1l1iO1i = '1' ELSE wire_nl1iOilOl_dataout; + wire_nl1iO0Oll_dataout <= nl1l00OiO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOilOO_dataout; + wire_nl1iO0OlO_dataout <= nl1l00Oli WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiO1i_dataout; + wire_nl1iO0OOi_dataout <= nl1l00Oll WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiO1l_dataout; + wire_nl1iO0OOl_dataout <= nl1l00OlO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiO1O_dataout; + wire_nl1iO0OOO_dataout <= nl1l00OOi WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiO0i_dataout; + wire_nl1iO100i_dataout <= nl1l00iil WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01il_dataout; + wire_nl1iO100l_dataout <= nl1l00iiO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01iO_dataout; + wire_nl1iO100O_dataout <= nl1l00ili WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01li_dataout; + wire_nl1iO101i_dataout <= nl1l00i0l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO010l_dataout; + wire_nl1iO101l_dataout <= nl1l00i0O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO010O_dataout; + wire_nl1iO101O_dataout <= nl1l00iii WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01ii_dataout; + wire_nl1iO10i_dataout <= nl1iO0Ol WHEN niOO1l00i = '1' ELSE nl1illii; + wire_nl1iO10ii_dataout <= nl1l00ill WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01ll_dataout; + wire_nl1iO10il_dataout <= nl1l00ilO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01lO_dataout; + wire_nl1iO10iO_dataout <= nl1l00iOi WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01Oi_dataout; + wire_nl1iO10l_dataout <= nl1iO0OO WHEN niOO1l00i = '1' ELSE nl1illil; + wire_nl1iO10li_dataout <= nl1l00iOl WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01Ol_dataout; + wire_nl1iO10ll_dataout <= nl1l00iOO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO01OO_dataout; + wire_nl1iO10lO_dataout <= nl1l00l1i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO001i_dataout; + wire_nl1iO10O_dataout <= nl1iOi1i WHEN niOO1l00i = '1' ELSE nl1illiO; + wire_nl1iO10Oi_dataout <= nl1l00l1l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO001l_dataout; + wire_nl1iO10Ol_dataout <= nl1l00l1O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO001O_dataout; + wire_nl1iO10OO_dataout <= nl1l00l0i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO000i_dataout; + wire_nl1iO110i_dataout <= nl1l0lO0l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1Oil_dataout; + wire_nl1iO110l_dataout <= nl1l0lO0O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1OiO_dataout; + wire_nl1iO110O_dataout <= nl1l0lOii WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1Oli_dataout; + wire_nl1iO111i_dataout <= nl1l0lO1l WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1O0l_dataout; + wire_nl1iO111l_dataout <= nl1l0lO1O WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1O0O_dataout; + wire_nl1iO111O_dataout <= nl1l0lO0i WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1Oii_dataout; + wire_nl1iO11i_dataout <= nl1iO0ll WHEN niOO1l00i = '1' ELSE nl1ill0i; + wire_nl1iO11ii_dataout <= nl1l0lOil WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1Oll_dataout; + wire_nl1iO11il_dataout <= nl1l0lOiO WHEN nl1l1iO0i = '1' ELSE wire_nl1iO1OlO_dataout; + wire_nl1iO11iO_dataout <= nl1l000Oi WHEN nl1l1iO1O = '1' ELSE wire_nl1iO1OOi_dataout; + wire_nl1iO11l_dataout <= nl1iO0lO WHEN niOO1l00i = '1' ELSE nl1ill0l; + wire_nl1iO11li_dataout <= nl1l000Ol WHEN nl1l1iO1O = '1' ELSE wire_nl1iO1OOl_dataout; + wire_nl1iO11ll_dataout <= nl1l000OO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO1OOO_dataout; + wire_nl1iO11lO_dataout <= nl1l00i1i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO011i_dataout; + wire_nl1iO11O_dataout <= nl1iO0Oi WHEN niOO1l00i = '1' ELSE nl1ill0O; + wire_nl1iO11Oi_dataout <= nl1l00i1l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO011l_dataout; + wire_nl1iO11Ol_dataout <= nl1l00i1O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO011O_dataout; + wire_nl1iO11OO_dataout <= nl1l00i0i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO010i_dataout; + wire_nl1iO1i_dataout <= nl11l1i OR niOO0O10O; + wire_nl1iO1i0i_dataout <= nl1l00lil WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00il_dataout; + wire_nl1iO1i0l_dataout <= nl1l00liO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00iO_dataout; + wire_nl1iO1i0O_dataout <= nl1l00lli WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00li_dataout; + wire_nl1iO1i1i_dataout <= nl1l00l0l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO000l_dataout; + wire_nl1iO1i1l_dataout <= nl1l00l0O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO000O_dataout; + wire_nl1iO1i1O_dataout <= nl1l00lii WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00ii_dataout; + wire_nl1iO1ii_dataout <= nl1iOi1l WHEN niOO1l00i = '1' ELSE nl1illli; + wire_nl1iO1iii_dataout <= nl1l00lll WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00ll_dataout; + wire_nl1iO1iil_dataout <= nl1l00llO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00lO_dataout; + wire_nl1iO1iiO_dataout <= nl1l00lOi WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00Oi_dataout; + wire_nl1iO1il_dataout <= nl1iOi1O WHEN niOO1l00i = '1' ELSE nl1illll; + wire_nl1iO1ili_dataout <= nl1l00lOl WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00Ol_dataout; + wire_nl1iO1ill_dataout <= nl1l0l10O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO00OO_dataout; + wire_nl1iO1ilO_dataout <= nl1l0l1ii WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0i1i_dataout; + wire_nl1iO1iO_dataout <= nl1iOi0i WHEN niOO1l00i = '1' ELSE nl1illlO; + wire_nl1iO1iOi_dataout <= nl1l0l1il WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0i1l_dataout; + wire_nl1iO1iOl_dataout <= nl1l0l1iO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0i1O_dataout; + wire_nl1iO1iOO_dataout <= nl1l0l1li WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0i0i_dataout; + wire_nl1iO1l_dataout <= nl11l1l OR niOO0O10O; + wire_nl1iO1l0i_dataout <= nl1l0l1Ol WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0iil_dataout; + wire_nl1iO1l0l_dataout <= nl1l0l1OO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0iiO_dataout; + wire_nl1iO1l0O_dataout <= nl1l0l01i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0ili_dataout; + wire_nl1iO1l1i_dataout <= nl1l0l1ll WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0i0l_dataout; + wire_nl1iO1l1l_dataout <= nl1l0l1lO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0i0O_dataout; + wire_nl1iO1l1O_dataout <= nl1l0l1Oi WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0iii_dataout; + wire_nl1iO1li_dataout <= nl1iOi0l WHEN niOO1l00i = '1' ELSE nl1illOi; + wire_nl1iO1lii_dataout <= nl1l0l01l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0ill_dataout; + wire_nl1iO1lil_dataout <= nl1l0l01O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0ilO_dataout; + wire_nl1iO1liO_dataout <= nl1l0l00i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0iOi_dataout; + wire_nl1iO1lli_dataout <= nl1l0l00l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0iOl_dataout; + wire_nl1iO1lll_dataout <= nl1l0l00O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0iOO_dataout; + wire_nl1iO1llO_dataout <= nl1l0l0ii WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0l1i_dataout; + wire_nl1iO1lOi_dataout <= nl1l0l0il WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0l1l_dataout; + wire_nl1iO1lOl_dataout <= nl1l0l0iO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0l1O_dataout; + wire_nl1iO1lOO_dataout <= nl1l0l0li WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0l0i_dataout; + wire_nl1iO1O_dataout <= nl11l1O OR niOO0O10O; + wire_nl1iO1O0i_dataout <= nl1l0l0Ol WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0lil_dataout; + wire_nl1iO1O0l_dataout <= nl1l0l0OO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0liO_dataout; + wire_nl1iO1O0O_dataout <= nl1l0li1i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0lli_dataout; + wire_nl1iO1O1i_dataout <= nl1l0l0ll WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0l0l_dataout; + wire_nl1iO1O1l_dataout <= nl1l0l0lO WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0l0O_dataout; + wire_nl1iO1O1O_dataout <= nl1l0l0Oi WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0lii_dataout; + wire_nl1iO1Oii_dataout <= nl1l0li1l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0lll_dataout; + wire_nl1iO1Oil_dataout <= nl1l0li1O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0llO_dataout; + wire_nl1iO1OiO_dataout <= nl1l0li0i WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0lOi_dataout; + wire_nl1iO1Ol_dataout <= nl1iO01l AND NOT(wire_niO01l0O_dataout); + wire_nl1iO1Oli_dataout <= nl1l0li0l WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0lOl_dataout; + wire_nl1iO1Oll_dataout <= nl1l0li0O WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0lOO_dataout; + wire_nl1iO1OlO_dataout <= nl1l0liii WHEN nl1l1iO1O = '1' ELSE wire_nl1iO0O1i_dataout; + wire_nl1iO1OOi_dataout <= nl1l000Oi WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0O1l_dataout; + wire_nl1iO1OOl_dataout <= nl1l000Ol WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0O1O_dataout; + wire_nl1iO1OOO_dataout <= nl1l000OO WHEN nl1l1iO1l = '1' ELSE wire_nl1iO0O0i_dataout; + wire_nl1iOi00i_dataout <= nl1l0i01l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1il_dataout; + wire_nl1iOi00l_dataout <= nl1l0i01O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1iO_dataout; + wire_nl1iOi00O_dataout <= nl1l0i00i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1li_dataout; + wire_nl1iOi01i_dataout <= nl1l0i1Ol WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl10l_dataout; + wire_nl1iOi01l_dataout <= nl1l0i1OO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl10O_dataout; + wire_nl1iOi01O_dataout <= nl1l0i01i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1ii_dataout; + wire_nl1iOi0ii_dataout <= nl1l0i00l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1ll_dataout; + wire_nl1iOi0il_dataout <= nl1l0i00O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1lO_dataout; + wire_nl1iOi0iO_dataout <= nl1l0i0ii WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1Oi_dataout; + wire_nl1iOi0li_dataout <= nl1l0i0il WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1Ol_dataout; + wire_nl1iOi0ll_dataout <= nl1l0i0iO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl1OO_dataout; + wire_nl1iOi0lO_dataout <= nl1l0i0li WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl01i_dataout; + wire_nl1iOi0O_dataout <= wire_nl1iOl0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOi0Oi_dataout <= nl1l0i0ll WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl01l_dataout; + wire_nl1iOi0Ol_dataout <= nl1l0i0lO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl01O_dataout; + wire_nl1iOi0OO_dataout <= nl1l0i0Oi WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl00i_dataout; + wire_nl1iOi10i_dataout <= nl1l0i11l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOil_dataout; + wire_nl1iOi10l_dataout <= nl1l0i11O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOiO_dataout; + wire_nl1iOi10O_dataout <= nl1l0i10i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOli_dataout; + wire_nl1iOi11i_dataout <= nl1l00OOl WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiO0l_dataout; + wire_nl1iOi11l_dataout <= nl1l00OOO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiO0O_dataout; + wire_nl1iOi11O_dataout <= nl1l0i11i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOii_dataout; + wire_nl1iOi1ii_dataout <= nl1l0i10l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOll_dataout; + wire_nl1iOi1il_dataout <= nl1l0i10O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOlO_dataout; + wire_nl1iOi1iO_dataout <= nl1l0i1ii WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOOi_dataout; + wire_nl1iOi1li_dataout <= nl1l0i1il WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOOl_dataout; + wire_nl1iOi1ll_dataout <= nl1l0i1iO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOiOOO_dataout; + wire_nl1iOi1lO_dataout <= nl1l0i1li WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl11i_dataout; + wire_nl1iOi1Oi_dataout <= nl1l0i1ll WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl11l_dataout; + wire_nl1iOi1Ol_dataout <= nl1l0i1lO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl11O_dataout; + wire_nl1iOi1OO_dataout <= nl1l0i1Oi WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl10i_dataout; + wire_nl1iOii_dataout <= nl11lii OR niOO0O10O; + wire_nl1iOii0i_dataout <= nl1l0ii1l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0il_dataout; + wire_nl1iOii0l_dataout <= nl1l0ii1O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0iO_dataout; + wire_nl1iOii0O_dataout <= nl1l0ii0i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0li_dataout; + wire_nl1iOii1i_dataout <= nl1l0i0Ol WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl00l_dataout; + wire_nl1iOii1l_dataout <= nl1l0i0OO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl00O_dataout; + wire_nl1iOii1O_dataout <= nl1l0ii1i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0ii_dataout; + wire_nl1iOiii_dataout <= wire_nl1iOlii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOiiii_dataout <= nl1l0ii0l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0ll_dataout; + wire_nl1iOiiil_dataout <= nl1l0ii0O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0lO_dataout; + wire_nl1iOiiiO_dataout <= nl1l0iiii WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0Oi_dataout; + wire_nl1iOiil_dataout <= wire_nl1iOlil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOiili_dataout <= nl1l0iiil WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0Ol_dataout; + wire_nl1iOiill_dataout <= nl1l0iiiO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOl0OO_dataout; + wire_nl1iOiilO_dataout <= nl1l0iili WHEN nl1l1iO1i = '1' ELSE wire_nl1iOli1i_dataout; + wire_nl1iOiiO_dataout <= wire_nl1iOliO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOiiOi_dataout <= nl1l0iill WHEN nl1l1iO1i = '1' ELSE wire_nl1iOli1l_dataout; + wire_nl1iOiiOl_dataout <= nl1l0iilO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOli1O_dataout; + wire_nl1iOiiOO_dataout <= nl1l0iiOi WHEN nl1l1iO1i = '1' ELSE wire_nl1iOli0i_dataout; + wire_nl1iOil_dataout <= nl11lil OR niOO0O10O; + wire_nl1iOil0i_dataout <= nl1l0il1l WHEN nl1l1iO1i = '1' ELSE wire_nl1iOliil_dataout; + wire_nl1iOil0l_dataout <= nl1l0il1O WHEN nl1l1iO1i = '1' ELSE wire_nl1iOliiO_dataout; + wire_nl1iOil0O_dataout <= nl1l011ii WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlili_dataout; + wire_nl1iOil1i_dataout <= nl1l0iiOl WHEN nl1l1iO1i = '1' ELSE wire_nl1iOli0l_dataout; + wire_nl1iOil1l_dataout <= nl1l0iiOO WHEN nl1l1iO1i = '1' ELSE wire_nl1iOli0O_dataout; + wire_nl1iOil1O_dataout <= nl1l0il1i WHEN nl1l1iO1i = '1' ELSE wire_nl1iOliii_dataout; + wire_nl1iOili_dataout <= wire_nl1iOlli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOilii_dataout <= nl1l011il WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlill_dataout; + wire_nl1iOilil_dataout <= nl1l011iO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlilO_dataout; + wire_nl1iOiliO_dataout <= nl1l011li WHEN nl1l1ilOO = '1' ELSE wire_nl1iOliOi_dataout; + wire_nl1iOill_dataout <= wire_nl1iOlll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOilli_dataout <= nl1l011ll WHEN nl1l1ilOO = '1' ELSE wire_nl1iOliOl_dataout; + wire_nl1iOilll_dataout <= nl1l011lO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOliOO_dataout; + wire_nl1iOillO_dataout <= nl1l011Oi WHEN nl1l1ilOO = '1' ELSE wire_nl1iOll1i_dataout; + wire_nl1iOilO_dataout <= wire_nl1iOllO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOilOi_dataout <= nl1l011Ol WHEN nl1l1ilOO = '1' ELSE wire_nl1iOll1l_dataout; + wire_nl1iOilOl_dataout <= nl1l011OO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOll1O_dataout; + wire_nl1iOilOO_dataout <= nl1l0101i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOll0i_dataout; + wire_nl1iOiO_dataout <= nl11liO OR niOO0O10O; + wire_nl1iOiO0i_dataout <= nl1l0100l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOllil_dataout; + wire_nl1iOiO0l_dataout <= nl1l0100O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlliO_dataout; + wire_nl1iOiO0O_dataout <= nl1l010ii WHEN nl1l1ilOO = '1' ELSE wire_nl1iOllli_dataout; + wire_nl1iOiO1i_dataout <= nl1l0101l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOll0l_dataout; + wire_nl1iOiO1l_dataout <= nl1l0101O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOll0O_dataout; + wire_nl1iOiO1O_dataout <= nl1l0100i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOllii_dataout; + wire_nl1iOiOi_dataout <= wire_nl1iOlOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOiOii_dataout <= nl1l010il WHEN nl1l1ilOO = '1' ELSE wire_nl1iOllll_dataout; + wire_nl1iOiOil_dataout <= nl1l010iO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlllO_dataout; + wire_nl1iOiOiO_dataout <= nl1l010li WHEN nl1l1ilOO = '1' ELSE wire_nl1iOllOi_dataout; + wire_nl1iOiOl_dataout <= wire_nl1iOlOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOiOli_dataout <= nl1l010ll WHEN nl1l1ilOO = '1' ELSE wire_nl1iOllOl_dataout; + wire_nl1iOiOll_dataout <= nl1l010lO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOllOO_dataout; + wire_nl1iOiOlO_dataout <= nl1l010Oi WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlO1i_dataout; + wire_nl1iOiOO_dataout <= wire_nl1iOlOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOiOOi_dataout <= nl1l010Ol WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlO1l_dataout; + wire_nl1iOiOOl_dataout <= nl1l010OO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlO1O_dataout; + wire_nl1iOiOOO_dataout <= nl1l01i1i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlO0i_dataout; + wire_nl1iOl00i_dataout <= nl1l01l0l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1il_dataout; + wire_nl1iOl00l_dataout <= nl1l01l0O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1iO_dataout; + wire_nl1iOl00O_dataout <= nl1l01lii WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1li_dataout; + wire_nl1iOl01i_dataout <= nl1l01l1l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO10l_dataout; + wire_nl1iOl01l_dataout <= nl1l01l1O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO10O_dataout; + wire_nl1iOl01O_dataout <= nl1l01l0i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1ii_dataout; + wire_nl1iOl0i_dataout <= wire_nl1iOO0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOl0ii_dataout <= nl1l01lil WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1ll_dataout; + wire_nl1iOl0il_dataout <= nl1l01liO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1lO_dataout; + wire_nl1iOl0iO_dataout <= nl1l01lli WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1Oi_dataout; + wire_nl1iOl0l_dataout <= wire_niOOO0O_w_lg_nl1iO00l7949w(0) WHEN (wire_w_lg_niOO1l00O7936w(0) AND wire_w_lg_niOO1l00l7950w(0)) = '1' ELSE nl1iO00l; + wire_nl1iOl0li_dataout <= nl1l01lll WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1Ol_dataout; + wire_nl1iOl0ll_dataout <= nl1l01llO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO1OO_dataout; + wire_nl1iOl0lO_dataout <= nl1l01lOi WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO01i_dataout; + wire_nl1iOl0Oi_dataout <= nl1l01lOl WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO01l_dataout; + wire_nl1iOl0Ol_dataout <= nl1l01lOO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO01O_dataout; + wire_nl1iOl0OO_dataout <= nl1l01O1i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO00i_dataout; + wire_nl1iOl10i_dataout <= nl1l01i0l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOil_dataout; + wire_nl1iOl10l_dataout <= nl1l01i0O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOiO_dataout; + wire_nl1iOl10O_dataout <= nl1l01iii WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOli_dataout; + wire_nl1iOl11i_dataout <= nl1l01i1l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlO0l_dataout; + wire_nl1iOl11l_dataout <= nl1l01i1O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlO0O_dataout; + wire_nl1iOl11O_dataout <= nl1l01i0i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOii_dataout; + wire_nl1iOl1i_dataout <= wire_nl1iOO1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOl1ii_dataout <= nl1l01iil WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOll_dataout; + wire_nl1iOl1il_dataout <= nl1l01iiO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOlO_dataout; + wire_nl1iOl1iO_dataout <= nl1l01ili WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOOi_dataout; + wire_nl1iOl1l_dataout <= wire_nl1iOO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOl1li_dataout <= nl1l01ill WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOOl_dataout; + wire_nl1iOl1ll_dataout <= nl1l01ilO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOlOOO_dataout; + wire_nl1iOl1lO_dataout <= nl1l01iOi WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO11i_dataout; + wire_nl1iOl1O_dataout <= wire_nl1iOO1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1iOl1Oi_dataout <= nl1l01iOl WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO11l_dataout; + wire_nl1iOl1Ol_dataout <= nl1l01iOO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO11O_dataout; + wire_nl1iOl1OO_dataout <= nl1l01l1i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO10i_dataout; + wire_nl1iOli_dataout <= nl11lli OR niOO0O10O; + wire_nl1iOli0i_dataout <= nl1l01O0l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO0il_dataout; + wire_nl1iOli0l_dataout <= nl1l01O0O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO0iO_dataout; + wire_nl1iOli0O_dataout <= nl1l01Oii WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO0li_dataout; + wire_nl1iOli1i_dataout <= nl1l01O1l WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO00l_dataout; + wire_nl1iOli1l_dataout <= nl1l01O1O WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO00O_dataout; + wire_nl1iOli1O_dataout <= nl1l01O0i WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO0ii_dataout; + wire_nl1iOlii_dataout <= dl_ctrl_link2(0) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0il; + wire_nl1iOliii_dataout <= nl1l01Oil WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO0ll_dataout; + wire_nl1iOliil_dataout <= nl1l01OiO WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO0lO_dataout; + wire_nl1iOliiO_dataout <= nl1l01Oli WHEN nl1l1ilOO = '1' ELSE wire_nl1iOO0Oi_dataout; + wire_nl1iOlil_dataout <= dl_ctrl_link2(1) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0iO; + wire_nl1iOlili_dataout <= nl1l1iOlO AND nl1iil10O; + wire_nl1iOlill_dataout <= nl1l1iOOi AND nl1iil10O; + wire_nl1iOlilO_dataout <= nl1l1iOOl AND nl1iil10O; + wire_nl1iOliO_dataout <= dl_ctrl_link2(2) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0li; + wire_nl1iOliOi_dataout <= nl1l1iOOO AND nl1iil10O; + wire_nl1iOliOl_dataout <= nl1l1l11i AND nl1iil10O; + wire_nl1iOliOO_dataout <= nl1l1l11l AND nl1iil10O; + wire_nl1iOll_dataout <= nl11lll AND NOT(niOO0O10O); + wire_nl1iOll0i_dataout <= nl1l1l10O AND nl1iil10O; + wire_nl1iOll0l_dataout <= nl1l1l1ii AND nl1iil10O; + wire_nl1iOll0O_dataout <= nl1l1l1il AND nl1iil10O; + wire_nl1iOll1i_dataout <= nl1l1l11O AND nl1iil10O; + wire_nl1iOll1l_dataout <= nl1l1l10i AND nl1iil10O; + wire_nl1iOll1O_dataout <= nl1l1l10l AND nl1iil10O; + wire_nl1iOlli_dataout <= dl_ctrl_link2(3) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0ll; + wire_nl1iOllii_dataout <= nl1l1l1iO AND nl1iil10O; + wire_nl1iOllil_dataout <= nl1l1l1li AND nl1iil10O; + wire_nl1iOlliO_dataout <= nl1l1l1ll AND nl1iil10O; + wire_nl1iOlll_dataout <= dl_ctrl_link2(4) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0lO; + wire_nl1iOllli_dataout <= nl1l1l1lO AND nl1iil10O; + wire_nl1iOllll_dataout <= nl1l1l1Oi AND nl1iil10O; + wire_nl1iOlllO_dataout <= nl1l1l1Ol AND nl1iil10O; + wire_nl1iOllO_dataout <= dl_ctrl_link2(5) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0Oi; + wire_nl1iOllOi_dataout <= nl1l1l1OO AND nl1iil10O; + wire_nl1iOllOl_dataout <= nl1l1l01i AND nl1iil10O; + wire_nl1iOllOO_dataout <= nl1l1l01l AND nl1iil10O; + wire_nl1iOlO_dataout <= nl11ilO AND NOT(niOO0O10O); + wire_nl1iOlO0i_dataout <= nl1l1l00O AND nl1iil10O; + wire_nl1iOlO0l_dataout <= nl1l1l0ii AND nl1iil10O; + wire_nl1iOlO0O_dataout <= nl1l1l0il AND nl1iil10O; + wire_nl1iOlO1i_dataout <= nl1l1l01O AND nl1iil10O; + wire_nl1iOlO1l_dataout <= nl1l1l00i AND nl1iil10O; + wire_nl1iOlO1O_dataout <= nl1l1l00l AND nl1iil10O; + wire_nl1iOlOi_dataout <= dl_ctrl_link2(6) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0Ol; + wire_nl1iOlOii_dataout <= nl1l1l0iO AND nl1iil10O; + wire_nl1iOlOil_dataout <= nl1l1l0li AND nl1iil10O; + wire_nl1iOlOiO_dataout <= nl1l1l0ll AND nl1iil10O; + wire_nl1iOlOl_dataout <= dl_ctrl_link2(7) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iO0OO; + wire_nl1iOlOli_dataout <= nl1l1l0lO AND nl1iil10O; + wire_nl1iOlOll_dataout <= nl1l1l0Oi AND nl1iil10O; + wire_nl1iOlOlO_dataout <= nl1l1l0Ol AND nl1iil10O; + wire_nl1iOlOO_dataout <= dl_ctrl_link2(8) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iOi1i; + wire_nl1iOlOOi_dataout <= nl1l1l0OO AND nl1iil10O; + wire_nl1iOlOOl_dataout <= nl1l1li1i AND nl1iil10O; + wire_nl1iOlOOO_dataout <= nl1l1li1l AND nl1iil10O; + wire_nl1iOO00i_dataout <= nl1l1ll0O AND nl1iil10O; + wire_nl1iOO00l_dataout <= nl1l1llii AND nl1iil10O; + wire_nl1iOO00O_dataout <= nl1l1llil AND nl1iil10O; + wire_nl1iOO01i_dataout <= nl1l1ll1O AND nl1iil10O; + wire_nl1iOO01l_dataout <= nl1l1ll0i AND nl1iil10O; + wire_nl1iOO01O_dataout <= nl1l1ll0l AND nl1iil10O; + wire_nl1iOO0i_dataout <= dl_ctrl_link2(12) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iOi0l; + wire_nl1iOO0ii_dataout <= nl1l1lliO AND nl1iil10O; + wire_nl1iOO0il_dataout <= nl1l1llli AND nl1iil10O; + wire_nl1iOO0iO_dataout <= nl1l1llll AND nl1iil10O; + wire_nl1iOO0li_dataout <= nl1l1lllO AND nl1iil10O; + wire_nl1iOO0ll_dataout <= nl1l1llOi AND nl1iil10O; + wire_nl1iOO0lO_dataout <= nl1l1llOl AND nl1iil10O; + wire_nl1iOO0Oi_dataout <= nl1l1llOO AND nl1iil10O; + wire_nl1iOO0Ol_dataout <= nl1l0l10O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1101O_dataout; + wire_nl1iOO0OO_dataout <= nl1l0l1ii WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1100i_dataout; + wire_nl1iOO10i_dataout <= nl1l1li0O AND nl1iil10O; + wire_nl1iOO10l_dataout <= nl1l1liii AND nl1iil10O; + wire_nl1iOO10O_dataout <= nl1l1liil AND nl1iil10O; + wire_nl1iOO11i_dataout <= nl1l1li1O AND nl1iil10O; + wire_nl1iOO11l_dataout <= nl1l1li0i AND nl1iil10O; + wire_nl1iOO11O_dataout <= nl1l1li0l AND nl1iil10O; + wire_nl1iOO1i_dataout <= dl_ctrl_link2(9) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iOi1l; + wire_nl1iOO1ii_dataout <= nl1l1liiO AND nl1iil10O; + wire_nl1iOO1il_dataout <= nl1l1lili AND nl1iil10O; + wire_nl1iOO1iO_dataout <= nl1l1lill AND nl1iil10O; + wire_nl1iOO1l_dataout <= dl_ctrl_link2(10) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iOi1O; + wire_nl1iOO1li_dataout <= nl1l1lilO AND nl1iil10O; + wire_nl1iOO1ll_dataout <= nl1l1liOi AND nl1iil10O; + wire_nl1iOO1lO_dataout <= nl1l1liOl AND nl1iil10O; + wire_nl1iOO1O_dataout <= dl_ctrl_link2(11) WHEN wire_w_lg_niOO1l00O7936w(0) = '1' ELSE nl1iOi0i; + wire_nl1iOO1Oi_dataout <= nl1l1liOO AND nl1iil10O; + wire_nl1iOO1Ol_dataout <= nl1l1ll1i AND nl1iil10O; + wire_nl1iOO1OO_dataout <= nl1l1ll1l AND nl1iil10O; + wire_nl1iOOi_dataout <= nl11iOi AND NOT(niOO0O10O); + wire_nl1iOOi0i_dataout <= nl1l0l1ll WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110il_dataout; + wire_nl1iOOi0l_dataout <= nl1l0l1lO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110iO_dataout; + wire_nl1iOOi0O_dataout <= nl1l0l1Oi WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110li_dataout; + wire_nl1iOOi1i_dataout <= nl1l0l1il WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1100l_dataout; + wire_nl1iOOi1l_dataout <= nl1l0l1iO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1100O_dataout; + wire_nl1iOOi1O_dataout <= nl1l0l1li WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110ii_dataout; + wire_nl1iOOiii_dataout <= nl1l0l1Ol WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110ll_dataout; + wire_nl1iOOiil_dataout <= nl1l0l1OO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110lO_dataout; + wire_nl1iOOiiO_dataout <= nl1l0l01i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110Oi_dataout; + wire_nl1iOOili_dataout <= nl1l0l01l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110Ol_dataout; + wire_nl1iOOill_dataout <= nl1l0l01O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l110OO_dataout; + wire_nl1iOOilO_dataout <= nl1l0l00i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11i1i_dataout; + wire_nl1iOOiOi_dataout <= nl1l0l00l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11i1l_dataout; + wire_nl1iOOiOl_dataout <= nl1l0l00O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11i1O_dataout; + wire_nl1iOOiOO_dataout <= nl1l0l0ii WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11i0i_dataout; + wire_nl1iOOl_dataout <= nl11iOl AND NOT(niOO0O10O); + wire_nl1iOOl0i_dataout <= nl1l0l0ll WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11iil_dataout; + wire_nl1iOOl0l_dataout <= nl1l0l0lO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11iiO_dataout; + wire_nl1iOOl0O_dataout <= nl1l0l0Oi WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11ili_dataout; + wire_nl1iOOl1i_dataout <= nl1l0l0il WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11i0l_dataout; + wire_nl1iOOl1l_dataout <= nl1l0l0iO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11i0O_dataout; + wire_nl1iOOl1O_dataout <= nl1l0l0li WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11iii_dataout; + wire_nl1iOOlii_dataout <= nl1l0l0Ol WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11ill_dataout; + wire_nl1iOOlil_dataout <= nl1l0l0OO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11ilO_dataout; + wire_nl1iOOliO_dataout <= nl1l0li1i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11iOi_dataout; + wire_nl1iOOlli_dataout <= nl1l0li1l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11iOl_dataout; + wire_nl1iOOlll_dataout <= nl1l0li1O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11iOO_dataout; + wire_nl1iOOllO_dataout <= nl1l0li0i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11l1i_dataout; + wire_nl1iOOlOi_dataout <= nl1l0li0l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11l1l_dataout; + wire_nl1iOOlOl_dataout <= nl1l0li0O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11l1O_dataout; + wire_nl1iOOlOO_dataout <= nl1l0liii WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11l0i_dataout; + wire_nl1iOOO_dataout <= nl11iOO AND NOT(niOO0O10O); + wire_nl1iOOO0i_dataout <= nl1l0lill WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11lil_dataout; + wire_nl1iOOO0l_dataout <= nl1l0lilO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11liO_dataout; + wire_nl1iOOO0O_dataout <= nl1l0liOi WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11lli_dataout; + wire_nl1iOOO1i_dataout <= nl1l0liil WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11l0l_dataout; + wire_nl1iOOO1l_dataout <= nl1l0liiO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11l0O_dataout; + wire_nl1iOOO1O_dataout <= nl1l0lili WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11lii_dataout; + wire_nl1iOOOii_dataout <= nl1l0liOl WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11lll_dataout; + wire_nl1iOOOil_dataout <= nl1l0liOO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11llO_dataout; + wire_nl1iOOOiO_dataout <= nl1l0ll1i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11lOi_dataout; + wire_nl1iOOOli_dataout <= nl1l0ll1l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11lOl_dataout; + wire_nl1iOOOll_dataout <= nl1l0ll1O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11lOO_dataout; + wire_nl1iOOOlO_dataout <= nl1l0ll0i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11O1i_dataout; + wire_nl1iOOOOi_dataout <= nl1l0ll0l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11O1l_dataout; + wire_nl1iOOOOl_dataout <= nl1l0ll0O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11O1O_dataout; + wire_nl1iOOOOO_dataout <= nl1l0llii WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11O0i_dataout; + wire_nl1l001O_dataout <= (nl1l00lO XOR nl1l00li) AND NOT(wire_niO01l0O_dataout); + wire_nl1l00i_dataout <= n1Oi10O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0lOOOO; + wire_nl1l00ii_dataout <= nl1l00li AND NOT(wire_niO01O0O_dataout); + wire_nl1l00iO_dataout <= nl1l001l AND NOT(wire_niO01O0O_dataout); + wire_nl1l00l_dataout <= n1Oi1ii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O111i; + wire_nl1l00ll_dataout <= nl1l00Oi AND NOT(wire_niO01l0O_dataout); + wire_nl1l00O_dataout <= n1Oi1il WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O111l; + wire_nl1l00Ol_dataout <= nl1l00lO AND NOT(wire_niO01l0O_dataout); + wire_nl1l00OO_dataout <= nl1l00il AND NOT(wire_niO01l0O_dataout); + wire_nl1l010O_dataout <= nl1l010i AND NOT(wire_niO01l0O_dataout); + wire_nl1l011i_dataout <= nl1l1OiO AND NOT(wire_niO01O0O_dataout); + wire_nl1l011O_dataout <= nl1l010l AND NOT(wire_niO01l0O_dataout); + wire_nl1l01i_dataout <= n1Oi11O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0ll11l; + wire_nl1l01ii_dataout <= nl1l1OOO AND NOT(wire_niO01l0O_dataout); + wire_nl1l01iO_dataout <= wire_nl1l01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l01l_dataout <= n1Oi10i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0lOOOi; + wire_nl1l01li_dataout <= wire_nl1l01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l01ll_dataout <= wire_nl1000i_w_lg_nl1l010l7907w(0) WHEN (nlll011OO AND (wire_w_lg_niOO1l0li7908w(0) AND (nlll011OO XOR nl1l01il))) = '1' ELSE nl1l010l; + wire_nl1l01O_dataout <= n1Oi10l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0lOOOl; + wire_nl1l01OO_dataout <= nl1l01il WHEN niOO1l0li = '1' ELSE nlll011OO; + wire_nl1l0i0i_dataout <= wire_nl1000i_w_lg_nl1l00Oi7900w(0) WHEN (nlll0ilOl AND (wire_w_lg_niOO1l0ll7901w(0) AND (nlll0ilOl XOR nl1l0i1i))) = '1' ELSE nl1l00Oi; + wire_nl1l0i1l_dataout <= wire_nl1l0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0i1O_dataout <= wire_nl1l0iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0ii_dataout <= n1Oi1iO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O111O; + wire_nl1l0iil_dataout <= nl1l0i1i WHEN niOO1l0ll = '1' ELSE nlll0ilOl; + wire_nl1l0il_dataout <= n1Oi1li WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O110i; + wire_nl1l0ill_dataout <= (nl1l0l0l XOR nl1l0l1O) AND NOT(wire_niO01l0O_dataout); + wire_nl1l0iO_dataout <= n1Oi1ll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O110l; + wire_nl1l0iOO_dataout <= nl1l0l1O AND NOT(wire_niO01O0O_dataout); + wire_nl1l0l0i_dataout <= nl1l0l0O AND NOT(wire_niO01l0O_dataout); + wire_nl1l0l1l_dataout <= nl1l0ili AND NOT(wire_niO01O0O_dataout); + wire_nl1l0li_dataout <= n1Oi1lO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O110O; + wire_nl1l0lii_dataout <= nl1l0l0l AND NOT(wire_niO01l0O_dataout); + wire_nl1l0lil_dataout <= nl1l0l1i AND NOT(wire_niO01l0O_dataout); + wire_nl1l0ll_dataout <= n1Oi1Oi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11ii; + wire_nl1l0lli_dataout <= wire_nl1l0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0lll_dataout <= wire_nl1l0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0llO_dataout <= wire_nl1000i_w_lg_nl1l0l0O7893w(0) WHEN (niOO1l0lO AND (wire_w_lg_niOO1l0Oi7894w(0) AND (niOO1l0lO XOR nl1l0liO))) = '1' ELSE nl1l0l0O; + wire_nl1l0lO_dataout <= n1Oi1Ol WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11il; + wire_nl1l0lOll_dataout <= wire_nl1lil0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0lOlO_dataout <= wire_nl1lil0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0lOOi_dataout <= wire_nl1lili1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0lOOl_dataout <= wire_nl1lili1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0lOOO_dataout <= wire_nl1lili1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O00i_dataout <= wire_nl1liO1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O00l_dataout <= wire_nl1liO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O00O_dataout <= wire_nl1liO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O01i_dataout <= wire_nl1liO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O01l_dataout <= wire_nl1liO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O01O_dataout <= wire_nl1liO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0ii_dataout <= wire_nl1liO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0il_dataout <= wire_nl1liO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0iO_dataout <= wire_nl1liO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0li_dataout <= wire_nl1liO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0ll_dataout <= wire_nl1liO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0lO_dataout <= wire_nl1liO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0Oi_dataout <= wire_nl1liO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0Ol_dataout <= wire_nl1liO01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O0OO_dataout <= wire_nl1liO00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O10i_dataout <= (NOT (nl1ll0iOi AND (nl1Ol1l0l AND (nl1ll0llO OR niOi1lOiO)))) AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O10l_dataout <= wire_nl1lilOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O10O_dataout <= wire_nl1lilOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O11i_dataout <= wire_nl1lili0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O11l_dataout <= wire_nl1lili0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O11O_dataout <= niOi1llli OR wire_niO01O0O_dataout; + wire_nl1l0O1i_dataout <= nl1l0liO WHEN niOO1l0Oi = '1' ELSE niOO1l0lO; + wire_nl1l0O1ii_dataout <= wire_nl1lilOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O1il_dataout <= niOi1lllO OR wire_niO01O0O_dataout; + wire_nl1l0O1iO_dataout <= wire_nl1lilOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O1li_dataout <= wire_nl1lilOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O1ll_dataout <= wire_nl1lilOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O1lO_dataout <= wire_nl1liO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O1Oi_dataout <= wire_nl1liO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O1Ol_dataout <= wire_nl1liO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0O1OO_dataout <= wire_nl1liO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oi_dataout <= n1Oi1OO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11iO; + wire_nl1l0Oi0i_dataout <= wire_nl1liO0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oi0l_dataout <= wire_nl1liO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oi0O_dataout <= wire_nl1liO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oi1i_dataout <= wire_nl1liO00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oi1l_dataout <= wire_nl1liO00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oi1O_dataout <= wire_nl1liO0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oiii_dataout <= wire_nl1liO0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oiil_dataout <= wire_nl1liO0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OiiO_dataout <= wire_nl1liO0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oili_dataout <= wire_nl1liO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Oill_dataout <= wire_nl1liO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OilO_dataout <= wire_nl1liOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OiOi_dataout <= wire_nl1liOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OiOl_dataout <= wire_nl1liOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OiOO_dataout <= wire_nl1liOi0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Ol_dataout <= n1Oi01i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11li; + wire_nl1l0Ol0i_dataout <= wire_nl1liOiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Ol0l_dataout <= wire_nl1liOiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Ol0O_dataout <= wire_nl1liOili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Ol1i_dataout <= wire_nl1liOi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Ol1l_dataout <= wire_nl1liOi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Ol1O_dataout <= wire_nl1liOiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Olii_dataout <= wire_nl1liOill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Olil_dataout <= wire_nl1liOilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OliO_dataout <= wire_nl1liOiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Olli_dataout <= wire_nl1liOiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0Olll_dataout <= wire_nl1liOiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OllO_dataout <= wire_nl1liOl1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OlOi_dataout <= wire_nl1liOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OlOl_dataout <= wire_nl1liOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OlOO_dataout <= wire_nl1liOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OO_dataout <= n1Oi01l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11ll; + wire_nl1l0OO0i_dataout <= wire_nl1liOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OO0l_dataout <= wire_nl1liOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OO0O_dataout <= wire_nl1liOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OO1i_dataout <= wire_nl1liOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OO1l_dataout <= wire_nl1liOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OO1O_dataout <= wire_nl1liOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOii_dataout <= wire_nl1liOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOil_dataout <= wire_nl1liOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOiO_dataout <= wire_nl1liOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOli_dataout <= wire_nl1liOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOll_dataout <= wire_nl1liOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOlO_dataout <= wire_nl1liOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOOi_dataout <= wire_nl1liOO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOOl_dataout <= wire_nl1liOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l0OOOO_dataout <= wire_nl1liOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l1000i_dataout <= nl1l0ll0l WHEN nl1l1iOll = '1' ELSE wire_nl1l10l0O_dataout; + wire_nl1l1000l_dataout <= nl1l0ll0O WHEN nl1l1iOll = '1' ELSE wire_nl1l10lii_dataout; + wire_nl1l1000O_dataout <= nl1l0llii WHEN nl1l1iOll = '1' ELSE wire_nl1l10lil_dataout; + wire_nl1l1001i_dataout <= nl1l0ll1l WHEN nl1l1iOll = '1' ELSE wire_nl1l10l1O_dataout; + wire_nl1l1001l_dataout <= nl1l0ll1O WHEN nl1l1iOll = '1' ELSE wire_nl1l10l0i_dataout; + wire_nl1l1001O_dataout <= nl1l0ll0i WHEN nl1l1iOll = '1' ELSE wire_nl1l10l0l_dataout; + wire_nl1l100ii_dataout <= nl1l0llil WHEN nl1l1iOll = '1' ELSE wire_nl1l10liO_dataout; + wire_nl1l100il_dataout <= nl1l0lliO WHEN nl1l1iOll = '1' ELSE wire_nl1l10lli_dataout; + wire_nl1l100iO_dataout <= nl1l0llli WHEN nl1l1iOll = '1' ELSE wire_nl1l10lll_dataout; + wire_nl1l100li_dataout <= nl1l0llll WHEN nl1l1iOll = '1' ELSE wire_nl1l10llO_dataout; + wire_nl1l100ll_dataout <= nl1l0lllO WHEN nl1l1iOll = '1' ELSE wire_nl1l10lOi_dataout; + wire_nl1l100lO_dataout <= nl1l0llOi WHEN nl1l1iOll = '1' ELSE wire_nl1l10lOl_dataout; + wire_nl1l100O_dataout <= nl1l11Ol WHEN niOO1l0ii = '1' ELSE niOO010il; + wire_nl1l100Oi_dataout <= nl1l0llOl WHEN nl1l1iOll = '1' ELSE wire_nl1l10lOO_dataout; + wire_nl1l100Ol_dataout <= nl1l0llOO WHEN nl1l1iOll = '1' ELSE wire_nl1l10O1i_dataout; + wire_nl1l100OO_dataout <= nl1l0lO1i WHEN nl1l1iOll = '1' ELSE wire_nl1l10O1l_dataout; + wire_nl1l1010i_dataout <= nl1l1Ol1l AND nl1l1iOii; + wire_nl1l1010l_dataout <= nl1l1Ol1O AND nl1l1iOii; + wire_nl1l1010O_dataout <= nl1l1Ol0i AND nl1l1iOii; + wire_nl1l1011i_dataout <= nl1l1OiOl AND nl1l1iOii; + wire_nl1l1011l_dataout <= nl1l1OiOO AND nl1l1iOii; + wire_nl1l1011O_dataout <= nl1l1Ol1i AND nl1l1iOii; + wire_nl1l101i_dataout <= wire_nl1l100O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l101ii_dataout <= nl1l0liil WHEN nl1l1iOll = '1' ELSE wire_nl1l10iiO_dataout; + wire_nl1l101il_dataout <= nl1l0liiO WHEN nl1l1iOll = '1' ELSE wire_nl1l10ili_dataout; + wire_nl1l101iO_dataout <= nl1l0lili WHEN nl1l1iOll = '1' ELSE wire_nl1l10ill_dataout; + wire_nl1l101l_dataout <= wire_nl1000i_w_lg_nl1l11ll7928w(0) WHEN (niOO010il AND (wire_w_lg_niOO1l0ii7929w(0) AND (niOO010il XOR nl1l11Ol))) = '1' ELSE nl1l11ll; + wire_nl1l101li_dataout <= nl1l0lill WHEN nl1l1iOll = '1' ELSE wire_nl1l10ilO_dataout; + wire_nl1l101ll_dataout <= nl1l0lilO WHEN nl1l1iOll = '1' ELSE wire_nl1l10iOi_dataout; + wire_nl1l101lO_dataout <= nl1l0liOi WHEN nl1l1iOll = '1' ELSE wire_nl1l10iOl_dataout; + wire_nl1l101Oi_dataout <= nl1l0liOl WHEN nl1l1iOll = '1' ELSE wire_nl1l10iOO_dataout; + wire_nl1l101Ol_dataout <= nl1l0liOO WHEN nl1l1iOll = '1' ELSE wire_nl1l10l1i_dataout; + wire_nl1l101OO_dataout <= nl1l0ll1i WHEN nl1l1iOll = '1' ELSE wire_nl1l10l1l_dataout; + wire_nl1l10i_dataout <= nl11l0i AND NOT(niOO0O10O); + wire_nl1l10i0i_dataout <= nl1l0lO0l WHEN nl1l1iOll = '1' ELSE wire_nl1l10O0O_dataout; + wire_nl1l10i0l_dataout <= nl1l0lO0O WHEN nl1l1iOll = '1' ELSE wire_nl1l10Oii_dataout; + wire_nl1l10i0O_dataout <= nl1l0lOii WHEN nl1l1iOll = '1' ELSE wire_nl1l10Oil_dataout; + wire_nl1l10i1i_dataout <= nl1l0lO1l WHEN nl1l1iOll = '1' ELSE wire_nl1l10O1O_dataout; + wire_nl1l10i1l_dataout <= nl1l0lO1O WHEN nl1l1iOll = '1' ELSE wire_nl1l10O0i_dataout; + wire_nl1l10i1O_dataout <= nl1l0lO0i WHEN nl1l1iOll = '1' ELSE wire_nl1l10O0l_dataout; + wire_nl1l10iii_dataout <= nl1l0lOil WHEN nl1l1iOll = '1' ELSE wire_nl1l10OiO_dataout; + wire_nl1l10iil_dataout <= nl1l0lOiO WHEN nl1l1iOll = '1' ELSE wire_nl1l10Oli_dataout; + wire_nl1l10iiO_dataout <= nl1l0i01l WHEN nl1l1iOli = '1' ELSE wire_nl1l10Oll_dataout; + wire_nl1l10ili_dataout <= nl1l0i01O WHEN nl1l1iOli = '1' ELSE wire_nl1l10OlO_dataout; + wire_nl1l10ill_dataout <= nl1l0i00i WHEN nl1l1iOli = '1' ELSE wire_nl1l10OOi_dataout; + wire_nl1l10ilO_dataout <= nl1l0i00l WHEN nl1l1iOli = '1' ELSE wire_nl1l10OOl_dataout; + wire_nl1l10iO_dataout <= (nl1l1i1O XOR nl1l1i1i) AND NOT(wire_niO01l0O_dataout); + wire_nl1l10iOi_dataout <= nl1l0i00O WHEN nl1l1iOli = '1' ELSE wire_nl1l10OOO_dataout; + wire_nl1l10iOl_dataout <= nl1l0i0ii WHEN nl1l1iOli = '1' ELSE wire_nl1l1i11i_dataout; + wire_nl1l10iOO_dataout <= nl1l0i0il WHEN nl1l1iOli = '1' ELSE wire_nl1l1i11l_dataout; + wire_nl1l10l_dataout <= nl11l0l AND NOT(niOO0O10O); + wire_nl1l10l0i_dataout <= nl1l0i0lO WHEN nl1l1iOli = '1' ELSE wire_nl1l1i10O_dataout; + wire_nl1l10l0l_dataout <= nl1l0i0Oi WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1ii_dataout; + wire_nl1l10l0O_dataout <= nl1l0i0Ol WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1il_dataout; + wire_nl1l10l1i_dataout <= nl1l0i0iO WHEN nl1l1iOli = '1' ELSE wire_nl1l1i11O_dataout; + wire_nl1l10l1l_dataout <= nl1l0i0li WHEN nl1l1iOli = '1' ELSE wire_nl1l1i10i_dataout; + wire_nl1l10l1O_dataout <= nl1l0i0ll WHEN nl1l1iOli = '1' ELSE wire_nl1l1i10l_dataout; + wire_nl1l10lii_dataout <= nl1l0i0OO WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1iO_dataout; + wire_nl1l10lil_dataout <= nl1l0ii1i WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1li_dataout; + wire_nl1l10liO_dataout <= nl1l0ii1l WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1ll_dataout; + wire_nl1l10lli_dataout <= nl1l0ii1O WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1lO_dataout; + wire_nl1l10lll_dataout <= nl1l0ii0i WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1Oi_dataout; + wire_nl1l10llO_dataout <= nl1l0ii0l WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1Ol_dataout; + wire_nl1l10lOi_dataout <= nl1l0ii0O WHEN nl1l1iOli = '1' ELSE wire_nl1l1i1OO_dataout; + wire_nl1l10lOl_dataout <= nl1l0iiii WHEN nl1l1iOli = '1' ELSE wire_nl1l1i01i_dataout; + wire_nl1l10lOO_dataout <= nl1l0iiil WHEN nl1l1iOli = '1' ELSE wire_nl1l1i01l_dataout; + wire_nl1l10O_dataout <= nl11l0O AND NOT(niOO0O10O); + wire_nl1l10O0i_dataout <= nl1l0iilO WHEN nl1l1iOli = '1' ELSE wire_nl1l1i00O_dataout; + wire_nl1l10O0l_dataout <= nl1l0iiOi WHEN nl1l1iOli = '1' ELSE wire_nl1l1i0ii_dataout; + wire_nl1l10O0O_dataout <= nl1l0iiOl WHEN nl1l1iOli = '1' ELSE wire_nl1l1i0il_dataout; + wire_nl1l10O1i_dataout <= nl1l0iiiO WHEN nl1l1iOli = '1' ELSE wire_nl1l1i01O_dataout; + wire_nl1l10O1l_dataout <= nl1l0iili WHEN nl1l1iOli = '1' ELSE wire_nl1l1i00i_dataout; + wire_nl1l10O1O_dataout <= nl1l0iill WHEN nl1l1iOli = '1' ELSE wire_nl1l1i00l_dataout; + wire_nl1l10Oi_dataout <= nl1l1i1i AND NOT(wire_niO01O0O_dataout); + wire_nl1l10Oii_dataout <= nl1l0iiOO WHEN nl1l1iOli = '1' ELSE wire_nl1l1i0iO_dataout; + wire_nl1l10Oil_dataout <= nl1l0il1i WHEN nl1l1iOli = '1' ELSE wire_nl1l1i0li_dataout; + wire_nl1l10OiO_dataout <= nl1l0il1l WHEN nl1l1iOli = '1' ELSE wire_nl1l1i0ll_dataout; + wire_nl1l10Oli_dataout <= nl1l0il1O WHEN nl1l1iOli = '1' ELSE wire_nl1l1i0lO_dataout; + wire_nl1l10Oll_dataout <= nl1l01Oll WHEN nl1l1iOiO = '1' ELSE wire_nl1l1i0Oi_dataout; + wire_nl1l10OlO_dataout <= nl1l01OlO WHEN nl1l1iOiO = '1' ELSE wire_nl1l1i0Ol_dataout; + wire_nl1l10OO_dataout <= nl1l10il AND NOT(wire_niO01O0O_dataout); + wire_nl1l10OOi_dataout <= nl1l01OOi WHEN nl1l1iOiO = '1' ELSE wire_nl1l1i0OO_dataout; + wire_nl1l10OOl_dataout <= nl1l01OOl WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ii1i_dataout; + wire_nl1l10OOO_dataout <= nl1l01OOO WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ii1l_dataout; + wire_nl1l1100i_dataout <= nl1l1lO1l AND nl1l1iOii; + wire_nl1l1100l_dataout <= nl1l1lO1O AND nl1l1iOii; + wire_nl1l1100O_dataout <= nl1l1lO0i AND nl1l1iOii; + wire_nl1l1101i_dataout <= nl1l0lOil WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1010l_dataout; + wire_nl1l1101l_dataout <= nl1l0lOiO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1010O_dataout; + wire_nl1l1101O_dataout <= nl1l1lO1i AND nl1l1iOii; + wire_nl1l110ii_dataout <= nl1l1lO0l AND nl1l1iOii; + wire_nl1l110il_dataout <= nl1l1lO0O AND nl1l1iOii; + wire_nl1l110iO_dataout <= nl1l1lOii AND nl1l1iOii; + wire_nl1l110l_dataout <= nl1l11il AND NOT(wire_niO01O0O_dataout); + wire_nl1l110li_dataout <= nl1l1lOil AND nl1l1iOii; + wire_nl1l110ll_dataout <= nl1l1lOiO AND nl1l1iOii; + wire_nl1l110lO_dataout <= nl1l1lOli AND nl1l1iOii; + wire_nl1l110Oi_dataout <= nl1l1lOll AND nl1l1iOii; + wire_nl1l110Ol_dataout <= nl1l1lOlO AND nl1l1iOii; + wire_nl1l110OO_dataout <= nl1l1lOOi AND nl1l1iOii; + wire_nl1l1110i_dataout <= nl1l0llll WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11Oil_dataout; + wire_nl1l1110l_dataout <= nl1l0lllO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11OiO_dataout; + wire_nl1l1110O_dataout <= nl1l0llOi WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11Oli_dataout; + wire_nl1l1111i_dataout <= nl1l0llil WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11O0l_dataout; + wire_nl1l1111l_dataout <= nl1l0lliO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11O0O_dataout; + wire_nl1l1111O_dataout <= nl1l0llli WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11Oii_dataout; + wire_nl1l111i_dataout <= (nl1l11li XOR nl1l11il) AND NOT(wire_niO01l0O_dataout); + wire_nl1l111ii_dataout <= nl1l0llOl WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11Oll_dataout; + wire_nl1l111il_dataout <= nl1l0llOO WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11OlO_dataout; + wire_nl1l111iO_dataout <= nl1l0lO1i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11OOi_dataout; + wire_nl1l111li_dataout <= nl1l0lO1l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11OOl_dataout; + wire_nl1l111ll_dataout <= nl1l0lO1O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l11OOO_dataout; + wire_nl1l111lO_dataout <= nl1l0lO0i WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1011i_dataout; + wire_nl1l111Oi_dataout <= nl1l0lO0l WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1011l_dataout; + wire_nl1l111Ol_dataout <= nl1l0lO0O WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1011O_dataout; + wire_nl1l111OO_dataout <= nl1l0lOii WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE wire_nl1l1010i_dataout; + wire_nl1l11i_dataout <= nl11l1i AND NOT(niOO0O10O); + wire_nl1l11i0i_dataout <= nl1l1O11l AND nl1l1iOii; + wire_nl1l11i0l_dataout <= nl1l1O11O AND nl1l1iOii; + wire_nl1l11i0O_dataout <= nl1l1O10i AND nl1l1iOii; + wire_nl1l11i1i_dataout <= nl1l1lOOl AND nl1l1iOii; + wire_nl1l11i1l_dataout <= nl1l1lOOO AND nl1l1iOii; + wire_nl1l11i1O_dataout <= nl1l1O11i AND nl1l1iOii; + wire_nl1l11ii_dataout <= nl1iOOOO AND NOT(wire_niO01O0O_dataout); + wire_nl1l11iii_dataout <= nl1l1O10l AND nl1l1iOii; + wire_nl1l11iil_dataout <= nl1l1O10O AND nl1l1iOii; + wire_nl1l11iiO_dataout <= nl1l1O1ii AND nl1l1iOii; + wire_nl1l11ili_dataout <= nl1l1O1il AND nl1l1iOii; + wire_nl1l11ill_dataout <= nl1l1O1iO AND nl1l1iOii; + wire_nl1l11ilO_dataout <= nl1l1O1li AND nl1l1iOii; + wire_nl1l11iO_dataout <= nl1l11ll AND NOT(wire_niO01l0O_dataout); + wire_nl1l11iOi_dataout <= nl1l1O1ll AND nl1l1iOii; + wire_nl1l11iOl_dataout <= nl1l1O1lO AND nl1l1iOii; + wire_nl1l11iOO_dataout <= nl1l1O1Oi AND nl1l1iOii; + wire_nl1l11l_dataout <= nl11l1l AND NOT(niOO0O10O); + wire_nl1l11l0i_dataout <= nl1l1O01l AND nl1l1iOii; + wire_nl1l11l0l_dataout <= nl1l1O01O AND nl1l1iOii; + wire_nl1l11l0O_dataout <= nl1l1O00i AND nl1l1iOii; + wire_nl1l11l1i_dataout <= nl1l1O1Ol AND nl1l1iOii; + wire_nl1l11l1l_dataout <= nl1l1O1OO AND nl1l1iOii; + wire_nl1l11l1O_dataout <= nl1l1O01i AND nl1l1iOii; + wire_nl1l11lii_dataout <= nl1l1O00l AND nl1l1iOii; + wire_nl1l11lil_dataout <= nl1l1O00O AND nl1l1iOii; + wire_nl1l11liO_dataout <= nl1l1O0ii AND nl1l1iOii; + wire_nl1l11lli_dataout <= nl1l1O0il AND nl1l1iOii; + wire_nl1l11lll_dataout <= nl1l1O0iO AND nl1l1iOii; + wire_nl1l11llO_dataout <= nl1l1O0li AND nl1l1iOii; + wire_nl1l11lO_dataout <= nl1l11li AND NOT(wire_niO01l0O_dataout); + wire_nl1l11lOi_dataout <= nl1l1O0ll AND nl1l1iOii; + wire_nl1l11lOl_dataout <= nl1l1O0lO AND nl1l1iOii; + wire_nl1l11lOO_dataout <= nl1l1O0Oi AND nl1l1iOii; + wire_nl1l11O_dataout <= nl11l1O AND NOT(niOO0O10O); + wire_nl1l11O0i_dataout <= nl1l1Oi1l AND nl1l1iOii; + wire_nl1l11O0l_dataout <= nl1l1Oi1O AND nl1l1iOii; + wire_nl1l11O0O_dataout <= nl1l1Oi0i AND nl1l1iOii; + wire_nl1l11O1i_dataout <= nl1l1O0Ol AND nl1l1iOii; + wire_nl1l11O1l_dataout <= nl1l1O0OO AND nl1l1iOii; + wire_nl1l11O1O_dataout <= nl1l1Oi1i AND nl1l1iOii; + wire_nl1l11Oi_dataout <= nl1l110O AND NOT(wire_niO01l0O_dataout); + wire_nl1l11Oii_dataout <= nl1l1Oi0l AND nl1l1iOii; + wire_nl1l11Oil_dataout <= nl1l1Oi0O AND nl1l1iOii; + wire_nl1l11OiO_dataout <= nl1l1Oiii AND nl1l1iOii; + wire_nl1l11Oli_dataout <= nl1l1Oiil AND nl1l1iOii; + wire_nl1l11Oll_dataout <= nl1l1OiiO AND nl1l1iOii; + wire_nl1l11OlO_dataout <= nl1l1Oili AND nl1l1iOii; + wire_nl1l11OO_dataout <= wire_nl1l101l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l11OOi_dataout <= nl1l1Oill AND nl1l1iOii; + wire_nl1l11OOl_dataout <= nl1l1OilO AND nl1l1iOii; + wire_nl1l11OOO_dataout <= nl1l1OiOi AND nl1l1iOii; + wire_nl1l1i00i_dataout <= nl1l0000i WHEN nl1l1iOiO = '1' ELSE wire_nl1l1il0O_dataout; + wire_nl1l1i00l_dataout <= nl1l0000l WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ilii_dataout; + wire_nl1l1i00O_dataout <= nl1l0000O WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ilil_dataout; + wire_nl1l1i01i_dataout <= nl1l0001i WHEN nl1l1iOiO = '1' ELSE wire_nl1l1il1O_dataout; + wire_nl1l1i01l_dataout <= nl1l0001l WHEN nl1l1iOiO = '1' ELSE wire_nl1l1il0i_dataout; + wire_nl1l1i01O_dataout <= nl1l0001O WHEN nl1l1iOiO = '1' ELSE wire_nl1l1il0l_dataout; + wire_nl1l1i0ii_dataout <= nl1l000ii WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iliO_dataout; + wire_nl1l1i0il_dataout <= nl1l000il WHEN nl1l1iOiO = '1' ELSE wire_nl1l1illi_dataout; + wire_nl1l1i0iO_dataout <= nl1l000iO WHEN nl1l1iOiO = '1' ELSE wire_nl1l1illl_dataout; + wire_nl1l1i0l_dataout <= nl1l1i1O AND NOT(wire_niO01l0O_dataout); + wire_nl1l1i0li_dataout <= nl1l000li WHEN nl1l1iOiO = '1' ELSE wire_nl1l1illO_dataout; + wire_nl1l1i0ll_dataout <= nl1l000ll WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ilOi_dataout; + wire_nl1l1i0lO_dataout <= nl1l000lO WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ilOl_dataout; + wire_nl1l1i0O_dataout <= nl1l10Ol AND NOT(wire_niO01l0O_dataout); + wire_nl1l1i0Oi_dataout <= nl1l1Ol0l AND nl1l1iOil; + wire_nl1l1i0Ol_dataout <= nl1l1Ol0O AND nl1l1iOil; + wire_nl1l1i0OO_dataout <= nl1l1Olii AND nl1l1iOil; + wire_nl1l1i10i_dataout <= nl1l0010i WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ii0O_dataout; + wire_nl1l1i10l_dataout <= nl1l0010l WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iiii_dataout; + wire_nl1l1i10O_dataout <= nl1l0010O WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iiil_dataout; + wire_nl1l1i11i_dataout <= nl1l0011i WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ii1O_dataout; + wire_nl1l1i11l_dataout <= nl1l0011l WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ii0i_dataout; + wire_nl1l1i11O_dataout <= nl1l0011O WHEN nl1l1iOiO = '1' ELSE wire_nl1l1ii0l_dataout; + wire_nl1l1i1ii_dataout <= nl1l001ii WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iiiO_dataout; + wire_nl1l1i1il_dataout <= nl1l001il WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iili_dataout; + wire_nl1l1i1iO_dataout <= nl1l001iO WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iill_dataout; + wire_nl1l1i1l_dataout <= nl1l1i0i AND NOT(wire_niO01l0O_dataout); + wire_nl1l1i1li_dataout <= nl1l001li WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iilO_dataout; + wire_nl1l1i1ll_dataout <= nl1l001ll WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iiOi_dataout; + wire_nl1l1i1lO_dataout <= nl1l001lO WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iiOl_dataout; + wire_nl1l1i1Oi_dataout <= nl1l001Oi WHEN nl1l1iOiO = '1' ELSE wire_nl1l1iiOO_dataout; + wire_nl1l1i1Ol_dataout <= nl1l001Ol WHEN nl1l1iOiO = '1' ELSE wire_nl1l1il1i_dataout; + wire_nl1l1i1OO_dataout <= nl1l001OO WHEN nl1l1iOiO = '1' ELSE wire_nl1l1il1l_dataout; + wire_nl1l1ii_dataout <= nl11lii AND NOT(niOO0O10O); + wire_nl1l1ii0i_dataout <= nl1l1Olll AND nl1l1iOil; + wire_nl1l1ii0l_dataout <= nl1l1OllO AND nl1l1iOil; + wire_nl1l1ii0O_dataout <= nl1l1OlOi AND nl1l1iOil; + wire_nl1l1ii1i_dataout <= nl1l1Olil AND nl1l1iOil; + wire_nl1l1ii1l_dataout <= nl1l1OliO AND nl1l1iOil; + wire_nl1l1ii1O_dataout <= nl1l1Olli AND nl1l1iOil; + wire_nl1l1iiii_dataout <= nl1l1OlOl AND nl1l1iOil; + wire_nl1l1iiil_dataout <= nl1l1OlOO AND nl1l1iOil; + wire_nl1l1iiiO_dataout <= nl1l1OO1i AND nl1l1iOil; + wire_nl1l1iil_dataout <= wire_nl1l1ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l1iili_dataout <= nl1l1OO1l AND nl1l1iOil; + wire_nl1l1iill_dataout <= nl1l1OO1O AND nl1l1iOil; + wire_nl1l1iilO_dataout <= nl1l1OO0i AND nl1l1iOil; + wire_nl1l1iiO_dataout <= wire_nl1l1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l1iiOi_dataout <= nl1l1OO0l AND nl1l1iOil; + wire_nl1l1iiOl_dataout <= nl1l1OO0O AND nl1l1iOil; + wire_nl1l1iiOO_dataout <= nl1l1OOii AND nl1l1iOil; + wire_nl1l1il_dataout <= nl11lil AND NOT(niOO0O10O); + wire_nl1l1il0i_dataout <= nl1l1OOll AND nl1l1iOil; + wire_nl1l1il0l_dataout <= nl1l1OOlO AND nl1l1iOil; + wire_nl1l1il0O_dataout <= nl1l1OOOi AND nl1l1iOil; + wire_nl1l1il1i_dataout <= nl1l1OOil AND nl1l1iOil; + wire_nl1l1il1l_dataout <= nl1l1OOiO AND nl1l1iOil; + wire_nl1l1il1O_dataout <= nl1l1OOli AND nl1l1iOil; + wire_nl1l1ili_dataout <= wire_nl1000i_w_lg_nl1l1i0i7921w(0) WHEN (nlliiillO AND (wire_w_lg_niOO1l0il7922w(0) AND (nlliiillO XOR nl1l1iii))) = '1' ELSE nl1l1i0i; + wire_nl1l1ilii_dataout <= nl1l1OOOl AND nl1l1iOil; + wire_nl1l1ilil_dataout <= nl1l1OOOO AND nl1l1iOil; + wire_nl1l1iliO_dataout <= nl1l0111i AND nl1l1iOil; + wire_nl1l1illi_dataout <= nl1l0111l AND nl1l1iOil; + wire_nl1l1illl_dataout <= nl1l0111O AND nl1l1iOil; + wire_nl1l1illO_dataout <= nl1l0110i AND nl1l1iOil; + wire_nl1l1ilOi_dataout <= nl1l0110l AND nl1l1iOil; + wire_nl1l1ilOl_dataout <= nl1l0110O AND nl1l1iOil; + wire_nl1l1iO_dataout <= nl11liO AND NOT(niOO0O10O); + wire_nl1l1iOl_dataout <= nl1l1iii WHEN niOO1l0il = '1' ELSE nlliiillO; + wire_nl1l1l0O_dataout <= nl1l1liO AND NOT(wire_niO01O0O_dataout); + wire_nl1l1l1l_dataout <= (nl1l1lll XOR nl1l1liO) AND NOT(wire_niO01l0O_dataout); + wire_nl1l1li_dataout <= nl11lli AND NOT(niOO0O10O); + wire_nl1l1lil_dataout <= nl1l1l1i AND NOT(wire_niO01O0O_dataout); + wire_nl1l1ll_dataout <= nl11lll OR niOO0O10O; + wire_nl1l1lli_dataout <= nl1l1llO AND NOT(wire_niO01l0O_dataout); + wire_nl1l1lO_dataout <= nl11lOi AND NOT(niOO0O10O); + wire_nl1l1lOi_dataout <= nl1l1lll AND NOT(wire_niO01l0O_dataout); + wire_nl1l1lOl_dataout <= nl1l1lii AND NOT(wire_niO01l0O_dataout); + wire_nl1l1O1i_dataout <= wire_nl1l1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l1O1l_dataout <= wire_nl1l1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1l1O1O_dataout <= wire_nl1000i_w_lg_nl1l1llO7914w(0) WHEN (nlll0101i AND (wire_w_lg_niOO1l0iO7915w(0) AND (nlll0101i XOR nl1l1lOO))) = '1' ELSE nl1l1llO; + wire_nl1l1Oii_dataout <= nl1l1lOO WHEN niOO1l0iO = '1' ELSE nlll0101i; + wire_nl1l1Oli_dataout <= (nl1l010i XOR nl1l011l) AND NOT(wire_niO01l0O_dataout); + wire_nl1l1OOl_dataout <= nl1l011l AND NOT(wire_niO01O0O_dataout); + wire_nl1li000i_dataout <= wire_nl1lO1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li000l_dataout <= wire_nl1lO1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li000O_dataout <= wire_nl1lO1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li001i_dataout <= wire_nl1ll010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li001l_dataout <= wire_nl1ll010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li001O_dataout <= wire_nl1ll01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00ii_dataout <= wire_nl1lO1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00il_dataout <= wire_nl1lO1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00iO_dataout <= wire_nl1lO011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00li_dataout <= wire_nl1lO011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00ll_dataout <= wire_nl1lO011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00lO_dataout <= wire_nl1lO1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00O_dataout <= nl1li00i AND NOT(wire_niO01l0O_dataout); + wire_nl1li00Oi_dataout <= wire_nl1lO1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00Ol_dataout <= wire_nl1lO1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li00OO_dataout <= wire_nl1lO1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li010i_dataout <= wire_nl1ll1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li010l_dataout <= wire_nl1ll1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li010O_dataout <= wire_nl1ll1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li011i_dataout <= wire_nl1ll1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li011l_dataout <= wire_nl1ll1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li011O_dataout <= wire_nl1ll1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01i_dataout <= nl1li11l AND NOT(wire_niO01O0O_dataout); + wire_nl1li01ii_dataout <= wire_nl1ll1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01il_dataout <= wire_nl1ll1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01iO_dataout <= wire_nl1ll1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01li_dataout <= wire_nl1ll1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01ll_dataout <= wire_nl1ll1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01lO_dataout <= wire_nl1ll011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01O_dataout <= nl1li00l AND NOT(wire_niO01l0O_dataout); + wire_nl1li01Oi_dataout <= wire_nl1ll011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01Ol_dataout <= wire_nl1ll011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li01OO_dataout <= wire_nl1ll010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0i_dataout <= n1Oi00O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11OO; + wire_nl1li0i0i_dataout <= wire_nl1lO1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0i0l_dataout <= wire_nl1lO1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0i0O_dataout <= wire_nl1lO1lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0i1i_dataout <= wire_nl1lO1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0i1l_dataout <= wire_nl1lO1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0i1O_dataout <= wire_nl1lO1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0ii_dataout <= nl1li1OO AND NOT(wire_niO01l0O_dataout); + wire_nl1li0iii_dataout <= wire_nl1lO1llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0iil_dataout <= wire_nl1lO1lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0iiO_dataout <= wire_nl1lO1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0ili_dataout <= wire_nl1lO1lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0ill_dataout <= wire_nl1lO1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0ilO_dataout <= wire_nl1lO1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0iOi_dataout <= wire_nl1lO1l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0iOl_dataout <= wire_nl1lO1l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0iOO_dataout <= wire_nl1lO1l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0l_dataout <= n1Oi0ii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O101i; + wire_nl1li0l0i_dataout <= wire_nl1lO1lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0l0l_dataout <= wire_nl1lO1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0l0O_dataout <= nl00li0il AND NOT(wire_niO01O0O_dataout); + wire_nl1li0l1i_dataout <= wire_nl1lO1l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0l1l_dataout <= wire_nl1lO1l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0l1O_dataout <= wire_nl1lO1lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lii_dataout <= nl00l0O0i AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lil_dataout <= nl00l0O0l AND NOT(wire_niO01O0O_dataout); + wire_nl1li0liO_dataout <= nl00l0O0O AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lli_dataout <= nl00l0Oii AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lll_dataout <= nl00l0Oil AND NOT(wire_niO01O0O_dataout); + wire_nl1li0llO_dataout <= nl00l0OiO AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lO_dataout <= wire_nl1lii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lOi_dataout <= nl00l0Oli AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lOl_dataout <= nl00l0Oll AND NOT(wire_niO01O0O_dataout); + wire_nl1li0lOO_dataout <= nl00l0OlO AND NOT(wire_niO01O0O_dataout); + wire_nl1li0O_dataout <= n1Oi0il WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O101l; + wire_nl1li0O0i_dataout <= nl00li11i AND NOT(wire_niO01O0O_dataout); + wire_nl1li0O0l_dataout <= nl00li11l AND NOT(wire_niO01O0O_dataout); + wire_nl1li0O0O_dataout <= nl00li11O AND NOT(wire_niO01O0O_dataout); + wire_nl1li0O1i_dataout <= nl00l0OOi AND NOT(wire_niO01O0O_dataout); + wire_nl1li0O1l_dataout <= nl00l0OOl AND NOT(wire_niO01O0O_dataout); + wire_nl1li0O1O_dataout <= nl00l0OOO AND NOT(wire_niO01O0O_dataout); + wire_nl1li0Oi_dataout <= wire_nl1lii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0Oii_dataout <= nl00li10i AND NOT(wire_niO01O0O_dataout); + wire_nl1li0Oil_dataout <= nl00li10l AND NOT(wire_niO01O0O_dataout); + wire_nl1li0OiO_dataout <= nl00li10O AND NOT(wire_niO01O0O_dataout); + wire_nl1li0Ol_dataout <= wire_nl1lii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0Oli_dataout <= nl00li1ii AND NOT(wire_niO01O0O_dataout); + wire_nl1li0Oll_dataout <= nl00li1il AND NOT(wire_niO01O0O_dataout); + wire_nl1li0OlO_dataout <= nl00li1iO AND NOT(wire_niO01O0O_dataout); + wire_nl1li0OO_dataout <= wire_nl1lii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li0OOi_dataout <= nl00li1li AND NOT(wire_niO01O0O_dataout); + wire_nl1li0OOl_dataout <= nl00li1ll AND NOT(wire_niO01O0O_dataout); + wire_nl1li0OOO_dataout <= nl00li1lO AND NOT(wire_niO01O0O_dataout); + wire_nl1li100i_dataout <= wire_nl1ll11il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li100l_dataout <= wire_nl1ll11iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li100O_dataout <= wire_nl1ll11li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li101i_dataout <= wire_nl1ll110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li101l_dataout <= wire_nl1ll110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li101O_dataout <= wire_nl1ll11ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10i_dataout <= wire_nl1li1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1li10ii_dataout <= wire_nl1ll11ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10il_dataout <= wire_nl1ll11lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10iO_dataout <= wire_nl1ll11Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10l_dataout <= wire_nl1li1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1li10li_dataout <= wire_nl1ll11Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10ll_dataout <= wire_nl1ll11OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10lO_dataout <= wire_nl1ll101i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10O_dataout <= wire_nl1li1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1li10Oi_dataout <= wire_nl1ll101l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10Ol_dataout <= wire_nl1ll101O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li10OO_dataout <= wire_nl1ll100i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li110i_dataout <= wire_nl1liOOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li110l_dataout <= wire_nl1liOOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li110O_dataout <= wire_nl1liOOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li111i_dataout <= wire_nl1liOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li111l_dataout <= wire_nl1liOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li111O_dataout <= wire_nl1liOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11ii_dataout <= wire_nl1liOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11il_dataout <= wire_nl1liOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11iO_dataout <= wire_nl1liOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11li_dataout <= wire_nl1liOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11ll_dataout <= wire_nl1liOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11lO_dataout <= wire_nl1ll111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11O_dataout <= wire_nl1li1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1li11Oi_dataout <= wire_nl1ll111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11Ol_dataout <= wire_nl1ll111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li11OO_dataout <= wire_nl1ll110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1i_dataout <= n1Oi01O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11lO; + wire_nl1li1i0i_dataout <= wire_nl1ll10il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1i0l_dataout <= wire_nl1ll10iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1i0O_dataout <= wire_nl1ll10li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1i1i_dataout <= wire_nl1ll100l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1i1l_dataout <= wire_nl1ll100O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1i1O_dataout <= wire_nl1ll10ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1ii_dataout <= nl1li0il WHEN niOO1l0Ol = '1' ELSE nl1li1lO; + wire_nl1li1iii_dataout <= wire_nl1ll10ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1iil_dataout <= wire_nl1ll10lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1iiO_dataout <= wire_nl1ll10Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1il_dataout <= nl1li0iO WHEN niOO1l0Ol = '1' ELSE nl1l0OOl; + wire_nl1li1ili_dataout <= wire_nl1ll10Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1ill_dataout <= wire_nl1ll10OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1ilO_dataout <= wire_nl1ll1i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1iO_dataout <= nl1li0li WHEN niOO1l0Ol = '1' ELSE nl1l0OOO; + wire_nl1li1iOi_dataout <= wire_nl1ll1i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1iOl_dataout <= wire_nl1ll1i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1iOO_dataout <= wire_nl1ll1i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1l_dataout <= n1Oi00i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11Oi; + wire_nl1li1l0i_dataout <= wire_nl1ll1iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1l0l_dataout <= wire_nl1ll1iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1l0O_dataout <= wire_nl1ll1ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1l1i_dataout <= wire_nl1ll1i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1l1l_dataout <= wire_nl1ll1i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1l1O_dataout <= wire_nl1ll1iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1li_dataout <= nl1li0ll WHEN niOO1l0Ol = '1' ELSE nl1li11i; + wire_nl1li1lii_dataout <= wire_nl1ll1ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1lil_dataout <= wire_nl1ll1ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1liO_dataout <= wire_nl1ll1iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1lli_dataout <= wire_nl1ll1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1lll_dataout <= wire_nl1ll1iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1llO_dataout <= wire_nl1ll1l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1lOi_dataout <= wire_nl1ll1l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1lOl_dataout <= wire_nl1ll1l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1lOO_dataout <= wire_nl1ll1l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1O_dataout <= n1Oi00l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O11Ol; + wire_nl1li1O0i_dataout <= wire_nl1ll1lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1O0l_dataout <= wire_nl1ll1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1O0O_dataout <= wire_nl1ll1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1O1i_dataout <= wire_nl1ll1l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1O1l_dataout <= wire_nl1ll1l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1O1O_dataout <= wire_nl1ll1lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1Oii_dataout <= wire_nl1ll1lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1Oil_dataout <= wire_nl1ll1llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1OiO_dataout <= wire_nl1ll1lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1Ol_dataout <= nl1li01l AND NOT(wire_niO01O0O_dataout); + wire_nl1li1Oli_dataout <= wire_nl1ll1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1Oll_dataout <= wire_nl1ll1lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1OlO_dataout <= wire_nl1ll1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1OOi_dataout <= wire_nl1ll1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1OOl_dataout <= wire_nl1ll1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1li1OOO_dataout <= wire_nl1ll1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii00i_dataout <= wire_nl1iOOili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii00l_dataout <= wire_nl1iOOill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii00O_dataout <= wire_nl1iOOilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii01i_dataout <= wire_nl1iOOiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii01l_dataout <= wire_nl1iOOiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii01O_dataout <= wire_nl1iOOiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0i_dataout <= wire_nlOiillOl_dataout WHEN wire_w_lg_niOO1l0OO7876w(0) = '1' ELSE nl1li0il; + wire_nl1lii0ii_dataout <= wire_nl1iOOiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0il_dataout <= wire_nl1iOOiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0iO_dataout <= wire_nl1iOOiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0l_dataout <= wire_nlOiillOO_dataout WHEN wire_w_lg_niOO1l0OO7876w(0) = '1' ELSE nl1li0iO; + wire_nl1lii0li_dataout <= wire_nl1iOOl1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0ll_dataout <= wire_nl1iOOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0lO_dataout <= wire_nl1iOOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0O_dataout <= wire_nlOiilO1i_dataout WHEN wire_w_lg_niOO1l0OO7876w(0) = '1' ELSE nl1li0li; + wire_nl1lii0Oi_dataout <= wire_nl1iOOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0Ol_dataout <= wire_nl1iOOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii0OO_dataout <= wire_nl1iOOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii10i_dataout <= nl00li01i AND NOT(wire_niO01O0O_dataout); + wire_nl1lii10l_dataout <= nl00li01l AND NOT(wire_niO01O0O_dataout); + wire_nl1lii10O_dataout <= nl00li01O AND NOT(wire_niO01O0O_dataout); + wire_nl1lii11i_dataout <= nl00li1Oi AND NOT(wire_niO01O0O_dataout); + wire_nl1lii11l_dataout <= nl00li1Ol AND NOT(wire_niO01O0O_dataout); + wire_nl1lii11O_dataout <= nl00li1OO AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1i_dataout <= wire_nl1liiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1ii_dataout <= nl00li00i AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1il_dataout <= wire_nl1iOO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1iO_dataout <= wire_nl1iOO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1l_dataout <= wire_nl1000i_w_lg_nl1li00l7877w(0) WHEN (wire_w_lg_niOO1l0OO7876w(0) AND (NOT ((((NOT (wire_nlOiillOl_dataout XOR nl1li0il)) AND (NOT (wire_nlOiillOO_dataout XOR nl1li0iO))) AND (NOT (wire_nlOiilO1i_dataout XOR nl1li0li))) AND (NOT (wire_nlOiilO1l_dataout XOR nl1li0ll))))) = '1' ELSE nl1li00l; + wire_nl1lii1li_dataout <= wire_nl1iOOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1ll_dataout <= wire_nl1iOOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1lO_dataout <= wire_nl1iOOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1Oi_dataout <= wire_nl1iOOi0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1Ol_dataout <= wire_nl1iOOi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lii1OO_dataout <= wire_nl1iOOi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liii_dataout <= n1Oi0iO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O101O; + wire_nl1liii0i_dataout <= wire_nl1iOOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liii0l_dataout <= wire_nl1iOOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liii0O_dataout <= wire_nl1iOOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liii1i_dataout <= wire_nl1iOOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liii1l_dataout <= wire_nl1iOOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liii1O_dataout <= wire_nl1iOOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiii_dataout <= wire_nlOiilO1l_dataout WHEN wire_w_lg_niOO1l0OO7876w(0) = '1' ELSE nl1li0ll; + wire_nl1liiiii_dataout <= wire_nl1iOOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiiil_dataout <= wire_nl1iOOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiiiO_dataout <= wire_nl1iOOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiili_dataout <= wire_nl1iOOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiill_dataout <= wire_nl1iOOO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiilO_dataout <= wire_nl1iOOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiiOi_dataout <= wire_nl1iOOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiiOl_dataout <= wire_nl1iOOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiiOO_dataout <= wire_nl1iOOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liil_dataout <= n1Oi0li WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O100i; + wire_nl1liil0i_dataout <= wire_nl1iOOOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liil0l_dataout <= wire_nl1iOOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liil0O_dataout <= wire_nl1iOOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liil1i_dataout <= wire_nl1iOOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liil1l_dataout <= wire_nl1iOOOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liil1O_dataout <= wire_nl1iOOOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liilii_dataout <= wire_nl1iOOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liilil_dataout <= wire_nl1iOOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiliO_dataout <= wire_nl1iOOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liilli_dataout <= wire_nl1l1111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liilll_dataout <= wire_nl1l1111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liillO_dataout <= wire_nl1l1111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liilOi_dataout <= wire_nl1l1110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liilOl_dataout <= wire_nl1l1110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liilOO_dataout <= wire_nl1l1110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiO_dataout <= n1Oi0ll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O100l; + wire_nl1liiO0i_dataout <= wire_nl1l111li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiO0l_dataout <= wire_nl1l111ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiO0O_dataout <= wire_nl1l111lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiO1i_dataout <= wire_nl1l111ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiO1l_dataout <= wire_nl1l111il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiO1O_dataout <= wire_nl1l111iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOii_dataout <= wire_nl1l111Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOil_dataout <= wire_nl1l111Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOiO_dataout <= wire_nl1l111OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOli_dataout <= wire_nl1l1101i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOll_dataout <= wire_nl1l1101l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOlO_dataout <= wire_nl1l101ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOOi_dataout <= wire_nl1l101il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOOl_dataout <= wire_nl1l101iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1liiOOO_dataout <= wire_nl1l101li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil00i_dataout <= wire_nl1l100Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil00l_dataout <= wire_nl1l100OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil00O_dataout <= wire_nl1l10i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil01i_dataout <= wire_nl1l100ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil01l_dataout <= wire_nl1l100lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil01O_dataout <= wire_nl1l100Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0ii_dataout <= wire_nl1l10i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0il_dataout <= wire_nl1l10i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0iO_dataout <= wire_nl1l10i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0li_dataout <= wire_nl1l10i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0ll_dataout <= wire_nl1l10i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0lO_dataout <= wire_nl1l10iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0Oi_dataout <= wire_nl1l10iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil0Ol_dataout <= wire_nl1lili0O_dataout AND NOT(niOi1llli); + wire_nl1lil0OO_dataout <= wire_nl1liliii_dataout AND NOT(niOi1llli); + wire_nl1lil10i_dataout <= wire_nl1l101Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil10l_dataout <= wire_nl1l101OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil10O_dataout <= wire_nl1l1001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil11i_dataout <= wire_nl1l101ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil11l_dataout <= wire_nl1l101lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil11O_dataout <= wire_nl1l101Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1ii_dataout <= wire_nl1l1001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1il_dataout <= wire_nl1l1001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1iO_dataout <= wire_nl1l1000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1li_dataout <= wire_nl1l1000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1ll_dataout <= wire_nl1l1000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1lO_dataout <= wire_nl1l100ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1Oi_dataout <= wire_nl1l100il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1Ol_dataout <= wire_nl1l100iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lil1OO_dataout <= wire_nl1l100li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lili_dataout <= n1Oi0lO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O100O; + wire_nl1lili0i_dataout <= wire_nl1lilill_dataout AND NOT(niOi1llli); + wire_nl1lili0l_dataout <= niOi1lliO AND NOT(niOi1llli); + wire_nl1lili0O_dataout <= wire_nl1lililO_dataout AND NOT(niOi1lliO); + wire_nl1lili1i_dataout <= wire_nl1liliil_dataout AND NOT(niOi1llli); + wire_nl1lili1l_dataout <= wire_nl1liliiO_dataout AND NOT(niOi1llli); + wire_nl1lili1O_dataout <= wire_nl1lilili_dataout AND NOT(niOi1llli); + wire_nl1liliii_dataout <= wire_nl1liliOi_dataout AND NOT(niOi1lliO); + wire_nl1liliil_dataout <= wire_nl1liliOl_dataout AND NOT(niOi1lliO); + wire_nl1liliiO_dataout <= wire_nl1liliOO_dataout AND NOT(niOi1lliO); + wire_nl1lilil_dataout <= wire_nl1lilOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lilili_dataout <= wire_nl1lill1i_dataout AND NOT(niOi1lliO); + wire_nl1lilill_dataout <= niOi1llii AND NOT(niOi1lliO); + wire_nl1lililO_dataout <= wire_nl1lill1l_dataout AND NOT(niOi1llii); + wire_nl1liliO_dataout <= wire_nl1lilOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1liliOi_dataout <= wire_nl1lill1O_dataout AND NOT(niOi1llii); + wire_nl1liliOl_dataout <= wire_nl1lill0i_dataout AND NOT(niOi1llii); + wire_nl1liliOO_dataout <= wire_nl1lill0l_dataout AND NOT(niOi1llii); + wire_nl1lill_dataout <= n1Oi0Oi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10ii; + wire_nl1lill0i_dataout <= wire_nl1lillil_dataout AND NOT(niOi1ll0O); + wire_nl1lill0l_dataout <= niOi1ll0i AND NOT(niOi1ll0O); + wire_nl1lill0O_dataout <= wire_nl1lilliO_dataout AND NOT(niOi1ll0i); + wire_nl1lill1i_dataout <= niOi1ll0O AND NOT(niOi1llii); + wire_nl1lill1l_dataout <= wire_nl1lill0O_dataout AND NOT(niOi1ll0O); + wire_nl1lill1O_dataout <= wire_nl1lillii_dataout AND NOT(niOi1ll0O); + wire_nl1lilli_dataout <= wire_nl1lilOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lillii_dataout <= wire_nl1lillli_dataout AND NOT(niOi1ll0i); + wire_nl1lillil_dataout <= niOi1ll1O AND NOT(niOi1ll0i); + wire_nl1lilliO_dataout <= wire_w_lg_niOi1llll55853w(0) AND NOT(niOi1ll1O); + wire_nl1lilll_dataout <= wire_nl1liO1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lillli_dataout <= niOi1llll AND NOT(niOi1ll1O); + wire_nl1lillO_dataout <= wire_nl1liO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lilO_dataout <= n1Oi0Ol WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10il; + wire_nl1lilOi_dataout <= nl1liOOO WHEN niOO1li1i = '1' ELSE nl1liO0i; + wire_nl1lilOii_dataout <= wire_nl1lilOli_dataout AND NOT(niOi1lllO); + wire_nl1lilOil_dataout <= wire_nl1lilOll_dataout AND NOT(niOi1lllO); + wire_nl1lilOiO_dataout <= niOi1llOi AND NOT(niOi1lllO); + wire_nl1lilOl_dataout <= nl1ll11i WHEN niOO1li1i = '1' ELSE nl1lil1O; + wire_nl1lilOli_dataout <= wire_w_lg_niOi1llll55853w(0) AND NOT(niOi1llOi); + wire_nl1lilOll_dataout <= niOi1llll AND NOT(niOi1llOi); + wire_nl1lilOO_dataout <= nl1ll11l WHEN niOO1li1i = '1' ELSE nl1lil0i; + wire_nl1lilOOi_dataout <= wire_nl1iliilO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1iOlO; + wire_nl1lilOOl_dataout <= wire_nl1iliiOi_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1iOOi; + wire_nl1lilOOO_dataout <= wire_nl1iliiOl_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1iOOl; + wire_nl1liO00i_dataout <= wire_nl1iliO1O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l01O; + wire_nl1liO00l_dataout <= wire_nl1iliO0i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l00i; + wire_nl1liO00O_dataout <= wire_nl1iliO0l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l00l; + wire_nl1liO01i_dataout <= wire_nl1ililOO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1OO; + wire_nl1liO01l_dataout <= wire_nl1iliO1i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l01i; + wire_nl1liO01O_dataout <= wire_nl1iliO1l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l01l; + wire_nl1liO0ii_dataout <= wire_nl1iliO0O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l00O; + wire_nl1liO0il_dataout <= wire_nl1iliOii_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0ii; + wire_nl1liO0iO_dataout <= wire_nl1iliOil_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0il; + wire_nl1liO0li_dataout <= wire_nl1iliOiO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0iO; + wire_nl1liO0ll_dataout <= wire_nl1iliOli_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0li; + wire_nl1liO0lO_dataout <= wire_nl1iliOll_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0ll; + wire_nl1liO0O_dataout <= nl1liOiO AND NOT(wire_niO01O0O_dataout); + wire_nl1liO0Oi_dataout <= wire_nl1iliOlO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0lO; + wire_nl1liO0Ol_dataout <= wire_nl1iliOOi_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0Oi; + wire_nl1liO0OO_dataout <= wire_nl1iliOOl_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0Ol; + wire_nl1liO10i_dataout <= wire_nl1ilil1O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l11O; + wire_nl1liO10l_dataout <= wire_nl1ilil0i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l10i; + wire_nl1liO10O_dataout <= wire_nl1ilil0l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l10l; + wire_nl1liO11i_dataout <= wire_nl1iliiOO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1iOOO; + wire_nl1liO11l_dataout <= wire_nl1ilil1i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l11i; + wire_nl1liO11O_dataout <= wire_nl1ilil1l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l11l; + wire_nl1liO1i_dataout <= nl1ll11O WHEN niOO1li1i = '1' ELSE nl1lil0l; + wire_nl1liO1ii_dataout <= wire_nl1ilil0O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l10O; + wire_nl1liO1il_dataout <= wire_nl1ililii_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1ii; + wire_nl1liO1iO_dataout <= wire_nl1ililil_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1il; + wire_nl1liO1l_dataout <= nl1ll10i WHEN niOO1li1i = '1' ELSE nl1lil0O; + wire_nl1liO1li_dataout <= wire_nl1ililiO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1iO; + wire_nl1liO1ll_dataout <= wire_nl1ililli_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1li; + wire_nl1liO1lO_dataout <= wire_nl1ililll_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1ll; + wire_nl1liO1Oi_dataout <= wire_nl1ilillO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1lO; + wire_nl1liO1Ol_dataout <= wire_nl1ililOi_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1Oi; + wire_nl1liO1OO_dataout <= wire_nl1ililOl_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l1Ol; + wire_nl1liOi_dataout <= n1Oi0OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1liOi0i_dataout <= wire_nl1ill11O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1li1O; + wire_nl1liOi0l_dataout <= wire_nl1ill10i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1li0i; + wire_nl1liOi0O_dataout <= wire_nl1ill10l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1li0l; + wire_nl1liOi1i_dataout <= wire_nl1iliOOO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1l0OO; + wire_nl1liOi1l_dataout <= wire_nl1ill11i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1li1i; + wire_nl1liOi1O_dataout <= wire_nl1ill11l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1li1l; + wire_nl1liOiii_dataout <= wire_nl1ill10O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1li0O; + wire_nl1liOiil_dataout <= wire_nl1ill1ii_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1liii; + wire_nl1liOiiO_dataout <= wire_nl1ill1il_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1liil; + wire_nl1liOil_dataout <= nl1lilii AND NOT(wire_niO01O0O_dataout); + wire_nl1liOili_dataout <= wire_nl1ill1iO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1liiO; + wire_nl1liOill_dataout <= wire_nl1ill1li_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1lili; + wire_nl1liOilO_dataout <= wire_nl1ill1ll_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1lill; + wire_nl1liOiOi_dataout <= wire_nl1ill1lO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1lilO; + wire_nl1liOiOl_dataout <= wire_nl1ill1Oi_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1liOi; + wire_nl1liOiOO_dataout <= wire_nl1ill1Ol_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1liOl; + wire_nl1liOl_dataout <= n1Oii1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1liOl0i_dataout <= wire_nl1ill01O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1ll1O; + wire_nl1liOl0l_dataout <= wire_nl1ill00i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1ll0i; + wire_nl1liOl0O_dataout <= wire_nl1ill00l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1ll0l; + wire_nl1liOl1i_dataout <= wire_nl1ill1OO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1liOO; + wire_nl1liOl1l_dataout <= wire_nl1ill01i_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1ll1i; + wire_nl1liOl1O_dataout <= wire_nl1ill01l_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1ll1l; + wire_nl1liOli_dataout <= nl1liOlO AND NOT(wire_niO01l0O_dataout); + wire_nl1liOlii_dataout <= wire_nl1ill00O_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1ll0O; + wire_nl1liOlil_dataout <= wire_nl1ill0ii_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1llii; + wire_nl1liOliO_dataout <= wire_nl1ill0il_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1llil; + wire_nl1liOlli_dataout <= wire_nl1ill0iO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1lliO; + wire_nl1liOlll_dataout <= wire_nl1ill0li_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1llli; + wire_nl1liOllO_dataout <= wire_nl1ill0ll_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1llll; + wire_nl1liOlOi_dataout <= wire_nl1ill0lO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1lllO; + wire_nl1liOlOl_dataout <= wire_nl1ill0Oi_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1llOi; + wire_nl1liOlOO_dataout <= wire_nl1ill0Ol_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1llOl; + wire_nl1liOO_dataout <= n1Oii1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1liOO0i_dataout <= wire_nl1iOOi1i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lO1O; + wire_nl1liOO0l_dataout <= wire_nl1iOOi1l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lO0i; + wire_nl1liOO0O_dataout <= wire_nl1iOOi1O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lO0l; + wire_nl1liOO1i_dataout <= wire_nl1ill0OO_dataout WHEN wire_nlill0Oll_w_lg_nl1iil10O55851w(0) = '1' ELSE nl1l1llOO; + wire_nl1liOO1l_dataout <= wire_nl1iOO0Ol_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lO1i; + wire_nl1liOO1O_dataout <= wire_nl1iOO0OO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lO1l; + wire_nl1liOOi_dataout <= nl1liOll AND NOT(wire_niO01l0O_dataout); + wire_nl1liOOii_dataout <= wire_nl1iOOi0i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lO0O; + wire_nl1liOOil_dataout <= wire_nl1iOOi0l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOii; + wire_nl1liOOiO_dataout <= wire_nl1iOOi0O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOil; + wire_nl1liOOl_dataout <= nl1liOii AND NOT(wire_niO01l0O_dataout); + wire_nl1liOOli_dataout <= wire_nl1iOOiii_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOiO; + wire_nl1liOOll_dataout <= wire_nl1iOOiil_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOli; + wire_nl1liOOlO_dataout <= wire_nl1iOOiiO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOll; + wire_nl1liOOOi_dataout <= wire_nl1iOOili_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOlO; + wire_nl1liOOOl_dataout <= wire_nl1iOOill_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOOi; + wire_nl1liOOOO_dataout <= wire_nl1iOOilO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOOl; + wire_nl1ll010i_dataout <= wire_nl1l10i0l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l0111O; + wire_nl1ll010l_dataout <= wire_nl1l10i0O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l0110i; + wire_nl1ll010O_dataout <= wire_nl1l10iii_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l0110l; + wire_nl1ll011i_dataout <= wire_nl1l10i1l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOOO; + wire_nl1ll011l_dataout <= wire_nl1l10i1O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l0111i; + wire_nl1ll011O_dataout <= wire_nl1l10i0i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l0111l; + wire_nl1ll01i_dataout <= wire_nlOiiOiii_dataout WHEN wire_w_lg_niOO1li1O7856w(0) = '1' ELSE nl1ll11O; + wire_nl1ll01ii_dataout <= wire_nl1l10iil_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l0110O; + wire_nl1ll01l_dataout <= wire_nlOiiOiil_dataout WHEN wire_w_lg_niOO1li1O7856w(0) = '1' ELSE nl1ll10i; + wire_nl1ll0i_dataout <= n1Oii0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1ll0l_dataout <= n1Oiiii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1ll0O_dataout <= n1Oiiil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1ll0O0i_dataout <= wire_nl1lliill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0O0l_dataout <= wire_nl1lliiOO_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0O0O_dataout <= wire_nl1llil1i_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0O1i_dataout <= ((niOi01i0l AND nl1OilOii) AND ((wire_nl1lOOlOi_w_lg_dataout55789w(0) AND (niOi1llOl AND niOi1O11l)) OR wire_nl1lOOO0l_w_lg_w_lg_dataout52008w55818w(0))) AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0O1l_dataout <= wire_nl1lli01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0O1O_dataout <= wire_nl1lli00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0Oii_dataout <= wire_nl1llil1l_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0Oil_dataout <= wire_nl1llil1O_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0OiO_dataout <= wire_nl1llil0i_o OR wire_niO01O0O_dataout; + wire_nl1ll0Oli_dataout <= wire_nl1llil0O_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0Oll_dataout <= wire_nl1llilii_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0OlO_dataout <= wire_nl1llilil_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0OOi_dataout <= wire_nl1lliliO_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0OOl_dataout <= wire_nl1llilli_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll0OOO_dataout <= wire_nl1llilll_o AND NOT(wire_niO01O0O_dataout); + wire_nl1ll100i_dataout <= wire_nl1iOOO1i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O01O; + wire_nl1ll100l_dataout <= wire_nl1iOOO1l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O00i; + wire_nl1ll100O_dataout <= wire_nl1iOOO1O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O00l; + wire_nl1ll101i_dataout <= wire_nl1iOOlOi_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1OO; + wire_nl1ll101l_dataout <= wire_nl1iOOlOl_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O01i; + wire_nl1ll101O_dataout <= wire_nl1iOOlOO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O01l; + wire_nl1ll10ii_dataout <= wire_nl1iOOO0i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O00O; + wire_nl1ll10il_dataout <= wire_nl1iOOO0l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0ii; + wire_nl1ll10iO_dataout <= wire_nl1iOOO0O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0il; + wire_nl1ll10l_dataout <= wire_nl1ll1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll10li_dataout <= wire_nl1iOOOii_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0iO; + wire_nl1ll10ll_dataout <= wire_nl1iOOOil_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0li; + wire_nl1ll10lO_dataout <= wire_nl1iOOOiO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0ll; + wire_nl1ll10O_dataout <= wire_nl1ll1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll10Oi_dataout <= wire_nl1iOOOli_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0lO; + wire_nl1ll10Ol_dataout <= wire_nl1iOOOll_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0Oi; + wire_nl1ll10OO_dataout <= wire_nl1iOOOlO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0Ol; + wire_nl1ll110i_dataout <= wire_nl1iOOl1i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O11O; + wire_nl1ll110l_dataout <= wire_nl1iOOl1l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O10i; + wire_nl1ll110O_dataout <= wire_nl1iOOl1O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O10l; + wire_nl1ll111i_dataout <= wire_nl1iOOiOi_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1lOOO; + wire_nl1ll111l_dataout <= wire_nl1iOOiOl_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O11i; + wire_nl1ll111O_dataout <= wire_nl1iOOiOO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O11l; + wire_nl1ll11ii_dataout <= wire_nl1iOOl0i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O10O; + wire_nl1ll11il_dataout <= wire_nl1iOOl0l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1ii; + wire_nl1ll11iO_dataout <= wire_nl1iOOl0O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1il; + wire_nl1ll11li_dataout <= wire_nl1iOOlii_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1iO; + wire_nl1ll11ll_dataout <= wire_nl1iOOlil_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1li; + wire_nl1ll11lO_dataout <= wire_nl1iOOliO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1ll; + wire_nl1ll11Oi_dataout <= wire_nl1iOOlli_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1lO; + wire_nl1ll11Ol_dataout <= wire_nl1iOOlll_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1Oi; + wire_nl1ll11OO_dataout <= wire_nl1iOOllO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O1Ol; + wire_nl1ll1i_dataout <= n1Oii1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1ll1i0i_dataout <= wire_nl1l1111i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oi1O; + wire_nl1ll1i0l_dataout <= wire_nl1l1111l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oi0i; + wire_nl1ll1i0O_dataout <= wire_nl1l1111O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oi0l; + wire_nl1ll1i1i_dataout <= wire_nl1iOOOOi_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1O0OO; + wire_nl1ll1i1l_dataout <= wire_nl1iOOOOl_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oi1i; + wire_nl1ll1i1O_dataout <= wire_nl1iOOOOO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oi1l; + wire_nl1ll1ii_dataout <= wire_nl1ll1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll1iii_dataout <= wire_nl1l1110i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oi0O; + wire_nl1ll1iil_dataout <= wire_nl1l1110l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oiii; + wire_nl1ll1iiO_dataout <= wire_nl1l1110O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oiil; + wire_nl1ll1il_dataout <= wire_nl1ll1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll1ili_dataout <= wire_nl1l111ii_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1OiiO; + wire_nl1ll1ill_dataout <= wire_nl1l111il_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oili; + wire_nl1ll1ilO_dataout <= wire_nl1l111iO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Oill; + wire_nl1ll1iO_dataout <= wire_nl1ll01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll1iOi_dataout <= wire_nl1l111li_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1OilO; + wire_nl1ll1iOl_dataout <= wire_nl1l111ll_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1OiOi; + wire_nl1ll1iOO_dataout <= wire_nl1l111lO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1OiOl; + wire_nl1ll1l_dataout <= n1Oii0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1ll1l0i_dataout <= wire_nl1l1101i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Ol1O; + wire_nl1ll1l0l_dataout <= wire_nl1l1101l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Ol0i; + wire_nl1ll1l0O_dataout <= wire_nl1l101ii_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1Ol0l; + wire_nl1ll1l1i_dataout <= wire_nl1l111Oi_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1OiOO; + wire_nl1ll1l1l_dataout <= wire_nl1l111Ol_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Ol1i; + wire_nl1ll1l1O_dataout <= wire_nl1l111OO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOii55850w(0) = '1' ELSE nl1l1Ol1l; + wire_nl1ll1li_dataout <= wire_nl1ll01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1ll1lii_dataout <= wire_nl1l101il_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1Ol0O; + wire_nl1ll1lil_dataout <= wire_nl1l101iO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1Olii; + wire_nl1ll1liO_dataout <= wire_nl1l101li_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1Olil; + wire_nl1ll1ll_dataout <= wire_nl1000i_w_lg_nl1liOlO7857w(0) WHEN (wire_w_lg_niOO1li1O7856w(0) AND wire_w_lg_niOO1li1l7858w(0)) = '1' ELSE nl1liOlO; + wire_nl1ll1lli_dataout <= wire_nl1l101ll_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OliO; + wire_nl1ll1lll_dataout <= wire_nl1l101lO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1Olli; + wire_nl1ll1llO_dataout <= wire_nl1l101Oi_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1Olll; + wire_nl1ll1lOi_dataout <= wire_nl1l101Ol_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OllO; + wire_nl1ll1lOl_dataout <= wire_nl1l101OO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OlOi; + wire_nl1ll1lOO_dataout <= wire_nl1l1001i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OlOl; + wire_nl1ll1O_dataout <= n1Oii0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1ll1O0i_dataout <= wire_nl1l1000l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OO1O; + wire_nl1ll1O0l_dataout <= wire_nl1l1000O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OO0i; + wire_nl1ll1O0O_dataout <= wire_nl1l100ii_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OO0l; + wire_nl1ll1O1i_dataout <= wire_nl1l1001l_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OlOO; + wire_nl1ll1O1l_dataout <= wire_nl1l1001O_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OO1i; + wire_nl1ll1O1O_dataout <= wire_nl1l1000i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OO1l; + wire_nl1ll1Oi_dataout <= wire_nlOiiOi0i_dataout WHEN wire_w_lg_niOO1li1O7856w(0) = '1' ELSE nl1liOOO; + wire_nl1ll1Oii_dataout <= wire_nl1l100il_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OO0O; + wire_nl1ll1Oil_dataout <= wire_nl1l100iO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOii; + wire_nl1ll1OiO_dataout <= wire_nl1l100li_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOil; + wire_nl1ll1Ol_dataout <= wire_nlOiiOi0l_dataout WHEN wire_w_lg_niOO1li1O7856w(0) = '1' ELSE nl1ll11i; + wire_nl1ll1Oli_dataout <= wire_nl1l100ll_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOiO; + wire_nl1ll1Oll_dataout <= wire_nl1l100lO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOli; + wire_nl1ll1OlO_dataout <= wire_nl1l100Oi_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOll; + wire_nl1ll1OO_dataout <= wire_nlOiiOi0O_dataout WHEN wire_w_lg_niOO1li1O7856w(0) = '1' ELSE nl1ll11l; + wire_nl1ll1OOi_dataout <= wire_nl1l100Ol_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOlO; + wire_nl1ll1OOl_dataout <= wire_nl1l100OO_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOOi; + wire_nl1ll1OOO_dataout <= wire_nl1l10i1i_dataout WHEN wire_nlill0Oll_w_lg_nl1l1iOil55849w(0) = '1' ELSE nl1l1OOOl; + wire_nl1lli00l_dataout <= wire_nl1lli0ii_dataout WHEN nl1ll0iOl = '1' ELSE wire_nl1lli00O_dataout; + wire_nl1lli00O_dataout <= nl1ll0iiO AND NOT(nl1ll0ilO); + wire_nl1lli01i_dataout <= wire_nl1lli01l_dataout OR ((nl1Ol1l0l AND nl1ll0iOi) AND niOi1Ol0i); + wire_nl1lli01l_dataout <= nl1ll0iil AND NOT(niOi1Olil); + wire_nl1lli0i_dataout <= wire_nl1lliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lli0ii_dataout <= (niOi01i0l AND (wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND (((wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55798w(0) OR wire_nl1lOOl0l_w_lg_dataout55800w(0)) OR wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55802w(0)) OR wire_nl1lOOl0l_w_lg_dataout55805w(0)))) OR (wire_w_lg_niOi01i0l54724w(0) AND (wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND (niOi1lO1l OR niOi1llOO))); + wire_nl1lli0l_dataout <= wire_nl1lliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lli0O_dataout <= niOO1li0i WHEN niOO1li0l = '1' ELSE (niOO1li0i AND nl1ll0Ol); + wire_nl1lli10i_dataout <= wire_nl1llilOO_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli10l_dataout <= wire_nl1lliO1i_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli10O_dataout <= wire_nl1lliO1O_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli11i_dataout <= wire_nl1llillO_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli11l_dataout <= wire_nl1llilOi_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli11O_dataout <= wire_nl1llilOl_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli1ii_dataout <= wire_nl1lliO0l_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli1il_dataout <= wire_nl1llil0l_o AND NOT(wire_niO01O0O_dataout); + wire_nl1lli1l_dataout <= wire_nl1lliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lli1O_dataout <= wire_nl1lli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1llii_dataout <= n1OiiiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lliii_dataout <= nl1ll0Ol WHEN niOO1li0l = '1' ELSE nl1llilO; + wire_nl1lliil_dataout <= wire_nl1llill_o(0) AND NOT(niOO1li0l); + wire_nl1lliill_dataout <= (NOT (wire_nl1lOOO0i_w_lg_dataout55790w(0) OR wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55791w(0))) WHEN nl1ll0iOl = '1' ELSE nl1ll0ili; + wire_nl1lliiO_dataout <= wire_nl1llill_o(1) AND NOT(niOO1li0l); + wire_nl1llil_dataout <= n1Oiili AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lliO_dataout <= n1Oiill AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lliO0O_dataout <= nl1ll0ill AND NOT(nl1Ol1l0l); + wire_nl1lliOii_dataout <= nl1ll0ilO AND NOT(nl1Ol1l0l); + wire_nl1lliOil_dataout <= nl1ll0iOi AND NOT(nl1Ol1l0l); + wire_nl1lliOiO_dataout <= nl1ll0iOl AND NOT(nl1Ol1l0l); + wire_nl1lliOli_dataout <= nl1ll0iOO OR nl1Ol1l0l; + wire_nl1lliOll_dataout <= nl1ll0ill AND NOT(wire_nllillil_w_lg_dataout55059w(0)); + wire_nl1lliOlO_dataout <= nl1ll0ilO AND NOT(wire_nllillil_w_lg_dataout55059w(0)); + wire_nl1lliOOi_dataout <= nl1ll0iOi AND NOT(wire_nllillil_w_lg_dataout55059w(0)); + wire_nl1lliOOl_dataout <= wire_nl1lll11O_dataout WHEN wire_nllillil_w_lg_dataout55059w(0) = '1' ELSE nl1ll0iOl; + wire_nl1lliOOO_dataout <= wire_nl1lll10i_dataout WHEN wire_nllillil_w_lg_dataout55059w(0) = '1' ELSE nl1ll0iOO; + wire_nl1lll00i_dataout <= nl1ll0iOO AND NOT(niOi1lOil); + wire_nl1lll00l_dataout <= nl1ll0lOl AND NOT(niOi1lOil); + wire_nl1lll00O_dataout <= (wire_nlill0Oll_w_lg_nl1ll0llO55563w(0) OR (nl1ll0iiO AND nl1ll0iil)) OR NOT(wire_w_lg_niOi1lOil55566w(0)); + wire_nl1lll01i_dataout <= nl1ll0ilO OR niOi1lOil; + wire_nl1lll01l_dataout <= nl1ll0iOi AND NOT(niOi1lOil); + wire_nl1lll01O_dataout <= nl1ll0iOl AND NOT(niOi1lOil); + wire_nl1lll0i_dataout <= wire_nl1lllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lll0ii_dataout <= nl1ll0l1i AND NOT(niOi1lOli); + wire_nl1lll0il_dataout <= wire_nl1llli1O_dataout AND NOT(niOi1lOli); + wire_nl1lll0iO_dataout <= wire_nl1llli0i_dataout AND NOT(niOi1lOli); + wire_nl1lll0l_dataout <= wire_nl1llliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lll0li_dataout <= wire_nl1llli0l_dataout AND NOT(niOi1lOli); + wire_nl1lll0ll_dataout <= wire_nl1llli0O_dataout AND NOT(niOi1lOli); + wire_nl1lll0lO_dataout <= wire_nl1llliii_dataout AND NOT(niOi1lOli); + wire_nl1lll0O_dataout <= niOO1li0O WHEN niOO1liii = '1' ELSE (niOO1li0O AND nl1lliOl); + wire_nl1lll0Oi_dataout <= wire_nl1llliil_dataout AND NOT(niOi1lOli); + wire_nl1lll0Ol_dataout <= wire_nl1llliiO_dataout AND NOT(niOi1lOli); + wire_nl1lll0OO_dataout <= wire_nl1lllili_dataout AND NOT(niOi1lOli); + wire_nl1lll10i_dataout <= wire_nl1lll1ii_dataout AND NOT(niOi1O0ll); + wire_nl1lll10l_dataout <= nl00lll0O WHEN niOi1O0ll = '1' ELSE wire_nl1lll1il_dataout; + wire_nl1lll10O_dataout <= wire_nl1lll1iO_dataout OR niOi1lOii; + wire_nl1lll11i_dataout <= wire_nl1lll10l_dataout WHEN wire_nllillil_w_lg_dataout55059w(0) = '1' ELSE nl1ll0lOl; + wire_nl1lll11l_dataout <= nl1ll0lOi AND NOT(wire_nllillil_w_lg_dataout55059w(0)); + wire_nl1lll11O_dataout <= wire_nl1lll10O_dataout OR niOi1O0ll; + wire_nl1lll1ii_dataout <= wire_nl1lll1li_dataout AND NOT(niOi1lOii); + wire_nl1lll1il_dataout <= niOi1Oiil WHEN niOi1lOii = '1' ELSE wire_nl1lll1ll_dataout; + wire_nl1lll1iO_dataout <= niOi1lO0O OR niOi1O10i; + wire_nl1lll1l_dataout <= wire_nl1lllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lll1li_dataout <= wire_w_lg_niOi1lO0O55569w(0) AND NOT(niOi1O10i); + wire_nl1lll1ll_dataout <= niOi0110O WHEN niOi1O10i = '1' ELSE wire_nl1lll1lO_dataout; + wire_nl1lll1lO_dataout <= niOi1Oiil AND niOi1lO0O; + wire_nl1lll1O_dataout <= wire_nl1lll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lll1OO_dataout <= nl1ll0ill AND NOT(niOi1lOil); + wire_nl1llli_dataout <= n1OiilO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1llli0i_dataout <= wire_nl1llliOi_o(2) WHEN niOi1Ol0l = '1' ELSE nl1ll0l1O; + wire_nl1llli0l_dataout <= wire_nl1llliOi_o(3) WHEN niOi1Ol0l = '1' ELSE nl1ll0l0i; + wire_nl1llli0O_dataout <= wire_nl1llliOi_o(4) WHEN niOi1Ol0l = '1' ELSE nl1ll0l0l; + wire_nl1llli1i_dataout <= wire_nl1lllill_dataout AND NOT(niOi1lOli); + wire_nl1llli1l_dataout <= wire_nl1lllilO_dataout AND NOT(niOi1lOli); + wire_nl1llli1O_dataout <= wire_nl1llliOi_o(1) WHEN niOi1Ol0l = '1' ELSE nl1ll0l1l; + wire_nl1lllii_dataout <= nl1lliOl WHEN niOO1liii = '1' ELSE nl1llllO; + wire_nl1llliii_dataout <= wire_nl1llliOi_o(5) WHEN niOi1Ol0l = '1' ELSE nl1ll0l0O; + wire_nl1llliil_dataout <= wire_nl1llliOi_o(6) WHEN niOi1Ol0l = '1' ELSE nl1ll0lii; + wire_nl1llliiO_dataout <= wire_nl1llliOi_o(7) WHEN niOi1Ol0l = '1' ELSE nl1ll0lil; + wire_nl1lllil_dataout <= wire_nl1lllll_o(0) AND NOT(niOO1liii); + wire_nl1lllili_dataout <= wire_nl1llliOi_o(8) WHEN niOi1Ol0l = '1' ELSE nl1ll0liO; + wire_nl1lllill_dataout <= wire_nl1llliOi_o(9) WHEN niOi1Ol0l = '1' ELSE nl1ll0lli; + wire_nl1lllilO_dataout <= wire_nl1llliOi_o(10) WHEN niOi1Ol0l = '1' ELSE nl1ll0lll; + wire_nl1llliO_dataout <= wire_nl1lllll_o(1) AND NOT(niOO1liii); + wire_nl1llliOO_dataout <= wire_nl1llll1O_dataout AND NOT(niOi1lOOi); + wire_nl1llll_dataout <= n1OiiOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1llll0i_dataout <= wire_nl1llll0O_dataout AND NOT(wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0)); + wire_nl1llll0l_dataout <= niOi1lOll OR niOi1lOlO; + wire_nl1llll0O_dataout <= wire_w_lg_niOi1lOll55514w(0) AND NOT(niOi1lOlO); + wire_nl1llll1i_dataout <= wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0) AND NOT(niOi1lOOi); + wire_nl1llll1l_dataout <= wire_nl1llll0i_dataout AND NOT(niOi1lOOi); + wire_nl1llll1O_dataout <= wire_nl1llll0l_dataout AND NOT(wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0)); + wire_nl1llllOO_dataout <= wire_nl1lllOll_dataout AND NOT(niOi1lOOO); + wire_nl1lllO_dataout <= n1OiiOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lllO0i_dataout <= wire_nl1lllOOO_dataout AND NOT(niOi1lOOO); + wire_nl1lllO0l_dataout <= wire_nl1llO11i_dataout AND NOT(niOi1lOOO); + wire_nl1lllO0O_dataout <= wire_nl1llO11l_dataout AND NOT(niOi1lOOO); + wire_nl1lllO1i_dataout <= wire_nl1lllOlO_dataout AND NOT(niOi1lOOO); + wire_nl1lllO1l_dataout <= wire_nl1lllOOi_dataout AND NOT(niOi1lOOO); + wire_nl1lllO1O_dataout <= wire_nl1lllOOl_dataout AND NOT(niOi1lOOO); + wire_nl1lllOii_dataout <= wire_nl1llO11O_dataout AND NOT(niOi1lOOO); + wire_nl1lllOil_dataout <= wire_nl1llO10i_dataout AND NOT(niOi1lOOO); + wire_nl1lllOiO_dataout <= wire_nl1llO10l_dataout AND NOT(niOi1lOOO); + wire_nl1lllOli_dataout <= wire_nl1llO10O_dataout AND NOT(niOi1lOOO); + wire_nl1lllOll_dataout <= wire_nl1llOlOi_dataout AND NOT(niOi1lOOl); + wire_nl1lllOlO_dataout <= wire_nl1llO1ii_o(1) AND NOT(niOi1lOOl); + wire_nl1lllOOi_dataout <= wire_nl1llO1ii_o(2) AND NOT(niOi1lOOl); + wire_nl1lllOOl_dataout <= wire_nl1llO1ii_o(3) AND NOT(niOi1lOOl); + wire_nl1lllOOO_dataout <= wire_nl1llO1ii_o(4) AND NOT(niOi1lOOl); + wire_nl1llO0i_dataout <= wire_nl1llO0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1llO0l_dataout <= nl1lO10i WHEN niOO1liil = '1' ELSE nl1llOil; + wire_nl1llO0ll_dataout <= wire_nl1llOi1l_dataout AND NOT(niOi1O0ll); + wire_nl1llO0lO_dataout <= wire_nl1llOi1O_dataout AND NOT(niOi1O0ll); + wire_nl1llO0O_dataout <= nl1lO10l WHEN niOO1liil = '1' ELSE nl1llO1i; + wire_nl1llO0Oi_dataout <= wire_nl1llOi0i_dataout AND NOT(niOi1O0ll); + wire_nl1llO0Ol_dataout <= wire_nl1llOi0l_dataout OR niOi1O0ll; + wire_nl1llO0OO_dataout <= wire_nl1llOi0O_dataout AND NOT(niOi1O0ll); + wire_nl1llO10i_dataout <= wire_nl1llO1ii_o(8) AND NOT(niOi1lOOl); + wire_nl1llO10l_dataout <= wire_nl1llO1ii_o(9) AND NOT(niOi1lOOl); + wire_nl1llO10O_dataout <= wire_nl1llO1ii_o(10) AND NOT(niOi1lOOl); + wire_nl1llO11i_dataout <= wire_nl1llO1ii_o(5) AND NOT(niOi1lOOl); + wire_nl1llO11l_dataout <= wire_nl1llO1ii_o(6) AND NOT(niOi1lOOl); + wire_nl1llO11O_dataout <= wire_nl1llO1ii_o(7) AND NOT(niOi1lOOl); + wire_nl1llO1lO_dataout <= wire_nl1llO1Oi_dataout AND nl1ll0lOl; + wire_nl1llO1O_dataout <= wire_nl1llO0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1llO1Oi_dataout <= (niOi01i0l AND (wire_nlill0Oll_w_lg_nl1OlO11l55412w(0) OR wire_w_lg_niOi1O11O55414w(0))) OR (wire_w_lg_niOi01i0l54724w(0) AND wire_nlill0Oll_w_lg_nl1OlO11l55419w(0)); + wire_nl1llOi_dataout <= n1OiiOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1llOi0i_dataout <= wire_nl1llOili_dataout AND NOT(niOi1O10O); + wire_nl1llOi0l_dataout <= wire_nl1llOill_dataout OR niOi1O10O; + wire_nl1llOi0O_dataout <= wire_nl1llOilO_dataout AND NOT(niOi1O10O); + wire_nl1llOi1i_dataout <= nl00lll0O WHEN niOi1O0ll = '1' ELSE wire_nl1llOiii_dataout; + wire_nl1llOi1l_dataout <= wire_nl1llOiil_dataout AND NOT(niOi1O10O); + wire_nl1llOi1O_dataout <= wire_nl1llOiiO_dataout AND NOT(niOi1O10O); + wire_nl1llOiii_dataout <= niOi1Oiil WHEN niOi1O10O = '1' ELSE wire_nl1llOiOi_dataout; + wire_nl1llOiil_dataout <= nl1ll0ill AND NOT(niOi1O10i); + wire_nl1llOiiO_dataout <= nl1ll0ilO AND NOT(niOi1O10i); + wire_nl1llOili_dataout <= nl1ll0iOi AND NOT(niOi1O10i); + wire_nl1llOill_dataout <= nl1ll0iOl OR niOi1O10i; + wire_nl1llOilO_dataout <= nl1ll0iOO AND NOT(niOi1O10i); + wire_nl1llOiOi_dataout <= niOi0110O WHEN niOi1O10i = '1' ELSE nl1ll0lOl; + wire_nl1llOl_dataout <= n1Oil1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1llOli_dataout <= nl1llOOi AND NOT(wire_niO01O0O_dataout); + wire_nl1llOlO_dataout <= nl1llO1l AND NOT(wire_niO01O0O_dataout); + wire_nl1llOlOi_dataout <= wire_nl1lO11ii_o(1) WHEN niOi1O1lO = '1' ELSE wire_nl1llOOiO_dataout; + wire_nl1llOlOl_dataout <= wire_nl1lO11ii_o(2) WHEN niOi1O1lO = '1' ELSE wire_nl1llOOli_dataout; + wire_nl1llOlOO_dataout <= wire_nl1lO11ii_o(3) WHEN niOi1O1lO = '1' ELSE wire_nl1llOOll_dataout; + wire_nl1llOO_dataout <= n1Oil1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1llOO0i_dataout <= wire_nl1lO11ii_o(7) WHEN niOi1O1lO = '1' ELSE wire_nl1llOOOO_dataout; + wire_nl1llOO0l_dataout <= wire_nl1lO11ii_o(8) WHEN niOi1O1lO = '1' ELSE wire_nl1lO111i_dataout; + wire_nl1llOO0O_dataout <= wire_nl1lO11ii_o(9) WHEN niOi1O1lO = '1' ELSE wire_nl1lO111l_dataout; + wire_nl1llOO1i_dataout <= wire_nl1lO11ii_o(4) WHEN niOi1O1lO = '1' ELSE wire_nl1llOOlO_dataout; + wire_nl1llOO1l_dataout <= wire_nl1lO11ii_o(5) WHEN niOi1O1lO = '1' ELSE wire_nl1llOOOi_dataout; + wire_nl1llOO1O_dataout <= wire_nl1lO11ii_o(6) WHEN niOi1O1lO = '1' ELSE wire_nl1llOOOl_dataout; + wire_nl1llOOii_dataout <= wire_nl1lO11ii_o(10) WHEN niOi1O1lO = '1' ELSE wire_nl1lO111O_dataout; + wire_nl1llOOil_dataout <= wire_nl1lO11ii_o(11) WHEN niOi1O1lO = '1' ELSE wire_nl1lO110i_dataout; + wire_nl1llOOiO_dataout <= wire_nl1lO110l_o(0) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOi0l_dataout; + wire_nl1llOOl_dataout <= nl1lO11i AND NOT(wire_niO01l0O_dataout); + wire_nl1llOOli_dataout <= wire_nl1lO110l_o(1) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOi0O_dataout; + wire_nl1llOOll_dataout <= wire_nl1lO110l_o(2) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOiii_dataout; + wire_nl1llOOlO_dataout <= wire_nl1lO110l_o(3) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOiil_dataout; + wire_nl1llOOOi_dataout <= wire_nl1lO110l_o(4) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOiiO_dataout; + wire_nl1llOOOl_dataout <= wire_nl1lO110l_o(5) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOili_dataout; + wire_nl1llOOOO_dataout <= wire_nl1lO110l_o(6) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOill_dataout; + wire_nl1lO000i_dataout <= nl1O1OlOi WHEN niOi1O00i = '1' ELSE wire_nl1lOi1il_dataout; + wire_nl1lO000l_dataout <= nl1O1OlOl WHEN niOi1O00i = '1' ELSE wire_nl1lOi1iO_dataout; + wire_nl1lO000O_dataout <= nl1O1OlOO WHEN niOi1O00i = '1' ELSE wire_nl1lOi1li_dataout; + wire_nl1lO001i_dataout <= nl1O1Olli WHEN niOi1O00i = '1' ELSE wire_nl1lOi10l_dataout; + wire_nl1lO001l_dataout <= nl1O1Olll WHEN niOi1O00i = '1' ELSE wire_nl1lOi10O_dataout; + wire_nl1lO001O_dataout <= nl1O1OllO WHEN niOi1O00i = '1' ELSE wire_nl1lOi1ii_dataout; + wire_nl1lO00ii_dataout <= nl1O1OO1i WHEN niOi1O00i = '1' ELSE wire_nl1lOi1ll_dataout; + wire_nl1lO00il_dataout <= nl1O1OO1l WHEN niOi1O00i = '1' ELSE wire_nl1lOi1lO_dataout; + wire_nl1lO00iO_dataout <= nl1O1OO1O WHEN niOi1O00i = '1' ELSE wire_nl1lOi1Oi_dataout; + wire_nl1lO00li_dataout <= nl1O1OO0i WHEN niOi1O00i = '1' ELSE wire_nl1lOi1Ol_dataout; + wire_nl1lO00ll_dataout <= nl1O1OO0l WHEN niOi1O00i = '1' ELSE wire_nl1lOi1OO_dataout; + wire_nl1lO00lO_dataout <= nl1O1OO0O WHEN niOi1O00i = '1' ELSE wire_nl1lOi01i_dataout; + wire_nl1lO00Oi_dataout <= nl1O1OOii WHEN niOi1O00i = '1' ELSE wire_nl1lOi01l_dataout; + wire_nl1lO00Ol_dataout <= nl1O1OOil WHEN niOi1O00i = '1' ELSE wire_nl1lOi01O_dataout; + wire_nl1lO00OO_dataout <= nl1O1OOiO WHEN niOi1O00i = '1' ELSE wire_nl1lOi00i_dataout; + wire_nl1lO010i_dataout <= nl1O1OiOi WHEN niOi1O00i = '1' ELSE wire_nl1lO0Oil_dataout; + wire_nl1lO010l_dataout <= nl1O1OiOl WHEN niOi1O00i = '1' ELSE wire_nl1lO0OiO_dataout; + wire_nl1lO010O_dataout <= nl1O1OiOO WHEN niOi1O00i = '1' ELSE wire_nl1lO0Oli_dataout; + wire_nl1lO011i_dataout <= nl1O1Oili WHEN niOi1O00i = '1' ELSE wire_nl1lO0O0l_dataout; + wire_nl1lO011l_dataout <= nl1O1Oill WHEN niOi1O00i = '1' ELSE wire_nl1lO0O0O_dataout; + wire_nl1lO011O_dataout <= nl1O1OilO WHEN niOi1O00i = '1' ELSE wire_nl1lO0Oii_dataout; + wire_nl1lO01ii_dataout <= nl1O1Ol1i WHEN niOi1O00i = '1' ELSE wire_nl1lO0Oll_dataout; + wire_nl1lO01il_dataout <= nl1O1Ol1l WHEN niOi1O00i = '1' ELSE wire_nl1lO0OlO_dataout; + wire_nl1lO01iO_dataout <= nl1O1Ol1O WHEN niOi1O00i = '1' ELSE wire_nl1lO0OOi_dataout; + wire_nl1lO01li_dataout <= nl1O1Ol0i WHEN niOi1O00i = '1' ELSE wire_nl1lO0OOl_dataout; + wire_nl1lO01ll_dataout <= nl1O1Ol0l WHEN niOi1O00i = '1' ELSE wire_nl1lO0OOO_dataout; + wire_nl1lO01lO_dataout <= nl1O1Ol0O WHEN niOi1O00i = '1' ELSE wire_nl1lOi11i_dataout; + wire_nl1lO01Oi_dataout <= nl1O1Olii WHEN niOi1O00i = '1' ELSE wire_nl1lOi11l_dataout; + wire_nl1lO01Ol_dataout <= nl1O1Olil WHEN niOi1O00i = '1' ELSE wire_nl1lOi11O_dataout; + wire_nl1lO01OO_dataout <= nl1O1OliO WHEN niOi1O00i = '1' ELSE wire_nl1lOi10i_dataout; + wire_nl1lO0i_dataout <= n1Oil0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lO0i0i_dataout <= nl1O1OOOi WHEN niOi1O00i = '1' ELSE wire_nl1lOi0il_dataout; + wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w56945w56951w(0) <= wire_nl1lO0i0i_w_lg_w_lg_dataout55287w56945w(0) AND wire_nl1lO0i1l_dataout; + wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w55288w55289w(0) <= wire_nl1lO0i0i_w_lg_w_lg_dataout55287w55288w(0) AND wire_nl1lO0i1l_dataout; + wire_nl1lO0i0i_w_lg_w_lg_dataout55287w56945w(0) <= wire_nl1lO0i0i_w_lg_dataout55287w(0) AND wire_nl1lO0i1O_w_lg_dataout56944w(0); + wire_nl1lO0i0i_w_lg_w_lg_dataout55287w55288w(0) <= wire_nl1lO0i0i_w_lg_dataout55287w(0) AND wire_nl1lO0i1O_dataout; + wire_nl1lO0i0i_w_lg_dataout55287w(0) <= NOT wire_nl1lO0i0i_dataout; + wire_nl1lO0i0l_dataout <= nl1O1OOOl WHEN niOi1O00i = '1' ELSE wire_nl1lOi0iO_dataout; + wire_nl1lO0i0O_dataout <= nl1O1l0ii WHEN niOi1O00l = '1' ELSE wire_nl1lOi0li_dataout; + wire_nl1lO0i1i_dataout <= nl1O1OOli WHEN niOi1O00i = '1' ELSE wire_nl1lOi00l_dataout; + wire_nl1lO0i1i_w_lg_dataout56948w(0) <= NOT wire_nl1lO0i1i_dataout; + wire_nl1lO0i1l_dataout <= nl1O1OOll WHEN niOi1O00i = '1' ELSE wire_nl1lOi00O_dataout; + wire_nl1lO0i1l_w_lg_dataout56946w(0) <= NOT wire_nl1lO0i1l_dataout; + wire_nl1lO0i1O_dataout <= nl1O1OOlO WHEN niOi1O00i = '1' ELSE wire_nl1lOi0ii_dataout; + wire_nl1lO0i1O_w_lg_dataout56944w(0) <= NOT wire_nl1lO0i1O_dataout; + wire_nl1lO0iii_dataout <= nl1O1l0il WHEN niOi1O00l = '1' ELSE wire_nl1lOi0ll_dataout; + wire_nl1lO0iil_dataout <= nl1O1l0iO WHEN niOi1O00l = '1' ELSE wire_nl1lOi0lO_dataout; + wire_nl1lO0iiO_dataout <= nl1O1l0li WHEN niOi1O00l = '1' ELSE wire_nl1lOi0Oi_dataout; + wire_nl1lO0ili_dataout <= nl1O1l0ll WHEN niOi1O00l = '1' ELSE wire_nl1lOi0Ol_dataout; + wire_nl1lO0ill_dataout <= nl1O1l0lO WHEN niOi1O00l = '1' ELSE wire_nl1lOi0OO_dataout; + wire_nl1lO0ilO_dataout <= nl1O1l0Oi WHEN niOi1O00l = '1' ELSE wire_nl1lOii1i_dataout; + wire_nl1lO0iO_dataout <= wire_nl1lO0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lO0iOi_dataout <= nl1O1l0Ol WHEN niOi1O00l = '1' ELSE wire_nl1lOii1l_dataout; + wire_nl1lO0iOl_dataout <= nl1O1l0OO WHEN niOi1O00l = '1' ELSE wire_nl1lOii1O_dataout; + wire_nl1lO0iOO_dataout <= nl1O1li1i WHEN niOi1O00l = '1' ELSE wire_nl1lOii0i_dataout; + wire_nl1lO0l_dataout <= n1Oilii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lO0l0i_dataout <= nl1O1li0l WHEN niOi1O00l = '1' ELSE wire_nl1lOiiil_dataout; + wire_nl1lO0l0l_dataout <= nl1O1li0O WHEN niOi1O00l = '1' ELSE wire_nl1lOiiiO_dataout; + wire_nl1lO0l0O_dataout <= nl1O1liii WHEN niOi1O00l = '1' ELSE wire_nl1lOiili_dataout; + wire_nl1lO0l1i_dataout <= nl1O1li1l WHEN niOi1O00l = '1' ELSE wire_nl1lOii0l_dataout; + wire_nl1lO0l1l_dataout <= nl1O1li1O WHEN niOi1O00l = '1' ELSE wire_nl1lOii0O_dataout; + wire_nl1lO0l1O_dataout <= nl1O1li0i WHEN niOi1O00l = '1' ELSE wire_nl1lOiiii_dataout; + wire_nl1lO0li_dataout <= wire_nl1lO0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lO0lii_dataout <= nl1O1liil WHEN niOi1O00l = '1' ELSE wire_nl1lOiill_dataout; + wire_nl1lO0lil_dataout <= nl1O1liiO WHEN niOi1O00l = '1' ELSE wire_nl1lOiilO_dataout; + wire_nl1lO0liO_dataout <= nl1O1lili WHEN niOi1O00l = '1' ELSE wire_nl1lOiiOi_dataout; + wire_nl1lO0ll_dataout <= wire_nl1lO0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lO0lli_dataout <= nl1O1lill WHEN niOi1O00l = '1' ELSE wire_nl1lOiiOl_dataout; + wire_nl1lO0lll_dataout <= nl1O1lilO WHEN niOi1O00l = '1' ELSE wire_nl1lOiiOO_dataout; + wire_nl1lO0llO_dataout <= nl1O1liOi WHEN niOi1O00l = '1' ELSE wire_nl1lOil1i_dataout; + wire_nl1lO0lO_dataout <= wire_nl1lOi1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1lO0lOi_dataout <= nl1O1liOl WHEN niOi1O00l = '1' ELSE wire_nl1lOil1l_dataout; + wire_nl1lO0lOl_dataout <= nl1O1liOO WHEN niOi1O00l = '1' ELSE wire_nl1lOil1O_dataout; + wire_nl1lO0lOO_dataout <= nl1O1ll1i WHEN niOi1O00l = '1' ELSE wire_nl1lOil0i_dataout; + wire_nl1lO0O_dataout <= n1Oilil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lO0O0i_dataout <= nl1O1ll0l WHEN niOi1O00l = '1' ELSE wire_nl1lOilil_dataout; + wire_nl1lO0O0l_dataout <= nl1O1ll0O WHEN niOi1O00l = '1' ELSE wire_nl1lOiliO_dataout; + wire_nl1lO0O0O_dataout <= nl1O1llii WHEN niOi1O00l = '1' ELSE wire_nl1lOilli_dataout; + wire_nl1lO0O1i_dataout <= nl1O1ll1l WHEN niOi1O00l = '1' ELSE wire_nl1lOil0l_dataout; + wire_nl1lO0O1l_dataout <= nl1O1ll1O WHEN niOi1O00l = '1' ELSE wire_nl1lOil0O_dataout; + wire_nl1lO0O1O_dataout <= nl1O1ll0i WHEN niOi1O00l = '1' ELSE wire_nl1lOilii_dataout; + wire_nl1lO0Oi_dataout <= nl1lOiOl WHEN niOO1lili = '1' ELSE nl1lOi1O; + wire_nl1lO0Oii_dataout <= nl1O1llil WHEN niOi1O00l = '1' ELSE wire_nl1lOilll_dataout; + wire_nl1lO0Oil_dataout <= nl1O1lliO WHEN niOi1O00l = '1' ELSE wire_nl1lOillO_dataout; + wire_nl1lO0OiO_dataout <= nl1O1llli WHEN niOi1O00l = '1' ELSE wire_nl1lOilOi_dataout; + wire_nl1lO0Ol_dataout <= nl1lOiOO WHEN niOO1lili = '1' ELSE nl1lO00l; + wire_nl1lO0Oli_dataout <= nl1O1llll WHEN niOi1O00l = '1' ELSE wire_nl1lOilOl_dataout; + wire_nl1lO0Oll_dataout <= nl1O1lllO WHEN niOi1O00l = '1' ELSE wire_nl1lOilOO_dataout; + wire_nl1lO0OlO_dataout <= nl1O1llOi WHEN niOi1O00l = '1' ELSE wire_nl1lOiO1i_dataout; + wire_nl1lO0OO_dataout <= nl1lOl1i WHEN niOO1lili = '1' ELSE nl1lO00O; + wire_nl1lO0OOi_dataout <= nl1O1llOl WHEN niOi1O00l = '1' ELSE wire_nl1lOiO1l_dataout; + wire_nl1lO0OOl_dataout <= nl1O1llOO WHEN niOi1O00l = '1' ELSE wire_nl1lOiO1O_dataout; + wire_nl1lO0OOO_dataout <= nl1O1lO1i WHEN niOi1O00l = '1' ELSE wire_nl1lOiO0i_dataout; + wire_nl1lO100i_dataout <= wire_nl1lO10iO_dataout AND NOT(niOi1O1Oi); + wire_nl1lO100l_dataout <= wire_nl1lO10li_dataout AND NOT(niOi1O1Oi); + wire_nl1lO100O_dataout <= wire_nl1lO10ll_dataout AND NOT(niOi1O1Oi); + wire_nl1lO101i_dataout <= wire_nl1lO10ii_dataout AND NOT(niOO01l0i); + wire_nl1lO101l_dataout <= niOi1O1Ol AND NOT(niOi1O1Oi); + wire_nl1lO101O_dataout <= wire_nl1lO10il_dataout AND NOT(niOi1O1Oi); + wire_nl1lO10ii_dataout <= wire_nl1lO10lO_dataout AND NOT(niOi1O1Oi); + wire_nl1lO10il_dataout <= niOi1O1OO AND NOT(niOi1O1Ol); + wire_nl1lO10iO_dataout <= wire_nl1lO10Oi_dataout AND NOT(niOi1O1Ol); + wire_nl1lO10li_dataout <= wire_nl1lO10Ol_dataout AND NOT(niOi1O1Ol); + wire_nl1lO10ll_dataout <= wire_nl1lO10OO_dataout AND NOT(niOi1O1Ol); + wire_nl1lO10lO_dataout <= wire_nl1lO1i1i_dataout AND NOT(niOi1O1Ol); + wire_nl1lO10O_dataout <= wire_nl1lO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lO10Oi_dataout <= niOi1O01i AND NOT(niOi1O1OO); + wire_nl1lO10Ol_dataout <= wire_nl1lO1i1l_dataout AND NOT(niOi1O1OO); + wire_nl1lO10OO_dataout <= wire_nl1lO1i1O_dataout AND NOT(niOi1O1OO); + wire_nl1lO110i_dataout <= wire_nl1lO110l_o(10) WHEN niOi1O1iO = '1' ELSE niOi1O1ll; + wire_nl1lO111i_dataout <= wire_nl1lO110l_o(7) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOilO_dataout; + wire_nl1lO111l_dataout <= wire_nl1lO110l_o(8) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOiOi_dataout; + wire_nl1lO111O_dataout <= wire_nl1lO110l_o(9) WHEN niOi1O1iO = '1' ELSE wire_nl1lOOiOl_dataout; + wire_nl1lO11l_dataout <= nl1llOOO AND NOT(wire_niO01l0O_dataout); + wire_nl1lO11li_dataout <= niOi1O1Oi AND NOT(niOO01l0i); + wire_nl1lO11ll_dataout <= wire_nl1lO101l_dataout AND NOT(niOO01l0i); + wire_nl1lO11lO_dataout <= wire_nl1lO101O_dataout AND NOT(niOO01l0i); + wire_nl1lO11O_dataout <= nl1llOll AND NOT(wire_niO01l0O_dataout); + wire_nl1lO11Oi_dataout <= wire_nl1lO100i_dataout AND NOT(niOO01l0i); + wire_nl1lO11Ol_dataout <= wire_nl1lO100l_dataout AND NOT(niOO01l0i); + wire_nl1lO11OO_dataout <= wire_nl1lO100O_dataout AND NOT(niOO01l0i); + wire_nl1lO1i_dataout <= n1Oil1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lO1i0i_dataout <= wire_nl1lO1i0O_dataout AND NOT(niOi1O01i); + wire_nl1lO1i0l_dataout <= niOi1O01O AND NOT(niOi1O01l); + wire_nl1lO1i0O_dataout <= wire_nl1lO1iii_dataout AND NOT(niOi1O01l); + wire_nl1lO1i1i_dataout <= wire_nl1lO1i0i_dataout AND NOT(niOi1O1OO); + wire_nl1lO1i1l_dataout <= niOi1O01l AND NOT(niOi1O01i); + wire_nl1lO1i1O_dataout <= wire_nl1lO1i0l_dataout AND NOT(niOi1O01i); + wire_nl1lO1ii_dataout <= wire_nl1lO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lO1iii_dataout <= (wire_nl1lO0i0i_w_lg_w_lg_w_lg_dataout55287w55288w55289w(0) AND wire_nl1lO0i1i_dataout) AND NOT(niOi1O01O); + wire_nl1lO1il_dataout <= wire_nl1lO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lO1ili_dataout <= wire_nl1lO1ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lO1ill_dataout <= nl00lllii WHEN (wire_nilO010O_w_lg_dataout8973w(0) AND wire_nilO010i_w_lg_dataout25163w(0)) = '1' ELSE nl1ll0lOO; + wire_nl1lO1iO_dataout <= wire_nl1000i_w_lg_nl1lO11i7822w(0) WHEN (wire_w_lg_niOO1liiO7821w(0) AND (NOT ((NOT (nl1llllO XOR nl1lO10i)) AND (NOT (nl1llilO XOR nl1lO10l))))) = '1' ELSE nl1lO11i; + wire_nl1lO1iOi_dataout <= wire_nl1lO1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lO1iOl_dataout <= wire_nl1OlOi1l_dataout WHEN (niOi1Ol1O AND (niOi01i0O AND wire_w_lg_niOi1Ol1i54886w(0))) = '1' ELSE nl1lO1iiO; + wire_nl1lO1l_dataout <= n1Oil0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lO1l0i_dataout <= nl1O1O1Oi WHEN niOi1O00i = '1' ELSE wire_nl1lO0iil_dataout; + wire_nl1lO1l0l_dataout <= nl1O1O1Ol WHEN niOi1O00i = '1' ELSE wire_nl1lO0iiO_dataout; + wire_nl1lO1l0O_dataout <= nl1O1O1OO WHEN niOi1O00i = '1' ELSE wire_nl1lO0ili_dataout; + wire_nl1lO1l1l_dataout <= nl1O1O1ll WHEN niOi1O00i = '1' ELSE wire_nl1lO0i0O_dataout; + wire_nl1lO1l1O_dataout <= nl1O1O1lO WHEN niOi1O00i = '1' ELSE wire_nl1lO0iii_dataout; + wire_nl1lO1lii_dataout <= nl1O1O01i WHEN niOi1O00i = '1' ELSE wire_nl1lO0ill_dataout; + wire_nl1lO1lil_dataout <= nl1O1O01l WHEN niOi1O00i = '1' ELSE wire_nl1lO0ilO_dataout; + wire_nl1lO1liO_dataout <= nl1O1O01O WHEN niOi1O00i = '1' ELSE wire_nl1lO0iOi_dataout; + wire_nl1lO1ll_dataout <= nl1llllO WHEN wire_w_lg_niOO1liiO7821w(0) = '1' ELSE nl1lO10i; + wire_nl1lO1lli_dataout <= nl1O1O00i WHEN niOi1O00i = '1' ELSE wire_nl1lO0iOl_dataout; + wire_nl1lO1lll_dataout <= nl1O1O00l WHEN niOi1O00i = '1' ELSE wire_nl1lO0iOO_dataout; + wire_nl1lO1llO_dataout <= nl1O1O00O WHEN niOi1O00i = '1' ELSE wire_nl1lO0l1i_dataout; + wire_nl1lO1lO_dataout <= nl1llilO WHEN wire_w_lg_niOO1liiO7821w(0) = '1' ELSE nl1lO10l; + wire_nl1lO1lOi_dataout <= nl1O1O0ii WHEN niOi1O00i = '1' ELSE wire_nl1lO0l1l_dataout; + wire_nl1lO1lOl_dataout <= nl1O1O0il WHEN niOi1O00i = '1' ELSE wire_nl1lO0l1O_dataout; + wire_nl1lO1lOO_dataout <= nl1O1O0iO WHEN niOi1O00i = '1' ELSE wire_nl1lO0l0i_dataout; + wire_nl1lO1O_dataout <= n1Oil0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lO1O0i_dataout <= nl1O1O0Oi WHEN niOi1O00i = '1' ELSE wire_nl1lO0lil_dataout; + wire_nl1lO1O0l_dataout <= nl1O1O0Ol WHEN niOi1O00i = '1' ELSE wire_nl1lO0liO_dataout; + wire_nl1lO1O0O_dataout <= nl1O1O0OO WHEN niOi1O00i = '1' ELSE wire_nl1lO0lli_dataout; + wire_nl1lO1O1i_dataout <= nl1O1O0li WHEN niOi1O00i = '1' ELSE wire_nl1lO0l0l_dataout; + wire_nl1lO1O1l_dataout <= nl1O1O0ll WHEN niOi1O00i = '1' ELSE wire_nl1lO0l0O_dataout; + wire_nl1lO1O1O_dataout <= nl1O1O0lO WHEN niOi1O00i = '1' ELSE wire_nl1lO0lii_dataout; + wire_nl1lO1Oii_dataout <= nl1O1Oi1i WHEN niOi1O00i = '1' ELSE wire_nl1lO0lll_dataout; + wire_nl1lO1Oil_dataout <= nl1O1Oi1l WHEN niOi1O00i = '1' ELSE wire_nl1lO0llO_dataout; + wire_nl1lO1OiO_dataout <= nl1O1Oi1O WHEN niOi1O00i = '1' ELSE wire_nl1lO0lOi_dataout; + wire_nl1lO1Oli_dataout <= nl1O1Oi0i WHEN niOi1O00i = '1' ELSE wire_nl1lO0lOl_dataout; + wire_nl1lO1Oll_dataout <= nl1O1Oi0l WHEN niOi1O00i = '1' ELSE wire_nl1lO0lOO_dataout; + wire_nl1lO1OlO_dataout <= nl1O1Oi0O WHEN niOi1O00i = '1' ELSE wire_nl1lO0O1i_dataout; + wire_nl1lO1OOi_dataout <= nl1O1Oiii WHEN niOi1O00i = '1' ELSE wire_nl1lO0O1l_dataout; + wire_nl1lO1OOl_dataout <= nl1O1Oiil WHEN niOi1O00i = '1' ELSE wire_nl1lO0O1O_dataout; + wire_nl1lO1OOO_dataout <= nl1O1OiiO WHEN niOi1O00i = '1' ELSE wire_nl1lO0O0i_dataout; + wire_nl1lOi00i_dataout <= nl1O1O10l WHEN niOi1O00l = '1' ELSE wire_nl1lOl1il_dataout; + wire_nl1lOi00l_dataout <= nl1O1O10O WHEN niOi1O00l = '1' ELSE wire_nl1lOl1iO_dataout; + wire_nl1lOi00O_dataout <= nl1O1O1ii WHEN niOi1O00l = '1' ELSE wire_nl1lOl1li_dataout; + wire_nl1lOi01i_dataout <= nl1O1O11l WHEN niOi1O00l = '1' ELSE wire_nl1lOl10l_dataout; + wire_nl1lOi01l_dataout <= nl1O1O11O WHEN niOi1O00l = '1' ELSE wire_nl1lOl10O_dataout; + wire_nl1lOi01O_dataout <= nl1O1O10i WHEN niOi1O00l = '1' ELSE wire_nl1lOl1ii_dataout; + wire_nl1lOi0ii_dataout <= nl1O1O1il WHEN niOi1O00l = '1' ELSE wire_nl1lOl1ll_dataout; + wire_nl1lOi0il_dataout <= nl1O1O1iO WHEN niOi1O00l = '1' ELSE wire_nl1lOl1lO_dataout; + wire_nl1lOi0iO_dataout <= nl1O1O1li WHEN niOi1O00l = '1' ELSE wire_nl1lOl1Oi_dataout; + wire_nl1lOi0l_dataout <= nl1lOiil AND NOT(wire_niO01O0O_dataout); + wire_nl1lOi0li_dataout <= nl1O1ii1O WHEN niOi1O00O = '1' ELSE wire_nl1lOl1Ol_dataout; + wire_nl1lOi0ll_dataout <= nl1O1ii0i WHEN niOi1O00O = '1' ELSE wire_nl1lOl1OO_dataout; + wire_nl1lOi0lO_dataout <= nl1O1ii0l WHEN niOi1O00O = '1' ELSE wire_nl1lOl01i_dataout; + wire_nl1lOi0Oi_dataout <= nl1O1ii0O WHEN niOi1O00O = '1' ELSE wire_nl1lOl01l_dataout; + wire_nl1lOi0Ol_dataout <= nl1O1iiii WHEN niOi1O00O = '1' ELSE wire_nl1lOl01O_dataout; + wire_nl1lOi0OO_dataout <= nl1O1iiil WHEN niOi1O00O = '1' ELSE wire_nl1lOl00i_dataout; + wire_nl1lOi10i_dataout <= nl1O1lO0l WHEN niOi1O00l = '1' ELSE wire_nl1lOiOil_dataout; + wire_nl1lOi10l_dataout <= nl1O1lO0O WHEN niOi1O00l = '1' ELSE wire_nl1lOiOiO_dataout; + wire_nl1lOi10O_dataout <= nl1O1lOii WHEN niOi1O00l = '1' ELSE wire_nl1lOiOli_dataout; + wire_nl1lOi11i_dataout <= nl1O1lO1l WHEN niOi1O00l = '1' ELSE wire_nl1lOiO0l_dataout; + wire_nl1lOi11l_dataout <= nl1O1lO1O WHEN niOi1O00l = '1' ELSE wire_nl1lOiO0O_dataout; + wire_nl1lOi11O_dataout <= nl1O1lO0i WHEN niOi1O00l = '1' ELSE wire_nl1lOiOii_dataout; + wire_nl1lOi1i_dataout <= nl1lOl1l WHEN niOO1lili = '1' ELSE nl1lO0ii; + wire_nl1lOi1ii_dataout <= nl1O1lOil WHEN niOi1O00l = '1' ELSE wire_nl1lOiOll_dataout; + wire_nl1lOi1il_dataout <= nl1O1lOiO WHEN niOi1O00l = '1' ELSE wire_nl1lOiOlO_dataout; + wire_nl1lOi1iO_dataout <= nl1O1lOli WHEN niOi1O00l = '1' ELSE wire_nl1lOiOOi_dataout; + wire_nl1lOi1li_dataout <= nl1O1lOll WHEN niOi1O00l = '1' ELSE wire_nl1lOiOOl_dataout; + wire_nl1lOi1ll_dataout <= nl1O1lOlO WHEN niOi1O00l = '1' ELSE wire_nl1lOiOOO_dataout; + wire_nl1lOi1lO_dataout <= nl1O1lOOi WHEN niOi1O00l = '1' ELSE wire_nl1lOl11i_dataout; + wire_nl1lOi1Oi_dataout <= nl1O1lOOl WHEN niOi1O00l = '1' ELSE wire_nl1lOl11l_dataout; + wire_nl1lOi1Ol_dataout <= nl1O1lOOO WHEN niOi1O00l = '1' ELSE wire_nl1lOl11O_dataout; + wire_nl1lOi1OO_dataout <= nl1O1O11i WHEN niOi1O00l = '1' ELSE wire_nl1lOl10i_dataout; + wire_nl1lOii_dataout <= n1OiliO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOii0i_dataout <= nl1O1iilO WHEN niOi1O00O = '1' ELSE wire_nl1lOl0il_dataout; + wire_nl1lOii0l_dataout <= nl1O1iiOi WHEN niOi1O00O = '1' ELSE wire_nl1lOl0iO_dataout; + wire_nl1lOii0O_dataout <= nl1O1iiOl WHEN niOi1O00O = '1' ELSE wire_nl1lOl0li_dataout; + wire_nl1lOii1i_dataout <= nl1O1iiiO WHEN niOi1O00O = '1' ELSE wire_nl1lOl00l_dataout; + wire_nl1lOii1l_dataout <= nl1O1iili WHEN niOi1O00O = '1' ELSE wire_nl1lOl00O_dataout; + wire_nl1lOii1O_dataout <= nl1O1iill WHEN niOi1O00O = '1' ELSE wire_nl1lOl0ii_dataout; + wire_nl1lOiii_dataout <= nl1lO0il AND NOT(wire_niO01O0O_dataout); + wire_nl1lOiiii_dataout <= nl1O1iiOO WHEN niOi1O00O = '1' ELSE wire_nl1lOl0ll_dataout; + wire_nl1lOiiil_dataout <= nl1O1il1i WHEN niOi1O00O = '1' ELSE wire_nl1lOl0lO_dataout; + wire_nl1lOiiiO_dataout <= nl1O1il1l WHEN niOi1O00O = '1' ELSE wire_nl1lOl0Oi_dataout; + wire_nl1lOiili_dataout <= nl1O1il1O WHEN niOi1O00O = '1' ELSE wire_nl1lOl0Ol_dataout; + wire_nl1lOiill_dataout <= nl1O1il0i WHEN niOi1O00O = '1' ELSE wire_nl1lOl0OO_dataout; + wire_nl1lOiilO_dataout <= nl1O1il0l WHEN niOi1O00O = '1' ELSE wire_nl1lOli1i_dataout; + wire_nl1lOiiO_dataout <= nl1lOill AND NOT(wire_niO01l0O_dataout); + wire_nl1lOiiOi_dataout <= nl1O1il0O WHEN niOi1O00O = '1' ELSE wire_nl1lOli1l_dataout; + wire_nl1lOiiOl_dataout <= nl1O1ilii WHEN niOi1O00O = '1' ELSE wire_nl1lOli1O_dataout; + wire_nl1lOiiOO_dataout <= nl1O1ilil WHEN niOi1O00O = '1' ELSE wire_nl1lOli0i_dataout; + wire_nl1lOil_dataout <= n1Oilli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOil0i_dataout <= nl1O1illO WHEN niOi1O00O = '1' ELSE wire_nl1lOliil_dataout; + wire_nl1lOil0l_dataout <= nl1O1ilOi WHEN niOi1O00O = '1' ELSE wire_nl1lOliiO_dataout; + wire_nl1lOil0O_dataout <= nl1O1ilOl WHEN niOi1O00O = '1' ELSE wire_nl1lOlili_dataout; + wire_nl1lOil1i_dataout <= nl1O1iliO WHEN niOi1O00O = '1' ELSE wire_nl1lOli0l_dataout; + wire_nl1lOil1l_dataout <= nl1O1illi WHEN niOi1O00O = '1' ELSE wire_nl1lOli0O_dataout; + wire_nl1lOil1O_dataout <= nl1O1illl WHEN niOi1O00O = '1' ELSE wire_nl1lOliii_dataout; + wire_nl1lOilii_dataout <= nl1O1ilOO WHEN niOi1O00O = '1' ELSE wire_nl1lOlill_dataout; + wire_nl1lOilil_dataout <= nl1O1iO1i WHEN niOi1O00O = '1' ELSE wire_nl1lOlilO_dataout; + wire_nl1lOiliO_dataout <= nl1O1iO1l WHEN niOi1O00O = '1' ELSE wire_nl1lOliOi_dataout; + wire_nl1lOilli_dataout <= nl1O1iO1O WHEN niOi1O00O = '1' ELSE wire_nl1lOliOl_dataout; + wire_nl1lOilll_dataout <= nl1O1iO0i WHEN niOi1O00O = '1' ELSE wire_nl1lOliOO_dataout; + wire_nl1lOillO_dataout <= nl1O1iO0l WHEN niOi1O00O = '1' ELSE wire_nl1lOll1i_dataout; + wire_nl1lOilO_dataout <= nl1lOili AND NOT(wire_niO01l0O_dataout); + wire_nl1lOilOi_dataout <= nl1O1iO0O WHEN niOi1O00O = '1' ELSE wire_nl1lOll1l_dataout; + wire_nl1lOilOl_dataout <= nl1O1iOii WHEN niOi1O00O = '1' ELSE wire_nl1lOll1O_dataout; + wire_nl1lOilOO_dataout <= nl1O1iOil WHEN niOi1O00O = '1' ELSE wire_nl1lOll0i_dataout; + wire_nl1lOiO_dataout <= n1Oilll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOiO0i_dataout <= nl1O1iOlO WHEN niOi1O00O = '1' ELSE wire_nl1lOllil_dataout; + wire_nl1lOiO0l_dataout <= nl1O1iOOi WHEN niOi1O00O = '1' ELSE wire_nl1lOlliO_dataout; + wire_nl1lOiO0O_dataout <= nl1O1iOOl WHEN niOi1O00O = '1' ELSE wire_nl1lOllli_dataout; + wire_nl1lOiO1i_dataout <= nl1O1iOiO WHEN niOi1O00O = '1' ELSE wire_nl1lOll0l_dataout; + wire_nl1lOiO1l_dataout <= nl1O1iOli WHEN niOi1O00O = '1' ELSE wire_nl1lOll0O_dataout; + wire_nl1lOiO1O_dataout <= nl1O1iOll WHEN niOi1O00O = '1' ELSE wire_nl1lOllii_dataout; + wire_nl1lOiOi_dataout <= nl1lOi0O AND NOT(wire_niO01l0O_dataout); + wire_nl1lOiOii_dataout <= nl1O1iOOO WHEN niOi1O00O = '1' ELSE wire_nl1lOllll_dataout; + wire_nl1lOiOil_dataout <= nl1O1l11i WHEN niOi1O00O = '1' ELSE wire_nl1lOlllO_dataout; + wire_nl1lOiOiO_dataout <= nl1O1l11l WHEN niOi1O00O = '1' ELSE wire_nl1lOllOi_dataout; + wire_nl1lOiOli_dataout <= nl1O1l11O WHEN niOi1O00O = '1' ELSE wire_nl1lOllOl_dataout; + wire_nl1lOiOll_dataout <= nl1O1l10i WHEN niOi1O00O = '1' ELSE wire_nl1lOllOO_dataout; + wire_nl1lOiOlO_dataout <= nl1O1l10l WHEN niOi1O00O = '1' ELSE wire_nl1lOlO1i_dataout; + wire_nl1lOiOOi_dataout <= nl1O1l10O WHEN niOi1O00O = '1' ELSE wire_nl1lOlO1l_dataout; + wire_nl1lOiOOl_dataout <= nl1O1l1ii WHEN niOi1O00O = '1' ELSE wire_nl1lOlO1O_dataout; + wire_nl1lOiOOO_dataout <= nl1O1l1il WHEN niOi1O00O = '1' ELSE wire_nl1lOlO0i_dataout; + wire_nl1lOl00i_dataout <= nl1O01O0l AND niOi1O0Ol; + wire_nl1lOl00l_dataout <= nl1O01O0O AND niOi1O0Ol; + wire_nl1lOl00O_dataout <= nl1O01Oii AND niOi1O0Ol; + wire_nl1lOl01i_dataout <= nl1O01O1l AND niOi1O0Ol; + wire_nl1lOl01l_dataout <= nl1O01O1O AND niOi1O0Ol; + wire_nl1lOl01O_dataout <= nl1O01O0i AND niOi1O0Ol; + wire_nl1lOl0i_dataout <= wire_nl1lOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOl0ii_dataout <= nl1O01Oil AND niOi1O0Ol; + wire_nl1lOl0il_dataout <= nl1O01OiO AND niOi1O0Ol; + wire_nl1lOl0iO_dataout <= nl1O01Oli AND niOi1O0Ol; + wire_nl1lOl0l_dataout <= wire_nl1lOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOl0li_dataout <= nl1O01Oll AND niOi1O0Ol; + wire_nl1lOl0ll_dataout <= nl1O01OlO AND niOi1O0Ol; + wire_nl1lOl0lO_dataout <= nl1O01OOi AND niOi1O0Ol; + wire_nl1lOl0O_dataout <= wire_nl1lOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOl0Oi_dataout <= nl1O01OOl AND niOi1O0Ol; + wire_nl1lOl0Ol_dataout <= nl1O01OOO AND niOi1O0Ol; + wire_nl1lOl0OO_dataout <= nl1O0011i AND niOi1O0Ol; + wire_nl1lOl10i_dataout <= nl1O1l1lO WHEN niOi1O00O = '1' ELSE wire_nl1lOlOil_dataout; + wire_nl1lOl10l_dataout <= nl1O1l1Oi WHEN niOi1O00O = '1' ELSE wire_nl1lOlOiO_dataout; + wire_nl1lOl10O_dataout <= nl1O1l1Ol WHEN niOi1O00O = '1' ELSE wire_nl1lOlOli_dataout; + wire_nl1lOl11i_dataout <= nl1O1l1iO WHEN niOi1O00O = '1' ELSE wire_nl1lOlO0l_dataout; + wire_nl1lOl11l_dataout <= nl1O1l1li WHEN niOi1O00O = '1' ELSE wire_nl1lOlO0O_dataout; + wire_nl1lOl11O_dataout <= nl1O1l1ll WHEN niOi1O00O = '1' ELSE wire_nl1lOlOii_dataout; + wire_nl1lOl1ii_dataout <= nl1O1l1OO WHEN niOi1O00O = '1' ELSE wire_nl1lOlOll_dataout; + wire_nl1lOl1il_dataout <= nl1O1l01i WHEN niOi1O00O = '1' ELSE wire_nl1lOlOlO_dataout; + wire_nl1lOl1iO_dataout <= nl1O1l01l WHEN niOi1O00O = '1' ELSE wire_nl1lOlOOi_dataout; + wire_nl1lOl1li_dataout <= nl1O1l01O WHEN niOi1O00O = '1' ELSE wire_nl1lOlOOl_dataout; + wire_nl1lOl1ll_dataout <= nl1O1l00i WHEN niOi1O00O = '1' ELSE wire_nl1lOlOOO_dataout; + wire_nl1lOl1lO_dataout <= nl1O1l00l WHEN niOi1O00O = '1' ELSE wire_nl1lOO11i_dataout; + wire_nl1lOl1Oi_dataout <= nl1O1l00O WHEN niOi1O00O = '1' ELSE wire_nl1lOO11l_dataout; + wire_nl1lOl1Ol_dataout <= nl1O01lOO AND niOi1O0Ol; + wire_nl1lOl1OO_dataout <= nl1O01O1i AND niOi1O0Ol; + wire_nl1lOli_dataout <= n1OillO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOli0i_dataout <= nl1O0010l AND niOi1O0Ol; + wire_nl1lOli0l_dataout <= nl1O0010O AND niOi1O0Ol; + wire_nl1lOli0O_dataout <= nl1O001ii AND niOi1O0Ol; + wire_nl1lOli1i_dataout <= nl1O0011l AND niOi1O0Ol; + wire_nl1lOli1l_dataout <= nl1O0011O AND niOi1O0Ol; + wire_nl1lOli1O_dataout <= nl1O0010i AND niOi1O0Ol; + wire_nl1lOlii_dataout <= wire_nl1lOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOliii_dataout <= nl1O001il AND niOi1O0Ol; + wire_nl1lOliil_dataout <= nl1O001iO AND niOi1O0Ol; + wire_nl1lOliiO_dataout <= nl1O001li AND niOi1O0Ol; + wire_nl1lOlil_dataout <= wire_nl1lOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOlili_dataout <= nl1O001ll AND niOi1O0Ol; + wire_nl1lOlill_dataout <= nl1O001lO AND niOi1O0Ol; + wire_nl1lOlilO_dataout <= nl1O001Oi AND niOi1O0Ol; + wire_nl1lOliO_dataout <= wire_nl1lOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOliOi_dataout <= nl1O001Ol AND niOi1O0Ol; + wire_nl1lOliOl_dataout <= nl1O001OO AND niOi1O0Ol; + wire_nl1lOliOO_dataout <= nl1O0001i AND niOi1O0Ol; + wire_nl1lOll_dataout <= n1OilOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOll0i_dataout <= nl1O0000l AND niOi1O0Ol; + wire_nl1lOll0l_dataout <= nl1O0000O AND niOi1O0Ol; + wire_nl1lOll0O_dataout <= nl1O000ii AND niOi1O0Ol; + wire_nl1lOll1i_dataout <= nl1O0001l AND niOi1O0Ol; + wire_nl1lOll1l_dataout <= nl1O0001O AND niOi1O0Ol; + wire_nl1lOll1O_dataout <= nl1O0000i AND niOi1O0Ol; + wire_nl1lOlli_dataout <= wire_nl1000i_w_lg_nl1lOill7802w(0) WHEN (wire_w_lg_niOO1lilO7801w(0) AND wire_w_lg_niOO1lill7803w(0)) = '1' ELSE nl1lOill; + wire_nl1lOllii_dataout <= nl1O000il AND niOi1O0Ol; + wire_nl1lOllil_dataout <= nl1O000iO AND niOi1O0Ol; + wire_nl1lOlliO_dataout <= nl1O000li AND niOi1O0Ol; + wire_nl1lOllli_dataout <= nl1O000ll AND niOi1O0Ol; + wire_nl1lOllll_dataout <= nl1O000lO AND niOi1O0Ol; + wire_nl1lOlllO_dataout <= nl1O000Oi AND niOi1O0Ol; + wire_nl1lOllO_dataout <= nl1lOO0i WHEN wire_w_lg_niOO1lilO7801w(0) = '1' ELSE nl1lOiOl; + wire_nl1lOllOi_dataout <= nl1O000Ol AND niOi1O0Ol; + wire_nl1lOllOl_dataout <= nl1O000OO AND niOi1O0Ol; + wire_nl1lOllOO_dataout <= nl1O00i1i AND niOi1O0Ol; + wire_nl1lOlO_dataout <= n1OilOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOlO0i_dataout <= nl1O00i0l AND niOi1O0Ol; + wire_nl1lOlO0l_dataout <= nl1O00i0O AND niOi1O0Ol; + wire_nl1lOlO0O_dataout <= nl1O00iii AND niOi1O0Ol; + wire_nl1lOlO1i_dataout <= nl1O00i1l AND niOi1O0Ol; + wire_nl1lOlO1l_dataout <= nl1O00i1O AND niOi1O0Ol; + wire_nl1lOlO1O_dataout <= nl1O00i0i AND niOi1O0Ol; + wire_nl1lOlOi_dataout <= nl1lOO0l WHEN wire_w_lg_niOO1lilO7801w(0) = '1' ELSE nl1lOiOO; + wire_nl1lOlOii_dataout <= nl1O00iil AND niOi1O0Ol; + wire_nl1lOlOil_dataout <= nl1O00iiO AND niOi1O0Ol; + wire_nl1lOlOiO_dataout <= nl1O00ili AND niOi1O0Ol; + wire_nl1lOlOl_dataout <= nl1lOO0O WHEN wire_w_lg_niOO1lilO7801w(0) = '1' ELSE nl1lOl1i; + wire_nl1lOlOli_dataout <= nl1O00ill AND niOi1O0Ol; + wire_nl1lOlOll_dataout <= nl1O00ilO AND niOi1O0Ol; + wire_nl1lOlOlO_dataout <= nl1O00iOi AND niOi1O0Ol; + wire_nl1lOlOO_dataout <= nl1lOOii WHEN wire_w_lg_niOO1lilO7801w(0) = '1' ELSE nl1lOl1l; + wire_nl1lOlOOi_dataout <= nl1O00iOl AND niOi1O0Ol; + wire_nl1lOlOOl_dataout <= nl1O00iOO AND niOi1O0Ol; + wire_nl1lOlOOO_dataout <= nl1O00l1i AND niOi1O0Ol; + wire_nl1lOO00i_dataout <= wire_nl1O111ii_dataout AND NOT(niOi1O0ii); + wire_nl1lOO00l_dataout <= wire_nl1O111il_dataout AND NOT(niOi1O0ii); + wire_nl1lOO00O_dataout <= wire_nl1O111iO_dataout AND NOT(niOi1O0ii); + wire_nl1lOO01i_dataout <= nl1O011Oi WHEN niOi1O0ii = '1' ELSE wire_nl1O1110i_dataout; + wire_nl1lOO01l_dataout <= nl1O011Ol WHEN niOi1O0ii = '1' ELSE wire_nl1O1110l_dataout; + wire_nl1lOO01O_dataout <= nl1O011OO WHEN niOi1O0ii = '1' ELSE wire_nl1O1110O_dataout; + wire_nl1lOO0ii_dataout <= nl1O0101i WHEN niOi1O0ii = '1' ELSE wire_nl1O111li_dataout; + wire_nl1lOO0il_dataout <= nl1O0101l WHEN niOi1O0ii = '1' ELSE wire_nl1O111ll_dataout; + wire_nl1lOO0iO_dataout <= nl1O0101O WHEN niOi1O0ii = '1' ELSE wire_nl1O111lO_dataout; + wire_nl1lOO0li_dataout <= nl1O0100i WHEN niOi1O0ii = '1' ELSE wire_nl1O111Oi_dataout; + wire_nl1lOO0ll_dataout <= nl1O0100l WHEN niOi1O0ii = '1' ELSE wire_nl1O111Ol_dataout; + wire_nl1lOO0lO_dataout <= nl1O0100O WHEN niOi1O0ii = '1' ELSE wire_nl1O111OO_dataout; + wire_nl1lOO0Oi_dataout <= nl1O010ii WHEN niOi1O0ii = '1' ELSE wire_nl1O1101i_dataout; + wire_nl1lOO0Ol_dataout <= nl1O010il WHEN niOi1O0ii = '1' ELSE wire_nl1O1101l_dataout; + wire_nl1lOO0OO_dataout <= nl1O010iO WHEN niOi1O0ii = '1' ELSE wire_nl1O1101O_dataout; + wire_nl1lOO10i_dataout <= nl1O0111i WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOii_dataout; + wire_nl1lOO10i_w_lg_dataout52155w(0) <= NOT wire_nl1lOO10i_dataout; + wire_nl1lOO10l_dataout <= nl1O0111l WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOil_dataout; + wire_nl1lOO10l_w_lg_dataout52147w(0) <= NOT wire_nl1lOO10l_dataout; + wire_nl1lOO10O_dataout <= nl1O0111O WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOiO_dataout; + wire_nl1lOO10O_w52150w(0) <= wire_nl1lOO10O_w_lg_w_lg_w_lg_dataout52141w52148w52149w(0) AND wire_nl1lOO11O_dataout; + wire_nl1lOO10O_w_lg_w_lg_w_lg_dataout52141w52148w52149w(0) <= wire_nl1lOO10O_w_lg_w_lg_dataout52141w52148w(0) AND wire_nl1lOO10i_dataout; + wire_nl1lOO10O_w_lg_w_lg_w_lg_dataout52141w52142w52151w(0) <= wire_nl1lOO10O_w_lg_w_lg_dataout52141w52142w(0) AND wire_nl1lOO10i_dataout; + wire_nl1lOO10O_w_lg_w_lg_dataout52141w52148w(0) <= wire_nl1lOO10O_w_lg_dataout52141w(0) AND wire_nl1lOO10l_w_lg_dataout52147w(0); + wire_nl1lOO10O_w_lg_w_lg_dataout52141w52142w(0) <= wire_nl1lOO10O_w_lg_dataout52141w(0) AND wire_nl1lOO10l_dataout; + wire_nl1lOO10O_w_lg_dataout52141w(0) <= NOT wire_nl1lOO10O_dataout; + wire_nl1lOO11i_dataout <= nl1O00l1l AND niOi1O0Ol; + wire_nl1lOO11l_dataout <= nl1O00l1O AND niOi1O0Ol; + wire_nl1lOO11O_dataout <= nl1O1OOOO WHEN niOi1O0ii = '1' ELSE wire_nl1lOOO0O_dataout; + wire_nl1lOO11O_w_lg_dataout52144w(0) <= NOT wire_nl1lOO11O_dataout; + wire_nl1lOO1i_dataout <= nl1O110l WHEN wire_w_lg_niOO1lilO7801w(0) = '1' ELSE nl1lOl1O; + wire_nl1lOO1ii_dataout <= nl1O0110i WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOli_dataout; + wire_nl1lOO1ii_w_lg_dataout52322w(0) <= NOT wire_nl1lOO1ii_dataout; + wire_nl1lOO1il_dataout <= nl1O0110l WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOll_dataout; + wire_nl1lOO1il_w_lg_dataout52291w(0) <= NOT wire_nl1lOO1il_dataout; + wire_nl1lOO1iO_dataout <= nl1O0110O WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOlO_dataout; + wire_nl1lOO1iO_w_lg_dataout52298w(0) <= NOT wire_nl1lOO1iO_dataout; + wire_nl1lOO1li_dataout <= nl1O011ii WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOOi_dataout; + wire_nl1lOO1li_w_lg_w_lg_w52301w52318w52319w(0) <= wire_nl1lOO1li_w_lg_w52301w52318w(0) AND wire_nl1lOO10l_dataout; + wire_nl1lOO1li_w_lg_w52301w52318w(0) <= wire_nl1lOO1li_w52301w(0) AND wire_nl1lOO10O_w_lg_dataout52141w(0); + wire_nl1lOO1li_w_lg_w52301w52302w(0) <= wire_nl1lOO1li_w52301w(0) AND wire_nl1lOO10O_dataout; + wire_nl1lOO1li_w_lg_w52323w52324w(0) <= wire_nl1lOO1li_w52323w(0) AND wire_nl1lOO10O_dataout; + wire_nl1lOO1li_w52301w(0) <= wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52299w52300w(0) AND wire_nl1lOO1ii_dataout; + wire_nl1lOO1li_w52309w(0) <= wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52299w52308w(0) AND wire_nl1lOO1ii_dataout; + wire_nl1lOO1li_w52323w(0) <= wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52290w52292w(0) AND wire_nl1lOO1ii_w_lg_dataout52322w(0); + wire_nl1lOO1li_w52293w(0) <= wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52290w52292w(0) AND wire_nl1lOO1ii_dataout; + wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52299w52300w(0) <= wire_nl1lOO1li_w_lg_w_lg_dataout52289w52299w(0) AND wire_nl1lOO1il_w_lg_dataout52291w(0); + wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52299w52308w(0) <= wire_nl1lOO1li_w_lg_w_lg_dataout52289w52299w(0) AND wire_nl1lOO1il_dataout; + wire_nl1lOO1li_w_lg_w_lg_w_lg_dataout52289w52290w52292w(0) <= wire_nl1lOO1li_w_lg_w_lg_dataout52289w52290w(0) AND wire_nl1lOO1il_w_lg_dataout52291w(0); + wire_nl1lOO1li_w_lg_w_lg_dataout52289w52299w(0) <= wire_nl1lOO1li_w_lg_dataout52289w(0) AND wire_nl1lOO1iO_w_lg_dataout52298w(0); + wire_nl1lOO1li_w_lg_w_lg_dataout52289w52290w(0) <= wire_nl1lOO1li_w_lg_dataout52289w(0) AND wire_nl1lOO1iO_dataout; + wire_nl1lOO1li_w_lg_dataout52289w(0) <= NOT wire_nl1lOO1li_dataout; + wire_nl1lOO1ll_dataout <= nl1O011il WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOOl_dataout; + wire_nl1lOO1ll_w_lg_dataout56970w(0) <= NOT wire_nl1lOO1ll_dataout; + wire_nl1lOO1lO_dataout <= nl1O011iO WHEN niOi1O0ii = '1' ELSE wire_nl1lOOOOO_dataout; + wire_nl1lOO1lO_w_lg_dataout56968w(0) <= NOT wire_nl1lOO1lO_dataout; + wire_nl1lOO1Oi_dataout <= nl1O011li WHEN niOi1O0ii = '1' ELSE wire_nl1O1111i_dataout; + wire_nl1lOO1Oi_w_lg_dataout56966w(0) <= NOT wire_nl1lOO1Oi_dataout; + wire_nl1lOO1Ol_dataout <= nl1O011ll WHEN niOi1O0ii = '1' ELSE wire_nl1O1111l_dataout; + wire_nl1lOO1Ol_w_lg_dataout56965w(0) <= NOT wire_nl1lOO1Ol_dataout; + wire_nl1lOO1OO_dataout <= nl1O011lO WHEN niOi1O0ii = '1' ELSE wire_nl1O1111O_dataout; + wire_nl1lOOi_dataout <= n1OilOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOOi0i_dataout <= nl1O010Oi WHEN niOi1O0ii = '1' ELSE wire_nl1O110ii_dataout; + wire_nl1lOOi0l_dataout <= nl1O010Ol WHEN niOi1O0ii = '1' ELSE wire_nl1O110il_dataout; + wire_nl1lOOi0l_w_lg_w_lg_dataout52550w55799w(0) <= wire_nl1lOOi0l_w_lg_dataout52550w(0) AND niOi1lO1O; + wire_nl1lOOi0l_w_lg_dataout55804w(0) <= wire_nl1lOOi0l_dataout AND niOi1lO1i; + wire_nl1lOOi0l_w_lg_dataout52550w(0) <= NOT wire_nl1lOOi0l_dataout; + wire_nl1lOOi0O_dataout <= nl1O010OO WHEN niOi1O0ii = '1' ELSE wire_nl1O110iO_dataout; + wire_nl1lOOi0O_w_lg_dataout52548w(0) <= NOT wire_nl1lOOi0O_dataout; + wire_nl1lOOi1i_dataout <= nl1O010li WHEN niOi1O0ii = '1' ELSE wire_nl1O1100i_dataout; + wire_nl1lOOi1l_dataout <= nl1O010ll WHEN niOi1O0ii = '1' ELSE wire_nl1O1100l_dataout; + wire_nl1lOOi1O_dataout <= nl1O010lO WHEN niOi1O0ii = '1' ELSE wire_nl1O1100O_dataout; + wire_nl1lOOiii_dataout <= nl1O01i1i WHEN niOi1O0ii = '1' ELSE wire_nl1O110li_dataout; + wire_nl1lOOiii_w_lg_dataout52546w(0) <= NOT wire_nl1lOOiii_dataout; + wire_nl1lOOiil_dataout <= nl1O01i1l WHEN niOi1O0ii = '1' ELSE wire_nl1O110ll_dataout; + wire_nl1lOOiil_w_lg_dataout52544w(0) <= NOT wire_nl1lOOiil_dataout; + wire_nl1lOOiiO_dataout <= nl1O01i1O WHEN niOi1O0ii = '1' ELSE wire_nl1O110lO_dataout; + wire_nl1lOOiiO_w_lg_dataout52542w(0) <= NOT wire_nl1lOOiiO_dataout; + wire_nl1lOOili_dataout <= nl1O01i0i WHEN niOi1O0ii = '1' ELSE wire_nl1O110Oi_dataout; + wire_nl1lOOili_w_lg_dataout52540w(0) <= NOT wire_nl1lOOili_dataout; + wire_nl1lOOill_dataout <= nl1O01i0l WHEN niOi1O0ii = '1' ELSE wire_nl1O110Ol_dataout; + wire_nl1lOOill_w_lg_dataout52538w(0) <= NOT wire_nl1lOOill_dataout; + wire_nl1lOOilO_dataout <= nl1O01i0O WHEN niOi1O0ii = '1' ELSE wire_nl1O110OO_dataout; + wire_nl1lOOilO_w_lg_dataout52536w(0) <= NOT wire_nl1lOOilO_dataout; + wire_nl1lOOiO_dataout <= wire_nl1lOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOOiOi_dataout <= nl1O01iii WHEN niOi1O0ii = '1' ELSE wire_nl1O11i1i_dataout; + wire_nl1lOOiOi_w_lg_dataout52534w(0) <= NOT wire_nl1lOOiOi_dataout; + wire_nl1lOOiOl_dataout <= nl1O01iil WHEN niOi1O0ii = '1' ELSE wire_nl1O11i1l_dataout; + wire_nl1lOOiOl_w_lg_w_lg_w52547w52549w52552w(0) <= wire_nl1lOOiOl_w_lg_w52547w52549w(0) AND wire_nl1lOOi0l_dataout; + wire_nl1lOOiOl_w_lg_w52547w52549w(0) <= wire_nl1lOOiOl_w52547w(0) AND wire_nl1lOOi0O_w_lg_dataout52548w(0); + wire_nl1lOOiOl_w_lg_w52547w56985w(0) <= wire_nl1lOOiOl_w52547w(0) AND wire_nl1lOOi0O_dataout; + wire_nl1lOOiOl_w52547w(0) <= wire_nl1lOOiOl_w_lg_w_lg_w_lg_w52539w52541w52543w52545w(0) AND wire_nl1lOOiii_w_lg_dataout52546w(0); + wire_nl1lOOiOl_w_lg_w_lg_w_lg_w52539w52541w52543w52545w(0) <= wire_nl1lOOiOl_w_lg_w_lg_w52539w52541w52543w(0) AND wire_nl1lOOiil_w_lg_dataout52544w(0); + wire_nl1lOOiOl_w_lg_w_lg_w52539w52541w52543w(0) <= wire_nl1lOOiOl_w_lg_w52539w52541w(0) AND wire_nl1lOOiiO_w_lg_dataout52542w(0); + wire_nl1lOOiOl_w_lg_w52539w52541w(0) <= wire_nl1lOOiOl_w52539w(0) AND wire_nl1lOOili_w_lg_dataout52540w(0); + wire_nl1lOOiOl_w52539w(0) <= wire_nl1lOOiOl_w_lg_w_lg_w_lg_dataout52533w52535w52537w(0) AND wire_nl1lOOill_w_lg_dataout52538w(0); + wire_nl1lOOiOl_w_lg_w_lg_w_lg_dataout52533w52535w52537w(0) <= wire_nl1lOOiOl_w_lg_w_lg_dataout52533w52535w(0) AND wire_nl1lOOilO_w_lg_dataout52536w(0); + wire_nl1lOOiOl_w_lg_w_lg_dataout52533w52535w(0) <= wire_nl1lOOiOl_w_lg_dataout52533w(0) AND wire_nl1lOOiOi_w_lg_dataout52534w(0); + wire_nl1lOOiOl_w_lg_dataout52533w(0) <= NOT wire_nl1lOOiOl_dataout; + wire_nl1lOOiOO_dataout <= nl1O01iiO WHEN niOi1O0ii = '1' ELSE wire_nl1O11i1O_dataout; + wire_nl1lOOiOO_w_lg_dataout56960w(0) <= NOT wire_nl1lOOiOO_dataout; + wire_nl1lOOl_dataout <= n1OiO1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOOl0i_dataout <= nl1O01iOi WHEN niOi1O0ii = '1' ELSE wire_nl1O11iii_dataout; + wire_nl1lOOl0i_w_lg_dataout52050w(0) <= NOT wire_nl1lOOl0i_dataout; + wire_nl1lOOl0l_dataout <= nl1O01iOl WHEN niOi1O0ii = '1' ELSE wire_nl1O11iil_dataout; + wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55802w(0) <= wire_nl1lOOl0l_w_lg_dataout54725w(0) AND niOi1llOO; + wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55798w(0) <= wire_nl1lOOl0l_w_lg_dataout54725w(0) AND niOi1lO1l; + wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55409w(0) <= wire_nl1lOOl0l_w_lg_dataout54725w(0) AND niOi1O11l; + wire_nl1lOOl0l_w_lg_dataout55800w(0) <= wire_nl1lOOl0l_dataout AND wire_nl1lOOi0l_w_lg_w_lg_dataout52550w55799w(0); + wire_nl1lOOl0l_w_lg_dataout55805w(0) <= wire_nl1lOOl0l_dataout AND wire_nl1lOOi0l_w_lg_dataout55804w(0); + wire_nl1lOOl0l_w_lg_dataout54725w(0) <= NOT wire_nl1lOOl0l_dataout; + wire_nl1lOOl0O_dataout <= nl1O01iOO WHEN niOi1O0ii = '1' ELSE wire_nl1O11iiO_dataout; + wire_nl1lOOl1i_dataout <= nl1O01ili WHEN niOi1O0ii = '1' ELSE wire_nl1O11i0i_dataout; + wire_nl1lOOl1i_w_lg_dataout56962w(0) <= NOT wire_nl1lOOl1i_dataout; + wire_nl1lOOl1l_dataout <= nl1O01ill WHEN niOi1O0ii = '1' ELSE wire_nl1O11i0l_dataout; + wire_nl1lOOl1O_dataout <= nl1O01ilO WHEN niOi1O0ii = '1' ELSE wire_nl1O11i0O_dataout; + wire_nl1lOOli_dataout <= wire_nl1lOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOOlii_dataout <= nl1O01l1i WHEN niOi1O0ii = '1' ELSE wire_nl1O11ili_dataout; + wire_nl1lOOlil_dataout <= nl1O01l1l WHEN niOi1O0ii = '1' ELSE wire_nl1O11ill_dataout; + wire_nl1lOOliO_dataout <= nl1O01l1O WHEN niOi1O0ii = '1' ELSE wire_nl1O11ilO_dataout; + wire_nl1lOOll_dataout <= wire_nl1O111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOOlli_dataout <= nl1O01l0i WHEN niOi1O0ii = '1' ELSE wire_nl1O11iOi_dataout; + wire_nl1lOOlll_dataout <= nl1O01l0l WHEN niOi1O0ii = '1' ELSE wire_nl1O11iOl_dataout; + wire_nl1lOOllO_dataout <= nl1O01l0O WHEN niOi1O0ii = '1' ELSE wire_nl1O11iOO_dataout; + wire_nl1lOOlO_dataout <= wire_nl1O111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOOlOi_dataout <= nl1O01lii WHEN niOi1O0ii = '1' ELSE wire_nl1O11l1i_dataout; + wire_nl1lOOlOi_w_lg_dataout55789w(0) <= NOT wire_nl1lOOlOi_dataout; + wire_nl1lOOlOi_w_lg_dataout55410w(0) <= wire_nl1lOOlOi_dataout OR wire_nl1lOOl0l_w_lg_w_lg_dataout54725w55409w(0); + wire_nl1lOOlOi_w_lg_dataout55417w(0) <= wire_nl1lOOlOi_dataout OR niOi1O11l; + wire_nl1lOOlOl_dataout <= nl1O01lil WHEN niOi1O0ii = '1' ELSE wire_nl1O11l1l_dataout; + wire_nl1lOOlOl_w_lg_dataout52282w(0) <= NOT wire_nl1lOOlOl_dataout; + wire_nl1lOOlOO_dataout <= nl1O01liO WHEN niOi1O0ii = '1' ELSE wire_nl1O11l1O_dataout; + wire_nl1lOOlOO_w_lg_dataout52012w(0) <= NOT wire_nl1lOOlOO_dataout; + wire_nl1lOOO_dataout <= n1OiO1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1lOOO0i_dataout <= nl1O01lOi WHEN niOi1O0ii = '1' ELSE wire_nl1O11lii_dataout; + wire_nl1lOOO0i_w_lg_w_lg_w_lg_w_lg_dataout5075w52330w52331w52332w(0) <= wire_nl1lOOO0i_w_lg_w_lg_w_lg_dataout5075w52330w52331w(0) AND wire_nl1lOOO1i_dataout; + wire_nl1lOOO0i_w_lg_w_lg_w_lg_dataout5075w52330w52331w(0) <= wire_nl1lOOO0i_w_lg_w_lg_dataout5075w52330w(0) AND wire_nl1lOOO1l_w_lg_dataout5083w(0); + wire_nl1lOOO0i_w_lg_w_lg_dataout5075w52330w(0) <= wire_nl1lOOO0i_w_lg_dataout5075w(0) AND wire_nl1lOOO1O_w_lg_dataout5082w(0); + wire_nl1lOOO0i_w_lg_w_lg_dataout5075w5688w(0) <= wire_nl1lOOO0i_w_lg_dataout5075w(0) AND wire_nlll0liO_w_lg_dataout5087w(0); + wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55411w(0) <= wire_nl1lOOO0i_w_lg_dataout5075w(0) AND wire_nl1lOOlOi_w_lg_dataout55410w(0); + wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55418w(0) <= wire_nl1lOOO0i_w_lg_dataout5075w(0) AND wire_nl1lOOlOi_w_lg_dataout55417w(0); + wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55791w(0) <= wire_nl1lOOO0i_w_lg_dataout5075w(0) AND wire_nl1lOOlOi_dataout; + wire_nl1lOOO0i_w_lg_w_lg_dataout5075w55507w(0) <= wire_nl1lOOO0i_w_lg_dataout5075w(0) AND niOi1O11l; + wire_nl1lOOO0i_w_lg_dataout56210w(0) <= wire_nl1lOOO0i_dataout AND wire_nl1lOOO1O_w_lg_dataout56209w(0); + wire_nl1lOOO0i_w_lg_dataout55790w(0) <= wire_nl1lOOO0i_dataout AND wire_nl1lOOlOi_w_lg_dataout55789w(0); + wire_nl1lOOO0i_w_lg_dataout5075w(0) <= NOT wire_nl1lOOO0i_dataout; + wire_nl1lOOO0i_w_lg_dataout5689w(0) <= wire_nl1lOOO0i_dataout OR wire_nl1lOOO0i_w_lg_w_lg_dataout5075w5688w(0); + wire_nl1lOOO0l_dataout <= nl1O01lOl WHEN niOi1O0ii = '1' ELSE wire_nl1O11lil_dataout; + wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout54760w56981w56982w(0) <= wire_nl1lOOO0l_w_lg_w_lg_dataout54760w56981w(0) AND wire_nl1lOOO1l_dataout; + wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout52008w56221w56222w(0) <= wire_nl1lOOO0l_w_lg_w_lg_dataout52008w56221w(0) AND nlliO1Oi; + wire_nl1lOOO0l_w_lg_w_lg_dataout54760w56981w(0) <= wire_nl1lOOO0l_w_lg_dataout54760w(0) AND wire_nl1lOOO1O_w_lg_dataout5082w(0); + wire_nl1lOOO0l_w_lg_w_lg_dataout52008w54761w(0) <= wire_nl1lOOO0l_w_lg_dataout52008w(0) AND wire_nl1lOOO0i_dataout; + wire_nl1lOOO0l_w_lg_w_lg_dataout52008w55818w(0) <= wire_nl1lOOO0l_w_lg_dataout52008w(0) AND niOi1llOl; + wire_nl1lOOO0l_w_lg_w_lg_dataout52008w52009w(0) <= wire_nl1lOOO0l_w_lg_dataout52008w(0) AND niOii1OOi; + wire_nl1lOOO0l_w_lg_w_lg_dataout52008w56221w(0) <= wire_nl1lOOO0l_w_lg_dataout52008w(0) AND nl1iiO0li; + wire_nl1lOOO0l_w_lg_dataout54760w(0) <= wire_nl1lOOO0l_dataout AND wire_nl1lOOO0i_w_lg_dataout5075w(0); + wire_nl1lOOO0l_w_lg_dataout52008w(0) <= NOT wire_nl1lOOO0l_dataout; + wire_nl1lOOO0l_w_lg_w_lg_w_lg_dataout52008w52009w52010w(0) <= wire_nl1lOOO0l_w_lg_w_lg_dataout52008w52009w(0) OR niOii1OlO; + wire_nl1lOOO0O_dataout <= nl1O1l0ii WHEN niOi1O0il = '1' ELSE wire_nl1O11liO_dataout; + wire_nl1lOOO1i_dataout <= nl1O01lli WHEN niOi1O0ii = '1' ELSE wire_nl1O11l0i_dataout; + wire_nl1lOOO1i_w_lg_dataout5085w(0) <= NOT wire_nl1lOOO1i_dataout; + wire_nl1lOOO1l_dataout <= nl1O01lll WHEN niOi1O0ii = '1' ELSE wire_nl1O11l0l_dataout; + wire_nl1lOOO1l_w_lg_dataout5083w(0) <= NOT wire_nl1lOOO1l_dataout; + wire_nl1lOOO1O_dataout <= nl1O01llO WHEN niOi1O0ii = '1' ELSE wire_nl1O11l0O_dataout; + wire_nl1lOOO1O_w_lg_w_lg_w_lg_w_lg_dataout5082w5084w5086w52281w(0) <= wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w5086w(0) AND wire_nl1lOOlOO_dataout; + wire_nl1lOOO1O_w_lg_w_lg_w_lg_w_lg_dataout5082w56204w56205w56206w(0) <= wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w56204w56205w(0) AND wire_nl1lOOlOO_dataout; + wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w5086w(0) <= wire_nl1lOOO1O_w_lg_w_lg_dataout5082w5084w(0) AND wire_nl1lOOO1i_w_lg_dataout5085w(0); + wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w52011w(0) <= wire_nl1lOOO1O_w_lg_w_lg_dataout5082w5084w(0) AND wire_nl1lOOO1i_dataout; + wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w56204w56205w(0) <= wire_nl1lOOO1O_w_lg_w_lg_dataout5082w56204w(0) AND wire_nl1lOOO1i_w_lg_dataout5085w(0); + wire_nl1lOOO1O_w_lg_w_lg_dataout5082w5084w(0) <= wire_nl1lOOO1O_w_lg_dataout5082w(0) AND wire_nl1lOOO1l_w_lg_dataout5083w(0); + wire_nl1lOOO1O_w_lg_w_lg_dataout5082w56204w(0) <= wire_nl1lOOO1O_w_lg_dataout5082w(0) AND wire_nl1lOOO1l_dataout; + wire_nl1lOOO1O_w_lg_dataout56209w(0) <= wire_nl1lOOO1O_dataout AND wire_nl1lOOO1l_w_lg_dataout5083w(0); + wire_nl1lOOO1O_w_lg_dataout5082w(0) <= NOT wire_nl1lOOO1O_dataout; + wire_nl1lOOOi_dataout <= wire_nl1O111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1lOOOii_dataout <= nl1O1l0il WHEN niOi1O0il = '1' ELSE wire_nl1O11lli_dataout; + wire_nl1lOOOil_dataout <= nl1O1l0iO WHEN niOi1O0il = '1' ELSE wire_nl1O11lll_dataout; + wire_nl1lOOOiO_dataout <= nl1O1l0li WHEN niOi1O0il = '1' ELSE wire_nl1O11llO_dataout; + wire_nl1lOOOl_dataout <= wire_nl1000i_w_lg_nl1O110l7798w(0) WHEN niOO1liOi = '1' ELSE nl1O110l; + wire_nl1lOOOli_dataout <= nl1O1l0ll WHEN niOi1O0il = '1' ELSE wire_nl1O11lOi_dataout; + wire_nl1lOOOll_dataout <= nl1O1l0lO WHEN niOi1O0il = '1' ELSE wire_nl1O11lOl_dataout; + wire_nl1lOOOlO_dataout <= nl1O1l0Oi WHEN niOi1O0il = '1' ELSE wire_nl1O11lOO_dataout; + wire_nl1lOOOO_dataout <= nlliiil1l WHEN niOO1liOi = '1' ELSE nl1lOO0i; + wire_nl1lOOOOi_dataout <= nl1O1l0Ol WHEN niOi1O0il = '1' ELSE wire_nl1O11O1i_dataout; + wire_nl1lOOOOl_dataout <= nl1O1l0OO WHEN niOi1O0il = '1' ELSE wire_nl1O11O1l_dataout; + wire_nl1lOOOOO_dataout <= nl1O1li1i WHEN niOi1O0il = '1' ELSE wire_nl1O11O1O_dataout; + wire_nl1O000l_dataout <= nl1O00ii AND NOT(wire_niO01O0O_dataout); + wire_nl1O001i_dataout <= nl1O000i AND NOT(wire_niO01l0O_dataout); + wire_nl1O001O_dataout <= nl1O01li AND NOT(wire_niO01l0O_dataout); + wire_nl1O00i_dataout <= n1Ol10O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1iil; + wire_nl1O00il_dataout <= nl1O000O AND NOT(wire_niO01O0O_dataout); + wire_nl1O00iO_dataout <= nl1O001l AND NOT(wire_niO01O0O_dataout); + wire_nl1O00l_dataout <= n1Ol1ii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1iiO; + wire_nl1O00ll_dataout <= wire_nl1O00Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O00lO_dataout <= wire_nl1O0i1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O00O_dataout <= n1Ol1il WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1ili; + wire_nl1O00Oi_dataout <= wire_niOOO0O_w_lg_nl1O00ii7754w(0) WHEN (wire_w_lg_niOO1ll1O7755w(0) AND wire_w_lg_w_dl_req_phypm_range7753w7756w(0)) = '1' ELSE nl1O00ii; + wire_nl1O010i_dataout <= wire_nl1000i_w_lg_nl1O1OOi7761w(0) WHEN (wire_ni0l01O_dataout AND (wire_w_lg_niOO1ll1l7762w(0) AND (wire_ni0l01O_dataout XOR nl1O011i))) = '1' ELSE nl1O1OOi; + wire_nl1O011l_dataout <= wire_nl1O010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O011O_dataout <= wire_nl1O01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O01i_dataout <= n1Ol11O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1i0l; + wire_nl1O01il_dataout <= nl1O011i WHEN niOO1ll1l = '1' ELSE wire_ni0l01O_dataout; + wire_nl1O01l_dataout <= n1Ol10i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1i0O; + wire_nl1O01ll_dataout <= wire_nl1O01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O01lO_dataout <= wire_nl1000i_w_lg_nl1O01Ol7758w(0) WHEN (nl1O000O XOR nl1O000i) = '1' ELSE nl1O01Ol; + wire_nl1O01O_dataout <= n1Ol10l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1iii; + wire_nl1O0i0i_dataout <= wire_nl1O0i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0i0l_dataout <= wire_nl1000i_w_lg_nl1O0iii7750w(0) WHEN (nl1O0iOl XOR nl1O0ilO) = '1' ELSE nl1O0iii; + wire_nl1O0i1i_dataout <= nl1O00li WHEN niOO1ll1O = '1' ELSE dl_req_phypm(0); + wire_nl1O0ii_dataout <= n1Ol1iO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1ill; + wire_nl1O0iiil_dataout <= wire_nl1Oi0O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iiiO_dataout <= wire_nl1Oi0O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iili_dataout <= wire_nl1Oi0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iill_dataout <= wire_nl1Oi0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iilO_dataout <= nl0101lOl AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iiO_dataout <= nl1O0ilO AND NOT(wire_niO01l0O_dataout); + wire_nl1O0iiOi_dataout <= nl0101lOO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iiOl_dataout <= nl0101O1i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iiOO_dataout <= nl0101O1l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0il_dataout <= n1Ol1li WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1ilO; + wire_nl1O0il0i_dataout <= nl0101O0O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0il0l_dataout <= nl0101Oii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0il0O_dataout <= nl0101Oil AND NOT(wire_niO01O0O_dataout); + wire_nl1O0il1i_dataout <= nl0101O1O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0il1l_dataout <= nl0101O0i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0il1O_dataout <= nl0101O0l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ilii_dataout <= nl0101OiO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ilil_dataout <= nl0101Oli AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iliO_dataout <= nl0101Oll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ill_dataout <= nl1O0i1O AND NOT(wire_niO01l0O_dataout); + wire_nl1O0illi_dataout <= nl0101OlO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0illl_dataout <= nl0101OOi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0illO_dataout <= nl0101OOl AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ilOi_dataout <= nl0101OOO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ilOl_dataout <= nl010011i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ilOO_dataout <= nl010011l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iO_dataout <= n1Ol1ll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1iOi; + wire_nl1O0iO0i_dataout <= nl010010O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iO0l_dataout <= nl01001ii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iO0O_dataout <= nl01001il AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iO1i_dataout <= nl010011O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iO1l_dataout <= nl010010i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iO1O_dataout <= nl010010l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOi_dataout <= nl1O0iOO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOii_dataout <= nl01001iO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOil_dataout <= nl01001li AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOiO_dataout <= nl01001ll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOli_dataout <= nl01001lO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOll_dataout <= nl01001Oi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOlO_dataout <= nl01001Ol AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOOi_dataout <= nl01001OO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOOl_dataout <= nl010001i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0iOOO_dataout <= nl010001l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l00i_dataout <= nl0100i0O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l00l_dataout <= nl0100iii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l00O_dataout <= nl0100iil AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l01i_dataout <= wire_nl010111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l01l_dataout <= wire_nl010111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l01O_dataout <= wire_nl010111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0i_dataout <= wire_nl1O0l0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O0l0ii_dataout <= wire_nl010110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0il_dataout <= niOO0O1OO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0iO_dataout <= nl0100ill AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0l_dataout <= wire_nl1O0liO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O0l0li_dataout <= nl0100ilO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0ll_dataout <= wire_nl010110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0lO_dataout <= wire_nl01011ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0O_dataout <= wire_niOOO0O_w_lg_nl1O0iOO7746w(0) WHEN (wire_w_lg_niOO1ll0i7747w(0) AND wire_w_lg_w_dl_req_phypm_range7745w7748w(0)) = '1' ELSE nl1O0iOO; + wire_nl1O0l0Oi_dataout <= wire_nl01011il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0Ol_dataout <= wire_nl01011iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l0OO_dataout <= wire_nl01011li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l10i_dataout <= nl010000O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l10l_dataout <= nl01000ii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l10O_dataout <= nl01000il AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l11i_dataout <= nl010001O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l11l_dataout <= nl010000i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l11O_dataout <= nl010000l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1i_dataout <= nl1O0iOl AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1ii_dataout <= nl01000iO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1il_dataout <= nl01000li AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1iO_dataout <= wire_nl011OOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1l_dataout <= nl1O0ili AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1li_dataout <= wire_nl011OOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1ll_dataout <= nl01000Oi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1lO_dataout <= nl01000Ol AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1Oi_dataout <= nl01000OO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1Ol_dataout <= nl0100i1i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0l1OO_dataout <= wire_nl011OOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0li_dataout <= n1Ol1lO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1iOl; + wire_nl1O0li0i_dataout <= nl00li0ll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0li0l_dataout <= nl00li0lO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0li0O_dataout <= nl00li0Oi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0li1i_dataout <= nl00li0ii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0li1l_dataout <= nl00li0iO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0li1O_dataout <= nl00li0li AND NOT(wire_niO01O0O_dataout); + wire_nl1O0liii_dataout <= nl00li0Ol AND NOT(wire_niO01O0O_dataout); + wire_nl1O0liil_dataout <= nl00li0OO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0liiO_dataout <= nl00lii1i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lili_dataout <= nl00lii1l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lill_dataout <= nl00lii1O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lilO_dataout <= nl00lii0i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0liO_dataout <= nl1O0l1O WHEN niOO1ll0i = '1' ELSE dl_req_phypm(1); + wire_nl1O0liOi_dataout <= nl00lii0l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0liOl_dataout <= nl00lii0O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0liOO_dataout <= nl00liiii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ll_dataout <= n1Ol1Oi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1iOO; + wire_nl1O0ll0i_dataout <= nl00liill AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ll0l_dataout <= nl00liilO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ll0O_dataout <= nl00liiOi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ll1i_dataout <= nl00liiil AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ll1l_dataout <= nl00liiiO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0ll1O_dataout <= nl00liili AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llii_dataout <= nl00liiOl AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llil_dataout <= nl00liiOO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lliO_dataout <= nl00lil1i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llli_dataout <= nl00lil1l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llll_dataout <= nl00lil1O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lllO_dataout <= nl00lil0i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llO_dataout <= wire_nl1O0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llOi_dataout <= nl00lil0l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llOl_dataout <= nl00lil0O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0llOO_dataout <= nl00lilii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lO_dataout <= n1Ol1Ol WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1l1i; + wire_nl1O0lO0i_dataout <= nl00lilll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lO0l_dataout <= nl00lillO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lO0O_dataout <= nl00lilOi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lO1i_dataout <= nl00lilil AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lO1l_dataout <= nl00liliO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lO1O_dataout <= nl00lilli AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOi_dataout <= wire_nl1000i_w_lg_nl1O0lOO7742w(0) WHEN (nl1O0Oii XOR nl1O0O0l) = '1' ELSE nl1O0lOO; + wire_nl1O0lOii_dataout <= nl00lilOl AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOil_dataout <= nl00lilOO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOiO_dataout <= nl00liO1i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOli_dataout <= nl00liO1l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOll_dataout <= nl00liO1O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOlO_dataout <= nl00liO0i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOOi_dataout <= nl00liO0l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOOl_dataout <= nl00liO0O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0lOOO_dataout <= nl00liOii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O00i_dataout <= nl00ll1ll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O00l_dataout <= nl00ll1lO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O00O_dataout <= nl00ll1Oi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O01i_dataout <= nl00ll1il AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O01l_dataout <= nl00ll1iO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O01O_dataout <= nl00ll1li AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0i_dataout <= nl1O0lll AND NOT(wire_niO01l0O_dataout); + wire_nl1O0O0ii_dataout <= nl00ll1Ol AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0il_dataout <= nl00ll1OO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0iO_dataout <= nl00ll01i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0li_dataout <= nl00ll01l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0ll_dataout <= nl00ll01O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0lO_dataout <= nl00ll00i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0O_dataout <= nl1O0Oil AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0Oi_dataout <= nl00ll00l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0Ol_dataout <= nl00ll00O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O0OO_dataout <= nl00ll0ii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O10i_dataout <= nl00liOll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O10l_dataout <= nl00liOlO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O10O_dataout <= nl00liOOi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O11i_dataout <= nl00liOil AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O11l_dataout <= nl00liOiO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O11O_dataout <= nl00liOli AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1ii_dataout <= nl00liOOl AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1il_dataout <= nl00liOOO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1iO_dataout <= nl00ll11i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1l_dataout <= nl1O0O0l AND NOT(wire_niO01l0O_dataout); + wire_nl1O0O1li_dataout <= nl00ll11l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1ll_dataout <= nl00ll11O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1lO_dataout <= nl00ll10i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1Oi_dataout <= nl00ll10l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1Ol_dataout <= nl00ll10O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0O1OO_dataout <= nl00ll1ii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oi_dataout <= n1Ol1OO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1l1l; + wire_nl1O0Oi0i_dataout <= nl00ll0ll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oi0l_dataout <= nl00ll0lO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oi0O_dataout <= wire_nl0iO0l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oi1i_dataout <= nl00ll0il AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oi1l_dataout <= nl00ll0iO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oi1O_dataout <= nl00ll0li AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oiii_dataout <= wire_nl0iO0l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oiil_dataout <= wire_nl0iO0l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OiiO_dataout <= wire_nl0iO0lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oili_dataout <= wire_nl0iO0lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oill_dataout <= wire_nl0iO0liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OilO_dataout <= wire_nl0iO0lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OiO_dataout <= nl1O0Oii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OiOi_dataout <= wire_nl0iO0lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OiOl_dataout <= wire_nl0iO0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OiOO_dataout <= wire_nl0iO0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Ol_dataout <= n1Ol01i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1l1O; + wire_nl1O0Ol0i_dataout <= nl00ll0Oi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Ol0l_dataout <= nl00ll0Ol AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Ol0O_dataout <= nl00ll0OO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Ol1i_dataout <= wire_nl0iO0lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Ol1l_dataout <= wire_nl0iO0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Ol1O_dataout <= wire_nl0iO0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Oli_dataout <= nl1O0O1O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Olii_dataout <= nl00lli1i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Olil_dataout <= nl00lli1l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OliO_dataout <= nl00lli1O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Olli_dataout <= nl00lli0i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0Olll_dataout <= nl00lli0l AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OllO_dataout <= nl00lli0O AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OlO_dataout <= wire_nl1O0OOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O0OlOi_dataout <= nl00lliii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OlOl_dataout <= nl00lilli AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OlOO_dataout <= nl00lilll AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OO_dataout <= n1Ol01l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1l0i; + wire_nl1O0OO0i_dataout <= nl00llill AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OO0l_dataout <= nl00ll1ii AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OO0O_dataout <= nl00ll1il AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OO1i_dataout <= nl00lliil AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OO1l_dataout <= nl00lliiO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OO1O_dataout <= nl00llili AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOi_dataout <= wire_nl1Oi11l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O0OOii_dataout <= nl00ll1iO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOil_dataout <= nl00ll1li AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOiO_dataout <= nl00llilO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOl_dataout <= wire_niOOO0O_w_lg_nl1O0Oil7738w(0) WHEN (wire_w_lg_niOO1ll0l7739w(0) AND wire_w_lg_w_dl_req_phypm_range7737w7740w(0)) = '1' ELSE nl1O0Oil; + wire_nl1O0OOli_dataout <= nl00lliOi AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOll_dataout <= nl00lliOl AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOlO_dataout <= wire_nl00l0O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOOi_dataout <= nl00lliOO AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOOl_dataout <= nl00lll1i AND NOT(wire_niO01O0O_dataout); + wire_nl1O0OOOO_dataout <= nl00lll1l AND NOT(wire_niO01O0O_dataout); + wire_nl1O1000i_dataout <= nl1O1iOOi WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1ii_dataout; + wire_nl1O1000l_dataout <= nl1O1iOOl WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1il_dataout; + wire_nl1O1000O_dataout <= nl1O1iOOO WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1iO_dataout; + wire_nl1O1001i_dataout <= nl1O1iOli WHEN niOi1O0iO = '1' ELSE wire_nl1O1i10i_dataout; + wire_nl1O1001l_dataout <= nl1O1iOll WHEN niOi1O0iO = '1' ELSE wire_nl1O1i10l_dataout; + wire_nl1O1001O_dataout <= nl1O1iOlO WHEN niOi1O0iO = '1' ELSE wire_nl1O1i10O_dataout; + wire_nl1O100ii_dataout <= nl1O1l11i WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1li_dataout; + wire_nl1O100il_dataout <= nl1O1l11l WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1ll_dataout; + wire_nl1O100iO_dataout <= nl1O1l11O WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1lO_dataout; + wire_nl1O100li_dataout <= nl1O1l10i WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1Oi_dataout; + wire_nl1O100ll_dataout <= nl1O1l10l WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1Ol_dataout; + wire_nl1O100lO_dataout <= nl1O1l10O WHEN niOi1O0iO = '1' ELSE wire_nl1O1i1OO_dataout; + wire_nl1O100Oi_dataout <= nl1O1l1ii WHEN niOi1O0iO = '1' ELSE wire_nl1O1i01i_dataout; + wire_nl1O100Ol_dataout <= nl1O1l1il WHEN niOi1O0iO = '1' ELSE wire_nl1O1i01l_dataout; + wire_nl1O100OO_dataout <= nl1O1l1iO WHEN niOi1O0iO = '1' ELSE wire_nl1O1i01O_dataout; + wire_nl1O1010i_dataout <= nl1O1ilOi WHEN niOi1O0iO = '1' ELSE wire_nl1O10Oii_dataout; + wire_nl1O1010l_dataout <= nl1O1ilOl WHEN niOi1O0iO = '1' ELSE wire_nl1O10Oil_dataout; + wire_nl1O1010O_dataout <= nl1O1ilOO WHEN niOi1O0iO = '1' ELSE wire_nl1O10OiO_dataout; + wire_nl1O1011i_dataout <= nl1O1illi WHEN niOi1O0iO = '1' ELSE wire_nl1O10O0i_dataout; + wire_nl1O1011l_dataout <= nl1O1illl WHEN niOi1O0iO = '1' ELSE wire_nl1O10O0l_dataout; + wire_nl1O1011O_dataout <= nl1O1illO WHEN niOi1O0iO = '1' ELSE wire_nl1O10O0O_dataout; + wire_nl1O101ii_dataout <= nl1O1iO1i WHEN niOi1O0iO = '1' ELSE wire_nl1O10Oli_dataout; + wire_nl1O101il_dataout <= nl1O1iO1l WHEN niOi1O0iO = '1' ELSE wire_nl1O10Oll_dataout; + wire_nl1O101iO_dataout <= nl1O1iO1O WHEN niOi1O0iO = '1' ELSE wire_nl1O10OlO_dataout; + wire_nl1O101li_dataout <= nl1O1iO0i WHEN niOi1O0iO = '1' ELSE wire_nl1O10OOi_dataout; + wire_nl1O101ll_dataout <= nl1O1iO0l WHEN niOi1O0iO = '1' ELSE wire_nl1O10OOl_dataout; + wire_nl1O101lO_dataout <= nl1O1iO0O WHEN niOi1O0iO = '1' ELSE wire_nl1O10OOO_dataout; + wire_nl1O101Oi_dataout <= nl1O1iOii WHEN niOi1O0iO = '1' ELSE wire_nl1O1i11i_dataout; + wire_nl1O101Ol_dataout <= nl1O1iOil WHEN niOi1O0iO = '1' ELSE wire_nl1O1i11l_dataout; + wire_nl1O101OO_dataout <= nl1O1iOiO WHEN niOi1O0iO = '1' ELSE wire_nl1O1i11O_dataout; + wire_nl1O10i_dataout <= n1OiO0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1O10i0i_dataout <= nl1O1l1Oi WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0ii_dataout; + wire_nl1O10i0l_dataout <= nl1O1l1Ol WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0il_dataout; + wire_nl1O10i0O_dataout <= nl1O1l1OO WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0iO_dataout; + wire_nl1O10i1i_dataout <= nl1O1l1li WHEN niOi1O0iO = '1' ELSE wire_nl1O1i00i_dataout; + wire_nl1O10i1l_dataout <= nl1O1l1ll WHEN niOi1O0iO = '1' ELSE wire_nl1O1i00l_dataout; + wire_nl1O10i1O_dataout <= nl1O1l1lO WHEN niOi1O0iO = '1' ELSE wire_nl1O1i00O_dataout; + wire_nl1O10iii_dataout <= nl1O1l01i WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0li_dataout; + wire_nl1O10iil_dataout <= nl1O1l01l WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0ll_dataout; + wire_nl1O10iiO_dataout <= nl1O1l01O WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0lO_dataout; + wire_nl1O10ili_dataout <= nl1O1l00i WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0Oi_dataout; + wire_nl1O10ill_dataout <= nl1O1l00l WHEN niOi1O0iO = '1' ELSE wire_nl1O1i0Ol_dataout; + wire_nl1O10ilO_dataout <= nl1O00l0i AND niOi1O0OO; + wire_nl1O10iOi_dataout <= nl1O00l0l AND niOi1O0OO; + wire_nl1O10iOl_dataout <= nl1O00l0O AND niOi1O0OO; + wire_nl1O10iOO_dataout <= nl1O00lii AND niOi1O0OO; + wire_nl1O10l_dataout <= n1OiOii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10iO; + wire_nl1O10l0i_dataout <= nl1O00lll AND niOi1O0OO; + wire_nl1O10l0l_dataout <= nl1O00llO AND niOi1O0OO; + wire_nl1O10l0O_dataout <= nl1O00lOi AND niOi1O0OO; + wire_nl1O10l1i_dataout <= nl1O00lil AND niOi1O0OO; + wire_nl1O10l1l_dataout <= nl1O00liO AND niOi1O0OO; + wire_nl1O10l1O_dataout <= nl1O00lli AND niOi1O0OO; + wire_nl1O10lii_dataout <= nl1O00lOl AND niOi1O0OO; + wire_nl1O10lil_dataout <= nl1O00lOO AND niOi1O0OO; + wire_nl1O10liO_dataout <= nl1O00O1i AND niOi1O0OO; + wire_nl1O10ll_dataout <= wire_nl1O10OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O10lli_dataout <= nl1O00O1l AND niOi1O0OO; + wire_nl1O10lll_dataout <= nl1O00O1O AND niOi1O0OO; + wire_nl1O10llO_dataout <= nl1O00O0i AND niOi1O0OO; + wire_nl1O10lO_dataout <= wire_nl1O1i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O10lOi_dataout <= nl1O00O0l AND niOi1O0OO; + wire_nl1O10lOl_dataout <= nl1O00O0O AND niOi1O0OO; + wire_nl1O10lOO_dataout <= nl1O00Oii AND niOi1O0OO; + wire_nl1O10O_dataout <= n1OiOil WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10li; + wire_nl1O10O0i_dataout <= nl1O00Oll AND niOi1O0OO; + wire_nl1O10O0l_dataout <= nl1O00OlO AND niOi1O0OO; + wire_nl1O10O0O_dataout <= nl1O00OOi AND niOi1O0OO; + wire_nl1O10O1i_dataout <= nl1O00Oil AND niOi1O0OO; + wire_nl1O10O1l_dataout <= nl1O00OiO AND niOi1O0OO; + wire_nl1O10O1O_dataout <= nl1O00Oli AND niOi1O0OO; + wire_nl1O10Oi_dataout <= wire_nl1O1i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O10Oii_dataout <= nl1O00OOl AND niOi1O0OO; + wire_nl1O10Oil_dataout <= nl1O00OOO AND niOi1O0OO; + wire_nl1O10OiO_dataout <= nl1O0i11i AND niOi1O0OO; + wire_nl1O10Ol_dataout <= wire_nl1O1i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O10Oli_dataout <= nl1O0i11l AND niOi1O0OO; + wire_nl1O10Oll_dataout <= nl1O0i11O AND niOi1O0OO; + wire_nl1O10OlO_dataout <= nl1O0i10i AND niOi1O0OO; + wire_nl1O10OO_dataout <= nl1O1l1i WHEN niOO1liOO = '1' ELSE nl1O1i0l; + wire_nl1O10OOi_dataout <= nl1O0i10l AND niOi1O0OO; + wire_nl1O10OOl_dataout <= nl1O0i10O AND niOi1O0OO; + wire_nl1O10OOO_dataout <= nl1O0i1ii AND niOi1O0OO; + wire_nl1O1100i_dataout <= nl1O1ll0l WHEN niOi1O0il = '1' ELSE wire_nl1O101ii_dataout; + wire_nl1O1100l_dataout <= nl1O1ll0O WHEN niOi1O0il = '1' ELSE wire_nl1O101il_dataout; + wire_nl1O1100O_dataout <= nl1O1llii WHEN niOi1O0il = '1' ELSE wire_nl1O101iO_dataout; + wire_nl1O1101i_dataout <= nl1O1ll1l WHEN niOi1O0il = '1' ELSE wire_nl1O1010i_dataout; + wire_nl1O1101l_dataout <= nl1O1ll1O WHEN niOi1O0il = '1' ELSE wire_nl1O1010l_dataout; + wire_nl1O1101O_dataout <= nl1O1ll0i WHEN niOi1O0il = '1' ELSE wire_nl1O1010O_dataout; + wire_nl1O110ii_dataout <= nl1O1llil WHEN niOi1O0il = '1' ELSE wire_nl1O101li_dataout; + wire_nl1O110il_dataout <= nl1O1lliO WHEN niOi1O0il = '1' ELSE wire_nl1O101ll_dataout; + wire_nl1O110iO_dataout <= nl1O1llli WHEN niOi1O0il = '1' ELSE wire_nl1O101lO_dataout; + wire_nl1O110li_dataout <= nl1O1llll WHEN niOi1O0il = '1' ELSE wire_nl1O101Oi_dataout; + wire_nl1O110ll_dataout <= nl1O1lllO WHEN niOi1O0il = '1' ELSE wire_nl1O101Ol_dataout; + wire_nl1O110lO_dataout <= nl1O1llOi WHEN niOi1O0il = '1' ELSE wire_nl1O101OO_dataout; + wire_nl1O110Oi_dataout <= nl1O1llOl WHEN niOi1O0il = '1' ELSE wire_nl1O1001i_dataout; + wire_nl1O110Ol_dataout <= nl1O1llOO WHEN niOi1O0il = '1' ELSE wire_nl1O1001l_dataout; + wire_nl1O110OO_dataout <= nl1O1lO1i WHEN niOi1O0il = '1' ELSE wire_nl1O1001O_dataout; + wire_nl1O1110i_dataout <= nl1O1li0l WHEN niOi1O0il = '1' ELSE wire_nl1O11Oii_dataout; + wire_nl1O1110l_dataout <= nl1O1li0O WHEN niOi1O0il = '1' ELSE wire_nl1O11Oil_dataout; + wire_nl1O1110O_dataout <= nl1O1liii WHEN niOi1O0il = '1' ELSE wire_nl1O11OiO_dataout; + wire_nl1O1111i_dataout <= nl1O1li1l WHEN niOi1O0il = '1' ELSE wire_nl1O11O0i_dataout; + wire_nl1O1111l_dataout <= nl1O1li1O WHEN niOi1O0il = '1' ELSE wire_nl1O11O0l_dataout; + wire_nl1O1111O_dataout <= nl1O1li0i WHEN niOi1O0il = '1' ELSE wire_nl1O11O0O_dataout; + wire_nl1O111i_dataout <= nlliiil1O WHEN niOO1liOi = '1' ELSE nl1lOO0l; + wire_nl1O111ii_dataout <= nl1O1liil WHEN niOi1O0il = '1' ELSE wire_nl1O11Oli_dataout; + wire_nl1O111il_dataout <= nl1O1liiO WHEN niOi1O0il = '1' ELSE wire_nl1O11Oll_dataout; + wire_nl1O111iO_dataout <= nl1O1lili WHEN niOi1O0il = '1' ELSE wire_nl1O11OlO_dataout; + wire_nl1O111l_dataout <= nlliiil0i WHEN niOO1liOi = '1' ELSE nl1lOO0O; + wire_nl1O111li_dataout <= nl1O1lill WHEN niOi1O0il = '1' ELSE wire_nl1O11OOi_dataout; + wire_nl1O111ll_dataout <= nl1O1lilO WHEN niOi1O0il = '1' ELSE wire_nl1O11OOl_dataout; + wire_nl1O111lO_dataout <= nl1O1liOi WHEN niOi1O0il = '1' ELSE wire_nl1O11OOO_dataout; + wire_nl1O111O_dataout <= nlliiilli WHEN niOO1liOi = '1' ELSE nl1lOOii; + wire_nl1O111Oi_dataout <= nl1O1liOl WHEN niOi1O0il = '1' ELSE wire_nl1O1011i_dataout; + wire_nl1O111Ol_dataout <= nl1O1liOO WHEN niOi1O0il = '1' ELSE wire_nl1O1011l_dataout; + wire_nl1O111OO_dataout <= nl1O1ll1i WHEN niOi1O0il = '1' ELSE wire_nl1O1011O_dataout; + wire_nl1O11i_dataout <= n1OiO1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1O11i0i_dataout <= nl1O1lO0l WHEN niOi1O0il = '1' ELSE wire_nl1O100ii_dataout; + wire_nl1O11i0l_dataout <= nl1O1lO0O WHEN niOi1O0il = '1' ELSE wire_nl1O100il_dataout; + wire_nl1O11i0O_dataout <= nl1O1lOii WHEN niOi1O0il = '1' ELSE wire_nl1O100iO_dataout; + wire_nl1O11i1i_dataout <= nl1O1lO1l WHEN niOi1O0il = '1' ELSE wire_nl1O1000i_dataout; + wire_nl1O11i1l_dataout <= nl1O1lO1O WHEN niOi1O0il = '1' ELSE wire_nl1O1000l_dataout; + wire_nl1O11i1O_dataout <= nl1O1lO0i WHEN niOi1O0il = '1' ELSE wire_nl1O1000O_dataout; + wire_nl1O11iii_dataout <= nl1O1lOil WHEN niOi1O0il = '1' ELSE wire_nl1O100li_dataout; + wire_nl1O11iil_dataout <= nl1O1lOiO WHEN niOi1O0il = '1' ELSE wire_nl1O100ll_dataout; + wire_nl1O11iiO_dataout <= nl1O1lOli WHEN niOi1O0il = '1' ELSE wire_nl1O100lO_dataout; + wire_nl1O11il_dataout <= wire_nl1O11lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O11ili_dataout <= nl1O1lOll WHEN niOi1O0il = '1' ELSE wire_nl1O100Oi_dataout; + wire_nl1O11ill_dataout <= nl1O1lOlO WHEN niOi1O0il = '1' ELSE wire_nl1O100Ol_dataout; + wire_nl1O11ilO_dataout <= nl1O1lOOi WHEN niOi1O0il = '1' ELSE wire_nl1O100OO_dataout; + wire_nl1O11iO_dataout <= wire_nl1O11Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O11iOi_dataout <= nl1O1lOOl WHEN niOi1O0il = '1' ELSE wire_nl1O10i1i_dataout; + wire_nl1O11iOl_dataout <= nl1O1lOOO WHEN niOi1O0il = '1' ELSE wire_nl1O10i1l_dataout; + wire_nl1O11iOO_dataout <= nl1O1O11i WHEN niOi1O0il = '1' ELSE wire_nl1O10i1O_dataout; + wire_nl1O11l_dataout <= n1OiO0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1O11l0i_dataout <= nl1O1O10l WHEN niOi1O0il = '1' ELSE wire_nl1O10iii_dataout; + wire_nl1O11l0l_dataout <= nl1O1O10O WHEN niOi1O0il = '1' ELSE wire_nl1O10iil_dataout; + wire_nl1O11l0O_dataout <= nl1O1O1ii WHEN niOi1O0il = '1' ELSE wire_nl1O10iiO_dataout; + wire_nl1O11l1i_dataout <= nl1O1O11l WHEN niOi1O0il = '1' ELSE wire_nl1O10i0i_dataout; + wire_nl1O11l1l_dataout <= nl1O1O11O WHEN niOi1O0il = '1' ELSE wire_nl1O10i0l_dataout; + wire_nl1O11l1O_dataout <= nl1O1O10i WHEN niOi1O0il = '1' ELSE wire_nl1O10i0O_dataout; + wire_nl1O11li_dataout <= wire_nl1O11ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1O11lii_dataout <= nl1O1O1il WHEN niOi1O0il = '1' ELSE wire_nl1O10ili_dataout; + wire_nl1O11lil_dataout <= nl1O1O1iO WHEN niOi1O0il = '1' ELSE wire_nl1O10ill_dataout; + wire_nl1O11liO_dataout <= nl1O1ii1O WHEN niOi1O0iO = '1' ELSE wire_nl1O10ilO_dataout; + wire_nl1O11ll_dataout <= niOO1liOl AND NOT(niOO0li0O); + wire_nl1O11lli_dataout <= nl1O1ii0i WHEN niOi1O0iO = '1' ELSE wire_nl1O10iOi_dataout; + wire_nl1O11lll_dataout <= nl1O1ii0l WHEN niOi1O0iO = '1' ELSE wire_nl1O10iOl_dataout; + wire_nl1O11llO_dataout <= nl1O1ii0O WHEN niOi1O0iO = '1' ELSE wire_nl1O10iOO_dataout; + wire_nl1O11lO_dataout <= wire_nl1O11Ol_dataout AND NOT(niOO0li0O); + wire_nl1O11lOi_dataout <= nl1O1iiii WHEN niOi1O0iO = '1' ELSE wire_nl1O10l1i_dataout; + wire_nl1O11lOl_dataout <= nl1O1iiil WHEN niOi1O0iO = '1' ELSE wire_nl1O10l1l_dataout; + wire_nl1O11lOO_dataout <= nl1O1iiiO WHEN niOi1O0iO = '1' ELSE wire_nl1O10l1O_dataout; + wire_nl1O11O_dataout <= n1OiO0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1O11O0i_dataout <= nl1O1iiOi WHEN niOi1O0iO = '1' ELSE wire_nl1O10lii_dataout; + wire_nl1O11O0l_dataout <= nl1O1iiOl WHEN niOi1O0iO = '1' ELSE wire_nl1O10lil_dataout; + wire_nl1O11O0O_dataout <= nl1O1iiOO WHEN niOi1O0iO = '1' ELSE wire_nl1O10liO_dataout; + wire_nl1O11O1i_dataout <= nl1O1iili WHEN niOi1O0iO = '1' ELSE wire_nl1O10l0i_dataout; + wire_nl1O11O1l_dataout <= nl1O1iill WHEN niOi1O0iO = '1' ELSE wire_nl1O10l0l_dataout; + wire_nl1O11O1O_dataout <= nl1O1iilO WHEN niOi1O0iO = '1' ELSE wire_nl1O10l0O_dataout; + wire_nl1O11Oi_dataout <= wire_nl1O11OO_dataout AND NOT(niOO0li0O); + wire_nl1O11Oii_dataout <= nl1O1il1i WHEN niOi1O0iO = '1' ELSE wire_nl1O10lli_dataout; + wire_nl1O11Oil_dataout <= nl1O1il1l WHEN niOi1O0iO = '1' ELSE wire_nl1O10lll_dataout; + wire_nl1O11OiO_dataout <= nl1O1il1O WHEN niOi1O0iO = '1' ELSE wire_nl1O10llO_dataout; + wire_nl1O11Ol_dataout <= wire_nl1O101i_o(0) AND NOT(niOO1liOl); + wire_nl1O11Oli_dataout <= nl1O1il0i WHEN niOi1O0iO = '1' ELSE wire_nl1O10lOi_dataout; + wire_nl1O11Oll_dataout <= nl1O1il0l WHEN niOi1O0iO = '1' ELSE wire_nl1O10lOl_dataout; + wire_nl1O11OlO_dataout <= nl1O1il0O WHEN niOi1O0iO = '1' ELSE wire_nl1O10lOO_dataout; + wire_nl1O11OO_dataout <= wire_nl1O101i_o(1) AND NOT(niOO1liOl); + wire_nl1O11OOi_dataout <= nl1O1ilii WHEN niOi1O0iO = '1' ELSE wire_nl1O10O1i_dataout; + wire_nl1O11OOl_dataout <= nl1O1ilil WHEN niOi1O0iO = '1' ELSE wire_nl1O10O1l_dataout; + wire_nl1O11OOO_dataout <= nl1O1iliO WHEN niOi1O0iO = '1' ELSE wire_nl1O10O1O_dataout; + wire_nl1O1i00i_dataout <= nl1O0i0ll AND niOi1O0OO; + wire_nl1O1i00l_dataout <= nl1O0i0lO AND niOi1O0OO; + wire_nl1O1i00O_dataout <= nl1O0i0Oi AND niOi1O0OO; + wire_nl1O1i01i_dataout <= nl1O0i0il AND niOi1O0OO; + wire_nl1O1i01l_dataout <= nl1O0i0iO AND niOi1O0OO; + wire_nl1O1i01O_dataout <= nl1O0i0li AND niOi1O0OO; + wire_nl1O1i0ii_dataout <= nl1O0i0Ol AND niOi1O0OO; + wire_nl1O1i0il_dataout <= nl1O0i0OO AND niOi1O0OO; + wire_nl1O1i0iO_dataout <= nl1O0ii1i AND niOi1O0OO; + wire_nl1O1i0li_dataout <= nl1O0ii1l AND niOi1O0OO; + wire_nl1O1i0ll_dataout <= nl1O0ii1O AND niOi1O0OO; + wire_nl1O1i0lO_dataout <= nl1O0ii0i AND niOi1O0OO; + wire_nl1O1i0Oi_dataout <= nl1O0ii0l AND niOi1O0OO; + wire_nl1O1i0Ol_dataout <= nl1O0ii0O AND niOi1O0OO; + wire_nl1O1i10i_dataout <= nl1O0i1ll AND niOi1O0OO; + wire_nl1O1i10l_dataout <= nl1O0i1lO AND niOi1O0OO; + wire_nl1O1i10O_dataout <= nl1O0i1Oi AND niOi1O0OO; + wire_nl1O1i11i_dataout <= nl1O0i1il AND niOi1O0OO; + wire_nl1O1i11l_dataout <= nl1O0i1iO AND niOi1O0OO; + wire_nl1O1i11O_dataout <= nl1O0i1li AND niOi1O0OO; + wire_nl1O1i1i_dataout <= nl1O1l1l WHEN niOO1liOO = '1' ELSE nl1O10ii; + wire_nl1O1i1ii_dataout <= nl1O0i1Ol AND niOi1O0OO; + wire_nl1O1i1il_dataout <= nl1O0i1OO AND niOi1O0OO; + wire_nl1O1i1iO_dataout <= nl1O0i01i AND niOi1O0OO; + wire_nl1O1i1l_dataout <= nl1O1l1O WHEN niOO1liOO = '1' ELSE nl1O10il; + wire_nl1O1i1li_dataout <= nl1O0i01l AND niOi1O0OO; + wire_nl1O1i1ll_dataout <= nl1O0i01O AND niOi1O0OO; + wire_nl1O1i1lO_dataout <= nl1O0i00i AND niOi1O0OO; + wire_nl1O1i1O_dataout <= nl1O1l0i WHEN niOO1liOO = '1' ELSE nl1O10iO; + wire_nl1O1i1Oi_dataout <= nl1O0i00l AND niOi1O0OO; + wire_nl1O1i1Ol_dataout <= nl1O0i00O AND niOi1O0OO; + wire_nl1O1i1OO_dataout <= nl1O0i0ii AND niOi1O0OO; + wire_nl1O1ii_dataout <= n1OiOiO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10ll; + wire_nl1O1iii_dataout <= nl1O1ili AND NOT(wire_niO01l0O_dataout); + wire_nl1O1iiO_dataout <= nl1O10li AND NOT(wire_niO01l0O_dataout); + wire_nl1O1il_dataout <= n1OiOli WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10lO; + wire_nl1O1ill_dataout <= nl1O1iOi AND NOT(wire_niO01O0O_dataout); + wire_nl1O1iO_dataout <= n1OiOll WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10Oi; + wire_nl1O1iOl_dataout <= nl1O1ilO AND NOT(wire_niO01O0O_dataout); + wire_nl1O1iOO_dataout <= nl1O1iil AND NOT(wire_niO01O0O_dataout); + wire_nl1O1l0l_dataout <= wire_nl1O1lli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O1l0O_dataout <= wire_nl1O1llO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O1li_dataout <= n1OiOlO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10Ol; + wire_nl1O1lii_dataout <= wire_nl1O1lOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O1lil_dataout <= wire_nl1O1lOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O1liO_dataout <= wire_nl1O1lOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1O1ll_dataout <= n1OiOOi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O10OO; + wire_nl1O1lli_dataout <= wire_niOOO0O_w_lg_nl1O1iOi7772w(0) WHEN (wire_w_lg_niOO1ll1i7768w(0) AND (NOT ((((NOT (dl_tx_typ_pm(0) XOR nl1O1l1i)) AND (NOT (dl_tx_typ_pm(1) XOR nl1O1l1l))) AND (NOT (dl_tx_typ_pm(2) XOR nl1O1l1O))) AND (NOT (dl_tx_req_pm XOR nl1O1l0i))))) = '1' ELSE nl1O1iOi; + wire_nl1O1llO_dataout <= dl_tx_typ_pm(0) WHEN wire_w_lg_niOO1ll1i7768w(0) = '1' ELSE nl1O1l1i; + wire_nl1O1lO_dataout <= n1OiOOl WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1i1i; + wire_nl1O1lOi_dataout <= dl_tx_typ_pm(1) WHEN wire_w_lg_niOO1ll1i7768w(0) = '1' ELSE nl1O1l1l; + wire_nl1O1lOl_dataout <= dl_tx_typ_pm(2) WHEN wire_w_lg_niOO1ll1i7768w(0) = '1' ELSE nl1O1l1O; + wire_nl1O1lOO_dataout <= dl_tx_req_pm WHEN wire_w_lg_niOO1ll1i7768w(0) = '1' ELSE nl1O1l0i; + wire_nl1O1O1O_dataout <= (nl1O1OlO XOR nl1O1Oli) AND NOT(wire_niO01l0O_dataout); + wire_nl1O1Oi_dataout <= n1OiOOO WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1i1l; + wire_nl1O1Oii_dataout <= nl1O1Oli AND NOT(wire_niO01O0O_dataout); + wire_nl1O1OiO_dataout <= nl1O1O1l AND NOT(wire_niO01O0O_dataout); + wire_nl1O1Ol_dataout <= n1Ol11i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1i1O; + wire_nl1O1Oll_dataout <= nl1O1OOi AND NOT(wire_niO01l0O_dataout); + wire_nl1O1OO_dataout <= n1Ol11l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1i0i; + wire_nl1O1OOl_dataout <= nl1O1OlO AND NOT(wire_niO01l0O_dataout); + wire_nl1O1OOO_dataout <= nl1O1Oil AND NOT(wire_niO01l0O_dataout); + wire_nl1Oi000i_dataout <= wire_nl1Oil1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi000l_dataout <= wire_nl1Oil1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi000O_dataout <= wire_nl1Oil1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi001i_dataout <= wire_nl1Oil1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi001l_dataout <= wire_nl1Oil1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi001O_dataout <= wire_nl1Oil1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00ii_dataout <= wire_nl1Oil1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00il_dataout <= wire_nl1Oil01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00iO_dataout <= wire_nl1Oil01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00l_dataout <= wire_nl1Oi0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1Oi00li_dataout <= wire_nl1Oil01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00ll_dataout <= wire_nl1Oil00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00lO_dataout <= wire_nl1Oil00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00O_dataout <= wire_nl1Oi0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1Oi00Oi_dataout <= wire_nl1Oil00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00Ol_dataout <= wire_nl1Oil0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi00OO_dataout <= wire_nl1Oil0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi010i_dataout <= wire_nl1OiiOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi010l_dataout <= wire_nl1OiiOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi010O_dataout <= wire_nl1OiiOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi011i_dataout <= wire_nl1OiiOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi011l_dataout <= wire_nl1OiiOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi011O_dataout <= wire_nl1OiiOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01ii_dataout <= wire_nl1OiiOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01il_dataout <= wire_nl1Oil11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01iO_dataout <= wire_nl1Oil11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01l_dataout <= nl1Oi1OO AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01li_dataout <= wire_nl1Oil11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01ll_dataout <= wire_nl1Oil10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01lO_dataout <= wire_nl1Oil10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01O_dataout <= nl1Oi1ll AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01Oi_dataout <= wire_nl1Oil10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01Ol_dataout <= wire_nl1Oil1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi01OO_dataout <= wire_nl1Oil1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0i_dataout <= n1Ol00O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oi0i0i_dataout <= wire_nl1Oil0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0i0l_dataout <= wire_nl1Oil0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0i0O_dataout <= wire_nl1Oil0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0i1i_dataout <= wire_nl1Oil0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0i1l_dataout <= wire_nl1Oil0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0i1O_dataout <= wire_nl1Oil0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0ii_dataout <= wire_niOOO0O_w_lg_nl1Oi01i7730w(0) WHEN (wire_w_lg_niOO1ll0O7731w(0) AND wire_w_lg_w_dl_req_phypm_range7729w7732w(0)) = '1' ELSE nl1Oi01i; + wire_nl1Oi0iii_dataout <= wire_nl1Oil0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0iil_dataout <= wire_nl1Oili1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0iiO_dataout <= wire_nl1Oili1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0ili_dataout <= wire_nl1Oili1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0ill_dataout <= wire_nl1Oili0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0ilO_dataout <= wire_nl1Oili0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0iOi_dataout <= wire_nl1Oili0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0iOl_dataout <= wire_nl1Oiliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0iOO_dataout <= wire_nl1Oiliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0l_dataout <= n1Ol0ii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oi0l0i_dataout <= wire_nl1OililO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0l0l_dataout <= wire_nl1OiliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0l0O_dataout <= wire_nl1OiliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0l1i_dataout <= wire_nl1OiliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0l1l_dataout <= wire_nl1Oilili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0l1O_dataout <= wire_nl1Oilill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0li_dataout <= nl1Oi00i WHEN niOO1ll0O = '1' ELSE dl_req_phypm(3); + wire_nl1Oi0lii_dataout <= wire_nl1OiliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0lil_dataout <= wire_nl1Oill1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0liO_dataout <= wire_nl1Oill1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0lli_dataout <= wire_nl1Oill1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0lll_dataout <= wire_nl1Oill0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi0llO_dataout <= wire_nl1Oi0lOl_dataout AND NOT(niOi1O0ll); + wire_nl1Oi0lOi_dataout <= wire_w_lg_niOi1O0li55222w(0) AND NOT(niOi1O0ll); + wire_nl1Oi0lOl_dataout <= (NOT (wire_nl011Ol0l_dataout AND (nl1OillOi AND niOi1O0lO))) OR niOi1O0li; + wire_nl1Oi0O_dataout <= n1Ol0il AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oi0O0l_dataout <= wire_nl1Oi0Oii_dataout AND NOT(niOi1O0ll); + wire_nl1Oi0O0O_dataout <= wire_w_lg_niOi1O0Oi55215w(0) AND NOT(niOi1O0ll); + wire_nl1Oi0Oi_dataout <= (nl1Oiiii XOR nl1Oii0l) AND NOT(wire_niO01l0O_dataout); + wire_nl1Oi0Oii_dataout <= (NOT (wire_nl011Olil_dataout AND (niOi1Olli AND (niOi1Olll AND niOi1O0lO)))) OR niOi1O0Oi; + wire_nl1Oi0OOi_dataout <= wire_nl1lO1l1l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01lOO; + wire_nl1Oi0OOl_dataout <= wire_nl1lO1l1O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01O1i; + wire_nl1Oi0OOO_dataout <= wire_nl1lO1l0i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01O1l; + wire_nl1Oi100i_dataout <= wire_nl1Oii1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi100l_dataout <= wire_nl1Oii1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi100O_dataout <= wire_nl1Oii1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi101i_dataout <= wire_nl1Oii1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi101l_dataout <= wire_nl1Oii1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi101O_dataout <= wire_nl1Oii1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10ii_dataout <= wire_nl1Oii1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10il_dataout <= wire_nl1Oii01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10iO_dataout <= wire_nl1Oii01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10l_dataout <= wire_nl1Oi10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10li_dataout <= wire_nl1Oii01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10ll_dataout <= wire_nl1Oii00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10lO_dataout <= wire_nl1Oii00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10O_dataout <= wire_nl1000i_w_lg_nl1Oi1il7734w(0) WHEN (nl1Oi1OO XOR nl1Oi1Oi) = '1' ELSE nl1Oi1il; + wire_nl1Oi10Oi_dataout <= wire_nl1Oii00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10Ol_dataout <= wire_nl1Oii0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi10OO_dataout <= wire_nl1Oii0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi110i_dataout <= nl00lll0O AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi110l_dataout <= wire_nl1Oi0OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi110O_dataout <= wire_nl1Oi0OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi111i_dataout <= nl00lll1O AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi111l_dataout <= nl00lll0i AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi111O_dataout <= nl00lll0l AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11ii_dataout <= wire_nl1Oi0OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11il_dataout <= wire_nl1Oii11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11iO_dataout <= wire_nl1Oii11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11l_dataout <= nl1O0Oll WHEN niOO1ll0l = '1' ELSE dl_req_phypm(2); + wire_nl1Oi11li_dataout <= wire_nl1Oii11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11ll_dataout <= wire_nl1Oii10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11lO_dataout <= wire_nl1Oii10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11Oi_dataout <= wire_nl1Oii10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11Ol_dataout <= wire_nl1Oii1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi11OO_dataout <= wire_nl1Oii1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1i_dataout <= n1Ol01O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nl0O1l0l; + wire_nl1Oi1i0i_dataout <= wire_nl1Oii0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1i0l_dataout <= wire_nl1Oii0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1i0O_dataout <= wire_nl1Oii0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1i1i_dataout <= wire_nl1Oii0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1i1l_dataout <= wire_nl1Oii0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1i1O_dataout <= wire_nl1Oii0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1iii_dataout <= wire_nl1Oii0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1iil_dataout <= wire_nl1Oiii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1iiO_dataout <= wire_nl1Oiii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1ili_dataout <= wire_nl1Oiii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1ill_dataout <= wire_nl1Oiii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1ilO_dataout <= wire_nl1Oiii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1iOi_dataout <= wire_nl1Oiii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1iOl_dataout <= wire_nl1Oiiiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1iOO_dataout <= wire_nl1Oiiiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1l_dataout <= n1Ol00i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oi1l0i_dataout <= wire_nl1OiiilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1l0l_dataout <= wire_nl1OiiiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1l0O_dataout <= wire_nl1OiiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1l1i_dataout <= wire_nl1OiiiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1l1l_dataout <= wire_nl1Oiiili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1l1O_dataout <= wire_nl1Oiiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1li_dataout <= nl1Oi1Oi AND NOT(wire_niO01l0O_dataout); + wire_nl1Oi1lii_dataout <= wire_nl1OiiiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1lil_dataout <= wire_nl1Oiil1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1liO_dataout <= wire_nl1Oiil1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1lli_dataout <= wire_nl1Oiil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1lll_dataout <= wire_nl1Oiil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1llO_dataout <= wire_nl1Oiil0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1lO_dataout <= nl1Oi10i AND NOT(wire_niO01l0O_dataout); + wire_nl1Oi1lOi_dataout <= wire_nl1Oiil0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1lOl_dataout <= wire_nl1Oiilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1lOO_dataout <= wire_nl1Oiilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1O_dataout <= n1Ol00l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oi1O0i_dataout <= wire_nl1OiillO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1O0l_dataout <= wire_nl1OiilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1O0O_dataout <= wire_nl1OiilOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1O1i_dataout <= wire_nl1OiiliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1O1l_dataout <= wire_nl1Oiilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1O1O_dataout <= wire_nl1Oiilll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1Oii_dataout <= wire_nl1OiilOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1Oil_dataout <= wire_nl1OiiO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1OiO_dataout <= wire_nl1OiiO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1Ol_dataout <= nl1Oi01i AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1Oli_dataout <= wire_nl1OiiO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1Oll_dataout <= wire_nl1OiiO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1OlO_dataout <= wire_nl1OiiO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1OOi_dataout <= wire_nl1OiiO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1OOl_dataout <= wire_nl1OiiOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oi1OOO_dataout <= wire_nl1OiiOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Oii00i_dataout <= wire_nl1lO1Oil_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0010O; + wire_nl1Oii00l_dataout <= wire_nl1lO1OiO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001ii; + wire_nl1Oii00O_dataout <= wire_nl1lO1Oli_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001il; + wire_nl1Oii01i_dataout <= wire_nl1lO1O0l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0011O; + wire_nl1Oii01l_dataout <= wire_nl1lO1O0O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0010i; + wire_nl1Oii01O_dataout <= wire_nl1lO1Oii_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0010l; + wire_nl1Oii0i_dataout <= nl1Oi0lO AND NOT(wire_niO01O0O_dataout); + wire_nl1Oii0ii_dataout <= wire_nl1lO1Oll_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001iO; + wire_nl1Oii0il_dataout <= wire_nl1lO1OlO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001li; + wire_nl1Oii0iO_dataout <= wire_nl1lO1OOi_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001ll; + wire_nl1Oii0li_dataout <= wire_nl1lO1OOl_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001lO; + wire_nl1Oii0ll_dataout <= wire_nl1lO1OOO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001Oi; + wire_nl1Oii0lO_dataout <= wire_nl1lO011i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001Ol; + wire_nl1Oii0O_dataout <= nl1Oiiil AND NOT(wire_niO01l0O_dataout); + wire_nl1Oii0Oi_dataout <= wire_nl1lO011l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O001OO; + wire_nl1Oii0Ol_dataout <= wire_nl1lO011O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0001i; + wire_nl1Oii0OO_dataout <= wire_nl1lO010i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0001l; + wire_nl1Oii10i_dataout <= wire_nl1lO1lil_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01O0O; + wire_nl1Oii10l_dataout <= wire_nl1lO1liO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01Oii; + wire_nl1Oii10O_dataout <= wire_nl1lO1lli_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01Oil; + wire_nl1Oii11i_dataout <= wire_nl1lO1l0l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01O1O; + wire_nl1Oii11l_dataout <= wire_nl1lO1l0O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01O0i; + wire_nl1Oii11O_dataout <= wire_nl1lO1lii_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01O0l; + wire_nl1Oii1ii_dataout <= wire_nl1lO1lll_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01OiO; + wire_nl1Oii1il_dataout <= wire_nl1lO1llO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01Oli; + wire_nl1Oii1iO_dataout <= wire_nl1lO1lOi_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01Oll; + wire_nl1Oii1l_dataout <= nl1Oii0l AND NOT(wire_niO01O0O_dataout); + wire_nl1Oii1li_dataout <= wire_nl1lO1lOl_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01OlO; + wire_nl1Oii1ll_dataout <= wire_nl1lO1lOO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01OOi; + wire_nl1Oii1lO_dataout <= wire_nl1lO1O1i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01OOl; + wire_nl1Oii1Oi_dataout <= wire_nl1lO1O1l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O01OOO; + wire_nl1Oii1Ol_dataout <= wire_nl1lO1O1O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0011i; + wire_nl1Oii1OO_dataout <= wire_nl1lO1O0i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0011l; + wire_nl1Oiii_dataout <= n1Ol0iO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oiii0i_dataout <= wire_nl1lO01il_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0000O; + wire_nl1Oiii0l_dataout <= wire_nl1lO01iO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000ii; + wire_nl1Oiii0O_dataout <= wire_nl1lO01li_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000il; + wire_nl1Oiii1i_dataout <= wire_nl1lO010l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0001O; + wire_nl1Oiii1l_dataout <= wire_nl1lO010O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0000i; + wire_nl1Oiii1O_dataout <= wire_nl1lO01ii_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O0000l; + wire_nl1Oiiiii_dataout <= wire_nl1lO01ll_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000iO; + wire_nl1Oiiiil_dataout <= wire_nl1lO01lO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000li; + wire_nl1OiiiiO_dataout <= wire_nl1lO01Oi_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000ll; + wire_nl1Oiiili_dataout <= wire_nl1lO01Ol_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000lO; + wire_nl1Oiiill_dataout <= wire_nl1lO01OO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000Oi; + wire_nl1OiiilO_dataout <= wire_nl1lO001i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000Ol; + wire_nl1OiiiO_dataout <= nl1Oiiii AND NOT(wire_niO01l0O_dataout); + wire_nl1OiiiOi_dataout <= wire_nl1lO001l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O000OO; + wire_nl1OiiiOl_dataout <= wire_nl1lO001O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00i1i; + wire_nl1OiiiOO_dataout <= wire_nl1lO000i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00i1l; + wire_nl1Oiil_dataout <= n1Ol0li AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oiil0i_dataout <= wire_nl1lO00il_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00i0O; + wire_nl1Oiil0l_dataout <= wire_nl1lO00iO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00iii; + wire_nl1Oiil0O_dataout <= wire_nl1lO00li_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00iil; + wire_nl1Oiil1i_dataout <= wire_nl1lO000l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00i1O; + wire_nl1Oiil1l_dataout <= wire_nl1lO000O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00i0i; + wire_nl1Oiil1O_dataout <= wire_nl1lO00ii_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00i0l; + wire_nl1Oiili_dataout <= nl1Oii1O AND NOT(wire_niO01l0O_dataout); + wire_nl1Oiilii_dataout <= wire_nl1lO00ll_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00iiO; + wire_nl1Oiilil_dataout <= wire_nl1lO00lO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00ili; + wire_nl1OiiliO_dataout <= wire_nl1lO00Oi_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00ill; + wire_nl1Oiilli_dataout <= wire_nl1lO00Ol_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00ilO; + wire_nl1Oiilll_dataout <= wire_nl1lO00OO_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00iOi; + wire_nl1OiillO_dataout <= wire_nl1lO0i1i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00iOl; + wire_nl1OiilO_dataout <= wire_nl1OiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiilOi_dataout <= wire_nl1lO0i1l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00iOO; + wire_nl1OiilOl_dataout <= wire_nl1lO0i1O_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00l1i; + wire_nl1OiilOO_dataout <= wire_nl1lO0i0i_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00l1l; + wire_nl1OiiO_dataout <= n1Ol0ll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OiiO0i_dataout <= wire_nl1lOO10l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00l0O; + wire_nl1OiiO0l_dataout <= wire_nl1lOO10O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00lii; + wire_nl1OiiO0O_dataout <= wire_nl1lOO1ii_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00lil; + wire_nl1OiiO1i_dataout <= wire_nl1lO0i0l_dataout WHEN wire_w_lg_niOi1O0Ol55208w(0) = '1' ELSE nl1O00l1O; + wire_nl1OiiO1l_dataout <= wire_nl1lOO11O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00l0i; + wire_nl1OiiO1O_dataout <= wire_nl1lOO10i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00l0l; + wire_nl1OiiOi_dataout <= wire_nl1Oil1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiiOii_dataout <= wire_nl1lOO1il_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00liO; + wire_nl1OiiOil_dataout <= wire_nl1lOO1iO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00lli; + wire_nl1OiiOiO_dataout <= wire_nl1lOO1li_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00lll; + wire_nl1OiiOl_dataout <= wire_nl1000i_w_lg_nl1Oiiil7722w(0) WHEN (wire_nlOii10OO_dataout AND (wire_w_lg_niOO1llii7723w(0) AND (wire_nlOii10OO_dataout XOR nl1Oiill))) = '1' ELSE nl1Oiiil; + wire_nl1OiiOli_dataout <= wire_nl1lOO1ll_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00llO; + wire_nl1OiiOll_dataout <= wire_nl1lOO1lO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00lOi; + wire_nl1OiiOlO_dataout <= wire_nl1lOO1Oi_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00lOl; + wire_nl1OiiOOi_dataout <= wire_nl1lOO1Ol_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00lOO; + wire_nl1OiiOOl_dataout <= wire_nl1lOO1OO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00O1i; + wire_nl1OiiOOO_dataout <= wire_nl1lOO01i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00O1l; + wire_nl1Oil00i_dataout <= wire_nl1lOOi0l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i10O; + wire_nl1Oil00l_dataout <= wire_nl1lOOi0O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1ii; + wire_nl1Oil00O_dataout <= wire_nl1lOOiii_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1il; + wire_nl1Oil01i_dataout <= wire_nl1lOOi1l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i11O; + wire_nl1Oil01l_dataout <= wire_nl1lOOi1O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i10i; + wire_nl1Oil01O_dataout <= wire_nl1lOOi0i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i10l; + wire_nl1Oil0ii_dataout <= wire_nl1lOOiil_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1iO; + wire_nl1Oil0il_dataout <= wire_nl1lOOiiO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1li; + wire_nl1Oil0iO_dataout <= wire_nl1lOOili_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1ll; + wire_nl1Oil0li_dataout <= wire_nl1lOOill_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1lO; + wire_nl1Oil0ll_dataout <= wire_nl1lOOilO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1Oi; + wire_nl1Oil0lO_dataout <= wire_nl1lOOiOi_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1Ol; + wire_nl1Oil0O_dataout <= (nl1OilOO XOR nl1OilOi) AND NOT(wire_niO01l0O_dataout); + wire_nl1Oil0Oi_dataout <= wire_nl1lOOiOl_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i1OO; + wire_nl1Oil0Ol_dataout <= wire_nl1lOOiOO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i01i; + wire_nl1Oil0OO_dataout <= wire_nl1lOOl1i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i01l; + wire_nl1Oil10i_dataout <= wire_nl1lOO00l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00O0O; + wire_nl1Oil10l_dataout <= wire_nl1lOO00O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00Oii; + wire_nl1Oil10O_dataout <= wire_nl1lOO0ii_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00Oil; + wire_nl1Oil11i_dataout <= wire_nl1lOO01l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00O1O; + wire_nl1Oil11l_dataout <= wire_nl1lOO01O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00O0i; + wire_nl1Oil11O_dataout <= wire_nl1lOO00i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00O0l; + wire_nl1Oil1ii_dataout <= wire_nl1lOO0il_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00OiO; + wire_nl1Oil1il_dataout <= wire_nl1lOO0iO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00Oli; + wire_nl1Oil1iO_dataout <= wire_nl1lOO0li_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00Oll; + wire_nl1Oil1li_dataout <= wire_nl1lOO0ll_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00OlO; + wire_nl1Oil1ll_dataout <= wire_nl1lOO0lO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00OOi; + wire_nl1Oil1lO_dataout <= wire_nl1lOO0Oi_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00OOl; + wire_nl1Oil1O_dataout <= nl1Oiill WHEN niOO1llii = '1' ELSE wire_nlOii10OO_dataout; + wire_nl1Oil1Oi_dataout <= wire_nl1lOO0Ol_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O00OOO; + wire_nl1Oil1Ol_dataout <= wire_nl1lOO0OO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i11i; + wire_nl1Oil1OO_dataout <= wire_nl1lOOi1i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i11l; + wire_nl1Oili_dataout <= n1Ol0lO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oili0i_dataout <= wire_nl1lOOl0l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i00O; + wire_nl1Oili0l_dataout <= wire_nl1lOOl0O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0ii; + wire_nl1Oili0O_dataout <= wire_nl1lOOlii_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0il; + wire_nl1Oili1i_dataout <= wire_nl1lOOl1l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i01O; + wire_nl1Oili1l_dataout <= wire_nl1lOOl1O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i00i; + wire_nl1Oili1O_dataout <= wire_nl1lOOl0i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i00l; + wire_nl1Oiliii_dataout <= wire_nl1lOOlil_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0iO; + wire_nl1Oiliil_dataout <= wire_nl1lOOliO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0li; + wire_nl1OiliiO_dataout <= wire_nl1lOOlli_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0ll; + wire_nl1Oilili_dataout <= wire_nl1lOOlll_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0lO; + wire_nl1Oilill_dataout <= wire_nl1lOOllO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0Oi; + wire_nl1OililO_dataout <= wire_nl1lOOlOi_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0Ol; + wire_nl1OiliOi_dataout <= wire_nl1lOOlOl_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0i0OO; + wire_nl1OiliOl_dataout <= wire_nl1lOOlOO_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0ii1i; + wire_nl1OiliOO_dataout <= wire_nl1lOOO1i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0ii1l; + wire_nl1Oill_dataout <= n1Ol0Oi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Oill0i_dataout <= wire_nl1lOOO0l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0ii0O; + wire_nl1Oill1i_dataout <= wire_nl1lOOO1l_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0ii1O; + wire_nl1Oill1l_dataout <= wire_nl1lOOO1O_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0ii0i; + wire_nl1Oill1O_dataout <= wire_nl1lOOO0i_dataout WHEN wire_w_lg_niOi1O0OO55207w(0) = '1' ELSE nl1O0ii0l; + wire_nl1Oilli_dataout <= nl1OilOi AND NOT(wire_niO01O0O_dataout); + wire_nl1OillO_dataout <= nl1Oil0l AND NOT(wire_niO01O0O_dataout); + wire_nl1OilO_dataout <= n1Ol0Ol AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OilOiO_dataout <= nl1OillOl AND NOT(wire_niO01O0O_dataout); + wire_nl1OilOl_dataout <= nl1OiO1i AND NOT(wire_niO01l0O_dataout); + wire_nl1OilOli_dataout <= dout_rcv0(62) AND NOT(wire_niO01O0O_dataout); + wire_nl1OilOll_dataout <= dout_rcv0(47) AND NOT(wire_niO01O0O_dataout); + wire_nl1OilOlO_dataout <= wire_nl1OiOl1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OilOOi_dataout <= wire_nl1OiOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OilOOl_dataout <= wire_nl1OiOi1O_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OilOOO_dataout <= wire_nl1OiOi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO01i_dataout <= nl1OilllO OR ((NOT (niOi011ii AND niOi1OOOO)) AND wire_nl011Ol0l_w_lg_dataout55199w(0)); + wire_nl1OiO0iO_dataout <= wire_nl1OiO0li_dataout AND NOT((niOi0111l OR (wire_nl011Ol1i_dataout OR niOi1Oi1i))); + wire_nl1OiO0l_dataout <= wire_nl1OiOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO0li_dataout <= nl1OillOi OR (wire_nl011Olil_dataout AND (wire_nlill0Oll_w_lg_w_lg_nl1OOii1l8961w55191w(0) AND wire_nlill0Oll_w_lg_nl1OilllO54891w(0))); + wire_nl1OiO0O_dataout <= wire_nl1OiOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO10i_dataout <= wire_nl1OiOili_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO10l_dataout <= wire_nl1OiOill_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO10O_dataout <= wire_nl1OiOilO_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO11i_dataout <= wire_nl1OiOi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO11l_dataout <= wire_nl1OiO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO11O_dataout <= wire_nl1OiO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO1ii_dataout <= wire_nl1OiOiOi_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO1il_dataout <= wire_nl1OiOiOl_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO1iO_dataout <= wire_nl1OiOiOO_o OR wire_niO01O0O_dataout; + wire_nl1OiO1l_dataout <= nl1OilOO AND NOT(wire_niO01l0O_dataout); + wire_nl1OiO1li_dataout <= wire_nl1OiO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO1ll_dataout <= wire_nl1OiOiii_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO1lO_dataout <= wire_nl1OiOiil_o AND NOT(wire_niO01O0O_dataout); + wire_nl1OiO1O_dataout <= nl1Oilll AND NOT(wire_niO01l0O_dataout); + wire_nl1OiO1Oi_dataout <= wire_nl1OiO1Ol_dataout AND NOT(niOO10lOl); + wire_nl1OiO1Ol_dataout <= nl1OilO0l OR nl1OilO0O; + wire_nl1OiO1OO_dataout <= wire_nl1OiO01i_dataout AND NOT((niOi0111l OR (niOi1Oi1i OR (wire_nl011Ol1l_w_lg_dataout54516w(0) AND (wire_nl011Ol1i_dataout AND nl1OillOi))))); + wire_nl1OiOi_dataout <= n1Ol0OO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OiOi0l_dataout <= wire_nl1Ol111l_dataout WHEN nl1OilO0i = '1' ELSE nl1Oillli; + wire_nl1OiOi0O_dataout <= wire_nl1Ol111O_dataout WHEN nl1OilO0i = '1' ELSE nl1Oillll; + wire_nl1OiOii_dataout <= wire_nl1000i_w_lg_nl1OiO1i7715w(0) WHEN (wire_nlOii1liO_dataout AND (wire_w_lg_niOO1llil7716w(0) AND (wire_nlOii1liO_dataout XOR nl1OiO0i))) = '1' ELSE nl1OiO1i; + wire_nl1OiOl_dataout <= n1Oli1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OiOl0i_dataout <= niOi1Oiil WHEN niOi1Oi0O = '1' ELSE nl1OilOii; + wire_nl1OiOl0l_dataout <= nl1OillOl AND NOT(niOi1Oi0O); + wire_nl1OiOl0O_dataout <= nl1OillOO AND NOT(niOi1Oi0O); + wire_nl1OiOl1i_dataout <= wire_nl1Ol11lO_dataout WHEN nl1OilO0i = '1' ELSE nl1Oillii; + wire_nl1OiOl1l_dataout <= wire_nl1Ol11Oi_dataout WHEN nl1OilO0i = '1' ELSE nl1Oillil; + wire_nl1OiOl1O_dataout <= wire_w_lg_niOi1Oiil55040w(0) WHEN niOi1Oi0O = '1' ELSE nl1OilO0O; + wire_nl1OiOlii_dataout <= nl1OilO1i OR niOi1Oi0O; + wire_nl1OiOlil_dataout <= nl1OilO1l AND NOT(niOi1Oi0O); + wire_nl1OiOliO_dataout <= nl1OilO1O AND NOT(niOi1Oi0O); + wire_nl1OiOll_dataout <= nl1OiO0i WHEN niOO1llil = '1' ELSE wire_nlOii1liO_dataout; + wire_nl1OiOlli_dataout <= nl1OilO0i AND NOT(niOi1Oi0O); + wire_nl1OiOlll_dataout <= wire_nl1OiOO1O_dataout WHEN niOi1Ol0l = '1' ELSE nl1OilliO; + wire_nl1OiOllO_dataout <= wire_nl1OiOO0i_dataout WHEN niOi1Ol0l = '1' ELSE nl1OilO0O; + wire_nl1OiOlOi_dataout <= wire_nl1OiOO0l_dataout WHEN niOi1Ol0l = '1' ELSE nl1OilOii; + wire_nl1OiOlOl_dataout <= nl1OillOl AND NOT(niOi1Ol0l); + wire_nl1OiOlOO_dataout <= wire_w_lg_niOi1Oi0O55062w(0) WHEN niOi1Ol0l = '1' ELSE nl1OillOO; + wire_nl1OiOO_dataout <= n1Oli1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OiOO0i_dataout <= wire_w_lg_niOi1Oi1O55066w(0) AND niOi1Oi0O; + wire_nl1OiOO0l_dataout <= niOi1Oi1O AND niOi1Oi0O; + wire_nl1OiOO0O_dataout <= nl1OilliO AND NOT(niOi1Oi1O); + wire_nl1OiOO1i_dataout <= niOi1Oi0O WHEN niOi1Ol0l = '1' ELSE nl1OilO1i; + wire_nl1OiOO1l_dataout <= nl1OilO1l AND NOT(niOi1Ol0l); + wire_nl1OiOO1O_dataout <= wire_nl1OiOO0O_dataout WHEN niOi1Oi0O = '1' ELSE nl1OilliO; + wire_nl1OiOOil_dataout <= nl1OilO0O AND NOT(niOi1Ol0l); + wire_nl1OiOOiO_dataout <= nl1OilOii AND NOT(niOi1Ol0l); + wire_nl1OiOOl_dataout <= wire_nl1OiOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OiOOli_dataout <= nl1OilliO WHEN niOi1Ol0l = '1' ELSE nl1OillOl; + wire_nl1OiOOll_dataout <= nl1OillOO AND NOT(niOi1Ol0l); + wire_nl1OiOOlO_dataout <= nl1OilO1i AND NOT(niOi1Ol0l); + wire_nl1OiOOO_dataout <= wire_nl1000i_w_lg_nl1Ol11l7712w(0) WHEN (nl1Ol1iO XOR nl1Ol1ii) = '1' ELSE nl1Ol11l; + wire_nl1OiOOOi_dataout <= wire_nlill0Oll_w_lg_nl1OilliO55056w(0) WHEN niOi1Ol0l = '1' ELSE nl1OilO1l; + wire_nl1OiOOOl_dataout <= nl1OilO1O AND NOT(niOi1Ol0l); + wire_nl1OiOOOO_dataout <= nl1OilO0i AND NOT(niOi1Ol0l); + wire_nl1Ol000i_dataout <= wire_nl1Ol0O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol000l_dataout <= wire_nl1Ol0O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol000O_dataout <= wire_nl1Ol0Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol001i_dataout <= wire_nl1Ol0O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol001l_dataout <= wire_nl1Ol0O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol001O_dataout <= wire_nl1Ol0O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00i_dataout <= nl1Ol1Oi WHEN niOO1lliO = '1' ELSE dl_req_phycfg(0); + wire_nl1Ol00ii_dataout <= wire_nl1Ol0Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00il_dataout <= wire_nl1Ol0OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00iO_dataout <= wire_nl1Ol0Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00li_dataout <= wire_nl1OllO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00ll_dataout <= wire_nl1OllO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00lO_dataout <= wire_nl1OllO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00Oi_dataout <= wire_nl1OllO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00Ol_dataout <= wire_nl1OllOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol00OO_dataout <= wire_nl1OllOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol010i_dataout <= wire_nl1Ol0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol010l_dataout <= wire_nl1Ol0iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol010O_dataout <= niOi1Ol0l AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01i_dataout <= wire_niOOO0O_w_lg_nl1Ol1li7708w(0) WHEN (wire_w_lg_niOO1lliO7709w(0) AND wire_w_lg_w_dl_req_phycfg_range7707w7710w(0)) = '1' ELSE nl1Ol1li; + wire_nl1Ol01ii_dataout <= wire_nl1Ol0lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01il_dataout <= wire_nl1Ol0liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01iO_dataout <= wire_nl1Ol0lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01li_dataout <= wire_nl1Ol0lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01ll_dataout <= wire_nl1Ol0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01lO_dataout <= wire_nl1Ol0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01Oi_dataout <= wire_nl1Ol0lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01Ol_dataout <= wire_nl1Ol0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol01OO_dataout <= wire_nl1Ol0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol0i_dataout <= n1Oli0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Ol0i0i_dataout <= derr_rcv0 WHEN (((wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND (wire_w_lg_w_k_gbl_hip_range55029w55039w(0) AND wire_w_lg_niOi1Oiil55040w(0))) AND wire_nlill0Oll_w_lg_nl1OilllO54891w(0)) AND (wire_nliliO10i_w_lg_nl1OilO0i55044w(0) OR wire_nliliO10i_w_lg_nl1ll0iOO55045w(0))) = '1' ELSE wire_nl1Ol0i0l_dataout; + wire_nl1Ol0i0l_dataout <= nl1OilOil AND NOT(niOi1Olli); + wire_nl1Ol0i1i_dataout <= wire_nl1OllOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol0i1l_dataout <= wire_nl1OllOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol0i1O_dataout <= wire_nl1OllOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol0ii_dataout <= wire_nl1Ol0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol0il_dataout <= wire_nl1000i_w_lg_nl1Ol0li7704w(0) WHEN (nl1Oli1l XOR nl1Ol0OO) = '1' ELSE nl1Ol0li; + wire_nl1Ol0iOi_dataout <= derr_rcv0 WHEN ((wire_nlill0Oll_w_lg_nl1OlO11l54923w(0) AND wire_w_lg_w_lg_w_k_gbl_hip_range55029w55032w55033w(0)) AND wire_nlill0Oll_w_lg_nl1ll0ilO55035w(0)) = '1' ELSE wire_nl1Ol0iOl_dataout; + wire_nl1Ol0iOl_dataout <= nl1Ol1l0i AND NOT(((wire_nlill0Oll_w_lg_nl1OilOii54862w(0) AND wire_nlill0Oll_w_lg_nl1ll0lOl5115w(0)) AND niOi1OiiO)); + wire_nl1Ol0l_dataout <= n1Oliii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Ol0lil_dataout <= wire_nl1OliO1l_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Ol0Oll_dataout; + wire_nl1Ol0liO_dataout <= wire_nl1OliO1O_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Ol0OlO_dataout; + wire_nl1Ol0lli_dataout <= wire_nl1OliO0i_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Ol0OOi_dataout; + wire_nl1Ol0lll_dataout <= wire_nl1OliO0l_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Ol0OOl_dataout; + wire_nl1Ol0llO_dataout <= wire_nl1OliO0O_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Ol0OOO_dataout; + wire_nl1Ol0lO_dataout <= nl1Ol0OO AND NOT(wire_niO01l0O_dataout); + wire_nl1Ol0lOi_dataout <= wire_nl1OliOii_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli11i_dataout; + wire_nl1Ol0lOl_dataout <= wire_nl1OliOil_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli11l_dataout; + wire_nl1Ol0lOO_dataout <= wire_nl1OliOiO_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli11O_dataout; + wire_nl1Ol0O_dataout <= n1Oliil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Ol0O0i_dataout <= wire_nl1OliOOi_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli1ii_dataout; + wire_nl1Ol0O0l_dataout <= wire_nl1OliOOl_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli1il_dataout; + wire_nl1Ol0O0O_dataout <= wire_nl1OliOOO_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli1iO_dataout; + wire_nl1Ol0O1i_dataout <= wire_nl1OliOli_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli10i_dataout; + wire_nl1Ol0O1l_dataout <= wire_nl1OliOll_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli10l_dataout; + wire_nl1Ol0O1O_dataout <= wire_nl1OliOlO_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli10O_dataout; + wire_nl1Ol0Oii_dataout <= wire_nl1Oll11i_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli1li_dataout; + wire_nl1Ol0Oil_dataout <= wire_nl1Oll11l_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli1ll_dataout; + wire_nl1Ol0OiO_dataout <= wire_nl1Oll11O_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli1lO_dataout; + wire_nl1Ol0Ol_dataout <= nl1Ol00O AND NOT(wire_niO01l0O_dataout); + wire_nl1Ol0Oli_dataout <= wire_nl1Oll10i_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Oli1Oi_dataout; + wire_nl1Ol0Oll_dataout <= wire_nl1Oli1Ol_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1l0O; + wire_nl1Ol0OlO_dataout <= wire_nl1Oli1OO_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1lii; + wire_nl1Ol0OOi_dataout <= wire_nl1Oli01i_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1lil; + wire_nl1Ol0OOl_dataout <= wire_nl1Oli01l_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1liO; + wire_nl1Ol0OOO_dataout <= wire_nl1Oli01O_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1lli; + wire_nl1Ol100i_dataout <= wire_nl1Ol10ll_dataout AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1Ol100l_dataout <= wire_nl1Ol10lO_dataout AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1Ol100O_dataout <= wire_nl1Ol10Ol_dataout AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1Ol101i_dataout <= nl1OilOii AND NOT(niOi1Oi0l); + wire_nl1Ol101O_dataout <= nl1OilliO WHEN wire_nl1OlOi1l_dataout = '1' ELSE wire_nl1Ol10Oi_dataout; + wire_nl1Ol10i_dataout <= nl1Ol1ii AND NOT(wire_niO01l0O_dataout); + wire_nl1Ol10ii_dataout <= wire_nl1Ol10OO_dataout AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1Ol10il_dataout <= wire_nl1Ol1i1i_dataout AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1Ol10iO_dataout <= wire_nl1Ol1i1l_dataout AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1Ol10li_dataout <= niOi1Oiii AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1Ol10ll_dataout <= wire_nl1Ol1iii_dataout WHEN niOi1Oiii = '1' ELSE wire_nl1OOi10i_dataout; + wire_nl1Ol10lO_dataout <= wire_nl1Ol1iil_dataout WHEN niOi1Oiii = '1' ELSE wire_nl1OOi10l_dataout; + wire_nl1Ol10O_dataout <= nl1OiOOi AND NOT(wire_niO01l0O_dataout); + wire_nl1Ol10Oi_dataout <= niOi1OllO WHEN niOi1Oiii = '1' ELSE nl1OilliO; + wire_nl1Ol10Ol_dataout <= wire_nl1Ol1i1O_dataout AND NOT(niOi1Oiii); + wire_nl1Ol10OO_dataout <= wire_nl1Ol1i0i_dataout AND NOT(niOi1Oiii); + wire_nl1Ol110i_dataout <= wire_nl1Ol100O_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Ol11Ol_dataout; + wire_nl1Ol110l_dataout <= wire_nl1Ol10ii_dataout WHEN niOi1Ol1l = '1' ELSE wire_nl1Ol101i_dataout; + wire_nl1Ol110O_dataout <= nl1OillOl AND NOT(niOi1Ol1l); + wire_nl1Ol111i_dataout <= wire_nl1Ol101O_dataout WHEN niOi1Ol1l = '1' ELSE nl1OilliO; + wire_nl1Ol111l_dataout <= wire_nl1Ol100i_dataout WHEN niOi1Ol1l = '1' ELSE nl1Oillli; + wire_nl1Ol111O_dataout <= wire_nl1Ol100l_dataout WHEN niOi1Ol1l = '1' ELSE nl1Oillll; + wire_nl1Ol11ii_dataout <= wire_nl1Ol10il_dataout WHEN niOi1Ol1l = '1' ELSE nl1OillOO; + wire_nl1Ol11il_dataout <= wire_nl1Ol10iO_dataout WHEN niOi1Ol1l = '1' ELSE nl1OilO1i; + wire_nl1Ol11iO_dataout <= wire_nl1OlOi1l_dataout WHEN niOi1Ol1l = '1' ELSE nl1OilO1l; + wire_nl1Ol11li_dataout <= wire_nl1Ol10li_dataout WHEN niOi1Ol1l = '1' ELSE nl1OilO1O; + wire_nl1Ol11ll_dataout <= nl1OilO0i AND NOT(niOi1Ol1l); + wire_nl1Ol11lO_dataout <= wire_nl1OOi11O_dataout WHEN niOi1Ol1l = '1' ELSE nl1Oillii; + wire_nl1Ol11Oi_dataout <= wire_nl1OOi11l_dataout WHEN niOi1Ol1l = '1' ELSE nl1Oillil; + wire_nl1Ol11Ol_dataout <= nl1OilO0O AND NOT(niOi1Oi0i); + wire_nl1Ol1i_dataout <= n1Oli1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Ol1i0i_dataout <= niOi0110O AND niOi1Oi0O; + wire_nl1Ol1i1i_dataout <= wire_w_lg_niOi1Oi0O55062w(0) AND NOT(niOi1Oiii); + wire_nl1Ol1i1l_dataout <= niOi1Oi0O AND NOT(niOi1Oiii); + wire_nl1Ol1i1O_dataout <= wire_w_lg_niOi0110O54834w(0) AND niOi1Oi0O; + wire_nl1Ol1iii_dataout <= wire_nl1OOi10i_dataout AND NOT(niOi1OllO); + wire_nl1Ol1iil_dataout <= wire_nl1OOi10l_dataout AND NOT(niOi1OllO); + wire_nl1Ol1il_dataout <= nl1Ol1li AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol1ili_dataout <= nl1Oillii WHEN wire_nlill0Oll_w_lg_nl1OilliO55056w(0) = '1' ELSE nl1Oill0l; + wire_nl1Ol1ill_dataout <= nl1Oillil WHEN wire_nlill0Oll_w_lg_nl1OilliO55056w(0) = '1' ELSE nl1Oill0O; + wire_nl1Ol1ill_w_lg_dataout55398w(0) <= wire_nl1Ol1ill_dataout AND wire_w_lg_niOi01i0l55397w(0); + wire_nl1Ol1ill_w_lg_dataout54875w(0) <= NOT wire_nl1Ol1ill_dataout; + wire_nl1Ol1l_dataout <= n1Oli0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Ol1ll_dataout <= nl1Ol1iO AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol1lO_dataout <= nl1Ol10l AND NOT(wire_niO01O0O_dataout); + wire_nl1Ol1O_dataout <= n1Oli0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Ol1Ol_dataout <= wire_nl1Ol01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1Ol1OO_dataout <= wire_nl1Ol00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1Oli00i_dataout <= nl1Ol1lll WHEN niOi1Oili = '1' ELSE wire_nl1Oliiii_dataout; + wire_nl1Oli00l_dataout <= nl1Ol1llO WHEN niOi1Oili = '1' ELSE wire_nl1Oliiil_dataout; + wire_nl1Oli00O_dataout <= nl1Ol1lOi WHEN niOi1Oili = '1' ELSE wire_nl1OliiiO_dataout; + wire_nl1Oli01i_dataout <= nl1Ol1lil WHEN niOi1Oili = '1' ELSE wire_nl1Olii0i_dataout; + wire_nl1Oli01l_dataout <= nl1Ol1liO WHEN niOi1Oili = '1' ELSE wire_nl1Olii0l_dataout; + wire_nl1Oli01O_dataout <= nl1Ol1lli WHEN niOi1Oili = '1' ELSE wire_nl1Olii0O_dataout; + wire_nl1Oli0i_dataout <= nl1Oli1l AND NOT(wire_niO01O0O_dataout); + wire_nl1Oli0ii_dataout <= nl1Ol1lOl WHEN niOi1Oili = '1' ELSE wire_nl1Oliili_dataout; + wire_nl1Oli0il_dataout <= k_ptr0(18) WHEN niOi1Oili = '1' ELSE wire_nl1Oliill_dataout; + wire_nl1Oli0iO_dataout <= k_ptr0(19) WHEN niOi1Oili = '1' ELSE wire_nl1OliilO_dataout; + wire_nl1Oli0l_dataout <= nl1Ol0Oi AND NOT(wire_niO01O0O_dataout); + wire_nl1Oli0li_dataout <= k_ptr0(20) WHEN niOi1Oili = '1' ELSE wire_nl1OliiOi_dataout; + wire_nl1Oli0ll_dataout <= k_ptr0(21) WHEN niOi1Oili = '1' ELSE wire_nl1OliiOl_dataout; + wire_nl1Oli0lO_dataout <= k_ptr0(22) WHEN niOi1Oili = '1' ELSE wire_nl1OliiOO_dataout; + wire_nl1Oli0Oi_dataout <= k_ptr0(23) WHEN niOi1Oili = '1' ELSE wire_nl1Olil1i_dataout; + wire_nl1Oli0Ol_dataout <= k_ptr0(24) WHEN niOi1Oili = '1' ELSE wire_nl1Olil1l_dataout; + wire_nl1Oli0OO_dataout <= k_ptr0(25) WHEN niOi1Oili = '1' ELSE wire_nl1Olil1O_dataout; + wire_nl1Oli10i_dataout <= wire_nl1Oli0ii_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1lOl; + wire_nl1Oli10l_dataout <= wire_nl1Oli0il_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1lOO; + wire_nl1Oli10O_dataout <= wire_nl1Oli0iO_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1O1i; + wire_nl1Oli11i_dataout <= wire_nl1Oli00i_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1lll; + wire_nl1Oli11l_dataout <= wire_nl1Oli00l_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1llO; + wire_nl1Oli11O_dataout <= wire_nl1Oli00O_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1lOi; + wire_nl1Oli1i_dataout <= nl1Oli1O AND NOT(wire_niO01O0O_dataout); + wire_nl1Oli1ii_dataout <= wire_nl1Oli0li_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1O1l; + wire_nl1Oli1il_dataout <= wire_nl1Oli0ll_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1O1O; + wire_nl1Oli1iO_dataout <= wire_nl1Oli0lO_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1O0i; + wire_nl1Oli1li_dataout <= wire_nl1Oli0Oi_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1O0l; + wire_nl1Oli1ll_dataout <= wire_nl1Oli0Ol_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1O0O; + wire_nl1Oli1lO_dataout <= wire_nl1Oli0OO_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1Oii; + wire_nl1Oli1Oi_dataout <= wire_nl1Olii1i_dataout WHEN niOi1OilO = '1' ELSE nl1Ol1Oil; + wire_nl1Oli1Ol_dataout <= nl1Ol1l0O WHEN niOi1Oili = '1' ELSE wire_nl1Olii1l_dataout; + wire_nl1Oli1OO_dataout <= nl1Ol1lii WHEN niOi1Oili = '1' ELSE wire_nl1Olii1O_dataout; + wire_nl1Olii_dataout <= n1OliiO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Olii0i_dataout <= k_ptr0(2) WHEN niOi1Oill = '1' ELSE wire_nl1Olilii_dataout; + wire_nl1Olii0l_dataout <= k_ptr0(3) WHEN niOi1Oill = '1' ELSE wire_nl1Olilil_dataout; + wire_nl1Olii0O_dataout <= k_ptr0(4) WHEN niOi1Oill = '1' ELSE wire_nl1OliliO_dataout; + wire_nl1Olii1i_dataout <= k_ptr0(26) WHEN niOi1Oili = '1' ELSE wire_nl1Olil0i_dataout; + wire_nl1Olii1l_dataout <= k_ptr0(0) WHEN niOi1Oill = '1' ELSE wire_nl1Olil0l_dataout; + wire_nl1Olii1O_dataout <= k_ptr0(1) WHEN niOi1Oill = '1' ELSE wire_nl1Olil0O_dataout; + wire_nl1Oliii_dataout <= wire_nl1OliiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1Oliiii_dataout <= k_ptr0(5) WHEN niOi1Oill = '1' ELSE wire_nl1Olilli_dataout; + wire_nl1Oliiil_dataout <= k_ptr0(6) WHEN niOi1Oill = '1' ELSE wire_nl1Olilll_dataout; + wire_nl1OliiiO_dataout <= k_ptr0(7) WHEN niOi1Oill = '1' ELSE wire_nl1OlillO_dataout; + wire_nl1Oliil_dataout <= wire_nl1OlilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1Oliili_dataout <= k_ptr0(8) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOi_dataout; + wire_nl1Oliill_dataout <= k_ptr0(0) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(0); + wire_nl1OliilO_dataout <= k_ptr0(1) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(1); + wire_nl1OliiO_dataout <= wire_niOOO0O_w_lg_nl1Oli1O7700w(0) WHEN (wire_w_lg_niOO1llli7701w(0) AND wire_w_lg_w_dl_req_phycfg_range7699w7702w(0)) = '1' ELSE nl1Oli1O; + wire_nl1OliiOi_dataout <= k_ptr0(2) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(2); + wire_nl1OliiOl_dataout <= k_ptr0(3) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(3); + wire_nl1OliiOO_dataout <= k_ptr0(4) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(4); + wire_nl1Olil_dataout <= n1Olili AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Olil0i_dataout <= k_ptr0(8) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(8); + wire_nl1Olil0l_dataout <= wire_nl1OlilOO_o(0) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1l0O; + wire_nl1Olil0O_dataout <= wire_nl1OlilOO_o(1) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1lii; + wire_nl1Olil1i_dataout <= k_ptr0(5) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(5); + wire_nl1Olil1l_dataout <= k_ptr0(6) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(6); + wire_nl1Olil1O_dataout <= k_ptr0(7) WHEN niOi1Oill = '1' ELSE wire_nl1OlilOO_o(7); + wire_nl1Olilii_dataout <= wire_nl1OlilOO_o(2) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1lil; + wire_nl1Olilil_dataout <= wire_nl1OlilOO_o(3) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1liO; + wire_nl1OliliO_dataout <= wire_nl1OlilOO_o(4) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1lli; + wire_nl1Olilli_dataout <= wire_nl1OlilOO_o(5) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1lll; + wire_nl1Olilll_dataout <= wire_nl1OlilOO_o(6) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1llO; + wire_nl1OlillO_dataout <= wire_nl1OlilOO_o(7) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1lOi; + wire_nl1OlilO_dataout <= nl1Oli0O WHEN niOO1llli = '1' ELSE dl_req_phycfg(1); + wire_nl1OlilOi_dataout <= wire_nl1OlilOO_o(8) WHEN wire_nl1OlilOl_o = '1' ELSE nl1Ol1lOl; + wire_nl1OliO_dataout <= n1Olill AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OliO0i_dataout <= nl1Ol1lil WHEN niOi1OllO = '1' ELSE wire_nl1Oll1ii_dataout; + wire_nl1OliO0l_dataout <= nl1Ol1liO WHEN niOi1OllO = '1' ELSE wire_nl1Oll1il_dataout; + wire_nl1OliO0O_dataout <= nl1Ol1lli WHEN niOi1OllO = '1' ELSE wire_nl1Oll1iO_dataout; + wire_nl1OliO1l_dataout <= nl1Ol1l0O WHEN niOi1OllO = '1' ELSE wire_nl1Oll10l_dataout; + wire_nl1OliO1O_dataout <= nl1Ol1lii WHEN niOi1OllO = '1' ELSE wire_nl1Oll10O_dataout; + wire_nl1OliOii_dataout <= nl1Ol1lll WHEN niOi1OllO = '1' ELSE wire_nl1Oll1li_dataout; + wire_nl1OliOil_dataout <= nl1Ol1llO WHEN niOi1OllO = '1' ELSE wire_nl1Oll1ll_dataout; + wire_nl1OliOiO_dataout <= nl1Ol1lOi WHEN niOi1OllO = '1' ELSE wire_nl1Oll1lO_dataout; + wire_nl1OliOli_dataout <= nl1Ol1lOl WHEN niOi1OllO = '1' ELSE wire_nl1Oll1Oi_dataout; + wire_nl1OliOll_dataout <= wire_nl1OlOiOO_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll1Ol_dataout; + wire_nl1OliOlO_dataout <= wire_nl1OlOl1i_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll1OO_dataout; + wire_nl1OliOO_dataout <= wire_nl1Oll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OliOOi_dataout <= wire_nl1OlOl1l_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll01i_dataout; + wire_nl1OliOOl_dataout <= wire_nl1OlOl1O_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll01l_dataout; + wire_nl1OliOOO_dataout <= wire_nl1OlOl0i_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll01O_dataout; + wire_nl1Oll00i_dataout <= nl1OOi0Oi WHEN niOi1OiOl = '1' ELSE wire_nl1Olliii_dataout; + wire_nl1Oll00l_dataout <= nl1OOi0Ol WHEN niOi1OiOl = '1' ELSE wire_nl1Olliil_dataout; + wire_nl1Oll00O_dataout <= nl1OOi0OO WHEN niOi1OiOl = '1' ELSE wire_nl1OlliiO_dataout; + wire_nl1Oll01i_dataout <= nl1OOi0li WHEN niOi1OiOl = '1' ELSE wire_nl1Olli0i_dataout; + wire_nl1Oll01l_dataout <= nl1OOi0ll WHEN niOi1OiOl = '1' ELSE wire_nl1Olli0l_dataout; + wire_nl1Oll01O_dataout <= nl1OOi0lO WHEN niOi1OiOl = '1' ELSE wire_nl1Olli0O_dataout; + wire_nl1Oll0ii_dataout <= nl1OOii1i WHEN niOi1OiOl = '1' ELSE wire_nl1Ollili_dataout; + wire_nl1Oll0il_dataout <= wire_nl1Ollill_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1l0O; + wire_nl1Oll0iO_dataout <= wire_nl1OllilO_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1lii; + wire_nl1Oll0l_dataout <= nl1Ollil AND NOT(wire_niO01l0O_dataout); + wire_nl1Oll0li_dataout <= wire_nl1OlliOi_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1lil; + wire_nl1Oll0ll_dataout <= wire_nl1OlliOl_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1liO; + wire_nl1Oll0lO_dataout <= wire_nl1OlliOO_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1lli; + wire_nl1Oll0Oi_dataout <= wire_nl1Olll1i_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1lll; + wire_nl1Oll0Ol_dataout <= wire_nl1Olll1l_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1llO; + wire_nl1Oll0OO_dataout <= wire_nl1Olll1O_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1lOi; + wire_nl1Oll10i_dataout <= wire_nl1OlOlil_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll0ii_dataout; + wire_nl1Oll10l_dataout <= wire_nl1Olllii_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0il_dataout; + wire_nl1Oll10O_dataout <= wire_nl1Olllil_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0iO_dataout; + wire_nl1Oll11i_dataout <= wire_nl1OlOl0l_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll00i_dataout; + wire_nl1Oll11l_dataout <= wire_nl1OlOl0O_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll00l_dataout; + wire_nl1Oll11O_dataout <= wire_nl1OlOlii_dataout WHEN niOi1OllO = '1' ELSE wire_nl1Oll00O_dataout; + wire_nl1Oll1i_dataout <= wire_nl1000i_w_lg_nl1Oll1O7696w(0) WHEN (nl1Ollli XOR nl1Ollil) = '1' ELSE nl1Oll1O; + wire_nl1Oll1ii_dataout <= wire_nl1OllliO_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0li_dataout; + wire_nl1Oll1il_dataout <= wire_nl1Olllli_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0ll_dataout; + wire_nl1Oll1iO_dataout <= wire_nl1Olllll_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0lO_dataout; + wire_nl1Oll1li_dataout <= wire_nl1OllllO_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0Oi_dataout; + wire_nl1Oll1ll_dataout <= wire_nl1OlllOi_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0Ol_dataout; + wire_nl1Oll1lO_dataout <= wire_nl1OlllOl_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Oll0OO_dataout; + wire_nl1Oll1Oi_dataout <= wire_nl1OlllOO_dataout WHEN niOi1OiOl = '1' ELSE wire_nl1Olli1i_dataout; + wire_nl1Oll1Ol_dataout <= nl1OOi0il WHEN niOi1OiOl = '1' ELSE wire_nl1Olli1l_dataout; + wire_nl1Oll1OO_dataout <= nl1OOi0iO WHEN niOi1OiOl = '1' ELSE wire_nl1Olli1O_dataout; + wire_nl1Olli_dataout <= n1OlilO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Olli0i_dataout <= nl1Ol1Oll WHEN niOi1OiOi = '1' ELSE nl1Ol1O1l; + wire_nl1Olli0l_dataout <= nl1Ol1OlO WHEN niOi1OiOi = '1' ELSE nl1Ol1O1O; + wire_nl1Olli0O_dataout <= nl1Ol1OOi WHEN niOi1OiOi = '1' ELSE nl1Ol1O0i; + wire_nl1Olli1i_dataout <= wire_nl1Olll0i_dataout WHEN niOi1OiOi = '1' ELSE nl1Ol1lOl; + wire_nl1Olli1l_dataout <= nl1Ol1OiO WHEN niOi1OiOi = '1' ELSE nl1Ol1lOO; + wire_nl1Olli1O_dataout <= nl1Ol1Oli WHEN niOi1OiOi = '1' ELSE nl1Ol1O1i; + wire_nl1Ollii_dataout <= nl1OliOl AND NOT(wire_niO01l0O_dataout); + wire_nl1Olliii_dataout <= nl1Ol1OOl WHEN niOi1OiOi = '1' ELSE nl1Ol1O0l; + wire_nl1Olliil_dataout <= nl1Ol1OOO WHEN niOi1OiOi = '1' ELSE nl1Ol1O0O; + wire_nl1OlliiO_dataout <= nl1Ol011i WHEN niOi1OiOi = '1' ELSE nl1Ol1Oii; + wire_nl1Ollili_dataout <= nl1Ol011l WHEN niOi1OiOi = '1' ELSE nl1Ol1Oil; + wire_nl1Ollill_dataout <= nl1Ol1OiO WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1l0O; + wire_nl1OllilO_dataout <= nl1Ol1Oli WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1lii; + wire_nl1OlliO_dataout <= nl1Ollll AND NOT(wire_niO01O0O_dataout); + wire_nl1OlliOi_dataout <= nl1Ol1Oll WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1lil; + wire_nl1OlliOl_dataout <= nl1Ol1OlO WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1liO; + wire_nl1OlliOO_dataout <= nl1Ol1OOi WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1lli; + wire_nl1Olll_dataout <= n1OliOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1Olll0i_dataout <= nl1Ol011l WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1lOl; + wire_nl1Olll1i_dataout <= nl1Ol1OOl WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1lll; + wire_nl1Olll1l_dataout <= nl1Ol1OOO WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1llO; + wire_nl1Olll1O_dataout <= nl1Ol011i WHEN wire_nl1Olll0l_o = '1' ELSE nl1Ol1lOi; + wire_nl1Olllii_dataout <= nl1OOi0il WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1l0O; + wire_nl1Olllil_dataout <= nl1OOi0iO WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1lii; + wire_nl1OllliO_dataout <= nl1OOi0li WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1lil; + wire_nl1Olllli_dataout <= nl1OOi0ll WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1liO; + wire_nl1Olllll_dataout <= nl1OOi0lO WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1lli; + wire_nl1OllllO_dataout <= nl1OOi0Oi WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1lll; + wire_nl1OlllO_dataout <= nl1Ollli AND NOT(wire_niO01O0O_dataout); + wire_nl1OlllOi_dataout <= nl1OOi0Ol WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1llO; + wire_nl1OlllOl_dataout <= nl1OOi0OO WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1lOi; + wire_nl1OlllOO_dataout <= nl1OOii1i WHEN wire_nl1Ol0lii_o = '1' ELSE nl1Ol1lOl; + wire_nl1OllO_dataout <= n1OliOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OllO0i_dataout <= wire_nl1OOOl1O_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol1Oli; + wire_nl1OllO0l_dataout <= wire_nl1OOOl0i_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol1Oll; + wire_nl1OllO0O_dataout <= wire_nl1OOOl0l_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol1OlO; + wire_nl1OllO1O_dataout <= wire_nl1OOOl1l_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol1OiO; + wire_nl1OllOi_dataout <= nl1Oll0O AND NOT(wire_niO01O0O_dataout); + wire_nl1OllOii_dataout <= wire_nl1OOOl0O_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol1OOi; + wire_nl1OllOil_dataout <= wire_nl1OOOlii_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol1OOl; + wire_nl1OllOiO_dataout <= wire_nl1OOOlil_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol1OOO; + wire_nl1OllOli_dataout <= wire_nl1OOOliO_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol011i; + wire_nl1OllOll_dataout <= wire_nl1OOOlli_dataout WHEN wire_nlill0Oll_w_lg_nl1OilllO54891w(0) = '1' ELSE nl1Ol011l; + wire_nl1OllOO_dataout <= wire_nl1OlO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1OlO01i_dataout <= wire_nl1OlOi1l_dataout WHEN niOi1Ol1l = '1' ELSE nl1OlO11l; + wire_nl1OlO01l_dataout <= niOi1OllO AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1OlO0l_dataout <= nl1OllOl WHEN niOO1llll = '1' ELSE dl_req_phycfg(2); + wire_nl1OlO10i_dataout <= wire_nl1OlO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OlO10l_dataout <= wire_nl1OlO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OlO10O_dataout <= wire_nl1OlO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OlO1i_dataout <= wire_nl1OlO0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1OlO1ii_dataout <= wire_nl1OlO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OlO1il_dataout <= wire_nl1OlO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OlO1iO_dataout <= wire_nl1OlOi1l_dataout AND niOi1OiOO; + wire_nl1OlO1l_dataout <= wire_niOOO0O_w_lg_nl1Ollll7692w(0) WHEN (wire_w_lg_niOO1llll7693w(0) AND wire_w_lg_w_dl_req_phycfg_range7691w7694w(0)) = '1' ELSE nl1Ollll; + wire_nl1OlO1li_dataout <= wire_nl1OlO01l_dataout AND niOi1OiOO; + wire_nl1OlO1ll_dataout <= wire_nl1OlO1lO_dataout AND niOi1OiOO; + wire_nl1OlO1lO_dataout <= wire_w_lg_niOi1OllO54888w(0) AND NOT(wire_nl1OlOi1l_dataout); + wire_nl1OlO1OO_dataout <= wire_nl1OlO01l_dataout WHEN niOi1Ol1l = '1' ELSE nl1OlO11i; + wire_nl1OlOi_dataout <= n1OliOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OlOi1l_dataout <= (wire_nl011iO1O_w54848w(0) AND (NOT (wire_nilO010O_w_lg_w_lg_w_lg_dataout8970w8972w54849w(0) OR wire_nilO010O_w_lg_w_lg_dataout8976w8977w(0)))) AND (wire_nlill0Oll_w_lg_nl1OOi01l54523w(0) AND wire_w_lg_niOi0101i54853w(0)); + wire_nl1OlOi1l_w_lg_dataout55402w(0) <= NOT wire_nl1OlOi1l_dataout; + wire_nl1OlOil_dataout <= wire_nl1OlOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OlOiO_dataout <= wire_nl1000i_w_lg_nl1OlOll7688w(0) WHEN (nl1OO11O XOR nl1OO11i) = '1' ELSE nl1OlOll; + wire_nl1OlOiOO_dataout <= wire_nl1OO1O1i_o(0) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOliO_dataout; + wire_nl1OlOl_dataout <= n1Oll1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OlOl0i_dataout <= wire_nl1OO1O1i_o(4) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOlOi_dataout; + wire_nl1OlOl0l_dataout <= wire_nl1OO1O1i_o(5) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOlOl_dataout; + wire_nl1OlOl0O_dataout <= wire_nl1OO1O1i_o(6) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOlOO_dataout; + wire_nl1OlOl1i_dataout <= wire_nl1OO1O1i_o(1) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOlli_dataout; + wire_nl1OlOl1l_dataout <= wire_nl1OO1O1i_o(2) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOlll_dataout; + wire_nl1OlOl1O_dataout <= wire_nl1OO1O1i_o(3) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOllO_dataout; + wire_nl1OlOlii_dataout <= wire_nl1OO1O1i_o(7) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOO1i_dataout; + wire_nl1OlOlil_dataout <= wire_nl1OO1O1i_o(8) WHEN niOi1OOiO = '1' ELSE wire_nl1OlOO1l_dataout; + wire_nl1OlOliO_dataout <= k_ptr0(18) WHEN niOi1OOii = '1' ELSE wire_nl1OlOO1O_dataout; + wire_nl1OlOlli_dataout <= wire_nl1OO1lOO_o(0) WHEN niOi1OOii = '1' ELSE wire_nl1OlOO0i_dataout; + wire_nl1OlOlll_dataout <= wire_nl1OO1lOO_o(1) WHEN niOi1OOii = '1' ELSE wire_nl1OlOO0l_dataout; + wire_nl1OlOllO_dataout <= wire_nl1OO1lOO_o(2) WHEN niOi1OOii = '1' ELSE wire_nl1OlOO0O_dataout; + wire_nl1OlOlOi_dataout <= wire_nl1OO1lOO_o(3) WHEN niOi1OOii = '1' ELSE wire_nl1OlOOii_dataout; + wire_nl1OlOlOl_dataout <= wire_nl1OO1lOO_o(4) WHEN niOi1OOii = '1' ELSE wire_nl1OlOOil_dataout; + wire_nl1OlOlOO_dataout <= wire_nl1OO1lOO_o(5) WHEN niOi1OOii = '1' ELSE wire_nl1OlOOiO_dataout; + wire_nl1OlOO_dataout <= n1Oll1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OlOO0i_dataout <= k_ptr0(19) WHEN niOi1OO0l = '1' ELSE wire_nl1OlOOOi_dataout; + wire_nl1OlOO0l_dataout <= k_ptr0(20) WHEN niOi1OO0l = '1' ELSE wire_nl1OlOOOl_dataout; + wire_nl1OlOO0O_dataout <= k_ptr0(21) WHEN niOi1OO0l = '1' ELSE wire_nl1OlOOOO_dataout; + wire_nl1OlOO1i_dataout <= wire_nl1OO1lOO_o(6) WHEN niOi1OOii = '1' ELSE wire_nl1OlOOli_dataout; + wire_nl1OlOO1l_dataout <= wire_nl1OO1lOO_o(7) WHEN niOi1OOii = '1' ELSE wire_nl1OlOOll_dataout; + wire_nl1OlOO1O_dataout <= k_ptr0(18) WHEN niOi1OO0l = '1' ELSE wire_nl1OlOOlO_dataout; + wire_nl1OlOOi_dataout <= nl1OO11i AND NOT(wire_niO01l0O_dataout); + wire_nl1OlOOii_dataout <= k_ptr0(22) WHEN niOi1OO0l = '1' ELSE wire_nl1OO111i_dataout; + wire_nl1OlOOil_dataout <= k_ptr0(23) WHEN niOi1OO0l = '1' ELSE wire_nl1OO111l_dataout; + wire_nl1OlOOiO_dataout <= k_ptr0(24) WHEN niOi1OO0l = '1' ELSE wire_nl1OO111O_dataout; + wire_nl1OlOOli_dataout <= k_ptr0(25) WHEN niOi1OO0l = '1' ELSE wire_nl1OO110i_dataout; + wire_nl1OlOOll_dataout <= k_ptr0(26) WHEN niOi1OO0l = '1' ELSE wire_nl1OO110l_dataout; + wire_nl1OlOOlO_dataout <= wire_nl1OO1O1i_o(0) WHEN niOi1OOil = '1' ELSE wire_nl1OO110O_dataout; + wire_nl1OlOOO_dataout <= nl1OlOii AND NOT(wire_niO01l0O_dataout); + wire_nl1OlOOOi_dataout <= wire_nl1OO1O1i_o(1) WHEN niOi1OOil = '1' ELSE wire_nl1OO11ii_dataout; + wire_nl1OlOOOl_dataout <= wire_nl1OO1O1i_o(2) WHEN niOi1OOil = '1' ELSE wire_nl1OO11il_dataout; + wire_nl1OlOOOO_dataout <= wire_nl1OO1O1i_o(3) WHEN niOi1OOil = '1' ELSE wire_nl1OO11iO_dataout; + wire_nl1OO000i_dataout <= wire_nl1OO0l1O_dataout AND NOT(niOi0111i); + wire_nl1OO000l_dataout <= wire_nl1OO0l0i_dataout AND NOT(niOi0111i); + wire_nl1OO000O_dataout <= wire_nl1OO0l0l_dataout AND NOT(niOi0111i); + wire_nl1OO001i_dataout <= wire_nl1OO0iOO_dataout AND NOT(niOi0111i); + wire_nl1OO001l_dataout <= wire_nl1OO0l1i_dataout AND NOT(niOi0111i); + wire_nl1OO001O_dataout <= wire_nl1OO0l1l_dataout AND NOT(niOi0111i); + wire_nl1OO00ii_dataout <= wire_nl1OO0l0O_dataout AND NOT(niOi0111i); + wire_nl1OO00il_dataout <= wire_nl1OO0lii_dataout AND NOT(niOi0111i); + wire_nl1OO00iO_dataout <= wire_nl1OO0lil_dataout AND NOT(niOi0111i); + wire_nl1OO00li_dataout <= wire_nl1OO0lli_dataout AND NOT(niOi0111i); + wire_nl1OO00ll_dataout <= ((niOi0110l AND (wire_nlill0Oll_w_lg_nl1OO010l54593w(0) AND niOi0110i)) AND niOi1OOOO) AND NOT(niOi0111i); + wire_nl1OO00lO_dataout <= nl1OOi0il WHEN niOi1OOlO = '1' ELSE wire_nl1OO0i0O_dataout; + wire_nl1OO00Oi_dataout <= nl1OOi0iO WHEN niOi1OOlO = '1' ELSE wire_nl1OO0iii_dataout; + wire_nl1OO00Ol_dataout <= nl1OOi0li WHEN niOi1OOlO = '1' ELSE wire_nl1OO0iil_dataout; + wire_nl1OO00OO_dataout <= nl1OOi0ll WHEN niOi1OOlO = '1' ELSE wire_nl1OO0iiO_dataout; + wire_nl1OO01ii_dataout <= wire_nl1OO00lO_dataout AND NOT(niOi0111i); + wire_nl1OO01il_dataout <= wire_nl1OO00Oi_dataout AND NOT(niOi0111i); + wire_nl1OO01iO_dataout <= wire_nl1OO00Ol_dataout AND NOT(niOi0111i); + wire_nl1OO01li_dataout <= wire_nl1OO00OO_dataout AND NOT(niOi0111i); + wire_nl1OO01ll_dataout <= wire_nl1OO0i1i_dataout AND NOT(niOi0111i); + wire_nl1OO01lO_dataout <= wire_nl1OO0i1l_dataout AND NOT(niOi0111i); + wire_nl1OO01Oi_dataout <= wire_nl1OO0i1O_dataout AND NOT(niOi0111i); + wire_nl1OO01Ol_dataout <= wire_nl1OO0i0i_dataout AND NOT(niOi0111i); + wire_nl1OO01OO_dataout <= wire_nl1OO0i0l_dataout AND NOT(niOi0111i); + wire_nl1OO0i_dataout <= n1Oll0O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OO0i0i_dataout <= nl1OOi0OO WHEN niOi1OOlO = '1' ELSE wire_nl1OO0iOi_dataout; + wire_nl1OO0i0l_dataout <= nl1OOii1i WHEN niOi1OOlO = '1' ELSE wire_nl1OO0iOl_dataout; + wire_nl1OO0i0O_dataout <= nl1OOi0il WHEN nl1OO010l = '1' ELSE nl1OlO11O; + wire_nl1OO0i1i_dataout <= nl1OOi0lO WHEN niOi1OOlO = '1' ELSE wire_nl1OO0ili_dataout; + wire_nl1OO0i1l_dataout <= nl1OOi0Oi WHEN niOi1OOlO = '1' ELSE wire_nl1OO0ill_dataout; + wire_nl1OO0i1O_dataout <= nl1OOi0Ol WHEN niOi1OOlO = '1' ELSE wire_nl1OO0ilO_dataout; + wire_nl1OO0iii_dataout <= nl1OOi0iO WHEN nl1OO010l = '1' ELSE nl1OO1O1l; + wire_nl1OO0iil_dataout <= nl1OOi0li WHEN nl1OO010l = '1' ELSE nl1OO1O1O; + wire_nl1OO0iiO_dataout <= nl1OOi0ll WHEN nl1OO010l = '1' ELSE nl1OO1O0i; + wire_nl1OO0ili_dataout <= nl1OOi0lO WHEN nl1OO010l = '1' ELSE nl1OO1O0l; + wire_nl1OO0ill_dataout <= nl1OOi0Oi WHEN nl1OO010l = '1' ELSE nl1OO1O0O; + wire_nl1OO0ilO_dataout <= nl1OOi0Ol WHEN nl1OO010l = '1' ELSE nl1OO1Oii; + wire_nl1OO0iOi_dataout <= nl1OOi0OO WHEN nl1OO010l = '1' ELSE nl1OO1Oil; + wire_nl1OO0iOl_dataout <= nl1OOii1i WHEN nl1OO010l = '1' ELSE nl1OO1OiO; + wire_nl1OO0iOO_dataout <= nl1OOi0il WHEN niOi1OOlO = '1' ELSE wire_nl1OlOiOO_dataout; + wire_nl1OO0l_dataout <= n1Ollii AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OO0l0i_dataout <= nl1OOi0lO WHEN niOi1OOlO = '1' ELSE wire_nl1OlOl0i_dataout; + wire_nl1OO0l0l_dataout <= nl1OOi0Oi WHEN niOi1OOlO = '1' ELSE wire_nl1OlOl0l_dataout; + wire_nl1OO0l0O_dataout <= nl1OOi0Ol WHEN niOi1OOlO = '1' ELSE wire_nl1OlOl0O_dataout; + wire_nl1OO0l1i_dataout <= nl1OOi0iO WHEN niOi1OOlO = '1' ELSE wire_nl1OlOl1i_dataout; + wire_nl1OO0l1l_dataout <= nl1OOi0li WHEN niOi1OOlO = '1' ELSE wire_nl1OlOl1l_dataout; + wire_nl1OO0l1O_dataout <= nl1OOi0ll WHEN niOi1OOlO = '1' ELSE wire_nl1OlOl1O_dataout; + wire_nl1OO0lii_dataout <= nl1OOi0OO WHEN niOi1OOlO = '1' ELSE wire_nl1OlOlii_dataout; + wire_nl1OO0lil_dataout <= nl1OOii1i WHEN niOi1OOlO = '1' ELSE wire_nl1OlOlil_dataout; + wire_nl1OO0lli_dataout <= wire_nl1OO0lll_dataout AND NOT((wire_nlill0Oll_w_lg_w_lg_nl1OO010i54591w54592w(0) AND wire_nlill0Oll_w_lg_nl1OO010l54593w(0))); + wire_nl1OO0lll_dataout <= nl1OO010i OR (niOi0111l OR nl1OO010l); + wire_nl1OO0O_dataout <= n1Ollil AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OO100i_dataout <= wire_nl1OO1ili_o(3) WHEN niOi1OlOO = '1' ELSE wire_nl1OO10Oi_dataout; + wire_nl1OO100l_dataout <= wire_nl1OO1ili_o(4) WHEN niOi1OlOO = '1' ELSE wire_nl1OO10Ol_dataout; + wire_nl1OO100O_dataout <= wire_nl1OO1ili_o(5) WHEN niOi1OlOO = '1' ELSE wire_nl1OO10OO_dataout; + wire_nl1OO101i_dataout <= wire_nl1OO1ili_o(0) WHEN niOi1OlOO = '1' ELSE wire_nl1OO10li_dataout; + wire_nl1OO101l_dataout <= wire_nl1OO1ili_o(1) WHEN niOi1OlOO = '1' ELSE wire_nl1OO10ll_dataout; + wire_nl1OO101O_dataout <= wire_nl1OO1ili_o(2) WHEN niOi1OlOO = '1' ELSE wire_nl1OO10lO_dataout; + wire_nl1OO10ii_dataout <= wire_nl1OO1ili_o(6) WHEN niOi1OlOO = '1' ELSE wire_nl1OO1i1i_dataout; + wire_nl1OO10il_dataout <= wire_nl1OO1ili_o(7) WHEN niOi1OlOO = '1' ELSE wire_nl1OO1i1l_dataout; + wire_nl1OO10iO_dataout <= wire_nl1OO1i1O_o(0) WHEN niOi1OlOl = '1' ELSE nl1OO1Oli; + wire_nl1OO10l_dataout <= nl1OO11O AND NOT(wire_niO01O0O_dataout); + wire_nl1OO10li_dataout <= wire_nl1OO1i1O_o(1) WHEN niOi1OlOl = '1' ELSE nl1OO1Oll; + wire_nl1OO10ll_dataout <= wire_nl1OO1i1O_o(2) WHEN niOi1OlOl = '1' ELSE nl1OO1OlO; + wire_nl1OO10lO_dataout <= wire_nl1OO1i1O_o(3) WHEN niOi1OlOl = '1' ELSE nl1OO1OOi; + wire_nl1OO10O_dataout <= nl1OlOOl AND NOT(wire_niO01O0O_dataout); + wire_nl1OO10Oi_dataout <= wire_nl1OO1i1O_o(4) WHEN niOi1OlOl = '1' ELSE nl1OO1OOl; + wire_nl1OO10Ol_dataout <= wire_nl1OO1i1O_o(5) WHEN niOi1OlOl = '1' ELSE nl1OO1OOO; + wire_nl1OO10OO_dataout <= wire_nl1OO1i1O_o(6) WHEN niOi1OlOl = '1' ELSE nl1OO011i; + wire_nl1OO110i_dataout <= wire_nl1OO1O1i_o(7) WHEN niOi1OOil = '1' ELSE wire_nl1OO11Oi_dataout; + wire_nl1OO110l_dataout <= wire_nl1OO1O1i_o(8) WHEN niOi1OOil = '1' ELSE wire_nl1OO11Ol_dataout; + wire_nl1OO110O_dataout <= k_ptr0(18) WHEN niOi1OO1l = '1' ELSE wire_nl1OO11OO_dataout; + wire_nl1OO111i_dataout <= wire_nl1OO1O1i_o(4) WHEN niOi1OOil = '1' ELSE wire_nl1OO11li_dataout; + wire_nl1OO111l_dataout <= wire_nl1OO1O1i_o(5) WHEN niOi1OOil = '1' ELSE wire_nl1OO11ll_dataout; + wire_nl1OO111O_dataout <= wire_nl1OO1O1i_o(6) WHEN niOi1OOil = '1' ELSE wire_nl1OO11lO_dataout; + wire_nl1OO11ii_dataout <= k_ptr0(19) WHEN niOi1OO1l = '1' ELSE wire_nl1OO101i_dataout; + wire_nl1OO11il_dataout <= k_ptr0(20) WHEN niOi1OO1l = '1' ELSE wire_nl1OO101l_dataout; + wire_nl1OO11iO_dataout <= k_ptr0(21) WHEN niOi1OO1l = '1' ELSE wire_nl1OO101O_dataout; + wire_nl1OO11l_dataout <= nl1OO10i AND NOT(wire_niO01O0O_dataout); + wire_nl1OO11li_dataout <= k_ptr0(22) WHEN niOi1OO1l = '1' ELSE wire_nl1OO100i_dataout; + wire_nl1OO11ll_dataout <= k_ptr0(23) WHEN niOi1OO1l = '1' ELSE wire_nl1OO100l_dataout; + wire_nl1OO11lO_dataout <= k_ptr0(24) WHEN niOi1OO1l = '1' ELSE wire_nl1OO100O_dataout; + wire_nl1OO11Oi_dataout <= k_ptr0(25) WHEN niOi1OO1l = '1' ELSE wire_nl1OO10ii_dataout; + wire_nl1OO11Ol_dataout <= k_ptr0(26) WHEN niOi1OO1l = '1' ELSE wire_nl1OO10il_dataout; + wire_nl1OO11OO_dataout <= nl1OO1Oli WHEN niOi1OlOO = '1' ELSE wire_nl1OO10iO_dataout; + wire_nl1OO1i_dataout <= n1Oll1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OO1i1i_dataout <= wire_nl1OO1i1O_o(7) WHEN niOi1OlOl = '1' ELSE nl1OO011l; + wire_nl1OO1i1l_dataout <= wire_nl1OO1i1O_o(8) WHEN niOi1OlOl = '1' ELSE nl1OO011O; + wire_nl1OO1il_dataout <= wire_nl1OO1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1OO1iO_dataout <= wire_nl1OO1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nl1OO1l_dataout <= n1Oll0i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OO1li_dataout <= wire_niOOO0O_w_lg_nl1OO10i7684w(0) WHEN (wire_w_lg_niOO1lllO7685w(0) AND wire_w_lg_w_dl_req_phycfg_range7683w7686w(0)) = '1' ELSE nl1OO10i; + wire_nl1OO1O_dataout <= n1Oll0l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OO1Oi_dataout <= nl1OO1ii WHEN niOO1lllO = '1' ELSE dl_req_phycfg(3); + wire_nl1OOi10i_dataout <= wire_nl01110ii_dataout WHEN niOi011il = '1' ELSE nl1OOi00O; + wire_nl1OOi10i_w_lg_dataout56727w(0) <= NOT wire_nl1OOi10i_dataout; + wire_nl1OOi10l_dataout <= wire_nl01110il_dataout WHEN niOi011il = '1' ELSE nl1OOi0ii; + wire_nl1OOi10l_w_lg_dataout56726w(0) <= NOT wire_nl1OOi10l_dataout; + wire_nl1OOi11l_dataout <= nl01l0l0O WHEN niOi011il = '1' ELSE nl1OO010O; + wire_nl1OOi11O_dataout <= nl01l0l0l WHEN niOi011il = '1' ELSE nl1OOi1lO; + wire_nl1OOii_dataout <= n1OlliO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OOil_dataout <= n1Ollli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OOil0i_dataout <= wire_nl1OOl1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOil0l_dataout <= wire_nl1OOl1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOil0O_dataout <= wire_nl1OOlill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOilii_dataout <= wire_nl1OOlilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOilil_dataout <= niOi011OO AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiliO_dataout <= (wire_nlill0Oll_w_lg_nl1OOi1OO54545w(0) AND niOi011iO) AND NOT(wire_niO01O0O_dataout); + wire_nl1OOilli_dataout <= wire_nl1OOllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOilll_dataout <= niOi011ll AND NOT(wire_niO01O0O_dataout); + wire_nl1OOillO_dataout <= wire_nl1OOliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOilOi_dataout <= wire_nl1OOliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOilOl_dataout <= wire_nl1OOl1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOilOO_dataout <= wire_nl1OOl1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiO0i_dataout <= wire_nl1OOl01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiO0l_dataout <= wire_nl1OOl00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiO0O_dataout <= wire_nl1OOl00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiO1i_dataout <= wire_nl1OOl1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiO1l_dataout <= wire_nl1OOl01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiO1O_dataout <= wire_nl1OOl01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOii_dataout <= wire_nl1OOl00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOil_dataout <= wire_nl1OOl0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOiO_dataout <= wire_nl1OOl0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOli_dataout <= wire_nl1OOll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOll_dataout <= wire_nl1OOllli_dataout OR wire_niO01O0O_dataout; + wire_nl1OOiOlO_dataout <= wire_nl1OOllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOOi_dataout <= wire_nl1OOlO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOOl_dataout <= wire_nl1OOlO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOiOOO_dataout <= wire_nl1OOlO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl00i_dataout <= wire_nl1OOli0O_dataout WHEN niOi011li = '1' ELSE nl1OOi0lO; + wire_nl1OOl00l_dataout <= wire_nl1OOliii_dataout WHEN niOi011li = '1' ELSE nl1OOi0Oi; + wire_nl1OOl00O_dataout <= wire_nl1OOliil_dataout WHEN niOi011li = '1' ELSE nl1OOi0Ol; + wire_nl1OOl01i_dataout <= wire_nl1OOli1O_dataout WHEN niOi011li = '1' ELSE nl1OOi0iO; + wire_nl1OOl01l_dataout <= wire_nl1OOli0i_dataout WHEN niOi011li = '1' ELSE nl1OOi0li; + wire_nl1OOl01O_dataout <= wire_nl1OOli0l_dataout WHEN niOi011li = '1' ELSE nl1OOi0ll; + wire_nl1OOl0ii_dataout <= wire_nl1OOliiO_dataout WHEN niOi011li = '1' ELSE nl1OOi0OO; + wire_nl1OOl0il_dataout <= wire_nl1OOlili_dataout WHEN niOi011li = '1' ELSE nl1OOii1i; + wire_nl1OOl0iO_dataout <= nl01l0l0O WHEN nl1OOii1O = '1' ELSE wire_nl1OOl0Oi_dataout; + wire_nl1OOl0li_dataout <= nl01l0l0l WHEN nl1OOii1O = '1' ELSE wire_nl1OOl0Ol_dataout; + wire_nl1OOl0ll_dataout <= wire_nl01110ii_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1OOl0OO_dataout; + wire_nl1OOl0lO_dataout <= wire_nl01110il_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1OOli1i_dataout; + wire_nl1OOl0Oi_dataout <= nl1OOi1Oi WHEN nl1OOi01O = '1' ELSE wire_nl1ii10OO_q(12); + wire_nl1OOl0Ol_dataout <= nl1OOi1Ol WHEN nl1OOi01O = '1' ELSE wire_nl1ii10OO_q(11); + wire_nl1OOl0OO_dataout <= nl1OOi00i WHEN nl1OOi01O = '1' ELSE wire_nl1ii10OO_q(9); + wire_nl1OOl10i_dataout <= wire_nl1OOlOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl10l_dataout <= wire_nl1OOlOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl10O_dataout <= wire_nl1OOlOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl11i_dataout <= wire_nl1OOlO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl11l_dataout <= wire_nl1OOlO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl11O_dataout <= wire_nl1OOlO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl1ii_dataout <= wire_nl1OOlOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl1il_dataout <= wire_nl1OOlOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl1iO_dataout <= wire_nl1OOlOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl1li_dataout <= wire_nl1OOlOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOl1ll_dataout <= wire_nl1OOl0iO_dataout WHEN niOi011li = '1' ELSE nl1OO010O; + wire_nl1OOl1lO_dataout <= wire_nl1OOl0li_dataout WHEN niOi011li = '1' ELSE nl1OOi1lO; + wire_nl1OOl1Oi_dataout <= wire_nl1OOl0ll_dataout WHEN niOi011li = '1' ELSE nl1OOi00O; + wire_nl1OOl1Ol_dataout <= wire_nl1OOl0lO_dataout WHEN niOi011li = '1' ELSE nl1OOi0ii; + wire_nl1OOl1OO_dataout <= wire_nl1OOli1l_dataout WHEN niOi011li = '1' ELSE nl1OOi0il; + wire_nl1OOli0i_dataout <= wire_nl01110OO_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(2); + wire_nl1OOli0l_dataout <= wire_nl0111i1i_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(3); + wire_nl1OOli0O_dataout <= wire_nl0111i1l_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(4); + wire_nl1OOli1i_dataout <= nl1OOi00l WHEN nl1OOi01O = '1' ELSE wire_nl1ii10OO_q(10); + wire_nl1OOli1l_dataout <= wire_nl01110Oi_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(0); + wire_nl1OOli1O_dataout <= wire_nl01110Ol_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(1); + wire_nl1OOliii_dataout <= wire_nl0111i1O_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(5); + wire_nl1OOliil_dataout <= wire_nl0111i0i_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(6); + wire_nl1OOliiO_dataout <= wire_nl0111i0l_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(7); + wire_nl1OOlili_dataout <= wire_nl0111i0O_dataout WHEN nl1OOii1O = '1' ELSE wire_nl1ii10OO_q(8); + wire_nl1OOlill_dataout <= nl01l0l0O WHEN niOi011ll = '1' ELSE nl1OOi1Oi; + wire_nl1OOlilO_dataout <= nl01l0l0l WHEN niOi011ll = '1' ELSE nl1OOi1Ol; + wire_nl1OOliOi_dataout <= wire_nl01110ii_dataout WHEN niOi011ll = '1' ELSE nl1OOi00i; + wire_nl1OOliOl_dataout <= wire_nl01110il_dataout WHEN niOi011ll = '1' ELSE nl1OOi00l; + wire_nl1OOll1i_dataout <= wire_nl1OOll1l_dataout AND NOT((((wire_nl011Ol1l_w_lg_dataout54516w(0) AND (nl1OOii1O AND niOi011Oi)) AND wire_nlill0Oll_w_lg_nl1OOi01l54523w(0)) OR (nl1OOi01l AND niOi011Oi))); + wire_nl1OOll1l_dataout <= nl1OOii1l OR ((wire_nlill0Oll_w_lg_nl1OOi01l54523w(0) AND niOi011OO) OR niOi0101i); + wire_nl1OOllli_dataout <= wire_nl1OOllll_dataout AND NOT(((wire_nl011Ol1l_dataout AND wire_w_lg_niOi011OO54520w(0)) AND nl1OOii1O)); + wire_nl1OOllll_dataout <= nl1OOii1O OR ((wire_nliliO10i_w_lg_nl1OOii1O54515w(0) AND wire_nl011Ol1l_w_lg_w_lg_dataout54516w54517w(0)) AND niOi011Ol); + wire_nl1OOllOl_dataout <= wire_nl1OOO11i_dataout AND NOT(niOi011OO); + wire_nl1OOllOO_dataout <= wire_nl1OOlOii_o(0) WHEN niOi011OO = '1' ELSE nl1OOii0i; + wire_nl1OOlO0i_dataout <= wire_nl1OOlOii_o(4) WHEN niOi011OO = '1' ELSE nl1OOiiil; + wire_nl1OOlO0l_dataout <= wire_nl1OOlOii_o(5) WHEN niOi011OO = '1' ELSE nl1OOiiiO; + wire_nl1OOlO0O_dataout <= wire_nl1OOlOii_o(6) WHEN niOi011OO = '1' ELSE nl1OOiili; + wire_nl1OOlO1i_dataout <= wire_nl1OOlOii_o(1) WHEN niOi011OO = '1' ELSE nl1OOii0l; + wire_nl1OOlO1l_dataout <= wire_nl1OOlOii_o(2) WHEN niOi011OO = '1' ELSE nl1OOii0O; + wire_nl1OOlO1O_dataout <= wire_nl1OOlOii_o(3) WHEN niOi011OO = '1' ELSE nl1OOiiii; + wire_nl1OOlOil_dataout <= wire_nl1OOlOOO_o(0) WHEN wire_nl011Ol1l_dataout = '1' ELSE nl1OOiill; + wire_nl1OOlOiO_dataout <= wire_nl1OOlOOO_o(1) WHEN wire_nl011Ol1l_dataout = '1' ELSE nl1OOiilO; + wire_nl1OOlOli_dataout <= wire_nl1OOlOOO_o(2) WHEN wire_nl011Ol1l_dataout = '1' ELSE nl1OOiiOi; + wire_nl1OOlOll_dataout <= wire_nl1OOlOOO_o(3) WHEN wire_nl011Ol1l_dataout = '1' ELSE nl1OOiiOl; + wire_nl1OOlOlO_dataout <= wire_nl1OOlOOO_o(4) WHEN wire_nl011Ol1l_dataout = '1' ELSE nl1OOiiOO; + wire_nl1OOlOOi_dataout <= wire_nl1OOlOOO_o(5) WHEN wire_nl011Ol1l_dataout = '1' ELSE nl1OOil1i; + wire_nl1OOlOOl_dataout <= wire_nl1OOlOOO_o(6) WHEN wire_nl011Ol1l_dataout = '1' ELSE nl1OOil1l; + wire_nl1OOO00i_dataout <= k_ptr0(6) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(5); + wire_nl1OOO00l_dataout <= k_ptr0(7) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(6); + wire_nl1OOO00O_dataout <= k_ptr0(8) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(7); + wire_nl1OOO01i_dataout <= k_ptr0(3) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(2); + wire_nl1OOO01l_dataout <= k_ptr0(4) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(3); + wire_nl1OOO01O_dataout <= k_ptr0(5) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(4); + wire_nl1OOO0li_dataout <= k_ptr0(0) WHEN niOi0100i = '1' ELSE wire_nl1OOOi0i_dataout; + wire_nl1OOO0ll_dataout <= k_ptr0(1) WHEN niOi0100i = '1' ELSE wire_nl1OOOi0l_dataout; + wire_nl1OOO0lO_dataout <= k_ptr0(2) WHEN niOi0100i = '1' ELSE wire_nl1OOOi0O_dataout; + wire_nl1OOO0Oi_dataout <= k_ptr0(3) WHEN niOi0100i = '1' ELSE wire_nl1OOOiii_dataout; + wire_nl1OOO0Ol_dataout <= k_ptr0(4) WHEN niOi0100i = '1' ELSE wire_nl1OOOiil_dataout; + wire_nl1OOO0OO_dataout <= k_ptr0(5) WHEN niOi0100i = '1' ELSE wire_nl1OOOiiO_dataout; + wire_nl1OOO10i_dataout <= wire_nl1OOO0iO_o(0) WHEN niOi0100l = '1' ELSE wire_nl1OOO1Oi_dataout; + wire_nl1OOO10l_dataout <= wire_nl1OOO0iO_o(1) WHEN niOi0100l = '1' ELSE wire_nl1OOO1Ol_dataout; + wire_nl1OOO10O_dataout <= wire_nl1OOO0iO_o(2) WHEN niOi0100l = '1' ELSE wire_nl1OOO1OO_dataout; + wire_nl1OOO11i_dataout <= nl1OOi01l OR niOi0101i; + wire_nl1OOO1ii_dataout <= wire_nl1OOO0iO_o(3) WHEN niOi0100l = '1' ELSE wire_nl1OOO01i_dataout; + wire_nl1OOO1il_dataout <= wire_nl1OOO0iO_o(4) WHEN niOi0100l = '1' ELSE wire_nl1OOO01l_dataout; + wire_nl1OOO1iO_dataout <= wire_nl1OOO0iO_o(5) WHEN niOi0100l = '1' ELSE wire_nl1OOO01O_dataout; + wire_nl1OOO1li_dataout <= wire_nl1OOO0iO_o(6) WHEN niOi0100l = '1' ELSE wire_nl1OOO00i_dataout; + wire_nl1OOO1ll_dataout <= wire_nl1OOO0iO_o(7) WHEN niOi0100l = '1' ELSE wire_nl1OOO00l_dataout; + wire_nl1OOO1lO_dataout <= wire_nl1OOO0iO_o(8) WHEN niOi0100l = '1' ELSE wire_nl1OOO00O_dataout; + wire_nl1OOO1Oi_dataout <= k_ptr0(0) WHEN niOi0101l = '1' ELSE wire_nl011110i_dataout; + wire_nl1OOO1Ol_dataout <= k_ptr0(1) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(0); + wire_nl1OOO1OO_dataout <= k_ptr0(2) WHEN niOi0101l = '1' ELSE wire_nl1OOO0ii_o(1); + wire_nl1OOOi_dataout <= n1O0Oli AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OOOi0i_dataout <= wire_nl1OOOiOi_o(0) WHEN niOi0101O = '1' ELSE wire_nl011110i_dataout; + wire_nl1OOOi0l_dataout <= wire_nl1OOOiOi_o(1) WHEN niOi0101O = '1' ELSE wire_nl011110l_dataout; + wire_nl1OOOi0O_dataout <= wire_nl1OOOiOi_o(2) WHEN niOi0101O = '1' ELSE wire_nl011110O_dataout; + wire_nl1OOOi1i_dataout <= k_ptr0(6) WHEN niOi0100i = '1' ELSE wire_nl1OOOili_dataout; + wire_nl1OOOi1l_dataout <= k_ptr0(7) WHEN niOi0100i = '1' ELSE wire_nl1OOOill_dataout; + wire_nl1OOOi1O_dataout <= k_ptr0(8) WHEN niOi0100i = '1' ELSE wire_nl1OOOilO_dataout; + wire_nl1OOOiii_dataout <= wire_nl1OOOiOi_o(3) WHEN niOi0101O = '1' ELSE wire_nl01111ii_dataout; + wire_nl1OOOiil_dataout <= wire_nl1OOOiOi_o(4) WHEN niOi0101O = '1' ELSE wire_nl01111il_dataout; + wire_nl1OOOiiO_dataout <= wire_nl1OOOiOi_o(5) WHEN niOi0101O = '1' ELSE wire_nl01111iO_dataout; + wire_nl1OOOili_dataout <= wire_nl1OOOiOi_o(6) WHEN niOi0101O = '1' ELSE wire_nl01111li_dataout; + wire_nl1OOOill_dataout <= wire_nl1OOOiOi_o(7) WHEN niOi0101O = '1' ELSE wire_nl01111ll_dataout; + wire_nl1OOOilO_dataout <= wire_nl1OOOiOi_o(8) WHEN niOi0101O = '1' ELSE wire_nl01111lO_dataout; + wire_nl1OOOl_dataout <= n1O0Oll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OOOl0i_dataout <= k_ptr0(2) WHEN niOi010iO = '1' ELSE wire_nl1OOOlOi_dataout; + wire_nl1OOOl0l_dataout <= k_ptr0(3) WHEN niOi010iO = '1' ELSE wire_nl1OOOlOl_dataout; + wire_nl1OOOl0O_dataout <= k_ptr0(4) WHEN niOi010iO = '1' ELSE wire_nl1OOOlOO_dataout; + wire_nl1OOOl1l_dataout <= k_ptr0(0) WHEN niOi010iO = '1' ELSE wire_nl1OOOlll_dataout; + wire_nl1OOOl1O_dataout <= k_ptr0(1) WHEN niOi010iO = '1' ELSE wire_nl1OOOllO_dataout; + wire_nl1OOOli_dataout <= wire_nl0110ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOOlii_dataout <= k_ptr0(5) WHEN niOi010iO = '1' ELSE wire_nl1OOOO1i_dataout; + wire_nl1OOOlil_dataout <= k_ptr0(6) WHEN niOi010iO = '1' ELSE wire_nl1OOOO1l_dataout; + wire_nl1OOOliO_dataout <= k_ptr0(7) WHEN niOi010iO = '1' ELSE wire_nl1OOOO1O_dataout; + wire_nl1OOOll_dataout <= wire_nl0110il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOOlli_dataout <= k_ptr0(8) WHEN niOi010iO = '1' ELSE wire_nl1OOOO0i_dataout; + wire_nl1OOOlll_dataout <= k_ptr0(18) WHEN niOi010ii = '1' ELSE wire_nl1OOOO0l_dataout; + wire_nl1OOOllO_dataout <= k_ptr0(19) WHEN niOi010ii = '1' ELSE wire_nl1OOOO0O_dataout; + wire_nl1OOOlO_dataout <= wire_nl0110iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOOlOi_dataout <= k_ptr0(20) WHEN niOi010ii = '1' ELSE wire_nl1OOOOii_dataout; + wire_nl1OOOlOl_dataout <= k_ptr0(21) WHEN niOi010ii = '1' ELSE wire_nl1OOOOil_dataout; + wire_nl1OOOlOO_dataout <= k_ptr0(22) WHEN niOi010ii = '1' ELSE wire_nl1OOOOiO_dataout; + wire_nl1OOOO_dataout <= n1O0OlO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nl1OOOO0i_dataout <= k_ptr0(26) WHEN niOi010ii = '1' ELSE wire_nl1OOOOOi_dataout; + wire_nl1OOOO0l_dataout <= wire_nl1OOOOOl_o(0) WHEN niOi0100O = '1' ELSE wire_nl01111Oi_dataout; + wire_nl1OOOO0O_dataout <= wire_nl1OOOOOl_o(1) WHEN niOi0100O = '1' ELSE wire_nl01111Ol_dataout; + wire_nl1OOOO1i_dataout <= k_ptr0(23) WHEN niOi010ii = '1' ELSE wire_nl1OOOOli_dataout; + wire_nl1OOOO1l_dataout <= k_ptr0(24) WHEN niOi010ii = '1' ELSE wire_nl1OOOOll_dataout; + wire_nl1OOOO1O_dataout <= k_ptr0(25) WHEN niOi010ii = '1' ELSE wire_nl1OOOOlO_dataout; + wire_nl1OOOOi_dataout <= wire_nl0110li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOOOii_dataout <= wire_nl1OOOOOl_o(2) WHEN niOi0100O = '1' ELSE wire_nl01111OO_dataout; + wire_nl1OOOOil_dataout <= wire_nl1OOOOOl_o(3) WHEN niOi0100O = '1' ELSE wire_nl011101i_dataout; + wire_nl1OOOOiO_dataout <= wire_nl1OOOOOl_o(4) WHEN niOi0100O = '1' ELSE wire_nl011101l_dataout; + wire_nl1OOOOl_dataout <= wire_nl0110ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOOOli_dataout <= wire_nl1OOOOOl_o(5) WHEN niOi0100O = '1' ELSE wire_nl011101O_dataout; + wire_nl1OOOOll_dataout <= wire_nl1OOOOOl_o(6) WHEN niOi0100O = '1' ELSE wire_nl011100i_dataout; + wire_nl1OOOOlO_dataout <= wire_nl1OOOOOl_o(7) WHEN niOi0100O = '1' ELSE wire_nl011100l_dataout; + wire_nl1OOOOO_dataout <= wire_nl0110lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nl1OOOOOi_dataout <= wire_nl1OOOOOl_o(8) WHEN niOi0100O = '1' ELSE wire_nl011100O_dataout; + wire_nli0000i_dataout <= wire_nli0li0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0000l_dataout <= wire_nli0li0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0000O_dataout <= wire_nli0liii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0001i_dataout <= wire_nli0li1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0001l_dataout <= wire_nli0li1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0001O_dataout <= wire_nli0li0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000ii_dataout <= wire_nli0liil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000il_dataout <= wire_nli0liiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000iO_dataout <= wire_nli0lili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000li_dataout <= wire_nli0lill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000ll_dataout <= wire_nli0lilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000lO_dataout <= wire_nli0liOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000Oi_dataout <= wire_nli0liOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000Ol_dataout <= wire_nli0liOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000Oli_dataout <= (NOT k_conf(308)) OR NOT(nl0iOiOli); + wire_nli000Oli_w_lg_dataout47728w(0) <= wire_nli000Oli_dataout AND wire_nli00i0lO_w_lg_dataout47727w(0); + wire_nli000Oli_w_lg_w_lg_dataout47728w47729w(0) <= NOT wire_nli000Oli_w_lg_dataout47728w(0); + wire_nli000Oll_dataout <= (NOT k_conf(309)) OR NOT(nl0iOiOli); + wire_nli000Oll_w_lg_dataout47689w(0) <= wire_nli000Oll_dataout AND wire_nli00li1O_w_lg_dataout47688w(0); + wire_nli000Oll_w_lg_w_lg_dataout47689w47690w(0) <= NOT wire_nli000Oll_w_lg_dataout47689w(0); + wire_nli000OlO_dataout <= (NOT k_conf(310)) OR NOT(nl0iOiOli); + wire_nli000OlO_w_lg_dataout47655w(0) <= wire_nli000OlO_dataout AND wire_nli00i0Oi_w_lg_dataout47654w(0); + wire_nli000OlO_w_lg_w_lg_dataout47655w47656w(0) <= NOT wire_nli000OlO_w_lg_dataout47655w(0); + wire_nli000OO_dataout <= wire_nli0ll1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli000OOi_dataout <= (NOT k_conf(311)) OR NOT(nl0iOiOli); + wire_nli000OOi_w_lg_dataout47621w(0) <= wire_nli000OOi_dataout AND wire_nli00i0Ol_w_lg_dataout47620w(0); + wire_nli000OOi_w_lg_w_lg_dataout47621w47622w(0) <= NOT wire_nli000OOi_w_lg_dataout47621w(0); + wire_nli000OOl_dataout <= (NOT k_conf(312)) OR NOT(nl0iOiOli); + wire_nli000OOl_w_lg_dataout47587w(0) <= wire_nli000OOl_dataout AND wire_nli00li0O_w_lg_dataout47586w(0); + wire_nli000OOl_w_lg_w_lg_dataout47587w47588w(0) <= NOT wire_nli000OOl_w_lg_dataout47587w(0); + wire_nli000OOO_dataout <= (NOT k_conf(313)) OR NOT(nl0iOiOli); + wire_nli000OOO_w_lg_dataout47553w(0) <= wire_nli000OOO_dataout AND wire_nli00liii_w_lg_dataout47552w(0); + wire_nli000OOO_w_lg_w_lg_dataout47553w47554w(0) <= NOT wire_nli000OOO_w_lg_dataout47553w(0); + wire_nli0010i_dataout <= wire_nli0l1ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0010l_dataout <= wire_nli0l00O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0010O_dataout <= wire_nli0l0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0011i_dataout <= wire_nli0l1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0011l_dataout <= wire_nli0l1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0011O_dataout <= wire_nli0l1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001ii_dataout <= wire_nli0l0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001il_dataout <= wire_nli0l0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001iO_dataout <= wire_nli0l0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001li_dataout <= wire_nli0l0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001ll_dataout <= wire_nli0l0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001lO_dataout <= wire_nli0l0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001Oi_dataout <= wire_nli0l0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001Ol_dataout <= wire_nli0l0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli001OO_dataout <= wire_nli0li1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00i00i_dataout <= (NOT k_conf(332)) OR NOT(nl0iOiOli); + wire_nli00i00i_w_lg_dataout46968w(0) <= wire_nli00i00i_dataout AND wire_nli00O0il_w_lg_dataout46967w(0); + wire_nli00i00i_w_lg_w_lg_dataout46968w46969w(0) <= NOT wire_nli00i00i_w_lg_dataout46968w(0); + wire_nli00i00l_dataout <= (NOT k_conf(333)) OR NOT(nl0iOiOli); + wire_nli00i00l_w_lg_dataout46938w(0) <= wire_nli00i00l_dataout AND wire_nli00Ol0i_w_lg_dataout46937w(0); + wire_nli00i00l_w_lg_w_lg_dataout46938w46939w(0) <= NOT wire_nli00i00l_w_lg_dataout46938w(0); + wire_nli00i00O_dataout <= (NOT k_conf(334)) OR NOT(nl0iOiOli); + wire_nli00i00O_w_lg_dataout46909w(0) <= wire_nli00i00O_dataout AND wire_nli00Ol0l_w_lg_dataout46908w(0); + wire_nli00i00O_w_lg_w_lg_dataout46909w46910w(0) <= NOT wire_nli00i00O_w_lg_dataout46909w(0); + wire_nli00i01i_dataout <= (NOT k_conf(329)) OR NOT(nl0iOiOli); + wire_nli00i01i_w_lg_dataout47055w(0) <= wire_nli00i01i_dataout AND wire_nli00O00l_w_lg_dataout47054w(0); + wire_nli00i01i_w_lg_w_lg_dataout47055w47056w(0) <= NOT wire_nli00i01i_w_lg_dataout47055w(0); + wire_nli00i01l_dataout <= (NOT k_conf(330)) OR NOT(nl0iOiOli); + wire_nli00i01l_w_lg_dataout47025w(0) <= wire_nli00i01l_dataout AND wire_nli00O00O_w_lg_dataout47024w(0); + wire_nli00i01l_w_lg_w_lg_dataout47025w47026w(0) <= NOT wire_nli00i01l_w_lg_dataout47025w(0); + wire_nli00i01O_dataout <= (NOT k_conf(331)) OR NOT(nl0iOiOli); + wire_nli00i01O_w_lg_dataout46996w(0) <= wire_nli00i01O_dataout AND wire_nli00O0ii_w_lg_dataout46995w(0); + wire_nli00i01O_w_lg_w_lg_dataout46996w46997w(0) <= NOT wire_nli00i01O_w_lg_dataout46996w(0); + wire_nli00i0i_dataout <= wire_nli0ll0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00i0ii_dataout <= (NOT k_conf(335)) OR NOT(nl0iOiOli); + wire_nli00i0ii_w_lg_dataout46881w(0) <= wire_nli00i0ii_dataout AND wire_nli00Ol0O_w_lg_dataout46880w(0); + wire_nli00i0ii_w_lg_w_lg_dataout46881w46882w(0) <= NOT wire_nli00i0ii_w_lg_dataout46881w(0); + wire_nli00i0il_dataout <= (NOT k_conf(336)) OR NOT(nl0iOiOli); + wire_nli00i0il_w_lg_dataout46853w(0) <= wire_nli00i0il_dataout AND wire_nli00Olii_w_lg_dataout46852w(0); + wire_nli00i0il_w_lg_w_lg_dataout46853w46854w(0) <= NOT wire_nli00i0il_w_lg_dataout46853w(0); + wire_nli00i0iO_dataout <= (NOT k_conf(337)) OR NOT(nl0iOiOli); + wire_nli00i0iO_w_lg_dataout46826w(0) <= wire_nli00i0iO_dataout AND wire_nli00Olil_w_lg_dataout46825w(0); + wire_nli00i0iO_w_lg_w_lg_dataout46826w46827w(0) <= NOT wire_nli00i0iO_w_lg_dataout46826w(0); + wire_nli00i0l_dataout <= wire_nli0ll0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00i0li_dataout <= (NOT k_conf(338)) OR NOT(nl0iOiOli); + wire_nli00i0li_w_lg_dataout46799w(0) <= wire_nli00i0li_dataout AND wire_nli00OliO_w_lg_dataout46798w(0); + wire_nli00i0li_w_lg_w_lg_dataout46799w46800w(0) <= NOT wire_nli00i0li_w_lg_dataout46799w(0); + wire_nli00i0ll_dataout <= (NOT k_conf(339)) OR NOT(nl0iOiOli); + wire_nli00i0ll_w_lg_dataout46772w(0) <= wire_nli00i0ll_dataout AND wire_nli00Olli_w_lg_dataout46771w(0); + wire_nli00i0ll_w_lg_w_lg_dataout46772w46773w(0) <= NOT wire_nli00i0ll_w_lg_dataout46772w(0); + wire_nli00i0lO_dataout <= (NOT k_conf(307)) OR NOT(nl0iOiOiO); + wire_nli00i0lO_w_lg_dataout47727w(0) <= wire_nli00i0lO_dataout AND wire_nli00li1l_w_lg_dataout47726w(0); + wire_nli00i0O_dataout <= wire_nli0llii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00i0Oi_dataout <= (NOT k_conf(307)) OR NOT(nl0iOiOiO); + wire_nli00i0Oi_w_lg_dataout47654w(0) <= wire_nli00i0Oi_dataout AND wire_nli00li0i_w_lg_dataout47653w(0); + wire_nli00i0Ol_dataout <= (NOT k_conf(307)) OR NOT(nl0iOiOiO); + wire_nli00i0Ol_w_lg_dataout47620w(0) <= wire_nli00i0Ol_dataout AND wire_nli00li0l_w_lg_dataout47619w(0); + wire_nli00i0OO_dataout <= (NOT k_conf(231)) OR NOT(nl0iOl11i); + wire_nli00i0OO_w_lg_dataout47714w(0) <= wire_nli00i0OO_dataout AND wire_nli00iO1l_w_lg_dataout47713w(0); + wire_nli00i0OO_w_lg_w_lg_dataout47714w47715w(0) <= NOT wire_nli00i0OO_w_lg_dataout47714w(0); + wire_nli00i10i_dataout <= (NOT k_conf(317)) OR NOT(nl0iOiOli); + wire_nli00i10i_w_lg_dataout47426w(0) <= wire_nli00i10i_dataout AND wire_nli00lill_w_lg_dataout47425w(0); + wire_nli00i10i_w_lg_w_lg_dataout47426w47427w(0) <= NOT wire_nli00i10i_w_lg_dataout47426w(0); + wire_nli00i10l_dataout <= (NOT k_conf(318)) OR NOT(nl0iOiOli); + wire_nli00i10l_w_lg_dataout47397w(0) <= wire_nli00i10l_dataout AND wire_nli00lilO_w_lg_dataout47396w(0); + wire_nli00i10l_w_lg_w_lg_dataout47397w47398w(0) <= NOT wire_nli00i10l_w_lg_dataout47397w(0); + wire_nli00i10O_dataout <= (NOT k_conf(319)) OR NOT(nl0iOiOli); + wire_nli00i10O_w_lg_dataout47366w(0) <= wire_nli00i10O_dataout AND wire_nli00liOi_w_lg_dataout47365w(0); + wire_nli00i10O_w_lg_w_lg_dataout47366w47367w(0) <= NOT wire_nli00i10O_w_lg_dataout47366w(0); + wire_nli00i11i_dataout <= (NOT k_conf(314)) OR NOT(nl0iOiOli); + wire_nli00i11i_w_lg_dataout47522w(0) <= wire_nli00i11i_dataout AND wire_nli00liil_w_lg_dataout47521w(0); + wire_nli00i11i_w_lg_w_lg_dataout47522w47523w(0) <= NOT wire_nli00i11i_w_lg_dataout47522w(0); + wire_nli00i11l_dataout <= (NOT k_conf(315)) OR NOT(nl0iOiOli); + wire_nli00i11l_w_lg_dataout47488w(0) <= wire_nli00i11l_dataout AND wire_nli00liiO_w_lg_dataout47487w(0); + wire_nli00i11l_w_lg_w_lg_dataout47488w47489w(0) <= NOT wire_nli00i11l_w_lg_dataout47488w(0); + wire_nli00i11O_dataout <= (NOT k_conf(316)) OR NOT(nl0iOiOli); + wire_nli00i11O_w_lg_dataout47458w(0) <= wire_nli00i11O_dataout AND wire_nli00lili_w_lg_dataout47457w(0); + wire_nli00i11O_w_lg_w_lg_dataout47458w47459w(0) <= NOT wire_nli00i11O_w_lg_dataout47458w(0); + wire_nli00i1i_dataout <= wire_nli0ll1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00i1ii_dataout <= (NOT k_conf(320)) OR NOT(nl0iOiOli); + wire_nli00i1ii_w_lg_dataout47335w(0) <= wire_nli00i1ii_dataout AND wire_nli00liOl_w_lg_dataout47334w(0); + wire_nli00i1ii_w_lg_w_lg_dataout47335w47336w(0) <= NOT wire_nli00i1ii_w_lg_dataout47335w(0); + wire_nli00i1il_dataout <= (NOT k_conf(321)) OR NOT(nl0iOiOli); + wire_nli00i1il_w_lg_dataout47304w(0) <= wire_nli00i1il_dataout AND wire_nli00lOiO_w_lg_dataout47303w(0); + wire_nli00i1il_w_lg_w_lg_dataout47304w47305w(0) <= NOT wire_nli00i1il_w_lg_dataout47304w(0); + wire_nli00i1iO_dataout <= (NOT k_conf(322)) OR NOT(nl0iOiOli); + wire_nli00i1iO_w_lg_dataout47274w(0) <= wire_nli00i1iO_dataout AND wire_nli00lOli_w_lg_dataout47273w(0); + wire_nli00i1iO_w_lg_w_lg_dataout47274w47275w(0) <= NOT wire_nli00i1iO_w_lg_dataout47274w(0); + wire_nli00i1l_dataout <= wire_nli0ll1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00i1li_dataout <= (NOT k_conf(323)) OR NOT(nl0iOiOli); + wire_nli00i1li_w_lg_dataout47241w(0) <= wire_nli00i1li_dataout AND wire_nli00lOll_w_lg_dataout47240w(0); + wire_nli00i1li_w_lg_w_lg_dataout47241w47242w(0) <= NOT wire_nli00i1li_w_lg_dataout47241w(0); + wire_nli00i1ll_dataout <= (NOT k_conf(324)) OR NOT(nl0iOiOli); + wire_nli00i1ll_w_lg_dataout47212w(0) <= wire_nli00i1ll_dataout AND wire_nli00liOO_w_lg_dataout47211w(0); + wire_nli00i1ll_w_lg_w_lg_dataout47212w47213w(0) <= NOT wire_nli00i1ll_w_lg_dataout47212w(0); + wire_nli00i1lO_dataout <= (NOT k_conf(325)) OR NOT(nl0iOiOli); + wire_nli00i1lO_w_lg_dataout47179w(0) <= wire_nli00i1lO_dataout AND wire_nli00lOOi_w_lg_dataout47178w(0); + wire_nli00i1lO_w_lg_w_lg_dataout47179w47180w(0) <= NOT wire_nli00i1lO_w_lg_dataout47179w(0); + wire_nli00i1O_dataout <= wire_nli0ll0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00i1Oi_dataout <= (NOT k_conf(326)) OR NOT(nl0iOiOli); + wire_nli00i1Oi_w_lg_dataout47147w(0) <= wire_nli00i1Oi_dataout AND wire_nli00O01l_w_lg_dataout47146w(0); + wire_nli00i1Oi_w_lg_w_lg_dataout47147w47148w(0) <= NOT wire_nli00i1Oi_w_lg_dataout47147w(0); + wire_nli00i1Ol_dataout <= (NOT k_conf(327)) OR NOT(nl0iOiOli); + wire_nli00i1Ol_w_lg_dataout47119w(0) <= wire_nli00i1Ol_dataout AND wire_nli00O01O_w_lg_dataout47118w(0); + wire_nli00i1Ol_w_lg_w_lg_dataout47119w47120w(0) <= NOT wire_nli00i1Ol_w_lg_dataout47119w(0); + wire_nli00i1OO_dataout <= (NOT k_conf(328)) OR NOT(nl0iOiOli); + wire_nli00i1OO_w_lg_dataout47088w(0) <= wire_nli00i1OO_dataout AND wire_nli00O00i_w_lg_dataout47087w(0); + wire_nli00i1OO_w_lg_w_lg_dataout47088w47089w(0) <= NOT wire_nli00i1OO_w_lg_dataout47088w(0); + wire_nli00ii0i_dataout <= (NOT k_conf(235)) OR NOT(nl0iOl11i); + wire_nli00ii0i_w_lg_dataout47575w(0) <= wire_nli00ii0i_dataout AND wire_nli00iO0O_w_lg_dataout47574w(0); + wire_nli00ii0i_w_lg_w_lg_dataout47575w47576w(0) <= NOT wire_nli00ii0i_w_lg_dataout47575w(0); + wire_nli00ii0l_dataout <= (NOT k_conf(236)) OR NOT(nl0iOl11i); + wire_nli00ii0l_w_lg_dataout47544w(0) <= wire_nli00ii0l_dataout AND wire_nli00iOii_w_lg_dataout47543w(0); + wire_nli00ii0l_w_lg_w_lg_dataout47544w47545w(0) <= NOT wire_nli00ii0l_w_lg_dataout47544w(0); + wire_nli00ii0O_dataout <= (NOT k_conf(237)) OR NOT(nl0iOl11i); + wire_nli00ii0O_w_lg_dataout47512w(0) <= wire_nli00ii0O_dataout AND wire_nli00iOil_w_lg_dataout47511w(0); + wire_nli00ii0O_w_lg_w_lg_dataout47512w47513w(0) <= NOT wire_nli00ii0O_w_lg_dataout47512w(0); + wire_nli00ii1i_dataout <= (NOT k_conf(232)) OR NOT(nl0iOl11i); + wire_nli00ii1i_w_lg_dataout47676w(0) <= wire_nli00ii1i_dataout AND wire_nli00iO1O_w_lg_dataout47675w(0); + wire_nli00ii1i_w_lg_w_lg_dataout47676w47677w(0) <= NOT wire_nli00ii1i_w_lg_dataout47676w(0); + wire_nli00ii1l_dataout <= (NOT k_conf(233)) OR NOT(nl0iOl11i); + wire_nli00ii1l_w_lg_dataout47643w(0) <= wire_nli00ii1l_dataout AND wire_nli00iO0i_w_lg_dataout47642w(0); + wire_nli00ii1l_w_lg_w_lg_dataout47643w47644w(0) <= NOT wire_nli00ii1l_w_lg_dataout47643w(0); + wire_nli00ii1O_dataout <= (NOT k_conf(234)) OR NOT(nl0iOl11i); + wire_nli00ii1O_w_lg_dataout47609w(0) <= wire_nli00ii1O_dataout AND wire_nli00iO0l_w_lg_dataout47608w(0); + wire_nli00ii1O_w_lg_w_lg_dataout47609w47610w(0) <= NOT wire_nli00ii1O_w_lg_dataout47609w(0); + wire_nli00iii_dataout <= wire_nli0llil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00iiii_dataout <= (NOT k_conf(238)) OR NOT(nl0iOl11i); + wire_nli00iiii_w_lg_dataout47478w(0) <= wire_nli00iiii_dataout AND wire_nli00iOiO_w_lg_dataout47477w(0); + wire_nli00iiii_w_lg_w_lg_dataout47478w47479w(0) <= NOT wire_nli00iiii_w_lg_dataout47478w(0); + wire_nli00iiil_dataout <= (NOT k_conf(239)) OR NOT(nl0iOl11i); + wire_nli00iiil_w_lg_dataout47448w(0) <= wire_nli00iiil_dataout AND wire_nli00iOli_w_lg_dataout47447w(0); + wire_nli00iiil_w_lg_w_lg_dataout47448w47449w(0) <= NOT wire_nli00iiil_w_lg_dataout47448w(0); + wire_nli00iiiO_dataout <= (NOT k_conf(240)) OR NOT(nl0iOl11i); + wire_nli00iiiO_w_lg_dataout47417w(0) <= wire_nli00iiiO_dataout AND wire_nli00iOll_w_lg_dataout47416w(0); + wire_nli00iiiO_w_lg_w_lg_dataout47417w47418w(0) <= NOT wire_nli00iiiO_w_lg_dataout47417w(0); + wire_nli00iil_dataout <= wire_nli0lliO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00iili_dataout <= (NOT k_conf(241)) OR NOT(nl0iOl11i); + wire_nli00iili_w_lg_dataout47387w(0) <= wire_nli00iili_dataout AND wire_nli00iOlO_w_lg_dataout47386w(0); + wire_nli00iili_w_lg_w_lg_dataout47387w47388w(0) <= NOT wire_nli00iili_w_lg_dataout47387w(0); + wire_nli00iill_dataout <= (NOT k_conf(242)) OR NOT(nl0iOl11i); + wire_nli00iill_w_lg_dataout47357w(0) <= wire_nli00iill_dataout AND wire_nli00iOOi_w_lg_dataout47356w(0); + wire_nli00iill_w_lg_w_lg_dataout47357w47358w(0) <= NOT wire_nli00iill_w_lg_dataout47357w(0); + wire_nli00iilO_dataout <= (NOT k_conf(243)) OR NOT(nl0iOl11i); + wire_nli00iilO_w_lg_dataout47326w(0) <= wire_nli00iilO_dataout AND wire_nli00iOOl_w_lg_dataout47325w(0); + wire_nli00iilO_w_lg_w_lg_dataout47326w47327w(0) <= NOT wire_nli00iilO_w_lg_dataout47326w(0); + wire_nli00iiO_dataout <= wire_nli0llli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00iiOi_dataout <= (NOT k_conf(244)) OR NOT(nl0iOl11i); + wire_nli00iiOi_w_lg_dataout47297w(0) <= wire_nli00iiOi_dataout AND wire_nli00iOOO_w_lg_dataout47296w(0); + wire_nli00iiOi_w_lg_w_lg_dataout47297w47298w(0) <= NOT wire_nli00iiOi_w_lg_dataout47297w(0); + wire_nli00iiOl_dataout <= (NOT k_conf(245)) OR NOT(nl0iOl11i); + wire_nli00iiOl_w_lg_dataout47266w(0) <= wire_nli00iiOl_dataout AND wire_nli00l11i_w_lg_dataout47265w(0); + wire_nli00iiOl_w_lg_w_lg_dataout47266w47267w(0) <= NOT wire_nli00iiOl_w_lg_dataout47266w(0); + wire_nli00iiOO_dataout <= (NOT k_conf(246)) OR NOT(nl0iOl11i); + wire_nli00iiOO_w_lg_dataout47233w(0) <= wire_nli00iiOO_dataout AND wire_nli00l11l_w_lg_dataout47232w(0); + wire_nli00iiOO_w_lg_w_lg_dataout47233w47234w(0) <= NOT wire_nli00iiOO_w_lg_dataout47233w(0); + wire_nli00il0i_dataout <= (NOT k_conf(250)) OR NOT(nl0iOl11i); + wire_nli00il0i_w_lg_dataout47111w(0) <= wire_nli00il0i_dataout AND wire_nli00l10O_w_lg_dataout47110w(0); + wire_nli00il0i_w_lg_w_lg_dataout47111w47112w(0) <= NOT wire_nli00il0i_w_lg_dataout47111w(0); + wire_nli00il0l_dataout <= (NOT k_conf(251)) OR NOT(nl0iOl11i); + wire_nli00il0l_w_lg_dataout47079w(0) <= wire_nli00il0l_dataout AND wire_nli00l1ii_w_lg_dataout47078w(0); + wire_nli00il0l_w_lg_w_lg_dataout47079w47080w(0) <= NOT wire_nli00il0l_w_lg_dataout47079w(0); + wire_nli00il0O_dataout <= (NOT k_conf(252)) OR NOT(nl0iOl11i); + wire_nli00il0O_w_lg_dataout47046w(0) <= wire_nli00il0O_dataout AND wire_nli00l1il_w_lg_dataout47045w(0); + wire_nli00il0O_w_lg_w_lg_dataout47046w47047w(0) <= NOT wire_nli00il0O_w_lg_dataout47046w(0); + wire_nli00il1i_dataout <= (NOT k_conf(247)) OR NOT(nl0iOl11i); + wire_nli00il1i_w_lg_dataout47202w(0) <= wire_nli00il1i_dataout AND wire_nli00l11O_w_lg_dataout47201w(0); + wire_nli00il1i_w_lg_w_lg_dataout47202w47203w(0) <= NOT wire_nli00il1i_w_lg_dataout47202w(0); + wire_nli00il1l_dataout <= (NOT k_conf(248)) OR NOT(nl0iOl11i); + wire_nli00il1l_w_lg_dataout47170w(0) <= wire_nli00il1l_dataout AND wire_nli00l10i_w_lg_dataout47169w(0); + wire_nli00il1l_w_lg_w_lg_dataout47170w47171w(0) <= NOT wire_nli00il1l_w_lg_dataout47170w(0); + wire_nli00il1O_dataout <= (NOT k_conf(249)) OR NOT(nl0iOl11i); + wire_nli00il1O_w_lg_dataout47139w(0) <= wire_nli00il1O_dataout AND wire_nli00l10l_w_lg_dataout47138w(0); + wire_nli00il1O_w_lg_w_lg_dataout47139w47140w(0) <= NOT wire_nli00il1O_w_lg_dataout47139w(0); + wire_nli00ili_dataout <= wire_nli0llll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00ilii_dataout <= (NOT k_conf(253)) OR NOT(nl0iOl11i); + wire_nli00ilii_w_lg_dataout47018w(0) <= wire_nli00ilii_dataout AND wire_nli00l1iO_w_lg_dataout47017w(0); + wire_nli00ilii_w_lg_w_lg_dataout47018w47019w(0) <= NOT wire_nli00ilii_w_lg_dataout47018w(0); + wire_nli00ilil_dataout <= (NOT k_conf(254)) OR NOT(nl0iOl11i); + wire_nli00ilil_w_lg_dataout46990w(0) <= wire_nli00ilil_dataout AND wire_nli00l1li_w_lg_dataout46989w(0); + wire_nli00ilil_w_lg_w_lg_dataout46990w46991w(0) <= NOT wire_nli00ilil_w_lg_dataout46990w(0); + wire_nli00iliO_dataout <= (NOT k_conf(255)) OR NOT(nl0iOl11i); + wire_nli00iliO_w_lg_dataout46961w(0) <= wire_nli00iliO_dataout AND wire_nli00l1ll_w_lg_dataout46960w(0); + wire_nli00iliO_w_lg_w_lg_dataout46961w46962w(0) <= NOT wire_nli00iliO_w_lg_dataout46961w(0); + wire_nli00ill_dataout <= wire_nli0lllO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00illi_dataout <= (NOT k_conf(256)) OR NOT(nl0iOl11i); + wire_nli00illi_w_lg_dataout46932w(0) <= wire_nli00illi_dataout AND wire_nli00l1lO_w_lg_dataout46931w(0); + wire_nli00illi_w_lg_w_lg_dataout46932w46933w(0) <= NOT wire_nli00illi_w_lg_dataout46932w(0); + wire_nli00illl_dataout <= (NOT k_conf(257)) OR NOT(nl0iOl11i); + wire_nli00illl_w_lg_dataout46902w(0) <= wire_nli00illl_dataout AND wire_nli00l1Oi_w_lg_dataout46901w(0); + wire_nli00illl_w_lg_w_lg_dataout46902w46903w(0) <= NOT wire_nli00illl_w_lg_dataout46902w(0); + wire_nli00illO_dataout <= (NOT k_conf(258)) OR NOT(nl0iOl11i); + wire_nli00illO_w_lg_dataout46874w(0) <= wire_nli00illO_dataout AND wire_nli00l1Ol_w_lg_dataout46873w(0); + wire_nli00illO_w_lg_w_lg_dataout46874w46875w(0) <= NOT wire_nli00illO_w_lg_dataout46874w(0); + wire_nli00ilO_dataout <= wire_nli0llOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00ilOi_dataout <= (NOT k_conf(259)) OR NOT(nl0iOl11i); + wire_nli00ilOi_w_lg_dataout46847w(0) <= wire_nli00ilOi_dataout AND wire_nli00l1OO_w_lg_dataout46846w(0); + wire_nli00ilOi_w_lg_w_lg_dataout46847w46848w(0) <= NOT wire_nli00ilOi_w_lg_dataout46847w(0); + wire_nli00ilOl_dataout <= (NOT k_conf(260)) OR NOT(nl0iOl11i); + wire_nli00ilOl_w_lg_dataout46820w(0) <= wire_nli00ilOl_dataout AND wire_nli00l01i_w_lg_dataout46819w(0); + wire_nli00ilOl_w_lg_w_lg_dataout46820w46821w(0) <= NOT wire_nli00ilOl_w_lg_dataout46820w(0); + wire_nli00ilOO_dataout <= (NOT k_conf(261)) OR NOT(nl0iOl11i); + wire_nli00ilOO_w_lg_dataout46794w(0) <= wire_nli00ilOO_dataout AND wire_nli00l01l_w_lg_dataout46793w(0); + wire_nli00ilOO_w_lg_w_lg_dataout46794w46795w(0) <= NOT wire_nli00ilOO_w_lg_dataout46794w(0); + wire_nli00iO0i_dataout <= (NOT k_conf(265)) OR NOT(nl0iOiOOO); + wire_nli00iO0i_w_lg_dataout47642w(0) <= wire_nli00iO0i_dataout AND wire_nli0i0l0i_w_lg_dataout47641w(0); + wire_nli00iO0l_dataout <= (NOT k_conf(266)) OR NOT(nl0iOiOOO); + wire_nli00iO0l_w_lg_dataout47608w(0) <= wire_nli00iO0l_dataout AND wire_nli0i001l_w_lg_dataout47607w(0); + wire_nli00iO0O_dataout <= (NOT k_conf(267)) OR NOT(nl0iOiOOO); + wire_nli00iO0O_w_lg_dataout47574w(0) <= wire_nli00iO0O_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47573w(0); + wire_nli00iO1i_dataout <= (NOT k_conf(262)) OR NOT(nl0iOl11i); + wire_nli00iO1i_w_lg_dataout46767w(0) <= wire_nli00iO1i_dataout AND wire_nli00l01O_w_lg_dataout46766w(0); + wire_nli00iO1i_w_lg_w_lg_dataout46767w46768w(0) <= NOT wire_nli00iO1i_w_lg_dataout46767w(0); + wire_nli00iO1l_dataout <= (NOT k_conf(263)) OR NOT(nl0iOiOOO); + wire_nli00iO1l_w_lg_dataout47713w(0) <= wire_nli00iO1l_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47712w(0); + wire_nli00iO1O_dataout <= (NOT k_conf(264)) OR NOT(nl0iOiOOO); + wire_nli00iO1O_w_lg_dataout47675w(0) <= wire_nli00iO1O_dataout AND wire_nli0i001i_w_lg_dataout47674w(0); + wire_nli00iOi_dataout <= wire_nli0llOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00iOii_dataout <= (NOT k_conf(268)) OR NOT(nl0iOiOOO); + wire_nli00iOii_w_lg_dataout47543w(0) <= wire_nli00iOii_dataout AND wire_nli0i0lii_w_lg_dataout47542w(0); + wire_nli00iOil_dataout <= (NOT k_conf(269)) OR NOT(nl0iOiOOO); + wire_nli00iOil_w_lg_dataout47511w(0) <= wire_nli00iOil_dataout AND wire_nli0i0lil_w_lg_dataout47510w(0); + wire_nli00iOiO_dataout <= (NOT k_conf(270)) OR NOT(nl0iOiOOO); + wire_nli00iOiO_w_lg_dataout47477w(0) <= wire_nli00iOiO_dataout AND wire_nli0i0liO_w_lg_dataout47476w(0); + wire_nli00iOl_dataout <= wire_nli0llOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00iOli_dataout <= (NOT k_conf(271)) OR NOT(nl0iOiOOO); + wire_nli00iOli_w_lg_dataout47447w(0) <= wire_nli00iOli_dataout AND wire_nli0i001O_w_lg_dataout47446w(0); + wire_nli00iOll_dataout <= (NOT k_conf(272)) OR NOT(nl0iOiOOO); + wire_nli00iOll_w_lg_dataout47416w(0) <= wire_nli00iOll_dataout AND wire_nli0i000i_w_lg_dataout47415w(0); + wire_nli00iOlO_dataout <= (NOT k_conf(273)) OR NOT(nl0iOiOOO); + wire_nli00iOlO_w_lg_dataout47386w(0) <= wire_nli00iOlO_dataout AND wire_nli0i000l_w_lg_dataout47385w(0); + wire_nli00iOO_dataout <= wire_nli0lO1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00iOOi_dataout <= (NOT k_conf(274)) OR NOT(nl0iOiOOO); + wire_nli00iOOi_w_lg_dataout47356w(0) <= wire_nli00iOOi_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47355w(0); + wire_nli00iOOl_dataout <= (NOT k_conf(275)) OR NOT(nl0iOiOOO); + wire_nli00iOOl_w_lg_dataout47325w(0) <= wire_nli00iOOl_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47324w(0); + wire_nli00iOOO_dataout <= (NOT k_conf(276)) OR NOT(nl0iOiOOO); + wire_nli00iOOO_w_lg_dataout47296w(0) <= wire_nli00iOOO_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47295w(0); + wire_nli00l00i_dataout <= (NOT k_conf(295)) OR NOT(nl0iOiOOl); + wire_nli00l00i_w_lg_dataout47200w(0) <= wire_nli00l00i_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47199w(0); + wire_nli00l00l_dataout <= (NOT k_conf(296)) OR NOT(nl0iOiOOl); + wire_nli00l00l_w_lg_dataout47168w(0) <= wire_nli00l00l_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47167w(0); + wire_nli00l00O_dataout <= (NOT k_conf(297)) OR NOT(nl0iOiOOl); + wire_nli00l00O_w_lg_dataout47137w(0) <= wire_nli00l00O_dataout AND wire_nli0ii1ii_w_lg_dataout47136w(0); + wire_nli00l01i_dataout <= (NOT k_conf(292)) OR NOT(nl0iOiOOO); + wire_nli00l01i_w_lg_dataout46819w(0) <= wire_nli00l01i_dataout AND wire_nli0i0i1i_w_lg_dataout46818w(0); + wire_nli00l01l_dataout <= (NOT k_conf(293)) OR NOT(nl0iOiOOO); + wire_nli00l01l_w_lg_dataout46793w(0) <= wire_nli00l01l_dataout AND wire_nli00l0OO_w_lg_dataout46792w(0); + wire_nli00l01O_dataout <= (NOT k_conf(294)) OR NOT(nl0iOiOOO); + wire_nli00l01O_w_lg_dataout46766w(0) <= wire_nli00l01O_dataout AND wire_nli00li1i_w_lg_dataout46765w(0); + wire_nli00l0i_dataout <= wire_nli0lO0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00l0ii_dataout <= (NOT k_conf(298)) OR NOT(nl0iOiOOl); + wire_nli00l0ii_w_lg_dataout47109w(0) <= wire_nli00l0ii_dataout AND wire_nli0i0i0i_w_lg_dataout47108w(0); + wire_nli00l0il_dataout <= (NOT k_conf(299)) OR NOT(nl0iOiOOl); + wire_nli00l0il_w_lg_dataout47077w(0) <= wire_nli00l0il_dataout AND wire_nli0i0i0l_w_lg_dataout47076w(0); + wire_nli00l0iO_dataout <= (NOT k_conf(300)) OR NOT(nl0iOiOOl); + wire_nli00l0iO_w_lg_dataout47044w(0) <= wire_nli00l0iO_dataout AND wire_nli0i0i0O_w_lg_dataout47043w(0); + wire_nli00l0l_dataout <= wire_nli0lO0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00l0li_dataout <= (NOT k_conf(301)) OR NOT(nl0iOiOOl); + wire_nli00l0li_w_lg_dataout47016w(0) <= wire_nli00l0li_dataout AND wire_nli0i0iii_w_lg_dataout47015w(0); + wire_nli00l0ll_dataout <= (NOT k_conf(302)) OR NOT(nl0iOiOOl); + wire_nli00l0ll_w_lg_dataout46988w(0) <= wire_nli00l0ll_dataout AND wire_nli0i0iil_w_lg_dataout46987w(0); + wire_nli00l0lO_dataout <= (NOT k_conf(303)) OR NOT(nl0iOiOOl); + wire_nli00l0lO_w_lg_dataout46959w(0) <= wire_nli00l0lO_dataout AND wire_nli0i00ll_w_lg_dataout46958w(0); + wire_nli00l0O_dataout <= wire_nli0lOii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00l0Oi_dataout <= (NOT k_conf(304)) OR NOT(nl0iOiOOl); + wire_nli00l0Oi_w_lg_dataout46930w(0) <= wire_nli00l0Oi_dataout AND wire_nli0i00lO_w_lg_dataout46929w(0); + wire_nli00l0Ol_dataout <= (NOT k_conf(305)) OR NOT(nl0iOiOOl); + wire_nli00l0Ol_w_lg_dataout46900w(0) <= wire_nli00l0Ol_dataout AND wire_nli0i00Oi_w_lg_dataout46899w(0); + wire_nli00l0OO_dataout <= wire_nlill0Oll_w_lg_nl0l0OiOO46545w(0) OR NOT(nl0iOiOOl); + wire_nli00l0OO_w_lg_dataout46792w(0) <= wire_nli00l0OO_dataout AND wire_nli0i0i1l_w_lg_dataout46791w(0); + wire_nli00l10i_dataout <= (NOT k_conf(280)) OR NOT(nl0iOiOOO); + wire_nli00l10i_w_lg_dataout47169w(0) <= wire_nli00l10i_dataout AND wire_nli00l00l_w_lg_dataout47168w(0); + wire_nli00l10l_dataout <= (NOT k_conf(281)) OR NOT(nl0iOiOOO); + wire_nli00l10l_w_lg_dataout47138w(0) <= wire_nli00l10l_dataout AND wire_nli00l00O_w_lg_dataout47137w(0); + wire_nli00l10O_dataout <= (NOT k_conf(282)) OR NOT(nl0iOiOOO); + wire_nli00l10O_w_lg_dataout47110w(0) <= wire_nli00l10O_dataout AND wire_nli00l0ii_w_lg_dataout47109w(0); + wire_nli00l11i_dataout <= (NOT k_conf(277)) OR NOT(nl0iOiOOO); + wire_nli00l11i_w_lg_dataout47265w(0) <= wire_nli00l11i_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOOl47245w47264w(0); + wire_nli00l11l_dataout <= (NOT k_conf(278)) OR NOT(nl0iOiOOO); + wire_nli00l11l_w_lg_dataout47232w(0) <= wire_nli00l11l_dataout AND wire_nli0i00li_w_lg_dataout47231w(0); + wire_nli00l11O_dataout <= (NOT k_conf(279)) OR NOT(nl0iOiOOO); + wire_nli00l11O_w_lg_dataout47201w(0) <= wire_nli00l11O_dataout AND wire_nli00l00i_w_lg_dataout47200w(0); + wire_nli00l1i_dataout <= wire_nli0lO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00l1ii_dataout <= (NOT k_conf(283)) OR NOT(nl0iOiOOO); + wire_nli00l1ii_w_lg_dataout47078w(0) <= wire_nli00l1ii_dataout AND wire_nli00l0il_w_lg_dataout47077w(0); + wire_nli00l1il_dataout <= (NOT k_conf(284)) OR NOT(nl0iOiOOO); + wire_nli00l1il_w_lg_dataout47045w(0) <= wire_nli00l1il_dataout AND wire_nli00l0iO_w_lg_dataout47044w(0); + wire_nli00l1iO_dataout <= (NOT k_conf(285)) OR NOT(nl0iOiOOO); + wire_nli00l1iO_w_lg_dataout47017w(0) <= wire_nli00l1iO_dataout AND wire_nli00l0li_w_lg_dataout47016w(0); + wire_nli00l1l_dataout <= wire_nli0lO1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00l1li_dataout <= (NOT k_conf(286)) OR NOT(nl0iOiOOO); + wire_nli00l1li_w_lg_dataout46989w(0) <= wire_nli00l1li_dataout AND wire_nli00l0ll_w_lg_dataout46988w(0); + wire_nli00l1ll_dataout <= (NOT k_conf(287)) OR NOT(nl0iOiOOO); + wire_nli00l1ll_w_lg_dataout46960w(0) <= wire_nli00l1ll_dataout AND wire_nli00l0lO_w_lg_dataout46959w(0); + wire_nli00l1lO_dataout <= (NOT k_conf(288)) OR NOT(nl0iOiOOO); + wire_nli00l1lO_w_lg_dataout46931w(0) <= wire_nli00l1lO_dataout AND wire_nli00l0Oi_w_lg_dataout46930w(0); + wire_nli00l1O_dataout <= wire_nli0lO0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00l1Oi_dataout <= (NOT k_conf(289)) OR NOT(nl0iOiOOO); + wire_nli00l1Oi_w_lg_dataout46901w(0) <= wire_nli00l1Oi_dataout AND wire_nli00l0Ol_w_lg_dataout46900w(0); + wire_nli00l1Ol_dataout <= (NOT k_conf(290)) OR NOT(nl0iOiOOO); + wire_nli00l1Ol_w_lg_dataout46873w(0) <= wire_nli00l1Ol_dataout AND wire_nli0i00Ol_w_lg_dataout46872w(0); + wire_nli00l1OO_dataout <= (NOT k_conf(291)) OR NOT(nl0iOiOOO); + wire_nli00l1OO_w_lg_dataout46846w(0) <= wire_nli00l1OO_dataout AND wire_nli0i00OO_w_lg_dataout46845w(0); + wire_nli00li0i_dataout <= wire_nli11O11O_w_lg_dataout46541w(0) OR NOT(nl0iOiO1l); + wire_nli00li0i_w_lg_dataout47653w(0) <= wire_nli00li0i_dataout AND wire_nli00ll1O_w_lg_dataout47652w(0); + wire_nli00li0l_dataout <= wire_nli11O10i_w_lg_dataout46540w(0) OR NOT(nl0iOiO1l); + wire_nli00li0l_w_lg_dataout47619w(0) <= wire_nli00li0l_dataout AND wire_nli00ll0i_w_lg_dataout47618w(0); + wire_nli00li0O_dataout <= wire_nliiOiilO_w_lg_nli11O1Oi46539w(0) OR NOT(nl0iOiO1l); + wire_nli00li0O_w_lg_dataout47586w(0) <= wire_nli00li0O_dataout AND wire_nli00ll0l_w_lg_dataout47585w(0); + wire_nli00li1i_dataout <= wire_nlill0Oll_w_lg_nl0lil11i46544w(0) OR NOT(nl0iOiOOl); + wire_nli00li1i_w_lg_dataout46765w(0) <= wire_nli00li1i_dataout AND wire_nli0i0i1O_w_lg_dataout46764w(0); + wire_nli00li1l_dataout <= wire_nli11O11i_w_lg_dataout46543w(0) OR NOT(nl0iOiO1l); + wire_nli00li1l_w_lg_dataout47726w(0) <= wire_nli00li1l_dataout AND wire_nli00ll1i_w_lg_dataout47725w(0); + wire_nli00li1O_dataout <= wire_nli11O11l_w_lg_dataout46542w(0) OR NOT(nl0iOiO1l); + wire_nli00li1O_w_lg_dataout47688w(0) <= wire_nli00li1O_dataout AND wire_nli00ll1l_w_lg_dataout47687w(0); + wire_nli00lii_dataout <= wire_nli0lOil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00liii_dataout <= wire_nlill0Oll_w_lg_nli11O0ii46538w(0) OR NOT(nl0iOiO1l); + wire_nli00liii_w_lg_dataout47552w(0) <= wire_nli00liii_dataout AND wire_nli00lO1i_w_lg_dataout47551w(0); + wire_nli00liil_dataout <= wire_nli11O10O_w_lg_dataout46537w(0) OR NOT(nl0iOiO1l); + wire_nli00liil_w_lg_dataout47521w(0) <= wire_nli00liil_dataout AND wire_nli00lO1l_w_lg_dataout47520w(0); + wire_nli00liiO_dataout <= wire_nliiOiilO_w_lg_nli11O1li46536w(0) OR NOT(nl0iOiO1l); + wire_nli00liiO_w_lg_dataout47487w(0) <= wire_nli00liiO_dataout AND wire_nli00lO1O_w_lg_dataout47486w(0); + wire_nli00lil_dataout <= wire_nli0lOiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00lili_dataout <= wire_nliiOiilO_w_lg_nli11O1ll46535w(0) OR NOT(nl0iOiO1l); + wire_nli00lili_w_lg_dataout47457w(0) <= wire_nli00lili_dataout AND wire_nli00lO0i_w_lg_dataout47456w(0); + wire_nli00lill_dataout <= wire_nliiOiilO_w_lg_nli11O1lO46534w(0) OR NOT(nl0iOiO1l); + wire_nli00lill_w_lg_dataout47425w(0) <= wire_nli00lill_dataout AND wire_nli00lO0l_w_lg_dataout47424w(0); + wire_nli00lilO_dataout <= wire_nliiOiilO_w_lg_nli11O1iO46533w(0) OR NOT(nl0iOiO1l); + wire_nli00lilO_w_lg_dataout47396w(0) <= wire_nli00lilO_dataout AND wire_nli00lO0O_w_lg_dataout47395w(0); + wire_nli00liO_dataout <= wire_nli0lOli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00liOi_dataout <= wire_nliiOiilO_w_lg_nli11O1il46532w(0) OR NOT(nl0iOiO1l); + wire_nli00liOi_w_lg_dataout47365w(0) <= wire_nli00liOi_dataout AND wire_nli00lOii_w_lg_dataout47364w(0); + wire_nli00liOl_dataout <= wire_nliiOiilO_w_lg_nli11li1i46531w(0) OR NOT(nl0iOiO1l); + wire_nli00liOl_w_lg_dataout47334w(0) <= wire_nli00liOl_dataout AND wire_nli00lOil_w_lg_dataout47333w(0); + wire_nli00liOO_dataout <= wire_nlOi0i01O_w_lg_dataout46530w(0) OR NOT(nl0iOiO1l); + wire_nli00liOO_w_lg_dataout47211w(0) <= wire_nli00liOO_dataout AND wire_nli00lOlO_w_lg_dataout47210w(0); + wire_nli00ll0i_dataout <= wire_nlill0Oll_w_lg_nli11Olii46526w(0) OR NOT(nl0iOilOO); + wire_nli00ll0i_w_lg_dataout47618w(0) <= wire_nli00ll0i_dataout AND wire_nli00lliO_w_lg_dataout47617w(0); + wire_nli00ll0l_dataout <= wire_nlill0Oll_w_lg_nli11OiOl46525w(0) OR NOT(nl0iOilOO); + wire_nli00ll0l_w_lg_dataout47585w(0) <= wire_nli00ll0l_dataout AND wire_nli00llli_w_lg_dataout47584w(0); + wire_nli00ll0O_dataout <= wire_nlill0Oll_w_lg_nli11OOll46524w(0) OR NOT(nl0iOilOl); + wire_nli00ll0O_w_lg_dataout47724w(0) <= wire_nli00ll0O_dataout AND wire_nli00llll_w_lg_dataout47723w(0); + wire_nli00ll1i_dataout <= wire_nlill0Oll_w_lg_nli11Ol0i46529w(0) OR NOT(nl0iOilOO); + wire_nli00ll1i_w_lg_dataout47725w(0) <= wire_nli00ll1i_dataout AND wire_nli00ll0O_w_lg_dataout47724w(0); + wire_nli00ll1l_dataout <= wire_nlill0Oll_w_lg_nli11Ol0l46528w(0) OR NOT(nl0iOilOO); + wire_nli00ll1l_w_lg_dataout47687w(0) <= wire_nli00ll1l_dataout AND wire_nli00llii_w_lg_dataout47686w(0); + wire_nli00ll1O_dataout <= wire_nlill0Oll_w_lg_nli11Ol0O46527w(0) OR NOT(nl0iOilOO); + wire_nli00ll1O_w_lg_dataout47652w(0) <= wire_nli00ll1O_dataout AND wire_nli00llil_w_lg_dataout47651w(0); + wire_nli00lli_dataout <= wire_nli0lOll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00llii_dataout <= wire_nlill0Oll_w_lg_nli11OOlO46523w(0) OR NOT(nl0iOilOl); + wire_nli00llii_w_lg_dataout47686w(0) <= wire_nli00llii_dataout AND wire_nli00lllO_w_lg_dataout47685w(0); + wire_nli00llil_dataout <= wire_nlill0Oll_w_lg_nli11OOOi46522w(0) OR NOT(nl0iOilOl); + wire_nli00llil_w_lg_dataout47651w(0) <= wire_nli00llil_dataout AND wire_nli00llOi_w_lg_dataout47650w(0); + wire_nli00lliO_dataout <= wire_nlill0Oll_w_lg_nli11OOOl46521w(0) OR NOT(nl0iOilOl); + wire_nli00lliO_w_lg_dataout47617w(0) <= wire_nli00lliO_dataout AND wire_nli00llOl_w_lg_dataout47616w(0); + wire_nli00lll_dataout <= wire_nli0lOlO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00llli_dataout <= wire_nlill0Oll_w_lg_nli11Olil46520w(0) OR NOT(nl0iOilOl); + wire_nli00llli_w_lg_dataout47584w(0) <= wire_nli00llli_dataout AND wire_nli00llOO_w_lg_dataout47583w(0); + wire_nli00llll_dataout <= wire_nli1011ii_w_lg_dataout46519w(0) OR NOT(nl0iOilOi); + wire_nli00llll_w_lg_dataout47723w(0) <= wire_nli00llll_dataout AND wire_nli00lOOl_w_lg_dataout47722w(0); + wire_nli00lllO_dataout <= wire_nli1011il_w_lg_dataout46518w(0) OR NOT(nl0iOilOi); + wire_nli00lllO_w_lg_dataout47685w(0) <= wire_nli00lllO_dataout AND wire_nli00lOOO_w_lg_dataout47684w(0); + wire_nli00llO_dataout <= wire_nli0lOOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00llOi_dataout <= wire_nli1011iO_w_lg_dataout46517w(0) OR NOT(nl0iOilOi); + wire_nli00llOi_w_lg_dataout47650w(0) <= wire_nli00llOi_dataout AND wire_nli00O11i_w_lg_dataout47649w(0); + wire_nli00llOl_dataout <= wire_nli1011li_w_lg_dataout46516w(0) OR NOT(nl0iOilOi); + wire_nli00llOl_w_lg_dataout47616w(0) <= wire_nli00llOl_dataout AND wire_nli00O11l_w_lg_dataout47615w(0); + wire_nli00llOO_dataout <= wire_nli1011ll_w_lg_dataout46515w(0) OR NOT(nl0iOilOi); + wire_nli00llOO_w_lg_dataout47583w(0) <= wire_nli00llOO_dataout AND wire_nli00O1ii_w_lg_dataout47582w(0); + wire_nli00lO0i_dataout <= wire_nli1011OO_w_lg_dataout46511w(0) OR NOT(nl0iOilOi); + wire_nli00lO0i_w_lg_dataout47456w(0) <= wire_nli00lO0i_dataout AND wire_nli00O1ll_w_lg_dataout47455w(0); + wire_nli00lO0l_dataout <= wire_nli10101i_w_lg_dataout46510w(0) OR NOT(nl0iOilOi); + wire_nli00lO0l_w_lg_dataout47424w(0) <= wire_nli00lO0l_dataout AND wire_nli00O1lO_w_lg_dataout47423w(0); + wire_nli00lO0O_dataout <= wire_nli10101l_w_lg_dataout46509w(0) OR NOT(nl0iOilOi); + wire_nli00lO0O_w_lg_dataout47395w(0) <= wire_nli00lO0O_dataout AND wire_nli00O1Oi_w_lg_dataout47394w(0); + wire_nli00lO1i_dataout <= wire_nli1011lO_w_lg_dataout46514w(0) OR NOT(nl0iOilOi); + wire_nli00lO1i_w_lg_dataout47551w(0) <= wire_nli00lO1i_dataout AND wire_nli00O1il_w_lg_dataout47550w(0); + wire_nli00lO1l_dataout <= wire_nli1011Oi_w_lg_dataout46513w(0) OR NOT(nl0iOilOi); + wire_nli00lO1l_w_lg_dataout47520w(0) <= wire_nli00lO1l_dataout AND wire_nli00O1iO_w_lg_dataout47519w(0); + wire_nli00lO1O_dataout <= wire_nli1011Ol_w_lg_dataout46512w(0) OR NOT(nl0iOilOi); + wire_nli00lO1O_w_lg_dataout47486w(0) <= wire_nli00lO1O_dataout AND wire_nli00O1li_w_lg_dataout47485w(0); + wire_nli00lOi_dataout <= wire_nli0lOOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00lOii_dataout <= wire_nli10101O_w_lg_dataout46508w(0) OR NOT(nl0iOilOi); + wire_nli00lOii_w_lg_dataout47364w(0) <= wire_nli00lOii_dataout AND wire_nli00Oi0l_w_lg_dataout47363w(0); + wire_nli00lOil_dataout <= wire_nli10100i_w_lg_dataout46507w(0) OR NOT(nl0iOilOi); + wire_nli00lOil_w_lg_dataout47333w(0) <= wire_nli00lOil_dataout AND wire_nli00O1Ol_w_lg_dataout47332w(0); + wire_nli00lOiO_dataout <= wire_nli10100l_w_lg_dataout46506w(0) OR NOT(nl0iOilOi); + wire_nli00lOiO_w_lg_dataout47303w(0) <= wire_nli00lOiO_dataout AND wire_nli00Oiii_w_lg_dataout47302w(0); + wire_nli00lOl_dataout <= wire_nli0lOOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00lOli_dataout <= wire_nli10100O_w_lg_dataout46505w(0) OR NOT(nl0iOilOi); + wire_nli00lOli_w_lg_dataout47273w(0) <= wire_nli00lOli_dataout AND wire_nli00Oiil_w_lg_dataout47272w(0); + wire_nli00lOll_dataout <= wire_nli1010ii_w_lg_dataout46504w(0) OR NOT(nl0iOilOi); + wire_nli00lOll_w_lg_dataout47240w(0) <= wire_nli00lOll_dataout AND wire_nli00OiiO_w_lg_dataout47239w(0); + wire_nli00lOlO_dataout <= wire_nli10110O_w_lg_dataout46503w(0) OR NOT(nl0iOilOi); + wire_nli00lOlO_w_lg_dataout47210w(0) <= wire_nli00lOlO_dataout AND wire_nli00O1OO_w_lg_dataout47209w(0); + wire_nli00lOO_dataout <= wire_nli0O11i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00lOOi_dataout <= wire_w_lg_niOO10OOi46502w(0) OR NOT(nl0iOilOi); + wire_nli00lOOi_w_lg_dataout47178w(0) <= wire_nli00lOOi_dataout AND wire_nli00O01i_w_lg_dataout47177w(0); + wire_nli00lOOl_dataout <= wire_nlill0Oll_w_lg_nli10001O46501w(0) OR NOT(nl0iOillO); + wire_nli00lOOl_w_lg_dataout47722w(0) <= wire_nli00lOOl_dataout AND wire_nli00O11O_w_lg_dataout47721w(0); + wire_nli00lOOO_dataout <= wire_nlill0Oll_w_lg_nli10Oiil46500w(0) OR NOT(nl0iOillO); + wire_nli00lOOO_w_lg_dataout47684w(0) <= wire_nli00lOOO_dataout AND wire_nli00O10i_w_lg_dataout47683w(0); + wire_nli00O00i_dataout <= wire_nlill0Oll_w_lg_nli10Olli46481w(0) OR NOT(nl0iOilll); + wire_nli00O00i_w_lg_dataout47087w(0) <= wire_nli00O00i_dataout AND wire_nli00OiOl_w_lg_dataout47086w(0); + wire_nli00O00l_dataout <= wire_nlill0Oll_w_lg_nli10OO1l46480w(0) OR NOT(nl0iOilll); + wire_nli00O00l_w_lg_dataout47054w(0) <= wire_nli00O00l_dataout AND wire_nli00OiOO_w_lg_dataout47053w(0); + wire_nli00O00O_dataout <= wire_nlill0Oll_w_lg_nli10OlOO46479w(0) OR NOT(nl0iOilll); + wire_nli00O00O_w_lg_dataout47024w(0) <= wire_nli00O00O_dataout AND wire_nli00Ol1i_w_lg_dataout47023w(0); + wire_nli00O01i_dataout <= wire_nlill0Oll_w_lg_nli10OllO46484w(0) OR NOT(nl0iOilll); + wire_nli00O01i_w_lg_dataout47177w(0) <= wire_nli00O01i_dataout AND wire_nli00Oill_w_lg_dataout47176w(0); + wire_nli00O01l_dataout <= wire_nlill0Oll_w_lg_nli10OO1i46483w(0) OR NOT(nl0iOilll); + wire_nli00O01l_w_lg_dataout47146w(0) <= wire_nli00O01l_dataout AND wire_nli00OilO_w_lg_dataout47145w(0); + wire_nli00O01O_dataout <= wire_nlill0Oll_w_lg_nli10OlOl46482w(0) OR NOT(nl0iOilll); + wire_nli00O01O_w_lg_dataout47118w(0) <= wire_nli00O01O_dataout AND wire_nli00OiOi_w_lg_dataout47117w(0); + wire_nli00O0i_dataout <= wire_nli0O10l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00O0ii_dataout <= wire_nlill0Oll_w_lg_nli10OliO46478w(0) OR NOT(nl0iOilll); + wire_nli00O0ii_w_lg_dataout46995w(0) <= wire_nli00O0ii_dataout AND wire_nli00Ol1l_w_lg_dataout46994w(0); + wire_nli00O0il_dataout <= wire_nlill0Oll_w_lg_nli10Olil46477w(0) OR NOT(nl0iOilll); + wire_nli00O0il_w_lg_dataout46967w(0) <= wire_nli00O0il_dataout AND wire_nli00Ol1O_w_lg_dataout46966w(0); + wire_nli00O0iO_dataout <= wire_w_lg_niOiiOi1i46476w(0) OR NOT(nl0iOilli); + wire_nli00O0iO_w_lg_dataout47720w(0) <= wire_nli00O0iO_dataout AND wire_nli00Olll_w_lg_dataout47719w(0); + wire_nli00O0l_dataout <= wire_nli0O10O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00O0li_dataout <= wire_w_lg_niOiiOi1l46475w(0) OR NOT(nl0iOilli); + wire_nli00O0li_w_lg_dataout47682w(0) <= wire_nli00O0li_dataout AND wire_nli00OllO_w_lg_dataout47681w(0); + wire_nli00O0ll_dataout <= wire_w_lg_niOiiOi1O46474w(0) OR NOT(nl0iOilli); + wire_nli00O0ll_w_lg_dataout47647w(0) <= wire_nli00O0ll_dataout AND wire_nli0i1liO_w_lg_dataout47646w(0); + wire_nli00O0lO_dataout <= wire_w_lg_niOiiOi0i46473w(0) OR NOT(nl0iOilli); + wire_nli00O0lO_w_lg_dataout47613w(0) <= wire_nli00O0lO_dataout AND wire_nli0i1i0i_w_lg_dataout47612w(0); + wire_nli00O0O_dataout <= wire_nli0O1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00O0Oi_dataout <= wire_w_lg_niOiiOi0l46472w(0) OR NOT(nl0iOilli); + wire_nli00O0Oi_w_lg_dataout47581w(0) <= wire_nli00O0Oi_dataout AND wire_nli00OlOl_w_lg_dataout47580w(0); + wire_nli00O0Ol_dataout <= wire_w_lg_niOillO0l46471w(0) OR NOT(nl0iOilli); + wire_nli00O0Ol_w_lg_dataout47549w(0) <= wire_nli00O0Ol_dataout AND wire_nli0i110O_w_lg_dataout47548w(0); + wire_nli00O0OO_dataout <= wire_w_lg_niOillO0i46470w(0) OR NOT(nl0iOilli); + wire_nli00O0OO_w_lg_dataout47518w(0) <= wire_nli00O0OO_dataout AND wire_nli00OlOO_w_lg_dataout47517w(0); + wire_nli00O10i_dataout <= wire_nlill0Oll_w_lg_nli1i01Ol46496w(0) OR NOT(nl0iOilll); + wire_nli00O10i_w_lg_dataout47683w(0) <= wire_nli00O10i_dataout AND wire_nli00O0li_w_lg_dataout47682w(0); + wire_nli00O10l_dataout <= wire_nlill0Oll_w_lg_nli1i01Oi46495w(0) OR NOT(nl0iOilll); + wire_nli00O10l_w_lg_dataout47648w(0) <= wire_nli00O10l_dataout AND wire_nli00O0ll_w_lg_dataout47647w(0); + wire_nli00O10O_dataout <= wire_nlill0Oll_w_lg_nli1i01lO46494w(0) OR NOT(nl0iOilll); + wire_nli00O10O_w_lg_dataout47614w(0) <= wire_nli00O10O_dataout AND wire_nli00O0lO_w_lg_dataout47613w(0); + wire_nli00O11i_dataout <= wire_nlill0Oll_w_lg_nli10OiiO46499w(0) OR NOT(nl0iOillO); + wire_nli00O11i_w_lg_dataout47649w(0) <= wire_nli00O11i_dataout AND wire_nli00O10l_w_lg_dataout47648w(0); + wire_nli00O11l_dataout <= wire_nlill0Oll_w_lg_nli10Oili46498w(0) OR NOT(nl0iOillO); + wire_nli00O11l_w_lg_dataout47615w(0) <= wire_nli00O11l_dataout AND wire_nli00O10O_w_lg_dataout47614w(0); + wire_nli00O11O_dataout <= wire_nlill0Oll_w_lg_nli1i01OO46497w(0) OR NOT(nl0iOilll); + wire_nli00O11O_w_lg_dataout47721w(0) <= wire_nli00O11O_dataout AND wire_nli00O0iO_w_lg_dataout47720w(0); + wire_nli00O1i_dataout <= wire_nli0O11l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00O1ii_dataout <= wire_nlill0Oll_w_lg_nli1i01ll46493w(0) OR NOT(nl0iOilll); + wire_nli00O1ii_w_lg_dataout47582w(0) <= wire_nli00O1ii_dataout AND wire_nli00O0Oi_w_lg_dataout47581w(0); + wire_nli00O1il_dataout <= wire_nlill0Oll_w_lg_nli1i01li46492w(0) OR NOT(nl0iOilll); + wire_nli00O1il_w_lg_dataout47550w(0) <= wire_nli00O1il_dataout AND wire_nli00O0Ol_w_lg_dataout47549w(0); + wire_nli00O1iO_dataout <= wire_nli1i1OiO_w_lg_dataout46491w(0) OR NOT(nl0iOilll); + wire_nli00O1iO_w_lg_dataout47519w(0) <= wire_nli00O1iO_dataout AND wire_nli00O0OO_w_lg_dataout47518w(0); + wire_nli00O1l_dataout <= wire_nli0O11O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00O1li_dataout <= wire_nli1i1Oli_w_lg_dataout46490w(0) OR NOT(nl0iOilll); + wire_nli00O1li_w_lg_dataout47485w(0) <= wire_nli00O1li_dataout AND wire_nli00Oi1i_w_lg_dataout47484w(0); + wire_nli00O1ll_dataout <= wire_nli1i1O1i_w_lg_dataout46489w(0) OR NOT(nl0iOilll); + wire_nli00O1ll_w_lg_dataout47455w(0) <= wire_nli00O1ll_dataout AND wire_nli00Oi1l_w_lg_dataout47454w(0); + wire_nli00O1lO_dataout <= wire_nli1i1O1l_w_lg_dataout46488w(0) OR NOT(nl0iOilll); + wire_nli00O1lO_w_lg_dataout47423w(0) <= wire_nli00O1lO_dataout AND wire_nli00Oi1O_w_lg_dataout47422w(0); + wire_nli00O1O_dataout <= wire_nli0O10i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00O1Oi_dataout <= wire_nlill0Oll_w_lg_nli1i011i46487w(0) OR NOT(nl0iOilll); + wire_nli00O1Oi_w_lg_dataout47394w(0) <= wire_nli00O1Oi_dataout AND wire_nli00Oi0i_w_lg_dataout47393w(0); + wire_nli00O1Ol_dataout <= wire_nlill0Oll_w_lg_nli10OO0l46486w(0) OR NOT(nl0iOilll); + wire_nli00O1Ol_w_lg_dataout47332w(0) <= wire_nli00O1Ol_dataout AND wire_nli00Oi0O_w_lg_dataout47331w(0); + wire_nli00O1OO_dataout <= wire_nlill0Oll_w_lg_nli10OO1O46485w(0) OR NOT(nl0iOilll); + wire_nli00O1OO_w_lg_dataout47209w(0) <= wire_nli00O1OO_dataout AND wire_nli00Oili_w_lg_dataout47208w(0); + wire_nli00Oi0i_dataout <= wire_nli1ii01O_w_lg_dataout46466w(0) OR NOT(nl0iOilli); + wire_nli00Oi0i_w_lg_dataout47393w(0) <= wire_nli00Oi0i_dataout AND wire_nli00OO0i_w_lg_dataout47392w(0); + wire_nli00Oi0l_dataout <= wire_nli1ii00i_w_lg_dataout46465w(0) OR NOT(nl0iOilli); + wire_nli00Oi0l_w_lg_dataout47363w(0) <= wire_nli00Oi0l_dataout AND wire_nli00OO0l_w_lg_dataout47362w(0); + wire_nli00Oi0O_dataout <= wire_nli1ii00l_w_lg_dataout46464w(0) OR NOT(nl0iOilli); + wire_nli00Oi0O_w_lg_dataout47331w(0) <= wire_nli00Oi0O_dataout AND wire_nli0i11Oi_w_lg_dataout47330w(0); + wire_nli00Oi1i_dataout <= wire_nli1ii1OO_w_lg_dataout46469w(0) OR NOT(nl0iOilli); + wire_nli00Oi1i_w_lg_dataout47484w(0) <= wire_nli00Oi1i_dataout AND wire_nli00OO1i_w_lg_dataout47483w(0); + wire_nli00Oi1l_dataout <= wire_nli1ii01i_w_lg_dataout46468w(0) OR NOT(nl0iOilli); + wire_nli00Oi1l_w_lg_dataout47454w(0) <= wire_nli00Oi1l_dataout AND wire_nli00OO1l_w_lg_dataout47453w(0); + wire_nli00Oi1O_dataout <= wire_nli1ii01l_w_lg_dataout46467w(0) OR NOT(nl0iOilli); + wire_nli00Oi1O_w_lg_dataout47422w(0) <= wire_nli00Oi1O_dataout AND wire_nli00OO1O_w_lg_dataout47421w(0); + wire_nli00Oii_dataout <= wire_nli0O1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00Oiii_dataout <= wire_nli1ii00O_w_lg_dataout46463w(0) OR NOT(nl0iOilli); + wire_nli00Oiii_w_lg_dataout47302w(0) <= wire_nli00Oiii_dataout AND wire_nli0i11Ol_w_lg_dataout47301w(0); + wire_nli00Oiil_dataout <= wire_nli1ii0ii_w_lg_dataout46462w(0) OR NOT(nl0iOilli); + wire_nli00Oiil_w_lg_dataout47272w(0) <= wire_nli00Oiil_dataout AND wire_nli0i11OO_w_lg_dataout47271w(0); + wire_nli00OiiO_dataout <= wire_nli1ii0il_w_lg_dataout46461w(0) OR NOT(nl0iOilli); + wire_nli00OiiO_w_lg_dataout47239w(0) <= wire_nli00OiiO_dataout AND wire_nli0i101i_w_lg_dataout47238w(0); + wire_nli00Oil_dataout <= wire_nli0O1iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00Oili_dataout <= wire_nli1ii0iO_w_lg_dataout46460w(0) OR NOT(nl0iOilli); + wire_nli00Oili_w_lg_dataout47208w(0) <= wire_nli00Oili_dataout AND wire_nli00OO0O_w_lg_dataout47207w(0); + wire_nli00Oill_dataout <= wire_w_lg_niOiiOi0O46459w(0) OR NOT(nl0iOilli); + wire_nli00Oill_w_lg_dataout47176w(0) <= wire_nli00Oill_dataout AND wire_nli00OOii_w_lg_dataout47175w(0); + wire_nli00OilO_dataout <= (NOT k_conf(218)) OR NOT(nl0iOilli); + wire_nli00OilO_w_lg_dataout47145w(0) <= wire_nli00OilO_dataout AND wire_nli0i100i_w_lg_dataout47144w(0); + wire_nli00OiO_dataout <= wire_nli0O1li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00OiOi_dataout <= (NOT k_conf(179)) OR NOT(nl0iOilli); + wire_nli00OiOi_w_lg_dataout47117w(0) <= wire_nli00OiOi_dataout AND wire_nli0i100l_w_lg_dataout47116w(0); + wire_nli00OiOl_dataout <= (NOT k_conf(180)) OR NOT(nl0iOilli); + wire_nli00OiOl_w_lg_dataout47086w(0) <= wire_nli00OiOl_dataout AND wire_nli00OOil_w_lg_dataout47085w(0); + wire_nli00OiOO_dataout <= (NOT k_conf(181)) OR NOT(nl0iOilli); + wire_nli00OiOO_w_lg_dataout47053w(0) <= wire_nli00OiOO_dataout AND wire_nli00OOiO_w_lg_dataout47052w(0); + wire_nli00Ol0i_dataout <= (NOT k_conf(185)) OR NOT(nl0iOilli); + wire_nli00Ol0i_w_lg_dataout46937w(0) <= wire_nli00Ol0i_dataout AND wire_nli0i10iO_w_lg_dataout46936w(0); + wire_nli00Ol0l_dataout <= (NOT k_conf(186)) OR NOT(nl0iOilli); + wire_nli00Ol0l_w_lg_dataout46908w(0) <= wire_nli00Ol0l_dataout AND wire_nli00OOlO_w_lg_dataout46907w(0); + wire_nli00Ol0O_dataout <= (NOT k_conf(187)) OR NOT(nl0iOilli); + wire_nli00Ol0O_w_lg_dataout46880w(0) <= wire_nli00Ol0O_dataout AND wire_nli00OOOi_w_lg_dataout46879w(0); + wire_nli00Ol1i_dataout <= (NOT k_conf(182)) OR NOT(nl0iOilli); + wire_nli00Ol1i_w_lg_dataout47023w(0) <= wire_nli00Ol1i_dataout AND wire_nli00OOli_w_lg_dataout47022w(0); + wire_nli00Ol1l_dataout <= (NOT k_conf(183)) OR NOT(nl0iOilli); + wire_nli00Ol1l_w_lg_dataout46994w(0) <= wire_nli00Ol1l_dataout AND wire_nli0i1Oli_w_lg_dataout46993w(0); + wire_nli00Ol1O_dataout <= (NOT k_conf(184)) OR NOT(nl0iOilli); + wire_nli00Ol1O_w_lg_dataout46966w(0) <= wire_nli00Ol1O_dataout AND wire_nli0i10il_w_lg_dataout46965w(0); + wire_nli00Oli_dataout <= wire_nli0O1ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00Olii_dataout <= (NOT k_conf(188)) OR NOT(nl0iOilli); + wire_nli00Olii_w_lg_dataout46852w(0) <= wire_nli00Olii_dataout AND wire_nli00OOOl_w_lg_dataout46851w(0); + wire_nli00Olil_dataout <= (NOT k_conf(189)) OR NOT(nl0iOilli); + wire_nli00Olil_w_lg_dataout46825w(0) <= wire_nli00Olil_dataout AND wire_nli00OOOO_w_lg_dataout46824w(0); + wire_nli00OliO_dataout <= (NOT k_conf(190)) OR NOT(nl0iOilli); + wire_nli00OliO_w_lg_dataout46798w(0) <= wire_nli00OliO_dataout AND wire_nli0i10Ol_w_lg_dataout46797w(0); + wire_nli00Oll_dataout <= wire_nli0O1lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00Olli_dataout <= (NOT k_conf(191)) OR NOT(nl0iOilli); + wire_nli00Olli_w_lg_dataout46771w(0) <= wire_nli00Olli_dataout AND wire_nli0i10OO_w_lg_dataout46770w(0); + wire_nli00Olll_dataout <= wire_nlill0Oll_w_lg_nli1il10l43974w(0) OR NOT(nl0iOiliO); + wire_nli00Olll_w_lg_dataout47719w(0) <= wire_nli00Olll_dataout AND wire_nli0i111O_w_lg_dataout47718w(0); + wire_nli00OllO_dataout <= wire_nlill0Oll_w_lg_nli1il10O43948w(0) OR NOT(nl0iOiliO); + wire_nli00OllO_w_lg_dataout47681w(0) <= wire_nli00OllO_dataout AND wire_nli0i110i_w_lg_dataout47680w(0); + wire_nli00OlO_dataout <= wire_nli0O1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00OlOi_dataout <= wire_nlill0Oll_w_lg_nli1il10i46430w(0) OR NOT(nl0iOiliO); + wire_nli00OlOl_dataout <= wire_nlill0Oll_w_lg_nli1il11O46429w(0) OR NOT(nl0iOiliO); + wire_nli00OlOl_w_lg_dataout47580w(0) <= wire_nli00OlOl_dataout AND wire_nli0i110l_w_lg_dataout47579w(0); + wire_nli00OlOO_dataout <= wire_nlill0Oll_w_lg_nli1il11i46428w(0) OR NOT(nl0iOiliO); + wire_nli00OlOO_w_lg_dataout47517w(0) <= wire_nli00OlOO_dataout AND wire_nli0i11ii_w_lg_dataout47516w(0); + wire_nli00OO0i_dataout <= wire_nli1iiOli_w_lg_dataout46424w(0) OR NOT(nl0iOiliO); + wire_nli00OO0i_w_lg_dataout47392w(0) <= wire_nli00OO0i_dataout AND wire_nli0i11ll_w_lg_dataout47391w(0); + wire_nli00OO0l_dataout <= wire_nli1iiOiO_w_lg_dataout46423w(0) OR NOT(nl0iOiliO); + wire_nli00OO0l_w_lg_dataout47362w(0) <= wire_nli00OO0l_dataout AND wire_nli0i11lO_w_lg_dataout47361w(0); + wire_nli00OO0O_dataout <= wire_nlOi00O1O_w_lg_dataout9870w(0) OR NOT(nl0iOiliO); + wire_nli00OO0O_w_lg_dataout47207w(0) <= wire_nli00OO0O_dataout AND wire_nli0i101l_w_lg_dataout47206w(0); + wire_nli00OO1i_dataout <= wire_nlill0Oll_w_lg_nli1iiOOO46427w(0) OR NOT(nl0iOiliO); + wire_nli00OO1i_w_lg_dataout47483w(0) <= wire_nli00OO1i_dataout AND wire_nli0i11il_w_lg_dataout47482w(0); + wire_nli00OO1l_dataout <= wire_nlill0Oll_w_lg_nli1iiOOl46426w(0) OR NOT(nl0iOiliO); + wire_nli00OO1l_w_lg_dataout47453w(0) <= wire_nli00OO1l_dataout AND wire_nli0i11iO_w_lg_dataout47452w(0); + wire_nli00OO1O_dataout <= wire_nli1iiOll_w_lg_dataout46425w(0) OR NOT(nl0iOiliO); + wire_nli00OO1O_w_lg_dataout47421w(0) <= wire_nli00OO1O_dataout AND wire_nli0i1lOl_w_lg_dataout47420w(0); + wire_nli00OOi_dataout <= wire_nli0O1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00OOii_dataout <= wire_nlOi00O0i_w_lg_dataout9865w(0) OR NOT(nl0iOiliO); + wire_nli00OOii_w_lg_dataout47175w(0) <= wire_nli00OOii_dataout AND wire_nli0i101O_w_lg_dataout47174w(0); + wire_nli00OOil_dataout <= wire_nlOiillOl_w_lg_dataout9855w(0) OR NOT(nl0iOiliO); + wire_nli00OOil_w_lg_dataout47085w(0) <= wire_nli00OOil_dataout AND wire_nli0i100O_w_lg_dataout47084w(0); + wire_nli00OOiO_dataout <= wire_nlOiillOO_w_lg_dataout9853w(0) OR NOT(nl0iOiliO); + wire_nli00OOiO_w_lg_dataout47052w(0) <= wire_nli00OOiO_dataout AND wire_nli0i10ii_w_lg_dataout47051w(0); + wire_nli00OOl_dataout <= wire_nli0O1OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00OOli_dataout <= wire_nlOiilO1i_w_lg_dataout9851w(0) OR NOT(nl0iOiliO); + wire_nli00OOli_w_lg_dataout47022w(0) <= wire_nli00OOli_dataout AND wire_nli0i01il_w_lg_dataout47021w(0); + wire_nli00OOll_dataout <= wire_nlOiilO1l_w_lg_dataout9857w(0) OR NOT(nl0iOiliO); + wire_nli00OOlO_dataout <= wire_nli1iiiil_w_lg_dataout46422w(0) OR NOT(nl0iOiliO); + wire_nli00OOlO_w_lg_dataout46907w(0) <= wire_nli00OOlO_dataout AND wire_nli0i10li_w_lg_dataout46906w(0); + wire_nli00OOO_dataout <= wire_nli0O01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli00OOOi_dataout <= wire_nli1iiiii_w_lg_dataout46421w(0) OR NOT(nl0iOiliO); + wire_nli00OOOi_w_lg_dataout46879w(0) <= wire_nli00OOOi_dataout AND wire_nli0i10ll_w_lg_dataout46878w(0); + wire_nli00OOOl_dataout <= wire_nl1000i_w_lg_niOO0ili46420w(0) OR NOT(nl0iOiliO); + wire_nli00OOOl_w_lg_dataout46851w(0) <= wire_nli00OOOl_dataout AND wire_nli0i01Oi_w_lg_dataout46850w(0); + wire_nli00OOOO_dataout <= wire_nli1iii0O_w_lg_dataout46419w(0) OR NOT(nl0iOiliO); + wire_nli00OOOO_w_lg_dataout46824w(0) <= wire_nli00OOOO_dataout AND wire_nli0i01Ol_w_lg_dataout46823w(0); + wire_nli01l0i_dataout <= wire_nli0iO0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01l0l_dataout <= wire_nli0iO0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01l0O_dataout <= wire_nli0iO0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01l1i_dataout <= wire_nli0OOOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01l1l_dataout <= wire_nli0OOOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01l1O_dataout <= wire_nli0iO1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01lii_dataout <= wire_nli0iOii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01lil_dataout <= wire_nli0iOil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01liO_dataout <= wire_nli0iOiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01lli_dataout <= wire_nli0iOli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01lll_dataout <= wire_nli0iOll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01llO_dataout <= wire_nli0iOlO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01lOi_dataout <= wire_nli0iOOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01lOl_dataout <= wire_nli0iOOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01lOO_dataout <= wire_nli0iOOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01O0i_dataout <= wire_nli0l1lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01O0l_dataout <= wire_nli0l1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01O0O_dataout <= wire_nli0l1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01O1i_dataout <= wire_nli0l11i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01O1l_dataout <= wire_nli0l11l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01O1O_dataout <= wire_nli0l11O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01Oii_dataout <= wire_nli0l1OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01Oil_dataout <= wire_nli0l01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01OiO_dataout <= wire_nli0l01l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01Oli_dataout <= wire_nli0l01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01Oll_dataout <= wire_nli0l00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01OlO_dataout <= wire_nli0l10i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01OOi_dataout <= wire_nli0l10l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01OOl_dataout <= wire_nli0l10O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli01OOO_dataout <= wire_nli0l1ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i000i_dataout <= wire_nlill0Oll_w_lg_nli11iill46316w(0) OR NOT(nl0iOl11O); + wire_nli0i000i_w_lg_dataout47415w(0) <= wire_nli0i000i_dataout AND wire_nli0i0lll_w_lg_dataout47414w(0); + wire_nli0i000l_dataout <= wire_nlill0Oll_w_lg_nli11ilil46315w(0) OR NOT(nl0iOl11O); + wire_nli0i000l_w_lg_dataout47385w(0) <= wire_nli0i000l_dataout AND wire_nli0i0llO_w_lg_dataout47384w(0); + wire_nli0i000O_dataout <= wire_nlill0Oll_w_lg_nli11iliO46314w(0) OR NOT(nl0iOl11O); + wire_nli0i000O_w_lg_dataout47354w(0) <= wire_nli0i000O_dataout AND wire_nli0i0lOi_w_lg_dataout47353w(0); + wire_nli0i001i_dataout <= wire_nlill0Oll_w_lg_nli11illO44166w(0) OR NOT(nl0iOl11O); + wire_nli0i001i_w_lg_dataout47674w(0) <= wire_nli0i001i_dataout AND wire_nli0i0l1O_w_lg_dataout47673w(0); + wire_nli0i001l_dataout <= (NOT k_conf(96)) OR NOT(nl0iOl11O); + wire_nli0i001l_w_lg_dataout47607w(0) <= wire_nli0i001l_dataout AND wire_nli0i0l0l_w_lg_dataout47606w(0); + wire_nli0i001O_dataout <= wire_nliiOiilO_w_lg_nli11l1ll46317w(0) OR NOT(nl0iOl11O); + wire_nli0i001O_w_lg_dataout47446w(0) <= wire_nli0i001O_dataout AND wire_nli0i0lli_w_lg_dataout47445w(0); + wire_nli0i00i_dataout <= wire_nli0Oi0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i00ii_dataout <= wire_nlill0Oll_w_lg_nli11illi46313w(0) OR NOT(nl0iOl11O); + wire_nli0i00ii_w_lg_dataout47323w(0) <= wire_nli0i00ii_dataout AND wire_nli0i0lOl_w_lg_dataout47322w(0); + wire_nli0i00il_dataout <= wire_nl1000i_w_lg_niOOl1il46312w(0) OR NOT(nl0iOl11O); + wire_nli0i00il_w_lg_dataout47294w(0) <= wire_nli0i00il_dataout AND wire_nli0i0lOO_w_lg_dataout47293w(0); + wire_nli0i00iO_dataout <= wire_nl1000i_w_lg_niOOil0i46311w(0) OR NOT(nl0iOl11O); + wire_nli0i00iO_w_lg_dataout47263w(0) <= wire_nli0i00iO_dataout AND wire_nli0i0O1i_w_lg_dataout47262w(0); + wire_nli0i00l_dataout <= wire_nli0Oi0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i00li_dataout <= wire_nliiOiilO_w_lg_nli11ilOi46310w(0) OR NOT(nl0iOl11O); + wire_nli0i00li_w_lg_dataout47231w(0) <= wire_nli0i00li_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47230w(0); + wire_nli0i00ll_dataout <= wire_nl1000i_w_lg_niOOil0l46309w(0) OR NOT(nl0iOl11O); + wire_nli0i00ll_w_lg_dataout46958w(0) <= wire_nli0i00ll_dataout AND wire_nli0i0iiO_w_lg_dataout46957w(0); + wire_nli0i00lO_dataout <= wire_nl1000i_w_lg_niOOil0O46308w(0) OR NOT(nl0iOl11O); + wire_nli0i00lO_w_lg_dataout46929w(0) <= wire_nli0i00lO_dataout AND wire_nli0i0ili_w_lg_dataout46928w(0); + wire_nli0i00O_dataout <= wire_nli0Oiii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i00Oi_dataout <= wire_nl1000i_w_lg_niOOilii46307w(0) OR NOT(nl0iOl11O); + wire_nli0i00Oi_w_lg_dataout46899w(0) <= wire_nli0i00Oi_dataout AND wire_nli0i0ill_w_lg_dataout46898w(0); + wire_nli0i00Ol_dataout <= wire_nl1000i_w_lg_niOOilil46306w(0) OR NOT(nl0iOl11O); + wire_nli0i00Ol_w_lg_dataout46872w(0) <= wire_nli0i00Ol_dataout AND wire_nli0i0ilO_w_lg_dataout46871w(0); + wire_nli0i00OO_dataout <= wire_nl1000i_w_lg_niOOiliO46305w(0) OR NOT(nl0iOl11O); + wire_nli0i00OO_w_lg_dataout46845w(0) <= wire_nli0i00OO_dataout AND wire_nli0i0iOi_w_lg_dataout46844w(0); + wire_nli0i010i_dataout <= wire_nli1l1ill_w_lg_dataout46326w(0) OR NOT(nl0iOil0l); + wire_nli0i010i_w_lg_dataout47142w(0) <= wire_nli0i010i_dataout AND wire_nli0i1O0l_dataout; + wire_nli0i010l_dataout <= wire_nli1l1ilO_w_lg_dataout46325w(0) OR NOT(nl0iOil0l); + wire_nli0i010l_w_lg_dataout47114w(0) <= wire_nli0i010l_dataout AND wire_nli0i1O0O_dataout; + wire_nli0i010O_dataout <= wire_nilO010i_w_lg_dataout25163w(0) OR NOT(nl0iOil0l); + wire_nli0i010O_w_lg_dataout47082w(0) <= wire_nli0i010O_dataout AND wire_nli0i1Oii_dataout; + wire_nli0i011i_dataout <= (NOT k_conf(307)) OR NOT(nl0iOil0l); + wire_nli0i011l_dataout <= wire_nli1l1iiO_w_lg_dataout46328w(0) OR NOT(nl0iOil0l); + wire_nli0i011l_w_lg_dataout47205w(0) <= wire_nli0i011l_dataout AND wire_nli0i1l1i_dataout; + wire_nli0i011O_dataout <= wire_nli1l1ili_w_lg_dataout46327w(0) OR NOT(nl0iOil0l); + wire_nli0i011O_w_lg_dataout47173w(0) <= wire_nli0i011O_dataout AND wire_nli0i1l1l_dataout; + wire_nli0i01i_dataout <= wire_nli0Oi1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i01ii_dataout <= wire_nilO010l_w_lg_dataout8971w(0) OR NOT(nl0iOil0l); + wire_nli0i01ii_w_lg_dataout47049w(0) <= wire_nli0i01ii_dataout AND wire_nli0i1Oil_dataout; + wire_nli0i01il_dataout <= wire_nilO010O_w_lg_dataout8970w(0) OR NOT(nl0iOil0l); + wire_nli0i01il_w_lg_dataout47021w(0) <= wire_nli0i01il_dataout AND wire_nli0i1OiO_dataout; + wire_nli0i01iO_dataout <= wire_w_lg_niOiiOiii46324w(0) OR NOT(nl0iOil0l); + wire_nli0i01iO_w_lg_dataout46964w(0) <= wire_nli0i01iO_dataout AND wire_nli0i1Oll_dataout; + wire_nli0i01l_dataout <= wire_nli0Oi1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i01li_dataout <= wire_nl1000i_w_lg_nl10illl46323w(0) OR NOT(nl0iOil0l); + wire_nli0i01li_w_lg_dataout46935w(0) <= wire_nli0i01li_dataout AND wire_nli0i1OlO_dataout; + wire_nli0i01ll_dataout <= wire_nl1000i_w_lg_nl10iili46322w(0) OR NOT(nl0iOil0l); + wire_nli0i01ll_w_lg_dataout46905w(0) <= wire_nli0i01ll_dataout AND wire_nli0i1OOi_dataout; + wire_nli0i01lO_dataout <= wire_nl1000i_w_lg_nl10iill46321w(0) OR NOT(nl0iOil0l); + wire_nli0i01lO_w_lg_dataout46877w(0) <= wire_nli0i01lO_dataout AND wire_nli0i1OOl_dataout; + wire_nli0i01O_dataout <= wire_nli0Oi0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i01Oi_dataout <= wire_nl1000i_w_lg_nl10iilO46320w(0) OR NOT(nl0iOil0l); + wire_nli0i01Oi_w_lg_dataout46850w(0) <= wire_nli0i01Oi_dataout AND wire_nli0i10lO_dataout; + wire_nli0i01Ol_dataout <= wire_nl1000i_w_lg_nl10iiOi46319w(0) OR NOT(nl0iOil0l); + wire_nli0i01Ol_w_lg_dataout46823w(0) <= wire_nli0i01Ol_dataout AND wire_nli0i10Oi_dataout; + wire_nli0i01OO_dataout <= wire_nlill0Oll_w_lg_nli11illl44167w(0) OR NOT(nl0iOl11O); + wire_nli0i01OO_w_lg_dataout47711w(0) <= wire_nli0i01OO_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOl11l47151w47710w(0); + wire_nli0i0i0i_dataout <= (NOT k_conf(99)) OR NOT(nl0iOl11l); + wire_nli0i0i0i_w_lg_dataout47108w(0) <= wire_nli0i0i0i_dataout AND wire_nli0ii1il_w_lg_dataout47107w(0); + wire_nli0i0i0l_dataout <= (NOT k_conf(100)) OR NOT(nl0iOl11l); + wire_nli0i0i0l_w_lg_dataout47076w(0) <= wire_nli0i0i0l_dataout AND wire_nli0ii1iO_w_lg_dataout47075w(0); + wire_nli0i0i0O_dataout <= (NOT k_conf(101)) OR NOT(nl0iOl11l); + wire_nli0i0i0O_w_lg_dataout47043w(0) <= wire_nli0i0i0O_dataout AND wire_nli0ii1li_w_lg_dataout47042w(0); + wire_nli0i0i1i_dataout <= wire_nl1000i_w_lg_niOOilli46304w(0) OR NOT(nl0iOl11O); + wire_nli0i0i1i_w_lg_dataout46818w(0) <= wire_nli0i0i1i_dataout AND wire_nli0i0iOl_w_lg_dataout46817w(0); + wire_nli0i0i1l_dataout <= wire_nl1000i_w_lg_niOOilll46303w(0) OR NOT(nl0iOl11O); + wire_nli0i0i1l_w_lg_dataout46791w(0) <= wire_nli0i0i1l_dataout AND wire_nli0i0iOO_w_lg_dataout46790w(0); + wire_nli0i0i1O_dataout <= wire_nl1000i_w_lg_niOOillO46302w(0) OR NOT(nl0iOl11O); + wire_nli0i0i1O_w_lg_dataout46764w(0) <= wire_nli0i0i1O_dataout AND wire_nli0i0l1i_w_lg_dataout46763w(0); + wire_nli0i0ii_dataout <= wire_nli0Oiil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0iii_dataout <= (NOT k_conf(102)) OR NOT(nl0iOl11l); + wire_nli0i0iii_w_lg_dataout47015w(0) <= wire_nli0i0iii_dataout AND wire_nli0ii1ll_w_lg_dataout47014w(0); + wire_nli0i0iil_dataout <= (NOT k_conf(103)) OR NOT(nl0iOl11l); + wire_nli0i0iil_w_lg_dataout46987w(0) <= wire_nli0i0iil_dataout AND wire_nli0ii1lO_w_lg_dataout46986w(0); + wire_nli0i0iiO_dataout <= (NOT k_conf(104)) OR NOT(nl0iOl11l); + wire_nli0i0iiO_w_lg_dataout46957w(0) <= wire_nli0i0iiO_dataout AND wire_nli0ii1Oi_w_lg_dataout46956w(0); + wire_nli0i0il_dataout <= wire_nli0OiiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0ili_dataout <= (NOT k_conf(105)) OR NOT(nl0iOl11l); + wire_nli0i0ili_w_lg_dataout46928w(0) <= wire_nli0i0ili_dataout AND wire_nli0ii1Ol_w_lg_dataout46927w(0); + wire_nli0i0ill_dataout <= (NOT k_conf(106)) OR NOT(nl0iOl11l); + wire_nli0i0ill_w_lg_dataout46898w(0) <= wire_nli0i0ill_dataout AND wire_nli0ii1OO_w_lg_dataout46897w(0); + wire_nli0i0ilO_dataout <= (NOT k_conf(107)) OR NOT(nl0iOl11l); + wire_nli0i0ilO_w_lg_dataout46871w(0) <= wire_nli0i0ilO_dataout AND wire_nli0ii01i_w_lg_dataout46870w(0); + wire_nli0i0iO_dataout <= wire_nli0Oili_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0iOi_dataout <= (NOT k_conf(108)) OR NOT(nl0iOl11l); + wire_nli0i0iOi_w_lg_dataout46844w(0) <= wire_nli0i0iOi_dataout AND wire_nli0ii01l_w_lg_dataout46843w(0); + wire_nli0i0iOl_dataout <= (NOT k_conf(109)) OR NOT(nl0iOl11l); + wire_nli0i0iOl_w_lg_dataout46817w(0) <= wire_nli0i0iOl_dataout AND wire_nli0ii01O_w_lg_dataout46816w(0); + wire_nli0i0iOO_dataout <= (NOT k_conf(110)) OR NOT(nl0iOl11l); + wire_nli0i0iOO_w_lg_dataout46790w(0) <= wire_nli0i0iOO_dataout AND wire_nli0ii00i_w_lg_dataout46789w(0); + wire_nli0i0l0i_dataout <= wire_nl0l0li0i_w_lg_dataout46240w(0) OR NOT(niOiiOiil); + wire_nli0i0l0i_w_lg_dataout47641w(0) <= wire_nli0i0l0i_dataout AND wire_nli0i0O0O_w_lg_dataout47640w(0); + wire_nli0i0l0l_dataout <= wire_nl0l0li0O_w_lg_dataout46239w(0) OR NOT(niOiiOiil); + wire_nli0i0l0l_w_lg_dataout47606w(0) <= wire_nli0i0l0l_dataout AND wire_nli0i0Oii_w_lg_dataout47605w(0); + wire_nli0i0l0O_dataout <= wire_nl0l0liil_w_lg_dataout46238w(0) OR NOT(niOiiOiil); + wire_nli0i0l0O_w_lg_dataout47572w(0) <= wire_nli0i0l0O_dataout AND wire_nli0i0Oil_w_lg_dataout47571w(0); + wire_nli0i0l1i_dataout <= (NOT k_conf(111)) OR NOT(nl0iOl11l); + wire_nli0i0l1i_w_lg_dataout46763w(0) <= wire_nli0i0l1i_dataout AND wire_nli0ii00l_w_lg_dataout46762w(0); + wire_nli0i0l1l_dataout <= wire_nl0l0l0OO_w_lg_dataout46242w(0) OR NOT(niOiiOiil); + wire_nli0i0l1l_w_lg_dataout47709w(0) <= wire_nli0i0l1l_dataout AND wire_nli0i0O0i_w_lg_dataout47708w(0); + wire_nli0i0l1O_dataout <= wire_nl0l0li1l_w_lg_dataout46241w(0) OR NOT(niOiiOiil); + wire_nli0i0l1O_w_lg_dataout47673w(0) <= wire_nli0i0l1O_dataout AND wire_nli0i0O0l_w_lg_dataout47672w(0); + wire_nli0i0li_dataout <= wire_nli0Oill_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0lii_dataout <= wire_nlill0Oll_w_lg_nl0l0liOi46237w(0) OR NOT(niOiiOiil); + wire_nli0i0lii_w_lg_dataout47542w(0) <= wire_nli0i0lii_dataout AND wire_nli0i0OiO_w_lg_dataout47541w(0); + wire_nli0i0lil_dataout <= wire_nlill0Oll_w_lg_nl0l0liOl46236w(0) OR NOT(niOiiOiil); + wire_nli0i0lil_w_lg_dataout47510w(0) <= wire_nli0i0lil_dataout AND wire_nli0i0Oli_w_lg_dataout47509w(0); + wire_nli0i0liO_dataout <= wire_nlill0Oll_w_lg_nl0l0liOO46235w(0) OR NOT(niOiiOiil); + wire_nli0i0liO_w_lg_dataout47476w(0) <= wire_nli0i0liO_dataout AND wire_nli0i0Oll_w_lg_dataout47475w(0); + wire_nli0i0ll_dataout <= wire_nli0OilO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0lli_dataout <= wire_nlill0Oll_w_lg_nl0l0ll1i46234w(0) OR NOT(niOiiOiil); + wire_nli0i0lli_w_lg_dataout47445w(0) <= wire_nli0i0lli_dataout AND wire_nli0i0OlO_w_lg_dataout47444w(0); + wire_nli0i0lll_dataout <= wire_nlill0Oll_w_lg_nl0l0ll1l46233w(0) OR NOT(niOiiOiil); + wire_nli0i0lll_w_lg_dataout47414w(0) <= wire_nli0i0lll_dataout AND wire_nli0i0OOi_w_lg_dataout47413w(0); + wire_nli0i0llO_dataout <= wire_nlill0Oll_w_lg_nl0l0ll1O46232w(0) OR NOT(niOiiOiil); + wire_nli0i0llO_w_lg_dataout47384w(0) <= wire_nli0i0llO_dataout AND wire_nli0i0OOl_w_lg_dataout47383w(0); + wire_nli0i0lO_dataout <= wire_nli0OiOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0lOi_dataout <= wire_nlill0Oll_w_lg_nl0l0ll0i46231w(0) OR NOT(niOiiOiil); + wire_nli0i0lOi_w_lg_dataout47353w(0) <= wire_nli0i0lOi_dataout AND wire_nli0i0OOO_w_lg_dataout47352w(0); + wire_nli0i0lOl_dataout <= wire_nlill0Oll_w_lg_nl0l0ll0l46230w(0) OR NOT(niOiiOiil); + wire_nli0i0lOl_w_lg_dataout47322w(0) <= wire_nli0i0lOl_dataout AND wire_nli0ii11i_w_lg_dataout47321w(0); + wire_nli0i0lOO_dataout <= wire_nlill0Oll_w_lg_nl0l0ll0O46229w(0) OR NOT(niOiiOiil); + wire_nli0i0lOO_w_lg_dataout47293w(0) <= wire_nli0i0lOO_dataout AND wire_nli0ii11l_w_lg_dataout47292w(0); + wire_nli0i0O0i_dataout <= wire_nlill0Oll_w_lg_nl0l0O1iO46274w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii00O_dataout; + wire_nli0i0O0i_w_lg_dataout47708w(0) <= wire_nli0i0O0i_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47707w(0); + wire_nli0i0O0l_dataout <= wire_nlill0Oll_w_lg_nl0l0O1li46273w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0ii_dataout; + wire_nli0i0O0l_w_lg_dataout47672w(0) <= wire_nli0i0O0l_dataout AND wire_nli0il10l_w_lg_dataout47671w(0); + wire_nli0i0O0O_dataout <= wire_nlill0Oll_w_lg_nl0l0O1ll46272w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0il_dataout; + wire_nli0i0O0O_w_lg_dataout47640w(0) <= wire_nli0i0O0O_dataout AND wire_nli0iiiiO_w_lg_dataout47639w(0); + wire_nli0i0O1i_dataout <= wire_nlill0Oll_w_lg_nl0l0llii46228w(0) OR NOT(niOiiOiil); + wire_nli0i0O1i_w_lg_dataout47262w(0) <= wire_nli0i0O1i_dataout AND wire_nli0ii11O_w_lg_dataout47261w(0); + wire_nli0i0O1l_dataout <= wire_nlill0Oll_w_lg_nl0l0llil46227w(0) OR NOT(niOiiOiil); + wire_nli0i0O1l_w_lg_dataout47229w(0) <= wire_nli0i0O1l_dataout AND wire_nli0ii10i_w_lg_dataout47228w(0); + wire_nli0i0Oi_dataout <= wire_nli0OiOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0Oii_dataout <= wire_nlill0Oll_w_lg_nl0l0O1lO46271w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0iO_dataout; + wire_nli0i0Oii_w_lg_dataout47605w(0) <= wire_nli0i0Oii_dataout AND wire_nli0iiili_w_lg_dataout47604w(0); + wire_nli0i0Oil_dataout <= wire_nlill0Oll_w_lg_nl0l0O1Oi46270w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0li_dataout; + wire_nli0i0Oil_w_lg_dataout47571w(0) <= wire_nli0i0Oil_dataout AND wire_nli0iiill_w_lg_dataout47570w(0); + wire_nli0i0OiO_dataout <= wire_nlill0Oll_w_lg_nl0l0O1Ol46269w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0ll_dataout; + wire_nli0i0OiO_w_lg_dataout47541w(0) <= wire_nli0i0OiO_dataout AND wire_nli0iiilO_w_lg_dataout47540w(0); + wire_nli0i0Ol_dataout <= wire_nli0OiOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0Oli_dataout <= wire_nlill0Oll_w_lg_nl0l0O1OO46268w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0lO_dataout; + wire_nli0i0Oli_w_lg_dataout47509w(0) <= wire_nli0i0Oli_dataout AND wire_nli0iiiOi_w_lg_dataout47508w(0); + wire_nli0i0Oll_dataout <= wire_nlill0Oll_w_lg_nl0l0O01i46267w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0Oi_dataout; + wire_nli0i0Oll_w_lg_dataout47475w(0) <= wire_nli0i0Oll_dataout AND wire_nli0iiiOl_w_lg_dataout47474w(0); + wire_nli0i0OlO_dataout <= wire_nlill0Oll_w_lg_nl0l0O01l46266w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0Ol_dataout; + wire_nli0i0OlO_w_lg_dataout47444w(0) <= wire_nli0i0OlO_dataout AND wire_nli0iiiOO_w_lg_dataout47443w(0); + wire_nli0i0OO_dataout <= wire_nli0Ol1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i0OOi_dataout <= wire_nlill0Oll_w_lg_nl0l0O01O46265w(0) WHEN niOiiOili = '1' ELSE wire_nli0ii0OO_dataout; + wire_nli0i0OOi_w_lg_dataout47413w(0) <= wire_nli0i0OOi_dataout AND wire_nli0iil1i_w_lg_dataout47412w(0); + wire_nli0i0OOl_dataout <= wire_nlill0Oll_w_lg_nl0l0O00i46264w(0) WHEN niOiiOili = '1' ELSE wire_nli0iii1i_dataout; + wire_nli0i0OOl_w_lg_dataout47383w(0) <= wire_nli0i0OOl_dataout AND wire_nli0iil1l_w_lg_dataout47382w(0); + wire_nli0i0OOO_dataout <= wire_nlill0Oll_w_lg_nl0l0O00l46263w(0) WHEN niOiiOili = '1' ELSE wire_nli0iii1l_dataout; + wire_nli0i0OOO_w_lg_dataout47352w(0) <= wire_nli0i0OOO_dataout AND wire_nli0iil1O_w_lg_dataout47351w(0); + wire_nli0i100i_dataout <= (NOT k_conf(167)) OR NOT(nl0iOilil); + wire_nli0i100i_w_lg_dataout47144w(0) <= wire_nli0i100i_dataout AND wire_nli0i1l1O_w_lg_dataout47143w(0); + wire_nli0i100l_dataout <= (NOT k_conf(131)) OR NOT(nl0iOilil); + wire_nli0i100l_w_lg_dataout47116w(0) <= wire_nli0i100l_dataout AND wire_nli0i1l0i_w_lg_dataout47115w(0); + wire_nli0i100O_dataout <= (NOT k_conf(132)) OR NOT(nl0iOilil); + wire_nli0i100O_w_lg_dataout47084w(0) <= wire_nli0i100O_dataout AND wire_nli0i1l0l_w_lg_dataout47083w(0); + wire_nli0i101i_dataout <= wire_nli1ill1i_w_lg_dataout46397w(0) OR NOT(nl0iOilil); + wire_nli0i101i_w_lg_dataout47238w(0) <= wire_nli0i101i_dataout AND wire_nli0i1iOO_w_lg_dataout47237w(0); + wire_nli0i101l_dataout <= wire_nli1ill1l_w_lg_dataout46396w(0) OR NOT(nl0iOilil); + wire_nli0i101l_w_lg_dataout47206w(0) <= wire_nli0i101l_dataout AND wire_nli0i011l_w_lg_dataout47205w(0); + wire_nli0i101O_dataout <= wire_nli1ill1O_w_lg_dataout46395w(0) OR NOT(nl0iOilil); + wire_nli0i101O_w_lg_dataout47174w(0) <= wire_nli0i101O_dataout AND wire_nli0i011O_w_lg_dataout47173w(0); + wire_nli0i10i_dataout <= wire_nli0O00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i10ii_dataout <= wire_nli1iliOl_w_lg_dataout46389w(0) OR NOT(nl0iOilil); + wire_nli0i10ii_w_lg_dataout47051w(0) <= wire_nli0i10ii_dataout AND wire_nli0i1l0O_w_lg_dataout47050w(0); + wire_nli0i10il_dataout <= (NOT k_port(0)) OR NOT(nl0iOilil); + wire_nli0i10il_w_lg_dataout46965w(0) <= wire_nli0i10il_dataout AND wire_nli0i01iO_w_lg_dataout46964w(0); + wire_nli0i10iO_dataout <= (NOT k_port(1)) OR NOT(nl0iOilil); + wire_nli0i10iO_w_lg_dataout46936w(0) <= wire_nli0i10iO_dataout AND wire_nli0i01li_w_lg_dataout46935w(0); + wire_nli0i10l_dataout <= wire_nli0O00O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i10li_dataout <= (NOT k_port(2)) OR NOT(nl0iOilil); + wire_nli0i10li_w_lg_dataout46906w(0) <= wire_nli0i10li_dataout AND wire_nli0i01ll_w_lg_dataout46905w(0); + wire_nli0i10ll_dataout <= (NOT k_port(3)) OR NOT(nl0iOilil); + wire_nli0i10ll_w_lg_dataout46878w(0) <= wire_nli0i10ll_dataout AND wire_nli0i01lO_w_lg_dataout46877w(0); + wire_nli0i10lO_dataout <= (NOT k_port(4)) OR NOT(nl0iOilil); + wire_nli0i10O_dataout <= wire_nli0O0ii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i10Oi_dataout <= (NOT k_port(5)) OR NOT(nl0iOilil); + wire_nli0i10Ol_dataout <= (NOT k_port(6)) OR NOT(nl0iOilil); + wire_nli0i10Ol_w_lg_dataout46797w(0) <= wire_nli0i10Ol_dataout AND wire_nli0i111i_dataout; + wire_nli0i10OO_dataout <= (NOT k_port(7)) OR NOT(nl0iOilil); + wire_nli0i10OO_w_lg_dataout46770w(0) <= wire_nli0i10OO_dataout AND wire_nli0i111l_dataout; + wire_nli0i110i_dataout <= wire_nli1illil_w_lg_dataout46415w(0) OR NOT(nl0iOilil); + wire_nli0i110i_w_lg_dataout47680w(0) <= wire_nli0i110i_dataout AND wire_nli0i1lil_w_lg_dataout47679w(0); + wire_nli0i110l_dataout <= (NOT k_conf(146)) OR NOT(nl0iOilil); + wire_nli0i110l_w_lg_dataout47579w(0) <= wire_nli0i110l_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOil0l44799w47578w(0); + wire_nli0i110O_dataout <= (NOT k_conf(147)) OR NOT(nl0iOilil); + wire_nli0i110O_w_lg_dataout47548w(0) <= wire_nli0i110O_dataout AND wire_nli0i1lli_w_lg_dataout47547w(0); + wire_nli0i111i_dataout <= wire_nlill0Oll_w_lg_nli1iiili46418w(0) OR NOT(nl0iOiliO); + wire_nli0i111l_dataout <= wire_nlill0Oll_w_lg_nli1iiill46417w(0) OR NOT(nl0iOiliO); + wire_nli0i111O_dataout <= wire_nli1illii_w_lg_dataout46416w(0) OR NOT(nl0iOilil); + wire_nli0i111O_w_lg_dataout47718w(0) <= wire_nli0i111O_dataout AND wire_nli0i1lii_w_lg_dataout47717w(0); + wire_nli0i11i_dataout <= wire_nli0O01l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i11ii_dataout <= (NOT k_conf(148)) OR NOT(nl0iOilil); + wire_nli0i11ii_w_lg_dataout47516w(0) <= wire_nli0i11ii_dataout AND wire_nli0i1lll_w_lg_dataout47515w(0); + wire_nli0i11il_dataout <= (NOT k_conf(149)) OR NOT(nl0iOilil); + wire_nli0i11il_w_lg_dataout47482w(0) <= wire_nli0i11il_dataout AND wire_nli0i1llO_w_lg_dataout47481w(0); + wire_nli0i11iO_dataout <= (NOT k_conf(150)) OR NOT(nl0iOilil); + wire_nli0i11iO_w_lg_dataout47452w(0) <= wire_nli0i11iO_dataout AND wire_nli0i1lOi_w_lg_dataout47451w(0); + wire_nli0i11l_dataout <= wire_nli0O01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i11li_dataout <= (NOT k_conf(151)) OR NOT(nl0iOilil); + wire_nli0i11ll_dataout <= (NOT k_conf(152)) OR NOT(nl0iOilil); + wire_nli0i11ll_w_lg_dataout47391w(0) <= wire_nli0i11ll_dataout AND wire_nli0i1lOO_w_lg_dataout47390w(0); + wire_nli0i11lO_dataout <= (NOT k_conf(153)) OR NOT(nl0iOilil); + wire_nli0i11lO_w_lg_dataout47361w(0) <= wire_nli0i11lO_dataout AND wire_nli0i1O1i_w_lg_dataout47360w(0); + wire_nli0i11O_dataout <= wire_nli0O00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i11Oi_dataout <= wire_nli1ill0i_w_lg_dataout46400w(0) OR NOT(nl0iOilil); + wire_nli0i11Oi_w_lg_dataout47330w(0) <= wire_nli0i11Oi_dataout AND wire_nli0i1O1l_w_lg_dataout47329w(0); + wire_nli0i11Ol_dataout <= wire_nli1ill0l_w_lg_dataout46399w(0) OR NOT(nl0iOilil); + wire_nli0i11Ol_w_lg_dataout47301w(0) <= wire_nli0i11Ol_dataout AND wire_nli0i1O1O_w_lg_dataout47300w(0); + wire_nli0i11OO_dataout <= wire_nli1ill0O_w_lg_dataout46398w(0) OR NOT(nl0iOilil); + wire_nli0i11OO_w_lg_dataout47271w(0) <= wire_nli0i11OO_dataout AND wire_nli0i1iOl_w_lg_dataout47270w(0); + wire_nli0i1i0i_dataout <= wire_nlill0Oll_w_lg_nli1iOiOl46377w(0) OR NOT(nl0iOilii); + wire_nli0i1i0i_w_lg_dataout47612w(0) <= wire_nli0i1i0i_dataout AND wire_nli00OlOi_dataout; + wire_nli0i1i0l_dataout <= wire_nliliO10i_w_lg_nli1iOiOi46376w(0) OR NOT(nl0iOilii); + wire_nli0i1i0O_dataout <= wire_nlill0Oll_w_lg_nli1iOili42902w(0) OR NOT(nl0iOilii); + wire_nli0i1i1i_dataout <= wire_nlill0Oll_w_lg_nli1iOl1l46380w(0) OR NOT(nl0iOilii); + wire_nli0i1i1l_dataout <= wire_nlill0Oll_w_lg_nli1iOl1i46379w(0) OR NOT(nl0iOilii); + wire_nli0i1i1O_dataout <= wire_nlill0Oll_w_lg_nli1iOiOO46378w(0) OR NOT(nl0iOilii); + wire_nli0i1ii_dataout <= wire_nli0O0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1iii_dataout <= wire_nlill0Oll_w_lg_nli1iOill42899w(0) OR NOT(nl0iOilii); + wire_nli0i1iil_dataout <= wire_nlill0Oll_w_lg_nli1iOilO42904w(0) OR NOT(nl0iOilii); + wire_nli0i1iiO_dataout <= wire_nlill0Oll_w_lg_nli1iOiiO46375w(0) OR NOT(nl0iOilii); + wire_nli0i1il_dataout <= wire_nli0O0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1ili_dataout <= wire_nliiOiilO_w_lg_nli1ilO1O46374w(0) OR NOT(nl0iOilii); + wire_nli0i1ill_dataout <= wire_nliliO10i_w_lg_nli1iOiil46373w(0) OR NOT(nl0iOilii); + wire_nli0i1ilO_dataout <= wire_nlill0Oll_w_lg_nli1iOi0l46372w(0) OR NOT(nl0iOilii); + wire_nli0i1iO_dataout <= wire_nli0O0li_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1iOi_dataout <= wire_nliliO10i_w_lg_nli1iOi0O46371w(0) OR NOT(nl0iOilii); + wire_nli0i1iOl_dataout <= wire_nlill0Oll_w_lg_nli1iOiii46370w(0) OR NOT(nl0iOilii); + wire_nli0i1iOl_w_lg_dataout47270w(0) <= wire_nli0i1iOl_dataout AND wire_nli0i1OOO_w_lg_dataout47269w(0); + wire_nli0i1iOO_dataout <= wire_nlill0Oll_w_lg_nli1iO0OO46369w(0) OR NOT(nl0iOilii); + wire_nli0i1iOO_w_lg_dataout47237w(0) <= wire_nli0i1iOO_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOil0O47059w47236w(0); + wire_nli0i1l0i_dataout <= wire_nlill0Oll_w_lg_nli1illOl46365w(0) OR NOT(nl0iOilii); + wire_nli0i1l0i_w_lg_dataout47115w(0) <= wire_nli0i1l0i_dataout AND wire_nli0i010l_w_lg_dataout47114w(0); + wire_nli0i1l0l_dataout <= wire_nl1000i_w_lg_niOOilOi46364w(0) OR NOT(nl0iOilii); + wire_nli0i1l0l_w_lg_dataout47083w(0) <= wire_nli0i1l0l_dataout AND wire_nli0i010O_w_lg_dataout47082w(0); + wire_nli0i1l0O_dataout <= wire_nl1000i_w_lg_niOlOill8545w(0) OR NOT(nl0iOilii); + wire_nli0i1l0O_w_lg_dataout47050w(0) <= wire_nli0i1l0O_dataout AND wire_nli0i01ii_w_lg_dataout47049w(0); + wire_nli0i1l1i_dataout <= wire_nlill0Oll_w_lg_nli1ilO1l46368w(0) OR NOT(nl0iOilii); + wire_nli0i1l1l_dataout <= wire_nlill0Oll_w_lg_nli1ilO1i46367w(0) OR NOT(nl0iOilii); + wire_nli0i1l1O_dataout <= wire_nlill0Oll_w_lg_nli1illOO46366w(0) OR NOT(nl0iOilii); + wire_nli0i1l1O_w_lg_dataout47143w(0) <= wire_nli0i1l1O_dataout AND wire_nli0i010i_w_lg_dataout47142w(0); + wire_nli0i1li_dataout <= wire_nli0O0ll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1lii_dataout <= (NOT k_conf(128)) OR NOT(nl0iOil0O); + wire_nli0i1lii_w_lg_dataout47717w(0) <= wire_nli0i1lii_dataout AND wire_nli0i1i1i_dataout; + wire_nli0i1lil_dataout <= (NOT k_conf(129)) OR NOT(nl0iOil0O); + wire_nli0i1lil_w_lg_dataout47679w(0) <= wire_nli0i1lil_dataout AND wire_nli0i1i1l_dataout; + wire_nli0i1liO_dataout <= (NOT k_conf(130)) OR NOT(nl0iOil0O); + wire_nli0i1liO_w_lg_dataout47646w(0) <= wire_nli0i1liO_dataout AND wire_nli0i1i1O_dataout; + wire_nli0i1ll_dataout <= wire_nli0O0lO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1lli_dataout <= (NOT k_conf(133)) OR NOT(nl0iOil0O); + wire_nli0i1lli_w_lg_dataout47547w(0) <= wire_nli0i1lli_dataout AND wire_nli0i1i0O_dataout; + wire_nli0i1lll_dataout <= (NOT k_conf(134)) OR NOT(nl0iOil0O); + wire_nli0i1lll_w_lg_dataout47515w(0) <= wire_nli0i1lll_dataout AND wire_nli0i1iii_dataout; + wire_nli0i1llO_dataout <= (NOT k_conf(135)) OR NOT(nl0iOil0O); + wire_nli0i1llO_w_lg_dataout47481w(0) <= wire_nli0i1llO_dataout AND wire_nli0i1iil_dataout; + wire_nli0i1lO_dataout <= wire_nli0O0Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1lOi_dataout <= (NOT k_conf(136)) OR NOT(nl0iOil0O); + wire_nli0i1lOi_w_lg_dataout47451w(0) <= wire_nli0i1lOi_dataout AND wire_nli0i1iiO_dataout; + wire_nli0i1lOl_dataout <= (NOT k_conf(137)) OR NOT(nl0iOil0O); + wire_nli0i1lOl_w_lg_dataout47420w(0) <= wire_nli0i1lOl_dataout AND wire_nli0i11li_dataout; + wire_nli0i1lOO_dataout <= (NOT k_conf(138)) OR NOT(nl0iOil0O); + wire_nli0i1lOO_w_lg_dataout47390w(0) <= wire_nli0i1lOO_dataout AND wire_nli0i1ili_dataout; + wire_nli0i1O0i_dataout <= (NOT k_conf(142)) OR NOT(nl0iOil0O); + wire_nli0i1O0l_dataout <= wire_nlill0Oll_w_lg_nli1l11ii46340w(0) OR NOT(nl0iOil0O); + wire_nli0i1O0O_dataout <= wire_nlill0Oll_w_lg_nli1l11il46339w(0) OR NOT(nl0iOil0O); + wire_nli0i1O1i_dataout <= (NOT k_conf(139)) OR NOT(nl0iOil0O); + wire_nli0i1O1i_w_lg_dataout47360w(0) <= wire_nli0i1O1i_dataout AND wire_nli0i1ill_dataout; + wire_nli0i1O1l_dataout <= (NOT k_conf(140)) OR NOT(nl0iOil0O); + wire_nli0i1O1l_w_lg_dataout47329w(0) <= wire_nli0i1O1l_dataout AND wire_nli0i1ilO_dataout; + wire_nli0i1O1O_dataout <= (NOT k_conf(141)) OR NOT(nl0iOil0O); + wire_nli0i1O1O_w_lg_dataout47300w(0) <= wire_nli0i1O1O_dataout AND wire_nli0i1iOi_dataout; + wire_nli0i1Oi_dataout <= wire_nli0O0Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1Oii_dataout <= wire_nlill0Oll_w_lg_nli1l11iO46338w(0) OR NOT(nl0iOil0O); + wire_nli0i1Oil_dataout <= wire_nlill0Oll_w_lg_nli1l11li46337w(0) OR NOT(nl0iOil0O); + wire_nli0i1OiO_dataout <= wire_nlill0Oll_w_lg_nli1l11ll46336w(0) OR NOT(nl0iOil0O); + wire_nli0i1Ol_dataout <= wire_nli0O0OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1Oli_dataout <= wire_nlill0Oll_w_lg_nli1l11lO46335w(0) OR NOT(nl0iOil0O); + wire_nli0i1Oli_w_lg_dataout46993w(0) <= wire_nli0i1Oli_dataout AND wire_nli00OOll_dataout; + wire_nli0i1Oll_dataout <= wire_nlill0Oll_w_lg_nli1l11Oi46334w(0) OR NOT(nl0iOil0O); + wire_nli0i1OlO_dataout <= wire_nlill0Oll_w_lg_nli1l11Ol46333w(0) OR NOT(nl0iOil0O); + wire_nli0i1OO_dataout <= wire_nli0Oi1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0i1OOi_dataout <= wire_nlill0Oll_w_lg_nli1iOl1O46332w(0) OR NOT(nl0iOil0O); + wire_nli0i1OOl_dataout <= wire_nlill0Oll_w_lg_nli1l110O46331w(0) OR NOT(nl0iOil0O); + wire_nli0i1OOO_dataout <= (NOT k_conf(307)) OR NOT(nl0iOil0l); + wire_nli0i1OOO_w_lg_dataout47269w(0) <= wire_nli0i1OOO_dataout AND wire_nli0i1O0i_dataout; + wire_nli0ii00i_dataout <= wire_nlill0Oll_w_lg_nl0l0OiiO46244w(0) OR NOT(niOiiOili); + wire_nli0ii00i_w_lg_dataout46789w(0) <= wire_nli0ii00i_dataout AND wire_nli0iiOii_w_lg_dataout46788w(0); + wire_nli0ii00l_dataout <= wire_nlill0Oll_w_lg_nl0l0Oili46243w(0) OR NOT(niOiiOili); + wire_nli0ii00l_w_lg_dataout46762w(0) <= wire_nli0ii00l_dataout AND wire_nli0iiOil_w_lg_dataout46761w(0); + wire_nli0ii00O_dataout <= wire_nl0l0l0OO_w_lg_dataout46242w(0) OR NOT(niOiiOiiO); + wire_nli0ii01i_dataout <= wire_nlill0Oll_w_lg_nl0l0Oi0O46247w(0) OR NOT(niOiiOili); + wire_nli0ii01i_w_lg_dataout46870w(0) <= wire_nli0ii01i_dataout AND wire_nli0iiO0i_w_lg_dataout46869w(0); + wire_nli0ii01l_dataout <= wire_nlill0Oll_w_lg_nl0l0Oiii46246w(0) OR NOT(niOiiOili); + wire_nli0ii01l_w_lg_dataout46843w(0) <= wire_nli0ii01l_dataout AND wire_nli0iiO0l_w_lg_dataout46842w(0); + wire_nli0ii01O_dataout <= wire_nlill0Oll_w_lg_nl0l0Oiil46245w(0) OR NOT(niOiiOili); + wire_nli0ii01O_w_lg_dataout46816w(0) <= wire_nli0ii01O_dataout AND wire_nli0iiO0O_w_lg_dataout46815w(0); + wire_nli0ii0i_dataout <= wire_nli0Ol0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ii0ii_dataout <= wire_nl0l0li1l_w_lg_dataout46241w(0) OR NOT(niOiiOiiO); + wire_nli0ii0il_dataout <= wire_nl0l0li0i_w_lg_dataout46240w(0) OR NOT(niOiiOiiO); + wire_nli0ii0iO_dataout <= wire_nl0l0li0O_w_lg_dataout46239w(0) OR NOT(niOiiOiiO); + wire_nli0ii0l_dataout <= wire_nli0Ol0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ii0li_dataout <= wire_nl0l0liil_w_lg_dataout46238w(0) OR NOT(niOiiOiiO); + wire_nli0ii0ll_dataout <= wire_nlill0Oll_w_lg_nl0l0liOi46237w(0) OR NOT(niOiiOiiO); + wire_nli0ii0lO_dataout <= wire_nlill0Oll_w_lg_nl0l0liOl46236w(0) OR NOT(niOiiOiiO); + wire_nli0ii0O_dataout <= wire_nli0Olii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ii0Oi_dataout <= wire_nlill0Oll_w_lg_nl0l0liOO46235w(0) OR NOT(niOiiOiiO); + wire_nli0ii0Ol_dataout <= wire_nlill0Oll_w_lg_nl0l0ll1i46234w(0) OR NOT(niOiiOiiO); + wire_nli0ii0OO_dataout <= wire_nlill0Oll_w_lg_nl0l0ll1l46233w(0) OR NOT(niOiiOiiO); + wire_nli0ii10i_dataout <= wire_nlill0Oll_w_lg_nl0l0O0iO46259w(0) WHEN niOiiOili = '1' ELSE wire_nli0iii0O_dataout; + wire_nli0ii10i_w_lg_dataout47228w(0) <= wire_nli0ii10i_dataout AND wire_nli0iilii_w_lg_dataout47227w(0); + wire_nli0ii10l_dataout <= wire_nlill0Oll_w_lg_nl0l0O0li46258w(0) OR NOT(niOiiOili); + wire_nli0ii10l_w_lg_dataout47198w(0) <= wire_nli0ii10l_dataout AND wire_nli0iilil_w_lg_dataout47197w(0); + wire_nli0ii10O_dataout <= wire_nlill0Oll_w_lg_nl0l0O0ll46257w(0) OR NOT(niOiiOili); + wire_nli0ii10O_w_lg_dataout47166w(0) <= wire_nli0ii10O_dataout AND wire_nli0iiliO_w_lg_dataout47165w(0); + wire_nli0ii11i_dataout <= wire_nlill0Oll_w_lg_nl0l0O00O46262w(0) WHEN niOiiOili = '1' ELSE wire_nli0iii1O_dataout; + wire_nli0ii11i_w_lg_dataout47321w(0) <= wire_nli0ii11i_dataout AND wire_nli0iil0i_w_lg_dataout47320w(0); + wire_nli0ii11l_dataout <= wire_nlill0Oll_w_lg_nl0l0O0ii46261w(0) WHEN niOiiOili = '1' ELSE wire_nli0iii0i_dataout; + wire_nli0ii11l_w_lg_dataout47292w(0) <= wire_nli0ii11l_dataout AND wire_nli0iil0l_w_lg_dataout47291w(0); + wire_nli0ii11O_dataout <= wire_nlill0Oll_w_lg_nl0l0O0il46260w(0) WHEN niOiiOili = '1' ELSE wire_nli0iii0l_dataout; + wire_nli0ii11O_w_lg_dataout47261w(0) <= wire_nli0ii11O_dataout AND wire_nli0iil0O_w_lg_dataout47260w(0); + wire_nli0ii1i_dataout <= wire_nli0Ol1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ii1ii_dataout <= wire_nlill0Oll_w_lg_nl0l0O0lO46256w(0) OR NOT(niOiiOili); + wire_nli0ii1ii_w_lg_dataout47136w(0) <= wire_nli0ii1ii_dataout AND wire_nli0iilli_w_lg_dataout47135w(0); + wire_nli0ii1il_dataout <= wire_nlill0Oll_w_lg_nl0l0O0Oi46255w(0) OR NOT(niOiiOili); + wire_nli0ii1il_w_lg_dataout47107w(0) <= wire_nli0ii1il_dataout AND wire_nli0iilll_w_lg_dataout47106w(0); + wire_nli0ii1iO_dataout <= wire_nlill0Oll_w_lg_nl0l0O0Ol46254w(0) OR NOT(niOiiOili); + wire_nli0ii1iO_w_lg_dataout47075w(0) <= wire_nli0ii1iO_dataout AND wire_nli0iillO_w_lg_dataout47074w(0); + wire_nli0ii1l_dataout <= wire_nli0Ol1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ii1li_dataout <= wire_nlill0Oll_w_lg_nl0l0O0OO46253w(0) OR NOT(niOiiOili); + wire_nli0ii1li_w_lg_dataout47042w(0) <= wire_nli0ii1li_dataout AND wire_nli0iilOi_w_lg_dataout47041w(0); + wire_nli0ii1ll_dataout <= wire_nlill0Oll_w_lg_nl0l0Oi1i46252w(0) OR NOT(niOiiOili); + wire_nli0ii1ll_w_lg_dataout47014w(0) <= wire_nli0ii1ll_dataout AND wire_nli0iilOl_w_lg_dataout47013w(0); + wire_nli0ii1lO_dataout <= wire_nlill0Oll_w_lg_nl0l0Oi1l46251w(0) OR NOT(niOiiOili); + wire_nli0ii1lO_w_lg_dataout46986w(0) <= wire_nli0ii1lO_dataout AND wire_nli0iilOO_w_lg_dataout46985w(0); + wire_nli0ii1O_dataout <= wire_nli0Ol0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ii1Oi_dataout <= wire_nlill0Oll_w_lg_nl0l0Oi1O46250w(0) OR NOT(niOiiOili); + wire_nli0ii1Oi_w_lg_dataout46956w(0) <= wire_nli0ii1Oi_dataout AND wire_nli0iiO1i_w_lg_dataout46955w(0); + wire_nli0ii1Ol_dataout <= wire_nlill0Oll_w_lg_nl0l0Oi0i46249w(0) OR NOT(niOiiOili); + wire_nli0ii1Ol_w_lg_dataout46927w(0) <= wire_nli0ii1Ol_dataout AND wire_nli0iiO1l_w_lg_dataout46926w(0); + wire_nli0ii1OO_dataout <= wire_nlill0Oll_w_lg_nl0l0Oi0l46248w(0) OR NOT(niOiiOili); + wire_nli0ii1OO_w_lg_dataout46897w(0) <= wire_nli0ii1OO_dataout AND wire_nli0iiO1O_w_lg_dataout46896w(0); + wire_nli0iii0i_dataout <= wire_nlill0Oll_w_lg_nl0l0ll0O46229w(0) OR NOT(niOiiOiiO); + wire_nli0iii0l_dataout <= wire_nlill0Oll_w_lg_nl0l0llii46228w(0) OR NOT(niOiiOiiO); + wire_nli0iii0O_dataout <= wire_nlill0Oll_w_lg_nl0l0llil46227w(0) OR NOT(niOiiOiiO); + wire_nli0iii1i_dataout <= wire_nlill0Oll_w_lg_nl0l0ll1O46232w(0) OR NOT(niOiiOiiO); + wire_nli0iii1l_dataout <= wire_nlill0Oll_w_lg_nl0l0ll0i46231w(0) OR NOT(niOiiOiiO); + wire_nli0iii1O_dataout <= wire_nlill0Oll_w_lg_nl0l0ll0l46230w(0) OR NOT(niOiiOiiO); + wire_nli0iiii_dataout <= wire_nli0Olil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iiiiO_dataout <= wire_nlill0Oll_w_lg_nl0l0lliO46224w(0) OR NOT(nl0iOiOli); + wire_nli0iiiiO_w_lg_dataout47639w(0) <= wire_nli0iiiiO_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47638w(0); + wire_nli0iiil_dataout <= wire_nli0OliO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iiili_dataout <= wire_nlill0Oll_w_lg_nl0l0llli46223w(0) OR NOT(nl0iOiOli); + wire_nli0iiili_w_lg_dataout47604w(0) <= wire_nli0iiili_dataout AND wire_nli0il1ii_w_lg_dataout47603w(0); + wire_nli0iiill_dataout <= wire_nlill0Oll_w_lg_nl0l0llll46222w(0) OR NOT(nl0iOiOli); + wire_nli0iiill_w_lg_dataout47570w(0) <= wire_nli0iiill_dataout AND wire_nli0il1il_w_lg_dataout47569w(0); + wire_nli0iiilO_dataout <= wire_nlill0Oll_w_lg_nl0l0lllO46221w(0) OR NOT(nl0iOiOli); + wire_nli0iiilO_w_lg_dataout47540w(0) <= wire_nli0iiilO_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47539w(0); + wire_nli0iiiO_dataout <= wire_nli0Olli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iiiOi_dataout <= wire_nlill0Oll_w_lg_nl0l0llOi46220w(0) OR NOT(nl0iOiOli); + wire_nli0iiiOi_w_lg_dataout47508w(0) <= wire_nli0iiiOi_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47507w(0); + wire_nli0iiiOl_dataout <= wire_nlill0Oll_w_lg_nl0l0llOl46219w(0) OR NOT(nl0iOiOli); + wire_nli0iiiOl_w_lg_dataout47474w(0) <= wire_nli0iiiOl_dataout AND wire_nli0il1ll_w_lg_dataout47473w(0); + wire_nli0iiiOO_dataout <= wire_nlill0Oll_w_lg_nl0l0llOO46218w(0) OR NOT(nl0iOiOli); + wire_nli0iiiOO_w_lg_dataout47443w(0) <= wire_nli0iiiOO_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w47442w(0); + wire_nli0iil0i_dataout <= wire_nlill0Oll_w_lg_nl0l0lO0i46214w(0) OR NOT(nl0iOiOli); + wire_nli0iil0i_w_lg_dataout47320w(0) <= wire_nli0iil0i_dataout AND wire_nli0iiOiO_w_lg_dataout47319w(0); + wire_nli0iil0l_dataout <= wire_nlill0Oll_w_lg_nl0l0lO0l46213w(0) OR NOT(nl0iOiOli); + wire_nli0iil0l_w_lg_dataout47291w(0) <= wire_nli0iil0l_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47290w(0); + wire_nli0iil0O_dataout <= wire_nlill0Oll_w_lg_nl0l0lO0O46212w(0) OR NOT(nl0iOiOli); + wire_nli0iil0O_w_lg_dataout47260w(0) <= wire_nli0iil0O_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47259w(0); + wire_nli0iil1i_dataout <= wire_nlill0Oll_w_lg_nl0l0lO1i46217w(0) OR NOT(nl0iOiOli); + wire_nli0iil1i_w_lg_dataout47412w(0) <= wire_nli0iil1i_dataout AND wire_nli0il1Oi_w_lg_dataout47411w(0); + wire_nli0iil1l_dataout <= wire_nlill0Oll_w_lg_nl0l0lO1l46216w(0) OR NOT(nl0iOiOli); + wire_nli0iil1l_w_lg_dataout47382w(0) <= wire_nli0iil1l_dataout AND wire_nli0il1Ol_w_lg_dataout47381w(0); + wire_nli0iil1O_dataout <= wire_nlill0Oll_w_lg_nl0l0lO1O46215w(0) OR NOT(nl0iOiOli); + wire_nli0iil1O_w_lg_dataout47351w(0) <= wire_nli0iil1O_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOiO47246w47350w(0); + wire_nli0iili_dataout <= wire_nli0Olll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iilii_dataout <= wire_nlill0Oll_w_lg_nl0l0lOii46211w(0) OR NOT(nl0iOiOli); + wire_nli0iilii_w_lg_dataout47227w(0) <= wire_nli0iilii_dataout AND wire_nli0ililO_w_lg_dataout47226w(0); + wire_nli0iilil_dataout <= wire_nlill0Oll_w_lg_nl0l0lOil46210w(0) OR NOT(nl0iOiOli); + wire_nli0iilil_w_lg_dataout47197w(0) <= wire_nli0iilil_dataout AND wire_nli0iiOli_w_lg_dataout47196w(0); + wire_nli0iiliO_dataout <= wire_nlill0Oll_w_lg_nl0l0lOiO46209w(0) OR NOT(nl0iOiOli); + wire_nli0iiliO_w_lg_dataout47165w(0) <= wire_nli0iiliO_dataout AND wire_nli0iiOll_w_lg_dataout47164w(0); + wire_nli0iill_dataout <= wire_nli0OllO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iilli_dataout <= wire_nlill0Oll_w_lg_nl0l0lOli46208w(0) OR NOT(nl0iOiOli); + wire_nli0iilli_w_lg_dataout47135w(0) <= wire_nli0iilli_dataout AND wire_nli0iiOlO_w_lg_dataout47134w(0); + wire_nli0iilll_dataout <= wire_nlill0Oll_w_lg_nl0l0lOll46207w(0) OR NOT(nl0iOiOli); + wire_nli0iilll_w_lg_dataout47106w(0) <= wire_nli0iilll_dataout AND wire_nli0iiOOi_w_lg_dataout47105w(0); + wire_nli0iillO_dataout <= wire_nlill0Oll_w_lg_nl0l0lOlO46206w(0) OR NOT(nl0iOiOli); + wire_nli0iillO_w_lg_dataout47074w(0) <= wire_nli0iillO_dataout AND wire_nli0iiOOl_w_lg_dataout47073w(0); + wire_nli0iilO_dataout <= wire_nli0OlOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iilOi_dataout <= wire_nlill0Oll_w_lg_nl0l0lOOi46205w(0) OR NOT(nl0iOiOli); + wire_nli0iilOi_w_lg_dataout47041w(0) <= wire_nli0iilOi_dataout AND wire_nli0iiOOO_w_lg_dataout47040w(0); + wire_nli0iilOl_dataout <= wire_nlill0Oll_w_lg_nl0l0lOOl46204w(0) OR NOT(nl0iOiOli); + wire_nli0iilOl_w_lg_dataout47013w(0) <= wire_nli0iilOl_dataout AND wire_nli0il11i_w_lg_dataout47012w(0); + wire_nli0iilOO_dataout <= wire_nlill0Oll_w_lg_nl0l0lOOO46203w(0) OR NOT(nl0iOiOli); + wire_nli0iilOO_w_lg_dataout46985w(0) <= wire_nli0iilOO_dataout AND wire_nli0il11l_w_lg_dataout46984w(0); + wire_nli0iiO0i_dataout <= wire_nlill0Oll_w_lg_nl0l0O10i46199w(0) OR NOT(nl0iOiOli); + wire_nli0iiO0i_w_lg_dataout46869w(0) <= wire_nli0iiO0i_dataout AND wire_nli0illiO_w_lg_dataout46868w(0); + wire_nli0iiO0l_dataout <= wire_nlill0Oll_w_lg_nl0l0O10l46198w(0) OR NOT(nl0iOiOli); + wire_nli0iiO0l_w_lg_dataout46842w(0) <= wire_nli0iiO0l_dataout AND wire_nli0illli_w_lg_dataout46841w(0); + wire_nli0iiO0O_dataout <= wire_nlill0Oll_w_lg_nl0l0O10O46197w(0) OR NOT(nl0iOiOli); + wire_nli0iiO0O_w_lg_dataout46815w(0) <= wire_nli0iiO0O_dataout AND wire_nli0illll_w_lg_dataout46814w(0); + wire_nli0iiO1i_dataout <= wire_nlill0Oll_w_lg_nl0l0O11i46202w(0) OR NOT(nl0iOiOli); + wire_nli0iiO1i_w_lg_dataout46955w(0) <= wire_nli0iiO1i_dataout AND wire_nli0il11O_w_lg_dataout46954w(0); + wire_nli0iiO1l_dataout <= wire_nlill0Oll_w_lg_nl0l0O11l46201w(0) OR NOT(nl0iOiOli); + wire_nli0iiO1l_w_lg_dataout46926w(0) <= wire_nli0iiO1l_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiOii46913w46925w(0); + wire_nli0iiO1O_dataout <= wire_nlill0Oll_w_lg_nl0l0O11O46200w(0) OR NOT(nl0iOiOli); + wire_nli0iiO1O_w_lg_dataout46896w(0) <= wire_nli0iiO1O_dataout AND wire_nli0illil_w_lg_dataout46895w(0); + wire_nli0iiOi_dataout <= wire_nli0OlOl_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iiOii_dataout <= wire_nlill0Oll_w_lg_nl0l0O1ii46196w(0) OR NOT(nl0iOiOli); + wire_nli0iiOii_w_lg_dataout46788w(0) <= wire_nli0iiOii_dataout AND wire_nli0illlO_w_lg_dataout46787w(0); + wire_nli0iiOil_dataout <= wire_nlill0Oll_w_lg_nl0l0O1il46195w(0) OR NOT(nl0iOiOli); + wire_nli0iiOil_w_lg_dataout46761w(0) <= wire_nli0iiOil_dataout AND wire_nli0illOi_w_lg_dataout46760w(0); + wire_nli0iiOiO_dataout <= k_conf(230) OR NOT(nl0iOiOiO); + wire_nli0iiOiO_w_lg_dataout47319w(0) <= wire_nli0iiOiO_dataout AND wire_nli0iliiO_w_lg_dataout47318w(0); + wire_nli0iiOl_dataout <= wire_nli0OlOO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iiOli_dataout <= wire_nlill0Oll_w_lg_nl0l0Oill46193w(0) OR NOT(nl0iOiOiO); + wire_nli0iiOli_w_lg_dataout47196w(0) <= wire_nli0iiOli_dataout AND wire_nli0il1OO_w_lg_dataout47195w(0); + wire_nli0iiOll_dataout <= (NOT k_conf(219)) OR NOT(nl0iOiOiO); + wire_nli0iiOll_w_lg_dataout47164w(0) <= wire_nli0iiOll_dataout AND wire_nli0il01i_w_lg_dataout47163w(0); + wire_nli0iiOlO_dataout <= (NOT k_conf(220)) OR NOT(nl0iOiOiO); + wire_nli0iiOlO_w_lg_dataout47134w(0) <= wire_nli0iiOlO_dataout AND wire_nli0iliOO_w_lg_dataout47133w(0); + wire_nli0iiOO_dataout <= wire_nli0OO1i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iiOOi_dataout <= (NOT k_conf(221)) OR NOT(nl0iOiOiO); + wire_nli0iiOOi_w_lg_dataout47105w(0) <= wire_nli0iiOOi_dataout AND wire_nli0il01l_w_lg_dataout47104w(0); + wire_nli0iiOOl_dataout <= wire_nlill0Oll_w_lg_nl0l0OilO46189w(0) OR NOT(nl0iOiOiO); + wire_nli0iiOOl_w_lg_dataout47073w(0) <= wire_nli0iiOOl_dataout AND wire_nli0il01O_w_lg_dataout47072w(0); + wire_nli0iiOOO_dataout <= wire_nlill0Oll_w_lg_nl0l0OiOi46188w(0) OR NOT(nl0iOiOiO); + wire_nli0iiOOO_w_lg_dataout47040w(0) <= wire_nli0iiOOO_dataout AND wire_nli0ill1O_w_lg_dataout47039w(0); + wire_nli0il00i_dataout <= wire_nli0ili0l_dataout OR niOiiOill; + wire_nli0il00i_w_lg_dataout47011w(0) <= wire_nli0il00i_dataout AND wire_nli0ill0i_w_lg_dataout47010w(0); + wire_nli0il00l_dataout <= wire_nl0lil1ll_w_lg_dataout46184w(0) OR NOT(nl0iOiO0l); + wire_nli0il00O_dataout <= wire_nl0lil1lO_w_lg_dataout46183w(0) OR NOT(nl0iOiO0l); + wire_nli0il01i_dataout <= wire_nli0ili1l_dataout OR niOiiOill; + wire_nli0il01i_w_lg_dataout47163w(0) <= wire_nli0il01i_dataout AND wire_nli0iliOl_w_lg_dataout47162w(0); + wire_nli0il01l_dataout <= wire_nli0ili1O_dataout OR niOiiOill; + wire_nli0il01l_w_lg_dataout47104w(0) <= wire_nli0il01l_dataout AND wire_nli0ill1i_w_lg_dataout47103w(0); + wire_nli0il01O_dataout <= wire_nli0ili0i_dataout OR niOiiOill; + wire_nli0il01O_w_lg_dataout47072w(0) <= wire_nli0il01O_dataout AND wire_nli0ill1l_w_lg_dataout47071w(0); + wire_nli0il0i_dataout <= wire_nli0OO0l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0il0ii_dataout <= wire_nl0lil1Oi_w_lg_dataout46182w(0) OR NOT(nl0iOiO0l); + wire_nli0il0il_dataout <= wire_nl0lil1Ol_w_lg_dataout46181w(0) OR NOT(nl0iOiO0l); + wire_nli0il0iO_dataout <= wire_nl0lil1OO_w_lg_dataout46180w(0) OR NOT(nl0iOiO0l); + wire_nli0il0l_dataout <= wire_nli0OO0O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0il0li_dataout <= wire_nl0lil01i_w_lg_dataout46179w(0) OR NOT(nl0iOiO0l); + wire_nli0il0ll_dataout <= wire_nl0lil01l_w_lg_dataout46178w(0) OR NOT(nl0iOiO0l); + wire_nli0il0lO_dataout <= wire_nl0lil01O_w_lg_dataout46177w(0) OR NOT(nl0iOiO0l); + wire_nli0il0O_dataout <= wire_nli0OOii_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0il0Oi_dataout <= (NOT k_conf(225)) OR NOT(nl0iOiO0l); + wire_nli0il0Ol_dataout <= wire_w_lg_w_k_conf_range46173w46174w(0) OR NOT(nl0iOiO0l); + wire_nli0il0OO_dataout <= (NOT k_conf(227)) OR NOT(nl0iOiO0l); + wire_nli0il10i_dataout <= wire_nl0lil1ll_w_lg_dataout46184w(0) WHEN niOiiOill = '1' ELSE wire_nli0il00l_dataout; + wire_nli0il10i_w_lg_dataout47706w(0) <= wire_nli0il10i_dataout AND wire_nli0iliii_w_lg_dataout47705w(0); + wire_nli0il10l_dataout <= wire_nl0lil1lO_w_lg_dataout46183w(0) WHEN niOiiOill = '1' ELSE wire_nli0il00O_dataout; + wire_nli0il10l_w_lg_dataout47671w(0) <= wire_nli0il10l_dataout AND wire_nli0ilO0i_w_lg_dataout47670w(0); + wire_nli0il10O_dataout <= wire_nl0lil1Oi_w_lg_dataout46182w(0) WHEN niOiiOill = '1' ELSE wire_nli0il0ii_dataout; + wire_nli0il10O_w_lg_dataout47637w(0) <= wire_nli0il10O_dataout AND wire_nli0ilO0l_w_lg_dataout47636w(0); + wire_nli0il11i_dataout <= wire_nlill0Oll_w_lg_nl0l0OiOl46187w(0) OR NOT(nl0iOiOiO); + wire_nli0il11i_w_lg_dataout47012w(0) <= wire_nli0il11i_dataout AND wire_nli0il00i_w_lg_dataout47011w(0); + wire_nli0il11l_dataout <= wire_w_lg_w_k_conf_range1869w46186w(0) OR NOT(nl0iOiOiO); + wire_nli0il11l_w_lg_dataout46984w(0) <= wire_nli0il11l_dataout AND wire_nli0ill0l_w_lg_dataout46983w(0); + wire_nli0il11O_dataout <= (NOT k_conf(223)) OR NOT(nl0iOiOiO); + wire_nli0il11O_w_lg_dataout46954w(0) <= wire_nli0il11O_dataout AND wire_nli0ill0O_w_lg_dataout46953w(0); + wire_nli0il1i_dataout <= wire_nli0OO1l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0il1ii_dataout <= wire_nl0lil1Ol_w_lg_dataout46181w(0) WHEN niOiiOill = '1' ELSE wire_nli0il0il_dataout; + wire_nli0il1ii_w_lg_dataout47603w(0) <= wire_nli0il1ii_dataout AND wire_nli0illOO_w_lg_dataout47602w(0); + wire_nli0il1il_dataout <= wire_nl0lil1OO_w_lg_dataout46180w(0) WHEN niOiiOill = '1' ELSE wire_nli0il0iO_dataout; + wire_nli0il1il_w_lg_dataout47569w(0) <= wire_nli0il1il_dataout AND wire_nli0ilO1i_w_lg_dataout47568w(0); + wire_nli0il1iO_dataout <= wire_nl0lil01i_w_lg_dataout46179w(0) WHEN niOiiOill = '1' ELSE wire_nli0il0li_dataout; + wire_nli0il1iO_w_lg_dataout47538w(0) <= wire_nli0il1iO_dataout AND wire_nli0ilO1l_w_lg_dataout47537w(0); + wire_nli0il1l_dataout <= wire_nli0OO1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0il1li_dataout <= wire_nl0lil01l_w_lg_dataout46178w(0) WHEN niOiiOill = '1' ELSE wire_nli0il0ll_dataout; + wire_nli0il1li_w_lg_dataout47506w(0) <= wire_nli0il1li_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOiO1O47492w47505w(0); + wire_nli0il1ll_dataout <= wire_nl0lil01O_w_lg_dataout46177w(0) WHEN niOiiOill = '1' ELSE wire_nli0il0lO_dataout; + wire_nli0il1ll_w_lg_dataout47473w(0) <= wire_nli0il1ll_dataout AND wire_nli0ilOli_w_lg_dataout47472w(0); + wire_nli0il1lO_dataout <= (NOT k_conf(225)) WHEN niOiiOill = '1' ELSE wire_nli0il0Oi_dataout; + wire_nli0il1lO_w_lg_dataout47441w(0) <= wire_nli0il1lO_dataout AND wire_nli0ilOll_w_lg_dataout47440w(0); + wire_nli0il1O_dataout <= wire_nli0OO0i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0il1Oi_dataout <= wire_w_lg_w_k_conf_range46173w46174w(0) WHEN niOiiOill = '1' ELSE wire_nli0il0Ol_dataout; + wire_nli0il1Oi_w_lg_dataout47411w(0) <= wire_nli0il1Oi_dataout AND wire_nli0ilOlO_w_lg_dataout47410w(0); + wire_nli0il1Ol_dataout <= (NOT k_conf(227)) WHEN niOiiOill = '1' ELSE wire_nli0il0OO_dataout; + wire_nli0il1Ol_w_lg_dataout47381w(0) <= wire_nli0il1Ol_dataout AND wire_nli0ilOOi_w_lg_dataout47380w(0); + wire_nli0il1OO_dataout <= wire_nli0ili1i_dataout OR niOiiOill; + wire_nli0il1OO_w_lg_dataout47195w(0) <= wire_nli0il1OO_dataout AND wire_nli0iliOi_w_lg_dataout47194w(0); + wire_nli0ili0i_dataout <= wire_nlill0Oll_w_lg_nl0OiOl0i46167w(0) OR NOT(nl0iOiO0l); + wire_nli0ili0l_dataout <= wire_nlill0Oll_w_lg_nl0OiO1Oi46166w(0) OR NOT(nl0iOiO0l); + wire_nli0ili1i_dataout <= wire_nlill0Oll_w_lg_nl0OiOlii46170w(0) OR NOT(nl0iOiO0l); + wire_nli0ili1l_dataout <= wire_nlill0Oll_w_lg_nl0OiOl0O46169w(0) OR NOT(nl0iOiO0l); + wire_nli0ili1O_dataout <= wire_nlill0Oll_w_lg_nl0OiOl0l46168w(0) OR NOT(nl0iOiO0l); + wire_nli0ilii_dataout <= wire_nli0OOil_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iliii_dataout <= wire_w_lg_niOiiOiOi46161w(0) OR NOT(niOiiOilO); + wire_nli0iliii_w_lg_dataout47705w(0) <= wire_nli0iliii_dataout AND wire_nli0ilO1O_w_lg_dataout47704w(0); + wire_nli0iliil_dataout <= wire_w_lg_niOiiOiOl46160w(0) OR NOT(niOiiOilO); + wire_nli0iliil_w_lg_dataout47349w(0) <= wire_nli0iliil_dataout AND wire_nli0ilOOl_w_lg_dataout47348w(0); + wire_nli0iliiO_dataout <= wire_w_lg_niOiiOiOO46159w(0) OR NOT(niOiiOilO); + wire_nli0iliiO_w_lg_dataout47318w(0) <= wire_nli0iliiO_dataout AND wire_nli0ilOOO_w_lg_dataout47317w(0); + wire_nli0ilil_dataout <= wire_nli0OOiO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ilili_dataout <= wire_w_lg_niOiiOl1i46158w(0) OR NOT(niOiiOilO); + wire_nli0ilili_w_lg_dataout47288w(0) <= wire_nli0ilili_dataout AND wire_nli0iO11i_w_lg_dataout47287w(0); + wire_nli0ilill_dataout <= wire_w_lg_niOiiOl1l46157w(0) OR NOT(niOiiOilO); + wire_nli0ilill_w_lg_dataout47257w(0) <= wire_nli0ilill_dataout AND wire_nli0iO11l_w_lg_dataout47256w(0); + wire_nli0ililO_dataout <= wire_w_lg_niOiiOl1O46156w(0) OR NOT(niOiiOilO); + wire_nli0ililO_w_lg_dataout47226w(0) <= wire_nli0ililO_dataout AND wire_nli0iO11O_w_lg_dataout47225w(0); + wire_nli0iliO_dataout <= wire_nli0OOli_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iliOi_dataout <= wire_w_lg_niOiiOl0i46155w(0) OR NOT(niOiiOilO); + wire_nli0iliOi_w_lg_dataout47194w(0) <= wire_nli0iliOi_dataout AND wire_nli0iO10i_w_lg_dataout47193w(0); + wire_nli0iliOl_dataout <= wire_w_lg_niOiiOl0l46154w(0) OR NOT(niOiiOilO); + wire_nli0iliOl_w_lg_dataout47162w(0) <= wire_nli0iliOl_dataout AND wire_nli0iO10l_w_lg_dataout47161w(0); + wire_nli0iliOO_dataout <= wire_w_lg_niOiiOl0O46153w(0) OR NOT(niOiiOilO); + wire_nli0iliOO_w_lg_dataout47133w(0) <= wire_nli0iliOO_dataout AND wire_nli0iO10O_w_lg_dataout47132w(0); + wire_nli0ill0i_dataout <= wire_w_lg_niOiiOlli46149w(0) OR NOT(niOiiOilO); + wire_nli0ill0i_w_lg_dataout47010w(0) <= wire_nli0ill0i_dataout AND wire_nli0iO1li_w_lg_dataout47009w(0); + wire_nli0ill0l_dataout <= wire_w_lg_niOiiOlll46148w(0) OR NOT(niOiiOilO); + wire_nli0ill0l_w_lg_dataout46983w(0) <= wire_nli0ill0l_dataout AND wire_nli0iO1ll_w_lg_dataout46982w(0); + wire_nli0ill0O_dataout <= wire_w_lg_niOiiOllO46147w(0) OR NOT(niOiiOilO); + wire_nli0ill0O_w_lg_dataout46953w(0) <= wire_nli0ill0O_dataout AND wire_nli0iO1lO_w_lg_dataout46952w(0); + wire_nli0ill1i_dataout <= wire_w_lg_niOiiOlii46152w(0) OR NOT(niOiiOilO); + wire_nli0ill1i_w_lg_dataout47103w(0) <= wire_nli0ill1i_dataout AND wire_nli0iO1ii_w_lg_dataout47102w(0); + wire_nli0ill1l_dataout <= wire_w_lg_niOiiOlil46151w(0) OR NOT(niOiiOilO); + wire_nli0ill1l_w_lg_dataout47071w(0) <= wire_nli0ill1l_dataout AND wire_nli0iO1il_w_lg_dataout47070w(0); + wire_nli0ill1O_dataout <= wire_w_lg_niOiiOliO46150w(0) OR NOT(niOiiOilO); + wire_nli0ill1O_w_lg_dataout47039w(0) <= wire_nli0ill1O_dataout AND wire_nli0iO1iO_w_lg_dataout47038w(0); + wire_nli0illi_dataout <= wire_nli0OOll_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0illii_dataout <= wire_w_lg_niOiiOlOi46146w(0) OR NOT(niOiiOilO); + wire_nli0illii_w_lg_dataout46924w(0) <= wire_nli0illii_dataout AND wire_nli0iO1Oi_w_lg_dataout46923w(0); + wire_nli0illil_dataout <= wire_w_lg_niOiiOlOl46145w(0) OR NOT(niOiiOilO); + wire_nli0illil_w_lg_dataout46895w(0) <= wire_nli0illil_dataout AND wire_nli0iO1Ol_w_lg_dataout46894w(0); + wire_nli0illiO_dataout <= wire_w_lg_niOiiOlOO46144w(0) OR NOT(niOiiOilO); + wire_nli0illiO_w_lg_dataout46868w(0) <= wire_nli0illiO_dataout AND wire_nli0iO1OO_w_lg_dataout46867w(0); + wire_nli0illl_dataout <= wire_nli0OOlO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0illli_dataout <= wire_w_lg_niOiiOO1i46143w(0) OR NOT(niOiiOilO); + wire_nli0illli_w_lg_dataout46841w(0) <= wire_nli0illli_dataout AND wire_nli0iO01i_w_lg_dataout46840w(0); + wire_nli0illll_dataout <= wire_w_lg_niOiiOO1l46142w(0) OR NOT(niOiiOilO); + wire_nli0illll_w_lg_dataout46814w(0) <= wire_nli0illll_dataout AND wire_nli0iO01l_w_lg_dataout46813w(0); + wire_nli0illlO_dataout <= wire_w_lg_niOiiOO1O46141w(0) OR NOT(niOiiOilO); + wire_nli0illlO_w_lg_dataout46787w(0) <= wire_nli0illlO_dataout AND wire_nli0iO01O_w_lg_dataout46786w(0); + wire_nli0illO_dataout <= wire_nli0OOOi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0illOi_dataout <= wire_w_lg_niOiiOO0i46140w(0) OR NOT(niOiiOilO); + wire_nli0illOi_w_lg_dataout46760w(0) <= wire_nli0illOi_dataout AND wire_nli0iO00i_w_lg_dataout46759w(0); + wire_nli0illOO_dataout <= k_conf(224) OR NOT(nl0iOiO1O); + wire_nli0illOO_w_lg_dataout47602w(0) <= wire_nli0illOO_dataout AND wire_nli0ilO0O_w_lg_dataout47601w(0); + wire_nli0ilO0i_dataout <= wire_nli0iO00O_dataout OR niOiiOO0l; + wire_nli0ilO0i_w_lg_dataout47670w(0) <= wire_nli0ilO0i_dataout AND wire_nli0iOliO_w_lg_dataout47669w(0); + wire_nli0ilO0l_dataout <= wire_nli0iO0ii_dataout OR niOiiOO0l; + wire_nli0ilO0l_w_lg_dataout47636w(0) <= wire_nli0ilO0l_dataout AND wire_nli0iOlli_w_lg_dataout47635w(0); + wire_nli0ilO0O_dataout <= wire_nli0iO0il_dataout OR niOiiOO0l; + wire_nli0ilO0O_w_lg_dataout47601w(0) <= wire_nli0ilO0O_dataout AND wire_nli0iOlll_w_lg_dataout47600w(0); + wire_nli0ilO1i_dataout <= wire_nl0l0l0Ol_w_lg_dataout46163w(0) OR NOT(nl0iOiO1O); + wire_nli0ilO1i_w_lg_dataout47568w(0) <= wire_nli0ilO1i_dataout AND wire_nli0ilOii_w_lg_dataout47567w(0); + wire_nli0ilO1l_dataout <= k_conf(224) OR NOT(nl0iOiO1O); + wire_nli0ilO1l_w_lg_dataout47537w(0) <= wire_nli0ilO1l_dataout AND wire_nli0ilOil_w_lg_dataout47536w(0); + wire_nli0ilO1O_dataout <= wire_w_lg_niOiiOiOi46161w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iO00l_dataout; + wire_nli0ilO1O_w_lg_dataout47704w(0) <= wire_nli0ilO1O_dataout AND wire_nli0iOlil_w_lg_dataout47703w(0); + wire_nli0ilOi_dataout <= wire_nlii111i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ilOii_dataout <= wire_nli0iO0iO_dataout OR niOiiOO0l; + wire_nli0ilOii_w_lg_dataout47567w(0) <= wire_nli0ilOii_dataout AND wire_nli0iOllO_w_lg_dataout47566w(0); + wire_nli0ilOil_dataout <= wire_nli0iO0li_dataout OR niOiiOO0l; + wire_nli0ilOil_w_lg_dataout47536w(0) <= wire_nli0ilOil_dataout AND wire_nli0iOlOi_w_lg_dataout47535w(0); + wire_nli0ilOiO_dataout <= wire_nli0iO0ll_dataout OR niOiiOO0l; + wire_nli0ilOiO_w_lg_dataout47504w(0) <= wire_nli0ilOiO_dataout AND wire_nli0iOlOl_w_lg_dataout47503w(0); + wire_nli0ilOl_dataout <= wire_nlii111l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ilOli_dataout <= wire_nli0iO0lO_dataout OR niOiiOO0l; + wire_nli0ilOli_w_lg_dataout47472w(0) <= wire_nli0ilOli_dataout AND wire_nli0iOlOO_w_lg_dataout47471w(0); + wire_nli0ilOll_dataout <= wire_nli0iO0Oi_dataout OR niOiiOO0l; + wire_nli0ilOll_w_lg_dataout47440w(0) <= wire_nli0ilOll_dataout AND wire_nli0iOO1i_w_lg_dataout47439w(0); + wire_nli0ilOlO_dataout <= wire_nli0iO0Ol_dataout OR niOiiOO0l; + wire_nli0ilOlO_w_lg_dataout47410w(0) <= wire_nli0ilOlO_dataout AND wire_nli0iOO1l_w_lg_dataout47409w(0); + wire_nli0ilOO_dataout <= wire_nlii111O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0ilOOi_dataout <= wire_nli0iO0OO_dataout OR niOiiOO0l; + wire_nli0ilOOi_w_lg_dataout47380w(0) <= wire_nli0ilOOi_dataout AND wire_nli0iOO1O_w_lg_dataout47379w(0); + wire_nli0ilOOl_dataout <= wire_w_lg_niOiiOiOl46160w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOi1i_dataout; + wire_nli0ilOOl_w_lg_dataout47348w(0) <= wire_nli0ilOOl_dataout AND wire_nli0iOO0i_w_lg_dataout47347w(0); + wire_nli0ilOOO_dataout <= wire_w_lg_niOiiOiOO46159w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOi1l_dataout; + wire_nli0ilOOO_w_lg_dataout47317w(0) <= wire_nli0ilOOO_dataout AND wire_nli0iOO0l_w_lg_dataout47316w(0); + wire_nli0iO00i_dataout <= wire_w_lg_niOiiOO0i46140w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOl0O_dataout; + wire_nli0iO00i_w_lg_dataout46759w(0) <= wire_nli0iO00i_dataout AND wire_nli0l11iO_w_lg_dataout46758w(0); + wire_nli0iO00l_dataout <= wire_nlill0Oll_w_lg_nl0OOi1ll46139w(0) OR NOT(nl0iOiO1l); + wire_nli0iO00O_dataout <= wire_nlill0Oll_w_lg_nl0OOi1lO46138w(0) OR NOT(nl0iOiO1l); + wire_nli0iO01i_dataout <= wire_w_lg_niOiiOO1i46143w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOl1O_dataout; + wire_nli0iO01i_w_lg_dataout46840w(0) <= wire_nli0iO01i_dataout AND wire_nli0l110O_w_lg_dataout46839w(0); + wire_nli0iO01l_dataout <= wire_w_lg_niOiiOO1l46142w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOl0i_dataout; + wire_nli0iO01l_w_lg_dataout46813w(0) <= wire_nli0iO01l_dataout AND wire_nli0l11ii_w_lg_dataout46812w(0); + wire_nli0iO01O_dataout <= wire_w_lg_niOiiOO1O46141w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOl0l_dataout; + wire_nli0iO01O_w_lg_dataout46786w(0) <= wire_nli0iO01O_dataout AND wire_nli0l11il_w_lg_dataout46785w(0); + wire_nli0iO0i_dataout <= wire_nlii110O_dataout WHEN nli1l0ii = '1' ELSE nli1li1i; + wire_nli0iO0ii_dataout <= wire_nlill0Oll_w_lg_nl0OOi1Oi46137w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0il_dataout <= wire_nlill0Oll_w_lg_nl0OOi1Ol46136w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0iO_dataout <= wire_nlill0Oll_w_lg_nl0OOi1OO46135w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0l_dataout <= wire_nlii11ii_dataout WHEN nli1l0ii = '1' ELSE nli1li1l; + wire_nli0iO0li_dataout <= wire_nlill0Oll_w_lg_nl0OOi01i46134w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0ll_dataout <= wire_nlill0Oll_w_lg_nl0OOi01l46133w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0lO_dataout <= wire_nlill0Oll_w_lg_nl0OOi01O46132w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0O_dataout <= wire_nlii11il_dataout WHEN nli1l0ii = '1' ELSE nli1li1O; + wire_nli0iO0Oi_dataout <= wire_nlill0Oll_w_lg_nl0OOi00i46131w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0Ol_dataout <= wire_nlill0Oll_w_lg_nl0OOi00l46130w(0) OR NOT(nl0iOiO1l); + wire_nli0iO0OO_dataout <= wire_nlill0Oll_w_lg_nl0OOi00O46129w(0) OR NOT(nl0iOiO1l); + wire_nli0iO10i_dataout <= wire_w_lg_niOiiOl0i46155w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOi0O_dataout; + wire_nli0iO10i_w_lg_dataout47193w(0) <= wire_nli0iO10i_dataout AND wire_nli0iOOiO_w_lg_dataout47192w(0); + wire_nli0iO10l_dataout <= wire_w_lg_niOiiOl0l46154w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOiii_dataout; + wire_nli0iO10l_w_lg_dataout47161w(0) <= wire_nli0iO10l_dataout AND wire_nli0iOOli_w_lg_dataout47160w(0); + wire_nli0iO10O_dataout <= wire_w_lg_niOiiOl0O46153w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOiil_dataout; + wire_nli0iO10O_w_lg_dataout47132w(0) <= wire_nli0iO10O_dataout AND wire_nli0iOOll_w_lg_dataout47131w(0); + wire_nli0iO11i_dataout <= wire_w_lg_niOiiOl1i46158w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOi1O_dataout; + wire_nli0iO11i_w_lg_dataout47287w(0) <= wire_nli0iO11i_dataout AND wire_nli0iOO0O_w_lg_dataout47286w(0); + wire_nli0iO11l_dataout <= wire_w_lg_niOiiOl1l46157w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOi0i_dataout; + wire_nli0iO11l_w_lg_dataout47256w(0) <= wire_nli0iO11l_dataout AND wire_nli0iOOii_w_lg_dataout47255w(0); + wire_nli0iO11O_dataout <= wire_w_lg_niOiiOl1O46156w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOi0l_dataout; + wire_nli0iO11O_w_lg_dataout47225w(0) <= wire_nli0iO11O_dataout AND wire_nli0iOOil_w_lg_dataout47224w(0); + wire_nli0iO1i_dataout <= wire_nlii110i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iO1ii_dataout <= wire_w_lg_niOiiOlii46152w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOiiO_dataout; + wire_nli0iO1ii_w_lg_dataout47102w(0) <= wire_nli0iO1ii_dataout AND wire_nli0iOOlO_w_lg_dataout47101w(0); + wire_nli0iO1il_dataout <= wire_w_lg_niOiiOlil46151w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOili_dataout; + wire_nli0iO1il_w_lg_dataout47070w(0) <= wire_nli0iO1il_dataout AND wire_nli0iOOOi_w_lg_dataout47069w(0); + wire_nli0iO1iO_dataout <= wire_w_lg_niOiiOliO46150w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOill_dataout; + wire_nli0iO1iO_w_lg_dataout47038w(0) <= wire_nli0iO1iO_dataout AND wire_nli0iOOOl_w_lg_dataout47037w(0); + wire_nli0iO1l_dataout <= wire_nli0l00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli0iO1li_dataout <= wire_w_lg_niOiiOlli46149w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOilO_dataout; + wire_nli0iO1li_w_lg_dataout47009w(0) <= wire_nli0iO1li_dataout AND wire_nli0iOOOO_w_lg_dataout47008w(0); + wire_nli0iO1ll_dataout <= wire_w_lg_niOiiOlll46148w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOiOi_dataout; + wire_nli0iO1ll_w_lg_dataout46982w(0) <= wire_nli0iO1ll_dataout AND wire_nli0l111i_w_lg_dataout46981w(0); + wire_nli0iO1lO_dataout <= wire_w_lg_niOiiOllO46147w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOiOl_dataout; + wire_nli0iO1lO_w_lg_dataout46952w(0) <= wire_nli0iO1lO_dataout AND wire_nli0l111l_w_lg_dataout46951w(0); + wire_nli0iO1O_dataout <= wire_nlii110l_dataout WHEN nli1l0ii = '1' ELSE nli1l0OO; + wire_nli0iO1Oi_dataout <= wire_w_lg_niOiiOlOi46146w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOiOO_dataout; + wire_nli0iO1Oi_w_lg_dataout46923w(0) <= wire_nli0iO1Oi_dataout AND wire_nli0l111O_w_lg_dataout46922w(0); + wire_nli0iO1Ol_dataout <= wire_w_lg_niOiiOlOl46145w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOl1i_dataout; + wire_nli0iO1Ol_w_lg_dataout46894w(0) <= wire_nli0iO1Ol_dataout AND wire_nli0l110i_w_lg_dataout46893w(0); + wire_nli0iO1OO_dataout <= wire_w_lg_niOiiOlOO46144w(0) WHEN niOiiOO0l = '1' ELSE wire_nli0iOl1l_dataout; + wire_nli0iO1OO_w_lg_dataout46867w(0) <= wire_nli0iO1OO_dataout AND wire_nli0l110l_w_lg_dataout46866w(0); + wire_nli0iOi0i_dataout <= wire_nlill0Oll_w_lg_nl0OOi0li46125w(0) OR NOT(nl0iOiO1l); + wire_nli0iOi0l_dataout <= wire_nlill0Oll_w_lg_nl0OOi0ll46124w(0) OR NOT(nl0iOiO1l); + wire_nli0iOi0O_dataout <= wire_nlill0Oll_w_lg_nl0OO1Oil46123w(0) OR NOT(nl0iOiO1l); + wire_nli0iOi1i_dataout <= wire_nlill0Oll_w_lg_nl0OOi0ii46128w(0) OR NOT(nl0iOiO1l); + wire_nli0iOi1l_dataout <= wire_nlill0Oll_w_lg_nl0OOi0il46127w(0) OR NOT(nl0iOiO1l); + wire_nli0iOi1O_dataout <= wire_nlill0Oll_w_lg_nl0OOi0iO46126w(0) OR NOT(nl0iOiO1l); + wire_nli0iOii_dataout <= wire_nlii11iO_dataout WHEN nli1l0ii = '1' ELSE nli1li0i; + wire_nli0iOiii_dataout <= wire_nlill0Oll_w_lg_nl0OO0Oii46122w(0) OR NOT(nl0iOiO1l); + wire_nli0iOiil_dataout <= wire_nlill0Oll_w_lg_nl0OO0Oil46121w(0) OR NOT(nl0iOiO1l); + wire_nli0iOiiO_dataout <= wire_nlill0Oll_w_lg_nl0OO0OiO46120w(0) OR NOT(nl0iOiO1l); + wire_nli0iOil_dataout <= wire_nlii11li_dataout WHEN nli1l0ii = '1' ELSE nli1li0l; + wire_nli0iOili_dataout <= wire_nlill0Oll_w_lg_nl0OO0Oli46119w(0) OR NOT(nl0iOiO1l); + wire_nli0iOill_dataout <= wire_nlill0Oll_w_lg_nl0OO0Oll46118w(0) OR NOT(nl0iOiO1l); + wire_nli0iOilO_dataout <= wire_nlill0Oll_w_lg_nl0OO0OlO46117w(0) OR NOT(nl0iOiO1l); + wire_nli0iOiO_dataout <= wire_nlii11ll_dataout WHEN nli1l0ii = '1' ELSE nli1li0O; + wire_nli0iOiOi_dataout <= wire_nlill0Oll_w_lg_nl0OO0OOi46116w(0) OR NOT(nl0iOiO1l); + wire_nli0iOiOl_dataout <= wire_nlill0Oll_w_lg_nl0OO0OOl46115w(0) OR NOT(nl0iOiO1l); + wire_nli0iOiOO_dataout <= wire_nlill0Oll_w_lg_nl0OO0OOO46114w(0) OR NOT(nl0iOiO1l); + wire_nli0iOl0i_dataout <= wire_nlill0Oll_w_lg_nl0OOi10i46110w(0) OR NOT(nl0iOiO1l); + wire_nli0iOl0l_dataout <= wire_nlill0Oll_w_lg_nl0OOi10l46109w(0) OR NOT(nl0iOiO1l); + wire_nli0iOl0O_dataout <= wire_nlill0Oll_w_lg_nl0OOi10O46108w(0) OR NOT(nl0iOiO1l); + wire_nli0iOl1i_dataout <= wire_nlill0Oll_w_lg_nl0OOi11i46113w(0) OR NOT(nl0iOiO1l); + wire_nli0iOl1l_dataout <= wire_nlill0Oll_w_lg_nl0OOi11l46112w(0) OR NOT(nl0iOiO1l); + wire_nli0iOl1O_dataout <= wire_nlill0Oll_w_lg_nl0OOi11O46111w(0) OR NOT(nl0iOiO1l); + wire_nli0iOli_dataout <= wire_nlii11lO_dataout WHEN nli1l0ii = '1' ELSE nli1liii; + wire_nli0iOlil_dataout <= (NOT k_conf(64)) WHEN niOiiOO0O = '1' ELSE wire_nli0l11li_dataout; + wire_nli0iOlil_w_lg_dataout47703w(0) <= wire_nli0iOlil_dataout AND wire_nli0l1iOi_w_lg_dataout47702w(0); + wire_nli0iOliO_dataout <= (NOT k_conf(65)) WHEN niOiiOO0O = '1' ELSE wire_nli0l11ll_dataout; + wire_nli0iOliO_w_lg_dataout47669w(0) <= wire_nli0iOliO_dataout AND wire_nli0l1iOl_w_lg_dataout47668w(0); + wire_nli0iOll_dataout <= wire_nlii11Oi_dataout WHEN nli1l0ii = '1' ELSE nli1liil; + wire_nli0iOlli_dataout <= (NOT k_conf(66)) WHEN niOiiOO0O = '1' ELSE wire_nli0l11lO_dataout; + wire_nli0iOlli_w_lg_dataout47635w(0) <= wire_nli0iOlli_dataout AND wire_nli0l1iOO_w_lg_dataout47634w(0); + wire_nli0iOlll_dataout <= (NOT k_conf(67)) WHEN niOiiOO0O = '1' ELSE wire_nli0l11Oi_dataout; + wire_nli0iOlll_w_lg_dataout47600w(0) <= wire_nli0iOlll_dataout AND wire_nli0l1l1i_w_lg_dataout47599w(0); + wire_nli0iOllO_dataout <= (NOT k_conf(68)) WHEN niOiiOO0O = '1' ELSE wire_nli0l11Ol_dataout; + wire_nli0iOllO_w_lg_dataout47566w(0) <= wire_nli0iOllO_dataout AND wire_nli0l1l1l_w_lg_dataout47565w(0); + wire_nli0iOlO_dataout <= wire_nlii11Ol_dataout WHEN nli1l0ii = '1' ELSE nli1liiO; + wire_nli0iOlOi_dataout <= (NOT k_conf(69)) WHEN niOiiOO0O = '1' ELSE wire_nli0l11OO_dataout; + wire_nli0iOlOi_w_lg_dataout47535w(0) <= wire_nli0iOlOi_dataout AND wire_nli0l1l1O_w_lg_dataout47534w(0); + wire_nli0iOlOl_dataout <= (NOT k_conf(70)) WHEN niOiiOO0O = '1' ELSE wire_nli0l101i_dataout; + wire_nli0iOlOl_w_lg_dataout47503w(0) <= wire_nli0iOlOl_dataout AND wire_nli0l1l0i_w_lg_dataout47502w(0); + wire_nli0iOlOO_dataout <= (NOT k_conf(71)) WHEN niOiiOO0O = '1' ELSE wire_nli0l101l_dataout; + wire_nli0iOlOO_w_lg_dataout47471w(0) <= wire_nli0iOlOO_dataout AND wire_nli0l1l0l_w_lg_dataout47470w(0); + wire_nli0iOO0i_dataout <= (NOT k_conf(75)) WHEN niOiiOO0O = '1' ELSE wire_nli0l100O_dataout; + wire_nli0iOO0i_w_lg_dataout47347w(0) <= wire_nli0iOO0i_dataout AND wire_nli0l1liO_w_lg_dataout47346w(0); + wire_nli0iOO0l_dataout <= (NOT k_conf(76)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10ii_dataout; + wire_nli0iOO0l_w_lg_dataout47316w(0) <= wire_nli0iOO0l_dataout AND wire_nli0l1lli_w_lg_dataout47315w(0); + wire_nli0iOO0O_dataout <= (NOT k_conf(77)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10il_dataout; + wire_nli0iOO0O_w_lg_dataout47286w(0) <= wire_nli0iOO0O_dataout AND wire_nli0l1lll_w_lg_dataout47285w(0); + wire_nli0iOO1i_dataout <= (NOT k_conf(72)) WHEN niOiiOO0O = '1' ELSE wire_nli0l101O_dataout; + wire_nli0iOO1i_w_lg_dataout47439w(0) <= wire_nli0iOO1i_dataout AND wire_nli0l1l0O_w_lg_dataout47438w(0); + wire_nli0iOO1l_dataout <= (NOT k_conf(73)) WHEN niOiiOO0O = '1' ELSE wire_nli0l100i_dataout; + wire_nli0iOO1l_w_lg_dataout47409w(0) <= wire_nli0iOO1l_dataout AND wire_nli0l1lii_w_lg_dataout47408w(0); + wire_nli0iOO1O_dataout <= (NOT k_conf(74)) WHEN niOiiOO0O = '1' ELSE wire_nli0l100l_dataout; + wire_nli0iOO1O_w_lg_dataout47379w(0) <= wire_nli0iOO1O_dataout AND wire_nli0l1lil_w_lg_dataout47378w(0); + wire_nli0iOOi_dataout <= wire_nlii11OO_dataout WHEN nli1l0ii = '1' ELSE nli1lili; + wire_nli0iOOii_dataout <= (NOT k_conf(78)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10iO_dataout; + wire_nli0iOOii_w_lg_dataout47255w(0) <= wire_nli0iOOii_dataout AND wire_nli0l1llO_w_lg_dataout47254w(0); + wire_nli0iOOil_dataout <= (NOT k_conf(79)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10li_dataout; + wire_nli0iOOil_w_lg_dataout47224w(0) <= wire_nli0iOOil_dataout AND wire_nli0l1lOi_w_lg_dataout47223w(0); + wire_nli0iOOiO_dataout <= (NOT k_conf(80)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10ll_dataout; + wire_nli0iOOiO_w_lg_dataout47192w(0) <= wire_nli0iOOiO_dataout AND wire_nli0l1lOl_w_lg_dataout47191w(0); + wire_nli0iOOl_dataout <= wire_nlii101i_dataout WHEN nli1l0ii = '1' ELSE nli1lill; + wire_nli0iOOli_dataout <= (NOT k_conf(81)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10lO_dataout; + wire_nli0iOOli_w_lg_dataout47160w(0) <= wire_nli0iOOli_dataout AND wire_nli0l1lOO_w_lg_dataout47159w(0); + wire_nli0iOOll_dataout <= (NOT k_conf(82)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10Oi_dataout; + wire_nli0iOOll_w_lg_dataout47131w(0) <= wire_nli0iOOll_dataout AND wire_nli0l1O1i_w_lg_dataout47130w(0); + wire_nli0iOOlO_dataout <= (NOT k_conf(83)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10Ol_dataout; + wire_nli0iOOlO_w_lg_dataout47101w(0) <= wire_nli0iOOlO_dataout AND wire_nli0l1O1l_w_lg_dataout47100w(0); + wire_nli0iOOO_dataout <= wire_nlii101l_dataout WHEN nli1l0ii = '1' ELSE nli1lilO; + wire_nli0iOOOi_dataout <= (NOT k_conf(84)) WHEN niOiiOO0O = '1' ELSE wire_nli0l10OO_dataout; + wire_nli0iOOOi_w_lg_dataout47069w(0) <= wire_nli0iOOOi_dataout AND wire_nli0l1O1O_w_lg_dataout47068w(0); + wire_nli0iOOOl_dataout <= (NOT k_conf(85)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1i1i_dataout; + wire_nli0iOOOl_w_lg_dataout47037w(0) <= wire_nli0iOOOl_dataout AND wire_nli0l1O0i_w_lg_dataout47036w(0); + wire_nli0iOOOO_dataout <= (NOT k_conf(86)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1i1l_dataout; + wire_nli0iOOOO_w_lg_dataout47008w(0) <= wire_nli0iOOOO_dataout AND wire_nli0l1O0l_w_lg_dataout47007w(0); + wire_nli0l000i_dataout <= wire_w_lg_niOil11ii45957w(0) OR NOT(niOil100O); + wire_nli0l000i_w_lg_dataout47129w(0) <= wire_nli0l000i_dataout AND wire_nli0li11O_w_lg_dataout47128w(0); + wire_nli0l000l_dataout <= wire_w_lg_niOil11il45956w(0) OR NOT(niOil100O); + wire_nli0l000l_w_lg_dataout47099w(0) <= wire_nli0l000l_dataout AND wire_nli0li10i_w_lg_dataout47098w(0); + wire_nli0l000O_dataout <= wire_w_lg_niOil11iO45955w(0) WHEN niOil100O = '1' ELSE wire_nli0l0l1l_dataout; + wire_nli0l000O_w_lg_dataout47067w(0) <= wire_nli0l000O_dataout AND wire_nli0li10l_w_lg_dataout47066w(0); + wire_nli0l001i_dataout <= wire_w_lg_niOil110i45960w(0) WHEN niOil100O = '1' ELSE wire_nli0l0iOO_dataout; + wire_nli0l001i_w_lg_dataout47222w(0) <= wire_nli0l001i_dataout AND wire_nli0l0OOO_w_lg_dataout47221w(0); + wire_nli0l001l_dataout <= wire_w_lg_niOil110l45959w(0) WHEN niOil100O = '1' ELSE wire_nli0l0l1i_dataout; + wire_nli0l001l_w_lg_dataout47190w(0) <= wire_nli0l001l_dataout AND wire_nli0li11i_w_lg_dataout47189w(0); + wire_nli0l001O_dataout <= wire_w_lg_niOil110O45958w(0) OR NOT(niOil100O); + wire_nli0l001O_w_lg_dataout47158w(0) <= wire_nli0l001O_dataout AND wire_nli0li11l_w_lg_dataout47157w(0); + wire_nli0l00i_dataout <= wire_nlii1i0O_dataout WHEN nli1l0ii = '1' ELSE nli1llil; + wire_nli0l00ii_dataout <= wire_w_lg_niOil11li45954w(0) WHEN niOil100O = '1' ELSE wire_nli0l0l1O_dataout; + wire_nli0l00ii_w_lg_dataout47035w(0) <= wire_nli0l00ii_dataout AND wire_nli0li10O_w_lg_dataout47034w(0); + wire_nli0l00il_dataout <= wire_w_lg_niOil11ll45953w(0) WHEN niOil100O = '1' ELSE wire_nli0l0l0i_dataout; + wire_nli0l00il_w_lg_dataout47006w(0) <= wire_nli0l00il_dataout AND wire_nli0li1ii_w_lg_dataout47005w(0); + wire_nli0l00iO_dataout <= wire_w_lg_niOil11lO45952w(0) WHEN niOil100O = '1' ELSE wire_nli0l0l0l_dataout; + wire_nli0l00iO_w_lg_dataout46979w(0) <= wire_nli0l00iO_dataout AND wire_nli0li1il_w_lg_dataout46978w(0); + wire_nli0l00l_dataout <= wire_nlii1iil_dataout AND nli1l0ii; + wire_nli0l00li_dataout <= wire_w_lg_niOil11Oi45951w(0) WHEN niOil100O = '1' ELSE wire_nli0l0l0O_dataout; + wire_nli0l00li_w_lg_dataout46949w(0) <= wire_nli0l00li_dataout AND wire_nli0li1iO_w_lg_dataout46948w(0); + wire_nli0l00ll_dataout <= wire_w_lg_niOil11Ol45950w(0) WHEN niOil100O = '1' ELSE wire_nli0l0lii_dataout; + wire_nli0l00ll_w_lg_dataout46920w(0) <= wire_nli0l00ll_dataout AND wire_nli0li1li_w_lg_dataout46919w(0); + wire_nli0l00lO_dataout <= wire_w_lg_niOil11OO45949w(0) WHEN niOil100O = '1' ELSE wire_nli0l0lil_dataout; + wire_nli0l00lO_w_lg_dataout46891w(0) <= wire_nli0l00lO_dataout AND wire_nli0li1ll_w_lg_dataout46890w(0); + wire_nli0l00O_dataout <= wire_nlii1iiO_dataout WHEN nli1l0ii = '1' ELSE nli1lliO; + wire_nli0l00Oi_dataout <= wire_w_lg_niOil101i45948w(0) WHEN niOil100O = '1' ELSE wire_nli0l0liO_dataout; + wire_nli0l00Oi_w_lg_dataout46864w(0) <= wire_nli0l00Oi_dataout AND wire_nli0li1lO_w_lg_dataout46863w(0); + wire_nli0l00Ol_dataout <= wire_w_lg_niOil101l45947w(0) WHEN niOil100O = '1' ELSE wire_nli0l0lli_dataout; + wire_nli0l00Ol_w_lg_dataout46837w(0) <= wire_nli0l00Ol_dataout AND wire_nli0li1Oi_w_lg_dataout46836w(0); + wire_nli0l00OO_dataout <= wire_w_lg_niOil101O45946w(0) WHEN niOil100O = '1' ELSE wire_nli0l0lll_dataout; + wire_nli0l00OO_w_lg_dataout46810w(0) <= wire_nli0l00OO_dataout AND wire_nli0li1Ol_w_lg_dataout46809w(0); + wire_nli0l010i_dataout <= wire_nl0O0lO0l_w_lg_dataout45972w(0) OR NOT(niOil100O); + wire_nli0l010i_w_lg_dataout47598w(0) <= wire_nli0l010i_dataout AND wire_nli0l0O1O_w_lg_dataout47597w(0); + wire_nli0l010l_dataout <= wire_w_lg_niOiiOOil45971w(0) WHEN niOil100O = '1' ELSE wire_nli0l0i0i_dataout; + wire_nli0l010l_w_lg_dataout47564w(0) <= wire_nli0l010l_dataout AND wire_nli0l0O0i_w_lg_dataout47563w(0); + wire_nli0l010O_dataout <= wire_w_lg_niOiiOOiO45970w(0) WHEN niOil100O = '1' ELSE wire_nli0l0i0l_dataout; + wire_nli0l010O_w_lg_dataout47533w(0) <= wire_nli0l010O_dataout AND wire_nli0l0O0l_w_lg_dataout47532w(0); + wire_nli0l011i_dataout <= wire_nl0O0lO1l_w_lg_dataout45975w(0) WHEN niOil100O = '1' ELSE wire_nli0l0i1O_dataout; + wire_nli0l011i_w_lg_dataout47701w(0) <= wire_nli0l011i_dataout AND wire_nli0l0lOO_w_lg_dataout47700w(0); + wire_nli0l011l_dataout <= wire_nl0O0lO1O_w_lg_dataout45974w(0) OR NOT(niOil100O); + wire_nli0l011l_w_lg_dataout47667w(0) <= wire_nli0l011l_dataout AND wire_nli0l0O1i_w_lg_dataout47666w(0); + wire_nli0l011O_dataout <= wire_nl0O0lO0i_w_lg_dataout45973w(0) OR NOT(niOil100O); + wire_nli0l011O_w_lg_dataout47633w(0) <= wire_nli0l011O_dataout AND wire_nli0l0O1l_w_lg_dataout47632w(0); + wire_nli0l01i_dataout <= wire_nlii1i1O_dataout WHEN nli1l0ii = '1' ELSE nli1ll0l; + wire_nli0l01ii_dataout <= wire_w_lg_niOiiOOli45969w(0) WHEN niOil100O = '1' ELSE wire_nli0l0i0O_dataout; + wire_nli0l01ii_w_lg_dataout47501w(0) <= wire_nli0l01ii_dataout AND wire_nli0l0O0O_w_lg_dataout47500w(0); + wire_nli0l01il_dataout <= wire_w_lg_niOiiOOll45968w(0) WHEN niOil100O = '1' ELSE wire_nli0l0iii_dataout; + wire_nli0l01il_w_lg_dataout47469w(0) <= wire_nli0l01il_dataout AND wire_nli0l0Oii_w_lg_dataout47468w(0); + wire_nli0l01iO_dataout <= wire_w_lg_niOiiOOlO45967w(0) WHEN niOil100O = '1' ELSE wire_nli0l0iil_dataout; + wire_nli0l01iO_w_lg_dataout47437w(0) <= wire_nli0l01iO_dataout AND wire_nli0l0Oil_w_lg_dataout47436w(0); + wire_nli0l01l_dataout <= wire_nlii1i0i_dataout WHEN nli1l0ii = '1' ELSE nli1ll0O; + wire_nli0l01li_dataout <= wire_w_lg_niOiiOOOi45966w(0) WHEN niOil100O = '1' ELSE wire_nli0l0iiO_dataout; + wire_nli0l01li_w_lg_dataout47407w(0) <= wire_nli0l01li_dataout AND wire_nli0l0OiO_w_lg_dataout47406w(0); + wire_nli0l01ll_dataout <= wire_w_lg_niOiiOOOl45965w(0) WHEN niOil100O = '1' ELSE wire_nli0l0ili_dataout; + wire_nli0l01ll_w_lg_dataout47377w(0) <= wire_nli0l01ll_dataout AND wire_nli0l0Oli_w_lg_dataout47376w(0); + wire_nli0l01lO_dataout <= wire_w_lg_niOiiOOOO45964w(0) WHEN niOil100O = '1' ELSE wire_nli0l0ill_dataout; + wire_nli0l01lO_w_lg_dataout47345w(0) <= wire_nli0l01lO_dataout AND wire_nli0l0Oll_w_lg_dataout47344w(0); + wire_nli0l01O_dataout <= wire_nlii1i0l_dataout WHEN nli1l0ii = '1' ELSE nli1llii; + wire_nli0l01Oi_dataout <= wire_w_lg_niOil111i45963w(0) WHEN niOil100O = '1' ELSE wire_nli0l0ilO_dataout; + wire_nli0l01Oi_w_lg_dataout47314w(0) <= wire_nli0l01Oi_dataout AND wire_nli0l0OlO_w_lg_dataout47313w(0); + wire_nli0l01Ol_dataout <= wire_w_lg_niOil111l45962w(0) WHEN niOil100O = '1' ELSE wire_nli0l0iOi_dataout; + wire_nli0l01Ol_w_lg_dataout47284w(0) <= wire_nli0l01Ol_dataout AND wire_nli0l0OOi_w_lg_dataout47283w(0); + wire_nli0l01OO_dataout <= wire_w_lg_niOil111O45961w(0) WHEN niOil100O = '1' ELSE wire_nli0l0iOl_dataout; + wire_nli0l01OO_w_lg_dataout47253w(0) <= wire_nli0l01OO_dataout AND wire_nli0l0OOl_w_lg_dataout47252w(0); + wire_nli0l0i0i_dataout <= wire_nlill0Oll_w_lg_nl0Ol0lOl45943w(0) OR NOT(nl0iOilOl); + wire_nli0l0i0l_dataout <= wire_nlill0Oll_w_lg_nl0Ol0lOO45942w(0) OR NOT(nl0iOilOl); + wire_nli0l0i0O_dataout <= wire_nlill0Oll_w_lg_nl0Ol0O1i45941w(0) OR NOT(nl0iOilOl); + wire_nli0l0i1i_dataout <= wire_w_lg_niOil100i45945w(0) WHEN niOil100O = '1' ELSE wire_nli0l0llO_dataout; + wire_nli0l0i1i_w_lg_dataout46783w(0) <= wire_nli0l0i1i_dataout AND wire_nli0li1OO_w_lg_dataout46782w(0); + wire_nli0l0i1l_dataout <= wire_w_lg_niOil100l45944w(0) WHEN niOil100O = '1' ELSE wire_nli0l0lOi_dataout; + wire_nli0l0i1l_w_lg_dataout46756w(0) <= wire_nli0l0i1l_dataout AND wire_nli0li01i_w_lg_dataout46755w(0); + wire_nli0l0i1O_dataout <= wire_w_lg_w_k_bar_range45930w45931w(0) OR NOT(nl0iOilOl); + wire_nli0l0ii_dataout <= wire_nlii1ili_dataout WHEN nli1l0ii = '1' ELSE nli1llli; + wire_nli0l0iii_dataout <= wire_nlill0Oll_w_lg_nl0Ol0O1l45940w(0) OR NOT(nl0iOilOl); + wire_nli0l0iil_dataout <= wire_nlill0Oll_w_lg_nl0Ol0O1O45939w(0) OR NOT(nl0iOilOl); + wire_nli0l0iiO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0O0i45938w(0) OR NOT(nl0iOilOl); + wire_nli0l0il_dataout <= wire_nlii1ill_dataout WHEN nli1l0ii = '1' ELSE nli1llll; + wire_nli0l0ili_dataout <= wire_nlill0Oll_w_lg_nl0Ol0O0l45937w(0) OR NOT(nl0iOilOl); + wire_nli0l0ill_dataout <= wire_nlill0Oll_w_lg_nl0Ol0O0O45936w(0) OR NOT(nl0iOilOl); + wire_nli0l0ilO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0Oii45935w(0) OR NOT(nl0iOilOl); + wire_nli0l0iO_dataout <= wire_nlii1ilO_dataout WHEN nli1l0ii = '1' ELSE nli1lllO; + wire_nli0l0iOi_dataout <= wire_nlill0Oll_w_lg_nl0Ol0Oil45934w(0) OR NOT(nl0iOilOl); + wire_nli0l0iOl_dataout <= wire_nlill0Oll_w_lg_nl0Ol0OiO45933w(0) OR NOT(nl0iOilOl); + wire_nli0l0iOO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0Oli45932w(0) OR NOT(nl0iOilOl); + wire_nli0l0l0i_dataout <= wire_nlill0Oll_w_lg_nl0Ol001l45927w(0) OR NOT(nl0iOilOl); + wire_nli0l0l0l_dataout <= wire_nlill0Oll_w_lg_nl0Ol001O45926w(0) OR NOT(nl0iOilOl); + wire_nli0l0l0O_dataout <= wire_nlill0Oll_w_lg_nl0Ol000i45925w(0) OR NOT(nl0iOilOl); + wire_nli0l0l1i_dataout <= wire_w_lg_w_k_bar_range45930w45931w(0) OR NOT(nl0iOilOl); + wire_nli0l0l1l_dataout <= wire_nlill0Oll_w_lg_nl0Ol01OO45929w(0) OR NOT(nl0iOilOl); + wire_nli0l0l1O_dataout <= wire_nlill0Oll_w_lg_nl0Ol001i45928w(0) OR NOT(nl0iOilOl); + wire_nli0l0li_dataout <= wire_nlii1iOi_dataout WHEN nli1l0ii = '1' ELSE nli1llOi; + wire_nli0l0lii_dataout <= wire_nlill0Oll_w_lg_nl0Ol000l45924w(0) OR NOT(nl0iOilOl); + wire_nli0l0lil_dataout <= wire_nlill0Oll_w_lg_nl0Ol000O45923w(0) OR NOT(nl0iOilOl); + wire_nli0l0liO_dataout <= wire_nlill0Oll_w_lg_nl0Ol00ii45922w(0) OR NOT(nl0iOilOl); + wire_nli0l0ll_dataout <= wire_nlii1iOl_dataout WHEN nli1l0ii = '1' ELSE nli1llOl; + wire_nli0l0lli_dataout <= wire_nlill0Oll_w_lg_nl0Ol00il45921w(0) OR NOT(nl0iOilOl); + wire_nli0l0lll_dataout <= wire_nlill0Oll_w_lg_nl0Ol00iO45920w(0) OR NOT(nl0iOilOl); + wire_nli0l0llO_dataout <= wire_nlill0Oll_w_lg_nl0Ol00li45919w(0) OR NOT(nl0iOilOl); + wire_nli0l0lO_dataout <= wire_nlii1iOO_dataout WHEN nli1l0ii = '1' ELSE nli1llOO; + wire_nli0l0lOi_dataout <= wire_nlill0Oll_w_lg_nl0Ol00ll45918w(0) OR NOT(nl0iOilOl); + wire_nli0l0lOO_dataout <= wire_w_lg_w_k_bar_range45915w45916w(0) OR NOT(niOil1l0l); + wire_nli0l0lOO_w_lg_dataout47700w(0) <= wire_nli0l0lOO_dataout AND wire_nli0liilO_w_lg_dataout47699w(0); + wire_nli0l0O0i_dataout <= wire_w_lg_niOil10ii45908w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li01l_dataout; + wire_nli0l0O0i_w_lg_dataout47563w(0) <= wire_nli0l0O0i_dataout AND wire_nli0lil1i_w_lg_dataout47562w(0); + wire_nli0l0O0l_dataout <= wire_w_lg_niOil10il45907w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li01O_dataout; + wire_nli0l0O0l_w_lg_dataout47532w(0) <= wire_nli0l0O0l_dataout AND wire_nli0lil1l_w_lg_dataout47531w(0); + wire_nli0l0O0O_dataout <= wire_w_lg_niOil10iO45906w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li00i_dataout; + wire_nli0l0O0O_w_lg_dataout47500w(0) <= wire_nli0l0O0O_dataout AND wire_nli0lil1O_w_lg_dataout47499w(0); + wire_nli0l0O1i_dataout <= wire_w_lg_w_k_bar_range45913w45914w(0) OR NOT(niOil1l0l); + wire_nli0l0O1i_w_lg_dataout47666w(0) <= wire_nli0l0O1i_dataout AND wire_nli0liiOi_w_lg_dataout47665w(0); + wire_nli0l0O1l_dataout <= (NOT k_bar(130)) OR NOT(niOil1l0l); + wire_nli0l0O1l_w_lg_dataout47632w(0) <= wire_nli0l0O1l_dataout AND wire_nli0liiOl_w_lg_dataout47631w(0); + wire_nli0l0O1O_dataout <= (NOT k_bar(131)) OR NOT(niOil1l0l); + wire_nli0l0O1O_w_lg_dataout47597w(0) <= wire_nli0l0O1O_dataout AND wire_nli0liiOO_w_lg_dataout47596w(0); + wire_nli0l0Oi_dataout <= wire_nlii1l1i_dataout WHEN nli1l0ii = '1' ELSE nli1lO1i; + wire_nli0l0Oii_dataout <= wire_w_lg_niOil10li45905w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li00l_dataout; + wire_nli0l0Oii_w_lg_dataout47468w(0) <= wire_nli0l0Oii_dataout AND wire_nli0lil0i_w_lg_dataout47467w(0); + wire_nli0l0Oil_dataout <= wire_w_lg_niOil10ll45904w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li00O_dataout; + wire_nli0l0Oil_w_lg_dataout47436w(0) <= wire_nli0l0Oil_dataout AND wire_nli0lil0l_w_lg_dataout47435w(0); + wire_nli0l0OiO_dataout <= wire_w_lg_niOil10lO45903w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0ii_dataout; + wire_nli0l0OiO_w_lg_dataout47406w(0) <= wire_nli0l0OiO_dataout AND wire_nli0lil0O_w_lg_dataout47405w(0); + wire_nli0l0Ol_dataout <= wire_nlii1l1l_dataout WHEN nli1l0ii = '1' ELSE nli1lO1l; + wire_nli0l0Oli_dataout <= wire_w_lg_niOil10Oi45902w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0il_dataout; + wire_nli0l0Oli_w_lg_dataout47376w(0) <= wire_nli0l0Oli_dataout AND wire_nli0lilii_w_lg_dataout47375w(0); + wire_nli0l0Oll_dataout <= wire_w_lg_niOil10Ol45901w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0iO_dataout; + wire_nli0l0Oll_w_lg_dataout47344w(0) <= wire_nli0l0Oll_dataout AND wire_nli0lilil_w_lg_dataout47343w(0); + wire_nli0l0OlO_dataout <= wire_w_lg_niOil10OO45900w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0li_dataout; + wire_nli0l0OlO_w_lg_dataout47313w(0) <= wire_nli0l0OlO_dataout AND wire_nli0liliO_w_lg_dataout47312w(0); + wire_nli0l0OO_dataout <= wire_nlii1l1O_dataout WHEN nli1l0ii = '1' ELSE nli1lO1O; + wire_nli0l0OOi_dataout <= wire_w_lg_niOil1i1i45899w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0ll_dataout; + wire_nli0l0OOi_w_lg_dataout47283w(0) <= wire_nli0l0OOi_dataout AND wire_nli0lilli_w_lg_dataout47282w(0); + wire_nli0l0OOl_dataout <= wire_w_lg_niOil1i1l45898w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0lO_dataout; + wire_nli0l0OOl_w_lg_dataout47252w(0) <= wire_nli0l0OOl_dataout AND wire_nli0lilll_w_lg_dataout47251w(0); + wire_nli0l0OOO_dataout <= wire_w_lg_niOil1i1O45897w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0Oi_dataout; + wire_nli0l0OOO_w_lg_dataout47221w(0) <= wire_nli0l0OOO_dataout AND wire_nli0lillO_w_lg_dataout47220w(0); + wire_nli0l100i_dataout <= wire_nlill0Oll_w_lg_nl0Ol1Oii46033w(0) OR NOT(nl0iOiO1i); + wire_nli0l100l_dataout <= wire_nlill0Oll_w_lg_nl0Ol1Oil46032w(0) OR NOT(nl0iOiO1i); + wire_nli0l100O_dataout <= wire_nlill0Oll_w_lg_nl0Ol1OiO46031w(0) OR NOT(nl0iOiO1i); + wire_nli0l101i_dataout <= wire_nlill0Oll_w_lg_nl0Ol1O0i46036w(0) OR NOT(nl0iOiO1i); + wire_nli0l101l_dataout <= wire_nlill0Oll_w_lg_nl0Ol1O0l46035w(0) OR NOT(nl0iOiO1i); + wire_nli0l101O_dataout <= wire_nlill0Oll_w_lg_nl0Ol1O0O46034w(0) OR NOT(nl0iOiO1i); + wire_nli0l10i_dataout <= wire_nlii100O_dataout WHEN nli1l0ii = '1' ELSE nli01i1l; + wire_nli0l10ii_dataout <= wire_nlill0Oll_w_lg_nl0Ol1Oli46030w(0) OR NOT(nl0iOiO1i); + wire_nli0l10il_dataout <= wire_nlill0Oll_w_lg_nl0Ol1Oll46029w(0) OR NOT(nl0iOiO1i); + wire_nli0l10iO_dataout <= wire_nlill0Oll_w_lg_nl0Ol1OlO46028w(0) OR NOT(nl0iOiO1i); + wire_nli0l10l_dataout <= wire_nlii10ii_dataout WHEN nli1l0ii = '1' ELSE nli01i1O; + wire_nli0l10li_dataout <= wire_nlill0Oll_w_lg_nl0Ol1OOi46027w(0) OR NOT(nl0iOiO1i); + wire_nli0l10ll_dataout <= wire_nlill0Oll_w_lg_nl0Ol1OOl46026w(0) OR NOT(nl0iOiO1i); + wire_nli0l10lO_dataout <= wire_nlill0Oll_w_lg_nl0Ol1OOO46025w(0) OR NOT(nl0iOiO1i); + wire_nli0l10O_dataout <= wire_nlii10il_dataout WHEN nli1l0ii = '1' ELSE nli01i0i; + wire_nli0l10Oi_dataout <= wire_nlill0Oll_w_lg_nl0Ol011i46024w(0) OR NOT(nl0iOiO1i); + wire_nli0l10Ol_dataout <= wire_nlill0Oll_w_lg_nl0Ol011l46023w(0) OR NOT(nl0iOiO1i); + wire_nli0l10OO_dataout <= wire_nlill0Oll_w_lg_nl0Ol011O46022w(0) OR NOT(nl0iOiO1i); + wire_nli0l110i_dataout <= (NOT k_conf(90)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1i0O_dataout; + wire_nli0l110i_w_lg_dataout46893w(0) <= wire_nli0l110i_dataout AND wire_nli0l1OiO_w_lg_dataout46892w(0); + wire_nli0l110l_dataout <= (NOT k_conf(91)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1iii_dataout; + wire_nli0l110l_w_lg_dataout46866w(0) <= wire_nli0l110l_dataout AND wire_nli0l1Oli_w_lg_dataout46865w(0); + wire_nli0l110O_dataout <= (NOT k_conf(92)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1iil_dataout; + wire_nli0l110O_w_lg_dataout46839w(0) <= wire_nli0l110O_dataout AND wire_nli0l1Oll_w_lg_dataout46838w(0); + wire_nli0l111i_dataout <= (NOT k_conf(87)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1i1O_dataout; + wire_nli0l111i_w_lg_dataout46981w(0) <= wire_nli0l111i_dataout AND wire_nli0l1O0O_w_lg_dataout46980w(0); + wire_nli0l111l_dataout <= (NOT k_conf(88)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1i0i_dataout; + wire_nli0l111l_w_lg_dataout46951w(0) <= wire_nli0l111l_dataout AND wire_nli0l1Oii_w_lg_dataout46950w(0); + wire_nli0l111O_dataout <= (NOT k_conf(89)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1i0l_dataout; + wire_nli0l111O_w_lg_dataout46922w(0) <= wire_nli0l111O_dataout AND wire_nli0l1Oil_w_lg_dataout46921w(0); + wire_nli0l11i_dataout <= wire_nlii101O_dataout WHEN nli1l0ii = '1' ELSE nli1liOi; + wire_nli0l11ii_dataout <= (NOT k_conf(93)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1iiO_dataout; + wire_nli0l11ii_w_lg_dataout46812w(0) <= wire_nli0l11ii_dataout AND wire_nli0l1OlO_w_lg_dataout46811w(0); + wire_nli0l11il_dataout <= (NOT k_conf(94)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1ili_dataout; + wire_nli0l11il_w_lg_dataout46785w(0) <= wire_nli0l11il_dataout AND wire_nli0l1OOi_w_lg_dataout46784w(0); + wire_nli0l11iO_dataout <= (NOT k_conf(95)) WHEN niOiiOO0O = '1' ELSE wire_nli0l1ill_dataout; + wire_nli0l11iO_w_lg_dataout46758w(0) <= wire_nli0l11iO_dataout AND wire_nli0l1OOl_w_lg_dataout46757w(0); + wire_nli0l11l_dataout <= wire_nlii100i_dataout WHEN nli1l0ii = '1' ELSE nli1liOl; + wire_nli0l11li_dataout <= wire_nlill0Oll_w_lg_nl0Ol1lOi46042w(0) OR NOT(nl0iOiO1i); + wire_nli0l11ll_dataout <= wire_nlill0Oll_w_lg_nl0Ol1lOl46041w(0) OR NOT(nl0iOiO1i); + wire_nli0l11lO_dataout <= wire_nlill0Oll_w_lg_nl0Ol1lOO46040w(0) OR NOT(nl0iOiO1i); + wire_nli0l11O_dataout <= wire_nlii100l_dataout WHEN nli1l0ii = '1' ELSE nli1liOO; + wire_nli0l11Oi_dataout <= wire_nlill0Oll_w_lg_nl0Ol1O1i46039w(0) OR NOT(nl0iOiO1i); + wire_nli0l11Ol_dataout <= wire_nlill0Oll_w_lg_nl0Ol1O1l46038w(0) OR NOT(nl0iOiO1i); + wire_nli0l11OO_dataout <= wire_nlill0Oll_w_lg_nl0Ol1O1O46037w(0) OR NOT(nl0iOiO1i); + wire_nli0l1i0i_dataout <= wire_nlill0Oll_w_lg_nl0Ol01ii46018w(0) OR NOT(nl0iOiO1i); + wire_nli0l1i0l_dataout <= wire_nlill0Oll_w_lg_nl0Ol01il46017w(0) OR NOT(nl0iOiO1i); + wire_nli0l1i0O_dataout <= wire_nlill0Oll_w_lg_nl0Ol01iO46016w(0) OR NOT(nl0iOiO1i); + wire_nli0l1i1i_dataout <= wire_nlill0Oll_w_lg_nl0Ol010i46021w(0) OR NOT(nl0iOiO1i); + wire_nli0l1i1l_dataout <= wire_nlill0Oll_w_lg_nl0Ol010l46020w(0) OR NOT(nl0iOiO1i); + wire_nli0l1i1O_dataout <= wire_nlill0Oll_w_lg_nl0Ol010O46019w(0) OR NOT(nl0iOiO1i); + wire_nli0l1ii_dataout <= wire_nlii10iO_dataout WHEN nli1l0ii = '1' ELSE nli01i0l; + wire_nli0l1iii_dataout <= wire_nlill0Oll_w_lg_nl0Ol01li46015w(0) OR NOT(nl0iOiO1i); + wire_nli0l1iil_dataout <= wire_nlill0Oll_w_lg_nl0Ol01ll46014w(0) OR NOT(nl0iOiO1i); + wire_nli0l1iiO_dataout <= wire_nlill0Oll_w_lg_nl0Ol01lO46013w(0) OR NOT(nl0iOiO1i); + wire_nli0l1il_dataout <= wire_nlii10li_dataout WHEN nli1l0ii = '1' ELSE nli01i0O; + wire_nli0l1ili_dataout <= wire_nlill0Oll_w_lg_nl0Ol01Oi46012w(0) OR NOT(nl0iOiO1i); + wire_nli0l1ill_dataout <= wire_nlill0Oll_w_lg_nl0Ol01Ol46011w(0) OR NOT(nl0iOiO1i); + wire_nli0l1iO_dataout <= wire_nlii10ll_dataout WHEN nli1l0ii = '1' ELSE nli01iii; + wire_nli0l1iOi_dataout <= wire_nlill0Oll_w_lg_nl0Ol00lO46009w(0) OR NOT(niOiiOOii); + wire_nli0l1iOi_w_lg_dataout47702w(0) <= wire_nli0l1iOi_dataout AND wire_nli0l011i_w_lg_dataout47701w(0); + wire_nli0l1iOl_dataout <= wire_nlill0Oll_w_lg_nl0Ol00Oi46008w(0) OR NOT(niOiiOOii); + wire_nli0l1iOl_w_lg_dataout47668w(0) <= wire_nli0l1iOl_dataout AND wire_nli0l011l_w_lg_dataout47667w(0); + wire_nli0l1iOO_dataout <= wire_nlill0Oll_w_lg_nl0Ol00Ol46007w(0) OR NOT(niOiiOOii); + wire_nli0l1iOO_w_lg_dataout47634w(0) <= wire_nli0l1iOO_dataout AND wire_nli0l011O_w_lg_dataout47633w(0); + wire_nli0l1l0i_dataout <= wire_nlill0Oll_w_lg_nl0Ol0i1O46003w(0) OR NOT(niOiiOOii); + wire_nli0l1l0i_w_lg_dataout47502w(0) <= wire_nli0l1l0i_dataout AND wire_nli0l01ii_w_lg_dataout47501w(0); + wire_nli0l1l0l_dataout <= wire_nlill0Oll_w_lg_nl0Ol0i0i46002w(0) OR NOT(niOiiOOii); + wire_nli0l1l0l_w_lg_dataout47470w(0) <= wire_nli0l1l0l_dataout AND wire_nli0l01il_w_lg_dataout47469w(0); + wire_nli0l1l0O_dataout <= wire_nlill0Oll_w_lg_nl0Ol0i0l46001w(0) OR NOT(niOiiOOii); + wire_nli0l1l0O_w_lg_dataout47438w(0) <= wire_nli0l1l0O_dataout AND wire_nli0l01iO_w_lg_dataout47437w(0); + wire_nli0l1l1i_dataout <= wire_nlill0Oll_w_lg_nl0Ol00OO46006w(0) OR NOT(niOiiOOii); + wire_nli0l1l1i_w_lg_dataout47599w(0) <= wire_nli0l1l1i_dataout AND wire_nli0l010i_w_lg_dataout47598w(0); + wire_nli0l1l1l_dataout <= wire_nlill0Oll_w_lg_nl0Ol0i1i46005w(0) OR NOT(niOiiOOii); + wire_nli0l1l1l_w_lg_dataout47565w(0) <= wire_nli0l1l1l_dataout AND wire_nli0l010l_w_lg_dataout47564w(0); + wire_nli0l1l1O_dataout <= wire_nlill0Oll_w_lg_nl0Ol0i1l46004w(0) OR NOT(niOiiOOii); + wire_nli0l1l1O_w_lg_dataout47534w(0) <= wire_nli0l1l1O_dataout AND wire_nli0l010O_w_lg_dataout47533w(0); + wire_nli0l1li_dataout <= wire_nlii10lO_dataout WHEN nli1l0ii = '1' ELSE nli01iil; + wire_nli0l1lii_dataout <= wire_nlill0Oll_w_lg_nl0Ol0i0O46000w(0) OR NOT(niOiiOOii); + wire_nli0l1lii_w_lg_dataout47408w(0) <= wire_nli0l1lii_dataout AND wire_nli0l01li_w_lg_dataout47407w(0); + wire_nli0l1lil_dataout <= wire_nlill0Oll_w_lg_nl0Ol0iii45999w(0) OR NOT(niOiiOOii); + wire_nli0l1lil_w_lg_dataout47378w(0) <= wire_nli0l1lil_dataout AND wire_nli0l01ll_w_lg_dataout47377w(0); + wire_nli0l1liO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0iil45998w(0) OR NOT(niOiiOOii); + wire_nli0l1liO_w_lg_dataout47346w(0) <= wire_nli0l1liO_dataout AND wire_nli0l01lO_w_lg_dataout47345w(0); + wire_nli0l1ll_dataout <= wire_nlii10Oi_dataout WHEN nli1l0ii = '1' ELSE nli01iiO; + wire_nli0l1lli_dataout <= wire_nlill0Oll_w_lg_nl0Ol0iiO45997w(0) OR NOT(niOiiOOii); + wire_nli0l1lli_w_lg_dataout47315w(0) <= wire_nli0l1lli_dataout AND wire_nli0l01Oi_w_lg_dataout47314w(0); + wire_nli0l1lll_dataout <= wire_nlill0Oll_w_lg_nl0Ol0ili45996w(0) OR NOT(niOiiOOii); + wire_nli0l1lll_w_lg_dataout47285w(0) <= wire_nli0l1lll_dataout AND wire_nli0l01Ol_w_lg_dataout47284w(0); + wire_nli0l1llO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0ill45995w(0) OR NOT(niOiiOOii); + wire_nli0l1llO_w_lg_dataout47254w(0) <= wire_nli0l1llO_dataout AND wire_nli0l01OO_w_lg_dataout47253w(0); + wire_nli0l1lO_dataout <= wire_nlii10Ol_dataout WHEN nli1l0ii = '1' ELSE nli1ll1i; + wire_nli0l1lOi_dataout <= wire_nlill0Oll_w_lg_nl0Ol0ilO45994w(0) OR NOT(niOiiOOii); + wire_nli0l1lOi_w_lg_dataout47223w(0) <= wire_nli0l1lOi_dataout AND wire_nli0l001i_w_lg_dataout47222w(0); + wire_nli0l1lOl_dataout <= wire_nlill0Oll_w_lg_nl0Ol0iOi45993w(0) OR NOT(niOiiOOii); + wire_nli0l1lOl_w_lg_dataout47191w(0) <= wire_nli0l1lOl_dataout AND wire_nli0l001l_w_lg_dataout47190w(0); + wire_nli0l1lOO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0iOl45992w(0) OR NOT(niOiiOOii); + wire_nli0l1lOO_w_lg_dataout47159w(0) <= wire_nli0l1lOO_dataout AND wire_nli0l001O_w_lg_dataout47158w(0); + wire_nli0l1O0i_dataout <= wire_nlill0Oll_w_lg_nl0Ol0l1O45988w(0) OR NOT(niOiiOOii); + wire_nli0l1O0i_w_lg_dataout47036w(0) <= wire_nli0l1O0i_dataout AND wire_nli0l00ii_w_lg_dataout47035w(0); + wire_nli0l1O0l_dataout <= wire_nlill0Oll_w_lg_nl0Ol0l0i45987w(0) OR NOT(niOiiOOii); + wire_nli0l1O0l_w_lg_dataout47007w(0) <= wire_nli0l1O0l_dataout AND wire_nli0l00il_w_lg_dataout47006w(0); + wire_nli0l1O0O_dataout <= wire_nlill0Oll_w_lg_nl0Ol0l0l45986w(0) OR NOT(niOiiOOii); + wire_nli0l1O0O_w_lg_dataout46980w(0) <= wire_nli0l1O0O_dataout AND wire_nli0l00iO_w_lg_dataout46979w(0); + wire_nli0l1O1i_dataout <= wire_nlill0Oll_w_lg_nl0Ol0iOO45991w(0) OR NOT(niOiiOOii); + wire_nli0l1O1i_w_lg_dataout47130w(0) <= wire_nli0l1O1i_dataout AND wire_nli0l000i_w_lg_dataout47129w(0); + wire_nli0l1O1l_dataout <= wire_nlill0Oll_w_lg_nl0Ol0l1i45990w(0) OR NOT(niOiiOOii); + wire_nli0l1O1l_w_lg_dataout47100w(0) <= wire_nli0l1O1l_dataout AND wire_nli0l000l_w_lg_dataout47099w(0); + wire_nli0l1O1O_dataout <= wire_nlill0Oll_w_lg_nl0Ol0l1l45989w(0) OR NOT(niOiiOOii); + wire_nli0l1O1O_w_lg_dataout47068w(0) <= wire_nli0l1O1O_dataout AND wire_nli0l000O_w_lg_dataout47067w(0); + wire_nli0l1Oi_dataout <= wire_nlii10OO_dataout WHEN nli1l0ii = '1' ELSE nli1ll1l; + wire_nli0l1Oii_dataout <= wire_nlill0Oll_w_lg_nl0Ol0l0O45985w(0) OR NOT(niOiiOOii); + wire_nli0l1Oii_w_lg_dataout46950w(0) <= wire_nli0l1Oii_dataout AND wire_nli0l00li_w_lg_dataout46949w(0); + wire_nli0l1Oil_dataout <= wire_nlill0Oll_w_lg_nl0Ol0lii45984w(0) OR NOT(niOiiOOii); + wire_nli0l1Oil_w_lg_dataout46921w(0) <= wire_nli0l1Oil_dataout AND wire_nli0l00ll_w_lg_dataout46920w(0); + wire_nli0l1OiO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0lil45983w(0) OR NOT(niOiiOOii); + wire_nli0l1OiO_w_lg_dataout46892w(0) <= wire_nli0l1OiO_dataout AND wire_nli0l00lO_w_lg_dataout46891w(0); + wire_nli0l1Ol_dataout <= wire_nlii1i1i_dataout WHEN nli1l0ii = '1' ELSE nli1ll1O; + wire_nli0l1Oli_dataout <= wire_nlill0Oll_w_lg_nl0Ol0liO45982w(0) OR NOT(niOiiOOii); + wire_nli0l1Oli_w_lg_dataout46865w(0) <= wire_nli0l1Oli_dataout AND wire_nli0l00Oi_w_lg_dataout46864w(0); + wire_nli0l1Oll_dataout <= wire_nlill0Oll_w_lg_nl0Ol0lli45981w(0) OR NOT(niOiiOOii); + wire_nli0l1Oll_w_lg_dataout46838w(0) <= wire_nli0l1Oll_dataout AND wire_nli0l00Ol_w_lg_dataout46837w(0); + wire_nli0l1OlO_dataout <= wire_nlill0Oll_w_lg_nl0Ol0lll45980w(0) OR NOT(niOiiOOii); + wire_nli0l1OlO_w_lg_dataout46811w(0) <= wire_nli0l1OlO_dataout AND wire_nli0l00OO_w_lg_dataout46810w(0); + wire_nli0l1OO_dataout <= wire_nlii1i1l_dataout WHEN nli1l0ii = '1' ELSE nli1ll0i; + wire_nli0l1OOi_dataout <= wire_nlill0Oll_w_lg_nl0Ol0llO45979w(0) OR NOT(niOiiOOii); + wire_nli0l1OOi_w_lg_dataout46784w(0) <= wire_nli0l1OOi_dataout AND wire_nli0l0i1i_w_lg_dataout46783w(0); + wire_nli0l1OOl_dataout <= wire_nlill0Oll_w_lg_nl0Ol0lOi45978w(0) OR NOT(niOiiOOii); + wire_nli0l1OOl_w_lg_dataout46757w(0) <= wire_nli0l1OOl_dataout AND wire_nli0l0i1l_w_lg_dataout46756w(0); + wire_nli0li00i_dataout <= wire_nlill0Oll_w_lg_nl0OO1lOi45878w(0) OR NOT(nl0iOilOi); + wire_nli0li00l_dataout <= wire_nlill0Oll_w_lg_nl0OO1lOl45877w(0) OR NOT(nl0iOilOi); + wire_nli0li00O_dataout <= wire_nlill0Oll_w_lg_nl0OO1lOO45876w(0) OR NOT(nl0iOilOi); + wire_nli0li01i_dataout <= wire_w_lg_niOil1l0i45881w(0) WHEN niOil1l0l = '1' ELSE wire_nli0liili_dataout; + wire_nli0li01i_w_lg_dataout46755w(0) <= wire_nli0li01i_dataout AND wire_nli0liOOi_w_lg_dataout46754w(0); + wire_nli0li01l_dataout <= wire_nlill0Oll_w_lg_nl0OO1lll45880w(0) OR NOT(nl0iOilOi); + wire_nli0li01O_dataout <= wire_nlill0Oll_w_lg_nl0OO1llO45879w(0) OR NOT(nl0iOilOi); + wire_nli0li0i_dataout <= wire_nlii1lii_dataout WHEN nli1l0ii = '1' ELSE nli1lOii; + wire_nli0li0ii_dataout <= wire_nlill0Oll_w_lg_nl0OO1O1i45875w(0) OR NOT(nl0iOilOi); + wire_nli0li0il_dataout <= wire_nlill0Oll_w_lg_nl0OO1O1l45874w(0) OR NOT(nl0iOilOi); + wire_nli0li0iO_dataout <= wire_nlill0Oll_w_lg_nl0OO1O1O45873w(0) OR NOT(nl0iOilOi); + wire_nli0li0l_dataout <= wire_nlii1lil_dataout WHEN nli1l0ii = '1' ELSE nli1lOil; + wire_nli0li0li_dataout <= wire_nlill0Oll_w_lg_nl0OO1O0i45872w(0) OR NOT(nl0iOilOi); + wire_nli0li0ll_dataout <= wire_nlill0Oll_w_lg_nl0OO1O0l45871w(0) OR NOT(nl0iOilOi); + wire_nli0li0lO_dataout <= wire_nlill0Oll_w_lg_nl0OO1O0O45870w(0) OR NOT(nl0iOilOi); + wire_nli0li0O_dataout <= wire_nlii1liO_dataout WHEN nli1l0ii = '1' ELSE nli1lOiO; + wire_nli0li0Oi_dataout <= wire_nlill0Oll_w_lg_nl0OO1Oii45869w(0) OR NOT(nl0iOilOi); + wire_nli0li0Ol_dataout <= wire_nlill0Oll_w_lg_nl0Ol0Oll45868w(0) OR NOT(nl0iOilOi); + wire_nli0li0OO_dataout <= wire_nlill0Oll_w_lg_nl0OO1iOO45867w(0) OR NOT(nl0iOilOi); + wire_nli0li10i_dataout <= wire_w_lg_niOil1iii45893w(0) OR NOT(niOil1l0l); + wire_nli0li10i_w_lg_dataout47098w(0) <= wire_nli0li10i_dataout AND wire_nli0liO1i_w_lg_dataout47097w(0); + wire_nli0li10l_dataout <= wire_w_lg_niOil1iil45892w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0Ol_dataout; + wire_nli0li10l_w_lg_dataout47066w(0) <= wire_nli0li10l_dataout AND wire_nli0liO1l_w_lg_dataout47065w(0); + wire_nli0li10O_dataout <= wire_w_lg_niOil1iiO45891w(0) WHEN niOil1l0l = '1' ELSE wire_nli0li0OO_dataout; + wire_nli0li10O_w_lg_dataout47034w(0) <= wire_nli0li10O_dataout AND wire_nli0liO1O_w_lg_dataout47033w(0); + wire_nli0li11i_dataout <= wire_w_lg_niOil1i0i45896w(0) OR NOT(niOil1l0l); + wire_nli0li11i_w_lg_dataout47189w(0) <= wire_nli0li11i_dataout AND wire_nli0lilOi_w_lg_dataout47188w(0); + wire_nli0li11l_dataout <= wire_w_lg_niOil1i0l45895w(0) OR NOT(niOil1l0l); + wire_nli0li11l_w_lg_dataout47157w(0) <= wire_nli0li11l_dataout AND wire_nli0lilOl_w_lg_dataout47156w(0); + wire_nli0li11O_dataout <= wire_w_lg_niOil1i0O45894w(0) OR NOT(niOil1l0l); + wire_nli0li11O_w_lg_dataout47128w(0) <= wire_nli0li11O_dataout AND wire_nli0lilOO_w_lg_dataout47127w(0); + wire_nli0li1i_dataout <= wire_nlii1l0i_dataout WHEN nli1l0ii = '1' ELSE nli1lO0i; + wire_nli0li1ii_dataout <= wire_w_lg_niOil1ili45890w(0) WHEN niOil1l0l = '1' ELSE wire_nli0lii1i_dataout; + wire_nli0li1ii_w_lg_dataout47005w(0) <= wire_nli0li1ii_dataout AND wire_nli0liO0i_w_lg_dataout47004w(0); + wire_nli0li1il_dataout <= wire_w_lg_niOil1ill45889w(0) WHEN niOil1l0l = '1' ELSE wire_nli0lii1l_dataout; + wire_nli0li1il_w_lg_dataout46978w(0) <= wire_nli0li1il_dataout AND wire_nli0liO0l_w_lg_dataout46977w(0); + wire_nli0li1iO_dataout <= wire_w_lg_niOil1ilO45888w(0) WHEN niOil1l0l = '1' ELSE wire_nli0lii1O_dataout; + wire_nli0li1iO_w_lg_dataout46948w(0) <= wire_nli0li1iO_dataout AND wire_nli0liO0O_w_lg_dataout46947w(0); + wire_nli0li1l_dataout <= wire_nlii1l0l_dataout WHEN nli1l0ii = '1' ELSE nli1lO0l; + wire_nli0li1li_dataout <= wire_w_lg_niOil1iOi45887w(0) WHEN niOil1l0l = '1' ELSE wire_nli0lii0i_dataout; + wire_nli0li1li_w_lg_dataout46919w(0) <= wire_nli0li1li_dataout AND wire_nli0liOii_w_lg_dataout46918w(0); + wire_nli0li1ll_dataout <= wire_w_lg_niOil1iOl45886w(0) WHEN niOil1l0l = '1' ELSE wire_nli0lii0l_dataout; + wire_nli0li1ll_w_lg_dataout46890w(0) <= wire_nli0li1ll_dataout AND wire_nli0liOil_w_lg_dataout46889w(0); + wire_nli0li1lO_dataout <= wire_w_lg_niOil1iOO45885w(0) WHEN niOil1l0l = '1' ELSE wire_nli0lii0O_dataout; + wire_nli0li1lO_w_lg_dataout46863w(0) <= wire_nli0li1lO_dataout AND wire_nli0liOiO_w_lg_dataout46862w(0); + wire_nli0li1O_dataout <= wire_nlii1l0O_dataout WHEN nli1l0ii = '1' ELSE nli1lO0O; + wire_nli0li1Oi_dataout <= wire_w_lg_niOil1l1i45884w(0) WHEN niOil1l0l = '1' ELSE wire_nli0liiii_dataout; + wire_nli0li1Oi_w_lg_dataout46836w(0) <= wire_nli0li1Oi_dataout AND wire_nli0liOli_w_lg_dataout46835w(0); + wire_nli0li1Ol_dataout <= wire_w_lg_niOil1l1l45883w(0) WHEN niOil1l0l = '1' ELSE wire_nli0liiil_dataout; + wire_nli0li1Ol_w_lg_dataout46809w(0) <= wire_nli0li1Ol_dataout AND wire_nli0liOll_w_lg_dataout46808w(0); + wire_nli0li1OO_dataout <= wire_w_lg_niOil1l1O45882w(0) WHEN niOil1l0l = '1' ELSE wire_nli0liiiO_dataout; + wire_nli0li1OO_w_lg_dataout46782w(0) <= wire_nli0li1OO_dataout AND wire_nli0liOlO_w_lg_dataout46781w(0); + wire_nli0lii0i_dataout <= wire_nlill0Oll_w_lg_nl0OO1l0i45863w(0) OR NOT(nl0iOilOi); + wire_nli0lii0l_dataout <= wire_nlill0Oll_w_lg_nl0OO1l0l45862w(0) OR NOT(nl0iOilOi); + wire_nli0lii0O_dataout <= wire_nlill0Oll_w_lg_nl0OO1l0O45861w(0) OR NOT(nl0iOilOi); + wire_nli0lii1i_dataout <= wire_nlill0Oll_w_lg_nl0OO1l1i45866w(0) OR NOT(nl0iOilOi); + wire_nli0lii1l_dataout <= wire_nlill0Oll_w_lg_nl0OO1l1l45865w(0) OR NOT(nl0iOilOi); + wire_nli0lii1O_dataout <= wire_nlill0Oll_w_lg_nl0OO1l1O45864w(0) OR NOT(nl0iOilOi); + wire_nli0liii_dataout <= wire_nlii1lli_dataout WHEN nli1l0ii = '1' ELSE nli1lOli; + wire_nli0liiii_dataout <= wire_nlill0Oll_w_lg_nl0OO1lii45860w(0) OR NOT(nl0iOilOi); + wire_nli0liiil_dataout <= wire_nlill0Oll_w_lg_nl0OO1lil45859w(0) OR NOT(nl0iOilOi); + wire_nli0liiiO_dataout <= wire_nlill0Oll_w_lg_nl0OO1liO45858w(0) OR NOT(nl0iOilOi); + wire_nli0liil_dataout <= wire_nlii1lll_dataout WHEN nli1l0ii = '1' ELSE nli1lOll; + wire_nli0liili_dataout <= wire_nlill0Oll_w_lg_nl0OO1lli45857w(0) OR NOT(nl0iOilOi); + wire_nli0liilO_dataout <= wire_nl0O110ii_w_lg_dataout45855w(0) WHEN niOil010i = '1' ELSE wire_nli0liOOl_dataout; + wire_nli0liilO_w_lg_dataout47699w(0) <= wire_nli0liilO_dataout AND wire_nli0ll01i_w_lg_dataout47698w(0); + wire_nli0liiO_dataout <= wire_nlii1llO_dataout WHEN nli1l0ii = '1' ELSE nli1lOlO; + wire_nli0liiOi_dataout <= wire_nl0O110il_w_lg_dataout45854w(0) OR NOT(niOil010i); + wire_nli0liiOi_w_lg_dataout47665w(0) <= wire_nli0liiOi_dataout AND wire_nli0ll01l_w_lg_dataout47664w(0); + wire_nli0liiOl_dataout <= wire_nl0O110iO_w_lg_dataout45853w(0) OR NOT(niOil010i); + wire_nli0liiOl_w_lg_dataout47631w(0) <= wire_nli0liiOl_dataout AND wire_nli0ll01O_w_lg_dataout47630w(0); + wire_nli0liiOO_dataout <= wire_nl0O110li_w_lg_dataout45852w(0) OR NOT(niOil010i); + wire_nli0liiOO_w_lg_dataout47596w(0) <= wire_nli0liiOO_dataout AND wire_nli0ll00i_w_lg_dataout47595w(0); + wire_nli0lil0i_dataout <= wire_w_lg_niOil1liO45848w(0) WHEN niOil010i = '1' ELSE wire_nli0ll11O_dataout; + wire_nli0lil0i_w_lg_dataout47467w(0) <= wire_nli0lil0i_dataout AND wire_nli0ll0il_w_lg_dataout47466w(0); + wire_nli0lil0l_dataout <= wire_w_lg_niOil1lli45847w(0) WHEN niOil010i = '1' ELSE wire_nli0ll10i_dataout; + wire_nli0lil0l_w_lg_dataout47435w(0) <= wire_nli0lil0l_dataout AND wire_nli0ll0iO_w_lg_dataout47434w(0); + wire_nli0lil0O_dataout <= wire_w_lg_niOil1lll45846w(0) OR NOT(niOil010i); + wire_nli0lil0O_w_lg_dataout47405w(0) <= wire_nli0lil0O_dataout AND wire_nli0ll0li_w_lg_dataout47404w(0); + wire_nli0lil1i_dataout <= wire_w_lg_niOil1l0O45851w(0) WHEN niOil010i = '1' ELSE wire_nli0liOOO_dataout; + wire_nli0lil1i_w_lg_dataout47562w(0) <= wire_nli0lil1i_dataout AND wire_nli0ll00l_w_lg_dataout47561w(0); + wire_nli0lil1l_dataout <= wire_w_lg_niOil1lii45850w(0) WHEN niOil010i = '1' ELSE wire_nli0ll11i_dataout; + wire_nli0lil1l_w_lg_dataout47531w(0) <= wire_nli0lil1l_dataout AND wire_nli0ll00O_w_lg_dataout47530w(0); + wire_nli0lil1O_dataout <= wire_w_lg_niOil1lil45849w(0) WHEN niOil010i = '1' ELSE wire_nli0ll11l_dataout; + wire_nli0lil1O_w_lg_dataout47499w(0) <= wire_nli0lil1O_dataout AND wire_nli0ll0ii_w_lg_dataout47498w(0); + wire_nli0lili_dataout <= wire_nlii1lOi_dataout WHEN nli1l0ii = '1' ELSE nli1lOOi; + wire_nli0lilii_dataout <= wire_w_lg_niOil1llO45845w(0) OR NOT(niOil010i); + wire_nli0lilii_w_lg_dataout47375w(0) <= wire_nli0lilii_dataout AND wire_nli0ll0ll_w_lg_dataout47374w(0); + wire_nli0lilil_dataout <= wire_w_lg_niOil1lOi45844w(0) OR NOT(niOil010i); + wire_nli0lilil_w_lg_dataout47343w(0) <= wire_nli0lilil_dataout AND wire_nli0ll0lO_w_lg_dataout47342w(0); + wire_nli0liliO_dataout <= wire_w_lg_niOil1lOl45843w(0) WHEN niOil010i = '1' ELSE wire_nli0ll10l_dataout; + wire_nli0liliO_w_lg_dataout47312w(0) <= wire_nli0liliO_dataout AND wire_nli0ll0Oi_w_lg_dataout47311w(0); + wire_nli0lill_dataout <= wire_nlii1lOl_dataout WHEN nli1l0ii = '1' ELSE nli1lOOl; + wire_nli0lilli_dataout <= wire_w_lg_niOil1lOO45842w(0) WHEN niOil010i = '1' ELSE wire_nli0ll10O_dataout; + wire_nli0lilli_w_lg_dataout47282w(0) <= wire_nli0lilli_dataout AND wire_nli0ll0Ol_w_lg_dataout47281w(0); + wire_nli0lilll_dataout <= wire_w_lg_niOil1O1i45841w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1ii_dataout; + wire_nli0lilll_w_lg_dataout47251w(0) <= wire_nli0lilll_dataout AND wire_nli0ll0OO_w_lg_dataout47250w(0); + wire_nli0lillO_dataout <= wire_w_lg_niOil1O1l45840w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1il_dataout; + wire_nli0lillO_w_lg_dataout47220w(0) <= wire_nli0lillO_dataout AND wire_nli0lli1i_w_lg_dataout47219w(0); + wire_nli0lilO_dataout <= wire_nlii1lOO_dataout WHEN nli1l0ii = '1' ELSE nli1lOOO; + wire_nli0lilOi_dataout <= wire_w_lg_niOil1O1O45839w(0) OR NOT(niOil010i); + wire_nli0lilOi_w_lg_dataout47188w(0) <= wire_nli0lilOi_dataout AND wire_nli0lli1l_w_lg_dataout47187w(0); + wire_nli0lilOl_dataout <= wire_w_lg_niOil1O0i45838w(0) OR NOT(niOil010i); + wire_nli0lilOl_w_lg_dataout47156w(0) <= wire_nli0lilOl_dataout AND wire_nli0lli1O_w_lg_dataout47155w(0); + wire_nli0lilOO_dataout <= wire_w_lg_niOil1O0l45837w(0) OR NOT(niOil010i); + wire_nli0lilOO_w_lg_dataout47127w(0) <= wire_nli0lilOO_dataout AND wire_nli0lli0i_w_lg_dataout47126w(0); + wire_nli0liO0i_dataout <= wire_w_lg_niOil1OiO45833w(0) OR NOT(niOil010i); + wire_nli0liO0i_w_lg_dataout47004w(0) <= wire_nli0liO0i_dataout AND wire_nli0lliil_w_lg_dataout47003w(0); + wire_nli0liO0l_dataout <= wire_w_lg_niOil1Oli45832w(0) OR NOT(niOil010i); + wire_nli0liO0l_w_lg_dataout46977w(0) <= wire_nli0liO0l_dataout AND wire_nli0lliiO_w_lg_dataout46976w(0); + wire_nli0liO0O_dataout <= wire_w_lg_niOil1Oll45831w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1iO_dataout; + wire_nli0liO0O_w_lg_dataout46947w(0) <= wire_nli0liO0O_dataout AND wire_nli0llili_w_lg_dataout46946w(0); + wire_nli0liO1i_dataout <= wire_w_lg_niOil1O0O45836w(0) OR NOT(niOil010i); + wire_nli0liO1i_w_lg_dataout47097w(0) <= wire_nli0liO1i_dataout AND wire_nli0lli0l_w_lg_dataout47096w(0); + wire_nli0liO1l_dataout <= wire_w_lg_niOil1Oii45835w(0) OR NOT(niOil010i); + wire_nli0liO1l_w_lg_dataout47065w(0) <= wire_nli0liO1l_dataout AND wire_nli0lli0O_w_lg_dataout47064w(0); + wire_nli0liO1O_dataout <= wire_w_lg_niOil1Oil45834w(0) OR NOT(niOil010i); + wire_nli0liO1O_w_lg_dataout47033w(0) <= wire_nli0liO1O_dataout AND wire_nli0lliii_w_lg_dataout47032w(0); + wire_nli0liOi_dataout <= wire_nlii1O1i_dataout WHEN nli1l0ii = '1' ELSE nli1O11i; + wire_nli0liOii_dataout <= wire_w_lg_niOil1OlO45830w(0) OR NOT(niOil010i); + wire_nli0liOii_w_lg_dataout46918w(0) <= wire_nli0liOii_dataout AND wire_nli0llill_w_lg_dataout46917w(0); + wire_nli0liOil_dataout <= wire_w_lg_niOil1OOi45829w(0) OR NOT(niOil010i); + wire_nli0liOil_w_lg_dataout46889w(0) <= wire_nli0liOil_dataout AND wire_nli0llilO_w_lg_dataout46888w(0); + wire_nli0liOiO_dataout <= wire_w_lg_niOil1OOl45828w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1li_dataout; + wire_nli0liOiO_w_lg_dataout46862w(0) <= wire_nli0liOiO_dataout AND wire_nli0lliOi_w_lg_dataout46861w(0); + wire_nli0liOl_dataout <= wire_nlii1O1l_dataout WHEN nli1l0ii = '1' ELSE nli1O11l; + wire_nli0liOli_dataout <= wire_w_lg_niOil1OOO45827w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1ll_dataout; + wire_nli0liOli_w_lg_dataout46835w(0) <= wire_nli0liOli_dataout AND wire_nli0lliOl_w_lg_dataout46834w(0); + wire_nli0liOll_dataout <= wire_w_lg_niOil011i45826w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1lO_dataout; + wire_nli0liOll_w_lg_dataout46808w(0) <= wire_nli0liOll_dataout AND wire_nli0lliOO_w_lg_dataout46807w(0); + wire_nli0liOlO_dataout <= wire_w_lg_niOil011l45825w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1Oi_dataout; + wire_nli0liOlO_w_lg_dataout46781w(0) <= wire_nli0liOlO_dataout AND wire_nli0lll1i_w_lg_dataout46780w(0); + wire_nli0liOO_dataout <= wire_nlii1O1O_dataout WHEN nli1l0ii = '1' ELSE nli1O11O; + wire_nli0liOOi_dataout <= wire_w_lg_niOil011O45824w(0) WHEN niOil010i = '1' ELSE wire_nli0ll1Ol_dataout; + wire_nli0liOOi_w_lg_dataout46754w(0) <= wire_nli0liOOi_dataout AND wire_nli0lll1l_w_lg_dataout46753w(0); + wire_nli0liOOl_dataout <= wire_w_lg_w_k_bar_range45818w45819w(0) OR NOT(nl0iOillO); + wire_nli0liOOO_dataout <= wire_nlill0Oll_w_lg_nl0OOi0lO45823w(0) OR NOT(nl0iOillO); + wire_nli0ll00i_dataout <= (NOT k_bar(67)) WHEN niOil0i1O = '1' ELSE wire_nli0lll0O_dataout; + wire_nli0ll00i_w_lg_dataout47595w(0) <= wire_nli0ll00i_dataout AND wire_nli0lO11i_w_lg_dataout47594w(0); + wire_nli0ll00l_dataout <= wire_w_lg_niOil010l45798w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lllii_dataout; + wire_nli0ll00l_w_lg_dataout47561w(0) <= wire_nli0ll00l_dataout AND wire_nli0lO11l_w_lg_dataout47560w(0); + wire_nli0ll00O_dataout <= wire_w_lg_niOil010O45797w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lllil_dataout; + wire_nli0ll00O_w_lg_dataout47530w(0) <= wire_nli0ll00O_dataout AND wire_nli0lO11O_w_lg_dataout47529w(0); + wire_nli0ll01i_dataout <= wire_w_lg_w_k_bar_range45805w45806w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lll1O_dataout; + wire_nli0ll01i_w_lg_dataout47698w(0) <= wire_nli0ll01i_dataout AND wire_nli0llOOi_w_lg_dataout47697w(0); + wire_nli0ll01l_dataout <= wire_w_lg_w_k_bar_range45803w45804w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lll0i_dataout; + wire_nli0ll01l_w_lg_dataout47664w(0) <= wire_nli0ll01l_dataout AND wire_nli0llOOl_w_lg_dataout47663w(0); + wire_nli0ll01O_dataout <= (NOT k_bar(66)) WHEN niOil0i1O = '1' ELSE wire_nli0lll0l_dataout; + wire_nli0ll01O_w_lg_dataout47630w(0) <= wire_nli0ll01O_dataout AND wire_nli0llOOO_w_lg_dataout47629w(0); + wire_nli0ll0i_dataout <= wire_nlii1Oii_dataout WHEN nli1l0ii = '1' ELSE nli1O1ii; + wire_nli0ll0ii_dataout <= wire_w_lg_niOil01ii45796w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llliO_dataout; + wire_nli0ll0ii_w_lg_dataout47498w(0) <= wire_nli0ll0ii_dataout AND wire_nli0lO10i_w_lg_dataout47497w(0); + wire_nli0ll0il_dataout <= wire_w_lg_niOil01il45795w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lllli_dataout; + wire_nli0ll0il_w_lg_dataout47466w(0) <= wire_nli0ll0il_dataout AND wire_nli0lO10l_w_lg_dataout47465w(0); + wire_nli0ll0iO_dataout <= wire_w_lg_niOil01iO45794w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lllll_dataout; + wire_nli0ll0iO_w_lg_dataout47434w(0) <= wire_nli0ll0iO_dataout AND wire_nli0lO10O_w_lg_dataout47433w(0); + wire_nli0ll0l_dataout <= wire_nlii1Oil_dataout WHEN nli1l0ii = '1' ELSE nli1O1il; + wire_nli0ll0li_dataout <= wire_w_lg_niOil01li45793w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llllO_dataout; + wire_nli0ll0li_w_lg_dataout47404w(0) <= wire_nli0ll0li_dataout AND wire_nli0lO1ii_w_lg_dataout47403w(0); + wire_nli0ll0ll_dataout <= wire_w_lg_niOil01ll45792w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lllOi_dataout; + wire_nli0ll0ll_w_lg_dataout47374w(0) <= wire_nli0ll0ll_dataout AND wire_nli0lO1il_w_lg_dataout47373w(0); + wire_nli0ll0lO_dataout <= wire_w_lg_niOil01lO45791w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lllOl_dataout; + wire_nli0ll0lO_w_lg_dataout47342w(0) <= wire_nli0ll0lO_dataout AND wire_nli0lO1iO_w_lg_dataout47341w(0); + wire_nli0ll0O_dataout <= wire_nlii1OiO_dataout WHEN nli1l0ii = '1' ELSE nli1O1iO; + wire_nli0ll0Oi_dataout <= wire_w_lg_niOil01Oi45790w(0) WHEN niOil0i1O = '1' ELSE wire_nli0lllOO_dataout; + wire_nli0ll0Oi_w_lg_dataout47311w(0) <= wire_nli0ll0Oi_dataout AND wire_nli0lO1li_w_lg_dataout47310w(0); + wire_nli0ll0Ol_dataout <= wire_w_lg_niOil01Ol45789w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llO1i_dataout; + wire_nli0ll0Ol_w_lg_dataout47281w(0) <= wire_nli0ll0Ol_dataout AND wire_nli0lO1ll_w_lg_dataout47280w(0); + wire_nli0ll0OO_dataout <= wire_w_lg_niOil01OO45788w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llO1l_dataout; + wire_nli0ll0OO_w_lg_dataout47250w(0) <= wire_nli0ll0OO_dataout AND wire_nli0lO1lO_w_lg_dataout47249w(0); + wire_nli0ll10i_dataout <= wire_w_lg_w_k_bar_range45818w45819w(0) OR NOT(nl0iOillO); + wire_nli0ll10l_dataout <= wire_nlill0Oll_w_lg_nl0OOi1ii45817w(0) OR NOT(nl0iOillO); + wire_nli0ll10O_dataout <= wire_nlill0Oll_w_lg_nl0OOi1il45816w(0) OR NOT(nl0iOillO); + wire_nli0ll11i_dataout <= wire_nlill0Oll_w_lg_nl0OOi0Oi45822w(0) OR NOT(nl0iOillO); + wire_nli0ll11l_dataout <= wire_nlill0Oll_w_lg_nl0OOi0Ol45821w(0) OR NOT(nl0iOillO); + wire_nli0ll11O_dataout <= wire_nlill0Oll_w_lg_nl0OOi0OO45820w(0) OR NOT(nl0iOillO); + wire_nli0ll1i_dataout <= wire_nlii1O0i_dataout WHEN nli1l0ii = '1' ELSE nli1O10i; + wire_nli0ll1ii_dataout <= wire_nlill0Oll_w_lg_nl0OOi1iO45815w(0) OR NOT(nl0iOillO); + wire_nli0ll1il_dataout <= wire_nlill0Oll_w_lg_nl0OOi1li45814w(0) OR NOT(nl0iOillO); + wire_nli0ll1iO_dataout <= wire_nlill0Oll_w_lg_nl0OiO1lO45813w(0) OR NOT(nl0iOillO); + wire_nli0ll1l_dataout <= wire_nlii1O0l_dataout WHEN nli1l0ii = '1' ELSE nli1O10l; + wire_nli0ll1li_dataout <= wire_nlill0Oll_w_lg_nl0OiO1ll45812w(0) OR NOT(nl0iOillO); + wire_nli0ll1ll_dataout <= wire_nlill0Oll_w_lg_nl0OiO1li45811w(0) OR NOT(nl0iOillO); + wire_nli0ll1lO_dataout <= wire_nlill0Oll_w_lg_nl0OiO1iO45810w(0) OR NOT(nl0iOillO); + wire_nli0ll1O_dataout <= wire_nlii1O0O_dataout WHEN nli1l0ii = '1' ELSE nli1O10O; + wire_nli0ll1Oi_dataout <= wire_nlill0Oll_w_lg_nl0OiO1il45809w(0) OR NOT(nl0iOillO); + wire_nli0ll1Ol_dataout <= wire_nlill0Oll_w_lg_nl0OiO0li45808w(0) OR NOT(nl0iOillO); + wire_nli0lli0i_dataout <= wire_w_lg_niOil000i45784w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llO0O_dataout; + wire_nli0lli0i_w_lg_dataout47126w(0) <= wire_nli0lli0i_dataout AND wire_nli0lO01i_w_lg_dataout47125w(0); + wire_nli0lli0l_dataout <= wire_w_lg_niOil000l45783w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llOii_dataout; + wire_nli0lli0l_w_lg_dataout47096w(0) <= wire_nli0lli0l_dataout AND wire_nli0lO01l_w_lg_dataout47095w(0); + wire_nli0lli0O_dataout <= wire_w_lg_niOil000O45782w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llOil_dataout; + wire_nli0lli0O_w_lg_dataout47064w(0) <= wire_nli0lli0O_dataout AND wire_nli0lO01O_w_lg_dataout47063w(0); + wire_nli0lli1i_dataout <= wire_w_lg_niOil001i45787w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llO1O_dataout; + wire_nli0lli1i_w_lg_dataout47219w(0) <= wire_nli0lli1i_dataout AND wire_nli0lO1Oi_w_lg_dataout47218w(0); + wire_nli0lli1l_dataout <= wire_w_lg_niOil001l45786w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llO0i_dataout; + wire_nli0lli1l_w_lg_dataout47187w(0) <= wire_nli0lli1l_dataout AND wire_nli0lO1Ol_w_lg_dataout47186w(0); + wire_nli0lli1O_dataout <= wire_w_lg_niOil001O45785w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llO0l_dataout; + wire_nli0lli1O_w_lg_dataout47155w(0) <= wire_nli0lli1O_dataout AND wire_nli0lO1OO_w_lg_dataout47154w(0); + wire_nli0llii_dataout <= wire_nlii1Oli_dataout WHEN nli1l0ii = '1' ELSE nli1O1li; + wire_nli0lliii_dataout <= wire_w_lg_niOil00ii45781w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llOiO_dataout; + wire_nli0lliii_w_lg_dataout47032w(0) <= wire_nli0lliii_dataout AND wire_nli0lO00i_w_lg_dataout47031w(0); + wire_nli0lliil_dataout <= wire_w_lg_niOil00il45780w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llOli_dataout; + wire_nli0lliil_w_lg_dataout47003w(0) <= wire_nli0lliil_dataout AND wire_nli0lO00l_w_lg_dataout47002w(0); + wire_nli0lliiO_dataout <= wire_w_lg_niOil00iO45779w(0) WHEN niOil0i1O = '1' ELSE wire_nli0llOll_dataout; + wire_nli0lliiO_w_lg_dataout46976w(0) <= wire_nli0lliiO_dataout AND wire_nli0lO00O_w_lg_dataout46975w(0); + wire_nli0llil_dataout <= wire_nlii1Oll_dataout WHEN nli1l0ii = '1' ELSE nli1O1ll; + wire_nli0llili_dataout <= wire_w_lg_niOil00li45778w(0) OR NOT(niOil0i1O); + wire_nli0llili_w_lg_dataout46946w(0) <= wire_nli0llili_dataout AND wire_nli0lO0ii_w_lg_dataout46945w(0); + wire_nli0llill_dataout <= wire_w_lg_niOil00ll45777w(0) OR NOT(niOil0i1O); + wire_nli0llill_w_lg_dataout46917w(0) <= wire_nli0llill_dataout AND wire_nli0lO0il_w_lg_dataout46916w(0); + wire_nli0llilO_dataout <= wire_w_lg_niOil00lO45776w(0) OR NOT(niOil0i1O); + wire_nli0llilO_w_lg_dataout46888w(0) <= wire_nli0llilO_dataout AND wire_nli0lO0iO_w_lg_dataout46887w(0); + wire_nli0lliO_dataout <= wire_nlii1OlO_dataout WHEN nli1l0ii = '1' ELSE nli1O1lO; + wire_nli0lliOi_dataout <= wire_w_lg_niOil00Oi45775w(0) OR NOT(niOil0i1O); + wire_nli0lliOi_w_lg_dataout46861w(0) <= wire_nli0lliOi_dataout AND wire_nli0lO0li_w_lg_dataout46860w(0); + wire_nli0lliOl_dataout <= wire_w_lg_niOil00Ol45774w(0) OR NOT(niOil0i1O); + wire_nli0lliOl_w_lg_dataout46834w(0) <= wire_nli0lliOl_dataout AND wire_nli0lO0ll_w_lg_dataout46833w(0); + wire_nli0lliOO_dataout <= wire_w_lg_niOil00OO45773w(0) OR NOT(niOil0i1O); + wire_nli0lliOO_w_lg_dataout46807w(0) <= wire_nli0lliOO_dataout AND wire_nli0lO0lO_w_lg_dataout46806w(0); + wire_nli0lll0i_dataout <= wire_nlill0Oll_w_lg_nl0OOO01O45769w(0) OR NOT(nl0iOilll); + wire_nli0lll0l_dataout <= wire_nlill0Oll_w_lg_nl0OOO00i45768w(0) OR NOT(nl0iOilll); + wire_nli0lll0O_dataout <= wire_nlill0Oll_w_lg_nl0OOO00l45767w(0) OR NOT(nl0iOilll); + wire_nli0lll1i_dataout <= wire_w_lg_niOil0i1i45772w(0) OR NOT(niOil0i1O); + wire_nli0lll1i_w_lg_dataout46780w(0) <= wire_nli0lll1i_dataout AND wire_nli0lO0Oi_w_lg_dataout46779w(0); + wire_nli0lll1l_dataout <= wire_w_lg_niOil0i1l45771w(0) OR NOT(niOil0i1O); + wire_nli0lll1l_w_lg_dataout46753w(0) <= wire_nli0lll1l_dataout AND wire_nli0lO0Ol_w_lg_dataout46752w(0); + wire_nli0lll1O_dataout <= wire_nlill0Oll_w_lg_nl0OOO01l45770w(0) OR NOT(nl0iOilll); + wire_nli0llli_dataout <= wire_nlii1OOi_dataout WHEN nli1l0ii = '1' ELSE nli1O1Oi; + wire_nli0lllii_dataout <= wire_nlill0Oll_w_lg_nl0OOO00O45766w(0) OR NOT(nl0iOilll); + wire_nli0lllil_dataout <= wire_nlill0Oll_w_lg_nl0OOO0ii45765w(0) OR NOT(nl0iOilll); + wire_nli0llliO_dataout <= wire_nlill0Oll_w_lg_nl0OOO0il45764w(0) OR NOT(nl0iOilll); + wire_nli0llll_dataout <= wire_nlii1OOl_dataout WHEN nli1l0ii = '1' ELSE nli1O1Ol; + wire_nli0lllli_dataout <= wire_nlill0Oll_w_lg_nl0OOO0iO45763w(0) OR NOT(nl0iOilll); + wire_nli0lllll_dataout <= wire_nlill0Oll_w_lg_nl0OOO1iO45762w(0) OR NOT(nl0iOilll); + wire_nli0llllO_dataout <= wire_nlill0Oll_w_lg_nl0OOO1li45761w(0) OR NOT(nl0iOilll); + wire_nli0lllO_dataout <= wire_nlii1OOO_dataout WHEN nli1l0ii = '1' ELSE nli1O1OO; + wire_nli0lllOi_dataout <= wire_nlill0Oll_w_lg_nl0OOO1ll45760w(0) OR NOT(nl0iOilll); + wire_nli0lllOl_dataout <= wire_nlill0Oll_w_lg_nl0OOO1lO45759w(0) OR NOT(nl0iOilll); + wire_nli0lllOO_dataout <= wire_nlill0Oll_w_lg_nl0OOO1Oi45758w(0) OR NOT(nl0iOilll); + wire_nli0llO0i_dataout <= wire_nlill0Oll_w_lg_nl0OOii1i45754w(0) OR NOT(nl0iOilll); + wire_nli0llO0l_dataout <= wire_nlill0Oll_w_lg_nl0OOO11l45753w(0) OR NOT(nl0iOilll); + wire_nli0llO0O_dataout <= wire_nlill0Oll_w_lg_nl0OOO11O45752w(0) OR NOT(nl0iOilll); + wire_nli0llO1i_dataout <= wire_nlill0Oll_w_lg_nl0OOO1Ol45757w(0) OR NOT(nl0iOilll); + wire_nli0llO1l_dataout <= wire_nlill0Oll_w_lg_nl0OOO1OO45756w(0) OR NOT(nl0iOilll); + wire_nli0llO1O_dataout <= wire_nlill0Oll_w_lg_nl0OOO01i45755w(0) OR NOT(nl0iOilll); + wire_nli0llOi_dataout <= wire_nlii011i_dataout WHEN nli1l0ii = '1' ELSE nli1O01i; + wire_nli0llOii_dataout <= wire_nlill0Oll_w_lg_nl0OOO10i45751w(0) OR NOT(nl0iOilll); + wire_nli0llOil_dataout <= wire_nlill0Oll_w_lg_nl0OOO10l45750w(0) OR NOT(nl0iOilll); + wire_nli0llOiO_dataout <= wire_nlill0Oll_w_lg_nl0OOO10O45749w(0) OR NOT(nl0iOilll); + wire_nli0llOl_dataout <= wire_nlii011l_dataout WHEN nli1l0ii = '1' ELSE nli1O01l; + wire_nli0llOli_dataout <= wire_nlill0Oll_w_lg_nl0OOO1ii45748w(0) OR NOT(nl0iOilll); + wire_nli0llOll_dataout <= wire_nlill0Oll_w_lg_nl0OOO1il45747w(0) OR NOT(nl0iOilll); + wire_nli0llOO_dataout <= wire_nlii011O_dataout WHEN nli1l0ii = '1' ELSE nli1O01O; + wire_nli0llOOi_dataout <= wire_nl0lliilO_w_lg_dataout45745w(0) OR NOT(nl0iOilli); + wire_nli0llOOi_w_lg_dataout47697w(0) <= wire_nli0llOOi_dataout AND wire_nli0lO0OO_w_lg_dataout47696w(0); + wire_nli0llOOl_dataout <= wire_nl0lliiOi_w_lg_dataout45744w(0) OR NOT(nl0iOilli); + wire_nli0llOOl_w_lg_dataout47663w(0) <= wire_nli0llOOl_dataout AND wire_nli0lOi1i_w_lg_dataout47662w(0); + wire_nli0llOOO_dataout <= wire_nl0lliiOl_w_lg_dataout45743w(0) OR NOT(nl0iOilli); + wire_nli0llOOO_w_lg_dataout47629w(0) <= wire_nli0llOOO_dataout AND wire_nli0lOi1l_w_lg_dataout47628w(0); + wire_nli0lO00i_dataout <= wire_w_lg_niOil0l0O45724w(0) OR NOT(nl0iOilli); + wire_nli0lO00i_w_lg_dataout47031w(0) <= wire_nli0lO00i_dataout AND wire_nli0lOl0O_w_lg_dataout47030w(0); + wire_nli0lO00l_dataout <= wire_w_lg_niOil0lii45723w(0) OR NOT(nl0iOilli); + wire_nli0lO00l_w_lg_dataout47002w(0) <= wire_nli0lO00l_dataout AND wire_nli0lOlii_w_lg_dataout47001w(0); + wire_nli0lO00O_dataout <= wire_w_lg_niOil0lil45722w(0) OR NOT(nl0iOilli); + wire_nli0lO00O_w_lg_dataout46975w(0) <= wire_nli0lO00O_dataout AND wire_nli0lOlil_w_lg_dataout46974w(0); + wire_nli0lO01i_dataout <= wire_w_lg_niOil0l1O45727w(0) OR NOT(nl0iOilli); + wire_nli0lO01i_w_lg_dataout47125w(0) <= wire_nli0lO01i_dataout AND wire_nli0lOl1O_w_lg_dataout47124w(0); + wire_nli0lO01l_dataout <= wire_w_lg_niOil0l0i45726w(0) OR NOT(nl0iOilli); + wire_nli0lO01l_w_lg_dataout47095w(0) <= wire_nli0lO01l_dataout AND wire_nli0lOl0i_w_lg_dataout47094w(0); + wire_nli0lO01O_dataout <= wire_w_lg_niOil0l0l45725w(0) OR NOT(nl0iOilli); + wire_nli0lO01O_w_lg_dataout47063w(0) <= wire_nli0lO01O_dataout AND wire_nli0lOl0l_w_lg_dataout47062w(0); + wire_nli0lO0i_dataout <= wire_nlii01ii_dataout WHEN nli1l0ii = '1' ELSE nli1O0ii; + wire_nli0lO0ii_dataout <= wire_w_lg_niOil0liO45721w(0) OR NOT(nl0iOilli); + wire_nli0lO0ii_w_lg_dataout46945w(0) <= wire_nli0lO0ii_dataout AND wire_nli0lOliO_w_lg_dataout46944w(0); + wire_nli0lO0il_dataout <= wire_w_lg_niOil0lli45720w(0) OR NOT(nl0iOilli); + wire_nli0lO0il_w_lg_dataout46916w(0) <= wire_nli0lO0il_dataout AND wire_nli0lOlli_w_lg_dataout46915w(0); + wire_nli0lO0iO_dataout <= wire_w_lg_niOil0lll45719w(0) OR NOT(nl0iOilli); + wire_nli0lO0iO_w_lg_dataout46887w(0) <= wire_nli0lO0iO_dataout AND wire_nli0lOlll_w_lg_dataout46886w(0); + wire_nli0lO0l_dataout <= wire_nlii01il_dataout WHEN nli1l0ii = '1' ELSE nli1O0il; + wire_nli0lO0li_dataout <= wire_w_lg_niOil0llO45718w(0) OR NOT(nl0iOilli); + wire_nli0lO0li_w_lg_dataout46860w(0) <= wire_nli0lO0li_dataout AND wire_nli0lOllO_w_lg_dataout46859w(0); + wire_nli0lO0ll_dataout <= wire_w_lg_niOil0lOi45717w(0) OR NOT(nl0iOilli); + wire_nli0lO0ll_w_lg_dataout46833w(0) <= wire_nli0lO0ll_dataout AND wire_nli0lOlOi_w_lg_dataout46832w(0); + wire_nli0lO0lO_dataout <= wire_w_lg_niOil0lOl45716w(0) OR NOT(nl0iOilli); + wire_nli0lO0lO_w_lg_dataout46806w(0) <= wire_nli0lO0lO_dataout AND wire_nli0lOlOl_w_lg_dataout46805w(0); + wire_nli0lO0O_dataout <= wire_nlii01iO_dataout WHEN nli1l0ii = '1' ELSE nli1O0iO; + wire_nli0lO0Oi_dataout <= wire_w_lg_niOil0lOO45715w(0) OR NOT(nl0iOilli); + wire_nli0lO0Oi_w_lg_dataout46779w(0) <= wire_nli0lO0Oi_dataout AND wire_nli0lOlOO_w_lg_dataout46778w(0); + wire_nli0lO0Ol_dataout <= wire_w_lg_niOil0O1i45714w(0) OR NOT(nl0iOilli); + wire_nli0lO0Ol_w_lg_dataout46752w(0) <= wire_nli0lO0Ol_dataout AND wire_nli0lOO1i_w_lg_dataout46751w(0); + wire_nli0lO0OO_dataout <= wire_w_lg_w_k_bar_range45712w45713w(0) OR NOT(nl0iOiliO); + wire_nli0lO0OO_w_lg_dataout47696w(0) <= wire_nli0lO0OO_dataout AND wire_nli0lOO1l_w_lg_dataout47695w(0); + wire_nli0lO10i_dataout <= wire_w_lg_niOil0i0O45739w(0) OR NOT(nl0iOilli); + wire_nli0lO10i_w_lg_dataout47497w(0) <= wire_nli0lO10i_dataout AND wire_nli0lOi0O_w_lg_dataout47496w(0); + wire_nli0lO10l_dataout <= wire_w_lg_niOil0iii45738w(0) OR NOT(nl0iOilli); + wire_nli0lO10l_w_lg_dataout47465w(0) <= wire_nli0lO10l_dataout AND wire_nli0lOiii_w_lg_dataout47464w(0); + wire_nli0lO10O_dataout <= wire_w_lg_niOil0iil45737w(0) OR NOT(nl0iOilli); + wire_nli0lO10O_w_lg_dataout47433w(0) <= wire_nli0lO10O_dataout AND wire_nli0lOiil_w_lg_dataout47432w(0); + wire_nli0lO11i_dataout <= wire_nl0lliiOO_w_lg_dataout45742w(0) OR NOT(nl0iOilli); + wire_nli0lO11i_w_lg_dataout47594w(0) <= wire_nli0lO11i_dataout AND wire_nli0lOi1O_w_lg_dataout47593w(0); + wire_nli0lO11l_dataout <= wire_w_lg_niOil0i0i45741w(0) OR NOT(nl0iOilli); + wire_nli0lO11l_w_lg_dataout47560w(0) <= wire_nli0lO11l_dataout AND wire_nli0lOi0i_w_lg_dataout47559w(0); + wire_nli0lO11O_dataout <= wire_w_lg_niOil0i0l45740w(0) OR NOT(nl0iOilli); + wire_nli0lO11O_w_lg_dataout47529w(0) <= wire_nli0lO11O_dataout AND wire_nli0lOi0l_w_lg_dataout47528w(0); + wire_nli0lO1i_dataout <= wire_nlii010i_dataout WHEN nli1l0ii = '1' ELSE nli1O00i; + wire_nli0lO1ii_dataout <= wire_w_lg_niOil0iiO45736w(0) OR NOT(nl0iOilli); + wire_nli0lO1ii_w_lg_dataout47403w(0) <= wire_nli0lO1ii_dataout AND wire_nli0lOiiO_w_lg_dataout47402w(0); + wire_nli0lO1il_dataout <= wire_w_lg_niOil0ili45735w(0) OR NOT(nl0iOilli); + wire_nli0lO1il_w_lg_dataout47373w(0) <= wire_nli0lO1il_dataout AND wire_nli0lOili_w_lg_dataout47372w(0); + wire_nli0lO1iO_dataout <= wire_w_lg_niOil0ill45734w(0) OR NOT(nl0iOilli); + wire_nli0lO1iO_w_lg_dataout47341w(0) <= wire_nli0lO1iO_dataout AND wire_nli0lOill_w_lg_dataout47340w(0); + wire_nli0lO1l_dataout <= wire_nlii010l_dataout WHEN nli1l0ii = '1' ELSE nli1O00l; + wire_nli0lO1li_dataout <= wire_w_lg_niOil0ilO45733w(0) OR NOT(nl0iOilli); + wire_nli0lO1li_w_lg_dataout47310w(0) <= wire_nli0lO1li_dataout AND wire_nli0lOilO_w_lg_dataout47309w(0); + wire_nli0lO1ll_dataout <= wire_w_lg_niOil0iOi45732w(0) OR NOT(nl0iOilli); + wire_nli0lO1ll_w_lg_dataout47280w(0) <= wire_nli0lO1ll_dataout AND wire_nli0lOiOi_w_lg_dataout47279w(0); + wire_nli0lO1lO_dataout <= wire_w_lg_niOil0iOl45731w(0) OR NOT(nl0iOilli); + wire_nli0lO1lO_w_lg_dataout47249w(0) <= wire_nli0lO1lO_dataout AND wire_nli0lOiOl_w_lg_dataout47248w(0); + wire_nli0lO1O_dataout <= wire_nlii010O_dataout WHEN nli1l0ii = '1' ELSE nli1O00O; + wire_nli0lO1Oi_dataout <= wire_w_lg_niOil0iOO45730w(0) OR NOT(nl0iOilli); + wire_nli0lO1Oi_w_lg_dataout47218w(0) <= wire_nli0lO1Oi_dataout AND wire_nli0lOiOO_w_lg_dataout47217w(0); + wire_nli0lO1Ol_dataout <= wire_w_lg_niOil0l1i45729w(0) OR NOT(nl0iOilli); + wire_nli0lO1Ol_w_lg_dataout47186w(0) <= wire_nli0lO1Ol_dataout AND wire_nli0lOl1i_w_lg_dataout47185w(0); + wire_nli0lO1OO_dataout <= wire_w_lg_niOil0l1l45728w(0) OR NOT(nl0iOilli); + wire_nli0lO1OO_w_lg_dataout47154w(0) <= wire_nli0lO1OO_dataout AND wire_nli0lOl1l_w_lg_dataout47153w(0); + wire_nli0lOi0i_dataout <= wire_w_lg_niOil0O1l45705w(0) OR NOT(nl0iOiliO); + wire_nli0lOi0i_w_lg_dataout47559w(0) <= wire_nli0lOi0i_dataout AND wire_nli0lOO0O_w_lg_dataout47558w(0); + wire_nli0lOi0l_dataout <= wire_w_lg_niOil0O1O45704w(0) OR NOT(nl0iOiliO); + wire_nli0lOi0l_w_lg_dataout47528w(0) <= wire_nli0lOi0l_dataout AND wire_nli0lOOii_w_lg_dataout47527w(0); + wire_nli0lOi0O_dataout <= wire_w_lg_niOil0O0i45703w(0) OR NOT(nl0iOiliO); + wire_nli0lOi0O_w_lg_dataout47496w(0) <= wire_nli0lOi0O_dataout AND wire_nli0lOOil_w_lg_dataout47495w(0); + wire_nli0lOi1i_dataout <= wire_w_lg_w_k_bar_range45710w45711w(0) OR NOT(nl0iOiliO); + wire_nli0lOi1i_w_lg_dataout47662w(0) <= wire_nli0lOi1i_dataout AND wire_nli0lOO1O_w_lg_dataout47661w(0); + wire_nli0lOi1l_dataout <= (NOT k_bar(2)) OR NOT(nl0iOiliO); + wire_nli0lOi1l_w_lg_dataout47628w(0) <= wire_nli0lOi1l_dataout AND wire_nli0lOO0i_w_lg_dataout47627w(0); + wire_nli0lOi1O_dataout <= (NOT k_bar(3)) OR NOT(nl0iOiliO); + wire_nli0lOi1O_w_lg_dataout47593w(0) <= wire_nli0lOi1O_dataout AND wire_nli0lOO0l_w_lg_dataout47592w(0); + wire_nli0lOii_dataout <= wire_nlii01li_dataout WHEN nli1l0ii = '1' ELSE nli1O0li; + wire_nli0lOiii_dataout <= wire_w_lg_niOil0O0l45702w(0) OR NOT(nl0iOiliO); + wire_nli0lOiii_w_lg_dataout47464w(0) <= wire_nli0lOiii_dataout AND wire_nli0lOOiO_w_lg_dataout47463w(0); + wire_nli0lOiil_dataout <= wire_w_lg_niOil0O0O45701w(0) OR NOT(nl0iOiliO); + wire_nli0lOiil_w_lg_dataout47432w(0) <= wire_nli0lOiil_dataout AND wire_nli0O110l_w_lg_dataout47431w(0); + wire_nli0lOiiO_dataout <= wire_w_lg_niOil0Oii45700w(0) OR NOT(nl0iOiliO); + wire_nli0lOiiO_w_lg_dataout47402w(0) <= wire_nli0lOiiO_dataout AND wire_nli0O1l0O_w_lg_dataout47401w(0); + wire_nli0lOil_dataout <= wire_nlii01ll_dataout WHEN nli1l0ii = '1' ELSE nli1O0ll; + wire_nli0lOili_dataout <= wire_w_lg_niOil0Oil45699w(0) OR NOT(nl0iOiliO); + wire_nli0lOili_w_lg_dataout47372w(0) <= wire_nli0lOili_dataout AND wire_nli0O11ii_w_lg_dataout47371w(0); + wire_nli0lOill_dataout <= wire_w_lg_niOil0OiO45698w(0) OR NOT(nl0iOiliO); + wire_nli0lOill_w_lg_dataout47340w(0) <= wire_nli0lOill_dataout AND wire_nli0O1lil_w_lg_dataout47339w(0); + wire_nli0lOilO_dataout <= wire_w_lg_niOil0Oli45697w(0) OR NOT(nl0iOiliO); + wire_nli0lOilO_w_lg_dataout47309w(0) <= wire_nli0lOilO_dataout AND wire_nli0O1liO_w_lg_dataout47308w(0); + wire_nli0lOiO_dataout <= wire_nlii01lO_dataout WHEN nli1l0ii = '1' ELSE nli1O0lO; + wire_nli0lOiOi_dataout <= wire_w_lg_niOil0Oll45696w(0) OR NOT(nl0iOiliO); + wire_nli0lOiOi_w_lg_dataout47279w(0) <= wire_nli0lOiOi_dataout AND wire_nli0O1lli_w_lg_dataout47278w(0); + wire_nli0lOiOl_dataout <= wire_w_lg_niOil0OlO45695w(0) OR NOT(nl0iOiliO); + wire_nli0lOiOl_w_lg_dataout47248w(0) <= wire_nli0lOiOl_dataout AND wire_nli0O1lll_w_lg_dataout47247w(0); + wire_nli0lOiOO_dataout <= wire_w_lg_niOil0OOi45694w(0) OR NOT(nl0iOiliO); + wire_nli0lOiOO_w_lg_dataout47217w(0) <= wire_nli0lOiOO_dataout AND wire_nli0O1llO_w_lg_dataout47216w(0); + wire_nli0lOl0i_dataout <= wire_w_lg_niOili11l45690w(0) OR NOT(nl0iOiliO); + wire_nli0lOl0i_w_lg_dataout47094w(0) <= wire_nli0lOl0i_dataout AND wire_nli0O101i_w_lg_dataout47093w(0); + wire_nli0lOl0l_dataout <= wire_w_lg_niOili11O45689w(0) OR NOT(nl0iOiliO); + wire_nli0lOl0l_w_lg_dataout47062w(0) <= wire_nli0lOl0l_dataout AND wire_nli0O101l_w_lg_dataout47061w(0); + wire_nli0lOl0O_dataout <= wire_w_lg_niOili10i45688w(0) OR NOT(nl0iOiliO); + wire_nli0lOl0O_w_lg_dataout47030w(0) <= wire_nli0lOl0O_dataout AND wire_nli0O1O1O_w_lg_dataout47029w(0); + wire_nli0lOl1i_dataout <= wire_w_lg_niOil0OOl45693w(0) OR NOT(nl0iOiliO); + wire_nli0lOl1i_w_lg_dataout47185w(0) <= wire_nli0lOl1i_dataout AND wire_nli0lOOli_w_lg_dataout47184w(0); + wire_nli0lOl1l_dataout <= wire_w_lg_niOil0OOO45692w(0) OR NOT(nl0iOiliO); + wire_nli0lOl1l_w_lg_dataout47153w(0) <= wire_nli0lOl1l_dataout AND wire_nli0O1lOl_w_lg_dataout47152w(0); + wire_nli0lOl1O_dataout <= wire_w_lg_niOili11i45691w(0) OR NOT(nl0iOiliO); + wire_nli0lOl1O_w_lg_dataout47124w(0) <= wire_nli0lOl1O_dataout AND wire_nli0O1lOO_w_lg_dataout47123w(0); + wire_nli0lOli_dataout <= wire_nlii01Oi_dataout WHEN nli1l0ii = '1' ELSE nli1O0Oi; + wire_nli0lOlii_dataout <= wire_w_lg_niOili10l45687w(0) OR NOT(nl0iOiliO); + wire_nli0lOlii_w_lg_dataout47001w(0) <= wire_nli0lOlii_dataout AND wire_nli0O1O0i_w_lg_dataout47000w(0); + wire_nli0lOlil_dataout <= wire_w_lg_niOili10O45686w(0) OR NOT(nl0iOiliO); + wire_nli0lOlil_w_lg_dataout46974w(0) <= wire_nli0lOlil_dataout AND wire_nli0lOOll_w_lg_dataout46973w(0); + wire_nli0lOliO_dataout <= wire_w_lg_niOili1ii45685w(0) OR NOT(nl0iOiliO); + wire_nli0lOliO_w_lg_dataout46944w(0) <= wire_nli0lOliO_dataout AND wire_nli0O100O_w_lg_dataout46943w(0); + wire_nli0lOll_dataout <= wire_nlii01Ol_dataout WHEN nli1l0ii = '1' ELSE nli1O0Ol; + wire_nli0lOlli_dataout <= wire_w_lg_niOili1il45684w(0) OR NOT(nl0iOiliO); + wire_nli0lOlli_w_lg_dataout46915w(0) <= wire_nli0lOlli_dataout AND wire_nli0O1Oii_w_lg_dataout46914w(0); + wire_nli0lOlll_dataout <= wire_w_lg_niOili1iO45683w(0) OR NOT(nl0iOiliO); + wire_nli0lOlll_w_lg_dataout46886w(0) <= wire_nli0lOlll_dataout AND wire_nli0O1Oil_w_lg_dataout46885w(0); + wire_nli0lOllO_dataout <= wire_w_lg_niOili1li45682w(0) OR NOT(nl0iOiliO); + wire_nli0lOllO_w_lg_dataout46859w(0) <= wire_nli0lOllO_dataout AND wire_nli0O10iO_w_lg_dataout46858w(0); + wire_nli0lOlO_dataout <= wire_nlii01OO_dataout WHEN nli1l0ii = '1' ELSE nli1O0OO; + wire_nli0lOlOi_dataout <= wire_w_lg_niOili1ll45681w(0) OR NOT(nl0iOiliO); + wire_nli0lOlOi_w_lg_dataout46832w(0) <= wire_nli0lOlOi_dataout AND wire_nli0O10li_w_lg_dataout46831w(0); + wire_nli0lOlOl_dataout <= wire_w_lg_niOili1lO45680w(0) OR NOT(nl0iOiliO); + wire_nli0lOlOl_w_lg_dataout46805w(0) <= wire_nli0lOlOl_dataout AND wire_nli0O10ll_w_lg_dataout46804w(0); + wire_nli0lOlOO_dataout <= wire_w_lg_niOili1Oi45679w(0) OR NOT(nl0iOiliO); + wire_nli0lOlOO_w_lg_dataout46778w(0) <= wire_nli0lOlOO_dataout AND wire_nli0O10lO_w_lg_dataout46777w(0); + wire_nli0lOO0i_dataout <= wire_nlill0Oll_w_lg_nl0lill1i45675w(0) OR NOT(nl0iOilil); + wire_nli0lOO0i_w_lg_dataout47627w(0) <= wire_nli0lOO0i_dataout AND wire_nli0lOOOl_w_lg_dataout47626w(0); + wire_nli0lOO0l_dataout <= wire_nlill0Oll_w_lg_nl0lill1l45674w(0) OR NOT(nl0iOilil); + wire_nli0lOO0l_w_lg_dataout47592w(0) <= wire_nli0lOO0l_dataout AND wire_nli0O1iOO_w_lg_dataout47591w(0); + wire_nli0lOO0O_dataout <= wire_nlill0Oll_w_lg_nl0lill1O45673w(0) OR NOT(nl0iOilil); + wire_nli0lOO0O_w_lg_dataout47558w(0) <= wire_nli0lOO0O_dataout AND wire_nli0O1l1i_w_lg_dataout47557w(0); + wire_nli0lOO1i_dataout <= wire_w_lg_niOili1Ol45678w(0) OR NOT(nl0iOiliO); + wire_nli0lOO1i_w_lg_dataout46751w(0) <= wire_nli0lOO1i_dataout AND wire_nli0O10Oi_w_lg_dataout46750w(0); + wire_nli0lOO1l_dataout <= wire_nlill0Oll_w_lg_nl0lil0ll45677w(0) OR NOT(nl0iOilil); + wire_nli0lOO1l_w_lg_dataout47695w(0) <= wire_nli0lOO1l_dataout AND wire_nli0lOOlO_w_lg_dataout47694w(0); + wire_nli0lOO1O_dataout <= wire_nlill0Oll_w_lg_nl0liliOO45676w(0) OR NOT(nl0iOilil); + wire_nli0lOO1O_w_lg_dataout47661w(0) <= wire_nli0lOO1O_dataout AND wire_nli0lOOOi_w_lg_dataout47660w(0); + wire_nli0lOOi_dataout <= wire_nlii001i_dataout WHEN nli1l0ii = '1' ELSE nli1Oi1i; + wire_nli0lOOii_dataout <= wire_nlill0Oll_w_lg_nl0lill0i45672w(0) OR NOT(nl0iOilil); + wire_nli0lOOii_w_lg_dataout47527w(0) <= wire_nli0lOOii_dataout AND wire_nli0O1l1l_w_lg_dataout47526w(0); + wire_nli0lOOil_dataout <= wire_nlill0Oll_w_lg_nl0lill0l45671w(0) OR NOT(nl0iOilil); + wire_nli0lOOil_w_lg_dataout47495w(0) <= wire_nli0lOOil_dataout AND wire_nli0O111O_w_lg_dataout47494w(0); + wire_nli0lOOiO_dataout <= wire_nlill0Oll_w_lg_nl0lill0O45670w(0) OR NOT(nl0iOilil); + wire_nli0lOOiO_w_lg_dataout47463w(0) <= wire_nli0lOOiO_dataout AND wire_nli0O1l0i_w_lg_dataout47462w(0); + wire_nli0lOOl_dataout <= wire_nlii001l_dataout WHEN nli1l0ii = '1' ELSE nli1Oi1l; + wire_nli0lOOli_dataout <= niOili1OO OR NOT(nl0iOilil); + wire_nli0lOOli_w_lg_dataout47184w(0) <= wire_nli0lOOli_dataout AND wire_nli0O1lOi_w_lg_dataout47183w(0); + wire_nli0lOOll_dataout <= wire_nlill0Oll_w_lg_nlill1lli45669w(0) OR NOT(nl0iOilil); + wire_nli0lOOll_w_lg_dataout46973w(0) <= wire_nli0lOOll_dataout AND wire_nli0O1O0l_w_lg_dataout46972w(0); + wire_nli0lOOlO_dataout <= (NOT k_conf(32)) OR NOT(nl0iOilii); + wire_nli0lOOlO_w_lg_dataout47694w(0) <= wire_nli0lOOlO_dataout AND wire_nli0O1ilO_w_lg_dataout47693w(0); + wire_nli0lOOO_dataout <= wire_nlii001O_dataout WHEN nli1l0ii = '1' ELSE nli1Oi1O; + wire_nli0lOOOi_dataout <= (NOT k_conf(33)) OR NOT(nl0iOilii); + wire_nli0lOOOi_w_lg_dataout47660w(0) <= wire_nli0lOOOi_dataout AND wire_nli0O1iOi_w_lg_dataout47659w(0); + wire_nli0lOOOl_dataout <= (NOT k_conf(34)) OR NOT(nl0iOilii); + wire_nli0lOOOl_w_lg_dataout47626w(0) <= wire_nli0lOOOl_dataout AND wire_nli0O1iOl_w_lg_dataout47625w(0); + wire_nli0lOOOO_dataout <= (NOT k_conf(35)) OR NOT(nl0iOilii); + wire_nli0O00i_dataout <= wire_nlii0iii_dataout WHEN nli1l0ii = '1' ELSE nli1Olii; + wire_nli0O00l_dataout <= wire_nlii0iil_dataout WHEN nli1l0ii = '1' ELSE nli1Olil; + wire_nli0O00O_dataout <= wire_nlii0iiO_dataout WHEN nli1l0ii = '1' ELSE nli1OliO; + wire_nli0O010i_dataout <= nl0l001Ol OR wire_w_lg_niOili01i45527w(0); + wire_nli0O011i_dataout <= nl0l00l1i AND NOT(wire_w_lg_niOili01i45527w(0)); + wire_nli0O011l_dataout <= nl0l00iOO AND NOT(wire_w_lg_niOili01i45527w(0)); + wire_nli0O011O_dataout <= nl0l00iOl AND NOT(wire_w_lg_niOili01i45527w(0)); + wire_nli0O01i_dataout <= wire_nlii0i0i_dataout WHEN nli1l0ii = '1' ELSE nli1Ol0i; + wire_nli0O01l_dataout <= wire_nlii0i0l_dataout WHEN nli1l0ii = '1' ELSE nli1Ol0l; + wire_nli0O01O_dataout <= wire_nlii0i0O_dataout WHEN nli1l0ii = '1' ELSE nli1Ol0O; + wire_nli0O0ii_dataout <= wire_nlii0ili_dataout WHEN nli1l0ii = '1' ELSE nli1Olli; + wire_nli0O0il_dataout <= wire_nlii0ill_dataout WHEN nli1l0ii = '1' ELSE nli1Olll; + wire_nli0O0iO_dataout <= wire_nlii0ilO_dataout WHEN nli1l0ii = '1' ELSE nli1OllO; + wire_nli0O0li_dataout <= wire_nlii0iOi_dataout WHEN nli1l0ii = '1' ELSE nli1OlOi; + wire_nli0O0ll_dataout <= wire_nlii0iOl_dataout WHEN nli1l0ii = '1' ELSE nli1OlOl; + wire_nli0O0lO_dataout <= wire_nlii0iOO_dataout WHEN nli1l0ii = '1' ELSE nli1OlOO; + wire_nli0O0Oi_dataout <= wire_nlii0l1i_dataout WHEN nli1l0ii = '1' ELSE nli1OO1i; + wire_nli0O0Ol_dataout <= wire_nlii0l1l_dataout WHEN nli1l0ii = '1' ELSE nli1OO1l; + wire_nli0O0OO_dataout <= wire_nlii0l1O_dataout WHEN nli1l0ii = '1' ELSE nli1OO1O; + wire_nli0O100i_dataout <= (NOT k_conf(54)) OR NOT(nl0iOilii); + wire_nli0O100l_dataout <= (NOT k_conf(55)) OR NOT(nl0iOilii); + wire_nli0O100O_dataout <= (NOT k_conf(56)) OR NOT(nl0iOilii); + wire_nli0O100O_w_lg_dataout46943w(0) <= wire_nli0O100O_dataout AND wire_nli0O1O0O_w_lg_dataout46942w(0); + wire_nli0O101i_dataout <= (NOT k_conf(51)) OR NOT(nl0iOilii); + wire_nli0O101i_w_lg_dataout47093w(0) <= wire_nli0O101i_dataout AND wire_nli0O1O1i_w_lg_dataout47092w(0); + wire_nli0O101l_dataout <= (NOT k_conf(52)) OR NOT(nl0iOilii); + wire_nli0O101l_w_lg_dataout47061w(0) <= wire_nli0O101l_dataout AND wire_nlill0Oll_w_lg_w_lg_nl0iOil0O47059w47060w(0); + wire_nli0O101O_dataout <= (NOT k_conf(53)) OR NOT(nl0iOilii); + wire_nli0O10i_dataout <= wire_nlii00ii_dataout WHEN nli1l0ii = '1' ELSE nli1Oiii; + wire_nli0O10ii_dataout <= (NOT k_conf(57)) OR NOT(nl0iOilii); + wire_nli0O10il_dataout <= (NOT k_conf(58)) OR NOT(nl0iOilii); + wire_nli0O10iO_dataout <= (NOT k_conf(59)) OR NOT(nl0iOilii); + wire_nli0O10iO_w_lg_dataout46858w(0) <= wire_nli0O10iO_dataout AND wire_nli0O1OiO_w_lg_dataout46857w(0); + wire_nli0O10l_dataout <= wire_nlii00il_dataout WHEN nli1l0ii = '1' ELSE nli1Oiil; + wire_nli0O10li_dataout <= (NOT k_conf(60)) OR NOT(nl0iOilii); + wire_nli0O10li_w_lg_dataout46831w(0) <= wire_nli0O10li_dataout AND wire_nli0O1Oli_w_lg_dataout46830w(0); + wire_nli0O10ll_dataout <= (NOT k_conf(61)) OR NOT(nl0iOilii); + wire_nli0O10ll_w_lg_dataout46804w(0) <= wire_nli0O10ll_dataout AND wire_nli0O1Oll_w_lg_dataout46803w(0); + wire_nli0O10lO_dataout <= (NOT k_conf(62)) OR NOT(nl0iOilii); + wire_nli0O10lO_w_lg_dataout46777w(0) <= wire_nli0O10lO_dataout AND wire_nli0O1OlO_w_lg_dataout46776w(0); + wire_nli0O10O_dataout <= wire_nlii00iO_dataout WHEN nli1l0ii = '1' ELSE nli1OiiO; + wire_nli0O10Oi_dataout <= (NOT k_conf(63)) OR NOT(nl0iOilii); + wire_nli0O10Oi_w_lg_dataout46750w(0) <= wire_nli0O10Oi_dataout AND wire_nli0O1OOi_w_lg_dataout46749w(0); + wire_nli0O10Ol_dataout <= wire_nlill0Oll_w_lg_nl0l00l1O45604w(0) OR NOT(nl0iOil0O); + wire_nli0O10OO_dataout <= wire_nlill0Oll_w_lg_nl0l00l1l45603w(0) OR NOT(nl0iOil0O); + wire_nli0O110i_dataout <= (NOT k_conf(39)) OR NOT(nl0iOilii); + wire_nli0O110l_dataout <= (NOT k_conf(40)) OR NOT(nl0iOilii); + wire_nli0O110l_w_lg_dataout47431w(0) <= wire_nli0O110l_dataout AND wire_nli0O1l0l_w_lg_dataout47430w(0); + wire_nli0O110O_dataout <= (NOT k_conf(41)) OR NOT(nl0iOilii); + wire_nli0O111i_dataout <= (NOT k_conf(36)) OR NOT(nl0iOilii); + wire_nli0O111l_dataout <= (NOT k_conf(37)) OR NOT(nl0iOilii); + wire_nli0O111O_dataout <= (NOT k_conf(38)) OR NOT(nl0iOilii); + wire_nli0O111O_w_lg_dataout47494w(0) <= wire_nli0O111O_dataout AND wire_nli0O1l1O_w_lg_dataout47493w(0); + wire_nli0O11i_dataout <= wire_nlii000i_dataout WHEN nli1l0ii = '1' ELSE nli1Oi0i; + wire_nli0O11ii_dataout <= (NOT k_conf(42)) OR NOT(nl0iOilii); + wire_nli0O11ii_w_lg_dataout47371w(0) <= wire_nli0O11ii_dataout AND wire_nli0O1lii_w_lg_dataout47370w(0); + wire_nli0O11il_dataout <= (NOT k_conf(43)) OR NOT(nl0iOilii); + wire_nli0O11iO_dataout <= (NOT k_conf(44)) OR NOT(nl0iOilii); + wire_nli0O11l_dataout <= wire_nlii000l_dataout WHEN nli1l0ii = '1' ELSE nli1Oi0l; + wire_nli0O11li_dataout <= (NOT k_conf(45)) OR NOT(nl0iOilii); + wire_nli0O11ll_dataout <= (NOT k_conf(46)) OR NOT(nl0iOilii); + wire_nli0O11lO_dataout <= (NOT k_conf(47)) OR NOT(nl0iOilii); + wire_nli0O11O_dataout <= wire_nlii000O_dataout WHEN nli1l0ii = '1' ELSE nli1Oi0O; + wire_nli0O11Oi_dataout <= (NOT k_conf(48)) OR NOT(nl0iOilii); + wire_nli0O11Ol_dataout <= (NOT k_conf(49)) OR NOT(nl0iOilii); + wire_nli0O11OO_dataout <= (NOT k_conf(50)) OR NOT(nl0iOilii); + wire_nli0O1i0i_dataout <= wire_nlill0Oll_w_lg_nl0l001Ol45599w(0) OR NOT(nl0iOil0O); + wire_nli0O1i0l_dataout <= wire_nlill0Oll_w_lg_nl0l0i00O45598w(0) OR NOT(nl0iOil0O); + wire_nli0O1i0O_dataout <= wire_nlill0Oll_w_lg_nl0l001Oi45597w(0) OR NOT(nl0iOil0O); + wire_nli0O1i1i_dataout <= wire_nlill0Oll_w_lg_nl0l00l1i45602w(0) OR NOT(nl0iOil0O); + wire_nli0O1i1l_dataout <= wire_nlill0Oll_w_lg_nl0l00iOO45601w(0) OR NOT(nl0iOil0O); + wire_nli0O1i1O_dataout <= wire_nlill0Oll_w_lg_nl0l00iOl45600w(0) OR NOT(nl0iOil0O); + wire_nli0O1ii_dataout <= wire_nlii00li_dataout WHEN nli1l0ii = '1' ELSE nli1Oili; + wire_nli0O1iii_dataout <= wire_nlill0Oll_w_lg_nl0l001lO45596w(0) OR NOT(nl0iOil0O); + wire_nli0O1iil_dataout <= wire_nlill0Oll_w_lg_nl0l001ll45595w(0) OR NOT(nl0iOil0O); + wire_nli0O1iiO_dataout <= wire_nlill0Oll_w_lg_nl0l001li45594w(0) OR NOT(nl0iOil0O); + wire_nli0O1il_dataout <= wire_nlii00ll_dataout WHEN nli1l0ii = '1' ELSE nli1Oill; + wire_nli0O1ili_dataout <= wire_nlill0Oll_w_lg_nl0l001iO45593w(0) OR NOT(nl0iOil0O); + wire_nli0O1ill_dataout <= wire_nlill0Oll_w_lg_nl0l000ll45592w(0) OR NOT(nl0iOil0O); + wire_nli0O1ilO_dataout <= (NOT k_conf(0)) OR NOT(nl0iOil0l); + wire_nli0O1ilO_w_lg_dataout47693w(0) <= wire_nli0O1ilO_dataout AND wire_nli0O10Ol_dataout; + wire_nli0O1iO_dataout <= wire_nlii00lO_dataout WHEN nli1l0ii = '1' ELSE nli1OilO; + wire_nli0O1iOi_dataout <= (NOT k_conf(1)) OR NOT(nl0iOil0l); + wire_nli0O1iOi_w_lg_dataout47659w(0) <= wire_nli0O1iOi_dataout AND wire_nli0O10OO_dataout; + wire_nli0O1iOl_dataout <= (NOT k_conf(2)) OR NOT(nl0iOil0l); + wire_nli0O1iOl_w_lg_dataout47625w(0) <= wire_nli0O1iOl_dataout AND wire_nli0O1i1i_dataout; + wire_nli0O1iOO_dataout <= (NOT k_conf(3)) OR NOT(nl0iOil0l); + wire_nli0O1iOO_w_lg_dataout47591w(0) <= wire_nli0O1iOO_dataout AND wire_nli0lOOOO_dataout; + wire_nli0O1l0i_dataout <= (NOT k_conf(7)) OR NOT(nl0iOil0l); + wire_nli0O1l0i_w_lg_dataout47462w(0) <= wire_nli0O1l0i_dataout AND wire_nli0O110i_dataout; + wire_nli0O1l0l_dataout <= (NOT k_conf(8)) OR NOT(nl0iOil0l); + wire_nli0O1l0l_w_lg_dataout47430w(0) <= wire_nli0O1l0l_dataout AND wire_nli0O1i1O_dataout; + wire_nli0O1l0O_dataout <= (NOT k_conf(9)) OR NOT(nl0iOil0l); + wire_nli0O1l0O_w_lg_dataout47401w(0) <= wire_nli0O1l0O_dataout AND wire_nli0O110O_dataout; + wire_nli0O1l1i_dataout <= (NOT k_conf(4)) OR NOT(nl0iOil0l); + wire_nli0O1l1i_w_lg_dataout47557w(0) <= wire_nli0O1l1i_dataout AND wire_nli0O111i_dataout; + wire_nli0O1l1l_dataout <= (NOT k_conf(5)) OR NOT(nl0iOil0l); + wire_nli0O1l1l_w_lg_dataout47526w(0) <= wire_nli0O1l1l_dataout AND wire_nli0O111l_dataout; + wire_nli0O1l1O_dataout <= (NOT k_conf(6)) OR NOT(nl0iOil0l); + wire_nli0O1l1O_w_lg_dataout47493w(0) <= wire_nli0O1l1O_dataout AND wire_nli0O1i1l_dataout; + wire_nli0O1li_dataout <= wire_nlii00Oi_dataout WHEN nli1l0ii = '1' ELSE nli1OiOi; + wire_nli0O1lii_dataout <= (NOT k_conf(10)) OR NOT(nl0iOil0l); + wire_nli0O1lii_w_lg_dataout47370w(0) <= wire_nli0O1lii_dataout AND wire_nli0O1i0i_dataout; + wire_nli0O1lil_dataout <= (NOT k_conf(11)) OR NOT(nl0iOil0l); + wire_nli0O1lil_w_lg_dataout47339w(0) <= wire_nli0O1lil_dataout AND wire_nli0O11il_dataout; + wire_nli0O1liO_dataout <= (NOT k_conf(12)) OR NOT(nl0iOil0l); + wire_nli0O1liO_w_lg_dataout47308w(0) <= wire_nli0O1liO_dataout AND wire_nli0O11iO_dataout; + wire_nli0O1ll_dataout <= wire_nlii00Ol_dataout WHEN nli1l0ii = '1' ELSE nli1OiOl; + wire_nli0O1lli_dataout <= (NOT k_conf(13)) OR NOT(nl0iOil0l); + wire_nli0O1lli_w_lg_dataout47278w(0) <= wire_nli0O1lli_dataout AND wire_nli0O11li_dataout; + wire_nli0O1lll_dataout <= (NOT k_conf(14)) OR NOT(nl0iOil0l); + wire_nli0O1lll_w_lg_dataout47247w(0) <= wire_nli0O1lll_dataout AND wire_nli0O11ll_dataout; + wire_nli0O1llO_dataout <= (NOT k_conf(15)) OR NOT(nl0iOil0l); + wire_nli0O1llO_w_lg_dataout47216w(0) <= wire_nli0O1llO_dataout AND wire_nli0O11lO_dataout; + wire_nli0O1lO_dataout <= wire_nlii00OO_dataout WHEN nli1l0ii = '1' ELSE nli1OiOO; + wire_nli0O1lOi_dataout <= (NOT k_conf(16)) OR NOT(nl0iOil0l); + wire_nli0O1lOi_w_lg_dataout47183w(0) <= wire_nli0O1lOi_dataout AND wire_nli0O11Oi_dataout; + wire_nli0O1lOl_dataout <= (NOT k_conf(17)) OR NOT(nl0iOil0l); + wire_nli0O1lOl_w_lg_dataout47152w(0) <= wire_nli0O1lOl_dataout AND wire_nli0O11Ol_dataout; + wire_nli0O1lOO_dataout <= (NOT k_conf(18)) OR NOT(nl0iOil0l); + wire_nli0O1lOO_w_lg_dataout47123w(0) <= wire_nli0O1lOO_dataout AND wire_nli0O11OO_dataout; + wire_nli0O1O0i_dataout <= (NOT k_conf(22)) OR NOT(nl0iOil0l); + wire_nli0O1O0i_w_lg_dataout47000w(0) <= wire_nli0O1O0i_dataout AND wire_nli0O100i_dataout; + wire_nli0O1O0l_dataout <= (NOT k_conf(23)) OR NOT(nl0iOil0l); + wire_nli0O1O0l_w_lg_dataout46972w(0) <= wire_nli0O1O0l_dataout AND wire_nli0O100l_dataout; + wire_nli0O1O0O_dataout <= (NOT k_conf(24)) OR NOT(nl0iOil0l); + wire_nli0O1O0O_w_lg_dataout46942w(0) <= wire_nli0O1O0O_dataout AND wire_nli0O1i0O_dataout; + wire_nli0O1O1i_dataout <= (NOT k_conf(19)) OR NOT(nl0iOil0l); + wire_nli0O1O1i_w_lg_dataout47092w(0) <= wire_nli0O1O1i_dataout AND wire_nli0O1i0l_dataout; + wire_nli0O1O1l_dataout <= (NOT k_conf(20)) OR NOT(nl0iOil0l); + wire_nli0O1O1O_dataout <= (NOT k_conf(21)) OR NOT(nl0iOil0l); + wire_nli0O1O1O_w_lg_dataout47029w(0) <= wire_nli0O1O1O_dataout AND wire_nli0O101O_dataout; + wire_nli0O1Oi_dataout <= wire_nlii0i1i_dataout WHEN nli1l0ii = '1' ELSE nli1Ol1i; + wire_nli0O1Oii_dataout <= (NOT k_conf(25)) OR NOT(nl0iOil0l); + wire_nli0O1Oii_w_lg_dataout46914w(0) <= wire_nli0O1Oii_dataout AND wire_nli0O10ii_dataout; + wire_nli0O1Oil_dataout <= (NOT k_conf(26)) OR NOT(nl0iOil0l); + wire_nli0O1Oil_w_lg_dataout46885w(0) <= wire_nli0O1Oil_dataout AND wire_nli0O10il_dataout; + wire_nli0O1OiO_dataout <= (NOT k_conf(27)) OR NOT(nl0iOil0l); + wire_nli0O1OiO_w_lg_dataout46857w(0) <= wire_nli0O1OiO_dataout AND wire_nli0O1iii_dataout; + wire_nli0O1Ol_dataout <= wire_nlii0i1l_dataout WHEN nli1l0ii = '1' ELSE nli1Ol1l; + wire_nli0O1Oli_dataout <= (NOT k_conf(28)) OR NOT(nl0iOil0l); + wire_nli0O1Oli_w_lg_dataout46830w(0) <= wire_nli0O1Oli_dataout AND wire_nli0O1iil_dataout; + wire_nli0O1Oll_dataout <= (NOT k_conf(29)) OR NOT(nl0iOil0l); + wire_nli0O1Oll_w_lg_dataout46803w(0) <= wire_nli0O1Oll_dataout AND wire_nli0O1iiO_dataout; + wire_nli0O1OlO_dataout <= (NOT k_conf(30)) OR NOT(nl0iOil0l); + wire_nli0O1OlO_w_lg_dataout46776w(0) <= wire_nli0O1OlO_dataout AND wire_nli0O1ili_dataout; + wire_nli0O1OO_dataout <= wire_nlii0i1O_dataout WHEN nli1l0ii = '1' ELSE nli1Ol1O; + wire_nli0O1OOi_dataout <= (NOT k_conf(31)) OR NOT(nl0iOil0l); + wire_nli0O1OOi_w_lg_dataout46749w(0) <= wire_nli0O1OOi_dataout AND wire_nli0O1ill_dataout; + wire_nli0O1OOl_dataout <= nl0l00l1O AND NOT(wire_w_lg_niOili01i45527w(0)); + wire_nli0O1OOl_w_lg_dataout47765w(0) <= wire_nli0O1OOl_dataout AND wire_w_lg_w_lg_niOiiO0Ol47734w47764w(0); + wire_nli0O1OOl_w_lg_dataout47761w(0) <= wire_nli0O1OOl_dataout AND wire_w_lg_w_lg_niOiiO00O47759w47760w(0); + wire_nli0O1OOO_dataout <= nl0l00l1l AND NOT(wire_w_lg_niOili01i45527w(0)); + wire_nli0O1OOO_w_lg_dataout47749w(0) <= wire_nli0O1OOO_dataout AND wire_w_lg_w_lg_niOiiO0il47745w47748w(0); + wire_nli0O1OOO_w_lg_dataout47737w(0) <= wire_nli0O1OOO_dataout AND wire_w_lg_w_lg_niOiiO0Ol47734w47736w(0); + wire_nli0O1OOO_w_lg_dataout47743w(0) <= wire_nli0O1OOO_dataout AND wire_w_lg_w_lg_niOiiO0lO47741w47742w(0); + wire_nli0Oi0i_dataout <= wire_nlii0lii_dataout WHEN nli1l0ii = '1' ELSE nli1OOii; + wire_nli0Oi0l_dataout <= wire_nlii0lil_dataout WHEN nli1l0ii = '1' ELSE nli1OOil; + wire_nli0Oi0O_dataout <= wire_nlii0liO_dataout WHEN nli1l0ii = '1' ELSE nli1OOiO; + wire_nli0Oi1i_dataout <= wire_nlii0l0i_dataout WHEN nli1l0ii = '1' ELSE nli1OO0i; + wire_nli0Oi1l_dataout <= wire_nlii0l0l_dataout WHEN nli1l0ii = '1' ELSE nli1OO0l; + wire_nli0Oi1O_dataout <= wire_nlii0l0O_dataout WHEN nli1l0ii = '1' ELSE nli1OO0O; + wire_nli0Oii0l_dataout <= wire_nli0Oii0O_dataout AND NOT((wire_w_lg_niOili0ii45092w(0) OR ((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0illl1O_dataout AND nl0l0i0iO)) OR wire_w_lg_niOilllOO44447w(0)))); + wire_nli0Oii0O_dataout <= nli0Oi0lO OR (wire_nlill0Oll_w_lg_nli0Oi0Ol45090w(0) AND niOili0il); + wire_nli0Oii1i_dataout <= wire_nli0Oii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli0Oii1l_dataout <= wire_nli0Oii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli0Oii1O_dataout <= niOili0il AND (niOili0ii AND niOill1ii); + wire_nli0Oiii_dataout <= wire_nlii0lli_dataout WHEN nli1l0ii = '1' ELSE nli1OOli; + wire_nli0Oiil_dataout <= wire_nlii0lll_dataout WHEN nli1l0ii = '1' ELSE nli1OOll; + wire_nli0OiiO_dataout <= wire_nlii0llO_dataout WHEN nli1l0ii = '1' ELSE nli1OOlO; + wire_nli0OiiOl_dataout <= (nli0OiilO AND wire_nlill0Oll_w_lg_nli0Oiill45088w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli0OiiOO_dataout <= nli0OiilO AND NOT(wire_niO01O0O_dataout); + wire_nli0Oil1i_dataout <= (((nli10OiiO AND niOiliOOi) OR (nli10Oiil AND niOiliOlO)) OR (nli10001O AND niOill11l)) AND NOT(wire_niO01O0O_dataout); + wire_nli0Oili_dataout <= wire_nlii0lOi_dataout WHEN nli1l0ii = '1' ELSE nli1OOOi; + wire_nli0Oill_dataout <= wire_nlii0lOl_dataout WHEN nli1l0ii = '1' ELSE nli1OOOl; + wire_nli0OilO_dataout <= wire_nlii0lOO_dataout WHEN nli1l0ii = '1' ELSE nli1OOOO; + wire_nli0OilOi_dataout <= nlii11i0O WHEN niOilii1i = '1' ELSE wire_nli0OilOl_dataout; + wire_nli0OilOl_dataout <= nlii1i1iO AND niOiliiil; + wire_nli0OilOO_dataout <= niOili0OO WHEN niOilllOO = '1' ELSE wire_nli0OiO1i_dataout; + wire_nli0OiO0i_dataout <= nlii11i1l WHEN niOilllOO = '1' ELSE wire_nli0OiO0l_dataout; + wire_nli0OiO0l_dataout <= nlii11i1l WHEN niOili0lO = '1' ELSE wire_nli0OiO0O_dataout; + wire_nli0OiO0O_dataout <= nlii1i10l AND niOili0Oi; + wire_nli0OiO1i_dataout <= nlii110OO WHEN niOililii = '1' ELSE wire_nli0OiO1l_dataout; + wire_nli0OiO1l_dataout <= (nl10ii0ll OR nl10ii0li) AND niOiliiil; + wire_nli0OiOi_dataout <= wire_nlii0O1i_dataout WHEN nli1l0ii = '1' ELSE nli0111i; + wire_nli0OiOiO_dataout <= nlii11i1O WHEN niOilllOO = '1' ELSE wire_nli0OiOli_dataout; + wire_nli0OiOl_dataout <= wire_nlii0O1l_dataout WHEN nli1l0ii = '1' ELSE nli0111l; + wire_nli0OiOli_dataout <= nlii11i1O WHEN niOili0lO = '1' ELSE wire_nli0OiOll_dataout; + wire_nli0OiOll_dataout <= nlii1i10O AND niOili0Oi; + wire_nli0OiOlO_dataout <= nlii1i10O WHEN niOilllOO = '1' ELSE wire_nli0OiOOi_dataout; + wire_nli0OiOO_dataout <= wire_nlii0O1O_dataout WHEN nli1l0ii = '1' ELSE nli0111O; + wire_nli0OiOOi_dataout <= nlii1i10O WHEN (niOiliiii AND niOililii) = '1' ELSE wire_nli0OiOOl_dataout; + wire_nli0OiOOl_dataout <= nlii11i1O AND (niOiliiil AND niOiliiiO); + wire_nli0Ol00i_dataout <= nlii11i1l WHEN niOilii0i = '1' ELSE wire_nli0Ol00l_dataout; + wire_nli0Ol00l_dataout <= nlii1i10l WHEN niOilllOO = '1' ELSE wire_nli0Ol00O_dataout; + wire_nli0Ol00O_dataout <= nlii1i10l AND niOilii0l; + wire_nli0Ol01O_dataout <= nlii11i1l WHEN niOilii0O = '1' ELSE wire_nli0Ol00i_dataout; + wire_nli0Ol0i_dataout <= wire_nlii0Oii_dataout WHEN nli1l0ii = '1' ELSE nli011ii; + wire_nli0Ol0l_dataout <= wire_nlii0Oil_dataout WHEN nli1l0ii = '1' ELSE nli011il; + wire_nli0Ol0li_dataout <= nlii11i1O WHEN niOilii0O = '1' ELSE wire_nli0Ol0ll_dataout; + wire_nli0Ol0ll_dataout <= nlii11i1O WHEN niOilii0i = '1' ELSE wire_nli0Ol0lO_dataout; + wire_nli0Ol0lO_dataout <= nlii1i10O WHEN niOilllOO = '1' ELSE wire_nli0Ol0Oi_dataout; + wire_nli0Ol0O_dataout <= wire_nlii0OiO_dataout WHEN nli1l0ii = '1' ELSE nli011iO; + wire_nli0Ol0Oi_dataout <= nlii1i10O AND niOilii0l; + wire_nli0Ol0Ol_dataout <= nlii1i10O WHEN niOilii0O = '1' ELSE wire_nli0Ol0OO_dataout; + wire_nli0Ol0OO_dataout <= nlii1i10O WHEN (niOiliiil AND niOiliiii) = '1' ELSE wire_nli0Oli1i_dataout; + wire_nli0Ol10i_dataout <= nlii11i0O WHEN niOiliili = '1' ELSE nlii1i1iO; + wire_nli0Ol11l_dataout <= niOiliilO WHEN niOilii1i = '1' ELSE wire_nli0Ol11O_dataout; + wire_nli0Ol11O_dataout <= niOiliill AND niOiliiil; + wire_nli0Ol1i_dataout <= wire_nlii0O0i_dataout WHEN nli1l0ii = '1' ELSE nli0110i; + wire_nli0Ol1il_dataout <= nlii1i10i WHEN niOiliili = '1' ELSE wire_nli0Ol1iO_dataout; + wire_nli0Ol1iO_dataout <= (((nl0OiOl0O AND nlii110OO) OR wire_w_lg_niOili0Ol45064w(0)) AND niOililii) OR (niOilii1i AND ((nl0OiOl0O AND niOili0OO) OR wire_w_lg_niOili0Ol45064w(0))); + wire_nli0Ol1l_dataout <= wire_nlii0O0l_dataout WHEN nli1l0ii = '1' ELSE nli0110l; + wire_nli0Ol1O_dataout <= wire_nlii0O0O_dataout WHEN nli1l0ii = '1' ELSE nli0110O; + wire_nli0Oli0l_dataout <= niOiliilO WHEN niOiliili = '1' ELSE niOiliill; + wire_nli0Oli1i_dataout <= nlii11i1O WHEN niOilllOO = '1' ELSE wire_nli0Oli1l_dataout; + wire_nli0Oli1l_dataout <= nlii11i1O AND (niOiliiiO AND niOililii); + wire_nli0Olii_dataout <= wire_nlii0Oli_dataout WHEN nli1l0ii = '1' ELSE nli011li; + wire_nli0Olil_dataout <= wire_nlii0Oll_dataout WHEN nli1l0ii = '1' ELSE nli011ll; + wire_nli0OliO_dataout <= wire_nlii0OlO_dataout WHEN nli1l0ii = '1' ELSE nli011lO; + wire_nli0Olli_dataout <= wire_nlii0OOi_dataout WHEN nli1l0ii = '1' ELSE nli011Oi; + wire_nli0Olll_dataout <= wire_nlii0OOl_dataout WHEN nli1l0ii = '1' ELSE nli011Ol; + wire_nli0OllO_dataout <= wire_nlii0OOO_dataout WHEN nli1l0ii = '1' ELSE nli011OO; + wire_nli0OlOi_dataout <= wire_nliii11i_dataout WHEN nli1l0ii = '1' ELSE nli0101i; + wire_nli0OlOl_dataout <= wire_nliii11l_dataout WHEN nli1l0ii = '1' ELSE nli0101l; + wire_nli0OlOO_dataout <= wire_nliii11O_dataout WHEN nli1l0ii = '1' ELSE nli0101O; + wire_nli0OO0i_dataout <= wire_nliii1ii_dataout WHEN nli1l0ii = '1' ELSE nli010ii; + wire_nli0OO0l_dataout <= wire_nliii1il_dataout WHEN nli1l0ii = '1' ELSE nli010il; + wire_nli0OO0O_dataout <= wire_nliii1iO_dataout WHEN nli1l0ii = '1' ELSE nli010iO; + wire_nli0OO1i_dataout <= wire_nliii10i_dataout WHEN nli1l0ii = '1' ELSE nli0100i; + wire_nli0OO1l_dataout <= wire_nliii10l_dataout WHEN nli1l0ii = '1' ELSE nli0100l; + wire_nli0OO1O_dataout <= wire_nliii10O_dataout WHEN nli1l0ii = '1' ELSE nli0100O; + wire_nli0OOii_dataout <= wire_nliii1li_dataout WHEN nli1l0ii = '1' ELSE nli010li; + wire_nli0OOil_dataout <= wire_nliii1ll_dataout WHEN nli1l0ii = '1' ELSE nli010ll; + wire_nli0OOiO_dataout <= wire_nliii1lO_dataout WHEN nli1l0ii = '1' ELSE nli010lO; + wire_nli0OOli_dataout <= wire_nliii1Oi_dataout WHEN nli1l0ii = '1' ELSE nli010Oi; + wire_nli0OOlii_dataout <= niOO10lil AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) AND wire_w_lg_niOill0OO44360w(0))); + wire_nli0OOll_dataout <= wire_nliii1Ol_dataout WHEN nli1l0ii = '1' ELSE nli010Ol; + wire_nli0OOlO_dataout <= wire_nliii1OO_dataout WHEN nli1l0ii = '1' ELSE nli010OO; + wire_nli0OOOi_dataout <= wire_nliii01i_dataout WHEN nli1l0ii = '1' ELSE nli01i1i; + wire_nli0OOOl_dataout <= wire_nliii00O_dataout WHEN nli1l0ii = '1' ELSE nli1l00i; + wire_nli0OOOO_dataout <= wire_nlii1iii_dataout WHEN nli1l0ii = '1' ELSE nli1l0Ol; + wire_nli10000i_dataout <= wire_nli10i1lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10000l_dataout <= wire_nli10i1Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10000O_dataout <= wire_nli10i1Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000ii_dataout <= wire_nli10i1OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000il_dataout <= wire_nli10i01i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000iO_dataout <= wire_nli10i01l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000li_dataout <= wire_nli10i01O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000ll_dataout <= wire_nli10i00i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000lO_dataout <= wire_nli10i00l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000Oi_dataout <= wire_nli10i00O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000Ol_dataout <= wire_nli10i0ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1000OO_dataout <= wire_nli10i0il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100i0i_dataout <= wire_nli10i0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100i0l_dataout <= wire_nli10i0Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100i0O_dataout <= wire_nli10il0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100i1i_dataout <= wire_nli10i0iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100i1l_dataout <= wire_nli10i0li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100i1O_dataout <= wire_nli10i0ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100iii_dataout <= wire_nli10il0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100iil_dataout <= wire_nli10ilii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100iiO_dataout <= wire_nli10ilil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100ili_dataout <= wire_nli10iliO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100ill_dataout <= wire_nli10illi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100ilO_dataout <= wire_nli10illl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100iO_dataout <= wire_nli10l1O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nli100iOi_dataout <= wire_nli10illO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100iOl_dataout <= wire_nli10ilOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100iOO_dataout <= wire_nli10ilOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100l0i_dataout <= wire_nli10iO1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100l0l_dataout <= wire_nli10iO0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100l0O_dataout <= wire_nli10iO0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100l1i_dataout <= wire_nli10ilOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100l1l_dataout <= wire_nli10iO1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100l1O_dataout <= wire_nli10iO1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100li_dataout <= niOO1OiiO AND NOT(wire_niO01l0O_dataout); + wire_nli100lii_dataout <= wire_nli10iO0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100lil_dataout <= wire_nli10l1Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100liO_dataout <= wire_nli10l1OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100ll_dataout <= niOO1Oili AND NOT(wire_niO01l0O_dataout); + wire_nli100lli_dataout <= wire_nli10l01i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100lll_dataout <= wire_nli10l01l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100llO_dataout <= wire_nli10l01O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100lO_dataout <= niOO1Ol1i AND NOT(wire_niO01l0O_dataout); + wire_nli100lOi_dataout <= wire_nli10l00i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100lOl_dataout <= wire_nli10l00l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100lOO_dataout <= wire_nli10l00O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100O0i_dataout <= wire_nli10l0li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100O0l_dataout <= wire_nli10l0ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100O0O_dataout <= wire_nli10l0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100O1i_dataout <= wire_nli10l0ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100O1l_dataout <= wire_nli10l0il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100O1O_dataout <= wire_nli10l0iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100Oi_dataout <= nli1001O AND NOT(wire_niO01l0O_dataout); + wire_nli100Oii_dataout <= wire_nli10l0Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100Oil_dataout <= wire_nli10l0Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100OiO_dataout <= wire_nli10l0OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100Ol_dataout <= niOO1Oill AND NOT(wire_niO01l0O_dataout); + wire_nli100Oli_dataout <= wire_nli10llil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100Oll_dataout <= wire_nli10lliO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100OlO_dataout <= wire_nli10llli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100OO_dataout <= niOO1OilO AND NOT(wire_niO01l0O_dataout); + wire_nli100OOi_dataout <= wire_nli10llll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100OOl_dataout <= wire_nli10lllO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli100OOO_dataout <= wire_nli10llOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10100i_dataout <= nli1001Ol AND niOiilO1O; + wire_nli10100i_w_lg_dataout46507w(0) <= NOT wire_nli10100i_dataout; + wire_nli10100l_dataout <= nli1001OO AND niOiilO1O; + wire_nli10100l_w_lg_dataout46506w(0) <= NOT wire_nli10100l_dataout; + wire_nli10100O_dataout <= nli10001i AND niOiilO1O; + wire_nli10100O_w_lg_dataout46505w(0) <= NOT wire_nli10100O_dataout; + wire_nli10101i_dataout <= nli1001ll AND niOiilO1O; + wire_nli10101i_w_lg_dataout46510w(0) <= NOT wire_nli10101i_dataout; + wire_nli10101l_dataout <= nli1001lO AND niOiilO1O; + wire_nli10101l_w_lg_dataout46509w(0) <= NOT wire_nli10101l_dataout; + wire_nli10101O_dataout <= nli1001Oi AND niOiilO1O; + wire_nli10101O_w_lg_dataout46508w(0) <= NOT wire_nli10101O_dataout; + wire_nli1010ii_dataout <= nli10001l AND niOiilO1O; + wire_nli1010ii_w_lg_dataout46504w(0) <= NOT wire_nli1010ii_dataout; + wire_nli10110i_dataout <= k_conf(210) AND NOT(wire_niO01O0O_dataout); + wire_nli10110l_dataout <= k_conf(211) AND NOT(wire_niO01O0O_dataout); + wire_nli10110O_dataout <= nli10011i AND niOiilO1O; + wire_nli10110O_w_lg_dataout46503w(0) <= NOT wire_nli10110O_dataout; + wire_nli10111i_dataout <= k_conf(212) AND NOT(wire_niO01O0O_dataout); + wire_nli10111l_dataout <= k_conf(208) AND NOT(wire_niO01O0O_dataout); + wire_nli10111O_dataout <= k_conf(209) AND NOT(wire_niO01O0O_dataout); + wire_nli1011ii_dataout <= nli10011l AND niOiilO1O; + wire_nli1011ii_w_lg_dataout46519w(0) <= NOT wire_nli1011ii_dataout; + wire_nli1011il_dataout <= nli10011O AND niOiilO1O; + wire_nli1011il_w_lg_dataout46518w(0) <= NOT wire_nli1011il_dataout; + wire_nli1011iO_dataout <= nli10010i AND niOiilO1O; + wire_nli1011iO_w_lg_dataout46517w(0) <= NOT wire_nli1011iO_dataout; + wire_nli1011li_dataout <= nli10010l AND niOiilO1O; + wire_nli1011li_w_lg_dataout46516w(0) <= NOT wire_nli1011li_dataout; + wire_nli1011ll_dataout <= nli10010O AND niOiilO1O; + wire_nli1011ll_w_lg_dataout46515w(0) <= NOT wire_nli1011ll_dataout; + wire_nli1011lO_dataout <= nli1001ii AND niOiilO1O; + wire_nli1011lO_w_lg_dataout46514w(0) <= NOT wire_nli1011lO_dataout; + wire_nli1011Oi_dataout <= nli1001il AND niOiilO1O; + wire_nli1011Oi_w_lg_dataout46513w(0) <= NOT wire_nli1011Oi_dataout; + wire_nli1011Ol_dataout <= nli1001iO AND niOiilO1O; + wire_nli1011Ol_w_lg_dataout46512w(0) <= NOT wire_nli1011Ol_dataout; + wire_nli1011OO_dataout <= nli1001li AND niOiilO1O; + wire_nli1011OO_w_lg_dataout46511w(0) <= NOT wire_nli1011OO_dataout; + wire_nli10i00i_dataout <= nl01l000l WHEN niOiiliOl = '1' ELSE wire_nli10ii0O_dataout; + wire_nli10i00l_dataout <= nl01l000O WHEN niOiiliOl = '1' ELSE wire_nli10iiii_dataout; + wire_nli10i00O_dataout <= nl01l00ii WHEN niOiiliOl = '1' ELSE wire_nli10iiil_dataout; + wire_nli10i01i_dataout <= nl01l001l WHEN niOiiliOl = '1' ELSE wire_nli10ii1O_dataout; + wire_nli10i01l_dataout <= nl01l001O WHEN niOiiliOl = '1' ELSE wire_nli10ii0i_dataout; + wire_nli10i01O_dataout <= nl01l000i WHEN niOiiliOl = '1' ELSE wire_nli10ii0l_dataout; + wire_nli10i0i_dataout <= nli101iO AND NOT(wire_niO01l0O_dataout); + wire_nli10i0ii_dataout <= nl01l00il WHEN niOiiliOl = '1' ELSE wire_nli10iiiO_dataout; + wire_nli10i0il_dataout <= nl01l00iO WHEN niOiiliOl = '1' ELSE wire_nli10iili_dataout; + wire_nli10i0iO_dataout <= nl01l00li WHEN niOiiliOl = '1' ELSE wire_nli10iill_dataout; + wire_nli10i0l_dataout <= nli101li AND NOT(wire_niO01l0O_dataout); + wire_nli10i0li_dataout <= nl01l00ll WHEN niOiiliOl = '1' ELSE wire_nli10iilO_dataout; + wire_nli10i0ll_dataout <= nl01l00lO WHEN niOiiliOl = '1' ELSE wire_nli10iiOi_dataout; + wire_nli10i0lO_dataout <= nl01l00Oi WHEN niOiiliOl = '1' ELSE wire_nli10iiOl_dataout; + wire_nli10i0O_dataout <= nli101ll AND NOT(wire_niO01l0O_dataout); + wire_nli10i0Oi_dataout <= nl01l00Ol WHEN niOiiliOl = '1' ELSE wire_nli10iiOO_dataout; + wire_nli10i0Ol_dataout <= nli11OOOO AND NOT(niOiill0i); + wire_nli10i0OO_dataout <= nli1010ll AND NOT(niOiill0i); + wire_nli10i10i_dataout <= wire_nli10lO1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i10l_dataout <= wire_nli10lO1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i10O_dataout <= wire_nli10lO0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i11i_dataout <= wire_nli10llOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i11l_dataout <= wire_nli10llOO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i11O_dataout <= wire_nli10lO1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i1i_dataout <= niOO1OiOi AND NOT(wire_niO01l0O_dataout); + wire_nli10i1ii_dataout <= wire_nli10lO0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i1il_dataout <= wire_nli10lO0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i1iO_dataout <= wire_nli10lOii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i1l_dataout <= nli101ii AND NOT(wire_niO01l0O_dataout); + wire_nli10i1li_dataout <= wire_nli10lOil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i1ll_dataout <= wire_nli10lOiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10i1lO_dataout <= wire_nli10i0Ol_dataout OR niOiiliOl; + wire_nli10i1O_dataout <= nli101il AND NOT(wire_niO01l0O_dataout); + wire_nli10i1Oi_dataout <= nl01l01Ol WHEN niOiiliOl = '1' ELSE wire_nli10i0OO_dataout; + wire_nli10i1Ol_dataout <= nl01l01OO WHEN niOiiliOl = '1' ELSE wire_nli10ii1i_dataout; + wire_nli10i1OO_dataout <= nl01l001i WHEN niOiiliOl = '1' ELSE wire_nli10ii1l_dataout; + wire_nli10ii0i_dataout <= nli1010OO AND NOT(niOiill0i); + wire_nli10ii0l_dataout <= nli101i1i AND NOT(niOiill0i); + wire_nli10ii0O_dataout <= nli101i1l AND NOT(niOiill0i); + wire_nli10ii1i_dataout <= nli1010lO AND NOT(niOiill0i); + wire_nli10ii1l_dataout <= nli1010Oi AND NOT(niOiill0i); + wire_nli10ii1O_dataout <= nli1010Ol AND NOT(niOiill0i); + wire_nli10iii_dataout <= nli101lO AND NOT(wire_niO01l0O_dataout); + wire_nli10iiii_dataout <= nli101i1O AND NOT(niOiill0i); + wire_nli10iiil_dataout <= nli101i0i AND NOT(niOiill0i); + wire_nli10iiiO_dataout <= nli101i0l AND NOT(niOiill0i); + wire_nli10iil_dataout <= nli101Oi AND NOT(wire_niO01l0O_dataout); + wire_nli10iili_dataout <= nli101i0O AND NOT(niOiill0i); + wire_nli10iill_dataout <= nli101iii AND NOT(niOiill0i); + wire_nli10iilO_dataout <= nli101iil AND NOT(niOiill0i); + wire_nli10iiO_dataout <= nli101Ol AND NOT(wire_niO01l0O_dataout); + wire_nli10iiOi_dataout <= nli101iiO AND NOT(niOiill0i); + wire_nli10iiOl_dataout <= nli101ili AND NOT(niOiill0i); + wire_nli10iiOO_dataout <= nli101ill AND NOT(niOiill0i); + wire_nli10il0l_dataout <= wire_nli10iOii_dataout OR niOiiliOO; + wire_nli10il0O_dataout <= nl01l01Ol WHEN niOiiliOO = '1' ELSE wire_nli10iOil_dataout; + wire_nli10ili_dataout <= nli11lii AND NOT(wire_niO01l0O_dataout); + wire_nli10ilii_dataout <= nl01l01OO WHEN niOiiliOO = '1' ELSE wire_nli10iOiO_dataout; + wire_nli10ilil_dataout <= nl01l001i WHEN niOiiliOO = '1' ELSE wire_nli10iOli_dataout; + wire_nli10iliO_dataout <= nl01l001l WHEN niOiiliOO = '1' ELSE wire_nli10iOll_dataout; + wire_nli10ill_dataout <= nli11l0O AND NOT(wire_niO01l0O_dataout); + wire_nli10illi_dataout <= nl01l001O WHEN niOiiliOO = '1' ELSE wire_nli10iOlO_dataout; + wire_nli10illl_dataout <= nl01l000i WHEN niOiiliOO = '1' ELSE wire_nli10iOOi_dataout; + wire_nli10illO_dataout <= nl01l000l WHEN niOiiliOO = '1' ELSE wire_nli10iOOl_dataout; + wire_nli10ilO_dataout <= nli11l1l AND NOT(wire_niO01l0O_dataout); + wire_nli10ilOi_dataout <= nl01l000O WHEN niOiiliOO = '1' ELSE wire_nli10iOOO_dataout; + wire_nli10ilOl_dataout <= nl01l00ii WHEN niOiiliOO = '1' ELSE wire_nli10l11i_dataout; + wire_nli10ilOO_dataout <= nl01l00il WHEN niOiiliOO = '1' ELSE wire_nli10l11l_dataout; + wire_nli10iO0i_dataout <= nl01l00lO WHEN niOiiliOO = '1' ELSE wire_nli10l10O_dataout; + wire_nli10iO0l_dataout <= nl01l00Oi WHEN niOiiliOO = '1' ELSE wire_nli10l1ii_dataout; + wire_nli10iO0O_dataout <= nl01l00Ol WHEN niOiiliOO = '1' ELSE wire_nli10l1il_dataout; + wire_nli10iO1i_dataout <= nl01l00iO WHEN niOiiliOO = '1' ELSE wire_nli10l11O_dataout; + wire_nli10iO1l_dataout <= nl01l00li WHEN niOiiliOO = '1' ELSE wire_nli10l10i_dataout; + wire_nli10iO1O_dataout <= nl01l00ll WHEN niOiiliOO = '1' ELSE wire_nli10l10l_dataout; + wire_nli10iOi_dataout <= nli1000l AND NOT(wire_niO01l0O_dataout); + wire_nli10iOii_dataout <= nli11OOOO WHEN niOiill0i = '1' ELSE nli101ilO; + wire_nli10iOil_dataout <= nli1010ll WHEN niOiill0i = '1' ELSE nli101iOi; + wire_nli10iOiO_dataout <= nli1010lO WHEN niOiill0i = '1' ELSE nli101iOl; + wire_nli10iOl_dataout <= niOO1Ol0l AND NOT(wire_niO01l0O_dataout); + wire_nli10iOli_dataout <= nli1010Oi WHEN niOiill0i = '1' ELSE nli101iOO; + wire_nli10iOll_dataout <= nli1010Ol WHEN niOiill0i = '1' ELSE nli101l1i; + wire_nli10iOlO_dataout <= nli1010OO WHEN niOiill0i = '1' ELSE nli101l1l; + wire_nli10iOO_dataout <= niOO1Ol1O AND NOT(wire_niO01l0O_dataout); + wire_nli10iOOi_dataout <= nli101i1i WHEN niOiill0i = '1' ELSE nli101l1O; + wire_nli10iOOl_dataout <= nli101i1l WHEN niOiill0i = '1' ELSE nli101l0i; + wire_nli10iOOO_dataout <= nli101i1O WHEN niOiill0i = '1' ELSE nli101l0l; + wire_nli10l00i_dataout <= nl01l001O WHEN niOiill1i = '1' ELSE wire_nli10li0O_dataout; + wire_nli10l00l_dataout <= nl01l000i WHEN niOiill1i = '1' ELSE wire_nli10liii_dataout; + wire_nli10l00O_dataout <= nl01l000l WHEN niOiill1i = '1' ELSE wire_nli10liil_dataout; + wire_nli10l01i_dataout <= nl01l01OO WHEN niOiill1i = '1' ELSE wire_nli10li1O_dataout; + wire_nli10l01l_dataout <= nl01l001i WHEN niOiill1i = '1' ELSE wire_nli10li0i_dataout; + wire_nli10l01O_dataout <= nl01l001l WHEN niOiill1i = '1' ELSE wire_nli10li0l_dataout; + wire_nli10l0ii_dataout <= nl01l000O WHEN niOiill1i = '1' ELSE wire_nli10liiO_dataout; + wire_nli10l0il_dataout <= nl01l00ii WHEN niOiill1i = '1' ELSE wire_nli10lili_dataout; + wire_nli10l0iO_dataout <= nl01l00il WHEN niOiill1i = '1' ELSE wire_nli10lill_dataout; + wire_nli10l0li_dataout <= nl01l00iO WHEN niOiill1i = '1' ELSE wire_nli10lilO_dataout; + wire_nli10l0ll_dataout <= nl01l00li WHEN niOiill1i = '1' ELSE wire_nli10liOi_dataout; + wire_nli10l0lO_dataout <= nl01l00ll WHEN niOiill1i = '1' ELSE wire_nli10liOl_dataout; + wire_nli10l0Oi_dataout <= nl01l00lO WHEN niOiill1i = '1' ELSE wire_nli10liOO_dataout; + wire_nli10l0Ol_dataout <= nl01l00Oi WHEN niOiill1i = '1' ELSE wire_nli10ll1i_dataout; + wire_nli10l0OO_dataout <= nl01l00Ol WHEN niOiill1i = '1' ELSE wire_nli10ll1l_dataout; + wire_nli10l10i_dataout <= nli101iii WHEN niOiill0i = '1' ELSE nli101liO; + wire_nli10l10l_dataout <= nli101iil WHEN niOiill0i = '1' ELSE nli101lli; + wire_nli10l10O_dataout <= nli101iiO WHEN niOiill0i = '1' ELSE nli101lll; + wire_nli10l11i_dataout <= nli101i0i WHEN niOiill0i = '1' ELSE nli101l0O; + wire_nli10l11l_dataout <= nli101i0l WHEN niOiill0i = '1' ELSE nli101lii; + wire_nli10l11O_dataout <= nli101i0O WHEN niOiill0i = '1' ELSE nli101lil; + wire_nli10l1i_dataout <= niOO1OiOO AND NOT(wire_niO01l0O_dataout); + wire_nli10l1ii_dataout <= nli101ili WHEN niOiill0i = '1' ELSE nli101llO; + wire_nli10l1il_dataout <= nli101ill WHEN niOiill0i = '1' ELSE nli101lOi; + wire_nli10l1l_dataout <= niOO1OiOl AND NOT(wire_niO01l0O_dataout); + wire_nli10l1O_dataout <= nli11O0l WHEN ((((NOT (niOO1Oill XOR niOO1OiiO)) AND (NOT (niOO1OilO XOR niOO1Oili))) AND (NOT (niOO1Ol1i XOR niOO1OiOi))) AND (NOT (nli1001O XOR nli101Ol))) = '1' ELSE wire_nli10l0i_o; + wire_nli10l1Ol_dataout <= wire_nli10li1i_dataout OR niOiill1i; + wire_nli10l1OO_dataout <= nl01l01Ol WHEN niOiill1i = '1' ELSE wire_nli10li1l_dataout; + wire_nli10li0i_dataout <= nli101iOO WHEN niOiill0i = '1' ELSE nli101O1l; + wire_nli10li0l_dataout <= nli101l1i WHEN niOiill0i = '1' ELSE nli101O1O; + wire_nli10li0O_dataout <= nli101l1l WHEN niOiill0i = '1' ELSE nli101O0i; + wire_nli10li1i_dataout <= nli101ilO WHEN niOiill0i = '1' ELSE nli101lOl; + wire_nli10li1l_dataout <= nli101iOi WHEN niOiill0i = '1' ELSE nli101lOO; + wire_nli10li1O_dataout <= nli101iOl WHEN niOiill0i = '1' ELSE nli101O1i; + wire_nli10liii_dataout <= nli101l1O WHEN niOiill0i = '1' ELSE nli101O0l; + wire_nli10liil_dataout <= nli101l0i WHEN niOiill0i = '1' ELSE nli101O0O; + wire_nli10liiO_dataout <= nli101l0l WHEN niOiill0i = '1' ELSE nli101Oii; + wire_nli10lili_dataout <= nli101l0O WHEN niOiill0i = '1' ELSE nli101Oil; + wire_nli10lill_dataout <= nli101lii WHEN niOiill0i = '1' ELSE nli101OiO; + wire_nli10lilO_dataout <= nli101lil WHEN niOiill0i = '1' ELSE nli101Oli; + wire_nli10liOi_dataout <= nli101liO WHEN niOiill0i = '1' ELSE nli101Oll; + wire_nli10liOl_dataout <= nli101lli WHEN niOiill0i = '1' ELSE nli101OlO; + wire_nli10liOO_dataout <= nli101lll WHEN niOiill0i = '1' ELSE nli101OOi; + wire_nli10ll1i_dataout <= nli101llO WHEN niOiill0i = '1' ELSE nli101OOl; + wire_nli10ll1l_dataout <= nli101lOi WHEN niOiill0i = '1' ELSE nli101OOO; + wire_nli10llil_dataout <= wire_nli10lOli_dataout OR niOiill0l; + wire_nli10lliO_dataout <= nl01l01Ol WHEN niOiill0l = '1' ELSE wire_nli10lOll_dataout; + wire_nli10llli_dataout <= nl01l01OO WHEN niOiill0l = '1' ELSE wire_nli10lOlO_dataout; + wire_nli10llll_dataout <= nl01l001i WHEN niOiill0l = '1' ELSE wire_nli10lOOi_dataout; + wire_nli10lllO_dataout <= nl01l001l WHEN niOiill0l = '1' ELSE wire_nli10lOOl_dataout; + wire_nli10llOi_dataout <= nl01l001O WHEN niOiill0l = '1' ELSE wire_nli10lOOO_dataout; + wire_nli10llOl_dataout <= nl01l000i WHEN niOiill0l = '1' ELSE wire_nli10O11i_dataout; + wire_nli10llOO_dataout <= nl01l000l WHEN niOiill0l = '1' ELSE wire_nli10O11l_dataout; + wire_nli10lO0i_dataout <= nl01l00iO WHEN niOiill0l = '1' ELSE wire_nli10O10O_dataout; + wire_nli10lO0l_dataout <= nl01l00li WHEN niOiill0l = '1' ELSE wire_nli10O1ii_dataout; + wire_nli10lO0O_dataout <= nl01l00ll WHEN niOiill0l = '1' ELSE wire_nli10O1il_dataout; + wire_nli10lO1i_dataout <= nl01l000O WHEN niOiill0l = '1' ELSE wire_nli10O11O_dataout; + wire_nli10lO1l_dataout <= nl01l00ii WHEN niOiill0l = '1' ELSE wire_nli10O10i_dataout; + wire_nli10lO1O_dataout <= nl01l00il WHEN niOiill0l = '1' ELSE wire_nli10O10l_dataout; + wire_nli10lOii_dataout <= nl01l00lO WHEN niOiill0l = '1' ELSE wire_nli10O1iO_dataout; + wire_nli10lOil_dataout <= nl01l00Oi WHEN niOiill0l = '1' ELSE wire_nli10O1li_dataout; + wire_nli10lOiO_dataout <= nl01l00Ol WHEN niOiill0l = '1' ELSE wire_nli10O1ll_dataout; + wire_nli10lOli_dataout <= wire_nli10O1lO_dataout OR niOiill1O; + wire_nli10lOll_dataout <= nli101lOO WHEN niOiill1O = '1' ELSE wire_nli10O1Oi_dataout; + wire_nli10lOlO_dataout <= nli101O1i WHEN niOiill1O = '1' ELSE wire_nli10O1Ol_dataout; + wire_nli10lOOi_dataout <= nli101O1l WHEN niOiill1O = '1' ELSE wire_nli10O1OO_dataout; + wire_nli10lOOl_dataout <= nli101O1O WHEN niOiill1O = '1' ELSE wire_nli10O01i_dataout; + wire_nli10lOOO_dataout <= nli101O0i WHEN niOiill1O = '1' ELSE wire_nli10O01l_dataout; + wire_nli10O00i_dataout <= nli1001il AND NOT(niOiill1l); + wire_nli10O00l_dataout <= nli1001iO AND NOT(niOiill1l); + wire_nli10O00O_dataout <= nli1001li AND NOT(niOiill1l); + wire_nli10O01i_dataout <= nli10010l AND NOT(niOiill1l); + wire_nli10O01l_dataout <= nli10010O AND NOT(niOiill1l); + wire_nli10O01O_dataout <= nli1001ii AND NOT(niOiill1l); + wire_nli10O0ii_dataout <= nli1001ll AND NOT(niOiill1l); + wire_nli10O0il_dataout <= nli1001lO AND NOT(niOiill1l); + wire_nli10O0iO_dataout <= nli1001Oi AND NOT(niOiill1l); + wire_nli10O0li_dataout <= nli1001Ol AND NOT(niOiill1l); + wire_nli10O0ll_dataout <= nli1001OO AND NOT(niOiill1l); + wire_nli10O0lO_dataout <= nli10001i AND NOT(niOiill1l); + wire_nli10O0Oi_dataout <= nli10001l AND NOT(niOiill1l); + wire_nli10O10i_dataout <= nli101Oil WHEN niOiill1O = '1' ELSE wire_nli10O00O_dataout; + wire_nli10O10l_dataout <= nli101OiO WHEN niOiill1O = '1' ELSE wire_nli10O0ii_dataout; + wire_nli10O10O_dataout <= nli101Oli WHEN niOiill1O = '1' ELSE wire_nli10O0il_dataout; + wire_nli10O11i_dataout <= nli101O0l WHEN niOiill1O = '1' ELSE wire_nli10O01O_dataout; + wire_nli10O11l_dataout <= nli101O0O WHEN niOiill1O = '1' ELSE wire_nli10O00i_dataout; + wire_nli10O11O_dataout <= nli101Oii WHEN niOiill1O = '1' ELSE wire_nli10O00l_dataout; + wire_nli10O1ii_dataout <= nli101Oll WHEN niOiill1O = '1' ELSE wire_nli10O0iO_dataout; + wire_nli10O1il_dataout <= nli101OlO WHEN niOiill1O = '1' ELSE wire_nli10O0li_dataout; + wire_nli10O1iO_dataout <= nli101OOi WHEN niOiill1O = '1' ELSE wire_nli10O0ll_dataout; + wire_nli10O1li_dataout <= nli101OOl WHEN niOiill1O = '1' ELSE wire_nli10O0lO_dataout; + wire_nli10O1ll_dataout <= nli101OOO WHEN niOiill1O = '1' ELSE wire_nli10O0Oi_dataout; + wire_nli10O1lO_dataout <= nli10011i AND NOT(niOiill1l); + wire_nli10O1Oi_dataout <= nli10011l AND NOT(niOiill1l); + wire_nli10O1Ol_dataout <= nli10011O AND NOT(niOiill1l); + wire_nli10O1OO_dataout <= nli10010i AND NOT(niOiill1l); + wire_nli10OilO_dataout <= wire_nli10Ol1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OiOi_dataout <= wire_nli10Ol1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OiOl_dataout <= wire_nli10Ol1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OiOO_dataout <= wire_nli10Ol0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10Ol0i_dataout <= wire_nl0l1lO0l_dataout WHEN niOiillii = '1' ELSE nli10Oili; + wire_nli10Ol1i_dataout <= wire_nl0l1lO1l_dataout WHEN niOiillii = '1' ELSE nli10001O; + wire_nli10Ol1l_dataout <= wire_nl0l1lO1O_dataout WHEN niOiillii = '1' ELSE nli10Oiil; + wire_nli10Ol1O_dataout <= wire_nl0l1lO0i_dataout WHEN niOiillii = '1' ELSE nli10OiiO; + wire_nli10OO0O_dataout <= wire_nli1i111O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOii_dataout <= wire_nli1i110i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOil_dataout <= wire_nli1i110l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOiO_dataout <= wire_nli1i110O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOli_dataout <= wire_nli1i11il_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOll_dataout <= wire_nli1i11ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOlO_dataout <= wire_nli1i11iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOOi_dataout <= wire_nli1i11lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOOl_dataout <= wire_nli1i11li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli10OOOO_dataout <= wire_nli1i11ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1100li_dataout <= wire_nli110l1l_dataout AND NOT(niOiil0ii); + wire_nli1100ll_dataout <= wire_nli110l1O_dataout AND NOT(niOiil0ii); + wire_nli1100lO_dataout <= wire_nli110l0i_dataout AND NOT(niOiil0ii); + wire_nli1100Oi_dataout <= wire_nli110l0l_dataout AND NOT(niOiil0ii); + wire_nli1100Ol_dataout <= wire_nli110l0O_dataout AND NOT(niOiil0ii); + wire_nli1100OO_dataout <= wire_nli110lii_dataout AND NOT(niOiil0ii); + wire_nli1101i_dataout <= wire_nlliOl1ii_o(4) WHEN wire_w_lg_niOO1Oiil6359w(0) = '1' ELSE nli1111O; + wire_nli1101l_dataout <= wire_nlliOl1ii_o(5) WHEN wire_w_lg_niOO1Oiil6359w(0) = '1' ELSE nli1110i; + wire_nli110i0i_dataout <= wire_nli110lll_dataout AND NOT(niOiil0ii); + wire_nli110i0l_dataout <= wire_nli110llO_dataout AND NOT(niOiil0ii); + wire_nli110i0O_dataout <= wire_nli110lOi_dataout AND NOT(niOiil0ii); + wire_nli110i1i_dataout <= wire_nli110lil_dataout AND NOT(niOiil0ii); + wire_nli110i1l_dataout <= wire_nli110liO_dataout AND NOT(niOiil0ii); + wire_nli110i1O_dataout <= wire_nli110lli_dataout AND NOT(niOiil0ii); + wire_nli110iii_dataout <= wire_nli110lOl_dataout AND NOT(niOiil0ii); + wire_nli110iil_dataout <= wire_nli110lOO_dataout AND NOT(niOiil0ii); + wire_nli110iiO_dataout <= wire_nli110O1i_dataout AND NOT(niOiil0ii); + wire_nli110ili_dataout <= wire_nli110O1l_dataout AND NOT(niOiil0ii); + wire_nli110ill_dataout <= wire_nli110O1O_dataout AND NOT(niOiil0ii); + wire_nli110ilO_dataout <= wire_nli110O0i_dataout AND NOT(niOiil0ii); + wire_nli110iOi_dataout <= wire_nli110O0l_dataout AND NOT(niOiil0ii); + wire_nli110iOl_dataout <= wire_nli110O0O_dataout AND NOT(niOiil0ii); + wire_nli110iOO_dataout <= wire_nli110Oii_dataout AND NOT(niOiil0ii); + wire_nli110l0i_dataout <= wire_nli11i1Ol_dataout WHEN niOiil00O = '1' ELSE nli11010l; + wire_nli110l0l_dataout <= wire_nli11i1Oi_dataout WHEN niOiil00O = '1' ELSE nli11010O; + wire_nli110l0O_dataout <= wire_nli11i1lO_dataout WHEN niOiil00O = '1' ELSE nli1101ii; + wire_nli110l1i_dataout <= wire_nli110Oil_dataout AND NOT(niOiil0ii); + wire_nli110l1l_dataout <= wire_nli110OiO_dataout WHEN niOiil00O = '1' ELSE nli111i1l; + wire_nli110l1O_dataout <= wire_nli11i1OO_dataout WHEN niOiil00O = '1' ELSE nli11010i; + wire_nli110lii_dataout <= wire_nli11i1ll_dataout WHEN niOiil00O = '1' ELSE nli1101il; + wire_nli110lil_dataout <= wire_nli11i1li_dataout WHEN niOiil00O = '1' ELSE nli1101iO; + wire_nli110liO_dataout <= wire_nli11i1iO_dataout WHEN niOiil00O = '1' ELSE nli1101li; + wire_nli110lli_dataout <= wire_nli11i1il_dataout WHEN niOiil00O = '1' ELSE nli1101ll; + wire_nli110lll_dataout <= wire_nli11i1ii_dataout WHEN niOiil00O = '1' ELSE nli1101lO; + wire_nli110llO_dataout <= wire_nli11i10O_dataout WHEN niOiil00O = '1' ELSE nli1101Oi; + wire_nli110lOi_dataout <= wire_nli11i10l_dataout WHEN niOiil00O = '1' ELSE nli1101Ol; + wire_nli110lOl_dataout <= wire_nli11i10i_dataout WHEN niOiil00O = '1' ELSE nli1101OO; + wire_nli110lOO_dataout <= wire_nli11i11O_dataout WHEN niOiil00O = '1' ELSE nli11001i; + wire_nli110O0i_dataout <= wire_nli110OOl_dataout WHEN niOiil00O = '1' ELSE nli11000l; + wire_nli110O0l_dataout <= wire_nli110OOi_dataout WHEN niOiil00O = '1' ELSE nli11000O; + wire_nli110O0O_dataout <= wire_nli110OlO_dataout WHEN niOiil00O = '1' ELSE nli1100ii; + wire_nli110O1i_dataout <= wire_nli11i11l_dataout WHEN niOiil00O = '1' ELSE nli11001l; + wire_nli110O1l_dataout <= wire_nli11i11i_dataout WHEN niOiil00O = '1' ELSE nli11001O; + wire_nli110O1O_dataout <= wire_nli110OOO_dataout WHEN niOiil00O = '1' ELSE nli11000i; + wire_nli110Oii_dataout <= wire_nli110Oll_dataout WHEN niOiil00O = '1' ELSE nli1100il; + wire_nli110Oil_dataout <= wire_nli110Oli_dataout WHEN niOiil00O = '1' ELSE nli1100iO; + wire_nli110OiO_dataout <= wire_nl0l1lO1l_dataout WHEN nl0iOil1i = '1' ELSE nli111i1l; + wire_nli110Oli_dataout <= wire_nl0l1O01O_dataout WHEN nl0iOil0i = '1' ELSE nli1100iO; + wire_nli110Oll_dataout <= wire_nl0l1O01l_dataout WHEN nl0iOil0i = '1' ELSE nli1100il; + wire_nli110OlO_dataout <= wire_nl0l1O01i_dataout WHEN nl0iOil0i = '1' ELSE nli1100ii; + wire_nli110OOi_dataout <= wire_nl0l1O1OO_dataout WHEN nl0iOil0i = '1' ELSE nli11000O; + wire_nli110OOl_dataout <= wire_nl0l1O1Ol_dataout WHEN nl0iOil0i = '1' ELSE nli11000l; + wire_nli110OOO_dataout <= wire_nl0l1O1Oi_dataout WHEN nl0iOil0i = '1' ELSE nli11000i; + wire_nli1110l_dataout <= wire_nli111ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1110O_dataout <= wire_nli111Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli11111i_dataout <= wire_nl0l1lOiO_dataout WHEN niOiil00i = '1' ELSE nl0OOO0iO; + wire_nli111ii_dataout <= wire_nli111Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli111il_dataout <= wire_nli111OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli111iO_dataout <= wire_nli1101i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli111li_dataout <= wire_nli1101l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli111ll_dataout <= wire_nl1000i_w_lg_nl0OOOlO6364w(0) WHEN (wire_w_lg_niOO1Oiil6359w(0) AND wire_w_lg_niOO1Oiii6365w(0)) = '1' ELSE nl0OOOlO; + wire_nli111Oi_dataout <= wire_nlliOl1ii_o(1) WHEN wire_w_lg_niOO1Oiil6359w(0) = '1' ELSE nl0OOOOO; + wire_nli111Ol_dataout <= wire_nlliOl1ii_o(2) WHEN wire_w_lg_niOO1Oiil6359w(0) = '1' ELSE nli1111i; + wire_nli111OO_dataout <= wire_nlliOl1ii_o(3) WHEN wire_w_lg_niOO1Oiil6359w(0) = '1' ELSE nli1111l; + wire_nli11i10i_dataout <= wire_nl0l1O1iO_dataout WHEN nl0iOil1O = '1' ELSE nli1101OO; + wire_nli11i10l_dataout <= wire_nl0l1O1il_dataout WHEN nl0iOil1O = '1' ELSE nli1101Ol; + wire_nli11i10O_dataout <= wire_nl0l1O1ii_dataout WHEN nl0iOil1O = '1' ELSE nli1101Oi; + wire_nli11i11i_dataout <= wire_nl0l1O1lO_dataout WHEN nl0iOil0i = '1' ELSE nli11001O; + wire_nli11i11l_dataout <= wire_nl0l1O1ll_dataout WHEN nl0iOil0i = '1' ELSE nli11001l; + wire_nli11i11O_dataout <= wire_nl0l1O1li_dataout WHEN nl0iOil1O = '1' ELSE nli11001i; + wire_nli11i1ii_dataout <= wire_nl0l1O10O_dataout WHEN nl0iOil1O = '1' ELSE nli1101lO; + wire_nli11i1il_dataout <= wire_nl0l1O10l_dataout WHEN nl0iOil1O = '1' ELSE nli1101ll; + wire_nli11i1iO_dataout <= wire_nl0l1O10i_dataout WHEN nl0iOil1O = '1' ELSE nli1101li; + wire_nli11i1li_dataout <= wire_nl0l1O11O_dataout WHEN nl0iOil1O = '1' ELSE nli1101iO; + wire_nli11i1ll_dataout <= wire_nl0l1O11l_dataout WHEN nl0iOil1l = '1' ELSE nli1101il; + wire_nli11i1lO_dataout <= wire_nl0l1O11i_dataout WHEN nl0iOil1l = '1' ELSE nli1101ii; + wire_nli11i1Oi_dataout <= wire_nl0l1lOOO_dataout WHEN nl0iOil1l = '1' ELSE nli11010O; + wire_nli11i1Ol_dataout <= wire_nl0l1lOOl_dataout WHEN nl0iOil1l = '1' ELSE nli11010l; + wire_nli11i1OO_dataout <= wire_nl0l1lOOi_dataout WHEN nl0iOil1l = '1' ELSE nli11010i; + wire_nli11iilO_dataout <= wire_nli11iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli11iiOi_dataout <= wire_nli11iiOl_dataout OR (wire_nlill0Oll_w_lg_nl0iOil1i48208w(0) AND wire_w_lg_w_lg_niOiil0Ol48209w48210w(0)); + wire_nli11iiOl_dataout <= nli11iiii AND NOT((wire_nliliiO1i_w_lg_w_lg_w_lg_dataout48201w48203w48204w(0) AND wire_nliliilOi_w_lg_dataout43982w(0))); + wire_nli11ilOl_dataout <= wire_nli11iO0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11ilOO_dataout <= wire_nli11iO0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11iO0i_dataout <= wire_nli11iOli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11iO0l_dataout <= wire_nl0l1lOll_dataout WHEN niOiili0l = '1' ELSE nli11iill; + wire_nli11iO0O_dataout <= wire_nl0l1lOlO_dataout WHEN niOiili0l = '1' ELSE nli11ilil; + wire_nli11iO1i_dataout <= wire_nli11iOii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11iO1l_dataout <= wire_nli11iOil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11iO1O_dataout <= wire_nli11iOiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11iOii_dataout <= wire_nl0l1lOOi_dataout WHEN niOiili0l = '1' ELSE nli11iliO; + wire_nli11iOil_dataout <= wire_nl0l1lOOl_dataout WHEN niOiili0l = '1' ELSE nli11illi; + wire_nli11iOiO_dataout <= wire_nli11iOll_o WHEN niOiili1l = '1' ELSE nli11illl; + wire_nli11iOli_dataout <= wire_nli11iOlO_o WHEN niOiili1l = '1' ELSE nli11illO; + wire_nli11iOOl_dataout <= wire_nl0l1lO1l_dataout WHEN niOiil0lO = '1' ELSE nli11illl; + wire_nli11iOOO_dataout <= wire_nl0l1lO1O_dataout WHEN niOiil0lO = '1' ELSE nli11illO; + wire_nli11l01O_dataout <= wire_nl0l1lOli_dataout WHEN niOiili0l = '1' ELSE nli11l1ll; + wire_nli11l0lO_dataout <= niOOOlil WHEN niOiiOiii = '1' ELSE nli10OlOO; + wire_nli11l0Oi_dataout <= wire_nli11l0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11l10i_dataout <= wire_nli11l10O_dataout AND NOT(niOiili1i); + wire_nli11l10l_dataout <= wire_nli11l1ii_dataout AND NOT(niOiili1i); + wire_nli11l10O_dataout <= nli11illl OR niOiil0OO; + wire_nli11l1ii_dataout <= nli11illO OR niOiil0OO; + wire_nli11l1il_dataout <= nli11illl AND NOT(niOiili1i); + wire_nli11l1iO_dataout <= nli11illO AND NOT(niOiili1i); + wire_nli11l1Oi_dataout <= wire_nli11l1Ol_dataout AND NOT((wire_nl0l1O11l_dataout AND niOiili0l)); + wire_nli11l1Ol_dataout <= nli11ilOi OR niOiili1O; + wire_nli11li0i_dataout <= wire_nli11li0l_dataout AND NOT(niOiillil); + wire_nli11li0l_dataout <= nli11l0Ol OR (wire_w_lg_niOiili0O48151w(0) AND wire_nlill0Oll_w_lg_nli11l0OO48152w(0)); + wire_nli11li1l_dataout <= wire_nli11li0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli11li1O_dataout <= wire_nli11liiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli11liiO_dataout <= (niOili0ii AND niOiili0O) WHEN niOiilO1O = '1' ELSE nli11l0OO; + wire_nli11lil_dataout <= (wire_w_lg_niOO1OO1l6182w(0) AND wire_nli11lOO_w_lg_dataout6185w(0)) AND NOT(wire_niO01l0O_dataout); + wire_nli11liO_dataout <= nli11l0l AND NOT(wire_niO01l0O_dataout); + wire_nli11lli_dataout <= (wire_w_lg_niOO1OO1l6182w(0) AND wire_nli11lOO_dataout) AND NOT(wire_niO01l0O_dataout); + wire_nli11lOO_dataout <= (wire_niOOO0O_w_lg_nli11O0l6157w(0) AND wire_w_lg_w_k_hip_range2413w6169w(0)) OR (wire_niOOO0O_w_lg_nli11O0l6157w(0) AND (wire_w_lg_w_k_hip_range2413w2429w(0) AND ((((NOT (nli101OO XOR nli101ll)) AND (NOT (nli1001i XOR nli101lO))) AND (NOT (nli1001l XOR nli101Oi))) AND (NOT (nli1001O XOR nli101Ol))))); + wire_nli11lOO_w_lg_dataout6185w(0) <= wire_nli11lOO_dataout AND wire_niOOO0O_w_lg_nli11l0l6184w(0); + wire_nli11lOO_w_lg_dataout5921w(0) <= NOT wire_nli11lOO_dataout; + wire_nli11O0il_dataout <= wire_nl0l1lOOl_dataout WHEN niOiiliiO = '1' ELSE nli11li1i; + wire_nli11O0iO_dataout <= wire_nl0l1lOOi_dataout WHEN niOiiliiO = '1' ELSE nli11O1il; + wire_nli11O0li_dataout <= wire_nl0l1lOlO_dataout WHEN niOiiliiO = '1' ELSE nli11O1iO; + wire_nli11O0ll_dataout <= wire_nli11O0Ol_dataout AND NOT(wire_nilOi01l_dataout); + wire_nli11O0lO_dataout <= wire_nli11O0OO_dataout AND NOT(wire_nilOi01l_dataout); + wire_nli11O0O_dataout <= nli1i0iO AND NOT(wire_niO01l0O_dataout); + wire_nli11O0Oi_dataout <= wire_nli11Oi1i_dataout AND NOT(wire_nilOi01l_dataout); + wire_nli11O0Ol_dataout <= wire_nl0l1lOiO_dataout WHEN niOiiliil = '1' ELSE nli11O1li; + wire_nli11O0OO_dataout <= wire_nl0l1lOli_dataout WHEN niOiiliil = '1' ELSE nli11O1ll; + wire_nli11O10i_dataout <= nli11O01l WHEN niOiiliii = '1' ELSE nli11O00O; + wire_nli11O10i_w_lg_dataout46540w(0) <= NOT wire_nli11O10i_dataout; + wire_nli11O10O_dataout <= k_conf(360) AND NOT((niOiilOlO OR wire_w_lg_niOiilO1i48030w(0))); + wire_nli11O10O_w_lg_dataout46537w(0) <= NOT wire_nli11O10O_dataout; + wire_nli11O11i_dataout <= nli11O1Ol WHEN niOiiliii = '1' ELSE nli11O01O; + wire_nli11O11i_w_lg_dataout46543w(0) <= NOT wire_nli11O11i_dataout; + wire_nli11O11l_dataout <= nli11O1OO WHEN niOiiliii = '1' ELSE nli11O00i; + wire_nli11O11l_w_lg_dataout46542w(0) <= NOT wire_nli11O11l_dataout; + wire_nli11O11O_dataout <= nli11O01i WHEN niOiiliii = '1' ELSE nli11O00l; + wire_nli11O11O_w_lg_dataout46541w(0) <= NOT wire_nli11O11O_dataout; + wire_nli11Oi0i_dataout <= wire_nli11Oi0l_dataout AND NOT(wire_nilOi01O_dataout); + wire_nli11Oi0l_dataout <= wire_nl0l1lO0O_dataout WHEN niOiilili = '1' ELSE nli11O1Oi; + wire_nli11Oi0O_dataout <= wire_nl0l1lO1l_dataout WHEN niOiilili = '1' ELSE nli11O1Ol; + wire_nli11Oi1i_dataout <= wire_nl0l1lOll_dataout WHEN niOiiliil = '1' ELSE nli11O1lO; + wire_nli11Oii_dataout <= nli1i0li AND NOT(wire_niO01l0O_dataout); + wire_nli11Oiii_dataout <= wire_nl0l1lO1O_dataout WHEN niOiilili = '1' ELSE nli11O1OO; + wire_nli11Oiil_dataout <= wire_nl0l1lO0i_dataout WHEN niOiilili = '1' ELSE nli11O01i; + wire_nli11OiiO_dataout <= wire_nl0l1lO0l_dataout WHEN niOiilili = '1' ELSE nli11O01l; + wire_nli11Oil_dataout <= nli1i0ll AND NOT(wire_niO01l0O_dataout); + wire_nli11Oili_dataout <= wire_nl0l1lO1l_dataout WHEN niOiilili = '1' ELSE nli11O01O; + wire_nli11Oill_dataout <= wire_nl0l1lO1O_dataout WHEN niOiilili = '1' ELSE nli11O00i; + wire_nli11OilO_dataout <= wire_nl0l1lO0i_dataout WHEN niOiilili = '1' ELSE nli11O00l; + wire_nli11OiO_dataout <= nli1i0lO AND NOT(wire_niO01l0O_dataout); + wire_nli11OiOi_dataout <= wire_nl0l1lO0l_dataout WHEN niOiilili = '1' ELSE nli11O00O; + wire_nli11OiOO_dataout <= wire_nli11Ol1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11Ol1i_dataout <= wire_nl0l1lOii_dataout WHEN niOiilili = '1' ELSE nli11O0ii; + wire_nli11OliO_dataout <= wire_nli11OlOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11Olli_dataout <= wire_nli11OO1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11Olll_dataout <= wire_nli11OO0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11OllO_dataout <= wire_nli11OO0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11OlOi_dataout <= wire_nli11OO0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli11OlOl_dataout <= wire_nl0l1lO0O_dataout WHEN niOiililO = '1' ELSE nli11OiOl; + wire_nli11OO0i_dataout <= wire_nli11OOil_dataout WHEN niOiililO = '1' ELSE nli11Ol0l; + wire_nli11OO0l_dataout <= wire_nli11OOiO_dataout WHEN niOiililO = '1' ELSE nli11Ol0O; + wire_nli11OO0O_dataout <= wire_nli11OOli_dataout WHEN niOiililO = '1' ELSE nli11Olii; + wire_nli11OO1O_dataout <= wire_nli11OOii_dataout WHEN niOiililO = '1' ELSE nli11Ol0i; + wire_nli11OOii_dataout <= wire_nl0l1lO1l_dataout WHEN wire_w_lg_niOiiliOi48102w(0) = '1' ELSE nli11Ol0i; + wire_nli11OOil_dataout <= wire_nl0l1lO1O_dataout WHEN wire_w_lg_niOiiliOi48102w(0) = '1' ELSE nli11Ol0l; + wire_nli11OOiO_dataout <= wire_nl0l1lO0i_dataout WHEN wire_w_lg_niOiiliOi48102w(0) = '1' ELSE nli11Ol0O; + wire_nli11OOli_dataout <= wire_nl0l1lO0l_dataout WHEN wire_w_lg_niOiiliOi48102w(0) = '1' ELSE nli11Olii; + wire_nli1i000i_dataout <= wire_nli1i0iii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i000l_dataout <= wire_nli1i0iiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i000O_dataout <= wire_nli1i0iOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i001l_dataout <= wire_nli1i0i0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i001O_dataout <= wire_nli1i0iil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i00ii_dataout <= wire_nli1i0ili_dataout OR wire_niO01Oil_dataout; + wire_nli1i00il_dataout <= wire_nli1i0ill_dataout OR wire_niO01Oil_dataout; + wire_nli1i00iO_dataout <= wire_nli1i0ilO_dataout OR wire_niO01Oil_dataout; + wire_nli1i00li_dataout <= wire_nli1i0iOi_dataout OR wire_niO01Oil_dataout; + wire_nli1i00ll_dataout <= wire_nli1i0iOO_dataout OR wire_niO01Oil_dataout; + wire_nli1i00lO_dataout <= wire_nli1i0l1i_dataout OR wire_niO01Oil_dataout; + wire_nli1i00Oi_dataout <= wire_nli1i0l1l_dataout OR wire_niO01Oil_dataout; + wire_nli1i00Ol_dataout <= wire_nli1i0l1O_dataout OR wire_niO01Oil_dataout; + wire_nli1i00OO_dataout <= wire_nli1i0l0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i0i0i_dataout <= wire_nli1i0lil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i0i0l_dataout <= wire_nli1i0liO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i0i0O_dataout <= wire_nli1i0lli_dataout WHEN niOiiOiii = '1' ELSE nli10OO0l; + wire_nli1i0i1i_dataout <= wire_nli1i0l0l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i0i1l_dataout <= wire_nli1i0l0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i0i1O_dataout <= wire_nli1i0lii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i0iii_dataout <= wire_nli1i0lOi_dataout WHEN niOiiOiii = '1' ELSE nli1i1OOl; + wire_nli1i0iil_dataout <= nli1i1OOl WHEN niOiiOiii = '1' ELSE nli1i1OOi; + wire_nli1i0iiO_dataout <= nli1i011i WHEN niOiiOiii = '1' ELSE nli1i1OOO; + wire_nli1i0ili_dataout <= wire_nli1i1O1i_dataout WHEN niOiiOiii = '1' ELSE nli1i011l; + wire_nli1i0ill_dataout <= wire_nli1i1O1l_dataout WHEN niOiiOiii = '1' ELSE nli1i011O; + wire_nli1i0ilO_dataout <= wire_nli1i1OiO_dataout WHEN niOiiOiii = '1' ELSE nli1i010i; + wire_nli1i0iOi_dataout <= wire_nli1i1Oli_dataout WHEN niOiiOiii = '1' ELSE nli1i010l; + wire_nli1i0iOl_dataout <= wire_nli1i0O1i_dataout WHEN niOiiOiii = '1' ELSE nli1i011i; + wire_nli1i0iOO_dataout <= wire_nli1i0O1l_dataout WHEN niOiiOiii = '1' ELSE nli1i010O; + wire_nli1i0l0i_dataout <= wire_nli1i0OiO_dataout WHEN niOiiOiii = '1' ELSE nli1i01li; + wire_nli1i0l0l_dataout <= wire_nli1i0Oli_dataout WHEN niOiiOiii = '1' ELSE nli1i01ll; + wire_nli1i0l0O_dataout <= wire_nli1i0Oll_dataout WHEN niOiiOiii = '1' ELSE nli1i01lO; + wire_nli1i0l1i_dataout <= wire_nli1i0O1O_dataout WHEN niOiiOiii = '1' ELSE nli1i01ii; + wire_nli1i0l1l_dataout <= wire_nli1i0Oii_dataout WHEN niOiiOiii = '1' ELSE nli1i01il; + wire_nli1i0l1O_dataout <= wire_nli1i0Oil_dataout WHEN niOiiOiii = '1' ELSE nli1i01iO; + wire_nli1i0lii_dataout <= wire_nli1i0OlO_dataout WHEN niOiiOiii = '1' ELSE nli1i01Oi; + wire_nli1i0lil_dataout <= wire_nli1i0OOi_dataout WHEN niOiiOiii = '1' ELSE nli1i01Ol; + wire_nli1i0liO_dataout <= wire_nli1i0OOl_dataout WHEN niOiiOiii = '1' ELSE nli1i01OO; + wire_nli1i0lli_dataout <= wire_nl0l1lOOl_dataout WHEN (wire_nli1iliOO_dataout AND niOiillli) = '1' ELSE nli10OO0l; + wire_nli1i0lOi_dataout <= wire_nlill0Oll_w_lg_nli1i1OOl48024w(0) WHEN (niOiiOi0O AND (wire_nl0l1lOOi_dataout AND niOiillli)) = '1' ELSE nli1i1OOl; + wire_nli1i0O1i_dataout <= (wire_nl0l1lOlO_dataout AND niOiiOi1l) WHEN niOiillli = '1' ELSE nli1i011i; + wire_nli1i0O1l_dataout <= (wire_nl0l1lOli_dataout AND niOiiOi0l) WHEN niOiillli = '1' ELSE nli1i010O; + wire_nli1i0O1O_dataout <= (wire_nl0l1lOll_dataout AND niOiiOi0l) WHEN niOiillli = '1' ELSE nli1i01ii; + wire_nli1i0Oi_dataout <= wire_nli1il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1i0Oii_dataout <= (wire_nl0l1lOil_dataout AND niOiiOi0i) WHEN niOiillll = '1' ELSE nli1i01il; + wire_nli1i0Oil_dataout <= (wire_nl0l1lOiO_dataout AND niOiiOi0i) WHEN niOiillll = '1' ELSE nli1i01iO; + wire_nli1i0OiO_dataout <= (wire_nl0l1lOii_dataout AND niOillO0i) WHEN niOiillll = '1' ELSE nli1i01li; + wire_nli1i0Ol_dataout <= (wire_nli1il0l_o OR (nli1i10O AND ((((NOT wire_nli10OOl_o(4)) AND (NOT wire_nli10OOl_o(3))) AND (NOT wire_nli10OOl_o(2))) AND (NOT wire_nli10OOl_o(1))))) AND NOT(wire_niO01O0O_dataout); + wire_nli1i0Oli_dataout <= wire_nl0l1lO0O_dataout WHEN niOiillll = '1' ELSE nli1i01ll; + wire_nli1i0Oll_dataout <= wire_nl0l1lO0l_dataout WHEN niOiillll = '1' ELSE nli1i01lO; + wire_nli1i0OlO_dataout <= (wire_nl0l1lO0i_dataout AND niOiiOi1O) WHEN niOiillll = '1' ELSE nli1i01Oi; + wire_nli1i0OO_dataout <= nli100il AND NOT(wire_niO01O0O_dataout); + wire_nli1i0OOi_dataout <= (wire_nl0l1lO1O_dataout AND niOiiOi1l) WHEN niOiillll = '1' ELSE nli1i01Ol; + wire_nli1i0OOl_dataout <= (wire_nl0l1lO1l_dataout AND niOiiOi1i) WHEN niOiillll = '1' ELSE nli1i01OO; + wire_nli1i100l_dataout <= nli1i1OOl WHEN niOiiOi0O = '1' ELSE nli10OliO; + wire_nli1i100O_dataout <= wire_nli1i10ii_dataout AND NOT((wire_nl0l1O1ii_dataout AND niOiilliO)); + wire_nli1i10ii_dataout <= wire_nli1i10il_dataout OR ((NOT k_conf(218)) AND ((wire_w_lg_niOiiOi1l48051w(0) AND (NOT (nli1i011i XOR niOOOO1l))) OR wire_w_lg_niOiillil48057w(0))); + wire_nli1i10il_dataout <= nli10Olli AND NOT(k_conf(218)); + wire_nli1i110i_dataout <= wire_nli1i11Ol_dataout WHEN niOiiOiii = '1' ELSE nli10Olil; + wire_nli1i110l_dataout <= wire_nli1i100l_dataout WHEN niOiiOiii = '1' ELSE nli10OliO; + wire_nli1i110O_dataout <= wire_nli1i100O_dataout WHEN niOiiOiii = '1' ELSE nli10Olli; + wire_nli1i111i_dataout <= wire_nli1i11Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1i111l_dataout <= niOOOl0l AND NOT(wire_niO01Oil_dataout); + wire_nli1i111O_dataout <= wire_nli1iii0O_dataout WHEN niOiiOiii = '1' ELSE nli10Oill; + wire_nli1i11ii_dataout <= wire_nli1i1i0i_dataout WHEN niOiiOiii = '1' ELSE nli10OllO; + wire_nli1i11il_dataout <= wire_nli1i1i0l_dataout WHEN niOiiOiii = '1' ELSE nli10Olll; + wire_nli1i11iO_dataout <= wire_nli1i1i0O_dataout WHEN niOiiOiii = '1' ELSE nli10OlOi; + wire_nli1i11li_dataout <= wire_nli1i1ill_dataout WHEN niOiiOiii = '1' ELSE nli10OO1i; + wire_nli1i11ll_dataout <= wire_nli1i1ilO_dataout WHEN niOiiOiii = '1' ELSE nli10OO1l; + wire_nli1i11lO_dataout <= wire_nli1i1l1l_dataout WHEN niOiiOiii = '1' ELSE nli10OlOl; + wire_nli1i11Oi_dataout <= wire_nli1i1l0O_dataout WHEN niOiiOiii = '1' ELSE nli10OO1O; + wire_nli1i11Ol_dataout <= wire_nli1i11OO_dataout AND NOT((wire_nl0l1O1ll_dataout AND (nl0iOil0i AND niOiilllO))); + wire_nli1i11OO_dataout <= nli10Olil OR (wire_nli1iii0O_dataout XOR nli10Oill); + wire_nli1i1i0i_dataout <= wire_nli1i1iii_dataout WHEN niOiiOi1l = '1' ELSE nli10OllO; + wire_nli1i1i0l_dataout <= niOOOO1l WHEN niOiiOi1l = '1' ELSE nli10Olll; + wire_nli1i1i0O_dataout <= niOOOlOl WHEN niOiiOi1l = '1' ELSE nli10OlOi; + wire_nli1i1ii_dataout <= nli101OO AND NOT(wire_niO01O0O_dataout); + wire_nli1i1iii_dataout <= wire_nli1i1iil_dataout AND NOT((wire_nl0l1O10i_dataout AND niOiilliO)); + wire_nli1i1iil_dataout <= nli10OllO OR (wire_nlill0Oll_w_lg_nli10OlOi48046w(0) AND niOOOlOl); + wire_nli1i1il_dataout <= nli1001i AND NOT(wire_niO01O0O_dataout); + wire_nli1i1ill_dataout <= wire_nli1i1iOi_dataout WHEN niOiiOi1O = '1' ELSE nli10OO1i; + wire_nli1i1ilO_dataout <= niOOOlll WHEN niOiiOi1O = '1' ELSE nli10OO1l; + wire_nli1i1iO_dataout <= nli1001l AND NOT(wire_niO01O0O_dataout); + wire_nli1i1iOi_dataout <= wire_nli1i1iOl_dataout AND NOT((wire_nl0l1O10l_dataout AND niOiilliO)); + wire_nli1i1iOl_dataout <= nli10OO1i OR (nli10OO1l XOR niOOOlll); + wire_nli1i1l0O_dataout <= wire_nli1i1lii_dataout WHEN niOiiOi1i = '1' ELSE nli10OO1O; + wire_nli1i1l1l_dataout <= wire_nli1i1l1O_dataout AND NOT((wire_nl0l1O10O_dataout AND niOiilliO)); + wire_nli1i1l1O_dataout <= nli10OlOl OR (nli10OlOO XOR niOOOlil); + wire_nli1i1li_dataout <= nli1001O AND NOT(wire_niO01O0O_dataout); + wire_nli1i1lii_dataout <= wire_nli1i1lil_dataout AND NOT((wire_nl0l1O11O_dataout AND niOiilliO)); + wire_nli1i1lil_dataout <= nli10OO1O OR (nl0l010Ol OR (wire_nlill0Oll_w_lg_nli10OO0i48038w(0) AND niOOOl0l)); + wire_nli1i1llO_dataout <= nli1i011l WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0l AND nli1i011l); + wire_nli1i1lOi_dataout <= nli1i011O WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0l AND nli1i011O); + wire_nli1i1O0l_dataout <= nli1i010i WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0i AND nli1i010i); + wire_nli1i1O0O_dataout <= nli1i010l WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0i AND nli1i010l); + wire_nli1i1O1i_dataout <= nli1i010O WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0l AND nli1i010O); + wire_nli1i1O1i_w_lg_dataout46489w(0) <= NOT wire_nli1i1O1i_dataout; + wire_nli1i1O1i_w_lg_w_lg_dataout48141w48143w(0) <= wire_nli1i1O1i_w_lg_dataout48141w(0) OR wire_nli1i1O1l_w_lg_dataout48142w(0); + wire_nli1i1O1i_w_lg_dataout48141w(0) <= wire_nli1i1O1i_dataout XOR wire_nli1i1llO_dataout; + wire_nli1i1O1l_dataout <= nli1i01ii WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0l AND nli1i01ii); + wire_nli1i1O1l_w_lg_dataout46488w(0) <= NOT wire_nli1i1O1l_dataout; + wire_nli1i1O1l_w_lg_dataout48142w(0) <= wire_nli1i1O1l_dataout XOR wire_nli1i1lOi_dataout; + wire_nli1i1OiO_dataout <= nli1i01il WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0i AND nli1i01il); + wire_nli1i1OiO_w_lg_dataout46491w(0) <= NOT wire_nli1i1OiO_dataout; + wire_nli1i1OiO_w_lg_w_lg_dataout48136w48138w(0) <= wire_nli1i1OiO_w_lg_dataout48136w(0) OR wire_nli1i1Oli_w_lg_dataout48137w(0); + wire_nli1i1OiO_w_lg_dataout48136w(0) <= wire_nli1i1OiO_dataout XOR wire_nli1i1O0l_dataout; + wire_nli1i1Oli_dataout <= nli1i01iO WHEN wire_w_lg_niOiilO1i48030w(0) = '1' ELSE (niOiiOi0i AND nli1i01iO); + wire_nli1i1Oli_w_lg_dataout46490w(0) <= NOT wire_nli1i1Oli_dataout; + wire_nli1i1Oli_w_lg_dataout48137w(0) <= wire_nli1i1Oli_dataout XOR wire_nli1i1O0O_dataout; + wire_nli1ii00i_dataout <= k_conf(174) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii00i_w_lg_dataout46465w(0) <= NOT wire_nli1ii00i_dataout; + wire_nli1ii00l_dataout <= k_conf(175) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii00l_w_lg_dataout46464w(0) <= NOT wire_nli1ii00l_dataout; + wire_nli1ii00O_dataout <= k_conf(176) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii00O_w_lg_dataout46463w(0) <= NOT wire_nli1ii00O_dataout; + wire_nli1ii01i_dataout <= k_conf(171) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii01i_w_lg_dataout46468w(0) <= NOT wire_nli1ii01i_dataout; + wire_nli1ii01l_dataout <= k_conf(172) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii01l_w_lg_dataout46467w(0) <= NOT wire_nli1ii01l_dataout; + wire_nli1ii01O_dataout <= k_conf(173) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii01O_w_lg_dataout46466w(0) <= NOT wire_nli1ii01O_dataout; + wire_nli1ii0i_dataout <= wire_nli1ilOl_dataout OR wire_niO01O0O_dataout; + wire_nli1ii0ii_dataout <= k_conf(177) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii0ii_w_lg_dataout46462w(0) <= NOT wire_nli1ii0ii_dataout; + wire_nli1ii0il_dataout <= k_conf(144) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii0il_w_lg_dataout46461w(0) <= NOT wire_nli1ii0il_dataout; + wire_nli1ii0iO_dataout <= k_conf(145) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii0iO_w_lg_dataout46460w(0) <= NOT wire_nli1ii0iO_dataout; + wire_nli1ii0l_dataout <= wire_nli1ilOO_dataout OR wire_niO01O0O_dataout; + wire_nli1ii0lO_dataout <= wire_nli1ii0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1ii0O_dataout <= wire_nli1iO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1ii0Oi_dataout <= wire_nli1ii0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1ii0Ol_dataout <= wire_nli1iii1i_dataout WHEN niOiiOiii = '1' ELSE nli1i001i; + wire_nli1ii0OO_dataout <= wire_nilOO00O_dataout WHEN niOiiOiii = '1' ELSE nli1ii0li; + wire_nli1ii1i_dataout <= nli1000i AND NOT(wire_niO01O0O_dataout); + wire_nli1ii1l_dataout <= nli1000O AND NOT(wire_niO01O0O_dataout); + wire_nli1ii1O_dataout <= nli100ii AND NOT(wire_niO01O0O_dataout); + wire_nli1ii1OO_dataout <= k_conf(170) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ii1OO_w_lg_dataout46469w(0) <= NOT wire_nli1ii1OO_dataout; + wire_nli1iii0O_dataout <= wire_niO1110l_dataout AND wire_nli1iliOO_dataout; + wire_nli1iii0O_w_lg_dataout46419w(0) <= NOT wire_nli1iii0O_dataout; + wire_nli1iii1i_dataout <= wire_nli1iii1l_dataout AND NOT((wire_nilOO00O_w_lg_dataout47986w(0) OR nl0illlli)); + wire_nli1iii1l_dataout <= nli1i001i OR ((nl0iOilli AND niOili01l) OR wire_nlill0Oll_w_lg_nli1ii0li47984w(0)); + wire_nli1iiii_dataout <= wire_nli1iO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1iiiii_dataout <= nli1iiilO AND NOT(niOiilOli); + wire_nli1iiiii_w_lg_dataout46421w(0) <= NOT wire_nli1iiiii_dataout; + wire_nli1iiiil_dataout <= nli1iiiOi AND NOT(niOiilOli); + wire_nli1iiiil_w_lg_dataout46422w(0) <= NOT wire_nli1iiiil_dataout; + wire_nli1iiil_dataout <= wire_nli1illi_dataout OR wire_niO01O0O_dataout; + wire_nli1iiiO_dataout <= wire_nli1illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1iiiOO_dataout <= wire_nlOi00lll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iil0i_dataout <= (wire_nilOO00l_dataout OR nli1il11l) AND NOT(wire_niO01Oil_dataout); + wire_nli1iil0l_dataout <= wire_nli1iiOil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iil0O_dataout <= wire_nli1iilii_dataout AND wire_nli1iiOiO_dataout; + wire_nli1iil1i_dataout <= wire_nlOi00lii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iil1l_dataout <= wire_nli1iilOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iil1O_dataout <= wire_nli1iil0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iili_dataout <= wire_nli1illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1iilii_dataout <= wire_nli1iilil_dataout AND NOT((wire_nl0l1O01O_dataout AND (nl0iOil0i AND (nl0iOiliO AND (niOili01l AND nli1iiill))))); + wire_nli1iilil_dataout <= nli1iiill OR (wire_nlill0Oll_w_lg_nli1iiiiO47976w(0) AND wire_nlOi00lii_dataout); + wire_nli1iill_dataout <= wire_nli1ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1iilO_dataout <= wire_nli1il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1iilOl_dataout <= wire_nli1iilOO_dataout AND wire_nli1iiOli_dataout; + wire_nli1iilOO_dataout <= wire_nli1iiO1i_dataout AND NOT((wire_nl0l1O01l_dataout AND (nl0iOil0i AND (nl0iOiliO AND (niOili01l AND nli1iiili))))); + wire_nli1iiO1i_dataout <= nli1iiili OR (wire_nlill0Oll_w_lg_nli1ii0ll47970w(0) AND wire_nlOi00lll_dataout); + wire_nli1iiOi_dataout <= wire_nli1ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1iiOil_dataout <= nli1iiiOi AND NOT(wire_nilOO0ii_dataout); + wire_nli1iiOiO_dataout <= nli1iiOOi AND niOiilO1i; + wire_nli1iiOiO_w_lg_dataout46423w(0) <= NOT wire_nli1iiOiO_dataout; + wire_nli1iiOl_dataout <= wire_nli1ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1iiOli_dataout <= nli1iiOlO AND niOiilO1i; + wire_nli1iiOli_w_lg_dataout46424w(0) <= NOT wire_nli1iiOli_dataout; + wire_nli1iiOll_dataout <= nli1iiiOl AND niOiilO1i; + wire_nli1iiOll_w_lg_dataout46425w(0) <= NOT wire_nli1iiOll_dataout; + wire_nli1iiOO_dataout <= wire_nli1iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1il00i_dataout <= wire_nli1il00l_dataout WHEN niOiillOi = '1' ELSE nli1iiOOi; + wire_nli1il00l_dataout <= nli1iiOOi WHEN niOiilOlO = '1' ELSE wire_nl0l1lOOi_dataout; + wire_nli1il01i_dataout <= wire_nli1iliiO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il01l_dataout <= wire_nli1ilill_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il01O_dataout <= wire_nli1ililO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il0ii_dataout <= wire_nli1il0il_dataout WHEN niOiillOi = '1' ELSE nli1iiOlO; + wire_nli1il0il_dataout <= nli1iiOlO WHEN niOiilOlO = '1' ELSE wire_nl0l1lOlO_dataout; + wire_nli1il0iO_dataout <= wire_nl0l1lOll_dataout WHEN niOiillOi = '1' ELSE nli1iiiOl; + wire_nli1il0lO_dataout <= wire_nl0l1lOli_dataout WHEN (nl0iOil1l AND (nl0iOiliO AND (k_conf(167) AND niOili01l))) = '1' ELSE nli1iiOOl; + wire_nli1il0O_dataout <= nli1i00l WHEN wire_nli1l01O_dataout = '1' ELSE nli1i0iO; + wire_nli1il1i_dataout <= nli1i10O WHEN ((((NOT (niOO1OllO XOR niOO1Olll)) AND (NOT (niOO1Olli XOR niOO1OliO))) AND (NOT (niOO1Olil XOR niOO1Olii))) AND (NOT (nli1i0lO XOR nli1i1OO))) = '1' ELSE wire_nli1il1l_o; + wire_nli1il1il_dataout <= wire_nli1il0iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il1iO_dataout <= wire_nli1il0ii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il1li_dataout <= wire_nli1il00i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il1ll_dataout <= wire_nli1il0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il1lO_dataout <= wire_nli1ili1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il1Oi_dataout <= wire_nli1ili1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il1Ol_dataout <= wire_nli1ili1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1il1OO_dataout <= wire_nli1iliii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1ili0i_dataout <= nli1il11l OR (wire_nl0l1lOii_dataout AND niOiillOO); + wire_nli1ili1i_dataout <= wire_nl0l1lOiO_dataout WHEN niOiillOO = '1' ELSE nli1iiOOO; + wire_nli1ili1l_dataout <= wire_nl0l1lOil_dataout WHEN niOiillOO = '1' ELSE nli1il11i; + wire_nli1ili1O_dataout <= wire_nli1ili0i_dataout AND NOT((niOiilOlO OR nli1il11l)); + wire_nli1ilii_dataout <= nli1i00O WHEN wire_nli1l01O_dataout = '1' ELSE nli1i0li; + wire_nli1iliii_dataout <= wire_nli1iliil_dataout AND NOT(niOiilOlO); + wire_nli1iliil_dataout <= wire_nl0l1lO0O_dataout WHEN niOiillOO = '1' ELSE (nli1il11O AND wire_nl1000i_w_lg_niOOOOiO8394w(0)); + wire_nli1iliiO_dataout <= wire_nli1ilili_dataout AND niOiilOll; + wire_nli1ilil_dataout <= nli1i0ii WHEN wire_nli1l01O_dataout = '1' ELSE nli1i0ll; + wire_nli1ilili_dataout <= wire_nl0l1lO0l_dataout WHEN niOiillOO = '1' ELSE nli1il10i; + wire_nli1ilill_dataout <= wire_nl0l1lO1l_dataout WHEN niOiillOO = '1' ELSE nli1il10l; + wire_nli1ililO_dataout <= wire_nl0l1lO1O_dataout WHEN niOiillOO = '1' ELSE nli1il10O; + wire_nli1iliO_dataout <= nli1i0il WHEN wire_nli1l01O_dataout = '1' ELSE nli1i0lO; + wire_nli1iliOl_dataout <= wire_w_lg_niOiilOlO47917w(0) AND niOiilO1i; + wire_nli1iliOl_w_lg_dataout46389w(0) <= NOT wire_nli1iliOl_dataout; + wire_nli1iliOO_dataout <= k_conf(132) AND wire_w_lg_niOiilOlO47917w(0); + wire_nli1ill0i_dataout <= k_conf(368) WHEN wire_nlill0Oll_w_lg_nli1il11i46428w(0) = '1' ELSE k_conf(365); + wire_nli1ill0i_w_lg_dataout46400w(0) <= NOT wire_nli1ill0i_dataout; + wire_nli1ill0l_dataout <= k_conf(369) WHEN wire_nlill0Oll_w_lg_nli1il11i46428w(0) = '1' ELSE k_conf(366); + wire_nli1ill0l_w_lg_dataout46399w(0) <= NOT wire_nli1ill0l_dataout; + wire_nli1ill0O_dataout <= k_conf(370) WHEN wire_nlill0Oll_w_lg_nli1il11i46428w(0) = '1' ELSE k_conf(367); + wire_nli1ill0O_w_lg_dataout46398w(0) <= NOT wire_nli1ill0O_dataout; + wire_nli1ill1i_dataout <= k_conf(157) WHEN wire_nlill0Oll_w_lg_nli1il11i46428w(0) = '1' ELSE k_conf(154); + wire_nli1ill1i_w_lg_dataout46397w(0) <= NOT wire_nli1ill1i_dataout; + wire_nli1ill1l_dataout <= k_conf(158) WHEN wire_nlill0Oll_w_lg_nli1il11i46428w(0) = '1' ELSE k_conf(155); + wire_nli1ill1l_w_lg_dataout46396w(0) <= NOT wire_nli1ill1l_dataout; + wire_nli1ill1O_dataout <= k_conf(159) WHEN wire_nlill0Oll_w_lg_nli1il11i46428w(0) = '1' ELSE k_conf(156); + wire_nli1ill1O_w_lg_dataout46395w(0) <= NOT wire_nli1ill1O_dataout; + wire_nli1illi_dataout <= nli1i01i WHEN wire_nli1l01O_dataout = '1' ELSE nli1i00l; + wire_nli1illii_dataout <= (NOT k_gbl_hip(34)) OR niOiilO1l; + wire_nli1illii_w_lg_dataout46416w(0) <= NOT wire_nli1illii_dataout; + wire_nli1illil_dataout <= k_gbl_hip(34) AND NOT(niOiilO1l); + wire_nli1illil_w_lg_dataout46415w(0) <= NOT wire_nli1illil_dataout; + wire_nli1illl_dataout <= nli1i01l WHEN wire_nli1l01O_dataout = '1' ELSE nli1i00O; + wire_nli1illO_dataout <= nli1i01O WHEN wire_nli1l01O_dataout = '1' ELSE nli1i0ii; + wire_nli1ilO0i_dataout <= wire_nli1ilOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1ilO0l_dataout <= wire_nli1ilOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1ilO0O_dataout <= wire_nli1iO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nli1ilOi_dataout <= nli1i00i WHEN wire_nli1l01O_dataout = '1' ELSE nli1i0il; + wire_nli1ilOii_dataout <= niOiliiOi AND NOT(wire_niO01O0O_dataout); + wire_nli1ilOil_dataout <= niOilil1l AND NOT(wire_niO01O0O_dataout); + wire_nli1ilOiO_dataout <= niOill11O AND NOT(wire_niO01O0O_dataout); + wire_nli1ilOl_dataout <= (wire_w_lg_niOO1OO1i5988w(0) XOR nli1i01i) WHEN wire_nli1l01O_dataout = '1' ELSE nli1i01i; + wire_nli1ilOli_dataout <= wire_nli1ilOll_dataout AND NOT((wire_nl0illiOO_dataout OR niOiilO1O)); + wire_nli1ilOll_dataout <= nli1illiO OR (nli1iOl1l AND (wire_nlill0Oll_w_lg_nli1illOi47944w(0) AND niOill11O)); + wire_nli1ilOO_dataout <= ((niOO1OO1i AND wire_w_lg_niOO1OlOO5989w(0)) XOR nli1i01l) WHEN wire_nli1l01O_dataout = '1' ELSE nli1i01l; + wire_nli1ilOOO_dataout <= wire_nli1iO11i_dataout AND NOT((wire_nl0illl1i_dataout OR niOiilO1O)); + wire_nli1iO00O_dataout <= wire_nli1iO0ii_dataout OR wire_w_lg_niOili00i47932w(0); + wire_nli1iO01i_dataout <= wire_nli1iO01l_dataout OR wire_nli0OOlii_dataout; + wire_nli1iO01l_dataout <= nli1illOl AND NOT((wire_nl0l1O10O_dataout AND niOiilO0i)); + wire_nli1iO0ii_dataout <= nli1illOO AND NOT((wire_nl0l1O10l_dataout AND niOiilO0i)); + wire_nli1iO0iO_dataout <= wire_nli1iO0li_dataout OR wire_w_lg_niOili00l47930w(0); + wire_nli1iO0li_dataout <= nli1ilO1i AND NOT((wire_nl0l1O10i_dataout AND niOiilO0i)); + wire_nli1iO0lO_dataout <= wire_nli1iO0Oi_dataout OR wire_w_lg_niOili00O47928w(0); + wire_nli1iO0Oi_dataout <= nli1ilO1l AND NOT((wire_nl0l1O11O_dataout AND niOiilO0i)); + wire_nli1iO10O_dataout <= wire_nli1iO1ii_dataout AND NOT((wire_nl0illl1l_dataout OR niOiilO1O)); + wire_nli1iO11i_dataout <= nli1il1ii OR (wire_nlill0Oll_w_lg_w_lg_nli1illlO47940w47941w(0) AND (wire_nli0O011O_dataout OR nli1iOl1i)); + wire_nli1iO1i_dataout <= ((wire_w_lg_niOO1OlOl5996w(0) AND wire_w_lg_niOO1OlOi5992w(0)) XOR nli1i01O) WHEN wire_nli1l01O_dataout = '1' ELSE nli1i01O; + wire_nli1iO1ii_dataout <= nli1illli OR (wire_nlill0Oll_w_lg_w_lg_nli1illll47936w47937w(0) AND (wire_nli0O011O_dataout OR nli1iOiOO)); + wire_nli1iO1l_dataout <= ((NOT (niOO1OlOl OR wire_w_lg_niOO1OlOi5992w(0))) XOR nli1i00i) WHEN wire_nli1l01O_dataout = '1' ELSE nli1i00i; + wire_nli1iO1lO_dataout <= wire_nli1iO01i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iO1Oi_dataout <= wire_nli1iO00O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iO1Ol_dataout <= wire_nli1iO0iO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iO1OO_dataout <= wire_nli1iO0lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOi1i_dataout <= wire_nl0l1lOlO_dataout WHEN (nl0iOil1l AND (nl0iOilii AND (k_conf(111) AND niOili01l))) = '1' ELSE nli1ilO1O; + wire_nli1iOl0i_dataout <= wire_nli1iOO0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOl0l_dataout <= wire_nli1iOOii_dataout OR wire_niO01Oil_dataout; + wire_nli1iOl0O_dataout <= wire_nli1iOOil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOlii_dataout <= wire_nli1iOO1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOlil_dataout <= wire_nli1iOOiO_dataout OR wire_niO01Oil_dataout; + wire_nli1iOliO_dataout <= wire_nli1iOOli_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOlli_dataout <= wire_nli1iOOlO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOlll_dataout <= wire_nli1iOOOi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOllO_dataout <= wire_nli1iOOOl_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOlOi_dataout <= wire_nli1l111i_dataout OR wire_niO01Oil_dataout; + wire_nli1iOlOl_dataout <= wire_nli1l111l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOlOO_dataout <= wire_nli1l111O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOO0i_dataout <= wire_nl0l1O11l_dataout WHEN niOiilOiO = '1' ELSE nli1iO0OO; + wire_nli1iOO0O_dataout <= wire_nl0l1lOOl_dataout WHEN niOiilO0l = '1' ELSE nli1iOi0l; + wire_nli1iOO1i_dataout <= wire_nli1l110i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOO1l_dataout <= wire_nli1l110l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1iOO1O_dataout <= wire_nli1iOO0i_dataout WHEN niOiilO0l = '1' ELSE nli1iO0OO; + wire_nli1iOOii_dataout <= wire_nl0l1lOOO_dataout WHEN niOiilO0l = '1' ELSE nli1iOi0O; + wire_nli1iOOil_dataout <= wire_nl0l1O11i_dataout WHEN niOiilO0l = '1' ELSE nli1iOiii; + wire_nli1iOOiO_dataout <= wire_nl0l1lOOi_dataout WHEN niOiilO0l = '1' ELSE nli1iOiil; + wire_nli1iOOli_dataout <= wire_nli1iOOll_dataout AND k_conf(133); + wire_nli1iOOll_dataout <= wire_nl0l1lOli_dataout WHEN niOiilO0l = '1' ELSE nli1iOiiO; + wire_nli1iOOlO_dataout <= wire_nl0l1lOii_dataout WHEN niOiilOii = '1' ELSE nli1iOili; + wire_nli1iOOOi_dataout <= wire_nl0l1lOil_dataout WHEN niOiilOii = '1' ELSE nli1iOill; + wire_nli1iOOOl_dataout <= wire_nl0l1lOiO_dataout WHEN niOiilOii = '1' ELSE nli1iOilO; + wire_nli1l001i_dataout <= wire_nliliO10i_w_lg_nli1liO1l47847w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l001l_dataout <= wire_nliliO10i_w_lg_nli1liO1l47847w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l00l_dataout <= rx_ready_vc0 AND NOT(wire_niO01l0O_dataout); + wire_nli1l010i_dataout <= wire_nliliO10i_w_lg_nli1lilOi47851w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l010l_dataout <= wire_nliliO10i_w_lg_nli1lilOi47851w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l010O_dataout <= wire_nliliO10i_w_lg_nli1lilOl47850w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l011i_dataout <= wire_nliliO10i_w_lg_nli1lillO47852w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l011l_dataout <= wire_nliliO10i_w_lg_nli1lillO47852w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l011O_dataout <= wire_nliliO10i_w_lg_nli1lilOi47851w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01ii_dataout <= wire_nliliO10i_w_lg_nli1lilOl47850w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01il_dataout <= wire_nliliO10i_w_lg_nli1lilOl47850w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01iO_dataout <= wire_nliliO10i_w_lg_nli1lilOO47849w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01li_dataout <= wire_nliliO10i_w_lg_nli1lilOO47849w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01ll_dataout <= wire_nliliO10i_w_lg_nli1lilOO47849w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01lO_dataout <= wire_nliliO10i_w_lg_nli1liO1i47848w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01O_dataout <= niOO01lOi WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE niOO0100l; + wire_nli1l01Oi_dataout <= wire_nliliO10i_w_lg_nli1liO1i47848w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01Ol_dataout <= wire_nliliO10i_w_lg_nli1liO1i47848w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l01OO_dataout <= wire_nliliO10i_w_lg_nli1liO1l47847w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0i0i_dataout <= (nl0iOiill AND (NOT (wire_nli1li0lO_dataout AND (wire_nli1liill_dataout AND wire_nli1lii0O_dataout)))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0i0l_dataout <= (nl0iOiill AND (NOT (wire_nli1liiOi_dataout AND wire_nli1li0Oi_dataout))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0i0O_dataout <= (nl0iOiill AND (NOT (wire_nli1liiOl_dataout AND wire_nli1li0Ol_dataout))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0i1i_dataout <= (nl0iOiill AND (NOT (wire_nli1li1li_dataout AND (wire_nli1li1lO_dataout AND (wire_nli1li1Ol_dataout AND (wire_nli1li01i_dataout AND (wire_nli1li01O_dataout AND (wire_nli1li00l_dataout AND (wire_nli1li0ii_dataout AND (wire_nlill0Oll_w_lg_nl0iOilli47862w(0) AND (wire_nli1liiil_dataout AND wire_nli1lii1l_dataout))))))))))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0i1l_dataout <= (nl0iOiill AND (NOT (wire_nli1li0li_dataout AND (wire_nli1lii0i_dataout AND (wire_nlill0Oll_w_lg_nl0iOil0l44799w(0) AND wire_nli1liiiO_dataout))))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0i1O_dataout <= (nl0iOiill AND (NOT (wire_nli1li0ll_dataout AND (wire_nli1liili_dataout AND wire_nli1lii0l_dataout)))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0iii_dataout <= (nl0iOiill AND (NOT (wire_nli1liiOO_dataout AND wire_nli1li0OO_dataout))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0iil_dataout <= (nl0iOiill AND wire_nli1lii1i_w_lg_dataout47882w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0iiO_dataout <= (nl0iOiill AND (NOT (wire_nli1li1ll_dataout AND (wire_nli1li1Oi_dataout AND (wire_nli1li1OO_dataout AND (wire_nli1li01l_dataout AND (wire_nli1li00i_dataout AND (wire_nli1li00O_dataout AND (wire_nli1lii1O_dataout AND wire_nli1li0il_dataout))))))))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0il_dataout <= wire_nli11lOO_w_lg_dataout5921w(0) WHEN (k_gbl_hip(33) OR k_hip(22)) = '1' ELSE wire_nli1l0iO_dataout; + wire_nli1l0ili_dataout <= (nl0iOiill AND (NOT (wire_nlill0Oll_w_lg_nl0iOil0l44799w(0) AND wire_nli1liiii_dataout))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0ill_dataout <= (nl0iOiill AND wire_nli1li0iO_w_lg_dataout47868w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0ilO_dataout <= (nl0iOiill AND wire_nli1liilO_w_lg_dataout47866w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0iO_dataout <= wire_nli1l0li_dataout OR NOT(wire_nli11lOO_dataout); + wire_nli1l0iOi_dataout <= (nl0iOiill AND (NOT (wire_nlill0Oll_w_lg_nl0iOilli47862w(0) AND wire_nli1lil1i_dataout))) AND NOT(wire_niO01O0O_dataout); + wire_nli1l0li_dataout <= (nli1l00i AND niOO1OO0i) AND NOT(niOO1OO1O); + wire_nli1l100i_dataout <= wire_nli1l10Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l100l_dataout <= wire_nli1l10OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l100O_dataout <= wire_nli1l1i1i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l101i_dataout <= wire_nli1l10ll_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l101l_dataout <= wire_nli1l10lO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l101O_dataout <= wire_nli1l10Oi_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l10ii_dataout <= wire_nli1l1i1l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l10il_dataout <= wire_nli1l1i1O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l10iO_dataout <= wire_nli1l1i0i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l10li_dataout <= wire_nl1ilil0l_dataout WHEN niOiilOil = '1' ELSE nli1iOl1O; + wire_nli1l10ll_dataout <= wire_nl1ilil0O_dataout WHEN niOiilOil = '1' ELSE nli1l110O; + wire_nli1l10lO_dataout <= wire_nl1iliilO_dataout WHEN niOiilOil = '1' ELSE nli1l11ii; + wire_nli1l10Oi_dataout <= wire_nl1iliiOi_dataout WHEN niOiilOil = '1' ELSE nli1l11il; + wire_nli1l10Ol_dataout <= wire_nl1iliiOl_dataout WHEN niOiilOil = '1' ELSE nli1l11iO; + wire_nli1l10OO_dataout <= wire_nl1iliiOO_dataout WHEN niOiilOil = '1' ELSE nli1l11li; + wire_nli1l110i_dataout <= wire_nl0l1lO1O_dataout WHEN niOiilOii = '1' ELSE nli1iOl1i; + wire_nli1l110l_dataout <= wire_nl0l1lO1l_dataout WHEN niOiilOii = '1' ELSE nli1iOl1l; + wire_nli1l111i_dataout <= wire_nl0l1lO0O_dataout WHEN niOiilOii = '1' ELSE nli1iOiOi; + wire_nli1l111l_dataout <= wire_nl0l1lO0l_dataout WHEN niOiilOii = '1' ELSE nli1iOiOl; + wire_nli1l111O_dataout <= wire_nl0l1lO0i_dataout WHEN niOiilOii = '1' ELSE nli1iOiOO; + wire_nli1l11OO_dataout <= wire_nli1l10li_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1l1i0i_dataout <= wire_nl1ilil0i_dataout WHEN niOiilOil = '1' ELSE nli1l11Ol; + wire_nli1l1i1i_dataout <= wire_nl1ilil1i_dataout WHEN niOiilOil = '1' ELSE nli1l11ll; + wire_nli1l1i1l_dataout <= wire_nl1ilil1l_dataout WHEN niOiilOil = '1' ELSE nli1l11lO; + wire_nli1l1i1O_dataout <= wire_nl1ilil1O_dataout WHEN niOiilOil = '1' ELSE nli1l11Oi; + wire_nli1l1iiO_dataout <= k_conf(361) OR niOiilOOi; + wire_nli1l1iiO_w_lg_dataout46328w(0) <= NOT wire_nli1l1iiO_dataout; + wire_nli1l1ili_dataout <= k_conf(362) AND NOT(niOiilOOi); + wire_nli1l1ili_w_lg_dataout46327w(0) <= NOT wire_nli1l1ili_dataout; + wire_nli1l1ill_dataout <= k_conf(363) AND NOT(niOiilOOi); + wire_nli1l1ill_w_lg_dataout46326w(0) <= NOT wire_nli1l1ill_dataout; + wire_nli1l1ilO_dataout <= k_conf(364) AND NOT(niOiilOOi); + wire_nli1l1ilO_w_lg_w_lg_w_lg_dataout46325w48154w48155w(0) <= wire_nli1l1ilO_w_lg_w_lg_dataout46325w48154w(0) AND wire_nli1l1ili_dataout; + wire_nli1l1ilO_w_lg_w_lg_dataout46325w48154w(0) <= wire_nli1l1ilO_w_lg_dataout46325w(0) AND wire_nli1l1ill_w_lg_dataout46326w(0); + wire_nli1l1ilO_w_lg_dataout46325w(0) <= NOT wire_nli1l1ilO_dataout; + wire_nli1l1OlO_dataout <= wire_nliliO10i_w_lg_nli1lilll47853w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l1OOi_dataout <= wire_nliliO10i_w_lg_nli1lilll47853w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l1OOl_dataout <= wire_nliliO10i_w_lg_nli1lilll47853w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1l1OOO_dataout <= wire_nliliO10i_w_lg_nli1lillO47852w(0) AND NOT(wire_niO01O0O_dataout); + wire_nli1li00i_dataout <= wire_nli1lilii_w_lg_dataout47857w(0) OR NOT(nl0iOiO1O); + wire_nli1li00l_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOilOO); + wire_nli1li00O_dataout <= wire_nli1lilil_w_lg_dataout47856w(0) OR NOT(nl0iOilOO); + wire_nli1li01i_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOiO0O); + wire_nli1li01l_dataout <= wire_nli1lil0O_w_lg_dataout47858w(0) OR NOT(nl0iOiO0O); + wire_nli1li01O_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOiO1O); + wire_nli1li0ii_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOillO); + wire_nli1li0il_dataout <= wire_nli1liliO_w_lg_dataout47855w(0) OR NOT(nl0iOillO); + wire_nli1li0iO_dataout <= wire_nlill0Oll_w_lg_nli1lilli47854w(0) OR NOT(nl0iOilll); + wire_nli1li0iO_w_lg_dataout47868w(0) <= NOT wire_nli1li0iO_dataout; + wire_nli1li0li_dataout <= wire_nliliO10i_w_lg_nli1lilll47853w(0) OR NOT(nl0iOilli); + wire_nli1li0ll_dataout <= wire_nliliO10i_w_lg_nli1lillO47852w(0) OR NOT(nl0iOilli); + wire_nli1li0lO_dataout <= wire_nliliO10i_w_lg_nli1lilOi47851w(0) OR NOT(nl0iOilli); + wire_nli1li0Oi_dataout <= wire_nliliO10i_w_lg_nli1lilOl47850w(0) OR NOT(nl0iOilli); + wire_nli1li0Ol_dataout <= wire_nliliO10i_w_lg_nli1lilOO47849w(0) OR NOT(nl0iOilli); + wire_nli1li0OO_dataout <= wire_nliliO10i_w_lg_nli1liO1i47848w(0) OR NOT(nl0iOilli); + wire_nli1li1li_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOiOOi); + wire_nli1li1ll_dataout <= wire_nli1lil1l_w_lg_dataout47861w(0) OR NOT(nl0iOiOOi); + wire_nli1li1lO_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOiOll); + wire_nli1li1Oi_dataout <= wire_nli1lil0i_w_lg_dataout47860w(0) OR NOT(nl0iOiOll); + wire_nli1li1Ol_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOiOil); + wire_nli1li1OO_dataout <= wire_nli1lil0l_w_lg_dataout47859w(0) OR NOT(nl0iOiOil); + wire_nli1lii0i_dataout <= wire_nlill0Oll_w_lg_nli1liO1O47844w(0) OR NOT(nl0iOilil); + wire_nli1lii0l_dataout <= wire_nlill0Oll_w_lg_nli1ll1ii47843w(0) OR NOT(nl0iOilil); + wire_nli1lii0O_dataout <= wire_nlill0Oll_w_lg_nli1ll1il47842w(0) OR NOT(nl0iOilil); + wire_nli1lii1i_dataout <= wire_nliliO10i_w_lg_nli1liO1l47847w(0) OR NOT(nl0iOilli); + wire_nli1lii1i_w_lg_dataout47882w(0) <= NOT wire_nli1lii1i_dataout; + wire_nli1lii1l_dataout <= wire_w_lg_niOiiO11O47846w(0) OR NOT(nl0iOiliO); + wire_nli1lii1O_dataout <= wire_nli1ll10O_w_lg_dataout47845w(0) OR NOT(nl0iOiliO); + wire_nli1liiii_dataout <= wire_nlill0Oll_w_lg_nli1ll1iO47841w(0) OR NOT(nl0iOilil); + wire_nli1liiil_dataout <= (NOT k_conf(116)) OR NOT(nl0iOilii); + wire_nli1liiiO_dataout <= (NOT k_conf(117)) OR NOT(nl0iOilii); + wire_nli1liili_dataout <= (NOT k_conf(118)) OR NOT(nl0iOilii); + wire_nli1liill_dataout <= (NOT k_conf(119)) OR NOT(nl0iOilii); + wire_nli1liilO_dataout <= wire_w_lg_niOiiO11l47838w(0) OR NOT(nl0iOilii); + wire_nli1liilO_w_lg_dataout47866w(0) <= NOT wire_nli1liilO_dataout; + wire_nli1liiOi_dataout <= (NOT k_conf(113)) OR NOT(nl0iOil0O); + wire_nli1liiOl_dataout <= (NOT k_conf(114)) OR NOT(nl0iOil0O); + wire_nli1liiOO_dataout <= (NOT k_conf(115)) OR NOT(nl0iOil0O); + wire_nli1lil0i_dataout <= k_conf(126) AND niOiilOOO; + wire_nli1lil0i_w_lg_dataout47860w(0) <= NOT wire_nli1lil0i_dataout; + wire_nli1lil0l_dataout <= k_conf(125) AND niOiilOOO; + wire_nli1lil0l_w_lg_dataout47859w(0) <= NOT wire_nli1lil0l_dataout; + wire_nli1lil0O_dataout <= k_conf(124) AND niOiilOOO; + wire_nli1lil0O_w_lg_dataout47858w(0) <= NOT wire_nli1lil0O_dataout; + wire_nli1lil1i_dataout <= wire_w_lg_w_k_conf_range44263w44264w(0) OR NOT(nl0iOil0l); + wire_nli1lil1l_dataout <= k_conf(127) AND niOiilOOO; + wire_nli1lil1l_w_lg_dataout47861w(0) <= NOT wire_nli1lil1l_dataout; + wire_nli1lilii_dataout <= k_conf(123) AND niOiilOOO; + wire_nli1lilii_w_lg_dataout47857w(0) <= NOT wire_nli1lilii_dataout; + wire_nli1lilil_dataout <= k_conf(122) AND niOiilOOO; + wire_nli1lilil_w_lg_dataout47856w(0) <= NOT wire_nli1lilil_dataout; + wire_nli1liliO_dataout <= k_conf(121) AND niOiilOOO; + wire_nli1liliO_w_lg_dataout47855w(0) <= NOT wire_nli1liliO_dataout; + wire_nli1liO0i_dataout <= wire_nilOOO0i_w_lg_dataout47830w(0) AND NOT(wire_niO01Oil_dataout); + wire_nli1liO0l_dataout <= wire_nli1liOlO_dataout OR wire_niO01Oil_dataout; + wire_nli1liO0O_dataout <= wire_nli1liOOi_dataout OR wire_niO01Oil_dataout; + wire_nli1liOii_dataout <= wire_nli1liOOl_dataout OR wire_niO01Oil_dataout; + wire_nli1liOil_dataout <= wire_nli1liOOO_dataout OR wire_niO01Oil_dataout; + wire_nli1liOiO_dataout <= wire_nli1ll11i_dataout OR wire_niO01Oil_dataout; + wire_nli1liOli_dataout <= wire_nli1ll11l_dataout OR wire_niO01Oil_dataout; + wire_nli1liOll_dataout <= wire_nli1ll11O_dataout OR wire_niO01Oil_dataout; + wire_nli1liOlO_dataout <= wire_nl0l1lO1O_dataout WHEN niOiilOOl = '1' ELSE nli1lilll; + wire_nli1liOOi_dataout <= wire_nl0l1lO0i_dataout WHEN niOiilOOl = '1' ELSE nli1lillO; + wire_nli1liOOl_dataout <= wire_nl0l1lO0l_dataout WHEN niOiilOOl = '1' ELSE nli1lilOi; + wire_nli1liOOO_dataout <= wire_nl0l1lO0O_dataout WHEN niOiilOOl = '1' ELSE nli1lilOl; + wire_nli1ll01i_dataout <= wire_nl0l1lO0i_dataout WHEN niOiiO11i = '1' ELSE nli1ll1ii; + wire_nli1ll01l_dataout <= wire_nl0l1lO0l_dataout WHEN niOiiO11i = '1' ELSE nli1ll1il; + wire_nli1ll0OO_dataout <= wire_nl0ll01ll_dataout WHEN niOiiO1OO = '1' ELSE wire_nli1lliil_dataout; + wire_nli1ll0OO_w_lg_dataout53423w(0) <= NOT wire_nli1ll0OO_dataout; + wire_nli1ll10O_dataout <= k_conf(120) AND niOiilOOO; + wire_nli1ll10O_w_lg_dataout47845w(0) <= NOT wire_nli1ll10O_dataout; + wire_nli1ll11i_dataout <= wire_nl0l1lOii_dataout WHEN niOiilOOl = '1' ELSE nli1lilOO; + wire_nli1ll11l_dataout <= wire_nl0l1lOil_dataout WHEN niOiilOOl = '1' ELSE nli1liO1i; + wire_nli1ll11O_dataout <= wire_nl0l1lOiO_dataout WHEN niOiilOOl = '1' ELSE nli1liO1l; + wire_nli1ll1li_dataout <= wire_nli1ll1OO_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1ll1ll_dataout <= wire_nli1ll01i_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1ll1lO_dataout <= wire_nli1ll01l_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1ll1Oi_dataout <= wire_nli1ll1Ol_dataout AND NOT(wire_niO01Oil_dataout); + wire_nli1ll1Ol_dataout <= nli1ll1iO AND niOiiO11l; + wire_nli1ll1OO_dataout <= wire_nl0l1lO1O_dataout WHEN niOiiO11i = '1' ELSE nli1liO1O; + wire_nli1lli0i_dataout <= wire_nl0O0i0OO_dataout WHEN niOiiO1OO = '1' ELSE wire_nli1lll0i_dataout; + wire_nli1lli0i_w_lg_dataout53447w(0) <= NOT wire_nli1lli0i_dataout; + wire_nli1lli0l_dataout <= (((wire_nl0O0iOOl_o AND niOiiO1ll) AND wire_w_lg_w_k_bar_range47783w47785w(0)) AND (wire_w_lg_w_lg_w_k_bar_range47787w47788w47789w(0) OR wire_w_lg_w_k_bar_range47787w47790w(0))) WHEN niOiiO1OO = '1' ELSE wire_nli1llili_dataout; + wire_nli1lli0l_w_lg_dataout53381w(0) <= NOT wire_nli1lli0l_dataout; + wire_nli1lli0O_dataout <= (wire_w_lg_w_k_bar_range47776w47779w(0) AND (wire_nli111i1i_o AND niOiiO1lO)) WHEN niOiiO1OO = '1' ELSE wire_nli1llill_dataout; + wire_nli1lli0O_w_lg_dataout53379w(0) <= NOT wire_nli1lli0O_dataout; + wire_nli1lli1i_dataout <= niOiiO1Oi WHEN niOiiO1OO = '1' ELSE wire_nli1lliiO_dataout; + wire_nli1lli1i_w_lg_w_lg_dataout53427w53428w(0) <= wire_nli1lli1i_w_lg_dataout53427w(0) AND wire_nli1ll0OO_w_lg_dataout53423w(0); + wire_nli1lli1i_w_lg_dataout53427w(0) <= NOT wire_nli1lli1i_dataout; + wire_nli1lli1l_dataout <= wire_nl0lOlO0l_dataout WHEN niOiiO1OO = '1' ELSE wire_nli1lll1l_dataout; + wire_nli1lli1l_w_lg_dataout53836w(0) <= NOT wire_nli1lli1l_dataout; + wire_nli1lli1O_dataout <= (((wire_nl0lOOi0i_o AND niOiiO1ii) AND wire_w_lg_w_k_bar_range47794w47796w(0)) AND (wire_w_lg_w_lg_w_k_bar_range47798w47799w47800w(0) OR wire_w_lg_w_k_bar_range47798w47801w(0))) WHEN niOiiO1OO = '1' ELSE wire_nli1lll1O_dataout; + wire_nli1lli1O_w_lg_dataout53834w(0) <= NOT wire_nli1lli1O_dataout; + wire_nli1lliii_dataout <= wire_nli1llilO_dataout AND NOT(niOiiO1OO); + wire_nli1lliii_w_lg_dataout53377w(0) <= NOT wire_nli1lliii_dataout; + wire_nli1lliil_dataout <= wire_nl0ll01ll_dataout AND niOiiO1Ol; + wire_nli1lliiO_dataout <= niOiiO1Oi AND niOiiO1Ol; + wire_nli1llili_dataout <= wire_nli1lllii_dataout AND niOiiO1Ol; + wire_nli1llill_dataout <= wire_nli1lllil_dataout AND niOiiO1Ol; + wire_nli1llilO_dataout <= wire_nli1llliO_dataout AND niOiiO1Ol; + wire_nli1lll0i_dataout <= (wire_w_lg_w_lg_niOiiO0Ol47768w47769w(0) OR (wire_w_lg_niOiiO0Ol47734w(0) AND (wire_nl0Ol10il_o OR wire_nl0Ol10ii_o))) AND niOiiO01O; + wire_nli1lll1l_dataout <= niOiiO01i AND niOiiO01O; + wire_nli1lll1O_dataout <= niOiiO01l AND niOiiO01O; + wire_nli1lllii_dataout <= (((niOiiO00O AND niOiiO0ll) OR wire_nli0O1OOl_w_lg_dataout47761w(0)) OR wire_nli0O1OOl_w_lg_dataout47765w(0)) AND nl01l0lOl; + wire_nli1lllil_dataout <= (((niOiiO0lO AND niOiiO0ll) OR wire_nli0O1OOO_w_lg_dataout47743w(0)) OR wire_nli0O1OOO_w_lg_dataout47749w(0)) AND niOiiO0OO; + wire_nli1llliO_dataout <= ((niOiiO0Ol AND niOiiO0Oi) OR wire_nli0O1OOO_w_lg_dataout47737w(0)) AND niOiiO0OO; + wire_nli1lO0li_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47716w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47730w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lO0ll_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47678w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47691w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lO0lO_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47645w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47657w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lO0Oi_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47611w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47623w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lO0Ol_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47577w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47589w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lO0OO_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47546w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47555w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOi0i_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47419w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47428w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOi0l_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47389w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47399w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOi0O_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47359w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47368w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOi1i_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47514w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47524w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOi1l_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47480w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47490w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOi1O_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47450w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47460w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOiii_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47328w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47337w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOiil_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47299w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47306w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOiiO_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47268w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47276w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOili_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47235w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47243w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOill_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47204w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47214w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOilO_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47172w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47181w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOiOi_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47141w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47149w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOiOl_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47113w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47121w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOiOO_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47081w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47090w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOl0i_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46963w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46970w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOl0l_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46934w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46940w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOl0O_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46904w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46911w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOl1i_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47048w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47057w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOl1l_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO47020w(0) OR wire_nlill0Oll_w_lg_nl0iOiili47027w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOl1O_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46992w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46998w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOlii_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46876w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46883w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOlil_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46849w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46855w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOliO_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46822w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46828w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOlli_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46796w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46801w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nli1lOlll_dataout <= (wire_nlill0Oll_w_lg_nl0iOiilO46769w(0) OR wire_nlill0Oll_w_lg_nl0iOiili46774w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nlii000i_dataout <= wire_nli110ii_q(55) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oi0i; + wire_nlii000l_dataout <= wire_nli110ii_q(56) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oi0l; + wire_nlii000O_dataout <= wire_nli110ii_q(57) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oi0O; + wire_nlii001i_dataout <= wire_nli110ii_q(52) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oi1i; + wire_nlii001l_dataout <= wire_nli110ii_q(53) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oi1l; + wire_nlii001O_dataout <= wire_nli110ii_q(54) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oi1O; + wire_nlii00ii_dataout <= wire_nli110ii_q(58) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oiii; + wire_nlii00il_dataout <= wire_nli110ii_q(59) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oiil; + wire_nlii00iO_dataout <= wire_nli110ii_q(60) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OiiO; + wire_nlii00li_dataout <= wire_nli110ii_q(61) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oili; + wire_nlii00liO_dataout <= wire_nliiOiilO_w_lg_nliii110l44705w(0) OR NOT(nl0iOiO1O); + wire_nlii00ll_dataout <= wire_nli110ii_q(62) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Oill; + wire_nlii00lli_dataout <= wire_nliiOiilO_w_lg_nliii110O44704w(0) OR NOT(nl0iOiO1O); + wire_nlii00lll_dataout <= wire_nliiOiilO_w_lg_nliii11ii44703w(0) OR NOT(nl0iOiO1O); + wire_nlii00llO_dataout <= wire_nliiOiilO_w_lg_nliii11il44702w(0) OR NOT(nl0iOiO1O); + wire_nlii00lO_dataout <= wire_nli110ii_q(63) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OilO; + wire_nlii00lOi_dataout <= wire_nliiOiilO_w_lg_nliii11iO44701w(0) OR NOT(nl0iOiO1O); + wire_nlii00lOl_dataout <= wire_nliiOiilO_w_lg_nliii11li44700w(0) OR NOT(nl0iOiO1O); + wire_nlii00lOO_dataout <= wire_nliiOiilO_w_lg_nliii11ll44699w(0) OR NOT(nl0iOiO1O); + wire_nlii00O0i_dataout <= wire_nliiOiilO_w_lg_nliii11OO44695w(0) OR NOT(nl0iOiO1O); + wire_nlii00O0l_dataout <= wire_nliiOiilO_w_lg_nliii101i44694w(0) OR NOT(nl0iOiO1O); + wire_nlii00O0O_dataout <= wire_nliiOiilO_w_lg_nliii101l44693w(0) OR NOT(nl0iOiO1O); + wire_nlii00O1i_dataout <= wire_nliiOiilO_w_lg_nliii11lO44698w(0) OR NOT(nl0iOiO1O); + wire_nlii00O1l_dataout <= wire_nliiOiilO_w_lg_nliii11Oi44697w(0) OR NOT(nl0iOiO1O); + wire_nlii00O1O_dataout <= wire_nliiOiilO_w_lg_nliii11Ol44696w(0) OR NOT(nl0iOiO1O); + wire_nlii00Oi_dataout <= wire_nli110ii_q(64) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OiOi; + wire_nlii00Oii_dataout <= wire_nliiOiilO_w_lg_nliii101O44692w(0) OR NOT(nl0iOiO1O); + wire_nlii00Oil_dataout <= wire_nliiOiilO_w_lg_nliii100i44691w(0) OR NOT(nl0iOiO1O); + wire_nlii00OiO_dataout <= wire_nliiOiilO_w_lg_nliii100l44690w(0) OR NOT(nl0iOiO1O); + wire_nlii00Ol_dataout <= wire_nli110ii_q(65) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OiOl; + wire_nlii00Oli_dataout <= wire_nliiOiilO_w_lg_nlii1l1ll44689w(0) OR NOT(nl0iOiO1O); + wire_nlii00Oll_dataout <= wire_nliiOiilO_w_lg_nlii0OO0l44688w(0) OR NOT(nl0iOiO1O); + wire_nlii00OlO_dataout <= wire_nliiOiilO_w_lg_nlii0OO0O44687w(0) OR NOT(nl0iOiO1O); + wire_nlii00OO_dataout <= wire_nli110ii_q(66) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OiOO; + wire_nlii00OOi_dataout <= wire_nliiOiilO_w_lg_nlii0OOii44686w(0) OR NOT(nl0iOiO1O); + wire_nlii00OOl_dataout <= wire_nliiOiilO_w_lg_nlii0OOil44685w(0) OR NOT(nl0iOiO1O); + wire_nlii00OOO_dataout <= wire_nliiOiilO_w_lg_nlii0OOiO44684w(0) OR NOT(nl0iOiO1O); + wire_nlii010i_dataout <= wire_nli110ii_q(40) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O00i; + wire_nlii010l_dataout <= wire_nli110ii_q(41) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O00l; + wire_nlii010O_dataout <= wire_nli110ii_q(42) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O00O; + wire_nlii011i_dataout <= wire_nli110ii_q(37) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O01i; + wire_nlii011l_dataout <= wire_nli110ii_q(38) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O01l; + wire_nlii011O_dataout <= wire_nli110ii_q(39) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O01O; + wire_nlii01ii_dataout <= wire_nli110ii_q(43) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0ii; + wire_nlii01il_dataout <= wire_nli110ii_q(44) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0il; + wire_nlii01iO_dataout <= wire_nli110ii_q(45) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0iO; + wire_nlii01li_dataout <= wire_nli110ii_q(46) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0li; + wire_nlii01ll_dataout <= wire_nli110ii_q(47) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0ll; + wire_nlii01lO_dataout <= wire_nli110ii_q(48) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0lO; + wire_nlii01Oi_dataout <= wire_nli110ii_q(49) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0Oi; + wire_nlii01Ol_dataout <= wire_nli110ii_q(50) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0Ol; + wire_nlii01OO_dataout <= wire_nli110ii_q(51) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O0OO; + wire_nlii0i00i_dataout <= wire_nl1000i_w_lg_nl100O1O44667w(0) OR NOT(nl0iOiO1l); + wire_nlii0i00l_dataout <= wire_nl1000i_w_lg_nl100O0i44666w(0) OR NOT(nl0iOiO1l); + wire_nlii0i00O_dataout <= wire_nl1000i_w_lg_nl100O0l44665w(0) OR NOT(nl0iOiO1l); + wire_nlii0i01i_dataout <= wire_nliiOiilO_w_lg_nliii01Oi44670w(0) OR NOT(nl0iOiO1l); + wire_nlii0i01l_dataout <= wire_nliiOiilO_w_lg_nliii100O44669w(0) OR NOT(nl0iOiO1l); + wire_nlii0i01O_dataout <= wire_nl1000i_w_lg_nl10i10i44668w(0) OR NOT(nl0iOiO1l); + wire_nlii0i0i_dataout <= wire_nli110ii_q(70) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Ol0i; + wire_nlii0i0ii_dataout <= wire_nl1000i_w_lg_nl100O0O44664w(0) OR NOT(nl0iOiO1l); + wire_nlii0i0il_dataout <= wire_nlill0Oll_w_lg_nliii000i44663w(0) OR NOT(nl0iOiO1i); + wire_nlii0i0iO_dataout <= wire_nlill0Oll_w_lg_nliii0lOO44662w(0) OR NOT(nl0iOiO1i); + wire_nlii0i0l_dataout <= wire_nli110ii_q(71) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Ol0l; + wire_nlii0i0li_dataout <= wire_nlill0Oll_w_lg_nliii0O1i44661w(0) OR NOT(nl0iOiO1i); + wire_nlii0i0ll_dataout <= wire_nliiiilOO_w_lg_nliii0O1l44660w(0) OR NOT(niOiliO0O); + wire_nlii0i0lO_dataout <= wire_nliiiilOO_w_lg_nliii0OOi44659w(0) OR NOT(niOiliO0O); + wire_nlii0i0O_dataout <= wire_nli110ii_q(72) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Ol0O; + wire_nlii0i0Oi_dataout <= wire_nliiiilOO_w_lg_nliii0OOl44658w(0) OR NOT(niOiliO0O); + wire_nlii0i0Ol_dataout <= wire_nliiiilOO_w_lg_nliii0OOO44657w(0) OR NOT(niOiliO0O); + wire_nlii0i0OO_dataout <= wire_nliiiilOO_w_lg_nliiii11i44656w(0) OR NOT(niOiliO0O); + wire_nlii0i10i_dataout <= wire_nliiOiilO_w_lg_nlii0OOOi44680w(0) OR NOT(nl0iOiO1O); + wire_nlii0i10l_dataout <= wire_nliiOiilO_w_lg_nlii0OOOl44679w(0) OR NOT(nl0iOiO1O); + wire_nlii0i10O_dataout <= wire_nliiOiilO_w_lg_nlii0OOOO44678w(0) OR NOT(nl0iOiO1O); + wire_nlii0i11i_dataout <= wire_nliiOiilO_w_lg_nlii0OOli44683w(0) OR NOT(nl0iOiO1O); + wire_nlii0i11l_dataout <= wire_nliiOiilO_w_lg_nlii0OOll44682w(0) OR NOT(nl0iOiO1O); + wire_nlii0i11O_dataout <= wire_nliiOiilO_w_lg_nlii0OOlO44681w(0) OR NOT(nl0iOiO1O); + wire_nlii0i1i_dataout <= wire_nli110ii_q(67) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Ol1i; + wire_nlii0i1ii_dataout <= wire_nliiOiilO_w_lg_nliii111i44677w(0) OR NOT(nl0iOiO1O); + wire_nlii0i1il_dataout <= wire_nliiOiilO_w_lg_nliii111l44676w(0) OR NOT(nl0iOiO1O); + wire_nlii0i1iO_dataout <= wire_nliiOiilO_w_lg_nliii111O44675w(0) OR NOT(nl0iOiO1O); + wire_nlii0i1l_dataout <= wire_nli110ii_q(68) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Ol1l; + wire_nlii0i1li_dataout <= wire_nliiOiilO_w_lg_nliii110i44674w(0) OR NOT(nl0iOiO1O); + wire_nlii0i1ll_dataout <= wire_nliiOiilO_w_lg_nliii001O44476w(0) OR NOT(nl0iOiO1l); + wire_nlii0i1lO_dataout <= wire_nliiOiilO_w_lg_nliii001l44673w(0) OR NOT(nl0iOiO1l); + wire_nlii0i1O_dataout <= wire_nli110ii_q(69) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Ol1O; + wire_nlii0i1Oi_dataout <= wire_nliiOiilO_w_lg_nliii001i44467w(0) OR NOT(nl0iOiO1l); + wire_nlii0i1Ol_dataout <= wire_nliiOiilO_w_lg_nliii01OO44672w(0) OR NOT(nl0iOiO1l); + wire_nlii0i1OO_dataout <= wire_nliiOiilO_w_lg_nliii01Ol44671w(0) OR NOT(nl0iOiO1l); + wire_nlii0ii0i_dataout <= wire_nliiiilOO_w_lg_nliiii10l44652w(0) OR NOT(niOiliO0O); + wire_nlii0ii0l_dataout <= wire_nliiiilOO_w_lg_nliiii10O44651w(0) OR NOT(niOiliO0O); + wire_nlii0ii0O_dataout <= wire_nliiiilOO_w_lg_nliiii1ii44650w(0) OR NOT(niOiliO0O); + wire_nlii0ii1i_dataout <= wire_nliiiilOO_w_lg_nliiii11l44655w(0) OR NOT(niOiliO0O); + wire_nlii0ii1l_dataout <= wire_nliiiilOO_w_lg_nliiii11O44654w(0) OR NOT(niOiliO0O); + wire_nlii0ii1O_dataout <= wire_nliiiilOO_w_lg_nliiii10i44653w(0) OR NOT(niOiliO0O); + wire_nlii0iii_dataout <= wire_nli110ii_q(73) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Olii; + wire_nlii0iiii_dataout <= wire_nliiiilOO_w_lg_nliiii1il44649w(0) OR NOT(niOiliO0O); + wire_nlii0iiil_dataout <= wire_nliiiilOO_w_lg_nliiii1iO44648w(0) OR NOT(niOiliO0O); + wire_nlii0iiiO_dataout <= wire_nliiiilOO_w_lg_nliiii1li44647w(0) OR NOT(niOiliO0O); + wire_nlii0iil_dataout <= wire_nli110ii_q(74) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Olil; + wire_nlii0iili_dataout <= wire_nliiiilOO_w_lg_nliiii1ll44646w(0) OR NOT(niOiliO0O); + wire_nlii0iill_dataout <= wire_nliiiilOO_w_lg_nliiii1lO44645w(0) OR NOT(niOiliO0O); + wire_nlii0iilO_dataout <= wire_nliiiilOO_w_lg_nliiii1Oi44644w(0) OR NOT(niOiliO0O); + wire_nlii0iiO_dataout <= wire_nli110ii_q(75) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OliO; + wire_nlii0iiOi_dataout <= wire_nliiiilOO_w_lg_nliiii1Ol44643w(0) OR NOT(niOiliO0O); + wire_nlii0iiOl_dataout <= wire_nliiiilOO_w_lg_nliiii1OO44642w(0) OR NOT(niOiliO0O); + wire_nlii0iiOO_dataout <= wire_nliiiilOO_w_lg_nliiii01i44641w(0) OR NOT(niOiliO0O); + wire_nlii0il0i_dataout <= wire_nliiiilOO_w_lg_nliiii00l44637w(0) OR NOT(niOiliO0O); + wire_nlii0il0l_dataout <= wire_nliiiilOO_w_lg_nliiii00O44636w(0) OR NOT(niOiliO0O); + wire_nlii0il0O_dataout <= wire_nliiiilOO_w_lg_nliiii0ii44635w(0) OR NOT(niOiliO0O); + wire_nlii0il1i_dataout <= wire_nliiiilOO_w_lg_nliiii01l44640w(0) OR NOT(niOiliO0O); + wire_nlii0il1l_dataout <= wire_nliiiilOO_w_lg_nliiii01O44639w(0) OR NOT(niOiliO0O); + wire_nlii0il1O_dataout <= wire_nliiiilOO_w_lg_nliiii00i44638w(0) OR NOT(niOiliO0O); + wire_nlii0ili_dataout <= wire_nli110ii_q(76) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Olli; + wire_nlii0ilii_dataout <= wire_nliiiilOO_w_lg_nliiii0il44634w(0) OR NOT(niOiliO0O); + wire_nlii0ilil_dataout <= wire_nliiiilOO_w_lg_nliiii0iO44633w(0) OR NOT(niOiliO0O); + wire_nlii0iliO_dataout <= wire_nliiiilOO_w_lg_nliiii0li44632w(0) OR NOT(niOiliO0O); + wire_nlii0ill_dataout <= wire_nli110ii_q(77) WHEN wire_nli1l0il_dataout = '1' ELSE nli1Olll; + wire_nlii0illi_dataout <= wire_nliiiilOO_w_lg_nliiii0ll44631w(0) OR NOT(niOiliO0O); + wire_nlii0illl_dataout <= wire_nliiiilOO_w_lg_nliiii0lO44630w(0) OR NOT(niOiliO0O); + wire_nlii0illO_dataout <= wire_nliiiilOO_w_lg_nliiii0Oi44629w(0) OR NOT(niOiliO0O); + wire_nlii0ilO_dataout <= wire_nli110ii_q(78) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OllO; + wire_nlii0ilOl_dataout <= wire_nliiiilOO_w_lg_nliiii0Ol44627w(0) OR NOT(niOiliOii); + wire_nlii0ilOO_dataout <= wire_nliiiilOO_w_lg_nliiii0OO44626w(0) OR NOT(niOiliOii); + wire_nlii0iO0i_dataout <= wire_nliiiilOO_w_lg_nliiiii0i44622w(0) OR NOT(niOiliOii); + wire_nlii0iO0l_dataout <= wire_nliiiilOO_w_lg_nliiiii0l44621w(0) OR NOT(niOiliOii); + wire_nlii0iO0O_dataout <= wire_nliiiilOO_w_lg_nliiiii0O44620w(0) OR NOT(niOiliOii); + wire_nlii0iO1i_dataout <= wire_nliiiilOO_w_lg_nliiiii1i44625w(0) OR NOT(niOiliOii); + wire_nlii0iO1l_dataout <= wire_nliiiilOO_w_lg_nliiiii1l44624w(0) OR NOT(niOiliOii); + wire_nlii0iO1O_dataout <= wire_nliiiilOO_w_lg_nliiiii1O44623w(0) OR NOT(niOiliOii); + wire_nlii0iOi_dataout <= wire_nli110ii_q(79) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OlOi; + wire_nlii0iOii_dataout <= wire_nliiiilOO_w_lg_nliiiiiii44619w(0) OR NOT(niOiliOii); + wire_nlii0iOil_dataout <= wire_nliiiilOO_w_lg_nliiiiiil44618w(0) OR NOT(niOiliOii); + wire_nlii0iOiO_dataout <= wire_nliiiilOO_w_lg_nliiiiiiO44617w(0) OR NOT(niOiliOii); + wire_nlii0iOl_dataout <= wire_nli110ii_q(80) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OlOl; + wire_nlii0iOli_dataout <= wire_nliiiilOO_w_lg_nliiiiili44616w(0) OR NOT(niOiliOii); + wire_nlii0iOll_dataout <= wire_nliiiilOO_w_lg_nliiiiill44615w(0) OR NOT(niOiliOii); + wire_nlii0iOlO_dataout <= wire_nliiiilOO_w_lg_nliiiiilO44614w(0) OR NOT(niOiliOii); + wire_nlii0iOO_dataout <= wire_nli110ii_q(81) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OlOO; + wire_nlii0iOOi_dataout <= wire_nliiiilOO_w_lg_nliiiiiOi44613w(0) OR NOT(niOiliOii); + wire_nlii0iOOl_dataout <= wire_nliiiilOO_w_lg_nliiiiiOl44612w(0) OR NOT(niOiliOii); + wire_nlii0iOOO_dataout <= wire_nliiiilOO_w_lg_nliiiiiOO44611w(0) OR NOT(niOiliOii); + wire_nlii0l00i_dataout <= wire_nliiOiilO_w_lg_nliiiiO0i44592w(0) OR NOT(niOiliOil); + wire_nlii0l00l_dataout <= wire_nliiOiilO_w_lg_nliiiiO0l44591w(0) OR NOT(niOiliOil); + wire_nlii0l00O_dataout <= wire_nliiOiilO_w_lg_nliiiiO0O44590w(0) OR NOT(niOiliOil); + wire_nlii0l01l_dataout <= wire_nliiOiilO_w_lg_nliiiiO1l44594w(0) OR NOT(niOiliOil); + wire_nlii0l01O_dataout <= wire_nliiOiilO_w_lg_nliiiiO1O44593w(0) OR NOT(niOiliOil); + wire_nlii0l0i_dataout <= wire_nli110ii_q(85) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OO0i; + wire_nlii0l0ii_dataout <= wire_nliiOiilO_w_lg_nliiiiOii44589w(0) OR NOT(niOiliOil); + wire_nlii0l0il_dataout <= wire_nliiOiilO_w_lg_nliiiiOil44588w(0) OR NOT(niOiliOil); + wire_nlii0l0iO_dataout <= wire_nliiOiilO_w_lg_nliiiiOiO44587w(0) OR NOT(niOiliOil); + wire_nlii0l0l_dataout <= wire_nli110ii_q(86) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OO0l; + wire_nlii0l0li_dataout <= wire_nliiOiilO_w_lg_nliiiiOli44586w(0) OR NOT(niOiliOil); + wire_nlii0l0ll_dataout <= wire_nliiOiilO_w_lg_nliiiiOll44585w(0) OR NOT(niOiliOil); + wire_nlii0l0lO_dataout <= wire_nliiOiilO_w_lg_nliiiiOlO44584w(0) OR NOT(niOiliOil); + wire_nlii0l0O_dataout <= wire_nli110ii_q(87) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OO0O; + wire_nlii0l0Oi_dataout <= wire_nliiOiilO_w_lg_nliiiiOOi44583w(0) OR NOT(niOiliOil); + wire_nlii0l0Ol_dataout <= wire_nliiOiilO_w_lg_nliiiiOOl44582w(0) OR NOT(niOiliOil); + wire_nlii0l0OO_dataout <= wire_nliiOiilO_w_lg_nliiiiOOO44581w(0) OR NOT(niOiliOil); + wire_nlii0l10i_dataout <= wire_nliiiilOO_w_lg_nliiiil0i44607w(0) OR NOT(niOiliOii); + wire_nlii0l10l_dataout <= wire_nliiiilOO_w_lg_nliiiil0l44606w(0) OR NOT(niOiliOii); + wire_nlii0l10O_dataout <= wire_nliiiilOO_w_lg_nliiiil0O44605w(0) OR NOT(niOiliOii); + wire_nlii0l11i_dataout <= wire_nliiiilOO_w_lg_nliiiil1i44610w(0) OR NOT(niOiliOii); + wire_nlii0l11l_dataout <= wire_nliiiilOO_w_lg_nliiiil1l44609w(0) OR NOT(niOiliOii); + wire_nlii0l11O_dataout <= wire_nliiiilOO_w_lg_nliiiil1O44608w(0) OR NOT(niOiliOii); + wire_nlii0l1i_dataout <= wire_nli110ii_q(82) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OO1i; + wire_nlii0l1ii_dataout <= wire_nliiiilOO_w_lg_nliiiilii44604w(0) OR NOT(niOiliOii); + wire_nlii0l1il_dataout <= wire_nliiiilOO_w_lg_nliiiilil44603w(0) OR NOT(niOiliOii); + wire_nlii0l1iO_dataout <= wire_nliiiilOO_w_lg_nliiiiliO44602w(0) OR NOT(niOiliOii); + wire_nlii0l1l_dataout <= wire_nli110ii_q(83) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OO1l; + wire_nlii0l1li_dataout <= wire_nliiiilOO_w_lg_nliiiilli44601w(0) OR NOT(niOiliOii); + wire_nlii0l1ll_dataout <= wire_nliiiilOO_w_lg_nliiiilll44600w(0) OR NOT(niOiliOii); + wire_nlii0l1lO_dataout <= wire_nliiiilOO_w_lg_nliiiillO44599w(0) OR NOT(niOiliOii); + wire_nlii0l1O_dataout <= wire_nli110ii_q(84) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OO1O; + wire_nlii0l1Oi_dataout <= wire_nliiiilOO_w_lg_nliiiilOi44598w(0) OR NOT(niOiliOii); + wire_nlii0l1Ol_dataout <= wire_nliiiilOO_w_lg_nliiiilOl44597w(0) OR NOT(niOiliOii); + wire_nlii0l1OO_dataout <= wire_nliiiilOO_w_lg_nliiiiO1i44596w(0) OR NOT(niOiliOii); + wire_nlii0li0i_dataout <= wire_nliiOiilO_w_lg_nliiil10i44577w(0) OR NOT(niOiliOil); + wire_nlii0li0l_dataout <= wire_nliiOiilO_w_lg_nliiil10l44576w(0) OR NOT(niOiliOil); + wire_nlii0li0O_dataout <= wire_nliiOiilO_w_lg_nliiil10O44575w(0) OR NOT(niOiliOil); + wire_nlii0li1i_dataout <= wire_nliiOiilO_w_lg_nliiil11i44580w(0) OR NOT(niOiliOil); + wire_nlii0li1l_dataout <= wire_nliiOiilO_w_lg_nliiil11l44579w(0) OR NOT(niOiliOil); + wire_nlii0li1O_dataout <= wire_nliiOiilO_w_lg_nliiil11O44578w(0) OR NOT(niOiliOil); + wire_nlii0lii_dataout <= wire_nli110ii_q(88) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOii; + wire_nlii0liii_dataout <= wire_nliiOiilO_w_lg_nliiil1ii44574w(0) OR NOT(niOiliOil); + wire_nlii0liil_dataout <= wire_nliiOiilO_w_lg_nliiil1il44573w(0) OR NOT(niOiliOil); + wire_nlii0liiO_dataout <= wire_nliiOiilO_w_lg_nliiil1iO44572w(0) OR NOT(niOiliOil); + wire_nlii0lil_dataout <= wire_nli110ii_q(89) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOil; + wire_nlii0lili_dataout <= wire_nliiOiilO_w_lg_nliiil1li44571w(0) OR NOT(niOiliOil); + wire_nlii0lill_dataout <= wire_nliiOiilO_w_lg_nliiil1ll44570w(0) OR NOT(niOiliOil); + wire_nlii0lilO_dataout <= wire_nliiOiilO_w_lg_nliiil1lO44569w(0) OR NOT(niOiliOil); + wire_nlii0liO_dataout <= wire_nli110ii_q(90) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOiO; + wire_nlii0liOi_dataout <= wire_nliiOiilO_w_lg_nliiil1Oi44568w(0) OR NOT(niOiliOil); + wire_nlii0liOl_dataout <= wire_nliiOiilO_w_lg_nliiil1Ol44567w(0) OR NOT(niOiliOil); + wire_nlii0liOO_dataout <= wire_nliiOiilO_w_lg_nliiil1OO44566w(0) OR NOT(niOiliOil); + wire_nlii0ll0l_dataout <= wire_nliiOiilO_w_lg_nliiil00i44561w(0) OR NOT(niOiliOiO); + wire_nlii0ll0O_dataout <= wire_nliiOiilO_w_lg_nliiil00l44560w(0) OR NOT(niOiliOiO); + wire_nlii0ll1i_dataout <= wire_nliiOiilO_w_lg_nliiil01i44565w(0) OR NOT(niOiliOil); + wire_nlii0ll1l_dataout <= wire_nliiOiilO_w_lg_nliiil01l44564w(0) OR NOT(niOiliOil); + wire_nlii0ll1O_dataout <= wire_nliiOiilO_w_lg_nliiil01O44563w(0) OR NOT(niOiliOil); + wire_nlii0lli_dataout <= wire_nli110ii_q(91) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOli; + wire_nlii0llii_dataout <= wire_nliiOiilO_w_lg_nliiil00O44559w(0) OR NOT(niOiliOiO); + wire_nlii0llil_dataout <= wire_nliiOiilO_w_lg_nliiil0ii44558w(0) OR NOT(niOiliOiO); + wire_nlii0lliO_dataout <= wire_nliiOiilO_w_lg_nliiil0il44557w(0) OR NOT(niOiliOiO); + wire_nlii0lll_dataout <= wire_nli110ii_q(92) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOll; + wire_nlii0llli_dataout <= wire_nliiOiilO_w_lg_nliiil0iO44556w(0) OR NOT(niOiliOiO); + wire_nlii0llll_dataout <= wire_nliiOiilO_w_lg_nliiil0li44555w(0) OR NOT(niOiliOiO); + wire_nlii0lllO_dataout <= wire_nliiOiilO_w_lg_nliiil0ll44554w(0) OR NOT(niOiliOiO); + wire_nlii0llO_dataout <= wire_nli110ii_q(93) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOlO; + wire_nlii0llOi_dataout <= wire_nliiOiilO_w_lg_nliiil0lO44553w(0) OR NOT(niOiliOiO); + wire_nlii0llOl_dataout <= wire_nliiOiilO_w_lg_nliiil0Oi44552w(0) OR NOT(niOiliOiO); + wire_nlii0llOO_dataout <= wire_nliiOiilO_w_lg_nliiil0Ol44551w(0) OR NOT(niOiliOiO); + wire_nlii0lO0i_dataout <= wire_nliiOiilO_w_lg_nliiili1O44547w(0) OR NOT(niOiliOiO); + wire_nlii0lO0l_dataout <= wire_nliiOiilO_w_lg_nliiili0i44546w(0) OR NOT(niOiliOiO); + wire_nlii0lO0O_dataout <= wire_nliiOiilO_w_lg_nliiili0l44545w(0) OR NOT(niOiliOiO); + wire_nlii0lO1i_dataout <= wire_nliiOiilO_w_lg_nliiil0OO44550w(0) OR NOT(niOiliOiO); + wire_nlii0lO1l_dataout <= wire_nliiOiilO_w_lg_nliiili1i44549w(0) OR NOT(niOiliOiO); + wire_nlii0lO1O_dataout <= wire_nliiOiilO_w_lg_nliiili1l44548w(0) OR NOT(niOiliOiO); + wire_nlii0lOi_dataout <= wire_nli110ii_q(94) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOOi; + wire_nlii0lOii_dataout <= wire_nliiOiilO_w_lg_nliiili0O44544w(0) OR NOT(niOiliOiO); + wire_nlii0lOil_dataout <= wire_nliiOiilO_w_lg_nliiiliii44543w(0) OR NOT(niOiliOiO); + wire_nlii0lOiO_dataout <= wire_nliiOiilO_w_lg_nliiiliil44542w(0) OR NOT(niOiliOiO); + wire_nlii0lOl_dataout <= wire_nli110ii_q(95) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOOl; + wire_nlii0lOli_dataout <= wire_nliiOiilO_w_lg_nliiiliiO44541w(0) OR NOT(niOiliOiO); + wire_nlii0lOll_dataout <= wire_nliiOiilO_w_lg_nliiilili44540w(0) OR NOT(niOiliOiO); + wire_nlii0lOlO_dataout <= wire_nliiOiilO_w_lg_nliiilill44539w(0) OR NOT(niOiliOiO); + wire_nlii0lOO_dataout <= wire_nli110ii_q(96) WHEN wire_nli1l0il_dataout = '1' ELSE nli1OOOO; + wire_nlii0lOOi_dataout <= wire_nliiOiilO_w_lg_nliiililO44538w(0) OR NOT(niOiliOiO); + wire_nlii0lOOl_dataout <= wire_nliiOiilO_w_lg_nliiiliOi44537w(0) OR NOT(niOiliOiO); + wire_nlii0lOOO_dataout <= wire_nliiOiilO_w_lg_nliiiliOl44536w(0) OR NOT(niOiliOiO); + wire_nlii0O00i_dataout <= wire_nliiOiilO_w_lg_nliiO1lii44517w(0) OR NOT(nl0iOilli); + wire_nlii0O00l_dataout <= wire_nliiOiilO_w_lg_nliiO1l0O44516w(0) OR NOT(nl0iOilli); + wire_nlii0O00O_dataout <= wire_nliiOiilO_w_lg_nliiO1l0l44515w(0) OR NOT(nl0iOilli); + wire_nlii0O01i_dataout <= wire_nliiOiilO_w_lg_nliiill0O44520w(0) OR NOT(nl0iOilll); + wire_nlii0O01l_dataout <= wire_nliiOiilO_w_lg_nliiO1liO44519w(0) OR NOT(nl0iOilli); + wire_nlii0O01O_dataout <= wire_nliiOiilO_w_lg_nliiO1lil44518w(0) OR NOT(nl0iOilli); + wire_nlii0O0i_dataout <= wire_nli110ii_q(100) WHEN wire_nli1l0il_dataout = '1' ELSE nli0110i; + wire_nlii0O0ii_dataout <= wire_nliiO0iOl_w_lg_nliiO10ii44514w(0) OR NOT(nl0iOilli); + wire_nlii0O0il_dataout <= wire_nliiOiilO_w_lg_nliiO011i44513w(0) OR NOT(nl0iOiliO); + wire_nlii0O0iO_dataout <= wire_nliiOiilO_w_lg_nliiO1OOO44512w(0) OR NOT(nl0iOiliO); + wire_nlii0O0l_dataout <= wire_nli110ii_q(101) WHEN wire_nli1l0il_dataout = '1' ELSE nli0110l; + wire_nlii0O0li_dataout <= wire_nliiOiilO_w_lg_nliiO1OOl44511w(0) OR NOT(nl0iOiliO); + wire_nlii0O0ll_dataout <= wire_nliiOiilO_w_lg_nliiO1OOi44510w(0) OR NOT(nl0iOiliO); + wire_nlii0O0lO_dataout <= wire_nliiOiilO_w_lg_nliiO1OlO44509w(0) OR NOT(nl0iOiliO); + wire_nlii0O0O_dataout <= wire_nli110ii_q(102) WHEN wire_nli1l0il_dataout = '1' ELSE nli0110O; + wire_nlii0O0Oi_dataout <= wire_nliiOiilO_w_lg_nliiO1lli44508w(0) OR NOT(nl0iOiliO); + wire_nlii0O0Ol_dataout <= wire_nliiO0iOl_w_lg_nliiO0iOO44507w(0) OR NOT(nl0iOilil); + wire_nlii0O0OO_dataout <= wire_nliiO0iOl_w_lg_nliiO0iOi44506w(0) OR NOT(nl0iOilil); + wire_nlii0O10i_dataout <= wire_nliiOiilO_w_lg_nliiill1O44532w(0) OR NOT(niOiliOiO); + wire_nlii0O10l_dataout <= wire_nliiOiilO_w_lg_nliiill0i44531w(0) OR NOT(niOiliOiO); + wire_nlii0O10O_dataout <= wire_nliiOiilO_w_lg_nliiill0l44530w(0) OR NOT(niOiliOiO); + wire_nlii0O11i_dataout <= wire_nliiOiilO_w_lg_nliiiliOO44535w(0) OR NOT(niOiliOiO); + wire_nlii0O11l_dataout <= wire_nliiOiilO_w_lg_nliiill1i44534w(0) OR NOT(niOiliOiO); + wire_nlii0O11O_dataout <= wire_nliiOiilO_w_lg_nliiill1l44533w(0) OR NOT(niOiliOiO); + wire_nlii0O1i_dataout <= wire_nli110ii_q(97) WHEN wire_nli1l0il_dataout = '1' ELSE nli0111i; + wire_nlii0O1il_dataout <= wire_nliiOiilO_w_lg_nliiO101i44528w(0) OR NOT(nl0iOilll); + wire_nlii0O1iO_dataout <= wire_nliiOiilO_w_lg_nliiO101l44527w(0) OR NOT(nl0iOilll); + wire_nlii0O1l_dataout <= wire_nli110ii_q(98) WHEN wire_nli1l0il_dataout = '1' ELSE nli0111l; + wire_nlii0O1li_dataout <= wire_nliiOiilO_w_lg_nliiO101O44526w(0) OR NOT(nl0iOilll); + wire_nlii0O1ll_dataout <= wire_nliiOiilO_w_lg_nliiO100i44525w(0) OR NOT(nl0iOilll); + wire_nlii0O1lO_dataout <= wire_nliiOiilO_w_lg_nliiO100l44524w(0) OR NOT(nl0iOilll); + wire_nlii0O1O_dataout <= wire_nli110ii_q(99) WHEN wire_nli1l0il_dataout = '1' ELSE nli0111O; + wire_nlii0O1Oi_dataout <= (NOT k_conf(216)) OR NOT(nl0iOilll); + wire_nlii0O1Ol_dataout <= wire_nliiOiilO_w_lg_nliiO11OO44522w(0) OR NOT(nl0iOilll); + wire_nlii0O1OO_dataout <= (NOT k_conf(217)) OR NOT(nl0iOilll); + wire_nlii0Oi0i_dataout <= wire_nliiOiilO_w_lg_nliiO0iiO44289w(0) OR NOT(nl0iOilil); + wire_nlii0Oi0l_dataout <= wire_nliiOiilO_w_lg_nliiO0iil44294w(0) OR NOT(nl0iOilil); + wire_nlii0Oi0O_dataout <= wire_nliiOiilO_w_lg_nliiO0iii44300w(0) OR NOT(nl0iOilil); + wire_nlii0Oi1i_dataout <= wire_nliiO0iOl_w_lg_nliiO0ilO44505w(0) OR NOT(nl0iOilil); + wire_nlii0Oi1l_dataout <= wire_nliiOiilO_w_lg_nliiO0ill44279w(0) OR NOT(nl0iOilil); + wire_nlii0Oi1O_dataout <= wire_nliiO0iOl_w_lg_nliiO0ili44284w(0) OR NOT(nl0iOilil); + wire_nlii0Oii_dataout <= wire_nli110ii_q(103) WHEN wire_nli1l0il_dataout = '1' ELSE nli011ii; + wire_nlii0Oiii_dataout <= wire_nliiO0iOl_w_lg_nliiO0i0O44504w(0) OR NOT(nl0iOilil); + wire_nlii0Oiil_dataout <= wire_nliiO0iOl_w_lg_nliiO0i0l44503w(0) OR NOT(nl0iOilil); + wire_nlii0OiiO_dataout <= wire_nliiOiilO_w_lg_nliiO0i0i44311w(0) OR NOT(nl0iOilil); + wire_nlii0Oil_dataout <= wire_nli110ii_q(104) WHEN wire_nli1l0il_dataout = '1' ELSE nli011il; + wire_nlii0Oili_dataout <= wire_nliiOiilO_w_lg_nliiO011l44316w(0) OR NOT(nl0iOilil); + wire_nlii0Oill_dataout <= wire_nliiOiilO_w_lg_nliiOi11i44502w(0) OR NOT(nl0iOilii); + wire_nlii0OilO_dataout <= wire_nliiOiilO_w_lg_nliiO0OOO44501w(0) OR NOT(nl0iOilii); + wire_nlii0OiO_dataout <= wire_nli110ii_q(105) WHEN wire_nli1l0il_dataout = '1' ELSE nli011iO; + wire_nlii0OiOi_dataout <= wire_nliiOiilO_w_lg_nliiO0OOl44500w(0) OR NOT(nl0iOilii); + wire_nlii0OiOl_dataout <= wire_nliiOiilO_w_lg_nliiO0OOi44499w(0) OR NOT(nl0iOilii); + wire_nlii0OiOO_dataout <= wire_nliiOiilO_w_lg_nliiO0OlO44498w(0) OR NOT(nl0iOilii); + wire_nlii0Ol0i_dataout <= wire_nliiOiilO_w_lg_nliiO0Oil44494w(0) OR NOT(nl0iOilii); + wire_nlii0Ol0l_dataout <= wire_nliiOiilO_w_lg_nliiO0Oii44493w(0) OR NOT(nl0iOilii); + wire_nlii0Ol0O_dataout <= wire_nliiOiilO_w_lg_nliiO0O0O44492w(0) OR NOT(nl0iOilii); + wire_nlii0Ol1i_dataout <= wire_nliiOiilO_w_lg_nliiO0Oll44497w(0) OR NOT(nl0iOilii); + wire_nlii0Ol1l_dataout <= wire_nliiOiilO_w_lg_nliiO0Oli44496w(0) OR NOT(nl0iOilii); + wire_nlii0Ol1O_dataout <= wire_nliiOiilO_w_lg_nliiO0OiO44495w(0) OR NOT(nl0iOilii); + wire_nlii0Oli_dataout <= wire_nli110ii_q(106) WHEN wire_nli1l0il_dataout = '1' ELSE nli011li; + wire_nlii0Olii_dataout <= wire_nliiOiilO_w_lg_nliiO0l1i44491w(0) OR NOT(nl0iOilii); + wire_nlii0Olil_dataout <= wire_nliiOiilO_w_lg_nliiOiiOi44490w(0) OR NOT(nl0iOil0O); + wire_nlii0OliO_dataout <= wire_nliiOiilO_w_lg_nliiOiill44489w(0) OR NOT(nl0iOil0O); + wire_nlii0Oll_dataout <= wire_nli110ii_q(107) WHEN wire_nli1l0il_dataout = '1' ELSE nli011ll; + wire_nlii0Olli_dataout <= wire_nliiOiilO_w_lg_nliiOiili44488w(0) OR NOT(nl0iOil0O); + wire_nlii0Olll_dataout <= wire_nliiOiilO_w_lg_nliiOiiiO44487w(0) OR NOT(nl0iOil0O); + wire_nlii0OllO_dataout <= wire_nliiOiilO_w_lg_nliiOiiil44486w(0) OR NOT(nl0iOil0O); + wire_nlii0OlO_dataout <= wire_nli110ii_q(108) WHEN wire_nli1l0il_dataout = '1' ELSE nli011lO; + wire_nlii0OlOi_dataout <= wire_w_lg_niOilll1i44485w(0) OR NOT(nl0iOil0O); + wire_nlii0OlOl_dataout <= wire_nliiOiilO_w_lg_nliiOii0l44484w(0) OR NOT(nl0iOil0O); + wire_nlii0OlOO_dataout <= wire_nliiOiilO_w_lg_nliiOii0i44483w(0) OR NOT(nl0iOil0O); + wire_nlii0OO0i_dataout <= wire_nliiOiilO_w_lg_nliiOi11l44479w(0) OR NOT(nl0iOil0O); + wire_nlii0OO1i_dataout <= wire_nliiOiilO_w_lg_nliiOii1O44482w(0) OR NOT(nl0iOil0O); + wire_nlii0OO1l_dataout <= wire_nliiOiilO_w_lg_nliiOii1l44481w(0) OR NOT(nl0iOil0O); + wire_nlii0OO1O_dataout <= wire_nliiOiilO_w_lg_nliiOii1i44480w(0) OR NOT(nl0iOil0O); + wire_nlii0OOi_dataout <= wire_nli110ii_q(109) WHEN wire_nli1l0il_dataout = '1' ELSE nli011Oi; + wire_nlii0OOl_dataout <= wire_nli110ii_q(110) WHEN wire_nli1l0il_dataout = '1' ELSE nli011Ol; + wire_nlii0OOO_dataout <= wire_nli110ii_q(111) WHEN wire_nli1l0il_dataout = '1' ELSE nli011OO; + wire_nlii100i_dataout <= wire_nliiii0O_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1liOl; + wire_nlii100iO_dataout <= wire_nlii100li_dataout AND (nl01l0lii AND nli0OOOlO); + wire_nlii100l_dataout <= wire_nliiiiii_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1liOO; + wire_nlii100li_dataout <= wire_nlii100ll_dataout OR NOT(niOillO1i); + wire_nlii100ll_dataout <= wire_nlii100Oi_dataout WHEN (nl01l0lOi OR nl01l0liO) = '1' ELSE wire_nlii100lO_dataout; + wire_nlii100lO_dataout <= nlii11i0O OR ((wire_nlill0Oll_w_lg_nlill1lii44977w(0) AND wire_nlill0Oll_w_lg_nlill1l0O44978w(0)) AND wire_nlill0Oll_w_lg_nlill1i0O44980w(0)); + wire_nlii100O_dataout <= wire_nliiiiil_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01i1l; + wire_nlii100Oi_dataout <= nlii11i0O OR ((wire_nlill0Oll_w_lg_nli0OOOOO44972w(0) AND wire_nlill0Oll_w_lg_nli0OOOOl44973w(0)) AND wire_nlill0Oll_w_lg_nli0OOOOi44975w(0)); + wire_nlii1010i_dataout <= (niOililOi AND nlii11i1i) WHEN niOililii = '1' ELSE nlii110OO; + wire_nlii1010l_dataout <= wire_nlii101ii_dataout WHEN niOililii = '1' ELSE nlii11i1i; + wire_nlii1011i_dataout <= (nl01l0lii AND (wire_nlill0Oll_w_lg_nl01l0liO44990w(0) AND (nl01l0l0l AND niOililOi))) AND NOT(wire_niO01O0O_dataout); + wire_nlii1011l_dataout <= (nl01l0lii AND niOililli) AND NOT(wire_niO01O0O_dataout); + wire_nlii1011O_dataout <= wire_nlii100iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii101i_dataout <= wire_nliiii1O_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1lill; + wire_nlii101ii_dataout <= wire_nlii101il_dataout OR ((wire_nilOi0lO_dataout AND (niOill1iO AND niOililiO)) AND niOililil); + wire_nlii101il_dataout <= nlii11i1i AND NOT((wire_nilOi00l_dataout AND wire_nilOi00i_dataout)); + wire_nlii101l_dataout <= wire_nliiii0i_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1lilO; + wire_nlii101O_dataout <= wire_nliiii0l_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1liOi; + wire_nlii10i0i_dataout <= wire_nilOl11O_dataout WHEN niOililll = '1' ELSE nlii1111i; + wire_nlii10i0l_dataout <= wire_nilOl10i_dataout WHEN niOililll = '1' ELSE nlii1111l; + wire_nlii10i0O_dataout <= wire_nilOl10l_dataout WHEN niOililll = '1' ELSE nlii1111O; + wire_nlii10i1i_dataout <= wire_nilOiOOO_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nli0OOOOi; + wire_nlii10i1l_dataout <= wire_nilOl11i_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nli0OOOOl; + wire_nlii10i1O_dataout <= wire_nilOl11l_dataout WHEN wire_nilOi0iO_dataout = '1' ELSE nli0OOOOO; + wire_nlii10ii_dataout <= wire_nliiiiiO_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01i1O; + wire_nlii10iii_dataout <= wire_nilOl10O_dataout WHEN niOililll = '1' ELSE nlii1110i; + wire_nlii10iil_dataout <= wire_nilOl1ii_dataout WHEN niOililll = '1' ELSE nlii1110l; + wire_nlii10iiO_dataout <= wire_nilOl1il_dataout WHEN niOililll = '1' ELSE nlii1110O; + wire_nlii10il_dataout <= wire_nliiiili_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01i0i; + wire_nlii10ili_dataout <= wire_nilOl1iO_dataout WHEN niOililll = '1' ELSE nlii111ii; + wire_nlii10ill_dataout <= wire_nilOl1li_dataout WHEN niOililll = '1' ELSE nlii111il; + wire_nlii10ilO_dataout <= wire_nilOl1ll_dataout WHEN niOililll = '1' ELSE nlii111iO; + wire_nlii10iO_dataout <= wire_nliiiill_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01i0l; + wire_nlii10iOi_dataout <= wire_nilOl1lO_dataout WHEN niOililll = '1' ELSE nlii111li; + wire_nlii10iOl_dataout <= wire_nilOl1Oi_dataout WHEN niOililll = '1' ELSE nlii111ll; + wire_nlii10iOO_dataout <= wire_nilOl1Ol_dataout WHEN niOililll = '1' ELSE nlii111lO; + wire_nlii10l0i_dataout <= wire_nilOil1l_dataout WHEN niOilillO = '1' ELSE nlii111OO; + wire_nlii10l0l_dataout <= wire_nilOil1O_dataout WHEN niOilillO = '1' ELSE nlii1101i; + wire_nlii10l0O_dataout <= wire_nilOil0i_dataout WHEN niOilillO = '1' ELSE nlii1101l; + wire_nlii10l1i_dataout <= wire_nilOl1OO_dataout WHEN niOililll = '1' ELSE nlii111Oi; + wire_nlii10l1O_dataout <= wire_nilOil1i_dataout WHEN niOilillO = '1' ELSE nlii111Ol; + wire_nlii10li_dataout <= wire_nliiiilO_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01i0O; + wire_nlii10lii_dataout <= wire_nilOil0l_dataout WHEN niOilillO = '1' ELSE nlii1101O; + wire_nlii10lil_dataout <= wire_nilOil0O_dataout WHEN niOilillO = '1' ELSE nlii1100i; + wire_nlii10liO_dataout <= wire_nilOilii_dataout WHEN niOilillO = '1' ELSE nlii1100l; + wire_nlii10ll_dataout <= wire_nliiiiOi_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01iii; + wire_nlii10lli_dataout <= wire_nilOilil_dataout WHEN niOilillO = '1' ELSE nlii1100O; + wire_nlii10lll_dataout <= wire_nilOiliO_dataout WHEN niOilillO = '1' ELSE nlii110ii; + wire_nlii10llO_dataout <= wire_nilOilli_dataout WHEN niOilillO = '1' ELSE nlii110il; + wire_nlii10lO_dataout <= wire_nliiiiOl_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01iil; + wire_nlii10lOi_dataout <= wire_nilOilll_dataout WHEN niOilillO = '1' ELSE nlii110iO; + wire_nlii10lOl_dataout <= wire_nilOillO_dataout WHEN niOilillO = '1' ELSE nlii110li; + wire_nlii10lOO_dataout <= wire_nilOilOi_dataout WHEN niOilillO = '1' ELSE nlii110ll; + wire_nlii10O1i_dataout <= wire_nilOiili_dataout WHEN niOilillO = '1' ELSE nlii110lO; + wire_nlii10O1l_dataout <= wire_nilOiill_dataout WHEN niOilillO = '1' ELSE nlii110Oi; + wire_nlii10O1O_dataout <= wire_nilOiilO_dataout WHEN niOilillO = '1' ELSE nlii110Ol; + wire_nlii10Oi_dataout <= wire_nliiiiOO_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli01iiO; + wire_nlii10Ol_dataout <= wire_nliiil1i_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1ll1i; + wire_nlii10OO_dataout <= wire_nliiil1l_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1ll1l; + wire_nlii110i_dataout <= wire_nliii00l_dataout WHEN nli1l0ii = '1' ELSE nli01iOi; + wire_nlii110l_dataout <= wire_nliii0ii_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1l0OO; + wire_nlii110O_dataout <= wire_nliii0il_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1li1i; + wire_nlii111i_dataout <= wire_nliii01l_dataout WHEN nli1l0ii = '1' ELSE nli01ili; + wire_nlii111l_dataout <= wire_nliii01O_dataout WHEN nli1l0ii = '1' ELSE nli01ill; + wire_nlii111O_dataout <= wire_nliii00i_dataout WHEN nli1l0ii = '1' ELSE nli01ilO; + wire_nlii11ii_dataout <= wire_nliii0iO_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1li1l; + wire_nlii11iil_dataout <= nli0OOOlO AND NOT(wire_niO01O0O_dataout); + wire_nlii11iiO_dataout <= niOililOi AND NOT(wire_niO01O0O_dataout); + wire_nlii11il_dataout <= wire_nliii0li_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1li1O; + wire_nlii11ili_dataout <= wire_nlii10i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11ill_dataout <= wire_nlii10i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11ilO_dataout <= wire_nlii10i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11iO_dataout <= wire_nliii0ll_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1li0i; + wire_nlii11iOi_dataout <= wire_nlii10i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11iOl_dataout <= wire_nlii10i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11iOO_dataout <= wire_nlii10i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11l0i_dataout <= wire_nlii10ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11l0l_dataout <= wire_nlii10ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11l0O_dataout <= wire_nlii10ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11l1i_dataout <= wire_nlii10iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11l1l_dataout <= wire_nlii10iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11l1O_dataout <= wire_nlii10iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11li_dataout <= wire_nliii0lO_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1li0l; + wire_nlii11lii_dataout <= wire_nlii10iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11lil_dataout <= wire_nlii10iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11liO_dataout <= wire_nlii10iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11ll_dataout <= wire_nliii0Oi_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1li0O; + wire_nlii11lli_dataout <= wire_nlii10l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11lll_dataout <= wire_nlii10l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11llO_dataout <= wire_nlii10l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11lO_dataout <= wire_nliii0Ol_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1liii; + wire_nlii11lOi_dataout <= wire_nlii10l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11lOl_dataout <= wire_nlii10l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11lOO_dataout <= wire_nlii10lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11O0i_dataout <= wire_nlii10lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11O0l_dataout <= wire_nlii10llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11O0O_dataout <= wire_nlii10lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11O1i_dataout <= wire_nlii10lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11O1l_dataout <= wire_nlii10liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11O1O_dataout <= wire_nlii10lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11Oi_dataout <= wire_nliii0OO_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1liil; + wire_nlii11Oii_dataout <= wire_nlii10lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11Oil_dataout <= wire_nlii10lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11OiO_dataout <= wire_nlii10O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11Ol_dataout <= wire_nliiii1i_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1liiO; + wire_nlii11Oli_dataout <= wire_nlii10O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11Oll_dataout <= wire_nlii10O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11OlO_dataout <= wire_nlii1010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11OO_dataout <= wire_nliiii1l_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1lili; + wire_nlii11OOi_dataout <= wire_nlii1010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii11OOl_dataout <= (niOililli AND ((((wire_nlill0Oll_w_lg_w_lg_w_lg_nlii110Ol44999w45000w45001w(0) OR wire_nlill0Oll_w_lg_w_lg_w_lg_nlii110Ol44999w45002w45003w(0)) OR wire_nlill0Oll_w_lg_w_lg_nlii110Ol44995w45005w(0)) OR (wire_nlill0Oll_w_lg_nlii110Ol45007w(0) AND wire_nlill0Oll_w_lg_nlii110lO44996w(0))) OR wire_nlill0Oll_w_lg_w_lg_nlii110Ol45007w45010w(0))) AND NOT(wire_niO01O0O_dataout); + wire_nlii11OOO_dataout <= (niOililli AND (wire_nlill0Oll_w_lg_nlii110Ol44995w(0) AND wire_nlill0Oll_w_lg_nlii110lO44996w(0))) AND NOT(wire_niO01O0O_dataout); + wire_nlii1i00i_dataout <= wire_nlii1iiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i00l_dataout <= wire_nlii1il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i00O_dataout <= wire_nlii1il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i01i_dataout <= wire_nlii1iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i01l_dataout <= wire_nlii1iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i01O_dataout <= wire_nlii1iiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0i_dataout <= wire_nliiil0O_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1ll0O; + wire_nlii1i0ii_dataout <= wire_nlii1il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0il_dataout <= wire_nlii1il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0iO_dataout <= ((nl11l0i1i AND (wire_nilOi11l_dataout AND niOiliO1i)) AND niOililOO) AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0l_dataout <= wire_nliiilii_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1llii; + wire_nlii1i0li_dataout <= ((wire_nilOi11l_dataout AND ((wire_nlill0Oll_w_lg_nl11lO1OO44955w(0) AND wire_nlill0Oll_w_lg_nl11lO1Ol44949w(0)) AND nl11lO1Oi)) AND niOiliO1O) AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0ll_dataout <= ((wire_nilOi11l_dataout AND (wire_nlill0Oll_w_lg_nl11lO1OO44950w(0) AND wire_nlill0Oll_w_lg_nl11lO1Oi44951w(0))) AND niOiliO1O) AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0lO_dataout <= (niOiliO0i AND niOiliO1O) AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0O_dataout <= wire_nliiilil_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1llil; + wire_nlii1i0Oi_dataout <= ((nl11lOO1l AND niOiliO0i) AND wire_nlill0Oll_w_lg_w_lg_nl11lOlOO44945w44946w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nlii1i0Ol_dataout <= niOiliO0i AND NOT(wire_niO01O0O_dataout); + wire_nlii1i1i_dataout <= wire_nliiil1O_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1ll1O; + wire_nlii1i1l_dataout <= wire_nliiil0i_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1ll0i; + wire_nlii1i1ll_dataout <= wire_nlii1iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i1lO_dataout <= wire_nlii1iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i1O_dataout <= wire_nliiil0l_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1ll0l; + wire_nlii1i1Oi_dataout <= wire_nlii1iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i1Ol_dataout <= wire_nlii1iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1i1OO_dataout <= wire_nlii1iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1iii_dataout <= wire_nli110ii_q(157) AND wire_nli1l0il_dataout; + wire_nlii1iiii_dataout <= nl11lO00i WHEN niOiliO1l = '1' ELSE nlii11iii; + wire_nlii1iiil_dataout <= nl11lO00l WHEN niOiliO1l = '1' ELSE nlii10Oii; + wire_nlii1iiiO_dataout <= nl11lO00O WHEN niOiliO1l = '1' ELSE nlii10Oil; + wire_nlii1iil_dataout <= wire_nli110ii_q(132) AND wire_nli1l0il_dataout; + wire_nlii1iili_dataout <= nl11lO0ii WHEN niOiliO1l = '1' ELSE nlii10OiO; + wire_nlii1iill_dataout <= nl11lO0il WHEN niOiliO1l = '1' ELSE nlii10Oli; + wire_nlii1iilO_dataout <= nl11lO0iO WHEN niOiliO1l = '1' ELSE nlii10Oll; + wire_nlii1iiO_dataout <= wire_nli110ii_q(0) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lliO; + wire_nlii1iiOi_dataout <= nl11lO0li WHEN niOiliO1l = '1' ELSE nlii10OlO; + wire_nlii1iiOl_dataout <= nl11lO0ll WHEN niOiliO1l = '1' ELSE nlii10OOi; + wire_nlii1iiOO_dataout <= nl11lO0lO WHEN niOiliO1l = '1' ELSE nlii10OOl; + wire_nlii1il0i_dataout <= nl11lOi1i WHEN niOiliO1l = '1' ELSE nlii1i11O; + wire_nlii1il1i_dataout <= nl11lO0Oi WHEN niOiliO1l = '1' ELSE nlii10OOO; + wire_nlii1il1l_dataout <= nl11lO0Ol WHEN niOiliO1l = '1' ELSE nlii1i11i; + wire_nlii1il1O_dataout <= nl11lO0OO WHEN niOiliO1l = '1' ELSE nlii1i11l; + wire_nlii1ili_dataout <= wire_nli110ii_q(1) WHEN wire_nli1l0il_dataout = '1' ELSE nli1llli; + wire_nlii1ill_dataout <= wire_nli110ii_q(2) WHEN wire_nli1l0il_dataout = '1' ELSE nli1llll; + wire_nlii1ilO_dataout <= wire_nli110ii_q(3) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lllO; + wire_nlii1iOi_dataout <= wire_nli110ii_q(4) WHEN wire_nli1l0il_dataout = '1' ELSE nli1llOi; + wire_nlii1iOl_dataout <= wire_nli110ii_q(5) WHEN wire_nli1l0il_dataout = '1' ELSE nli1llOl; + wire_nlii1iOO_dataout <= wire_nli110ii_q(6) WHEN wire_nli1l0il_dataout = '1' ELSE nli1llOO; + wire_nlii1l00i_dataout <= wire_nlii1ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l00l_dataout <= wire_nlii1llii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l00O_dataout <= wire_nlii1llil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l01i_dataout <= wire_nlii1ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l01l_dataout <= wire_nlii1ll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l01O_dataout <= wire_nlii1ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0i_dataout <= wire_nli110ii_q(10) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lO0i; + wire_nlii1l0ii_dataout <= wire_nlii1lliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0il_dataout <= wire_nlii1llli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0iO_dataout <= wire_nlii1llll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0l_dataout <= wire_nli110ii_q(11) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lO0l; + wire_nlii1l0li_dataout <= wire_nlii1lllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0ll_dataout <= wire_nlii1llOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0lO_dataout <= wire_nlii1llOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0O_dataout <= wire_nli110ii_q(12) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lO0O; + wire_nlii1l0Oi_dataout <= wire_nlii1llOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0Ol_dataout <= wire_nlii1lO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l0OO_dataout <= wire_nlii1lO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l1i_dataout <= wire_nli110ii_q(7) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lO1i; + wire_nlii1l1l_dataout <= wire_nli110ii_q(8) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lO1l; + wire_nlii1l1lO_dataout <= wire_nlii1liOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l1O_dataout <= wire_nli110ii_q(9) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lO1O; + wire_nlii1l1Oi_dataout <= wire_nlii1liOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l1Ol_dataout <= wire_nlii1ll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1l1OO_dataout <= wire_nlii1ll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1li0i_dataout <= wire_nlii1lO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1li0l_dataout <= wire_nlii1lOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1li0O_dataout <= wire_nlii1lOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1li1i_dataout <= wire_nlii1lO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1li1l_dataout <= wire_nlii1lO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1li1O_dataout <= wire_nlii1lO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1lii_dataout <= wire_nli110ii_q(13) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOii; + wire_nlii1liii_dataout <= wire_nlii1lOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1liil_dataout <= wire_nlii1lOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1liiO_dataout <= wire_nlii1lOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1lil_dataout <= wire_nli110ii_q(14) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOil; + wire_nlii1lili_dataout <= wire_nlii1lOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1lill_dataout <= wire_nlii1lOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1lilO_dataout <= wire_nlii1lOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1liO_dataout <= wire_nli110ii_q(15) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOiO; + wire_nlii1liOi_dataout <= wire_nlii1lOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlii1liOl_dataout <= (NOT (wire_nlii00liO_dataout AND (wire_nlii0i1ll_dataout AND (wire_nlii0i0il_dataout AND (wire_nlii0i0ll_dataout AND (wire_nlii0ilOl_dataout AND (wire_nlii0l01l_dataout AND (wire_nlii0ll0l_dataout AND (wire_nlii0O1il_dataout AND (wire_nlii0O01l_dataout AND (wire_nlii0O0il_dataout AND (wire_nlii0O0Ol_dataout AND (wire_nlii0Oill_dataout AND (wire_nlill0Oll_w_lg_nl0iOil0l44799w(0) AND wire_nlii0Olil_dataout)))))))))))))) AND niOiliO0l; + wire_nlii1liOO_dataout <= (NOT (wire_nlii00lli_dataout AND (wire_nlii0i1lO_dataout AND (wire_nlii0i0iO_dataout AND (wire_nlii0i0lO_dataout AND (wire_nlii0ilOO_dataout AND (wire_nlii0l01O_dataout AND (wire_nlii0O1iO_dataout AND wire_nlii0ll0O_dataout)))))))) AND niOiliO0l; + wire_nlii1ll0i_dataout <= (NOT (wire_nlii00lOl_dataout AND (wire_nlii0i01i_dataout AND (wire_nlii0ii1i_dataout AND (wire_nlii0iO0i_dataout AND (wire_nlii0l0ii_dataout AND (wire_nlii0llli_dataout AND (wire_nlii0O1Oi_dataout AND (wire_nlii0Oi1i_dataout AND (wire_nlii0Olli_dataout AND wire_nlii0OiOi_dataout)))))))))) AND niOiliO0l; + wire_nlii1ll0l_dataout <= (NOT (wire_nlii00lOO_dataout AND (wire_nlii0i01l_dataout AND (wire_nlii0ii1l_dataout AND (wire_nlii0iO0l_dataout AND (wire_nlii0l0il_dataout AND (wire_nlii0llll_dataout AND (wire_nlii0O1Ol_dataout AND (wire_nlii0O0iO_dataout AND wire_nlii0O01O_dataout))))))))) AND niOiliO0l; + wire_nlii1ll0O_dataout <= (NOT (wire_nlii00O1i_dataout AND (wire_nlii0ii1O_dataout AND (wire_nlii0iO0O_dataout AND (wire_nlii0l0iO_dataout AND (wire_nlii0lllO_dataout AND (wire_nlii0O1OO_dataout AND (wire_nlii0O0li_dataout AND wire_nlii0O00i_dataout)))))))) AND niOiliO0l; + wire_nlii1ll1i_dataout <= (NOT (wire_nlii00lll_dataout AND (wire_nlii0i1Oi_dataout AND (wire_nlii0i0li_dataout AND (wire_nlii0i0Oi_dataout AND (wire_nlii0iO1i_dataout AND (wire_nlii0l00i_dataout AND (wire_nlii0O1li_dataout AND wire_nlii0llii_dataout)))))))) AND niOiliO0l; + wire_nlii1ll1l_dataout <= (NOT (wire_nlii00llO_dataout AND (wire_nlii0i1Ol_dataout AND (wire_nlii0i0Ol_dataout AND (wire_nlii0iO1l_dataout AND (wire_nlii0l00l_dataout AND (wire_nlii0O1ll_dataout AND wire_nlii0llil_dataout))))))) AND niOiliO0l; + wire_nlii1ll1O_dataout <= (NOT (wire_nlii00lOi_dataout AND (wire_nlii0i1OO_dataout AND (wire_nlii0i0OO_dataout AND (wire_nlii0iO1O_dataout AND (wire_nlii0l00O_dataout AND (wire_nlii0lliO_dataout AND (wire_nlii0O1lO_dataout AND (wire_nlii0O0OO_dataout AND (wire_nlii0OliO_dataout AND wire_nlii0OilO_dataout)))))))))) AND niOiliO0l; + wire_nlii1lli_dataout <= wire_nli110ii_q(16) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOli; + wire_nlii1llii_dataout <= (NOT (wire_nlii00O1l_dataout AND (wire_nlii0ii0i_dataout AND (wire_nlii0iOii_dataout AND (wire_nlii0l0li_dataout AND (wire_nlii0llOi_dataout AND (wire_nlii0O01i_dataout AND (wire_nlii0O0ll_dataout AND wire_nlii0O00l_dataout)))))))) AND niOiliO0l; + wire_nlii1llil_dataout <= (NOT (wire_nlii00O1O_dataout AND (wire_nlii0ii0l_dataout AND (wire_nlii0iOil_dataout AND (wire_nlii0llOl_dataout AND wire_nlii0l0ll_dataout))))) AND niOiliO0l; + wire_nlii1lliO_dataout <= (NOT (wire_nlii00O0i_dataout AND (wire_nlii0ii0O_dataout AND (wire_nlii0iOiO_dataout AND (wire_nlii0llOO_dataout AND wire_nlii0l0lO_dataout))))) AND niOiliO0l; + wire_nlii1lll_dataout <= wire_nli110ii_q(17) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOll; + wire_nlii1llli_dataout <= (NOT (wire_nlii00O0l_dataout AND (wire_nlii0iiii_dataout AND (wire_nlii0iOli_dataout AND (wire_nlii0lO1i_dataout AND wire_nlii0l0Oi_dataout))))) AND niOiliO0l; + wire_nlii1llll_dataout <= (NOT (wire_nlii00O0O_dataout AND (wire_nlii0iiil_dataout AND (wire_nlii0iOll_dataout AND (wire_nlii0l0Ol_dataout AND (wire_nlii0lO1l_dataout AND (wire_nlii0O00O_dataout AND (wire_nlii0O0lO_dataout AND (wire_nlii0Oi1l_dataout AND (wire_nlii0Olll_dataout AND wire_nlii0OiOl_dataout)))))))))) AND niOiliO0l; + wire_nlii1lllO_dataout <= (NOT (wire_nlii00Oii_dataout AND (wire_nlii0iiiO_dataout AND (wire_nlii0iOlO_dataout AND (wire_nlii0l0OO_dataout AND (wire_nlii0lO1O_dataout AND (wire_nlii0O0ii_dataout AND (wire_nlii0O0Oi_dataout AND (wire_nlii0Oi1O_dataout AND (wire_nlii0OllO_dataout AND wire_nlii0OiOO_dataout)))))))))) AND niOiliO0l; + wire_nlii1llO_dataout <= wire_nli110ii_q(18) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOlO; + wire_nlii1llOi_dataout <= (NOT (wire_nlii00Oil_dataout AND (wire_nlii0iili_dataout AND (wire_nlii0iOOi_dataout AND (wire_nlii0li1i_dataout AND (wire_nlii0lO0i_dataout AND (wire_nlii0Oi0i_dataout AND (wire_nlii0OlOi_dataout AND wire_nlii0Ol1i_dataout)))))))) AND niOiliO0l; + wire_nlii1llOl_dataout <= (NOT (wire_nlii00OiO_dataout AND (wire_nlii0iill_dataout AND (wire_nlii0iOOl_dataout AND (wire_nlii0li1l_dataout AND (wire_nlii0lO0l_dataout AND (wire_nlii0Oi0l_dataout AND (wire_nlii0OlOl_dataout AND wire_nlii0Ol1l_dataout)))))))) AND niOiliO0l; + wire_nlii1llOO_dataout <= (NOT (wire_nlii00Oli_dataout AND (wire_nlii0iilO_dataout AND (wire_nlii0iOOO_dataout AND (wire_nlii0li1O_dataout AND (wire_nlii0lO0O_dataout AND (wire_nlii0Oi0O_dataout AND (wire_nlii0Ol1O_dataout AND (wire_nlill0Oll_w_lg_nl0iOil0l44799w(0) AND wire_nlii0OlOO_dataout))))))))) AND niOiliO0l; + wire_nlii1lO0i_dataout <= (NOT (wire_nlii00OOl_dataout AND (wire_nlii0il1i_dataout AND (wire_nlii0l10i_dataout AND (wire_nlii0liii_dataout AND (wire_nlii0lOli_dataout AND (wire_nlii0Oili_dataout AND (wire_nlii0OO0i_dataout AND wire_nlii0Olii_dataout)))))))) AND niOiliO0l; + wire_nlii1lO0l_dataout <= (NOT (wire_nlii00OOO_dataout AND (wire_nlii0il1l_dataout AND (wire_nlii0l10l_dataout AND (wire_nlii0lOll_dataout AND wire_nlii0liil_dataout))))) AND niOiliO0l; + wire_nlii1lO0O_dataout <= (NOT (wire_nlii0i11i_dataout AND (wire_nlii0il1O_dataout AND (wire_nlii0l10O_dataout AND (wire_nlii0lOlO_dataout AND wire_nlii0liiO_dataout))))) AND niOiliO0l; + wire_nlii1lO1i_dataout <= (NOT (wire_nlii00Oll_dataout AND (wire_nlii0iiOi_dataout AND (wire_nlii0l11i_dataout AND (wire_nlii0li0i_dataout AND (wire_nlii0lOii_dataout AND (wire_nlii0Oiii_dataout AND (wire_nlii0OO1i_dataout AND wire_nlii0Ol0i_dataout)))))))) AND niOiliO0l; + wire_nlii1lO1l_dataout <= (NOT (wire_nlii00OlO_dataout AND (wire_nlii0iiOl_dataout AND (wire_nlii0l11l_dataout AND (wire_nlii0li0l_dataout AND (wire_nlii0lOil_dataout AND (wire_nlii0Oiil_dataout AND (wire_nlii0OO1l_dataout AND wire_nlii0Ol0l_dataout)))))))) AND niOiliO0l; + wire_nlii1lO1O_dataout <= (NOT (wire_nlii00OOi_dataout AND (wire_nlii0iiOO_dataout AND (wire_nlii0l11O_dataout AND (wire_nlii0li0O_dataout AND (wire_nlii0lOiO_dataout AND (wire_nlii0OiiO_dataout AND (wire_nlii0OO1O_dataout AND wire_nlii0Ol0O_dataout)))))))) AND niOiliO0l; + wire_nlii1lOi_dataout <= wire_nli110ii_q(19) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOOi; + wire_nlii1lOii_dataout <= (NOT (wire_nlii0i11l_dataout AND (wire_nlii0il0i_dataout AND (wire_nlii0l1ii_dataout AND (wire_nlii0lOOi_dataout AND wire_nlii0lili_dataout))))) AND niOiliO0l; + wire_nlii1lOil_dataout <= (NOT (wire_nlii0i11O_dataout AND (wire_nlii0il0l_dataout AND (wire_nlii0l1il_dataout AND (wire_nlii0lOOl_dataout AND wire_nlii0lill_dataout))))) AND niOiliO0l; + wire_nlii1lOiO_dataout <= (NOT (wire_nlii0i10i_dataout AND (wire_nlii0il0O_dataout AND (wire_nlii0l1iO_dataout AND (wire_nlii0lOOO_dataout AND wire_nlii0lilO_dataout))))) AND niOiliO0l; + wire_nlii1lOl_dataout <= wire_nli110ii_q(20) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOOl; + wire_nlii1lOli_dataout <= (NOT (wire_nlii0i10l_dataout AND (wire_nlii0ilii_dataout AND (wire_nlii0l1li_dataout AND (wire_nlii0O11i_dataout AND wire_nlii0liOi_dataout))))) AND niOiliO0l; + wire_nlii1lOll_dataout <= (NOT (wire_nlii0i10O_dataout AND (wire_nlii0i01O_dataout AND (wire_nlii0ilil_dataout AND (wire_nlii0l1ll_dataout AND (wire_nlii0O11l_dataout AND wire_nlii0liOl_dataout)))))) AND niOiliO0l; + wire_nlii1lOlO_dataout <= (NOT (wire_nlii0i1ii_dataout AND (wire_nlii0i00i_dataout AND (wire_nlii0iliO_dataout AND (wire_nlii0l1lO_dataout AND (wire_nlii0O11O_dataout AND wire_nlii0liOO_dataout)))))) AND niOiliO0l; + wire_nlii1lOO_dataout <= wire_nli110ii_q(21) WHEN wire_nli1l0il_dataout = '1' ELSE nli1lOOO; + wire_nlii1lOOi_dataout <= (NOT (wire_nlii0i1il_dataout AND (wire_nlii0i00l_dataout AND (wire_nlii0illi_dataout AND (wire_nlii0l1Oi_dataout AND (wire_nlii0O10i_dataout AND wire_nlii0ll1i_dataout)))))) AND niOiliO0l; + wire_nlii1lOOl_dataout <= (NOT (wire_nlii0i1iO_dataout AND (wire_nlii0i00O_dataout AND (wire_nlii0illl_dataout AND (wire_nlii0l1Ol_dataout AND (wire_nlii0O10l_dataout AND wire_nlii0ll1l_dataout)))))) AND niOiliO0l; + wire_nlii1lOOO_dataout <= (NOT (wire_nlii0i1li_dataout AND (wire_nlii0i0ii_dataout AND (wire_nlii0illO_dataout AND (wire_nlii0l1OO_dataout AND (wire_nlii0O10O_dataout AND wire_nlii0ll1O_dataout)))))) AND niOiliO0l; + wire_nlii1O0i_dataout <= wire_nli110ii_q(25) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O10i; + wire_nlii1O0l_dataout <= wire_nli110ii_q(26) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O10l; + wire_nlii1O0O_dataout <= wire_nli110ii_q(27) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O10O; + wire_nlii1O1i_dataout <= wire_nli110ii_q(22) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O11i; + wire_nlii1O1l_dataout <= wire_nli110ii_q(23) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O11l; + wire_nlii1O1O_dataout <= wire_nli110ii_q(24) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O11O; + wire_nlii1Oii_dataout <= wire_nli110ii_q(28) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1ii; + wire_nlii1Oil_dataout <= wire_nli110ii_q(29) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1il; + wire_nlii1OiO_dataout <= wire_nli110ii_q(30) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1iO; + wire_nlii1Oli_dataout <= wire_nli110ii_q(31) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1li; + wire_nlii1Oll_dataout <= wire_nli110ii_q(32) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1ll; + wire_nlii1OlO_dataout <= wire_nli110ii_q(33) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1lO; + wire_nlii1OOi_dataout <= wire_nli110ii_q(34) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1Oi; + wire_nlii1OOl_dataout <= wire_nli110ii_q(35) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1Ol; + wire_nlii1OOO_dataout <= wire_nli110ii_q(36) WHEN wire_nli1l0il_dataout = '1' ELSE nli1O1OO; + wire_nliii000l_dataout <= wire_nliii000O_dataout AND NOT((niOill10l OR (wire_nl0l1lOil_dataout AND niOill10i))); + wire_nliii000O_dataout <= nliii100O OR niOiliOOi; + wire_nliii00i_dataout <= wire_nli110ii_q(128) AND wire_nli1l0il_dataout; + wire_nliii00iO_dataout <= wire_nliii00li_dataout AND NOT((niOill10l OR (wire_nl0l1lOii_dataout AND niOill10i))); + wire_nliii00l_dataout <= wire_nli110ii_q(129) AND wire_nli1l0il_dataout; + wire_nliii00li_dataout <= nliii01Oi OR niOiliOlO; + wire_nliii00O_dataout <= wire_nliiiliO_dataout WHEN wire_nli1l0il_dataout = '1' ELSE nli1l00i; + wire_nliii00Ol_dataout <= wire_nliii00OO_dataout AND NOT((niOill10l OR (wire_nl0l1lO0O_dataout AND niOill10i))); + wire_nliii00OO_dataout <= nliii01Ol OR (niOiliOOi AND wire_nliiOiilO_w_lg_nliii001i44467w(0)); + wire_nliii010i_dataout <= nl01l00ii WHEN niOill11l = '1' ELSE nliii11Oi; + wire_nliii010l_dataout <= nl01l00il WHEN niOill11l = '1' ELSE nliii11Ol; + wire_nliii010O_dataout <= nl01l00iO WHEN niOill11l = '1' ELSE nliii11OO; + wire_nliii011i_dataout <= nl01l000i WHEN niOill11l = '1' ELSE nliii11li; + wire_nliii011l_dataout <= nl01l000l WHEN niOill11l = '1' ELSE nliii11ll; + wire_nliii011O_dataout <= nl01l000O WHEN niOill11l = '1' ELSE nliii11lO; + wire_nliii01i_dataout <= wire_nli110ii_q(127) WHEN wire_nli1l0il_dataout = '1' ELSE nli01i1i; + wire_nliii01ii_dataout <= nl01l00li WHEN niOill11l = '1' ELSE nliii101i; + wire_nliii01il_dataout <= nl01l00ll WHEN niOill11l = '1' ELSE nliii101l; + wire_nliii01iO_dataout <= nl01l00lO WHEN niOill11l = '1' ELSE nliii101O; + wire_nliii01l_dataout <= wire_nli110ii_q(130) AND wire_nli1l0il_dataout; + wire_nliii01li_dataout <= nl01l00Oi WHEN niOill11l = '1' ELSE nliii100i; + wire_nliii01ll_dataout <= nl01l00Ol WHEN niOill11l = '1' ELSE nliii100l; + wire_nliii01O_dataout <= wire_nli110ii_q(131) AND wire_nli1l0il_dataout; + wire_nliii0i0l_dataout <= wire_nliii0i0O_dataout AND NOT((niOill10l OR (wire_nl0l1lO0l_dataout AND niOill10i))); + wire_nliii0i0O_dataout <= nliii01OO OR (niOiliOOl AND nliii001i); + wire_nliii0ii_dataout <= nli1l0OO WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(141); + wire_nliii0il_dataout <= nli1li1i WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(142); + wire_nliii0ili_dataout <= wire_nliii0ill_dataout AND NOT((niOill10l OR (wire_nl0l1lO0i_dataout AND niOill10i))); + wire_nliii0ill_dataout <= nliii001i OR niOiliOOl; + wire_nliii0iO_dataout <= nli1li1l WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(143); + wire_nliii0l1l_dataout <= wire_nliii0l1O_dataout AND NOT((niOill10l OR (wire_nl0l1lO1O_dataout AND niOill10i))); + wire_nliii0l1O_dataout <= nliii001l OR (niOill11l AND nliii001O); + wire_nliii0li_dataout <= nli1li1O WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(144); + wire_nliii0lii_dataout <= wire_nliii0lil_dataout AND NOT((niOill10l OR (wire_nl0l1lO1l_dataout AND niOill10i))); + wire_nliii0lil_dataout <= nliii001O OR niOill11l; + wire_nliii0ll_dataout <= nli1li0i WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(145); + wire_nliii0lO_dataout <= nli1li0l WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(146); + wire_nliii0O0i_dataout <= wire_nliii0Oii_dataout AND NOT(wire_niO01Oil_dataout); + wire_nliii0O0l_dataout <= wire_nliii0Oil_dataout AND NOT(wire_niO01Oil_dataout); + wire_nliii0O0O_dataout <= wire_nl0l1lO1l_dataout WHEN niOill10O = '1' ELSE nliii000i; + wire_nliii0O1O_dataout <= wire_nliii0O0O_dataout AND NOT(wire_niO01Oil_dataout); + wire_nliii0Oi_dataout <= nli1li0O WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(147); + wire_nliii0Oii_dataout <= wire_nl0l1lO1O_dataout WHEN niOill10O = '1' ELSE nliii0lOO; + wire_nliii0Oil_dataout <= wire_nl0l1lO0i_dataout WHEN niOill10O = '1' ELSE nliii0O1i; + wire_nliii0Ol_dataout <= nli1liii WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(148); + wire_nliii0OO_dataout <= nli1liil WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(149); + wire_nliii10i_dataout <= wire_nli110ii_q(115) WHEN wire_nli1l0il_dataout = '1' ELSE nli0100i; + wire_nliii10ii_dataout <= wire_nliii1iil_dataout WHEN niOiliOli = '1' ELSE nlii1l1ll; + wire_nliii10il_dataout <= wire_nliii1iiO_dataout WHEN niOiliOli = '1' ELSE nlii0OO0l; + wire_nliii10iO_dataout <= wire_nliii1ili_dataout WHEN niOiliOli = '1' ELSE nlii0OO0O; + wire_nliii10l_dataout <= wire_nli110ii_q(116) WHEN wire_nli1l0il_dataout = '1' ELSE nli0100l; + wire_nliii10li_dataout <= wire_nliii1ill_dataout WHEN niOiliOli = '1' ELSE nlii0OOii; + wire_nliii10ll_dataout <= wire_nliii1ilO_dataout WHEN niOiliOli = '1' ELSE nlii0OOil; + wire_nliii10lO_dataout <= wire_nliii1iOi_dataout WHEN niOiliOli = '1' ELSE nlii0OOiO; + wire_nliii10O_dataout <= wire_nli110ii_q(117) WHEN wire_nli1l0il_dataout = '1' ELSE nli0100O; + wire_nliii10Oi_dataout <= wire_nliii1iOl_dataout WHEN niOiliOli = '1' ELSE nlii0OOli; + wire_nliii10Ol_dataout <= wire_nliii1iOO_dataout WHEN niOiliOli = '1' ELSE nlii0OOll; + wire_nliii10OO_dataout <= wire_nliii1l1i_dataout WHEN niOiliOli = '1' ELSE nlii0OOlO; + wire_nliii11i_dataout <= wire_nli110ii_q(112) WHEN wire_nli1l0il_dataout = '1' ELSE nli0101i; + wire_nliii11l_dataout <= wire_nli110ii_q(113) WHEN wire_nli1l0il_dataout = '1' ELSE nli0101l; + wire_nliii11O_dataout <= wire_nli110ii_q(114) WHEN wire_nli1l0il_dataout = '1' ELSE nli0101O; + wire_nliii1i0i_dataout <= wire_nliii1l0l_dataout WHEN niOiliOli = '1' ELSE nliii111i; + wire_nliii1i0l_dataout <= wire_nliii1l0O_dataout WHEN niOiliOli = '1' ELSE nliii111l; + wire_nliii1i0O_dataout <= wire_nliii1lii_dataout WHEN niOiliOli = '1' ELSE nliii111O; + wire_nliii1i1i_dataout <= wire_nliii1l1l_dataout WHEN niOiliOli = '1' ELSE nlii0OOOi; + wire_nliii1i1l_dataout <= wire_nliii1l1O_dataout WHEN niOiliOli = '1' ELSE nlii0OOOl; + wire_nliii1i1O_dataout <= wire_nliii1l0i_dataout WHEN niOiliOli = '1' ELSE nlii0OOOO; + wire_nliii1ii_dataout <= wire_nli110ii_q(118) WHEN wire_nli1l0il_dataout = '1' ELSE nli010ii; + wire_nliii1iii_dataout <= wire_nliii1lil_dataout WHEN niOiliOli = '1' ELSE nliii110i; + wire_nliii1iil_dataout <= nl01l01Ol WHEN niOiliOOl = '1' ELSE nlii1l1ll; + wire_nliii1iiO_dataout <= nl01l01OO WHEN niOiliOOl = '1' ELSE nlii0OO0l; + wire_nliii1il_dataout <= wire_nli110ii_q(119) WHEN wire_nli1l0il_dataout = '1' ELSE nli010il; + wire_nliii1ili_dataout <= nl01l001i WHEN niOiliOOl = '1' ELSE nlii0OO0O; + wire_nliii1ill_dataout <= nl01l001l WHEN niOiliOOl = '1' ELSE nlii0OOii; + wire_nliii1ilO_dataout <= nl01l001O WHEN niOiliOOl = '1' ELSE nlii0OOil; + wire_nliii1iO_dataout <= wire_nli110ii_q(120) WHEN wire_nli1l0il_dataout = '1' ELSE nli010iO; + wire_nliii1iOi_dataout <= nl01l000i WHEN niOiliOOl = '1' ELSE nlii0OOiO; + wire_nliii1iOl_dataout <= nl01l000l WHEN niOiliOOl = '1' ELSE nlii0OOli; + wire_nliii1iOO_dataout <= nl01l000O WHEN niOiliOOl = '1' ELSE nlii0OOll; + wire_nliii1l0i_dataout <= nl01l00li WHEN niOiliOOl = '1' ELSE nlii0OOOO; + wire_nliii1l0l_dataout <= nl01l00ll WHEN niOiliOOl = '1' ELSE nliii111i; + wire_nliii1l0O_dataout <= nl01l00lO WHEN niOiliOOl = '1' ELSE nliii111l; + wire_nliii1l1i_dataout <= nl01l00ii WHEN niOiliOOl = '1' ELSE nlii0OOlO; + wire_nliii1l1l_dataout <= nl01l00il WHEN niOiliOOl = '1' ELSE nlii0OOOi; + wire_nliii1l1O_dataout <= nl01l00iO WHEN niOiliOOl = '1' ELSE nlii0OOOl; + wire_nliii1li_dataout <= wire_nli110ii_q(121) WHEN wire_nli1l0il_dataout = '1' ELSE nli010li; + wire_nliii1lii_dataout <= nl01l00Oi WHEN niOiliOOl = '1' ELSE nliii111O; + wire_nliii1lil_dataout <= nl01l00Ol WHEN niOiliOOl = '1' ELSE nliii110i; + wire_nliii1ll_dataout <= wire_nli110ii_q(122) WHEN wire_nli1l0il_dataout = '1' ELSE nli010ll; + wire_nliii1lli_dataout <= wire_nliii1Oll_dataout WHEN niOiliOll = '1' ELSE nliii110l; + wire_nliii1lll_dataout <= wire_nliii1OlO_dataout WHEN niOiliOll = '1' ELSE nliii110O; + wire_nliii1llO_dataout <= wire_nliii1OOi_dataout WHEN niOiliOll = '1' ELSE nliii11ii; + wire_nliii1lO_dataout <= wire_nli110ii_q(123) WHEN wire_nli1l0il_dataout = '1' ELSE nli010lO; + wire_nliii1lOi_dataout <= wire_nliii1OOl_dataout WHEN niOiliOll = '1' ELSE nliii11il; + wire_nliii1lOl_dataout <= wire_nliii1OOO_dataout WHEN niOiliOll = '1' ELSE nliii11iO; + wire_nliii1lOO_dataout <= wire_nliii011i_dataout WHEN niOiliOll = '1' ELSE nliii11li; + wire_nliii1O0i_dataout <= wire_nliii010l_dataout WHEN niOiliOll = '1' ELSE nliii11Ol; + wire_nliii1O0l_dataout <= wire_nliii010O_dataout WHEN niOiliOll = '1' ELSE nliii11OO; + wire_nliii1O0O_dataout <= wire_nliii01ii_dataout WHEN niOiliOll = '1' ELSE nliii101i; + wire_nliii1O1i_dataout <= wire_nliii011l_dataout WHEN niOiliOll = '1' ELSE nliii11ll; + wire_nliii1O1l_dataout <= wire_nliii011O_dataout WHEN niOiliOll = '1' ELSE nliii11lO; + wire_nliii1O1O_dataout <= wire_nliii010i_dataout WHEN niOiliOll = '1' ELSE nliii11Oi; + wire_nliii1Oi_dataout <= wire_nli110ii_q(124) WHEN wire_nli1l0il_dataout = '1' ELSE nli010Oi; + wire_nliii1Oii_dataout <= wire_nliii01il_dataout WHEN niOiliOll = '1' ELSE nliii101l; + wire_nliii1Oil_dataout <= wire_nliii01iO_dataout WHEN niOiliOll = '1' ELSE nliii101O; + wire_nliii1OiO_dataout <= wire_nliii01li_dataout WHEN niOiliOll = '1' ELSE nliii100i; + wire_nliii1Ol_dataout <= wire_nli110ii_q(125) WHEN wire_nli1l0il_dataout = '1' ELSE nli010Ol; + wire_nliii1Oli_dataout <= wire_nliii01ll_dataout WHEN niOiliOll = '1' ELSE nliii100l; + wire_nliii1Oll_dataout <= nl01l01Ol WHEN niOill11l = '1' ELSE nliii110l; + wire_nliii1OlO_dataout <= nl01l01OO WHEN niOill11l = '1' ELSE nliii110O; + wire_nliii1OO_dataout <= wire_nli110ii_q(126) WHEN wire_nli1l0il_dataout = '1' ELSE nli010OO; + wire_nliii1OOi_dataout <= nl01l001i WHEN niOill11l = '1' ELSE nliii11ii; + wire_nliii1OOl_dataout <= nl01l001l WHEN niOill11l = '1' ELSE nliii11il; + wire_nliii1OOO_dataout <= nl01l001O WHEN niOill11l = '1' ELSE nliii11iO; + wire_nliiii0i_dataout <= nli1lilO WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(153); + wire_nliiii0l_dataout <= nli1liOi WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(154); + wire_nliiii0O_dataout <= nli1liOl WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(155); + wire_nliiii1i_dataout <= nli1liiO WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(150); + wire_nliiii1l_dataout <= nli1lili WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(151); + wire_nliiii1O_dataout <= nli1lill WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(152); + wire_nliiiiii_dataout <= nli1liOO WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(156); + wire_nliiiiil_dataout <= nli01i1l WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(133); + wire_nliiiiiO_dataout <= nli01i1O WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(134); + wire_nliiiili_dataout <= nli01i0i WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(135); + wire_nliiiill_dataout <= nli01i0l WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(136); + wire_nliiiilO_dataout <= nli01i0O WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(137); + wire_nliiiiOi_dataout <= nli01iii WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(138); + wire_nliiiiOl_dataout <= nli01iil WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(139); + wire_nliiiiOO_dataout <= nli01iiO WHEN k_gbl_hip(33) = '1' ELSE wire_nli110ii_q(140); + wire_nliiil0i_dataout <= wire_nli110ii_q(137) WHEN k_gbl_hip(33) = '1' ELSE nli1ll0i; + wire_nliiil0l_dataout <= wire_nli110ii_q(135) WHEN k_gbl_hip(33) = '1' ELSE nli1ll0l; + wire_nliiil0O_dataout <= wire_nli110ii_q(139) WHEN k_gbl_hip(33) = '1' ELSE nli1ll0O; + wire_nliiil1i_dataout <= wire_nli110ii_q(134) WHEN k_gbl_hip(33) = '1' ELSE nli1ll1i; + wire_nliiil1l_dataout <= wire_nli110ii_q(138) WHEN k_gbl_hip(33) = '1' ELSE nli1ll1l; + wire_nliiil1O_dataout <= wire_nli110ii_q(133) WHEN k_gbl_hip(33) = '1' ELSE nli1ll1O; + wire_nliiilii_dataout <= wire_nli110ii_q(136) WHEN k_gbl_hip(33) = '1' ELSE nli1llii; + wire_nliiilil_dataout <= wire_nli110ii_q(140) WHEN k_gbl_hip(33) = '1' ELSE nli1llil; + wire_nliiiliO_dataout <= wire_nliiilli_dataout AND NOT(niOO1OO1O); + wire_nliiilli_dataout <= wire_nliiilll_dataout OR NOT(((NOT wire_nli110ii_q(128)) AND (NOT wire_nli110ii_q(129)))); + wire_nliiillii_dataout <= wire_nliil10OO_dataout WHEN niOill0li = '1' ELSE wire_nliiliOOi_dataout; + wire_nliiillil_dataout <= wire_nliil1i1i_dataout WHEN niOill0li = '1' ELSE wire_nliiliOOl_dataout; + wire_nliiilliO_dataout <= wire_nliil1i1l_dataout WHEN niOill0li = '1' ELSE wire_nliiliOOO_dataout; + wire_nliiilll_dataout <= nli1l00i AND niOO1OO0i; + wire_nliiillli_dataout <= wire_nliil1i1O_dataout WHEN niOill0li = '1' ELSE wire_nliill11i_dataout; + wire_nliiillll_dataout <= wire_nliil1i0i_dataout WHEN niOill0li = '1' ELSE wire_nliill11l_dataout; + wire_nliiilllO_dataout <= wire_nliil1i0l_dataout WHEN niOill0li = '1' ELSE wire_nliill11O_dataout; + wire_nliiillO_dataout <= nl1Ol1l0i WHEN wire_w_lg_w_k_hip_range2413w2429w(0) = '1' ELSE (nl1Ol1l0i OR nllillOO); + wire_nliiillOi_dataout <= wire_nliil1i0O_dataout WHEN niOill0li = '1' ELSE wire_nliill10i_dataout; + wire_nliiillOl_dataout <= wire_nliil1iii_dataout WHEN niOill0li = '1' ELSE wire_nliill10l_dataout; + wire_nliiillOO_dataout <= wire_nliil1iil_dataout WHEN niOill0li = '1' ELSE wire_nliill10O_dataout; + wire_nliiilO0i_dataout <= wire_nliil1ilO_dataout WHEN niOill0li = '1' ELSE wire_nliill1li_dataout; + wire_nliiilO0l_dataout <= wire_nliil1iOi_dataout WHEN niOill0li = '1' ELSE wire_nliill1ll_dataout; + wire_nliiilO0O_dataout <= wire_nliil1iOl_dataout WHEN niOill0li = '1' ELSE wire_nliill1lO_dataout; + wire_nliiilO1i_dataout <= wire_nliil1iiO_dataout WHEN niOill0li = '1' ELSE wire_nliill1ii_dataout; + wire_nliiilO1l_dataout <= wire_nliil1ili_dataout WHEN niOill0li = '1' ELSE wire_nliill1il_dataout; + wire_nliiilO1O_dataout <= wire_nliil1ill_dataout WHEN niOill0li = '1' ELSE wire_nliill1iO_dataout; + wire_nliiilOii_dataout <= wire_nliil1iOO_dataout WHEN niOill0li = '1' ELSE wire_nliill1Oi_dataout; + wire_nliiilOil_dataout <= wire_nliil1l1i_dataout WHEN niOill0li = '1' ELSE wire_nliill1Ol_dataout; + wire_nliiilOiO_dataout <= wire_nliil1l1l_dataout WHEN niOill0li = '1' ELSE wire_nliill1OO_dataout; + wire_nliiilOl_dataout <= nliO0lll AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiilOli_dataout <= wire_nliil1l1O_dataout WHEN niOill0li = '1' ELSE wire_nliill01i_dataout; + wire_nliiilOll_dataout <= wire_nliil1l0i_dataout WHEN niOill0li = '1' ELSE wire_nliill01l_dataout; + wire_nliiilOlO_dataout <= wire_nliil1l0l_dataout WHEN niOill0li = '1' ELSE wire_nliill01O_dataout; + wire_nliiilOO_dataout <= nliO0llO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiilOOi_dataout <= wire_nliil1l0O_dataout WHEN niOill0li = '1' ELSE wire_nliill00i_dataout; + wire_nliiilOOl_dataout <= wire_nliil1lii_dataout WHEN niOill0li = '1' ELSE wire_nliill00l_dataout; + wire_nliiilOOO_dataout <= wire_nliil1lil_dataout WHEN niOill0li = '1' ELSE wire_nliill00O_dataout; + wire_nliiiO00i_dataout <= wire_nliil1OlO_dataout WHEN niOill0li = '1' ELSE wire_nliillili_dataout; + wire_nliiiO00l_dataout <= wire_nliil1OOi_dataout WHEN niOill0li = '1' ELSE wire_nliillill_dataout; + wire_nliiiO00O_dataout <= wire_nliil1OOl_dataout WHEN niOill0li = '1' ELSE wire_nliillilO_dataout; + wire_nliiiO01i_dataout <= wire_nliil1OiO_dataout WHEN niOill0li = '1' ELSE wire_nliilliii_dataout; + wire_nliiiO01l_dataout <= wire_nliil1Oli_dataout WHEN niOill0li = '1' ELSE wire_nliilliil_dataout; + wire_nliiiO01O_dataout <= wire_nliil1Oll_dataout WHEN niOill0li = '1' ELSE wire_nliilliiO_dataout; + wire_nliiiO0i_dataout <= nliO0O1i AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiO0ii_dataout <= wire_nliil1OOO_dataout WHEN niOill0li = '1' ELSE wire_nliilliOi_dataout; + wire_nliiiO0il_dataout <= wire_nliil011i_dataout WHEN niOill0li = '1' ELSE wire_nliilliOl_dataout; + wire_nliiiO0iO_dataout <= wire_nliil011l_dataout WHEN niOill0li = '1' ELSE wire_nliilliOO_dataout; + wire_nliiiO0l_dataout <= nliO0O1l AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiO0li_dataout <= wire_nliil011O_dataout WHEN niOill0li = '1' ELSE wire_nliilll1i_dataout; + wire_nliiiO0ll_dataout <= wire_nliil010i_dataout WHEN niOill0li = '1' ELSE wire_nliilll1l_dataout; + wire_nliiiO0lO_dataout <= wire_nliil010l_dataout WHEN niOill0li = '1' ELSE wire_nliilll1O_dataout; + wire_nliiiO0O_dataout <= nliO0O1O AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiO0Oi_dataout <= wire_nliil010O_dataout WHEN niOill0li = '1' ELSE wire_nliilll0i_dataout; + wire_nliiiO0Ol_dataout <= wire_nliil01ii_dataout WHEN niOill0li = '1' ELSE wire_nliilll0l_dataout; + wire_nliiiO0OO_dataout <= wire_nliil01il_dataout WHEN niOill0li = '1' ELSE wire_nliilll0O_dataout; + wire_nliiiO10i_dataout <= wire_nliil1llO_dataout WHEN niOill0li = '1' ELSE wire_nliill0li_dataout; + wire_nliiiO10l_dataout <= wire_nliil1lOi_dataout WHEN niOill0li = '1' ELSE wire_nliill0ll_dataout; + wire_nliiiO10O_dataout <= wire_nliil1lOl_dataout WHEN niOill0li = '1' ELSE wire_nliill0lO_dataout; + wire_nliiiO11i_dataout <= wire_nliil1liO_dataout WHEN niOill0li = '1' ELSE wire_nliill0ii_dataout; + wire_nliiiO11l_dataout <= wire_nliil1lli_dataout WHEN niOill0li = '1' ELSE wire_nliill0il_dataout; + wire_nliiiO11O_dataout <= wire_nliil1lll_dataout WHEN niOill0li = '1' ELSE wire_nliill0iO_dataout; + wire_nliiiO1i_dataout <= nliO0lOi AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiO1ii_dataout <= wire_nliil1lOO_dataout WHEN niOill0li = '1' ELSE wire_nliill0Oi_dataout; + wire_nliiiO1il_dataout <= wire_nliil1O1i_dataout WHEN niOill0li = '1' ELSE wire_nliill0Ol_dataout; + wire_nliiiO1iO_dataout <= wire_nliil1O1l_dataout WHEN niOill0li = '1' ELSE wire_nliill0OO_dataout; + wire_nliiiO1l_dataout <= nliO0lOl AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiO1li_dataout <= wire_nliil1O1O_dataout WHEN niOill0li = '1' ELSE wire_nliilli1i_dataout; + wire_nliiiO1ll_dataout <= wire_nliil1O0i_dataout WHEN niOill0li = '1' ELSE wire_nliilli1l_dataout; + wire_nliiiO1lO_dataout <= wire_nliil1O0l_dataout WHEN niOill0li = '1' ELSE wire_nliilli1O_dataout; + wire_nliiiO1O_dataout <= nliO0lOO AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiO1Oi_dataout <= wire_nliil1O0O_dataout WHEN niOill0li = '1' ELSE wire_nliilli0i_dataout; + wire_nliiiO1Ol_dataout <= wire_nliil1Oii_dataout WHEN niOill0li = '1' ELSE wire_nliilli0l_dataout; + wire_nliiiO1OO_dataout <= wire_nliil1Oil_dataout WHEN niOill0li = '1' ELSE wire_nliilli0O_dataout; + wire_nliiiOi0i_dataout <= wire_nliil01lO_dataout WHEN niOill0li = '1' ELSE wire_nliilllli_dataout; + wire_nliiiOi0l_dataout <= wire_nliil01Oi_dataout WHEN niOill0li = '1' ELSE wire_nliilllll_dataout; + wire_nliiiOi0O_dataout <= wire_nliil01Ol_dataout WHEN niOill0li = '1' ELSE wire_nliillllO_dataout; + wire_nliiiOi1i_dataout <= wire_nliil01iO_dataout WHEN niOill0li = '1' ELSE wire_nliilllii_dataout; + wire_nliiiOi1l_dataout <= wire_nliil01li_dataout WHEN niOill0li = '1' ELSE wire_nliilllil_dataout; + wire_nliiiOi1O_dataout <= wire_nliil01ll_dataout WHEN niOill0li = '1' ELSE wire_nliillliO_dataout; + wire_nliiiOii_dataout <= wire_nlilOO0i_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOiii_dataout <= wire_nliil01OO_dataout WHEN niOill0li = '1' ELSE wire_nliilllOi_dataout; + wire_nliiiOiil_dataout <= wire_nliil001i_dataout WHEN niOill0li = '1' ELSE wire_nliilllOl_dataout; + wire_nliiiOiiO_dataout <= wire_nliil001l_dataout WHEN niOill0li = '1' ELSE wire_nliilllOO_dataout; + wire_nliiiOil_dataout <= wire_nlilOO0l_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOili_dataout <= wire_nliil001O_dataout WHEN niOill0li = '1' ELSE wire_nliillO1i_dataout; + wire_nliiiOill_dataout <= wire_nliiliill_dataout WHEN niOO01ii = '1' ELSE wire_nliil000i_dataout; + wire_nliiiOilO_dataout <= wire_nliiliilO_dataout WHEN niOO01ii = '1' ELSE wire_nliil000l_dataout; + wire_nliiiOiO_dataout <= wire_nlilOO0O_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOiOi_dataout <= wire_nliiliiOi_dataout WHEN niOO01ii = '1' ELSE wire_nliil000O_dataout; + wire_nliiiOiOl_dataout <= wire_nliiliiOl_dataout WHEN niOO01ii = '1' ELSE wire_nliil00ii_dataout; + wire_nliiiOiOO_dataout <= wire_nliiliiOO_dataout WHEN niOO01ii = '1' ELSE wire_nliil00il_dataout; + wire_nliiiOl0i_dataout <= wire_nliilil0i_dataout WHEN niOO01ii = '1' ELSE wire_nliil00lO_dataout; + wire_nliiiOl0l_dataout <= wire_nliilil0l_dataout WHEN niOO01ii = '1' ELSE wire_nliil00Oi_dataout; + wire_nliiiOl0O_dataout <= wire_nliilil0O_dataout WHEN niOO01ii = '1' ELSE wire_nliil00Ol_dataout; + wire_nliiiOl1i_dataout <= wire_nliilil1i_dataout WHEN niOO01ii = '1' ELSE wire_nliil00iO_dataout; + wire_nliiiOl1l_dataout <= wire_nliilil1l_dataout WHEN niOO01ii = '1' ELSE wire_nliil00li_dataout; + wire_nliiiOl1O_dataout <= wire_nliilil1O_dataout WHEN niOO01ii = '1' ELSE wire_nliil00ll_dataout; + wire_nliiiOli_dataout <= wire_nlilOOii_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOlii_dataout <= wire_nliililii_dataout WHEN niOO01ii = '1' ELSE wire_nliil00OO_dataout; + wire_nliiiOlil_dataout <= wire_nliililil_dataout WHEN niOO01ii = '1' ELSE wire_nliil0i1i_dataout; + wire_nliiiOliO_dataout <= wire_nliililiO_dataout WHEN niOO01ii = '1' ELSE wire_nliil0i1l_dataout; + wire_nliiiOll_dataout <= wire_nlilOOil_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOlli_dataout <= wire_nliililli_dataout WHEN niOO01ii = '1' ELSE wire_nliil0i1O_dataout; + wire_nliiiOlll_dataout <= wire_nliililll_dataout WHEN niOO01ii = '1' ELSE wire_nliil0i0i_dataout; + wire_nliiiOllO_dataout <= wire_nliilillO_dataout WHEN niOO01ii = '1' ELSE wire_nliil0i0l_dataout; + wire_nliiiOlO_dataout <= wire_nlilOOiO_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOlOi_dataout <= wire_nliililOi_dataout WHEN niOO01ii = '1' ELSE wire_nliil0i0O_dataout; + wire_nliiiOlOl_dataout <= wire_nliililOl_dataout WHEN niOO01ii = '1' ELSE wire_nliil0iii_dataout; + wire_nliiiOlOO_dataout <= wire_nliililOO_dataout WHEN niOO01ii = '1' ELSE wire_nliil0iil_dataout; + wire_nliiiOO0i_dataout <= wire_nliiliO0i_dataout WHEN niOO01ii = '1' ELSE wire_nliil0ilO_dataout; + wire_nliiiOO0l_dataout <= wire_nliiliO0l_dataout WHEN niOO01ii = '1' ELSE wire_nliil0iOi_dataout; + wire_nliiiOO0O_dataout <= wire_nliiliO0O_dataout WHEN niOO01ii = '1' ELSE wire_nliil0iOl_dataout; + wire_nliiiOO1i_dataout <= wire_nliiliO1i_dataout WHEN niOO01ii = '1' ELSE wire_nliil0iiO_dataout; + wire_nliiiOO1l_dataout <= wire_nliiliO1l_dataout WHEN niOO01ii = '1' ELSE wire_nliil0ili_dataout; + wire_nliiiOO1O_dataout <= wire_nliiliO1O_dataout WHEN niOO01ii = '1' ELSE wire_nliil0ill_dataout; + wire_nliiiOOi_dataout <= wire_nlilOOli_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOOii_dataout <= wire_nliiliOii_dataout WHEN niOO01ii = '1' ELSE wire_nliil0iOO_dataout; + wire_nliiiOOil_dataout <= wire_nliiliOil_dataout WHEN niOO01ii = '1' ELSE wire_nliil0l1i_dataout; + wire_nliiiOOiO_dataout <= wire_nliiliOiO_dataout WHEN niOO01ii = '1' ELSE wire_nliil0l1l_dataout; + wire_nliiiOOl_dataout <= wire_nlilOOll_dataout AND wire_w_lg_w_k_gbl_hip_range1050w1051w(0); + wire_nliiiOOli_dataout <= wire_nliiliOli_dataout WHEN niOO01ii = '1' ELSE wire_nliil0l1O_dataout; + wire_nliiiOOll_dataout <= wire_nliiliOll_dataout WHEN niOO01ii = '1' ELSE wire_nliil0l0i_dataout; + wire_nliiiOOlO_dataout <= wire_nliiliOlO_dataout WHEN niOO01ii = '1' ELSE wire_nliil0l0l_dataout; + wire_nliiiOOO_dataout <= nlliO10l WHEN niOO1OOil = '1' ELSE wire_nliil1il_dataout; + wire_nliiiOOOi_dataout <= nii010O WHEN niOO01ii = '1' ELSE wire_nliil0l0O_dataout; + wire_nliiiOOOl_dataout <= nii01ii WHEN niOO01ii = '1' ELSE wire_nliil0lii_dataout; + wire_nliiiOOOO_dataout <= nii01il WHEN niOO01ii = '1' ELSE wire_nliil0lil_dataout; + wire_nliil000i_dataout <= wire_nliili1il_dataout WHEN niOill1il = '1' ELSE nliii0O1l; + wire_nliil000l_dataout <= wire_nliili1iO_dataout WHEN niOill1il = '1' ELSE nliii0OOi; + wire_nliil000O_dataout <= wire_nliili1li_dataout WHEN niOill1il = '1' ELSE nliii0OOl; + wire_nliil001i_dataout <= niii0iO WHEN niOO01ii = '1' ELSE wire_nliilllOl_dataout; + wire_nliil001l_dataout <= niii0li WHEN niOO01ii = '1' ELSE wire_nliilllOO_dataout; + wire_nliil001O_dataout <= niii0ll WHEN niOO01ii = '1' ELSE wire_nliillO1i_dataout; + wire_nliil00i_dataout <= wire_nliil0lO_dataout AND NOT(niOO1OO0O); + wire_nliil00ii_dataout <= wire_nliili1ll_dataout WHEN niOill1il = '1' ELSE nliii0OOO; + wire_nliil00il_dataout <= wire_nliili1lO_dataout WHEN niOill1il = '1' ELSE nliiii11i; + wire_nliil00iO_dataout <= wire_nliili1Oi_dataout WHEN niOill1il = '1' ELSE nliiii11l; + wire_nliil00l_dataout <= niOO01l1O WHEN niOO1OO0O = '1' ELSE wire_nliil0Oi_dataout; + wire_nliil00li_dataout <= wire_nliili1Ol_dataout WHEN niOill1il = '1' ELSE nliiii11O; + wire_nliil00ll_dataout <= wire_nliili1OO_dataout WHEN niOill1il = '1' ELSE nliiii10i; + wire_nliil00lO_dataout <= wire_nliili01i_dataout WHEN niOill1il = '1' ELSE nliiii10l; + wire_nliil00O_dataout <= niOO010il WHEN niOO1OO0O = '1' ELSE wire_nliil0Ol_dataout; + wire_nliil00Oi_dataout <= wire_nliili01l_dataout WHEN niOill1il = '1' ELSE nliiii10O; + wire_nliil00Ol_dataout <= wire_nliili01O_dataout WHEN niOill1il = '1' ELSE nliiii1ii; + wire_nliil00OO_dataout <= wire_nliili00i_dataout WHEN niOill1il = '1' ELSE nliiii1il; + wire_nliil010i_dataout <= niii1lO WHEN niOO01ii = '1' ELSE wire_nliilll1l_dataout; + wire_nliil010l_dataout <= niii1Oi WHEN niOO01ii = '1' ELSE wire_nliilll1O_dataout; + wire_nliil010O_dataout <= niii1Ol WHEN niOO01ii = '1' ELSE wire_nliilll0i_dataout; + wire_nliil011i_dataout <= niii1iO WHEN niOO01ii = '1' ELSE wire_nliilliOl_dataout; + wire_nliil011l_dataout <= niii1li WHEN niOO01ii = '1' ELSE wire_nliilliOO_dataout; + wire_nliil011O_dataout <= niii1ll WHEN niOO01ii = '1' ELSE wire_nliilll1i_dataout; + wire_nliil01i_dataout <= wire_nliil0iO_dataout AND NOT(niOO1OO0O); + wire_nliil01ii_dataout <= niii1OO WHEN niOO01ii = '1' ELSE wire_nliilll0l_dataout; + wire_nliil01il_dataout <= niii01i WHEN niOO01ii = '1' ELSE wire_nliilll0O_dataout; + wire_nliil01iO_dataout <= niii01l WHEN niOO01ii = '1' ELSE wire_nliilllii_dataout; + wire_nliil01l_dataout <= wire_nliil0li_dataout AND NOT(niOO1OO0O); + wire_nliil01li_dataout <= niii01O WHEN niOO01ii = '1' ELSE wire_nliilllil_dataout; + wire_nliil01ll_dataout <= niii00i WHEN niOO01ii = '1' ELSE wire_nliillliO_dataout; + wire_nliil01lO_dataout <= niii00l WHEN niOO01ii = '1' ELSE wire_nliilllli_dataout; + wire_nliil01O_dataout <= wire_nliil0ll_dataout AND NOT(niOO1OO0O); + wire_nliil01Oi_dataout <= niii00O WHEN niOO01ii = '1' ELSE wire_nliilllll_dataout; + wire_nliil01Ol_dataout <= niii0ii WHEN niOO01ii = '1' ELSE wire_nliillllO_dataout; + wire_nliil01OO_dataout <= niii0il WHEN niOO01ii = '1' ELSE wire_nliilllOi_dataout; + wire_nliil0i0i_dataout <= wire_nliili0il_dataout WHEN niOill1il = '1' ELSE nliiii1lO; + wire_nliil0i0l_dataout <= wire_nliili0iO_dataout WHEN niOill1il = '1' ELSE nliiii1Oi; + wire_nliil0i0O_dataout <= wire_nliili0li_dataout WHEN niOill1il = '1' ELSE nliiii1Ol; + wire_nliil0i1i_dataout <= wire_nliili00l_dataout WHEN niOill1il = '1' ELSE nliiii1iO; + wire_nliil0i1l_dataout <= wire_nliili00O_dataout WHEN niOill1il = '1' ELSE nliiii1li; + wire_nliil0i1O_dataout <= wire_nliili0ii_dataout WHEN niOill1il = '1' ELSE nliiii1ll; + wire_nliil0ii_dataout <= nll0OOOOl WHEN niOO1OO0O = '1' ELSE wire_nliil0OO_dataout; + wire_nliil0iii_dataout <= wire_nliili0ll_dataout WHEN niOill1il = '1' ELSE nliiii1OO; + wire_nliil0iil_dataout <= wire_nliili0lO_dataout WHEN niOill1il = '1' ELSE nliiii01i; + wire_nliil0iiO_dataout <= wire_nliili0Oi_dataout WHEN niOill1il = '1' ELSE nliiii01l; + wire_nliil0il_dataout <= nlli101ll WHEN niOO1OO0O = '1' ELSE wire_nliili1i_dataout; + wire_nliil0ili_dataout <= wire_nliili0Ol_dataout WHEN niOill1il = '1' ELSE nliiii01O; + wire_nliil0ill_dataout <= wire_nliili0OO_dataout WHEN niOill1il = '1' ELSE nliiii00i; + wire_nliil0ilO_dataout <= wire_nliilii1i_dataout WHEN niOill1il = '1' ELSE nliiii00l; + wire_nliil0iO_dataout <= niOO01l1O WHEN niOO1OO0l = '1' ELSE nliO0i0l; + wire_nliil0iOi_dataout <= wire_nliilii1l_dataout WHEN niOill1il = '1' ELSE nliiii00O; + wire_nliil0iOl_dataout <= wire_nliilii1O_dataout WHEN niOill1il = '1' ELSE nliiii0ii; + wire_nliil0iOO_dataout <= wire_nliilii0i_dataout WHEN niOill1il = '1' ELSE nliiii0il; + wire_nliil0l0i_dataout <= wire_nliiliiil_dataout WHEN niOill1il = '1' ELSE nliiii0lO; + wire_nliil0l0l_dataout <= wire_nliiliiiO_dataout WHEN niOill1il = '1' ELSE nliiii0Oi; + wire_nliil0l0O_dataout <= wire_nilOilOl_dataout WHEN niOill1il = '1' ELSE nliiii0Ol; + wire_nliil0l1i_dataout <= wire_nliilii0l_dataout WHEN niOill1il = '1' ELSE nliiii0iO; + wire_nliil0l1l_dataout <= wire_nliilii0O_dataout WHEN niOill1il = '1' ELSE nliiii0li; + wire_nliil0l1O_dataout <= wire_nliiliiii_dataout WHEN niOill1il = '1' ELSE nliiii0ll; + wire_nliil0li_dataout <= niOO010il WHEN niOO1OO0l = '1' ELSE nliO0i0O; + wire_nliil0lii_dataout <= wire_nilOilOO_dataout WHEN niOill1il = '1' ELSE nliiii0OO; + wire_nliil0lil_dataout <= wire_nilOiO1i_dataout WHEN niOill1il = '1' ELSE nliiiii1i; + wire_nliil0liO_dataout <= wire_nilOiO1l_dataout WHEN niOill1il = '1' ELSE nliiiii1l; + wire_nliil0ll_dataout <= nll0OOOOl WHEN niOO1OO0l = '1' ELSE nliO0iii; + wire_nliil0lli_dataout <= wire_nilOiO1O_dataout WHEN niOill1il = '1' ELSE nliiiii1O; + wire_nliil0lll_dataout <= wire_nilOiO0i_dataout WHEN niOill1il = '1' ELSE nliiiii0i; + wire_nliil0llO_dataout <= wire_nilOiO0l_dataout WHEN niOill1il = '1' ELSE nliiiii0l; + wire_nliil0lO_dataout <= nlli101ll WHEN niOO1OO0l = '1' ELSE nliO0l1l; + wire_nliil0lOi_dataout <= wire_nilOiO0O_dataout WHEN niOill1il = '1' ELSE nliiiii0O; + wire_nliil0lOl_dataout <= wire_nilOiOii_dataout WHEN niOill1il = '1' ELSE nliiiiiii; + wire_nliil0lOO_dataout <= wire_nilOiOil_dataout WHEN niOill1il = '1' ELSE nliiiiiil; + wire_nliil0O0i_dataout <= wire_nilOiOlO_dataout WHEN niOill1il = '1' ELSE nliiiiilO; + wire_nliil0O0l_dataout <= wire_nilOiOOi_dataout WHEN niOill1il = '1' ELSE nliiiiiOi; + wire_nliil0O0O_dataout <= wire_nilOiOOl_dataout WHEN niOill1il = '1' ELSE nliiiiiOl; + wire_nliil0O1i_dataout <= wire_nilOiOiO_dataout WHEN niOill1il = '1' ELSE nliiiiiiO; + wire_nliil0O1l_dataout <= wire_nilOiOli_dataout WHEN niOill1il = '1' ELSE nliiiiili; + wire_nliil0O1O_dataout <= wire_nilOiOll_dataout WHEN niOill1il = '1' ELSE nliiiiill; + wire_nliil0Oi_dataout <= nliO0i0l WHEN niOO1OO0l = '1' ELSE niOO01l1O; + wire_nliil0Oii_dataout <= wire_nilOiOOO_dataout WHEN niOill1il = '1' ELSE nliiiiiOO; + wire_nliil0Oil_dataout <= wire_nilOl11i_dataout WHEN niOill1il = '1' ELSE nliiiil1i; + wire_nliil0OiO_dataout <= wire_nilOl11l_dataout WHEN niOill1il = '1' ELSE nliiiil1l; + wire_nliil0Ol_dataout <= nliO0i0O WHEN niOO1OO0l = '1' ELSE niOO010il; + wire_nliil0Oli_dataout <= wire_nilOl11O_dataout WHEN niOill1il = '1' ELSE nliiiil1O; + wire_nliil0Oll_dataout <= wire_nilOl10i_dataout WHEN niOill1il = '1' ELSE nliiiil0i; + wire_nliil0OlO_dataout <= wire_nilOl10l_dataout WHEN niOill1il = '1' ELSE nliiiil0l; + wire_nliil0OO_dataout <= nliO0iii WHEN niOO1OO0l = '1' ELSE nll0OOOOl; + wire_nliil0OOi_dataout <= wire_nilOl10O_dataout WHEN niOill1il = '1' ELSE nliiiil0O; + wire_nliil0OOl_dataout <= wire_nilOl1ii_dataout WHEN niOill1il = '1' ELSE nliiiilii; + wire_nliil0OOO_dataout <= wire_nilOl1il_dataout WHEN niOill1il = '1' ELSE nliiiilil; + wire_nliil100i_dataout <= nii00lO WHEN niOO01ii = '1' ELSE wire_nliil0OlO_dataout; + wire_nliil100l_dataout <= nii00Oi WHEN niOO01ii = '1' ELSE wire_nliil0OOi_dataout; + wire_nliil100O_dataout <= nii00Ol WHEN niOO01ii = '1' ELSE wire_nliil0OOl_dataout; + wire_nliil101i_dataout <= nii00iO WHEN niOO01ii = '1' ELSE wire_nliil0OiO_dataout; + wire_nliil101l_dataout <= nii00li WHEN niOO01ii = '1' ELSE wire_nliil0Oli_dataout; + wire_nliil101O_dataout <= nii00ll WHEN niOO01ii = '1' ELSE wire_nliil0Oll_dataout; + wire_nliil10i_dataout <= nlliO1iO WHEN niOO1OOil = '1' ELSE wire_nliil1lO_dataout; + wire_nliil10ii_dataout <= nii00OO WHEN niOO01ii = '1' ELSE wire_nliil0OOO_dataout; + wire_nliil10il_dataout <= nii0i1i WHEN niOO01ii = '1' ELSE wire_nliili11i_dataout; + wire_nliil10iO_dataout <= nii0i1l WHEN niOO01ii = '1' ELSE wire_nliili11l_dataout; + wire_nliil10l_dataout <= nlliO1li WHEN niOO1OOil = '1' ELSE wire_nliil1Oi_dataout; + wire_nliil10li_dataout <= nii0i1O WHEN niOO01ii = '1' ELSE wire_nliili11O_dataout; + wire_nliil10ll_dataout <= nii0i0i WHEN niOO01ii = '1' ELSE wire_nliili10i_dataout; + wire_nliil10lO_dataout <= nii0i0l WHEN niOO01ii = '1' ELSE wire_nliili10l_dataout; + wire_nliil10O_dataout <= nlliO1ll WHEN niOO1OOil = '1' ELSE wire_nliil1Ol_dataout; + wire_nliil10Oi_dataout <= nii0i0O WHEN niOO01ii = '1' ELSE wire_nliili10O_dataout; + wire_nliil10Ol_dataout <= nii0iii WHEN niOO01ii = '1' ELSE wire_nliili1ii_dataout; + wire_nliil10OO_dataout <= nii0iil WHEN niOO01ii = '1' ELSE wire_nliiliOOi_dataout; + wire_nliil110i_dataout <= nii01lO WHEN niOO01ii = '1' ELSE wire_nliil0llO_dataout; + wire_nliil110l_dataout <= nii01Oi WHEN niOO01ii = '1' ELSE wire_nliil0lOi_dataout; + wire_nliil110O_dataout <= nii01Ol WHEN niOO01ii = '1' ELSE wire_nliil0lOl_dataout; + wire_nliil111i_dataout <= nii01iO WHEN niOO01ii = '1' ELSE wire_nliil0liO_dataout; + wire_nliil111l_dataout <= nii01li WHEN niOO01ii = '1' ELSE wire_nliil0lli_dataout; + wire_nliil111O_dataout <= nii01ll WHEN niOO01ii = '1' ELSE wire_nliil0lll_dataout; + wire_nliil11i_dataout <= nlliO10O WHEN niOO1OOil = '1' ELSE wire_nliil1iO_dataout; + wire_nliil11ii_dataout <= nii01OO WHEN niOO01ii = '1' ELSE wire_nliil0lOO_dataout; + wire_nliil11il_dataout <= nii001i WHEN niOO01ii = '1' ELSE wire_nliil0O1i_dataout; + wire_nliil11iO_dataout <= nii001l WHEN niOO01ii = '1' ELSE wire_nliil0O1l_dataout; + wire_nliil11l_dataout <= nlliO1ii WHEN niOO1OOil = '1' ELSE wire_nliil1li_dataout; + wire_nliil11li_dataout <= nii001O WHEN niOO01ii = '1' ELSE wire_nliil0O1O_dataout; + wire_nliil11ll_dataout <= nii000i WHEN niOO01ii = '1' ELSE wire_nliil0O0i_dataout; + wire_nliil11lO_dataout <= nii000l WHEN niOO01ii = '1' ELSE wire_nliil0O0l_dataout; + wire_nliil11O_dataout <= nlliO1il WHEN niOO1OOil = '1' ELSE wire_nliil1ll_dataout; + wire_nliil11Oi_dataout <= nii000O WHEN niOO01ii = '1' ELSE wire_nliil0O0O_dataout; + wire_nliil11Ol_dataout <= nii00ii WHEN niOO01ii = '1' ELSE wire_nliil0Oii_dataout; + wire_nliil11OO_dataout <= nii00il WHEN niOO01ii = '1' ELSE wire_nliil0Oil_dataout; + wire_nliil1i0i_dataout <= nii0ilO WHEN niOO01ii = '1' ELSE wire_nliill11l_dataout; + wire_nliil1i0l_dataout <= nii0iOi WHEN niOO01ii = '1' ELSE wire_nliill11O_dataout; + wire_nliil1i0O_dataout <= nii0iOl WHEN niOO01ii = '1' ELSE wire_nliill10i_dataout; + wire_nliil1i1i_dataout <= nii0iiO WHEN niOO01ii = '1' ELSE wire_nliiliOOl_dataout; + wire_nliil1i1l_dataout <= nii0ili WHEN niOO01ii = '1' ELSE wire_nliiliOOO_dataout; + wire_nliil1i1O_dataout <= nii0ill WHEN niOO01ii = '1' ELSE wire_nliill11i_dataout; + wire_nliil1ii_dataout <= nlliO1lO WHEN niOO1OOil = '1' ELSE wire_nliil1OO_dataout; + wire_nliil1iii_dataout <= nii0iOO WHEN niOO01ii = '1' ELSE wire_nliill10l_dataout; + wire_nliil1iil_dataout <= nii0l1i WHEN niOO01ii = '1' ELSE wire_nliill10O_dataout; + wire_nliil1iiO_dataout <= nii0l1l WHEN niOO01ii = '1' ELSE wire_nliill1ii_dataout; + wire_nliil1il_dataout <= niOO01l0i WHEN niOO1OOii = '1' ELSE wire_nliil01i_dataout; + wire_nliil1ili_dataout <= nii0l1O WHEN niOO01ii = '1' ELSE wire_nliill1il_dataout; + wire_nliil1ill_dataout <= nii0l0i WHEN niOO01ii = '1' ELSE wire_nliill1iO_dataout; + wire_nliil1ilO_dataout <= nii0l0l WHEN niOO01ii = '1' ELSE wire_nliill1li_dataout; + wire_nliil1iO_dataout <= wire_nl1lO11li_dataout WHEN niOO1OOii = '1' ELSE wire_nliil01l_dataout; + wire_nliil1iOi_dataout <= nii0l0O WHEN niOO01ii = '1' ELSE wire_nliill1ll_dataout; + wire_nliil1iOl_dataout <= nii0lii WHEN niOO01ii = '1' ELSE wire_nliill1lO_dataout; + wire_nliil1iOO_dataout <= nii0lil WHEN niOO01ii = '1' ELSE wire_nliill1Oi_dataout; + wire_nliil1l0i_dataout <= nii0llO WHEN niOO01ii = '1' ELSE wire_nliill01l_dataout; + wire_nliil1l0l_dataout <= nii0lOi WHEN niOO01ii = '1' ELSE wire_nliill01O_dataout; + wire_nliil1l0O_dataout <= nii0lOl WHEN niOO01ii = '1' ELSE wire_nliill00i_dataout; + wire_nliil1l1i_dataout <= nii0liO WHEN niOO01ii = '1' ELSE wire_nliill1Ol_dataout; + wire_nliil1l1l_dataout <= nii0lli WHEN niOO01ii = '1' ELSE wire_nliill1OO_dataout; + wire_nliil1l1O_dataout <= nii0lll WHEN niOO01ii = '1' ELSE wire_nliill01i_dataout; + wire_nliil1li_dataout <= wire_nl1lO11ll_dataout WHEN niOO1OOii = '1' ELSE wire_nliil01O_dataout; + wire_nliil1lii_dataout <= nii0lOO WHEN niOO01ii = '1' ELSE wire_nliill00l_dataout; + wire_nliil1lil_dataout <= nii0O1i WHEN niOO01ii = '1' ELSE wire_nliill00O_dataout; + wire_nliil1liO_dataout <= nii0O1l WHEN niOO01ii = '1' ELSE wire_nliill0ii_dataout; + wire_nliil1ll_dataout <= wire_nl1lO11lO_dataout WHEN niOO1OOii = '1' ELSE wire_nliil00i_dataout; + wire_nliil1lli_dataout <= nii0O1O WHEN niOO01ii = '1' ELSE wire_nliill0il_dataout; + wire_nliil1lll_dataout <= nii0O0i WHEN niOO01ii = '1' ELSE wire_nliill0iO_dataout; + wire_nliil1llO_dataout <= nii0O0l WHEN niOO01ii = '1' ELSE wire_nliill0li_dataout; + wire_nliil1lO_dataout <= wire_nl1lO11Oi_dataout WHEN niOO1OOii = '1' ELSE wire_nliil00l_dataout; + wire_nliil1lOi_dataout <= nii0O0O WHEN niOO01ii = '1' ELSE wire_nliill0ll_dataout; + wire_nliil1lOl_dataout <= nii0Oii WHEN niOO01ii = '1' ELSE wire_nliill0lO_dataout; + wire_nliil1lOO_dataout <= nii0Oil WHEN niOO01ii = '1' ELSE wire_nliill0Oi_dataout; + wire_nliil1O0i_dataout <= nii0OlO WHEN niOO01ii = '1' ELSE wire_nliilli1l_dataout; + wire_nliil1O0l_dataout <= nii0OOi WHEN niOO01ii = '1' ELSE wire_nliilli1O_dataout; + wire_nliil1O0O_dataout <= nii0OOl WHEN niOO01ii = '1' ELSE wire_nliilli0i_dataout; + wire_nliil1O1i_dataout <= nii0OiO WHEN niOO01ii = '1' ELSE wire_nliill0Ol_dataout; + wire_nliil1O1l_dataout <= nii0Oli WHEN niOO01ii = '1' ELSE wire_nliill0OO_dataout; + wire_nliil1O1O_dataout <= nii0Oll WHEN niOO01ii = '1' ELSE wire_nliilli1i_dataout; + wire_nliil1Oi_dataout <= wire_nl1lO11Ol_dataout WHEN niOO1OOii = '1' ELSE wire_nliil00O_dataout; + wire_nliil1Oii_dataout <= nii0OOO WHEN niOO01ii = '1' ELSE wire_nliilli0l_dataout; + wire_nliil1Oil_dataout <= niii11i WHEN niOO01ii = '1' ELSE wire_nliilli0O_dataout; + wire_nliil1OiO_dataout <= niii11l WHEN niOO01ii = '1' ELSE wire_nliilliii_dataout; + wire_nliil1Ol_dataout <= wire_nl1lO11OO_dataout WHEN niOO1OOii = '1' ELSE wire_nliil0ii_dataout; + wire_nliil1Oli_dataout <= niii11O WHEN niOO01ii = '1' ELSE wire_nliilliil_dataout; + wire_nliil1Oll_dataout <= niii10i WHEN niOO01ii = '1' ELSE wire_nliilliiO_dataout; + wire_nliil1OlO_dataout <= niii10l WHEN niOO01ii = '1' ELSE wire_nliillili_dataout; + wire_nliil1OO_dataout <= wire_nl1lO101i_dataout WHEN niOO1OOii = '1' ELSE wire_nliil0il_dataout; + wire_nliil1OOi_dataout <= niii10O WHEN niOO01ii = '1' ELSE wire_nliillill_dataout; + wire_nliil1OOl_dataout <= niii1ii WHEN niOO01ii = '1' ELSE wire_nliillilO_dataout; + wire_nliil1OOO_dataout <= niii1il WHEN niOO01ii = '1' ELSE wire_nliilliOi_dataout; + wire_nliili00i_dataout <= wire_nilOiiil_dataout AND nliiill1O; + wire_nliili00l_dataout <= wire_nilOiiiO_dataout AND nliiill1O; + wire_nliili00O_dataout <= wire_nilOiili_dataout AND nliiill1O; + wire_nliili01i_dataout <= wire_nilOii0l_dataout AND nliiill1O; + wire_nliili01l_dataout <= wire_nilOii0O_dataout AND nliiill1O; + wire_nliili01O_dataout <= wire_nilOiiii_dataout AND nliiill1O; + wire_nliili0ii_dataout <= wire_nilOiill_dataout AND nliiill1O; + wire_nliili0il_dataout <= wire_nilOiilO_dataout AND nliiill1O; + wire_nliili0iO_dataout <= wire_nilOiiOi_dataout AND nliiill1O; + wire_nliili0li_dataout <= wire_nilOiiOl_dataout AND nliiill1O; + wire_nliili0ll_dataout <= wire_nilOiiOO_dataout AND nliiill1O; + wire_nliili0lO_dataout <= wire_nilOil1i_dataout AND nliiill1O; + wire_nliili0Oi_dataout <= wire_nilOil1l_dataout AND nliiill1O; + wire_nliili0Ol_dataout <= wire_nilOil1O_dataout AND nliiill1O; + wire_nliili0OO_dataout <= wire_nilOil0i_dataout AND nliiill1O; + wire_nliili10i_dataout <= wire_nilOl1lO_dataout WHEN niOill1il = '1' ELSE nliiiillO; + wire_nliili10l_dataout <= wire_nilOl1Oi_dataout WHEN niOill1il = '1' ELSE nliiiilOi; + wire_nliili10O_dataout <= wire_nilOl1Ol_dataout WHEN niOill1il = '1' ELSE nliiiilOl; + wire_nliili11i_dataout <= wire_nilOl1iO_dataout WHEN niOill1il = '1' ELSE nliiiiliO; + wire_nliili11l_dataout <= wire_nilOl1li_dataout WHEN niOill1il = '1' ELSE nliiiilli; + wire_nliili11O_dataout <= wire_nilOl1ll_dataout WHEN niOill1il = '1' ELSE nliiiilll; + wire_nliili1i_dataout <= nliO0l1l WHEN niOO1OO0l = '1' ELSE nlli101ll; + wire_nliili1ii_dataout <= wire_nilOl1OO_dataout WHEN niOill1il = '1' ELSE nliiiiO1i; + wire_nliili1il_dataout <= wire_nilOi0lO_dataout AND nliiill1O; + wire_nliili1iO_dataout <= wire_nilOi0Oi_dataout AND nliiill1O; + wire_nliili1li_dataout <= wire_nilOi0Ol_dataout AND nliiill1O; + wire_nliili1ll_dataout <= wire_nilOi0OO_dataout AND nliiill1O; + wire_nliili1lO_dataout <= wire_nilOii1i_dataout AND nliiill1O; + wire_nliili1Oi_dataout <= wire_nilOii1l_dataout AND nliiill1O; + wire_nliili1Ol_dataout <= wire_nilOii1O_dataout AND nliiill1O; + wire_nliili1OO_dataout <= wire_nilOii0i_dataout AND nliiill1O; + wire_nliilii0i_dataout <= wire_nilOilil_dataout AND nliiill1O; + wire_nliilii0l_dataout <= wire_nilOiliO_dataout AND nliiill1O; + wire_nliilii0O_dataout <= wire_nilOilli_dataout AND nliiill1O; + wire_nliilii1i_dataout <= wire_nilOil0l_dataout AND nliiill1O; + wire_nliilii1l_dataout <= wire_nilOil0O_dataout AND nliiill1O; + wire_nliilii1O_dataout <= wire_nilOilii_dataout AND nliiill1O; + wire_nliiliiii_dataout <= wire_nilOilll_dataout AND nliiill1O; + wire_nliiliiil_dataout <= wire_nilOillO_dataout AND nliiill1O; + wire_nliiliiiO_dataout <= wire_nilOilOi_dataout AND nliiill1O; + wire_nliiliil_dataout <= nllilO0i WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nliiliiO_dataout; + wire_nliiliill_dataout <= ni0Ol0O AND niii0iO; + wire_nliiliilO_dataout <= nii1l0l AND niii0iO; + wire_nliiliiO_dataout <= niOO010iO AND niOO0100O; + wire_nliiliiOi_dataout <= nii1l0O AND niii0iO; + wire_nliiliiOl_dataout <= nii1lii AND niii0iO; + wire_nliiliiOO_dataout <= nii1lil AND niii0iO; + wire_nliilil0i_dataout <= nii1llO AND niii0iO; + wire_nliilil0l_dataout <= nii1lOi AND niii0iO; + wire_nliilil0O_dataout <= nii1lOl AND niii0iO; + wire_nliilil1i_dataout <= nii1liO AND niii0iO; + wire_nliilil1l_dataout <= nii1lli AND niii0iO; + wire_nliilil1O_dataout <= nii1lll AND niii0iO; + wire_nliilili_dataout <= wire_w_lg_w_k_hip_range2413w5753w(0) WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nliilill_dataout; + wire_nliililii_dataout <= nii1lOO AND niii0iO; + wire_nliililil_dataout <= nii1O1i AND niii0iO; + wire_nliililiO_dataout <= nii1O1l AND niii0iO; + wire_nliilill_dataout <= (nll0OiOi OR niOO010ll) WHEN (nll0OilO AND wire_w_lg_niOO010iO5648w(0)) = '1' ELSE niOO010ll; + wire_nliililli_dataout <= nii1O1O AND niii0iO; + wire_nliililll_dataout <= nii1O0i AND niii0iO; + wire_nliilillO_dataout <= nii1O0l AND niii0iO; + wire_nliililOi_dataout <= nii1O0O AND niii0iO; + wire_nliililOl_dataout <= nii1Oii AND niii0iO; + wire_nliililOO_dataout <= nii1Oil AND niii0iO; + wire_nliiliO0i_dataout <= nii1OlO AND niii0iO; + wire_nliiliO0l_dataout <= nii1OOi AND niii0iO; + wire_nliiliO0O_dataout <= nii1OOl AND niii0iO; + wire_nliiliO1i_dataout <= nii1OiO AND niii0iO; + wire_nliiliO1l_dataout <= nii1Oli AND niii0iO; + wire_nliiliO1O_dataout <= nii1Oll AND niii0iO; + wire_nliiliOii_dataout <= nii1OOO AND niii0iO; + wire_nliiliOil_dataout <= nii011i AND niii0iO; + wire_nliiliOiO_dataout <= nii011l AND niii0iO; + wire_nliiliOl_dataout <= nllilO0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nll0OiOO; + wire_nliiliOli_dataout <= nii011O AND niii0iO; + wire_nliiliOll_dataout <= nii010i AND niii0iO; + wire_nliiliOlO_dataout <= nii010l AND niii0iO; + wire_nliiliOO_dataout <= nll0OiOl AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nliiliOOi_dataout <= wire_nliillO1l_dataout WHEN niOill1li = '1' ELSE nliiiiO1l; + wire_nliiliOOl_dataout <= wire_nliillO1O_dataout WHEN niOill1li = '1' ELSE nliiiiO1O; + wire_nliiliOOO_dataout <= wire_nliillO0i_dataout WHEN niOill1li = '1' ELSE nliiiiO0i; + wire_nliill00i_dataout <= wire_nliilO1il_dataout WHEN niOill1li = '1' ELSE nliiil1il; + wire_nliill00l_dataout <= wire_nliilO1iO_dataout WHEN niOill1li = '1' ELSE nliiil1iO; + wire_nliill00O_dataout <= wire_nliilO1li_dataout WHEN niOill1li = '1' ELSE nliiil1li; + wire_nliill01i_dataout <= wire_nliilO10l_dataout WHEN niOill1li = '1' ELSE nliiil10l; + wire_nliill01l_dataout <= wire_nliilO10O_dataout WHEN niOill1li = '1' ELSE nliiil10O; + wire_nliill01O_dataout <= wire_nliilO1ii_dataout WHEN niOill1li = '1' ELSE nliiil1ii; + wire_nliill0i_dataout <= wire_nl1lO01ii_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOiil_dataout; + wire_nliill0ii_dataout <= wire_nliilO1ll_dataout WHEN niOill1li = '1' ELSE nliiil1ll; + wire_nliill0il_dataout <= wire_nliilO1lO_dataout WHEN niOill1li = '1' ELSE nliiil1lO; + wire_nliill0iO_dataout <= wire_nliilO1Oi_dataout WHEN niOill1li = '1' ELSE nliiil1Oi; + wire_nliill0l_dataout <= wire_nl1lO01il_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOiiO_dataout; + wire_nliill0li_dataout <= wire_nliilO1Ol_dataout WHEN niOill1li = '1' ELSE nliiil1Ol; + wire_nliill0ll_dataout <= wire_nliilO1OO_dataout WHEN niOill1li = '1' ELSE nliiil1OO; + wire_nliill0lO_dataout <= wire_nliilO01i_dataout WHEN niOill1li = '1' ELSE nliiil01i; + wire_nliill0O_dataout <= wire_nl1lO01iO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOili_dataout; + wire_nliill0Oi_dataout <= wire_nliilO01l_dataout WHEN niOill1li = '1' ELSE nliiil01l; + wire_nliill0Ol_dataout <= wire_nliilO01O_dataout WHEN niOill1li = '1' ELSE nliiil01O; + wire_nliill0OO_dataout <= wire_nliilO00i_dataout WHEN niOill1li = '1' ELSE nliiil00i; + wire_nliill10i_dataout <= wire_nliillOil_dataout WHEN niOill1li = '1' ELSE nliiiiOil; + wire_nliill10l_dataout <= wire_nliillOiO_dataout WHEN niOill1li = '1' ELSE nliiiiOiO; + wire_nliill10O_dataout <= wire_nliillOli_dataout WHEN niOill1li = '1' ELSE nliiiiOli; + wire_nliill11i_dataout <= wire_nliillO0l_dataout WHEN niOill1li = '1' ELSE nliiiiO0l; + wire_nliill11l_dataout <= wire_nliillO0O_dataout WHEN niOill1li = '1' ELSE nliiiiO0O; + wire_nliill11O_dataout <= wire_nliillOii_dataout WHEN niOill1li = '1' ELSE nliiiiOii; + wire_nliill1i_dataout <= wire_nl1lO010i_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOi0l_dataout; + wire_nliill1ii_dataout <= wire_nliillOll_dataout WHEN niOill1li = '1' ELSE nliiiiOll; + wire_nliill1il_dataout <= wire_nliillOlO_dataout WHEN niOill1li = '1' ELSE nliiiiOlO; + wire_nliill1iO_dataout <= wire_nliillOOi_dataout WHEN niOill1li = '1' ELSE nliiiiOOi; + wire_nliill1l_dataout <= wire_nl1lO010l_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOi0O_dataout; + wire_nliill1li_dataout <= wire_nliillOOl_dataout WHEN niOill1li = '1' ELSE nliiiiOOl; + wire_nliill1ll_dataout <= wire_nliillOOO_dataout WHEN niOill1li = '1' ELSE nliiiiOOO; + wire_nliill1lO_dataout <= wire_nliilO11i_dataout WHEN niOill1li = '1' ELSE nliiil11i; + wire_nliill1O_dataout <= wire_nl1lO010O_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOiii_dataout; + wire_nliill1Oi_dataout <= wire_nliilO11l_dataout WHEN niOill1li = '1' ELSE nliiil11l; + wire_nliill1Ol_dataout <= wire_nliilO11O_dataout WHEN niOill1li = '1' ELSE nliiil11O; + wire_nliill1OO_dataout <= wire_nliilO10i_dataout WHEN niOill1li = '1' ELSE nliiil10i; + wire_nliilli0i_dataout <= wire_nliilO0il_dataout WHEN niOill1li = '1' ELSE nliiil0il; + wire_nliilli0l_dataout <= wire_nliilO0iO_dataout WHEN niOill1li = '1' ELSE nliiil0iO; + wire_nliilli0O_dataout <= wire_nliilO0li_dataout WHEN niOill1li = '1' ELSE nliiil0li; + wire_nliilli1i_dataout <= wire_nliilO00l_dataout WHEN niOill1li = '1' ELSE nliiil00l; + wire_nliilli1l_dataout <= wire_nliilO00O_dataout WHEN niOill1li = '1' ELSE nliiil00O; + wire_nliilli1O_dataout <= wire_nliilO0ii_dataout WHEN niOill1li = '1' ELSE nliiil0ii; + wire_nliillii_dataout <= wire_nl1lO01li_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOill_dataout; + wire_nliilliii_dataout <= wire_nliilO0ll_dataout WHEN niOill1li = '1' ELSE nliiil0ll; + wire_nliilliil_dataout <= wire_nliilO0lO_dataout WHEN niOill1li = '1' ELSE nliiil0lO; + wire_nliilliiO_dataout <= wire_nliilO0Oi_dataout WHEN niOill1li = '1' ELSE nliiil0Oi; + wire_nliillil_dataout <= wire_nl1lO01ll_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOilO_dataout; + wire_nliillili_dataout <= wire_nliilO0Ol_dataout WHEN niOill1li = '1' ELSE nliiil0Ol; + wire_nliillill_dataout <= wire_nliilO0OO_dataout WHEN niOill1li = '1' ELSE nliiil0OO; + wire_nliillilO_dataout <= wire_nliilOi1i_dataout WHEN niOill1li = '1' ELSE nliiili1i; + wire_nliilliO_dataout <= wire_nl1lO01lO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOiOi_dataout; + wire_nliilliOi_dataout <= wire_nliilOi1l_dataout WHEN niOill1li = '1' ELSE nliiili1l; + wire_nliilliOl_dataout <= wire_nliilOi1O_dataout WHEN niOill1li = '1' ELSE nliiili1O; + wire_nliilliOO_dataout <= wire_nliilOi0i_dataout WHEN niOill1li = '1' ELSE nliiili0i; + wire_nliilll0i_dataout <= wire_nliilOiil_dataout WHEN niOill1li = '1' ELSE nliiiliil; + wire_nliilll0l_dataout <= wire_nliilOiiO_dataout WHEN niOill1li = '1' ELSE nliiiliiO; + wire_nliilll0O_dataout <= wire_nliilOili_dataout WHEN niOill1li = '1' ELSE nliiilili; + wire_nliilll1i_dataout <= wire_nliilOi0l_dataout WHEN niOill1li = '1' ELSE nliiili0l; + wire_nliilll1l_dataout <= wire_nliilOi0O_dataout WHEN niOill1li = '1' ELSE nliiili0O; + wire_nliilll1O_dataout <= wire_nliilOiii_dataout WHEN niOill1li = '1' ELSE nliiiliii; + wire_nliillli_dataout <= wire_nl1lO01Oi_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOiOl_dataout; + wire_nliilllii_dataout <= wire_nliilOill_dataout WHEN niOill1li = '1' ELSE nliiilill; + wire_nliilllil_dataout <= wire_nliilOilO_dataout WHEN niOill1li = '1' ELSE nliiililO; + wire_nliillliO_dataout <= wire_nliilOiOi_dataout WHEN niOill1li = '1' ELSE nliiiliOi; + wire_nliillll_dataout <= wire_nl1lO01Ol_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOiOO_dataout; + wire_nliilllli_dataout <= wire_nliilOiOl_dataout WHEN niOill1li = '1' ELSE nliiiliOl; + wire_nliilllll_dataout <= wire_nliilOiOO_dataout WHEN niOill1li = '1' ELSE nliiiliOO; + wire_nliillllO_dataout <= wire_nliilOl1i_dataout WHEN niOill1li = '1' ELSE nliiill1i; + wire_nliilllO_dataout <= wire_nl1lO01OO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOl1i_dataout; + wire_nliilllOi_dataout <= wire_nliilOl1l_dataout WHEN niOill1li = '1' ELSE nliiill1l; + wire_nliilllOl_dataout <= wire_nliilOl1O_dataout WHEN niOill1li = '1' ELSE nliiill1O; + wire_nliilllOO_dataout <= wire_nliilOl0i_dataout WHEN niOill1li = '1' ELSE nliiill0i; + wire_nliillO0i_dataout <= wire_nilOi0Ol_dataout WHEN niOill1iO = '1' ELSE nliiiiO0i; + wire_nliillO0l_dataout <= wire_nilOi0OO_dataout WHEN niOill1iO = '1' ELSE nliiiiO0l; + wire_nliillO0O_dataout <= wire_nilOii1i_dataout WHEN niOill1iO = '1' ELSE nliiiiO0O; + wire_nliillO1i_dataout <= wire_nliilOl0l_dataout WHEN niOill1li = '1' ELSE nliiill0l; + wire_nliillO1l_dataout <= wire_nilOi0lO_dataout WHEN niOill1iO = '1' ELSE nliiiiO1l; + wire_nliillO1O_dataout <= wire_nilOi0Oi_dataout WHEN niOill1iO = '1' ELSE nliiiiO1O; + wire_nliillOi_dataout <= wire_nl1lO001i_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOl1l_dataout; + wire_nliillOii_dataout <= wire_nilOii1l_dataout WHEN niOill1iO = '1' ELSE nliiiiOii; + wire_nliillOil_dataout <= wire_nilOii1O_dataout WHEN niOill1iO = '1' ELSE nliiiiOil; + wire_nliillOiO_dataout <= wire_nilOii0i_dataout WHEN niOill1iO = '1' ELSE nliiiiOiO; + wire_nliillOl_dataout <= wire_nl1lO001l_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOl1O_dataout; + wire_nliillOli_dataout <= wire_nilOii0l_dataout WHEN niOill1iO = '1' ELSE nliiiiOli; + wire_nliillOll_dataout <= wire_nilOii0O_dataout WHEN niOill1iO = '1' ELSE nliiiiOll; + wire_nliillOlO_dataout <= wire_nilOiiii_dataout WHEN niOill1iO = '1' ELSE nliiiiOlO; + wire_nliillOO_dataout <= wire_nl1lO001O_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOl0i_dataout; + wire_nliillOOi_dataout <= wire_nilOiiil_dataout WHEN niOill1iO = '1' ELSE nliiiiOOi; + wire_nliillOOl_dataout <= wire_nilOiiiO_dataout WHEN niOill1iO = '1' ELSE nliiiiOOl; + wire_nliillOOO_dataout <= wire_nilOiili_dataout WHEN niOill1iO = '1' ELSE nliiiiOOO; + wire_nliilO00i_dataout <= wire_nilOilOl_dataout WHEN niOill1iO = '1' ELSE nliiil00i; + wire_nliilO00l_dataout <= wire_nilOilOO_dataout WHEN niOill1iO = '1' ELSE nliiil00l; + wire_nliilO00O_dataout <= wire_nilOiO1i_dataout WHEN niOill1iO = '1' ELSE nliiil00O; + wire_nliilO01i_dataout <= wire_nilOilll_dataout WHEN niOill1iO = '1' ELSE nliiil01i; + wire_nliilO01l_dataout <= wire_nilOillO_dataout WHEN niOill1iO = '1' ELSE nliiil01l; + wire_nliilO01O_dataout <= wire_nilOilOi_dataout WHEN niOill1iO = '1' ELSE nliiil01O; + wire_nliilO0i_dataout <= wire_nl1lO00ii_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOlil_dataout; + wire_nliilO0ii_dataout <= wire_nilOiO1l_dataout WHEN niOill1iO = '1' ELSE nliiil0ii; + wire_nliilO0il_dataout <= wire_nilOiO1O_dataout WHEN niOill1iO = '1' ELSE nliiil0il; + wire_nliilO0iO_dataout <= wire_nilOiO0i_dataout WHEN niOill1iO = '1' ELSE nliiil0iO; + wire_nliilO0l_dataout <= wire_nl1lO00il_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOliO_dataout; + wire_nliilO0li_dataout <= wire_nilOiO0l_dataout WHEN niOill1iO = '1' ELSE nliiil0li; + wire_nliilO0ll_dataout <= wire_nilOiO0O_dataout WHEN niOill1iO = '1' ELSE nliiil0ll; + wire_nliilO0lO_dataout <= wire_nilOiOii_dataout WHEN niOill1iO = '1' ELSE nliiil0lO; + wire_nliilO0O_dataout <= wire_nl1lO00iO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOlli_dataout; + wire_nliilO0Oi_dataout <= wire_nilOiOil_dataout WHEN niOill1iO = '1' ELSE nliiil0Oi; + wire_nliilO0Ol_dataout <= wire_nilOiOiO_dataout WHEN niOill1iO = '1' ELSE nliiil0Ol; + wire_nliilO0OO_dataout <= wire_nilOiOli_dataout WHEN niOill1iO = '1' ELSE nliiil0OO; + wire_nliilO10i_dataout <= wire_nilOiiOl_dataout WHEN niOill1iO = '1' ELSE nliiil10i; + wire_nliilO10l_dataout <= wire_nilOiiOO_dataout WHEN niOill1iO = '1' ELSE nliiil10l; + wire_nliilO10O_dataout <= wire_nilOil1i_dataout WHEN niOill1iO = '1' ELSE nliiil10O; + wire_nliilO11i_dataout <= wire_nilOiill_dataout WHEN niOill1iO = '1' ELSE nliiil11i; + wire_nliilO11l_dataout <= wire_nilOiilO_dataout WHEN niOill1iO = '1' ELSE nliiil11l; + wire_nliilO11O_dataout <= wire_nilOiiOi_dataout WHEN niOill1iO = '1' ELSE nliiil11O; + wire_nliilO1i_dataout <= wire_nl1lO000i_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOl0l_dataout; + wire_nliilO1ii_dataout <= wire_nilOil1l_dataout WHEN niOill1iO = '1' ELSE nliiil1ii; + wire_nliilO1il_dataout <= wire_nilOil1O_dataout WHEN niOill1iO = '1' ELSE nliiil1il; + wire_nliilO1iO_dataout <= wire_nilOil0i_dataout WHEN niOill1iO = '1' ELSE nliiil1iO; + wire_nliilO1l_dataout <= wire_nl1lO000l_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOl0O_dataout; + wire_nliilO1li_dataout <= wire_nilOil0l_dataout WHEN niOill1iO = '1' ELSE nliiil1li; + wire_nliilO1ll_dataout <= wire_nilOil0O_dataout WHEN niOill1iO = '1' ELSE nliiil1ll; + wire_nliilO1lO_dataout <= wire_nilOilii_dataout WHEN niOill1iO = '1' ELSE nliiil1lO; + wire_nliilO1O_dataout <= wire_nl1lO000O_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOlii_dataout; + wire_nliilO1Oi_dataout <= wire_nilOilil_dataout WHEN niOill1iO = '1' ELSE nliiil1Oi; + wire_nliilO1Ol_dataout <= wire_nilOiliO_dataout WHEN niOill1iO = '1' ELSE nliiil1Ol; + wire_nliilO1OO_dataout <= wire_nilOilli_dataout WHEN niOill1iO = '1' ELSE nliiil1OO; + wire_nliilOi0i_dataout <= wire_nilOiOOl_dataout WHEN niOill1iO = '1' ELSE nliiili0i; + wire_nliilOi0l_dataout <= wire_nilOiOOO_dataout WHEN niOill1iO = '1' ELSE nliiili0l; + wire_nliilOi0O_dataout <= wire_nilOl11i_dataout WHEN niOill1iO = '1' ELSE nliiili0O; + wire_nliilOi1i_dataout <= wire_nilOiOll_dataout WHEN niOill1iO = '1' ELSE nliiili1i; + wire_nliilOi1l_dataout <= wire_nilOiOlO_dataout WHEN niOill1iO = '1' ELSE nliiili1l; + wire_nliilOi1O_dataout <= wire_nilOiOOi_dataout WHEN niOill1iO = '1' ELSE nliiili1O; + wire_nliilOii_dataout <= wire_nl1lO00li_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOlll_dataout; + wire_nliilOiii_dataout <= wire_nilOl11l_dataout WHEN niOill1iO = '1' ELSE nliiiliii; + wire_nliilOiil_dataout <= wire_nilOl11O_dataout WHEN niOill1iO = '1' ELSE nliiiliil; + wire_nliilOiiO_dataout <= wire_nilOl10i_dataout WHEN niOill1iO = '1' ELSE nliiiliiO; + wire_nliilOil_dataout <= wire_nl1lO00ll_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOllO_dataout; + wire_nliilOili_dataout <= wire_nilOl10l_dataout WHEN niOill1iO = '1' ELSE nliiilili; + wire_nliilOill_dataout <= wire_nilOl10O_dataout WHEN niOill1iO = '1' ELSE nliiilill; + wire_nliilOilO_dataout <= wire_nilOl1ii_dataout WHEN niOill1iO = '1' ELSE nliiililO; + wire_nliilOiO_dataout <= wire_nl1lO00lO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOlOi_dataout; + wire_nliilOiOi_dataout <= wire_nilOl1il_dataout WHEN niOill1iO = '1' ELSE nliiiliOi; + wire_nliilOiOl_dataout <= wire_nilOl1iO_dataout WHEN niOill1iO = '1' ELSE nliiiliOl; + wire_nliilOiOO_dataout <= wire_nilOl1li_dataout WHEN niOill1iO = '1' ELSE nliiiliOO; + wire_nliilOl0i_dataout <= wire_nilOl1Ol_dataout WHEN niOill1iO = '1' ELSE nliiill0i; + wire_nliilOl0l_dataout <= wire_nilOl1OO_dataout WHEN niOill1iO = '1' ELSE nliiill0l; + wire_nliilOl1i_dataout <= wire_nilOl1ll_dataout WHEN niOill1iO = '1' ELSE nliiill1i; + wire_nliilOl1l_dataout <= wire_nilOl1lO_dataout WHEN niOill1iO = '1' ELSE nliiill1l; + wire_nliilOl1O_dataout <= wire_nilOl1Oi_dataout WHEN niOill1iO = '1' ELSE nliiill1O; + wire_nliilOli_dataout <= wire_nl1lO00Oi_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOlOl_dataout; + wire_nliilOlil_dataout <= wire_nliilOlOi_dataout AND NOT(niOill1ll); + wire_nliilOliO_dataout <= wire_nliilOlOl_dataout AND NOT(niOill1ll); + wire_nliilOll_dataout <= wire_nl1lO00Ol_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOlOO_dataout; + wire_nliilOlli_dataout <= wire_nliilOlOO_dataout OR niOill1ll; + wire_nliilOlll_dataout <= wire_nliilOO1i_dataout AND NOT(niOill1ll); + wire_nliilOllO_dataout <= wire_nliilOO1l_dataout OR niOill1ll; + wire_nliilOlO_dataout <= wire_nl1lO00OO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOO1i_dataout; + wire_nliilOlOi_dataout <= wire_nliilOO1O_dataout OR niOill1lO; + wire_nliilOlOl_dataout <= wire_nliilOO0i_dataout OR niOill1lO; + wire_nliilOlOO_dataout <= wire_nliilOO0l_dataout AND NOT(niOill1lO); + wire_nliilOO0i_dataout <= wire_nliilOOiO_dataout OR niOill1Oi; + wire_nliilOO0l_dataout <= wire_nliilOOli_dataout AND NOT(niOill1Oi); + wire_nliilOO0O_dataout <= wire_nliilOOll_dataout AND NOT(niOill1Oi); + wire_nliilOO1i_dataout <= wire_nliilOO0O_dataout AND NOT(niOill1lO); + wire_nliilOO1l_dataout <= wire_nliilOOii_dataout OR niOill1lO; + wire_nliilOO1O_dataout <= wire_nliilOOil_dataout AND NOT(niOill1Oi); + wire_nliilOOi_dataout <= wire_nl1lOOl0O_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOO1l_dataout; + wire_nliilOOii_dataout <= wire_nliilOOlO_dataout OR niOill1Oi; + wire_nliilOOil_dataout <= wire_nliilOOOi_dataout OR niOill1Ol; + wire_nliilOOiO_dataout <= wire_nliilOOOl_dataout AND NOT(niOill1Ol); + wire_nliilOOl_dataout <= wire_nl1lOOlii_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOO1O_dataout; + wire_nliilOOli_dataout <= wire_nliilOOOO_dataout AND NOT(niOill1Ol); + wire_nliilOOll_dataout <= wire_nliiO111i_dataout AND NOT(niOill1Ol); + wire_nliilOOlO_dataout <= niOill1OO OR niOill1Ol; + wire_nliilOOO_dataout <= wire_nl1lOOlil_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOO0i_dataout; + wire_nliilOOOi_dataout <= wire_nliiO111l_dataout AND NOT(niOill1OO); + wire_nliilOOOl_dataout <= wire_nliiO111O_dataout AND NOT(niOill1OO); + wire_nliilOOOO_dataout <= wire_nliiO110i_dataout AND NOT(niOill1OO); + wire_nliiO000l_dataout <= wire_nliiO000O_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lOil_dataout AND niOilli1l))); + wire_nliiO000O_dataout <= nliiO1OOO OR wire_nilOOiil_dataout; + wire_nliiO001i_dataout <= wire_nliiO001l_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lOiO_dataout AND niOilli1l))); + wire_nliiO001l_dataout <= nliiO1OOl OR wire_nilOOiiO_dataout; + wire_nliiO00i_dataout <= wire_nl1lO1O1O_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11il_dataout; + wire_nliiO00iO_dataout <= wire_nliiO00li_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lO1l_dataout AND niOilli1l))); + wire_nliiO00l_dataout <= wire_nl1lO1O0i_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11iO_dataout; + wire_nliiO00li_dataout <= nliiO011i OR wire_nilOOi0O_dataout; + wire_nliiO00O_dataout <= wire_nl1lO1O0l_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11li_dataout; + wire_nliiO010i_dataout <= nliiO1lli OR wire_w_lg_niOill0OO44360w(0); + wire_nliiO011O_dataout <= wire_nliiO010i_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lOOO_dataout AND niOilli1i))); + wire_nliiO01i_dataout <= wire_nl1lO1lOO_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil110l_dataout; + wire_nliiO01ii_dataout <= wire_nliiO01il_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lOOl_dataout AND niOilli1i))); + wire_nliiO01il_dataout <= nliiO1OlO OR wire_nilOOili_dataout; + wire_nliiO01l_dataout <= wire_nl1lO1O1i_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil110O_dataout; + wire_nliiO01ll_dataout <= wire_nliiO01lO_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lOli_dataout AND niOilli1i))); + wire_nliiO01lO_dataout <= nliiO1OOi OR wire_nilOOill_dataout; + wire_nliiO01O_dataout <= wire_nl1lO1O1l_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11ii_dataout; + wire_nliiO0ii_dataout <= wire_nl1lO1O0O_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11ll_dataout; + wire_nliiO0il_dataout <= wire_nl1lO1Oii_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11lO_dataout; + wire_nliiO0iO_dataout <= wire_nl1lO1Oil_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11Oi_dataout; + wire_nliiO0l0i_dataout <= wire_nl0l1O10l_dataout WHEN niOilli0O = '1' ELSE nliiO0i0l; + wire_nliiO0l0l_dataout <= wire_nl0l1O10i_dataout WHEN niOilli0O = '1' ELSE nliiO0i0O; + wire_nliiO0l0O_dataout <= wire_nl0l1O11O_dataout WHEN niOilli0O = '1' ELSE nliiO0iii; + wire_nliiO0l1l_dataout <= wire_nl0l1O1ii_dataout WHEN niOilli0O = '1' ELSE nliiO011l; + wire_nliiO0l1O_dataout <= wire_nl0l1O10O_dataout WHEN niOilli0O = '1' ELSE nliiO0i0i; + wire_nliiO0li_dataout <= wire_nl1lO1OiO_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11Ol_dataout; + wire_nliiO0lil_dataout <= wire_nl0l1O11l_dataout WHEN niOilliii = '1' ELSE nliiO0iil; + wire_nliiO0liO_dataout <= wire_nl0l1O11i_dataout WHEN niOilliii = '1' ELSE nliiO0iiO; + wire_nliiO0ll_dataout <= wire_nl1lO1Oli_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil11OO_dataout; + wire_nliiO0lli_dataout <= wire_nl0l1lOOO_dataout WHEN niOilliii = '1' ELSE nliiO0ili; + wire_nliiO0lll_dataout <= wire_nl0l1lOOl_dataout WHEN niOilliii = '1' ELSE nliiO0ill; + wire_nliiO0lO_dataout <= wire_nl1lO1Oll_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil101i_dataout; + wire_nliiO0lOi_dataout <= wire_nl0l1lOii_dataout WHEN (nl0iOil1l AND (nl0iOilil AND niOillill)) = '1' ELSE nliiO0ilO; + wire_nliiO0O1i_dataout <= wire_nl0l1lO0O_dataout WHEN (nl0iOil1i AND niOilliil) = '1' ELSE nliiO0iOi; + wire_nliiO0Oi_dataout <= wire_nl1lO1OlO_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil101l_dataout; + wire_nliiO0Ol_dataout <= wire_nl1lO1OOi_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil101O_dataout; + wire_nliiO0OO_dataout <= wire_nl1lO1OOl_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil100i_dataout; + wire_nliiO10i_dataout <= wire_nl1lO1l1O_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOil_dataout; + wire_nliiO10il_dataout <= wire_nl0l1lOli_dataout WHEN (nl0iOil1l AND (nl0iOilll AND (niOillllO AND (k_conf(112) AND k_conf(217))))) = '1' ELSE nliiill0O; + wire_nliiO10l_dataout <= wire_nl1lO1l0i_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOiO_dataout; + wire_nliiO10O_dataout <= wire_nl1lO1l0l_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOli_dataout; + wire_nliiO10Oi_dataout <= wire_nl0l1lOil_dataout WHEN (nl0iOil1i AND (nl0iOilll AND (niOillllO AND (k_conf(112) AND k_conf(216))))) = '1' ELSE nliiO11OO; + wire_nliiO110i_dataout <= wire_nliiO11ii_dataout OR niOill01i; + wire_nliiO110l_dataout <= wire_nliiO11il_dataout OR niOill01i; + wire_nliiO110O_dataout <= wire_nliiO11iO_dataout AND NOT(niOill01l); + wire_nliiO111i_dataout <= wire_nliiO110l_dataout AND NOT(niOill1OO); + wire_nliiO111l_dataout <= wire_nliiO110O_dataout OR niOill01i; + wire_nliiO111O_dataout <= niOill01l OR niOill01i; + wire_nliiO11i_dataout <= wire_nl1lOOliO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOO0l_dataout; + wire_nliiO11ii_dataout <= wire_nliiO11li_dataout OR niOill01l; + wire_nliiO11il_dataout <= wire_nliiO11ll_dataout OR niOill01l; + wire_nliiO11iO_dataout <= wire_nliiO11lO_dataout OR niOill01O; + wire_nliiO11l_dataout <= wire_nl1lO0i0l_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOO0O_dataout; + wire_nliiO11li_dataout <= wire_nliiO11Oi_dataout OR niOill01O; + wire_nliiO11ll_dataout <= niOill00i OR niOill01O; + wire_nliiO11lO_dataout <= niOill00l AND NOT(niOill00i); + wire_nliiO11O_dataout <= wire_nl1lO1l1l_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOii_dataout; + wire_nliiO11Oi_dataout <= wire_nliiO11Ol_dataout OR niOill00i; + wire_nliiO11Ol_dataout <= niOill00O OR niOill00l; + wire_nliiO1i0i_dataout <= wire_nliilOliO_dataout WHEN niOill0il = '1' ELSE wire_nliiO1ili_dataout; + wire_nliiO1i0l_dataout <= wire_nliilOlli_dataout WHEN niOill0il = '1' ELSE wire_nliiO1ill_dataout; + wire_nliiO1i0O_dataout <= wire_nliilOlll_dataout WHEN niOill0il = '1' ELSE wire_nliiO1ilO_dataout; + wire_nliiO1i1O_dataout <= wire_nliilOlil_dataout WHEN niOill0il = '1' ELSE wire_nliiO1iiO_dataout; + wire_nliiO1ii_dataout <= wire_nl1lO1l0O_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOll_dataout; + wire_nliiO1iii_dataout <= wire_nliilOllO_dataout WHEN niOill0il = '1' ELSE wire_nliiO1iOi_dataout; + wire_nliiO1iil_dataout <= wire_nliiO1iOl_dataout OR niOill0il; + wire_nliiO1iiO_dataout <= nliiO101i AND NOT(niOill0ii); + wire_nliiO1il_dataout <= wire_nl1lO1lii_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOlO_dataout; + wire_nliiO1ili_dataout <= nliiO101l AND NOT(niOill0ii); + wire_nliiO1ill_dataout <= nliiO101O AND NOT(niOill0ii); + wire_nliiO1ilO_dataout <= nliiO100i AND NOT(niOill0ii); + wire_nliiO1iO_dataout <= wire_nl1lO1lil_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOOi_dataout; + wire_nliiO1iOi_dataout <= nliiO100l AND NOT(niOill0ii); + wire_nliiO1iOl_dataout <= nliiO100O AND NOT(niOill0ii); + wire_nliiO1li_dataout <= wire_nl1lO1liO_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOOl_dataout; + wire_nliiO1ll_dataout <= wire_nl1lO1lli_dataout WHEN niOO1OOOO = '1' ELSE wire_nliiOOOO_dataout; + wire_nliiO1lll_dataout <= wire_nl0l1lOOO_dataout WHEN niOill0ll = '1' ELSE nliiO10ii; + wire_nliiO1llO_dataout <= wire_nl0l1lOOl_dataout WHEN niOill0ll = '1' ELSE nliiO1l0l; + wire_nliiO1lO_dataout <= wire_nl1lO1lll_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil111i_dataout; + wire_nliiO1lOi_dataout <= wire_nl0l1lOli_dataout WHEN niOill0ll = '1' ELSE nliiO1l0O; + wire_nliiO1lOO_dataout <= wire_nl0l1lOiO_dataout WHEN niOill0lO = '1' ELSE nliiO1lii; + wire_nliiO1O1i_dataout <= wire_nl0l1lOil_dataout WHEN niOill0lO = '1' ELSE nliiO1lil; + wire_nliiO1O1l_dataout <= wire_nl0l1lO1l_dataout WHEN niOill0lO = '1' ELSE nliiO1liO; + wire_nliiO1Oi_dataout <= wire_nl1lO1llO_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil111l_dataout; + wire_nliiO1Ol_dataout <= wire_nl1lO1lOi_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil111O_dataout; + wire_nliiO1OO_dataout <= wire_nl1lO1lOl_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil110i_dataout; + wire_nliiOi0i_dataout <= wire_nl1lO011O_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil10il_dataout; + wire_nliiOi0ii_dataout <= wire_nl0l1lO0O_dataout WHEN (nl0iOil1i AND niOillilO) = '1' ELSE nliiO0OOO; + wire_nliiOi0l_dataout <= wire_nl1lO010i_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil10iO_dataout; + wire_nliiOi0O_dataout <= wire_nl1lO010l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil10li_dataout; + wire_nliiOi10i_dataout <= wire_nl0l1O10O_dataout WHEN niOilliiO = '1' ELSE nliiO0O0O; + wire_nliiOi10l_dataout <= wire_nl0l1O10l_dataout WHEN niOilliiO = '1' ELSE nliiO0Oii; + wire_nliiOi10O_dataout <= wire_nl0l1O10i_dataout WHEN niOilliiO = '1' ELSE nliiO0Oil; + wire_nliiOi11O_dataout <= wire_nl0l1O1ii_dataout WHEN niOilliiO = '1' ELSE nliiO0l1i; + wire_nliiOi1i_dataout <= wire_nl1lO1OOO_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil100l_dataout; + wire_nliiOi1ii_dataout <= wire_nl0l1O11O_dataout WHEN niOilliiO = '1' ELSE nliiO0OiO; + wire_nliiOi1iO_dataout <= wire_nl0l1O11l_dataout WHEN niOillili = '1' ELSE nliiO0Oli; + wire_nliiOi1l_dataout <= wire_nl1lO011i_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil100O_dataout; + wire_nliiOi1li_dataout <= wire_nl0l1O11i_dataout WHEN niOillili = '1' ELSE nliiO0Oll; + wire_nliiOi1ll_dataout <= wire_nl0l1lOOO_dataout WHEN niOillili = '1' ELSE nliiO0OlO; + wire_nliiOi1lO_dataout <= wire_nl0l1lOOl_dataout WHEN niOillili = '1' ELSE nliiO0OOi; + wire_nliiOi1O_dataout <= wire_nl1lO011l_dataout WHEN niOO1OOOO = '1' ELSE wire_nlil10ii_dataout; + wire_nliiOi1Ol_dataout <= wire_nl0l1lOii_dataout WHEN (nl0iOil1i AND (nl0iOilii AND niOillill)) = '1' ELSE nliiO0OOl; + wire_nliiOiii_dataout <= wire_nl1lO010O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil10ll_dataout; + wire_nliiOiil_dataout <= wire_nl1lO01ii_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil10lO_dataout; + wire_nliiOiiO_dataout <= wire_nl1lO01il_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil10Oi_dataout; + wire_nliiOiiOl_dataout <= wire_nliiOiiOO_dataout AND NOT(((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1O1ii_dataout AND niOilll1l)) OR wire_w_lg_niOilll0i44317w(0))); + wire_nliiOiiOO_dataout <= nliiOi11l OR niOO10lil; + wire_nliiOil0l_dataout <= wire_nliiOil0O_dataout AND NOT(((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1O10O_dataout AND niOilll1l)) OR (wire_w_lg_w_lg_niOilllOl44309w44310w(0) AND wire_nliiOiilO_w_lg_nliiO0i0i44311w(0)))); + wire_nliiOil0O_dataout <= nliiOii1i OR niOO10lii; + wire_nliiOili_dataout <= wire_nl1lO01iO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil10Ol_dataout; + wire_nliiOill_dataout <= wire_nl1lO01li_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil10OO_dataout; + wire_nliiOillO_dataout <= wire_nliiOilOi_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1O10l_dataout AND niOilll1l))); + wire_nliiOilO_dataout <= wire_nl1lO01ll_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1i1i_dataout; + wire_nliiOilOi_dataout <= nliiOii1l OR niOO10lOi; + wire_nliiOiO0l_dataout <= wire_nliiOiO0O_dataout AND NOT(((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1O11O_dataout AND niOilll1l)) OR wire_w_lg_niOilll0i44301w(0))); + wire_nliiOiO0O_dataout <= nliiOii0i OR niOO10lll; + wire_nliiOiO1i_dataout <= wire_nliiOiO1l_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1O10i_dataout AND niOilll1l))); + wire_nliiOiO1l_dataout <= nliiOii1O OR niOO10llO; + wire_nliiOiOi_dataout <= wire_nl1lO01lO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1i1l_dataout; + wire_nliiOiOl_dataout <= wire_nl1lO01Oi_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1i1O_dataout; + wire_nliiOiOlO_dataout <= wire_nliiOiOOi_dataout AND NOT(((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1O11l_dataout AND niOilll0l)) OR wire_w_lg_niOilll0i44295w(0))); + wire_nliiOiOO_dataout <= wire_nl1lO01Ol_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1i0i_dataout; + wire_nliiOiOOi_dataout <= nliiOii0l OR niOO1i0i; + wire_nliiOl01l_dataout <= wire_nliiOl01O_dataout AND NOT(((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lOOl_dataout AND niOilll0l)) OR wire_w_lg_niOilll0i44280w(0))); + wire_nliiOl01O_dataout <= nliiOiiiO OR nlii11i0O; + wire_nliiOl0i_dataout <= wire_nl1lO001O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1iil_dataout; + wire_nliiOl0l_dataout <= wire_nl1lO000i_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1iiO_dataout; + wire_nliiOl0li_dataout <= wire_nliiOl0ll_dataout AND NOT((wire_w_lg_w_lg_w44270w44271w44272w(0) OR (wire_nl0l1lOii_dataout AND niOilllli))); + wire_nliiOl0ll_dataout <= nliiOiili OR nliiOOill; + wire_nliiOl0O_dataout <= wire_nl1lO000l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1ili_dataout; + wire_nliiOl10i_dataout <= nliiOii0O OR niOO10liO; + wire_nliiOl10l_dataout <= wire_nliiOl10O_dataout AND NOT((niOilll1O OR (niOilll0i AND wire_nliiOiilO_w_lg_nliiO0iiO44289w(0)))); + wire_nliiOl10O_dataout <= nliiOiiii OR niOO10lli; + wire_nliiOl11O_dataout <= wire_nliiOl10i_dataout AND NOT(niOilll1O); + wire_nliiOl1i_dataout <= wire_nl1lO01OO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1i0l_dataout; + wire_nliiOl1l_dataout <= wire_nl1lO001i_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1i0O_dataout; + wire_nliiOl1ll_dataout <= wire_nliiOl1lO_dataout AND NOT(((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lOOO_dataout AND niOilll0l)) OR wire_w_lg_niOilll0i44285w(0))); + wire_nliiOl1lO_dataout <= nliiOiiil OR nl10iO1li; + wire_nliiOl1O_dataout <= wire_nl1lO001l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1iii_dataout; + wire_nliiOli0i_dataout <= nliiOiill OR wire_nilOOilO_dataout; + wire_nliiOli1O_dataout <= wire_nliiOli0i_dataout AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lO0O_dataout AND niOilllli))); + wire_nliiOlii_dataout <= wire_nl1lO000O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1ill_dataout; + wire_nliiOliii_dataout <= nliiOiiOi AND NOT((wire_w_lg_w_k_conf_range44263w44264w(0) OR (wire_nl0l1lO1l_dataout AND niOilllli))); + wire_nliiOlil_dataout <= wire_nl1lO00ii_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1ilO_dataout; + wire_nliiOliO_dataout <= wire_nl1lO00il_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1iOi_dataout; + wire_nliiOliOi_dataout <= (nl01l0lOl OR (nl01l0llO OR (nl01l0lOi OR (wire_nlill0Oll_w_lg_nl01l0l0l44252w(0) AND niOilllOi)))) WHEN (wire_nl1000i_w_lg_niOO001i44257w(0) AND wire_nl1000i_w_lg_niOO010O44258w(0)) = '1' ELSE wire_nliiOliOl_dataout; + wire_nliiOliOi_w_lg_w_lg_dataout44320w45270w(0) <= wire_nliiOliOi_w_lg_dataout44320w(0) AND nliiO0l1i; + wire_nliiOliOi_w_lg_w_lg_w_lg_dataout44320w45270w45271w(0) <= NOT wire_nliiOliOi_w_lg_w_lg_dataout44320w45270w(0); + wire_nliiOliOi_w_lg_dataout44320w(0) <= NOT wire_nliiOliOi_dataout; + wire_nliiOliOl_dataout <= niOO010O AND NOT(niOO001i); + wire_nliiOlli_dataout <= wire_nl1lO00iO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1iOl_dataout; + wire_nliiOlll_dataout <= wire_nl1lO00li_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1iOO_dataout; + wire_nliiOllO_dataout <= wire_nl1lO00ll_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1l1i_dataout; + wire_nliiOlOi_dataout <= wire_nl1lO00lO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1l1l_dataout; + wire_nliiOlOl_dataout <= wire_nl1lO00Oi_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1l1O_dataout; + wire_nliiOlOO_dataout <= wire_nl1lO00Ol_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1l0i_dataout; + wire_nliiOO0i_dataout <= wire_nl1lOOlil_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1lil_dataout; + wire_nliiOO0l_dataout <= wire_nl1lOOliO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1liO_dataout; + wire_nliiOO0O_dataout <= wire_nl1lO0i0l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1lli_dataout; + wire_nliiOO1i_dataout <= wire_nl1lO00OO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1l0l_dataout; + wire_nliiOO1l_dataout <= wire_nl1lOOl0O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1l0O_dataout; + wire_nliiOO1O_dataout <= wire_nl1lOOlii_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1lii_dataout; + wire_nliiOOii_dataout <= wire_nl1iliilO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1lll_dataout; + wire_nliiOOil_dataout <= wire_nl1iliiOi_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1llO_dataout; + wire_nliiOOiO_dataout <= wire_nl1iliiOl_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1lOi_dataout; + wire_nliiOOiOi_dataout <= wire_nliiOOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOiOl_dataout <= wire_nliiOOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOiOO_dataout <= wire_nliiOOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOl0i_dataout <= wire_nliiOOlli_dataout WHEN niOillO0O = '1' ELSE nliiOOill; + wire_nliiOOl0l_dataout <= wire_nliiOOOll_dataout WHEN niOillO0O = '1' ELSE nliiOOiii; + wire_nliiOOl0O_dataout <= wire_nlil1111i_dataout WHEN niOillO0O = '1' ELSE nliiOOiiO; + wire_nliiOOl1i_dataout <= wire_nliiOOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOl1l_dataout <= wire_nliiOOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOl1O_dataout <= wire_nliiOOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOli_dataout <= wire_nl1iliiOO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1lOl_dataout; + wire_nliiOOlii_dataout <= wire_nliiOOOOO_dataout WHEN niOillO0O = '1' ELSE nliiOOili; + wire_nliiOOlil_dataout <= (wire_niO1110l_w_lg_dataout44125w(0) AND nlil1lOiO) WHEN niOillO0O = '1' ELSE nliiOOiil; + wire_nliiOOliO_dataout <= wire_niO1110l_dataout WHEN niOillO0O = '1' ELSE nlil1lOiO; + wire_nliiOOll_dataout <= wire_nl1ilil1i_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1lOO_dataout; + wire_nliiOOlli_dataout <= wire_nliiOOlll_dataout AND (k_conf(131) AND nliiOOiil); + wire_nliiOOlll_dataout <= wire_nliiOOllO_dataout AND NOT((((nl0OiO1Oi OR nli1il11O) OR (niOillO0l AND niOillO0i)) OR (niOillO0i AND nli1i011i))); + wire_nliiOOllO_dataout <= wire_nlill0Oll_w_lg_nliiOOiii44117w(0) AND NOT((nliiOOili AND nliiOOiiO)); + wire_nliiOOlO_dataout <= wire_nl1ilil1l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1O1i_dataout; + wire_nliiOOlOl_dataout <= wire_w_lg_niOilOO1i43375w(0) WHEN nlil00iiO = '1' ELSE nlil1lO0i; + wire_nliiOOlOO_dataout <= wire_w_lg_niOilOO1i43375w(0) WHEN nlil00i1i = '1' ELSE wire_nliiOOlOl_dataout; + wire_nliiOOO0O_dataout <= wire_nliiOOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOO1O_dataout <= wire_w_lg_niOilOO1i43375w(0) WHEN nlil00i0O = '1' ELSE wire_nliiOOlOO_dataout; + wire_nliiOOOi_dataout <= wire_nl1ilil1O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1O1l_dataout; + wire_nliiOOOiO_dataout <= niOilOO1i WHEN nlil00iiO = '1' ELSE nlil1lO1O; + wire_nliiOOOl_dataout <= wire_nl1ilil0i_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1O1O_dataout; + wire_nliiOOOli_dataout <= wire_nliiOOOiO_dataout AND NOT(nlil00i1i); + wire_nliiOOOll_dataout <= wire_nliiOOOlO_dataout OR nli1il11O; + wire_nliiOOOlO_dataout <= nliiOOiii AND NOT(nliiOOiil); + wire_nliiOOOO_dataout <= wire_nl1ilil0l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1O0i_dataout; + wire_nliiOOOOi_dataout <= wire_nliiOOOli_dataout AND NOT(nlil00i0O); + wire_nliiOOOOl_dataout <= wire_nliiOOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliiOOOOO_dataout <= wire_nlil1111l_dataout WHEN nliiOOili = '1' ELSE wire_nlil1110O_dataout; + wire_nlil0000l_dataout <= wire_nlil0000O_dataout OR (nlil01i0i AND niOilO0il); + wire_nlil0000O_dataout <= nlil01i1O AND NOT(niOilO0li); + wire_nlil000i_dataout <= nll0O0l0O WHEN niOO1OOlO = '1' ELSE wire_nlili1il_dataout; + wire_nlil000l_dataout <= nll0O0lii WHEN niOO1OOlO = '1' ELSE wire_nlili1iO_dataout; + wire_nlil000ll_dataout <= wire_nlil000lO_dataout OR niOilO0li; + wire_nlil000lO_dataout <= nlil01i0i AND nli11ilOi; + wire_nlil000O_dataout <= nll0O0lil WHEN niOO1OOlO = '1' ELSE wire_nlili1li_dataout; + wire_nlil0010i_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO00i = '1' ELSE wire_nlil001Ol_dataout; + wire_nlil0010l_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO00i = '1' ELSE wire_nlil001OO_dataout; + wire_nlil0010O_dataout <= wire_nlil0001i_o(1) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010il; + wire_nlil0011i_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO00i = '1' ELSE wire_nlil001ll_dataout; + wire_nlil0011l_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO00i = '1' ELSE wire_nlil001lO_dataout; + wire_nlil0011O_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO00i = '1' ELSE wire_nlil001Oi_dataout; + wire_nlil001i_dataout <= nll0O0l1O WHEN niOO1OOlO = '1' ELSE wire_nlili10l_dataout; + wire_nlil001ii_dataout <= wire_nlil0001i_o(2) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010iO; + wire_nlil001il_dataout <= wire_nlil0001i_o(3) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010li; + wire_nlil001iO_dataout <= wire_nlil0001i_o(4) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010ll; + wire_nlil001l_dataout <= nll0O0l0i WHEN niOO1OOlO = '1' ELSE wire_nlili10O_dataout; + wire_nlil001li_dataout <= wire_nlil0001i_o(5) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010lO; + wire_nlil001ll_dataout <= wire_nlil0001i_o(6) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010Oi; + wire_nlil001lO_dataout <= wire_nlil0001i_o(7) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010Ol; + wire_nlil001O_dataout <= nll0O0l0l WHEN niOO1OOlO = '1' ELSE wire_nlili1ii_dataout; + wire_nlil001Oi_dataout <= wire_nlil0001i_o(8) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil010OO; + wire_nlil001Ol_dataout <= wire_nlil0001i_o(9) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil01i1i; + wire_nlil001OO_dataout <= wire_nlil0001i_o(10) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil01i1l; + wire_nlil00ii_dataout <= nll0O0liO WHEN niOO1OOlO = '1' ELSE wire_nlili1ll_dataout; + wire_nlil00il_dataout <= nll0O0lli WHEN niOO1OOlO = '1' ELSE wire_nlili1lO_dataout; + wire_nlil00iO_dataout <= nll0O0lll WHEN niOO1OOlO = '1' ELSE wire_nlili1Oi_dataout; + wire_nlil00iOi_dataout <= wire_nlil00O1i_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00iOl_dataout <= wire_nilO011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil00iOO_dataout <= wire_nlil00lOl_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00l0i_dataout <= wire_nlil00O0O_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00l0l_dataout <= wire_nlil00Oii_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00l0O_dataout <= wire_nlil00Oil_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00l1i_dataout <= wire_nlil00O1O_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00l1l_dataout <= wire_nlil00O0i_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00l1O_dataout <= wire_nlil00O0l_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00li_dataout <= nll0O0llO WHEN niOO1OOlO = '1' ELSE wire_nlili1Ol_dataout; + wire_nlil00lii_dataout <= wire_nlil00OiO_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00lil_dataout <= wire_nlil00Oli_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00liO_dataout <= wire_nlil00Oll_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00ll_dataout <= nll0O0lOi WHEN niOO1OOlO = '1' ELSE wire_nlili1OO_dataout; + wire_nlil00lli_dataout <= wire_nlil00OlO_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00lll_dataout <= wire_nlil00OOi_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00llO_dataout <= wire_nlil00OOl_o AND NOT(wire_niO01O0O_dataout); + wire_nlil00lO_dataout <= nll0O0lOl WHEN niOO1OOlO = '1' ELSE wire_nlili01i_dataout; + wire_nlil00lOi_dataout <= wire_nlil00OOO_o OR wire_niO01O0O_dataout; + wire_nlil00Oi_dataout <= nll0O0lOO WHEN niOO1OOlO = '1' ELSE wire_nlili01l_dataout; + wire_nlil00Ol_dataout <= nll0O0O1i WHEN niOO1OOlO = '1' ELSE wire_nlili01O_dataout; + wire_nlil00OO_dataout <= nll0O0O1l WHEN niOO1OOlO = '1' ELSE wire_nlili00i_dataout; + wire_nlil010i_dataout <= wire_nl1ill0ii_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0Oil_dataout; + wire_nlil010l_dataout <= wire_nl1ill0il_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0OiO_dataout; + wire_nlil010O_dataout <= wire_nl1ill0iO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0Oli_dataout; + wire_nlil0110i_dataout <= wire_nlil011il_dataout OR niOilO01l; + wire_nlil0110l_dataout <= wire_nlil011iO_dataout OR niOilO01l; + wire_nlil0110O_dataout <= wire_nlil011li_o(1) WHEN wire_w_lg_niOilOl1l43927w(0) = '1' ELSE nlil1lOli; + wire_nlil0111i_dataout <= wire_nlil0110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil0111l_dataout <= wire_nlil0110O_dataout OR niOilO01l; + wire_nlil0111O_dataout <= wire_nlil011ii_dataout OR niOilO01l; + wire_nlil011i_dataout <= wire_nl1ill00i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0O0l_dataout; + wire_nlil011ii_dataout <= wire_nlil011li_o(2) WHEN wire_w_lg_niOilOl1l43927w(0) = '1' ELSE nlil1OOiO; + wire_nlil011il_dataout <= wire_nlil011li_o(3) WHEN wire_w_lg_niOilOl1l43927w(0) = '1' ELSE nlil1OOli; + wire_nlil011iO_dataout <= wire_nlil011li_o(4) WHEN wire_w_lg_niOilOl1l43927w(0) = '1' ELSE nlil1OOll; + wire_nlil011l_dataout <= wire_nl1ill00l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0O0O_dataout; + wire_nlil011O_dataout <= wire_nl1ill00O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0Oii_dataout; + wire_nlil01i0O_dataout <= wire_nlil01lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01ii_dataout <= wire_nl1ill0li_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0Oll_dataout; + wire_nlil01iii_dataout <= wire_nlil01lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01iil_dataout <= wire_nlil01llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01iiO_dataout <= wire_nlil01lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01il_dataout <= wire_nl1ill0ll_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0OlO_dataout; + wire_nlil01ili_dataout <= wire_nlil01lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01ill_dataout <= wire_nlil01lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01ilO_dataout <= wire_nlil01O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01iO_dataout <= wire_nl1ill0lO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0OOi_dataout; + wire_nlil01iOi_dataout <= wire_nlil01Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01iOl_dataout <= wire_nlil01OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01iOO_dataout <= wire_nlil01OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01l0i_dataout <= wire_nlil0011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01l0l_dataout <= wire_nlil0011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01l0O_dataout <= wire_nlil0010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01l1i_dataout <= wire_nlil01OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01l1l_dataout <= wire_nlil01OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01l1O_dataout <= wire_nlil0011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01li_dataout <= wire_nl1ill0Oi_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0OOl_dataout; + wire_nlil01lii_dataout <= wire_nlil0010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01lil_dataout <= wire_nlil0000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01liO_dataout <= wire_nlil000ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil01ll_dataout <= wire_nl1ill0Ol_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0OOO_dataout; + wire_nlil01lli_dataout <= wire_nlil01O1l_dataout OR niOilO01O; + wire_nlil01lll_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO01O = '1' ELSE wire_nlil01O1O_dataout; + wire_nlil01llO_dataout <= niOO0Olii WHEN niOilO01O = '1' ELSE wire_nlil01O0i_dataout; + wire_nlil01lO_dataout <= wire_nl1ill0OO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlili11i_dataout; + wire_nlil01lOi_dataout <= wire_nlil01O0l_dataout AND NOT(niOilO01O); + wire_nlil01lOl_dataout <= wire_nlil01O0O_dataout AND NOT(niOilO01O); + wire_nlil01lOO_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO01O = '1' ELSE wire_nlil01Oii_dataout; + wire_nlil01O0i_dataout <= wire_nlil01OiO_o(3) WHEN niOilO00l = '1' ELSE nlil0101O; + wire_nlil01O0l_dataout <= wire_nlil01OiO_o(4) WHEN niOilO00l = '1' ELSE nlil0100i; + wire_nlil01O0O_dataout <= wire_nlil01OiO_o(5) WHEN niOilO00l = '1' ELSE nlil0100l; + wire_nlil01O1i_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO01O = '1' ELSE wire_nlil01Oil_dataout; + wire_nlil01O1l_dataout <= wire_nlil01OiO_o(1) WHEN niOilO00l = '1' ELSE nlil1OOlO; + wire_nlil01O1O_dataout <= wire_nlil01OiO_o(2) WHEN niOilO00l = '1' ELSE nlil0101l; + wire_nlil01Oi_dataout <= nll0O0iOO WHEN niOO1OOlO = '1' ELSE wire_nlili11l_dataout; + wire_nlil01Oii_dataout <= wire_nlil01OiO_o(6) WHEN niOilO00l = '1' ELSE nlil0100O; + wire_nlil01Oil_dataout <= wire_nlil01OiO_o(7) WHEN niOilO00l = '1' ELSE nlil010ii; + wire_nlil01Ol_dataout <= nll0O0l1i WHEN niOO1OOlO = '1' ELSE wire_nlili11O_dataout; + wire_nlil01Oll_dataout <= wire_nlil0010O_dataout OR niOilO00i; + wire_nlil01OlO_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO00i = '1' ELSE wire_nlil001ii_dataout; + wire_nlil01OO_dataout <= nll0O0l1l WHEN niOO1OOlO = '1' ELSE wire_nlili10i_dataout; + wire_nlil01OOi_dataout <= wire_niO01ill_w_lg_niOO0Olii20546w(0) WHEN niOilO00i = '1' ELSE wire_nlil001il_dataout; + wire_nlil01OOl_dataout <= wire_nlil001iO_dataout AND NOT(niOilO00i); + wire_nlil01OOO_dataout <= wire_nlil001li_dataout AND NOT(niOilO00i); + wire_nlil0i00i_dataout <= nlil00i1O AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i00l_dataout <= nlil00i0i OR wire_nilOO0ii_w_lg_dataout43403w(0); + wire_nlil0i00O_dataout <= nlil00i0l AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i01i_dataout <= nlil000OO AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i01l_dataout <= nlil00i1i AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i01O_dataout <= nlil00i1l AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0i_dataout <= nll0O0O0O WHEN niOO1OOlO = '1' ELSE wire_nlili0il_dataout; + wire_nlil0i0ii_dataout <= nlil00i0O AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0il_dataout <= nlil00iii AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0iO_dataout <= nlil00iil AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0l_dataout <= nll0O0Oii WHEN niOO1OOlO = '1' ELSE wire_nlili0iO_dataout; + wire_nlil0i0li_dataout <= nlil00iiO AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0ll_dataout <= nlil00ili AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0lO_dataout <= nlil00ill AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0O_dataout <= nll0O0Oil WHEN niOO1OOlO = '1' ELSE wire_nlili0li_dataout; + wire_nlil0i0Oi_dataout <= nlil00ilO AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil0i0Ol_dataout <= wire_nlil0iilO_dataout AND NOT(niOilOi1i); + wire_nlil0i0OO_dataout <= wire_nlil0iiOi_dataout AND NOT(niOilOi1i); + wire_nlil0i10i_dataout <= nlil00i1i AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i10l_dataout <= nlil00i1l AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i10O_dataout <= nlil00i1O AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i11l_dataout <= nlil000Ol AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i11O_dataout <= nlil000OO AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1i_dataout <= nll0O0O1O WHEN niOO1OOlO = '1' ELSE wire_nlili00l_dataout; + wire_nlil0i1ii_dataout <= nlil00i0i AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1il_dataout <= nlil00i0l AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1iO_dataout <= nlil00i0O AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1l_dataout <= nll0O0O0i WHEN niOO1OOlO = '1' ELSE wire_nlili00O_dataout; + wire_nlil0i1li_dataout <= nlil00iii AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1ll_dataout <= nlil00iil AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1lO_dataout <= nlil00iiO AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1O_dataout <= nll0O0O0l WHEN niOO1OOlO = '1' ELSE wire_nlili0ii_dataout; + wire_nlil0i1Oi_dataout <= nlil00ili AND NOT(wire_nilOO0ii_dataout); + wire_nlil0i1Ol_dataout <= nlil00ill OR wire_nilOO0ii_dataout; + wire_nlil0i1OO_dataout <= nlil00ilO AND NOT(wire_nilOO0ii_dataout); + wire_nlil0ii0i_dataout <= wire_nlil0il1l_dataout AND NOT(niOilOi1i); + wire_nlil0ii0l_dataout <= wire_nlil0il1O_dataout AND NOT(niOilOi1i); + wire_nlil0ii0O_dataout <= wire_nlil0il0i_dataout AND NOT(niOilOi1i); + wire_nlil0ii1i_dataout <= wire_nlil0iiOl_dataout AND NOT(niOilOi1i); + wire_nlil0ii1l_dataout <= wire_nlil0iiOO_dataout AND NOT(niOilOi1i); + wire_nlil0ii1O_dataout <= wire_nlil0il1i_dataout OR niOilOi1i; + wire_nlil0iii_dataout <= nll0O0OiO WHEN niOO1OOlO = '1' ELSE wire_nlili0ll_dataout; + wire_nlil0iiii_dataout <= wire_nlil0il0l_dataout AND NOT(niOilOi1i); + wire_nlil0iiil_dataout <= wire_nlil0il0O_dataout AND NOT(niOilOi1i); + wire_nlil0iiiO_dataout <= wire_nlil0ilii_dataout AND NOT(niOilOi1i); + wire_nlil0iil_dataout <= nll0O0Oli WHEN niOO1OOlO = '1' ELSE wire_nlili0lO_dataout; + wire_nlil0iili_dataout <= wire_nlil0ilil_dataout AND NOT(niOilOi1i); + wire_nlil0iill_dataout <= wire_nlil0iliO_dataout AND NOT(niOilOi1i); + wire_nlil0iilO_dataout <= wire_nlil0ilOi_dataout AND NOT(niOilO0Ol); + wire_nlil0iiO_dataout <= nll0O0Oll WHEN niOO1OOlO = '1' ELSE wire_nlili0Oi_dataout; + wire_nlil0iiOi_dataout <= wire_nlil0ilOl_dataout AND NOT(niOilO0Ol); + wire_nlil0iiOl_dataout <= wire_nlil0ilOO_dataout AND NOT(niOilO0Ol); + wire_nlil0iiOO_dataout <= wire_nlil0iO1i_dataout AND NOT(niOilO0Ol); + wire_nlil0il0i_dataout <= wire_nlil0iO0l_dataout AND NOT(niOilO0Ol); + wire_nlil0il0l_dataout <= wire_nlil0iO0O_dataout AND NOT(niOilO0Ol); + wire_nlil0il0O_dataout <= wire_nlil0iOii_dataout AND NOT(niOilO0Ol); + wire_nlil0il1i_dataout <= wire_nlil0iO1l_dataout OR niOilO0Ol; + wire_nlil0il1l_dataout <= wire_nlil0iO1O_dataout AND NOT(niOilO0Ol); + wire_nlil0il1O_dataout <= wire_nlil0iO0i_dataout AND NOT(niOilO0Ol); + wire_nlil0ili_dataout <= nll0O0OlO WHEN niOO1OOlO = '1' ELSE wire_nlili0Ol_dataout; + wire_nlil0ilii_dataout <= wire_nlil0iOil_dataout AND NOT(niOilO0Ol); + wire_nlil0ilil_dataout <= wire_nlil0iOiO_dataout AND NOT(niOilO0Ol); + wire_nlil0iliO_dataout <= wire_nlil0iOli_dataout AND NOT(niOilO0Ol); + wire_nlil0ill_dataout <= nll0O0OOi WHEN niOO1OOlO = '1' ELSE wire_nlili0OO_dataout; + wire_nlil0ilO_dataout <= nll0O0OOl WHEN niOO1OOlO = '1' ELSE wire_nlilii1i_dataout; + wire_nlil0ilOi_dataout <= wire_nlil0iOll_dataout AND NOT(nl0l010li); + wire_nlil0ilOl_dataout <= wire_nlil0iOlO_dataout AND NOT(nl0l010li); + wire_nlil0ilOO_dataout <= wire_nlil0iOOi_dataout AND NOT(nl0l010li); + wire_nlil0iO0i_dataout <= wire_nlil0l11l_dataout AND NOT(nl0l010li); + wire_nlil0iO0l_dataout <= wire_nlil0l11O_dataout AND NOT(nl0l010li); + wire_nlil0iO0O_dataout <= wire_nlil0l10i_dataout AND NOT(nl0l010li); + wire_nlil0iO1i_dataout <= wire_nlil0iOOl_dataout OR nl0l010li; + wire_nlil0iO1l_dataout <= wire_nlil0iOOO_dataout AND NOT(nl0l010li); + wire_nlil0iO1O_dataout <= wire_nlil0l11i_dataout AND NOT(nl0l010li); + wire_nlil0iOi_dataout <= nll0O0OOO WHEN niOO1OOlO = '1' ELSE wire_nlilii1l_dataout; + wire_nlil0iOii_dataout <= wire_nlil0l10l_dataout AND NOT(nl0l010li); + wire_nlil0iOil_dataout <= wire_nlil0l10O_dataout AND NOT(nl0l010li); + wire_nlil0iOiO_dataout <= wire_nlil0l1ii_dataout AND NOT(nl0l010li); + wire_nlil0iOl_dataout <= nll0Oi11i WHEN niOO1OOlO = '1' ELSE wire_nlilii1O_dataout; + wire_nlil0iOli_dataout <= wire_nlil0l1il_dataout AND NOT(nl0l010li); + wire_nlil0iOll_dataout <= wire_nlil0l1iO_dataout AND NOT(niOilOi0O); + wire_nlil0iOlO_dataout <= wire_nlil0l1li_dataout AND NOT(niOilOi0O); + wire_nlil0iOO_dataout <= nll0Oi11l WHEN niOO1OOlO = '1' ELSE wire_nlilii0i_dataout; + wire_nlil0iOOi_dataout <= wire_nlil0l1ll_dataout AND NOT(niOilOi0O); + wire_nlil0iOOl_dataout <= wire_nilOO0ii_dataout WHEN niOilOi0O = '1' ELSE wire_nlil0l1lO_dataout; + wire_nlil0iOOO_dataout <= wire_nilOO0ii_w_lg_dataout43403w(0) WHEN niOilOi0O = '1' ELSE wire_nlil0l1Oi_dataout; + wire_nlil0l00i_dataout <= nlil00ili AND NOT(niOilOi0i); + wire_nlil0l00l_dataout <= nlil00ill AND NOT(niOilOi0i); + wire_nlil0l00O_dataout <= nlil00ilO AND NOT(niOilOi0i); + wire_nlil0l01i_dataout <= nlil00iii AND NOT(niOilOi0i); + wire_nlil0l01l_dataout <= nlil00iil AND NOT(niOilOi0i); + wire_nlil0l01O_dataout <= nlil00iiO AND NOT(niOilOi0i); + wire_nlil0l0i_dataout <= nll0Oi10O WHEN niOO1OOlO = '1' ELSE wire_nliliiil_dataout; + wire_nlil0l0l_dataout <= nll0Oi1ii WHEN niOO1OOlO = '1' ELSE wire_nliliiiO_dataout; + wire_nlil0l0li_dataout <= wire_nlil0Oi0l_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O10l_dataout; + wire_nlil0l0ll_dataout <= wire_nlili1l1l_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O10O_dataout; + wire_nlil0l0lO_dataout <= wire_nlili1l1O_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1ii_dataout; + wire_nlil0l0O_dataout <= nll0Oi1il WHEN niOO1OOlO = '1' ELSE wire_nliliili_dataout; + wire_nlil0l0Oi_dataout <= wire_nlili1l0i_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1il_dataout; + wire_nlil0l0Ol_dataout <= wire_nlili1l0l_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1iO_dataout; + wire_nlil0l0OO_dataout <= wire_nlil0Oi0O_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1li_dataout; + wire_nlil0l10i_dataout <= wire_nlil0l01l_dataout AND NOT(niOilOi0O); + wire_nlil0l10l_dataout <= wire_nlil0l01O_dataout AND NOT(niOilOi0O); + wire_nlil0l10O_dataout <= wire_nlil0l00i_dataout AND NOT(niOilOi0O); + wire_nlil0l11i_dataout <= wire_nlil0l1Ol_dataout AND NOT(niOilOi0O); + wire_nlil0l11l_dataout <= wire_nlil0l1OO_dataout AND NOT(niOilOi0O); + wire_nlil0l11O_dataout <= wire_nlil0l01i_dataout AND NOT(niOilOi0O); + wire_nlil0l1i_dataout <= nll0Oi11O WHEN niOO1OOlO = '1' ELSE wire_nlilii0l_dataout; + wire_nlil0l1ii_dataout <= wire_nlil0l00l_dataout AND NOT(niOilOi0O); + wire_nlil0l1il_dataout <= wire_nlil0l00O_dataout AND NOT(niOilOi0O); + wire_nlil0l1iO_dataout <= nlil000OO AND NOT(niOilOi0i); + wire_nlil0l1l_dataout <= nll0Oi10i WHEN niOO1OOlO = '1' ELSE wire_nlilii0O_dataout; + wire_nlil0l1li_dataout <= nlil00i1i AND NOT(niOilOi0i); + wire_nlil0l1ll_dataout <= nlil00i1l AND NOT(niOilOi0i); + wire_nlil0l1lO_dataout <= wire_w_lg_niOilOi1l43406w(0) WHEN niOilOi0i = '1' ELSE nlil00i1O; + wire_nlil0l1O_dataout <= nll0Oi10l WHEN niOO1OOlO = '1' ELSE wire_nliliiii_dataout; + wire_nlil0l1Oi_dataout <= niOilOi1l WHEN niOilOi0i = '1' ELSE nlil00i0i; + wire_nlil0l1Ol_dataout <= nlil00i0l AND NOT(niOilOi0i); + wire_nlil0l1OO_dataout <= nlil00i0O AND NOT(niOilOi0i); + wire_nlil0li0i_dataout <= wire_nlili1lli_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1Ol_dataout; + wire_nlil0li0l_dataout <= wire_nlili1lll_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1OO_dataout; + wire_nlil0li0O_dataout <= wire_nlili1llO_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O01i_dataout; + wire_nlil0li1i_dataout <= wire_nlili1lii_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1ll_dataout; + wire_nlil0li1l_dataout <= wire_nlili1lil_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1lO_dataout; + wire_nlil0li1O_dataout <= wire_nlili1liO_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1Oi_dataout; + wire_nlil0lii_dataout <= nll0Oi1iO WHEN niOO1OOlO = '1' ELSE wire_nliliill_dataout; + wire_nlil0liii_dataout <= wire_nlili1lOi_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O01l_dataout; + wire_nlil0liil_dataout <= wire_nlil0ll0O_dataout AND NOT(niOilOiil); + wire_nlil0liiO_dataout <= wire_nlil0llii_dataout AND NOT(niOilOiil); + wire_nlil0lil_dataout <= nll0Oi1li WHEN niOO1OOlO = '1' ELSE wire_nliliilO_dataout; + wire_nlil0lili_dataout <= wire_nlil0llil_dataout AND NOT(niOilOiil); + wire_nlil0lill_dataout <= wire_nlil0lliO_dataout AND NOT(niOilOiil); + wire_nlil0lilO_dataout <= wire_nlil0llli_dataout OR niOilOiil; + wire_nlil0liO_dataout <= nll0Oi1ll WHEN niOO1OOlO = '1' ELSE wire_nliliiOi_dataout; + wire_nlil0liOi_dataout <= wire_nlil0llll_dataout AND NOT(niOilOiil); + wire_nlil0liOl_dataout <= wire_nlil0lllO_dataout AND NOT(niOilOiil); + wire_nlil0liOO_dataout <= wire_nlil0llOi_dataout AND NOT(niOilOiil); + wire_nlil0ll0i_dataout <= wire_nlil0lO1l_dataout AND NOT(niOilOiil); + wire_nlil0ll0l_dataout <= wire_nlil0lO1O_dataout AND NOT(niOilOiil); + wire_nlil0ll0O_dataout <= nlil000OO AND NOT(nlil1i01l); + wire_nlil0ll1i_dataout <= wire_nlil0llOl_dataout AND NOT(niOilOiil); + wire_nlil0ll1l_dataout <= wire_nlil0llOO_dataout AND NOT(niOilOiil); + wire_nlil0ll1O_dataout <= wire_nlil0lO1i_dataout AND NOT(niOilOiil); + wire_nlil0lli_dataout <= nll0Oi1lO WHEN niOO1OOlO = '1' ELSE wire_nliliiOl_dataout; + wire_nlil0llii_dataout <= nlil00i1i AND NOT(nlil1i01l); + wire_nlil0llil_dataout <= nlil00i1l AND NOT(nlil1i01l); + wire_nlil0lliO_dataout <= nlil00i1O AND NOT(nlil1i01l); + wire_nlil0lll_dataout <= nll0Oi1Oi WHEN niOO1OOlO = '1' ELSE wire_nliliiOO_dataout; + wire_nlil0llli_dataout <= nlil00i0i OR nlil1i01l; + wire_nlil0llll_dataout <= nlil00i0l AND NOT(nlil1i01l); + wire_nlil0lllO_dataout <= nlil00i0O AND NOT(nlil1i01l); + wire_nlil0llO_dataout <= nll0Oi1Ol WHEN niOO1OOlO = '1' ELSE wire_nlilil1i_dataout; + wire_nlil0llOi_dataout <= nlil00iii AND NOT(nlil1i01l); + wire_nlil0llOl_dataout <= nlil00iil AND NOT(nlil1i01l); + wire_nlil0llOO_dataout <= nlil00iiO AND NOT(nlil1i01l); + wire_nlil0lO0l_dataout <= wire_nlil0O00i_dataout WHEN niOilOO1i = '1' ELSE nlil01i0l; + wire_nlil0lO0O_dataout <= wire_nlil0O00l_dataout WHEN niOilOO1i = '1' ELSE nlil000Ol; + wire_nlil0lO1i_dataout <= nlil00ili AND NOT(nlil1i01l); + wire_nlil0lO1l_dataout <= nlil00ill AND NOT(nlil1i01l); + wire_nlil0lO1O_dataout <= nlil00ilO AND NOT(nlil1i01l); + wire_nlil0lOi_dataout <= nll0Oi1OO WHEN niOO1OOlO = '1' ELSE wire_nlilil1l_dataout; + wire_nlil0lOii_dataout <= wire_nlil0O00O_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O10l_dataout; + wire_nlil0lOil_dataout <= wire_nlil0O0ii_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O10O_dataout; + wire_nlil0lOiO_dataout <= wire_nlil0O0il_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1ii_dataout; + wire_nlil0lOl_dataout <= nll0Oi01i WHEN niOO1OOlO = '1' ELSE wire_nlilil1O_dataout; + wire_nlil0lOli_dataout <= wire_nlil0O0iO_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1il_dataout; + wire_nlil0lOll_dataout <= wire_nlil0O0li_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1iO_dataout; + wire_nlil0lOlO_dataout <= wire_nlil0O0ll_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1li_dataout; + wire_nlil0lOO_dataout <= nll0Oi01l WHEN niOO1OOlO = '1' ELSE wire_nlilil0i_dataout; + wire_nlil0lOOi_dataout <= wire_nlil0O0lO_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1ll_dataout; + wire_nlil0lOOl_dataout <= wire_nlil0O0Oi_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1lO_dataout; + wire_nlil0lOOO_dataout <= wire_nlil0O0Ol_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1Oi_dataout; + wire_nlil0O00i_dataout <= wire_nlil0Oi0i_dataout AND NOT(nl0l010li); + wire_nlil0O00l_dataout <= nlil000Ol OR nl0l010li; + wire_nlil0O00O_dataout <= wire_nlil0Oi0l_dataout AND NOT(nl0l010li); + wire_nlil0O01i_dataout <= nlil00ill AND NOT(niOilOiiO); + wire_nlil0O01l_dataout <= nlil00ilO AND NOT(niOilOiiO); + wire_nlil0O0i_dataout <= nll0Oi00O WHEN niOO1OOlO = '1' ELSE wire_nlililil_dataout; + wire_nlil0O0ii_dataout <= wire_nlili1l1l_dataout AND NOT(nl0l010li); + wire_nlil0O0il_dataout <= wire_nlili1l1O_dataout AND NOT(nl0l010li); + wire_nlil0O0iO_dataout <= wire_nlili1l0i_dataout AND NOT(nl0l010li); + wire_nlil0O0l_dataout <= nll0Oi0ii WHEN niOO1OOlO = '1' ELSE wire_nlililiO_dataout; + wire_nlil0O0li_dataout <= wire_nlili1l0l_dataout AND NOT(nl0l010li); + wire_nlil0O0ll_dataout <= wire_nlil0Oi0O_dataout AND NOT(nl0l010li); + wire_nlil0O0lO_dataout <= wire_nlili1lii_dataout AND NOT(nl0l010li); + wire_nlil0O0O_dataout <= nll0Oi0il WHEN niOO1OOlO = '1' ELSE wire_nlililli_dataout; + wire_nlil0O0Oi_dataout <= wire_nlili1lil_dataout AND NOT(nl0l010li); + wire_nlil0O0Ol_dataout <= wire_nlili1liO_dataout OR nl0l010li; + wire_nlil0O0OO_dataout <= wire_nlili1lli_dataout AND NOT(nl0l010li); + wire_nlil0O10i_dataout <= wire_nlil0Oi1O_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O01l_dataout; + wire_nlil0O10l_dataout <= nlil000OO AND NOT(niOilOiiO); + wire_nlil0O10O_dataout <= nlil00i1i AND NOT(niOilOiiO); + wire_nlil0O11i_dataout <= wire_nlil0O0OO_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1Ol_dataout; + wire_nlil0O11l_dataout <= wire_nlil0Oi1i_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O1OO_dataout; + wire_nlil0O11O_dataout <= wire_nlil0Oi1l_dataout WHEN niOilOO1i = '1' ELSE wire_nlil0O01i_dataout; + wire_nlil0O1i_dataout <= nll0Oi01O WHEN niOO1OOlO = '1' ELSE wire_nlilil0l_dataout; + wire_nlil0O1ii_dataout <= nlil00i1l AND NOT(niOilOiiO); + wire_nlil0O1il_dataout <= nlil00i1O AND NOT(niOilOiiO); + wire_nlil0O1iO_dataout <= nlil00i0i AND NOT(niOilOiiO); + wire_nlil0O1l_dataout <= nll0Oi00i WHEN niOO1OOlO = '1' ELSE wire_nlilil0O_dataout; + wire_nlil0O1li_dataout <= nlil00i0l OR niOilOiiO; + wire_nlil0O1ll_dataout <= nlil00i0O AND NOT(niOilOiiO); + wire_nlil0O1lO_dataout <= nlil00iii AND NOT(niOilOiiO); + wire_nlil0O1O_dataout <= nll0Oi00l WHEN niOO1OOlO = '1' ELSE wire_nlililii_dataout; + wire_nlil0O1Oi_dataout <= nlil00iil AND NOT(niOilOiiO); + wire_nlil0O1Ol_dataout <= nlil00iiO AND NOT(niOilOiiO); + wire_nlil0O1OO_dataout <= nlil00ili AND NOT(niOilOiiO); + wire_nlil0Oi0i_dataout <= nlil01i0l WHEN niOilOllO = '1' ELSE wire_nlili1iOO_dataout; + wire_nlil0Oi0l_dataout <= nlil000OO AND NOT(niOilOllO); + wire_nlil0Oi0O_dataout <= nlil00i0l OR niOilOllO; + wire_nlil0Oi1i_dataout <= wire_nlili1lll_dataout AND NOT(nl0l010li); + wire_nlil0Oi1l_dataout <= wire_nlili1llO_dataout AND NOT(nl0l010li); + wire_nlil0Oi1O_dataout <= wire_nlili1lOi_dataout AND NOT(nl0l010li); + wire_nlil0Oii_dataout <= nll0Oi0iO WHEN niOO1OOlO = '1' ELSE wire_nlililll_dataout; + wire_nlil0Oiii_dataout <= wire_nlil0Ol0l_dataout AND NOT(niOilOill); + wire_nlil0Oiil_dataout <= wire_nlil0Ol0O_dataout AND NOT(niOilOill); + wire_nlil0OiiO_dataout <= wire_nlil0Olii_dataout AND NOT(niOilOill); + wire_nlil0Oil_dataout <= nll0Oi0li WHEN niOO1OOlO = '1' ELSE wire_nlilillO_dataout; + wire_nlil0Oili_dataout <= wire_nlil0Olil_dataout AND NOT(niOilOill); + wire_nlil0Oill_dataout <= wire_nlil0OliO_dataout AND NOT(niOilOill); + wire_nlil0OilO_dataout <= wire_nlil0Olli_dataout AND NOT(niOilOill); + wire_nlil0OiO_dataout <= nll0Oi0ll WHEN niOO1OOlO = '1' ELSE wire_nlililOi_dataout; + wire_nlil0OiOi_dataout <= wire_nlil0Olll_dataout AND NOT(niOilOill); + wire_nlil0OiOl_dataout <= wire_nlil0OllO_dataout AND NOT(niOilOill); + wire_nlil0OiOO_dataout <= wire_nlil0OlOi_dataout AND NOT(niOilOill); + wire_nlil0Ol0i_dataout <= wire_nlil0OO1l_dataout AND NOT(niOilOill); + wire_nlil0Ol0l_dataout <= wire_nlil0OO1O_dataout AND NOT(niOilOili); + wire_nlil0Ol0O_dataout <= wire_nlil0OO0i_dataout AND NOT(niOilOili); + wire_nlil0Ol1i_dataout <= wire_nlil0OlOl_dataout OR niOilOill; + wire_nlil0Ol1l_dataout <= wire_nlil0OlOO_dataout AND NOT(niOilOill); + wire_nlil0Ol1O_dataout <= wire_nlil0OO1i_dataout AND NOT(niOilOill); + wire_nlil0Oli_dataout <= nll0Oi0lO WHEN niOO1OOlO = '1' ELSE wire_nlililOl_dataout; + wire_nlil0Olii_dataout <= wire_nlil0OO0l_dataout AND NOT(niOilOili); + wire_nlil0Olil_dataout <= wire_nlil0OO0O_dataout AND NOT(niOilOili); + wire_nlil0OliO_dataout <= wire_nlil0OOii_dataout AND NOT(niOilOili); + wire_nlil0Oll_dataout <= nll0Oi0Oi WHEN niOO1OOlO = '1' ELSE wire_nlililOO_dataout; + wire_nlil0Olli_dataout <= wire_nlil0OOil_dataout AND NOT(niOilOili); + wire_nlil0Olll_dataout <= wire_nlil0OOiO_dataout AND NOT(niOilOili); + wire_nlil0OllO_dataout <= wire_nlil0OOli_dataout AND NOT(niOilOili); + wire_nlil0OlO_dataout <= nll0Oi0Ol WHEN niOO1OOlO = '1' ELSE wire_nliliO1i_dataout; + wire_nlil0OlOi_dataout <= wire_nlil0OOll_dataout AND NOT(niOilOili); + wire_nlil0OlOl_dataout <= wire_nlil0OOlO_dataout OR niOilOili; + wire_nlil0OlOO_dataout <= wire_nlil0OOOi_dataout AND NOT(niOilOili); + wire_nlil0OO0i_dataout <= nlil00i1i AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OO0l_dataout <= nlil00i1l AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OO0O_dataout <= nlil00i1O AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OO1i_dataout <= wire_nlil0OOOl_dataout AND NOT(niOilOili); + wire_nlil0OO1l_dataout <= wire_nlil0OOOO_dataout AND NOT(niOilOili); + wire_nlil0OO1O_dataout <= nlil000OO AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOi_dataout <= nll0Oi0OO WHEN niOO1OOlO = '1' ELSE wire_nliliO1l_dataout; + wire_nlil0OOii_dataout <= nlil00i0i AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOil_dataout <= nlil00i0l AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOiO_dataout <= nlil00i0O AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOl_dataout <= nll0Oii1i WHEN niOO1OOlO = '1' ELSE wire_nliliO1O_dataout; + wire_nlil0OOli_dataout <= nlil00iii AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOll_dataout <= nlil00iil AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOlO_dataout <= nlil00iiO AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOO_dataout <= nll0Oii1l WHEN niOO1OOlO = '1' ELSE wire_nliliO0i_dataout; + wire_nlil0OOOi_dataout <= nlil00ili AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil0OOOl_dataout <= nlil00ill OR wire_nliliO10i_w_lg_nl111iOiO43397w(0); + wire_nlil0OOOO_dataout <= nlil00ilO AND NOT(wire_nliliO10i_w_lg_nl111iOiO43397w(0)); + wire_nlil1000i_dataout <= wire_nlil100iO_dataout WHEN niOillOll = '1' ELSE nlil11lOl; + wire_nlil1000l_dataout <= wire_nlil100li_dataout WHEN niOillOll = '1' ELSE nlil11lOO; + wire_nlil1000O_dataout <= wire_nlil100ll_o(0) WHEN wire_w_lg_niOillOil44080w(0) = '1' ELSE nlil11lll; + wire_nlil1001i_dataout <= wire_nlil1000O_dataout WHEN niOillOll = '1' ELSE nlil11lll; + wire_nlil1001l_dataout <= wire_nlil100ii_dataout WHEN niOillOll = '1' ELSE nlil11llO; + wire_nlil1001O_dataout <= wire_nlil100il_dataout WHEN niOillOll = '1' ELSE nlil11lOi; + wire_nlil100i_dataout <= wire_nl1iliOiO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil01il_dataout; + wire_nlil100ii_dataout <= wire_nlil100ll_o(1) WHEN wire_w_lg_niOillOil44080w(0) = '1' ELSE nlil11llO; + wire_nlil100il_dataout <= wire_nlil100ll_o(2) WHEN wire_w_lg_niOillOil44080w(0) = '1' ELSE nlil11lOi; + wire_nlil100iO_dataout <= wire_nlil100ll_o(3) WHEN wire_w_lg_niOillOil44080w(0) = '1' ELSE nlil11lOl; + wire_nlil100l_dataout <= wire_nl1iliOli_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil01iO_dataout; + wire_nlil100li_dataout <= wire_nlil100ll_o(4) WHEN wire_w_lg_niOillOil44080w(0) = '1' ELSE nlil11lOO; + wire_nlil100lO_dataout <= wire_nlil10i1O_dataout AND NOT(niOillOli); + wire_nlil100O_dataout <= wire_nl1iliOll_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil01li_dataout; + wire_nlil100Oi_dataout <= wire_nlil10i0i_dataout AND NOT(niOillOli); + wire_nlil100Ol_dataout <= wire_nlil10i0l_dataout AND NOT(niOillOli); + wire_nlil100OO_dataout <= wire_nlil10i0O_dataout AND NOT(niOillOli); + wire_nlil1010i_dataout <= wire_nlil100Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1010l_dataout <= wire_nlil100OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1010O_dataout <= wire_nlil10i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1011i_dataout <= wire_nlil10l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1011l_dataout <= wire_nlil100lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1011O_dataout <= wire_nlil100Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil101i_dataout <= wire_nl1iliO0O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil010l_dataout; + wire_nlil101ii_dataout <= wire_nlil10i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil101il_dataout <= wire_nlil10lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil101iO_dataout <= wire_nlil101OO_dataout AND NOT(niOillOlO); + wire_nlil101l_dataout <= wire_nl1iliOii_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil010O_dataout; + wire_nlil101li_dataout <= wire_nlil1001i_dataout AND NOT(niOillOlO); + wire_nlil101ll_dataout <= wire_nlil1001l_dataout AND NOT(niOillOlO); + wire_nlil101lO_dataout <= wire_nlil1001O_dataout AND NOT(niOillOlO); + wire_nlil101O_dataout <= wire_nl1iliOil_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil01ii_dataout; + wire_nlil101Oi_dataout <= wire_nlil1000i_dataout AND NOT(niOillOlO); + wire_nlil101Ol_dataout <= wire_nlil1000l_dataout AND NOT(niOillOlO); + wire_nlil101OO_dataout <= niOillOil WHEN niOillOll = '1' ELSE nlil11l0i; + wire_nlil10i0i_dataout <= wire_nlil10iiO_dataout WHEN niOillOOi = '1' ELSE nlil11O1O; + wire_nlil10i0l_dataout <= wire_nlil10ili_dataout WHEN niOillOOi = '1' ELSE nlil11O0i; + wire_nlil10i0O_dataout <= wire_nlil10ill_dataout WHEN niOillOOi = '1' ELSE nlil11O0l; + wire_nlil10i1i_dataout <= wire_nlil10iii_dataout AND NOT(niOillOli); + wire_nlil10i1l_dataout <= wire_nlil10iil_dataout AND NOT(niOillOli); + wire_nlil10i1O_dataout <= niOillOiO WHEN niOillOOi = '1' ELSE nlil11O1l; + wire_nlil10ii_dataout <= wire_nl1iliOlO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil01ll_dataout; + wire_nlil10iii_dataout <= wire_nlil10ilO_dataout WHEN niOillOOi = '1' ELSE nlil11O0O; + wire_nlil10iil_dataout <= wire_nlil10iOi_dataout WHEN niOillOOi = '1' ELSE nlil11Oii; + wire_nlil10iiO_dataout <= wire_nlil10iOl_o(0) WHEN wire_w_lg_niOillOiO44057w(0) = '1' ELSE nlil11O1O; + wire_nlil10il_dataout <= wire_nl1iliOOi_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil01lO_dataout; + wire_nlil10ili_dataout <= wire_nlil10iOl_o(1) WHEN wire_w_lg_niOillOiO44057w(0) = '1' ELSE nlil11O0i; + wire_nlil10ill_dataout <= wire_nlil10iOl_o(2) WHEN wire_w_lg_niOillOiO44057w(0) = '1' ELSE nlil11O0l; + wire_nlil10ilO_dataout <= wire_nlil10iOl_o(3) WHEN wire_w_lg_niOillOiO44057w(0) = '1' ELSE nlil11O0O; + wire_nlil10iO_dataout <= wire_nl1iliilO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil01Oi_dataout; + wire_nlil10iOi_dataout <= wire_nlil10iOl_o(4) WHEN wire_w_lg_niOillOiO44057w(0) = '1' ELSE nlil11Oii; + wire_nlil10l0i_dataout <= wire_nlil10l0l_dataout AND NOT(niOillOll); + wire_nlil10l0l_dataout <= wire_nlill0Oll_w_lg_nlil11O1i44035w(0) WHEN wire_nlOilOiiO_dataout = '1' ELSE nlil11O1i; + wire_nlil10l1O_dataout <= wire_nlil10l0i_dataout AND NOT(niOillOlO); + wire_nlil10li_dataout <= wire_nl1iliiOi_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil01Ol_dataout; + wire_nlil10lil_dataout <= wire_nlil10liO_dataout AND NOT(((wire_nilOOi0i_dataout OR wire_nlil1i10l_w_lg_dataout44029w(0)) OR nlil110ii)); + wire_nlil10liO_dataout <= wire_nlil10lli_dataout AND NOT(niOillOOi); + wire_nlil10ll_dataout <= wire_nl1iliiOl_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil01OO_dataout; + wire_nlil10lli_dataout <= wire_nlill0Oll_w_lg_nlil11Oil44028w(0) WHEN wire_nlOilOiiO_dataout = '1' ELSE nlil11Oil; + wire_nlil10lO_dataout <= wire_nl1iliiOO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil001i_dataout; + wire_nlil10Oi_dataout <= wire_nl1ilil1i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil001l_dataout; + wire_nlil10Ol_dataout <= wire_nl1ilil1l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil001O_dataout; + wire_nlil10OO_dataout <= wire_nl1ilil1O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil000i_dataout; + wire_nlil10OOO_dataout <= nli1il10O AND wire_w_lg_w_k_conf_range44000w44004w(0); + wire_nlil10OOO_w_lg_dataout44032w(0) <= NOT wire_nlil10OOO_dataout; + wire_nlil110i_dataout <= wire_nl1ililiO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1Oil_dataout; + wire_nlil110il_dataout <= wire_nlil110Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil110iO_dataout <= wire_nlil110Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil110l_dataout <= wire_nl1ililli_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1OiO_dataout; + wire_nlil110li_dataout <= wire_nlil110OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil110ll_dataout <= wire_nlil11i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil110lO_dataout <= wire_nlil11i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil110O_dataout <= wire_nl1ililll_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1Oli_dataout; + wire_nlil110Oi_dataout <= wire_nlil11iii_dataout AND NOT(nlil000Ol); + wire_nlil110Ol_dataout <= wire_nlil11i1O_dataout AND NOT(nlil000Ol); + wire_nlil110OO_dataout <= wire_nlil11i0i_dataout AND NOT(nlil000Ol); + wire_nlil1110i_dataout <= wire_nlil1110O_dataout AND NOT(nliiOOiil); + wire_nlil1110l_dataout <= nliiOOiiO AND NOT(nliiOOiil); + wire_nlil1110O_dataout <= nliiOOili OR nlil1i00l; + wire_nlil1111i_dataout <= wire_nlil1111O_dataout WHEN nliiOOili = '1' ELSE nliiOOiiO; + wire_nlil1111l_dataout <= wire_nlil1110O_dataout WHEN nl0l010ll = '1' ELSE wire_nlil1110i_dataout; + wire_nlil1111O_dataout <= wire_nlil1110l_dataout OR nl0l010ll; + wire_nlil111i_dataout <= wire_nl1ilil0O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1O0l_dataout; + wire_nlil111ii_dataout <= niOilOO1i WHEN nlil00iiO = '1' ELSE nlil1lO1l; + wire_nlil111iO_dataout <= niOilOO1i WHEN nlil00i1i = '1' ELSE wire_nlil111ii_dataout; + wire_nlil111l_dataout <= wire_nl1ililii_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1O0O_dataout; + wire_nlil111ll_dataout <= wire_nlil111iO_dataout AND NOT(nlil00i0O); + wire_nlil111lO_dataout <= wire_nlil111ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil111O_dataout <= wire_nl1ililil_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1Oii_dataout; + wire_nlil111Ol_dataout <= wire_nlil111OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil111OO_dataout <= (wire_nilOO0il_w_lg_dataout44112w(0) AND wire_nilOO0ii_dataout) AND NOT((wire_nilOO0il_dataout AND wire_nilOO0ii_dataout)); + wire_nlil11i0i_dataout <= nlil1100i WHEN niOillOii = '1' ELSE wire_nlil11iiO_dataout; + wire_nlil11i0l_dataout <= nlil1100l WHEN niOillOii = '1' ELSE wire_nlil11ili_dataout; + wire_nlil11i0O_dataout <= nlil1100O WHEN niOillOii = '1' ELSE wire_nlil11ill_dataout; + wire_nlil11i1i_dataout <= wire_nlil11i0l_dataout AND NOT(nlil000Ol); + wire_nlil11i1l_dataout <= wire_nlil11i0O_dataout AND NOT(nlil000Ol); + wire_nlil11i1O_dataout <= nlil1101O WHEN niOillOii = '1' ELSE wire_nlil11iil_dataout; + wire_nlil11ii_dataout <= wire_nl1ilillO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1Oll_dataout; + wire_nlil11iii_dataout <= nlil111Oi OR niOillOii; + wire_nlil11iil_dataout <= nlil1101O WHEN wire_nilOO0ii_w_lg_dataout43403w(0) = '1' ELSE wire_nlil11ilO_dataout; + wire_nlil11iiO_dataout <= nlil1100i WHEN wire_nilOO0ii_w_lg_dataout43403w(0) = '1' ELSE wire_nlil11iOi_dataout; + wire_nlil11il_dataout <= wire_nl1ililOi_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1OlO_dataout; + wire_nlil11ili_dataout <= nlil1100l WHEN wire_nilOO0ii_w_lg_dataout43403w(0) = '1' ELSE wire_nlil11iOl_dataout; + wire_nlil11ill_dataout <= nlil1100O WHEN wire_nilOO0ii_w_lg_dataout43403w(0) = '1' ELSE wire_nlil11iOO_dataout; + wire_nlil11ilO_dataout <= wire_nlil11l1i_o(0) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil1101O; + wire_nlil11iO_dataout <= wire_nl1ililOl_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1OOi_dataout; + wire_nlil11iOi_dataout <= wire_nlil11l1i_o(1) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil1100i; + wire_nlil11iOl_dataout <= wire_nlil11l1i_o(2) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil1100l; + wire_nlil11iOO_dataout <= wire_nlil11l1i_o(3) WHEN wire_nlOilOO1O_dataout = '1' ELSE nlil1100O; + wire_nlil11l0l_dataout <= wire_nlil11l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil11l0O_dataout <= wire_nlil11lii_dataout WHEN (niOilOO1O OR niOilO0OO) = '1' ELSE nlil110ii; + wire_nlil11li_dataout <= wire_nl1ililOO_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1OOl_dataout; + wire_nlil11lii_dataout <= wire_nlil11lil_dataout OR wire_nilO011i_dataout; + wire_nlil11lil_dataout <= nlil110ii AND NOT((wire_nilOO0il_dataout AND nlil110ii)); + wire_nlil11ll_dataout <= wire_nl1iliO1i_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil1OOO_dataout; + wire_nlil11lO_dataout <= wire_nl1iliO1l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil011i_dataout; + wire_nlil11Oi_dataout <= wire_nl1iliO1O_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil011l_dataout; + wire_nlil11Ol_dataout <= wire_nl1iliO0i_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil011O_dataout; + wire_nlil11Oli_dataout <= wire_nlil101iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil11Oll_dataout <= wire_nlil101li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil11OlO_dataout <= wire_nlil101ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil11OO_dataout <= wire_nl1iliO0l_dataout WHEN niOO1OOOl = '1' ELSE wire_nlil010i_dataout; + wire_nlil11OOi_dataout <= wire_nlil101lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil11OOl_dataout <= wire_nlil101Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil11OOO_dataout <= wire_nlil101Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1i00O_dataout <= wire_nlil1i0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1i0i_dataout <= wire_nl1ililii_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00il_dataout; + wire_nlil1i0ii_dataout <= wire_nlil1i0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1i0il_dataout <= wire_nlil1i0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1i0iO_dataout <= wire_nlil1i0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1i0l_dataout <= wire_nl1ililil_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00iO_dataout; + wire_nlil1i0li_dataout <= wire_nlil1ii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1i0ll_dataout <= wire_nlil1ii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1i0lO_dataout <= nlil11OiO WHEN niOilO1li = '1' ELSE wire_nlil1ii1O_dataout; + wire_nlil1i0O_dataout <= wire_nl1ililiO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00li_dataout; + wire_nlil1i0Oi_dataout <= nlil1i1OO WHEN niOilO1li = '1' ELSE wire_nlil1ii0i_dataout; + wire_nlil1i0Ol_dataout <= wire_nlil1ii0l_dataout AND NOT(niOilO1li); + wire_nlil1i0OO_dataout <= wire_nlil1ii0O_dataout AND NOT(niOilO1li); + wire_nlil1i10l_dataout <= nli1il10l AND wire_w_lg_w_k_conf_range43970w43999w(0); + wire_nlil1i10l_w_lg_dataout44029w(0) <= NOT wire_nlil1i10l_dataout; + wire_nlil1i1i_dataout <= wire_nl1ilil0i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil000l_dataout; + wire_nlil1i1l_dataout <= wire_nl1ilil0l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil000O_dataout; + wire_nlil1i1lO_dataout <= nlil1i01l AND wire_w_lg_niOO10O0O43993w(0); + wire_nlil1i1O_dataout <= wire_nl1ilil0O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00ii_dataout; + wire_nlil1i1Oi_dataout <= nlil1i01O AND wire_w_lg_niOO10O0O43993w(0); + wire_nlil1i1Ol_dataout <= nlil1i00i AND wire_w_lg_niOO10O0O43993w(0); + wire_nlil1ii0i_dataout <= wire_nlil1l00i_dataout WHEN nlil00i0O = '1' ELSE wire_nlil1iiiO_dataout; + wire_nlil1ii0l_dataout <= wire_nlil1liOi_dataout WHEN nlil00i0O = '1' ELSE wire_nlil1iill_dataout; + wire_nlil1ii0O_dataout <= wire_nlil1liOl_dataout WHEN nlil00i0O = '1' ELSE wire_nlil1iilO_dataout; + wire_nlil1ii1i_dataout <= wire_nlil1iiii_dataout AND NOT(niOilO1li); + wire_nlil1ii1l_dataout <= wire_nlil1iiil_dataout AND NOT(niOilO1li); + wire_nlil1ii1O_dataout <= nlil11OiO WHEN nlil00i0O = '1' ELSE wire_nlil1iili_dataout; + wire_nlil1iii_dataout <= wire_nl1ililli_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00ll_dataout; + wire_nlil1iiii_dataout <= wire_nlil1llii_dataout WHEN nlil00i0O = '1' ELSE wire_nlil1iiOi_dataout; + wire_nlil1iiil_dataout <= wire_nlil1llil_dataout WHEN nlil00i0O = '1' ELSE wire_nlil1iiOl_dataout; + wire_nlil1iiiO_dataout <= nlil1i1OO WHEN nlil00i1i = '1' ELSE wire_nlil1iiOO_dataout; + wire_nlil1iil_dataout <= wire_nl1ililll_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00lO_dataout; + wire_nlil1iili_dataout <= wire_nlil1lilO_dataout WHEN nlil00i1i = '1' ELSE nlil11OiO; + wire_nlil1iill_dataout <= wire_nlil1liOi_dataout WHEN nlil00i1i = '1' ELSE wire_nlil1il1i_dataout; + wire_nlil1iilO_dataout <= wire_nlil1liOl_dataout WHEN nlil00i1i = '1' ELSE wire_nlil1il1l_dataout; + wire_nlil1iiO_dataout <= wire_nl1ilillO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00Oi_dataout; + wire_nlil1iiOi_dataout <= wire_nlil1liOO_dataout WHEN nlil00i1i = '1' ELSE wire_nlil1il1O_dataout; + wire_nlil1iiOl_dataout <= wire_nlil1ll1i_dataout WHEN nlil00i1i = '1' ELSE wire_nlil1il0i_dataout; + wire_nlil1iiOO_dataout <= wire_nlil1l00i_dataout WHEN nlil00iiO = '1' ELSE nlil1i1OO; + wire_nlil1il0i_dataout <= wire_nlil1l0il_dataout WHEN nlil00iiO = '1' ELSE wire_nlil1ilil_dataout; + wire_nlil1il0l_dataout <= wire_nlil1iOOO_dataout WHEN nlil00i0l = '1' ELSE wire_nlil1iliO_dataout; + wire_nlil1il0O_dataout <= wire_nlil1l11i_dataout WHEN nlil00i0l = '1' ELSE wire_nlil1illi_dataout; + wire_nlil1il1i_dataout <= wire_nlil1l00l_dataout WHEN nlil00iiO = '1' ELSE wire_nlil1il0l_dataout; + wire_nlil1il1l_dataout <= wire_nlil1l00O_dataout WHEN nlil00iiO = '1' ELSE wire_nlil1il0O_dataout; + wire_nlil1il1O_dataout <= wire_nlil1l0ii_dataout WHEN nlil00iiO = '1' ELSE wire_nlil1ilii_dataout; + wire_nlil1ili_dataout <= wire_nl1ililOi_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00Ol_dataout; + wire_nlil1ilii_dataout <= wire_nlil1l11l_dataout WHEN nlil00i0l = '1' ELSE wire_nlil1illl_dataout; + wire_nlil1ilil_dataout <= wire_nlil1l11O_dataout WHEN nlil00i0l = '1' ELSE wire_nlil1illO_dataout; + wire_nlil1iliO_dataout <= wire_nlil1iOll_dataout WHEN nlil00i1O = '1' ELSE wire_nlil1ilOi_dataout; + wire_nlil1ill_dataout <= wire_nl1ililOl_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil00OO_dataout; + wire_nlil1illi_dataout <= wire_nlil1iOlO_dataout WHEN nlil00i1O = '1' ELSE wire_nlil1ilOl_dataout; + wire_nlil1illl_dataout <= wire_nlil1iOOi_dataout WHEN nlil00i1O = '1' ELSE wire_nlil1ilOO_dataout; + wire_nlil1illO_dataout <= wire_nlil1iOOl_dataout WHEN nlil00i1O = '1' ELSE wire_nlil1iO1i_dataout; + wire_nlil1ilO_dataout <= wire_nl1ililOO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0i1i_dataout; + wire_nlil1ilOi_dataout <= wire_nilOO0ii_w_lg_dataout43403w(0) WHEN nlil00i0i = '1' ELSE wire_nlil1iO1l_dataout; + wire_nlil1ilOl_dataout <= wire_nlil1iO1O_dataout AND NOT(nlil00i0i); + wire_nlil1ilOO_dataout <= wire_nlil1iO0i_dataout AND NOT(nlil00i0i); + wire_nlil1iO0i_dataout <= nlil1i01O AND NOT(nlil00ill); + wire_nlil1iO0l_dataout <= nlil1i00i AND NOT(nlil00ill); + wire_nlil1iO0O_dataout <= (nlil1llOO AND (niOilOO1i AND niOilO1iO)) OR (nlil1llOO AND (wire_w_lg_niOilOO1i43375w(0) AND niOilO1iO)); + wire_nlil1iO1i_dataout <= wire_nlil1iO0l_dataout AND NOT(nlil00i0i); + wire_nlil1iO1l_dataout <= nlil1i01i AND NOT(nlil00ill); + wire_nlil1iO1O_dataout <= wire_nlil1iO0O_dataout WHEN nlil00ill = '1' ELSE nlil1i01l; + wire_nlil1iOi_dataout <= wire_nl1iliO1i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0i1l_dataout; + wire_nlil1iOl_dataout <= wire_nl1iliO1l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0i1O_dataout; + wire_nlil1iOll_dataout <= nlil1i01i OR wire_nilOO0ii_w_lg_dataout43403w(0); + wire_nlil1iOlO_dataout <= nlil1i01l AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil1iOO_dataout <= wire_nl1iliO1O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0i0i_dataout; + wire_nlil1iOOi_dataout <= nlil1i01O AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil1iOOl_dataout <= nlil1i00i AND NOT(wire_nilOO0ii_w_lg_dataout43403w(0)); + wire_nlil1iOOO_dataout <= wire_nlil1l10i_dataout OR nl0l010li; + wire_nlil1l00i_dataout <= nlil1i1OO WHEN niOilO1il = '1' ELSE wire_nlil1l0Oi_dataout; + wire_nlil1l00l_dataout <= wire_nlil1l0iO_dataout AND NOT(niOilO1il); + wire_nlil1l00O_dataout <= wire_nlil1l0li_dataout AND NOT(niOilO1il); + wire_nlil1l0i_dataout <= wire_nl1iliOii_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0iil_dataout; + wire_nlil1l0ii_dataout <= wire_nlil1l0ll_dataout OR niOilO1il; + wire_nlil1l0il_dataout <= wire_nlil1l0lO_dataout AND NOT(niOilO1il); + wire_nlil1l0iO_dataout <= wire_nlil1l0Ol_dataout AND NOT(wire_w_lg_niOilOO1i43375w(0)); + wire_nlil1l0l_dataout <= wire_nl1iliOil_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0iiO_dataout; + wire_nlil1l0li_dataout <= wire_nlil1l0OO_dataout AND NOT(wire_w_lg_niOilOO1i43375w(0)); + wire_nlil1l0ll_dataout <= wire_nlil1li1i_dataout OR wire_w_lg_niOilOO1i43375w(0); + wire_nlil1l0lO_dataout <= wire_nlil1li1l_dataout AND NOT(wire_w_lg_niOilOO1i43375w(0)); + wire_nlil1l0O_dataout <= wire_nl1iliOiO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0ili_dataout; + wire_nlil1l0Oi_dataout <= wire_nilOO1li_w_lg_dataout43976w(0) WHEN wire_w_lg_niOilOO1i43375w(0) = '1' ELSE nlil1i1OO; + wire_nlil1l0Ol_dataout <= wire_nlil1li1O_dataout AND NOT(niOilO10O); + wire_nlil1l0OO_dataout <= wire_nlil1li0i_dataout OR niOilO10O; + wire_nlil1l10i_dataout <= wire_nlil1l1il_dataout OR niOilO10i; + wire_nlil1l10l_dataout <= wire_nlil1l1iO_dataout AND NOT(niOilO10i); + wire_nlil1l10O_dataout <= wire_nlil1l1li_dataout AND NOT(niOilO10i); + wire_nlil1l11i_dataout <= wire_nlil1l10l_dataout AND NOT(nl0l010li); + wire_nlil1l11l_dataout <= wire_nlil1l10O_dataout AND NOT(nl0l010li); + wire_nlil1l11O_dataout <= wire_nlil1l1ii_dataout AND NOT(nl0l010li); + wire_nlil1l1i_dataout <= wire_nl1iliO0i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0i0l_dataout; + wire_nlil1l1ii_dataout <= wire_nlil1l1ll_dataout AND NOT(niOilO10i); + wire_nlil1l1il_dataout <= nlil1i01i OR niOilO11l; + wire_nlil1l1iO_dataout <= nlil1i01l AND NOT(niOilO11l); + wire_nlil1l1l_dataout <= wire_nl1iliO0l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0i0O_dataout; + wire_nlil1l1li_dataout <= nlil1i01O AND NOT(niOilO11l); + wire_nlil1l1ll_dataout <= nlil1i00i AND NOT(niOilO11l); + wire_nlil1l1O_dataout <= wire_nl1iliO0O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0iii_dataout; + wire_nlil1li0i_dataout <= nlil1i01l AND NOT(niOilO10l); + wire_nlil1li0l_dataout <= nlil1i01O AND NOT(niOilO10l); + wire_nlil1li0O_dataout <= nlil1i00i AND NOT(niOilO10l); + wire_nlil1li1i_dataout <= wire_nlil1li0l_dataout AND NOT(niOilO10O); + wire_nlil1li1l_dataout <= wire_nlil1li0O_dataout AND NOT(niOilO10O); + wire_nlil1li1O_dataout <= nlil1i01i AND NOT(niOilO10l); + wire_nlil1lii_dataout <= wire_nl1iliOli_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0ill_dataout; + wire_nlil1lil_dataout <= wire_nl1iliOll_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0ilO_dataout; + wire_nlil1lilO_dataout <= nlil11OiO WHEN niOilO1il = '1' ELSE wire_nlil1ll0O_dataout; + wire_nlil1liO_dataout <= wire_nl1iliOlO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0iOi_dataout; + wire_nlil1liOi_dataout <= wire_nlil1ll1l_dataout AND NOT(niOilO1il); + wire_nlil1liOl_dataout <= wire_nlil1ll1O_dataout AND NOT(niOilO1il); + wire_nlil1liOO_dataout <= wire_nlil1ll0i_dataout AND NOT(niOilO1il); + wire_nlil1ll0i_dataout <= nlil1i01O AND NOT(wire_w_lg_niOilOO1i43375w(0)); + wire_nlil1ll0l_dataout <= nlil1i00i OR wire_w_lg_niOilOO1i43375w(0); + wire_nlil1ll0O_dataout <= wire_nilOO1ll_w_lg_dataout43968w(0) WHEN wire_w_lg_niOilOO1i43375w(0) = '1' ELSE nlil11OiO; + wire_nlil1ll1i_dataout <= wire_nlil1ll0l_dataout OR niOilO1il; + wire_nlil1ll1l_dataout <= nlil1i01i AND NOT(wire_w_lg_niOilOO1i43375w(0)); + wire_nlil1ll1O_dataout <= nlil1i01l AND NOT(wire_w_lg_niOilOO1i43375w(0)); + wire_nlil1lli_dataout <= wire_nl1iliOOi_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0iOl_dataout; + wire_nlil1llii_dataout <= wire_nlil1lliO_dataout OR niOilO1il; + wire_nlil1llil_dataout <= wire_nlil1llli_dataout AND NOT(niOilO1il); + wire_nlil1lliO_dataout <= nlil1i01O OR wire_w_lg_niOilOO1i43375w(0); + wire_nlil1lll_dataout <= wire_nl1iliOOl_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0iOO_dataout; + wire_nlil1llli_dataout <= nlil1i00i AND NOT(wire_w_lg_niOilOO1i43375w(0)); + wire_nlil1llO_dataout <= wire_nl1iliOOO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0l1i_dataout; + wire_nlil1lOi_dataout <= wire_nl1ill11i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0l1l_dataout; + wire_nlil1lOl_dataout <= wire_nl1ill11l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0l1O_dataout; + wire_nlil1lOll_dataout <= wire_nlil1Oiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1lOlO_dataout <= wire_nlil1Oi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1lOO_dataout <= wire_nl1ill11O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0l0i_dataout; + wire_nlil1lOOi_dataout <= wire_nlil1Oi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1lOOl_dataout <= wire_nlil1O10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1lOOO_dataout <= wire_nlil1O01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1O00i_dataout <= wire_nlil1O0ll_dataout WHEN nlil00i0O = '1' ELSE wire_nlil1O00l_dataout; + wire_nlil1O00l_dataout <= wire_nlil1O00O_dataout OR nlil00i1i; + wire_nlil1O00O_dataout <= wire_nlil1O0iO_dataout WHEN nlil00iiO = '1' ELSE wire_nlil1O0ii_dataout; + wire_nlil1O01l_dataout <= wire_nlil1O01O_dataout AND NOT(nlil00ill); + wire_nlil1O01O_dataout <= nlil1lO1i OR niOilO1li; + wire_nlil1O0i_dataout <= wire_nl1ill1ii_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0lil_dataout; + wire_nlil1O0ii_dataout <= wire_nlil1O0il_dataout AND NOT(nlil00iil); + wire_nlil1O0il_dataout <= nlil1lO0l AND NOT(wire_nilOO0lO_dataout); + wire_nlil1O0iO_dataout <= wire_nlil1O0li_dataout OR NOT(niOilOO1O); + wire_nlil1O0l_dataout <= wire_nl1ill1il_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0liO_dataout; + wire_nlil1O0li_dataout <= nlil1lO0l OR wire_nilO011l_dataout; + wire_nlil1O0ll_dataout <= wire_nlil1O0lO_dataout OR NOT(niOilOO1O); + wire_nlil1O0lO_dataout <= nlil1lO0l OR wire_nilO011l_dataout; + wire_nlil1O0O_dataout <= wire_nl1ill1iO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0lli_dataout; + wire_nlil1O0Oi_dataout <= wire_nlil1O0Ol_dataout AND NOT(nlil000OO); + wire_nlil1O0Ol_dataout <= wire_nlil1O0OO_dataout OR niOilOl1O; + wire_nlil1O0OO_dataout <= nlil1lO0O OR niOilOl0i; + wire_nlil1O10i_dataout <= wire_nlil1OiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1O10l_dataout <= niOilO1iO WHEN nlil00ill = '1' ELSE wire_nlil1O10O_dataout; + wire_nlil1O10O_dataout <= wire_nlil1O1ii_dataout AND NOT(niOilO1li); + wire_nlil1O11i_dataout <= wire_nlil1O00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1O11l_dataout <= wire_nlil1O0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1O11O_dataout <= wire_nlil1Oiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1O1i_dataout <= wire_nl1ill10i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0l0l_dataout; + wire_nlil1O1ii_dataout <= wire_nlil1O1il_dataout AND NOT((wire_w_lg_niOilOO1i43375w(0) AND (niOilOlll AND nlil00iiO))); + wire_nlil1O1il_dataout <= nlil1llOO OR ((wire_nlill0Oll_w_lg_nlil00i0l43959w(0) OR (niOilOO1i AND nlil00iiO)) OR wire_w_lg_w_lg_niOilOO1i43375w43962w(0)); + wire_nlil1O1l_dataout <= wire_nl1ill10l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0l0O_dataout; + wire_nlil1O1O_dataout <= wire_nl1ill10O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0lii_dataout; + wire_nlil1Oi0i_dataout <= nlil1llOi AND NOT(nlil000OO); + wire_nlil1Oi0l_dataout <= wire_nlil1Oi0O_dataout OR niOilO1ll; + wire_nlil1Oi0O_dataout <= nlil1llOl AND NOT(nlil000OO); + wire_nlil1Oi1O_dataout <= wire_nlil1Oi0i_dataout OR niOilO1OO; + wire_nlil1Oii_dataout <= wire_nl1ill1li_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0lll_dataout; + wire_nlil1Oiii_dataout <= wire_nlil1Oili_dataout AND NOT(niOilO01i); + wire_nlil1Oiil_dataout <= wire_nlil1Oill_dataout AND NOT(niOilO01i); + wire_nlil1OiiO_dataout <= wire_nlil1OilO_dataout AND NOT(niOilO01i); + wire_nlil1Oil_dataout <= wire_nl1ill1ll_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0llO_dataout; + wire_nlil1Oili_dataout <= wire_nlil1OiOi_dataout AND NOT(niOilO1OO); + wire_nlil1Oill_dataout <= wire_nlil1OiOl_dataout AND NOT(niOilO1OO); + wire_nlil1OilO_dataout <= wire_nlil1OiOO_dataout OR niOilO1OO; + wire_nlil1OiO_dataout <= wire_nl1ill1lO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0lOi_dataout; + wire_nlil1OiOi_dataout <= wire_nlil1Ol1i_dataout AND NOT(niOilO1Ol); + wire_nlil1OiOl_dataout <= wire_nlil1Ol1l_dataout OR niOilO1Ol; + wire_nlil1OiOO_dataout <= wire_nlil1Ol1O_dataout OR niOilO1Ol; + wire_nlil1Ol0i_dataout <= nlil1lOii AND NOT(niOilO1ll); + wire_nlil1Ol0l_dataout <= nlil1lOil OR niOilO1ll; + wire_nlil1Ol1i_dataout <= niOilO1ll AND NOT(niOilO1lO); + wire_nlil1Ol1l_dataout <= wire_w_lg_niOilOlli43955w(0) WHEN niOilO1lO = '1' ELSE wire_nlil1Ol0i_dataout; + wire_nlil1Ol1O_dataout <= wire_w_lg_niOilOlli43955w(0) WHEN niOilO1lO = '1' ELSE wire_nlil1Ol0l_dataout; + wire_nlil1Oli_dataout <= wire_nl1ill1Oi_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0lOl_dataout; + wire_nlil1Oll_dataout <= wire_nl1ill1Ol_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0lOO_dataout; + wire_nlil1OlO_dataout <= wire_nl1ill1OO_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0O1i_dataout; + wire_nlil1OOi_dataout <= wire_nl1ill01i_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0O1l_dataout; + wire_nlil1OOl_dataout <= wire_nl1ill01l_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0O1O_dataout; + wire_nlil1OOO_dataout <= wire_nl1ill01O_dataout WHEN niOO1OOOi = '1' ELSE wire_nlil0O0i_dataout; + wire_nlil1OOOi_dataout <= wire_nlil0111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1OOOl_dataout <= wire_nlil0111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlil1OOOO_dataout <= wire_nlil0110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlili000i_dataout <= nlil00iiO AND NOT(niOilOiOi); + wire_nlili000l_dataout <= nlil00ili AND NOT(niOilOiOi); + wire_nlili000O_dataout <= nlil00ill AND NOT(niOilOiOi); + wire_nlili001i_dataout <= nlil00i0O AND NOT(niOilOiOi); + wire_nlili001l_dataout <= nlil00iii AND NOT(niOilOiOi); + wire_nlili001O_dataout <= nlil00iil AND NOT(niOilOiOi); + wire_nlili00i_dataout <= nliOiOli WHEN niOO1OOll = '1' ELSE wire_nlill1il_dataout; + wire_nlili00ii_dataout <= nlil00ilO AND NOT(niOilOiOi); + wire_nlili00l_dataout <= nliOiOll WHEN niOO1OOll = '1' ELSE wire_nlill1iO_dataout; + wire_nlili00lO_dataout <= wire_nlili0ill_dataout OR niOilOliO; + wire_nlili00O_dataout <= nliOiOlO WHEN niOO1OOll = '1' ELSE wire_nlill1li_dataout; + wire_nlili00Oi_dataout <= wire_nlili0ilO_dataout AND NOT(niOilOliO); + wire_nlili00Ol_dataout <= wire_nlili0iOi_dataout AND NOT(niOilOliO); + wire_nlili00OO_dataout <= wire_nlili0iOl_dataout AND NOT(niOilOliO); + wire_nlili010i_dataout <= wire_nlili001l_dataout AND NOT(niOilOiOl); + wire_nlili010l_dataout <= wire_nlili001O_dataout AND NOT(niOilOiOl); + wire_nlili010O_dataout <= wire_nlili000i_dataout AND NOT(niOilOiOl); + wire_nlili011i_dataout <= wire_nlili01Ol_dataout AND NOT(niOilOiOl); + wire_nlili011l_dataout <= wire_nlili01OO_dataout AND NOT(niOilOiOl); + wire_nlili011O_dataout <= wire_nlili001i_dataout AND NOT(niOilOiOl); + wire_nlili01i_dataout <= nliOiOii WHEN niOO1OOll = '1' ELSE wire_nlill10l_dataout; + wire_nlili01ii_dataout <= wire_nlili000l_dataout AND NOT(niOilOiOl); + wire_nlili01il_dataout <= wire_nlili000O_dataout AND NOT(niOilOiOl); + wire_nlili01iO_dataout <= wire_nlili00ii_dataout AND NOT(niOilOiOl); + wire_nlili01l_dataout <= nliOiOil WHEN niOO1OOll = '1' ELSE wire_nlill10O_dataout; + wire_nlili01li_dataout <= nlil000OO AND NOT(niOilOiOi); + wire_nlili01ll_dataout <= nlil00i1i OR niOilOiOi; + wire_nlili01lO_dataout <= nlil00i1l AND NOT(niOilOiOi); + wire_nlili01O_dataout <= nliOiOiO WHEN niOO1OOll = '1' ELSE wire_nlill1ii_dataout; + wire_nlili01Oi_dataout <= nlil00i1O AND NOT(niOilOiOi); + wire_nlili01Ol_dataout <= nlil00i0i AND NOT(niOilOiOi); + wire_nlili01OO_dataout <= nlil00i0l AND NOT(niOilOiOi); + wire_nlili0i0i_dataout <= wire_nlili0l1O_dataout AND NOT(niOilOliO); + wire_nlili0i0l_dataout <= wire_nlili0l0i_dataout OR niOilOliO; + wire_nlili0i0O_dataout <= wire_nlili0l0l_dataout AND NOT(niOilOliO); + wire_nlili0i1i_dataout <= wire_nlili0iOO_dataout AND NOT(niOilOliO); + wire_nlili0i1l_dataout <= wire_nlili0l1i_dataout AND NOT(niOilOliO); + wire_nlili0i1O_dataout <= wire_nlili0l1l_dataout AND NOT(niOilOliO); + wire_nlili0ii_dataout <= nliOiOOi WHEN niOO1OOll = '1' ELSE wire_nlill1ll_dataout; + wire_nlili0iii_dataout <= wire_nlili0l0O_dataout AND NOT(niOilOliO); + wire_nlili0iil_dataout <= wire_nlili0lii_dataout AND NOT(niOilOliO); + wire_nlili0iiO_dataout <= wire_nlili0lil_dataout AND NOT(niOilOliO); + wire_nlili0il_dataout <= nliOiOOl WHEN niOO1OOll = '1' ELSE wire_nlill1lO_dataout; + wire_nlili0ili_dataout <= wire_nlili0liO_dataout AND NOT(niOilOliO); + wire_nlili0ill_dataout <= nlil01i0l WHEN niOilOlil = '1' ELSE wire_nlili0lli_dataout; + wire_nlili0ilO_dataout <= wire_nlili0lll_dataout AND NOT(niOilOlil); + wire_nlili0iO_dataout <= nliOiOOO WHEN niOO1OOll = '1' ELSE wire_nlill1Oi_dataout; + wire_nlili0iOi_dataout <= wire_nlili0llO_dataout AND NOT(niOilOlil); + wire_nlili0iOl_dataout <= wire_nlili0lOi_dataout AND NOT(niOilOlil); + wire_nlili0iOO_dataout <= wire_nlili0lOl_dataout AND NOT(niOilOlil); + wire_nlili0l0i_dataout <= wire_nlili0O1O_dataout OR niOilOlil; + wire_nlili0l0l_dataout <= wire_nlili0O0i_dataout AND NOT(niOilOlil); + wire_nlili0l0O_dataout <= wire_nlili0O0l_dataout AND NOT(niOilOlil); + wire_nlili0l1i_dataout <= wire_nlili0lOO_dataout AND NOT(niOilOlil); + wire_nlili0l1l_dataout <= wire_nlili0O1i_dataout AND NOT(niOilOlil); + wire_nlili0l1O_dataout <= wire_nlili0O1l_dataout AND NOT(niOilOlil); + wire_nlili0li_dataout <= nliOl11i WHEN niOO1OOll = '1' ELSE wire_nlill1Ol_dataout; + wire_nlili0lii_dataout <= wire_nlili0O0O_dataout AND NOT(niOilOlil); + wire_nlili0lil_dataout <= wire_nlili0Oii_dataout AND NOT(niOilOlil); + wire_nlili0liO_dataout <= wire_nlili0Oil_dataout AND NOT(niOilOlil); + wire_nlili0ll_dataout <= nliOl11l WHEN niOO1OOll = '1' ELSE wire_nlill1OO_dataout; + wire_nlili0lli_dataout <= wire_nlili0OiO_dataout OR niOilOl1O; + wire_nlili0lll_dataout <= wire_nlili0Oli_dataout AND NOT(niOilOl1O); + wire_nlili0llO_dataout <= wire_nlili0Oll_dataout AND NOT(niOilOl1O); + wire_nlili0lO_dataout <= nliOl11O WHEN niOO1OOll = '1' ELSE wire_nlill01i_dataout; + wire_nlili0lOi_dataout <= wire_nlili0OlO_dataout OR niOilOl1O; + wire_nlili0lOl_dataout <= wire_nlili0OOi_dataout AND NOT(niOilOl1O); + wire_nlili0lOO_dataout <= wire_nlili0OOl_dataout AND NOT(niOilOl1O); + wire_nlili0O0i_dataout <= wire_nlilii11O_dataout AND NOT(niOilOl1O); + wire_nlili0O0l_dataout <= wire_nlilii10i_dataout AND NOT(niOilOl1O); + wire_nlili0O0O_dataout <= wire_nlilii10l_dataout AND NOT(niOilOl1O); + wire_nlili0O1i_dataout <= wire_nlili0OOO_dataout AND NOT(niOilOl1O); + wire_nlili0O1l_dataout <= wire_nlilii11i_dataout AND NOT(niOilOl1O); + wire_nlili0O1O_dataout <= wire_nlilii11l_dataout AND NOT(niOilOl1O); + wire_nlili0Oi_dataout <= nliOl10i WHEN niOO1OOll = '1' ELSE wire_nlill01l_dataout; + wire_nlili0Oii_dataout <= wire_nlilii10O_dataout AND NOT(niOilOl1O); + wire_nlili0Oil_dataout <= wire_nlilii1ii_dataout AND NOT(niOilOl1O); + wire_nlili0OiO_dataout <= nlil01i0l WHEN niOilOl0i = '1' ELSE wire_nlilii1il_dataout; + wire_nlili0Ol_dataout <= nliOl10l WHEN niOO1OOll = '1' ELSE wire_nlill01O_dataout; + wire_nlili0Oli_dataout <= wire_nlilii1iO_dataout AND NOT(niOilOl0i); + wire_nlili0Oll_dataout <= wire_nlilii1li_dataout AND NOT(niOilOl0i); + wire_nlili0OlO_dataout <= wire_nlilii1ll_dataout OR niOilOl0i; + wire_nlili0OO_dataout <= nliOl10O WHEN niOO1OOll = '1' ELSE wire_nlill00i_dataout; + wire_nlili0OOi_dataout <= wire_nlilii1lO_dataout AND NOT(niOilOl0i); + wire_nlili0OOl_dataout <= wire_nlilii1Oi_dataout AND NOT(niOilOl0i); + wire_nlili0OOO_dataout <= wire_nlilii1Ol_dataout AND NOT(niOilOl0i); + wire_nlili100i_dataout <= wire_nlili1l1l_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1i1l_dataout; + wire_nlili100l_dataout <= wire_nlili1l1O_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1i1O_dataout; + wire_nlili100O_dataout <= wire_nlili1l0i_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1i0i_dataout; + wire_nlili101i_dataout <= nlil00ilO AND NOT(niOilOl1l); + wire_nlili101l_dataout <= wire_nlili1iOO_dataout WHEN niOilOO1i = '1' ELSE nlil01i0l; + wire_nlili101O_dataout <= wire_nlili1l1i_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1i1i_dataout; + wire_nlili10i_dataout <= nliOilli WHEN niOO1OOll = '1' ELSE wire_nliliOil_dataout; + wire_nlili10ii_dataout <= wire_nlili1l0l_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1i0l_dataout; + wire_nlili10il_dataout <= wire_nlili1l0O_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1i0O_dataout; + wire_nlili10iO_dataout <= wire_nlili1lii_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1iii_dataout; + wire_nlili10l_dataout <= nliOilll WHEN niOO1OOll = '1' ELSE wire_nliliOiO_dataout; + wire_nlili10li_dataout <= wire_nlili1lil_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1iil_dataout; + wire_nlili10ll_dataout <= wire_nlili1liO_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1iiO_dataout; + wire_nlili10lO_dataout <= wire_nlili1lli_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1ili_dataout; + wire_nlili10O_dataout <= nliOillO WHEN niOO1OOll = '1' ELSE wire_nliliOli_dataout; + wire_nlili10Oi_dataout <= wire_nlili1lll_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1ill_dataout; + wire_nlili10Ol_dataout <= wire_nlili1llO_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1ilO_dataout; + wire_nlili10OO_dataout <= wire_nlili1lOi_dataout WHEN niOilOO1i = '1' ELSE wire_nlili1iOi_dataout; + wire_nlili110i_dataout <= nlil000OO AND NOT(niOilOl1l); + wire_nlili110l_dataout <= nlil00i1i AND NOT(niOilOl1l); + wire_nlili110O_dataout <= nlil00i1l AND NOT(niOilOl1l); + wire_nlili11i_dataout <= nll0Oii1O WHEN niOO1OOlO = '1' ELSE wire_nliliO0l_dataout; + wire_nlili11ii_dataout <= nlil00i1O AND NOT(niOilOl1l); + wire_nlili11il_dataout <= nlil00i0i AND NOT(niOilOl1l); + wire_nlili11iO_dataout <= nlil00i0l AND NOT(niOilOl1l); + wire_nlili11l_dataout <= nliOilil WHEN niOO1OOll = '1' ELSE wire_nliliO0O_dataout; + wire_nlili11li_dataout <= nlil00i0O OR niOilOl1l; + wire_nlili11ll_dataout <= nlil00iii AND NOT(niOilOl1l); + wire_nlili11lO_dataout <= nlil00iil AND NOT(niOilOl1l); + wire_nlili11O_dataout <= nliOiliO WHEN niOO1OOll = '1' ELSE wire_nliliOii_dataout; + wire_nlili11Oi_dataout <= nlil00iiO AND NOT(niOilOl1l); + wire_nlili11Ol_dataout <= nlil00ili AND NOT(niOilOl1l); + wire_nlili11OO_dataout <= nlil00ill AND NOT(niOilOl1l); + wire_nlili1i0i_dataout <= nlil00i1O AND NOT(niOilOilO); + wire_nlili1i0l_dataout <= nlil00i0i AND NOT(niOilOilO); + wire_nlili1i0O_dataout <= nlil00i0l AND NOT(niOilOilO); + wire_nlili1i1i_dataout <= nlil000OO OR niOilOilO; + wire_nlili1i1l_dataout <= nlil00i1i AND NOT(niOilOilO); + wire_nlili1i1O_dataout <= nlil00i1l AND NOT(niOilOilO); + wire_nlili1ii_dataout <= nliOilOi WHEN niOO1OOll = '1' ELSE wire_nliliOll_dataout; + wire_nlili1iii_dataout <= nlil00i0O AND NOT(niOilOilO); + wire_nlili1iil_dataout <= nlil00iii AND NOT(niOilOilO); + wire_nlili1iiO_dataout <= nlil00iil AND NOT(niOilOilO); + wire_nlili1il_dataout <= nliOilOl WHEN niOO1OOll = '1' ELSE wire_nliliOlO_dataout; + wire_nlili1ili_dataout <= nlil00iiO AND NOT(niOilOilO); + wire_nlili1ill_dataout <= nlil00ili AND NOT(niOilOilO); + wire_nlili1ilO_dataout <= nlil00ill AND NOT(niOilOilO); + wire_nlili1iO_dataout <= nliOilOO WHEN niOO1OOll = '1' ELSE wire_nliliOOi_dataout; + wire_nlili1iOi_dataout <= nlil00ilO AND NOT(niOilOilO); + wire_nlili1iOO_dataout <= nlil01i0l AND wire_nilOO0il_dataout; + wire_nlili1l0i_dataout <= nlil00i1O AND NOT(niOilOllO); + wire_nlili1l0l_dataout <= nlil00i0i AND NOT(niOilOllO); + wire_nlili1l0O_dataout <= nlil00i0l AND NOT(niOilOllO); + wire_nlili1l1i_dataout <= nlil000OO OR niOilOllO; + wire_nlili1l1l_dataout <= nlil00i1i AND NOT(niOilOllO); + wire_nlili1l1O_dataout <= nlil00i1l AND NOT(niOilOllO); + wire_nlili1li_dataout <= nliOiO1i WHEN niOO1OOll = '1' ELSE wire_nliliOOl_dataout; + wire_nlili1lii_dataout <= nlil00i0O AND NOT(niOilOllO); + wire_nlili1lil_dataout <= nlil00iii AND NOT(niOilOllO); + wire_nlili1liO_dataout <= nlil00iil AND NOT(niOilOllO); + wire_nlili1ll_dataout <= nliOiO1l WHEN niOO1OOll = '1' ELSE wire_nliliOOO_dataout; + wire_nlili1lli_dataout <= nlil00iiO AND NOT(niOilOllO); + wire_nlili1lll_dataout <= nlil00ili AND NOT(niOilOllO); + wire_nlili1llO_dataout <= nlil00ill AND NOT(niOilOllO); + wire_nlili1lO_dataout <= nliOiO1O WHEN niOO1OOll = '1' ELSE wire_nlill11i_dataout; + wire_nlili1lOi_dataout <= nlil00ilO AND NOT(niOilOllO); + wire_nlili1lOl_dataout <= wire_nlili1OlO_dataout AND NOT(niOilOl1i); + wire_nlili1lOO_dataout <= wire_nlili1OOi_dataout OR niOilOl1i; + wire_nlili1O0i_dataout <= wire_nlili011l_dataout AND NOT(niOilOl1i); + wire_nlili1O0l_dataout <= wire_nlili011O_dataout AND NOT(niOilOl1i); + wire_nlili1O0O_dataout <= wire_nlili010i_dataout AND NOT(niOilOl1i); + wire_nlili1O1i_dataout <= wire_nlili1OOl_dataout AND NOT(niOilOl1i); + wire_nlili1O1l_dataout <= wire_nlili1OOO_dataout AND NOT(niOilOl1i); + wire_nlili1O1O_dataout <= wire_nlili011i_dataout AND NOT(niOilOl1i); + wire_nlili1Oi_dataout <= nliOiO0i WHEN niOO1OOll = '1' ELSE wire_nlill11l_dataout; + wire_nlili1Oii_dataout <= wire_nlili010l_dataout AND NOT(niOilOl1i); + wire_nlili1Oil_dataout <= wire_nlili010O_dataout AND NOT(niOilOl1i); + wire_nlili1OiO_dataout <= wire_nlili01ii_dataout AND NOT(niOilOl1i); + wire_nlili1Ol_dataout <= nliOiO0l WHEN niOO1OOll = '1' ELSE wire_nlill11O_dataout; + wire_nlili1Oli_dataout <= wire_nlili01il_dataout AND NOT(niOilOl1i); + wire_nlili1Oll_dataout <= wire_nlili01iO_dataout AND NOT(niOilOl1i); + wire_nlili1OlO_dataout <= wire_nlili01li_dataout AND NOT(niOilOiOl); + wire_nlili1OO_dataout <= nliOiO0O WHEN niOO1OOll = '1' ELSE wire_nlill10i_dataout; + wire_nlili1OOi_dataout <= wire_nlili01ll_dataout OR niOilOiOl; + wire_nlili1OOl_dataout <= wire_nlili01lO_dataout AND NOT(niOilOiOl); + wire_nlili1OOO_dataout <= wire_nlili01Oi_dataout AND NOT(niOilOiOl); + wire_nlilii00i_dataout <= wire_nliliii1l_dataout OR niOilOl0O; + wire_nlilii00l_dataout <= wire_nliliii1O_dataout AND NOT(niOilOl0O); + wire_nlilii00O_dataout <= wire_nliliii0i_dataout AND NOT(niOilOl0O); + wire_nlilii01i_dataout <= wire_nlilii0Ol_dataout AND NOT(niOilOl0O); + wire_nlilii01l_dataout <= wire_nlilii0OO_dataout AND NOT(niOilOl0O); + wire_nlilii01O_dataout <= wire_nliliii1i_dataout AND NOT(niOilOl0O); + wire_nlilii0i_dataout <= nliOl1li WHEN niOO1OOll = '1' ELSE wire_nlill0il_dataout; + wire_nlilii0ii_dataout <= nlil000OO AND NOT(niOilOl0l); + wire_nlilii0il_dataout <= nlil00i1i AND NOT(niOilOl0l); + wire_nlilii0iO_dataout <= nlil00i1l AND NOT(niOilOl0l); + wire_nlilii0l_dataout <= nliOl1ll WHEN niOO1OOll = '1' ELSE wire_nlill0iO_dataout; + wire_nlilii0li_dataout <= nlil00i1O AND NOT(niOilOl0l); + wire_nlilii0ll_dataout <= nlil00i0i AND NOT(niOilOl0l); + wire_nlilii0lO_dataout <= nlil00i0l AND NOT(niOilOl0l); + wire_nlilii0O_dataout <= nliOl1lO WHEN niOO1OOll = '1' ELSE wire_nlill0li_dataout; + wire_nlilii0Oi_dataout <= nlil00i0O AND NOT(niOilOl0l); + wire_nlilii0Ol_dataout <= nlil00iii AND NOT(niOilOl0l); + wire_nlilii0OO_dataout <= nlil00iil AND NOT(niOilOl0l); + wire_nlilii10i_dataout <= wire_nlilii01O_dataout AND NOT(niOilOl0i); + wire_nlilii10l_dataout <= wire_nlilii00i_dataout AND NOT(niOilOl0i); + wire_nlilii10O_dataout <= wire_nlilii00l_dataout AND NOT(niOilOl0i); + wire_nlilii11i_dataout <= wire_nlilii1OO_dataout AND NOT(niOilOl0i); + wire_nlilii11l_dataout <= wire_nlilii01i_dataout AND NOT(niOilOl0i); + wire_nlilii11O_dataout <= wire_nlilii01l_dataout AND NOT(niOilOl0i); + wire_nlilii1i_dataout <= nliOl1ii WHEN niOO1OOll = '1' ELSE wire_nlill00l_dataout; + wire_nlilii1ii_dataout <= wire_nlilii00O_dataout AND NOT(niOilOl0i); + wire_nlilii1il_dataout <= nlil01i0l OR niOilOl0O; + wire_nlilii1iO_dataout <= wire_nlilii0ii_dataout AND NOT(niOilOl0O); + wire_nlilii1l_dataout <= nliOl1il WHEN niOO1OOll = '1' ELSE wire_nlill00O_dataout; + wire_nlilii1li_dataout <= wire_nlilii0il_dataout AND NOT(niOilOl0O); + wire_nlilii1ll_dataout <= wire_nlilii0iO_dataout AND NOT(niOilOl0O); + wire_nlilii1lO_dataout <= wire_nlilii0li_dataout AND NOT(niOilOl0O); + wire_nlilii1O_dataout <= nliOl1iO WHEN niOO1OOll = '1' ELSE wire_nlill0ii_dataout; + wire_nlilii1Oi_dataout <= wire_nlilii0ll_dataout AND NOT(niOilOl0O); + wire_nlilii1Ol_dataout <= wire_nlilii0lO_dataout AND NOT(niOilOl0O); + wire_nlilii1OO_dataout <= wire_nlilii0Oi_dataout AND NOT(niOilOl0O); + wire_nliliii0i_dataout <= nlil00ilO AND NOT(niOilOl0l); + wire_nliliii1i_dataout <= nlil00iiO AND NOT(niOilOl0l); + wire_nliliii1l_dataout <= nlil00ili OR niOilOl0l; + wire_nliliii1O_dataout <= nlil00ill AND NOT(niOilOl0l); + wire_nliliiii_dataout <= nliOl1Oi WHEN niOO1OOll = '1' ELSE wire_nlill0ll_dataout; + wire_nliliiil_dataout <= nliOl1Ol WHEN niOO1OOll = '1' ELSE wire_nlill0lO_dataout; + wire_nliliiiO_dataout <= nliOl1OO WHEN niOO1OOll = '1' ELSE wire_nlill0Oi_dataout; + wire_nliliili_dataout <= nliOl01i WHEN niOO1OOll = '1' ELSE wire_nlill0Ol_dataout; + wire_nliliill_dataout <= nliOl01l WHEN niOO1OOll = '1' ELSE wire_nlill0OO_dataout; + wire_nliliilll_dataout <= nlil1lO1i AND niOilOO0l; + wire_nliliilO_dataout <= nliOl01O WHEN niOO1OOll = '1' ELSE wire_nlilli1i_dataout; + wire_nliliilOi_dataout <= wire_nliliiO1l_dataout AND NOT(nlil00ilO); + wire_nliliilOi_w_lg_dataout43982w(0) <= NOT wire_nliliilOi_dataout; + wire_nliliilOl_dataout <= wire_nliliiO1O_dataout AND NOT(nlil00ilO); + wire_nliliilOl_w_lg_dataout43980w(0) <= NOT wire_nliliilOl_dataout; + wire_nliliilOO_dataout <= wire_nliliiO0i_dataout AND NOT(nlil00ilO); + wire_nliliilOO_w_lg_dataout48202w(0) <= NOT wire_nliliilOO_dataout; + wire_nliliiO0i_dataout <= wire_nliliiOil_dataout AND NOT(nlil00ill); + wire_nliliiO0l_dataout <= wire_nliliiOiO_dataout AND NOT(nlil00ill); + wire_nliliiO0O_dataout <= wire_nliliiOli_dataout AND NOT(nlil00iii); + wire_nliliiO1i_dataout <= wire_nliliiO0l_dataout AND NOT(nlil00ilO); + wire_nliliiO1i_w48213w(0) <= wire_nliliiO1i_w_lg_w_lg_w_lg_dataout48201w48203w48212w(0) AND wire_nliliilOi_dataout; + wire_nliliiO1i_w_lg_w_lg_w_lg_dataout48201w48203w48212w(0) <= wire_nliliiO1i_w_lg_w_lg_dataout48201w48203w(0) AND wire_nliliilOl_w_lg_dataout43980w(0); + wire_nliliiO1i_w_lg_w_lg_w_lg_dataout48201w48203w48204w(0) <= wire_nliliiO1i_w_lg_w_lg_dataout48201w48203w(0) AND wire_nliliilOl_dataout; + wire_nliliiO1i_w_lg_w_lg_dataout48201w48203w(0) <= wire_nliliiO1i_w_lg_dataout48201w(0) AND wire_nliliilOO_w_lg_dataout48202w(0); + wire_nliliiO1i_w_lg_dataout48219w(0) <= wire_nliliiO1i_dataout AND wire_nliliilOO_w_lg_dataout48202w(0); + wire_nliliiO1i_w_lg_dataout48201w(0) <= NOT wire_nliliiO1i_dataout; + wire_nliliiO1l_dataout <= wire_nliliiO0O_dataout OR nlil00ill; + wire_nliliiO1O_dataout <= wire_nliliiOii_dataout AND NOT(nlil00ill); + wire_nliliiOi_dataout <= nliOl00i WHEN niOO1OOll = '1' ELSE wire_nlilli1l_dataout; + wire_nliliiOii_dataout <= wire_nliliiOll_dataout OR nlil00iii; + wire_nliliiOil_dataout <= wire_nliliiOlO_dataout AND NOT(nlil00iii); + wire_nliliiOiO_dataout <= wire_nliliiOOi_dataout AND NOT(nlil00iii); + wire_nliliiOl_dataout <= nliOl00l WHEN niOO1OOll = '1' ELSE wire_nlilli1O_dataout; + wire_nliliiOli_dataout <= wire_nliliiOOl_dataout OR nlil00i0O; + wire_nliliiOll_dataout <= wire_nliliiOOO_dataout OR nlil00i0O; + wire_nliliiOlO_dataout <= wire_nlilil11i_dataout AND NOT(nlil00i0O); + wire_nliliiOO_dataout <= nliOl00O WHEN niOO1OOll = '1' ELSE wire_nlilli0i_dataout; + wire_nliliiOOi_dataout <= wire_nlilil11l_dataout AND NOT(nlil00i0O); + wire_nliliiOOl_dataout <= wire_nlilil11O_dataout AND NOT(nlil00i0i); + wire_nliliiOOO_dataout <= wire_nlilil10i_dataout AND NOT(nlil00i0i); + wire_nlilil00i_dataout <= wire_nlilil0ii_dataout AND NOT(nlil00ili); + wire_nlilil00l_dataout <= wire_nlilil0il_dataout AND NOT(nlil00iiO); + wire_nlilil00O_dataout <= wire_nlilil0il_dataout OR nlil00iiO; + wire_nlilil01i_dataout <= wire_nlilil00i_dataout AND NOT(nlil000OO); + wire_nlilil01l_dataout <= wire_nlilil00l_dataout OR nlil00ili; + wire_nlilil01O_dataout <= wire_nlilil00O_dataout AND NOT(nlil00ili); + wire_nlilil0i_dataout <= nliOl0li WHEN niOO1OOll = '1' ELSE wire_nlilliil_dataout; + wire_nlilil0ii_dataout <= wire_nlill0Oll_w_lg_nlil00iil43346w(0) AND NOT(nlil00iiO); + wire_nlilil0il_dataout <= wire_nlill0Oll_w_lg_nlil00i0l43345w(0) OR nlil00iil; + wire_nlilil0l_dataout <= nliOl0ll WHEN niOO1OOll = '1' ELSE wire_nlilliiO_dataout; + wire_nlilil0O_dataout <= nliOl0lO WHEN niOO1OOll = '1' ELSE wire_nlillili_dataout; + wire_nlilil10i_dataout <= wire_nlilil1il_dataout AND NOT(nlil00i1O); + wire_nlilil10l_dataout <= wire_nlilil1iO_dataout OR nlil00i1O; + wire_nlilil10O_dataout <= wire_nlilil1li_dataout AND NOT(nlil00i1O); + wire_nlilil11i_dataout <= wire_nlilil10l_dataout OR nlil00i0i; + wire_nlilil11l_dataout <= wire_nlilil10O_dataout AND NOT(nlil00i0i); + wire_nlilil11O_dataout <= wire_nlilil1ii_dataout OR nlil00i1O; + wire_nlilil1i_dataout <= nliOl0ii WHEN niOO1OOll = '1' ELSE wire_nlilli0l_dataout; + wire_nlilil1ii_dataout <= wire_nlilil1ll_dataout AND NOT(nlil00i1l); + wire_nlilil1il_dataout <= wire_nlilil1lO_dataout OR nlil00i1l; + wire_nlilil1iO_dataout <= wire_nlilil1Oi_dataout OR nlil00i1l; + wire_nlilil1l_dataout <= nliOl0il WHEN niOO1OOll = '1' ELSE wire_nlilli0O_dataout; + wire_nlilil1li_dataout <= wire_nlill0Oll_w_lg_nlil00i1i43347w(0) AND NOT(nlil00i1l); + wire_nlilil1ll_dataout <= wire_nlilil1Ol_dataout OR nlil00i1i; + wire_nlilil1lO_dataout <= wire_nlilil1OO_dataout OR nlil00i1i; + wire_nlilil1O_dataout <= nliOl0iO WHEN niOO1OOll = '1' ELSE wire_nlilliii_dataout; + wire_nlilil1Oi_dataout <= wire_nlilil01i_dataout OR nlil00i1i; + wire_nlilil1Ol_dataout <= wire_nlilil01l_dataout AND NOT(nlil000OO); + wire_nlilil1OO_dataout <= wire_nlilil01O_dataout AND NOT(nlil000OO); + wire_nlililii_dataout <= nliOl0Oi WHEN niOO1OOll = '1' ELSE wire_nlillill_dataout; + wire_nlililil_dataout <= nliOl0Ol WHEN niOO1OOll = '1' ELSE wire_nlillilO_dataout; + wire_nlililiO_dataout <= nliOl0OO WHEN niOO1OOll = '1' ELSE wire_nlilliOi_dataout; + wire_nlilill0i_dataout <= nlilill1O AND niOilOO0O; + wire_nlilill0l_dataout <= nlililliO AND niOilOO0O; + wire_nlilill0O_dataout <= nl0OiO1Oi AND niOilOO0O; + wire_nlililli_dataout <= nliOli1i WHEN niOO1OOll = '1' ELSE wire_nlilliOl_dataout; + wire_nlilillii_dataout <= nli1il11O AND niOilOO0O; + wire_nlililll_dataout <= nliOli1l WHEN niOO1OOll = '1' ELSE wire_nlilliOO_dataout; + wire_nlilillli_dataout <= wire_nlilillOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilillll_dataout <= niOO0O0OO AND NOT(wire_niO01O0O_dataout); + wire_nlililllO_dataout <= wire_nlilillOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilillO_dataout <= nliOli1O WHEN niOO1OOll = '1' ELSE wire_nlilll1i_dataout; + wire_nlilillOi_dataout <= wire_nlilillOl_dataout AND wire_nilOO0ii_dataout; + wire_nlilillOl_dataout <= nlilill1O OR nli1il11l; + wire_nlilillOO_dataout <= wire_nlililO1i_dataout AND wire_nilOO0ii_dataout; + wire_nlililO1i_dataout <= nlililliO OR (wire_nlill0Oll_w_lg_w_lg_nl10iO1li43256w43257w(0) OR wire_niO01ill_w_lg_niOO0O0OO43259w(0)); + wire_nlililOi_dataout <= nliOli0i WHEN niOO1OOll = '1' ELSE wire_nlilll1l_dataout; + wire_nlililOl_dataout <= nliOli0l WHEN niOO1OOll = '1' ELSE wire_nlilll1O_dataout; + wire_nlililOll_dataout <= nli1illiO AND NOT(wire_niO01O0O_dataout); + wire_nlililOlO_dataout <= nli1il1ii AND NOT(wire_niO01O0O_dataout); + wire_nlililOO_dataout <= nliOli0O WHEN niOO1OOll = '1' ELSE wire_nlilll0i_dataout; + wire_nlililOOi_dataout <= nli1illli AND NOT(wire_niO01O0O_dataout); + wire_nlililOOl_dataout <= nl0illlll AND (nliliO11O AND ((wire_nlill0Oll_w_lg_nliliO11l42939w(0) AND wire_nlill0Oll_w_lg_nliliO11i42940w(0)) AND wire_nlill0Oll_w_lg_nlililOli42942w(0))); + wire_nlililOOl_w_lg_dataout43903w(0) <= wire_nlililOOl_dataout OR wire_nliliO10i_w_lg_w_lg_nl10liOii43901w43902w(0); + wire_nliliO00i_dataout <= wire_nliliO00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO00l_dataout <= wire_nliliO0ii_dataout OR wire_niO01O0O_dataout; + wire_nliliO00O_dataout <= wire_nliliOiiO_dataout WHEN nliliO10l = '1' ELSE wire_nliliOi1l_dataout; + wire_nliliO01i_dataout <= wire_nliliO0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO01l_dataout <= wire_nliliO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO01O_dataout <= wire_nliliO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO0i_dataout <= nliOlili WHEN niOO1OOll = '1' ELSE wire_nlilllil_dataout; + wire_nliliO0ii_dataout <= wire_nliliOili_dataout WHEN nliliO10l = '1' ELSE wire_nliliOi1O_dataout; + wire_nliliO0il_dataout <= wire_nliliOill_dataout WHEN nliliO10l = '1' ELSE nlililOli; + wire_nliliO0iO_dataout <= wire_nliliOilO_dataout WHEN nliliO10l = '1' ELSE nliliO11i; + wire_nliliO0l_dataout <= nliOlill WHEN niOO1OOll = '1' ELSE wire_nlillliO_dataout; + wire_nliliO0li_dataout <= wire_nliliOiOi_dataout WHEN nliliO10l = '1' ELSE nliliO11l; + wire_nliliO0ll_dataout <= wire_nliliOiOl_dataout WHEN nliliO10l = '1' ELSE wire_nliliOi0i_dataout; + wire_nliliO0lO_dataout <= wire_nliliOiOO_dataout WHEN nliliO10l = '1' ELSE wire_nliliOi0l_dataout; + wire_nliliO0O_dataout <= nll0O0iOO WHEN niOO1OOli = '1' ELSE wire_nl1iliilO_dataout; + wire_nliliO0Oi_dataout <= wire_nliliOl1i_dataout WHEN nliliO10l = '1' ELSE wire_nliliOi0O_dataout; + wire_nliliO0Ol_dataout <= nliliO1iO WHEN nliliO10l = '1' ELSE wire_nliliOiii_dataout; + wire_nliliO0OO_dataout <= wire_nliliOl1l_dataout WHEN nliliO10l = '1' ELSE wire_nliliOi1i_dataout; + wire_nliliO1i_dataout <= nliOliii WHEN niOO1OOll = '1' ELSE wire_nlilll0l_dataout; + wire_nliliO1l_dataout <= nliOliil WHEN niOO1OOll = '1' ELSE wire_nlilll0O_dataout; + wire_nliliO1ll_dataout <= wire_nliliO0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO1lO_dataout <= wire_nliliO0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO1O_dataout <= nliOliiO WHEN niOO1OOll = '1' ELSE wire_nlilllii_dataout; + wire_nliliO1Oi_dataout <= wire_nliliO0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO1Ol_dataout <= wire_nliliO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliO1OO_dataout <= wire_nliliO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliliOi0i_dataout <= wire_nlill1iOi_o(0) WHEN wire_nliliOiil_o = '1' ELSE nliliO10O; + wire_nliliOi0l_dataout <= wire_nlill1iOi_o(1) WHEN wire_nliliOiil_o = '1' ELSE nliliO1ii; + wire_nliliOi0O_dataout <= wire_nlill1iOi_o(2) WHEN wire_nliliOiil_o = '1' ELSE nliliO1il; + wire_nliliOi1i_dataout <= nliliO1li AND NOT(wire_nliliOiil_o); + wire_nliliOi1l_dataout <= nliliO11O AND NOT(wire_nliliOiil_o); + wire_nliliOi1O_dataout <= nliliO10l OR wire_nliliOiil_o; + wire_nliliOii_dataout <= nll0O0l1i WHEN niOO1OOli = '1' ELSE wire_nl1iliiOi_dataout; + wire_nliliOiii_dataout <= wire_nlill1iOi_o(3) WHEN wire_nliliOiil_o = '1' ELSE nliliO1iO; + wire_nliliOiiO_dataout <= nliliO11O OR nl0illlll; + wire_nliliOil_dataout <= nll0O0l1l WHEN niOO1OOli = '1' ELSE wire_nl1iliiOl_dataout; + wire_nliliOili_dataout <= nliliO10l AND NOT(nl0illlll); + wire_nliliOill_dataout <= wire_nliliOl1O_dataout WHEN nl0illlll = '1' ELSE nlililOli; + wire_nliliOilO_dataout <= wire_nliliOl0i_dataout WHEN nl0illlll = '1' ELSE nliliO11i; + wire_nliliOiO_dataout <= nll0O0l1O WHEN niOO1OOli = '1' ELSE wire_nl1iliiOO_dataout; + wire_nliliOiOi_dataout <= wire_nliliOl0l_dataout WHEN nl0illlll = '1' ELSE nliliO11l; + wire_nliliOiOl_dataout <= wire_nliliOl0O_dataout WHEN nl0illlll = '1' ELSE nliliO10O; + wire_nliliOiOO_dataout <= wire_nliliOlii_dataout WHEN nl0illlll = '1' ELSE nliliO1ii; + wire_nliliOl0i_dataout <= wire_nliliOllO_o(1) WHEN niOilOOii = '1' ELSE wire_nliliOlOl_dataout; + wire_nliliOl0l_dataout <= wire_nliliOllO_o(2) WHEN niOilOOii = '1' ELSE wire_nliliOlOO_dataout; + wire_nliliOl0O_dataout <= wire_nliliOllO_o(0) WHEN niOilOOii = '1' ELSE wire_nliliOO1i_dataout; + wire_nliliOl1i_dataout <= wire_nliliOlil_dataout WHEN nl0illlll = '1' ELSE nliliO1il; + wire_nliliOl1l_dataout <= wire_nliliOliO_dataout WHEN nl0illlll = '1' ELSE nliliO1li; + wire_nliliOl1O_dataout <= wire_nliliOllO_o(0) WHEN niOilOOii = '1' ELSE wire_nliliOlOi_dataout; + wire_nliliOli_dataout <= nll0O0l0i WHEN niOO1OOli = '1' ELSE wire_nl1ilil1i_dataout; + wire_nliliOlii_dataout <= wire_nliliOllO_o(1) WHEN niOilOOii = '1' ELSE wire_nliliOO1l_dataout; + wire_nliliOlil_dataout <= wire_nliliOllO_o(2) WHEN niOilOOii = '1' ELSE wire_nliliOO1O_dataout; + wire_nliliOliO_dataout <= wire_nliliOO0i_dataout OR niOilOOii; + wire_nliliOll_dataout <= nll0O0l0l WHEN niOO1OOli = '1' ELSE wire_nl1ilil1l_dataout; + wire_nliliOlO_dataout <= nll0O0l0O WHEN niOO1OOli = '1' ELSE wire_nl1ilil1O_dataout; + wire_nliliOlOi_dataout <= nliliO10O WHEN niOilOOil = '1' ELSE wire_nliliOOil_dataout; + wire_nliliOlOl_dataout <= wire_nliliOOii_o(0) WHEN niOilOOil = '1' ELSE wire_nliliOOiO_dataout; + wire_nliliOlOO_dataout <= wire_nliliOOii_o(1) WHEN niOilOOil = '1' ELSE wire_nliliOOli_dataout; + wire_nliliOO0i_dataout <= wire_nliliOOOl_dataout OR niOilOOil; + wire_nliliOO0i_w_lg_dataout43231w(0) <= NOT wire_nliliOO0i_dataout; + wire_nliliOO1i_dataout <= nliliO10O WHEN niOilOOil = '1' ELSE wire_nliliOOll_dataout; + wire_nliliOO1l_dataout <= wire_nliliOOii_o(0) WHEN niOilOOil = '1' ELSE wire_nliliOOlO_dataout; + wire_nliliOO1O_dataout <= wire_nliliOOii_o(1) WHEN niOilOOil = '1' ELSE wire_nliliOOOi_dataout; + wire_nliliOOi_dataout <= nll0O0lii WHEN niOO1OOli = '1' ELSE wire_nl1ilil0i_dataout; + wire_nliliOOil_dataout <= wire_nlill111l_o(0) WHEN niOilOOiO = '1' ELSE wire_nlill111O_dataout; + wire_nliliOOiO_dataout <= wire_nlill111l_o(1) WHEN niOilOOiO = '1' ELSE wire_nlill110i_dataout; + wire_nliliOOl_dataout <= nll0O0lil WHEN niOO1OOli = '1' ELSE wire_nl1ilil0l_dataout; + wire_nliliOOli_dataout <= wire_nlill111l_o(2) WHEN niOilOOiO = '1' ELSE wire_nlill110l_dataout; + wire_nliliOOll_dataout <= wire_nlill111l_o(0) WHEN niOilOOiO = '1' ELSE wire_nlill110O_dataout; + wire_nliliOOlO_dataout <= wire_nlill111l_o(1) WHEN niOilOOiO = '1' ELSE wire_nlill11ii_dataout; + wire_nliliOOO_dataout <= nll0O0liO WHEN niOO1OOli = '1' ELSE wire_nl1ilil0O_dataout; + wire_nliliOOOi_dataout <= wire_nlill111l_o(2) WHEN niOilOOiO = '1' ELSE wire_nlill11il_dataout; + wire_nliliOOOl_dataout <= wire_nlill11iO_dataout OR niOilOOiO; + wire_nliliOOOl_w_lg_dataout43190w(0) <= NOT wire_nliliOOOl_dataout; + wire_nlill00i_dataout <= nll0O0OOi WHEN niOO1OOli = '1' ELSE wire_nl1iliOli_dataout; + wire_nlill00l_dataout <= nll0O0OOl WHEN niOO1OOli = '1' ELSE wire_nl1iliOll_dataout; + wire_nlill00O_dataout <= nll0O0OOO WHEN niOO1OOli = '1' ELSE wire_nl1iliOlO_dataout; + wire_nlill00Ol_dataout <= nlill1lli AND NOT(wire_niO01O0O_dataout); + wire_nlill011i_dataout <= nlill1l0O AND NOT(niOilOOOO); + wire_nlill011l_dataout <= nlill1lii AND NOT(niOilOOOO); + wire_nlill01i_dataout <= nll0O0Oli WHEN niOO1OOli = '1' ELSE wire_nl1iliOii_dataout; + wire_nlill01il_dataout <= wire_nlill01iO_dataout AND NOT((wire_nilOi0li_dataout AND (((((((((niOiO11OO OR niOiO11Ol) OR niOiO11Oi) OR niOiO11lO) OR niOiO11ll) OR niOiO11li) OR niOiO11iO) OR niOiO11il) OR niOiO11ii) OR niOiO110O))); + wire_nlill01iO_dataout <= nlill1liO OR (wire_nl1000i_w_lg_w_lg_niOOi01il42910w42911w(0) AND wire_w_lg_w_lg_w_lg_w42915w42916w42917w42918w(0)); + wire_nlill01l_dataout <= nll0O0Oll WHEN niOO1OOli = '1' ELSE wire_nl1iliOil_dataout; + wire_nlill01O_dataout <= nll0O0OlO WHEN niOO1OOli = '1' ELSE wire_nl1iliOiO_dataout; + wire_nlill0ii_dataout <= nll0Oi11i WHEN niOO1OOli = '1' ELSE wire_nl1iliOOi_dataout; + wire_nlill0il_dataout <= nll0Oi11l WHEN niOO1OOli = '1' ELSE wire_nl1iliOOl_dataout; + wire_nlill0ilO_dataout <= wire_nlill0l1l_dataout AND NOT(niOiO10iO); + wire_nlill0iO_dataout <= nll0Oi11O WHEN niOO1OOli = '1' ELSE wire_nl1iliOOO_dataout; + wire_nlill0iOi_dataout <= wire_nlill0l1O_dataout AND NOT(niOiO10iO); + wire_nlill0iOl_dataout <= wire_nlill0l0i_dataout AND NOT(niOiO10iO); + wire_nlill0iOO_dataout <= wire_nlill0l0l_dataout AND NOT(niOiO10iO); + wire_nlill0l0i_dataout <= wire_nlill0lil_dataout AND NOT(niOiO10li); + wire_nlill0l0l_dataout <= niOiO10ll AND NOT(niOiO10li); + wire_nlill0l0O_dataout <= wire_nlill0liO_dataout AND NOT(niOiO10ll); + wire_nlill0l1i_dataout <= niOiO10li AND NOT(niOiO10iO); + wire_nlill0l1l_dataout <= wire_nlill0l0O_dataout AND NOT(niOiO10li); + wire_nlill0l1O_dataout <= wire_nlill0lii_dataout AND NOT(niOiO10li); + wire_nlill0li_dataout <= nll0Oi10i WHEN niOO1OOli = '1' ELSE wire_nl1ill11i_dataout; + wire_nlill0lii_dataout <= wire_nlill0lli_dataout AND NOT(niOiO10ll); + wire_nlill0lil_dataout <= niOiO10lO AND NOT(niOiO10ll); + wire_nlill0liO_dataout <= wire_w_lg_niOiO10Oi42898w(0) AND NOT(niOiO10lO); + wire_nlill0ll_dataout <= nll0Oi10l WHEN niOO1OOli = '1' ELSE wire_nl1ill11l_dataout; + wire_nlill0lli_dataout <= niOiO10Oi AND NOT(niOiO10lO); + wire_nlill0llO_dataout <= wire_nlill0lOO_dataout AND NOT(niOiO10Ol); + wire_nlill0llO_w_lg_dataout59397w(0) <= NOT wire_nlill0llO_dataout; + wire_nlill0lO_dataout <= nll0Oi10O WHEN niOO1OOli = '1' ELSE wire_nl1ill11O_dataout; + wire_nlill0lOi_dataout <= wire_nlill0O1i_dataout AND NOT(niOiO10Ol); + wire_nlill0lOi_w_lg_dataout59395w(0) <= NOT wire_nlill0lOi_dataout; + wire_nlill0lOl_dataout <= wire_nlill0O1l_dataout AND NOT(niOiO10Ol); + wire_nlill0lOl_w_lg_dataout59394w(0) <= NOT wire_nlill0lOl_dataout; + wire_nlill0lOO_dataout <= wire_nlill0O1O_dataout OR niOiO10OO; + wire_nlill0O0i_dataout <= wire_nlill0Oii_dataout OR niOiO1i1i; + wire_nlill0O0l_dataout <= wire_w_lg_niOiO1i1l42897w(0) AND NOT(niOiO1i1i); + wire_nlill0O0O_dataout <= wire_nlill0Oil_dataout OR niOiO1i1l; + wire_nlill0O1i_dataout <= wire_nlill0O0i_dataout AND NOT(niOiO10OO); + wire_nlill0O1l_dataout <= wire_nlill0O0l_dataout AND NOT(niOiO10OO); + wire_nlill0O1O_dataout <= wire_nlill0O0O_dataout AND NOT(niOiO1i1i); + wire_nlill0Oi_dataout <= nll0Oi1ii WHEN niOO1OOli = '1' ELSE wire_nl1ill10i_dataout; + wire_nlill0Oii_dataout <= wire_nlill0OiO_dataout OR niOiO1i1l; + wire_nlill0Oil_dataout <= wire_nlill0Oli_dataout AND NOT(niOiO1i1O); + wire_nlill0OiO_dataout <= wire_w_lg_niOiO1i0i42896w(0) AND NOT(niOiO1i1O); + wire_nlill0Ol_dataout <= nll0Oi1il WHEN niOO1OOli = '1' ELSE wire_nl1ill10l_dataout; + wire_nlill0Oli_dataout <= (NOT ((wire_nilOlilO_w_lg_dataout42890w(0) AND wire_nilOlill_w_lg_dataout42891w(0)) AND wire_nilOlili_w_lg_dataout42893w(0))) OR niOiO1i0i; + wire_nlill0OO_dataout <= nll0Oi1iO WHEN niOO1OOli = '1' ELSE wire_nl1ill10O_dataout; + wire_nlill0OOi_dataout <= nlill0OlO AND NOT(wire_niO01O0O_dataout); + wire_nlill0OOl_dataout <= wire_nilOO00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlill100i_dataout <= wire_nlill10Ol_dataout OR niOilOOll; + wire_nlill100i_w_lg_dataout43113w(0) <= NOT wire_nlill100i_dataout; + wire_nlill101i_dataout <= wire_nlill10ii_o(0) WHEN niOilOOll = '1' ELSE wire_nlill10ll_dataout; + wire_nlill101l_dataout <= wire_nlill10ii_o(1) WHEN niOilOOll = '1' ELSE wire_nlill10lO_dataout; + wire_nlill101O_dataout <= wire_nlill10ii_o(2) WHEN niOilOOll = '1' ELSE wire_nlill10Oi_dataout; + wire_nlill10i_dataout <= nll0O0lOi WHEN niOO1OOli = '1' ELSE wire_nl1ililli_dataout; + wire_nlill10il_dataout <= nliliO10O WHEN niOilOOlO = '1' ELSE wire_nlill1i1O_dataout; + wire_nlill10iO_dataout <= wire_nlill1i1l_o(0) WHEN niOilOOlO = '1' ELSE wire_nlill1i0i_dataout; + wire_nlill10l_dataout <= nll0O0lOl WHEN niOO1OOli = '1' ELSE wire_nl1ililll_dataout; + wire_nlill10li_dataout <= wire_nlill1i1l_o(1) WHEN niOilOOlO = '1' ELSE wire_nlill1i0l_dataout; + wire_nlill10ll_dataout <= nliliO10O WHEN niOilOOlO = '1' ELSE wire_nlill1iii_dataout; + wire_nlill10lO_dataout <= wire_nlill1i1l_o(0) WHEN niOilOOlO = '1' ELSE wire_nlill1iil_dataout; + wire_nlill10O_dataout <= nll0O0lOO WHEN niOO1OOli = '1' ELSE wire_nl1ilillO_dataout; + wire_nlill10Oi_dataout <= wire_nlill1i1l_o(1) WHEN niOilOOlO = '1' ELSE wire_nlill1iiO_dataout; + wire_nlill10Ol_dataout <= wire_nlill1ili_dataout OR niOilOOlO; + wire_nlill10Ol_w_lg_dataout43082w(0) <= NOT wire_nlill10Ol_dataout; + wire_nlill110i_dataout <= nliliO1ii WHEN niOilOOli = '1' ELSE wire_nlill11Ol_dataout; + wire_nlill110l_dataout <= wire_nlill11lO_o(0) WHEN niOilOOli = '1' ELSE wire_nlill11OO_dataout; + wire_nlill110O_dataout <= nliliO10O WHEN niOilOOli = '1' ELSE wire_nlill101i_dataout; + wire_nlill111O_dataout <= nliliO10O WHEN niOilOOli = '1' ELSE wire_nlill11Oi_dataout; + wire_nlill11i_dataout <= nll0O0lli WHEN niOO1OOli = '1' ELSE wire_nl1ililii_dataout; + wire_nlill11ii_dataout <= nliliO1ii WHEN niOilOOli = '1' ELSE wire_nlill101l_dataout; + wire_nlill11il_dataout <= wire_nlill11lO_o(0) WHEN niOilOOli = '1' ELSE wire_nlill101O_dataout; + wire_nlill11iO_dataout <= wire_nlill100i_dataout OR niOilOOli; + wire_nlill11iO_w_lg_dataout43154w(0) <= NOT wire_nlill11iO_dataout; + wire_nlill11l_dataout <= nll0O0lll WHEN niOO1OOli = '1' ELSE wire_nl1ililil_dataout; + wire_nlill11O_dataout <= nll0O0llO WHEN niOO1OOli = '1' ELSE wire_nl1ililiO_dataout; + wire_nlill11Oi_dataout <= wire_nlill10ii_o(0) WHEN niOilOOll = '1' ELSE wire_nlill10il_dataout; + wire_nlill11Ol_dataout <= wire_nlill10ii_o(1) WHEN niOilOOll = '1' ELSE wire_nlill10iO_dataout; + wire_nlill11OO_dataout <= wire_nlill10ii_o(2) WHEN niOilOOll = '1' ELSE wire_nlill10li_dataout; + wire_nlill1i0i_dataout <= wire_nlill1iOi_o(1) WHEN niOilOOOi = '1' ELSE wire_nlill1iOO_dataout; + wire_nlill1i0l_dataout <= wire_nlill1iOi_o(2) WHEN niOilOOOi = '1' ELSE wire_nlill1l1i_dataout; + wire_nlill1i1O_dataout <= wire_nlill1iOi_o(0) WHEN niOilOOOi = '1' ELSE wire_nlill1iOl_dataout; + wire_nlill1ii_dataout <= nll0O0O1i WHEN niOO1OOli = '1' ELSE wire_nl1ililOi_dataout; + wire_nlill1iii_dataout <= wire_nlill1iOi_o(0) WHEN niOilOOOi = '1' ELSE nliliO10O; + wire_nlill1iil_dataout <= wire_nlill1iOi_o(1) WHEN niOilOOOi = '1' ELSE nliliO1ii; + wire_nlill1iiO_dataout <= wire_nlill1iOi_o(2) WHEN niOilOOOi = '1' ELSE nliliO1il; + wire_nlill1il_dataout <= nll0O0O1l WHEN niOO1OOli = '1' ELSE wire_nl1ililOl_dataout; + wire_nlill1ili_dataout <= wire_nlill1l1l_dataout OR niOilOOOi; + wire_nlill1ili_w_lg_dataout43041w(0) <= NOT wire_nlill1ili_dataout; + wire_nlill1iO_dataout <= nll0O0O1O WHEN niOO1OOli = '1' ELSE wire_nl1ililOO_dataout; + wire_nlill1iOl_dataout <= nliliO10O WHEN niOilOOOl = '1' ELSE nlililOli; + wire_nlill1iOO_dataout <= nliliO1ii WHEN niOilOOOl = '1' ELSE nliliO11i; + wire_nlill1l0l_dataout <= nl11OO0iO AND ((wire_nlill0Oll_w_lg_nliliO11l42939w(0) AND wire_nlill0Oll_w_lg_nliliO11i42940w(0)) AND wire_nlill0Oll_w_lg_nlililOli42942w(0)); + wire_nlill1l1i_dataout <= nliliO1il WHEN niOilOOOl = '1' ELSE nliliO11l; + wire_nlill1l1l_dataout <= nliliO1li OR niOilOOOl; + wire_nlill1l1l_w_lg_dataout43005w(0) <= NOT wire_nlill1l1l_dataout; + wire_nlill1li_dataout <= nll0O0O0i WHEN niOO1OOli = '1' ELSE wire_nl1iliO1i_dataout; + wire_nlill1ll_dataout <= nll0O0O0l WHEN niOO1OOli = '1' ELSE wire_nl1iliO1l_dataout; + wire_nlill1lll_dataout <= wire_nlill1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlill1llO_dataout <= wire_nlill1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlill1lO_dataout <= nll0O0O0O WHEN niOO1OOli = '1' ELSE wire_nl1iliO1O_dataout; + wire_nlill1lOi_dataout <= wire_nlill1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlill1lOl_dataout <= wire_nlill1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlill1lOO_dataout <= wire_nlill1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlill1O0i_dataout <= nlill1lii WHEN niOiO110l = '1' ELSE wire_nlill1OiO_dataout; + wire_nlill1O0l_dataout <= nlill1liO WHEN niOiO110l = '1' ELSE wire_nlill1Oli_dataout; + wire_nlill1O0O_dataout <= wire_nlill01il_dataout WHEN niOiO111O = '1' ELSE wire_nlill1Oll_dataout; + wire_nlill1O1i_dataout <= wire_nlill01il_dataout WHEN niOiO110l = '1' ELSE wire_nlill1O0O_dataout; + wire_nlill1O1l_dataout <= nlill1i0O WHEN niOiO110l = '1' ELSE wire_nlill1Oii_dataout; + wire_nlill1O1O_dataout <= nlill1l0O WHEN niOiO110l = '1' ELSE wire_nlill1Oil_dataout; + wire_nlill1Oi_dataout <= nll0O0Oii WHEN niOO1OOli = '1' ELSE wire_nl1iliO0i_dataout; + wire_nlill1Oii_dataout <= wire_nlill1OlO_dataout WHEN niOiO111O = '1' ELSE nlill1i0O; + wire_nlill1Oil_dataout <= wire_nlill1OOi_dataout WHEN niOiO111O = '1' ELSE nlill1l0O; + wire_nlill1OiO_dataout <= wire_nlill1OOl_dataout WHEN niOiO111O = '1' ELSE nlill1lii; + wire_nlill1Ol_dataout <= nll0O0Oil WHEN niOO1OOli = '1' ELSE wire_nl1iliO0l_dataout; + wire_nlill1Oli_dataout <= nlill1lil AND NOT(niOiO111O); + wire_nlill1Oll_dataout <= wire_nlill01il_dataout AND NOT(niOiO110i); + wire_nlill1OlO_dataout <= nlill1i0O WHEN niOiO111i = '1' ELSE wire_nlill1OOO_dataout; + wire_nlill1OO_dataout <= nll0O0OiO WHEN niOO1OOli = '1' ELSE wire_nl1iliO0O_dataout; + wire_nlill1OOi_dataout <= nlill1l0O WHEN niOiO111i = '1' ELSE wire_nlill011i_dataout; + wire_nlill1OOl_dataout <= nlill1lii WHEN niOiO111i = '1' ELSE wire_nlill011l_dataout; + wire_nlill1OOO_dataout <= nlill1i0O AND NOT(niOilOOOO); + wire_nlilli0i_dataout <= nll0Oi1Oi WHEN niOO1OOli = '1' ELSE wire_nl1ill1li_dataout; + wire_nlilli0l_dataout <= nll0Oi1Ol WHEN niOO1OOli = '1' ELSE wire_nl1ill1ll_dataout; + wire_nlilli0O_dataout <= nll0Oi1OO WHEN niOO1OOli = '1' ELSE wire_nl1ill1lO_dataout; + wire_nlilli1i_dataout <= nll0Oi1li WHEN niOO1OOli = '1' ELSE wire_nl1ill1ii_dataout; + wire_nlilli1l_dataout <= nll0Oi1ll WHEN niOO1OOli = '1' ELSE wire_nl1ill1il_dataout; + wire_nlilli1O_dataout <= nll0Oi1lO WHEN niOO1OOli = '1' ELSE wire_nl1ill1iO_dataout; + wire_nlilliii_dataout <= nll0Oi01i WHEN niOO1OOli = '1' ELSE wire_nl1ill1Oi_dataout; + wire_nlilliil_dataout <= nll0Oi01l WHEN niOO1OOli = '1' ELSE wire_nl1ill1Ol_dataout; + wire_nlilliiO_dataout <= nll0Oi01O WHEN niOO1OOli = '1' ELSE wire_nl1ill1OO_dataout; + wire_nlillil0i_dataout <= wire_nlillll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillil0l_dataout <= wire_nlilllili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillil0O_dataout <= wire_nlillli1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillili_dataout <= nll0Oi00i WHEN niOO1OOli = '1' ELSE wire_nl1ill01i_dataout; + wire_nlillilii_dataout <= wire_nlilll0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillilil_dataout <= wire_nlilll00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliliO_dataout <= wire_nlilll1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillill_dataout <= nll0Oi00l WHEN niOO1OOli = '1' ELSE wire_nl1ill01l_dataout; + wire_nlillilli_dataout <= wire_nlilll10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillilll_dataout <= wire_nlilliOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillillO_dataout <= wire_nlillliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillilO_dataout <= nll0Oi00O WHEN niOO1OOli = '1' ELSE wire_nl1ill01O_dataout; + wire_nlillilOi_dataout <= wire_nlillli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillilOl_dataout <= wire_nlilll0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlillilOO_dataout <= wire_nlilll0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliO0i_dataout <= wire_nlilliOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliO0l_dataout <= wire_nlillll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliO0O_dataout <= wire_nlilllO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliO1i_dataout <= wire_nlilll1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliO1l_dataout <= wire_nlilll1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliO1O_dataout <= wire_nlilll11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliOi_dataout <= nll0Oi0ii WHEN niOO1OOli = '1' ELSE wire_nl1ill00i_dataout; + wire_nlilliOii_dataout <= wire_nlilllOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliOil_dataout <= wire_nlilllOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilliOiO_dataout <= wire_nlilliOli_dataout AND NOT(niOiO1i0l); + wire_nlilliOl_dataout <= nll0Oi0il WHEN niOO1OOli = '1' ELSE wire_nl1ill00l_dataout; + wire_nlilliOli_dataout <= nlilliilO OR (niOiO1llO AND niOiO1i0O); + wire_nlilliOO_dataout <= nll0Oi0iO WHEN niOO1OOli = '1' ELSE wire_nl1ill00O_dataout; + wire_nlilliOOi_dataout <= wire_nlilliOOl_dataout AND NOT(niOiO1i0l); + wire_nlilliOOl_dataout <= nlillii0i OR (niOiO1lOl AND niOiO1i0O); + wire_nlilll00i_dataout <= wire_nlilll00l_dataout AND NOT(niOiO1ill); + wire_nlilll00l_dataout <= nlillii1i OR (niOiO1lOl AND niOiO1ilO); + wire_nlilll01i_dataout <= nlilliiiO OR (niOiO1llO AND niOiO1ilO); + wire_nlilll0i_dataout <= nll0Oi0Oi WHEN niOO1OOli = '1' ELSE wire_nl1ill0li_dataout; + wire_nlilll0ii_dataout <= wire_nlilll0il_dataout AND NOT(niOiO1iOi); + wire_nlilll0il_dataout <= nlilliiil OR (niOiO1llO AND niOiO1iOl); + wire_nlilll0l_dataout <= nll0Oi0Ol WHEN niOO1OOli = '1' ELSE wire_nl1ill0ll_dataout; + wire_nlilll0ll_dataout <= wire_nlilll0lO_dataout AND NOT(niOiO1iOi); + wire_nlilll0lO_dataout <= nlilli0OO OR (niOiO1lOl AND niOiO1iOl); + wire_nlilll0O_dataout <= nll0Oi0OO WHEN niOO1OOli = '1' ELSE wire_nl1ill0lO_dataout; + wire_nlilll0Ol_dataout <= wire_nlilll0OO_dataout AND NOT(niOiO1iOO); + wire_nlilll0OO_dataout <= nlilliiii OR (niOiO1llO AND niOiO1l1i); + wire_nlilll10l_dataout <= wire_nlilll10O_dataout AND NOT(niOiO1iii); + wire_nlilll10O_dataout <= nlillii1O OR (niOiO1lOl AND niOiO1iil); + wire_nlilll11i_dataout <= wire_nlilll11l_dataout AND NOT(niOiO1iii); + wire_nlilll11l_dataout <= nlilliill OR (niOiO1llO AND niOiO1iil); + wire_nlilll1i_dataout <= nll0Oi0li WHEN niOO1OOli = '1' ELSE wire_nl1ill0ii_dataout; + wire_nlilll1il_dataout <= wire_nlilll1iO_dataout AND NOT(niOiO1iiO); + wire_nlilll1iO_dataout <= nlilliili OR (niOiO1llO AND niOiO1ili); + wire_nlilll1l_dataout <= nll0Oi0ll WHEN niOO1OOli = '1' ELSE wire_nl1ill0il_dataout; + wire_nlilll1lO_dataout <= wire_nlilll1Oi_dataout AND NOT(niOiO1iiO); + wire_nlilll1O_dataout <= nll0Oi0lO WHEN niOO1OOli = '1' ELSE wire_nl1ill0iO_dataout; + wire_nlilll1Oi_dataout <= nlillii1l OR (niOiO1lOl AND niOiO1ili); + wire_nlilll1OO_dataout <= wire_nlilll01i_dataout AND NOT(niOiO1ill); + wire_nlillli0i_dataout <= nlilli0Ol OR (niOiO1lOl AND niOiO1l1i); + wire_nlillli0O_dataout <= wire_nlillliii_dataout AND NOT(niOiO1l1l); + wire_nlillli1O_dataout <= wire_nlillli0i_dataout AND NOT(niOiO1iOO); + wire_nlilllii_dataout <= nll0Oii1i WHEN niOO1OOli = '1' ELSE wire_nl1ill0Oi_dataout; + wire_nlillliii_dataout <= nlillii0O OR (niOiO1llO AND niOiO1l1O); + wire_nlilllil_dataout <= nll0Oii1l WHEN niOO1OOli = '1' ELSE wire_nl1ill0Ol_dataout; + wire_nlilllili_dataout <= wire_nlilllill_dataout AND NOT(niOiO1l1l); + wire_nlilllill_dataout <= nlilli0Oi OR (niOiO1lOl AND niOiO1l1O); + wire_nlillliO_dataout <= nll0Oii1O WHEN niOO1OOli = '1' ELSE wire_nl1ill0OO_dataout; + wire_nlillliOi_dataout <= wire_nlillliOl_dataout AND NOT(niOiO1l0i); + wire_nlillliOl_dataout <= nlillii0l OR (niOiO1llO AND niOiO1l0l); + wire_nlillll0l_dataout <= wire_nlillll0O_dataout AND NOT((wire_nlillllOO_w_lg_o42294w(0) OR wire_nlOii0Oll_w_lg_dataout42177w(0))); + wire_nlillll0O_dataout <= wire_nlillllii_dataout OR (wire_nl1000i_w_lg_w_lg_nlilliiOi42828w42829w(0) AND (wire_w_lg_w_lg_niOiO1lii42830w42831w(0) OR wire_nilOl00i_w_lg_dataout42840w(0))); + wire_nlillll1l_dataout <= wire_nlillll1O_dataout AND NOT(niOiO1l0i); + wire_nlillll1O_dataout <= nlillil1l OR (niOiO1lOl AND niOiO1l0l); + wire_nlillllii_dataout <= nlilliiOi AND NOT(niOiO1OOi); + wire_nlilllO1i_dataout <= wire_nlilllO1l_dataout AND NOT(niOiO1l0O); + wire_nlilllO1l_dataout <= nlilliiOl OR (niOl101Ol AND ((((nlliiilii AND nlliiil0O) AND wire_nl1000i_w_lg_nlliiil0l34446w(0)) AND nlliiiliO) AND niOiO1lii)); + wire_nlilllOli_dataout <= wire_nlilllOll_dataout AND NOT(niOiO1l0O); + wire_nlilllOll_dataout <= nlilliiOO OR (niOl101Ol AND (((wire_nl1000i_w_lg_nlliiilii42785w(0) AND nlliiil0l) AND nlliiiliO) AND niOiO1lii)); + wire_nlilllOOO_dataout <= wire_nlillO11i_dataout AND NOT(niOiO1l0O); + wire_nlillO11i_dataout <= nlillil1i OR (niOl101Ol AND (((wire_nl1000i_w_lg_nlliiilii42785w(0) AND wire_nl1000i_w_lg_nlliiil0l34446w(0)) AND nlliiiliO) AND niOiO1lii)); + wire_nlillO1iO_dataout <= nlillil1O AND NOT((((nlillOlil AND nlilliiOi) AND wire_nlOi1Oi1O_dataout) AND niOiO1lOO)); + wire_nlillO1iO_w_lg_dataout29688w(0) <= NOT wire_nlillO1iO_dataout; + wire_nlillOlOO_dataout <= wire_nlilO1O1i_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOO0i_dataout <= wire_nlilO1iOl_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOO0l_dataout <= wire_nlilO1iOO_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOO0O_dataout <= wire_nlilO1l1i_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOO1i_dataout <= wire_nlilO1ill_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOO1l_dataout <= wire_nlilO1ilO_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOO1O_dataout <= wire_nlilO1iOi_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOii_dataout <= wire_nlilO1l1l_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOil_dataout <= wire_nlilO1l1O_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOiO_dataout <= wire_nlilO1l0i_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOl_dataout <= nliO0O0i WHEN niOO0111i = '1' ELSE nliOilil; + wire_nlillOOli_dataout <= wire_nlilO1l0l_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOll_dataout <= wire_nlilO1l0O_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOlO_dataout <= wire_nlilO1lii_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOO_dataout <= nliO0O0l WHEN niOO0111i = '1' ELSE nliOiliO; + wire_nlillOOOi_dataout <= wire_nlilO1lil_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOOl_dataout <= wire_nlilO1liO_o AND NOT(wire_niO01O0O_dataout); + wire_nlillOOOO_dataout <= wire_nlilO1lli_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO000i_dataout <= nlillOliO AND NOT(niOiO1OOO); + wire_nlilO000l_dataout <= wire_nlilO0lii_dataout WHEN niOiO1OOO = '1' ELSE nlillOlli; + wire_nlilO000O_dataout <= nlillOlll AND NOT(niOiO1OOO); + wire_nlilO001i_dataout <= wire_nlilO0l0l_dataout WHEN niOiO1OOO = '1' ELSE nlillil1O; + wire_nlilO001l_dataout <= wire_nlilO0l0O_dataout WHEN niOiO1OOO = '1' ELSE nlillOlii; + wire_nlilO001O_dataout <= nlillOlil AND NOT(niOiO1OOO); + wire_nlilO00i_dataout <= nliOi1iO WHEN niOO0111i = '1' ELSE nliOiOOi; + wire_nlilO00ii_dataout <= nlillOllO AND NOT(niOiO1OOO); + wire_nlilO00il_dataout <= niOiO1lOi WHEN niOiO1OOO = '1' ELSE nlillOlOi; + wire_nlilO00iO_dataout <= nlillOi1O AND NOT(niOiO1OOO); + wire_nlilO00l_dataout <= nliOi1li WHEN niOO0111i = '1' ELSE nliOiOOl; + wire_nlilO00li_dataout <= nlillOi0i OR niOiO1OOO; + wire_nlilO00ll_dataout <= nlillOlOl WHEN niOiO1OOO = '1' ELSE nlillO1Oi; + wire_nlilO00lO_dataout <= nlilOilli WHEN niOiO1OOO = '1' ELSE nlillO1Ol; + wire_nlilO00O_dataout <= nliOi1ll WHEN niOO0111i = '1' ELSE nliOiOOO; + wire_nlilO00Oi_dataout <= nlilOilll WHEN niOiO1OOO = '1' ELSE nlillO1OO; + wire_nlilO00Ol_dataout <= nlilOillO WHEN niOiO1OOO = '1' ELSE nlillO01i; + wire_nlilO00OO_dataout <= nlilOilOi WHEN niOiO1OOO = '1' ELSE nlillO01l; + wire_nlilO010i_dataout <= nlillOiOO OR niOiO1O1l; + wire_nlilO010l_dataout <= nlillOlii AND NOT(niOiO1O1l); + wire_nlilO010O_dataout <= nlillOlil AND NOT(niOiO1O1l); + wire_nlilO011i_dataout <= wire_nlilOiiil_dataout WHEN nlillOlOi = '1' ELSE nlillOl0l; + wire_nlilO011l_dataout <= wire_nlilOiiiO_dataout WHEN nlillOlOi = '1' ELSE nlillOl0O; + wire_nlilO011O_dataout <= nlillil1O OR niOiO1O1l; + wire_nlilO01i_dataout <= nliOi10O WHEN niOO0111i = '1' ELSE nliOiOli; + wire_nlilO01ii_dataout <= nlillOliO AND NOT(niOiO1O1l); + wire_nlilO01il_dataout <= nlillOlli OR niOiO1O1l; + wire_nlilO01iO_dataout <= nlillOlll AND NOT(niOiO1O1l); + wire_nlilO01l_dataout <= nliOi1ii WHEN niOO0111i = '1' ELSE nliOiOll; + wire_nlilO01li_dataout <= nlillOllO AND NOT(niOiO1O1l); + wire_nlilO01ll_dataout <= nlillOlOi AND NOT(niOiO1O1l); + wire_nlilO01lO_dataout <= wire_nlilO0l1i_dataout WHEN niOiO1OOO = '1' ELSE nlillOi0l; + wire_nlilO01O_dataout <= nliOi1il WHEN niOO0111i = '1' ELSE nliOiOlO; + wire_nlilO01Oi_dataout <= wire_nlilO0l1l_dataout WHEN niOiO1OOO = '1' ELSE nlillOi0O; + wire_nlilO01Ol_dataout <= wire_nlilO0l1O_dataout WHEN niOiO1OOO = '1' ELSE nlillOiii; + wire_nlilO01OO_dataout <= wire_nlilO0l0i_dataout WHEN niOiO1OOO = '1' ELSE nlillOiil; + wire_nlilO0i0i_dataout <= nlilOiO1l WHEN niOiO1OOO = '1' ELSE nlillO00O; + wire_nlilO0i0l_dataout <= nlilOiO1O WHEN niOiO1OOO = '1' ELSE nlillO0ii; + wire_nlilO0i0O_dataout <= nlilOiO0i WHEN niOiO1OOO = '1' ELSE nlillO0il; + wire_nlilO0i1i_dataout <= nlilOilOl WHEN niOiO1OOO = '1' ELSE nlillO01O; + wire_nlilO0i1l_dataout <= nlilOilOO WHEN niOiO1OOO = '1' ELSE nlillO00i; + wire_nlilO0i1O_dataout <= nlilOiO1i WHEN niOiO1OOO = '1' ELSE nlillO00l; + wire_nlilO0ii_dataout <= nliOi1lO WHEN niOO0111i = '1' ELSE nliOl11i; + wire_nlilO0iii_dataout <= nlilOiO0l WHEN niOiO1OOO = '1' ELSE nlillO0iO; + wire_nlilO0iil_dataout <= nlilOiO0O WHEN niOiO1OOO = '1' ELSE nlillO0li; + wire_nlilO0iiO_dataout <= nlilOiOii WHEN niOiO1OOO = '1' ELSE nlillO0ll; + wire_nlilO0il_dataout <= nliOi1Oi WHEN niOO0111i = '1' ELSE nliOl11l; + wire_nlilO0ili_dataout <= nlilOiOil WHEN niOiO1OOO = '1' ELSE nlillO0lO; + wire_nlilO0ill_dataout <= nlilOiOiO WHEN niOiO1OOO = '1' ELSE nlillO0Oi; + wire_nlilO0ilO_dataout <= nlilOiOli WHEN niOiO1OOO = '1' ELSE nlillO0Ol; + wire_nlilO0iO_dataout <= nliOi1Ol WHEN niOO0111i = '1' ELSE nliOl11O; + wire_nlilO0iOi_dataout <= nlilOiOll WHEN niOiO1OOO = '1' ELSE nlillO0OO; + wire_nlilO0iOl_dataout <= nlilOiOlO WHEN niOiO1OOO = '1' ELSE nlillOi1i; + wire_nlilO0iOO_dataout <= nlilOiOOi WHEN niOiO1OOO = '1' ELSE nlillOi1l; + wire_nlilO0l0i_dataout <= nlillOiil WHEN niOiO1lOi = '1' ELSE wire_nlilO0lli_dataout; + wire_nlilO0l0l_dataout <= wire_nlilO0lil_dataout AND NOT(niOiO1lOi); + wire_nlilO0l0O_dataout <= wire_nlilO0lll_dataout AND NOT(niOiO1lOi); + wire_nlilO0l1i_dataout <= nlillOi0l AND niOiO1lOi; + wire_nlilO0l1l_dataout <= nlillOi0O AND niOiO1lOi; + wire_nlilO0l1O_dataout <= nlillOiii WHEN niOiO1lOi = '1' ELSE wire_nlilO0liO_dataout; + wire_nlilO0li_dataout <= nliOi1OO WHEN niOO0111i = '1' ELSE nliOl10i; + wire_nlilO0lii_dataout <= wire_nlilO0llO_dataout AND NOT(niOiO1lOi); + wire_nlilO0lil_dataout <= wire_nlilO0lOi_dataout OR niOiO1lll; + wire_nlilO0liO_dataout <= nlillOiii OR niOiO1lll; + wire_nlilO0ll_dataout <= nliOi01i WHEN niOO0111i = '1' ELSE nliOl10l; + wire_nlilO0lli_dataout <= nlillOiil OR niOiO1lll; + wire_nlilO0lll_dataout <= wire_w_lg_niOiO1lOO42299w(0) AND NOT(niOiO1lll); + wire_nlilO0llO_dataout <= niOiO1lOO OR niOiO1lll; + wire_nlilO0lO_dataout <= nliOi01l WHEN niOO0111i = '1' ELSE nliOl10O; + wire_nlilO0lOi_dataout <= nlillil1O AND niOiO1lOO; + wire_nlilO0O0i_dataout <= nlillOi1O OR wire_nlOi1Oi1O_dataout; + wire_nlilO0O0l_dataout <= nlillOi0l AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilO0O0O_dataout <= nlillOi0O OR wire_nlOi1Oi1O_dataout; + wire_nlilO0O1O_dataout <= niOiO1lOO WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillil1O; + wire_nlilO0Oi_dataout <= nliOi01O WHEN niOO0111i = '1' ELSE nliOl1ii; + wire_nlilO0Oii_dataout <= nlillOlil OR wire_nlOi1Oi1O_dataout; + wire_nlilO0Oil_dataout <= nlillOliO AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilO0OiO_dataout <= nlillOi1O AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilO0Ol_dataout <= nliOi00i WHEN niOO0111i = '1' ELSE nliOl1il; + wire_nlilO0Oli_dataout <= nlillOi0i AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilO0Oll_dataout <= nlillOi0l OR wire_nlOi1Oi1O_dataout; + wire_nlilO0OlO_dataout <= nlillOi0O AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilO0OO_dataout <= nliOi00l WHEN niOO0111i = '1' ELSE nliOl1iO; + wire_nlilO0OOi_dataout <= nlillOlOl WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO1Oi; + wire_nlilO0OOl_dataout <= nlilOilli WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO1Ol; + wire_nlilO0OOO_dataout <= nlilOilll WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO1OO; + wire_nlilO100i_dataout <= wire_nlilO1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO100l_dataout <= wire_nlilO1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO100O_dataout <= wire_nlilO1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO101i_dataout <= wire_nlilOiiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO101l_dataout <= wire_nlilOiiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO101O_dataout <= wire_nlilO1i1l_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO10i_dataout <= nliO0OiO WHEN niOO0111i = '1' ELSE nliOilOi; + wire_nlilO10ii_dataout <= wire_nlilO1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO10il_dataout <= wire_nlilO011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO10iO_dataout <= wire_nlilO011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO10l_dataout <= nliO0Oli WHEN niOO0111i = '1' ELSE nliOilOl; + wire_nlilO10li_dataout <= wire_nlilO1O0l_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO10ll_dataout <= wire_nlilO1O0O_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO10lO_dataout <= wire_nlilO1Oii_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO10O_dataout <= nliO0Oll WHEN niOO0111i = '1' ELSE nliOilOO; + wire_nlilO10Oi_dataout <= wire_nlilO1Oil_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO10Ol_dataout <= wire_nlilO1OiO_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO10OO_dataout <= wire_nlilO1Oli_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO110i_dataout <= wire_nlilO1lOl_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO110l_dataout <= wire_nlilO1lOO_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO110O_dataout <= wire_nlilO1O1O_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO111i_dataout <= wire_nlilO1lll_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO111l_dataout <= wire_nlilO1llO_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO111O_dataout <= wire_nlilO1lOi_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO11i_dataout <= nliO0O0O WHEN niOO0111i = '1' ELSE nliOilli; + wire_nlilO11ii_dataout <= wire_nlilO1O0i_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO11il_dataout <= wire_nlilO1i0i_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO11iO_dataout <= wire_nlilO1i0l_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO11l_dataout <= nliO0Oii WHEN niOO0111i = '1' ELSE nliOilll; + wire_nlilO11li_dataout <= wire_nlilO1iii_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO11ll_dataout <= wire_nlilO1iil_o AND NOT(wire_niO01O0O_dataout); + wire_nlilO11lO_dataout <= wire_nlilOiili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO11O_dataout <= nliO0Oil WHEN niOO0111i = '1' ELSE nliOillO; + wire_nlilO11Oi_dataout <= wire_nlilOiill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO11Ol_dataout <= wire_nlilOiilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO11OO_dataout <= wire_nlilOiiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilO1i1i_dataout <= wire_nlilO1Oll_o OR wire_niO01O0O_dataout; + wire_nlilO1ii_dataout <= nliO0OlO WHEN niOO0111i = '1' ELSE nliOiO1i; + wire_nlilO1il_dataout <= nliO0OOi WHEN niOO0111i = '1' ELSE nliOiO1l; + wire_nlilO1iO_dataout <= nliO0OOl WHEN niOO0111i = '1' ELSE nliOiO1O; + wire_nlilO1li_dataout <= nliO0OOO WHEN niOO0111i = '1' ELSE nliOiO0i; + wire_nlilO1ll_dataout <= nliOi11i WHEN niOO0111i = '1' ELSE nliOiO0l; + wire_nlilO1lO_dataout <= nliOi11l WHEN niOO0111i = '1' ELSE nliOiO0O; + wire_nlilO1Oi_dataout <= nliOi11O WHEN niOO0111i = '1' ELSE nliOiOii; + wire_nlilO1Ol_dataout <= nliOi10i WHEN niOO0111i = '1' ELSE nliOiOil; + wire_nlilO1OlO_dataout <= wire_nlilOii0i_dataout WHEN nlillOlOi = '1' ELSE nlillOl1i; + wire_nlilO1OO_dataout <= nliOi10l WHEN niOO0111i = '1' ELSE nliOiOiO; + wire_nlilO1OOi_dataout <= wire_nlilOii0l_dataout WHEN nlillOlOi = '1' ELSE nlillOl1l; + wire_nlilO1OOl_dataout <= wire_nlilOii0O_dataout WHEN nlillOlOi = '1' ELSE nlillOl1O; + wire_nlilO1OOO_dataout <= wire_nlilOiiii_dataout WHEN nlillOlOi = '1' ELSE nlillOl0i; + wire_nlilOi00i_dataout <= nlillOlil AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilOi00l_dataout <= nlillOliO OR wire_nlOi1Oi1O_dataout; + wire_nlilOi00O_dataout <= nlillOlli AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilOi01i_dataout <= nlilOiOlO WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillOi1i; + wire_nlilOi01l_dataout <= nlilOiOOi WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillOi1l; + wire_nlilOi01O_dataout <= nlillOlii AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilOi0i_dataout <= nliOi0iO WHEN niOO0111i = '1' ELSE nliOl1Oi; + wire_nlilOi0ii_dataout <= nlillOlll AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilOi0il_dataout <= nlillOllO AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilOi0iO_dataout <= nlillOlOi AND NOT(wire_nlOi1Oi1O_dataout); + wire_nlilOi0l_dataout <= nliOi0li WHEN niOO0111i = '1' ELSE nliOl1Ol; + wire_nlilOi0li_dataout <= nlillOi1O AND NOT(niOiO1O0i); + wire_nlilOi0ll_dataout <= nlillOi0i AND NOT(niOiO1O0i); + wire_nlilOi0lO_dataout <= nlillOlii AND NOT(niOiO1O0i); + wire_nlilOi0O_dataout <= nliOi0ll WHEN niOO0111i = '1' ELSE nliOl1OO; + wire_nlilOi0Oi_dataout <= nlillOlil AND NOT(niOiO1O0i); + wire_nlilOi0Ol_dataout <= nlillOliO AND NOT(niOiO1O0i); + wire_nlilOi0OO_dataout <= nlillOlli AND NOT(niOiO1O0i); + wire_nlilOi10i_dataout <= nlilOilOO WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO00i; + wire_nlilOi10l_dataout <= nlilOiO1i WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO00l; + wire_nlilOi10O_dataout <= nlilOiO1l WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO00O; + wire_nlilOi11i_dataout <= nlilOillO WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO01i; + wire_nlilOi11l_dataout <= nlilOilOi WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO01l; + wire_nlilOi11O_dataout <= nlilOilOl WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO01O; + wire_nlilOi1i_dataout <= nliOi00O WHEN niOO0111i = '1' ELSE nliOl1li; + wire_nlilOi1ii_dataout <= nlilOiO1O WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0ii; + wire_nlilOi1il_dataout <= nlilOiO0i WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0il; + wire_nlilOi1iO_dataout <= nlilOiO0l WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0iO; + wire_nlilOi1l_dataout <= nliOi0ii WHEN niOO0111i = '1' ELSE nliOl1ll; + wire_nlilOi1li_dataout <= nlilOiO0O WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0li; + wire_nlilOi1ll_dataout <= nlilOiOii WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0ll; + wire_nlilOi1lO_dataout <= nlilOiOil WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0lO; + wire_nlilOi1O_dataout <= nliOi0il WHEN niOO0111i = '1' ELSE nliOl1lO; + wire_nlilOi1Oi_dataout <= nlilOiOiO WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0Oi; + wire_nlilOi1Ol_dataout <= nlilOiOli WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0Ol; + wire_nlilOi1OO_dataout <= nlilOiOll WHEN wire_nlOi1Oi1O_dataout = '1' ELSE nlillO0OO; + wire_nlilOii0i_dataout <= wire_nlilOO11O_dataout WHEN niOiO1O0i = '1' ELSE nlillOl1i; + wire_nlilOii0l_dataout <= wire_nlilOO10i_dataout WHEN niOiO1O0i = '1' ELSE nlillOl1l; + wire_nlilOii0O_dataout <= wire_nlilOO10l_dataout WHEN niOiO1O0i = '1' ELSE nlillOl1O; + wire_nlilOii1i_dataout <= nlillOlll AND NOT(niOiO1O0i); + wire_nlilOii1l_dataout <= nlillOllO OR niOiO1O0i; + wire_nlilOii1O_dataout <= nlillOlOi AND NOT(niOiO1O0i); + wire_nlilOiii_dataout <= nliOi0lO WHEN niOO0111i = '1' ELSE nliOl01i; + wire_nlilOiiii_dataout <= wire_nlilOllOi_dataout WHEN niOiO1O0i = '1' ELSE nlillOl0i; + wire_nlilOiiil_dataout <= wire_nlilOllOl_dataout WHEN niOiO1O0i = '1' ELSE nlillOl0l; + wire_nlilOiiiO_dataout <= wire_nlilOllOO_dataout WHEN niOiO1O0i = '1' ELSE nlillOl0O; + wire_nlilOiil_dataout <= nliOi0Oi WHEN niOO0111i = '1' ELSE nliOl01l; + wire_nlilOiili_dataout <= k_cnt(101) WHEN nlillOiOO = '1' ELSE wire_nlilOil1i_dataout; + wire_nlilOiill_dataout <= k_cnt(102) WHEN nlillOiOO = '1' ELSE wire_nlilOil1l_dataout; + wire_nlilOiilO_dataout <= k_cnt(103) WHEN nlillOiOO = '1' ELSE wire_nlilOil1O_dataout; + wire_nlilOiiO_dataout <= nliOi0Ol WHEN niOO0111i = '1' ELSE nliOl01O; + wire_nlilOiiOi_dataout <= k_cnt(104) WHEN nlillOiOO = '1' ELSE wire_nlilOil0i_dataout; + wire_nlilOiiOl_dataout <= k_cnt(105) WHEN nlillOiOO = '1' ELSE wire_nlilOil0l_dataout; + wire_nlilOiiOO_dataout <= k_cnt(106) WHEN nlillOiOO = '1' ELSE wire_nlilOil0O_dataout; + wire_nlilOil0i_dataout <= wire_nlilOilii_o(4) WHEN niOiO1O1i = '1' ELSE nlillOilO; + wire_nlilOil0l_dataout <= wire_nlilOilii_o(5) WHEN niOiO1O1i = '1' ELSE nlillOiOi; + wire_nlilOil0O_dataout <= wire_nlilOilii_o(6) WHEN niOiO1O1i = '1' ELSE nlillOiOl; + wire_nlilOil1i_dataout <= wire_nlilOilii_o(1) WHEN niOiO1O1i = '1' ELSE nlillOiiO; + wire_nlilOil1l_dataout <= wire_nlilOilii_o(2) WHEN niOiO1O1i = '1' ELSE nlillOili; + wire_nlilOil1O_dataout <= wire_nlilOilii_o(3) WHEN niOiO1O1i = '1' ELSE nlillOill; + wire_nlilOili_dataout <= nliOi0OO WHEN niOO0111i = '1' ELSE nliOl00i; + wire_nlilOill_dataout <= nliOii1i WHEN niOO0111i = '1' ELSE nliOl00l; + wire_nlilOilO_dataout <= nliOii1l WHEN niOO0111i = '1' ELSE nliOl00O; + wire_nlilOiOi_dataout <= nliOii1O WHEN niOO0111i = '1' ELSE nliOl0ii; + wire_nlilOiOl_dataout <= nliOii0i WHEN niOO0111i = '1' ELSE nliOl0il; + wire_nlilOiOO_dataout <= nliOii0l WHEN niOO0111i = '1' ELSE nliOl0iO; + wire_nlilOiOOO_dataout <= wire_nlilOl00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl00i_dataout <= wire_nlilOliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl00l_dataout <= wire_niilO1iO_dataout WHEN niOiO1O1O = '1' ELSE nlillOlOl; + wire_nlilOl00O_dataout <= wire_niilO1li_dataout WHEN niOiO1O1O = '1' ELSE nlilOilli; + wire_nlilOl01i_dataout <= wire_nlilOli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl01l_dataout <= wire_nlilOliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl01O_dataout <= wire_nlilOliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl0i_dataout <= nliOiiiO WHEN niOO0111i = '1' ELSE nliOl0Oi; + wire_nlilOl0ii_dataout <= wire_niilO1ll_dataout WHEN niOiO1O1O = '1' ELSE nlilOilll; + wire_nlilOl0il_dataout <= wire_niilO1lO_dataout WHEN niOiO1O1O = '1' ELSE nlilOillO; + wire_nlilOl0iO_dataout <= wire_niilO1Oi_dataout WHEN niOiO1O1O = '1' ELSE nlilOilOi; + wire_nlilOl0l_dataout <= nliOiili WHEN niOO0111i = '1' ELSE nliOl0Ol; + wire_nlilOl0li_dataout <= wire_niilO1Ol_dataout WHEN niOiO1O1O = '1' ELSE nlilOilOl; + wire_nlilOl0ll_dataout <= wire_niilO1OO_dataout WHEN niOiO1O1O = '1' ELSE nlilOilOO; + wire_nlilOl0lO_dataout <= wire_niilO01i_dataout WHEN niOiO1O1O = '1' ELSE nlilOiO1i; + wire_nlilOl0O_dataout <= nliOiill WHEN niOO0111i = '1' ELSE nliOl0OO; + wire_nlilOl0Oi_dataout <= wire_niilO01l_dataout WHEN niOiO1O1O = '1' ELSE nlilOiO1l; + wire_nlilOl0Ol_dataout <= wire_niilO01O_dataout WHEN niOiO1O1O = '1' ELSE nlilOiO1O; + wire_nlilOl0OO_dataout <= wire_niilO00i_dataout WHEN niOiO1O1O = '1' ELSE nlilOiO0i; + wire_nlilOl10i_dataout <= wire_nlilOl0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl10l_dataout <= wire_nlilOl0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl10O_dataout <= wire_nlilOl0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl11i_dataout <= wire_nlilOl00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl11l_dataout <= wire_nlilOl0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl11O_dataout <= wire_nlilOl0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1i_dataout <= nliOii0O WHEN niOO0111i = '1' ELSE nliOl0li; + wire_nlilOl1ii_dataout <= wire_nlilOl0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1il_dataout <= wire_nlilOl0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1iO_dataout <= wire_nlilOl0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1l_dataout <= nliOiiii WHEN niOO0111i = '1' ELSE nliOl0ll; + wire_nlilOl1li_dataout <= wire_nlilOl0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1ll_dataout <= wire_nlilOli1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1lO_dataout <= wire_nlilOli1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1O_dataout <= nliOiiil WHEN niOO0111i = '1' ELSE nliOl0lO; + wire_nlilOl1Oi_dataout <= wire_nlilOli1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1Ol_dataout <= wire_nlilOli0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOl1OO_dataout <= wire_nlilOli0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlilOli0i_dataout <= wire_niiOiO1l_dataout WHEN niOiO1O1O = '1' ELSE nlilOiOil; + wire_nlilOli0l_dataout <= wire_niiOiO1O_dataout WHEN niOiO1O1O = '1' ELSE nlilOiOiO; + wire_nlilOli0O_dataout <= wire_niiOiO0i_dataout WHEN niOiO1O1O = '1' ELSE nlilOiOli; + wire_nlilOli1i_dataout <= wire_niilO00l_dataout WHEN niOiO1O1O = '1' ELSE nlilOiO0l; + wire_nlilOli1l_dataout <= wire_niiOilOO_dataout WHEN niOiO1O1O = '1' ELSE nlilOiO0O; + wire_nlilOli1O_dataout <= wire_niiOiO1i_dataout WHEN niOiO1O1O = '1' ELSE nlilOiOii; + wire_nlilOlii_dataout <= nliOiilO WHEN niOO0111i = '1' ELSE nliOli1i; + wire_nlilOliii_dataout <= wire_niiOiO0l_dataout WHEN niOiO1O1O = '1' ELSE nlilOiOll; + wire_nlilOliil_dataout <= wire_niiOiO0O_dataout WHEN niOiO1O1O = '1' ELSE nlilOiOlO; + wire_nlilOliiO_dataout <= wire_niiOiOii_dataout WHEN niOiO1O1O = '1' ELSE nlilOiOOi; + wire_nlilOlil_dataout <= nliOiiOi WHEN niOO0111i = '1' ELSE nliOli1l; + wire_nlilOliO_dataout <= nliOiiOl WHEN niOO0111i = '1' ELSE nliOli1O; + wire_nlilOlli_dataout <= nliOiiOO WHEN niOO0111i = '1' ELSE nliOli0i; + wire_nlilOlll_dataout <= nliOil1i WHEN niOO0111i = '1' ELSE nliOli0l; + wire_nlilOllO_dataout <= nliOil1l WHEN niOO0111i = '1' ELSE nliOli0O; + wire_nlilOllOi_dataout <= wire_nlilOlO1i_dataout AND NOT(nlilOO0ll); + wire_nlilOllOl_dataout <= wire_nlilOlO1l_dataout AND NOT(nlilOO0ll); + wire_nlilOllOO_dataout <= wire_nlilOlO1O_dataout AND NOT(nlilOO0ll); + wire_nlilOlO0i_dataout <= wire_nlilOlOii_dataout AND NOT(niOiO1O0O); + wire_nlilOlO0l_dataout <= wire_nlilOlOil_dataout OR niOiO1O0O; + wire_nlilOlO0O_dataout <= wire_w_lg_niOiO1Oii42231w(0) AND NOT(niOiO1O0O); + wire_nlilOlO1i_dataout <= wire_nlilOlO0i_dataout OR niOiO1O0l; + wire_nlilOlO1l_dataout <= wire_nlilOlO0l_dataout AND NOT(niOiO1O0l); + wire_nlilOlO1O_dataout <= wire_nlilOlO0O_dataout AND NOT(niOiO1O0l); + wire_nlilOlOi_dataout <= nliOil1O WHEN niOO0111i = '1' ELSE nliOliii; + wire_nlilOlOii_dataout <= wire_nlilOlOiO_dataout OR niOiO1Oii; + wire_nlilOlOil_dataout <= wire_nlilOlOli_dataout OR niOiO1Oii; + wire_nlilOlOiO_dataout <= wire_nlilOlOll_dataout AND NOT(niOiO1Oil); + wire_nlilOlOl_dataout <= nliOil0i WHEN niOO0111i = '1' ELSE nliOliil; + wire_nlilOlOli_dataout <= wire_w_lg_niOiO1OiO42230w(0) AND NOT(niOiO1Oil); + wire_nlilOlOll_dataout <= wire_w_lg_niOiO1Oli42229w(0) OR niOiO1OiO; + wire_nlilOlOO_dataout <= nliOil0l WHEN niOO0111i = '1' ELSE nliOliiO; + wire_nlilOO00i_dataout <= wire_nilOOlll_dataout WHEN niOiO1OiO = '1' ELSE wire_nlilOO0ii_dataout; + wire_nlilOO00l_dataout <= wire_nilOOllO_dataout WHEN niOiO1OiO = '1' ELSE wire_nlilOO0il_dataout; + wire_nlilOO00O_dataout <= wire_nilOOlOi_dataout WHEN niOiO1Oli = '1' ELSE wire_nilOOO1i_dataout; + wire_nlilOO01i_dataout <= wire_nilOOlil_dataout WHEN niOiO1Oil = '1' ELSE wire_nlilOO00i_dataout; + wire_nlilOO01l_dataout <= wire_nilOOliO_dataout WHEN niOiO1Oil = '1' ELSE wire_nlilOO00l_dataout; + wire_nlilOO01O_dataout <= wire_nilOOlli_dataout WHEN niOiO1OiO = '1' ELSE wire_nlilOO00O_dataout; + wire_nlilOO0i_dataout <= wire_nlilOOlO_dataout OR niOO011OO; + wire_nlilOO0ii_dataout <= wire_nilOOlOl_dataout WHEN niOiO1Oli = '1' ELSE wire_nilOOO1l_dataout; + wire_nlilOO0il_dataout <= wire_nilOOlOO_dataout WHEN niOiO1Oli = '1' ELSE wire_nilOOO1O_dataout; + wire_nlilOO0l_dataout <= wire_nlilOOOi_dataout OR niOO011OO; + wire_nlilOO0O_dataout <= wire_nlilOOOl_dataout OR niOO011OO; + wire_nlilOO0Oi_dataout <= wire_nlilOOi1O_o AND NOT(wire_niO01O0O_dataout); + wire_nlilOO0Ol_dataout <= wire_nlilOOi0i_o AND NOT(wire_niO01O0O_dataout); + wire_nlilOO0OO_dataout <= wire_nlilOOi0l_o AND NOT(wire_niO01O0O_dataout); + wire_nlilOO10i_dataout <= wire_nlilOO1ii_dataout AND NOT(nlilOO0ll); + wire_nlilOO10l_dataout <= wire_nlilOO1il_dataout AND NOT(nlilOO0ll); + wire_nlilOO10O_dataout <= wire_nilOOiOi_dataout WHEN niOiO1O0l = '1' ELSE wire_nlilOO1iO_dataout; + wire_nlilOO11O_dataout <= wire_nlilOO10O_dataout AND NOT(nlilOO0ll); + wire_nlilOO1i_dataout <= nliOil0O WHEN niOO0111i = '1' ELSE nliOlili; + wire_nlilOO1ii_dataout <= wire_nilOOiOl_dataout WHEN niOiO1O0l = '1' ELSE wire_nlilOO1li_dataout; + wire_nlilOO1il_dataout <= wire_nilOOiOO_dataout WHEN niOiO1O0l = '1' ELSE wire_nlilOO1ll_dataout; + wire_nlilOO1iO_dataout <= wire_nilOOl1i_dataout WHEN niOiO1O0O = '1' ELSE wire_nlilOO1lO_dataout; + wire_nlilOO1l_dataout <= nliOilii WHEN niOO0111i = '1' ELSE nliOlill; + wire_nlilOO1li_dataout <= wire_nilOOl1l_dataout WHEN niOiO1O0O = '1' ELSE wire_nlilOO1Oi_dataout; + wire_nlilOO1ll_dataout <= wire_nilOOl1O_dataout WHEN niOiO1O0O = '1' ELSE wire_nlilOO1Ol_dataout; + wire_nlilOO1lO_dataout <= wire_nilOOl0i_dataout WHEN niOiO1Oii = '1' ELSE wire_nlilOO1OO_dataout; + wire_nlilOO1Oi_dataout <= wire_nilOOl0l_dataout WHEN niOiO1Oii = '1' ELSE wire_nlilOO01i_dataout; + wire_nlilOO1Ol_dataout <= wire_nilOOl0O_dataout WHEN niOiO1Oii = '1' ELSE wire_nlilOO01l_dataout; + wire_nlilOO1OO_dataout <= wire_nilOOlii_dataout WHEN niOiO1Oil = '1' ELSE wire_nlilOO01O_dataout; + wire_nlilOOi1i_dataout <= wire_nlilOOi0O_o AND NOT(wire_niO01O0O_dataout); + wire_nlilOOi1l_dataout <= wire_nlilOOiii_o OR wire_niO01O0O_dataout; + wire_nlilOOii_dataout <= wire_nlilOOOO_dataout OR niOO011OO; + wire_nlilOOiil_dataout <= nlilOiOOl AND NOT(wire_nlOii0Oll_w_lg_dataout42177w(0)); + wire_nlilOOiiO_dataout <= nlilOO0li AND NOT(wire_nlOii0Oll_w_lg_dataout42177w(0)); + wire_nlilOOil_dataout <= wire_nliO111i_dataout OR niOO011OO; + wire_nlilOOili_dataout <= nlilOO0ll AND NOT(wire_nlOii0Oll_w_lg_dataout42177w(0)); + wire_nlilOOill_dataout <= nlilOO0lO OR wire_nlOii0Oll_w_lg_dataout42177w(0); + wire_nlilOOilO_dataout <= nlilOO0iO OR niOiO1OOl; + wire_nlilOOiO_dataout <= wire_nliO111l_dataout OR niOO011OO; + wire_nlilOOiOi_dataout <= nlilOiOOl WHEN niOiO1Oll = '1' ELSE wire_nlilOOl1l_dataout; + wire_nlilOOiOl_dataout <= wire_nlilOOl1O_dataout AND NOT(niOiO1Oll); + wire_nlilOOiOO_dataout <= wire_nlilOOl0i_dataout AND NOT(niOiO1Oll); + wire_nlilOOl0i_dataout <= nlilOO0ll AND NOT(niOiO1OOi); + wire_nlilOOl0l_dataout <= nlilOO0lO AND NOT(niOiO1OOi); + wire_nlilOOl1i_dataout <= wire_nlilOOl0l_dataout OR niOiO1Oll; + wire_nlilOOl1l_dataout <= nlilOiOOl OR niOiO1OOi; + wire_nlilOOl1O_dataout <= nlilOO0li OR niOiO1OOi; + wire_nlilOOli_dataout <= wire_nliO111O_dataout OR niOO011OO; + wire_nlilOOlii_dataout <= nlilOO0li AND NOT(niOiO1OlO); + wire_nlilOOlil_dataout <= nlilOO0ll OR niOiO1OlO; + wire_nlilOOliO_dataout <= nlilOO0lO AND NOT(niOiO1OlO); + wire_nlilOOll_dataout <= wire_nliO110i_dataout OR niOO011OO; + wire_nlilOOlO_dataout <= wire_nliO110l_dataout OR niOO011Ol; + wire_nlilOOO0i_dataout <= wire_nlilOOOii_dataout OR nlillOllO; + wire_nlilOOO0l_dataout <= wire_nlilOOOil_dataout AND NOT(nlillOllO); + wire_nlilOOO0O_dataout <= wire_nlilOOOiO_dataout AND NOT(nlillOllO); + wire_nlilOOO1i_dataout <= wire_nlilOOO0i_dataout AND NOT(nlillOlOi); + wire_nlilOOO1l_dataout <= wire_nlilOOO0l_dataout AND NOT(nlillOlOi); + wire_nlilOOO1O_dataout <= wire_nlilOOO0O_dataout AND NOT(nlillOlOi); + wire_nlilOOOi_dataout <= wire_nliO110O_dataout OR niOO011Ol; + wire_nlilOOOii_dataout <= wire_nlilOOOli_dataout AND NOT(nlillOlll); + wire_nlilOOOil_dataout <= wire_nlilOOOll_dataout OR nlillOlll; + wire_nlilOOOiO_dataout <= wire_nl1000i_w_lg_nlillOlli42169w(0) AND NOT(nlillOlll); + wire_nlilOOOl_dataout <= wire_nliO11ii_dataout OR niOO011Ol; + wire_nlilOOOli_dataout <= wire_nlilOOOlO_dataout OR nlillOlli; + wire_nlilOOOll_dataout <= wire_nlilOOOOi_dataout OR nlillOlli; + wire_nlilOOOlO_dataout <= wire_nlilOOOOl_dataout AND NOT(nlillOliO); + wire_nlilOOOO_dataout <= wire_nliO11il_dataout OR niOO011Ol; + wire_nlilOOOOi_dataout <= wire_nl1000i_w_lg_nlillOlil42168w(0) AND NOT(nlillOliO); + wire_nlilOOOOl_dataout <= wire_nl1000i_w_lg_nlillOlii42167w(0) OR nlillOlil; + wire_nlilOOOOO_dataout <= wire_nliO1111l_dataout AND NOT(nlilOO0lO); + wire_nliO010i_dataout <= nliO0l0l OR NOT(niOO0111l); + wire_nliO010l_dataout <= nliO0l0O OR NOT(niOO0111l); + wire_nliO010O_dataout <= nliO0lii OR NOT(niOO0111l); + wire_nliO011i_dataout <= nl1il1iOO WHEN niOO0111O = '1' ELSE wire_nliO01iO_dataout; + wire_nliO011l_dataout <= nliO0l1O OR NOT(niOO0111l); + wire_nliO011O_dataout <= nliO0l0i OR NOT(niOO0111l); + wire_nliO01ii_dataout <= nliO0lil OR NOT(niOO0111l); + wire_nliO01il_dataout <= nliO0liO OR NOT(niOO0111l); + wire_nliO01iO_dataout <= nliO0lli OR NOT(niOO0111l); + wire_nliO100i_dataout <= nl1il1iOl WHEN niOO011Oi = '1' ELSE wire_nliO10lO_dataout; + wire_nliO100l_dataout <= nl1il1iOO WHEN niOO011Oi = '1' ELSE wire_nliO10Oi_dataout; + wire_nliO100O_dataout <= nliO0l1O WHEN niOO011ll = '1' ELSE wire_nliO10Ol_dataout; + wire_nliO101i_dataout <= wire_nliO10iO_dataout OR niOO011Oi; + wire_nliO101l_dataout <= nl1il1ilO WHEN niOO011Oi = '1' ELSE wire_nliO10li_dataout; + wire_nliO101O_dataout <= nl1il1iOi WHEN niOO011Oi = '1' ELSE wire_nliO10ll_dataout; + wire_nliO10ii_dataout <= nliO0l0i WHEN niOO011ll = '1' ELSE wire_nliO10OO_dataout; + wire_nliO10il_dataout <= nliO0l0l WHEN niOO011ll = '1' ELSE wire_nliO1i1i_dataout; + wire_nliO10iO_dataout <= nliO0l0O WHEN niOO011ll = '1' ELSE wire_nliO1i1l_dataout; + wire_nliO10li_dataout <= nliO0lii WHEN niOO011ll = '1' ELSE wire_nliO1i1O_dataout; + wire_nliO10ll_dataout <= nliO0lil WHEN niOO011ll = '1' ELSE wire_nliO1i0i_dataout; + wire_nliO10lO_dataout <= nliO0liO WHEN niOO011ll = '1' ELSE wire_nliO1i0l_dataout; + wire_nliO10Oi_dataout <= nliO0lli WHEN niOO011ll = '1' ELSE wire_nliO1i0O_dataout; + wire_nliO10Ol_dataout <= wire_nliO1iii_dataout AND NOT(niOO011iO); + wire_nliO10OO_dataout <= wire_nliO1iil_dataout AND NOT(niOO011iO); + wire_nliO110i_dataout <= wire_nliO11lO_dataout OR niOO011Ol; + wire_nliO110l_dataout <= wire_nliO11Oi_dataout OR niOO011lO; + wire_nliO110O_dataout <= wire_nliO11Ol_dataout OR niOO011lO; + wire_nliO1111i_dataout <= wire_nl1000i_w_lg_nlilOO0ll42166w(0) AND NOT(nlilOO0lO); + wire_nliO1111l_dataout <= wire_nl1000i_w_lg_nlilOO0li42165w(0) OR nlilOO0ll; + wire_nliO111i_dataout <= wire_nliO11iO_dataout OR niOO011Ol; + wire_nliO111l_dataout <= wire_nliO11li_dataout OR niOO011Ol; + wire_nliO111O_dataout <= wire_nliO11ll_dataout OR niOO011Ol; + wire_nliO11ii_dataout <= wire_nliO11OO_dataout OR niOO011lO; + wire_nliO11il_dataout <= wire_nliO101i_dataout OR niOO011lO; + wire_nliO11iO_dataout <= wire_nliO101l_dataout AND NOT(niOO011lO); + wire_nliO11li_dataout <= wire_nliO101O_dataout AND NOT(niOO011lO); + wire_nliO11ll_dataout <= wire_nliO100i_dataout AND NOT(niOO011lO); + wire_nliO11lO_dataout <= wire_nliO100l_dataout AND NOT(niOO011lO); + wire_nliO11Oi_dataout <= wire_nliO100O_dataout OR niOO011Oi; + wire_nliO11Ol_dataout <= wire_nliO10ii_dataout OR niOO011Oi; + wire_nliO11OO_dataout <= wire_nliO10il_dataout OR niOO011Oi; + wire_nliO1i0i_dataout <= wire_nliO1ilO_dataout OR niOO011iO; + wire_nliO1i0l_dataout <= wire_nliO1iOi_dataout OR niOO011iO; + wire_nliO1i0O_dataout <= wire_nliO1iOl_dataout OR niOO011iO; + wire_nliO1i1i_dataout <= wire_nliO1iiO_dataout AND NOT(niOO011iO); + wire_nliO1i1l_dataout <= wire_nliO1ili_dataout AND NOT(niOO011iO); + wire_nliO1i1O_dataout <= wire_nliO1ill_dataout OR niOO011iO; + wire_nliO1iii_dataout <= wire_nliO1iOO_dataout OR niOO011il; + wire_nliO1iil_dataout <= wire_nliO1l1i_dataout OR niOO011il; + wire_nliO1iiO_dataout <= wire_nliO1l1l_dataout OR niOO011il; + wire_nliO1ili_dataout <= wire_nliO1l1O_dataout OR niOO011il; + wire_nliO1ill_dataout <= wire_nliO1l0i_dataout AND NOT(niOO011il); + wire_nliO1ilO_dataout <= wire_nliO1l0l_dataout AND NOT(niOO011il); + wire_nliO1iOi_dataout <= wire_nliO1l0O_dataout AND NOT(niOO011il); + wire_nliO1iOl_dataout <= wire_nliO1lii_dataout AND NOT(niOO011il); + wire_nliO1iOO_dataout <= nliO0iiO WHEN niOO0110O = '1' ELSE wire_nliO1lil_dataout; + wire_nliO1l0i_dataout <= nliO0iOi WHEN niOO0110O = '1' ELSE wire_nliO1llO_dataout; + wire_nliO1l0l_dataout <= nliO0iOl WHEN niOO0110O = '1' ELSE wire_nliO1lOi_dataout; + wire_nliO1l0O_dataout <= nliO0iOO WHEN niOO0110O = '1' ELSE wire_nliO1lOl_dataout; + wire_nliO1l1i_dataout <= nliO0ili WHEN niOO0110O = '1' ELSE wire_nliO1liO_dataout; + wire_nliO1l1l_dataout <= nliO0ill WHEN niOO0110O = '1' ELSE wire_nliO1lli_dataout; + wire_nliO1l1O_dataout <= nliO0ilO WHEN niOO0110O = '1' ELSE wire_nliO1lll_dataout; + wire_nliO1lii_dataout <= nliO0l1i WHEN niOO0110O = '1' ELSE wire_nliO1lOO_dataout; + wire_nliO1lil_dataout <= nl1il1iil WHEN niOO011ii = '1' ELSE wire_nliO1O1i_dataout; + wire_nliO1liO_dataout <= nl1il1iiO WHEN niOO011ii = '1' ELSE wire_nliO1O1l_dataout; + wire_nliO1lli_dataout <= nl1il1ili WHEN niOO011ii = '1' ELSE wire_nliO1O1O_dataout; + wire_nliO1lll_dataout <= nl1il1ill WHEN niOO011ii = '1' ELSE wire_nliO1O0i_dataout; + wire_nliO1llO_dataout <= nl1il1ilO WHEN niOO011ii = '1' ELSE wire_nliO1O0l_dataout; + wire_nliO1lOi_dataout <= nl1il1iOi WHEN niOO011ii = '1' ELSE wire_nliO1O0O_dataout; + wire_nliO1lOl_dataout <= nl1il1iOl WHEN niOO011ii = '1' ELSE wire_nliO1Oii_dataout; + wire_nliO1lOO_dataout <= nl1il1iOO WHEN niOO011ii = '1' ELSE wire_nliO1Oil_dataout; + wire_nliO1O0i_dataout <= nliO0l0O WHEN niOO0110i = '1' ELSE wire_nliO1OlO_dataout; + wire_nliO1O0l_dataout <= nliO0lii WHEN niOO0110i = '1' ELSE wire_nliO1OOi_dataout; + wire_nliO1O0O_dataout <= nliO0lil WHEN niOO0110i = '1' ELSE wire_nliO1OOl_dataout; + wire_nliO1O1i_dataout <= nliO0l1O WHEN niOO0110i = '1' ELSE wire_nliO1OiO_dataout; + wire_nliO1O1l_dataout <= nliO0l0i WHEN niOO0110i = '1' ELSE wire_nliO1Oli_dataout; + wire_nliO1O1O_dataout <= nliO0l0l WHEN niOO0110i = '1' ELSE wire_nliO1Oll_dataout; + wire_nliO1Oii_dataout <= nliO0liO WHEN niOO0110i = '1' ELSE wire_nliO1OOO_dataout; + wire_nliO1Oil_dataout <= nliO0lli WHEN niOO0110i = '1' ELSE wire_nliO011i_dataout; + wire_nliO1OiO_dataout <= nl1il1iil WHEN niOO0111O = '1' ELSE wire_nliO011l_dataout; + wire_nliO1Oli_dataout <= nl1il1iiO WHEN niOO0111O = '1' ELSE wire_nliO011O_dataout; + wire_nliO1Oll_dataout <= nl1il1ili WHEN niOO0111O = '1' ELSE wire_nliO010i_dataout; + wire_nliO1OlO_dataout <= nl1il1ill WHEN niOO0111O = '1' ELSE wire_nliO010l_dataout; + wire_nliO1OOi_dataout <= nl1il1ilO WHEN niOO0111O = '1' ELSE wire_nliO010O_dataout; + wire_nliO1OOl_dataout <= nl1il1iOi WHEN niOO0111O = '1' ELSE wire_nliO01ii_dataout; + wire_nliO1OOO_dataout <= nl1il1iOl WHEN niOO0111O = '1' ELSE wire_nliO01il_dataout; + wire_nliOliOi_dataout <= wire_nll1ilOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOliOl_dataout <= wire_nll11l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOliOO_dataout <= wire_nll11lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOll0i_dataout <= wire_nll1il0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOll0l_dataout <= wire_nll1ilii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOll0O_dataout <= wire_nll1ilil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOll1i_dataout <= wire_nll11lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOll1l_dataout <= wire_nll1il0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOll1O_dataout <= wire_nll1il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOllii_dataout <= wire_nll1iliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOllil_dataout <= wire_nll1illi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlliO_dataout <= wire_nll1illl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOllli_dataout <= wire_nll1illO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOllll_dataout <= wire_nll11liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlllO_dataout <= wire_nll1iill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOllOi_dataout <= wire_nll1iilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOllOl_dataout <= wire_nll1iiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOllOO_dataout <= wire_nll1iiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlO0i_dataout <= wire_nll1il1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlO0l_dataout <= wire_nll1ii1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlO0O_dataout <= wire_nll1ii0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlO1i_dataout <= wire_nll1iiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlO1l_dataout <= wire_nll1il1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlO1O_dataout <= wire_nll1il1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOii_dataout <= wire_nll1ii0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOil_dataout <= wire_nll1ii0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOiO_dataout <= wire_nll1iiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOli_dataout <= wire_nll1iiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOll_dataout <= wire_nll1iiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOlO_dataout <= wire_nll1iili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOOi_dataout <= wire_nll10iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOOl_dataout <= wire_nll10iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOlOOO_dataout <= wire_nll10l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO00i_dataout <= wire_nll10O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO00l_dataout <= wire_nll10O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO00O_dataout <= wire_nll10Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO01i_dataout <= wire_nll10O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO01l_dataout <= wire_nll10O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO01O_dataout <= wire_nll10O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0ii_dataout <= wire_nll10Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0il_dataout <= wire_nll10OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0iO_dataout <= wire_nll10Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0li_dataout <= wire_nll10Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0ll_dataout <= wire_nll10OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0lO_dataout <= wire_nll10OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0Oi_dataout <= wire_nll10OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0Ol_dataout <= wire_nll10OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO0OO_dataout <= wire_nll1i11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO10i_dataout <= wire_nll10l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO10l_dataout <= wire_nll10l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO10O_dataout <= wire_nll10lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO11i_dataout <= wire_nll10l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO11l_dataout <= wire_nll10l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO11O_dataout <= wire_nll10l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1ii_dataout <= wire_nll10lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1il_dataout <= wire_nll10liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1iO_dataout <= wire_nll10lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1li_dataout <= wire_nll10lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1ll_dataout <= wire_nll10llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1lO_dataout <= wire_nll10lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1Oi_dataout <= wire_nll10lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1Ol_dataout <= wire_nll10lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOO1OO_dataout <= wire_nll10O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOi0i_dataout <= wire_nll1i10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOi0l_dataout <= wire_nll1i10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOi0O_dataout <= wire_nll1i1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOi1i_dataout <= wire_nll1i11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOi1l_dataout <= wire_nll1i11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOi1O_dataout <= wire_nll1i10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOiii_dataout <= wire_nll1i1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOiil_dataout <= wire_nll1i1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOiiO_dataout <= wire_nll1i1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOili_dataout <= wire_nll1i1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOill_dataout <= wire_nll1i1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOilO_dataout <= wire_nll1i1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOiOi_dataout <= wire_nll1i1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOiOl_dataout <= wire_nll1i1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOiOO_dataout <= wire_nll1i01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOl0i_dataout <= wire_nll1i00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOl0l_dataout <= wire_nll1i00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOl0O_dataout <= wire_nll1i0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOl1i_dataout <= wire_nll1i01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOl1l_dataout <= wire_nll1i01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOl1O_dataout <= wire_nll1i00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOlii_dataout <= wire_nll1i0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOlil_dataout <= wire_nll1i0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOliO_dataout <= wire_nll1i0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOlli_dataout <= wire_nll1i0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOlll_dataout <= wire_nll1i0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOllO_dataout <= wire_nll1i0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOlOi_dataout <= wire_nll1i0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOlOl_dataout <= wire_nll1i0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOlOO_dataout <= wire_nll1ii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOO0i_dataout <= wire_nll11llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOO0l_dataout <= wire_nll11lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOO0O_dataout <= wire_nll11lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOO1i_dataout <= wire_nll1ii1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOO1l_dataout <= wire_nll11lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOO1O_dataout <= wire_nll11lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOii_dataout <= wire_nll11lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOil_dataout <= wire_nll11O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOiO_dataout <= wire_nll11O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOli_dataout <= wire_nll11O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOll_dataout <= wire_nll11O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOlO_dataout <= wire_nll11O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOOi_dataout <= wire_nll11O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOOl_dataout <= wire_nll11Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nliOOOOO_dataout <= wire_nll11Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0000i_dataout <= wire_nll0iili_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1il_dataout; + wire_nll0000l_dataout <= wire_nll0iill_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1iO_dataout; + wire_nll0000O_dataout <= wire_nll0iilO_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1li_dataout; + wire_nll0001i_dataout <= wire_nll0iiii_dataout WHEN nlliO01i = '1' ELSE wire_nll0i10l_dataout; + wire_nll0001l_dataout <= wire_nll0iiil_dataout WHEN nlliO01i = '1' ELSE wire_nll0i10O_dataout; + wire_nll0001O_dataout <= wire_nll0iiiO_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1ii_dataout; + wire_nll000ii_dataout <= wire_nll0iiOi_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1ll_dataout; + wire_nll000il_dataout <= wire_nll0iiOl_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1lO_dataout; + wire_nll000iO_dataout <= wire_nll0iiOO_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1Oi_dataout; + wire_nll000li_dataout <= wire_nll0il1i_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1Ol_dataout; + wire_nll000ll_dataout <= wire_nll0il1l_dataout WHEN nlliO01i = '1' ELSE wire_nll0i1OO_dataout; + wire_nll000lO_dataout <= wire_nll0il1O_dataout WHEN nlliO01i = '1' ELSE wire_nll0i01i_dataout; + wire_nll000Oi_dataout <= wire_nll0il0i_dataout WHEN nlliO01i = '1' ELSE wire_nll0i01l_dataout; + wire_nll000Ol_dataout <= wire_nl1iliilO_dataout WHEN nlliO1OO = '1' ELSE nliOilil; + wire_nll000OO_dataout <= wire_nl1iliiOi_dataout WHEN nlliO1OO = '1' ELSE nliOiliO; + wire_nll0010i_dataout <= wire_nll0i0li_dataout WHEN nlliO01i = '1' ELSE wire_nll00Oil_dataout; + wire_nll0010l_dataout <= wire_nll0i0ll_dataout WHEN nlliO01i = '1' ELSE wire_nll00OiO_dataout; + wire_nll0010O_dataout <= wire_nll0i0lO_dataout WHEN nlliO01i = '1' ELSE wire_nll00Oli_dataout; + wire_nll0011i_dataout <= wire_nll0i0ii_dataout WHEN nlliO01i = '1' ELSE wire_nll00O0l_dataout; + wire_nll0011l_dataout <= wire_nll0i0il_dataout WHEN nlliO01i = '1' ELSE wire_nll00O0O_dataout; + wire_nll0011O_dataout <= wire_nll0i0iO_dataout WHEN nlliO01i = '1' ELSE wire_nll00Oii_dataout; + wire_nll001ii_dataout <= wire_nll0i0Oi_dataout WHEN nlliO01i = '1' ELSE wire_nll00Oll_dataout; + wire_nll001il_dataout <= wire_nll0i0Ol_dataout WHEN nlliO01i = '1' ELSE wire_nll00OlO_dataout; + wire_nll001iO_dataout <= wire_nll0i0OO_dataout WHEN nlliO01i = '1' ELSE wire_nll00OOi_dataout; + wire_nll001li_dataout <= wire_nll0ii1i_dataout WHEN nlliO01i = '1' ELSE wire_nll00OOl_dataout; + wire_nll001ll_dataout <= wire_nll0ii1l_dataout WHEN nlliO01i = '1' ELSE wire_nll00OOO_dataout; + wire_nll001lO_dataout <= wire_nll0ii1O_dataout WHEN nlliO01i = '1' ELSE wire_nll0i11i_dataout; + wire_nll001Oi_dataout <= wire_nll0ii0i_dataout WHEN nlliO01i = '1' ELSE wire_nll0i11l_dataout; + wire_nll001Ol_dataout <= wire_nll0ii0l_dataout WHEN nlliO01i = '1' ELSE wire_nll0i11O_dataout; + wire_nll001OO_dataout <= wire_nll0ii0O_dataout WHEN nlliO01i = '1' ELSE wire_nll0i10i_dataout; + wire_nll00i0i_dataout <= wire_nl1ilil1l_dataout WHEN nlliO1OO = '1' ELSE nliOilOi; + wire_nll00i0l_dataout <= wire_nl1ilil1O_dataout WHEN nlliO1OO = '1' ELSE nliOilOl; + wire_nll00i0O_dataout <= wire_nl1ilil0i_dataout WHEN nlliO1OO = '1' ELSE nliOilOO; + wire_nll00i1i_dataout <= wire_nl1iliiOl_dataout WHEN nlliO1OO = '1' ELSE nliOilli; + wire_nll00i1l_dataout <= wire_nl1iliiOO_dataout WHEN nlliO1OO = '1' ELSE nliOilll; + wire_nll00i1O_dataout <= wire_nl1ilil1i_dataout WHEN nlliO1OO = '1' ELSE nliOillO; + wire_nll00iii_dataout <= wire_nl1ilil0l_dataout WHEN nlliO1OO = '1' ELSE nliOiO1i; + wire_nll00iil_dataout <= wire_nl1ilil0O_dataout WHEN nlliO1OO = '1' ELSE nliOiO1l; + wire_nll00iiO_dataout <= wire_nl1ililii_dataout WHEN nlliO1OO = '1' ELSE nliOiO1O; + wire_nll00ili_dataout <= wire_nl1ililil_dataout WHEN nlliO1OO = '1' ELSE nliOiO0i; + wire_nll00ill_dataout <= wire_nl1ililiO_dataout WHEN nlliO1OO = '1' ELSE nliOiO0l; + wire_nll00ilO_dataout <= wire_nl1ililli_dataout WHEN nlliO1OO = '1' ELSE nliOiO0O; + wire_nll00iOi_dataout <= wire_nl1ililll_dataout WHEN nlliO1OO = '1' ELSE nliOiOii; + wire_nll00iOl_dataout <= wire_nl1ilillO_dataout WHEN nlliO1OO = '1' ELSE nliOiOil; + wire_nll00iOO_dataout <= wire_nl1ililOi_dataout WHEN nlliO1OO = '1' ELSE nliOiOiO; + wire_nll00l0i_dataout <= wire_nl1iliO1l_dataout WHEN nlliO1OO = '1' ELSE nliOiOOi; + wire_nll00l0l_dataout <= wire_nl1iliO1O_dataout WHEN nlliO1OO = '1' ELSE nliOiOOl; + wire_nll00l0O_dataout <= wire_nl1iliO0i_dataout WHEN nlliO1OO = '1' ELSE nliOiOOO; + wire_nll00l1i_dataout <= wire_nl1ililOl_dataout WHEN nlliO1OO = '1' ELSE nliOiOli; + wire_nll00l1l_dataout <= wire_nl1ililOO_dataout WHEN nlliO1OO = '1' ELSE nliOiOll; + wire_nll00l1O_dataout <= wire_nl1iliO1i_dataout WHEN nlliO1OO = '1' ELSE nliOiOlO; + wire_nll00lii_dataout <= wire_nl1iliO0l_dataout WHEN nlliO1OO = '1' ELSE nliOl11i; + wire_nll00lil_dataout <= wire_nl1iliO0O_dataout WHEN nlliO1OO = '1' ELSE nliOl11l; + wire_nll00liO_dataout <= wire_nl1iliOii_dataout WHEN nlliO1OO = '1' ELSE nliOl11O; + wire_nll00lli_dataout <= wire_nl1iliOil_dataout WHEN nlliO1OO = '1' ELSE nliOl10i; + wire_nll00lll_dataout <= wire_nl1iliOiO_dataout WHEN nlliO1OO = '1' ELSE nliOl10l; + wire_nll00llO_dataout <= wire_nl1iliOli_dataout WHEN nlliO1OO = '1' ELSE nliOl10O; + wire_nll00lOi_dataout <= wire_nl1iliOll_dataout WHEN nlliO1OO = '1' ELSE nliOl1ii; + wire_nll00lOl_dataout <= wire_nl1iliOlO_dataout WHEN nlliO1OO = '1' ELSE nliOl1il; + wire_nll00lOO_dataout <= wire_nl1iliOOi_dataout WHEN nlliO1OO = '1' ELSE nliOl1iO; + wire_nll00O0i_dataout <= wire_nl1ill11l_dataout WHEN nlliO1OO = '1' ELSE nliOl1Oi; + wire_nll00O0l_dataout <= wire_nl1ill11O_dataout WHEN nlliO1OO = '1' ELSE nliOl1Ol; + wire_nll00O0O_dataout <= wire_nl1ill10i_dataout WHEN nlliO1OO = '1' ELSE nliOl1OO; + wire_nll00O1i_dataout <= wire_nl1iliOOl_dataout WHEN nlliO1OO = '1' ELSE nliOl1li; + wire_nll00O1l_dataout <= wire_nl1iliOOO_dataout WHEN nlliO1OO = '1' ELSE nliOl1ll; + wire_nll00O1O_dataout <= wire_nl1ill11i_dataout WHEN nlliO1OO = '1' ELSE nliOl1lO; + wire_nll00Oii_dataout <= wire_nl1ill10l_dataout WHEN nlliO1OO = '1' ELSE nliOl01i; + wire_nll00Oil_dataout <= wire_nl1ill10O_dataout WHEN nlliO1OO = '1' ELSE nliOl01l; + wire_nll00OiO_dataout <= wire_nl1ill1ii_dataout WHEN nlliO1OO = '1' ELSE nliOl01O; + wire_nll00Oli_dataout <= wire_nl1ill1il_dataout WHEN nlliO1OO = '1' ELSE nliOl00i; + wire_nll00Oll_dataout <= wire_nl1ill1iO_dataout WHEN nlliO1OO = '1' ELSE nliOl00l; + wire_nll00OlO_dataout <= wire_nl1ill1li_dataout WHEN nlliO1OO = '1' ELSE nliOl00O; + wire_nll00OOi_dataout <= wire_nl1ill1ll_dataout WHEN nlliO1OO = '1' ELSE nliOl0ii; + wire_nll00OOl_dataout <= wire_nl1ill1lO_dataout WHEN nlliO1OO = '1' ELSE nliOl0il; + wire_nll00OOO_dataout <= wire_nl1ill1Oi_dataout WHEN nlliO1OO = '1' ELSE nliOl0iO; + wire_nll0100i_dataout <= wire_nl1lOO1Ol_dataout WHEN nlliO01l = '1' ELSE wire_nll001il_dataout; + wire_nll0100l_dataout <= wire_nl1lOO1OO_dataout WHEN nlliO01l = '1' ELSE wire_nll001iO_dataout; + wire_nll0100O_dataout <= wire_nl1lOO01i_dataout WHEN nlliO01l = '1' ELSE wire_nll001li_dataout; + wire_nll0101i_dataout <= wire_nl1lOO1ll_dataout WHEN nlliO01l = '1' ELSE wire_nll0010l_dataout; + wire_nll0101l_dataout <= wire_nl1lOO1lO_dataout WHEN nlliO01l = '1' ELSE wire_nll0010O_dataout; + wire_nll0101O_dataout <= wire_nl1lOO1Oi_dataout WHEN nlliO01l = '1' ELSE wire_nll001ii_dataout; + wire_nll010ii_dataout <= wire_nl1lOO01l_dataout WHEN nlliO01l = '1' ELSE wire_nll001ll_dataout; + wire_nll010il_dataout <= wire_nl1lOO01O_dataout WHEN nlliO01l = '1' ELSE wire_nll001lO_dataout; + wire_nll010iO_dataout <= wire_nl1lOO00i_dataout WHEN nlliO01l = '1' ELSE wire_nll001Oi_dataout; + wire_nll010li_dataout <= wire_nl1lOO00l_dataout WHEN nlliO01l = '1' ELSE wire_nll001Ol_dataout; + wire_nll010ll_dataout <= wire_nl1lOO00O_dataout WHEN nlliO01l = '1' ELSE wire_nll001OO_dataout; + wire_nll010lO_dataout <= wire_nl1lOO0ii_dataout WHEN nlliO01l = '1' ELSE wire_nll0001i_dataout; + wire_nll010Oi_dataout <= wire_nl1lOO0il_dataout WHEN nlliO01l = '1' ELSE wire_nll0001l_dataout; + wire_nll010Ol_dataout <= wire_nl1lOO0iO_dataout WHEN nlliO01l = '1' ELSE wire_nll0001O_dataout; + wire_nll010OO_dataout <= wire_nl1lOO0li_dataout WHEN nlliO01l = '1' ELSE wire_nll0000i_dataout; + wire_nll0110i_dataout <= wire_nl1lOOO1O_dataout WHEN nlliO01l = '1' ELSE wire_nll01Oil_dataout; + wire_nll0110l_dataout <= wire_nl1lOOO0i_dataout WHEN nlliO01l = '1' ELSE wire_nll01OiO_dataout; + wire_nll0110O_dataout <= wire_nl1lOOO0l_dataout WHEN nlliO01l = '1' ELSE wire_nll01Oli_dataout; + wire_nll0111i_dataout <= wire_nl1lOOlOO_dataout WHEN nlliO01l = '1' ELSE wire_nll01O0l_dataout; + wire_nll0111l_dataout <= wire_nl1lOOO1i_dataout WHEN nlliO01l = '1' ELSE wire_nll01O0O_dataout; + wire_nll0111O_dataout <= wire_nl1lOOO1l_dataout WHEN nlliO01l = '1' ELSE wire_nll01Oii_dataout; + wire_nll011ii_dataout <= (nl1lO1iiO OR nl1ll0lOO) WHEN nlliO01l = '1' ELSE wire_nll01Oll_dataout; + wire_nll011il_dataout <= wire_nl1lOO11O_dataout WHEN nlliO01l = '1' ELSE wire_nll01OlO_dataout; + wire_nll011iO_dataout <= wire_nl1lOO10i_dataout WHEN nlliO01l = '1' ELSE wire_nll01OOi_dataout; + wire_nll011li_dataout <= wire_nl1lOO10l_dataout WHEN nlliO01l = '1' ELSE wire_nll01OOl_dataout; + wire_nll011ll_dataout <= wire_nl1lOO10O_dataout WHEN nlliO01l = '1' ELSE wire_nll01OOO_dataout; + wire_nll011lO_dataout <= wire_nl1lOO1ii_dataout WHEN nlliO01l = '1' ELSE wire_nll0011i_dataout; + wire_nll011Oi_dataout <= wire_nl1lOO1il_dataout WHEN nlliO01l = '1' ELSE wire_nll0011l_dataout; + wire_nll011Ol_dataout <= wire_nl1lOO1iO_dataout WHEN nlliO01l = '1' ELSE wire_nll0011O_dataout; + wire_nll011OO_dataout <= wire_nl1lOO1li_dataout WHEN nlliO01l = '1' ELSE wire_nll0010i_dataout; + wire_nll01i0i_dataout <= wire_nl1lOO0Ol_dataout WHEN nlliO01l = '1' ELSE wire_nll000il_dataout; + wire_nll01i0l_dataout <= wire_nl1lOO0OO_dataout WHEN nlliO01l = '1' ELSE wire_nll000iO_dataout; + wire_nll01i0O_dataout <= wire_nl1lOOi1i_dataout WHEN nlliO01l = '1' ELSE wire_nll000li_dataout; + wire_nll01i1i_dataout <= wire_nl1lOO0ll_dataout WHEN nlliO01l = '1' ELSE wire_nll0000l_dataout; + wire_nll01i1l_dataout <= wire_nl1lOO0lO_dataout WHEN nlliO01l = '1' ELSE wire_nll0000O_dataout; + wire_nll01i1O_dataout <= wire_nl1lOO0Oi_dataout WHEN nlliO01l = '1' ELSE wire_nll000ii_dataout; + wire_nll01iii_dataout <= wire_nl1lOOi1l_dataout WHEN nlliO01l = '1' ELSE wire_nll000ll_dataout; + wire_nll01iil_dataout <= wire_nl1lOOi1O_dataout WHEN nlliO01l = '1' ELSE wire_nll000lO_dataout; + wire_nll01iiO_dataout <= wire_nl1lOOi0i_dataout WHEN nlliO01l = '1' ELSE wire_nll000Oi_dataout; + wire_nll01ili_dataout <= wire_nl1lO010i_dataout WHEN nlliO01i = '1' ELSE wire_nll000Ol_dataout; + wire_nll01ill_dataout <= wire_nl1lO010l_dataout WHEN nlliO01i = '1' ELSE wire_nll000OO_dataout; + wire_nll01ilO_dataout <= wire_nl1lO010O_dataout WHEN nlliO01i = '1' ELSE wire_nll00i1i_dataout; + wire_nll01iOi_dataout <= wire_nl1lO01ii_dataout WHEN nlliO01i = '1' ELSE wire_nll00i1l_dataout; + wire_nll01iOl_dataout <= wire_nl1lO01il_dataout WHEN nlliO01i = '1' ELSE wire_nll00i1O_dataout; + wire_nll01iOO_dataout <= wire_nl1lO01iO_dataout WHEN nlliO01i = '1' ELSE wire_nll00i0i_dataout; + wire_nll01l0i_dataout <= wire_nl1lO01Oi_dataout WHEN nlliO01i = '1' ELSE wire_nll00iil_dataout; + wire_nll01l0l_dataout <= wire_nl1lO01Ol_dataout WHEN nlliO01i = '1' ELSE wire_nll00iiO_dataout; + wire_nll01l0O_dataout <= wire_nl1lO01OO_dataout WHEN nlliO01i = '1' ELSE wire_nll00ili_dataout; + wire_nll01l1i_dataout <= wire_nl1lO01li_dataout WHEN nlliO01i = '1' ELSE wire_nll00i0l_dataout; + wire_nll01l1l_dataout <= wire_nl1lO01ll_dataout WHEN nlliO01i = '1' ELSE wire_nll00i0O_dataout; + wire_nll01l1O_dataout <= wire_nl1lO01lO_dataout WHEN nlliO01i = '1' ELSE wire_nll00iii_dataout; + wire_nll01lii_dataout <= wire_nl1lO001i_dataout WHEN nlliO01i = '1' ELSE wire_nll00ill_dataout; + wire_nll01lil_dataout <= wire_nl1lO001l_dataout WHEN nlliO01i = '1' ELSE wire_nll00ilO_dataout; + wire_nll01liO_dataout <= wire_nl1lO001O_dataout WHEN nlliO01i = '1' ELSE wire_nll00iOi_dataout; + wire_nll01lli_dataout <= wire_nl1lO000i_dataout WHEN nlliO01i = '1' ELSE wire_nll00iOl_dataout; + wire_nll01lll_dataout <= wire_nl1lO000l_dataout WHEN nlliO01i = '1' ELSE wire_nll00iOO_dataout; + wire_nll01llO_dataout <= wire_nl1lO000O_dataout WHEN nlliO01i = '1' ELSE wire_nll00l1i_dataout; + wire_nll01lOi_dataout <= wire_nl1lO00ii_dataout WHEN nlliO01i = '1' ELSE wire_nll00l1l_dataout; + wire_nll01lOl_dataout <= wire_nl1lO00il_dataout WHEN nlliO01i = '1' ELSE wire_nll00l1O_dataout; + wire_nll01lOO_dataout <= wire_nl1lO00iO_dataout WHEN nlliO01i = '1' ELSE wire_nll00l0i_dataout; + wire_nll01O0i_dataout <= wire_nl1lO00Oi_dataout WHEN nlliO01i = '1' ELSE wire_nll00lil_dataout; + wire_nll01O0l_dataout <= wire_nl1lO00Ol_dataout WHEN nlliO01i = '1' ELSE wire_nll00liO_dataout; + wire_nll01O0O_dataout <= wire_nl1lO00OO_dataout WHEN nlliO01i = '1' ELSE wire_nll00lli_dataout; + wire_nll01O1i_dataout <= wire_nl1lO00li_dataout WHEN nlliO01i = '1' ELSE wire_nll00l0l_dataout; + wire_nll01O1l_dataout <= wire_nl1lO00ll_dataout WHEN nlliO01i = '1' ELSE wire_nll00l0O_dataout; + wire_nll01O1O_dataout <= wire_nl1lO00lO_dataout WHEN nlliO01i = '1' ELSE wire_nll00lii_dataout; + wire_nll01Oii_dataout <= wire_nl1lOOl0O_dataout WHEN nlliO01i = '1' ELSE wire_nll00lll_dataout; + wire_nll01Oil_dataout <= wire_nl1lOOlii_dataout WHEN nlliO01i = '1' ELSE wire_nll00llO_dataout; + wire_nll01OiO_dataout <= wire_nl1lOOlil_dataout WHEN nlliO01i = '1' ELSE wire_nll00lOi_dataout; + wire_nll01Oli_dataout <= wire_nl1lOOliO_dataout WHEN nlliO01i = '1' ELSE wire_nll00lOl_dataout; + wire_nll01Oll_dataout <= wire_nl1lO0i0l_dataout WHEN nlliO01i = '1' ELSE wire_nll00lOO_dataout; + wire_nll01OlO_dataout <= wire_nll0i01O_dataout WHEN nlliO01i = '1' ELSE wire_nll00O1i_dataout; + wire_nll01OOi_dataout <= wire_nll0i00i_dataout WHEN nlliO01i = '1' ELSE wire_nll00O1l_dataout; + wire_nll01OOl_dataout <= wire_nll0i00l_dataout WHEN nlliO01i = '1' ELSE wire_nll00O1O_dataout; + wire_nll01OOO_dataout <= wire_nll0i00O_dataout WHEN nlliO01i = '1' ELSE wire_nll00O0i_dataout; + wire_nll0i00i_dataout <= wire_nl1iliiOi_dataout WHEN niOO0101l = '1' ELSE wire_nll0il0O_dataout; + wire_nll0i00l_dataout <= wire_nl1iliiOl_dataout WHEN niOO0101l = '1' ELSE wire_nll0ilii_dataout; + wire_nll0i00O_dataout <= wire_nl1iliiOO_dataout WHEN niOO0101l = '1' ELSE wire_nll0ilil_dataout; + wire_nll0i01i_dataout <= wire_nl1ill0Ol_dataout WHEN nlliO1OO = '1' ELSE nliOlili; + wire_nll0i01l_dataout <= wire_nl1ill0OO_dataout WHEN nlliO1OO = '1' ELSE nliOlill; + wire_nll0i01O_dataout <= wire_nl1iliilO_dataout WHEN niOO0101l = '1' ELSE wire_nll0il0l_dataout; + wire_nll0i0ii_dataout <= wire_nl1ilil1i_dataout WHEN niOO0101l = '1' ELSE wire_nll0iliO_dataout; + wire_nll0i0il_dataout <= wire_nl1ilil1l_dataout WHEN niOO0101l = '1' ELSE wire_nll0illi_dataout; + wire_nll0i0iO_dataout <= wire_nl1ilil1O_dataout WHEN niOO0101l = '1' ELSE wire_nll0illl_dataout; + wire_nll0i0li_dataout <= wire_nl1ilil0i_dataout WHEN niOO0101l = '1' ELSE wire_nll0illO_dataout; + wire_nll0i0ll_dataout <= wire_nl1ilil0l_dataout WHEN niOO0101l = '1' ELSE wire_nll0ilOi_dataout; + wire_nll0i0lO_dataout <= wire_nl1ilil0O_dataout WHEN niOO0101l = '1' ELSE wire_nll0ilOl_dataout; + wire_nll0i0Oi_dataout <= wire_nl1ililii_dataout WHEN niOO0101l = '1' ELSE wire_nll0ilOO_dataout; + wire_nll0i0Ol_dataout <= wire_nl1ililil_dataout WHEN niOO0101l = '1' ELSE wire_nll0iO1i_dataout; + wire_nll0i0OO_dataout <= wire_nl1ililiO_dataout WHEN niOO0101l = '1' ELSE wire_nll0iO1l_dataout; + wire_nll0i10i_dataout <= wire_nl1ill01l_dataout WHEN nlliO1OO = '1' ELSE nliOl0Oi; + wire_nll0i10l_dataout <= wire_nl1ill01O_dataout WHEN nlliO1OO = '1' ELSE nliOl0Ol; + wire_nll0i10O_dataout <= wire_nl1ill00i_dataout WHEN nlliO1OO = '1' ELSE nliOl0OO; + wire_nll0i11i_dataout <= wire_nl1ill1Ol_dataout WHEN nlliO1OO = '1' ELSE nliOl0li; + wire_nll0i11l_dataout <= wire_nl1ill1OO_dataout WHEN nlliO1OO = '1' ELSE nliOl0ll; + wire_nll0i11O_dataout <= wire_nl1ill01i_dataout WHEN nlliO1OO = '1' ELSE nliOl0lO; + wire_nll0i1ii_dataout <= wire_nl1ill00l_dataout WHEN nlliO1OO = '1' ELSE nliOli1i; + wire_nll0i1il_dataout <= wire_nl1ill00O_dataout WHEN nlliO1OO = '1' ELSE nliOli1l; + wire_nll0i1iO_dataout <= wire_nl1ill0ii_dataout WHEN nlliO1OO = '1' ELSE nliOli1O; + wire_nll0i1li_dataout <= wire_nl1ill0il_dataout WHEN nlliO1OO = '1' ELSE nliOli0i; + wire_nll0i1ll_dataout <= wire_nl1ill0iO_dataout WHEN nlliO1OO = '1' ELSE nliOli0l; + wire_nll0i1lO_dataout <= wire_nl1ill0li_dataout WHEN nlliO1OO = '1' ELSE nliOli0O; + wire_nll0i1Oi_dataout <= wire_nl1ill0ll_dataout WHEN nlliO1OO = '1' ELSE nliOliii; + wire_nll0i1Ol_dataout <= wire_nl1ill0lO_dataout WHEN nlliO1OO = '1' ELSE nliOliil; + wire_nll0i1OO_dataout <= wire_nl1ill0Oi_dataout WHEN nlliO1OO = '1' ELSE nliOliiO; + wire_nll0ii00i_dataout <= wire_nll0il1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii00l_dataout <= wire_nll0il1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii00O_dataout <= wire_nll0il1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii01i_dataout <= wire_nll0il10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii01l_dataout <= wire_nll0il10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii01O_dataout <= wire_nll0il1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0i_dataout <= wire_nl1ililOi_dataout WHEN niOO0101l = '1' ELSE wire_nll0iO0O_dataout; + wire_nll0ii0ii_dataout <= wire_nll0il1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0il_dataout <= wire_nll0il1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0iO_dataout <= wire_nll0il1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0l_dataout <= wire_nl1ililOl_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOii_dataout; + wire_nll0ii0li_dataout <= wire_nll0il1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0ll_dataout <= wire_nll0il1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0lO_dataout <= wire_nll0il01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0O_dataout <= wire_nl1ililOO_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOil_dataout; + wire_nll0ii0Oi_dataout <= wire_nll0il01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0Ol_dataout <= wire_nll0il01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii0OO_dataout <= wire_nll0il00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii10i_dataout <= wire_nll0iiOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii10l_dataout <= wire_nll0iiOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii10O_dataout <= wire_nll0iiOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii11i_dataout <= wire_nll0iiO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii11l_dataout <= wire_nll0iiO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii11O_dataout <= wire_nll0iiOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1i_dataout <= wire_nl1ililli_dataout WHEN niOO0101l = '1' ELSE wire_nll0iO1O_dataout; + wire_nll0ii1ii_dataout <= wire_nll0iiOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1il_dataout <= wire_nll0iiOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1iO_dataout <= wire_nll0iiOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1l_dataout <= wire_nl1ililll_dataout WHEN niOO0101l = '1' ELSE wire_nll0iO0i_dataout; + wire_nll0ii1li_dataout <= wire_nll0iiOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1ll_dataout <= wire_nll0iiOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1lO_dataout <= wire_nll0il11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1O_dataout <= wire_nl1ilillO_dataout WHEN niOO0101l = '1' ELSE wire_nll0iO0l_dataout; + wire_nll0ii1Oi_dataout <= wire_nll0il11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1Ol_dataout <= wire_nll0il11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ii1OO_dataout <= wire_nll0il10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iii0i_dataout <= wire_nll0il0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iii0l_dataout <= wire_nll0il0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iii0O_dataout <= wire_nll0il0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iii1i_dataout <= wire_nll0il00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iii1l_dataout <= wire_nll0il00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iii1O_dataout <= wire_nll0il0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiii_dataout <= wire_nl1iliO1i_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOiO_dataout; + wire_nll0iiiii_dataout <= wire_nll0il0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiiil_dataout <= wire_nll0il0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiiiO_dataout <= wire_nll0il0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiil_dataout <= wire_nl1iliO1l_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOli_dataout; + wire_nll0iiili_dataout <= wire_nll0il0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiill_dataout <= wire_nll0il0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiilO_dataout <= wire_nll0ili1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiiO_dataout <= wire_nl1iliO1O_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOll_dataout; + wire_nll0iiiOi_dataout <= wire_nll0ili1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiiOl_dataout <= wire_nll0ili1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiiOO_dataout <= wire_nll0ili0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iil0i_dataout <= wire_nll0iliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iil0l_dataout <= wire_nll0iliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iil0O_dataout <= wire_nll0ilili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iil1i_dataout <= wire_nll0ili0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iil1l_dataout <= wire_nll0ili0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iil1O_dataout <= wire_nll0iliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iili_dataout <= wire_nl1iliO0i_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOlO_dataout; + wire_nll0iilii_dataout <= wire_nll0ilill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iilil_dataout <= wire_nll0ililO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiliO_dataout <= wire_nll0iliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iill_dataout <= wire_nl1iliO0l_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOOi_dataout; + wire_nll0iilli_dataout <= wire_nll0iliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iilll_dataout <= wire_nll0iliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iillO_dataout <= wire_nll0ill1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iilO_dataout <= wire_nl1iliO0O_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOOl_dataout; + wire_nll0iilOi_dataout <= wire_nll0ill1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iilOl_dataout <= wire_nll0ill1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iilOO_dataout <= wire_nll0ill0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiO0i_dataout <= wire_nll0illil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiO0l_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0lOO XOR (nll0i0lll XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0l0l XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR niOiO0l1O)))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0iO1lO; + wire_nll0iiO0O_dataout <= (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oil XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0iOO XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0illl XOR (nlli0ilil XOR nlli0ilii))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i01Oi; + wire_nll0iiO1i_dataout <= wire_nll0ill0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiO1l_dataout <= wire_nll0ill0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiO1O_dataout <= wire_nll0illii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0iiOi_dataout <= wire_nl1iliOii_dataout WHEN niOO0101l = '1' ELSE wire_nll0iOOO_dataout; + wire_nll0iiOii_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l1i XOR (nll0i0iOO XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0illl XOR (nlli0iliO XOR niOiO0i0l)))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i01Ol; + wire_nll0iiOil_dataout <= (nll0i0OOO XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0illi XOR (nlli0ilil XOR nlli0il0i))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i01OO; + wire_nll0iiOiO_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOl XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lii XOR (nll0i0l0l XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0illl XOR (nlli0illi XOR niOiO0i0O))))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i001i; + wire_nll0iiOl_dataout <= wire_nl1iliOil_dataout WHEN niOO0101l = '1' ELSE wire_nll0l11i_dataout; + wire_nll0iiOli_dataout <= (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oil XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0llO XOR (nll0i0liO XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0iOO XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0illl XOR niOiO0iii)))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i001l; + wire_nll0iiOll_dataout <= (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OiO XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0lOi XOR (nll0i0lli XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1i XOR (nll0i0iOO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii0i XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illi XOR niOiO0l1l)))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i001O; + wire_nll0iiOlO_dataout <= (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0liO XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0i XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR niOiO0iii)))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i000i; + wire_nll0iiOO_dataout <= wire_nl1iliOiO_dataout WHEN niOO0101l = '1' ELSE wire_nll0l11l_dataout; + wire_nll0iiOOi_dataout <= (nll0i0OOO XOR (nll0i0OlO XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O1i XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0liO XOR (nll0i0lii XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0iOO XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0iili XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0il1l XOR (nlli0iilO XOR (nlli0iill XOR niOiO0iil)))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i000l; + wire_nll0iiOOl_dataout <= (nll0i0OOi XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O1l XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1i XOR (nll0i0iOO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1i XOR (nlli0iill XOR (nlli0illl XOR nlli0il0O))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i000O; + wire_nll0iiOOO_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0O1O XOR (nll0i0lOO XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0lil XOR (nll0i0l0i XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0iiOO XOR (nlli0iliO XOR niOiO0l1i))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00ii; + wire_nll0il00i_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0llO XOR (nll0i0lil XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l1l XOR (nlli0i0Ol XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR (nlli0ilil XOR niOiO0l1i))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0ill; + wire_nll0il00l_dataout <= (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0lOi XOR (nll0i0liO XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l1O XOR (nlli0i0Oi XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR (nlli0iliO XOR (nlli0ilil XOR (nlli0ilii XOR niOiO0l1l)))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0ilO; + wire_nll0il00O_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0lOl XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0i XOR (nlli0i0lO XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR (nlli0ilil XOR niOiO0l1O)))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0iOi; + wire_nll0il01i_dataout <= (nll0i0OOO XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0liO XOR (nll0i0l0l XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0iiil XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR niOiO0iOi))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0iil; + wire_nll0il01l_dataout <= (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0lli XOR (nll0i0l0O XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0iOO XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iiii XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR niOiO0iOl)))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0iiO; + wire_nll0il01O_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0lll XOR (nll0i0lii XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1i XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0ii0O XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR niOiO0iOO))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0ili; + wire_nll0il0i_dataout <= wire_nl1iliOOi_dataout WHEN niOO0101l = '1' ELSE wire_nll0l10O_dataout; + wire_nll0il0ii_dataout <= wire_nll0illiO_dataout WHEN niOiO0O0O = '1' ELSE nll0i0iOl; + wire_nll0il0il_dataout <= wire_nll0illli_dataout WHEN niOiO0O0O = '1' ELSE nll0i0iOO; + wire_nll0il0iO_dataout <= wire_nll0illll_dataout WHEN niOiO0O0O = '1' ELSE nll0i0l1i; + wire_nll0il0l_dataout <= wire_nl1lO1l1l_dataout AND NOT(nlliO11l); + wire_nll0il0li_dataout <= wire_nll0illlO_dataout WHEN niOiO0O0O = '1' ELSE nll0i0l1l; + wire_nll0il0ll_dataout <= wire_nll0illOi_dataout WHEN niOiO0O0O = '1' ELSE nll0i0l1O; + wire_nll0il0lO_dataout <= wire_nll0illOl_dataout WHEN niOiO0O0O = '1' ELSE nll0i0l0i; + wire_nll0il0O_dataout <= wire_nl1lO1l1O_dataout AND NOT(nlliO11l); + wire_nll0il0Oi_dataout <= wire_nll0illOO_dataout WHEN niOiO0O0O = '1' ELSE nll0i0l0l; + wire_nll0il0Ol_dataout <= wire_nll0ilO1i_dataout WHEN niOiO0O0O = '1' ELSE nll0i0l0O; + wire_nll0il0OO_dataout <= wire_nll0ilO1l_dataout WHEN niOiO0O0O = '1' ELSE nll0i0lii; + wire_nll0il10i_dataout <= (nll0i0OOi XOR (nll0i0Oli XOR (nll0i0Oii XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0lli XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0l1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iill XOR (nlli0iliO XOR nlli0il0O))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00ll; + wire_nll0il10l_dataout <= (nll0i0OOl XOR (nll0i0Oll XOR (nll0i0Oil XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lll XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1l XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0illl XOR (nlli0ilil XOR nlli0il0l))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00lO; + wire_nll0il10O_dataout <= (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O1O XOR (nll0i0O1i XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0lii XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0iili XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR (nlli0iliO XOR niOiO0l1l)))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00Oi; + wire_nll0il11i_dataout <= (nll0i0OOO XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0i XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0lil XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0iOO XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR (nlli0ilil XOR niOiO0iil)))))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00il; + wire_nll0il11l_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0Oll XOR (nll0i0Oil XOR (nll0i0O0l XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0lil XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1i XOR (nll0i0iOO XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOi XOR (nlli0illl XOR niOiO0iiO))))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00iO; + wire_nll0il11O_dataout <= (nll0i0OOO XOR (nll0i0OlO XOR (nll0i0OiO XOR (nll0i0O0O XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0liO XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR (nlli0illi XOR niOiO0iil)))))))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00li; + wire_nll0il1i_dataout <= wire_nl1iliOli_dataout WHEN niOO0101l = '1' ELSE wire_nll0l11O_dataout; + wire_nll0il1ii_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0i XOR (nll0i0O1l XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0lil XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0iOO XOR (nlli0ii1i XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illi XOR niOiO0iiO))))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00Ol; + wire_nll0il1il_dataout <= (nll0i0OOO XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0l XOR (nll0i0O1O XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0liO XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l1i XOR (nlli0i0OO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0illl XOR niOiO0iOi))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i00OO; + wire_nll0il1iO_dataout <= (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O0i XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lli XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l1l XOR (nlli0i0Ol XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR niOiO0iOl)))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0i1i; + wire_nll0il1l_dataout <= wire_nl1iliOll_dataout WHEN niOO0101l = '1' ELSE wire_nll0l10i_dataout; + wire_nll0il1li_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0l XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lll XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l1O XOR (nlli0i0Oi XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR niOiO0ili)))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0i1l; + wire_nll0il1ll_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0llO XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0l0i XOR (nlli0i0lO XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0l XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iilO XOR niOiO0ill))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0i1O; + wire_nll0il1lO_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iill XOR niOiO0ill))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0i0i; + wire_nll0il1O_dataout <= wire_nl1iliOlO_dataout WHEN niOO0101l = '1' ELSE wire_nll0l10l_dataout; + wire_nll0il1Oi_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0lil XOR (nll0i0l0l XOR (nll0i0iOO XOR (nll0i0iOl XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR niOiO0ilO)))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0i0l; + wire_nll0il1Ol_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lOi XOR (nll0i0liO XOR (nll0i0l0O XOR (nll0i0l1i XOR (nll0i0iOO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iiOi XOR niOiO0iOO))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0i0O; + wire_nll0il1OO_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lli XOR (nll0i0lii XOR (nll0i0l1l XOR (nll0i0l1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iilO XOR niOiO0l1i))))))))))))))))))))))) WHEN niOiO0O0O = '1' ELSE nll0i0iii; + wire_nll0ili0i_dataout <= wire_nll0ilO0O_dataout WHEN niOiO0O0O = '1' ELSE nll0i0lll; + wire_nll0ili0l_dataout <= wire_nll0ilOii_dataout WHEN niOiO0O0O = '1' ELSE nll0i0llO; + wire_nll0ili0O_dataout <= wire_nll0ilOil_dataout WHEN niOiO0O0O = '1' ELSE nll0i0lOi; + wire_nll0ili1i_dataout <= wire_nll0ilO1O_dataout WHEN niOiO0O0O = '1' ELSE nll0i0lil; + wire_nll0ili1l_dataout <= wire_nll0ilO0i_dataout WHEN niOiO0O0O = '1' ELSE nll0i0liO; + wire_nll0ili1O_dataout <= wire_nll0ilO0l_dataout WHEN niOiO0O0O = '1' ELSE nll0i0lli; + wire_nll0ilii_dataout <= wire_nl1lO1l0i_dataout AND NOT(nlliO11l); + wire_nll0iliii_dataout <= wire_nll0ilOiO_dataout WHEN niOiO0O0O = '1' ELSE nll0i0lOl; + wire_nll0iliil_dataout <= wire_nll0ilOli_dataout WHEN niOiO0O0O = '1' ELSE nll0i0lOO; + wire_nll0iliiO_dataout <= wire_nll0ilOll_dataout WHEN niOiO0O0O = '1' ELSE nll0i0O1i; + wire_nll0ilil_dataout <= wire_nl1lO1l0l_dataout AND NOT(nlliO11l); + wire_nll0ilili_dataout <= wire_nll0ilOlO_dataout WHEN niOiO0O0O = '1' ELSE nll0i0O1l; + wire_nll0ilill_dataout <= wire_nll0ilOOi_dataout WHEN niOiO0O0O = '1' ELSE nll0i0O1O; + wire_nll0ililO_dataout <= wire_nll0ilOOl_dataout WHEN niOiO0O0O = '1' ELSE nll0i0O0i; + wire_nll0iliO_dataout <= wire_nl1lO1l0O_dataout AND NOT(nlliO11l); + wire_nll0iliOi_dataout <= wire_nll0ilOOO_dataout WHEN niOiO0O0O = '1' ELSE nll0i0O0l; + wire_nll0iliOl_dataout <= wire_nll0iO11i_dataout WHEN niOiO0O0O = '1' ELSE nll0i0O0O; + wire_nll0iliOO_dataout <= wire_nll0iO11l_dataout WHEN niOiO0O0O = '1' ELSE nll0i0Oii; + wire_nll0ill0i_dataout <= wire_nll0iO10O_dataout WHEN niOiO0O0O = '1' ELSE nll0i0Oll; + wire_nll0ill0l_dataout <= wire_nll0iO1ii_dataout WHEN niOiO0O0O = '1' ELSE nll0i0OlO; + wire_nll0ill0O_dataout <= wire_nll0iO1il_dataout WHEN niOiO0O0O = '1' ELSE nll0i0OOi; + wire_nll0ill1i_dataout <= wire_nll0iO11O_dataout WHEN niOiO0O0O = '1' ELSE nll0i0Oil; + wire_nll0ill1l_dataout <= wire_nll0iO10i_dataout WHEN niOiO0O0O = '1' ELSE nll0i0OiO; + wire_nll0ill1O_dataout <= wire_nll0iO10l_dataout WHEN niOiO0O0O = '1' ELSE nll0i0Oli; + wire_nll0illi_dataout <= wire_nl1lO1lii_dataout AND NOT(nlliO11l); + wire_nll0illii_dataout <= wire_nll0iO1iO_dataout WHEN niOiO0O0O = '1' ELSE nll0i0OOl; + wire_nll0illil_dataout <= wire_nll0iO1li_dataout WHEN niOiO0O0O = '1' ELSE nll0i0OOO; + wire_nll0illiO_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0l0i XOR (nll0i0l1i XOR (nll0i0iOl XOR (wire_nllii0lii_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0Oil_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0iliO XOR niOiO0lOi)))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0illl_dataout <= wire_nl1lO1lil_dataout AND NOT(nlliO11l); + wire_nll0illli_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0O0l XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOO XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (nlli0i0iO XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOi XOR niOiO0l0l))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0illll_dataout <= (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0lll XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0iOl XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0ii0O XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iill XOR niOiO0l0O))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0illlO_dataout <= (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0llO XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0iOO XOR (nll0i0iOl XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0ii0l XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR (nlli0iliO XOR niOiO0lli))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0illO_dataout <= wire_nl1lO1liO_dataout AND NOT(nlliO11l); + wire_nll0illOi_dataout <= (nll0i0OOO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0iOO XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (niOiO0O1O XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0illi XOR (nlli0iliO XOR (nlli0ilil XOR niOiO0l0i)))))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0illOl_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0i XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i0iO XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (niOiO0O1O XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR niOiO0lii)))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0illOO_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0lli XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0l XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0il XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i0ll XOR (nlli0iili XOR (niOiO0O1O XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO0lil))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilO0i_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0i XOR (nll0i0O1l XOR (nll0i0liO XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0iOO XOR (nll0i0iOl XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0l_dataout XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iill XOR niOiO0l0l))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilO0l_dataout <= (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l1O XOR (nll0i0iOO XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0iili XOR (niOiO0O1O XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO0l0O)))))))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilO0O_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0liO XOR (nll0i0lil XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i0iO XOR (nlli0i00O XOR (nlli0i01O XOR (nlli0i01l XOR (niOiO0O1O XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR niOiO0lii)))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilO1i_dataout <= (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0lli XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0l0O XOR (nll0i0l0i XOR (nll0i0l1i XOR (nll0i0iOl XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0i0li XOR (niOiO0O1O XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR nlli0ilii))))))))))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilO1l_dataout <= (nll0i0OOO XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0O0O XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0lli XOR (nll0i0liO XOR (nll0i0lii XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOO XOR (nll0i0iOl XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0illi XOR (nlli0ilil XOR (nlli0ilii XOR niOiO0l0i)))))))))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilO1O_dataout <= (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0Oii XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0l1i XOR (nll0i0iOO XOR (nll0i0iOl XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0i0li XOR (niOiO0O1O XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0iliO XOR niOiO0lll)))))))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOi_dataout <= wire_nl1lO1lli_dataout AND NOT(nlliO11l); + wire_nll0ilOii_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lli XOR (nll0i0liO XOR (nll0i0iOl XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0il XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR niOiO0lil)))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOil_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0iOO XOR (nll0i0iOl XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0ii XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR niOiO0O0i)))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOiO_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0l1i XOR (nll0i0iOO XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i0iO XOR (nlli0i00O XOR (nlli0i01O XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO0O0l))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOl_dataout <= wire_nl1lO1lll_dataout AND NOT(nlliO11l); + wire_nll0ilOli_dataout <= (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O1O XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0l0i XOR (nll0i0l1l XOR (nll0i0iOl XOR (wire_nllii0lii_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOO XOR (nlli0illl XOR nlli0illi))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOll_dataout <= (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0O0i XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0l0l XOR (nll0i0l1O XOR (nll0i0iOO XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0illi XOR nlli0iliO))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOlO_dataout <= (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0O0l XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lOi XOR (nll0i0l0O XOR (nll0i0l0i XOR (nll0i0l1i XOR (nll0i0iOl XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOi XOR niOiO0liO))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOO_dataout <= wire_nl1lO1llO_dataout AND NOT(nlliO11l); + wire_nll0ilOOi_dataout <= (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0O0O XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lii XOR (nll0i0l0l XOR (nll0i0l1l XOR (nll0i0iOO XOR (nll0i0iOl XOR (wire_nllii0l0i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR niOiO0lli)))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOOl_dataout <= (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oii XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lil XOR (nll0i0l0O XOR (nll0i0l1O XOR (nll0i0l1i XOR (nll0i0iOO XOR (wire_nllii0l1O_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i01O XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0li XOR (niOiO0O1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iill XOR niOiO0lll)))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0ilOOO_dataout <= (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0Oil XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1i XOR (nll0i0liO XOR (nll0i0lii XOR (nll0i0l0i XOR (nll0i0l1l XOR (nll0i0l1i XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0iili XOR (nlli0iiil XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0illl XOR niOiO0lOl)))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO0i_dataout <= wire_nl1lO1O1i_dataout AND NOT(nlliO11l); + wire_nll0iO0l_dataout <= wire_nl1lO1O1l_dataout AND NOT(nlliO11l); + wire_nll0iO0O_dataout <= wire_nl1lO1O1O_dataout AND NOT(nlliO11l); + wire_nll0iO10i_dataout <= (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lll XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0iOO XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iili XOR (niOiO0O1O XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR niOiO0lOl))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO10l_dataout <= (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O0i XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lll XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0l0O XOR (nll0i0l0l XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0i0ll XOR (nlli0i0li XOR (niOiO0O1O XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illi XOR (nlli0ilil XOR niOiO0lOO)))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO10O_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0l XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOO XOR (nll0i0llO XOR (nll0i0lli XOR (nll0i0liO XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0iOl XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0illl XOR (nlli0iliO XOR (nlli0ilii XOR niOiO0O1i))))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO11i_dataout <= (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0i XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0l0l XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0l1i XOR (wire_nllii0lii_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (niOiO0O1O XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOl XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR niOiO0lOO))))))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO11l_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O0O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0liO XOR (nll0i0l0O XOR (nll0i0l0l XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0l1i XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO0llO))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO11O_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0OlO XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0Oii XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOO XOR (nll0i0lOl XOR (nll0i0lli XOR (nll0i0lii XOR (nll0i0l0O XOR (nll0i0l0i XOR (nll0i0l1O XOR (nll0i0l1l XOR (nll0i0iOl XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i01O XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR niOiO0lOi)))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO1i_dataout <= wire_nl1lO1lOi_dataout AND NOT(nlliO11l); + wire_nll0iO1ii_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0Oil XOR (nll0i0O0O XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0O1i XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0lil XOR (nll0i0lii XOR (nll0i0iOO XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i01O XOR (nlli0ii1i XOR (nlli0iili XOR (niOiO0O1O XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR (nlli0ilil XOR niOiO0O1i))))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO1il_dataout <= (nll0i0OOO XOR (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oli XOR (nll0i0OiO XOR (nll0i0Oii XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0O1l XOR (nll0i0lOl XOR (nll0i0llO XOR (nll0i0lll XOR (nll0i0liO XOR (nll0i0lil XOR (nll0i0l1i XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (niOiO0O1O XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR niOiO0O1l))))))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO1iO_dataout <= (nll0i0OOO XOR (nll0i0OOi XOR (nll0i0Oll XOR (nll0i0Oli XOR (nll0i0Oil XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1O XOR (nll0i0lOO XOR (nll0i0lOi XOR (nll0i0llO XOR (nll0i0lli XOR (nll0i0liO XOR (nll0i0l1l XOR (nll0i0iOl XOR (wire_nllii0l1O_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR niOiO0O0i)))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO1l_dataout <= wire_nl1lO1lOl_dataout AND NOT(nlliO11l); + wire_nll0iO1li_dataout <= (nll0i0OOl XOR (nll0i0OlO XOR (nll0i0Oll XOR (nll0i0OiO XOR (nll0i0O0O XOR (nll0i0O0l XOR (nll0i0O0i XOR (nll0i0O1i XOR (nll0i0lOl XOR (nll0i0lOi XOR (nll0i0lll XOR (nll0i0lli XOR (nll0i0l1O XOR (nll0i0iOO XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR niOiO0O0l))))))))))))))))))))))))))))))))))))) OR niOiOii1O; + wire_nll0iO1O_dataout <= wire_nl1lO1lOO_dataout AND NOT(nlliO11l); + wire_nll0iOii_dataout <= wire_nl1lO1O0i_dataout AND NOT(nlliO11l); + wire_nll0iOil_dataout <= wire_nl1lO1O0l_dataout AND NOT(nlliO11l); + wire_nll0iOiO_dataout <= wire_nl1lO1O0O_dataout AND NOT(nlliO11l); + wire_nll0iOli_dataout <= wire_nl1lO1Oii_dataout AND NOT(nlliO11l); + wire_nll0iOll_dataout <= wire_nl1lO1Oil_dataout AND NOT(nlliO11l); + wire_nll0iOlO_dataout <= wire_nl1lO1OiO_dataout AND NOT(nlliO11l); + wire_nll0iOOi_dataout <= wire_nl1lO1Oli_dataout AND NOT(nlliO11l); + wire_nll0iOOl_dataout <= wire_nl1lO1Oll_dataout AND NOT(nlliO11l); + wire_nll0iOOO_dataout <= wire_nl1lO1OlO_dataout AND NOT(nlliO11l); + wire_nll0l00i_dataout <= wire_nlilOO0l_dataout OR niOO0101O; + wire_nll0l00l_dataout <= wire_nlilOO0O_dataout OR niOO0101O; + wire_nll0l00O_dataout <= wire_nlilOOii_dataout OR niOO0101O; + wire_nll0l01i_dataout <= wire_nll0l0iO_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0O1l; + wire_nll0l01l_dataout <= wire_nll0l0li_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0O1O; + wire_nll0l01O_dataout <= wire_nlilOO0i_dataout OR niOO0101O; + wire_nll0l0ii_dataout <= wire_nlilOOil_dataout OR niOO0101O; + wire_nll0l0il_dataout <= wire_nlilOOiO_dataout OR niOO0101O; + wire_nll0l0iO_dataout <= wire_nlilOOli_dataout OR niOO0101O; + wire_nll0l0li_dataout <= wire_nlilOOll_dataout OR niOO0101O; + wire_nll0l0lO_dataout <= nl1il1iil WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0l1O; + wire_nll0l0Oi_dataout <= nl1il1iiO WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0l0i; + wire_nll0l0Ol_dataout <= nl1il1ili WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0l0l; + wire_nll0l0OO_dataout <= nl1il1ill WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0l0O; + wire_nll0l10i_dataout <= wire_nl1lO011i_dataout AND NOT(nlliO11l); + wire_nll0l10l_dataout <= wire_nl1lO011l_dataout AND NOT(nlliO11l); + wire_nll0l10O_dataout <= wire_nl1lO011O_dataout AND NOT(nlliO11l); + wire_nll0l11i_dataout <= wire_nl1lO1OOi_dataout AND NOT(nlliO11l); + wire_nll0l11l_dataout <= wire_nl1lO1OOl_dataout AND NOT(nlliO11l); + wire_nll0l11O_dataout <= wire_nl1lO1OOO_dataout AND NOT(nlliO11l); + wire_nll0l1li_dataout <= wire_nll0l01O_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0lll; + wire_nll0l1ll_dataout <= wire_nll0l00i_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0llO; + wire_nll0l1lO_dataout <= wire_nll0l00l_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0lOi; + wire_nll0l1Oi_dataout <= wire_nll0l00O_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0lOl; + wire_nll0l1Ol_dataout <= wire_nll0l0ii_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0lOO; + wire_nll0l1OO_dataout <= wire_nll0l0il_dataout WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0O1i; + wire_nll0li0i_dataout <= nl1il1iOO WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0lli; + wire_nll0li0l_dataout <= wire_nll0liOl_dataout OR niOO0100i; + wire_nll0li0O_dataout <= nl1il1iil WHEN niOO0100i = '1' ELSE nliO0iiO; + wire_nll0li1i_dataout <= nl1il1ilO WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0lii; + wire_nll0li1l_dataout <= nl1il1iOi WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0lil; + wire_nll0li1O_dataout <= nl1il1iOl WHEN wire_nl1000i_w_lg_nllillOl5218w(0) = '1' ELSE nliO0liO; + wire_nll0liii_dataout <= nl1il1iiO WHEN niOO0100i = '1' ELSE nliO0ili; + wire_nll0liil_dataout <= nl1il1ili WHEN niOO0100i = '1' ELSE nliO0ill; + wire_nll0liiO_dataout <= nl1il1ill WHEN niOO0100i = '1' ELSE nliO0ilO; + wire_nll0lil0i_dataout <= wire_nll0lil0l_dataout OR (niOiO0OOO AND wire_nl1000i_w_lg_nll0liiOl29690w(0)); + wire_nll0lil0l_dataout <= nll0liiOi AND NOT((niOiO0OOi OR nll0liiOl)); + wire_nll0lil1i_dataout <= wire_nll0liliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lil1l_dataout <= wire_nll0lil0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lil1O_dataout <= wire_nll0lilli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lili_dataout <= nl1il1ilO WHEN niOO0100i = '1' ELSE nliO0iOi; + wire_nll0liliO_dataout <= wire_nll0lilll_dataout AND NOT(niOiO0OiO); + wire_nll0lill_dataout <= nl1il1iOi WHEN niOO0100i = '1' ELSE nliO0iOl; + wire_nll0lilli_dataout <= wire_nll0lillO_dataout OR niOiO0OiO; + wire_nll0lilll_dataout <= wire_nll0lilOi_dataout OR niOiO0Oil; + wire_nll0lillO_dataout <= wire_nll0lilOl_dataout OR niOiO0Oil; + wire_nll0lilO_dataout <= nl1il1iOl WHEN niOO0100i = '1' ELSE nliO0iOO; + wire_nll0lilOi_dataout <= wire_nll0lilOO_dataout AND NOT(niOiO0Oii); + wire_nll0lilOl_dataout <= wire_nll0liO1i_dataout OR niOiO0Oii; + wire_nll0lilOO_dataout <= nll0lilil AND NOT(niOiO0OOi); + wire_nll0liO1i_dataout <= nll0liiOl AND NOT(niOiO0OOi); + wire_nll0liOi_dataout <= nl1il1iOO WHEN niOO0100i = '1' ELSE nliO0l1i; + wire_nll0liOl_dataout <= nliO0iil AND nl1OilOii; + wire_nll0ll00i_dataout <= wire_nll0lliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll00l_dataout <= wire_nll0lliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll00O_dataout <= wire_nll0lliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll01i_dataout <= wire_nll0llili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll01l_dataout <= wire_nll0llill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll01O_dataout <= wire_nll0llilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0ii_dataout <= wire_nll0lll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0il_dataout <= wire_nll0lll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0iO_dataout <= wire_nll0lll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0li_dataout <= wire_nll0lll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0ll_dataout <= wire_nll0lll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0lO_dataout <= wire_nll0lll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0Oi_dataout <= wire_nll0lllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0Ol_dataout <= wire_nll0lllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0ll0OO_dataout <= wire_nll0llliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lli0i_dataout <= wire_nll0lllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lli0l_dataout <= wire_nll0lllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lli0O_dataout <= wire_nll0lllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lli1i_dataout <= wire_nll0lllli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lli1l_dataout <= wire_nll0lllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lli1O_dataout <= wire_nll0llllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lliii_dataout <= wire_nll0llO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lliil_dataout <= wire_nll0llO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lliiO_dataout <= wire_nll0llO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0llili_dataout <= wire_nll0llO0i_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0llill_dataout <= wire_nll0llO0l_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0llilO_dataout <= wire_nll0llO0O_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lliOi_dataout <= wire_nll0llOii_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lliOl_dataout <= wire_nll0llOil_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lliOO_dataout <= wire_nll0llOiO_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lll0i_dataout <= wire_nll0llOOi_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lll0l_dataout <= wire_nll0llOOl_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lll0O_dataout <= wire_nll0llOOO_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lll1i_dataout <= wire_nll0llOli_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lll1l_dataout <= wire_nll0llOll_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lll1O_dataout <= wire_nll0llOlO_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nll0lllii_dataout <= wire_nll0lO11i_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0lllil_dataout <= wire_nll0lO11l_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0llliO_dataout <= wire_nll0lO11O_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0lllli_dataout <= wire_nll0lO10i_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0lllll_dataout <= wire_nll0lO10l_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0llllO_dataout <= wire_nll0lO10O_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0lllOi_dataout <= wire_nll0lO1ii_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0lllOl_dataout <= wire_nll0lO1il_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0lllOO_dataout <= wire_nll0lO1iO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0llO0i_dataout <= nll0ll11O WHEN niOiO0Oli = '1' ELSE nll0liiOO; + wire_nll0llO0l_dataout <= nll0ll10i WHEN niOiO0Oli = '1' ELSE nll0liOii; + wire_nll0llO0O_dataout <= nll0ll10l WHEN niOiO0Oli = '1' ELSE nll0liOil; + wire_nll0llO1i_dataout <= wire_nll0lO1li_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0llO1l_dataout <= wire_nll0lO1ll_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0llO1O_dataout <= wire_nll0lO1lO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nll0llOii_dataout <= nll0ll10O WHEN niOiO0Oli = '1' ELSE nll0liOiO; + wire_nll0llOil_dataout <= nll0ll1ii WHEN niOiO0Oli = '1' ELSE nll0liOli; + wire_nll0llOiO_dataout <= nll0ll1il WHEN niOiO0Oli = '1' ELSE nll0liOll; + wire_nll0llOli_dataout <= nll0ll1iO WHEN niOiO0Oli = '1' ELSE nll0liOlO; + wire_nll0llOll_dataout <= nll0ll1li WHEN niOiO0Oli = '1' ELSE nll0liOOi; + wire_nll0llOlO_dataout <= nll0ll1ll WHEN niOiO0Oli = '1' ELSE nll0liOOl; + wire_nll0llOOi_dataout <= nll0ll1lO WHEN niOiO0Oli = '1' ELSE nll0liOOO; + wire_nll0llOOl_dataout <= nll0ll1Oi WHEN niOiO0Oli = '1' ELSE nll0ll11i; + wire_nll0llOOO_dataout <= nll0ll1Ol WHEN niOiO0Oli = '1' ELSE nll0ll11l; + wire_nll0lO00i_dataout <= nll0ll1OO OR niOiO0Oll; + wire_nll0lO01l_dataout <= wire_nll0lO01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lO01O_dataout <= wire_nll0lO00i_dataout AND NOT((wire_nl1000i_w_lg_nlilOO0iO5228w(0) OR niOiO0OOO)); + wire_nll0lO10i_dataout <= wire_nll0lO1Oi_o(3) WHEN niOiO0Oli = '1' ELSE nll0ll10O; + wire_nll0lO10l_dataout <= wire_nll0lO1Oi_o(4) WHEN niOiO0Oli = '1' ELSE nll0ll1ii; + wire_nll0lO10O_dataout <= wire_nll0lO1Oi_o(5) WHEN niOiO0Oli = '1' ELSE nll0ll1il; + wire_nll0lO11i_dataout <= wire_nll0lO1Oi_o(0) WHEN niOiO0Oli = '1' ELSE nll0ll11O; + wire_nll0lO11l_dataout <= wire_nll0lO1Oi_o(1) WHEN niOiO0Oli = '1' ELSE nll0ll10i; + wire_nll0lO11O_dataout <= wire_nll0lO1Oi_o(2) WHEN niOiO0Oli = '1' ELSE nll0ll10l; + wire_nll0lO1ii_dataout <= wire_nll0lO1Oi_o(6) WHEN niOiO0Oli = '1' ELSE nll0ll1iO; + wire_nll0lO1il_dataout <= wire_nll0lO1Oi_o(7) WHEN niOiO0Oli = '1' ELSE nll0ll1li; + wire_nll0lO1iO_dataout <= wire_nll0lO1Oi_o(8) WHEN niOiO0Oli = '1' ELSE nll0ll1ll; + wire_nll0lO1li_dataout <= wire_nll0lO1Oi_o(9) WHEN niOiO0Oli = '1' ELSE nll0ll1lO; + wire_nll0lO1ll_dataout <= wire_nll0lO1Oi_o(10) WHEN niOiO0Oli = '1' ELSE nll0ll1Oi; + wire_nll0lO1lO_dataout <= wire_nll0lO1Oi_o(11) WHEN niOiO0Oli = '1' ELSE nll0ll1Ol; + wire_nll0lOi0i_dataout <= (wire_nll0lOl1l_o AND wire_nlOilOiiO_dataout) AND NOT(wire_niO01O0O_dataout); + wire_nll0lOi0l_dataout <= wire_nll0lOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOi0O_dataout <= wire_nll0lOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOiii_dataout <= wire_nll0lOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOiil_dataout <= wire_nll0lOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOiiO_dataout <= wire_nll0lOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOili_dataout <= wire_nll0lOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOill_dataout <= wire_nll0lOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOilO_dataout <= wire_nll0lOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOiOi_dataout <= wire_nll0lOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOiOl_dataout <= wire_nll0lOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOiOO_dataout <= wire_nll0lOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0lOl0i_dataout <= wire_nll0lOlOl_dataout AND NOT(niOiO0OlO); + wire_nll0lOl0l_dataout <= wire_nll0lOlOO_dataout AND NOT(niOiO0OlO); + wire_nll0lOl0O_dataout <= wire_nll0lOO1i_dataout AND NOT(niOiO0OlO); + wire_nll0lOl1O_dataout <= wire_nll0lOlOi_dataout AND NOT(niOiO0OlO); + wire_nll0lOlii_dataout <= wire_nll0lOO1l_dataout AND NOT(niOiO0OlO); + wire_nll0lOlil_dataout <= wire_nll0lOO1O_dataout AND NOT(niOiO0OlO); + wire_nll0lOliO_dataout <= wire_nll0lOO0i_dataout AND NOT(niOiO0OlO); + wire_nll0lOlli_dataout <= wire_nll0lOO0l_dataout AND NOT(niOiO0OlO); + wire_nll0lOlll_dataout <= wire_nll0lOO0O_dataout AND NOT(niOiO0OlO); + wire_nll0lOllO_dataout <= wire_nll0lOOii_dataout AND NOT(niOiO0OlO); + wire_nll0lOlOi_dataout <= wire_nll0lOOil_o(0) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0ii; + wire_nll0lOlOl_dataout <= wire_nll0lOOil_o(1) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0il; + wire_nll0lOlOO_dataout <= wire_nll0lOOil_o(2) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0iO; + wire_nll0lOO0i_dataout <= wire_nll0lOOil_o(6) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0Oi; + wire_nll0lOO0l_dataout <= wire_nll0lOOil_o(7) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0Ol; + wire_nll0lOO0O_dataout <= wire_nll0lOOil_o(8) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0OO; + wire_nll0lOO1i_dataout <= wire_nll0lOOil_o(3) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0li; + wire_nll0lOO1l_dataout <= wire_nll0lOOil_o(4) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0ll; + wire_nll0lOO1O_dataout <= wire_nll0lOOil_o(5) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lO0lO; + wire_nll0lOOii_dataout <= wire_nll0lOOil_o(9) WHEN wire_nlOilOiiO_dataout = '1' ELSE nll0lOi1i; + wire_nll0lOOll_dataout <= wire_nll0lOOlO_dataout OR ((nlilOO0iO AND nll0O0i0i) AND (nll0OOOOi OR nll0OOOlO)); + wire_nll0lOOlO_dataout <= nll0lOi1l AND NOT(niOiO0OOi); + wire_nll0O000i_dataout <= wire_nllii1OiO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10il; + wire_nll0O000l_dataout <= wire_nllii1Oli_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10iO; + wire_nll0O000O_dataout <= wire_nllii1Oll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10li; + wire_nll0O001i_dataout <= wire_nllii1O0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O100l; + wire_nll0O001l_dataout <= wire_nllii1Oii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O100O; + wire_nll0O001O_dataout <= wire_nllii1Oil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10ii; + wire_nll0O00ii_dataout <= wire_nllii1OlO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10ll; + wire_nll0O00il_dataout <= wire_nllii1OOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10lO; + wire_nll0O00iO_dataout <= wire_nllii1OOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10Oi; + wire_nll0O00li_dataout <= wire_nllii1OOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O10Ol; + wire_nll0O010i_dataout <= nll0O100l WHEN nlli0iO1i = '1' ELSE nll0O11il; + wire_nll0O010l_dataout <= nll0O100O WHEN nlli0iO1i = '1' ELSE nll0O11iO; + wire_nll0O010O_dataout <= nll0O10ii WHEN nlli0iO1i = '1' ELSE nll0O11li; + wire_nll0O011i_dataout <= nll0O1i1i AND NOT(niOO01i1O); + wire_nll0O011l_dataout <= nll0O101O WHEN nlli0iO1i = '1' ELSE nll0lOi1O; + wire_nll0O011O_dataout <= nll0O100i WHEN nlli0iO1i = '1' ELSE nll0O11ii; + wire_nll0O01ii_dataout <= nll0O10il WHEN nlli0iO1i = '1' ELSE nll0O11ll; + wire_nll0O01il_dataout <= nll0O10iO WHEN nlli0iO1i = '1' ELSE nll0O11lO; + wire_nll0O01iO_dataout <= nll0O10li WHEN nlli0iO1i = '1' ELSE nll0O11Oi; + wire_nll0O01li_dataout <= nll0O10ll WHEN nlli0iO1i = '1' ELSE nll0O11Ol; + wire_nll0O01ll_dataout <= nll0O10lO WHEN nlli0iO1i = '1' ELSE nll0O11OO; + wire_nll0O01lO_dataout <= nll0O10Oi WHEN nlli0iO1i = '1' ELSE nll0O101i; + wire_nll0O01Oi_dataout <= nll0O10Ol WHEN nlli0iO1i = '1' ELSE nll0O101l; + wire_nll0O01Ol_dataout <= wire_nllii1O0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O101O; + wire_nll0O01OO_dataout <= wire_nllii1O0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0O100i; + wire_nll0O1i0i_dataout <= wire_nll0O1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1i0l_dataout <= wire_nll0O1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1i0O_dataout <= wire_nll0O1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1i1O_dataout <= wire_nll0O1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1iii_dataout <= wire_nll0O1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1iil_dataout <= wire_nll0O1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1iiO_dataout <= wire_nll0O1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1ili_dataout <= wire_nll0O1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1ill_dataout <= wire_nll0O1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1ilO_dataout <= wire_nll0O1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1iOi_dataout <= wire_nll0O1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1iOl_dataout <= wire_nll0O1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1iOO_dataout <= wire_nll0O01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1l0i_dataout <= wire_nll0O001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1l0l_dataout <= wire_nll0O000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1l0O_dataout <= wire_nll0O000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1l1i_dataout <= wire_nll0O01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1l1l_dataout <= wire_nll0O001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1l1O_dataout <= wire_nll0O001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1lii_dataout <= wire_nll0O000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1lil_dataout <= wire_nll0O00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1liO_dataout <= wire_nll0O00il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1lli_dataout <= wire_nll0O00iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1lll_dataout <= wire_nll0O00li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1llO_dataout <= wire_nll0O1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1lOi_dataout <= wire_nll0O1lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0O1lOl_dataout <= wire_nll0O1OOi_dataout WHEN nll0O0i0i = '1' ELSE nll0O10OO; + wire_nll0O1lOO_dataout <= wire_nll0O1OOl_dataout WHEN nll0O0i0i = '1' ELSE nll0O1i1i; + wire_nll0O1O0i_dataout <= wire_nll0O010l_dataout WHEN nll0O0i0i = '1' ELSE nll0O11iO; + wire_nll0O1O0l_dataout <= wire_nll0O010O_dataout WHEN nll0O0i0i = '1' ELSE nll0O11li; + wire_nll0O1O0O_dataout <= wire_nll0O01ii_dataout WHEN nll0O0i0i = '1' ELSE nll0O11ll; + wire_nll0O1O1i_dataout <= wire_nll0O011l_dataout WHEN nll0O0i0i = '1' ELSE nll0lOi1O; + wire_nll0O1O1l_dataout <= wire_nll0O011O_dataout WHEN nll0O0i0i = '1' ELSE nll0O11ii; + wire_nll0O1O1O_dataout <= wire_nll0O010i_dataout WHEN nll0O0i0i = '1' ELSE nll0O11il; + wire_nll0O1Oii_dataout <= wire_nll0O01il_dataout WHEN nll0O0i0i = '1' ELSE nll0O11lO; + wire_nll0O1Oil_dataout <= wire_nll0O01iO_dataout WHEN nll0O0i0i = '1' ELSE nll0O11Oi; + wire_nll0O1OiO_dataout <= wire_nll0O01li_dataout WHEN nll0O0i0i = '1' ELSE nll0O11Ol; + wire_nll0O1Oli_dataout <= wire_nll0O01ll_dataout WHEN nll0O0i0i = '1' ELSE nll0O11OO; + wire_nll0O1Oll_dataout <= wire_nll0O01lO_dataout WHEN nll0O0i0i = '1' ELSE nll0O101i; + wire_nll0O1OlO_dataout <= wire_nll0O01Oi_dataout WHEN nll0O0i0i = '1' ELSE nll0O101l; + wire_nll0O1OOi_dataout <= wire_nll0O00ll_o WHEN nlli0ilOl = '1' ELSE wire_nll0O1OOO_dataout; + wire_nll0O1OOl_dataout <= niOiOi11l WHEN nlli0ilOl = '1' ELSE wire_nll0O011i_dataout; + wire_nll0O1OOO_dataout <= nll0O10OO AND NOT(niOO01i1O); + wire_nll0Oii0l_dataout <= wire_nll0OlOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oii0O_dataout <= wire_nll0Oli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oiiii_dataout <= nll0O0i0i AND NOT(wire_niO01O0O_dataout); + wire_nll0Oiiil_dataout <= nll0O0i0l AND NOT(wire_niO01O0O_dataout); + wire_nll0OiiiO_dataout <= nll0O0i0O AND NOT(wire_niO01O0O_dataout); + wire_nll0Oiili_dataout <= nll0O0iii AND NOT(wire_niO01O0O_dataout); + wire_nll0Oiill_dataout <= nll0O0iil AND NOT(wire_niO01O0O_dataout); + wire_nll0OiilO_dataout <= nll0O0iiO AND NOT(wire_niO01O0O_dataout); + wire_nll0OiiOi_dataout <= wire_nll0Oliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiiOl_dataout <= wire_nll0Olili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiiOO_dataout <= niOiOi0ii AND NOT(wire_niO01O0O_dataout); + wire_nll0Oil0i_dataout <= wire_nll0OlOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oil0l_dataout <= wire_nll0OlOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oil0O_dataout <= wire_nll0OO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oil1i_dataout <= wire_nll0OlOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oil1l_dataout <= wire_nll0OlOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oil1O_dataout <= wire_nll0OlOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oilii_dataout <= wire_nll0OO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oilil_dataout <= wire_nll0OO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiliO_dataout <= wire_nll0OO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oilli_dataout <= wire_nll0OO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oilll_dataout <= wire_nll0OO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OillO_dataout <= wire_nll0OO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OilOi_dataout <= wire_nll0OO1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OilOl_dataout <= wire_nll0OO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OilOO_dataout <= wire_nll0OO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiO0i_dataout <= wire_nll0OO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiO0l_dataout <= wire_nll0OO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiO0O_dataout <= wire_nll0OO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiO1i_dataout <= wire_nll0OO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiO1l_dataout <= wire_nll0OO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiO1O_dataout <= wire_nll0OO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOii_dataout <= wire_nll0OO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOil_dataout <= wire_nll0OO01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOiO_dataout <= wire_nll0OO00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOli_dataout <= wire_nll0OO00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOll_dataout <= wire_nll0OO00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOlO_dataout <= wire_nll0OO0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOOi_dataout <= wire_nll0OO0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOOl_dataout <= wire_nll0OO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0OiOOO_dataout <= wire_nll0OO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol00i_dataout <= wire_nll0OOiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol00l_dataout <= wire_nll0OOiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol00O_dataout <= wire_nll0OOl1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol01i_dataout <= wire_nll0OOill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol01l_dataout <= wire_nll0OOilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol01O_dataout <= wire_nll0OOiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0ii_dataout <= wire_nll0OOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0il_dataout <= wire_nll0OOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0iO_dataout <= wire_nll0OOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0li_dataout <= wire_nll0OOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0ll_dataout <= wire_nll0OOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0lO_dataout <= wire_nll0OOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0O_dataout <= wire_nlli100l_dataout OR niOO01i0l; + wire_nll0Ol0Oi_dataout <= wire_nll0OOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0Ol_dataout <= wire_nll0OOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol0OO_dataout <= wire_nll0OOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol10i_dataout <= wire_nll0OO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol10l_dataout <= wire_nll0OO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol10O_dataout <= wire_nll0OOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol11i_dataout <= wire_nll0OO0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol11l_dataout <= wire_nll0OO0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol11O_dataout <= wire_nll0OO0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1ii_dataout <= wire_nll0OOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1il_dataout <= wire_nll0OOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1iO_dataout <= wire_nll0OOi0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1li_dataout <= wire_nll0OOi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1ll_dataout <= wire_nll0OOi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1lO_dataout <= wire_nll0OOiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1Oi_dataout <= wire_nll0OOiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1Ol_dataout <= wire_nll0OOiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Ol1OO_dataout <= wire_nll0OOili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oli0i_dataout <= wire_nll0OOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oli0l_dataout <= wire_nll0OOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oli0O_dataout <= wire_nll0Oliii_dataout OR (wire_nl1000i_w_lg_nlli0ilOl36234w(0) AND (wire_nl1000i_w_lg_nlli0ilOO5658w(0) AND wire_nl1000i_w_lg_w_lg_nlli0iO1i36270w36271w(0))); + wire_nll0Oli1i_dataout <= wire_nll0OOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oli1l_dataout <= wire_nll0OOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Oli1O_dataout <= wire_nll0OOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll0Olii_dataout <= wire_nll0OOOO_dataout AND NOT(niOO01i0l); + wire_nll0Oliii_dataout <= nll0O0i1O AND NOT(niOiOi11O); + wire_nll0Oliil_dataout <= wire_nll0Olill_dataout AND NOT(niOiOi11O); + wire_nll0Olil_dataout <= wire_nlli111i_dataout AND NOT(niOO01i0l); + wire_nll0Olili_dataout <= wire_nll0OlilO_dataout OR niOiOi1il; + wire_nll0Olill_dataout <= wire_nll0OliOi_dataout OR niOiOi1il; + wire_nll0OlilO_dataout <= wire_nll0OliOl_dataout OR niOiOi1ii; + wire_nll0OliO_dataout <= wire_nlli111l_dataout AND NOT(niOO01i0l); + wire_nll0OliOi_dataout <= wire_nll0OliOO_dataout OR niOiOi1ii; + wire_nll0OliOl_dataout <= niOiOi10i OR niOiOi10O; + wire_nll0OliOO_dataout <= wire_nll0Oll1i_dataout OR niOiOi10O; + wire_nll0Oll1i_dataout <= nll0O0ill OR niOiOi10i; + wire_nll0Olli_dataout <= wire_nlli111O_dataout AND NOT(niOO01i0l); + wire_nll0Olll_dataout <= wire_nlli110i_dataout AND NOT(niOO01i0l); + wire_nll0OllO_dataout <= wire_nlli110l_dataout AND NOT(niOO01i0l); + wire_nll0OlOi_dataout <= wire_nlli110O_dataout AND NOT(niOO01i0l); + wire_nll0OlOl_dataout <= wire_nlli11ii_dataout AND NOT(niOO01i0l); + wire_nll0OlOli_dataout <= niOiOi1iO WHEN niOiOi0ii = '1' ELSE nll0O1i1l; + wire_nll0OlOll_dataout <= wire_w_lg_niOiOi0li35985w(0) WHEN niOiOi0ii = '1' ELSE nll0O0iOl; + wire_nll0OlOlO_dataout <= wire_nllii0iOO_dataout WHEN niOiOi0ii = '1' ELSE nll0O0iOO; + wire_nll0OlOO_dataout <= wire_nlli11il_dataout AND NOT(niOO01i0l); + wire_nll0OlOOi_dataout <= wire_nllii0l1i_dataout WHEN niOiOi0ii = '1' ELSE nll0O0l1i; + wire_nll0OlOOl_dataout <= wire_nllii0l1l_dataout WHEN niOiOi0ii = '1' ELSE nll0O0l1l; + wire_nll0OlOOO_dataout <= wire_nllii0l1O_dataout WHEN niOiOi0ii = '1' ELSE nll0O0l1O; + wire_nll0OO00i_dataout <= wire_nllii0Oii_dataout WHEN niOiOi0ii = '1' ELSE nll0O0Oii; + wire_nll0OO00l_dataout <= wire_nllii0Oil_dataout WHEN niOiOi0ii = '1' ELSE nll0O0Oil; + wire_nll0OO00O_dataout <= nlli0i01l WHEN niOiOi0ii = '1' ELSE nll0O0OiO; + wire_nll0OO01i_dataout <= wire_nllii0O0i_dataout WHEN niOiOi0ii = '1' ELSE nll0O0O0i; + wire_nll0OO01l_dataout <= wire_nllii0O0l_dataout WHEN niOiOi0ii = '1' ELSE nll0O0O0l; + wire_nll0OO01O_dataout <= wire_nllii0O0O_dataout WHEN niOiOi0ii = '1' ELSE nll0O0O0O; + wire_nll0OO0i_dataout <= wire_nlli11Oi_dataout AND NOT(niOO01i0l); + wire_nll0OO0ii_dataout <= nlli0i01O WHEN niOiOi0ii = '1' ELSE nll0O0Oli; + wire_nll0OO0il_dataout <= nlli0i00i WHEN niOiOi0ii = '1' ELSE nll0O0Oll; + wire_nll0OO0iO_dataout <= nlli0i00l WHEN niOiOi0ii = '1' ELSE nll0O0OlO; + wire_nll0OO0l_dataout <= wire_nlli11Ol_dataout AND NOT(niOO01i0l); + wire_nll0OO0li_dataout <= nlli0i00O WHEN niOiOi0ii = '1' ELSE nll0O0OOi; + wire_nll0OO0ll_dataout <= nlli0i0ii WHEN niOiOi0ii = '1' ELSE nll0O0OOl; + wire_nll0OO0lO_dataout <= nlli0i0il WHEN niOiOi0ii = '1' ELSE nll0O0OOO; + wire_nll0OO0O_dataout <= wire_nlli11OO_dataout OR niOO01i0l; + wire_nll0OO0Oi_dataout <= nlli0i0iO WHEN niOiOi0ii = '1' ELSE nll0Oi11i; + wire_nll0OO0Ol_dataout <= nlli0i0li WHEN niOiOi0ii = '1' ELSE nll0Oi11l; + wire_nll0OO0OO_dataout <= nlli0i0ll WHEN niOiOi0ii = '1' ELSE nll0Oi11O; + wire_nll0OO10i_dataout <= wire_nllii0lii_dataout WHEN niOiOi0ii = '1' ELSE nll0O0lii; + wire_nll0OO10l_dataout <= wire_nllii0lil_dataout WHEN niOiOi0ii = '1' ELSE nll0O0lil; + wire_nll0OO10O_dataout <= wire_nllii0liO_dataout WHEN niOiOi0ii = '1' ELSE nll0O0liO; + wire_nll0OO11i_dataout <= wire_nllii0l0i_dataout WHEN niOiOi0ii = '1' ELSE nll0O0l0i; + wire_nll0OO11l_dataout <= wire_nllii0l0l_dataout WHEN niOiOi0ii = '1' ELSE nll0O0l0l; + wire_nll0OO11O_dataout <= wire_nllii0l0O_dataout WHEN niOiOi0ii = '1' ELSE nll0O0l0O; + wire_nll0OO1i_dataout <= wire_nlli11iO_dataout AND NOT(niOO01i0l); + wire_nll0OO1ii_dataout <= wire_nllii0lli_dataout WHEN niOiOi0ii = '1' ELSE nll0O0lli; + wire_nll0OO1il_dataout <= wire_nllii0lll_dataout WHEN niOiOi0ii = '1' ELSE nll0O0lll; + wire_nll0OO1iO_dataout <= wire_nllii0llO_dataout WHEN niOiOi0ii = '1' ELSE nll0O0llO; + wire_nll0OO1l_dataout <= wire_nlli11li_dataout AND NOT(niOO01i0l); + wire_nll0OO1li_dataout <= wire_nllii0lOi_dataout WHEN niOiOi0ii = '1' ELSE nll0O0lOi; + wire_nll0OO1ll_dataout <= wire_nllii0lOl_dataout WHEN niOiOi0ii = '1' ELSE nll0O0lOl; + wire_nll0OO1lO_dataout <= wire_nllii0lOO_dataout WHEN niOiOi0ii = '1' ELSE nll0O0lOO; + wire_nll0OO1O_dataout <= wire_nlli11lO_dataout AND NOT(niOO01i0l); + wire_nll0OO1Oi_dataout <= wire_nllii0O1i_dataout WHEN niOiOi0ii = '1' ELSE nll0O0O1i; + wire_nll0OO1Ol_dataout <= wire_nllii0O1l_dataout WHEN niOiOi0ii = '1' ELSE nll0O0O1l; + wire_nll0OO1OO_dataout <= wire_nllii0O1O_dataout WHEN niOiOi0ii = '1' ELSE nll0O0O1O; + wire_nll0OOi0i_dataout <= nlli0i0OO WHEN niOiOi0ii = '1' ELSE nll0Oi1ii; + wire_nll0OOi0l_dataout <= nlli0ii1i WHEN niOiOi0ii = '1' ELSE nll0Oi1il; + wire_nll0OOi0O_dataout <= nlli0ii1l WHEN niOiOi0ii = '1' ELSE nll0Oi1iO; + wire_nll0OOi1i_dataout <= nlli0i0lO WHEN niOiOi0ii = '1' ELSE nll0Oi10i; + wire_nll0OOi1l_dataout <= nlli0i0Oi WHEN niOiOi0ii = '1' ELSE nll0Oi10l; + wire_nll0OOi1O_dataout <= nlli0i0Ol WHEN niOiOi0ii = '1' ELSE nll0Oi10O; + wire_nll0OOii_dataout <= wire_nlli100i_dataout AND NOT(niOO01i0l); + wire_nll0OOiii_dataout <= nlli0ii1O WHEN niOiOi0ii = '1' ELSE nll0Oi1li; + wire_nll0OOiil_dataout <= nlli0ii0i WHEN niOiOi0ii = '1' ELSE nll0Oi1ll; + wire_nll0OOiiO_dataout <= nlli0ii0l WHEN niOiOi0ii = '1' ELSE nll0Oi1lO; + wire_nll0OOil_dataout <= wire_nlli100O_dataout AND NOT(niOO01i0l); + wire_nll0OOili_dataout <= nlli0ii0O WHEN niOiOi0ii = '1' ELSE nll0Oi1Oi; + wire_nll0OOill_dataout <= nlli0iiii WHEN niOiOi0ii = '1' ELSE nll0Oi1Ol; + wire_nll0OOilO_dataout <= nlli0iiil WHEN niOiOi0ii = '1' ELSE nll0Oi1OO; + wire_nll0OOiO_dataout <= wire_nlli10ii_dataout AND NOT(niOO01i0l); + wire_nll0OOiOi_dataout <= nlli0iiiO WHEN niOiOi0ii = '1' ELSE nll0Oi01i; + wire_nll0OOiOl_dataout <= nlli0iili WHEN niOiOi0ii = '1' ELSE nll0Oi01l; + wire_nll0OOiOO_dataout <= nlli0iill WHEN niOiOi0ii = '1' ELSE nll0Oi01O; + wire_nll0OOl0i_dataout <= nlli0iiOO WHEN niOiOi0ii = '1' ELSE nll0Oi0ii; + wire_nll0OOl0l_dataout <= nlli0il1i WHEN niOiOi0ii = '1' ELSE nll0Oi0il; + wire_nll0OOl0O_dataout <= nlli0il1l WHEN niOiOi0ii = '1' ELSE nll0Oi0iO; + wire_nll0OOl1i_dataout <= nlli0iilO WHEN niOiOi0ii = '1' ELSE nll0Oi00i; + wire_nll0OOl1l_dataout <= nlli0iiOi WHEN niOiOi0ii = '1' ELSE nll0Oi00l; + wire_nll0OOl1O_dataout <= nlli0iiOl WHEN niOiOi0ii = '1' ELSE nll0Oi00O; + wire_nll0OOli_dataout <= wire_nlli10il_dataout AND NOT(niOO01i0l); + wire_nll0OOlii_dataout <= nlli0il1O WHEN niOiOi0ii = '1' ELSE nll0Oi0li; + wire_nll0OOlil_dataout <= nlli0il0i WHEN niOiOi0ii = '1' ELSE nll0Oi0ll; + wire_nll0OOliO_dataout <= nlli0il0l WHEN niOiOi0ii = '1' ELSE nll0Oi0lO; + wire_nll0OOll_dataout <= wire_nlli11ll_dataout AND NOT(niOO01i0l); + wire_nll0OOlli_dataout <= nlli0il0O WHEN niOiOi0ii = '1' ELSE nll0Oi0Oi; + wire_nll0OOlll_dataout <= nlli0ilii WHEN niOiOi0ii = '1' ELSE nll0Oi0Ol; + wire_nll0OOllO_dataout <= nlli0ilil WHEN niOiOi0ii = '1' ELSE nll0Oi0OO; + wire_nll0OOlO_dataout <= wire_nlli101i_dataout AND NOT(niOO01i0l); + wire_nll0OOlOi_dataout <= nlli0iliO WHEN niOiOi0ii = '1' ELSE nll0Oii1i; + wire_nll0OOlOl_dataout <= nlli0illi WHEN niOiOi0ii = '1' ELSE nll0Oii1l; + wire_nll0OOlOO_dataout <= nlli0illl WHEN niOiOi0ii = '1' ELSE nll0Oii1O; + wire_nll0OOOi_dataout <= wire_nlli101l_dataout AND NOT(niOO01i0l); + wire_nll0OOOl_dataout <= wire_nlli101O_dataout AND NOT(niOO01i0l); + wire_nll0OOOO_dataout <= wire_nlli10li_o WHEN niOO01i0i = '1' ELSE nll0O0lO; + wire_nll0OOOOO_dataout <= wire_nlli1110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10000i_dataout <= wire_nll100l0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oill; + wire_nll10000l_dataout <= wire_nll100lii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11OilO; + wire_nll10000O_dataout <= wire_nll100lil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11OiOi; + wire_nll10001i_dataout <= wire_nll100l1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oiil; + wire_nll10001l_dataout <= wire_nll100l0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11OiiO; + wire_nll10001O_dataout <= wire_nll100l0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oili; + wire_nll1000i_dataout <= wire_nll011OO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O01i_dataout; + wire_nll1000ii_dataout <= wire_nll100liO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11OiOl; + wire_nll1000il_dataout <= wire_nll100lli_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11OiOO; + wire_nll1000iO_dataout <= wire_nll100lll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Ol1i; + wire_nll1000l_dataout <= wire_nll0101i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O01l_dataout; + wire_nll1000li_dataout <= wire_nll100llO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Ol1l; + wire_nll1000ll_dataout <= wire_nll100lOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Ol1O; + wire_nll1000lO_dataout <= wire_nll100lOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Ol0i; + wire_nll1000O_dataout <= wire_nll0101l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O01O_dataout; + wire_nll1000Oi_dataout <= wire_nll100lOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Ol0l; + wire_nll1000Ol_dataout <= wire_nll100O1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Ol0O; + wire_nll1000OO_dataout <= wire_nll100O1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Olii; + wire_nll10010i_dataout <= wire_nll100i0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0ll; + wire_nll10010l_dataout <= wire_nll100iii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0lO; + wire_nll10010O_dataout <= wire_nll100iil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0Oi; + wire_nll10011i_dataout <= (nll11OllO XOR (nll11Olli XOR (nll11OliO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11OiiO XOR (nll11Oi0l XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0Ol XOR (nlli0i0Ol XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR (nlli0ilil XOR niOiO00iO))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0il; + wire_nll10011l_dataout <= (nll11Olll XOR (nll11Olli XOR (nll11OliO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Oili XOR (nll11Oi0O XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11O0OO XOR (nlli0i0Oi XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR (nlli0iliO XOR niOiO00ll)))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0iO; + wire_nll10011O_dataout <= (nll11OllO XOR (nll11Olll XOR (nll11Olli XOR (nll11OliO XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Oill XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1i XOR (nlli0i0lO XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR (nlli0ilil XOR niOiO01il)))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0li; + wire_nll1001i_dataout <= wire_nll011lO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1Oi_dataout; + wire_nll1001ii_dataout <= wire_nll100iiO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0Ol; + wire_nll1001il_dataout <= wire_nll100ili_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0OO; + wire_nll1001iO_dataout <= wire_nll100ill_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oi1i; + wire_nll1001l_dataout <= wire_nll011Oi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1Ol_dataout; + wire_nll1001li_dataout <= wire_nll100ilO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oi1l; + wire_nll1001ll_dataout <= wire_nll100iOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oi1O; + wire_nll1001lO_dataout <= wire_nll100iOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oi0i; + wire_nll1001O_dataout <= wire_nll011Ol_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1OO_dataout; + wire_nll1001Oi_dataout <= wire_nll100iOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oi0l; + wire_nll1001Ol_dataout <= wire_nll100l1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oi0O; + wire_nll1001OO_dataout <= wire_nll100l1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Oiii; + wire_nll100i0i_dataout <= wire_nll100O0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Olll; + wire_nll100i0l_dataout <= wire_nll100Oii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11OllO; + wire_nll100i0O_dataout <= (NOT (wire_nllii1Oll_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii011l_dataout XOR wire_nllii1OOO_dataout))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olli XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oi1i XOR (nll11O0Oi XOR (nll11O0ll XOR (wire_nllii0lii_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0Oil_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR niOiO01iO))))))))))))))))))))))))))))))))))))))); + wire_nll100i1i_dataout <= wire_nll100O1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Olil; + wire_nll100i1l_dataout <= wire_nll100O0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11OliO; + wire_nll100i1O_dataout <= wire_nll100O0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11Olli; + wire_nll100ii_dataout <= wire_nll0101O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O00i_dataout; + wire_nll100iii_dataout <= (wire_nllii1Oll_dataout XOR (wire_nllii1Oli_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii011i_dataout XOR (wire_nllii1OOO_dataout XOR wire_nllii1OOl_dataout))))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olll XOR (nll11OliO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol1l XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0lO XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (nlli0i0iO XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOi XOR niOiO01Oi))))))))))))))))))))))))))))))))))))))))))); + wire_nll100iil_dataout <= (NOT (wire_nllii1Oll_dataout XOR (wire_nllii1Oli_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii1OOl_dataout XOR wire_nllii1OOi_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11Olil XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11Oiil XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0ll XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0ii0O XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iill XOR niOiO01Ol))))))))))))))))))))))))))))))))))))))))); + wire_nll100iiO_dataout <= (NOT (wire_nllii1Oli_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii011l_dataout XOR (wire_nllii1OOi_dataout XOR wire_nllii1OlO_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11OliO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiiO XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0lO XOR (nll11O0ll XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0ii0l XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR (nlli0iliO XOR niOiO000i))))))))))))))))))))))))))))))))))))))))))); + wire_nll100il_dataout <= wire_nll0100i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O00l_dataout; + wire_nll100ili_dataout <= (NOT (wire_nllii1Oll_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011i_dataout XOR (wire_nllii1OOO_dataout XOR wire_nllii1OlO_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0O XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oill XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0lO XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0illi XOR (nlli0iliO XOR niOiO01li))))))))))))))))))))))))))))))))))))))))))))); + wire_nll100ill_dataout <= (NOT (wire_nllii1Oll_dataout XOR (wire_nllii1Oli_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii011l_dataout XOR wire_nllii1OOl_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olli XOR (nll11Olil XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1i XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i0iO XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR niOiO01OO)))))))))))))))))))))))))))))))))))))))))))); + wire_nll100ilO_dataout <= (NOT (wire_nllii1Oli_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011i_dataout XOR wire_nllii1OOi_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11OliO XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oiii XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1l XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0il XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO01ll))))))))))))))))))))))))))))))))))))))))))); + wire_nll100iO_dataout <= wire_nll0100l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O00O_dataout; + wire_nll100iOi_dataout <= (wire_nllii1Oll_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011l_dataout XOR wire_nllii1OlO_dataout))))))) WHEN niOiOii1O = '1' ELSE (nll11OliO XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11Oill XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oiii XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11Oi1O XOR (nll11Oi1i XOR (nll11O0Oi XOR (nll11O0ll XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR nlli0ilii))))))))))))))))))))))))))))))))))))))))))))))))))); + wire_nll100iOl_dataout <= (wire_nllii1Oll_dataout XOR (wire_nllii1Oli_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011l_dataout XOR (wire_nllii011i_dataout XOR wire_nllii1OOO_dataout))))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11OliO XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol1O XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oiii XOR (nll11Oi0O XOR (nll11Oi0i XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0lO XOR (nll11O0ll XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0illi XOR niOiO01lO)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nll100iOO_dataout <= (wire_nllii1Oli_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii011i_dataout XOR (wire_nllii1OOO_dataout XOR wire_nllii1OOl_dataout))))))) WHEN niOiOii1O = '1' ELSE (nll11Olli XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0i XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11Oill XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0lO XOR (nll11O0ll XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0iliO XOR niOiO000l)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nll100l0i_dataout <= (NOT (wire_nllii1Oli_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii011l_dataout XOR (wire_nllii1OOl_dataout XOR wire_nllii1OOi_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oill XOR (nll11Oiii XOR (nll11Oi0O XOR (nll11O0ll XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0il XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR niOiO001i))))))))))))))))))))))))))))))))))))))))); + wire_nll100l0l_dataout <= (NOT (wire_nllii1OiO_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011i_dataout XOR (wire_nllii1OOi_dataout XOR wire_nllii1OlO_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olli XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oiil XOR (nll11Oiii XOR (nll11O0lO XOR (nll11O0ll XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0ii XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR niOiO001l))))))))))))))))))))))))))))))))))))))))); + wire_nll100l0O_dataout <= (wire_nllii1Oil_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii1OOO_dataout XOR wire_nllii1OlO_dataout))))))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11OliO XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOl XOR (nll11OiOi XOR (nll11OiiO XOR (nll11Oiil XOR (nll11O0Oi XOR (nll11O0lO XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i0iO XOR (nlli0i00O XOR (nlli0i01O XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO0i1i))))))))))))))))))))))))))))))))))))))))); + wire_nll100l1i_dataout <= (NOT (wire_nllii1Oll_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii1OOl_dataout XOR wire_nllii1OOi_dataout))))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olll XOR (nll11OliO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1i XOR (nll11OiOl XOR (nll11Oi0O XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0lO XOR (nll11O0ll XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0l_dataout XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iill XOR niOiO01Oi))))))))))))))))))))))))))))))))))))))); + wire_nll100l1l_dataout <= (wire_nllii1Oll_dataout XOR (wire_nllii1Oli_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii1OOO_dataout XOR (wire_nllii1OOi_dataout XOR wire_nllii1OlO_dataout))))))) WHEN niOiOii1O = '1' ELSE (nll11Olil XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11O0OO XOR (nll11O0lO XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO01Ol)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nll100l1O_dataout <= (wire_nllii1Oll_dataout XOR (wire_nllii1Oli_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii1OOO_dataout XOR (wire_nllii1OOl_dataout XOR wire_nllii1OlO_dataout))))))))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olli XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oili XOR (nll11Oi0O XOR (nll11Oi0l XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i0iO XOR (nlli0i00O XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR niOiO01OO)))))))))))))))))))))))))))))))))))))))))))); + wire_nll100li_dataout <= wire_nll0100O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0ii_dataout; + wire_nll100lii_dataout <= (NOT (wire_nllii1Oll_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii1OOO_dataout XOR wire_nllii1OOl_dataout)))))) WHEN niOiOii1O = '1' ELSE (nll11Ol0O XOR (nll11Ol0l XOR (nll11OiOO XOR (nll11OilO XOR (nll11Oill XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oi1i XOR (nll11O0Ol XOR (nll11O0ll XOR (wire_nllii0lii_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOO XOR (nlli0illl XOR nlli0illi))))))))))))))))))))))))))))))))); + wire_nll100lil_dataout <= (NOT (wire_nllii1Oli_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii1OOl_dataout XOR wire_nllii1OOi_dataout)))))) WHEN niOiOii1O = '1' ELSE (nll11Olii XOR (nll11Ol0O XOR (nll11Ol1i XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oi1l XOR (nll11O0OO XOR (nll11O0lO XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0illi XOR nlli0iliO))))))))))))))))))))))))))))))))); + wire_nll100liO_dataout <= (NOT (wire_nllii1OiO_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii011l_dataout XOR (wire_nllii1OOi_dataout XOR wire_nllii1OlO_dataout)))))) WHEN niOiOii1O = '1' ELSE (nll11Olil XOR (nll11Olii XOR (nll11Ol1l XOR (nll11OiOl XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oili XOR (nll11Oi1O XOR (nll11Oi1i XOR (nll11O0Oi XOR (nll11O0ll XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOi XOR niOiO001O))))))))))))))))))))))))))))))))); + wire_nll100ll_dataout <= wire_nll010ii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0il_dataout; + wire_nll100lli_dataout <= (wire_nllii1Oil_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011i_dataout XOR wire_nllii1OlO_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11OliO XOR (nll11Olil XOR (nll11Ol1O XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oi0i XOR (nll11Oi1l XOR (nll11O0Ol XOR (nll11O0lO XOR (nll11O0ll XOR (wire_nllii0l0i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR niOiO000i)))))))))))))))))))))))))))))))))); + wire_nll100lll_dataout <= (NOT (wire_nllii1Oii_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011O_dataout XOR wire_nllii1OOO_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11Olli XOR (nll11OliO XOR (nll11Ol0i XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oi0l XOR (nll11Oi1O XOR (nll11O0OO XOR (nll11O0Oi XOR (nll11O0lO XOR (wire_nllii0l1O_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i01O XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iill XOR niOiO000l)))))))))))))))))))))))))))))))))); + wire_nll100llO_dataout <= (NOT (wire_nllii1O0O_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii011l_dataout XOR wire_nllii1OOl_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11Olli XOR (nll11Ol0l XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOi XOR (nll11Oi0O XOR (nll11Oi0i XOR (nll11Oi1i XOR (nll11O0Ol XOR (nll11O0Oi XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0iili XOR (nlli0iiil XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0illl XOR niOiO000O)))))))))))))))))))))))))))))))))); + wire_nll100lO_dataout <= wire_nll010il_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0iO_dataout; + wire_nll100lOi_dataout <= (wire_nllii1Oll_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii011i_dataout XOR (wire_nllii1OOO_dataout XOR wire_nllii1OOi_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11Olli XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1i XOR (nll11OilO XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0Oi XOR (wire_nllii0lii_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOl XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR niOiO00ii))))))))))))))))))))))))))))))))))))))))))))))); + wire_nll100lOl_dataout <= (NOT (wire_nllii1Oll_dataout XOR (wire_nllii1Oli_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii1OOl_dataout XOR wire_nllii1OlO_dataout)))))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11OliO XOR (nll11Olil XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oili XOR (nll11Oi0O XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0Oi XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR niOiO00il))))))))))))))))))))))))))))))))))))))))))); + wire_nll100lOO_dataout <= (wire_nllii1Oli_dataout XOR (wire_nllii1OiO_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii011l_dataout XOR wire_nllii1OOi_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olli XOR (nll11OliO XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oill XOR (nll11Oiii XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0ll XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l0l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0Oil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i01O XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR niOiO00iO)))))))))))))))))))))))))))))))))))))))))))); + wire_nll100O0i_dataout <= (wire_nllii1OiO_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii010i_dataout XOR wire_nllii1OOO_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olll XOR (nll11Olli XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11O0lO XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lll_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i01O XOR (nlli0ii1i XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR (nlli0ilil XOR niOiO00Oi))))))))))))))))))))))))))))))))))))))))))); + wire_nll100O0l_dataout <= (wire_nllii1Oil_dataout XOR (wire_nllii1O0l_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii011O_dataout XOR wire_nllii1OOl_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olll XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11O0Oi XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0lli_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0i0OO XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iill XOR (nlli0illi XOR (nlli0iliO XOR niOiO00Ol))))))))))))))))))))))))))))))))))))))))); + wire_nll100O0O_dataout <= (wire_nllii1Oii_dataout XOR (wire_nllii1O0i_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011l_dataout XOR wire_nllii1OOi_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olli XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OilO XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oiii XOR (nll11Oi0O XOR (nll11O0Ol XOR (nll11O0ll XOR (wire_nllii0l1O_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0liO_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR niOiO00OO)))))))))))))))))))))))))))))))))))))); + wire_nll100O1i_dataout <= (wire_nllii1OiO_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011i_dataout XOR wire_nllii1OlO_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11Olli XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oiil XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0lO XOR (wire_nllii0l0l_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0Oii_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1l_dataout XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0illl XOR (nlli0illi XOR niOiO00li)))))))))))))))))))))))))))))))))))))))))); + wire_nll100O1l_dataout <= (wire_nllii1Oll_dataout XOR (wire_nllii1Oil_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii011l_dataout XOR wire_nllii1O0l_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11Olli XOR (nll11OliO XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1i XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oill XOR (nll11Oiil XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11Oi1O XOR (nll11Oi1l XOR (wire_nllii0lii_dataout XOR (wire_nllii0l0i_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1i_dataout XOR (wire_nllii0lOi_dataout XOR (wire_nllii0O0O_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1l_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00l XOR (nlli0i01l XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illi XOR niOiO00ll))))))))))))))))))))))))))))))))))))))))))); + wire_nll100O1O_dataout <= (wire_nllii1Oli_dataout XOR (wire_nllii1Oii_dataout XOR (wire_nllii1O0O_dataout XOR (wire_nllii011i_dataout XOR wire_nllii1O0i_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11OllO XOR (nll11Olll XOR (nll11Olli XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1l XOR (nll11OiOl XOR (nll11OiOi XOR (nll11OilO XOR (nll11OiiO XOR (nll11Oiii XOR (nll11Oi0O XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11O0ll XOR (wire_nllii0l0O_dataout XOR (wire_nllii0l1O_dataout XOR (wire_nllii0l1l_dataout XOR (wire_nllii0iOO_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0O0l_dataout XOR (wire_nllii0O0i_dataout XOR (wire_nllii0O1O_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i0ii XOR (nlli0i00O XOR (nlli0i00i XOR (nlli0ii1l XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0l XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0illl XOR niOiO00lO))))))))))))))))))))))))))))))))))))))))))); + wire_nll100Oi_dataout <= wire_nll010iO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0li_dataout; + wire_nll100Oii_dataout <= (wire_nllii1O0O_dataout XOR (wire_nllii010i_dataout XOR (wire_nllii011O_dataout XOR (wire_nllii011i_dataout XOR wire_nllii1OlO_dataout)))) WHEN niOiOii1O = '1' ELSE (nll11Olll XOR (nll11OliO XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oiii XOR (nll11O0OO XOR (nll11O0lO XOR (wire_nllii0l1l_dataout XOR (wire_nllii0lOO_dataout XOR (wire_nllii0lOl_dataout XOR (wire_nllii0llO_dataout XOR (wire_nllii0lil_dataout XOR (wire_nllii0O1i_dataout XOR (nlli0i0iO XOR (nlli0i0il XOR (nlli0i00O XOR (nlli0i00l XOR (nlli0i00i XOR (nlli0i01O XOR (nlli0i01l XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR niOiO0i1i))))))))))))))))))))))))))))))))))))); + wire_nll100Ol_dataout <= wire_nll010li_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0ll_dataout; + wire_nll100OO_dataout <= wire_nll010ll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0lO_dataout; + wire_nll10100i_dataout <= wire_nll1001il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10100l_dataout <= wire_nll1001iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10100O_dataout <= wire_nll1001li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10101i_dataout <= wire_nll10010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10101l_dataout <= wire_nll10010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10101O_dataout <= wire_nll1001ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010i_dataout <= wire_nll1OOOO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O11i_dataout; + wire_nll1010ii_dataout <= wire_nll1001ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010il_dataout <= wire_nll1001lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010iO_dataout <= wire_nll1001Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010l_dataout <= wire_nll0111i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O11l_dataout; + wire_nll1010li_dataout <= wire_nll1001Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010ll_dataout <= wire_nll1001OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010lO_dataout <= wire_nll10001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010O_dataout <= wire_nll0111l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O11O_dataout; + wire_nll1010Oi_dataout <= wire_nll10001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010Ol_dataout <= wire_nll10001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1010OO_dataout <= wire_nll10000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10110i_dataout <= wire_nll101Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10110l_dataout <= wire_nll101OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10110O_dataout <= wire_nll101Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10111i_dataout <= wire_nll101O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10111l_dataout <= wire_nll101O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll10111O_dataout <= wire_nll101Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011i_dataout <= wire_nll1OOlO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOOi_dataout; + wire_nll1011ii_dataout <= wire_nll101Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011il_dataout <= wire_nll101OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011iO_dataout <= wire_nll101OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011l_dataout <= wire_nll1OOOi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOOl_dataout; + wire_nll1011li_dataout <= wire_nll101OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011ll_dataout <= wire_nll101OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011lO_dataout <= wire_nll10011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011O_dataout <= wire_nll1OOOl_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOOO_dataout; + wire_nll1011Oi_dataout <= wire_nll10011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011Ol_dataout <= wire_nll10011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1011OO_dataout <= wire_nll10010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101i0i_dataout <= wire_nll1000il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101i0l_dataout <= wire_nll1000iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101i0O_dataout <= wire_nll1000li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101i1i_dataout <= wire_nll10000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101i1l_dataout <= wire_nll10000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101i1O_dataout <= wire_nll1000ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101ii_dataout <= wire_nll0111O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O10i_dataout; + wire_nll101iii_dataout <= wire_nll1000ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101iil_dataout <= wire_nll1000lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101iiO_dataout <= wire_nll1000Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101il_dataout <= wire_nll0110i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O10l_dataout; + wire_nll101ili_dataout <= wire_nll1000Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101ill_dataout <= wire_nll1000OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101ilO_dataout <= wire_nll100i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101iO_dataout <= wire_nll0110l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O10O_dataout; + wire_nll101iOi_dataout <= wire_nll100i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101iOl_dataout <= wire_nll100i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101iOO_dataout <= wire_nll100i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101l0i_dataout <= (nll11OllO XOR (nll11Olll XOR (nll11Olii XOR (nll11Ol0l XOR (nll11OiOl XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0Oi XOR (nll11O0lO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0illl XOR (nlli0iliO XOR niOiO011l)))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11lOll; + wire_nll101l0l_dataout <= (nll11OllO XOR (nll11Olil XOR (nll11Ol0O XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oili XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0lO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0illi XOR niOiO01li)))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11lOlO; + wire_nll101l0O_dataout <= (nll11OllO XOR (nll11Olll XOR (nll11Olli XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11Oill XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0i XOR (nll11Oi1l XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0illl XOR (nlli0illi XOR niOiO00Oi))))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11lOOi; + wire_nll101l1i_dataout <= wire_nll100i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll101l1l_dataout <= (nll11OllO XOR (nll11Olll XOR (nll11Olli XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11OilO XOR (nll11Oiil XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11Oi1l XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0illl XOR (nlli0illi XOR niOiO00lO))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll100Oil; + wire_nll101l1O_dataout <= (nll11OliO XOR (nll11Olil XOR (nll11Ol0l XOR (nll11OiOi XOR (nll11OilO XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0lO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0illl XOR niOiO000i)))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11lOli; + wire_nll101li_dataout <= wire_nll0110O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1ii_dataout; + wire_nll101lii_dataout <= (nll11Olli XOR (nll11OliO XOR (nll11Ol0l XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiiO XOR (nll11Oi0O XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0lO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0illl XOR niOiO000l)))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11lOOl; + wire_nll101lil_dataout <= (nll11Olll XOR (nll11Olli XOR (nll11Ol0O XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11Oili XOR (nll11Oiii XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Oi XOR (nll11O0lO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii0i XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illi XOR niOiO000O)))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11lOOO; + wire_nll101liO_dataout <= (nll11Olli XOR (nll11OliO XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11OilO XOR (nll11Oill XOR (nll11Oi0O XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1i XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiil XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR niOiO000l)))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O11i; + wire_nll101ll_dataout <= wire_nll011ii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1il_dataout; + wire_nll101lli_dataout <= (nll11OllO XOR (nll11OliO XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11OiOi XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0O XOR (nll11Oi0i XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0lO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0iili XOR (nlli0iiil XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0il1l XOR (nlli0iilO XOR (nlli0iill XOR niOiO011O)))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O11l; + wire_nll101lll_dataout <= (nll11Olli XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11OiOl XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Oi XOR (nll11O0lO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1i XOR (nlli0iill XOR (nlli0illl XOR nlli0il0O))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O11O; + wire_nll101llO_dataout <= (nll11OllO XOR (nll11Olli XOR (nll11OliO XOR (nll11Olii XOR (nll11OiOO XOR (nll11OilO XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oi0l XOR (nll11Oi1i XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0iiOO XOR niOiO01iO)))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O10i; + wire_nll101lO_dataout <= wire_nll011il_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1iO_dataout; + wire_nll101lOi_dataout <= (nll11OllO XOR (nll11OliO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1i XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oill XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oi0l XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0lO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOl XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR niOiO01lO))))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O10l; + wire_nll101lOl_dataout <= (nll11OllO XOR (nll11Olll XOR (nll11Olil XOR (nll11Ol0l XOR (nll11Ol1l XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oi0l XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Oi XOR (nll11O0lO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOi XOR (nlli0illl XOR niOiO010i))))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O10O; + wire_nll101lOO_dataout <= (nll11OllO XOR (nll11OliO XOR (nll11Ol0O XOR (nll11Ol1O XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oi0O XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0Ol XOR (nll11O0Oi XOR (nll11O0lO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iilO XOR (nlli0illi XOR niOiO011O)))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1ii; + wire_nll101O0i_dataout <= (nll11OllO XOR (nll11Olll XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1i XOR (nll11OiOl XOR (nll11Oili XOR (nll11OiiO XOR (nll11Oi0l XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0lO XOR (nlli0ii1i XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii0i XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illi XOR niOiO010i))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1ll; + wire_nll101O0l_dataout <= (nll11OllO XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1l XOR (nll11OiOO XOR (nll11Oill XOR (nll11Oili XOR (nll11Oi0O XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0Oi XOR (nlli0i0OO XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0illl XOR niOiO010O))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1lO; + wire_nll101O0O_dataout <= (nll11Olli XOR (nll11Olil XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11Ol1i XOR (nll11OilO XOR (nll11Oill XOR (nll11Oiii XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11O0Ol XOR (nlli0i0Ol XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR niOiO01ii)))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1Oi; + wire_nll101O1i_dataout <= (nll11Olli XOR (nll11Olii XOR (nll11Ol0i XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oili XOR (nll11Oiii XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1l XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0Oi XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii0i XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iill XOR (nlli0iliO XOR nlli0il0O))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1il; + wire_nll101O1l_dataout <= (nll11Olll XOR (nll11Olil XOR (nll11Ol0l XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oill XOR (nll11Oiil XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11Oi1O XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0Ol XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0illl XOR (nlli0ilil XOR nlli0il0l))))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1iO; + wire_nll101O1O_dataout <= (nll11Olll XOR (nll11Olli XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11OiOO XOR (nll11OiOi XOR (nll11OiiO XOR (nll11Oiil XOR (nll11Oi0i XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0iili XOR (nlli0ii0O XOR (nlli0ii0l XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR niOiO00li))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1li; + wire_nll101Oi_dataout <= wire_nll011iO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1li_dataout; + wire_nll101Oii_dataout <= (nll11Olll XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0i XOR (nll11Ol1l XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oiil XOR (nll11Oi0l XOR (nll11Oi0i XOR (nll11O0OO XOR (nlli0i0Oi XOR (nlli0iili XOR (nlli0iiiO XOR (nlli0ii0O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOi XOR niOiO001i))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1Ol; + wire_nll101Oil_dataout <= (nll11OllO XOR (nll11Olli XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11OiOl XOR (nll11OiOi XOR (nll11OiiO XOR (nll11Oi0O XOR (nll11Oi0l XOR (nll11Oi1i XOR (nlli0i0lO XOR (nlli0iiiO XOR (nlli0iiil XOR (nlli0ii0l XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iilO XOR niOiO00OO))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O1OO; + wire_nll101OiO_dataout <= (nll11OllO XOR (nll11Olli XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OilO XOR (nll11Oili XOR (nll11Oiil XOR (nll11Oiii XOR (nll11Oi0l XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0iiiO XOR (nlli0iiii XOR (nlli0ii0O XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1i XOR (nlli0iiOO XOR niOiO001l)))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O01i; + wire_nll101Ol_dataout <= wire_nll011li_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1ll_dataout; + wire_nll101Oli_dataout <= (nll11OllO XOR (nll11Olli XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oill XOR (nll11OiiO XOR (nll11Oi0l XOR (nll11Oi1l XOR (nll11O0lO XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0ii1i XOR (nlli0i0ll XOR (nlli0iiiO XOR (nlli0ii0l XOR (nlli0ii1O XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0iiOO XOR (nlli0iiOl XOR niOiO010l)))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O01l; + wire_nll101Oll_dataout <= (nll11Olll XOR (nll11OliO XOR (nll11Olil XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOl XOR (nll11OiOi XOR (nll11OilO XOR (nll11Oili XOR (nll11Oi0O XOR (nll11Oi1O XOR (nll11O0Oi XOR (nll11O0lO XOR (nlli0ii1i XOR (nlli0i0OO XOR (nlli0i0li XOR (nlli0iiil XOR (nlli0ii0i XOR (nlli0il1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOl XOR (nlli0iiOi XOR niOiO00il))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O01O; + wire_nll101OlO_dataout <= (nll11OllO XOR (nll11Olli XOR (nll11OliO XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11OiOO XOR (nll11OiOl XOR (nll11OiOi XOR (nll11Oill XOR (nll11Oiii XOR (nll11Oi0i XOR (nll11O0Ol XOR (nll11O0Oi XOR (nlli0i0OO XOR (nlli0i0Ol XOR (nlli0iili XOR (nlli0iiii XOR (nlli0ii1O XOR (nlli0il1l XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOi XOR (nlli0iilO XOR niOiO00iO))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O00i; + wire_nll101OO_dataout <= wire_nll011ll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O1lO_dataout; + wire_nll101OOi_dataout <= (nll11OllO XOR (nll11OliO XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1O XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11OiOl XOR (nll11Oi0O XOR (nll11Oi1l XOR (nll11O0OO XOR (nll11O0Ol XOR (nll11O0ll XOR (nlli0ii1l XOR (nlli0i0Ol XOR (nlli0i0Oi XOR (nlli0i0ll XOR (nlli0iiil XOR (nlli0il1i XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iilO XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR niOiO010O))))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O00l; + wire_nll101OOl_dataout <= (nll11Olli XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol0i XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11OiOO XOR (nll11Oiii XOR (nll11Oi1O XOR (nll11Oi1i XOR (nll11O0OO XOR (nll11O0lO XOR (nlli0ii1i XOR (nlli0i0Oi XOR (nlli0i0lO XOR (nlli0i0li XOR (nlli0iiii XOR (nlli0iiOO XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iill XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR niOiO01ii)))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O00O; + wire_nll101OOO_dataout <= (nll11Olll XOR (nll11OliO XOR (nll11Olil XOR (nll11Olii XOR (nll11Ol0O XOR (nll11Ol0l XOR (nll11Ol1O XOR (nll11Ol1l XOR (nll11Ol1i XOR (nll11Oiil XOR (nll11Oi0i XOR (nll11Oi1l XOR (nll11Oi1i XOR (nll11O0Oi XOR (nlli0i0OO XOR (nlli0i0lO XOR (nlli0i0ll XOR (nlli0iili XOR (nlli0ii0O XOR (nlli0iiOl XOR (nlli0iiOi XOR (nlli0iilO XOR (nlli0illl XOR (nlli0illi XOR (nlli0iliO XOR niOiO00il))))))))))))))))))))))))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll11O0ii; + wire_nll10i0i_dataout <= wire_nll010OO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oi1i_dataout; + wire_nll10i0l_dataout <= wire_nll01i1i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oi1l_dataout; + wire_nll10i0O_dataout <= wire_nll01i1l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oi1O_dataout; + wire_nll10i1i_dataout <= wire_nll010lO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0Oi_dataout; + wire_nll10i1l_dataout <= wire_nll010Oi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0Ol_dataout; + wire_nll10i1O_dataout <= wire_nll010Ol_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1O0OO_dataout; + wire_nll10iii_dataout <= wire_nll01i1O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oi0i_dataout; + wire_nll10iil_dataout <= wire_nll01i0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oi0l_dataout; + wire_nll10iiO_dataout <= wire_nll01i0l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oi0O_dataout; + wire_nll10ili_dataout <= wire_nll01i0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oiii_dataout; + wire_nll10ill_dataout <= wire_nll01iii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oiil_dataout; + wire_nll10ilO_dataout <= wire_nll01iil_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1OiiO_dataout; + wire_nll10iOi_dataout <= wire_nll01iiO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1Oili_dataout; + wire_nll10iOl_dataout <= wire_nll1iO1O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10iOO_dataout <= wire_nll1iO0i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10l0i_dataout <= wire_nll1iOil_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10l0l_dataout <= wire_nll1iOiO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10l0O_dataout <= wire_nll1iOli_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10l1i_dataout <= wire_nll1iO0l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10l1l_dataout <= wire_nll1iO0O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10l1O_dataout <= wire_nll1iOii_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10lii_dataout <= wire_nll1iOll_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10lil_dataout <= wire_nll1iOlO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10liO_dataout <= wire_nll1iOOi_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10lli_dataout <= wire_nll1iOOl_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10lll_dataout <= wire_nll1iOOO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10llO_dataout <= wire_nll1l11i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10lOi_dataout <= wire_nll1l11l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10lOl_dataout <= wire_nll1l11O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10lOO_dataout <= wire_nll1l10i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10O0i_dataout <= wire_nll1l1il_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10O0l_dataout <= wire_nll1l1iO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10O0O_dataout <= wire_nll1l1li_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10O1i_dataout <= wire_nll1l10l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10O1l_dataout <= wire_nll1l10O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10O1O_dataout <= wire_nll1l1ii_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10Oii_dataout <= wire_nll1l1ll_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10Oil_dataout <= wire_nll1l1lO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10OiO_dataout <= wire_nll1l1Oi_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10Oli_dataout <= wire_nll1l1Ol_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10Oll_dataout <= wire_nll1l1OO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10OlO_dataout <= wire_nll1l01i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10OOi_dataout <= wire_nll1l01l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10OOl_dataout <= wire_nll1l01O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll10OOO_dataout <= wire_nll1l00i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1100i_dataout <= wire_nll101lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1100l_dataout <= wire_nll101Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1100O_dataout <= wire_nll101Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1101i_dataout <= wire_nll101iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1101l_dataout <= wire_nll101li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1101O_dataout <= wire_nll101ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110ii_dataout <= wire_nll101OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110il_dataout <= wire_nll1001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110iO_dataout <= wire_nll1001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110li_dataout <= wire_nll1001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110ll_dataout <= wire_nll1000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110lO_dataout <= wire_nll1000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110Oi_dataout <= wire_nll1000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110Ol_dataout <= wire_nll100ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll110OO_dataout <= wire_nll100il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1110i_dataout <= wire_nll11OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1110l_dataout <= wire_nll11OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1110O_dataout <= wire_nll11OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1111i_dataout <= wire_nll11OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1111l_dataout <= wire_nll11Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1111O_dataout <= wire_nll11Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111ii_dataout <= wire_nll11OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111il_dataout <= wire_nll1011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111iO_dataout <= wire_nll1011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111li_dataout <= wire_nll1011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111ll_dataout <= wire_nll1010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111lO_dataout <= wire_nll1010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111Oi_dataout <= wire_nll1010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111Ol_dataout <= wire_nll101ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll111OO_dataout <= wire_nll101il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11i0i_dataout <= wire_nll100lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11i0l_dataout <= wire_nll100Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11i0O_dataout <= wire_nll100Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11i1i_dataout <= wire_nll100iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11i1l_dataout <= wire_nll100li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11i1O_dataout <= wire_nll100ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11iii_dataout <= wire_nll100OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11iil_dataout <= wire_nll10i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11iiO_dataout <= wire_nll10i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11ili_dataout <= wire_nll10i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11ill_dataout <= wire_nll10i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11ilO_dataout <= wire_nll10i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11iOi_dataout <= wire_nll10i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11iOl_dataout <= wire_nll10iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11iOO_dataout <= wire_nll10iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11l0i_dataout <= wire_nll10ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11l0l_dataout <= wire_nll10iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11l0O_dataout <= nliO0i0l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1ilOl_dataout; + wire_nll11l1i_dataout <= wire_nll10iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11l1l_dataout <= wire_nll10ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11l1O_dataout <= wire_nll10ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11lii_dataout <= nliO0i0O WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1ilOO_dataout; + wire_nll11lil_dataout <= nliO0iii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1iO1i_dataout; + wire_nll11liO_dataout <= nliO0l1l WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1iO1l_dataout; + wire_nll11lli_dataout <= wire_nll1Ol0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1llii_dataout; + wire_nll11lll_dataout <= wire_nll1Olii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1llil_dataout; + wire_nll11llO_dataout <= wire_nll1Olil_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lliO_dataout; + wire_nll11lOi_dataout <= wire_nll1OliO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1llli_dataout; + wire_nll11lOl_dataout <= wire_nll1Olli_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1llll_dataout; + wire_nll11lOO_dataout <= wire_nll1Olll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lllO_dataout; + wire_nll11O0i_dataout <= wire_nll1OlOO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lO1i_dataout; + wire_nll11O0l_dataout <= wire_nll1OO1i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lO1l_dataout; + wire_nll11O0O_dataout <= wire_nll1OO1l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lO1O_dataout; + wire_nll11O1i_dataout <= wire_nll1OllO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1llOi_dataout; + wire_nll11O1l_dataout <= wire_nll1OlOi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1llOl_dataout; + wire_nll11O1O_dataout <= wire_nll1OlOl_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1llOO_dataout; + wire_nll11Oii_dataout <= wire_nll1OO1O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lO0i_dataout; + wire_nll11Oil_dataout <= wire_nll1OO0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lO0l_dataout; + wire_nll11OiO_dataout <= wire_nll1OO0l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lO0O_dataout; + wire_nll11Oli_dataout <= wire_nll1OO0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOii_dataout; + wire_nll11Oll_dataout <= wire_nll1OOii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOil_dataout; + wire_nll11OlO_dataout <= wire_nll1OOil_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOiO_dataout; + wire_nll11OlOi_dataout <= wire_nll101l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OlOl_dataout <= wire_nll101l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OlOO_dataout <= wire_nll101l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OO0i_dataout <= wire_nll101lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OO0l_dataout <= wire_nll101liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OO0O_dataout <= wire_nll101lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OO1i_dataout <= wire_nll101l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OO1l_dataout <= wire_nll101l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OO1O_dataout <= wire_nll101lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOi_dataout <= wire_nll1OOiO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOli_dataout; + wire_nll11OOii_dataout <= wire_nll101lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOil_dataout <= wire_nll101llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOiO_dataout <= wire_nll101lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOl_dataout <= wire_nll1OOli_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOll_dataout; + wire_nll11OOli_dataout <= wire_nll101lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOll_dataout <= wire_nll101lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOlO_dataout <= wire_nll101O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOO_dataout <= wire_nll1OOll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nll1lOlO_dataout; + wire_nll11OOOi_dataout <= wire_nll101O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOOl_dataout <= wire_nll101O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll11OOOO_dataout <= wire_nll101O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nll1i00i_dataout <= wire_nll1liil_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i00l_dataout <= wire_nll1liiO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i00O_dataout <= wire_nll1lili_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i01i_dataout <= wire_nll1li0l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i01l_dataout <= wire_nll1li0O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i01O_dataout <= wire_nll1liii_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0ii_dataout <= wire_nll1lill_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0il_dataout <= wire_nll1lilO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0iO_dataout <= wire_nll1liOi_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0li_dataout <= wire_nll1liOl_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0ll_dataout <= wire_nll1liOO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0lO_dataout <= wire_nll1ll1i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0Oi_dataout <= wire_nll1ll1l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0Ol_dataout <= wire_nll1ll1O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i0OO_dataout <= wire_nll1ll0i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i10i_dataout <= wire_nll1l0il_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i10l_dataout <= wire_nll1l0iO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i10O_dataout <= wire_nll1l0li_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i11i_dataout <= wire_nll1l00l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i11l_dataout <= wire_nll1l00O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i11O_dataout <= wire_nll1l0ii_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1ii_dataout <= wire_nll1l0ll_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1il_dataout <= wire_nll1l0lO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1iO_dataout <= wire_nll1l0Oi_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1li_dataout <= wire_nll1l0Ol_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1ll_dataout <= wire_nll1l0OO_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1lO_dataout <= wire_nll1li1i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1Oi_dataout <= wire_nll1li1l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1Ol_dataout <= wire_nll1li1O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1i1OO_dataout <= wire_nll1li0i_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1ii0i_dataout <= wire_nll0l1ll_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0llO; + wire_nll1ii0l_dataout <= wire_nll0l1lO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0lOi; + wire_nll1ii0O_dataout <= wire_nll0l1Oi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0lOl; + wire_nll1ii1i_dataout <= wire_nll1ll0l_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1ii1l_dataout <= wire_nll1ll0O_dataout AND NOT(wire_w_lg_w_k_gbl_hip_range1050w1051w(0)); + wire_nll1ii1O_dataout <= wire_nll0l1li_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0lll; + wire_nll1iiii_dataout <= wire_nll0l1Ol_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0lOO; + wire_nll1iiil_dataout <= wire_nll0l1OO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0O1i; + wire_nll1iiiO_dataout <= wire_nll0l01i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0O1l; + wire_nll1iili_dataout <= wire_nll0l01l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0O1O; + wire_nll1iill_dataout <= wire_nll0l0lO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0l1O; + wire_nll1iilO_dataout <= wire_nll0l0Oi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0l0i; + wire_nll1iiOi_dataout <= wire_nll0l0Ol_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0l0l; + wire_nll1iiOl_dataout <= wire_nll0l0OO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0l0O; + wire_nll1iiOO_dataout <= wire_nll0li1i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0lii; + wire_nll1il0i_dataout <= wire_nll0li0l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0iil; + wire_nll1il0l_dataout <= wire_nll0li0O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0iiO; + wire_nll1il0O_dataout <= wire_nll0liii_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0ili; + wire_nll1il1i_dataout <= wire_nll0li1l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0lil; + wire_nll1il1l_dataout <= wire_nll0li1O_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0liO; + wire_nll1il1O_dataout <= wire_nll0li0i_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0lli; + wire_nll1ilii_dataout <= wire_nll0liil_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0ill; + wire_nll1ilil_dataout <= wire_nll0liiO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0ilO; + wire_nll1iliO_dataout <= wire_nll0lili_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0iOi; + wire_nll1illi_dataout <= wire_nll0lill_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0iOl; + wire_nll1illl_dataout <= wire_nll0lilO_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0iOO; + wire_nll1illO_dataout <= wire_nll0liOi_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nliO0l1i; + wire_nll1ilOi_dataout <= nl1OilOii WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE nli01iOO; + wire_nll1ilOl_dataout <= wire_nll1Oill_dataout WHEN nll0O0iOi = '1' ELSE nliO0i0l; + wire_nll1ilOO_dataout <= wire_nll1OilO_dataout WHEN nll0O0iOi = '1' ELSE nliO0i0O; + wire_nll1iO0i_dataout <= nliOiliO WHEN nll0O0iOi = '1' ELSE nliO0O0l; + wire_nll1iO0l_dataout <= nliOilli WHEN nll0O0iOi = '1' ELSE nliO0O0O; + wire_nll1iO0O_dataout <= nliOilll WHEN nll0O0iOi = '1' ELSE nliO0Oii; + wire_nll1iO1i_dataout <= wire_nll1OiOi_dataout WHEN nll0O0iOi = '1' ELSE nliO0iii; + wire_nll1iO1l_dataout <= wire_nll1OiOl_dataout WHEN nll0O0iOi = '1' ELSE nliO0l1l; + wire_nll1iO1O_dataout <= nliOilil WHEN nll0O0iOi = '1' ELSE nliO0O0i; + wire_nll1iOii_dataout <= nliOillO WHEN nll0O0iOi = '1' ELSE nliO0Oil; + wire_nll1iOil_dataout <= nliOilOi WHEN nll0O0iOi = '1' ELSE nliO0OiO; + wire_nll1iOiO_dataout <= nliOilOl WHEN nll0O0iOi = '1' ELSE nliO0Oli; + wire_nll1iOli_dataout <= nliOilOO WHEN nll0O0iOi = '1' ELSE nliO0Oll; + wire_nll1iOll_dataout <= nliOiO1i WHEN nll0O0iOi = '1' ELSE nliO0OlO; + wire_nll1iOlO_dataout <= nliOiO1l WHEN nll0O0iOi = '1' ELSE nliO0OOi; + wire_nll1iOOi_dataout <= nliOiO1O WHEN nll0O0iOi = '1' ELSE nliO0OOl; + wire_nll1iOOl_dataout <= nliOiO0i WHEN nll0O0iOi = '1' ELSE nliO0OOO; + wire_nll1iOOO_dataout <= nliOiO0l WHEN nll0O0iOi = '1' ELSE nliOi11i; + wire_nll1l00i_dataout <= nliOl1iO WHEN nll0O0iOi = '1' ELSE nliOi00l; + wire_nll1l00l_dataout <= nliOl1li WHEN nll0O0iOi = '1' ELSE nliOi00O; + wire_nll1l00O_dataout <= nliOl1ll WHEN nll0O0iOi = '1' ELSE nliOi0ii; + wire_nll1l01i_dataout <= nliOl10O WHEN nll0O0iOi = '1' ELSE nliOi01l; + wire_nll1l01l_dataout <= nliOl1ii WHEN nll0O0iOi = '1' ELSE nliOi01O; + wire_nll1l01O_dataout <= nliOl1il WHEN nll0O0iOi = '1' ELSE nliOi00i; + wire_nll1l0ii_dataout <= nliOl1lO WHEN nll0O0iOi = '1' ELSE nliOi0il; + wire_nll1l0il_dataout <= nliOl1Oi WHEN nll0O0iOi = '1' ELSE nliOi0iO; + wire_nll1l0iO_dataout <= nliOl1Ol WHEN nll0O0iOi = '1' ELSE nliOi0li; + wire_nll1l0li_dataout <= nliOl1OO WHEN nll0O0iOi = '1' ELSE nliOi0ll; + wire_nll1l0ll_dataout <= nliOl01i WHEN nll0O0iOi = '1' ELSE nliOi0lO; + wire_nll1l0lO_dataout <= nliOl01l WHEN nll0O0iOi = '1' ELSE nliOi0Oi; + wire_nll1l0Oi_dataout <= nliOl01O WHEN nll0O0iOi = '1' ELSE nliOi0Ol; + wire_nll1l0Ol_dataout <= nliOl00i WHEN nll0O0iOi = '1' ELSE nliOi0OO; + wire_nll1l0OO_dataout <= nliOl00l WHEN nll0O0iOi = '1' ELSE nliOii1i; + wire_nll1l10i_dataout <= nliOiOiO WHEN nll0O0iOi = '1' ELSE nliOi10l; + wire_nll1l10l_dataout <= nliOiOli WHEN nll0O0iOi = '1' ELSE nliOi10O; + wire_nll1l10O_dataout <= nliOiOll WHEN nll0O0iOi = '1' ELSE nliOi1ii; + wire_nll1l11i_dataout <= nliOiO0O WHEN nll0O0iOi = '1' ELSE nliOi11l; + wire_nll1l11l_dataout <= nliOiOii WHEN nll0O0iOi = '1' ELSE nliOi11O; + wire_nll1l11O_dataout <= nliOiOil WHEN nll0O0iOi = '1' ELSE nliOi10i; + wire_nll1l1ii_dataout <= nliOiOlO WHEN nll0O0iOi = '1' ELSE nliOi1il; + wire_nll1l1il_dataout <= nliOiOOi WHEN nll0O0iOi = '1' ELSE nliOi1iO; + wire_nll1l1iO_dataout <= nliOiOOl WHEN nll0O0iOi = '1' ELSE nliOi1li; + wire_nll1l1li_dataout <= nliOiOOO WHEN nll0O0iOi = '1' ELSE nliOi1ll; + wire_nll1l1ll_dataout <= nliOl11i WHEN nll0O0iOi = '1' ELSE nliOi1lO; + wire_nll1l1lO_dataout <= nliOl11l WHEN nll0O0iOi = '1' ELSE nliOi1Oi; + wire_nll1l1Oi_dataout <= nliOl11O WHEN nll0O0iOi = '1' ELSE nliOi1Ol; + wire_nll1l1Ol_dataout <= nliOl10i WHEN nll0O0iOi = '1' ELSE nliOi1OO; + wire_nll1l1OO_dataout <= nliOl10l WHEN nll0O0iOi = '1' ELSE nliOi01i; + wire_nll1li0i_dataout <= nliOl0iO WHEN nll0O0iOi = '1' ELSE nliOii0l; + wire_nll1li0l_dataout <= nliOl0li WHEN nll0O0iOi = '1' ELSE nliOii0O; + wire_nll1li0O_dataout <= nliOl0ll WHEN nll0O0iOi = '1' ELSE nliOiiii; + wire_nll1li1i_dataout <= nliOl00O WHEN nll0O0iOi = '1' ELSE nliOii1l; + wire_nll1li1l_dataout <= nliOl0ii WHEN nll0O0iOi = '1' ELSE nliOii1O; + wire_nll1li1O_dataout <= nliOl0il WHEN nll0O0iOi = '1' ELSE nliOii0i; + wire_nll1liii_dataout <= nliOl0lO WHEN nll0O0iOi = '1' ELSE nliOiiil; + wire_nll1liil_dataout <= nliOl0Oi WHEN nll0O0iOi = '1' ELSE nliOiiiO; + wire_nll1liiO_dataout <= nliOl0Ol WHEN nll0O0iOi = '1' ELSE nliOiili; + wire_nll1lili_dataout <= nliOl0OO WHEN nll0O0iOi = '1' ELSE nliOiill; + wire_nll1lill_dataout <= nliOli1i WHEN nll0O0iOi = '1' ELSE nliOiilO; + wire_nll1lilO_dataout <= nliOli1l WHEN nll0O0iOi = '1' ELSE nliOiiOi; + wire_nll1liOi_dataout <= nliOli1O WHEN nll0O0iOi = '1' ELSE nliOiiOl; + wire_nll1liOl_dataout <= nliOli0i WHEN nll0O0iOi = '1' ELSE nliOiiOO; + wire_nll1liOO_dataout <= nliOli0l WHEN nll0O0iOi = '1' ELSE nliOil1i; + wire_nll1ll0i_dataout <= nliOliiO WHEN nll0O0iOi = '1' ELSE nliOil0l; + wire_nll1ll0l_dataout <= nliOlili WHEN nll0O0iOi = '1' ELSE nliOil0O; + wire_nll1ll0O_dataout <= nliOlill WHEN nll0O0iOi = '1' ELSE nliOilii; + wire_nll1ll1i_dataout <= nliOli0O WHEN nll0O0iOi = '1' ELSE nliOil1l; + wire_nll1ll1l_dataout <= nliOliii WHEN nll0O0iOi = '1' ELSE nliOil1O; + wire_nll1ll1O_dataout <= nliOliil WHEN nll0O0iOi = '1' ELSE nliOil0i; + wire_nll1llii_dataout <= nll0O0iOO WHEN nll0O0iOi = '1' ELSE nliOilil; + wire_nll1llil_dataout <= nll0O0l1i WHEN nll0O0iOi = '1' ELSE nliOiliO; + wire_nll1lliO_dataout <= nll0O0l1l WHEN nll0O0iOi = '1' ELSE nliOilli; + wire_nll1llli_dataout <= nll0O0l1O WHEN nll0O0iOi = '1' ELSE nliOilll; + wire_nll1llll_dataout <= nll0O0l0i WHEN nll0O0iOi = '1' ELSE nliOillO; + wire_nll1lllO_dataout <= nll0O0l0l WHEN nll0O0iOi = '1' ELSE nliOilOi; + wire_nll1llOi_dataout <= nll0O0l0O WHEN nll0O0iOi = '1' ELSE nliOilOl; + wire_nll1llOl_dataout <= nll0O0lii WHEN nll0O0iOi = '1' ELSE nliOilOO; + wire_nll1llOO_dataout <= nll0O0lil WHEN nll0O0iOi = '1' ELSE nliOiO1i; + wire_nll1lO0i_dataout <= nll0O0llO WHEN nll0O0iOi = '1' ELSE nliOiO0l; + wire_nll1lO0l_dataout <= nll0O0lOi WHEN nll0O0iOi = '1' ELSE nliOiO0O; + wire_nll1lO0O_dataout <= nll0O0lOl WHEN nll0O0iOi = '1' ELSE nliOiOii; + wire_nll1lO1i_dataout <= nll0O0liO WHEN nll0O0iOi = '1' ELSE nliOiO1l; + wire_nll1lO1l_dataout <= nll0O0lli WHEN nll0O0iOi = '1' ELSE nliOiO1O; + wire_nll1lO1O_dataout <= nll0O0lll WHEN nll0O0iOi = '1' ELSE nliOiO0i; + wire_nll1lOii_dataout <= nll0O0lOO WHEN nll0O0iOi = '1' ELSE nliOiOil; + wire_nll1lOil_dataout <= nll0O0O1i WHEN nll0O0iOi = '1' ELSE nliOiOiO; + wire_nll1lOiO_dataout <= nll0O0O1l WHEN nll0O0iOi = '1' ELSE nliOiOli; + wire_nll1lOli_dataout <= nll0O0O1O WHEN nll0O0iOi = '1' ELSE nliOiOll; + wire_nll1lOll_dataout <= nll0O0O0i WHEN nll0O0iOi = '1' ELSE nliOiOlO; + wire_nll1lOlO_dataout <= nll0O0O0l WHEN nll0O0iOi = '1' ELSE nliOiOOi; + wire_nll1lOOi_dataout <= nll0O0O0O WHEN nll0O0iOi = '1' ELSE nliOiOOl; + wire_nll1lOOl_dataout <= nll0O0Oii WHEN nll0O0iOi = '1' ELSE nliOiOOO; + wire_nll1lOOO_dataout <= nll0O0Oil WHEN nll0O0iOi = '1' ELSE nliOl11i; + wire_nll1O00i_dataout <= nll0Oi1lO WHEN nll0O0iOi = '1' ELSE nliOl00l; + wire_nll1O00l_dataout <= nll0Oi1Oi WHEN nll0O0iOi = '1' ELSE nliOl00O; + wire_nll1O00O_dataout <= nll0Oi1Ol WHEN nll0O0iOi = '1' ELSE nliOl0ii; + wire_nll1O01i_dataout <= nll0Oi1iO WHEN nll0O0iOi = '1' ELSE nliOl01l; + wire_nll1O01l_dataout <= nll0Oi1li WHEN nll0O0iOi = '1' ELSE nliOl01O; + wire_nll1O01O_dataout <= nll0Oi1ll WHEN nll0O0iOi = '1' ELSE nliOl00i; + wire_nll1O0ii_dataout <= nll0Oi1OO WHEN nll0O0iOi = '1' ELSE nliOl0il; + wire_nll1O0il_dataout <= nll0Oi01i WHEN nll0O0iOi = '1' ELSE nliOl0iO; + wire_nll1O0iO_dataout <= nll0Oi01l WHEN nll0O0iOi = '1' ELSE nliOl0li; + wire_nll1O0li_dataout <= nll0Oi01O WHEN nll0O0iOi = '1' ELSE nliOl0ll; + wire_nll1O0ll_dataout <= nll0Oi00i WHEN nll0O0iOi = '1' ELSE nliOl0lO; + wire_nll1O0lO_dataout <= nll0Oi00l WHEN nll0O0iOi = '1' ELSE nliOl0Oi; + wire_nll1O0Oi_dataout <= nll0Oi00O WHEN nll0O0iOi = '1' ELSE nliOl0Ol; + wire_nll1O0Ol_dataout <= nll0Oi0ii WHEN nll0O0iOi = '1' ELSE nliOl0OO; + wire_nll1O0OO_dataout <= nll0Oi0il WHEN nll0O0iOi = '1' ELSE nliOli1i; + wire_nll1O10i_dataout <= nll0O0OlO WHEN nll0O0iOi = '1' ELSE nliOl10l; + wire_nll1O10l_dataout <= nll0O0OOi WHEN nll0O0iOi = '1' ELSE nliOl10O; + wire_nll1O10O_dataout <= nll0O0OOl WHEN nll0O0iOi = '1' ELSE nliOl1ii; + wire_nll1O11i_dataout <= nll0O0OiO WHEN nll0O0iOi = '1' ELSE nliOl11l; + wire_nll1O11l_dataout <= nll0O0Oli WHEN nll0O0iOi = '1' ELSE nliOl11O; + wire_nll1O11O_dataout <= nll0O0Oll WHEN nll0O0iOi = '1' ELSE nliOl10i; + wire_nll1O1ii_dataout <= nll0O0OOO WHEN nll0O0iOi = '1' ELSE nliOl1il; + wire_nll1O1il_dataout <= nll0Oi11i WHEN nll0O0iOi = '1' ELSE nliOl1iO; + wire_nll1O1iO_dataout <= nll0Oi11l WHEN nll0O0iOi = '1' ELSE nliOl1li; + wire_nll1O1li_dataout <= nll0Oi11O WHEN nll0O0iOi = '1' ELSE nliOl1ll; + wire_nll1O1ll_dataout <= nll0Oi10i WHEN nll0O0iOi = '1' ELSE nliOl1lO; + wire_nll1O1lO_dataout <= nll0Oi10l WHEN nll0O0iOi = '1' ELSE nliOl1Oi; + wire_nll1O1Oi_dataout <= nll0Oi10O WHEN nll0O0iOi = '1' ELSE nliOl1Ol; + wire_nll1O1Ol_dataout <= nll0Oi1ii WHEN nll0O0iOi = '1' ELSE nliOl1OO; + wire_nll1O1OO_dataout <= nll0Oi1il WHEN nll0O0iOi = '1' ELSE nliOl01i; + wire_nll1Oi0i_dataout <= nll0Oi0lO WHEN nll0O0iOi = '1' ELSE nliOli0l; + wire_nll1Oi0l_dataout <= nll0Oi0Oi WHEN nll0O0iOi = '1' ELSE nliOli0O; + wire_nll1Oi0O_dataout <= nll0Oi0Ol WHEN nll0O0iOi = '1' ELSE nliOliii; + wire_nll1Oi1i_dataout <= nll0Oi0iO WHEN nll0O0iOi = '1' ELSE nliOli1l; + wire_nll1Oi1l_dataout <= nll0Oi0li WHEN nll0O0iOi = '1' ELSE nliOli1O; + wire_nll1Oi1O_dataout <= nll0Oi0ll WHEN nll0O0iOi = '1' ELSE nliOli0i; + wire_nll1Oiii_dataout <= nll0Oi0OO WHEN nll0O0iOi = '1' ELSE nliOliil; + wire_nll1Oiil_dataout <= nll0Oii1i WHEN nll0O0iOi = '1' ELSE nliOliiO; + wire_nll1OiiO_dataout <= nll0Oii1l WHEN nll0O0iOi = '1' ELSE nliOlili; + wire_nll1Oili_dataout <= nll0Oii1O WHEN nll0O0iOi = '1' ELSE nliOlill; + wire_nll1Oill_dataout <= wire_nll1OiOO_dataout AND NOT(niOO0100l); + wire_nll1OilO_dataout <= wire_nll1Ol1i_dataout AND NOT(niOO0100l); + wire_nll1OiOi_dataout <= wire_nll1Ol1l_dataout AND NOT(niOO0100l); + wire_nll1OiOl_dataout <= wire_nll1Ol1O_dataout AND NOT(niOO0100l); + wire_nll1OiOO_dataout <= niOO01l1O WHEN niOO0101i = '1' ELSE nliO0i0l; + wire_nll1Ol0O_dataout <= wire_nl1lOOi0l_dataout WHEN nlliO01l = '1' ELSE wire_nll01ili_dataout; + wire_nll1Ol1i_dataout <= niOO010il WHEN niOO0101i = '1' ELSE nliO0i0O; + wire_nll1Ol1l_dataout <= nll0OOOOl WHEN niOO0101i = '1' ELSE nliO0iii; + wire_nll1Ol1O_dataout <= nlli101ll WHEN niOO0101i = '1' ELSE nliO0l1l; + wire_nll1Olii_dataout <= wire_nl1lOOi0O_dataout WHEN nlliO01l = '1' ELSE wire_nll01ill_dataout; + wire_nll1Olil_dataout <= wire_nl1lOOiii_dataout WHEN nlliO01l = '1' ELSE wire_nll01ilO_dataout; + wire_nll1OliO_dataout <= wire_nl1lOOiil_dataout WHEN nlliO01l = '1' ELSE wire_nll01iOi_dataout; + wire_nll1Olli_dataout <= wire_nl1lOOiiO_dataout WHEN nlliO01l = '1' ELSE wire_nll01iOl_dataout; + wire_nll1Olll_dataout <= wire_nl1lOOili_dataout WHEN nlliO01l = '1' ELSE wire_nll01iOO_dataout; + wire_nll1OllO_dataout <= wire_nl1lOOill_dataout WHEN nlliO01l = '1' ELSE wire_nll01l1i_dataout; + wire_nll1OlOi_dataout <= wire_nl1lOOilO_dataout WHEN nlliO01l = '1' ELSE wire_nll01l1l_dataout; + wire_nll1OlOl_dataout <= wire_nl1lOOiOi_dataout WHEN nlliO01l = '1' ELSE wire_nll01l1O_dataout; + wire_nll1OlOO_dataout <= wire_nl1lOOiOl_dataout WHEN nlliO01l = '1' ELSE wire_nll01l0i_dataout; + wire_nll1OO0i_dataout <= wire_nl1lOOl1O_dataout WHEN nlliO01l = '1' ELSE wire_nll01lil_dataout; + wire_nll1OO0l_dataout <= wire_nl1lOOl0i_dataout WHEN nlliO01l = '1' ELSE wire_nll01liO_dataout; + wire_nll1OO0O_dataout <= wire_nl1lOOl0l_dataout WHEN nlliO01l = '1' ELSE wire_nll01lli_dataout; + wire_nll1OO1i_dataout <= wire_nll01l0l_dataout AND NOT(nlliO01l); + wire_nll1OO1l_dataout <= wire_nll01l0O_dataout AND NOT(nlliO01l); + wire_nll1OO1O_dataout <= wire_nl1lOOl1l_dataout WHEN nlliO01l = '1' ELSE wire_nll01lii_dataout; + wire_nll1OOii_dataout <= wire_nll01lll_dataout AND NOT(nlliO01l); + wire_nll1OOil_dataout <= wire_nll01llO_dataout AND NOT(nlliO01l); + wire_nll1OOiO_dataout <= wire_nll01lOi_dataout AND NOT(nlliO01l); + wire_nll1OOli_dataout <= wire_nll01lOl_dataout AND NOT(nlliO01l); + wire_nll1OOll_dataout <= wire_nl1lOOlli_dataout WHEN nlliO01l = '1' ELSE wire_nll01lOO_dataout; + wire_nll1OOlO_dataout <= wire_nl1lOOlll_dataout WHEN nlliO01l = '1' ELSE wire_nll01O1i_dataout; + wire_nll1OOOi_dataout <= wire_nl1lOOllO_dataout WHEN nlliO01l = '1' ELSE wire_nll01O1l_dataout; + wire_nll1OOOl_dataout <= wire_nll01O1O_dataout AND NOT(nlliO01l); + wire_nll1OOOO_dataout <= wire_nl1lOOlOl_dataout WHEN nlliO01l = '1' ELSE wire_nll01O0i_dataout; + wire_nlli0000i_dataout <= wire_nlli000OO_dataout WHEN niOiOi0ii = '1' ELSE nlli1OO1i; + wire_nlli0000l_dataout <= wire_nlli00lOO_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00i1i_dataout; + wire_nlli0000O_dataout <= wire_nlli00O1i_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00i1l_dataout; + wire_nlli0001i_dataout <= wire_nlli000lO_dataout WHEN niOiOi0ii = '1' ELSE nlli1OlOi; + wire_nlli0001l_dataout <= wire_nlli000Oi_dataout WHEN niOiOi0ii = '1' ELSE nlli1OlOl; + wire_nlli0001O_dataout <= wire_nlli000Ol_dataout WHEN niOiOi0ii = '1' ELSE nlli1OlOO; + wire_nlli000i_dataout <= wire_nlli0i1O_dataout AND NOT(niOO010Oi); + wire_nlli000ii_dataout <= wire_nlli00O1l_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00i1O_dataout; + wire_nlli000il_dataout <= wire_nlli00O1O_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00i0i_dataout; + wire_nlli000iO_dataout <= wire_nlli00O0i_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00i0l_dataout; + wire_nlli000l_dataout <= niOO01i1l WHEN niOO010Oi = '1' ELSE wire_nlli0i0i_dataout; + wire_nlli000li_dataout <= wire_nlli00O0l_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00i0O_dataout; + wire_nlli000ll_dataout <= wire_nlli00O0O_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00iii_dataout; + wire_nlli000lO_dataout <= wire_nlli00Oii_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00iil_dataout; + wire_nlli000O_dataout <= wire_w_lg_niOO01i1l5387w(0) WHEN niOO010Oi = '1' ELSE wire_nlli0i0l_dataout; + wire_nlli000Oi_dataout <= wire_nlli00Oil_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00iiO_dataout; + wire_nlli000Ol_dataout <= wire_nlli00OiO_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00ili_dataout; + wire_nlli000OO_dataout <= wire_nlli00Oli_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli00ill_dataout; + wire_nlli0010i_dataout <= wire_nlli001OO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0010l_dataout <= wire_nlli0001i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0010O_dataout <= wire_nlli0001l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0011i_dataout <= wire_nlli001lO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0011l_dataout <= wire_nlli001Oi_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0011O_dataout <= wire_nlli001Ol_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli001i_dataout <= nll0OilO AND NOT(niOO010Oi); + wire_nlli001ii_dataout <= wire_nlli0001O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli001il_dataout <= wire_nlli0000i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli001iO_dataout <= wire_nlli0000l_dataout WHEN niOiOi0ii = '1' ELSE nlli1Ol0O; + wire_nlli001l_dataout <= niOO01i1l WHEN niOO010Oi = '1' ELSE nll0Ol1i; + wire_nlli001li_dataout <= wire_nlli0000O_dataout WHEN niOiOi0ii = '1' ELSE nlli1Olii; + wire_nlli001ll_dataout <= wire_nlli000ii_dataout WHEN niOiOi0ii = '1' ELSE nlli1Olil; + wire_nlli001lO_dataout <= wire_nlli000il_dataout WHEN niOiOi0ii = '1' ELSE nlli1OliO; + wire_nlli001O_dataout <= wire_nlli0i1l_dataout AND NOT(niOO010Oi); + wire_nlli001Oi_dataout <= wire_nlli000iO_dataout WHEN niOiOi0ii = '1' ELSE nlli1Olli; + wire_nlli001Ol_dataout <= wire_nlli000li_dataout WHEN niOiOi0ii = '1' ELSE nlli1Olll; + wire_nlli001OO_dataout <= wire_nlli000ll_dataout WHEN niOiOi0ii = '1' ELSE nlli1OllO; + wire_nlli00i0i_dataout <= wire_nlli00liO_o(4) WHEN niOiOi0iO = '1' ELSE wire_nlli00iOl_dataout; + wire_nlli00i0l_dataout <= wire_nlli00liO_o(5) WHEN niOiOi0iO = '1' ELSE wire_nlli00iOO_dataout; + wire_nlli00i0O_dataout <= wire_nlli00liO_o(6) WHEN niOiOi0iO = '1' ELSE wire_nlli00l1i_dataout; + wire_nlli00i1i_dataout <= wire_nlli00liO_o(1) WHEN niOiOi0iO = '1' ELSE nlli1Ol0O; + wire_nlli00i1l_dataout <= wire_nlli00liO_o(2) WHEN niOiOi0iO = '1' ELSE wire_nlli00ilO_dataout; + wire_nlli00i1O_dataout <= wire_nlli00liO_o(3) WHEN niOiOi0iO = '1' ELSE wire_nlli00iOi_dataout; + wire_nlli00ii_dataout <= wire_nlli0i0O_dataout WHEN niOO010lO = '1' ELSE nll0O0lO; + wire_nlli00iii_dataout <= wire_nlli00liO_o(7) WHEN niOiOi0iO = '1' ELSE wire_nlli00l1l_dataout; + wire_nlli00iil_dataout <= wire_nlli00liO_o(8) WHEN niOiOi0iO = '1' ELSE wire_nlli00l1O_dataout; + wire_nlli00iiO_dataout <= wire_nlli00liO_o(9) WHEN niOiOi0iO = '1' ELSE wire_nlli00l0i_dataout; + wire_nlli00il_dataout <= wire_nlli0iii_dataout WHEN niOO010lO = '1' ELSE nll0O0Oi; + wire_nlli00ili_dataout <= wire_nlli00liO_o(10) WHEN niOiOi0iO = '1' ELSE wire_nlli00l0l_dataout; + wire_nlli00ill_dataout <= wire_nlli00liO_o(11) WHEN niOiOi0iO = '1' ELSE wire_nlli00l0O_dataout; + wire_nlli00ilO_dataout <= wire_nlli00lii_o(1) WHEN niOiOi0il = '1' ELSE nlli1Olii; + wire_nlli00iO_dataout <= wire_nlli0iil_dataout WHEN niOO010lO = '1' ELSE nll0O0Ol; + wire_nlli00iOi_dataout <= wire_nlli00lii_o(2) WHEN niOiOi0il = '1' ELSE nlli1Olil; + wire_nlli00iOl_dataout <= wire_nlli00lii_o(3) WHEN niOiOi0il = '1' ELSE nlli1OliO; + wire_nlli00iOO_dataout <= wire_nlli00lii_o(4) WHEN niOiOi0il = '1' ELSE nlli1Olli; + wire_nlli00l0i_dataout <= wire_nlli00lii_o(8) WHEN niOiOi0il = '1' ELSE nlli1OlOl; + wire_nlli00l0l_dataout <= wire_nlli00lii_o(9) WHEN niOiOi0il = '1' ELSE nlli1OlOO; + wire_nlli00l0O_dataout <= wire_nlli00lii_o(10) WHEN niOiOi0il = '1' ELSE nlli1OO1i; + wire_nlli00l1i_dataout <= wire_nlli00lii_o(5) WHEN niOiOi0il = '1' ELSE nlli1Olll; + wire_nlli00l1l_dataout <= wire_nlli00lii_o(6) WHEN niOiOi0il = '1' ELSE nlli1OllO; + wire_nlli00l1O_dataout <= wire_nlli00lii_o(7) WHEN niOiOi0il = '1' ELSE nlli1OlOi; + wire_nlli00li_dataout <= wire_nlli0iiO_dataout WHEN niOO010lO = '1' ELSE nll0O0OO; + wire_nlli00ll_dataout <= wire_nlli0ili_dataout WHEN niOO010lO = '1' ELSE nll0Oi1i; + wire_nlli00lO_dataout <= wire_nlli0ill_dataout WHEN niOO010lO = '1' ELSE nll0Oi1l; + wire_nlli00lOO_dataout <= wire_nlli00Oll_o(0) WHEN niOiOi0lO = '1' ELSE wire_nlli0i11l_dataout; + wire_nlli00O0i_dataout <= wire_nlli00Oll_o(4) WHEN niOiOi0lO = '1' ELSE wire_nlli0i10O_dataout; + wire_nlli00O0l_dataout <= wire_nlli00Oll_o(5) WHEN niOiOi0lO = '1' ELSE wire_nlli0i1ii_dataout; + wire_nlli00O0O_dataout <= wire_nlli00Oll_o(6) WHEN niOiOi0lO = '1' ELSE wire_nlli0i1il_dataout; + wire_nlli00O1i_dataout <= wire_nlli00Oll_o(1) WHEN niOiOi0lO = '1' ELSE wire_nlli0i11O_dataout; + wire_nlli00O1l_dataout <= wire_nlli00Oll_o(2) WHEN niOiOi0lO = '1' ELSE wire_nlli0i10i_dataout; + wire_nlli00O1O_dataout <= wire_nlli00Oll_o(3) WHEN niOiOi0lO = '1' ELSE wire_nlli0i10l_dataout; + wire_nlli00Oi_dataout <= wire_nlli0ilO_dataout WHEN niOO010lO = '1' ELSE nll0Oi1O; + wire_nlli00Oii_dataout <= wire_nlli00Oll_o(7) WHEN niOiOi0lO = '1' ELSE wire_nlli0i1iO_dataout; + wire_nlli00Oil_dataout <= wire_nlli00Oll_o(8) WHEN niOiOi0lO = '1' ELSE wire_nlli0i1li_dataout; + wire_nlli00OiO_dataout <= wire_nlli00Oll_o(9) WHEN niOiOi0lO = '1' ELSE wire_nlli0i1ll_dataout; + wire_nlli00Ol_dataout <= wire_nlli0iOi_dataout WHEN niOO010lO = '1' ELSE nll0Oi0i; + wire_nlli00Oli_dataout <= wire_nlli00Oll_o(10) WHEN niOiOi0lO = '1' ELSE niOiOi0Oi; + wire_nlli00OO_dataout <= wire_nlli0iOl_dataout WHEN niOO010lO = '1' ELSE nll0Oi0l; + wire_nlli0100i_dataout <= wire_nlli01i1i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0100l_dataout <= wire_nlli01i1l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0100O_dataout <= wire_nlli01i1O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0101i_dataout <= wire_nlli010Oi_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0101l_dataout <= wire_nlli010Ol_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0101O_dataout <= wire_nlli010OO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli010i_dataout <= wire_nlli0l0O_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00li_dataout; + wire_nlli010ii_dataout <= wire_nlli01i0i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli010il_dataout <= wire_nlli01i0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Oi0i; + wire_nlli010iO_dataout <= wire_nlli01i0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Oili; + wire_nlli010l_dataout <= wire_nlli0lii_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00ll_dataout; + wire_nlli010li_dataout <= wire_nlli01iii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Oill; + wire_nlli010ll_dataout <= wire_nlli01iil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1OilO; + wire_nlli010lO_dataout <= wire_nlli01iiO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1OiOi; + wire_nlli010O_dataout <= wire_nlli0lil_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00lO_dataout; + wire_nlli010Oi_dataout <= wire_nlli01ili_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1OiOl; + wire_nlli010Ol_dataout <= wire_nlli01ill_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1OiOO; + wire_nlli010OO_dataout <= wire_nlli01ilO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Ol1i; + wire_nlli0110i_dataout <= wire_nlli0011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0110l_dataout <= wire_nlli0011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0110O_dataout <= wire_nlli0010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0111i_dataout <= wire_nlli01OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0111l_dataout <= wire_nlli01OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0111O_dataout <= wire_nlli0011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli011i_dataout <= wire_nlli0l1O_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00ii_dataout; + wire_nlli011ii_dataout <= wire_nlli0010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli011il_dataout <= wire_nlli0010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli011iO_dataout <= wire_nlli001ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli011l_dataout <= wire_nlli0l0i_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00il_dataout; + wire_nlli011li_dataout <= wire_nlli001il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli011ll_dataout <= wire_nlli010il_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli011lO_dataout <= wire_nlli010iO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli011O_dataout <= wire_nlli0l0l_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00iO_dataout; + wire_nlli011Oi_dataout <= wire_nlli010li_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli011Ol_dataout <= wire_nlli010ll_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli011OO_dataout <= wire_nlli010lO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli01i0i_dataout <= wire_nlli01l1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Ol0l; + wire_nlli01i0l_dataout <= nlli0iili WHEN nlli0iO1i = '1' ELSE nlli1Oi0i; + wire_nlli01i0O_dataout <= wire_nlli01l1O_dataout WHEN nlli0iO1i = '1' ELSE nlli1Oili; + wire_nlli01i1i_dataout <= wire_nlli01iOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Ol1l; + wire_nlli01i1l_dataout <= wire_nlli01iOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Ol1O; + wire_nlli01i1O_dataout <= wire_nlli01iOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1Ol0i; + wire_nlli01ii_dataout <= wire_nlli0liO_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00Oi_dataout; + wire_nlli01iii_dataout <= wire_nlli01l0i_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(1); + wire_nlli01iil_dataout <= wire_nlli01l0l_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(2); + wire_nlli01iiO_dataout <= wire_nlli01l0O_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(3); + wire_nlli01il_dataout <= wire_nlli0lli_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00Ol_dataout; + wire_nlli01ili_dataout <= wire_nlli01lii_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(4); + wire_nlli01ill_dataout <= wire_nlli01lil_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(5); + wire_nlli01ilO_dataout <= wire_nlli01liO_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(6); + wire_nlli01iO_dataout <= wire_nlli0lll_dataout WHEN niOO010Oi = '1' ELSE wire_nlli00OO_dataout; + wire_nlli01iOi_dataout <= wire_nlli01lli_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(7); + wire_nlli01iOl_dataout <= wire_nlli01lll_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(8); + wire_nlli01iOO_dataout <= wire_nlli01llO_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(9); + wire_nlli01l0i_dataout <= wire_nlli01Oll_o(0) WHEN niOiOi00O = '1' ELSE wire_nlli01lOO_dataout; + wire_nlli01l0l_dataout <= wire_nlli01Oll_o(1) WHEN niOiOi00O = '1' ELSE wire_nlli01O1i_dataout; + wire_nlli01l0O_dataout <= wire_nlli01Oll_o(2) WHEN niOiOi00O = '1' ELSE wire_nlli01O1l_dataout; + wire_nlli01l1i_dataout <= wire_nlli01lOi_dataout WHEN nlli0iO1i = '1' ELSE wire_nlli01l1l_o(10); + wire_nlli01l1O_dataout <= wire_nlli0i11l_dataout WHEN niOiOi00O = '1' ELSE wire_nlli01lOl_dataout; + wire_nlli01li_dataout <= wire_nlli0llO_dataout WHEN niOO010Oi = '1' ELSE wire_nlli0i1i_dataout; + wire_nlli01lii_dataout <= wire_nlli01Oll_o(3) WHEN niOiOi00O = '1' ELSE wire_nlli01O1O_dataout; + wire_nlli01lil_dataout <= wire_nlli01Oll_o(4) WHEN niOiOi00O = '1' ELSE wire_nlli01O0i_dataout; + wire_nlli01liO_dataout <= wire_nlli01Oll_o(5) WHEN niOiOi00O = '1' ELSE wire_nlli01O0l_dataout; + wire_nlli01ll_dataout <= wire_nllii1iO_dataout WHEN niOO010Oi = '1' ELSE nll0Oiii; + wire_nlli01lli_dataout <= wire_nlli01Oll_o(6) WHEN niOiOi00O = '1' ELSE wire_nlli01O0O_dataout; + wire_nlli01lll_dataout <= wire_nlli01Oll_o(7) WHEN niOiOi00O = '1' ELSE wire_nlli01Oii_dataout; + wire_nlli01llO_dataout <= wire_nlli01Oll_o(8) WHEN niOiOi00O = '1' ELSE wire_nlli01Oil_dataout; + wire_nlli01lO_dataout <= niOO01i1l AND niOO010Oi; + wire_nlli01lOi_dataout <= wire_nlli01Oll_o(9) WHEN niOiOi00O = '1' ELSE wire_nlli01OiO_dataout; + wire_nlli01lOl_dataout <= wire_nlli00Oll_o(0) WHEN niOiOi00l = '1' ELSE wire_nlli0i11l_dataout; + wire_nlli01lOO_dataout <= wire_nlli00Oll_o(1) WHEN niOiOi00l = '1' ELSE wire_nlli0i11O_dataout; + wire_nlli01O0i_dataout <= wire_nlli00Oll_o(5) WHEN niOiOi00l = '1' ELSE wire_nlli0i1ii_dataout; + wire_nlli01O0l_dataout <= wire_nlli00Oll_o(6) WHEN niOiOi00l = '1' ELSE wire_nlli0i1il_dataout; + wire_nlli01O0O_dataout <= wire_nlli00Oll_o(7) WHEN niOiOi00l = '1' ELSE wire_nlli0i1iO_dataout; + wire_nlli01O1i_dataout <= wire_nlli00Oll_o(2) WHEN niOiOi00l = '1' ELSE wire_nlli0i10i_dataout; + wire_nlli01O1l_dataout <= wire_nlli00Oll_o(3) WHEN niOiOi00l = '1' ELSE wire_nlli0i10l_dataout; + wire_nlli01O1O_dataout <= wire_nlli00Oll_o(4) WHEN niOiOi00l = '1' ELSE wire_nlli0i10O_dataout; + wire_nlli01Oi_dataout <= wire_nllii1OO_dataout WHEN niOO010Oi = '1' ELSE nll0Ol1l; + wire_nlli01Oii_dataout <= wire_nlli00Oll_o(8) WHEN niOiOi00l = '1' ELSE wire_nlli0i1li_dataout; + wire_nlli01Oil_dataout <= wire_nlli00Oll_o(9) WHEN niOiOi00l = '1' ELSE wire_nlli0i1ll_dataout; + wire_nlli01OiO_dataout <= wire_nlli00Oll_o(10) WHEN niOiOi00l = '1' ELSE niOiOi0Oi; + wire_nlli01Ol_dataout <= wire_nllii01i_dataout WHEN niOO010Oi = '1' ELSE nll0Ol1O; + wire_nlli01OO_dataout <= wire_nllii01l_dataout WHEN niOO010Oi = '1' ELSE nll0Ol0i; + wire_nlli01OOi_dataout <= wire_nlli001iO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli01OOl_dataout <= wire_nlli001li_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli01OOO_dataout <= wire_nlli001ll_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0i0i_dataout <= nll0Oili AND NOT(niOO010lO); + wire_nlli0i0l_dataout <= nll0Oill AND NOT(niOO010lO); + wire_nlli0i0O_dataout <= nll0O0lO AND NOT(wire_nll0O1il_o); + wire_nlli0i10i_dataout <= nlli0i0lO AND nlli0illi; + wire_nlli0i10l_dataout <= nlli0i0Oi AND nlli0illi; + wire_nlli0i10O_dataout <= nlli0i0Ol AND nlli0illi; + wire_nlli0i11l_dataout <= nlli0i0li AND nlli0illi; + wire_nlli0i11O_dataout <= nlli0i0ll AND nlli0illi; + wire_nlli0i1i_dataout <= wire_nlli0iOO_dataout WHEN niOO010lO = '1' ELSE nll0Oi0O; + wire_nlli0i1ii_dataout <= nlli0i0OO AND nlli0illi; + wire_nlli0i1il_dataout <= nlli0ii1i AND nlli0illi; + wire_nlli0i1iO_dataout <= nlli0ii1l AND nlli0illi; + wire_nlli0i1l_dataout <= nll0Oiil OR niOO010lO; + wire_nlli0i1li_dataout <= nlli0ii1O AND nlli0illi; + wire_nlli0i1ll_dataout <= nlli0ii0i AND nlli0illi; + wire_nlli0i1O_dataout <= nll0OiiO AND NOT(niOO010lO); + wire_nlli0iii_dataout <= wire_nlli0l1i_o(1) AND NOT(wire_nll0O1il_o); + wire_nlli0iil_dataout <= wire_nlli0l1i_o(2) AND NOT(wire_nll0O1il_o); + wire_nlli0iiO_dataout <= wire_nlli0l1i_o(3) AND NOT(wire_nll0O1il_o); + wire_nlli0ili_dataout <= wire_nlli0l1i_o(4) AND NOT(wire_nll0O1il_o); + wire_nlli0ill_dataout <= wire_nlli0l1i_o(5) AND NOT(wire_nll0O1il_o); + wire_nlli0ilO_dataout <= wire_nlli0l1i_o(6) AND NOT(wire_nll0O1il_o); + wire_nlli0iO0i_dataout <= wire_nlli0lill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iO0l_dataout <= wire_nlli0lilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iO0O_dataout <= wire_nlli0liOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOi_dataout <= wire_nlli0l1i_o(7) AND NOT(wire_nll0O1il_o); + wire_nlli0iOii_dataout <= wire_nlli0liOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOil_dataout <= wire_nlli0liOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOiO_dataout <= wire_nlli0ll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOl_dataout <= wire_nlli0l1i_o(8) AND NOT(wire_nll0O1il_o); + wire_nlli0iOli_dataout <= wire_nlli0ll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOll_dataout <= wire_nlli0ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOlO_dataout <= wire_nlli0ll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOO_dataout <= wire_nlli0l1i_o(9) AND NOT(wire_nll0O1il_o); + wire_nlli0iOOi_dataout <= wire_nlli0ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOOl_dataout <= wire_nlli0ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0iOOO_dataout <= wire_nlli0llii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l00i_dataout <= wire_nlli0lOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l00l_dataout <= wire_nlli0lOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l00O_dataout <= wire_nlli0lOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l01i_dataout <= wire_nlli0lOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l01l_dataout <= wire_nlli0lOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l01O_dataout <= wire_nlli0lOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0i_dataout <= wire_nlli0lOl_dataout WHEN niOO01i1l = '1' ELSE nll0O0Oi; + wire_nlli0l0ii_dataout <= wire_nlli0lOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0il_dataout <= wire_nlli0lOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0iO_dataout <= wire_nlli0O11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0l_dataout <= wire_nlli0lOO_dataout WHEN niOO01i1l = '1' ELSE nll0O0Ol; + wire_nlli0l0li_dataout <= wire_nlli0O11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0ll_dataout <= wire_nlli0O11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0lO_dataout <= wire_nlli0O10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0O_dataout <= wire_nlli0O1i_dataout WHEN niOO01i1l = '1' ELSE nll0O0OO; + wire_nlli0l0Oi_dataout <= wire_nlli0O10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0Ol_dataout <= wire_nlli0O10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l0OO_dataout <= wire_nlli0O1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l10i_dataout <= wire_nlli0llll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l10l_dataout <= wire_nlli0lllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l10O_dataout <= wire_nlli0llOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l11i_dataout <= wire_nlli0llil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l11l_dataout <= wire_nlli0lliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l11O_dataout <= wire_nlli0llli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1ii_dataout <= wire_nlli0llOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1il_dataout <= wire_nlli0llOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1iO_dataout <= wire_nlli0lO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1li_dataout <= wire_nlli0lO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1ll_dataout <= wire_nlli0lO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1lO_dataout <= wire_nlli0lO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1O_dataout <= wire_nlli0lOi_dataout WHEN niOO01i1l = '1' ELSE nll0O0lO; + wire_nlli0l1Oi_dataout <= wire_nlli0lO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1Ol_dataout <= wire_nlli0lO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0l1OO_dataout <= wire_nlli0lOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0li0i_dataout <= wire_nlli0O1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0li0l_dataout <= wire_nlli0O1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0li0O_dataout <= wire_nlli0O1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0li1i_dataout <= wire_nlli0O1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0li1l_dataout <= wire_nlli0O1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0li1O_dataout <= wire_nlli0O1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0lii_dataout <= wire_nlli0O1l_dataout WHEN niOO01i1l = '1' ELSE nll0Oi1i; + wire_nlli0liii_dataout <= wire_nlli0O1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0liil_dataout <= wire_nlli0O1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0liiO_dataout <= wire_nlli0O01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0lil_dataout <= wire_nlli0O1O_dataout WHEN niOO01i1l = '1' ELSE nll0Oi1l; + wire_nlli0lili_dataout <= wire_nlli0O01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli0lill_dataout <= wire_nlli0O00l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lilO_dataout <= wire_nlli0O00O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0liO_dataout <= wire_nlli0O0i_dataout WHEN niOO01i1l = '1' ELSE nll0Oi1O; + wire_nlli0liOi_dataout <= wire_nlli0O0ii_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0liOl_dataout <= wire_nlli0O0il_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0liOO_dataout <= wire_nlli0O0iO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0ll0i_dataout <= wire_nlli0O0Oi_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0ll0l_dataout <= wire_nlli0O0Ol_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0ll0O_dataout <= wire_nlli0O0OO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0ll1i_dataout <= wire_nlli0O0li_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0ll1l_dataout <= wire_nlli0O0ll_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0ll1O_dataout <= wire_nlli0O0lO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lli_dataout <= wire_nlli0O0l_dataout WHEN niOO01i1l = '1' ELSE nll0Oi0i; + wire_nlli0llii_dataout <= wire_nlli0Oi1i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0llil_dataout <= wire_nlli0Oi1l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lliO_dataout <= wire_nlli0Oi1O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lll_dataout <= wire_nlli0O0O_dataout WHEN niOO01i1l = '1' ELSE nll0Oi0l; + wire_nlli0llli_dataout <= wire_nlli0Oi0i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0llll_dataout <= wire_nlli0Oi0l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lllO_dataout <= wire_nlli0Oi0O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0llO_dataout <= wire_nlli0Oii_dataout WHEN niOO01i1l = '1' ELSE nll0Oi0O; + wire_nlli0llOi_dataout <= wire_nlli0Oiii_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0llOl_dataout <= wire_nlli0Oiil_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0llOO_dataout <= wire_nlli0OiiO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lO0i_dataout <= wire_nlli0OiOi_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lO0l_dataout <= wire_nlli0OiOl_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lO0O_dataout <= wire_nlli0OiOO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lO1i_dataout <= wire_nlli0Oili_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lO1l_dataout <= wire_nlli0Oill_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lO1O_dataout <= wire_nlli0OilO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOi_dataout <= wire_nlliiiOi_dataout AND nll0Oii1l; + wire_nlli0lOii_dataout <= wire_nlli0Ol1i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOil_dataout <= wire_nlli0Ol1l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOiO_dataout <= wire_nlli0Ol1O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOl_dataout <= wire_nlliiiOl_dataout AND nll0Oii1l; + wire_nlli0lOli_dataout <= wire_nlli0Ol0i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOll_dataout <= wire_nlli0Ol0l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOlO_dataout <= wire_nlli0Ol0O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOO_dataout <= wire_nlliiiOO_dataout AND nll0Oii1l; + wire_nlli0lOOi_dataout <= wire_nlli0Olii_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOOl_dataout <= wire_nlli0Olil_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0lOOO_dataout <= wire_nlli0OliO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O00i_dataout <= wire_nlli0OOll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ilOi; + wire_nlli0O00l_dataout <= wire_nlli0OOlO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1OO1l; + wire_nlli0O00O_dataout <= wire_nlli0OOOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i1lO; + wire_nlli0O01i_dataout <= wire_nlli0OOil_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O01l_dataout <= wire_nlli0OOiO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O01O_dataout <= wire_nlli0OOli_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0illO; + wire_nlli0O0i_dataout <= wire_nlliil0i_dataout AND nll0Oii1l; + wire_nlli0O0ii_dataout <= wire_nlli0OOOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i1Oi; + wire_nlli0O0il_dataout <= wire_nlli0OOOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i1Ol; + wire_nlli0O0iO_dataout <= wire_nllii111i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i1OO; + wire_nlli0O0l_dataout <= wire_nlliil0l_dataout AND nll0Oii1l; + wire_nlli0O0li_dataout <= wire_nllii111l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i01i; + wire_nlli0O0ll_dataout <= wire_nllii101i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i01l; + wire_nlli0O0lO_dataout <= wire_nllii101l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i01O; + wire_nlli0O0O_dataout <= wire_nlliil0O_dataout AND nll0Oii1l; + wire_nlli0O0Oi_dataout <= wire_nllii101O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i00i; + wire_nlli0O0Ol_dataout <= wire_nllii100i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i00l; + wire_nlli0O0OO_dataout <= wire_nllii100l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i00O; + wire_nlli0O10i_dataout <= wire_nlli0OlOi_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O10l_dataout <= wire_nlli0OlOl_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O10O_dataout <= wire_nlli0OlOO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O11i_dataout <= wire_nlli0Olli_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O11l_dataout <= wire_nlli0Olll_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O11O_dataout <= wire_nlli0OllO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1i_dataout <= wire_nlliil1i_dataout AND nll0Oii1l; + wire_nlli0O1ii_dataout <= wire_nlli0OO1i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1il_dataout <= wire_nlli0OO1l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1iO_dataout <= wire_nlli0OO1O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1l_dataout <= wire_nlliil1l_dataout AND nll0Oii1l; + wire_nlli0O1li_dataout <= wire_nlli0OO0i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1ll_dataout <= wire_nlli0OO0l_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1lO_dataout <= wire_nlli0O01O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1O_dataout <= wire_nlliil1O_dataout AND nll0Oii1l; + wire_nlli0O1Oi_dataout <= wire_nlli0O00i_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1Ol_dataout <= wire_nlli0OO0O_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0O1OO_dataout <= wire_nlli0OOii_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli0Oi0i_dataout <= wire_nllii10iO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0li; + wire_nlli0Oi0l_dataout <= wire_nllii10li_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0ll; + wire_nlli0Oi0O_dataout <= wire_nllii10ll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0lO; + wire_nlli0Oi1i_dataout <= wire_nllii100O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0ii; + wire_nlli0Oi1l_dataout <= wire_nllii10ii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0il; + wire_nlli0Oi1O_dataout <= wire_nllii10il_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0iO; + wire_nlli0Oii_dataout <= wire_nlliilii_dataout AND nll0Oii1l; + wire_nlli0Oiii_dataout <= wire_nllii10lO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0Oi; + wire_nlli0Oiil_dataout <= wire_nllii10Oi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0Ol; + wire_nlli0OiiO_dataout <= wire_nllii10Ol_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0i0OO; + wire_nlli0Oili_dataout <= wire_nllii10OO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ii1i; + wire_nlli0Oill_dataout <= wire_nllii1i1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ii1l; + wire_nlli0OilO_dataout <= wire_nllii1i1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ii1O; + wire_nlli0OiOi_dataout <= wire_nllii1i1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ii0i; + wire_nlli0OiOl_dataout <= wire_nllii1i0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ii0l; + wire_nlli0OiOO_dataout <= wire_nllii1i0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ii0O; + wire_nlli0Ol0i_dataout <= wire_nllii1iiO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iili; + wire_nlli0Ol0l_dataout <= wire_nllii1ili_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iill; + wire_nlli0Ol0O_dataout <= wire_nllii1ill_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iilO; + wire_nlli0Ol1i_dataout <= wire_nllii1i0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iiii; + wire_nlli0Ol1l_dataout <= wire_nllii1iii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iiil; + wire_nlli0Ol1O_dataout <= wire_nllii1iil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iiiO; + wire_nlli0Oli_dataout <= nll0Oiil AND NOT(niOO01l1l); + wire_nlli0Olii_dataout <= wire_nllii1ilO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iiOi; + wire_nlli0Olil_dataout <= wire_nllii1iOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iiOl; + wire_nlli0OliO_dataout <= wire_nllii1iOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iiOO; + wire_nlli0Oll_dataout <= nll0OiiO OR niOO01l1l; + wire_nlli0Olli_dataout <= wire_nllii1iOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0il1i; + wire_nlli0Olll_dataout <= wire_nllii1l1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0il1l; + wire_nlli0OllO_dataout <= wire_nllii1l1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0il1O; + wire_nlli0OlO_dataout <= nll0Oili AND NOT(niOO01l1l); + wire_nlli0OlOi_dataout <= wire_nllii1l1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0il0i; + wire_nlli0OlOl_dataout <= wire_nllii1l0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0il0l; + wire_nlli0OlOO_dataout <= wire_nllii1l0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0il0O; + wire_nlli0OO0i_dataout <= wire_nllii1liO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0illi; + wire_nlli0OO0l_dataout <= wire_nllii1lli_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0illl; + wire_nlli0OO0O_dataout <= nlli0ilOO WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ilOl; + wire_nlli0OO1i_dataout <= wire_nllii1l0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ilii; + wire_nlli0OO1l_dataout <= wire_nllii1lii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ilil; + wire_nlli0OO1O_dataout <= wire_nllii1lil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iliO; + wire_nlli0OOi_dataout <= nll0Oill AND NOT(niOO01l1l); + wire_nlli0OOii_dataout <= nlli0iO1i WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0ilOO; + wire_nlli0OOil_dataout <= niOiOii1O WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iO1i; + wire_nlli0OOiO_dataout <= wire_nllii1lll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli0iO1l; + wire_nlli0OOl_dataout <= wire_nllii01O_dataout WHEN niOO01i1l = '1' ELSE nll0O0lO; + wire_nlli0OOli_dataout <= wire_nllii1O1O_dataout WHEN niOiOii1O = '1' ELSE nlli0illO; + wire_nlli0OOll_dataout <= nllilOlOl WHEN niOiOii1O = '1' ELSE nlli0ilOi; + wire_nlli0OOlO_dataout <= wire_nllii111O_dataout AND NOT(niOiOii1i); + wire_nlli0OOO_dataout <= wire_nllii00i_dataout WHEN niOO01i1l = '1' ELSE nll0O0Oi; + wire_nlli0OOOi_dataout <= wire_nllii110i_dataout AND NOT(niOiOii1i); + wire_nlli0OOOl_dataout <= wire_nllii110l_dataout AND NOT(niOiOii1i); + wire_nlli0OOOO_dataout <= wire_nllii110O_dataout AND NOT(niOiOii1i); + wire_nlli1000i_dataout <= wire_nlli10l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1000l_dataout <= wire_nlli10lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1000O_dataout <= wire_nlli10lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1001i_dataout <= wire_nlli10l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1001l_dataout <= wire_nlli10l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1001O_dataout <= wire_nlli10l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100i_dataout <= wire_nlli1l1i_o WHEN niOO01i0i = '1' ELSE nll0OilO; + wire_nlli100ii_dataout <= wire_nlli10liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100il_dataout <= wire_nlli10lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100iO_dataout <= wire_nlli10lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100l_dataout <= wire_nlliiiil_dataout WHEN niOO01i0i = '1' ELSE nliOlilO; + wire_nlli100li_dataout <= wire_nlli10llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100ll_dataout <= wire_nlli10lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100lO_dataout <= wire_nlli10lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100O_dataout <= niOO010ll WHEN niOO01i0i = '1' ELSE nll0OiOi; + wire_nlli100Oi_dataout <= wire_nlli10lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100Ol_dataout <= wire_nlli10O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli100OO_dataout <= wire_nlli10O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli101i_dataout <= wire_nlli1iOi_o WHEN niOO01i0i = '1' ELSE nll0Ol1l; + wire_nlli101l_dataout <= wire_nlli1iOl_o WHEN niOO01i0i = '1' ELSE nll0Ol1O; + wire_nlli101lO_dataout <= wire_nlli10iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli101O_dataout <= wire_nlli1iOO_o WHEN niOO01i0i = '1' ELSE nll0Ol0i; + wire_nlli101Oi_dataout <= wire_nlli10iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli101Ol_dataout <= wire_nlli10l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli101OO_dataout <= wire_nlli10l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10i0i_dataout <= wire_nlli10O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10i0l_dataout <= wire_nlli10Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10i0O_dataout <= wire_nlli10Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10i1i_dataout <= wire_nlli10O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10i1l_dataout <= wire_nlli10O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10i1O_dataout <= wire_nlli10O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10ii_dataout <= wire_nlli10iO_dataout WHEN niOO01i0i = '1' ELSE nll0OiOl; + wire_nlli10iii_dataout <= wire_nlli10OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10iil_dataout <= wire_nlli10Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10iiO_dataout <= wire_nlli10Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10il_dataout <= wire_nlli1iii_o WHEN niOO01i0i = '1' ELSE nll0OiOO; + wire_nlli10ili_dataout <= wire_nlli10OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10ill_dataout <= wire_nlli10OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10ilO_dataout <= wire_nlli10OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10iO_dataout <= wire_nlli01lO_dataout AND nll0Oiil; + wire_nlli10iOi_dataout <= wire_nlli10OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli10iOl_dataout <= wire_nllii0lii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11i1l; + wire_nlli10iOO_dataout <= wire_nllii0l0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11lli; + wire_nlli10l0i_dataout <= wire_nllii0l1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11lOl; + wire_nlli10l0l_dataout <= wire_nllii0l1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11lOO; + wire_nlli10l0O_dataout <= wire_nllii0iOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11O1i; + wire_nlli10l1i_dataout <= wire_nllii0l0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11lll; + wire_nlli10l1l_dataout <= wire_nllii0l0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11llO; + wire_nlli10l1O_dataout <= wire_nllii0l1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11lOi; + wire_nlli10lii_dataout <= wire_nllii0lOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11O1l; + wire_nlli10lil_dataout <= wire_nllii0lOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11O1O; + wire_nlli10liO_dataout <= wire_nllii0lOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11O0i; + wire_nlli10lli_dataout <= wire_nllii0llO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11O0l; + wire_nlli10lll_dataout <= wire_nllii0lll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11O0O; + wire_nlli10llO_dataout <= wire_nllii0lli_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11Oii; + wire_nlli10lOi_dataout <= wire_nllii0liO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11Oil; + wire_nlli10lOl_dataout <= wire_nllii0lil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11OiO; + wire_nlli10lOO_dataout <= wire_nllii0Oil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11Oli; + wire_nlli10O0i_dataout <= wire_nllii0O0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11OOl; + wire_nlli10O0l_dataout <= wire_nllii0O1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11OOO; + wire_nlli10O0O_dataout <= wire_nllii0O1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1011i; + wire_nlli10O1i_dataout <= wire_nllii0Oii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11Oll; + wire_nlli10O1l_dataout <= wire_nllii0O0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11OlO; + wire_nlli10O1O_dataout <= wire_nllii0O0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli11OOi; + wire_nlli10Oii_dataout <= wire_nllii0O1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1011l; + wire_nlli10Oil_dataout <= nlli0i0iO WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1011O; + wire_nlli10OiO_dataout <= nlli0i0il WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1010i; + wire_nlli10Oli_dataout <= nlli0i0ii WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1010l; + wire_nlli10Oll_dataout <= nlli0i00O WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli1010O; + wire_nlli10OlO_dataout <= nlli0i00l WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli101ii; + wire_nlli10OOi_dataout <= nlli0i00i WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli101il; + wire_nlli10OOl_dataout <= nlli0i01O WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli101iO; + wire_nlli10OOO_dataout <= nlli0i01l WHEN wire_nlOiOi11i_dataout = '1' ELSE nlli101li; + wire_nlli110i_dataout <= wire_nlli10Ol_o WHEN niOO01i0i = '1' ELSE nll0Oi1i; + wire_nlli110ii_dataout <= wire_nlli110il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli110il_dataout <= wire_nlli110iO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli110iO_dataout <= (wire_nl1000i_w_lg_nlli0iO1l36184w(0) AND (wire_nl1000i_w_lg_nlli0i01i36186w(0) OR wire_nl1000i_w_lg_nlli0i1OO36188w(0))) WHEN niOiOi01i = '1' ELSE nll0OOOOl; + wire_nlli110l_dataout <= wire_nlli10OO_o WHEN niOO01i0i = '1' ELSE nll0Oi1l; + wire_nlli110O_dataout <= wire_nlli1i1i_o WHEN niOO01i0i = '1' ELSE nll0Oi1O; + wire_nlli1110i_dataout <= wire_nlli111il_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli1110l_dataout <= wire_nlli111ll_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli1110O_dataout <= wire_nlli111li_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli1111i_dataout <= wire_nlli1110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1111l_dataout <= wire_nlli1110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1111O_dataout <= wire_nlli111ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli111i_dataout <= wire_nlli10ll_o WHEN niOO01i0i = '1' ELSE nll0O0Oi; + wire_nlli111ii_dataout <= wire_nlli111iO_dataout AND NOT(wire_nlOilO1OO_dataout); + wire_nlli111il_dataout <= (nlli0iO1l AND (nlli0i1lO OR nlli1OO1l)) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0Oii0i; + wire_nlli111iO_dataout <= (wire_nl1000i_w_lg_nlli0iO1l36221w(0) AND wire_w_lg_niOiOi1lO36222w(0)) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0OOOOi; + wire_nlli111l_dataout <= wire_nlli10lO_o WHEN niOO01i0i = '1' ELSE nll0O0Ol; + wire_nlli111li_dataout <= (nlli0iO1l AND (wire_nl1000i_w_lg_nlli0i01i36199w(0) OR wire_nl1000i_w_lg_nlli0i1OO36201w(0))) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0OOOlO; + wire_nlli111ll_dataout <= (nlli0iO1l AND niOiOi1lO) WHEN wire_nlOiOi11i_dataout = '1' ELSE nll0OOOll; + wire_nlli111O_dataout <= wire_nlli10Oi_o WHEN niOO01i0i = '1' ELSE nll0O0OO; + wire_nlli11i0i_dataout <= niOiOi01l WHEN niOiOi01i = '1' ELSE nlli1100O; + wire_nlli11i1O_dataout <= wire_nlli11i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli11ii_dataout <= wire_nlli1i1l_o WHEN niOO01i0i = '1' ELSE nll0Oi0i; + wire_nlli11il_dataout <= wire_nlli1i1O_o WHEN niOO01i0i = '1' ELSE nll0Oi0l; + wire_nlli11iO_dataout <= wire_nlli1i0i_o WHEN niOO01i0i = '1' ELSE nll0Oi0O; + wire_nlli11li_dataout <= wire_nlli1i0l_o WHEN niOO01i0i = '1' ELSE nll0Oiii; + wire_nlli11ll_dataout <= wire_nlli1i0O_o WHEN niOO01i0i = '1' ELSE nll0Ol1i; + wire_nlli11lO_dataout <= wire_nlli1iiO_o WHEN niOO01i0i = '1' ELSE nll0Oiil; + wire_nlli11Oi_dataout <= wire_nlli1ili_o WHEN niOO01i0i = '1' ELSE nll0OiiO; + wire_nlli11Ol_dataout <= wire_nlli1ill_o WHEN niOO01i0i = '1' ELSE nll0Oili; + wire_nlli11OO_dataout <= wire_nlli1ilO_o WHEN niOO01i0i = '1' ELSE nll0Oill; + wire_nlli1l0i_dataout <= wire_nlli0l0l_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1O0i_dataout; + wire_nlli1l0l_dataout <= wire_nlli0l0O_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1O0l_dataout; + wire_nlli1l0O_dataout <= wire_nlli0lii_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1O0O_dataout; + wire_nlli1l1l_dataout <= wire_nlli0l1O_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1O1l_dataout; + wire_nlli1l1O_dataout <= wire_nlli0l0i_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1O1O_dataout; + wire_nlli1lii_dataout <= wire_nlli0lil_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1Oii_dataout; + wire_nlli1lil_dataout <= wire_nlli0liO_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1Oil_dataout; + wire_nlli1liO_dataout <= wire_nlli0lli_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1OiO_dataout; + wire_nlli1lli_dataout <= wire_nlli0lll_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1Oli_dataout; + wire_nlli1lll_dataout <= wire_nlli0llO_dataout WHEN niOO010Oi = '1' ELSE wire_nlli1Oll_dataout; + wire_nlli1llO_dataout <= niOO01i1l WHEN niOO010Oi = '1' ELSE nll0OilO; + wire_nlli1lOi_dataout <= wire_nlli1OlO_dataout AND NOT(niOO010Oi); + wire_nlli1lOl_dataout <= wire_nlli1OOi_dataout AND NOT(niOO010Oi); + wire_nlli1lOO_dataout <= niOO01i1l WHEN niOO010Oi = '1' ELSE wire_nlli1OOl_dataout; + wire_nlli1O0i_dataout <= wire_nlli0iil_dataout WHEN nll0O0iOi = '1' ELSE nll0O0Ol; + wire_nlli1O0l_dataout <= wire_nlli0iiO_dataout WHEN nll0O0iOi = '1' ELSE nll0O0OO; + wire_nlli1O0O_dataout <= wire_nlli0ili_dataout WHEN nll0O0iOi = '1' ELSE nll0Oi1i; + wire_nlli1O1i_dataout <= wire_w_lg_niOO01i1l5387w(0) WHEN niOO010Oi = '1' ELSE wire_nlli1OOO_dataout; + wire_nlli1O1l_dataout <= wire_nlli0i0O_dataout WHEN nll0O0iOi = '1' ELSE nll0O0lO; + wire_nlli1O1O_dataout <= wire_nlli0iii_dataout WHEN nll0O0iOi = '1' ELSE nll0O0Oi; + wire_nlli1Oi0l_dataout <= wire_nlli1Oi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1Oi0O_dataout <= (wire_nl1000i_w_lg_nlli0i01i36177w(0) OR wire_nl1000i_w_lg_nlli0i1OO36179w(0)) AND NOT(wire_nlOilO1OO_dataout); + wire_nlli1Oii_dataout <= wire_nlli0ill_dataout WHEN nll0O0iOi = '1' ELSE nll0Oi1l; + wire_nlli1Oil_dataout <= wire_nlli0ilO_dataout WHEN nll0O0iOi = '1' ELSE nll0Oi1O; + wire_nlli1OiO_dataout <= wire_nlli0iOi_dataout WHEN nll0O0iOi = '1' ELSE nll0Oi0i; + wire_nlli1Oli_dataout <= wire_nlli0iOl_dataout WHEN nll0O0iOi = '1' ELSE nll0Oi0l; + wire_nlli1Oll_dataout <= wire_nlli0iOO_dataout WHEN nll0O0iOi = '1' ELSE nll0Oi0O; + wire_nlli1OlO_dataout <= nll0Oiil AND NOT(nll0O0iOi); + wire_nlli1OO0i_dataout <= wire_nlli011lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OO0l_dataout <= wire_nlli011Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OO0O_dataout <= wire_nlli011Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OO1O_dataout <= wire_nlli011ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOi_dataout <= nll0OiiO OR nll0O0iOi; + wire_nlli1OOii_dataout <= wire_nlli011OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOil_dataout <= wire_nlli0101i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOiO_dataout <= wire_nlli0101l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOl_dataout <= nll0Oili AND NOT(nll0O0iOi); + wire_nlli1OOli_dataout <= wire_nlli0101O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOll_dataout <= wire_nlli0100i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOlO_dataout <= wire_nlli0100l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOO_dataout <= nll0Oill AND NOT(nll0O0iOi); + wire_nlli1OOOi_dataout <= wire_nlli0100O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOOl_dataout <= wire_nlli010ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlli1OOOO_dataout <= wire_nlli01OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllii000i_dataout <= wire_nlOiO0lOi_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00ll_dataout; + wire_nllii000l_dataout <= wire_nlOiO0lOl_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00lO_dataout; + wire_nllii000O_dataout <= wire_nlOiO0lOO_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00Oi_dataout; + wire_nllii001i_dataout <= wire_nlOiO0lli_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00il_dataout; + wire_nllii001l_dataout <= wire_nlOiO0lll_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00iO_dataout; + wire_nllii001O_dataout <= wire_nlOiO0llO_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00li_dataout; + wire_nllii00i_dataout <= wire_nlliiiOl_dataout AND niOO01i1i; + wire_nllii00ii_dataout <= wire_nlOiO0O1i_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00Ol_dataout; + wire_nllii00il_dataout <= wire_nlOiO0O1l_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00OO_dataout; + wire_nllii00iO_dataout <= wire_nlOiO0O1O_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0i1i_dataout; + wire_nllii00l_dataout <= wire_nlliiiOO_dataout AND niOO01i1i; + wire_nllii00li_dataout <= wire_nlOiO0O0i_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0i1l_dataout; + wire_nllii00ll_dataout <= wire_nlOiO0O0l_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0i1O_dataout; + wire_nllii00lO_dataout <= wire_nlOiO0O0O_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0i0i_dataout; + wire_nllii00O_dataout <= wire_nlliil1i_dataout AND niOO01i1i; + wire_nllii00Oi_dataout <= wire_nlOiO0Oii_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0i0l_dataout; + wire_nllii00Ol_dataout <= wire_nlOiO0Oil_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0i0O_dataout; + wire_nllii00OO_dataout <= wire_nlOiO0OiO_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0iii_dataout; + wire_nllii010i_dataout <= wire_nlOiO0Oii_dataout WHEN niOiOiO0O = '1' ELSE nlliO11il; + wire_nllii010l_dataout <= wire_nlOiO0iOl_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO01lO_dataout; + wire_nllii010O_dataout <= wire_nlOiO0iOO_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO01Oi_dataout; + wire_nllii011i_dataout <= wire_nlOiO0O0i_dataout WHEN niOiOiO0O = '1' ELSE nlliO110l; + wire_nllii011l_dataout <= wire_nlOiO0O0l_dataout WHEN niOiOiO0O = '1' ELSE nlliO110O; + wire_nllii011O_dataout <= wire_nlOiO0O0O_dataout WHEN niOiOiO0O = '1' ELSE nlliO11ii; + wire_nllii01i_dataout <= wire_nllil10l_dataout WHEN niOO01i1l = '1' ELSE nll0Ol1O; + wire_nllii01ii_dataout <= wire_nlOiO0l1i_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO01Ol_dataout; + wire_nllii01il_dataout <= wire_nlOiO0l1l_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO01OO_dataout; + wire_nllii01iO_dataout <= wire_nlOiO0l1O_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO001i_dataout; + wire_nllii01l_dataout <= wire_nllil10O_dataout WHEN niOO01i1l = '1' ELSE nll0Ol0i; + wire_nllii01li_dataout <= wire_nlOiO0l0i_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO001l_dataout; + wire_nllii01ll_dataout <= wire_nlOiO0l0l_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO001O_dataout; + wire_nllii01lO_dataout <= wire_nlOiO0l0O_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO000i_dataout; + wire_nllii01O_dataout <= wire_nlliiiOi_dataout AND niOO01i1i; + wire_nllii01Oi_dataout <= wire_nlOiO0lii_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO000l_dataout; + wire_nllii01Ol_dataout <= wire_nlOiO0lil_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO000O_dataout; + wire_nllii01OO_dataout <= wire_nlOiO0liO_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO00ii_dataout; + wire_nllii0i0i_dataout <= wire_nlOiO0OOi_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0ill_dataout; + wire_nllii0i0l_dataout <= wire_nlOiO0OOl_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0ilO_dataout; + wire_nllii0i0O_dataout <= wire_nlOiO0OOO_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0iOi_dataout; + wire_nllii0i1i_dataout <= wire_nlOiO0Oli_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0iil_dataout; + wire_nllii0i1l_dataout <= wire_nlOiO0Oll_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0iiO_dataout; + wire_nllii0i1O_dataout <= wire_nlOiO0OlO_dataout WHEN niOiOii1l = '1' ELSE wire_nlOiO0ili_dataout; + wire_nllii0ii_dataout <= wire_nlliil1l_dataout AND niOO01i1i; + wire_nllii0iii_dataout <= nllilOlOO WHEN niOiOii1l = '1' ELSE wire_nlOiO0iOl_dataout; + wire_nllii0iil_dataout <= nllilOO1i WHEN niOiOii1l = '1' ELSE wire_nlOiO0iOO_dataout; + wire_nllii0iiO_dataout <= nllilOO1l WHEN niOiOii1l = '1' ELSE wire_nlOiO0l1i_dataout; + wire_nllii0il_dataout <= wire_nlliil1O_dataout AND niOO01i1i; + wire_nllii0ili_dataout <= nllilOO1O WHEN niOiOii1l = '1' ELSE wire_nlOiO0l1l_dataout; + wire_nllii0ill_dataout <= nllilOO0i WHEN niOiOii1l = '1' ELSE wire_nlOiO0l1O_dataout; + wire_nllii0ilO_dataout <= nllilOO0l WHEN niOiOii1l = '1' ELSE wire_nlOiO0l0i_dataout; + wire_nllii0iO_dataout <= wire_nlliil0i_dataout AND niOO01i1i; + wire_nllii0iOi_dataout <= nllilOO0O WHEN niOiOii1l = '1' ELSE wire_nlOiO0l0l_dataout; + wire_nllii0iOl_dataout <= nllilOOii WHEN niOiOii1l = '1' ELSE wire_nlOiO0l0O_dataout; + wire_nllii0iOO_dataout <= nllilOOil WHEN niOiOii1l = '1' ELSE wire_nlOiO0lii_dataout; + wire_nllii0l0i_dataout <= nllilOOlO WHEN niOiOii1l = '1' ELSE wire_nlOiO0lll_dataout; + wire_nllii0l0l_dataout <= nllilOOOi WHEN niOiOii1l = '1' ELSE wire_nlOiO0llO_dataout; + wire_nllii0l0O_dataout <= nllilOOOl WHEN niOiOii1l = '1' ELSE wire_nlOiO0lOi_dataout; + wire_nllii0l1i_dataout <= nllilOOiO WHEN niOiOii1l = '1' ELSE wire_nlOiO0lil_dataout; + wire_nllii0l1l_dataout <= nllilOOli WHEN niOiOii1l = '1' ELSE wire_nlOiO0liO_dataout; + wire_nllii0l1O_dataout <= nllilOOll WHEN niOiOii1l = '1' ELSE wire_nlOiO0lli_dataout; + wire_nllii0li_dataout <= wire_nlliil0l_dataout AND niOO01i1i; + wire_nllii0lii_dataout <= nllilOOOO WHEN niOiOii1l = '1' ELSE wire_nlOiO0lOl_dataout; + wire_nllii0lil_dataout <= nlliO111i WHEN niOiOii1l = '1' ELSE wire_nlOiO0lOO_dataout; + wire_nllii0liO_dataout <= nlliO111l WHEN niOiOii1l = '1' ELSE wire_nlOiO0O1i_dataout; + wire_nllii0ll_dataout <= wire_nlliil0O_dataout AND niOO01i1i; + wire_nllii0lli_dataout <= nlliO111O WHEN niOiOii1l = '1' ELSE wire_nlOiO0O1l_dataout; + wire_nllii0lll_dataout <= nlliO110i WHEN niOiOii1l = '1' ELSE wire_nlOiO0O1O_dataout; + wire_nllii0llO_dataout <= nlliO110l WHEN niOiOii1l = '1' ELSE wire_nlOiO0O0i_dataout; + wire_nllii0lO_dataout <= wire_nlliilii_dataout AND niOO01i1i; + wire_nllii0lOi_dataout <= nlliO110O WHEN niOiOii1l = '1' ELSE wire_nlOiO0O0l_dataout; + wire_nllii0lOl_dataout <= nlliO11ii WHEN niOiOii1l = '1' ELSE wire_nlOiO0O0O_dataout; + wire_nllii0lOO_dataout <= nlliO11il WHEN niOiOii1l = '1' ELSE wire_nlOiO0Oii_dataout; + wire_nllii0O0i_dataout <= nlliO11lO WHEN niOiOii1l = '1' ELSE wire_nlOiO0Oll_dataout; + wire_nllii0O0l_dataout <= nlliO11Oi WHEN niOiOii1l = '1' ELSE wire_nlOiO0OlO_dataout; + wire_nllii0O0O_dataout <= nlliO11Ol WHEN niOiOii1l = '1' ELSE wire_nlOiO0OOi_dataout; + wire_nllii0O1i_dataout <= nlliO11iO WHEN niOiOii1l = '1' ELSE wire_nlOiO0Oil_dataout; + wire_nllii0O1l_dataout <= nlliO11li WHEN niOiOii1l = '1' ELSE wire_nlOiO0OiO_dataout; + wire_nllii0O1O_dataout <= nlliO11ll WHEN niOiOii1l = '1' ELSE wire_nlOiO0Oli_dataout; + wire_nllii0Oii_dataout <= nlliO11OO WHEN niOiOii1l = '1' ELSE wire_nlOiO0OOl_dataout; + wire_nllii0Oil_dataout <= nlliO101i WHEN niOiOii1l = '1' ELSE wire_nlOiO0OOO_dataout; + wire_nllii0OOi_dataout <= wire_nlliii00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllii0OOl_dataout <= ((wire_nlOiOi11i_dataout AND wire_nlOiii10i_dataout) AND wire_w_lg_niOiOil0l35920w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nllii100i_dataout <= wire_nlOiO01OO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01il_dataout; + wire_nllii100l_dataout <= wire_nlOiO001i_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01iO_dataout; + wire_nllii100O_dataout <= wire_nlOiO001l_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01li_dataout; + wire_nllii101i_dataout <= wire_nlOiO01lO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii010l_dataout; + wire_nllii101l_dataout <= wire_nlOiO01Oi_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii010O_dataout; + wire_nllii101O_dataout <= wire_nlOiO01Ol_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01ii_dataout; + wire_nllii10i_dataout <= wire_nllii0il_dataout WHEN niOO01i1l = '1' ELSE nll0Oi1l; + wire_nllii10ii_dataout <= wire_nlOiO001O_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01ll_dataout; + wire_nllii10il_dataout <= wire_nlOiO000i_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01lO_dataout; + wire_nllii10iO_dataout <= wire_nlOiO000l_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01Oi_dataout; + wire_nllii10l_dataout <= wire_nllii0iO_dataout WHEN niOO01i1l = '1' ELSE nll0Oi1O; + wire_nllii10li_dataout <= wire_nlOiO000O_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01Ol_dataout; + wire_nllii10ll_dataout <= wire_nlOiO00ii_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii01OO_dataout; + wire_nllii10lO_dataout <= wire_nlOiO00il_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii001i_dataout; + wire_nllii10O_dataout <= wire_nllii0li_dataout WHEN niOO01i1l = '1' ELSE nll0Oi0i; + wire_nllii10Oi_dataout <= wire_nlOiO00iO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii001l_dataout; + wire_nllii10Ol_dataout <= wire_nlOiO00li_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii001O_dataout; + wire_nllii10OO_dataout <= wire_nlOiO00ll_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii000i_dataout; + wire_nllii110i_dataout <= wire_nllii11li_dataout WHEN niOiOi0OO = '1' ELSE nlli0i1lO; + wire_nllii110l_dataout <= wire_nllii11ll_dataout WHEN niOiOi0OO = '1' ELSE nlli0i1Oi; + wire_nllii110O_dataout <= wire_nllii11lO_dataout WHEN niOiOi0OO = '1' ELSE nlli0i1Ol; + wire_nllii111i_dataout <= wire_nllii11ii_dataout AND NOT(niOiOii1i); + wire_nllii111l_dataout <= wire_nllii11il_dataout AND NOT(niOiOii1i); + wire_nllii111O_dataout <= wire_nllii11iO_dataout WHEN niOiOi0OO = '1' ELSE nlli1OO1l; + wire_nllii11i_dataout <= wire_nllii00l_dataout WHEN niOO01i1l = '1' ELSE nll0O0Ol; + wire_nllii11ii_dataout <= wire_nllii11Oi_dataout WHEN niOiOi0OO = '1' ELSE nlli0i1OO; + wire_nllii11il_dataout <= wire_nllii11Ol_dataout WHEN niOiOi0OO = '1' ELSE nlli0i01i; + wire_nllii11iO_dataout <= niOiOil0l WHEN wire_nl1000i_w_lg_nlli0ilOi35930w(0) = '1' ELSE niOiOil0O; + wire_nllii11l_dataout <= wire_nllii00O_dataout WHEN niOO01i1l = '1' ELSE nll0O0OO; + wire_nllii11li_dataout <= niOiOil0O WHEN wire_nl1000i_w_lg_nlli0ilOi35930w(0) = '1' ELSE nllilil0O; + wire_nllii11ll_dataout <= niOiOilll WHEN wire_nl1000i_w_lg_nlli0ilOi35930w(0) = '1' ELSE niOiOilOi; + wire_nllii11lO_dataout <= niOiOilOi WHEN wire_nl1000i_w_lg_nlli0ilOi35930w(0) = '1' ELSE nllilOllO; + wire_nllii11O_dataout <= wire_nllii0ii_dataout WHEN niOO01i1l = '1' ELSE nll0Oi1i; + wire_nllii11Oi_dataout <= niOiOilii WHEN wire_nl1000i_w_lg_nlli0ilOi35930w(0) = '1' ELSE niOiOiliO; + wire_nllii11Ol_dataout <= niOiOiliO WHEN wire_nl1000i_w_lg_nlli0ilOi35930w(0) = '1' ELSE nllilOlll; + wire_nllii1i0i_dataout <= wire_nlOiO00OO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00il_dataout; + wire_nllii1i0l_dataout <= wire_nlOiO0i1i_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00iO_dataout; + wire_nllii1i0O_dataout <= wire_nlOiO0i1l_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00li_dataout; + wire_nllii1i1i_dataout <= wire_nlOiO00lO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii000l_dataout; + wire_nllii1i1l_dataout <= wire_nlOiO00Oi_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii000O_dataout; + wire_nllii1i1O_dataout <= wire_nlOiO00Ol_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00ii_dataout; + wire_nllii1ii_dataout <= wire_nllii0ll_dataout WHEN niOO01i1l = '1' ELSE nll0Oi0l; + wire_nllii1iii_dataout <= wire_nlOiO0i1O_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00ll_dataout; + wire_nllii1iil_dataout <= wire_nlOiO0i0i_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00lO_dataout; + wire_nllii1iiO_dataout <= wire_nlOiO0i0l_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00Oi_dataout; + wire_nllii1il_dataout <= wire_nllii0lO_dataout WHEN niOO01i1l = '1' ELSE nll0Oi0O; + wire_nllii1ili_dataout <= wire_nlOiO0i0O_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00Ol_dataout; + wire_nllii1ill_dataout <= wire_nlOiO0iii_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii00OO_dataout; + wire_nllii1ilO_dataout <= wire_nlOiO0iil_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0i1i_dataout; + wire_nllii1iO_dataout <= wire_w_lg_w_k_hip_range2413w5340w(0) WHEN niOO01i1l = '1' ELSE nll0Oiii; + wire_nllii1iOi_dataout <= wire_nlOiO0iiO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0i1l_dataout; + wire_nllii1iOl_dataout <= wire_nlOiO0ili_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0i1O_dataout; + wire_nllii1iOO_dataout <= wire_nlOiO0ill_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0i0i_dataout; + wire_nllii1l0i_dataout <= wire_nlOiO0iOO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0iil_dataout; + wire_nllii1l0l_dataout <= wire_nlOiO0l1i_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0iiO_dataout; + wire_nllii1l0O_dataout <= wire_nlOiO0l1l_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0ili_dataout; + wire_nllii1l1i_dataout <= wire_nlOiO0ilO_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0i0l_dataout; + wire_nllii1l1l_dataout <= wire_nlOiO0iOi_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0i0O_dataout; + wire_nllii1l1O_dataout <= wire_nlOiO0iOl_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0iii_dataout; + wire_nllii1li_dataout <= nll0Ol1i OR niOO01i1l; + wire_nllii1lii_dataout <= wire_nlOiO0l1O_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0ill_dataout; + wire_nllii1lil_dataout <= wire_nlOiO0l0i_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0ilO_dataout; + wire_nllii1liO_dataout <= wire_nlOiO0l0l_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0iOi_dataout; + wire_nllii1ll_dataout <= nll0Oiil AND NOT(niOO01i1l); + wire_nllii1lli_dataout <= wire_nlOiO0l0O_dataout WHEN niOiOiO0O = '1' ELSE wire_nllii0iOl_dataout; + wire_nllii1lll_dataout <= wire_nllii1llO_dataout OR nlli0ilOO; + wire_nllii1llO_dataout <= nlli0iO1l AND NOT(niOiOii1i); + wire_nllii1lO_dataout <= nll0OiiO AND NOT(niOO01i1l); + wire_nllii1O0i_dataout <= wire_nlOiO0lii_dataout WHEN niOiOiO0O = '1' ELSE nllilOOil; + wire_nllii1O0l_dataout <= wire_nlOiO0lil_dataout WHEN niOiOiO0O = '1' ELSE nllilOOiO; + wire_nllii1O0O_dataout <= wire_nlOiO0liO_dataout WHEN niOiOiO0O = '1' ELSE nllilOOli; + wire_nllii1O1O_dataout <= wire_nlOiO0l0i_dataout WHEN niOiOiO0O = '1' ELSE nllilOO0l; + wire_nllii1Oi_dataout <= nll0Oili OR niOO01i1l; + wire_nllii1Oii_dataout <= wire_nlOiO0lli_dataout WHEN niOiOiO0O = '1' ELSE nllilOOll; + wire_nllii1Oil_dataout <= wire_nlOiO0lll_dataout WHEN niOiOiO0O = '1' ELSE nllilOOlO; + wire_nllii1OiO_dataout <= wire_nlOiO0llO_dataout WHEN niOiOiO0O = '1' ELSE nllilOOOi; + wire_nllii1Ol_dataout <= nll0Oill AND NOT(niOO01i1l); + wire_nllii1Oli_dataout <= wire_nlOiO0lOi_dataout WHEN niOiOiO0O = '1' ELSE nllilOOOl; + wire_nllii1Oll_dataout <= wire_nlOiO0lOl_dataout WHEN niOiOiO0O = '1' ELSE nllilOOOO; + wire_nllii1OlO_dataout <= wire_nlOiO0lOO_dataout WHEN niOiOiO0O = '1' ELSE nlliO111i; + wire_nllii1OO_dataout <= wire_nllil10i_dataout WHEN niOO01i1l = '1' ELSE nll0Ol1l; + wire_nllii1OOi_dataout <= wire_nlOiO0O1i_dataout WHEN niOiOiO0O = '1' ELSE nlliO111l; + wire_nllii1OOl_dataout <= wire_nlOiO0O1l_dataout WHEN niOiOiO0O = '1' ELSE nlliO111O; + wire_nllii1OOO_dataout <= wire_nlOiO0O1O_dataout WHEN niOiOiO0O = '1' ELSE nlliO110i; + wire_nlliii00O_dataout <= wire_nlliii0ii_dataout OR ((niOiOiO0O OR niOiOiO0i) AND wire_nlOiOi11i_dataout); + wire_nlliii0ii_dataout <= nlli0iO1O AND NOT((((niOiOiliO OR niOiOilii) AND wire_nlOiOi11i_dataout) OR wire_nlOilO1OO_dataout)); + wire_nlliiiil_dataout <= wire_nlliiiiO_dataout OR niOO01i1O; + wire_nlliiiiO_dataout <= nliOlilO AND NOT((nll0OiOO OR nll0OiOl)); + wire_nlliiilOO_dataout <= nllili00i AND NOT(wire_niO01O0O_dataout); + wire_nlliiiO0i_dataout <= nllili0il AND NOT(wire_niO01O0O_dataout); + wire_nlliiiO0l_dataout <= nllili0iO AND NOT(wire_niO01O0O_dataout); + wire_nlliiiO0O_dataout <= nllili0li AND NOT(wire_niO01O0O_dataout); + wire_nlliiiO1i_dataout <= nllili00l AND NOT(wire_niO01O0O_dataout); + wire_nlliiiO1l_dataout <= nllili00O AND NOT(wire_niO01O0O_dataout); + wire_nlliiiO1O_dataout <= nllili0ii AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOi_dataout <= nll0Oi11l WHEN niOO01iil = '1' ELSE wire_nlliilil_dataout; + wire_nlliiiOii_dataout <= nllili0ll AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOil_dataout <= nllili0lO AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOiO_dataout <= nllili0Oi AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOl_dataout <= nll0Oi11O WHEN niOO01iil = '1' ELSE wire_nlliiliO_dataout; + wire_nlliiiOli_dataout <= nllili0Ol AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOll_dataout <= nllili0OO AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOlO_dataout <= nllilii1O AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOO_dataout <= nll0Oi10i WHEN niOO01iil = '1' ELSE wire_nlliilli_dataout; + wire_nlliiiOOi_dataout <= nllilii0i AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOOl_dataout <= nllilii0l AND NOT(wire_niO01O0O_dataout); + wire_nlliiiOOO_dataout <= nllilii0O AND NOT(wire_niO01O0O_dataout); + wire_nlliil00i_dataout <= niOiOiili AND niOiOii0i; + wire_nlliil01i_dataout <= wire_nlOiOi11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliil01l_dataout <= niOiOiiil AND niOiOii0i; + wire_nlliil01O_dataout <= niOiOiiiO AND niOiOii0i; + wire_nlliil0i_dataout <= nll0Oi1il WHEN niOO01iil = '1' ELSE wire_nlliilOl_dataout; + wire_nlliil0l_dataout <= nll0Oi1iO WHEN niOO01iil = '1' ELSE wire_nlliilOO_dataout; + wire_nlliil0O_dataout <= nll0Oi1li WHEN niOO01iil = '1' ELSE wire_nlliiO1i_dataout; + wire_nlliil10i_dataout <= nlliliili AND NOT(wire_niO01O0O_dataout); + wire_nlliil10l_dataout <= nlliliiOi AND NOT(wire_niO01O0O_dataout); + wire_nlliil10O_dataout <= nlliliiOl AND NOT(wire_niO01O0O_dataout); + wire_nlliil11i_dataout <= nlliliiii AND NOT(wire_niO01O0O_dataout); + wire_nlliil11l_dataout <= nlliliiil AND NOT(wire_niO01O0O_dataout); + wire_nlliil11O_dataout <= nlliliiiO AND NOT(wire_niO01O0O_dataout); + wire_nlliil1i_dataout <= nll0Oi10l WHEN niOO01iil = '1' ELSE wire_nlliilll_dataout; + wire_nlliil1ii_dataout <= nlliliiOO AND NOT(wire_niO01O0O_dataout); + wire_nlliil1il_dataout <= nllilil1l AND NOT(wire_niO01O0O_dataout); + wire_nlliil1iO_dataout <= nllilil1O AND NOT(wire_niO01O0O_dataout); + wire_nlliil1l_dataout <= nll0Oi10O WHEN niOO01iil = '1' ELSE wire_nlliillO_dataout; + wire_nlliil1li_dataout <= nllilil0i AND NOT(wire_niO01O0O_dataout); + wire_nlliil1ll_dataout <= nllilil0l AND NOT(wire_niO01O0O_dataout); + wire_nlliil1lO_dataout <= wire_nlliil01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliil1O_dataout <= nll0Oi1ii WHEN niOO01iil = '1' ELSE wire_nlliilOi_dataout; + wire_nlliil1Oi_dataout <= wire_nlliil01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliil1Ol_dataout <= wire_nlliil00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliil1OO_dataout <= (wire_w_lg_niOiOii0O35888w(0) AND (nlliiilOl AND nlliiilOi)) AND NOT(wire_niO01O0O_dataout); + wire_nlliilii_dataout <= nll0Oi1ll WHEN niOO01iil = '1' ELSE wire_nlliiO1l_dataout; + wire_nlliilil_dataout <= wire_nlliiOOO_o(0) WHEN niOO01iii = '1' ELSE wire_nlliiO1O_dataout; + wire_nlliiliO_dataout <= wire_nlliiOOO_o(1) WHEN niOO01iii = '1' ELSE wire_nlliiO0i_dataout; + wire_nlliilli_dataout <= wire_nlliiOOO_o(2) WHEN niOO01iii = '1' ELSE wire_nlliiO0l_dataout; + wire_nlliilll_dataout <= wire_nlliiOOO_o(3) WHEN niOO01iii = '1' ELSE wire_nlliiO0O_dataout; + wire_nlliillO_dataout <= wire_nlliiOOO_o(4) WHEN niOO01iii = '1' ELSE wire_nlliiOii_dataout; + wire_nlliilOi_dataout <= wire_nlliiOOO_o(5) WHEN niOO01iii = '1' ELSE wire_nlliiOil_dataout; + wire_nlliilOl_dataout <= wire_nlliiOOO_o(6) WHEN niOO01iii = '1' ELSE wire_nlliiOiO_dataout; + wire_nlliilOO_dataout <= wire_nlliiOOO_o(7) WHEN niOO01iii = '1' ELSE wire_nlliiOli_dataout; + wire_nlliiO0i_dataout <= wire_nlliiOOi_o(2) WHEN niOO01i0O = '1' ELSE nll0Oi11O; + wire_nlliiO0l_dataout <= wire_nlliiOOi_o(3) WHEN niOO01i0O = '1' ELSE nll0Oi10i; + wire_nlliiO0O_dataout <= wire_nlliiOOi_o(4) WHEN niOO01i0O = '1' ELSE nll0Oi10l; + wire_nlliiO1i_dataout <= wire_nlliiOOO_o(8) WHEN niOO01iii = '1' ELSE wire_nlliiOll_dataout; + wire_nlliiO1l_dataout <= wire_nlliiOOO_o(9) WHEN niOO01iii = '1' ELSE wire_nlliiOlO_dataout; + wire_nlliiO1O_dataout <= wire_nlliiOOi_o(1) WHEN niOO01i0O = '1' ELSE nll0Oi11l; + wire_nlliiOii_dataout <= wire_nlliiOOi_o(5) WHEN niOO01i0O = '1' ELSE nll0Oi10O; + wire_nlliiOil_dataout <= wire_nlliiOOi_o(6) WHEN niOO01i0O = '1' ELSE nll0Oi1ii; + wire_nlliiOiO_dataout <= wire_nlliiOOi_o(7) WHEN niOO01i0O = '1' ELSE nll0Oi1il; + wire_nlliiOli_dataout <= wire_nlliiOOi_o(8) WHEN niOO01i0O = '1' ELSE nll0Oi1iO; + wire_nlliiOll_dataout <= wire_nlliiOOi_o(9) WHEN niOO01i0O = '1' ELSE nll0Oi1li; + wire_nlliiOlO_dataout <= wire_nlliiOOi_o(10) WHEN niOO01i0O = '1' ELSE nll0Oi1ll; + wire_nllil00i_dataout <= nl1i110i WHEN niOO01iOO = '1' ELSE wire_nllil0ii_dataout; + wire_nllil00l_dataout <= nl1i110l WHEN niOO01iOO = '1' ELSE wire_nllil0il_dataout; + wire_nllil00O_dataout <= nl1i110O WHEN niOO01iOO = '1' ELSE wire_nllil0iO_dataout; + wire_nllil01i_dataout <= nl1i111i WHEN niOO01iOl = '1' ELSE wire_nllil00i_dataout; + wire_nllil01l_dataout <= nl1i111l WHEN niOO01iOl = '1' ELSE wire_nllil00l_dataout; + wire_nllil01O_dataout <= nl1i111O WHEN niOO01iOl = '1' ELSE wire_nllil00O_dataout; + wire_nllil0ii_dataout <= nl1i11ii WHEN niOO01l1i = '1' ELSE nl1i11li; + wire_nllil0il_dataout <= nl1i11il WHEN niOO01l1i = '1' ELSE nl1i11ll; + wire_nllil0iO_dataout <= nl1i11iO WHEN niOO01l1i = '1' ELSE nl1i11lO; + wire_nllil0lO_dataout <= niOO01l1O OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nllil0lO_w_lg_dataout8888w(0) <= NOT wire_nllil0lO_dataout; + wire_nllil10i_dataout <= wire_nllil1ii_dataout AND NOT(niOO01ili); + wire_nllil10l_dataout <= wire_nllil1il_dataout AND NOT(niOO01ili); + wire_nllil10O_dataout <= wire_nllil1iO_dataout AND NOT(niOO01ili); + wire_nllil1ii_dataout <= nl10OOii WHEN niOO01ill = '1' ELSE wire_nllil1li_dataout; + wire_nllil1il_dataout <= nl10OOil WHEN niOO01ill = '1' ELSE wire_nllil1ll_dataout; + wire_nllil1iO_dataout <= nl10OOiO WHEN niOO01ill = '1' ELSE wire_nllil1lO_dataout; + wire_nllil1li_dataout <= nl10OOli WHEN niOO01ilO = '1' ELSE wire_nllil1Oi_dataout; + wire_nllil1ll_dataout <= nl10OOll WHEN niOO01ilO = '1' ELSE wire_nllil1Ol_dataout; + wire_nllil1lO_dataout <= nl10OOlO WHEN niOO01ilO = '1' ELSE wire_nllil1OO_dataout; + wire_nllil1Oi_dataout <= nl10OOOi WHEN niOO01iOi = '1' ELSE wire_nllil01i_dataout; + wire_nllil1Ol_dataout <= nl10OOOl WHEN niOO01iOi = '1' ELSE wire_nllil01l_dataout; + wire_nllil1OO_dataout <= nl10OOOO WHEN niOO01iOi = '1' ELSE wire_nllil01O_dataout; + wire_nllililii_dataout <= (((niOiOiO1l AND niOiOilii) AND (NOT (niOiOil0l OR (niOiOil0O OR niOiOil0i)))) OR ((niOiOiliO AND nllilOlOi) AND (NOT (niOiOil0O OR (nllilil0O OR niOiOil1O))))) AND NOT(wire_niO01O0O_dataout); + wire_nllililil_dataout <= wire_nllilli0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllililiO_dataout <= wire_nllilli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllililli_dataout <= wire_nllilliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllililll_dataout <= wire_nllilliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllilillO_dataout <= wire_nllilliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllililOi_dataout <= wire_nllillili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllililOl_dataout <= wire_nllillill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllililOO_dataout <= wire_nllillilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliO0i_dataout <= wire_nllilll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliO0l_dataout <= wire_nllilll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliO0O_dataout <= wire_nllilll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliO1i_dataout <= wire_nllilliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliO1l_dataout <= wire_nllilliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliO1O_dataout <= wire_nllilliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOii_dataout <= wire_nllilll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOil_dataout <= wire_nllilll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOiO_dataout <= wire_nllilll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOli_dataout <= wire_nllilllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOll_dataout <= wire_nllilllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOlO_dataout <= wire_nllillliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOOi_dataout <= wire_nllilllli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOOl_dataout <= wire_nllilllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliliOOO_dataout <= wire_nllillllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill00i_dataout <= wire_nllilO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill00l_dataout <= wire_nllilO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill00O_dataout <= wire_nllilO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill01i_dataout <= wire_nllillOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill01l_dataout <= wire_nllillOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill01O_dataout <= wire_nllillOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill0ii_dataout <= wire_nllilO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill0il_dataout <= wire_nllilO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill0iO_dataout <= wire_nllilO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill0li_dataout <= wire_nllilO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill10i_dataout <= wire_nllillO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill10l_dataout <= wire_nllillO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill10O_dataout <= wire_nllillO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill11i_dataout <= wire_nllilllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill11l_dataout <= wire_nllilllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill11O_dataout <= wire_nllilllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1ii_dataout <= wire_nllillO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1il_dataout <= wire_nllillO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1iO_dataout <= wire_nllillO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1li_dataout <= wire_nllillOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1ll_dataout <= wire_nllillOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1lO_dataout <= wire_nllillOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1Oi_dataout <= wire_nllillOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1Ol_dataout <= wire_nllillOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllill1OO_dataout <= wire_nllillOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllilli0l_dataout <= wire_nllilO1il_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili11O; + wire_nllilli0O_dataout <= wire_nllilO1iO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili10i; + wire_nllilliii_dataout <= wire_nllilO1li_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili10l; + wire_nllilliil_dataout <= wire_nllilO1ll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili10O; + wire_nllilliiO_dataout <= wire_nllilO1lO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1ii; + wire_nllillil_dataout <= (nllillOl OR (nliO0iil OR nli1i1ll)) WHEN (nl1OilOii AND nlliO01l) = '1' ELSE wire_nllilliO_dataout; + wire_nllillil_w_lg_dataout55059w(0) <= NOT wire_nllillil_dataout; + wire_nllillili_dataout <= wire_nllilO1Oi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1il; + wire_nllillill_dataout <= wire_nllilO1Ol_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1iO; + wire_nllillilO_dataout <= wire_nllilO1OO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1li; + wire_nllilliO_dataout <= nliO0iil WHEN nlliO01i = '1' ELSE nli1i1ll; + wire_nllilliOi_dataout <= wire_nllilO01i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1ll; + wire_nllilliOl_dataout <= wire_nllilO01l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1lO; + wire_nllilliOO_dataout <= wire_nllilO01O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1Oi; + wire_nllilll0i_dataout <= wire_nllilO0ii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili01l; + wire_nllilll0l_dataout <= wire_nllilO0il_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili01O; + wire_nllilll0O_dataout <= wire_nllilO0iO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili00i; + wire_nllilll1i_dataout <= wire_nllilO00i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1Ol; + wire_nllilll1l_dataout <= wire_nllilO00l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili1OO; + wire_nllilll1O_dataout <= wire_nllilO00O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili01i; + wire_nllilllii_dataout <= wire_nllilO0li_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili00l; + wire_nllilllil_dataout <= wire_nllilO0ll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili00O; + wire_nllillliO_dataout <= wire_nllilO0lO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0ii; + wire_nllilllli_dataout <= wire_nllilO0Oi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0il; + wire_nllilllll_dataout <= wire_nllilO0Ol_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0iO; + wire_nllillllO_dataout <= wire_nllilO0OO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0li; + wire_nllilllOi_dataout <= wire_nllilOi1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0ll; + wire_nllilllOl_dataout <= wire_nllilOi1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0lO; + wire_nllilllOO_dataout <= wire_nllilOi1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0Oi; + wire_nllillO0i_dataout <= wire_nllilOiii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilii1l; + wire_nllillO0l_dataout <= wire_nllilOiil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilii1O; + wire_nllillO0O_dataout <= wire_nllilOiiO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilii0i; + wire_nllillO1i_dataout <= wire_nllilOi0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0Ol; + wire_nllillO1l_dataout <= wire_nllilOi0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllili0OO; + wire_nllillO1O_dataout <= wire_nllilOi0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilii1i; + wire_nllillOii_dataout <= wire_nllilOili_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilii0l; + wire_nllillOil_dataout <= wire_nllilOill_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilii0O; + wire_nllillOiO_dataout <= wire_nllilOilO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliiii; + wire_nllillOli_dataout <= wire_nllilOiOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliiil; + wire_nllillOll_dataout <= wire_nllilOiOl_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliiiO; + wire_nllillOlO_dataout <= wire_nllilOiOO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliili; + wire_nllillOOi_dataout <= wire_nllilOl1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliill; + wire_nllillOOl_dataout <= wire_nllilOl1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliilO; + wire_nllillOOO_dataout <= wire_nllilOl1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliiOi; + wire_nllilO00i_dataout <= wire_nlOiO0O1O_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0i1i_dataout; + wire_nllilO00l_dataout <= wire_nlOiO0O0i_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0i1l_dataout; + wire_nllilO00O_dataout <= wire_nlOiO0O0l_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0i1O_dataout; + wire_nllilO01i_dataout <= wire_nlOiO0lOO_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00Oi_dataout; + wire_nllilO01l_dataout <= wire_nlOiO0O1i_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00Ol_dataout; + wire_nllilO01O_dataout <= wire_nlOiO0O1l_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00OO_dataout; + wire_nllilO0ii_dataout <= wire_nlOiO0O0O_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0i0i_dataout; + wire_nllilO0il_dataout <= wire_nlOiO0Oii_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0i0l_dataout; + wire_nllilO0iO_dataout <= wire_nlOiO0Oil_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0i0O_dataout; + wire_nllilO0li_dataout <= wire_nlOiO0OiO_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0iii_dataout; + wire_nllilO0ll_dataout <= wire_nlOiO0Oli_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0iil_dataout; + wire_nllilO0lO_dataout <= wire_nlOiO0Oll_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0iiO_dataout; + wire_nllilO0Oi_dataout <= wire_nlOiO0OlO_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0ili_dataout; + wire_nllilO0Ol_dataout <= wire_nlOiO0OOi_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0ill_dataout; + wire_nllilO0OO_dataout <= wire_nlOiO0OOl_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0ilO_dataout; + wire_nllilO10i_dataout <= wire_nllilOlii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilil1l; + wire_nllilO10l_dataout <= wire_nllilOlil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilil1O; + wire_nllilO10O_dataout <= wire_nllilOliO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilil0i; + wire_nllilO11i_dataout <= wire_nllilOl0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliiOl; + wire_nllilO11l_dataout <= wire_nllilOl0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliliiOO; + wire_nllilO11O_dataout <= wire_nllilOl0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilil1i; + wire_nllilO1ii_dataout <= wire_nllilOlli_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilil0l; + wire_nllilO1il_dataout <= wire_nlOiO0lii_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO000l_dataout; + wire_nllilO1iO_dataout <= wire_nlOiO0lil_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO000O_dataout; + wire_nllilO1li_dataout <= wire_nlOiO0liO_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00ii_dataout; + wire_nllilO1ll_dataout <= wire_nlOiO0lli_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00il_dataout; + wire_nllilO1lO_dataout <= wire_nlOiO0lll_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00iO_dataout; + wire_nllilO1Oi_dataout <= wire_nlOiO0llO_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00li_dataout; + wire_nllilO1Ol_dataout <= wire_nlOiO0lOi_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00ll_dataout; + wire_nllilO1OO_dataout <= wire_nlOiO0lOl_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO00lO_dataout; + wire_nllilOi0i_dataout <= nllilOO1l WHEN nllilOlOi = '1' ELSE wire_nlOiO0l1i_dataout; + wire_nllilOi0l_dataout <= nllilOO1O WHEN nllilOlOi = '1' ELSE wire_nlOiO0l1l_dataout; + wire_nllilOi0O_dataout <= nllilOO0i WHEN nllilOlOi = '1' ELSE wire_nlOiO0l1O_dataout; + wire_nllilOi1i_dataout <= wire_nlOiO0OOO_dataout WHEN nllilOlOi = '1' ELSE wire_nlOiO0iOi_dataout; + wire_nllilOi1l_dataout <= nllilOlOO WHEN nllilOlOi = '1' ELSE wire_nlOiO0iOl_dataout; + wire_nllilOi1O_dataout <= nllilOO1i WHEN nllilOlOi = '1' ELSE wire_nlOiO0iOO_dataout; + wire_nllilOiii_dataout <= nllilOO0l WHEN nllilOlOi = '1' ELSE wire_nlOiO0l0i_dataout; + wire_nllilOiil_dataout <= nllilOO0O WHEN nllilOlOi = '1' ELSE wire_nlOiO0l0l_dataout; + wire_nllilOiiO_dataout <= nllilOOii WHEN nllilOlOi = '1' ELSE wire_nlOiO0l0O_dataout; + wire_nllilOili_dataout <= nllilOOil WHEN nllilOlOi = '1' ELSE wire_nlOiO0lii_dataout; + wire_nllilOill_dataout <= nllilOOiO WHEN nllilOlOi = '1' ELSE wire_nlOiO0lil_dataout; + wire_nllilOilO_dataout <= nllilOOli WHEN nllilOlOi = '1' ELSE wire_nlOiO0liO_dataout; + wire_nllilOiOi_dataout <= nllilOOll WHEN nllilOlOi = '1' ELSE wire_nlOiO0lli_dataout; + wire_nllilOiOl_dataout <= nllilOOlO WHEN nllilOlOi = '1' ELSE wire_nlOiO0lll_dataout; + wire_nllilOiOO_dataout <= nllilOOOi WHEN nllilOlOi = '1' ELSE wire_nlOiO0llO_dataout; + wire_nllilOl0i_dataout <= nlliO111l WHEN nllilOlOi = '1' ELSE wire_nlOiO0O1i_dataout; + wire_nllilOl0l_dataout <= nlliO111O WHEN nllilOlOi = '1' ELSE wire_nlOiO0O1l_dataout; + wire_nllilOl0O_dataout <= nlliO110i WHEN nllilOlOi = '1' ELSE wire_nlOiO0O1O_dataout; + wire_nllilOl1i_dataout <= nllilOOOl WHEN nllilOlOi = '1' ELSE wire_nlOiO0lOi_dataout; + wire_nllilOl1l_dataout <= nllilOOOO WHEN nllilOlOi = '1' ELSE wire_nlOiO0lOl_dataout; + wire_nllilOl1O_dataout <= nlliO111i WHEN nllilOlOi = '1' ELSE wire_nlOiO0lOO_dataout; + wire_nllilOlii_dataout <= nlliO110l WHEN nllilOlOi = '1' ELSE wire_nlOiO0O0i_dataout; + wire_nllilOlil_dataout <= nlliO110O WHEN nllilOlOi = '1' ELSE wire_nlOiO0O0l_dataout; + wire_nllilOliO_dataout <= nlliO11ii WHEN nllilOlOi = '1' ELSE wire_nlOiO0O0O_dataout; + wire_nllilOlli_dataout <= nlliO11il WHEN nllilOlOi = '1' ELSE wire_nlOiO0Oii_dataout; + wire_nlliO00i_dataout <= wire_nlll11ii_dataout AND NOT(niOO01lOO); + wire_nlliO00l_dataout <= wire_nlll11il_dataout AND NOT(niOO01lOO); + wire_nlliO00O_dataout <= wire_nlll11Ol_dataout AND NOT(niOO01lOO); + wire_nlliO010i_dataout <= wire_nlOiO0i1l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO110l; + wire_nlliO010l_dataout <= wire_nlOiO0i1O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO110O; + wire_nlliO010O_dataout <= wire_nlOiO0i0i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11ii; + wire_nlliO011i_dataout <= wire_nlOiO00Ol_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO111l; + wire_nlliO011l_dataout <= wire_nlOiO00OO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO111O; + wire_nlliO011O_dataout <= wire_nlOiO0i1i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO110i; + wire_nlliO01ii_dataout <= wire_nlOiO0i0l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11il; + wire_nlliO01il_dataout <= wire_nlOiO0i0O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11iO; + wire_nlliO01iO_dataout <= wire_nlOiO0iii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11li; + wire_nlliO01li_dataout <= wire_nlOiO0iil_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11ll; + wire_nlliO01ll_dataout <= wire_nlOiO0iiO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11lO; + wire_nlliO01lO_dataout <= wire_nlOiO0ili_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11Oi; + wire_nlliO01O_dataout <= wire_nlliOO1O_dataout AND NOT(niOO01lOO); + wire_nlliO01Oi_dataout <= wire_nlOiO0ill_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11Ol; + wire_nlliO01Ol_dataout <= wire_nlOiO0ilO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO11OO; + wire_nlliO01OO_dataout <= wire_nlOiO0iOi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO101i; + wire_nlliO0ii_dataout <= wire_nlliOO0i_dataout AND NOT(niOO01lOO); + wire_nlliO0il_dataout <= wire_nlll11Oi_dataout AND NOT(niOO01lOO); + wire_nlliO0iO_dataout <= wire_nlll11li_dataout AND NOT(niOO01lOO); + wire_nlliO0li_dataout <= wire_nlll11ll_dataout AND NOT(niOO01lOO); + wire_nlliO0ll_dataout <= wire_nlll11lO_dataout AND NOT(niOO01lOO); + wire_nlliO0lO_dataout <= wire_nlliOO0l_dataout AND NOT(niOO01lOO); + wire_nlliO0Oi_dataout <= wire_nlliOO0O_dataout AND NOT(niOO01lOO); + wire_nlliO0Ol_dataout <= wire_nlliOOii_dataout AND NOT(niOO01lOO); + wire_nlliO0OO_dataout <= wire_nlliOOil_dataout AND NOT(niOO01lOO); + wire_nlliO100i_dataout <= wire_nlliO1lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO100l_dataout <= wire_nlliO1llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO100O_dataout <= wire_nlliO1lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO101l_dataout <= wire_nlliO1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO101O_dataout <= wire_nlliO1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10ii_dataout <= wire_nlliO1lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10il_dataout <= wire_nlliO1lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10iO_dataout <= wire_nlliO1O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10li_dataout <= wire_nlliO1O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10ll_dataout <= wire_nlliO1O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10lO_dataout <= wire_nlliO1O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10Oi_dataout <= wire_nlliO1O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10Ol_dataout <= wire_nlliO1O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO10OO_dataout <= wire_nlliO1Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1i0i_dataout <= wire_nlliO1Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1i0l_dataout <= wire_nlliO1OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1i0O_dataout <= wire_nlliO1OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1i1i_dataout <= wire_nlliO1Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1i1l_dataout <= wire_nlliO1OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1i1O_dataout <= wire_nlliO1Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1iii_dataout <= wire_nlliO1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1iil_dataout <= wire_nlliO1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1iiO_dataout <= wire_nlliO011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1ili_dataout <= wire_nlliO011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1ill_dataout <= wire_nlliO011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1ilO_dataout <= wire_nlliO010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1iOi_dataout <= wire_nlliO010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1iOl_dataout <= wire_nlliO010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1iOO_dataout <= wire_nlliO01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1l0i_dataout <= wire_nlliO01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1l0l_dataout <= wire_nlliO01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1l0O_dataout <= wire_nlliO01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1l1i_dataout <= wire_nlliO01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1l1l_dataout <= wire_nlliO01iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1l1O_dataout <= wire_nlliO01li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1lii_dataout <= wire_nlliO01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1lil_dataout <= wire_nlliO01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliO1liO_dataout <= niOiOil0l WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilil0O; + wire_nlliO1lli_dataout <= niOiOilii WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOlll; + wire_nlliO1lll_dataout <= niOiOilll WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOllO; + wire_nlliO1llO_dataout <= niOiOilOO WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOlOi; + wire_nlliO1lOi_dataout <= niOiOiO0i WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOlOl; + wire_nlliO1lOl_dataout <= wire_nlOiO01lO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOlOO; + wire_nlliO1lOO_dataout <= wire_nlOiO01Oi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOO1i; + wire_nlliO1O0i_dataout <= wire_nlOiO001l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOO0l; + wire_nlliO1O0l_dataout <= wire_nlOiO001O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOO0O; + wire_nlliO1O0O_dataout <= wire_nlOiO000i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOii; + wire_nlliO1O1i_dataout <= wire_nlOiO01Ol_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOO1l; + wire_nlliO1O1l_dataout <= wire_nlOiO01OO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOO1O; + wire_nlliO1O1O_dataout <= wire_nlOiO001i_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOO0i; + wire_nlliO1Oii_dataout <= wire_nlOiO000l_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOil; + wire_nlliO1Oil_dataout <= wire_nlOiO000O_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOiO; + wire_nlliO1OiO_dataout <= wire_nlOiO00ii_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOli; + wire_nlliO1Oli_dataout <= wire_nlOiO00il_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOll; + wire_nlliO1Oll_dataout <= wire_nlOiO00iO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOlO; + wire_nlliO1OlO_dataout <= wire_nlOiO00li_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOOi; + wire_nlliO1OOi_dataout <= wire_nlOiO00ll_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOOl; + wire_nlliO1OOl_dataout <= wire_nlOiO00lO_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nllilOOOO; + wire_nlliO1OOO_dataout <= wire_nlOiO00Oi_dataout WHEN wire_nlOiOi11i_dataout = '1' ELSE nlliO111i; + wire_nlliOi0i_dataout <= wire_nlliOOlO_dataout AND NOT(niOO01lOO); + wire_nlliOi0l_dataout <= wire_nlliOOOi_dataout AND NOT(niOO01lOO); + wire_nlliOi0O_dataout <= wire_nlliOOOl_dataout AND NOT(niOO01lOO); + wire_nlliOi1i_dataout <= wire_nlliOOiO_dataout AND NOT(niOO01lOO); + wire_nlliOi1l_dataout <= wire_nlliOOli_dataout AND NOT(niOO01lOO); + wire_nlliOi1O_dataout <= wire_nlliOOll_dataout AND NOT(niOO01lOO); + wire_nlliOiii_dataout <= wire_nlliOOOO_dataout AND NOT(niOO01lOO); + wire_nlliOiil_dataout <= wire_nlll111i_dataout AND NOT(niOO01lOO); + wire_nlliOiiO_dataout <= wire_nlliOliO_dataout AND NOT(niOO01lOO); + wire_nlliOili_dataout <= wire_nlll11iO_dataout AND NOT(niOO01lOO); + wire_nlliOill_dataout <= wire_nlliOlli_dataout AND NOT(niOO01lOO); + wire_nlliOilO_dataout <= wire_nlliOlll_dataout AND NOT(niOO01lOO); + wire_nlliOiOi_dataout <= wire_nlliOllO_dataout AND NOT(niOO01lOO); + wire_nlliOiOl_dataout <= wire_nlliOlOi_dataout AND NOT(niOO01lOO); + wire_nlliOiOO_dataout <= wire_nlliOlOl_dataout AND NOT(niOO01lOO); + wire_nlliOl0i_dataout <= wire_nlll110O_dataout AND NOT(niOO01lOO); + wire_nlliOl0l_dataout <= wire_nlll111l_dataout AND NOT(niOO01lOO); + wire_nlliOl0O_dataout <= wire_nlll111O_dataout AND NOT(niOO01lOO); + wire_nlliOl11O_dataout <= (nlilOO0iO AND (nlll00l1i OR wire_nl11llO_w_lg_nlll1ilil35500w(0))) AND NOT(wire_niO01O0O_dataout); + wire_nlliOl1i_dataout <= wire_nlliOlOO_dataout AND NOT(niOO01lOO); + wire_nlliOl1l_dataout <= wire_nlliOO1i_dataout AND NOT(niOO01lOO); + wire_nlliOl1O_dataout <= wire_nlliOO1l_dataout AND NOT(niOO01lOO); + wire_nlliOli0i_dataout <= wire_nlliOllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOli0l_dataout <= wire_nlliOlllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOli0O_dataout <= wire_nlliOllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOli1O_dataout <= (niOiOl1lO AND niOO1li0i) AND NOT(wire_niO01O0O_dataout); + wire_nlliOlii_dataout <= wire_nlll110i_dataout AND NOT(niOO01lOO); + wire_nlliOliii_dataout <= wire_nlliOllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOliil_dataout <= wire_nlliOllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOliiO_dataout <= wire_nlliOlO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOlil_dataout <= wire_nlll110l_dataout OR niOO01lOO; + wire_nlliOlili_dataout <= wire_nlliOlO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOlill_dataout <= wire_nlliOlO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOlilO_dataout <= wire_nlliOO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOliO_dataout <= wire_nlll100i_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO11O; + wire_nlliOliOi_dataout <= wire_nlliOO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOliOl_dataout <= wire_nlliOO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOliOO_dataout <= wire_nlliOO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOll0i_dataout <= wire_nlliOO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOll0l_dataout <= wire_nlliOO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOll0O_dataout <= wire_nlliOO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOll1i_dataout <= wire_nlliOO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOll1l_dataout <= wire_nlliOO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOll1O_dataout <= wire_nlliOO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOlli_dataout <= wire_nlll100l_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO10l; + wire_nlliOllii_dataout <= wire_nlliOO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOllil_dataout <= wire_nlliOO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOlliO_dataout <= wire_nlliOO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOlll_dataout <= wire_nlll100O_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO10O; + wire_nlliOllli_dataout <= wire_nlliOO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlliOllll_dataout <= wire_nlliOlO0i_dataout WHEN niOiOiOlO = '1' ELSE nlliOl1li; + wire_nlliOlllO_dataout <= wire_nlliOlO0l_dataout WHEN niOiOiOlO = '1' ELSE nlliOl1ll; + wire_nlliOllO_dataout <= wire_nlll10ii_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1ii; + wire_nlliOllOi_dataout <= wire_nlliOlO0O_dataout WHEN niOiOiOlO = '1' ELSE nlliOl1lO; + wire_nlliOllOl_dataout <= wire_nlliOlOii_dataout WHEN niOiOiOlO = '1' ELSE nlliOl1Oi; + wire_nlliOllOO_dataout <= wire_nlliOlOil_dataout WHEN niOiOiOlO = '1' ELSE nlliOl1Ol; + wire_nlliOlO0i_dataout <= wire_nlliOl1iO_o(1) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(0); + wire_nlliOlO0l_dataout <= wire_nlliOl1iO_o(2) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(1); + wire_nlliOlO0O_dataout <= wire_nlliOl1iO_o(3) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(2); + wire_nlliOlO1i_dataout <= wire_nlliOlOiO_dataout WHEN niOiOiOlO = '1' ELSE nlliOl1OO; + wire_nlliOlO1l_dataout <= wire_nlliOlOli_dataout WHEN niOiOiOlO = '1' ELSE nlliOl01i; + wire_nlliOlO1O_dataout <= wire_nlliOlOll_dataout WHEN niOiOiOlO = '1' ELSE nlliOl01l; + wire_nlliOlOi_dataout <= wire_nlll10il_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1il; + wire_nlliOlOii_dataout <= wire_nlliOl1iO_o(4) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(3); + wire_nlliOlOil_dataout <= wire_nlliOl1iO_o(5) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(4); + wire_nlliOlOiO_dataout <= wire_nlliOl1iO_o(6) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(5); + wire_nlliOlOl_dataout <= wire_nlll10iO_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1iO; + wire_nlliOlOli_dataout <= wire_nlliOl1iO_o(7) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(6); + wire_nlliOlOll_dataout <= wire_nlliOl1iO_o(8) WHEN wire_nlliOlOOl_o = '1' ELSE wire_nlliOlOlO_o(7); + wire_nlliOlOO_dataout <= wire_nlll10li_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1li; + wire_nlliOO00i_dataout <= wire_nlliO0lOi_q(4) WHEN niOiOiOOl = '1' ELSE nlll1lOll; + wire_nlliOO00l_dataout <= wire_nlliO0lOi_q(5) WHEN niOiOiOOl = '1' ELSE nlll1lOlO; + wire_nlliOO00O_dataout <= wire_nlliO0lOi_q(6) WHEN niOiOiOOl = '1' ELSE nlll1lOOi; + wire_nlliOO01i_dataout <= wire_nlliO0lOi_q(1) WHEN niOiOiOOl = '1' ELSE nlll1lOil; + wire_nlliOO01l_dataout <= wire_nlliO0lOi_q(2) WHEN niOiOiOOl = '1' ELSE nlll1lOiO; + wire_nlliOO01O_dataout <= wire_nlliO0lOi_q(3) WHEN niOiOiOOl = '1' ELSE nlll1lOli; + wire_nlliOO0i_dataout <= wire_nlll10Ol_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilO1i; + wire_nlliOO0ii_dataout <= wire_nlliO0lOi_q(7) WHEN niOiOiOOl = '1' ELSE nlll1lOOl; + wire_nlliOO0l_dataout <= wire_nlll1i1i_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilO0O; + wire_nlliOO0li_dataout <= wire_nlliOOi1O_dataout AND NOT(niOiOiOOO); + wire_nlliOO0ll_dataout <= wire_nlliOOi0i_dataout AND NOT(niOiOiOOO); + wire_nlliOO0lO_dataout <= wire_nlliOOi0l_dataout AND NOT(niOiOiOOO); + wire_nlliOO0O_dataout <= wire_nlll1i1l_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOii; + wire_nlliOO0Oi_dataout <= wire_nlliOOi0O_dataout AND NOT(niOiOiOOO); + wire_nlliOO0Ol_dataout <= wire_nlliOOiii_dataout AND NOT(niOiOiOOO); + wire_nlliOO0OO_dataout <= wire_nlliOOiil_dataout AND NOT(niOiOiOOO); + wire_nlliOO10i_dataout <= wire_nlliOO1il_o(3) AND NOT(niOiOiOOi); + wire_nlliOO10l_dataout <= wire_nlliOO1il_o(4) AND NOT(niOiOiOOi); + wire_nlliOO10O_dataout <= wire_nlliOO1il_o(5) AND NOT(niOiOiOOi); + wire_nlliOO11i_dataout <= wire_nlliOO1il_o(0) AND NOT(niOiOiOOi); + wire_nlliOO11l_dataout <= wire_nlliOO1il_o(1) AND NOT(niOiOiOOi); + wire_nlliOO11O_dataout <= wire_nlliOO1il_o(2) AND NOT(niOiOiOOi); + wire_nlliOO1i_dataout <= wire_nlll10ll_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1ll; + wire_nlliOO1ii_dataout <= wire_nlliOO1il_o(6) AND NOT(niOiOiOOi); + wire_nlliOO1iO_dataout <= wire_nlliOO01i_dataout WHEN wire_nl1000i_w_lg_nlll1OO0O966w(0) = '1' ELSE nlliOl0li; + wire_nlliOO1l_dataout <= wire_nlll10lO_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1lO; + wire_nlliOO1li_dataout <= wire_nlliOO01l_dataout WHEN wire_nl1000i_w_lg_nlll1OO0O966w(0) = '1' ELSE nlliOl0ll; + wire_nlliOO1ll_dataout <= wire_nlliOO01O_dataout WHEN wire_nl1000i_w_lg_nlll1OO0O966w(0) = '1' ELSE nlliOl0lO; + wire_nlliOO1lO_dataout <= wire_nlliOO00i_dataout WHEN wire_nl1000i_w_lg_nlll1OO0O966w(0) = '1' ELSE nlliOl0Oi; + wire_nlliOO1O_dataout <= wire_nlll10Oi_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nll0Ol0l; + wire_nlliOO1Oi_dataout <= wire_nlliOO00l_dataout WHEN wire_nl1000i_w_lg_nlll1OO0O966w(0) = '1' ELSE nlliOl0Ol; + wire_nlliOO1Ol_dataout <= wire_nlliOO00O_dataout WHEN wire_nl1000i_w_lg_nlll1OO0O966w(0) = '1' ELSE nlliOl0OO; + wire_nlliOO1OO_dataout <= wire_nlliOO0ii_dataout WHEN wire_nl1000i_w_lg_nlll1OO0O966w(0) = '1' ELSE nlliOli1i; + wire_nlliOOi0i_dataout <= nlliOOiOO WHEN niOiOl11i = '1' ELSE nlliOOlil; + wire_nlliOOi0l_dataout <= nlliOOl1i WHEN niOiOl11i = '1' ELSE nlliOOliO; + wire_nlliOOi0O_dataout <= nlliOOl1l WHEN niOiOl11i = '1' ELSE nlliOOlli; + wire_nlliOOi1i_dataout <= wire_nlliOOiiO_dataout AND NOT(niOiOiOOO); + wire_nlliOOi1l_dataout <= wire_nlliOOili_dataout AND NOT(niOiOiOOO); + wire_nlliOOi1O_dataout <= nlliOli1l WHEN niOiOl11i = '1' ELSE nlliOOlii; + wire_nlliOOii_dataout <= wire_nlll1i1O_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOil; + wire_nlliOOiii_dataout <= nlliOOl1O WHEN niOiOl11i = '1' ELSE nlliOOlll; + wire_nlliOOiil_dataout <= nlliOOl0i WHEN niOiOl11i = '1' ELSE nlliOOllO; + wire_nlliOOiiO_dataout <= nlliOOl0l WHEN niOiOl11i = '1' ELSE nlliOOlOi; + wire_nlliOOil_dataout <= wire_nlll1i0i_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOiO; + wire_nlliOOili_dataout <= nlliOOl0O WHEN niOiOl11i = '1' ELSE nlliOOlOl; + wire_nlliOOiO_dataout <= wire_nlll1i0l_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOli; + wire_nlliOOli_dataout <= wire_nlll1i0O_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOll; + wire_nlliOOll_dataout <= wire_nlll1iii_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOlO; + wire_nlliOOlO_dataout <= wire_nlll1iil_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOOi; + wire_nlliOOOi_dataout <= wire_nlll1iiO_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOOl; + wire_nlliOOOl_dataout <= wire_nlll1ili_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilOOO; + wire_nlliOOOO_dataout <= wire_nlll1ill_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO11i; + wire_nlll0000i_dataout <= wire_nlll0000l_dataout AND nlilOO0iO; + wire_nlll0000l_dataout <= wire_nlll0000O_dataout OR wire_nlOili11i_dataout; + wire_nlll0000O_dataout <= nlll0101l AND NOT((niOiOl0Oi AND niOiOl0il)); + wire_nlll0010i_dataout <= wire_nlll0010l_o(9) WHEN niOiOl00O = '1' ELSE nlll010Oi; + wire_nlll0011i_dataout <= wire_nlll0010l_o(6) WHEN niOiOl00O = '1' ELSE nlll010li; + wire_nlll0011l_dataout <= wire_nlll0010l_o(7) WHEN niOiOl00O = '1' ELSE nlll010ll; + wire_nlll0011O_dataout <= wire_nlll0010l_o(8) WHEN niOiOl00O = '1' ELSE nlll010lO; + wire_nlll001ll_dataout <= wire_nlll001lO_dataout OR ((((nlll1il1O AND wire_w_lg_niOl11OOl34628w(0)) AND wire_nlOl1l0Ol_dataout) AND nlll0101l) OR wire_nlOili11i_dataout); + wire_nlll001lO_dataout <= nlll0101O AND NOT((wire_nl1000i_w_lg_nlilOO0iO5228w(0) OR wire_w_lg_niOiOl0li34626w(0))); + wire_nlll00iO_dataout <= wire_nl1lOOO1O_w_lg_w_lg_w_lg_dataout5082w5084w5086w(0) WHEN nl1OilOii = '1' ELSE nll0Ol0l; + wire_nlll00l0i_dataout <= wire_nlll00OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00l0l_dataout <= wire_nlll00OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00l0O_dataout <= wire_nlll00OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00l1l_dataout <= wire_nlll00Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00l1O_dataout <= wire_nlll00OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00li_dataout <= (k_gbl_hip(32) AND wire_nl1lOOl0l_dataout) WHEN nl1OilOii = '1' ELSE nllilO1i; + wire_nlll00lii_dataout <= wire_nlll0i11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00lil_dataout <= wire_nlll0i11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00liO_dataout <= wire_nlll0i11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00ll_dataout <= wire_nl1lOOi0l_dataout WHEN nl1OilOii = '1' ELSE nllilO0O; + wire_nlll00lli_dataout <= wire_nlll0i10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00lll_dataout <= wire_nlll0i10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00llO_dataout <= wire_nlll0i10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00lO_dataout <= wire_nl1lOOi0O_dataout WHEN nl1OilOii = '1' ELSE nllilOii; + wire_nlll00lOi_dataout <= wire_nlll0i1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00lOl_dataout <= wire_nlll0i00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00lOO_dataout <= wire_nlll0i00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00O0i_dataout <= wire_nlll0i0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00O0l_dataout <= wire_nlll0i0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00O0O_dataout <= wire_nlll0i0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00O1i_dataout <= wire_nlll0i0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00O1l_dataout <= wire_nlll0i0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00O1O_dataout <= wire_nlll0i0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00Oi_dataout <= wire_nl1lOOiii_dataout WHEN nl1OilOii = '1' ELSE nllilOil; + wire_nlll00Oii_dataout <= wire_nlll0i0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00Oil_dataout <= wire_nlll0i0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00OiO_dataout <= wire_nlll0i0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00Ol_dataout <= wire_nl1lOOiil_dataout WHEN nl1OilOii = '1' ELSE nllilOiO; + wire_nlll00Oli_dataout <= wire_nlll0ii1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll00Oll_dataout <= wire_nlll0i1il_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll00OlO_dataout <= wire_nlll0i1iO_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll00OO_dataout <= wire_nl1lOOiiO_dataout WHEN nl1OilOii = '1' ELSE nllilOli; + wire_nlll00OOi_dataout <= wire_nlll0i1li_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll00OOl_dataout <= wire_nlll0i1ll_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll00OOO_dataout <= wire_nlll0i1lO_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0110i_dataout <= nlll1OO0O AND NOT(niOiOl01i); + wire_nlll0110l_dataout <= nlll1OOii OR niOiOl01i; + wire_nlll0111i_dataout <= nlll1OO0O AND NOT(nlll1ilil); + wire_nlll0111l_dataout <= nlll1OOii OR nlll1ilil; + wire_nlll0111O_dataout <= nlll1lOOO AND NOT(niOiOl01i); + wire_nlll011ii_dataout <= wire_nlll011li_dataout OR niOiOl01O; + wire_nlll011il_dataout <= wire_nlll011ll_dataout AND NOT(niOiOl01O); + wire_nlll011iO_dataout <= wire_nlll011lO_dataout AND NOT(niOiOl01O); + wire_nlll011li_dataout <= nlll1lOOO AND NOT(niOiOl01l); + wire_nlll011ll_dataout <= nlll1OO0O OR niOiOl01l; + wire_nlll011lO_dataout <= nlll1OOii AND NOT(niOiOl01l); + wire_nlll01i0i_dataout <= wire_nlll01lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01i0l_dataout <= wire_nlll0000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01i0O_dataout <= wire_nlll001ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01i1l_dataout <= wire_nlll01l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01i1O_dataout <= niOiOl00i AND NOT(wire_niO01O0O_dataout); + wire_nlll01iii_dataout <= wire_nlll01lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01iil_dataout <= wire_nlll01O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01iiO_dataout <= wire_nlll01O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01ili_dataout <= wire_nlll01O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01ill_dataout <= wire_nlll01O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01ilO_dataout <= wire_nlll01O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01iOi_dataout <= wire_nlll01O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01iOl_dataout <= wire_nlll01Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01iOO_dataout <= wire_nlll01Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01l0i_dataout <= wire_nlll01l0l_dataout OR niOiOl00i; + wire_nlll01l0l_dataout <= nlll1OOil AND NOT(wire_nlOii0OOO_dataout); + wire_nlll01l1i_dataout <= wire_nlll01OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01l1l_dataout <= wire_nlll01lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01l1O_dataout <= wire_nlll01lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll01lii_dataout <= wire_nlll01liO_dataout AND NOT(niOiOl00l); + wire_nlll01lil_dataout <= wire_nlll01lli_dataout AND NOT(niOiOl00l); + wire_nlll01liO_dataout <= wire_nlll01lll_o(0) WHEN nlll1ilii = '1' ELSE nlll010Ol; + wire_nlll01ll_dataout <= k_hip(0) AND NOT(niOO01liO); + wire_nlll01lli_dataout <= wire_nlll01lll_o(1) WHEN nlll1ilii = '1' ELSE nlll010OO; + wire_nlll01lO_dataout <= wire_w_lg_w_k_hip_range2413w2429w(0) AND NOT(niOO01liO); + wire_nlll01lOi_dataout <= (niOiOl0ll AND wire_nlOii0OOO_w_lg_dataout34636w(0)) AND NOT(niOiOl0Ol); + wire_nlll01lOO_dataout <= wire_nlll01Oli_dataout AND NOT(niOiOl0ii); + wire_nlll01O0i_dataout <= wire_nlll01OOl_dataout AND NOT(niOiOl0ii); + wire_nlll01O0l_dataout <= wire_nlll01OOO_dataout AND NOT(niOiOl0ii); + wire_nlll01O0O_dataout <= wire_nlll0011i_dataout AND NOT(niOiOl0ii); + wire_nlll01O1i_dataout <= wire_nlll01Oll_dataout AND NOT(niOiOl0ii); + wire_nlll01O1l_dataout <= wire_nlll01OlO_dataout AND NOT(niOiOl0ii); + wire_nlll01O1O_dataout <= wire_nlll01OOi_dataout AND NOT(niOiOl0ii); + wire_nlll01Oi_dataout <= nllillOi WHEN niOO01liO = '1' ELSE nli1i1ll; + wire_nlll01Oii_dataout <= wire_nlll0011l_dataout AND NOT(niOiOl0ii); + wire_nlll01Oil_dataout <= wire_nlll0011O_dataout AND NOT(niOiOl0ii); + wire_nlll01OiO_dataout <= wire_nlll0010i_dataout AND NOT(niOiOl0ii); + wire_nlll01Oli_dataout <= wire_nlll0010l_o(0) WHEN niOiOl00O = '1' ELSE nlll0100i; + wire_nlll01Oll_dataout <= wire_nlll0010l_o(1) WHEN niOiOl00O = '1' ELSE nlll0100l; + wire_nlll01OlO_dataout <= wire_nlll0010l_o(2) WHEN niOiOl00O = '1' ELSE nlll0100O; + wire_nlll01OOi_dataout <= wire_nlll0010l_o(3) WHEN niOiOl00O = '1' ELSE nlll010ii; + wire_nlll01OOl_dataout <= wire_nlll0010l_o(4) WHEN niOiOl00O = '1' ELSE nlll010il; + wire_nlll01OOO_dataout <= wire_nlll0010l_o(5) WHEN niOiOl00O = '1' ELSE nlll010iO; + wire_nlll0i00i_dataout <= nlll0iOlO WHEN niOiOl0Oi = '1' ELSE nlll00i1O; + wire_nlll0i00l_dataout <= wire_nlll0ii1l_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i00O_dataout <= wire_nlll0ii1O_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i01i_dataout <= nlll0iOiO WHEN niOiOl0Oi = '1' ELSE nlll000OO; + wire_nlll0i01l_dataout <= nlll0iOli WHEN niOiOl0Oi = '1' ELSE nlll00i1i; + wire_nlll0i01O_dataout <= nlll0iOll WHEN niOiOl0Oi = '1' ELSE nlll00i1l; + wire_nlll0i0i_dataout <= wire_nl1lOOiOi_dataout WHEN nl1OilOii = '1' ELSE nllilOOl; + wire_nlll0i0ii_dataout <= wire_nlll0ii0i_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0il_dataout <= wire_nlll0ii0l_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0iO_dataout <= wire_nlll0ii0O_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0l_dataout <= wire_nl1lOOiOl_dataout WHEN nl1OilOii = '1' ELSE nllilOOO; + wire_nlll0i0li_dataout <= wire_nlll0iiii_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0ll_dataout <= wire_nlll0iiil_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0lO_dataout <= wire_nlll0iiiO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0O_dataout <= wire_nl1lOOO0l_dataout WHEN nl1OilOii = '1' ELSE nlliO11i; + wire_nlll0i0Oi_dataout <= wire_nlll0iili_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0Ol_dataout <= wire_nlll0iill_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i0OO_dataout <= wire_nlll0iilO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0i10i_dataout <= wire_nlll0i01i_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0i10l_dataout <= wire_nlll0i01l_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0i10O_dataout <= wire_nlll0i01O_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0i11i_dataout <= wire_nlll0i1Oi_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0i11l_dataout <= wire_nlll0i1Ol_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0i11O_dataout <= wire_nlll0i1OO_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0i1i_dataout <= wire_nl1lOOili_dataout WHEN nl1OilOii = '1' ELSE nllilOll; + wire_nlll0i1ii_dataout <= wire_nlll0i00i_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll0i1il_dataout <= nlll0iO1i WHEN niOiOl0Oi = '1' ELSE nlll01i1i; + wire_nlll0i1iO_dataout <= nlll0iO1l WHEN niOiOl0Oi = '1' ELSE nlll000il; + wire_nlll0i1l_dataout <= wire_nl1lOOill_dataout WHEN nl1OilOii = '1' ELSE nllilOlO; + wire_nlll0i1li_dataout <= nlll0iO1O WHEN niOiOl0Oi = '1' ELSE nlll000iO; + wire_nlll0i1ll_dataout <= nlll0iO0i WHEN niOiOl0Oi = '1' ELSE nlll000li; + wire_nlll0i1lO_dataout <= nlll0iO0l WHEN niOiOl0Oi = '1' ELSE nlll000ll; + wire_nlll0i1O_dataout <= wire_nl1lOOilO_dataout WHEN nl1OilOii = '1' ELSE nllilOOi; + wire_nlll0i1Oi_dataout <= nlll0iO0O WHEN niOiOl0Oi = '1' ELSE nlll000lO; + wire_nlll0i1Ol_dataout <= nlll0iOii WHEN niOiOl0Oi = '1' ELSE nlll000Oi; + wire_nlll0i1OO_dataout <= nlll0iOil WHEN niOiOl0Oi = '1' ELSE nlll000Ol; + wire_nlll0ii0i_dataout <= wire_nlll0iiOl_o(2) WHEN niOiOl0iO = '1' ELSE nlll00i0O; + wire_nlll0ii0l_dataout <= wire_nlll0iiOl_o(3) WHEN niOiOl0iO = '1' ELSE nlll00iii; + wire_nlll0ii0O_dataout <= wire_nlll0iiOl_o(4) WHEN niOiOl0iO = '1' ELSE nlll00iil; + wire_nlll0ii1i_dataout <= wire_nlll0iiOi_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll0ii1l_dataout <= wire_nlll0iiOl_o(0) WHEN niOiOl0iO = '1' ELSE nlll00i0i; + wire_nlll0ii1O_dataout <= wire_nlll0iiOl_o(1) WHEN niOiOl0iO = '1' ELSE nlll00i0l; + wire_nlll0iii_dataout <= wire_nl1lOOO0i_w_lg_dataout5075w(0) WHEN nl1OilOii = '1' ELSE nlliO11l; + wire_nlll0iiii_dataout <= wire_nlll0iiOl_o(5) WHEN niOiOl0iO = '1' ELSE nlll00iiO; + wire_nlll0iiil_dataout <= wire_nlll0iiOl_o(6) WHEN niOiOl0iO = '1' ELSE nlll00ili; + wire_nlll0iiiO_dataout <= wire_nlll0iiOl_o(7) WHEN niOiOl0iO = '1' ELSE nlll00ill; + wire_nlll0iil_dataout <= nlliO1Ol AND NOT(nl1OilOii); + wire_nlll0iili_dataout <= wire_nlll0iiOl_o(8) WHEN niOiOl0iO = '1' ELSE nlll00ilO; + wire_nlll0iill_dataout <= wire_nlll0iiOl_o(9) WHEN niOiOl0iO = '1' ELSE nlll00iOi; + wire_nlll0iilO_dataout <= wire_nlll0iiOl_o(10) WHEN niOiOl0iO = '1' ELSE nlll00iOl; + wire_nlll0iiO_dataout <= nlliO1OO AND NOT(nl1OilOii); + wire_nlll0iiOi_dataout <= wire_nlll0iiOl_o(11) WHEN niOiOl0iO = '1' ELSE nlll00iOO; + wire_nlll0il0i_dataout <= wire_nlll0il0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0il0l_dataout <= wire_nlll0il0O_dataout AND NOT((wire_nl1000i_w_lg_nlilOO0iO5228w(0) OR niOiOl0li)); + wire_nlll0il0O_dataout <= (nlll0iOOi AND wire_nl1000i_w_lg_nlll0il1O34569w(0)) WHEN niOiOl0Ol = '1' ELSE wire_nlll0ilii_dataout; + wire_nlll0ili_dataout <= nlliO01i OR nl1OilOii; + wire_nlll0ilii_dataout <= nlll00l1i OR (niOiOl0ll OR (niOOi1i0l AND nlll0101O)); + wire_nlll0ill_dataout <= nlliO01l AND NOT(nl1OilOii); + wire_nlll0ilO_dataout <= nlliO1Oi OR nl1OilOii; + wire_nlll0iOi_dataout <= nllillOi AND nllillOl; + wire_nlll0iOl_dataout <= wire_nlll0iOO_dataout AND NOT(nllillOl); + wire_nlll0iOO_dataout <= nllillOi WHEN nli1i1ll = '1' ELSE nllillOl; + wire_nlll0l00l_dataout <= niOiOl0OO WHEN nlliiilll = '1' ELSE nlll0il1O; + wire_nlll0l00O_dataout <= wire_nlll0liii_dataout WHEN nlliiilll = '1' ELSE nlll0iO1i; + wire_nlll0l01i_dataout <= wire_nlll0li1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l01l_dataout <= wire_nlll0li0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l01O_dataout <= wire_nlll0li0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l0i_dataout <= k_hip(4) OR niOO01O1i; + wire_nlll0l0ii_dataout <= wire_nlll0liil_dataout WHEN nlliiilll = '1' ELSE nlll0iO1l; + wire_nlll0l0il_dataout <= wire_nlll0liiO_dataout WHEN nlliiilll = '1' ELSE nlll0iO1O; + wire_nlll0l0iO_dataout <= wire_nlll0lili_dataout WHEN nlliiilll = '1' ELSE nlll0iO0i; + wire_nlll0l0l_dataout <= k_hip(5) AND NOT(niOO01O1i); + wire_nlll0l0li_dataout <= wire_nlll0lill_dataout WHEN nlliiilll = '1' ELSE nlll0iO0l; + wire_nlll0l0ll_dataout <= wire_nlll0lilO_dataout WHEN nlliiilll = '1' ELSE nlll0iO0O; + wire_nlll0l0lO_dataout <= wire_nlll0liOi_dataout WHEN nlliiilll = '1' ELSE nlll0iOii; + wire_nlll0l0O_dataout <= k_hip(6) AND NOT(niOO01O1i); + wire_nlll0l0Oi_dataout <= wire_nlll0liOl_dataout WHEN nlliiilll = '1' ELSE nlll0iOil; + wire_nlll0l0Ol_dataout <= wire_nlll0liOO_dataout WHEN nlliiilll = '1' ELSE nlll0iOiO; + wire_nlll0l0OO_dataout <= wire_nlll0ll1i_dataout WHEN nlliiilll = '1' ELSE nlll0iOli; + wire_nlll0l10i_dataout <= wire_nlll0l00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l10l_dataout <= wire_nlll0l0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l10O_dataout <= wire_nlll0l0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l11i_dataout <= wire_nlll0l00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l11l_dataout <= (nlliiilll AND niOiOli0i) AND NOT(wire_niO01O0O_dataout); + wire_nlll0l11O_dataout <= nlliiilll AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1i_dataout <= niOO01lOi AND NOT(nlliO01l); + wire_nlll0l1ii_dataout <= wire_nlll0l0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1il_dataout <= wire_nlll0l0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1iO_dataout <= wire_nlll0l0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1li_dataout <= wire_nlll0l0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1ll_dataout <= wire_nlll0l0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1lO_dataout <= wire_nlll0l0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1Oi_dataout <= wire_nlll0l0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1Ol_dataout <= wire_nlll0li1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0l1OO_dataout <= wire_nlll0li1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll0li0i_dataout <= wire_w_lg_niOiOli1i34556w(0) WHEN nlliiilll = '1' ELSE nlll0iOOl; + wire_nlll0li0l_dataout <= niOiOli0i WHEN nlliiilll = '1' ELSE nlll0iOOO; + wire_nlll0li1i_dataout <= wire_nlll0ll1l_dataout WHEN nlliiilll = '1' ELSE nlll0iOll; + wire_nlll0li1l_dataout <= wire_nlll0ll1O_dataout WHEN nlliiilll = '1' ELSE nlll0iOlO; + wire_nlll0li1O_dataout <= (nlliiil0l OR (wire_nl1000i_w_lg_nlliiil0l34446w(0) AND (NOT (wire_nl1000i_w_lg_niOOi1iii34557w(0) AND wire_nl1000i_w_lg_niOOi1i0O34491w(0))))) WHEN nlliiilll = '1' ELSE nlll0iOOi; + wire_nlll0lii_dataout <= k_hip(7) OR niOO01O1i; + wire_nlll0liii_dataout <= wire_nlll0lO1O_o(1) WHEN niOiOli1O = '1' ELSE wire_nlll0ll0i_dataout; + wire_nlll0liii_w_lg_dataout34277w(0) <= NOT wire_nlll0liii_dataout; + wire_nlll0liil_dataout <= wire_nlll0lO1O_o(2) WHEN niOiOli1O = '1' ELSE wire_nlll0ll0l_dataout; + wire_nlll0liil_w_lg_dataout34279w(0) <= NOT wire_nlll0liil_dataout; + wire_nlll0liiO_dataout <= wire_nlll0lO1O_o(3) WHEN niOiOli1O = '1' ELSE wire_nlll0ll0O_dataout; + wire_nlll0liiO_w_lg_dataout34281w(0) <= NOT wire_nlll0liiO_dataout; + wire_nlll0lili_dataout <= wire_nlll0lO1O_o(4) WHEN niOiOli1O = '1' ELSE wire_nlll0llii_dataout; + wire_nlll0lili_w_lg_dataout34283w(0) <= NOT wire_nlll0lili_dataout; + wire_nlll0lill_dataout <= wire_nlll0lO1O_o(5) WHEN niOiOli1O = '1' ELSE wire_nlll0llil_dataout; + wire_nlll0lill_w_lg_dataout34285w(0) <= NOT wire_nlll0lill_dataout; + wire_nlll0lilO_dataout <= wire_nlll0lO1O_o(6) WHEN niOiOli1O = '1' ELSE wire_nlll0lliO_dataout; + wire_nlll0lilO_w_lg_dataout34287w(0) <= NOT wire_nlll0lilO_dataout; + wire_nlll0liO_dataout <= wire_nl1lO010O_dataout WHEN wire_nl1lOOO0i_w_lg_dataout5075w(0) = '1' ELSE wire_nl1lO1l0i_dataout; + wire_nlll0liO_w_lg_w_lg_dataout5087w5088w(0) <= wire_nlll0liO_w_lg_dataout5087w(0) AND nlliO11l; + wire_nlll0liO_w_lg_dataout5744w(0) <= wire_nlll0liO_dataout AND wire_nl1000i_w_lg_w_lg_nllilO1i5110w5743w(0); + wire_nlll0liO_w_lg_dataout5750w(0) <= wire_nlll0liO_dataout AND wire_nl1000i_w_lg_nllilO1i5749w(0); + wire_nlll0liO_w_lg_dataout5087w(0) <= NOT wire_nlll0liO_dataout; + wire_nlll0liOi_dataout <= wire_nlll0lO1O_o(7) WHEN niOiOli1O = '1' ELSE wire_nlll0llli_dataout; + wire_nlll0liOi_w_lg_dataout34289w(0) <= NOT wire_nlll0liOi_dataout; + wire_nlll0liOl_dataout <= wire_nlll0lO1O_o(8) WHEN niOiOli1O = '1' ELSE wire_nlll0llll_dataout; + wire_nlll0liOl_w_lg_dataout34291w(0) <= NOT wire_nlll0liOl_dataout; + wire_nlll0liOO_dataout <= wire_nlll0lO1O_o(9) WHEN niOiOli1O = '1' ELSE wire_nlll0lllO_dataout; + wire_nlll0liOO_w_lg_dataout34293w(0) <= NOT wire_nlll0liOO_dataout; + wire_nlll0ll0i_dataout <= wire_nlll0lO1i_o(0) WHEN niOiOli1l = '1' ELSE nllii0OlO; + wire_nlll0ll0l_dataout <= wire_nlll0lO1i_o(1) WHEN niOiOli1l = '1' ELSE nlliii0Oi; + wire_nlll0ll0O_dataout <= wire_nlll0lO1i_o(2) WHEN niOiOli1l = '1' ELSE nlliii0Ol; + wire_nlll0ll1i_dataout <= wire_nlll0lO1O_o(10) WHEN niOiOli1O = '1' ELSE wire_nlll0llOi_dataout; + wire_nlll0ll1i_w_lg_dataout34295w(0) <= NOT wire_nlll0ll1i_dataout; + wire_nlll0ll1l_dataout <= wire_nlll0lO1O_o(11) WHEN niOiOli1O = '1' ELSE wire_nlll0llOl_dataout; + wire_nlll0ll1l_w_lg_dataout34297w(0) <= NOT wire_nlll0ll1l_dataout; + wire_nlll0ll1O_dataout <= wire_nlll0lO1O_o(12) WHEN niOiOli1O = '1' ELSE wire_nlll0llOO_dataout; + wire_nlll0ll1O_w_lg_dataout34299w(0) <= NOT wire_nlll0ll1O_dataout; + wire_nlll0llii_dataout <= wire_nlll0lO1i_o(3) WHEN niOiOli1l = '1' ELSE nlliii0OO; + wire_nlll0llil_dataout <= wire_nlll0lO1i_o(4) WHEN niOiOli1l = '1' ELSE nlliiii1i; + wire_nlll0lliO_dataout <= wire_nlll0lO1i_o(5) WHEN niOiOli1l = '1' ELSE nlliiii1l; + wire_nlll0llli_dataout <= wire_nlll0lO1i_o(6) WHEN niOiOli1l = '1' ELSE nlliiii1O; + wire_nlll0llll_dataout <= wire_nlll0lO1i_o(7) WHEN niOiOli1l = '1' ELSE nlliiii0i; + wire_nlll0lllO_dataout <= wire_nlll0lO1i_o(8) WHEN niOiOli1l = '1' ELSE nlliiii0l; + wire_nlll0llOi_dataout <= wire_nlll0lO1i_o(9) WHEN niOiOli1l = '1' ELSE nlliiii0O; + wire_nlll0llOl_dataout <= wire_nlll0lO1i_o(10) WHEN niOiOli1l = '1' ELSE nlliiiiii; + wire_nlll0llOO_dataout <= wire_nlll0lO1i_o(11) WHEN niOiOli1l = '1' ELSE nlliiiiil; + wire_nlll0lOll_dataout <= wire_nlll0lOOi_dataout AND NOT(nlll1OOii); + wire_nlll0lOlO_dataout <= wire_nl1000i_w_lg_nlll1OO0O966w(0) AND NOT(nlll1OOii); + wire_nlll0lOOi_dataout <= wire_nl1000i_w_lg_nlll1lOOO34167w(0) OR nlll1OO0O; + wire_nlll0lOOl_dataout <= wire_nlll0O11l_dataout AND NOT(nlll1ilil); + wire_nlll0lOOO_dataout <= wire_nlll0O11O_dataout AND NOT(nlll1ilil); + wire_nlll0O10i_dataout <= wire_nlll0O1ii_dataout AND NOT(nlll1ilii); + wire_nlll0O10l_dataout <= wire_nlll0O1il_dataout AND NOT(nlll1il0O); + wire_nlll0O10O_dataout <= wire_nlll0O1iO_dataout OR nlll1il0O; + wire_nlll0O11i_dataout <= wire_nlll0O10i_dataout AND NOT(nlll1ilil); + wire_nlll0O11l_dataout <= wire_nlll0O10l_dataout OR nlll1ilii; + wire_nlll0O11O_dataout <= wire_nlll0O10O_dataout AND NOT(nlll1ilii); + wire_nlll0O1ii_dataout <= wire_nl1000i_w_lg_nlll1il0l34166w(0) AND NOT(nlll1il0O); + wire_nlll0O1il_dataout <= wire_nlll0O1li_dataout OR nlll1il0l; + wire_nlll0O1iO_dataout <= wire_nlll0O1ll_dataout OR nlll1il0l; + wire_nlll0O1li_dataout <= wire_nlll0O1lO_dataout AND NOT(nlll1il0i); + wire_nlll0O1ll_dataout <= wire_nl1000i_w_lg_nlll1il1O34165w(0) AND NOT(nlll1il0i); + wire_nlll0O1lO_dataout <= wire_nl1000i_w_lg_nlll1il1l34164w(0) OR nlll1il1O; + wire_nlll1000i_dataout <= wire_nlll1i11l_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10i0l_dataout; + wire_nlll1000l_dataout <= wire_nlll1i11O_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10i0O_dataout; + wire_nlll1000O_dataout <= wire_nlll1i10i_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10iii_dataout; + wire_nlll1001i_dataout <= wire_nlll10OOl_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10i1l_dataout; + wire_nlll1001l_dataout <= wire_nlll10OOO_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10i1O_dataout; + wire_nlll1001O_dataout <= wire_nlll1i11i_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10i0i_dataout; + wire_nlll100i_dataout <= wire_nlll0liO_dataout WHEN nlliO01i = '1' ELSE nlliO11O; + wire_nlll100ii_dataout <= wire_nlll1i10l_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10iil_dataout; + wire_nlll100il_dataout <= wire_nlll1i10O_dataout WHEN nlll1il0O = '1' ELSE wire_nlll10iiO_dataout; + wire_nlll100iO_dataout <= wire_nlliO0lOi_q(0) WHEN nlll1il0O = '1' ELSE wire_nlll10ili_dataout; + wire_nlll100l_dataout <= niOO01l0i WHEN nlliO01i = '1' ELSE nlliO10l; + wire_nlll100li_dataout <= wire_nlliO0lOi_q(1) WHEN nlll1il0O = '1' ELSE wire_nlll10ill_dataout; + wire_nlll100ll_dataout <= wire_nlliO0lOi_q(2) WHEN nlll1il0O = '1' ELSE wire_nlll10ilO_dataout; + wire_nlll100lO_dataout <= wire_nlliO0lOi_q(3) WHEN nlll1il0O = '1' ELSE wire_nlll10iOi_dataout; + wire_nlll100O_dataout <= wire_nl1lO11li_dataout WHEN nlliO01i = '1' ELSE nlliO10O; + wire_nlll100Oi_dataout <= wire_nlliO0lOi_q(4) WHEN nlll1il0O = '1' ELSE wire_nlll10iOl_dataout; + wire_nlll100Ol_dataout <= wire_nlliO0lOi_q(5) WHEN nlll1il0O = '1' ELSE wire_nlll10iOO_dataout; + wire_nlll100OO_dataout <= wire_nlliO0lOi_q(6) WHEN nlll1il0O = '1' ELSE wire_nlll10l1i_dataout; + wire_nlll1010i_dataout <= wire_nlll1i1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1010l_dataout <= wire_nlll1i1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1010O_dataout <= wire_nlll1i1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1011i_dataout <= wire_nlll100Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1011l_dataout <= wire_nlll100OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1011O_dataout <= wire_nlll10i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101ii_dataout <= wire_nlll1i1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101il_dataout <= wire_nlll1i1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101iO_dataout <= wire_nlll1i1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101li_dataout <= wire_nlll1i1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101ll_dataout <= wire_nlll1i1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101lO_dataout <= wire_nlll1i01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101Oi_dataout <= wire_nlll1i01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101Ol_dataout <= wire_nlll1i01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll101OO_dataout <= wire_nlll1i00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll10i0i_dataout <= wire_nlll10l0l_dataout WHEN niOiOl11i = '1' ELSE nlliOOl1i; + wire_nlll10i0l_dataout <= wire_nlll10l0O_dataout WHEN niOiOl11i = '1' ELSE nlliOOl1l; + wire_nlll10i0O_dataout <= wire_nlll10lii_dataout WHEN niOiOl11i = '1' ELSE nlliOOl1O; + wire_nlll10i1i_dataout <= wire_nlliO0lOi_q(7) WHEN nlll1il0O = '1' ELSE wire_nlll10l1l_dataout; + wire_nlll10i1l_dataout <= wire_nlll10l1O_dataout WHEN niOiOl11i = '1' ELSE nlliOli1l; + wire_nlll10i1O_dataout <= wire_nlll10l0i_dataout WHEN niOiOl11i = '1' ELSE nlliOOiOO; + wire_nlll10ii_dataout <= wire_nl1lO11ll_dataout WHEN nlliO01i = '1' ELSE nlliO1ii; + wire_nlll10iii_dataout <= wire_nlll10lil_dataout WHEN niOiOl11i = '1' ELSE nlliOOl0i; + wire_nlll10iil_dataout <= wire_nlll10liO_dataout WHEN niOiOl11i = '1' ELSE nlliOOl0l; + wire_nlll10iiO_dataout <= wire_nlll10lli_dataout WHEN niOiOl11i = '1' ELSE nlliOOl0O; + wire_nlll10il_dataout <= wire_nl1lO11lO_dataout WHEN nlliO01i = '1' ELSE nlliO1il; + wire_nlll10ili_dataout <= wire_nlll10lll_dataout WHEN niOiOl11i = '1' ELSE nlliOOlii; + wire_nlll10ill_dataout <= wire_nlll10llO_dataout WHEN niOiOl11i = '1' ELSE nlliOOlil; + wire_nlll10ilO_dataout <= wire_nlll10lOi_dataout WHEN niOiOl11i = '1' ELSE nlliOOliO; + wire_nlll10iO_dataout <= wire_nl1lO11Oi_dataout WHEN nlliO01i = '1' ELSE nlliO1iO; + wire_nlll10iOi_dataout <= wire_nlll10lOl_dataout WHEN niOiOl11i = '1' ELSE nlliOOlli; + wire_nlll10iOl_dataout <= wire_nlll10lOO_dataout WHEN niOiOl11i = '1' ELSE nlliOOlll; + wire_nlll10iOO_dataout <= wire_nlll10O1i_dataout WHEN niOiOl11i = '1' ELSE nlliOOllO; + wire_nlll10l0i_dataout <= wire_nlll10O0l_dataout AND NOT(niOiOl11l); + wire_nlll10l0l_dataout <= wire_nlll10O0O_dataout AND NOT(niOiOl11l); + wire_nlll10l0O_dataout <= wire_nlll10Oii_dataout AND NOT(niOiOl11l); + wire_nlll10l1i_dataout <= wire_nlll10O1l_dataout WHEN niOiOl11i = '1' ELSE nlliOOlOi; + wire_nlll10l1l_dataout <= wire_nlll10O1O_dataout WHEN niOiOl11i = '1' ELSE nlliOOlOl; + wire_nlll10l1O_dataout <= wire_nlll10O0i_dataout OR niOiOl11l; + wire_nlll10li_dataout <= wire_nl1lO11Ol_dataout WHEN nlliO01i = '1' ELSE nlliO1li; + wire_nlll10lii_dataout <= wire_nlll10Oil_dataout AND NOT(niOiOl11l); + wire_nlll10lil_dataout <= wire_nlll10OiO_dataout AND NOT(niOiOl11l); + wire_nlll10liO_dataout <= wire_nlll10Oli_dataout AND NOT(niOiOl11l); + wire_nlll10ll_dataout <= wire_nl1lO11OO_dataout WHEN nlliO01i = '1' ELSE nlliO1ll; + wire_nlll10lli_dataout <= wire_nlll10Oll_dataout AND NOT(niOiOl11l); + wire_nlll10lll_dataout <= wire_nlll10OOi_o(0) AND NOT(niOiOl11l); + wire_nlll10llO_dataout <= wire_nlll10OOi_o(1) AND NOT(niOiOl11l); + wire_nlll10lO_dataout <= wire_nl1lO101i_dataout WHEN nlliO01i = '1' ELSE nlliO1lO; + wire_nlll10lOi_dataout <= wire_nlll10OOi_o(2) AND NOT(niOiOl11l); + wire_nlll10lOl_dataout <= wire_nlll10OOi_o(3) AND NOT(niOiOl11l); + wire_nlll10lOO_dataout <= wire_nlll10OOi_o(4) AND NOT(niOiOl11l); + wire_nlll10O0i_dataout <= wire_nlll10OlO_o(0) AND NOT(niOiOl11O); + wire_nlll10O0l_dataout <= wire_nlll10OlO_o(1) AND NOT(niOiOl11O); + wire_nlll10O0O_dataout <= wire_nlll10OlO_o(2) AND NOT(niOiOl11O); + wire_nlll10O1i_dataout <= wire_nlll10OOi_o(5) AND NOT(niOiOl11l); + wire_nlll10O1l_dataout <= wire_nlll10OOi_o(6) AND NOT(niOiOl11l); + wire_nlll10O1O_dataout <= wire_nlll10OOi_o(7) AND NOT(niOiOl11l); + wire_nlll10Oi_dataout <= wire_nlll00iO_dataout WHEN nlliO01l = '1' ELSE nll0Ol0l; + wire_nlll10Oii_dataout <= wire_nlll10OlO_o(3) AND NOT(niOiOl11O); + wire_nlll10Oil_dataout <= wire_nlll10OlO_o(4) AND NOT(niOiOl11O); + wire_nlll10OiO_dataout <= wire_nlll10OlO_o(5) AND NOT(niOiOl11O); + wire_nlll10Ol_dataout <= wire_nlll00li_dataout WHEN nlliO01l = '1' ELSE nllilO1i; + wire_nlll10Oli_dataout <= wire_nlll10OlO_o(6) AND NOT(niOiOl11O); + wire_nlll10Oll_dataout <= wire_nlll10OlO_o(7) AND NOT(niOiOl11O); + wire_nlll10OO_dataout <= nl1OilOii AND nlliO01l; + wire_nlll10OOl_dataout <= wire_nlll1i1ii_o(0) AND NOT(niOiOl10i); + wire_nlll10OOO_dataout <= wire_nlll1i1ii_o(1) AND NOT(niOiOl10i); + wire_nlll110i_dataout <= wire_nlll1iOO_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO01i; + wire_nlll110l_dataout <= wire_nlll1l1i_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO01l; + wire_nlll110O_dataout <= wire_nlll1l1l_o AND wire_w_lg_niOO01lOl5214w(0); + wire_nlll111i_dataout <= wire_nlll1ilO_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO11l; + wire_nlll111l_dataout <= wire_nlll1iOi_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1Ol; + wire_nlll111O_dataout <= wire_nlll1iOl_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO1OO; + wire_nlll11ii_dataout <= wire_nlll1l0i_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllillOi; + wire_nlll11il_dataout <= wire_nlll1l0l_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllillOl; + wire_nlll11iO_dataout <= wire_nlll1l0O_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nlliO10i; + wire_nlll11li_dataout <= wire_nlll11OO_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilO1O; + wire_nlll11ll_dataout <= wire_nlll101l_o WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilO0i; + wire_nlll11lO_dataout <= wire_nlll10OO_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilO0l; + wire_nlll11O0i_dataout <= wire_nlll1001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11O0l_dataout <= wire_nlll1001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11O0O_dataout <= wire_nlll1000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11O1O_dataout <= wire_nlll1001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11Oi_dataout <= wire_nlll0l1i_dataout WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllilO1l; + wire_nlll11Oii_dataout <= wire_nlll1000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11Oil_dataout <= wire_nlll1000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11OiO_dataout <= wire_nlll100ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11Ol_dataout <= nl1Ol1l0i WHEN wire_w_lg_niOO01lOl5214w(0) = '1' ELSE nllillOO; + wire_nlll11Oli_dataout <= wire_nlll100il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11Oll_dataout <= wire_nlll100iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11OlO_dataout <= wire_nlll100li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11OOi_dataout <= wire_nlll100ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11OOl_dataout <= wire_nlll100lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll11OOO_dataout <= wire_nlll100Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1i00i_dataout <= wire_nlll1ii1i_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i00l_dataout <= wire_nlll1iiOO_o(0) WHEN niOiOl10l = '1' ELSE wire_nlll1ii1l_dataout; + wire_nlll1i00O_dataout <= wire_nlll1iiOO_o(1) WHEN niOiOl10l = '1' ELSE wire_nlll1ii1O_dataout; + wire_nlll1i01i_dataout <= wire_nlll1i0Oi_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i01l_dataout <= wire_nlll1i0Ol_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i01O_dataout <= wire_nlll1i0OO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i0i_dataout <= wire_nlll00Ol_dataout WHEN nlliO01l = '1' ELSE nllilOiO; + wire_nlll1i0ii_dataout <= wire_nlll1iiOO_o(2) WHEN niOiOl10l = '1' ELSE wire_nlll1ii0i_dataout; + wire_nlll1i0il_dataout <= wire_nlll1iiOO_o(3) WHEN niOiOl10l = '1' ELSE wire_nlll1ii0l_dataout; + wire_nlll1i0iO_dataout <= wire_nlll1iiOO_o(4) WHEN niOiOl10l = '1' ELSE wire_nlll1ii0O_dataout; + wire_nlll1i0l_dataout <= wire_nlll00OO_dataout WHEN nlliO01l = '1' ELSE nllilOli; + wire_nlll1i0li_dataout <= wire_nlll1iiOO_o(5) WHEN niOiOl10l = '1' ELSE wire_nlll1iiii_dataout; + wire_nlll1i0ll_dataout <= wire_nlll1iiOO_o(6) WHEN niOiOl10l = '1' ELSE wire_nlll1iiil_dataout; + wire_nlll1i0lO_dataout <= wire_nlll1iiOO_o(7) WHEN niOiOl10l = '1' ELSE wire_nlll1iiiO_dataout; + wire_nlll1i0O_dataout <= wire_nlll0i1i_dataout WHEN nlliO01l = '1' ELSE nllilOll; + wire_nlll1i0Oi_dataout <= wire_nlll1iiOO_o(8) WHEN niOiOl10l = '1' ELSE wire_nlll1iili_dataout; + wire_nlll1i0Ol_dataout <= wire_nlll1iiOO_o(9) WHEN niOiOl10l = '1' ELSE wire_nlll1iill_dataout; + wire_nlll1i0OO_dataout <= wire_nlll1iiOO_o(10) WHEN niOiOl10l = '1' ELSE wire_nlll1iilO_dataout; + wire_nlll1i10i_dataout <= wire_nlll1i1ii_o(5) AND NOT(niOiOl10i); + wire_nlll1i10l_dataout <= wire_nlll1i1ii_o(6) AND NOT(niOiOl10i); + wire_nlll1i10O_dataout <= wire_nlll1i1ii_o(7) AND NOT(niOiOl10i); + wire_nlll1i11i_dataout <= wire_nlll1i1ii_o(2) AND NOT(niOiOl10i); + wire_nlll1i11l_dataout <= wire_nlll1i1ii_o(3) AND NOT(niOiOl10i); + wire_nlll1i11O_dataout <= wire_nlll1i1ii_o(4) AND NOT(niOiOl10i); + wire_nlll1i1i_dataout <= wire_nlll00ll_dataout WHEN nlliO01l = '1' ELSE nllilO0O; + wire_nlll1i1il_dataout <= wire_nlll1i00l_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i1iO_dataout <= wire_nlll1i00O_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i1l_dataout <= wire_nlll00lO_dataout WHEN nlliO01l = '1' ELSE nllilOii; + wire_nlll1i1li_dataout <= wire_nlll1i0ii_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i1ll_dataout <= wire_nlll1i0il_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i1lO_dataout <= wire_nlll1i0iO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i1O_dataout <= wire_nlll00Oi_dataout WHEN nlliO01l = '1' ELSE nllilOil; + wire_nlll1i1Oi_dataout <= wire_nlll1i0li_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i1Ol_dataout <= wire_nlll1i0ll_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1i1OO_dataout <= wire_nlll1i0lO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1ii0i_dataout <= wire_nlll1iiOl_o(2) WHEN niOl1011i = '1' ELSE nlll11lii; + wire_nlll1ii0l_dataout <= wire_nlll1iiOl_o(3) WHEN niOl1011i = '1' ELSE nlll11lil; + wire_nlll1ii0O_dataout <= wire_nlll1iiOl_o(4) WHEN niOl1011i = '1' ELSE nlll11liO; + wire_nlll1ii1i_dataout <= wire_nlll1iiOO_o(11) WHEN niOiOl10l = '1' ELSE wire_nlll1iiOi_dataout; + wire_nlll1ii1l_dataout <= wire_nlll1iiOl_o(0) WHEN niOl1011i = '1' ELSE nlll11l0l; + wire_nlll1ii1O_dataout <= wire_nlll1iiOl_o(1) WHEN niOl1011i = '1' ELSE nlll11l0O; + wire_nlll1iii_dataout <= wire_nlll0i1l_dataout WHEN nlliO01l = '1' ELSE nllilOlO; + wire_nlll1iiii_dataout <= wire_nlll1iiOl_o(5) WHEN niOl1011i = '1' ELSE nlll11lli; + wire_nlll1iiil_dataout <= wire_nlll1iiOl_o(6) WHEN niOl1011i = '1' ELSE nlll11lll; + wire_nlll1iiiO_dataout <= wire_nlll1iiOl_o(7) WHEN niOl1011i = '1' ELSE nlll11llO; + wire_nlll1iil_dataout <= wire_nlll0i1O_dataout WHEN nlliO01l = '1' ELSE nllilOOi; + wire_nlll1iili_dataout <= wire_nlll1iiOl_o(8) WHEN niOl1011i = '1' ELSE nlll11lOi; + wire_nlll1iill_dataout <= wire_nlll1iiOl_o(9) WHEN niOl1011i = '1' ELSE nlll11lOl; + wire_nlll1iilO_dataout <= wire_nlll1iiOl_o(10) WHEN niOl1011i = '1' ELSE nlll11lOO; + wire_nlll1iiO_dataout <= wire_nlll0i0i_dataout WHEN nlliO01l = '1' ELSE nllilOOl; + wire_nlll1iiOi_dataout <= wire_nlll1iiOl_o(11) WHEN niOl1011i = '1' ELSE nlll11O1i; + wire_nlll1ili_dataout <= wire_nlll0i0l_dataout WHEN nlliO01l = '1' ELSE nllilOOO; + wire_nlll1ill_dataout <= wire_nlll0i0O_dataout WHEN nlliO01l = '1' ELSE nlliO11i; + wire_nlll1illi_dataout <= wire_nlll1iO1O_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1illl_dataout <= wire_nlll1iO0l_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1illO_dataout <= wire_nlll1iO0O_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1ilO_dataout <= wire_nlll0iii_dataout WHEN nlliO01l = '1' ELSE nlliO11l; + wire_nlll1ilOi_dataout <= wire_nlll1iOii_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1ilOl_dataout <= wire_nlll1iOiO_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1ilOO_dataout <= wire_nlll1iOli_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1iO1i_dataout <= wire_nlll1iOlO_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1iO1l_dataout <= wire_nlll1iOOl_o OR wire_niO01O0O_dataout; + wire_nlll1iOOO_dataout <= nlll11O1l WHEN wire_nl1000i_w_lg_nlilOO0iO5228w(0) = '1' ELSE wire_nlll1l1il_dataout; + wire_nlll1l00i_dataout <= wire_nlll1l0ll_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l00l_dataout <= wire_nlll1l0lO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l00O_dataout <= wire_nlll1l0Oi_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l01i_dataout <= nlll11O1l OR NOT(niOiOl1ii); + wire_nlll1l01O_dataout <= wire_nlll1l0li_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l0ii_dataout <= wire_nlll1l0Ol_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l0il_dataout <= wire_nlll1l0OO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l0iO_dataout <= wire_nlll1li1i_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll1l0li_dataout <= nlll1il1l AND NOT(niOiOl1iO); + wire_nlll1l0ll_dataout <= nlll1il1O OR niOiOl1iO; + wire_nlll1l0lO_dataout <= nlll1il0i AND NOT(niOiOl1iO); + wire_nlll1l0O_dataout <= nl1OilOii WHEN nlliO01l = '1' ELSE nlliO10i; + wire_nlll1l0Oi_dataout <= nlll1il0l AND NOT(niOiOl1iO); + wire_nlll1l0Ol_dataout <= nlll1il0O AND NOT(niOiOl1iO); + wire_nlll1l0OO_dataout <= nlll1ilii AND NOT(niOiOl1iO); + wire_nlll1l10i_dataout <= wire_nlll1l1lO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l10l_dataout <= wire_nlll1l1Oi_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l10O_dataout <= wire_nlll1l1Ol_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l11i_dataout <= wire_nlll1l1iO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l11l_dataout <= wire_nlll1l1li_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l11O_dataout <= wire_nlll1l1ll_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1l1ii_dataout <= wire_nlll1l1OO_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll1l1il_dataout <= wire_nlll1l01i_dataout WHEN niOiOl1il = '1' ELSE nlll11O1l; + wire_nlll1l1iO_dataout <= niOiOl1ii WHEN niOiOl1il = '1' ELSE nlll1il1l; + wire_nlll1l1li_dataout <= nlll1il1O AND NOT(niOiOl1il); + wire_nlll1l1ll_dataout <= wire_w_lg_niOiOl1ii34770w(0) WHEN niOiOl1il = '1' ELSE nlll1il0i; + wire_nlll1l1lO_dataout <= nlll1il0l AND NOT(niOiOl1il); + wire_nlll1l1Oi_dataout <= nlll1il0O AND NOT(niOiOl1il); + wire_nlll1l1Ol_dataout <= nlll1ilii AND NOT(niOiOl1il); + wire_nlll1l1OO_dataout <= nlll1ilil AND NOT(niOiOl1il); + wire_nlll1li0i_dataout <= wire_nlll1lill_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1li0l_dataout <= wire_nlll1lilO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1li0O_dataout <= wire_nlll1liOi_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1li1i_dataout <= nlll1ilil AND NOT(niOiOl1iO); + wire_nlll1li1O_dataout <= nlll11O1l OR NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1lii_dataout <= niOO01l0l AND wire_nl1000i_w_lg_nli1i1ll5104w(0); + wire_nlll1liii_dataout <= wire_nlll1liOl_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1liil_dataout <= wire_nlll1liOO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1liiO_dataout <= wire_nlll1ll1i_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1lil_dataout <= nlliO1Ol AND NOT(wire_nl1000i_w_lg_nli1i1ll5104w(0)); + wire_nlll1lili_dataout <= wire_nlll1ll1l_dataout OR wire_nl1000i_w_lg_nlilOO0iO5228w(0); + wire_nlll1lill_dataout <= nlll1il1l AND NOT(niOiOl1li); + wire_nlll1lilO_dataout <= nlll1il1O AND NOT(niOiOl1li); + wire_nlll1liO_dataout <= wire_w_lg_niOO01l0l5119w(0) WHEN wire_nl1000i_w_lg_nli1i1ll5104w(0) = '1' ELSE nlliO1OO; + wire_nlll1liOi_dataout <= nlll1il0i AND NOT(niOiOl1li); + wire_nlll1liOl_dataout <= nlll1il0l OR niOiOl1li; + wire_nlll1liOO_dataout <= nlll1il0O AND NOT(niOiOl1li); + wire_nlll1ll0l_dataout <= nlll1il1l AND NOT(niOiOl1ll); + wire_nlll1ll0O_dataout <= nlll1il1O AND NOT(niOiOl1ll); + wire_nlll1ll1i_dataout <= nlll1ilii AND NOT(niOiOl1li); + wire_nlll1ll1l_dataout <= nlll1ilil AND NOT(niOiOl1li); + wire_nlll1lli_dataout <= nlliO01i AND NOT(wire_nl1000i_w_lg_nli1i1ll5104w(0)); + wire_nlll1llii_dataout <= nlll1il0i AND NOT(niOiOl1ll); + wire_nlll1llil_dataout <= nlll1il0l AND NOT(niOiOl1ll); + wire_nlll1lliO_dataout <= nlll1il0O AND NOT(niOiOl1ll); + wire_nlll1lll_dataout <= niOO01l0l WHEN wire_nl1000i_w_lg_nli1i1ll5104w(0) = '1' ELSE nlliO01l; + wire_nlll1llli_dataout <= nlll1ilii OR niOiOl1ll; + wire_nlll1llll_dataout <= nlll1ilil AND NOT(niOiOl1ll); + wire_nlll1lOl_dataout <= wire_nlll1O0l_dataout WHEN niOO01lii = '1' ELSE nllillOi; + wire_nlll1lOO_dataout <= niOO01l0O AND niOO01lii; + wire_nlll1O00i_dataout <= wire_nlll1O0lO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O00l_dataout <= wire_nlll1O0Oi_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O00O_dataout <= wire_nlll1O0Ol_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O01i_dataout <= wire_nlll1OO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O01l_dataout <= wire_nlll1OO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O01O_dataout <= wire_nlll1O0ll_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O0i_dataout <= wire_nlll1OiO_dataout WHEN niOO01lii = '1' ELSE nlliO01l; + wire_nlll1O0ii_dataout <= wire_nlll1O0OO_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O0il_dataout <= wire_nlll1Oi1i_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O0iO_dataout <= wire_nlll1Oi1l_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O0l_dataout <= nli1i1ll WHEN niOO01l0O = '1' ELSE nllillOi; + wire_nlll1O0li_dataout <= wire_nlll1Oi1O_dataout AND NOT(wire_nl1000i_w_lg_nlilOO0iO5228w(0)); + wire_nlll1O0ll_dataout <= wire_nlll1OiOl_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1Oi0i_dataout; + wire_nlll1O0lO_dataout <= wire_nlll1OiOO_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1Oi0l_dataout; + wire_nlll1O0O_dataout <= wire_nlll1Oli_dataout AND NOT(niOO01l0O); + wire_nlll1O0Oi_dataout <= wire_nlll1Ol1i_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1Oi0O_dataout; + wire_nlll1O0Ol_dataout <= wire_nlll1Ol1l_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1Oiii_dataout; + wire_nlll1O0OO_dataout <= wire_nlll1Ol1O_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1Oiil_dataout; + wire_nlll1O10i_dataout <= wire_nlll1O00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O10l_dataout <= wire_nlll1O00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O10O_dataout <= wire_nlll1O0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O11i_dataout <= (niOO000ll AND wire_nlOl1l0Ol_dataout) AND NOT(wire_niO01O0O_dataout); + wire_nlll1O11l_dataout <= wire_nlll1O01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O11O_dataout <= wire_nlll1O00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1i_dataout <= wire_nlll1O0O_dataout WHEN niOO01lii = '1' ELSE nlliO1Ol; + wire_nlll1O1ii_dataout <= wire_nlll1O0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1il_dataout <= wire_nlll1O0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1iO_dataout <= wire_nlll1O0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1l_dataout <= wire_nlll1Oii_dataout WHEN niOO01lii = '1' ELSE nlliO1OO; + wire_nlll1O1li_dataout <= wire_nlll1OlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1ll_dataout <= wire_nlll1OlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1lO_dataout <= wire_nlll1OlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1O_dataout <= wire_nlll1Oil_dataout WHEN niOO01lii = '1' ELSE nlliO01i; + wire_nlll1O1Oi_dataout <= wire_nlll1OO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1Ol_dataout <= wire_nlll1OO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1O1OO_dataout <= wire_nlll1OO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlll1Oi0i_dataout <= nlll1lOii WHEN niOiOl1Oi = '1' ELSE nlll1llOl; + wire_nlll1Oi0l_dataout <= nlll1lOil WHEN niOiOl1Oi = '1' ELSE nlll1llOO; + wire_nlll1Oi0O_dataout <= nlll1lOiO WHEN niOiOl1Oi = '1' ELSE nlll1lO1i; + wire_nlll1Oi1i_dataout <= wire_nlll1Ol0i_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1OiiO_dataout; + wire_nlll1Oi1l_dataout <= wire_nlll1Ol0l_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1Oili_dataout; + wire_nlll1Oi1O_dataout <= wire_nlll1Ol0O_dataout WHEN niOiOl1OO = '1' ELSE wire_nlll1Oill_dataout; + wire_nlll1Oii_dataout <= wire_nlll1Oll_dataout AND NOT(niOO01l0O); + wire_nlll1Oiii_dataout <= nlll1lOli WHEN niOiOl1Oi = '1' ELSE nlll1lO1l; + wire_nlll1Oiil_dataout <= nlll1lOll WHEN niOiOl1Oi = '1' ELSE nlll1lO1O; + wire_nlll1OiiO_dataout <= nlll1lOlO WHEN niOiOl1Oi = '1' ELSE nlll1lO0i; + wire_nlll1Oil_dataout <= wire_nlll1OlO_dataout AND NOT(niOO01l0O); + wire_nlll1Oili_dataout <= nlll1lOOi WHEN niOiOl1Oi = '1' ELSE nlll1lO0l; + wire_nlll1Oill_dataout <= nlll1lOOl WHEN niOiOl1Oi = '1' ELSE nlll1lO0O; + wire_nlll1OiO_dataout <= wire_nlll1OOi_dataout OR niOO01l0O; + wire_nlll1OiOl_dataout <= wire_nlll1Olii_o(0) AND NOT(niOiOl1Ol); + wire_nlll1OiOO_dataout <= wire_nlll1Olii_o(1) AND NOT(niOiOl1Ol); + wire_nlll1Ol0i_dataout <= wire_nlll1Olii_o(5) AND NOT(niOiOl1Ol); + wire_nlll1Ol0l_dataout <= wire_nlll1Olii_o(6) AND NOT(niOiOl1Ol); + wire_nlll1Ol0O_dataout <= wire_nlll1Olii_o(7) AND NOT(niOiOl1Ol); + wire_nlll1Ol1i_dataout <= wire_nlll1Olii_o(2) AND NOT(niOiOl1Ol); + wire_nlll1Ol1l_dataout <= wire_nlll1Olii_o(3) AND NOT(niOiOl1Ol); + wire_nlll1Ol1O_dataout <= wire_nlll1Olii_o(4) AND NOT(niOiOl1Ol); + wire_nlll1Oli_dataout <= nlliO1Ol OR k_hip(0); + wire_nlll1Oll_dataout <= nlliO1OO AND NOT(k_hip(0)); + wire_nlll1OlO_dataout <= nlliO01i AND NOT(k_hip(0)); + wire_nlll1OlOi_dataout <= nlll1llOl WHEN nlll1OOii = '1' ELSE nlll1lOii; + wire_nlll1OlOl_dataout <= nlll1llOO WHEN nlll1OOii = '1' ELSE nlll1lOil; + wire_nlll1OlOO_dataout <= nlll1lO1i WHEN nlll1OOii = '1' ELSE nlll1lOiO; + wire_nlll1OO0i_dataout <= nlll1lO0l WHEN nlll1OOii = '1' ELSE nlll1lOOi; + wire_nlll1OO0l_dataout <= nlll1lO0O WHEN nlll1OOii = '1' ELSE nlll1lOOl; + wire_nlll1OO1i_dataout <= nlll1lO1l WHEN nlll1OOii = '1' ELSE nlll1lOli; + wire_nlll1OO1l_dataout <= nlll1lO1O WHEN nlll1OOii = '1' ELSE nlll1lOll; + wire_nlll1OO1O_dataout <= nlll1lO0i WHEN nlll1OOii = '1' ELSE nlll1lOlO; + wire_nlll1OOi_dataout <= nlliO01l AND NOT(k_hip(0)); + wire_nlll1OOiO_dataout <= wire_nlll1OOlO_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1OOli_dataout <= wire_nlll1OOOi_o AND NOT(wire_niO01O0O_dataout); + wire_nlll1OOll_dataout <= wire_nlll1OOOl_o OR wire_niO01O0O_dataout; + wire_nlll1OOOO_dataout <= nlll1lOOO AND NOT(nlll1ilil); + wire_nllli01O_dataout <= (wire_nl1000i_w_lg_nllli0il4654w(0) AND wire_w_lg_w_k_hip_range2413w4666w(0)) OR (wire_nl1000i_w_lg_nllli0il4654w(0) AND (wire_w_lg_w_k_hip_range2413w2429w(0) AND ((((NOT (nllliili XOR nlllii0O)) AND (NOT (nllliill XOR nllliiii))) AND (NOT (nllliilO XOR nllliiil))) AND (NOT (nllliiOi XOR nllliiiO))))); + wire_nllli01O_w_lg_dataout4682w(0) <= wire_nllli01O_dataout AND wire_nl1000i_w_lg_nllli1il4681w(0); + wire_nllli01O_w_lg_dataout4050w(0) <= NOT wire_nllli01O_dataout; + wire_nllli0iO_dataout <= nlllllil AND NOT(wire_niO01O0O_dataout); + wire_nllli0li_dataout <= nllllliO AND NOT(wire_niO01O0O_dataout); + wire_nllli0ll_dataout <= nlllllli AND NOT(wire_niO01O0O_dataout); + wire_nllli0lO_dataout <= nlllllll AND NOT(wire_niO01O0O_dataout); + wire_nllli1ll_dataout <= (wire_nlllOl0O_w_lg_dataout4679w(0) AND wire_nllli01O_w_lg_dataout4682w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nllli1lO_dataout <= nllli1il AND NOT(wire_niO01O0O_dataout); + wire_nllli1Oi_dataout <= (wire_nlllOl0O_w_lg_dataout4679w(0) AND wire_nllli01O_dataout) AND NOT(wire_niO01O0O_dataout); + wire_nlllil0O_dataout <= wire_nllliOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlllilii_dataout <= nlllii1l AND NOT(wire_niO01O0O_dataout); + wire_nlllilil_dataout <= nlllii1O AND NOT(wire_niO01O0O_dataout); + wire_nllliliO_dataout <= nlllii0i AND NOT(wire_niO01O0O_dataout); + wire_nlllilli_dataout <= nlllii0l AND NOT(wire_niO01O0O_dataout); + wire_nlllilll_dataout <= nlllii0O AND NOT(wire_niO01O0O_dataout); + wire_nlllillO_dataout <= nllliiii AND NOT(wire_niO01O0O_dataout); + wire_nlllilOi_dataout <= nllliiil AND NOT(wire_niO01O0O_dataout); + wire_nlllilOl_dataout <= nllliiiO AND NOT(wire_niO01O0O_dataout); + wire_nlllilOO_dataout <= nllli1li AND NOT(wire_niO01O0O_dataout); + wire_nllliO0i_dataout <= niOO01OOO AND NOT(wire_niO01O0O_dataout); + wire_nllliO0l_dataout <= niOO01OOi AND NOT(wire_niO01O0O_dataout); + wire_nllliO0O_dataout <= niOO01Oli AND NOT(wire_niO01O0O_dataout); + wire_nllliO1i_dataout <= nllli1iO AND NOT(wire_niO01O0O_dataout); + wire_nllliO1l_dataout <= nllli10l AND NOT(wire_niO01O0O_dataout); + wire_nllliO1O_dataout <= nlllil1i AND NOT(wire_niO01O0O_dataout); + wire_nllliOii_dataout <= niOO01OiO AND NOT(wire_niO01O0O_dataout); + wire_nllliOil_dataout <= nllli0il WHEN ((((NOT (niOO01O0O XOR niOO01O0i)) AND (NOT (niOO01Oii XOR niOO01O0l))) AND (NOT (niOO01Oll XOR niOO01Oil))) AND (NOT (nllliiOi XOR nllliiiO))) = '1' ELSE wire_nllliOiO_o; + wire_nllll0lO_dataout <= nllliili AND NOT(wire_niO01l0O_dataout); + wire_nllll0Oi_dataout <= nllliill AND NOT(wire_niO01l0O_dataout); + wire_nllll0Ol_dataout <= nllliilO AND NOT(wire_niO01l0O_dataout); + wire_nllll0OO_dataout <= nllliiOi AND NOT(wire_niO01l0O_dataout); + wire_nllllllO_dataout <= wire_nlllO1il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllllOi_dataout <= niOO001il AND NOT(wire_niO01l0O_dataout); + wire_nlllllOl_dataout <= niOO0010O AND NOT(wire_niO01l0O_dataout); + wire_nlllllOO_dataout <= niOO0010i AND NOT(wire_niO01l0O_dataout); + wire_nllllO0i_dataout <= niOO0011O AND NOT(wire_niO01l0O_dataout); + wire_nllllO0l_dataout <= nlllliOi AND NOT(wire_niO01l0O_dataout); + wire_nllllO0O_dataout <= (wire_nlllO1lO_o OR (nllll0ll AND ((((NOT wire_nllll00i_o(4)) AND (NOT wire_nllll00i_o(3))) AND (NOT wire_nllll00i_o(2))) AND (NOT wire_nllll00i_o(1))))) AND NOT(wire_niO01l0O_dataout); + wire_nllllO1i_dataout <= nlllllll AND NOT(wire_niO01l0O_dataout); + wire_nllllO1l_dataout <= niOO001ii AND NOT(wire_niO01l0O_dataout); + wire_nllllO1O_dataout <= niOO0010l AND NOT(wire_niO01l0O_dataout); + wire_nllllOii_dataout <= nlllil0l AND NOT(wire_niO01l0O_dataout); + wire_nllllOil_dataout <= nllliiOl AND NOT(wire_niO01l0O_dataout); + wire_nllllOiO_dataout <= nlllil1l AND NOT(wire_niO01l0O_dataout); + wire_nllllOli_dataout <= nlllil1O AND NOT(wire_niO01l0O_dataout); + wire_nllllOll_dataout <= wire_nlllO00O_dataout OR wire_niO01l0O_dataout; + wire_nllllOlO_dataout <= wire_nlllO0ii_dataout OR wire_niO01l0O_dataout; + wire_nllllOOi_dataout <= wire_nlllO0il_dataout AND NOT(wire_niO01l0O_dataout); + wire_nllllOOl_dataout <= wire_nlllO0iO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nllllOOO_dataout <= wire_nlllO01l_dataout OR wire_niO01l0O_dataout; + wire_nlllO00i_dataout <= nlllll1i WHEN tx_valid_vc0 = '1' ELSE nlllll0O; + wire_nlllO00l_dataout <= nlllll1l WHEN tx_valid_vc0 = '1' ELSE nlllllii; + wire_nlllO00O_dataout <= (wire_w_lg_niOO001lO4482w(0) XOR nlllliOl) WHEN tx_valid_vc0 = '1' ELSE nlllliOl; + wire_nlllO01i_dataout <= nlllllii WHEN tx_valid_vc0 = '1' ELSE nlllllll; + wire_nlllO01l_dataout <= nlllliOl WHEN tx_valid_vc0 = '1' ELSE nlllll0i; + wire_nlllO01O_dataout <= nlllliOO WHEN tx_valid_vc0 = '1' ELSE nlllll0l; + wire_nlllO0ii_dataout <= ((niOO001lO AND wire_w_lg_niOO001ll4483w(0)) XOR nlllliOO) WHEN tx_valid_vc0 = '1' ELSE nlllliOO; + wire_nlllO0il_dataout <= ((wire_w_lg_niOO001li4490w(0) AND wire_w_lg_niOO001iO4486w(0)) XOR nlllll1i) WHEN tx_valid_vc0 = '1' ELSE nlllll1i; + wire_nlllO0iO_dataout <= ((NOT (niOO001li OR wire_w_lg_niOO001iO4486w(0))) XOR nlllll1l) WHEN tx_valid_vc0 = '1' ELSE nlllll1l; + wire_nlllO10i_dataout <= wire_nlllO1Oi_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllO10l_dataout <= wire_nlllO1Ol_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllO10O_dataout <= wire_nlllO1OO_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllO11i_dataout <= wire_nlllO01O_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllO11l_dataout <= wire_nlllO00i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllO11O_dataout <= wire_nlllO00l_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllO1ii_dataout <= wire_nlllO01i_dataout AND NOT(wire_niO01l0O_dataout); + wire_nlllO1il_dataout <= nllll0ll WHEN ((((NOT (niOO001il XOR niOO001ii)) AND (NOT (niOO0010O XOR niOO0010l))) AND (NOT (niOO0010i XOR niOO0011O))) AND (NOT (nlllllll XOR nlllliOi))) = '1' ELSE wire_nlllO1iO_o; + wire_nlllO1Oi_dataout <= nlllll0i WHEN tx_valid_vc0 = '1' ELSE nlllllil; + wire_nlllO1Ol_dataout <= nlllll0l WHEN tx_valid_vc0 = '1' ELSE nllllliO; + wire_nlllO1OO_dataout <= nlllll0O WHEN tx_valid_vc0 = '1' ELSE nlllllli; + wire_nlllOl0O_dataout <= wire_n1ll00l_dataout WHEN wire_w_lg_w_k_gbl_hip_range1050w1051w(0) = '1' ELSE wire_nlO0Ol1O_dataout; + wire_nlllOl0O_w_lg_dataout4591w(0) <= wire_nlllOl0O_dataout AND wire_w_lg_niOO01OlO4590w(0); + wire_nlllOl0O_w_lg_dataout4679w(0) <= NOT wire_nlllOl0O_dataout; + wire_nlllOlii_dataout <= k_hip(12) AND NOT(niOO001Oi); + wire_nlllOlil_dataout <= k_hip(13) AND NOT(niOO001Oi); + wire_nlllOliO_dataout <= k_hip(14) OR niOO001Oi; + wire_nlllOlli_dataout <= k_hip(15) OR niOO001Oi; + wire_nllO0iii_dataout <= wire_nllOO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0iil_dataout <= wire_nllOO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0iiO_dataout <= wire_nllOO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0ili_dataout <= wire_nllOO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0ill_dataout <= wire_nllOO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0ilO_dataout <= wire_nllOO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0iOi_dataout <= wire_nllOO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0iOl_dataout <= wire_nllOO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0iOO_dataout <= wire_nllOO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0l0i_dataout <= wire_nllOO00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0l0l_dataout <= wire_nllOO0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0l0O_dataout <= wire_nllOO0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0l1i_dataout <= wire_nllOO01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0l1l_dataout <= wire_nllOO00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0l1O_dataout <= wire_nllOO00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0lii_dataout <= wire_nllOO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0lil_dataout <= wire_nllOO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0liO_dataout <= wire_nllOO0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0lli_dataout <= wire_nllOO0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0lll_dataout <= wire_nllOO0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0llO_dataout <= wire_nllOO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0lOi_dataout <= wire_nllOO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0lOl_dataout <= wire_nllOOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0lOO_dataout <= wire_nllOOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0O0i_dataout <= wire_nllOOi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0O0l_dataout <= wire_nllOOiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0O0O_dataout <= wire_nllOOiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0O1i_dataout <= wire_nllOOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0O1l_dataout <= wire_nllOOi0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0O1O_dataout <= wire_nllOOi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0Oii_dataout <= wire_nllOOiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0Oil_dataout <= wire_nllOOili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0OiO_dataout <= wire_nllOOill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0Oli_dataout <= wire_nllOOilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0Oll_dataout <= wire_nllOOiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0OlO_dataout <= wire_nllOOiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0OOi_dataout <= wire_nllOOiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0OOl_dataout <= wire_nllOOl1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllO0OOO_dataout <= wire_nllOOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi00i_dataout <= wire_nllOOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi00l_dataout <= wire_nllOOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi00O_dataout <= wire_nllOOOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi01i_dataout <= wire_nllOOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi01l_dataout <= wire_nllOOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi01O_dataout <= wire_nllOOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0ii_dataout <= wire_nllOOOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0il_dataout <= wire_nllOOOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0iO_dataout <= wire_nllOOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0li_dataout <= wire_nllOOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0ll_dataout <= wire_nllOl01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0lO_dataout <= wire_nllOl00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0Oi_dataout <= wire_nllOl00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0Ol_dataout <= wire_nllOl00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi0OO_dataout <= wire_nllOl0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi10i_dataout <= wire_nllOOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi10l_dataout <= wire_nllOOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi10O_dataout <= wire_nllOOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi11i_dataout <= wire_nllOOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi11l_dataout <= wire_nllOOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi11O_dataout <= wire_nllOOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1ii_dataout <= wire_nllOOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1il_dataout <= wire_nllOOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1iO_dataout <= wire_nllOOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1li_dataout <= wire_nllOOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1ll_dataout <= wire_nllOOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1lO_dataout <= wire_nllOOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1Oi_dataout <= wire_nllOOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1Ol_dataout <= wire_nllOOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOi1OO_dataout <= wire_nllOOO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOii0i_dataout <= wire_nllOl0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOii0l_dataout <= wire_nllOl0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOii0O_dataout <= wire_nllOl0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOii1i_dataout <= wire_nllOl0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOii1l_dataout <= wire_nllOl0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOii1O_dataout <= wire_nllOl0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiiii_dataout <= wire_nllOl0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiiil_dataout <= wire_nllOl0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiiiO_dataout <= wire_nllOli1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiili_dataout <= wire_nllOli1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiill_dataout <= wire_nllOli1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiilO_dataout <= wire_nllOli0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiiOi_dataout <= wire_nllOli0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiiOl_dataout <= wire_nllOli0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiiOO_dataout <= wire_nllOliii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOil0i_dataout <= wire_nllOlill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOil0l_dataout <= wire_nllOlilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOil0O_dataout <= wire_nllOliOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOil1i_dataout <= wire_nllOliil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOil1l_dataout <= wire_nllOliiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOil1O_dataout <= wire_nllOlili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilii_dataout <= wire_nllOliOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiliii_dataout <= wire_nllOilOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiliil_dataout <= wire_nllOilOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiliiO_dataout <= wire_nllOilOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilil_dataout <= wire_nllOliOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilili_dataout <= wire_nllOilOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilill_dataout <= wire_nllOilOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOililO_dataout <= wire_nllOilOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiliO_dataout <= wire_nllOll1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiliOi_dataout <= wire_nllOilOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiliOl_dataout <= wire_nllOiO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiliOO_dataout <= wire_nllOiO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOill0i_dataout <= wire_nllOiO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOill0l_dataout <= wire_nllOiO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOill0O_dataout <= wire_nllOiO1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOill1i_dataout <= wire_nllOiO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOill1l_dataout <= wire_nllOiO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOill1O_dataout <= wire_nllOiO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilli_dataout <= wire_nllOll1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillii_dataout <= wire_nllOiO1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillil_dataout <= wire_nllOiO1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilliO_dataout <= wire_nllOiO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilll_dataout <= wire_nllOll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillli_dataout <= wire_nllOiO1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillll_dataout <= wire_nllOiO1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilllO_dataout <= wire_nllOiO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillO_dataout <= wire_nllOll0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillOi_dataout <= wire_nllOiO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillOl_dataout <= wire_nllOiO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOillOO_dataout <= wire_nllOiO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilO0i_dataout <= wire_nllOiO00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilO0l_dataout <= wire_nllOiO0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilO0O_dataout <= wire_nllOiO0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilO1i_dataout <= wire_nllOiO01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilO1l_dataout <= wire_nllOiO00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilO1O_dataout <= wire_nllOiO00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilOi_dataout <= wire_nllOll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilOii_dataout <= wire_nllOiO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilOil_dataout <= wire_nllOiO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilOiO_dataout <= wire_nllOiO0ll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOl11OO; + wire_nllOilOl_dataout <= wire_nllOll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilOli_dataout <= wire_nllOiO0lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil10O; + wire_nllOilOll_dataout <= wire_nllOiO0Oi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1ii; + wire_nllOilOlO_dataout <= wire_nllOiO0Ol_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1il; + wire_nllOilOO_dataout <= wire_nllOllii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOilOOi_dataout <= wire_nllOiO0OO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1iO; + wire_nllOilOOl_dataout <= wire_nllOiOi1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1li; + wire_nllOilOOO_dataout <= wire_nllOiOi1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1ll; + wire_nllOiO00i_dataout <= wire_nllOiOl0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0OO; + wire_nllOiO00l_dataout <= wire_nllOiOlii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOili1i; + wire_nllOiO00O_dataout <= wire_nllOiOlil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOili1l; + wire_nllOiO01i_dataout <= wire_nllOiOl1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0lO; + wire_nllOiO01l_dataout <= wire_nllOiOl0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0Oi; + wire_nllOiO01O_dataout <= wire_nllOiOl0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0Ol; + wire_nllOiO0i_dataout <= wire_nllOllll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiO0ii_dataout <= wire_nllOiOliO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOili1O; + wire_nllOiO0il_dataout <= wire_nllOiOlli_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOili0i; + wire_nllOiO0iO_dataout <= wire_nllOiOlll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOili0l; + wire_nllOiO0l_dataout <= wire_nllOlllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiO0li_dataout <= wire_nllOiOllO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOili0O; + wire_nllOiO0ll_dataout <= (NOT (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol1iO_dataout))) WHEN nlO00O11l = '1' ELSE wire_nllOiOlOi_dataout; + wire_nllOiO0lO_dataout <= (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol1il_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol01O_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOlOl_dataout; + wire_nllOiO0O_dataout <= wire_nllOllOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiO0Oi_dataout <= (NOT (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol1il_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol01l_dataout))))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOlOO_dataout; + wire_nllOiO0Ol_dataout <= (NOT (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1il_dataout XOR (wire_nlO0Ol01l_dataout XOR wire_nlO0Ol01i_dataout)))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOO1i_dataout; + wire_nllOiO0OO_dataout <= (NOT (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol01i_dataout))))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOO1l_dataout; + wire_nllOiO10i_dataout <= wire_nllOiOi0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1OO; + wire_nllOiO10l_dataout <= wire_nllOiOiii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil01i; + wire_nllOiO10O_dataout <= wire_nllOiOiil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil01l; + wire_nllOiO11i_dataout <= wire_nllOiOi1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1lO; + wire_nllOiO11l_dataout <= wire_nllOiOi0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1Oi; + wire_nllOiO11O_dataout <= wire_nllOiOi0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil1Ol; + wire_nllOiO1i_dataout <= wire_nllOllil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiO1ii_dataout <= wire_nllOiOiiO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil01O; + wire_nllOiO1il_dataout <= wire_nllOiOili_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil00i; + wire_nllOiO1iO_dataout <= wire_nllOiOill_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil00l; + wire_nllOiO1l_dataout <= wire_nllOlliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiO1li_dataout <= wire_nllOiOilO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil00O; + wire_nllOiO1ll_dataout <= wire_nllOiOiOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0ii; + wire_nllOiO1lO_dataout <= wire_nllOiOiOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0il; + wire_nllOiO1O_dataout <= wire_nllOllli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiO1Oi_dataout <= wire_nllOiOiOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0iO; + wire_nllOiO1Ol_dataout <= wire_nllOiOl1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0li; + wire_nllOiO1OO_dataout <= wire_nllOiOl1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllOil0ll; + wire_nllOiOi0i_dataout <= (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol1ll_dataout)))) WHEN nlO00O11l = '1' ELSE wire_nllOiOO0O_dataout; + wire_nllOiOi0l_dataout <= (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol01O_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOii_dataout; + wire_nllOiOi0O_dataout <= (NOT (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol01l_dataout)))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOil_dataout; + wire_nllOiOi1i_dataout <= (NOT (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol1il_dataout)))))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOO1O_dataout; + wire_nllOiOi1l_dataout <= (NOT (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol01l_dataout XOR wire_nlO0Ol1il_dataout))))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOO0i_dataout; + wire_nllOiOi1O_dataout <= (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol01i_dataout XOR wire_nlO0Ol1il_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOO0l_dataout; + wire_nllOiOii_dataout <= wire_nllOllOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOiii_dataout <= (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol00i_dataout XOR (wire_nlO0Ol01l_dataout XOR wire_nlO0Ol01i_dataout)))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOiO_dataout; + wire_nllOiOiil_dataout <= (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol00i_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol01i_dataout)))))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOli_dataout; + wire_nllOiOiiO_dataout <= (NOT (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol1il_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol01l_dataout)))))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOll_dataout; + wire_nllOiOil_dataout <= wire_nllOllOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOili_dataout <= (NOT (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol1il_dataout XOR (wire_nlO0Ol01l_dataout XOR wire_nlO0Ol01i_dataout))))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOlO_dataout; + wire_nllOiOill_dataout <= (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol1il_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol01i_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOOi_dataout; + wire_nllOiOilO_dataout <= (NOT (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol01O_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOOl_dataout; + wire_nllOiOiO_dataout <= wire_nllOlO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOiOi_dataout <= (NOT (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol01l_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOiOOOO_dataout; + wire_nllOiOiOl_dataout <= (NOT (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol1il_dataout XOR (wire_nlO0Ol01l_dataout XOR wire_nlO0Ol01i_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOl111i_dataout; + wire_nllOiOiOO_dataout <= (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol01i_dataout XOR wire_nlO0Ol1il_dataout)) WHEN nlO00O11l = '1' ELSE wire_nllOl111l_dataout; + wire_nllOiOl0i_dataout <= (NOT (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol01i_dataout))))) WHEN nlO00O11l = '1' ELSE wire_nllOl110O_dataout; + wire_nllOiOl0l_dataout <= (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol01l_dataout XOR wire_nlO0Ol1il_dataout))) WHEN nlO00O11l = '1' ELSE wire_nllOl11ii_dataout; + wire_nllOiOl0O_dataout <= (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol01i_dataout XOR wire_nlO0Ol1lO_dataout)) WHEN nlO00O11l = '1' ELSE wire_nllOl11il_dataout; + wire_nllOiOl1i_dataout <= (NOT (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol1ll_dataout)) WHEN nlO00O11l = '1' ELSE wire_nllOl111O_dataout; + wire_nllOiOl1l_dataout <= (NOT (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol1li_dataout)) WHEN nlO00O11l = '1' ELSE wire_nllOl110i_dataout; + wire_nllOiOl1O_dataout <= (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol01l_dataout)) WHEN nlO00O11l = '1' ELSE wire_nllOl110l_dataout; + wire_nllOiOli_dataout <= wire_nllOlO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOlii_dataout <= (wire_nlO0Ol1OO_dataout XOR (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1ll_dataout XOR wire_nlO0Ol1iO_dataout))) WHEN nlO00O11l = '1' ELSE wire_nllOl11iO_dataout; + wire_nllOiOlil_dataout <= (wire_nlO0Ol1Ol_dataout XOR (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol1li_dataout XOR wire_nlO0Ol1il_dataout))) WHEN nlO00O11l = '1' ELSE wire_nllOl11li_dataout; + wire_nllOiOliO_dataout <= (wire_nlO0Ol1Oi_dataout XOR (wire_nlO0Ol1li_dataout XOR (wire_nlO0Ol00i_dataout XOR wire_nlO0Ol1iO_dataout))) WHEN nlO00O11l = '1' ELSE wire_nllOl11ll_dataout; + wire_nllOiOll_dataout <= wire_nllOlO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOlli_dataout <= (wire_nlO0Ol1lO_dataout XOR (wire_nlO0Ol1iO_dataout XOR (wire_nlO0Ol01O_dataout XOR wire_nlO0Ol1il_dataout))) WHEN nlO00O11l = '1' ELSE wire_nllOl11lO_dataout; + wire_nllOiOlll_dataout <= (wire_nlO0Ol1ll_dataout XOR (wire_nlO0Ol01l_dataout XOR wire_nlO0Ol1il_dataout)) WHEN nlO00O11l = '1' ELSE wire_nllOl11Oi_dataout; + wire_nllOiOllO_dataout <= (wire_nlO0Ol01i_dataout XOR wire_nlO0Ol1li_dataout) WHEN nlO00O11l = '1' ELSE wire_nllOl11Ol_dataout; + wire_nllOiOlO_dataout <= wire_nllOlO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOlOi_dataout <= (nllOili0O XOR (nllOili0l XOR (nllOili0i XOR (nllOili1O XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil00O XOR (nllOil01l XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1ll XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOlO1i))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0i XOR (nllOili1O XOR (nllOili1i XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0il XOR (nllOil00O XOR (nllOil00l XOR (nllOil01O XOR (nllOil01l XOR (nllOil1li XOR (nllOil1ii XOR (nllOl11OO XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR niOiOlili))))))))))))))))))))))))))))))))))))))); + wire_nllOiOlOl_dataout <= (nllOili1O XOR (nllOili1l XOR (nllOil0Ol XOR (nllOil0ii XOR (nllOil00O XOR (nllOil01O XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOll0l)))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0l XOR (nllOili1O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0ll XOR (nllOil0iO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00l XOR (nllOil00i XOR (nllOil01l XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1il XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOlill))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOlOO_dataout <= (nllOili0O XOR (nllOili0l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00O XOR (nllOil00i XOR (nllOil01O XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1ii XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOliii)))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili1l XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil01l XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1il XOR (nllOl11OO XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR niOiOliOi))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOO0i_dataout <= (nllOili0l XOR (nllOili0i XOR (nllOil0OO XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil00i XOR (nllOil01i XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOllil)))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili1O XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00l XOR (nllOil01O XOR (nllOil01i XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1ll XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOliiO))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOO0l_dataout <= (nllOili0i XOR (nllOili1O XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil00O XOR (nllOil00l XOR (nllOil1OO XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1li XOR (nllOil1il XOR (nllOil1ii XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOllii)))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili1O XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00l XOR (nllOil00i XOR (nllOil01O XOR (nllOil01i XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1lO XOR (nllOil1li XOR (nllOil1ii XOR (nllOl11OO XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR wire_nlO0i0i1i_dataout))))))))))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOO0O_dataout <= (nllOili0O XOR (nllOili1O XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ii XOR (nllOil01l XOR (nllOil01i XOR (nllOil1OO XOR (nllOil1Oi XOR (nllOil1iO XOR (nllOil1il XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR niOiOliOO)))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili1O XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0lO XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00i XOR (nllOil01O XOR (nllOil01i XOR (nllOil1OO XOR (nllOil1Oi XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1il XOR (nllOil1ii XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOlilO)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOO1i_dataout <= (nllOili0O XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0iO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00l XOR (nllOil00i XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1il XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOliil)))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili1O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil01O XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1iO XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOll0l))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOO1l_dataout <= (nllOili0O XOR (nllOili0l XOR (nllOili0i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00l XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Oi XOR (nllOil1ll XOR (nllOil1iO XOR (nllOil1il XOR (nllOil1ii XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOlO1l))))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0il XOR (nllOil00O XOR (nllOil00l XOR (nllOil00i XOR (nllOil01O XOR (nllOil01l XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil10O XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOliil))))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOO1O_dataout <= (nllOili0i XOR (nllOili1O XOR (nllOil0Ol XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil01O XOR (nllOil1OO XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1il XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOllii)))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0i XOR (nllOili1l XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0iO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00i XOR (nllOil01l XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1li XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR niOiOliOl)))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOi_dataout <= wire_nllOlO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOOii_dataout <= (nllOili0i XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0il XOR (nllOil01O XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR wire_nlO0i00OO_dataout))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0i XOR (nllOili1O XOR (nllOili1i XOR (nllOil0Oi XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil00l XOR (nllOil00i XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1iO XOR (nllOil1il XOR (nllOil1ii XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOllii)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOil_dataout <= (nllOili0O XOR (nllOili0i XOR (nllOili1O XOR (nllOili1i XOR (nllOil0iO XOR (nllOil00O XOR (nllOil00i XOR (nllOil01O XOR (nllOil1Ol XOR (nllOil1li XOR (nllOil1il XOR (nllOil1ii XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00iO_dataout XOR niOiOlili)))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0l XOR (nllOili1O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0li XOR (nllOil0il XOR (nllOil1OO XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1iO XOR (nllOil1il XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR niOiOlill))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOiO_dataout <= (nllOili0O XOR (nllOili1O XOR (nllOili1l XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0li XOR (nllOil0ii XOR (nllOil00O XOR (nllOil00l XOR (nllOil00i XOR (nllOil01l XOR (nllOil1Ol XOR (nllOil1iO XOR (nllOil1il XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOlilO))))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili1l XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00O XOR (nllOil00l XOR (nllOil01O XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1iO XOR (nllOil10O XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOliOi)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOl_dataout <= wire_nllOlO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOOli_dataout <= (nllOili0O XOR (nllOili0l XOR (nllOili1l XOR (nllOil0Ol XOR (nllOil0ll XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00l XOR (nllOil01O XOR (nllOil01l XOR (nllOil1Ol XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1ii XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOll1i))))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0i XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00l XOR (nllOil00i XOR (nllOil1OO XOR (nllOil1Ol XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOliOl)))))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOll_dataout <= (nllOili0O XOR (nllOili1O XOR (nllOil0OO XOR (nllOil0lO XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00O XOR (nllOil00i XOR (nllOil01O XOR (nllOil1OO XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1il XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOliOO)))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili1O XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00O XOR (nllOil00l XOR (nllOil01i XOR (nllOil1OO XOR (nllOl11OO XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR niOiOll0O))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOlO_dataout <= (nllOili0i XOR (nllOili1i XOR (nllOil0Oi XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0ii XOR (nllOil00l XOR (nllOil00i XOR (nllOil01i XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1iO XOR (nllOil1il XOR (nllOil1ii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i1O_dataout XOR wire_nlO0i00OO_dataout))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0i XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0ii XOR (nllOil00O XOR (nllOil01l XOR (nllOil01i XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR niOiOlliO))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOO_dataout <= wire_nllOlOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOiOOOi_dataout <= (nllOili0l XOR (nllOili1l XOR (nllOil0Ol XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0il XOR (nllOil00O XOR (nllOil00l XOR (nllOil01l XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1il XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1l_dataout XOR wire_nlO0i00Ol_dataout))))))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili1O XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0il XOR (nllOil0ii XOR (nllOil01O XOR (nllOil01l XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOlO0l))))))))))))))))))))))))))))))))))))))))); + wire_nllOiOOOl_dataout <= (nllOili0l XOR (nllOili0i XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0iO XOR (nllOil0ii XOR (nllOil01O XOR (nllOil01l XOR (nllOil1Oi XOR (nllOil1li XOR (nllOil1iO XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOllOl))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOil0OO XOR (nllOil0Ol XOR (nllOil0iO XOR (nllOil00O XOR (nllOil00l XOR (nllOil00i XOR (nllOil01l XOR (nllOil1li XOR (nllOil1il XOR (nllOl11OO XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i0i0l_dataout XOR wire_nlO0i0i0i_dataout))))))))))))))))))))))))))))))))); + wire_nllOiOOOO_dataout <= (nllOili0O XOR (nllOili0l XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0li XOR (nllOil0il XOR (nllOil00i XOR (nllOil01O XOR (nllOil1Ol XOR (nllOil1ll XOR (nllOil1li XOR (nllOil10O XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOll1i))))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili1i XOR (nllOil0OO XOR (nllOil0li XOR (nllOil0ii XOR (nllOil00O XOR (nllOil00l XOR (nllOil01O XOR (nllOil1ll XOR (nllOil1iO XOR (nllOil10O XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0i_dataout XOR wire_nlO0i0i1O_dataout))))))))))))))))))))))))))))))))); + wire_nllOl00i_dataout <= wire_nllOOOOO_dataout WHEN niOO0000i = '1' ELSE nllO1iOO; + wire_nllOl00l_dataout <= wire_nlO1111i_dataout WHEN niOO0000i = '1' ELSE nllO1l1i; + wire_nllOl00O_dataout <= wire_nlO1111l_dataout WHEN niOO0000i = '1' ELSE nllO1l1l; + wire_nllOl01i_dataout <= wire_nllOOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl01l_dataout <= wire_nllOO1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl01O_dataout <= wire_nllOOOOl_dataout WHEN niOO0000i = '1' ELSE nllO1iOl; + wire_nllOl0ii_dataout <= wire_nlO1111O_dataout WHEN niOO0000i = '1' ELSE nllO1l1O; + wire_nllOl0il_dataout <= wire_nlO1110i_dataout WHEN niOO0000i = '1' ELSE nllO1l0i; + wire_nllOl0iO_dataout <= wire_nlO1110l_dataout WHEN niOO0000i = '1' ELSE nllO1l0l; + wire_nllOl0li_dataout <= wire_nlO1110O_dataout WHEN niOO0000i = '1' ELSE nllO1l0O; + wire_nllOl0ll_dataout <= wire_nlO111ii_dataout WHEN niOO0000i = '1' ELSE nllO1lii; + wire_nllOl0lO_dataout <= wire_nlO111il_dataout WHEN niOO0000i = '1' ELSE nllO1lil; + wire_nllOl0Oi_dataout <= wire_nlO111iO_dataout WHEN niOO0000i = '1' ELSE nllO1liO; + wire_nllOl0Ol_dataout <= wire_nlO111li_dataout WHEN niOO0000i = '1' ELSE nllO1lli; + wire_nllOl0OO_dataout <= wire_nlO111ll_dataout WHEN niOO0000i = '1' ELSE nllO1lll; + wire_nllOl10i_dataout <= wire_nllOlOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl10l_dataout <= wire_nllOlOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl10O_dataout <= wire_nllOlOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl110i_dataout <= (nllOili0O XOR (nllOili0i XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil01O XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1li XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i000O_dataout XOR niOiOlO0i))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili0i XOR (nllOil0Ol XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0ii XOR (nllOil1OO XOR (nllOil1Oi XOR (nllOil1li XOR (nllOil1il XOR (nllOil1ii XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOllil)))))))))))))))))))))))))))))))))); + wire_nllOl110l_dataout <= (nllOili0O XOR (nllOili0i XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00O XOR (nllOil00i XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR niOiOlliO)))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili0i XOR (nllOili1O XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0li XOR (nllOil00O XOR (nllOil00l XOR (nllOil01O XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1il XOR (nllOil1ii XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOllli))))))))))))))))))))))))))))))))))))))))))))))); + wire_nllOl110O_dataout <= (nllOili0O XOR (nllOili0i XOR (nllOili1l XOR (nllOili1i XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0ii XOR (nllOil00O XOR (nllOil00l XOR (nllOil01O XOR (nllOil1Ol XOR (nllOil1ll XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR niOiOllll)))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili1O XOR (nllOili1l XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00l XOR (nllOil00i XOR (nllOil1OO XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1iO XOR (nllOil1il XOR (nllOil1ii XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOlllO))))))))))))))))))))))))))))))))))))))))))); + wire_nllOl111i_dataout <= (nllOili0O XOR (nllOili1O XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0ll XOR (nllOil0iO XOR (nllOil00l XOR (nllOil00i XOR (nllOil1OO XOR (nllOil1lO XOR (nllOil1ll XOR (nllOil1ii XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOll1l))))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili1l XOR (nllOili1i XOR (nllOil0ll XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00O XOR (nllOil00i XOR (nllOil1lO XOR (nllOil1li XOR (nllOil1ii XOR (nllOl11OO XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOll1O))))))))))))))))))))))))))))))))); + wire_nllOl111l_dataout <= (nllOili0i XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0li XOR (nllOil00O XOR (nllOil00l XOR (nllOil01i XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1il XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOll0i)))))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili1O XOR (nllOili1l XOR (nllOil0lO XOR (nllOil0iO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00l XOR (nllOil1Oi XOR (nllOil1ll XOR (nllOil1il XOR (nllOil10O XOR (nllOl11OO XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR niOiOll0l)))))))))))))))))))))))))))))))))); + wire_nllOl111O_dataout <= (nllOili0l XOR (nllOili1O XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0ll XOR (nllOil0ii XOR (nllOil00O XOR (nllOil01l XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1iO XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOll0O))))))))))))))))))) WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0i XOR (nllOili1O XOR (nllOil0Oi XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00O XOR (nllOil1Ol XOR (nllOil1lO XOR (nllOil1iO XOR (nllOil1ii XOR (nllOil10O XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR niOiOllii)))))))))))))))))))))))))))))))))); + wire_nllOl11i_dataout <= wire_nllOlOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl11ii_dataout <= niOiOOill WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0i XOR (nllOili1O XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00O XOR (nllOil00l XOR (nllOil01i XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOil1li XOR (nllOil1iO XOR (nllOil1il XOR (nllOl11OO XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOllOi)))))))))))))))))))))))))))))))))))))))))))); + wire_nllOl11il_dataout <= niOiOOiOi WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili0i XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0ii XOR (nllOil00O XOR (nllOil01l XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil1ll XOR (nllOil1li XOR (nllOil1iO XOR (nllOil10O XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOllOl)))))))))))))))))))))))))))))))))))))))))); + wire_nllOl11iO_dataout <= niOiOOiOO WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0l XOR (nllOili0i XOR (nllOili1O XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0lO XOR (nllOil0li XOR (nllOil0ii XOR (nllOil00O XOR (nllOil00l XOR (nllOil01l XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1lO XOR (nllOil1ll XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOllOO))))))))))))))))))))))))))))))))))))))))))); + wire_nllOl11l_dataout <= wire_nllOlOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl11li_dataout <= niOiOOl1l WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0l XOR (nllOili0i XOR (nllOili1O XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0Oi XOR (nllOil0ll XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00O XOR (nllOil01O XOR (nllOil01i XOR (nllOil1OO XOR (nllOil1Oi XOR (nllOil1lO XOR (nllOl11OO XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOlO1i))))))))))))))))))))))))))))))))))))))))))); + wire_nllOl11ll_dataout <= niOiOOl0i WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0l XOR (nllOili0i XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0Ol XOR (nllOil0lO XOR (nllOil0iO XOR (nllOil0il XOR (nllOil0ii XOR (nllOil00i XOR (nllOil01l XOR (nllOil01i XOR (nllOil1Ol XOR (nllOil1Oi XOR (nllOil10O XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOlO1l))))))))))))))))))))))))))))))))))))))))))); + wire_nllOl11lO_dataout <= niOiOOl0O WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0l XOR (nllOili1O XOR (nllOili1i XOR (nllOil0OO XOR (nllOil0Oi XOR (nllOil0li XOR (nllOil0iO XOR (nllOil0il XOR (nllOil00l XOR (nllOil01O XOR (nllOil01l XOR (nllOil1OO XOR (nllOil1Ol XOR (nllOil1ii XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i001O_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOlO1O))))))))))))))))))))))))))))))))))))))))); + wire_nllOl11O_dataout <= wire_nllOlOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl11Oi_dataout <= niOiOOlil WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (nllOili0O XOR (nllOili0i XOR (nllOili1l XOR (nllOili1i XOR (nllOil0Ol XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0iO XOR (nllOil00O XOR (nllOil00i XOR (nllOil01O XOR (nllOil01i XOR (nllOil1OO XOR (nllOil1il XOR (nllOl11OO XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOlO0i)))))))))))))))))))))))))))))))))))))); + wire_nllOl11Ol_dataout <= niOiOOlli WHEN wire_w_lg_niOl11l1O32019w(0) = '1' ELSE (niOOi1iiO XOR (nllOili0l XOR (nllOili1O XOR (nllOili1l XOR (nllOil0OO XOR (nllOil0lO XOR (nllOil0ll XOR (nllOil0li XOR (nllOil0ii XOR (nllOil00l XOR (nllOil00i XOR (nllOil01l XOR (nllOil01i XOR (nllOil1iO XOR (nllOil10O XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR niOiOlO0l)))))))))))))))))))))))))))))))))))))); + wire_nllOl1ii_dataout <= wire_nllOlOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1il_dataout <= wire_nllOlOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1iO_dataout <= wire_nllOO11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1li_dataout <= wire_nllOO11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1ll_dataout <= wire_nllOO11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1lO_dataout <= wire_nllOO10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1Oi_dataout <= wire_nllOO10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1Ol_dataout <= wire_nllOO10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOl1OO_dataout <= wire_nllOO1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nllOli0i_dataout <= wire_nlO111OO_dataout WHEN niOO0000i = '1' ELSE nllO1lOO; + wire_nllOli0l_dataout <= wire_nlO1101i_dataout WHEN niOO0000i = '1' ELSE nllO1O1i; + wire_nllOli0O_dataout <= wire_nlO1101l_dataout WHEN niOO0000i = '1' ELSE nllO1O1l; + wire_nllOli1i_dataout <= wire_nlO111lO_dataout WHEN niOO0000i = '1' ELSE nllO1llO; + wire_nllOli1l_dataout <= wire_nlO111Oi_dataout WHEN niOO0000i = '1' ELSE nllO1lOi; + wire_nllOli1O_dataout <= wire_nlO111Ol_dataout WHEN niOO0000i = '1' ELSE nllO1lOl; + wire_nllOliii_dataout <= wire_nlO1101O_dataout WHEN niOO0000i = '1' ELSE nllO1O1O; + wire_nllOliil_dataout <= wire_nlO1100i_dataout WHEN niOO0000i = '1' ELSE nllO1O0i; + wire_nllOliiO_dataout <= wire_nlO1100l_dataout WHEN niOO0000i = '1' ELSE nllO1O0l; + wire_nllOlili_dataout <= wire_nlO1100O_dataout WHEN niOO0000i = '1' ELSE nllO1O0O; + wire_nllOlill_dataout <= wire_nlO110ii_dataout WHEN niOO0000i = '1' ELSE nllO1Oii; + wire_nllOlilO_dataout <= wire_nlO110il_dataout WHEN niOO0000i = '1' ELSE nllO1Oil; + wire_nllOliOi_dataout <= wire_nlO110iO_dataout WHEN niOO0000i = '1' ELSE nllO1OiO; + wire_nllOliOl_dataout <= wire_nlO110li_dataout WHEN niOO0000i = '1' ELSE nllO1Oli; + wire_nllOliOO_dataout <= wire_nlO110ll_dataout WHEN niOO0000i = '1' ELSE nllO1Oll; + wire_nllOll0i_dataout <= wire_nlO110OO_dataout WHEN niOO0000i = '1' ELSE nllO1OOO; + wire_nllOll0l_dataout <= wire_nlO11i1i_dataout WHEN niOO0000i = '1' ELSE nllO011i; + wire_nllOll0O_dataout <= wire_nlO11i1l_dataout WHEN niOO0000i = '1' ELSE nllO011l; + wire_nllOll1i_dataout <= wire_nlO110lO_dataout WHEN niOO0000i = '1' ELSE nllO1OlO; + wire_nllOll1l_dataout <= wire_nlO110Oi_dataout WHEN niOO0000i = '1' ELSE nllO1OOi; + wire_nllOll1O_dataout <= wire_nlO110Ol_dataout WHEN niOO0000i = '1' ELSE nllO1OOl; + wire_nllOllii_dataout <= wire_nlO11i1O_dataout WHEN niOO0000i = '1' ELSE nllO011O; + wire_nllOllil_dataout <= wire_nlO11i0i_dataout WHEN niOO0000i = '1' ELSE nllO010i; + wire_nllOlliO_dataout <= wire_nlO11i0l_dataout WHEN niOO0000i = '1' ELSE nllO010l; + wire_nllOllli_dataout <= wire_nlO11i0O_dataout WHEN niOO0000i = '1' ELSE nllO010O; + wire_nllOllll_dataout <= wire_nlO11iii_dataout WHEN niOO0000i = '1' ELSE nllO01ii; + wire_nllOlllO_dataout <= wire_nlO11iil_dataout WHEN niOO0000i = '1' ELSE nllO01il; + wire_nllOllOi_dataout <= wire_nlO11iiO_dataout WHEN niOO0000i = '1' ELSE nllO01iO; + wire_nllOllOl_dataout <= wire_nlO11ili_dataout WHEN niOO0000i = '1' ELSE nllO01li; + wire_nllOllOO_dataout <= wire_nlO11ill_dataout WHEN niOO0000i = '1' ELSE nllO01ll; + wire_nllOlO0i_dataout <= wire_nlO11iOO_dataout WHEN niOO0000i = '1' ELSE nllO01OO; + wire_nllOlO0l_dataout <= wire_nlO11l1i_dataout WHEN niOO0000i = '1' ELSE nllO001i; + wire_nllOlO0O_dataout <= wire_nlO11l1l_dataout WHEN niOO0000i = '1' ELSE nllO001l; + wire_nllOlO1i_dataout <= wire_nlO11ilO_dataout WHEN niOO0000i = '1' ELSE nllO01lO; + wire_nllOlO1l_dataout <= wire_nlO11iOi_dataout WHEN niOO0000i = '1' ELSE nllO01Oi; + wire_nllOlO1O_dataout <= wire_nlO11iOl_dataout WHEN niOO0000i = '1' ELSE nllO01Ol; + wire_nllOlOii_dataout <= wire_nlO11l1O_dataout WHEN niOO0000i = '1' ELSE nllO001O; + wire_nllOlOil_dataout <= wire_nlO11l0i_dataout WHEN niOO0000i = '1' ELSE nllO000i; + wire_nllOlOiO_dataout <= wire_nlO11l0l_dataout WHEN niOO0000i = '1' ELSE nllO000l; + wire_nllOlOli_dataout <= wire_nlO11l0O_dataout WHEN niOO0000i = '1' ELSE nllO000O; + wire_nllOlOll_dataout <= wire_nlO11lii_dataout WHEN niOO0000i = '1' ELSE nllO00ii; + wire_nllOlOlO_dataout <= wire_nlO11lil_dataout WHEN niOO0000i = '1' ELSE nllO00il; + wire_nllOlOOi_dataout <= wire_nlO11liO_dataout WHEN niOO0000i = '1' ELSE nllO00iO; + wire_nllOlOOl_dataout <= wire_nlO11lli_dataout WHEN niOO0000i = '1' ELSE nllO00li; + wire_nllOlOOO_dataout <= wire_nlO11lll_dataout WHEN niOO0000i = '1' ELSE nllO00ll; + wire_nllOO00i_dataout <= wire_nlll0lli_q(10) WHEN niOO0000i = '1' ELSE nlllOO0l; + wire_nllOO00l_dataout <= wire_nlll0lli_q(11) WHEN niOO0000i = '1' ELSE nlllOO0O; + wire_nllOO00O_dataout <= wire_nlll0lli_q(12) WHEN niOO0000i = '1' ELSE nlllOOii; + wire_nllOO01i_dataout <= wire_nlll0lli_q(7) WHEN niOO0000i = '1' ELSE nlllOO1l; + wire_nllOO01l_dataout <= wire_nlll0lli_q(8) WHEN niOO0000i = '1' ELSE nlllOO1O; + wire_nllOO01O_dataout <= wire_nlll0lli_q(9) WHEN niOO0000i = '1' ELSE nlllOO0i; + wire_nllOO0ii_dataout <= wire_nlll0lli_q(13) WHEN niOO0000i = '1' ELSE nlllOOil; + wire_nllOO0il_dataout <= wire_nlll0lli_q(14) WHEN niOO0000i = '1' ELSE nlllOOiO; + wire_nllOO0iO_dataout <= wire_nlll0lli_q(15) WHEN niOO0000i = '1' ELSE nlllOOli; + wire_nllOO0li_dataout <= wire_nlll0lli_q(16) WHEN niOO0000i = '1' ELSE nlllOOll; + wire_nllOO0ll_dataout <= wire_nlll0lli_q(17) WHEN niOO0000i = '1' ELSE nlllOOlO; + wire_nllOO0lO_dataout <= wire_nlll0lli_q(18) WHEN niOO0000i = '1' ELSE nlllOOOi; + wire_nllOO0Oi_dataout <= wire_nlll0lli_q(19) WHEN niOO0000i = '1' ELSE nlllOOOl; + wire_nllOO0Ol_dataout <= wire_nlll0lli_q(20) WHEN niOO0000i = '1' ELSE nlllOOOO; + wire_nllOO0OO_dataout <= wire_nlll0lli_q(21) WHEN niOO0000i = '1' ELSE nllO111i; + wire_nllOO10i_dataout <= wire_nlO11lOO_dataout WHEN niOO0000i = '1' ELSE nllO00OO; + wire_nllOO10l_dataout <= wire_nlO11O1i_dataout WHEN niOO0000i = '1' ELSE nllO0i1i; + wire_nllOO10O_dataout <= wire_nlO11O1l_dataout WHEN niOO0000i = '1' ELSE nllO0i1l; + wire_nllOO11i_dataout <= wire_nlO11llO_dataout WHEN niOO0000i = '1' ELSE nllO00lO; + wire_nllOO11l_dataout <= wire_nlO11lOi_dataout WHEN niOO0000i = '1' ELSE nllO00Oi; + wire_nllOO11O_dataout <= wire_nlO11lOl_dataout WHEN niOO0000i = '1' ELSE nllO00Ol; + wire_nllOO1ii_dataout <= wire_nlO0011O_dataout WHEN niOO0000i = '1' ELSE nllO0i1O; + wire_nllOO1il_dataout <= wire_nlO0010i_dataout WHEN niOO0000i = '1' ELSE nllO0i0l; + wire_nllOO1iO_dataout <= wire_nlll0lli_q(0) WHEN niOO0000i = '1' ELSE nlO1iiOi; + wire_nllOO1li_dataout <= wire_nlll0lli_q(1) WHEN niOO0000i = '1' ELSE nlllOlll; + wire_nllOO1ll_dataout <= wire_nlll0lli_q(2) WHEN niOO0000i = '1' ELSE nlllOllO; + wire_nllOO1lO_dataout <= wire_nlll0lli_q(3) WHEN niOO0000i = '1' ELSE nlllOlOi; + wire_nllOO1Oi_dataout <= wire_nlll0lli_q(4) WHEN niOO0000i = '1' ELSE nlllOlOl; + wire_nllOO1Ol_dataout <= wire_nlll0lli_q(5) WHEN niOO0000i = '1' ELSE nlllOlOO; + wire_nllOO1OO_dataout <= wire_nlll0lli_q(6) WHEN niOO0000i = '1' ELSE nlllOO1i; + wire_nllOOi0i_dataout <= wire_nlll0lli_q(25) WHEN niOO0000i = '1' ELSE nllO110l; + wire_nllOOi0l_dataout <= wire_nlll0lli_q(26) WHEN niOO0000i = '1' ELSE nllO110O; + wire_nllOOi0O_dataout <= wire_nlll0lli_q(27) WHEN niOO0000i = '1' ELSE nllO11ii; + wire_nllOOi1i_dataout <= wire_nlll0lli_q(22) WHEN niOO0000i = '1' ELSE nllO111l; + wire_nllOOi1l_dataout <= wire_nlll0lli_q(23) WHEN niOO0000i = '1' ELSE nllO111O; + wire_nllOOi1O_dataout <= wire_nlll0lli_q(24) WHEN niOO0000i = '1' ELSE nllO110i; + wire_nllOOiii_dataout <= wire_nlll0lli_q(28) WHEN niOO0000i = '1' ELSE nllO11il; + wire_nllOOiil_dataout <= wire_nlll0lli_q(29) WHEN niOO0000i = '1' ELSE nllO11iO; + wire_nllOOiiO_dataout <= wire_nlll0lli_q(30) WHEN niOO0000i = '1' ELSE nllO11li; + wire_nllOOili_dataout <= wire_nlll0lli_q(31) WHEN niOO0000i = '1' ELSE nllO11ll; + wire_nllOOill_dataout <= wire_nlll0lli_q(32) WHEN niOO0000i = '1' ELSE nllO11lO; + wire_nllOOilO_dataout <= wire_nlll0lli_q(33) WHEN niOO0000i = '1' ELSE nllO11Oi; + wire_nllOOiOi_dataout <= wire_nlll0lli_q(34) WHEN niOO0000i = '1' ELSE nllO11Ol; + wire_nllOOiOl_dataout <= wire_nlll0lli_q(35) WHEN niOO0000i = '1' ELSE nllO11OO; + wire_nllOOiOO_dataout <= wire_nlll0lli_q(36) WHEN niOO0000i = '1' ELSE nllO101i; + wire_nllOOl0i_dataout <= wire_nlll0lli_q(40) WHEN niOO0000i = '1' ELSE nllO100l; + wire_nllOOl0l_dataout <= wire_nlll0lli_q(41) WHEN niOO0000i = '1' ELSE nllO100O; + wire_nllOOl0O_dataout <= wire_nlll0lli_q(42) WHEN niOO0000i = '1' ELSE nllO10ii; + wire_nllOOl1i_dataout <= wire_nlll0lli_q(37) WHEN niOO0000i = '1' ELSE nllO101l; + wire_nllOOl1l_dataout <= wire_nlll0lli_q(38) WHEN niOO0000i = '1' ELSE nllO101O; + wire_nllOOl1O_dataout <= wire_nlll0lli_q(39) WHEN niOO0000i = '1' ELSE nllO100i; + wire_nllOOlii_dataout <= wire_nlll0lli_q(43) WHEN niOO0000i = '1' ELSE nllO10il; + wire_nllOOlil_dataout <= wire_nlll0lli_q(44) WHEN niOO0000i = '1' ELSE nllO10iO; + wire_nllOOliO_dataout <= wire_nlll0lli_q(45) WHEN niOO0000i = '1' ELSE nllO10li; + wire_nllOOlli_dataout <= wire_nlll0lli_q(46) WHEN niOO0000i = '1' ELSE nllO10ll; + wire_nllOOlll_dataout <= wire_nlll0lli_q(47) WHEN niOO0000i = '1' ELSE nllO10lO; + wire_nllOOllO_dataout <= wire_nlll0lli_q(48) WHEN niOO0000i = '1' ELSE nllO10Oi; + wire_nllOOlOi_dataout <= wire_nlll0lli_q(49) WHEN niOO0000i = '1' ELSE nllO10Ol; + wire_nllOOlOl_dataout <= wire_nlll0lli_q(50) WHEN niOO0000i = '1' ELSE nllO10OO; + wire_nllOOlOO_dataout <= wire_nlll0lli_q(51) WHEN niOO0000i = '1' ELSE nllO1i1i; + wire_nllOOO0i_dataout <= wire_nlll0lli_q(55) WHEN niOO0000i = '1' ELSE nllO1i0l; + wire_nllOOO0l_dataout <= wire_nlll0lli_q(56) WHEN niOO0000i = '1' ELSE nllO1i0O; + wire_nllOOO0O_dataout <= wire_nlll0lli_q(57) WHEN niOO0000i = '1' ELSE nllO1iii; + wire_nllOOO1i_dataout <= wire_nlll0lli_q(52) WHEN niOO0000i = '1' ELSE nllO1i1l; + wire_nllOOO1l_dataout <= wire_nlll0lli_q(53) WHEN niOO0000i = '1' ELSE nllO1i1O; + wire_nllOOO1O_dataout <= wire_nlll0lli_q(54) WHEN niOO0000i = '1' ELSE nllO1i0i; + wire_nllOOOii_dataout <= wire_nlll0lli_q(58) WHEN niOO0000i = '1' ELSE nllO1iil; + wire_nllOOOil_dataout <= wire_nlll0lli_q(59) WHEN niOO0000i = '1' ELSE nllO1iiO; + wire_nllOOOiO_dataout <= wire_nlll0lli_q(60) WHEN niOO0000i = '1' ELSE nllO1ili; + wire_nllOOOli_dataout <= wire_nlll0lli_q(61) WHEN niOO0000i = '1' ELSE nllO1ill; + wire_nllOOOll_dataout <= wire_nlll0lli_q(62) WHEN niOO0000i = '1' ELSE nllO1ilO; + wire_nllOOOlO_dataout <= wire_nlll0lli_q(63) WHEN niOO0000i = '1' ELSE nllO1iOi; + wire_nllOOOOi_dataout <= nllO0i0l WHEN niOO0000i = '1' ELSE nllO0i0i; + wire_nllOOOOl_dataout <= wire_nlO1O0il_dataout WHEN niOO0001i = '1' ELSE wire_nlO11O1O_dataout; + wire_nllOOOOO_dataout <= wire_nlO1O0iO_dataout WHEN niOO0001i = '1' ELSE wire_nlO11O0i_dataout; + wire_nlO00000i_dataout <= niOl1110O WHEN niOiOO0OO = '1' ELSE wire_nlO00i10i_dataout; + wire_nlO00000l_dataout <= niOl1110l WHEN niOiOO0OO = '1' ELSE wire_nlO00i10l_dataout; + wire_nlO00000O_dataout <= niOl1110i WHEN niOiOO0OO = '1' ELSE wire_nlO00i10O_dataout; + wire_nlO00001i_dataout <= niOl111iO WHEN niOiOO0OO = '1' ELSE wire_nlO00i11i_dataout; + wire_nlO00001l_dataout <= niOl111il WHEN niOiOO0OO = '1' ELSE wire_nlO00i11l_dataout; + wire_nlO00001O_dataout <= niOl111ii WHEN niOiOO0OO = '1' ELSE wire_nlO00i11O_dataout; + wire_nlO0000i_dataout <= wire_nlO0i1li_dataout WHEN niOO0001O = '1' ELSE nllO1lOi; + wire_nlO0000ii_dataout <= niOl1111O WHEN niOiOO0OO = '1' ELSE wire_nlO00i1ii_dataout; + wire_nlO0000il_dataout <= niOl1111l WHEN niOiOO0OO = '1' ELSE wire_nlO00i1il_dataout; + wire_nlO0000iO_dataout <= niOl1111i WHEN niOiOO0OO = '1' ELSE wire_nlO00i1iO_dataout; + wire_nlO0000l_dataout <= wire_nlO0i1ll_dataout WHEN niOO0001O = '1' ELSE nllO1lOl; + wire_nlO0000li_dataout <= niOiOOOOO WHEN niOiOO0OO = '1' ELSE wire_nlO00i1li_dataout; + wire_nlO0000ll_dataout <= niOiOOOOl WHEN niOiOO0OO = '1' ELSE wire_nlO00i1ll_dataout; + wire_nlO0000lO_dataout <= niOiOOOOi WHEN niOiOO0OO = '1' ELSE wire_nlO00i1lO_dataout; + wire_nlO0000O_dataout <= wire_nlO0i1lO_dataout WHEN niOO0001O = '1' ELSE nllO1lOO; + wire_nlO0000Oi_dataout <= niOiOOOlO WHEN niOiOO0OO = '1' ELSE wire_nlO00i1Oi_dataout; + wire_nlO0000Ol_dataout <= niOiOOOll WHEN niOiOO0OO = '1' ELSE wire_nlO00i1Ol_dataout; + wire_nlO0000OO_dataout <= niOiOOOli WHEN niOiOO0OO = '1' ELSE wire_nlO00i1OO_dataout; + wire_nlO00010i_dataout <= wire_nlO000O0i_dataout AND NOT(niOiOO0OO); + wire_nlO00010l_dataout <= wire_nl1000i_w_lg_nlO0il00i29492w(0) WHEN niOiOO0OO = '1' ELSE wire_nlO000O0l_dataout; + wire_nlO00010O_dataout <= nlO0il00i WHEN niOiOO0OO = '1' ELSE wire_nlO000O0O_dataout; + wire_nlO00011i_dataout <= wire_nlO000O1i_dataout AND NOT(niOiOO0OO); + wire_nlO00011l_dataout <= wire_nlO000O1l_dataout AND NOT(niOiOO0OO); + wire_nlO00011O_dataout <= wire_nlO000O1O_dataout AND NOT(niOiOO0OO); + wire_nlO0001i_dataout <= wire_nlO0i1ii_dataout WHEN niOO0001O = '1' ELSE nllO1lli; + wire_nlO0001ii_dataout <= wire_nlO000Oii_dataout OR niOiOO0OO; + wire_nlO0001il_dataout <= wire_nlO000Oil_dataout OR niOiOO0OO; + wire_nlO0001iO_dataout <= wire_nlO000OiO_dataout OR niOiOO0OO; + wire_nlO0001l_dataout <= wire_nlO0i1il_dataout WHEN niOO0001O = '1' ELSE nllO1lll; + wire_nlO0001li_dataout <= wire_nlO000Oli_dataout OR niOiOO0OO; + wire_nlO0001ll_dataout <= wire_nlO000Oll_dataout OR niOiOO0OO; + wire_nlO0001lO_dataout <= wire_nlO000OlO_dataout OR niOiOO0OO; + wire_nlO0001O_dataout <= wire_nlO0i1iO_dataout WHEN niOO0001O = '1' ELSE nllO1llO; + wire_nlO0001Oi_dataout <= niOl111lO WHEN niOiOO0OO = '1' ELSE wire_nlO000OOi_dataout; + wire_nlO0001Ol_dataout <= niOl111ll WHEN niOiOO0OO = '1' ELSE wire_nlO000OOl_dataout; + wire_nlO0001OO_dataout <= niOl111li WHEN niOiOO0OO = '1' ELSE wire_nlO000OOO_dataout; + wire_nlO000i0i_dataout <= niOiOOO0O WHEN niOiOO0OO = '1' ELSE wire_nlO00i00i_dataout; + wire_nlO000i0l_dataout <= niOiOOO0l WHEN niOiOO0OO = '1' ELSE wire_nlO00i00l_dataout; + wire_nlO000i0O_dataout <= niOiOOO0i WHEN niOiOO0OO = '1' ELSE wire_nlO00i00O_dataout; + wire_nlO000i1i_dataout <= niOiOOOiO WHEN niOiOO0OO = '1' ELSE wire_nlO00i01i_dataout; + wire_nlO000i1l_dataout <= niOiOOOil WHEN niOiOO0OO = '1' ELSE wire_nlO00i01l_dataout; + wire_nlO000i1O_dataout <= niOiOOOii WHEN niOiOO0OO = '1' ELSE wire_nlO00i01O_dataout; + wire_nlO000ii_dataout <= wire_nlO0i1Oi_dataout WHEN niOO0001O = '1' ELSE nllO1O1i; + wire_nlO000iii_dataout <= wire_nlO00i0ii_dataout OR niOiOO0Ol; + wire_nlO000iil_dataout <= wire_nlO00i0il_dataout OR niOiOO0Ol; + wire_nlO000iiO_dataout <= wire_nlO00i0iO_dataout AND NOT(niOiOO0Ol); + wire_nlO000il_dataout <= wire_nlO0i1Ol_dataout WHEN niOO0001O = '1' ELSE nllO1O1l; + wire_nlO000ili_dataout <= wire_nlO00i0iO_dataout OR niOiOO0Ol; + wire_nlO000ill_dataout <= wire_nlO00i0li_dataout OR niOiOO0Ol; + wire_nlO000ilO_dataout <= wire_nlO00i0ll_dataout OR niOiOO0Ol; + wire_nlO000iO_dataout <= wire_nlO0i1OO_dataout WHEN niOO0001O = '1' ELSE nllO1O1O; + wire_nlO000iOi_dataout <= wire_nlO00i0lO_dataout OR niOiOO0Ol; + wire_nlO000iOl_dataout <= wire_nlO00i0Oi_dataout AND NOT(niOiOO0Ol); + wire_nlO000iOO_dataout <= wire_nlO00i0Ol_dataout OR niOiOO0Ol; + wire_nlO000l0i_dataout <= wire_nlO00ii1O_dataout OR niOiOO0Ol; + wire_nlO000l0l_dataout <= wire_nlO00ii0i_dataout OR niOiOO0Ol; + wire_nlO000l0O_dataout <= wire_nlO00ii0l_dataout OR niOiOO0Ol; + wire_nlO000l1i_dataout <= wire_nlO00i0OO_dataout OR niOiOO0Ol; + wire_nlO000l1l_dataout <= wire_nlO00ii1i_dataout OR niOiOO0Ol; + wire_nlO000l1O_dataout <= wire_nlO00ii1l_dataout OR niOiOO0Ol; + wire_nlO000li_dataout <= wire_nlO0i01i_dataout WHEN niOO0001O = '1' ELSE nllO1O0i; + wire_nlO000lii_dataout <= wire_nlO00ii0O_dataout AND NOT(niOiOO0Ol); + wire_nlO000lil_dataout <= wire_nlO00iiii_dataout OR niOiOO0Ol; + wire_nlO000liO_dataout <= wire_nlO00iiil_dataout OR niOiOO0Ol; + wire_nlO000ll_dataout <= wire_nlO0i01l_dataout WHEN niOO0001O = '1' ELSE nllO1O0l; + wire_nlO000lli_dataout <= wire_nlO00iiiO_dataout OR niOiOO0Ol; + wire_nlO000lll_dataout <= wire_nlO00iili_dataout OR niOiOO0Ol; + wire_nlO000llO_dataout <= wire_nlO00iill_dataout OR niOiOO0Ol; + wire_nlO000lO_dataout <= wire_nlO0i01O_dataout WHEN niOO0001O = '1' ELSE nllO1O0O; + wire_nlO000lOi_dataout <= wire_nlO00iilO_dataout OR niOiOO0Ol; + wire_nlO000lOl_dataout <= wire_nlO00iiOi_dataout OR niOiOO0Ol; + wire_nlO000lOO_dataout <= wire_nlO00iiOl_dataout AND NOT(niOiOO0Ol); + wire_nlO000O0i_dataout <= wire_nlO00il1O_dataout OR niOiOO0Ol; + wire_nlO000O0l_dataout <= wire_nl1000i_w_lg_nlO0il00i29492w(0) WHEN niOiOO0Ol = '1' ELSE wire_nlO00il0i_dataout; + wire_nlO000O0O_dataout <= nlO0il00i WHEN niOiOO0Ol = '1' ELSE wire_nlO00il0l_dataout; + wire_nlO000O1i_dataout <= wire_nlO00iiOO_dataout OR niOiOO0Ol; + wire_nlO000O1l_dataout <= wire_nlO00il1i_dataout OR niOiOO0Ol; + wire_nlO000O1O_dataout <= wire_nlO00il1l_dataout OR niOiOO0Ol; + wire_nlO000Oi_dataout <= wire_nlO0i00i_dataout WHEN niOO0001O = '1' ELSE nllO1Oii; + wire_nlO000Oii_dataout <= wire_nlO00il0O_dataout OR niOiOO0Ol; + wire_nlO000Oil_dataout <= wire_nlO00ilii_dataout OR niOiOO0Ol; + wire_nlO000OiO_dataout <= wire_nlO00ilil_dataout OR niOiOO0Ol; + wire_nlO000Ol_dataout <= wire_nlO0i00l_dataout WHEN niOO0001O = '1' ELSE nllO1Oil; + wire_nlO000Oli_dataout <= wire_nlO00iliO_dataout OR niOiOO0Ol; + wire_nlO000Oll_dataout <= wire_nlO00illi_dataout OR niOiOO0Ol; + wire_nlO000OlO_dataout <= wire_nlO00illl_dataout OR niOiOO0Ol; + wire_nlO000OO_dataout <= wire_nlO0i00O_dataout WHEN niOO0001O = '1' ELSE nllO1OiO; + wire_nlO000OOi_dataout <= niOl111lO WHEN niOiOO0Ol = '1' ELSE wire_nlO00illO_dataout; + wire_nlO000OOl_dataout <= niOl111ll WHEN niOiOO0Ol = '1' ELSE wire_nlO00ilOi_dataout; + wire_nlO000OOO_dataout <= niOl111li WHEN niOiOO0Ol = '1' ELSE wire_nlO00ilOl_dataout; + wire_nlO00100i_dataout <= wire_nl1000i_w_lg_nlO1lOl0O29432w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO00010i_dataout; + wire_nlO00100l_dataout <= wire_nl1000i_w_lg_nlO1lOO0O29431w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO00010l_dataout; + wire_nlO00100O_dataout <= wire_nl1000i_w_lg_nlO1lOO0l29430w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO00010O_dataout; + wire_nlO00101i_dataout <= wire_nl1000i_w_lg_nlO1lOliO29435w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO00011i_dataout; + wire_nlO00101l_dataout <= wire_nl1000i_w_lg_nlO1lOlil29434w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO00011l_dataout; + wire_nlO00101O_dataout <= wire_nl1000i_w_lg_nlO1lOlii29433w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO00011O_dataout; + wire_nlO0010i_dataout <= wire_nlO00OiO_dataout AND NOT(niOO000Oi); + wire_nlO0010ii_dataout <= wire_nl1000i_w_lg_nlO1lOO0i29429w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO0001ii_dataout; + wire_nlO0010il_dataout <= wire_nl1000i_w_lg_nlO1lOO1O29428w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO0001il_dataout; + wire_nlO0010iO_dataout <= wire_nl1000i_w_lg_nlO1lOO1l29427w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO0001iO_dataout; + wire_nlO0010l_dataout <= wire_nlO00Oll_dataout WHEN niOO0001O = '1' ELSE nllO1iOl; + wire_nlO0010li_dataout <= wire_nl1000i_w_lg_nlO1lOO1i29426w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO0001li_dataout; + wire_nlO0010ll_dataout <= wire_nl1000i_w_lg_nlO1lOlOO29425w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO0001ll_dataout; + wire_nlO0010lO_dataout <= wire_nl1000i_w_lg_nlO1lOlOl29424w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO0001lO_dataout; + wire_nlO0010O_dataout <= wire_nlO00OlO_dataout WHEN niOO0001O = '1' ELSE nllO1iOO; + wire_nlO0010Oi_dataout <= nlO0ili1l WHEN niOiOOi1i = '1' ELSE wire_nlO0001Oi_dataout; + wire_nlO0010Ol_dataout <= nlO0ili1O WHEN niOiOOi1i = '1' ELSE wire_nlO0001Ol_dataout; + wire_nlO0010OO_dataout <= nlO0ili0i WHEN niOiOOi1i = '1' ELSE wire_nlO0001OO_dataout; + wire_nlO00110i_dataout <= wire_nl1000i_w_lg_nlO1lOl0l29447w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001O0i_dataout; + wire_nlO00110l_dataout <= wire_nl1000i_w_lg_nlO1lOl0i29446w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001O0l_dataout; + wire_nlO00110O_dataout <= wire_nl1000i_w_lg_nlO1lOl1O29445w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001O0O_dataout; + wire_nlO00111i_dataout <= wire_nl1000i_w_lg_nlO1lOiii29450w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001O1i_dataout; + wire_nlO00111l_dataout <= wire_nl1000i_w_lg_nlO1lOi0O29449w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001O1l_dataout; + wire_nlO00111O_dataout <= wire_nl1000i_w_lg_nlO1O0l1i29448w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001O1O_dataout; + wire_nlO0011i_dataout <= nllO0i1i WHEN niOO000Oi = '1' ELSE wire_nlO00Oii_dataout; + wire_nlO0011ii_dataout <= wire_nl1000i_w_lg_nlO1lOl1l29444w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001Oii_dataout; + wire_nlO0011il_dataout <= wire_nl1000i_w_lg_nlO1lOl1i29443w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001Oil_dataout; + wire_nlO0011iO_dataout <= wire_nl1000i_w_lg_nlO1lOiOO29442w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001OiO_dataout; + wire_nlO0011l_dataout <= nllO0i1l WHEN niOO000Oi = '1' ELSE wire_nlO00Oil_dataout; + wire_nlO0011li_dataout <= wire_nl1000i_w_lg_nlO1lOiOl29441w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001Oli_dataout; + wire_nlO0011ll_dataout <= wire_nl1000i_w_lg_nlO1lOiOi29440w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001Oll_dataout; + wire_nlO0011lO_dataout <= wire_nl1000i_w_lg_nlO1lOlOi29439w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001OlO_dataout; + wire_nlO0011O_dataout <= nllO0i1O WHEN niOO000Oi = '1' ELSE wire_nlO00Oli_dataout; + wire_nlO0011Oi_dataout <= wire_nl1000i_w_lg_nlO1lOllO29438w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001OOi_dataout; + wire_nlO0011Ol_dataout <= wire_nl1000i_w_lg_nlO1lOlll29437w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001OOl_dataout; + wire_nlO0011OO_dataout <= wire_nl1000i_w_lg_nlO1lOlli29436w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001OOO_dataout; + wire_nlO001i0i_dataout <= nlO0iliil WHEN niOiOOi1i = '1' ELSE wire_nlO00000i_dataout; + wire_nlO001i0l_dataout <= nlO0iliiO WHEN niOiOOi1i = '1' ELSE wire_nlO00000l_dataout; + wire_nlO001i0O_dataout <= nlO0ilili WHEN niOiOOi1i = '1' ELSE wire_nlO00000O_dataout; + wire_nlO001i1i_dataout <= nlO0ili0l WHEN niOiOOi1i = '1' ELSE wire_nlO00001i_dataout; + wire_nlO001i1l_dataout <= nlO0ili0O WHEN niOiOOi1i = '1' ELSE wire_nlO00001l_dataout; + wire_nlO001i1O_dataout <= nlO0iliii WHEN niOiOOi1i = '1' ELSE wire_nlO00001O_dataout; + wire_nlO001ii_dataout <= wire_nlO00OOi_dataout WHEN niOO0001O = '1' ELSE nllO1l1i; + wire_nlO001iii_dataout <= nlO0ilill WHEN niOiOOi1i = '1' ELSE wire_nlO0000ii_dataout; + wire_nlO001iil_dataout <= nlO0ililO WHEN niOiOOi1i = '1' ELSE wire_nlO0000il_dataout; + wire_nlO001iiO_dataout <= nlO0iliOi WHEN niOiOOi1i = '1' ELSE wire_nlO0000iO_dataout; + wire_nlO001il_dataout <= wire_nlO00OOl_dataout WHEN niOO0001O = '1' ELSE nllO1l1l; + wire_nlO001ili_dataout <= nlO0iliOl WHEN niOiOOi1i = '1' ELSE wire_nlO0000li_dataout; + wire_nlO001ill_dataout <= nlO0iliOO WHEN niOiOOi1i = '1' ELSE wire_nlO0000ll_dataout; + wire_nlO001ilO_dataout <= nlO0ill1i WHEN niOiOOi1i = '1' ELSE wire_nlO0000lO_dataout; + wire_nlO001iO_dataout <= wire_nlO00OOO_dataout WHEN niOO0001O = '1' ELSE nllO1l1O; + wire_nlO001iOi_dataout <= nlO0ill1l WHEN niOiOOi1i = '1' ELSE wire_nlO0000Oi_dataout; + wire_nlO001iOl_dataout <= nlO0ill1O WHEN niOiOOi1i = '1' ELSE wire_nlO0000Ol_dataout; + wire_nlO001iOO_dataout <= nlO0ill0i WHEN niOiOOi1i = '1' ELSE wire_nlO0000OO_dataout; + wire_nlO001l0i_dataout <= nlO0illil WHEN niOiOOi1i = '1' ELSE wire_nlO000i0i_dataout; + wire_nlO001l0l_dataout <= nlO0illiO WHEN niOiOOi1i = '1' ELSE wire_nlO000i0l_dataout; + wire_nlO001l0O_dataout <= nlO0illli WHEN niOiOOi1i = '1' ELSE wire_nlO000i0O_dataout; + wire_nlO001l1i_dataout <= nlO0ill0l WHEN niOiOOi1i = '1' ELSE wire_nlO000i1i_dataout; + wire_nlO001l1l_dataout <= nlO0ill0O WHEN niOiOOi1i = '1' ELSE wire_nlO000i1l_dataout; + wire_nlO001l1O_dataout <= nlO0illii WHEN niOiOOi1i = '1' ELSE wire_nlO000i1O_dataout; + wire_nlO001li_dataout <= wire_nlO0i11i_dataout WHEN niOO0001O = '1' ELSE nllO1l0i; + wire_nlO001lii_dataout <= wire_nlO000iii_dataout AND NOT(niOiOO0OO); + wire_nlO001lil_dataout <= wire_nlO000iil_dataout AND NOT(niOiOO0OO); + wire_nlO001liO_dataout <= wire_nlO000iiO_dataout AND NOT(niOiOO0OO); + wire_nlO001ll_dataout <= wire_nlO0i11l_dataout WHEN niOO0001O = '1' ELSE nllO1l0l; + wire_nlO001lli_dataout <= wire_nlO000ili_dataout AND NOT(niOiOO0OO); + wire_nlO001lll_dataout <= wire_nlO000ill_dataout AND NOT(niOiOO0OO); + wire_nlO001llO_dataout <= wire_nlO000ilO_dataout AND NOT(niOiOO0OO); + wire_nlO001lO_dataout <= wire_nlO0i11O_dataout WHEN niOO0001O = '1' ELSE nllO1l0O; + wire_nlO001lOi_dataout <= wire_nlO000iOi_dataout AND NOT(niOiOO0OO); + wire_nlO001lOl_dataout <= wire_nlO000iOl_dataout AND NOT(niOiOO0OO); + wire_nlO001lOO_dataout <= wire_nlO000iOO_dataout AND NOT(niOiOO0OO); + wire_nlO001O0i_dataout <= wire_nlO000l0i_dataout AND NOT(niOiOO0OO); + wire_nlO001O0l_dataout <= wire_nlO000l0l_dataout AND NOT(niOiOO0OO); + wire_nlO001O0O_dataout <= wire_nlO000l0O_dataout AND NOT(niOiOO0OO); + wire_nlO001O1i_dataout <= wire_nlO000l1i_dataout AND NOT(niOiOO0OO); + wire_nlO001O1l_dataout <= wire_nlO000l1l_dataout AND NOT(niOiOO0OO); + wire_nlO001O1O_dataout <= wire_nlO000l1O_dataout AND NOT(niOiOO0OO); + wire_nlO001Oi_dataout <= wire_nlO0i10i_dataout WHEN niOO0001O = '1' ELSE nllO1lii; + wire_nlO001Oii_dataout <= wire_nlO000lii_dataout AND NOT(niOiOO0OO); + wire_nlO001Oil_dataout <= wire_nlO000lil_dataout AND NOT(niOiOO0OO); + wire_nlO001OiO_dataout <= wire_nlO000liO_dataout AND NOT(niOiOO0OO); + wire_nlO001Ol_dataout <= wire_nlO0i10l_dataout WHEN niOO0001O = '1' ELSE nllO1lil; + wire_nlO001Oli_dataout <= wire_nlO000lli_dataout AND NOT(niOiOO0OO); + wire_nlO001Oll_dataout <= wire_nlO000lll_dataout AND NOT(niOiOO0OO); + wire_nlO001OlO_dataout <= wire_nlO000llO_dataout AND NOT(niOiOO0OO); + wire_nlO001OO_dataout <= wire_nlO0i10O_dataout WHEN niOO0001O = '1' ELSE nllO1liO; + wire_nlO001OOi_dataout <= wire_nlO000lOi_dataout AND NOT(niOiOO0OO); + wire_nlO001OOl_dataout <= wire_nlO000lOl_dataout AND NOT(niOiOO0OO); + wire_nlO001OOO_dataout <= wire_nlO000lOO_dataout AND NOT(niOiOO0OO); + wire_nlO00i00i_dataout <= niOiOOO0O WHEN niOiOO0Ol = '1' ELSE wire_nlO00l11O_dataout; + wire_nlO00i00l_dataout <= niOiOOO0l WHEN niOiOO0Ol = '1' ELSE wire_nlO00l10i_dataout; + wire_nlO00i00O_dataout <= niOiOOO0i WHEN niOiOO0Ol = '1' ELSE wire_nlO00l10l_dataout; + wire_nlO00i01i_dataout <= niOiOOOiO WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOOO_dataout; + wire_nlO00i01l_dataout <= niOiOOOil WHEN niOiOO0Ol = '1' ELSE wire_nlO00l11i_dataout; + wire_nlO00i01O_dataout <= niOiOOOii WHEN niOiOO0Ol = '1' ELSE wire_nlO00l11l_dataout; + wire_nlO00i0i_dataout <= wire_nlO0i0li_dataout WHEN niOO0001O = '1' ELSE nllO1OOi; + wire_nlO00i0ii_dataout <= wire_nl1000i_w_lg_nlO0il00i29492w(0) WHEN nlO00lOiO = '1' ELSE wire_nlO00l10O_dataout; + wire_nlO00i0il_dataout <= nlO0il00i WHEN nlO00lOiO = '1' ELSE wire_nlO00l1ii_dataout; + wire_nlO00i0iO_dataout <= niOiOO0Oi OR nlO00lOiO; + wire_nlO00i0l_dataout <= wire_nlO0i0ll_dataout WHEN niOO0001O = '1' ELSE nllO1OOl; + wire_nlO00i0li_dataout <= niOl111lO WHEN nlO00lOiO = '1' ELSE wire_nlO00l1il_dataout; + wire_nlO00i0ll_dataout <= niOl111ll WHEN nlO00lOiO = '1' ELSE wire_nlO00l1iO_dataout; + wire_nlO00i0lO_dataout <= niOl111li WHEN nlO00lOiO = '1' ELSE wire_nlO00l1li_dataout; + wire_nlO00i0O_dataout <= wire_nlO0i0lO_dataout WHEN niOO0001O = '1' ELSE nllO1OOO; + wire_nlO00i0Oi_dataout <= niOl111iO WHEN nlO00lOiO = '1' ELSE wire_nlO00l1ll_dataout; + wire_nlO00i0Ol_dataout <= niOl111il WHEN nlO00lOiO = '1' ELSE wire_nlO00l1lO_dataout; + wire_nlO00i0OO_dataout <= niOl111ii WHEN nlO00lOiO = '1' ELSE wire_nlO00l1Oi_dataout; + wire_nlO00i10i_dataout <= niOl1110O WHEN niOiOO0Ol = '1' ELSE wire_nlO00iO1O_dataout; + wire_nlO00i10l_dataout <= niOl1110l WHEN niOiOO0Ol = '1' ELSE wire_nlO00iO0i_dataout; + wire_nlO00i10O_dataout <= niOl1110i WHEN niOiOO0Ol = '1' ELSE wire_nlO00iO0l_dataout; + wire_nlO00i11i_dataout <= niOl111iO WHEN niOiOO0Ol = '1' ELSE wire_nlO00ilOO_dataout; + wire_nlO00i11l_dataout <= niOl111il WHEN niOiOO0Ol = '1' ELSE wire_nlO00iO1i_dataout; + wire_nlO00i11O_dataout <= niOl111ii WHEN niOiOO0Ol = '1' ELSE wire_nlO00iO1l_dataout; + wire_nlO00i1i_dataout <= wire_nlO0i0ii_dataout WHEN niOO0001O = '1' ELSE nllO1Oli; + wire_nlO00i1ii_dataout <= niOl1111O WHEN niOiOO0Ol = '1' ELSE wire_nlO00iO0O_dataout; + wire_nlO00i1il_dataout <= niOl1111l WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOii_dataout; + wire_nlO00i1iO_dataout <= niOl1111i WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOil_dataout; + wire_nlO00i1l_dataout <= wire_nlO0i0il_dataout WHEN niOO0001O = '1' ELSE nllO1Oll; + wire_nlO00i1li_dataout <= niOiOOOOO WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOiO_dataout; + wire_nlO00i1ll_dataout <= niOiOOOOl WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOli_dataout; + wire_nlO00i1lO_dataout <= niOiOOOOi WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOll_dataout; + wire_nlO00i1O_dataout <= wire_nlO0i0iO_dataout WHEN niOO0001O = '1' ELSE nllO1OlO; + wire_nlO00i1Oi_dataout <= niOiOOOlO WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOlO_dataout; + wire_nlO00i1Ol_dataout <= niOiOOOll WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOOi_dataout; + wire_nlO00i1OO_dataout <= niOiOOOli WHEN niOiOO0Ol = '1' ELSE wire_nlO00iOOl_dataout; + wire_nlO00ii0i_dataout <= niOl1111O WHEN nlO00lOiO = '1' ELSE wire_nlO00l01l_dataout; + wire_nlO00ii0l_dataout <= niOl1111l WHEN nlO00lOiO = '1' ELSE wire_nlO00l01O_dataout; + wire_nlO00ii0O_dataout <= niOl1111i WHEN nlO00lOiO = '1' ELSE wire_nlO00l00i_dataout; + wire_nlO00ii1i_dataout <= niOl1110O WHEN nlO00lOiO = '1' ELSE wire_nlO00l1Ol_dataout; + wire_nlO00ii1l_dataout <= niOl1110l WHEN nlO00lOiO = '1' ELSE wire_nlO00l1OO_dataout; + wire_nlO00ii1O_dataout <= niOl1110i WHEN nlO00lOiO = '1' ELSE wire_nlO00l01i_dataout; + wire_nlO00iii_dataout <= wire_nlO0i0Oi_dataout WHEN niOO0001O = '1' ELSE nllO011i; + wire_nlO00iiii_dataout <= niOiOOOOO WHEN nlO00lOiO = '1' ELSE wire_nlO00l00l_dataout; + wire_nlO00iiil_dataout <= niOiOOOOl WHEN nlO00lOiO = '1' ELSE wire_nlO00l00O_dataout; + wire_nlO00iiiO_dataout <= niOiOOOOi WHEN nlO00lOiO = '1' ELSE wire_nlO00l0ii_dataout; + wire_nlO00iil_dataout <= wire_nlO0i0Ol_dataout WHEN niOO0001O = '1' ELSE nllO011l; + wire_nlO00iili_dataout <= niOiOOOlO WHEN nlO00lOiO = '1' ELSE wire_nlO00l0il_dataout; + wire_nlO00iill_dataout <= niOiOOOll WHEN nlO00lOiO = '1' ELSE wire_nlO00l0iO_dataout; + wire_nlO00iilO_dataout <= niOiOOOli WHEN nlO00lOiO = '1' ELSE wire_nlO00l0li_dataout; + wire_nlO00iiO_dataout <= wire_nlO0i0OO_dataout WHEN niOO0001O = '1' ELSE nllO011O; + wire_nlO00iiOi_dataout <= niOiOOOiO WHEN nlO00lOiO = '1' ELSE wire_nlO00l0ll_dataout; + wire_nlO00iiOl_dataout <= niOiOOOil WHEN nlO00lOiO = '1' ELSE wire_nlO00l0lO_dataout; + wire_nlO00iiOO_dataout <= niOiOOOii WHEN nlO00lOiO = '1' ELSE wire_nlO00l0Oi_dataout; + wire_nlO00il0i_dataout <= niOiOOO1O WHEN nlO00lOiO = '1' ELSE wire_nlO00li1l_dataout; + wire_nlO00il0l_dataout <= niOiOOO1l WHEN nlO00lOiO = '1' ELSE wire_nlO00li1O_dataout; + wire_nlO00il0O_dataout <= niOiOOO1i WHEN nlO00lOiO = '1' ELSE wire_nlO00li0i_dataout; + wire_nlO00il1i_dataout <= niOiOOO0O WHEN nlO00lOiO = '1' ELSE wire_nlO00l0Ol_dataout; + wire_nlO00il1l_dataout <= niOiOOO0l WHEN nlO00lOiO = '1' ELSE wire_nlO00l0OO_dataout; + wire_nlO00il1O_dataout <= niOiOOO0i WHEN nlO00lOiO = '1' ELSE wire_nlO00li1i_dataout; + wire_nlO00ili_dataout <= wire_nlO0ii1i_dataout WHEN niOO0001O = '1' ELSE nllO010i; + wire_nlO00ilii_dataout <= niOiOOlOO WHEN nlO00lOiO = '1' ELSE wire_nlO00li0l_dataout; + wire_nlO00ilil_dataout <= niOiOOlOl WHEN nlO00lOiO = '1' ELSE wire_nlO00li0O_dataout; + wire_nlO00iliO_dataout <= niOiOOlOi WHEN nlO00lOiO = '1' ELSE wire_nlO00liii_dataout; + wire_nlO00ill_dataout <= wire_nlO0ii1l_dataout WHEN niOO0001O = '1' ELSE nllO010l; + wire_nlO00illi_dataout <= niOiOOllO WHEN nlO00lOiO = '1' ELSE wire_nlO00liil_dataout; + wire_nlO00illl_dataout <= niOiOOlll WHEN nlO00lOiO = '1' ELSE wire_nlO00liiO_dataout; + wire_nlO00illO_dataout <= nlO0ili1l WHEN nlO00lOiO = '1' ELSE wire_nlO00lili_dataout; + wire_nlO00ilO_dataout <= wire_nlO0ii1O_dataout WHEN niOO0001O = '1' ELSE nllO010O; + wire_nlO00ilOi_dataout <= nlO0ili1O WHEN nlO00lOiO = '1' ELSE wire_nlO00lill_dataout; + wire_nlO00ilOl_dataout <= nlO0ili0i WHEN nlO00lOiO = '1' ELSE wire_nlO00lilO_dataout; + wire_nlO00ilOO_dataout <= nlO0ili0l WHEN nlO00lOiO = '1' ELSE wire_nlO00liOi_dataout; + wire_nlO00iO0i_dataout <= nlO0iliiO WHEN nlO00lOiO = '1' ELSE wire_nlO00ll1l_dataout; + wire_nlO00iO0l_dataout <= nlO0ilili WHEN nlO00lOiO = '1' ELSE wire_nlO00ll1O_dataout; + wire_nlO00iO0O_dataout <= nlO0ilill WHEN nlO00lOiO = '1' ELSE wire_nlO00ll0i_dataout; + wire_nlO00iO1i_dataout <= nlO0ili0O WHEN nlO00lOiO = '1' ELSE wire_nlO00liOl_dataout; + wire_nlO00iO1l_dataout <= nlO0iliii WHEN nlO00lOiO = '1' ELSE wire_nlO00liOO_dataout; + wire_nlO00iO1O_dataout <= nlO0iliil WHEN nlO00lOiO = '1' ELSE wire_nlO00ll1i_dataout; + wire_nlO00iOi_dataout <= wire_nlO0ii0i_dataout WHEN niOO0001O = '1' ELSE nllO01ii; + wire_nlO00iOii_dataout <= nlO0ililO WHEN nlO00lOiO = '1' ELSE wire_nlO00ll0l_dataout; + wire_nlO00iOil_dataout <= nlO0iliOi WHEN nlO00lOiO = '1' ELSE wire_nlO00ll0O_dataout; + wire_nlO00iOiO_dataout <= nlO0iliOl WHEN nlO00lOiO = '1' ELSE wire_nlO00llii_dataout; + wire_nlO00iOl_dataout <= wire_nlO0ii0l_dataout WHEN niOO0001O = '1' ELSE nllO01il; + wire_nlO00iOli_dataout <= nlO0iliOO WHEN nlO00lOiO = '1' ELSE wire_nlO00llil_dataout; + wire_nlO00iOll_dataout <= nlO0ill1i WHEN nlO00lOiO = '1' ELSE wire_nlO00lliO_dataout; + wire_nlO00iOlO_dataout <= nlO0ill1l WHEN nlO00lOiO = '1' ELSE wire_nlO00llli_dataout; + wire_nlO00iOO_dataout <= wire_nlO0ii0O_dataout WHEN niOO0001O = '1' ELSE nllO01iO; + wire_nlO00iOOi_dataout <= nlO0ill1O WHEN nlO00lOiO = '1' ELSE wire_nlO00llll_dataout; + wire_nlO00iOOl_dataout <= nlO0ill0i WHEN nlO00lOiO = '1' ELSE wire_nlO00lllO_dataout; + wire_nlO00iOOO_dataout <= nlO0ill0l WHEN nlO00lOiO = '1' ELSE wire_nlO00llOi_dataout; + wire_nlO00l00i_dataout <= niOl1111i AND niOiOO0Oi; + wire_nlO00l00l_dataout <= niOiOOOOO AND niOiOO0Oi; + wire_nlO00l00O_dataout <= niOiOOOOl AND niOiOO0Oi; + wire_nlO00l01i_dataout <= niOl1110i AND niOiOO0Oi; + wire_nlO00l01l_dataout <= niOl1111O AND niOiOO0Oi; + wire_nlO00l01O_dataout <= niOl1111l AND niOiOO0Oi; + wire_nlO00l0i_dataout <= wire_nlO0iili_dataout WHEN niOO0001O = '1' ELSE nllO01Oi; + wire_nlO00l0ii_dataout <= niOiOOOOi AND niOiOO0Oi; + wire_nlO00l0il_dataout <= niOiOOOlO AND niOiOO0Oi; + wire_nlO00l0iO_dataout <= niOiOOOll AND niOiOO0Oi; + wire_nlO00l0l_dataout <= wire_nlO0iill_dataout WHEN niOO0001O = '1' ELSE nllO01Ol; + wire_nlO00l0li_dataout <= niOiOOOli AND niOiOO0Oi; + wire_nlO00l0ll_dataout <= niOiOOOiO AND niOiOO0Oi; + wire_nlO00l0lO_dataout <= niOiOOOil AND niOiOO0Oi; + wire_nlO00l0O_dataout <= wire_nlO0iilO_dataout WHEN niOO0001O = '1' ELSE nllO01OO; + wire_nlO00l0Oi_dataout <= niOiOOOii AND niOiOO0Oi; + wire_nlO00l0Ol_dataout <= niOiOOO0O AND niOiOO0Oi; + wire_nlO00l0OO_dataout <= niOiOOO0l AND niOiOO0Oi; + wire_nlO00l10i_dataout <= nlO0illiO WHEN nlO00lOiO = '1' ELSE wire_nlO00lO1l_dataout; + wire_nlO00l10l_dataout <= nlO0illli WHEN nlO00lOiO = '1' ELSE wire_nlO00lO1O_dataout; + wire_nlO00l10O_dataout <= wire_nl1000i_w_lg_nlO0il00i29492w(0) AND niOiOO0Oi; + wire_nlO00l11i_dataout <= nlO0ill0O WHEN nlO00lOiO = '1' ELSE wire_nlO00llOl_dataout; + wire_nlO00l11l_dataout <= nlO0illii WHEN nlO00lOiO = '1' ELSE wire_nlO00llOO_dataout; + wire_nlO00l11O_dataout <= nlO0illil WHEN nlO00lOiO = '1' ELSE wire_nlO00lO1i_dataout; + wire_nlO00l1i_dataout <= wire_nlO0iiii_dataout WHEN niOO0001O = '1' ELSE nllO01li; + wire_nlO00l1ii_dataout <= nlO0il00i AND niOiOO0Oi; + wire_nlO00l1il_dataout <= niOl111lO AND niOiOO0Oi; + wire_nlO00l1iO_dataout <= niOl111ll AND niOiOO0Oi; + wire_nlO00l1l_dataout <= wire_nlO0iiil_dataout WHEN niOO0001O = '1' ELSE nllO01ll; + wire_nlO00l1li_dataout <= niOl111li AND niOiOO0Oi; + wire_nlO00l1ll_dataout <= niOl111iO AND niOiOO0Oi; + wire_nlO00l1lO_dataout <= niOl111il AND niOiOO0Oi; + wire_nlO00l1O_dataout <= wire_nlO0iiiO_dataout WHEN niOO0001O = '1' ELSE nllO01lO; + wire_nlO00l1Oi_dataout <= niOl111ii AND niOiOO0Oi; + wire_nlO00l1Ol_dataout <= niOl1110O AND niOiOO0Oi; + wire_nlO00l1OO_dataout <= niOl1110l AND niOiOO0Oi; + wire_nlO00li0i_dataout <= niOiOOO1i AND niOiOO0Oi; + wire_nlO00li0l_dataout <= niOiOOlOO AND niOiOO0Oi; + wire_nlO00li0O_dataout <= niOiOOlOl AND niOiOO0Oi; + wire_nlO00li1i_dataout <= niOiOOO0i AND niOiOO0Oi; + wire_nlO00li1l_dataout <= niOiOOO1O AND niOiOO0Oi; + wire_nlO00li1O_dataout <= niOiOOO1l AND niOiOO0Oi; + wire_nlO00lii_dataout <= wire_nlO0iiOi_dataout WHEN niOO0001O = '1' ELSE nllO001i; + wire_nlO00liii_dataout <= niOiOOlOi AND niOiOO0Oi; + wire_nlO00liil_dataout <= niOiOOllO AND niOiOO0Oi; + wire_nlO00liiO_dataout <= niOiOOlll AND niOiOO0Oi; + wire_nlO00lil_dataout <= wire_nlO0iiOl_dataout WHEN niOO0001O = '1' ELSE nllO001l; + wire_nlO00lili_dataout <= wire_nl1000i_w_lg_nlO1lOilO29455w(0) AND niOiOO0Oi; + wire_nlO00lill_dataout <= wire_nl1000i_w_lg_nlO1lOill29454w(0) AND niOiOO0Oi; + wire_nlO00lilO_dataout <= wire_nl1000i_w_lg_nlO1lOili29453w(0) AND niOiOO0Oi; + wire_nlO00liO_dataout <= wire_nlO0iiOO_dataout WHEN niOO0001O = '1' ELSE nllO001O; + wire_nlO00liOi_dataout <= wire_nl1000i_w_lg_nlO1lOiiO29452w(0) AND niOiOO0Oi; + wire_nlO00liOl_dataout <= wire_nl1000i_w_lg_nlO1lOiil29451w(0) AND niOiOO0Oi; + wire_nlO00liOO_dataout <= wire_nl1000i_w_lg_nlO1lOiii29450w(0) AND niOiOO0Oi; + wire_nlO00ll0i_dataout <= wire_nl1000i_w_lg_nlO1lOl0i29446w(0) AND niOiOO0Oi; + wire_nlO00ll0l_dataout <= wire_nl1000i_w_lg_nlO1lOl1O29445w(0) AND niOiOO0Oi; + wire_nlO00ll0O_dataout <= wire_nl1000i_w_lg_nlO1lOl1l29444w(0) AND niOiOO0Oi; + wire_nlO00ll1i_dataout <= wire_nl1000i_w_lg_nlO1lOi0O29449w(0) AND niOiOO0Oi; + wire_nlO00ll1l_dataout <= wire_nl1000i_w_lg_nlO1O0l1i29448w(0) AND niOiOO0Oi; + wire_nlO00ll1O_dataout <= wire_nl1000i_w_lg_nlO1lOl0l29447w(0) AND niOiOO0Oi; + wire_nlO00lli_dataout <= wire_nlO0il1i_dataout WHEN niOO0001O = '1' ELSE nllO000i; + wire_nlO00llii_dataout <= wire_nl1000i_w_lg_nlO1lOl1i29443w(0) AND niOiOO0Oi; + wire_nlO00llil_dataout <= wire_nl1000i_w_lg_nlO1lOiOO29442w(0) AND niOiOO0Oi; + wire_nlO00lliO_dataout <= wire_nl1000i_w_lg_nlO1lOiOl29441w(0) AND niOiOO0Oi; + wire_nlO00lll_dataout <= wire_nlO0il1l_dataout WHEN niOO0001O = '1' ELSE nllO000l; + wire_nlO00llli_dataout <= wire_nl1000i_w_lg_nlO1lOiOi29440w(0) AND niOiOO0Oi; + wire_nlO00llll_dataout <= wire_nl1000i_w_lg_nlO1lOlOi29439w(0) AND niOiOO0Oi; + wire_nlO00lllO_dataout <= wire_nl1000i_w_lg_nlO1lOllO29438w(0) AND niOiOO0Oi; + wire_nlO00llO_dataout <= wire_nlO0il1O_dataout WHEN niOO0001O = '1' ELSE nllO000O; + wire_nlO00llOi_dataout <= wire_nl1000i_w_lg_nlO1lOlll29437w(0) AND niOiOO0Oi; + wire_nlO00llOl_dataout <= wire_nl1000i_w_lg_nlO1lOlli29436w(0) AND niOiOO0Oi; + wire_nlO00llOO_dataout <= wire_nl1000i_w_lg_nlO1lOliO29435w(0) AND niOiOO0Oi; + wire_nlO00lO1i_dataout <= wire_nl1000i_w_lg_nlO1lOlil29434w(0) AND niOiOO0Oi; + wire_nlO00lO1l_dataout <= wire_nl1000i_w_lg_nlO1lOlii29433w(0) AND niOiOO0Oi; + wire_nlO00lO1O_dataout <= wire_nl1000i_w_lg_nlO1lOl0O29432w(0) AND niOiOO0Oi; + wire_nlO00lOi_dataout <= wire_nlO0il0i_dataout WHEN niOO0001O = '1' ELSE nllO00ii; + wire_nlO00lOl_dataout <= wire_nlO0il0l_dataout WHEN niOO0001O = '1' ELSE nllO00il; + wire_nlO00lOO_dataout <= wire_nlO0il0O_dataout WHEN niOO0001O = '1' ELSE nllO00iO; + wire_nlO00O00i_dataout <= wire_nlO00O0Ol_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00O11i; + wire_nlO00O00l_dataout <= wire_nlO00Oi1i_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00O11l; + wire_nlO00O00O_dataout <= wire_nlO00Oi1O_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol1li; + wire_nlO00O01i_dataout <= wire_nlO00O0ll_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00lOOi; + wire_nlO00O01l_dataout <= wire_nlO00O0lO_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00lOOl; + wire_nlO00O01O_dataout <= wire_nlO00O0Oi_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00lOOO; + wire_nlO00O0i_dataout <= wire_nlO0illi_dataout WHEN niOO0001O = '1' ELSE nllO00Oi; + wire_nlO00O0ii_dataout <= wire_nlO00Oi0l_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00lOiO; + wire_nlO00O0il_dataout <= wire_nlO00Oi0O_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00lOli; + wire_nlO00O0iO_dataout <= ((nlO0OlOii AND niOl1010l) AND ((NOT (((wire_nl1000i_w_lg_nlOi1OiOl29642w(0) AND wire_nl1000i_w_lg_nlOi1OiOi29643w(0)) AND wire_nl1000i_w_lg_nlOi1OilO29645w(0)) AND wire_nl1000i_w_lg_nlOi1Oill29647w(0))) OR (NOT wire_nl1000i_w_lg_w_lg_nlOi1Ol1O29650w29652w(0)))) WHEN nlO00O11l = '1' ELSE nlO00lOll; + wire_nlO00O0l_dataout <= wire_nlO0illl_dataout WHEN niOO0001O = '1' ELSE nllO00Ol; + wire_nlO00O0O_dataout <= wire_nlO0illO_dataout WHEN niOO0001O = '1' ELSE nllO00OO; + wire_nlO00O10i_dataout <= wire_nlO00O00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O10l_dataout <= wire_nlO00O0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O10O_dataout <= wire_nlO00O0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O1i_dataout <= wire_nlO0ilii_dataout WHEN niOO0001O = '1' ELSE nllO00li; + wire_nlO00O1ii_dataout <= wire_nlO00O1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O1il_dataout <= wire_nlO00O1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O1iO_dataout <= wire_nlO00O01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O1l_dataout <= wire_nlO0ilil_dataout WHEN niOO0001O = '1' ELSE nllO00ll; + wire_nlO00O1li_dataout <= wire_nlO00O01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O1ll_dataout <= wire_nlO00O01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O1lO_dataout <= wire_nlO00O00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO00O1O_dataout <= wire_nlO0iliO_dataout WHEN niOO0001O = '1' ELSE nllO00lO; + wire_nlO00O1Oi_dataout <= wire_nlO00O00l_dataout OR wire_niO01O0O_dataout; + wire_nlO00O1Ol_dataout <= wire_nlO00O0iO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00lOll; + wire_nlO00O1OO_dataout <= wire_nlO00O0li_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00lOlO; + wire_nlO00Oii_dataout <= wire_nlO0ilOi_dataout WHEN niOO0001O = '1' ELSE nllO0i1i; + wire_nlO00OiiO_dataout <= nlO00lOiO OR niOiOOi0O; + wire_nlO00Oil_dataout <= wire_nlO0ilOl_dataout WHEN niOO0001O = '1' ELSE nllO0i1l; + wire_nlO00Oili_dataout <= wire_nlO00Ol1i_dataout AND NOT(niOiOOi0O); + wire_nlO00Oill_dataout <= wire_nlO00Ol1l_dataout AND NOT(niOiOOi0O); + wire_nlO00OilO_dataout <= wire_nlO00Ol1O_dataout AND NOT(niOiOOi0O); + wire_nlO00OiO_dataout <= wire_nlO0ilOO_dataout WHEN niOO0001O = '1' ELSE nllO0i0l; + wire_nlO00OiOi_dataout <= wire_nlO00Ol0i_dataout AND NOT(niOiOOi0O); + wire_nlO00OiOl_dataout <= wire_nlO00Ol0l_dataout AND NOT(niOiOOi0O); + wire_nlO00OiOO_dataout <= wire_nlO00Ol0O_dataout OR niOiOOi0O; + wire_nlO00Ol0i_dataout <= wire_nlO00Olli_dataout AND NOT(niOiOOi0l); + wire_nlO00Ol0l_dataout <= wire_nlO00Olll_dataout AND NOT(niOiOOi0l); + wire_nlO00Ol0O_dataout <= wire_nlO00OllO_dataout AND NOT(niOiOOi0l); + wire_nlO00Ol1i_dataout <= wire_nlO00Olii_dataout OR niOiOOi0l; + wire_nlO00Ol1l_dataout <= wire_nlO00Olil_dataout AND NOT(niOiOOi0l); + wire_nlO00Ol1O_dataout <= wire_nlO00OliO_dataout AND NOT(niOiOOi0l); + wire_nlO00Oli_dataout <= wire_nlll0lli_q(132) WHEN niOO0001O = '1' ELSE nllO0i1O; + wire_nlO00Olii_dataout <= wire_nlO00OlOi_dataout AND NOT(niOl11l0l); + wire_nlO00Olil_dataout <= wire_nlO00OlOl_dataout AND NOT(niOl11l0l); + wire_nlO00OliO_dataout <= wire_nlO00OlOO_dataout OR niOl11l0l; + wire_nlO00Oll_dataout <= wire_nlll0lli_q(64) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iO1i_dataout; + wire_nlO00Olli_dataout <= wire_nlO00OO1i_dataout AND NOT(niOl11l0l); + wire_nlO00Olll_dataout <= wire_nlO00OO1l_dataout AND NOT(niOl11l0l); + wire_nlO00OllO_dataout <= wire_nlO00OO1O_dataout AND NOT(niOl11l0l); + wire_nlO00OlO_dataout <= wire_nlll0lli_q(65) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iO1l_dataout; + wire_nlO00OlOi_dataout <= nlO00lOlO AND NOT(niOiOOiil); + wire_nlO00OlOl_dataout <= nlO00lOOi OR niOiOOiil; + wire_nlO00OlOO_dataout <= nlO00lOOl AND NOT(niOiOOiil); + wire_nlO00OO1i_dataout <= nlO00lOOO AND NOT(niOiOOiil); + wire_nlO00OO1l_dataout <= nlO00O11i AND NOT(niOiOOiil); + wire_nlO00OO1O_dataout <= nlO00O11l AND NOT(niOiOOiil); + wire_nlO00OOi_dataout <= wire_nlll0lli_q(66) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iO1O_dataout; + wire_nlO00OOil_dataout <= niOiOOiil AND NOT(niOl11l0l); + wire_nlO00OOiO_dataout <= wire_w_lg_niOiOOiil29534w(0) AND NOT(niOl11l0l); + wire_nlO00OOl_dataout <= wire_nlll0lli_q(67) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iO0i_dataout; + wire_nlO00OOO_dataout <= wire_nlll0lli_q(68) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iO0l_dataout; + wire_nlO00OOOi_dataout <= nlO00lOlO AND NOT(niOiOOiiO); + wire_nlO00OOOl_dataout <= nlO00lOOi AND NOT(niOiOOiiO); + wire_nlO00OOOO_dataout <= nlO00lOOl AND NOT(niOiOOiiO); + wire_nlO01000i_dataout <= nlO0OlO1l WHEN nlO00lOll = '1' ELSE wire_nlO01i1il_dataout; + wire_nlO01000l_dataout <= nlO0OlO1O WHEN nlO00lOll = '1' ELSE wire_nlO01i1iO_dataout; + wire_nlO01000O_dataout <= nlO0OlO0i WHEN nlO00lOll = '1' ELSE wire_nlO01i1li_dataout; + wire_nlO01001i_dataout <= nlO0OllOl WHEN nlO00lOll = '1' ELSE wire_nlO01i10l_dataout; + wire_nlO01001l_dataout <= nlO0OllOO WHEN nlO00lOll = '1' ELSE wire_nlO01i10O_dataout; + wire_nlO01001O_dataout <= nlO0OlO1i WHEN nlO00lOll = '1' ELSE wire_nlO01i1ii_dataout; + wire_nlO0100i_dataout <= nllO1l0i WHEN niOO000Oi = '1' ELSE wire_nlO001li_dataout; + wire_nlO0100ii_dataout <= nlO0OlO0l WHEN nlO00lOll = '1' ELSE wire_nlO01i1ll_dataout; + wire_nlO0100il_dataout <= nlO0OlO0O WHEN nlO00lOll = '1' ELSE wire_nlO01i1lO_dataout; + wire_nlO0100iO_dataout <= wire_nlO01i1Oi_dataout AND NOT(nlO00lOll); + wire_nlO0100l_dataout <= nllO1l0l WHEN niOO000Oi = '1' ELSE wire_nlO001ll_dataout; + wire_nlO0100li_dataout <= wire_nlO01i1Ol_dataout AND NOT(nlO00lOll); + wire_nlO0100ll_dataout <= wire_nlO01i1OO_dataout OR nlO00lOll; + wire_nlO0100lO_dataout <= wire_nlO01i01i_dataout OR nlO00lOll; + wire_nlO0100O_dataout <= nllO1l0O WHEN niOO000Oi = '1' ELSE wire_nlO001lO_dataout; + wire_nlO0100Oi_dataout <= wire_nlO01i01l_dataout OR nlO00lOll; + wire_nlO0100Ol_dataout <= wire_nlO01i01O_dataout AND NOT(nlO00lOll); + wire_nlO0100OO_dataout <= wire_nlO01i00i_dataout OR nlO00lOll; + wire_nlO01010i_dataout <= nlO0Oll1l WHEN nlO00lOll = '1' ELSE wire_nlO010Oil_dataout; + wire_nlO01010l_dataout <= nlO0Oll1O WHEN nlO00lOll = '1' ELSE wire_nlO010OiO_dataout; + wire_nlO01010O_dataout <= nlO0Oll0i WHEN nlO00lOll = '1' ELSE wire_nlO010Oli_dataout; + wire_nlO01011i_dataout <= nlO0OliOl WHEN nlO00lOll = '1' ELSE wire_nlO010O0l_dataout; + wire_nlO01011l_dataout <= nlO0OliOO WHEN nlO00lOll = '1' ELSE wire_nlO010O0O_dataout; + wire_nlO01011O_dataout <= nlO0Oll1i WHEN nlO00lOll = '1' ELSE wire_nlO010Oii_dataout; + wire_nlO0101i_dataout <= nllO1l1i WHEN niOO000Oi = '1' ELSE wire_nlO001ii_dataout; + wire_nlO0101ii_dataout <= nlO0Oll0l WHEN nlO00lOll = '1' ELSE wire_nlO010Oll_dataout; + wire_nlO0101il_dataout <= nlO0Oll0O WHEN nlO00lOll = '1' ELSE wire_nlO010OlO_dataout; + wire_nlO0101iO_dataout <= nlO0Ollii WHEN nlO00lOll = '1' ELSE wire_nlO010OOi_dataout; + wire_nlO0101l_dataout <= nllO1l1l WHEN niOO000Oi = '1' ELSE wire_nlO001il_dataout; + wire_nlO0101li_dataout <= nlO0Ollil WHEN nlO00lOll = '1' ELSE wire_nlO010OOl_dataout; + wire_nlO0101ll_dataout <= nlO0OlliO WHEN nlO00lOll = '1' ELSE wire_nlO010OOO_dataout; + wire_nlO0101lO_dataout <= nlO0Ollli WHEN nlO00lOll = '1' ELSE wire_nlO01i11i_dataout; + wire_nlO0101O_dataout <= nllO1l1O WHEN niOO000Oi = '1' ELSE wire_nlO001iO_dataout; + wire_nlO0101Oi_dataout <= nlO0Ollll WHEN nlO00lOll = '1' ELSE wire_nlO01i11l_dataout; + wire_nlO0101Ol_dataout <= nlO0OlllO WHEN nlO00lOll = '1' ELSE wire_nlO01i11O_dataout; + wire_nlO0101OO_dataout <= nlO0OllOi WHEN nlO00lOll = '1' ELSE wire_nlO01i10i_dataout; + wire_nlO010i0i_dataout <= nlO0iO1ii WHEN nlO00O11i = '1' ELSE wire_nlO01i0il_dataout; + wire_nlO010i0l_dataout <= nlO0iO1il WHEN nlO00O11i = '1' ELSE wire_nlO01i0iO_dataout; + wire_nlO010i0O_dataout <= nlO0iO1iO WHEN nlO00O11i = '1' ELSE wire_nlO01i0li_dataout; + wire_nlO010i1i_dataout <= wire_nlO01i00l_dataout AND NOT(nlO00lOll); + wire_nlO010i1l_dataout <= nlO0iO10l WHEN nlO00O11i = '1' ELSE wire_nlO01i00O_dataout; + wire_nlO010i1O_dataout <= nlO0iO10O WHEN nlO00O11i = '1' ELSE wire_nlO01i0ii_dataout; + wire_nlO010ii_dataout <= nllO1lii WHEN niOO000Oi = '1' ELSE wire_nlO001Oi_dataout; + wire_nlO010iii_dataout <= nlO0iO1li WHEN nlO00O11i = '1' ELSE wire_nlO01i0ll_dataout; + wire_nlO010iil_dataout <= nlO0iO1ll WHEN nlO00O11i = '1' ELSE wire_nlO01i0lO_dataout; + wire_nlO010iiO_dataout <= nlO0iO1lO WHEN nlO00O11i = '1' ELSE wire_nlO01i0Oi_dataout; + wire_nlO010il_dataout <= nllO1lil WHEN niOO000Oi = '1' ELSE wire_nlO001Ol_dataout; + wire_nlO010ili_dataout <= nlO0iO1Oi WHEN nlO00O11i = '1' ELSE wire_nlO01i0Ol_dataout; + wire_nlO010ill_dataout <= nlO0iO1Ol WHEN nlO00O11i = '1' ELSE wire_nlO01i0OO_dataout; + wire_nlO010ilO_dataout <= nlO0iO1OO WHEN nlO00O11i = '1' ELSE wire_nlO01ii1i_dataout; + wire_nlO010iO_dataout <= nllO1liO WHEN niOO000Oi = '1' ELSE wire_nlO001OO_dataout; + wire_nlO010iOi_dataout <= nlO0iO01i WHEN nlO00O11i = '1' ELSE wire_nlO01ii1l_dataout; + wire_nlO010iOl_dataout <= nlO0iO01l WHEN nlO00O11i = '1' ELSE wire_nlO01ii1O_dataout; + wire_nlO010iOO_dataout <= nlO0iO01O WHEN nlO00O11i = '1' ELSE wire_nlO01ii0i_dataout; + wire_nlO010l0i_dataout <= nlO0iO0ii WHEN nlO00O11i = '1' ELSE wire_nlO01iiil_dataout; + wire_nlO010l0l_dataout <= nlO0iO0il WHEN nlO00O11i = '1' ELSE wire_nlO01iiiO_dataout; + wire_nlO010l0O_dataout <= nlO0iO0iO WHEN nlO00O11i = '1' ELSE wire_nlO01iili_dataout; + wire_nlO010l1i_dataout <= nlO0iO00i WHEN nlO00O11i = '1' ELSE wire_nlO01ii0l_dataout; + wire_nlO010l1l_dataout <= nlO0iO00l WHEN nlO00O11i = '1' ELSE wire_nlO01ii0O_dataout; + wire_nlO010l1O_dataout <= nlO0iO00O WHEN nlO00O11i = '1' ELSE wire_nlO01iiii_dataout; + wire_nlO010li_dataout <= nllO1lli WHEN niOO000Oi = '1' ELSE wire_nlO0001i_dataout; + wire_nlO010lii_dataout <= nlO0iO0li WHEN nlO00O11i = '1' ELSE wire_nlO01iill_dataout; + wire_nlO010lil_dataout <= nlO0iO0ll WHEN nlO00O11i = '1' ELSE wire_nlO01iilO_dataout; + wire_nlO010liO_dataout <= nlO0iO0lO WHEN nlO00O11i = '1' ELSE wire_nlO01iiOi_dataout; + wire_nlO010ll_dataout <= nllO1lll WHEN niOO000Oi = '1' ELSE wire_nlO0001l_dataout; + wire_nlO010lli_dataout <= nlO0iO0Oi WHEN nlO00O11i = '1' ELSE wire_nlO01iiOl_dataout; + wire_nlO010lll_dataout <= nlO0iO0Ol WHEN nlO00O11i = '1' ELSE wire_nlO01iiOO_dataout; + wire_nlO010llO_dataout <= nlO0iO0OO WHEN nlO00O11i = '1' ELSE wire_nlO01il1i_dataout; + wire_nlO010lO_dataout <= nllO1llO WHEN niOO000Oi = '1' ELSE wire_nlO0001O_dataout; + wire_nlO010lOi_dataout <= nlO0iOi1i WHEN nlO00O11i = '1' ELSE wire_nlO01il1l_dataout; + wire_nlO010lOl_dataout <= nlO0iOi1l WHEN nlO00O11i = '1' ELSE wire_nlO01il1O_dataout; + wire_nlO010lOO_dataout <= nlO0iOi1O WHEN nlO00O11i = '1' ELSE wire_nlO01il0i_dataout; + wire_nlO010O0i_dataout <= nlO0iOiii WHEN nlO00O11i = '1' ELSE wire_nlO01ilil_dataout; + wire_nlO010O0l_dataout <= nlO0iOiil WHEN nlO00O11i = '1' ELSE wire_nlO01iliO_dataout; + wire_nlO010O0O_dataout <= nlO0iOiiO WHEN nlO00O11i = '1' ELSE wire_nlO01illi_dataout; + wire_nlO010O1i_dataout <= nlO0iOi0i WHEN nlO00O11i = '1' ELSE wire_nlO01il0l_dataout; + wire_nlO010O1l_dataout <= nlO0iOi0l WHEN nlO00O11i = '1' ELSE wire_nlO01il0O_dataout; + wire_nlO010O1O_dataout <= nlO0iOi0O WHEN nlO00O11i = '1' ELSE wire_nlO01ilii_dataout; + wire_nlO010Oi_dataout <= nllO1lOi WHEN niOO000Oi = '1' ELSE wire_nlO0000i_dataout; + wire_nlO010Oii_dataout <= nlO0iOili WHEN nlO00O11i = '1' ELSE wire_nlO01illl_dataout; + wire_nlO010Oil_dataout <= nlO0iOill WHEN nlO00O11i = '1' ELSE wire_nlO01illO_dataout; + wire_nlO010OiO_dataout <= nlO0iOilO WHEN nlO00O11i = '1' ELSE wire_nlO01ilOi_dataout; + wire_nlO010Ol_dataout <= nllO1lOl WHEN niOO000Oi = '1' ELSE wire_nlO0000l_dataout; + wire_nlO010Oli_dataout <= nlO0iOiOi WHEN nlO00O11i = '1' ELSE wire_nlO01ilOl_dataout; + wire_nlO010Oll_dataout <= nlO0iOiOl WHEN nlO00O11i = '1' ELSE wire_nlO01ilOO_dataout; + wire_nlO010OlO_dataout <= nlO0il00l WHEN nlO00O11i = '1' ELSE wire_nlO01iO1i_dataout; + wire_nlO010OO_dataout <= nllO1lOO WHEN niOO000Oi = '1' ELSE wire_nlO0000O_dataout; + wire_nlO010OOi_dataout <= nlO0il00O WHEN nlO00O11i = '1' ELSE wire_nlO01iO1l_dataout; + wire_nlO010OOl_dataout <= nlO0il0ii WHEN nlO00O11i = '1' ELSE wire_nlO01iO1O_dataout; + wire_nlO010OOO_dataout <= nlO0il0il WHEN nlO00O11i = '1' ELSE wire_nlO01iO0i_dataout; + wire_nlO01100i_dataout <= wire_nlO0110iO_dataout AND NOT(nlO00lOll); + wire_nlO01100l_dataout <= wire_nlO0110iO_dataout AND NOT(nlO00lOll); + wire_nlO01100O_dataout <= wire_nlO0110li_dataout AND NOT(nlO00lOll); + wire_nlO01101l_dataout <= wire_nlO0110il_dataout OR nlO00lOll; + wire_nlO01101O_dataout <= wire_nlO0110iO_dataout AND NOT(nlO00lOll); + wire_nlO0110i_dataout <= wire_nlll0lli_q(120) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1i0O; + wire_nlO0110ii_dataout <= nlO00O11i OR nlO00lOll; + wire_nlO0110il_dataout <= wire_nlO0110ll_dataout AND NOT(nlO00O11i); + wire_nlO0110iO_dataout <= wire_nlO0110lO_dataout AND NOT(nlO00O11i); + wire_nlO0110l_dataout <= wire_nlll0lli_q(121) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1iii; + wire_nlO0110li_dataout <= wire_nlO0110Oi_dataout AND NOT(nlO00O11i); + wire_nlO0110ll_dataout <= wire_nlO0110Ol_dataout AND NOT(nlO00lOOO); + wire_nlO0110lO_dataout <= wire_nlO0110OO_dataout AND NOT(nlO00lOOO); + wire_nlO0110O_dataout <= wire_nlll0lli_q(122) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1iil; + wire_nlO0110Oi_dataout <= wire_nlO011i1i_dataout AND NOT(nlO00lOOO); + wire_nlO0110Ol_dataout <= wire_nlO011i1l_dataout AND NOT(nlO00lOOl); + wire_nlO0110OO_dataout <= wire_nlO011i1O_dataout AND NOT(nlO00lOOl); + wire_nlO01110i_dataout <= wire_nlO0100li_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol11O; + wire_nlO01110l_dataout <= wire_nlO0100ll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol10i; + wire_nlO01110O_dataout <= wire_nlO0100lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol10l; + wire_nlO01111i_dataout <= wire_nlO0100ii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOOO; + wire_nlO01111l_dataout <= wire_nlO0100il_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol11i; + wire_nlO01111O_dataout <= wire_nlO0100iO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol11l; + wire_nlO0111i_dataout <= wire_nlll0lli_q(117) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1i1O; + wire_nlO0111ii_dataout <= wire_nlO0100Oi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol10O; + wire_nlO0111il_dataout <= wire_nlO0100Ol_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol1ii; + wire_nlO0111iO_dataout <= wire_nlO0100OO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol1il; + wire_nlO0111l_dataout <= wire_nlll0lli_q(118) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1i0i; + wire_nlO0111li_dataout <= wire_nlO010i1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Ol1iO; + wire_nlO0111ll_dataout <= ((nlO00lOiO OR (nlO00lOll OR nlO00lOli)) OR nlO1Ol1li) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi1ll; + wire_nlO0111lO_dataout <= niOiOO0lO WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi1lO; + wire_nlO0111O_dataout <= wire_nlll0lli_q(119) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1i0l; + wire_nlO011i0i_dataout <= wire_nlO011iii_dataout AND NOT(niOiOOi1l); + wire_nlO011i0l_dataout <= wire_nlO011iil_dataout AND NOT(niOiOOi1i); + wire_nlO011i0O_dataout <= wire_nlO011iiO_dataout AND NOT(niOiOOi1i); + wire_nlO011i1i_dataout <= wire_nlO011i0i_dataout AND NOT(nlO00lOOl); + wire_nlO011i1l_dataout <= wire_nlO011i0l_dataout AND NOT(niOiOOi1l); + wire_nlO011i1O_dataout <= wire_nlO011i0O_dataout AND NOT(niOiOOi1l); + wire_nlO011ii_dataout <= wire_nlll0lli_q(123) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1iiO; + wire_nlO011iii_dataout <= wire_nlO011ili_dataout AND NOT(niOiOOi1i); + wire_nlO011iil_dataout <= wire_nlO011ill_dataout AND NOT(niOiOO0OO); + wire_nlO011iiO_dataout <= niOiOO0Ol AND NOT(niOiOO0OO); + wire_nlO011il_dataout <= wire_nlll0lli_q(124) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1ili; + wire_nlO011ili_dataout <= niOiOO0Ol OR niOiOO0OO; + wire_nlO011ill_dataout <= wire_nlO011ilO_dataout OR niOiOO0Ol; + wire_nlO011ilO_dataout <= nlO00lOiO OR niOiOO0Oi; + wire_nlO011iO_dataout <= wire_nlll0lli_q(125) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1ill; + wire_nlO011iOi_dataout <= wire_nlO010i1l_dataout OR nlO00lOll; + wire_nlO011iOl_dataout <= wire_nlO010i1O_dataout AND NOT(nlO00lOll); + wire_nlO011iOO_dataout <= wire_nlO010i0i_dataout OR nlO00lOll; + wire_nlO011l0i_dataout <= wire_nlO010iil_dataout OR nlO00lOll; + wire_nlO011l0l_dataout <= wire_nlO010iiO_dataout OR nlO00lOll; + wire_nlO011l0O_dataout <= nlO0lilli WHEN nlO00lOll = '1' ELSE wire_nlO010ili_dataout; + wire_nlO011l1i_dataout <= wire_nlO010i0l_dataout OR nlO00lOll; + wire_nlO011l1l_dataout <= wire_nlO010i0O_dataout OR nlO00lOll; + wire_nlO011l1O_dataout <= wire_nlO010iii_dataout OR nlO00lOll; + wire_nlO011li_dataout <= wire_nlll0lli_q(126) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1ilO; + wire_nlO011lii_dataout <= nlO0Ol00l WHEN nlO00lOll = '1' ELSE wire_nlO010ill_dataout; + wire_nlO011lil_dataout <= nlO0Ol00O WHEN nlO00lOll = '1' ELSE wire_nlO010ilO_dataout; + wire_nlO011liO_dataout <= nlO0Ol0ii WHEN nlO00lOll = '1' ELSE wire_nlO010iOi_dataout; + wire_nlO011ll_dataout <= wire_nlll0lli_q(127) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1iOi; + wire_nlO011lli_dataout <= nlO0Ol0il WHEN nlO00lOll = '1' ELSE wire_nlO010iOl_dataout; + wire_nlO011lll_dataout <= nlO0Ol0iO WHEN nlO00lOll = '1' ELSE wire_nlO010iOO_dataout; + wire_nlO011llO_dataout <= nlO0Ol0li WHEN nlO00lOll = '1' ELSE wire_nlO010l1i_dataout; + wire_nlO011lOi_dataout <= nlO0Ol0ll WHEN nlO00lOll = '1' ELSE wire_nlO010l1l_dataout; + wire_nlO011lOl_dataout <= nlO0Ol0lO WHEN nlO00lOll = '1' ELSE wire_nlO010l1O_dataout; + wire_nlO011lOO_dataout <= nlO0Ol0Oi WHEN nlO00lOll = '1' ELSE wire_nlO010l0i_dataout; + wire_nlO011O0i_dataout <= nlO0Oli1l WHEN nlO00lOll = '1' ELSE wire_nlO010lil_dataout; + wire_nlO011O0l_dataout <= nlO0Oli1O WHEN nlO00lOll = '1' ELSE wire_nlO010liO_dataout; + wire_nlO011O0O_dataout <= nlO0Oli0i WHEN nlO00lOll = '1' ELSE wire_nlO010lli_dataout; + wire_nlO011O1i_dataout <= nlO0Ol0Ol WHEN nlO00lOll = '1' ELSE wire_nlO010l0l_dataout; + wire_nlO011O1l_dataout <= nlO0Ol0OO WHEN nlO00lOll = '1' ELSE wire_nlO010l0O_dataout; + wire_nlO011O1O_dataout <= nlO0Oli1i WHEN nlO00lOll = '1' ELSE wire_nlO010lii_dataout; + wire_nlO011Oii_dataout <= nlO0Oli0l WHEN nlO00lOll = '1' ELSE wire_nlO010lll_dataout; + wire_nlO011Oil_dataout <= nlO0Oli0O WHEN nlO00lOll = '1' ELSE wire_nlO010llO_dataout; + wire_nlO011OiO_dataout <= nlO0Oliii WHEN nlO00lOll = '1' ELSE wire_nlO010lOi_dataout; + wire_nlO011Ol_dataout <= nllO1iOl WHEN niOO000Oi = '1' ELSE wire_nlO0010l_dataout; + wire_nlO011Oli_dataout <= nlO0Oliil WHEN nlO00lOll = '1' ELSE wire_nlO010lOl_dataout; + wire_nlO011Oll_dataout <= nlO0OliiO WHEN nlO00lOll = '1' ELSE wire_nlO010lOO_dataout; + wire_nlO011OlO_dataout <= nlO0Olili WHEN nlO00lOll = '1' ELSE wire_nlO010O1i_dataout; + wire_nlO011OO_dataout <= nllO1iOO WHEN niOO000Oi = '1' ELSE wire_nlO0010O_dataout; + wire_nlO011OOi_dataout <= nlO0Olill WHEN nlO00lOll = '1' ELSE wire_nlO010O1l_dataout; + wire_nlO011OOl_dataout <= nlO0OlilO WHEN nlO00lOll = '1' ELSE wire_nlO010O1O_dataout; + wire_nlO011OOO_dataout <= nlO0OliOi WHEN nlO00lOll = '1' ELSE wire_nlO010O0i_dataout; + wire_nlO01i00i_dataout <= wire_nlO01l1il_dataout OR nlO00O11i; + wire_nlO01i00l_dataout <= wire_nlO01l1iO_dataout OR nlO00O11i; + wire_nlO01i00O_dataout <= nlO0iO10l WHEN nlO00lOOO = '1' ELSE wire_nlO01l1li_dataout; + wire_nlO01i01i_dataout <= wire_nlO01l10l_dataout OR nlO00O11i; + wire_nlO01i01l_dataout <= wire_nlO01l10O_dataout OR nlO00O11i; + wire_nlO01i01O_dataout <= wire_nlO01l1ii_dataout OR nlO00O11i; + wire_nlO01i0i_dataout <= nllO1O0i WHEN niOO000Oi = '1' ELSE wire_nlO000li_dataout; + wire_nlO01i0ii_dataout <= nlO0iO10O WHEN nlO00lOOO = '1' ELSE wire_nlO01l1ll_dataout; + wire_nlO01i0il_dataout <= nlO0iO1ii WHEN nlO00lOOO = '1' ELSE wire_nlO01l1lO_dataout; + wire_nlO01i0iO_dataout <= nlO0iO1il WHEN nlO00lOOO = '1' ELSE wire_nlO01l1Oi_dataout; + wire_nlO01i0l_dataout <= nllO1O0l WHEN niOO000Oi = '1' ELSE wire_nlO000ll_dataout; + wire_nlO01i0li_dataout <= nlO0iO1iO WHEN nlO00lOOO = '1' ELSE wire_nlO01l1Ol_dataout; + wire_nlO01i0ll_dataout <= nlO0iO1li WHEN nlO00lOOO = '1' ELSE wire_nlO01l1OO_dataout; + wire_nlO01i0lO_dataout <= nlO0iO1ll WHEN nlO00lOOO = '1' ELSE wire_nlO01l01i_dataout; + wire_nlO01i0O_dataout <= nllO1O0O WHEN niOO000Oi = '1' ELSE wire_nlO000lO_dataout; + wire_nlO01i0Oi_dataout <= nlO0iO1lO WHEN nlO00lOOO = '1' ELSE wire_nlO01l01l_dataout; + wire_nlO01i0Ol_dataout <= nlO0iO1Oi WHEN nlO00lOOO = '1' ELSE wire_nlO01l01O_dataout; + wire_nlO01i0OO_dataout <= nlO0iO1Ol WHEN nlO00lOOO = '1' ELSE wire_nlO01l00i_dataout; + wire_nlO01i10i_dataout <= nlO0il0lO WHEN nlO00O11i = '1' ELSE wire_nlO01iOil_dataout; + wire_nlO01i10l_dataout <= nlO0il0Oi WHEN nlO00O11i = '1' ELSE wire_nlO01iOiO_dataout; + wire_nlO01i10O_dataout <= nlO0il0Ol WHEN nlO00O11i = '1' ELSE wire_nlO01iOli_dataout; + wire_nlO01i11i_dataout <= nlO0il0iO WHEN nlO00O11i = '1' ELSE wire_nlO01iO0l_dataout; + wire_nlO01i11l_dataout <= nlO0il0li WHEN nlO00O11i = '1' ELSE wire_nlO01iO0O_dataout; + wire_nlO01i11O_dataout <= nlO0il0ll WHEN nlO00O11i = '1' ELSE wire_nlO01iOii_dataout; + wire_nlO01i1i_dataout <= nllO1O1i WHEN niOO000Oi = '1' ELSE wire_nlO000ii_dataout; + wire_nlO01i1ii_dataout <= nlO0il0OO WHEN nlO00O11i = '1' ELSE wire_nlO01iOll_dataout; + wire_nlO01i1il_dataout <= nlO0ili1i WHEN nlO00O11i = '1' ELSE wire_nlO01iOlO_dataout; + wire_nlO01i1iO_dataout <= wire_nlO01iOOi_dataout AND NOT(nlO00O11i); + wire_nlO01i1l_dataout <= nllO1O1l WHEN niOO000Oi = '1' ELSE wire_nlO000il_dataout; + wire_nlO01i1li_dataout <= wire_nlO01iOOl_dataout AND NOT(nlO00O11i); + wire_nlO01i1ll_dataout <= wire_nlO01iOOO_dataout AND NOT(nlO00O11i); + wire_nlO01i1lO_dataout <= wire_nlO01l11i_dataout AND NOT(nlO00O11i); + wire_nlO01i1O_dataout <= nllO1O1O WHEN niOO000Oi = '1' ELSE wire_nlO000iO_dataout; + wire_nlO01i1Oi_dataout <= wire_nlO01l11l_dataout OR nlO00O11i; + wire_nlO01i1Ol_dataout <= wire_nlO01l11O_dataout OR nlO00O11i; + wire_nlO01i1OO_dataout <= wire_nlO01l10i_dataout AND NOT(nlO00O11i); + wire_nlO01ii0i_dataout <= nlO0iO01O WHEN nlO00lOOO = '1' ELSE wire_nlO01l0il_dataout; + wire_nlO01ii0l_dataout <= nlO0iO00i WHEN nlO00lOOO = '1' ELSE wire_nlO01l0iO_dataout; + wire_nlO01ii0O_dataout <= nlO0iO00l WHEN nlO00lOOO = '1' ELSE wire_nlO01l0li_dataout; + wire_nlO01ii1i_dataout <= nlO0iO1OO WHEN nlO00lOOO = '1' ELSE wire_nlO01l00l_dataout; + wire_nlO01ii1l_dataout <= nlO0iO01i WHEN nlO00lOOO = '1' ELSE wire_nlO01l00O_dataout; + wire_nlO01ii1O_dataout <= nlO0iO01l WHEN nlO00lOOO = '1' ELSE wire_nlO01l0ii_dataout; + wire_nlO01iii_dataout <= nllO1Oii WHEN niOO000Oi = '1' ELSE wire_nlO000Oi_dataout; + wire_nlO01iiii_dataout <= nlO0iO00O WHEN nlO00lOOO = '1' ELSE wire_nlO01l0ll_dataout; + wire_nlO01iiil_dataout <= nlO0iO0ii WHEN nlO00lOOO = '1' ELSE wire_nlO01l0lO_dataout; + wire_nlO01iiiO_dataout <= nlO0iO0il WHEN nlO00lOOO = '1' ELSE wire_nlO01l0Oi_dataout; + wire_nlO01iil_dataout <= nllO1Oil WHEN niOO000Oi = '1' ELSE wire_nlO000Ol_dataout; + wire_nlO01iili_dataout <= nlO0iO0iO WHEN nlO00lOOO = '1' ELSE wire_nlO01l0Ol_dataout; + wire_nlO01iill_dataout <= nlO0iO0li WHEN nlO00lOOO = '1' ELSE wire_nlO01l0OO_dataout; + wire_nlO01iilO_dataout <= nlO0iO0ll WHEN nlO00lOOO = '1' ELSE wire_nlO01li1i_dataout; + wire_nlO01iiO_dataout <= nllO1OiO WHEN niOO000Oi = '1' ELSE wire_nlO000OO_dataout; + wire_nlO01iiOi_dataout <= nlO0iO0lO WHEN nlO00lOOO = '1' ELSE wire_nlO01li1l_dataout; + wire_nlO01iiOl_dataout <= nlO0iO0Oi WHEN nlO00lOOO = '1' ELSE wire_nlO01li1O_dataout; + wire_nlO01iiOO_dataout <= nlO0iO0Ol WHEN nlO00lOOO = '1' ELSE wire_nlO01li0i_dataout; + wire_nlO01il0i_dataout <= nlO0iOi1O WHEN nlO00lOOO = '1' ELSE wire_nlO01liil_dataout; + wire_nlO01il0l_dataout <= nlO0iOi0i WHEN nlO00lOOO = '1' ELSE wire_nlO01liiO_dataout; + wire_nlO01il0O_dataout <= nlO0iOi0l WHEN nlO00lOOO = '1' ELSE wire_nlO01lili_dataout; + wire_nlO01il1i_dataout <= nlO0iO0OO WHEN nlO00lOOO = '1' ELSE wire_nlO01li0l_dataout; + wire_nlO01il1l_dataout <= nlO0iOi1i WHEN nlO00lOOO = '1' ELSE wire_nlO01li0O_dataout; + wire_nlO01il1O_dataout <= nlO0iOi1l WHEN nlO00lOOO = '1' ELSE wire_nlO01liii_dataout; + wire_nlO01ili_dataout <= nllO1Oli WHEN niOO000Oi = '1' ELSE wire_nlO00i1i_dataout; + wire_nlO01ilii_dataout <= nlO0iOi0O WHEN nlO00lOOO = '1' ELSE wire_nlO01lill_dataout; + wire_nlO01ilil_dataout <= nlO0iOiii WHEN nlO00lOOO = '1' ELSE wire_nlO01lilO_dataout; + wire_nlO01iliO_dataout <= nlO0iOiil WHEN nlO00lOOO = '1' ELSE wire_nlO01liOi_dataout; + wire_nlO01ill_dataout <= nllO1Oll WHEN niOO000Oi = '1' ELSE wire_nlO00i1l_dataout; + wire_nlO01illi_dataout <= nlO0iOiiO WHEN nlO00lOOO = '1' ELSE wire_nlO01liOl_dataout; + wire_nlO01illl_dataout <= nlO0iOili WHEN nlO00lOOO = '1' ELSE wire_nlO01liOO_dataout; + wire_nlO01illO_dataout <= nlO0iOill WHEN nlO00lOOO = '1' ELSE wire_nlO01ll1i_dataout; + wire_nlO01ilO_dataout <= nllO1OlO WHEN niOO000Oi = '1' ELSE wire_nlO00i1O_dataout; + wire_nlO01ilOi_dataout <= nlO0iOilO WHEN nlO00lOOO = '1' ELSE wire_nlO01ll1l_dataout; + wire_nlO01ilOl_dataout <= nlO0iOiOi WHEN nlO00lOOO = '1' ELSE wire_nlO01ll1O_dataout; + wire_nlO01ilOO_dataout <= nlO0iOiOl WHEN nlO00lOOO = '1' ELSE wire_nlO01ll0i_dataout; + wire_nlO01iO0i_dataout <= nlO0ili0l WHEN nlO00lOOO = '1' ELSE wire_nlO01llil_dataout; + wire_nlO01iO0l_dataout <= nlO0ili0O WHEN nlO00lOOO = '1' ELSE wire_nlO01lliO_dataout; + wire_nlO01iO0O_dataout <= nlO0iliii WHEN nlO00lOOO = '1' ELSE wire_nlO01llli_dataout; + wire_nlO01iO1i_dataout <= nlO0ili1l WHEN nlO00lOOO = '1' ELSE wire_nlO01ll0l_dataout; + wire_nlO01iO1l_dataout <= nlO0ili1O WHEN nlO00lOOO = '1' ELSE wire_nlO01ll0O_dataout; + wire_nlO01iO1O_dataout <= nlO0ili0i WHEN nlO00lOOO = '1' ELSE wire_nlO01llii_dataout; + wire_nlO01iOi_dataout <= nllO1OOi WHEN niOO000Oi = '1' ELSE wire_nlO00i0i_dataout; + wire_nlO01iOii_dataout <= nlO0iliil WHEN nlO00lOOO = '1' ELSE wire_nlO01llll_dataout; + wire_nlO01iOil_dataout <= nlO0iliiO WHEN nlO00lOOO = '1' ELSE wire_nlO01lllO_dataout; + wire_nlO01iOiO_dataout <= nlO0ilili WHEN nlO00lOOO = '1' ELSE wire_nlO01llOi_dataout; + wire_nlO01iOl_dataout <= nllO1OOl WHEN niOO000Oi = '1' ELSE wire_nlO00i0l_dataout; + wire_nlO01iOli_dataout <= nlO0ilill WHEN nlO00lOOO = '1' ELSE wire_nlO01llOl_dataout; + wire_nlO01iOll_dataout <= nlO0ililO WHEN nlO00lOOO = '1' ELSE wire_nlO01llOO_dataout; + wire_nlO01iOlO_dataout <= nlO0iliOi WHEN nlO00lOOO = '1' ELSE wire_nlO01lO1i_dataout; + wire_nlO01iOO_dataout <= nllO1OOO WHEN niOO000Oi = '1' ELSE wire_nlO00i0O_dataout; + wire_nlO01iOOi_dataout <= nlO0iliOl WHEN nlO00lOOO = '1' ELSE wire_nlO01lO1l_dataout; + wire_nlO01iOOl_dataout <= nlO0iliOO WHEN nlO00lOOO = '1' ELSE wire_nlO01lO1O_dataout; + wire_nlO01iOOO_dataout <= nlO0ill1i WHEN nlO00lOOO = '1' ELSE wire_nlO01lO0i_dataout; + wire_nlO01l00i_dataout <= nlO0iO1Ol WHEN nlO00lOOl = '1' ELSE wire_nlO01O1il_dataout; + wire_nlO01l00l_dataout <= nlO0iO1OO WHEN nlO00lOOl = '1' ELSE wire_nlO01O1iO_dataout; + wire_nlO01l00O_dataout <= nlO0iO01i WHEN nlO00lOOl = '1' ELSE wire_nlO01O1li_dataout; + wire_nlO01l01i_dataout <= niOiOOilO WHEN nlO00lOOl = '1' ELSE wire_nlO01O10l_dataout; + wire_nlO01l01l_dataout <= niOiOOili WHEN nlO00lOOl = '1' ELSE wire_nlO01O10O_dataout; + wire_nlO01l01O_dataout <= nlO0iO1Oi WHEN nlO00lOOl = '1' ELSE wire_nlO01O1ii_dataout; + wire_nlO01l0i_dataout <= nllO010i WHEN niOO000Oi = '1' ELSE wire_nlO00ili_dataout; + wire_nlO01l0ii_dataout <= nlO0iO01l WHEN nlO00lOOl = '1' ELSE wire_nlO01O1ll_dataout; + wire_nlO01l0il_dataout <= nlO0iO01O WHEN nlO00lOOl = '1' ELSE wire_nlO01O1lO_dataout; + wire_nlO01l0iO_dataout <= nlO0iO00i WHEN nlO00lOOl = '1' ELSE wire_nlO01O1Oi_dataout; + wire_nlO01l0l_dataout <= nllO010l WHEN niOO000Oi = '1' ELSE wire_nlO00ill_dataout; + wire_nlO01l0li_dataout <= nlO0iO00l WHEN nlO00lOOl = '1' ELSE wire_nlO01O1Ol_dataout; + wire_nlO01l0ll_dataout <= nlO0iO00O WHEN nlO00lOOl = '1' ELSE wire_nlO01O1OO_dataout; + wire_nlO01l0lO_dataout <= nlO0iO0ii WHEN nlO00lOOl = '1' ELSE wire_nlO01O01i_dataout; + wire_nlO01l0O_dataout <= nllO010O WHEN niOO000Oi = '1' ELSE wire_nlO00ilO_dataout; + wire_nlO01l0Oi_dataout <= nlO0iO0il WHEN nlO00lOOl = '1' ELSE wire_nlO01O01l_dataout; + wire_nlO01l0Ol_dataout <= nlO0iO0iO WHEN nlO00lOOl = '1' ELSE wire_nlO01O01O_dataout; + wire_nlO01l0OO_dataout <= nlO0iO0li WHEN nlO00lOOl = '1' ELSE wire_nlO01O00i_dataout; + wire_nlO01l10i_dataout <= nlO0ill0l WHEN nlO00lOOO = '1' ELSE wire_nlO01lOil_dataout; + wire_nlO01l10l_dataout <= nlO0ill0O WHEN nlO00lOOO = '1' ELSE wire_nlO01lOiO_dataout; + wire_nlO01l10O_dataout <= nlO0illii WHEN nlO00lOOO = '1' ELSE wire_nlO01lOli_dataout; + wire_nlO01l11i_dataout <= nlO0ill1l WHEN nlO00lOOO = '1' ELSE wire_nlO01lO0l_dataout; + wire_nlO01l11l_dataout <= nlO0ill1O WHEN nlO00lOOO = '1' ELSE wire_nlO01lO0O_dataout; + wire_nlO01l11O_dataout <= nlO0ill0i WHEN nlO00lOOO = '1' ELSE wire_nlO01lOii_dataout; + wire_nlO01l1i_dataout <= nllO011i WHEN niOO000Oi = '1' ELSE wire_nlO00iii_dataout; + wire_nlO01l1ii_dataout <= nlO0illil WHEN nlO00lOOO = '1' ELSE wire_nlO01lOll_dataout; + wire_nlO01l1il_dataout <= nlO0illiO WHEN nlO00lOOO = '1' ELSE wire_nlO01lOlO_dataout; + wire_nlO01l1iO_dataout <= nlO0illli WHEN nlO00lOOO = '1' ELSE wire_nlO01lOOi_dataout; + wire_nlO01l1l_dataout <= nllO011l WHEN niOO000Oi = '1' ELSE wire_nlO00iil_dataout; + wire_nlO01l1li_dataout <= niOiOOliO WHEN nlO00lOOl = '1' ELSE wire_nlO01lOOl_dataout; + wire_nlO01l1ll_dataout <= niOiOOlii WHEN nlO00lOOl = '1' ELSE wire_nlO01lOOO_dataout; + wire_nlO01l1lO_dataout <= niOiOOl0l WHEN nlO00lOOl = '1' ELSE wire_nlO01O11i_dataout; + wire_nlO01l1O_dataout <= nllO011O WHEN niOO000Oi = '1' ELSE wire_nlO00iiO_dataout; + wire_nlO01l1Oi_dataout <= niOiOOl1O WHEN nlO00lOOl = '1' ELSE wire_nlO01O11l_dataout; + wire_nlO01l1Ol_dataout <= niOiOOl1i WHEN nlO00lOOl = '1' ELSE wire_nlO01O11O_dataout; + wire_nlO01l1OO_dataout <= niOiOOiOl WHEN nlO00lOOl = '1' ELSE wire_nlO01O10i_dataout; + wire_nlO01li0i_dataout <= nlO0iO0Ol WHEN nlO00lOOl = '1' ELSE wire_nlO01O0il_dataout; + wire_nlO01li0l_dataout <= nlO0iO0OO WHEN nlO00lOOl = '1' ELSE wire_nlO01O0iO_dataout; + wire_nlO01li0O_dataout <= nlO0iOi1i WHEN nlO00lOOl = '1' ELSE wire_nlO01O0li_dataout; + wire_nlO01li1i_dataout <= nlO0iO0ll WHEN nlO00lOOl = '1' ELSE wire_nlO01O00l_dataout; + wire_nlO01li1l_dataout <= nlO0iO0lO WHEN nlO00lOOl = '1' ELSE wire_nlO01O00O_dataout; + wire_nlO01li1O_dataout <= nlO0iO0Oi WHEN nlO00lOOl = '1' ELSE wire_nlO01O0ii_dataout; + wire_nlO01lii_dataout <= nllO01ii WHEN niOO000Oi = '1' ELSE wire_nlO00iOi_dataout; + wire_nlO01liii_dataout <= nlO0iOi1l WHEN nlO00lOOl = '1' ELSE wire_nlO01O0ll_dataout; + wire_nlO01liil_dataout <= nlO0iOi1O WHEN nlO00lOOl = '1' ELSE wire_nlO01O0lO_dataout; + wire_nlO01liiO_dataout <= nlO0iOi0i WHEN nlO00lOOl = '1' ELSE wire_nlO01O0Oi_dataout; + wire_nlO01lil_dataout <= nllO01il WHEN niOO000Oi = '1' ELSE wire_nlO00iOl_dataout; + wire_nlO01lili_dataout <= nlO0iOi0l WHEN nlO00lOOl = '1' ELSE wire_nlO01O0Ol_dataout; + wire_nlO01lill_dataout <= nlO0iOi0O WHEN nlO00lOOl = '1' ELSE wire_nlO01O0OO_dataout; + wire_nlO01lilO_dataout <= nlO0iOiii WHEN nlO00lOOl = '1' ELSE wire_nlO01Oi1i_dataout; + wire_nlO01liO_dataout <= nllO01iO WHEN niOO000Oi = '1' ELSE wire_nlO00iOO_dataout; + wire_nlO01liOi_dataout <= nlO0iOiil WHEN nlO00lOOl = '1' ELSE wire_nlO01Oi1l_dataout; + wire_nlO01liOl_dataout <= nlO0iOiiO WHEN nlO00lOOl = '1' ELSE wire_nlO01Oi1O_dataout; + wire_nlO01liOO_dataout <= nlO0iOili WHEN nlO00lOOl = '1' ELSE wire_nlO01Oi0i_dataout; + wire_nlO01ll0i_dataout <= nlO0iOiOl WHEN nlO00lOOl = '1' ELSE wire_nlO01Oiil_dataout; + wire_nlO01ll0l_dataout <= nlO0ili1l WHEN nlO00lOOl = '1' ELSE wire_nlO01OiiO_dataout; + wire_nlO01ll0O_dataout <= nlO0ili1O WHEN nlO00lOOl = '1' ELSE wire_nlO01Oili_dataout; + wire_nlO01ll1i_dataout <= nlO0iOill WHEN nlO00lOOl = '1' ELSE wire_nlO01Oi0l_dataout; + wire_nlO01ll1l_dataout <= nlO0iOilO WHEN nlO00lOOl = '1' ELSE wire_nlO01Oi0O_dataout; + wire_nlO01ll1O_dataout <= nlO0iOiOi WHEN nlO00lOOl = '1' ELSE wire_nlO01Oiii_dataout; + wire_nlO01lli_dataout <= nllO01li WHEN niOO000Oi = '1' ELSE wire_nlO00l1i_dataout; + wire_nlO01llii_dataout <= nlO0ili0i WHEN nlO00lOOl = '1' ELSE wire_nlO01Oill_dataout; + wire_nlO01llil_dataout <= nlO0ili0l WHEN nlO00lOOl = '1' ELSE wire_nlO01OilO_dataout; + wire_nlO01lliO_dataout <= nlO0ili0O WHEN nlO00lOOl = '1' ELSE wire_nlO01OiOi_dataout; + wire_nlO01lll_dataout <= nllO01ll WHEN niOO000Oi = '1' ELSE wire_nlO00l1l_dataout; + wire_nlO01llli_dataout <= nlO0iliii WHEN nlO00lOOl = '1' ELSE wire_nlO01OiOl_dataout; + wire_nlO01llll_dataout <= nlO0iliil WHEN nlO00lOOl = '1' ELSE wire_nlO01OiOO_dataout; + wire_nlO01lllO_dataout <= nlO0iliiO WHEN nlO00lOOl = '1' ELSE wire_nlO01Ol1i_dataout; + wire_nlO01llO_dataout <= nllO01lO WHEN niOO000Oi = '1' ELSE wire_nlO00l1O_dataout; + wire_nlO01llOi_dataout <= nlO0ilili WHEN nlO00lOOl = '1' ELSE wire_nlO01Ol1l_dataout; + wire_nlO01llOl_dataout <= nlO0ilill WHEN nlO00lOOl = '1' ELSE wire_nlO01Ol1O_dataout; + wire_nlO01llOO_dataout <= nlO0ililO WHEN nlO00lOOl = '1' ELSE wire_nlO01Ol0i_dataout; + wire_nlO01lO0i_dataout <= nlO0ill1i WHEN nlO00lOOl = '1' ELSE wire_nlO01Olil_dataout; + wire_nlO01lO0l_dataout <= nlO0ill1l WHEN nlO00lOOl = '1' ELSE wire_nlO01OliO_dataout; + wire_nlO01lO0O_dataout <= nlO0ill1O WHEN nlO00lOOl = '1' ELSE wire_nlO01Olli_dataout; + wire_nlO01lO1i_dataout <= nlO0iliOi WHEN nlO00lOOl = '1' ELSE wire_nlO01Ol0l_dataout; + wire_nlO01lO1l_dataout <= nlO0iliOl WHEN nlO00lOOl = '1' ELSE wire_nlO01Ol0O_dataout; + wire_nlO01lO1O_dataout <= nlO0iliOO WHEN nlO00lOOl = '1' ELSE wire_nlO01Olii_dataout; + wire_nlO01lOi_dataout <= nllO01Oi WHEN niOO000Oi = '1' ELSE wire_nlO00l0i_dataout; + wire_nlO01lOii_dataout <= nlO0ill0i WHEN nlO00lOOl = '1' ELSE wire_nlO01Olll_dataout; + wire_nlO01lOil_dataout <= nlO0ill0l WHEN nlO00lOOl = '1' ELSE wire_nlO01OllO_dataout; + wire_nlO01lOiO_dataout <= nlO0ill0O WHEN nlO00lOOl = '1' ELSE wire_nlO01OlOi_dataout; + wire_nlO01lOl_dataout <= nllO01Ol WHEN niOO000Oi = '1' ELSE wire_nlO00l0l_dataout; + wire_nlO01lOli_dataout <= nlO0illii WHEN nlO00lOOl = '1' ELSE wire_nlO01OlOl_dataout; + wire_nlO01lOll_dataout <= nlO0illil WHEN nlO00lOOl = '1' ELSE wire_nlO01OlOO_dataout; + wire_nlO01lOlO_dataout <= nlO0illiO WHEN nlO00lOOl = '1' ELSE wire_nlO01OO1i_dataout; + wire_nlO01lOO_dataout <= nllO01OO WHEN niOO000Oi = '1' ELSE wire_nlO00l0O_dataout; + wire_nlO01lOOi_dataout <= nlO0illli WHEN nlO00lOOl = '1' ELSE wire_nlO01OO1l_dataout; + wire_nlO01lOOl_dataout <= wire_w_lg_niOl11iii29465w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OO1O_dataout; + wire_nlO01lOOO_dataout <= wire_w_lg_niOl11iil29464w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OO0i_dataout; + wire_nlO01O00i_dataout <= nlO0iO0li WHEN niOiOOi1l = '1' ELSE wire_nlO0011il_dataout; + wire_nlO01O00l_dataout <= nlO0iO0ll WHEN niOiOOi1l = '1' ELSE wire_nlO0011iO_dataout; + wire_nlO01O00O_dataout <= nlO0iO0lO WHEN niOiOOi1l = '1' ELSE wire_nlO0011li_dataout; + wire_nlO01O01i_dataout <= nlO0iO0ii WHEN niOiOOi1l = '1' ELSE wire_nlO00110l_dataout; + wire_nlO01O01l_dataout <= nlO0iO0il WHEN niOiOOi1l = '1' ELSE wire_nlO00110O_dataout; + wire_nlO01O01O_dataout <= nlO0iO0iO WHEN niOiOOi1l = '1' ELSE wire_nlO0011ii_dataout; + wire_nlO01O0i_dataout <= nllO000i WHEN niOO000Oi = '1' ELSE wire_nlO00lli_dataout; + wire_nlO01O0ii_dataout <= nlO0iO0Oi WHEN niOiOOi1l = '1' ELSE wire_nlO0011ll_dataout; + wire_nlO01O0il_dataout <= nlO0iO0Ol WHEN niOiOOi1l = '1' ELSE wire_nlO0011lO_dataout; + wire_nlO01O0iO_dataout <= nlO0iO0OO WHEN niOiOOi1l = '1' ELSE wire_nlO0011Oi_dataout; + wire_nlO01O0l_dataout <= nllO000l WHEN niOO000Oi = '1' ELSE wire_nlO00lll_dataout; + wire_nlO01O0li_dataout <= nlO0iOi1i WHEN niOiOOi1l = '1' ELSE wire_nlO0011Ol_dataout; + wire_nlO01O0ll_dataout <= nlO0iOi1l WHEN niOiOOi1l = '1' ELSE wire_nlO0011OO_dataout; + wire_nlO01O0lO_dataout <= nlO0iOi1O WHEN niOiOOi1l = '1' ELSE wire_nlO00101i_dataout; + wire_nlO01O0O_dataout <= nllO000O WHEN niOO000Oi = '1' ELSE wire_nlO00llO_dataout; + wire_nlO01O0Oi_dataout <= nlO0iOi0i WHEN niOiOOi1l = '1' ELSE wire_nlO00101l_dataout; + wire_nlO01O0Ol_dataout <= nlO0iOi0l WHEN niOiOOi1l = '1' ELSE wire_nlO00101O_dataout; + wire_nlO01O0OO_dataout <= nlO0iOi0O WHEN niOiOOi1l = '1' ELSE wire_nlO00100i_dataout; + wire_nlO01O10i_dataout <= wire_w_lg_niOl11ilO29460w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OOil_dataout; + wire_nlO01O10l_dataout <= wire_w_lg_niOl11iOi29459w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OOiO_dataout; + wire_nlO01O10O_dataout <= wire_w_lg_niOl11iOl29458w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OOli_dataout; + wire_nlO01O11i_dataout <= wire_w_lg_niOl11iiO29463w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OO0l_dataout; + wire_nlO01O11l_dataout <= wire_w_lg_niOl11ili29462w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OO0O_dataout; + wire_nlO01O11O_dataout <= wire_w_lg_niOl11ill29461w(0) WHEN niOiOOi1l = '1' ELSE wire_nlO01OOii_dataout; + wire_nlO01O1i_dataout <= nllO001i WHEN niOO000Oi = '1' ELSE wire_nlO00lii_dataout; + wire_nlO01O1ii_dataout <= nlO0iO1Oi WHEN niOiOOi1l = '1' ELSE wire_nlO01OOll_dataout; + wire_nlO01O1il_dataout <= nlO0iO1Ol WHEN niOiOOi1l = '1' ELSE wire_nlO01OOlO_dataout; + wire_nlO01O1iO_dataout <= nlO0iO1OO WHEN niOiOOi1l = '1' ELSE wire_nlO01OOOi_dataout; + wire_nlO01O1l_dataout <= nllO001l WHEN niOO000Oi = '1' ELSE wire_nlO00lil_dataout; + wire_nlO01O1li_dataout <= nlO0iO01i WHEN niOiOOi1l = '1' ELSE wire_nlO01OOOl_dataout; + wire_nlO01O1ll_dataout <= nlO0iO01l WHEN niOiOOi1l = '1' ELSE wire_nlO01OOOO_dataout; + wire_nlO01O1lO_dataout <= nlO0iO01O WHEN niOiOOi1l = '1' ELSE wire_nlO00111i_dataout; + wire_nlO01O1O_dataout <= nllO001O WHEN niOO000Oi = '1' ELSE wire_nlO00liO_dataout; + wire_nlO01O1Oi_dataout <= nlO0iO00i WHEN niOiOOi1l = '1' ELSE wire_nlO00111l_dataout; + wire_nlO01O1Ol_dataout <= nlO0iO00l WHEN niOiOOi1l = '1' ELSE wire_nlO00111O_dataout; + wire_nlO01O1OO_dataout <= nlO0iO00O WHEN niOiOOi1l = '1' ELSE wire_nlO00110i_dataout; + wire_nlO01Oi0i_dataout <= nlO0iOili WHEN niOiOOi1l = '1' ELSE wire_nlO0010il_dataout; + wire_nlO01Oi0l_dataout <= nlO0iOill WHEN niOiOOi1l = '1' ELSE wire_nlO0010iO_dataout; + wire_nlO01Oi0O_dataout <= nlO0iOilO WHEN niOiOOi1l = '1' ELSE wire_nlO0010li_dataout; + wire_nlO01Oi1i_dataout <= nlO0iOiii WHEN niOiOOi1l = '1' ELSE wire_nlO00100l_dataout; + wire_nlO01Oi1l_dataout <= nlO0iOiil WHEN niOiOOi1l = '1' ELSE wire_nlO00100O_dataout; + wire_nlO01Oi1O_dataout <= nlO0iOiiO WHEN niOiOOi1l = '1' ELSE wire_nlO0010ii_dataout; + wire_nlO01Oii_dataout <= nllO00ii WHEN niOO000Oi = '1' ELSE wire_nlO00lOi_dataout; + wire_nlO01Oiii_dataout <= nlO0iOiOi WHEN niOiOOi1l = '1' ELSE wire_nlO0010ll_dataout; + wire_nlO01Oiil_dataout <= nlO0iOiOl WHEN niOiOOi1l = '1' ELSE wire_nlO0010lO_dataout; + wire_nlO01OiiO_dataout <= nlO0ili1l WHEN niOiOOi1l = '1' ELSE wire_nlO0010Oi_dataout; + wire_nlO01Oil_dataout <= nllO00il WHEN niOO000Oi = '1' ELSE wire_nlO00lOl_dataout; + wire_nlO01Oili_dataout <= nlO0ili1O WHEN niOiOOi1l = '1' ELSE wire_nlO0010Ol_dataout; + wire_nlO01Oill_dataout <= nlO0ili0i WHEN niOiOOi1l = '1' ELSE wire_nlO0010OO_dataout; + wire_nlO01OilO_dataout <= nlO0ili0l WHEN niOiOOi1l = '1' ELSE wire_nlO001i1i_dataout; + wire_nlO01OiO_dataout <= nllO00iO WHEN niOO000Oi = '1' ELSE wire_nlO00lOO_dataout; + wire_nlO01OiOi_dataout <= nlO0ili0O WHEN niOiOOi1l = '1' ELSE wire_nlO001i1l_dataout; + wire_nlO01OiOl_dataout <= nlO0iliii WHEN niOiOOi1l = '1' ELSE wire_nlO001i1O_dataout; + wire_nlO01OiOO_dataout <= nlO0iliil WHEN niOiOOi1l = '1' ELSE wire_nlO001i0i_dataout; + wire_nlO01Ol0i_dataout <= nlO0ililO WHEN niOiOOi1l = '1' ELSE wire_nlO001iil_dataout; + wire_nlO01Ol0l_dataout <= nlO0iliOi WHEN niOiOOi1l = '1' ELSE wire_nlO001iiO_dataout; + wire_nlO01Ol0O_dataout <= nlO0iliOl WHEN niOiOOi1l = '1' ELSE wire_nlO001ili_dataout; + wire_nlO01Ol1i_dataout <= nlO0iliiO WHEN niOiOOi1l = '1' ELSE wire_nlO001i0l_dataout; + wire_nlO01Ol1l_dataout <= nlO0ilili WHEN niOiOOi1l = '1' ELSE wire_nlO001i0O_dataout; + wire_nlO01Ol1O_dataout <= nlO0ilill WHEN niOiOOi1l = '1' ELSE wire_nlO001iii_dataout; + wire_nlO01Oli_dataout <= nllO00li WHEN niOO000Oi = '1' ELSE wire_nlO00O1i_dataout; + wire_nlO01Olii_dataout <= nlO0iliOO WHEN niOiOOi1l = '1' ELSE wire_nlO001ill_dataout; + wire_nlO01Olil_dataout <= nlO0ill1i WHEN niOiOOi1l = '1' ELSE wire_nlO001ilO_dataout; + wire_nlO01OliO_dataout <= nlO0ill1l WHEN niOiOOi1l = '1' ELSE wire_nlO001iOi_dataout; + wire_nlO01Oll_dataout <= nllO00ll WHEN niOO000Oi = '1' ELSE wire_nlO00O1l_dataout; + wire_nlO01Olli_dataout <= nlO0ill1O WHEN niOiOOi1l = '1' ELSE wire_nlO001iOl_dataout; + wire_nlO01Olll_dataout <= nlO0ill0i WHEN niOiOOi1l = '1' ELSE wire_nlO001iOO_dataout; + wire_nlO01OllO_dataout <= nlO0ill0l WHEN niOiOOi1l = '1' ELSE wire_nlO001l1i_dataout; + wire_nlO01OlO_dataout <= nllO00lO WHEN niOO000Oi = '1' ELSE wire_nlO00O1O_dataout; + wire_nlO01OlOi_dataout <= nlO0ill0O WHEN niOiOOi1l = '1' ELSE wire_nlO001l1l_dataout; + wire_nlO01OlOl_dataout <= nlO0illii WHEN niOiOOi1l = '1' ELSE wire_nlO001l1O_dataout; + wire_nlO01OlOO_dataout <= nlO0illil WHEN niOiOOi1l = '1' ELSE wire_nlO001l0i_dataout; + wire_nlO01OO0i_dataout <= niOiOOlii WHEN niOiOOi1i = '1' ELSE wire_nlO001lil_dataout; + wire_nlO01OO0l_dataout <= niOiOOl0l WHEN niOiOOi1i = '1' ELSE wire_nlO001lli_dataout; + wire_nlO01OO0O_dataout <= niOiOOl1O WHEN niOiOOi1i = '1' ELSE wire_nlO001liO_dataout; + wire_nlO01OO1i_dataout <= nlO0illiO WHEN niOiOOi1l = '1' ELSE wire_nlO001l0l_dataout; + wire_nlO01OO1l_dataout <= nlO0illli WHEN niOiOOi1l = '1' ELSE wire_nlO001l0O_dataout; + wire_nlO01OO1O_dataout <= niOiOOliO WHEN niOiOOi1i = '1' ELSE wire_nlO001lii_dataout; + wire_nlO01OOi_dataout <= nllO00Oi WHEN niOO000Oi = '1' ELSE wire_nlO00O0i_dataout; + wire_nlO01OOii_dataout <= niOiOOl1i WHEN niOiOOi1i = '1' ELSE wire_nlO001lli_dataout; + wire_nlO01OOil_dataout <= niOiOOiOl WHEN niOiOOi1i = '1' ELSE wire_nlO001lli_dataout; + wire_nlO01OOiO_dataout <= niOiOOilO WHEN niOiOOi1i = '1' ELSE wire_nlO001lli_dataout; + wire_nlO01OOl_dataout <= nllO00Ol WHEN niOO000Oi = '1' ELSE wire_nlO00O0l_dataout; + wire_nlO01OOli_dataout <= niOiOOili WHEN niOiOOi1i = '1' ELSE wire_nlO001lli_dataout; + wire_nlO01OOll_dataout <= wire_nl1000i_w_lg_nlO1lOilO29455w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001lll_dataout; + wire_nlO01OOlO_dataout <= wire_nl1000i_w_lg_nlO1lOill29454w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001llO_dataout; + wire_nlO01OOO_dataout <= nllO00OO WHEN niOO000Oi = '1' ELSE wire_nlO00O0O_dataout; + wire_nlO01OOOi_dataout <= wire_nl1000i_w_lg_nlO1lOili29453w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001lOi_dataout; + wire_nlO01OOOl_dataout <= wire_nl1000i_w_lg_nlO1lOiiO29452w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001lOl_dataout; + wire_nlO01OOOO_dataout <= wire_nl1000i_w_lg_nlO1lOiil29451w(0) WHEN niOiOOi1i = '1' ELSE wire_nlO001lOO_dataout; + wire_nlO0i000i_dataout <= wire_nl1000i_w_lg_nlO1lOiOi29440w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0Oi; + wire_nlO0i000l_dataout <= wire_nl1000i_w_lg_nlO1lOlOi29439w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0Ol; + wire_nlO0i000O_dataout <= wire_nl1000i_w_lg_nlO1lOllO29438w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0OO; + wire_nlO0i001i_dataout <= wire_nl1000i_w_lg_nlO1lOl1i29443w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0li; + wire_nlO0i001l_dataout <= wire_nl1000i_w_lg_nlO1lOiOO29442w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0ll; + wire_nlO0i001O_dataout <= wire_nl1000i_w_lg_nlO1lOiOl29441w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0lO; + wire_nlO0i00i_dataout <= wire_nlll0lli_q(87) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1iO_dataout; + wire_nlO0i00ii_dataout <= wire_nl1000i_w_lg_nlO1lOlll29437w(0) WHEN niOl11l1l = '1' ELSE nlO0iOi1i; + wire_nlO0i00il_dataout <= wire_nl1000i_w_lg_nlO1lOlli29436w(0) WHEN niOl11l1l = '1' ELSE nlO0iOi1l; + wire_nlO0i00iO_dataout <= wire_nl1000i_w_lg_nlO1lOliO29435w(0) WHEN niOl11l1l = '1' ELSE nlO0iOi1O; + wire_nlO0i00l_dataout <= wire_nlll0lli_q(88) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1li_dataout; + wire_nlO0i00li_dataout <= wire_nl1000i_w_lg_nlO1lOlil29434w(0) WHEN niOl11l1l = '1' ELSE nlO0iOi0i; + wire_nlO0i00ll_dataout <= wire_nl1000i_w_lg_nlO1lOlii29433w(0) WHEN niOl11l1l = '1' ELSE nlO0iOi0l; + wire_nlO0i00lO_dataout <= wire_nl1000i_w_lg_nlO1lOl0O29432w(0) WHEN niOl11l1l = '1' ELSE nlO0iOi0O; + wire_nlO0i00O_dataout <= wire_nlll0lli_q(89) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1ll_dataout; + wire_nlO0i00Oi_dataout <= wire_nl1000i_w_lg_nlO1lOO0O29431w(0) WHEN niOl11l1l = '1' ELSE nlO0iOiii; + wire_nlO0i00Ol_dataout <= wire_nl1000i_w_lg_nlO1lOO0l29430w(0) WHEN niOl11l1l = '1' ELSE nlO0iOiil; + wire_nlO0i00OO_dataout <= wire_nl1000i_w_lg_nlO1lOO0i29429w(0) WHEN niOl11l1l = '1' ELSE nlO0iOiiO; + wire_nlO0i010i_dataout <= wire_nl1000i_w_lg_nlO1lOilO29455w(0) WHEN niOl11l1l = '1' ELSE nlO0iO1Oi; + wire_nlO0i010l_dataout <= wire_nl1000i_w_lg_nlO1lOill29454w(0) WHEN niOl11l1l = '1' ELSE nlO0iO1Ol; + wire_nlO0i010O_dataout <= wire_nl1000i_w_lg_nlO1lOili29453w(0) WHEN niOl11l1l = '1' ELSE nlO0iO1OO; + wire_nlO0i011i_dataout <= wire_w_lg_niOl11iOi29459w(0) WHEN niOl11iOO = '1' ELSE nlO0iO1ll; + wire_nlO0i011l_dataout <= wire_w_lg_niOl11iOl29458w(0) WHEN niOl11iOO = '1' ELSE nlO0iO1lO; + wire_nlO0i01i_dataout <= wire_nlll0lli_q(84) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l10O_dataout; + wire_nlO0i01ii_dataout <= wire_nl1000i_w_lg_nlO1lOiiO29452w(0) WHEN niOl11l1l = '1' ELSE nlO0iO01i; + wire_nlO0i01il_dataout <= wire_nl1000i_w_lg_nlO1lOiil29451w(0) WHEN niOl11l1l = '1' ELSE nlO0iO01l; + wire_nlO0i01iO_dataout <= wire_nl1000i_w_lg_nlO1lOiii29450w(0) WHEN niOl11l1l = '1' ELSE nlO0iO01O; + wire_nlO0i01l_dataout <= wire_nlll0lli_q(85) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1ii_dataout; + wire_nlO0i01li_dataout <= wire_nl1000i_w_lg_nlO1lOi0O29449w(0) WHEN niOl11l1l = '1' ELSE nlO0iO00i; + wire_nlO0i01ll_dataout <= wire_nl1000i_w_lg_nlO1O0l1i29448w(0) WHEN niOl11l1l = '1' ELSE nlO0iO00l; + wire_nlO0i01lO_dataout <= wire_nl1000i_w_lg_nlO1lOl0l29447w(0) WHEN niOl11l1l = '1' ELSE nlO0iO00O; + wire_nlO0i01O_dataout <= wire_nlll0lli_q(86) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1il_dataout; + wire_nlO0i01Oi_dataout <= wire_nl1000i_w_lg_nlO1lOl0i29446w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0ii; + wire_nlO0i01Ol_dataout <= wire_nl1000i_w_lg_nlO1lOl1O29445w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0il; + wire_nlO0i01OO_dataout <= wire_nl1000i_w_lg_nlO1lOl1l29444w(0) WHEN niOl11l1l = '1' ELSE nlO0iO0iO; + wire_nlO0i0i0i_dataout <= wire_nl1000i_w_lg_nlO1lOlOO29425w(0) WHEN niOl11l1l = '1' ELSE nlO0iOiOi; + wire_nlO0i0i0l_dataout <= wire_nl1000i_w_lg_nlO1lOlOl29424w(0) WHEN niOl11l1l = '1' ELSE nlO0iOiOl; + wire_nlO0i0i1i_dataout <= wire_nl1000i_w_lg_nlO1lOO1O29428w(0) WHEN niOl11l1l = '1' ELSE nlO0iOili; + wire_nlO0i0i1l_dataout <= wire_nl1000i_w_lg_nlO1lOO1l29427w(0) WHEN niOl11l1l = '1' ELSE nlO0iOill; + wire_nlO0i0i1O_dataout <= wire_nl1000i_w_lg_nlO1lOO1i29426w(0) WHEN niOl11l1l = '1' ELSE nlO0iOilO; + wire_nlO0i0ii_dataout <= wire_nlll0lli_q(90) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1lO_dataout; + wire_nlO0i0il_dataout <= wire_nlll0lli_q(91) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1Oi_dataout; + wire_nlO0i0iO_dataout <= wire_nlll0lli_q(92) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1Ol_dataout; + wire_nlO0i0li_dataout <= wire_nlll0lli_q(93) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l1OO_dataout; + wire_nlO0i0ll_dataout <= wire_nlll0lli_q(94) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l01i_dataout; + wire_nlO0i0lO_dataout <= wire_nlll0lli_q(95) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l01l_dataout; + wire_nlO0i0Oi_dataout <= wire_nlll0lli_q(96) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l01O_dataout; + wire_nlO0i0Ol_dataout <= wire_nlll0lli_q(97) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l00i_dataout; + wire_nlO0i0OO_dataout <= wire_nlll0lli_q(98) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l00l_dataout; + wire_nlO0i10i_dataout <= wire_nlll0lli_q(72) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOiO_dataout; + wire_nlO0i10l_dataout <= wire_nlll0lli_q(73) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOli_dataout; + wire_nlO0i10O_dataout <= wire_nlll0lli_q(74) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOll_dataout; + wire_nlO0i111i_dataout <= nlO00lOOO AND NOT(niOiOOiiO); + wire_nlO0i111l_dataout <= nlO00O11i OR niOiOOiiO; + wire_nlO0i111O_dataout <= nlO00O11l AND NOT(niOiOOiiO); + wire_nlO0i11i_dataout <= wire_nlll0lli_q(69) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iO0O_dataout; + wire_nlO0i11l_dataout <= wire_nlll0lli_q(70) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOii_dataout; + wire_nlO0i11O_dataout <= wire_nlll0lli_q(71) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOil_dataout; + wire_nlO0i1ii_dataout <= wire_nlll0lli_q(75) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOlO_dataout; + wire_nlO0i1il_dataout <= wire_nlll0lli_q(76) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOOi_dataout; + wire_nlO0i1iO_dataout <= wire_nlll0lli_q(77) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOOl_dataout; + wire_nlO0i1l0i_dataout <= wire_w_lg_niOl1101i29486w(0) WHEN niOl11iOO = '1' ELSE nlO0illOl; + wire_nlO0i1l0l_dataout <= wire_w_lg_niOl1101l29485w(0) WHEN niOl11iOO = '1' ELSE nlO0illOO; + wire_nlO0i1l0O_dataout <= wire_w_lg_niOl1101O29484w(0) WHEN niOl11iOO = '1' ELSE nlO0ilO1i; + wire_nlO0i1l1i_dataout <= wire_w_lg_niOl111Oi29489w(0) WHEN niOl11iOO = '1' ELSE nlO0illll; + wire_nlO0i1l1l_dataout <= wire_w_lg_niOl111Ol29488w(0) WHEN niOl11iOO = '1' ELSE nlO0illlO; + wire_nlO0i1l1O_dataout <= wire_w_lg_niOl111OO29487w(0) WHEN niOl11iOO = '1' ELSE nlO0illOi; + wire_nlO0i1li_dataout <= wire_nlll0lli_q(78) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0iOOO_dataout; + wire_nlO0i1lii_dataout <= wire_w_lg_niOl1100i29483w(0) WHEN niOl11iOO = '1' ELSE nlO0ilO1l; + wire_nlO0i1lil_dataout <= wire_w_lg_niOl1100l29482w(0) WHEN niOl11iOO = '1' ELSE nlO0ilO1O; + wire_nlO0i1liO_dataout <= wire_w_lg_niOl1100O29481w(0) WHEN niOl11iOO = '1' ELSE nlO0ilO0i; + wire_nlO0i1ll_dataout <= wire_nlll0lli_q(79) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l11i_dataout; + wire_nlO0i1lli_dataout <= wire_w_lg_niOl110ii29480w(0) WHEN niOl11iOO = '1' ELSE nlO0ilO0l; + wire_nlO0i1lll_dataout <= wire_w_lg_niOl110il29479w(0) WHEN niOl11iOO = '1' ELSE nlO0ilO0O; + wire_nlO0i1llO_dataout <= wire_w_lg_niOl110iO29478w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOii; + wire_nlO0i1lO_dataout <= wire_nlll0lli_q(80) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l11l_dataout; + wire_nlO0i1lOi_dataout <= wire_w_lg_niOl110li29477w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOil; + wire_nlO0i1lOl_dataout <= wire_w_lg_niOl110ll29476w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOiO; + wire_nlO0i1lOO_dataout <= wire_w_lg_niOl110lO29475w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOli; + wire_nlO0i1O0i_dataout <= wire_w_lg_niOl11i1i29471w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOOl; + wire_nlO0i1O0l_dataout <= wire_w_lg_niOl11i1l29470w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOOO; + wire_nlO0i1O0O_dataout <= wire_w_lg_niOl11i1O29469w(0) WHEN niOl11iOO = '1' ELSE nlO0iO11i; + wire_nlO0i1O1i_dataout <= wire_w_lg_niOl110Oi29474w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOll; + wire_nlO0i1O1l_dataout <= wire_w_lg_niOl110Ol29473w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOlO; + wire_nlO0i1O1O_dataout <= wire_w_lg_niOl110OO29472w(0) WHEN niOl11iOO = '1' ELSE nlO0ilOOi; + wire_nlO0i1Oi_dataout <= wire_nlll0lli_q(81) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l11O_dataout; + wire_nlO0i1Oii_dataout <= wire_w_lg_niOl11i0i29468w(0) WHEN niOl11iOO = '1' ELSE nlO0iO11l; + wire_nlO0i1Oil_dataout <= wire_w_lg_niOl11i0l29467w(0) WHEN niOl11iOO = '1' ELSE nlO0iO11O; + wire_nlO0i1OiO_dataout <= wire_w_lg_niOl11i0O29466w(0) WHEN niOl11iOO = '1' ELSE nlO0iO10i; + wire_nlO0i1Ol_dataout <= wire_nlll0lli_q(82) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l10i_dataout; + wire_nlO0i1Oli_dataout <= wire_w_lg_niOl11iii29465w(0) WHEN niOl11iOO = '1' ELSE nlO0iO10l; + wire_nlO0i1Oll_dataout <= wire_w_lg_niOl11iil29464w(0) WHEN niOl11iOO = '1' ELSE nlO0iO10O; + wire_nlO0i1OlO_dataout <= wire_w_lg_niOl11iiO29463w(0) WHEN niOl11iOO = '1' ELSE nlO0iO1ii; + wire_nlO0i1OO_dataout <= wire_nlll0lli_q(83) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l10l_dataout; + wire_nlO0i1OOi_dataout <= wire_w_lg_niOl11ili29462w(0) WHEN niOl11iOO = '1' ELSE nlO0iO1il; + wire_nlO0i1OOl_dataout <= wire_w_lg_niOl11ill29461w(0) WHEN niOl11iOO = '1' ELSE nlO0iO1iO; + wire_nlO0i1OOO_dataout <= wire_w_lg_niOl11ilO29460w(0) WHEN niOl11iOO = '1' ELSE nlO0iO1li; + wire_nlO0ii0i_dataout <= wire_nlll0lli_q(102) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0iO_dataout; + wire_nlO0ii0l_dataout <= wire_nlll0lli_q(103) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0li_dataout; + wire_nlO0ii0O_dataout <= wire_nlll0lli_q(104) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0ll_dataout; + wire_nlO0ii1i_dataout <= wire_nlll0lli_q(99) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l00O_dataout; + wire_nlO0ii1l_dataout <= wire_nlll0lli_q(100) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0ii_dataout; + wire_nlO0ii1O_dataout <= wire_nlll0lli_q(101) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0il_dataout; + wire_nlO0iiii_dataout <= wire_nlll0lli_q(105) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0lO_dataout; + wire_nlO0iiil_dataout <= wire_nlll0lli_q(106) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0Oi_dataout; + wire_nlO0iiiO_dataout <= wire_nlll0lli_q(107) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0Ol_dataout; + wire_nlO0iili_dataout <= wire_nlll0lli_q(108) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0l0OO_dataout; + wire_nlO0iill_dataout <= wire_nlll0lli_q(109) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0li1i_dataout; + wire_nlO0iilO_dataout <= wire_nlll0lli_q(110) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0li1l_dataout; + wire_nlO0iiOi_dataout <= wire_nlll0lli_q(111) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0li1O_dataout; + wire_nlO0iiOl_dataout <= wire_nlll0lli_q(112) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0li0i_dataout; + wire_nlO0iiOO_dataout <= wire_nlll0lli_q(113) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0li0l_dataout; + wire_nlO0il0i_dataout <= wire_nlll0lli_q(117) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0liiO_dataout; + wire_nlO0il0l_dataout <= wire_nlll0lli_q(118) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0lili_dataout; + wire_nlO0il0O_dataout <= wire_nlll0lli_q(119) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0lill_dataout; + wire_nlO0il1i_dataout <= wire_nlll0lli_q(114) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0li0O_dataout; + wire_nlO0il1l_dataout <= wire_nlll0lli_q(115) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0liii_dataout; + wire_nlO0il1O_dataout <= wire_nlll0lli_q(116) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0liil_dataout; + wire_nlO0ilii_dataout <= wire_nlll0lli_q(120) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0lilO_dataout; + wire_nlO0ilil_dataout <= wire_nlll0lli_q(121) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0liOi_dataout; + wire_nlO0iliO_dataout <= wire_nlll0lli_q(122) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0liOl_dataout; + wire_nlO0illi_dataout <= wire_nlll0lli_q(123) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0liOO_dataout; + wire_nlO0illl_dataout <= wire_nlll0lli_q(124) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0ll1i_dataout; + wire_nlO0illO_dataout <= wire_nlll0lli_q(125) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0ll1l_dataout; + wire_nlO0ilOi_dataout <= wire_nlll0lli_q(126) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0ll1O_dataout; + wire_nlO0ilOl_dataout <= wire_nlll0lli_q(127) WHEN wire_nlll0lli_q(131) = '1' ELSE wire_nlO0ll0i_dataout; + wire_nlO0ilOO_dataout <= wire_nlO0ll0l_dataout OR wire_nlll0lli_q(131); + wire_nlO0iO0i_dataout <= wire_nlll0lli_q(3) WHEN niOO0001l = '1' ELSE nllO1l1l; + wire_nlO0iO0l_dataout <= wire_nlll0lli_q(4) WHEN niOO0001l = '1' ELSE nllO1l1O; + wire_nlO0iO0O_dataout <= wire_nlll0lli_q(5) WHEN niOO0001l = '1' ELSE nllO1l0i; + wire_nlO0iO1i_dataout <= wire_nlll0lli_q(0) WHEN niOO0001l = '1' ELSE nllO1iOl; + wire_nlO0iO1l_dataout <= wire_nlll0lli_q(1) WHEN niOO0001l = '1' ELSE nllO1iOO; + wire_nlO0iO1O_dataout <= wire_nlll0lli_q(2) WHEN niOO0001l = '1' ELSE nllO1l1i; + wire_nlO0iOii_dataout <= wire_nlll0lli_q(6) WHEN niOO0001l = '1' ELSE nllO1l0l; + wire_nlO0iOil_dataout <= wire_nlll0lli_q(7) WHEN niOO0001l = '1' ELSE nllO1l0O; + wire_nlO0iOiO_dataout <= wire_nlll0lli_q(8) WHEN niOO0001l = '1' ELSE nllO1lii; + wire_nlO0iOl0i_dataout <= wire_nlO0l011l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOl0l_dataout <= wire_nlO0l011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOl0O_dataout <= wire_nlO0l010i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOl1i_dataout <= wire_nlO0l1OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOl1l_dataout <= wire_nlO0l011i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOl1O_dataout <= wire_nlO0l1OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOli_dataout <= wire_nlll0lli_q(9) WHEN niOO0001l = '1' ELSE nllO1lil; + wire_nlO0iOlii_dataout <= wire_nlO0l010l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOlil_dataout <= wire_nlO0l010O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOliO_dataout <= wire_nlO0l01ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOll_dataout <= wire_nlll0lli_q(10) WHEN niOO0001l = '1' ELSE nllO1liO; + wire_nlO0iOlli_dataout <= wire_nlO0l01il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOlll_dataout <= wire_nlO0l01iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOllO_dataout <= wire_nlO0l01li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOlO_dataout <= wire_nlll0lli_q(11) WHEN niOO0001l = '1' ELSE nllO1lli; + wire_nlO0iOlOi_dataout <= wire_nlO0l01ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOlOl_dataout <= wire_nlO0l01lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOlOO_dataout <= wire_nlO0l01Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOO0i_dataout <= wire_nlO0l001l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOO0l_dataout <= wire_nlO0l001O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOO0O_dataout <= wire_nlO0l000i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOO1i_dataout <= wire_nlO0l01Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOO1l_dataout <= wire_nlO0l01OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOO1O_dataout <= wire_nlO0l001i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOi_dataout <= wire_nlll0lli_q(12) WHEN niOO0001l = '1' ELSE nllO1lll; + wire_nlO0iOOii_dataout <= wire_nlO0l000l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOil_dataout <= wire_nlO0l000O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOiO_dataout <= wire_nlO0l00ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOl_dataout <= wire_nlll0lli_q(13) WHEN niOO0001l = '1' ELSE nllO1llO; + wire_nlO0iOOli_dataout <= wire_nlO0l00il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOll_dataout <= wire_nlO0l00iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOlO_dataout <= wire_nlO0l00li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOO_dataout <= wire_nlll0lli_q(14) WHEN niOO0001l = '1' ELSE nllO1lOi; + wire_nlO0iOOOi_dataout <= wire_nlO0l00ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOOl_dataout <= wire_nlO0l00lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0iOOOO_dataout <= wire_nlO0l00Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l000i_dataout <= nlO0ilO1i WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iliii; + wire_nlO0l000l_dataout <= nlO0ilO1l WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iliil; + wire_nlO0l000O_dataout <= nlO0ilO1O WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iliiO; + wire_nlO0l001i_dataout <= nlO0illOi WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ili0i; + wire_nlO0l001l_dataout <= nlO0illOl WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ili0l; + wire_nlO0l001O_dataout <= nlO0illOO WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ili0O; + wire_nlO0l00i_dataout <= wire_nlll0lli_q(33) WHEN niOO0001l = '1' ELSE nllO011l; + wire_nlO0l00ii_dataout <= nlO0ilO0i WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilili; + wire_nlO0l00il_dataout <= nlO0ilO0l WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilill; + wire_nlO0l00iO_dataout <= nlO0ilO0O WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ililO; + wire_nlO0l00l_dataout <= wire_nlll0lli_q(34) WHEN niOO0001l = '1' ELSE nllO011O; + wire_nlO0l00li_dataout <= nlO0ilOii WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iliOi; + wire_nlO0l00ll_dataout <= nlO0ilOil WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iliOl; + wire_nlO0l00lO_dataout <= nlO0ilOiO WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iliOO; + wire_nlO0l00O_dataout <= wire_nlll0lli_q(35) WHEN niOO0001l = '1' ELSE nllO010i; + wire_nlO0l00Oi_dataout <= nlO0ilOli WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ill1i; + wire_nlO0l00Ol_dataout <= nlO0ilOll WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ill1l; + wire_nlO0l00OO_dataout <= nlO0ilOlO WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ill1O; + wire_nlO0l010i_dataout <= wire_nlO0Ol1li_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0ii; + wire_nlO0l010l_dataout <= wire_nlO0Ol1ll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0il; + wire_nlO0l010O_dataout <= wire_nlO0Ol1lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0iO; + wire_nlO0l011i_dataout <= wire_nlO0O000l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il01O; + wire_nlO0l011l_dataout <= wire_nlO0Ol1il_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il00l; + wire_nlO0l011O_dataout <= wire_nlO0Ol1iO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il00O; + wire_nlO0l01i_dataout <= wire_nlll0lli_q(30) WHEN niOO0001l = '1' ELSE nllO1OOl; + wire_nlO0l01ii_dataout <= wire_nlO0Ol1Oi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0li; + wire_nlO0l01il_dataout <= wire_nlO0Ol1Ol_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0ll; + wire_nlO0l01iO_dataout <= wire_nlO0Ol1OO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0lO; + wire_nlO0l01l_dataout <= wire_nlll0lli_q(31) WHEN niOO0001l = '1' ELSE nllO1OOO; + wire_nlO0l01li_dataout <= wire_nlO0Ol01i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0Oi; + wire_nlO0l01ll_dataout <= wire_nlO0Ol01l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0Ol; + wire_nlO0l01lO_dataout <= wire_nlO0Ol01O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il0OO; + wire_nlO0l01O_dataout <= wire_nlll0lli_q(32) WHEN niOO0001l = '1' ELSE nllO011i; + wire_nlO0l01Oi_dataout <= wire_nlO0Ol00i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ili1i; + wire_nlO0l01Ol_dataout <= nlO0illll WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ili1l; + wire_nlO0l01OO_dataout <= nlO0illlO WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ili1O; + wire_nlO0l0i0i_dataout <= nlO0iO11i WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illii; + wire_nlO0l0i0l_dataout <= nlO0iO11l WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illil; + wire_nlO0l0i0O_dataout <= nlO0iO11O WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illiO; + wire_nlO0l0i1i_dataout <= nlO0ilOOi WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ill0i; + wire_nlO0l0i1l_dataout <= nlO0ilOOl WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ill0l; + wire_nlO0l0i1O_dataout <= nlO0ilOOO WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ill0O; + wire_nlO0l0ii_dataout <= wire_nlll0lli_q(36) WHEN niOO0001l = '1' ELSE nllO010l; + wire_nlO0l0iii_dataout <= nlO0iO10i WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illli; + wire_nlO0l0iil_dataout <= wire_nlO0O00ll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illll; + wire_nlO0l0iiO_dataout <= wire_nlO0O00lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illlO; + wire_nlO0l0il_dataout <= wire_nlll0lli_q(37) WHEN niOO0001l = '1' ELSE nllO010O; + wire_nlO0l0ili_dataout <= wire_nlO0O00Oi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illOi; + wire_nlO0l0ill_dataout <= wire_nlO0O00Ol_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illOl; + wire_nlO0l0ilO_dataout <= wire_nlO0O00OO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0illOO; + wire_nlO0l0iO_dataout <= wire_nlll0lli_q(38) WHEN niOO0001l = '1' ELSE nllO01ii; + wire_nlO0l0iOi_dataout <= wire_nlO0O0i1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilO1i; + wire_nlO0l0iOl_dataout <= wire_nlO0O0i1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilO1l; + wire_nlO0l0iOO_dataout <= wire_nlO0O0i1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilO1O; + wire_nlO0l0l0i_dataout <= wire_nlO0O0iii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOii; + wire_nlO0l0l0l_dataout <= wire_nlO0O0iil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOil; + wire_nlO0l0l0O_dataout <= wire_nlO0O0iiO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOiO; + wire_nlO0l0l1i_dataout <= wire_nlO0O0i0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilO0i; + wire_nlO0l0l1l_dataout <= wire_nlO0O0i0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilO0l; + wire_nlO0l0l1O_dataout <= wire_nlO0O0i0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilO0O; + wire_nlO0l0li_dataout <= wire_nlll0lli_q(39) WHEN niOO0001l = '1' ELSE nllO01il; + wire_nlO0l0lii_dataout <= wire_nlO0O0ili_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOli; + wire_nlO0l0lil_dataout <= wire_nlO0O0ill_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOll; + wire_nlO0l0liO_dataout <= wire_nlO0O0ilO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOlO; + wire_nlO0l0ll_dataout <= wire_nlll0lli_q(40) WHEN niOO0001l = '1' ELSE nllO01iO; + wire_nlO0l0lli_dataout <= wire_nlO0O0iOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOOi; + wire_nlO0l0lll_dataout <= wire_nlO0O0iOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOOl; + wire_nlO0l0llO_dataout <= wire_nlO0O0iOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0ilOOO; + wire_nlO0l0lO_dataout <= wire_nlll0lli_q(41) WHEN niOO0001l = '1' ELSE nllO01li; + wire_nlO0l0lOi_dataout <= wire_nlO0O0l1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO11i; + wire_nlO0l0lOl_dataout <= wire_nlO0O0l1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO11l; + wire_nlO0l0lOO_dataout <= wire_nlO0O0l1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO11O; + wire_nlO0l0O0i_dataout <= wire_nlO0O0lii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1ii; + wire_nlO0l0O0l_dataout <= wire_nlO0O0lil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1il; + wire_nlO0l0O0O_dataout <= wire_nlO0O0liO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1iO; + wire_nlO0l0O1i_dataout <= wire_nlO0O0l0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO10i; + wire_nlO0l0O1l_dataout <= wire_nlO0O0l0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO10l; + wire_nlO0l0O1O_dataout <= wire_nlO0O0l0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO10O; + wire_nlO0l0Oi_dataout <= wire_nlll0lli_q(42) WHEN niOO0001l = '1' ELSE nllO01ll; + wire_nlO0l0Oii_dataout <= wire_nlO0O0lli_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1li; + wire_nlO0l0Oil_dataout <= wire_nlO0O0lll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1ll; + wire_nlO0l0OiO_dataout <= wire_nlO0O0llO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1lO; + wire_nlO0l0Ol_dataout <= wire_nlll0lli_q(43) WHEN niOO0001l = '1' ELSE nllO01lO; + wire_nlO0l0Oli_dataout <= wire_nlO0O0lOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1Oi; + wire_nlO0l0Oll_dataout <= wire_nlO0O0lOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1Ol; + wire_nlO0l0OlO_dataout <= wire_nlO0O0lOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO1OO; + wire_nlO0l0OO_dataout <= wire_nlll0lli_q(44) WHEN niOO0001l = '1' ELSE nllO01Oi; + wire_nlO0l0OOi_dataout <= wire_nlO0O0O1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO01i; + wire_nlO0l0OOl_dataout <= wire_nlO0O0O1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO01l; + wire_nlO0l0OOO_dataout <= wire_nlO0O0O1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO01O; + wire_nlO0l100i_dataout <= wire_nlO0l0l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l100l_dataout <= wire_nlO0l0l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l100O_dataout <= wire_nlO0l0l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l101i_dataout <= wire_nlO0l0iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l101l_dataout <= wire_nlO0l0iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l101O_dataout <= wire_nlO0l0l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10i_dataout <= wire_nlll0lli_q(18) WHEN niOO0001l = '1' ELSE nllO1O1l; + wire_nlO0l10ii_dataout <= wire_nlO0l0l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10il_dataout <= wire_nlO0l0l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10iO_dataout <= wire_nlO0l0lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10l_dataout <= wire_nlll0lli_q(19) WHEN niOO0001l = '1' ELSE nllO1O1O; + wire_nlO0l10li_dataout <= wire_nlO0l0lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10ll_dataout <= wire_nlO0l0liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10lO_dataout <= wire_nlO0l0lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10O_dataout <= wire_nlll0lli_q(20) WHEN niOO0001l = '1' ELSE nllO1O0i; + wire_nlO0l10Oi_dataout <= wire_nlO0l0lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10Ol_dataout <= wire_nlO0l0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l10OO_dataout <= wire_nlO0l0lOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l110i_dataout <= wire_nlO0l0i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l110l_dataout <= wire_nlO0l0i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l110O_dataout <= wire_nlO0l0i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l111i_dataout <= wire_nlO0l00Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l111l_dataout <= wire_nlO0l00OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l111O_dataout <= wire_nlO0l0i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11i_dataout <= wire_nlll0lli_q(15) WHEN niOO0001l = '1' ELSE nllO1lOl; + wire_nlO0l11ii_dataout <= wire_nlO0l0i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11il_dataout <= wire_nlO0l0i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11iO_dataout <= wire_nlO0l0iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11l_dataout <= wire_nlll0lli_q(16) WHEN niOO0001l = '1' ELSE nllO1lOO; + wire_nlO0l11li_dataout <= wire_nlO0l0iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11ll_dataout <= wire_nlO0l0iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11lO_dataout <= wire_nlO0l0ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11O_dataout <= wire_nlll0lli_q(17) WHEN niOO0001l = '1' ELSE nllO1O1i; + wire_nlO0l11Oi_dataout <= wire_nlO0l0ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11Ol_dataout <= wire_nlO0l0ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l11OO_dataout <= wire_nlO0l0iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1i0i_dataout <= wire_nlO0l0O1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1i0l_dataout <= wire_nlO0l0O1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1i0O_dataout <= wire_nlO0l0O0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1i1i_dataout <= wire_nlO0l0lOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1i1l_dataout <= wire_nlO0l0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1i1O_dataout <= wire_nlO0l0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1ii_dataout <= wire_nlll0lli_q(21) WHEN niOO0001l = '1' ELSE nllO1O0l; + wire_nlO0l1iii_dataout <= wire_nlO0l0O0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1iil_dataout <= wire_nlO0l0O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1iiO_dataout <= wire_nlO0l0Oii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1il_dataout <= wire_nlll0lli_q(22) WHEN niOO0001l = '1' ELSE nllO1O0O; + wire_nlO0l1ili_dataout <= wire_nlO0l0Oil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1ill_dataout <= wire_nlO0l0OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1ilO_dataout <= wire_nlO0l0Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1iO_dataout <= wire_nlll0lli_q(23) WHEN niOO0001l = '1' ELSE nllO1Oii; + wire_nlO0l1iOi_dataout <= wire_nlO0l0Oll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1iOl_dataout <= wire_nlO0l0OlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1iOO_dataout <= wire_nlO0l0OOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1l0i_dataout <= wire_nlO0li11l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1l0l_dataout <= wire_nlO0li11O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1l0O_dataout <= wire_nlO0li10i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1l1i_dataout <= wire_nlO0l0OOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1l1l_dataout <= wire_nlO0l0OOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1l1O_dataout <= wire_nlO0li11i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1li_dataout <= wire_nlll0lli_q(24) WHEN niOO0001l = '1' ELSE nllO1Oil; + wire_nlO0l1lii_dataout <= wire_nlO0li10l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1lil_dataout <= wire_nlO0li10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1liO_dataout <= wire_nlO0li1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1ll_dataout <= wire_nlll0lli_q(25) WHEN niOO0001l = '1' ELSE nllO1OiO; + wire_nlO0l1lli_dataout <= wire_nlO0li1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1lll_dataout <= wire_nlO0li1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1llO_dataout <= wire_nlO0li1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1lO_dataout <= wire_nlll0lli_q(26) WHEN niOO0001l = '1' ELSE nllO1Oli; + wire_nlO0l1lOi_dataout <= wire_nlO0li1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1lOl_dataout <= wire_nlO0li1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1lOO_dataout <= wire_nlO0li1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1O0i_dataout <= wire_nlO0li01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1O0l_dataout <= wire_nlO0li01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1O0O_dataout <= wire_nlO0li00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1O1i_dataout <= wire_nlO0li1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1O1l_dataout <= wire_nlO0li1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1O1O_dataout <= wire_nlO0li01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1Oi_dataout <= wire_nlll0lli_q(27) WHEN niOO0001l = '1' ELSE nllO1Oll; + wire_nlO0l1Oii_dataout <= wire_nlO0li00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1Oil_dataout <= wire_nlO0li00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1OiO_dataout <= wire_nlO0li0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1Ol_dataout <= wire_nlll0lli_q(28) WHEN niOO0001l = '1' ELSE nllO1OlO; + wire_nlO0l1Oli_dataout <= wire_nlO0li0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1Oll_dataout <= wire_nlO0li0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1OlO_dataout <= wire_nlO0li0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1OO_dataout <= wire_nlll0lli_q(29) WHEN niOO0001l = '1' ELSE nllO1OOi; + wire_nlO0l1OOi_dataout <= wire_nlO0li0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0l1OOl_dataout <= (wire_nlO0O000l_dataout OR (nlO0il01O OR nlO00O11O)) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0il00i; + wire_nlO0l1OOO_dataout <= (wire_nlO0O000l_dataout OR nlO0il01O) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO00O11O; + wire_nlO0li00i_dataout <= wire_nlO0Oi1ii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOiii; + wire_nlO0li00l_dataout <= wire_nlO0Oi1il_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOiil; + wire_nlO0li00O_dataout <= wire_nlO0Oi1iO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOiiO; + wire_nlO0li01i_dataout <= wire_nlO0Oi10i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOi0i; + wire_nlO0li01l_dataout <= wire_nlO0Oi10l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOi0l; + wire_nlO0li01O_dataout <= wire_nlO0Oi10O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOi0O; + wire_nlO0li0i_dataout <= wire_nlll0lli_q(48) WHEN niOO0001l = '1' ELSE nllO001l; + wire_nlO0li0ii_dataout <= wire_nlO0Oi1li_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOili; + wire_nlO0li0il_dataout <= wire_nlO0Oi1ll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOill; + wire_nlO0li0iO_dataout <= wire_nlO0Oi1lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOilO; + wire_nlO0li0l_dataout <= wire_nlll0lli_q(49) WHEN niOO0001l = '1' ELSE nllO001O; + wire_nlO0li0li_dataout <= wire_nlO0Oi1Oi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOiOi; + wire_nlO0li0ll_dataout <= wire_nlO0Oi1Ol_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOiOl; + wire_nlO0li0O_dataout <= wire_nlll0lli_q(50) WHEN niOO0001l = '1' ELSE nllO000i; + wire_nlO0li10i_dataout <= wire_nlO0O0Oii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0ii; + wire_nlO0li10l_dataout <= wire_nlO0O0Oil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0il; + wire_nlO0li10O_dataout <= wire_nlO0O0OiO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0iO; + wire_nlO0li11i_dataout <= wire_nlO0O0O0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO00i; + wire_nlO0li11l_dataout <= wire_nlO0O0O0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO00l; + wire_nlO0li11O_dataout <= wire_nlO0O0O0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO00O; + wire_nlO0li1i_dataout <= wire_nlll0lli_q(45) WHEN niOO0001l = '1' ELSE nllO01Ol; + wire_nlO0li1ii_dataout <= wire_nlO0O0Oli_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0li; + wire_nlO0li1il_dataout <= wire_nlO0O0Oll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0ll; + wire_nlO0li1iO_dataout <= wire_nlO0O0OlO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0lO; + wire_nlO0li1l_dataout <= wire_nlll0lli_q(46) WHEN niOO0001l = '1' ELSE nllO01OO; + wire_nlO0li1li_dataout <= wire_nlO0O0OOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0Oi; + wire_nlO0li1ll_dataout <= wire_nlO0O0OOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0Ol; + wire_nlO0li1lO_dataout <= wire_nlO0O0OOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iO0OO; + wire_nlO0li1O_dataout <= wire_nlll0lli_q(47) WHEN niOO0001l = '1' ELSE nllO001i; + wire_nlO0li1Oi_dataout <= wire_nlO0Oi11i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOi1i; + wire_nlO0li1Ol_dataout <= wire_nlO0Oi11l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOi1l; + wire_nlO0li1OO_dataout <= wire_nlO0Oi11O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0iOi1O; + wire_nlO0liii_dataout <= wire_nlll0lli_q(51) WHEN niOO0001l = '1' ELSE nllO000l; + wire_nlO0liil_dataout <= wire_nlll0lli_q(52) WHEN niOO0001l = '1' ELSE nllO000O; + wire_nlO0liiO_dataout <= wire_nlll0lli_q(53) WHEN niOO0001l = '1' ELSE nllO00ii; + wire_nlO0lili_dataout <= wire_nlll0lli_q(54) WHEN niOO0001l = '1' ELSE nllO00il; + wire_nlO0lill_dataout <= wire_nlll0lli_q(55) WHEN niOO0001l = '1' ELSE nllO00iO; + wire_nlO0lilll_dataout <= wire_nlO0O011O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0lillO_dataout <= wire_nlO0ll1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0lilO_dataout <= wire_nlll0lli_q(56) WHEN niOO0001l = '1' ELSE nllO00li; + wire_nlO0lilOi_dataout <= wire_nlO0ll1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0lilOl_dataout <= wire_nlO0ll1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0lilOO_dataout <= wire_nlO0lOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liO0i_dataout <= wire_nlO0lOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liO0l_dataout <= wire_nlO0lOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liO0O_dataout <= wire_nlO0lOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liO1i_dataout <= wire_nlO0lOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liO1l_dataout <= wire_nlO0lOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liO1O_dataout <= wire_nlO0lOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOi_dataout <= wire_nlll0lli_q(57) WHEN niOO0001l = '1' ELSE nllO00ll; + wire_nlO0liOii_dataout <= wire_nlO0lOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOil_dataout <= wire_nlO0lOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOiO_dataout <= wire_nlO0lOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOl_dataout <= wire_nlll0lli_q(58) WHEN niOO0001l = '1' ELSE nllO00lO; + wire_nlO0liOli_dataout <= wire_nlO0lOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOll_dataout <= wire_nlO0ll1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOlO_dataout <= wire_nlO0ll01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOO_dataout <= wire_nlll0lli_q(59) WHEN niOO0001l = '1' ELSE nllO00Oi; + wire_nlO0liOOi_dataout <= wire_nlO0ll01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOOl_dataout <= wire_nlO0ll01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0liOOO_dataout <= wire_nlO0ll00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0ll00i_dataout <= wire_nlO0lllil_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0ll0OO_dataout; + wire_nlO0ll00l_dataout <= wire_nlO0llliO_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lli1i_dataout; + wire_nlO0ll00O_dataout <= wire_nlO0lllli_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lli1l_dataout; + wire_nlO0ll01i_dataout <= wire_nlO0lll0l_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0ll0lO_dataout; + wire_nlO0ll01l_dataout <= wire_nlO0lll0O_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0ll0Oi_dataout; + wire_nlO0ll01O_dataout <= wire_nlO0lllii_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0ll0Ol_dataout; + wire_nlO0ll0i_dataout <= wire_nlll0lli_q(63) WHEN niOO0001l = '1' ELSE nllO0i1l; + wire_nlO0ll0ii_dataout <= wire_nlO0lllll_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lli1O_dataout; + wire_nlO0ll0il_dataout <= wire_nlO0llllO_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lli0i_dataout; + wire_nlO0ll0iO_dataout <= wire_nlO0lllOi_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lli0l_dataout; + wire_nlO0ll0l_dataout <= nllO0i0l OR niOO0001l; + wire_nlO0ll0li_dataout <= wire_nlO0lllOl_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lli0O_dataout; + wire_nlO0ll0ll_dataout <= wire_nlO0lliii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liiOl; + wire_nlO0ll0lO_dataout <= wire_nlO0lliil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liiOO; + wire_nlO0ll0Oi_dataout <= wire_nlO0lliiO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lil1i; + wire_nlO0ll0Ol_dataout <= wire_nlO0llili_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lil1l; + wire_nlO0ll0OO_dataout <= wire_nlO0llill_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lil1O; + wire_nlO0ll10i_dataout <= wire_nlO0ll0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0ll10l_dataout <= wire_nlO0ll0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0ll10O_dataout <= wire_nlO0ll0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0ll11i_dataout <= wire_nlO0ll00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0ll11l_dataout <= wire_nlO0ll00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0ll11O_dataout <= wire_nlO0ll0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0ll1i_dataout <= wire_nlll0lli_q(60) WHEN niOO0001l = '1' ELSE nllO00Ol; + wire_nlO0ll1ii_dataout <= (niOl11l0l OR ((k_conf(216) AND nlO0lii1l) AND nlO0iOiOO)) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lii1i; + wire_nlO0ll1il_dataout <= niOl11l0O WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0li0OO; + wire_nlO0ll1iO_dataout <= niOl11l0i WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lii1l; + wire_nlO0ll1l_dataout <= wire_nlll0lli_q(61) WHEN niOO0001l = '1' ELSE nllO00OO; + wire_nlO0ll1O_dataout <= wire_nlll0lli_q(62) WHEN niOO0001l = '1' ELSE nllO0i1i; + wire_nlO0ll1OO_dataout <= wire_nlO0lll0i_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0ll0ll_dataout; + wire_nlO0lli0i_dataout <= wire_nlO0lliOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lilii; + wire_nlO0lli0l_dataout <= wire_nlO0lll1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lilil; + wire_nlO0lli0O_dataout <= wire_nlO0lll1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liliO; + wire_nlO0lli1i_dataout <= wire_nlO0llilO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lil0i; + wire_nlO0lli1l_dataout <= wire_nlO0lliOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lil0l; + wire_nlO0lli1O_dataout <= wire_nlO0lliOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lil0O; + wire_nlO0lliii_dataout <= nlO0liiOl AND NOT(niOl11lil); + wire_nlO0lliil_dataout <= wire_nlO0lll1O_o(1) AND NOT(niOl11lil); + wire_nlO0lliiO_dataout <= wire_nlO0lll1O_o(2) AND NOT(niOl11lil); + wire_nlO0llili_dataout <= wire_nlO0lll1O_o(3) AND NOT(niOl11lil); + wire_nlO0llill_dataout <= wire_nlO0lll1O_o(4) AND NOT(niOl11lil); + wire_nlO0llilO_dataout <= wire_nlO0lll1O_o(5) AND NOT(niOl11lil); + wire_nlO0lliOi_dataout <= wire_nlO0lll1O_o(6) AND NOT(niOl11lil); + wire_nlO0lliOl_dataout <= wire_nlO0lll1O_o(7) AND NOT(niOl11lil); + wire_nlO0lliOO_dataout <= wire_nlO0lll1O_o(8) AND NOT(niOl11lil); + wire_nlO0lll0i_dataout <= wire_nlO0lllOO_dataout AND NOT(niOl1010l); + wire_nlO0lll0l_dataout <= wire_nlO0llO1i_dataout AND NOT(niOl1010l); + wire_nlO0lll0O_dataout <= wire_nlO0llO1l_dataout AND NOT(niOl1010l); + wire_nlO0lll1i_dataout <= wire_nlO0lll1O_o(9) AND NOT(niOl11lil); + wire_nlO0lll1l_dataout <= wire_nlO0lll1O_o(10) AND NOT(niOl11lil); + wire_nlO0lllii_dataout <= wire_nlO0llO1O_dataout AND NOT(niOl1010l); + wire_nlO0lllil_dataout <= wire_nlO0llO0i_dataout AND NOT(niOl1010l); + wire_nlO0llliO_dataout <= wire_nlO0llO0l_dataout AND NOT(niOl1010l); + wire_nlO0lllli_dataout <= wire_nlO0llO0O_dataout AND NOT(niOl1010l); + wire_nlO0lllll_dataout <= wire_nlO0llOii_dataout AND NOT(niOl1010l); + wire_nlO0llllO_dataout <= wire_nlO0llOil_dataout AND NOT(niOl1010l); + wire_nlO0lllOi_dataout <= wire_nlO0llOiO_dataout AND NOT(niOl1010l); + wire_nlO0lllOl_dataout <= wire_nlO0llOli_dataout AND NOT(niOl1010l); + wire_nlO0lllOO_dataout <= wire_nlO0lO0lO_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0llOll_dataout; + wire_nlO0llO0i_dataout <= wire_nlO0lOi1i_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0llOOO_dataout; + wire_nlO0llO0l_dataout <= wire_nlO0lOi1l_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0lO11i_dataout; + wire_nlO0llO0O_dataout <= wire_nlO0lOi1O_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0lO11l_dataout; + wire_nlO0llO1i_dataout <= wire_nlO0lO0Oi_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0llOlO_dataout; + wire_nlO0llO1l_dataout <= wire_nlO0lO0Ol_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0llOOi_dataout; + wire_nlO0llO1O_dataout <= wire_nlO0lO0OO_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0llOOl_dataout; + wire_nlO0llOii_dataout <= wire_nlO0lOi0i_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0lO11O_dataout; + wire_nlO0llOil_dataout <= wire_nlO0lOi0l_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0lO10i_dataout; + wire_nlO0llOiO_dataout <= wire_nlO0lOi0O_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0lO10l_dataout; + wire_nlO0llOl_dataout <= wire_nlO0lO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0llOli_dataout <= wire_nlO0lOiii_dataout WHEN wire_nlO0Oi1lO_dataout = '1' ELSE wire_nlO0lO10O_dataout; + wire_nlO0llOll_dataout <= wire_nlO0lO0il_o(0) WHEN niOl11lli = '1' ELSE wire_nlO0lO1ii_dataout; + wire_nlO0llOlO_dataout <= wire_nlO0lO0il_o(1) WHEN niOl11lli = '1' ELSE wire_nlO0lO1il_dataout; + wire_nlO0llOO_dataout <= wire_nlO0lOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0llOOi_dataout <= wire_nlO0lO0il_o(2) WHEN niOl11lli = '1' ELSE wire_nlO0lO1iO_dataout; + wire_nlO0llOOl_dataout <= wire_nlO0lO0il_o(3) WHEN niOl11lli = '1' ELSE wire_nlO0lO1li_dataout; + wire_nlO0llOOO_dataout <= wire_nlO0lO0il_o(4) WHEN niOl11lli = '1' ELSE wire_nlO0lO1ll_dataout; + wire_nlO0lO01i_dataout <= wire_nlO0lO00i_o(8) AND niOl11llO; + wire_nlO0lO01l_dataout <= wire_nlO0lO00i_o(9) AND niOl11llO; + wire_nlO0lO0i_dataout <= wire_nlO0O11O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nllO0i0O; + wire_nlO0lO0l_dataout <= wire_nlO0O10i_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE wire_nlO0lOiO_dataout; + wire_nlO0lO0lO_dataout <= wire_nlO0O01iO_dataout WHEN niOl11lli = '1' ELSE wire_nlO0lOiil_dataout; + wire_nlO0lO0O_dataout <= wire_nlO0O10l_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE wire_nlO0lOli_dataout; + wire_nlO0lO0Oi_dataout <= wire_nlO0lO00i_o(0) WHEN niOl11lli = '1' ELSE wire_nlO0lOiiO_dataout; + wire_nlO0lO0Ol_dataout <= wire_nlO0lO00i_o(1) WHEN niOl11lli = '1' ELSE wire_nlO0lOili_dataout; + wire_nlO0lO0OO_dataout <= wire_nlO0lO00i_o(2) WHEN niOl11lli = '1' ELSE wire_nlO0lOill_dataout; + wire_nlO0lO10i_dataout <= wire_nlO0lO0il_o(8) WHEN niOl11lli = '1' ELSE wire_nlO0lO1OO_dataout; + wire_nlO0lO10l_dataout <= wire_nlO0lO0il_o(9) WHEN niOl11lli = '1' ELSE wire_nlO0lO01i_dataout; + wire_nlO0lO10O_dataout <= wire_nlO0lO0il_o(10) WHEN niOl11lli = '1' ELSE wire_nlO0lO01l_dataout; + wire_nlO0lO11i_dataout <= wire_nlO0lO0il_o(5) WHEN niOl11lli = '1' ELSE wire_nlO0lO1lO_dataout; + wire_nlO0lO11l_dataout <= wire_nlO0lO0il_o(6) WHEN niOl11lli = '1' ELSE wire_nlO0lO1Oi_dataout; + wire_nlO0lO11O_dataout <= wire_nlO0lO0il_o(7) WHEN niOl11lli = '1' ELSE wire_nlO0lO1Ol_dataout; + wire_nlO0lO1i_dataout <= wire_nlO0lO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0lO1ii_dataout <= wire_nlO0O01iO_dataout WHEN niOl11llO = '1' ELSE wire_w_lg_niOl11lll29365w(0); + wire_nlO0lO1il_dataout <= wire_nlO0lO00i_o(0) WHEN niOl11llO = '1' ELSE niOl11lll; + wire_nlO0lO1iO_dataout <= wire_nlO0lO00i_o(1) AND niOl11llO; + wire_nlO0lO1l_dataout <= wire_nlO0lO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0lO1li_dataout <= wire_nlO0lO00i_o(2) AND niOl11llO; + wire_nlO0lO1ll_dataout <= wire_nlO0lO00i_o(3) AND niOl11llO; + wire_nlO0lO1lO_dataout <= wire_nlO0lO00i_o(4) AND niOl11llO; + wire_nlO0lO1O_dataout <= wire_nlO0lOii_dataout OR wire_niO01O0O_dataout; + wire_nlO0lO1Oi_dataout <= wire_nlO0lO00i_o(5) AND niOl11llO; + wire_nlO0lO1Ol_dataout <= wire_nlO0lO00i_o(6) AND niOl11llO; + wire_nlO0lO1OO_dataout <= wire_nlO0lO00i_o(7) AND niOl11llO; + wire_nlO0lOi0i_dataout <= wire_nlO0lO00i_o(6) WHEN niOl11lli = '1' ELSE wire_nlO0lOiOO_dataout; + wire_nlO0lOi0l_dataout <= wire_nlO0lO00i_o(7) WHEN niOl11lli = '1' ELSE wire_nlO0lOl1i_dataout; + wire_nlO0lOi0O_dataout <= wire_nlO0lO00i_o(8) WHEN niOl11lli = '1' ELSE wire_nlO0lOl1l_dataout; + wire_nlO0lOi1i_dataout <= wire_nlO0lO00i_o(3) WHEN niOl11lli = '1' ELSE wire_nlO0lOilO_dataout; + wire_nlO0lOi1l_dataout <= wire_nlO0lO00i_o(4) WHEN niOl11lli = '1' ELSE wire_nlO0lOiOi_dataout; + wire_nlO0lOi1O_dataout <= wire_nlO0lO00i_o(5) WHEN niOl11lli = '1' ELSE wire_nlO0lOiOl_dataout; + wire_nlO0lOii_dataout <= wire_nlO0O10O_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE wire_nlO0lOll_dataout; + wire_nlO0lOiii_dataout <= wire_nlO0lO00i_o(9) WHEN niOl11lli = '1' ELSE wire_nlO0lOl1O_dataout; + wire_nlO0lOiil_dataout <= wire_nlO0lOl0i_o(0) WHEN niOl11llO = '1' ELSE niOl11lll; + wire_nlO0lOiiO_dataout <= wire_nlO0lOl0i_o(1) OR NOT(niOl11llO); + wire_nlO0lOil_dataout <= wire_nlO0O1ii_o WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lliO; + wire_nlO0lOili_dataout <= wire_nlO0lOl0i_o(2) AND niOl11llO; + wire_nlO0lOill_dataout <= wire_nlO0lOl0i_o(3) AND niOl11llO; + wire_nlO0lOilO_dataout <= wire_nlO0lOl0i_o(4) AND niOl11llO; + wire_nlO0lOiO_dataout <= nlO0llli AND NOT(niOO0000l); + wire_nlO0lOiOi_dataout <= wire_nlO0lOl0i_o(5) AND niOl11llO; + wire_nlO0lOiOl_dataout <= wire_nlO0lOl0i_o(6) AND niOl11llO; + wire_nlO0lOiOO_dataout <= wire_nlO0lOl0i_o(7) AND niOl11llO; + wire_nlO0lOl0O_dataout <= wire_nlO0O11li_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOO1l_dataout; + wire_nlO0lOl1i_dataout <= wire_nlO0lOl0i_o(8) AND niOl11llO; + wire_nlO0lOl1l_dataout <= wire_nlO0lOl0i_o(9) AND niOl11llO; + wire_nlO0lOl1O_dataout <= wire_nlO0lOl0i_o(10) AND niOl11llO; + wire_nlO0lOli_dataout <= nlO0llll AND NOT(niOO0000l); + wire_nlO0lOlii_dataout <= wire_nlO0O11ll_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOO1O_dataout; + wire_nlO0lOlil_dataout <= wire_nlO0O11lO_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOO0i_dataout; + wire_nlO0lOliO_dataout <= wire_nlO0O11Oi_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOO0l_dataout; + wire_nlO0lOll_dataout <= nlO0lllO OR niOO0000l; + wire_nlO0lOlli_dataout <= wire_nlO0O11Ol_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOO0O_dataout; + wire_nlO0lOlll_dataout <= wire_nlO0O11OO_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOOii_dataout; + wire_nlO0lOllO_dataout <= wire_nlO0O101i_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOOil_dataout; + wire_nlO0lOlOi_dataout <= wire_nlO0O101l_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOOiO_dataout; + wire_nlO0lOlOl_dataout <= wire_nlO0O101O_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOOli_dataout; + wire_nlO0lOlOO_dataout <= wire_nlO0O100i_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOOll_dataout; + wire_nlO0lOO0i_dataout <= wire_nlO0lOOOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lii0l; + wire_nlO0lOO0l_dataout <= wire_nlO0O111i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lii0O; + wire_nlO0lOO0O_dataout <= wire_nlO0O111l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liiii; + wire_nlO0lOO1i_dataout <= wire_nlO0O100l_dataout WHEN niOl11lOi = '1' ELSE wire_nlO0lOOlO_dataout; + wire_nlO0lOO1l_dataout <= wire_nlO0lOOOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lii1O; + wire_nlO0lOO1O_dataout <= wire_nlO0lOOOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lii0i; + wire_nlO0lOOii_dataout <= wire_nlO0O111O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liiil; + wire_nlO0lOOil_dataout <= wire_nlO0O110i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liiiO; + wire_nlO0lOOiO_dataout <= wire_nlO0O110l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liili; + wire_nlO0lOOli_dataout <= wire_nlO0O110O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liill; + wire_nlO0lOOll_dataout <= wire_nlO0O11ii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liilO; + wire_nlO0lOOlO_dataout <= wire_nlO0O11il_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0liiOi; + wire_nlO0lOOOi_dataout <= nlO0lii1O AND NOT(niOl11lOl); + wire_nlO0lOOOl_dataout <= wire_nlO0O11iO_o(1) AND NOT(niOl11lOl); + wire_nlO0lOOOO_dataout <= wire_nlO0O11iO_o(2) AND NOT(niOl11lOl); + wire_nlO0O000l_dataout <= wire_nilO0OOO_dataout AND nlOi1OiOO; + wire_nlO0O000O_dataout <= ((nlll11l0i AND wire_nl1000i_w_lg_nlOi1OiOO29159w(0)) AND nlO00O11l) OR ((wire_nilO0OOl_dataout AND nlOi1OiOO) AND nlO00O11l); + wire_nlO0O000O_w_lg_dataout28852w(0) <= NOT wire_nlO0O000O_dataout; + wire_nlO0O001i_dataout <= wire_nlO0O0O0l_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O001l_dataout <= wire_nlO0O0O0O_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O001O_dataout <= wire_nlO0O0Oii_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O00i_dataout <= nlO0llli AND NOT(wire_nlO0Oill_w_lg_dataout4340w(0)); + wire_nlO0O00l_dataout <= nlO0llll OR wire_nlO0Oill_w_lg_dataout4340w(0); + wire_nlO0O00ll_dataout <= wire_nilO01ll_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi1OO_dataout; + wire_nlO0O00lO_dataout <= wire_nilO01lO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi01i_dataout; + wire_nlO0O00O_dataout <= nlO0lllO AND NOT(wire_nlO0Oill_w_lg_dataout4340w(0)); + wire_nlO0O00Oi_dataout <= wire_nilO01Oi_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi01l_dataout; + wire_nlO0O00Ol_dataout <= wire_nilO01Ol_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi01O_dataout; + wire_nlO0O00OO_dataout <= wire_nilO01OO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi00i_dataout; + wire_nlO0O010i_dataout <= wire_nlO0O0OOi_dataout AND (wire_nlOi01O0i_w_lg_dataout29166w(0) OR wire_nlO0O000O_dataout); + wire_nlO0O011i_dataout <= wire_nlO0lOl0i_o(10) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O011O_dataout <= wire_nlO0O010i_dataout WHEN (wire_w_lg_w_lg_w_k_conf_range29168w29169w29170w(0) AND wire_w_lg_niOl1010l29171w(0)) = '1' ELSE nlO0iOiOO; + wire_nlO0O01i_dataout <= wire_nlO0O0ii_dataout WHEN niOO000il = '1' ELSE wire_nlO0O01O_dataout; + wire_nlO0O01iO_dataout <= wire_nlO0O0lOi_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O01l_dataout <= nlO0lliO OR niOO000il; + wire_nlO0O01li_dataout <= wire_nlO0O0lOl_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O01ll_dataout <= wire_nlO0O0lOO_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O01lO_dataout <= wire_nlO0O0O1i_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O01O_dataout <= nllO0i0O AND NOT(wire_nlO0Oill_w_lg_dataout4340w(0)); + wire_nlO0O01Oi_dataout <= wire_nlO0O0O1l_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O01Ol_dataout <= wire_nlO0O0O1O_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O01OO_dataout <= wire_nlO0O0O0i_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O0i0i_dataout <= wire_nilO000i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0il_dataout; + wire_nlO0O0i0l_dataout <= wire_nilO000l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0iO_dataout; + wire_nlO0O0i0O_dataout <= wire_nilO000O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0li_dataout; + wire_nlO0O0i1i_dataout <= wire_nilO001i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi00l_dataout; + wire_nlO0O0i1l_dataout <= wire_nilO001l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi00O_dataout; + wire_nlO0O0i1O_dataout <= wire_nilO001O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0ii_dataout; + wire_nlO0O0ii_dataout <= wire_nl1000i_w_lg_nllO0i0O4338w(0) AND (niOO000ii OR (NOT wire_nlll0lli_q(62))); + wire_nlO0O0iii_dataout <= wire_nilO00ii_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0ll_dataout; + wire_nlO0O0iil_dataout <= wire_nilO00il_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0lO_dataout; + wire_nlO0O0iiO_dataout <= wire_nilO00iO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0Oi_dataout; + wire_nlO0O0ili_dataout <= wire_nilO00li_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0Ol_dataout; + wire_nlO0O0ill_dataout <= wire_nilO00ll_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oi0OO_dataout; + wire_nlO0O0ilO_dataout <= wire_nilO00lO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oii1i_dataout; + wire_nlO0O0iOi_dataout <= wire_nilO00Oi_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oii1l_dataout; + wire_nlO0O0iOl_dataout <= wire_nilO00Ol_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oii1O_dataout; + wire_nlO0O0iOO_dataout <= wire_nilO00OO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oii0i_dataout; + wire_nlO0O0l0i_dataout <= wire_nilO0i0i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oiiil_dataout; + wire_nlO0O0l0l_dataout <= wire_nilO0i0l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiiiO_dataout; + wire_nlO0O0l0O_dataout <= wire_nilO0i0O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oiili_dataout; + wire_nlO0O0l1i_dataout <= wire_nilO0i1i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oii0l_dataout; + wire_nlO0O0l1l_dataout <= wire_nilO0i1l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oii0O_dataout; + wire_nlO0O0l1O_dataout <= wire_nilO0i1O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oiiii_dataout; + wire_nlO0O0lii_dataout <= wire_nilO0iii_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oiill_dataout; + wire_nlO0O0lil_dataout <= wire_nilO0iil_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiilO_dataout; + wire_nlO0O0liO_dataout <= wire_nilO0iiO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiiOi_dataout; + wire_nlO0O0ll_dataout <= nlO0lliO AND NOT((wire_w_lg_niOO000ll4352w(0) AND wire_nl1000i_w_lg_nllO0i0l4357w(0))); + wire_nlO0O0lli_dataout <= wire_nilO0ili_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiiOl_dataout; + wire_nlO0O0lll_dataout <= wire_nilO0ill_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiiOO_dataout; + wire_nlO0O0llO_dataout <= wire_nilO0ilO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oil1i_dataout; + wire_nlO0O0lOi_dataout <= wire_nilO0iOi_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oil1l_dataout; + wire_nlO0O0lOi_w_lg_dataout29753w(0) <= NOT wire_nlO0O0lOi_dataout; + wire_nlO0O0lOl_dataout <= wire_nilO0iOl_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oil1O_dataout; + wire_nlO0O0lOl_w_lg_dataout29751w(0) <= NOT wire_nlO0O0lOl_dataout; + wire_nlO0O0lOO_dataout <= wire_nilO0iOO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oil0i_dataout; + wire_nlO0O0lOO_w_lg_dataout29749w(0) <= NOT wire_nlO0O0lOO_dataout; + wire_nlO0O0O0i_dataout <= wire_nilO0l0i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oilil_dataout; + wire_nlO0O0O0i_w_lg_dataout29741w(0) <= NOT wire_nlO0O0O0i_dataout; + wire_nlO0O0O0l_dataout <= wire_nilO0l0l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiliO_dataout; + wire_nlO0O0O0l_w_lg_dataout29739w(0) <= NOT wire_nlO0O0O0l_dataout; + wire_nlO0O0O0O_dataout <= wire_nilO0l0O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oilli_dataout; + wire_nlO0O0O0O_w_lg_dataout29737w(0) <= NOT wire_nlO0O0O0O_dataout; + wire_nlO0O0O1i_dataout <= wire_nilO0l1i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oil0l_dataout; + wire_nlO0O0O1i_w_lg_dataout29747w(0) <= NOT wire_nlO0O0O1i_dataout; + wire_nlO0O0O1l_dataout <= wire_nilO0l1l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oil0O_dataout; + wire_nlO0O0O1l_w_lg_dataout29745w(0) <= NOT wire_nlO0O0O1l_dataout; + wire_nlO0O0O1O_dataout <= wire_nilO0l1O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oilii_dataout; + wire_nlO0O0O1O_w_lg_dataout29743w(0) <= NOT wire_nlO0O0O1O_dataout; + wire_nlO0O0Oi_dataout <= wire_nlO0Oi1i_dataout AND NOT(niOO000iO); + wire_nlO0O0Oii_dataout <= wire_nilO0lii_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Oilll_dataout; + wire_nlO0O0Oii_w_lg_dataout29736w(0) <= NOT wire_nlO0O0Oii_dataout; + wire_nlO0O0Oil_dataout <= wire_nilO0lil_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OillO_dataout; + wire_nlO0O0OiO_dataout <= wire_nilO0liO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OilOi_dataout; + wire_nlO0O0Ol_dataout <= wire_nlO0Oi1l_dataout AND NOT(niOO000iO); + wire_nlO0O0Oli_dataout <= wire_nilO0lli_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OilOl_dataout; + wire_nlO0O0Oll_dataout <= wire_nilO0lll_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OilOO_dataout; + wire_nlO0O0OlO_dataout <= wire_nilO0llO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiO1i_dataout; + wire_nlO0O0OO_dataout <= wire_nlO0Oi1O_dataout OR niOO000iO; + wire_nlO0O0OOi_dataout <= wire_nilO0lOi_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiO1l_dataout; + wire_nlO0O0OOi_w_lg_dataout29186w(0) <= NOT wire_nlO0O0OOi_dataout; + wire_nlO0O0OOi_w_lg_w_lg_dataout29186w29291w(0) <= wire_nlO0O0OOi_w_lg_dataout29186w(0) OR wire_nlO0O000O_dataout; + wire_nlO0O0OOl_dataout <= wire_nilO0lOl_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiO1O_dataout; + wire_nlO0O0OOO_dataout <= wire_nilO0lOO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiO0i_dataout; + wire_nlO0O100i_dataout <= wire_nlO0O10OO_dataout AND NOT(niOl1010l); + wire_nlO0O100l_dataout <= wire_nlO0O1i1i_dataout AND NOT(niOl1010l); + wire_nlO0O100O_dataout <= wire_nlO0O1O0O_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1i1l_dataout; + wire_nlO0O101i_dataout <= wire_nlO0O10lO_dataout AND NOT(niOl1010l); + wire_nlO0O101l_dataout <= wire_nlO0O10Oi_dataout AND NOT(niOl1010l); + wire_nlO0O101O_dataout <= wire_nlO0O10Ol_dataout AND NOT(niOl1010l); + wire_nlO0O10ii_dataout <= wire_nlO0O1Oii_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1i1O_dataout; + wire_nlO0O10il_dataout <= wire_nlO0O1Oil_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1i0i_dataout; + wire_nlO0O10iO_dataout <= wire_nlO0O1OiO_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1i0l_dataout; + wire_nlO0O10li_dataout <= wire_nlO0O1Oli_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1i0O_dataout; + wire_nlO0O10ll_dataout <= wire_nlO0O1Oll_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1iii_dataout; + wire_nlO0O10lO_dataout <= wire_nlO0O1OlO_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1iil_dataout; + wire_nlO0O10Oi_dataout <= wire_nlO0O1OOi_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1iiO_dataout; + wire_nlO0O10Ol_dataout <= wire_nlO0O1OOl_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1ili_dataout; + wire_nlO0O10OO_dataout <= wire_nlO0O1OOO_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1ill_dataout; + wire_nlO0O110i_dataout <= wire_nlO0O11iO_o(6) AND NOT(niOl11lOl); + wire_nlO0O110l_dataout <= wire_nlO0O11iO_o(7) AND NOT(niOl11lOl); + wire_nlO0O110O_dataout <= wire_nlO0O11iO_o(8) AND NOT(niOl11lOl); + wire_nlO0O111i_dataout <= wire_nlO0O11iO_o(3) AND NOT(niOl11lOl); + wire_nlO0O111l_dataout <= wire_nlO0O11iO_o(4) AND NOT(niOl11lOl); + wire_nlO0O111O_dataout <= wire_nlO0O11iO_o(5) AND NOT(niOl11lOl); + wire_nlO0O11ii_dataout <= wire_nlO0O11iO_o(9) AND NOT(niOl11lOl); + wire_nlO0O11il_dataout <= wire_nlO0O11iO_o(10) AND NOT(niOl11lOl); + wire_nlO0O11li_dataout <= wire_nlO0O100O_dataout AND NOT(niOl1010l); + wire_nlO0O11ll_dataout <= wire_nlO0O10ii_dataout AND NOT(niOl1010l); + wire_nlO0O11lO_dataout <= wire_nlO0O10il_dataout AND NOT(niOl1010l); + wire_nlO0O11O_dataout <= wire_nlO0O1il_dataout WHEN nlO0llli = '1' ELSE nllO0i0O; + wire_nlO0O11Oi_dataout <= wire_nlO0O10iO_dataout AND NOT(niOl1010l); + wire_nlO0O11Ol_dataout <= wire_nlO0O10li_dataout AND NOT(niOl1010l); + wire_nlO0O11OO_dataout <= wire_nlO0O10ll_dataout AND NOT(niOl1010l); + wire_nlO0O1i0i_dataout <= wire_nlO0O1lll_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1iOO_dataout; + wire_nlO0O1i0l_dataout <= wire_nlO0O1llO_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1l1i_dataout; + wire_nlO0O1i0O_dataout <= wire_nlO0O1lOi_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1l1l_dataout; + wire_nlO0O1i1i_dataout <= wire_nlO0O011i_dataout WHEN niOl11O1i = '1' ELSE wire_nlO0O1ilO_dataout; + wire_nlO0O1i1l_dataout <= wire_nlO0O1liO_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1iOi_dataout; + wire_nlO0O1i1O_dataout <= wire_nlO0O1lli_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1iOl_dataout; + wire_nlO0O1iii_dataout <= wire_nlO0O1lOl_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1l1O_dataout; + wire_nlO0O1iil_dataout <= wire_nlO0O1lOO_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1l0i_dataout; + wire_nlO0O1iiO_dataout <= wire_nlO0O1O1i_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1l0l_dataout; + wire_nlO0O1il_dataout <= nllO0i0O WHEN niOO0000O = '1' ELSE wire_nlO0O01i_dataout; + wire_nlO0O1ili_dataout <= wire_nlO0O1O1l_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1l0O_dataout; + wire_nlO0O1ill_dataout <= wire_nlO0O1O1O_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1lii_dataout; + wire_nlO0O1ilO_dataout <= wire_nlO0O1O0i_dataout WHEN niOl11lOO = '1' ELSE wire_nlO0O1lil_dataout; + wire_nlO0O1iO_dataout <= nlO0lliO WHEN niOO0000O = '1' ELSE wire_nlO0O01l_dataout; + wire_nlO0O1iOi_dataout <= wire_nlO0O01iO_dataout AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1iOl_dataout <= wire_nlO0lO00i_o(0) OR NOT(wire_nlO0Oi1Oi_dataout); + wire_nlO0O1iOO_dataout <= wire_nlO0lO00i_o(1) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1l0i_dataout <= wire_nlO0lO00i_o(5) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1l0l_dataout <= wire_nlO0lO00i_o(6) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1l0O_dataout <= wire_nlO0lO00i_o(7) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1l1i_dataout <= wire_nlO0lO00i_o(2) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1l1l_dataout <= wire_nlO0lO00i_o(3) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1l1O_dataout <= wire_nlO0lO00i_o(4) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1li_dataout <= wire_nlO0O1Oi_dataout AND NOT(niOO0000O); + wire_nlO0O1lii_dataout <= wire_nlO0lO00i_o(8) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1lil_dataout <= wire_nlO0lO00i_o(9) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1liO_dataout <= wire_nlO0lO0il_o(0) OR NOT(wire_nlO0Oi1Oi_dataout); + wire_nlO0O1ll_dataout <= wire_nlO0O1Ol_dataout AND NOT(niOO0000O); + wire_nlO0O1lli_dataout <= wire_nlO0lO0il_o(1) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1lll_dataout <= wire_nlO0lO0il_o(2) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1llO_dataout <= wire_nlO0lO0il_o(3) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1lO_dataout <= wire_nlO0O1OO_dataout OR niOO0000O; + wire_nlO0O1lOi_dataout <= wire_nlO0lO0il_o(4) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1lOl_dataout <= wire_nlO0lO0il_o(5) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1lOO_dataout <= wire_nlO0lO0il_o(6) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1O0i_dataout <= wire_nlO0lO0il_o(10) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1O0O_dataout <= wire_nlO0lOl0i_o(0) OR NOT(wire_nlO0Oi1Oi_dataout); + wire_nlO0O1O1i_dataout <= wire_nlO0lO0il_o(7) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1O1l_dataout <= wire_nlO0lO0il_o(8) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1O1O_dataout <= wire_nlO0lO0il_o(9) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1Oi_dataout <= wire_nlO0O00i_dataout AND NOT(niOO000il); + wire_nlO0O1Oii_dataout <= wire_nlO0lOl0i_o(1) OR NOT(wire_nlO0Oi1Oi_dataout); + wire_nlO0O1Oil_dataout <= wire_nlO0lOl0i_o(2) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1OiO_dataout <= wire_nlO0lOl0i_o(3) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1Ol_dataout <= wire_nlO0O00l_dataout OR niOO000il; + wire_nlO0O1Oli_dataout <= wire_nlO0lOl0i_o(4) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1Oll_dataout <= wire_nlO0lOl0i_o(5) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1OlO_dataout <= wire_nlO0lOl0i_o(6) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1OO_dataout <= wire_nlO0O00O_dataout AND NOT(niOO000il); + wire_nlO0O1OOi_dataout <= wire_nlO0lOl0i_o(7) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1OOl_dataout <= wire_nlO0lOl0i_o(8) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0O1OOO_dataout <= wire_nlO0lOl0i_o(9) AND wire_nlO0Oi1Oi_dataout; + wire_nlO0Oi00i_dataout <= wire_nilO01OO_dataout WHEN niOl11O0i = '1' ELSE nlliOOO0i; + wire_nlO0Oi00l_dataout <= wire_nilO001i_dataout WHEN niOl11O0i = '1' ELSE nlliOOO0l; + wire_nlO0Oi00O_dataout <= wire_nilO001l_dataout WHEN niOl11O0i = '1' ELSE nlliOOO0O; + wire_nlO0Oi01i_dataout <= wire_nilO01lO_dataout WHEN niOl11O0i = '1' ELSE nlliOOO1i; + wire_nlO0Oi01l_dataout <= wire_nilO01Oi_dataout WHEN niOl11O0i = '1' ELSE nlliOOO1l; + wire_nlO0Oi01O_dataout <= wire_nilO01Ol_dataout WHEN niOl11O0i = '1' ELSE nlliOOO1O; + wire_nlO0Oi0ii_dataout <= wire_nilO001O_dataout WHEN niOl11O0i = '1' ELSE nlliOOOii; + wire_nlO0Oi0il_dataout <= wire_nilO000i_dataout WHEN niOl11O0i = '1' ELSE nlliOOOil; + wire_nlO0Oi0iO_dataout <= wire_nilO000l_dataout WHEN niOl11O0i = '1' ELSE nlliOOOiO; + wire_nlO0Oi0li_dataout <= wire_nilO000O_dataout WHEN niOl11O0i = '1' ELSE nlliOOOli; + wire_nlO0Oi0ll_dataout <= wire_nilO00ii_dataout WHEN niOl11O0i = '1' ELSE nlliOOOll; + wire_nlO0Oi0lO_dataout <= wire_nilO00il_dataout WHEN niOl11O0i = '1' ELSE nlliOOOlO; + wire_nlO0Oi0O_dataout <= nlO0llli AND NOT(niOO000li); + wire_nlO0Oi0Oi_dataout <= wire_nilO00iO_dataout WHEN niOl11O0i = '1' ELSE nlliOOOOi; + wire_nlO0Oi0Ol_dataout <= wire_nilO00li_dataout WHEN niOl11O0i = '1' ELSE nlliOOOOl; + wire_nlO0Oi0OO_dataout <= wire_nilO00ll_dataout WHEN niOl11O0i = '1' ELSE nlliOOOOO; + wire_nlO0Oi10i_dataout <= wire_nilO0O0i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOil_dataout; + wire_nlO0Oi10l_dataout <= wire_nilO0O0l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOiO_dataout; + wire_nlO0Oi10O_dataout <= wire_nilO0O0O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOli_dataout; + wire_nlO0Oi11i_dataout <= wire_nilO0O1i_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiO0l_dataout; + wire_nlO0Oi11l_dataout <= wire_nilO0O1l_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiO0O_dataout; + wire_nlO0Oi11O_dataout <= wire_nilO0O1O_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOii_dataout; + wire_nlO0Oi1i_dataout <= nlO0llli OR k_hip(0); + wire_nlO0Oi1ii_dataout <= wire_nilO0Oii_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOll_dataout; + wire_nlO0Oi1il_dataout <= wire_nilO0Oil_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOlO_dataout; + wire_nlO0Oi1iO_dataout <= wire_nilO0OiO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOOi_dataout; + wire_nlO0Oi1l_dataout <= nlO0llll AND NOT(k_hip(0)); + wire_nlO0Oi1li_dataout <= wire_nilO0Oli_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOOl_dataout; + wire_nlO0Oi1ll_dataout <= wire_nilO0Oll_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0OiOOO_dataout; + wire_nlO0Oi1lO_dataout <= wire_nilO0OlO_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Ol11i_dataout; + wire_nlO0Oi1lO_w_lg_dataout29185w(0) <= NOT wire_nlO0Oi1lO_dataout; + wire_nlO0Oi1O_dataout <= nlO0lllO AND NOT(k_hip(0)); + wire_nlO0Oi1Oi_dataout <= wire_nilO0OOi_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Ol11l_dataout; + wire_nlO0Oi1Ol_dataout <= wire_nilO0OOl_dataout WHEN niOl11O0l = '1' ELSE wire_nlO0Ol11O_dataout; + wire_nlO0Oi1OO_dataout <= wire_nilO01ll_dataout WHEN niOl11O0i = '1' ELSE nlliOOlOO; + wire_nlO0Oii0i_dataout <= wire_nilO00OO_dataout WHEN niOl11O0i = '1' ELSE nlll1110i; + wire_nlO0Oii0l_dataout <= wire_nilO0i1i_dataout WHEN niOl11O0i = '1' ELSE nlll1110l; + wire_nlO0Oii0O_dataout <= wire_nilO0i1l_dataout WHEN niOl11O0i = '1' ELSE nlll1110O; + wire_nlO0Oii1i_dataout <= wire_nilO00lO_dataout WHEN niOl11O0i = '1' ELSE nlll1111i; + wire_nlO0Oii1l_dataout <= wire_nilO00Oi_dataout WHEN niOl11O0i = '1' ELSE nlll1111l; + wire_nlO0Oii1O_dataout <= wire_nilO00Ol_dataout WHEN niOl11O0i = '1' ELSE nlll1111O; + wire_nlO0Oiii_dataout <= nlO0llll OR niOO000li; + wire_nlO0Oiiii_dataout <= wire_nilO0i1O_dataout WHEN niOl11O0i = '1' ELSE nlll111ii; + wire_nlO0Oiiil_dataout <= wire_nilO0i0i_dataout WHEN niOl11O0i = '1' ELSE nlll111il; + wire_nlO0OiiiO_dataout <= wire_nilO0i0l_dataout WHEN niOl11O0i = '1' ELSE nlll111iO; + wire_nlO0Oiil_dataout <= nlO0lllO AND NOT(niOO000li); + wire_nlO0Oiili_dataout <= wire_nilO0i0O_dataout WHEN niOl11O0i = '1' ELSE nlll111li; + wire_nlO0Oiill_dataout <= wire_nilO0iii_dataout WHEN niOl11O0i = '1' ELSE nlll111ll; + wire_nlO0OiilO_dataout <= wire_nilO0iil_dataout WHEN niOl11O0i = '1' ELSE nlll111lO; + wire_nlO0OiiOi_dataout <= wire_nilO0iiO_dataout WHEN niOl11O0i = '1' ELSE nlll111Oi; + wire_nlO0OiiOl_dataout <= wire_nilO0ili_dataout WHEN niOl11O0i = '1' ELSE nlll111Ol; + wire_nlO0OiiOO_dataout <= wire_nilO0ill_dataout WHEN niOl11O0i = '1' ELSE nlll111OO; + wire_nlO0Oil0i_dataout <= wire_nilO0iOO_dataout WHEN niOl11O0i = '1' ELSE nlll1100i; + wire_nlO0Oil0l_dataout <= wire_nilO0l1i_dataout WHEN niOl11O0i = '1' ELSE nlll1100l; + wire_nlO0Oil0O_dataout <= wire_nilO0l1l_dataout WHEN niOl11O0i = '1' ELSE nlll1100O; + wire_nlO0Oil1i_dataout <= wire_nilO0ilO_dataout WHEN niOl11O0i = '1' ELSE nlll1101i; + wire_nlO0Oil1l_dataout <= wire_nilO0iOi_dataout WHEN niOl11O0i = '1' ELSE nlll1101l; + wire_nlO0Oil1O_dataout <= wire_nilO0iOl_dataout WHEN niOl11O0i = '1' ELSE nlll1101O; + wire_nlO0Oilii_dataout <= wire_nilO0l1O_dataout WHEN niOl11O0i = '1' ELSE nlll110ii; + wire_nlO0Oilil_dataout <= wire_nilO0l0i_dataout WHEN niOl11O0i = '1' ELSE nlll110il; + wire_nlO0OiliO_dataout <= wire_nilO0l0l_dataout WHEN niOl11O0i = '1' ELSE nlll110iO; + wire_nlO0Oill_dataout <= wire_nlO0OilO_dataout OR (wire_w_lg_w_k_hip_range2413w2429w(0) AND niOO000lO); + wire_nlO0Oill_w_lg_w_lg_dataout4340w4341w(0) <= wire_nlO0Oill_w_lg_dataout4340w(0) AND nlO0llli; + wire_nlO0Oill_w_lg_w_lg_dataout4340w4343w(0) <= wire_nlO0Oill_w_lg_dataout4340w(0) AND nlO0llll; + wire_nlO0Oill_w_lg_dataout4340w(0) <= NOT wire_nlO0Oill_dataout; + wire_nlO0Oilli_dataout <= wire_nilO0l0O_dataout WHEN niOl11O0i = '1' ELSE nlll110li; + wire_nlO0Oilll_dataout <= wire_nilO0lii_dataout WHEN niOl11O0i = '1' ELSE nlll110ll; + wire_nlO0OillO_dataout <= wire_nilO0lil_dataout WHEN niOl11O0i = '1' ELSE nlll110lO; + wire_nlO0OilO_dataout <= (niOO000ll AND wire_nlOl1l0Ol_w_lg_dataout4348w(0)) OR (k_hip(0) AND niOO000lO); + wire_nlO0OilOi_dataout <= wire_nilO0liO_dataout WHEN niOl11O0i = '1' ELSE nlll110Oi; + wire_nlO0OilOl_dataout <= wire_nilO0lli_dataout WHEN niOl11O0i = '1' ELSE nlll110Ol; + wire_nlO0OilOO_dataout <= wire_nilO0lll_dataout WHEN niOl11O0i = '1' ELSE nlll110OO; + wire_nlO0OiO0i_dataout <= wire_nilO0lOO_dataout WHEN niOl11O0i = '1' ELSE nlll11i0i; + wire_nlO0OiO0l_dataout <= wire_nilO0O1i_dataout WHEN niOl11O0i = '1' ELSE nlll11i0l; + wire_nlO0OiO0O_dataout <= wire_nilO0O1l_dataout WHEN niOl11O0i = '1' ELSE nlll11i0O; + wire_nlO0OiO1i_dataout <= wire_nilO0llO_dataout WHEN niOl11O0i = '1' ELSE nlll11i1i; + wire_nlO0OiO1l_dataout <= wire_nilO0lOi_dataout WHEN niOl11O0i = '1' ELSE nlll11i1l; + wire_nlO0OiO1O_dataout <= wire_nilO0lOl_dataout WHEN niOl11O0i = '1' ELSE nlll11i1O; + wire_nlO0OiOii_dataout <= wire_nilO0O1O_dataout WHEN niOl11O0i = '1' ELSE nlll11iii; + wire_nlO0OiOil_dataout <= wire_nilO0O0i_dataout WHEN niOl11O0i = '1' ELSE nlll11iil; + wire_nlO0OiOiO_dataout <= wire_nilO0O0l_dataout WHEN niOl11O0i = '1' ELSE nlll11iiO; + wire_nlO0OiOli_dataout <= wire_nilO0O0O_dataout WHEN niOl11O0i = '1' ELSE nlll11ili; + wire_nlO0OiOll_dataout <= wire_nilO0Oii_dataout WHEN niOl11O0i = '1' ELSE nlll11ill; + wire_nlO0OiOlO_dataout <= wire_nilO0Oil_dataout WHEN niOl11O0i = '1' ELSE nlll11ilO; + wire_nlO0OiOOi_dataout <= wire_nilO0OiO_dataout WHEN niOl11O0i = '1' ELSE nlll11iOi; + wire_nlO0OiOOl_dataout <= wire_nilO0Oli_dataout WHEN niOl11O0i = '1' ELSE nlll11iOl; + wire_nlO0OiOOO_dataout <= wire_nilO0Oll_dataout WHEN niOl11O0i = '1' ELSE nlll11iOO; + wire_nlO0Ol00i_dataout <= nlll00iOO WHEN nlOi1OiOO = '1' ELSE nlll11O1i; + wire_nlO0Ol01i_dataout <= nlll00ilO WHEN nlOi1OiOO = '1' ELSE nlll11lOi; + wire_nlO0Ol01l_dataout <= nlll00iOi WHEN nlOi1OiOO = '1' ELSE nlll11lOl; + wire_nlO0Ol01O_dataout <= nlll00iOl WHEN nlOi1OiOO = '1' ELSE nlll11lOO; + wire_nlO0Ol0i_dataout <= niOO000Ol AND wire_w_lg_w_k_hip_range2413w4342w(0); + wire_nlO0Ol10i_dataout <= nlll11l0i AND (wire_nl1000i_w_lg_nlOi1OiOO29159w(0) AND wire_nl11llO_w_lg_nlO00O11l29156w(0)); + wire_nlO0Ol11i_dataout <= wire_nilO0OlO_dataout WHEN niOl11O0i = '1' ELSE nlll11l1i; + wire_nlO0Ol11l_dataout <= wire_nilO0OOi_dataout WHEN niOl11O0i = '1' ELSE nlll11l1l; + wire_nlO0Ol11O_dataout <= wire_nlO0Ol10i_dataout AND NOT(niOl11O0i); + wire_nlO0Ol1il_dataout <= nlll00i0i WHEN nlOi1OiOO = '1' ELSE nlll11l0l; + wire_nlO0Ol1iO_dataout <= nlll00i0l WHEN nlOi1OiOO = '1' ELSE nlll11l0O; + wire_nlO0Ol1li_dataout <= nlll00i0O WHEN nlOi1OiOO = '1' ELSE nlll11lii; + wire_nlO0Ol1ll_dataout <= nlll00iii WHEN nlOi1OiOO = '1' ELSE nlll11lil; + wire_nlO0Ol1lO_dataout <= nlll00iil WHEN nlOi1OiOO = '1' ELSE nlll11liO; + wire_nlO0Ol1O_dataout <= niOO000Ol WHEN (wire_w_lg_w_k_hip_range2413w2429w(0) AND wire_nlO0Oill_w_lg_w_lg_dataout4340w4343w(0)) = '1' ELSE wire_nlO0Ol0i_dataout; + wire_nlO0Ol1Oi_dataout <= nlll00iiO WHEN nlOi1OiOO = '1' ELSE nlll11lli; + wire_nlO0Ol1Ol_dataout <= nlll00ili WHEN nlOi1OiOO = '1' ELSE nlll11lll; + wire_nlO0Ol1OO_dataout <= nlll00ill WHEN nlOi1OiOO = '1' ELSE nlll11llO; + wire_nlO0Olll_dataout <= nlOil01l AND NOT((NOT k_gbl_hip(32))); + wire_nlO0Olll_w_lg_dataout59543w(0) <= NOT wire_nlO0Olll_dataout; + wire_nlO0OllO_dataout <= wire_n1liOli_dataout WHEN (wire_nl1000i_w_lg_n1l010O4314w(0) AND (niOO00i1l AND niOO00iOi)) = '1' ELSE wire_nlO0OlOi_dataout; + wire_nlO0OlOi_dataout <= wire_n1liOli_dataout WHEN (niOO00lll AND (niOO00i1O AND niOO00lii)) = '1' ELSE wire_nlO0OlOl_dataout; + wire_nlO0OlOil_dataout <= wire_nlO0OOill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OlOiO_dataout <= wire_nlO0OOilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OlOl_dataout <= wire_n1liOli_dataout WHEN (niOO00lll AND (niOO00i1O AND niOO000OO)) = '1' ELSE wire_nlO0OlOO_dataout; + wire_nlO0OlOli_dataout <= wire_nlO0OOiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OlOll_dataout <= wire_nlO0OOiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OlOlO_dataout <= wire_nlO0OOiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OlOO_dataout <= wire_n1liOli_dataout WHEN (wire_nl1000i_w_lg_n1l010O4314w(0) AND wire_w_lg_niOO00lll4327w(0)) = '1' ELSE wire_nlO0OO1i_dataout; + wire_nlO0OlOOi_dataout <= wire_nlO0OOl1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OlOOl_dataout <= wire_nlO0OOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OlOOO_dataout <= wire_nlO0OOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO00i_dataout <= wire_nlO0OOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO00l_dataout <= wire_nlO0OOOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO00O_dataout <= wire_nlO0OOOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO01i_dataout <= wire_nlO0OOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO01l_dataout <= wire_nlO0OOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO01O_dataout <= wire_nlO0OOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0ii_dataout <= wire_nlO0OOOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0il_dataout <= wire_nlO0OOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0iO_dataout <= wire_nlO0OOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0li_dataout <= wire_nlO0OOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0ll_dataout <= wire_nlO0OOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0lO_dataout <= wire_nlO0OOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0Oi_dataout <= wire_nlOi1111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0Ol_dataout <= wire_nlOi1111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO0OO_dataout <= wire_nlOi1111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO10i_dataout <= wire_nlO0OOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO10l_dataout <= wire_nlO0OOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO10O_dataout <= wire_nlO0OOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO11i_dataout <= wire_nlO0OOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO11l_dataout <= wire_nlO0OOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO11O_dataout <= wire_nlO0OOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1i_dataout <= n1l000i WHEN niOO00i0i = '1' ELSE wire_n1liOli_dataout; + wire_nlO0OO1ii_dataout <= wire_nlO0OOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1il_dataout <= wire_nlO0OOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1iO_dataout <= wire_nlO0OOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1li_dataout <= wire_nlO0OOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1ll_dataout <= wire_nlO0OOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1lO_dataout <= wire_nlO0OOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1Oi_dataout <= wire_nlO0OOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1Ol_dataout <= wire_nlO0OOO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OO1OO_dataout <= wire_nlO0OOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOi0i_dataout <= wire_nlOi111ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOi0l_dataout <= wire_nlOi111il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOi0O_dataout <= wire_nlOi111iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOi1i_dataout <= wire_nlOi1110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOi1l_dataout <= wire_nlOi1110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOi1O_dataout <= wire_nlOi1110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOiii_dataout <= wire_nlOi111li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOiil_dataout <= wire_nlOi111ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOiiO_dataout <= wire_nlOi111lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOili_dataout <= wire_nlOi111Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO0OOill_dataout <= (wire_nlOi1l00i_dataout XOR (wire_nlOi1l01l_dataout XOR (wire_nlOi1l01i_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1lili_dataout XOR (wire_nlOi1liiO_dataout XOR wire_nlOi1liil_dataout)))))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0lilli; + wire_nlO0OOilO_dataout <= (NOT (wire_nlOi1l00l_dataout XOR (wire_nlOi1l01O_dataout XOR (wire_nlOi1l01l_dataout XOR (wire_nlOi1l01i_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1lili_dataout XOR wire_nlOi1liiO_dataout))))))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol00l; + wire_nlO0OOiOi_dataout <= (wire_nlOi1l00O_dataout XOR (wire_nlOi1l00i_dataout XOR (wire_nlOi1l01O_dataout XOR (wire_nlOi1l01l_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1lili_dataout XOR wire_nlOi1liiO_dataout)))))))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol00O; + wire_nlO0OOiOl_dataout <= (wire_nlOi1l0ii_dataout XOR (wire_nlOi1l00l_dataout XOR (wire_nlOi1l00i_dataout XOR (wire_nlOi1l01O_dataout XOR (wire_nlOi1l01i_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1lili_dataout XOR wire_nlOi1li0O_dataout))))))))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0ii; + wire_nlO0OOiOO_dataout <= (wire_nlOi1l0il_dataout XOR (wire_nlOi1l00O_dataout XOR (wire_nlOi1l00l_dataout XOR (wire_nlOi1l00i_dataout XOR (wire_nlOi1l01l_dataout XOR (wire_nlOi1l01i_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR niOl11Oll)))))))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0il; + wire_nlO0OOl0i_dataout <= (NOT (((wire_w_lg_niOl11OOi29015w(0) OR wire_nl1000i_w_lg_nlOi1OiOl29018w(0)) OR (wire_nl1000i_w_lg_nlOi1Ol1l29021w(0) AND (niOOi1ill AND niOOi1ili))) XOR wire_nlOi1l00l_w_lg_dataout29032w(0))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0lO; + wire_nlO0OOl0l_dataout <= (NOT (wire_nlOi1l00O_dataout XOR (wire_nlOi1l01l_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lili_dataout XOR (wire_nlOi1liiO_dataout XOR niOl11OlO)))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0Oi; + wire_nlO0OOl0O_dataout <= (wire_nlOi1l0ii_dataout XOR (wire_nlOi1l01O_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lill_dataout XOR niOl11Oii)))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0Ol; + wire_nlO0OOl1i_dataout <= (NOT (wire_nlOi1l0ii_dataout XOR (wire_nlOi1l00O_dataout XOR (wire_nlOi1l01O_dataout XOR (wire_nlOi1l01l_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1liiO_dataout XOR niOl11Oil))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0iO; + wire_nlO0OOl1l_dataout <= (NOT (wire_nlOi1l0il_dataout XOR (wire_nlOi1l0ii_dataout XOR (wire_nlOi1l00i_dataout XOR (wire_nlOi1l01O_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lili_dataout XOR niOl11O0O))))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0li; + wire_nlO0OOl1O_dataout <= (wire_nlOi1l0il_dataout XOR (wire_nlOi1l00i_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1l0OO_dataout XOR niOl11Oii))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0ll; + wire_nlO0OOlii_dataout <= (wire_nlOi1l0il_dataout XOR (wire_nlOi1l00i_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1liiO_dataout XOR wire_nlOi1liii_dataout))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ol0OO; + wire_nlO0OOlil_dataout <= (NOT (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1lili_dataout XOR niOl11Oli)))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oli1i; + wire_nlO0OOliO_dataout <= (NOT (wire_nlOi1l01i_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lill_dataout XOR niOl11OiO)))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oli1l; + wire_nlO0OOlli_dataout <= (wire_nlOi1l01l_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0li_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lilO_dataout XOR (wire_nlOi1lili_dataout XOR niOl11OiO)))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oli1O; + wire_nlO0OOlll_dataout <= (NOT (wire_nlOi1l01O_dataout XOR (wire_nlOi1l01i_dataout XOR (wire_nlOi1l0Ol_dataout XOR (wire_nlOi1l0Oi_dataout XOR (wire_nlOi1l0lO_dataout XOR (wire_nlOi1l0ll_dataout XOR (wire_nlOi1l0iO_dataout XOR (wire_nlOi1li0l_dataout XOR (wire_nlOi1li0i_dataout XOR (wire_nlOi1li1O_dataout XOR (wire_nlOi1li1l_dataout XOR (wire_nlOi1li1i_dataout XOR (wire_nlOi1l0OO_dataout XOR (wire_nlOi1lill_dataout XOR (wire_nlOi1lili_dataout XOR (wire_nlOi1liiO_dataout XOR niOl11OlO))))))))))))))))) WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oli0i; + wire_nlO0OOllO_dataout <= wire_nlOi1l01i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oli0l; + wire_nlO0OOlOi_dataout <= wire_nlOi1l01l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oli0O; + wire_nlO0OOlOl_dataout <= wire_nlOi1l01O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oliii; + wire_nlO0OOlOO_dataout <= wire_nlOi1l00i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oliil; + wire_nlO0OOO0i_dataout <= wire_nlOi1l0il_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OlilO; + wire_nlO0OOO0l_dataout <= wire_nlOi1l0iO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OliOi; + wire_nlO0OOO0O_dataout <= wire_nlOi1l0li_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OliOl; + wire_nlO0OOO1i_dataout <= wire_nlOi1l00l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OliiO; + wire_nlO0OOO1l_dataout <= wire_nlOi1l00O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Olili; + wire_nlO0OOO1O_dataout <= wire_nlOi1l0ii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Olill; + wire_nlO0OOOii_dataout <= wire_nlOi1l0ll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OliOO; + wire_nlO0OOOil_dataout <= wire_nlOi1l0lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oll1i; + wire_nlO0OOOiO_dataout <= nlO0Oll1l AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlO0OOOli_dataout <= nlO0Oll1O AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlO0OOOll_dataout <= wire_nlOi1l0Oi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oll0i; + wire_nlO0OOOlO_dataout <= wire_nlOi1l0Ol_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oll0l; + wire_nlO0OOOOi_dataout <= wire_nlOi1l0OO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Oll0O; + wire_nlO0OOOOl_dataout <= wire_nlOi1li1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ollii; + wire_nlO0OOOOO_dataout <= wire_nlOi1li1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ollil; + wire_nlO1000i_dataout <= wire_nlO1iOOO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1il_dataout; + wire_nlO1000l_dataout <= wire_nlO1l11i_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1iO_dataout; + wire_nlO1000O_dataout <= wire_nlO1l11l_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1li_dataout; + wire_nlO1001i_dataout <= wire_nlO1iOlO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i10l_dataout; + wire_nlO1001l_dataout <= wire_nlO1iOOi_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i10O_dataout; + wire_nlO1001O_dataout <= wire_nlO1iOOl_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1ii_dataout; + wire_nlO100ii_dataout <= wire_nlO1l11O_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1ll_dataout; + wire_nlO100il_dataout <= wire_nlO1l10i_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1lO_dataout; + wire_nlO100iO_dataout <= wire_nlO1l10l_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1Oi_dataout; + wire_nlO100li_dataout <= wire_nlO1l10O_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1Ol_dataout; + wire_nlO100ll_dataout <= wire_nlO1l1ii_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i1OO_dataout; + wire_nlO100lO_dataout <= wire_nlO1l1il_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i01i_dataout; + wire_nlO100Oi_dataout <= wire_nlO1l1iO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i01l_dataout; + wire_nlO100Ol_dataout <= wire_nlO1l1li_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i01O_dataout; + wire_nlO100OO_dataout <= wire_nlO1l1ll_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i00i_dataout; + wire_nlO1010i_dataout <= wire_nlO1ilOO_dataout WHEN niOO001OO = '1' ELSE wire_nlO10Oil_dataout; + wire_nlO1010l_dataout <= wire_nlO1iO1i_dataout WHEN niOO001OO = '1' ELSE wire_nlO10OiO_dataout; + wire_nlO1010O_dataout <= wire_nlO1iO1l_dataout WHEN niOO001OO = '1' ELSE wire_nlO10Oli_dataout; + wire_nlO1011i_dataout <= wire_nlO1illO_dataout WHEN niOO001OO = '1' ELSE wire_nlO10O0l_dataout; + wire_nlO1011l_dataout <= wire_nlO1ilOi_dataout WHEN niOO001OO = '1' ELSE wire_nlO10O0O_dataout; + wire_nlO1011O_dataout <= wire_nlO1ilOl_dataout WHEN niOO001OO = '1' ELSE wire_nlO10Oii_dataout; + wire_nlO101ii_dataout <= wire_nlO1iO1O_dataout WHEN niOO001OO = '1' ELSE wire_nlO10Oll_dataout; + wire_nlO101il_dataout <= wire_nlO1iO0i_dataout WHEN niOO001OO = '1' ELSE wire_nlO10OlO_dataout; + wire_nlO101iO_dataout <= wire_nlO1iO0l_dataout WHEN niOO001OO = '1' ELSE wire_nlO10OOi_dataout; + wire_nlO101li_dataout <= wire_nlO1iO0O_dataout WHEN niOO001OO = '1' ELSE wire_nlO10OOl_dataout; + wire_nlO101ll_dataout <= wire_nlO1iOii_dataout WHEN niOO001OO = '1' ELSE wire_nlO10OOO_dataout; + wire_nlO101lO_dataout <= wire_nlO1iOil_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i11i_dataout; + wire_nlO101Oi_dataout <= wire_nlO1iOiO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i11l_dataout; + wire_nlO101Ol_dataout <= wire_nlO1iOli_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i11O_dataout; + wire_nlO101OO_dataout <= wire_nlO1iOll_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i10i_dataout; + wire_nlO10i0i_dataout <= wire_nlO1l1OO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0il_dataout; + wire_nlO10i0l_dataout <= wire_nlO1l01i_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0iO_dataout; + wire_nlO10i0O_dataout <= wire_nlO1l01l_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0li_dataout; + wire_nlO10i1i_dataout <= wire_nlO1l1lO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i00l_dataout; + wire_nlO10i1l_dataout <= wire_nlO1l1Oi_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i00O_dataout; + wire_nlO10i1O_dataout <= wire_nlO1l1Ol_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0ii_dataout; + wire_nlO10iii_dataout <= wire_nlO1l01O_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0ll_dataout; + wire_nlO10iil_dataout <= wire_nlO1l00i_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0lO_dataout; + wire_nlO10iiO_dataout <= wire_nlO1l00l_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0Oi_dataout; + wire_nlO10ili_dataout <= wire_nlO1l00O_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0Ol_dataout; + wire_nlO10ill_dataout <= wire_nlO1l0ii_dataout WHEN niOO001OO = '1' ELSE wire_nlO1i0OO_dataout; + wire_nlO10ilO_dataout <= wire_nlO1l0il_dataout WHEN niOO001OO = '1' ELSE wire_nlO1ii1i_dataout; + wire_nlO10iOi_dataout <= wire_nlO1l0iO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1ii1l_dataout; + wire_nlO10iOl_dataout <= wire_nlO1l0li_dataout WHEN niOO001OO = '1' ELSE wire_nlO1ii1O_dataout; + wire_nlO10iOO_dataout <= wire_nlO1l0ll_dataout WHEN niOO001OO = '1' ELSE wire_nlO1ii0i_dataout; + wire_nlO10l0i_dataout <= wire_nlO1l0OO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1iiil_dataout; + wire_nlO10l0l_dataout <= wire_nlO1li1i_dataout WHEN niOO001OO = '1' ELSE wire_nlO1iiiO_dataout; + wire_nlO10l0O_dataout <= wire_nlO1li1l_dataout WHEN niOO001OO = '1' ELSE wire_nlO1iili_dataout; + wire_nlO10l1i_dataout <= wire_nlO1l0lO_dataout WHEN niOO001OO = '1' ELSE wire_nlO1ii0l_dataout; + wire_nlO10l1l_dataout <= wire_nlO1l0Oi_dataout WHEN niOO001OO = '1' ELSE wire_nlO1ii0O_dataout; + wire_nlO10l1O_dataout <= wire_nlO1l0Ol_dataout WHEN niOO001OO = '1' ELSE wire_nlO1iiii_dataout; + wire_nlO10lii_dataout <= nlO1iiOi WHEN niOO001Ol = '1' ELSE wire_nlO011Ol_dataout; + wire_nlO10lil_dataout <= nlllOlll WHEN niOO001Ol = '1' ELSE wire_nlO011OO_dataout; + wire_nlO10liO_dataout <= nlllOllO WHEN niOO001Ol = '1' ELSE wire_nlO0101i_dataout; + wire_nlO10lli_dataout <= nlllOlOi WHEN niOO001Ol = '1' ELSE wire_nlO0101l_dataout; + wire_nlO10lll_dataout <= nlllOlOl WHEN niOO001Ol = '1' ELSE wire_nlO0101O_dataout; + wire_nlO10llO_dataout <= nlllOlOO WHEN niOO001Ol = '1' ELSE wire_nlO0100i_dataout; + wire_nlO10lOi_dataout <= nlllOO1i WHEN niOO001Ol = '1' ELSE wire_nlO0100l_dataout; + wire_nlO10lOl_dataout <= nlllOO1l WHEN niOO001Ol = '1' ELSE wire_nlO0100O_dataout; + wire_nlO10lOO_dataout <= nlllOO1O WHEN niOO001Ol = '1' ELSE wire_nlO010ii_dataout; + wire_nlO10O0i_dataout <= nlllOOii WHEN niOO001Ol = '1' ELSE wire_nlO010ll_dataout; + wire_nlO10O0l_dataout <= nlllOOil WHEN niOO001Ol = '1' ELSE wire_nlO010lO_dataout; + wire_nlO10O0O_dataout <= nlllOOiO WHEN niOO001Ol = '1' ELSE wire_nlO010Oi_dataout; + wire_nlO10O1i_dataout <= nlllOO0i WHEN niOO001Ol = '1' ELSE wire_nlO010il_dataout; + wire_nlO10O1l_dataout <= nlllOO0l WHEN niOO001Ol = '1' ELSE wire_nlO010iO_dataout; + wire_nlO10O1O_dataout <= nlllOO0O WHEN niOO001Ol = '1' ELSE wire_nlO010li_dataout; + wire_nlO10Oii_dataout <= nlllOOli WHEN niOO001Ol = '1' ELSE wire_nlO010Ol_dataout; + wire_nlO10Oil_dataout <= nlllOOll WHEN niOO001Ol = '1' ELSE wire_nlO010OO_dataout; + wire_nlO10OiO_dataout <= nlllOOlO WHEN niOO001Ol = '1' ELSE wire_nlO01i1i_dataout; + wire_nlO10Oli_dataout <= nlllOOOi WHEN niOO001Ol = '1' ELSE wire_nlO01i1l_dataout; + wire_nlO10Oll_dataout <= nlllOOOl WHEN niOO001Ol = '1' ELSE wire_nlO01i1O_dataout; + wire_nlO10OlO_dataout <= nlllOOOO WHEN niOO001Ol = '1' ELSE wire_nlO01i0i_dataout; + wire_nlO10OOi_dataout <= nllO111i WHEN niOO001Ol = '1' ELSE wire_nlO01i0l_dataout; + wire_nlO10OOl_dataout <= nllO111l WHEN niOO001Ol = '1' ELSE wire_nlO01i0O_dataout; + wire_nlO10OOO_dataout <= nllO111O WHEN niOO001Ol = '1' ELSE wire_nlO01iii_dataout; + wire_nlO1100i_dataout <= wire_nlO1OiOi_dataout WHEN niOO0001i = '1' ELSE wire_nlO101il_dataout; + wire_nlO1100l_dataout <= wire_nlO1OiOl_dataout WHEN niOO0001i = '1' ELSE wire_nlO101iO_dataout; + wire_nlO1100O_dataout <= wire_nlO1OiOO_dataout WHEN niOO0001i = '1' ELSE wire_nlO101li_dataout; + wire_nlO1101i_dataout <= wire_nlO1Oili_dataout WHEN niOO0001i = '1' ELSE wire_nlO1010l_dataout; + wire_nlO1101l_dataout <= wire_nlO1Oill_dataout WHEN niOO0001i = '1' ELSE wire_nlO1010O_dataout; + wire_nlO1101O_dataout <= wire_nlO1OilO_dataout WHEN niOO0001i = '1' ELSE wire_nlO101ii_dataout; + wire_nlO110ii_dataout <= wire_nlO1Ol1i_dataout WHEN niOO0001i = '1' ELSE wire_nlO101ll_dataout; + wire_nlO110il_dataout <= wire_nlO1Ol1l_dataout WHEN niOO0001i = '1' ELSE wire_nlO101lO_dataout; + wire_nlO110iO_dataout <= wire_nlO1Ol1O_dataout WHEN niOO0001i = '1' ELSE wire_nlO101Oi_dataout; + wire_nlO110li_dataout <= wire_nlO1Ol0i_dataout WHEN niOO0001i = '1' ELSE wire_nlO101Ol_dataout; + wire_nlO110ll_dataout <= wire_nlO1Ol0l_dataout WHEN niOO0001i = '1' ELSE wire_nlO101OO_dataout; + wire_nlO110lO_dataout <= wire_nlO1Ol0O_dataout WHEN niOO0001i = '1' ELSE wire_nlO1001i_dataout; + wire_nlO110Oi_dataout <= wire_nlO1Olii_dataout WHEN niOO0001i = '1' ELSE wire_nlO1001l_dataout; + wire_nlO110Ol_dataout <= wire_nlO1Olil_dataout WHEN niOO0001i = '1' ELSE wire_nlO1001O_dataout; + wire_nlO110OO_dataout <= wire_nlO1OliO_dataout WHEN niOO0001i = '1' ELSE wire_nlO1000i_dataout; + wire_nlO1110i_dataout <= wire_nlO1O0Oi_dataout WHEN niOO0001i = '1' ELSE wire_nlO11Oil_dataout; + wire_nlO1110l_dataout <= wire_nlO1O0Ol_dataout WHEN niOO0001i = '1' ELSE wire_nlO11OiO_dataout; + wire_nlO1110O_dataout <= wire_nlO1O0OO_dataout WHEN niOO0001i = '1' ELSE wire_nlO11Oli_dataout; + wire_nlO1111i_dataout <= wire_nlO1O0li_dataout WHEN niOO0001i = '1' ELSE wire_nlO11O0l_dataout; + wire_nlO1111l_dataout <= wire_nlO1O0ll_dataout WHEN niOO0001i = '1' ELSE wire_nlO11O0O_dataout; + wire_nlO1111O_dataout <= wire_nlO1O0lO_dataout WHEN niOO0001i = '1' ELSE wire_nlO11Oii_dataout; + wire_nlO111ii_dataout <= wire_nlO1Oi1i_dataout WHEN niOO0001i = '1' ELSE wire_nlO11Oll_dataout; + wire_nlO111il_dataout <= wire_nlO1Oi1l_dataout WHEN niOO0001i = '1' ELSE wire_nlO11OlO_dataout; + wire_nlO111iO_dataout <= wire_nlO1Oi1O_dataout WHEN niOO0001i = '1' ELSE wire_nlO11OOi_dataout; + wire_nlO111li_dataout <= wire_nlO1Oi0i_dataout WHEN niOO0001i = '1' ELSE wire_nlO11OOl_dataout; + wire_nlO111ll_dataout <= wire_nlO1Oi0l_dataout WHEN niOO0001i = '1' ELSE wire_nlO11OOO_dataout; + wire_nlO111lO_dataout <= wire_nlO1Oi0O_dataout WHEN niOO0001i = '1' ELSE wire_nlO1011i_dataout; + wire_nlO111Oi_dataout <= wire_nlO1Oiii_dataout WHEN niOO0001i = '1' ELSE wire_nlO1011l_dataout; + wire_nlO111Ol_dataout <= wire_nlO1Oiil_dataout WHEN niOO0001i = '1' ELSE wire_nlO1011O_dataout; + wire_nlO111OO_dataout <= wire_nlO1OiiO_dataout WHEN niOO0001i = '1' ELSE wire_nlO1010i_dataout; + wire_nlO11i0i_dataout <= wire_nlO1OlOi_dataout WHEN niOO0001i = '1' ELSE wire_nlO100il_dataout; + wire_nlO11i0l_dataout <= wire_nlO1OlOl_dataout WHEN niOO0001i = '1' ELSE wire_nlO100iO_dataout; + wire_nlO11i0O_dataout <= wire_nlO1OlOO_dataout WHEN niOO0001i = '1' ELSE wire_nlO100li_dataout; + wire_nlO11i1i_dataout <= wire_nlO1Olli_dataout WHEN niOO0001i = '1' ELSE wire_nlO1000l_dataout; + wire_nlO11i1l_dataout <= wire_nlO1Olll_dataout WHEN niOO0001i = '1' ELSE wire_nlO1000O_dataout; + wire_nlO11i1O_dataout <= wire_nlO1OllO_dataout WHEN niOO0001i = '1' ELSE wire_nlO100ii_dataout; + wire_nlO11iii_dataout <= wire_nlO1OO1i_dataout WHEN niOO0001i = '1' ELSE wire_nlO100ll_dataout; + wire_nlO11iil_dataout <= wire_nlO1OO1l_dataout WHEN niOO0001i = '1' ELSE wire_nlO100lO_dataout; + wire_nlO11iiO_dataout <= wire_nlO1OO1O_dataout WHEN niOO0001i = '1' ELSE wire_nlO100Oi_dataout; + wire_nlO11ili_dataout <= wire_nlO1OO0i_dataout WHEN niOO0001i = '1' ELSE wire_nlO100Ol_dataout; + wire_nlO11ill_dataout <= wire_nlO1OO0l_dataout WHEN niOO0001i = '1' ELSE wire_nlO100OO_dataout; + wire_nlO11ilO_dataout <= wire_nlO1OO0O_dataout WHEN niOO0001i = '1' ELSE wire_nlO10i1i_dataout; + wire_nlO11iOi_dataout <= wire_nlO1OOii_dataout WHEN niOO0001i = '1' ELSE wire_nlO10i1l_dataout; + wire_nlO11iOl_dataout <= wire_nlO1OOil_dataout WHEN niOO0001i = '1' ELSE wire_nlO10i1O_dataout; + wire_nlO11iOO_dataout <= wire_nlO1OOiO_dataout WHEN niOO0001i = '1' ELSE wire_nlO10i0i_dataout; + wire_nlO11l0i_dataout <= wire_nlO1OOOi_dataout WHEN niOO0001i = '1' ELSE wire_nlO10iil_dataout; + wire_nlO11l0l_dataout <= wire_nlO1OOOl_dataout WHEN niOO0001i = '1' ELSE wire_nlO10iiO_dataout; + wire_nlO11l0O_dataout <= wire_nlO1OOOO_dataout WHEN niOO0001i = '1' ELSE wire_nlO10ili_dataout; + wire_nlO11l1i_dataout <= wire_nlO1OOli_dataout WHEN niOO0001i = '1' ELSE wire_nlO10i0l_dataout; + wire_nlO11l1l_dataout <= wire_nlO1OOll_dataout WHEN niOO0001i = '1' ELSE wire_nlO10i0O_dataout; + wire_nlO11l1O_dataout <= wire_nlO1OOlO_dataout WHEN niOO0001i = '1' ELSE wire_nlO10iii_dataout; + wire_nlO11lii_dataout <= wire_nlO0111i_dataout WHEN niOO0001i = '1' ELSE wire_nlO10ill_dataout; + wire_nlO11lil_dataout <= wire_nlO0111l_dataout WHEN niOO0001i = '1' ELSE wire_nlO10ilO_dataout; + wire_nlO11liO_dataout <= wire_nlO0111O_dataout WHEN niOO0001i = '1' ELSE wire_nlO10iOi_dataout; + wire_nlO11lli_dataout <= wire_nlO0110i_dataout WHEN niOO0001i = '1' ELSE wire_nlO10iOl_dataout; + wire_nlO11lll_dataout <= wire_nlO0110l_dataout WHEN niOO0001i = '1' ELSE wire_nlO10iOO_dataout; + wire_nlO11llO_dataout <= wire_nlO0110O_dataout WHEN niOO0001i = '1' ELSE wire_nlO10l1i_dataout; + wire_nlO11lOi_dataout <= wire_nlO011ii_dataout WHEN niOO0001i = '1' ELSE wire_nlO10l1l_dataout; + wire_nlO11lOl_dataout <= wire_nlO011il_dataout WHEN niOO0001i = '1' ELSE wire_nlO10l1O_dataout; + wire_nlO11lOO_dataout <= wire_nlO011iO_dataout WHEN niOO0001i = '1' ELSE wire_nlO10l0i_dataout; + wire_nlO11O0i_dataout <= wire_nlO1iiOO_dataout WHEN niOO001OO = '1' ELSE wire_nlO10lil_dataout; + wire_nlO11O0l_dataout <= wire_nlO1il1i_dataout WHEN niOO001OO = '1' ELSE wire_nlO10liO_dataout; + wire_nlO11O0O_dataout <= wire_nlO1il1l_dataout WHEN niOO001OO = '1' ELSE wire_nlO10lli_dataout; + wire_nlO11O1i_dataout <= wire_nlO011li_dataout WHEN niOO0001i = '1' ELSE wire_nlO10l0l_dataout; + wire_nlO11O1l_dataout <= wire_nlO011ll_dataout WHEN niOO0001i = '1' ELSE wire_nlO10l0O_dataout; + wire_nlO11O1O_dataout <= wire_nlO1iiOl_dataout WHEN niOO001OO = '1' ELSE wire_nlO10lii_dataout; + wire_nlO11Oii_dataout <= wire_nlO1il1O_dataout WHEN niOO001OO = '1' ELSE wire_nlO10lll_dataout; + wire_nlO11Oil_dataout <= wire_nlO1il0i_dataout WHEN niOO001OO = '1' ELSE wire_nlO10llO_dataout; + wire_nlO11OiO_dataout <= wire_nlO1il0l_dataout WHEN niOO001OO = '1' ELSE wire_nlO10lOi_dataout; + wire_nlO11Oli_dataout <= wire_nlO1il0O_dataout WHEN niOO001OO = '1' ELSE wire_nlO10lOl_dataout; + wire_nlO11Oll_dataout <= wire_nlO1ilii_dataout WHEN niOO001OO = '1' ELSE wire_nlO10lOO_dataout; + wire_nlO11OlO_dataout <= wire_nlO1ilil_dataout WHEN niOO001OO = '1' ELSE wire_nlO10O1i_dataout; + wire_nlO11OOi_dataout <= wire_nlO1iliO_dataout WHEN niOO001OO = '1' ELSE wire_nlO10O1l_dataout; + wire_nlO11OOl_dataout <= wire_nlO1illi_dataout WHEN niOO001OO = '1' ELSE wire_nlO10O1O_dataout; + wire_nlO11OOO_dataout <= wire_nlO1illl_dataout WHEN niOO001OO = '1' ELSE wire_nlO10O0i_dataout; + wire_nlO1i00i_dataout <= nllO10ii WHEN niOO001Ol = '1' ELSE wire_nlO01lll_dataout; + wire_nlO1i00l_dataout <= nllO10il WHEN niOO001Ol = '1' ELSE wire_nlO01llO_dataout; + wire_nlO1i00O_dataout <= nllO10iO WHEN niOO001Ol = '1' ELSE wire_nlO01lOi_dataout; + wire_nlO1i01i_dataout <= nllO100i WHEN niOO001Ol = '1' ELSE wire_nlO01lil_dataout; + wire_nlO1i01l_dataout <= nllO100l WHEN niOO001Ol = '1' ELSE wire_nlO01liO_dataout; + wire_nlO1i01O_dataout <= nllO100O WHEN niOO001Ol = '1' ELSE wire_nlO01lli_dataout; + wire_nlO1i0ii_dataout <= nllO10li WHEN niOO001Ol = '1' ELSE wire_nlO01lOl_dataout; + wire_nlO1i0il_dataout <= nllO10ll WHEN niOO001Ol = '1' ELSE wire_nlO01lOO_dataout; + wire_nlO1i0iO_dataout <= nllO10lO WHEN niOO001Ol = '1' ELSE wire_nlO01O1i_dataout; + wire_nlO1i0li_dataout <= nllO10Oi WHEN niOO001Ol = '1' ELSE wire_nlO01O1l_dataout; + wire_nlO1i0ll_dataout <= nllO10Ol WHEN niOO001Ol = '1' ELSE wire_nlO01O1O_dataout; + wire_nlO1i0lO_dataout <= nllO10OO WHEN niOO001Ol = '1' ELSE wire_nlO01O0i_dataout; + wire_nlO1i0Oi_dataout <= nllO1i1i WHEN niOO001Ol = '1' ELSE wire_nlO01O0l_dataout; + wire_nlO1i0Ol_dataout <= nllO1i1l WHEN niOO001Ol = '1' ELSE wire_nlO01O0O_dataout; + wire_nlO1i0OO_dataout <= nllO1i1O WHEN niOO001Ol = '1' ELSE wire_nlO01Oii_dataout; + wire_nlO1i10i_dataout <= nllO11ii WHEN niOO001Ol = '1' ELSE wire_nlO01ill_dataout; + wire_nlO1i10l_dataout <= nllO11il WHEN niOO001Ol = '1' ELSE wire_nlO01ilO_dataout; + wire_nlO1i10O_dataout <= nllO11iO WHEN niOO001Ol = '1' ELSE wire_nlO01iOi_dataout; + wire_nlO1i11i_dataout <= nllO110i WHEN niOO001Ol = '1' ELSE wire_nlO01iil_dataout; + wire_nlO1i11l_dataout <= nllO110l WHEN niOO001Ol = '1' ELSE wire_nlO01iiO_dataout; + wire_nlO1i11O_dataout <= nllO110O WHEN niOO001Ol = '1' ELSE wire_nlO01ili_dataout; + wire_nlO1i1ii_dataout <= nllO11li WHEN niOO001Ol = '1' ELSE wire_nlO01iOl_dataout; + wire_nlO1i1il_dataout <= nllO11ll WHEN niOO001Ol = '1' ELSE wire_nlO01iOO_dataout; + wire_nlO1i1iO_dataout <= nllO11lO WHEN niOO001Ol = '1' ELSE wire_nlO01l1i_dataout; + wire_nlO1i1li_dataout <= nllO11Oi WHEN niOO001Ol = '1' ELSE wire_nlO01l1l_dataout; + wire_nlO1i1ll_dataout <= nllO11Ol WHEN niOO001Ol = '1' ELSE wire_nlO01l1O_dataout; + wire_nlO1i1lO_dataout <= nllO11OO WHEN niOO001Ol = '1' ELSE wire_nlO01l0i_dataout; + wire_nlO1i1Oi_dataout <= nllO101i WHEN niOO001Ol = '1' ELSE wire_nlO01l0l_dataout; + wire_nlO1i1Ol_dataout <= nllO101l WHEN niOO001Ol = '1' ELSE wire_nlO01l0O_dataout; + wire_nlO1i1OO_dataout <= nllO101O WHEN niOO001Ol = '1' ELSE wire_nlO01lii_dataout; + wire_nlO1ii0i_dataout <= nllO1iii WHEN niOO001Ol = '1' ELSE wire_nlO01Oll_dataout; + wire_nlO1ii0l_dataout <= nllO1iil WHEN niOO001Ol = '1' ELSE wire_nlO01OlO_dataout; + wire_nlO1ii0O_dataout <= nllO1iiO WHEN niOO001Ol = '1' ELSE wire_nlO01OOi_dataout; + wire_nlO1ii1i_dataout <= nllO1i0i WHEN niOO001Ol = '1' ELSE wire_nlO01Oil_dataout; + wire_nlO1ii1l_dataout <= nllO1i0l WHEN niOO001Ol = '1' ELSE wire_nlO01OiO_dataout; + wire_nlO1ii1O_dataout <= nllO1i0O WHEN niOO001Ol = '1' ELSE wire_nlO01Oli_dataout; + wire_nlO1iiii_dataout <= nllO1ili WHEN niOO001Ol = '1' ELSE wire_nlO01OOl_dataout; + wire_nlO1iiil_dataout <= nllO1ill WHEN niOO001Ol = '1' ELSE wire_nlO01OOO_dataout; + wire_nlO1iiiO_dataout <= nllO1ilO WHEN niOO001Ol = '1' ELSE wire_nlO0011i_dataout; + wire_nlO1iili_dataout <= nllO1iOi WHEN niOO001Ol = '1' ELSE wire_nlO0011l_dataout; + wire_nlO1iiOl_dataout <= wire_nlll0lli_q(0) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1li1O_dataout; + wire_nlO1iiOO_dataout <= wire_nlll0lli_q(1) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1li0i_dataout; + wire_nlO1il0i_dataout <= wire_nlll0lli_q(5) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1liil_dataout; + wire_nlO1il0l_dataout <= wire_nlll0lli_q(6) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1liiO_dataout; + wire_nlO1il0O_dataout <= wire_nlll0lli_q(7) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lili_dataout; + wire_nlO1il1i_dataout <= wire_nlll0lli_q(2) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1li0l_dataout; + wire_nlO1il1l_dataout <= wire_nlll0lli_q(3) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1li0O_dataout; + wire_nlO1il1O_dataout <= wire_nlll0lli_q(4) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1liii_dataout; + wire_nlO1ilii_dataout <= wire_nlll0lli_q(8) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lill_dataout; + wire_nlO1ilil_dataout <= wire_nlll0lli_q(9) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lilO_dataout; + wire_nlO1iliO_dataout <= wire_nlll0lli_q(10) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1liOi_dataout; + wire_nlO1illi_dataout <= wire_nlll0lli_q(11) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1liOl_dataout; + wire_nlO1illl_dataout <= wire_nlll0lli_q(12) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1liOO_dataout; + wire_nlO1illO_dataout <= wire_nlll0lli_q(13) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1ll1i_dataout; + wire_nlO1ilOi_dataout <= wire_nlll0lli_q(14) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1ll1l_dataout; + wire_nlO1ilOl_dataout <= wire_nlll0lli_q(15) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1ll1O_dataout; + wire_nlO1ilOO_dataout <= wire_nlll0lli_q(16) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1ll0i_dataout; + wire_nlO1iO0i_dataout <= wire_nlll0lli_q(20) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1llil_dataout; + wire_nlO1iO0l_dataout <= wire_nlll0lli_q(21) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lliO_dataout; + wire_nlO1iO0O_dataout <= wire_nlll0lli_q(22) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1llli_dataout; + wire_nlO1iO1i_dataout <= wire_nlll0lli_q(17) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1ll0l_dataout; + wire_nlO1iO1l_dataout <= wire_nlll0lli_q(18) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1ll0O_dataout; + wire_nlO1iO1O_dataout <= wire_nlll0lli_q(19) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1llii_dataout; + wire_nlO1iOii_dataout <= wire_nlll0lli_q(23) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1llll_dataout; + wire_nlO1iOil_dataout <= wire_nlll0lli_q(24) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lllO_dataout; + wire_nlO1iOiO_dataout <= wire_nlll0lli_q(25) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1llOi_dataout; + wire_nlO1iOli_dataout <= wire_nlll0lli_q(26) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1llOl_dataout; + wire_nlO1iOll_dataout <= wire_nlll0lli_q(27) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1llOO_dataout; + wire_nlO1iOlO_dataout <= wire_nlll0lli_q(28) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lO1i_dataout; + wire_nlO1iOOi_dataout <= wire_nlll0lli_q(29) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lO1l_dataout; + wire_nlO1iOOl_dataout <= wire_nlll0lli_q(30) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lO1O_dataout; + wire_nlO1iOOO_dataout <= wire_nlll0lli_q(31) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lO0i_dataout; + wire_nlO1l00i_dataout <= wire_nlll0lli_q(50) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1il_dataout; + wire_nlO1l00l_dataout <= wire_nlll0lli_q(51) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1iO_dataout; + wire_nlO1l00O_dataout <= wire_nlll0lli_q(52) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1li_dataout; + wire_nlO1l01i_dataout <= wire_nlll0lli_q(47) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O10l_dataout; + wire_nlO1l01l_dataout <= wire_nlll0lli_q(48) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O10O_dataout; + wire_nlO1l01O_dataout <= wire_nlll0lli_q(49) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1ii_dataout; + wire_nlO1l0ii_dataout <= wire_nlll0lli_q(53) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1ll_dataout; + wire_nlO1l0il_dataout <= wire_nlll0lli_q(54) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1lO_dataout; + wire_nlO1l0iO_dataout <= wire_nlll0lli_q(55) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1Oi_dataout; + wire_nlO1l0li_dataout <= wire_nlll0lli_q(56) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1Ol_dataout; + wire_nlO1l0ll_dataout <= wire_nlll0lli_q(57) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O1OO_dataout; + wire_nlO1l0lO_dataout <= wire_nlll0lli_q(58) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O01i_dataout; + wire_nlO1l0Oi_dataout <= wire_nlll0lli_q(59) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O01l_dataout; + wire_nlO1l0Ol_dataout <= wire_nlll0lli_q(60) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O01O_dataout; + wire_nlO1l0OO_dataout <= wire_nlll0lli_q(61) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O00i_dataout; + wire_nlO1l10i_dataout <= wire_nlll0lli_q(35) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOil_dataout; + wire_nlO1l10l_dataout <= wire_nlll0lli_q(36) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOiO_dataout; + wire_nlO1l10O_dataout <= wire_nlll0lli_q(37) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOli_dataout; + wire_nlO1l11i_dataout <= wire_nlll0lli_q(32) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lO0l_dataout; + wire_nlO1l11l_dataout <= wire_nlll0lli_q(33) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lO0O_dataout; + wire_nlO1l11O_dataout <= wire_nlll0lli_q(34) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOii_dataout; + wire_nlO1l1ii_dataout <= wire_nlll0lli_q(38) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOll_dataout; + wire_nlO1l1il_dataout <= wire_nlll0lli_q(39) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOlO_dataout; + wire_nlO1l1iO_dataout <= wire_nlll0lli_q(40) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOOi_dataout; + wire_nlO1l1li_dataout <= wire_nlll0lli_q(41) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOOl_dataout; + wire_nlO1l1ll_dataout <= wire_nlll0lli_q(42) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1lOOO_dataout; + wire_nlO1l1lO_dataout <= wire_nlll0lli_q(43) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O11i_dataout; + wire_nlO1l1Oi_dataout <= wire_nlll0lli_q(44) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O11l_dataout; + wire_nlO1l1Ol_dataout <= wire_nlll0lli_q(45) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O11O_dataout; + wire_nlO1l1OO_dataout <= wire_nlll0lli_q(46) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O10i_dataout; + wire_nlO1li0i_dataout <= wire_nlll0lli_q(65) WHEN nlO0lliO = '1' ELSE wire_nlO011OO_dataout; + wire_nlO1li0l_dataout <= wire_nlll0lli_q(66) WHEN nlO0lliO = '1' ELSE wire_nlO0101i_dataout; + wire_nlO1li0O_dataout <= wire_nlll0lli_q(67) WHEN nlO0lliO = '1' ELSE wire_nlO0101l_dataout; + wire_nlO1li1i_dataout <= wire_nlll0lli_q(62) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O00l_dataout; + wire_nlO1li1l_dataout <= wire_nlll0lli_q(63) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE wire_nlO1O00O_dataout; + wire_nlO1li1O_dataout <= wire_nlll0lli_q(64) WHEN nlO0lliO = '1' ELSE wire_nlO011Ol_dataout; + wire_nlO1liii_dataout <= wire_nlll0lli_q(68) WHEN nlO0lliO = '1' ELSE wire_nlO0101O_dataout; + wire_nlO1liil_dataout <= wire_nlll0lli_q(69) WHEN nlO0lliO = '1' ELSE wire_nlO0100i_dataout; + wire_nlO1liiO_dataout <= wire_nlll0lli_q(70) WHEN nlO0lliO = '1' ELSE wire_nlO0100l_dataout; + wire_nlO1lili_dataout <= wire_nlll0lli_q(71) WHEN nlO0lliO = '1' ELSE wire_nlO0100O_dataout; + wire_nlO1lill_dataout <= wire_nlll0lli_q(72) WHEN nlO0lliO = '1' ELSE wire_nlO010ii_dataout; + wire_nlO1lilO_dataout <= wire_nlll0lli_q(73) WHEN nlO0lliO = '1' ELSE wire_nlO010il_dataout; + wire_nlO1liOi_dataout <= wire_nlll0lli_q(74) WHEN nlO0lliO = '1' ELSE wire_nlO010iO_dataout; + wire_nlO1liOl_dataout <= wire_nlll0lli_q(75) WHEN nlO0lliO = '1' ELSE wire_nlO010li_dataout; + wire_nlO1liOO_dataout <= wire_nlll0lli_q(76) WHEN nlO0lliO = '1' ELSE wire_nlO010ll_dataout; + wire_nlO1ll0i_dataout <= wire_nlll0lli_q(80) WHEN nlO0lliO = '1' ELSE wire_nlO010OO_dataout; + wire_nlO1ll0l_dataout <= wire_nlll0lli_q(81) WHEN nlO0lliO = '1' ELSE wire_nlO01i1i_dataout; + wire_nlO1ll0O_dataout <= wire_nlll0lli_q(82) WHEN nlO0lliO = '1' ELSE wire_nlO01i1l_dataout; + wire_nlO1ll1i_dataout <= wire_nlll0lli_q(77) WHEN nlO0lliO = '1' ELSE wire_nlO010lO_dataout; + wire_nlO1ll1l_dataout <= wire_nlll0lli_q(78) WHEN nlO0lliO = '1' ELSE wire_nlO010Oi_dataout; + wire_nlO1ll1O_dataout <= wire_nlll0lli_q(79) WHEN nlO0lliO = '1' ELSE wire_nlO010Ol_dataout; + wire_nlO1llii_dataout <= wire_nlll0lli_q(83) WHEN nlO0lliO = '1' ELSE wire_nlO01i1O_dataout; + wire_nlO1llil_dataout <= wire_nlll0lli_q(84) WHEN nlO0lliO = '1' ELSE wire_nlO01i0i_dataout; + wire_nlO1lliO_dataout <= wire_nlll0lli_q(85) WHEN nlO0lliO = '1' ELSE wire_nlO01i0l_dataout; + wire_nlO1llli_dataout <= wire_nlll0lli_q(86) WHEN nlO0lliO = '1' ELSE wire_nlO01i0O_dataout; + wire_nlO1llll_dataout <= wire_nlll0lli_q(87) WHEN nlO0lliO = '1' ELSE wire_nlO01iii_dataout; + wire_nlO1lllO_dataout <= wire_nlll0lli_q(88) WHEN nlO0lliO = '1' ELSE wire_nlO01iil_dataout; + wire_nlO1llOi_dataout <= wire_nlll0lli_q(89) WHEN nlO0lliO = '1' ELSE wire_nlO01iiO_dataout; + wire_nlO1llOl_dataout <= wire_nlll0lli_q(90) WHEN nlO0lliO = '1' ELSE wire_nlO01ili_dataout; + wire_nlO1llOO_dataout <= wire_nlll0lli_q(91) WHEN nlO0lliO = '1' ELSE wire_nlO01ill_dataout; + wire_nlO1lO0i_dataout <= wire_nlll0lli_q(95) WHEN nlO0lliO = '1' ELSE wire_nlO01iOO_dataout; + wire_nlO1lO0l_dataout <= wire_nlll0lli_q(96) WHEN nlO0lliO = '1' ELSE wire_nlO01l1i_dataout; + wire_nlO1lO0O_dataout <= wire_nlll0lli_q(97) WHEN nlO0lliO = '1' ELSE wire_nlO01l1l_dataout; + wire_nlO1lO1i_dataout <= wire_nlll0lli_q(92) WHEN nlO0lliO = '1' ELSE wire_nlO01ilO_dataout; + wire_nlO1lO1l_dataout <= wire_nlll0lli_q(93) WHEN nlO0lliO = '1' ELSE wire_nlO01iOi_dataout; + wire_nlO1lO1O_dataout <= wire_nlll0lli_q(94) WHEN nlO0lliO = '1' ELSE wire_nlO01iOl_dataout; + wire_nlO1lOii_dataout <= wire_nlll0lli_q(98) WHEN nlO0lliO = '1' ELSE wire_nlO01l1O_dataout; + wire_nlO1lOil_dataout <= wire_nlll0lli_q(99) WHEN nlO0lliO = '1' ELSE wire_nlO01l0i_dataout; + wire_nlO1lOiO_dataout <= wire_nlll0lli_q(100) WHEN nlO0lliO = '1' ELSE wire_nlO01l0l_dataout; + wire_nlO1lOli_dataout <= wire_nlll0lli_q(101) WHEN nlO0lliO = '1' ELSE wire_nlO01l0O_dataout; + wire_nlO1lOll_dataout <= wire_nlll0lli_q(102) WHEN nlO0lliO = '1' ELSE wire_nlO01lii_dataout; + wire_nlO1lOlO_dataout <= wire_nlll0lli_q(103) WHEN nlO0lliO = '1' ELSE wire_nlO01lil_dataout; + wire_nlO1lOOi_dataout <= wire_nlll0lli_q(104) WHEN nlO0lliO = '1' ELSE wire_nlO01liO_dataout; + wire_nlO1lOOii_dataout <= wire_nlO1O10iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOil_dataout <= wire_nlO1O10li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOiO_dataout <= wire_nlO1O10ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOl_dataout <= wire_nlll0lli_q(105) WHEN nlO0lliO = '1' ELSE wire_nlO01lli_dataout; + wire_nlO1lOOli_dataout <= wire_nlO1O10lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOll_dataout <= wire_nlO1O10Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOlO_dataout <= wire_nlO1O10Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOO_dataout <= wire_nlll0lli_q(106) WHEN nlO0lliO = '1' ELSE wire_nlO01lll_dataout; + wire_nlO1lOOOi_dataout <= wire_nlO1O10OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOOl_dataout <= wire_nlO1O1i1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1lOOOO_dataout <= wire_nlO1O1i1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O000i_dataout <= niOl111Ol WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOl1i XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOill XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (niOiOO0ii XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOO1lO))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O000l_dataout <= niOl111Oi WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOl1i XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOilO XOR (nlO1lOili XOR (nlO1lOiii XOR (nlO1O0l1i XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (niOiOO0ii XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR wire_nlO0i0i1i_dataout))))))))))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O000O_dataout <= niOl110Oi WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOllO XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOl1i XOR (nlO1lOiOO XOR (nlO1lOiOi XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1l_dataout XOR (wire_nlO0i0i1i_dataout XOR niOiOO1il)))))))))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O001i_dataout <= niOl1101l WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOl1O XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO1Ol))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O001l_dataout <= niOl1101i WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOi0O XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (niOiOO0ii XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOO1il)))))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O001O_dataout <= niOl111OO WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOili XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (niOiOO0ii XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR niOiOO1ll)))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00i_dataout <= wire_nlll0lli_q(125) WHEN nlO0lliO = '1' ELSE wire_nlO01OOO_dataout; + wire_nlO1O00ii_dataout <= niOl110lO WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOi XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (niOiOO0ii XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO1OO)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00il_dataout <= niOl110ll WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOlli XOR (nlO1lOlil XOR (nlO1lOiOO XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR niOiOO1iO))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00iO_dataout <= niOl110li WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOiiO XOR (nlO1lOi0O XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i000i_dataout XOR (niOiOO0ii XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOO1li)))))))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00l_dataout <= wire_nlll0lli_q(126) WHEN nlO0lliO = '1' ELSE wire_nlO0011i_dataout; + wire_nlO1O00li_dataout <= niOl110iO WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (niOiOO0ii XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOO1ll)))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00ll_dataout <= niOl110il WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1i XOR (nlO1lOiOO XOR (nlO1O0l1i XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO1lO)))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00lO_dataout <= niOl110ii WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR niOiOO0il)))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00O_dataout <= wire_nlll0lli_q(127) WHEN nlO0lliO = '1' ELSE wire_nlO0011l_dataout; + wire_nlO1O00Oi_dataout <= niOl1100O WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOO0iO))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O00Ol_dataout <= niOl11i0O WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOliO XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOili XOR (nlO1lOiil XOR (nlO1O0l1i XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i0i0l_dataout XOR wire_nlO0i0i0i_dataout))))))))))))))))))))))))))))))))); + wire_nlO1O00OO_dataout <= niOl11i0l WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlli XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOill XOR (nlO1lOiiO XOR (nlO1lOi0O XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0i_dataout XOR wire_nlO0i0i1O_dataout))))))))))))))))))))))))))))))))); + wire_nlO1O010i_dataout <= wire_nlO1O0i0O_dataout OR nlO00O11l; + wire_nlO1O010l_dataout <= wire_nlO1O0iii_dataout OR nlO00O11l; + wire_nlO1O010O_dataout <= wire_nlO1O0iil_dataout OR nlO00O11l; + wire_nlO1O011i_dataout <= wire_nlO1O0i1O_dataout OR nlO00O11l; + wire_nlO1O011l_dataout <= wire_nlO1O0i0i_dataout OR nlO00O11l; + wire_nlO1O011O_dataout <= wire_nlO1O0i0l_dataout OR nlO00O11l; + wire_nlO1O01i_dataout <= wire_nlll0lli_q(122) WHEN nlO0lliO = '1' ELSE wire_nlO01OlO_dataout; + wire_nlO1O01ii_dataout <= wire_nlO1O0iiO_dataout OR nlO00O11l; + wire_nlO1O01il_dataout <= wire_nlO1O0ili_dataout OR nlO00O11l; + wire_nlO1O01iO_dataout <= wire_nlO1O0ill_dataout OR nlO00O11l; + wire_nlO1O01l_dataout <= wire_nlll0lli_q(123) WHEN nlO0lliO = '1' ELSE wire_nlO01OOi_dataout; + wire_nlO1O01li_dataout <= wire_nlO1O0ilO_dataout OR nlO00O11l; + wire_nlO1O01ll_dataout <= wire_nlO1O0iOi_dataout OR nlO00O11l; + wire_nlO1O01lO_dataout <= wire_nlO1O0iOl_dataout OR nlO00O11l; + wire_nlO1O01O_dataout <= wire_nlll0lli_q(124) WHEN nlO0lliO = '1' ELSE wire_nlO01OOl_dataout; + wire_nlO1O01Oi_dataout <= niOl1100l WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOili XOR (nlO1lOiii XOR (nlO1O0l1i XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO01l)))))))))))))))))))))))))))))))))))))))); + wire_nlO1O01Ol_dataout <= niOl1100i WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlll XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiil XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOO1iO))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O01OO_dataout <= niOl1101O WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOl1l XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1O0l1i XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR niOiOO1li))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0i0i_dataout <= niOl11i1i WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOlOl XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlii XOR (nlO1lOiOO XOR (nlO1lOiOi XOR (nlO1lOili XOR (nlO1lOiil XOR (nlO1lOiii XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOO01O)))))))))))))))))))))))))))))))))); + wire_nlO1O0i0l_dataout <= niOl110OO WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOlli XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOiii XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (niOiOO0ii XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO00i))))))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0i0O_dataout <= niOl110Ol WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOiOO XOR (nlO1lOilO XOR (nlO1lOill XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1lOiii XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR niOiOO01i))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0i1i_dataout <= niOl11i0i WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlll XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl0i XOR (nlO1lOilO XOR (nlO1lOili XOR (nlO1lOiii XOR (nlO1O0l1i XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOO1Oi))))))))))))))))))))))))))))))))); + wire_nlO1O0i1l_dataout <= niOl11i1O WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOllO XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOiOi XOR (nlO1lOill XOR (nlO1lOiil XOR (nlO1lOi0O XOR (nlO1O0l1i XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR niOiOO1Ol)))))))))))))))))))))))))))))))))); + wire_nlO1O0i1O_dataout <= niOl11i1l WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOlOi XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOiOl XOR (nlO1lOilO XOR (nlO1lOiiO XOR (nlO1lOiii XOR (nlO1lOi0O XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01iO_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010i_dataout XOR (niOiOO0ii XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR niOiOO1OO)))))))))))))))))))))))))))))))))); + wire_nlO1O0iii_dataout <= niOl11iOl WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1i XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOiil XOR (nlO1O0l1i XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1OiO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR niOiOO01l)))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0iil_dataout <= niOl11iOi WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl1l XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOill XOR (nlO1lOili XOR (nlO1lOiiO XOR (nlO1lOi0O XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1Oil_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i010O_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i000i_dataout XOR (niOiOO0ii XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO01O))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0iiO_dataout <= niOl11ilO WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOllO XOR (nlO1lOlli XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl0l XOR (nlO1lOl1l XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOilO XOR (nlO1lOill XOR (wire_nlO0i1lil_dataout XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1Oii_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i010l_dataout XOR (wire_nlO0i010i_dataout XOR (niOiOO0ii XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOO00i)))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0il_dataout <= wire_nlll0lli_q(64) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlO1iiOi; + wire_nlO1O0ili_dataout <= niOl11ill WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlOi XOR (nlO1lOlll XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0O XOR (nlO1lOl1O XOR (nlO1lOl1i XOR (nlO1lOiOO XOR (nlO1lOiOi XOR (nlO1lOilO XOR (nlO1O0l1i XOR (wire_nlO0i1lii_dataout XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1O0O_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i010i_dataout XOR (wire_nlO0i000i_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i1O_dataout XOR (wire_nlO0i0i1i_dataout XOR niOiOO00l))))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0ill_dataout <= niOl11ili WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOlOl XOR (nlO1lOllO XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOlii XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiOl XOR (nlO1lOiOi XOR (nlO1lOi0O XOR (wire_nlO0i1l0O_dataout XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1llO_dataout XOR (wire_nlO0i1O0l_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i000i_dataout XOR (niOiOO0ii XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i000O_dataout XOR (wire_nlO0i0i0l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1l_dataout XOR niOiOO00l))))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0ilO_dataout <= niOl11iiO WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1i XOR (nlO1lOlOO XOR (nlO1lOlOi XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOlil XOR (nlO1lOl0l XOR (nlO1lOl1O XOR (nlO1lOl1l XOR (nlO1lOiOO XOR (nlO1lOiOl XOR (nlO1lOiii XOR (wire_nlO0i1l0l_dataout XOR (wire_nlO0i1l1l_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lll_dataout XOR (wire_nlO0i1O0i_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01iO_dataout XOR (niOiOO0ii XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00li_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i000l_dataout XOR (wire_nlO0i0i0i_dataout XOR (wire_nlO0i0i1O_dataout XOR niOiOO00O))))))))))))))))))))))))))))))))))))))))); + wire_nlO1O0iO_dataout <= wire_nlll0lli_q(65) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOlll; + wire_nlO1O0iOi_dataout <= niOl11iil WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (nlO1lOO0O XOR (nlO1lOO0i XOR (nlO1lOO1l XOR (nlO1lOO1i XOR (nlO1lOlOl XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOliO XOR (nlO1lOl0O XOR (nlO1lOl0i XOR (nlO1lOl1O XOR (nlO1lOl1i XOR (nlO1lOiOO XOR (nlO1lOiil XOR (nlO1O0l1i XOR (wire_nlO0i1l0i_dataout XOR (wire_nlO0i1l1i_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOl_dataout XOR (wire_nlO0i1lli_dataout XOR (wire_nlO0i1O1O_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i1OOO_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i01ll_dataout XOR (wire_nlO0i01il_dataout XOR (wire_nlO0i001l_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01Ol_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i00lO_dataout XOR (wire_nlO0i00iO_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR niOiOO0il)))))))))))))))))))))))))))))))))))))); + wire_nlO1O0iOl_dataout <= niOl11iii WHEN wire_w_lg_niOl11l1i29456w(0) = '1' ELSE (niOOi1iil XOR (nlO1lOO0l XOR (nlO1lOO1O XOR (nlO1lOO1l XOR (nlO1lOlOO XOR (nlO1lOllO XOR (nlO1lOlll XOR (nlO1lOlli XOR (nlO1lOlii XOR (nlO1lOl0l XOR (nlO1lOl0i XOR (nlO1lOl1l XOR (nlO1lOl1i XOR (nlO1lOiiO XOR (nlO1lOi0O XOR (wire_nlO0i1l1O_dataout XOR (wire_nlO0i1O1i_dataout XOR (wire_nlO0i1lOO_dataout XOR (wire_nlO0i1lOi_dataout XOR (wire_nlO0i1liO_dataout XOR (wire_nlO0i1O1l_dataout XOR (wire_nlO0i011l_dataout XOR (wire_nlO0i011i_dataout XOR (wire_nlO0i1OOl_dataout XOR (wire_nlO0i1OOi_dataout XOR (wire_nlO0i1OlO_dataout XOR (wire_nlO0i1Oll_dataout XOR (wire_nlO0i1Oli_dataout XOR (wire_nlO0i01li_dataout XOR (wire_nlO0i01ii_dataout XOR (wire_nlO0i001i_dataout XOR (wire_nlO0i01OO_dataout XOR (wire_nlO0i01Oi_dataout XOR (wire_nlO0i01lO_dataout XOR (wire_nlO0i00ll_dataout XOR (wire_nlO0i00il_dataout XOR (wire_nlO0i00ii_dataout XOR (wire_nlO0i000O_dataout XOR niOiOO0iO)))))))))))))))))))))))))))))))))))))); + wire_nlO1O0li_dataout <= wire_nlll0lli_q(66) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOllO; + wire_nlO1O0ll_dataout <= wire_nlll0lli_q(67) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOlOi; + wire_nlO1O0lO_dataout <= wire_nlll0lli_q(68) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOlOl; + wire_nlO1O0O0l_dataout <= wire_nlO1O0O0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O0O0O_dataout <= wire_nlO1O0Oii_dataout OR (wire_nl1000i_w_lg_nlO1Ol1li29671w(0) AND (wire_nl1000i_w_lg_nlO00lOiO29672w(0) AND (wire_nl1000i_w_lg_nlO00lOli29673w(0) AND (wire_nl1000i_w_lg_nlO00lOll29674w(0) AND wire_nilOO0Oi_w_lg_w_lg_w_lg_dataout29675w29678w29679w(0))))); + wire_nlO1O0Oi_dataout <= wire_nlll0lli_q(69) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOlOO; + wire_nlO1O0Oii_dataout <= nlO1Oi10i AND NOT(((niOl101li OR niOiOO0ll) AND wire_nlOl1l0Ol_dataout)); + wire_nlO1O0Ol_dataout <= wire_nlll0lli_q(70) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOO1i; + wire_nlO1O0OO_dataout <= wire_nlll0lli_q(71) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOO1l; + wire_nlO1O100i_dataout <= wire_nlO1O1l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O100l_dataout <= wire_nlO1O1lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O100O_dataout <= wire_nlO1O1lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O101i_dataout <= wire_nlO1O1l1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O101l_dataout <= wire_nlO1O1l0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O101O_dataout <= wire_nlO1O1l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O10i_dataout <= wire_nlll0lli_q(110) WHEN nlO0lliO = '1' ELSE wire_nlO01lOO_dataout; + wire_nlO1O10ii_dataout <= wire_nlO1O1liO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O10il_dataout <= wire_nlO1O1lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O10iO_dataout <= wire_nlO1O1lll_dataout WHEN niOiOO0li = '1' ELSE nlO1O0l1i; + wire_nlO1O10l_dataout <= wire_nlll0lli_q(111) WHEN nlO0lliO = '1' ELSE wire_nlO01O1i_dataout; + wire_nlO1O10li_dataout <= wire_nlO1O1llO_dataout WHEN niOiOO0li = '1' ELSE nlO1lOi0O; + wire_nlO1O10ll_dataout <= wire_nlO1O1lOi_dataout WHEN niOiOO0li = '1' ELSE nlO1lOiii; + wire_nlO1O10lO_dataout <= wire_nlO1O1lOl_dataout WHEN niOiOO0li = '1' ELSE nlO1lOiil; + wire_nlO1O10O_dataout <= wire_nlll0lli_q(112) WHEN nlO0lliO = '1' ELSE wire_nlO01O1l_dataout; + wire_nlO1O10Oi_dataout <= wire_nlO1O1lOO_dataout WHEN niOiOO0li = '1' ELSE nlO1lOiiO; + wire_nlO1O10Ol_dataout <= wire_nlO1O1O1i_dataout WHEN niOiOO0li = '1' ELSE nlO1lOili; + wire_nlO1O10OO_dataout <= wire_nlO1O1O1l_dataout WHEN niOiOO0li = '1' ELSE nlO1lOill; + wire_nlO1O110i_dataout <= wire_nlO1O1i0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O110l_dataout <= wire_nlO1O1iii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O110O_dataout <= wire_nlO1O1iil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O111i_dataout <= wire_nlO1O1i1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O111l_dataout <= wire_nlO1O1i0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O111O_dataout <= wire_nlO1O1i0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11i_dataout <= wire_nlll0lli_q(107) WHEN nlO0lliO = '1' ELSE wire_nlO01llO_dataout; + wire_nlO1O11ii_dataout <= wire_nlO1O1iiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11il_dataout <= wire_nlO1O1ili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11iO_dataout <= wire_nlO1O1ill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11l_dataout <= wire_nlll0lli_q(108) WHEN nlO0lliO = '1' ELSE wire_nlO01lOi_dataout; + wire_nlO1O11li_dataout <= wire_nlO1O1ilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11ll_dataout <= wire_nlO1O1iOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11lO_dataout <= wire_nlO1O1iOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11O_dataout <= wire_nlll0lli_q(109) WHEN nlO0lliO = '1' ELSE wire_nlO01lOl_dataout; + wire_nlO1O11Oi_dataout <= wire_nlO1O1iOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11Ol_dataout <= wire_nlO1O1l1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O11OO_dataout <= wire_nlO1O1l1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1O1i0i_dataout <= wire_nlO1O1O0O_dataout WHEN niOiOO0li = '1' ELSE nlO1lOiOO; + wire_nlO1O1i0l_dataout <= wire_nlO1O1Oii_dataout WHEN niOiOO0li = '1' ELSE nlO1lOl1i; + wire_nlO1O1i0O_dataout <= wire_nlO1O1Oil_dataout WHEN niOiOO0li = '1' ELSE nlO1lOl1l; + wire_nlO1O1i1i_dataout <= wire_nlO1O1O1O_dataout WHEN niOiOO0li = '1' ELSE nlO1lOilO; + wire_nlO1O1i1l_dataout <= wire_nlO1O1O0i_dataout WHEN niOiOO0li = '1' ELSE nlO1lOiOi; + wire_nlO1O1i1O_dataout <= wire_nlO1O1O0l_dataout WHEN niOiOO0li = '1' ELSE nlO1lOiOl; + wire_nlO1O1ii_dataout <= wire_nlll0lli_q(113) WHEN nlO0lliO = '1' ELSE wire_nlO01O1O_dataout; + wire_nlO1O1iii_dataout <= wire_nlO1O1OiO_dataout WHEN niOiOO0li = '1' ELSE nlO1lOl1O; + wire_nlO1O1iil_dataout <= wire_nlO1O1Oli_dataout WHEN niOiOO0li = '1' ELSE nlO1lOl0i; + wire_nlO1O1iiO_dataout <= wire_nlO1O1Oll_dataout WHEN niOiOO0li = '1' ELSE nlO1lOl0l; + wire_nlO1O1il_dataout <= wire_nlll0lli_q(114) WHEN nlO0lliO = '1' ELSE wire_nlO01O0i_dataout; + wire_nlO1O1ili_dataout <= wire_nlO1O1OlO_dataout WHEN niOiOO0li = '1' ELSE nlO1lOl0O; + wire_nlO1O1ill_dataout <= wire_nlO1O1OOi_dataout WHEN niOiOO0li = '1' ELSE nlO1lOlii; + wire_nlO1O1ilO_dataout <= wire_nlO1O1OOl_dataout WHEN niOiOO0li = '1' ELSE nlO1lOlil; + wire_nlO1O1iO_dataout <= wire_nlll0lli_q(115) WHEN nlO0lliO = '1' ELSE wire_nlO01O0l_dataout; + wire_nlO1O1iOi_dataout <= wire_nlO1O1OOO_dataout WHEN niOiOO0li = '1' ELSE nlO1lOliO; + wire_nlO1O1iOl_dataout <= wire_nlO1O011i_dataout WHEN niOiOO0li = '1' ELSE nlO1lOlli; + wire_nlO1O1iOO_dataout <= wire_nlO1O011l_dataout WHEN niOiOO0li = '1' ELSE nlO1lOlll; + wire_nlO1O1l0i_dataout <= wire_nlO1O010O_dataout WHEN niOiOO0li = '1' ELSE nlO1lOlOO; + wire_nlO1O1l0l_dataout <= wire_nlO1O01ii_dataout WHEN niOiOO0li = '1' ELSE nlO1lOO1i; + wire_nlO1O1l0O_dataout <= wire_nlO1O01il_dataout WHEN niOiOO0li = '1' ELSE nlO1lOO1l; + wire_nlO1O1l1i_dataout <= wire_nlO1O011O_dataout WHEN niOiOO0li = '1' ELSE nlO1lOllO; + wire_nlO1O1l1l_dataout <= wire_nlO1O010i_dataout WHEN niOiOO0li = '1' ELSE nlO1lOlOi; + wire_nlO1O1l1O_dataout <= wire_nlO1O010l_dataout WHEN niOiOO0li = '1' ELSE nlO1lOlOl; + wire_nlO1O1li_dataout <= wire_nlll0lli_q(116) WHEN nlO0lliO = '1' ELSE wire_nlO01O0O_dataout; + wire_nlO1O1lii_dataout <= wire_nlO1O01iO_dataout WHEN niOiOO0li = '1' ELSE nlO1lOO1O; + wire_nlO1O1lil_dataout <= wire_nlO1O01li_dataout WHEN niOiOO0li = '1' ELSE nlO1lOO0i; + wire_nlO1O1liO_dataout <= wire_nlO1O01ll_dataout WHEN niOiOO0li = '1' ELSE nlO1lOO0l; + wire_nlO1O1ll_dataout <= wire_nlll0lli_q(117) WHEN nlO0lliO = '1' ELSE wire_nlO01Oii_dataout; + wire_nlO1O1lli_dataout <= wire_nlO1O01lO_dataout WHEN niOiOO0li = '1' ELSE nlO1lOO0O; + wire_nlO1O1lll_dataout <= wire_nlO1O01Oi_dataout OR nlO00O11l; + wire_nlO1O1llO_dataout <= wire_nlO1O01Ol_dataout OR nlO00O11l; + wire_nlO1O1lO_dataout <= wire_nlll0lli_q(118) WHEN nlO0lliO = '1' ELSE wire_nlO01Oil_dataout; + wire_nlO1O1lOi_dataout <= wire_nlO1O01OO_dataout OR nlO00O11l; + wire_nlO1O1lOl_dataout <= wire_nlO1O001i_dataout OR nlO00O11l; + wire_nlO1O1lOO_dataout <= wire_nlO1O001l_dataout OR nlO00O11l; + wire_nlO1O1O0i_dataout <= wire_nlO1O000O_dataout OR nlO00O11l; + wire_nlO1O1O0l_dataout <= wire_nlO1O00ii_dataout OR nlO00O11l; + wire_nlO1O1O0O_dataout <= wire_nlO1O00il_dataout OR nlO00O11l; + wire_nlO1O1O1i_dataout <= wire_nlO1O001O_dataout OR nlO00O11l; + wire_nlO1O1O1l_dataout <= wire_nlO1O000i_dataout OR nlO00O11l; + wire_nlO1O1O1O_dataout <= wire_nlO1O000l_dataout OR nlO00O11l; + wire_nlO1O1Oi_dataout <= wire_nlll0lli_q(119) WHEN nlO0lliO = '1' ELSE wire_nlO01OiO_dataout; + wire_nlO1O1Oii_dataout <= wire_nlO1O00iO_dataout OR nlO00O11l; + wire_nlO1O1Oil_dataout <= wire_nlO1O00li_dataout OR nlO00O11l; + wire_nlO1O1OiO_dataout <= wire_nlO1O00ll_dataout OR nlO00O11l; + wire_nlO1O1Ol_dataout <= wire_nlll0lli_q(120) WHEN nlO0lliO = '1' ELSE wire_nlO01Oli_dataout; + wire_nlO1O1Oli_dataout <= wire_nlO1O00lO_dataout OR nlO00O11l; + wire_nlO1O1Oll_dataout <= wire_nlO1O00Oi_dataout OR nlO00O11l; + wire_nlO1O1OlO_dataout <= wire_nlO1O00Ol_dataout OR nlO00O11l; + wire_nlO1O1OO_dataout <= wire_nlll0lli_q(121) WHEN nlO0lliO = '1' ELSE wire_nlO01Oll_dataout; + wire_nlO1O1OOi_dataout <= wire_nlO1O00OO_dataout OR nlO00O11l; + wire_nlO1O1OOl_dataout <= wire_nlO1O0i1i_dataout OR nlO00O11l; + wire_nlO1O1OOO_dataout <= wire_nlO1O0i1l_dataout OR nlO00O11l; + wire_nlO1Oi0i_dataout <= wire_nlll0lli_q(75) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOO0O; + wire_nlO1Oi0l_dataout <= wire_nlll0lli_q(76) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOii; + wire_nlO1Oi0O_dataout <= wire_nlll0lli_q(77) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOil; + wire_nlO1Oi1i_dataout <= wire_nlll0lli_q(72) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOO1O; + wire_nlO1Oi1ii_dataout <= (wire_nl1000i_w_lg_nlO0il01O29664w(0) AND wire_w_lg_w_lg_niOO000ll4352w29665w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oi1il_dataout <= niOO000ll AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oi1l_dataout <= wire_nlll0lli_q(73) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOO0i; + wire_nlO1Oi1O_dataout <= wire_nlll0lli_q(74) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOO0l; + wire_nlO1Oiii_dataout <= wire_nlll0lli_q(78) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOiO; + wire_nlO1Oiil_dataout <= wire_nlll0lli_q(79) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOli; + wire_nlO1OiiO_dataout <= wire_nlll0lli_q(80) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOll; + wire_nlO1Oili_dataout <= wire_nlll0lli_q(81) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOlO; + wire_nlO1Oill_dataout <= wire_nlll0lli_q(82) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOOi; + wire_nlO1OilO_dataout <= wire_nlll0lli_q(83) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOOl; + wire_nlO1OiOi_dataout <= wire_nlll0lli_q(84) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nlllOOOO; + wire_nlO1OiOl_dataout <= wire_nlll0lli_q(85) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO111i; + wire_nlO1OiOO_dataout <= wire_nlll0lli_q(86) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO111l; + wire_nlO1Ol00i_dataout <= wire_nlO1OO00i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol00l_dataout <= wire_nlO1OO00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol00O_dataout <= wire_nlO1OO00O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol01i_dataout <= wire_nlO1OO01i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol01l_dataout <= wire_nlO1OO01l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol01O_dataout <= wire_nlO1OO01O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0i_dataout <= wire_nlll0lli_q(90) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO110O; + wire_nlO1Ol0ii_dataout <= wire_nlO1OO0ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0il_dataout <= wire_nlO1OO0il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0iO_dataout <= wire_nlO1OO0iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0l_dataout <= wire_nlll0lli_q(91) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11ii; + wire_nlO1Ol0li_dataout <= wire_nlO1OO0li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0ll_dataout <= wire_nlO1OO0ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0lO_dataout <= wire_nlO1OO0lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0O_dataout <= wire_nlll0lli_q(92) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11il; + wire_nlO1Ol0Oi_dataout <= wire_nlO1OO0Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0Ol_dataout <= wire_nlO1OO0Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol0OO_dataout <= wire_nlO1OO0OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol1i_dataout <= wire_nlll0lli_q(87) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO111O; + wire_nlO1Ol1l_dataout <= wire_nlll0lli_q(88) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO110i; + wire_nlO1Ol1ll_dataout <= wire_nlO1OO1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol1lO_dataout <= wire_nlO0111ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol1O_dataout <= wire_nlll0lli_q(89) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO110l; + wire_nlO1Ol1Oi_dataout <= wire_nlO0111lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol1Ol_dataout <= wire_nlO1OO1Ol_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ol1OO_dataout <= wire_nlO1OO1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oli0i_dataout <= wire_nlO1OOi0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oli0l_dataout <= wire_nlO1OOi0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oli0O_dataout <= wire_nlO1OOi0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oli1i_dataout <= wire_nlO1OOi1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oli1l_dataout <= wire_nlO1OOi1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oli1O_dataout <= wire_nlO1OOi1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Olii_dataout <= wire_nlll0lli_q(93) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11iO; + wire_nlO1Oliii_dataout <= wire_nlO1OOiii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oliil_dataout <= wire_nlO1OOiil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OliiO_dataout <= wire_nlO1OOiiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Olil_dataout <= wire_nlll0lli_q(94) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11li; + wire_nlO1Olili_dataout <= wire_nlO1OOili_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Olill_dataout <= wire_nlO1OOill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlilO_dataout <= wire_nlO1OOilO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OliO_dataout <= wire_nlll0lli_q(95) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11ll; + wire_nlO1OliOi_dataout <= wire_nlO1OOiOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OliOl_dataout <= wire_nlO1OOiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OliOO_dataout <= wire_nlO1OOiOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oll0i_dataout <= wire_nlO1OOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oll0l_dataout <= wire_nlO1OOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oll0O_dataout <= wire_nlO1OOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oll1i_dataout <= wire_nlO1OOl1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oll1l_dataout <= wire_nlO1OOl1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Oll1O_dataout <= wire_nlO1OOl1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Olli_dataout <= wire_nlll0lli_q(96) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11lO; + wire_nlO1Ollii_dataout <= wire_nlO1OOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ollil_dataout <= wire_nlO1OOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlliO_dataout <= wire_nlO1OOliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Olll_dataout <= wire_nlll0lli_q(97) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11Oi; + wire_nlO1Ollli_dataout <= wire_nlO1OOlli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1Ollll_dataout <= wire_nlO1OOlll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlllO_dataout <= wire_nlO1OOllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OllO_dataout <= wire_nlll0lli_q(98) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11Ol; + wire_nlO1OllOi_dataout <= wire_nlO1OOlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OllOl_dataout <= wire_nlO1OOlOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OllOO_dataout <= wire_nlO1OOlOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlO0i_dataout <= wire_nlO1OOO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlO0l_dataout <= wire_nlO1OOO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlO0O_dataout <= wire_nlO1OOO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlO1i_dataout <= wire_nlO1OOO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlO1l_dataout <= wire_nlO1OOO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlO1O_dataout <= wire_nlO1OOO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOi_dataout <= wire_nlll0lli_q(99) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO11OO; + wire_nlO1OlOii_dataout <= wire_nlO1OOOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOil_dataout <= wire_nlO1OOOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOiO_dataout <= wire_nlO1OOOiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOl_dataout <= wire_nlll0lli_q(100) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO101i; + wire_nlO1OlOli_dataout <= wire_nlO1OOOli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOll_dataout <= wire_nlO1OOOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOlO_dataout <= wire_nlO1OOOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOO_dataout <= wire_nlll0lli_q(101) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO101l; + wire_nlO1OlOOi_dataout <= wire_nlO1OOOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOOl_dataout <= wire_nlO1OOOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OlOOO_dataout <= wire_nlO1OOOOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO00i_dataout <= nlO1Oi01O AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlO1OO00l_dataout <= nlO1Oi00i AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlO1OO00O_dataout <= wire_nlO0110ii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi00l; + wire_nlO1OO01i_dataout <= wire_nlO01100i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi1OO; + wire_nlO1OO01l_dataout <= wire_nlO01100l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi01i; + wire_nlO1OO01O_dataout <= wire_nlO01100O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi01l; + wire_nlO1OO0i_dataout <= wire_nlll0lli_q(105) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO100O; + wire_nlO1OO0ii_dataout <= wire_nlO011iOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi00O; + wire_nlO1OO0il_dataout <= wire_nlO011iOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0ii; + wire_nlO1OO0iO_dataout <= wire_nlO011iOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0il; + wire_nlO1OO0l_dataout <= wire_nlll0lli_q(106) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10ii; + wire_nlO1OO0li_dataout <= wire_nlO011l1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0iO; + wire_nlO1OO0ll_dataout <= wire_nlO011l1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0li; + wire_nlO1OO0lO_dataout <= wire_nlO011l1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0ll; + wire_nlO1OO0O_dataout <= wire_nlll0lli_q(107) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10il; + wire_nlO1OO0Oi_dataout <= wire_nlO011l0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0lO; + wire_nlO1OO0Ol_dataout <= wire_nlO011l0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0Oi; + wire_nlO1OO0OO_dataout <= wire_nlO011l0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0Ol; + wire_nlO1OO10i_dataout <= wire_nlO01110i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO10l_dataout <= wire_nlO01110l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO10O_dataout <= wire_nlO01110O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO11i_dataout <= wire_nlO01111i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO11l_dataout <= wire_nlO01111l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO11O_dataout <= wire_nlO01111O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO1i_dataout <= wire_nlll0lli_q(102) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO101O; + wire_nlO1OO1ii_dataout <= wire_nlO0111ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO1il_dataout <= wire_nlO0111il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO1iO_dataout <= wire_nlO0111iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO1l_dataout <= wire_nlll0lli_q(103) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO100i; + wire_nlO1OO1li_dataout <= wire_nlO0111li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlO1OO1ll_dataout <= wire_nlO1OO1lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi10O; + wire_nlO1OO1lO_dataout <= wire_nlO1OO1Oi_dataout OR niOiOO0lO; + wire_nlO1OO1O_dataout <= wire_nlll0lli_q(104) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO100l; + wire_nlO1OO1Oi_dataout <= nlO1Oi10O AND NOT(nlO1Oi1ll); + wire_nlO1OO1Ol_dataout <= wire_nlO01101l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi1Oi; + wire_nlO1OO1OO_dataout <= wire_nlO01101O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi1Ol; + wire_nlO1OOi0i_dataout <= wire_nlO011lli_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oii1O; + wire_nlO1OOi0l_dataout <= wire_nlO011lll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oii0i; + wire_nlO1OOi0O_dataout <= wire_nlO011llO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oii0l; + wire_nlO1OOi1i_dataout <= wire_nlO011lii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oi0OO; + wire_nlO1OOi1l_dataout <= wire_nlO011lil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oii1i; + wire_nlO1OOi1O_dataout <= wire_nlO011liO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oii1l; + wire_nlO1OOii_dataout <= wire_nlll0lli_q(108) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10iO; + wire_nlO1OOiii_dataout <= wire_nlO011lOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oii0O; + wire_nlO1OOiil_dataout <= wire_nlO011lOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oiiii; + wire_nlO1OOiiO_dataout <= wire_nlO011lOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oiiil; + wire_nlO1OOil_dataout <= wire_nlll0lli_q(109) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10li; + wire_nlO1OOili_dataout <= wire_nlO011O1i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiiiO; + wire_nlO1OOill_dataout <= wire_nlO011O1l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oiili; + wire_nlO1OOilO_dataout <= wire_nlO011O1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oiill; + wire_nlO1OOiO_dataout <= wire_nlll0lli_q(110) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10ll; + wire_nlO1OOiOi_dataout <= wire_nlO011O0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiilO; + wire_nlO1OOiOl_dataout <= wire_nlO011O0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiiOi; + wire_nlO1OOiOO_dataout <= wire_nlO011O0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiiOl; + wire_nlO1OOl0i_dataout <= wire_nlO011Oli_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oil1O; + wire_nlO1OOl0l_dataout <= wire_nlO011Oll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oil0i; + wire_nlO1OOl0O_dataout <= wire_nlO011OlO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oil0l; + wire_nlO1OOl1i_dataout <= wire_nlO011Oii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiiOO; + wire_nlO1OOl1l_dataout <= wire_nlO011Oil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oil1i; + wire_nlO1OOl1O_dataout <= wire_nlO011OiO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oil1l; + wire_nlO1OOli_dataout <= wire_nlll0lli_q(111) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10lO; + wire_nlO1OOlii_dataout <= wire_nlO011OOi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oil0O; + wire_nlO1OOlil_dataout <= wire_nlO011OOl_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oilii; + wire_nlO1OOliO_dataout <= wire_nlO011OOO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oilil; + wire_nlO1OOll_dataout <= wire_nlll0lli_q(112) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10Oi; + wire_nlO1OOlli_dataout <= wire_nlO01011i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiliO; + wire_nlO1OOlll_dataout <= wire_nlO01011l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oilli; + wire_nlO1OOllO_dataout <= wire_nlO01011O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1Oilll; + wire_nlO1OOlO_dataout <= wire_nlll0lli_q(113) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10Ol; + wire_nlO1OOlOi_dataout <= wire_nlO01010i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OillO; + wire_nlO1OOlOl_dataout <= wire_nlO01010l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OilOi; + wire_nlO1OOlOO_dataout <= wire_nlO01010O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OilOl; + wire_nlO1OOO0i_dataout <= wire_nlO0101li_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiO1O; + wire_nlO1OOO0l_dataout <= wire_nlO0101ll_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiO0i; + wire_nlO1OOO0O_dataout <= wire_nlO0101lO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiO0l; + wire_nlO1OOO1i_dataout <= wire_nlO0101ii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OilOO; + wire_nlO1OOO1l_dataout <= wire_nlO0101il_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiO1i; + wire_nlO1OOO1O_dataout <= wire_nlO0101iO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiO1l; + wire_nlO1OOOi_dataout <= wire_nlll0lli_q(114) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO10OO; + wire_nlO1OOOii_dataout <= wire_nlO0101Oi_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiO0O; + wire_nlO1OOOil_dataout <= wire_nlO0101Ol_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOii; + wire_nlO1OOOiO_dataout <= wire_nlO0101OO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOil; + wire_nlO1OOOl_dataout <= wire_nlll0lli_q(115) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1i1i; + wire_nlO1OOOli_dataout <= wire_nlO01001i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOiO; + wire_nlO1OOOll_dataout <= wire_nlO01001l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOli; + wire_nlO1OOOlO_dataout <= wire_nlO01001O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOll; + wire_nlO1OOOO_dataout <= wire_nlll0lli_q(116) WHEN wire_nl1000i_w_lg_nlO0lliO4409w(0) = '1' ELSE nllO1i1l; + wire_nlO1OOOOi_dataout <= wire_nlO01000i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOlO; + wire_nlO1OOOOl_dataout <= wire_nlO01000l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOOi; + wire_nlO1OOOOO_dataout <= wire_nlO01000O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO1OiOOl; + wire_nlOi0000l_dataout <= nlOi000iO WHEN k_gbl_hip(23) = '1' ELSE n11O010O; + wire_nlOi0001O_dataout <= nlOi001ll WHEN niOl101OO = '1' ELSE n11O01ii; + wire_nlOi000ii_dataout <= (nlOi00i1i XOR nlOi000Ol) AND NOT(wire_niO01O0O_dataout); + wire_nlOi000ll_dataout <= nlOi000Ol AND NOT(wire_niO01lOO_dataout); + wire_nlOi000Oi_dataout <= nlOi0000O AND NOT(wire_niO01lOO_dataout); + wire_nlOi000OO_dataout <= nlOi00i1l AND NOT(wire_niO01O0O_dataout); + wire_nlOi0010i_dataout <= nlOi01OlO AND NOT(wire_niO01lOO_dataout); + wire_nlOi0010O_dataout <= nlOi001il AND NOT(wire_niO01O0O_dataout); + wire_nlOi0011l_dataout <= nlOi0010l AND NOT(wire_niO01lOO_dataout); + wire_nlOi001iO_dataout <= nlOi001ii AND NOT(wire_niO01O0O_dataout); + wire_nlOi001li_dataout <= nlOi0011O AND NOT(wire_niO01O0O_dataout); + wire_nlOi001lO_dataout <= wire_nlOi001Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi001Oi_dataout <= wire_nlOi0001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi001Ol_dataout <= wire_niO01ill_w_lg_nlOi001il28841w(0) WHEN ((wire_w_lg_niOl101OO28842w(0) AND (nlOi001ll XOR n11O01ii)) AND n11O01ii) = '1' ELSE nlOi001il; + wire_nlOi00i0i_dataout <= nlOi000lO AND NOT(wire_niO01O0O_dataout); + wire_nlOi00i0O_dataout <= wire_nlOi00iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi00i1O_dataout <= nlOi00i1i AND NOT(wire_niO01O0O_dataout); + wire_nlOi00iii_dataout <= wire_nlOi00ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi00iil_dataout <= wire_niO01ill_w_lg_nlOi00i1l28834w(0) WHEN ((wire_w_lg_niOl1001i28835w(0) AND (nlOi00i0l XOR n11O010O)) AND n11O010O) = '1' ELSE nlOi00i1l; + wire_nlOi00ilO_dataout <= nlOi00i0l WHEN niOl1001i = '1' ELSE n11O010O; + wire_nlOi00iOl_dataout <= nlOi00iOO WHEN k_gbl_hip(23) = '1' ELSE nlilOiOOl; + wire_nlOi00l1O_dataout <= nlOi00l0i WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO11O_dataout; + wire_nlOi00l1O_w_lg_w_lg_dataout21012w21013w(0) <= wire_nlOi00l1O_w_lg_dataout21012w(0) AND niOl0i0Ol; + wire_nlOi00l1O_w_lg_dataout21012w(0) <= wire_nlOi00l1O_dataout AND n1110O0l; + wire_nlOi00lii_dataout <= nlOi00lil WHEN k_gbl_hip(23) = '1' ELSE n11O1O0l; + wire_nlOi00lll_dataout <= nlOi00llO WHEN k_gbl_hip(23) = '1' ELSE n11O1O0O; + wire_nlOi00O0i_dataout <= n11li1li WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi00O0l; + wire_nlOi00O0i_w_lg_dataout9865w(0) <= NOT wire_nlOi00O0i_dataout; + wire_nlOi00O1O_dataout <= n11li1iO WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi00OlO; + wire_nlOi00O1O_w_lg_dataout9870w(0) <= NOT wire_nlOi00O1O_dataout; + wire_nlOi00Oii_dataout <= wire_nlOi00OiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi00Oil_dataout <= wire_nlOi00Oli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi00OiO_dataout <= nlOi0i1il WHEN niOl1001l = '1' ELSE nlOi00OlO; + wire_nlOi00Oli_dataout <= nlOi0i1iO WHEN niOl1001l = '1' ELSE nlOi00O0l; + wire_nlOi00OOl_dataout <= nlOi0i11l AND NOT(wire_niO01lOO_dataout); + wire_nlOi0100i_dataout <= wire_nlOi0100O_dataout AND NOT(wire_nlOi01i1i_dataout); + wire_nlOi0100l_dataout <= wire_nlOi01i1l_dataout AND NOT(wire_nlOi01i1i_dataout); + wire_nlOi0100O_dataout <= wire_nlOi010Oi_dataout AND NOT(wire_nlOi01i1l_dataout); + wire_nlOi0101i_dataout <= wire_nlOi0100i_dataout AND NOT(wire_nlOi010Ol_dataout); + wire_nlOi0101l_dataout <= wire_nlOi01i1i_dataout AND NOT(wire_nlOi010Ol_dataout); + wire_nlOi0101O_dataout <= wire_nlOi0100l_dataout AND NOT(wire_nlOi010Ol_dataout); + wire_nlOi010li_dataout <= wire_nlillO1iO_dataout WHEN niOl101ll = '1' ELSE wire_nlOi01i1O_dataout; + wire_nlOi010li_w_lg_dataout29711w(0) <= NOT wire_nlOi010li_dataout; + wire_nlOi010ll_dataout <= wire_nlOi01i0i_dataout AND NOT(niOl101ll); + wire_nlOi010ll_w_lg_dataout29709w(0) <= NOT wire_nlOi010ll_dataout; + wire_nlOi010lO_dataout <= wire_nlOi01i0l_dataout AND NOT(niOl101ll); + wire_nlOi010lO_w_lg_dataout29707w(0) <= NOT wire_nlOi010lO_dataout; + wire_nlOi010Oi_dataout <= wire_nlOi01i0O_dataout AND NOT(niOl101ll); + wire_nlOi010Oi_w_lg_dataout29705w(0) <= NOT wire_nlOi010Oi_dataout; + wire_nlOi010Ol_dataout <= wire_nlOi01iii_dataout AND NOT(niOl101ll); + wire_nlOi010Ol_w_lg_dataout29703w(0) <= NOT wire_nlOi010Ol_dataout; + wire_nlOi010OO_dataout <= wire_nlOi01iil_dataout AND NOT(niOl101ll); + wire_nlOi010OO_w_lg_dataout29701w(0) <= NOT wire_nlOi010OO_dataout; + wire_nlOi0110i_dataout <= wire_nlOi011iO_dataout AND NOT(wire_nlOi010ll_dataout); + wire_nlOi0110l_dataout <= wire_nlOi011li_dataout AND NOT(wire_nlOi010ll_dataout); + wire_nlOi0110O_dataout <= wire_nlOi011ll_dataout AND NOT(wire_nlOi010ll_dataout); + wire_nlOi0111i_dataout <= wire_nlOi010lO_dataout AND NOT(wire_nlOi010ll_dataout); + wire_nlOi0111l_dataout <= wire_nlOi011ii_dataout AND NOT(wire_nlOi010ll_dataout); + wire_nlOi0111O_dataout <= wire_nlOi011il_dataout AND NOT(wire_nlOi010ll_dataout); + wire_nlOi011ii_dataout <= wire_nlOi011lO_dataout AND NOT(wire_nlOi010lO_dataout); + wire_nlOi011il_dataout <= wire_nlOi011Oi_dataout AND NOT(wire_nlOi010lO_dataout); + wire_nlOi011iO_dataout <= wire_nlOi010OO_dataout AND NOT(wire_nlOi010lO_dataout); + wire_nlOi011li_dataout <= wire_nlOi011Ol_dataout AND NOT(wire_nlOi010lO_dataout); + wire_nlOi011ll_dataout <= wire_nlOi011OO_dataout AND NOT(wire_nlOi010lO_dataout); + wire_nlOi011lO_dataout <= wire_nlOi0101i_dataout AND NOT(wire_nlOi010OO_dataout); + wire_nlOi011Oi_dataout <= wire_nlOi010Ol_dataout AND NOT(wire_nlOi010OO_dataout); + wire_nlOi011Ol_dataout <= wire_nlOi0101l_dataout AND NOT(wire_nlOi010OO_dataout); + wire_nlOi011OO_dataout <= wire_nlOi0101O_dataout AND NOT(wire_nlOi010OO_dataout); + wire_nlOi01i0i_dataout <= (nll0liiOl AND wire_nlOi1Oi0i_w_lg_dataout28866w(0)) AND niOl101li; + wire_nlOi01i0l_dataout <= (wire_nilOO11l_dataout AND wire_nlOi1Oi0l_w_lg_dataout28864w(0)) AND niOl101li; + wire_nlOi01i0O_dataout <= wire_nilOO0Oi_dataout WHEN niOl101li = '1' ELSE wire_nlOi01ill_dataout; + wire_nlOi01i1i_dataout <= wire_nlOi01iiO_dataout AND NOT(niOl101ll); + wire_nlOi01i1i_w_lg_dataout29699w(0) <= NOT wire_nlOi01i1i_dataout; + wire_nlOi01i1l_dataout <= wire_nlOi01ili_dataout AND NOT(niOl101ll); + wire_nlOi01i1l_w_lg_dataout29698w(0) <= NOT wire_nlOi01i1l_dataout; + wire_nlOi01i1O_dataout <= wire_nlillO1iO_dataout AND niOl101li; + wire_nlOi01iii_dataout <= niOl101lO AND niOl101li; + wire_nlOi01iil_dataout <= niOl101iO AND niOl101li; + wire_nlOi01iiO_dataout <= (wire_nilOO11i_dataout AND wire_nlOi1Oiii_w_lg_dataout28862w(0)) AND niOl101li; + wire_nlOi01ili_dataout <= (nll0liiOi AND wire_nlOi1Oiil_w_lg_dataout28860w(0)) WHEN niOl101li = '1' ELSE wire_nlOi01ilO_dataout; + wire_nlOi01ill_dataout <= wire_nilOO0Oi_dataout WHEN wire_nilOOi1O_dataout = '1' ELSE wire_nlOi01iOi_dataout; + wire_nlOi01ilO_dataout <= nll0liiOi AND wire_nilOOi1O_dataout; + wire_nlOi01iOi_dataout <= wire_nilOO0Oi_dataout AND NOT(wire_nlOi0lO0i_dataout); + wire_nlOi01lii_dataout <= wire_nlOi01lli_dataout AND NOT(nlO00O11l); + wire_nlOi01lil_dataout <= wire_nlOi01lll_dataout AND NOT(nlO00O11l); + wire_nlOi01liO_dataout <= wire_nlOi01llO_dataout AND NOT(nlO00O11l); + wire_nlOi01lli_dataout <= wire_nlOi01lOi_dataout OR nlO00O11i; + wire_nlOi01lll_dataout <= wire_nlOi01lOl_dataout AND NOT(nlO00O11i); + wire_nlOi01llO_dataout <= wire_nlOi01lOO_dataout AND NOT(nlO00O11i); + wire_nlOi01lOi_dataout <= wire_nlOi01O1i_dataout AND NOT(nlO00lOOO); + wire_nlOi01lOl_dataout <= wire_nlOi01O1l_dataout OR nlO00lOOO; + wire_nlOi01lOO_dataout <= wire_nl1000i_w_lg_nlO00lOOl28855w(0) AND NOT(nlO00lOOO); + wire_nlOi01O0i_dataout <= k_gbl_hip(32) AND wire_nlO0O000O_w_lg_dataout28852w(0); + wire_nlOi01O0i_w_lg_dataout29166w(0) <= NOT wire_nlOi01O0i_dataout; + wire_nlOi01O0O_dataout <= nlliiiliO AND (niOl101Oi OR nlliiilii); + wire_nlOi01O1i_dataout <= wire_nl1000i_w_lg_nlO00lOOi28854w(0) OR nlO00lOOl; + wire_nlOi01O1l_dataout <= wire_nlOi01O1O_dataout OR nlO00lOOl; + wire_nlOi01O1O_dataout <= wire_nl1000i_w_lg_nlO00lOlO28853w(0) AND NOT(nlO00lOOi); + wire_nlOi01Oil_dataout <= nlliiiliO AND (niOO10O0l OR niOl101Oi); + wire_nlOi01Oll_dataout <= nlOi01OOO WHEN k_gbl_hip(23) = '1' ELSE n11O01ii; + wire_nlOi01OOi_dataout <= (nlOi001ii XOR nlOi0010l) AND NOT(wire_niO01O0O_dataout); + wire_nlOi0i01i_dataout <= n11li1li WHEN wire_w_lg_niOl1001O28823w(0) = '1' ELSE nlOi0i1iO; + wire_nlOi0i01O_dataout <= nlOi0i00i WHEN k_gbl_hip(23) = '1' ELSE n11i110i; + wire_nlOi0i01O_w_lg_dataout46530w(0) <= NOT wire_nlOi0i01O_dataout; + wire_nlOi0i10O_dataout <= nlOi0i10i AND NOT(wire_niO01O0O_dataout); + wire_nlOi0i11i_dataout <= nlOi00O0O AND NOT(wire_niO01lOO_dataout); + wire_nlOi0i11O_dataout <= nlOi0i10l AND NOT(wire_niO01O0O_dataout); + wire_nlOi0i1ii_dataout <= nlOi00OOO AND NOT(wire_niO01O0O_dataout); + wire_nlOi0i1li_dataout <= wire_nlOi0i1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0i1ll_dataout <= wire_nlOi0i1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0i1lO_dataout <= wire_nlOi0i01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0i1Oi_dataout <= wire_niO01ill_w_lg_nlOi0i10l28824w(0) WHEN (wire_w_lg_niOl1001O28823w(0) AND (NOT ((NOT (nlOi0i1il XOR n11li1iO)) AND (NOT (nlOi0i1iO XOR n11li1li))))) = '1' ELSE nlOi0i10l; + wire_nlOi0i1OO_dataout <= n11li1iO WHEN wire_w_lg_niOl1001O28823w(0) = '1' ELSE nlOi0i1il; + wire_nlOi0ii0O_dataout <= wire_niO111iO_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0l1li; + wire_nlOi0ii0O_w_lg_dataout9020w(0) <= NOT wire_nlOi0ii0O_dataout; + wire_nlOi0iiii_dataout <= wire_niO111li_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0il1O; + wire_nlOi0iiil_dataout <= wire_niO111ll_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0il0i; + wire_nlOi0iiil_w_lg_dataout9017w(0) <= NOT wire_nlOi0iiil_dataout; + wire_nlOi0iiiO_dataout <= wire_niO111lO_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0il0l; + wire_nlOi0iiiO_w_lg_w_lg_w_lg_w_lg_dataout9016w9018w9019w9021w(0) <= wire_nlOi0iiiO_w_lg_w_lg_w_lg_dataout9016w9018w9019w(0) AND wire_nlOi0ii0O_w_lg_dataout9020w(0); + wire_nlOi0iiiO_w_lg_w_lg_w_lg_dataout9016w9018w9019w(0) <= wire_nlOi0iiiO_w_lg_w_lg_dataout9016w9018w(0) AND wire_nlOi0iiii_dataout; + wire_nlOi0iiiO_w_lg_w_lg_dataout9016w9018w(0) <= wire_nlOi0iiiO_w_lg_dataout9016w(0) AND wire_nlOi0iiil_w_lg_dataout9017w(0); + wire_nlOi0iiiO_w_lg_dataout9016w(0) <= NOT wire_nlOi0iiiO_dataout; + wire_nlOi0iili_dataout <= wire_niO111Oi_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0il0O; + wire_nlOi0iili_w_lg_w_lg_w_lg_dataout20928w20937w20938w(0) <= wire_nlOi0iili_w_lg_w_lg_dataout20928w20937w(0) AND niOl0Oiii; + wire_nlOi0iili_w_lg_w_lg_w_lg_dataout20928w20939w20940w(0) <= wire_nlOi0iili_w_lg_w_lg_dataout20928w20939w(0) AND wire_w_lg_niOl0Oiii20898w(0); + wire_nlOi0iili_w_lg_w_lg_dataout20928w20937w(0) <= wire_nlOi0iili_w_lg_dataout20928w(0) AND wire_w_lg_niOl0l1OO20936w(0); + wire_nlOi0iili_w_lg_w_lg_dataout20928w20939w(0) <= wire_nlOi0iili_w_lg_dataout20928w(0) AND niOl0iOOl; + wire_nlOi0iili_w_lg_dataout20928w(0) <= NOT wire_nlOi0iili_dataout; + wire_nlOi0iili_w20941w(0) <= wire_nlOi0iili_w_lg_w_lg_w_lg_dataout20928w20937w20938w(0) OR wire_nlOi0iili_w_lg_w_lg_w_lg_dataout20928w20939w20940w(0); + wire_nlOi0iili_w_lg_w20941w20942w(0) <= wire_nlOi0iili_w20941w(0) OR niOl0l1ii; + wire_nlOi0iili_w_lg_w_lg_w20941w20942w20943w(0) <= wire_nlOi0iili_w_lg_w20941w20942w(0) OR niOl0l1il; + wire_nlOi0iill_dataout <= wire_niO111OO_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0ilii; + wire_nlOi0iilO_dataout <= wire_niO1101i_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0ilil; + wire_nlOi0iiOi_dataout <= wire_niO1101l_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0iliO; + wire_nlOi0iiOl_dataout <= wire_niO1101O_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0illi; + wire_nlOi0iiOO_dataout <= wire_niO1100i_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0illl; + wire_nlOi0il1i_dataout <= wire_niO1100l_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0illO; + wire_nlOi0il1l_dataout <= wire_niO1100O_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOi0ilOi; + wire_nlOi0ilOO_dataout <= wire_nlOi0iOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iO0i_dataout <= wire_nlOi0l11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iO0l_dataout <= wire_nlOi0l11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iO0O_dataout <= wire_nlOi0l11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iO1i_dataout <= wire_nlOi0iOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iO1l_dataout <= wire_nlOi0iOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iO1O_dataout <= wire_nlOi0iOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iOii_dataout <= wire_nlOi0l10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iOil_dataout <= wire_nlOi0l10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iOiO_dataout <= wire_nlOi0l10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iOli_dataout <= wire_nlOi0l1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iOll_dataout <= wire_nlOi0l1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0iOlO_dataout <= nlOi0l00O WHEN niOl1000i = '1' ELSE nlOi0l1li; + wire_nlOi0iOOi_dataout <= nlOi0l0ii WHEN niOl1000i = '1' ELSE nlOi0il1O; + wire_nlOi0iOOl_dataout <= nlOi0l0il WHEN niOl1000i = '1' ELSE nlOi0il0i; + wire_nlOi0iOOO_dataout <= nlOi0l0iO WHEN niOl1000i = '1' ELSE nlOi0il0l; + wire_nlOi0l00i_dataout <= nlOi0l01l AND NOT(wire_niO01lOO_dataout); + wire_nlOi0l00l_dataout <= nlOi0l1Oi AND NOT(wire_niO01lOO_dataout); + wire_nlOi0l01i_dataout <= nlOi0l01O AND NOT(wire_niO01lOO_dataout); + wire_nlOi0l10i_dataout <= nlOi0l0Ol WHEN niOl1000i = '1' ELSE nlOi0iliO; + wire_nlOi0l10l_dataout <= nlOi0l0OO WHEN niOl1000i = '1' ELSE nlOi0illi; + wire_nlOi0l10O_dataout <= nlOi0li1i WHEN niOl1000i = '1' ELSE nlOi0illl; + wire_nlOi0l11i_dataout <= nlOi0l0li WHEN niOl1000i = '1' ELSE nlOi0il0O; + wire_nlOi0l11l_dataout <= nlOi0l0lO WHEN niOl1000i = '1' ELSE nlOi0ilii; + wire_nlOi0l11O_dataout <= nlOi0l0Oi WHEN niOl1000i = '1' ELSE nlOi0ilil; + wire_nlOi0l1ii_dataout <= nlOi0li1l WHEN niOl1000i = '1' ELSE nlOi0illO; + wire_nlOi0l1il_dataout <= nlOi0li1O WHEN niOl1000i = '1' ELSE nlOi0ilOi; + wire_nlOi0l1lO_dataout <= nlOi0l1OO AND NOT(wire_niO01O0O_dataout); + wire_nlOi0l1Ol_dataout <= nlOi0ilOl AND NOT(wire_niO01O0O_dataout); + wire_nlOi0li0i_dataout <= wire_nlOi0ll1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0li0l_dataout <= wire_nlOi0ll0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0li0O_dataout <= wire_nlOi0ll0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0liii_dataout <= wire_nlOi0llii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0liil_dataout <= wire_nlOi0llil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0liiO_dataout <= wire_nlOi0lliO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0lili_dataout <= wire_nlOi0llli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0lill_dataout <= wire_nlOi0llll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0lilO_dataout <= wire_nlOi0lllO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0liOi_dataout <= wire_nlOi0llOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0liOl_dataout <= wire_nlOi0llOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0liOO_dataout <= wire_nlOi0llOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0ll0l_dataout <= wire_niO111iO_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l00O; + wire_nlOi0ll0O_dataout <= wire_niO111li_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0ii; + wire_nlOi0ll1i_dataout <= wire_nlOi0lO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0ll1l_dataout <= wire_nlOi0lO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0ll1O_dataout <= wire_nl1000i_w_lg_nlOi0l01O28780w(0) WHEN (wire_w_lg_niOl1000O28779w(0) AND wire_w_lg_niOl1000l28781w(0)) = '1' ELSE nlOi0l01O; + wire_nlOi0llii_dataout <= wire_niO111ll_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0il; + wire_nlOi0llil_dataout <= wire_niO111lO_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0iO; + wire_nlOi0lliO_dataout <= wire_niO111Oi_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0li; + wire_nlOi0llli_dataout <= wire_niO111Ol_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0ll; + wire_nlOi0llll_dataout <= wire_niO111OO_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0lO; + wire_nlOi0lllO_dataout <= wire_niO1101i_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0Oi; + wire_nlOi0llOi_dataout <= wire_niO1101l_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0Ol; + wire_nlOi0llOl_dataout <= wire_niO1101O_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0l0OO; + wire_nlOi0llOO_dataout <= wire_niO1100i_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0li1i; + wire_nlOi0lO0i_dataout <= nlOi0lO0l WHEN k_gbl_hip(23) = '1' ELSE n1110O0l; + wire_nlOi0lO0i_w_lg_dataout28858w(0) <= NOT wire_nlOi0lO0i_dataout; + wire_nlOi0lO1i_dataout <= wire_niO1100l_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0li1l; + wire_nlOi0lO1l_dataout <= wire_niO1100O_dataout WHEN wire_w_lg_niOl1000O28779w(0) = '1' ELSE nlOi0li1O; + wire_nlOi0lOil_dataout <= nlOi0lOOi WHEN k_gbl_hip(23) = '1' ELSE niOOOOiO; + wire_nlOi0lOli_dataout <= wire_nlOi0lOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0lOll_dataout <= wire_niO01ill_w_lg_nlOi0lOOi28776w(0) WHEN (nlOi0O10l XOR nlOi0O11O) = '1' ELSE nlOi0lOOi; + wire_nlOi0lOOO_dataout <= nlOi0O11O AND NOT(wire_niO01O0O_dataout); + wire_nlOi0O00i_dataout <= wire_nlOi0O00l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0O00l_dataout <= wire_nl1000i_w_lg_nlOi0O0ii28769w(0) WHEN (nlOi0O0Ol XOR nlOi0O0lO) = '1' ELSE nlOi0O0ii; + wire_nlOi0O01l_dataout <= nlOi0O0ii WHEN k_gbl_hip(23) = '1' ELSE n11O1lii; + wire_nlOi0O0iO_dataout <= nlOi0O0lO AND NOT(wire_niO01lOO_dataout); + wire_nlOi0O0ll_dataout <= nlOi0O01O AND NOT(wire_niO01lOO_dataout); + wire_nlOi0O0Oi_dataout <= nlOi0O0OO AND NOT(wire_niO01O0O_dataout); + wire_nlOi0O10i_dataout <= nlOi0O10O AND NOT(wire_niO01lOO_dataout); + wire_nlOi0O11l_dataout <= nlOi0lOiO AND NOT(wire_niO01O0O_dataout); + wire_nlOi0O1ii_dataout <= nlOi0O10l AND NOT(wire_niO01lOO_dataout); + wire_nlOi0O1il_dataout <= nlOi0O11i AND NOT(wire_niO01lOO_dataout); + wire_nlOi0O1li_dataout <= wire_nlOi0O1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0O1ll_dataout <= wire_nlOi0O1OO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0O1lO_dataout <= wire_nl1000i_w_lg_nlOi0O10O28772w(0) WHEN (wire_w_lg_niOl100ii28773w(0) AND (nlOi0O1iO XOR niOOOOiO)) = '1' ELSE nlOi0O10O; + wire_nlOi0O1OO_dataout <= nlOi0O1iO WHEN niOl100ii = '1' ELSE niOOOOiO; + wire_nlOi0Oi0i_dataout <= wire_nlOi0Oi0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0Oi0l_dataout <= wire_nlOi0OiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0Oi0O_dataout <= wire_niO01ill_w_lg_nlOi0O0OO28765w(0) WHEN (wire_w_lg_niOl100il28766w(0) AND (nlOi0Oi1O XOR n11O1lii)) = '1' ELSE nlOi0O0OO; + wire_nlOi0Oi1i_dataout <= nlOi0O0Ol AND NOT(wire_niO01O0O_dataout); + wire_nlOi0Oi1l_dataout <= nlOi0O0li AND NOT(wire_niO01O0O_dataout); + wire_nlOi0OiiO_dataout <= nlOi0Oi1O WHEN niOl100il = '1' ELSE n11O1lii; + wire_nlOi0Oill_dataout <= nlOi0Ol1i WHEN k_gbl_hip(23) = '1' ELSE n11O1l0O; + wire_nlOi0OiOi_dataout <= wire_nlOi0OiOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi0OiOl_dataout <= wire_nl1000i_w_lg_nlOi0Ol1i28762w(0) WHEN (nlOi0Olil XOR nlOi0Ol0O) = '1' ELSE nlOi0Ol1i; + wire_nlOi0Ol0l_dataout <= nlOi0OilO AND NOT(wire_niO01lOO_dataout); + wire_nlOi0Ol1O_dataout <= nlOi0Ol0O AND NOT(wire_niO01lOO_dataout); + wire_nlOi0Olii_dataout <= nlOi0OliO AND NOT(wire_niO01O0O_dataout); + wire_nlOi0Olli_dataout <= nlOi0Olil AND NOT(wire_niO01O0O_dataout); + wire_nlOi0Olll_dataout <= nlOi0Ol0i AND NOT(wire_niO01O0O_dataout); + wire_nlOi0OlOi_dataout <= wire_nlOi0OlOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0OlOl_dataout <= wire_nlOi0OO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0OlOO_dataout <= wire_niO01ill_w_lg_nlOi0OliO28758w(0) WHEN (wire_w_lg_niOl100iO28759w(0) AND (nlOi0OllO XOR n11O1l0O)) = '1' ELSE nlOi0OliO; + wire_nlOi0OO0l_dataout <= nlOi0OOli WHEN k_gbl_hip(23) = '1' ELSE nl11i0Oi; + wire_nlOi0OO0l_w_lg_dataout20783w(0) <= NOT wire_nlOi0OO0l_dataout; + wire_nlOi0OO1O_dataout <= nlOi0OllO WHEN niOl100iO = '1' ELSE n11O1l0O; + wire_nlOi0OOii_dataout <= wire_nlOi0OOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOi0OOil_dataout <= wire_niO01ill_w_lg_nlOi0OOli28755w(0) WHEN (nlOii111l XOR nlOi0OOOO) = '1' ELSE nlOi0OOli; + wire_nlOi0OOlO_dataout <= nlOi0OOOO AND NOT(wire_niO01O0O_dataout); + wire_nlOi0OOOl_dataout <= nlOi0OO0O AND NOT(wire_niO01O0O_dataout); + wire_nlOi1110i_dataout <= nlO0OlllO AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlOi1110l_dataout <= nlO0OllOi AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlOi1110O_dataout <= wire_nlOi1li0O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OllOl; + wire_nlOi1111i_dataout <= wire_nlOi1li1O_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OlliO; + wire_nlOi1111l_dataout <= wire_nlOi1li0i_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ollli; + wire_nlOi1111O_dataout <= wire_nlOi1li0l_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0Ollll; + wire_nlOi111ii_dataout <= wire_nlOi1liii_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OllOO; + wire_nlOi111il_dataout <= wire_nlOi1liil_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OlO1i; + wire_nlOi111iO_dataout <= nlO0OlO1l AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlOi111li_dataout <= wire_nlOi1liiO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OlO1O; + wire_nlOi111ll_dataout <= wire_nlOi1lili_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OlO0i; + wire_nlOi111lO_dataout <= wire_nlOi1lill_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OlO0l; + wire_nlOi111Oi_dataout <= wire_nlOi1lilO_dataout WHEN wire_nlOl1l0Ol_dataout = '1' ELSE nlO0OlO0O; + wire_nlOi1l00i_dataout <= nll0liOiO WHEN niOl11OOi = '1' ELSE wire_nlOi1ll1i_dataout; + wire_nlOi1l00l_dataout <= nll0liOli WHEN niOl11OOi = '1' ELSE wire_nlOi1ll1l_dataout; + wire_nlOi1l00l_w_lg_dataout29032w(0) <= wire_nlOi1l00l_dataout XOR wire_nlOi1l01i_w_lg_dataout29031w(0); + wire_nlOi1l00O_dataout <= nll0liOll WHEN niOl11OOi = '1' ELSE wire_nlOi1ll1O_dataout; + wire_nlOi1l01i_dataout <= nll0liiOO WHEN niOl11OOi = '1' ELSE wire_nlOi1liOi_dataout; + wire_nlOi1l01i_w_lg_dataout29031w(0) <= wire_nlOi1l01i_dataout XOR wire_nlOi1l0lO_w_lg_dataout29030w(0); + wire_nlOi1l01l_dataout <= nll0liOii WHEN niOl11OOi = '1' ELSE wire_nlOi1liOl_dataout; + wire_nlOi1l01O_dataout <= nll0liOil WHEN niOl11OOi = '1' ELSE wire_nlOi1liOO_dataout; + wire_nlOi1l0ii_dataout <= nll0liOlO WHEN niOl11OOi = '1' ELSE wire_nlOi1ll0i_dataout; + wire_nlOi1l0il_dataout <= nll0liOOi WHEN niOl11OOi = '1' ELSE wire_nlOi1ll0l_dataout; + wire_nlOi1l0iO_dataout <= nll0liOOl WHEN niOl11OOi = '1' ELSE wire_nlOi1ll0O_dataout; + wire_nlOi1l0li_dataout <= nll0liOOO WHEN niOl11OOi = '1' ELSE wire_nlOi1llii_dataout; + wire_nlOi1l0li_w_lg_dataout29029w(0) <= wire_nlOi1l0li_dataout XOR wire_nlOi1li0i_w_lg_dataout29028w(0); + wire_nlOi1l0ll_dataout <= nll0ll11i WHEN niOl11OOi = '1' ELSE wire_nlOi1llil_dataout; + wire_nlOi1l0lO_dataout <= nll0ll11l WHEN niOl11OOi = '1' ELSE wire_nlOi1lliO_dataout; + wire_nlOi1l0lO_w_lg_dataout29030w(0) <= wire_nlOi1l0lO_dataout XOR wire_nlOi1l0li_w_lg_dataout29029w(0); + wire_nlOi1l0Oi_dataout <= wire_nlOi1llli_dataout AND NOT(niOl11OOi); + wire_nlOi1l0Ol_dataout <= wire_nlOi1llll_dataout AND NOT(niOl11OOi); + wire_nlOi1l0OO_dataout <= wire_nlOi1lllO_dataout AND NOT(niOl11OOi); + wire_nlOi1li0i_dataout <= wire_nlOi1lO1i_dataout AND NOT(niOl11OOi); + wire_nlOi1li0i_w_lg_dataout29028w(0) <= wire_nlOi1li0i_dataout XOR wire_nlOi1li1O_w_lg_dataout29027w(0); + wire_nlOi1li0l_dataout <= wire_nlOi1lO1l_dataout AND NOT(niOl11OOi); + wire_nlOi1li0O_dataout <= wire_nlOi1lO1O_dataout AND NOT(niOl11OOi); + wire_nlOi1li1i_dataout <= wire_nlOi1llOi_dataout AND NOT(niOl11OOi); + wire_nlOi1li1i_w_lg_dataout29026w(0) <= wire_nlOi1li1i_dataout XOR wire_nlOi1lill_w_lg_dataout29025w(0); + wire_nlOi1li1l_dataout <= wire_nlOi1llOl_dataout AND NOT(niOl11OOi); + wire_nlOi1li1O_dataout <= wire_nlOi1llOO_dataout AND NOT(niOl11OOi); + wire_nlOi1li1O_w_lg_dataout29027w(0) <= wire_nlOi1li1O_dataout XOR wire_nlOi1li1i_w_lg_dataout29026w(0); + wire_nlOi1liii_dataout <= wire_nlOi1lO0i_dataout AND NOT(niOl11OOi); + wire_nlOi1liil_dataout <= wire_nlOi1lO0l_dataout AND NOT(niOl11OOi); + wire_nlOi1liiO_dataout <= nll0lilil WHEN niOl11OOi = '1' ELSE wire_nlOi1lO0O_dataout; + wire_nlOi1lili_dataout <= wire_nlOi1lOii_dataout AND NOT(niOl11OOi); + wire_nlOi1lill_dataout <= wire_nlOi1lOil_dataout AND NOT(niOl11OOi); + wire_nlOi1lill_w_lg_dataout29025w(0) <= wire_nlOi1lill_dataout XOR niOl11O0O; + wire_nlOi1lilO_dataout <= wire_nlOi1lOiO_dataout AND NOT(niOl11OOi); + wire_nlOi1liOi_dataout <= wire_nlOi1lOli_dataout AND NOT(nlOi1OiOl); + wire_nlOi1liOl_dataout <= wire_nlOi1lOll_dataout AND NOT(nlOi1OiOl); + wire_nlOi1liOO_dataout <= wire_nlOi1lOlO_dataout AND NOT(nlOi1OiOl); + wire_nlOi1ll0i_dataout <= wire_nlOi1O11i_dataout AND NOT(nlOi1OiOl); + wire_nlOi1ll0l_dataout <= wire_nlOi1O11l_dataout AND NOT(nlOi1OiOl); + wire_nlOi1ll0O_dataout <= wire_nlOi1O11O_dataout AND NOT(nlOi1OiOl); + wire_nlOi1ll1i_dataout <= wire_nlOi1lOOi_dataout AND NOT(nlOi1OiOl); + wire_nlOi1ll1l_dataout <= wire_nlOi1lOOl_dataout AND NOT(nlOi1OiOl); + wire_nlOi1ll1O_dataout <= wire_nlOi1lOOO_dataout AND NOT(nlOi1OiOl); + wire_nlOi1llii_dataout <= wire_nlOi1O10i_dataout AND NOT(nlOi1OiOl); + wire_nlOi1llil_dataout <= wire_nlOi1O10l_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lliO_dataout <= wire_nlOi1O10O_dataout AND NOT(nlOi1OiOl); + wire_nlOi1llli_dataout <= wire_nlOi1O1ii_dataout AND NOT(nlOi1OiOl); + wire_nlOi1llll_dataout <= wire_nlOi1O1il_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lllO_dataout <= wire_nlOi1O1iO_dataout AND NOT(nlOi1OiOl); + wire_nlOi1llOi_dataout <= wire_nlOi1O1li_dataout AND NOT(nlOi1OiOl); + wire_nlOi1llOl_dataout <= wire_nlOi1O1ll_dataout AND NOT(nlOi1OiOl); + wire_nlOi1llOO_dataout <= wire_nlOi1O1lO_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lO0i_dataout <= wire_nilOO0li_dataout WHEN nlOi1OiOl = '1' ELSE wire_nlOi1O01i_dataout; + wire_nlOi1lO0l_dataout <= wire_nilOO0ll_dataout WHEN nlOi1OiOl = '1' ELSE wire_nlOi1O01l_dataout; + wire_nlOi1lO0O_dataout <= wire_nlOi1O01O_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lO1i_dataout <= wire_nlOi1O1Oi_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lO1l_dataout <= wire_nlOi1O1Ol_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lO1O_dataout <= wire_nilOO0iO_dataout WHEN nlOi1OiOl = '1' ELSE wire_nlOi1O1OO_dataout; + wire_nlOi1lOii_dataout <= wire_nlOi1O00i_dataout OR nlOi1OiOl; + wire_nlOi1lOil_dataout <= wire_nlOi1O00l_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lOiO_dataout <= wire_nlOi1O00O_dataout AND NOT(nlOi1OiOl); + wire_nlOi1lOli_dataout <= nlillO1Oi WHEN nlOi1Oill = '1' ELSE wire_nilOll0O_dataout; + wire_nlOi1lOll_dataout <= nlillO1Ol WHEN nlOi1Oill = '1' ELSE wire_nilOllii_dataout; + wire_nlOi1lOlO_dataout <= nlillO1OO WHEN nlOi1Oill = '1' ELSE wire_nilOllil_dataout; + wire_nlOi1lOOi_dataout <= nlillO01i WHEN nlOi1Oill = '1' ELSE wire_nilOlliO_dataout; + wire_nlOi1lOOl_dataout <= nlillO01l WHEN nlOi1Oill = '1' ELSE wire_nilOllli_dataout; + wire_nlOi1lOOO_dataout <= nlillO01O WHEN nlOi1Oill = '1' ELSE wire_nilOllll_dataout; + wire_nlOi1O00i_dataout <= nlillOi0O WHEN nlOi1Oill = '1' ELSE wire_nilOlOOO_dataout; + wire_nlOi1O00l_dataout <= nlillOiii AND nlOi1Oill; + wire_nlOi1O00O_dataout <= nlillOiil OR NOT(nlOi1Oill); + wire_nlOi1O01i_dataout <= nlillOl1l WHEN nlOi1Oill = '1' ELSE wire_nilOlOlO_dataout; + wire_nlOi1O01l_dataout <= nlillOl1O WHEN nlOi1Oill = '1' ELSE wire_nilOlOOi_dataout; + wire_nlOi1O01O_dataout <= nlillOi0l WHEN nlOi1Oill = '1' ELSE wire_nilOlOOl_dataout; + wire_nlOi1O10i_dataout <= nlillO0ii WHEN nlOi1Oill = '1' ELSE wire_nilOllOO_dataout; + wire_nlOi1O10l_dataout <= nlillO0il WHEN nlOi1Oill = '1' ELSE wire_nilOlO1i_dataout; + wire_nlOi1O10O_dataout <= nlillO0iO WHEN nlOi1Oill = '1' ELSE wire_nilOlO1l_dataout; + wire_nlOi1O11i_dataout <= nlillO00i WHEN nlOi1Oill = '1' ELSE wire_nilOlllO_dataout; + wire_nlOi1O11l_dataout <= nlillO00l WHEN nlOi1Oill = '1' ELSE wire_nilOllOi_dataout; + wire_nlOi1O11O_dataout <= nlillO00O WHEN nlOi1Oill = '1' ELSE wire_nilOllOl_dataout; + wire_nlOi1O1ii_dataout <= nlillO0li WHEN nlOi1Oill = '1' ELSE wire_nilOlO1O_dataout; + wire_nlOi1O1il_dataout <= nlillO0ll WHEN nlOi1Oill = '1' ELSE wire_nilOlO0i_dataout; + wire_nlOi1O1iO_dataout <= nlillO0lO WHEN nlOi1Oill = '1' ELSE wire_nilOlO0l_dataout; + wire_nlOi1O1li_dataout <= nlillO0Oi WHEN nlOi1Oill = '1' ELSE wire_nilOlO0O_dataout; + wire_nlOi1O1ll_dataout <= nlillO0Ol WHEN nlOi1Oill = '1' ELSE wire_nilOlOii_dataout; + wire_nlOi1O1lO_dataout <= nlillO0OO WHEN nlOi1Oill = '1' ELSE wire_nilOlOil_dataout; + wire_nlOi1O1Oi_dataout <= nlillOi1i WHEN nlOi1Oill = '1' ELSE wire_nilOlOiO_dataout; + wire_nlOi1O1Ol_dataout <= nlillOi1l WHEN nlOi1Oill = '1' ELSE wire_nilOlOli_dataout; + wire_nlOi1O1OO_dataout <= nlillOl1i WHEN nlOi1Oill = '1' ELSE wire_nilOlOll_dataout; + wire_nlOi1Oi0i_dataout <= nlOi1OilO AND wire_nlOl1l0Ol_dataout; + wire_nlOi1Oi0i_w_lg_dataout28866w(0) <= NOT wire_nlOi1Oi0i_dataout; + wire_nlOi1Oi0l_dataout <= nlOi1OiOi AND wire_nlOl1l0Ol_dataout; + wire_nlOi1Oi0l_w_lg_dataout28864w(0) <= NOT wire_nlOi1Oi0l_dataout; + wire_nlOi1Oi0O_dataout <= nlOi1OiOl AND wire_nlOl1l0Ol_dataout; + wire_nlOi1Oi1O_dataout <= nlOi1Oill AND wire_nlOl1l0Ol_dataout; + wire_nlOi1Oiii_dataout <= nlOi1Ol1l AND wire_nlOl1l0Ol_dataout; + wire_nlOi1Oiii_w_lg_dataout28862w(0) <= NOT wire_nlOi1Oiii_dataout; + wire_nlOi1Oiil_dataout <= nlOi1Ol1O AND wire_nlOl1l0Ol_dataout; + wire_nlOi1Oiil_w_lg_dataout28860w(0) <= NOT wire_nlOi1Oiil_dataout; + wire_nlOi1Ol0i_dataout <= wire_nlOi1OlOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1Ol0l_dataout <= wire_nlOi1OO1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1Ol0O_dataout <= wire_nlOi1OO1l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1Olii_dataout <= wire_nlOi1OO1O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1Olil_dataout <= wire_nlOi1OO0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1OliO_dataout <= wire_nlOi1OO0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1Olli_dataout <= wire_nlOi1OO0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1Olll_dataout <= wire_nlOi1OOii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1OllO_dataout <= wire_nlOi1OOil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOi1OlOi_dataout <= wire_nlOi1OlOl_dataout OR (niOl1010i AND wire_w_lg_niOl1011O28876w(0)); + wire_nlOi1OlOl_dataout <= nlO0OlOii AND NOT(wire_nlOl1l0Ol_dataout); + wire_nlOi1OO0i_dataout <= wire_nlOi1OOll_dataout WHEN niOl1010i = '1' ELSE nlOi1OiOl; + wire_nlOi1OO0l_dataout <= wire_nlOi1OOlO_dataout WHEN niOl1010i = '1' ELSE nlOi1OiOO; + wire_nlOi1OO0O_dataout <= wire_nlOi1OOOi_dataout WHEN niOl1010i = '1' ELSE nlOi1Ol1i; + wire_nlOi1OO1i_dataout <= wire_nlOi010li_dataout WHEN niOl1010i = '1' ELSE nlOi1Oill; + wire_nlOi1OO1l_dataout <= wire_nlOi1OOiO_dataout WHEN niOl1010i = '1' ELSE nlOi1OilO; + wire_nlOi1OO1O_dataout <= wire_nlOi1OOli_dataout WHEN niOl1010i = '1' ELSE nlOi1OiOi; + wire_nlOi1OOii_dataout <= wire_nlOi1OOOl_dataout WHEN niOl1010i = '1' ELSE nlOi1Ol1l; + wire_nlOi1OOil_dataout <= wire_nlOi1OOOO_dataout WHEN niOl1010i = '1' ELSE nlOi1Ol1O; + wire_nlOi1OOiO_dataout <= wire_nlOi010ll_dataout AND NOT(wire_nlOi010li_dataout); + wire_nlOi1OOli_dataout <= wire_nlOi0111i_dataout AND NOT(wire_nlOi010li_dataout); + wire_nlOi1OOll_dataout <= wire_nlOi0111l_dataout AND NOT(wire_nlOi010li_dataout); + wire_nlOi1OOlO_dataout <= wire_nlOi0111O_dataout AND NOT(wire_nlOi010li_dataout); + wire_nlOi1OOOi_dataout <= wire_nlOi0110i_dataout AND NOT(wire_nlOi010li_dataout); + wire_nlOi1OOOl_dataout <= wire_nlOi0110l_dataout AND NOT(wire_nlOi010li_dataout); + wire_nlOi1OOOO_dataout <= wire_nlOi0110O_dataout AND NOT(wire_nlOi010li_dataout); + wire_nlOii000i_dataout <= wire_nlOii000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii000l_dataout <= wire_nlOii00li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii000O_dataout <= wire_niO01ill_w_lg_nlOii01OO28730w(0) WHEN ((wire_w_lg_niOl100Oi28731w(0) AND (nlOii001O XOR niOl0OiiO)) AND niOl0OiiO) = '1' ELSE nlOii01OO; + wire_nlOii001i_dataout <= nlOii01Ol AND NOT(wire_niO01O0O_dataout); + wire_nlOii001l_dataout <= nlOii01li AND NOT(wire_niO01O0O_dataout); + wire_nlOii00li_dataout <= nlOii001O WHEN niOl100Oi = '1' ELSE niOl0OiiO; + wire_nlOii00lO_dataout <= nlOii0i1i WHEN k_gbl_hip(23) = '1' ELSE niOl0OiiO; + wire_nlOii00Ol_dataout <= (nlOii0iil XOR nlOii0i0O) AND NOT(wire_niO01O0O_dataout); + wire_nlOii010l_dataout <= (nlOii01Ol XOR nlOii01lO) AND NOT(wire_niO01O0O_dataout); + wire_nlOii011i_dataout <= nlOii1OiO WHEN niOl100lO = '1' ELSE nlOO01OOO; + wire_nlOii011O_dataout <= nlOii01ii WHEN k_gbl_hip(23) = '1' ELSE niOl0OiiO; + wire_nlOii01iO_dataout <= nlOii01lO AND NOT(wire_niO01lOO_dataout); + wire_nlOii01ll_dataout <= nlOii010i AND NOT(wire_niO01lOO_dataout); + wire_nlOii01Oi_dataout <= nlOii01OO AND NOT(wire_niO01O0O_dataout); + wire_nlOii0i0l_dataout <= nlOii00Oi AND NOT(wire_niO01lOO_dataout); + wire_nlOii0i1O_dataout <= nlOii0i0O AND NOT(wire_niO01lOO_dataout); + wire_nlOii0iii_dataout <= nlOii0iiO AND NOT(wire_niO01O0O_dataout); + wire_nlOii0ili_dataout <= nlOii0iil AND NOT(wire_niO01O0O_dataout); + wire_nlOii0ill_dataout <= nlOii0i0i AND NOT(wire_niO01O0O_dataout); + wire_nlOii0iOi_dataout <= wire_nlOii0iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii0iOl_dataout <= wire_nlOii0l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii0iOO_dataout <= wire_niO01ill_w_lg_nlOii0iiO28723w(0) WHEN ((wire_w_lg_niOl100Ol28724w(0) AND (nlOii0ilO XOR niOl0OiiO)) AND niOl0OiiO) = '1' ELSE nlOii0iiO; + wire_nlOii0l0i_dataout <= nlOii0ilO WHEN niOl100Ol = '1' ELSE niOl0OiiO; + wire_nlOii0l0O_dataout <= nlOii0lii WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO10i_dataout; + wire_nlOii0l0O_w_lg_w_lg_dataout21190w24751w(0) <= wire_nlOii0l0O_w_lg_dataout21190w(0) AND n1110Oil; + wire_nlOii0l0O_w_lg_dataout21190w(0) <= NOT wire_nlOii0l0O_dataout; + wire_nlOii0l0O_w_lg_dataout23875w(0) <= wire_nlOii0l0O_dataout OR wire_w_lg_niOl0Ol0l23874w(0); + wire_nlOii0lli_dataout <= nlOii0lll WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO10l_dataout; + wire_nlOii0lli_w_lg_dataout25161w(0) <= NOT wire_nlOii0lli_dataout; + wire_nlOii0lOl_dataout <= nlOii0lOO WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO10O_dataout; + wire_nlOii0lOl_w_lg_dataout24922w(0) <= NOT wire_nlOii0lOl_dataout; + wire_nlOii0lOl_w_lg_dataout23877w(0) <= wire_nlOii0lOl_dataout OR wire_w_lg_niOli1OiO23876w(0); + wire_nlOii0O1O_dataout <= nlOii0O0i WHEN k_gbl_hip(23) = '1' ELSE nli1il11i; + wire_nlOii0O1O_w_lg_dataout9833w(0) <= NOT wire_nlOii0O1O_dataout; + wire_nlOii0Oii_dataout <= nlOii0Oil WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO01i_dataout; + wire_nlOii0Oii_w26816w(0) <= wire_nlOii0Oii_w_lg_w_lg_w_lg_w26809w26811w26813w26815w(0) AND wire_nlOlOi10O_dataout; + wire_nlOii0Oii_w_lg_w_lg_w_lg_w26809w26811w26813w26815w(0) <= wire_nlOii0Oii_w_lg_w_lg_w26809w26811w26813w(0) AND wire_nlOlOi1ii_w_lg_dataout26814w(0); + wire_nlOii0Oii_w_lg_w_lg_w26809w26811w26813w(0) <= wire_nlOii0Oii_w_lg_w26809w26811w(0) AND wire_nlOlOi1il_w_lg_dataout26812w(0); + wire_nlOii0Oii_w_lg_w26809w26811w(0) <= wire_nlOii0Oii_w26809w(0) AND wire_nlOlOi1iO_w_lg_dataout26810w(0); + wire_nlOii0Oii_w26809w(0) <= wire_nlOii0Oii_w_lg_w_lg_w_lg_dataout21042w26805w26807w(0) AND wire_nlOlOi1li_w_lg_dataout26808w(0); + wire_nlOii0Oii_w_lg_w_lg_w_lg_dataout21042w26805w26807w(0) <= wire_nlOii0Oii_w_lg_w_lg_dataout21042w26805w(0) AND wire_nlOlOi1ll_w_lg_dataout26806w(0); + wire_nlOii0Oii_w_lg_w_lg_dataout21042w26805w(0) <= wire_nlOii0Oii_w_lg_dataout21042w(0) AND wire_nlOlOi1lO_w_lg_dataout26804w(0); + wire_nlOii0Oii_w_lg_w_lg_w_lg_dataout21042w21043w21044w(0) <= wire_nlOii0Oii_w_lg_w_lg_dataout21042w21043w(0) AND niOl0i0ii; + wire_nlOii0Oii_w_lg_dataout21042w(0) <= NOT wire_nlOii0Oii_dataout; + wire_nlOii0Oii_w_lg_w_lg_dataout21042w21043w(0) <= wire_nlOii0Oii_w_lg_dataout21042w(0) OR niOli101i; + wire_nlOii0Oll_dataout <= nlOii0OlO WHEN k_gbl_hip(23) = '1' ELSE n1110OlO; + wire_nlOii0Oll_w_lg_dataout42177w(0) <= NOT wire_nlOii0Oll_dataout; + wire_nlOii0OOO_dataout <= nlOiii11i WHEN k_gbl_hip(23) = '1' ELSE n1110Oll; + wire_nlOii0OOO_w_lg_dataout34636w(0) <= NOT wire_nlOii0OOO_dataout; + wire_nlOii101O_dataout <= nlOii100i WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO1Oi_dataout; + wire_nlOii101O_w_lg_w_lg_dataout20780w20781w(0) <= wire_nlOii101O_w_lg_dataout20780w(0) AND nlOllll0O; + wire_nlOii101O_w_lg_dataout20779w(0) <= wire_nlOii101O_dataout AND wire_w_lg_niOli1l1i20778w(0); + wire_nlOii101O_w_lg_dataout20780w(0) <= wire_nlOii101O_dataout AND niOli1l1i; + wire_nlOii10ii_dataout <= nlOii10il WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO1Ol_dataout; + wire_nlOii10ii_w_lg_w_lg_dataout23869w23871w(0) <= wire_nlOii10ii_w_lg_dataout23869w(0) AND wire_w_lg_w_lg_niOlO1O0i20967w23870w(0); + wire_nlOii10ii_w_lg_dataout23869w(0) <= NOT wire_nlOii10ii_dataout; + wire_nlOii10ii_w_lg_dataout23472w(0) <= wire_nlOii10ii_dataout OR niOl0Ol0i; + wire_nlOii10ll_dataout <= nlOii10lO WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO1OO_dataout; + wire_nlOii10OO_dataout <= nlOii1i0i WHEN k_gbl_hip(23) = '1' ELSE niOl1iiOl; + wire_nlOii110i_dataout <= nlOii111l AND NOT(wire_niO01lOO_dataout); + wire_nlOii110l_dataout <= nlOi0OOOi AND NOT(wire_niO01lOO_dataout); + wire_nlOii111i_dataout <= nlOii111O AND NOT(wire_niO01lOO_dataout); + wire_nlOii11ii_dataout <= wire_nlOii11iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOii11il_dataout <= wire_nlOii11lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOii11iO_dataout <= wire_nl1000i_w_lg_nlOii111O28751w(0) WHEN (wire_w_lg_niOl100li28752w(0) AND (nlOii110O XOR nl11i0Oi)) = '1' ELSE nlOii111O; + wire_nlOii11lO_dataout <= nlOii110O WHEN niOl100li = '1' ELSE nl11i0Oi; + wire_nlOii11Ol_dataout <= nlOii11OO WHEN k_gbl_hip(23) = '1' ELSE wire_nilOO1lO_dataout; + wire_nlOii1i0O_dataout <= nlOii1iiO AND NOT(wire_niO01lOO_dataout); + wire_nlOii1i1l_dataout <= (nlOii1ill XOR nlOii1iiO) AND NOT(wire_niO01O0O_dataout); + wire_nlOii1iil_dataout <= nlOii1i1i AND NOT(wire_niO01lOO_dataout); + wire_nlOii1ili_dataout <= nlOii1ilO AND NOT(wire_niO01O0O_dataout); + wire_nlOii1iOi_dataout <= nlOii1ill AND NOT(wire_niO01O0O_dataout); + wire_nlOii1iOl_dataout <= nlOii1iii AND NOT(wire_niO01O0O_dataout); + wire_nlOii1l1i_dataout <= wire_nlOii1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii1l1l_dataout <= wire_nlOii1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii1l1O_dataout <= wire_niO01ill_w_lg_nlOii1ilO28744w(0) WHEN ((wire_w_lg_niOl100ll28745w(0) AND (nlOii1iOO XOR niOl1iiOl)) AND niOl1iiOl) = '1' ELSE nlOii1ilO; + wire_nlOii1lii_dataout <= nlOii1iOO WHEN niOl100ll = '1' ELSE niOl1iiOl; + wire_nlOii1liO_dataout <= nlOii1lOi WHEN k_gbl_hip(23) = '1' ELSE nlOO01OOO; + wire_nlOii1lll_dataout <= (nlOii1O0l XOR nlOii1O1O) AND NOT(wire_niO01O0O_dataout); + wire_nlOii1lOO_dataout <= nlOii1O1O AND NOT(wire_niO01lOO_dataout); + wire_nlOii1O0i_dataout <= nlOii1O0O AND NOT(wire_niO01O0O_dataout); + wire_nlOii1O1l_dataout <= nlOii1lli AND NOT(wire_niO01lOO_dataout); + wire_nlOii1Oii_dataout <= nlOii1O0l AND NOT(wire_niO01O0O_dataout); + wire_nlOii1Oil_dataout <= nlOii1O1i AND NOT(wire_niO01O0O_dataout); + wire_nlOii1Oli_dataout <= wire_nlOii1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii1Oll_dataout <= wire_nlOii011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOii1OlO_dataout <= wire_niO01ill_w_lg_nlOii1O0O28737w(0) WHEN ((wire_w_lg_niOl100lO28738w(0) AND (nlOii1OiO XOR nlOO01OOO)) AND nlOO01OOO) = '1' ELSE nlOii1O0O; + wire_nlOiii00l_dataout <= nlOiii1Oi AND NOT(wire_niO01lOO_dataout); + wire_nlOiii01O_dataout <= nlOiii00O AND NOT(wire_niO01lOO_dataout); + wire_nlOiii0ii_dataout <= nlOiii0iO AND NOT(wire_niO01O0O_dataout); + wire_nlOiii0li_dataout <= nlOiii0il AND NOT(wire_niO01O0O_dataout); + wire_nlOiii0ll_dataout <= nlOiii00i AND NOT(wire_niO01O0O_dataout); + wire_nlOiii0Oi_dataout <= wire_nlOiii0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiii0Ol_dataout <= wire_nlOiiii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiii0OO_dataout <= wire_niO01ill_w_lg_nlOiii0iO28716w(0) WHEN ((wire_w_lg_niOl100OO28717w(0) AND (nlOiii0lO XOR nlOllllil)) AND nlOllllil) = '1' ELSE nlOiii0iO; + wire_nlOiii10i_dataout <= nlOiii10l WHEN k_gbl_hip(23) = '1' ELSE n1110OOl; + wire_nlOiii10i_w_lg_dataout42170w(0) <= NOT wire_nlOiii10i_dataout; + wire_nlOiii1il_dataout <= nlOiii1iO WHEN k_gbl_hip(23) = '1' ELSE n1110OOi; + wire_nlOiii1lO_dataout <= nlOiii01i WHEN k_gbl_hip(23) = '1' ELSE nlOllllil; + wire_nlOiii1Ol_dataout <= (nlOiii0il XOR nlOiii00O) AND NOT(wire_niO01O0O_dataout); + wire_nlOiiii0i_dataout <= nlOiii0lO WHEN niOl100OO = '1' ELSE nlOllllil; + wire_nlOiiii0O_dataout <= nlOiiiiiO AND k_gbl_hip(23); + wire_nlOiiiiii_dataout <= (nlOiiiiOi XOR nlOiiiill) AND NOT(wire_niO01O0O_dataout); + wire_nlOiiiilO_dataout <= nlOiiiiOl AND NOT(wire_niO01O0O_dataout); + wire_nlOiiiiOO_dataout <= nlOiiiiOi AND NOT(wire_niO01O0O_dataout); + wire_nlOiiil1i_dataout <= nlOiiiili AND NOT(wire_niO01O0O_dataout); + wire_nlOiiil1l_dataout <= nlOiiiiOl AND NOT(wire_niO01lOO_dataout); + wire_nlOiiillO_dataout <= nlOlO0lOO WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiil1OO; + wire_nlOiiilOi_dataout <= nlOlOi1Oi WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiiO0l; + wire_nlOiiilOl_dataout <= nlOlOi1Ol WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiiO0O; + wire_nlOiiilOO_dataout <= nlOlOi1OO WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiiOii; + wire_nlOiiiO0i_dataout <= nlOlOi00i WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiiOll; + wire_nlOiiiO1i_dataout <= nlOlOi01i WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiiOil; + wire_nlOiiiO1l_dataout <= nlOlOi01l WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiiOiO; + wire_nlOiiiO1O_dataout <= nlOlOi01O WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiiOli; + wire_nlOiiiOOi_dataout <= wire_nlOiil10O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiiiOOl_dataout <= wire_nlOiil1ii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiiiOOO_dataout <= wire_nlOiil1il_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiil00i_dataout <= nlOiiiOlO AND NOT(wire_niO01lOO_dataout); + wire_nlOiil00O_dataout <= nlOiil0il AND NOT(wire_niO01O0O_dataout); + wire_nlOiil01l_dataout <= nlOiil00l AND NOT(wire_niO01lOO_dataout); + wire_nlOiil0iO_dataout <= nlOiil0ii AND NOT(wire_niO01O0O_dataout); + wire_nlOiil0li_dataout <= nlOiil01O AND NOT(wire_niO01O0O_dataout); + wire_nlOiil10i_dataout <= wire_nlOiil1lO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiil10l_dataout <= wire_nlOiil1Oi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiil10O_dataout <= nlOiil0ll WHEN niOl10i1i = '1' ELSE nlOiil1OO; + wire_nlOiil11i_dataout <= wire_nlOiil1iO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiil11l_dataout <= wire_nlOiil1li_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiil11O_dataout <= wire_nlOiil1ll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiil1ii_dataout <= nlOiil0lO WHEN niOl10i1i = '1' ELSE nlOiiiO0l; + wire_nlOiil1il_dataout <= nlOiil0Oi WHEN niOl10i1i = '1' ELSE nlOiiiO0O; + wire_nlOiil1iO_dataout <= nlOiil0Ol WHEN niOl10i1i = '1' ELSE nlOiiiOii; + wire_nlOiil1li_dataout <= nlOiil0OO WHEN niOl10i1i = '1' ELSE nlOiiiOil; + wire_nlOiil1ll_dataout <= nlOiili1i WHEN niOl10i1i = '1' ELSE nlOiiiOiO; + wire_nlOiil1lO_dataout <= nlOiili1l WHEN niOl10i1i = '1' ELSE nlOiiiOli; + wire_nlOiil1Oi_dataout <= nlOiili1O WHEN niOl10i1i = '1' ELSE nlOiiiOll; + wire_nlOiili0i_dataout <= wire_nlOiiliOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiili0l_dataout <= wire_nlOiiliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiili0O_dataout <= wire_nlOiill1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiliii_dataout <= wire_nlOiill1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiliil_dataout <= wire_nlOiill1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiliiO_dataout <= wire_nlOiill0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiilili_dataout <= wire_nlOiill0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiilill_dataout <= wire_nlOiill0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiililO_dataout <= wire_nlOiillii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiliOi_dataout <= wire_niO01ill_w_lg_nlOiil0il28687w(0) WHEN (wire_w_lg_niOl10i1O28686w(0) AND wire_w_lg_niOl10i1l28688w(0)) = '1' ELSE nlOiil0il; + wire_nlOiiliOO_dataout <= nlOlO0lOO WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiil0ll; + wire_nlOiill0i_dataout <= nlOlOi01i WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiil0OO; + wire_nlOiill0l_dataout <= nlOlOi01l WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiili1i; + wire_nlOiill0O_dataout <= nlOlOi01O WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiili1l; + wire_nlOiill1i_dataout <= nlOlOi1Oi WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiil0lO; + wire_nlOiill1l_dataout <= nlOlOi1Ol WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiil0Oi; + wire_nlOiill1O_dataout <= nlOlOi1OO WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiil0Ol; + wire_nlOiillii_dataout <= nlOlOi00i WHEN wire_w_lg_niOl10i1O28686w(0) = '1' ELSE nlOiili1O; + wire_nlOiillOl_dataout <= niil00Ol WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiO11i; + wire_nlOiillOl_w_lg_dataout9855w(0) <= NOT wire_nlOiillOl_dataout; + wire_nlOiillOO_dataout <= niil010i WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiilO1O; + wire_nlOiillOO_w_lg_dataout9853w(0) <= NOT wire_nlOiillOO_dataout; + wire_nlOiilO1i_dataout <= niil010l WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiilO0i; + wire_nlOiilO1i_w_lg_dataout9851w(0) <= NOT wire_nlOiilO1i_dataout; + wire_nlOiilO1l_dataout <= niil010O WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiilO0l; + wire_nlOiilO1l_w_lg_w_lg_w_lg_w_lg_dataout9857w9858w9868w9869w(0) <= wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9868w(0) AND wire_nlOiillOl_dataout; + wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9868w(0) <= wire_nlOiilO1l_w_lg_w_lg_dataout9857w9858w(0) AND wire_nlOiillOO_w_lg_dataout9853w(0); + wire_nlOiilO1l_w_lg_w_lg_w_lg_dataout9857w9858w9859w(0) <= wire_nlOiilO1l_w_lg_w_lg_dataout9857w9858w(0) AND wire_nlOiillOO_dataout; + wire_nlOiilO1l_w_lg_w_lg_dataout9857w9858w(0) <= wire_nlOiilO1l_w_lg_dataout9857w(0) AND wire_nlOiilO1i_w_lg_dataout9851w(0); + wire_nlOiilO1l_w_lg_w_lg_dataout9857w9862w(0) <= wire_nlOiilO1l_w_lg_dataout9857w(0) AND wire_nlOiilO1i_dataout; + wire_nlOiilO1l_w_lg_dataout9852w(0) <= wire_nlOiilO1l_dataout AND wire_nlOiilO1i_w_lg_dataout9851w(0); + wire_nlOiilO1l_w_lg_dataout9857w(0) <= NOT wire_nlOiilO1l_dataout; + wire_nlOiilOii_dataout <= wire_nlOiilOll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiilOil_dataout <= wire_nlOiilOlO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiilOiO_dataout <= wire_nlOiilOOi_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiilOli_dataout <= wire_nlOiilOOl_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiilOll_dataout <= nlOiiO1lO WHEN niOl10i0i = '1' ELSE nlOiiO11i; + wire_nlOiilOlO_dataout <= nlOiiO1Oi WHEN niOl10i0i = '1' ELSE nlOiilO1O; + wire_nlOiilOOi_dataout <= nlOiiO1Ol WHEN niOl10i0i = '1' ELSE nlOiilO0i; + wire_nlOiilOOl_dataout <= nlOiiO1OO WHEN niOl10i0i = '1' ELSE nlOiilO0l; + wire_nlOiiO00i_dataout <= wire_nlOiiO0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiO00l_dataout <= wire_nlOiiO0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiO00O_dataout <= wire_niO01ill_w_lg_nlOiiO1iO28670w(0) WHEN (wire_w_lg_niOl10i0l28669w(0) AND (NOT ((((NOT (nlOiiO1lO XOR niil00Ol)) AND (NOT (nlOiiO1Oi XOR niil010i))) AND (NOT (nlOiiO1Ol XOR niil010l))) AND (NOT (nlOiiO1OO XOR niil010O))))) = '1' ELSE nlOiiO1iO; + wire_nlOiiO01i_dataout <= wire_nlOiiO00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiO01l_dataout <= wire_nlOiiO0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiO01O_dataout <= wire_nlOiiO0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiO0il_dataout <= niil00Ol WHEN wire_w_lg_niOl10i0l28669w(0) = '1' ELSE nlOiiO1lO; + wire_nlOiiO0iO_dataout <= niil010i WHEN wire_w_lg_niOl10i0l28669w(0) = '1' ELSE nlOiiO1Oi; + wire_nlOiiO0li_dataout <= niil010l WHEN wire_w_lg_niOl10i0l28669w(0) = '1' ELSE nlOiiO1Ol; + wire_nlOiiO0ll_dataout <= niil010O WHEN wire_w_lg_niOl10i0l28669w(0) = '1' ELSE nlOiiO1OO; + wire_nlOiiO10l_dataout <= nlOiilO0O AND NOT(wire_niO01lOO_dataout); + wire_nlOiiO11O_dataout <= nlOiiO10O AND NOT(wire_niO01lOO_dataout); + wire_nlOiiO1ii_dataout <= nlOiiO1iO AND NOT(wire_niO01O0O_dataout); + wire_nlOiiO1li_dataout <= nlOiiO1il AND NOT(wire_niO01O0O_dataout); + wire_nlOiiO1ll_dataout <= nlOiiO10i AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOi0i_dataout <= wire_n1l10OlO_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiOlli; + wire_nlOiiOi0l_dataout <= wire_n1l10OOi_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiOiiO; + wire_nlOiiOi0O_dataout <= wire_n1l10OOl_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiOili; + wire_nlOiiOiii_dataout <= wire_n1l10OOO_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiOill; + wire_nlOiiOiil_dataout <= wire_n1l1i11i_dataout WHEN (NOT k_gbl_hip(23)) = '1' ELSE nlOiiOilO; + wire_nlOiiOiOl_dataout <= wire_nlOiiOl0i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOiOO_dataout <= wire_nlOiiOl0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOl0i_dataout <= nlOiiOO0O WHEN niOl10i0O = '1' ELSE nlOiiOlli; + wire_nlOiiOl0l_dataout <= nlOiiOOii WHEN niOl10i0O = '1' ELSE nlOiiOiiO; + wire_nlOiiOl0O_dataout <= nlOiiOOil WHEN niOl10i0O = '1' ELSE nlOiiOili; + wire_nlOiiOl1i_dataout <= wire_nlOiiOl0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOl1l_dataout <= wire_nlOiiOlii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOl1O_dataout <= wire_nlOiiOlil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOlii_dataout <= nlOiiOOiO WHEN niOl10i0O = '1' ELSE nlOiiOill; + wire_nlOiiOlil_dataout <= nlOiiOOli WHEN niOl10i0O = '1' ELSE nlOiiOilO; + wire_nlOiiOllO_dataout <= nlOiiOlOO AND NOT(wire_niO01lOO_dataout); + wire_nlOiiOlOl_dataout <= nlOiiOiOi AND NOT(wire_niO01lOO_dataout); + wire_nlOiiOO0i_dataout <= nlOiiOO1l AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOO0l_dataout <= nlOiiOlOi AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOO1i_dataout <= nlOiiOO1O AND NOT(wire_niO01O0O_dataout); + wire_nlOiiOOll_dataout <= wire_nlOil111l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiOOlO_dataout <= wire_nlOil110i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiOOOi_dataout <= wire_nlOil110l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiOOOl_dataout <= wire_nlOil110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiiOOOO_dataout <= wire_nlOil11ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOil000i_dataout <= wire_nlOil0ilO_o(2) AND NOT(wire_niO01O0O_dataout); + wire_nlOil000l_dataout <= wire_nlOil0ilO_o(3) AND NOT(wire_niO01O0O_dataout); + wire_nlOil000O_dataout <= wire_nlOil0ilO_o(4) AND NOT(wire_niO01O0O_dataout); + wire_nlOil001l_dataout <= wire_nlOil0iOi_o AND NOT(wire_niO01O0O_dataout); + wire_nlOil001O_dataout <= wire_nlOil0ilO_o(1) AND NOT(wire_niO01O0O_dataout); + wire_nlOil00ii_dataout <= nlOil1i0O AND NOT(wire_niO01O0O_dataout); + wire_nlOil00il_dataout <= nlOil1i1l AND NOT(wire_niO01O0O_dataout); + wire_nlOil00iO_dataout <= nlOil1i0i AND NOT(wire_niO01O0O_dataout); + wire_nlOil00li_dataout <= nlOil1i0l AND NOT(wire_niO01O0O_dataout); + wire_nlOil00ll_dataout <= wire_nlOil0lOi_dataout OR wire_niO01O0O_dataout; + wire_nlOil00lO_dataout <= wire_nlOil0lOl_dataout OR wire_niO01O0O_dataout; + wire_nlOil00Oi_dataout <= wire_nlOil0lOO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil00Ol_dataout <= wire_nlOil0O1i_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil00OO_dataout <= wire_nlOil0liO_dataout OR wire_niO01O0O_dataout; + wire_nlOil0i0i_dataout <= nlOil01Oi AND NOT(wire_niO01O0O_dataout); + wire_nlOil0i0l_dataout <= nlOil01Ol AND NOT(wire_niO01O0O_dataout); + wire_nlOil0i0O_dataout <= nlOil01OO AND NOT(wire_niO01O0O_dataout); + wire_nlOil0i1i_dataout <= wire_nlOil0lli_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil0i1l_dataout <= wire_nlOil0lll_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil0i1O_dataout <= wire_nlOil0llO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil0iii_dataout <= nlOil001i AND NOT(wire_niO01O0O_dataout); + wire_nlOil0iil_dataout <= wire_nlOil0l0l_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil0iiO_dataout <= wire_nlOil0l0O_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil0ili_dataout <= wire_nlOil0lii_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil0ill_dataout <= wire_nlOil0lil_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOil0l0l_dataout <= nlOil010l WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil01Oi; + wire_nlOil0l0O_dataout <= nlOil010O WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil01Ol; + wire_nlOil0lii_dataout <= nlOil01ii WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil01OO; + wire_nlOil0lil_dataout <= nlOil01il WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil001i; + wire_nlOil0liO_dataout <= nlOil011i WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil010l; + wire_nlOil0lli_dataout <= nlOil011l WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil010O; + wire_nlOil0lll_dataout <= nlOil011O WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil01ii; + wire_nlOil0llO_dataout <= nlOil010i WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil01il; + wire_nlOil0lOi_dataout <= (wire_w_lg_niOl10lli28474w(0) XOR nlOil011i) WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil011i; + wire_nlOil0lOl_dataout <= ((niOl10lli AND wire_w_lg_niOl10liO28475w(0)) XOR nlOil011l) WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil011l; + wire_nlOil0lOO_dataout <= ((wire_w_lg_niOl10lil28482w(0) AND wire_w_lg_niOl10lii28478w(0)) XOR nlOil011O) WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil011O; + wire_nlOil0O1i_dataout <= ((NOT (niOl10lil OR wire_w_lg_niOl10lii28478w(0))) XOR nlOil010i) WHEN wire_nlOl1l0il_dataout = '1' ELSE nlOil010i; + wire_nlOil100i_dataout <= nlOil01iO AND NOT(wire_niO01lOO_dataout); + wire_nlOil100l_dataout <= nlOil01li AND NOT(wire_niO01lOO_dataout); + wire_nlOil100O_dataout <= nlOil01ll AND NOT(wire_niO01lOO_dataout); + wire_nlOil10ii_dataout <= nlOil01lO AND NOT(wire_niO01lOO_dataout); + wire_nlOil110i_dataout <= wire_n1l10OlO_dataout WHEN wire_w_lg_niOl10iil28649w(0) = '1' ELSE nlOiiOO0O; + wire_nlOil110l_dataout <= wire_n1l10OOi_dataout WHEN wire_w_lg_niOl10iil28649w(0) = '1' ELSE nlOiiOOii; + wire_nlOil110O_dataout <= wire_n1l10OOl_dataout WHEN wire_w_lg_niOl10iil28649w(0) = '1' ELSE nlOiiOOil; + wire_nlOil111i_dataout <= wire_nlOil11il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOil111l_dataout <= wire_niO01ill_w_lg_nlOiiOO1O28650w(0) WHEN (wire_w_lg_niOl10iil28649w(0) AND wire_w_lg_niOl10iii28651w(0)) = '1' ELSE nlOiiOO1O; + wire_nlOil11ii_dataout <= wire_n1l10OOO_dataout WHEN wire_w_lg_niOl10iil28649w(0) = '1' ELSE nlOiiOOiO; + wire_nlOil11il_dataout <= wire_n1l1i11i_dataout WHEN wire_w_lg_niOl10iil28649w(0) = '1' ELSE nlOiiOOli; + wire_nlOil1iii_dataout <= nlOil101l AND NOT(wire_niO01lOO_dataout); + wire_nlOil1iil_dataout <= nlOil101O AND NOT(wire_niO01lOO_dataout); + wire_nlOil1iiO_dataout <= nlOil10il AND NOT(wire_niO01lOO_dataout); + wire_nlOil1ili_dataout <= nlOil1i1O AND NOT(wire_niO01lOO_dataout); + wire_nlOil1ill_dataout <= niOl10iOO AND NOT(wire_niO01lOO_dataout); + wire_nlOil1ilO_dataout <= niOl10iOi AND NOT(wire_niO01lOO_dataout); + wire_nlOil1iOi_dataout <= niOl10ili AND NOT(wire_niO01lOO_dataout); + wire_nlOil1iOl_dataout <= niOl10iiO AND NOT(wire_niO01lOO_dataout); + wire_nlOil1O0i_dataout <= nlOil10Oi AND NOT(wire_niO01O0O_dataout); + wire_nlOil1O0l_dataout <= nlOil10Ol AND NOT(wire_niO01O0O_dataout); + wire_nlOil1O0O_dataout <= nlOil10OO AND NOT(wire_niO01O0O_dataout); + wire_nlOil1Oii_dataout <= nlOil1i1i AND NOT(wire_niO01O0O_dataout); + wire_nlOili00i_dataout <= wire_niO01ill_w_lg_nlOili1Oi28463w(0) WHEN (nlOiOi11l AND (wire_w_lg_niOl10lll28464w(0) AND (nlOiOi11l XOR nlOili01i))) = '1' ELSE nlOili1Oi; + wire_nlOili01l_dataout <= wire_nlOili00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOili01O_dataout <= wire_nlOili0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOili0il_dataout <= nlOili01i WHEN niOl10lll = '1' ELSE nlOiOi11l; + wire_nlOili11i_dataout <= nlOili10l WHEN k_gbl_hip(23) = '1' ELSE nlOiOi11l; + wire_nlOili11O_dataout <= (nlOili1lO XOR nlOili1li) AND NOT(wire_niO01O0O_dataout); + wire_nlOili1ii_dataout <= nlOili1li AND NOT(wire_niO01lOO_dataout); + wire_nlOili1iO_dataout <= nlOili11l AND NOT(wire_niO01lOO_dataout); + wire_nlOili1ll_dataout <= nlOili1Oi AND NOT(wire_niO01O0O_dataout); + wire_nlOili1Ol_dataout <= nlOili1lO AND NOT(wire_niO01O0O_dataout); + wire_nlOili1OO_dataout <= nlOili1il AND NOT(wire_niO01O0O_dataout); + wire_nlOilii0i_dataout <= nlOill0iO AND NOT(wire_niO01O0O_dataout); + wire_nlOilii0l_dataout <= nlOill0li AND NOT(wire_niO01O0O_dataout); + wire_nlOilii0O_dataout <= nlOill0ll AND NOT(wire_niO01O0O_dataout); + wire_nlOilii1O_dataout <= nlOill0il AND NOT(wire_niO01O0O_dataout); + wire_nlOiliil_dataout <= wire_nlOlO1Oi_dataout AND NOT(niOO00l1l); + wire_nlOiliiO_dataout <= wire_nlOli11l_dataout AND NOT(niOO00l1l); + wire_nlOilil0O_dataout <= nlOilii1i AND NOT(wire_niO01O0O_dataout); + wire_nlOilili_dataout <= wire_nlOll0il_dataout AND NOT(niOO00l1l); + wire_nlOililii_dataout <= nlOilii1l AND NOT(wire_niO01O0O_dataout); + wire_nlOililil_dataout <= nlOiliiii AND NOT(wire_niO01O0O_dataout); + wire_nlOililiO_dataout <= nlOilil1l AND NOT(wire_niO01O0O_dataout); + wire_nlOilill_dataout <= wire_nlOll0iO_dataout AND NOT(niOO00l1l); + wire_nlOililli_dataout <= niOl10O1O AND NOT(wire_niO01O0O_dataout); + wire_nlOililll_dataout <= niOl10O1i AND NOT(wire_niO01O0O_dataout); + wire_nlOilillO_dataout <= niOl10lOi AND NOT(wire_niO01O0O_dataout); + wire_nlOililO_dataout <= wire_nlOll0li_dataout AND NOT(niOO00l1l); + wire_nlOililOi_dataout <= niOl10llO AND NOT(wire_niO01O0O_dataout); + wire_nlOiliOi_dataout <= wire_nlOll0ll_dataout AND NOT(niOO00l1l); + wire_nlOiliOl_dataout <= wire_nlOll0lO_dataout AND NOT(niOO00l1l); + wire_nlOiliOO_dataout <= wire_nlOll0Oi_dataout AND NOT(niOO00l1l); + wire_nlOill0i_dataout <= wire_nlOlli1l_dataout AND NOT(niOO00l1l); + wire_nlOill0l_dataout <= wire_nlOlli1O_dataout AND NOT(niOO00l1l); + wire_nlOill0O_dataout <= wire_nlOlli0i_dataout AND NOT(niOO00l1l); + wire_nlOill10i_dataout <= nlOiliiOi AND NOT(wire_niO01lOO_dataout); + wire_nlOill10l_dataout <= nlOiliiOl AND NOT(wire_niO01lOO_dataout); + wire_nlOill10O_dataout <= nlOiliiOO AND NOT(wire_niO01lOO_dataout); + wire_nlOill11O_dataout <= nlOiliilO AND NOT(wire_niO01lOO_dataout); + wire_nlOill1i_dataout <= wire_nlOll0Ol_dataout AND NOT(niOO00l1l); + wire_nlOill1l_dataout <= wire_nlOll0OO_dataout AND NOT(niOO00l1l); + wire_nlOill1O_dataout <= wire_nlOlli1i_dataout AND NOT(niOO00l1l); + wire_nlOilli0i_dataout <= wire_nlOilllll_o(3) AND NOT(wire_niO01lOO_dataout); + wire_nlOilli0l_dataout <= wire_nlOilllll_o(4) AND NOT(wire_niO01lOO_dataout); + wire_nlOilli0O_dataout <= nlOilil0l AND NOT(wire_niO01lOO_dataout); + wire_nlOilli1i_dataout <= wire_nlOillllO_o AND NOT(wire_niO01lOO_dataout); + wire_nlOilli1l_dataout <= wire_nlOilllll_o(1) AND NOT(wire_niO01lOO_dataout); + wire_nlOilli1O_dataout <= wire_nlOilllll_o(2) AND NOT(wire_niO01lOO_dataout); + wire_nlOillii_dataout <= wire_nlOlli0l_dataout AND NOT(niOO00l1l); + wire_nlOilliii_dataout <= nlOilil1i AND NOT(wire_niO01lOO_dataout); + wire_nlOilliil_dataout <= nlOilil1O AND NOT(wire_niO01lOO_dataout); + wire_nlOilliiO_dataout <= nlOilil0i AND NOT(wire_niO01lOO_dataout); + wire_nlOillil_dataout <= wire_nlOlli0O_dataout AND NOT(niOO00l1l); + wire_nlOillili_dataout <= wire_nlOillOlO_dataout OR wire_niO01lOO_dataout; + wire_nlOillill_dataout <= wire_nlOillOOi_dataout OR wire_niO01lOO_dataout; + wire_nlOillilO_dataout <= wire_nlOillOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilliO_dataout <= wire_nlOlliii_dataout AND NOT(niOO00l1l); + wire_nlOilliOi_dataout <= wire_nlOillOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilliOl_dataout <= wire_nlOillOil_dataout OR wire_niO01lOO_dataout; + wire_nlOilliOO_dataout <= wire_nlOillOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilll0i_dataout <= nlOill0Oi AND NOT(wire_niO01lOO_dataout); + wire_nlOilll0l_dataout <= nlOill0Ol AND NOT(wire_niO01lOO_dataout); + wire_nlOilll0O_dataout <= nlOill0OO AND NOT(wire_niO01lOO_dataout); + wire_nlOilll1i_dataout <= wire_nlOillOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilll1l_dataout <= wire_nlOillOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilll1O_dataout <= nlOill0lO AND NOT(wire_niO01lOO_dataout); + wire_nlOillli_dataout <= wire_nlOlliil_dataout AND NOT(niOO00l1l); + wire_nlOilllii_dataout <= wire_nlOillO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilllil_dataout <= wire_nlOillO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOillliO_dataout <= wire_nlOillO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOillll_dataout <= wire_nlOlliiO_dataout AND NOT(niOO00l1l); + wire_nlOilllli_dataout <= wire_nlOillOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilllO_dataout <= wire_nlOllili_dataout AND NOT(niOO00l1l); + wire_nlOillO0i_dataout <= nlOill00i WHEN ni0i1i0l = '1' ELSE nlOill0lO; + wire_nlOillO0l_dataout <= nlOill00l WHEN ni0i1i0l = '1' ELSE nlOill0Oi; + wire_nlOillO0O_dataout <= nlOill00O WHEN ni0i1i0l = '1' ELSE nlOill0Ol; + wire_nlOillOi_dataout <= wire_nlOllill_dataout AND NOT(niOO00l1l); + wire_nlOillOii_dataout <= nlOill0ii WHEN ni0i1i0l = '1' ELSE nlOill0OO; + wire_nlOillOil_dataout <= nlOill1OO WHEN ni0i1i0l = '1' ELSE nlOill00i; + wire_nlOillOiO_dataout <= nlOill01i WHEN ni0i1i0l = '1' ELSE nlOill00l; + wire_nlOillOl_dataout <= wire_nlOllilO_dataout AND NOT(niOO00l1l); + wire_nlOillOli_dataout <= nlOill01l WHEN ni0i1i0l = '1' ELSE nlOill00O; + wire_nlOillOll_dataout <= nlOill01O WHEN ni0i1i0l = '1' ELSE nlOill0ii; + wire_nlOillOlO_dataout <= (wire_w_lg_niOl10OlO28289w(0) XOR nlOill1OO) WHEN ni0i1i0l = '1' ELSE nlOill1OO; + wire_nlOillOO_dataout <= wire_nlOlliOi_dataout AND NOT(niOO00l1l); + wire_nlOillOOi_dataout <= ((niOl10OlO AND wire_w_lg_niOl10Oll28290w(0)) XOR nlOill01i) WHEN ni0i1i0l = '1' ELSE nlOill01i; + wire_nlOillOOl_dataout <= ((wire_w_lg_niOl10Oli28297w(0) AND wire_w_lg_niOl10OiO28293w(0)) XOR nlOill01l) WHEN ni0i1i0l = '1' ELSE nlOill01l; + wire_nlOillOOO_dataout <= ((NOT (niOl10Oli OR wire_w_lg_niOl10OiO28293w(0))) XOR nlOill01O) WHEN ni0i1i0l = '1' ELSE nlOill01O; + wire_nlOilO00O_dataout <= nlOilO0iO AND NOT(wire_niO01lOO_dataout); + wire_nlOilO01l_dataout <= (nlOilO0ll XOR nlOilO0iO) AND NOT(wire_niO01O0O_dataout); + wire_nlOilO0i_dataout <= wire_nlOlll1l_dataout AND NOT(niOO00l1l); + wire_nlOilO0il_dataout <= nlOilO01i AND NOT(wire_niO01lOO_dataout); + wire_nlOilO0l_dataout <= wire_nlOlll1O_dataout AND NOT(niOO00l1l); + wire_nlOilO0li_dataout <= nlOilO0lO AND NOT(wire_niO01O0O_dataout); + wire_nlOilO0O_dataout <= wire_nlOlll0i_dataout AND NOT(niOO00l1l); + wire_nlOilO0Oi_dataout <= nlOilO0ll AND NOT(wire_niO01O0O_dataout); + wire_nlOilO0Ol_dataout <= nlOilO0ii AND NOT(wire_niO01O0O_dataout); + wire_nlOilO1i_dataout <= wire_nlOlliOl_dataout AND NOT(niOO00l1l); + wire_nlOilO1l_dataout <= wire_nlOlliOO_dataout AND NOT(niOO00l1l); + wire_nlOilO1O_dataout <= wire_nlOlll1i_dataout AND NOT(niOO00l1l); + wire_nlOilO1OO_dataout <= nlOilO00i WHEN k_gbl_hip(23) = '1' ELSE ni0i110i; + wire_nlOilOi1i_dataout <= wire_nlOilOi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilOi1l_dataout <= wire_nlOilOiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilOi1O_dataout <= wire_niO01ill_w_lg_nlOilO0lO28278w(0) WHEN ((wire_w_lg_niOl10OOi28279w(0) AND (nlOilO0OO XOR ni0i110i)) AND ni0i110i) = '1' ELSE nlOilO0lO; + wire_nlOilOii_dataout <= wire_nlOlll0l_dataout AND NOT(niOO00l1l); + wire_nlOilOiii_dataout <= nlOilO0OO WHEN niOl10OOi = '1' ELSE ni0i110i; + wire_nlOilOiiO_dataout <= nlOilOiOi WHEN k_gbl_hip(23) = '1' ELSE nlOiO10il; + wire_nlOilOil_dataout <= wire_nlOlll0O_dataout AND NOT(niOO00l1l); + wire_nlOilOill_dataout <= (nlOilOl0l XOR nlOilOl1O) AND NOT(wire_niO01O0O_dataout); + wire_nlOilOiO_dataout <= wire_nlOlllii_dataout AND NOT(niOO00l1l); + wire_nlOilOiOO_dataout <= nlOilOl1O AND NOT(wire_niO01lOO_dataout); + wire_nlOilOl0i_dataout <= nlOilOl0O AND NOT(wire_niO01O0O_dataout); + wire_nlOilOl1l_dataout <= nlOilOili AND NOT(wire_niO01lOO_dataout); + wire_nlOilOli_dataout <= wire_nlOlllil_dataout AND NOT(niOO00l1l); + wire_nlOilOlii_dataout <= nlOilOl0l AND NOT(wire_niO01O0O_dataout); + wire_nlOilOlil_dataout <= nlOilOl1i AND NOT(wire_niO01O0O_dataout); + wire_nlOilOll_dataout <= wire_nlOllliO_dataout AND NOT(niOO00l1l); + wire_nlOilOlli_dataout <= wire_nlOilOllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilOlll_dataout <= wire_nlOilOO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOilOllO_dataout <= wire_niO01ill_w_lg_nlOilOl0O28271w(0) WHEN (nlOiO10il AND (wire_w_lg_niOl10OOl28272w(0) AND (nlOiO10il XOR nlOilOliO))) = '1' ELSE nlOilOl0O; + wire_nlOilOlO_dataout <= wire_nlOlllli_dataout AND NOT(niOO00l1l); + wire_nlOilOO0l_dataout <= (nlOilOOOl XOR nlOilOOlO) AND NOT(wire_niO01O0O_dataout); + wire_nlOilOO1i_dataout <= nlOilOliO WHEN niOl10OOl = '1' ELSE nlOiO10il; + wire_nlOilOO1O_dataout <= nlOilOOii WHEN k_gbl_hip(23) = '1' ELSE nlOiO1lOO; + wire_nlOilOOi_dataout <= wire_nlOlllll_dataout AND NOT(niOO00l1l); + wire_nlOilOOiO_dataout <= nlOilOOlO AND NOT(wire_niO01lOO_dataout); + wire_nlOilOOl_dataout <= wire_nlOllllO_dataout AND NOT(niOO00l1l); + wire_nlOilOOll_dataout <= nlOilOO0i AND NOT(wire_niO01lOO_dataout); + wire_nlOilOOO_dataout <= wire_nlOlllOi_dataout AND NOT(niOO00l1l); + wire_nlOilOOOi_dataout <= nlOilOOOO AND NOT(wire_niO01O0O_dataout); + wire_nlOiO000i_dataout <= wire_nlOili0li_q(7) WHEN k_gbl_hip(23) = '1' ELSE ni0i1l0O; + wire_nlOiO000i_w_lg_w_lg_w36605w36606w36610w(0) <= wire_nlOiO000i_w_lg_w36605w36606w(0) AND wire_nlOiO01Oi_dataout; + wire_nlOiO000i_w_lg_w36605w36606w(0) <= wire_nlOiO000i_w36605w(0) AND wire_nlOiO01Ol_dataout; + wire_nlOiO000i_w36605w(0) <= wire_nlOiO000i_w_lg_w_lg_w_lg_dataout36602w36603w36604w(0) AND wire_nlOiO01OO_dataout; + wire_nlOiO000i_w_lg_w_lg_w_lg_dataout36602w36603w36604w(0) <= wire_nlOiO000i_w_lg_w_lg_dataout36602w36603w(0) AND wire_nlOiO001i_dataout; + wire_nlOiO000i_w_lg_w_lg_dataout36602w36603w(0) <= wire_nlOiO000i_w_lg_dataout36602w(0) AND wire_nlOiO001l_dataout; + wire_nlOiO000i_w_lg_dataout36602w(0) <= wire_nlOiO000i_dataout AND wire_nlOiO001O_dataout; + wire_nlOiO000l_dataout <= wire_nlOili0li_q(8) WHEN k_gbl_hip(23) = '1' ELSE ni0i1lii; + wire_nlOiO000O_dataout <= wire_nlOili0li_q(9) WHEN k_gbl_hip(23) = '1' ELSE ni0i1lil; + wire_nlOiO001i_dataout <= wire_nlOili0li_q(4) WHEN k_gbl_hip(23) = '1' ELSE ni0i1l1O; + wire_nlOiO001l_dataout <= wire_nlOili0li_q(5) WHEN k_gbl_hip(23) = '1' ELSE ni0i1l0i; + wire_nlOiO001O_dataout <= wire_nlOili0li_q(6) WHEN k_gbl_hip(23) = '1' ELSE ni0i1l0l; + wire_nlOiO00i_dataout <= wire_nlOlO11l_dataout AND NOT(niOO00l1l); + wire_nlOiO00ii_dataout <= wire_nlOili0li_q(10) WHEN k_gbl_hip(23) = '1' ELSE ni0i1liO; + wire_nlOiO00il_dataout <= wire_nlOili0li_q(11) WHEN k_gbl_hip(23) = '1' ELSE ni0i1lli; + wire_nlOiO00iO_dataout <= wire_nlOili0li_q(12) WHEN k_gbl_hip(23) = '1' ELSE ni0i1lll; + wire_nlOiO00l_dataout <= wire_nlOlO11O_dataout AND NOT(niOO00l1l); + wire_nlOiO00li_dataout <= wire_nlOili0li_q(13) WHEN k_gbl_hip(23) = '1' ELSE ni0i1llO; + wire_nlOiO00ll_dataout <= wire_nlOili0li_q(14) WHEN k_gbl_hip(23) = '1' ELSE ni0i1lOi; + wire_nlOiO00lO_dataout <= wire_nlOili0li_q(15) WHEN k_gbl_hip(23) = '1' ELSE ni0i1lOl; + wire_nlOiO00O_dataout <= wire_nlOlO10i_dataout AND NOT(niOO00l1l); + wire_nlOiO00Oi_dataout <= wire_nlOili0li_q(16) WHEN k_gbl_hip(23) = '1' ELSE ni0i1lOO; + wire_nlOiO00Ol_dataout <= wire_nlOili0li_q(17) WHEN k_gbl_hip(23) = '1' ELSE ni0i1O1i; + wire_nlOiO00OO_dataout <= wire_nlOili0li_q(18) WHEN k_gbl_hip(23) = '1' ELSE ni0i1O1l; + wire_nlOiO010i_dataout <= wire_nlOili0li_q(64) WHEN k_gbl_hip(23) = '1' ELSE ni0i1i0O; + wire_nlOiO010l_dataout <= wire_nlOili0li_q(65) WHEN k_gbl_hip(23) = '1' ELSE ni0i1iii; + wire_nlOiO010O_dataout <= wire_nlOili0li_q(66) WHEN k_gbl_hip(23) = '1' ELSE ni0i1iil; + wire_nlOiO011l_dataout <= wire_nlOiO011O_dataout OR wire_niO01lOO_dataout; + wire_nlOiO011O_dataout <= wire_niO01iOi_w_lg_nlOiO10Ol28193w(0) OR NOT((n11li1li AND wire_niO01iOi_w_lg_n11li1iO9835w(0))); + wire_nlOiO01i_dataout <= wire_nlOllOOl_dataout AND NOT(niOO00l1l); + wire_nlOiO01ii_dataout <= wire_nlOili0li_q(67) WHEN k_gbl_hip(23) = '1' ELSE ni0i1iiO; + wire_nlOiO01il_dataout <= wire_nlOili0li_q(68) WHEN k_gbl_hip(23) = '1' ELSE ni0i1ili; + wire_nlOiO01iO_dataout <= wire_nlOili0li_q(69) WHEN k_gbl_hip(23) = '1' ELSE ni0i1ill; + wire_nlOiO01l_dataout <= wire_nlOllOOO_dataout AND NOT(niOO00l1l); + wire_nlOiO01li_dataout <= wire_nlOili0li_q(70) WHEN k_gbl_hip(23) = '1' ELSE ni0i1ilO; + wire_nlOiO01ll_dataout <= wire_nlOili0li_q(71) WHEN k_gbl_hip(23) = '1' ELSE ni0i1iOi; + wire_nlOiO01lO_dataout <= wire_nlOili0li_q(0) WHEN k_gbl_hip(23) = '1' ELSE ni0i1iOl; + wire_nlOiO01lO_w_lg_dataout36611w(0) <= NOT wire_nlOiO01lO_dataout; + wire_nlOiO01O_dataout <= wire_nlOlO11i_dataout AND NOT(niOO00l1l); + wire_nlOiO01Oi_dataout <= wire_nlOili0li_q(1) WHEN k_gbl_hip(23) = '1' ELSE ni0i1iOO; + wire_nlOiO01Oi_w_lg_dataout36607w(0) <= NOT wire_nlOiO01Oi_dataout; + wire_nlOiO01Ol_dataout <= wire_nlOili0li_q(2) WHEN k_gbl_hip(23) = '1' ELSE ni0i1l1i; + wire_nlOiO01OO_dataout <= wire_nlOili0li_q(3) WHEN k_gbl_hip(23) = '1' ELSE ni0i1l1l; + wire_nlOiO0i0i_dataout <= wire_nlOili0li_q(22) WHEN k_gbl_hip(23) = '1' ELSE ni0i1O0O; + wire_nlOiO0i0l_dataout <= wire_nlOili0li_q(23) WHEN k_gbl_hip(23) = '1' ELSE ni0i1Oii; + wire_nlOiO0i0O_dataout <= wire_nlOili0li_q(24) WHEN k_gbl_hip(23) = '1' ELSE ni0i1Oil; + wire_nlOiO0i0O_w_lg_dataout36600w(0) <= NOT wire_nlOiO0i0O_dataout; + wire_nlOiO0i1i_dataout <= wire_nlOili0li_q(19) WHEN k_gbl_hip(23) = '1' ELSE ni0i1O1O; + wire_nlOiO0i1l_dataout <= wire_nlOili0li_q(20) WHEN k_gbl_hip(23) = '1' ELSE ni0i1O0i; + wire_nlOiO0i1O_dataout <= wire_nlOili0li_q(21) WHEN k_gbl_hip(23) = '1' ELSE ni0i1O0l; + wire_nlOiO0ii_dataout <= wire_nlOlO10l_dataout AND NOT(niOO00l1l); + wire_nlOiO0iii_dataout <= wire_nlOili0li_q(25) WHEN k_gbl_hip(23) = '1' ELSE ni0i1OiO; + wire_nlOiO0iii_w_lg_dataout36598w(0) <= NOT wire_nlOiO0iii_dataout; + wire_nlOiO0iil_dataout <= wire_nlOili0li_q(26) WHEN k_gbl_hip(23) = '1' ELSE ni0i1Oli; + wire_nlOiO0iil_w_lg_dataout36587w(0) <= NOT wire_nlOiO0iil_dataout; + wire_nlOiO0iiO_dataout <= wire_nlOili0li_q(27) WHEN k_gbl_hip(23) = '1' ELSE ni0i1Oll; + wire_nlOiO0il_dataout <= wire_nlOlO10O_dataout AND NOT(niOO00l1l); + wire_nlOiO0ili_dataout <= wire_nlOili0li_q(28) WHEN k_gbl_hip(23) = '1' ELSE ni0i1OlO; + wire_nlOiO0ill_dataout <= wire_nlOili0li_q(29) WHEN k_gbl_hip(23) = '1' ELSE ni0i1OOi; + wire_nlOiO0ill_w_lg_dataout36593w(0) <= NOT wire_nlOiO0ill_dataout; + wire_nlOiO0ilO_dataout <= wire_nlOili0li_q(30) WHEN k_gbl_hip(23) = '1' ELSE ni0i1OOl; + wire_nlOiO0iO_dataout <= wire_nlOlO1ii_dataout AND NOT(niOO00l1l); + wire_nlOiO0iOi_dataout <= wire_nlOili0li_q(31) WHEN k_gbl_hip(23) = '1' ELSE ni0i1OOO; + wire_nlOiO0iOi_w_lg_w_lg_w36595w36596w36597w(0) <= wire_nlOiO0iOi_w_lg_w36595w36596w(0) AND wire_nlOiO0iil_dataout; + wire_nlOiO0iOi_w_lg_w36595w36596w(0) <= wire_nlOiO0iOi_w36595w(0) AND wire_nlOiO0iiO_dataout; + wire_nlOiO0iOi_w36586w(0) <= wire_nlOiO0iOi_w_lg_w_lg_w_lg_dataout36583w36584w36585w(0) AND wire_nlOiO0iiO_dataout; + wire_nlOiO0iOi_w36595w(0) <= wire_nlOiO0iOi_w_lg_w_lg_w_lg_dataout36591w36592w36594w(0) AND wire_nlOiO0ili_dataout; + wire_nlOiO0iOi_w_lg_w_lg_w_lg_dataout36583w36584w36585w(0) <= wire_nlOiO0iOi_w_lg_w_lg_dataout36583w36584w(0) AND wire_nlOiO0ili_dataout; + wire_nlOiO0iOi_w_lg_w_lg_w_lg_dataout36591w36592w36594w(0) <= wire_nlOiO0iOi_w_lg_w_lg_dataout36591w36592w(0) AND wire_nlOiO0ill_w_lg_dataout36593w(0); + wire_nlOiO0iOi_w_lg_w_lg_dataout36583w36584w(0) <= wire_nlOiO0iOi_w_lg_dataout36583w(0) AND wire_nlOiO0ill_dataout; + wire_nlOiO0iOi_w_lg_w_lg_dataout36591w36592w(0) <= wire_nlOiO0iOi_w_lg_dataout36591w(0) AND wire_nlOiO0ilO_dataout; + wire_nlOiO0iOi_w_lg_dataout36583w(0) <= wire_nlOiO0iOi_dataout AND wire_nlOiO0ilO_dataout; + wire_nlOiO0iOi_w_lg_dataout36591w(0) <= NOT wire_nlOiO0iOi_dataout; + wire_nlOiO0iOl_dataout <= wire_nlOili0li_q(32) WHEN k_gbl_hip(23) = '1' ELSE ni0i011i; + wire_nlOiO0iOl_w_lg_dataout36581w(0) <= NOT wire_nlOiO0iOl_dataout; + wire_nlOiO0iOO_dataout <= wire_nlOili0li_q(33) WHEN k_gbl_hip(23) = '1' ELSE ni0i011l; + wire_nlOiO0iOO_w_lg_dataout36577w(0) <= NOT wire_nlOiO0iOO_dataout; + wire_nlOiO0l0i_dataout <= wire_nlOili0li_q(37) WHEN k_gbl_hip(23) = '1' ELSE ni0i010O; + wire_nlOiO0l0l_dataout <= wire_nlOili0li_q(38) WHEN k_gbl_hip(23) = '1' ELSE ni0i01ii; + wire_nlOiO0l0O_dataout <= wire_nlOili0li_q(39) WHEN k_gbl_hip(23) = '1' ELSE ni0i01il; + wire_nlOiO0l0O_w_lg_w_lg_w36575w36576w36580w(0) <= wire_nlOiO0l0O_w_lg_w36575w36576w(0) AND wire_nlOiO0iOO_dataout; + wire_nlOiO0l0O_w_lg_w36575w36576w(0) <= wire_nlOiO0l0O_w36575w(0) AND wire_nlOiO0l1i_dataout; + wire_nlOiO0l0O_w36575w(0) <= wire_nlOiO0l0O_w_lg_w_lg_w_lg_dataout36572w36573w36574w(0) AND wire_nlOiO0l1l_dataout; + wire_nlOiO0l0O_w_lg_w_lg_w_lg_dataout36572w36573w36574w(0) <= wire_nlOiO0l0O_w_lg_w_lg_dataout36572w36573w(0) AND wire_nlOiO0l1O_dataout; + wire_nlOiO0l0O_w_lg_w_lg_dataout36572w36573w(0) <= wire_nlOiO0l0O_w_lg_dataout36572w(0) AND wire_nlOiO0l0i_dataout; + wire_nlOiO0l0O_w_lg_dataout36572w(0) <= wire_nlOiO0l0O_dataout AND wire_nlOiO0l0l_dataout; + wire_nlOiO0l1i_dataout <= wire_nlOili0li_q(34) WHEN k_gbl_hip(23) = '1' ELSE ni0i011O; + wire_nlOiO0l1l_dataout <= wire_nlOili0li_q(35) WHEN k_gbl_hip(23) = '1' ELSE ni0i010i; + wire_nlOiO0l1O_dataout <= wire_nlOili0li_q(36) WHEN k_gbl_hip(23) = '1' ELSE ni0i010l; + wire_nlOiO0li_dataout <= wire_nlOlO1il_dataout AND NOT(niOO00l1l); + wire_nlOiO0lii_dataout <= wire_nlOili0li_q(40) WHEN k_gbl_hip(23) = '1' ELSE ni0i01iO; + wire_nlOiO0lil_dataout <= wire_nlOili0li_q(41) WHEN k_gbl_hip(23) = '1' ELSE ni0i01li; + wire_nlOiO0liO_dataout <= wire_nlOili0li_q(42) WHEN k_gbl_hip(23) = '1' ELSE ni0i01ll; + wire_nlOiO0ll_dataout <= wire_nlOlO1iO_dataout AND NOT(niOO00l1l); + wire_nlOiO0lli_dataout <= wire_nlOili0li_q(43) WHEN k_gbl_hip(23) = '1' ELSE ni0i01lO; + wire_nlOiO0lll_dataout <= wire_nlOili0li_q(44) WHEN k_gbl_hip(23) = '1' ELSE ni0i01Oi; + wire_nlOiO0llO_dataout <= wire_nlOili0li_q(45) WHEN k_gbl_hip(23) = '1' ELSE ni0i01Ol; + wire_nlOiO0lO_dataout <= wire_nlOlO1li_dataout AND NOT(niOO00l1l); + wire_nlOiO0lOi_dataout <= wire_nlOili0li_q(46) WHEN k_gbl_hip(23) = '1' ELSE ni0i01OO; + wire_nlOiO0lOl_dataout <= wire_nlOili0li_q(47) WHEN k_gbl_hip(23) = '1' ELSE ni0i001i; + wire_nlOiO0lOO_dataout <= wire_nlOili0li_q(48) WHEN k_gbl_hip(23) = '1' ELSE ni0i001l; + wire_nlOiO0O0i_dataout <= wire_nlOili0li_q(52) WHEN k_gbl_hip(23) = '1' ELSE ni0i000O; + wire_nlOiO0O0l_dataout <= wire_nlOili0li_q(53) WHEN k_gbl_hip(23) = '1' ELSE ni0i00ii; + wire_nlOiO0O0O_dataout <= wire_nlOili0li_q(54) WHEN k_gbl_hip(23) = '1' ELSE ni0i00il; + wire_nlOiO0O1i_dataout <= wire_nlOili0li_q(49) WHEN k_gbl_hip(23) = '1' ELSE ni0i001O; + wire_nlOiO0O1l_dataout <= wire_nlOili0li_q(50) WHEN k_gbl_hip(23) = '1' ELSE ni0i000i; + wire_nlOiO0O1O_dataout <= wire_nlOili0li_q(51) WHEN k_gbl_hip(23) = '1' ELSE ni0i000l; + wire_nlOiO0Oi_dataout <= wire_nlOlO1ll_dataout AND NOT(niOO00l1l); + wire_nlOiO0Oii_dataout <= wire_nlOili0li_q(55) WHEN k_gbl_hip(23) = '1' ELSE ni0i00iO; + wire_nlOiO0Oil_dataout <= wire_nlOili0li_q(56) WHEN k_gbl_hip(23) = '1' ELSE ni0i00li; + wire_nlOiO0Oil_w_lg_dataout36570w(0) <= NOT wire_nlOiO0Oil_dataout; + wire_nlOiO0OiO_dataout <= wire_nlOili0li_q(57) WHEN k_gbl_hip(23) = '1' ELSE ni0i00ll; + wire_nlOiO0OiO_w_lg_dataout36568w(0) <= NOT wire_nlOiO0OiO_dataout; + wire_nlOiO0Ol_dataout <= wire_nlOlO1lO_dataout AND NOT(niOO00l1l); + wire_nlOiO0Oli_dataout <= wire_nlOili0li_q(58) WHEN k_gbl_hip(23) = '1' ELSE ni0i00lO; + wire_nlOiO0Oli_w_lg_dataout36557w(0) <= NOT wire_nlOiO0Oli_dataout; + wire_nlOiO0Oll_dataout <= wire_nlOili0li_q(59) WHEN k_gbl_hip(23) = '1' ELSE ni0i00Oi; + wire_nlOiO0OlO_dataout <= wire_nlOili0li_q(60) WHEN k_gbl_hip(23) = '1' ELSE ni0i00Ol; + wire_nlOiO0OO_dataout <= wire_nlOll0ii_dataout AND NOT(niOO00l1l); + wire_nlOiO0OOi_dataout <= wire_nlOili0li_q(61) WHEN k_gbl_hip(23) = '1' ELSE ni0i00OO; + wire_nlOiO0OOi_w_lg_dataout36563w(0) <= NOT wire_nlOiO0OOi_dataout; + wire_nlOiO0OOl_dataout <= wire_nlOili0li_q(62) WHEN k_gbl_hip(23) = '1' ELSE ni0i0i1i; + wire_nlOiO0OOO_dataout <= wire_nlOili0li_q(63) WHEN k_gbl_hip(23) = '1' ELSE ni0i0i1l; + wire_nlOiO0OOO_w_lg_w_lg_w36565w36566w36567w(0) <= wire_nlOiO0OOO_w_lg_w36565w36566w(0) AND wire_nlOiO0Oli_dataout; + wire_nlOiO0OOO_w_lg_w36565w36566w(0) <= wire_nlOiO0OOO_w36565w(0) AND wire_nlOiO0Oll_dataout; + wire_nlOiO0OOO_w36556w(0) <= wire_nlOiO0OOO_w_lg_w_lg_w_lg_dataout36553w36554w36555w(0) AND wire_nlOiO0Oll_dataout; + wire_nlOiO0OOO_w36565w(0) <= wire_nlOiO0OOO_w_lg_w_lg_w_lg_dataout36561w36562w36564w(0) AND wire_nlOiO0OlO_dataout; + wire_nlOiO0OOO_w_lg_w_lg_w_lg_dataout36553w36554w36555w(0) <= wire_nlOiO0OOO_w_lg_w_lg_dataout36553w36554w(0) AND wire_nlOiO0OlO_dataout; + wire_nlOiO0OOO_w_lg_w_lg_w_lg_dataout36561w36562w36564w(0) <= wire_nlOiO0OOO_w_lg_w_lg_dataout36561w36562w(0) AND wire_nlOiO0OOi_w_lg_dataout36563w(0); + wire_nlOiO0OOO_w_lg_w_lg_dataout36553w36554w(0) <= wire_nlOiO0OOO_w_lg_dataout36553w(0) AND wire_nlOiO0OOi_dataout; + wire_nlOiO0OOO_w_lg_w_lg_dataout36561w36562w(0) <= wire_nlOiO0OOO_w_lg_dataout36561w(0) AND wire_nlOiO0OOl_dataout; + wire_nlOiO0OOO_w_lg_dataout36553w(0) <= wire_nlOiO0OOO_dataout AND wire_nlOiO0OOl_dataout; + wire_nlOiO0OOO_w_lg_dataout36561w(0) <= NOT wire_nlOiO0OOO_dataout; + wire_nlOiO10i_dataout <= wire_nlOllO1l_dataout AND NOT(niOO00l1l); + wire_nlOiO10l_dataout <= wire_nlOllO1O_dataout AND NOT(niOO00l1l); + wire_nlOiO10O_dataout <= wire_nlOllO0i_dataout AND NOT(niOO00l1l); + wire_nlOiO10OO_dataout <= wire_nlOiO1iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO110i_dataout <= wire_nlOiO110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO110l_dataout <= wire_nlOiO11li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO110O_dataout <= wire_niO01ill_w_lg_nlOilOOOO28264w(0) WHEN (nlOiO1lOO AND (wire_w_lg_niOl10OOO28265w(0) AND (nlOiO1lOO XOR nlOiO111O))) = '1' ELSE nlOilOOOO; + wire_nlOiO111i_dataout <= nlOilOOOl AND NOT(wire_niO01O0O_dataout); + wire_nlOiO111l_dataout <= nlOilOOli AND NOT(wire_niO01O0O_dataout); + wire_nlOiO11i_dataout <= wire_nlOlllOl_dataout AND NOT(niOO00l1l); + wire_nlOiO11l_dataout <= wire_nlOlllOO_dataout AND NOT(niOO00l1l); + wire_nlOiO11li_dataout <= nlOiO111O WHEN niOl10OOO = '1' ELSE nlOiO1lOO; + wire_nlOiO11O_dataout <= wire_nlOllO1i_dataout AND NOT(niOO00l1l); + wire_nlOiO1i0i_dataout <= wire_nlOiO1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1i0l_dataout <= wire_nlOiO1l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1i0O_dataout <= wire_nlOiO1l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1i1i_dataout <= wire_nlOiO1l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1i1l_dataout <= wire_nlOiO1l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1i1O_dataout <= wire_nlOiO1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1ii_dataout <= wire_nlOllO0l_dataout AND NOT(niOO00l1l); + wire_nlOiO1iii_dataout <= wire_nlOiO1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1iil_dataout <= wire_nlOiO1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1iiO_dataout <= wire_nlOiO1liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1il_dataout <= wire_nlOllO0O_dataout AND NOT(niOO00l1l); + wire_nlOiO1ili_dataout <= wire_nlOiO1lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1ill_dataout <= wire_nlOiO1lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1ilO_dataout <= wire_nlOiO1llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1iO_dataout <= wire_nlOllOii_dataout AND NOT(niOO00l1l); + wire_nlOiO1iOi_dataout <= wire_nlOiO1lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1iOl_dataout <= wire_nlOiO1lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiO1iOO_dataout <= niOl1i11i WHEN nlOiO10Ol = '1' ELSE nlOiO1lOO; + wire_nlOiO1l0i_dataout <= wire_nlOiO1O0i_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO101O; + wire_nlOiO1l0l_dataout <= wire_nlOiO1O0l_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO100i; + wire_nlOiO1l0O_dataout <= wire_nlOiO1O0O_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO100l; + wire_nlOiO1l1i_dataout <= wire_nlOiO1O1i_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO11OO; + wire_nlOiO1l1l_dataout <= wire_nlOiO1O1l_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO101i; + wire_nlOiO1l1O_dataout <= wire_nlOiO1O1O_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO101l; + wire_nlOiO1li_dataout <= wire_nlOllOil_dataout AND NOT(niOO00l1l); + wire_nlOiO1lii_dataout <= wire_nlOiO1Oii_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO100O; + wire_nlOiO1lil_dataout <= wire_nlOiO1Oil_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO10ii; + wire_nlOiO1liO_dataout <= niOl1i11l WHEN nlOiO10Ol = '1' ELSE nlOiO10il; + wire_nlOiO1ll_dataout <= wire_nlOllOiO_dataout AND NOT(niOO00l1l); + wire_nlOiO1lli_dataout <= wire_nlOiO1Oli_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO10iO; + wire_nlOiO1lll_dataout <= wire_nlOiO1Oll_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO10li; + wire_nlOiO1llO_dataout <= wire_nlOiO1OlO_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO10ll; + wire_nlOiO1lO_dataout <= wire_nlOllOli_dataout AND NOT(niOO00l1l); + wire_nlOiO1lOi_dataout <= wire_nlOiO1OOi_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO10lO; + wire_nlOiO1lOl_dataout <= wire_nlOiO1OOl_dataout WHEN nlOiO10Ol = '1' ELSE nlOiO10Oi; + wire_nlOiO1O0i_dataout <= wire_nlOiO1OiO_o(3) AND NOT(niOl1i11i); + wire_nlOiO1O0l_dataout <= wire_nlOiO1OiO_o(4) AND NOT(niOl1i11i); + wire_nlOiO1O0O_dataout <= wire_nlOiO1OiO_o(5) AND NOT(niOl1i11i); + wire_nlOiO1O1i_dataout <= wire_nlOiO1OiO_o(0) AND NOT(niOl1i11i); + wire_nlOiO1O1l_dataout <= wire_nlOiO1OiO_o(1) AND NOT(niOl1i11i); + wire_nlOiO1O1O_dataout <= wire_nlOiO1OiO_o(2) AND NOT(niOl1i11i); + wire_nlOiO1Oi_dataout <= wire_nlOllOll_dataout AND NOT(niOO00l1l); + wire_nlOiO1Oii_dataout <= wire_nlOiO1OiO_o(6) AND NOT(niOl1i11i); + wire_nlOiO1Oil_dataout <= wire_nlOiO1OiO_o(7) AND NOT(niOl1i11i); + wire_nlOiO1Ol_dataout <= wire_nlOllOlO_dataout AND NOT(niOO00l1l); + wire_nlOiO1Oli_dataout <= wire_nlOiO1OOO_o(0) AND NOT(niOl1i11l); + wire_nlOiO1Oll_dataout <= wire_nlOiO1OOO_o(1) AND NOT(niOl1i11l); + wire_nlOiO1OlO_dataout <= wire_nlOiO1OOO_o(2) AND NOT(niOl1i11l); + wire_nlOiO1OO_dataout <= wire_nlOllOOi_dataout AND NOT(niOO00l1l); + wire_nlOiO1OOi_dataout <= wire_nlOiO1OOO_o(3) AND NOT(niOl1i11l); + wire_nlOiO1OOl_dataout <= wire_nlOiO1OOO_o(4) AND NOT(niOl1i11l); + wire_nlOiOi00i_dataout <= nlOiOl01O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0li_dataout; + wire_nlOiOi00l_dataout <= nlOiOl00i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0ll_dataout; + wire_nlOiOi00O_dataout <= nlOiOl00l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0lO_dataout; + wire_nlOiOi01i_dataout <= nlOiOl1OO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0ii_dataout; + wire_nlOiOi01l_dataout <= nlOiOl01i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0il_dataout; + wire_nlOiOi01O_dataout <= nlOiOl01l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0iO_dataout; + wire_nlOiOi0i_dataout <= wire_nlOlii0O_dataout AND NOT(niOO00l1l); + wire_nlOiOi0ii_dataout <= nlOiOl00O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0Oi_dataout; + wire_nlOiOi0il_dataout <= nlOiOl0ii WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0Ol_dataout; + wire_nlOiOi0iO_dataout <= nlOiOl0il WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i0OO_dataout; + wire_nlOiOi0l_dataout <= wire_nlOliiii_dataout AND NOT(niOO00l1l); + wire_nlOiOi0li_dataout <= nlOiOl0iO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ii1i_dataout; + wire_nlOiOi0ll_dataout <= nlOiOl0li WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ii1l_dataout; + wire_nlOiOi0lO_dataout <= nlOiOl0ll WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ii1O_dataout; + wire_nlOiOi0O_dataout <= wire_nlOliiil_dataout AND NOT(niOO00l1l); + wire_nlOiOi0Oi_dataout <= nlOiOl0lO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ii0i_dataout; + wire_nlOiOi0Ol_dataout <= nlOiOl0Oi WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ii0l_dataout; + wire_nlOiOi0OO_dataout <= nlOiOl0Ol WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ii0O_dataout; + wire_nlOiOi10i_dataout <= wire_nlOiOi1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOi10l_dataout <= (niOl1i10i AND nlOiO011i) AND NOT(wire_niO01lOO_dataout); + wire_nlOiOi11i_dataout <= wire_w_lg_niOl1i11O28120w(0) WHEN k_gbl_hip(23) = '1' ELSE ni0i1i0l; + wire_nlOiOi11i_w_lg_dataout36238w(0) <= NOT wire_nlOiOi11i_dataout; + wire_nlOiOi1i_dataout <= wire_nlOlii1O_dataout AND NOT(niOO00l1l); + wire_nlOiOi1iO_dataout <= wire_nlOiOi1li_dataout OR wire_nlOiOi1Oi_dataout; + wire_nlOiOi1l_dataout <= wire_nlOlii0i_dataout AND NOT(niOO00l1l); + wire_nlOiOi1li_dataout <= nlOiO011i AND NOT(niOl1i10i); + wire_nlOiOi1ll_dataout <= (wire_niO01ill_w_lg_nlOiOO1ll28114w(0) AND wire_nlOil11li_q(75)) WHEN k_gbl_hip(23) = '1' ELSE nlO1Oi10i; + wire_nlOiOi1ll_w_lg_w_lg_dataout18936w18937w(0) <= wire_nlOiOi1ll_w_lg_dataout18936w(0) AND n1llO1Ol; + wire_nlOiOi1ll_w_lg_dataout18936w(0) <= NOT wire_nlOiOi1ll_dataout; + wire_nlOiOi1O_dataout <= wire_nlOlii0l_dataout AND NOT(niOO00l1l); + wire_nlOiOi1Oi_dataout <= nlOiOi11O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l0OO_dataout; + wire_nlOiOi1Ol_dataout <= nlOiOl1Oi WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i00l_dataout; + wire_nlOiOi1OO_dataout <= nlOiOl1Ol WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1i00O_dataout; + wire_nlOiOii0i_dataout <= nlOiOli1O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iili_dataout; + wire_nlOiOii0l_dataout <= nlOiOli0i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iill_dataout; + wire_nlOiOii0O_dataout <= nlOiOli0l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iilO_dataout; + wire_nlOiOii1i_dataout <= nlOiOl0OO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iiii_dataout; + wire_nlOiOii1l_dataout <= nlOiOli1i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iiil_dataout; + wire_nlOiOii1O_dataout <= nlOiOli1l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iiiO_dataout; + wire_nlOiOiii_dataout <= wire_nlOliiiO_dataout AND NOT(niOO00l1l); + wire_nlOiOiiii_dataout <= nlOiOli0O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iiOi_dataout; + wire_nlOiOiiil_dataout <= nlOiOliii WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iiOl_dataout; + wire_nlOiOiiiO_dataout <= nlOiOliil WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iiOO_dataout; + wire_nlOiOiil_dataout <= wire_nlOliili_dataout AND NOT(niOO00l1l); + wire_nlOiOiili_dataout <= nlOiOliiO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1il1i_dataout; + wire_nlOiOiill_dataout <= nlOiOlili WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1il1l_dataout; + wire_nlOiOiilO_dataout <= nlOiOlill WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1il1O_dataout; + wire_nlOiOiiO_dataout <= wire_nlOliill_dataout AND NOT(niOO00l1l); + wire_nlOiOiiOi_dataout <= nlOiOlilO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1il0i_dataout; + wire_nlOiOiiOl_dataout <= nlOiOliOi WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1il0l_dataout; + wire_nlOiOiiOO_dataout <= nlOiOliOl WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1il0O_dataout; + wire_nlOiOil0i_dataout <= nlOiOll1O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1illi_dataout; + wire_nlOiOil0l_dataout <= nlOiOll0i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1illl_dataout; + wire_nlOiOil0O_dataout <= nlOiOll0l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1illO_dataout; + wire_nlOiOil1i_dataout <= nlOiOliOO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ilii_dataout; + wire_nlOiOil1l_dataout <= nlOiOll1i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ilil_dataout; + wire_nlOiOil1O_dataout <= nlOiOll1l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iliO_dataout; + wire_nlOiOili_dataout <= wire_nlOliilO_dataout AND NOT(niOO00l1l); + wire_nlOiOilii_dataout <= nlOiOll0O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ilOi_dataout; + wire_nlOiOilil_dataout <= nlOiOllii WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ilOl_dataout; + wire_nlOiOiliO_dataout <= nlOiOllil WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1ilOO_dataout; + wire_nlOiOill_dataout <= wire_nlOliiOi_dataout AND NOT(niOO00l1l); + wire_nlOiOilli_dataout <= nlOiOlliO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iO1i_dataout; + wire_nlOiOilll_dataout <= nlOiOllli WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iO1l_dataout; + wire_nlOiOillO_dataout <= nlOiOllll WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iO1O_dataout; + wire_nlOiOilO_dataout <= wire_nlOliiOl_dataout AND NOT(niOO00l1l); + wire_nlOiOilOi_dataout <= nlOiOlllO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iO0i_dataout; + wire_nlOiOilOl_dataout <= nlOiOllOi WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iO0l_dataout; + wire_nlOiOilOO_dataout <= nlOiOllOl WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iO0O_dataout; + wire_nlOiOiO0i_dataout <= nlOiOlO1O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOli_dataout; + wire_nlOiOiO0l_dataout <= nlOiOlO0i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOll_dataout; + wire_nlOiOiO0O_dataout <= nlOiOlO0l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOlO_dataout; + wire_nlOiOiO1i_dataout <= nlOiOllOO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOii_dataout; + wire_nlOiOiO1l_dataout <= nlOiOlO1i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOil_dataout; + wire_nlOiOiO1O_dataout <= nlOiOlO1l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOiO_dataout; + wire_nlOiOiOi_dataout <= wire_nlOliiOO_dataout AND NOT(niOO00l1l); + wire_nlOiOiOii_dataout <= nlOiOlO0O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOOi_dataout; + wire_nlOiOiOil_dataout <= nlOiOlOii WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOOl_dataout; + wire_nlOiOiOiO_dataout <= nlOiOlOil WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1iOOO_dataout; + wire_nlOiOiOl_dataout <= wire_nlOlil1i_dataout AND NOT(niOO00l1l); + wire_nlOiOiOli_dataout <= nlOiOlOiO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l11i_dataout; + wire_nlOiOiOll_dataout <= nlOiOlOli WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l11l_dataout; + wire_nlOiOiOlO_dataout <= nlOiOlOll WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l11O_dataout; + wire_nlOiOiOO_dataout <= wire_nlOlil1l_dataout AND NOT(niOO00l1l); + wire_nlOiOiOOi_dataout <= nlOiOlOlO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l10i_dataout; + wire_nlOiOiOOl_dataout <= nlOiOlOOi WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l10l_dataout; + wire_nlOiOiOOO_dataout <= nlOiOlOOl WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l10O_dataout; + wire_nlOiOl0i_dataout <= wire_nlOlil0O_dataout AND NOT(niOO00l1l); + wire_nlOiOl0l_dataout <= wire_nlOlilii_dataout AND NOT(niOO00l1l); + wire_nlOiOl0O_dataout <= wire_nlOlilil_dataout AND NOT(niOO00l1l); + wire_nlOiOl10i_dataout <= nlOiOO11O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1li_dataout; + wire_nlOiOl10l_dataout <= nlOiOO10i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1ll_dataout; + wire_nlOiOl10O_dataout <= nlOiOO10l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1lO_dataout; + wire_nlOiOl11i_dataout <= nlOiOlOOO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1ii_dataout; + wire_nlOiOl11l_dataout <= nlOiOO11i WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1il_dataout; + wire_nlOiOl11O_dataout <= nlOiOO11l WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1iO_dataout; + wire_nlOiOl1i_dataout <= wire_nlOlil1O_dataout AND NOT(niOO00l1l); + wire_nlOiOl1ii_dataout <= nlOiOO10O WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1Oi_dataout; + wire_nlOiOl1il_dataout <= nlOiOO1ii WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1Ol_dataout; + wire_nlOiOl1iO_dataout <= nlOiOO1il WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l1OO_dataout; + wire_nlOiOl1l_dataout <= wire_nlOlil0i_dataout AND NOT(niOO00l1l); + wire_nlOiOl1li_dataout <= nlOiOO1iO WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l01i_dataout; + wire_nlOiOl1ll_dataout <= nlOiOO1li WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l01l_dataout; + wire_nlOiOl1ll_w_lg_dataout18919w(0) <= NOT wire_nlOiOl1ll_dataout; + wire_nlOiOl1lO_dataout <= nlOiOO1ll WHEN k_gbl_hip(23) = '1' ELSE wire_nlOl1l01O_dataout; + wire_nlOiOl1lO_w_lg_dataout18765w(0) <= NOT wire_nlOiOl1lO_dataout; + wire_nlOiOl1O_dataout <= wire_nlOlil0l_dataout AND NOT(niOO00l1l); + wire_nlOiOlii_dataout <= wire_nlOliliO_dataout AND NOT(niOO00l1l); + wire_nlOiOlil_dataout <= wire_nlOlilli_dataout AND NOT(niOO00l1l); + wire_nlOiOliO_dataout <= wire_nlOlilll_dataout AND NOT(niOO00l1l); + wire_nlOiOlli_dataout <= wire_nlOlillO_dataout AND NOT(niOO00l1l); + wire_nlOiOlll_dataout <= wire_nlOlilOi_dataout AND NOT(niOO00l1l); + wire_nlOiOllO_dataout <= wire_nlOlilOl_dataout AND NOT(niOO00l1l); + wire_nlOiOlOi_dataout <= wire_nlOlilOO_dataout AND NOT(niOO00l1l); + wire_nlOiOlOl_dataout <= wire_nlOliO1i_dataout AND NOT(niOO00l1l); + wire_nlOiOlOO_dataout <= wire_nlOliO1l_dataout AND NOT(niOO00l1l); + wire_nlOiOO00i_dataout <= wire_nlOl1100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO00l_dataout <= wire_nlOl1100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO00O_dataout <= wire_nlOl1100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO01i_dataout <= wire_nlOl1101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO01l_dataout <= wire_nlOl1101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO01O_dataout <= wire_nlOl1101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0i_dataout <= wire_nlOliO0O_dataout AND NOT(niOO00l1l); + wire_nlOiOO0ii_dataout <= wire_nlOl110ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0il_dataout <= wire_nlOl110il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0iO_dataout <= wire_nlOl110iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0l_dataout <= wire_nlOliOii_dataout AND NOT(niOO00l1l); + wire_nlOiOO0li_dataout <= wire_nlOl110li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0ll_dataout <= wire_nlOl110ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0lO_dataout <= wire_nlOl110lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0O_dataout <= wire_nlOliOil_dataout AND NOT(niOO00l1l); + wire_nlOiOO0Oi_dataout <= wire_nlOl110Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0Ol_dataout <= wire_nlOl110Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO0OO_dataout <= wire_nlOl110OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO1i_dataout <= wire_nlOliO1O_dataout AND NOT(niOO00l1l); + wire_nlOiOO1l_dataout <= wire_nlOliO0i_dataout AND NOT(niOO00l1l); + wire_nlOiOO1O_dataout <= wire_nlOliO0l_dataout AND NOT(niOO00l1l); + wire_nlOiOO1Oi_dataout <= wire_nlOl111Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO1Ol_dataout <= wire_nlOl111Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOO1OO_dataout <= wire_nlOl111OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOi0i_dataout <= wire_nlOl11i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOi0l_dataout <= wire_nlOl11i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOi0O_dataout <= wire_nlOl11i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOi1i_dataout <= wire_nlOl11i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOi1l_dataout <= wire_nlOl11i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOi1O_dataout <= wire_nlOl11i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOii_dataout <= wire_nlOliOiO_dataout AND NOT(niOO00l1l); + wire_nlOiOOiii_dataout <= wire_nlOl11iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOiil_dataout <= wire_nlOl11iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOiiO_dataout <= wire_nlOl11iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOil_dataout <= wire_nlOliOli_dataout AND NOT(niOO00l1l); + wire_nlOiOOili_dataout <= wire_nlOl11ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOill_dataout <= wire_nlOl11ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOilO_dataout <= wire_nlOl11ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOiO_dataout <= wire_nlOliOll_dataout AND NOT(niOO00l1l); + wire_nlOiOOiOi_dataout <= wire_nlOl11iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOiOl_dataout <= wire_nlOl11iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOiOO_dataout <= wire_nlOl11iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOl0i_dataout <= wire_nlOl11l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOl0l_dataout <= wire_nlOl11l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOl0O_dataout <= wire_nlOl11l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOl1i_dataout <= wire_nlOl11l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOl1l_dataout <= wire_nlOl11l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOl1O_dataout <= wire_nlOl11l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOli_dataout <= wire_nlOliOlO_dataout AND NOT(niOO00l1l); + wire_nlOiOOlii_dataout <= wire_nlOl11lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOlil_dataout <= wire_nlOl11lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOliO_dataout <= wire_nlOl11liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOll_dataout <= wire_nlOliOOi_dataout AND NOT(niOO00l1l); + wire_nlOiOOlli_dataout <= wire_nlOl11lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOlll_dataout <= wire_nlOl11lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOllO_dataout <= wire_nlOl11llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOlO_dataout <= wire_nlOliOOl_dataout AND NOT(niOO00l1l); + wire_nlOiOOlOi_dataout <= wire_nlOl11lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOlOl_dataout <= wire_nlOl11lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOlOO_dataout <= wire_nlOl11lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOO0i_dataout <= wire_nlOl11O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOO0l_dataout <= wire_nlOl11O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOO0O_dataout <= wire_nlOl11O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOO1i_dataout <= wire_nlOl11O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOO1l_dataout <= wire_nlOl11O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOO1O_dataout <= wire_nlOl11O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOi_dataout <= wire_nlOliOOO_dataout AND NOT(niOO00l1l); + wire_nlOiOOOii_dataout <= wire_nlOl11Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOil_dataout <= wire_nlOl11Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOiO_dataout <= wire_nlOl11OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOl_dataout <= wire_nlOll11i_dataout AND NOT(niOO00l1l); + wire_nlOiOOOli_dataout <= wire_nlOl11Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOll_dataout <= wire_nlOl11Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOlO_dataout <= wire_nlOl11OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOO_dataout <= wire_nlOll11l_dataout AND NOT(niOO00l1l); + wire_nlOiOOOOi_dataout <= wire_nlOl11OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOOl_dataout <= wire_nlOl11OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOiOOOOO_dataout <= wire_nlOl11OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl000i_dataout <= wire_nlOO11Oi_dataout AND NOT(niOO00l1l); + wire_nlOl000l_dataout <= wire_nlOO11Ol_dataout AND NOT(niOO00l1l); + wire_nlOl000O_dataout <= wire_nlOO11OO_dataout AND NOT(niOO00l1l); + wire_nlOl001i_dataout <= wire_nlOO11li_dataout AND NOT(niOO00l1l); + wire_nlOl001l_dataout <= wire_nlOO11ll_dataout AND NOT(niOO00l1l); + wire_nlOl001O_dataout <= wire_nlOO11lO_dataout AND NOT(niOO00l1l); + wire_nlOl00ii_dataout <= wire_nlOO101i_dataout AND NOT(niOO00l1l); + wire_nlOl00il_dataout <= wire_nlOO101l_dataout AND NOT(niOO00l1l); + wire_nlOl00iO_dataout <= wire_nlOO101O_dataout AND NOT(niOO00l1l); + wire_nlOl00li_dataout <= wire_nlOO100i_dataout AND NOT(niOO00l1l); + wire_nlOl00ll_dataout <= wire_nlOO100l_dataout AND NOT(niOO00l1l); + wire_nlOl00lO_dataout <= wire_nlOO100O_dataout AND NOT(niOO00l1l); + wire_nlOl00Oi_dataout <= wire_nlOO10ii_dataout AND NOT(niOO00l1l); + wire_nlOl00Ol_dataout <= wire_nlOO10il_dataout AND NOT(niOO00l1l); + wire_nlOl00OO_dataout <= wire_nlOO10iO_dataout AND NOT(niOO00l1l); + wire_nlOl010i_dataout <= wire_nlOlOOOi_dataout AND NOT(niOO00l1l); + wire_nlOl010l_dataout <= wire_nlOlOOOl_dataout AND NOT(niOO00l1l); + wire_nlOl010O_dataout <= wire_nlOlOOOO_dataout AND NOT(niOO00l1l); + wire_nlOl011i_dataout <= wire_nlOlOOli_dataout AND NOT(niOO00l1l); + wire_nlOl011l_dataout <= wire_nlOlOOll_dataout AND NOT(niOO00l1l); + wire_nlOl011O_dataout <= wire_nlOlOOlO_dataout AND NOT(niOO00l1l); + wire_nlOl01ii_dataout <= wire_nlOO111i_dataout AND NOT(niOO00l1l); + wire_nlOl01il_dataout <= wire_nlOO111l_dataout AND NOT(niOO00l1l); + wire_nlOl01iO_dataout <= wire_nlOO111O_dataout AND NOT(niOO00l1l); + wire_nlOl01li_dataout <= wire_nlOO110i_dataout AND NOT(niOO00l1l); + wire_nlOl01ll_dataout <= wire_nlOO110l_dataout AND NOT(niOO00l1l); + wire_nlOl01lO_dataout <= wire_nlOO110O_dataout AND NOT(niOO00l1l); + wire_nlOl01Oi_dataout <= wire_nlOO11ii_dataout AND NOT(niOO00l1l); + wire_nlOl01Ol_dataout <= wire_nlOO11il_dataout AND NOT(niOO00l1l); + wire_nlOl01OO_dataout <= wire_nlOO11iO_dataout AND NOT(niOO00l1l); + wire_nlOl0i0i_dataout <= wire_nlOO10Oi_dataout AND NOT(niOO00l1l); + wire_nlOl0i0l_dataout <= wire_nlOO10Ol_dataout AND NOT(niOO00l1l); + wire_nlOl0i0O_dataout <= wire_nlOO10OO_dataout AND NOT(niOO00l1l); + wire_nlOl0i1i_dataout <= wire_nlOO10li_dataout AND NOT(niOO00l1l); + wire_nlOl0i1l_dataout <= wire_nlOO10ll_dataout AND NOT(niOO00l1l); + wire_nlOl0i1O_dataout <= wire_nlOO10lO_dataout AND NOT(niOO00l1l); + wire_nlOl0iii_dataout <= wire_nlOO1i1i_dataout AND NOT(niOO00l1l); + wire_nlOl0iil_dataout <= wire_nlOO1i1l_dataout AND NOT(niOO00l1l); + wire_nlOl0iiO_dataout <= wire_nlOO1i1O_dataout AND NOT(niOO00l1l); + wire_nlOl0ili_dataout <= wire_nlOO1i0i_dataout AND NOT(niOO00l1l); + wire_nlOl0ill_dataout <= wire_nlOO1i0l_dataout AND NOT(niOO00l1l); + wire_nlOl0ilO_dataout <= wire_nlOO1i0O_dataout AND NOT(niOO00l1l); + wire_nlOl0iOi_dataout <= wire_nlOO1iii_dataout AND NOT(niOO00l1l); + wire_nlOl0iOl_dataout <= wire_nlOO1iil_dataout AND NOT(niOO00l1l); + wire_nlOl0iOO_dataout <= wire_nlOO1iiO_dataout AND NOT(niOO00l1l); + wire_nlOl0l0i_dataout <= wire_nlOO1iOi_dataout AND NOT(niOO00l1l); + wire_nlOl0l0l_dataout <= wire_nlOO1iOl_dataout AND NOT(niOO00l1l); + wire_nlOl0l0O_dataout <= wire_nlOO1iOO_dataout AND NOT(niOO00l1l); + wire_nlOl0l1i_dataout <= wire_nlOO1ili_dataout AND NOT(niOO00l1l); + wire_nlOl0l1l_dataout <= wire_nlOO1ill_dataout AND NOT(niOO00l1l); + wire_nlOl0l1O_dataout <= wire_nlOO1ilO_dataout AND NOT(niOO00l1l); + wire_nlOl0lii_dataout <= wire_nlOO1l1i_dataout AND NOT(niOO00l1l); + wire_nlOl0lil_dataout <= wire_nlOO1l1l_dataout AND NOT(niOO00l1l); + wire_nlOl0liO_dataout <= wire_nlOO1l1O_dataout AND NOT(niOO00l1l); + wire_nlOl0lli_dataout <= wire_nlOO1l0i_dataout AND NOT(niOO00l1l); + wire_nlOl0lll_dataout <= wire_nlOO1l0l_dataout AND NOT(niOO00l1l); + wire_nlOl0llO_dataout <= wire_nlOO1l0O_dataout AND NOT(niOO00l1l); + wire_nlOl0lOi_dataout <= wire_nlOO1lii_dataout AND NOT(niOO00l1l); + wire_nlOl0lOl_dataout <= wire_nlOO1lil_dataout AND NOT(niOO00l1l); + wire_nlOl0lOO_dataout <= wire_nlOO1liO_dataout AND NOT(niOO00l1l); + wire_nlOl0O0i_dataout <= wire_nlOO1lOi_dataout AND NOT(niOO00l1l); + wire_nlOl0O0l_dataout <= wire_nlOO1lOl_dataout AND NOT(niOO00l1l); + wire_nlOl0O0O_dataout <= wire_nlOO1lOO_dataout AND NOT(niOO00l1l); + wire_nlOl0O1i_dataout <= wire_nlOO1lli_dataout AND NOT(niOO00l1l); + wire_nlOl0O1l_dataout <= wire_nlOO1lll_dataout AND NOT(niOO00l1l); + wire_nlOl0O1O_dataout <= wire_nlOO1llO_dataout AND NOT(niOO00l1l); + wire_nlOl0Oii_dataout <= wire_nlOO1O1i_dataout AND NOT(niOO00l1l); + wire_nlOl0Oil_dataout <= wire_nlOO1O1l_dataout AND NOT(niOO00l1l); + wire_nlOl0OiO_dataout <= wire_nlOO1O1O_dataout AND NOT(niOO00l1l); + wire_nlOl0Oli_dataout <= wire_nlOO1O0i_dataout AND NOT(niOO00l1l); + wire_nlOl0Oll_dataout <= wire_nlOO1O0l_dataout AND NOT(niOO00l1l); + wire_nlOl0OlO_dataout <= wire_nlOO1O0O_dataout AND NOT(niOO00l1l); + wire_nlOl0OOi_dataout <= nlOili0l AND NOT(niOO00l1l); + wire_nlOl0OOl_dataout <= wire_nlOli11O_dataout AND NOT(niOO00l1l); + wire_nlOl0OOO_dataout <= wire_nlOli11i_dataout AND NOT(niOO00l1l); + wire_nlOl1000i_dataout <= nlOiOl01O AND NOT(n1lO0lOl); + wire_nlOl1000l_dataout <= nlOiOl00i AND NOT(n1lO0lOl); + wire_nlOl1000O_dataout <= nlOiOl00l AND NOT(n1lO0lOl); + wire_nlOl1001i_dataout <= nlOiOl1OO AND NOT(n1lO0lOl); + wire_nlOl1001l_dataout <= nlOiOl01i AND NOT(n1lO0lOl); + wire_nlOl1001O_dataout <= nlOiOl01l AND NOT(n1lO0lOl); + wire_nlOl100i_dataout <= wire_nlOll00O_dataout AND NOT(niOO00l1l); + wire_nlOl100ii_dataout <= nlOiOl00O AND NOT(n1lO0lOl); + wire_nlOl100il_dataout <= nlOiOl0ii AND NOT(n1lO0lOl); + wire_nlOl100iO_dataout <= nlOiOl0il AND NOT(n1lO0lOl); + wire_nlOl100l_dataout <= wire_nlOlO1Ol_dataout AND NOT(niOO00l1l); + wire_nlOl100li_dataout <= nlOiOl0iO AND NOT(n1lO0lOl); + wire_nlOl100ll_dataout <= nlOiOl0li AND NOT(n1lO0lOl); + wire_nlOl100lO_dataout <= nlOiOl0ll AND NOT(n1lO0lOl); + wire_nlOl100O_dataout <= wire_nlOlO1OO_dataout AND NOT(niOO00l1l); + wire_nlOl100Oi_dataout <= nlOiOl0lO AND NOT(n1lO0lOl); + wire_nlOl100Ol_dataout <= nlOiOl0Oi AND NOT(n1lO0lOl); + wire_nlOl100OO_dataout <= nlOiOl0Ol AND NOT(n1lO0lOl); + wire_nlOl1010i_dataout <= wire_nlOil11li_q(65) WHEN niOl1i10l = '1' ELSE wire_nlOl1i10i_dataout; + wire_nlOl1010l_dataout <= wire_nlOil11li_q(66) WHEN niOl1i10l = '1' ELSE wire_nlOl1i10l_dataout; + wire_nlOl1010O_dataout <= wire_nlOil11li_q(67) WHEN niOl1i10l = '1' ELSE wire_nlOl1i10O_dataout; + wire_nlOl1011i_dataout <= wire_nlOil11li_q(62) WHEN niOl1i10l = '1' ELSE wire_nlOl1i11i_dataout; + wire_nlOl1011l_dataout <= wire_nlOil11li_q(63) WHEN niOl1i10l = '1' ELSE wire_nlOl1i11l_dataout; + wire_nlOl1011O_dataout <= wire_nlOil11li_q(64) WHEN niOl1i10l = '1' ELSE wire_nlOl1i11O_dataout; + wire_nlOl101i_dataout <= wire_nlOll01O_dataout AND NOT(niOO00l1l); + wire_nlOl101ii_dataout <= wire_nlOil11li_q(68) WHEN niOl1i10l = '1' ELSE wire_nlOl1i1ii_dataout; + wire_nlOl101il_dataout <= wire_nlOil11li_q(69) WHEN niOl1i10l = '1' ELSE wire_nlOl1i1il_dataout; + wire_nlOl101iO_dataout <= wire_nlOil11li_q(70) WHEN niOl1i10l = '1' ELSE wire_nlOl1i1iO_dataout; + wire_nlOl101l_dataout <= wire_nlOll00i_dataout AND NOT(niOO00l1l); + wire_nlOl101li_dataout <= wire_nlOil11li_q(71) WHEN niOl1i10l = '1' ELSE wire_nlOl1i1li_dataout; + wire_nlOl101ll_dataout <= wire_nlOil11li_q(72) WHEN niOl1i10l = '1' ELSE wire_nlOl1i1ll_dataout; + wire_nlOl101lO_dataout <= wire_nlOil11li_q(73) WHEN niOl1i10l = '1' ELSE wire_nlOl1i1lO_dataout; + wire_nlOl101O_dataout <= wire_nlOll00l_dataout AND NOT(niOO00l1l); + wire_nlOl101Oi_dataout <= nlOiOi11O AND NOT(n1lO0lOl); + wire_nlOl101Ol_dataout <= nlOiOl1Oi AND NOT(n1lO0lOl); + wire_nlOl101OO_dataout <= nlOiOl1Ol AND NOT(n1lO0lOl); + wire_nlOl10i0i_dataout <= nlOiOli1O AND NOT(n1lO0lOl); + wire_nlOl10i0l_dataout <= nlOiOli0i AND NOT(n1lO0lOl); + wire_nlOl10i0O_dataout <= nlOiOli0l AND NOT(n1lO0lOl); + wire_nlOl10i1i_dataout <= nlOiOl0OO AND NOT(n1lO0lOl); + wire_nlOl10i1l_dataout <= nlOiOli1i AND NOT(n1lO0lOl); + wire_nlOl10i1O_dataout <= nlOiOli1l AND NOT(n1lO0lOl); + wire_nlOl10ii_dataout <= wire_nlOlO01i_dataout AND NOT(niOO00l1l); + wire_nlOl10iii_dataout <= nlOiOli0O AND NOT(n1lO0lOl); + wire_nlOl10iil_dataout <= nlOiOliii AND NOT(n1lO0lOl); + wire_nlOl10iiO_dataout <= nlOiOliil AND NOT(n1lO0lOl); + wire_nlOl10il_dataout <= wire_nlOlO01l_dataout AND NOT(niOO00l1l); + wire_nlOl10ili_dataout <= nlOiOliiO AND NOT(n1lO0lOl); + wire_nlOl10ill_dataout <= nlOiOlili AND NOT(n1lO0lOl); + wire_nlOl10ilO_dataout <= nlOiOlill AND NOT(n1lO0lOl); + wire_nlOl10iO_dataout <= wire_nlOlO01O_dataout AND NOT(niOO00l1l); + wire_nlOl10iOi_dataout <= nlOiOlilO AND NOT(n1lO0lOl); + wire_nlOl10iOl_dataout <= nlOiOliOi AND NOT(n1lO0lOl); + wire_nlOl10iOO_dataout <= nlOiOliOl AND NOT(n1lO0lOl); + wire_nlOl10l0i_dataout <= nlOiOll1O AND NOT(n1lO0lOl); + wire_nlOl10l0l_dataout <= nlOiOll0i AND NOT(n1lO0lOl); + wire_nlOl10l0O_dataout <= nlOiOll0l AND NOT(n1lO0lOl); + wire_nlOl10l1i_dataout <= nlOiOliOO AND NOT(n1lO0lOl); + wire_nlOl10l1l_dataout <= nlOiOll1i AND NOT(n1lO0lOl); + wire_nlOl10l1O_dataout <= nlOiOll1l AND NOT(n1lO0lOl); + wire_nlOl10li_dataout <= wire_nlOlO00i_dataout AND NOT(niOO00l1l); + wire_nlOl10lii_dataout <= nlOiOll0O AND NOT(n1lO0lOl); + wire_nlOl10lil_dataout <= nlOiOllii AND NOT(n1lO0lOl); + wire_nlOl10liO_dataout <= nlOiOllil AND NOT(n1lO0lOl); + wire_nlOl10ll_dataout <= wire_nlOlO00l_dataout AND NOT(niOO00l1l); + wire_nlOl10lli_dataout <= nlOiOlliO AND NOT(n1lO0lOl); + wire_nlOl10lll_dataout <= nlOiOllli AND NOT(n1lO0lOl); + wire_nlOl10llO_dataout <= nlOiOllll AND NOT(n1lO0lOl); + wire_nlOl10lO_dataout <= wire_nlOlO00O_dataout AND NOT(niOO00l1l); + wire_nlOl10lOi_dataout <= nlOiOlllO AND NOT(n1lO0lOl); + wire_nlOl10lOl_dataout <= nlOiOllOi AND NOT(n1lO0lOl); + wire_nlOl10lOO_dataout <= nlOiOllOl AND NOT(n1lO0lOl); + wire_nlOl10O0i_dataout <= nlOiOlO1O AND NOT(n1lO0lOl); + wire_nlOl10O0l_dataout <= nlOiOlO0i AND NOT(n1lO0lOl); + wire_nlOl10O0O_dataout <= nlOiOlO0l AND NOT(n1lO0lOl); + wire_nlOl10O1i_dataout <= nlOiOllOO AND NOT(n1lO0lOl); + wire_nlOl10O1l_dataout <= nlOiOlO1i AND NOT(n1lO0lOl); + wire_nlOl10O1O_dataout <= nlOiOlO1l AND NOT(n1lO0lOl); + wire_nlOl10Oi_dataout <= wire_nlOlO0ii_dataout AND NOT(niOO00l1l); + wire_nlOl10Oii_dataout <= nlOiOlO0O AND NOT(n1lO0lOl); + wire_nlOl10Oil_dataout <= nlOiOlOii AND NOT(n1lO0lOl); + wire_nlOl10OiO_dataout <= nlOiOlOil AND NOT(n1lO0lOl); + wire_nlOl10Ol_dataout <= wire_nlOlO0il_dataout AND NOT(niOO00l1l); + wire_nlOl10Oli_dataout <= nlOiOlOiO AND NOT(n1lO0lOl); + wire_nlOl10Oll_dataout <= nlOiOlOli AND NOT(n1lO0lOl); + wire_nlOl10OlO_dataout <= nlOiOlOll AND NOT(n1lO0lOl); + wire_nlOl10OO_dataout <= wire_nlOlO0iO_dataout AND NOT(niOO00l1l); + wire_nlOl10OOi_dataout <= nlOiOlOlO AND NOT(n1lO0lOl); + wire_nlOl10OOl_dataout <= nlOiOlOOi AND NOT(n1lO0lOl); + wire_nlOl10OOO_dataout <= nlOiOlOOl AND NOT(n1lO0lOl); + wire_nlOl1100i_dataout <= wire_nlOil11li_q(5) WHEN niOl1i10l = '1' ELSE wire_nlOl1000i_dataout; + wire_nlOl1100l_dataout <= wire_nlOil11li_q(6) WHEN niOl1i10l = '1' ELSE wire_nlOl1000l_dataout; + wire_nlOl1100O_dataout <= wire_nlOil11li_q(7) WHEN niOl1i10l = '1' ELSE wire_nlOl1000O_dataout; + wire_nlOl1101i_dataout <= wire_nlOil11li_q(2) WHEN niOl1i10l = '1' ELSE wire_nlOl1001i_dataout; + wire_nlOl1101l_dataout <= wire_nlOil11li_q(3) WHEN niOl1i10l = '1' ELSE wire_nlOl1001l_dataout; + wire_nlOl1101O_dataout <= wire_nlOil11li_q(4) WHEN niOl1i10l = '1' ELSE wire_nlOl1001O_dataout; + wire_nlOl110i_dataout <= wire_nlOll10O_dataout AND NOT(niOO00l1l); + wire_nlOl110ii_dataout <= wire_nlOil11li_q(8) WHEN niOl1i10l = '1' ELSE wire_nlOl100ii_dataout; + wire_nlOl110il_dataout <= wire_nlOil11li_q(9) WHEN niOl1i10l = '1' ELSE wire_nlOl100il_dataout; + wire_nlOl110iO_dataout <= wire_nlOil11li_q(10) WHEN niOl1i10l = '1' ELSE wire_nlOl100iO_dataout; + wire_nlOl110l_dataout <= wire_nlOll1ii_dataout AND NOT(niOO00l1l); + wire_nlOl110li_dataout <= wire_nlOil11li_q(11) WHEN niOl1i10l = '1' ELSE wire_nlOl100li_dataout; + wire_nlOl110ll_dataout <= wire_nlOil11li_q(12) WHEN niOl1i10l = '1' ELSE wire_nlOl100ll_dataout; + wire_nlOl110lO_dataout <= wire_nlOil11li_q(13) WHEN niOl1i10l = '1' ELSE wire_nlOl100lO_dataout; + wire_nlOl110O_dataout <= wire_nlOll1il_dataout AND NOT(niOO00l1l); + wire_nlOl110Oi_dataout <= wire_nlOil11li_q(14) WHEN niOl1i10l = '1' ELSE wire_nlOl100Oi_dataout; + wire_nlOl110Ol_dataout <= wire_nlOil11li_q(15) WHEN niOl1i10l = '1' ELSE wire_nlOl100Ol_dataout; + wire_nlOl110OO_dataout <= wire_nlOil11li_q(16) WHEN niOl1i10l = '1' ELSE wire_nlOl100OO_dataout; + wire_nlOl1110i_dataout <= wire_nlOl1010i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl1110l_dataout <= wire_nlOl1010l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl1110O_dataout <= wire_nlOl1010O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl1111i_dataout <= wire_nlOl1011i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl1111l_dataout <= wire_nlOl1011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl1111O_dataout <= wire_nlOl1011O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl111i_dataout <= wire_nlOll11O_dataout AND NOT(niOO00l1l); + wire_nlOl111ii_dataout <= wire_nlOl101ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl111il_dataout <= wire_nlOl101il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl111iO_dataout <= wire_nlOl101iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl111l_dataout <= wire_nlOll10i_dataout AND NOT(niOO00l1l); + wire_nlOl111li_dataout <= wire_nlOl101li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl111ll_dataout <= wire_nlOl101ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl111lO_dataout <= wire_nlOl101lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOl111O_dataout <= wire_nlOll10l_dataout AND NOT(niOO00l1l); + wire_nlOl111Oi_dataout <= wire_nlOil11li_q(74) WHEN niOl1i10l = '1' ELSE wire_nlOl101Oi_dataout; + wire_nlOl111Ol_dataout <= wire_nlOil11li_q(0) WHEN niOl1i10l = '1' ELSE wire_nlOl101Ol_dataout; + wire_nlOl111OO_dataout <= wire_nlOil11li_q(1) WHEN niOl1i10l = '1' ELSE wire_nlOl101OO_dataout; + wire_nlOl11i0i_dataout <= wire_nlOil11li_q(20) WHEN niOl1i10l = '1' ELSE wire_nlOl10i0i_dataout; + wire_nlOl11i0l_dataout <= wire_nlOil11li_q(21) WHEN niOl1i10l = '1' ELSE wire_nlOl10i0l_dataout; + wire_nlOl11i0O_dataout <= wire_nlOil11li_q(22) WHEN niOl1i10l = '1' ELSE wire_nlOl10i0O_dataout; + wire_nlOl11i1i_dataout <= wire_nlOil11li_q(17) WHEN niOl1i10l = '1' ELSE wire_nlOl10i1i_dataout; + wire_nlOl11i1l_dataout <= wire_nlOil11li_q(18) WHEN niOl1i10l = '1' ELSE wire_nlOl10i1l_dataout; + wire_nlOl11i1O_dataout <= wire_nlOil11li_q(19) WHEN niOl1i10l = '1' ELSE wire_nlOl10i1O_dataout; + wire_nlOl11ii_dataout <= wire_nlOll1iO_dataout AND NOT(niOO00l1l); + wire_nlOl11iii_dataout <= wire_nlOil11li_q(23) WHEN niOl1i10l = '1' ELSE wire_nlOl10iii_dataout; + wire_nlOl11iil_dataout <= wire_nlOil11li_q(24) WHEN niOl1i10l = '1' ELSE wire_nlOl10iil_dataout; + wire_nlOl11iiO_dataout <= wire_nlOil11li_q(25) WHEN niOl1i10l = '1' ELSE wire_nlOl10iiO_dataout; + wire_nlOl11il_dataout <= wire_nlOll1li_dataout AND NOT(niOO00l1l); + wire_nlOl11ili_dataout <= wire_nlOil11li_q(26) WHEN niOl1i10l = '1' ELSE wire_nlOl10ili_dataout; + wire_nlOl11ill_dataout <= wire_nlOil11li_q(27) WHEN niOl1i10l = '1' ELSE wire_nlOl10ill_dataout; + wire_nlOl11ilO_dataout <= wire_nlOil11li_q(28) WHEN niOl1i10l = '1' ELSE wire_nlOl10ilO_dataout; + wire_nlOl11iO_dataout <= wire_nlOll1ll_dataout AND NOT(niOO00l1l); + wire_nlOl11iOi_dataout <= wire_nlOil11li_q(29) WHEN niOl1i10l = '1' ELSE wire_nlOl10iOi_dataout; + wire_nlOl11iOl_dataout <= wire_nlOil11li_q(30) WHEN niOl1i10l = '1' ELSE wire_nlOl10iOl_dataout; + wire_nlOl11iOO_dataout <= wire_nlOil11li_q(31) WHEN niOl1i10l = '1' ELSE wire_nlOl10iOO_dataout; + wire_nlOl11l0i_dataout <= wire_nlOil11li_q(35) WHEN niOl1i10l = '1' ELSE wire_nlOl10l0i_dataout; + wire_nlOl11l0l_dataout <= wire_nlOil11li_q(36) WHEN niOl1i10l = '1' ELSE wire_nlOl10l0l_dataout; + wire_nlOl11l0O_dataout <= wire_nlOil11li_q(37) WHEN niOl1i10l = '1' ELSE wire_nlOl10l0O_dataout; + wire_nlOl11l1i_dataout <= wire_nlOil11li_q(32) WHEN niOl1i10l = '1' ELSE wire_nlOl10l1i_dataout; + wire_nlOl11l1l_dataout <= wire_nlOil11li_q(33) WHEN niOl1i10l = '1' ELSE wire_nlOl10l1l_dataout; + wire_nlOl11l1O_dataout <= wire_nlOil11li_q(34) WHEN niOl1i10l = '1' ELSE wire_nlOl10l1O_dataout; + wire_nlOl11li_dataout <= wire_nlOll1lO_dataout AND NOT(niOO00l1l); + wire_nlOl11lii_dataout <= wire_nlOil11li_q(38) WHEN niOl1i10l = '1' ELSE wire_nlOl10lii_dataout; + wire_nlOl11lil_dataout <= wire_nlOil11li_q(39) WHEN niOl1i10l = '1' ELSE wire_nlOl10lil_dataout; + wire_nlOl11liO_dataout <= wire_nlOil11li_q(40) WHEN niOl1i10l = '1' ELSE wire_nlOl10liO_dataout; + wire_nlOl11ll_dataout <= wire_nlOll1Oi_dataout AND NOT(niOO00l1l); + wire_nlOl11lli_dataout <= wire_nlOil11li_q(41) WHEN niOl1i10l = '1' ELSE wire_nlOl10lli_dataout; + wire_nlOl11lll_dataout <= wire_nlOil11li_q(42) WHEN niOl1i10l = '1' ELSE wire_nlOl10lll_dataout; + wire_nlOl11llO_dataout <= wire_nlOil11li_q(43) WHEN niOl1i10l = '1' ELSE wire_nlOl10llO_dataout; + wire_nlOl11lO_dataout <= wire_nlOll1Ol_dataout AND NOT(niOO00l1l); + wire_nlOl11lOi_dataout <= wire_nlOil11li_q(44) WHEN niOl1i10l = '1' ELSE wire_nlOl10lOi_dataout; + wire_nlOl11lOl_dataout <= wire_nlOil11li_q(45) WHEN niOl1i10l = '1' ELSE wire_nlOl10lOl_dataout; + wire_nlOl11lOO_dataout <= wire_nlOil11li_q(46) WHEN niOl1i10l = '1' ELSE wire_nlOl10lOO_dataout; + wire_nlOl11O0i_dataout <= wire_nlOil11li_q(50) WHEN niOl1i10l = '1' ELSE wire_nlOl10O0i_dataout; + wire_nlOl11O0l_dataout <= wire_nlOil11li_q(51) WHEN niOl1i10l = '1' ELSE wire_nlOl10O0l_dataout; + wire_nlOl11O0O_dataout <= wire_nlOil11li_q(52) WHEN niOl1i10l = '1' ELSE wire_nlOl10O0O_dataout; + wire_nlOl11O1i_dataout <= wire_nlOil11li_q(47) WHEN niOl1i10l = '1' ELSE wire_nlOl10O1i_dataout; + wire_nlOl11O1l_dataout <= wire_nlOil11li_q(48) WHEN niOl1i10l = '1' ELSE wire_nlOl10O1l_dataout; + wire_nlOl11O1O_dataout <= wire_nlOil11li_q(49) WHEN niOl1i10l = '1' ELSE wire_nlOl10O1O_dataout; + wire_nlOl11Oi_dataout <= wire_nlOll1OO_dataout AND NOT(niOO00l1l); + wire_nlOl11Oii_dataout <= wire_nlOil11li_q(53) WHEN niOl1i10l = '1' ELSE wire_nlOl10Oii_dataout; + wire_nlOl11Oil_dataout <= wire_nlOil11li_q(54) WHEN niOl1i10l = '1' ELSE wire_nlOl10Oil_dataout; + wire_nlOl11OiO_dataout <= wire_nlOil11li_q(55) WHEN niOl1i10l = '1' ELSE wire_nlOl10OiO_dataout; + wire_nlOl11Ol_dataout <= wire_nlOll01i_dataout AND NOT(niOO00l1l); + wire_nlOl11Oli_dataout <= wire_nlOil11li_q(56) WHEN niOl1i10l = '1' ELSE wire_nlOl10Oli_dataout; + wire_nlOl11Oll_dataout <= wire_nlOil11li_q(57) WHEN niOl1i10l = '1' ELSE wire_nlOl10Oll_dataout; + wire_nlOl11OlO_dataout <= wire_nlOil11li_q(58) WHEN niOl1i10l = '1' ELSE wire_nlOl10OlO_dataout; + wire_nlOl11OO_dataout <= wire_nlOll01l_dataout AND NOT(niOO00l1l); + wire_nlOl11OOi_dataout <= wire_nlOil11li_q(59) WHEN niOl1i10l = '1' ELSE wire_nlOl10OOi_dataout; + wire_nlOl11OOl_dataout <= wire_nlOil11li_q(60) WHEN niOl1i10l = '1' ELSE wire_nlOl10OOl_dataout; + wire_nlOl11OOO_dataout <= wire_nlOil11li_q(61) WHEN niOl1i10l = '1' ELSE wire_nlOl10OOO_dataout; + wire_nlOl1i00i_dataout <= niOl1i1ii WHEN n1lO0lOl = '1' ELSE nlOiOO1lO; + wire_nlOl1i00l_dataout <= nlO1Oi00O AND niOl1i1il; + wire_nlOl1i00O_dataout <= nlO1Oi0ii AND niOl1i1il; + wire_nlOl1i01O_dataout <= wire_nlOl1i00i_dataout OR wire_niO01lOO_dataout; + wire_nlOl1i0i_dataout <= wire_nlOlO0Oi_dataout AND NOT(niOO00l1l); + wire_nlOl1i0ii_dataout <= nlO1Oi0il AND niOl1i1il; + wire_nlOl1i0il_dataout <= nlO1Oi0iO AND niOl1i1il; + wire_nlOl1i0iO_dataout <= nlO1Oi0li AND niOl1i1il; + wire_nlOl1i0l_dataout <= wire_nlOlO0Ol_dataout AND NOT(niOO00l1l); + wire_nlOl1i0li_dataout <= nlO1Oi0ll AND niOl1i1il; + wire_nlOl1i0ll_dataout <= nlO1Oi0lO AND niOl1i1il; + wire_nlOl1i0lO_dataout <= nlO1Oi0Oi AND niOl1i1il; + wire_nlOl1i0O_dataout <= wire_nlOlO0OO_dataout AND NOT(niOO00l1l); + wire_nlOl1i0Oi_dataout <= nlO1Oi0Ol AND niOl1i1il; + wire_nlOl1i0Ol_dataout <= nlO1Oi0OO AND niOl1i1il; + wire_nlOl1i0OO_dataout <= nlO1Oii1i AND niOl1i1il; + wire_nlOl1i10i_dataout <= nlOiOO11O AND NOT(n1lO0lOl); + wire_nlOl1i10l_dataout <= nlOiOO10i AND NOT(n1lO0lOl); + wire_nlOl1i10O_dataout <= nlOiOO10l AND NOT(n1lO0lOl); + wire_nlOl1i11i_dataout <= nlOiOlOOO AND NOT(n1lO0lOl); + wire_nlOl1i11l_dataout <= nlOiOO11i AND NOT(n1lO0lOl); + wire_nlOl1i11O_dataout <= nlOiOO11l AND NOT(n1lO0lOl); + wire_nlOl1i1i_dataout <= wire_nlOlO0li_dataout AND NOT(niOO00l1l); + wire_nlOl1i1ii_dataout <= nlOiOO10O AND NOT(n1lO0lOl); + wire_nlOl1i1il_dataout <= nlOiOO1ii AND NOT(n1lO0lOl); + wire_nlOl1i1iO_dataout <= nlOiOO1il AND NOT(n1lO0lOl); + wire_nlOl1i1l_dataout <= wire_nlOlO0ll_dataout AND NOT(niOO00l1l); + wire_nlOl1i1li_dataout <= nlOiOO1iO AND NOT(n1lO0lOl); + wire_nlOl1i1ll_dataout <= nlOiOO1li AND NOT(n1lO0lOl); + wire_nlOl1i1lO_dataout <= nlOiOO1ll AND NOT(n1lO0lOl); + wire_nlOl1i1O_dataout <= wire_nlOlO0lO_dataout AND NOT(niOO00l1l); + wire_nlOl1i1Ol_dataout <= nlO1Oi10i AND nlOl1li0l; + wire_nlOl1ii0i_dataout <= nlO1Oii0l AND niOl1i1il; + wire_nlOl1ii0l_dataout <= nlO1Oii0O AND niOl1i1il; + wire_nlOl1ii0O_dataout <= nlO1Oiiii AND niOl1i1il; + wire_nlOl1ii1i_dataout <= nlO1Oii1l AND niOl1i1il; + wire_nlOl1ii1l_dataout <= nlO1Oii1O AND niOl1i1il; + wire_nlOl1ii1O_dataout <= nlO1Oii0i AND niOl1i1il; + wire_nlOl1iii_dataout <= wire_nlOlOi1i_dataout AND NOT(niOO00l1l); + wire_nlOl1iiii_dataout <= nlO1Oiiil AND niOl1i1il; + wire_nlOl1iiil_dataout <= nlO1OiiiO AND niOl1i1il; + wire_nlOl1iiiO_dataout <= nlO1Oiili AND niOl1i1il; + wire_nlOl1iil_dataout <= wire_nlOlOi1l_dataout AND NOT(niOO00l1l); + wire_nlOl1iili_dataout <= nlO1Oiill AND niOl1i1il; + wire_nlOl1iill_dataout <= nlO1OiilO AND niOl1i1il; + wire_nlOl1iilO_dataout <= nlO1OiiOi AND niOl1i1il; + wire_nlOl1iiO_dataout <= wire_nlOlOi1O_dataout AND NOT(niOO00l1l); + wire_nlOl1iiOi_dataout <= nlO1OiiOl AND niOl1i1il; + wire_nlOl1iiOl_dataout <= nlO1OiiOO AND niOl1i1il; + wire_nlOl1iiOO_dataout <= nlO1Oil1i AND niOl1i1il; + wire_nlOl1il0i_dataout <= nlO1Oil0l AND niOl1i1il; + wire_nlOl1il0l_dataout <= nlO1Oil0O AND niOl1i1il; + wire_nlOl1il0O_dataout <= nlO1Oilii AND niOl1i1il; + wire_nlOl1il1i_dataout <= nlO1Oil1l AND niOl1i1il; + wire_nlOl1il1l_dataout <= nlO1Oil1O AND niOl1i1il; + wire_nlOl1il1O_dataout <= nlO1Oil0i AND niOl1i1il; + wire_nlOl1ili_dataout <= wire_nlOlOi0i_dataout AND NOT(niOO00l1l); + wire_nlOl1ilii_dataout <= nlO1Oilil AND niOl1i1il; + wire_nlOl1ilil_dataout <= nlO1OiliO AND niOl1i1il; + wire_nlOl1iliO_dataout <= nlO1Oilli AND niOl1i1il; + wire_nlOl1ill_dataout <= wire_nlOlOi0l_dataout AND NOT(niOO00l1l); + wire_nlOl1illi_dataout <= nlO1Oilll AND niOl1i1il; + wire_nlOl1illl_dataout <= nlO1OillO AND niOl1i1il; + wire_nlOl1illO_dataout <= nlO1OilOi AND niOl1i1il; + wire_nlOl1ilO_dataout <= wire_nlOlOi0O_dataout AND NOT(niOO00l1l); + wire_nlOl1ilOi_dataout <= nlO1OilOl AND niOl1i1il; + wire_nlOl1ilOl_dataout <= nlO1OilOO AND niOl1i1il; + wire_nlOl1ilOO_dataout <= nlO1OiO1i AND niOl1i1il; + wire_nlOl1iO0i_dataout <= nlO1OiO0l AND niOl1i1il; + wire_nlOl1iO0l_dataout <= nlO1OiO0O AND niOl1i1il; + wire_nlOl1iO0O_dataout <= nlO1OiOii AND niOl1i1il; + wire_nlOl1iO1i_dataout <= nlO1OiO1l AND niOl1i1il; + wire_nlOl1iO1l_dataout <= nlO1OiO1O AND niOl1i1il; + wire_nlOl1iO1O_dataout <= nlO1OiO0i AND niOl1i1il; + wire_nlOl1iOi_dataout <= wire_nlOlOiii_dataout AND NOT(niOO00l1l); + wire_nlOl1iOii_dataout <= nlO1OiOil AND niOl1i1il; + wire_nlOl1iOil_dataout <= nlO1OiOiO AND niOl1i1il; + wire_nlOl1iOiO_dataout <= nlO1OiOli AND niOl1i1il; + wire_nlOl1iOl_dataout <= wire_nlOlOiil_dataout AND NOT(niOO00l1l); + wire_nlOl1iOli_dataout <= nlO1OiOll AND niOl1i1il; + wire_nlOl1iOll_dataout <= nlO1OiOlO AND niOl1i1il; + wire_nlOl1iOlO_dataout <= nlO1OiOOi AND niOl1i1il; + wire_nlOl1iOO_dataout <= wire_nlOlOiiO_dataout AND NOT(niOO00l1l); + wire_nlOl1iOOi_dataout <= nlO1OiOOl AND niOl1i1il; + wire_nlOl1iOOl_dataout <= nlO1OiOOO AND niOl1i1il; + wire_nlOl1iOOO_dataout <= nlO1Ol11i AND niOl1i1il; + wire_nlOl1l01i_dataout <= nlO1Oi00l AND niOl1i1il; + wire_nlOl1l01l_dataout <= nlO1Oi1lO AND niOl1i1il; + wire_nlOl1l01O_dataout <= nlO1Oi1ll AND niOl1i1il; + wire_nlOl1l0i_dataout <= wire_nlOlOiOi_dataout AND NOT(niOO00l1l); + wire_nlOl1l0il_dataout <= ((NOT k_gbl_hip(24)) AND wire_w_lg_w_k_gbl_hip_range28022w28025w(0)) OR wire_w_lg_w_k_gbl_hip_range28020w28029w(0); + wire_nlOl1l0l_dataout <= wire_nlOlOiOl_dataout AND NOT(niOO00l1l); + wire_nlOl1l0O_dataout <= wire_nlOlOiOO_dataout AND NOT(niOO00l1l); + wire_nlOl1l0Ol_dataout <= nlOl1li0l WHEN k_gbl_hip(23) = '1' ELSE n1lO0lOl; + wire_nlOl1l0Ol_w_lg_dataout4337w(0) <= wire_nlOl1l0Ol_dataout AND wire_nl11llO_w_lg_nlO0lllO4336w(0); + wire_nlOl1l0Ol_w_lg_dataout4348w(0) <= NOT wire_nlOl1l0Ol_dataout; + wire_nlOl1l0OO_dataout <= nlO1O0O0i WHEN (NOT k_gbl_hip(23)) = '1' ELSE wire_nlOl1li1i_dataout; + wire_nlOl1l0OO_w_lg_dataout28027w(0) <= wire_nlOl1l0OO_dataout OR niOl1i1iO; + wire_nlOl1l10i_dataout <= nlO1Ol10l AND niOl1i1il; + wire_nlOl1l10l_dataout <= nlO1Ol10O AND niOl1i1il; + wire_nlOl1l10O_dataout <= nlO1Ol1ii AND niOl1i1il; + wire_nlOl1l11i_dataout <= nlO1Ol11l AND niOl1i1il; + wire_nlOl1l11l_dataout <= nlO1Ol11O AND niOl1i1il; + wire_nlOl1l11O_dataout <= nlO1Ol10i AND niOl1i1il; + wire_nlOl1l1i_dataout <= wire_nlOlOili_dataout AND NOT(niOO00l1l); + wire_nlOl1l1ii_dataout <= nlO1Ol1il AND niOl1i1il; + wire_nlOl1l1il_dataout <= nlO1Ol1iO AND niOl1i1il; + wire_nlOl1l1iO_dataout <= nlO1Oi1Oi AND niOl1i1il; + wire_nlOl1l1l_dataout <= wire_nlOlOill_dataout AND NOT(niOO00l1l); + wire_nlOl1l1li_dataout <= nlO1Oi1Ol AND niOl1i1il; + wire_nlOl1l1ll_dataout <= nlO1Oi1OO AND niOl1i1il; + wire_nlOl1l1lO_dataout <= nlO1Oi01i AND niOl1i1il; + wire_nlOl1l1O_dataout <= wire_nlOlOilO_dataout AND NOT(niOO00l1l); + wire_nlOl1l1Oi_dataout <= nlO1Oi01l AND niOl1i1il; + wire_nlOl1l1Ol_dataout <= nlO1Oi01O AND niOl1i1il; + wire_nlOl1l1OO_dataout <= nlO1Oi00i AND niOl1i1il; + wire_nlOl1li0O_dataout <= wire_nlOl1liiO_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOl1li1i_dataout <= nlOl1i01l WHEN (k_gbl_hip(24) AND niOl1i1iO) = '1' ELSE wire_nlOl1li1l_dataout; + wire_nlOl1li1l_dataout <= nlOl1i01l AND nlOl1li0l; + wire_nlOl1lii_dataout <= wire_nlOlOl1i_dataout AND NOT(niOO00l1l); + wire_nlOl1liii_dataout <= wire_nlOl1lill_dataout AND NOT(wire_niO01O0O_dataout); + wire_nlOl1liil_dataout <= (wire_nlOl1ll1l_o AND wire_nl1000i_w_lg_nlOil1O1O28018w(0)) AND NOT(wire_niO01O0O_dataout); + wire_nlOl1liiO_dataout <= wire_nlOl1lili_dataout OR nlO1O0O0i; + wire_nlOl1lil_dataout <= wire_nlOlOl1l_dataout AND NOT(niOO00l1l); + wire_nlOl1lili_dataout <= nlOl1i01l AND NOT(wire_nlOl1l0OO_dataout); + wire_nlOl1lill_dataout <= wire_nlOl1lilO_dataout OR (wire_nl1000i_w_lg_nlO1Oi1ll28015w(0) AND (nlO1Oi1lO AND nlOl1li0l)); + wire_nlOl1lilO_dataout <= nlOl1li0i AND NOT((nlO1Oi1ll AND nlOl1li0l)); + wire_nlOl1liO_dataout <= wire_nlOlOl1O_dataout AND NOT(niOO00l1l); + wire_nlOl1lli_dataout <= wire_nlOlOl0i_dataout AND NOT(niOO00l1l); + wire_nlOl1lll_dataout <= wire_nlOlOl0l_dataout AND NOT(niOO00l1l); + wire_nlOl1llO_dataout <= wire_nlOlOl0O_dataout AND NOT(niOO00l1l); + wire_nlOl1lOi_dataout <= wire_nlOlOlii_dataout AND NOT(niOO00l1l); + wire_nlOl1lOl_dataout <= wire_nlOlOlil_dataout AND NOT(niOO00l1l); + wire_nlOl1lOO_dataout <= wire_nlOlOliO_dataout AND NOT(niOO00l1l); + wire_nlOl1O0i_dataout <= wire_nlOlOlOi_dataout AND NOT(niOO00l1l); + wire_nlOl1O0l_dataout <= wire_nlOlOlOl_dataout AND NOT(niOO00l1l); + wire_nlOl1O0O_dataout <= wire_nlOlOlOO_dataout AND NOT(niOO00l1l); + wire_nlOl1O1i_dataout <= wire_nlOlOlli_dataout AND NOT(niOO00l1l); + wire_nlOl1O1l_dataout <= wire_nlOlOlll_dataout AND NOT(niOO00l1l); + wire_nlOl1O1O_dataout <= wire_nlOlOllO_dataout AND NOT(niOO00l1l); + wire_nlOl1Oii_dataout <= wire_nlOlOO1i_dataout AND NOT(niOO00l1l); + wire_nlOl1Oil_dataout <= wire_nlOlOO1l_dataout AND NOT(niOO00l1l); + wire_nlOl1OiO_dataout <= wire_nlOlOO1O_dataout AND NOT(niOO00l1l); + wire_nlOl1Oli_dataout <= wire_nlOlOO0i_dataout AND NOT(niOO00l1l); + wire_nlOl1Oll_dataout <= wire_nlOlOO0l_dataout AND NOT(niOO00l1l); + wire_nlOl1OlO_dataout <= wire_nlOlOO0O_dataout AND NOT(niOO00l1l); + wire_nlOl1OOi_dataout <= wire_nlOlOOii_dataout AND NOT(niOO00l1l); + wire_nlOl1OOl_dataout <= wire_nlOlOOil_dataout AND NOT(niOO00l1l); + wire_nlOl1OOO_dataout <= wire_nlOlOOiO_dataout AND NOT(niOO00l1l); + wire_nlOli0ii_dataout <= nlOili0O OR (wire_nl1000i_w_lg_n1l011l4303w(0) OR wire_nl11llO_w_lg_n1l011O4307w(0)); + wire_nlOli10i_dataout <= wire_nlOli0ii_dataout WHEN niOO00i0O = '1' ELSE wire_nlOli1ii_dataout; + wire_nlOli10l_dataout <= nlO0OOOO OR niOO00i0O; + wire_nlOli10O_dataout <= nlOili0l OR niOO00i0O; + wire_nlOli11i_dataout <= wire_nlOlii1l_dataout WHEN niOO00lll = '1' ELSE wire_nlOli10i_dataout; + wire_nlOli11l_dataout <= wire_nlOli10l_dataout AND NOT(niOO00lll); + wire_nlOli11O_dataout <= wire_nlOli10O_dataout AND NOT(niOO00lll); + wire_nlOli1ii_dataout <= nlOili0O AND NOT((wire_w_lg_niOO00iii4313w(0) OR wire_w_lg_niOO00ill4320w(0))); + wire_nlOlii0i_dataout <= wire_n1il0lO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0llO_dataout; + wire_nlOlii0l_dataout <= wire_n1il0Oi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0lOi_dataout; + wire_nlOlii0O_dataout <= wire_n1il0Ol_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0lOl_dataout; + wire_nlOlii1l_dataout <= nlOili0O AND NOT(niOO00iii); + wire_nlOlii1O_dataout <= wire_n1il0ll_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0lll_dataout; + wire_nlOliiii_dataout <= wire_n1il0OO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0lOO_dataout; + wire_nlOliiil_dataout <= wire_n1ili1i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0O1i_dataout; + wire_nlOliiiO_dataout <= wire_n1ili1l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0O1l_dataout; + wire_nlOliili_dataout <= wire_n1ili1O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0O1O_dataout; + wire_nlOliill_dataout <= wire_n1ili0i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0O0i_dataout; + wire_nlOliilO_dataout <= wire_n1ili0l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0O0l_dataout; + wire_nlOliiOi_dataout <= wire_n1ili0O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0O0O_dataout; + wire_nlOliiOl_dataout <= wire_n1iliii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0Oii_dataout; + wire_nlOliiOO_dataout <= wire_n1iliil_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0Oil_dataout; + wire_nlOlil00i_dataout <= wire_nlOlilOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil00l_dataout <= wire_nlOlilOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil00O_dataout <= wire_nlOlilOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil01i_dataout <= wire_nlOlilO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil01l_dataout <= wire_nlOlilO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil01O_dataout <= wire_nlOlilOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil0i_dataout <= wire_n1ililO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0OlO_dataout; + wire_nlOlil0ii_dataout <= wire_nlOlilOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil0il_dataout <= wire_nlOlilOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil0iO_dataout <= wire_nlOlilOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil0l_dataout <= wire_n1iliOi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0OOi_dataout; + wire_nlOlil0O_dataout <= wire_n1iliOl_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0OOl_dataout; + wire_nlOlil1i_dataout <= wire_n1iliiO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0OiO_dataout; + wire_nlOlil1ii_dataout <= wire_w_lg_niOl1i1li25150w(0) AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1il_dataout <= wire_w_lg_niOl1i1ll25149w(0) AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1iO_dataout <= wire_nlOlilllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1l_dataout <= wire_n1ilili_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0Oli_dataout; + wire_nlOlil1li_dataout <= wire_nlOlillOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1ll_dataout <= wire_nlOlillOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1lO_dataout <= wire_nlOlillOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1O_dataout <= wire_n1ilill_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0Oll_dataout; + wire_nlOlil1Oi_dataout <= wire_nlOlilO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1Ol_dataout <= wire_nlOlilO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlil1OO_dataout <= wire_nlOlilO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlilii_dataout <= wire_n1iliOO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOO0OOO_dataout; + wire_nlOlilil_dataout <= wire_n1ill1i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi11i_dataout; + wire_nlOliliO_dataout <= wire_n1ill1l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi11l_dataout; + wire_nlOlilli_dataout <= wire_n1ill1O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi11O_dataout; + wire_nlOlilll_dataout <= wire_n1ill0i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi10i_dataout; + wire_nlOlilllO_dataout <= n1Oi101O WHEN niOl1i1lO = '1' ELSE nlOliiO0l; + wire_nlOlillO_dataout <= wire_n1ill0l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi10l_dataout; + wire_nlOlillOi_dataout <= n011iOii WHEN niOl1i1lO = '1' ELSE nlOliiO0O; + wire_nlOlillOl_dataout <= n01O1ill WHEN niOl1i1lO = '1' ELSE nlOliiOii; + wire_nlOlillOO_dataout <= n00il1OO WHEN niOl1i1lO = '1' ELSE nlOliiOil; + wire_nlOlilO0i_dataout <= n0O0lO1i WHEN niOl1i1lO = '1' ELSE nlOliiOlO; + wire_nlOlilO0O_dataout <= n1Oi1l0i WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOliiOOi; + wire_nlOlilO1i_dataout <= n0i01O0i WHEN niOl1i1lO = '1' ELSE nlOliiOiO; + wire_nlOlilO1l_dataout <= n0iOliil WHEN niOl1i1lO = '1' ELSE nlOliiOli; + wire_nlOlilO1O_dataout <= n0ll01lO WHEN niOl1i1lO = '1' ELSE nlOliiOll; + wire_nlOlilOi_dataout <= wire_n1ill0O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi10O_dataout; + wire_nlOlilOii_dataout <= n011l0il WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOliiOOl; + wire_nlOlilOil_dataout <= n01O1OlO WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOliiOOO; + wire_nlOlilOiO_dataout <= n00ill1i WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOlil11i; + wire_nlOlilOl_dataout <= wire_n1illii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1ii_dataout; + wire_nlOlilOli_dataout <= n0i0000l WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOlil11l; + wire_nlOlilOll_dataout <= n0iOlOiO WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOlil11O; + wire_nlOlilOlO_dataout <= n0ll0iOi WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOlil10i; + wire_nlOlilOO_dataout <= wire_n1illil_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1il_dataout; + wire_nlOlilOOi_dataout <= n0O0O01l WHEN wire_w_lg_niOl1i1OO25058w(0) = '1' ELSE nlOlil10l; + wire_nlOlilOOl_dataout <= wire_n1il0liO_dataout WHEN n1110Oii = '1' ELSE wire_n1il00OO_dataout; + wire_nlOlilOOO_dataout <= wire_nlOlilOOl_dataout OR wire_niO01ill_w_lg_n11O0i1i20661w(0); + wire_nlOliO0i_dataout <= wire_n1illlO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1lO_dataout; + wire_nlOliO0l_dataout <= wire_n1illOi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1Oi_dataout; + wire_nlOliO0lO_dataout <= wire_nlOliOlil_dataout OR wire_niO01lOO_dataout; + wire_nlOliO0O_dataout <= wire_n1illOl_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1Ol_dataout; + wire_nlOliO0Oi_dataout <= wire_nlOliOliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliO0Ol_dataout <= wire_nlOliOlli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliO0OO_dataout <= wire_nlOliOlll_dataout OR wire_niO01lOO_dataout; + wire_nlOliO1i_dataout <= wire_n1illiO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1iO_dataout; + wire_nlOliO1l_dataout <= wire_n1illli_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1li_dataout; + wire_nlOliO1O_dataout <= wire_n1illll_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1ll_dataout; + wire_nlOliOi0i_dataout <= wire_nlOliOlOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOi0l_dataout <= wire_nlOliOO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOi0O_dataout <= wire_nlOliOO1l_dataout OR wire_niO01lOO_dataout; + wire_nlOliOi1i_dataout <= wire_nlOliOllO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOi1l_dataout <= wire_nlOliOlOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOi1O_dataout <= wire_nlOliOlOl_dataout OR wire_niO01lOO_dataout; + wire_nlOliOii_dataout <= wire_n1illOO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi1OO_dataout; + wire_nlOliOiii_dataout <= wire_nlOliOO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOiil_dataout <= wire_nlOliOO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOiiO_dataout <= wire_nlOliOO0l_dataout OR wire_niO01lOO_dataout; + wire_nlOliOil_dataout <= wire_n1ilO1i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi01i_dataout; + wire_nlOliOili_dataout <= wire_nlOliOO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOill_dataout <= wire_nlOliOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOilO_dataout <= wire_nlOliOOil_dataout OR wire_niO01lOO_dataout; + wire_nlOliOiO_dataout <= wire_n1ilO1l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi01l_dataout; + wire_nlOliOiOi_dataout <= wire_nlOliOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOiOl_dataout <= wire_nlOliOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOiOO_dataout <= wire_nlOliOOll_dataout OR wire_niO01lOO_dataout; + wire_nlOliOl0i_dataout <= wire_nlOliOOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOl0l_dataout <= wire_nlOll111i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOl0O_dataout <= wire_nlOll111l_dataout OR wire_niO01lOO_dataout; + wire_nlOliOl1i_dataout <= wire_nlOliOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOl1l_dataout <= wire_nlOliOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOl1O_dataout <= wire_nlOliOOOl_dataout OR wire_niO01lOO_dataout; + wire_nlOliOli_dataout <= wire_n1ilO1O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi01O_dataout; + wire_nlOliOlii_dataout <= wire_nlOll111O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOliOlil_dataout <= nlOlil10O WHEN niOl1i01i = '1' ELSE wire_nlOll110O_dataout; + wire_nlOliOliO_dataout <= nlOliO11i WHEN niOl1i01i = '1' ELSE wire_nlOll11ii_dataout; + wire_nlOliOll_dataout <= wire_n1ilO0i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi00i_dataout; + wire_nlOliOlli_dataout <= nlOliO11l WHEN niOl1i01i = '1' ELSE wire_nlOll11il_dataout; + wire_nlOliOlll_dataout <= nlOliO11O WHEN niOl1i01i = '1' ELSE wire_nlOll11iO_dataout; + wire_nlOliOllO_dataout <= nlOliO10i WHEN niOl1i01i = '1' ELSE wire_nlOll11li_dataout; + wire_nlOliOlO_dataout <= wire_n1ilO0l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi00l_dataout; + wire_nlOliOlOi_dataout <= nlOliO10l WHEN niOl1i01i = '1' ELSE wire_nlOll11ll_dataout; + wire_nlOliOlOl_dataout <= nlOliO10O WHEN niOl1i01i = '1' ELSE wire_nlOll11lO_dataout; + wire_nlOliOlOO_dataout <= nlOliO1ii WHEN niOl1i01i = '1' ELSE wire_nlOll11Oi_dataout; + wire_nlOliOO0i_dataout <= nlOliO1ll WHEN niOl1i01i = '1' ELSE wire_nlOll101l_dataout; + wire_nlOliOO0l_dataout <= nlOliO1lO WHEN niOl1i01i = '1' ELSE wire_nlOll101O_dataout; + wire_nlOliOO0O_dataout <= nlOliO1Oi WHEN niOl1i01i = '1' ELSE wire_nlOll100i_dataout; + wire_nlOliOO1i_dataout <= nlOliO1il WHEN niOl1i01i = '1' ELSE wire_nlOll11Ol_dataout; + wire_nlOliOO1l_dataout <= nlOliO1iO WHEN niOl1i01i = '1' ELSE wire_nlOll11OO_dataout; + wire_nlOliOO1O_dataout <= nlOliO1li WHEN niOl1i01i = '1' ELSE wire_nlOll101i_dataout; + wire_nlOliOOi_dataout <= wire_n1ilO0O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi00O_dataout; + wire_nlOliOOii_dataout <= nlOliO1Ol WHEN niOl1i01i = '1' ELSE wire_nlOll100l_dataout; + wire_nlOliOOil_dataout <= nlOliO1OO WHEN niOl1i01i = '1' ELSE wire_nlOll100O_dataout; + wire_nlOliOOiO_dataout <= nlOliO01i WHEN niOl1i01i = '1' ELSE wire_nlOll10ii_dataout; + wire_nlOliOOl_dataout <= wire_n1ilOii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0ii_dataout; + wire_nlOliOOli_dataout <= nlOliO01l WHEN niOl1i01i = '1' ELSE wire_nlOll10il_dataout; + wire_nlOliOOll_dataout <= nlOliO01O WHEN niOl1i01i = '1' ELSE wire_nlOll10iO_dataout; + wire_nlOliOOlO_dataout <= nlOliO00i WHEN niOl1i01i = '1' ELSE wire_nlOll10li_dataout; + wire_nlOliOOO_dataout <= wire_n1ilOil_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0il_dataout; + wire_nlOliOOOi_dataout <= nlOliO00l WHEN niOl1i01i = '1' ELSE wire_nlOll10ll_dataout; + wire_nlOliOOOl_dataout <= nlOliO00O WHEN niOl1i01i = '1' ELSE wire_nlOll10lO_dataout; + wire_nlOliOOOO_dataout <= nlOliO0ii WHEN niOl1i01i = '1' ELSE wire_nlOll10Oi_dataout; + wire_nlOll00i_dataout <= wire_n1iO1lO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiilO_dataout; + wire_nlOll00ii_dataout <= wire_nlOll0i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00il_dataout <= wire_nlOll0i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00iO_dataout <= wire_nlOll0iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00l_dataout <= wire_n1iO1Oi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiiOi_dataout; + wire_nlOll00li_dataout <= wire_nlOll0iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00ll_dataout <= wire_nlOll0iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00lO_dataout <= wire_nlOll0ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00O_dataout <= wire_n1iO1Ol_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiiOl_dataout; + wire_nlOll00Oi_dataout <= wire_nlOll0ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00Ol_dataout <= wire_nlOll0ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll00OO_dataout <= wire_nlOll0iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll010i_dataout <= wire_nlOll011O_dataout WHEN niOl0i01i = '1' ELSE wire_n10iO11l_dataout; + wire_nlOll011l_dataout <= wire_nlOi0iill_dataout WHEN wire_niO01ill_w_lg_n11O0OiO21115w(0) = '1' ELSE n11O0i0i; + wire_nlOll011O_dataout <= n1iiii1i WHEN niOO10lOO = '1' ELSE wire_nlOll011l_dataout; + wire_nlOll01i_dataout <= wire_n1iO1iO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiiiO_dataout; + wire_nlOll01l_dataout <= wire_n1iO1li_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiili_dataout; + wire_nlOll01O_dataout <= wire_n1iO1ll_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiill_dataout; + wire_nlOll0i0i_dataout <= wire_nlOll0l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll0i0l_dataout <= wire_nlOll0l1O_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0i0O_dataout <= wire_nlOll0l0i_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0i1i_dataout <= wire_nlOll0iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll0i1l_dataout <= wire_nlOll0iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll0i1O_dataout <= wire_nlOll0l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll0ii_dataout <= wire_n1iO1OO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiiOO_dataout; + wire_nlOll0iii_dataout <= wire_nlOll0l0l_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0iil_dataout <= wire_nlOll0l0O_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0iiO_dataout <= wire_nlOll0lii_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0il_dataout <= wire_n1iO01l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOil1l_dataout; + wire_nlOll0ili_dataout <= wire_nlOll0lil_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0ill_dataout <= wire_nlOll0liO_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0ilO_dataout <= wire_nlOll0lli_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0iO_dataout <= wire_n1iO01O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOil1O_dataout; + wire_nlOll0iOi_dataout <= wire_nlOll0lll_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0iOl_dataout <= wire_nlOll0llO_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0iOO_dataout <= wire_nlOll0lOi_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0l0i_dataout <= wire_nlOll0O1i_o(1) WHEN niOl1i01l = '1' ELSE nlOll01iO; + wire_nlOll0l0l_dataout <= wire_nlOll0O1i_o(2) WHEN niOl1i01l = '1' ELSE nlOll01li; + wire_nlOll0l0O_dataout <= wire_nlOll0O1i_o(3) WHEN niOl1i01l = '1' ELSE nlOll01ll; + wire_nlOll0l1i_dataout <= wire_nlOll0lOl_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0l1l_dataout <= wire_nlOll0lOO_dataout AND NOT(wire_niO01ill_w_lg_nlOll0O0i19983w(0)); + wire_nlOll0l1O_dataout <= wire_nlOll0O1i_o(0) WHEN niOl1i01l = '1' ELSE nlOliO0ll; + wire_nlOll0li_dataout <= wire_n1iO00i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOil0i_dataout; + wire_nlOll0lii_dataout <= wire_nlOll0O1i_o(4) WHEN niOl1i01l = '1' ELSE nlOll01lO; + wire_nlOll0lil_dataout <= wire_nlOll0O1i_o(5) WHEN niOl1i01l = '1' ELSE nlOll01Oi; + wire_nlOll0liO_dataout <= wire_nlOll0O1i_o(6) WHEN niOl1i01l = '1' ELSE nlOll01Ol; + wire_nlOll0ll_dataout <= wire_n1iO00l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOil0l_dataout; + wire_nlOll0lli_dataout <= wire_nlOll0O1i_o(7) WHEN niOl1i01l = '1' ELSE nlOll01OO; + wire_nlOll0lll_dataout <= wire_nlOll0O1i_o(8) WHEN niOl1i01l = '1' ELSE nlOll001i; + wire_nlOll0llO_dataout <= wire_nlOll0O1i_o(9) WHEN niOl1i01l = '1' ELSE nlOll001l; + wire_nlOll0lO_dataout <= wire_n1iO00O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOil0O_dataout; + wire_nlOll0lOi_dataout <= wire_nlOll0O1i_o(10) WHEN niOl1i01l = '1' ELSE nlOll001O; + wire_nlOll0lOl_dataout <= wire_nlOll0O1i_o(11) WHEN niOl1i01l = '1' ELSE nlOll000i; + wire_nlOll0lOO_dataout <= wire_nlOll0O1i_o(12) WHEN niOl1i01l = '1' ELSE nlOll000l; + wire_nlOll0Oi_dataout <= wire_n1iO0ii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOilii_dataout; + wire_nlOll0Oil_dataout <= wire_nlOll0OOi_o AND NOT(wire_niO01lOO_dataout); + wire_nlOll0OiO_dataout <= wire_nlOll0OOl_o AND NOT(wire_niO01lOO_dataout); + wire_nlOll0Ol_dataout <= wire_n1iO0il_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOilil_dataout; + wire_nlOll0Oli_dataout <= wire_nlOll0OOO_o AND NOT(wire_niO01lOO_dataout); + wire_nlOll0Oll_dataout <= wire_nlOlli11i_o AND NOT(wire_niO01lOO_dataout); + wire_nlOll0OlO_dataout <= wire_nlOlli11l_o OR wire_niO01lOO_dataout; + wire_nlOll0OO_dataout <= wire_n1iO0iO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiliO_dataout; + wire_nlOll100i_dataout <= n00ilOOl WHEN niOl1i1Ol = '1' ELSE nlOliO1Oi; + wire_nlOll100l_dataout <= n00ilOOO WHEN niOl1i1Ol = '1' ELSE nlOliO1Ol; + wire_nlOll100O_dataout <= n01O00iO WHEN niOl1i1Ol = '1' ELSE nlOliO1OO; + wire_nlOll101i_dataout <= n0i00l1O WHEN niOl1i1Ol = '1' ELSE nlOliO1li; + wire_nlOll101l_dataout <= n0i00l0i WHEN niOl1i1Ol = '1' ELSE nlOliO1ll; + wire_nlOll101O_dataout <= n00ilOOi WHEN niOl1i1Ol = '1' ELSE nlOliO1lO; + wire_nlOll10i_dataout <= wire_n1ilOlO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0lO_dataout; + wire_nlOll10ii_dataout <= n01O00li WHEN niOl1i1Ol = '1' ELSE nlOliO01i; + wire_nlOll10il_dataout <= n01O00ll WHEN niOl1i1Ol = '1' ELSE nlOliO01l; + wire_nlOll10iO_dataout <= n011ll0l WHEN niOl1i1Ol = '1' ELSE nlOliO01O; + wire_nlOll10l_dataout <= wire_n1ilOOi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0Oi_dataout; + wire_nlOll10li_dataout <= n011ll0O WHEN niOl1i1Ol = '1' ELSE nlOliO00i; + wire_nlOll10ll_dataout <= n011llii WHEN niOl1i1Ol = '1' ELSE nlOliO00l; + wire_nlOll10lO_dataout <= n1Oi011i WHEN niOl1i1Ol = '1' ELSE nlOliO00O; + wire_nlOll10O_dataout <= wire_n1ilOOl_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0Ol_dataout; + wire_nlOll10Oi_dataout <= n1Oi011l WHEN niOl1i1Ol = '1' ELSE nlOliO0ii; + wire_nlOll10Ol_dataout <= n1Oi011O WHEN niOl1i1Ol = '1' ELSE nlOliO0il; + wire_nlOll10OO_dataout <= wire_w_lg_niOl1i1Oi25148w(0) OR wire_w_lg_niOO10l1i20908w(0); + wire_nlOll110i_dataout <= wire_nlOll10OO_dataout WHEN niOl1i1Ol = '1' ELSE nlOliO0iO; + wire_nlOll110l_dataout <= wire_nlOll1i1i_dataout WHEN niOl1i1Ol = '1' ELSE nlOliO0li; + wire_nlOll110O_dataout <= n0O0OiOl WHEN niOl1i1Ol = '1' ELSE nlOlil10O; + wire_nlOll111i_dataout <= nlOliO0il WHEN niOl1i01i = '1' ELSE wire_nlOll10Ol_dataout; + wire_nlOll111l_dataout <= wire_nlOll110i_dataout OR niOl1i01i; + wire_nlOll111O_dataout <= wire_nlOll110l_dataout AND NOT(niOl1i01i); + wire_nlOll11i_dataout <= wire_n1ilOiO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0iO_dataout; + wire_nlOll11ii_dataout <= n0O0OiOO WHEN niOl1i1Ol = '1' ELSE nlOliO11i; + wire_nlOll11il_dataout <= n0O0Ol1i WHEN niOl1i1Ol = '1' ELSE nlOliO11l; + wire_nlOll11iO_dataout <= n0ll0Oli WHEN niOl1i1Ol = '1' ELSE nlOliO11O; + wire_nlOll11l_dataout <= wire_n1ilOli_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0li_dataout; + wire_nlOll11li_dataout <= n0ll0Oll WHEN niOl1i1Ol = '1' ELSE nlOliO10i; + wire_nlOll11ll_dataout <= n0ll0OlO WHEN niOl1i1Ol = '1' ELSE nlOliO10l; + wire_nlOll11lO_dataout <= n0iOO00O WHEN niOl1i1Ol = '1' ELSE nlOliO10O; + wire_nlOll11O_dataout <= wire_n1ilOll_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0ll_dataout; + wire_nlOll11Oi_dataout <= n0iOO0ii WHEN niOl1i1Ol = '1' ELSE nlOliO1ii; + wire_nlOll11Ol_dataout <= n0iOO0il WHEN niOl1i1Ol = '1' ELSE nlOliO1il; + wire_nlOll11OO_dataout <= n0i00l1l WHEN niOl1i1Ol = '1' ELSE nlOliO1iO; + wire_nlOll1i1i_dataout <= niOl1i1Oi AND NOT(wire_w_lg_niOO10l1i20908w(0)); + wire_nlOll1ii_dataout <= wire_n1ilOOO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOi0OO_dataout; + wire_nlOll1iiO_dataout <= wire_nlOlilOOO_dataout WHEN n11O0l0O = '1' ELSE wire_n1il001i_dataout; + wire_nlOll1il_dataout <= wire_n1iO11i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOii1i_dataout; + wire_nlOll1ill_dataout <= wire_n1il0lOi_dataout WHEN n11O0Oil = '1' ELSE wire_nlOll1iiO_dataout; + wire_nlOll1iO_dataout <= wire_n1iO11l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOii1l_dataout; + wire_nlOll1iOl_dataout <= wire_n1il0OOi_dataout WHEN n11O0lli = '1' ELSE wire_nlOll1ill_dataout; + wire_nlOll1iOO_dataout <= wire_nlOll1iOl_dataout OR wire_niO01lOO_dataout; + wire_nlOll1l0i_dataout <= n1il11lO WHEN wire_niO01ill_w_lg_n11O0i1i20661w(0) = '1' ELSE wire_nlOll1l1O_dataout; + wire_nlOll1l0l_dataout <= wire_nlOll1l0i_dataout WHEN n11O0l0O = '1' ELSE wire_n1il01Ol_dataout; + wire_nlOll1l0O_dataout <= wire_n1il0lll_dataout WHEN n11O0Oil = '1' ELSE wire_nlOll1l0l_dataout; + wire_nlOll1l1O_dataout <= wire_n1il0lli_dataout WHEN n1110Oii = '1' ELSE wire_n1il0i1l_dataout; + wire_nlOll1li_dataout <= wire_n1iO11O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOii1O_dataout; + wire_nlOll1lil_dataout <= wire_n1il0Oll_dataout WHEN n11O0lli = '1' ELSE wire_nlOll1l0O_dataout; + wire_nlOll1ll_dataout <= wire_n1iO10i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOii0i_dataout; + wire_nlOll1lli_dataout <= wire_nlOll1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll1lll_dataout <= n1il11ll WHEN n1110Oii = '1' ELSE wire_n1il00Ol_dataout; + wire_nlOll1lO_dataout <= wire_n1iO10l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOii0l_dataout; + wire_nlOll1lOi_dataout <= wire_nlOll1lll_dataout OR wire_niO01ill_w_lg_n11O0i1i20661w(0); + wire_nlOll1lOO_dataout <= wire_nlOll1lOi_dataout WHEN n11O0l0O = '1' ELSE wire_n1il01OO_dataout; + wire_nlOll1O0O_dataout <= n1il11li WHEN n1110Oii = '1' ELSE wire_n1il0i1i_dataout; + wire_nlOll1O1i_dataout <= n1il11ll WHEN n11O0Oil = '1' ELSE wire_nlOll1lOO_dataout; + wire_nlOll1O1l_dataout <= n1il11ll WHEN n11O0lli = '1' ELSE wire_nlOll1O1i_dataout; + wire_nlOll1O1O_dataout <= wire_nlOll1O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll1Oi_dataout <= wire_n1iO10O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOii0O_dataout; + wire_nlOll1Oii_dataout <= n1il11li WHEN wire_niO01ill_w_lg_n11O0i1i20661w(0) = '1' ELSE wire_nlOll1O0O_dataout; + wire_nlOll1Oil_dataout <= wire_nlOll1Oii_dataout WHEN n11O0l0O = '1' ELSE wire_n1il01Oi_dataout; + wire_nlOll1Ol_dataout <= wire_n1iO1ii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiiii_dataout; + wire_nlOll1Oli_dataout <= n1il11li WHEN n11O0Oil = '1' ELSE wire_nlOll1Oil_dataout; + wire_nlOll1OlO_dataout <= n1il11li WHEN n11O0lli = '1' ELSE wire_nlOll1Oli_dataout; + wire_nlOll1OO_dataout <= wire_n1iO1il_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiiil_dataout; + wire_nlOll1OOi_dataout <= wire_nlOll1OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOll1OOO_dataout <= k_conf(360) WHEN niOO10lOO = '1' ELSE wire_nlOi0iill_dataout; + wire_nlOlli00i_dataout <= nlOll0Oii AND NOT(niOl0111l); + wire_nlOlli01i_dataout <= nlOll0O0i AND NOT(niOl0111l); + wire_nlOlli01l_dataout <= nlOll0O0l AND NOT(niOl0111l); + wire_nlOlli01O_dataout <= nlOll0O0O AND NOT(niOl0111l); + wire_nlOlli0i_dataout <= wire_n1iO0Oi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOilOi_dataout; + wire_nlOlli0l_dataout <= wire_n1iO0Ol_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOilOl_dataout; + wire_nlOlli0O_dataout <= wire_n1iO0OO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOilOO_dataout; + wire_nlOlli0Ol_dataout <= nlOll000O AND NOT(niOl1i0il); + wire_nlOlli0OO_dataout <= nlOll0O0i OR niOl1i0il; + wire_nlOlli10i_dataout <= nlOll0O0i AND NOT(niOl1i00i); + wire_nlOlli10l_dataout <= nlOll0O0l AND NOT(niOl1i00i); + wire_nlOlli10O_dataout <= nlOll0O0O AND NOT(niOl1i00i); + wire_nlOlli11O_dataout <= nlOll000O AND NOT(niOl1i00i); + wire_nlOlli1i_dataout <= wire_n1iO0li_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOilli_dataout; + wire_nlOlli1ii_dataout <= nlOll0Oii OR niOl1i00i; + wire_nlOlli1l_dataout <= wire_n1iO0ll_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOilll_dataout; + wire_nlOlli1li_dataout <= wire_nlOlli1OO_dataout OR niOl1i00l; + wire_nlOlli1ll_dataout <= wire_nlOlli01i_dataout AND NOT(niOl1i00l); + wire_nlOlli1lO_dataout <= wire_nlOlli01l_dataout AND NOT(niOl1i00l); + wire_nlOlli1O_dataout <= wire_n1iO0lO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOillO_dataout; + wire_nlOlli1Oi_dataout <= wire_nlOlli01O_dataout AND NOT(niOl1i00l); + wire_nlOlli1Ol_dataout <= wire_nlOlli00i_dataout AND NOT(niOl1i00l); + wire_nlOlli1OO_dataout <= nlOll000O OR niOl0111l; + wire_nlOllii1i_dataout <= nlOll0O0l AND NOT(niOl1i0il); + wire_nlOllii1l_dataout <= nlOll0O0O AND NOT(niOl1i0il); + wire_nlOllii1O_dataout <= nlOll0Oii AND NOT(niOl1i0il); + wire_nlOlliii_dataout <= wire_n1iOi1i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiO1i_dataout; + wire_nlOlliiii_dataout <= nlOll000O AND NOT(niOl01OOl); + wire_nlOlliiil_dataout <= nlOll0O0i AND NOT(niOl01OOl); + wire_nlOlliiiO_dataout <= nlOll0O0l OR niOl01OOl; + wire_nlOlliil_dataout <= wire_n1iOi1l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiO1l_dataout; + wire_nlOlliili_dataout <= nlOll0O0O AND NOT(niOl01OOl); + wire_nlOlliill_dataout <= nlOll0Oii AND NOT(niOl01OOl); + wire_nlOlliilO_dataout <= nlOll000O AND NOT(niOl1i0iO); + wire_nlOlliiO_dataout <= wire_n1iOi1O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiO1O_dataout; + wire_nlOlliiOi_dataout <= nlOll0O0i AND NOT(niOl1i0iO); + wire_nlOlliiOl_dataout <= nlOll0O0l AND NOT(niOl1i0iO); + wire_nlOlliiOO_dataout <= nlOll0O0O OR niOl1i0iO; + wire_nlOllil1i_dataout <= nlOll0Oii AND NOT(niOl1i0iO); + wire_nlOllili_dataout <= wire_n1iOi0i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiO0i_dataout; + wire_nlOllill_dataout <= wire_n1iOi0l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiO0l_dataout; + wire_nlOllilO_dataout <= wire_n1iOi0O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiO0O_dataout; + wire_nlOlliOi_dataout <= wire_n1iOiii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOii_dataout; + wire_nlOlliOl_dataout <= wire_n1iOiil_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOil_dataout; + wire_nlOlliOO_dataout <= wire_n1iOiiO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOiO_dataout; + wire_nlOlll00i_dataout <= wire_nlOllliOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll00l_dataout <= wire_nlOllliOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll00O_dataout <= wire_nlOllliOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll01i_dataout <= wire_nlOlllili_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll01l_dataout <= wire_nlOlllill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll01O_dataout <= wire_nlOlllilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll0i_dataout <= wire_n1iOiOi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOOi_dataout; + wire_nlOlll0ii_dataout <= wire_nlOllll1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll0il_dataout <= wire_nlOllll1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll0iO_dataout <= wire_nlOllll1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll0l_dataout <= wire_n1iOiOl_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOOl_dataout; + wire_nlOlll0li_dataout <= wire_niilliOl_dataout AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlll0ll_dataout <= wire_nlOllli0i_o(0) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlll0lO_dataout <= wire_nlOllli0i_o(1) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlll0O_dataout <= wire_n1iOiOO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOOO_dataout; + wire_nlOlll0Oi_dataout <= wire_nlOllli0i_o(2) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlll0Ol_dataout <= wire_nlOllli0i_o(3) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlll0OO_dataout <= wire_nlOllli0i_o(4) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlll10i_dataout <= wire_nlOlll0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll10l_dataout <= wire_nlOlll0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll10O_dataout <= wire_nlOlll0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll11i_dataout <= wire_nlOlll0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll11l_dataout <= wire_nlOlll0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll11O_dataout <= wire_nlOlll0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1i_dataout <= wire_n1iOili_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOli_dataout; + wire_nlOlll1ii_dataout <= wire_nlOllli1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1il_dataout <= wire_nlOllli1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1iO_dataout <= wire_nlOllli1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1l_dataout <= wire_n1iOill_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOll_dataout; + wire_nlOlll1li_dataout <= wire_nlOii0Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1ll_dataout <= wire_nlOllli0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1lO_dataout <= wire_nlOllli0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1O_dataout <= wire_n1iOilO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOiOlO_dataout; + wire_nlOlll1Oi_dataout <= wire_nlOllliii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1Ol_dataout <= wire_nlOllliil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlll1OO_dataout <= wire_nlOllliiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllli0l_dataout <= wire_nlOllll0i_o(0) AND nlOllll0l; + wire_nlOllli0O_dataout <= wire_nlOllll0i_o(1) AND nlOllll0l; + wire_nlOllli1i_dataout <= wire_nlOllli0i_o(5) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOllli1l_dataout <= wire_nlOllli0i_o(6) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOllli1O_dataout <= wire_nlOllli0i_o(7) AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlllii_dataout <= wire_n1iOl1i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl11i_dataout; + wire_nlOllliii_dataout <= wire_nlOllll0i_o(2) AND nlOllll0l; + wire_nlOllliil_dataout <= wire_nlOllll0i_o(3) AND nlOllll0l; + wire_nlOllliiO_dataout <= wire_nlOllll0i_o(4) AND nlOllll0l; + wire_nlOlllil_dataout <= wire_n1iOl1l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl11l_dataout; + wire_nlOlllili_dataout <= wire_nlOllll0i_o(5) AND nlOllll0l; + wire_nlOlllill_dataout <= wire_nlOllll0i_o(6) AND nlOllll0l; + wire_nlOlllilO_dataout <= wire_nlOllll0i_o(7) AND nlOllll0l; + wire_nlOllliO_dataout <= wire_n1iOl1O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl11O_dataout; + wire_nlOllliOi_dataout <= wire_nlOllll0i_o(8) AND nlOllll0l; + wire_nlOllliOl_dataout <= wire_nlOllll0i_o(9) AND nlOllll0l; + wire_nlOllliOO_dataout <= wire_nlOllll0i_o(10) AND nlOllll0l; + wire_nlOllll1i_dataout <= wire_nlOllll0i_o(11) AND nlOllll0l; + wire_nlOllll1l_dataout <= wire_nlOllll0i_o(12) AND nlOllll0l; + wire_nlOllll1O_dataout <= wire_nlOllll0i_o(13) AND nlOllll0l; + wire_nlOlllli_dataout <= wire_n1iOl0i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl10i_dataout; + wire_nlOlllliO_dataout <= wire_nlOllllOi_o AND NOT(wire_niO01lOO_dataout); + wire_nlOlllll_dataout <= wire_n1iOl0l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl10l_dataout; + wire_nlOllllli_dataout <= wire_nlOllllOl_o AND NOT(wire_niO01lOO_dataout); + wire_nlOllllll_dataout <= wire_nlOllllOO_o AND NOT(wire_niO01lOO_dataout); + wire_nlOlllllO_dataout <= wire_nlOlllO1i_o OR wire_niO01lOO_dataout; + wire_nlOllllO_dataout <= wire_n1iOl0O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl10O_dataout; + wire_nlOlllO0i_dataout <= nlOllll0O AND NOT(n11O0llO); + wire_nlOlllO0l_dataout <= nlOllllii OR n11O0llO; + wire_nlOlllO0O_dataout <= wire_nlOlllOli_dataout AND NOT(niOl1i0ll); + wire_nlOlllO1l_dataout <= nlOlliOOO AND NOT(n11O0llO); + wire_nlOlllO1O_dataout <= nlOllll0l AND NOT(n11O0llO); + wire_nlOlllOi_dataout <= wire_n1iOlii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1ii_dataout; + wire_nlOlllOii_dataout <= wire_nlOlllOll_dataout AND NOT(niOl1i0ll); + wire_nlOlllOil_dataout <= wire_nlOlllOlO_dataout AND NOT(niOl1i0ll); + wire_nlOlllOiO_dataout <= wire_nlOlllOOi_dataout OR niOl1i0ll; + wire_nlOlllOl_dataout <= wire_n1iOlil_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1il_dataout; + wire_nlOlllOli_dataout <= nlOlliOOO OR niOl1i0li; + wire_nlOlllOll_dataout <= nlOllll0l AND NOT(niOl1i0li); + wire_nlOlllOlO_dataout <= nlOllll0O AND NOT(niOl1i0li); + wire_nlOlllOO_dataout <= wire_n1iOliO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1iO_dataout; + wire_nlOlllOOi_dataout <= nlOllllii AND NOT(niOl1i0li); + wire_nlOllO00i_dataout <= nlOllll0O OR niOl1i0Ol; + wire_nlOllO00l_dataout <= nlOllllii AND NOT(niOl1i0Ol); + wire_nlOllO01l_dataout <= nlOlliOOO AND NOT(niOl1i0Ol); + wire_nlOllO01O_dataout <= nlOllll0l AND NOT(niOl1i0Ol); + wire_nlOllO0i_dataout <= wire_n1iOlOi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1Oi_dataout; + wire_nlOllO0l_dataout <= wire_n1iOlOl_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1Ol_dataout; + wire_nlOllO0li_dataout <= (wire_niO01ill_w_lg_w_lg_w_lg_nlOO1O1Ol24778w24780w24781w(0) AND wire_w_lg_niOl1i0OO24782w(0)) AND NOT(wire_niO01lOO_dataout); + wire_nlOllO0O_dataout <= wire_n1iOlOO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1OO_dataout; + wire_nlOllO1i_dataout <= wire_n1iOlli_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1li_dataout; + wire_nlOllO1il_dataout <= wire_nlOllO1lO_dataout AND NOT(niOl1l11O); + wire_nlOllO1iO_dataout <= wire_nlOllO1Oi_dataout AND NOT(niOl1l11O); + wire_nlOllO1l_dataout <= wire_n1iOlll_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1ll_dataout; + wire_nlOllO1li_dataout <= wire_nlOllO1Ol_dataout AND NOT(niOl1l11O); + wire_nlOllO1ll_dataout <= wire_nlOllO1OO_dataout OR niOl1l11O; + wire_nlOllO1lO_dataout <= nlOlliOOO AND NOT(niOl1i0Oi); + wire_nlOllO1O_dataout <= wire_n1iOllO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl1lO_dataout; + wire_nlOllO1Oi_dataout <= nlOllll0l OR niOl1i0Oi; + wire_nlOllO1Ol_dataout <= nlOllll0O AND NOT(niOl1i0Oi); + wire_nlOllO1OO_dataout <= nlOllllii AND NOT(niOl1i0Oi); + wire_nlOllOii_dataout <= wire_n1iOO1i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl01i_dataout; + wire_nlOllOil_dataout <= wire_n1iOO1l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl01l_dataout; + wire_nlOllOiO_dataout <= wire_n1iOO1O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl01O_dataout; + wire_nlOllOli_dataout <= wire_n1iOO0i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl00i_dataout; + wire_nlOllOll_dataout <= wire_n1iOO0l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl00l_dataout; + wire_nlOllOlO_dataout <= wire_n1iOO0O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl00O_dataout; + wire_nlOllOO0i_dataout <= wire_nlOllOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOO0l_dataout <= wire_nlOllOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOO0O_dataout <= wire_nlOllOOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOO1l_dataout <= wire_nlOllOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOO1O_dataout <= wire_nlOllOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOOi_dataout <= wire_n1iOOii_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0ii_dataout; + wire_nlOllOOii_dataout <= wire_nlOllOOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOOil_dataout <= wire_nlOlO111i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOOiO_dataout <= wire_nlOlO111l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOllOOl_dataout <= wire_n1iOOil_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0il_dataout; + wire_nlOllOOli_dataout <= wire_niO01ill_w_lg_nlOOOl1ll24777w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO111O_dataout; + wire_nlOllOOll_dataout <= wire_niO01ill_w_lg_nlOOOl1lO24776w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO110i_dataout; + wire_nlOllOOlO_dataout <= wire_niO01ill_w_lg_nlOOOl1Oi24775w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO110l_dataout; + wire_nlOllOOO_dataout <= wire_n1iOOiO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0iO_dataout; + wire_nlOllOOOi_dataout <= wire_niO01ill_w_lg_nlOOOl1Ol24774w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO110O_dataout; + wire_nlOllOOOl_dataout <= wire_niO01ill_w_lg_nlOOOl1OO24773w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO11ii_dataout; + wire_nlOllOOOO_dataout <= wire_niO01ill_w_lg_nlOOOl01i24772w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO11il_dataout; + wire_nlOlO001i_dataout <= nlOlO011i AND niOl1iiil; + wire_nlOlO001l_dataout <= nlOlO1OOO OR niOl1iiil; + wire_nlOlO00i_dataout <= wire_nlll0lli_q(37) WHEN niOO00l1i = '1' ELSE wire_nlOO1OlO_dataout; + wire_nlOlO00ii_dataout <= wire_nlOlO00il_dataout WHEN n1lillil = '1' ELSE nlOlO1OOO; + wire_nlOlO00il_dataout <= nlOlO1OOO OR ((wire_niO01ill_w_lg_nlOOOi10i24752w(0) OR wire_w_lg_niOl00lil21194w(0)) OR (n1iO0l0O AND niOl00l0O)); + wire_nlOlO00l_dataout <= wire_nlll0lli_q(38) WHEN niOO00l1i = '1' ELSE wire_nlOO1OOi_dataout; + wire_nlOlO00O_dataout <= wire_nlll0lli_q(39) WHEN niOO00l1i = '1' ELSE wire_nlOO1OOl_dataout; + wire_nlOlO00Ol_dataout <= wire_nlOlO00OO_dataout OR (((n11O0Oil AND n1110OlO) AND wire_niO01ill_w_lg_n11Oi1il24747w(0)) OR (n11Oi11l AND n11O0Oil)); + wire_nlOlO00OO_dataout <= nlOlO011l AND NOT(niOl1iili); + wire_nlOlO010O_dataout <= wire_nlOlO0llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO01i_dataout <= wire_nlll0lli_q(34) WHEN niOO00l1i = '1' ELSE wire_nlOO1OiO_dataout; + wire_nlOlO01ii_dataout <= wire_nlOlO01Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO01il_dataout <= wire_nlOlO01lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO01iO_dataout <= wire_nlOlO00Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO01l_dataout <= wire_nlll0lli_q(35) WHEN niOO00l1i = '1' ELSE wire_nlOO1Oli_dataout; + wire_nlOlO01li_dataout <= wire_nlOlO0l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO01ll_dataout <= wire_nlOlO0l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO01lO_dataout <= nlOlO011i WHEN n11O0lii = '1' ELSE wire_nlOlO01OO_dataout; + wire_nlOlO01O_dataout <= wire_nlll0lli_q(36) WHEN niOO00l1i = '1' ELSE wire_nlOO1Oll_dataout; + wire_nlOlO01Oi_dataout <= wire_nlOlO00ii_dataout WHEN n11O0lii = '1' ELSE wire_nlOlO01Ol_dataout; + wire_nlOlO01Ol_dataout <= wire_nlOlO001l_dataout AND NOT(niOl1iiiO); + wire_nlOlO01OO_dataout <= wire_nlOlO001i_dataout OR niOl1iiiO; + wire_nlOlO0ii_dataout <= wire_nlll0lli_q(40) WHEN niOO00l1i = '1' ELSE wire_nlOO1OOO_dataout; + wire_nlOlO0il_dataout <= wire_nlll0lli_q(41) WHEN niOO00l1i = '1' ELSE wire_nlOO011i_dataout; + wire_nlOlO0iO_dataout <= wire_nlll0lli_q(42) WHEN niOO00l1i = '1' ELSE wire_nlOO011l_dataout; + wire_nlOlO0l0i_dataout <= nlOlO011O AND NOT(niOl1iill); + wire_nlOlO0l0l_dataout <= wire_nlOlO0l0O_dataout OR niOl1iill; + wire_nlOlO0l0O_dataout <= nlOlO010i AND n11O0Oil; + wire_nlOlO0l1l_dataout <= nlOlO010i WHEN niOl1iilO = '1' ELSE wire_nlOlO0l0l_dataout; + wire_nlOlO0l1O_dataout <= wire_nlOlO0l0i_dataout OR niOl1iilO; + wire_nlOlO0li_dataout <= wire_nlll0lli_q(43) WHEN niOO00l1i = '1' ELSE wire_nlOO011O_dataout; + wire_nlOlO0ll_dataout <= wire_nlll0lli_q(44) WHEN niOO00l1i = '1' ELSE wire_nlOO010i_dataout; + wire_nlOlO0llO_dataout <= wire_nlOlO0lOi_dataout OR (niOli1l1l AND wire_niO01ill_w_lg_nlOlO1l0i24728w(0)); + wire_nlOlO0lO_dataout <= wire_nlll0lli_q(45) WHEN niOO00l1i = '1' ELSE wire_nlOO010l_dataout; + wire_nlOlO0lOi_dataout <= nlOlO1l0i AND NOT(niOl1iiOi); + wire_nlOlO0O0i_dataout <= wire_nlOlO0O0l_dataout OR niOl00ili; + wire_nlOlO0O0l_dataout <= nlOlO010l OR (niOO10lOO AND wire_w_lg_niOl00lil21194w(0)); + wire_nlOlO0O1i_dataout <= wire_nlOlO0O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO0O1l_dataout <= wire_nlOlO0O1O_dataout AND n11O0iOl; + wire_nlOlO0O1O_dataout <= wire_nlOlO0O0i_dataout WHEN n1lillil = '1' ELSE nlOlO010l; + wire_nlOlO0Oi_dataout <= wire_nlll0lli_q(46) WHEN niOO00l1i = '1' ELSE wire_nlOO010O_dataout; + wire_nlOlO0Oii_dataout <= niil0liO WHEN n1101l1i = '1' ELSE wire_nlOlO0Oil_dataout; + wire_nlOlO0Oii_w_lg_dataout21224w(0) <= NOT wire_nlOlO0Oii_dataout; + wire_nlOlO0Oil_dataout <= niil0l1l WHEN n1101iOO = '1' ELSE wire_nlOlO0OiO_dataout; + wire_nlOlO0OiO_dataout <= niil01ii WHEN n1101iOl = '1' ELSE niil01il; + wire_nlOlO0Ol_dataout <= wire_nlll0lli_q(47) WHEN niOO00l1i = '1' ELSE wire_nlOO01ii_dataout; + wire_nlOlO0OO_dataout <= wire_nlll0lli_q(48) WHEN niOO00l1i = '1' ELSE wire_nlOO01il_dataout; + wire_nlOlO101i_dataout <= n1101lii WHEN niOl1ii1i = '1' ELSE nlOllOlOi; + wire_nlOlO101l_dataout <= n1101lil WHEN niOl1ii1i = '1' ELSE nlOllOlOl; + wire_nlOlO101O_dataout <= n1101liO WHEN niOl1ii1i = '1' ELSE nlOllOlOO; + wire_nlOlO10i_dataout <= wire_n1iOOOi_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0Oi_dataout; + wire_nlOlO10l_dataout <= wire_n1iOOOl_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0Ol_dataout; + wire_nlOlO10li_dataout <= wire_nlOlO10Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO10ll_dataout <= wire_nlOlO10Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO10lO_dataout <= wire_nlOlO10OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO10O_dataout <= wire_n1iOOOO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0OO_dataout; + wire_nlOlO10Oi_dataout <= wire_nlOlO1i1i_dataout AND NOT(n11O0lil); + wire_nlOlO10Ol_dataout <= wire_nlOlO1i1l_dataout AND NOT(n11O0lil); + wire_nlOlO10OO_dataout <= wire_nlOlO1i1O_dataout OR n11O0lil; + wire_nlOlO110i_dataout <= wire_niO01ill_w_lg_nlOOOl1lO24776w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO11lO_dataout; + wire_nlOlO110l_dataout <= wire_niO01ill_w_lg_nlOOOl1Oi24775w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO11Oi_dataout; + wire_nlOlO110O_dataout <= wire_niO01ill_w_lg_nlOOOl1Ol24774w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO11Ol_dataout; + wire_nlOlO111i_dataout <= wire_niO01ill_w_lg_nlOOOl01l24771w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO11iO_dataout; + wire_nlOlO111l_dataout <= wire_niO01ill_w_lg_nlOOOl01O24770w(0) WHEN niOl1ii1O = '1' ELSE wire_nlOlO11li_dataout; + wire_nlOlO111O_dataout <= wire_niO01ill_w_lg_nlOOOl1ll24777w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO11ll_dataout; + wire_nlOlO11i_dataout <= wire_n1iOOli_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0li_dataout; + wire_nlOlO11ii_dataout <= wire_niO01ill_w_lg_nlOOOl1OO24773w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO11OO_dataout; + wire_nlOlO11il_dataout <= wire_niO01ill_w_lg_nlOOOl01i24772w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO101i_dataout; + wire_nlOlO11iO_dataout <= wire_niO01ill_w_lg_nlOOOl01l24771w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO101l_dataout; + wire_nlOlO11l_dataout <= wire_n1iOOll_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0ll_dataout; + wire_nlOlO11li_dataout <= wire_niO01ill_w_lg_nlOOOl01O24770w(0) WHEN niOl1ii1l = '1' ELSE wire_nlOlO101O_dataout; + wire_nlOlO11ll_dataout <= n1101l1l WHEN niOl1ii1i = '1' ELSE nlOllO0iO; + wire_nlOlO11lO_dataout <= n1101l1O WHEN niOl1ii1i = '1' ELSE nlOllOliO; + wire_nlOlO11O_dataout <= wire_n1iOOlO_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOl0lO_dataout; + wire_nlOlO11Oi_dataout <= n1101l0i WHEN niOl1ii1i = '1' ELSE nlOllOlli; + wire_nlOlO11Ol_dataout <= n1101l0l WHEN niOl1ii1i = '1' ELSE nlOllOlll; + wire_nlOlO11OO_dataout <= n1101l0O WHEN niOl1ii1i = '1' ELSE nlOllOllO; + wire_nlOlO1i0i_dataout <= wire_nlOlO1iii_dataout OR niOl1ii0O; + wire_nlOlO1i0l_dataout <= wire_nlOlO1iil_dataout AND NOT(niOl1ii0O); + wire_nlOlO1i0O_dataout <= wire_nlOlO1iil_dataout OR niOl1ii0O; + wire_nlOlO1i1i_dataout <= wire_nlOlO1i0i_dataout OR n11O0lll; + wire_nlOlO1i1l_dataout <= wire_nlOlO1i0l_dataout AND NOT(n11O0lll); + wire_nlOlO1i1O_dataout <= wire_nlOlO1i0O_dataout OR n11O0lll; + wire_nlOlO1ii_dataout <= wire_n1l111i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOli1i_dataout; + wire_nlOlO1iii_dataout <= niOl1ii0i AND NOT(niOl1ii0l); + wire_nlOlO1iil_dataout <= niOl1ii0i OR niOl1ii0l; + wire_nlOlO1il_dataout <= wire_n1l111l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOli1l_dataout; + wire_nlOlO1iO_dataout <= wire_n1l111O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOli1O_dataout; + wire_nlOlO1l0l_dataout <= wire_nlOlO1lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1l0O_dataout <= wire_nlOlO1lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1li_dataout <= wire_n1l110i_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOli0i_dataout; + wire_nlOlO1lii_dataout <= wire_nlOlO1lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1lil_dataout <= wire_nlOlO1O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1liO_dataout <= wire_nlOlO1O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1ll_dataout <= wire_n1l110l_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOli0l_dataout; + wire_nlOlO1lli_dataout <= wire_nlOlO1O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1lll_dataout <= wire_nlOlO1O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1llO_dataout <= wire_nlOlO1O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlO1lO_dataout <= wire_n1l110O_dataout WHEN niOO00l1i = '1' ELSE wire_nlOOli0O_dataout; + wire_nlOlO1lOi_dataout <= wire_nlOlO1O0O_dataout AND NOT(n11O0Oil); + wire_nlOlO1lOl_dataout <= wire_nlOlO1Oii_dataout AND NOT(n11O0Oil); + wire_nlOlO1lOO_dataout <= wire_nlOlO1Oil_dataout AND NOT(n11O0Oil); + wire_nlOlO1O0i_dataout <= wire_nlOlO1OlO_dataout AND NOT(n11O0Oil); + wire_nlOlO1O0l_dataout <= wire_nlOlO1OOi_dataout AND NOT(n11O0Oil); + wire_nlOlO1O0O_dataout <= n1Oi1O1O WHEN niOl1iiii = '1' ELSE nlOlO10iO; + wire_nlOlO1O1i_dataout <= wire_nlOlO1OiO_dataout AND NOT(n11O0Oil); + wire_nlOlO1O1l_dataout <= wire_nlOlO1Oli_dataout AND NOT(n11O0Oil); + wire_nlOlO1O1O_dataout <= wire_nlOlO1Oll_dataout AND NOT(n11O0Oil); + wire_nlOlO1Oi_dataout <= wire_nlOOil1i_dataout AND NOT(niOO00l1i); + wire_nlOlO1Oii_dataout <= n011liii WHEN niOl1iiii = '1' ELSE nlOlO1ilO; + wire_nlOlO1Oil_dataout <= n01O01ll WHEN niOl1iiii = '1' ELSE nlOlO1iOi; + wire_nlOlO1OiO_dataout <= n00illOO WHEN niOl1iiii = '1' ELSE nlOlO1iOl; + wire_nlOlO1Ol_dataout <= wire_nlll0lli_q(32) WHEN niOO00l1i = '1' ELSE wire_nlOO1Oii_dataout; + wire_nlOlO1Oli_dataout <= n0i00i0i WHEN niOl1iiii = '1' ELSE nlOlO1iOO; + wire_nlOlO1Oll_dataout <= n0iOO1il WHEN niOl1iiii = '1' ELSE nlOlO1l1i; + wire_nlOlO1OlO_dataout <= n0ll0llO WHEN niOl1iiii = '1' ELSE nlOlO1l1l; + wire_nlOlO1OO_dataout <= wire_nlll0lli_q(33) WHEN niOO00l1i = '1' ELSE wire_nlOO1Oil_dataout; + wire_nlOlO1OOi_dataout <= n0O0Oi1i WHEN niOl1iiii = '1' ELSE nlOlO1l1O; + wire_nlOlOi00O_dataout <= wire_nlOlOi0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0i_dataout <= wire_nlll0lli_q(52) WHEN niOO00l1i = '1' ELSE wire_nlOO01lO_dataout; + wire_nlOlOi0ii_dataout <= wire_nlOlOi0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0il_dataout <= wire_nlOlOii1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0iO_dataout <= wire_nlOlOii1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0l_dataout <= wire_nlll0lli_q(53) WHEN niOO00l1i = '1' ELSE wire_nlOO01Oi_dataout; + wire_nlOlOi0li_dataout <= wire_nlOlOii1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0ll_dataout <= wire_nlOlOii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0lO_dataout <= wire_nlOlOii0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0O_dataout <= wire_nlll0lli_q(54) WHEN niOO00l1i = '1' ELSE wire_nlOO01Ol_dataout; + wire_nlOlOi0Oi_dataout <= wire_nlOlOii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOi0Ol_dataout <= wire_niil0lOO_dataout WHEN niOl001OO = '1' ELSE nlOlO0lOO; + wire_nlOlOi0OO_dataout <= wire_niil0O1i_dataout WHEN niOl001OO = '1' ELSE nlOlOi1Oi; + wire_nlOlOi10l_dataout <= nlOlO0lOO AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi10l_w_lg_dataout26817w(0) <= NOT wire_nlOlOi10l_dataout; + wire_nlOlOi10O_dataout <= nlOlOi1Oi AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi10O_w_lg_dataout26844w(0) <= NOT wire_nlOlOi10O_dataout; + wire_nlOlOi1i_dataout <= wire_nlll0lli_q(49) WHEN niOO00l1i = '1' ELSE wire_nlOO01iO_dataout; + wire_nlOlOi1ii_dataout <= nlOlOi1Ol AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi1ii_w_lg_dataout26814w(0) <= NOT wire_nlOlOi1ii_dataout; + wire_nlOlOi1il_dataout <= nlOlOi1OO AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi1il_w_lg_dataout26812w(0) <= NOT wire_nlOlOi1il_dataout; + wire_nlOlOi1iO_dataout <= nlOlOi01i AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi1iO_w_lg_dataout26810w(0) <= NOT wire_nlOlOi1iO_dataout; + wire_nlOlOi1l_dataout <= wire_nlll0lli_q(50) WHEN niOO00l1i = '1' ELSE wire_nlOO01li_dataout; + wire_nlOlOi1li_dataout <= nlOlOi01l AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi1li_w_lg_dataout26808w(0) <= NOT wire_nlOlOi1li_dataout; + wire_nlOlOi1ll_dataout <= nlOlOi01O AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi1ll_w_lg_dataout26806w(0) <= NOT wire_nlOlOi1ll_dataout; + wire_nlOlOi1lO_dataout <= nlOlOi00i AND wire_nlOii0Oii_w_lg_dataout21042w(0); + wire_nlOlOi1lO_w_lg_dataout26804w(0) <= NOT wire_nlOlOi1lO_dataout; + wire_nlOlOi1O_dataout <= wire_nlll0lli_q(51) WHEN niOO00l1i = '1' ELSE wire_nlOO01ll_dataout; + wire_nlOlOii0i_dataout <= wire_niil0O0l_dataout WHEN niOl001OO = '1' ELSE nlOlOi01l; + wire_nlOlOii0l_dataout <= wire_niil0O0O_dataout WHEN niOl001OO = '1' ELSE nlOlOi01O; + wire_nlOlOii0O_dataout <= wire_niil0Oii_dataout WHEN niOl001OO = '1' ELSE nlOlOi00i; + wire_nlOlOii1i_dataout <= wire_niil0O1l_dataout WHEN niOl001OO = '1' ELSE nlOlOi1Ol; + wire_nlOlOii1l_dataout <= wire_niil0O1O_dataout WHEN niOl001OO = '1' ELSE nlOlOi1OO; + wire_nlOlOii1O_dataout <= wire_niil0O0i_dataout WHEN niOl001OO = '1' ELSE nlOlOi01i; + wire_nlOlOiii_dataout <= wire_nlll0lli_q(55) WHEN niOO00l1i = '1' ELSE wire_nlOO01OO_dataout; + wire_nlOlOiil_dataout <= wire_nlll0lli_q(56) WHEN niOO00l1i = '1' ELSE wire_nlOO001i_dataout; + wire_nlOlOiiO_dataout <= wire_nlll0lli_q(57) WHEN niOO00l1i = '1' ELSE wire_nlOO001l_dataout; + wire_nlOlOili_dataout <= wire_nlll0lli_q(58) WHEN niOO00l1i = '1' ELSE wire_nlOO001O_dataout; + wire_nlOlOill_dataout <= wire_nlll0lli_q(59) WHEN niOO00l1i = '1' ELSE wire_nlOO000i_dataout; + wire_nlOlOilO_dataout <= wire_nlll0lli_q(60) WHEN niOO00l1i = '1' ELSE wire_nlOO000l_dataout; + wire_nlOlOiO0i_dataout <= wire_nlOlOl01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiO0l_dataout <= wire_nlOlOl01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiO0O_dataout <= wire_nlOlOl01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOi_dataout <= wire_nlll0lli_q(61) WHEN niOO00l1i = '1' ELSE wire_nlOO000O_dataout; + wire_nlOlOiOii_dataout <= wire_nlOlOl00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOil_dataout <= wire_nlOlOl00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOiO_dataout <= wire_nlOlOl00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOl_dataout <= wire_nlll0lli_q(62) WHEN niOO00l1i = '1' ELSE wire_nlOO00ii_dataout; + wire_nlOlOiOli_dataout <= wire_nlOlOl0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOll_dataout <= wire_nlOlOl0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOlO_dataout <= wire_nlOO10Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOO_dataout <= wire_nlll0lli_q(63) WHEN niOO00l1i = '1' ELSE wire_nlOO00il_dataout; + wire_nlOlOiOOi_dataout <= wire_nlOlOl1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOOl_dataout <= nlOlOilOl AND NOT(wire_niO01lOO_dataout); + wire_nlOlOiOOO_dataout <= nlOlOilOO OR wire_niO01lOO_dataout; + wire_nlOlOl00i_dataout <= wire_nlOO1011O_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOli1i_dataout; + wire_nlOlOl00l_dataout <= wire_nlOO1010i_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOli1l_dataout; + wire_nlOlOl00O_dataout <= wire_nlOO1010l_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOli1O_dataout; + wire_nlOlOl01i_dataout <= wire_nlOO11OOO_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOl0Oi_dataout; + wire_nlOlOl01l_dataout <= wire_nlOO1011i_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOl0Ol_dataout; + wire_nlOlOl01O_dataout <= wire_nlOO1011l_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOl0OO_dataout; + wire_nlOlOl0i_dataout <= wire_nlll0lli_q(3) WHEN niOO00l1i = '1' ELSE wire_nlOO00lO_dataout; + wire_nlOlOl0ii_dataout <= wire_nlOO1010O_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOli0i_dataout; + wire_nlOlOl0il_dataout <= wire_nlOO101ii_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOli0l_dataout; + wire_nlOlOl0iO_dataout <= wire_nlOO101il_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOli0O_dataout; + wire_nlOlOl0l_dataout <= wire_nlll0lli_q(4) WHEN niOO00l1i = '1' ELSE wire_nlOO00Oi_dataout; + wire_nlOlOl0li_dataout <= wire_nlOO101iO_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOliii_dataout; + wire_nlOlOl0ll_dataout <= wire_nlOO101li_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOliil_dataout; + wire_nlOlOl0lO_dataout <= wire_nlOO101ll_dataout WHEN n11O0Oil = '1' ELSE wire_nlOlOliiO_dataout; + wire_nlOlOl0O_dataout <= wire_nlll0lli_q(5) WHEN niOO00l1i = '1' ELSE wire_nlOO00Ol_dataout; + wire_nlOlOl0Oi_dataout <= wire_nlOO11ill_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOlili_dataout; + wire_nlOlOl0Ol_dataout <= wire_nlOO11ilO_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOlill_dataout; + wire_nlOlOl0OO_dataout <= wire_nlOO11iOi_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOlilO_dataout; + wire_nlOlOl10i_dataout <= wire_nlOlOl0li_dataout OR wire_niO01lOO_dataout; + wire_nlOlOl10l_dataout <= wire_nlOlOl0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOl10O_dataout <= wire_nlOlOl0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOl11i_dataout <= nlOlOiO1i AND NOT(wire_niO01lOO_dataout); + wire_nlOlOl11l_dataout <= nlOlOiO1l AND NOT(wire_niO01lOO_dataout); + wire_nlOlOl11O_dataout <= wire_nlOlOl0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOlOl1i_dataout <= wire_nlll0lli_q(0) WHEN niOO00l1i = '1' ELSE wire_nlOO00iO_dataout; + wire_nlOlOl1ii_dataout <= wire_nlOlOl1il_dataout AND niOl0011O; + wire_nlOlOl1il_dataout <= nlOlOiliO OR ((((((nlOlOilOl XOR nlOlOilli) OR (nlOlOilOO XOR nlOlOilll)) OR (nlOlOiO1i XOR nlOlOillO)) OR (nlOlOiO1l XOR nlOlOilOi)) AND wire_niO01ill_w_lg_nlOlOilOl24719w(0)) AND wire_niO01ill_w_lg_nlOlOilli24721w(0)); + wire_nlOlOl1l_dataout <= wire_nlll0lli_q(1) WHEN niOO00l1i = '1' ELSE wire_nlOO00li_dataout; + wire_nlOlOl1O_dataout <= wire_nlll0lli_q(2) WHEN niOO00l1i = '1' ELSE wire_nlOO00ll_dataout; + wire_nlOlOli0i_dataout <= wire_nlOO11l1l_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOll1i_dataout; + wire_nlOlOli0l_dataout <= wire_nlOO11l1O_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOll1l_dataout; + wire_nlOlOli0O_dataout <= wire_nlOO11l0i_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOll1O_dataout; + wire_nlOlOli1i_dataout <= wire_nlOO11iOl_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOliOi_dataout; + wire_nlOlOli1l_dataout <= wire_nlOO11iOO_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOliOl_dataout; + wire_nlOlOli1O_dataout <= wire_nlOO11l1i_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOliOO_dataout; + wire_nlOlOlii_dataout <= wire_nlll0lli_q(6) WHEN niOO00l1i = '1' ELSE wire_nlOO00OO_dataout; + wire_nlOlOliii_dataout <= wire_nlOO11l0l_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOll0i_dataout; + wire_nlOlOliil_dataout <= wire_nlOO11l0O_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOll0l_dataout; + wire_nlOlOliiO_dataout <= wire_nlOO11lii_dataout WHEN n11O0lii = '1' ELSE wire_nlOlOll0O_dataout; + wire_nlOlOlil_dataout <= wire_nlll0lli_q(7) WHEN niOO00l1i = '1' ELSE wire_nlOO0i1i_dataout; + wire_nlOlOlili_dataout <= nlOlOi00l WHEN niOl1il0O = '1' ELSE wire_nlOlOllii_dataout; + wire_nlOlOlill_dataout <= nlOlOil1i WHEN niOl1il0O = '1' ELSE wire_nlOlOllil_dataout; + wire_nlOlOlilO_dataout <= nlOlOil1l WHEN niOl1il0O = '1' ELSE wire_nlOlOlliO_dataout; + wire_nlOlOliO_dataout <= wire_nlll0lli_q(8) WHEN niOO00l1i = '1' ELSE wire_nlOO0i1l_dataout; + wire_nlOlOliOi_dataout <= nlOlOil1O WHEN niOl1il0O = '1' ELSE wire_nlOlOllli_dataout; + wire_nlOlOliOl_dataout <= nlOlOil0i WHEN niOl1il0O = '1' ELSE wire_nlOlOllll_dataout; + wire_nlOlOliOO_dataout <= nlOlOil0l WHEN niOl1il0O = '1' ELSE wire_nlOlOlllO_dataout; + wire_nlOlOll0i_dataout <= wire_nlOO11i0O_dataout WHEN niOl1il0O = '1' ELSE wire_nlOlOlO1i_dataout; + wire_nlOlOll0l_dataout <= wire_nlOO11iii_dataout WHEN niOl1il0O = '1' ELSE wire_nlOlOlO1l_dataout; + wire_nlOlOll0O_dataout <= wire_nlOO11iil_dataout WHEN niOl1il0O = '1' ELSE wire_nlOlOlO1O_dataout; + wire_nlOlOll1i_dataout <= nlOlOil0O WHEN niOl1il0O = '1' ELSE wire_nlOlOllOi_dataout; + wire_nlOlOll1l_dataout <= nlOlOilii WHEN niOl1il0O = '1' ELSE wire_nlOlOllOl_dataout; + wire_nlOlOll1O_dataout <= wire_nlOO11i0l_dataout WHEN niOl1il0O = '1' ELSE wire_nlOlOllOO_dataout; + wire_nlOlOlli_dataout <= wire_nlll0lli_q(9) WHEN niOO00l1i = '1' ELSE wire_nlOO0i1O_dataout; + wire_nlOlOllii_dataout <= nlOlOi00l WHEN n11O0Oii = '1' ELSE wire_nlOlOlO0i_dataout; + wire_nlOlOllil_dataout <= nlOlOil1i WHEN n11O0Oii = '1' ELSE wire_nlOlOlO0l_dataout; + wire_nlOlOlliO_dataout <= nlOlOil1l WHEN n11O0Oii = '1' ELSE wire_nlOlOlO0O_dataout; + wire_nlOlOlll_dataout <= wire_nlll0lli_q(10) WHEN niOO00l1i = '1' ELSE wire_nlOO0i0i_dataout; + wire_nlOlOllli_dataout <= nlOlOil1O WHEN n11O0Oii = '1' ELSE wire_nlOlOlOii_dataout; + wire_nlOlOllll_dataout <= nlOlOil0i WHEN n11O0Oii = '1' ELSE wire_nlOlOlOil_dataout; + wire_nlOlOlllO_dataout <= nlOlOil0l WHEN n11O0Oii = '1' ELSE wire_nlOlOlOiO_dataout; + wire_nlOlOllO_dataout <= wire_nlll0lli_q(11) WHEN niOO00l1i = '1' ELSE wire_nlOO0i0l_dataout; + wire_nlOlOllOi_dataout <= nlOlOil0O WHEN n11O0Oii = '1' ELSE wire_nlOlOlOli_dataout; + wire_nlOlOllOl_dataout <= nlOlOilii WHEN n11O0Oii = '1' ELSE wire_nlOlOlOll_dataout; + wire_nlOlOllOO_dataout <= wire_nlOO111OO_dataout WHEN n11O0Oii = '1' ELSE wire_nlOlOlOlO_dataout; + wire_nlOlOlO0i_dataout <= nlOlOi00l WHEN n11O0l1i = '1' ELSE wire_nlOlOO11i_dataout; + wire_nlOlOlO0l_dataout <= nlOlOil1i WHEN n11O0l1i = '1' ELSE wire_nlOlOO11l_dataout; + wire_nlOlOlO0O_dataout <= nlOlOil1l WHEN n11O0l1i = '1' ELSE wire_nlOlOO11O_dataout; + wire_nlOlOlO1i_dataout <= wire_nlOO1101i_dataout WHEN n11O0Oii = '1' ELSE wire_nlOlOlOOi_dataout; + wire_nlOlOlO1l_dataout <= wire_nlOO1101l_dataout WHEN n11O0Oii = '1' ELSE wire_nlOlOlOOl_dataout; + wire_nlOlOlO1O_dataout <= wire_nlOO1101O_dataout WHEN n11O0Oii = '1' ELSE wire_nlOlOlOOO_dataout; + wire_nlOlOlOi_dataout <= wire_nlll0lli_q(12) WHEN niOO00l1i = '1' ELSE wire_nlOO0i0O_dataout; + wire_nlOlOlOii_dataout <= nlOlOil1O WHEN n11O0l1i = '1' ELSE wire_nlOlOO10i_dataout; + wire_nlOlOlOil_dataout <= nlOlOil0i WHEN n11O0l1i = '1' ELSE wire_nlOlOO10l_dataout; + wire_nlOlOlOiO_dataout <= nlOlOil0l WHEN n11O0l1i = '1' ELSE wire_nlOlOO10O_dataout; + wire_nlOlOlOl_dataout <= wire_nlll0lli_q(13) WHEN niOO00l1i = '1' ELSE wire_nlOO0iii_dataout; + wire_nlOlOlOli_dataout <= nlOlOil0O WHEN n11O0l1i = '1' ELSE wire_nlOlOO1ii_dataout; + wire_nlOlOlOll_dataout <= nlOlOilii WHEN n11O0l1i = '1' ELSE wire_nlOlOO1il_dataout; + wire_nlOlOlOlO_dataout <= wire_nlOO111Oi_dataout WHEN n11O0l1i = '1' ELSE wire_nlOlOO1iO_dataout; + wire_nlOlOlOO_dataout <= wire_nlll0lli_q(14) WHEN niOO00l1i = '1' ELSE wire_nlOO0iil_dataout; + wire_nlOlOlOOi_dataout <= wire_nlOO111Ol_dataout WHEN n11O0l1i = '1' ELSE wire_nlOlOO1li_dataout; + wire_nlOlOlOOl_dataout <= wire_nlOO1110i_dataout WHEN n11O0l1i = '1' ELSE wire_nlOlOO1ll_dataout; + wire_nlOlOlOOO_dataout <= wire_nlOO1110l_dataout WHEN n11O0l1i = '1' ELSE wire_nlOlOO1lO_dataout; + wire_nlOlOO00i_dataout <= nlOlOil0O WHEN n11O0iOl = '1' ELSE wire_nlOlOOi1i_dataout; + wire_nlOlOO00l_dataout <= nlOlOilii WHEN n11O0iOl = '1' ELSE wire_nlOlOOi1l_dataout; + wire_nlOlOO00O_dataout <= wire_nlOO1111l_dataout WHEN n11O0iOl = '1' ELSE wire_nlOlOOi1O_dataout; + wire_nlOlOO01i_dataout <= nlOlOil1O WHEN n11O0iOl = '1' ELSE wire_nlOlOO0Oi_dataout; + wire_nlOlOO01l_dataout <= nlOlOil0i WHEN n11O0iOl = '1' ELSE wire_nlOlOO0Ol_dataout; + wire_nlOlOO01O_dataout <= nlOlOil0l WHEN n11O0iOl = '1' ELSE wire_nlOlOO0OO_dataout; + wire_nlOlOO0i_dataout <= wire_nlll0lli_q(18) WHEN niOO00l1i = '1' ELSE wire_nlOO0ilO_dataout; + wire_nlOlOO0ii_dataout <= wire_nlOO1111O_dataout WHEN n11O0iOl = '1' ELSE wire_nlOlOOi0i_dataout; + wire_nlOlOO0il_dataout <= wire_nlOO1110i_dataout WHEN n11O0iOl = '1' ELSE wire_nlOlOOi0l_dataout; + wire_nlOlOO0iO_dataout <= wire_nlOO1110l_dataout WHEN n11O0iOl = '1' ELSE wire_nlOlOOi0O_dataout; + wire_nlOlOO0l_dataout <= wire_nlll0lli_q(19) WHEN niOO00l1i = '1' ELSE wire_nlOO0iOi_dataout; + wire_nlOlOO0li_dataout <= nlOlOi00l WHEN niOl1il1O = '1' ELSE wire_nlOlOOiii_dataout; + wire_nlOlOO0ll_dataout <= nlOlOil1i WHEN niOl1il1O = '1' ELSE wire_nlOlOOiil_dataout; + wire_nlOlOO0lO_dataout <= nlOlOil1l WHEN niOl1il1O = '1' ELSE wire_nlOlOOiiO_dataout; + wire_nlOlOO0O_dataout <= wire_nlll0lli_q(20) WHEN niOO00l1i = '1' ELSE wire_nlOO0iOl_dataout; + wire_nlOlOO0Oi_dataout <= nlOlOil1O WHEN niOl1il1O = '1' ELSE wire_nlOlOOili_dataout; + wire_nlOlOO0Ol_dataout <= nlOlOil0i WHEN niOl1il1O = '1' ELSE wire_nlOlOOill_dataout; + wire_nlOlOO0OO_dataout <= nlOlOil0l WHEN niOl1il1O = '1' ELSE wire_nlOlOOilO_dataout; + wire_nlOlOO10i_dataout <= nlOlOil1O WHEN n11O0iOO = '1' ELSE wire_nlOlOO01i_dataout; + wire_nlOlOO10l_dataout <= nlOlOil0i WHEN n11O0iOO = '1' ELSE wire_nlOlOO01l_dataout; + wire_nlOlOO10O_dataout <= nlOlOil0l WHEN n11O0iOO = '1' ELSE wire_nlOlOO01O_dataout; + wire_nlOlOO11i_dataout <= nlOlOi00l WHEN n11O0iOO = '1' ELSE wire_nlOlOO1Oi_dataout; + wire_nlOlOO11l_dataout <= nlOlOil1i WHEN n11O0iOO = '1' ELSE wire_nlOlOO1Ol_dataout; + wire_nlOlOO11O_dataout <= nlOlOil1l WHEN n11O0iOO = '1' ELSE wire_nlOlOO1OO_dataout; + wire_nlOlOO1i_dataout <= wire_nlll0lli_q(15) WHEN niOO00l1i = '1' ELSE wire_nlOO0iiO_dataout; + wire_nlOlOO1ii_dataout <= nlOlOil0O WHEN n11O0iOO = '1' ELSE wire_nlOlOO00i_dataout; + wire_nlOlOO1il_dataout <= nlOlOilii WHEN n11O0iOO = '1' ELSE wire_nlOlOO00l_dataout; + wire_nlOlOO1iO_dataout <= wire_nlOO1110O_dataout WHEN n11O0iOO = '1' ELSE wire_nlOlOO00O_dataout; + wire_nlOlOO1l_dataout <= wire_nlll0lli_q(16) WHEN niOO00l1i = '1' ELSE wire_nlOO0ili_dataout; + wire_nlOlOO1li_dataout <= wire_nlOO111ii_dataout WHEN n11O0iOO = '1' ELSE wire_nlOlOO0ii_dataout; + wire_nlOlOO1ll_dataout <= wire_nlOO111il_dataout WHEN n11O0iOO = '1' ELSE wire_nlOlOO0il_dataout; + wire_nlOlOO1lO_dataout <= wire_nlOO111iO_dataout WHEN n11O0iOO = '1' ELSE wire_nlOlOO0iO_dataout; + wire_nlOlOO1O_dataout <= wire_nlll0lli_q(17) WHEN niOO00l1i = '1' ELSE wire_nlOO0ill_dataout; + wire_nlOlOO1Oi_dataout <= nlOlOi00l WHEN n11O0iOl = '1' ELSE wire_nlOlOO0li_dataout; + wire_nlOlOO1Ol_dataout <= nlOlOil1i WHEN n11O0iOl = '1' ELSE wire_nlOlOO0ll_dataout; + wire_nlOlOO1OO_dataout <= nlOlOil1l WHEN n11O0iOl = '1' ELSE wire_nlOlOO0lO_dataout; + wire_nlOlOOi0i_dataout <= wire_nlOlOOl1i_dataout AND NOT(niOl1il1O); + wire_nlOlOOi0l_dataout <= wire_nlOlOOl1l_dataout AND NOT(niOl1il1O); + wire_nlOlOOi0O_dataout <= wire_nlOlOOl1O_dataout OR niOl1il1O; + wire_nlOlOOi1i_dataout <= nlOlOil0O WHEN niOl1il1O = '1' ELSE wire_nlOlOOiOi_dataout; + wire_nlOlOOi1l_dataout <= nlOlOilii WHEN niOl1il1O = '1' ELSE wire_nlOlOOiOl_dataout; + wire_nlOlOOi1O_dataout <= wire_nlOlOOiOO_dataout AND NOT(niOl1il1O); + wire_nlOlOOii_dataout <= wire_nlll0lli_q(21) WHEN niOO00l1i = '1' ELSE wire_nlOO0iOO_dataout; + wire_nlOlOOiii_dataout <= wire_nlOlOOl0i_dataout WHEN niOl1il1i = '1' ELSE nlOlOi00l; + wire_nlOlOOiil_dataout <= wire_nlOlOOl0l_dataout WHEN niOl1il1i = '1' ELSE nlOlOil1i; + wire_nlOlOOiiO_dataout <= wire_nlOlOOl0O_dataout WHEN niOl1il1i = '1' ELSE nlOlOil1l; + wire_nlOlOOil_dataout <= wire_nlll0lli_q(22) WHEN niOO00l1i = '1' ELSE wire_nlOO0l1i_dataout; + wire_nlOlOOili_dataout <= wire_nlOlOOlii_dataout WHEN niOl1il1i = '1' ELSE nlOlOil1O; + wire_nlOlOOill_dataout <= wire_nlOlOOlil_dataout WHEN niOl1il1i = '1' ELSE nlOlOil0i; + wire_nlOlOOilO_dataout <= wire_nlOlOOliO_dataout WHEN niOl1il1i = '1' ELSE nlOlOil0l; + wire_nlOlOOiO_dataout <= wire_nlll0lli_q(23) WHEN niOO00l1i = '1' ELSE wire_nlOO0l1l_dataout; + wire_nlOlOOiOi_dataout <= wire_nlOlOOlli_dataout WHEN niOl1il1i = '1' ELSE nlOlOil0O; + wire_nlOlOOiOl_dataout <= wire_nlOlOOlll_dataout WHEN niOl1il1i = '1' ELSE nlOlOilii; + wire_nlOlOOiOO_dataout <= wire_nlOlOOllO_dataout WHEN niOl1il1i = '1' ELSE nlOlOilOl; + wire_nlOlOOl0i_dataout <= wire_nlOlOOO1i_dataout AND NOT(niOl1iiOO); + wire_nlOlOOl0l_dataout <= wire_nlOlOOO1l_dataout AND NOT(niOl1iiOO); + wire_nlOlOOl0O_dataout <= wire_nlOlOOO1O_dataout AND NOT(niOl1iiOO); + wire_nlOlOOl1i_dataout <= wire_nlOlOOlOi_dataout WHEN niOl1il1i = '1' ELSE nlOlOilOO; + wire_nlOlOOl1l_dataout <= wire_nlOlOOlOl_dataout WHEN niOl1il1i = '1' ELSE nlOlOiO1i; + wire_nlOlOOl1O_dataout <= wire_nlOlOOlOO_dataout WHEN niOl1il1i = '1' ELSE nlOlOiO1l; + wire_nlOlOOli_dataout <= wire_nlll0lli_q(24) WHEN niOO00l1i = '1' ELSE wire_nlOO0l1O_dataout; + wire_nlOlOOlii_dataout <= wire_nlOlOOO0i_dataout AND NOT(niOl1iiOO); + wire_nlOlOOlil_dataout <= wire_nlOlOOO0l_dataout AND NOT(niOl1iiOO); + wire_nlOlOOliO_dataout <= wire_nlOlOOO0O_dataout AND NOT(niOl1iiOO); + wire_nlOlOOll_dataout <= wire_nlll0lli_q(25) WHEN niOO00l1i = '1' ELSE wire_nlOO0l0i_dataout; + wire_nlOlOOlli_dataout <= wire_nlOlOOOii_dataout AND NOT(niOl1iiOO); + wire_nlOlOOlll_dataout <= wire_nlOlOOOil_dataout AND NOT(niOl1iiOO); + wire_nlOlOOllO_dataout <= nlOlOilOl AND NOT(niOl1iiOO); + wire_nlOlOOlO_dataout <= wire_nlll0lli_q(26) WHEN niOO00l1i = '1' ELSE wire_nlOO0l0l_dataout; + wire_nlOlOOlOi_dataout <= nlOlOilOO AND NOT(niOl1iiOO); + wire_nlOlOOlOl_dataout <= nlOlOiO1i OR niOl1iiOO; + wire_nlOlOOlOO_dataout <= nlOlOiO1l AND NOT(niOl1iiOO); + wire_nlOlOOO0i_dataout <= wire_nlOlOOOiO_o(3) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOil1O; + wire_nlOlOOO0l_dataout <= wire_nlOlOOOiO_o(4) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOil0i; + wire_nlOlOOO0O_dataout <= wire_nlOlOOOiO_o(5) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOil0l; + wire_nlOlOOO1i_dataout <= wire_nlOlOOOiO_o(0) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOi00l; + wire_nlOlOOO1l_dataout <= wire_nlOlOOOiO_o(1) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOil1i; + wire_nlOlOOO1O_dataout <= wire_nlOlOOOiO_o(2) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOil1l; + wire_nlOlOOOi_dataout <= wire_nlll0lli_q(27) WHEN niOO00l1i = '1' ELSE wire_nlOO0l0O_dataout; + wire_nlOlOOOii_dataout <= wire_nlOlOOOiO_o(6) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOil0O; + wire_nlOlOOOil_dataout <= wire_nlOlOOOiO_o(7) WHEN wire_niO01ill_w_lg_nlOlOiO1i24684w(0) = '1' ELSE nlOlOilii; + wire_nlOlOOOl_dataout <= wire_nlll0lli_q(28) WHEN niOO00l1i = '1' ELSE wire_nlOO0lii_dataout; + wire_nlOlOOOO_dataout <= wire_nlll0lli_q(29) WHEN niOO00l1i = '1' ELSE wire_nlOO0lil_dataout; + wire_nlOO000i_dataout <= wire_n100lli_dataout WHEN niOO00iOl = '1' ELSE nlOii1il; + wire_nlOO000l_dataout <= wire_n100lll_dataout WHEN niOO00iOl = '1' ELSE nlOii1iO; + wire_nlOO000O_dataout <= wire_n100llO_dataout WHEN niOO00iOl = '1' ELSE nlOii1li; + wire_nlOO001i_dataout <= wire_n100lii_dataout WHEN niOO00iOl = '1' ELSE nlOii10l; + wire_nlOO001l_dataout <= wire_n100lil_dataout WHEN niOO00iOl = '1' ELSE nlOii10O; + wire_nlOO001O_dataout <= wire_n100liO_dataout WHEN niOO00iOl = '1' ELSE nlOii1ii; + wire_nlOO00ii_dataout <= wire_n100lOi_dataout WHEN niOO00iOl = '1' ELSE nlOii1ll; + wire_nlOO00il_dataout <= wire_n100lOl_dataout WHEN niOO00iOl = '1' ELSE nlOii1lO; + wire_nlOO00iO_dataout <= wire_n100lOO_dataout WHEN niOO00iOl = '1' ELSE nlOii1Oi; + wire_nlOO00li_dataout <= wire_n100O1i_dataout WHEN niOO00iOl = '1' ELSE nlOii1Ol; + wire_nlOO00ll_dataout <= wire_n100O1l_dataout WHEN niOO00iOl = '1' ELSE nlOii1OO; + wire_nlOO00lO_dataout <= wire_n100O1O_dataout WHEN niOO00iOl = '1' ELSE nlOii01i; + wire_nlOO00Oi_dataout <= wire_n100O0i_dataout WHEN niOO00iOl = '1' ELSE nlOii01l; + wire_nlOO00Ol_dataout <= wire_n100O0l_dataout WHEN niOO00iOl = '1' ELSE nlOii01O; + wire_nlOO00OO_dataout <= wire_n100O0O_dataout WHEN niOO00iOl = '1' ELSE nlOii00i; + wire_nlOO0101i_dataout <= nlOO1O1lO AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO0101l_dataout <= nlOO1O1Ol OR wire_w_lg_niOl0iOOO20933w(0); + wire_nlOO010i_dataout <= wire_n100ili_dataout WHEN niOO00iOl = '1' ELSE nlOi0Oil; + wire_nlOO010l_dataout <= wire_n100ill_dataout WHEN niOO00iOl = '1' ELSE nlOi0OiO; + wire_nlOO010O_dataout <= wire_n100ilO_dataout WHEN niOO00iOl = '1' ELSE nlOi0Oli; + wire_nlOO0110i_dataout <= nlOO1O1iO WHEN niOl1l11l = '1' ELSE wire_nlOO011Oi_dataout; + wire_nlOO0110l_dataout <= nlOO1O1li WHEN niOl1l11l = '1' ELSE wire_nlOO011Ol_dataout; + wire_nlOO0110O_dataout <= nlOO1O1ll WHEN niOl1l11l = '1' ELSE wire_nlOO011OO_dataout; + wire_nlOO0111i_dataout <= nlOO1O10O WHEN niOl1l11l = '1' ELSE wire_nlOO011li_dataout; + wire_nlOO0111l_dataout <= nlOO1O1ii WHEN niOl1l11l = '1' ELSE wire_nlOO011ll_dataout; + wire_nlOO0111O_dataout <= nlOO1O1il WHEN niOl1l11l = '1' ELSE wire_nlOO011lO_dataout; + wire_nlOO011i_dataout <= wire_n100iii_dataout WHEN niOO00iOl = '1' ELSE nlOi0O0l; + wire_nlOO011ii_dataout <= nlOO1O1lO WHEN niOl1l11l = '1' ELSE wire_nlOO0101i_dataout; + wire_nlOO011il_dataout <= wire_nlOO0101l_dataout AND NOT(niOl1l11l); + wire_nlOO011iO_dataout <= nlOO1i1Oi AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO011l_dataout <= wire_n100iil_dataout WHEN niOO00iOl = '1' ELSE nlOi0O0O; + wire_nlOO011li_dataout <= nlOO1O10O AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO011ll_dataout <= nlOO1O1ii AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO011lO_dataout <= nlOO1O1il AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO011O_dataout <= wire_n100iiO_dataout WHEN niOO00iOl = '1' ELSE nlOi0Oii; + wire_nlOO011Oi_dataout <= nlOO1O1iO AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO011Ol_dataout <= nlOO1O1li AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO011OO_dataout <= nlOO1O1ll AND NOT(wire_w_lg_niOl0iOOO20933w(0)); + wire_nlOO01ii_dataout <= wire_n100iOi_dataout WHEN niOO00iOl = '1' ELSE nlOi0Oll; + wire_nlOO01il_dataout <= wire_n100iOl_dataout WHEN niOO00iOl = '1' ELSE nlOi0OlO; + wire_nlOO01iO_dataout <= wire_n100iOO_dataout WHEN niOO00iOl = '1' ELSE nlOi0OOi; + wire_nlOO01li_dataout <= wire_n100l1i_dataout WHEN niOO00iOl = '1' ELSE nlOi0OOl; + wire_nlOO01ll_dataout <= wire_n100l1l_dataout WHEN niOO00iOl = '1' ELSE nlOi0OOO; + wire_nlOO01lO_dataout <= wire_n100l1O_dataout WHEN niOO00iOl = '1' ELSE nlOii11i; + wire_nlOO01Oi_dataout <= wire_n100l0i_dataout WHEN niOO00iOl = '1' ELSE nlOii11l; + wire_nlOO01Ol_dataout <= wire_n100l0l_dataout WHEN niOO00iOl = '1' ELSE nlOii11O; + wire_nlOO01OO_dataout <= wire_n100l0O_dataout WHEN niOO00iOl = '1' ELSE nlOii10i; + wire_nlOO0i0i_dataout <= wire_n100Oli_dataout WHEN niOO00iOl = '1' ELSE nlOii0il; + wire_nlOO0i0l_dataout <= wire_n100Oll_dataout WHEN niOO00iOl = '1' ELSE nlOii0iO; + wire_nlOO0i0O_dataout <= wire_n100OlO_dataout WHEN niOO00iOl = '1' ELSE nlOii0li; + wire_nlOO0i1i_dataout <= wire_n100Oii_dataout WHEN niOO00iOl = '1' ELSE nlOii00l; + wire_nlOO0i1l_dataout <= wire_n100Oil_dataout WHEN niOO00iOl = '1' ELSE nlOii00O; + wire_nlOO0i1O_dataout <= wire_n100OiO_dataout WHEN niOO00iOl = '1' ELSE nlOii0ii; + wire_nlOO0iii_dataout <= wire_n100OOi_dataout WHEN niOO00iOl = '1' ELSE nlOii0ll; + wire_nlOO0iil_dataout <= wire_n100OOl_dataout WHEN niOO00iOl = '1' ELSE nlOii0lO; + wire_nlOO0iiO_dataout <= wire_n100OOO_dataout WHEN niOO00iOl = '1' ELSE nlOii0Oi; + wire_nlOO0ili_dataout <= wire_n10i11i_dataout WHEN niOO00iOl = '1' ELSE nlOii0Ol; + wire_nlOO0ill_dataout <= wire_n10i11l_dataout WHEN niOO00iOl = '1' ELSE nlOii0OO; + wire_nlOO0ilO_dataout <= wire_n10i11O_dataout WHEN niOO00iOl = '1' ELSE nlOiii1i; + wire_nlOO0ilOl_dataout <= wire_nlOOi0iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0ilOO_dataout <= wire_nlOOi0iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iO0i_dataout <= wire_nlOOi0l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iO0l_dataout <= wire_nlOOi0l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iO0O_dataout <= wire_nlOOi0l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iO1i_dataout <= wire_nlOOi0l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iO1l_dataout <= wire_nlOOi0l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iO1O_dataout <= wire_nlOOi0l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOi_dataout <= wire_n10i10i_dataout WHEN niOO00iOl = '1' ELSE nlOiii1l; + wire_nlOO0iOii_dataout <= wire_nlOOi0lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOil_dataout <= wire_nlOOi0lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOiO_dataout <= wire_nlOOi0liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOl_dataout <= wire_n10i10l_dataout WHEN niOO00iOl = '1' ELSE nlOiii1O; + wire_nlOO0iOli_dataout <= wire_nlOOi0lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOll_dataout <= wire_nlOOi0lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOlO_dataout <= wire_nlOOi0llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOO_dataout <= wire_n10i10O_dataout WHEN niOO00iOl = '1' ELSE nlOiii0i; + wire_nlOO0iOOi_dataout <= wire_nlOOi0lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOOl_dataout <= wire_nlOOi0lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0iOOO_dataout <= wire_nlOOi1i1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l00i_dataout <= wire_nlOOi0O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l00l_dataout <= wire_nlOOi0O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l00O_dataout <= wire_nlOOi0O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l01i_dataout <= wire_nlOOi0lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l01l_dataout <= wire_nlOOi0O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l01O_dataout <= wire_nlOOi0O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0i_dataout <= wire_n10i1li_dataout WHEN niOO00iOl = '1' ELSE nlOiiiil; + wire_nlOO0l0ii_dataout <= wire_nlOOi0O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0il_dataout <= wire_nlOOi0Oii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0iO_dataout <= wire_nlOOi1l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0l_dataout <= wire_n10i1ll_dataout WHEN niOO00iOl = '1' ELSE nlOiiiiO; + wire_nlOO0l0li_dataout <= wire_nlOOi1l1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0ll_dataout <= wire_nlOOi1l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0lO_dataout <= wire_nlOOi1l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0O_dataout <= wire_n10i1lO_dataout WHEN niOO00iOl = '1' ELSE nlOiiili; + wire_nlOO0l0Oi_dataout <= wire_nlOOi1l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0Ol_dataout <= wire_nlOOi1lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l0OO_dataout <= wire_nlOOi1lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l10i_dataout <= wire_nlOOi1i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l10l_dataout <= wire_nlOOi1i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l10O_dataout <= wire_nlOOi1iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l11i_dataout <= wire_nlOOi1i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l11l_dataout <= wire_nlOOi1i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l11O_dataout <= wire_nlOOi1i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1i_dataout <= wire_n10i1ii_dataout WHEN niOO00iOl = '1' ELSE nlOiii0l; + wire_nlOO0l1ii_dataout <= wire_nlOOi1iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1il_dataout <= wire_nlOOi10il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1iO_dataout <= wire_nlOOi10iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1l_dataout <= wire_n10i1il_dataout WHEN niOO00iOl = '1' ELSE nlOiii0O; + wire_nlOO0l1li_dataout <= wire_nlOOi10li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1ll_dataout <= wire_nlOOi10ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1lO_dataout <= wire_nlOOi10lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1O_dataout <= wire_n10i1iO_dataout WHEN niOO00iOl = '1' ELSE nlOiiiii; + wire_nlOO0l1Oi_dataout <= wire_nlOOi10Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1Ol_dataout <= wire_nlOOi10Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0l1OO_dataout <= wire_nlOOi10OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0li0i_dataout <= wire_nlOOi1ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0li0l_dataout <= wire_nlOOi1ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0li0O_dataout <= wire_nlOOi1iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0li1i_dataout <= wire_nlOOi1liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0li1l_dataout <= wire_nlOOi1iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0li1O_dataout <= wire_nlOOi1ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lii_dataout <= wire_n10i1Oi_dataout WHEN niOO00iOl = '1' ELSE nlOiiill; + wire_nlOO0liii_dataout <= wire_nlOOi1iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0liil_dataout <= wire_nlOOi1iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0liiO_dataout <= wire_nlOOi1l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lil_dataout <= wire_n10i1Ol_dataout WHEN niOO00iOl = '1' ELSE nlOiiilO; + wire_nlOO0lili_dataout <= wire_nlOOl1i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lill_dataout <= wire_nlOOl1iOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lilO_dataout <= wire_niO10O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0liO_dataout <= wire_n10i1OO_dataout WHEN niOO00iOl = '1' ELSE nlOiiiOi; + wire_nlOO0liOi_dataout <= wire_niO10l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0liOl_dataout <= wire_niO10i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0liOO_dataout <= wire_niO1001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0ll0i_dataout <= wire_niO11i1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0ll0l_dataout <= wire_nlOOi0Oil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0ll0O_dataout <= wire_nlOOi0OiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0ll1i_dataout <= wire_niO1011l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0ll1l_dataout <= wire_niO11O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0ll1O_dataout <= wire_niO11l1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lli_dataout <= wire_n10i01i_dataout WHEN niOO00iOl = '1' ELSE nlOiiiOl; + wire_nlOO0llii_dataout <= wire_nlOOi0Oli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0llil_dataout <= wire_nlOOi0Oll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lliO_dataout <= wire_nlOOi0OlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lll_dataout <= wire_n10i01l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0ll_dataout; + wire_nlOO0llli_dataout <= wire_nlOOi0OOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0llll_dataout <= wire_nlOOi0OOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lllO_dataout <= wire_nlOOi0OOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0llO_dataout <= wire_n10i01O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0lO_dataout; + wire_nlOO0llOi_dataout <= wire_nlOOii1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0llOl_dataout <= wire_nlOOii1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0llOO_dataout <= wire_nlOOii1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lO0i_dataout <= wire_nlOOii1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lO0l_dataout <= wire_nlOOii01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lO0O_dataout <= wire_nlOOii11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lO1i_dataout <= wire_nlOOii1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lO1l_dataout <= wire_nlOOii1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lO1O_dataout <= wire_nlOOii1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOi_dataout <= wire_n10i00i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0Oi_dataout; + wire_nlOO0lOii_dataout <= wire_nlOOii11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOil_dataout <= wire_nlOOii11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOiO_dataout <= wire_nlOOii10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOl_dataout <= wire_n10i00l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0Ol_dataout; + wire_nlOO0lOli_dataout <= wire_nlOOii10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOll_dataout <= wire_nlOOii10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOlO_dataout <= wire_nlOOii1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOO_dataout <= wire_n10i00O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0OO_dataout; + wire_nlOO0lOOi_dataout <= wire_nlOOii1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOOl_dataout <= wire_nlOOii01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0lOOO_dataout <= wire_nlOOii01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O00i_dataout <= wire_nlOOii0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O00l_dataout <= wire_nlOOii0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O00O_dataout <= wire_nlOOiii1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O01i_dataout <= wire_nlOOii0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O01l_dataout <= wire_nlOOii0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O01O_dataout <= wire_nlOOii0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0i_dataout <= wire_n10i0li_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOi0i_dataout; + wire_nlOO0O0ii_dataout <= wire_nlOOiii1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0il_dataout <= wire_nlOOiii1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0iO_dataout <= wire_nlOOiii0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0l_dataout <= wire_n10i0ll_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOi0l_dataout; + wire_nlOO0O0li_dataout <= wire_nlOOiii0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0ll_dataout <= wire_nlOOiii0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0lO_dataout <= wire_nlOOiiiii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0O_dataout <= wire_n10i0lO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOi0O_dataout; + wire_nlOO0O0Oi_dataout <= wire_nlOOiiiil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0Ol_dataout <= wire_nlOOiiiiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O0OO_dataout <= wire_nlOOiiili_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O10i_dataout <= wire_nlOOii0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O10l_dataout <= wire_nlOOii0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O10O_dataout <= wire_nlOOii0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O11i_dataout <= wire_nlOOii00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O11l_dataout <= wire_nlOOii00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O11O_dataout <= wire_nlOOii00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1i_dataout <= wire_n10i0ii_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOi1i_dataout; + wire_nlOO0O1ii_dataout <= wire_nlOOi0i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1il_dataout <= wire_nlOOi0iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1iO_dataout <= wire_nlOOi0iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1l_dataout <= wire_n10i0il_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOi1l_dataout; + wire_nlOO0O1li_dataout <= wire_nlOOi0iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1ll_dataout <= wire_nlOOi0ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1lO_dataout <= wire_nlOOi0ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1O_dataout <= wire_n10i0iO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOi1O_dataout; + wire_nlOO0O1Oi_dataout <= wire_nlOOi0ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1Ol_dataout <= wire_nlOOi0iOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0O1OO_dataout <= wire_nlOOii0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oi0i_dataout <= wire_nlOOiiiOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oi0l_dataout <= wire_nlOOiiiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oi0O_dataout <= wire_nlOOiil1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oi1i_dataout <= wire_nlOOiiill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oi1l_dataout <= wire_nlOOiiilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oi1O_dataout <= wire_nlOOiiiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oii_dataout <= wire_n10i0Oi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOiii_dataout; + wire_nlOO0Oiii_dataout <= wire_nlOOiil1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oiil_dataout <= wire_nlOOiil1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OiiO_dataout <= wire_nlOOiil0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oil_dataout <= wire_n10i0Ol_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOiil_dataout; + wire_nlOO0Oili_dataout <= wire_nlOOiil0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oill_dataout <= wire_nlOOiil0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OilO_dataout <= wire_nlOOiilii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OiO_dataout <= wire_n10i0OO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOiiO_dataout; + wire_nlOO0OiOi_dataout <= wire_nlOOiilil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OiOl_dataout <= wire_nlOOiiliO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OiOO_dataout <= wire_nlOOiilli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Ol0i_dataout <= wire_nlOOiilOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Ol0l_dataout <= wire_nlOOiilOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Ol0O_dataout <= wire_nlOOiiO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Ol1i_dataout <= wire_nlOOiilll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Ol1l_dataout <= wire_nlOOiillO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Ol1O_dataout <= wire_nlOOiilOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oli_dataout <= wire_n10ii1i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOili_dataout; + wire_nlOO0Olii_dataout <= wire_nlOOiiO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Olil_dataout <= wire_nlOOiiO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OliO_dataout <= wire_nlOOiiO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Oll_dataout <= wire_n10ii1l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOill_dataout; + wire_nlOO0Olli_dataout <= wire_nlOOil10O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0Olll_dataout <= wire_nlOOil1ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OllO_dataout <= wire_nlOOil1il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OlO_dataout <= wire_n10ii1O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOilO_dataout; + wire_nlOO0OlOi_dataout <= wire_nlOOil1iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OlOl_dataout <= wire_nlOOil1li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OlOO_dataout <= wire_nlOOil1ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OO0i_dataout <= wire_nlOOil1OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OO0l_dataout <= wire_nlOOil01i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OO0O_dataout <= wire_nlOOil01l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OO1i_dataout <= wire_nlOOil1lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OO1l_dataout <= wire_nlOOil1Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OO1O_dataout <= wire_nlOOil1Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOi_dataout <= wire_n10ii0i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOiOi_dataout; + wire_nlOO0OOii_dataout <= wire_nlOOil01O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOil_dataout <= wire_nlOOil00i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOiO_dataout <= wire_nlOOil00l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOl_dataout <= wire_n10ii0l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOiOl_dataout; + wire_nlOO0OOli_dataout <= wire_nlOOil00O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOll_dataout <= wire_nlOOl10li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOlO_dataout <= wire_nlOOl10ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOO_dataout <= wire_n10ii0O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOiOO_dataout; + wire_nlOO0OOOi_dataout <= wire_nlOOl10lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOOl_dataout <= wire_nlOOiiO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO0OOOO_dataout <= wire_nlOOiiO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1000i_dataout <= wire_nlOO10O1l_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO10i1i_dataout; + wire_nlOO1000l_dataout <= wire_nlOO10O1O_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO10i1l_dataout; + wire_nlOO1000O_dataout <= wire_nlOO10O0i_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO10i1O_dataout; + wire_nlOO1001i_dataout <= wire_nlOO10lOl_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO100Oi_dataout; + wire_nlOO1001l_dataout <= wire_nlOO10lOO_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO100Ol_dataout; + wire_nlOO1001O_dataout <= wire_nlOO10O1i_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO100OO_dataout; + wire_nlOO100i_dataout <= wire_nlll0lli_q(112) WHEN niOO00l1i = '1' ELSE nlOiiO1i; + wire_nlOO100ii_dataout <= wire_nlOO10O0l_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO10i0i_dataout; + wire_nlOO100il_dataout <= wire_nlOO10O0O_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO10i0l_dataout; + wire_nlOO100iO_dataout <= wire_nlOO10i0O_dataout AND NOT(niOl1illO); + wire_nlOO100l_dataout <= wire_nlll0lli_q(113) WHEN niOO00l1i = '1' ELSE nlOiiO1l; + wire_nlOO100li_dataout <= wire_nlOO10iii_dataout AND NOT(niOl1illO); + wire_nlOO100ll_dataout <= wire_nlOO10iil_dataout AND NOT(niOl1illO); + wire_nlOO100lO_dataout <= wire_nlOO10iiO_dataout AND NOT(niOl1illO); + wire_nlOO100O_dataout <= wire_nlll0lli_q(114) WHEN niOO00l1i = '1' ELSE nlOiiO1O; + wire_nlOO100Oi_dataout <= wire_nlOO10ili_dataout AND NOT(niOl1illO); + wire_nlOO100Ol_dataout <= wire_nlOO10ill_dataout AND NOT(niOl1illO); + wire_nlOO100OO_dataout <= wire_nlOO10ilO_dataout AND NOT(niOl1illO); + wire_nlOO1010i_dataout <= wire_nlOO1001i_dataout WHEN niOl1ilil = '1' ELSE nlOlOil0i; + wire_nlOO1010l_dataout <= wire_nlOO1001l_dataout WHEN niOl1ilil = '1' ELSE nlOlOil0l; + wire_nlOO1010O_dataout <= wire_nlOO1001O_dataout WHEN niOl1ilil = '1' ELSE nlOlOil0O; + wire_nlOO1011i_dataout <= wire_nlOO101Oi_dataout WHEN niOl1ilil = '1' ELSE nlOlOil1i; + wire_nlOO1011l_dataout <= wire_nlOO101Ol_dataout WHEN niOl1ilil = '1' ELSE nlOlOil1l; + wire_nlOO1011O_dataout <= wire_nlOO101OO_dataout WHEN niOl1ilil = '1' ELSE nlOlOil1O; + wire_nlOO101i_dataout <= wire_nlll0lli_q(109) WHEN niOO00l1i = '1' ELSE nlOiilOi; + wire_nlOO101ii_dataout <= wire_nlOO1000i_dataout WHEN niOl1ilil = '1' ELSE nlOlOilii; + wire_nlOO101il_dataout <= wire_nlOO1000l_dataout WHEN niOl1ilil = '1' ELSE nlOlOilOl; + wire_nlOO101iO_dataout <= wire_nlOO1000O_dataout WHEN niOl1ilil = '1' ELSE nlOlOilOO; + wire_nlOO101l_dataout <= wire_nlll0lli_q(110) WHEN niOO00l1i = '1' ELSE nlOiilOl; + wire_nlOO101li_dataout <= wire_nlOO100ii_dataout WHEN niOl1ilil = '1' ELSE nlOlOiO1i; + wire_nlOO101ll_dataout <= wire_nlOO100il_dataout WHEN niOl1ilil = '1' ELSE nlOlOiO1l; + wire_nlOO101lO_dataout <= wire_nlOO10lli_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO100iO_dataout; + wire_nlOO101O_dataout <= wire_nlll0lli_q(111) WHEN niOO00l1i = '1' ELSE nlOiilOO; + wire_nlOO101Oi_dataout <= wire_nlOO10lll_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO100li_dataout; + wire_nlOO101Ol_dataout <= wire_nlOO10llO_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO100ll_dataout; + wire_nlOO101OO_dataout <= wire_nlOO10lOi_dataout WHEN niOl1iliO = '1' ELSE wire_nlOO100lO_dataout; + wire_nlOO10i0i_dataout <= nlOlOiO1i AND NOT(niOl1illO); + wire_nlOO10i0l_dataout <= nlOlOiO1l OR niOl1illO; + wire_nlOO10i0O_dataout <= wire_nlOlOOOiO_o(0) WHEN niOl1illl = '1' ELSE wire_nlOO10iOl_dataout; + wire_nlOO10i1i_dataout <= wire_nlOO10iOi_dataout AND NOT(niOl1illO); + wire_nlOO10i1l_dataout <= nlOlOilOl AND NOT(niOl1illO); + wire_nlOO10i1O_dataout <= nlOlOilOO AND NOT(niOl1illO); + wire_nlOO10ii_dataout <= wire_nlll0lli_q(115) WHEN niOO00l1i = '1' ELSE nlOiiO0i; + wire_nlOO10iii_dataout <= wire_nlOlOOOiO_o(1) WHEN niOl1illl = '1' ELSE wire_nlOO10iOO_dataout; + wire_nlOO10iil_dataout <= wire_nlOlOOOiO_o(2) WHEN niOl1illl = '1' ELSE wire_nlOO10l1i_dataout; + wire_nlOO10iiO_dataout <= wire_nlOlOOOiO_o(3) WHEN niOl1illl = '1' ELSE wire_nlOO10l1l_dataout; + wire_nlOO10il_dataout <= wire_nlll0lli_q(116) WHEN niOO00l1i = '1' ELSE nlOiiO0l; + wire_nlOO10ili_dataout <= wire_nlOlOOOiO_o(4) WHEN niOl1illl = '1' ELSE wire_nlOO10l1O_dataout; + wire_nlOO10ill_dataout <= wire_nlOlOOOiO_o(5) WHEN niOl1illl = '1' ELSE wire_nlOO10l0i_dataout; + wire_nlOO10ilO_dataout <= wire_nlOlOOOiO_o(6) WHEN niOl1illl = '1' ELSE wire_nlOO10l0l_dataout; + wire_nlOO10iO_dataout <= wire_nlll0lli_q(117) WHEN niOO00l1i = '1' ELSE nlOiiO0O; + wire_nlOO10iOi_dataout <= wire_nlOlOOOiO_o(7) WHEN niOl1illl = '1' ELSE wire_nlOO10l0O_dataout; + wire_nlOO10iOl_dataout <= wire_nlOlOOOiO_o(0) WHEN niOl1illi = '1' ELSE nlOlOi00l; + wire_nlOO10iOO_dataout <= wire_nlOlOOOiO_o(1) WHEN niOl1illi = '1' ELSE nlOlOil1i; + wire_nlOO10l0i_dataout <= wire_nlOlOOOiO_o(5) WHEN niOl1illi = '1' ELSE nlOlOil0l; + wire_nlOO10l0l_dataout <= wire_nlOlOOOiO_o(6) WHEN niOl1illi = '1' ELSE nlOlOil0O; + wire_nlOO10l0O_dataout <= wire_nlOlOOOiO_o(7) WHEN niOl1illi = '1' ELSE nlOlOilii; + wire_nlOO10l1i_dataout <= wire_nlOlOOOiO_o(2) WHEN niOl1illi = '1' ELSE nlOlOil1l; + wire_nlOO10l1l_dataout <= wire_nlOlOOOiO_o(3) WHEN niOl1illi = '1' ELSE nlOlOil1O; + wire_nlOO10l1O_dataout <= wire_nlOlOOOiO_o(4) WHEN niOl1illi = '1' ELSE nlOlOil0i; + wire_nlOO10li_dataout <= wire_nlll0lli_q(118) WHEN niOO00l1i = '1' ELSE nlOiiOii; + wire_nlOO10ll_dataout <= wire_nlll0lli_q(119) WHEN niOO00l1i = '1' ELSE nlOiiOil; + wire_nlOO10lli_dataout <= nlOlOi00l AND NOT(niOli1iOl); + wire_nlOO10lll_dataout <= nlOlOil1i AND NOT(niOli1iOl); + wire_nlOO10llO_dataout <= nlOlOil1l AND NOT(niOli1iOl); + wire_nlOO10lO_dataout <= wire_nlll0lli_q(120) WHEN niOO00l1i = '1' ELSE nlOiiOiO; + wire_nlOO10lOi_dataout <= nlOlOil1O AND NOT(niOli1iOl); + wire_nlOO10lOl_dataout <= nlOlOil0i AND NOT(niOli1iOl); + wire_nlOO10lOO_dataout <= nlOlOil0l AND NOT(niOli1iOl); + wire_nlOO10O0i_dataout <= nlOlOilOO OR niOli1iOl; + wire_nlOO10O0l_dataout <= nlOlOiO1i AND NOT(niOli1iOl); + wire_nlOO10O0O_dataout <= nlOlOiO1l AND NOT(niOli1iOl); + wire_nlOO10O1i_dataout <= nlOlOil0O AND NOT(niOli1iOl); + wire_nlOO10O1l_dataout <= nlOlOilii AND NOT(niOli1iOl); + wire_nlOO10O1O_dataout <= nlOlOilOl AND NOT(niOli1iOl); + wire_nlOO10Oi_dataout <= wire_nlll0lli_q(121) WHEN niOO00l1i = '1' ELSE nlOiiOli; + wire_nlOO10Oii_dataout <= wire_nlOO10Oil_dataout OR (n111i11l AND niOli10Ol); + wire_nlOO10Oil_dataout <= nlOlOilil AND NOT(n111i11l); + wire_nlOO10Ol_dataout <= wire_nlll0lli_q(122) WHEN niOO00l1i = '1' ELSE nlOiiOll; + wire_nlOO10Oll_dataout <= niOl1ilOl AND NOT(wire_niO01lOO_dataout); + wire_nlOO10OO_dataout <= wire_nlll0lli_q(123) WHEN niOO00l1i = '1' ELSE nlOiiOlO; + wire_nlOO10OOi_dataout <= nlOO10Oli WHEN niOO10lOO = '1' ELSE k_port(0); + wire_nlOO10OOl_dataout <= nlOO1i10O WHEN niOO10lOO = '1' ELSE k_port(1); + wire_nlOO10OOO_dataout <= nlOO1i1ii WHEN niOO10lOO = '1' ELSE k_port(2); + wire_nlOO1100i_dataout <= wire_nlOO110il_dataout AND NOT(niOl0O0Ol); + wire_nlOO1100l_dataout <= wire_nlOO110iO_dataout AND NOT(niOl0O0Ol); + wire_nlOO1100O_dataout <= wire_nlOO110li_dataout AND NOT(niOl0O0Ol); + wire_nlOO1101i_dataout <= wire_nlOO1100l_dataout WHEN n1lillil = '1' ELSE nlOlOilOO; + wire_nlOO1101l_dataout <= wire_nlOO1100O_dataout WHEN n1lillil = '1' ELSE nlOlOiO1i; + wire_nlOO1101O_dataout <= wire_nlOO110ii_dataout WHEN n1lillil = '1' ELSE nlOlOiO1l; + wire_nlOO110i_dataout <= wire_nlll0lli_q(97) WHEN niOO00l1i = '1' ELSE nlOiil1i; + wire_nlOO110ii_dataout <= wire_nlOO110ll_dataout OR niOl0O0Ol; + wire_nlOO110il_dataout <= wire_nlOO110lO_dataout AND NOT(niOl0O0OO); + wire_nlOO110iO_dataout <= wire_nlOO110Oi_dataout OR niOl0O0OO; + wire_nlOO110l_dataout <= wire_nlll0lli_q(98) WHEN niOO00l1i = '1' ELSE nlOiil1l; + wire_nlOO110li_dataout <= wire_nlOO110Ol_dataout AND NOT(niOl0O0OO); + wire_nlOO110ll_dataout <= wire_nlOO110OO_dataout AND NOT(niOl0O0OO); + wire_nlOO110lO_dataout <= wire_nlOO11i1i_dataout AND NOT(niOl0Oi1l); + wire_nlOO110O_dataout <= wire_nlll0lli_q(99) WHEN niOO00l1i = '1' ELSE nlOiil1O; + wire_nlOO110Oi_dataout <= wire_nlOO11i1l_dataout AND NOT(niOl0Oi1l); + wire_nlOO110Ol_dataout <= wire_nlOO11i1O_dataout AND NOT(niOl0Oi1l); + wire_nlOO110OO_dataout <= wire_nlOO11i0i_dataout OR niOl0Oi1l; + wire_nlOO1110i_dataout <= nlOlOiO1i AND NOT(niOl0i0lO); + wire_nlOO1110l_dataout <= nlOlOiO1l AND NOT(niOl0i0lO); + wire_nlOO1110O_dataout <= nlOlOilOl AND NOT(niOl1il0i); + wire_nlOO1111l_dataout <= nlOlOilOl OR niOl0i0lO; + wire_nlOO1111O_dataout <= nlOlOilOO AND NOT(niOl0i0lO); + wire_nlOO111i_dataout <= wire_nlll0lli_q(30) WHEN niOO00l1i = '1' ELSE wire_nlOO0liO_dataout; + wire_nlOO111ii_dataout <= nlOlOilOO AND NOT(niOl1il0i); + wire_nlOO111il_dataout <= nlOlOiO1i AND NOT(niOl1il0i); + wire_nlOO111iO_dataout <= nlOlOiO1l OR niOl1il0i; + wire_nlOO111l_dataout <= wire_nlll0lli_q(31) WHEN niOO00l1i = '1' ELSE wire_nlOO0lli_dataout; + wire_nlOO111O_dataout <= wire_nlll0lli_q(96) WHEN niOO00l1i = '1' ELSE nlOiiiOO; + wire_nlOO111Oi_dataout <= nlOlOilOl AND NOT(niOl0i0lO); + wire_nlOO111Ol_dataout <= nlOlOilOO OR niOl0i0lO; + wire_nlOO111OO_dataout <= wire_nlOO1100i_dataout WHEN n1lillil = '1' ELSE nlOlOilOl; + wire_nlOO11i0i_dataout <= nlOlOiO1l AND NOT(niOl0Oi0i); + wire_nlOO11i0l_dataout <= wire_nlOO1111l_dataout WHEN niOl1il0l = '1' ELSE nlOlOilOl; + wire_nlOO11i0O_dataout <= wire_nlOO1111O_dataout WHEN niOl1il0l = '1' ELSE nlOlOilOO; + wire_nlOO11i1i_dataout <= nlOlOilOl AND NOT(niOl0Oi0i); + wire_nlOO11i1l_dataout <= nlOlOilOO OR niOl0Oi0i; + wire_nlOO11i1O_dataout <= nlOlOiO1i AND NOT(niOl0Oi0i); + wire_nlOO11ii_dataout <= wire_nlll0lli_q(100) WHEN niOO00l1i = '1' ELSE nlOiil0i; + wire_nlOO11iii_dataout <= wire_nlOO1110i_dataout WHEN niOl1il0l = '1' ELSE nlOlOiO1i; + wire_nlOO11iil_dataout <= wire_nlOO1110l_dataout WHEN niOl1il0l = '1' ELSE nlOlOiO1l; + wire_nlOO11il_dataout <= wire_nlll0lli_q(101) WHEN niOO00l1i = '1' ELSE nlOiil0l; + wire_nlOO11ill_dataout <= wire_nlOO11lil_dataout WHEN niOl1ilil = '1' ELSE nlOlOi00l; + wire_nlOO11ilO_dataout <= wire_nlOO11liO_dataout WHEN niOl1ilil = '1' ELSE nlOlOil1i; + wire_nlOO11iO_dataout <= wire_nlll0lli_q(102) WHEN niOO00l1i = '1' ELSE nlOiil0O; + wire_nlOO11iOi_dataout <= wire_nlOO11lli_dataout WHEN niOl1ilil = '1' ELSE nlOlOil1l; + wire_nlOO11iOl_dataout <= wire_nlOO11lll_dataout WHEN niOl1ilil = '1' ELSE nlOlOil1O; + wire_nlOO11iOO_dataout <= wire_nlOO11llO_dataout WHEN niOl1ilil = '1' ELSE nlOlOil0i; + wire_nlOO11l0i_dataout <= wire_nlOO11O1i_dataout WHEN niOl1ilil = '1' ELSE nlOlOilOl; + wire_nlOO11l0l_dataout <= wire_nlOO11O1l_dataout WHEN niOl1ilil = '1' ELSE nlOlOilOO; + wire_nlOO11l0O_dataout <= wire_nlOO11O1O_dataout WHEN niOl1ilil = '1' ELSE nlOlOiO1i; + wire_nlOO11l1i_dataout <= wire_nlOO11lOi_dataout WHEN niOl1ilil = '1' ELSE nlOlOil0l; + wire_nlOO11l1l_dataout <= wire_nlOO11lOl_dataout WHEN niOl1ilil = '1' ELSE nlOlOil0O; + wire_nlOO11l1O_dataout <= wire_nlOO11lOO_dataout WHEN niOl1ilil = '1' ELSE nlOlOilii; + wire_nlOO11li_dataout <= wire_nlll0lli_q(103) WHEN niOO00l1i = '1' ELSE nlOiilii; + wire_nlOO11lii_dataout <= wire_nlOO11O0i_dataout WHEN niOl1ilil = '1' ELSE nlOlOiO1l; + wire_nlOO11lil_dataout <= wire_nlOO11O0l_dataout AND NOT(niOl1iliO); + wire_nlOO11liO_dataout <= wire_nlOO11O0O_dataout AND NOT(niOl1iliO); + wire_nlOO11ll_dataout <= wire_nlll0lli_q(104) WHEN niOO00l1i = '1' ELSE nlOiilil; + wire_nlOO11lli_dataout <= wire_nlOO11Oii_dataout AND NOT(niOl1iliO); + wire_nlOO11lll_dataout <= wire_nlOO11Oil_dataout AND NOT(niOl1iliO); + wire_nlOO11llO_dataout <= wire_nlOO11OiO_dataout AND NOT(niOl1iliO); + wire_nlOO11lO_dataout <= wire_nlll0lli_q(105) WHEN niOO00l1i = '1' ELSE nlOiiliO; + wire_nlOO11lOi_dataout <= wire_nlOO11Oli_dataout AND NOT(niOl1iliO); + wire_nlOO11lOl_dataout <= wire_nlOO11Oll_dataout AND NOT(niOl1iliO); + wire_nlOO11lOO_dataout <= wire_nlOO11OlO_dataout AND NOT(niOl1iliO); + wire_nlOO11O0i_dataout <= nlOlOiO1l AND NOT(niOl1iliO); + wire_nlOO11O0l_dataout <= wire_nlOlOOOiO_o(0) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOi00l; + wire_nlOO11O0O_dataout <= wire_nlOlOOOiO_o(1) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOil1i; + wire_nlOO11O1i_dataout <= nlOlOilOl AND NOT(niOl1iliO); + wire_nlOO11O1l_dataout <= nlOlOilOO OR niOl1iliO; + wire_nlOO11O1O_dataout <= nlOlOiO1i AND NOT(niOl1iliO); + wire_nlOO11Oi_dataout <= wire_nlll0lli_q(106) WHEN niOO00l1i = '1' ELSE nlOiilli; + wire_nlOO11Oii_dataout <= wire_nlOlOOOiO_o(2) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOil1l; + wire_nlOO11Oil_dataout <= wire_nlOlOOOiO_o(3) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOil1O; + wire_nlOO11OiO_dataout <= wire_nlOlOOOiO_o(4) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOil0i; + wire_nlOO11Ol_dataout <= wire_nlll0lli_q(107) WHEN niOO00l1i = '1' ELSE nlOiilll; + wire_nlOO11Oli_dataout <= wire_nlOlOOOiO_o(5) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOil0l; + wire_nlOO11Oll_dataout <= wire_nlOlOOOiO_o(6) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOil0O; + wire_nlOO11OlO_dataout <= wire_nlOlOOOiO_o(7) WHEN wire_niO01iOi_w_lg_nlOlOilOO24659w(0) = '1' ELSE nlOlOilii; + wire_nlOO11OO_dataout <= wire_nlll0lli_q(108) WHEN niOO00l1i = '1' ELSE nlOiillO; + wire_nlOO11OOO_dataout <= wire_nlOO101lO_dataout WHEN niOl1ilil = '1' ELSE nlOlOi00l; + wire_nlOO1i00i_dataout <= wire_nlOO1i0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1i00l_dataout <= wire_nlOO1i0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1i00O_dataout <= wire_nlOO1i0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1i01i_dataout <= wire_nlOO1i0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1i01l_dataout <= wire_nlOO1i0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1i01O_dataout <= wire_nlOO1i0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1i0i_dataout <= wire_nlll0lli_q(127) WHEN niOO00l1i = '1' ELSE nlOil11i; + wire_nlOO1i0ii_dataout <= wire_nlOO1i0OO_dataout WHEN niOl1ilOO = '1' ELSE nlOO10Oli; + wire_nlOO1i0il_dataout <= wire_nlOO1ii1i_dataout WHEN niOl1ilOO = '1' ELSE nlOO1i10O; + wire_nlOO1i0iO_dataout <= wire_nlOO1ii1l_dataout WHEN niOl1ilOO = '1' ELSE nlOO1i1ii; + wire_nlOO1i0l_dataout <= wire_nlll0lli_q(64) WHEN niOO00l1i = '1' ELSE nlOil11l; + wire_nlOO1i0li_dataout <= wire_nlOO1ii1O_dataout WHEN niOl1ilOO = '1' ELSE nlOO1i1il; + wire_nlOO1i0ll_dataout <= wire_nlOO1ii0i_dataout WHEN niOl1ilOO = '1' ELSE nlOO1i1iO; + wire_nlOO1i0lO_dataout <= wire_nlOO1ii0l_dataout WHEN niOl1ilOO = '1' ELSE nlOO1i1li; + wire_nlOO1i0O_dataout <= wire_nlll0lli_q(65) WHEN niOO00l1i = '1' ELSE nlOil11O; + wire_nlOO1i0Oi_dataout <= wire_nlOO1ii0O_dataout WHEN niOl1ilOO = '1' ELSE nlOO1i1ll; + wire_nlOO1i0Ol_dataout <= wire_nlOO1iiii_dataout WHEN niOl1ilOO = '1' ELSE nlOO1i1lO; + wire_nlOO1i0OO_dataout <= n1Oi01li WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iiil_dataout; + wire_nlOO1i10i_dataout <= nlOO1i1ll WHEN niOO10lOO = '1' ELSE k_port(6); + wire_nlOO1i10l_dataout <= nlOO1i1lO WHEN niOO10lOO = '1' ELSE k_port(7); + wire_nlOO1i11i_dataout <= nlOO1i1il WHEN niOO10lOO = '1' ELSE k_port(3); + wire_nlOO1i11l_dataout <= nlOO1i1iO WHEN niOO10lOO = '1' ELSE k_port(4); + wire_nlOO1i11O_dataout <= nlOO1i1li WHEN niOO10lOO = '1' ELSE k_port(5); + wire_nlOO1i1i_dataout <= wire_nlll0lli_q(124) WHEN niOO00l1i = '1' ELSE nlOiiOOi; + wire_nlOO1i1l_dataout <= wire_nlll0lli_q(125) WHEN niOO00l1i = '1' ELSE nlOiiOOl; + wire_nlOO1i1O_dataout <= wire_nlll0lli_q(126) WHEN niOO00l1i = '1' ELSE nlOiiOOO; + wire_nlOO1i1Ol_dataout <= wire_nlOO1i0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1i1OO_dataout <= wire_nlOO1i0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1ii0i_dataout <= n1Oi01Ol WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iilO_dataout; + wire_nlOO1ii0l_dataout <= n1Oi01OO WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iiOi_dataout; + wire_nlOO1ii0O_dataout <= n1Oi001i WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iiOl_dataout; + wire_nlOO1ii1i_dataout <= n1Oi01ll WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iiiO_dataout; + wire_nlOO1ii1l_dataout <= n1Oi01lO WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iili_dataout; + wire_nlOO1ii1O_dataout <= n1Oi01Oi WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iill_dataout; + wire_nlOO1iii_dataout <= wire_nlll0lli_q(66) WHEN niOO00l1i = '1' ELSE nlOil10i; + wire_nlOO1iiii_dataout <= n1Oi001l WHEN n1Oi1O1l = '1' ELSE wire_nlOO1iiOO_dataout; + wire_nlOO1iiil_dataout <= n011llOl WHEN n011li0O = '1' ELSE wire_nlOO1il1i_dataout; + wire_nlOO1iiiO_dataout <= n011llOO WHEN n011li0O = '1' ELSE wire_nlOO1il1l_dataout; + wire_nlOO1iil_dataout <= wire_nlll0lli_q(67) WHEN niOO00l1i = '1' ELSE nlOil10l; + wire_nlOO1iili_dataout <= n011lO1i WHEN n011li0O = '1' ELSE wire_nlOO1il1O_dataout; + wire_nlOO1iill_dataout <= n011lO1l WHEN n011li0O = '1' ELSE wire_nlOO1il0i_dataout; + wire_nlOO1iilO_dataout <= n011lO1O WHEN n011li0O = '1' ELSE wire_nlOO1il0l_dataout; + wire_nlOO1iiO_dataout <= wire_nlll0lli_q(68) WHEN niOO00l1i = '1' ELSE nlOil10O; + wire_nlOO1iiOi_dataout <= n011lO0i WHEN n011li0O = '1' ELSE wire_nlOO1il0O_dataout; + wire_nlOO1iiOl_dataout <= n011lO0l WHEN n011li0O = '1' ELSE wire_nlOO1ilii_dataout; + wire_nlOO1iiOO_dataout <= n011lO0O WHEN n011li0O = '1' ELSE wire_nlOO1ilil_dataout; + wire_nlOO1il0i_dataout <= n00iO1li WHEN n00illOl = '1' ELSE wire_nlOO1illO_dataout; + wire_nlOO1il0l_dataout <= n00iO1ll WHEN n00illOl = '1' ELSE wire_nlOO1ilOi_dataout; + wire_nlOO1il0O_dataout <= n00iO1lO WHEN n00illOl = '1' ELSE wire_nlOO1ilOl_dataout; + wire_nlOO1il1i_dataout <= n00iO1ii WHEN n00illOl = '1' ELSE wire_nlOO1iliO_dataout; + wire_nlOO1il1l_dataout <= n00iO1il WHEN n00illOl = '1' ELSE wire_nlOO1illi_dataout; + wire_nlOO1il1O_dataout <= n00iO1iO WHEN n00illOl = '1' ELSE wire_nlOO1illl_dataout; + wire_nlOO1ili_dataout <= wire_nlll0lli_q(69) WHEN niOO00l1i = '1' ELSE nlOil1ii; + wire_nlOO1ilii_dataout <= n00iO1Oi WHEN n00illOl = '1' ELSE wire_nlOO1ilOO_dataout; + wire_nlOO1ilil_dataout <= n00iO1Ol WHEN n00illOl = '1' ELSE wire_nlOO1iO1i_dataout; + wire_nlOO1iliO_dataout <= n0O0Olil WHEN n0O0O0OO = '1' ELSE nlOO10Oli; + wire_nlOO1ill_dataout <= wire_nlll0lli_q(70) WHEN niOO00l1i = '1' ELSE nlOil1il; + wire_nlOO1illi_dataout <= n0O0OliO WHEN n0O0O0OO = '1' ELSE nlOO1i10O; + wire_nlOO1illl_dataout <= n0O0Olli WHEN n0O0O0OO = '1' ELSE nlOO1i1ii; + wire_nlOO1illO_dataout <= n0O0Olll WHEN n0O0O0OO = '1' ELSE nlOO1i1il; + wire_nlOO1ilO_dataout <= wire_nlll0lli_q(71) WHEN niOO00l1i = '1' ELSE nlOil1iO; + wire_nlOO1ilOi_dataout <= n0O0OllO WHEN n0O0O0OO = '1' ELSE nlOO1i1iO; + wire_nlOO1ilOl_dataout <= n0O0OlOi WHEN n0O0O0OO = '1' ELSE nlOO1i1li; + wire_nlOO1ilOO_dataout <= n0O0OlOl WHEN n0O0O0OO = '1' ELSE nlOO1i1ll; + wire_nlOO1iO0i_dataout <= wire_nlOO1iO0O_dataout AND NOT(niOl011Ol); + wire_nlOO1iO0i_w_lg_dataout24105w(0) <= NOT wire_nlOO1iO0i_dataout; + wire_nlOO1iO0l_dataout <= wire_nlOO1iOii_dataout AND NOT(niOl011Ol); + wire_nlOO1iO0l_w_lg_dataout26694w(0) <= NOT wire_nlOO1iO0l_dataout; + wire_nlOO1iO0O_dataout <= niOl1iO1l AND NOT(niOl1iO0i); + wire_nlOO1iO1i_dataout <= n0O0OlOO WHEN n0O0O0OO = '1' ELSE nlOO1i1lO; + wire_nlOO1iO1O_dataout <= niOl1iO0i AND NOT(niOl011Ol); + wire_nlOO1iO1O_w_lg_dataout24104w(0) <= NOT wire_nlOO1iO1O_dataout; + wire_nlOO1iOi_dataout <= wire_nlll0lli_q(72) WHEN niOO00l1i = '1' ELSE nlOil1li; + wire_nlOO1iOii_dataout <= wire_nlOO1iOil_dataout AND NOT(niOl1iO0i); + wire_nlOO1iOil_dataout <= (wire_niO01ill_w_lg_n1101liO11541w(0) AND (niOl1O1li AND niOl1iO1i)) AND NOT(niOl1iO1l); + wire_nlOO1iOl_dataout <= wire_nlll0lli_q(73) WHEN niOO00l1i = '1' ELSE nlOil1ll; + wire_nlOO1iOO_dataout <= wire_nlll0lli_q(74) WHEN niOO00l1i = '1' ELSE nlOil1lO; + wire_nlOO1l00i_dataout <= wire_nlOO1l0ll_dataout OR n11O0O0i; + wire_nlOO1l00l_dataout <= wire_nlOO1l0lO_dataout AND NOT(n11O0O0i); + wire_nlOO1l00O_dataout <= wire_nlOO1l0Oi_dataout AND NOT(n11O0O0i); + wire_nlOO1l01i_dataout <= wire_nlOO1l0iO_dataout AND NOT(n11O0O0O); + wire_nlOO1l01l_dataout <= wire_nlOO1l0li_dataout AND NOT(n11O0O0i); + wire_nlOO1l01O_dataout <= wire_nlOO1l0ll_dataout AND NOT(n11O0O0i); + wire_nlOO1l0i_dataout <= wire_nlll0lli_q(78) WHEN niOO00l1i = '1' ELSE nlOil01i; + wire_nlOO1l0ii_dataout <= wire_nlOO1l0Ol_dataout OR n11O0O0i; + wire_nlOO1l0il_dataout <= wire_nlOO1l0OO_dataout AND NOT(n11O0O0i); + wire_nlOO1l0iO_dataout <= wire_nlOO1li1i_dataout AND NOT(n11O0O0i); + wire_nlOO1l0l_dataout <= wire_nlll0lli_q(79) WHEN niOO00l1i = '1' ELSE nlOil01l; + wire_nlOO1l0li_dataout <= wire_nlOO1li1l_dataout AND NOT(n11O0O1O); + wire_nlOO1l0ll_dataout <= wire_nlOO1li1O_dataout OR n11O0O1O; + wire_nlOO1l0lO_dataout <= wire_nlOO1li0i_dataout OR n11O0O1O; + wire_nlOO1l0O_dataout <= wire_nlll0lli_q(80) WHEN niOO00l1i = '1' ELSE nlOil01O; + wire_nlOO1l0Oi_dataout <= wire_nlOO1li0l_dataout OR n11O0O1O; + wire_nlOO1l0Ol_dataout <= wire_nlOO1li0O_dataout AND NOT(n11O0O1O); + wire_nlOO1l0OO_dataout <= wire_nlOO1liii_dataout AND NOT(n11O0O1O); + wire_nlOO1l10O_dataout <= wire_nlOO1l0iO_dataout OR n11O0O0O; + wire_nlOO1l1i_dataout <= wire_nlll0lli_q(75) WHEN niOO00l1i = '1' ELSE nlOil1Oi; + wire_nlOO1l1ii_dataout <= wire_nlOO1l01l_dataout AND NOT(n11O0O0O); + wire_nlOO1l1ii_w_lg_dataout24112w(0) <= NOT wire_nlOO1l1ii_dataout; + wire_nlOO1l1il_dataout <= wire_nlOO1l01O_dataout AND NOT(n11O0O0O); + wire_nlOO1l1iO_dataout <= wire_nlOO1l00i_dataout OR n11O0O0O; + wire_nlOO1l1iO_w_lg_dataout24024w(0) <= NOT wire_nlOO1l1iO_dataout; + wire_nlOO1l1l_dataout <= wire_nlll0lli_q(76) WHEN niOO00l1i = '1' ELSE nlOil1Ol; + wire_nlOO1l1li_dataout <= wire_nlOO1l00i_dataout OR n11O0O0O; + wire_nlOO1l1li_w_lg_dataout24007w(0) <= NOT wire_nlOO1l1li_dataout; + wire_nlOO1l1ll_dataout <= wire_nlOO1l00l_dataout OR n11O0O0O; + wire_nlOO1l1ll_w_lg_dataout27120w(0) <= NOT wire_nlOO1l1ll_dataout; + wire_nlOO1l1lO_dataout <= wire_nlOO1l0ii_dataout OR n11O0O0O; + wire_nlOO1l1lO_w_lg_dataout27118w(0) <= NOT wire_nlOO1l1lO_dataout; + wire_nlOO1l1O_dataout <= wire_nlll0lli_q(77) WHEN niOO00l1i = '1' ELSE nlOil1OO; + wire_nlOO1l1Oi_dataout <= wire_nlOO1l00O_dataout AND NOT(n11O0O0O); + wire_nlOO1l1Oi_w_lg_dataout27125w(0) <= NOT wire_nlOO1l1Oi_dataout; + wire_nlOO1l1Ol_dataout <= wire_nlOO1l0ii_dataout OR n11O0O0O; + wire_nlOO1l1Ol_w_lg_dataout27123w(0) <= NOT wire_nlOO1l1Ol_dataout; + wire_nlOO1l1OO_dataout <= wire_nlOO1l0il_dataout AND NOT(n11O0O0O); + wire_nlOO1l1OO_w_lg_w_lg_dataout27122w27128w(0) <= wire_nlOO1l1OO_w_lg_dataout27122w(0) AND wire_nlOO1l1Ol_dataout; + wire_nlOO1l1OO_w_lg_dataout27122w(0) <= NOT wire_nlOO1l1OO_dataout; + wire_nlOO1li0i_dataout <= wire_nlOO1lili_dataout OR niOl1iOil; + wire_nlOO1li0l_dataout <= wire_nlOO1lill_dataout OR niOl1iOil; + wire_nlOO1li0O_dataout <= wire_nlOO1lilO_dataout AND NOT(niOl1iOil); + wire_nlOO1li1i_dataout <= wire_nlOO1liil_dataout AND NOT(n11O0O1O); + wire_nlOO1li1l_dataout <= wire_nlOO1liiO_dataout AND NOT(niOl1iOil); + wire_nlOO1li1O_dataout <= wire_nlOO1liiO_dataout OR niOl1iOil; + wire_nlOO1lii_dataout <= wire_nlll0lli_q(81) WHEN niOO00l1i = '1' ELSE nlOil00i; + wire_nlOO1liii_dataout <= wire_nlOO1liOi_dataout AND NOT(niOl1iOil); + wire_nlOO1liil_dataout <= wire_nlOO1liOl_dataout AND NOT(niOl1iOil); + wire_nlOO1liiO_dataout <= wire_nlOO1liOO_dataout OR niOl1iOii; + wire_nlOO1lil_dataout <= wire_nlll0lli_q(82) WHEN niOO00l1i = '1' ELSE nlOil00l; + wire_nlOO1lili_dataout <= wire_nlOO1ll1i_dataout OR niOl1iOii; + wire_nlOO1lill_dataout <= wire_nlOO1ll1l_dataout OR niOl1iOii; + wire_nlOO1lilO_dataout <= wire_nlOO1ll1O_dataout AND NOT(niOl1iOii); + wire_nlOO1liO_dataout <= wire_nlll0lli_q(83) WHEN niOO00l1i = '1' ELSE nlOil00O; + wire_nlOO1liOi_dataout <= wire_nlOO1ll0i_dataout AND NOT(niOl1iOii); + wire_nlOO1liOl_dataout <= wire_nlOO1ll0l_dataout AND NOT(niOl1iOii); + wire_nlOO1liOO_dataout <= wire_nlOO1ll0O_dataout OR n11O0lOO; + wire_nlOO1ll0i_dataout <= wire_nlOO1llli_dataout AND NOT(n11O0lOO); + wire_nlOO1ll0l_dataout <= wire_nlOO1llll_dataout AND NOT(n11O0lOO); + wire_nlOO1ll0O_dataout <= wire_nlOO1lllO_dataout OR n11O0O1i; + wire_nlOO1ll1i_dataout <= wire_nlOO1llii_dataout OR n11O0lOO; + wire_nlOO1ll1l_dataout <= wire_nlOO1llil_dataout OR n11O0lOO; + wire_nlOO1ll1O_dataout <= wire_nlOO1lliO_dataout AND NOT(n11O0lOO); + wire_nlOO1lli_dataout <= wire_nlll0lli_q(84) WHEN niOO00l1i = '1' ELSE nlOil0ii; + wire_nlOO1llii_dataout <= wire_nlOO1llOi_dataout OR n11O0O1i; + wire_nlOO1llil_dataout <= wire_nlOO1llOl_dataout OR n11O0O1i; + wire_nlOO1lliO_dataout <= wire_nlOO1llOO_dataout AND NOT(n11O0O1i); + wire_nlOO1lll_dataout <= wire_nlll0lli_q(85) WHEN niOO00l1i = '1' ELSE nlOil0il; + wire_nlOO1llli_dataout <= wire_nlOO1lO1i_dataout AND NOT(n11O0O1i); + wire_nlOO1llll_dataout <= wire_nlOO1lO1l_dataout AND NOT(n11O0O1i); + wire_nlOO1lllO_dataout <= wire_nlOO1lO1O_dataout OR n11O0lOl; + wire_nlOO1llO_dataout <= wire_nlll0lli_q(86) WHEN niOO00l1i = '1' ELSE nlOil0iO; + wire_nlOO1llOi_dataout <= wire_nlOO1lO0i_dataout AND NOT(n11O0lOl); + wire_nlOO1llOl_dataout <= wire_nlOO1lO0l_dataout AND NOT(n11O0lOl); + wire_nlOO1llOO_dataout <= wire_nlOO1lO0O_dataout OR n11O0lOl; + wire_nlOO1lO0i_dataout <= wire_nlOO1lOli_dataout OR n11O0llO; + wire_nlOO1lO0l_dataout <= wire_nlOO1lOli_dataout AND NOT(n11O0llO); + wire_nlOO1lO0O_dataout <= wire_nlOO1lOll_dataout OR n11O0llO; + wire_nlOO1lO1i_dataout <= wire_nlOO1lOii_dataout AND NOT(n11O0lOl); + wire_nlOO1lO1l_dataout <= wire_nlOO1lOil_dataout AND NOT(n11O0lOl); + wire_nlOO1lO1O_dataout <= wire_nlOO1lOiO_dataout OR n11O0llO; + wire_nlOO1lOi_dataout <= wire_nlll0lli_q(87) WHEN niOO00l1i = '1' ELSE nlOil0li; + wire_nlOO1lOii_dataout <= wire_nlOO1lOlO_dataout AND NOT(n11O0llO); + wire_nlOO1lOil_dataout <= wire_nlOO1lOlO_dataout OR n11O0llO; + wire_nlOO1lOiO_dataout <= wire_nlOO1lOOi_dataout OR n11O0lll; + wire_nlOO1lOl_dataout <= wire_nlll0lli_q(88) WHEN niOO00l1i = '1' ELSE nlOil0ll; + wire_nlOO1lOli_dataout <= wire_nlOO1lOOl_dataout AND NOT(n11O0lll); + wire_nlOO1lOll_dataout <= wire_nlOO1lOOO_dataout OR n11O0lll; + wire_nlOO1lOlO_dataout <= wire_nlOO1lOOO_dataout AND NOT(n11O0lll); + wire_nlOO1lOO_dataout <= wire_nlll0lli_q(89) WHEN niOO00l1i = '1' ELSE nlOil0lO; + wire_nlOO1lOOi_dataout <= wire_nlOO1O11i_dataout AND NOT(n11O0liO); + wire_nlOO1lOOl_dataout <= wire_nlOO1O11l_dataout OR n11O0liO; + wire_nlOO1lOOO_dataout <= n11O0lli AND NOT(n11O0liO); + wire_nlOO1O00i_dataout <= wire_nlOO1O0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O00l_dataout <= wire_nlOO1O0OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O00O_dataout <= wire_nlOO1Oi1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O01i_dataout <= wire_nlOO1O0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O01l_dataout <= wire_nlOO1O0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O01O_dataout <= wire_nlOO1O0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O0i_dataout <= wire_nlll0lli_q(93) WHEN niOO00l1i = '1' ELSE nlOili1i; + wire_nlOO1O0ii_dataout <= wire_nlOO1Oi1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O0il_dataout <= wire_nlOO1Oi1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O0iO_dataout <= wire_nlOO1Oi0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O0l_dataout <= wire_nlll0lli_q(94) WHEN niOO00l1i = '1' ELSE nlOili1l; + wire_nlOO1O0li_dataout <= wire_nlOO011il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOO1O0ll_dataout <= wire_nlOO1Olli_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1Oi0l_dataout; + wire_nlOO1O0lO_dataout <= wire_nlOO1Olll_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1Oi0O_dataout; + wire_nlOO1O0O_dataout <= wire_nlll0lli_q(95) WHEN niOO00l1i = '1' ELSE nlOili1O; + wire_nlOO1O0Oi_dataout <= wire_nlOO1OllO_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1Oiii_dataout; + wire_nlOO1O0Ol_dataout <= wire_nlOO1OlOi_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1Oiil_dataout; + wire_nlOO1O0OO_dataout <= wire_nlOO1OlOl_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1OiiO_dataout; + wire_nlOO1O11i_dataout <= n11O0l1O OR n11O0lli; + wire_nlOO1O11l_dataout <= wire_nlOO1O11O_dataout OR n11O0lli; + wire_nlOO1O11O_dataout <= n11O0l0O OR n11O0l1O; + wire_nlOO1O1i_dataout <= wire_nlll0lli_q(90) WHEN niOO00l1i = '1' ELSE nlOil0Oi; + wire_nlOO1O1l_dataout <= wire_nlll0lli_q(91) WHEN niOO00l1i = '1' ELSE nlOil0Ol; + wire_nlOO1O1O_dataout <= wire_nlll0lli_q(92) WHEN niOO00l1i = '1' ELSE nlOil0OO; + wire_nlOO1Oi0i_dataout <= wire_nlOO1OiOi_dataout AND NOT(niOl1iOll); + wire_nlOO1Oi0l_dataout <= wire_nlOO1Olli_dataout AND NOT(niOl1iOiO); + wire_nlOO1Oi0O_dataout <= wire_nlOO1Olll_dataout AND NOT(niOl1iOiO); + wire_nlOO1Oi1i_dataout <= wire_nlOO1OlOO_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1Oili_dataout; + wire_nlOO1Oi1l_dataout <= wire_nlOO1OO1i_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1Oill_dataout; + wire_nlOO1Oi1O_dataout <= wire_nlOO1OO1l_dataout WHEN niOl1iOll = '1' ELSE wire_nlOO1OilO_dataout; + wire_nlOO1Oii_dataout <= wire_n1000Oi_dataout WHEN niOO00iOl = '1' ELSE nlOi0lll; + wire_nlOO1Oiii_dataout <= wire_nlOO1OllO_dataout AND NOT(niOl1iOiO); + wire_nlOO1Oiil_dataout <= wire_nlOO1OlOi_dataout AND NOT(niOl1iOiO); + wire_nlOO1OiiO_dataout <= wire_nlOO1OlOl_dataout AND NOT(niOl1iOiO); + wire_nlOO1Oil_dataout <= wire_n1000Ol_dataout WHEN niOO00iOl = '1' ELSE nlOi0llO; + wire_nlOO1Oili_dataout <= wire_nlOO1OlOO_dataout AND NOT(niOl1iOiO); + wire_nlOO1Oill_dataout <= wire_nlOO1OO1i_dataout AND NOT(niOl1iOiO); + wire_nlOO1OilO_dataout <= wire_nlOO1OO1l_dataout AND NOT(niOl1iOiO); + wire_nlOO1OiO_dataout <= wire_n1000OO_dataout WHEN niOO00iOl = '1' ELSE nlOi0lOi; + wire_nlOO1OiOi_dataout <= nlOO1O1Oi OR niOl1iOiO; + wire_nlOO1Oli_dataout <= wire_n100i1i_dataout WHEN niOO00iOl = '1' ELSE nlOi0lOl; + wire_nlOO1Oll_dataout <= wire_n100i1l_dataout WHEN niOO00iOl = '1' ELSE nlOi0lOO; + wire_nlOO1Olli_dataout <= wire_nlOO1OO1O_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO1OOOO_dataout; + wire_nlOO1Olll_dataout <= wire_nlOO1OO0i_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO0111i_dataout; + wire_nlOO1OllO_dataout <= wire_nlOO1OO0l_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO0111l_dataout; + wire_nlOO1OlO_dataout <= wire_n100i1O_dataout WHEN niOO00iOl = '1' ELSE nlOi0O1i; + wire_nlOO1OlOi_dataout <= wire_nlOO1OO0O_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO0111O_dataout; + wire_nlOO1OlOl_dataout <= wire_nlOO1OOii_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO0110i_dataout; + wire_nlOO1OlOO_dataout <= wire_nlOO1OOil_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO0110l_dataout; + wire_nlOO1OO0i_dataout <= wire_nlOO1OOll_o(1) WHEN niOl1iOlO = '1' ELSE wire_nlOO0111i_dataout; + wire_nlOO1OO0l_dataout <= wire_nlOO1OOll_o(2) WHEN niOl1iOlO = '1' ELSE wire_nlOO0111l_dataout; + wire_nlOO1OO0O_dataout <= wire_nlOO1OOll_o(3) WHEN niOl1iOlO = '1' ELSE wire_nlOO0111O_dataout; + wire_nlOO1OO1i_dataout <= wire_nlOO1OOiO_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO0110O_dataout; + wire_nlOO1OO1l_dataout <= wire_nlOO1OOli_dataout WHEN niOl1iOOO = '1' ELSE wire_nlOO011ii_dataout; + wire_nlOO1OO1O_dataout <= wire_nlOO1OOll_o(0) WHEN niOl1iOlO = '1' ELSE wire_nlOO1OOOO_dataout; + wire_nlOO1OOi_dataout <= wire_n100i0i_dataout WHEN niOO00iOl = '1' ELSE nlOi0O1l; + wire_nlOO1OOii_dataout <= wire_nlOO1OOll_o(4) WHEN niOl1iOlO = '1' ELSE wire_nlOO0110i_dataout; + wire_nlOO1OOil_dataout <= wire_nlOO1OOll_o(5) WHEN niOl1iOlO = '1' ELSE wire_nlOO0110l_dataout; + wire_nlOO1OOiO_dataout <= wire_nlOO1OOll_o(6) WHEN niOl1iOlO = '1' ELSE wire_nlOO0110O_dataout; + wire_nlOO1OOl_dataout <= wire_n100i0l_dataout WHEN niOO00iOl = '1' ELSE nlOi0O1O; + wire_nlOO1OOli_dataout <= wire_nlOO1OOll_o(7) WHEN niOl1iOlO = '1' ELSE wire_nlOO011ii_dataout; + wire_nlOO1OOO_dataout <= wire_n100i0O_dataout WHEN niOO00iOl = '1' ELSE nlOi0O0i; + wire_nlOO1OOOO_dataout <= nlOO1i1Oi WHEN niOl1l11l = '1' ELSE wire_nlOO011iO_dataout; + wire_nlOOi00i_dataout <= wire_n10illi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOO0i_dataout; + wire_nlOOi00l_dataout <= wire_n10illl_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOO0l_dataout; + wire_nlOOi00O_dataout <= wire_n10illO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOO0O_dataout; + wire_nlOOi010i_dataout <= niOl1li1l WHEN n1lillil = '1' ELSE nlOO01lOl; + wire_nlOOi010l_dataout <= niOl1li1i WHEN n1lillil = '1' ELSE nlOO01lOO; + wire_nlOOi010O_dataout <= niOl1l0OO WHEN n1lillil = '1' ELSE nlOO01O1i; + wire_nlOOi011i_dataout <= (niOl1l0lO AND nlOO01O0i) WHEN n1lillil = '1' ELSE nlOO01OlO; + wire_nlOOi011l_dataout <= (niOl1l0ll AND nlOO01O0l) WHEN n1lillil = '1' ELSE nlOO01OOi; + wire_nlOOi011O_dataout <= (niOl1l0li AND nlOO01O0O) WHEN n1lillil = '1' ELSE nlOO01OOl; + wire_nlOOi01i_dataout <= wire_n10ilii_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOO1i_dataout; + wire_nlOOi01ii_dataout <= niOl1l0Ol WHEN n1lillil = '1' ELSE nlOO01O1l; + wire_nlOOi01il_dataout <= niOl1l0Oi WHEN n1lillil = '1' ELSE nlOO01O1O; + wire_nlOOi01iO_dataout <= niOl1l0lO WHEN n1lillil = '1' ELSE nlOO01O0i; + wire_nlOOi01l_dataout <= wire_n10ilil_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOO1l_dataout; + wire_nlOOi01li_dataout <= niOl1l0ll WHEN n1lillil = '1' ELSE nlOO01O0l; + wire_nlOOi01ll_dataout <= niOl1l0li WHEN n1lillil = '1' ELSE nlOO01O0O; + wire_nlOOi01O_dataout <= wire_n10iliO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOO1O_dataout; + wire_nlOOi0i0O_dataout <= nlOO00ilO WHEN niOl1l1Oi = '1' ELSE (niil01il OR (nlOO00ilO OR n1Oi1l0O)); + wire_nlOOi0ii_dataout <= wire_n10ilOi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOii_dataout; + wire_nlOOi0iii_dataout <= nlOO00iOi WHEN niOl1l1Oi = '1' ELSE (niil01ii OR (nlOO00iOi OR n011l0li)); + wire_nlOOi0iil_dataout <= nlOO00iOl WHEN niOl1l1Oi = '1' ELSE (niil0iOO OR (nlOO00iOl OR n01O1OOl)); + wire_nlOOi0iiO_dataout <= nlOO00iOO WHEN niOl1l1Oi = '1' ELSE (niil0l1l OR (nlOO00iOO OR n00ill1O)); + wire_nlOOi0il_dataout <= wire_n10ilOl_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOil_dataout; + wire_nlOOi0ili_dataout <= nlOO00l1i WHEN niOl1l1Oi = '1' ELSE (niil0l1O OR (nlOO00l1i OR n0i000ii)); + wire_nlOOi0ill_dataout <= nlOO00l1l WHEN niOl1l1Oi = '1' ELSE (niil0l0i OR (nlOO00l1l OR n0iOlOll)); + wire_nlOOi0ilO_dataout <= nlOO00l1O WHEN niOl1l1Oi = '1' ELSE (niil0l0l OR (nlOO00l1O OR n0ll0iOO)); + wire_nlOOi0iO_dataout <= wire_n10ilOO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOiO_dataout; + wire_nlOOi0iOi_dataout <= nlOO00l0i WHEN niOl1l1Oi = '1' ELSE (niil0liO OR (nlOO00l0i OR n0O0O00i)); + wire_nlOOi0iOl_dataout <= ((niOl1ll1O AND n1Oi101O) OR nlOO1O1OO) AND NOT(niOl1l1Oi); + wire_nlOOi0iOO_dataout <= ((niOl1ll1l AND n011iOii) OR nlOO0100l) AND NOT(niOl1l1Oi); + wire_nlOOi0l0i_dataout <= ((niOl1liOi AND n0iOliil) OR nlOO010iO) AND NOT(niOl1l1Oi); + wire_nlOOi0l0l_dataout <= ((niOl1lilO AND n0ll01lO) OR nlOO010li) AND NOT(niOl1l1Oi); + wire_nlOOi0l0O_dataout <= ((niOl1lill AND n0O0lO1i) OR nlOO010ll) AND NOT(niOl1l1Oi); + wire_nlOOi0l1i_dataout <= ((niOl1ll1i AND n01O1ill) OR nlOO0100O) AND NOT(niOl1l1Oi); + wire_nlOOi0l1l_dataout <= ((niOl1liOO AND n00il1OO) OR nlOO010ii) AND NOT(niOl1l1Oi); + wire_nlOOi0l1O_dataout <= ((niOl1liOl AND n0i01O0i) OR nlOO010il) AND NOT(niOl1l1Oi); + wire_nlOOi0li_dataout <= wire_n10iO1i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOli_dataout; + wire_nlOOi0lii_dataout <= (niOl1ll1O OR nlOO010lO) AND NOT(niOl1l1Oi); + wire_nlOOi0lil_dataout <= (niOl1ll1l OR nlOO010Oi) AND NOT(niOl1l1Oi); + wire_nlOOi0liO_dataout <= (niOl1ll1i OR nlOO010Ol) AND NOT(niOl1l1Oi); + wire_nlOOi0ll_dataout <= wire_n10iO1l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOll_dataout; + wire_nlOOi0lli_dataout <= (niOl1liOO OR nlOO010OO) AND NOT(niOl1l1Oi); + wire_nlOOi0lll_dataout <= (niOl1liOl OR nlOO01i1i) AND NOT(niOl1l1Oi); + wire_nlOOi0llO_dataout <= (niOl1liOi OR nlOO01i1l) AND NOT(niOl1l1Oi); + wire_nlOOi0lO_dataout <= wire_n10iO1O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOlO_dataout; + wire_nlOOi0lOi_dataout <= (niOl1lilO OR nlOO01i1O) AND NOT(niOl1l1Oi); + wire_nlOOi0lOl_dataout <= (niOl1lill OR nlOO01i0i) AND NOT(niOl1l1Oi); + wire_nlOOi0lOO_dataout <= (((wire_nlOOO01lO_dataout AND n1Oi1l0i) AND n1Oi1O1l) OR nlOO01l0O) AND NOT(niOl1l1Oi); + wire_nlOOi0O0i_dataout <= (((wire_nlOOO1Oll_dataout AND n0i0000l) AND n0i00i1O) OR nlOO01lli) AND NOT(niOl1l1Oi); + wire_nlOOi0O0l_dataout <= (((wire_nlOOO1Oii_dataout AND n0iOlOiO) AND n0iOO1ii) OR nlOO01lll) AND NOT(niOl1l1Oi); + wire_nlOOi0O0O_dataout <= (((wire_nlOOO1O1O_dataout AND n0ll0iOi) AND n0ll0lll) OR nlOO01llO) AND NOT(niOl1l1Oi); + wire_nlOOi0O1i_dataout <= (((wire_nlOOO01il_dataout AND n011l0il) AND n011li0O) OR nlOO01lii) AND NOT(niOl1l1Oi); + wire_nlOOi0O1l_dataout <= (((wire_nlOOO010i_dataout AND n01O1OlO) AND n01O01li) OR nlOO01lil) AND NOT(niOl1l1Oi); + wire_nlOOi0O1O_dataout <= (((wire_nlOOO1OOO_dataout AND n00ill1i) AND n00illOl) OR nlOO01liO) AND NOT(niOl1l1Oi); + wire_nlOOi0Oi_dataout <= wire_n10iO0i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOOi_dataout; + wire_nlOOi0Oii_dataout <= (((wire_nlOOO1lOl_dataout AND n0O0O01l) AND n0O0O0OO) OR nlOO01lOi) AND NOT(niOl1l1Oi); + wire_nlOOi0Oil_dataout <= (((n1Oi1O1i AND n1Oi1liO) AND n1Oi1Oii) OR nlOO001li) AND NOT(niOl1l1Oi); + wire_nlOOi0OiO_dataout <= (((n011li0l AND n011l0Oi) AND n011lill) OR nlOO001ll) AND NOT(niOl1l1Oi); + wire_nlOOi0Ol_dataout <= wire_n10iO0l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOOl_dataout; + wire_nlOOi0Oli_dataout <= (((n01O01iO AND n01O011l) AND n01O01OO) OR nlOO001lO) AND NOT(niOl1l1Oi); + wire_nlOOi0Oll_dataout <= (((n00illOi AND n00ill0O) AND n00ilO0i) OR nlOO001Oi) AND NOT(niOl1l1Oi); + wire_nlOOi0OlO_dataout <= (((n0i00i1l AND n0i000li) AND n0i00iil) OR nlOO001Ol) AND NOT(niOl1l1Oi); + wire_nlOOi0OO_dataout <= wire_n10iO0O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOOOO_dataout; + wire_nlOOi0OOi_dataout <= (((n0iOO10O AND n0iOlOOl) AND n0iOO1lO) OR nlOO001OO) AND NOT(niOl1l1Oi); + wire_nlOOi0OOl_dataout <= (((n0ll0lli AND n0ll0l1O) AND n0ll0O1i) OR nlOO0001i) AND NOT(niOl1l1Oi); + wire_nlOOi0OOO_dataout <= (((n0O0O0Ol AND n0O0O0ii) AND n0O0Oi0l) OR nlOO0001l) AND NOT(niOl1l1Oi); + wire_nlOOi100i_dataout <= wire_nlOOil0ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi100l_dataout <= wire_nlOOil0lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi100O_dataout <= wire_nlOOil0Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi101i_dataout <= wire_nlOOil0il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi101l_dataout <= wire_nlOOil0iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi101O_dataout <= wire_nlOOil0li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi10i_dataout <= wire_n10iili_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOl0i_dataout; + wire_nlOOi10ii_dataout <= wire_nlOOil0Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi10il_dataout <= wire_nlOOi1lli_dataout AND NOT(niOlO1O0i); + wire_nlOOi10iO_dataout <= wire_nlOOi1lll_dataout AND NOT(niOlO1O0i); + wire_nlOOi10l_dataout <= wire_n10iill_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOl0l_dataout; + wire_nlOOi10li_dataout <= wire_nlOOi1llO_dataout AND NOT(niOlO1O0i); + wire_nlOOi10ll_dataout <= wire_nlOOi1lOi_dataout AND NOT(niOlO1O0i); + wire_nlOOi10lO_dataout <= wire_nlOOi1lOl_dataout AND NOT(niOlO1O0i); + wire_nlOOi10O_dataout <= wire_n10iilO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOl0O_dataout; + wire_nlOOi10Oi_dataout <= wire_nlOOi1lOO_dataout AND NOT(niOlO1O0i); + wire_nlOOi10Ol_dataout <= wire_nlOOi1O1i_dataout AND NOT(niOlO1O0i); + wire_nlOOi10OO_dataout <= wire_nlOOi1O1l_dataout AND NOT(niOlO1O0i); + wire_nlOOi110i_dataout <= wire_nlOOiiOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi110l_dataout <= wire_nlOOiiOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi110O_dataout <= wire_nlOOiiOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi111i_dataout <= wire_nlOOiiOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi111l_dataout <= wire_nlOOiiOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi111O_dataout <= wire_nlOOiiOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11i_dataout <= wire_n10iiii_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOl1i_dataout; + wire_nlOOi11ii_dataout <= wire_nlOOiiOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11il_dataout <= wire_nlOOiiOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11iO_dataout <= wire_nlOOiiOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11l_dataout <= wire_n10iiil_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOl1l_dataout; + wire_nlOOi11li_dataout <= wire_nlOOil11i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11ll_dataout <= wire_nlOOil11l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11lO_dataout <= wire_nlOOil11O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11O_dataout <= wire_n10iiiO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOl1O_dataout; + wire_nlOOi11Oi_dataout <= wire_nlOOil10i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11Ol_dataout <= wire_nlOOil10l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi11OO_dataout <= wire_nlOOil0ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOi1i0i_dataout <= wire_nlOOi1O0O_dataout AND NOT(niOlO1O0i); + wire_nlOOi1i0l_dataout <= wire_nlOOi1Oii_dataout AND NOT(niOlO1O0i); + wire_nlOOi1i0O_dataout <= wire_nlOOi1Oil_dataout AND NOT(niOlO1O0i); + wire_nlOOi1i1i_dataout <= wire_nlOOi1O1O_dataout AND NOT(niOlO1O0i); + wire_nlOOi1i1l_dataout <= wire_nlOOi1O0i_dataout AND NOT(niOlO1O0i); + wire_nlOOi1i1O_dataout <= wire_nlOOi1O0l_dataout AND NOT(niOlO1O0i); + wire_nlOOi1ii_dataout <= wire_n10iiOi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOlii_dataout; + wire_nlOOi1iii_dataout <= wire_nlOOi1OiO_dataout AND NOT(niOlO1O0i); + wire_nlOOi1iil_dataout <= wire_nlOOi1Oli_dataout AND NOT(niOlO1O0i); + wire_nlOOi1iiO_dataout <= wire_nlOOi1Oll_dataout AND NOT(niOlO1O0i); + wire_nlOOi1il_dataout <= wire_n10iiOl_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOlil_dataout; + wire_nlOOi1ili_dataout <= wire_nlOOi1OlO_dataout AND NOT(niOlO1O0i); + wire_nlOOi1ill_dataout <= wire_nlOOi1OOi_dataout AND NOT(niOlO1O0i); + wire_nlOOi1ilO_dataout <= wire_nlOOi1OOl_dataout AND NOT(niOlO1O0i); + wire_nlOOi1iO_dataout <= wire_n10iiOO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOliO_dataout; + wire_nlOOi1iOi_dataout <= wire_nlOOi1OOO_dataout AND NOT(niOlO1O0i); + wire_nlOOi1iOl_dataout <= wire_nlOOi011i_dataout AND NOT(niOlO1O0i); + wire_nlOOi1iOO_dataout <= wire_nlOOi011l_dataout AND NOT(niOlO1O0i); + wire_nlOOi1l0i_dataout <= wire_nlOOi010O_dataout AND NOT(niOlO1O0i); + wire_nlOOi1l0l_dataout <= wire_nlOOi01ii_dataout AND NOT(niOlO1O0i); + wire_nlOOi1l0O_dataout <= wire_nlOOi01il_dataout AND NOT(niOlO1O0i); + wire_nlOOi1l1i_dataout <= wire_nlOOi011O_dataout AND NOT(niOlO1O0i); + wire_nlOOi1l1l_dataout <= wire_nlOOi010i_dataout AND NOT(niOlO1O0i); + wire_nlOOi1l1O_dataout <= wire_nlOOi010l_dataout AND NOT(niOlO1O0i); + wire_nlOOi1li_dataout <= wire_n10il1i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOlli_dataout; + wire_nlOOi1lii_dataout <= wire_nlOOi01iO_dataout AND NOT(niOlO1O0i); + wire_nlOOi1lil_dataout <= wire_nlOOi01li_dataout AND NOT(niOlO1O0i); + wire_nlOOi1liO_dataout <= wire_nlOOi01ll_dataout AND NOT(niOlO1O0i); + wire_nlOOi1ll_dataout <= wire_n10il1l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOlll_dataout; + wire_nlOOi1lli_dataout <= (niOl1l1ll AND nlOO01i0l) WHEN n1lillil = '1' ELSE nlOO01iOi; + wire_nlOOi1lll_dataout <= (niOl1l1li AND nlOO01i0O) WHEN n1lillil = '1' ELSE nlOO01iOl; + wire_nlOOi1llO_dataout <= (niOl1l1iO AND nlOO01iii) WHEN n1lillil = '1' ELSE nlOO01iOO; + wire_nlOOi1lO_dataout <= wire_n10il1O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOllO_dataout; + wire_nlOOi1lOi_dataout <= (niOl1l1il AND nlOO01iil) WHEN n1lillil = '1' ELSE nlOO01l1i; + wire_nlOOi1lOl_dataout <= (niOl1l1ii AND nlOO01iiO) WHEN n1lillil = '1' ELSE nlOO01l1l; + wire_nlOOi1lOO_dataout <= (niOl1l10O AND nlOO01ili) WHEN n1lillil = '1' ELSE nlOO01l1O; + wire_nlOOi1O0i_dataout <= niOl1l1li WHEN n1lillil = '1' ELSE nlOO01i0O; + wire_nlOOi1O0l_dataout <= niOl1l1iO WHEN n1lillil = '1' ELSE nlOO01iii; + wire_nlOOi1O0O_dataout <= niOl1l1il WHEN n1lillil = '1' ELSE nlOO01iil; + wire_nlOOi1O1i_dataout <= (niOl1l10l AND nlOO01ill) WHEN n1lillil = '1' ELSE nlOO01l0i; + wire_nlOOi1O1l_dataout <= (niOl1l10i AND nlOO01ilO) WHEN n1lillil = '1' ELSE nlOO01l0l; + wire_nlOOi1O1O_dataout <= niOl1l1ll WHEN n1lillil = '1' ELSE nlOO01i0l; + wire_nlOOi1Oi_dataout <= wire_n10il0i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOlOi_dataout; + wire_nlOOi1Oii_dataout <= niOl1l1ii WHEN n1lillil = '1' ELSE nlOO01iiO; + wire_nlOOi1Oil_dataout <= niOl1l10O WHEN n1lillil = '1' ELSE nlOO01ili; + wire_nlOOi1OiO_dataout <= niOl1l10l WHEN n1lillil = '1' ELSE nlOO01ill; + wire_nlOOi1Ol_dataout <= wire_n10il0l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOlOl_dataout; + wire_nlOOi1Oli_dataout <= niOl1l10i WHEN n1lillil = '1' ELSE nlOO01ilO; + wire_nlOOi1Oll_dataout <= (niOl1li1l AND nlOO01lOl) WHEN n1lillil = '1' ELSE nlOO01Oii; + wire_nlOOi1OlO_dataout <= (niOl1li1i AND nlOO01lOO) WHEN n1lillil = '1' ELSE nlOO01Oil; + wire_nlOOi1OO_dataout <= wire_n10il0O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOOlOO_dataout; + wire_nlOOi1OOi_dataout <= (niOl1l0OO AND nlOO01O1i) WHEN n1lillil = '1' ELSE nlOO01OiO; + wire_nlOOi1OOl_dataout <= (niOl1l0Ol AND nlOO01O1l) WHEN n1lillil = '1' ELSE nlOO01Oli; + wire_nlOOi1OOO_dataout <= (niOl1l0Oi AND nlOO01O1O) WHEN n1lillil = '1' ELSE nlOO01Oll; + wire_nlOOii00i_dataout <= (nlOO00i0O OR n01lOO1i) AND NOT(niOl1l1Oi); + wire_nlOOii00l_dataout <= (nlOO00iii OR n00iii0l) AND NOT(niOl1l1Oi); + wire_nlOOii00O_dataout <= (nlOO00iil OR n0i011iO) AND NOT(niOl1l1Oi); + wire_nlOOii01i_dataout <= (((n0O0O0OO AND n0O0O0iO) AND wire_w_lg_niOl1l01l24417w(0)) OR nlOO000li) AND NOT(niOl1l1Oi); + wire_nlOOii01l_dataout <= (nlOO00i0i OR n1O0Oiil) AND NOT(niOl1l1Oi); + wire_nlOOii01O_dataout <= (nlOO00i0l OR n011i1lO) AND NOT(niOl1l1Oi); + wire_nlOOii0i_dataout <= wire_n10iOli_dataout WHEN niOO00iOl = '1' ELSE wire_n11110i_dataout; + wire_nlOOii0ii_dataout <= (nlOO00iiO OR n0iOilOi) AND NOT(niOl1l1Oi); + wire_nlOOii0il_dataout <= (nlOO00ili OR n0ll1i1l) AND NOT(niOl1l1Oi); + wire_nlOOii0iO_dataout <= (nlOO00ill OR n0O0l10O) AND NOT(niOl1l1Oi); + wire_nlOOii0l_dataout <= wire_n10iOll_dataout WHEN niOO00iOl = '1' ELSE wire_n11110l_dataout; + wire_nlOOii0li_dataout <= niOl1Olil AND NOT(niOl1l1Oi); + wire_nlOOii0ll_dataout <= niOl1Olii AND NOT(niOl1l1Oi); + wire_nlOOii0lO_dataout <= niOl1Ol0O AND NOT(niOl1l1Oi); + wire_nlOOii0O_dataout <= wire_n10iOlO_dataout WHEN niOO00iOl = '1' ELSE wire_n11110O_dataout; + wire_nlOOii0Oi_dataout <= niOl1Ol0l AND NOT(niOl1l1Oi); + wire_nlOOii0Ol_dataout <= niOl1Ol0i AND NOT(niOl1l1Oi); + wire_nlOOii0OO_dataout <= niOl1Ol1O AND NOT(niOl1l1Oi); + wire_nlOOii10i_dataout <= (((n00illOl AND n00ill0l) AND wire_w_lg_niOl1l00O24433w(0)) OR nlOO000Ol) AND NOT(niOl1l1Oi); + wire_nlOOii10l_dataout <= (((n0i00i1O AND n0i000iO) AND wire_w_lg_niOl1l00l24429w(0)) OR nlOO000OO) AND NOT(niOl1l1Oi); + wire_nlOOii10O_dataout <= (((n0iOO1ii AND n0iOlOOi) AND wire_w_lg_niOl1l00i24425w(0)) OR nlOO00i1i) AND NOT(niOl1l1Oi); + wire_nlOOii11i_dataout <= (((n1Oi1O1l AND n1Oi1lil) AND wire_w_lg_niOl1l0iO24445w(0)) OR nlOO000ll) AND NOT(niOl1l1Oi); + wire_nlOOii11l_dataout <= (((n011li0O AND n011l0lO) AND wire_w_lg_niOl1l0il24441w(0)) OR nlOO000lO) AND NOT(niOl1l1Oi); + wire_nlOOii11O_dataout <= (((n01O01li AND n01O011i) AND wire_w_lg_niOl1l0ii24437w(0)) OR nlOO000Oi) AND NOT(niOl1l1Oi); + wire_nlOOii1i_dataout <= wire_n10iOii_dataout WHEN niOO00iOl = '1' ELSE wire_n11111i_dataout; + wire_nlOOii1ii_dataout <= (((n0ll0lll AND n0ll0l1l) AND wire_w_lg_niOl1l01O24421w(0)) OR nlOO00i1l) AND NOT(niOl1l1Oi); + wire_nlOOii1il_dataout <= (((n0O0O0OO AND n0O0O00O) AND wire_w_lg_niOl1l01l24417w(0)) OR nlOO00i1O) AND NOT(niOl1l1Oi); + wire_nlOOii1iO_dataout <= (((n1Oi1O1l AND n1Oi1lll) AND wire_w_lg_niOl1l0iO24445w(0)) OR nlOO0001O) AND NOT(niOl1l1Oi); + wire_nlOOii1l_dataout <= wire_n10iOil_dataout WHEN niOO00iOl = '1' ELSE wire_n11111l_dataout; + wire_nlOOii1li_dataout <= (((n011li0O AND n011l0OO) AND wire_w_lg_niOl1l0il24441w(0)) OR nlOO0000i) AND NOT(niOl1l1Oi); + wire_nlOOii1ll_dataout <= (((n01O01li AND n01O010i) AND wire_w_lg_niOl1l0ii24437w(0)) OR nlOO0000l) AND NOT(niOl1l1Oi); + wire_nlOOii1lO_dataout <= (((n00illOl AND n00illil) AND wire_w_lg_niOl1l00O24433w(0)) OR nlOO0000O) AND NOT(niOl1l1Oi); + wire_nlOOii1O_dataout <= wire_n10iOiO_dataout WHEN niOO00iOl = '1' ELSE wire_n11111O_dataout; + wire_nlOOii1Oi_dataout <= (((n0i00i1O AND n0i000lO) AND wire_w_lg_niOl1l00l24429w(0)) OR nlOO000ii) AND NOT(niOl1l1Oi); + wire_nlOOii1Ol_dataout <= (((n0iOO1ii AND n0iOO11i) AND wire_w_lg_niOl1l00i24425w(0)) OR nlOO000il) AND NOT(niOl1l1Oi); + wire_nlOOii1OO_dataout <= (((n0ll0lll AND n0ll0l0l) AND wire_w_lg_niOl1l01O24421w(0)) OR nlOO000iO) AND NOT(niOl1l1Oi); + wire_nlOOiii0i_dataout <= ((niOl1ll1l AND n011l0il) OR nlOO00lOl) AND NOT(niOl1l1Oi); + wire_nlOOiii0l_dataout <= ((niOl1ll1i AND n01O1OlO) OR nlOO00lOO) AND NOT(niOl1l1Oi); + wire_nlOOiii0O_dataout <= ((niOl1liOO AND n00ill1i) OR nlOO00O1i) AND NOT(niOl1l1Oi); + wire_nlOOiii1i_dataout <= niOl1Ol1l AND NOT(niOl1l1Oi); + wire_nlOOiii1l_dataout <= niOl1Ol1i AND NOT(niOl1l1Oi); + wire_nlOOiii1O_dataout <= ((niOl1ll1O AND n1Oi1l0i) OR nlOO00lOi) AND NOT(niOl1l1Oi); + wire_nlOOiiii_dataout <= wire_n10iOOi_dataout WHEN niOO00iOl = '1' ELSE wire_n1111ii_dataout; + wire_nlOOiiiii_dataout <= ((niOl1liOl AND n0i0000l) OR nlOO00O1l) AND NOT(niOl1l1Oi); + wire_nlOOiiiil_dataout <= ((niOl1liOi AND n0iOlOiO) OR nlOO00O1O) AND NOT(niOl1l1Oi); + wire_nlOOiiiiO_dataout <= ((niOl1lilO AND n0ll0iOi) OR nlOO00O0i) AND NOT(niOl1l1Oi); + wire_nlOOiiil_dataout <= wire_n10iOOl_dataout WHEN niOO00iOl = '1' ELSE wire_n1111il_dataout; + wire_nlOOiiili_dataout <= ((niOl1lill AND n0O0O01l) OR nlOO00O0l) AND NOT(niOl1l1Oi); + wire_nlOOiiill_dataout <= ((niOl1ll1O AND n1Oi1O0O) OR nlOO00O0O) AND NOT(niOl1l1Oi); + wire_nlOOiiilO_dataout <= ((niOl1ll1l AND n011lili) OR nlOO00Oii) AND NOT(niOl1l1Oi); + wire_nlOOiiiO_dataout <= wire_n10iOOO_dataout WHEN niOO00iOl = '1' ELSE wire_n1111iO_dataout; + wire_nlOOiiiOi_dataout <= ((niOl1ll1i AND n01O01Ol) OR nlOO00Oil) AND NOT(niOl1l1Oi); + wire_nlOOiiiOl_dataout <= ((niOl1liOO AND n00ilO1O) OR nlOO00OiO) AND NOT(niOl1l1Oi); + wire_nlOOiiiOO_dataout <= ((niOl1liOl AND n0i00iii) OR nlOO00Oli) AND NOT(niOl1l1Oi); + wire_nlOOiil0i_dataout <= ((niOl1ll1O AND n1Oi1O0l) OR nlOO00OOl) AND NOT(niOl1l1Oi); + wire_nlOOiil0l_dataout <= ((niOl1ll1l AND n011liiO) OR nlOO00OOO) AND NOT(niOl1l1Oi); + wire_nlOOiil0O_dataout <= ((niOl1ll1i AND n01O01Oi) OR nlOO0i11i) AND NOT(niOl1l1Oi); + wire_nlOOiil1i_dataout <= ((niOl1liOi AND n0iOO1ll) OR nlOO00Oll) AND NOT(niOl1l1Oi); + wire_nlOOiil1l_dataout <= ((niOl1lilO AND n0ll0lOO) OR nlOO00OlO) AND NOT(niOl1l1Oi); + wire_nlOOiil1O_dataout <= ((niOl1lill AND n0O0Oi0i) OR nlOO00OOi) AND NOT(niOl1l1Oi); + wire_nlOOiili_dataout <= wire_n10l11i_dataout WHEN niOO00iOl = '1' ELSE wire_n1111li_dataout; + wire_nlOOiilii_dataout <= ((niOl1liOO AND n00ilO1l) OR nlOO0i11l) AND NOT(niOl1l1Oi); + wire_nlOOiilil_dataout <= ((niOl1liOl AND n0i00i0O) OR nlOO0i11O) AND NOT(niOl1l1Oi); + wire_nlOOiiliO_dataout <= ((niOl1liOi AND n0iOO1li) OR nlOO0i10i) AND NOT(niOl1l1Oi); + wire_nlOOiill_dataout <= wire_n10l11l_dataout WHEN niOO00iOl = '1' ELSE wire_n1111ll_dataout; + wire_nlOOiilli_dataout <= ((niOl1lilO AND n0ll0lOl) OR nlOO0i10l) AND NOT(niOl1l1Oi); + wire_nlOOiilll_dataout <= ((niOl1lill AND n0O0Oi1O) OR nlOO0i10O) AND NOT(niOl1l1Oi); + wire_nlOOiillO_dataout <= ((wire_w_lg_niOl0O10i24355w(0) AND wire_w_lg_w_lg_niOl0O11O24356w24357w(0)) OR nlOO0i1ii) AND NOT(niOl1l1Oi); + wire_nlOOiilO_dataout <= wire_n10l11O_dataout WHEN niOO00iOl = '1' ELSE wire_n1111lO_dataout; + wire_nlOOiilOi_dataout <= ((wire_w_lg_niOl0lOlO24350w(0) AND wire_w_lg_w_lg_niOl0lOll24351w24352w(0)) OR nlOO0i1il) AND NOT(niOl1l1Oi); + wire_nlOOiilOl_dataout <= ((wire_w_lg_niOl0lO0l24345w(0) AND wire_w_lg_w_lg_niOl0lO0i24346w24347w(0)) OR nlOO0i1iO) AND NOT(niOl1l1Oi); + wire_nlOOiilOO_dataout <= ((wire_w_lg_niOl0llOi24340w(0) AND wire_w_lg_w_lg_niOl0lllO24341w24342w(0)) OR nlOO0i1li) AND NOT(niOl1l1Oi); + wire_nlOOiiO0i_dataout <= ((wire_w_lg_niOl0l0OO24320w(0) AND wire_w_lg_w_lg_niOl0l0Ol24321w24322w(0)) OR nlOO0i1Ol) AND NOT(niOl1l1Oi); + wire_nlOOiiO0l_dataout <= niOl0lOOO AND NOT(niOl1l1Oi); + wire_nlOOiiO0O_dataout <= niOl0lOil AND NOT(niOl1l1Oi); + wire_nlOOiiO1i_dataout <= ((wire_w_lg_niOl0ll0O24335w(0) AND wire_w_lg_w_lg_niOl0ll0l24336w24337w(0)) OR nlOO0i1ll) AND NOT(niOl1l1Oi); + wire_nlOOiiO1l_dataout <= ((wire_w_lg_niOl0liOl24330w(0) AND wire_w_lg_w_lg_niOl0liOi24331w24332w(0)) OR nlOO0i1lO) AND NOT(niOl1l1Oi); + wire_nlOOiiO1O_dataout <= ((wire_w_lg_niOl0liii24325w(0) AND wire_w_lg_w_lg_niOl0li0O24326w24327w(0)) OR nlOO0i1Oi) AND NOT(niOl1l1Oi); + wire_nlOOiiOi_dataout <= wire_n10l10i_dataout WHEN niOO00iOl = '1' ELSE wire_n1111Oi_dataout; + wire_nlOOiiOii_dataout <= niOl0lO1i AND NOT(niOl1l1Oi); + wire_nlOOiiOil_dataout <= niOl0lliO AND NOT(niOl1l1Oi); + wire_nlOOiiOiO_dataout <= niOl0ll1l AND NOT(niOl1l1Oi); + wire_nlOOiiOl_dataout <= wire_n10l10l_dataout WHEN niOO00iOl = '1' ELSE wire_n1111Ol_dataout; + wire_nlOOiiOli_dataout <= niOl0lili AND NOT(niOl1l1Oi); + wire_nlOOiiOll_dataout <= niOl0li1O AND NOT(niOl1l1Oi); + wire_nlOOiiOlO_dataout <= niOl0l0ll AND NOT(niOl1l1Oi); + wire_nlOOiiOO_dataout <= wire_n10l10O_dataout WHEN niOO00iOl = '1' ELSE wire_n11101i_dataout; + wire_nlOOiiOOi_dataout <= (niOli1i1i OR nlOO0iilO) AND NOT(niOl1l1Oi); + wire_nlOOiiOOl_dataout <= (niOli1i1l OR nlOO0iiOi) AND NOT(niOl1l1Oi); + wire_nlOOiiOOO_dataout <= (niOli1i1O OR nlOO0iiOl) AND NOT(niOl1l1Oi); + wire_nlOOil00i_dataout <= ((niOl1li0l AND wire_w_lg_niOl0lill20872w(0)) OR nlOO0i0Oi) AND NOT(niOl1l1Oi); + wire_nlOOil00l_dataout <= ((niOl1li0i AND wire_w_lg_niOl0li0i20880w(0)) OR nlOO0i0Ol) AND NOT(niOl1l1Oi); + wire_nlOOil00O_dataout <= ((niOl1li1O AND wire_w_lg_niOl0l0lO20888w(0)) OR nlOO0i0OO) AND NOT(niOl1l1Oi); + wire_nlOOil01i_dataout <= ((niOl1liil AND wire_w_lg_niOl0lO1l20848w(0)) OR nlOO0i0li) AND NOT(niOl1l1Oi); + wire_nlOOil01l_dataout <= ((niOl1liii AND wire_w_lg_niOl0llli20856w(0)) OR nlOO0i0ll) AND NOT(niOl1l1Oi); + wire_nlOOil01O_dataout <= ((niOl1li0O AND wire_w_lg_niOl0ll1O20864w(0)) OR nlOO0i0lO) AND NOT(niOl1l1Oi); + wire_nlOOil0i_dataout <= wire_n10l1li_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOliiO_dataout; + wire_nlOOil0ii_dataout <= wire_nlOOl11il_dataout AND NOT(niOl1l1Oi); + wire_nlOOil0il_dataout <= wire_nlOOl11iO_dataout AND NOT(niOl1l1Oi); + wire_nlOOil0iO_dataout <= wire_nlOOl11li_dataout AND NOT(niOl1l1Oi); + wire_nlOOil0l_dataout <= wire_n10l1ll_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlili_dataout; + wire_nlOOil0li_dataout <= wire_nlOOl11ll_dataout AND NOT(niOl1l1Oi); + wire_nlOOil0ll_dataout <= wire_nlOOl11lO_dataout AND NOT(niOl1l1Oi); + wire_nlOOil0lO_dataout <= wire_nlOOl11Oi_dataout AND NOT(niOl1l1Oi); + wire_nlOOil0O_dataout <= wire_n10l1lO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlill_dataout; + wire_nlOOil0Oi_dataout <= wire_nlOOl11Ol_dataout AND NOT(niOl1l1Oi); + wire_nlOOil0Ol_dataout <= wire_nlOOl11OO_dataout AND NOT(niOl1l1Oi); + wire_nlOOil10i_dataout <= (niOli1iii OR nlOO0il1O) AND NOT(niOl1l1Oi); + wire_nlOOil10l_dataout <= (niOli1iil OR nlOO0il0i) AND NOT(niOl1l1Oi); + wire_nlOOil10O_dataout <= (wire_nlOOO0OiO_dataout OR nlOO0i1OO) AND NOT(niOl1l1Oi); + wire_nlOOil11i_dataout <= (niOli1i0i OR nlOO0iiOO) AND NOT(niOl1l1Oi); + wire_nlOOil11l_dataout <= (niOli1i0l OR nlOO0il1i) AND NOT(niOl1l1Oi); + wire_nlOOil11O_dataout <= (niOli1i0O OR nlOO0il1l) AND NOT(niOl1l1Oi); + wire_nlOOil1i_dataout <= wire_n10l1ii_dataout WHEN niOO00iOl = '1' ELSE nlO0llOi; + wire_nlOOil1ii_dataout <= (wire_nlOOO0O0O_dataout OR nlOO0i01i) AND NOT(niOl1l1Oi); + wire_nlOOil1il_dataout <= (wire_nlOOO0O1O_dataout OR nlOO0i01l) AND NOT(niOl1l1Oi); + wire_nlOOil1iO_dataout <= (wire_nlOOO0lOO_dataout OR nlOO0i01O) AND NOT(niOl1l1Oi); + wire_nlOOil1l_dataout <= wire_n10l1il_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOliii_dataout; + wire_nlOOil1li_dataout <= (wire_nlOOO0llO_dataout OR nlOO0i00i) AND NOT(niOl1l1Oi); + wire_nlOOil1ll_dataout <= (wire_nlOOO0liO_dataout OR nlOO0i00l) AND NOT(niOl1l1Oi); + wire_nlOOil1lO_dataout <= (wire_nlOOO0l0O_dataout OR nlOO0i00O) AND NOT(niOl1l1Oi); + wire_nlOOil1O_dataout <= wire_n10l1iO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOliil_dataout; + wire_nlOOil1Oi_dataout <= (wire_nlOOO0l1O_dataout OR nlOO0i0ii) AND NOT(niOl1l1Oi); + wire_nlOOil1Ol_dataout <= ((niOl1lili AND wire_w_lg_niOl0O11i20832w(0)) OR nlOO0i0il) AND NOT(niOl1l1Oi); + wire_nlOOil1OO_dataout <= ((niOl1liiO AND wire_w_lg_niOl0lOiO20840w(0)) OR nlOO0i0iO) AND NOT(niOl1l1Oi); + wire_nlOOilii_dataout <= wire_n10l1Oi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlilO_dataout; + wire_nlOOilil_dataout <= wire_n10l1Ol_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOliOi_dataout; + wire_nlOOiliO_dataout <= wire_n10l1OO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOliOl_dataout; + wire_nlOOilli_dataout <= wire_n10l01i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOliOO_dataout; + wire_nlOOilll_dataout <= wire_n10l01l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOll1i_dataout; + wire_nlOOillO_dataout <= wire_n10l01O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOll1l_dataout; + wire_nlOOilOi_dataout <= wire_n10l00i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOll1O_dataout; + wire_nlOOilOl_dataout <= wire_n10l00l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOll0i_dataout; + wire_nlOOilOO_dataout <= wire_n10l00O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOll0l_dataout; + wire_nlOOiO0i_dataout <= wire_n10l0li_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlliO_dataout; + wire_nlOOiO0l_dataout <= wire_n10l0ll_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOllli_dataout; + wire_nlOOiO0O_dataout <= wire_n10l0lO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOllll_dataout; + wire_nlOOiO1i_dataout <= wire_n10l0ii_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOll0O_dataout; + wire_nlOOiO1l_dataout <= wire_n10l0il_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOllii_dataout; + wire_nlOOiO1O_dataout <= wire_n10l0iO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOllil_dataout; + wire_nlOOiOii_dataout <= wire_n10l0Oi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlllO_dataout; + wire_nlOOiOil_dataout <= wire_n10l0Ol_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOllOi_dataout; + wire_nlOOiOiO_dataout <= wire_n10l0OO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOllOl_dataout; + wire_nlOOiOli_dataout <= wire_n10li1i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOllOO_dataout; + wire_nlOOiOll_dataout <= wire_n10li1l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlO1i_dataout; + wire_nlOOiOlO_dataout <= wire_n10li1O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlO1l_dataout; + wire_nlOOiOOi_dataout <= wire_n10li0i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlO1O_dataout; + wire_nlOOiOOl_dataout <= wire_n10li0l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlO0i_dataout; + wire_nlOOiOOO_dataout <= wire_n10li0O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlO0l_dataout; + wire_nlOOl00i_dataout <= wire_n10llli_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1iO_dataout; + wire_nlOOl00l_dataout <= wire_n10llll_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1li_dataout; + wire_nlOOl00O_dataout <= wire_n10lllO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1ll_dataout; + wire_nlOOl01i_dataout <= wire_n10llii_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO10O_dataout; + wire_nlOOl01l_dataout <= wire_n10llil_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1ii_dataout; + wire_nlOOl01O_dataout <= wire_n10lliO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1il_dataout; + wire_nlOOl0ii_dataout <= wire_n10llOi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1lO_dataout; + wire_nlOOl0il_dataout <= wire_n10llOl_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1Oi_dataout; + wire_nlOOl0iO_dataout <= wire_n10llOO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1Ol_dataout; + wire_nlOOl0li_dataout <= wire_n10lO1i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO1OO_dataout; + wire_nlOOl0ll_dataout <= wire_n10lO1l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO01i_dataout; + wire_nlOOl0lO_dataout <= wire_n10lO1O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO01l_dataout; + wire_nlOOl0Oi_dataout <= wire_n10lO0i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO01O_dataout; + wire_nlOOl0Ol_dataout <= wire_n10lO0l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO00i_dataout; + wire_nlOOl0OO_dataout <= wire_n10lO0O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO00l_dataout; + wire_nlOOl10i_dataout <= wire_n10lili_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOiO_dataout; + wire_nlOOl10l_dataout <= wire_n10lill_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOli_dataout; + wire_nlOOl10li_dataout <= wire_nlOOl10Oi_dataout AND NOT(niOlO1O0i); + wire_nlOOl10ll_dataout <= wire_nlOOl10Ol_dataout AND NOT(niOlO1O0i); + wire_nlOOl10lO_dataout <= wire_nlOOl10OO_dataout AND NOT(niOlO1O0i); + wire_nlOOl10O_dataout <= wire_n10lilO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOll_dataout; + wire_nlOOl10Oi_dataout <= wire_nlOOl1i1i_dataout WHEN n1lillil = '1' ELSE nlOO0ii1i; + wire_nlOOl10Ol_dataout <= nlOO0ii1O WHEN n1lillil = '1' ELSE nlOO0ii1l; + wire_nlOOl10OO_dataout <= wire_nlOOl1i1O_dataout WHEN n1lillil = '1' ELSE nlOO0ii1O; + wire_nlOOl11i_dataout <= wire_n10liii_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlO0O_dataout; + wire_nlOOl11il_dataout <= n1Ol011i WHEN niOl1l1lO = '1' ELSE nlOO0il0l; + wire_nlOOl11iO_dataout <= n010ll0l WHEN niOl1l1lO = '1' ELSE nlOO0il0O; + wire_nlOOl11l_dataout <= wire_n10liil_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOii_dataout; + wire_nlOOl11li_dataout <= n00100iO WHEN niOl1l1lO = '1' ELSE nlOO0ilii; + wire_nlOOl11ll_dataout <= n00llOOi WHEN niOl1l1lO = '1' ELSE nlOO0ilil; + wire_nlOOl11lO_dataout <= n0ii0l1l WHEN niOl1l1lO = '1' ELSE nlOO0iliO; + wire_nlOOl11O_dataout <= wire_n10liiO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOil_dataout; + wire_nlOOl11Oi_dataout <= n0l1O00O WHEN niOl1l1lO = '1' ELSE nlOO0illi; + wire_nlOOl11Ol_dataout <= n0lO0Oli WHEN niOl1l1lO = '1' ELSE nlOO0illl; + wire_nlOOl11OO_dataout <= n0OiOiOl WHEN niOl1l1lO = '1' ELSE nlOO0illO; + wire_nlOOl1i0i_dataout <= wire_nlOOl1i0l_dataout OR NOT(niOl1l1OO); + wire_nlOOl1i0l_dataout <= nlOO01OOO AND NOT(n1lillil); + wire_nlOOl1i1i_dataout <= nlOO0ii1i OR (nlOO0ii1l OR niOl1l1Ol); + wire_nlOOl1i1O_dataout <= nlOO0ii1O OR NOT(niOl0l0li); + wire_nlOOl1ii_dataout <= wire_n10liOi_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOlO_dataout; + wire_nlOOl1il_dataout <= wire_n10liOl_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOOi_dataout; + wire_nlOOl1iO_dataout <= wire_n10liOO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOOl_dataout; + wire_nlOOl1iOl_dataout <= wire_nlOOl1iOO_dataout OR NOT(niOl1l01i); + wire_nlOOl1iOO_dataout <= nlOO0011i AND NOT(n1lillil); + wire_nlOOl1li_dataout <= wire_n10ll1i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOlOOO_dataout; + wire_nlOOl1ll_dataout <= wire_n10ll1l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO11i_dataout; + wire_nlOOl1lO_dataout <= wire_n10ll1O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO11l_dataout; + wire_nlOOl1Oi_dataout <= wire_n10ll0i_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO11O_dataout; + wire_nlOOl1Ol_dataout <= wire_n10ll0l_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO10i_dataout; + wire_nlOOl1OO_dataout <= wire_n10ll0O_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO10l_dataout; + wire_nlOOli0i_dataout <= wire_n10lOli_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0iO_dataout; + wire_nlOOli0l_dataout <= wire_n10lOll_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0li_dataout; + wire_nlOOli0O_dataout <= wire_n10lOlO_dataout WHEN niOO00iOl = '1' ELSE wire_n1111OO_dataout; + wire_nlOOli1i_dataout <= wire_n10lOii_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO00O_dataout; + wire_nlOOli1l_dataout <= wire_n10lOil_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0ii_dataout; + wire_nlOOli1O_dataout <= wire_n10lOiO_dataout WHEN niOO00iOl = '1' ELSE wire_nlOOO0il_dataout; + wire_nlOOliii_dataout <= wire_n11iOii_dataout WHEN niOO00ili = '1' ELSE nlOi111i; + wire_nlOOliil_dataout <= wire_n11iOil_dataout WHEN niOO00ili = '1' ELSE nlOi111l; + wire_nlOOliiO_dataout <= wire_n11iOiO_dataout WHEN niOO00ili = '1' ELSE nlOi111O; + wire_nlOOlili_dataout <= wire_n11iOli_dataout WHEN niOO00ili = '1' ELSE nlOi110i; + wire_nlOOlill_dataout <= wire_n11iOll_dataout WHEN niOO00ili = '1' ELSE nlOi110l; + wire_nlOOlilO_dataout <= wire_n11iOlO_dataout WHEN niOO00ili = '1' ELSE nlOi110O; + wire_nlOOliOi_dataout <= wire_n11iOOi_dataout WHEN niOO00ili = '1' ELSE nlOi11ii; + wire_nlOOliOl_dataout <= wire_n11iOOl_dataout WHEN niOO00ili = '1' ELSE nlOi11il; + wire_nlOOliOO_dataout <= wire_n11iOOO_dataout WHEN niOO00ili = '1' ELSE nlOi11iO; + wire_nlOOll0i_dataout <= wire_n11l10i_dataout WHEN niOO00ili = '1' ELSE nlOi11Oi; + wire_nlOOll0l_dataout <= wire_n11l10l_dataout WHEN niOO00ili = '1' ELSE nlOi11Ol; + wire_nlOOll0O_dataout <= wire_n11l10O_dataout WHEN niOO00ili = '1' ELSE nlOi11OO; + wire_nlOOll1i_dataout <= wire_n11l11i_dataout WHEN niOO00ili = '1' ELSE nlOi11li; + wire_nlOOll1l_dataout <= wire_n11l11l_dataout WHEN niOO00ili = '1' ELSE nlOi11ll; + wire_nlOOll1O_dataout <= wire_n11l11O_dataout WHEN niOO00ili = '1' ELSE nlOi11lO; + wire_nlOOllii_dataout <= wire_n11l1ii_dataout WHEN niOO00ili = '1' ELSE nlOi101i; + wire_nlOOllil_dataout <= wire_n11l1il_dataout WHEN niOO00ili = '1' ELSE nlOi101l; + wire_nlOOlliO_dataout <= wire_n11l1iO_dataout WHEN niOO00ili = '1' ELSE nlOi101O; + wire_nlOOllli_dataout <= wire_n11l1li_dataout WHEN niOO00ili = '1' ELSE nlOi100i; + wire_nlOOllll_dataout <= wire_n11l1ll_dataout WHEN niOO00ili = '1' ELSE nlOi100l; + wire_nlOOlllO_dataout <= wire_n11l1lO_dataout WHEN niOO00ili = '1' ELSE nlOi100O; + wire_nlOOllOi_dataout <= wire_n11l1Oi_dataout WHEN niOO00ili = '1' ELSE nlOi10ii; + wire_nlOOllOl_dataout <= wire_n11l1Ol_dataout WHEN niOO00ili = '1' ELSE nlOi10il; + wire_nlOOllOO_dataout <= wire_n11l1OO_dataout WHEN niOO00ili = '1' ELSE nlOi10iO; + wire_nlOOlO0i_dataout <= wire_n11l00i_dataout WHEN niOO00ili = '1' ELSE nlOi10Oi; + wire_nlOOlO0l_dataout <= wire_n11l00l_dataout WHEN niOO00ili = '1' ELSE nlOi10Ol; + wire_nlOOlO0O_dataout <= wire_n11l00O_dataout WHEN niOO00ili = '1' ELSE nlOi10OO; + wire_nlOOlO1i_dataout <= wire_n11l01i_dataout WHEN niOO00ili = '1' ELSE nlOi10li; + wire_nlOOlO1l_dataout <= wire_n11l01l_dataout WHEN niOO00ili = '1' ELSE nlOi10ll; + wire_nlOOlO1O_dataout <= wire_n11l01O_dataout WHEN niOO00ili = '1' ELSE nlOi10lO; + wire_nlOOlOii_dataout <= wire_n11l0ii_dataout WHEN niOO00ili = '1' ELSE nlOi1i1i; + wire_nlOOlOil_dataout <= wire_n11l0il_dataout WHEN niOO00ili = '1' ELSE nlOi1i1l; + wire_nlOOlOiO_dataout <= wire_n11l0iO_dataout WHEN niOO00ili = '1' ELSE nlOi1i1O; + wire_nlOOlOli_dataout <= wire_n11l0li_dataout WHEN niOO00ili = '1' ELSE nlOi1i0i; + wire_nlOOlOll_dataout <= wire_n11l0ll_dataout WHEN niOO00ili = '1' ELSE nlOi1i0l; + wire_nlOOlOlO_dataout <= wire_n11l0lO_dataout WHEN niOO00ili = '1' ELSE nlOi1i0O; + wire_nlOOlOOi_dataout <= wire_n11l0Oi_dataout WHEN niOO00ili = '1' ELSE nlOi1iii; + wire_nlOOlOOl_dataout <= wire_n11l0Ol_dataout WHEN niOO00ili = '1' ELSE nlOi1iil; + wire_nlOOlOOO_dataout <= wire_n11l0OO_dataout WHEN niOO00ili = '1' ELSE nlOi1iiO; + wire_nlOOO00i_dataout <= wire_n11ll0i_dataout WHEN niOO00ili = '1' ELSE nlOi1lOi; + wire_nlOOO00l_dataout <= wire_n11ll0l_dataout WHEN niOO00ili = '1' ELSE nlOi1lOl; + wire_nlOOO00O_dataout <= wire_n11ll0O_dataout WHEN niOO00ili = '1' ELSE nlOi1lOO; + wire_nlOOO010i_dataout <= n01O011i WHEN niOl1O10O = '1' ELSE wire_nlOOO010l_dataout; + wire_nlOOO010l_dataout <= n01O011l WHEN niOl1O1ii = '1' ELSE wire_nlOOO010O_dataout; + wire_nlOOO010O_dataout <= n01O010i WHEN niOl1O1il = '1' ELSE wire_nlOOO01ii_dataout; + wire_nlOOO011i_dataout <= n00ill0O WHEN niOl1O1ii = '1' ELSE wire_nlOOO011l_dataout; + wire_nlOOO011l_dataout <= n00illil WHEN niOl1O1il = '1' ELSE wire_nlOOO011O_dataout; + wire_nlOOO011O_dataout <= n00illiO OR NOT(niOl1O1iO); + wire_nlOOO01i_dataout <= wire_n11ll1i_dataout WHEN niOO00ili = '1' ELSE nlOi1lli; + wire_nlOOO01ii_dataout <= n01O010l OR NOT(niOl1O1iO); + wire_nlOOO01il_dataout <= n011l0lO WHEN niOl1O10O = '1' ELSE wire_nlOOO01iO_dataout; + wire_nlOOO01iO_dataout <= n011l0Oi WHEN niOl1O1ii = '1' ELSE wire_nlOOO01li_dataout; + wire_nlOOO01l_dataout <= wire_n11ll1l_dataout WHEN niOO00ili = '1' ELSE nlOi1lll; + wire_nlOOO01li_dataout <= n011l0OO WHEN niOl1O1il = '1' ELSE wire_nlOOO01ll_dataout; + wire_nlOOO01ll_dataout <= n011li1i OR NOT(niOl1O1iO); + wire_nlOOO01lO_dataout <= n1Oi1lil WHEN niOl1O10O = '1' ELSE wire_nlOOO01Oi_dataout; + wire_nlOOO01O_dataout <= wire_n11ll1O_dataout WHEN niOO00ili = '1' ELSE nlOi1llO; + wire_nlOOO01Oi_dataout <= n1Oi1liO WHEN niOl1O1ii = '1' ELSE wire_nlOOO01Ol_dataout; + wire_nlOOO01Ol_dataout <= n1Oi1lll WHEN niOl1O1il = '1' ELSE wire_nlOOO01OO_dataout; + wire_nlOOO01OO_dataout <= n1Oi1llO OR NOT(niOl1O1iO); + wire_nlOOO0ii_dataout <= wire_n11llii_dataout WHEN niOO00ili = '1' ELSE nlOi1O1i; + wire_nlOOO0il_dataout <= wire_n11llil_dataout WHEN niOO00ili = '1' ELSE nlOi1O1l; + wire_nlOOO0iO_dataout <= wire_n11lliO_dataout WHEN niOO00ili = '1' ELSE nlOi1O1O; + wire_nlOOO0l0i_dataout <= n0O0O0OO WHEN niOl1O1OO = '1' ELSE wire_nlOOO0l0l_dataout; + wire_nlOOO0l0l_dataout <= n0O0O0Ol OR NOT(niOl1O01i); + wire_nlOOO0l0O_dataout <= niOl1OOll WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0lii_dataout; + wire_nlOOO0l0O_w_lg_dataout24214w(0) <= wire_nlOOO0l0O_dataout AND niOl0li0O; + wire_nlOOO0l1O_dataout <= niOl1O1li WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0l0i_dataout; + wire_nlOOO0l1O_w_lg_dataout24218w(0) <= wire_nlOOO0l1O_dataout AND niOl0l0Ol; + wire_nlOOO0li_dataout <= wire_n11llli_dataout WHEN niOO00ili = '1' ELSE nlOi1O0i; + wire_nlOOO0lii_dataout <= n0ll0lll WHEN niOl1O1OO = '1' ELSE wire_nlOOO0lil_dataout; + wire_nlOOO0lil_dataout <= n0ll0lli OR NOT(niOl1O01i); + wire_nlOOO0liO_dataout <= niOl1OOlO WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0lli_dataout; + wire_nlOOO0liO_w_lg_dataout24210w(0) <= wire_nlOOO0liO_dataout AND niOl0liOi; + wire_nlOOO0ll_dataout <= wire_n11llll_dataout WHEN niOO00ili = '1' ELSE wire_n11101O_dataout; + wire_nlOOO0lli_dataout <= n0iOO1ii WHEN niOl1O1OO = '1' ELSE wire_nlOOO0lll_dataout; + wire_nlOOO0lll_dataout <= n0iOO10O OR NOT(niOl1O01i); + wire_nlOOO0llO_dataout <= niOl1OOOi WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0lOi_dataout; + wire_nlOOO0llO_w_lg_dataout24206w(0) <= wire_nlOOO0llO_dataout AND niOl0ll0l; + wire_nlOOO0lO_dataout <= wire_n11lllO_dataout WHEN niOO00ili = '1' ELSE wire_n11100i_dataout; + wire_nlOOO0lOi_dataout <= n0i00i1O WHEN niOl1O1OO = '1' ELSE wire_nlOOO0lOl_dataout; + wire_nlOOO0lOl_dataout <= n0i00i1l OR NOT(niOl1O01i); + wire_nlOOO0lOO_dataout <= niOl1O1ll WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0O1i_dataout; + wire_nlOOO0lOO_w_lg_dataout24202w(0) <= wire_nlOOO0lOO_dataout AND niOl0lllO; + wire_nlOOO0O0i_dataout <= n01O01li WHEN niOl1O1OO = '1' ELSE wire_nlOOO0O0l_dataout; + wire_nlOOO0O0l_dataout <= n01O01iO OR NOT(niOl1O01i); + wire_nlOOO0O0O_dataout <= niOl1O1lO WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0Oii_dataout; + wire_nlOOO0O0O_w_lg_dataout24194w(0) <= wire_nlOOO0O0O_dataout AND niOl0lOll; + wire_nlOOO0O1i_dataout <= n00illOl WHEN niOl1O1OO = '1' ELSE wire_nlOOO0O1l_dataout; + wire_nlOOO0O1l_dataout <= n00illOi OR NOT(niOl1O01i); + wire_nlOOO0O1O_dataout <= niOl1OOOl WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0O0i_dataout; + wire_nlOOO0O1O_w_lg_dataout24198w(0) <= wire_nlOOO0O1O_dataout AND niOl0lO0i; + wire_nlOOO0Oi_dataout <= wire_n11llOi_dataout WHEN niOO00ili = '1' ELSE wire_n11100l_dataout; + wire_nlOOO0Oii_dataout <= n011li0O WHEN niOl1O1OO = '1' ELSE wire_nlOOO0Oil_dataout; + wire_nlOOO0Oil_dataout <= n011li0l OR NOT(niOl1O01i); + wire_nlOOO0OiO_dataout <= niOl1O1Ol WHEN niOl1O1Oi = '1' ELSE wire_nlOOO0Oli_dataout; + wire_nlOOO0OiO_w_lg_dataout24190w(0) <= wire_nlOOO0OiO_dataout AND niOl0O11O; + wire_nlOOO0Ol_dataout <= wire_n11llOl_dataout WHEN niOO00ili = '1' ELSE wire_n11100O_dataout; + wire_nlOOO0Oli_dataout <= n1Oi1O1l WHEN niOl1O1OO = '1' ELSE wire_nlOOO0Oll_dataout; + wire_nlOOO0Oll_dataout <= n1Oi1O1i OR NOT(niOl1O01i); + wire_nlOOO0OO_dataout <= wire_n11llOO_dataout WHEN niOO00ili = '1' ELSE wire_n1110ii_dataout; + wire_nlOOO10i_dataout <= wire_n11li0i_dataout WHEN niOO00ili = '1' ELSE nlOi1iOi; + wire_nlOOO10il_dataout <= wire_niO01ill_w_lg_n1101ill24107w(0) AND NOT(n1101ilO); + wire_nlOOO10iO_dataout <= wire_niO01ill_w_lg_n1101ill24107w(0) AND NOT(n1101ilO); + wire_nlOOO10l_dataout <= wire_n11li0l_dataout WHEN niOO00ili = '1' ELSE nlOi1iOl; + wire_nlOOO10li_dataout <= n1101ill OR n1101ilO; + wire_nlOOO10ll_dataout <= wire_niO01ill_w_lg_n1101ill24107w(0) AND NOT(n1101ilO); + wire_nlOOO10lO_dataout <= wire_nlOOO10Ol_dataout AND NOT(n1101ilO); + wire_nlOOO10O_dataout <= wire_n11li0O_dataout WHEN niOO00ili = '1' ELSE nlOi1iOO; + wire_nlOOO10Oi_dataout <= n1101ill OR n1101ilO; + wire_nlOOO10Ol_dataout <= wire_niO01ill_w_lg_n1101ili24106w(0) AND NOT(n1101ill); + wire_nlOOO10OO_dataout <= wire_nlOOO1i1l_dataout OR n1101ilO; + wire_nlOOO11i_dataout <= wire_n11li1i_dataout WHEN niOO00ili = '1' ELSE nlOi1ili; + wire_nlOOO11l_dataout <= wire_n11li1l_dataout WHEN niOO00ili = '1' ELSE nlOi1ill; + wire_nlOOO11O_dataout <= wire_n11li1O_dataout WHEN niOO00ili = '1' ELSE nlOi1ilO; + wire_nlOOO1i0i_dataout <= wire_nlOO1iO0i_w_lg_dataout24105w(0) AND NOT(wire_nlOO1iO0l_dataout); + wire_nlOOO1i0l_dataout <= wire_nlOO1iO0i_dataout OR wire_nlOO1iO0l_dataout; + wire_nlOOO1i0O_dataout <= wire_nlOO1iO0i_w_lg_dataout24105w(0) AND NOT(wire_nlOO1iO0l_dataout); + wire_nlOOO1i1i_dataout <= n1101ill OR n1101ilO; + wire_nlOOO1i1l_dataout <= n1101ili OR n1101ill; + wire_nlOOO1i1O_dataout <= wire_nlOO1iO0i_w_lg_dataout24105w(0) AND NOT(wire_nlOO1iO0l_dataout); + wire_nlOOO1ii_dataout <= wire_n11liii_dataout WHEN niOO00ili = '1' ELSE nlOi1l1i; + wire_nlOOO1iii_dataout <= wire_nlOOO1iiO_dataout AND NOT(wire_nlOO1iO0l_dataout); + wire_nlOOO1iil_dataout <= wire_nlOO1iO0i_dataout OR wire_nlOO1iO0l_dataout; + wire_nlOOO1iiO_dataout <= wire_nlOO1iO1O_w_lg_dataout24104w(0) AND NOT(wire_nlOO1iO0i_dataout); + wire_nlOOO1il_dataout <= wire_n11liil_dataout WHEN niOO00ili = '1' ELSE nlOi1l1l; + wire_nlOOO1ili_dataout <= wire_nlOOO1ilO_dataout OR wire_nlOO1iO0l_dataout; + wire_nlOOO1ill_dataout <= wire_nlOO1iO0i_dataout OR wire_nlOO1iO0l_dataout; + wire_nlOOO1ilO_dataout <= wire_nlOO1iO1O_dataout OR wire_nlOO1iO0i_dataout; + wire_nlOOO1iO_dataout <= wire_n11liiO_dataout WHEN niOO00ili = '1' ELSE nlOi1l1O; + wire_nlOOO1li_dataout <= wire_n11lili_dataout WHEN niOO00ili = '1' ELSE nlOi1l0i; + wire_nlOOO1ll_dataout <= wire_n11lill_dataout WHEN niOO00ili = '1' ELSE nlOi1l0l; + wire_nlOOO1lO_dataout <= wire_n11lilO_dataout WHEN niOO00ili = '1' ELSE nlOi1l0O; + wire_nlOOO1lOl_dataout <= n0O0O00O WHEN niOl1O10O = '1' ELSE wire_nlOOO1lOO_dataout; + wire_nlOOO1lOO_dataout <= n0O0O0ii WHEN niOl1O1ii = '1' ELSE wire_nlOOO1O1i_dataout; + wire_nlOOO1O0i_dataout <= n0ll0l1O WHEN niOl1O1ii = '1' ELSE wire_nlOOO1O0l_dataout; + wire_nlOOO1O0l_dataout <= n0ll0l0l WHEN niOl1O1il = '1' ELSE wire_nlOOO1O0O_dataout; + wire_nlOOO1O0O_dataout <= n0ll0l0O OR NOT(niOl1O1iO); + wire_nlOOO1O1i_dataout <= n0O0O0iO WHEN niOl1O1il = '1' ELSE wire_nlOOO1O1l_dataout; + wire_nlOOO1O1l_dataout <= n0O0O0li OR NOT(niOl1O1iO); + wire_nlOOO1O1O_dataout <= n0ll0l1l WHEN niOl1O10O = '1' ELSE wire_nlOOO1O0i_dataout; + wire_nlOOO1Oi_dataout <= wire_n11liOi_dataout WHEN niOO00ili = '1' ELSE nlOi1lii; + wire_nlOOO1Oii_dataout <= n0iOlOOi WHEN niOl1O10O = '1' ELSE wire_nlOOO1Oil_dataout; + wire_nlOOO1Oil_dataout <= n0iOlOOl WHEN niOl1O1ii = '1' ELSE wire_nlOOO1OiO_dataout; + wire_nlOOO1OiO_dataout <= n0iOO11i WHEN niOl1O1il = '1' ELSE wire_nlOOO1Oli_dataout; + wire_nlOOO1Ol_dataout <= wire_n11liOl_dataout WHEN niOO00ili = '1' ELSE nlOi1lil; + wire_nlOOO1Oli_dataout <= n0iOO11l OR NOT(niOl1O1iO); + wire_nlOOO1Oll_dataout <= n0i000iO WHEN niOl1O10O = '1' ELSE wire_nlOOO1OlO_dataout; + wire_nlOOO1OlO_dataout <= n0i000li WHEN niOl1O1ii = '1' ELSE wire_nlOOO1OOi_dataout; + wire_nlOOO1OO_dataout <= wire_n11liOO_dataout WHEN niOO00ili = '1' ELSE nlOi1liO; + wire_nlOOO1OOi_dataout <= n0i000lO WHEN niOl1O1il = '1' ELSE wire_nlOOO1OOl_dataout; + wire_nlOOO1OOl_dataout <= n0i000Oi OR NOT(niOl1O1iO); + wire_nlOOO1OOO_dataout <= n00ill0l WHEN niOl1O10O = '1' ELSE wire_nlOOO011i_dataout; + wire_nlOOOi0i_dataout <= wire_n11lO0i_dataout WHEN niOO00ili = '1' ELSE wire_n1110ll_dataout; + wire_nlOOOi0l_dataout <= wire_n11lO0l_dataout WHEN niOO00ili = '1' ELSE wire_n1110lO_dataout; + wire_nlOOOi0O_dataout <= wire_n11lO0O_dataout WHEN niOO00ili = '1' ELSE wire_n1110Oi_dataout; + wire_nlOOOi1i_dataout <= wire_n11lO1i_dataout WHEN niOO00ili = '1' ELSE wire_n1110il_dataout; + wire_nlOOOi1l_dataout <= wire_n11lO1l_dataout WHEN niOO00ili = '1' ELSE wire_n1110iO_dataout; + wire_nlOOOi1O_dataout <= wire_n11lO1O_dataout WHEN niOO00ili = '1' ELSE wire_n1110li_dataout; + wire_nlOOOiii_dataout <= wire_n11lOii_dataout WHEN niOO00ili = '1' ELSE wire_n1110Ol_dataout; + wire_nlOOOiil_dataout <= wire_n11lOil_dataout WHEN niOO00ili = '1' ELSE wire_n1110OO_dataout; + wire_nlOOOiiO_dataout <= wire_n11lOiO_dataout WHEN niOO00ili = '1' ELSE wire_n111i1i_dataout; + wire_nlOOOili_dataout <= wire_n11lOli_dataout WHEN niOO00ili = '1' ELSE wire_n111i1l_dataout; + wire_nlOOOill_dataout <= wire_n11lOll_dataout WHEN niOO00ili = '1' ELSE wire_n111i1O_dataout; + wire_nlOOOilO_dataout <= wire_n11lOlO_dataout WHEN niOO00ili = '1' ELSE wire_n111i0i_dataout; + wire_nlOOOiOi_dataout <= wire_n11lOOi_dataout WHEN niOO00ili = '1' ELSE wire_n111i0l_dataout; + wire_nlOOOiOl_dataout <= wire_n11lOOl_dataout WHEN niOO00ili = '1' ELSE wire_n111i0O_dataout; + wire_nlOOOiOO_dataout <= wire_n11lOOO_dataout WHEN niOO00ili = '1' ELSE wire_n111iii_dataout; + wire_nlOOOl00l_dataout <= wire_n1110l0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl00O_dataout <= wire_n1110l0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0i_dataout <= wire_n11O10i_dataout WHEN niOO00ili = '1' ELSE wire_n111ill_dataout; + wire_nlOOOl0ii_dataout <= wire_n1110l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0il_dataout <= wire_n1110lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0iO_dataout <= wire_n1110lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0l_dataout <= wire_n11O10l_dataout WHEN niOO00ili = '1' ELSE wire_n111ilO_dataout; + wire_nlOOOl0li_dataout <= wire_n1110liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0ll_dataout <= wire_n1110lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0lO_dataout <= wire_n1110lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0O_dataout <= wire_n11O10O_dataout WHEN niOO00ili = '1' ELSE wire_n111iOi_dataout; + wire_nlOOOl0Oi_dataout <= wire_nlOOOOiOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0Ol_dataout <= wire_nlOOOOiOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl0OO_dataout <= wire_nlOOOOl1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOl1i_dataout <= wire_n11O11i_dataout WHEN niOO00ili = '1' ELSE wire_n111iil_dataout; + wire_nlOOOl1l_dataout <= wire_n11O11l_dataout WHEN niOO00ili = '1' ELSE wire_n111iiO_dataout; + wire_nlOOOl1O_dataout <= wire_n11O11O_dataout WHEN niOO00ili = '1' ELSE wire_n111ili_dataout; + wire_nlOOOli0i_dataout <= wire_nlOOOOl0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOli0l_dataout <= wire_nlOOOOl0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOli0O_dataout <= wire_nlOOOOlii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOli1i_dataout <= wire_nlOOOOl1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOli1l_dataout <= wire_nlOOOOl1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOli1O_dataout <= wire_nlOOOOl0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlii_dataout <= wire_n11O1ii_dataout WHEN niOO00ili = '1' ELSE wire_n111iOl_dataout; + wire_nlOOOliii_dataout <= wire_nlOOOOO1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOliil_dataout <= wire_nlOOOOO1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOliiO_dataout <= wire_nlOOOOO1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlil_dataout <= wire_n11O1il_dataout WHEN niOO00ili = '1' ELSE wire_n111iOO_dataout; + wire_nlOOOlili_dataout <= wire_nlOOOOO0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlill_dataout <= wire_nlOOOOO0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlilO_dataout <= wire_nlOOOOO0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOliO_dataout <= wire_n11O1iO_dataout WHEN niOO00ili = '1' ELSE wire_n111l1i_dataout; + wire_nlOOOliOi_dataout <= wire_nlOOOOOii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOliOl_dataout <= wire_nlOOOOOil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOliOO_dataout <= wire_nlOOOOOiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOll0i_dataout <= wire_nlOOOOOOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOll0l_dataout <= wire_nlOOOOOOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOll0O_dataout <= wire_nlOOOOOOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOll1i_dataout <= wire_nlOOOOOli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOll1l_dataout <= wire_nlOOOOOll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOll1O_dataout <= wire_nlOOOOOlO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlli_dataout <= wire_n11O1li_dataout WHEN niOO00ili = '1' ELSE wire_n111l1l_dataout; + wire_nlOOOllii_dataout <= wire_n111111i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOllil_dataout <= wire_n111111l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlliO_dataout <= wire_n111111O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlll_dataout <= wire_n11O1ll_dataout WHEN niOO00ili = '1' ELSE wire_n111l1O_dataout; + wire_nlOOOllli_dataout <= wire_n111110i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOllll_dataout <= wire_n111110l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlllO_dataout <= wire_n111110O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOllO_dataout <= wire_n11O1lO_dataout WHEN niOO00ili = '1' ELSE wire_n111l0i_dataout; + wire_nlOOOllOi_dataout <= wire_n11111ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOllOl_dataout <= wire_n11111il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOllOO_dataout <= wire_n11111iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlO0i_dataout <= wire_n11111Oi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlO0l_dataout <= wire_n11111Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlO0O_dataout <= wire_n11111OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlO1i_dataout <= wire_n11111li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlO1l_dataout <= wire_n11111ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlO1O_dataout <= wire_n11111lO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOi_dataout <= wire_n11O1Oi_dataout WHEN niOO00ili = '1' ELSE wire_n111l0l_dataout; + wire_nlOOOlOii_dataout <= wire_n111101i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOil_dataout <= wire_n111101l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOiO_dataout <= wire_n111101O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOl_dataout <= wire_n11O1Ol_dataout WHEN niOO00ili = '1' ELSE wire_n111l0O_dataout; + wire_nlOOOlOli_dataout <= wire_n111100i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOll_dataout <= wire_n111100l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOlO_dataout <= wire_n111100O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOO_dataout <= wire_n11O1OO_dataout WHEN niOO00ili = '1' ELSE wire_n111lii_dataout; + wire_nlOOOlOOi_dataout <= wire_n11110ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOOl_dataout <= wire_n11110il_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOlOOO_dataout <= wire_n11110iO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO00i_dataout <= wire_n1111l0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO00l_dataout <= wire_n1111lii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO00O_dataout <= wire_n1111lil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO01i_dataout <= wire_n1111O0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO01l_dataout <= wire_n1111O0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO01O_dataout <= wire_n1111O0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0i_dataout <= wire_n11O00i_dataout WHEN niOO00ili = '1' ELSE wire_n111lll_dataout; + wire_nlOOOO0ii_dataout <= wire_n1111liO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0il_dataout <= wire_n1111lli_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0iO_dataout <= wire_n1111lll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0l_dataout <= wire_n11O00l_dataout WHEN niOO00ili = '1' ELSE wire_n111llO_dataout; + wire_nlOOOO0li_dataout <= wire_n1111llO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0ll_dataout <= wire_n1111lOi_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0lO_dataout <= wire_n1110l1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0O_dataout <= wire_n11O00O_dataout WHEN niOO00ili = '1' ELSE wire_n111lOi_dataout; + wire_nlOOOO0Oi_dataout <= wire_n1110ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0Ol_dataout <= wire_n1110iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO0OO_dataout <= wire_n1110i0i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO10i_dataout <= wire_n1111i0O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO10l_dataout <= wire_n1111iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO10O_dataout <= wire_n1111iil_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO11i_dataout <= wire_n11110li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO11l_dataout <= wire_n11110ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO11O_dataout <= wire_n1111i0l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1i_dataout <= wire_n11O01i_dataout WHEN niOO00ili = '1' ELSE wire_n111lil_dataout; + wire_nlOOOO1ii_dataout <= wire_n1111iiO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1il_dataout <= wire_n1111ili_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1iO_dataout <= wire_n1111ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1l_dataout <= wire_n11O01l_dataout WHEN niOO00ili = '1' ELSE wire_n111liO_dataout; + wire_nlOOOO1li_dataout <= wire_n1111ilO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1ll_dataout <= wire_n1111lOl_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1lO_dataout <= wire_n1111lOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1O_dataout <= wire_n11O01O_dataout WHEN niOO00ili = '1' ELSE wire_n111lli_dataout; + wire_nlOOOO1Oi_dataout <= wire_n1111O1i_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1Ol_dataout <= wire_n1111O1l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOO1OO_dataout <= wire_n1111O1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOi0i_dataout <= wire_n111001O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOi0l_dataout <= wire_n1110iOO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOi0O_dataout <= wire_n1110ill_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOi1i_dataout <= wire_n11100OO_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOi1l_dataout <= wire_n11100ll_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOi1O_dataout <= wire_n11100ii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOii_dataout <= wire_n11O0ii_dataout WHEN niOO00ili = '1' ELSE wire_n111lOl_dataout; + wire_nlOOOOiii_dataout <= wire_n1110iii_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOiil_dataout <= wire_n1110i1O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOiiO_dataout <= wire_n11100Ol_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOil_dataout <= wire_n11O0il_dataout WHEN niOO00ili = '1' ELSE wire_n111lOO_dataout; + wire_nlOOOOili_dataout <= wire_n11100li_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOill_dataout <= wire_n111000O_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOilO_dataout <= wire_n111001l_dataout AND NOT(wire_niO01lOO_dataout); + wire_nlOOOOiO_dataout <= wire_n11O0iO_dataout WHEN niOO00ili = '1' ELSE wire_n111O1i_dataout; + wire_nlOOOOiOi_dataout <= wire_nlOOOOiOl_dataout AND NOT(niOlO1O0i); + wire_nlOOOOiOl_dataout <= nlOOOi10i OR niOl01iOO; + wire_nlOOOOiOO_dataout <= (nlOOOi10l OR n1Oi1lii) AND nlOllll0l; + wire_nlOOOOl0i_dataout <= (nlOOOi1iO OR n0i000il) AND nlOllll0l; + wire_nlOOOOl0l_dataout <= (nlOOOi1li OR n0iOlOlO) AND nlOllll0l; + wire_nlOOOOl0O_dataout <= (nlOOOi1ll OR n0ll0l1i) AND nlOllll0l; + wire_nlOOOOl1i_dataout <= (nlOOOi10O OR n011l0ll) AND nlOllll0l; + wire_nlOOOOl1l_dataout <= (nlOOOi1ii OR n01O1OOO) AND nlOllll0l; + wire_nlOOOOl1O_dataout <= (nlOOOi1il OR n00ill0i) AND nlOllll0l; + wire_nlOOOOli_dataout <= wire_n11O0li_dataout WHEN niOO00ili = '1' ELSE wire_n111O1l_dataout; + wire_nlOOOOlii_dataout <= (nlOOOi1lO OR n0O0O00l) AND nlOllll0l; + wire_nlOOOOll_dataout <= wire_n11O0ll_dataout WHEN niOO00ili = '1' ELSE wire_n111O1O_dataout; + wire_nlOOOOlO_dataout <= wire_n11O0lO_dataout WHEN niOO00ili = '1' ELSE wire_n111O0i_dataout; + wire_nlOOOOO0i_dataout <= n0O0Ol0i WHEN niOl1O0li = '1' ELSE nlOOOi01i; + wire_nlOOOOO0l_dataout <= n0O0Ol0l WHEN niOl1O0li = '1' ELSE nlOOOi01l; + wire_nlOOOOO0O_dataout <= n0O0Ol0O WHEN niOl1O0li = '1' ELSE nlOOOi01O; + wire_nlOOOOO1i_dataout <= nlOOOi1Oi WHEN niOl1O0li = '1' ELSE (((((((wire_w_lg_niOl1O0iO23983w(0) OR wire_w_lg_niOl1O0il23984w(0)) OR wire_w_lg_niOl1O0ii23986w(0)) OR wire_w_lg_niOl1O00O23988w(0)) OR wire_w_lg_niOl1O00l23990w(0)) OR wire_w_lg_niOl1O00i23992w(0)) OR wire_w_lg_niOl1O01O23994w(0)) OR wire_w_lg_niOl1O01l23996w(0)); + wire_nlOOOOO1l_dataout <= n0O0Ol1l WHEN niOl1O0li = '1' ELSE nlOOOi1Ol; + wire_nlOOOOO1O_dataout <= n0O0Ol1O WHEN niOl1O0li = '1' ELSE nlOOOi1OO; + wire_nlOOOOOi_dataout <= wire_n11O0Oi_dataout WHEN niOO00ili = '1' ELSE wire_n111O0l_dataout; + wire_nlOOOOOii_dataout <= n0ll0OOi WHEN niOl1O0li = '1' ELSE nlOOOi00i; + wire_nlOOOOOil_dataout <= n0ll0OOl WHEN niOl1O0li = '1' ELSE nlOOOi00l; + wire_nlOOOOOiO_dataout <= n0ll0OOO WHEN niOl1O0li = '1' ELSE nlOOOi00O; + wire_nlOOOOOl_dataout <= wire_n11O0Ol_dataout WHEN niOO00ili = '1' ELSE wire_n111O0O_dataout; + wire_nlOOOOOli_dataout <= n0lli11i WHEN niOl1O0li = '1' ELSE nlOOOi0ii; + wire_nlOOOOOll_dataout <= n0lli11l WHEN niOl1O0li = '1' ELSE nlOOOi0il; + wire_nlOOOOOlO_dataout <= n0iOO0iO WHEN niOl1O0li = '1' ELSE nlOOOi0iO; + wire_nlOOOOOO_dataout <= wire_n11O0OO_dataout WHEN niOO00ili = '1' ELSE wire_n111Oii_dataout; + wire_nlOOOOOOi_dataout <= n0iOO0li WHEN niOl1O0li = '1' ELSE nlOOOi0li; + wire_nlOOOOOOl_dataout <= n0iOO0ll WHEN niOl1O0li = '1' ELSE nlOOOi0ll; + wire_nlOOOOOOO_dataout <= n0iOO0lO WHEN niOl1O0li = '1' ELSE nlOOOi0lO; + wire_n0000OiO_a <= ( n001iO0i & n001iO1O & n001iO1l & n001iO1i & n001ilOO & n001ilOl); + wire_n0000OiO_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n0000OiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n0000OiO_a, + b => wire_n0000OiO_b, + cin => wire_gnd, + o => wire_n0000OiO_o + ); + wire_n000l1il_a <= ( wire_n000l10O_dataout & wire_n000l10l_dataout & wire_n000l10i_dataout & wire_n000l11O_dataout & wire_n000l11l_dataout & wire_n000l11i_dataout & "1"); + wire_n000l1il_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n000l1il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n000l1il_a, + b => wire_n000l1il_b, + cin => wire_gnd, + o => wire_n000l1il_o + ); + wire_n0010iil_a <= ( n00100iO & n00100il & n00100ii & n01OO0iO); + wire_n0010iil_b <= ( "0" & "0" & "0" & "1"); + n0010iil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n0010iil_a, + b => wire_n0010iil_b, + cin => wire_gnd, + o => wire_n0010iil_o + ); + wire_n0011OOl_a <= ( n01OO0il & n01OO0ii & n01OO00O & n01OO00l & "1"); + wire_n0011OOl_b <= ( "1" & "1" & "1" & "0" & "1"); + n0011OOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0011OOl_a, + b => wire_n0011OOl_b, + cin => wire_gnd, + o => wire_n0011OOl_o + ); + wire_n001i0Ol_a <= ( n001i10O & n001i10l & n001i10i & n001i11O & n001i11l & n001i11i & n0010l0i); + wire_n001i0Ol_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n001i0Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n001i0Ol_a, + b => wire_n001i0Ol_b, + cin => wire_gnd, + o => wire_n001i0Ol_o + ); + wire_n001li0i_a <= ( n001illO & n001illl & n001illi & n001iliO & n001ilil & n001ilii & n001il0O); + wire_n001li0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n001li0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n001li0i_a, + b => wire_n001li0i_b, + cin => wire_gnd, + o => wire_n001li0i_o + ); + wire_n00il11O_a <= ( n00iiliO & n00iilil); + wire_n00il11O_b <= ( "0" & "1"); + n00il11O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n00il11O_a, + b => wire_n00il11O_b, + cin => wire_gnd, + o => wire_n00il11O_o + ); + wire_n00ililO_a <= ( n00il1Ol & n00il1Oi & n00il1lO & n00il1ll & "1"); + wire_n00ililO_b <= ( "1" & "1" & "1" & "0" & "1"); + n00ililO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n00ililO_a, + b => wire_n00ililO_b, + cin => wire_gnd, + o => wire_n00ililO_o + ); + wire_n00l11lO_a <= ( n00illlO & n00illll & n00illli & n00illiO & n00illil & n00illii & n00ill0O & n00ill0l); + wire_n00l11lO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n00l11lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n00l11lO_a, + b => wire_n00l11lO_b, + cin => wire_gnd, + o => wire_n00l11lO_o + ); + wire_n00lll1O_a <= ( n00l0OlO & n00l0Oll & n00l0Oli & n00l0OiO & "1"); + wire_n00lll1O_b <= ( "1" & "1" & "1" & "0" & "1"); + n00lll1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n00lll1O_a, + b => wire_n00lll1O_b, + cin => wire_gnd, + o => wire_n00lll1O_o + ); + wire_n00lO1lO_a <= ( n00llOOi & n00llOlO & n00llOll & n00l0OOi); + wire_n00lO1lO_b <= ( "0" & "0" & "0" & "1"); + n00lO1lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n00lO1lO_a, + b => wire_n00lO1lO_b, + cin => wire_gnd, + o => wire_n00lO1lO_o + ); + wire_n00O01il_a <= ( n00O1i1i & n00O10OO & n00O10Ol & n00O10Oi & n00O10lO & n00O10ll & n00O10li); + wire_n00O01il_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n00O01il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n00O01il_a, + b => wire_n00O01il_b, + cin => wire_gnd, + o => wire_n00O01il_o + ); + wire_n00O111O_a <= ( n00lOlli & n00lOliO & n00lOlil & n00lOlii & n00lOl0O & n00lOl0l & n00lO0il); + wire_n00O111O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n00O111O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n00O111O_a, + b => wire_n00O111O_b, + cin => wire_gnd, + o => wire_n00O111O_o + ); + wire_n00OOiOi_a <= ( n00O1iil & n00O1iii & n00O1i0O & n00O1i0l & n00O1i0i & n00O1i1O); + wire_n00OOiOi_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n00OOiOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n00OOiOi_a, + b => wire_n00OOiOi_b, + cin => wire_gnd, + o => wire_n00OOiOi_o + ); + wire_n010l0li_a <= ( n0100l0i & n0100l1O & n0100l1l & n0100l1i & "1"); + wire_n010l0li_b <= ( "1" & "1" & "1" & "0" & "1"); + n010l0li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n010l0li_a, + b => wire_n010l0li_b, + cin => wire_gnd, + o => wire_n010l0li_o + ); + wire_n010lO0i_a <= ( n010ll0l & n010ll0i & n010ll1O & n0100l0l); + wire_n010lO0i_b <= ( "0" & "0" & "0" & "1"); + n010lO0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n010lO0i_a, + b => wire_n010lO0i_b, + cin => wire_gnd, + o => wire_n010lO0i_o + ); + wire_n010Olli_a <= ( n010Oi1l & n010Oi1i & n010O0OO & n010O0Ol & n010O0Oi & n010O0lO & n010lOOO); + wire_n010Olli_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n010Olli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n010Olli_a, + b => wire_n010Olli_b, + cin => wire_gnd, + o => wire_n010Olli_o + ); + wire_n011illi_a <= ( n011ii1i & n011i0OO); + wire_n011illi_b <= ( "0" & "1"); + n011illi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n011illi_a, + b => wire_n011illi_b, + cin => wire_gnd, + o => wire_n011illi_o + ); + wire_n011l00i_a <= ( n011iO0O & n011iO0l & n011iO0i & n011iO1O & "1"); + wire_n011l00i_b <= ( "1" & "1" & "1" & "0" & "1"); + n011l00i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n011l00i_a, + b => wire_n011l00i_b, + cin => wire_gnd, + o => wire_n011l00i_o + ); + wire_n011OO0i_a <= ( n011li0i & n011li1O & n011li1l & n011li1i & n011l0OO & n011l0Ol & n011l0Oi & n011l0lO); + wire_n011OO0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n011OO0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n011OO0i_a, + b => wire_n011OO0i_b, + cin => wire_gnd, + o => wire_n011OO0i_o + ); + wire_n01i1lOO_a <= ( n01i11il & n01i11ii & n01i110O & n01i110l & n01i110i & n01i111O & n01i111l); + wire_n01i1lOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n01i1lOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n01i1lOO_a, + b => wire_n01i1lOO_b, + cin => wire_gnd, + o => wire_n01i1lOO_o + ); + wire_n01iO00l_a <= ( n01i11OO & n01i11Ol & n01i11Oi & n01i11lO & n01i11ll & n01i11li); + wire_n01iO00l_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n01iO00l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n01iO00l_a, + b => wire_n01iO00l_b, + cin => wire_gnd, + o => wire_n01iO00l_o + ); + wire_n01l1i0i_a <= ( wire_n01l1i1l_dataout & wire_n01l1i1i_dataout & wire_n01l10OO_dataout & wire_n01l10Ol_dataout & wire_n01l10Oi_dataout & wire_n01l10lO_dataout & "1"); + wire_n01l1i0i_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n01l1i0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n01l1i0i_a, + b => wire_n01l1i0i_b, + cin => wire_gnd, + o => wire_n01l1i0i_o + ); + wire_n01O10Ol_a <= ( n01O110l & n01O110i); + wire_n01O10Ol_b <= ( "0" & "1"); + n01O10Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n01O10Ol_a, + b => wire_n01O10Ol_b, + cin => wire_gnd, + o => wire_n01O10Ol_o + ); + wire_n01O1Oil_a <= ( n01O1ili & n01O1iiO & n01O1iil & n01O1iii & "1"); + wire_n01O1Oil_b <= ( "1" & "1" & "1" & "0" & "1"); + n01O1Oil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n01O1Oil_a, + b => wire_n01O1Oil_b, + cin => wire_gnd, + o => wire_n01O1Oil_o + ); + wire_n01Oiiil_a <= ( n01O01il & n01O01ii & n01O010O & n01O010l & n01O010i & n01O011O & n01O011l & n01O011i); + wire_n01Oiiil_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n01Oiiil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n01Oiiil_a, + b => wire_n01Oiiil_b, + cin => wire_gnd, + o => wire_n01Oiiil_o + ); + wire_n0i0001i_a <= ( n0i01O1O & n0i01O1l & n0i01O1i & n0i01lOO & "1"); + wire_n0i0001i_b <= ( "1" & "1" & "1" & "0" & "1"); + n0i0001i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0i0001i_a, + b => wire_n0i0001i_b, + cin => wire_gnd, + o => wire_n0i0001i_o + ); + wire_n0i01lii_a <= ( n0i010Oi & n0i010lO); + wire_n0i01lii_b <= ( "0" & "1"); + n0i01lii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n0i01lii_a, + b => wire_n0i01lii_b, + cin => wire_gnd, + o => wire_n0i01lii_o + ); + wire_n0i0iO1i_a <= ( n0i00i1i & n0i000OO & n0i000Ol & n0i000Oi & n0i000lO & n0i000ll & n0i000li & n0i000iO); + wire_n0i0iO1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0i0iO1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n0i0iO1i_a, + b => wire_n0i0iO1i_b, + cin => wire_gnd, + o => wire_n0i0iO1i_o + ); + wire_n0i11llO_a <= ( wire_n0i11lli_dataout & wire_n0i11liO_dataout & wire_n0i11lil_dataout & wire_n0i11lii_dataout & wire_n0i11l0O_dataout & wire_n0i11l0l_dataout & "1"); + wire_n0i11llO_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n0i11llO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0i11llO_a, + b => wire_n0i11llO_b, + cin => wire_gnd, + o => wire_n0i11llO_o + ); + wire_n0ii00ii_a <= ( n0i0Ol1i & n0i0OiOO & n0i0OiOl & n0i0OiOi & "1"); + wire_n0ii00ii_b <= ( "1" & "1" & "1" & "0" & "1"); + n0ii00ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0ii00ii_a, + b => wire_n0ii00ii_b, + cin => wire_gnd, + o => wire_n0ii00ii_o + ); + wire_n0ii0O1i_a <= ( n0ii0l1l & n0ii0l1i & n0ii0iOO & n0i0Ol1l); + wire_n0ii0O1i_b <= ( "0" & "0" & "0" & "1"); + n0ii0O1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n0ii0O1i_a, + b => wire_n0ii0O1i_b, + cin => wire_gnd, + o => wire_n0ii0O1i_o + ); + wire_n0iiilii_a <= ( n0iii0Ol & n0iii0Oi & n0iii0lO & n0iii0ll & n0iii0li & n0iii0iO & n0ii0OlO); + wire_n0iiilii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0iiilii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0iiilii_a, + b => wire_n0iiilii_b, + cin => wire_gnd, + o => wire_n0iiilii_o + ); + wire_n0iilllO_a <= ( n0iil10l & n0iil10i & n0iil11O & n0iil11l & n0iil11i & n0iiiOOO & n0iiiOOl); + wire_n0iilllO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0iilllO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0iilllO_a, + b => wire_n0iilllO_b, + cin => wire_gnd, + o => wire_n0iilllO_o + ); + wire_n0ili01l_a <= ( n0iil1lO & n0iil1ll & n0iil1li & n0iil1iO & n0iil1il & n0iil1ii); + wire_n0ili01l_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n0ili01l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n0ili01l_a, + b => wire_n0ili01l_b, + cin => wire_gnd, + o => wire_n0ili01l_o + ); + wire_n0illi1i_a <= ( wire_n0ill0Ol_dataout & wire_n0ill0Oi_dataout & wire_n0ill0lO_dataout & wire_n0ill0ll_dataout & wire_n0ill0li_dataout & wire_n0ill0iO_dataout & "1"); + wire_n0illi1i_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n0illi1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0illi1i_a, + b => wire_n0illi1i_b, + cin => wire_gnd, + o => wire_n0illi1i_o + ); + wire_n0iOl0ll_a <= ( n0iOl11l & n0iOl11i); + wire_n0iOl0ll_b <= ( "0" & "1"); + n0iOl0ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n0iOl0ll_a, + b => wire_n0iOl0ll_b, + cin => wire_gnd, + o => wire_n0iOl0ll_o + ); + wire_n0iOlO0l_a <= ( n0iOliii & n0iOli0O & n0iOli0l & n0iOli0i & "1"); + wire_n0iOlO0l_b <= ( "1" & "1" & "1" & "0" & "1"); + n0iOlO0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0iOlO0l_a, + b => wire_n0iOlO0l_b, + cin => wire_gnd, + o => wire_n0iOlO0l_o + ); + wire_n0l00i1i_a <= ( n0l01liO & n0l01lil & n0l01lii & n0l01l0O & n0l01l0l & n0l01l0i & n0l01l1O); + wire_n0l00i1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0l00i1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0l00i1i_a, + b => wire_n0l00i1i_b, + cin => wire_gnd, + o => wire_n0l00i1i_o + ); + wire_n0l010ll_a <= ( n0l0111O & n0l0111l & n0l0111i & n0l1OOOO & n0l1OOOl & n0l1OOOi & n0l1Ol1i); + wire_n0l010ll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0l010ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0l010ll_a, + b => wire_n0l010ll_b, + cin => wire_gnd, + o => wire_n0l010ll_o + ); + wire_n0l0OO0O_a <= ( n0l01O1i & n0l01lOO & n0l01lOl & n0l01lOi & n0l01llO & n0l01lll); + wire_n0l0OO0O_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n0l0OO0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n0l0OO0O_a, + b => wire_n0l0OO0O_b, + cin => wire_gnd, + o => wire_n0l0OO0O_o + ); + wire_n0l11i0l_a <= ( n0iOO10l & n0iOO10i & n0iOO11O & n0iOO11l & n0iOO11i & n0iOlOOO & n0iOlOOl & n0iOlOOi); + wire_n0l11i0l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0l11i0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n0l11i0l_a, + b => wire_n0l11i0l_b, + cin => wire_gnd, + o => wire_n0l11i0l_o + ); + wire_n0l1lOll_a <= ( n0l1i00l & n0l1i00i & n0l1i01O & n0l1i01l & "1"); + wire_n0l1lOll_b <= ( "1" & "1" & "1" & "0" & "1"); + n0l1lOll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0l1lOll_a, + b => wire_n0l1lOll_b, + cin => wire_gnd, + o => wire_n0l1lOll_o + ); + wire_n0l1Oi0l_a <= ( n0l1O00O & n0l1O00l & n0l1O00i & n0l1i00O); + wire_n0l1Oi0l_b <= ( "0" & "0" & "0" & "1"); + n0l1Oi0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n0l1Oi0l_a, + b => wire_n0l1Oi0l_b, + cin => wire_gnd, + o => wire_n0l1Oi0l_o + ); + wire_n0li010l_a <= ( wire_n0li011O_dataout & wire_n0li011l_dataout & wire_n0li011i_dataout & wire_n0li1OOO_dataout & wire_n0li1OOl_dataout & wire_n0li1OOi_dataout & "1"); + wire_n0li010l_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n0li010l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0li010l_a, + b => wire_n0li010l_b, + cin => wire_gnd, + o => wire_n0li010l_o + ); + wire_n0ll0iiO_a <= ( n0ll01ll & n0ll01li & n0ll01iO & n0ll01il & "1"); + wire_n0ll0iiO_b <= ( "1" & "1" & "1" & "0" & "1"); + n0ll0iiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0ll0iiO_a, + b => wire_n0ll0iiO_b, + cin => wire_gnd, + o => wire_n0ll0iiO_o + ); + wire_n0ll1OOO_a <= ( n0ll1l0O & n0ll1l0l); + wire_n0ll1OOO_b <= ( "0" & "1"); + n0ll1OOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n0ll1OOO_a, + b => wire_n0ll1OOO_b, + cin => wire_gnd, + o => wire_n0ll1OOO_o + ); + wire_n0lll1iO_a <= ( n0ll0liO & n0ll0lil & n0ll0lii & n0ll0l0O & n0ll0l0l & n0ll0l0i & n0ll0l1O & n0ll0l1l); + wire_n0lll1iO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0lll1iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n0lll1iO_a, + b => wire_n0lll1iO_b, + cin => wire_gnd, + o => wire_n0lll1iO_o + ); + wire_n0lO0iOO_a <= ( n0llOOiO & n0llOOil & n0llOOii & n0llOO0O & "1"); + wire_n0lO0iOO_b <= ( "1" & "1" & "1" & "0" & "1"); + n0lO0iOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0lO0iOO_a, + b => wire_n0lO0iOO_b, + cin => wire_gnd, + o => wire_n0lO0iOO_o + ); + wire_n0lOi1iO_a <= ( n0lO0Oli & n0lO0OiO & n0lO0Oil & n0llOOli); + wire_n0lOi1iO_b <= ( "0" & "0" & "0" & "1"); + n0lOi1iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n0lOi1iO_a, + b => wire_n0lOi1iO_b, + cin => wire_gnd, + o => wire_n0lOi1iO_o + ); + wire_n0lOiOOO_a <= ( n0lOilii & n0lOil0O & n0lOil0l & n0lOil0i & n0lOil1O & n0lOil1l & n0lOi00l); + wire_n0lOiOOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0lOiOOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0lOiOOO_a, + b => wire_n0lOiOOO_b, + cin => wire_gnd, + o => wire_n0lOiOOO_o + ); + wire_n0lOO10l_a <= ( n0lOl0Oi & n0lOl0lO & n0lOl0ll & n0lOl0li & n0lOl0iO & n0lOl0il & n0lOl0ii); + wire_n0lOO10l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0lOO10l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0lOO10l_a, + b => wire_n0lOO10l_b, + cin => wire_gnd, + o => wire_n0lOO10l_o + ); + wire_n0O0ll0i_a <= ( n0O0l0li & n0O0l0iO); + wire_n0O0ll0i_b <= ( "0" & "1"); + n0O0ll0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n0O0ll0i_a, + b => wire_n0O0ll0i_b, + cin => wire_gnd, + o => wire_n0O0ll0i_o + ); + wire_n0O0O1Oi_a <= ( n0O0llOO & n0O0llOl & n0O0llOi & n0O0lllO & "1"); + wire_n0O0O1Oi_b <= ( "1" & "1" & "1" & "0" & "1"); + n0O0O1Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0O0O1Oi_a, + b => wire_n0O0O1Oi_b, + cin => wire_gnd, + o => wire_n0O0O1Oi_o + ); + wire_n0O1iili_a <= ( n0lOli0l & n0lOli0i & n0lOli1O & n0lOli1l & n0lOli1i & n0lOl0OO); + wire_n0O1iili_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n0O1iili : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n0O1iili_a, + b => wire_n0O1iili_b, + cin => wire_gnd, + o => wire_n0O1iili_o + ); + wire_n0O1lliO_a <= ( wire_n0O1llii_dataout & wire_n0O1ll0O_dataout & wire_n0O1ll0l_dataout & wire_n0O1ll0i_dataout & wire_n0O1ll1O_dataout & wire_n0O1ll1l_dataout & "1"); + wire_n0O1lliO_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n0O1lliO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0O1lliO_a, + b => wire_n0O1lliO_b, + cin => wire_gnd, + o => wire_n0O1lliO_o + ); + wire_n0Oi1lOi_a <= ( n0O0O0Oi & n0O0O0lO & n0O0O0ll & n0O0O0li & n0O0O0iO & n0O0O0il & n0O0O0ii & n0O0O00O); + wire_n0Oi1lOi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0Oi1lOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n0Oi1lOi_a, + b => wire_n0Oi1lOi_b, + cin => wire_gnd, + o => wire_n0Oi1lOi_o + ); + wire_n0OiO00i_a <= ( n0OiiiOi & n0OiiilO & n0Oiiill & n0Oiiili & "1"); + wire_n0OiO00i_b <= ( "1" & "1" & "1" & "0" & "1"); + n0OiO00i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n0OiO00i_a, + b => wire_n0OiO00i_b, + cin => wire_gnd, + o => wire_n0OiO00i_o + ); + wire_n0OiOlOi_a <= ( n0OiOiOl & n0OiOiOi & n0OiOilO & n0OiiiOl); + wire_n0OiOlOi_b <= ( "0" & "0" & "0" & "1"); + n0OiOlOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n0OiOlOi_a, + b => wire_n0OiOlOi_b, + cin => wire_gnd, + o => wire_n0OiOlOi_o + ); + wire_n0Ol0liO_a <= ( n0Ol011l & n0Ol011i & n0Ol1OOO & n0Ol1OOl & n0Ol1OOi & n0Ol1OlO & n0Ol1Oll); + wire_n0Ol0liO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0Ol0liO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0Ol0liO_a, + b => wire_n0Ol0liO_b, + cin => wire_gnd, + o => wire_n0Ol0liO_o + ); + wire_n0Ol1l0i_a <= ( n0Ol10ll & n0Ol10li & n0Ol10iO & n0Ol10il & n0Ol10ii & n0Ol100O & n0OiOOiO); + wire_n0Ol1l0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n0Ol1l0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0Ol1l0i_a, + b => wire_n0Ol1l0i_b, + cin => wire_gnd, + o => wire_n0Ol1l0i_o + ); + wire_n0OO00Oi_a <= ( wire_n0OO00ll_dataout & wire_n0OO00li_dataout & wire_n0OO00iO_dataout & wire_n0OO00il_dataout & wire_n0OO00ii_dataout & wire_n0OO000O_dataout & "1"); + wire_n0OO00Oi_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n0OO00Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n0OO00Oi_a, + b => wire_n0OO00Oi_b, + cin => wire_gnd, + o => wire_n0OO00Oi_o + ); + wire_n0OO11Ol_a <= ( n0Ol01iO & n0Ol01il & n0Ol01ii & n0Ol010O & n0Ol010l & n0Ol010i); + wire_n0OO11Ol_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n0OO11Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n0OO11Ol_a, + b => wire_n0OO11Ol_b, + cin => wire_gnd, + o => wire_n0OO11Ol_o + ); + wire_n110100O_a <= ( "0" & wire_nlOii0Oii_dataout & "0" & "0" & "0" & "0" & wire_nlOlOi1lO_dataout & wire_nlOlOi1ll_dataout & wire_nlOlOi1li_dataout & wire_nlOlOi1iO_dataout & wire_nlOlOi1il_dataout & wire_nlOlOi1ii_dataout & wire_nlOlOi10O_dataout & wire_nlOlOi10l_dataout & "1"); + wire_n110100O_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n110100O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 15, + width_b => 15, + width_o => 15 + ) + PORT MAP ( + a => wire_n110100O_a, + b => wire_n110100O_b, + cin => wire_gnd, + o => wire_n110100O_o + ); + wire_n11010li_a <= ( "0" & wire_nlOii0Oii_dataout & "0" & "0" & "0" & "0" & wire_nlOlOi1lO_dataout & wire_nlOlOi1ll_dataout & wire_nlOlOi1li_dataout & wire_nlOlOi1iO_dataout & wire_nlOlOi1il_dataout & wire_nlOlOi1ii_dataout & wire_nlOlOi10O_dataout & "1"); + wire_n11010li_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n11010li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 14, + width_b => 14, + width_o => 14 + ) + PORT MAP ( + a => wire_n11010li_a, + b => wire_n11010li_b, + cin => wire_gnd, + o => wire_n11010li_o + ); + wire_n11ilO1i_a <= ( n110OOll & n110OOli & n110OOiO & n110OOil & "1"); + wire_n11ilO1i_b <= ( "1" & "1" & "1" & "0" & "1"); + n11ilO1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n11ilO1i_a, + b => wire_n11ilO1i_b, + cin => wire_gnd, + o => wire_n11ilO1i_o + ); + wire_n11ll01O_a <= ( n11li11l & n11li11i & n11l0OOO & "1"); + wire_n11ll01O_b <= ( "1" & "1" & "0" & "1"); + n11ll01O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n11ll01O_a, + b => wire_n11ll01O_b, + cin => wire_gnd, + o => wire_n11ll01O_o + ); + wire_n1iiOl0l_a <= ( n1iillil & n1iillii & n1iill0O & n1iill0l & n1iill0i & n1iill1O & n1iill1l & n1iill1i & n1iiliOO & n1iiliOl & n1iiliOi & n1iililO & n1iilill & n1iilili & n1iiliiO & n1iiliil & n1iiliii & n1iili0O & n1iili0l & n11Oi0ii & "1"); + wire_n1iiOl0l_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1iiOl0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 21, + width_b => 21, + width_o => 21 + ) + PORT MAP ( + a => wire_n1iiOl0l_a, + b => wire_n1iiOl0l_b, + cin => wire_gnd, + o => wire_n1iiOl0l_o + ); + wire_n1il11ii_a <= ( n1iiOlli & n1iiOliO & n1iiOlil & n1iiOlii & n1iillli & "1"); + wire_n1il11ii_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + n1il11ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n1il11ii_a, + b => wire_n1il11ii_b, + cin => wire_gnd, + o => wire_n1il11ii_o + ); + wire_n1ill0Oi_a <= ( n1il1i0l & n1il1i0i & n1il1i1O & n1il1i1l & n1il1i1i & n1il10OO & n1il10Ol & n1il10Oi & n1il10lO & n1il10ll & n1il10li & n1il10iO & n1il10il & n1il10ii & n1il100O & n1il100l & n1il100i & n1il101O & n1il101l & "1"); + wire_n1ill0Oi_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1ill0Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 20, + width_b => 20, + width_o => 20 + ) + PORT MAP ( + a => wire_n1ill0Oi_a, + b => wire_n1ill0Oi_b, + cin => wire_gnd, + o => wire_n1ill0Oi_o + ); + wire_n1ilOlOl_a <= ( n1illOii & n1illO0O & n1illO0l & n1illO0i & n1illO1O & n1illO1l & n1illO1i & n1illlOO & n1illlOl & n1illlOi & n1illllO & n1illlll & n1illlli & n1illliO & n1illlil & n1illlii & n1illl0O & n1illl0l & n1illl0i & n1illl1O & "1"); + wire_n1ilOlOl_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1ilOlOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 21, + width_b => 21, + width_o => 21 + ) + PORT MAP ( + a => wire_n1ilOlOl_a, + b => wire_n1ilOlOl_b, + cin => wire_gnd, + o => wire_n1ilOlOl_o + ); + wire_n1ilOlOO_a <= ( k_cnt(84 DOWNTO 65) & "1"); + wire_n1ilOlOO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1ilOlOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 21, + width_b => 21, + width_o => 21 + ) + PORT MAP ( + a => wire_n1ilOlOO_a, + b => wire_n1ilOlOO_b, + cin => wire_gnd, + o => wire_n1ilOlOO_o + ); + wire_n1iO0i1O_a <= ( n1iO001i & n1iO01OO & n1iO01Ol & n1iO01Oi & n1iO11iO & "1"); + wire_n1iO0i1O_b <= ( "1" & "1" & "1" & "1" & "0" & "1"); + n1iO0i1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n1iO0i1O_a, + b => wire_n1iO0i1O_b, + cin => wire_gnd, + o => wire_n1iO0i1O_o + ); + wire_n1iO1lOl_a <= ( n1iO11il & n1iO11ii & n1iO110O & n1iO110l & n1iO110i & n1iO111O & "1"); + wire_n1iO1lOl_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1iO1lOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n1iO1lOl_a, + b => wire_n1iO1lOl_b, + cin => wire_gnd, + o => wire_n1iO1lOl_o + ); + wire_n1iOi1Oi_a <= ( n1iO0l0l & n1iO0l0i & n1iO0l1O & n1iO0l1l & n1iO0l1i & n1iO0iOO & n1iO0iOl & n1iO0iOi & n1iO0ilO & n1iO0ill & n1iO0ili & n1iO001l & "1"); + wire_n1iOi1Oi_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1iOi1Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_n1iOi1Oi_a, + b => wire_n1iOi1Oi_b, + cin => wire_gnd, + o => wire_n1iOi1Oi_o + ); + wire_n1iOO1li_a <= ( n1iOl1iO & n1iOl1il & n1iOl1ii & n1iOl10O & n1iOl10l & n1iOl10i); + wire_n1iOO1li_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n1iOO1li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n1iOO1li_a, + b => wire_n1iOO1li_b, + cin => wire_gnd, + o => wire_n1iOO1li_o + ); + wire_n1iOOOil_a <= ( n1iOl0Oi & n1iOl0lO & n1iOl0ll & n1iOl0li & n1iOl0iO & n1iOl0il & n1iOl0ii & n1iOl00O & n1iOl00l & n1iOl00i & n1iOl01O & n1iOl01l & n1iOl01i & n1iOl1OO & n1iOl1Ol & n1iOl1Oi & n1iOl1lO & n1iOl1ll & n1iOl1li); + wire_n1iOOOil_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n1iOOOil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 19, + width_b => 19, + width_o => 19 + ) + PORT MAP ( + a => wire_n1iOOOil_a, + b => wire_n1iOOOil_b, + cin => wire_gnd, + o => wire_n1iOOOil_o + ); + wire_n1l010Ol_a <= ( n1l1OO1l & n1l1OO1i & "1"); + wire_n1l010Ol_b <= ( "1" & "0" & "1"); + n1l010Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_n1l010Ol_a, + b => wire_n1l010Ol_b, + cin => wire_gnd, + o => wire_n1l010Ol_o + ); + wire_n1l01i1l_a <= ( n1l1OO1l & n1l1OO1i); + wire_n1l01i1l_b <= ( "0" & "1"); + n1l01i1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n1l01i1l_a, + b => wire_n1l01i1l_b, + cin => wire_gnd, + o => wire_n1l01i1l_o + ); + wire_n1l01iii_a(0) <= ( n1l1OO1l); + wire_n1l01iii_b <= ( "1"); + n1l01iii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 1, + width_b => 1, + width_o => 1 + ) + PORT MAP ( + a => wire_n1l01iii_a, + b => wire_n1l01iii_b, + cin => wire_gnd, + o => wire_n1l01iii_o + ); + wire_n1l01O1i_a <= ( n1l1OOOi & n1l1OOlO & n1l1OOll & n1l1OOli & n1l1OOiO & n1l1OOil & n1l1OOii & n1l1OO0O & n1l1OO0l & n1l1OO0i & n1l1OO1O & "1"); + wire_n1l01O1i_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1l01O1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_n1l01O1i_a, + b => wire_n1l01O1i_b, + cin => wire_gnd, + o => wire_n1l01O1i_o + ); + wire_n1l1Ol1O_a <= ( n1l1O1Ol & n1l1O1Oi & n1l1O1lO & n1l1O1ll & n1l1O1li & n1l1O1iO & n1l1O1il & n1l1Ol0l); + wire_n1l1Ol1O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n1l1Ol1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n1l1Ol1O_a, + b => wire_n1l1Ol1O_b, + cin => wire_gnd, + o => wire_n1l1Ol1O_o + ); + wire_n1lii0ll_a <= ( n1l0011O & n1l0011l); + wire_n1lii0ll_b <= ( "0" & "1"); + n1lii0ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n1lii0ll_a, + b => wire_n1lii0ll_b, + cin => wire_gnd, + o => wire_n1lii0ll_o + ); + wire_n1lil0li_a <= ( n1l00i1O & n1l00i1l & n1l00i1i & n1l000OO & "1"); + wire_n1lil0li_b <= ( "1" & "1" & "1" & "0" & "1"); + n1lil0li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1lil0li_a, + b => wire_n1lil0li_b, + cin => wire_gnd, + o => wire_n1lil0li_o + ); + wire_n1lil1ll_a <= ( n1l000Ol & n1l000Oi & n1l000lO & n1l000ll & "1"); + wire_n1lil1ll_b <= ( "1" & "1" & "1" & "0" & "1"); + n1lil1ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1lil1ll_a, + b => wire_n1lil1ll_b, + cin => wire_gnd, + o => wire_n1lil1ll_o + ); + wire_n1lil1lO_a <= ( k_conf(343 DOWNTO 341) & "1"); + wire_n1lil1lO_b <= ( "1" & "1" & "0" & "1"); + n1lil1lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n1lil1lO_a, + b => wire_n1lil1lO_b, + cin => wire_gnd, + o => wire_n1lil1lO_o + ); + wire_n1lOilOl_a <= ( n1lOi1Ol & n1lOi1Oi & n1lOi1lO & "1"); + wire_n1lOilOl_b <= ( "1" & "1" & "0" & "1"); + n1lOilOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n1lOilOl_a, + b => wire_n1lOilOl_b, + cin => wire_gnd, + o => wire_n1lOilOl_o + ); + wire_n1O100i_a <= ( n1lOlOi & niOO00Oll & niOO00Oli & niOO00OiO & "1"); + wire_n1O100i_b <= ( wire_ni01lOi_w_lg_n1lOO1l3771w & wire_w_lg_niOO00OOl3742w & wire_w_lg_niOO00Oil3768w & wire_w_lg_niOO00Oii3766w & "1"); + n1O100i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1O100i_a, + b => wire_n1O100i_b, + cin => wire_gnd, + o => wire_n1O100i_o + ); + wire_n1O1iOi_a <= ( n1O1Oll & niOO0i10O & niOO0i1il & niOO0i1li & "1"); + wire_n1O1iOi_b <= ( wire_ni1lOlO_w_lg_n1O1lOl3726w & wire_w_lg_niOO0i10l3724w & wire_w_lg_niOO0i1ii3722w & wire_w_lg_niOO0i1iO3720w & "1"); + n1O1iOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1O1iOi_a, + b => wire_n1O1iOi_b, + cin => wire_gnd, + o => wire_n1O1iOi_o + ); + wire_n1Oi110O_a <= ( n1O0OllO & n1O0Olll); + wire_n1Oi110O_b <= ( "0" & "1"); + n1Oi110O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_n1Oi110O_a, + b => wire_n1Oi110O_b, + cin => wire_gnd, + o => wire_n1Oi110O_o + ); + wire_n1Oi1iOO_a <= ( n1Oi101l & n1Oi101i & n1Oi11OO & n1Oi11Ol & "1"); + wire_n1Oi1iOO_b <= ( "1" & "1" & "1" & "0" & "1"); + n1Oi1iOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1Oi1iOO_a, + b => wire_n1Oi1iOO_b, + cin => wire_gnd, + o => wire_n1Oi1iOO_o + ); + wire_n1Oii1OO_a <= ( n1Oi1lOO & n1Oi1lOl & n1Oi1lOi & n1Oi1llO & n1Oi1lll & n1Oi1lli & n1Oi1liO & n1Oi1lil); + wire_n1Oii1OO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n1Oii1OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_n1Oii1OO_a, + b => wire_n1Oii1OO_b, + cin => wire_gnd, + o => wire_n1Oii1OO_o + ); + wire_n1Ol01OO_a <= ( n1Ol011i & n1Ol1OOO & n1Ol1OOl & n1OiO11i); + wire_n1Ol01OO_b <= ( "0" & "0" & "0" & "1"); + n1Ol01OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_n1Ol01OO_a, + b => wire_n1Ol01OO_b, + cin => wire_gnd, + o => wire_n1Ol01OO_o + ); + wire_n1Ol1l0O_a <= ( n1OilOOO & n1OilOOl & n1OilOOi & n1OilOlO & "1"); + wire_n1Ol1l0O_b <= ( "1" & "1" & "1" & "0" & "1"); + n1Ol1l0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_n1Ol1l0O_a, + b => wire_n1Ol1l0O_b, + cin => wire_gnd, + o => wire_n1Ol1l0O_o + ); + wire_n1Oli10O_a <= ( n1Ol0lOi & n1Ol0llO & n1Ol0lll & n1Ol0lli & n1Ol0liO & n1Ol0lil & n1Ol00ll); + wire_n1Oli10O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n1Oli10O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n1Oli10O_a, + b => wire_n1Oli10O_b, + cin => wire_gnd, + o => wire_n1Oli10O_o + ); + wire_n1Oll1ll_a <= ( n1Olii0i & n1Olii1O & n1Olii1l & n1Olii1i & n1Oli0OO & n1Oli0Ol & n1Oli0Oi); + wire_n1Oll1ll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + n1Oll1ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n1Oll1ll_a, + b => wire_n1Oll1ll_b, + cin => wire_gnd, + o => wire_n1Oll1ll_o + ); + wire_n1OO0l1i_a <= ( n1Oliill & n1Oliili & n1OliiiO & n1Oliiil & n1Oliiii & n1Olii0O); + wire_n1OO0l1i_b <= ( "0" & "0" & "0" & "0" & "0" & "1"); + n1OO0l1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6, + width_o => 6 + ) + PORT MAP ( + a => wire_n1OO0l1i_a, + b => wire_n1OO0l1i_b, + cin => wire_gnd, + o => wire_n1OO0l1i_o + ); + wire_n1OOilOO_a <= ( wire_n1OOilOi_dataout & wire_n1OOillO_dataout & wire_n1OOilll_dataout & wire_n1OOilli_dataout & wire_n1OOiliO_dataout & wire_n1OOilil_dataout & "1"); + wire_n1OOilOO_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + n1OOilOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_n1OOilOO_a, + b => wire_n1OOilOO_b, + cin => wire_gnd, + o => wire_n1OOilOO_o + ); + wire_ni00lO0O_a <= ( ni00ll1i & ni00liOO & ni00liOl); + wire_ni00lO0O_b <= ( "0" & "0" & "1"); + ni00lO0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni00lO0O_a, + b => wire_ni00lO0O_b, + cin => wire_gnd, + o => wire_ni00lO0O_o + ); + wire_ni00lOil_a <= ( ni00ll1i & ni00liOO & ni00liOl & "1"); + wire_ni00lOil_b <= ( "1" & "1" & "0" & "1"); + ni00lOil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni00lOil_a, + b => wire_ni00lOil_b, + cin => wire_gnd, + o => wire_ni00lOil_o + ); + wire_ni01O01i_a <= ( ni01lOiO & ni01lOil & ni01lOii & "1"); + wire_ni01O01i_b <= ( "1" & "1" & "0" & "1"); + ni01O01i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni01O01i_a, + b => wire_ni01O01i_b, + cin => wire_gnd, + o => wire_ni01O01i_o + ); + wire_ni01O1Ol_a <= ( ni01lOiO & ni01lOil & ni01lOii); + wire_ni01O1Ol_b <= ( "0" & "0" & "1"); + ni01O1Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni01O1Ol_a, + b => wire_ni01O1Ol_b, + cin => wire_gnd, + o => wire_ni01O1Ol_o + ); + wire_ni100OO_a <= ( ni10Oii & niOO0iOlO & niOO0iOOl & niOO0l11i & "1"); + wire_ni100OO_b <= ( wire_ni01lOi_w_lg_ni10liO2719w & wire_w_lg_niOO0iOll2717w & wire_w_lg_niOO0iOOi2715w & wire_w_lg_niOO0iOOO2713w & "1"); + ni100OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_ni100OO_a, + b => wire_ni100OO_b, + cin => wire_gnd, + o => wire_ni100OO_o + ); + wire_ni1010O_a <= ( ni11l0l & niOO0ilOO & niOO0ilOl & niOO0ilOi & "1"); + wire_ni1010O_b <= ( wire_ni1lOlO_w_lg_ni11liO2764w & wire_w_lg_niOO0iO1O2735w & wire_w_lg_niOO0illO2761w & wire_w_lg_niOO0illl2759w & "1"); + ni1010O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_ni1010O_a, + b => wire_ni1010O_b, + cin => wire_gnd, + o => wire_ni1010O_o + ); + wire_ni101liO_a <= ( ni101i0i & ni101i1O & ni101i1l); + wire_ni101liO_b <= ( "0" & "0" & "1"); + ni101liO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni101liO_a, + b => wire_ni101liO_b, + cin => wire_gnd, + o => wire_ni101liO_o + ); + wire_ni101lll_a <= ( ni101i0i & ni101i1O & ni101i1l & "1"); + wire_ni101lll_b <= ( "1" & "1" & "0" & "1"); + ni101lll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni101lll_a, + b => wire_ni101lll_b, + cin => wire_gnd, + o => wire_ni101lll_o + ); + wire_ni11010i_a <= ( ni111llO & ni111lll & ni111lli & "1"); + wire_ni11010i_b <= ( "1" & "1" & "0" & "1"); + ni11010i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni11010i_a, + b => wire_ni11010i_b, + cin => wire_gnd, + o => wire_ni11010i_o + ); + wire_ni11011l_a <= ( ni111llO & ni111lll & ni111lli); + wire_ni11011l_b <= ( "0" & "0" & "1"); + ni11011l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni11011l_a, + b => wire_ni11011l_b, + cin => wire_gnd, + o => wire_ni11011l_o + ); + wire_ni1i1i1i_a <= ( ni1i11ll & ni1i11li & ni1i11iO); + wire_ni1i1i1i_b <= ( "0" & "0" & "1"); + ni1i1i1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni1i1i1i_a, + b => wire_ni1i1i1i_b, + cin => wire_gnd, + o => wire_ni1i1i1i_o + ); + wire_ni1i1i1O_a <= ( ni1i11ll & ni1i11li & ni1i11iO & "1"); + wire_ni1i1i1O_b <= ( "1" & "1" & "0" & "1"); + ni1i1i1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni1i1i1O_a, + b => wire_ni1i1i1O_b, + cin => wire_gnd, + o => wire_ni1i1i1O_o + ); + wire_ni1l11il_a <= ( ni1iOO1O & ni1iOO1l & ni1iOO1i); + wire_ni1l11il_b <= ( "0" & "0" & "1"); + ni1l11il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni1l11il_a, + b => wire_ni1l11il_b, + cin => wire_gnd, + o => wire_ni1l11il_o + ); + wire_ni1l11li_a <= ( ni1iOO1O & ni1iOO1l & ni1iOO1i & "1"); + wire_ni1l11li_b <= ( "1" & "1" & "0" & "1"); + ni1l11li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni1l11li_a, + b => wire_ni1l11li_b, + cin => wire_gnd, + o => wire_ni1l11li_o + ); + wire_ni1lOlOO_a <= ( ni1lOili & ni1lOiiO & ni1lOiil); + wire_ni1lOlOO_b <= ( "0" & "0" & "1"); + ni1lOlOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni1lOlOO_a, + b => wire_ni1lOlOO_b, + cin => wire_gnd, + o => wire_ni1lOlOO_o + ); + wire_ni1lOO1l_a <= ( ni1lOili & ni1lOiiO & ni1lOiil & "1"); + wire_ni1lOO1l_b <= ( "1" & "1" & "0" & "1"); + ni1lOO1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni1lOO1l_a, + b => wire_ni1lOO1l_b, + cin => wire_gnd, + o => wire_ni1lOO1l_o + ); + wire_ni1OOiii_a <= ( ni1OO01l & ni1OO01i & ni1OO1OO); + wire_ni1OOiii_b <= ( "0" & "0" & "1"); + ni1OOiii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_ni1OOiii_a, + b => wire_ni1OOiii_b, + cin => wire_gnd, + o => wire_ni1OOiii_o + ); + wire_ni1OOiiO_a <= ( ni1OO01l & ni1OO01i & ni1OO1OO & "1"); + wire_ni1OOiiO_b <= ( "1" & "1" & "0" & "1"); + ni1OOiiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_ni1OOiiO_a, + b => wire_ni1OOiiO_b, + cin => wire_gnd, + o => wire_ni1OOiiO_o + ); + wire_nii1l00l_a <= ( ni0i0i0l & ni0i0i0i & ni0i0i1O & "1"); + wire_nii1l00l_b <= ( "1" & "1" & "0" & "1"); + nii1l00l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nii1l00l_a, + b => wire_nii1l00l_b, + cin => wire_gnd, + o => wire_nii1l00l_o + ); + wire_niii0iiO_a <= ( niii0i1i & niii00OO & niii1OlO); + wire_niii0iiO_b <= ( "0" & "0" & "1"); + niii0iiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_niii0iiO_a, + b => wire_niii0iiO_b, + cin => wire_gnd, + o => wire_niii0iiO_o + ); + wire_nil100li_a <= ( wire_nilOO01i_dataout & "0" & "0" & "0" & wire_nil10lil_dataout & wire_nil10lii_dataout & wire_nil10l0O_dataout & wire_nil10l0l_dataout & wire_nil10l0i_dataout & wire_nil10l1O_dataout & wire_nil10l1l_dataout & wire_nil10l1i_dataout & wire_nil10iOO_dataout & "0" & "0"); + wire_nil100li_b <= ( wire_nil100ll_o(8 DOWNTO 0) & nil10lOl & nil10lOi & nil10llO & nil10lll & nil10lli & nil11iiO); + nil100li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 15, + width_b => 15, + width_o => 15 + ) + PORT MAP ( + a => wire_nil100li_a, + b => wire_nil100li_b, + cin => wire_gnd, + o => wire_nil100li_o + ); + wire_nil100ll_a <= ( "0" & nil10Oii & nil10O0O & nil10O0l & nil10O0i & nil10O1O & nil10O1l & nil10O1i & nil10lOO); + wire_nil100ll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nil100ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nil100ll_a, + b => wire_nil100ll_b, + cin => wire_gnd, + o => wire_nil100ll_o + ); + wire_nil100lO_a <= ( wire_nil10i0O_dataout & "0" & "0" & "0" & "0" & wire_nil10i0l_dataout & wire_nil10i0i_dataout & wire_nil10i1O_dataout & wire_nil10i1l_dataout & wire_nil10i1i_dataout & wire_nil100OO_dataout & wire_nil100Ol_dataout & wire_nil100Oi_dataout & "0" & "0"); + wire_nil100lO_b <= ( "0" & "0" & nil1i10l & nil1i10i & nil1i11O & nil1i11l & nil1i11i & nil10OOO & nil10OOl & nil10OOi & nil10OlO & nil10Oll & nil10Oli & nil10OiO & nil10Oil); + nil100lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 15, + width_b => 15, + width_o => 15 + ) + PORT MAP ( + a => wire_nil100lO_a, + b => wire_nil100lO_b, + cin => wire_gnd, + o => wire_nil100lO_o + ); + wire_nil10liO_a <= ( "0" & wire_nilliOlO_dataout & wire_nilliOll_dataout & wire_nilliOli_dataout & wire_nilliOiO_dataout & wire_nilliOil_dataout & wire_nilliOii_dataout & wire_nilliO0O_dataout & wire_nilliO0l_dataout); + wire_nil10liO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1"); + nil10liO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nil10liO_a, + b => wire_nil10liO_b, + cin => wire_gnd, + o => wire_nil10liO_o + ); + wire_niO0li0O_a <= ( niO0l0lO & niO0l0ll & niO00O0O); + wire_niO0li0O_b <= ( "0" & "0" & "1"); + niO0li0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_niO0li0O_a, + b => wire_niO0li0O_b, + cin => wire_gnd, + o => wire_niO0li0O_o + ); + wire_niOi11li_a <= ( niOi111i & niO0OOOO & niO0lOOl); + wire_niOi11li_b <= ( "0" & "0" & "1"); + niOi11li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_niOi11li_a, + b => wire_niOi11li_b, + cin => wire_gnd, + o => wire_niOi11li_o + ); + wire_niOlii1l_a <= ( niOl10Oi & niOl10lO & niOl10ll); + wire_niOlii1l_b <= ( "0" & "0" & "1"); + niOlii1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_niOlii1l_a, + b => wire_niOlii1l_b, + cin => wire_gnd, + o => wire_niOlii1l_o + ); + wire_niOlOi0l_a <= ( niOliOli & niOliOiO & niOliOil); + wire_niOlOi0l_b <= ( "0" & "0" & "1"); + niOlOi0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_niOlOi0l_a, + b => wire_niOlOi0l_b, + cin => wire_gnd, + o => wire_niOlOi0l_o + ); + wire_nl00iOil_a <= ( nl00iO1i & nl000lOO); + wire_nl00iOil_b <= ( "0" & "1"); + nl00iOil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl00iOil_a, + b => wire_nl00iOil_b, + cin => wire_gnd, + o => wire_nl00iOil_o + ); + wire_nl01i10li_a <= ( wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout); + wire_nl01i10li_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl01i10li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl01i10li_a, + b => wire_nl01i10li_b, + cin => wire_gnd, + o => wire_nl01i10li_o + ); + wire_nl01i11Oi_a <= ( nl010OlOO & nl010OlOl & nl010OlOi & nl010OllO & nl010Olll & nl010Olli & nl010OliO & nl010Olil & "1"); + wire_nl01i11Oi_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl01i11Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl01i11Oi_a, + b => wire_nl01i11Oi_b, + cin => wire_gnd, + o => wire_nl01i11Oi_o + ); + wire_nl01illi_a <= ( nl01il1l & nl01illl); + wire_nl01illi_b <= ( "0" & "1"); + nl01illi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl01illi_a, + b => wire_nl01illi_b, + cin => wire_gnd, + o => wire_nl01illi_o + ); + wire_nl01iO0O_a <= ( nl01ilOi & nl01illO); + wire_nl01iO0O_b <= ( "0" & "1"); + nl01iO0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl01iO0O_a, + b => wire_nl01iO0O_b, + cin => wire_gnd, + o => wire_nl01iO0O_o + ); + wire_nl01l1lii_a <= ( wire_nl01l1lil_o(11 DOWNTO 0) & "1"); + wire_nl01l1lii_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + wire_nl01l1lii_w_o_range53564w(0) <= wire_nl01l1lii_o(11); + nl01l1lii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl01l1lii_a, + b => wire_nl01l1lii_b, + cin => wire_gnd, + o => wire_nl01l1lii_o + ); + wire_nl01l1lil_a <= ( "0" & wire_nl01l01iO_dataout & wire_nl01l01il_dataout & wire_nl01l01ii_dataout & wire_nl01l010O_dataout & wire_nl01l010l_dataout & wire_nl01l010i_dataout & wire_nl01l011O_dataout & wire_nl01l011l_dataout & wire_nl01l011i_dataout & wire_nl01l1OOO_dataout & wire_nl01l1OOl_dataout); + wire_nl01l1lil_b <= ( "0" & nl01l0ili & nl01l0iiO & nl01l0iil & nl01l0iii & nl01l0i0O & nl01l0i0l & nl01l0i0i & nl01l0i1O & nl01l0i1l & nl01l0i1i & nl01l00OO); + nl01l1lil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl01l1lil_a, + b => wire_nl01l1lil_b, + cin => wire_gnd, + o => wire_nl01l1lil_o + ); + wire_nl01lliOO_a <= ( nl01lllOl & nl01lllOi & nl01llllO & nl01lllll & nl01lllli & nl01llliO & nl01lllil & nl01lllii & nl01lll0O & nl01lll0l & nl01lll0i & nl01lll1O & nl01lll1l & "1"); + wire_nl01lliOO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nilOilOO_w_lg_dataout53156w & wire_nilOilOl_w_lg_dataout53154w & "1"); + nl01lliOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 14, + width_b => 14, + width_o => 14 + ) + PORT MAP ( + a => wire_nl01lliOO_a, + b => wire_nl01lliOO_b, + cin => wire_gnd, + o => wire_nl01lliOO_o + ); + wire_nl01lO0ii_a <= ( niOi0i11O & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout & "0" & "0" & "1"); + wire_nl01lO0ii_b <= ( wire_nilOiiiO_w_lg_dataout53114w & wire_nilOiiil_w_lg_dataout53112w & wire_nilOiiii_w_lg_dataout53110w & wire_nilOii0O_w_lg_dataout53108w & wire_nilOii0l_w_lg_dataout53106w & wire_nilOii0i_w_lg_dataout45173w & wire_nilOii1O_w_lg_dataout45174w & wire_nilOii1l_w_lg_dataout53102w & wire_nilOii1i_w_lg_dataout53100w & wire_nilOi0OO_w_lg_dataout45178w & wire_nilOi0Ol_w_lg_dataout45180w & wire_nilOi0Oi_w_lg_dataout53096w & wire_nilOi0lO_w_lg_dataout53094w & "1"); + nl01lO0ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 14, + width_b => 14, + width_o => 14 + ) + PORT MAP ( + a => wire_nl01lO0ii_a, + b => wire_nl01lO0ii_b, + cin => wire_gnd, + o => wire_nl01lO0ii_o + ); + wire_nl0iiOiO_a <= ( nl0iiO1l & nl0i0O1i); + wire_nl0iiOiO_b <= ( "0" & "1"); + nl0iiOiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl0iiOiO_a, + b => wire_nl0iiOiO_b, + cin => wire_gnd, + o => wire_nl0iiOiO_o + ); + wire_nl0iliil_a <= ( nl0iOiiO & nl0iOiil & nl0iOiii & nl0iOi0O & nl0iOi0l & nl0iOi0i & nl0iOi1O & nl0iOi1l & nl0iOi1i & nl0iO0OO & nl0iO0Ol & nl0iO0Oi & "1"); + wire_nl0iliil_b <= ( wire_niOOO0O_w_lg_nl0ill0l6972w & wire_niOOO0O_w_lg_nl0ill0i6970w & wire_niOOO0O_w_lg_nl0ill1O6968w & wire_niOOO0O_w_lg_nl0ill1l6966w & wire_niOOO0O_w_lg_nl0ill1i6964w & wire_niOOO0O_w_lg_nl0iliOO6962w & wire_niOOO0O_w_lg_nl0iliOl6960w & wire_niOOO0O_w_lg_nl0iliOi6958w & wire_niOOO0O_w_lg_nl0ililO6956w & wire_niOOO0O_w_lg_nl0ilill6954w & wire_niOOO0O_w_lg_nl0ilili6952w & wire_niOOO0O_w_lg_nl0il1li6950w & "1"); + nl0iliil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl0iliil_a, + b => wire_nl0iliil_b, + cin => wire_gnd, + o => wire_nl0iliil_o + ); + wire_nl0iliiO_a <= ( nl0iOl1l & nl0iOl1i & nl0iOiOO & nl0iOiOl & nl0iOiOi & nl0iOilO & nl0iOill & nl0iOili & "1"); + wire_nl0iliiO_b <= ( wire_niOOO0O_w_lg_nl0illOi6930w & wire_niOOO0O_w_lg_nl0illlO6928w & wire_niOOO0O_w_lg_nl0illll6926w & wire_niOOO0O_w_lg_nl0illli6924w & wire_niOOO0O_w_lg_nl0illiO6922w & wire_niOOO0O_w_lg_nl0illil6920w & wire_niOOO0O_w_lg_nl0illii6918w & wire_niOOO0O_w_lg_nl0ill0O6916w & "1"); + nl0iliiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl0iliiO_a, + b => wire_nl0iliiO_b, + cin => wire_gnd, + o => wire_nl0iliiO_o + ); + wire_nl0ilil0l_a <= ( niOi0O01i & wire_nl1lOOiOl_dataout & wire_nl1lOOiOi_dataout & wire_nl1lOOilO_dataout & wire_nl1lOOill_dataout & wire_nl1lOOili_dataout & wire_nl1lOOiiO_dataout & wire_nl1lOOiil_dataout & wire_nl1lOOiii_dataout & wire_nl1lOOi0O_dataout & wire_nl1lOOi0l_dataout & "0" & "0" & "1"); + wire_nl0ilil0l_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nl0ililil_w_lg_dataout52203w & wire_nl0ililii_w_lg_dataout52201w & wire_nl0ilil0O_w_lg_dataout52199w & "1"); + nl0ilil0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 14, + width_b => 14, + width_o => 14 + ) + PORT MAP ( + a => wire_nl0ilil0l_a, + b => wire_nl0ilil0l_b, + cin => wire_gnd, + o => wire_nl0ilil0l_o + ); + wire_nl0iO01l_a <= ( nl0ill0l & nl0ill0i & nl0ill1O & nl0ill1l & nl0ill1i & nl0iliOO & nl0iliOl & nl0iliOi & nl0ililO & nl0ilill & nl0ilili & nl0il1li); + wire_nl0iO01l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl0iO01l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl0iO01l_a, + b => wire_nl0iO01l_b, + cin => wire_gnd, + o => wire_nl0iO01l_o + ); + wire_nl0iO0ll_a <= ( nl0illOi & nl0illlO & nl0illll & nl0illli & nl0illiO & nl0illil & nl0illii & nl0ill0O); + wire_nl0iO0ll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl0iO0ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl0iO0ll_a, + b => wire_nl0iO0ll_b, + cin => wire_gnd, + o => wire_nl0iO0ll_o + ); + wire_nl0l01l1i_a <= ( wire_nl1lOO10i_dataout & wire_nl1lOO11O_dataout); + wire_nl0l01l1i_b <= ( k_dev(1 DOWNTO 0)); + nl0l01l1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl0l01l1i_a, + b => wire_nl0l01l1i_b, + cin => wire_gnd, + o => wire_nl0l01l1i_o + ); + wire_nl0l0Oii_a <= ( nl0liOil & nl0liOii & nl0liO0O & nl0liO0l & nl0liO0i & nl0liO1O & nl0liO1l & nl0liO1i & nl0lilOO & nl0lilOl & nl0lilOi & nl0lillO & "1"); + wire_nl0l0Oii_b <= ( wire_niOOO0O_w_lg_nl0li10i6652w & wire_niOOO0O_w_lg_nl0li11O6650w & wire_niOOO0O_w_lg_nl0li11l6648w & wire_niOOO0O_w_lg_nl0li11i6646w & wire_niOOO0O_w_lg_nl0l0OOO6644w & wire_niOOO0O_w_lg_nl0l0OOl6642w & wire_niOOO0O_w_lg_nl0l0OOi6640w & wire_niOOO0O_w_lg_nl0l0OlO6638w & wire_niOOO0O_w_lg_nl0l0Oll6636w & wire_niOOO0O_w_lg_nl0l0Oli6634w & wire_niOOO0O_w_lg_nl0l0OiO6632w & wire_niOOO0O_w_lg_nl0l0ili6630w & "1"); + nl0l0Oii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl0l0Oii_a, + b => wire_nl0l0Oii_b, + cin => wire_gnd, + o => wire_nl0l0Oii_o + ); + wire_nl0l0Oil_a <= ( nl0ll11i & nl0liOOO & nl0liOOl & nl0liOOi & nl0liOlO & nl0liOll & nl0liOli & nl0liOiO & "1"); + wire_nl0l0Oil_b <= ( wire_niOOO0O_w_lg_nl0li1lO6610w & wire_niOOO0O_w_lg_nl0li1ll6608w & wire_niOOO0O_w_lg_nl0li1li6606w & wire_niOOO0O_w_lg_nl0li1iO6604w & wire_niOOO0O_w_lg_nl0li1il6602w & wire_niOOO0O_w_lg_nl0li1ii6600w & wire_niOOO0O_w_lg_nl0li10O6598w & wire_niOOO0O_w_lg_nl0li10l6596w & "1"); + nl0l0Oil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl0l0Oil_a, + b => wire_nl0l0Oil_b, + cin => wire_gnd, + o => wire_nl0l0Oil_o + ); + wire_nl0lil1i_a <= ( nl0li10i & nl0li11O & nl0li11l & nl0li11i & nl0l0OOO & nl0l0OOl & nl0l0OOi & nl0l0OlO & nl0l0Oll & nl0l0Oli & nl0l0OiO & nl0l0ili); + wire_nl0lil1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl0lil1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl0lil1i_a, + b => wire_nl0lil1i_b, + cin => wire_gnd, + o => wire_nl0lil1i_o + ); + wire_nl0lilli_a <= ( nl0li1lO & nl0li1ll & nl0li1li & nl0li1iO & nl0li1il & nl0li1ii & nl0li10O & nl0li10l); + wire_nl0lilli_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl0lilli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl0lilli_a, + b => wire_nl0lilli_b, + cin => wire_gnd, + o => wire_nl0lilli_o + ); + wire_nl101i0li_a <= ( "0" & nl11OiOOi & nl11OiOlO & nl11OiOll & nl11OiOli & nl11OiOiO & nl11OiOil & nl11OiOii & nl11OiO0O & nl11OiO0l); + wire_nl101i0li_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl101i0li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nl101i0li_a, + b => wire_nl101i0li_b, + cin => wire_gnd, + o => wire_nl101i0li_o + ); + wire_nl10iiOll_a <= ( "0" & niOi10OOO & wire_nl10iiO1l_dataout & wire_nl10iiO1i_dataout & wire_nl10iilOO_dataout & wire_nl10iilOl_dataout & wire_nl10iilOi_dataout & wire_nl10iillO_dataout & wire_nl10iilll_dataout); + wire_nl10iiOll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl10iiOll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl10iiOll_a, + b => wire_nl10iiOll_b, + cin => wire_gnd, + o => wire_nl10iiOll_o + ); + wire_nl10iiOlO_a <= ( nlOil1ll & nlOil1li & nlOil1iO & nlOil1il & nlOil1ii & nlOil10O & nlOil10l & nlOil10i); + wire_nl10iiOlO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nl1000i_w_lg_w_lg_w_lg_nlOil11O59625w59627w59628w); + nl10iiOlO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl10iiOlO_a, + b => wire_nl10iiOlO_b, + cin => wire_gnd, + o => wire_nl10iiOlO_o + ); + wire_nl10iiOOi_a <= ( wire_nl10il1il_dataout & wire_nl10il1ii_dataout & wire_nl10il10O_dataout & wire_nl10il10l_dataout & wire_nl10il10i_dataout & wire_nl10il11O_dataout & wire_nl10il11l_dataout & wire_nl10il11i_dataout); + wire_nl10iiOOi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nl10iiOOO_w_lg_w_lg_w_lg_dataout59596w59598w59599w); + nl10iiOOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl10iiOOi_a, + b => wire_nl10iiOOi_b, + cin => wire_gnd, + o => wire_nl10iiOOi_o + ); + wire_nl10il1iO_a <= ( nlOil1ll & nlOil1li & nlOil1iO & nlOil1il & nlOil1ii & nlOil10O & nlOil10l & nlOil10i & nlOil11O & nlOil11l); + wire_nl10il1iO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl10il1iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nl10il1iO_a, + b => wire_nl10il1iO_b, + cin => wire_gnd, + o => wire_nl10il1iO_o + ); + wire_nl10iOi0l_a <= ( nl10ilOOi & nl10ilOlO & nl10ilOll & nl10ilOli & nl10ilOiO & nl10ilOil & nl10ilOii & nl10ilO0O); + wire_nl10iOi0l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl10iOi0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl10iOi0l_a, + b => wire_nl10iOi0l_b, + cin => wire_gnd, + o => wire_nl10iOi0l_o + ); + wire_nl10lOO1l_a <= ( nl10O00iO & nl10O00il & nl10O00ii & nl10O000O & nl10O000l & nl10O000i & nl10O001O & nl10O001l & nl10O001i & nl10O01OO & nl10O01Ol & nl10O100l & "1"); + wire_nl10lOO1l_b <= ( wire_nlill0Oll_w_lg_nl1i11OiO58258w & wire_nlill0Oll_w_lg_nl1i11Oil58256w & wire_nlill0Oll_w_lg_nl1i11Oii58254w & wire_nlill0Oll_w_lg_nl1i11O0O58252w & wire_nlill0Oll_w_lg_nl1i11O0l58250w & wire_nlill0Oll_w_lg_nl1i11O0i58248w & wire_nlill0Oll_w_lg_nl1i11O1O58246w & wire_nlill0Oll_w_lg_nl1i11O1l58244w & wire_nlill0Oll_w_lg_nl1i11O1i58242w & wire_nlill0Oll_w_lg_nl1i11lOO58240w & wire_nlill0Oll_w_lg_nl1i11lOl58238w & wire_nlill0Oll_w_lg_nl1i1101O58236w & "1"); + nl10lOO1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl10lOO1l_a, + b => wire_nl10lOO1l_b, + cin => wire_gnd, + o => wire_nl10lOO1l_o + ); + wire_nl10lOOli_a <= ( nl10O0iOl & nl10O0iOi & nl10O0ilO & nl10O0ill & nl10O0ili & nl10O0iiO & nl10O0iil & nl10O0iii & nl10O0i0O & nl10O0i0l & nl10O0i0i & nl10O0i1O & "1"); + wire_nl10lOOli_b <= ( wire_nlill0Oll_w_lg_nl1i101Ol58186w & wire_nlill0Oll_w_lg_nl1i101Oi58184w & wire_nlill0Oll_w_lg_nl1i101lO58182w & wire_nlill0Oll_w_lg_nl1i101ll58180w & wire_nlill0Oll_w_lg_nl1i101li58178w & wire_nlill0Oll_w_lg_nl1i101iO58176w & wire_nlill0Oll_w_lg_nl1i101il58174w & wire_nlill0Oll_w_lg_nl1i101ii58172w & wire_nlill0Oll_w_lg_nl1i1010O58170w & wire_nlill0Oll_w_lg_nl1i1010l58168w & wire_nlill0Oll_w_lg_nl1i1010i58166w & wire_nlill0Oll_w_lg_nl1i1011O58164w & "1"); + nl10lOOli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl10lOOli_a, + b => wire_nl10lOOli_b, + cin => wire_gnd, + o => wire_nl10lOOli_o + ); + wire_nl10O011l_a <= ( nl10O11Ol & nl10O11Oi & nl10O11lO & nl10O11ll & nl10O11li); + wire_nl10O011l_b <= ( "0" & "0" & "0" & "0" & "1"); + nl10O011l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl10O011l_a, + b => wire_nl10O011l_b, + cin => wire_gnd, + o => wire_nl10O011l_o + ); + wire_nl10O01Oi_a <= ( nl10O100i & nl10O101O & nl10O101l & nl10O101i & nl10O11OO); + wire_nl10O01Oi_b <= ( "0" & "0" & "0" & "0" & "1"); + nl10O01Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl10O01Oi_a, + b => wire_nl10O01Oi_b, + cin => wire_gnd, + o => wire_nl10O01Oi_o + ); + wire_nl10O111l_a <= ( nl10O0OlO & nl10O0Oll & nl10O0Oli & nl10O0OiO & nl10O0Oil & nl10O0Oii & nl10O0O0O & nl10O0O0l & nl10O0O0i & nl10O0O1O & nl10O0O1l & nl10O0O1i & "1"); + wire_nl10O111l_b <= ( wire_nlill0Oll_w_lg_nl1i10ilO58114w & wire_nlill0Oll_w_lg_nl1i10ill58112w & wire_nlill0Oll_w_lg_nl1i10ili58110w & wire_nlill0Oll_w_lg_nl1i10iiO58108w & wire_nlill0Oll_w_lg_nl1i10iil58106w & wire_nlill0Oll_w_lg_nl1i10iii58104w & wire_nlill0Oll_w_lg_nl1i10i0O58102w & wire_nlill0Oll_w_lg_nl1i10i0l58100w & wire_nlill0Oll_w_lg_nl1i10i0i58098w & wire_nlill0Oll_w_lg_nl1i10i1O58096w & wire_nlill0Oll_w_lg_nl1i10i1l58094w & wire_nlill0Oll_w_lg_nl1i10i1i58092w & "1"); + nl10O111l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl10O111l_a, + b => wire_nl10O111l_b, + cin => wire_gnd, + o => wire_nl10O111l_o + ); + wire_nl10O1O0O_a <= ( nl10O11iO & nl10O11il & nl10O11ii & nl10O110O & nl10lll0i); + wire_nl10O1O0O_b <= ( "0" & "0" & "0" & "0" & "1"); + nl10O1O0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nl10O1O0O_a, + b => wire_nl10O1O0O_b, + cin => wire_gnd, + o => wire_nl10O1O0O_o + ); + wire_nl110iOil_a <= ( nl110OilO & nl110Oill & nl110Oili & nl110OiiO & nl110Oiil & nl110Oiii & nl110Oi0O & nl110Oi0l & nl110Oi0i & nl110Oi1O & nl110Oi1l & nl1101l0O & "1"); + wire_nl110iOil_b <= ( "1" & "1" & "1" & wire_nlill0Oll_w_lg_nl11OiO0i60523w & wire_nlill0Oll_w_lg_nl11OiO1O60521w & wire_nlill0Oll_w_lg_nl11OiO1l60519w & wire_nlill0Oll_w_lg_nl11OiO1i60517w & wire_nlill0Oll_w_lg_nl11OilOO60515w & wire_nlill0Oll_w_lg_nl11OilOl60513w & wire_nlill0Oll_w_lg_nl11OilOi60511w & wire_nlill0Oll_w_lg_nl11OillO60509w & wire_nlill0Oll_w_lg_nl11Oilll60507w & "1"); + nl110iOil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl110iOil_a, + b => wire_nl110iOil_b, + cin => wire_gnd, + o => wire_nl110iOil_o + ); + wire_nl110iOli_a <= ( nl110OilO & nl110Oill & nl110Oili & nl110OiiO & nl110Oiil & nl110Oiii & nl110Oi0O & nl110Oi0l & nl110Oi0i & nl110Oi1O & nl110Oi1l & nl1101l0O); + wire_nl110iOli_b <= ( "0" & "0" & "0" & nl11OiO0i & nl11OiO1O & nl11OiO1l & nl11OiO1i & nl11OilOO & nl11OilOl & nl11OilOi & nl11OillO & nl11Oilll); + nl110iOli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl110iOli_a, + b => wire_nl110iOli_b, + cin => wire_gnd, + o => wire_nl110iOli_o + ); + wire_nl110l1Oi_a <= ( nl110Ol0l & nl110Ol0i & nl110Ol1O & nl110Ol1l & nl110Ol1i & nl110OiOO & nl110OiOl & nl110OiOi & "1"); + wire_nl110l1Oi_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl110l1Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl110l1Oi_a, + b => wire_nl110l1Oi_b, + cin => wire_gnd, + o => wire_nl110l1Oi_o + ); + wire_nl110l1Ol_a <= ( nl110Ol0l & nl110Ol0i & nl110Ol1O & nl110Ol1l & nl110Ol1i & nl110OiOO & nl110OiOl & nl110OiOi); + wire_nl110l1Ol_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl110l1Ol : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl110l1Ol_a, + b => wire_nl110l1Ol_b, + cin => wire_gnd, + o => wire_nl110l1Ol_o + ); + wire_nl110liiO_a <= ( nl110OO1l & nl110OO1i & nl110OlOO & nl110OlOl & nl110OlOi & nl110OllO & nl110Olll & nl110Olli & nl110OliO & nl110Olil & nl110Olii & nl110Ol0O & "1"); + wire_nl110liiO_b <= ( "1" & "1" & "1" & wire_nlill0Oll_w_lg_nl11OiO0i60523w & wire_nlill0Oll_w_lg_nl11OiO1O60521w & wire_nlill0Oll_w_lg_nl11OiO1l60519w & wire_nlill0Oll_w_lg_nl11OiO1i60517w & wire_nlill0Oll_w_lg_nl11OilOO60515w & wire_nlill0Oll_w_lg_nl11OilOl60513w & wire_nlill0Oll_w_lg_nl11OilOi60511w & wire_nlill0Oll_w_lg_nl11OillO60509w & wire_nlill0Oll_w_lg_nl11Oilll60507w & "1"); + nl110liiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl110liiO_a, + b => wire_nl110liiO_b, + cin => wire_gnd, + o => wire_nl110liiO_o + ); + wire_nl110lill_a <= ( nl110OO1l & nl110OO1i & nl110OlOO & nl110OlOl & nl110OlOi & nl110OllO & nl110Olll & nl110Olli & nl110OliO & nl110Olil & nl110Olii & nl110Ol0O); + wire_nl110lill_b <= ( "0" & "0" & "0" & nl11OiO0i & nl11OiO1O & nl11OiO1l & nl11OiO1i & nl11OilOO & nl11OilOl & nl11OilOi & nl11OillO & nl11Oilll); + nl110lill : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl110lill_a, + b => wire_nl110lill_b, + cin => wire_gnd, + o => wire_nl110lill_o + ); + wire_nl110llOl_a <= ( nl110OOli & nl110OOiO & nl110OOil & nl110OOii & nl110OO0O & nl110OO0l & nl110OO0i & nl110OO1O & "1"); + wire_nl110llOl_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl110llOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl110llOl_a, + b => wire_nl110llOl_b, + cin => wire_gnd, + o => wire_nl110llOl_o + ); + wire_nl110llOO_a <= ( nl110OOli & nl110OOiO & nl110OOil & nl110OOii & nl110OO0O & nl110OO0l & nl110OO0i & nl110OO1O); + wire_nl110llOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl110llOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl110llOO_a, + b => wire_nl110llOO_b, + cin => wire_gnd, + o => wire_nl110llOO_o + ); + wire_nl110O0OO_a <= ( nl11i111O & nl11i111l & nl11i111i & nl110OOOO & nl110OOOl & nl110OOOi & nl110OOlO & nl110OOll & "1"); + wire_nl110O0OO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl110O0OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl110O0OO_a, + b => wire_nl110O0OO_b, + cin => wire_gnd, + o => wire_nl110O0OO_o + ); + wire_nl110O1li_a <= ( nl11i11OO & nl11i11Ol & nl11i11Oi & nl11i11lO & nl11i11ll & nl11i11li & nl11i11iO & nl11i11il & nl11i11ii & nl11i110O & nl11i110l & nl11i110i & "1"); + wire_nl110O1li_b <= ( "1" & "1" & "1" & wire_nlill0Oll_w_lg_nl11OiO0i60523w & wire_nlill0Oll_w_lg_nl11OiO1O60521w & wire_nlill0Oll_w_lg_nl11OiO1l60519w & wire_nlill0Oll_w_lg_nl11OiO1i60517w & wire_nlill0Oll_w_lg_nl11OilOO60515w & wire_nlill0Oll_w_lg_nl11OilOl60513w & wire_nlill0Oll_w_lg_nl11OilOi60511w & wire_nlill0Oll_w_lg_nl11OillO60509w & wire_nlill0Oll_w_lg_nl11Oilll60507w & "1"); + nl110O1li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl110O1li_a, + b => wire_nl110O1li_b, + cin => wire_gnd, + o => wire_nl110O1li_o + ); + wire_nl110O1lO_a <= ( nl11i11OO & nl11i11Ol & nl11i11Oi & nl11i11lO & nl11i11ll & nl11i11li & nl11i11iO & nl11i11il & nl11i11ii & nl11i110O & nl11i110l & nl11i110i); + wire_nl110O1lO_b <= ( "0" & "0" & "0" & nl11OiO0i & nl11OiO1O & nl11OiO1l & nl11OiO1i & nl11OilOO & nl11OilOl & nl11OilOi & nl11OillO & nl11Oilll); + nl110O1lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl110O1lO_a, + b => wire_nl110O1lO_b, + cin => wire_gnd, + o => wire_nl110O1lO_o + ); + wire_nl110Oi1i_a <= ( nl11i111O & nl11i111l & nl11i111i & nl110OOOO & nl110OOOl & nl110OOOi & nl110OOlO & nl110OOll); + wire_nl110Oi1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl110Oi1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl110Oi1i_a, + b => wire_nl110Oi1i_b, + cin => wire_gnd, + o => wire_nl110Oi1i_o + ); + wire_nl111l1li_a <= ( nl110111l & nl110111i & nl111OOOO & nl111OOOl & nl111OOOi & nl111OOlO & nl111OOll & nl111OOli & nl111OOiO & nl111OOil & nl111OOii & nl111OO0O & "1"); + wire_nl111l1li_b <= ( wire_nl110illi_w_lg_dataout61365w & wire_nl110iliO_w_lg_dataout61363w & wire_nl110ilil_w_lg_dataout61361w & wire_nl110ilii_w_lg_dataout61359w & wire_nl110il0O_w_lg_dataout61357w & wire_nl110il0l_w_lg_dataout61355w & wire_nl110il0i_w_lg_dataout61353w & wire_nl110il1O_w_lg_dataout61351w & wire_nl110il1l_w_lg_dataout61349w & wire_nl110il1i_w_lg_dataout61347w & wire_nl110iiOO_w_lg_dataout61345w & wire_nl110iiOl_w_lg_dataout61343w & "1"); + nl111l1li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl111l1li_a, + b => wire_nl111l1li_b, + cin => wire_gnd, + o => wire_nl111l1li_o + ); + wire_nl111l1ll_a <= ( nl1101l0l & nl1101l0i & nl1101l1O & nl1101l1l & nl1101l1i & nl1101iOO & nl1101iOl & nl1101iOi & nl1101ilO & nl1101ill & nl1101ili & nl1101iiO & "1"); + wire_nl111l1ll_b <= ( wire_nl110lOlO_w_lg_dataout61323w & wire_nl110lOll_w_lg_dataout61321w & wire_nl110lOli_w_lg_dataout61319w & wire_nl110lOiO_w_lg_dataout61317w & wire_nl110lOil_w_lg_dataout61315w & wire_nl110lOii_w_lg_dataout61313w & wire_nl110lO0O_w_lg_dataout61311w & wire_nl110lO0l_w_lg_dataout61309w & wire_nl110lO0i_w_lg_dataout61307w & wire_nl110lO1O_w_lg_dataout61305w & wire_nl110lO1l_w_lg_dataout61303w & wire_nl110lO1i_w_lg_dataout61301w & "1"); + nl111l1ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl111l1ll_a, + b => wire_nl111l1ll_b, + cin => wire_gnd, + o => wire_nl111l1ll_o + ); + wire_nl111O0iO_a <= ( nl110110l & nl110110i & nl110111O & "1"); + wire_nl111O0iO_b <= ( wire_nl110iOOl_w_lg_dataout61202w & wire_nl110iOOi_w_lg_dataout61200w & wire_nl110iOlO_w_lg_dataout61198w & "1"); + nl111O0iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nl111O0iO_a, + b => wire_nl111O0iO_b, + cin => wire_gnd, + o => wire_nl111O0iO_o + ); + wire_nl111O0lO_a <= ( nl11011li & nl11011iO & nl11011il & nl11011ii & nl110110O & nl110110l & nl110110i & nl110111O & "1"); + wire_nl111O0lO_b <= ( wire_nl110l10i_w_lg_dataout61212w & wire_nl110l11O_w_lg_dataout61210w & wire_nl110l11l_w_lg_dataout61208w & wire_nl110l11i_w_lg_dataout61206w & wire_nl110iOOO_w_lg_dataout61204w & wire_nl110iOOl_w_lg_dataout61202w & wire_nl110iOOi_w_lg_dataout61200w & wire_nl110iOlO_w_lg_dataout61198w & "1"); + nl111O0lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl111O0lO_a, + b => wire_nl111O0lO_b, + cin => wire_gnd, + o => wire_nl111O0lO_o + ); + wire_nl111Oi0i_a <= ( nl11010ii & nl110100O & nl110100l & nl110100i & nl110101O & nl110101l & nl110101i & nl11011OO & nl11011Ol & nl11011Oi & nl11011lO & nl11011ll & "1"); + wire_nl111Oi0i_b <= ( wire_nl110l0ll_w_lg_dataout61105w & wire_nl110l0li_w_lg_dataout61103w & wire_nl110l0iO_w_lg_dataout61101w & wire_nl110l0il_w_lg_dataout61099w & wire_nl110l0ii_w_lg_dataout61097w & wire_nl110l00O_w_lg_dataout61095w & wire_nl110l00l_w_lg_dataout61093w & wire_nl110l00i_w_lg_dataout61091w & wire_nl110l01O_w_lg_dataout61089w & wire_nl110l01l_w_lg_dataout61087w & wire_nl110l01i_w_lg_dataout61085w & wire_nl110l1OO_w_lg_dataout61083w & "1"); + nl111Oi0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl111Oi0i_a, + b => wire_nl111Oi0i_b, + cin => wire_gnd, + o => wire_nl111Oi0i_o + ); + wire_nl111Oi1i_a <= ( nl11011Oi & nl11011lO & nl11011ll & "1"); + wire_nl111Oi1i_b <= ( wire_nl110l01l_w_lg_dataout61087w & wire_nl110l01i_w_lg_dataout61085w & wire_nl110l1OO_w_lg_dataout61083w & "1"); + nl111Oi1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nl111Oi1i_a, + b => wire_nl111Oi1i_b, + cin => wire_gnd, + o => wire_nl111Oi1i_o + ); + wire_nl111Oiil_a <= ( nl11010li & nl11010iO & nl11010il & "1"); + wire_nl111Oiil_b <= ( wire_nl110liOO_w_lg_dataout60996w & wire_nl110liOl_w_lg_dataout60994w & wire_nl110liOi_w_lg_dataout60992w & "1"); + nl111Oiil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nl111Oiil_a, + b => wire_nl111Oiil_b, + cin => wire_gnd, + o => wire_nl111Oiil_o + ); + wire_nl111Oill_a <= ( nl11010OO & nl11010Ol & nl11010Oi & nl11010lO & nl11010ll & nl11010li & nl11010iO & nl11010il & "1"); + wire_nl111Oill_b <= ( wire_nl110ll0l_w_lg_dataout61006w & wire_nl110ll0i_w_lg_dataout61004w & wire_nl110ll1O_w_lg_dataout61002w & wire_nl110ll1l_w_lg_dataout61000w & wire_nl110ll1i_w_lg_dataout60998w & wire_nl110liOO_w_lg_dataout60996w & wire_nl110liOl_w_lg_dataout60994w & wire_nl110liOi_w_lg_dataout60992w & "1"); + nl111Oill : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl111Oill_a, + b => wire_nl111Oill_b, + cin => wire_gnd, + o => wire_nl111Oill_o + ); + wire_nl111OllO_a <= ( nl1101i1O & nl1101i1l & nl1101i1i & "1"); + wire_nl111OllO_b <= ( wire_nl110O01i_w_lg_dataout60897w & wire_nl110O1OO_w_lg_dataout60895w & wire_nl110O1Ol_w_lg_dataout60893w & "1"); + nl111OllO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nl111OllO_a, + b => wire_nl111OllO_b, + cin => wire_gnd, + o => wire_nl111OllO_o + ); + wire_nl111OlOO_a <= ( nl1101iil & nl1101iii & nl1101i0O & nl1101i0l & nl1101i0i & nl1101i1O & nl1101i1l & nl1101i1i & "1"); + wire_nl111OlOO_b <= ( wire_nl110O00O_w_lg_dataout60907w & wire_nl110O00l_w_lg_dataout60905w & wire_nl110O00i_w_lg_dataout60903w & wire_nl110O01O_w_lg_dataout60901w & wire_nl110O01l_w_lg_dataout60899w & wire_nl110O01i_w_lg_dataout60897w & wire_nl110O1OO_w_lg_dataout60895w & wire_nl110O1Ol_w_lg_dataout60893w & "1"); + nl111OlOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl111OlOO_a, + b => wire_nl111OlOO_b, + cin => wire_gnd, + o => wire_nl111OlOO_o + ); + wire_nl11Oil1i_a <= ( nl11Oii0l & nl11Oii0i); + wire_nl11Oil1i_b <= ( "0" & "1"); + nl11Oil1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl11Oil1i_a, + b => wire_nl11Oil1i_b, + cin => wire_gnd, + o => wire_nl11Oil1i_o + ); + wire_nl11Oil1O_a <= ( nl11Oii0l & nl11Oii0i & "1"); + wire_nl11Oil1O_b <= ( "1" & "0" & "1"); + nl11Oil1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_nl11Oil1O_a, + b => wire_nl11Oil1O_b, + cin => wire_gnd, + o => wire_nl11Oil1O_o + ); + wire_nl1i00lli_a <= ( wire_nl1i0li0l_dataout & wire_nl1i0li0i_dataout & wire_nl1i0li1O_dataout & wire_nl1i0li1l_dataout & wire_nl1i0li1i_dataout & wire_nl1i0l0OO_dataout & wire_nl1i0l0Ol_dataout & wire_nl1i0l0Oi_dataout & wire_nl1i0l0lO_dataout & wire_nl1i0l0ll_dataout & wire_nl1i0l0li_dataout & wire_nl1i0l0iO_dataout); + wire_nl1i00lli_b <= ( "0" & "0" & "0" & nl1iiOi0O & nl1iiOi0l & nl1iiOi0i & nl1iiOi1O & nl1iiOi1l & nl1iiOi1i & nl1iiO0OO & nl1iiO0Ol & nl1iiO0Oi); + nl1i00lli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i00lli_a, + b => wire_nl1i00lli_b, + cin => wire_gnd, + o => wire_nl1i00lli_o + ); + wire_nl1i00OlO_a <= ( wire_nl1i0lO1i_dataout & wire_nl1i0llOO_dataout & wire_nl1i0llOl_dataout & wire_nl1i0llOi_dataout & wire_nl1i0lllO_dataout & wire_nl1i0llll_dataout & wire_nl1i0llli_dataout & wire_nl1i0lliO_dataout); + wire_nl1i00OlO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i00OlO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i00OlO_a, + b => wire_nl1i00OlO_b, + cin => wire_gnd, + o => wire_nl1i00OlO_o + ); + wire_nl1i0ii0l_a <= ( wire_nl1i0O1lO_dataout & wire_nl1i0O1ll_dataout & wire_nl1i0O1li_dataout & wire_nl1i0O1iO_dataout & wire_nl1i0O1il_dataout & wire_nl1i0O1ii_dataout & wire_nl1i0O10O_dataout & wire_nl1i0O10l_dataout & wire_nl1i0O10i_dataout & wire_nl1i0O11O_dataout & wire_nl1i0O11l_dataout & wire_nl1i0O11i_dataout); + wire_nl1i0ii0l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i0ii0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i0ii0l_a, + b => wire_nl1i0ii0l_b, + cin => wire_gnd, + o => wire_nl1i0ii0l_o + ); + wire_nl1i0ilil_a <= ( wire_nl1i0Oiil_dataout & wire_nl1i0Oiii_dataout & wire_nl1i0Oi0O_dataout & wire_nl1i0Oi0l_dataout & wire_nl1i0Oi0i_dataout & wire_nl1i0Oi1O_dataout & wire_nl1i0Oi1l_dataout & wire_nl1i0Oi1i_dataout); + wire_nl1i0ilil_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i0ilil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i0ilil_a, + b => wire_nl1i0ilil_b, + cin => wire_gnd, + o => wire_nl1i0ilil_o + ); + wire_nl1i0l0il_a <= ( wire_nl1ii11OO_dataout & wire_nl1ii11Ol_dataout & wire_nl1ii11Oi_dataout & wire_nl1ii11lO_dataout & wire_nl1ii11ll_dataout & wire_nl1ii11li_dataout & wire_nl1ii11iO_dataout & wire_nl1ii11il_dataout); + wire_nl1i0l0il_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i0l0il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i0l0il_a, + b => wire_nl1i0l0il_b, + cin => wire_gnd, + o => wire_nl1i0l0il_o + ); + wire_nl1i0l10i_a <= ( wire_nl1i0OO0i_dataout & wire_nl1i0OO1O_dataout & wire_nl1i0OO1l_dataout & wire_nl1i0OO1i_dataout & wire_nl1i0OlOO_dataout & wire_nl1i0OlOl_dataout & wire_nl1i0OlOi_dataout & wire_nl1i0OllO_dataout & wire_nl1i0Olll_dataout & wire_nl1i0Olli_dataout & wire_nl1i0OliO_dataout & wire_nl1i0Olil_dataout); + wire_nl1i0l10i_b <= ( "0" & "0" & "0" & nl1iiOi0O & nl1iiOi0l & nl1iiOi0i & nl1iiOi1O & nl1iiOi1l & nl1iiOi1i & nl1iiO0OO & nl1iiO0Ol & nl1iiO0Oi); + nl1i0l10i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i0l10i_a, + b => wire_nl1i0l10i_b, + cin => wire_gnd, + o => wire_nl1i0l10i_o + ); + wire_nl1i0ll0O_a <= ( nl1i1Ol0l & nl1i1Ol0i & nl1i1Ol1O & nl1i1Ol1l & nl1i1Ol1i & nl1i1OiOO & nl1i1OiOl & nl1i1OiOi & nl1i1OilO & nl1i1Oill & nl1i1Oili & nl1i10iOi); + wire_nl1i0ll0O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i0ll0O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i0ll0O_a, + b => wire_nl1i0ll0O_b, + cin => wire_gnd, + o => wire_nl1i0ll0O_o + ); + wire_nl1i0ll1O_a <= ( nl1i1Ol0l & nl1i1Ol0i & nl1i1Ol1O & nl1i1Ol1l & nl1i1Ol1i & nl1i1OiOO & nl1i1OiOl & nl1i1OiOi & nl1i1OilO & nl1i1Oill & nl1i1Oili & nl1i10iOi & "1"); + wire_nl1i0ll1O_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1i0ll1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl1i0ll1O_a, + b => wire_nl1i0ll1O_b, + cin => wire_gnd, + o => wire_nl1i0ll1O_o + ); + wire_nl1i0lOli_a <= ( nl1i1OlOi & nl1i1OllO & nl1i1Olll & nl1i1Olli & nl1i1OliO & nl1i1Olil & nl1i1Olii & nl1i1Ol0O & "1"); + wire_nl1i0lOli_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1i0lOli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1i0lOli_a, + b => wire_nl1i0lOli_b, + cin => wire_gnd, + o => wire_nl1i0lOli_o + ); + wire_nl1i0lOOi_a <= ( nl1i1OlOi & nl1i1OllO & nl1i1Olll & nl1i1Olli & nl1i1OliO & nl1i1Olil & nl1i1Olii & nl1i1Ol0O); + wire_nl1i0lOOi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i0lOOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i0lOOi_a, + b => wire_nl1i0lOOi_b, + cin => wire_gnd, + o => wire_nl1i0lOOi_o + ); + wire_nl1i0O0li_a <= ( nl1i1OOli & nl1i1OOiO & nl1i1OOil & nl1i1OOii & nl1i1OO0O & nl1i1OO0l & nl1i1OO0i & nl1i1OO1O & nl1i1OO1l & nl1i1OO1i & nl1i1OlOO & nl1i1OlOl & "1"); + wire_nl1i0O0li_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1i0O0li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl1i0O0li_a, + b => wire_nl1i0O0li_b, + cin => wire_gnd, + o => wire_nl1i0O0li_o + ); + wire_nl1i0O0Oi_a <= ( nl1i1OOli & nl1i1OOiO & nl1i1OOil & nl1i1OOii & nl1i1OO0O & nl1i1OO0l & nl1i1OO0i & nl1i1OO1O & nl1i1OO1l & nl1i1OO1i & nl1i1OlOO & nl1i1OlOl); + wire_nl1i0O0Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i0O0Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i0O0Oi_a, + b => wire_nl1i0O0Oi_b, + cin => wire_gnd, + o => wire_nl1i0O0Oi_o + ); + wire_nl1i0Ol0l_a <= ( nl1i0111O & nl1i0111l & nl1i0111i & nl1i1OOOO & nl1i1OOOl & nl1i1OOOi & nl1i1OOlO & nl1i1OOll); + wire_nl1i0Ol0l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i0Ol0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i0Ol0l_a, + b => wire_nl1i0Ol0l_b, + cin => wire_gnd, + o => wire_nl1i0Ol0l_o + ); + wire_nl1i0Ol1l_a <= ( nl1i0111O & nl1i0111l & nl1i0111i & nl1i1OOOO & nl1i1OOOl & nl1i1OOOi & nl1i1OOlO & nl1i1OOll & "1"); + wire_nl1i0Ol1l_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1i0Ol1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1i0Ol1l_a, + b => wire_nl1i0Ol1l_b, + cin => wire_gnd, + o => wire_nl1i0Ol1l_o + ); + wire_nl1i11lil_a <= ( nl1i1Ol0l & nl1i1Ol0i & nl1i1Ol1O & nl1i1Ol1l & nl1i1Ol1i & nl1i1OiOO & nl1i1OiOl & nl1i1OiOi & nl1i1OilO & nl1i1Oill & nl1i1Oili & nl1i10iOi & "1"); + wire_nl1i11lil_b <= ( wire_nlill0Oll_w_lg_nl1i11OiO58258w & wire_nlill0Oll_w_lg_nl1i11Oil58256w & wire_nlill0Oll_w_lg_nl1i11Oii58254w & wire_nlill0Oll_w_lg_nl1i11O0O58252w & wire_nlill0Oll_w_lg_nl1i11O0l58250w & wire_nlill0Oll_w_lg_nl1i11O0i58248w & wire_nlill0Oll_w_lg_nl1i11O1O58246w & wire_nlill0Oll_w_lg_nl1i11O1l58244w & wire_nlill0Oll_w_lg_nl1i11O1i58242w & wire_nlill0Oll_w_lg_nl1i11lOO58240w & wire_nlill0Oll_w_lg_nl1i11lOl58238w & wire_nlill0Oll_w_lg_nl1i1101O58236w & "1"); + nl1i11lil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl1i11lil_a, + b => wire_nl1i11lil_b, + cin => wire_gnd, + o => wire_nl1i11lil_o + ); + wire_nl1i11liO_a <= ( nl1i1OlOi & nl1i1OllO & nl1i1Olll & nl1i1Olli & nl1i1OliO & nl1i1Olil & nl1i1Olii & nl1i1Ol0O & "1"); + wire_nl1i11liO_b <= ( wire_nlill0Oll_w_lg_nl1i1011l58216w & wire_nlill0Oll_w_lg_nl1i1011i58214w & wire_nlill0Oll_w_lg_nl1i11OOO58212w & wire_nlill0Oll_w_lg_nl1i11OOl58210w & wire_nlill0Oll_w_lg_nl1i11OOi58208w & wire_nlill0Oll_w_lg_nl1i11OlO58206w & wire_nlill0Oll_w_lg_nl1i11Oll58204w & wire_nlill0Oll_w_lg_nl1i11Oli58202w & "1"); + nl1i11liO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1i11liO_a, + b => wire_nl1i11liO_b, + cin => wire_gnd, + o => wire_nl1i11liO_o + ); + wire_nl1i11lli_a <= ( nl1i1OOli & nl1i1OOiO & nl1i1OOil & nl1i1OOii & nl1i1OO0O & nl1i1OO0l & nl1i1OO0i & nl1i1OO1O & nl1i1OO1l & nl1i1OO1i & nl1i1OlOO & nl1i1OlOl & "1"); + wire_nl1i11lli_b <= ( wire_nlill0Oll_w_lg_nl1i101Ol58186w & wire_nlill0Oll_w_lg_nl1i101Oi58184w & wire_nlill0Oll_w_lg_nl1i101lO58182w & wire_nlill0Oll_w_lg_nl1i101ll58180w & wire_nlill0Oll_w_lg_nl1i101li58178w & wire_nlill0Oll_w_lg_nl1i101iO58176w & wire_nlill0Oll_w_lg_nl1i101il58174w & wire_nlill0Oll_w_lg_nl1i101ii58172w & wire_nlill0Oll_w_lg_nl1i1010O58170w & wire_nlill0Oll_w_lg_nl1i1010l58168w & wire_nlill0Oll_w_lg_nl1i1010i58166w & wire_nlill0Oll_w_lg_nl1i1011O58164w & "1"); + nl1i11lli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl1i11lli_a, + b => wire_nl1i11lli_b, + cin => wire_gnd, + o => wire_nl1i11lli_o + ); + wire_nl1i11lll_a <= ( nl1i0111O & nl1i0111l & nl1i0111i & nl1i1OOOO & nl1i1OOOl & nl1i1OOOi & nl1i1OOlO & nl1i1OOll & "1"); + wire_nl1i11lll_b <= ( wire_nlill0Oll_w_lg_nl1i100ii58144w & wire_nlill0Oll_w_lg_nl1i1000O58142w & wire_nlill0Oll_w_lg_nl1i1000l58140w & wire_nlill0Oll_w_lg_nl1i1000i58138w & wire_nlill0Oll_w_lg_nl1i1001O58136w & wire_nlill0Oll_w_lg_nl1i1001l58134w & wire_nlill0Oll_w_lg_nl1i1001i58132w & wire_nlill0Oll_w_lg_nl1i101OO58130w & "1"); + nl1i11lll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1i11lll_a, + b => wire_nl1i11lll_b, + cin => wire_gnd, + o => wire_nl1i11lll_o + ); + wire_nl1i11llO_a <= ( nl1i010il & nl1i010ii & nl1i0100O & nl1i0100l & nl1i0100i & nl1i0101O & nl1i0101l & nl1i0101i & nl1i011OO & nl1i011Ol & nl1i011Oi & nl1i011lO & "1"); + wire_nl1i11llO_b <= ( wire_nlill0Oll_w_lg_nl1i10ilO58114w & wire_nlill0Oll_w_lg_nl1i10ill58112w & wire_nlill0Oll_w_lg_nl1i10ili58110w & wire_nlill0Oll_w_lg_nl1i10iiO58108w & wire_nlill0Oll_w_lg_nl1i10iil58106w & wire_nlill0Oll_w_lg_nl1i10iii58104w & wire_nlill0Oll_w_lg_nl1i10i0O58102w & wire_nlill0Oll_w_lg_nl1i10i0l58100w & wire_nlill0Oll_w_lg_nl1i10i0i58098w & wire_nlill0Oll_w_lg_nl1i10i1O58096w & wire_nlill0Oll_w_lg_nl1i10i1l58094w & wire_nlill0Oll_w_lg_nl1i10i1i58092w & "1"); + nl1i11llO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl1i11llO_a, + b => wire_nl1i11llO_b, + cin => wire_gnd, + o => wire_nl1i11llO_o + ); + wire_nl1i11lOi_a <= ( nl1i011ll & nl1i011li & nl1i011iO & nl1i011il & nl1i011ii & nl1i0110O & nl1i0110l & nl1i0110i & "1"); + wire_nl1i11lOi_b <= ( wire_nlill0Oll_w_lg_nl1i100OO58072w & wire_nlill0Oll_w_lg_nl1i100Ol58070w & wire_nlill0Oll_w_lg_nl1i100Oi58068w & wire_nlill0Oll_w_lg_nl1i100lO58066w & wire_nlill0Oll_w_lg_nl1i100ll58064w & wire_nlill0Oll_w_lg_nl1i100li58062w & wire_nlill0Oll_w_lg_nl1i100iO58060w & wire_nlill0Oll_w_lg_nl1i100il58058w & "1"); + nl1i11lOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1i11lOi_a, + b => wire_nl1i11lOi_b, + cin => wire_gnd, + o => wire_nl1i11lOi_o + ); + wire_nl1i1iOOi_a <= ( nl1i11OiO & nl1i11Oil & nl1i11Oii & nl1i11O0O & nl1i11O0l & nl1i11O0i & nl1i11O1O & nl1i11O1l & nl1i11O1i & nl1i11lOO & nl1i11lOl & nl1i1101O); + wire_nl1i1iOOi_b <= ( "0" & "0" & "0" & nl0100lll & nl0100lli & nl0100liO & nl0100lil & nl0100lii & nl0100l0O & nl0100l0l & nl0100l0i & nl0100l1O); + nl1i1iOOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i1iOOi_a, + b => wire_nl1i1iOOi_b, + cin => wire_gnd, + o => wire_nl1i1iOOi_o + ); + wire_nl1i1l1OO_a <= ( nl1i1011l & nl1i1011i & nl1i11OOO & nl1i11OOl & nl1i11OOi & nl1i11OlO & nl1i11Oll & nl1i11Oli); + wire_nl1i1l1OO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i1l1OO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i1l1OO_a, + b => wire_nl1i1l1OO_b, + cin => wire_gnd, + o => wire_nl1i1l1OO_o + ); + wire_nl1i1llil_a <= ( nl1i101Ol & nl1i101Oi & nl1i101lO & nl1i101ll & nl1i101li & nl1i101iO & nl1i101il & nl1i101ii & nl1i1010O & nl1i1010l & nl1i1010i & nl1i1011O); + wire_nl1i1llil_b <= ( "0" & "0" & "0" & nl0100lll & nl0100lli & nl0100liO & nl0100lil & nl0100lii & nl0100l0O & nl0100l0l & nl0100l0i & nl0100l1O); + nl1i1llil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i1llil_a, + b => wire_nl1i1llil_b, + cin => wire_gnd, + o => wire_nl1i1llil_o + ); + wire_nl1i1lOli_a <= ( nl1i100ii & nl1i1000O & nl1i1000l & nl1i1000i & nl1i1001O & nl1i1001l & nl1i1001i & nl1i101OO); + wire_nl1i1lOli_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i1lOli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i1lOli_a, + b => wire_nl1i1lOli_b, + cin => wire_gnd, + o => wire_nl1i1lOli_o + ); + wire_nl1i1O00O_a <= ( nl1i10ilO & nl1i10ill & nl1i10ili & nl1i10iiO & nl1i10iil & nl1i10iii & nl1i10i0O & nl1i10i0l & nl1i10i0i & nl1i10i1O & nl1i10i1l & nl1i10i1i); + wire_nl1i1O00O_b <= ( "0" & "0" & "0" & nl0100lll & nl0100lli & nl0100liO & nl0100lil & nl0100lii & nl0100l0O & nl0100l0l & nl0100l0i & nl0100l1O); + nl1i1O00O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1i1O00O_a, + b => wire_nl1i1O00O_b, + cin => wire_gnd, + o => wire_nl1i1O00O_o + ); + wire_nl1i1OiiO_a <= ( nl1i100OO & nl1i100Ol & nl1i100Oi & nl1i100lO & nl1i100ll & nl1i100li & nl1i100iO & nl1i100il); + wire_nl1i1OiiO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1i1OiiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1i1OiiO_a, + b => wire_nl1i1OiiO_b, + cin => wire_gnd, + o => wire_nl1i1OiiO_o + ); + wire_nl1ii10iO_a <= ( nl1i011ll & nl1i011li & nl1i011iO & nl1i011il & nl1i011ii & nl1i0110O & nl1i0110l & nl1i0110i & "1"); + wire_nl1ii10iO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1ii10iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1ii10iO_a, + b => wire_nl1ii10iO_b, + cin => wire_gnd, + o => wire_nl1ii10iO_o + ); + wire_nl1ii10lO_a <= ( nl1i011ll & nl1i011li & nl1i011iO & nl1i011il & nl1i011ii & nl1i0110O & nl1i0110l & nl1i0110i); + wire_nl1ii10lO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1ii10lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1ii10lO_a, + b => wire_nl1ii10lO_b, + cin => wire_gnd, + o => wire_nl1ii10lO_o + ); + wire_nl1ii110l_a <= ( nl1i010il & nl1i010ii & nl1i0100O & nl1i0100l & nl1i0100i & nl1i0101O & nl1i0101l & nl1i0101i & nl1i011OO & nl1i011Ol & nl1i011Oi & nl1i011lO); + wire_nl1ii110l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1ii110l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1ii110l_a, + b => wire_nl1ii110l_b, + cin => wire_gnd, + o => wire_nl1ii110l_o + ); + wire_nl1ii111l_a <= ( nl1i010il & nl1i010ii & nl1i0100O & nl1i0100l & nl1i0100i & nl1i0101O & nl1i0101l & nl1i0101i & nl1i011OO & nl1i011Ol & nl1i011Oi & nl1i011lO & "1"); + wire_nl1ii111l_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1ii111l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nl1ii111l_a, + b => wire_nl1ii111l_b, + cin => wire_gnd, + o => wire_nl1ii111l_o + ); + wire_nl1iiO10l_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nl1iiO10l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1iiO10l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1iiO10l_a, + b => wire_nl1iiO10l_b, + cin => wire_gnd, + o => wire_nl1iiO10l_o + ); + wire_nl1iiO11l_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nl1iiO11l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1iiO11l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nl1iiO11l_a, + b => wire_nl1iiO11l_b, + cin => wire_gnd, + o => wire_nl1iiO11l_o + ); + wire_nl1iiO11O_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nl1iiO11O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1"); + nl1iiO11O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nl1iiO11O_a, + b => wire_nl1iiO11O_b, + cin => wire_gnd, + o => wire_nl1iiO11O_o + ); + wire_nl1iiO1ii_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nl1iiO1ii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "1"); + nl1iiO1ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nl1iiO1ii_a, + b => wire_nl1iiO1ii_b, + cin => wire_gnd, + o => wire_nl1iiO1ii_o + ); + wire_nl1il10lO_a <= ( wire_nl1lOOiOl_dataout & wire_nl1lOOiOi_dataout & wire_nl1lOOilO_dataout & wire_nl1lOOill_dataout & wire_nl1lOOili_dataout & wire_nl1lOOiiO_dataout & wire_nl1lOOiil_dataout & wire_nl1lOOiii_dataout); + wire_nl1il10lO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1il10lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1il10lO_a, + b => wire_nl1il10lO_b, + cin => wire_gnd, + o => wire_nl1il10lO_o + ); + wire_nl1iliill_w_lg_w_o_range56062w56066w(0) <= wire_nl1iliill_w_o_range56062w(0) AND wire_nl1iliill_w_lg_w_o_range56060w56061w(0); + wire_nl1iliill_w_lg_w_o_range56060w56980w(0) <= wire_nl1iliill_w_o_range56060w(0) AND wire_nl1iliill_w_lg_w_o_range56062w56063w(0); + wire_nl1iliill_w_lg_w_o_range56060w56061w(0) <= NOT wire_nl1iliill_w_o_range56060w(0); + wire_nl1iliill_w_lg_w_o_range56062w56063w(0) <= NOT wire_nl1iliill_w_o_range56062w(0); + wire_nl1iliill_a <= ( wire_nl1lOO1Ol_dataout & wire_nl1lOO1Oi_dataout & wire_nl1lOO1lO_dataout & wire_nl1lOO1ll_dataout & wire_nl1lOO1li_dataout & wire_nl1lOO1iO_dataout & wire_nl1lOO1il_dataout & wire_nl1lOO1ii_dataout & wire_nl1lOO10O_dataout & wire_nl1lOO10l_dataout & wire_nl1lOO10i_dataout & wire_nl1lOO11O_dataout); + wire_nl1iliill_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nl1lOOl1i_dataout & wire_nl1lOOiOO_dataout); + wire_nl1iliill_w_o_range56060w(0) <= wire_nl1iliill_o(0); + wire_nl1iliill_w_o_range56062w(0) <= wire_nl1iliill_o(1); + nl1iliill : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1iliill_a, + b => wire_nl1iliill_b, + cin => wire_gnd, + o => wire_nl1iliill_o + ); + wire_nl1llill_a <= ( nl1lli1i & nl1ll0OO); + wire_nl1llill_b <= ( "0" & "1"); + nl1llill : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl1llill_a, + b => wire_nl1llill_b, + cin => wire_gnd, + o => wire_nl1llill_o + ); + wire_nl1llliOi_a <= ( nl1ll0lll & nl1ll0lli & nl1ll0liO & nl1ll0lil & nl1ll0lii & nl1ll0l0O & nl1ll0l0l & nl1ll0l0i & nl1ll0l1O & nl1ll0l1l & "1"); + wire_nl1llliOi_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1llliOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nl1llliOi_a, + b => wire_nl1llliOi_b, + cin => wire_gnd, + o => wire_nl1llliOi_o + ); + wire_nl1lllll_a <= ( nl1lll1i & nl1lliOO); + wire_nl1lllll_b <= ( "0" & "1"); + nl1lllll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl1lllll_a, + b => wire_nl1lllll_b, + cin => wire_gnd, + o => wire_nl1lllll_o + ); + wire_nl1llO1ii_a <= ( wire_nl1llOOil_dataout & wire_nl1llOOii_dataout & wire_nl1llOO0O_dataout & wire_nl1llOO0l_dataout & wire_nl1llOO0i_dataout & wire_nl1llOO1O_dataout & wire_nl1llOO1l_dataout & wire_nl1llOO1i_dataout & wire_nl1llOlOO_dataout & wire_nl1llOlOl_dataout & "1"); + wire_nl1llO1ii_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1llO1ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nl1llO1ii_a, + b => wire_nl1llO1ii_b, + cin => wire_gnd, + o => wire_nl1llO1ii_o + ); + wire_nl1lO110l_a <= ( niOi1O1ll & wire_nl1lOOiOl_dataout & wire_nl1lOOiOi_dataout & wire_nl1lOOilO_dataout & wire_nl1lOOill_dataout & wire_nl1lOOili_dataout & wire_nl1lOOiiO_dataout & wire_nl1lOOiil_dataout & wire_nl1lOOiii_dataout & wire_nl1lOOi0O_dataout & wire_nl1lOOi0l_dataout); + wire_nl1lO110l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1lO110l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nl1lO110l_a, + b => wire_nl1lO110l_b, + cin => wire_gnd, + o => wire_nl1lO110l_o + ); + wire_nl1lO11ii_a <= ( niOi1O1ll & wire_nl1lOOiOl_dataout & wire_nl1lOOiOi_dataout & wire_nl1lOOilO_dataout & wire_nl1lOOill_dataout & wire_nl1lOOili_dataout & wire_nl1lOOiiO_dataout & wire_nl1lOOiil_dataout & wire_nl1lOOiii_dataout & wire_nl1lOOi0O_dataout & wire_nl1lOOi0l_dataout & "1"); + wire_nl1lO11ii_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1lO11ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nl1lO11ii_a, + b => wire_nl1lO11ii_b, + cin => wire_gnd, + o => wire_nl1lO11ii_o + ); + wire_nl1O101i_a <= ( nl1O110O & nl1lOOil); + wire_nl1O101i_b <= ( "0" & "1"); + nl1O101i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nl1O101i_a, + b => wire_nl1O101i_b, + cin => wire_gnd, + o => wire_nl1O101i_o + ); + wire_nl1OlilOO_a <= ( nl1Ol1Oil & nl1Ol1Oii & nl1Ol1O0O & nl1Ol1O0l & nl1Ol1O0i & nl1Ol1O1O & nl1Ol1O1l & nl1Ol1O1i & nl1Ol1lOO); + wire_nl1OlilOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OlilOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1OlilOO_a, + b => wire_nl1OlilOO_b, + cin => wire_gnd, + o => wire_nl1OlilOO_o + ); + wire_nl1OO1i1O_a <= ( nl1OO011O & nl1OO011l & nl1OO011i & nl1OO1OOO & nl1OO1OOl & nl1OO1OOi & nl1OO1OlO & nl1OO1Oll & nl1OO1Oli); + wire_nl1OO1i1O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1"); + nl1OO1i1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1OO1i1O_a, + b => wire_nl1OO1i1O_b, + cin => wire_gnd, + o => wire_nl1OO1i1O_o + ); + wire_nl1OO1ili_a <= ( "0" & nl1OO011O & nl1OO011l & nl1OO011i & nl1OO1OOO & nl1OO1OOl & nl1OO1OOi & nl1OO1OlO & nl1OO1Oll); + wire_nl1OO1ili_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OO1ili : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1OO1ili_a, + b => wire_nl1OO1ili_b, + cin => wire_gnd, + o => wire_nl1OO1ili_o + ); + wire_nl1OO1lOl_a <= ( "0" & nl1OO011O & nl1OO011l & nl1OO011i & nl1OO1OOO & nl1OO1OOl & nl1OO1OOi & nl1OO1OlO & nl1OO1Oll & nl1OO1Oli); + wire_nl1OO1lOl_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OO1lOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nl1OO1lOl_a, + b => wire_nl1OO1lOl_b, + cin => wire_gnd, + o => wire_nl1OO1lOl_o + ); + wire_nl1OO1lOO_a <= ( "0" & k_ptr0(26 DOWNTO 19)); + wire_nl1OO1lOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OO1lOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1OO1lOO_a, + b => wire_nl1OO1lOO_b, + cin => wire_gnd, + o => wire_nl1OO1lOO_o + ); + wire_nl1OO1O1i_a <= ( "0" & k_ptr0(26 DOWNTO 18)); + wire_nl1OO1O1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OO1O1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nl1OO1O1i_a, + b => wire_nl1OO1O1i_b, + cin => wire_gnd, + o => wire_nl1OO1O1i_o + ); + wire_nl1OOlOii_a <= ( nl1OOiili & nl1OOiiiO & nl1OOiiil & nl1OOiiii & nl1OOii0O & nl1OOii0l & nl1OOii0i); + wire_nl1OOlOii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OOlOii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nl1OOlOii_a, + b => wire_nl1OOlOii_b, + cin => wire_gnd, + o => wire_nl1OOlOii_o + ); + wire_nl1OOlOOO_a <= ( nl1OOil1l & nl1OOil1i & nl1OOiiOO & nl1OOiiOl & nl1OOiiOi & nl1OOiilO & nl1OOiill); + wire_nl1OOlOOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OOlOOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nl1OOlOOO_a, + b => wire_nl1OOlOOO_b, + cin => wire_gnd, + o => wire_nl1OOlOOO_o + ); + wire_nl1OOO0ii_a <= ( wire_nl01111lO_dataout & wire_nl01111ll_dataout & wire_nl01111li_dataout & wire_nl01111iO_dataout & wire_nl01111il_dataout & wire_nl01111ii_dataout & wire_nl011110O_dataout & wire_nl011110l_dataout); + wire_nl1OOO0ii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OOO0ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nl1OOO0ii_a, + b => wire_nl1OOO0ii_b, + cin => wire_gnd, + o => wire_nl1OOO0ii_o + ); + wire_nl1OOO0il_a <= ( k_ptr0(17 DOWNTO 9) & "1"); + wire_nl1OOO0il_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nl1OOO0il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nl1OOO0il_a, + b => wire_nl1OOO0il_b, + cin => wire_gnd, + o => wire_nl1OOO0il_o + ); + wire_nl1OOO0iO_a <= ( k_ptr0(8 DOWNTO 0)); + wire_nl1OOO0iO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OOO0iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1OOO0iO_a, + b => wire_nl1OOO0iO_b, + cin => wire_gnd, + o => wire_nl1OOO0iO_o + ); + wire_nl1OOOiOi_a <= ( wire_nl01111lO_dataout & wire_nl01111ll_dataout & wire_nl01111li_dataout & wire_nl01111iO_dataout & wire_nl01111il_dataout & wire_nl01111ii_dataout & wire_nl011110O_dataout & wire_nl011110l_dataout & wire_nl011110i_dataout); + wire_nl1OOOiOi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OOOiOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1OOOiOi_a, + b => wire_nl1OOOiOi_b, + cin => wire_gnd, + o => wire_nl1OOOiOi_o + ); + wire_nl1OOOOOl_a <= ( wire_nl011100O_dataout & wire_nl011100l_dataout & wire_nl011100i_dataout & wire_nl011101O_dataout & wire_nl011101l_dataout & wire_nl011101i_dataout & wire_nl01111OO_dataout & wire_nl01111Ol_dataout & wire_nl01111Oi_dataout); + wire_nl1OOOOOl_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nl1OOOOOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nl1OOOOOl_a, + b => wire_nl1OOOOOl_b, + cin => wire_gnd, + o => wire_nl1OOOOOl_o + ); + wire_nli10l0l_a <= ( nli101Ol & niOO1OiOi & niOO1OilO & niOO1Oill & "1"); + wire_nli10l0l_b <= ( wire_niOOO0O_w_lg_nli1001O6123w & wire_w_lg_niOO1Ol1i6094w & wire_w_lg_niOO1Oili6120w & wire_w_lg_niOO1OiiO6118w & "1"); + nli10l0l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nli10l0l_a, + b => wire_nli10l0l_b, + cin => wire_gnd, + o => wire_nli10l0l_o + ); + wire_nli10OOl_a <= ( nli1i0lO & niOO1Olil & niOO1Olli & niOO1OllO & "1"); + wire_nli10OOl_b <= ( wire_nl1000i_w_lg_nli1i1OO6078w & wire_w_lg_niOO1Olii6076w & wire_w_lg_niOO1OliO6074w & wire_w_lg_niOO1Olll6072w & "1"); + nli10OOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nli10OOl_a, + b => wire_nli10OOl_b, + cin => wire_gnd, + o => wire_nli10OOl_o + ); + wire_nlil0001i_a <= ( nlil01i1l & nlil01i1i & nlil010OO & nlil010Ol & nlil010Oi & nlil010lO & nlil010ll & nlil010li & nlil010iO & nlil010il & "1"); + wire_nlil0001i_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlil0001i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlil0001i_a, + b => wire_nlil0001i_b, + cin => wire_gnd, + o => wire_nlil0001i_o + ); + wire_nlil011li_a <= ( nlil1OOll & nlil1OOli & nlil1OOiO & nlil1lOli & "1"); + wire_nlil011li_b <= ( "1" & "1" & "1" & "0" & "1"); + nlil011li : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlil011li_a, + b => wire_nlil011li_b, + cin => wire_gnd, + o => wire_nlil011li_o + ); + wire_nlil01OiO_a <= ( nlil010ii & nlil0100O & nlil0100l & nlil0100i & nlil0101O & nlil0101l & nlil1OOlO & "1"); + wire_nlil01OiO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlil01OiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlil01OiO_a, + b => wire_nlil01OiO_b, + cin => wire_gnd, + o => wire_nlil01OiO_o + ); + wire_nlil100ll_a <= ( nlil11lOO & nlil11lOl & nlil11lOi & nlil11llO & nlil11lll); + wire_nlil100ll_b <= ( "0" & "0" & "0" & "0" & "1"); + nlil100ll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlil100ll_a, + b => wire_nlil100ll_b, + cin => wire_gnd, + o => wire_nlil100ll_o + ); + wire_nlil10iOl_a <= ( nlil11Oii & nlil11O0O & nlil11O0l & nlil11O0i & nlil11O1O); + wire_nlil10iOl_b <= ( "0" & "0" & "0" & "0" & "1"); + nlil10iOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlil10iOl_a, + b => wire_nlil10iOl_b, + cin => wire_gnd, + o => wire_nlil10iOl_o + ); + wire_nlil11l1i_a <= ( nlil1100O & nlil1100l & nlil1100i & nlil1101O); + wire_nlil11l1i_b <= ( "0" & "0" & "0" & "1"); + nlil11l1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nlil11l1i_a, + b => wire_nlil11l1i_b, + cin => wire_gnd, + o => wire_nlil11l1i_o + ); + wire_nliliOllO_a <= ( nliliO1iO & nliliO1il & nliliO1ii & nliliO10O); + wire_nliliOllO_b <= ( "0" & "1" & "1" & "1"); + nliliOllO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nliliOllO_a, + b => wire_nliliOllO_b, + cin => wire_gnd, + o => wire_nliliOllO_o + ); + wire_nliliOOii_a <= ( nliliO1iO & nliliO1il & nliliO1ii); + wire_nliliOOii_b <= ( "0" & "1" & "1"); + nliliOOii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_nliliOOii_a, + b => wire_nliliOOii_b, + cin => wire_gnd, + o => wire_nliliOOii_o + ); + wire_nlill10ii_a <= ( nliliO1iO & nliliO1il & nliliO1ii & nliliO10O); + wire_nlill10ii_b <= ( "0" & "0" & "1" & "1"); + nlill10ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nlill10ii_a, + b => wire_nlill10ii_b, + cin => wire_gnd, + o => wire_nlill10ii_o + ); + wire_nlill111l_a <= ( nliliO1iO & nliliO1il & nliliO1ii & nliliO10O); + wire_nlill111l_b <= ( "0" & "1" & "0" & "1"); + nlill111l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nlill111l_a, + b => wire_nlill111l_b, + cin => wire_gnd, + o => wire_nlill111l_o + ); + wire_nlill11lO_a <= ( nliliO1iO & nliliO1il); + wire_nlill11lO_b <= ( "0" & "1"); + nlill11lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nlill11lO_a, + b => wire_nlill11lO_b, + cin => wire_gnd, + o => wire_nlill11lO_o + ); + wire_nlill1i1l_a <= ( nliliO1iO & nliliO1il & nliliO1ii); + wire_nlill1i1l_b <= ( "0" & "0" & "1"); + nlill1i1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3, + width_o => 3 + ) + PORT MAP ( + a => wire_nlill1i1l_a, + b => wire_nlill1i1l_b, + cin => wire_gnd, + o => wire_nlill1i1l_o + ); + wire_nlill1iOi_a <= ( nliliO1iO & nliliO1il & nliliO1ii & nliliO10O); + wire_nlill1iOi_b <= ( "0" & "0" & "0" & "1"); + nlill1iOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4, + width_o => 4 + ) + PORT MAP ( + a => wire_nlill1iOi_a, + b => wire_nlill1iOi_b, + cin => wire_gnd, + o => wire_nlill1iOi_o + ); + wire_nlilOilii_a <= ( nlillOiOl & nlillOiOi & nlillOilO & nlillOill & nlillOili & nlillOiiO & "1"); + wire_nlilOilii_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlilOilii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlilOilii_a, + b => wire_nlilOilii_b, + cin => wire_gnd, + o => wire_nlilOilii_o + ); + wire_nll0lO1Oi_a <= ( nll0ll1Ol & nll0ll1Oi & nll0ll1lO & nll0ll1ll & nll0ll1li & nll0ll1iO & nll0ll1il & nll0ll1ii & nll0ll10O & nll0ll10l & nll0ll10i & nll0ll11O); + wire_nll0lO1Oi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nll0lO1Oi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nll0lO1Oi_a, + b => wire_nll0lO1Oi_b, + cin => wire_gnd, + o => wire_nll0lO1Oi_o + ); + wire_nll0lOOil_a <= ( nll0lOi1i & nll0lO0OO & nll0lO0Ol & nll0lO0Oi & nll0lO0lO & nll0lO0ll & nll0lO0li & nll0lO0iO & nll0lO0il & nll0lO0ii); + wire_nll0lOOil_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nll0lOOil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nll0lOOil_a, + b => wire_nll0lOOil_b, + cin => wire_gnd, + o => wire_nll0lOOil_o + ); + wire_nll0O00lO_a <= ( nll0ll1Ol & nll0ll1Oi & nll0ll1lO & nll0ll1ll & nll0ll1li & nll0ll1iO & nll0ll1il & nll0ll1ii & nll0ll10O & nll0ll10l & nll0ll10i & nll0ll11O & "1"); + wire_nll0O00lO_b <= ( wire_nl1000i_w_lg_nll0O101l36349w & wire_nl1000i_w_lg_nll0O101i36347w & wire_nl1000i_w_lg_nll0O11OO36345w & wire_nl1000i_w_lg_nll0O11Ol36343w & wire_nl1000i_w_lg_nll0O11Oi36341w & wire_nl1000i_w_lg_nll0O11lO36339w & wire_nl1000i_w_lg_nll0O11ll36337w & wire_nl1000i_w_lg_nll0O11li36335w & wire_nl1000i_w_lg_nll0O11iO36333w & wire_nl1000i_w_lg_nll0O11il36331w & wire_nl1000i_w_lg_nll0O11ii36329w & wire_nl1000i_w_lg_nll0lOi1O36327w & "1"); + nll0O00lO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nll0O00lO_a, + b => wire_nll0O00lO_b, + cin => wire_gnd, + o => wire_nll0O00lO_o + ); + wire_nlli00lii_a <= ( nlli1OO1i & nlli1OlOO & nlli1OlOl & nlli1OlOi & nlli1OllO & nlli1Olll & nlli1Olli & nlli1OliO & nlli1Olil & nlli1Olii & "1"); + wire_nlli00lii_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlli00lii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlli00lii_a, + b => wire_nlli00lii_b, + cin => wire_gnd, + o => wire_nlli00lii_o + ); + wire_nlli00liO_a <= ( nlli1OO1i & nlli1OlOO & nlli1OlOl & nlli1OlOi & nlli1OllO & nlli1Olll & nlli1Olli & nlli1OliO & nlli1Olil & nlli1Olii & nlli1Ol0O & "1"); + wire_nlli00liO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlli00liO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nlli00liO_a, + b => wire_nlli00liO_b, + cin => wire_gnd, + o => wire_nlli00liO_o + ); + wire_nlli00Oll_a <= ( niOiOi0Oi & wire_nlli0i1ll_dataout & wire_nlli0i1li_dataout & wire_nlli0i1iO_dataout & wire_nlli0i1il_dataout & wire_nlli0i1ii_dataout & wire_nlli0i10O_dataout & wire_nlli0i10l_dataout & wire_nlli0i10i_dataout & wire_nlli0i11O_dataout & wire_nlli0i11l_dataout); + wire_nlli00Oll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlli00Oll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlli00Oll_a, + b => wire_nlli00Oll_b, + cin => wire_gnd, + o => wire_nlli00Oll_o + ); + wire_nlli01l1l_a <= ( nlli1Ol0l & nlli1Ol0i & nlli1Ol1O & nlli1Ol1l & nlli1Ol1i & nlli1OiOO & nlli1OiOl & nlli1OiOi & nlli1OilO & nlli1Oill & "1"); + wire_nlli01l1l_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlli01l1l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlli01l1l_a, + b => wire_nlli01l1l_b, + cin => wire_gnd, + o => wire_nlli01l1l_o + ); + wire_nlli01Oll_a <= ( niOiOi0Oi & wire_nlli0i1ll_dataout & wire_nlli0i1li_dataout & wire_nlli0i1iO_dataout & wire_nlli0i1il_dataout & wire_nlli0i1ii_dataout & wire_nlli0i10O_dataout & wire_nlli0i10l_dataout & wire_nlli0i10i_dataout & wire_nlli0i11O_dataout); + wire_nlli01Oll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlli01Oll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nlli01Oll_a, + b => wire_nlli01Oll_b, + cin => wire_gnd, + o => wire_nlli01Oll_o + ); + wire_nlli0l1i_a <= ( nll0Oi0O & nll0Oi0l & nll0Oi0i & nll0Oi1O & nll0Oi1l & nll0Oi1i & nll0O0OO & nll0O0Ol & nll0O0Oi & "1"); + wire_nlli0l1i_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlli0l1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nlli0l1i_a, + b => wire_nlli0l1i_b, + cin => wire_gnd, + o => wire_nlli0l1i_o + ); + wire_nlliiOOi_a <= ( nll0Oi1ll & nll0Oi1li & nll0Oi1iO & nll0Oi1il & nll0Oi1ii & nll0Oi10O & nll0Oi10l & nll0Oi10i & nll0Oi11O & nll0Oi11l & "1"); + wire_nlliiOOi_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlliiOOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlliiOOi_a, + b => wire_nlliiOOi_b, + cin => wire_gnd, + o => wire_nlliiOOi_o + ); + wire_nlliiOOO_a <= ( nll0Oi1ll & nll0Oi1li & nll0Oi1iO & nll0Oi1il & nll0Oi1ii & nll0Oi10O & nll0Oi10l & nll0Oi10i & nll0Oi11O & nll0Oi11l); + wire_nlliiOOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlliiOOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nlliiOOO_a, + b => wire_nlliiOOO_b, + cin => wire_gnd, + o => wire_nlliiOOO_o + ); + wire_nlliOl1ii_a <= ( wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6) & wire_nlliOl1il_o(6 DOWNTO 1) & "1"); + wire_nlliOl1ii_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nl1000i_w_lg_nlll00iil35444w & wire_nl1000i_w_lg_nlll00iii35442w & wire_nl1000i_w_lg_nlll00i0O35440w & wire_nl1000i_w_lg_nlll00i0l35438w & wire_nl1000i_w_lg_nlll00i0i35436w & "1"); + nlliOl1ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 33, + width_b => 33, + width_o => 33 + ) + PORT MAP ( + a => wire_nlliOl1ii_a, + b => wire_nlliOl1ii_b, + cin => wire_gnd, + o => wire_nlliOl1ii_o + ); + wire_nlliOl1il_a <= ( "0" & nlll11liO & nlll11lil & nlll11lii & nlll11l0O & nlll11l0l & "1"); + wire_nlliOl1il_b <= ( "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlliOl1il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlliOl1il_a, + b => wire_nlliOl1il_b, + cin => wire_gnd, + o => wire_nlliOl1il_o + ); + wire_nlliOl1iO_a <= ( "0" & nlliOli1i & nlliOl0OO & nlliOl0Ol & nlliOl0Oi & nlliOl0lO & nlliOl0ll & nlliOl0li & "1"); + wire_nlliOl1iO_b <= ( "1" & wire_nl1000i_w_lg_nlliOl0iO35358w & wire_nl1000i_w_lg_nlliOl0il35356w & wire_nl1000i_w_lg_nlliOl0ii35354w & wire_nl1000i_w_lg_nlliOl00O35352w & wire_nl1000i_w_lg_nlliOl00l35350w & wire_nl1000i_w_lg_nlliOl00i35348w & wire_nl1000i_w_lg_nlliOl01O35346w & "1"); + nlliOl1iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlliOl1iO_a, + b => wire_nlliOl1iO_b, + cin => wire_gnd, + o => wire_nlliOl1iO_o + ); + wire_nlliOlOlO_a <= ( wire_nlliOlOOi_o(8 DOWNTO 0)); + wire_nlliOlOlO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlliOlOlO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlliOlOlO_a, + b => wire_nlliOlOlO_b, + cin => wire_gnd, + o => wire_nlliOlOlO_o + ); + wire_nlliOlOOi_a <= ( "0" & "0" & k_rtry(7 DOWNTO 1)); + wire_nlliOlOOi_b <= ( "0" & wire_nlliOl1iO_o(8 DOWNTO 1)); + nlliOlOOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9, + width_o => 9 + ) + PORT MAP ( + a => wire_nlliOlOOi_a, + b => wire_nlliOlOOi_b, + cin => wire_gnd, + o => wire_nlliOlOOi_o + ); + wire_nlliOO1il_a <= ( nlll1lO0O & nlll1lO0l & nlll1lO0i & nlll1lO1O & nlll1lO1l & nlll1lO1i & nlll1llOO); + wire_nlliOO1il_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlliOO1il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7, + width_o => 7 + ) + PORT MAP ( + a => wire_nlliOO1il_a, + b => wire_nlliOO1il_b, + cin => wire_gnd, + o => wire_nlliOO1il_o + ); + wire_nlll0010l_a <= ( nlll010Oi & nlll010lO & nlll010ll & nlll010li & nlll010iO & nlll010il & nlll010ii & nlll0100O & nlll0100l & nlll0100i); + wire_nlll0010l_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll0010l : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nlll0010l_a, + b => wire_nlll0010l_b, + cin => wire_gnd, + o => wire_nlll0010l_o + ); + wire_nlll01lll_a <= ( nlll010OO & nlll010Ol); + wire_nlll01lll_b <= ( "0" & "1"); + nlll01lll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2, + width_o => 2 + ) + PORT MAP ( + a => wire_nlll01lll_a, + b => wire_nlll01lll_b, + cin => wire_gnd, + o => wire_nlll01lll_o + ); + wire_nlll0iiOl_a <= ( nlll00iOO & nlll00iOl & nlll00iOi & nlll00ilO & nlll00ill & nlll00ili & nlll00iiO & nlll00iil & nlll00iii & nlll00i0O & nlll00i0l & nlll00i0i); + wire_nlll0iiOl_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll0iiOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nlll0iiOl_a, + b => wire_nlll0iiOl_b, + cin => wire_gnd, + o => wire_nlll0iiOl_o + ); + wire_nlll0lO1i_a <= ( nlliiiiil & nlliiiiii & nlliiii0O & nlliiii0l & nlliiii0i & nlliiii1O & nlliiii1l & nlliiii1i & nlliii0OO & nlliii0Ol & nlliii0Oi & nllii0OlO); + wire_nlll0lO1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll0lO1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nlll0lO1i_a, + b => wire_nlll0lO1i_b, + cin => wire_gnd, + o => wire_nlll0lO1i_o + ); + wire_nlll0lO1O_a <= ( nlliiiiil & nlliiiiii & nlliiii0O & nlliiii0l & nlliiii0i & nlliiii1O & nlliiii1l & nlliiii1i & nlliii0OO & nlliii0Ol & nlliii0Oi & nllii0OlO & "1"); + wire_nlll0lO1O_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlll0lO1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nlll0lO1O_a, + b => wire_nlll0lO1O_b, + cin => wire_gnd, + o => wire_nlll0lO1O_o + ); + wire_nlll0lOil_a <= ( wire_nlll0ll1O_dataout & wire_nlll0ll1l_dataout & wire_nlll0ll1i_dataout & wire_nlll0liOO_dataout & wire_nlll0liOl_dataout & wire_nlll0liOi_dataout & wire_nlll0lilO_dataout & wire_nlll0lill_dataout & wire_nlll0lili_dataout & wire_nlll0liiO_dataout & wire_nlll0liil_dataout & wire_nlll0liii_dataout & "1"); + wire_nlll0lOil_b <= ( wire_nl1000i_w_lg_nlll00i1O34381w & wire_nl1000i_w_lg_nlll00i1l34379w & wire_nl1000i_w_lg_nlll00i1i34377w & wire_nl1000i_w_lg_nlll000OO34375w & wire_nl1000i_w_lg_nlll000Ol34373w & wire_nl1000i_w_lg_nlll000Oi34371w & wire_nl1000i_w_lg_nlll000lO34369w & wire_nl1000i_w_lg_nlll000ll34367w & wire_nl1000i_w_lg_nlll000li34365w & wire_nl1000i_w_lg_nlll000iO34363w & wire_nl1000i_w_lg_nlll000il34361w & wire_nl1000i_w_lg_nlll01i1i34359w & "1"); + nlll0lOil : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nlll0lOil_a, + b => wire_nlll0lOil_b, + cin => wire_gnd, + o => wire_nlll0lOil_o + ); + wire_nlll0lOiO_a <= ( wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13) & wire_nlll0lOli_o(13 DOWNTO 1) & "1"); + wire_nlll0lOiO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & wire_nlll0ll1O_w_lg_dataout34299w & wire_nlll0ll1l_w_lg_dataout34297w & wire_nlll0ll1i_w_lg_dataout34295w & wire_nlll0liOO_w_lg_dataout34293w & wire_nlll0liOl_w_lg_dataout34291w & wire_nlll0liOi_w_lg_dataout34289w & wire_nlll0lilO_w_lg_dataout34287w & wire_nlll0lill_w_lg_dataout34285w & wire_nlll0lili_w_lg_dataout34283w & wire_nlll0liiO_w_lg_dataout34281w & wire_nlll0liil_w_lg_dataout34279w & wire_nlll0liii_w_lg_dataout34277w & "1"); + nlll0lOiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 33, + width_b => 33, + width_o => 33 + ) + PORT MAP ( + a => wire_nlll0lOiO_a, + b => wire_nlll0lOiO_b, + cin => wire_gnd, + o => wire_nlll0lOiO_o + ); + wire_nlll0lOli_a <= ( "0" & nlll00iOO & nlll00iOl & nlll00iOi & nlll00ilO & nlll00ill & nlll00ili & nlll00iiO & nlll00iil & nlll00iii & nlll00i0O & nlll00i0l & nlll00i0i & "1"); + wire_nlll0lOli_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlll0lOli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 14, + width_b => 14, + width_o => 14 + ) + PORT MAP ( + a => wire_nlll0lOli_a, + b => wire_nlll0lOli_b, + cin => wire_gnd, + o => wire_nlll0lOli_o + ); + wire_nlll10OlO_a <= ( nlliOOl0O & nlliOOl0l & nlliOOl0i & nlliOOl1O & nlliOOl1l & nlliOOl1i & nlliOOiOO & nlliOli1l); + wire_nlll10OlO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll10OlO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlll10OlO_a, + b => wire_nlll10OlO_b, + cin => wire_gnd, + o => wire_nlll10OlO_o + ); + wire_nlll10OOi_a <= ( nlliOOlOl & nlliOOlOi & nlliOOllO & nlliOOlll & nlliOOlli & nlliOOliO & nlliOOlil & nlliOOlii); + wire_nlll10OOi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll10OOi : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlll10OOi_a, + b => wire_nlll10OOi_b, + cin => wire_gnd, + o => wire_nlll10OOi_o + ); + wire_nlll1i1ii_a <= ( wire_nlliO0lOi_q(7 DOWNTO 0)); + wire_nlll1i1ii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll1i1ii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlll1i1ii_a, + b => wire_nlll1i1ii_b, + cin => wire_gnd, + o => wire_nlll1i1ii_o + ); + wire_nlll1iiOl_a <= ( nlll11O1i & nlll11lOO & nlll11lOl & nlll11lOi & nlll11llO & nlll11lll & nlll11lli & nlll11liO & nlll11lil & nlll11lii & nlll11l0O & nlll11l0l); + wire_nlll1iiOl_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll1iiOl : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nlll1iiOl_a, + b => wire_nlll1iiOl_b, + cin => wire_gnd, + o => wire_nlll1iiOl_o + ); + wire_nlll1iiOO_a <= ( nlll00i1O & nlll00i1l & nlll00i1i & nlll000OO & nlll000Ol & nlll000Oi & nlll000lO & nlll000ll & nlll000li & nlll000iO & nlll000il & nlll01i1i); + wire_nlll1iiOO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll1iiOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12, + width_o => 12 + ) + PORT MAP ( + a => wire_nlll1iiOO_a, + b => wire_nlll1iiOO_b, + cin => wire_gnd, + o => wire_nlll1iiOO_o + ); + wire_nlll1Olii_a <= ( nlll1lO0O & nlll1lO0l & nlll1lO0i & nlll1lO1O & nlll1lO1l & nlll1lO1i & nlll1llOO & nlll1llOl); + wire_nlll1Olii_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlll1Olii : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlll1Olii_a, + b => wire_nlll1Olii_b, + cin => wire_gnd, + o => wire_nlll1Olii_o + ); + wire_nllliOli_a <= ( nllliiiO & niOO01Oil & niOO01Oii & niOO01O0O & "1"); + wire_nllliOli_b <= ( wire_nl1000i_w_lg_nllliiOi4618w & wire_w_lg_niOO01Oll4589w & wire_w_lg_niOO01O0l4615w & wire_w_lg_niOO01O0i4613w & "1"); + nllliOli : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nllliOli_a, + b => wire_nllliOli_b, + cin => wire_gnd, + o => wire_nllliOli_o + ); + wire_nllll00i_a <= ( nlllllll & niOO0010i & niOO0010O & niOO001il & "1"); + wire_nllll00i_b <= ( wire_niOOO0O_w_lg_nlllliOi4573w & wire_w_lg_niOO0011O4571w & wire_w_lg_niOO0010l4569w & wire_w_lg_niOO001ii4567w & "1"); + nllll00i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nllll00i_a, + b => wire_nllll00i_b, + cin => wire_gnd, + o => wire_nllll00i_o + ); + wire_nlO0lll1O_a <= ( nlO0liliO & nlO0lilil & nlO0lilii & nlO0lil0O & nlO0lil0l & nlO0lil0i & nlO0lil1O & nlO0lil1l & nlO0lil1i & nlO0liiOO & "1"); + wire_nlO0lll1O_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlO0lll1O : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlO0lll1O_a, + b => wire_nlO0lll1O_b, + cin => wire_gnd, + o => wire_nlO0lll1O_o + ); + wire_nlO0lO00i_a <= ( niOl11O1l & wire_nlO0O001O_dataout & wire_nlO0O001l_dataout & wire_nlO0O001i_dataout & wire_nlO0O01OO_dataout & wire_nlO0O01Ol_dataout & wire_nlO0O01Oi_dataout & wire_nlO0O01lO_dataout & wire_nlO0O01ll_dataout & wire_nlO0O01li_dataout); + wire_nlO0lO00i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlO0lO00i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10, + width_o => 10 + ) + PORT MAP ( + a => wire_nlO0lO00i_a, + b => wire_nlO0lO00i_b, + cin => wire_gnd, + o => wire_nlO0lO00i_o + ); + wire_nlO0lO0il_a <= ( niOl11O1l & wire_nlO0O001O_dataout & wire_nlO0O001l_dataout & wire_nlO0O001i_dataout & wire_nlO0O01OO_dataout & wire_nlO0O01Ol_dataout & wire_nlO0O01Oi_dataout & wire_nlO0O01lO_dataout & wire_nlO0O01ll_dataout & wire_nlO0O01li_dataout & wire_nlO0O01iO_dataout); + wire_nlO0lO0il_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlO0lO0il : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlO0lO0il_a, + b => wire_nlO0lO0il_b, + cin => wire_gnd, + o => wire_nlO0lO0il_o + ); + wire_nlO0lOl0i_a <= ( niOl11O1l & wire_nlO0O001O_dataout & wire_nlO0O001l_dataout & wire_nlO0O001i_dataout & wire_nlO0O01OO_dataout & wire_nlO0O01Ol_dataout & wire_nlO0O01Oi_dataout & wire_nlO0O01lO_dataout & wire_nlO0O01ll_dataout & wire_nlO0O01li_dataout & wire_nlO0O01iO_dataout); + wire_nlO0lOl0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1"); + nlO0lOl0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlO0lOl0i_a, + b => wire_nlO0lOl0i_b, + cin => wire_gnd, + o => wire_nlO0lOl0i_o + ); + wire_nlO0O11iO_a <= ( nlO0liiOi & nlO0liilO & nlO0liill & nlO0liili & nlO0liiiO & nlO0liiil & nlO0liiii & nlO0lii0O & nlO0lii0l & nlO0lii0i & "1"); + wire_nlO0O11iO_b <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "1"); + nlO0O11iO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11, + width_o => 11 + ) + PORT MAP ( + a => wire_nlO0O11iO_a, + b => wire_nlO0O11iO_b, + cin => wire_gnd, + o => wire_nlO0O11iO_o + ); + wire_nlOil0ilO_a <= ( nlOil01lO & niOl10l0O & niOl10l0l & wire_w_lg_niOl10l0l28505w & "1"); + wire_nlOil0ilO_b <= ( wire_nl1000i_w_lg_nlOil1OOO28520w & wire_w_lg_niOl10l0i28518w & wire_w_lg_niOl10l1O28516w & wire_w_lg_w_lg_niOl10l1O28513w28514w & "1"); + nlOil0ilO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlOil0ilO_a, + b => wire_nlOil0ilO_b, + cin => wire_gnd, + o => wire_nlOil0ilO_o + ); + wire_nlOilllll_a <= ( nlOill0ll & niOl10Oil & niOl10Oii & wire_w_lg_niOl10Oii28320w & "1"); + wire_nlOilllll_b <= ( wire_niO01ill_w_lg_nlOill1Ol28335w & wire_w_lg_niOl10O0O28333w & wire_w_lg_niOl10O0l28331w & wire_w_lg_w_lg_niOl10O0l28328w28329w & "1"); + nlOilllll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlOilllll_a, + b => wire_nlOilllll_b, + cin => wire_gnd, + o => wire_nlOilllll_o + ); + wire_nlOiO1OiO_a <= ( nlOiO10ii & nlOiO100O & nlOiO100l & nlOiO100i & nlOiO101O & nlOiO101l & nlOiO101i & nlOiO11OO); + wire_nlOiO1OiO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOiO1OiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlOiO1OiO_a, + b => wire_nlOiO1OiO_b, + cin => wire_gnd, + o => wire_nlOiO1OiO_o + ); + wire_nlOiO1OOO_a <= ( nlOiO10Oi & nlOiO10lO & nlOiO10ll & nlOiO10li & nlOiO10iO); + wire_nlOiO1OOO_b <= ( "0" & "0" & "0" & "0" & "1"); + nlOiO1OOO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5, + width_o => 5 + ) + PORT MAP ( + a => wire_nlOiO1OOO_a, + b => wire_nlOiO1OOO_b, + cin => wire_gnd, + o => wire_nlOiO1OOO_o + ); + wire_nlOll0O1i_a <= ( nlOll000l & nlOll000i & nlOll001O & nlOll001l & nlOll001i & nlOll01OO & nlOll01Ol & nlOll01Oi & nlOll01lO & nlOll01ll & nlOll01li & nlOll01iO & nlOliO0ll); + wire_nlOll0O1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOll0O1i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13, + width_o => 13 + ) + PORT MAP ( + a => wire_nlOll0O1i_a, + b => wire_nlOll0O1i_b, + cin => wire_gnd, + o => wire_nlOll0O1i_o + ); + wire_nlOllli0i_a <= ( "0" & wire_niilll0O_dataout & wire_niilll0l_dataout & wire_niilll0i_dataout & wire_niilll1O_dataout & wire_niilll1l_dataout & wire_niilll1i_dataout & wire_niilliOO_dataout); + wire_nlOllli0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1"); + nlOllli0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlOllli0i_a, + b => wire_nlOllli0i_b, + cin => wire_gnd, + o => wire_nlOllli0i_o + ); + wire_nlOllll0i_a <= ( nlOlliOOl & nlOlliOOi & nlOlliOlO & nlOlliOll & nlOlliOli & nlOlliOiO & nlOlliOil & nlOlliOii & nlOlliO0O & nlOlliO0l & nlOlliO0i & nlOlliO1O & nlOlliO1l & nlOlliO1i); + wire_nlOllll0i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOllll0i : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 14, + width_b => 14, + width_o => 14 + ) + PORT MAP ( + a => wire_nlOllll0i_a, + b => wire_nlOllll0i_b, + cin => wire_gnd, + o => wire_nlOllll0i_o + ); + wire_nlOlOOOiO_a <= ( nlOlOilii & nlOlOil0O & nlOlOil0l & nlOlOil0i & nlOlOil1O & nlOlOil1l & nlOlOil1i & nlOlOi00l); + wire_nlOlOOOiO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOlOOOiO : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlOlOOOiO_a, + b => wire_nlOlOOOiO_b, + cin => wire_gnd, + o => wire_nlOlOOOiO_o + ); + wire_nlOO1OOll_a <= ( nlOO1O1lO & nlOO1O1ll & nlOO1O1li & nlOO1O1iO & nlOO1O1il & nlOO1O1ii & nlOO1O10O & nlOO1i1Oi); + wire_nlOO1OOll_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + nlOO1OOll : oper_add + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8, + width_o => 8 + ) + PORT MAP ( + a => wire_nlOO1OOll_a, + b => wire_nlOO1OOll_b, + cin => wire_gnd, + o => wire_nlOO1OOll_o + ); + wire_nl001lliO_i <= ( nl01i0OOi & nl01i0OlO & nl01i0Oll & nl01i0Oli & nl01i0OiO & nl01i0Oil); + nl001lliO : oper_decoder + GENERIC MAP ( + width_i => 6, + width_o => 64 + ) + PORT MAP ( + i => wire_nl001lliO_i, + o => wire_nl001lliO_o + ); + wire_nl00il01i_i <= ( nl11lO1Oi & nl11lO1lO & nl11lO1ll & nl11lO1li & nl11lO1iO & nl11lO1il); + nl00il01i : oper_decoder + GENERIC MAP ( + width_i => 6, + width_o => 64 + ) + PORT MAP ( + i => wire_nl00il01i_i, + o => wire_nl00il01i_o + ); + wire_n0000Oll_a <= ( n001iO0i & n001iO1O & n001iO1l & n001iO1i & n001ilOO & n001ilOl); + wire_n0000Oll_b <= ( wire_n000l1il_o(6 DOWNTO 1)); + n0000Oll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0000Oll_a, + b => wire_n0000Oll_b, + cin => wire_vcc, + o => wire_n0000Oll_o + ); + wire_n00010ll_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n00010ll_b <= ( n001iO0i & n001iO1O & n001iO1l & n001iO1i & n001ilOO & n001ilOl); + n00010ll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n00010ll_a, + b => wire_n00010ll_b, + cin => wire_gnd, + o => wire_n00010ll_o + ); + wire_n00010OO_a <= ( n001iO0i & n001iO1O & n001iO1l & n001iO1i & n001ilOO & n001ilOl); + wire_n00010OO_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n00010OO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n00010OO_a, + b => wire_n00010OO_b, + cin => wire_gnd, + o => wire_n00010OO_o + ); + wire_n000l1ii_a <= ( k_cnt(62 DOWNTO 57)); + wire_n000l1ii_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n000l1ii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n000l1ii_a, + b => wire_n000l1ii_b, + cin => wire_vcc, + o => wire_n000l1ii_o + ); + wire_n001101l_a <= ( n01OO0il & n01OO0ii & n01OO00O & n01OO00l); + wire_n001101l_b <= ( "1" & "0" & "0" & "1"); + n001101l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n001101l_a, + b => wire_n001101l_b, + cin => wire_gnd, + o => wire_n001101l_o + ); + wire_n00110Oi_a <= ( n01OO0il & n01OO0ii & n01OO00O & n01OO00l); + wire_n00110Oi_b <= ( "1" & "0" & "0" & "1"); + n00110Oi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n00110Oi_a, + b => wire_n00110Oi_b, + cin => wire_vcc, + o => wire_n00110Oi_o + ); + wire_n00liiOO_a <= ( "0" & "1"); + wire_n00liiOO_b <= ( n11li1li & n11li1iO); + n00liiOO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n00liiOO_a, + b => wire_n00liiOO_b, + cin => wire_gnd, + o => wire_n00liiOO_o + ); + wire_n00liO0O_a <= ( n00l0OlO & n00l0Oll & n00l0Oli & n00l0OiO); + wire_n00liO0O_b <= ( "1" & "0" & "0" & "1"); + n00liO0O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n00liO0O_a, + b => wire_n00liO0O_b, + cin => wire_gnd, + o => wire_n00liO0O_o + ); + wire_n00ll11l_a <= ( n00l0OlO & n00l0Oll & n00l0Oli & n00l0OiO); + wire_n00ll11l_b <= ( "1" & "0" & "0" & "1"); + n00ll11l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n00ll11l_a, + b => wire_n00ll11l_b, + cin => wire_vcc, + o => wire_n00ll11l_o + ); + wire_n00OiOOO_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n00OiOOO_b <= ( n00O1iil & n00O1iii & n00O1i0O & n00O1i0l & n00O1i0i & n00O1i1O); + n00OiOOO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n00OiOOO_a, + b => wire_n00OiOOO_b, + cin => wire_gnd, + o => wire_n00OiOOO_o + ); + wire_n00Ol10i_a <= ( n00O1iil & n00O1iii & n00O1i0O & n00O1i0l & n00O1i0i & n00O1i1O); + wire_n00Ol10i_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n00Ol10i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n00Ol10i_a, + b => wire_n00Ol10i_b, + cin => wire_gnd, + o => wire_n00Ol10i_o + ); + wire_n00OOiOO_a <= ( n00O1iil & n00O1iii & n00O1i0O & n00O1i0l & n00O1i0i & n00O1i1O); + wire_n00OOiOO_b <= ( wire_n0i11llO_o(6 DOWNTO 1)); + n00OOiOO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n00OOiOO_a, + b => wire_n00OOiOO_b, + cin => wire_vcc, + o => wire_n00OOiOO_o + ); + wire_n010i0ii_a <= ( "0" & "1"); + wire_n010i0ii_b <= ( n11li1li & n11li1iO); + n010i0ii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n010i0ii_a, + b => wire_n010i0ii_b, + cin => wire_gnd, + o => wire_n010i0ii_o + ); + wire_n010iiOi_a <= ( n0100l0i & n0100l1O & n0100l1l & n0100l1i); + wire_n010iiOi_b <= ( "1" & "0" & "0" & "1"); + n010iiOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n010iiOi_a, + b => wire_n010iiOi_b, + cin => wire_gnd, + o => wire_n010iiOi_o + ); + wire_n010iliO_a <= ( n0100l0i & n0100l1O & n0100l1l & n0100l1i); + wire_n010iliO_b <= ( "1" & "0" & "0" & "1"); + n010iliO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n010iliO_a, + b => wire_n010iliO_b, + cin => wire_vcc, + o => wire_n010iliO_o + ); + wire_n01iilii_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n01iilii_b <= ( n01i11OO & n01i11Ol & n01i11Oi & n01i11lO & n01i11ll & n01i11li); + n01iilii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n01iilii_a, + b => wire_n01iilii_b, + cin => wire_gnd, + o => wire_n01iilii_o + ); + wire_n01iilll_a <= ( n01i11OO & n01i11Ol & n01i11Oi & n01i11lO & n01i11ll & n01i11li); + wire_n01iilll_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n01iilll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n01iilll_a, + b => wire_n01iilll_b, + cin => wire_gnd, + o => wire_n01iilll_o + ); + wire_n01iO0ii_a <= ( n01i11OO & n01i11Ol & n01i11Oi & n01i11lO & n01i11ll & n01i11li); + wire_n01iO0ii_b <= ( wire_n01l1i0i_o(6 DOWNTO 1)); + n01iO0ii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n01iO0ii_a, + b => wire_n01iO0ii_b, + cin => wire_vcc, + o => wire_n01iO0ii_o + ); + wire_n01l1i1O_a <= ( k_cnt(62 DOWNTO 57)); + wire_n01l1i1O_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n01l1i1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n01l1i1O_a, + b => wire_n01l1i1O_b, + cin => wire_vcc, + o => wire_n01l1i1O_o + ); + wire_n01OOOll_a <= ( "0" & "1"); + wire_n01OOOll_b <= ( n11li1li & n11li1iO); + n01OOOll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n01OOOll_a, + b => wire_n01OOOll_b, + cin => wire_gnd, + o => wire_n01OOOll_o + ); + wire_n0i11lll_a <= ( k_cnt(62 DOWNTO 57)); + wire_n0i11lll_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0i11lll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0i11lll_a, + b => wire_n0i11lll_b, + cin => wire_vcc, + o => wire_n0i11lll_o + ); + wire_n0ii100i_a <= ( "0" & "1"); + wire_n0ii100i_b <= ( n11li1li & n11li1iO); + n0ii100i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n0ii100i_a, + b => wire_n0ii100i_b, + cin => wire_gnd, + o => wire_n0ii100i_o + ); + wire_n0ii1ili_a <= ( n0i0Ol1i & n0i0OiOO & n0i0OiOl & n0i0OiOi); + wire_n0ii1ili_b <= ( "1" & "0" & "0" & "1"); + n0ii1ili : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0ii1ili_a, + b => wire_n0ii1ili_b, + cin => wire_gnd, + o => wire_n0ii1ili_o + ); + wire_n0ii1l0O_a <= ( n0i0Ol1i & n0i0OiOO & n0i0OiOl & n0i0OiOi); + wire_n0ii1l0O_b <= ( "1" & "0" & "0" & "1"); + n0ii1l0O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0ii1l0O_a, + b => wire_n0ii1l0O_b, + cin => wire_vcc, + o => wire_n0ii1l0O_o + ); + wire_n0il1l0i_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n0il1l0i_b <= ( n0iil1lO & n0iil1ll & n0iil1li & n0iil1iO & n0iil1il & n0iil1ii); + n0il1l0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0il1l0i_a, + b => wire_n0il1l0i_b, + cin => wire_gnd, + o => wire_n0il1l0i_o + ); + wire_n0il1lil_a <= ( n0iil1lO & n0iil1ll & n0iil1li & n0iil1iO & n0iil1il & n0iil1ii); + wire_n0il1lil_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0il1lil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0il1lil_a, + b => wire_n0il1lil_b, + cin => wire_gnd, + o => wire_n0il1lil_o + ); + wire_n0ili00i_a <= ( n0iil1lO & n0iil1ll & n0iil1li & n0iil1iO & n0iil1il & n0iil1ii); + wire_n0ili00i_b <= ( wire_n0illi1i_o(6 DOWNTO 1)); + n0ili00i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0ili00i_a, + b => wire_n0ili00i_b, + cin => wire_vcc, + o => wire_n0ili00i_o + ); + wire_n0ill0OO_a <= ( k_cnt(62 DOWNTO 57)); + wire_n0ill0OO_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0ill0OO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0ill0OO_a, + b => wire_n0ill0OO_b, + cin => wire_vcc, + o => wire_n0ill0OO_o + ); + wire_n0l0l0il_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n0l0l0il_b <= ( n0l01O1i & n0l01lOO & n0l01lOl & n0l01lOi & n0l01llO & n0l01lll); + n0l0l0il : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0l0l0il_a, + b => wire_n0l0l0il_b, + cin => wire_gnd, + o => wire_n0l0l0il_o + ); + wire_n0l0l0lO_a <= ( n0l01O1i & n0l01lOO & n0l01lOl & n0l01lOi & n0l01llO & n0l01lll); + wire_n0l0l0lO_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0l0l0lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0l0l0lO_a, + b => wire_n0l0l0lO_b, + cin => wire_gnd, + o => wire_n0l0l0lO_o + ); + wire_n0l0OOil_a <= ( n0l01O1i & n0l01lOO & n0l01lOl & n0l01lOi & n0l01llO & n0l01lll); + wire_n0l0OOil_b <= ( wire_n0li010l_o(6 DOWNTO 1)); + n0l0OOil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0l0OOil_a, + b => wire_n0l0OOil_b, + cin => wire_vcc, + o => wire_n0l0OOil_o + ); + wire_n0l1iOil_a <= ( "0" & "1"); + wire_n0l1iOil_b <= ( n11li1li & n11li1iO); + n0l1iOil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n0l1iOil_a, + b => wire_n0l1iOil_b, + cin => wire_gnd, + o => wire_n0l1iOil_o + ); + wire_n0l1l0li_a <= ( n0l1i00l & n0l1i00i & n0l1i01O & n0l1i01l); + wire_n0l1l0li_b <= ( "1" & "0" & "0" & "1"); + n0l1l0li : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0l1l0li_a, + b => wire_n0l1l0li_b, + cin => wire_vcc, + o => wire_n0l1l0li_o + ); + wire_n0l1l1Ol_a <= ( n0l1i00l & n0l1i00i & n0l1i01O & n0l1i01l); + wire_n0l1l1Ol_b <= ( "1" & "0" & "0" & "1"); + n0l1l1Ol : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0l1l1Ol_a, + b => wire_n0l1l1Ol_b, + cin => wire_gnd, + o => wire_n0l1l1Ol_o + ); + wire_n0li010i_a <= ( k_cnt(62 DOWNTO 57)); + wire_n0li010i_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0li010i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0li010i_a, + b => wire_n0li010i_b, + cin => wire_vcc, + o => wire_n0li010i_o + ); + wire_n0lO1ilO_a <= ( "0" & "1"); + wire_n0lO1ilO_b <= ( n11li1li & n11li1iO); + n0lO1ilO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n0lO1ilO_a, + b => wire_n0lO1ilO_b, + cin => wire_gnd, + o => wire_n0lO1ilO_o + ); + wire_n0lO1O1O_a <= ( n0llOOiO & n0llOOil & n0llOOii & n0llOO0O); + wire_n0lO1O1O_b <= ( "1" & "0" & "0" & "1"); + n0lO1O1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0lO1O1O_a, + b => wire_n0lO1O1O_b, + cin => wire_gnd, + o => wire_n0lO1O1O_o + ); + wire_n0lO1OOl_a <= ( n0llOOiO & n0llOOil & n0llOOii & n0llOO0O); + wire_n0lO1OOl_b <= ( "1" & "0" & "0" & "1"); + n0lO1OOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0lO1OOl_a, + b => wire_n0lO1OOl_b, + cin => wire_vcc, + o => wire_n0lO1OOl_o + ); + wire_n0O1011i_a <= ( n0lOli0l & n0lOli0i & n0lOli1O & n0lOli1l & n0lOli1i & n0lOl0OO); + wire_n0O1011i_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0O1011i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0O1011i_a, + b => wire_n0O1011i_b, + cin => wire_gnd, + o => wire_n0O1011i_o + ); + wire_n0O11OlO_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n0O11OlO_b <= ( n0lOli0l & n0lOli0i & n0lOli1O & n0lOli1l & n0lOli1i & n0lOl0OO); + n0O11OlO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0O11OlO_a, + b => wire_n0O11OlO_b, + cin => wire_gnd, + o => wire_n0O11OlO_o + ); + wire_n0O1iilO_a <= ( n0lOli0l & n0lOli0i & n0lOli1O & n0lOli1l & n0lOli1i & n0lOl0OO); + wire_n0O1iilO_b <= ( wire_n0O1lliO_o(6 DOWNTO 1)); + n0O1iilO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0O1iilO_a, + b => wire_n0O1iilO_b, + cin => wire_vcc, + o => wire_n0O1iilO_o + ); + wire_n0O1llil_a <= ( k_cnt(62 DOWNTO 57)); + wire_n0O1llil_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0O1llil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0O1llil_a, + b => wire_n0O1llil_b, + cin => wire_vcc, + o => wire_n0O1llil_o + ); + wire_n0Oi1lO_a <= ( n0Oii1l & n0Oii1i & n0Oi0OO & n0Oi0Ol & n0Oi0Oi & n0Oi0lO & n0Oi0ll & n0Oi0li & n0Oi0iO & n0Oi0il); + wire_n0Oi1lO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + n0Oi1lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_n0Oi1lO_a, + b => wire_n0Oi1lO_b, + cin => wire_vcc, + o => wire_n0Oi1lO_o + ); + wire_n0Oil01i_a <= ( "0" & "1"); + wire_n0Oil01i_b <= ( n11li1li & n11li1iO); + n0Oil01i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n0Oil01i_a, + b => wire_n0Oil01i_b, + cin => wire_gnd, + o => wire_n0Oil01i_o + ); + wire_n0Oiliii_a <= ( n0OiiiOi & n0OiiilO & n0Oiiill & n0Oiiili); + wire_n0Oiliii_b <= ( "1" & "0" & "0" & "1"); + n0Oiliii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0Oiliii_a, + b => wire_n0Oiliii_b, + cin => wire_gnd, + o => wire_n0Oiliii_o + ); + wire_n0Oill1O_a <= ( n0OiiiOi & n0OiiilO & n0Oiiill & n0Oiiili); + wire_n0Oill1O_b <= ( "1" & "0" & "0" & "1"); + n0Oill1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n0Oill1O_a, + b => wire_n0Oill1O_b, + cin => wire_vcc, + o => wire_n0Oill1O_o + ); + wire_n0Olll0l_a <= ( n0Ol01iO & n0Ol01il & n0Ol01ii & n0Ol010O & n0Ol010l & n0Ol010i); + wire_n0Olll0l_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0Olll0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0Olll0l_a, + b => wire_n0Olll0l_b, + cin => wire_gnd, + o => wire_n0Olll0l_o + ); + wire_n0Olll1i_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n0Olll1i_b <= ( n0Ol01iO & n0Ol01il & n0Ol01ii & n0Ol010O & n0Ol010l & n0Ol010i); + n0Olll1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0Olll1i_a, + b => wire_n0Olll1i_b, + cin => wire_gnd, + o => wire_n0Olll1i_o + ); + wire_n0OO00lO_a <= ( k_cnt(62 DOWNTO 57)); + wire_n0OO00lO_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n0OO00lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0OO00lO_a, + b => wire_n0OO00lO_b, + cin => wire_vcc, + o => wire_n0OO00lO_o + ); + wire_n0OO101i_a <= ( n0Ol01iO & n0Ol01il & n0Ol01ii & n0Ol010O & n0Ol010l & n0Ol010i); + wire_n0OO101i_b <= ( wire_n0OO00Oi_o(6 DOWNTO 1)); + n0OO101i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n0OO101i_a, + b => wire_n0OO101i_b, + cin => wire_vcc, + o => wire_n0OO101i_o + ); + wire_n10ilOOl_a <= ( "0" & "0" & "1"); + wire_n10ilOOl_b <= ( "0" & niOO10l1i & "1"); + n10ilOOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n10ilOOl_a, + b => wire_n10ilOOl_b, + cin => wire_gnd, + o => wire_n10ilOOl_o + ); + wire_n10l1i1i_a <= ( "0" & "1"); + wire_n10l1i1i_b <= ( n11li1li & n11li1iO); + n10l1i1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n10l1i1i_a, + b => wire_n10l1i1i_b, + cin => wire_gnd, + o => wire_n10l1i1i_o + ); + wire_n10lil0l_a <= ( "0" & "1"); + wire_n10lil0l_b <= ( niOO10l1i & wire_w_lg_niOO10l1i20908w); + n10lil0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n10lil0l_a, + b => wire_n10lil0l_b, + cin => wire_gnd, + o => wire_n10lil0l_o + ); + wire_n110100l_w_lg_w_lg_o24931w24932w(0) <= wire_n110100l_w_lg_o24931w(0) AND niOli1iOl; + wire_n110100l_w_lg_w_lg_o23825w23826w(0) <= wire_n110100l_w_lg_o23825w(0) AND niOli1iOl; + wire_n110100l_w_lg_o24931w(0) <= wire_n110100l_o AND niOl1i00O; + wire_n110100l_w_lg_o23825w(0) <= wire_n110100l_o AND niOl1OOOO; + wire_n110100l_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + wire_n110100l_b <= ( wire_nlOii0Oii_dataout & "0" & "0" & "0" & "0" & wire_nlOlOi1lO_dataout & wire_nlOlOi1ll_dataout & wire_nlOlOi1li_dataout & wire_nlOlOi1iO_dataout & wire_nlOlOi1il_dataout & wire_nlOlOi1ii_dataout & wire_nlOlOi10O_dataout & wire_nlOlOi10l_dataout); + n110100l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13 + ) + PORT MAP ( + a => wire_n110100l_a, + b => wire_n110100l_b, + cin => wire_gnd, + o => wire_n110100l_o + ); + wire_n11010iO_w_lg_w_lg_o23823w23824w(0) <= wire_n11010iO_w_lg_o23823w(0) AND niOli1iOO; + wire_n11010iO_w_lg_w_lg_o24929w24930w(0) <= wire_n11010iO_w_lg_o24929w(0) AND niOli1iOO; + wire_n11010iO_w_lg_o23823w(0) <= wire_n11010iO_o AND niOl0111i; + wire_n11010iO_w_lg_o24929w(0) <= wire_n11010iO_o AND niOl1i0ii; + wire_n11010iO_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + wire_n11010iO_b <= ( wire_nlOii0Oii_dataout & "0" & "0" & "0" & "0" & wire_nlOlOi1lO_dataout & wire_nlOlOi1ll_dataout & wire_nlOlOi1li_dataout & wire_nlOlOi1iO_dataout & wire_nlOlOi1il_dataout & wire_nlOlOi1ii_dataout & wire_nlOlOi10O_dataout & wire_nlOlOi10l_dataout); + n11010iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 13, + width_b => 13 + ) + PORT MAP ( + a => wire_n11010iO_a, + b => wire_n11010iO_b, + cin => wire_gnd, + o => wire_n11010iO_o + ); + wire_n11O100l_a <= ( "0" & "0" & "1"); + wire_n11O100l_b <= ( n0i00l0i & n0i00l1O & n0i00l1l); + n11O100l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O100l_a, + b => wire_n11O100l_b, + cin => wire_gnd, + o => wire_n11O100l_o + ); + wire_n11O101l_a <= ( "0" & "0" & "1"); + wire_n11O101l_b <= ( n0iOO0il & n0iOO0ii & n0iOO00O); + n11O101l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O101l_a, + b => wire_n11O101l_b, + cin => wire_gnd, + o => wire_n11O101l_o + ); + wire_n11O10il_a <= ( "0" & "0" & "1"); + wire_n11O10il_b <= ( n00ilOOO & n00ilOOl & n00ilOOi); + n11O10il : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O10il_a, + b => wire_n11O10il_b, + cin => wire_gnd, + o => wire_n11O10il_o + ); + wire_n11O10ll_a <= ( "0" & "0" & "1"); + wire_n11O10ll_b <= ( n01O00ll & n01O00li & n01O00iO); + n11O10ll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O10ll_a, + b => wire_n11O10ll_b, + cin => wire_gnd, + o => wire_n11O10ll_o + ); + wire_n11O10Ol_a <= ( "0" & "0" & "1"); + wire_n11O10Ol_b <= ( n011llii & n011ll0O & n011ll0l); + n11O10Ol : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O10Ol_a, + b => wire_n11O10Ol_b, + cin => wire_gnd, + o => wire_n11O10Ol_o + ); + wire_n11O11ll_a <= ( "0" & "0" & "1"); + wire_n11O11ll_b <= ( n0O0Ol1i & n0O0OiOO & n0O0OiOl); + n11O11ll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O11ll_a, + b => wire_n11O11ll_b, + cin => wire_gnd, + o => wire_n11O11ll_o + ); + wire_n11O11Ol_a <= ( "0" & "0" & "1"); + wire_n11O11Ol_b <= ( n0ll0OlO & n0ll0Oll & n0ll0Oli); + n11O11Ol : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O11Ol_a, + b => wire_n11O11Ol_b, + cin => wire_gnd, + o => wire_n11O11Ol_o + ); + wire_n11O1i1i_a <= ( "0" & "0" & "1"); + wire_n11O1i1i_b <= ( n1Oi011O & n1Oi011l & n1Oi011i); + n11O1i1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_n11O1i1i_a, + b => wire_n11O1i1i_b, + cin => wire_gnd, + o => wire_n11O1i1i_o + ); + wire_n1l1Ol0i_a <= ( n1l1O1Ol & n1l1O1Oi & n1l1O1lO & n1l1O1ll & n1l1O1li & n1l1O1iO & n1l1O1il & n1l1Ol0l); + wire_n1l1Ol0i_b <= ( nlOlOi00i & nlOlOi01O & nlOlOi01l & nlOlOi01i & nlOlOi1OO & nlOlOi1Ol & nlOlOi1Oi & nlOlO0lOO); + n1l1Ol0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_n1l1Ol0i_a, + b => wire_n1l1Ol0i_b, + cin => wire_gnd, + o => wire_n1l1Ol0i_o + ); + wire_n1O000i_a <= ( wire_n0OOO0l_dataout & wire_n0OOO0i_dataout & wire_n0OOO1O_dataout & wire_n0OOO1l_dataout); + wire_n1O000i_b <= ( wire_n1O1iOi_o(4 DOWNTO 1)); + n1O000i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1O000i_a, + b => wire_n1O000i_b, + cin => wire_vcc, + o => wire_n1O000i_o + ); + wire_n1O001i_a <= ( "1" & "0" & "0" & "0"); + wire_n1O001i_b <= ( wire_n1O1iOi_o(4 DOWNTO 1)); + n1O001i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1O001i_a, + b => wire_n1O001i_b, + cin => wire_vcc, + o => wire_n1O001i_o + ); + wire_n1O101O_a <= ( "1" & "0" & "0" & "0"); + wire_n1O101O_b <= ( wire_n1O100i_o(4 DOWNTO 1)); + n1O101O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1O101O_a, + b => wire_n1O101O_b, + cin => wire_vcc, + o => wire_n1O101O_o + ); + wire_n1OiOl1O_a <= ( "0" & "1"); + wire_n1OiOl1O_b <= ( n11li1li & n11li1iO); + n1OiOl1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_n1OiOl1O_a, + b => wire_n1OiOl1O_b, + cin => wire_gnd, + o => wire_n1OiOl1O_o + ); + wire_n1OiOOiO_a <= ( n1OilOOO & n1OilOOl & n1OilOOi & n1OilOlO); + wire_n1OiOOiO_b <= ( "1" & "0" & "0" & "1"); + n1OiOOiO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1OiOOiO_a, + b => wire_n1OiOOiO_b, + cin => wire_gnd, + o => wire_n1OiOOiO_o + ); + wire_n1Ol110l_a <= ( n1OilOOO & n1OilOOl & n1OilOOi & n1OilOlO); + wire_n1Ol110l_b <= ( "1" & "0" & "0" & "1"); + n1Ol110l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_n1Ol110l_a, + b => wire_n1Ol110l_b, + cin => wire_vcc, + o => wire_n1Ol110l_o + ); + wire_n1OO0l1O_a <= ( n1Oliill & n1Oliili & n1OliiiO & n1Oliiil & n1Oliiii & n1Olii0O); + wire_n1OO0l1O_b <= ( wire_n1OOilOO_o(6 DOWNTO 1)); + n1OO0l1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n1OO0l1O_a, + b => wire_n1OO0l1O_b, + cin => wire_vcc, + o => wire_n1OO0l1O_o + ); + wire_n1OO111O_a <= ( "0" & "0" & "0" & "0" & "1" & "1"); + wire_n1OO111O_b <= ( n1Oliill & n1Oliili & n1OliiiO & n1Oliiil & n1Oliiii & n1Olii0O); + n1OO111O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n1OO111O_a, + b => wire_n1OO111O_b, + cin => wire_gnd, + o => wire_n1OO111O_o + ); + wire_n1OO11ii_a <= ( n1Oliill & n1Oliili & n1OliiiO & n1Oliiil & n1Oliiii & n1Olii0O); + wire_n1OO11ii_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n1OO11ii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n1OO11ii_a, + b => wire_n1OO11ii_b, + cin => wire_gnd, + o => wire_n1OO11ii_o + ); + wire_n1OOilOl_a <= ( k_cnt(62 DOWNTO 57)); + wire_n1OOilOl_b <= ( "0" & "0" & "0" & "1" & "0" & "0"); + n1OOilOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 6, + width_b => 6 + ) + PORT MAP ( + a => wire_n1OOilOl_a, + b => wire_n1OOilOl_b, + cin => wire_vcc, + o => wire_n1OOilOl_o + ); + wire_ni1010l_a <= ( "1" & "0" & "0" & "0"); + wire_ni1010l_b <= ( wire_ni1010O_o(4 DOWNTO 1)); + ni1010l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_ni1010l_a, + b => wire_ni1010l_b, + cin => wire_vcc, + o => wire_ni1010l_o + ); + wire_ni1i00l_a <= ( "1" & "0" & "0" & "0"); + wire_ni1i00l_b <= ( wire_ni100OO_o(4 DOWNTO 1)); + ni1i00l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_ni1i00l_a, + b => wire_ni1i00l_b, + cin => wire_vcc, + o => wire_ni1i00l_o + ); + wire_ni1i0il_a <= ( wire_ni1iO1O_dataout & wire_ni1iO1l_dataout & wire_ni1iO1i_dataout & wire_ni1ilOO_dataout); + wire_ni1i0il_b <= ( wire_ni100OO_o(4 DOWNTO 1)); + ni1i0il : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_ni1i0il_a, + b => wire_ni1i0il_b, + cin => wire_vcc, + o => wire_ni1i0il_o + ); + wire_nil0Olil_a <= ( "1" & "0" & "1"); + wire_nil0Olil_b <= ( k_conf(130 DOWNTO 128)); + nil0Olil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nil0Olil_a, + b => wire_nil0Olil_b, + cin => wire_vcc, + o => wire_nil0Olil_o + ); + wire_nil0OO1O_a <= ( "0" & "0" & "1"); + wire_nil0OO1O_b <= ( k_conf(130 DOWNTO 128)); + nil0OO1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nil0OO1O_a, + b => wire_nil0OO1O_b, + cin => wire_vcc, + o => wire_nil0OO1O_o + ); + wire_nili10lO_a <= ( "1" & "0" & "0"); + wire_nili10lO_b <= ( k_conf(130 DOWNTO 128)); + nili10lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nili10lO_a, + b => wire_nili10lO_b, + cin => wire_vcc, + o => wire_nili10lO_o + ); + wire_nili111i_a <= ( "0" & "1" & "0"); + wire_nili111i_b <= ( k_conf(130 DOWNTO 128)); + nili111i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nili111i_a, + b => wire_nili111i_b, + cin => wire_vcc, + o => wire_nili111i_o + ); + wire_nili11Ol_a <= ( "0" & "1" & "1"); + wire_nili11Ol_b <= ( k_conf(130 DOWNTO 128)); + nili11Ol : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nili11Ol_a, + b => wire_nili11Ol_b, + cin => wire_vcc, + o => wire_nili11Ol_o + ); + wire_nl00il01l_w_lg_o52792w(0) <= NOT wire_nl00il01l_o; + wire_nl00il01l_a <= ( "0" & "0"); + wire_nl00il01l_b <= ( "0" & "0"); + nl00il01l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 2, + width_b => 2 + ) + PORT MAP ( + a => wire_nl00il01l_a, + b => wire_nl00il01l_b, + cin => wire_gnd, + o => wire_nl00il01l_o + ); + wire_nl01i10lO_a <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0"); + wire_nl01i10lO_b <= ( wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout); + nl01i10lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nl01i10lO_a, + b => wire_nl01i10lO_b, + cin => wire_gnd, + o => wire_nl01i10lO_o + ); + wire_nl01il01i_a <= ( wire_nl01il0iO_dataout & wire_nl01il0il_dataout & wire_nl01il0ii_dataout & wire_nl01il00O_dataout & wire_nl01il00l_dataout & niOi001ll & "0" & "0" & "0" & "0" & "0"); + wire_nl01il01i_b <= ( nl01l0ili & nl01l0iiO & nl01l0iil & nl01l0iii & nl01l0i0O & nl01l0i0l & nl01l0i0i & nl01l0i1O & nl01l0i1l & nl01l0i1i & nl01l00OO); + nl01il01i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11 + ) + PORT MAP ( + a => wire_nl01il01i_a, + b => wire_nl01il01i_b, + cin => wire_gnd, + o => wire_nl01il01i_o + ); + wire_nl01illOl_w_lg_o53585w(0) <= wire_nl01illOl_o AND wire_w_lg_niOi0001l53584w(0); + wire_nl01illOl_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1"); + wire_nl01illOl_b <= ( nl01l0ili & nl01l0iiO & nl01l0iil & nl01l0iii & nl01l0i0O & nl01l0i0l & nl01l0i0i & nl01l0i1O & nl01l0i1l & nl01l0i1i & nl01l00OO); + nl01illOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11 + ) + PORT MAP ( + a => wire_nl01illOl_a, + b => wire_nl01illOl_b, + cin => wire_vcc, + o => wire_nl01illOl_o + ); + wire_nl01iOO1i_a <= ( nl0OOO1il & nl0OOO1ii & nl0OOO10O & nl0OOO10l & nl0OOO10i & nl0OOO11O & nl0OOO11l & nl0OOii1i); + wire_nl01iOO1i_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout); + nl01iOO1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl01iOO1i_a, + b => wire_nl01iOO1i_b, + cin => wire_gnd, + o => wire_nl01iOO1i_o + ); + wire_nl01iOO1l_w_lg_o53419w(0) <= wire_nl01iOO1l_o OR wire_nl01iOO1i_o; + wire_nl01iOO1l_a <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout); + wire_nl01iOO1l_b <= ( nl0OOO01i & nl0OOO1OO & nl0OOO1Ol & nl0OOO1Oi & nl0OOO1lO & nl0OOO1ll & nl0OOO1li & nl0OOO1iO); + nl01iOO1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl01iOO1l_a, + b => wire_nl01iOO1l_b, + cin => wire_gnd, + o => wire_nl01iOO1l_o + ); + wire_nl0il0iO_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl0il0iO_b <= ( wire_nl0iliil_o(12 DOWNTO 1)); + nl0il0iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0il0iO_a, + b => wire_nl0il0iO_b, + cin => wire_gnd, + o => wire_nl0il0iO_o + ); + wire_nl0il0ll_a <= ( nl0iOiiO & nl0iOiil & nl0iOiii & nl0iOi0O & nl0iOi0l & nl0iOi0i & nl0iOi1O & nl0iOi1l & nl0iOi1i & nl0iO0OO & nl0iO0Ol & nl0iO0Oi); + wire_nl0il0ll_b <= ( nl0ill0l & nl0ill0i & nl0ill1O & nl0ill1l & nl0ill1i & nl0iliOO & nl0iliOl & nl0iliOi & nl0ililO & nl0ilill & nl0ilili & nl0il1li); + nl0il0ll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0il0ll_a, + b => wire_nl0il0ll_b, + cin => wire_gnd, + o => wire_nl0il0ll_o + ); + wire_nl0ili0i_a <= ( "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl0ili0i_b <= ( wire_nl0iliiO_o(8 DOWNTO 1)); + nl0ili0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0ili0i_a, + b => wire_nl0ili0i_b, + cin => wire_gnd, + o => wire_nl0ili0i_o + ); + wire_nl0ili0O_a <= ( nl0iOl1l & nl0iOl1i & nl0iOiOO & nl0iOiOl & nl0iOiOi & nl0iOilO & nl0iOill & nl0iOili); + wire_nl0ili0O_b <= ( nl0illOi & nl0illlO & nl0illll & nl0illli & nl0illiO & nl0illil & nl0illii & nl0ill0O); + nl0ili0O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0ili0O_a, + b => wire_nl0ili0O_b, + cin => wire_gnd, + o => wire_nl0ili0O_o + ); + wire_nl0l0li0l_a <= ( "0" & "1" & "1"); + wire_nl0l0li0l_b <= ( nl0l0OiOl & nl0l0OiOi & nl0l0OilO); + nl0l0li0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nl0l0li0l_a, + b => wire_nl0l0li0l_b, + cin => wire_vcc, + o => wire_nl0l0li0l_o + ); + wire_nl0l0li1i_a <= ( "0" & "0" & "1"); + wire_nl0l0li1i_b <= ( nl0l0OiOl & nl0l0OiOi & nl0l0OilO); + nl0l0li1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nl0l0li1i_a, + b => wire_nl0l0li1i_b, + cin => wire_vcc, + o => wire_nl0l0li1i_o + ); + wire_nl0l0li1O_a <= ( "0" & "1" & "0"); + wire_nl0l0li1O_b <= ( nl0l0OiOl & nl0l0OiOi & nl0l0OilO); + nl0l0li1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nl0l0li1O_a, + b => wire_nl0l0li1O_b, + cin => wire_vcc, + o => wire_nl0l0li1O_o + ); + wire_nl0l0liii_a <= ( "1" & "0" & "0"); + wire_nl0l0liii_b <= ( nl0l0OiOl & nl0l0OiOi & nl0l0OilO); + nl0l0liii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 3, + width_b => 3 + ) + PORT MAP ( + a => wire_nl0l0liii_a, + b => wire_nl0l0liii_b, + cin => wire_vcc, + o => wire_nl0l0liii_o + ); + wire_nl0l0liO_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl0l0liO_b <= ( wire_nl0l0Oii_o(12 DOWNTO 1)); + nl0l0liO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0l0liO_a, + b => wire_nl0l0liO_b, + cin => wire_gnd, + o => wire_nl0l0liO_o + ); + wire_nl0l0lll_a <= ( nl0liOil & nl0liOii & nl0liO0O & nl0liO0l & nl0liO0i & nl0liO1O & nl0liO1l & nl0liO1i & nl0lilOO & nl0lilOl & nl0lilOi & nl0lillO); + wire_nl0l0lll_b <= ( nl0li10i & nl0li11O & nl0li11l & nl0li11i & nl0l0OOO & nl0l0OOl & nl0l0OOi & nl0l0OlO & nl0l0Oll & nl0l0Oli & nl0l0OiO & nl0l0ili); + nl0l0lll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0l0lll_a, + b => wire_nl0l0lll_b, + cin => wire_gnd, + o => wire_nl0l0lll_o + ); + wire_nl0l0O0i_a <= ( "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl0l0O0i_b <= ( wire_nl0l0Oil_o(8 DOWNTO 1)); + nl0l0O0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0l0O0i_a, + b => wire_nl0l0O0i_b, + cin => wire_gnd, + o => wire_nl0l0O0i_o + ); + wire_nl0l0O0O_a <= ( nl0ll11i & nl0liOOO & nl0liOOl & nl0liOOi & nl0liOlO & nl0liOll & nl0liOli & nl0liOiO); + wire_nl0l0O0O_b <= ( nl0li1lO & nl0li1ll & nl0li1li & nl0li1iO & nl0li1il & nl0li1ii & nl0li10O & nl0li10l); + nl0l0O0O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0l0O0O_a, + b => wire_nl0l0O0O_b, + cin => wire_gnd, + o => wire_nl0l0O0O_o + ); + wire_nl0ll0lli_a <= ( nl0lllO1i & nl0llllOO & nl0llllOl & nl0llllOi & nl0lllllO & nl0llllll & nl0llllli & nl0lllliO & nl0llllil & nl0llllii & nl0llll0O & nl0llll0l & nl0llll0i & nl0llll1O & nl0llll1l & nl0llll1i & nl0llliOO & nl0llliOl & nl0llliOi & nl0lllilO & nl0lllill & nl0lllili & nl0llliiO & nl0llliil & nl0llliii & nl0llli0O & nl0llli0l & nl0llli0i); + wire_nl0ll0lli_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout); + nl0ll0lli : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 28, + width_b => 28 + ) + PORT MAP ( + a => wire_nl0ll0lli_a, + b => wire_nl0ll0lli_b, + cin => wire_vcc, + o => wire_nl0ll0lli_o + ); + wire_nl0lli1li_a <= ( nl0llO1Ol & nl0llO1Oi & nl0llO1lO & nl0llO1ll & nl0llO1li & nl0llO1iO & nl0llO1il & nl0llO1ii & nl0llO10O & nl0llO10l & nl0llO10i & nl0llO11O & nl0llO11l & nl0llO11i & nl0lllOOO & nl0lllOOl & nl0lllOOi & nl0lllOlO & nl0lllOll & nl0lllOli & nl0lllOiO & nl0lllOil & nl0lllOii & nl0lllO0O & nl0lllO0l & nl0lllO0i & nl0lllO1O & nl0lllO1l); + wire_nl0lli1li_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout); + nl0lli1li : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 28, + width_b => 28 + ) + PORT MAP ( + a => wire_nl0lli1li_a, + b => wire_nl0lli1li_b, + cin => wire_vcc, + o => wire_nl0lli1li_o + ); + wire_nl0lOOi0i_a <= ( wire_nl0O10ilO_dataout & wire_nl0O10ill_dataout & wire_nl0O10ili_dataout & wire_nl0O10iiO_dataout & wire_nl0O10iil_dataout & wire_nl0O10iii_dataout & wire_nl0O10i0O_dataout & wire_nl0O10i0l_dataout & wire_nl0O10i0i_dataout & wire_nl0O10i1O_dataout & wire_nl0O10i1l_dataout & wire_nl0O10i1i_dataout & wire_nl0O100OO_dataout & wire_nl0O100Ol_dataout & wire_nl0O100Oi_dataout & wire_nl0O100lO_dataout & wire_nl0O100ll_dataout & wire_nl0O100li_dataout & wire_nl0O100iO_dataout & wire_nl0O100il_dataout & wire_nl0O100ii_dataout & wire_nl0O1000O_dataout & wire_nl0O1000l_dataout & wire_nl0O1000i_dataout & wire_nl0O1001O_dataout & wire_nl0O1001l_dataout & wire_nl0O1001i_dataout & wire_nl0O101OO_dataout); + wire_nl0lOOi0i_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout); + nl0lOOi0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 28, + width_b => 28 + ) + PORT MAP ( + a => wire_nl0lOOi0i_a, + b => wire_nl0lOOi0i_b, + cin => wire_vcc, + o => wire_nl0lOOi0i_o + ); + wire_nl0lOOO0i_a <= ( wire_nl0O10Oli_dataout & wire_nl0O10OiO_dataout & wire_nl0O10Oil_dataout & wire_nl0O10Oii_dataout & wire_nl0O10O0O_dataout & wire_nl0O10O0l_dataout & wire_nl0O10O0i_dataout & wire_nl0O10O1O_dataout & wire_nl0O10O1l_dataout & wire_nl0O10O1i_dataout & wire_nl0O10lOO_dataout & wire_nl0O10lOl_dataout & wire_nl0O10lOi_dataout & wire_nl0O10llO_dataout & wire_nl0O10lll_dataout & wire_nl0O10lli_dataout & wire_nl0O10liO_dataout & wire_nl0O10lil_dataout & wire_nl0O10lii_dataout & wire_nl0O10l0O_dataout & wire_nl0O10l0l_dataout & wire_nl0O10l0i_dataout & wire_nl0O10l1O_dataout & wire_nl0O10l1l_dataout & wire_nl0O10l1i_dataout & wire_nl0O10iOO_dataout & wire_nl0O10iOl_dataout & wire_nl0O10iOi_dataout); + wire_nl0lOOO0i_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout); + nl0lOOO0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 28, + width_b => 28 + ) + PORT MAP ( + a => wire_nl0lOOO0i_a, + b => wire_nl0lOOO0i_b, + cin => wire_vcc, + o => wire_nl0lOOO0i_o + ); + wire_nl0O0iOOl_a <= ( wire_nl0Oi11ii_dataout & wire_nl0Oi110O_dataout & wire_nl0Oi110l_dataout & wire_nl0Oi110i_dataout & wire_nl0Oi111O_dataout & wire_nl0Oi111l_dataout & wire_nl0Oi111i_dataout & wire_nl0O0OOOO_dataout & wire_nl0O0OOOl_dataout & wire_nl0O0OOOi_dataout & wire_nl0O0OOlO_dataout & wire_nl0O0OOll_dataout & wire_nl0O0OOli_dataout & wire_nl0O0OOiO_dataout & wire_nl0O0OOil_dataout & wire_nl0O0OOii_dataout & wire_nl0O0OO0O_dataout & wire_nl0O0OO0l_dataout & wire_nl0O0OO0i_dataout & wire_nl0O0OO1O_dataout & wire_nl0O0OO1l_dataout & wire_nl0O0OO1i_dataout & wire_nl0O0OlOO_dataout & wire_nl0O0OlOl_dataout & wire_nl0O0OlOi_dataout & wire_nl0O0OllO_dataout & wire_nl0O0Olll_dataout & wire_nl0O0Olli_dataout); + wire_nl0O0iOOl_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout); + nl0O0iOOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 28, + width_b => 28 + ) + PORT MAP ( + a => wire_nl0O0iOOl_a, + b => wire_nl0O0iOOl_b, + cin => wire_vcc, + o => wire_nl0O0iOOl_o + ); + wire_nl0O0l0Ol_a <= ( wire_nl0Oi1i0l_dataout & wire_nl0Oi1i0i_dataout & wire_nl0Oi1i1O_dataout & wire_nl0Oi1i1l_dataout & wire_nl0Oi1i1i_dataout & wire_nl0Oi10OO_dataout & wire_nl0Oi10Ol_dataout & wire_nl0Oi10Oi_dataout & wire_nl0Oi10lO_dataout & wire_nl0Oi10ll_dataout & wire_nl0Oi10li_dataout & wire_nl0Oi10iO_dataout & wire_nl0Oi10il_dataout & wire_nl0Oi10ii_dataout & wire_nl0Oi100O_dataout & wire_nl0Oi100l_dataout & wire_nl0Oi100i_dataout & wire_nl0Oi101O_dataout & wire_nl0Oi101l_dataout & wire_nl0Oi101i_dataout & wire_nl0Oi11OO_dataout & wire_nl0Oi11Ol_dataout & wire_nl0Oi11Oi_dataout & wire_nl0Oi11lO_dataout & wire_nl0Oi11ll_dataout & wire_nl0Oi11li_dataout & wire_nl0Oi11iO_dataout & wire_nl0Oi11il_dataout); + wire_nl0O0l0Ol_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout); + nl0O0l0Ol : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 28, + width_b => 28 + ) + PORT MAP ( + a => wire_nl0O0l0Ol_a, + b => wire_nl0O0l0Ol_b, + cin => wire_vcc, + o => wire_nl0O0l0Ol_o + ); + wire_nl0Ol10ii_a <= ( nl0OOO1il & nl0OOO1ii & nl0OOO10O & nl0OOO10l & nl0OOO10i & nl0OOO11O & nl0OOO11l & nl0OOii1i); + wire_nl0Ol10ii_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout); + nl0Ol10ii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0Ol10ii_a, + b => wire_nl0Ol10ii_b, + cin => wire_gnd, + o => wire_nl0Ol10ii_o + ); + wire_nl0Ol10il_a <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout); + wire_nl0Ol10il_b <= ( nl0OOO01i & nl0OOO1OO & nl0OOO1Ol & nl0OOO1Oi & nl0OOO1lO & nl0OOO1ll & nl0OOO1li & nl0OOO1iO); + nl0Ol10il : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0Ol10il_a, + b => wire_nl0Ol10il_b, + cin => wire_gnd, + o => wire_nl0Ol10il_o + ); + wire_nl0Ol10li_a <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout); + wire_nl0Ol10li_b <= ( nl0OOO1il & nl0OOO1ii & nl0OOO10O & nl0OOO10l & nl0OOO10i & nl0OOO11O & nl0OOO11l & nl0OOii1i); + nl0Ol10li : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0Ol10li_a, + b => wire_nl0Ol10li_b, + cin => wire_vcc, + o => wire_nl0Ol10li_o + ); + wire_nl0Ol10lO_a <= ( nl0OOO0iO & nl0OOO0il & nl0OOO0ii & nl0OOO00O & nl0OOO00l & nl0OOO00i & nl0OOO01O & nl0OOO01l); + wire_nl0Ol10lO_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout); + nl0Ol10lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl0Ol10lO_a, + b => wire_nl0Ol10lO_b, + cin => wire_vcc, + o => wire_nl0Ol10lO_o + ); + wire_nl0Ol1i0i_a <= ( wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout); + wire_nl0Ol1i0i_b <= ( "1" & "1" & "1" & "0" & "1" & "1" & "1" & "0" & "1" & "1"); + nl0Ol1i0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nl0Ol1i0i_a, + b => wire_nl0Ol1i0i_b, + cin => wire_vcc, + o => wire_nl0Ol1i0i_o + ); + wire_nl0Ol1i0l_w_lg_o47754w(0) <= wire_nl0Ol1i0l_o AND wire_nl0Ol1i0i_o; + wire_nl0Ol1i0l_w_lg_w_lg_o47754w47756w(0) <= wire_nl0Ol1i0l_w_lg_o47754w(0) OR wire_nl0Ol1i1l_w_lg_o47755w(0); + wire_nl0Ol1i0l_a <= ( "1" & "1" & "1" & "0" & "1" & "1" & "0" & "0" & "0" & "0"); + wire_nl0Ol1i0l_b <= ( wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout); + nl0Ol1i0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nl0Ol1i0l_a, + b => wire_nl0Ol1i0l_b, + cin => wire_vcc, + o => wire_nl0Ol1i0l_o + ); + wire_nl0Ol1i1i_a <= ( wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout); + wire_nl0Ol1i1i_b <= ( "1" & "1" & "1" & "1" & "0" & "1" & "1" & "1" & "1" & "1"); + nl0Ol1i1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nl0Ol1i1i_a, + b => wire_nl0Ol1i1i_b, + cin => wire_vcc, + o => wire_nl0Ol1i1i_o + ); + wire_nl0Ol1i1l_w_lg_o47755w(0) <= wire_nl0Ol1i1l_o AND wire_nl0Ol1i1i_o; + wire_nl0Ol1i1l_a <= ( "1" & "1" & "1" & "1" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nl0Ol1i1l_b <= ( wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout); + nl0Ol1i1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nl0Ol1i1l_a, + b => wire_nl0Ol1i1l_b, + cin => wire_vcc, + o => wire_nl0Ol1i1l_o + ); + wire_nl0Ol1iiO_a <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout); + wire_nl0Ol1iiO_b <= ( nl0OOi10O & nl0OOi10l & nl0OOi10i & nl0OOi11O & nl0OOi11l & nl0OOi11i & nl0OO0OOO & nl0OO0OOl & nl0OO0OOi & nl0OO0OlO & nl0OO0Oll & nl0OO0Oli & nl0OO0OiO & nl0OO0Oil & nl0OO0Oii & nl0OO1Oil & nl0OOi1li & nl0OOi1iO & nl0OOi1il & nl0OOi1ii); + nl0Ol1iiO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 20, + width_b => 20 + ) + PORT MAP ( + a => wire_nl0Ol1iiO_a, + b => wire_nl0Ol1iiO_b, + cin => wire_vcc, + o => wire_nl0Ol1iiO_o + ); + wire_nl0Ol1ill_a <= ( nl0OOi0ll & nl0OOi0li & nl0OOi0iO & nl0OOi0il & nl0OOi0ii & nl0OOi00O & nl0OOi00l & nl0OOi00i & nl0OOi01O & nl0OOi01l & nl0OOi01i & nl0OOi1OO & nl0OOi1Ol & nl0OOi1Oi & nl0OOi1lO & nl0OOi1ll & nl0OOi0OO & nl0OOi0Ol & nl0OOi0Oi & nl0OOi0lO); + wire_nl0Ol1ill_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout); + nl0Ol1ill : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 20, + width_b => 20 + ) + PORT MAP ( + a => wire_nl0Ol1ill_a, + b => wire_nl0Ol1ill_b, + cin => wire_vcc, + o => wire_nl0Ol1ill_o + ); + wire_nl0Ol1iOl_a <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout & wire_nilOilOi_dataout & wire_nilOillO_dataout & wire_nilOilll_dataout & wire_nilOilli_dataout & wire_nilOiliO_dataout & wire_nilOilil_dataout & wire_nilOilii_dataout & wire_nilOil0O_dataout & wire_nilOil0l_dataout & wire_nilOil0i_dataout & wire_nilOil1O_dataout & wire_nilOil1l_dataout); + wire_nl0Ol1iOl_b <= ( nl0Ol01Ol & nl0Ol01Oi & nl0Ol01lO & nl0Ol01ll & nl0Ol01li & nl0Ol01iO & nl0Ol01il & nl0Ol01ii & nl0Ol010O & nl0Ol010l & nl0Ol010i & nl0Ol011O & nl0Ol011l & nl0Ol011i & nl0Ol1OOO & nl0Ol1OOl & nl0Ol1OOi & nl0Ol1OlO & nl0Ol1Oll & nl0Ol1Oli & nl0Ol1OiO & nl0Ol1Oil & nl0Ol1Oii & nl0Ol1O0O & nl0Ol1O0l & nl0Ol1O0i & nl0Ol1O1O & nl0Ol1O1l & nl0Ol1O1i & nl0Ol1lOO & nl0Ol1lOl & nl0Ol1lOi & nl0Ol00ll & nl0Ol00li & nl0Ol00iO & nl0Ol00il & nl0Ol00ii & nl0Ol000O & nl0Ol000l & nl0Ol000i & nl0Ol001O & nl0Ol001l & nl0Ol001i & nl0Ol01OO); + nl0Ol1iOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 44, + width_b => 44 + ) + PORT MAP ( + a => wire_nl0Ol1iOl_a, + b => wire_nl0Ol1iOl_b, + cin => wire_vcc, + o => wire_nl0Ol1iOl_o + ); + wire_nl0Ol1l0l_w_lg_o48607w(0) <= wire_nl0Ol1l0l_o OR wire_nlill0Oll_w_lg_nl0OiOlil48606w(0); + wire_nl0Ol1l0l_a <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout); + wire_nl0Ol1l0l_b <= ( nl0Ol00ll & nl0Ol00li & nl0Ol00iO & nl0Ol00il & nl0Ol00ii & nl0Ol000O & nl0Ol000l & nl0Ol000i & nl0Ol001O & nl0Ol001l & nl0Ol001i & nl0Ol01OO); + nl0Ol1l0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0Ol1l0l_a, + b => wire_nl0Ol1l0l_b, + cin => wire_vcc, + o => wire_nl0Ol1l0l_o + ); + wire_nl0Ol1l1i_a <= ( nl0Ol0lOi & nl0Ol0llO & nl0Ol0lll & nl0Ol0lli & nl0Ol0liO & nl0Ol0lil & nl0Ol0lii & nl0Ol0l0O & nl0Ol0l0l & nl0Ol0l0i & nl0Ol0l1O & nl0Ol0l1l & nl0Ol0l1i & nl0Ol0iOO & nl0Ol0iOl & nl0Ol0iOi & nl0Ol0ilO & nl0Ol0ill & nl0Ol0ili & nl0Ol0iiO & nl0Ol0iil & nl0Ol0iii & nl0Ol0i0O & nl0Ol0i0l & nl0Ol0i0i & nl0Ol0i1O & nl0Ol0i1l & nl0Ol0i1i & nl0Ol00OO & nl0Ol00Ol & nl0Ol00Oi & nl0Ol00lO & nl0Ol0Oli & nl0Ol0OiO & nl0Ol0Oil & nl0Ol0Oii & nl0Ol0O0O & nl0Ol0O0l & nl0Ol0O0i & nl0Ol0O1O & nl0Ol0O1l & nl0Ol0O1i & nl0Ol0lOO & nl0Ol0lOl); + wire_nl0Ol1l1i_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout & wire_nilOiO0O_dataout & wire_nilOiO0l_dataout & wire_nilOiO0i_dataout & wire_nilOiO1O_dataout & wire_nilOiO1l_dataout & wire_nilOiO1i_dataout & wire_nilOilOO_dataout & wire_nilOilOl_dataout & wire_nilOilOi_dataout & wire_nilOillO_dataout & wire_nilOilll_dataout & wire_nilOilli_dataout & wire_nilOiliO_dataout & wire_nilOilil_dataout & wire_nilOilii_dataout & wire_nilOil0O_dataout & wire_nilOil0l_dataout & wire_nilOil0i_dataout & wire_nilOil1O_dataout & wire_nilOil1l_dataout); + nl0Ol1l1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 44, + width_b => 44 + ) + PORT MAP ( + a => wire_nl0Ol1l1i_a, + b => wire_nl0Ol1l1i_b, + cin => wire_vcc, + o => wire_nl0Ol1l1i_o + ); + wire_nl0Ol1lil_w_lg_o48604w(0) <= wire_nl0Ol1lil_o AND niOiil10i; + wire_nl0Ol1lil_a <= ( nl0Ol0Oli & nl0Ol0OiO & nl0Ol0Oil & nl0Ol0Oii & nl0Ol0O0O & nl0Ol0O0l & nl0Ol0O0i & nl0Ol0O1O & nl0Ol0O1l & nl0Ol0O1i & nl0Ol0lOO & nl0Ol0lOl); + wire_nl0Ol1lil_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout); + nl0Ol1lil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0Ol1lil_a, + b => wire_nl0Ol1lil_b, + cin => wire_vcc, + o => wire_nl0Ol1lil_o + ); + wire_nl0Ol1lli_a <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout); + wire_nl0Ol1lli_b <= ( nl0OO1lli & nl0OO1liO & nl0OO1lil & nl0OO1lii & nl0OO1l0O & nl0OO1l0l & nl0OO1l0i & nl0OO1l1O & nl0OO1l1l & nl0OO1l1i & nl0OO1iOO & nl0Ol0Oll); + nl0Ol1lli : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0Ol1lli_a, + b => wire_nl0Ol1lli_b, + cin => wire_vcc, + o => wire_nl0Ol1lli_o + ); + wire_nl0Ol1lll_a <= ( nl0OO1Oii & nl0OO1O0O & nl0OO1O0l & nl0OO1O0i & nl0OO1O1O & nl0OO1O1l & nl0OO1O1i & nl0OO1lOO & nl0OO1lOl & nl0OO1lOi & nl0OO1llO & nl0OO1lll); + wire_nl0Ol1lll_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout); + nl0Ol1lll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl0Ol1lll_a, + b => wire_nl0Ol1lll_b, + cin => wire_vcc, + o => wire_nl0Ol1lll_o + ); + wire_nl101i0iO_a <= ( "0" & "0" & "0" & "0" & wire_nilOi01i_dataout & wire_nilOi1OO_dataout & wire_nilOi1Ol_dataout & wire_nilOi1Oi_dataout & wire_nilOi1lO_dataout & wire_nilOi1ll_dataout & wire_nilOi1li_dataout & wire_nilOi1iO_dataout); + wire_nl101i0iO_b <= ( "0" & "0" & wire_nl101i0li_o(9 DOWNTO 0)); + nl101i0iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl101i0iO_a, + b => wire_nl101i0iO_b, + cin => wire_vcc, + o => wire_nl101i0iO_o + ); + wire_nl101O0OO_a <= ( wire_nilOi1il_dataout & wire_nilOi1ii_dataout & wire_nilOi10O_dataout & wire_nilOi10l_dataout & wire_nilOi10i_dataout); + wire_nl101O0OO_b <= ( "0" & "0" & "0" & "1" & "0"); + nl101O0OO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl101O0OO_a, + b => wire_nl101O0OO_b, + cin => wire_vcc, + o => wire_nl101O0OO_o + ); + wire_nl101Oi1i_a <= ( "0" & "0" & "0" & "0" & wire_nilOi01i_dataout & wire_nilOi1OO_dataout & wire_nilOi1Ol_dataout & wire_nilOi1Oi_dataout & wire_nilOi1lO_dataout & wire_nilOi1ll_dataout & wire_nilOi1li_dataout & wire_nilOi1iO_dataout); + wire_nl101Oi1i_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & k_gbl_hip(32)); + nl101Oi1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl101Oi1i_a, + b => wire_nl101Oi1i_b, + cin => wire_vcc, + o => wire_nl101Oi1i_o + ); + wire_nl101Oi1O_a <= ( "0" & "0" & "0" & "0" & wire_nilOi01i_dataout & wire_nilOi1OO_dataout & wire_nilOi1Ol_dataout & wire_nilOi1Oi_dataout & wire_nilOi1lO_dataout & wire_nilOi1ll_dataout & wire_nilOi1li_dataout & wire_nilOi1iO_dataout); + wire_nl101Oi1O_b <= ( "0" & "0" & wire_nl10iiOll_o(8 DOWNTO 0) & wire_nl10iilli_dataout); + nl101Oi1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl101Oi1O_a, + b => wire_nl101Oi1O_b, + cin => wire_vcc, + o => wire_nl101Oi1O_o + ); + wire_nl10lOO0l_w_lg_o58909w(0) <= wire_nl10lOO0l_o OR wire_w_lg_niOi1ii0l58908w(0); + wire_nl10lOO0l_a <= ( k_cnt(116 DOWNTO 112)); + wire_nl10lOO0l_b <= ( nl10O11iO & nl10O11il & nl10O11ii & nl10O110O & nl10lll0i); + nl10lOO0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl10lOO0l_a, + b => wire_nl10lOO0l_b, + cin => wire_vcc, + o => wire_nl10lOO0l_o + ); + wire_nl10lOO1i_w_lg_o58910w(0) <= wire_nl10lOO1i_o AND wire_w_lg_niOi1illO57815w(0); + wire_nl10lOO1i_a <= ( wire_nl10lOO1l_o(12 DOWNTO 1)); + wire_nl10lOO1i_b <= ( "0" & "0" & "0" & niOiO10iO & wire_nlill0l1i_dataout & wire_nlill0iOO_dataout & wire_nlill0iOl_dataout & wire_nlill0iOi_dataout & wire_nlill0ilO_dataout & "0" & "0" & "0"); + nl10lOO1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl10lOO1i_a, + b => wire_nl10lOO1i_b, + cin => wire_gnd, + o => wire_nl10lOO1i_o + ); + wire_nl10lOOiO_w_lg_o58802w(0) <= wire_nl10lOOiO_o AND wire_w_lg_niOi1ilOl57737w(0); + wire_nl10lOOiO_a <= ( wire_nl10lOOli_o(12 DOWNTO 1)); + wire_nl10lOOiO_b <= ( "0" & "0" & "0" & niOiO10iO & wire_nlill0l1i_dataout & wire_nlill0iOO_dataout & wire_nlill0iOl_dataout & wire_nlill0iOi_dataout & wire_nlill0ilO_dataout & "0" & "0" & "0"); + nl10lOOiO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl10lOOiO_a, + b => wire_nl10lOOiO_b, + cin => wire_gnd, + o => wire_nl10lOOiO_o + ); + wire_nl10lOOOi_w_lg_o58801w(0) <= wire_nl10lOOOi_o OR wire_w_lg_niOi1iiiO58800w(0); + wire_nl10lOOOi_a <= ( k_cnt(116 DOWNTO 112)); + wire_nl10lOOOi_b <= ( nl10O11Ol & nl10O11Oi & nl10O11lO & nl10O11ll & nl10O11li); + nl10lOOOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl10lOOOi_a, + b => wire_nl10lOOOi_b, + cin => wire_vcc, + o => wire_nl10lOOOi_o + ); + wire_nl10O110l_w_lg_o58694w(0) <= wire_nl10O110l_o OR wire_w_lg_niOi1iiOi58693w(0); + wire_nl10O110l_a <= ( k_cnt(116 DOWNTO 112)); + wire_nl10O110l_b <= ( nl10O100i & nl10O101O & nl10O101l & nl10O101i & nl10O11OO); + nl10O110l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 5, + width_b => 5 + ) + PORT MAP ( + a => wire_nl10O110l_a, + b => wire_nl10O110l_b, + cin => wire_vcc, + o => wire_nl10O110l_o + ); + wire_nl10O111i_w_lg_o58696w(0) <= wire_nl10O111i_o AND wire_w_lg_niOi1iill58695w(0); + wire_nl10O111i_a <= ( wire_nl10O111l_o(12 DOWNTO 1)); + wire_nl10O111i_b <= ( "0" & "0" & "0" & niOiO10iO & wire_nlill0l1i_dataout & wire_nlill0iOO_dataout & wire_nlill0iOl_dataout & wire_nlill0iOi_dataout & wire_nlill0ilO_dataout & "0" & "0" & "0"); + nl10O111i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl10O111i_a, + b => wire_nl10O111i_b, + cin => wire_gnd, + o => wire_nl10O111i_o + ); + wire_nl111000l_a <= ( "0" & "0" & "0" & niOi10OOO & wire_nl10iiO1l_dataout & wire_nl10iiO1i_dataout & wire_nl10iilOO_dataout & wire_nl10iilOl_dataout & wire_nl10iilOi_dataout & wire_nl10iillO_dataout & wire_nl10iilll_dataout & wire_nl10iilli_dataout); + wire_nl111000l_b <= ( nl1110OOl & nl1110OOi & nl1110OlO & nl1110Oll & nl1110Oli & nl1110OiO & nl1110Oil & nl1110Oii & nl1110O0O & nl1110O0l & nl1110O0i & nl1110O1O); + nl111000l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl111000l_a, + b => wire_nl111000l_b, + cin => wire_vcc, + o => wire_nl111000l_o + ); + wire_nl111001i_a <= ( "0" & "0" & "0" & niOi10OOO & wire_nl10iiO1l_dataout & wire_nl10iiO1i_dataout & wire_nl10iilOO_dataout & wire_nl10iilOl_dataout & wire_nl10iilOi_dataout & wire_nl10iillO_dataout & wire_nl10iilll_dataout & wire_nl10iilli_dataout); + wire_nl111001i_b <= ( nl1110i0i & nl1110i1O & nl1110i1l & nl1110i1i & nl11100OO & nl11100Ol & nl11100Oi & nl11100lO & nl11100ll & nl11100li & nl11100iO & nl11101il); + nl111001i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl111001i_a, + b => wire_nl111001i_b, + cin => wire_vcc, + o => wire_nl111001i_o + ); + wire_nl111l10i_a <= ( nl111l0ii & nl111l00O & nl111l00l & nl111l00i & nl111l01O & nl111l01l & nl111l01i & nl111l1OO & nl111l1Ol & nl111l1Oi & nl111l1lO & nl111iOli); + wire_nl111l10i_b <= ( "0" & "0" & "0" & niOiO10iO & wire_nlill0l1i_dataout & wire_nlill0iOO_dataout & wire_nlill0iOl_dataout & wire_nlill0iOi_dataout & wire_nlill0ilO_dataout & "0" & "0" & "0"); + nl111l10i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl111l10i_a, + b => wire_nl111l10i_b, + cin => wire_gnd, + o => wire_nl111l10i_o + ); + wire_nl111l1iO_w_lg_o61436w(0) <= wire_nl111l1iO_o OR wire_nlill0Oll_w_lg_w_lg_w_lg_nl111ll1i61431w61433w61435w(0); + wire_nl111l1iO_a <= ( nl111liOi & nl111lilO & nl111lill & nl111lili & nl111liiO & nl111liil & nl111liii & nl111li0O & nl111li0l & nl111li0i & nl111li1O & nl111li1l); + wire_nl111l1iO_b <= ( "0" & "0" & "0" & niOiO10iO & wire_nlill0l1i_dataout & wire_nlill0iOO_dataout & wire_nlill0iOl_dataout & wire_nlill0iOi_dataout & wire_nlill0ilO_dataout & "0" & "0" & "0"); + nl111l1iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl111l1iO_a, + b => wire_nl111l1iO_b, + cin => wire_gnd, + o => wire_nl111l1iO_o + ); + wire_nl111O0ll_a <= ( "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl111O0ll_b <= ( wire_nl111O0lO_o(8 DOWNTO 1)); + nl111O0ll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl111O0ll_a, + b => wire_nl111O0ll_b, + cin => wire_gnd, + o => wire_nl111O0ll_o + ); + wire_nl111Oi1O_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl111Oi1O_b <= ( wire_nl111Oi0i_o(12 DOWNTO 1)); + nl111Oi1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl111Oi1O_a, + b => wire_nl111Oi1O_b, + cin => wire_gnd, + o => wire_nl111Oi1O_o + ); + wire_nl111Oili_a <= ( "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl111Oili_b <= ( wire_nl111Oill_o(8 DOWNTO 1)); + nl111Oili : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl111Oili_a, + b => wire_nl111Oili_b, + cin => wire_gnd, + o => wire_nl111Oili_o + ); + wire_nl111OlOl_a <= ( "0" & "0" & "0" & "0" & "0" & "1" & "1" & "0"); + wire_nl111OlOl_b <= ( wire_nl111OlOO_o(8 DOWNTO 1)); + nl111OlOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 8, + width_b => 8 + ) + PORT MAP ( + a => wire_nl111OlOl_a, + b => wire_nl111OlOl_b, + cin => wire_gnd, + o => wire_nl111OlOl_o + ); + wire_nl1i110lO_a <= ( wire_nl1i11lil_o(12 DOWNTO 1)); + wire_nl1i110lO_b <= ( "0" & "0" & "0" & nl0100lll & nl0100lli & nl0100liO & nl0100lil & nl0100lii & nl0100l0O & nl0100l0l & nl0100l0i & nl0100l1O); + nl1i110lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1i110lO_a, + b => wire_nl1i110lO_b, + cin => wire_gnd, + o => wire_nl1i110lO_o + ); + wire_nl1i11i1O_a <= ( wire_nl1i11lli_o(12 DOWNTO 1)); + wire_nl1i11i1O_b <= ( "0" & "0" & "0" & nl0100lll & nl0100lli & nl0100liO & nl0100lil & nl0100lii & nl0100l0O & nl0100l0l & nl0100l0i & nl0100l1O); + nl1i11i1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1i11i1O_a, + b => wire_nl1i11i1O_b, + cin => wire_gnd, + o => wire_nl1i11i1O_o + ); + wire_nl1i11iil_a <= ( wire_nl1i11llO_o(12 DOWNTO 1)); + wire_nl1i11iil_b <= ( "0" & "0" & "0" & nl0100lll & nl0100lli & nl0100liO & nl0100lil & nl0100lii & nl0100l0O & nl0100l0l & nl0100l0i & nl0100l1O); + nl1i11iil : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1i11iil_a, + b => wire_nl1i11iil_b, + cin => wire_gnd, + o => wire_nl1i11iil_o + ); + wire_nl1i11iOi_a <= ( wire_nl1i11lil_o(12 DOWNTO 1)); + wire_nl1i11iOi_b <= ( "0" & "0" & "0" & wire_nl0101ilO_dataout & wire_nl0101ill_dataout & wire_nl0101ili_dataout & wire_nl0101iiO_dataout & wire_nl0101iil_dataout & wire_nl0101iii_dataout & wire_nl0101i0O_dataout & wire_nl0101i0l_dataout & wire_nl0101i0i_dataout); + nl1i11iOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1i11iOi_a, + b => wire_nl1i11iOi_b, + cin => wire_gnd, + o => wire_nl1i11iOi_o + ); + wire_nl1i11l0O_a <= ( wire_nl1i11llO_o(12 DOWNTO 1)); + wire_nl1i11l0O_b <= ( "0" & "0" & "0" & wire_nl0101ilO_dataout & wire_nl0101ill_dataout & wire_nl0101ili_dataout & wire_nl0101iiO_dataout & wire_nl0101iil_dataout & wire_nl0101iii_dataout & wire_nl0101i0O_dataout & wire_nl0101i0l_dataout & wire_nl0101i0i_dataout); + nl1i11l0O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1i11l0O_a, + b => wire_nl1i11l0O_b, + cin => wire_gnd, + o => wire_nl1i11l0O_o + ); + wire_nl1i11l1O_a <= ( wire_nl1i11lli_o(12 DOWNTO 1)); + wire_nl1i11l1O_b <= ( "0" & "0" & "0" & wire_nl0101ilO_dataout & wire_nl0101ill_dataout & wire_nl0101ili_dataout & wire_nl0101iiO_dataout & wire_nl0101iil_dataout & wire_nl0101iii_dataout & wire_nl0101i0O_dataout & wire_nl0101i0l_dataout & wire_nl0101i0i_dataout); + nl1i11l1O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1i11l1O_a, + b => wire_nl1i11l1O_b, + cin => wire_gnd, + o => wire_nl1i11l1O_o + ); + wire_nl1iililO_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + wire_nl1iililO_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + nl1iililO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11 + ) + PORT MAP ( + a => wire_nl1iililO_a, + b => wire_nl1iililO_b, + cin => wire_gnd, + o => wire_nl1iililO_o + ); + wire_nl1iiliOi_w_lg_o56528w(0) <= wire_nl1iiliOi_o AND wire_nl1iililO_o; + wire_nl1iiliOi_a <= ( wire_nl1iilliO_dataout & wire_nl1iillil_dataout & wire_nl1iillii_dataout & wire_nl1iill0O_dataout & wire_nl1iill0l_dataout & wire_nl1iill0i_dataout & wire_nl1iill1O_dataout & wire_nl1iill1l_dataout & wire_nl1iill1i_dataout & wire_nl1iiliOO_dataout & wire_nl1iiliOl_dataout & "0"); + wire_nl1iiliOi_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + nl1iiliOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1iiliOi_a, + b => wire_nl1iiliOi_b, + cin => wire_gnd, + o => wire_nl1iiliOi_o + ); + wire_nl1il001O_a <= ( nl1ll0lll & nl1ll0lli & nl1ll0liO & nl1ll0lil & nl1ll0lii & nl1ll0l0O & nl1ll0l0l & nl1ll0l0i & nl1ll0l1O & nl1ll0l1l & nl1ll0l1i); + wire_nl1il001O_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + nl1il001O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11 + ) + PORT MAP ( + a => wire_nl1il001O_a, + b => wire_nl1il001O_b, + cin => wire_gnd, + o => wire_nl1il001O_o + ); + wire_nl1il10OO_a <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1" & "0" & "0"); + wire_nl1il10OO_b <= ( wire_nl1lOOiOl_dataout & wire_nl1lOOiOi_dataout & wire_nl1lOOilO_dataout & wire_nl1lOOill_dataout & wire_nl1lOOili_dataout & wire_nl1lOOiiO_dataout & wire_nl1lOOiil_dataout & wire_nl1lOOiii_dataout & wire_nl1lOOi0O_dataout & wire_nl1lOOi0l_dataout); + nl1il10OO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nl1il10OO_a, + b => wire_nl1il10OO_b, + cin => wire_gnd, + o => wire_nl1il10OO_o + ); + wire_nl1ili00O_a <= ( wire_nl1lOOiOl_dataout & wire_nl1lOOiOi_dataout & wire_nl1lOOilO_dataout & wire_nl1lOOill_dataout & wire_nl1lOOili_dataout & wire_nl1lOOiiO_dataout & wire_nl1lOOiil_dataout & wire_nl1lOOiii_dataout & wire_nl1lOOi0O_dataout & wire_nl1lOOi0l_dataout); + wire_nl1ili00O_b <= ( wire_nl1iliill_o(11 DOWNTO 2)); + nl1ili00O : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nl1ili00O_a, + b => wire_nl1ili00O_b, + cin => wire_vcc, + o => wire_nl1ili00O_o + ); + wire_nl1ili0li_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0" & "0"); + wire_nl1ili0li_b <= ( wire_nl1lOO1Ol_dataout & wire_nl1lOO1Oi_dataout & wire_nl1lOO1lO_dataout & wire_nl1lOO1ll_dataout & wire_nl1lOO1li_dataout & wire_nl1lOO1iO_dataout & wire_nl1lOO1il_dataout & wire_nl1lOO1ii_dataout & wire_nl1lOO10O_dataout & wire_nl1lOO10l_dataout & wire_nl1lOO10i_dataout & wire_nl1lOO11O_dataout); + nl1ili0li : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1ili0li_a, + b => wire_nl1ili0li_b, + cin => wire_vcc, + o => wire_nl1ili0li_o + ); + wire_nl1ili0Oi_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "1"); + wire_nl1ili0Oi_b <= ( wire_nl1lOO1Ol_dataout & wire_nl1lOO1Oi_dataout & wire_nl1lOO1lO_dataout & wire_nl1lOO1ll_dataout & wire_nl1lOO1li_dataout & wire_nl1lOO1iO_dataout & wire_nl1lOO1il_dataout & wire_nl1lOO1ii_dataout & wire_nl1lOO10O_dataout & wire_nl1lOO10l_dataout & wire_nl1lOO10i_dataout & wire_nl1lOO11O_dataout); + nl1ili0Oi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1ili0Oi_a, + b => wire_nl1ili0Oi_b, + cin => wire_vcc, + o => wire_nl1ili0Oi_o + ); + wire_nl1ilii1i_w_lg_o56077w(0) <= wire_nl1ilii1i_o AND niOi1liOl; + wire_nl1ilii1i_w_lg_w_lg_o56077w56078w(0) <= wire_nl1ilii1i_w_lg_o56077w(0) OR niOi1liOO; + wire_nl1ilii1i_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + wire_nl1ilii1i_b <= ( wire_nl1lOO1Ol_dataout & wire_nl1lOO1Oi_dataout & wire_nl1lOO1lO_dataout & wire_nl1lOO1ll_dataout & wire_nl1lOO1li_dataout & wire_nl1lOO1iO_dataout & wire_nl1lOO1il_dataout & wire_nl1lOO1ii_dataout & wire_nl1lOO10O_dataout & wire_nl1lOO10l_dataout & wire_nl1lOO10i_dataout & wire_nl1lOO11O_dataout); + nl1ilii1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nl1ilii1i_a, + b => wire_nl1ilii1i_b, + cin => wire_vcc, + o => wire_nl1ilii1i_o + ); + wire_nl1llO1li_a <= ( wire_nl1llOOil_dataout & wire_nl1llOOii_dataout & wire_nl1llOO0O_dataout & wire_nl1llOO0l_dataout & wire_nl1llOO0i_dataout & wire_nl1llOO1O_dataout & wire_nl1llOO1l_dataout & wire_nl1llOO1i_dataout & wire_nl1llOlOO_dataout & wire_nl1llOlOl_dataout & wire_nl1llOlOi_dataout); + wire_nl1llO1li_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + nl1llO1li : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11 + ) + PORT MAP ( + a => wire_nl1llO1li_a, + b => wire_nl1llO1li_b, + cin => wire_gnd, + o => wire_nl1llO1li_o + ); + wire_nl1Ol0lii_a <= ( nl1OOii1i & nl1OOi0OO & nl1OOi0Ol & nl1OOi0Oi & nl1OOi0lO & nl1OOi0ll & nl1OOi0li & nl1OOi0iO & nl1OOi0il); + wire_nl1Ol0lii_b <= ( k_ptr0(26 DOWNTO 18)); + nl1Ol0lii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9 + ) + PORT MAP ( + a => wire_nl1Ol0lii_a, + b => wire_nl1Ol0lii_b, + cin => wire_gnd, + o => wire_nl1Ol0lii_o + ); + wire_nl1OlilOl_a <= ( wire_nl1OlilOO_o(8 DOWNTO 0)); + wire_nl1OlilOl_b <= ( k_ptr0(26 DOWNTO 18)); + nl1OlilOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9 + ) + PORT MAP ( + a => wire_nl1OlilOl_a, + b => wire_nl1OlilOl_b, + cin => wire_gnd, + o => wire_nl1OlilOl_o + ); + wire_nl1Olll0l_a <= ( nl1Ol011l & nl1Ol011i & nl1Ol1OOO & nl1Ol1OOl & nl1Ol1OOi & nl1Ol1OlO & nl1Ol1Oll & nl1Ol1Oli & nl1Ol1OiO); + wire_nl1Olll0l_b <= ( k_ptr0(26 DOWNTO 18)); + nl1Olll0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9 + ) + PORT MAP ( + a => wire_nl1Olll0l_a, + b => wire_nl1Olll0l_b, + cin => wire_gnd, + o => wire_nl1Olll0l_o + ); + wire_nl1OOi11i_a <= ( k_ptr0(26 DOWNTO 18)); + wire_nl1OOi11i_b <= ( nl1OOii1i & nl1OOi0OO & nl1OOi0Ol & nl1OOi0Oi & nl1OOi0lO & nl1OOi0ll & nl1OOi0li & nl1OOi0iO & nl1OOi0il); + nl1OOi11i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9 + ) + PORT MAP ( + a => wire_nl1OOi11i_a, + b => wire_nl1OOi11i_b, + cin => wire_vcc, + o => wire_nl1OOi11i_o + ); + wire_nl1OOOiOO_a <= ( wire_nl011100O_dataout & wire_nl011100l_dataout & wire_nl011100i_dataout & wire_nl011101O_dataout & wire_nl011101l_dataout & wire_nl011101i_dataout & wire_nl01111OO_dataout & wire_nl01111Ol_dataout & wire_nl01111Oi_dataout); + wire_nl1OOOiOO_b <= ( k_ptr0(17 DOWNTO 9)); + nl1OOOiOO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 9, + width_b => 9 + ) + PORT MAP ( + a => wire_nl1OOOiOO_a, + b => wire_nl1OOOiOO_b, + cin => wire_gnd, + o => wire_nl1OOOiOO_o + ); + wire_nli10l0i_a <= ( "1" & "0" & "0" & "0"); + wire_nli10l0i_b <= ( wire_nli10l0l_o(4 DOWNTO 1)); + nli10l0i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nli10l0i_a, + b => wire_nli10l0i_b, + cin => wire_vcc, + o => wire_nli10l0i_o + ); + wire_nli111i1i_a <= ( nli1100iO & nli1100il & nli1100ii & nli11000O & nli11000l & nli11000i & nli11001O & nli11001l & nli11001i & nli1101OO & nli1101Ol & nli1101Oi & nli1101lO & nli1101ll & nli1101li & nli1101iO & nli1101il & nli1101ii & nli11010O & nli11010l & nli11010i); + wire_nli111i1i_b <= ( wire_nilOl1OO_dataout & wire_nilOl1Ol_dataout & wire_nilOl1Oi_dataout & wire_nilOl1lO_dataout & wire_nilOl1ll_dataout & wire_nilOl1li_dataout & wire_nilOl1iO_dataout & wire_nilOl1il_dataout & wire_nilOl1ii_dataout & wire_nilOl10O_dataout & wire_nilOl10l_dataout & wire_nilOl10i_dataout & wire_nilOl11O_dataout & wire_nilOl11l_dataout & wire_nilOl11i_dataout & wire_nilOiOOO_dataout & wire_nilOiOOl_dataout & wire_nilOiOOi_dataout & wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout); + nli111i1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 21, + width_b => 21 + ) + PORT MAP ( + a => wire_nli111i1i_a, + b => wire_nli111i1i_b, + cin => wire_vcc, + o => wire_nli111i1i_o + ); + wire_nli1il0l_a <= ( wire_nlll0lii_dataout & wire_nlll0l0O_dataout & wire_nlll0l0l_dataout & wire_nlll0l0i_dataout); + wire_nli1il0l_b <= ( wire_nli10OOl_o(4 DOWNTO 1)); + nli1il0l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nli1il0l_a, + b => wire_nli1il0l_b, + cin => wire_vcc, + o => wire_nli1il0l_o + ); + wire_nli1il1l_a <= ( "1" & "0" & "0" & "0"); + wire_nli1il1l_b <= ( wire_nli10OOl_o(4 DOWNTO 1)); + nli1il1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nli1il1l_a, + b => wire_nli1il1l_b, + cin => wire_vcc, + o => wire_nli1il1l_o + ); + wire_nll0lOl1l_a <= ( nil11iil & nil11iii & nil11i0O & nil11i0l & nil11i0i & nil11i1O & nil11i1l & nil11i1i & nil110OO & nil110Ol); + wire_nll0lOl1l_b <= ( nll0lOi1i & nll0lO0OO & nll0lO0Ol & nll0lO0Oi & nll0lO0lO & nll0lO0ll & nll0lO0li & nll0lO0iO & nll0lO0il & nll0lO0ii); + nll0lOl1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nll0lOl1l_a, + b => wire_nll0lOl1l_b, + cin => wire_vcc, + o => wire_nll0lOl1l_o + ); + wire_nll0O00ll_a <= ( wire_nll0O00lO_o(12 DOWNTO 1)); + wire_nll0O00ll_b <= ( "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + nll0O00ll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nll0O00ll_a, + b => wire_nll0O00ll_b, + cin => wire_vcc, + o => wire_nll0O00ll_o + ); + wire_nll0O0i1i_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + wire_nll0O0i1i_b <= ( niOiOi0Oi & wire_nlli0i1ll_dataout & wire_nlli0i1li_dataout & wire_nlli0i1iO_dataout & wire_nlli0i1il_dataout & wire_nlli0i1ii_dataout & wire_nlli0i10O_dataout & wire_nlli0i10l_dataout & wire_nlli0i10i_dataout & wire_nlli0i11O_dataout & wire_nlli0i11l_dataout); + nll0O0i1i : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11 + ) + PORT MAP ( + a => wire_nll0O0i1i_a, + b => wire_nll0O0i1i_b, + cin => wire_gnd, + o => wire_nll0O0i1i_o + ); + wire_nll0O1il_a <= ( nll0Oi0O & nll0Oi0l & nll0Oi0i & nll0Oi1O & nll0Oi1l & nll0Oi1i & nll0O0OO & nll0O0Ol & nll0O0Oi & nll0O0lO); + wire_nll0O1il_b <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + nll0O1il : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 10, + width_b => 10 + ) + PORT MAP ( + a => wire_nll0O1il_a, + b => wire_nll0O1il_b, + cin => wire_vcc, + o => wire_nll0O1il_o + ); + wire_nlliOlOOl_a <= ( nlliOl0iO & nlliOl0il & nlliOl0ii & nlliOl00O & nlliOl00l & nlliOl00i & nlliOl01O); + wire_nlliOlOOl_b <= ( nlliOli1i & nlliOl0OO & nlliOl0Ol & nlliOl0Oi & nlliOl0lO & nlliOl0ll & nlliOl0li); + nlliOlOOl : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 7, + width_b => 7 + ) + PORT MAP ( + a => wire_nlliOlOOl_a, + b => wire_nlliOlOOl_b, + cin => wire_vcc, + o => wire_nlliOlOOl_o + ); + wire_nlll0lOii_a <= ( "1" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0"); + wire_nlll0lOii_b <= ( wire_nlll0lOiO_o(12 DOWNTO 1)); + nlll0lOii : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 12, + width_b => 12 + ) + PORT MAP ( + a => wire_nlll0lOii_a, + b => wire_nlll0lOii_b, + cin => wire_gnd, + o => wire_nlll0lOii_o + ); + wire_nllliOiO_a <= ( "1" & "0" & "0" & "0"); + wire_nllliOiO_b <= ( wire_nllliOli_o(4 DOWNTO 1)); + nllliOiO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nllliOiO_a, + b => wire_nllliOiO_b, + cin => wire_vcc, + o => wire_nllliOiO_o + ); + wire_nlllO1iO_a <= ( "1" & "0" & "0" & "0"); + wire_nlllO1iO_b <= ( wire_nllll00i_o(4 DOWNTO 1)); + nlllO1iO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlllO1iO_a, + b => wire_nlllO1iO_b, + cin => wire_vcc, + o => wire_nlllO1iO_o + ); + wire_nlllO1lO_a <= ( wire_nlllOlli_dataout & wire_nlllOliO_dataout & wire_nlllOlil_dataout & wire_nlllOlii_dataout); + wire_nlllO1lO_b <= ( wire_nllll00i_o(4 DOWNTO 1)); + nlllO1lO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlllO1lO_a, + b => wire_nlllO1lO_b, + cin => wire_vcc, + o => wire_nlllO1lO_o + ); + wire_nlOi1O0ll_a <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1" & "0"); + wire_nlOi1O0ll_b <= ( nlO0liliO & nlO0lilil & nlO0lilii & nlO0lil0O & nlO0lil0l & nlO0lil0i & nlO0lil1O & nlO0lil1l & nlO0lil1i & nlO0liiOO & nlO0liiOl); + nlOi1O0ll : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 11, + width_b => 11 + ) + PORT MAP ( + a => wire_nlOi1O0ll_a, + b => wire_nlOi1O0ll_b, + cin => wire_gnd, + o => wire_nlOi1O0ll_o + ); + wire_nlOil0iOi_a <= ( wire_niilO11O_dataout & wire_niilO11l_dataout & wire_niilO11i_dataout & wire_niillOOO_dataout); + wire_nlOil0iOi_b <= ( nlOil1Oll & nlOil1Oli & nlOil1OiO & nlOil1Oil); + nlOil0iOi : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlOil0iOi_a, + b => wire_nlOil0iOi_b, + cin => wire_vcc, + o => wire_nlOil0iOi_o + ); + wire_nlOillllO_a <= ( wire_niillOOl_dataout & wire_niillOOi_dataout & wire_niillOlO_dataout & wire_niillOll_dataout); + wire_nlOillllO_b <= ( nlOill1li & nlOill1iO & nlOill1il & nlOill1ii); + nlOillllO : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlOillllO_a, + b => wire_nlOillllO_b, + cin => wire_vcc, + o => wire_nlOillllO_o + ); + wire_nlOl1ll1l_a <= ( nlOil1Oll & nlOil1Oli & nlOil1OiO & nlOil1Oil); + wire_nlOl1ll1l_b <= ( wire_niilO1ii_dataout & wire_niilO10O_dataout & wire_niilO10l_dataout & wire_niilO10i_dataout); + nlOl1ll1l : oper_less_than + GENERIC MAP ( + sgate_representation => 0, + width_a => 4, + width_b => 4 + ) + PORT MAP ( + a => wire_nlOl1ll1l_a, + b => wire_nlOl1ll1l_b, + cin => wire_vcc, + o => wire_nlOl1ll1l_o + ); + wire_nl00l110i_data <= ( nl01lO0li & nl01lO0lO & nl01lO0Ol & nl01lOi1i & nl01lOi1O & nl01lOi0l & nl01lOiii & nl01lOiiO & nl01lOill & nl01lOiOi & nl01lOiOO & nl01lOl1l & nl01lOl0i & nl01lOl0O & nl01lOlil & nl01lOlli & nl01lOllO & nl01lOlOl & nl01lOO1i & nl01lOO1O & nl01lOO0l & nl01lOOii & nl01lOOiO & nl01lOOll & nl01lOOOi & nl01lOOOO & nl01O111l & nl01O110i & nl01O110O & nl01O11il & nl01O11li & nl01O11lO & nl01O11Ol & nl01O101i & nl01O101O & nl01O100l & nl01O10ii & nl01O10iO & nl01O10ll & nl01O10Oi & nl01O10OO & nl01O1i1l & nl01O1i0i & nl01O1i0O & nl01O1iil & nl01O1ili & nl01O1ilO & nl01O1iOl & nl01O1l1i & nl01O1l1O & nl01O1l0l & nl01O1lii & nl01O1liO & nl01O1lll & nl01O1lOi & nl01O1lOO & nl01O1O1l & nl01O1O0i & nl01O1O0O & nl01O1Oil & nl01O1Oli & nl01O1OlO & nl01O1OOl & nl01O011i); + wire_nl00l110i_sel <= ( wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout); + nl00l110i : oper_mux + GENERIC MAP ( + width_data => 64, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl00l110i_data, + o => wire_nl00l110i_o, + sel => wire_nl00l110i_sel + ); + wire_nl00l111O_data <= ( nl01lO0iO & nl01lO0ll & nl01lO0Oi & nl01lO0OO & nl01lOi1l & nl01lOi0i & nl01lOi0O & nl01lOiil & nl01lOili & nl01lOilO & nl01lOiOl & nl01lOl1i & nl01lOl1O & nl01lOl0l & nl01lOlii & nl01lOliO & nl01lOlll & nl01lOlOi & nl01lOlOO & nl01lOO1l & nl01lOO0i & nl01lOO0O & nl01lOOil & nl01lOOli & nl01lOOlO & nl01lOOOl & nl01O111i & nl01O111O & nl01O110l & nl01O11ii & nl01O11iO & nl01O11ll & nl01O11Oi & nl01O11OO & nl01O101l & nl01O100i & nl01O100O & nl01O10il & nl01O10li & nl01O10lO & nl01O10Ol & nl01O1i1i & nl01O1i1O & nl01O1i0l & nl01O1iii & nl01O1iiO & nl01O1ill & nl01O1iOi & nl01O1iOO & nl01O1l1l & nl01O1l0i & nl01O1l0O & nl01O1lil & nl01O1lli & nl01O1llO & nl01O1lOl & nl01O1O1i & nl01O1O1O & nl01O1O0l & nl01O1Oii & nl01O1OiO & nl01O1Oll & nl01O1OOi & nl01O1OOO); + wire_nl00l111O_sel <= ( wire_nilOiOlO_dataout & wire_nilOiOll_dataout & wire_nilOiOli_dataout & wire_nilOiOiO_dataout & wire_nilOiOil_dataout & wire_nilOiOii_dataout); + nl00l111O : oper_mux + GENERIC MAP ( + width_data => 64, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl00l111O_data, + o => wire_nl00l111O_o, + sel => wire_nl00l111O_sel + ); + wire_nl0l01OOi_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "1"); + wire_nl0l01OOi_sel <= ( wire_nl1lO00ii_dataout & wire_nl1lO000O_dataout & wire_nl1lO000l_dataout); + nl0l01OOi : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl0l01OOi_data, + o => wire_nl0l01OOi_o, + sel => wire_nl0l01OOi_sel + ); + wire_nliiO1l1i_w_lg_o44431w(0) <= NOT wire_nliiO1l1i_o; + wire_nliiO1l1i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0" & nliiOi11l & nliiOii1i & nliiOii1l & nliiOii1O & nliiOii0i & nliiOii0l & niOilll1i & nliiOiiil & nliiOiiiO & "0" & "0" & "0" & "0" & "0" & "0" & nliiOiili & nliiOiill & "0" & "0" & "0" & nliiOiiOi); + wire_nliiO1l1i_sel <= ( nliiO100l & nliiO100i & nliiO101O & nliiO101l & nliiO101i); + nliiO1l1i : oper_mux + GENERIC MAP ( + width_data => 32, + width_sel => 5 + ) + PORT MAP ( + data => wire_nliiO1l1i_data, + o => wire_nliiO1l1i_o, + sel => wire_nliiO1l1i_sel + ); + wire_nliliOiil_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & wire_nlill1l0l_dataout); + wire_nliliOiil_sel <= ( nliliO1il & nliliO1ii & nliliO10O); + nliliOiil : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliliOiil_data, + o => wire_nliliOiil_o, + sel => wire_nliliOiil_sel + ); + wire_nliliOlll_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nliliOlll_sel <= ( wire_nliliOllO_o(2 DOWNTO 0)); + nliliOlll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliliOlll_data, + o => wire_nliliOlll_o, + sel => wire_nliliOlll_sel + ); + wire_nliliOO0O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nliliOO0O_sel <= ( wire_nliliOOii_o(1 DOWNTO 0) & nliliO10O); + nliliOO0O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nliliOO0O_data, + o => wire_nliliOO0O_o, + sel => wire_nliliOO0O_sel + ); + wire_nlill100O_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nlill100O_sel <= ( wire_nlill10ii_o(2 DOWNTO 0)); + nlill100O : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlill100O_data, + o => wire_nlill100O_o, + sel => wire_nlill100O_sel + ); + wire_nlill111i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nlill111i_sel <= ( wire_nlill111l_o(2 DOWNTO 0)); + nlill111i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlill111i_data, + o => wire_nlill111i_o, + sel => wire_nlill111i_sel + ); + wire_nlill11ll_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nlill11ll_sel <= ( wire_nlill11lO_o(0) & nliliO1ii & nliliO10O); + nlill11ll : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlill11ll_data, + o => wire_nlill11ll_o, + sel => wire_nlill11ll_sel + ); + wire_nlill1i1i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nlill1i1i_sel <= ( wire_nlill1i1l_o(1 DOWNTO 0) & nliliO10O); + nlill1i1i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlill1i1i_data, + o => wire_nlill1i1i_o, + sel => wire_nlill1i1i_sel + ); + wire_nlill1ilO_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nlill1ilO_sel <= ( wire_nlill1iOi_o(2 DOWNTO 0)); + nlill1ilO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlill1ilO_data, + o => wire_nlill1ilO_o, + sel => wire_nlill1ilO_sel + ); + wire_nlill1l0i_data <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0" & nl0illlll); + wire_nlill1l0i_sel <= ( nliliO1il & nliliO1ii & nliliO10O); + nlill1l0i : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlill1l0i_data, + o => wire_nlill1l0i_o, + sel => wire_nlill1l0i_sel + ); + wire_nlillllOO_w_lg_o42294w(0) <= NOT wire_nlillllOO_o; + wire_nlillllOO_data <= ( wire_niO1110i_dataout & wire_niO1111O_dataout & wire_niO1111l_dataout & wire_niO1111i_dataout & wire_nilOOOOO_dataout & wire_nilOOOOl_dataout & wire_nilOOOOi_dataout & wire_nilOOOlO_dataout); + wire_nlillllOO_sel <= ( nlillOl0O & nlillOl0l & nlillOl0i); + nlillllOO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlillllOO_data, + o => wire_nlillllOO_o, + sel => wire_nlillllOO_sel + ); + wire_nlilllOiO_w_lg_o42807w(0) <= wire_nlilllOiO_o OR wire_nlillllOO_w_lg_o42294w(0); + wire_nlilllOiO_data <= ( nlillii0i & nlillii1O & nlillii1l & nlillii1i & nlilli0OO & nlilli0Ol & nlilli0Oi & nlillil1l); + wire_nlilllOiO_sel <= ( nlillOl0O & nlillOl0l & nlillOl0i); + nlilllOiO : oper_mux + GENERIC MAP ( + width_data => 8, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilllOiO_data, + o => wire_nlilllOiO_o, + sel => wire_nlilllOiO_sel + ); + wire_n0OO0li_data <= ( n0Ol0Oi & "0" & wire_n0OOiii_dataout & wire_n0OOi1l_dataout); + wire_n0OO0li_sel <= ( n0Oli1i & n0Ol0OO & n0Ol0Ol & n0Ol0Oi); + n0OO0li : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0li_data, + o => wire_n0OO0li_o, + sel => wire_n0OO0li_sel + ); + wire_n0OO0ll_data <= ( n0Ol0Ol & niOO0il1O & wire_n0OOiil_dataout & wire_n0OOi1O_dataout); + wire_n0OO0ll_sel <= ( n0Oli1i & n0Ol0OO & n0Ol0Ol & n0Ol0Oi); + n0OO0ll : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0ll_data, + o => wire_n0OO0ll_o, + sel => wire_n0OO0ll_sel + ); + wire_n0OO0lO_data <= ( n0Ol0OO & "0" & wire_n0OOiiO_dataout & wire_n0OOi0i_dataout); + wire_n0OO0lO_sel <= ( n0Oli1i & n0Ol0OO & n0Ol0Ol & n0Ol0Oi); + n0OO0lO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0lO_data, + o => wire_n0OO0lO_o, + sel => wire_n0OO0lO_sel + ); + wire_n0OO0Oi_data <= ( n0Oli1i & wire_w_lg_niOO0il1O3274w & wire_n0OOili_dataout & wire_n0OOi0l_dataout); + wire_n0OO0Oi_sel <= ( n0Oli1i & n0Ol0OO & n0Ol0Ol & n0Ol0Oi); + n0OO0Oi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0Oi_data, + o => wire_n0OO0Oi_o, + sel => wire_n0OO0Oi_sel + ); + wire_n0OO0Ol_data <= ( wire_n0OOlll_dataout & wire_n0OOliO_dataout & wire_n0OOi0O_dataout & n0OiOOi); + wire_n0OO0Ol_sel <= ( n0Oli1i & n0Ol0OO & n0Ol0Ol & n0Ol0Oi); + n0OO0Ol : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0Ol_data, + o => wire_n0OO0Ol_o, + sel => wire_n0OO0Ol_sel + ); + wire_n0OO0OO_data <= ( wire_n0OOllO_dataout & n0OiOOl & wire_w_lg_niOO0iiOO3252w & n1O1lli); + wire_n0OO0OO_sel <= ( n0Oli1i & n0Ol0OO & n0Ol0Ol & n0Ol0Oi); + n0OO0OO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n0OO0OO_data, + o => wire_n0OO0OO_o, + sel => wire_n0OO0OO_sel + ); + wire_n0OO1Oi_data <= ( wire_n0OOlii_dataout & "0"); + wire_n0OO1Oi_sel <= ( n0Ol0OO & wire_ni1lOlO_w_lg_n0Ol0OO3319w); + n0OO1Oi : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_n0OO1Oi_data, + o => wire_n0OO1Oi_o, + sel => wire_n0OO1Oi_sel + ); + wire_n0OO1Ol_data <= ( "0" & wire_n0OOlil_dataout & niOO0iiOO); + wire_n0OO1Ol_sel <= ( wire_ni1llii_w_lg_n0Oli1i3312w & n0Ol0OO & n0Ol0Ol); + n0OO1Ol : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n0OO1Ol_data, + o => wire_n0OO1Ol_o, + sel => wire_n0OO1Ol_sel + ); + wire_n101011i_data <= ( "0" & n11O1O0O & wire_n10l010O_dataout); + wire_n101011i_sel <= ( n11O0Oil & niOl00iii & n11O0lil); + n101011i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n101011i_data, + o => wire_n101011i_o, + sel => wire_n101011i_sel + ); + wire_n101011l_data <= ( "0" & n11O1O1O & wire_n10O1O0O_dataout & wire_n10lO1li_dataout); + wire_n101011l_sel <= ( wire_niO01iOi_w_lg_w_lg_n11O0Oil21254w21255w & niOl00iil & n11O0lOO & n11O0O1i); + n101011l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n101011l_data, + o => wire_n101011l_o, + sel => wire_n101011l_sel + ); + wire_n101100O_data <= ( n11O00ll & "0" & wire_n1i1001i_dataout); + wire_n101100O_sel <= ( niOl000ll & n11O0O0O & n11O0O0l); + n101100O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n101100O_data, + o => wire_n101100O_o, + sel => wire_n101100O_sel + ); + wire_n101101i_data <= ( n11O01lO & "0" & wire_n1i101lO_dataout & wire_n10l1l0l_dataout); + wire_n101101i_sel <= ( niOl000li & n11O0O0O & n11O0O0l & n11O0llO); + n101101i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n101101i_data, + o => wire_n101101i_o, + sel => wire_n101101i_sel + ); + wire_n101101l_data <= ( n11O01Oi & "0" & wire_n1i101Oi_dataout & wire_n10l1l0O_dataout); + wire_n101101l_sel <= ( niOl000li & n11O0O0O & n11O0O0l & n11O0llO); + n101101l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n101101l_data, + o => wire_n101101l_o, + sel => wire_n101101l_sel + ); + wire_n10110ii_data <= ( n11O010O & "0" & wire_n1i1000i_dataout); + wire_n10110ii_sel <= ( niOl000ll & n11O0O0O & n11O0O0l); + n10110ii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n10110ii_data, + o => wire_n10110ii_o, + sel => wire_n10110ii_sel + ); + wire_n10110iO_data <= ( n11O01li & k_conf(360) & wire_n1i11i0i_dataout & wire_n10lllOl_dataout & wire_n10llllO_dataout & wire_n10i0iiO_dataout); + wire_n10110iO_sel <= ( niOl000lO & wire_niO01ill_w_lg_w_lg_w_lg_n11O0O0O22889w22890w22891w & n11O0O1O & n11O0O1i & n11O0lOl & n11O0lll); + n10110iO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n10110iO_data, + o => wire_n10110iO_o, + sel => wire_n10110iO_sel + ); + wire_n10110lO_data <= ( wire_n1iii11O_dataout & wire_n1ii1l0O_dataout & wire_n1i0000O_dataout & wire_n1i11O1i_dataout & wire_n1i11i0l_dataout & wire_n10OlO1l_dataout & wire_n10Oii0i_dataout & wire_n10O1Oii_dataout & wire_n10lllOO_dataout & wire_n10lli1l_dataout & wire_n10liO0l_dataout & wire_n10l1lli_dataout & wire_n10iO1li_dataout & wire_n10i0iOl_dataout & wire_n10i1Oil_dataout & wire_n100iOil_dataout & wire_n100iiil_dataout & wire_n1000i1l_dataout & wire_n101OOil_dataout & wire_n101ll0i_dataout & wire_n1i1liii_dataout & wire_n101l0il_dataout & wire_n101iO1O_dataout & wire_n1010lOl_dataout & wire_n101010l_dataout); + wire_n10110lO_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n10110lO : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n10110lO_data, + o => wire_n10110lO_o, + sel => wire_n10110lO_sel + ); + wire_n10110Oi_data <= ( wire_n1iii10i_dataout & wire_n1ii1lii_dataout & wire_n1i000ii_dataout & wire_n1i11O1l_dataout & wire_n1i11i0O_dataout & wire_n10OlO1O_dataout & wire_n10Oii0l_dataout & wire_n10O1Oil_dataout & wire_n10llO1i_dataout & wire_n10lli1O_dataout & wire_n10liO0O_dataout & wire_n10l1lll_dataout & wire_n10iO1ll_dataout & wire_n10i0iOO_dataout & wire_n10i1OiO_dataout & wire_n100iOiO_dataout & wire_n100iiiO_dataout & wire_n1000i1O_dataout & wire_n101OOiO_dataout & wire_n101ll0l_dataout & wire_n1i1liil_dataout & wire_n101l0iO_dataout & wire_n101iO0i_dataout & wire_n1010lOO_dataout & wire_n101010O_dataout); + wire_n10110Oi_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n10110Oi : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n10110Oi_data, + o => wire_n10110Oi_o, + sel => wire_n10110Oi_sel + ); + wire_n10110Ol_data <= ( wire_n1iii10l_dataout & wire_n1ii1lil_dataout & wire_n1i000il_dataout & wire_n1i11O1O_dataout & wire_n1i11iii_dataout & wire_n10OlO0i_dataout & wire_n10Oii0O_dataout & wire_n10O1OiO_dataout & wire_n10llO1l_dataout & wire_n10lli0i_dataout & wire_n10liOii_dataout & wire_n10l1llO_dataout & wire_n10iO1lO_dataout & wire_n10i0l1i_dataout & wire_n10i1Oli_dataout & wire_n100iOli_dataout & wire_n100iili_dataout & wire_n1000i0i_dataout & wire_n101OOli_dataout & wire_n101ll0O_dataout & wire_n1i1liiO_dataout & wire_n101l0li_dataout & wire_n101iO0l_dataout & wire_n1010O1i_dataout & wire_n10101ii_dataout); + wire_n10110Ol_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n10110Ol : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n10110Ol_data, + o => wire_n10110Ol_o, + sel => wire_n10110Ol_sel + ); + wire_n10110OO_data <= ( wire_n1iii10O_dataout & wire_n1ii1liO_dataout & wire_n1i000iO_dataout & wire_n1i11O0i_dataout & wire_n1i11iil_dataout & wire_n10OlO0l_dataout & wire_n10Oiiii_dataout & wire_n10O1Oli_dataout & wire_n10llO1O_dataout & wire_n10lli0l_dataout & wire_n10liOil_dataout & wire_n10l1lOi_dataout & wire_n10iO1Oi_dataout & wire_n10i0l1l_dataout & wire_n10i1Oll_dataout & wire_n100iOll_dataout & wire_n100iill_dataout & wire_n1000i0l_dataout & wire_n101OOll_dataout & wire_n101llii_dataout & wire_n1i1lili_dataout & wire_n101l0ll_dataout & wire_n101iO0O_dataout & wire_n1010O1l_dataout & wire_n10101il_dataout); + wire_n10110OO_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n10110OO : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n10110OO_data, + o => wire_n10110OO_o, + sel => wire_n10110OO_sel + ); + wire_n101110O_data <= ( n11O0i0O & wire_n1i11i1O_dataout & wire_n10l1liO_dataout & wire_n10iO1ii_dataout & wire_n10i0ill_dataout & wire_n10i1Oii_dataout & wire_n100iOii_dataout & wire_n101iO1l_dataout); + wire_n101110O_sel <= ( niOl000ii & n11O0O1O & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0iOO); + n101110O : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_n101110O_data, + o => wire_n101110O_o, + sel => wire_n101110O_sel + ); + wire_n101111l_data <= ( n11O1O0i & wire_n10Ollli_dataout & wire_n100iO0l_dataout & wire_n1000i1i_dataout & "0"); + wire_n101111l_sel <= ( niOl0000O & n11O0O1O & n11O0liO & n11O0l0O & wire_niO01ill_w_lg_n11O0l0l23097w); + n101111l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n101111l_data, + o => wire_n101111l_o, + sel => wire_n101111l_sel + ); + wire_n10111li_data <= ( n11O01ii & wire_n1i0000i_dataout & "0"); + wire_n10111li_sel <= ( niOl000il & n11O0O0O & n11O0O0i); + n10111li : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n10111li_data, + o => wire_n10111li_o, + sel => wire_n10111li_sel + ); + wire_n10111lO_data <= ( n11O0i1i & wire_n1i0000l_dataout & wire_n1i101Ol_dataout & wire_n10OlllO_dataout & wire_n101OOii_dataout); + wire_n10111lO_sel <= ( niOl000iO & n11O0O0O & n11O0O0l & n11O0O1O & n11O0l0O); + n10111lO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n10111lO_data, + o => wire_n10111lO_o, + sel => wire_n10111lO_sel + ); + wire_n10111Ol_data <= ( n11O00lO & wire_n1i00l1l_dataout & wire_n1i001Oi_dataout); + wire_n10111Ol_sel <= ( niOl000ll & n11O0O0O & n11O0O0l); + n10111Ol : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n10111Ol_data, + o => wire_n10111Ol_o, + sel => wire_n10111Ol_sel + ); + wire_n10111OO_data <= ( n11O01ll & "0" & wire_n1i101ll_dataout & wire_n10l1l0i_dataout); + wire_n10111OO_sel <= ( niOl000li & n11O0O0O & n11O0O0l & n11O0llO); + n10111OO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n10111OO_data, + o => wire_n10111OO_o, + sel => wire_n10111OO_sel + ); + wire_n1011i0i_data <= ( wire_n1iii1li_dataout & wire_n1ii1lOi_dataout & wire_n1i000Oi_dataout & wire_n1i11Oil_dataout & wire_n1i11ilO_dataout & wire_n10OlOiO_dataout & wire_n10Oiill_dataout & wire_n10O1OOl_dataout & wire_n10llOii_dataout & wire_n10lliiO_dataout & wire_n10liOlO_dataout & wire_n10l1O1l_dataout & wire_n10iO01l_dataout & wire_n10i0l0O_dataout & wire_n10i1OOO_dataout & wire_n100iOOO_dataout & wire_n100iiOO_dataout & wire_n1000iiO_dataout & wire_n101OOOO_dataout & wire_n101llll_dataout & wire_n1i1liOl_dataout & wire_n101l0OO_dataout & wire_n101iOli_dataout & wire_n1010O0O_dataout & wire_n10101lO_dataout); + wire_n1011i0i_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011i0i : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011i0i_data, + o => wire_n1011i0i_o, + sel => wire_n1011i0i_sel + ); + wire_n1011i0l_data <= ( wire_n1iii1ll_dataout & wire_n1ii1lOl_dataout & wire_n1i000Ol_dataout & wire_n1i11OiO_dataout & wire_n1i11iOi_dataout & wire_n10OlOli_dataout & wire_n10OiilO_dataout & wire_n10O1OOO_dataout & wire_n10llOil_dataout & wire_n10llili_dataout & wire_n10liOOi_dataout & wire_n10l1O1O_dataout & wire_n10iO01O_dataout & wire_n10i0lii_dataout & wire_n10i011i_dataout & wire_n100l11i_dataout & wire_n100il1i_dataout & wire_n1000ili_dataout & wire_n100111i_dataout & wire_n101lllO_dataout & wire_n1i1liOO_dataout & wire_n101li1i_dataout & wire_n101iOll_dataout & wire_n1010Oii_dataout & wire_n10101Oi_dataout); + wire_n1011i0l_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011i0l : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011i0l_data, + o => wire_n1011i0l_o, + sel => wire_n1011i0l_sel + ); + wire_n1011i0O_data <= ( wire_n1iii1lO_dataout & wire_n1ii1lOO_dataout & wire_n1i000OO_dataout & wire_n1i11Oli_dataout & wire_n1i11iOl_dataout & wire_n10OlOll_dataout & wire_n10OiiOi_dataout & wire_n10O011i_dataout & wire_n10llOiO_dataout & wire_n10llill_dataout & wire_n10liOOl_dataout & wire_n10l1O0i_dataout & wire_n10iO00i_dataout & wire_n10i0lil_dataout & wire_n10i011l_dataout & wire_n100l11l_dataout & wire_n100il1l_dataout & wire_n1000ill_dataout & wire_n100111l_dataout & wire_n101llOi_dataout & wire_n1i1ll1i_dataout & wire_n101li1l_dataout & wire_n101iOlO_dataout & wire_n1010Oil_dataout & wire_n10101Ol_dataout); + wire_n1011i0O_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011i0O : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011i0O_data, + o => wire_n1011i0O_o, + sel => wire_n1011i0O_sel + ); + wire_n1011i1i_data <= ( wire_n1iii1ii_dataout & wire_n1ii1lli_dataout & wire_n1i000li_dataout & wire_n1i11O0l_dataout & wire_n1i11iiO_dataout & wire_n10OlO0O_dataout & wire_n10Oiiil_dataout & wire_n10O1Oll_dataout & wire_n10llO0i_dataout & wire_n10lli0O_dataout & wire_n10liOiO_dataout & wire_n10l1lOl_dataout & wire_n10iO1Ol_dataout & wire_n10i0l1O_dataout & wire_n10i1OlO_dataout & wire_n100iOlO_dataout & wire_n100iilO_dataout & wire_n1000i0O_dataout & wire_n101OOlO_dataout & wire_n101llil_dataout & wire_n1i1lill_dataout & wire_n101l0lO_dataout & wire_n101iOii_dataout & wire_n1010O1O_dataout & wire_n10101iO_dataout); + wire_n1011i1i_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011i1i : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011i1i_data, + o => wire_n1011i1i_o, + sel => wire_n1011i1i_sel + ); + wire_n1011i1l_data <= ( wire_n1iii1il_dataout & wire_n1ii1lll_dataout & wire_n1i000ll_dataout & wire_n1i11O0O_dataout & wire_n1i11ili_dataout & wire_n10OlOii_dataout & wire_n10OiiiO_dataout & wire_n10O1OlO_dataout & wire_n10llO0l_dataout & wire_n10lliii_dataout & wire_n10liOli_dataout & wire_n10l1lOO_dataout & wire_n10iO1OO_dataout & wire_n10i0l0i_dataout & wire_n10i1OOi_dataout & wire_n100iOOi_dataout & wire_n100iiOi_dataout & wire_n1000iii_dataout & wire_n101OOOi_dataout & wire_n101lliO_dataout & wire_n1i1lilO_dataout & wire_n101l0Oi_dataout & wire_n101iOil_dataout & wire_n1010O0i_dataout & wire_n10101li_dataout); + wire_n1011i1l_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011i1l : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011i1l_data, + o => wire_n1011i1l_o, + sel => wire_n1011i1l_sel + ); + wire_n1011i1O_data <= ( wire_n1iii1iO_dataout & wire_n1ii1llO_dataout & wire_n1i000lO_dataout & wire_n1i11Oii_dataout & wire_n1i11ill_dataout & wire_n10OlOil_dataout & wire_n10Oiili_dataout & wire_n10O1OOi_dataout & wire_n10llO0O_dataout & wire_n10lliil_dataout & wire_n10liOll_dataout & wire_n10l1O1i_dataout & wire_n10iO01i_dataout & wire_n10i0l0l_dataout & wire_n10i1OOl_dataout & wire_n100iOOl_dataout & wire_n100iiOl_dataout & wire_n1000iil_dataout & wire_n101OOOl_dataout & wire_n101llli_dataout & wire_n1i1liOi_dataout & wire_n101l0Ol_dataout & wire_n101iOiO_dataout & wire_n1010O0l_dataout & wire_n10101ll_dataout); + wire_n1011i1O_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011i1O : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011i1O_data, + o => wire_n1011i1O_o, + sel => wire_n1011i1O_sel + ); + wire_n1011iii_data <= ( wire_n1iii1Oi_dataout & wire_n1ii1O1i_dataout & wire_n1i00i1i_dataout & wire_n1i11Oll_dataout & wire_n1i11iOO_dataout & wire_n10OlOlO_dataout & wire_n10OiiOl_dataout & wire_n10O011l_dataout & wire_n10llOli_dataout & wire_n10llilO_dataout & wire_n10liOOO_dataout & wire_n10l1O0l_dataout & wire_n10iO00l_dataout & wire_n10i0liO_dataout & wire_n10i011O_dataout & wire_n100l11O_dataout & wire_n100il1O_dataout & wire_n1000ilO_dataout & wire_n100111O_dataout & wire_n101llOl_dataout & wire_n1i1ll1l_dataout & wire_n101li1O_dataout & wire_n101iOOi_dataout & wire_n1010OiO_dataout & wire_n10101OO_dataout); + wire_n1011iii_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011iii : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011iii_data, + o => wire_n1011iii_o, + sel => wire_n1011iii_sel + ); + wire_n1011iil_data <= ( wire_n1iii1Ol_dataout & wire_n1ii1O1l_dataout & wire_n1i00i1l_dataout & wire_n1i11OlO_dataout & wire_n1i11l1i_dataout & wire_n10OlOOi_dataout & wire_n10OiiOO_dataout & wire_n10O011O_dataout & wire_n10llOll_dataout & wire_n10lliOi_dataout & wire_n10ll11i_dataout & wire_n10l1O0O_dataout & wire_n10iO00O_dataout & wire_n10i0lli_dataout & wire_n10i010i_dataout & wire_n100l10i_dataout & wire_n100il0i_dataout & wire_n1000iOi_dataout & wire_n100110i_dataout & wire_n101llOO_dataout & wire_n1i1ll1O_dataout & wire_n101li0i_dataout & wire_n101iOOl_dataout & wire_n1010Oli_dataout & wire_n101001i_dataout); + wire_n1011iil_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011iil : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011iil_data, + o => wire_n1011iil_o, + sel => wire_n1011iil_sel + ); + wire_n1011iiO_data <= ( wire_n1iii1OO_dataout & wire_n1ii1O1O_dataout & wire_n1i00i1O_dataout & wire_n1i11OOi_dataout & wire_n1i11l1l_dataout & wire_n10OlOOl_dataout & wire_n10Oil1i_dataout & wire_n10O010i_dataout & wire_n10llOlO_dataout & wire_n10lliOl_dataout & wire_n10ll11l_dataout & wire_n10l1Oii_dataout & wire_n10iO0ii_dataout & wire_n10i0lll_dataout & wire_n10i010l_dataout & wire_n100l10l_dataout & wire_n100il0l_dataout & wire_n1000iOl_dataout & wire_n100110l_dataout & wire_n101lO1i_dataout & wire_n1i1ll0i_dataout & wire_n101li0l_dataout & wire_n101iOOO_dataout & wire_n1010Oll_dataout & wire_n101001l_dataout); + wire_n1011iiO_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011iiO : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011iiO_data, + o => wire_n1011iiO_o, + sel => wire_n1011iiO_sel + ); + wire_n1011ili_data <= ( wire_n1iii01i_dataout & wire_n1ii1O0i_dataout & wire_n1i00i0i_dataout & wire_n1i11OOl_dataout & wire_n1i11l1O_dataout & wire_n10OlOOO_dataout & wire_n10Oil1l_dataout & wire_n10O010l_dataout & wire_n10llOOi_dataout & wire_n10lliOO_dataout & wire_n10ll11O_dataout & wire_n10l1Oil_dataout & wire_n10iO0il_dataout & wire_n10i0llO_dataout & wire_n10i010O_dataout & wire_n100l10O_dataout & wire_n100il0O_dataout & wire_n1000iOO_dataout & wire_n100110O_dataout & wire_n101lO1l_dataout & wire_n1i1ll0l_dataout & wire_n101li0O_dataout & wire_n101l11i_dataout & wire_n1010OlO_dataout & wire_n101001O_dataout); + wire_n1011ili_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011ili : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011ili_data, + o => wire_n1011ili_o, + sel => wire_n1011ili_sel + ); + wire_n1011ill_data <= ( wire_n1iii01l_dataout & wire_n1ii1O0l_dataout & wire_n1i00i0l_dataout & wire_n1i11OOO_dataout & wire_n1i11l0i_dataout & wire_n10OO11i_dataout & wire_n10Oil1O_dataout & wire_n10O010O_dataout & wire_n10llOOl_dataout & wire_n10lll1i_dataout & wire_n10ll10i_dataout & wire_n10l1OiO_dataout & wire_n10iO0iO_dataout & wire_n10i0lOi_dataout & wire_n10i01ii_dataout & wire_n100l1ii_dataout & wire_n100ilii_dataout & wire_n1000l1i_dataout & wire_n10011ii_dataout & wire_n101lO1O_dataout & wire_n1i1ll0O_dataout & wire_n101liii_dataout & wire_n101l11l_dataout & wire_n1010OOi_dataout & wire_n101000i_dataout); + wire_n1011ill_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011ill : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011ill_data, + o => wire_n1011ill_o, + sel => wire_n1011ill_sel + ); + wire_n1011ilO_data <= ( wire_n1iii01O_dataout & wire_n1ii1O0O_dataout & wire_n1i00i0O_dataout & wire_n1i1011i_dataout & wire_n1i11l0l_dataout & wire_n10OO11l_dataout & wire_n10Oil0i_dataout & wire_n10O01ii_dataout & wire_n10llOOO_dataout & wire_n10lll1l_dataout & wire_n10ll10l_dataout & wire_n10l1Oli_dataout & wire_n10iO0li_dataout & wire_n10i0lOl_dataout & wire_n10i01il_dataout & wire_n100l1il_dataout & wire_n100ilil_dataout & wire_n1000l1l_dataout & wire_n10011il_dataout & wire_n101lO0i_dataout & wire_n1i1llii_dataout & wire_n101liil_dataout & wire_n101l11O_dataout & wire_n1010OOl_dataout & wire_n101000l_dataout); + wire_n1011ilO_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011ilO : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011ilO_data, + o => wire_n1011ilO_o, + sel => wire_n1011ilO_sel + ); + wire_n1011iOi_data <= ( wire_n1iii00i_dataout & wire_n1ii1Oii_dataout & wire_n1i00iii_dataout & wire_n1i1011l_dataout & wire_n1i11l0O_dataout & wire_n10OO11O_dataout & wire_n10Oil0l_dataout & wire_n10O01il_dataout & wire_n10lO11i_dataout & wire_n10lll1O_dataout & wire_n10ll10O_dataout & wire_n10l1Oll_dataout & wire_n10iO0ll_dataout & wire_n10i0lOO_dataout & wire_n10i01iO_dataout & wire_n100l1iO_dataout & wire_n100iliO_dataout & wire_n1000l1O_dataout & wire_n10011iO_dataout & wire_n101lO0l_dataout & wire_n1i1llil_dataout & wire_n101liiO_dataout & wire_n101l10i_dataout & wire_n1010OOO_dataout & wire_n101000O_dataout); + wire_n1011iOi_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011iOi : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011iOi_data, + o => wire_n1011iOi_o, + sel => wire_n1011iOi_sel + ); + wire_n1011iOl_data <= ( wire_n1iii00l_dataout & wire_n1ii1Oil_dataout & wire_n1i00iil_dataout & wire_n1i1011O_dataout & wire_n1i11lii_dataout & wire_n10OO10i_dataout & wire_n10Oil0O_dataout & wire_n10O01iO_dataout & wire_n10lO11l_dataout & wire_n10lll0i_dataout & wire_n10ll1ii_dataout & wire_n10l1OlO_dataout & wire_n10iO0lO_dataout & wire_n10i0O1i_dataout & wire_n10i01li_dataout & wire_n100l1li_dataout & wire_n100illi_dataout & wire_n1000l0i_dataout & wire_n10011li_dataout & wire_n101lO0O_dataout & wire_n1i1lliO_dataout & wire_n101lili_dataout & wire_n101l10l_dataout & wire_n101i11i_dataout & wire_n10100ii_dataout); + wire_n1011iOl_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011iOl : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011iOl_data, + o => wire_n1011iOl_o, + sel => wire_n1011iOl_sel + ); + wire_n1011iOO_data <= ( wire_n1iii00O_dataout & wire_n1ii1OiO_dataout & wire_n1i00iiO_dataout & wire_n1i1010i_dataout & wire_n1i11lil_dataout & wire_n10OO10l_dataout & wire_n10Oilii_dataout & wire_n10O01li_dataout & wire_n10lO11O_dataout & wire_n10lll0l_dataout & wire_n10ll1il_dataout & wire_n10l1OOi_dataout & wire_n10iO0Oi_dataout & wire_n10i0O1l_dataout & wire_n10i01ll_dataout & wire_n100l1ll_dataout & wire_n100illl_dataout & wire_n1000l0l_dataout & wire_n10011ll_dataout & wire_n101lOii_dataout & wire_n1i1llli_dataout & wire_n101lill_dataout & wire_n101l10O_dataout & wire_n101i11l_dataout & wire_n10100il_dataout); + wire_n1011iOO_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011iOO : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011iOO_data, + o => wire_n1011iOO_o, + sel => wire_n1011iOO_sel + ); + wire_n1011l0i_data <= ( wire_n1iii0li_dataout & wire_n1ii1OOi_dataout & wire_n1i00iOi_dataout & wire_n1i101il_dataout & wire_n1i11llO_dataout & wire_n10OO1iO_dataout & wire_n10Oilll_dataout & wire_n10O01Ol_dataout & wire_n10lO1ii_dataout & wire_n10llliO_dataout & wire_n10ll1lO_dataout & wire_n10l011l_dataout & wire_n10iOi1l_dataout & wire_n10i0O0O_dataout & wire_n10i01OO_dataout & wire_n100l1OO_dataout & wire_n100ilOO_dataout & wire_n1000liO_dataout & wire_n10011OO_dataout & wire_n101lOll_dataout & wire_n10iOiOl_dataout & wire_n101liOO_dataout & wire_n101l1li_dataout & wire_n101i10O_dataout & wire_n10100lO_dataout); + wire_n1011l0i_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011l0i : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011l0i_data, + o => wire_n1011l0i_o, + sel => wire_n1011l0i_sel + ); + wire_n1011l0l_data <= ( wire_n1iii0ll_dataout & wire_n1ii1OOl_dataout & wire_n1i00iOl_dataout & wire_n1i101iO_dataout & wire_n1i11lOi_dataout & wire_n10OO1li_dataout & wire_n10OillO_dataout & wire_n10O01OO_dataout & wire_n10lO1il_dataout & wire_n10lllli_dataout & wire_n10ll1Oi_dataout & wire_n10l011O_dataout & wire_n10iOi1O_dataout & wire_n10i0Oii_dataout & wire_n10i001i_dataout & wire_n100l01i_dataout & wire_n100iO1i_dataout & wire_n1000lli_dataout & wire_n100101i_dataout & wire_n101lOlO_dataout & wire_n1i1llOO_dataout & wire_n101ll1i_dataout & wire_n101l1ll_dataout & wire_n101i1ii_dataout & wire_n10100Oi_dataout); + wire_n1011l0l_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011l0l : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011l0l_data, + o => wire_n1011l0l_o, + sel => wire_n1011l0l_sel + ); + wire_n1011l0O_data <= ( wire_n1iii0lO_dataout & wire_n1ii1OOO_dataout & wire_n1i00iOO_dataout & wire_n1i101li_dataout & wire_n1i11lOl_dataout & wire_n10OO1ll_dataout & wire_n10OilOi_dataout & wire_n10O001i_dataout & wire_n10lO1iO_dataout & wire_n10lllll_dataout & wire_n10ll1Ol_dataout & wire_n10l010i_dataout & wire_n10iOi0i_dataout & wire_n10i0Oil_dataout & wire_n10i001l_dataout & wire_n100l01l_dataout & wire_n100iO1l_dataout & wire_n1000lll_dataout & wire_n100101l_dataout & wire_n101lOOi_dataout & wire_n101ll1O_dataout & wire_n101ll1l_dataout & wire_n101l1lO_dataout & wire_n101i1il_dataout & wire_n10100Ol_dataout); + wire_n1011l0O_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011l0O : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011l0O_data, + o => wire_n1011l0O_o, + sel => wire_n1011l0O_sel + ); + wire_n1011l1i_data <= ( wire_n1iii0ii_dataout & wire_n1ii1Oli_dataout & wire_n1i00ili_dataout & wire_n1i1010l_dataout & wire_n1i11liO_dataout & wire_n10OO10O_dataout & wire_n10Oilil_dataout & wire_n10O01ll_dataout & wire_n10lO10i_dataout & wire_n10lll0O_dataout & wire_n10ll1iO_dataout & wire_n10l1OOl_dataout & wire_n10iO0Ol_dataout & wire_n10i0O1O_dataout & wire_n10i01lO_dataout & wire_n100l1lO_dataout & wire_n100illO_dataout & wire_n1000l0O_dataout & wire_n10011lO_dataout & wire_n101lOil_dataout & wire_n1i1llll_dataout & wire_n101lilO_dataout & wire_n101l1ii_dataout & wire_n101i11O_dataout & wire_n10100iO_dataout); + wire_n1011l1i_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011l1i : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011l1i_data, + o => wire_n1011l1i_o, + sel => wire_n1011l1i_sel + ); + wire_n1011l1l_data <= ( wire_n1iii0il_dataout & wire_n1ii1Oll_dataout & wire_n1i00ill_dataout & wire_n1i1010O_dataout & wire_n1i11lli_dataout & wire_n10OO1ii_dataout & wire_n10OiliO_dataout & wire_n10O01lO_dataout & wire_n10lO10l_dataout & wire_n10lllii_dataout & wire_n10ll1li_dataout & wire_n10l1OOO_dataout & wire_n10iO0OO_dataout & wire_n10i0O0i_dataout & wire_n10i01Oi_dataout & wire_n100l1Oi_dataout & wire_n100ilOi_dataout & wire_n1000lii_dataout & wire_n10011Oi_dataout & wire_n101lOiO_dataout & wire_n1i1lllO_dataout & wire_n101liOi_dataout & wire_n101l1il_dataout & wire_n101i10i_dataout & wire_n10100li_dataout); + wire_n1011l1l_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011l1l : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011l1l_data, + o => wire_n1011l1l_o, + sel => wire_n1011l1l_sel + ); + wire_n1011l1O_data <= ( wire_n1iii0iO_dataout & wire_n1ii1OlO_dataout & wire_n1i00ilO_dataout & wire_n1i101ii_dataout & wire_n1i11lll_dataout & wire_n10OO1il_dataout & wire_n10Oilli_dataout & wire_n10O01Oi_dataout & wire_n10lO10O_dataout & wire_n10lllil_dataout & wire_n10ll1ll_dataout & wire_n10l011i_dataout & wire_n10iOi1i_dataout & wire_n10i0O0l_dataout & wire_n10i01Ol_dataout & wire_n100l1Ol_dataout & wire_n100ilOl_dataout & wire_n1000lil_dataout & wire_n10011Ol_dataout & wire_n101lOli_dataout & wire_n1i1llOi_dataout & wire_n101liOl_dataout & wire_n101l1iO_dataout & wire_n101i10l_dataout & wire_n10100ll_dataout); + wire_n1011l1O_sel <= ( n11O0Oil & n11O0Oii & n11O0O0O & n11O0O0l & n11O0O0i & n11O0O1O & n11O0O1l & n11O0lOO & n11O0O1i & n11O0lOl & n11O0lOi & n11O0lil & n11O0llO & n11O0lll & n11O0lli & n11O0liO & n11O0l1O & n11O0lii & n11O0l0O & n11O0l0l & n11O0l0i & n11O0l1i & n11O0iOO & n11O0iOl & n11O0l1l); + n1011l1O : oper_selector + GENERIC MAP ( + width_data => 25, + width_sel => 25 + ) + PORT MAP ( + data => wire_n1011l1O_data, + o => wire_n1011l1O_o, + sel => wire_n1011l1O_sel + ); + wire_n1011lii_data <= ( wire_nlOll1OOO_dataout & n11O0i0i & wire_n1i00l1i_dataout & wire_n10OllOi_dataout & wire_n10iOi0l_dataout & wire_nlOll010i_dataout); + wire_n1011lii_sel <= ( n11O0Oil & niOl000Oi & n11O0O0O & n11O0O1O & n11O0llO & n11O0lll); + n1011lii : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n1011lii_data, + o => wire_n1011lii_o, + sel => wire_n1011lii_sel + ); + wire_n1011liO_data <= ( "1" & n11O0i1l & wire_n10OllOO_dataout); + wire_n1011liO_sel <= ( n11O0Oil & niOl000Ol & n11O0O1O); + n1011liO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011liO_data, + o => wire_n1011liO_o, + sel => wire_n1011liO_sel + ); + wire_n1011lli_data <= ( "0" & n11O0i1O & wire_n10OlO1i_dataout); + wire_n1011lli_sel <= ( n11O0Oil & niOl000Ol & n11O0O1O); + n1011lli : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011lli_data, + o => wire_n1011lli_o, + sel => wire_n1011lli_sel + ); + wire_n1011llO_data <= ( wire_n1iiii1l_dataout & n11O0i0l & wire_n10liO0i_dataout & wire_n10liO1i_dataout & wire_n100iO1O_dataout); + wire_n1011llO_sel <= ( n11O0Oil & niOl000OO & n11O0lOi & n11O0lil & n11O0liO); + n1011llO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1011llO_data, + o => wire_n1011llO_o, + sel => wire_n1011llO_sel + ); + wire_n1011lOl_data <= ( "0" & n11O0iOi & wire_n10lilOO_dataout & wire_n10iO10l_dataout & wire_n10i0ilO_dataout & wire_n101l00i_dataout); + wire_n1011lOl_sel <= ( wire_niO01iOi_w_lg_n11O0Oil21467w & niOl00i1i & n11O0lil & n11O0llO & n11O0lll & n11O0iOO); + n1011lOl : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n1011lOl_data, + o => wire_n1011lOl_o, + sel => wire_n1011lOl_sel + ); + wire_n1011O0i_data <= ( "0" & n11O010i & wire_n1i0001i_dataout); + wire_n1011O0i_sel <= ( n11O0Oil & niOl00i1l & n11O0O0O); + n1011O0i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011O0i_data, + o => wire_n1011O0i_o, + sel => wire_n1011O0i_sel + ); + wire_n1011O0l_data <= ( "1" & n11O010l & wire_n1i0001l_dataout); + wire_n1011O0l_sel <= ( n11O0Oil & niOl00i1l & n11O0O0O); + n1011O0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011O0l_data, + o => wire_n1011O0l_o, + sel => wire_n1011O0l_sel + ); + wire_n1011O1l_data <= ( "0" & n11O011l & wire_n1i001Ol_dataout); + wire_n1011O1l_sel <= ( n11O0Oil & niOl00i1l & n11O0O0O); + n1011O1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011O1l_data, + o => wire_n1011O1l_o, + sel => wire_n1011O1l_sel + ); + wire_n1011O1O_data <= ( "0" & n11O011O & wire_n1i001OO_dataout); + wire_n1011O1O_sel <= ( n11O0Oil & niOl00i1l & n11O0O0O); + n1011O1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011O1O_data, + o => wire_n1011O1O_o, + sel => wire_n1011O1O_sel + ); + wire_n1011Oii_data <= ( "0" & n11O1Oil & wire_n1i1001O_dataout); + wire_n1011Oii_sel <= ( niOl00i1O & niOl00i0i & n11O0O0l); + n1011Oii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011Oii_data, + o => wire_n1011Oii_o, + sel => wire_n1011Oii_sel + ); + wire_n1011OiO_data <= ( "0" & n11O1Oii & wire_n1i1001l_dataout); + wire_n1011OiO_sel <= ( niOl00i1O & niOl00i0i & n11O0O0l); + n1011OiO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011OiO_data, + o => wire_n1011OiO_o, + sel => wire_n1011OiO_sel + ); + wire_n1011Oli_data <= ( "0" & n11O00ii & wire_n10O1O1l_dataout & wire_n10l010l_dataout & wire_n10i000l_dataout); + wire_n1011Oli_sel <= ( n11O0Oil & niOl00i0l & n11O0O1i & n11O0lil & n11O0lli); + n1011Oli : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1011Oli_data, + o => wire_n1011Oli_o, + sel => wire_n1011Oli_sel + ); + wire_n1011OlO_data <= ( "0" & n11O00il & wire_n10O1O1i_dataout & wire_n10ll1OO_dataout & wire_n10l010O_dataout & wire_n10i000i_dataout & wire_n100iO0i_dataout); + wire_n1011OlO_sel <= ( n11O0Oil & niOl00i0O & n11O0O1i & n11O0lOi & n11O0lil & n11O0lli & n11O0liO); + n1011OlO : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_n1011OlO_data, + o => wire_n1011OlO_o, + sel => wire_n1011OlO_sel + ); + wire_n1011OOl_data <= ( "0" & n11O1O0l & wire_n10l010l_dataout); + wire_n1011OOl_sel <= ( n11O0Oil & niOl00iii & n11O0lil); + n1011OOl : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1011OOl_data, + o => wire_n1011OOl_o, + sel => wire_n1011OOl_sel + ); + wire_n11OOO0l_data <= ( n11O00iO & wire_n10iO10O_dataout & wire_n10i0ili_dataout & wire_n100iO0O_dataout); + wire_n11OOO0l_sel <= ( niOl0001i & n11O0llO & n11O0lll & n11O0liO); + n11OOO0l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n11OOO0l_data, + o => wire_n11OOO0l_o, + sel => wire_n11OOO0l_sel + ); + wire_n11OOOii_data <= ( n11O0iii & wire_n10iO1il_dataout & wire_n10ii11l_dataout); + wire_n11OOOii_sel <= ( niOl0001l & n11O0llO & n11O0lll); + n11OOOii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11OOOii_data, + o => wire_n11OOOii_o, + sel => wire_n11OOOii_sel + ); + wire_n11OOOil_data <= ( n11O0iil & wire_n10iO1iO_dataout & wire_n10ii11O_dataout); + wire_n11OOOil_sel <= ( niOl0001l & n11O0llO & n11O0lll); + n11OOOil : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11OOOil_data, + o => wire_n11OOOil_o, + sel => wire_n11OOOil_sel + ); + wire_n11OOOli_data <= ( n11O0iiO & wire_n10l1lii_dataout & wire_n101l1Oi_dataout); + wire_n11OOOli_sel <= ( niOl0001O & n11O0lil & n11O0iOO); + n11OOOli : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11OOOli_data, + o => wire_n11OOOli_o, + sel => wire_n11OOOli_sel + ); + wire_n11OOOll_data <= ( n11O0ili & wire_n10l1lil_dataout & wire_n101l1Ol_dataout); + wire_n11OOOll_sel <= ( niOl0001O & n11O0lil & n11O0iOO); + n11OOOll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n11OOOll_data, + o => wire_n11OOOll_o, + sel => wire_n11OOOll_sel + ); + wire_n11OOOOi_data <= ( n11O0ill & wire_n10l01ii_dataout & wire_n10ii10i_dataout & wire_n10i1O0O_dataout & wire_n101l1OO_dataout & wire_n10100OO_dataout); + wire_n11OOOOi_sel <= ( niOl0000i & n11O0lil & n11O0lll & n11O0lli & n11O0iOO & n11O0l1l); + n11OOOOi : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n11OOOOi_data, + o => wire_n11OOOOi_o, + sel => wire_n11OOOOi_sel + ); + wire_n11OOOOO_data <= ( n11O0ilO & "0" & wire_n10ll01i_dataout & wire_n10l01il_dataout & wire_n10i0iOi_dataout & wire_n10i001O_dataout & wire_n101l01O_dataout); + wire_n11OOOOO_sel <= ( niOl0000l & n11O0lOl & n11O0lOi & n11O0lil & n11O0lll & n11O0lli & n11O0iOO); + n11OOOOO : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_n11OOOOO_data, + o => wire_n11OOOOO_o, + sel => wire_n11OOOOO_sel + ); + wire_n1l0Oli_data <= ( wire_n1lil1l_dataout & "1" & n1l010l); + wire_n1l0Oli_sel <= ( n1l011O & n1l011l & wire_nl1000i_w_lg_n1l011i4156w); + n1l0Oli : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1l0Oli_data, + o => wire_n1l0Oli_o, + sel => wire_n1l0Oli_sel + ); + wire_n1l0OOi_data <= ( wire_n1lil0i_dataout & wire_n1li0ii_dataout & wire_n1li1Ol_dataout & "0"); + wire_n1l0OOi_sel <= ( n1l011O & n1l011l & n1l011i & nlOiliii); + n1l0OOi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1l0OOi_data, + o => wire_n1l0OOi_o, + sel => wire_n1l0OOi_sel + ); + wire_n1l0OOl_data <= ( wire_n1lil0l_dataout & wire_n1li0il_dataout & wire_n1li1OO_dataout & wire_n1liOli_w_lg_dataout4044w); + wire_n1l0OOl_sel <= ( n1l011O & n1l011l & n1l011i & nlOiliii); + n1l0OOl : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1l0OOl_data, + o => wire_n1l0OOl_o, + sel => wire_n1l0OOl_sel + ); + wire_n1l0OOO_data <= ( wire_n1lil0O_dataout & wire_n1li0iO_dataout & wire_n1li01i_dataout & "0"); + wire_n1l0OOO_sel <= ( n1l011O & n1l011l & n1l011i & nlOiliii); + n1l0OOO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1l0OOO_data, + o => wire_n1l0OOO_o, + sel => wire_n1l0OOO_sel + ); + wire_n1li11i_data <= ( wire_n1lilii_dataout & wire_n1li0li_dataout & wire_n1li01l_dataout & wire_n1liOli_dataout); + wire_n1li11i_sel <= ( n1l011O & n1l011l & n1l011i & nlOiliii); + n1li11i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_n1li11i_data, + o => wire_n1li11i_o, + sel => wire_n1li11i_sel + ); + wire_n1liO0il_data <= ( n1lillil & "0" & wire_n1ll00li_dataout & wire_n1ll1O1l_dataout & wire_n1ll1iOl_dataout & wire_n1ll11lO_dataout & wire_n1ll11lO_dataout & wire_n1ll11lO_dataout & wire_n1ll11lO_dataout & wire_n1ll11lO_dataout); + wire_n1liO0il_sel <= ( wire_w_lg_w_lg_w_lg_niOli0iil18989w19425w19426w & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO); + n1liO0il : oper_selector + GENERIC MAP ( + width_data => 10, + width_sel => 10 + ) + PORT MAP ( + data => wire_n1liO0il_data, + o => wire_n1liO0il_o, + sel => wire_n1liO0il_sel + ); + wire_n1liO0ll_data <= ( wire_n1ll0lli_dataout & n1lill1i & wire_n1ll10Oi_dataout); + wire_n1liO0ll_sel <= ( n1lilO0l & niOli0i0i & n1lilO1O); + n1liO0ll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1liO0ll_data, + o => wire_n1liO0ll_o, + sel => wire_n1liO0ll_sel + ); + wire_n1liO0lO_data <= ( wire_n1ll0lll_dataout & n1lill1l & wire_n1ll10Ol_dataout); + wire_n1liO0lO_sel <= ( n1lilO0l & niOli0i0i & n1lilO1O); + n1liO0lO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1liO0lO_data, + o => wire_n1liO0lO_o, + sel => wire_n1liO0lO_sel + ); + wire_n1liOiil_data <= ( wire_n1ll0O0O_dataout & n1lillii & wire_n1ll00iO_dataout); + wire_n1liOiil_sel <= ( n1lilO0l & niOli0i0l & n1lillOi); + n1liOiil : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_n1liOiil_data, + o => wire_n1liOiil_o, + sel => wire_n1liOiil_sel + ); + wire_n1liOili_data <= ( wire_n1ll0Oii_dataout & wire_n1ll0ill_dataout & "0" & wire_n1ll01li_dataout & wire_n1ll1O1O_dataout & wire_n1ll10OO_dataout & wire_n1liOOOi_dataout & wire_n1liOOOi_dataout & wire_n1liOOOi_dataout & wire_n1liOOOi_dataout & wire_n1liOOOi_dataout & wire_n1liOlOl_dataout); + wire_n1liOili_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOili : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOili_data, + o => wire_n1liOili_o, + sel => wire_n1liOili_sel + ); + wire_n1liOill_data <= ( wire_n1ll0Oil_dataout & wire_n1ll0ilO_dataout & "0" & wire_n1ll01ll_dataout & wire_n1ll1O0i_dataout & wire_n1ll1i1i_dataout & wire_n1liOOOl_dataout & wire_n1liOOOl_dataout & wire_n1liOOOl_dataout & wire_n1liOOOl_dataout & wire_n1liOOOl_dataout & wire_n1liOlOO_dataout); + wire_n1liOill_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOill : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOill_data, + o => wire_n1liOill_o, + sel => wire_n1liOill_sel + ); + wire_n1liOilO_data <= ( wire_n1ll0OiO_dataout & wire_n1ll0iOi_dataout & "0" & wire_n1ll01lO_dataout & wire_n1ll1O0l_dataout & wire_n1ll1i1l_dataout & wire_n1liOOOO_dataout & wire_n1liOOOO_dataout & wire_n1liOOOO_dataout & wire_n1liOOOO_dataout & wire_n1liOOOO_dataout & wire_n1liOO1i_dataout); + wire_n1liOilO_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOilO : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOilO_data, + o => wire_n1liOilO_o, + sel => wire_n1liOilO_sel + ); + wire_n1liOiOi_data <= ( wire_n1ll0Oli_dataout & wire_n1ll0iOl_dataout & "0" & wire_n1ll01Oi_dataout & wire_n1ll1O0O_dataout & wire_n1ll1i1O_dataout & wire_n1ll111i_dataout & wire_n1ll111i_dataout & wire_n1ll111i_dataout & wire_n1ll111i_dataout & wire_n1ll111i_dataout & wire_n1liOO1l_dataout); + wire_n1liOiOi_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOiOi : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOiOi_data, + o => wire_n1liOiOi_o, + sel => wire_n1liOiOi_sel + ); + wire_n1liOiOl_data <= ( wire_n1ll0Oll_dataout & wire_n1ll0iOO_dataout & "0" & wire_n1ll01Ol_dataout & wire_n1ll1Oii_dataout & wire_n1ll1i0i_dataout & wire_n1ll111l_dataout & wire_n1ll111l_dataout & wire_n1ll111l_dataout & wire_n1ll111l_dataout & wire_n1ll111l_dataout & wire_n1liOO1O_dataout); + wire_n1liOiOl_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOiOl : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOiOl_data, + o => wire_n1liOiOl_o, + sel => wire_n1liOiOl_sel + ); + wire_n1liOiOO_data <= ( "0" & wire_n1ll0l1i_dataout & "1" & wire_n1ll01OO_dataout & wire_n1ll1Oil_dataout & wire_n1ll1i0l_dataout & wire_n1ll111O_dataout & wire_n1ll111O_dataout & wire_n1ll111O_dataout & wire_n1ll111O_dataout & wire_n1ll111O_dataout & wire_n1liOO0i_dataout); + wire_n1liOiOO_sel <= ( wire_niO01ill_w_lg_n1lilO0l18986w & n1lilO0i & wire_niO01ill_w_lg_n1lillOO19215w & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOiOO : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOiOO_data, + o => wire_n1liOiOO_o, + sel => wire_n1liOiOO_sel + ); + wire_n1liOl0i_data <= ( wire_n1ll0OOi_dataout & wire_n1ll0l1O_dataout & "0" & wire_n1ll001l_dataout & wire_n1ll1Oli_dataout & wire_n1ll1iii_dataout & wire_n1ll110l_dataout & wire_n1ll110l_dataout & wire_n1ll110l_dataout & wire_n1ll110l_dataout & wire_n1ll110l_dataout & wire_n1liOO0O_dataout); + wire_n1liOl0i_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOl0i : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOl0i_data, + o => wire_n1liOl0i_o, + sel => wire_n1liOl0i_sel + ); + wire_n1liOl0l_data <= ( "0" & wire_n1ll0l0i_dataout & wire_n1ll001O_dataout & wire_n1ll1Oll_dataout & wire_n1ll1iil_dataout & wire_n1ll110O_dataout & wire_n1ll110O_dataout & wire_n1ll110O_dataout & wire_n1ll110O_dataout & wire_n1ll110O_dataout & wire_n1liOOii_dataout); + wire_n1liOl0l_sel <= ( niOli0iii & n1lilO0i & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOl0l : oper_selector + GENERIC MAP ( + width_data => 11, + width_sel => 11 + ) + PORT MAP ( + data => wire_n1liOl0l_data, + o => wire_n1liOl0l_o, + sel => wire_n1liOl0l_sel + ); + wire_n1liOl0O_data <= ( wire_n1ll0OOl_dataout & wire_n1ll0l0l_dataout & "0" & wire_n1ll000i_dataout & wire_n1ll1OlO_dataout & wire_n1ll1iiO_dataout & wire_n1ll11ii_dataout & wire_n1ll11ii_dataout & wire_n1ll11ii_dataout & wire_n1ll11ii_dataout & wire_n1ll11ii_dataout & wire_n1liOOil_dataout); + wire_n1liOl0O_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOl0O : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOl0O_data, + o => wire_n1liOl0O_o, + sel => wire_n1liOl0O_sel + ); + wire_n1liOl1O_data <= ( wire_n1ll0OlO_dataout & wire_n1ll0l1l_dataout & "0" & wire_n1ll001i_dataout & wire_n1ll1OiO_dataout & wire_n1ll1i0O_dataout & wire_n1ll110i_dataout & wire_n1ll110i_dataout & wire_n1ll110i_dataout & wire_n1ll110i_dataout & wire_n1ll110i_dataout & wire_n1liOO0l_dataout); + wire_n1liOl1O_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOl1O : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOl1O_data, + o => wire_n1liOl1O_o, + sel => wire_n1liOl1O_sel + ); + wire_n1liOlii_data <= ( wire_n1ll0OOO_dataout & wire_n1ll0l0O_dataout & "0" & wire_n1ll000l_dataout & wire_n1ll1OOi_dataout & wire_n1ll1ili_dataout & wire_n1ll11il_dataout & wire_n1ll11il_dataout & wire_n1ll11il_dataout & wire_n1ll11il_dataout & wire_n1ll11il_dataout & wire_n1liOOiO_dataout); + wire_n1liOlii_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOlii : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOlii_data, + o => wire_n1liOlii_o, + sel => wire_n1liOlii_sel + ); + wire_n1liOlil_data <= ( wire_n1lli11i_dataout & wire_n1ll0lii_dataout & "0" & wire_n1ll000O_dataout & wire_n1ll1OOl_dataout & wire_n1ll1ill_dataout & wire_n1ll11iO_dataout & wire_n1ll11iO_dataout & wire_n1ll11iO_dataout & wire_n1ll11iO_dataout & wire_n1ll11iO_dataout & wire_n1liOOli_dataout); + wire_n1liOlil_sel <= ( n1lilO0l & n1lilO0i & niOli0i0O & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOlil : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOlil_data, + o => wire_n1liOlil_o, + sel => wire_n1liOlil_sel + ); + wire_n1liOliO_data <= ( "0" & wire_n1ll0lil_dataout & wire_n1ll00ii_dataout & wire_n1ll1OOO_dataout & "1" & wire_n1ll1ilO_dataout & wire_n1ll11li_dataout & wire_n1ll11li_dataout & wire_n1ll11li_dataout & wire_n1ll11li_dataout & wire_n1ll11li_dataout & wire_n1liOOll_dataout); + wire_n1liOliO_sel <= ( wire_niO01ill_w_lg_w_lg_n1lilO0l19027w19028w & n1lilO0i & n1lillOi & n1lilO1l & n1lilO1i & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOliO : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_n1liOliO_data, + o => wire_n1liOliO_o, + sel => wire_n1liOliO_sel + ); + wire_n1liOlll_data <= ( "0" & wire_n1ll0liO_dataout & wire_n1ll00il_dataout & wire_n1ll011i_dataout & wire_n1ll1iOi_dataout & wire_n1ll11ll_dataout & wire_n1ll11ll_dataout & wire_n1ll11ll_dataout & wire_n1ll11ll_dataout & wire_n1ll11ll_dataout & wire_n1liOOlO_dataout); + wire_n1liOlll_sel <= ( niOli0iii & n1lilO0i & n1lillOi & n1lilO1l & n1lilO1O & n1lilllO & n1lillll & n1lilOil & n1lillli & n1lilliO & wire_w_lg_niOli0iil18989w); + n1liOlll : oper_selector + GENERIC MAP ( + width_data => 11, + width_sel => 11 + ) + PORT MAP ( + data => wire_n1liOlll_data, + o => wire_n1liOlll_o, + sel => wire_n1liOlll_sel + ); + wire_n1lOiO0O_data <= ( wire_n1lOlOiO_dataout & wire_n1lOlill_dataout & wire_n1lOl0ii_dataout & "0" & n1110O0O & wire_n1lOl10i_dataout); + wire_n1lOiO0O_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & wire_niO01ill_w_lg_w_lg_n1lOi01O18792w18888w & n1lOi01i & n1lOi00i); + n1lOiO0O : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n1lOiO0O_data, + o => wire_n1lOiO0O_o, + sel => wire_n1lOiO0O_sel + ); + wire_n1lOiOil_data <= ( wire_n1lOlOli_dataout & wire_n1lOlilO_dataout & wire_n1lOl0il_dataout & "0" & n1110O0O & wire_n1lOl10l_dataout); + wire_n1lOiOil_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & wire_niO01ill_w_lg_w_lg_n1lOi01O18871w18872w & n1lOi01l & n1lOi00i); + n1lOiOil : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n1lOiOil_data, + o => wire_n1lOiOil_o, + sel => wire_n1lOiOil_sel + ); + wire_n1lOiOli_data <= ( wire_n1lOlOll_dataout & wire_n1lOliOi_dataout & wire_n1lOl0iO_dataout & n1110O0O & "0" & wire_n1lOl10O_dataout); + wire_n1lOiOli_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & n1lOi01O & wire_niO01ill_w_lg_w_lg_n1lOi01l18853w18854w & n1lOi00i); + n1lOiOli : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n1lOiOli_data, + o => wire_n1lOiOli_o, + sel => wire_n1lOiOli_sel + ); + wire_n1lOiOlO_data <= ( wire_n1lOlOlO_dataout & wire_n1lOliOl_dataout & wire_n1lOl0li_dataout & "0" & wire_n1lOl00l_dataout & wire_n1lOl1ii_dataout); + wire_n1lOiOlO_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & niOli0OiO & n1lOi1OO & n1lOi00i); + n1lOiOlO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n1lOiOlO_data, + o => wire_n1lOiOlO_o, + sel => wire_n1lOiOlO_sel + ); + wire_n1lOiOOi_data <= ( wire_n1lOlOOi_dataout & wire_n1lOliOO_dataout & wire_n1lOl0ll_dataout & "0" & wire_n1lOl1il_dataout); + wire_n1lOiOOi_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & niOli0Oil & n1lOi00i); + n1lOiOOi : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1lOiOOi_data, + o => wire_n1lOiOOi_o, + sel => wire_n1lOiOOi_sel + ); + wire_n1lOiOOl_data <= ( wire_n1lOlOOl_dataout & wire_n1lOll1i_dataout & wire_n1lOl0lO_dataout & "0" & wire_n1lOl1iO_dataout); + wire_n1lOiOOl_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & niOli0Oil & n1lOi00i); + n1lOiOOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_n1lOiOOl_data, + o => wire_n1lOiOOl_o, + sel => wire_n1lOiOOl_sel + ); + wire_n1lOl11i_data <= ( wire_n1lOlOOO_dataout & wire_n1lOll1l_dataout & wire_n1lOl0Oi_dataout & "0" & wire_n1lOl00O_dataout & wire_n1lOl1li_dataout); + wire_n1lOl11i_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & niOli0OiO & n1lOi1OO & n1lOi00i); + n1lOl11i : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_n1lOl11i_data, + o => wire_n1lOl11i_o, + sel => wire_n1lOl11i_sel + ); + wire_n1lOl11O_data <= ( wire_n1lOO11i_dataout & wire_n1lOll1O_dataout & wire_n1lOl0Ol_dataout & wire_niO01ill_w_lg_n1110O0O18762w & wire_niO01ill_w_lg_n1110O0O18762w & wire_niO01ill_w_lg_n1110O0O18762w & wire_niO01ill_w_lg_n1110O0O18762w & wire_n1lOl1ll_dataout); + wire_n1lOl11O_sel <= ( n1lOi0ii & n1lOi00O & n1lOi00l & n1lOi01O & n1lOi01l & n1lOi01i & n1lOi1OO & n1lOi00i); + n1lOl11O : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_n1lOl11O_data, + o => wire_n1lOl11O_o, + sel => wire_n1lOl11O_sel + ); + wire_ni1O0iO_data <= ( wire_ni0111i_dataout & "1" & ni1llli); + wire_ni1O0iO_sel <= ( ni1llil & ni1ll0O & wire_ni1lOlO_w_lg_ni1ll0l2534w); + ni1O0iO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_ni1O0iO_data, + o => wire_ni1O0iO_o, + sel => wire_ni1O0iO_sel + ); + wire_ni1O0lO_data <= ( wire_ni0111O_dataout & wire_ni1Ol0O_dataout & wire_ni1OiOi_dataout & "0"); + wire_ni1O0lO_sel <= ( ni1llil & ni1ll0O & ni1ll0l & ni1l11l); + ni1O0lO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1O0lO_data, + o => wire_ni1O0lO_o, + sel => wire_ni1O0lO_sel + ); + wire_ni1O0Oi_data <= ( wire_ni0110i_dataout & wire_ni1Olii_dataout & wire_ni1OiOl_dataout & wire_ni010ii_w_lg_dataout2517w); + wire_ni1O0Oi_sel <= ( ni1llil & ni1ll0O & ni1ll0l & ni1l11l); + ni1O0Oi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1O0Oi_data, + o => wire_ni1O0Oi_o, + sel => wire_ni1O0Oi_sel + ); + wire_ni1O0Ol_data <= ( wire_ni0110l_dataout & wire_ni1Olil_dataout & wire_ni1OiOO_dataout & "0"); + wire_ni1O0Ol_sel <= ( ni1llil & ni1ll0O & ni1ll0l & ni1l11l); + ni1O0Ol : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1O0Ol_data, + o => wire_ni1O0Ol_o, + sel => wire_ni1O0Ol_sel + ); + wire_ni1O0OO_data <= ( wire_ni0110O_dataout & wire_ni1OliO_dataout & wire_ni1Ol1i_dataout & wire_ni010ii_dataout); + wire_ni1O0OO_sel <= ( ni1llil & ni1ll0O & ni1ll0l & ni1l11l); + ni1O0OO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_ni1O0OO_data, + o => wire_ni1O0OO_o, + sel => wire_ni1O0OO_sel + ); + wire_nl1011ilO_data <= ( wire_nl1010ilO_dataout & nl11OO0il & "0"); + wire_nl1011ilO_sel <= ( nl11OOi1O & niOi10i1O & niOi10i0l); + nl1011ilO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1011ilO_data, + o => wire_nl1011ilO_o, + sel => wire_nl1011ilO_sel + ); + wire_nl1011iOl_data <= ( wire_nl1010iOi_dataout & wire_nl101i1ii_dataout & wire_nl101i1ii_dataout & wire_w_lg_niOi10iOi60173w & wire_w_lg_niOi10iOi60173w & wire_w_lg_niOi10iOi60173w & wire_w_lg_niOi10iil60170w & wire_w_lg_niOi10iil60170w & wire_nl1011lOO_dataout); + wire_nl1011iOl_sel <= ( nl11OOi1O & nl11OO0ll & nl11OO0li & nl11OOi1l & nl11OOi1i & nl11OO0OO & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011iOl : oper_selector + GENERIC MAP ( + width_data => 9, + width_sel => 9 + ) + PORT MAP ( + data => wire_nl1011iOl_data, + o => wire_nl1011iOl_o, + sel => wire_nl1011iOl_sel + ); + wire_nl1011iOO_data <= ( wire_nl1010iOl_dataout & niOi10l0i & wire_nl1010i1l_dataout & nl11OO0iO); + wire_nl1011iOO_sel <= ( nl11OOi1O & nl11OO0ll & nl11OO0li & niOi10i0i); + nl1011iOO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1011iOO_data, + o => wire_nl1011iOO_o, + sel => wire_nl1011iOO_sel + ); + wire_nl1011l0i_data <= ( wire_nl1010l1i_dataout & "0" & wire_nl1010i0i_dataout & wire_nl1011Oii_dataout & wire_nl1011Oii_dataout & wire_nl1010i0i_dataout); + wire_nl1011l0i_sel <= ( nl11OOi1O & niOi10iii & nl11OO0li & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011l0i : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl1011l0i_data, + o => wire_nl1011l0i_o, + sel => wire_nl1011l0i_sel + ); + wire_nl1011l0l_data <= ( wire_nl1010l1l_dataout & "0" & wire_nl1010i0l_dataout & wire_nl101001O_dataout & wire_nl10101li_dataout & wire_nl1011Oil_dataout & wire_nl1011O1i_dataout & wire_nl1010i0l_dataout); + wire_nl1011l0l_sel <= ( nl11OOi1O & niOi10i0O & nl11OO0li & nl11OOi1l & nl11OO0OO & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011l0l : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1011l0l_data, + o => wire_nl1011l0l_o, + sel => wire_nl1011l0l_sel + ); + wire_nl1011l0O_data <= ( wire_nl1010l1O_dataout & "0" & wire_nl1010i0O_dataout & wire_nl101000i_dataout & wire_nl10101ll_dataout & wire_nl1011OiO_dataout & wire_nl1011OiO_dataout & wire_nl1010i0O_dataout); + wire_nl1011l0O_sel <= ( nl11OOi1O & niOi10i0O & nl11OO0li & nl11OOi1l & nl11OO0OO & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011l0O : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1011l0O_data, + o => wire_nl1011l0O_o, + sel => wire_nl1011l0O_sel + ); + wire_nl1011l1l_data <= ( wire_nl1010iOO_dataout & niOi10l0i & wire_nl1010i1O_dataout & "0" & wire_nl1011O0O_dataout & wire_nl1011O0O_dataout & wire_nl1010i1O_dataout); + wire_nl1011l1l_sel <= ( nl11OOi1O & nl11OO0ll & nl11OO0li & niOi10i0l & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011l1l : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nl1011l1l_data, + o => wire_nl1011l1l_o, + sel => wire_nl1011l1l_sel + ); + wire_nl1011lil_data <= ( wire_nl1010l0i_dataout & "0" & wire_nl1010iii_dataout & wire_nl101000l_dataout & wire_nl10101OO_dataout & wire_nl1011Oli_dataout & wire_nl1011Oli_dataout & wire_nl1010iii_dataout); + wire_nl1011lil_sel <= ( nl11OOi1O & wire_nlill0Oll_w_lg_nl11OO0OO60061w & nl11OO0li & nl11OOi1l & nl11OOi1i & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011lil : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1011lil_data, + o => wire_nl1011lil_o, + sel => wire_nl1011lil_sel + ); + wire_nl1011lli_data <= ( wire_nl1010l0l_dataout & "0" & wire_nl1010iil_dataout & wire_nl1011Oll_dataout & wire_nl1011Oll_dataout & wire_nl1010iil_dataout); + wire_nl1011lli_sel <= ( nl11OOi1O & niOi10iii & nl11OO0li & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011lli : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl1011lli_data, + o => wire_nl1011lli_o, + sel => wire_nl1011lli_sel + ); + wire_nl1011lll_data <= ( wire_nl1010l0O_dataout & "0" & wire_nl1010iiO_dataout & wire_nl1011OlO_dataout & wire_nl1011OlO_dataout & wire_nl1010iiO_dataout); + wire_nl1011lll_sel <= ( nl11OOi1O & niOi10iii & nl11OO0li & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011lll : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl1011lll_data, + o => wire_nl1011lll_o, + sel => wire_nl1011lll_sel + ); + wire_nl1011llO_data <= ( wire_nl1010lii_dataout & "0" & wire_nl1010ili_dataout & wire_nl1011OOi_dataout & wire_nl1011OOi_dataout & wire_nl1010ili_dataout); + wire_nl1011llO_sel <= ( nl11OOi1O & niOi10iii & nl11OO0li & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011llO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl1011llO_data, + o => wire_nl1011llO_o, + sel => wire_nl1011llO_sel + ); + wire_nl1011lOl_data <= ( wire_nl1010lil_dataout & wire_w_lg_niOi10l0i60003w & wire_nl1010ill_dataout & wire_nl101000O_dataout & wire_nl101001i_dataout & wire_nl10101lO_dataout & wire_nl1011OOl_dataout & wire_nl1011O1l_dataout & wire_nl1010ill_dataout); + wire_nl1011lOl_sel <= ( nl11OOi1O & nl11OO0ll & nl11OO0li & nl11OOi1l & nl11OOi1i & nl11OO0OO & nl11OO0Ol & nl11OO0Oi & nl11OO0lO); + nl1011lOl : oper_selector + GENERIC MAP ( + width_data => 9, + width_sel => 9 + ) + PORT MAP ( + data => wire_nl1011lOl_data, + o => wire_nl1011lOl_o, + sel => wire_nl1011lOl_sel + ); + wire_nl10OOl_data <= ( wire_nl1illO_dataout & wire_nl1iOlO_dataout); + wire_nl10OOl_sel <= ( nl11iOi & wire_nl1000i_w_lg_nl11iOi2246w); + nl10OOl : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl10OOl_data, + o => wire_nl10OOl_o, + sel => wire_nl10OOl_sel + ); + wire_nl10OOO_data <= ( wire_nl1ilOi_dataout & wire_nl1iOOi_dataout); + wire_nl10OOO_sel <= ( nl11iOl & wire_nl1000i_w_lg_nl11iOl2239w); + nl10OOO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl10OOO_data, + o => wire_nl10OOO_o, + sel => wire_nl10OOO_sel + ); + wire_nl1i00i_data <= ( nli11OiOl & nli1i01ll & nli11O1Oi & "0" & nl0OOO10l & nl0OOi1ll & nl0OO1Oil & nl0OO1l1O & nl0Ol0O1O & nl0Ol0l0O & nl0Ol000i & nl0Ol01ii & "0" & nl0l0OilO & nli1l1l0O & wire_nl0iO0lil_dataout); + wire_nl1i00i_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i00i : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i00i_data, + o => wire_nl1i00i_o, + sel => wire_nl1i00i_sel + ); + wire_nl1i00l_data <= ( "0" & nli1i01li & nli11O0ii & "0" & nl0OOO10O & nl0OOi1lO & nl0OO0Oii & nl0OO1l0i & nl0Ol0O0i & nl0Ol0lii & nl0Ol000l & nl0Ol01il & "0" & nl0l0OiOi & nli1l1lii & wire_nl0iO0liO_dataout); + wire_nl1i00l_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i00l : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i00l_data, + o => wire_nl1i00l_o, + sel => wire_nl1i00l_sel + ); + wire_nl1i00O_data <= ( "0" & wire_nli1i1OiO_dataout & wire_nli11O10O_dataout & "0" & nl0OOO1ii & nl0OOi1Oi & nl0OO0Oil & nl0OO1l0l & nl0Ol0O0l & nl0Ol0lil & nl0Ol000O & nl0Ol01iO & "0" & nl0l0OiOl & nli1l1lil & wire_nl0iO0lli_dataout); + wire_nl1i00O_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i00O : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i00O_data, + o => wire_nl1i00O_o, + sel => wire_nl1i00O_sel + ); + wire_nl1i01i_data <= ( nli11Ol0l & nli1i01Ol & wire_nli11O11l_dataout & nli10Oiil & nl0OOO11l & nl0OOi0Oi & nl0OOi1il & nl0OO1iOO & nl0Ol0lOO & nl0Ol0l1O & nl0Ol001i & nl0Ol010i & nli11illO & k_conf(219) & "0" & wire_nl0iO0l0l_dataout); + wire_nl1i01i_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i01i : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i01i_data, + o => wire_nl1i01i_o, + sel => wire_nl1i01i_sel + ); + wire_nl1i01l_data <= ( nli11Ol0O & nli1i01Oi & wire_nli11O11O_dataout & nli10OiiO & nl0OOO11O & nl0OOi0Ol & nl0OOi1iO & nl0OO1l1i & nl0Ol0O1i & nl0Ol0l0i & nl0Ol001l & nl0Ol010l & "0" & k_conf(220) & "0" & wire_nl0iO0l0O_dataout); + wire_nl1i01l_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i01l : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i01l_data, + o => wire_nl1i01l_o, + sel => wire_nl1i01l_sel + ); + wire_nl1i01O_data <= ( nli11Olii & nli1i01lO & wire_nli11O10i_dataout & nli10Oili & nl0OOO10i & nl0OOi0OO & nl0OOi1li & nl0OO1l1l & nl0Ol0O1l & nl0Ol0l0l & nl0Ol001O & nl0Ol010O & k_conf(96) & k_conf(221) & nli1l001O & wire_nl0iO0lii_dataout); + wire_nl1i01O_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i01O : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i01O_data, + o => wire_nl1i01O_o, + sel => wire_nl1i01O_sel + ); + wire_nl1i0ii_data <= ( "0" & wire_nli1i1Oli_dataout & nli11O1li & "0" & nl0OOO1il & nl0OOi1Ol & nl0OO0OiO & nl0OO1l0O & nl0Ol0O0O & nl0Ol0liO & nl0Ol00ii & nl0Ol01li & "0" & k_conf(222) & nli1l1liO & wire_nl0iO0lll_dataout); + wire_nl1i0ii_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i0ii : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i0ii_data, + o => wire_nl1i0ii_o, + sel => wire_nl1i0ii_sel + ); + wire_nl1i0il_data <= ( "0" & wire_nli1i1O1i_dataout & nli11O1ll & wire_nli0O1OOl_dataout & nl0OOO1iO & nl0OOi1OO & nl0OO0Oli & nl0OO1lii & nl0Ol0Oii & nl0Ol0lli & nl0Ol00il & nl0Ol01ll & nli11l1ll & k_conf(223) & nli1l1lli & wire_nl0iO0llO_dataout); + wire_nl1i0il_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i0il : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i0il_data, + o => wire_nl1i0il_o, + sel => wire_nl1i0il_sel + ); + wire_nl1i0iO_data <= ( "0" & wire_nli1i1O1l_dataout & nli11O1lO & wire_nli0O1OOO_dataout & nl0OOO1li & nl0OOi01i & nl0OO0Oll & nl0OO1lil & nl0Ol0Oil & nl0Ol0lll & nl0Ol00iO & nl0Ol01lO & nli11iill & "0" & nli1l1lll & wire_nl0iO0lOi_dataout); + wire_nl1i0iO_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i0iO : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i0iO_data, + o => wire_nl1i0iO_o, + sel => wire_nl1i0iO_sel + ); + wire_nl1i0li_data <= ( "0" & nli1i011i & nli11O1iO & wire_nli0O011i_dataout & nl0OOO1ll & nl0OOi01l & nl0OO0OlO & nl0OO1liO & nl0Ol0OiO & nl0Ol0llO & nl0Ol00li & nl0Ol01Oi & nli11ilil & "0" & nli1l1llO & wire_nl0iO0lOl_dataout); + wire_nl1i0li_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i0li : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i0li_data, + o => wire_nl1i0li_o, + sel => wire_nl1i0li_sel + ); + wire_nl1i0ll_data <= ( "0" & "0" & nli11O1il & "0" & nl0OOO1lO & nl0OOi01O & nl0OO0OOi & nl0OO1lli & nl0Ol0Oli & nl0Ol0lOi & nl0Ol00ll & nl0Ol01Ol & nli11iliO & "0" & nli1l1lOi & wire_nl0iO0lOO_dataout); + wire_nl1i0ll_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i0ll : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i0ll_data, + o => wire_nl1i0ll_o, + sel => wire_nl1i0ll_sel + ); + wire_nl1i0lO_data <= ( "0" & nli10OO0l & nli11li1i & "0" & nl0OOO1Oi & nl0OOi00i & nl0OO0OOl & nl0OO1lll & nl0Ol00lO & "0" & nl0Ol1lOi & nli11illi & "0" & nli1l1lOl & wire_nl0iO0O1i_dataout); + wire_nl1i0lO_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & wire_nl1000i_w_lg_nl11l1O1558w & nl11l1l & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i0lO : oper_selector + GENERIC MAP ( + width_data => 15, + width_sel => 15 + ) + PORT MAP ( + data => wire_nl1i0lO_data, + o => wire_nl1i0lO_o, + sel => wire_nl1i0lO_sel + ); + wire_nl1i0Ol_data <= ( "0" & "0" & "0" & "0" & nl0OOO1Ol & nl0OOi00l & nl0OO0OOO & nl0OO1llO & nl0Ol00Oi & "0" & nl0Ol1lOl & niOOl1il & "0" & nli1l1lOO); + wire_nl1i0Ol_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & niOO0llll & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1i0Ol : oper_selector + GENERIC MAP ( + width_data => 14, + width_sel => 14 + ) + PORT MAP ( + data => wire_nl1i0Ol_data, + o => wire_nl1i0Ol_o, + sel => wire_nl1i0Ol_sel + ); + wire_nl1i0OO_data <= ( "0" & "0" & "0" & wire_nli0O011l_dataout & nl0OOO1OO & nl0OOi00O & nl0OOi11i & nl0OO1lOi & nl0Ol00Ol & "0" & nl0Ol1lOO & niOOil0i & "0" & nli1l1O1i); + wire_nl1i0OO_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & niOO0llll & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1i0OO : oper_selector + GENERIC MAP ( + width_data => 14, + width_sel => 14 + ) + PORT MAP ( + data => wire_nl1i0OO_data, + o => wire_nl1i0OO_o, + sel => wire_nl1i0OO_sel + ); + wire_nl1i10i_data <= ( wire_nl1iO1l_dataout & wire_nl1l11l_dataout); + wire_nl1i10i_sel <= ( nl11l1O & wire_nl1000i_w_lg_nl11l1O2211w); + nl1i10i : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i10i_data, + o => wire_nl1i10i_o, + sel => wire_nl1i10i_sel + ); + wire_nl1i10l_data <= ( wire_nl1iO1O_dataout & wire_nl1l11O_dataout); + wire_nl1i10l_sel <= ( nl11l0i & wire_nl1000i_w_lg_nl11l0i2204w); + nl1i10l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i10l_data, + o => wire_nl1i10l_o, + sel => wire_nl1i10l_sel + ); + wire_nl1i10O_data <= ( wire_nl1iO0i_dataout & wire_nl1l10i_dataout); + wire_nl1i10O_sel <= ( nl11l0l & wire_nl1000i_w_lg_nl11l0l2197w); + nl1i10O : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i10O_data, + o => wire_nl1i10O_o, + sel => wire_nl1i10O_sel + ); + wire_nl1i11i_data <= ( wire_nl1ilOl_dataout & wire_nl1iOOl_dataout); + wire_nl1i11i_sel <= ( nl11iOO & wire_nl1000i_w_lg_nl11iOO2232w); + nl1i11i : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i11i_data, + o => wire_nl1i11i_o, + sel => wire_nl1i11i_sel + ); + wire_nl1i11l_data <= ( wire_nl1ilOO_dataout & wire_nl1iOOO_dataout); + wire_nl1i11l_sel <= ( nl11l1i & wire_nl1000i_w_lg_nl11l1i2225w); + nl1i11l : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i11l_data, + o => wire_nl1i11l_o, + sel => wire_nl1i11l_sel + ); + wire_nl1i11O_data <= ( wire_nl1iO1i_dataout & wire_nl1l11i_dataout); + wire_nl1i11O_sel <= ( nl11l1l & wire_nl1000i_w_lg_nl11l1l2218w); + nl1i11O : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i11O_data, + o => wire_nl1i11O_o, + sel => wire_nl1i11O_sel + ); + wire_nl1i1ii_data <= ( wire_nl1iO0l_dataout & wire_nl1l10l_dataout); + wire_nl1i1ii_sel <= ( nl11l0O & wire_nl1000i_w_lg_nl11l0O2190w); + nl1i1ii : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1ii_data, + o => wire_nl1i1ii_o, + sel => wire_nl1i1ii_sel + ); + wire_nl1i1il_data <= ( wire_nl1iO0O_dataout & wire_nl1l10O_dataout); + wire_nl1i1il_sel <= ( nl11lii & wire_nl1000i_w_lg_nl11lii2183w); + nl1i1il : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1il_data, + o => wire_nl1i1il_o, + sel => wire_nl1i1il_sel + ); + wire_nl1i1iO_data <= ( wire_nl1iOii_dataout & wire_nl1l1ii_dataout); + wire_nl1i1iO_sel <= ( nl11lil & wire_nl1000i_w_lg_nl11lil2176w); + nl1i1iO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1iO_data, + o => wire_nl1i1iO_o, + sel => wire_nl1i1iO_sel + ); + wire_nl1i1li_data <= ( wire_nl1iOil_dataout & wire_nl1l1il_dataout); + wire_nl1i1li_sel <= ( nl11liO & wire_nl1000i_w_lg_nl11liO2169w); + nl1i1li : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1li_data, + o => wire_nl1i1li_o, + sel => wire_nl1i1li_sel + ); + wire_nl1i1ll_data <= ( wire_nl1iOiO_dataout & wire_nl1l1iO_dataout); + wire_nl1i1ll_sel <= ( nl11lli & wire_nl1000i_w_lg_nl11lli2162w); + nl1i1ll : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1ll_data, + o => wire_nl1i1ll_o, + sel => wire_nl1i1ll_sel + ); + wire_nl1i1lO_data <= ( wire_nl1iOli_dataout & wire_nl1l1li_dataout); + wire_nl1i1lO_sel <= ( nl11lll & wire_nl1000i_w_lg_nl11lll2155w); + nl1i1lO : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1lO_data, + o => wire_nl1i1lO_o, + sel => wire_nl1i1lO_sel + ); + wire_nl1i1Oi_data <= ( wire_nl1l1ll_dataout & wire_nl1iOll_dataout); + wire_nl1i1Oi_sel <= ( nl11lOi & wire_nl11llO_w_lg_nl11lOi2148w); + nl1i1Oi : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1Oi_data, + o => wire_nl1i1Oi_o, + sel => wire_nl1i1Oi_sel + ); + wire_nl1i1Ol_data <= ( wire_nl1l1lO_dataout & wire_nl1illl_dataout); + wire_nl1i1Ol_sel <= ( wire_nl1000i_w_lg_nl11ilO2143w & nl11ilO); + nl1i1Ol : oper_selector + GENERIC MAP ( + width_data => 2, + width_sel => 2 + ) + PORT MAP ( + data => wire_nl1i1Ol_data, + o => wire_nl1i1Ol_o, + sel => wire_nl1i1Ol_sel + ); + wire_nl1i1OO_data <= ( nli11Ol0i & nli1i01OO & wire_nli11O11i_dataout & nli10001O & nl0OOii1i & nl0OOi0lO & nl0OOi1ii & nl0Ol0Oll & nl0Ol0lOl & nl0Ol0l1l & nl0Ol01OO & nl0Ol011O & nli11illl & nl0l0Oill & "0" & wire_nl0iO0l0i_dataout); + wire_nl1i1OO_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1O & nl11l1l & nl11l1i & nl11iOO & nl11iOl & nl11iOi & nl11ilO); + nl1i1OO : oper_selector + GENERIC MAP ( + width_data => 16, + width_sel => 16 + ) + PORT MAP ( + data => wire_nl1i1OO_data, + o => wire_nl1i1OO_o, + sel => wire_nl1i1OO_sel + ); + wire_nl1ii0i_data <= ( nli1iOl1i & "0" & nli1il10O & "0" & nl0OiOl0O & nl0OOi0iO & nl0OOi10i & nl0OO1O1i & nl0Ol0i1l & nl0Ol1O1O & "0" & k_conf(296) & nli1l1O0i); + wire_nl1ii0i_sel <= ( nl11lOi & niOO0lllO & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1ii0i : oper_selector + GENERIC MAP ( + width_data => 13, + width_sel => 13 + ) + PORT MAP ( + data => wire_nl1ii0i_data, + o => wire_nl1ii0i_o, + sel => wire_nl1ii0i_sel + ); + wire_nl1ii0l_data <= ( nli1iOiOO & "0" & "0" & wire_nli0O010i_dataout & "0" & nl0OOi0li & nl0OOi10l & nl0OO1O1l & nl0Ol0i1O & nl0Ol1O0i & "0" & k_conf(297) & nli1l1O0l); + wire_nl1ii0l_sel <= ( nl11lOi & niOO0lllO & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1ii0l : oper_selector + GENERIC MAP ( + width_data => 13, + width_sel => 13 + ) + PORT MAP ( + data => wire_nl1ii0l_data, + o => wire_nl1ii0l_o, + sel => wire_nl1ii0l_sel + ); + wire_nl1ii0O_data <= ( nli1iOiOl & "0" & nli1il10i & "0" & nl0OiOl0l & nl0OOi0ll & nl0OOi10O & nl0OO1O1O & nl0Ol0i0i & nl0Ol1O0l & "0" & k_conf(298) & nli1l1O0O); + wire_nl1ii0O_sel <= ( nl11lOi & niOO0lllO & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1ii0O : oper_selector + GENERIC MAP ( + width_data => 13, + width_sel => 13 + ) + PORT MAP ( + data => wire_nl1ii0O_data, + o => wire_nl1ii0O_o, + sel => wire_nl1ii0O_sel + ); + wire_nl1ii1i_data <= ( "0" & "0" & "0" & "0" & nl0OOO01i & nl0OOi0ii & nl0OOi11l & nl0OO1lOl & nl0Ol00OO & "0" & nl0Ol1O1i & nli11ilOi & "0" & nli1l1O1l); + wire_nl1ii1i_sel <= ( nl11lOi & nl11lll & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & niOO0llll & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1ii1i : oper_selector + GENERIC MAP ( + width_data => 14, + width_sel => 14 + ) + PORT MAP ( + data => wire_nl1ii1i_data, + o => wire_nl1ii1i_o, + sel => wire_nl1ii1i_sel + ); + wire_nl1ii1O_data <= ( nli1iOl1l & "0" & nli1il10l & wire_nli0O011O_dataout & nl0OiOlii & nl0OOi0il & nl0OOi11O & nl0OO1lOO & nl0Ol0i1i & nl0Ol1O1l & "0" & k_conf(295) & nli1l1O1O); + wire_nl1ii1O_sel <= ( nl11lOi & niOO0lllO & nl11lli & nl11liO & nl11lil & nl11lii & nl11l0O & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1ii1O : oper_selector + GENERIC MAP ( + width_data => 13, + width_sel => 13 + ) + PORT MAP ( + data => wire_nl1ii1O_data, + o => wire_nl1ii1O_o, + sel => wire_nl1ii1O_sel + ); + wire_nl1iiil_data <= ( nli1iOiOi & "0" & nli1il11O & "0" & nl0OiOl0i & nl0OO1O0i & nl0Ol0i0l & nl0Ol1O0O & "0" & k_conf(299) & nli1l1Oii); + wire_nl1iiil_sel <= ( nl11lOi & niOO0llOi & nl11lli & nl11liO & nl11lil & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1iiil : oper_selector + GENERIC MAP ( + width_data => 11, + width_sel => 11 + ) + PORT MAP ( + data => wire_nl1iiil_data, + o => wire_nl1iiil_o, + sel => wire_nl1iiil_sel + ); + wire_nl1iiiO_data <= ( nli1iOili & "0" & "0" & "0" & "0" & nl0OO1O0l & nl0Ol0i0O & nl0Ol1Oii & "0" & k_conf(300) & nli1l1Oil); + wire_nl1iiiO_sel <= ( nl11lOi & niOO0llOi & nl11lli & nl11liO & nl11lil & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1iiiO : oper_selector + GENERIC MAP ( + width_data => 11, + width_sel => 11 + ) + PORT MAP ( + data => wire_nl1iiiO_data, + o => wire_nl1iiiO_o, + sel => wire_nl1iiiO_sel + ); + wire_nl1iili_data <= ( nli1iOill & "0" & nli1il11i & "0" & nl0OiO1Oi & nl0OO1O0O & nl0Ol0iii & nl0Ol1Oil & "0" & k_conf(301) & nli1l1OiO); + wire_nl1iili_sel <= ( nl11lOi & niOO0llOi & nl11lli & nl11liO & nl11lil & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1iili : oper_selector + GENERIC MAP ( + width_data => 11, + width_sel => 11 + ) + PORT MAP ( + data => wire_nl1iili_data, + o => wire_nl1iili_o, + sel => wire_nl1iili_sel + ); + wire_nl1iill_data <= ( nli1iOilO & "0" & nli1iiOOO & "0" & "0" & nl0OO1Oii & nl0Ol0iil & nl0Ol1OiO & "0" & k_conf(302) & nli1l1Oli); + wire_nl1iill_sel <= ( nl11lOi & niOO0llOi & nl11lli & nl11liO & nl11lil & nl11l0l & nl11l0i & nl11l1l & nl11iOO & nl11iOl & nl11iOi); + nl1iill : oper_selector + GENERIC MAP ( + width_data => 11, + width_sel => 11 + ) + PORT MAP ( + data => wire_nl1iill_data, + o => wire_nl1iill_o, + sel => wire_nl1iill_sel + ); + wire_nl1iiOi_data <= ( nli1iOiiO & "0" & nli1iiOOl & "0" & nl0Ol0iiO & nl0Ol1Oli & niOOil0l & k_conf(303)); + wire_nl1iiOi_sel <= ( nl11lOi & niOO0lOlO & nl11lli & nl11lil & nl11l0i & nl11l1l & nl11iOO & nl11iOl); + nl1iiOi : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1iiOi_data, + o => wire_nl1iiOi_o, + sel => wire_nl1iiOi_sel + ); + wire_nl1iiOl_data <= ( "0" & "0" & wire_nli1iiOll_dataout & "0" & nl0Ol0ili & nl0Ol1Oll & niOOil0O & k_conf(304)); + wire_nl1iiOl_sel <= ( nl11lOi & niOO0lOlO & nl11lli & nl11lil & nl11l0i & nl11l1l & nl11iOO & wire_niOO0llOl40_w_lg_w_lg_q1262w1263w); + nl1iiOl : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1iiOl_data, + o => wire_nl1iiOl_o, + sel => wire_nl1iiOl_sel + ); + wire_nl1iiOO_data <= ( nli1ilO1O & "0" & wire_nli1iiOli_dataout & "0" & wire_niOO0llOO38_w_lg_w_lg_q1253w1254w & nl0Ol1OlO & niOOilii & k_conf(305)); + wire_nl1iiOO_sel <= ( wire_niOO0lO1i36_w_lg_w_lg_q1245w1246w & niOO0lOlO & nl11lli & nl11lil & nl11l0i & nl11l1l & nl11iOO & nl11iOl); + nl1iiOO : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1iiOO_data, + o => wire_nl1iiOO_o, + sel => wire_nl1iiOO_sel + ); + wire_nl1il0i_data <= ( nli1iOiii & "0" & "0" & "0" & nl0Ol0iOO & nl0Ol011i & niOOilll & nl0l0OiOO); + wire_nl1il0i_sel <= ( nl11lOi & wire_niOO0lOii24_w_lg_w_lg_q1146w1147w & nl11lli & nl11lil & nl11l0i & nl11l1l & nl11iOO & nl11iOl); + nl1il0i : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1il0i_data, + o => wire_nl1il0i_o, + sel => wire_nl1il0i_sel + ); + wire_nl1il0l_data <= ( wire_niOO0lOil22_w_lg_w_lg_q1136w1137w & "0" & "0" & "0" & wire_niOO0lOiO20_w_lg_w_lg_q1127w1128w & nl0Ol011l & niOOillO & nl0lil11i); + wire_nl1il0l_sel <= ( wire_niOO0lOli18_w_lg_w_lg_q1120w1121w & niOO0lOlO & nl11lli & nl11lil & wire_niOO0lOll16_w_lg_w_lg_q1114w1115w & nl11l1l & nl11iOO & nl11iOl); + nl1il0l : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1il0l_data, + o => wire_nl1il0l_o, + sel => wire_nl1il0l_sel + ); + wire_nl1il1i_data <= ( nli1iOiil & "0" & wire_nli1iiOiO_dataout & "0" & nl0Ol0ilO & nl0Ol1OOi & niOOilil & "0"); + wire_nl1il1i_sel <= ( nl11lOi & niOO0lOlO & nl11lli & nl11lil & nl11l0i & wire_niOO0lO1l34_w_lg_w_lg_q1217w1218w & nl11iOO & nl11iOl); + nl1il1i : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1il1i_data, + o => wire_nl1il1i_o, + sel => wire_nl1il1i_sel + ); + wire_nl1il1l_data <= ( nli1iOi0l & "0" & "0" & "0" & nl0Ol0iOi & nl0Ol1OOl & niOOiliO & "0"); + wire_nl1il1l_sel <= ( nl11lOi & niOO0lOlO & nl11lli & nl11lil & nl11l0i & nl11l1l & nl11iOO & wire_niOO0lO1O32_w_lg_w_lg_q1190w1191w); + nl1il1l : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1il1l_data, + o => wire_nl1il1l_o, + sel => wire_nl1il1l_sel + ); + wire_nl1il1O_data <= ( nli1iOi0O & "0" & "0" & "0" & nl0Ol0iOl & wire_niOO0lO0i30_w_lg_w_lg_q1179w1180w & niOOilli & "0"); + wire_nl1il1O_sel <= ( nl11lOi & niOO0lOlO & nl11lli & nl11lil & nl11l0i & wire_niOO0lO0l28_w_lg_w_lg_q1167w1168w & wire_niOO0lO0O26_w_lg_w_lg_q1164w1165w & nl11iOl); + nl1il1O : oper_selector + GENERIC MAP ( + width_data => 8, + width_sel => 8 + ) + PORT MAP ( + data => wire_nl1il1O_data, + o => wire_nl1il1O_o, + sel => wire_nl1il1O_sel + ); + wire_nl1lliiOO_data <= ( wire_nl1llO0ll_dataout & niOi1lOOi & wire_nl1lll1OO_dataout & wire_nl1lliOll_dataout & wire_nl1lliO0O_dataout); + wire_nl1lliiOO_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & nl1ll0ilO & nl1ll0ill); + nl1lliiOO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1lliiOO_data, + o => wire_nl1lliiOO_o, + sel => wire_nl1lliiOO_sel + ); + wire_nl1llil0i_data <= ( wire_nl1llO0OO_dataout & wire_nl1llll1i_dataout & wire_nl1lll00i_dataout & wire_nl1lliOOO_dataout & wire_nl1lliOli_dataout); + wire_nl1llil0i_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & nl1ll0ilO & nl1ll0ill); + nl1llil0i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1llil0i_data, + o => wire_nl1llil0i_o, + sel => wire_nl1llil0i_sel + ); + wire_nl1llil0l_data <= ( wire_nl1llOi1i_dataout & wire_nl1llll1l_dataout & wire_nl1lll00l_dataout & wire_nl1lll11i_dataout & nl1ll0lOl); + wire_nl1llil0l_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & nl1ll0ilO & nl1ll0ill); + nl1llil0l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1llil0l_data, + o => wire_nl1llil0l_o, + sel => wire_nl1llil0l_sel + ); + wire_nl1llil0O_data <= ( "0" & wire_nl1llllOO_dataout & wire_nl1lll0ii_dataout & nl1ll0l1i); + wire_nl1llil0O_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llil0O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llil0O_data, + o => wire_nl1llil0O_o, + sel => wire_nl1llil0O_sel + ); + wire_nl1llil1i_data <= ( wire_nl1llO0lO_dataout & wire_nl1llliOO_dataout & wire_nl1lll01i_dataout & wire_nl1lliOlO_dataout & wire_nl1lliOii_dataout); + wire_nl1llil1i_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & nl1ll0ilO & nl1ll0ill); + nl1llil1i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1llil1i_data, + o => wire_nl1llil1i_o, + sel => wire_nl1llil1i_sel + ); + wire_nl1llil1l_data <= ( wire_nl1llO0Oi_dataout & wire_nl1llll1l_dataout & wire_nl1lll01l_dataout & wire_nl1lliOOi_dataout & wire_nl1lliOil_dataout); + wire_nl1llil1l_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & nl1ll0ilO & nl1ll0ill); + nl1llil1l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1llil1l_data, + o => wire_nl1llil1l_o, + sel => wire_nl1llil1l_sel + ); + wire_nl1llil1O_data <= ( wire_nl1llO0Ol_dataout & "0" & wire_nl1lll01O_dataout & wire_nl1lliOOl_dataout & wire_nl1lliOiO_dataout); + wire_nl1llil1O_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & nl1ll0ilO & nl1ll0ill); + nl1llil1O : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1llil1O_data, + o => wire_nl1llil1O_o, + sel => wire_nl1llil1O_sel + ); + wire_nl1llilii_data <= ( "0" & wire_nl1lllO1i_dataout & wire_nl1lll0il_dataout & nl1ll0l1l); + wire_nl1llilii_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llilii : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llilii_data, + o => wire_nl1llilii_o, + sel => wire_nl1llilii_sel + ); + wire_nl1llilil_data <= ( "0" & wire_nl1lllO1l_dataout & wire_nl1lll0iO_dataout & nl1ll0l1O); + wire_nl1llilil_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llilil : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llilil_data, + o => wire_nl1llilil_o, + sel => wire_nl1llilil_sel + ); + wire_nl1lliliO_data <= ( "0" & wire_nl1lllO1O_dataout & wire_nl1lll0li_dataout & nl1ll0l0i); + wire_nl1lliliO_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1lliliO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1lliliO_data, + o => wire_nl1lliliO_o, + sel => wire_nl1lliliO_sel + ); + wire_nl1llilli_data <= ( "0" & wire_nl1lllO0i_dataout & wire_nl1lll0ll_dataout & nl1ll0l0l); + wire_nl1llilli_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llilli : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llilli_data, + o => wire_nl1llilli_o, + sel => wire_nl1llilli_sel + ); + wire_nl1llilll_data <= ( "0" & wire_nl1lllO0l_dataout & wire_nl1lll0lO_dataout & nl1ll0l0O); + wire_nl1llilll_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llilll : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llilll_data, + o => wire_nl1llilll_o, + sel => wire_nl1llilll_sel + ); + wire_nl1llillO_data <= ( "0" & wire_nl1lllO0O_dataout & wire_nl1lll0Oi_dataout & nl1ll0lii); + wire_nl1llillO_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llillO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llillO_data, + o => wire_nl1llillO_o, + sel => wire_nl1llillO_sel + ); + wire_nl1llilOi_data <= ( "0" & wire_nl1lllOii_dataout & wire_nl1lll0Ol_dataout & nl1ll0lil); + wire_nl1llilOi_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llilOi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llilOi_data, + o => wire_nl1llilOi_o, + sel => wire_nl1llilOi_sel + ); + wire_nl1llilOl_data <= ( "0" & wire_nl1lllOil_dataout & wire_nl1lll0OO_dataout & nl1ll0liO); + wire_nl1llilOl_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llilOl : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llilOl_data, + o => wire_nl1llilOl_o, + sel => wire_nl1llilOl_sel + ); + wire_nl1llilOO_data <= ( "0" & wire_nl1lllOiO_dataout & wire_nl1llli1i_dataout & nl1ll0lli); + wire_nl1llilOO_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1llilOO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1llilOO_data, + o => wire_nl1llilOO_o, + sel => wire_nl1llilOO_sel + ); + wire_nl1lliO0l_data <= ( "0" & wire_nl1llO1lO_dataout & wire_nl1lll00O_dataout & wire_nl1lll11l_dataout & nl1ll0lOi); + wire_nl1lliO0l_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & nl1ll0ilO & nl1ll0ill); + nl1lliO0l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1lliO0l_data, + o => wire_nl1lliO0l_o, + sel => wire_nl1lliO0l_sel + ); + wire_nl1lliO1i_data <= ( "0" & wire_nl1lllOli_dataout & wire_nl1llli1l_dataout & nl1ll0lll); + wire_nl1lliO1i_sel <= ( nl1ll0iOO & nl1ll0iOl & nl1ll0iOi & niOi1lO0i); + nl1lliO1i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nl1lliO1i_data, + o => wire_nl1lliO1i_o, + sel => wire_nl1lliO1i_sel + ); + wire_nl1lliO1O_data <= ( "0" & niOi1lO0l & nl1ll0llO); + wire_nl1lliO1O_sel <= ( wire_nliliO10i_w_lg_w_lg_nl1ll0iOO55586w55587w & nl1ll0iOi & nl1ll0ill); + nl1lliO1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1lliO1O_data, + o => wire_nl1lliO1O_o, + sel => wire_nl1lliO1O_sel + ); + wire_nl1OiOi1O_data <= ( wire_nl1Ol111i_dataout & nl1OilliO & wire_nl1OiOlll_dataout); + wire_nl1OiOi1O_sel <= ( nl1OilO0i & wire_nlill0Oll_w_lg_w_lg_w_lg_nl1OilO1O55178w55179w55180w & nl1OilO1l); + nl1OiOi1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nl1OiOi1O_data, + o => wire_nl1OiOi1O_o, + sel => wire_nl1OiOi1O_sel + ); + wire_nl1OiOiii_data <= ( wire_nl1Ol110i_dataout & wire_nl1OiOOil_dataout & nl1OilO0O & wire_nl1OiOllO_dataout & wire_nl1OiOl1O_dataout); + wire_nl1OiOiii_sel <= ( nl1OilO0i & nl1OilO1O & niOi1Oi1l & nl1OilO1l & nl1OillOO); + nl1OiOiii : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1OiOiii_data, + o => wire_nl1OiOiii_o, + sel => wire_nl1OiOiii_sel + ); + wire_nl1OiOiil_data <= ( wire_nl1Ol110l_dataout & wire_nl1OiOOiO_dataout & nl1OilOii & wire_nl1OiOlOi_dataout & wire_nl1OiOl0i_dataout); + wire_nl1OiOiil_sel <= ( nl1OilO0i & nl1OilO1O & niOi1Oi1l & nl1OilO1l & nl1OillOO); + nl1OiOiil : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1OiOiil_data, + o => wire_nl1OiOiil_o, + sel => wire_nl1OiOiil_sel + ); + wire_nl1OiOili_data <= ( wire_nl1Ol110O_dataout & wire_nl1OiOOli_dataout & "0" & wire_nl1OiOlOl_dataout & wire_nl1OiOl0l_dataout); + wire_nl1OiOili_sel <= ( nl1OilO0i & nl1OilO1O & niOi1Oi1l & nl1OilO1l & nl1OillOO); + nl1OiOili : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1OiOili_data, + o => wire_nl1OiOili_o, + sel => wire_nl1OiOili_sel + ); + wire_nl1OiOill_data <= ( wire_nl1Ol11ii_dataout & wire_nl1OiOOll_dataout & "0" & wire_nl1OiOlOO_dataout & wire_nl1OiOl0O_dataout); + wire_nl1OiOill_sel <= ( nl1OilO0i & nl1OilO1O & niOi1Oi1l & nl1OilO1l & nl1OillOO); + nl1OiOill : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1OiOill_data, + o => wire_nl1OiOill_o, + sel => wire_nl1OiOill_sel + ); + wire_nl1OiOilO_data <= ( wire_nl1Ol11il_dataout & wire_nl1OiOOlO_dataout & "0" & wire_nl1OiOO1i_dataout & wire_nl1OiOlii_dataout); + wire_nl1OiOilO_sel <= ( nl1OilO0i & nl1OilO1O & niOi1Oi1l & nl1OilO1l & nl1OillOO); + nl1OiOilO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1OiOilO_data, + o => wire_nl1OiOilO_o, + sel => wire_nl1OiOilO_sel + ); + wire_nl1OiOiOi_data <= ( wire_nl1Ol11iO_dataout & wire_nl1OiOOOi_dataout & "1" & wire_nl1OiOO1l_dataout & "0" & wire_nl1OiOlil_dataout); + wire_nl1OiOiOi_sel <= ( nl1OilO0i & nl1OilO1O & nl1OillOl & nl1OilO1l & nl1OilO1i & nl1OillOO); + nl1OiOiOi : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl1OiOiOi_data, + o => wire_nl1OiOiOi_o, + sel => wire_nl1OiOiOi_sel + ); + wire_nl1OiOiOl_data <= ( wire_nl1Ol11li_dataout & wire_nl1OiOOOl_dataout & "0" & wire_nl1OiOOOl_dataout & wire_nl1OiOliO_dataout); + wire_nl1OiOiOl_sel <= ( nl1OilO0i & nl1OilO1O & niOi1Oi1l & nl1OilO1l & nl1OillOO); + nl1OiOiOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nl1OiOiOl_data, + o => wire_nl1OiOiOl_o, + sel => wire_nl1OiOiOl_sel + ); + wire_nl1OiOiOO_data <= ( wire_nl1Ol11ll_dataout & wire_nl1OiOOOO_dataout & "0" & wire_nl1OiOOOO_dataout & "1" & wire_nl1OiOlli_dataout); + wire_nl1OiOiOO_sel <= ( nl1OilO0i & nl1OilO1O & nl1OillOl & nl1OilO1l & nl1OilO1i & nl1OillOO); + nl1OiOiOO : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nl1OiOiOO_data, + o => wire_nl1OiOiOO_o, + sel => wire_nl1OiOiOO_sel + ); + wire_nli11iOll_data <= ( wire_nli11l1il_dataout & wire_nli11l10i_dataout & wire_nli11iOOl_dataout); + wire_nli11iOll_sel <= ( niOiil0ll & niOiil0li & wire_w_lg_niOiil0iO48178w); + nli11iOll : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli11iOll_data, + o => wire_nli11iOll_o, + sel => wire_nli11iOll_sel + ); + wire_nli11iOlO_data <= ( wire_nli11l1iO_dataout & wire_nli11l10l_dataout & wire_nli11iOOO_dataout); + wire_nli11iOlO_sel <= ( niOiil0ll & niOiil0li & wire_w_lg_niOiil0iO48178w); + nli11iOlO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nli11iOlO_data, + o => wire_nli11iOlO_o, + sel => wire_nli11iOlO_sel + ); + wire_nlil00lOl_data <= ( nlil000Ol & wire_nlil0lO0O_dataout & "0" & "1" & wire_nlil0i11l_dataout); + wire_nlil00lOl_sel <= ( niOilO0ll & nlil00iiO & nlil00iil & nlil00i0l & nlil00i0i); + nlil00lOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlil00lOl_data, + o => wire_nlil00lOl_o, + sel => wire_nlil00lOl_sel + ); + wire_nlil00O0i_data <= ( "0" & wire_nlili00Ol_dataout & wire_nlili1lOO_dataout & wire_nlili100i_dataout & wire_nlili110l_dataout & wire_nlil0Oiil_dataout & wire_nlil0lOil_dataout & wire_nlil0liiO_dataout & wire_nlil0l0ll_dataout & wire_nlil0i0OO_dataout & wire_nlil0i01l_dataout & wire_nlil0i10i_dataout); + wire_nlil00O0i_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00O0i : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00O0i_data, + o => wire_nlil00O0i_o, + sel => wire_nlil00O0i_sel + ); + wire_nlil00O0l_data <= ( "0" & wire_nlili00OO_dataout & wire_nlili1O1i_dataout & wire_nlili100l_dataout & wire_nlili110O_dataout & wire_nlil0OiiO_dataout & wire_nlil0lOiO_dataout & wire_nlil0lili_dataout & wire_nlil0l0lO_dataout & wire_nlil0ii1i_dataout & wire_nlil0i01O_dataout & wire_nlil0i10l_dataout); + wire_nlil00O0l_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00O0l : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00O0l_data, + o => wire_nlil00O0l_o, + sel => wire_nlil00O0l_sel + ); + wire_nlil00O0O_data <= ( "0" & wire_nlili0i1i_dataout & wire_nlili1O1l_dataout & wire_nlili100O_dataout & wire_nlili11ii_dataout & wire_nlil0Oili_dataout & wire_nlil0lOli_dataout & wire_nlil0lill_dataout & wire_nlil0l0Oi_dataout & wire_nlil0ii1l_dataout & wire_nlil0i00i_dataout & wire_nlil0i10O_dataout); + wire_nlil00O0O_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00O0O : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00O0O_data, + o => wire_nlil00O0O_o, + sel => wire_nlil00O0O_sel + ); + wire_nlil00O1i_data <= ( nlil01i0l & wire_nlili00lO_dataout & wire_nlili101l_dataout & wire_nlil0lO0l_dataout & wire_nlili101l_dataout); + wire_nlil00O1i_sel <= ( niOilO0lO & nlil00ill & nlil00i1i & nlil00iiO & nlil00i0O); + nlil00O1i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlil00O1i_data, + o => wire_nlil00O1i_o, + sel => wire_nlil00O1i_sel + ); + wire_nlil00O1O_data <= ( "0" & wire_nlili00Oi_dataout & wire_nlili1lOl_dataout & wire_nlili101O_dataout & "1" & wire_nlili110i_dataout & wire_nlil0Oiii_dataout & wire_nlil0lOii_dataout & wire_nlil0liil_dataout & wire_nlil0l0li_dataout & wire_nlil0i0Ol_dataout & wire_nlil0i01i_dataout & wire_nlil0i11O_dataout); + wire_nlil00O1O_sel <= ( nlil00ilO & nlil00ill & nlil00i1l & nlil00i1i & nlil000OO & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00O1O : oper_selector + GENERIC MAP ( + width_data => 13, + width_sel => 13 + ) + PORT MAP ( + data => wire_nlil00O1O_data, + o => wire_nlil00O1O_o, + sel => wire_nlil00O1O_sel + ); + wire_nlil00Oii_data <= ( "0" & wire_nlili0i1l_dataout & wire_nlili1O1O_dataout & wire_nlili10ii_dataout & wire_nlili11il_dataout & wire_nlil0Oill_dataout & wire_nlil0lOll_dataout & wire_nlil0lilO_dataout & wire_nlil0l0Ol_dataout & wire_nlil0ii1O_dataout & wire_nlil0i00l_dataout & wire_nlil0i1ii_dataout); + wire_nlil00Oii_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00Oii : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00Oii_data, + o => wire_nlil00Oii_o, + sel => wire_nlil00Oii_sel + ); + wire_nlil00Oil_data <= ( "0" & wire_nlili0i1O_dataout & wire_nlili1O0i_dataout & wire_nlili10il_dataout & wire_nlili11iO_dataout & wire_nlil0OilO_dataout & wire_nlil0lOlO_dataout & wire_nlil0liOi_dataout & wire_nlil0l0OO_dataout & wire_nlil0ii0i_dataout & wire_nlil0i00O_dataout & wire_nlil0i1il_dataout); + wire_nlil00Oil_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00Oil : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00Oil_data, + o => wire_nlil00Oil_o, + sel => wire_nlil00Oil_sel + ); + wire_nlil00OiO_data <= ( "0" & wire_nlili0i0i_dataout & wire_nlili1O0l_dataout & wire_nlili10iO_dataout & wire_nlili11li_dataout & wire_nlil0OiOi_dataout & wire_nlil0lOOi_dataout & wire_nlil0liOl_dataout & wire_nlil0li1i_dataout & wire_nlil0ii0l_dataout & wire_nlil0i0ii_dataout & wire_nlil0i1iO_dataout); + wire_nlil00OiO_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00OiO : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00OiO_data, + o => wire_nlil00OiO_o, + sel => wire_nlil00OiO_sel + ); + wire_nlil00Oli_data <= ( "0" & wire_nlili0i0l_dataout & wire_nlili1O0O_dataout & wire_nlili10li_dataout & wire_nlili11ll_dataout & wire_nlil0OiOl_dataout & wire_nlil0lOOl_dataout & wire_nlil0liOO_dataout & wire_nlil0li1l_dataout & wire_nlil0ii0O_dataout & wire_nlil0i0il_dataout & wire_nlil0i1li_dataout); + wire_nlil00Oli_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00Oli : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00Oli_data, + o => wire_nlil00Oli_o, + sel => wire_nlil00Oli_sel + ); + wire_nlil00Oll_data <= ( "0" & wire_nlili0i0O_dataout & wire_nlili1Oii_dataout & wire_nlili10ll_dataout & wire_nlili11lO_dataout & wire_nlil0OiOO_dataout & wire_nlil0lOOO_dataout & wire_nlil0ll1i_dataout & wire_nlil0li1O_dataout & wire_nlil0iiii_dataout & wire_nlil0i0iO_dataout & wire_nlil0i1ll_dataout); + wire_nlil00Oll_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00Oll : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00Oll_data, + o => wire_nlil00Oll_o, + sel => wire_nlil00Oll_sel + ); + wire_nlil00OlO_data <= ( "0" & wire_nlili0iii_dataout & wire_nlili1Oil_dataout & wire_nlili10lO_dataout & wire_nlili11Oi_dataout & wire_nlil0Ol1i_dataout & wire_nlil0O11i_dataout & wire_nlil0ll1l_dataout & wire_nlil0li0i_dataout & wire_nlil0iiil_dataout & wire_nlil0i0li_dataout & wire_nlil0i1lO_dataout); + wire_nlil00OlO_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00OlO : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00OlO_data, + o => wire_nlil00OlO_o, + sel => wire_nlil00OlO_sel + ); + wire_nlil00OOi_data <= ( "0" & wire_nlili0iil_dataout & wire_nlili1OiO_dataout & wire_nlili10Oi_dataout & wire_nlili11Ol_dataout & wire_nlil0Ol1l_dataout & wire_nlil0O11l_dataout & wire_nlil0ll1O_dataout & wire_nlil0li0l_dataout & wire_nlil0iiiO_dataout & wire_nlil0i0ll_dataout & wire_nlil0i1Oi_dataout); + wire_nlil00OOi_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00OOi : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00OOi_data, + o => wire_nlil00OOi_o, + sel => wire_nlil00OOi_sel + ); + wire_nlil00OOl_data <= ( "1" & wire_nlili0iiO_dataout & wire_nlili1Oli_dataout & wire_nlili10Ol_dataout & "0" & wire_nlili11OO_dataout & wire_nlil0Ol1O_dataout & wire_nlil0O11O_dataout & wire_nlil0ll0i_dataout & wire_nlil0li0O_dataout & wire_nlil0iili_dataout & wire_nlil0i0lO_dataout & wire_nlil0i1Ol_dataout); + wire_nlil00OOl_sel <= ( nlil00ilO & nlil00ill & nlil00i1l & nlil00i1i & nlil000OO & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00OOl : oper_selector + GENERIC MAP ( + width_data => 13, + width_sel => 13 + ) + PORT MAP ( + data => wire_nlil00OOl_data, + o => wire_nlil00OOl_o, + sel => wire_nlil00OOl_sel + ); + wire_nlil00OOO_data <= ( "0" & wire_nlili0ili_dataout & wire_nlili1Oll_dataout & wire_nlili10OO_dataout & wire_nlili101i_dataout & wire_nlil0Ol0i_dataout & wire_nlil0O10i_dataout & wire_nlil0ll0l_dataout & wire_nlil0liii_dataout & wire_nlil0iill_dataout & wire_nlil0i0Oi_dataout & wire_nlil0i1OO_dataout); + wire_nlil00OOO_sel <= ( niOilO0Oi & nlil00ill & nlil00i1l & nlil00i1i & nlil00iii & nlil00ili & nlil00iiO & nlil00iil & nlil00i0O & nlil00i0l & nlil00i1O & nlil00i0i); + nlil00OOO : oper_selector + GENERIC MAP ( + width_data => 12, + width_sel => 12 + ) + PORT MAP ( + data => wire_nlil00OOO_data, + o => wire_nlil00OOO_o, + sel => wire_nlil00OOO_sel + ); + wire_nlilO1i0i_data <= ( nlillOi0l & "0" & wire_nlilO0Oll_dataout & wire_nlilO0O0l_dataout & wire_nlilO01lO_dataout); + wire_nlilO1i0i_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1i0i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1i0i_data, + o => wire_nlilO1i0i_o, + sel => wire_nlilO1i0i_sel + ); + wire_nlilO1i0l_data <= ( nlillOi0O & "0" & wire_nlilO0OlO_dataout & wire_nlilO0O0O_dataout & wire_nlilO01Oi_dataout); + wire_nlilO1i0l_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1i0l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1i0l_data, + o => wire_nlilO1i0l_o, + sel => wire_nlilO1i0l_sel + ); + wire_nlilO1i1l_data <= ( nlillOiOO & "1" & "0" & wire_nlilO010i_dataout); + wire_nlilO1i1l_sel <= ( wire_nl11llO_w_lg_w_lg_nlillOlOi42755w42756w & niOiO1lli & nlillOlli & nlillOlii); + nlilO1i1l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlilO1i1l_data, + o => wire_nlilO1i1l_o, + sel => wire_nlilO1i1l_sel + ); + wire_nlilO1iii_data <= ( nlillOiii & "1" & wire_nlilO01Ol_dataout); + wire_nlilO1iii_sel <= ( niOiO1lil & niOiO1lli & nlillOlil); + nlilO1iii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilO1iii_data, + o => wire_nlilO1iii_o, + sel => wire_nlilO1iii_sel + ); + wire_nlilO1iil_data <= ( nlillOiil & "0" & wire_nlilO01OO_dataout); + wire_nlilO1iil_sel <= ( niOiO1lil & niOiO1lli & nlillOlil); + nlilO1iil : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilO1iil_data, + o => wire_nlilO1iil_o, + sel => wire_nlilO1iil_sel + ); + wire_nlilO1ill_data <= ( nlillO1Oi & nlillOlOl & wire_nlilO0OOi_dataout & wire_nlilO0OOi_dataout & wire_nlilO00ll_dataout); + wire_nlilO1ill_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1ill : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1ill_data, + o => wire_nlilO1ill_o, + sel => wire_nlilO1ill_sel + ); + wire_nlilO1ilO_data <= ( nlillO1Ol & nlilOilli & wire_nlilO0OOl_dataout & wire_nlilO0OOl_dataout & wire_nlilO00lO_dataout); + wire_nlilO1ilO_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1ilO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1ilO_data, + o => wire_nlilO1ilO_o, + sel => wire_nlilO1ilO_sel + ); + wire_nlilO1iOi_data <= ( nlillO1OO & nlilOilll & wire_nlilO0OOO_dataout & wire_nlilO0OOO_dataout & wire_nlilO00Oi_dataout); + wire_nlilO1iOi_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1iOi : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1iOi_data, + o => wire_nlilO1iOi_o, + sel => wire_nlilO1iOi_sel + ); + wire_nlilO1iOl_data <= ( nlillO01i & nlilOillO & wire_nlilOi11i_dataout & wire_nlilOi11i_dataout & wire_nlilO00Ol_dataout); + wire_nlilO1iOl_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1iOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1iOl_data, + o => wire_nlilO1iOl_o, + sel => wire_nlilO1iOl_sel + ); + wire_nlilO1iOO_data <= ( nlillO01l & nlilOilOi & wire_nlilOi11l_dataout & wire_nlilOi11l_dataout & wire_nlilO00OO_dataout); + wire_nlilO1iOO_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1iOO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1iOO_data, + o => wire_nlilO1iOO_o, + sel => wire_nlilO1iOO_sel + ); + wire_nlilO1l0i_data <= ( nlillO00O & nlilOiO1l & wire_nlilOi10O_dataout & wire_nlilOi10O_dataout & wire_nlilO0i0i_dataout); + wire_nlilO1l0i_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1l0i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1l0i_data, + o => wire_nlilO1l0i_o, + sel => wire_nlilO1l0i_sel + ); + wire_nlilO1l0l_data <= ( nlillO0ii & nlilOiO1O & wire_nlilOi1ii_dataout & wire_nlilOi1ii_dataout & wire_nlilO0i0l_dataout); + wire_nlilO1l0l_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1l0l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1l0l_data, + o => wire_nlilO1l0l_o, + sel => wire_nlilO1l0l_sel + ); + wire_nlilO1l0O_data <= ( nlillO0il & nlilOiO0i & wire_nlilOi1il_dataout & wire_nlilOi1il_dataout & wire_nlilO0i0O_dataout); + wire_nlilO1l0O_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1l0O : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1l0O_data, + o => wire_nlilO1l0O_o, + sel => wire_nlilO1l0O_sel + ); + wire_nlilO1l1i_data <= ( nlillO01O & nlilOilOl & wire_nlilOi11O_dataout & wire_nlilOi11O_dataout & wire_nlilO0i1i_dataout); + wire_nlilO1l1i_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1l1i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1l1i_data, + o => wire_nlilO1l1i_o, + sel => wire_nlilO1l1i_sel + ); + wire_nlilO1l1l_data <= ( nlillO00i & nlilOilOO & wire_nlilOi10i_dataout & wire_nlilOi10i_dataout & wire_nlilO0i1l_dataout); + wire_nlilO1l1l_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1l1l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1l1l_data, + o => wire_nlilO1l1l_o, + sel => wire_nlilO1l1l_sel + ); + wire_nlilO1l1O_data <= ( nlillO00l & nlilOiO1i & wire_nlilOi10l_dataout & wire_nlilOi10l_dataout & wire_nlilO0i1O_dataout); + wire_nlilO1l1O_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1l1O : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1l1O_data, + o => wire_nlilO1l1O_o, + sel => wire_nlilO1l1O_sel + ); + wire_nlilO1lii_data <= ( nlillO0iO & nlilOiO0l & wire_nlilOi1iO_dataout & wire_nlilOi1iO_dataout & wire_nlilO0iii_dataout); + wire_nlilO1lii_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1lii : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1lii_data, + o => wire_nlilO1lii_o, + sel => wire_nlilO1lii_sel + ); + wire_nlilO1lil_data <= ( nlillO0li & nlilOiO0O & wire_nlilOi1li_dataout & wire_nlilOi1li_dataout & wire_nlilO0iil_dataout); + wire_nlilO1lil_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1lil : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1lil_data, + o => wire_nlilO1lil_o, + sel => wire_nlilO1lil_sel + ); + wire_nlilO1liO_data <= ( nlillO0ll & nlilOiOii & wire_nlilOi1ll_dataout & wire_nlilOi1ll_dataout & wire_nlilO0iiO_dataout); + wire_nlilO1liO_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1liO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1liO_data, + o => wire_nlilO1liO_o, + sel => wire_nlilO1liO_sel + ); + wire_nlilO1lli_data <= ( nlillO0lO & nlilOiOil & wire_nlilOi1lO_dataout & wire_nlilOi1lO_dataout & wire_nlilO0ili_dataout); + wire_nlilO1lli_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1lli : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1lli_data, + o => wire_nlilO1lli_o, + sel => wire_nlilO1lli_sel + ); + wire_nlilO1lll_data <= ( nlillO0Oi & nlilOiOiO & wire_nlilOi1Oi_dataout & wire_nlilOi1Oi_dataout & wire_nlilO0ill_dataout); + wire_nlilO1lll_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1lll : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1lll_data, + o => wire_nlilO1lll_o, + sel => wire_nlilO1lll_sel + ); + wire_nlilO1llO_data <= ( nlillO0Ol & nlilOiOli & wire_nlilOi1Ol_dataout & wire_nlilOi1Ol_dataout & wire_nlilO0ilO_dataout); + wire_nlilO1llO_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1llO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1llO_data, + o => wire_nlilO1llO_o, + sel => wire_nlilO1llO_sel + ); + wire_nlilO1lOi_data <= ( nlillO0OO & nlilOiOll & wire_nlilOi1OO_dataout & wire_nlilOi1OO_dataout & wire_nlilO0iOi_dataout); + wire_nlilO1lOi_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1lOi : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1lOi_data, + o => wire_nlilO1lOi_o, + sel => wire_nlilO1lOi_sel + ); + wire_nlilO1lOl_data <= ( nlillOi1i & nlilOiOlO & wire_nlilOi01i_dataout & wire_nlilOi01i_dataout & wire_nlilO0iOl_dataout); + wire_nlilO1lOl_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1lOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1lOl_data, + o => wire_nlilO1lOl_o, + sel => wire_nlilO1lOl_sel + ); + wire_nlilO1lOO_data <= ( nlillOi1l & nlilOiOOi & wire_nlilOi01l_dataout & wire_nlilOi01l_dataout & wire_nlilO0iOO_dataout); + wire_nlilO1lOO_sel <= ( niOiO1liO & niOiO1lli & nlillOlli & nlillOliO & nlillOlil); + nlilO1lOO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1lOO_data, + o => wire_nlilO1lOO_o, + sel => wire_nlilO1lOO_sel + ); + wire_nlilO1O0i_data <= ( wire_nlilOi0ll_dataout & "0" & "1" & wire_nlilO0Oli_dataout & wire_nlilO0Oli_dataout & wire_nlilO00li_dataout & nlillOi0i); + wire_nlilO1O0i_sel <= ( nlillOlOi & nlillOllO & nlillOlll & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1O0i : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nlilO1O0i_data, + o => wire_nlilO1O0i_o, + sel => wire_nlilO1O0i_sel + ); + wire_nlilO1O0l_data <= ( wire_nlilOi0lO_dataout & "0" & wire_nlilOi01O_dataout & wire_nlilOi01O_dataout & wire_nlilO001l_dataout & wire_nlilO010l_dataout); + wire_nlilO1O0l_sel <= ( nlillOlOi & niOiO1lli & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1O0l : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nlilO1O0l_data, + o => wire_nlilO1O0l_o, + sel => wire_nlilO1O0l_sel + ); + wire_nlilO1O0O_data <= ( wire_nlilOi0Oi_dataout & "0" & wire_nlilOi00i_dataout & wire_nlilO0Oii_dataout & wire_nlilO001O_dataout & wire_nlilO010O_dataout); + wire_nlilO1O0O_sel <= ( nlillOlOi & niOiO1lli & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1O0O : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nlilO1O0O_data, + o => wire_nlilO1O0O_o, + sel => wire_nlilO1O0O_sel + ); + wire_nlilO1O1i_data <= ( nlillil1O & "1" & wire_nlilO0O1O_dataout & wire_nlilO001i_dataout & wire_nlilO011O_dataout); + wire_nlilO1O1i_sel <= ( wire_nl11llO_w_lg_w_lg_nlillOlOi42452w42453w & nlillOllO & nlillOliO & nlillOlil & nlillOlii); + nlilO1O1i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlilO1O1i_data, + o => wire_nlilO1O1i_o, + sel => wire_nlilO1O1i_sel + ); + wire_nlilO1O1O_data <= ( wire_nlilOi0li_dataout & "1" & "0" & wire_nlilO0OiO_dataout & wire_nlilO0O0i_dataout & wire_nlilO00iO_dataout & nlillOi1O); + wire_nlilO1O1O_sel <= ( nlillOlOi & nlillOllO & nlillOlll & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1O1O : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nlilO1O1O_data, + o => wire_nlilO1O1O_o, + sel => wire_nlilO1O1O_sel + ); + wire_nlilO1Oii_data <= ( wire_nlilOi0Ol_dataout & "0" & wire_nlilOi00l_dataout & wire_nlilO0Oil_dataout & wire_nlilO000i_dataout & wire_nlilO01ii_dataout); + wire_nlilO1Oii_sel <= ( nlillOlOi & niOiO1lli & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1Oii : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nlilO1Oii_data, + o => wire_nlilO1Oii_o, + sel => wire_nlilO1Oii_sel + ); + wire_nlilO1Oil_data <= ( wire_nlilOi0OO_dataout & "0" & "1" & wire_nlilOi00O_dataout & wire_nlilOi00O_dataout & wire_nlilO000l_dataout & wire_nlilO01il_dataout); + wire_nlilO1Oil_sel <= ( nlillOlOi & nlillOllO & nlillOlll & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1Oil : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nlilO1Oil_data, + o => wire_nlilO1Oil_o, + sel => wire_nlilO1Oil_sel + ); + wire_nlilO1OiO_data <= ( wire_nlilOii1i_dataout & "1" & "0" & wire_nlilOi0ii_dataout & wire_nlilOi0ii_dataout & wire_nlilO000O_dataout & wire_nlilO01iO_dataout); + wire_nlilO1OiO_sel <= ( nlillOlOi & nlillOllO & nlillOlll & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1OiO : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nlilO1OiO_data, + o => wire_nlilO1OiO_o, + sel => wire_nlilO1OiO_sel + ); + wire_nlilO1Oli_data <= ( wire_nlilOii1l_dataout & "0" & wire_nlilOi0il_dataout & wire_nlilOi0il_dataout & wire_nlilO00ii_dataout & wire_nlilO01li_dataout); + wire_nlilO1Oli_sel <= ( nlillOlOi & niOiO1lli & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1Oli : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nlilO1Oli_data, + o => wire_nlilO1Oli_o, + sel => wire_nlilO1Oli_sel + ); + wire_nlilO1Oll_data <= ( wire_nlilOii1O_dataout & "0" & wire_nlilOi0iO_dataout & wire_nlilOi0iO_dataout & wire_nlilO00il_dataout & wire_nlilO01ll_dataout); + wire_nlilO1Oll_sel <= ( nlillOlOi & niOiO1lli & nlillOlli & nlillOliO & nlillOlil & nlillOlii); + nlilO1Oll : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nlilO1Oll_data, + o => wire_nlilO1Oll_o, + sel => wire_nlilO1Oll_sel + ); + wire_nlilOOi0i_data <= ( "0" & wire_nlilOOilO_dataout & nlilOO0iO); + wire_nlilOOi0i_sel <= ( nlilOO0lO & nlilOO0ll & nlilOO0li); + nlilOOi0i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilOOi0i_data, + o => wire_nlilOOi0i_o, + sel => wire_nlilOOi0i_sel + ); + wire_nlilOOi0l_data <= ( wire_nlilOOlii_dataout & wire_nlilOOiOl_dataout & wire_nlilOOiiO_dataout); + wire_nlilOOi0l_sel <= ( nlilOO0lO & nlilOO0ll & nlilOO0li); + nlilOOi0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilOOi0l_data, + o => wire_nlilOOi0l_o, + sel => wire_nlilOOi0l_sel + ); + wire_nlilOOi0O_data <= ( wire_nlilOOlil_dataout & wire_nlilOOiOO_dataout & wire_nlilOOili_dataout); + wire_nlilOOi0O_sel <= ( nlilOO0lO & nlilOO0ll & nlilOO0li); + nlilOOi0O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilOOi0O_data, + o => wire_nlilOOi0O_o, + sel => wire_nlilOOi0O_sel + ); + wire_nlilOOi1O_data <= ( nlilOiOOl & wire_nlilOOiOi_dataout & wire_nlilOOiil_dataout); + wire_nlilOOi1O_sel <= ( nlilOO0lO & nlilOO0ll & nlilOO0li); + nlilOOi1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilOOi1O_data, + o => wire_nlilOOi1O_o, + sel => wire_nlilOOi1O_sel + ); + wire_nlilOOiii_data <= ( wire_nlilOOliO_dataout & wire_nlilOOl1i_dataout & wire_nlilOOill_dataout); + wire_nlilOOiii_sel <= ( nlilOO0lO & nlilOO0ll & nlilOO0li); + nlilOOiii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlilOOiii_data, + o => wire_nlilOOiii_o, + sel => wire_nlilOOiii_sel + ); + wire_nlli10li_data <= ( wire_nlli0OOl_dataout & nll0O0lO & wire_nlli011i_dataout & wire_nlli1l1l_dataout); + wire_nlli10li_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli10li : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli10li_data, + o => wire_nlli10li_o, + sel => wire_nlli10li_sel + ); + wire_nlli10ll_data <= ( wire_nlli0OOO_dataout & nll0O0Oi & wire_nlli011l_dataout & wire_nlli1l1O_dataout); + wire_nlli10ll_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli10ll : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli10ll_data, + o => wire_nlli10ll_o, + sel => wire_nlli10ll_sel + ); + wire_nlli10lO_data <= ( wire_nllii11i_dataout & nll0O0Ol & wire_nlli011O_dataout & wire_nlli1l0i_dataout); + wire_nlli10lO_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli10lO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli10lO_data, + o => wire_nlli10lO_o, + sel => wire_nlli10lO_sel + ); + wire_nlli10Oi_data <= ( wire_nllii11l_dataout & nll0O0OO & wire_nlli010i_dataout & wire_nlli1l0l_dataout); + wire_nlli10Oi_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli10Oi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli10Oi_data, + o => wire_nlli10Oi_o, + sel => wire_nlli10Oi_sel + ); + wire_nlli10Ol_data <= ( wire_nllii11O_dataout & nll0Oi1i & wire_nlli010l_dataout & wire_nlli1l0O_dataout); + wire_nlli10Ol_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli10Ol : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli10Ol_data, + o => wire_nlli10Ol_o, + sel => wire_nlli10Ol_sel + ); + wire_nlli10OO_data <= ( wire_nllii10i_dataout & nll0Oi1l & wire_nlli010O_dataout & wire_nlli1lii_dataout); + wire_nlli10OO_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli10OO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli10OO_data, + o => wire_nlli10OO_o, + sel => wire_nlli10OO_sel + ); + wire_nlli1i0i_data <= ( wire_nllii1il_dataout & nll0Oi0O & wire_nlli01li_dataout & wire_nlli1lll_dataout); + wire_nlli1i0i_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1i0i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1i0i_data, + o => wire_nlli1i0i_o, + sel => wire_nlli1i0i_sel + ); + wire_nlli1i0l_data <= ( wire_nllii1iO_dataout & nll0Oiii & wire_nlli01ll_dataout & wire_nlli01ll_dataout); + wire_nlli1i0l_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1i0l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1i0l_data, + o => wire_nlli1i0l_o, + sel => wire_nlli1i0l_sel + ); + wire_nlli1i0O_data <= ( wire_nllii1li_dataout & nll0Ol1i & wire_nlli001l_dataout & wire_nlli001l_dataout); + wire_nlli1i0O_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1i0O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1i0O_data, + o => wire_nlli1i0O_o, + sel => wire_nlli1i0O_sel + ); + wire_nlli1i1i_data <= ( wire_nllii10l_dataout & nll0Oi1O & wire_nlli01ii_dataout & wire_nlli1lil_dataout); + wire_nlli1i1i_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1i1i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1i1i_data, + o => wire_nlli1i1i_o, + sel => wire_nlli1i1i_sel + ); + wire_nlli1i1l_data <= ( wire_nllii10O_dataout & nll0Oi0i & wire_nlli01il_dataout & wire_nlli1liO_dataout); + wire_nlli1i1l_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1i1l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1i1l_data, + o => wire_nlli1i1l_o, + sel => wire_nlli1i1l_sel + ); + wire_nlli1i1O_data <= ( wire_nllii1ii_dataout & nll0Oi0l & wire_nlli01iO_dataout & wire_nlli1lli_dataout); + wire_nlli1i1O_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1i1O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1i1O_data, + o => wire_nlli1i1O_o, + sel => wire_nlli1i1O_sel + ); + wire_nlli1iii_data <= ( niOO01i1l & "0" & wire_nlli01lO_dataout); + wire_nlli1iii_sel <= ( nll0Oill & wire_nl1000i_w_lg_nll0Oili5471w & nll0OiiO); + nlli1iii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlli1iii_data, + o => wire_nlli1iii_o, + sel => wire_nlli1iii_sel + ); + wire_nlli1iiO_data <= ( wire_nllii1ll_dataout & wire_nlli0Oli_dataout & wire_nlli001O_dataout & wire_nlli1lOi_dataout); + wire_nlli1iiO_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1iiO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1iiO_data, + o => wire_nlli1iiO_o, + sel => wire_nlli1iiO_sel + ); + wire_nlli1ili_data <= ( wire_nllii1lO_dataout & wire_nlli0Oll_dataout & wire_nlli000i_dataout & wire_nlli1lOl_dataout); + wire_nlli1ili_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1ili : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1ili_data, + o => wire_nlli1ili_o, + sel => wire_nlli1ili_sel + ); + wire_nlli1ill_data <= ( wire_nllii1Oi_dataout & wire_nlli0OlO_dataout & wire_nlli000l_dataout & wire_nlli1lOO_dataout); + wire_nlli1ill_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1ill : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1ill_data, + o => wire_nlli1ill_o, + sel => wire_nlli1ill_sel + ); + wire_nlli1ilO_data <= ( wire_nllii1Ol_dataout & wire_nlli0OOi_dataout & wire_nlli000O_dataout & wire_nlli1O1i_dataout); + wire_nlli1ilO_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1ilO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1ilO_data, + o => wire_nlli1ilO_o, + sel => wire_nlli1ilO_sel + ); + wire_nlli1iOi_data <= ( wire_nllii1OO_dataout & nll0Ol1l & wire_nlli01Oi_dataout & wire_nlli01Oi_dataout); + wire_nlli1iOi_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1iOi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1iOi_data, + o => wire_nlli1iOi_o, + sel => wire_nlli1iOi_sel + ); + wire_nlli1iOl_data <= ( wire_nllii01i_dataout & nll0Ol1O & wire_nlli01Ol_dataout & wire_nlli01Ol_dataout); + wire_nlli1iOl_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1iOl : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1iOl_data, + o => wire_nlli1iOl_o, + sel => wire_nlli1iOl_sel + ); + wire_nlli1iOO_data <= ( wire_nllii01l_dataout & nll0Ol0i & wire_nlli01OO_dataout & wire_nlli01OO_dataout); + wire_nlli1iOO_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1iOO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1iOO_data, + o => wire_nlli1iOO_o, + sel => wire_nlli1iOO_sel + ); + wire_nlli1l1i_data <= ( "0" & nll0OilO & wire_nlli001i_dataout & wire_nlli1llO_dataout); + wire_nlli1l1i_sel <= ( nll0Oill & nll0Oili & nll0OiiO & nll0Oiil); + nlli1l1i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlli1l1i_data, + o => wire_nlli1l1i_o, + sel => wire_nlli1l1i_sel + ); + wire_nlll101l_data <= ( "0" & wire_nlll01lO_dataout & wire_nlll1lOO_dataout); + wire_nlll101l_sel <= ( wire_nl11llO_w_lg_nlliO01l5197w & nlliO01i & nlliO1OO); + nlll101l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll101l_data, + o => wire_nlll101l_o, + sel => wire_nlll101l_sel + ); + wire_nlll11OO_data <= ( "0" & wire_nlll01ll_dataout & wire_nlll1lii_dataout); + wire_nlll11OO_sel <= ( wire_nl11llO_w_lg_nlliO01l5207w & nlliO01i & nlliO1Ol); + nlll11OO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll11OO_data, + o => wire_nlll11OO_o, + sel => wire_nlll11OO_sel + ); + wire_nlll1iO0l_data <= ( wire_nlll1ll0l_dataout & "0" & wire_nlll1li0i_dataout & wire_nlll1l01O_dataout & wire_nlll1l11i_dataout); + wire_nlll1iO0l_sel <= ( nlll1ilil & niOiOl10O & nlll1il0O & nlll1il0i & nlll1il1O); + nlll1iO0l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlll1iO0l_data, + o => wire_nlll1iO0l_o, + sel => wire_nlll1iO0l_sel + ); + wire_nlll1iO0O_data <= ( wire_nlll1ll0O_dataout & "0" & wire_nlll1li0l_dataout & wire_nlll1l00i_dataout & wire_nlll1l11l_dataout); + wire_nlll1iO0O_sel <= ( nlll1ilil & niOiOl10O & nlll1il0O & nlll1il0i & nlll1il1O); + nlll1iO0O : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlll1iO0O_data, + o => wire_nlll1iO0O_o, + sel => wire_nlll1iO0O_sel + ); + wire_nlll1iO1O_data <= ( nlll11O1l & wire_nlll1li1O_dataout & "0" & wire_nlll1iOOO_dataout); + wire_nlll1iO1O_sel <= ( wire_nl11llO_w_lg_w_lg_w_lg_nlll1ilil34878w34879w34880w & nlll1il0l & nlll1il0i & nlll1il1O); + nlll1iO1O : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlll1iO1O_data, + o => wire_nlll1iO1O_o, + sel => wire_nlll1iO1O_sel + ); + wire_nlll1iOi_data <= ( wire_nlll0iil_dataout & "0" & wire_nlll1O1i_dataout & wire_nlll1lil_dataout); + wire_nlll1iOi_sel <= ( nlliO01l & nlliO01i & nlliO1OO & nlliO1Ol); + nlll1iOi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlll1iOi_data, + o => wire_nlll1iOi_o, + sel => wire_nlll1iOi_sel + ); + wire_nlll1iOii_data <= ( wire_nlll1llii_dataout & "0" & wire_nlll1li0O_dataout & nlilOO0iO & wire_nlll1l00l_dataout & wire_nlll1l11O_dataout); + wire_nlll1iOii_sel <= ( nlll1ilil & wire_nl1000i_w_lg_nlll1ilii34837w & nlll1il0O & nlll1il0l & nlll1il0i & nlll1il1O); + nlll1iOii : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nlll1iOii_data, + o => wire_nlll1iOii_o, + sel => wire_nlll1iOii_sel + ); + wire_nlll1iOiO_data <= ( wire_nlll1llil_dataout & "0" & wire_nlll1liii_dataout & wire_nlll1l00O_dataout & wire_nlll1l10i_dataout); + wire_nlll1iOiO_sel <= ( nlll1ilil & niOiOl10O & nlll1il0O & nlll1il0i & nlll1il1O); + nlll1iOiO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlll1iOiO_data, + o => wire_nlll1iOiO_o, + sel => wire_nlll1iOiO_sel + ); + wire_nlll1iOl_data <= ( wire_nlll0iiO_dataout & niOO01liO & wire_nlll1O1l_dataout & wire_nlll1liO_dataout); + wire_nlll1iOl_sel <= ( nlliO01l & nlliO01i & nlliO1OO & nlliO1Ol); + nlll1iOl : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlll1iOl_data, + o => wire_nlll1iOl_o, + sel => wire_nlll1iOl_sel + ); + wire_nlll1iOli_data <= ( wire_nlll1lliO_dataout & nlilOO0iO & wire_nlll1liil_dataout & "0" & wire_nlll1l0ii_dataout & wire_nlll1l10l_dataout); + wire_nlll1iOli_sel <= ( nlll1ilil & nlll1ilii & nlll1il0O & wire_nl1000i_w_lg_nlll1il0l34806w & nlll1il0i & nlll1il1O); + nlll1iOli : oper_selector + GENERIC MAP ( + width_data => 6, + width_sel => 6 + ) + PORT MAP ( + data => wire_nlll1iOli_data, + o => wire_nlll1iOli_o, + sel => wire_nlll1iOli_sel + ); + wire_nlll1iOlO_data <= ( wire_nlll1llli_dataout & "0" & wire_nlll1liiO_dataout & wire_nlll1l0il_dataout & wire_nlll1l10O_dataout); + wire_nlll1iOlO_sel <= ( nlll1ilil & niOiOl10O & nlll1il0O & nlll1il0i & nlll1il1O); + nlll1iOlO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlll1iOlO_data, + o => wire_nlll1iOlO_o, + sel => wire_nlll1iOlO_sel + ); + wire_nlll1iOO_data <= ( wire_nlll0ili_dataout & "0" & wire_nlll1O1O_dataout & wire_nlll1lli_dataout); + wire_nlll1iOO_sel <= ( nlliO01l & nlliO01i & nlliO1OO & nlliO1Ol); + nlll1iOO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlll1iOO_data, + o => wire_nlll1iOO_o, + sel => wire_nlll1iOO_sel + ); + wire_nlll1iOOl_data <= ( wire_nlll1llll_dataout & wire_nl1000i_w_lg_nlilOO0iO5228w & wire_nlll1lili_dataout & wire_nl1000i_w_lg_nlilOO0iO5228w & wire_nlll1l0iO_dataout & wire_nlll1l1ii_dataout & "1"); + wire_nlll1iOOl_sel <= ( nlll1ilil & nlll1ilii & nlll1il0O & nlll1il0l & nlll1il0i & nlll1il1O & nlll1il1l); + nlll1iOOl : oper_selector + GENERIC MAP ( + width_data => 7, + width_sel => 7 + ) + PORT MAP ( + data => wire_nlll1iOOl_data, + o => wire_nlll1iOOl_o, + sel => wire_nlll1iOOl_sel + ); + wire_nlll1l0i_data <= ( wire_nlll0iOi_dataout & wire_nlll01Oi_dataout & wire_nlll1lOl_dataout & nllillOi); + wire_nlll1l0i_sel <= ( nlliO01l & nlliO01i & nlliO1OO & nlliO1Ol); + nlll1l0i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlll1l0i_data, + o => wire_nlll1l0i_o, + sel => wire_nlll1l0i_sel + ); + wire_nlll1l0l_data <= ( wire_nlll0iOl_dataout & nllillOl & wire_w_lg_niOO01lii5127w & nli1i1ll); + wire_nlll1l0l_sel <= ( nlliO01l & nlliO01i & nlliO1OO & nlliO1Ol); + nlll1l0l : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlll1l0l_data, + o => wire_nlll1l0l_o, + sel => wire_nlll1l0l_sel + ); + wire_nlll1l1i_data <= ( wire_nlll0ill_dataout & wire_w_lg_niOO01liO5159w & wire_nlll1O0i_dataout & wire_nlll1lll_dataout); + wire_nlll1l1i_sel <= ( nlliO01l & nlliO01i & nlliO1OO & nlliO1Ol); + nlll1l1i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlll1l1i_data, + o => wire_nlll1l1i_o, + sel => wire_nlll1l1i_sel + ); + wire_nlll1l1l_data <= ( wire_nlll0ilO_dataout & "0" & nlliO1Oi); + wire_nlll1l1l_sel <= ( nlliO01l & nlliO01i & wire_nl1000i_w_lg_nlliO1OO5141w); + nlll1l1l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll1l1l_data, + o => wire_nlll1l1l_o, + sel => wire_nlll1l1l_sel + ); + wire_nlll1OOlO_data <= ( wire_nlll011ii_dataout & wire_nlll0111O_dataout & wire_nlll1OOOO_dataout); + wire_nlll1OOlO_sel <= ( nlll1OOii & nlll1lOOO & nlll1OO0O); + nlll1OOlO : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll1OOlO_data, + o => wire_nlll1OOlO_o, + sel => wire_nlll1OOlO_sel + ); + wire_nlll1OOOi_data <= ( wire_nlll011il_dataout & wire_nlll0110i_dataout & wire_nlll0111i_dataout); + wire_nlll1OOOi_sel <= ( nlll1OOii & nlll1lOOO & nlll1OO0O); + nlll1OOOi : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll1OOOi_data, + o => wire_nlll1OOOi_o, + sel => wire_nlll1OOOi_sel + ); + wire_nlll1OOOl_data <= ( wire_nlll011iO_dataout & wire_nlll0110l_dataout & wire_nlll0111l_dataout); + wire_nlll1OOOl_sel <= ( nlll1OOii & nlll1lOOO & nlll1OO0O); + nlll1OOOl : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlll1OOOl_data, + o => wire_nlll1OOOl_o, + sel => wire_nlll1OOOl_sel + ); + wire_nlO00O0li_data <= ( wire_nlO00OOOi_dataout & "0" & wire_nlO00Oili_dataout); + wire_nlO00O0li_sel <= ( nlO00O11l & niOiOOi0i & nlO00lOOO); + nlO00O0li : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00O0li_data, + o => wire_nlO00O0li_o, + sel => wire_nlO00O0li_sel + ); + wire_nlO00O0ll_data <= ( wire_nlO00OOOl_dataout & wire_nlO00OOil_dataout & wire_nlO00Oill_dataout & "0"); + wire_nlO00O0ll_sel <= ( nlO00O11l & nlO00O11i & nlO00lOOO & niOiOOi1O); + nlO00O0ll : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlO00O0ll_data, + o => wire_nlO00O0ll_o, + sel => wire_nlO00O0ll_sel + ); + wire_nlO00O0lO_data <= ( wire_nlO00OOOO_dataout & niOl11l0l & wire_nlO00OilO_dataout & "0"); + wire_nlO00O0lO_sel <= ( nlO00O11l & nlO00O11i & nlO00lOOO & niOiOOi1O); + nlO00O0lO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlO00O0lO_data, + o => wire_nlO00O0lO_o, + sel => wire_nlO00O0lO_sel + ); + wire_nlO00O0Oi_data <= ( wire_nlO0i111i_dataout & wire_nlO00OOiO_dataout & wire_nlO00OiOi_dataout & "0"); + wire_nlO00O0Oi_sel <= ( nlO00O11l & nlO00O11i & nlO00lOOO & niOiOOi1O); + nlO00O0Oi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlO00O0Oi_data, + o => wire_nlO00O0Oi_o, + sel => wire_nlO00O0Oi_sel + ); + wire_nlO00O0Ol_data <= ( wire_nlO0i111l_dataout & "0" & wire_nlO00OiOl_dataout); + wire_nlO00O0Ol_sel <= ( nlO00O11l & niOiOOi0i & nlO00lOOO); + nlO00O0Ol : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00O0Ol_data, + o => wire_nlO00O0Ol_o, + sel => wire_nlO00O0Ol_sel + ); + wire_nlO00Oi0l_data <= ( "0" & nlO00lOiO & wire_nlO00OiiO_dataout); + wire_nlO00Oi0l_sel <= ( nlO00O11l & niOiOOi0i & nlO00lOOO); + nlO00Oi0l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00Oi0l_data, + o => wire_nlO00Oi0l_o, + sel => wire_nlO00Oi0l_sel + ); + wire_nlO00Oi0O_data <= ( "0" & nlO00lOli & "1"); + wire_nlO00Oi0O_sel <= ( nlO00O11l & wire_nl1000i_w_lg_w_lg_nlO00O11i29542w29543w & wire_nl1000i_w_lg_nlO00lOOl29539w); + nlO00Oi0O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00Oi0O_data, + o => wire_nlO00Oi0O_o, + sel => wire_nlO00Oi0O_sel + ); + wire_nlO00Oi1i_data <= ( wire_nlO0i111O_dataout & "0" & wire_nlO00OiOO_dataout & "1"); + wire_nlO00Oi1i_sel <= ( nlO00O11l & nlO00O11i & nlO00lOOO & niOiOOi1O); + nlO00Oi1i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlO00Oi1i_data, + o => wire_nlO00Oi1i_o, + sel => wire_nlO00Oi1i_sel + ); + wire_nlO00Oi1O_data <= ( "0" & nlO1Ol1li & "1"); + wire_nlO00Oi1O_sel <= ( nlO00O11l & wire_nl1000i_w_lg_w_lg_w_lg_nlO00O11i29542w29563w29564w & nlO00lOOi); + nlO00Oi1O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO00Oi1O_data, + o => wire_nlO00Oi1O_o, + sel => wire_nlO00Oi1O_sel + ); + wire_nlO0O10i_data <= ( wire_nlO0Oi0O_dataout & wire_nlO0O0Oi_dataout & wire_nlO0O1li_dataout); + wire_nlO0O10i_sel <= ( nlO0lllO & nlO0llll & nlO0llli); + nlO0O10i : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0O10i_data, + o => wire_nlO0O10i_o, + sel => wire_nlO0O10i_sel + ); + wire_nlO0O10l_data <= ( wire_nlO0Oiii_dataout & wire_nlO0O0Ol_dataout & wire_nlO0O1ll_dataout); + wire_nlO0O10l_sel <= ( nlO0lllO & nlO0llll & nlO0llli); + nlO0O10l : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0O10l_data, + o => wire_nlO0O10l_o, + sel => wire_nlO0O10l_sel + ); + wire_nlO0O10O_data <= ( wire_nlO0Oiil_dataout & wire_nlO0O0OO_dataout & wire_nlO0O1lO_dataout); + wire_nlO0O10O_sel <= ( nlO0lllO & nlO0llll & nlO0llli); + nlO0O10O : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0O10O_data, + o => wire_nlO0O10O_o, + sel => wire_nlO0O10O_sel + ); + wire_nlO0O1ii_data <= ( "0" & wire_nlO0O0ll_dataout & wire_nlO0O1iO_dataout); + wire_nlO0O1ii_sel <= ( nlO0lllO & nlO0llll & nlO0llli); + nlO0O1ii : oper_selector + GENERIC MAP ( + width_data => 3, + width_sel => 3 + ) + PORT MAP ( + data => wire_nlO0O1ii_data, + o => wire_nlO0O1ii_o, + sel => wire_nlO0O1ii_sel + ); + wire_nlOll0OOi_data <= ( wire_nlOlliilO_dataout & wire_nlOlliiii_dataout & wire_nlOlli0Ol_dataout & wire_nlOlli1li_dataout & wire_nlOlli11O_dataout); + wire_nlOll0OOi_sel <= ( nlOll0Oii & nlOll0O0O & nlOll0O0l & nlOll0O0i & nlOll000O); + nlOll0OOi : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlOll0OOi_data, + o => wire_nlOll0OOi_o, + sel => wire_nlOll0OOi_sel + ); + wire_nlOll0OOl_data <= ( wire_nlOlliiOi_dataout & wire_nlOlliiil_dataout & wire_nlOlli0OO_dataout & wire_nlOlli1ll_dataout & wire_nlOlli10i_dataout); + wire_nlOll0OOl_sel <= ( nlOll0Oii & nlOll0O0O & nlOll0O0l & nlOll0O0i & nlOll000O); + nlOll0OOl : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlOll0OOl_data, + o => wire_nlOll0OOl_o, + sel => wire_nlOll0OOl_sel + ); + wire_nlOll0OOO_data <= ( wire_nlOlliiOl_dataout & wire_nlOlliiiO_dataout & wire_nlOllii1i_dataout & wire_nlOlli1lO_dataout & wire_nlOlli10l_dataout); + wire_nlOll0OOO_sel <= ( nlOll0Oii & nlOll0O0O & nlOll0O0l & nlOll0O0i & nlOll000O); + nlOll0OOO : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlOll0OOO_data, + o => wire_nlOll0OOO_o, + sel => wire_nlOll0OOO_sel + ); + wire_nlOlli11i_data <= ( wire_nlOlliiOO_dataout & wire_nlOlliili_dataout & wire_nlOllii1l_dataout & wire_nlOlli1Oi_dataout & wire_nlOlli10O_dataout); + wire_nlOlli11i_sel <= ( nlOll0Oii & nlOll0O0O & nlOll0O0l & nlOll0O0i & nlOll000O); + nlOlli11i : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlOlli11i_data, + o => wire_nlOlli11i_o, + sel => wire_nlOlli11i_sel + ); + wire_nlOlli11l_data <= ( wire_nlOllil1i_dataout & wire_nlOlliill_dataout & wire_nlOllii1O_dataout & wire_nlOlli1Ol_dataout & wire_nlOlli1ii_dataout); + wire_nlOlli11l_sel <= ( nlOll0Oii & nlOll0O0O & nlOll0O0l & nlOll0O0i & nlOll000O); + nlOlli11l : oper_selector + GENERIC MAP ( + width_data => 5, + width_sel => 5 + ) + PORT MAP ( + data => wire_nlOlli11l_data, + o => wire_nlOlli11l_o, + sel => wire_nlOlli11l_sel + ); + wire_nlOllllOi_data <= ( wire_nlOllO01l_dataout & wire_nlOllO1il_dataout & wire_nlOlllO0O_dataout & wire_nlOlllO1l_dataout); + wire_nlOllllOi_sel <= ( nlOllllii & nlOllll0O & nlOllll0l & nlOlliOOO); + nlOllllOi : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOllllOi_data, + o => wire_nlOllllOi_o, + sel => wire_nlOllllOi_sel + ); + wire_nlOllllOl_data <= ( wire_nlOllO01O_dataout & wire_nlOllO1iO_dataout & wire_nlOlllOii_dataout & wire_nlOlllO1O_dataout); + wire_nlOllllOl_sel <= ( nlOllllii & nlOllll0O & nlOllll0l & nlOlliOOO); + nlOllllOl : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOllllOl_data, + o => wire_nlOllllOl_o, + sel => wire_nlOllllOl_sel + ); + wire_nlOllllOO_data <= ( wire_nlOllO00i_dataout & wire_nlOllO1li_dataout & wire_nlOlllOil_dataout & wire_nlOlllO0i_dataout); + wire_nlOllllOO_sel <= ( nlOllllii & nlOllll0O & nlOllll0l & nlOlliOOO); + nlOllllOO : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOllllOO_data, + o => wire_nlOllllOO_o, + sel => wire_nlOllllOO_sel + ); + wire_nlOlllO1i_data <= ( wire_nlOllO00l_dataout & wire_nlOllO1ll_dataout & wire_nlOlllOiO_dataout & wire_nlOlllO0l_dataout); + wire_nlOlllO1i_sel <= ( nlOllllii & nlOllll0O & nlOllll0l & nlOlliOOO); + nlOlllO1i : oper_selector + GENERIC MAP ( + width_data => 4, + width_sel => 4 + ) + PORT MAP ( + data => wire_nlOlllO1i_data, + o => wire_nlOlllO1i_o, + sel => wire_nlOlllO1i_sel + ); + wire_n0OOO0O_w_lg_w_q_range2464w2565w(0) <= NOT wire_n0OOO0O_w_q_range2464w(0); + wire_n0OOO0O_data <= ( tx_err_vc1 & tx_sop_vc1_0 & tx_sop_vc1_1 & tx_eop_vc1_0 & niOO0O1lO & tx_data_vc1_0(63 DOWNTO 0) & tx_data_vc1_1(63 DOWNTO 0)); + wire_n0OOO0O_rdaddress <= ( niOO0iO1i & niOO0iO1l & niOO0iO0l & niOO0iOii); + wire_n0OOO0O_wraddress <= ( ni10Oii & ni10O0O & ni10O0l & ni10O0i); + wire_n0OOO0O_w_q_range2445w(0) <= wire_n0OOO0O_q(128); + wire_n0OOO0O_w_q_range2448w(0) <= wire_n0OOO0O_q(129); + wire_n0OOO0O_w_q_range2464w(0) <= wire_n0OOO0O_q(94); + n0OOO0O : cycloneiv_pciehip_pciexp_dcfiforam + GENERIC MAP ( + addr_width => 4, + data_width => 133 + ) + PORT MAP ( + data => wire_n0OOO0O_data, + q => wire_n0OOO0O_q, + rdaddress => wire_n0OOO0O_rdaddress, + rdclock => wire_niO0011l_dataout, + wraddress => wire_n0OOO0O_wraddress, + wrclock => wire_niO01OOO_dataout, + wren => tx_valid_vc1 + ); + wire_n1llO0O_data <= ( wire_n0010iO_dataout & wire_n001ili_dataout & wire_n001iiO_dataout & wire_n001iil_dataout & wire_n001iii_dataout & wire_n001i0O_dataout & wire_n001i0l_dataout & wire_n001i0i_dataout & wire_n001i1O_dataout & wire_n001i1l_dataout & wire_n001i1i_dataout & wire_n0010OO_dataout & wire_n0010Ol_dataout & wire_n0010Oi_dataout & wire_n0010lO_dataout & wire_n0010ll_dataout & wire_n0010li_dataout & wire_n001l1O_dataout & wire_n001l1l_dataout & wire_n001l1i_dataout & wire_n001iOO_dataout & wire_n001iOl_dataout & wire_n001iOi_dataout & wire_n001ilO_dataout & wire_n001ill_dataout & wire_ni1lOlO_w_lg_w_lg_n0OiOOl3227w3968w & wire_n00010i_dataout & wire_n00010l_dataout & wire_n0001iO_dataout & wire_n0001li_dataout & wire_n0i0i0O_dataout & wire_n0i0i0l_dataout & wire_n0i0i0i_dataout & wire_n0i0i1O_dataout & wire_n0i0i1l_dataout & wire_n0i0i1i_dataout & wire_n0i00OO_dataout & wire_n0i00Ol_dataout & wire_n0i00Oi_dataout & wire_n0i00lO_dataout & wire_n0i00ll_dataout & wire_n0i00li_dataout & wire_n0i00iO_dataout & wire_n0i00il_dataout & wire_n0i00ii_dataout & wire_n0i000O_dataout & wire_n0i000l_dataout & wire_n0i000i_dataout & wire_n0i001O_dataout & wire_n0i001l_dataout & wire_n0i001i_dataout & wire_n0i01OO_dataout & wire_n0i01Ol_dataout & wire_n0i01Oi_dataout & wire_n0i01lO_dataout & wire_n0i01ll_dataout & wire_n0i01li_dataout & wire_n0i01iO_dataout & wire_n0i01il_dataout & wire_n0i01ii_dataout & wire_n0i010O_dataout & wire_n0i010l_dataout & wire_n0i010i_dataout & wire_n0i011O_dataout & wire_n0i011l_dataout & wire_n0i011i_dataout & wire_n0i1OOO_dataout & wire_n0i1OOl_dataout & wire_n0i1OOi_dataout & wire_n0i1OlO_dataout & wire_n0i1Oll_dataout & wire_n0i1Oli_dataout & wire_n0i1OiO_dataout & wire_n0i1Oil_dataout & wire_n0i1Oii_dataout & wire_n0i1O0O_dataout & wire_n0i1O0l_dataout & wire_n0i1O0i_dataout & wire_n0i1O1O_dataout & wire_n0i1O1l_dataout & wire_n0i1O1i_dataout & wire_n0i1lOO_dataout & wire_n0i1lOl_dataout & wire_n0i1lOi_dataout & wire_n0i1llO_dataout & wire_n0i1lll_dataout & wire_n0i1lli_dataout & wire_n0i1liO_dataout + & wire_n0i1lil_dataout & wire_n0i1lii_dataout & wire_n0i1l0O_dataout & wire_n0i1l0l_dataout & wire_n0i1l0i_dataout & wire_n0i1l1O_dataout & wire_n000OOl_dataout & wire_n000OOi_dataout & wire_n000OlO_dataout & wire_n000Oll_dataout & wire_n000Oli_dataout & wire_n000OiO_dataout & wire_n000Oil_dataout & wire_n000Oii_dataout & wire_n000O0O_dataout & wire_n000O0l_dataout & wire_n000O0i_dataout & wire_n000O1O_dataout & wire_n000O1l_dataout & wire_n000O1i_dataout & wire_n000lOO_dataout & wire_n000lOl_dataout & wire_n000lOi_dataout & wire_n000llO_dataout & wire_n000lll_dataout & wire_n000lli_dataout & wire_n000liO_dataout & wire_n000lil_dataout & wire_n000lii_dataout & wire_n000l0O_dataout & wire_n000l0l_dataout & wire_n000l0i_dataout & wire_n000l1O_dataout & wire_n000l1l_dataout & wire_n000l1i_dataout & wire_n000iOO_dataout & wire_n000iOl_dataout & wire_n000iOi_dataout & wire_n000ilO_dataout & wire_n000ill_dataout & wire_n000ili_dataout & wire_n000iiO_dataout & wire_n000iil_dataout & wire_n000iii_dataout & wire_n000i0O_dataout & wire_n000i0l_dataout & wire_n000i0i_dataout & wire_n000i1O_dataout & wire_n000i1l_dataout & wire_n000i1i_dataout & wire_n0000OO_dataout & wire_n0000Ol_dataout & wire_n0000Oi_dataout & wire_n0000lO_dataout & wire_n0000ll_dataout & wire_n0000li_dataout & wire_n0000iO_dataout & wire_n0000il_dataout & wire_n0000ii_dataout & wire_n00000O_dataout & wire_n00000l_dataout & wire_n00000i_dataout & wire_n00001O_dataout & wire_n00001l_dataout & wire_n00001i_dataout & wire_n0001OO_dataout & wire_n0001Ol_dataout & wire_n0001Oi_dataout & wire_n0001lO_dataout & wire_n0001ll_dataout); + wire_n1llO0O_rdaddress <= ( niOO00OlO & niOO00OOi & niOO0i11i & niOO0i11O); + wire_n1llO0O_wraddress <= ( n1O1Oll & n1O1Oli & n1O1OiO & n1O1Oil); + n1llO0O : cycloneiv_pciehip_pciexp_dcfiforam + GENERIC MAP ( + addr_width => 4, + data_width => 158 + ) + PORT MAP ( + data => wire_n1llO0O_data, + q => wire_n1llO0O_q, + rdaddress => wire_n1llO0O_rdaddress, + rdclock => wire_niO01OOO_dataout, + wraddress => wire_n1llO0O_wraddress, + wrclock => wire_niO0011l_dataout, + wren => wire_n1O0l0l_dataout + ); + wire_nl01iilO_data <= ( nl0OiO0l & nl0OiO0i & nl0OiO1O & nl0OiO1l & nl0OiO1i & nl0OilOO & nl0OilOl & nl0OilOi & nl0OillO & nl0Oilll & nl0Oilli & nl0OiliO & nl0Oilil & nl0Oilii & nl0Oil0O & nl0Oil0l & nl0Oil0i & nl0Oil1O & nl0Oil1l & nl0Oil1i & nl0OiiOO & nl0OiiOl & nl0OiiOi & nl0OiilO & nl0Oiill & nl0Oiili & nl0O1l0O & wire_nl0Oii0O_dataout & wire_nl0Oii0l_dataout & wire_nl0Oii0i_dataout & wire_nl0Oii1O_dataout & wire_nl0Oii1l_dataout & wire_nl0Oii1i_dataout & wire_nl0Oi0OO_dataout & wire_nl0Oi0Ol_dataout & wire_nl0Oi0Oi_dataout & wire_nl0Oi0lO_dataout & wire_nl0Oi0ll_dataout & wire_nl0Oi0li_dataout & wire_nl0Oi0iO_dataout & wire_nl0Oi0il_dataout & wire_nl0Oi0ii_dataout & wire_nl0Oi00O_dataout & wire_nl0Oi00l_dataout & wire_nl0Oi00i_dataout & wire_nl0Oi01O_dataout & wire_nl0Oi01l_dataout & wire_nl0Oi01i_dataout & wire_nl0Oi1OO_dataout & wire_nl0Oi1Ol_dataout & wire_nl0Oi1Oi_dataout & wire_nl0Oi1lO_dataout & wire_nl0Oi1ll_dataout & wire_nl0Oi1li_dataout); + wire_nl01iilO_rdaddress <= ( nl01il1l & nl01illl); + wire_nl01iilO_wraddress <= ( nl01ilOi & nl01illO); + nl01iilO : cycloneiv_pciehip_pciexp_dcfiforam + GENERIC MAP ( + addr_width => 2, + data_width => 54 + ) + PORT MAP ( + data => wire_nl01iilO_data, + q => wire_nl01iilO_q, + rdaddress => wire_nl01iilO_rdaddress, + rdclock => pld_clk, + wraddress => wire_nl01iilO_wraddress, + wrclock => core_clk, + wren => niOO1Oi1l + ); + wire_nli110ii_data <= ( wire_nliiillO_dataout & wire_nliiiOOl_dataout & wire_nliiiOOi_dataout & wire_nliiiOlO_dataout & wire_nliiiOll_dataout & wire_nliiiOli_dataout & wire_nliiiOiO_dataout & wire_nliiiOil_dataout & wire_nliiiOii_dataout & wire_nliiiO0O_dataout & wire_nliiiO0l_dataout & wire_nliiiO0i_dataout & wire_nliiiO1O_dataout & wire_nliiiO1l_dataout & wire_nliiiO1i_dataout & wire_nliiilOO_dataout & wire_nliiilOl_dataout & wire_nliil1ii_dataout & wire_nliil10O_dataout & wire_nliil10l_dataout & wire_nliil10i_dataout & wire_nliil11O_dataout & wire_nliil11l_dataout & wire_nliil11i_dataout & wire_nliiiOOO_dataout & wire_nl1000i_w_lg_w_lg_nllillOl5080w6320w & wire_nliiliil_dataout & wire_nliilili_dataout & wire_nliiliOl_dataout & wire_nliiliOO_dataout & wire_nlilOO1l_dataout & wire_nlilOO1i_dataout & wire_nlilOlOO_dataout & wire_nlilOlOl_dataout & wire_nlilOlOi_dataout & wire_nlilOllO_dataout & wire_nlilOlll_dataout & wire_nlilOlli_dataout & wire_nlilOliO_dataout & wire_nlilOlil_dataout & wire_nlilOlii_dataout & wire_nlilOl0O_dataout & wire_nlilOl0l_dataout & wire_nlilOl0i_dataout & wire_nlilOl1O_dataout & wire_nlilOl1l_dataout & wire_nlilOl1i_dataout & wire_nlilOiOO_dataout & wire_nlilOiOl_dataout & wire_nlilOiOi_dataout & wire_nlilOilO_dataout & wire_nlilOill_dataout & wire_nlilOili_dataout & wire_nlilOiiO_dataout & wire_nlilOiil_dataout & wire_nlilOiii_dataout & wire_nlilOi0O_dataout & wire_nlilOi0l_dataout & wire_nlilOi0i_dataout & wire_nlilOi1O_dataout & wire_nlilOi1l_dataout & wire_nlilOi1i_dataout & wire_nlilO0OO_dataout & wire_nlilO0Ol_dataout & wire_nlilO0Oi_dataout & wire_nlilO0lO_dataout & wire_nlilO0ll_dataout & wire_nlilO0li_dataout & wire_nlilO0iO_dataout & wire_nlilO0il_dataout & wire_nlilO0ii_dataout & wire_nlilO00O_dataout & wire_nlilO00l_dataout & wire_nlilO00i_dataout & wire_nlilO01O_dataout & wire_nlilO01l_dataout & wire_nlilO01i_dataout & wire_nlilO1OO_dataout & wire_nlilO1Ol_dataout & wire_nlilO1Oi_dataout & wire_nlilO1lO_dataout & wire_nlilO1ll_dataout & wire_nlilO1li_dataout & wire_nlilO1iO_dataout + & wire_nlilO1il_dataout & wire_nlilO1ii_dataout & wire_nlilO10O_dataout & wire_nlilO10l_dataout & wire_nlilO10i_dataout & wire_nlilO11O_dataout & wire_nlilO11l_dataout & wire_nlilO11i_dataout & wire_nlillOOO_dataout & wire_nlillOOl_dataout & wire_nliiOi0i_dataout & wire_nliiOi1O_dataout & wire_nliiOi1l_dataout & wire_nliiOi1i_dataout & wire_nliiO0OO_dataout & wire_nliiO0Ol_dataout & wire_nliiO0Oi_dataout & wire_nliiO0lO_dataout & wire_nliiO0ll_dataout & wire_nliiO0li_dataout & wire_nliiO0iO_dataout & wire_nliiO0il_dataout & wire_nliiO0ii_dataout & wire_nliiO00O_dataout & wire_nliiO00l_dataout & wire_nliiO00i_dataout & wire_nliiO01O_dataout & wire_nliiO01l_dataout & wire_nliiO01i_dataout & wire_nliiO1OO_dataout & wire_nliiO1Ol_dataout & wire_nliiO1Oi_dataout & wire_nliiO1lO_dataout & wire_nliiO1ll_dataout & wire_nliiO1li_dataout & wire_nliiO1iO_dataout & wire_nliiO1il_dataout & wire_nliiO1ii_dataout & wire_nliiO10O_dataout & wire_nliiO10l_dataout & wire_nliiO10i_dataout & wire_nliiO11O_dataout & wire_nliiO11l_dataout & wire_nliiO11i_dataout & wire_nliilOOO_dataout & wire_nliilOOl_dataout & wire_nliilOOi_dataout & wire_nliilOlO_dataout & wire_nliilOll_dataout & wire_nliilOli_dataout & wire_nliilOiO_dataout & wire_nliilOil_dataout & wire_nliilOii_dataout & wire_nliilO0O_dataout & wire_nliilO0l_dataout & wire_nliilO0i_dataout & wire_nliilO1O_dataout & wire_nliilO1l_dataout & wire_nliilO1i_dataout & wire_nliillOO_dataout & wire_nliillOl_dataout & wire_nliillOi_dataout & wire_nliilllO_dataout & wire_nliillll_dataout & wire_nliillli_dataout & wire_nliilliO_dataout & wire_nliillil_dataout & wire_nliillii_dataout & wire_nliill0O_dataout & wire_nliill0l_dataout & wire_nliill0i_dataout & wire_nliill1O_dataout & wire_nliill1l_dataout & wire_nliill1i_dataout); + wire_nli110ii_rdaddress <= ( niOO1OiOl & niOO1OiOO & niOO1Ol1O & niOO1Ol0l); + wire_nli110ii_wraddress <= ( nli1i0lO & nli1i0ll & nli1i0li & nli1i0iO); + nli110ii : cycloneiv_pciehip_pciexp_dcfiforam + GENERIC MAP ( + addr_width => 4, + data_width => 158 + ) + PORT MAP ( + data => wire_nli110ii_data, + q => wire_nli110ii_q, + rdaddress => wire_nli110ii_rdaddress, + rdclock => pld_clk, + wraddress => wire_nli110ii_wraddress, + wrclock => core_clk, + wren => wire_nli1l01O_dataout + ); + wire_nlll0lli_w_lg_w_q_range4070w4398w(0) <= wire_nlll0lli_w_q_range4070w(0) AND wire_nlll0lli_w_lg_w_q_range4359w4397w(0); + wire_nlll0lli_w_lg_w_q_range4231w4450w(0) <= wire_nlll0lli_w_q_range4231w(0) AND wire_nlll0lli_w_lg_w_q_range4229w4449w(0); + wire_nlll0lli_w_lg_w_q_range4359w4397w(0) <= NOT wire_nlll0lli_w_q_range4359w(0); + wire_nlll0lli_w_lg_w_q_range4229w4449w(0) <= NOT wire_nlll0lli_w_q_range4229w(0); + wire_nlll0lli_w_lg_w_q_range4087w4304w(0) <= NOT wire_nlll0lli_w_q_range4087w(0); + wire_nlll0lli_w_lg_w_lg_w_q_range4070w4398w4399w(0) <= wire_nlll0lli_w_lg_w_q_range4070w4398w(0) OR wire_nlll0lli_w_q_range4067w(0); + wire_nlll0lli_data <= ( tx_err_vc0 & tx_sop_vc0_0 & tx_sop_vc0_1 & tx_eop_vc0_0 & niOO0O1ll & tx_data_vc0_0(63 DOWNTO 0) & tx_data_vc0_1(63 DOWNTO 0)); + wire_nlll0lli_rdaddress <= ( niOO01OiO & niOO01Oli & niOO01OOi & niOO01OOO); + wire_nlll0lli_wraddress <= ( nlllllll & nlllllli & nllllliO & nlllllil); + wire_nlll0lli_w_q_range4067w(0) <= wire_nlll0lli_q(128); + wire_nlll0lli_w_q_range4070w(0) <= wire_nlll0lli_q(129); + wire_nlll0lli_w_q_range4359w(0) <= wire_nlll0lli_q(130); + wire_nlll0lli_w_q_range4231w(0) <= wire_nlll0lli_q(32); + wire_nlll0lli_w_q_range4229w(0) <= wire_nlll0lli_q(33); + wire_nlll0lli_w_q_range4087w(0) <= wire_nlll0lli_q(94); + nlll0lli : cycloneiv_pciehip_pciexp_dcfiforam + GENERIC MAP ( + addr_width => 4, + data_width => 133 + ) + PORT MAP ( + data => wire_nlll0lli_data, + q => wire_nlll0lli_q, + rdaddress => wire_nlll0lli_rdaddress, + rdclock => core_clk, + wraddress => wire_nlll0lli_wraddress, + wrclock => pld_clk, + wren => tx_valid_vc0 + ); + wire_nlOil11li_data <= ( wire_nlOl1i1Ol_dataout & wire_nlOl1l0OO_dataout & wire_nlOl1l01O_dataout & wire_nlOl1l01l_dataout & wire_nlOl1l01i_dataout & wire_nlOl1l1OO_dataout & wire_nlOl1l1Ol_dataout & wire_nlOl1l1Oi_dataout & wire_nlOl1l1lO_dataout & wire_nlOl1l1ll_dataout & wire_nlOl1l1li_dataout & wire_nlOl1l1iO_dataout & wire_nlOl1l1il_dataout & wire_nlOl1l1ii_dataout & wire_nlOl1l10O_dataout & wire_nlOl1l10l_dataout & wire_nlOl1l10i_dataout & wire_nlOl1l11O_dataout & wire_nlOl1l11l_dataout & wire_nlOl1l11i_dataout & wire_nlOl1iOOO_dataout & wire_nlOl1iOOl_dataout & wire_nlOl1iOOi_dataout & wire_nlOl1iOlO_dataout & wire_nlOl1iOll_dataout & wire_nlOl1iOli_dataout & wire_nlOl1iOiO_dataout & wire_nlOl1iOil_dataout & wire_nlOl1iOii_dataout & wire_nlOl1iO0O_dataout & wire_nlOl1iO0l_dataout & wire_nlOl1iO0i_dataout & wire_nlOl1iO1O_dataout & wire_nlOl1iO1l_dataout & wire_nlOl1iO1i_dataout & wire_nlOl1ilOO_dataout & wire_nlOl1ilOl_dataout & wire_nlOl1ilOi_dataout & wire_nlOl1illO_dataout & wire_nlOl1illl_dataout & wire_nlOl1illi_dataout & wire_nlOl1iliO_dataout & wire_nlOl1ilil_dataout & wire_nlOl1ilii_dataout & wire_nlOl1il0O_dataout & wire_nlOl1il0l_dataout & wire_nlOl1il0i_dataout & wire_nlOl1il1O_dataout & wire_nlOl1il1l_dataout & wire_nlOl1il1i_dataout & wire_nlOl1iiOO_dataout & wire_nlOl1iiOl_dataout & wire_nlOl1iiOi_dataout & wire_nlOl1iilO_dataout & wire_nlOl1iill_dataout & wire_nlOl1iili_dataout & wire_nlOl1iiiO_dataout & wire_nlOl1iiil_dataout & wire_nlOl1iiii_dataout & wire_nlOl1ii0O_dataout & wire_nlOl1ii0l_dataout & wire_nlOl1ii0i_dataout & wire_nlOl1ii1O_dataout & wire_nlOl1ii1l_dataout & wire_nlOl1ii1i_dataout & wire_nlOl1i0OO_dataout & wire_nlOl1i0Ol_dataout & wire_nlOl1i0Oi_dataout & wire_nlOl1i0lO_dataout & wire_nlOl1i0ll_dataout & wire_nlOl1i0li_dataout & wire_nlOl1i0iO_dataout & wire_nlOl1i0il_dataout & wire_nlOl1i0ii_dataout & wire_nlOl1i00O_dataout & wire_nlOl1i00l_dataout); + wire_nlOil11li_rdaddress <= ( niOl10iiO & niOl10ili & niOl10iOi & niOl10iOO); + wire_nlOil11li_wraddress <= ( nlOil001i & nlOil01OO & nlOil01Ol & nlOil01Oi); + nlOil11li : cycloneiv_pciehip_pciexp_dcfiforam + GENERIC MAP ( + addr_width => 4, + data_width => 76 + ) + PORT MAP ( + data => wire_nlOil11li_data, + q => wire_nlOil11li_q, + rdaddress => wire_nlOil11li_rdaddress, + rdclock => phy_clk, + wraddress => wire_nlOil11li_wraddress, + wrclock => core_clk, + wren => wire_nlOl1l0il_dataout + ); + wire_nlOili0li_data <= ( "0" & "0" & ni0i1iOi & ni0i1ilO & ni0i1ill & ni0i1ili & ni0i1iiO & ni0i1iil & ni0i1iii & ni0i1i0O & ni0i0i1l & ni0i0i1i & ni0i00OO & ni0i00Ol & ni0i00Oi & ni0i00lO & ni0i00ll & ni0i00li & ni0i00iO & ni0i00il & ni0i00ii & ni0i000O & ni0i000l & ni0i000i & ni0i001O & ni0i001l & ni0i001i & ni0i01OO & ni0i01Ol & ni0i01Oi & ni0i01lO & ni0i01ll & ni0i01li & ni0i01iO & ni0i01il & ni0i01ii & ni0i010O & ni0i010l & ni0i010i & ni0i011O & ni0i011l & ni0i011i & ni0i1OOO & ni0i1OOl & ni0i1OOi & ni0i1OlO & ni0i1Oll & ni0i1Oli & ni0i1OiO & ni0i1Oil & ni0i1Oii & ni0i1O0O & ni0i1O0l & ni0i1O0i & ni0i1O1O & ni0i1O1l & ni0i1O1i & ni0i1lOO & ni0i1lOl & ni0i1lOi & ni0i1llO & ni0i1lll & ni0i1lli & ni0i1liO & ni0i1lil & ni0i1lii & ni0i1l0O & ni0i1l0l & ni0i1l0i & ni0i1l1O & ni0i1l1l & ni0i1l1i & ni0i1iOO & ni0i1iOl); + wire_nlOili0li_rdaddress <= ( niOl10llO & niOl10lOi & niOl10O1i & niOl10O1O); + wire_nlOili0li_wraddress <= ( nlOill0OO & nlOill0Ol & nlOill0Oi & nlOill0lO); + nlOili0li : cycloneiv_pciehip_pciexp_dcfiforam + GENERIC MAP ( + addr_width => 4, + data_width => 74 + ) + PORT MAP ( + data => wire_nlOili0li_data, + q => wire_nlOili0li_q, + rdaddress => wire_nlOili0li_rdaddress, + rdclock => core_clk, + wraddress => wire_nlOili0li_wraddress, + wrclock => phy_clk, + wren => ni0i1i0l + ); + wire_nlliO0lOi_data <= ( nlll1lOOl & nlll1lOOi & nlll1lOlO & nlll1lOll & nlll1lOli & nlll1lOiO & nlll1lOil & nlll1lOii); + wire_nlliO0lOi_rdaddress <= ( nlll11liO & nlll11lil & nlll11lii & nlll11l0O & nlll11l0l); + wire_nlliO0lOi_wraddress <= ( nlll00iil & nlll00iii & nlll00i0O & nlll00i0l & nlll00i0i); + nlliO0lOi : cycloneiv_pciehip_pciexp_dcram_rtry + GENERIC MAP ( + addr_width => 5, + data_width => 8 + ) + PORT MAP ( + data => wire_nlliO0lOi_data, + q => wire_nlliO0lOi_q, + rdaddress => wire_nlliO0lOi_rdaddress, + rdclock => core_clk, + wraddress => wire_nlliO0lOi_wraddress, + wrclock => core_clk, + wren => niOiOl1lO + ); + wire_nl1ii10OO_data <= ( nl01l0l0O & nl01l0l0l & wire_nl01110il_dataout & wire_nl01110ii_dataout & wire_nl0111i0O_dataout & wire_nl0111i0l_dataout & wire_nl0111i0i_dataout & wire_nl0111i1O_dataout & wire_nl0111i1l_dataout & wire_nl0111i1i_dataout & wire_nl01110OO_dataout & wire_nl01110Ol_dataout & wire_nl01110Oi_dataout); + wire_nl1ii10OO_rdaddress <= ( nl1OOiili & nl1OOiiiO & nl1OOiiil & nl1OOiiii & nl1OOii0O & nl1OOii0l & nl1OOii0i); + wire_nl1ii10OO_wraddress <= ( nl1OOil1l & nl1OOil1i & nl1OOiiOO & nl1OOiiOl & nl1OOiiOi & nl1OOiilO & nl1OOiill); + nl1ii10OO : cycloneiv_pciehip_pciexp_dcram_rxvc + GENERIC MAP ( + addr_width => 7, + data_width => 13 + ) + PORT MAP ( + data => wire_nl1ii10OO_data, + q => wire_nl1ii10OO_q, + rdaddress => wire_nl1ii10OO_rdaddress, + rdclock => wire_niO0011O_dataout, + wraddress => wire_nl1ii10OO_wraddress, + wrclock => wire_niO0011O_dataout, + wren => wire_vcc + ); + + END RTL; --cycloneiv_pciehip_pciexp_top_hip +--synopsys translate_on +--VALID FILE +LIBRARY ieee; + USE ieee.std_logic_1164.all; + +--====Revision Log================ +--Rev: 1.25 Mon Sep 15 09:07:20 PDT 2008 + + +ENTITY cycloneiv_pciehip_hip_top IS + PORT ( + --phy_clk, + --core_clk, + -- LTSSM L0 State flag + -- Redundancy Scan I/Os for MRAM + -- REGSCAN I/Os for MRAM I/O testing + -- BIST-related I/Os for MRAM + -- Shared between 3 MRAM BISTs + -- Shared between 3 MRAM BISTs + -- scan test IO + -- FRZ signals for MRAMs + -- Redundancy IDs for the 3 MRAMs + -- Control signals from Control Block and POR + + -- Debug signals + + -- Extra signals + + -- DPRIO inputs/outpus + mdio_out : OUT STD_LOGIC; -- Single bit data-out for MDIO Interface + data_enable_n : OUT STD_LOGIC; + dprio_curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- MDIO current state for digital testbus + + mdc : IN STD_LOGIC; -- MDIO Interface clock + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- 5 bit device address + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- 5 bit port address + mdio_in : IN STD_LOGIC; -- Single bit data-in for MDIO Interface + mdio_dis : IN STD_LOGIC; -- MDIO disable input (using CSR) + ser_shift_load : IN STD_LOGIC; -- Serial programming mode shift/load control + csr_hip_in : IN STD_LOGIC_VECTOR(1631 DOWNTO 0); -- CSR inputs + csr_hip_in_reserved : IN STD_LOGIC_VECTOR(127 DOWNTO 0); -- reserved CSR inputs; not connected to MDIO + hip_base_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- DPRIO HIP base address + + -- LMI interface + lmi_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + lmi_ack : OUT STD_LOGIC; + + lmi_rden : IN STD_LOGIC; + lmi_wren : IN STD_LOGIC; + lmi_addr : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + lmi_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Global clock and reset IOs + reset_status : OUT STD_LOGIC; + l2_exit : OUT STD_LOGIC; + hotrst_exit : OUT STD_LOGIC; + dlup_exit : OUT STD_LOGIC; + + pld_clk : IN STD_LOGIC; + pld_srst : IN STD_LOGIC; + pld_rst : IN STD_LOGIC; + --input phy_clk; + pclk_ch0 : IN STD_LOGIC; + pclk_central : IN STD_LOGIC; + pll_fixed_clk : IN STD_LOGIC; + phy_rst : IN STD_LOGIC; + phy_srst : IN STD_LOGIC; + --input core_clk; + core_clk_in : IN STD_LOGIC; + core_clk_out : OUT STD_LOGIC; + core_rst : IN STD_LOGIC; + core_por : IN STD_LOGIC; + core_crst : IN STD_LOGIC; + core_srst : IN STD_LOGIC; + + -- Global signals for SW mode + swdn_wake : OUT STD_LOGIC; + swup_hotrst : OUT STD_LOGIC; + + swdn_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + swup_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + + -- User Interface signals for VC0 + rx_valid_vc0 : OUT STD_LOGIC; + rx_err_vc0 : OUT STD_LOGIC; -- uncorrectable error + rx_bar_dec_vc0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc0_0 : OUT STD_LOGIC; + rx_eop_vc0_0 : OUT STD_LOGIC; + rx_data_vc0_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc0_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc0_1 : OUT STD_LOGIC; + rx_eop_vc0_1 : OUT STD_LOGIC; + rx_data_vc0_1 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc0_1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_fifo_full_vc0 : OUT STD_LOGIC; + rx_fifo_empty_vc0 : OUT STD_LOGIC; + rx_fifo_wrp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_fifo_rdp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_cred_vc0 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0); + tx_ready_vc0 : OUT STD_LOGIC; + --for FIFO monitoring + tx_fifo_full_vc0 : OUT STD_LOGIC; + tx_fifo_empty_vc0 : OUT STD_LOGIC; + tx_fifo_wrp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_fifo_rdp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + rx_mask_vc0 : IN STD_LOGIC; + rx_ready_vc0 : IN STD_LOGIC; + tx_valid_vc0 : IN STD_LOGIC; + tx_err_vc0 : IN STD_LOGIC; + tx_sop_vc0_0 : IN STD_LOGIC; + tx_eop_vc0_0 : IN STD_LOGIC; + tx_data_vc0_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + tx_sop_vc0_1 : IN STD_LOGIC; + tx_eop_vc0_1 : IN STD_LOGIC; + tx_data_vc0_1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + + -- User Interface signals for VC1 + rx_valid_vc1 : OUT STD_LOGIC; + rx_err_vc1 : OUT STD_LOGIC; -- uncorrectable error + rx_bar_dec_vc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc1_0 : OUT STD_LOGIC; + rx_eop_vc1_0 : OUT STD_LOGIC; + rx_data_vc1_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc1_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc1_1 : OUT STD_LOGIC; + rx_eop_vc1_1 : OUT STD_LOGIC; + rx_data_vc1_1 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc1_1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_fifo_full_vc1 : OUT STD_LOGIC; + rx_fifo_empty_vc1 : OUT STD_LOGIC; + rx_fifo_wrp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_fifo_rdp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_cred_vc1 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0); + tx_ready_vc1 : OUT STD_LOGIC; + --for FIFO monitoring + tx_fifo_full_vc1 : OUT STD_LOGIC; + tx_fifo_empty_vc1 : OUT STD_LOGIC; + tx_fifo_wrp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_fifo_rdp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + rx_mask_vc1 : IN STD_LOGIC; + rx_ready_vc1 : IN STD_LOGIC; + tx_valid_vc1 : IN STD_LOGIC; + tx_err_vc1 : IN STD_LOGIC; + tx_sop_vc1_0 : IN STD_LOGIC; + tx_eop_vc1_0 : IN STD_LOGIC; + tx_data_vc1_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + tx_sop_vc1_1 : IN STD_LOGIC; + tx_eop_vc1_1 : IN STD_LOGIC; + tx_data_vc1_1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + + -- Power Management signals + tl_pme_to_sr : OUT STD_LOGIC; + + tl_pme_to_cr : IN STD_LOGIC; + tl_pm_event : IN STD_LOGIC; + tl_pm_data : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + tl_pm_auxpwr : IN STD_LOGIC; + + -- Control Status Register signals + tl_cfg_sts : OUT STD_LOGIC_VECTOR(52 DOWNTO 0); + tl_cfg_sts_wr : OUT STD_LOGIC; + tl_cfg_ctl : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + tl_cfg_ctl_wr : OUT STD_LOGIC; + tl_cfg_add : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- Interrupt signals + tl_app_inta_ack : OUT STD_LOGIC; + tl_app_msi_ack : OUT STD_LOGIC; + int_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + tl_app_inta_sts : IN STD_LOGIC; + tl_app_msi_req : IN STD_LOGIC; + tl_app_msi_tc : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + tl_app_msi_num : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + tl_aer_msi_num : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + tl_pex_msi_num : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + tl_hpg_ctrler : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + + -- TL-bypass signals + dl_up : OUT STD_LOGIC; + dl_vc_status : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dl_err_dll : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + dl_err_phy : OUT STD_LOGIC; + dl_rpbuf_emp : OUT STD_LOGIC; + dl_dll_req : OUT STD_LOGIC; + lane_act : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + link_up : OUT STD_LOGIC; + dl_ltssm : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + clr_rxpath : OUT STD_LOGIC; + dl_rx_val_pm : OUT STD_LOGIC; + dl_rx_typ_pm : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_tx_ack_pm : OUT STD_LOGIC; + dl_ack_phypm : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dl_rst_enter_comp_bit : OUT STD_LOGIC; + dl_rst_tx_margin_field : OUT STD_LOGIC; + dl_current_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dl_current_deemp : OUT STD_LOGIC; + dl_link_auto_bdw_status : OUT STD_LOGIC; + dl_link_bdw_mng_status : OUT STD_LOGIC; + dl_ack_req_upfc : OUT STD_LOGIC; + dl_ack_snd_upfc : OUT STD_LOGIC; + + dl_rx_ecrcchk : IN STD_LOGIC; + dl_aspm_cr0 : IN STD_LOGIC; -- ww51.5 change by Ning Xue + dl_comclk_reg : IN STD_LOGIC; -- ww51.5 change by Ning Xue + dl_vc_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dl_vcid_map : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + dl_inh_dllp : IN STD_LOGIC; + dl_req_wake : IN STD_LOGIC; + dl_txcfg_extsy : IN STD_LOGIC; + dl_tx_req_pm : IN STD_LOGIC; + dl_tx_typ_pm : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_maxpload_dcr : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_req_phypm : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dl_req_phycfg : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dl_req_upfc : IN STD_LOGIC; + dl_snd_upfc : IN STD_LOGIC; + dl_typ_upfc : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dl_vcid_upfc : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_hdr_upfc : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dl_data_upfc : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dl_ctrl_link2 : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + -- Test Port Interface signals + test_out_hip : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + ev_1us : OUT STD_LOGIC; + ev_128ns : OUT STD_LOGIC; + wake_oen : OUT STD_LOGIC; + serr_out : OUT STD_LOGIC; + + tl_slotclk_cfg : IN STD_LOGIC; + mode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + test_in_hip : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + cpl_pending : IN STD_LOGIC; + cpl_err : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + + -- PIPE interface signals + rate : OUT STD_LOGIC; + rate_tied_to_gnd : OUT STD_LOGIC; + eidle_infer_sel0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph0 : OUT STD_LOGIC; + tx_margin0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 0 + txdata0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak0 : OUT STD_LOGIC; + txdetectrx0 : OUT STD_LOGIC; + txelecidle0 : OUT STD_LOGIC; + txcompl0 : OUT STD_LOGIC; + rxpolarity0 : OUT STD_LOGIC; + powerdown0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak0 : IN STD_LOGIC; + rxvalid0 : IN STD_LOGIC; + phystatus0 : IN STD_LOGIC; + rxelecidle0 : IN STD_LOGIC; + rxstatus0 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph1 : OUT STD_LOGIC; + tx_margin1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 1 + txdata1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak1 : OUT STD_LOGIC; + txdetectrx1 : OUT STD_LOGIC; + txelecidle1 : OUT STD_LOGIC; + txcompl1 : OUT STD_LOGIC; + rxpolarity1 : OUT STD_LOGIC; + powerdown1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak1 : IN STD_LOGIC; + rxvalid1 : IN STD_LOGIC; + phystatus1 : IN STD_LOGIC; + rxelecidle1 : IN STD_LOGIC; + rxstatus1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph2 : OUT STD_LOGIC; + tx_margin2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 2 + txdata2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak2 : OUT STD_LOGIC; + txdetectrx2 : OUT STD_LOGIC; + txelecidle2 : OUT STD_LOGIC; + txcompl2 : OUT STD_LOGIC; + rxpolarity2 : OUT STD_LOGIC; + powerdown2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak2 : IN STD_LOGIC; + rxvalid2 : IN STD_LOGIC; + phystatus2 : IN STD_LOGIC; + rxelecidle2 : IN STD_LOGIC; + rxstatus2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel3 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph3 : OUT STD_LOGIC; + tx_margin3 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 3 + txdata3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak3 : OUT STD_LOGIC; + txdetectrx3 : OUT STD_LOGIC; + txelecidle3 : OUT STD_LOGIC; + txcompl3 : OUT STD_LOGIC; + rxpolarity3 : OUT STD_LOGIC; + powerdown3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak3 : IN STD_LOGIC; + rxvalid3 : IN STD_LOGIC; + phystatus3 : IN STD_LOGIC; + rxelecidle3 : IN STD_LOGIC; + rxstatus3 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel4 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph4 : OUT STD_LOGIC; + tx_margin4 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 4 + txdata4 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak4 : OUT STD_LOGIC; + txdetectrx4 : OUT STD_LOGIC; + txelecidle4 : OUT STD_LOGIC; + txcompl4 : OUT STD_LOGIC; + rxpolarity4 : OUT STD_LOGIC; + powerdown4 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak4 : IN STD_LOGIC; + rxvalid4 : IN STD_LOGIC; + phystatus4 : IN STD_LOGIC; + rxelecidle4 : IN STD_LOGIC; + rxstatus4 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel5 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph5 : OUT STD_LOGIC; + tx_margin5 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 5 + txdata5 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak5 : OUT STD_LOGIC; + txdetectrx5 : OUT STD_LOGIC; + txelecidle5 : OUT STD_LOGIC; + txcompl5 : OUT STD_LOGIC; + rxpolarity5 : OUT STD_LOGIC; + powerdown5 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak5 : IN STD_LOGIC; + rxvalid5 : IN STD_LOGIC; + phystatus5 : IN STD_LOGIC; + rxelecidle5 : IN STD_LOGIC; + rxstatus5 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel6 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph6 : OUT STD_LOGIC; + tx_margin6 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 6 + txdata6 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak6 : OUT STD_LOGIC; + txdetectrx6 : OUT STD_LOGIC; + txelecidle6 : OUT STD_LOGIC; + txcompl6 : OUT STD_LOGIC; + rxpolarity6 : OUT STD_LOGIC; + powerdown6 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak6 : IN STD_LOGIC; + rxvalid6 : IN STD_LOGIC; + phystatus6 : IN STD_LOGIC; + rxelecidle6 : IN STD_LOGIC; + rxstatus6 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel7 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph7 : OUT STD_LOGIC; + tx_margin7 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- interface with the PHY PCS Lane 7 + txdata7 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak7 : OUT STD_LOGIC; + txdetectrx7 : OUT STD_LOGIC; + txelecidle7 : OUT STD_LOGIC; + txcompl7 : OUT STD_LOGIC; + rxpolarity7 : OUT STD_LOGIC; + powerdown7 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + rxdata7 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak7 : IN STD_LOGIC; + rxvalid7 : IN STD_LOGIC; + phystatus7 : IN STD_LOGIC; + rxelecidle7 : IN STD_LOGIC; + rxstatus7 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- LTSSM L0 State output + ltssm_l0_state : OUT STD_LOGIC; + + -- Redundancy Scan I/Os for MRAM + mram_red_sclk : IN STD_LOGIC; + mram_red_enscan : IN STD_LOGIC; + mram_red_scen : IN STD_LOGIC; + mram_red_scin : IN STD_LOGIC; + mram_red_scsel : IN STD_LOGIC; + mram_red_scrst : IN STD_LOGIC; + mram_red_scout : OUT STD_LOGIC; + -- REGSCAN I/Os for MRAM I/O testing + mram_regscanen : IN STD_LOGIC; + mram_regscanin : IN STD_LOGIC; + mram_regscanout : OUT STD_LOGIC; + mram_hip_test_enable : IN STD_LOGIC; + + -- BIST inputs/outputs + bist_testen : IN STD_LOGIC; -- shared for all 3 memory blocks + + bist_scanin : IN STD_LOGIC; -- shared for all 3 memory blocks + bist_scanen : IN STD_LOGIC; -- shared for all 3 memory blocks + bisten_rpl : IN STD_LOGIC; + + bisten_rcv0 : IN STD_LOGIC; + + bisten_rcv1 : IN STD_LOGIC; + + bist_scanout_rpl : OUT STD_LOGIC; + + bist_scanout_rcv0 : OUT STD_LOGIC; + + bist_scanout_rcv1 : OUT STD_LOGIC; + bist_donea_rpl : OUT STD_LOGIC; + bist_doneb_rpl : OUT STD_LOGIC; + bist_pass_rpl : OUT STD_LOGIC; + derr_rpl : OUT STD_LOGIC; + derr_cor_ext_rpl : OUT STD_LOGIC; + bist_donea_rcv0 : OUT STD_LOGIC; + bist_doneb_rcv0 : OUT STD_LOGIC; + bist_pass_rcv0 : OUT STD_LOGIC; + derr_cor_ext_rcv0 : OUT STD_LOGIC; + bist_donea_rcv1 : OUT STD_LOGIC; + bist_doneb_rcv1 : OUT STD_LOGIC; + bist_pass_rcv1 : OUT STD_LOGIC; + derr_cor_ext_rcv1 : OUT STD_LOGIC; + + -- scan test IO + scan_mode_n : IN STD_LOGIC; + scan_en : IN STD_LOGIC; + + -- FRZ signals for MRAMs + nfrzdrv : IN STD_LOGIC; + frzreg : IN STD_LOGIC; + frzlogic : IN STD_LOGIC; + + -- Redundancy IDs for the MRAMs + id_rpl : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + id_rcv0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + id_rcv1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- Control signals from Control Block and POR + plniotri : IN STD_LOGIC; + entest : IN STD_LOGIC; + npor : IN STD_LOGIC; + + -- Debug I/Os + dbg_pipex1_rx : IN STD_LOGIC_VECTOR(14 DOWNTO 0); + + -- Extra inputs/outputs + -- used hip_extraout[15] to implement ltssm_l0_state, + -- used hip_extraout [14:7] for 8 out of 16 rx_fifo_wr/rdp_vc0/1 [3:0] + + -- input [15:0] hip_extrain; // Used 4 hip_extrain signals to account for + hip_extrain : IN STD_LOGIC_VECTOR(11 DOWNTO 0); -- dl_req_phypm[3], dl_aspm_cr0, dl_comclk_reg, mram_hip_test_enable + + hip_extraclkin : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + hip_extraout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); + hip_extraclkout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END cycloneiv_pciehip_hip_top; + +ARCHITECTURE trans OF cycloneiv_pciehip_hip_top IS + COMPONENT cycloneiv_pciehip_hip_dprio_top + PORT ( + mdc : IN STD_LOGIC; + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + mdio_in : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + mdio_rst : IN STD_LOGIC; + serial_mode : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + ser_si : IN STD_LOGIC; + csr_hip_in : IN STD_LOGIC_VECTOR(1759 DOWNTO 0); + hip_base_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + ser_so : OUT STD_LOGIC; + mdio_out : OUT STD_LOGIC; + data_enable_n : OUT STD_LOGIC; + curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + out_hip_ctrl_1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_8 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_9 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_14 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_15 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_16 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_19 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_20 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_21 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_22 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_23 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_24 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_25 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_26 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_27 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_28 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_29 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_30 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_31 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_32 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_33 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_34 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_35 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_36 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_37 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_38 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_39 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_40 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_41 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_42 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_43 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_44 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_45 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_46 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_47 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_48 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_49 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_50 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_51 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_52 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_53 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_54 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_55 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_56 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_57 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_58 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_59 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_60 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_61 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_62 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_63 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_64 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_65 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_66 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_67 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_68 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_69 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_70 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_71 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_72 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_73 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_74 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_75 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_76 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_77 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_78 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_79 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_80 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_81 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_82 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_83 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_84 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_85 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_86 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_87 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_88 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_89 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_90 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_91 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_92 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_93 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_94 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_95 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_96 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_97 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_98 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_99 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_100 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_101 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_102 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_103 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_104 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_105 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_106 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_107 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_108 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_109 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + out_hip_ctrl_110 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_iei_detect + PORT ( + rxelecidle : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + pclk : IN STD_LOGIC; + uclk : IN STD_LOGIC; + prstn : IN STD_LOGIC; + urstn : IN STD_LOGIC; + rate : IN STD_LOGIC; + enable_inf_ei : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + rxupdatefc : IN STD_LOGIC; + test_in_0 : IN STD_LOGIC; + eidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + datain_ch0 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + datain_ch1 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + datain_ch2 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + datain_ch3 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + datain_ch4 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + datain_ch5 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + datain_ch6 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + datain_ch7 : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + rxelecidle_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxvalid : IN STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_pciexp_top_hip +-- GENERIC ( +-- G_RX_BUF : INTEGER := 9; 11; +-- G_RH_NUM : INTEGER := 7; 8; +-- G_RTRY_BUF : INTEGER := 8; 11; +-- G_RTRY_NUM : INTEGER := 6; +-- G_TAG_NUM : INTEGER := 64 +-- ); + PORT ( + adrd_rcv0 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adrd_rcv1 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adrd_rpl : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + adwr_rcv0 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adwr_rcv1 : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + adwr_rpl : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + clr_rxpath : OUT STD_LOGIC; + core_clk : IN STD_LOGIC; + core_clk_vc0 : OUT STD_LOGIC; + core_clk_vc1 : OUT STD_LOGIC; + core_crst : IN STD_LOGIC; + core_npor : IN STD_LOGIC; + core_rstn : IN STD_LOGIC; + core_srst : IN STD_LOGIC; + cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + cpl_pending : IN STD_LOGIC; + derr_rcv0 : IN STD_LOGIC; + derr_rcv1 : IN STD_LOGIC; + din_rcv0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + din_rcv1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + din_rpl : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + dl_ack_phypm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + dl_ack_req_upfc : OUT STD_LOGIC; + dl_ack_snd_upfc : OUT STD_LOGIC; + dl_aspm_cr0 : IN STD_LOGIC; + dl_comclk_reg : IN STD_LOGIC; + dl_ctrl_link2 : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + dl_current_deemp : OUT STD_LOGIC; + dl_current_speed : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + dl_data_upfc : IN STD_LOGIC_VECTOR (11 DOWNTO 0); + dl_dll_req : OUT STD_LOGIC; + dl_err_dll : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dl_err_phy : OUT STD_LOGIC; + dl_hdr_upfc : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + dl_inh_dllp : IN STD_LOGIC; + dl_link_auto_bdw_status : OUT STD_LOGIC; + dl_link_bdw_mng_status : OUT STD_LOGIC; + dl_ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + dl_maxpload_dcr : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + dl_req_phycfg : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + dl_req_phypm : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + dl_req_upfc : IN STD_LOGIC; + dl_req_wake : IN STD_LOGIC; + dl_rpbuf_emp : OUT STD_LOGIC; + dl_rst_enter_comp_bit : OUT STD_LOGIC; + dl_rst_tx_margin_field : OUT STD_LOGIC; + dl_rx_ecrcchk : IN STD_LOGIC; + dl_rx_typ_pm : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + dl_rx_val_fc : OUT STD_LOGIC; + dl_rx_val_pm : OUT STD_LOGIC; + dl_snd_upfc : IN STD_LOGIC; + dl_tx_ack_pm : OUT STD_LOGIC; + dl_tx_req_pm : IN STD_LOGIC; + dl_tx_typ_pm : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + dl_txcfg_extsy : IN STD_LOGIC; + dl_typ_upfc : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + dl_up : OUT STD_LOGIC; + dl_vc_ctrl : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + dl_vc_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + dl_vcid_map : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + dl_vcid_upfc : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + dlup_exit : OUT STD_LOGIC; + dout_rcv0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + dout_rcv1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + dout_rpl : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + eidle_infer_sel : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + ev_128ns : OUT STD_LOGIC; + ev_1us : OUT STD_LOGIC; + hotrst_exit : OUT STD_LOGIC; + int_status : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + k_bar : IN STD_LOGIC_VECTOR (227 DOWNTO 0); + k_cnt : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + k_conf : IN STD_LOGIC_VECTOR (383 DOWNTO 0); + k_dev : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + k_gbl_hip : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + k_hip : IN STD_LOGIC_VECTOR (22 DOWNTO 0); + k_port : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + k_ptr0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0); + k_ptr1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0); + k_rtry : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + k_vc0 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc1 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc2 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc3 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc4 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc5 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc6 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + k_vc7 : IN STD_LOGIC_VECTOR (55 DOWNTO 0); + l2_exit : OUT STD_LOGIC; + lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + lane_reversal_enable : OUT STD_LOGIC; + link_up : OUT STD_LOGIC; + lmi_ack : OUT STD_LOGIC; + lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0); + lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + lmi_rden : IN STD_LOGIC; + lmi_wren : IN STD_LOGIC; + mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + phy_clk : IN STD_LOGIC; + phy_rstn : IN STD_LOGIC; + phy_srst : IN STD_LOGIC; + phystatus0 : IN STD_LOGIC; + phystatus1 : IN STD_LOGIC; + phystatus2 : IN STD_LOGIC; + phystatus3 : IN STD_LOGIC; + phystatus4 : IN STD_LOGIC; + phystatus5 : IN STD_LOGIC; + phystatus6 : IN STD_LOGIC; + phystatus7 : IN STD_LOGIC; + pld_clk : IN STD_LOGIC; + pld_rstn : IN STD_LOGIC; + pld_srst : IN STD_LOGIC; + powerdown0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown1 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown2 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown3 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown4 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown5 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown6 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + powerdown7 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + prstn : OUT STD_LOGIC; + rate : OUT STD_LOGIC; + reset_status : OUT STD_LOGIC; + rx_bar_dec_vc0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_bar_dec_vc1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc0_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc0_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc1_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_be_vc1_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rx_data_vc0_0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_data_vc0_1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_data_vc1_0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_data_vc1_1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + rx_eop_vc0_0 : OUT STD_LOGIC; + rx_eop_vc0_1 : OUT STD_LOGIC; + rx_eop_vc1_0 : OUT STD_LOGIC; + rx_eop_vc1_1 : OUT STD_LOGIC; + rx_err_vc0 : OUT STD_LOGIC; + rx_err_vc1 : OUT STD_LOGIC; + rx_fifo_empty_vc0 : OUT STD_LOGIC; + rx_fifo_empty_vc1 : OUT STD_LOGIC; + rx_fifo_full_vc0 : OUT STD_LOGIC; + rx_fifo_full_vc1 : OUT STD_LOGIC; + rx_fifo_rdp0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_fifo_rdp1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_fifo_wrp0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_fifo_wrp1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + rx_mask_vc0 : IN STD_LOGIC; + rx_mask_vc1 : IN STD_LOGIC; + rx_ready_vc0 : IN STD_LOGIC; + rx_ready_vc1 : IN STD_LOGIC; + rx_sop_vc0_0 : OUT STD_LOGIC; + rx_sop_vc0_1 : OUT STD_LOGIC; + rx_sop_vc1_0 : OUT STD_LOGIC; + rx_sop_vc1_1 : OUT STD_LOGIC; + rx_valid_vc0 : OUT STD_LOGIC; + rx_valid_vc1 : OUT STD_LOGIC; + rxdata0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata3 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata4 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata5 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata6 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdata7 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rxdatak0 : IN STD_LOGIC; + rxdatak1 : IN STD_LOGIC; + rxdatak2 : IN STD_LOGIC; + rxdatak3 : IN STD_LOGIC; + rxdatak4 : IN STD_LOGIC; + rxdatak5 : IN STD_LOGIC; + rxdatak6 : IN STD_LOGIC; + rxdatak7 : IN STD_LOGIC; + rxelecidle0 : IN STD_LOGIC; + rxelecidle1 : IN STD_LOGIC; + rxelecidle2 : IN STD_LOGIC; + rxelecidle3 : IN STD_LOGIC; + rxelecidle4 : IN STD_LOGIC; + rxelecidle5 : IN STD_LOGIC; + rxelecidle6 : IN STD_LOGIC; + rxelecidle7 : IN STD_LOGIC; + rxpolarity0 : OUT STD_LOGIC; + rxpolarity1 : OUT STD_LOGIC; + rxpolarity2 : OUT STD_LOGIC; + rxpolarity3 : OUT STD_LOGIC; + rxpolarity4 : OUT STD_LOGIC; + rxpolarity5 : OUT STD_LOGIC; + rxpolarity6 : OUT STD_LOGIC; + rxpolarity7 : OUT STD_LOGIC; + rxstatus0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus1 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus2 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus3 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus4 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus5 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus6 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxstatus7 : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + rxvalid0 : IN STD_LOGIC; + rxvalid1 : IN STD_LOGIC; + rxvalid2 : IN STD_LOGIC; + rxvalid3 : IN STD_LOGIC; + rxvalid4 : IN STD_LOGIC; + rxvalid5 : IN STD_LOGIC; + rxvalid6 : IN STD_LOGIC; + rxvalid7 : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + serr_out : OUT STD_LOGIC; + successful_speed_negotiation_int : OUT STD_LOGIC; + swdn_in : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + swdn_wake : OUT STD_LOGIC; + swup_hotrst : OUT STD_LOGIC; + swup_in : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + test_in_hip : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + test_out_hip : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); + tl_aer_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_app_inta_ack : OUT STD_LOGIC; + tl_app_inta_sts : IN STD_LOGIC; + tl_app_msi_ack : OUT STD_LOGIC; + tl_app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_app_msi_req : IN STD_LOGIC; + tl_app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + tl_cfg_ctl_wr : OUT STD_LOGIC; + tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0); + tl_cfg_sts_wr : OUT STD_LOGIC; + tl_hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tl_pm_auxpwr : IN STD_LOGIC; + tl_pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + tl_pm_event : IN STD_LOGIC; + tl_pme_to_cr : IN STD_LOGIC; + tl_pme_to_sr : OUT STD_LOGIC; + tl_slotclk_cfg : IN STD_LOGIC; + tx_cred_vc0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0); + tx_cred_vc1 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0); + tx_data_vc0_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_data_vc0_1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_data_vc1_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_data_vc1_1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + tx_deemph : OUT STD_LOGIC; + tx_eop_vc0_0 : IN STD_LOGIC; + tx_eop_vc0_1 : IN STD_LOGIC; + tx_eop_vc1_0 : IN STD_LOGIC; + tx_eop_vc1_1 : IN STD_LOGIC; + tx_err_vc0 : IN STD_LOGIC; + tx_err_vc1 : IN STD_LOGIC; + tx_fifo_empty_vc0 : OUT STD_LOGIC; + tx_fifo_empty_vc1 : OUT STD_LOGIC; + tx_fifo_full_vc0 : OUT STD_LOGIC; + tx_fifo_full_vc1 : OUT STD_LOGIC; + tx_fifo_rdp_vc0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_fifo_rdp_vc1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_fifo_wrp_vc0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_fifo_wrp_vc1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + tx_margin : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + tx_ready_vc0 : OUT STD_LOGIC; + tx_ready_vc1 : OUT STD_LOGIC; + tx_sop_vc0_0 : IN STD_LOGIC; + tx_sop_vc0_1 : IN STD_LOGIC; + tx_sop_vc1_0 : IN STD_LOGIC; + tx_sop_vc1_1 : IN STD_LOGIC; + tx_valid_vc0 : IN STD_LOGIC; + tx_valid_vc1 : IN STD_LOGIC; + txcompl0 : OUT STD_LOGIC; + txcompl1 : OUT STD_LOGIC; + txcompl2 : OUT STD_LOGIC; + txcompl3 : OUT STD_LOGIC; + txcompl4 : OUT STD_LOGIC; + txcompl5 : OUT STD_LOGIC; + txcompl6 : OUT STD_LOGIC; + txcompl7 : OUT STD_LOGIC; + txdata0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata3 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata4 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata5 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata6 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdata7 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + txdatak0 : OUT STD_LOGIC; + txdatak1 : OUT STD_LOGIC; + txdatak2 : OUT STD_LOGIC; + txdatak3 : OUT STD_LOGIC; + txdatak4 : OUT STD_LOGIC; + txdatak5 : OUT STD_LOGIC; + txdatak6 : OUT STD_LOGIC; + txdatak7 : OUT STD_LOGIC; + txdetectrx0 : OUT STD_LOGIC; + txdetectrx1 : OUT STD_LOGIC; + txdetectrx2 : OUT STD_LOGIC; + txdetectrx3 : OUT STD_LOGIC; + txdetectrx4 : OUT STD_LOGIC; + txdetectrx5 : OUT STD_LOGIC; + txdetectrx6 : OUT STD_LOGIC; + txdetectrx7 : OUT STD_LOGIC; + txelecidle0 : OUT STD_LOGIC; + txelecidle1 : OUT STD_LOGIC; + txelecidle2 : OUT STD_LOGIC; + txelecidle3 : OUT STD_LOGIC; + txelecidle4 : OUT STD_LOGIC; + txelecidle5 : OUT STD_LOGIC; + txelecidle6 : OUT STD_LOGIC; + txelecidle7 : OUT STD_LOGIC; + urstn : OUT STD_LOGIC; + usrst : OUT STD_LOGIC; + wake_oen : OUT STD_LOGIC; + wren_rcv0 : OUT STD_LOGIC; + wren_rcv1 : OUT STD_LOGIC; + wren_rpl : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_clkmux + PORT ( + resetn : IN STD_LOGIC; + scan_mode : IN STD_LOGIC; + pclk_ch0 : IN STD_LOGIC; + pclk_central : IN STD_LOGIC; + pll_fixed_clk : IN STD_LOGIC; + core_clk_in : IN STD_LOGIC; + r_pclk_sel : IN STD_LOGIC; + r_core_clk_source_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + r_core_clk_div_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + r_core_clk_out_sel : IN STD_LOGIC; + r_core_clk_dbg_sel : IN STD_LOGIC; + pclk_out : OUT STD_LOGIC; + core_clk : OUT STD_LOGIC; + core_clk_out : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_mram_top + GENERIC ( + ADDR_WIDTH : INTEGER := 14; + DATA_WIDTH : INTEGER := 72 + ); + PORT ( + core_clk : IN STD_LOGIC; + dprio_mram_in : IN STD_LOGIC_VECTOR(34 DOWNTO 0); + addrA : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + addrB : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + wren : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + rstn : IN STD_LOGIC; + srst : IN STD_LOGIC; + bisten : IN STD_LOGIC; + dprio_bist_in : IN STD_LOGIC_VECTOR(74 DOWNTO 0); + enscan : IN STD_LOGIC; + rscen : IN STD_LOGIC; + prv_mram : IN STD_LOGIC; + rscin : IN STD_LOGIC; + rscsel : IN STD_LOGIC; + rscrst : IN STD_LOGIC; + rsclk : IN STD_LOGIC; + id : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + scanen : IN STD_LOGIC; + scanin : IN STD_LOGIC; + mram_hip_test_enable : IN STD_LOGIC; + bist_scanen : IN STD_LOGIC; + bist_scanin : IN STD_LOGIC; + testen : IN STD_LOGIC; + uncor_err_ext_en : IN STD_LOGIC; + scanout : OUT STD_LOGIC; + rscout : OUT STD_LOGIC; + bist_scanout : OUT STD_LOGIC; + bistdoneA : OUT STD_LOGIC; + bistdoneB : OUT STD_LOGIC; + pass : OUT STD_LOGIC; + derr : OUT STD_LOGIC; + derr_cor_ext : OUT STD_LOGIC; + nfrzdrv : IN STD_LOGIC; + frzreg : IN STD_LOGIC; + frzlogic : IN STD_LOGIC; + scan_mode : IN STD_LOGIC + ); + END COMPONENT; + + -- cycloneiv: cycloneiv specific to pass pcs wrap back control to digi_quad_wrapper + SIGNAL dq_pld_side_pcs_wrpbck_rpidft : STD_LOGIC; + SIGNAL dq_pcs_side_pcs_wrpbck : STD_LOGIC; + + SIGNAL dbg_pipex1_tx : STD_LOGIC_VECTOR(14 DOWNTO 0); + + -- RX signals after being muxed with Debug signals + SIGNAL rxstatus0_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle0_muxout : STD_LOGIC; + SIGNAL phystatus0_muxout : STD_LOGIC; + SIGNAL rxvalid0_muxout : STD_LOGIC; + SIGNAL rxdatak0_muxout : STD_LOGIC; + SIGNAL rxdata0_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxstatus1_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle1_muxout : STD_LOGIC; + SIGNAL phystatus1_muxout : STD_LOGIC; + SIGNAL rxvalid1_muxout : STD_LOGIC; + SIGNAL rxdatak1_muxout : STD_LOGIC; + SIGNAL rxdata1_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxstatus2_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle2_muxout : STD_LOGIC; + SIGNAL phystatus2_muxout : STD_LOGIC; + SIGNAL rxvalid2_muxout : STD_LOGIC; + SIGNAL rxdatak2_muxout : STD_LOGIC; + SIGNAL rxdata2_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxstatus3_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle3_muxout : STD_LOGIC; + SIGNAL phystatus3_muxout : STD_LOGIC; + SIGNAL rxvalid3_muxout : STD_LOGIC; + SIGNAL rxdatak3_muxout : STD_LOGIC; + SIGNAL rxdata3_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxstatus4_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle4_muxout : STD_LOGIC; + SIGNAL phystatus4_muxout : STD_LOGIC; + SIGNAL rxvalid4_muxout : STD_LOGIC; + SIGNAL rxdatak4_muxout : STD_LOGIC; + SIGNAL rxdata4_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxstatus5_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle5_muxout : STD_LOGIC; + SIGNAL phystatus5_muxout : STD_LOGIC; + SIGNAL rxvalid5_muxout : STD_LOGIC; + SIGNAL rxdatak5_muxout : STD_LOGIC; + SIGNAL rxdata5_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxstatus6_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle6_muxout : STD_LOGIC; + SIGNAL phystatus6_muxout : STD_LOGIC; + SIGNAL rxvalid6_muxout : STD_LOGIC; + SIGNAL rxdatak6_muxout : STD_LOGIC; + SIGNAL rxdata6_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxstatus7_muxout : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL rxelecidle7_muxout : STD_LOGIC; + SIGNAL phystatus7_muxout : STD_LOGIC; + SIGNAL rxvalid7_muxout : STD_LOGIC; + SIGNAL rxdatak7_muxout : STD_LOGIC; + SIGNAL rxdata7_muxout : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL rxelecidle0_infer : STD_LOGIC; + SIGNAL rxelecidle1_infer : STD_LOGIC; + SIGNAL rxelecidle2_infer : STD_LOGIC; + SIGNAL rxelecidle3_infer : STD_LOGIC; + SIGNAL rxelecidle4_infer : STD_LOGIC; + SIGNAL rxelecidle5_infer : STD_LOGIC; + SIGNAL rxelecidle6_infer : STD_LOGIC; + SIGNAL rxelecidle7_infer : STD_LOGIC; + + -- clock connections + SIGNAL pclk : STD_LOGIC; + SIGNAL core_clk : STD_LOGIC; + + -- Gated-clock for VC0/1 RX buffers + SIGNAL clk_vc0 : STD_LOGIC; + SIGNAL clk_vc1 : STD_LOGIC; + + -- configuration signals + SIGNAL k_gbl : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL k_dev : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL k_port : STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- clk-stealing enable signals for the MRAMs + SIGNAL k_clk_x8_sel_rtry : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL k_clk_x8_sel_rcv0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL k_clk_x8_sel_rcv1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- ECC enable signals for the MRAMs + SIGNAL k_ecc_enable_rtry : STD_LOGIC; + SIGNAL k_ecc_enable_rcv0 : STD_LOGIC; + SIGNAL k_ecc_enable_rcv1 : STD_LOGIC; + + -- clk mux selections + SIGNAL k_pclk_sel : STD_LOGIC; + SIGNAL k_core_clk_source_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL k_core_clk_div_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL k_core_clk_out_sel : STD_LOGIC; + SIGNAL k_core_clk_dbg_sel : STD_LOGIC; + + -- RX,TX debug signal selection + SIGNAL k_pipex1_dbg_sel : STD_LOGIC; + + -- Electrical Idle Inferral enable + SIGNAL k_iei_enable : STD_LOGIC_VECTOR(5 DOWNTO 0); + + SIGNAL k_conf_func0 : STD_LOGIC_VECTOR(383 DOWNTO 0); + SIGNAL k_bar_func0 : STD_LOGIC_VECTOR(227 DOWNTO 0); + SIGNAL k_cnt : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL k_vc0 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc1 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc2 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc3 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc4 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc5 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc6 : STD_LOGIC_VECTOR(55 DOWNTO 0); + SIGNAL k_vc7 : STD_LOGIC_VECTOR(55 DOWNTO 0); + -- cycloneiv + -- SIGNAL k_rtry : STD_LOGIC_VECTOR(10 DOWNTO 0); + -- SIGNAL k_ptr0 : STD_LOGIC_VECTOR(43 DOWNTO 0); + -- SIGNAL k_ptr1 : STD_LOGIC_VECTOR(43 DOWNTO 0); + SIGNAL k_rtry : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL k_ptr0 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL k_ptr1 : STD_LOGIC_VECTOR(35 DOWNTO 0); + -- wire [3:0] k_hip; + SIGNAL k_hip : STD_LOGIC_VECTOR(22 DOWNTO 0); + SIGNAL k_mem_bist : STD_LOGIC_VECTOR(74 DOWNTO 0); + SIGNAL k_rtry_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL k_rcv0_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL k_rcv1_mem : STD_LOGIC_VECTOR(29 DOWNTO 0); + + SIGNAL out_hip_ctrl_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_6 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_8 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_9 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_10 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_11 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_12 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_13 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_14 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_15 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_17 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_18 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_19 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_20 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_21 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_22 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_23 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_24 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_25 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_26 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_27 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_28 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_29 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_30 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_31 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_32 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_33 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_34 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_35 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_36 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_37 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_38 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_39 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_40 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_41 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_42 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_43 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_44 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_45 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_46 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_47 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_48 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_50 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_51 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_52 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_53 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_54 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_55 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_56 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_57 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_58 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_59 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_60 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_61 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_62 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_63 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_64 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_65 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_66 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_67 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_68 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_69 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_70 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_71 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_72 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_73 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_74 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_75 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_76 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_77 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_78 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_79 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_80 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_81 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_82 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_83 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_84 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_85 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_86 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_87 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_88 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_89 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_90 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_91 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_92 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_93 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_94 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_95 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_96 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_97 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_98 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_99 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_100 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_101 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_102 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_103 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_104 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_105 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_106 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_107 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_108 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_109 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL out_hip_ctrl_110 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- interface with replay buffer + SIGNAL wren_rpl : STD_LOGIC; + -- cycloneiv + --SIGNAL adwr_rpl : STD_LOGIC_VECTOR(10 DOWNTO 0); + --SIGNAL adrd_rpl : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL adwr_rpl : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL adrd_rpl : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL din_rpl : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL dout_rpl : STD_LOGIC_VECTOR(63 DOWNTO 0); + + SIGNAL derr_cor_ext_rpl_int : STD_LOGIC; + SIGNAL bist_pass_rpl_int : STD_LOGIC; + SIGNAL bist_doneb_rpl_int : STD_LOGIC; + SIGNAL bist_donea_rpl_int : STD_LOGIC; + SIGNAL bist_scanout_rpl_int : STD_LOGIC; + + -- interface with receive buffers + SIGNAL wren_rcv0 : STD_LOGIC; + -- cycloneiv + --SIGNAL adwr_rcv0 : STD_LOGIC_VECTOR(10 DOWNTO 0); + --SIGNAL adrd_rcv0 : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL adwr_rcv0 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL adrd_rcv0 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL din_rcv0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL dout_rcv0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL derr_rcv0 : STD_LOGIC; + + SIGNAL derr_cor_ext_rcv0_int : STD_LOGIC; + SIGNAL bist_pass_rcv0_int : STD_LOGIC; + SIGNAL bist_doneb_rcv0_int : STD_LOGIC; + SIGNAL bist_donea_rcv0_int : STD_LOGIC; + SIGNAL bist_scanout_rcv0_int : STD_LOGIC; + + SIGNAL wren_rcv1 : STD_LOGIC; + -- cycloneiv + --SIGNAL adwr_rcv1 : STD_LOGIC_VECTOR(10 DOWNTO 0); + --SIGNAL adrd_rcv1 : STD_LOGIC_VECTOR(10 DOWNTO 0); + SIGNAL adwr_rcv1 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL adrd_rcv1 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL din_rcv1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL dout_rcv1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL derr_rcv1 : STD_LOGIC; + + SIGNAL derr_cor_ext_rcv1_int : STD_LOGIC; + SIGNAL bist_pass_rcv1_int : STD_LOGIC; + SIGNAL bist_doneb_rcv1_int : STD_LOGIC; + SIGNAL bist_donea_rcv1_int : STD_LOGIC; + SIGNAL bist_scanout_rcv1_int : STD_LOGIC; + + -- No-connect wires + SIGNAL dout_rpl_nc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dout_rcv0_nc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dout_rcv1_nc : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL urstn : STD_LOGIC; + SIGNAL prstn : STD_LOGIC; + SIGNAL usrst : STD_LOGIC; + SIGNAL red_scout_rpl : STD_LOGIC; + SIGNAL red_scout_rcv0 : STD_LOGIC; + SIGNAL regscanout_rpl : STD_LOGIC; + SIGNAL regscanout_rcv0 : STD_LOGIC; + + SIGNAL eidle_infer_sel : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL tx_deemph : STD_LOGIC; + SIGNAL tx_margin : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL pld_rstn : STD_LOGIC; + SIGNAL phy_rstn : STD_LOGIC; + SIGNAL core_rstn : STD_LOGIC; + SIGNAL core_npor : STD_LOGIC; + SIGNAL scan_mode : STD_LOGIC; + + SIGNAL pld_srst_int : STD_LOGIC; + SIGNAL pld_rstn_int : STD_LOGIC; + SIGNAL phy_srst_int : STD_LOGIC; + SIGNAL phy_rstn_int : STD_LOGIC; + SIGNAL core_crst_int : STD_LOGIC; + SIGNAL core_srst_int : STD_LOGIC; + SIGNAL core_rstn_int : STD_LOGIC; + SIGNAL core_npor_int : STD_LOGIC; + + SIGNAL hard_reset : STD_LOGIC; + + SIGNAL lane_reversal_enable : STD_LOGIC; + SIGNAL ser_si : STD_LOGIC; + SIGNAL serial_mode : STD_LOGIC; + SIGNAL ser_so : STD_LOGIC; + + SIGNAL dl_rx_val_fc : STD_LOGIC; + + -- temporary signal names for {out1, out2} assignment - shawn VHDL + SIGNAL temp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL temp1 : STD_LOGIC_VECTOR(71 DOWNTO 0); + SIGNAL temp2 : STD_LOGIC_VECTOR(71 DOWNTO 0); + SIGNAL temp3 : STD_LOGIC_VECTOR(71 DOWNTO 0); + SIGNAL tmp_csr_hip_in : STD_LOGIC_VECTOR(1759 DOWNTO 0); + + SIGNAL successful_speed_negotiation_int : STD_LOGIC; + -- X-HDL generated signals + + SIGNAL xhdl150 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl151 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl152 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl153 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl154 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl155 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl156 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl157 : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL xhdl158 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL xhdl159 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL xhdl160 : STD_LOGIC_VECTOR(34 DOWNTO 0); + SIGNAL xhdl161 : STD_LOGIC_VECTOR(12 DOWNTO 0); + SIGNAL xhdl162 : STD_LOGIC_VECTOR(12 DOWNTO 0); + SIGNAL xhdl163 : STD_LOGIC_VECTOR(71 DOWNTO 0); + SIGNAL xhdl164 : STD_LOGIC_VECTOR(34 DOWNTO 0); + SIGNAL xhdl165 : STD_LOGIC_VECTOR(12 DOWNTO 0); + SIGNAL xhdl166 : STD_LOGIC_VECTOR(12 DOWNTO 0); + SIGNAL xhdl167 : STD_LOGIC_VECTOR(71 DOWNTO 0); + SIGNAL xhdl168 : STD_LOGIC_VECTOR(34 DOWNTO 0); + SIGNAL xhdl169 : STD_LOGIC_VECTOR(13 DOWNTO 0); + SIGNAL xhdl170 : STD_LOGIC_VECTOR(13 DOWNTO 0); + SIGNAL xhdl171 : STD_LOGIC_VECTOR(71 DOWNTO 0); + + -- Declare intermediate signals for referenced outputs + SIGNAL mdio_out_xhdl34 : STD_LOGIC; + SIGNAL data_enable_n_xhdl2 : STD_LOGIC; + SIGNAL dprio_curr_state_xhdl24 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL lmi_dout_xhdl33 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL lmi_ack_xhdl32 : STD_LOGIC; + SIGNAL reset_status_xhdl46 : STD_LOGIC; + SIGNAL l2_exit_xhdl29 : STD_LOGIC; + SIGNAL hotrst_exit_xhdl27 : STD_LOGIC; + SIGNAL dlup_exit_xhdl23 : STD_LOGIC; + SIGNAL core_clk_out_xhdl1 : STD_LOGIC; + SIGNAL swdn_wake_xhdl86 : STD_LOGIC; + SIGNAL swup_hotrst_xhdl87 : STD_LOGIC; + SIGNAL rx_valid_vc0_xhdl75 : STD_LOGIC; + SIGNAL rx_err_vc0_xhdl61 : STD_LOGIC; + SIGNAL rx_bar_dec_vc0_xhdl47 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rx_sop_vc0_0_xhdl71 : STD_LOGIC; + SIGNAL rx_eop_vc0_0_xhdl57 : STD_LOGIC; + SIGNAL rx_data_vc0_0_xhdl53 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rx_be_vc0_0_xhdl49 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rx_sop_vc0_1_xhdl72 : STD_LOGIC; + SIGNAL rx_eop_vc0_1_xhdl58 : STD_LOGIC; + SIGNAL rx_data_vc0_1_xhdl54 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rx_be_vc0_1_xhdl50 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rx_fifo_full_vc0_xhdl65 : STD_LOGIC; + SIGNAL rx_fifo_empty_vc0_xhdl63 : STD_LOGIC; + SIGNAL rx_fifo_wrp_vc0_xhdl69 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rx_fifo_rdp_vc0_xhdl67 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tx_cred_vc0_xhdl97 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL tx_ready_vc0_xhdl107 : STD_LOGIC; + SIGNAL tx_fifo_full_vc0_xhdl101 : STD_LOGIC; + SIGNAL tx_fifo_empty_vc0_xhdl99 : STD_LOGIC; + SIGNAL tx_fifo_wrp_vc0_xhdl105 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tx_fifo_rdp_vc0_xhdl103 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rx_valid_vc1_xhdl76 : STD_LOGIC; + SIGNAL rx_err_vc1_xhdl62 : STD_LOGIC; + SIGNAL rx_bar_dec_vc1_xhdl48 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rx_sop_vc1_0_xhdl73 : STD_LOGIC; + SIGNAL rx_eop_vc1_0_xhdl59 : STD_LOGIC; + SIGNAL rx_data_vc1_0_xhdl55 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rx_be_vc1_0_xhdl51 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rx_sop_vc1_1_xhdl74 : STD_LOGIC; + SIGNAL rx_eop_vc1_1_xhdl60 : STD_LOGIC; + SIGNAL rx_data_vc1_1_xhdl56 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rx_be_vc1_1_xhdl52 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rx_fifo_full_vc1_xhdl66 : STD_LOGIC; + SIGNAL rx_fifo_empty_vc1_xhdl64 : STD_LOGIC; + SIGNAL rx_fifo_wrp_vc1_xhdl70 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rx_fifo_rdp_vc1_xhdl68 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tx_cred_vc1_xhdl98 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL tx_ready_vc1_xhdl108 : STD_LOGIC; + SIGNAL tx_fifo_full_vc1_xhdl102 : STD_LOGIC; + SIGNAL tx_fifo_empty_vc1_xhdl100 : STD_LOGIC; + SIGNAL tx_fifo_wrp_vc1_xhdl106 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tx_fifo_rdp_vc1_xhdl104 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tl_pme_to_sr_xhdl96 : STD_LOGIC; + SIGNAL tl_cfg_sts_xhdl94 : STD_LOGIC_VECTOR(52 DOWNTO 0); + SIGNAL tl_cfg_sts_wr_xhdl95 : STD_LOGIC; + SIGNAL tl_cfg_ctl_xhdl92 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL tl_cfg_ctl_wr_xhdl93 : STD_LOGIC; + SIGNAL tl_cfg_add_xhdl91 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tl_app_inta_ack_xhdl89 : STD_LOGIC; + SIGNAL tl_app_msi_ack_xhdl90 : STD_LOGIC; + SIGNAL int_status_xhdl28 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dl_up_xhdl21 : STD_LOGIC; + SIGNAL dl_vc_status_xhdl22 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dl_err_dll_xhdl10 : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dl_err_phy_xhdl11 : STD_LOGIC; + SIGNAL dl_rpbuf_emp_xhdl15 : STD_LOGIC; + SIGNAL dl_dll_req_xhdl9 : STD_LOGIC; + SIGNAL lane_act_xhdl30 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL link_up_xhdl31 : STD_LOGIC; + SIGNAL dl_ltssm_xhdl14 : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL clr_rxpath_xhdl0 : STD_LOGIC; + SIGNAL dl_rx_val_pm_xhdl19 : STD_LOGIC; + SIGNAL dl_rx_typ_pm_xhdl18 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dl_tx_ack_pm_xhdl20 : STD_LOGIC; + SIGNAL dl_ack_phypm_xhdl4 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dl_rst_enter_comp_bit_xhdl16 : STD_LOGIC; + SIGNAL dl_rst_tx_margin_field_xhdl17 : STD_LOGIC; + SIGNAL dl_current_speed_xhdl8 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dl_current_deemp_xhdl7 : STD_LOGIC; + SIGNAL dl_link_auto_bdw_status_xhdl12 : STD_LOGIC; + SIGNAL dl_link_bdw_mng_status_xhdl13 : STD_LOGIC; + SIGNAL dl_ack_req_upfc_xhdl5 : STD_LOGIC; + SIGNAL dl_ack_snd_upfc_xhdl6 : STD_LOGIC; + SIGNAL test_out_hip_xhdl88 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ev_1us_xhdl26 : STD_LOGIC; + SIGNAL ev_128ns_xhdl25 : STD_LOGIC; + SIGNAL wake_oen_xhdl149 : STD_LOGIC; + SIGNAL serr_out_xhdl85 : STD_LOGIC; + SIGNAL rate_xhdl45 : STD_LOGIC; + SIGNAL txdata0_xhdl117 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak0_xhdl125 : STD_LOGIC; + SIGNAL txdetectrx0_xhdl133 : STD_LOGIC; + SIGNAL txelecidle0_xhdl141 : STD_LOGIC; + SIGNAL txcompl0_xhdl109 : STD_LOGIC; + SIGNAL rxpolarity0_xhdl77 : STD_LOGIC; + SIGNAL powerdown0_xhdl37 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txdata1_xhdl118 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak1_xhdl126 : STD_LOGIC; + SIGNAL txdetectrx1_xhdl134 : STD_LOGIC; + SIGNAL txelecidle1_xhdl142 : STD_LOGIC; + SIGNAL txcompl1_xhdl110 : STD_LOGIC; + SIGNAL rxpolarity1_xhdl78 : STD_LOGIC; + SIGNAL powerdown1_xhdl38 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txdata2_xhdl119 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak2_xhdl127 : STD_LOGIC; + SIGNAL txdetectrx2_xhdl135 : STD_LOGIC; + SIGNAL txelecidle2_xhdl143 : STD_LOGIC; + SIGNAL txcompl2_xhdl111 : STD_LOGIC; + SIGNAL rxpolarity2_xhdl79 : STD_LOGIC; + SIGNAL powerdown2_xhdl39 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txdata3_xhdl120 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak3_xhdl128 : STD_LOGIC; + SIGNAL txdetectrx3_xhdl136 : STD_LOGIC; + SIGNAL txelecidle3_xhdl144 : STD_LOGIC; + SIGNAL txcompl3_xhdl112 : STD_LOGIC; + SIGNAL rxpolarity3_xhdl80 : STD_LOGIC; + SIGNAL powerdown3_xhdl40 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txdata4_xhdl121 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak4_xhdl129 : STD_LOGIC; + SIGNAL txdetectrx4_xhdl137 : STD_LOGIC; + SIGNAL txelecidle4_xhdl145 : STD_LOGIC; + SIGNAL txcompl4_xhdl113 : STD_LOGIC; + SIGNAL rxpolarity4_xhdl81 : STD_LOGIC; + SIGNAL powerdown4_xhdl41 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txdata5_xhdl122 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak5_xhdl130 : STD_LOGIC; + SIGNAL txdetectrx5_xhdl138 : STD_LOGIC; + SIGNAL txelecidle5_xhdl146 : STD_LOGIC; + SIGNAL txcompl5_xhdl114 : STD_LOGIC; + SIGNAL rxpolarity5_xhdl82 : STD_LOGIC; + SIGNAL powerdown5_xhdl42 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txdata6_xhdl123 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak6_xhdl131 : STD_LOGIC; + SIGNAL txdetectrx6_xhdl139 : STD_LOGIC; + SIGNAL txelecidle6_xhdl147 : STD_LOGIC; + SIGNAL txcompl6_xhdl115 : STD_LOGIC; + SIGNAL rxpolarity6_xhdl83 : STD_LOGIC; + SIGNAL powerdown6_xhdl43 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL txdata7_xhdl124 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdatak7_xhdl132 : STD_LOGIC; + SIGNAL txdetectrx7_xhdl140 : STD_LOGIC; + SIGNAL txelecidle7_xhdl148 : STD_LOGIC; + SIGNAL txcompl7_xhdl116 : STD_LOGIC; + SIGNAL rxpolarity7_xhdl84 : STD_LOGIC; + SIGNAL powerdown7_xhdl44 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL mram_red_scout_xhdl35 : STD_LOGIC; + SIGNAL mram_regscanout_xhdl36 : STD_LOGIC; + SIGNAL derr_rpl_xhdl3 : STD_LOGIC; +BEGIN + -- Drive referenced outputs + mdio_out <= mdio_out_xhdl34; + data_enable_n <= data_enable_n_xhdl2; + dprio_curr_state <= dprio_curr_state_xhdl24; + lmi_dout <= lmi_dout_xhdl33; + lmi_ack <= lmi_ack_xhdl32; + reset_status <= reset_status_xhdl46; + l2_exit <= l2_exit_xhdl29; + hotrst_exit <= hotrst_exit_xhdl27; + dlup_exit <= dlup_exit_xhdl23; + core_clk_out <= core_clk_out_xhdl1; + swdn_wake <= swdn_wake_xhdl86; + swup_hotrst <= swup_hotrst_xhdl87; + rx_valid_vc0 <= rx_valid_vc0_xhdl75; + rx_err_vc0 <= rx_err_vc0_xhdl61; + rx_bar_dec_vc0 <= rx_bar_dec_vc0_xhdl47; + rx_sop_vc0_0 <= rx_sop_vc0_0_xhdl71; + rx_eop_vc0_0 <= rx_eop_vc0_0_xhdl57; + rx_data_vc0_0 <= rx_data_vc0_0_xhdl53; + rx_be_vc0_0 <= rx_be_vc0_0_xhdl49; + rx_sop_vc0_1 <= rx_sop_vc0_1_xhdl72; + rx_eop_vc0_1 <= rx_eop_vc0_1_xhdl58; + rx_data_vc0_1 <= rx_data_vc0_1_xhdl54; + rx_be_vc0_1 <= rx_be_vc0_1_xhdl50; + rx_fifo_full_vc0 <= rx_fifo_full_vc0_xhdl65; + rx_fifo_empty_vc0 <= rx_fifo_empty_vc0_xhdl63; + rx_fifo_wrp_vc0 <= rx_fifo_wrp_vc0_xhdl69; + rx_fifo_rdp_vc0 <= rx_fifo_rdp_vc0_xhdl67; + tx_cred_vc0 <= tx_cred_vc0_xhdl97; + tx_ready_vc0 <= tx_ready_vc0_xhdl107; + tx_fifo_full_vc0 <= tx_fifo_full_vc0_xhdl101; + tx_fifo_empty_vc0 <= tx_fifo_empty_vc0_xhdl99; + tx_fifo_wrp_vc0 <= tx_fifo_wrp_vc0_xhdl105; + tx_fifo_rdp_vc0 <= tx_fifo_rdp_vc0_xhdl103; + rx_valid_vc1 <= rx_valid_vc1_xhdl76; + rx_err_vc1 <= rx_err_vc1_xhdl62; + rx_bar_dec_vc1 <= rx_bar_dec_vc1_xhdl48; + rx_sop_vc1_0 <= rx_sop_vc1_0_xhdl73; + rx_eop_vc1_0 <= rx_eop_vc1_0_xhdl59; + rx_data_vc1_0 <= rx_data_vc1_0_xhdl55; + rx_be_vc1_0 <= rx_be_vc1_0_xhdl51; + rx_sop_vc1_1 <= rx_sop_vc1_1_xhdl74; + rx_eop_vc1_1 <= rx_eop_vc1_1_xhdl60; + rx_data_vc1_1 <= rx_data_vc1_1_xhdl56; + rx_be_vc1_1 <= rx_be_vc1_1_xhdl52; + rx_fifo_full_vc1 <= rx_fifo_full_vc1_xhdl66; + rx_fifo_empty_vc1 <= rx_fifo_empty_vc1_xhdl64; + rx_fifo_wrp_vc1 <= rx_fifo_wrp_vc1_xhdl70; + rx_fifo_rdp_vc1 <= rx_fifo_rdp_vc1_xhdl68; + tx_cred_vc1 <= tx_cred_vc1_xhdl98; + tx_ready_vc1 <= tx_ready_vc1_xhdl108; + tx_fifo_full_vc1 <= tx_fifo_full_vc1_xhdl102; + tx_fifo_empty_vc1 <= tx_fifo_empty_vc1_xhdl100; + tx_fifo_wrp_vc1 <= tx_fifo_wrp_vc1_xhdl106; + tx_fifo_rdp_vc1 <= tx_fifo_rdp_vc1_xhdl104; + tl_pme_to_sr <= tl_pme_to_sr_xhdl96; + tl_cfg_sts <= tl_cfg_sts_xhdl94; + tl_cfg_sts_wr <= tl_cfg_sts_wr_xhdl95; + tl_cfg_ctl <= tl_cfg_ctl_xhdl92; + tl_cfg_ctl_wr <= tl_cfg_ctl_wr_xhdl93; + tl_cfg_add <= tl_cfg_add_xhdl91; + tl_app_inta_ack <= tl_app_inta_ack_xhdl89; + tl_app_msi_ack <= tl_app_msi_ack_xhdl90; + int_status <= int_status_xhdl28; + dl_up <= dl_up_xhdl21; + dl_vc_status <= dl_vc_status_xhdl22; + dl_err_dll <= dl_err_dll_xhdl10; + dl_err_phy <= dl_err_phy_xhdl11; + dl_rpbuf_emp <= dl_rpbuf_emp_xhdl15; + dl_dll_req <= dl_dll_req_xhdl9; + lane_act <= lane_act_xhdl30; + link_up <= link_up_xhdl31; + dl_ltssm <= dl_ltssm_xhdl14; + clr_rxpath <= clr_rxpath_xhdl0; + dl_rx_val_pm <= dl_rx_val_pm_xhdl19; + dl_rx_typ_pm <= dl_rx_typ_pm_xhdl18; + dl_tx_ack_pm <= dl_tx_ack_pm_xhdl20; + dl_ack_phypm <= dl_ack_phypm_xhdl4; + dl_rst_enter_comp_bit <= dl_rst_enter_comp_bit_xhdl16; + dl_rst_tx_margin_field <= dl_rst_tx_margin_field_xhdl17; + dl_current_speed <= dl_current_speed_xhdl8; + dl_current_deemp <= dl_current_deemp_xhdl7; + dl_link_auto_bdw_status <= dl_link_auto_bdw_status_xhdl12; + dl_link_bdw_mng_status <= dl_link_bdw_mng_status_xhdl13; + dl_ack_req_upfc <= dl_ack_req_upfc_xhdl5; + dl_ack_snd_upfc <= dl_ack_snd_upfc_xhdl6; + test_out_hip <= test_out_hip_xhdl88; + ev_1us <= ev_1us_xhdl26; + ev_128ns <= ev_128ns_xhdl25; + wake_oen <= wake_oen_xhdl149; + serr_out <= serr_out_xhdl85; + rate <= rate_xhdl45; + txdata0 <= txdata0_xhdl117; + txdatak0 <= txdatak0_xhdl125; + txdetectrx0 <= txdetectrx0_xhdl133; + txelecidle0 <= txelecidle0_xhdl141; + txcompl0 <= txcompl0_xhdl109; + rxpolarity0 <= rxpolarity0_xhdl77; + powerdown0 <= powerdown0_xhdl37; + txdata1 <= txdata1_xhdl118; + txdatak1 <= txdatak1_xhdl126; + txdetectrx1 <= txdetectrx1_xhdl134; + txelecidle1 <= txelecidle1_xhdl142; + txcompl1 <= txcompl1_xhdl110; + rxpolarity1 <= rxpolarity1_xhdl78; + powerdown1 <= powerdown1_xhdl38; + txdata2 <= txdata2_xhdl119; + txdatak2 <= txdatak2_xhdl127; + txdetectrx2 <= txdetectrx2_xhdl135; + txelecidle2 <= txelecidle2_xhdl143; + txcompl2 <= txcompl2_xhdl111; + rxpolarity2 <= rxpolarity2_xhdl79; + powerdown2 <= powerdown2_xhdl39; + txdata3 <= txdata3_xhdl120; + txdatak3 <= txdatak3_xhdl128; + txdetectrx3 <= txdetectrx3_xhdl136; + txelecidle3 <= txelecidle3_xhdl144; + txcompl3 <= txcompl3_xhdl112; + rxpolarity3 <= rxpolarity3_xhdl80; + powerdown3 <= powerdown3_xhdl40; + txdata4 <= txdata4_xhdl121; + txdatak4 <= txdatak4_xhdl129; + txdetectrx4 <= txdetectrx4_xhdl137; + txelecidle4 <= txelecidle4_xhdl145; + txcompl4 <= txcompl4_xhdl113; + rxpolarity4 <= rxpolarity4_xhdl81; + powerdown4 <= powerdown4_xhdl41; + txdata5 <= txdata5_xhdl122; + txdatak5 <= txdatak5_xhdl130; + txdetectrx5 <= txdetectrx5_xhdl138; + txelecidle5 <= txelecidle5_xhdl146; + txcompl5 <= txcompl5_xhdl114; + rxpolarity5 <= rxpolarity5_xhdl82; + powerdown5 <= powerdown5_xhdl42; + txdata6 <= txdata6_xhdl123; + txdatak6 <= txdatak6_xhdl131; + txdetectrx6 <= txdetectrx6_xhdl139; + txelecidle6 <= txelecidle6_xhdl147; + txcompl6 <= txcompl6_xhdl115; + rxpolarity6 <= rxpolarity6_xhdl83; + powerdown6 <= powerdown6_xhdl43; + txdata7 <= txdata7_xhdl124; + txdatak7 <= txdatak7_xhdl132; + txdetectrx7 <= txdetectrx7_xhdl140; + txelecidle7 <= txelecidle7_xhdl148; + txcompl7 <= txcompl7_xhdl116; + rxpolarity7 <= rxpolarity7_xhdl84; + powerdown7 <= powerdown7_xhdl44; + mram_red_scout <= mram_red_scout_xhdl35; + mram_regscanout <= mram_regscanout_xhdl36; + derr_rpl <= derr_rpl_xhdl3; + + -- cycloneiv: cycloneiv specific to pass pcs wrap back control to digi_quad_wrapper + dq_pcs_side_pcs_wrpbck <= dq_pld_side_pcs_wrpbck_rpidft; + + -- Tie off extra outputs + hip_extraclkout <= "00"; + hip_extraout(3 DOWNTO 1) <= "000"; + hip_extraout(6 DOWNTO 4) <= "111"; + -- Use the hip_extraout[0] for successful_speed_negotiation_int to user logic to reset Word Align in PCS + hip_extraout(0) <= successful_speed_negotiation_int; + + -- Disable Serial Mode for this project + ser_si <= '0'; + serial_mode <= '0'; + + -- Decode LTSSM L0 state from the dl_ltssm bus + ltssm_l0_state <= '1' WHEN (dl_ltssm_xhdl14 = "01111") ELSE + '0'; + + -- Muxing RX Debug signals and RX normal op signals + + rxstatus0_muxout <= dbg_pipex1_rx(14 DOWNTO 12) WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus0; + rxelecidle0_muxout <= dbg_pipex1_rx(11) WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle0; + phystatus0_muxout <= dbg_pipex1_rx(10) WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus0; + rxvalid0_muxout <= dbg_pipex1_rx(9) WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid0; + rxdatak0_muxout <= dbg_pipex1_rx(8) WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak0; + rxdata0_muxout <= dbg_pipex1_rx(7 DOWNTO 0) WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata0; + + rxstatus1_muxout <= "000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus1; + rxelecidle1_muxout <= '1' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle1; + phystatus1_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus1; + rxvalid1_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid1; + rxdatak1_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak1; + rxdata1_muxout <= "00000000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata1; + + rxstatus2_muxout <= "000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus2; + rxelecidle2_muxout <= '1' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle2; + phystatus2_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus2; + rxvalid2_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid2; + rxdatak2_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak2; + rxdata2_muxout <= "00000000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata2; + + rxstatus3_muxout <= "000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus3; + rxelecidle3_muxout <= '1' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle3; + phystatus3_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus3; + rxvalid3_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid3; + rxdatak3_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak3; + rxdata3_muxout <= "00000000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata3; + + rxstatus4_muxout <= "000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus4; + rxelecidle4_muxout <= '1' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle4; + phystatus4_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus4; + rxvalid4_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid4; + rxdatak4_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak4; + rxdata4_muxout <= "00000000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata4; + + rxstatus5_muxout <= "000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus5; + rxelecidle5_muxout <= '1' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle5; + phystatus5_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus5; + rxvalid5_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid5; + rxdatak5_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak5; + rxdata5_muxout <= "00000000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata5; + + rxstatus6_muxout <= "000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus6; + rxelecidle6_muxout <= '1' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle6; + phystatus6_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus6; + rxvalid6_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid6; + rxdatak6_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak6; + rxdata6_muxout <= "00000000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata6; + + rxstatus7_muxout <= "000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxstatus7; + rxelecidle7_muxout <= '1' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxelecidle7; + phystatus7_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + phystatus7; + rxvalid7_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxvalid7; + rxdatak7_muxout <= '0' WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdatak7; + rxdata7_muxout <= "00000000" WHEN (k_pipex1_dbg_sel = '1') ELSE + rxdata7; + + -- Tapping off from Ch.0 TX signals to drive the TX Debug signals + dbg_pipex1_tx(14 DOWNTO 0) <= (powerdown0_xhdl37 & rxpolarity0_xhdl77 & txcompl0_xhdl109 & txelecidle0_xhdl141 & txdetectrx0_xhdl133 & txdatak0_xhdl125 & txdata0_xhdl117); + + -- Mux dbg_pipex1_tx signals with BIST and ECC output signals + derr_cor_ext_rcv1 <= dbg_pipex1_tx(14) WHEN (k_pipex1_dbg_sel = '1') ELSE + derr_cor_ext_rcv1_int; + bist_pass_rcv1 <= dbg_pipex1_tx(13) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_pass_rcv1_int; + bist_doneb_rcv1 <= dbg_pipex1_tx(12) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_doneb_rcv1_int; + bist_donea_rcv1 <= dbg_pipex1_tx(11) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_donea_rcv1_int; + bist_scanout_rcv1 <= dbg_pipex1_tx(10) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_scanout_rcv1_int; + + derr_cor_ext_rcv0 <= dbg_pipex1_tx(9) WHEN (k_pipex1_dbg_sel = '1') ELSE + derr_cor_ext_rcv0_int; + bist_pass_rcv0 <= dbg_pipex1_tx(8) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_pass_rcv0_int; + bist_doneb_rcv0 <= dbg_pipex1_tx(7) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_doneb_rcv0_int; + bist_donea_rcv0 <= dbg_pipex1_tx(6) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_donea_rcv0_int; + bist_scanout_rcv0 <= dbg_pipex1_tx(5) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_scanout_rcv0_int; + + derr_cor_ext_rpl <= dbg_pipex1_tx(4) WHEN (k_pipex1_dbg_sel = '1') ELSE + derr_cor_ext_rpl_int; + bist_pass_rpl <= dbg_pipex1_tx(3) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_pass_rpl_int; + bist_doneb_rpl <= dbg_pipex1_tx(2) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_doneb_rpl_int; + bist_donea_rpl <= dbg_pipex1_tx(1) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_donea_rpl_int; + bist_scanout_rpl <= dbg_pipex1_tx(0) WHEN (k_pipex1_dbg_sel = '1') ELSE + bist_scanout_rpl_int; + + -- Configuration bits assignment + -- Hard-wired value for k_gbl is now done inside the pciexp_top_hip module + --assign k_gbl[15:0] = {4'b1111, 1'b0, out_hip_ctrl_1[10], 1'b1, 1'b1, 6'b000000,out_hip_ctrl_1[1:0]}; // + -- k_gbl[15:12]=1111 type of core controlled by mode[1:0] signal for RP, EP shared silicon + -- k_gbl[11]=0 if core is instantiated + -- k_gbl[10]=0 cut-through mode disabled; 1 cut-through mode enabled + -- k_gbl[9]: 1: slot reg implemented (harden to 1) + -- k_gbl[8]: 1: 250Mhz; 0 125Mhz (harden to 1) + -- k_gbl[7:2]=000000 to disable VC7 to VC2 + -- k_gbl[0] = PCIe 1.1a (1) or PCie 1.0 (0) + --assign k_gbl[31:16] = {4'b0000, out_hip_ctrl_2[11],1'b1, 1'b0, 1'b0, out_hip_ctrl_2[7], 7'b0000000}; // + -- k_gbl[31:28]=0000 receiver detected all lanes + -- k_gbl[27]=0 rx buffer date checking disabled; 1: rx buffer date checking enabled + -- k_gbl[26]=1 re-ordering enabled in RX + -- k_gbl[25]=0 to indicate of separated RX buffers + -- k_gbl[24]: reserved + -- k_gbl[23]: CDC enable + -- k_gbl[22:16]: 0000000: single function enabled + k_gbl(15 DOWNTO 0) <= out_hip_ctrl_1; + k_gbl(31 DOWNTO 16) <= out_hip_ctrl_2; + k_gbl(47 DOWNTO 32) <= out_hip_ctrl_3; + k_gbl(63 DOWNTO 48) <= out_hip_ctrl_4; + k_dev(4 DOWNTO 0) <= out_hip_ctrl_5(15 DOWNTO 11); + k_port(7 DOWNTO 0) <= out_hip_ctrl_5(7 DOWNTO 0); + + -- Register 6[6:0] for clk mux selection, bit [7] to select dbg_pipex1_rx or dbg_pipex1_tx signals, bit [8] to enable IEI logic + k_clk_x8_sel_rtry <= (out_hip_ctrl_7(8 DOWNTO 7) & out_hip_ctrl_6(15 DOWNTO 14)); + k_clk_x8_sel_rcv1 <= (out_hip_ctrl_7(6 DOWNTO 5) & out_hip_ctrl_6(13 DOWNTO 12)); + k_clk_x8_sel_rcv0 <= (out_hip_ctrl_7(4 DOWNTO 3) & out_hip_ctrl_6(11 DOWNTO 10)); + -- assign k_iei_enable = out_hip_ctrl_6[9:8]; // Moved to 006Ah address + + k_pipex1_dbg_sel <= out_hip_ctrl_6(7); + + k_pclk_sel <= out_hip_ctrl_6(6); + k_core_clk_source_sel <= out_hip_ctrl_6(5 DOWNTO 4); + k_core_clk_div_sel <= out_hip_ctrl_6(3 DOWNTO 1); + k_core_clk_out_sel <= out_hip_ctrl_6(0); + k_core_clk_dbg_sel <= out_hip_ctrl_7(9); + + -- Register 7 is used for Adapter functions + + k_ecc_enable_rcv0 <= '0'; --shawn out_hip_ctrl_7[0]; + k_ecc_enable_rcv1 <= '0'; --shawn out_hip_ctrl_7[1]; + k_ecc_enable_rtry <= '0'; --shawn out_hip_ctrl_7[2]; + k_hip(7 DOWNTO 4) <= out_hip_ctrl_7(15 DOWNTO 12); + + -- Register 8 is used for Adapter functions + + k_hip(11 DOWNTO 8) <= out_hip_ctrl_8(3 DOWNTO 0); + k_hip(16 DOWNTO 12) <= out_hip_ctrl_8(8 DOWNTO 4); + k_hip(22 DOWNTO 17) <= out_hip_ctrl_8(14 DOWNTO 9); + + k_conf_func0(15 DOWNTO 0) <= out_hip_ctrl_9; + k_conf_func0(31 DOWNTO 16) <= out_hip_ctrl_10; + k_conf_func0(47 DOWNTO 32) <= out_hip_ctrl_11; + k_conf_func0(63 DOWNTO 48) <= out_hip_ctrl_12; + k_conf_func0(79 DOWNTO 64) <= out_hip_ctrl_13; + k_conf_func0(95 DOWNTO 80) <= out_hip_ctrl_14; + k_conf_func0(111 DOWNTO 96) <= out_hip_ctrl_15; + k_conf_func0(127 DOWNTO 112) <= out_hip_ctrl_16; + k_conf_func0(143 DOWNTO 128) <= out_hip_ctrl_17; + k_conf_func0(159 DOWNTO 144) <= out_hip_ctrl_18; + k_conf_func0(175 DOWNTO 160) <= out_hip_ctrl_19; + k_conf_func0(191 DOWNTO 176) <= out_hip_ctrl_20; + k_conf_func0(207 DOWNTO 192) <= out_hip_ctrl_21; + k_conf_func0(223 DOWNTO 208) <= out_hip_ctrl_22; + k_conf_func0(239 DOWNTO 224) <= out_hip_ctrl_23; + k_conf_func0(255 DOWNTO 240) <= out_hip_ctrl_24; + k_conf_func0(271 DOWNTO 256) <= out_hip_ctrl_25; + k_conf_func0(287 DOWNTO 272) <= out_hip_ctrl_26; + k_conf_func0(303 DOWNTO 288) <= out_hip_ctrl_27; + k_conf_func0(319 DOWNTO 304) <= out_hip_ctrl_28; + k_conf_func0(335 DOWNTO 320) <= out_hip_ctrl_29; + k_conf_func0(351 DOWNTO 336) <= out_hip_ctrl_30; + k_conf_func0(367 DOWNTO 352) <= out_hip_ctrl_31; + k_conf_func0(383 DOWNTO 368) <= out_hip_ctrl_32; + k_bar_func0(15 DOWNTO 0) <= out_hip_ctrl_33; + k_bar_func0(31 DOWNTO 16) <= out_hip_ctrl_34; + k_bar_func0(47 DOWNTO 32) <= out_hip_ctrl_35; + k_bar_func0(63 DOWNTO 48) <= out_hip_ctrl_36; + k_bar_func0(79 DOWNTO 64) <= out_hip_ctrl_37; + k_bar_func0(95 DOWNTO 80) <= out_hip_ctrl_38; + k_bar_func0(111 DOWNTO 96) <= out_hip_ctrl_39; + k_bar_func0(127 DOWNTO 112) <= out_hip_ctrl_40; + k_bar_func0(143 DOWNTO 128) <= out_hip_ctrl_41; + k_bar_func0(159 DOWNTO 144) <= out_hip_ctrl_42; + k_bar_func0(175 DOWNTO 160) <= out_hip_ctrl_43; + k_bar_func0(191 DOWNTO 176) <= out_hip_ctrl_44; + k_bar_func0(207 DOWNTO 192) <= out_hip_ctrl_45; + k_bar_func0(223 DOWNTO 208) <= out_hip_ctrl_46; + k_bar_func0(227 DOWNTO 224) <= out_hip_ctrl_47(3 DOWNTO 0); + k_cnt(15 DOWNTO 0) <= out_hip_ctrl_48; + k_cnt(31 DOWNTO 16) <= out_hip_ctrl_49; + k_cnt(47 DOWNTO 32) <= out_hip_ctrl_50; + k_cnt(63 DOWNTO 48) <= out_hip_ctrl_51; + k_cnt(79 DOWNTO 64) <= out_hip_ctrl_52; + k_cnt(95 DOWNTO 80) <= out_hip_ctrl_53; + k_cnt(111 DOWNTO 96) <= out_hip_ctrl_54; + k_cnt(127 DOWNTO 112) <= out_hip_ctrl_55; + k_vc0(15 DOWNTO 0) <= out_hip_ctrl_56; + k_vc0(31 DOWNTO 16) <= out_hip_ctrl_57; + k_vc0(47 DOWNTO 32) <= out_hip_ctrl_58; + k_vc0(55 DOWNTO 48) <= out_hip_ctrl_59(7 DOWNTO 0); + k_vc1(15 DOWNTO 0) <= out_hip_ctrl_60; + k_vc1(31 DOWNTO 16) <= out_hip_ctrl_61; + k_vc1(47 DOWNTO 32) <= out_hip_ctrl_62; + k_vc1(55 DOWNTO 48) <= out_hip_ctrl_63(7 DOWNTO 0); + k_vc2(15 DOWNTO 0) <= out_hip_ctrl_64; + k_vc2(31 DOWNTO 16) <= out_hip_ctrl_65; + k_vc2(47 DOWNTO 32) <= out_hip_ctrl_66; + k_vc2(55 DOWNTO 48) <= out_hip_ctrl_67(7 DOWNTO 0); + k_vc3(15 DOWNTO 0) <= out_hip_ctrl_68; + k_vc3(31 DOWNTO 16) <= out_hip_ctrl_69; + k_vc3(47 DOWNTO 32) <= out_hip_ctrl_70; + k_vc3(55 DOWNTO 48) <= out_hip_ctrl_71(7 DOWNTO 0); + k_vc4(15 DOWNTO 0) <= out_hip_ctrl_72; + k_vc4(31 DOWNTO 16) <= out_hip_ctrl_73; + k_vc4(47 DOWNTO 32) <= out_hip_ctrl_74; + k_vc4(55 DOWNTO 48) <= out_hip_ctrl_75(7 DOWNTO 0); + k_vc5(15 DOWNTO 0) <= out_hip_ctrl_76; + k_vc5(31 DOWNTO 16) <= out_hip_ctrl_77; + k_vc5(47 DOWNTO 32) <= out_hip_ctrl_78; + k_vc5(55 DOWNTO 48) <= out_hip_ctrl_79(7 DOWNTO 0); + k_vc6(15 DOWNTO 0) <= out_hip_ctrl_80; + k_vc6(31 DOWNTO 16) <= out_hip_ctrl_81; + k_vc6(47 DOWNTO 32) <= out_hip_ctrl_82; + k_vc6(55 DOWNTO 48) <= out_hip_ctrl_83(7 DOWNTO 0); + k_vc7(15 DOWNTO 0) <= out_hip_ctrl_84; + k_vc7(31 DOWNTO 16) <= out_hip_ctrl_85; + k_vc7(47 DOWNTO 32) <= out_hip_ctrl_86; + k_vc7(55 DOWNTO 48) <= out_hip_ctrl_87(7 DOWNTO 0); + -- cycloneiv + --k_hip(3 DOWNTO 0) <= (out_hip_ctrl_88(15) & out_hip_ctrl_88(14) & out_hip_ctrl_88(13) & out_hip_ctrl_88(12)); + k_hip(3 DOWNTO 0) <= (out_hip_ctrl_88(15) & '0' & out_hip_ctrl_88(13) & out_hip_ctrl_88(12)); + --k_rtry(10 DOWNTO 0) <= out_hip_ctrl_88(10 DOWNTO 0); + k_rtry(7 DOWNTO 0) <= out_hip_ctrl_88(7 DOWNTO 0); + --k_ptr0(43 DOWNTO 32) <= out_hip_ctrl_91(11 DOWNTO 0); + k_ptr0(35 DOWNTO 32) <= out_hip_ctrl_91(3 DOWNTO 0); + --k_ptr1(43 DOWNTO 32) <= out_hip_ctrl_94(11 DOWNTO 0); + k_ptr1(35 DOWNTO 32) <= out_hip_ctrl_94(3 DOWNTO 0); + + k_ptr0(15 DOWNTO 0) <= out_hip_ctrl_89; + k_ptr0(31 DOWNTO 16) <= out_hip_ctrl_90; + k_ptr1(15 DOWNTO 0) <= out_hip_ctrl_92; + k_ptr1(31 DOWNTO 16) <= out_hip_ctrl_93; + k_mem_bist(15 DOWNTO 0) <= out_hip_ctrl_95; + k_mem_bist(31 DOWNTO 16) <= out_hip_ctrl_96; + k_mem_bist(47 DOWNTO 32) <= out_hip_ctrl_97; + k_mem_bist(63 DOWNTO 48) <= out_hip_ctrl_98; + k_mem_bist(74 DOWNTO 64) <= out_hip_ctrl_99(10 DOWNTO 0); + k_rtry_mem(29 DOWNTO 0) <= (out_hip_ctrl_103(14 DOWNTO 0) & out_hip_ctrl_100(14 DOWNTO 0)); + k_rcv0_mem(29 DOWNTO 0) <= (out_hip_ctrl_104(14 DOWNTO 0) & out_hip_ctrl_101(14 DOWNTO 0)); + k_rcv1_mem(29 DOWNTO 0) <= (out_hip_ctrl_105(14 DOWNTO 0) & out_hip_ctrl_102(14 DOWNTO 0)); + k_iei_enable <= out_hip_ctrl_106(5 DOWNTO 0); + + -- Fan out PIPE signals to 8 PCS channels + eidle_infer_sel0 <= eidle_infer_sel; + eidle_infer_sel1 <= eidle_infer_sel; + eidle_infer_sel2 <= eidle_infer_sel; + eidle_infer_sel3 <= eidle_infer_sel; + eidle_infer_sel4 <= eidle_infer_sel; + eidle_infer_sel5 <= eidle_infer_sel; + eidle_infer_sel6 <= eidle_infer_sel; + eidle_infer_sel7 <= eidle_infer_sel; + + tx_deemph0 <= tx_deemph; + tx_deemph1 <= tx_deemph; + tx_deemph2 <= tx_deemph; + tx_deemph3 <= tx_deemph; + tx_deemph4 <= tx_deemph; + tx_deemph5 <= tx_deemph; + tx_deemph6 <= tx_deemph; + tx_deemph7 <= tx_deemph; + + tx_margin0 <= tx_margin; + tx_margin1 <= tx_margin; + tx_margin2 <= tx_margin; + tx_margin3 <= tx_margin; + tx_margin4 <= tx_margin; + tx_margin5 <= tx_margin; + tx_margin6 <= tx_margin; + tx_margin7 <= tx_margin; + + -- add tied to ground rate. it is connected to slave PCS quad + rate_tied_to_gnd <= '0'; + + -- Fixing polarity of Reset and Scan signals + + pld_rstn <= NOT(pld_rst); + phy_rstn <= NOT(phy_rst); + core_rstn <= NOT(core_rst); + core_npor <= NOT(core_por); + + scan_mode <= NOT(scan_mode_n); + + -- Internal Hard Reset + + hard_reset <= (NOT((plniotri AND NOT(entest) AND npor))) OR phy_rst; + + core_crst_int <= core_crst OR hard_reset; + core_srst_int <= core_srst OR hard_reset; + phy_srst_int <= phy_srst OR hard_reset; + pld_srst_int <= pld_srst OR hard_reset; + + core_rstn_int <= core_rstn AND (NOT(hard_reset)); + core_npor_int <= core_npor AND (NOT(hard_reset)); + phy_rstn_int <= phy_rstn AND (NOT(hard_reset)); + pld_rstn_int <= pld_rstn AND (NOT(hard_reset)); + + -- DPRIO module + tmp_csr_hip_in <= (csr_hip_in_reserved & csr_hip_in); --shawn + + + + dprio : cycloneiv_pciehip_hip_dprio_top + PORT MAP ( + mdc => mdc, + dev_addr => dev_addr, + port_addr => port_addr, + mdio_in => mdio_in, + mdio_dis => mdio_dis, + mdio_rst => hard_reset, + serial_mode => serial_mode, + ser_shift_load => ser_shift_load, + ser_si => ser_si, + csr_hip_in => tmp_csr_hip_in, --shawn + -- .csr_hip_in({csr_hip_in_reserved,csr_hip_in}), //shawn + hip_base_addr => hip_base_addr, + ser_so => ser_so, + mdio_out => mdio_out_xhdl34, + data_enable_n => data_enable_n_xhdl2, + curr_state => dprio_curr_state_xhdl24, + out_hip_ctrl_1 => out_hip_ctrl_1, + out_hip_ctrl_2 => out_hip_ctrl_2, + out_hip_ctrl_3 => out_hip_ctrl_3, + out_hip_ctrl_4 => out_hip_ctrl_4, + out_hip_ctrl_5 => out_hip_ctrl_5, + out_hip_ctrl_6 => out_hip_ctrl_6, + out_hip_ctrl_7 => out_hip_ctrl_7, + out_hip_ctrl_8 => out_hip_ctrl_8, + out_hip_ctrl_9 => out_hip_ctrl_9, + out_hip_ctrl_10 => out_hip_ctrl_10, + out_hip_ctrl_11 => out_hip_ctrl_11, + out_hip_ctrl_12 => out_hip_ctrl_12, + out_hip_ctrl_13 => out_hip_ctrl_13, + out_hip_ctrl_14 => out_hip_ctrl_14, + out_hip_ctrl_15 => out_hip_ctrl_15, + out_hip_ctrl_16 => out_hip_ctrl_16, + out_hip_ctrl_17 => out_hip_ctrl_17, + out_hip_ctrl_18 => out_hip_ctrl_18, + out_hip_ctrl_19 => out_hip_ctrl_19, + out_hip_ctrl_20 => out_hip_ctrl_20, + out_hip_ctrl_21 => out_hip_ctrl_21, + out_hip_ctrl_22 => out_hip_ctrl_22, + out_hip_ctrl_23 => out_hip_ctrl_23, + out_hip_ctrl_24 => out_hip_ctrl_24, + out_hip_ctrl_25 => out_hip_ctrl_25, + out_hip_ctrl_26 => out_hip_ctrl_26, + out_hip_ctrl_27 => out_hip_ctrl_27, + out_hip_ctrl_28 => out_hip_ctrl_28, + out_hip_ctrl_29 => out_hip_ctrl_29, + out_hip_ctrl_30 => out_hip_ctrl_30, + out_hip_ctrl_31 => out_hip_ctrl_31, + out_hip_ctrl_32 => out_hip_ctrl_32, + out_hip_ctrl_33 => out_hip_ctrl_33, + out_hip_ctrl_34 => out_hip_ctrl_34, + out_hip_ctrl_35 => out_hip_ctrl_35, + out_hip_ctrl_36 => out_hip_ctrl_36, + out_hip_ctrl_37 => out_hip_ctrl_37, + out_hip_ctrl_38 => out_hip_ctrl_38, + out_hip_ctrl_39 => out_hip_ctrl_39, + out_hip_ctrl_40 => out_hip_ctrl_40, + out_hip_ctrl_41 => out_hip_ctrl_41, + out_hip_ctrl_42 => out_hip_ctrl_42, + out_hip_ctrl_43 => out_hip_ctrl_43, + out_hip_ctrl_44 => out_hip_ctrl_44, + out_hip_ctrl_45 => out_hip_ctrl_45, + out_hip_ctrl_46 => out_hip_ctrl_46, + out_hip_ctrl_47 => out_hip_ctrl_47, + out_hip_ctrl_48 => out_hip_ctrl_48, + out_hip_ctrl_49 => out_hip_ctrl_49, + out_hip_ctrl_50 => out_hip_ctrl_50, + out_hip_ctrl_51 => out_hip_ctrl_51, + out_hip_ctrl_52 => out_hip_ctrl_52, + out_hip_ctrl_53 => out_hip_ctrl_53, + out_hip_ctrl_54 => out_hip_ctrl_54, + out_hip_ctrl_55 => out_hip_ctrl_55, + out_hip_ctrl_56 => out_hip_ctrl_56, + out_hip_ctrl_57 => out_hip_ctrl_57, + out_hip_ctrl_58 => out_hip_ctrl_58, + out_hip_ctrl_59 => out_hip_ctrl_59, + out_hip_ctrl_60 => out_hip_ctrl_60, + out_hip_ctrl_61 => out_hip_ctrl_61, + out_hip_ctrl_62 => out_hip_ctrl_62, + out_hip_ctrl_63 => out_hip_ctrl_63, + out_hip_ctrl_64 => out_hip_ctrl_64, + out_hip_ctrl_65 => out_hip_ctrl_65, + out_hip_ctrl_66 => out_hip_ctrl_66, + out_hip_ctrl_67 => out_hip_ctrl_67, + out_hip_ctrl_68 => out_hip_ctrl_68, + out_hip_ctrl_69 => out_hip_ctrl_69, + out_hip_ctrl_70 => out_hip_ctrl_70, + out_hip_ctrl_71 => out_hip_ctrl_71, + out_hip_ctrl_72 => out_hip_ctrl_72, + out_hip_ctrl_73 => out_hip_ctrl_73, + out_hip_ctrl_74 => out_hip_ctrl_74, + out_hip_ctrl_75 => out_hip_ctrl_75, + out_hip_ctrl_76 => out_hip_ctrl_76, + out_hip_ctrl_77 => out_hip_ctrl_77, + out_hip_ctrl_78 => out_hip_ctrl_78, + out_hip_ctrl_79 => out_hip_ctrl_79, + out_hip_ctrl_80 => out_hip_ctrl_80, + out_hip_ctrl_81 => out_hip_ctrl_81, + out_hip_ctrl_82 => out_hip_ctrl_82, + out_hip_ctrl_83 => out_hip_ctrl_83, + out_hip_ctrl_84 => out_hip_ctrl_84, + out_hip_ctrl_85 => out_hip_ctrl_85, + out_hip_ctrl_86 => out_hip_ctrl_86, + out_hip_ctrl_87 => out_hip_ctrl_87, + out_hip_ctrl_88 => out_hip_ctrl_88, + out_hip_ctrl_89 => out_hip_ctrl_89, + out_hip_ctrl_90 => out_hip_ctrl_90, + out_hip_ctrl_91 => out_hip_ctrl_91, + out_hip_ctrl_92 => out_hip_ctrl_92, + out_hip_ctrl_93 => out_hip_ctrl_93, + out_hip_ctrl_94 => out_hip_ctrl_94, + out_hip_ctrl_95 => out_hip_ctrl_95, + out_hip_ctrl_96 => out_hip_ctrl_96, + out_hip_ctrl_97 => out_hip_ctrl_97, + out_hip_ctrl_98 => out_hip_ctrl_98, + out_hip_ctrl_99 => out_hip_ctrl_99, + out_hip_ctrl_100 => out_hip_ctrl_100, + out_hip_ctrl_101 => out_hip_ctrl_101, + out_hip_ctrl_102 => out_hip_ctrl_102, + out_hip_ctrl_103 => out_hip_ctrl_103, + out_hip_ctrl_104 => out_hip_ctrl_104, + out_hip_ctrl_105 => out_hip_ctrl_105, + out_hip_ctrl_106 => out_hip_ctrl_106, + out_hip_ctrl_107 => out_hip_ctrl_107, + out_hip_ctrl_108 => out_hip_ctrl_108, + out_hip_ctrl_109 => out_hip_ctrl_109, + out_hip_ctrl_110 => out_hip_ctrl_110 + ); + + rxelecidle7_infer <= temp(7); + rxelecidle6_infer <= temp(6); + rxelecidle5_infer <= temp(5); + rxelecidle4_infer <= temp(4); + rxelecidle3_infer <= temp(3); + rxelecidle2_infer <= temp(2); + rxelecidle1_infer <= temp(1); + rxelecidle0_infer <= temp(0); + -- Electrical Idle Inferral module + + + xhdl150 <= (rxdatak0_muxout & rxdata0_muxout); + xhdl151 <= (rxdatak1_muxout & rxdata1_muxout); + xhdl152 <= (rxdatak2_muxout & rxdata2_muxout); + xhdl153 <= (rxdatak3_muxout & rxdata3_muxout); + xhdl154 <= (rxdatak4_muxout & rxdata4_muxout); + xhdl155 <= (rxdatak5_muxout & rxdata5_muxout); + xhdl156 <= (rxdatak6_muxout & rxdata6_muxout); + xhdl157 <= (rxdatak7_muxout & rxdata7_muxout); + xhdl158 <= (rxelecidle7_muxout & rxelecidle6_muxout & rxelecidle5_muxout & rxelecidle4_muxout & rxelecidle3_muxout & rxelecidle2_muxout & rxelecidle1_muxout & rxelecidle0_muxout); + xhdl159 <= (rxvalid7_muxout & rxvalid6_muxout & rxvalid5_muxout & rxvalid4_muxout & rxvalid3_muxout & rxvalid2_muxout & rxvalid1_muxout & rxvalid0_muxout); + iei_detect_1 : cycloneiv_pciehip_iei_detect + PORT MAP ( + rxelecidle => temp, + pclk => pclk, + uclk => core_clk, + prstn => prstn, + urstn => urstn, + rate => rate_xhdl45, + enable_inf_ei => k_iei_enable, + rxupdatefc => dl_rx_val_fc, + test_in_0 => test_in_hip(0), + eidleinfersel => eidle_infer_sel, + datain_ch0 => xhdl150, + datain_ch1 => xhdl151, + datain_ch2 => xhdl152, + datain_ch3 => xhdl153, + datain_ch4 => xhdl154, + datain_ch5 => xhdl155, + datain_ch6 => xhdl156, + datain_ch7 => xhdl157, + rxelecidle_in => xhdl158, + rxvalid => xhdl159 + ); + + -- TOP_HIP module + -- #( + -- .G_RX_BUF (11), // 16KB per VC + -- .G_RH_NUM (8), + -- .G_RTRY_BUF (11), // 16KB Retry Buffer + -- .G_RTRY_NUM (6), + -- .G_TAG_NUM (64) + -- ) + + + pciexp_top_hip_1 : cycloneiv_pciehip_pciexp_top_hip + PORT MAP ( + k_conf => k_conf_func0, + k_ptr0 => k_ptr0, + k_ptr1 => k_ptr1, + k_vc0 => k_vc0, + k_vc1 => k_vc1, + k_vc2 => k_vc2, + k_vc3 => k_vc3, + k_vc4 => k_vc4, + k_vc5 => k_vc5, + k_vc6 => k_vc6, + k_vc7 => k_vc7, + k_port => k_port, + k_gbl_hip => k_gbl, + k_cnt => k_cnt, + k_rtry => k_rtry, + k_dev => k_dev, + k_bar => k_bar_func0, + k_hip => k_hip, + + -- Global clock and reset signals + pld_clk => pld_clk, + pld_srst => pld_srst_int, + pld_rstn => pld_rstn_int, + phy_clk => pclk, + phy_rstn => phy_rstn_int, + phy_srst => phy_srst_int, + core_clk => core_clk, + core_rstn => core_rstn_int, + core_npor => core_npor_int, + core_crst => core_crst_int, + core_srst => core_srst_int, + urstn => urstn, + prstn => prstn, + usrst => usrst, + reset_status => reset_status_xhdl46, + l2_exit => l2_exit_xhdl29, + hotrst_exit => hotrst_exit_xhdl27, + dlup_exit => dlup_exit_xhdl23, + core_clk_vc0 => clk_vc0, + core_clk_vc1 => clk_vc1, + + -- PIPE interface signals + rate => rate_xhdl45, + eidle_infer_sel => eidle_infer_sel, + lane_reversal_enable => lane_reversal_enable, + -- interface with the PHY PCS Lane 0 + tx_deemph => tx_deemph, + tx_margin => tx_margin, + txdata0 => txdata0_xhdl117, + txdatak0 => txdatak0_xhdl125, + txdetectrx0 => txdetectrx0_xhdl133, + txelecidle0 => txelecidle0_xhdl141, + txcompl0 => txcompl0_xhdl109, + rxpolarity0 => rxpolarity0_xhdl77, + powerdown0 => powerdown0_xhdl37, + rxdata0 => rxdata0_muxout, + rxdatak0 => rxdatak0_muxout, + rxvalid0 => rxvalid0_muxout, + phystatus0 => phystatus0_muxout, + rxelecidle0 => rxelecidle0_infer, + rxstatus0 => rxstatus0_muxout, + -- interface with the PHY PCS Lane 1 + txdata1 => txdata1_xhdl118, + txdatak1 => txdatak1_xhdl126, + txdetectrx1 => txdetectrx1_xhdl134, + txelecidle1 => txelecidle1_xhdl142, + txcompl1 => txcompl1_xhdl110, + rxpolarity1 => rxpolarity1_xhdl78, + powerdown1 => powerdown1_xhdl38, + rxdata1 => rxdata1_muxout, + rxdatak1 => rxdatak1_muxout, + rxvalid1 => rxvalid1_muxout, + phystatus1 => phystatus1_muxout, + rxelecidle1 => rxelecidle1_infer, + rxstatus1 => rxstatus1_muxout, + -- interface with the PHY PCS Lane 2 + txdata2 => txdata2_xhdl119, + txdatak2 => txdatak2_xhdl127, + txdetectrx2 => txdetectrx2_xhdl135, + txelecidle2 => txelecidle2_xhdl143, + txcompl2 => txcompl2_xhdl111, + rxpolarity2 => rxpolarity2_xhdl79, + powerdown2 => powerdown2_xhdl39, + rxdata2 => rxdata2_muxout, + rxdatak2 => rxdatak2_muxout, + rxvalid2 => rxvalid2_muxout, + phystatus2 => phystatus2_muxout, + rxelecidle2 => rxelecidle2_infer, + rxstatus2 => rxstatus2_muxout, + -- interface with the PHY PCS Lane 3 + txdata3 => txdata3_xhdl120, + txdatak3 => txdatak3_xhdl128, + txdetectrx3 => txdetectrx3_xhdl136, + txelecidle3 => txelecidle3_xhdl144, + txcompl3 => txcompl3_xhdl112, + rxpolarity3 => rxpolarity3_xhdl80, + powerdown3 => powerdown3_xhdl40, + rxdata3 => rxdata3_muxout, + rxdatak3 => rxdatak3_muxout, + rxvalid3 => rxvalid3_muxout, + phystatus3 => phystatus3_muxout, + rxelecidle3 => rxelecidle3_infer, + rxstatus3 => rxstatus3_muxout, + -- interface with the PHY PCS Lane 4 + txdata4 => txdata4_xhdl121, + txdatak4 => txdatak4_xhdl129, + txdetectrx4 => txdetectrx4_xhdl137, + txelecidle4 => txelecidle4_xhdl145, + txcompl4 => txcompl4_xhdl113, + rxpolarity4 => rxpolarity4_xhdl81, + powerdown4 => powerdown4_xhdl41, + rxdata4 => rxdata4_muxout, + rxdatak4 => rxdatak4_muxout, + rxvalid4 => rxvalid4_muxout, + phystatus4 => phystatus4_muxout, + rxelecidle4 => rxelecidle4_infer, + rxstatus4 => rxstatus4_muxout, + -- interface with the PHY PCS Lane 5 + txdata5 => txdata5_xhdl122, + txdatak5 => txdatak5_xhdl130, + txdetectrx5 => txdetectrx5_xhdl138, + txelecidle5 => txelecidle5_xhdl146, + txcompl5 => txcompl5_xhdl114, + rxpolarity5 => rxpolarity5_xhdl82, + powerdown5 => powerdown5_xhdl42, + rxdata5 => rxdata5_muxout, + rxdatak5 => rxdatak5_muxout, + rxvalid5 => rxvalid5_muxout, + phystatus5 => phystatus5_muxout, + rxelecidle5 => rxelecidle5_infer, + rxstatus5 => rxstatus5_muxout, + -- interface with the PHY PCS Lane 6 + txdata6 => txdata6_xhdl123, + txdatak6 => txdatak6_xhdl131, + txdetectrx6 => txdetectrx6_xhdl139, + txelecidle6 => txelecidle6_xhdl147, + txcompl6 => txcompl6_xhdl115, + rxpolarity6 => rxpolarity6_xhdl83, + powerdown6 => powerdown6_xhdl43, + rxdata6 => rxdata6_muxout, + rxdatak6 => rxdatak6_muxout, + rxvalid6 => rxvalid6_muxout, + phystatus6 => phystatus6_muxout, + rxelecidle6 => rxelecidle6_infer, + rxstatus6 => rxstatus6_muxout, + -- interface with the PHY PCS Lane 7 + txdata7 => txdata7_xhdl124, + txdatak7 => txdatak7_xhdl132, + txdetectrx7 => txdetectrx7_xhdl140, + txelecidle7 => txelecidle7_xhdl148, + txcompl7 => txcompl7_xhdl116, + rxpolarity7 => rxpolarity7_xhdl84, + powerdown7 => powerdown7_xhdl44, + rxdata7 => rxdata7_muxout, + rxdatak7 => rxdatak7_muxout, + rxvalid7 => rxvalid7_muxout, + phystatus7 => phystatus7_muxout, + rxelecidle7 => rxelecidle7_infer, + rxstatus7 => rxstatus7_muxout, + + -- LMI config access interface + lmi_rden => lmi_rden, + lmi_wren => lmi_wren, + lmi_addr => lmi_addr, + lmi_din => lmi_din, + lmi_dout => lmi_dout_xhdl33, + lmi_ack => lmi_ack_xhdl32, + + -- Configuration status + tl_cfg_sts => tl_cfg_sts_xhdl94, + tl_cfg_sts_wr => tl_cfg_sts_wr_xhdl95, + tl_cfg_ctl => tl_cfg_ctl_xhdl92, + tl_cfg_ctl_wr => tl_cfg_ctl_wr_xhdl93, + tl_cfg_add => tl_cfg_add_xhdl91, + + -- parameters + tl_slotclk_cfg => tl_slotclk_cfg, + mode => mode, + test_in_hip => test_in_hip(31 DOWNTO 0), + test_out_hip => test_out_hip_xhdl88, + ev_1us => ev_1us_xhdl26, + ev_128ns => ev_128ns_xhdl25, + wake_oen => wake_oen_xhdl149, + cpl_pending => cpl_pending, + cpl_err => cpl_err, + serr_out => serr_out_xhdl85, + + -- sw mode + swdn_in => swdn_in, + swdn_wake => swdn_wake_xhdl86, + swup_in => swup_in, + swup_hotrst => swup_hotrst_xhdl87, + + --power mgt + tl_pme_to_cr => tl_pme_to_cr, + tl_pme_to_sr => tl_pme_to_sr_xhdl96, + tl_pm_event => tl_pm_event, + tl_pm_data => tl_pm_data, + tl_pm_auxpwr => tl_pm_auxpwr, + + --interrupts + int_status => int_status_xhdl28, + tl_app_inta_sts => tl_app_inta_sts, + tl_app_inta_ack => tl_app_inta_ack_xhdl89, + tl_app_msi_req => tl_app_msi_req, + tl_app_msi_tc => tl_app_msi_tc, + tl_app_msi_ack => tl_app_msi_ack_xhdl90, + tl_app_msi_num => tl_app_msi_num, + tl_aer_msi_num => tl_aer_msi_num, + tl_pex_msi_num => tl_pex_msi_num, + tl_hpg_ctrler => tl_hpg_ctrler, + + --TL bypass + dl_rx_ecrcchk => dl_rx_ecrcchk, + dl_aspm_cr0 => dl_aspm_cr0, + dl_comclk_reg => dl_comclk_reg, + dl_up => dl_up_xhdl21, + dl_vc_ctrl => dl_vc_ctrl, + dl_vc_status => dl_vc_status_xhdl22, + dl_vcid_map => dl_vcid_map, + dl_err_dll => dl_err_dll_xhdl10, + dl_err_phy => dl_err_phy_xhdl11, + dl_rpbuf_emp => dl_rpbuf_emp_xhdl15, + dl_dll_req => dl_dll_req_xhdl9, + dl_inh_dllp => dl_inh_dllp, + lane_act => lane_act_xhdl30, + link_up => link_up_xhdl31, + dl_ltssm => dl_ltssm_xhdl14, + clr_rxpath => clr_rxpath_xhdl0, + dl_rx_val_fc => dl_rx_val_fc, + dl_req_wake => dl_req_wake, + dl_txcfg_extsy => dl_txcfg_extsy, + dl_rx_val_pm => dl_rx_val_pm_xhdl19, + dl_rx_typ_pm => dl_rx_typ_pm_xhdl18, + dl_tx_req_pm => dl_tx_req_pm, + dl_tx_ack_pm => dl_tx_ack_pm_xhdl20, + dl_tx_typ_pm => dl_tx_typ_pm, + dl_maxpload_dcr => dl_maxpload_dcr, + dl_req_phypm => dl_req_phypm, + dl_ack_phypm => dl_ack_phypm_xhdl4, + dl_req_phycfg => dl_req_phycfg, + dl_req_upfc => dl_req_upfc, + dl_snd_upfc => dl_snd_upfc, + dl_ack_req_upfc => dl_ack_req_upfc_xhdl5, + dl_ack_snd_upfc => dl_ack_snd_upfc_xhdl6, + dl_typ_upfc => dl_typ_upfc, + dl_vcid_upfc => dl_vcid_upfc, + dl_hdr_upfc => dl_hdr_upfc, + dl_data_upfc => dl_data_upfc, + -- gen2 signals + dl_rst_enter_comp_bit => dl_rst_enter_comp_bit_xhdl16, + dl_rst_tx_margin_field => dl_rst_tx_margin_field_xhdl17, + dl_current_speed => dl_current_speed_xhdl8, + dl_current_deemp => dl_current_deemp_xhdl7, + dl_ctrl_link2 => dl_ctrl_link2, + dl_link_auto_bdw_status => dl_link_auto_bdw_status_xhdl12, + dl_link_bdw_mng_status => dl_link_bdw_mng_status_xhdl13, + + --data path + --VC0 + rx_mask_vc0 => rx_mask_vc0, + rx_valid_vc0 => rx_valid_vc0_xhdl75, + rx_ready_vc0 => rx_ready_vc0, + rx_err_vc0 => rx_err_vc0_xhdl61, + rx_bar_dec_vc0 => rx_bar_dec_vc0_xhdl47, + rx_sop_vc0_0 => rx_sop_vc0_0_xhdl71, + rx_eop_vc0_0 => rx_eop_vc0_0_xhdl57, + rx_data_vc0_0 => rx_data_vc0_0_xhdl53, + rx_be_vc0_0 => rx_be_vc0_0_xhdl49, + rx_sop_vc0_1 => rx_sop_vc0_1_xhdl72, + rx_eop_vc0_1 => rx_eop_vc0_1_xhdl58, + rx_data_vc0_1 => rx_data_vc0_1_xhdl54, + rx_be_vc0_1 => rx_be_vc0_1_xhdl50, + rx_fifo_full_vc0 => rx_fifo_full_vc0_xhdl65, + rx_fifo_empty_vc0 => rx_fifo_empty_vc0_xhdl63, + rx_fifo_wrp0 => rx_fifo_wrp_vc0_xhdl69, + rx_fifo_rdp0 => rx_fifo_rdp_vc0_xhdl67, + tx_cred_vc0 => tx_cred_vc0_xhdl97, + tx_valid_vc0 => tx_valid_vc0, + tx_ready_vc0 => tx_ready_vc0_xhdl107, + tx_err_vc0 => tx_err_vc0, + tx_sop_vc0_0 => tx_sop_vc0_0, + tx_eop_vc0_0 => tx_eop_vc0_0, + tx_data_vc0_0 => tx_data_vc0_0, + tx_sop_vc0_1 => tx_sop_vc0_1, + tx_eop_vc0_1 => tx_eop_vc0_1, + tx_data_vc0_1 => tx_data_vc0_1, + --for FIFO monitoring + tx_fifo_full_vc0 => tx_fifo_full_vc0_xhdl101, + tx_fifo_empty_vc0 => tx_fifo_empty_vc0_xhdl99, + tx_fifo_wrp_vc0 => tx_fifo_wrp_vc0_xhdl105, + tx_fifo_rdp_vc0 => tx_fifo_rdp_vc0_xhdl103, + + --data path + --VC1 + rx_mask_vc1 => rx_mask_vc1, + rx_valid_vc1 => rx_valid_vc1_xhdl76, + rx_ready_vc1 => rx_ready_vc1, + rx_err_vc1 => rx_err_vc1_xhdl62, + rx_bar_dec_vc1 => rx_bar_dec_vc1_xhdl48, + rx_sop_vc1_0 => rx_sop_vc1_0_xhdl73, + rx_eop_vc1_0 => rx_eop_vc1_0_xhdl59, + rx_data_vc1_0 => rx_data_vc1_0_xhdl55, + rx_be_vc1_0 => rx_be_vc1_0_xhdl51, + rx_sop_vc1_1 => rx_sop_vc1_1_xhdl74, + rx_eop_vc1_1 => rx_eop_vc1_1_xhdl60, + rx_data_vc1_1 => rx_data_vc1_1_xhdl56, + rx_be_vc1_1 => rx_be_vc1_1_xhdl52, + rx_fifo_full_vc1 => rx_fifo_full_vc1_xhdl66, + rx_fifo_empty_vc1 => rx_fifo_empty_vc1_xhdl64, + rx_fifo_wrp1 => rx_fifo_wrp_vc1_xhdl70, + rx_fifo_rdp1 => rx_fifo_rdp_vc1_xhdl68, + tx_cred_vc1 => tx_cred_vc1_xhdl98, + tx_valid_vc1 => tx_valid_vc1, + tx_ready_vc1 => tx_ready_vc1_xhdl108, + tx_err_vc1 => tx_err_vc1, + tx_sop_vc1_0 => tx_sop_vc1_0, + tx_eop_vc1_0 => tx_eop_vc1_0, + tx_data_vc1_0 => tx_data_vc1_0, + tx_sop_vc1_1 => tx_sop_vc1_1, + tx_eop_vc1_1 => tx_eop_vc1_1, + tx_data_vc1_1 => tx_data_vc1_1, + --for FIFO monitoring + tx_fifo_full_vc1 => tx_fifo_full_vc1_xhdl102, + tx_fifo_empty_vc1 => tx_fifo_empty_vc1_xhdl100, + tx_fifo_wrp_vc1 => tx_fifo_wrp_vc1_xhdl106, + tx_fifo_rdp_vc1 => tx_fifo_rdp_vc1_xhdl104, + + --MRAM interface + --RX buffer0 + wren_rcv0 => wren_rcv0, + adwr_rcv0 => adwr_rcv0, + din_rcv0 => din_rcv0, + adrd_rcv0 => adrd_rcv0, + dout_rcv0 => dout_rcv0, + derr_rcv0 => derr_rcv0, + --RX buffer1 + wren_rcv1 => wren_rcv1, + adwr_rcv1 => adwr_rcv1, + din_rcv1 => din_rcv1, + adrd_rcv1 => adrd_rcv1, + dout_rcv1 => dout_rcv1, + derr_rcv1 => derr_rcv1, + -- Replay buffer + wren_rpl => wren_rpl, + adwr_rpl => adwr_rpl, + din_rpl => din_rpl, + adrd_rpl => adrd_rpl, + dout_rpl => dout_rpl, + -- Misc + scan_mode => scan_mode, + -- LTSSM signal: successful_speed_negotiation_int to user logic to reset Word Align in PCS + successful_speed_negotiation_int => successful_speed_negotiation_int + ); + + --shawn for VHDL + dout_rpl <= (temp1(70 DOWNTO 63) & temp1(61 DOWNTO 54) & temp1(52 DOWNTO 45) & temp1(43 DOWNTO 36) & temp1(34 DOWNTO 27) & temp1(25 DOWNTO 18) & temp1(16 DOWNTO 9) & temp1(7 DOWNTO 0)); + dout_rpl_nc <= (temp1(71) & temp1(62) & temp1(53) & temp1(44) & temp1(35) & temp1(26) & temp1(17) & temp1(8)); + + -- Retry buffer + + + -- .dprio_mram_in({k_clk_x8_sel_rtry,k_rtry_rben1,k_rtry_raen2,k_rtry_outreg,k_rtry_mem}), + xhdl160 <= (k_clk_x8_sel_rtry & k_ecc_enable_rtry & k_rtry_mem); + -- cycloneiv + --xhdl161 <= ("111" & adwr_rpl); + --xhdl162 <= ("111" & adrd_rpl); + xhdl161 <= ("11111" & adwr_rpl); + xhdl162 <= ("11111" & adrd_rpl); + -- .data({8'h00,din_rpl}), + xhdl163 <= ('0' & din_rpl(63 DOWNTO 56) & '0' & din_rpl(55 DOWNTO 48) & '0' & din_rpl(47 DOWNTO 40) & '0' & din_rpl(39 DOWNTO 32) & '0' & din_rpl(31 DOWNTO 24) & '0' & din_rpl(23 DOWNTO 16) & '0' & din_rpl(15 DOWNTO 8) & '0' & din_rpl(7 DOWNTO 0)); + rtry_buffer : cycloneiv_pciehip_mram_top + GENERIC MAP ( + ADDR_WIDTH => 13, + DATA_WIDTH => 72 + ) + PORT MAP ( + core_clk => core_clk, + dprio_mram_in => xhdl160, + addrA => xhdl161, + addrB => xhdl162, + data => xhdl163, + wren => wren_rpl, + dout => temp1, + -- .dout({dout_rpl_nc[7],dout_rpl[63:56],dout_rpl_nc[6],dout_rpl[55:48],dout_rpl_nc[5],dout_rpl[47:40],dout_rpl_nc[4],dout_rpl[39:32],dout_rpl_nc[3],dout_rpl[31:24],dout_rpl_nc[2],dout_rpl[23:16],dout_rpl_nc[1],dout_rpl[15:8],dout_rpl_nc[0],dout_rpl[7:0]}), + bisten => bisten_rpl, + rstn => urstn, + srst => usrst, + dprio_bist_in => k_mem_bist, + -- Redundancy Scan I/Os + rsclk => mram_red_sclk, + enscan => mram_red_enscan, + rscen => mram_red_scen, + rscsel => mram_red_scsel, + rscrst => mram_red_scrst, + prv_mram => mram_red_scin, + rscin => mram_red_scin, + rscout => red_scout_rpl, + id => id_rpl, + -- RegScan I/Os + scanen => mram_regscanen, + scanin => mram_regscanin, + scanout => regscanout_rpl, + mram_hip_test_enable => mram_hip_test_enable, + bist_scanen => bist_scanen, + bist_scanin => bist_scanin, + testen => bist_testen, + bist_scanout => bist_scanout_rpl_int, + bistdoneA => bist_donea_rpl_int, + bistdoneB => bist_doneb_rpl_int, + pass => bist_pass_rpl_int, + uncor_err_ext_en => '1', + -- enable pulse extender inside the MRAM + derr => derr_rpl_xhdl3, + derr_cor_ext => derr_cor_ext_rpl_int, + nfrzdrv => nfrzdrv, + frzreg => frzreg, + frzlogic => frzlogic, + scan_mode => scan_mode + ); + + dout_rcv0 <= (temp2(70 DOWNTO 63) & temp2(61 DOWNTO 54) & temp2(52 DOWNTO 45) & temp2(43 DOWNTO 36) & temp2(34 DOWNTO 27) & temp2(25 DOWNTO 18) & temp2(16 DOWNTO 9) & temp2(7 DOWNTO 0)); + dout_rcv0_nc <= (temp2(71) & temp2(62) & temp2(53) & temp2(44) & temp2(35) & temp2(26) & temp2(17) & temp2(8)); + + -- Receive buffer for VC0 + + + -- .dprio_mram_in({k_clk_x8_sel_rcv0,k_rcv0_rben1,k_rcv0_raen2,k_rcv0_outreg,k_rcv0_mem}), // 6 bits will drive rxcorea[3,4,22] and rxcoreb[3,4,22] for testing + xhdl164 <= (k_clk_x8_sel_rcv0 & k_ecc_enable_rcv0 & k_rcv0_mem); -- 6 bits will drive rxcorea[3,4,22] and rxcoreb[3,4,22] for testing + -- cycloneiv + --xhdl165 <= ("111" & adwr_rcv0); + --xhdl166 <= ("111" & adrd_rcv0); + xhdl165 <= ("1111" & adwr_rcv0); + xhdl166 <= ("1111" & adrd_rcv0); + -- .data({8'h00,din_rcv0}), + xhdl167 <= ('0' & din_rcv0(63 DOWNTO 56) & '0' & din_rcv0(55 DOWNTO 48) & '0' & din_rcv0(47 DOWNTO 40) & '0' & din_rcv0(39 DOWNTO 32) & '0' & din_rcv0(31 DOWNTO 24) & '0' & din_rcv0(23 DOWNTO 16) & '0' & din_rcv0(15 DOWNTO 8) & '0' & din_rcv0(7 DOWNTO 0)); + rcv0_buffer : cycloneiv_pciehip_mram_top + GENERIC MAP ( + ADDR_WIDTH => 13, + DATA_WIDTH => 72 + ) + PORT MAP ( + core_clk => clk_vc0, + dprio_mram_in => xhdl164, + addrA => xhdl165, + addrB => xhdl166, + data => xhdl167, + wren => wren_rcv0, + -- .dout({dout_rcv0_nc,dout_rcv0}), + -- .dout({dout_rcv0_nc[7],dout_rcv0[63:56],dout_rcv0_nc[6],dout_rcv0[55:48],dout_rcv0_nc[5],dout_rcv0[47:40],dout_rcv0_nc[4],dout_rcv0[39:32],dout_rcv0_nc[3],dout_rcv0[31:24],dout_rcv0_nc[2],dout_rcv0[23:16],dout_rcv0_nc[1],dout_rcv0[15:8],dout_rcv0_nc[0],dout_rcv0[7:0]}), + dout => temp2, + bisten => bisten_rcv0, + rstn => urstn, + srst => usrst, + dprio_bist_in => k_mem_bist, + -- Redundancy Scan I/Os + rsclk => mram_red_sclk, + enscan => mram_red_enscan, + rscen => mram_red_scen, + rscsel => mram_red_scsel, + rscrst => mram_red_scrst, + prv_mram => red_scout_rpl, + rscin => mram_red_scin, + -- .rscin(red_scout_rpl), + rscout => red_scout_rcv0, + id => id_rcv0, + -- RegScan I/Os + scanen => mram_regscanen, + scanin => regscanout_rpl, + -- cycloneiv + -- scanout => regscanout_rcv0, + scanout => mram_regscanout, + mram_hip_test_enable => mram_hip_test_enable, + bist_scanen => bist_scanen, + bist_scanin => bist_scanin, + testen => bist_testen, + bist_scanout => bist_scanout_rcv0_int, + bistdoneA => bist_donea_rcv0_int, + bistdoneB => bist_doneb_rcv0_int, + pass => bist_pass_rcv0_int, + uncor_err_ext_en => '0', + -- disable the pulse extender inside the MRAM + derr => derr_rcv0, + derr_cor_ext => derr_cor_ext_rcv0_int, + nfrzdrv => nfrzdrv, + frzreg => frzreg, + frzlogic => frzlogic, + scan_mode => scan_mode + ); + + --shawn for VHDL + dout_rcv1 <= (temp3(70 DOWNTO 63) & temp3(61 DOWNTO 54) & temp3(52 DOWNTO 45) & temp3(43 DOWNTO 36) & temp3(34 DOWNTO 27) & temp3(25 DOWNTO 18) & temp3(16 DOWNTO 9) & temp3(7 DOWNTO 0)); + dout_rcv1_nc <= (temp3(71) & temp3(62) & temp3(53) & temp3(44) & temp3(35) & temp3(26) & temp3(17) & temp3(8)); + + -- Receive buffer for VC1 not existed in cycloneiv + + + -- Clock muxing module + + + u_clkmux : cycloneiv_pciehip_clkmux + PORT MAP ( + resetn => core_npor, + scan_mode => scan_mode, + pclk_ch0 => pclk_ch0, + pclk_central => pclk_central, + pll_fixed_clk => pll_fixed_clk, + core_clk_in => core_clk_in, + r_pclk_sel => k_pclk_sel, + r_core_clk_source_sel => k_core_clk_source_sel, + r_core_clk_div_sel => k_core_clk_div_sel, + r_core_clk_out_sel => k_core_clk_out_sel, + r_core_clk_dbg_sel => k_core_clk_dbg_sel, + pclk_out => pclk, + core_clk => core_clk, + core_clk_out => core_clk_out_xhdl1 + ); + +END trans; + + +-- *********************************************************** +-- This WYSIWYG atom header was automatically generated by the +-- Atmgen build tool. To change it, alter data stored in the +-- corresponding WYS file(s) in the tools/atmgen subdirectory. +-- *********************************************************** + +-- *** Section 1 -- Header *** + +-- ----------------------------------------------------------- +-- +-- Module Name : cycloneiv_hssi_pcie_hip +-- +-- Description : DEV_FAMILY_CYCLONEIV cycloneiv_hssi_pcie_hip Verilog simulation model +-- +-- ----------------------------------------------------------- + +-- *** End of Section 1 *** + +-- *** Section 3 -- Module declaration *** + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +LIBRARY STD; +USE STD.textio.ALL; +USE work.cycloneiv_pcie_hip_components.all; + +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +ENTITY cycloneiv_hssi_pcie_hip IS + GENERIC ( + + -- generic control parameters -- + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + -- tipd :interconnect path delays -- + tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01; + tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01; + tipd_bistenrpl : VitalDelayType01 := DefpropDelay01; + tipd_bistscanen : VitalDelayType01 := DefpropDelay01; + tipd_bistscanin : VitalDelayType01 := DefpropDelay01; + tipd_bisttesten : VitalDelayType01 := DefpropDelay01; + tipd_coreclkin : VitalDelayType01 := DefpropDelay01; + tipd_corecrst : VitalDelayType01 := DefpropDelay01; + tipd_corepor : VitalDelayType01 := DefpropDelay01; + tipd_corerst : VitalDelayType01 := DefpropDelay01; + tipd_coresrst : VitalDelayType01 := DefpropDelay01; + tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_cplpending : VitalDelayType01 := DefpropDelay01; + tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01; + tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01; + tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01; + tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01; + tipd_dlreqwake : VitalDelayType01 := DefpropDelay01; + tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01; + tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01; + tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01; + tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01; + tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dpclk : VitalDelayType01 := DefpropDelay01; + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_dprioin : VitalDelayType01 := DefpropDelay01; + tipd_dprioload : VitalDelayType01 := DefpropDelay01; + tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_lmirden : VitalDelayType01 := DefpropDelay01; + tipd_lmiwren : VitalDelayType01 := DefpropDelay01; + tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01; + tipd_mramregscanen : VitalDelayType01 := DefpropDelay01; + tipd_mramregscanin : VitalDelayType01 := DefpropDelay01; + tipd_pclkcentral : VitalDelayType01 := DefpropDelay01; + tipd_pclkch0 : VitalDelayType01 := DefpropDelay01; + tipd_phyrst : VitalDelayType01 := DefpropDelay01; + tipd_physrst : VitalDelayType01 := DefpropDelay01; + tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pldclk : VitalDelayType01 := DefpropDelay01; + tipd_pldrst : VitalDelayType01 := DefpropDelay01; + tipd_pldsrst : VitalDelayType01 := DefpropDelay01; + tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01; + tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01; + tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01; + tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01; + tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01; + tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_scanen : VitalDelayType01 := DefpropDelay01; + tipd_scanmoden : VitalDelayType01 := DefpropDelay01; + tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlappintasts : VitalDelayType01 := DefpropDelay01; + tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01; + tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01; + tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01; + tipd_tlpmevent : VitalDelayType01 := DefpropDelay01; + tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01; + tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01; + tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01; + tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01; + tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01; + tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01; + tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01; + tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01; + tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01; + + -- tpd: Edge-Sensitive Paths -- + -- TCO of pldclk + tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01; + + -- TCO of dpclk + tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01; + tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01; + + -- tpd: parallel and Full Connection Paths -- + -- tsetup and thold values : setup and hold times -- + -- TSU of pldclk + tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + + -- THOLD of pldclk + thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + + -- TSU of dpclk + tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + + -- THOLD of dpclk + thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + + -- Pulse Width parameters -- + + -- *** End of Section 3 *** + + -- *** Section 4 -- Port size declarations *** + + -- Note: Variable port sizes dictated by parameters are not currently defined in + -- the WYS file data. Busses are marked with the VARIABLE notation as a reminder. + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- * VARIABLE + + -- *** End of Section 4 *** + + -- *** Section 5 -- Port declarations *** + + lpm_type : STRING := "cycloneiv_hssi_pcie_hip"; + advanced_errors : STRING := "false"; + allow_rx_valid_empty : STRING := "false"; -- july3,2008 + bar0_64bit_mem_space : STRING := "true"; + bar0_io_space : STRING := "false"; + bar0_prefetchable : STRING := "true"; + bar0_size_mask : INTEGER := 32; + bar1_64bit_mem_space : STRING := "false"; + bar1_io_space : STRING := "false"; + bar1_prefetchable : STRING := "false"; + bar1_size_mask : INTEGER := 4; + bar2_64bit_mem_space : STRING := "false"; + bar2_io_space : STRING := "false"; + bar2_prefetchable : STRING := "false"; + bar2_size_mask : INTEGER := 4; + bar3_64bit_mem_space : STRING := "false"; + bar3_io_space : STRING := "false"; + bar3_prefetchable : STRING := "false"; + bar3_size_mask : INTEGER := 4; + bar4_64bit_mem_space : STRING := "false"; + bar4_io_space : STRING := "false"; + bar4_prefetchable : STRING := "false"; + bar4_size_mask : INTEGER := 4; + bar5_64bit_mem_space : STRING := "false"; + bar5_io_space : STRING := "false"; + bar5_prefetchable : STRING := "false"; + bar5_size_mask : INTEGER := 4; + bar_io_window_size : STRING := "NONE"; + bar_prefetchable : INTEGER := 0; + base_address : INTEGER := 0; + bridge_port_ssid_support : STRING := "false"; + bridge_port_vga_enable : STRING := "false"; + bypass_cdc : STRING := "false"; + bypass_tl : STRING := "false"; + class_code : INTEGER := 16711680; + completion_timeout : STRING := "ABCD"; + core_clk_divider : INTEGER := 1; + core_clk_source : STRING := "PLL_FIXED_CLK"; + credit_buffer_allocation_aux : STRING := "BALANCED"; + deemphasis_enable : STRING := "false"; + device_address : INTEGER := 0; + device_id : INTEGER := 1; + device_number : INTEGER := 0; + diffclock_nfts_count : INTEGER := 128; + disable_async_l2_logic : STRING := "false"; -- july2,2008 + disable_cdc_clk_ppm : STRING := "true"; + disable_device_number_mismatch : STRING := "false"; + disable_link_x2_support : STRING := "false"; + disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + dll_active_report_support : STRING := "false"; + ei_delay_powerdown_count : INTEGER := 10; + eie_before_nfts_count : INTEGER := 4; + enable_adapter_half_rate_mode : STRING := "false"; + enable_ch0_pclk_out : STRING := "false"; + enable_completion_timeout_disable : STRING := "true"; + enable_coreclk_out_half_rate : STRING := "false"; + enable_d1pm_support : STRING := "false"; + enable_d2pm_support : STRING := "false"; + enable_ecrc_check : STRING := "false"; + enable_ecrc_gen : STRING := "false"; + enable_function_msi_support : STRING := "true"; + enable_function_msix_support : STRING := "false"; + enable_gen2_core : STRING := "true"; + enable_hip_x1_loopback : STRING := "false"; + enable_l1_aspm : STRING := "false"; + enable_msi_64bit_addressing : STRING := "true"; + enable_msi_masking : STRING := "false"; + enable_rcv0buf_a_we : STRING := "true"; + enable_rcv0buf_b_re : STRING := "true"; + enable_rcv0buf_output_regs : STRING := "false"; + enable_rcv1buf_a_we : STRING := "true"; + enable_rcv1buf_b_re : STRING := "true"; + enable_rcv1buf_output_regs : STRING := "false"; + enable_retrybuf_a_we : STRING := "true"; + enable_retrybuf_b_re : STRING := "true"; + enable_retrybuf_ecc : STRING := "false"; -- ww12 + enable_retrybuf_output_regs : STRING := "false"; + enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx0buf_ecc : STRING := "false"; -- ww12 + enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx1buf_ecc : STRING := "false"; -- ww12 + enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx_buffer_checking : STRING := "false"; + enable_rx_ei_l0s_exit_refined : STRING := "false"; + enable_rx_reordering : STRING := "true"; + enable_slot_register : STRING := "false"; + endpoint_l0_latency : INTEGER := 0; + endpoint_l1_latency : INTEGER := 0; + expansion_base_address_register : INTEGER := 0; + extend_tag_field : STRING := "false"; + fc_init_timer : INTEGER := 1024; + flow_control_timeout_count : INTEGER := 200; + flow_control_update_count : INTEGER := 30; + gen2_diffclock_nfts_count : INTEGER := 255; + gen2_lane_rate_mode : STRING := "false"; + gen2_sameclock_nfts_count : INTEGER := 255; + hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + iei_logic : STRING := "IEI_IIIS"; + indicator : INTEGER := 7; + l01_entry_latency : INTEGER := 31; + l0_exit_latency_diffclock : INTEGER := 6; + l0_exit_latency_sameclock : INTEGER := 6; + l1_exit_latency_diffclock : INTEGER := 0; + l1_exit_latency_sameclock : INTEGER := 0; + lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000"; + low_priority_vc : INTEGER := 0; + max_link_width : INTEGER := 4; + max_payload_size : INTEGER := 2; + maximum_current : INTEGER := 0; + migrated_from_prev_family : STRING := "false"; + millisecond_cycle_count : INTEGER := 0; + mram_bist_settings : STRING := ""; + msi_function_count : INTEGER := 2; + msix_pba_bir : INTEGER := 0; + msix_pba_offset : INTEGER := 0; + msix_table_bir : INTEGER := 0; + msix_table_offset : INTEGER := 0; + msix_table_size : INTEGER := 0; + no_command_completed : STRING := "true"; + no_soft_reset : STRING := "false"; + pcie_mode : STRING := "SHARED_MODE"; + pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; + port_link_number : INTEGER := 1; + port_address : INTEGER := 0; + register_pipe_signals : STRING := "false"; + retry_buffer_last_active_address : INTEGER := 2047; + retry_buffer_memory_settings : INTEGER := 0; + revision_id : INTEGER := 1; + rx0_adap_fifo_full_value : INTEGER := 9; + rx1_adap_fifo_full_value : INTEGER := 9; + rx_cdc_full_value : INTEGER := 12; + rx_idl_os_count : INTEGER := 0; + rx_ptr0_nonposted_dpram_max : INTEGER := 0; + rx_ptr0_nonposted_dpram_min : INTEGER := 0; + rx_ptr0_posted_dpram_max : INTEGER := 0; + rx_ptr0_posted_dpram_min : INTEGER := 0; + rx_ptr1_nonposted_dpram_max : INTEGER := 0; + rx_ptr1_nonposted_dpram_min : INTEGER := 0; + rx_ptr1_posted_dpram_max : INTEGER := 0; + rx_ptr1_posted_dpram_min : INTEGER := 0; + sameclock_nfts_count : INTEGER := 128; + single_rx_detect : INTEGER := 0; + skp_os_schedule_count : INTEGER := 0; + slot_number : INTEGER := 0; + slot_power_limit : INTEGER := 0; + slot_power_scale : INTEGER := 0; + ssid : INTEGER := 0; + ssvid : INTEGER := 0; + subsystem_device_id : INTEGER := 1; + subsystem_vendor_id : INTEGER := 4466; + surprise_down_error_support : STRING := "false"; + tx0_adap_fifo_full_value : INTEGER := 11; + tx1_adap_fifo_full_value : INTEGER := 11; + tx_cdc_full_value : INTEGER := 12; + tx_cdc_stop_dummy_full_value : INTEGER := 11; + use_crc_forwarding : STRING := "false"; + vc0_clk_enable : STRING := "true"; + vc0_rx_buffer_memory_settings : INTEGER := 0; + vc0_rx_flow_ctrl_compl_data : INTEGER := 448; + vc0_rx_flow_ctrl_compl_header : INTEGER := 112; + vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc0_rx_flow_ctrl_posted_data : INTEGER := 360; + vc0_rx_flow_ctrl_posted_header : INTEGER := 50; + vc1_clk_enable : STRING := "false"; + vc1_rx_buffer_memory_settings : INTEGER := 0; + vc1_rx_flow_ctrl_compl_data : INTEGER := 448; + vc1_rx_flow_ctrl_compl_header : INTEGER := 112; + vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc1_rx_flow_ctrl_posted_data : INTEGER := 360; + vc1_rx_flow_ctrl_posted_header : INTEGER := 50; + vc_arbitration : INTEGER := 1; + vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + vendor_id : INTEGER := 4466 + ); + PORT ( + bistenrcv0 : IN STD_LOGIC := '0'; + bistenrcv1 : IN STD_LOGIC := '0'; + bistenrpl : IN STD_LOGIC := '0'; + bistscanen : IN STD_LOGIC := '0'; + bistscanin : IN STD_LOGIC := '0'; + bisttesten : IN STD_LOGIC := '0'; + coreclkin : IN STD_LOGIC := '0'; + corecrst : IN STD_LOGIC := '0'; + corepor : IN STD_LOGIC := '0'; + corerst : IN STD_LOGIC := '0'; + coresrst : IN STD_LOGIC := '0'; + cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0'); + cplpending : IN STD_LOGIC := '0'; + dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0'); + dlaspmcr0 : IN STD_LOGIC := '0'; + dlcomclkreg : IN STD_LOGIC := '0'; + dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0'); + dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0'); + dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + dlinhdllp : IN STD_LOGIC := '1'; + dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0'); + dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0'); + dlrequpfc : IN STD_LOGIC := '0'; + dlreqwake : IN STD_LOGIC := '0'; + dlrxecrcchk : IN STD_LOGIC := '0'; + dlsndupfc : IN STD_LOGIC := '0'; + dltxcfgextsy : IN STD_LOGIC := '0'; + dltxreqpm : IN STD_LOGIC := '0'; + dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0'); + dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0'); + dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + dpclk : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC := '0'; + dprioload : IN STD_LOGIC := '0'; + extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0'); + lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0'); + lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0'); + lmirden : IN STD_LOGIC := '0'; + lmiwren : IN STD_LOGIC := '0'; + mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0'); + mramhiptestenable : IN STD_LOGIC := '0'; + mramregscanen : IN STD_LOGIC := '0'; + mramregscanin : IN STD_LOGIC := '0'; + pclkcentral : IN STD_LOGIC := '0'; + pclkch0 : IN STD_LOGIC := '0'; + phyrst : IN STD_LOGIC := '0'; + physrst : IN STD_LOGIC := '0'; + phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + pldclk : IN STD_LOGIC := '0'; + pldrst : IN STD_LOGIC := '0'; + pldsrst : IN STD_LOGIC := '0'; + pllfixedclk : IN STD_LOGIC := '0'; + rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + rxmaskvc0 : IN STD_LOGIC := '0'; + rxmaskvc1 : IN STD_LOGIC := '0'; + rxreadyvc0 : IN STD_LOGIC := '0'; + rxreadyvc1 : IN STD_LOGIC := '0'; + rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0'); + rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + scanen : IN STD_LOGIC := '0'; + scanmoden : IN STD_LOGIC := '0'; + swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0'); + testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0'); + tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlappintasts : IN STD_LOGIC := '0'; + tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlappmsireq : IN STD_LOGIC := '0'; + tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlpmauxpwr : IN STD_LOGIC := '0'; + tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0'); + tlpmetocr : IN STD_LOGIC := '0'; + tlpmevent : IN STD_LOGIC := '0'; + tlslotclkcfg : IN STD_LOGIC := '0'; + txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txeopvc00 : IN STD_LOGIC := '0'; + txeopvc01 : IN STD_LOGIC := '0'; + txeopvc10 : IN STD_LOGIC := '0'; + txeopvc11 : IN STD_LOGIC := '0'; + txerrvc0 : IN STD_LOGIC := '0'; + txerrvc1 : IN STD_LOGIC := '0'; + txsopvc00 : IN STD_LOGIC := '0'; + txsopvc01 : IN STD_LOGIC := '0'; + txsopvc10 : IN STD_LOGIC := '0'; + txsopvc11 : IN STD_LOGIC := '0'; + txvalidvc0 : IN STD_LOGIC := '0'; + txvalidvc1 : IN STD_LOGIC := '0'; + bistdonearcv0 : OUT STD_LOGIC; + bistdonearcv1 : OUT STD_LOGIC; + bistdonearpl : OUT STD_LOGIC; + bistdonebrcv0 : OUT STD_LOGIC; + bistdonebrcv1 : OUT STD_LOGIC; + bistdonebrpl : OUT STD_LOGIC; + bistpassrcv0 : OUT STD_LOGIC; + bistpassrcv1 : OUT STD_LOGIC; + bistpassrpl : OUT STD_LOGIC; + bistscanoutrcv0 : OUT STD_LOGIC; + bistscanoutrcv1 : OUT STD_LOGIC; + bistscanoutrpl : OUT STD_LOGIC; + clrrxpath : OUT STD_LOGIC; + coreclkout : OUT STD_LOGIC; + dataenablen : OUT STD_LOGIC; + derrcorextrcv0 : OUT STD_LOGIC; + derrcorextrcv1 : OUT STD_LOGIC; + derrcorextrpl : OUT STD_LOGIC; + derrrpl : OUT STD_LOGIC; + dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + dlackrequpfc : OUT STD_LOGIC; + dlacksndupfc : OUT STD_LOGIC; + dlcurrentdeemp : OUT STD_LOGIC; + dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + dldllreq : OUT STD_LOGIC; + dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + dlerrphy : OUT STD_LOGIC; + dllinkautobdwstatus : OUT STD_LOGIC; + dllinkbdwmngstatus : OUT STD_LOGIC; + dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + dlrpbufemp : OUT STD_LOGIC; + dlrstentercompbit : OUT STD_LOGIC; + dlrsttxmarginfield : OUT STD_LOGIC; + dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + dlrxvalpm : OUT STD_LOGIC; + dltxackpm : OUT STD_LOGIC; + dlup : OUT STD_LOGIC; + dlupexit : OUT STD_LOGIC; + dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + dprioout : OUT STD_LOGIC; + dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0); + ev128ns : OUT STD_LOGIC; + ev1us : OUT STD_LOGIC; + extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0); + gen2rate : OUT STD_LOGIC; + gen2rategnd : OUT STD_LOGIC; + hotrstexit : OUT STD_LOGIC; + intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + l2exit : OUT STD_LOGIC; + laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + linkup : OUT STD_LOGIC; + lmiack : OUT STD_LOGIC; + lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0); + ltssml0state : OUT STD_LOGIC; + mramregscanout : OUT STD_LOGIC; + powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0); + resetstatus : OUT STD_LOGIC; + rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxeopvc00 : OUT STD_LOGIC; + rxeopvc01 : OUT STD_LOGIC; + rxeopvc10 : OUT STD_LOGIC; + rxeopvc11 : OUT STD_LOGIC; + rxerrvc0 : OUT STD_LOGIC; + rxerrvc1 : OUT STD_LOGIC; + rxfifoemptyvc0 : OUT STD_LOGIC; + rxfifoemptyvc1 : OUT STD_LOGIC; + rxfifofullvc0 : OUT STD_LOGIC; + rxfifofullvc1 : OUT STD_LOGIC; + rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxsopvc00 : OUT STD_LOGIC; + rxsopvc01 : OUT STD_LOGIC; + rxsopvc10 : OUT STD_LOGIC; + rxsopvc11 : OUT STD_LOGIC; + rxvalidvc0 : OUT STD_LOGIC; + rxvalidvc1 : OUT STD_LOGIC; + r2cerr0ext : OUT STD_LOGIC; + serrout : OUT STD_LOGIC; + successspeednegoint : OUT STD_LOGIC; + swdnwake : OUT STD_LOGIC; + swuphotrst : OUT STD_LOGIC; + testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + tlappintaack : OUT STD_LOGIC; + tlappmsiack : OUT STD_LOGIC; + tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0); + tlcfgctlwr : OUT STD_LOGIC; + tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0); + tlcfgstswr : OUT STD_LOGIC; + tlpmetosr : OUT STD_LOGIC; + txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0); + txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0); + txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txfifoemptyvc0 : OUT STD_LOGIC; + txfifoemptyvc1 : OUT STD_LOGIC; + txfifofullvc0 : OUT STD_LOGIC; + txfifofullvc1 : OUT STD_LOGIC; + txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0); + txreadyvc0 : OUT STD_LOGIC; + txreadyvc1 : OUT STD_LOGIC; + wakeoen : OUT STD_LOGIC + ); +END cycloneiv_hssi_pcie_hip; + +ARCHITECTURE trans OF cycloneiv_hssi_pcie_hip IS + + COMPONENT cycloneiv_pciehip_param + GENERIC ( + advanced_errors : STRING := "false"; + allow_rx_valid_empty : STRING := "false"; + bar0_64bit_mem_space : STRING := "true"; + bar0_io_space : STRING := "false"; + bar0_prefetchable : STRING := "true"; + bar0_size_mask : INTEGER := 32; + bar1_64bit_mem_space : STRING := "false"; + bar1_io_space : STRING := "false"; + bar1_prefetchable : STRING := "false"; + bar1_size_mask : INTEGER := 4; + bar2_64bit_mem_space : STRING := "false"; + bar2_io_space : STRING := "false"; + bar2_prefetchable : STRING := "false"; + bar2_size_mask : INTEGER := 4; + bar3_64bit_mem_space : STRING := "false"; + bar3_io_space : STRING := "false"; + bar3_prefetchable : STRING := "false"; + bar3_size_mask : INTEGER := 4; + bar4_64bit_mem_space : STRING := "false"; + bar4_io_space : STRING := "false"; + bar4_prefetchable : STRING := "false"; + bar4_size_mask : INTEGER := 4; + bar5_64bit_mem_space : STRING := "false"; + bar5_io_space : STRING := "false"; + bar5_prefetchable : STRING := "false"; + bar5_size_mask : INTEGER := 4; + bar_io_window_size : STRING := "NONE"; + bar_prefetchable : INTEGER := 0; + base_address : INTEGER := 0; + bridge_port_ssid_support : STRING := "false"; + bridge_port_vga_enable : STRING := "false"; + bypass_cdc : STRING := "false"; + bypass_tl : STRING := "false"; + class_code : INTEGER := 16711680; + completion_timeout : STRING := "ABCD"; + core_clk_divider : INTEGER := 1; + core_clk_source : STRING := "PLL_FIXED_CLK"; + credit_buffer_allocation_aux : STRING := "BALANCED"; + deemphasis_enable : STRING := "false"; + device_address : INTEGER := 0; + device_id : INTEGER := 1; + device_number : INTEGER := 0; + diffclock_nfts_count : INTEGER := 128; + disable_async_l2_logic : STRING := "false"; + disable_cdc_clk_ppm : STRING := "true"; + disable_link_x2_support : STRING := "false"; + disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + dll_active_report_support : STRING := "false"; + ei_delay_powerdown_count : INTEGER := 10; + eie_before_nfts_count : INTEGER := 4; + enable_adapter_half_rate_mode : STRING := "false"; + enable_ch0_pclk_out : STRING := "true"; + enable_completion_timeout_disable : STRING := "true"; + enable_coreclk_out_half_rate : STRING := "false"; + enable_ecrc_check : STRING := "true"; + enable_ecrc_gen : STRING := "true"; + enable_function_msi_support : STRING := "true"; + enable_function_msix_support : STRING := "false"; + enable_gen2_core : STRING := "true"; + enable_hip_x1_loopback : STRING := "false"; + enable_l1_aspm : STRING := "false"; + enable_msi_64bit_addressing : STRING := "true"; + enable_msi_masking : STRING := "false"; + enable_rcv0buf_a_we : STRING := "true"; + enable_rcv0buf_b_re : STRING := "true"; + enable_rcv0buf_output_regs : STRING := "false"; + enable_rcv1buf_a_we : STRING := "true"; + enable_rcv1buf_b_re : STRING := "true"; + enable_rcv1buf_output_regs : STRING := "false"; + enable_retrybuf_a_we : STRING := "true"; + enable_retrybuf_b_re : STRING := "true"; + enable_retrybuf_ecc : STRING := "false"; + enable_retrybuf_output_regs : STRING := "false"; + enable_retrybuf_x8_clk_stealing : INTEGER := 0; + enable_rx0buf_ecc : STRING := "false"; + enable_rx0buf_x8_clk_stealing : INTEGER := 0; + enable_rx1buf_ecc : STRING := "false"; + enable_rx1buf_x8_clk_stealing : INTEGER := 0; + enable_rx_buffer_checking : STRING := "false"; + enable_rx_ei_l0s_exit_refined : STRING := "false"; + enable_rx_reordering : STRING := "true"; + enable_slot_register : STRING := "false"; + endpoint_l0_latency : INTEGER := 0; + endpoint_l1_latency : INTEGER := 0; + expansion_base_address_register : INTEGER := 0; + extend_tag_field : STRING := "false"; + fc_init_timer : INTEGER := 1024; + flow_control_timeout_count : INTEGER := 200; + flow_control_update_count : INTEGER := 30; + gen2_diffclock_nfts_count : INTEGER := 255; + gen2_lane_rate_mode : STRING := "false"; + gen2_sameclock_nfts_count : INTEGER := 255; + hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + iei_logic : STRING := "DISABLE"; + indicator : INTEGER := 7; + l01_entry_latency : INTEGER := 31; + l0_exit_latency_diffclock : INTEGER := 6; + l0_exit_latency_sameclock : INTEGER := 6; + l1_exit_latency_diffclock : INTEGER := 0; + l1_exit_latency_sameclock : INTEGER := 0; + lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000"; + low_priority_vc : INTEGER := 0; + max_link_width : INTEGER := 4; + max_payload_size : INTEGER := 2; + maximum_current : INTEGER := 0; + migrated_from_prev_family : STRING := "false"; + millisecond_cycle_count : INTEGER := 0; + mram_bist_settings : STRING := ""; + msi_function_count : INTEGER := 2; + msix_pba_bir : INTEGER := 0; + msix_pba_offset : INTEGER := 0; + msix_table_bir : INTEGER := 0; + msix_table_offset : INTEGER := 0; + msix_table_size : INTEGER := 0; + no_command_completed : STRING := "true"; + no_soft_reset : STRING := "false"; + pcie_mode : STRING := "SHARED_MODE"; + pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; + port_link_number : INTEGER := 1; + port_address : INTEGER := 0; + register_pipe_signals : STRING := "false"; + retry_buffer_last_active_address : INTEGER := 4095; + retry_buffer_memory_settings : INTEGER := 0; + revision_id : INTEGER := 1; + rx0_adap_fifo_full_value : INTEGER := 9; + rx1_adap_fifo_full_value : INTEGER := 9; + rx_cdc_full_value : INTEGER := 12; + rx_idl_os_count : INTEGER := 0; + rx_ptr0_nonposted_dpram_max : INTEGER := 0; + rx_ptr0_nonposted_dpram_min : INTEGER := 0; + rx_ptr0_posted_dpram_max : INTEGER := 0; + rx_ptr0_posted_dpram_min : INTEGER := 0; + rx_ptr1_nonposted_dpram_max : INTEGER := 0; + rx_ptr1_nonposted_dpram_min : INTEGER := 0; + rx_ptr1_posted_dpram_max : INTEGER := 0; + rx_ptr1_posted_dpram_min : INTEGER := 0; + sameclock_nfts_count : INTEGER := 128; + single_rx_detect : INTEGER := 0; + skp_os_schedule_count : INTEGER := 0; + slot_number : INTEGER := 0; + slot_power_limit : INTEGER := 0; + slot_power_scale : INTEGER := 0; + ssid : INTEGER := 0; + ssvid : INTEGER := 0; + subsystem_device_id : INTEGER := 1; + subsystem_vendor_id : INTEGER := 4466; + surprise_down_error_support : STRING := "false"; + tx0_adap_fifo_full_value : INTEGER := 11; + tx1_adap_fifo_full_value : INTEGER := 11; + tx_cdc_full_value : INTEGER := 12; + tx_cdc_stop_dummy_full_value : INTEGER := 11; + use_crc_forwarding : STRING := "false"; + vc0_clk_enable : STRING := "true"; + vc0_rx_buffer_memory_settings : INTEGER := 0; + vc0_rx_flow_ctrl_compl_data : INTEGER := 448; + vc0_rx_flow_ctrl_compl_header : INTEGER := 112; + vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc0_rx_flow_ctrl_posted_data : INTEGER := 360; + vc0_rx_flow_ctrl_posted_header : INTEGER := 50; + vc1_clk_enable : STRING := "false"; + vc1_rx_buffer_memory_settings : INTEGER := 0; + vc1_rx_flow_ctrl_compl_data : INTEGER := 448; + vc1_rx_flow_ctrl_compl_header : INTEGER := 112; + vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc1_rx_flow_ctrl_posted_data : INTEGER := 360; + vc1_rx_flow_ctrl_posted_header : INTEGER := 50; + vc_arbitration : INTEGER := 1; + vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + vendor_id : INTEGER := 4466 + ); + PORT ( + test_in : IN STD_LOGIC; + csr_hip_in : OUT STD_LOGIC_VECTOR(1759 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneiv_pciehip_hip_top + PORT ( + mdio_out : OUT STD_LOGIC; + data_enable_n : OUT STD_LOGIC; + dprio_curr_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + mdc : IN STD_LOGIC; + dev_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + port_addr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + mdio_in : IN STD_LOGIC; + mdio_dis : IN STD_LOGIC; + ser_shift_load : IN STD_LOGIC; + csr_hip_in : IN STD_LOGIC_VECTOR(1631 DOWNTO 0); + csr_hip_in_reserved : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + hip_base_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + lmi_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + lmi_ack : OUT STD_LOGIC; + lmi_rden : IN STD_LOGIC; + lmi_wren : IN STD_LOGIC; + lmi_addr : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + lmi_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + reset_status : OUT STD_LOGIC; + l2_exit : OUT STD_LOGIC; + hotrst_exit : OUT STD_LOGIC; + dlup_exit : OUT STD_LOGIC; + pld_clk : IN STD_LOGIC; + pld_srst : IN STD_LOGIC; + pld_rst : IN STD_LOGIC; + pclk_ch0 : IN STD_LOGIC; + pclk_central : IN STD_LOGIC; + pll_fixed_clk : IN STD_LOGIC; + phy_rst : IN STD_LOGIC; + phy_srst : IN STD_LOGIC; + core_clk_in : IN STD_LOGIC; + core_clk_out : OUT STD_LOGIC; + core_rst : IN STD_LOGIC; + core_por : IN STD_LOGIC; + core_crst : IN STD_LOGIC; + core_srst : IN STD_LOGIC; + swdn_wake : OUT STD_LOGIC; + swup_hotrst : OUT STD_LOGIC; + swdn_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + swup_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + rx_valid_vc0 : OUT STD_LOGIC; + rx_err_vc0 : OUT STD_LOGIC; + rx_bar_dec_vc0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc0_0 : OUT STD_LOGIC; + rx_eop_vc0_0 : OUT STD_LOGIC; + rx_data_vc0_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc0_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc0_1 : OUT STD_LOGIC; + rx_eop_vc0_1 : OUT STD_LOGIC; + rx_data_vc0_1 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc0_1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_fifo_full_vc0 : OUT STD_LOGIC; + rx_fifo_empty_vc0 : OUT STD_LOGIC; + rx_fifo_wrp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_fifo_rdp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_cred_vc0 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0); + tx_ready_vc0 : OUT STD_LOGIC; + tx_fifo_full_vc0 : OUT STD_LOGIC; + tx_fifo_empty_vc0 : OUT STD_LOGIC; + tx_fifo_wrp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_fifo_rdp_vc0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_mask_vc0 : IN STD_LOGIC; + rx_ready_vc0 : IN STD_LOGIC; + tx_valid_vc0 : IN STD_LOGIC; + tx_err_vc0 : IN STD_LOGIC; + tx_sop_vc0_0 : IN STD_LOGIC; + tx_eop_vc0_0 : IN STD_LOGIC; + tx_data_vc0_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + tx_sop_vc0_1 : IN STD_LOGIC; + tx_eop_vc0_1 : IN STD_LOGIC; + tx_data_vc0_1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_valid_vc1 : OUT STD_LOGIC; + rx_err_vc1 : OUT STD_LOGIC; + rx_bar_dec_vc1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc1_0 : OUT STD_LOGIC; + rx_eop_vc1_0 : OUT STD_LOGIC; + rx_data_vc1_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc1_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_sop_vc1_1 : OUT STD_LOGIC; + rx_eop_vc1_1 : OUT STD_LOGIC; + rx_data_vc1_1 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + rx_be_vc1_1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + rx_fifo_full_vc1 : OUT STD_LOGIC; + rx_fifo_empty_vc1 : OUT STD_LOGIC; + rx_fifo_wrp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_fifo_rdp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_cred_vc1 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0); + tx_ready_vc1 : OUT STD_LOGIC; + tx_fifo_full_vc1 : OUT STD_LOGIC; + tx_fifo_empty_vc1 : OUT STD_LOGIC; + tx_fifo_wrp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tx_fifo_rdp_vc1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + rx_mask_vc1 : IN STD_LOGIC; + rx_ready_vc1 : IN STD_LOGIC; + tx_valid_vc1 : IN STD_LOGIC; + tx_err_vc1 : IN STD_LOGIC; + tx_sop_vc1_0 : IN STD_LOGIC; + tx_eop_vc1_0 : IN STD_LOGIC; + tx_data_vc1_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + tx_sop_vc1_1 : IN STD_LOGIC; + tx_eop_vc1_1 : IN STD_LOGIC; + tx_data_vc1_1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + tl_pme_to_sr : OUT STD_LOGIC; + tl_pme_to_cr : IN STD_LOGIC; + tl_pm_event : IN STD_LOGIC; + tl_pm_data : IN STD_LOGIC_VECTOR(9 DOWNTO 0); + tl_pm_auxpwr : IN STD_LOGIC; + tl_cfg_sts : OUT STD_LOGIC_VECTOR(52 DOWNTO 0); + tl_cfg_sts_wr : OUT STD_LOGIC; + tl_cfg_ctl : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + tl_cfg_ctl_wr : OUT STD_LOGIC; + tl_cfg_add : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tl_app_inta_ack : OUT STD_LOGIC; + tl_app_msi_ack : OUT STD_LOGIC; + int_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + tl_app_inta_sts : IN STD_LOGIC; + tl_app_msi_req : IN STD_LOGIC; + tl_app_msi_tc : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + tl_app_msi_num : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + tl_aer_msi_num : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + tl_pex_msi_num : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + tl_hpg_ctrler : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + dl_up : OUT STD_LOGIC; + dl_vc_status : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + dl_err_dll : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + dl_err_phy : OUT STD_LOGIC; + dl_rpbuf_emp : OUT STD_LOGIC; + dl_dll_req : OUT STD_LOGIC; + lane_act : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + link_up : OUT STD_LOGIC; + dl_ltssm : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + clr_rxpath : OUT STD_LOGIC; + dl_rx_val_pm : OUT STD_LOGIC; + dl_rx_typ_pm : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_tx_ack_pm : OUT STD_LOGIC; + dl_ack_phypm : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dl_rst_enter_comp_bit : OUT STD_LOGIC; + dl_rst_tx_margin_field : OUT STD_LOGIC; + dl_current_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + dl_current_deemp : OUT STD_LOGIC; + dl_link_auto_bdw_status : OUT STD_LOGIC; + dl_link_bdw_mng_status : OUT STD_LOGIC; + dl_ack_req_upfc : OUT STD_LOGIC; + dl_ack_snd_upfc : OUT STD_LOGIC; + dl_rx_ecrcchk : IN STD_LOGIC; + dl_aspm_cr0 : IN STD_LOGIC; + dl_comclk_reg : IN STD_LOGIC; + dl_vc_ctrl : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dl_vcid_map : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + dl_inh_dllp : IN STD_LOGIC; + dl_req_wake : IN STD_LOGIC; + dl_txcfg_extsy : IN STD_LOGIC; + dl_tx_req_pm : IN STD_LOGIC; + dl_tx_typ_pm : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_maxpload_dcr : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_req_phypm : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dl_req_phycfg : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dl_req_upfc : IN STD_LOGIC; + dl_snd_upfc : IN STD_LOGIC; + dl_typ_upfc : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + dl_vcid_upfc : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + dl_hdr_upfc : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dl_data_upfc : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dl_ctrl_link2 : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + test_out_hip : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + ev_1us : OUT STD_LOGIC; + ev_128ns : OUT STD_LOGIC; + wake_oen : OUT STD_LOGIC; + serr_out : OUT STD_LOGIC; + tl_slotclk_cfg : IN STD_LOGIC; + mode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + test_in_hip : IN STD_LOGIC_VECTOR(39 DOWNTO 0); + cpl_pending : IN STD_LOGIC; + cpl_err : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + rate : OUT STD_LOGIC; + rate_tied_to_gnd : OUT STD_LOGIC; + eidle_infer_sel0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph0 : OUT STD_LOGIC; + tx_margin0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak0 : OUT STD_LOGIC; + txdetectrx0 : OUT STD_LOGIC; + txelecidle0 : OUT STD_LOGIC; + txcompl0 : OUT STD_LOGIC; + rxpolarity0 : OUT STD_LOGIC; + powerdown0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak0 : IN STD_LOGIC; + rxvalid0 : IN STD_LOGIC; + phystatus0 : IN STD_LOGIC; + rxelecidle0 : IN STD_LOGIC; + rxstatus0 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph1 : OUT STD_LOGIC; + tx_margin1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak1 : OUT STD_LOGIC; + txdetectrx1 : OUT STD_LOGIC; + txelecidle1 : OUT STD_LOGIC; + txcompl1 : OUT STD_LOGIC; + rxpolarity1 : OUT STD_LOGIC; + powerdown1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak1 : IN STD_LOGIC; + rxvalid1 : IN STD_LOGIC; + phystatus1 : IN STD_LOGIC; + rxelecidle1 : IN STD_LOGIC; + rxstatus1 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph2 : OUT STD_LOGIC; + tx_margin2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak2 : OUT STD_LOGIC; + txdetectrx2 : OUT STD_LOGIC; + txelecidle2 : OUT STD_LOGIC; + txcompl2 : OUT STD_LOGIC; + rxpolarity2 : OUT STD_LOGIC; + powerdown2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak2 : IN STD_LOGIC; + rxvalid2 : IN STD_LOGIC; + phystatus2 : IN STD_LOGIC; + rxelecidle2 : IN STD_LOGIC; + rxstatus2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel3 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph3 : OUT STD_LOGIC; + tx_margin3 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak3 : OUT STD_LOGIC; + txdetectrx3 : OUT STD_LOGIC; + txelecidle3 : OUT STD_LOGIC; + txcompl3 : OUT STD_LOGIC; + rxpolarity3 : OUT STD_LOGIC; + powerdown3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak3 : IN STD_LOGIC; + rxvalid3 : IN STD_LOGIC; + phystatus3 : IN STD_LOGIC; + rxelecidle3 : IN STD_LOGIC; + rxstatus3 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel4 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph4 : OUT STD_LOGIC; + tx_margin4 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata4 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak4 : OUT STD_LOGIC; + txdetectrx4 : OUT STD_LOGIC; + txelecidle4 : OUT STD_LOGIC; + txcompl4 : OUT STD_LOGIC; + rxpolarity4 : OUT STD_LOGIC; + powerdown4 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak4 : IN STD_LOGIC; + rxvalid4 : IN STD_LOGIC; + phystatus4 : IN STD_LOGIC; + rxelecidle4 : IN STD_LOGIC; + rxstatus4 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel5 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph5 : OUT STD_LOGIC; + tx_margin5 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata5 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak5 : OUT STD_LOGIC; + txdetectrx5 : OUT STD_LOGIC; + txelecidle5 : OUT STD_LOGIC; + txcompl5 : OUT STD_LOGIC; + rxpolarity5 : OUT STD_LOGIC; + powerdown5 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak5 : IN STD_LOGIC; + rxvalid5 : IN STD_LOGIC; + phystatus5 : IN STD_LOGIC; + rxelecidle5 : IN STD_LOGIC; + rxstatus5 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel6 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph6 : OUT STD_LOGIC; + tx_margin6 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata6 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak6 : OUT STD_LOGIC; + txdetectrx6 : OUT STD_LOGIC; + txelecidle6 : OUT STD_LOGIC; + txcompl6 : OUT STD_LOGIC; + rxpolarity6 : OUT STD_LOGIC; + powerdown6 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak6 : IN STD_LOGIC; + rxvalid6 : IN STD_LOGIC; + phystatus6 : IN STD_LOGIC; + rxelecidle6 : IN STD_LOGIC; + rxstatus6 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + eidle_infer_sel7 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + tx_deemph7 : OUT STD_LOGIC; + tx_margin7 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + txdata7 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txdatak7 : OUT STD_LOGIC; + txdetectrx7 : OUT STD_LOGIC; + txelecidle7 : OUT STD_LOGIC; + txcompl7 : OUT STD_LOGIC; + rxpolarity7 : OUT STD_LOGIC; + powerdown7 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + rxdata7 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + rxdatak7 : IN STD_LOGIC; + rxvalid7 : IN STD_LOGIC; + phystatus7 : IN STD_LOGIC; + rxelecidle7 : IN STD_LOGIC; + rxstatus7 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + ltssm_l0_state : OUT STD_LOGIC; + mram_red_sclk : IN STD_LOGIC; + mram_red_enscan : IN STD_LOGIC; + mram_red_scen : IN STD_LOGIC; + mram_red_scin : IN STD_LOGIC; + mram_red_scsel : IN STD_LOGIC; + mram_red_scrst : IN STD_LOGIC; + mram_red_scout : OUT STD_LOGIC; + mram_regscanen : IN STD_LOGIC; + mram_regscanin : IN STD_LOGIC; + mram_regscanout : OUT STD_LOGIC; + mram_hip_test_enable : IN STD_LOGIC; + bist_testen : IN STD_LOGIC; + bist_scanin : IN STD_LOGIC; + bist_scanen : IN STD_LOGIC; + bisten_rpl : IN STD_LOGIC; + bisten_rcv0 : IN STD_LOGIC; + bisten_rcv1 : IN STD_LOGIC; + bist_scanout_rpl : OUT STD_LOGIC; + bist_scanout_rcv0 : OUT STD_LOGIC; + bist_scanout_rcv1 : OUT STD_LOGIC; + bist_donea_rpl : OUT STD_LOGIC; + bist_doneb_rpl : OUT STD_LOGIC; + bist_pass_rpl : OUT STD_LOGIC; + derr_rpl : OUT STD_LOGIC; + derr_cor_ext_rpl : OUT STD_LOGIC; + bist_donea_rcv0 : OUT STD_LOGIC; + bist_doneb_rcv0 : OUT STD_LOGIC; + bist_pass_rcv0 : OUT STD_LOGIC; + derr_cor_ext_rcv0 : OUT STD_LOGIC; + bist_donea_rcv1 : OUT STD_LOGIC; + bist_doneb_rcv1 : OUT STD_LOGIC; + bist_pass_rcv1 : OUT STD_LOGIC; + derr_cor_ext_rcv1 : OUT STD_LOGIC; + scan_mode_n : IN STD_LOGIC; + scan_en : IN STD_LOGIC; + nfrzdrv : IN STD_LOGIC; + frzreg : IN STD_LOGIC; + frzlogic : IN STD_LOGIC; + id_rpl : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + id_rcv0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + id_rcv1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + plniotri : IN STD_LOGIC; + entest : IN STD_LOGIC; + npor : IN STD_LOGIC; + dbg_pipex1_rx : IN STD_LOGIC_VECTOR(14 DOWNTO 0); + hip_extrain : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + hip_extraclkin : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + hip_extraout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); + hip_extraclkout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + END COMPONENT; + + + -- *** End of Section 5 *** + + -- *** Section 6 -- Parameter declarations and default values *** + + -- *** End of Section 6 *** + + -- *** Section 7 -- Port declarations with defaults, if any *** + + -- This section will always be empty for WYSIWYG atoms + -- tri1 devclrn; //sample + + -- *** End of Section 7 *** + + SIGNAL test_in : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- CSR vector ---------------- --------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + SIGNAL init_hip_in : STD_LOGIC_VECTOR(1759 DOWNTO 0); + + --/////////////////////////////////////////////////////////////////////////// + -- non-kits parameters ---------------- -----------------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL init_deviceaddress : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL init_hipbaseaddress : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL init_portaddress : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL deviceaddress_in : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL hipbaseaddress_in : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL portaddress_in : STD_LOGIC_VECTOR(4 DOWNTO 0); + + --/////////////////////////////////////////////////////////////////////////// + -- WYS input interface signals --------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL bistenrcv0_in : STD_LOGIC; + SIGNAL bistenrcv1_in : STD_LOGIC; + SIGNAL bistenrpl_in : STD_LOGIC; + SIGNAL bistscanen_in : STD_LOGIC; + SIGNAL bistscanin_in : STD_LOGIC; + SIGNAL bisttesten_in : STD_LOGIC; + SIGNAL coreclkin_in : STD_LOGIC; + SIGNAL corecrst_in : STD_LOGIC; + SIGNAL corepor_in : STD_LOGIC; + SIGNAL corerst_in : STD_LOGIC; + SIGNAL coresrst_in : STD_LOGIC; + SIGNAL cplerr_in : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL cplpending_in : STD_LOGIC; + SIGNAL dbgpipex1rx_in : STD_LOGIC_VECTOR(14 DOWNTO 0); + SIGNAL dlaspmcr0_in : STD_LOGIC; + SIGNAL dlcomclkreg_in : STD_LOGIC; + SIGNAL dlctrllink2_in : STD_LOGIC_VECTOR(12 DOWNTO 0); + SIGNAL dldataupfc_in : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL dlhdrupfc_in : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dlinhdllp_in : STD_LOGIC; + SIGNAL dlmaxploaddcr_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dlreqphycfg_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dlreqphypm_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dlrequpfc_in : STD_LOGIC; + SIGNAL dlreqwake_in : STD_LOGIC; + SIGNAL dlrxecrcchk_in : STD_LOGIC; + SIGNAL dlsndupfc_in : STD_LOGIC; + SIGNAL dltxcfgextsy_in : STD_LOGIC; + SIGNAL dltxreqpm_in : STD_LOGIC; + SIGNAL dltxtyppm_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dltypupfc_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dlvcctrl_in : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dlvcidmap_in : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL dlvcidupfc_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dpclk_in : STD_LOGIC; + SIGNAL dpriodisable_in : STD_LOGIC; + SIGNAL dprioin_in : STD_LOGIC; + SIGNAL dprioload_in : STD_LOGIC; + SIGNAL extrain_in : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL lmiaddr_in : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL lmidin_in : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL lmirden_in : STD_LOGIC; + SIGNAL lmiwren_in : STD_LOGIC; + SIGNAL mode_in : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL mramhiptestenable_in : STD_LOGIC; + SIGNAL mramregscanen_in : STD_LOGIC; + SIGNAL mramregscanin_in : STD_LOGIC; + SIGNAL pclkcentral_in : STD_LOGIC; + SIGNAL pclkch0_in : STD_LOGIC; + SIGNAL phyrst_in : STD_LOGIC; + SIGNAL physrst_in : STD_LOGIC; + SIGNAL phystatus_in : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL pldclk_in : STD_LOGIC; + SIGNAL pldrst_in : STD_LOGIC; + SIGNAL pldsrst_in : STD_LOGIC; + SIGNAL pllfixedclk_in : STD_LOGIC; + SIGNAL rxdata_in : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rxdatak_in : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxelecidle_in : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxmaskvc0_in : STD_LOGIC; + SIGNAL rxmaskvc1_in : STD_LOGIC; + SIGNAL rxreadyvc0_in : STD_LOGIC; + SIGNAL rxreadyvc1_in : STD_LOGIC; + SIGNAL rxstatus_in : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL rxvalid_in : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL scanen_in : STD_LOGIC; + SIGNAL scanmoden_in : STD_LOGIC; + SIGNAL swdnin_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL swupin_in : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL testin_in : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL tlaermsinum_in : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL tlappintasts_in : STD_LOGIC; + SIGNAL tlappmsinum_in : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL tlappmsireq_in : STD_LOGIC; + SIGNAL tlappmsitc_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL tlhpgctrler_in : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL tlpexmsinum_in : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL tlpmauxpwr_in : STD_LOGIC; + SIGNAL tlpmdata_in : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL tlpmetocr_in : STD_LOGIC; + SIGNAL tlpmevent_in : STD_LOGIC; + SIGNAL tlslotclkcfg_in : STD_LOGIC; + SIGNAL txdatavc00_in : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL txdatavc01_in : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL txdatavc10_in : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL txdatavc11_in : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL txeopvc00_in : STD_LOGIC; + SIGNAL txeopvc01_in : STD_LOGIC; + SIGNAL txeopvc10_in : STD_LOGIC; + SIGNAL txeopvc11_in : STD_LOGIC; + SIGNAL txerrvc0_in : STD_LOGIC; + SIGNAL txerrvc1_in : STD_LOGIC; + SIGNAL txsopvc00_in : STD_LOGIC; + SIGNAL txsopvc01_in : STD_LOGIC; + SIGNAL txsopvc10_in : STD_LOGIC; + SIGNAL txsopvc11_in : STD_LOGIC; + SIGNAL txvalidvc0_in : STD_LOGIC; + SIGNAL txvalidvc1_in : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- WYS input interconnect path delay buffers ------------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL bistenrcv0_ipd : STD_LOGIC; + SIGNAL bistenrcv1_ipd : STD_LOGIC; + SIGNAL bistenrpl_ipd : STD_LOGIC; + SIGNAL bistscanen_ipd : STD_LOGIC; + SIGNAL bistscanin_ipd : STD_LOGIC; + SIGNAL bisttesten_ipd : STD_LOGIC; + SIGNAL coreclkin_ipd : STD_LOGIC; + SIGNAL corecrst_ipd : STD_LOGIC; + SIGNAL corepor_ipd : STD_LOGIC; + SIGNAL corerst_ipd : STD_LOGIC; + SIGNAL coresrst_ipd : STD_LOGIC; + SIGNAL cplerr_ipd : STD_LOGIC_VECTOR(7 - 1 DOWNTO 0); + SIGNAL cplpending_ipd : STD_LOGIC; + SIGNAL dbgpipex1rx_ipd : STD_LOGIC_VECTOR(15 - 1 DOWNTO 0); + SIGNAL dlaspmcr0_ipd : STD_LOGIC; + SIGNAL dlcomclkreg_ipd : STD_LOGIC; + SIGNAL dlctrllink2_ipd : STD_LOGIC_VECTOR(13 - 1 DOWNTO 0); + SIGNAL dldataupfc_ipd : STD_LOGIC_VECTOR(12 - 1 DOWNTO 0); + SIGNAL dlhdrupfc_ipd : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + SIGNAL dlinhdllp_ipd : STD_LOGIC; + SIGNAL dlmaxploaddcr_ipd : STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + SIGNAL dlreqphycfg_ipd : STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + SIGNAL dlreqphypm_ipd : STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + SIGNAL dlrequpfc_ipd : STD_LOGIC; + SIGNAL dlreqwake_ipd : STD_LOGIC; + SIGNAL dlrxecrcchk_ipd : STD_LOGIC; + SIGNAL dlsndupfc_ipd : STD_LOGIC; + SIGNAL dltxcfgextsy_ipd : STD_LOGIC; + SIGNAL dltxreqpm_ipd : STD_LOGIC; + SIGNAL dltxtyppm_ipd : STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + SIGNAL dltypupfc_ipd : STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + SIGNAL dlvcctrl_ipd : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + SIGNAL dlvcidmap_ipd : STD_LOGIC_VECTOR(24 - 1 DOWNTO 0); + SIGNAL dlvcidupfc_ipd : STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + SIGNAL dpclk_ipd : STD_LOGIC; + SIGNAL dpriodisable_ipd : STD_LOGIC; + SIGNAL dprioin_ipd : STD_LOGIC; + SIGNAL dprioload_ipd : STD_LOGIC; + SIGNAL extrain_ipd : STD_LOGIC_VECTOR(12 - 1 DOWNTO 0); + SIGNAL lmiaddr_ipd : STD_LOGIC_VECTOR(12 - 1 DOWNTO 0); + SIGNAL lmidin_ipd : STD_LOGIC_VECTOR(32 - 1 DOWNTO 0); + SIGNAL lmirden_ipd : STD_LOGIC; + SIGNAL lmiwren_ipd : STD_LOGIC; + SIGNAL mode_ipd : STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + SIGNAL mramhiptestenable_ipd : STD_LOGIC; + SIGNAL mramregscanen_ipd : STD_LOGIC; + SIGNAL mramregscanin_ipd : STD_LOGIC; + SIGNAL pclkcentral_ipd : STD_LOGIC; + SIGNAL pclkch0_ipd : STD_LOGIC; + SIGNAL phyrst_ipd : STD_LOGIC; + SIGNAL physrst_ipd : STD_LOGIC; + SIGNAL phystatus_ipd : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + SIGNAL pldclk_ipd : STD_LOGIC; + SIGNAL pldrst_ipd : STD_LOGIC; + SIGNAL pldsrst_ipd : STD_LOGIC; + SIGNAL pllfixedclk_ipd : STD_LOGIC; + SIGNAL rxdata_ipd : STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + SIGNAL rxdatak_ipd : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + SIGNAL rxelecidle_ipd : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + SIGNAL rxmaskvc0_ipd : STD_LOGIC; + SIGNAL rxmaskvc1_ipd : STD_LOGIC; + SIGNAL rxreadyvc0_ipd : STD_LOGIC; + SIGNAL rxreadyvc1_ipd : STD_LOGIC; + SIGNAL rxstatus_ipd : STD_LOGIC_VECTOR(24 - 1 DOWNTO 0); + SIGNAL rxvalid_ipd : STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + SIGNAL scanen_ipd : STD_LOGIC; + SIGNAL scanmoden_ipd : STD_LOGIC; + SIGNAL swdnin_ipd : STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + SIGNAL swupin_ipd : STD_LOGIC_VECTOR(7 - 1 DOWNTO 0); + SIGNAL testin_ipd : STD_LOGIC_VECTOR(40 - 1 DOWNTO 0); + SIGNAL tlaermsinum_ipd : STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + SIGNAL tlappintasts_ipd : STD_LOGIC; + SIGNAL tlappmsinum_ipd : STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + SIGNAL tlappmsireq_ipd : STD_LOGIC; + SIGNAL tlappmsitc_ipd : STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + SIGNAL tlhpgctrler_ipd : STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + SIGNAL tlpexmsinum_ipd : STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + SIGNAL tlpmauxpwr_ipd : STD_LOGIC; + SIGNAL tlpmdata_ipd : STD_LOGIC_VECTOR(10 - 1 DOWNTO 0); + SIGNAL tlpmetocr_ipd : STD_LOGIC; + SIGNAL tlpmevent_ipd : STD_LOGIC; + SIGNAL tlslotclkcfg_ipd : STD_LOGIC; + SIGNAL txdatavc00_ipd : STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + SIGNAL txdatavc01_ipd : STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + SIGNAL txdatavc10_ipd : STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + SIGNAL txdatavc11_ipd : STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + SIGNAL txeopvc00_ipd : STD_LOGIC; + SIGNAL txeopvc01_ipd : STD_LOGIC; + SIGNAL txeopvc10_ipd : STD_LOGIC; + SIGNAL txeopvc11_ipd : STD_LOGIC; + SIGNAL txerrvc0_ipd : STD_LOGIC; + SIGNAL txerrvc1_ipd : STD_LOGIC; + SIGNAL txsopvc00_ipd : STD_LOGIC; + SIGNAL txsopvc01_ipd : STD_LOGIC; + SIGNAL txsopvc10_ipd : STD_LOGIC; + SIGNAL txsopvc11_ipd : STD_LOGIC; + SIGNAL txvalidvc0_ipd : STD_LOGIC; + SIGNAL txvalidvc1_ipd : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- WYS output tmp ---------------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL bistdonearcv0_tmp : STD_LOGIC; + SIGNAL bistdonearcv1_tmp : STD_LOGIC; + SIGNAL bistdonearpl_tmp : STD_LOGIC; + SIGNAL bistdonebrcv0_tmp : STD_LOGIC; + SIGNAL bistdonebrcv1_tmp : STD_LOGIC; + SIGNAL bistdonebrpl_tmp : STD_LOGIC; + SIGNAL bistpassrcv0_tmp : STD_LOGIC; + SIGNAL bistpassrcv1_tmp : STD_LOGIC; + SIGNAL bistpassrpl_tmp : STD_LOGIC; + SIGNAL bistscanoutrcv0_tmp : STD_LOGIC; + SIGNAL bistscanoutrcv1_tmp : STD_LOGIC; + SIGNAL bistscanoutrpl_tmp : STD_LOGIC; + SIGNAL clrrxpath_tmp : STD_LOGIC; + SIGNAL coreclkout_tmp : STD_LOGIC; + SIGNAL dataenablen_tmp : STD_LOGIC; + SIGNAL derrcorextrcv0_tmp : STD_LOGIC; + SIGNAL derrcorextrcv1_tmp : STD_LOGIC; + SIGNAL derrcorextrpl_tmp : STD_LOGIC; + SIGNAL derrrpl_tmp : STD_LOGIC; + SIGNAL dlackphypm_tmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dlackrequpfc_tmp : STD_LOGIC; + SIGNAL dlacksndupfc_tmp : STD_LOGIC; + SIGNAL dlcurrentdeemp_tmp : STD_LOGIC; + SIGNAL dlcurrentspeed_tmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dldllreq_tmp : STD_LOGIC; + SIGNAL dlerrdll_tmp : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dlerrphy_tmp : STD_LOGIC; + SIGNAL dllinkautobdwstatus_tmp : STD_LOGIC; + SIGNAL dllinkbdwmngstatus_tmp : STD_LOGIC; + SIGNAL dlltssm_tmp : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dlrpbufemp_tmp : STD_LOGIC; + SIGNAL dlrstentercompbit_tmp : STD_LOGIC; + SIGNAL dlrsttxmarginfield_tmp : STD_LOGIC; + SIGNAL dlrxtyppm_tmp : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dlrxvalpm_tmp : STD_LOGIC; + SIGNAL dltxackpm_tmp : STD_LOGIC; + SIGNAL dlup_tmp : STD_LOGIC; + SIGNAL dlupexit_tmp : STD_LOGIC; + SIGNAL dlvcstatus_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dprioout_tmp : STD_LOGIC; + SIGNAL dpriostate_tmp : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL eidleinfersel_tmp : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL ev128ns_tmp : STD_LOGIC; + SIGNAL ev1us_tmp : STD_LOGIC; + SIGNAL extraclkout_tmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL extraout_tmp : STD_LOGIC_VECTOR(14 DOWNTO 0); + SIGNAL gen2rate_tmp : STD_LOGIC; + SIGNAL gen2rategnd_tmp : STD_LOGIC; + SIGNAL hipextraclkout_tmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL hipextraout_tmp : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL hotrstexit_tmp : STD_LOGIC; + SIGNAL intstatus_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL l2exit_tmp : STD_LOGIC; + SIGNAL laneact_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL linkup_tmp : STD_LOGIC; + SIGNAL lmiack_tmp : STD_LOGIC; + SIGNAL lmidout_tmp : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL ltssml0state_tmp : STD_LOGIC; + SIGNAL mramregscanout_tmp : STD_LOGIC; + SIGNAL powerdown_tmp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL resetstatus_tmp : STD_LOGIC; + SIGNAL rxbardecvc0_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxbardecvc1_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxbevc00_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxbevc01_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxbevc10_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxbevc11_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxdatavc00_tmp : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rxdatavc01_tmp : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rxdatavc10_tmp : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rxdatavc11_tmp : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL rxeopvc00_tmp : STD_LOGIC; + SIGNAL rxeopvc01_tmp : STD_LOGIC; + SIGNAL rxeopvc10_tmp : STD_LOGIC; + SIGNAL rxeopvc11_tmp : STD_LOGIC; + SIGNAL rxerrvc0_tmp : STD_LOGIC; + SIGNAL rxerrvc1_tmp : STD_LOGIC; + SIGNAL rxfifoemptyvc0_tmp : STD_LOGIC; + SIGNAL rxfifoemptyvc1_tmp : STD_LOGIC; + SIGNAL rxfifofullvc0_tmp : STD_LOGIC; + SIGNAL rxfifofullvc1_tmp : STD_LOGIC; + SIGNAL rxfifordpvc0_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxfifordpvc1_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxfifowrpvc0_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxfifowrpvc1_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rxpolarity_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxsopvc00_tmp : STD_LOGIC; + SIGNAL rxsopvc01_tmp : STD_LOGIC; + SIGNAL rxsopvc10_tmp : STD_LOGIC; + SIGNAL rxsopvc11_tmp : STD_LOGIC; + SIGNAL rxvalidvc0_tmp : STD_LOGIC; + SIGNAL rxvalidvc1_tmp : STD_LOGIC; + SIGNAL r2cerr0ext_tmp : STD_LOGIC; + SIGNAL serrout_tmp : STD_LOGIC; + SIGNAL successspeednegoint_tmp : STD_LOGIC; + SIGNAL swdnwake_tmp : STD_LOGIC; + SIGNAL swuphotrst_tmp : STD_LOGIC; + SIGNAL testout_tmp : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL tlappintaack_tmp : STD_LOGIC; + SIGNAL tlappmsiack_tmp : STD_LOGIC; + SIGNAL tlcfgadd_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL tlcfgctl_tmp : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL tlcfgctlwr_tmp : STD_LOGIC; + SIGNAL tlcfgsts_tmp : STD_LOGIC_VECTOR(52 DOWNTO 0); + SIGNAL tlcfgstswr_tmp : STD_LOGIC; + SIGNAL tlpmetosr_tmp : STD_LOGIC; + SIGNAL txcompl_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txcredvc0_tmp : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL txcredvc1_tmp : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL txdata_tmp : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL txdatak_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdeemph_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txdetectrx_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txelecidle_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL txfifoemptyvc0_tmp : STD_LOGIC; + SIGNAL txfifoemptyvc1_tmp : STD_LOGIC; + SIGNAL txfifofullvc0_tmp : STD_LOGIC; + SIGNAL txfifofullvc1_tmp : STD_LOGIC; + SIGNAL txfifordpvc0_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txfifordpvc1_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txfifowrpvc0_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txfifowrpvc1_tmp : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL txmargin_tmp : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL txreadyvc0_tmp : STD_LOGIC; + SIGNAL txreadyvc1_tmp : STD_LOGIC; + SIGNAL wakeoen_tmp : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- RTL input declarations------------- ------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL ht_in_bist_scanen : STD_LOGIC; + SIGNAL ht_in_bist_scanin : STD_LOGIC; + SIGNAL ht_in_bist_testen : STD_LOGIC; + SIGNAL ht_in_bisten_rcv0 : STD_LOGIC; + SIGNAL ht_in_bisten_rcv1 : STD_LOGIC; + SIGNAL ht_in_bisten_rpl : STD_LOGIC; + SIGNAL ht_in_core_clk_in : STD_LOGIC; + SIGNAL ht_in_core_crst : STD_LOGIC; + SIGNAL ht_in_core_por : STD_LOGIC; + SIGNAL ht_in_core_rst : STD_LOGIC; + SIGNAL ht_in_core_srst : STD_LOGIC; + SIGNAL ht_in_cpl_err : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL ht_in_cpl_pending : STD_LOGIC; + SIGNAL ht_in_dbg_pipex1_rx : STD_LOGIC_VECTOR(14 DOWNTO 0); + SIGNAL ht_in_dev_addr : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_in_dl_aspm_cr0 : STD_LOGIC; -- ww7.2 + SIGNAL ht_in_dl_comclk_reg : STD_LOGIC; -- ww7.2 + SIGNAL ht_in_dl_ctrl_link2 : STD_LOGIC_VECTOR(12 DOWNTO 0); + SIGNAL ht_in_dl_data_upfc : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL ht_in_dl_hdr_upfc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_dl_inh_dllp : STD_LOGIC; + SIGNAL ht_in_dl_maxpload_dcr : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_dl_req_phycfg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_in_dl_req_phypm : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_in_dl_req_upfc : STD_LOGIC; + SIGNAL ht_in_dl_req_wake : STD_LOGIC; + SIGNAL ht_in_dl_rx_ecrcchk : STD_LOGIC; + SIGNAL ht_in_dl_snd_upfc : STD_LOGIC; + SIGNAL ht_in_dl_tx_req_pm : STD_LOGIC; + SIGNAL ht_in_dl_tx_typ_pm : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_dl_txcfg_extsy : STD_LOGIC; + SIGNAL ht_in_dl_typ_upfc : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_in_dl_vc_ctrl : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_dl_vcid_map : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL ht_in_dl_vcid_upfc : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_hip_extrain : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL ht_in_hip_extraclkin : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_in_entest : STD_LOGIC; + SIGNAL ht_in_frzlogic : STD_LOGIC; + SIGNAL ht_in_frzreg : STD_LOGIC; + SIGNAL ht_in_hip_base_addr : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_id_rcv0 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_id_rcv1 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_id_rpl : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_lmi_addr : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL ht_in_lmi_din : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL ht_in_lmi_rden : STD_LOGIC; + SIGNAL ht_in_lmi_wren : STD_LOGIC; + SIGNAL ht_in_mdc : STD_LOGIC; + SIGNAL ht_in_mdio_dis : STD_LOGIC; + SIGNAL ht_in_mdio_in : STD_LOGIC; + SIGNAL ht_in_mode : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_in_mram_hip_test_enable : STD_LOGIC; --ww7.2 + SIGNAL ht_in_mram_red_enscan : STD_LOGIC; --ww7.2 + SIGNAL ht_in_mram_red_scen : STD_LOGIC; + SIGNAL ht_in_mram_red_scin : STD_LOGIC; + SIGNAL ht_in_mram_red_sclk : STD_LOGIC; + SIGNAL ht_in_mram_red_scrst : STD_LOGIC; + SIGNAL ht_in_mram_red_scsel : STD_LOGIC; + SIGNAL ht_in_mram_regscanen : STD_LOGIC; + SIGNAL ht_in_mram_regscanin : STD_LOGIC; + SIGNAL ht_in_nfrzdrv : STD_LOGIC; + SIGNAL ht_in_npor : STD_LOGIC; + SIGNAL ht_in_pclk_central : STD_LOGIC; + SIGNAL ht_in_pclk_ch0 : STD_LOGIC; + SIGNAL ht_in_phy_rst : STD_LOGIC; + SIGNAL ht_in_phy_srst : STD_LOGIC; + SIGNAL ht_in_phystatus0 : STD_LOGIC; + SIGNAL ht_in_phystatus1 : STD_LOGIC; + SIGNAL ht_in_phystatus2 : STD_LOGIC; + SIGNAL ht_in_phystatus3 : STD_LOGIC; + SIGNAL ht_in_phystatus4 : STD_LOGIC; + SIGNAL ht_in_phystatus5 : STD_LOGIC; + SIGNAL ht_in_phystatus6 : STD_LOGIC; + SIGNAL ht_in_phystatus7 : STD_LOGIC; + SIGNAL ht_in_pld_clk : STD_LOGIC; + SIGNAL ht_in_pld_rst : STD_LOGIC; + SIGNAL ht_in_pld_srst : STD_LOGIC; + SIGNAL ht_in_pll_fixed_clk : STD_LOGIC; + SIGNAL ht_in_plniotri : STD_LOGIC; + SIGNAL ht_in_port_addr : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_in_rx_mask_vc0 : STD_LOGIC; + SIGNAL ht_in_rx_mask_vc1 : STD_LOGIC; + SIGNAL ht_in_rx_ready_vc0 : STD_LOGIC; + SIGNAL ht_in_rx_ready_vc1 : STD_LOGIC; + SIGNAL ht_in_rxdata0 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdata1 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdata2 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdata3 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdata4 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdata5 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdata6 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdata7 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_in_rxdatak0 : STD_LOGIC; + SIGNAL ht_in_rxdatak1 : STD_LOGIC; + SIGNAL ht_in_rxdatak2 : STD_LOGIC; + SIGNAL ht_in_rxdatak3 : STD_LOGIC; + SIGNAL ht_in_rxdatak4 : STD_LOGIC; + SIGNAL ht_in_rxdatak5 : STD_LOGIC; + SIGNAL ht_in_rxdatak6 : STD_LOGIC; + SIGNAL ht_in_rxdatak7 : STD_LOGIC; + SIGNAL ht_in_rxelecidle0 : STD_LOGIC; + SIGNAL ht_in_rxelecidle1 : STD_LOGIC; + SIGNAL ht_in_rxelecidle2 : STD_LOGIC; + SIGNAL ht_in_rxelecidle3 : STD_LOGIC; + SIGNAL ht_in_rxelecidle4 : STD_LOGIC; + SIGNAL ht_in_rxelecidle5 : STD_LOGIC; + SIGNAL ht_in_rxelecidle6 : STD_LOGIC; + SIGNAL ht_in_rxelecidle7 : STD_LOGIC; + SIGNAL ht_in_rxstatus0 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxstatus1 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxstatus2 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxstatus3 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxstatus4 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxstatus5 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxstatus6 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxstatus7 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_rxvalid0 : STD_LOGIC; + SIGNAL ht_in_rxvalid1 : STD_LOGIC; + SIGNAL ht_in_rxvalid2 : STD_LOGIC; + SIGNAL ht_in_rxvalid3 : STD_LOGIC; + SIGNAL ht_in_rxvalid4 : STD_LOGIC; + SIGNAL ht_in_rxvalid5 : STD_LOGIC; + SIGNAL ht_in_rxvalid6 : STD_LOGIC; + SIGNAL ht_in_rxvalid7 : STD_LOGIC; + SIGNAL ht_in_scan_en : STD_LOGIC; + SIGNAL ht_in_scan_mode_n : STD_LOGIC; + SIGNAL ht_in_ser_shift_load : STD_LOGIC; + SIGNAL ht_in_swdn_in : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_swup_in : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL ht_in_test_in_hip : STD_LOGIC_VECTOR(39 DOWNTO 0); + SIGNAL ht_in_tl_aer_msi_num : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_in_tl_app_inta_sts : STD_LOGIC; + SIGNAL ht_in_tl_app_msi_num : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_in_tl_app_msi_req : STD_LOGIC; + SIGNAL ht_in_tl_app_msi_tc : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_in_tl_hpg_ctrler : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_in_tl_pex_msi_num : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_in_tl_pm_auxpwr : STD_LOGIC; + SIGNAL ht_in_tl_pm_data : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL ht_in_tl_pm_event : STD_LOGIC; + SIGNAL ht_in_tl_pme_to_cr : STD_LOGIC; + SIGNAL ht_in_tl_slotclk_cfg : STD_LOGIC; + SIGNAL ht_in_tx_data_vc0_0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_in_tx_data_vc0_1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_in_tx_data_vc1_0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_in_tx_data_vc1_1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_in_tx_eop_vc0_0 : STD_LOGIC; + SIGNAL ht_in_tx_eop_vc0_1 : STD_LOGIC; + SIGNAL ht_in_tx_eop_vc1_0 : STD_LOGIC; + SIGNAL ht_in_tx_eop_vc1_1 : STD_LOGIC; + SIGNAL ht_in_tx_err_vc0 : STD_LOGIC; + SIGNAL ht_in_tx_err_vc1 : STD_LOGIC; + SIGNAL ht_in_tx_sop_vc0_0 : STD_LOGIC; + SIGNAL ht_in_tx_sop_vc0_1 : STD_LOGIC; + SIGNAL ht_in_tx_sop_vc1_0 : STD_LOGIC; + SIGNAL ht_in_tx_sop_vc1_1 : STD_LOGIC; + SIGNAL ht_in_tx_valid_vc0 : STD_LOGIC; + SIGNAL ht_in_tx_valid_vc1 : STD_LOGIC; + + --/////////////////////////////////////////////////////////////////////////// + -- RTL output declarations------------- -----------------------------------// + --/////////////////////////////////////////////////////////////////////////// + SIGNAL ht_out_bist_donea_rcv0 : STD_LOGIC; + SIGNAL ht_out_bist_donea_rcv1 : STD_LOGIC; + SIGNAL ht_out_bist_donea_rpl : STD_LOGIC; + SIGNAL ht_out_bist_doneb_rcv0 : STD_LOGIC; + SIGNAL ht_out_bist_doneb_rcv1 : STD_LOGIC; + SIGNAL ht_out_bist_doneb_rpl : STD_LOGIC; + SIGNAL ht_out_bist_pass_rcv0 : STD_LOGIC; + SIGNAL ht_out_bist_pass_rcv1 : STD_LOGIC; + SIGNAL ht_out_bist_pass_rpl : STD_LOGIC; + SIGNAL ht_out_bist_scanout_rcv0 : STD_LOGIC; + SIGNAL ht_out_bist_scanout_rcv1 : STD_LOGIC; + SIGNAL ht_out_bist_scanout_rpl : STD_LOGIC; + SIGNAL ht_out_clr_rxpath : STD_LOGIC; + SIGNAL ht_out_core_clk_out : STD_LOGIC; + SIGNAL ht_out_data_enable_n : STD_LOGIC; + SIGNAL ht_out_derr_cor_ext_rcv0 : STD_LOGIC; + SIGNAL ht_out_derr_cor_ext_rcv1 : STD_LOGIC; + SIGNAL ht_out_derr_cor_ext_rpl : STD_LOGIC; + SIGNAL ht_out_derr_rpl : STD_LOGIC; + SIGNAL ht_out_dl_ack_phypm : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_dl_ack_req_upfc : STD_LOGIC; + SIGNAL ht_out_dl_ack_snd_upfc : STD_LOGIC; + SIGNAL ht_out_dl_current_deemp : STD_LOGIC; + SIGNAL ht_out_dl_current_speed : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_dl_dll_req : STD_LOGIC; + SIGNAL ht_out_dl_err_dll : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_out_dl_err_phy : STD_LOGIC; + SIGNAL ht_out_dl_link_auto_bdw_status : STD_LOGIC; + SIGNAL ht_out_dl_link_bdw_mng_status : STD_LOGIC; + SIGNAL ht_out_dl_ltssm : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ht_out_dl_rpbuf_emp : STD_LOGIC; + SIGNAL ht_out_dl_rst_enter_comp_bit : STD_LOGIC; + SIGNAL ht_out_dl_rst_tx_margin_field : STD_LOGIC; + SIGNAL ht_out_dl_rx_typ_pm : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_dl_rx_val_pm : STD_LOGIC; + SIGNAL ht_out_dl_tx_ack_pm : STD_LOGIC; + SIGNAL ht_out_dl_up : STD_LOGIC; + SIGNAL ht_out_dl_vc_status : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_dlup_exit : STD_LOGIC; + SIGNAL ht_out_dprio_curr_state : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel0 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel1 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel2 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel3 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel4 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel5 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel6 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_eidle_infer_sel7 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_ev_128ns : STD_LOGIC; + SIGNAL ht_out_ev_1us : STD_LOGIC; + SIGNAL ht_out_extraout : STD_LOGIC_VECTOR(14 DOWNTO 0); + SIGNAL ht_out_hip_extraclkout : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_hip_extraout : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL ht_out_hotrst_exit : STD_LOGIC; + SIGNAL ht_out_int_status : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_l2_exit : STD_LOGIC; + SIGNAL ht_out_lane_act : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_link_up : STD_LOGIC; + SIGNAL ht_out_lmi_ack : STD_LOGIC; + SIGNAL ht_out_lmi_dout : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL ht_out_ltssm_l0_state : STD_LOGIC; + SIGNAL ht_out_mdio_out : STD_LOGIC; + SIGNAL ht_out_mram_red_scout : STD_LOGIC; -- not needed in WYS + SIGNAL ht_out_mram_regscanout : STD_LOGIC; + SIGNAL ht_out_powerdown0 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_powerdown1 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_powerdown2 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_powerdown3 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_powerdown4 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_powerdown5 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_powerdown6 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_powerdown7 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ht_out_rate : STD_LOGIC; + SIGNAL ht_out_rate_tied_to_gnd : STD_LOGIC; + SIGNAL ht_out_reset_status : STD_LOGIC; + SIGNAL ht_out_rx_bar_dec_vc0 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_rx_bar_dec_vc1 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_rx_be_vc0_0 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_rx_be_vc0_1 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_rx_be_vc1_0 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_rx_be_vc1_1 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_rx_data_vc0_0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_out_rx_data_vc0_1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_out_rx_data_vc1_0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_out_rx_data_vc1_1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_out_rx_eop_vc0_0 : STD_LOGIC; + SIGNAL ht_out_rx_eop_vc0_1 : STD_LOGIC; + SIGNAL ht_out_rx_eop_vc1_0 : STD_LOGIC; + SIGNAL ht_out_rx_eop_vc1_1 : STD_LOGIC; + SIGNAL ht_out_rx_err_vc0 : STD_LOGIC; + SIGNAL ht_out_rx_err_vc1 : STD_LOGIC; + SIGNAL ht_out_rx_fifo_empty_vc0 : STD_LOGIC; + SIGNAL ht_out_rx_fifo_empty_vc1 : STD_LOGIC; + SIGNAL ht_out_rx_fifo_full_vc0 : STD_LOGIC; + SIGNAL ht_out_rx_fifo_full_vc1 : STD_LOGIC; + SIGNAL ht_out_rx_fifo_rdp_vc0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_rx_fifo_rdp_vc1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_rx_fifo_wrp_vc0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_rx_fifo_wrp_vc1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_rx_sop_vc0_0 : STD_LOGIC; + SIGNAL ht_out_rx_sop_vc0_1 : STD_LOGIC; + SIGNAL ht_out_rx_sop_vc1_0 : STD_LOGIC; + SIGNAL ht_out_rx_sop_vc1_1 : STD_LOGIC; + SIGNAL ht_out_rx_valid_vc0 : STD_LOGIC; + SIGNAL ht_out_rx_valid_vc1 : STD_LOGIC; + SIGNAL ht_out_rxpolarity0 : STD_LOGIC; + SIGNAL ht_out_rxpolarity1 : STD_LOGIC; + SIGNAL ht_out_rxpolarity2 : STD_LOGIC; + SIGNAL ht_out_rxpolarity3 : STD_LOGIC; + SIGNAL ht_out_rxpolarity4 : STD_LOGIC; + SIGNAL ht_out_rxpolarity5 : STD_LOGIC; + SIGNAL ht_out_rxpolarity6 : STD_LOGIC; + SIGNAL ht_out_rxpolarity7 : STD_LOGIC; + SIGNAL ht_out_serr_out : STD_LOGIC; + SIGNAL ht_out_swdn_wake : STD_LOGIC; + SIGNAL ht_out_swup_hotrst : STD_LOGIC; + SIGNAL ht_out_test_out_hip : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL ht_out_tl_app_inta_ack : STD_LOGIC; + SIGNAL ht_out_tl_app_msi_ack : STD_LOGIC; + SIGNAL ht_out_tl_cfg_add : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_tl_cfg_ctl : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL ht_out_tl_cfg_ctl_wr : STD_LOGIC; + SIGNAL ht_out_tl_cfg_sts : STD_LOGIC_VECTOR(52 DOWNTO 0); + SIGNAL ht_out_tl_cfg_sts_wr : STD_LOGIC; + SIGNAL ht_out_tl_pme_to_sr : STD_LOGIC; + SIGNAL ht_out_tx_cred_vc0 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL ht_out_tx_cred_vc1 : STD_LOGIC_VECTOR(35 DOWNTO 0); + SIGNAL ht_out_tx_deemph0 : STD_LOGIC; + SIGNAL ht_out_tx_deemph1 : STD_LOGIC; + SIGNAL ht_out_tx_deemph2 : STD_LOGIC; + SIGNAL ht_out_tx_deemph3 : STD_LOGIC; + SIGNAL ht_out_tx_deemph4 : STD_LOGIC; + SIGNAL ht_out_tx_deemph5 : STD_LOGIC; + SIGNAL ht_out_tx_deemph6 : STD_LOGIC; + SIGNAL ht_out_tx_deemph7 : STD_LOGIC; + SIGNAL ht_out_tx_fifo_empty_vc0 : STD_LOGIC; + SIGNAL ht_out_tx_fifo_empty_vc1 : STD_LOGIC; + SIGNAL ht_out_tx_fifo_full_vc0 : STD_LOGIC; + SIGNAL ht_out_tx_fifo_full_vc1 : STD_LOGIC; + SIGNAL ht_out_tx_fifo_rdp_vc0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_tx_fifo_rdp_vc1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_tx_fifo_wrp_vc0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_tx_fifo_wrp_vc1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ht_out_tx_margin0 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_margin1 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_margin2 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_margin3 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_margin4 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_margin5 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_margin6 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_margin7 : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL ht_out_tx_ready_vc0 : STD_LOGIC; + SIGNAL ht_out_tx_ready_vc1 : STD_LOGIC; + SIGNAL ht_out_txcompl0 : STD_LOGIC; + SIGNAL ht_out_txcompl1 : STD_LOGIC; + SIGNAL ht_out_txcompl2 : STD_LOGIC; + SIGNAL ht_out_txcompl3 : STD_LOGIC; + SIGNAL ht_out_txcompl4 : STD_LOGIC; + SIGNAL ht_out_txcompl5 : STD_LOGIC; + SIGNAL ht_out_txcompl6 : STD_LOGIC; + SIGNAL ht_out_txcompl7 : STD_LOGIC; + SIGNAL ht_out_txdata0 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdata1 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdata2 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdata3 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdata4 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdata5 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdata6 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdata7 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ht_out_txdatak0 : STD_LOGIC; + SIGNAL ht_out_txdatak1 : STD_LOGIC; + SIGNAL ht_out_txdatak2 : STD_LOGIC; + SIGNAL ht_out_txdatak3 : STD_LOGIC; + SIGNAL ht_out_txdatak4 : STD_LOGIC; + SIGNAL ht_out_txdatak5 : STD_LOGIC; + SIGNAL ht_out_txdatak6 : STD_LOGIC; + SIGNAL ht_out_txdatak7 : STD_LOGIC; + SIGNAL ht_out_txdetectrx0 : STD_LOGIC; + SIGNAL ht_out_txdetectrx1 : STD_LOGIC; + SIGNAL ht_out_txdetectrx2 : STD_LOGIC; + SIGNAL ht_out_txdetectrx3 : STD_LOGIC; + SIGNAL ht_out_txdetectrx4 : STD_LOGIC; + SIGNAL ht_out_txdetectrx5 : STD_LOGIC; + SIGNAL ht_out_txdetectrx6 : STD_LOGIC; + SIGNAL ht_out_txdetectrx7 : STD_LOGIC; + SIGNAL ht_out_txelecidle0 : STD_LOGIC; + SIGNAL ht_out_txelecidle1 : STD_LOGIC; + SIGNAL ht_out_txelecidle2 : STD_LOGIC; + SIGNAL ht_out_txelecidle3 : STD_LOGIC; + SIGNAL ht_out_txelecidle4 : STD_LOGIC; + SIGNAL ht_out_txelecidle5 : STD_LOGIC; + SIGNAL ht_out_txelecidle6 : STD_LOGIC; + SIGNAL ht_out_txelecidle7 : STD_LOGIC; + SIGNAL ht_out_wake_oen : STD_LOGIC; +BEGIN + + ------------------------ + -- Functionality Section -- + ------------------------ + + --/////////////////////////////////////////////////////////////////////////// + -- primary wys output -----------------------------------------------------// + -- now part of Vital assignment -------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + bistdonearcv0 <= bistdonearcv0_tmp; + bistdonearcv1 <= bistdonearcv1_tmp; + bistdonearpl <= bistdonearpl_tmp; + bistdonebrcv0 <= bistdonebrcv0_tmp; + bistdonebrcv1 <= bistdonebrcv1_tmp; + bistdonebrpl <= bistdonebrpl_tmp; + bistpassrcv0 <= bistpassrcv0_tmp; + bistpassrcv1 <= bistpassrcv1_tmp; + bistpassrpl <= bistpassrpl_tmp; + bistscanoutrcv0 <= bistscanoutrcv0_tmp; + bistscanoutrcv1 <= bistscanoutrcv1_tmp; + bistscanoutrpl <= bistscanoutrpl_tmp; + -- clrrxpath <= clrrxpath_tmp; + coreclkout <= coreclkout_tmp; + -- dataenablen <= dataenablen_tmp; + derrcorextrcv0 <= derrcorextrcv0_tmp; + derrcorextrcv1 <= derrcorextrcv1_tmp; + derrcorextrpl <= derrcorextrpl_tmp; + derrrpl <= derrrpl_tmp; + -- dlackphypm <= dlackphypm_tmp; + -- dlackrequpfc <= dlackrequpfc_tmp; + -- dlacksndupfc <= dlacksndupfc_tmp; + -- dlcurrentdeemp <= dlcurrentdeemp_tmp; + -- dlcurrentspeed <= dlcurrentspeed_tmp; + -- dldllreq <= dldllreq_tmp; + -- dlerrdll <= dlerrdll_tmp; + -- dlerrphy <= dlerrphy_tmp; + -- dllinkautobdwstatus <= dllinkautobdwstatus_tmp; + -- dllinkbdwmngstatus <= dllinkbdwmngstatus_tmp; + -- dlltssm <= dlltssm_tmp; + -- dlrpbufemp <= dlrpbufemp_tmp; + -- dlrstentercompbit <= dlrstentercompbit_tmp; + -- dlrsttxmarginfield <= dlrsttxmarginfield_tmp; + -- dlrxtyppm <= dlrxtyppm_tmp; + -- dlrxvalpm <= dlrxvalpm_tmp; + -- dltxackpm <= dltxackpm_tmp; + -- dlup <= dlup_tmp; + -- dlupexit <= dlupexit_tmp; + -- dlvcstatus <= dlvcstatus_tmp; + -- dprioout <= dprioout_tmp; + -- dpriostate <= dpriostate_tmp; + eidleinfersel <= eidleinfersel_tmp; + -- ev128ns <= ev128ns_tmp; + -- ev1us <= ev1us_tmp; + -- extraclkout <= extraclkout_tmp; + extraout <= extraout_tmp; + gen2rate <= gen2rate_tmp; + gen2rategnd <= gen2rategnd_tmp; + -- hotrstexit <= hotrstexit_tmp; + -- intstatus <= intstatus_tmp; + -- l2exit <= l2exit_tmp; + -- laneact <= laneact_tmp; + -- linkup <= linkup_tmp; + -- lmiack <= lmiack_tmp; + -- lmidout <= lmidout_tmp; + ltssml0state <= ltssml0state_tmp; + mramregscanout <= mramregscanout_tmp; + powerdown <= powerdown_tmp; + -- resetstatus <= resetstatus_tmp; + -- rxbardecvc0 <= rxbardecvc0_tmp; + -- rxbardecvc1 <= rxbardecvc1_tmp; + -- rxbevc00 <= rxbevc00_tmp; + -- rxbevc01 <= rxbevc01_tmp; + -- rxbevc10 <= rxbevc10_tmp; + -- rxbevc11 <= rxbevc11_tmp; + -- rxdatavc00 <= rxdatavc00_tmp; + -- rxdatavc01 <= rxdatavc01_tmp; + -- rxdatavc10 <= rxdatavc10_tmp; + -- rxdatavc11 <= rxdatavc11_tmp; + -- rxeopvc00 <= rxeopvc00_tmp; + -- rxeopvc01 <= rxeopvc01_tmp; + -- rxeopvc10 <= rxeopvc10_tmp; + -- rxeopvc11 <= rxeopvc11_tmp; + -- rxerrvc0 <= rxerrvc0_tmp; + -- rxerrvc1 <= rxerrvc1_tmp; + -- rxfifoemptyvc0 <= rxfifoemptyvc0_tmp; + -- rxfifoemptyvc1 <= rxfifoemptyvc1_tmp; + -- rxfifofullvc0 <= rxfifofullvc0_tmp; + -- rxfifofullvc1 <= rxfifofullvc1_tmp; + rxfifordpvc0 <= rxfifordpvc0_tmp; + rxfifordpvc1 <= rxfifordpvc1_tmp; + rxfifowrpvc0 <= rxfifowrpvc0_tmp; + rxfifowrpvc1 <= rxfifowrpvc1_tmp; + rxpolarity <= rxpolarity_tmp; + -- rxsopvc00 <= rxsopvc00_tmp; + -- rxsopvc01 <= rxsopvc01_tmp; + -- rxsopvc10 <= rxsopvc10_tmp; + -- rxsopvc11 <= rxsopvc11_tmp; + -- rxvalidvc0 <= rxvalidvc0_tmp; + -- rxvalidvc1 <= rxvalidvc1_tmp; + -- r2cerr0ext <= r2cerr0ext_tmp; + -- serrout <= serrout_tmp; + -- successspeednegoint <= successspeednegoint_tmp; + -- swdnwake <= swdnwake_tmp; + -- swuphotrst <= swuphotrst_tmp; + testout <= testout_tmp; + -- tlappintaack <= tlappintaack_tmp; + -- tlappmsiack <= tlappmsiack_tmp; + tlcfgadd <= tlcfgadd_tmp; + tlcfgctl <= tlcfgctl_tmp; + tlcfgctlwr <= tlcfgctlwr_tmp; + tlcfgsts <= tlcfgsts_tmp; + tlcfgstswr <= tlcfgstswr_tmp; + -- tlpmetosr <= tlpmetosr_tmp; + txcompl <= txcompl_tmp; + -- txcredvc0 <= txcredvc0_tmp; + -- txcredvc1 <= txcredvc1_tmp; + txdata <= txdata_tmp; + txdatak <= txdatak_tmp; + txdeemph <= txdeemph_tmp; + txdetectrx <= txdetectrx_tmp; + txelecidle <= txelecidle_tmp; + -- txfifoemptyvc0 <= txfifoemptyvc0_tmp; + -- txfifoemptyvc1 <= txfifoemptyvc1_tmp; + -- txfifofullvc0 <= txfifofullvc0_tmp; + -- txfifofullvc1 <= txfifofullvc1_tmp; + -- txfifordpvc0 <= txfifordpvc0_tmp; + -- txfifordpvc1 <= txfifordpvc1_tmp; + -- txfifowrpvc0 <= txfifowrpvc0_tmp; + -- txfifowrpvc1 <= txfifowrpvc1_tmp; + txmargin <= txmargin_tmp; + -- txreadyvc0 <= txreadyvc0_tmp; + -- txreadyvc1 <= txreadyvc1_tmp; + wakeoen <= wakeoen_tmp; + + --/////////////////////////////////////////////////////////////////////////// + -- WYS input filtering ------------- ------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + bistenrcv0_in <= '1' WHEN (bistenrcv0 = '1') ELSE + '0'; + bistenrcv1_in <= '1' WHEN (bistenrcv1 = '1') ELSE + '0'; + bistenrpl_in <= '1' WHEN (bistenrpl = '1') ELSE + '0'; + bistscanen_in <= '1' WHEN (bistscanen = '1') ELSE + '0'; + bistscanin_in <= '1' WHEN (bistscanin = '1') ELSE + '0'; + bisttesten_in <= '1' WHEN (bisttesten = '1') ELSE + '0'; + coreclkin_in <= '1' WHEN (coreclkin = '1') ELSE + '0'; + corecrst_in <= '1' WHEN (corecrst = '1') ELSE + '0'; + corepor_in <= '1' WHEN (corepor = '1') ELSE + '0'; + corerst_in <= '1' WHEN (corerst = '1') ELSE + '0'; + coresrst_in <= '1' WHEN (coresrst = '1') ELSE + '0'; + + cplerr_in(0) <= '1' WHEN (cplerr(0) = '1') ELSE + '0'; + cplerr_in(1) <= '1' WHEN (cplerr(1) = '1') ELSE + '0'; + cplerr_in(2) <= '1' WHEN (cplerr(2) = '1') ELSE + '0'; + cplerr_in(3) <= '1' WHEN (cplerr(3) = '1') ELSE + '0'; + cplerr_in(4) <= '1' WHEN (cplerr(4) = '1') ELSE + '0'; + cplerr_in(5) <= '1' WHEN (cplerr(5) = '1') ELSE + '0'; + cplerr_in(6) <= '1' WHEN (cplerr(6) = '1') ELSE + '0'; + + cplpending_in <= '1' WHEN (cplpending = '1') ELSE + '0'; + + dbgpipex1rx_in(0) <= '1' WHEN (dbgpipex1rx(0) = '1') ELSE + '0'; + dbgpipex1rx_in(1) <= '1' WHEN (dbgpipex1rx(1) = '1') ELSE + '0'; + dbgpipex1rx_in(2) <= '1' WHEN (dbgpipex1rx(2) = '1') ELSE + '0'; + dbgpipex1rx_in(3) <= '1' WHEN (dbgpipex1rx(3) = '1') ELSE + '0'; + dbgpipex1rx_in(4) <= '1' WHEN (dbgpipex1rx(4) = '1') ELSE + '0'; + dbgpipex1rx_in(5) <= '1' WHEN (dbgpipex1rx(5) = '1') ELSE + '0'; + dbgpipex1rx_in(6) <= '1' WHEN (dbgpipex1rx(6) = '1') ELSE + '0'; + dbgpipex1rx_in(7) <= '1' WHEN (dbgpipex1rx(7) = '1') ELSE + '0'; + dbgpipex1rx_in(8) <= '1' WHEN (dbgpipex1rx(8) = '1') ELSE + '0'; + dbgpipex1rx_in(9) <= '1' WHEN (dbgpipex1rx(9) = '1') ELSE + '0'; + dbgpipex1rx_in(10) <= '1' WHEN (dbgpipex1rx(10) = '1') ELSE + '0'; + dbgpipex1rx_in(11) <= '1' WHEN (dbgpipex1rx(11) = '1') ELSE + '0'; + dbgpipex1rx_in(12) <= '1' WHEN (dbgpipex1rx(12) = '1') ELSE + '0'; + dbgpipex1rx_in(13) <= '1' WHEN (dbgpipex1rx(13) = '1') ELSE + '0'; + dbgpipex1rx_in(14) <= '1' WHEN (dbgpipex1rx(14) = '1') ELSE + '0'; + + dlaspmcr0_in <= '1' WHEN (dlaspmcr0 = '1') ELSE + '0'; + dlcomclkreg_in <= '1' WHEN (dlcomclkreg = '1') ELSE + '0'; + + dlctrllink2_in(0) <= '1' WHEN (dlctrllink2(0) = '1') ELSE + '0'; + dlctrllink2_in(1) <= '1' WHEN (dlctrllink2(1) = '1') ELSE + '0'; + dlctrllink2_in(2) <= '1' WHEN (dlctrllink2(2) = '1') ELSE + '0'; + dlctrllink2_in(3) <= '1' WHEN (dlctrllink2(3) = '1') ELSE + '0'; + dlctrllink2_in(4) <= '1' WHEN (dlctrllink2(4) = '1') ELSE + '0'; + dlctrllink2_in(5) <= '1' WHEN (dlctrllink2(5) = '1') ELSE + '0'; + dlctrllink2_in(6) <= '1' WHEN (dlctrllink2(6) = '1') ELSE + '0'; + dlctrllink2_in(7) <= '1' WHEN (dlctrllink2(7) = '1') ELSE + '0'; + dlctrllink2_in(8) <= '1' WHEN (dlctrllink2(8) = '1') ELSE + '0'; + dlctrllink2_in(9) <= '1' WHEN (dlctrllink2(9) = '1') ELSE + '0'; + dlctrllink2_in(10) <= '1' WHEN (dlctrllink2(10) = '1') ELSE + '0'; + dlctrllink2_in(11) <= '1' WHEN (dlctrllink2(11) = '1') ELSE + '0'; + dlctrllink2_in(12) <= '1' WHEN (dlctrllink2(12) = '1') ELSE + '0'; + + dldataupfc_in(0) <= '1' WHEN (dldataupfc(0) = '1') ELSE + '0'; + dldataupfc_in(1) <= '1' WHEN (dldataupfc(1) = '1') ELSE + '0'; + dldataupfc_in(2) <= '1' WHEN (dldataupfc(2) = '1') ELSE + '0'; + dldataupfc_in(3) <= '1' WHEN (dldataupfc(3) = '1') ELSE + '0'; + dldataupfc_in(4) <= '1' WHEN (dldataupfc(4) = '1') ELSE + '0'; + dldataupfc_in(5) <= '1' WHEN (dldataupfc(5) = '1') ELSE + '0'; + dldataupfc_in(6) <= '1' WHEN (dldataupfc(6) = '1') ELSE + '0'; + dldataupfc_in(7) <= '1' WHEN (dldataupfc(7) = '1') ELSE + '0'; + dldataupfc_in(8) <= '1' WHEN (dldataupfc(8) = '1') ELSE + '0'; + dldataupfc_in(9) <= '1' WHEN (dldataupfc(9) = '1') ELSE + '0'; + dldataupfc_in(10) <= '1' WHEN (dldataupfc(10) = '1') ELSE + '0'; + dldataupfc_in(11) <= '1' WHEN (dldataupfc(11) = '1') ELSE + '0'; + + dlhdrupfc_in(0) <= '1' WHEN (dlhdrupfc(0) = '1') ELSE + '0'; + dlhdrupfc_in(1) <= '1' WHEN (dlhdrupfc(1) = '1') ELSE + '0'; + dlhdrupfc_in(2) <= '1' WHEN (dlhdrupfc(2) = '1') ELSE + '0'; + dlhdrupfc_in(3) <= '1' WHEN (dlhdrupfc(3) = '1') ELSE + '0'; + dlhdrupfc_in(4) <= '1' WHEN (dlhdrupfc(4) = '1') ELSE + '0'; + dlhdrupfc_in(5) <= '1' WHEN (dlhdrupfc(5) = '1') ELSE + '0'; + dlhdrupfc_in(6) <= '1' WHEN (dlhdrupfc(6) = '1') ELSE + '0'; + dlhdrupfc_in(7) <= '1' WHEN (dlhdrupfc(7) = '1') ELSE + '0'; + + dlinhdllp_in <= '0' WHEN (dlinhdllp = '0') ELSE -- inverted + '1'; + + dlmaxploaddcr_in(0) <= '1' WHEN (dlmaxploaddcr(0) = '1') ELSE + '0'; + dlmaxploaddcr_in(1) <= '1' WHEN (dlmaxploaddcr(1) = '1') ELSE + '0'; + dlmaxploaddcr_in(2) <= '1' WHEN (dlmaxploaddcr(2) = '1') ELSE + '0'; + + dlreqphycfg_in(0) <= '1' WHEN (dlreqphycfg(0) = '1') ELSE + '0'; + dlreqphycfg_in(1) <= '1' WHEN (dlreqphycfg(1) = '1') ELSE + '0'; + dlreqphycfg_in(2) <= '1' WHEN (dlreqphycfg(2) = '1') ELSE + '0'; + dlreqphycfg_in(3) <= '1' WHEN (dlreqphycfg(3) = '1') ELSE + '0'; + + dlreqphypm_in(0) <= '1' WHEN (dlreqphypm(0) = '1') ELSE + '0'; + dlreqphypm_in(1) <= '1' WHEN (dlreqphypm(1) = '1') ELSE + '0'; + dlreqphypm_in(2) <= '1' WHEN (dlreqphypm(2) = '1') ELSE + '0'; + dlreqphypm_in(3) <= '1' WHEN (dlreqphypm(3) = '1') ELSE + '0'; + + dlrequpfc_in <= '1' WHEN (dlrequpfc = '1') ELSE + '0'; + dlreqwake_in <= '1' WHEN (dlreqwake = '1') ELSE + '0'; + dlrxecrcchk_in <= '1' WHEN (dlrxecrcchk = '1') ELSE + '0'; + dlsndupfc_in <= '1' WHEN (dlsndupfc = '1') ELSE + '0'; + dltxcfgextsy_in <= '1' WHEN (dltxcfgextsy = '1') ELSE + '0'; + dltxreqpm_in <= '1' WHEN (dltxreqpm = '1') ELSE + '0'; + + dltxtyppm_in(0) <= '1' WHEN (dltxtyppm(0) = '1') ELSE + '0'; + dltxtyppm_in(1) <= '1' WHEN (dltxtyppm(1) = '1') ELSE + '0'; + dltxtyppm_in(2) <= '1' WHEN (dltxtyppm(2) = '1') ELSE + '0'; + + dltypupfc_in(0) <= '1' WHEN (dltypupfc(0) = '1') ELSE + '0'; + dltypupfc_in(1) <= '1' WHEN (dltypupfc(1) = '1') ELSE + '0'; + + dlvcctrl_in(0) <= '1' WHEN (dlvcctrl(0) = '1') ELSE + '0'; + dlvcctrl_in(1) <= '1' WHEN (dlvcctrl(1) = '1') ELSE + '0'; + dlvcctrl_in(2) <= '1' WHEN (dlvcctrl(2) = '1') ELSE + '0'; + dlvcctrl_in(3) <= '1' WHEN (dlvcctrl(3) = '1') ELSE + '0'; + dlvcctrl_in(4) <= '1' WHEN (dlvcctrl(4) = '1') ELSE + '0'; + dlvcctrl_in(5) <= '1' WHEN (dlvcctrl(5) = '1') ELSE + '0'; + dlvcctrl_in(6) <= '1' WHEN (dlvcctrl(6) = '1') ELSE + '0'; + dlvcctrl_in(7) <= '1' WHEN (dlvcctrl(7) = '1') ELSE + '0'; + + dlvcidmap_in(0) <= '1' WHEN (dlvcidmap(0) = '1') ELSE + '0'; + dlvcidmap_in(1) <= '1' WHEN (dlvcidmap(1) = '1') ELSE + '0'; + dlvcidmap_in(2) <= '1' WHEN (dlvcidmap(2) = '1') ELSE + '0'; + dlvcidmap_in(3) <= '1' WHEN (dlvcidmap(3) = '1') ELSE + '0'; + dlvcidmap_in(4) <= '1' WHEN (dlvcidmap(4) = '1') ELSE + '0'; + dlvcidmap_in(5) <= '1' WHEN (dlvcidmap(5) = '1') ELSE + '0'; + dlvcidmap_in(6) <= '1' WHEN (dlvcidmap(6) = '1') ELSE + '0'; + dlvcidmap_in(7) <= '1' WHEN (dlvcidmap(7) = '1') ELSE + '0'; + dlvcidmap_in(8) <= '1' WHEN (dlvcidmap(8) = '1') ELSE + '0'; + dlvcidmap_in(9) <= '1' WHEN (dlvcidmap(9) = '1') ELSE + '0'; + dlvcidmap_in(10) <= '1' WHEN (dlvcidmap(10) = '1') ELSE + '0'; + dlvcidmap_in(11) <= '1' WHEN (dlvcidmap(11) = '1') ELSE + '0'; + dlvcidmap_in(12) <= '1' WHEN (dlvcidmap(12) = '1') ELSE + '0'; + dlvcidmap_in(13) <= '1' WHEN (dlvcidmap(13) = '1') ELSE + '0'; + dlvcidmap_in(14) <= '1' WHEN (dlvcidmap(14) = '1') ELSE + '0'; + dlvcidmap_in(15) <= '1' WHEN (dlvcidmap(15) = '1') ELSE + '0'; + dlvcidmap_in(16) <= '1' WHEN (dlvcidmap(16) = '1') ELSE + '0'; + dlvcidmap_in(17) <= '1' WHEN (dlvcidmap(17) = '1') ELSE + '0'; + dlvcidmap_in(18) <= '1' WHEN (dlvcidmap(18) = '1') ELSE + '0'; + dlvcidmap_in(19) <= '1' WHEN (dlvcidmap(19) = '1') ELSE + '0'; + dlvcidmap_in(20) <= '1' WHEN (dlvcidmap(20) = '1') ELSE + '0'; + dlvcidmap_in(21) <= '1' WHEN (dlvcidmap(21) = '1') ELSE + '0'; + dlvcidmap_in(22) <= '1' WHEN (dlvcidmap(22) = '1') ELSE + '0'; + dlvcidmap_in(23) <= '1' WHEN (dlvcidmap(23) = '1') ELSE + '0'; + + dlvcidupfc_in(0) <= '1' WHEN (dlvcidupfc(0) = '1') ELSE + '0'; + dlvcidupfc_in(1) <= '1' WHEN (dlvcidupfc(1) = '1') ELSE + '0'; + dlvcidupfc_in(2) <= '1' WHEN (dlvcidupfc(2) = '1') ELSE + '0'; + + dpclk_in <= '1' WHEN (dpclk = '1') ELSE + '0'; + dpriodisable_in <= '0' WHEN (dpriodisable = '0') ELSE -- inverted + '1'; + dprioin_in <= '1' WHEN (dprioin = '1') ELSE + '0'; + dprioload_in <= '1' WHEN (dprioload = '1') ELSE + '0'; + + extrain_in(0) <= '1' WHEN (extrain(0) = '1') ELSE + '0'; + extrain_in(1) <= '1' WHEN (extrain(1) = '1') ELSE + '0'; + extrain_in(2) <= '1' WHEN (extrain(2) = '1') ELSE + '0'; + extrain_in(3) <= '1' WHEN (extrain(3) = '1') ELSE + '0'; + extrain_in(4) <= '1' WHEN (extrain(4) = '1') ELSE + '0'; + extrain_in(5) <= '1' WHEN (extrain(5) = '1') ELSE + '0'; + extrain_in(6) <= '1' WHEN (extrain(6) = '1') ELSE + '0'; + extrain_in(7) <= '1' WHEN (extrain(7) = '1') ELSE + '0'; + extrain_in(8) <= '1' WHEN (extrain(8) = '1') ELSE + '0'; + extrain_in(9) <= '1' WHEN (extrain(9) = '1') ELSE + '0'; + extrain_in(10) <= '1' WHEN (extrain(10) = '1') ELSE + '0'; + extrain_in(11) <= '1' WHEN (extrain(11) = '1') ELSE + '0'; + + lmiaddr_in(0) <= '1' WHEN (lmiaddr(0) = '1') ELSE + '0'; + lmiaddr_in(1) <= '1' WHEN (lmiaddr(1) = '1') ELSE + '0'; + lmiaddr_in(2) <= '1' WHEN (lmiaddr(2) = '1') ELSE + '0'; + lmiaddr_in(3) <= '1' WHEN (lmiaddr(3) = '1') ELSE + '0'; + lmiaddr_in(4) <= '1' WHEN (lmiaddr(4) = '1') ELSE + '0'; + lmiaddr_in(5) <= '1' WHEN (lmiaddr(5) = '1') ELSE + '0'; + lmiaddr_in(6) <= '1' WHEN (lmiaddr(6) = '1') ELSE + '0'; + lmiaddr_in(7) <= '1' WHEN (lmiaddr(7) = '1') ELSE + '0'; + lmiaddr_in(8) <= '1' WHEN (lmiaddr(8) = '1') ELSE + '0'; + lmiaddr_in(9) <= '1' WHEN (lmiaddr(9) = '1') ELSE + '0'; + lmiaddr_in(10) <= '1' WHEN (lmiaddr(10) = '1') ELSE + '0'; + lmiaddr_in(11) <= '1' WHEN (lmiaddr(11) = '1') ELSE + '0'; + + lmidin_in(0) <= '1' WHEN (lmidin(0) = '1') ELSE + '0'; + lmidin_in(1) <= '1' WHEN (lmidin(1) = '1') ELSE + '0'; + lmidin_in(2) <= '1' WHEN (lmidin(2) = '1') ELSE + '0'; + lmidin_in(3) <= '1' WHEN (lmidin(3) = '1') ELSE + '0'; + lmidin_in(4) <= '1' WHEN (lmidin(4) = '1') ELSE + '0'; + lmidin_in(5) <= '1' WHEN (lmidin(5) = '1') ELSE + '0'; + lmidin_in(6) <= '1' WHEN (lmidin(6) = '1') ELSE + '0'; + lmidin_in(7) <= '1' WHEN (lmidin(7) = '1') ELSE + '0'; + lmidin_in(8) <= '1' WHEN (lmidin(8) = '1') ELSE + '0'; + lmidin_in(9) <= '1' WHEN (lmidin(9) = '1') ELSE + '0'; + lmidin_in(10) <= '1' WHEN (lmidin(10) = '1') ELSE + '0'; + lmidin_in(11) <= '1' WHEN (lmidin(11) = '1') ELSE + '0'; + lmidin_in(12) <= '1' WHEN (lmidin(12) = '1') ELSE + '0'; + lmidin_in(13) <= '1' WHEN (lmidin(13) = '1') ELSE + '0'; + lmidin_in(14) <= '1' WHEN (lmidin(14) = '1') ELSE + '0'; + lmidin_in(15) <= '1' WHEN (lmidin(15) = '1') ELSE + '0'; + lmidin_in(16) <= '1' WHEN (lmidin(16) = '1') ELSE + '0'; + lmidin_in(17) <= '1' WHEN (lmidin(17) = '1') ELSE + '0'; + lmidin_in(18) <= '1' WHEN (lmidin(18) = '1') ELSE + '0'; + lmidin_in(19) <= '1' WHEN (lmidin(19) = '1') ELSE + '0'; + lmidin_in(20) <= '1' WHEN (lmidin(20) = '1') ELSE + '0'; + lmidin_in(21) <= '1' WHEN (lmidin(21) = '1') ELSE + '0'; + lmidin_in(22) <= '1' WHEN (lmidin(22) = '1') ELSE + '0'; + lmidin_in(23) <= '1' WHEN (lmidin(23) = '1') ELSE + '0'; + lmidin_in(24) <= '1' WHEN (lmidin(24) = '1') ELSE + '0'; + lmidin_in(25) <= '1' WHEN (lmidin(25) = '1') ELSE + '0'; + lmidin_in(26) <= '1' WHEN (lmidin(26) = '1') ELSE + '0'; + lmidin_in(27) <= '1' WHEN (lmidin(27) = '1') ELSE + '0'; + lmidin_in(28) <= '1' WHEN (lmidin(28) = '1') ELSE + '0'; + lmidin_in(29) <= '1' WHEN (lmidin(29) = '1') ELSE + '0'; + lmidin_in(30) <= '1' WHEN (lmidin(30) = '1') ELSE + '0'; + lmidin_in(31) <= '1' WHEN (lmidin(31) = '1') ELSE + '0'; + + lmirden_in <= '1' WHEN (lmirden = '1') ELSE + '0'; + lmiwren_in <= '1' WHEN (lmiwren = '1') ELSE + '0'; + + mode_in(0) <= '1' WHEN (mode(0) = '1') ELSE + '0'; + mode_in(1) <= '1' WHEN (mode(1) = '1') ELSE + '0'; + + mramhiptestenable_in <= '1' WHEN (mramhiptestenable = '1') ELSE + '0'; + mramregscanen_in <= '1' WHEN (mramregscanen = '1') ELSE + '0'; + mramregscanin_in <= '1' WHEN (mramregscanin = '1') ELSE + '0'; + pclkcentral_in <= '1' WHEN (pclkcentral = '1') ELSE + '0'; + pclkch0_in <= '1' WHEN (pclkch0 = '1') ELSE + '0'; + phyrst_in <= '1' WHEN (phyrst = '1') ELSE + '0'; + physrst_in <= '1' WHEN (physrst = '1') ELSE + '0'; + + phystatus_in(0) <= '1' WHEN (phystatus(0) = '1') ELSE + '0'; + phystatus_in(1) <= '1' WHEN (phystatus(1) = '1') ELSE + '0'; + phystatus_in(2) <= '1' WHEN (phystatus(2) = '1') ELSE + '0'; + phystatus_in(3) <= '1' WHEN (phystatus(3) = '1') ELSE + '0'; + phystatus_in(4) <= '1' WHEN (phystatus(4) = '1') ELSE + '0'; + phystatus_in(5) <= '1' WHEN (phystatus(5) = '1') ELSE + '0'; + phystatus_in(6) <= '1' WHEN (phystatus(6) = '1') ELSE + '0'; + phystatus_in(7) <= '1' WHEN (phystatus(7) = '1') ELSE + '0'; + + pldclk_in <= '1' WHEN (pldclk = '1') ELSE + '0'; + pldrst_in <= '1' WHEN (pldrst = '1') ELSE + '0'; + pldsrst_in <= '1' WHEN (pldsrst = '1') ELSE + '0'; + pllfixedclk_in <= '1' WHEN (pllfixedclk = '1') ELSE + '0'; + + rxdata_in(0) <= '1' WHEN (rxdata(0) = '1') ELSE + '0'; + rxdata_in(1) <= '1' WHEN (rxdata(1) = '1') ELSE + '0'; + rxdata_in(2) <= '1' WHEN (rxdata(2) = '1') ELSE + '0'; + rxdata_in(3) <= '1' WHEN (rxdata(3) = '1') ELSE + '0'; + rxdata_in(4) <= '1' WHEN (rxdata(4) = '1') ELSE + '0'; + rxdata_in(5) <= '1' WHEN (rxdata(5) = '1') ELSE + '0'; + rxdata_in(6) <= '1' WHEN (rxdata(6) = '1') ELSE + '0'; + rxdata_in(7) <= '1' WHEN (rxdata(7) = '1') ELSE + '0'; + rxdata_in(8) <= '1' WHEN (rxdata(8) = '1') ELSE + '0'; + rxdata_in(9) <= '1' WHEN (rxdata(9) = '1') ELSE + '0'; + rxdata_in(10) <= '1' WHEN (rxdata(10) = '1') ELSE + '0'; + rxdata_in(11) <= '1' WHEN (rxdata(11) = '1') ELSE + '0'; + rxdata_in(12) <= '1' WHEN (rxdata(12) = '1') ELSE + '0'; + rxdata_in(13) <= '1' WHEN (rxdata(13) = '1') ELSE + '0'; + rxdata_in(14) <= '1' WHEN (rxdata(14) = '1') ELSE + '0'; + rxdata_in(15) <= '1' WHEN (rxdata(15) = '1') ELSE + '0'; + rxdata_in(16) <= '1' WHEN (rxdata(16) = '1') ELSE + '0'; + rxdata_in(17) <= '1' WHEN (rxdata(17) = '1') ELSE + '0'; + rxdata_in(18) <= '1' WHEN (rxdata(18) = '1') ELSE + '0'; + rxdata_in(19) <= '1' WHEN (rxdata(19) = '1') ELSE + '0'; + rxdata_in(20) <= '1' WHEN (rxdata(20) = '1') ELSE + '0'; + rxdata_in(21) <= '1' WHEN (rxdata(21) = '1') ELSE + '0'; + rxdata_in(22) <= '1' WHEN (rxdata(22) = '1') ELSE + '0'; + rxdata_in(23) <= '1' WHEN (rxdata(23) = '1') ELSE + '0'; + rxdata_in(24) <= '1' WHEN (rxdata(24) = '1') ELSE + '0'; + rxdata_in(25) <= '1' WHEN (rxdata(25) = '1') ELSE + '0'; + rxdata_in(26) <= '1' WHEN (rxdata(26) = '1') ELSE + '0'; + rxdata_in(27) <= '1' WHEN (rxdata(27) = '1') ELSE + '0'; + rxdata_in(28) <= '1' WHEN (rxdata(28) = '1') ELSE + '0'; + rxdata_in(29) <= '1' WHEN (rxdata(29) = '1') ELSE + '0'; + rxdata_in(30) <= '1' WHEN (rxdata(30) = '1') ELSE + '0'; + rxdata_in(31) <= '1' WHEN (rxdata(31) = '1') ELSE + '0'; + rxdata_in(32) <= '1' WHEN (rxdata(32) = '1') ELSE + '0'; + rxdata_in(33) <= '1' WHEN (rxdata(33) = '1') ELSE + '0'; + rxdata_in(34) <= '1' WHEN (rxdata(34) = '1') ELSE + '0'; + rxdata_in(35) <= '1' WHEN (rxdata(35) = '1') ELSE + '0'; + rxdata_in(36) <= '1' WHEN (rxdata(36) = '1') ELSE + '0'; + rxdata_in(37) <= '1' WHEN (rxdata(37) = '1') ELSE + '0'; + rxdata_in(38) <= '1' WHEN (rxdata(38) = '1') ELSE + '0'; + rxdata_in(39) <= '1' WHEN (rxdata(39) = '1') ELSE + '0'; + rxdata_in(40) <= '1' WHEN (rxdata(40) = '1') ELSE + '0'; + rxdata_in(41) <= '1' WHEN (rxdata(41) = '1') ELSE + '0'; + rxdata_in(42) <= '1' WHEN (rxdata(42) = '1') ELSE + '0'; + rxdata_in(43) <= '1' WHEN (rxdata(43) = '1') ELSE + '0'; + rxdata_in(44) <= '1' WHEN (rxdata(44) = '1') ELSE + '0'; + rxdata_in(45) <= '1' WHEN (rxdata(45) = '1') ELSE + '0'; + rxdata_in(46) <= '1' WHEN (rxdata(46) = '1') ELSE + '0'; + rxdata_in(47) <= '1' WHEN (rxdata(47) = '1') ELSE + '0'; + rxdata_in(48) <= '1' WHEN (rxdata(48) = '1') ELSE + '0'; + rxdata_in(49) <= '1' WHEN (rxdata(49) = '1') ELSE + '0'; + rxdata_in(50) <= '1' WHEN (rxdata(50) = '1') ELSE + '0'; + rxdata_in(51) <= '1' WHEN (rxdata(51) = '1') ELSE + '0'; + rxdata_in(52) <= '1' WHEN (rxdata(52) = '1') ELSE + '0'; + rxdata_in(53) <= '1' WHEN (rxdata(53) = '1') ELSE + '0'; + rxdata_in(54) <= '1' WHEN (rxdata(54) = '1') ELSE + '0'; + rxdata_in(55) <= '1' WHEN (rxdata(55) = '1') ELSE + '0'; + rxdata_in(56) <= '1' WHEN (rxdata(56) = '1') ELSE + '0'; + rxdata_in(57) <= '1' WHEN (rxdata(57) = '1') ELSE + '0'; + rxdata_in(58) <= '1' WHEN (rxdata(58) = '1') ELSE + '0'; + rxdata_in(59) <= '1' WHEN (rxdata(59) = '1') ELSE + '0'; + rxdata_in(60) <= '1' WHEN (rxdata(60) = '1') ELSE + '0'; + rxdata_in(61) <= '1' WHEN (rxdata(61) = '1') ELSE + '0'; + rxdata_in(62) <= '1' WHEN (rxdata(62) = '1') ELSE + '0'; + rxdata_in(63) <= '1' WHEN (rxdata(63) = '1') ELSE + '0'; + + rxdatak_in(0) <= '1' WHEN (rxdatak(0) = '1') ELSE + '0'; + rxdatak_in(1) <= '1' WHEN (rxdatak(1) = '1') ELSE + '0'; + rxdatak_in(2) <= '1' WHEN (rxdatak(2) = '1') ELSE + '0'; + rxdatak_in(3) <= '1' WHEN (rxdatak(3) = '1') ELSE + '0'; + rxdatak_in(4) <= '1' WHEN (rxdatak(4) = '1') ELSE + '0'; + rxdatak_in(5) <= '1' WHEN (rxdatak(5) = '1') ELSE + '0'; + rxdatak_in(6) <= '1' WHEN (rxdatak(6) = '1') ELSE + '0'; + rxdatak_in(7) <= '1' WHEN (rxdatak(7) = '1') ELSE + '0'; + + rxelecidle_in(0) <= '1' WHEN (rxelecidle(0) = '1') ELSE + '0'; + rxelecidle_in(1) <= '1' WHEN (rxelecidle(1) = '1') ELSE + '0'; + rxelecidle_in(2) <= '1' WHEN (rxelecidle(2) = '1') ELSE + '0'; + rxelecidle_in(3) <= '1' WHEN (rxelecidle(3) = '1') ELSE + '0'; + rxelecidle_in(4) <= '1' WHEN (rxelecidle(4) = '1') ELSE + '0'; + rxelecidle_in(5) <= '1' WHEN (rxelecidle(5) = '1') ELSE + '0'; + rxelecidle_in(6) <= '1' WHEN (rxelecidle(6) = '1') ELSE + '0'; + rxelecidle_in(7) <= '1' WHEN (rxelecidle(7) = '1') ELSE + '0'; + + rxmaskvc0_in <= '1' WHEN (rxmaskvc0 = '1') ELSE + '0'; + rxmaskvc1_in <= '1' WHEN (rxmaskvc1 = '1') ELSE + '0'; + rxreadyvc0_in <= '1' WHEN (rxreadyvc0 = '1') ELSE + '0'; + rxreadyvc1_in <= '1' WHEN (rxreadyvc1 = '1') ELSE + '0'; + + rxstatus_in(0) <= '1' WHEN (rxstatus(0) = '1') ELSE + '0'; + rxstatus_in(1) <= '1' WHEN (rxstatus(1) = '1') ELSE + '0'; + rxstatus_in(2) <= '1' WHEN (rxstatus(2) = '1') ELSE + '0'; + rxstatus_in(3) <= '1' WHEN (rxstatus(3) = '1') ELSE + '0'; + rxstatus_in(4) <= '1' WHEN (rxstatus(4) = '1') ELSE + '0'; + rxstatus_in(5) <= '1' WHEN (rxstatus(5) = '1') ELSE + '0'; + rxstatus_in(6) <= '1' WHEN (rxstatus(6) = '1') ELSE + '0'; + rxstatus_in(7) <= '1' WHEN (rxstatus(7) = '1') ELSE + '0'; + rxstatus_in(8) <= '1' WHEN (rxstatus(8) = '1') ELSE + '0'; + rxstatus_in(9) <= '1' WHEN (rxstatus(9) = '1') ELSE + '0'; + rxstatus_in(10) <= '1' WHEN (rxstatus(10) = '1') ELSE + '0'; + rxstatus_in(11) <= '1' WHEN (rxstatus(11) = '1') ELSE + '0'; + rxstatus_in(12) <= '1' WHEN (rxstatus(12) = '1') ELSE + '0'; + rxstatus_in(13) <= '1' WHEN (rxstatus(13) = '1') ELSE + '0'; + rxstatus_in(14) <= '1' WHEN (rxstatus(14) = '1') ELSE + '0'; + rxstatus_in(15) <= '1' WHEN (rxstatus(15) = '1') ELSE + '0'; + rxstatus_in(16) <= '1' WHEN (rxstatus(16) = '1') ELSE + '0'; + rxstatus_in(17) <= '1' WHEN (rxstatus(17) = '1') ELSE + '0'; + rxstatus_in(18) <= '1' WHEN (rxstatus(18) = '1') ELSE + '0'; + rxstatus_in(19) <= '1' WHEN (rxstatus(19) = '1') ELSE + '0'; + rxstatus_in(20) <= '1' WHEN (rxstatus(20) = '1') ELSE + '0'; + rxstatus_in(21) <= '1' WHEN (rxstatus(21) = '1') ELSE + '0'; + rxstatus_in(22) <= '1' WHEN (rxstatus(22) = '1') ELSE + '0'; + rxstatus_in(23) <= '1' WHEN (rxstatus(23) = '1') ELSE + '0'; + + rxvalid_in(0) <= '1' WHEN (rxvalid(0) = '1') ELSE + '0'; + rxvalid_in(1) <= '1' WHEN (rxvalid(1) = '1') ELSE + '0'; + rxvalid_in(2) <= '1' WHEN (rxvalid(2) = '1') ELSE + '0'; + rxvalid_in(3) <= '1' WHEN (rxvalid(3) = '1') ELSE + '0'; + rxvalid_in(4) <= '1' WHEN (rxvalid(4) = '1') ELSE + '0'; + rxvalid_in(5) <= '1' WHEN (rxvalid(5) = '1') ELSE + '0'; + rxvalid_in(6) <= '1' WHEN (rxvalid(6) = '1') ELSE + '0'; + rxvalid_in(7) <= '1' WHEN (rxvalid(7) = '1') ELSE + '0'; + + scanen_in <= '1' WHEN (scanen = '1') ELSE + '0'; + scanmoden_in <= '0' WHEN (scanmoden = '0') ELSE -- inverted + '1'; + + swdnin_in(0) <= '1' WHEN (swdnin(0) = '1') ELSE + '0'; + swdnin_in(1) <= '1' WHEN (swdnin(1) = '1') ELSE + '0'; + swdnin_in(2) <= '1' WHEN (swdnin(2) = '1') ELSE + '0'; + + swupin_in(0) <= '1' WHEN (swupin(0) = '1') ELSE + '0'; + swupin_in(1) <= '1' WHEN (swupin(1) = '1') ELSE + '0'; + swupin_in(2) <= '1' WHEN (swupin(2) = '1') ELSE + '0'; + swupin_in(3) <= '1' WHEN (swupin(3) = '1') ELSE + '0'; + swupin_in(4) <= '1' WHEN (swupin(4) = '1') ELSE + '0'; + swupin_in(5) <= '1' WHEN (swupin(5) = '1') ELSE + '0'; + swupin_in(6) <= '1' WHEN (swupin(6) = '1') ELSE + '0'; + + testin_in(0) <= '1' WHEN (testin(0) = '1') ELSE + '0'; + testin_in(1) <= '1' WHEN (testin(1) = '1') ELSE + '0'; + testin_in(2) <= '1' WHEN (testin(2) = '1') ELSE + '0'; + testin_in(3) <= '1' WHEN (testin(3) = '1') ELSE + '0'; + testin_in(4) <= '1' WHEN (testin(4) = '1') ELSE + '0'; + testin_in(5) <= '1' WHEN (testin(5) = '1') ELSE + '0'; + testin_in(6) <= '1' WHEN (testin(6) = '1') ELSE + '0'; + testin_in(7) <= '1' WHEN (testin(7) = '1') ELSE + '0'; + testin_in(8) <= '1' WHEN (testin(8) = '1') ELSE + '0'; + testin_in(9) <= '1' WHEN (testin(9) = '1') ELSE + '0'; + testin_in(10) <= '1' WHEN (testin(10) = '1') ELSE + '0'; + testin_in(11) <= '1' WHEN (testin(11) = '1') ELSE + '0'; + testin_in(12) <= '1' WHEN (testin(12) = '1') ELSE + '0'; + testin_in(13) <= '1' WHEN (testin(13) = '1') ELSE + '0'; + testin_in(14) <= '1' WHEN (testin(14) = '1') ELSE + '0'; + testin_in(15) <= '1' WHEN (testin(15) = '1') ELSE + '0'; + testin_in(16) <= '1' WHEN (testin(16) = '1') ELSE + '0'; + testin_in(17) <= '1' WHEN (testin(17) = '1') ELSE + '0'; + testin_in(18) <= '1' WHEN (testin(18) = '1') ELSE + '0'; + testin_in(19) <= '1' WHEN (testin(19) = '1') ELSE + '0'; + testin_in(20) <= '1' WHEN (testin(20) = '1') ELSE + '0'; + testin_in(21) <= '1' WHEN (testin(21) = '1') ELSE + '0'; + testin_in(22) <= '1' WHEN (testin(22) = '1') ELSE + '0'; + testin_in(23) <= '1' WHEN (testin(23) = '1') ELSE + '0'; + testin_in(24) <= '1' WHEN (testin(24) = '1') ELSE + '0'; + testin_in(25) <= '1' WHEN (testin(25) = '1') ELSE + '0'; + testin_in(26) <= '1' WHEN (testin(26) = '1') ELSE + '0'; + testin_in(27) <= '1' WHEN (testin(27) = '1') ELSE + '0'; + testin_in(28) <= '1' WHEN (testin(28) = '1') ELSE + '0'; + testin_in(29) <= '1' WHEN (testin(29) = '1') ELSE + '0'; + testin_in(30) <= '1' WHEN (testin(30) = '1') ELSE + '0'; + testin_in(31) <= '1' WHEN (testin(31) = '1') ELSE + '0'; + testin_in(32) <= '1' WHEN (testin(32) = '1') ELSE + '0'; + testin_in(33) <= '1' WHEN (testin(33) = '1') ELSE + '0'; + testin_in(34) <= '1' WHEN (testin(34) = '1') ELSE + '0'; + testin_in(35) <= '1' WHEN (testin(35) = '1') ELSE + '0'; + testin_in(36) <= '1' WHEN (testin(36) = '1') ELSE + '0'; + testin_in(37) <= '1' WHEN (testin(37) = '1') ELSE + '0'; + testin_in(38) <= '1' WHEN (testin(38) = '1') ELSE + '0'; + testin_in(39) <= '1' WHEN (testin(39) = '1') ELSE + '0'; + + tlaermsinum_in(0) <= '1' WHEN (tlaermsinum(0) = '1') ELSE + '0'; + tlaermsinum_in(1) <= '1' WHEN (tlaermsinum(1) = '1') ELSE + '0'; + tlaermsinum_in(2) <= '1' WHEN (tlaermsinum(2) = '1') ELSE + '0'; + tlaermsinum_in(3) <= '1' WHEN (tlaermsinum(3) = '1') ELSE + '0'; + tlaermsinum_in(4) <= '1' WHEN (tlaermsinum(4) = '1') ELSE + '0'; + + tlappintasts_in <= '1' WHEN (tlappintasts = '1') ELSE + '0'; + + tlappmsinum_in(0) <= '1' WHEN (tlappmsinum(0) = '1') ELSE + '0'; + tlappmsinum_in(1) <= '1' WHEN (tlappmsinum(1) = '1') ELSE + '0'; + tlappmsinum_in(2) <= '1' WHEN (tlappmsinum(2) = '1') ELSE + '0'; + tlappmsinum_in(3) <= '1' WHEN (tlappmsinum(3) = '1') ELSE + '0'; + tlappmsinum_in(4) <= '1' WHEN (tlappmsinum(4) = '1') ELSE + '0'; + + tlappmsireq_in <= '1' WHEN (tlappmsireq = '1') ELSE + '0'; + + tlappmsitc_in(0) <= '1' WHEN (tlappmsitc(0) = '1') ELSE + '0'; + tlappmsitc_in(1) <= '1' WHEN (tlappmsitc(1) = '1') ELSE + '0'; + tlappmsitc_in(2) <= '1' WHEN (tlappmsitc(2) = '1') ELSE + '0'; + + tlhpgctrler_in(0) <= '1' WHEN (tlhpgctrler(0) = '1') ELSE + '0'; + tlhpgctrler_in(1) <= '1' WHEN (tlhpgctrler(1) = '1') ELSE + '0'; + tlhpgctrler_in(2) <= '1' WHEN (tlhpgctrler(2) = '1') ELSE + '0'; + tlhpgctrler_in(3) <= '1' WHEN (tlhpgctrler(3) = '1') ELSE + '0'; + tlhpgctrler_in(4) <= '1' WHEN (tlhpgctrler(4) = '1') ELSE + '0'; + + tlpexmsinum_in(0) <= '1' WHEN (tlpexmsinum(0) = '1') ELSE + '0'; + tlpexmsinum_in(1) <= '1' WHEN (tlpexmsinum(1) = '1') ELSE + '0'; + tlpexmsinum_in(2) <= '1' WHEN (tlpexmsinum(2) = '1') ELSE + '0'; + tlpexmsinum_in(3) <= '1' WHEN (tlpexmsinum(3) = '1') ELSE + '0'; + tlpexmsinum_in(4) <= '1' WHEN (tlpexmsinum(4) = '1') ELSE + '0'; + + tlpmauxpwr_in <= '1' WHEN (tlpmauxpwr = '1') ELSE + '0'; + + tlpmdata_in(0) <= '1' WHEN (tlpmdata(0) = '1') ELSE + '0'; + tlpmdata_in(1) <= '1' WHEN (tlpmdata(1) = '1') ELSE + '0'; + tlpmdata_in(2) <= '1' WHEN (tlpmdata(2) = '1') ELSE + '0'; + tlpmdata_in(3) <= '1' WHEN (tlpmdata(3) = '1') ELSE + '0'; + tlpmdata_in(4) <= '1' WHEN (tlpmdata(4) = '1') ELSE + '0'; + tlpmdata_in(5) <= '1' WHEN (tlpmdata(5) = '1') ELSE + '0'; + tlpmdata_in(6) <= '1' WHEN (tlpmdata(6) = '1') ELSE + '0'; + tlpmdata_in(7) <= '1' WHEN (tlpmdata(7) = '1') ELSE + '0'; + tlpmdata_in(8) <= '1' WHEN (tlpmdata(8) = '1') ELSE + '0'; + tlpmdata_in(9) <= '1' WHEN (tlpmdata(9) = '1') ELSE + '0'; + + tlpmetocr_in <= '1' WHEN (tlpmetocr = '1') ELSE + '0'; + tlpmevent_in <= '1' WHEN (tlpmevent = '1') ELSE + '0'; + tlslotclkcfg_in <= '1' WHEN (tlslotclkcfg = '1') ELSE + '0'; + + txdatavc00_in(0) <= '1' WHEN (txdatavc00(0) = '1') ELSE + '0'; + txdatavc00_in(1) <= '1' WHEN (txdatavc00(1) = '1') ELSE + '0'; + txdatavc00_in(2) <= '1' WHEN (txdatavc00(2) = '1') ELSE + '0'; + txdatavc00_in(3) <= '1' WHEN (txdatavc00(3) = '1') ELSE + '0'; + txdatavc00_in(4) <= '1' WHEN (txdatavc00(4) = '1') ELSE + '0'; + txdatavc00_in(5) <= '1' WHEN (txdatavc00(5) = '1') ELSE + '0'; + txdatavc00_in(6) <= '1' WHEN (txdatavc00(6) = '1') ELSE + '0'; + txdatavc00_in(7) <= '1' WHEN (txdatavc00(7) = '1') ELSE + '0'; + txdatavc00_in(8) <= '1' WHEN (txdatavc00(8) = '1') ELSE + '0'; + txdatavc00_in(9) <= '1' WHEN (txdatavc00(9) = '1') ELSE + '0'; + txdatavc00_in(10) <= '1' WHEN (txdatavc00(10) = '1') ELSE + '0'; + txdatavc00_in(11) <= '1' WHEN (txdatavc00(11) = '1') ELSE + '0'; + txdatavc00_in(12) <= '1' WHEN (txdatavc00(12) = '1') ELSE + '0'; + txdatavc00_in(13) <= '1' WHEN (txdatavc00(13) = '1') ELSE + '0'; + txdatavc00_in(14) <= '1' WHEN (txdatavc00(14) = '1') ELSE + '0'; + txdatavc00_in(15) <= '1' WHEN (txdatavc00(15) = '1') ELSE + '0'; + txdatavc00_in(16) <= '1' WHEN (txdatavc00(16) = '1') ELSE + '0'; + txdatavc00_in(17) <= '1' WHEN (txdatavc00(17) = '1') ELSE + '0'; + txdatavc00_in(18) <= '1' WHEN (txdatavc00(18) = '1') ELSE + '0'; + txdatavc00_in(19) <= '1' WHEN (txdatavc00(19) = '1') ELSE + '0'; + txdatavc00_in(20) <= '1' WHEN (txdatavc00(20) = '1') ELSE + '0'; + txdatavc00_in(21) <= '1' WHEN (txdatavc00(21) = '1') ELSE + '0'; + txdatavc00_in(22) <= '1' WHEN (txdatavc00(22) = '1') ELSE + '0'; + txdatavc00_in(23) <= '1' WHEN (txdatavc00(23) = '1') ELSE + '0'; + txdatavc00_in(24) <= '1' WHEN (txdatavc00(24) = '1') ELSE + '0'; + txdatavc00_in(25) <= '1' WHEN (txdatavc00(25) = '1') ELSE + '0'; + txdatavc00_in(26) <= '1' WHEN (txdatavc00(26) = '1') ELSE + '0'; + txdatavc00_in(27) <= '1' WHEN (txdatavc00(27) = '1') ELSE + '0'; + txdatavc00_in(28) <= '1' WHEN (txdatavc00(28) = '1') ELSE + '0'; + txdatavc00_in(29) <= '1' WHEN (txdatavc00(29) = '1') ELSE + '0'; + txdatavc00_in(30) <= '1' WHEN (txdatavc00(30) = '1') ELSE + '0'; + txdatavc00_in(31) <= '1' WHEN (txdatavc00(31) = '1') ELSE + '0'; + txdatavc00_in(32) <= '1' WHEN (txdatavc00(32) = '1') ELSE + '0'; + txdatavc00_in(33) <= '1' WHEN (txdatavc00(33) = '1') ELSE + '0'; + txdatavc00_in(34) <= '1' WHEN (txdatavc00(34) = '1') ELSE + '0'; + txdatavc00_in(35) <= '1' WHEN (txdatavc00(35) = '1') ELSE + '0'; + txdatavc00_in(36) <= '1' WHEN (txdatavc00(36) = '1') ELSE + '0'; + txdatavc00_in(37) <= '1' WHEN (txdatavc00(37) = '1') ELSE + '0'; + txdatavc00_in(38) <= '1' WHEN (txdatavc00(38) = '1') ELSE + '0'; + txdatavc00_in(39) <= '1' WHEN (txdatavc00(39) = '1') ELSE + '0'; + txdatavc00_in(40) <= '1' WHEN (txdatavc00(40) = '1') ELSE + '0'; + txdatavc00_in(41) <= '1' WHEN (txdatavc00(41) = '1') ELSE + '0'; + txdatavc00_in(42) <= '1' WHEN (txdatavc00(42) = '1') ELSE + '0'; + txdatavc00_in(43) <= '1' WHEN (txdatavc00(43) = '1') ELSE + '0'; + txdatavc00_in(44) <= '1' WHEN (txdatavc00(44) = '1') ELSE + '0'; + txdatavc00_in(45) <= '1' WHEN (txdatavc00(45) = '1') ELSE + '0'; + txdatavc00_in(46) <= '1' WHEN (txdatavc00(46) = '1') ELSE + '0'; + txdatavc00_in(47) <= '1' WHEN (txdatavc00(47) = '1') ELSE + '0'; + txdatavc00_in(48) <= '1' WHEN (txdatavc00(48) = '1') ELSE + '0'; + txdatavc00_in(49) <= '1' WHEN (txdatavc00(49) = '1') ELSE + '0'; + txdatavc00_in(50) <= '1' WHEN (txdatavc00(50) = '1') ELSE + '0'; + txdatavc00_in(51) <= '1' WHEN (txdatavc00(51) = '1') ELSE + '0'; + txdatavc00_in(52) <= '1' WHEN (txdatavc00(52) = '1') ELSE + '0'; + txdatavc00_in(53) <= '1' WHEN (txdatavc00(53) = '1') ELSE + '0'; + txdatavc00_in(54) <= '1' WHEN (txdatavc00(54) = '1') ELSE + '0'; + txdatavc00_in(55) <= '1' WHEN (txdatavc00(55) = '1') ELSE + '0'; + txdatavc00_in(56) <= '1' WHEN (txdatavc00(56) = '1') ELSE + '0'; + txdatavc00_in(57) <= '1' WHEN (txdatavc00(57) = '1') ELSE + '0'; + txdatavc00_in(58) <= '1' WHEN (txdatavc00(58) = '1') ELSE + '0'; + txdatavc00_in(59) <= '1' WHEN (txdatavc00(59) = '1') ELSE + '0'; + txdatavc00_in(60) <= '1' WHEN (txdatavc00(60) = '1') ELSE + '0'; + txdatavc00_in(61) <= '1' WHEN (txdatavc00(61) = '1') ELSE + '0'; + txdatavc00_in(62) <= '1' WHEN (txdatavc00(62) = '1') ELSE + '0'; + txdatavc00_in(63) <= '1' WHEN (txdatavc00(63) = '1') ELSE + '0'; + + txdatavc01_in(0) <= '1' WHEN (txdatavc01(0) = '1') ELSE + '0'; + txdatavc01_in(1) <= '1' WHEN (txdatavc01(1) = '1') ELSE + '0'; + txdatavc01_in(2) <= '1' WHEN (txdatavc01(2) = '1') ELSE + '0'; + txdatavc01_in(3) <= '1' WHEN (txdatavc01(3) = '1') ELSE + '0'; + txdatavc01_in(4) <= '1' WHEN (txdatavc01(4) = '1') ELSE + '0'; + txdatavc01_in(5) <= '1' WHEN (txdatavc01(5) = '1') ELSE + '0'; + txdatavc01_in(6) <= '1' WHEN (txdatavc01(6) = '1') ELSE + '0'; + txdatavc01_in(7) <= '1' WHEN (txdatavc01(7) = '1') ELSE + '0'; + txdatavc01_in(8) <= '1' WHEN (txdatavc01(8) = '1') ELSE + '0'; + txdatavc01_in(9) <= '1' WHEN (txdatavc01(9) = '1') ELSE + '0'; + txdatavc01_in(10) <= '1' WHEN (txdatavc01(10) = '1') ELSE + '0'; + txdatavc01_in(11) <= '1' WHEN (txdatavc01(11) = '1') ELSE + '0'; + txdatavc01_in(12) <= '1' WHEN (txdatavc01(12) = '1') ELSE + '0'; + txdatavc01_in(13) <= '1' WHEN (txdatavc01(13) = '1') ELSE + '0'; + txdatavc01_in(14) <= '1' WHEN (txdatavc01(14) = '1') ELSE + '0'; + txdatavc01_in(15) <= '1' WHEN (txdatavc01(15) = '1') ELSE + '0'; + txdatavc01_in(16) <= '1' WHEN (txdatavc01(16) = '1') ELSE + '0'; + txdatavc01_in(17) <= '1' WHEN (txdatavc01(17) = '1') ELSE + '0'; + txdatavc01_in(18) <= '1' WHEN (txdatavc01(18) = '1') ELSE + '0'; + txdatavc01_in(19) <= '1' WHEN (txdatavc01(19) = '1') ELSE + '0'; + txdatavc01_in(20) <= '1' WHEN (txdatavc01(20) = '1') ELSE + '0'; + txdatavc01_in(21) <= '1' WHEN (txdatavc01(21) = '1') ELSE + '0'; + txdatavc01_in(22) <= '1' WHEN (txdatavc01(22) = '1') ELSE + '0'; + txdatavc01_in(23) <= '1' WHEN (txdatavc01(23) = '1') ELSE + '0'; + txdatavc01_in(24) <= '1' WHEN (txdatavc01(24) = '1') ELSE + '0'; + txdatavc01_in(25) <= '1' WHEN (txdatavc01(25) = '1') ELSE + '0'; + txdatavc01_in(26) <= '1' WHEN (txdatavc01(26) = '1') ELSE + '0'; + txdatavc01_in(27) <= '1' WHEN (txdatavc01(27) = '1') ELSE + '0'; + txdatavc01_in(28) <= '1' WHEN (txdatavc01(28) = '1') ELSE + '0'; + txdatavc01_in(29) <= '1' WHEN (txdatavc01(29) = '1') ELSE + '0'; + txdatavc01_in(30) <= '1' WHEN (txdatavc01(30) = '1') ELSE + '0'; + txdatavc01_in(31) <= '1' WHEN (txdatavc01(31) = '1') ELSE + '0'; + txdatavc01_in(32) <= '1' WHEN (txdatavc01(32) = '1') ELSE + '0'; + txdatavc01_in(33) <= '1' WHEN (txdatavc01(33) = '1') ELSE + '0'; + txdatavc01_in(34) <= '1' WHEN (txdatavc01(34) = '1') ELSE + '0'; + txdatavc01_in(35) <= '1' WHEN (txdatavc01(35) = '1') ELSE + '0'; + txdatavc01_in(36) <= '1' WHEN (txdatavc01(36) = '1') ELSE + '0'; + txdatavc01_in(37) <= '1' WHEN (txdatavc01(37) = '1') ELSE + '0'; + txdatavc01_in(38) <= '1' WHEN (txdatavc01(38) = '1') ELSE + '0'; + txdatavc01_in(39) <= '1' WHEN (txdatavc01(39) = '1') ELSE + '0'; + txdatavc01_in(40) <= '1' WHEN (txdatavc01(40) = '1') ELSE + '0'; + txdatavc01_in(41) <= '1' WHEN (txdatavc01(41) = '1') ELSE + '0'; + txdatavc01_in(42) <= '1' WHEN (txdatavc01(42) = '1') ELSE + '0'; + txdatavc01_in(43) <= '1' WHEN (txdatavc01(43) = '1') ELSE + '0'; + txdatavc01_in(44) <= '1' WHEN (txdatavc01(44) = '1') ELSE + '0'; + txdatavc01_in(45) <= '1' WHEN (txdatavc01(45) = '1') ELSE + '0'; + txdatavc01_in(46) <= '1' WHEN (txdatavc01(46) = '1') ELSE + '0'; + txdatavc01_in(47) <= '1' WHEN (txdatavc01(47) = '1') ELSE + '0'; + txdatavc01_in(48) <= '1' WHEN (txdatavc01(48) = '1') ELSE + '0'; + txdatavc01_in(49) <= '1' WHEN (txdatavc01(49) = '1') ELSE + '0'; + txdatavc01_in(50) <= '1' WHEN (txdatavc01(50) = '1') ELSE + '0'; + txdatavc01_in(51) <= '1' WHEN (txdatavc01(51) = '1') ELSE + '0'; + txdatavc01_in(52) <= '1' WHEN (txdatavc01(52) = '1') ELSE + '0'; + txdatavc01_in(53) <= '1' WHEN (txdatavc01(53) = '1') ELSE + '0'; + txdatavc01_in(54) <= '1' WHEN (txdatavc01(54) = '1') ELSE + '0'; + txdatavc01_in(55) <= '1' WHEN (txdatavc01(55) = '1') ELSE + '0'; + txdatavc01_in(56) <= '1' WHEN (txdatavc01(56) = '1') ELSE + '0'; + txdatavc01_in(57) <= '1' WHEN (txdatavc01(57) = '1') ELSE + '0'; + txdatavc01_in(58) <= '1' WHEN (txdatavc01(58) = '1') ELSE + '0'; + txdatavc01_in(59) <= '1' WHEN (txdatavc01(59) = '1') ELSE + '0'; + txdatavc01_in(60) <= '1' WHEN (txdatavc01(60) = '1') ELSE + '0'; + txdatavc01_in(61) <= '1' WHEN (txdatavc01(61) = '1') ELSE + '0'; + txdatavc01_in(62) <= '1' WHEN (txdatavc01(62) = '1') ELSE + '0'; + txdatavc01_in(63) <= '1' WHEN (txdatavc01(63) = '1') ELSE + '0'; + + txdatavc10_in(0) <= '1' WHEN (txdatavc10(0) = '1') ELSE + '0'; + txdatavc10_in(1) <= '1' WHEN (txdatavc10(1) = '1') ELSE + '0'; + txdatavc10_in(2) <= '1' WHEN (txdatavc10(2) = '1') ELSE + '0'; + txdatavc10_in(3) <= '1' WHEN (txdatavc10(3) = '1') ELSE + '0'; + txdatavc10_in(4) <= '1' WHEN (txdatavc10(4) = '1') ELSE + '0'; + txdatavc10_in(5) <= '1' WHEN (txdatavc10(5) = '1') ELSE + '0'; + txdatavc10_in(6) <= '1' WHEN (txdatavc10(6) = '1') ELSE + '0'; + txdatavc10_in(7) <= '1' WHEN (txdatavc10(7) = '1') ELSE + '0'; + txdatavc10_in(8) <= '1' WHEN (txdatavc10(8) = '1') ELSE + '0'; + txdatavc10_in(9) <= '1' WHEN (txdatavc10(9) = '1') ELSE + '0'; + txdatavc10_in(10) <= '1' WHEN (txdatavc10(10) = '1') ELSE + '0'; + txdatavc10_in(11) <= '1' WHEN (txdatavc10(11) = '1') ELSE + '0'; + txdatavc10_in(12) <= '1' WHEN (txdatavc10(12) = '1') ELSE + '0'; + txdatavc10_in(13) <= '1' WHEN (txdatavc10(13) = '1') ELSE + '0'; + txdatavc10_in(14) <= '1' WHEN (txdatavc10(14) = '1') ELSE + '0'; + txdatavc10_in(15) <= '1' WHEN (txdatavc10(15) = '1') ELSE + '0'; + txdatavc10_in(16) <= '1' WHEN (txdatavc10(16) = '1') ELSE + '0'; + txdatavc10_in(17) <= '1' WHEN (txdatavc10(17) = '1') ELSE + '0'; + txdatavc10_in(18) <= '1' WHEN (txdatavc10(18) = '1') ELSE + '0'; + txdatavc10_in(19) <= '1' WHEN (txdatavc10(19) = '1') ELSE + '0'; + txdatavc10_in(20) <= '1' WHEN (txdatavc10(20) = '1') ELSE + '0'; + txdatavc10_in(21) <= '1' WHEN (txdatavc10(21) = '1') ELSE + '0'; + txdatavc10_in(22) <= '1' WHEN (txdatavc10(22) = '1') ELSE + '0'; + txdatavc10_in(23) <= '1' WHEN (txdatavc10(23) = '1') ELSE + '0'; + txdatavc10_in(24) <= '1' WHEN (txdatavc10(24) = '1') ELSE + '0'; + txdatavc10_in(25) <= '1' WHEN (txdatavc10(25) = '1') ELSE + '0'; + txdatavc10_in(26) <= '1' WHEN (txdatavc10(26) = '1') ELSE + '0'; + txdatavc10_in(27) <= '1' WHEN (txdatavc10(27) = '1') ELSE + '0'; + txdatavc10_in(28) <= '1' WHEN (txdatavc10(28) = '1') ELSE + '0'; + txdatavc10_in(29) <= '1' WHEN (txdatavc10(29) = '1') ELSE + '0'; + txdatavc10_in(30) <= '1' WHEN (txdatavc10(30) = '1') ELSE + '0'; + txdatavc10_in(31) <= '1' WHEN (txdatavc10(31) = '1') ELSE + '0'; + txdatavc10_in(32) <= '1' WHEN (txdatavc10(32) = '1') ELSE + '0'; + txdatavc10_in(33) <= '1' WHEN (txdatavc10(33) = '1') ELSE + '0'; + txdatavc10_in(34) <= '1' WHEN (txdatavc10(34) = '1') ELSE + '0'; + txdatavc10_in(35) <= '1' WHEN (txdatavc10(35) = '1') ELSE + '0'; + txdatavc10_in(36) <= '1' WHEN (txdatavc10(36) = '1') ELSE + '0'; + txdatavc10_in(37) <= '1' WHEN (txdatavc10(37) = '1') ELSE + '0'; + txdatavc10_in(38) <= '1' WHEN (txdatavc10(38) = '1') ELSE + '0'; + txdatavc10_in(39) <= '1' WHEN (txdatavc10(39) = '1') ELSE + '0'; + txdatavc10_in(40) <= '1' WHEN (txdatavc10(40) = '1') ELSE + '0'; + txdatavc10_in(41) <= '1' WHEN (txdatavc10(41) = '1') ELSE + '0'; + txdatavc10_in(42) <= '1' WHEN (txdatavc10(42) = '1') ELSE + '0'; + txdatavc10_in(43) <= '1' WHEN (txdatavc10(43) = '1') ELSE + '0'; + txdatavc10_in(44) <= '1' WHEN (txdatavc10(44) = '1') ELSE + '0'; + txdatavc10_in(45) <= '1' WHEN (txdatavc10(45) = '1') ELSE + '0'; + txdatavc10_in(46) <= '1' WHEN (txdatavc10(46) = '1') ELSE + '0'; + txdatavc10_in(47) <= '1' WHEN (txdatavc10(47) = '1') ELSE + '0'; + txdatavc10_in(48) <= '1' WHEN (txdatavc10(48) = '1') ELSE + '0'; + txdatavc10_in(49) <= '1' WHEN (txdatavc10(49) = '1') ELSE + '0'; + txdatavc10_in(50) <= '1' WHEN (txdatavc10(50) = '1') ELSE + '0'; + txdatavc10_in(51) <= '1' WHEN (txdatavc10(51) = '1') ELSE + '0'; + txdatavc10_in(52) <= '1' WHEN (txdatavc10(52) = '1') ELSE + '0'; + txdatavc10_in(53) <= '1' WHEN (txdatavc10(53) = '1') ELSE + '0'; + txdatavc10_in(54) <= '1' WHEN (txdatavc10(54) = '1') ELSE + '0'; + txdatavc10_in(55) <= '1' WHEN (txdatavc10(55) = '1') ELSE + '0'; + txdatavc10_in(56) <= '1' WHEN (txdatavc10(56) = '1') ELSE + '0'; + txdatavc10_in(57) <= '1' WHEN (txdatavc10(57) = '1') ELSE + '0'; + txdatavc10_in(58) <= '1' WHEN (txdatavc10(58) = '1') ELSE + '0'; + txdatavc10_in(59) <= '1' WHEN (txdatavc10(59) = '1') ELSE + '0'; + txdatavc10_in(60) <= '1' WHEN (txdatavc10(60) = '1') ELSE + '0'; + txdatavc10_in(61) <= '1' WHEN (txdatavc10(61) = '1') ELSE + '0'; + txdatavc10_in(62) <= '1' WHEN (txdatavc10(62) = '1') ELSE + '0'; + txdatavc10_in(63) <= '1' WHEN (txdatavc10(63) = '1') ELSE + '0'; + + txdatavc11_in(0) <= '1' WHEN (txdatavc11(0) = '1') ELSE + '0'; + txdatavc11_in(1) <= '1' WHEN (txdatavc11(1) = '1') ELSE + '0'; + txdatavc11_in(2) <= '1' WHEN (txdatavc11(2) = '1') ELSE + '0'; + txdatavc11_in(3) <= '1' WHEN (txdatavc11(3) = '1') ELSE + '0'; + txdatavc11_in(4) <= '1' WHEN (txdatavc11(4) = '1') ELSE + '0'; + txdatavc11_in(5) <= '1' WHEN (txdatavc11(5) = '1') ELSE + '0'; + txdatavc11_in(6) <= '1' WHEN (txdatavc11(6) = '1') ELSE + '0'; + txdatavc11_in(7) <= '1' WHEN (txdatavc11(7) = '1') ELSE + '0'; + txdatavc11_in(8) <= '1' WHEN (txdatavc11(8) = '1') ELSE + '0'; + txdatavc11_in(9) <= '1' WHEN (txdatavc11(9) = '1') ELSE + '0'; + txdatavc11_in(10) <= '1' WHEN (txdatavc11(10) = '1') ELSE + '0'; + txdatavc11_in(11) <= '1' WHEN (txdatavc11(11) = '1') ELSE + '0'; + txdatavc11_in(12) <= '1' WHEN (txdatavc11(12) = '1') ELSE + '0'; + txdatavc11_in(13) <= '1' WHEN (txdatavc11(13) = '1') ELSE + '0'; + txdatavc11_in(14) <= '1' WHEN (txdatavc11(14) = '1') ELSE + '0'; + txdatavc11_in(15) <= '1' WHEN (txdatavc11(15) = '1') ELSE + '0'; + txdatavc11_in(16) <= '1' WHEN (txdatavc11(16) = '1') ELSE + '0'; + txdatavc11_in(17) <= '1' WHEN (txdatavc11(17) = '1') ELSE + '0'; + txdatavc11_in(18) <= '1' WHEN (txdatavc11(18) = '1') ELSE + '0'; + txdatavc11_in(19) <= '1' WHEN (txdatavc11(19) = '1') ELSE + '0'; + txdatavc11_in(20) <= '1' WHEN (txdatavc11(20) = '1') ELSE + '0'; + txdatavc11_in(21) <= '1' WHEN (txdatavc11(21) = '1') ELSE + '0'; + txdatavc11_in(22) <= '1' WHEN (txdatavc11(22) = '1') ELSE + '0'; + txdatavc11_in(23) <= '1' WHEN (txdatavc11(23) = '1') ELSE + '0'; + txdatavc11_in(24) <= '1' WHEN (txdatavc11(24) = '1') ELSE + '0'; + txdatavc11_in(25) <= '1' WHEN (txdatavc11(25) = '1') ELSE + '0'; + txdatavc11_in(26) <= '1' WHEN (txdatavc11(26) = '1') ELSE + '0'; + txdatavc11_in(27) <= '1' WHEN (txdatavc11(27) = '1') ELSE + '0'; + txdatavc11_in(28) <= '1' WHEN (txdatavc11(28) = '1') ELSE + '0'; + txdatavc11_in(29) <= '1' WHEN (txdatavc11(29) = '1') ELSE + '0'; + txdatavc11_in(30) <= '1' WHEN (txdatavc11(30) = '1') ELSE + '0'; + txdatavc11_in(31) <= '1' WHEN (txdatavc11(31) = '1') ELSE + '0'; + txdatavc11_in(32) <= '1' WHEN (txdatavc11(32) = '1') ELSE + '0'; + txdatavc11_in(33) <= '1' WHEN (txdatavc11(33) = '1') ELSE + '0'; + txdatavc11_in(34) <= '1' WHEN (txdatavc11(34) = '1') ELSE + '0'; + txdatavc11_in(35) <= '1' WHEN (txdatavc11(35) = '1') ELSE + '0'; + txdatavc11_in(36) <= '1' WHEN (txdatavc11(36) = '1') ELSE + '0'; + txdatavc11_in(37) <= '1' WHEN (txdatavc11(37) = '1') ELSE + '0'; + txdatavc11_in(38) <= '1' WHEN (txdatavc11(38) = '1') ELSE + '0'; + txdatavc11_in(39) <= '1' WHEN (txdatavc11(39) = '1') ELSE + '0'; + txdatavc11_in(40) <= '1' WHEN (txdatavc11(40) = '1') ELSE + '0'; + txdatavc11_in(41) <= '1' WHEN (txdatavc11(41) = '1') ELSE + '0'; + txdatavc11_in(42) <= '1' WHEN (txdatavc11(42) = '1') ELSE + '0'; + txdatavc11_in(43) <= '1' WHEN (txdatavc11(43) = '1') ELSE + '0'; + txdatavc11_in(44) <= '1' WHEN (txdatavc11(44) = '1') ELSE + '0'; + txdatavc11_in(45) <= '1' WHEN (txdatavc11(45) = '1') ELSE + '0'; + txdatavc11_in(46) <= '1' WHEN (txdatavc11(46) = '1') ELSE + '0'; + txdatavc11_in(47) <= '1' WHEN (txdatavc11(47) = '1') ELSE + '0'; + txdatavc11_in(48) <= '1' WHEN (txdatavc11(48) = '1') ELSE + '0'; + txdatavc11_in(49) <= '1' WHEN (txdatavc11(49) = '1') ELSE + '0'; + txdatavc11_in(50) <= '1' WHEN (txdatavc11(50) = '1') ELSE + '0'; + txdatavc11_in(51) <= '1' WHEN (txdatavc11(51) = '1') ELSE + '0'; + txdatavc11_in(52) <= '1' WHEN (txdatavc11(52) = '1') ELSE + '0'; + txdatavc11_in(53) <= '1' WHEN (txdatavc11(53) = '1') ELSE + '0'; + txdatavc11_in(54) <= '1' WHEN (txdatavc11(54) = '1') ELSE + '0'; + txdatavc11_in(55) <= '1' WHEN (txdatavc11(55) = '1') ELSE + '0'; + txdatavc11_in(56) <= '1' WHEN (txdatavc11(56) = '1') ELSE + '0'; + txdatavc11_in(57) <= '1' WHEN (txdatavc11(57) = '1') ELSE + '0'; + txdatavc11_in(58) <= '1' WHEN (txdatavc11(58) = '1') ELSE + '0'; + txdatavc11_in(59) <= '1' WHEN (txdatavc11(59) = '1') ELSE + '0'; + txdatavc11_in(60) <= '1' WHEN (txdatavc11(60) = '1') ELSE + '0'; + txdatavc11_in(61) <= '1' WHEN (txdatavc11(61) = '1') ELSE + '0'; + txdatavc11_in(62) <= '1' WHEN (txdatavc11(62) = '1') ELSE + '0'; + txdatavc11_in(63) <= '1' WHEN (txdatavc11(63) = '1') ELSE + '0'; + + txeopvc00_in <= '1' WHEN (txeopvc00 = '1') ELSE + '0'; + txeopvc01_in <= '1' WHEN (txeopvc01 = '1') ELSE + '0'; + txeopvc10_in <= '1' WHEN (txeopvc10 = '1') ELSE + '0'; + txeopvc11_in <= '1' WHEN (txeopvc11 = '1') ELSE + '0'; + txerrvc0_in <= '1' WHEN (txerrvc0 = '1') ELSE + '0'; + txerrvc1_in <= '1' WHEN (txerrvc1 = '1') ELSE + '0'; + txsopvc00_in <= '1' WHEN (txsopvc00 = '1') ELSE + '0'; + txsopvc01_in <= '1' WHEN (txsopvc01 = '1') ELSE + '0'; + txsopvc10_in <= '1' WHEN (txsopvc10 = '1') ELSE + '0'; + txsopvc11_in <= '1' WHEN (txsopvc11 = '1') ELSE + '0'; + txvalidvc0_in <= '1' WHEN (txvalidvc0 = '1') ELSE + '0'; + txvalidvc1_in <= '1' WHEN (txvalidvc1 = '1') ELSE + '0'; + + --/////////////////////////////////////////////////////////////////////////// + -- WYS input --> RTL_input port association ------------- -----------------// + --/////////////////////////////////////////////////////////////////////////// + ht_in_bist_scanen <= bistscanen_ipd; + ht_in_bist_scanin <= bistscanin_ipd; + ht_in_bist_testen <= bisttesten_ipd; + ht_in_bisten_rcv0 <= bistenrcv0_ipd; + ht_in_bisten_rcv1 <= bistenrcv1_ipd; + ht_in_bisten_rpl <= bistenrpl_ipd; + ht_in_core_clk_in <= coreclkin_ipd; + ht_in_core_crst <= corecrst_ipd; + ht_in_core_por <= corepor_ipd; + ht_in_core_rst <= corerst_ipd; + ht_in_core_srst <= coresrst_ipd; + ht_in_cpl_err <= cplerr_ipd; + ht_in_cpl_pending <= cplpending_ipd; + ht_in_dbg_pipex1_rx <= dbgpipex1rx_ipd; + ht_in_dl_aspm_cr0 <= dlaspmcr0_ipd; + ht_in_dl_comclk_reg <= dlcomclkreg_ipd; + ht_in_dl_ctrl_link2 <= dlctrllink2_ipd; + ht_in_dl_data_upfc <= dldataupfc_ipd; + ht_in_dl_hdr_upfc <= dlhdrupfc_ipd; + ht_in_dl_inh_dllp <= dlinhdllp_ipd; + ht_in_dl_maxpload_dcr <= dlmaxploaddcr_ipd; + ht_in_dl_req_phycfg <= dlreqphycfg_ipd; + ht_in_dl_req_phypm <= dlreqphypm_ipd; + ht_in_dl_req_upfc <= dlrequpfc_ipd; + ht_in_dl_req_wake <= dlreqwake_ipd; + ht_in_dl_rx_ecrcchk <= dlrxecrcchk_ipd; + ht_in_dl_snd_upfc <= dlsndupfc_ipd; + ht_in_dl_tx_req_pm <= dltxreqpm_ipd; + ht_in_dl_tx_typ_pm <= dltxtyppm_ipd; + ht_in_dl_txcfg_extsy <= dltxcfgextsy_ipd; + ht_in_dl_typ_upfc <= dltypupfc_ipd; + ht_in_dl_vc_ctrl <= dlvcctrl_ipd; + ht_in_dl_vcid_map <= dlvcidmap_ipd; + ht_in_dl_vcid_upfc <= dlvcidupfc_ipd; + ht_in_entest <= '0'; -- no need in WYS + ht_in_frzlogic <= '0'; -- no need in WYS + ht_in_frzreg <= '0'; -- no need in WYS + ht_in_hip_extraclkin <= "00"; -- reserved + ht_in_hip_extrain <= extrain_ipd; -- reserved + ht_in_id_rcv0 <= "00000000"; -- not in WYS - HIP MRAM IDs + ht_in_id_rcv1 <= "00000000"; -- not in WYS - HIP MRAM IDs + ht_in_id_rpl <= "00000000"; -- not in WYS - HIP MRAM IDs + ht_in_lmi_addr <= lmiaddr_ipd; + ht_in_lmi_din <= lmidin_ipd; + ht_in_lmi_rden <= lmirden_ipd; + ht_in_lmi_wren <= lmiwren_ipd; + ht_in_mdc <= dpclk_ipd; + ht_in_mdio_dis <= dpriodisable_ipd; + ht_in_mdio_in <= dprioin_ipd; + ht_in_mode <= mode_ipd; + ht_in_mram_hip_test_enable <= mramhiptestenable_ipd; + ht_in_mram_red_enscan <= '0'; -- no need in WYS + ht_in_mram_red_scen <= '0'; -- no need in WYS + ht_in_mram_red_scin <= '0'; -- no need in WYS + ht_in_mram_red_sclk <= '0'; -- no need in WYS + ht_in_mram_red_scrst <= '0'; -- no need in WYS + ht_in_mram_red_scsel <= '0'; -- no need in WYS + ht_in_mram_regscanen <= mramregscanen_ipd; + ht_in_mram_regscanin <= mramregscanin_ipd; + ht_in_nfrzdrv <= '1'; -- no need in WYS + ht_in_npor <= '1'; -- no need in WYS + ht_in_pclk_central <= pclkcentral_ipd; + ht_in_pclk_ch0 <= pclkch0_ipd; + ht_in_phy_rst <= phyrst_ipd; + ht_in_phy_srst <= physrst_ipd; + ht_in_phystatus0 <= phystatus_ipd(0); + ht_in_phystatus1 <= phystatus_ipd(1); + ht_in_phystatus2 <= phystatus_ipd(2); + ht_in_phystatus3 <= phystatus_ipd(3); + ht_in_phystatus4 <= phystatus_ipd(4); + ht_in_phystatus5 <= phystatus_ipd(5); + ht_in_phystatus6 <= phystatus_ipd(6); + ht_in_phystatus7 <= phystatus_ipd(7); + ht_in_pld_clk <= pldclk_ipd; + ht_in_pld_rst <= pldrst_ipd; + ht_in_pld_srst <= pldsrst_ipd; + ht_in_pll_fixed_clk <= pllfixedclk_ipd; + ht_in_plniotri <= '1'; -- no need in WYS + ht_in_rx_mask_vc0 <= rxmaskvc0_ipd; + ht_in_rx_mask_vc1 <= rxmaskvc1_ipd; + ht_in_rx_ready_vc0 <= rxreadyvc0_ipd; + ht_in_rx_ready_vc1 <= rxreadyvc1_ipd; + ht_in_rxdata0 <= rxdata_ipd(7 DOWNTO 0); + ht_in_rxdata1 <= rxdata_ipd(15 DOWNTO 8); + ht_in_rxdata2 <= rxdata_ipd(23 DOWNTO 16); + ht_in_rxdata3 <= rxdata_ipd(31 DOWNTO 24); + ht_in_rxdata4 <= rxdata_ipd(39 DOWNTO 32); + ht_in_rxdata5 <= rxdata_ipd(47 DOWNTO 40); + ht_in_rxdata6 <= rxdata_ipd(55 DOWNTO 48); + ht_in_rxdata7 <= rxdata_ipd(63 DOWNTO 56); + ht_in_rxdatak0 <= rxdatak_ipd(0); + ht_in_rxdatak1 <= rxdatak_ipd(1); + ht_in_rxdatak2 <= rxdatak_ipd(2); + ht_in_rxdatak3 <= rxdatak_ipd(3); + ht_in_rxdatak4 <= rxdatak_ipd(4); + ht_in_rxdatak5 <= rxdatak_ipd(5); + ht_in_rxdatak6 <= rxdatak_ipd(6); + ht_in_rxdatak7 <= rxdatak_ipd(7); + ht_in_rxelecidle0 <= rxelecidle_ipd(0); + ht_in_rxelecidle1 <= rxelecidle_ipd(1); + ht_in_rxelecidle2 <= rxelecidle_ipd(2); + ht_in_rxelecidle3 <= rxelecidle_ipd(3); + ht_in_rxelecidle4 <= rxelecidle_ipd(4); + ht_in_rxelecidle5 <= rxelecidle_ipd(5); + ht_in_rxelecidle6 <= rxelecidle_ipd(6); + ht_in_rxelecidle7 <= rxelecidle_ipd(7); + ht_in_rxstatus0 <= rxstatus_ipd(2 DOWNTO 0); + ht_in_rxstatus1 <= rxstatus_ipd(5 DOWNTO 3); + ht_in_rxstatus2 <= rxstatus_ipd(8 DOWNTO 6); + ht_in_rxstatus3 <= rxstatus_ipd(11 DOWNTO 9); + ht_in_rxstatus4 <= rxstatus_ipd(14 DOWNTO 12); + ht_in_rxstatus5 <= rxstatus_ipd(17 DOWNTO 15); + ht_in_rxstatus6 <= rxstatus_ipd(20 DOWNTO 18); + ht_in_rxstatus7 <= rxstatus_ipd(23 DOWNTO 21); + ht_in_rxvalid0 <= rxvalid_ipd(0); + ht_in_rxvalid1 <= rxvalid_ipd(1); + ht_in_rxvalid2 <= rxvalid_ipd(2); + ht_in_rxvalid3 <= rxvalid_ipd(3); + ht_in_rxvalid4 <= rxvalid_ipd(4); + ht_in_rxvalid5 <= rxvalid_ipd(5); + ht_in_rxvalid6 <= rxvalid_ipd(6); + ht_in_rxvalid7 <= rxvalid_ipd(7); + ht_in_scan_en <= scanen_ipd; + ht_in_scan_mode_n <= scanmoden_ipd; + ht_in_ser_shift_load <= dprioload_ipd; + ht_in_swdn_in <= swdnin_ipd; + ht_in_swup_in <= swupin_ipd; + ht_in_test_in_hip <= testin_ipd; + ht_in_tl_aer_msi_num <= tlaermsinum_ipd; + ht_in_tl_app_inta_sts <= tlappintasts_ipd; + ht_in_tl_app_msi_num <= tlappmsinum_ipd; + ht_in_tl_app_msi_req <= tlappmsireq_ipd; + ht_in_tl_app_msi_tc <= tlappmsitc_ipd; + ht_in_tl_hpg_ctrler <= tlhpgctrler_ipd; + ht_in_tl_pex_msi_num <= tlpexmsinum_ipd; + ht_in_tl_pm_auxpwr <= tlpmauxpwr_ipd; + ht_in_tl_pm_data <= tlpmdata_ipd; + ht_in_tl_pm_event <= tlpmevent_ipd; + ht_in_tl_pme_to_cr <= tlpmetocr_ipd; + ht_in_tl_slotclk_cfg <= tlslotclkcfg_ipd; + ht_in_tx_data_vc0_0 <= txdatavc00_ipd; + ht_in_tx_data_vc0_1 <= txdatavc01_ipd; + ht_in_tx_data_vc1_0 <= txdatavc10_ipd; + ht_in_tx_data_vc1_1 <= txdatavc11_ipd; + ht_in_tx_eop_vc0_0 <= txeopvc00_ipd; + ht_in_tx_eop_vc0_1 <= txeopvc01_ipd; + ht_in_tx_eop_vc1_0 <= txeopvc10_ipd; + ht_in_tx_eop_vc1_1 <= txeopvc11_ipd; + ht_in_tx_err_vc0 <= txerrvc0_ipd; + ht_in_tx_err_vc1 <= txerrvc1_ipd; + ht_in_tx_sop_vc0_0 <= txsopvc00_ipd; + ht_in_tx_sop_vc0_1 <= txsopvc01_ipd; + ht_in_tx_sop_vc1_0 <= txsopvc10_ipd; + ht_in_tx_sop_vc1_1 <= txsopvc11_ipd; + ht_in_tx_valid_vc0 <= txvalidvc0_ipd; + ht_in_tx_valid_vc1 <= txvalidvc1_ipd; + + -- actually is CRAMs at FPGA + ht_in_dev_addr <= deviceaddress_in; + ht_in_hip_base_addr <= hipbaseaddress_in; + ht_in_port_addr <= portaddress_in; + + --/////////////////////////////////////////////////////////////////////////// + -- RTL_output --> WYS output port association ------------- ---------------// + --/////////////////////////////////////////////////////////////////////////// + bistdonearcv0_tmp <= ht_out_bist_donea_rcv0; + bistdonearcv1_tmp <= ht_out_bist_donea_rcv1; + bistdonearpl_tmp <= ht_out_bist_donea_rpl; + bistdonebrcv0_tmp <= ht_out_bist_doneb_rcv0; + bistdonebrcv1_tmp <= ht_out_bist_doneb_rcv1; + bistdonebrpl_tmp <= ht_out_bist_doneb_rpl; + bistpassrcv0_tmp <= ht_out_bist_pass_rcv0; + bistpassrcv1_tmp <= ht_out_bist_pass_rcv1; + bistpassrpl_tmp <= ht_out_bist_pass_rpl; + bistscanoutrcv0_tmp <= ht_out_bist_scanout_rcv0; + bistscanoutrcv1_tmp <= ht_out_bist_scanout_rcv1; + bistscanoutrpl_tmp <= ht_out_bist_scanout_rpl; + clrrxpath_tmp <= ht_out_clr_rxpath; + coreclkout_tmp <= ht_out_core_clk_out; + dataenablen_tmp <= ht_out_data_enable_n; + derrcorextrcv0_tmp <= ht_out_derr_cor_ext_rcv0; + derrcorextrcv1_tmp <= ht_out_derr_cor_ext_rcv1; + derrcorextrpl_tmp <= ht_out_derr_cor_ext_rpl; + derrrpl_tmp <= ht_out_derr_rpl; + dlackphypm_tmp <= ht_out_dl_ack_phypm; + dlackrequpfc_tmp <= ht_out_dl_ack_req_upfc; + dlacksndupfc_tmp <= ht_out_dl_ack_snd_upfc; + dlcurrentdeemp_tmp <= ht_out_dl_current_deemp; + dlcurrentspeed_tmp <= ht_out_dl_current_speed; + dldllreq_tmp <= ht_out_dl_dll_req; + dlerrdll_tmp <= ht_out_dl_err_dll; + dlerrphy_tmp <= ht_out_dl_err_phy; + dllinkautobdwstatus_tmp <= ht_out_dl_link_auto_bdw_status; + dllinkbdwmngstatus_tmp <= ht_out_dl_link_bdw_mng_status; + dlltssm_tmp <= ht_out_dl_ltssm; + dlrpbufemp_tmp <= ht_out_dl_rpbuf_emp; + dlrstentercompbit_tmp <= ht_out_dl_rst_enter_comp_bit; + dlrsttxmarginfield_tmp <= ht_out_dl_rst_tx_margin_field; + dlrxtyppm_tmp <= ht_out_dl_rx_typ_pm; + dlrxvalpm_tmp <= ht_out_dl_rx_val_pm; + dltxackpm_tmp <= ht_out_dl_tx_ack_pm; + dlup_tmp <= ht_out_dl_up; + dlvcstatus_tmp <= ht_out_dl_vc_status; + dlupexit_tmp <= ht_out_dlup_exit; + dpriostate_tmp <= ht_out_dprio_curr_state; + eidleinfersel_tmp(2 DOWNTO 0) <= ht_out_eidle_infer_sel0; + eidleinfersel_tmp(5 DOWNTO 3) <= ht_out_eidle_infer_sel1; + eidleinfersel_tmp(8 DOWNTO 6) <= ht_out_eidle_infer_sel2; + eidleinfersel_tmp(11 DOWNTO 9) <= ht_out_eidle_infer_sel3; + eidleinfersel_tmp(14 DOWNTO 12) <= ht_out_eidle_infer_sel4; + eidleinfersel_tmp(17 DOWNTO 15) <= ht_out_eidle_infer_sel5; + eidleinfersel_tmp(20 DOWNTO 18) <= ht_out_eidle_infer_sel6; + eidleinfersel_tmp(23 DOWNTO 21) <= ht_out_eidle_infer_sel7; + ev128ns_tmp <= ht_out_ev_128ns; + ev1us_tmp <= ht_out_ev_1us; + extraclkout_tmp <= ht_out_hip_extraclkout; + extraout_tmp <= ht_out_extraout; + ------------ to complete: update RTL ------------------------------ + ht_out_extraout <= "00000000" & ht_out_hip_extraout; + ------------- end -------------------------------------------------- + + gen2rate_tmp <= ht_out_rate; + gen2rategnd_tmp <= ht_out_rate_tied_to_gnd; + hipextraclkout_tmp <= ht_out_hip_extraclkout; + hipextraout_tmp <= ht_out_hip_extraout; + hotrstexit_tmp <= ht_out_hotrst_exit; + intstatus_tmp <= ht_out_int_status; + l2exit_tmp <= ht_out_l2_exit; + laneact_tmp <= ht_out_lane_act; + linkup_tmp <= ht_out_link_up; + lmiack_tmp <= ht_out_lmi_ack; + lmidout_tmp <= ht_out_lmi_dout; + ltssml0state_tmp <= ht_out_ltssm_l0_state; + dprioout_tmp <= ht_out_mdio_out; + mramregscanout_tmp <= ht_out_mram_regscanout; + powerdown_tmp(1 DOWNTO 0) <= ht_out_powerdown0; + powerdown_tmp(3 DOWNTO 2) <= ht_out_powerdown1; + powerdown_tmp(5 DOWNTO 4) <= ht_out_powerdown2; + powerdown_tmp(7 DOWNTO 6) <= ht_out_powerdown3; + powerdown_tmp(9 DOWNTO 8) <= ht_out_powerdown4; + powerdown_tmp(11 DOWNTO 10) <= ht_out_powerdown5; + powerdown_tmp(13 DOWNTO 12) <= ht_out_powerdown6; + powerdown_tmp(15 DOWNTO 14) <= ht_out_powerdown7; + resetstatus_tmp <= ht_out_reset_status; + rxbardecvc0_tmp <= ht_out_rx_bar_dec_vc0; + rxbardecvc1_tmp <= ht_out_rx_bar_dec_vc1; + rxbevc00_tmp <= ht_out_rx_be_vc0_0; + rxbevc01_tmp <= ht_out_rx_be_vc0_1; + rxbevc10_tmp <= ht_out_rx_be_vc1_0; + rxbevc11_tmp <= ht_out_rx_be_vc1_1; + rxdatavc00_tmp <= ht_out_rx_data_vc0_0; + rxdatavc01_tmp <= ht_out_rx_data_vc0_1; + rxdatavc10_tmp <= ht_out_rx_data_vc1_0; + rxdatavc11_tmp <= ht_out_rx_data_vc1_1; + rxeopvc00_tmp <= ht_out_rx_eop_vc0_0; + rxeopvc01_tmp <= ht_out_rx_eop_vc0_1; + rxeopvc10_tmp <= ht_out_rx_eop_vc1_0; + rxeopvc11_tmp <= ht_out_rx_eop_vc1_1; + rxerrvc0_tmp <= ht_out_rx_err_vc0; + rxerrvc1_tmp <= ht_out_rx_err_vc1; + rxfifoemptyvc0_tmp <= ht_out_rx_fifo_empty_vc0; + rxfifoemptyvc1_tmp <= ht_out_rx_fifo_empty_vc1; + rxfifofullvc0_tmp <= ht_out_rx_fifo_full_vc0; + rxfifofullvc1_tmp <= ht_out_rx_fifo_full_vc1; + rxsopvc00_tmp <= ht_out_rx_sop_vc0_0; + rxsopvc01_tmp <= ht_out_rx_sop_vc0_1; + rxsopvc10_tmp <= ht_out_rx_sop_vc1_0; + rxsopvc11_tmp <= ht_out_rx_sop_vc1_1; + rxvalidvc0_tmp <= ht_out_rx_valid_vc0; + rxvalidvc1_tmp <= ht_out_rx_valid_vc1; + rxpolarity_tmp(0) <= ht_out_rxpolarity0; + rxpolarity_tmp(1) <= ht_out_rxpolarity1; + rxpolarity_tmp(2) <= ht_out_rxpolarity2; + rxpolarity_tmp(3) <= ht_out_rxpolarity3; + rxpolarity_tmp(4) <= ht_out_rxpolarity4; + rxpolarity_tmp(5) <= ht_out_rxpolarity5; + rxpolarity_tmp(6) <= ht_out_rxpolarity6; + rxpolarity_tmp(7) <= ht_out_rxpolarity7; + r2cerr0ext_tmp <= ht_out_hip_extraout(0); + serrout_tmp <= ht_out_serr_out; + successspeednegoint_tmp <= ht_out_hip_extraout(1); + swdnwake_tmp <= ht_out_swdn_wake; + swuphotrst_tmp <= ht_out_swup_hotrst; + testout_tmp <= ht_out_test_out_hip; + tlappintaack_tmp <= ht_out_tl_app_inta_ack; + tlappmsiack_tmp <= ht_out_tl_app_msi_ack; + tlcfgadd_tmp <= ht_out_tl_cfg_add; + tlcfgctl_tmp <= ht_out_tl_cfg_ctl; + tlcfgctlwr_tmp <= ht_out_tl_cfg_ctl_wr; + tlcfgsts_tmp <= ht_out_tl_cfg_sts; + tlcfgstswr_tmp <= ht_out_tl_cfg_sts_wr; + tlpmetosr_tmp <= ht_out_tl_pme_to_sr; + txcredvc0_tmp <= ht_out_tx_cred_vc0; + txcredvc1_tmp <= ht_out_tx_cred_vc1; + txdeemph_tmp(0) <= ht_out_tx_deemph0; + txdeemph_tmp(1) <= ht_out_tx_deemph1; + txdeemph_tmp(2) <= ht_out_tx_deemph2; + txdeemph_tmp(3) <= ht_out_tx_deemph3; + txdeemph_tmp(4) <= ht_out_tx_deemph4; + txdeemph_tmp(5) <= ht_out_tx_deemph5; + txdeemph_tmp(6) <= ht_out_tx_deemph6; + txdeemph_tmp(7) <= ht_out_tx_deemph7; + txfifoemptyvc0_tmp <= ht_out_tx_fifo_empty_vc0; + txfifoemptyvc1_tmp <= ht_out_tx_fifo_empty_vc1; + txfifofullvc0_tmp <= ht_out_tx_fifo_full_vc0; + txfifofullvc1_tmp <= ht_out_tx_fifo_full_vc1; + txfifordpvc0_tmp <= ht_out_tx_fifo_rdp_vc0; + txfifordpvc1_tmp <= ht_out_tx_fifo_rdp_vc1; + txfifowrpvc0_tmp <= ht_out_tx_fifo_wrp_vc0; + txfifowrpvc1_tmp <= ht_out_tx_fifo_wrp_vc1; + txmargin_tmp(2 DOWNTO 0) <= ht_out_tx_margin0; + txmargin_tmp(5 DOWNTO 3) <= ht_out_tx_margin1; + txmargin_tmp(8 DOWNTO 6) <= ht_out_tx_margin2; + txmargin_tmp(11 DOWNTO 9) <= ht_out_tx_margin3; + txmargin_tmp(14 DOWNTO 12) <= ht_out_tx_margin4; + txmargin_tmp(17 DOWNTO 15) <= ht_out_tx_margin5; + txmargin_tmp(20 DOWNTO 18) <= ht_out_tx_margin6; + txmargin_tmp(23 DOWNTO 21) <= ht_out_tx_margin7; + txreadyvc0_tmp <= ht_out_tx_ready_vc0; + txreadyvc1_tmp <= ht_out_tx_ready_vc1; + txcompl_tmp(0) <= ht_out_txcompl0; + txcompl_tmp(1) <= ht_out_txcompl1; + txcompl_tmp(2) <= ht_out_txcompl2; + txcompl_tmp(3) <= ht_out_txcompl3; + txcompl_tmp(4) <= ht_out_txcompl4; + txcompl_tmp(5) <= ht_out_txcompl5; + txcompl_tmp(6) <= ht_out_txcompl6; + txcompl_tmp(7) <= ht_out_txcompl7; + txdata_tmp(7 DOWNTO 0) <= ht_out_txdata0; + txdata_tmp(15 DOWNTO 8) <= ht_out_txdata1; + txdata_tmp(23 DOWNTO 16) <= ht_out_txdata2; + txdata_tmp(31 DOWNTO 24) <= ht_out_txdata3; + txdata_tmp(39 DOWNTO 32) <= ht_out_txdata4; + txdata_tmp(47 DOWNTO 40) <= ht_out_txdata5; + txdata_tmp(55 DOWNTO 48) <= ht_out_txdata6; + txdata_tmp(63 DOWNTO 56) <= ht_out_txdata7; + txdatak_tmp(0) <= ht_out_txdatak0; + txdatak_tmp(1) <= ht_out_txdatak1; + txdatak_tmp(2) <= ht_out_txdatak2; + txdatak_tmp(3) <= ht_out_txdatak3; + txdatak_tmp(4) <= ht_out_txdatak4; + txdatak_tmp(5) <= ht_out_txdatak5; + txdatak_tmp(6) <= ht_out_txdatak6; + txdatak_tmp(7) <= ht_out_txdatak7; + txdetectrx_tmp(0) <= ht_out_txdetectrx0; + txdetectrx_tmp(1) <= ht_out_txdetectrx1; + txdetectrx_tmp(2) <= ht_out_txdetectrx2; + txdetectrx_tmp(3) <= ht_out_txdetectrx3; + txdetectrx_tmp(4) <= ht_out_txdetectrx4; + txdetectrx_tmp(5) <= ht_out_txdetectrx5; + txdetectrx_tmp(6) <= ht_out_txdetectrx6; + txdetectrx_tmp(7) <= ht_out_txdetectrx7; + txelecidle_tmp(0) <= ht_out_txelecidle0; + txelecidle_tmp(1) <= ht_out_txelecidle1; + txelecidle_tmp(2) <= ht_out_txelecidle2; + txelecidle_tmp(3) <= ht_out_txelecidle3; + txelecidle_tmp(4) <= ht_out_txelecidle4; + txelecidle_tmp(5) <= ht_out_txelecidle5; + txelecidle_tmp(6) <= ht_out_txelecidle6; + txelecidle_tmp(7) <= ht_out_txelecidle7; + wakeoen_tmp <= ht_out_wake_oen; + + --/////////////////////////////////////////////////////////////////////////// + -- RTL Instantiation------------- -----------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + + + m_ht : cycloneiv_pciehip_hip_top + PORT MAP ( + + -- input port section ------------------------------------------------- + bist_scanen => ht_in_bist_scanen, + bist_scanin => ht_in_bist_scanin, + bist_testen => ht_in_bist_testen, + bisten_rcv0 => ht_in_bisten_rcv0, + bisten_rcv1 => ht_in_bisten_rcv1, + bisten_rpl => ht_in_bisten_rpl, + core_clk_in => ht_in_core_clk_in, + core_crst => ht_in_core_crst, + core_por => ht_in_core_por, + core_rst => ht_in_core_rst, + core_srst => ht_in_core_srst, + cpl_err => ht_in_cpl_err, + cpl_pending => ht_in_cpl_pending, + dbg_pipex1_rx => ht_in_dbg_pipex1_rx, + dev_addr => ht_in_dev_addr, + dl_aspm_cr0 => ht_in_dl_aspm_cr0, --ww7.2 + dl_comclk_reg => ht_in_dl_comclk_reg, --ww7.2 + dl_ctrl_link2 => ht_in_dl_ctrl_link2, + dl_data_upfc => ht_in_dl_data_upfc, + dl_hdr_upfc => ht_in_dl_hdr_upfc, + dl_inh_dllp => ht_in_dl_inh_dllp, + dl_maxpload_dcr => ht_in_dl_maxpload_dcr, + dl_req_phycfg => ht_in_dl_req_phycfg, + dl_req_phypm => ht_in_dl_req_phypm, + dl_req_upfc => ht_in_dl_req_upfc, + dl_req_wake => ht_in_dl_req_wake, + dl_rx_ecrcchk => ht_in_dl_rx_ecrcchk, + dl_snd_upfc => ht_in_dl_snd_upfc, + dl_tx_req_pm => ht_in_dl_tx_req_pm, + dl_tx_typ_pm => ht_in_dl_tx_typ_pm, + dl_txcfg_extsy => ht_in_dl_txcfg_extsy, + dl_typ_upfc => ht_in_dl_typ_upfc, + dl_vc_ctrl => ht_in_dl_vc_ctrl, + dl_vcid_map => ht_in_dl_vcid_map, + dl_vcid_upfc => ht_in_dl_vcid_upfc, + entest => ht_in_entest, + hip_extraclkin => ht_in_hip_extraclkin, --ww7.2 + hip_extrain => ht_in_hip_extrain, --ww7.2 + frzlogic => ht_in_frzlogic, + frzreg => ht_in_frzreg, + hip_base_addr => ht_in_hip_base_addr, + id_rcv0 => ht_in_id_rcv0, + id_rcv1 => ht_in_id_rcv1, + id_rpl => ht_in_id_rpl, + lmi_addr => ht_in_lmi_addr, + lmi_din => ht_in_lmi_din, + lmi_rden => ht_in_lmi_rden, + lmi_wren => ht_in_lmi_wren, + mdc => ht_in_mdc, + mdio_dis => ht_in_mdio_dis, + mdio_in => ht_in_mdio_in, + mode => ht_in_mode, + mram_hip_test_enable => ht_in_mram_hip_test_enable, --ww7.2 + mram_red_enscan => ht_in_mram_red_enscan, --ww7.2 + mram_red_scen => ht_in_mram_red_scen, + mram_red_scin => ht_in_mram_red_scin, + mram_red_sclk => ht_in_mram_red_sclk, + mram_red_scrst => ht_in_mram_red_scrst, + mram_red_scsel => ht_in_mram_red_scsel, + mram_regscanen => ht_in_mram_regscanen, + mram_regscanin => ht_in_mram_regscanin, + nfrzdrv => ht_in_nfrzdrv, + npor => ht_in_npor, + pclk_central => ht_in_pclk_central, + pclk_ch0 => ht_in_pclk_ch0, + phy_rst => ht_in_phy_rst, + phy_srst => ht_in_phy_srst, + phystatus0 => ht_in_phystatus0, + phystatus1 => ht_in_phystatus1, + phystatus2 => ht_in_phystatus2, + phystatus3 => ht_in_phystatus3, + phystatus4 => ht_in_phystatus4, + phystatus5 => ht_in_phystatus5, + phystatus6 => ht_in_phystatus6, + phystatus7 => ht_in_phystatus7, + pld_clk => ht_in_pld_clk, + pld_rst => ht_in_pld_rst, + pld_srst => ht_in_pld_srst, + pll_fixed_clk => ht_in_pll_fixed_clk, + plniotri => ht_in_plniotri, + port_addr => ht_in_port_addr, + rx_mask_vc0 => ht_in_rx_mask_vc0, + rx_mask_vc1 => ht_in_rx_mask_vc1, + rx_ready_vc0 => ht_in_rx_ready_vc0, + rx_ready_vc1 => ht_in_rx_ready_vc1, + rxdata0 => ht_in_rxdata0, + rxdata1 => ht_in_rxdata1, + rxdata2 => ht_in_rxdata2, + rxdata3 => ht_in_rxdata3, + rxdata4 => ht_in_rxdata4, + rxdata5 => ht_in_rxdata5, + rxdata6 => ht_in_rxdata6, + rxdata7 => ht_in_rxdata7, + rxdatak0 => ht_in_rxdatak0, + rxdatak1 => ht_in_rxdatak1, + rxdatak2 => ht_in_rxdatak2, + rxdatak3 => ht_in_rxdatak3, + rxdatak4 => ht_in_rxdatak4, + rxdatak5 => ht_in_rxdatak5, + rxdatak6 => ht_in_rxdatak6, + rxdatak7 => ht_in_rxdatak7, + rxelecidle0 => ht_in_rxelecidle0, + rxelecidle1 => ht_in_rxelecidle1, + rxelecidle2 => ht_in_rxelecidle2, + rxelecidle3 => ht_in_rxelecidle3, + rxelecidle4 => ht_in_rxelecidle4, + rxelecidle5 => ht_in_rxelecidle5, + rxelecidle6 => ht_in_rxelecidle6, + rxelecidle7 => ht_in_rxelecidle7, + rxstatus0 => ht_in_rxstatus0, + rxstatus1 => ht_in_rxstatus1, + rxstatus2 => ht_in_rxstatus2, + rxstatus3 => ht_in_rxstatus3, + rxstatus4 => ht_in_rxstatus4, + rxstatus5 => ht_in_rxstatus5, + rxstatus6 => ht_in_rxstatus6, + rxstatus7 => ht_in_rxstatus7, + rxvalid0 => ht_in_rxvalid0, + rxvalid1 => ht_in_rxvalid1, + rxvalid2 => ht_in_rxvalid2, + rxvalid3 => ht_in_rxvalid3, + rxvalid4 => ht_in_rxvalid4, + rxvalid5 => ht_in_rxvalid5, + rxvalid6 => ht_in_rxvalid6, + rxvalid7 => ht_in_rxvalid7, + scan_en => ht_in_scan_en, + scan_mode_n => ht_in_scan_mode_n, + ser_shift_load => ht_in_ser_shift_load, + swdn_in => ht_in_swdn_in, + swup_in => ht_in_swup_in, + test_in_hip => ht_in_test_in_hip, + tl_aer_msi_num => ht_in_tl_aer_msi_num, + tl_app_inta_sts => ht_in_tl_app_inta_sts, + tl_app_msi_num => ht_in_tl_app_msi_num, + tl_app_msi_req => ht_in_tl_app_msi_req, + tl_app_msi_tc => ht_in_tl_app_msi_tc, + tl_hpg_ctrler => ht_in_tl_hpg_ctrler, + tl_pex_msi_num => ht_in_tl_pex_msi_num, + tl_pm_auxpwr => ht_in_tl_pm_auxpwr, + tl_pm_data => ht_in_tl_pm_data, + tl_pm_event => ht_in_tl_pm_event, + tl_pme_to_cr => ht_in_tl_pme_to_cr, + tl_slotclk_cfg => ht_in_tl_slotclk_cfg, + tx_data_vc0_0 => ht_in_tx_data_vc0_0, + tx_data_vc0_1 => ht_in_tx_data_vc0_1, + tx_data_vc1_0 => ht_in_tx_data_vc1_0, + tx_data_vc1_1 => ht_in_tx_data_vc1_1, + tx_eop_vc0_0 => ht_in_tx_eop_vc0_0, + tx_eop_vc0_1 => ht_in_tx_eop_vc0_1, + tx_eop_vc1_0 => ht_in_tx_eop_vc1_0, + tx_eop_vc1_1 => ht_in_tx_eop_vc1_1, + tx_err_vc0 => ht_in_tx_err_vc0, + tx_err_vc1 => ht_in_tx_err_vc1, + tx_sop_vc0_0 => ht_in_tx_sop_vc0_0, + tx_sop_vc0_1 => ht_in_tx_sop_vc0_1, + tx_sop_vc1_0 => ht_in_tx_sop_vc1_0, + tx_sop_vc1_1 => ht_in_tx_sop_vc1_1, + tx_valid_vc0 => ht_in_tx_valid_vc0, + tx_valid_vc1 => ht_in_tx_valid_vc1, + + --output port section ------------------------------------------------- + bist_donea_rcv0 => ht_out_bist_donea_rcv0, + bist_donea_rcv1 => ht_out_bist_donea_rcv1, + bist_donea_rpl => ht_out_bist_donea_rpl, + bist_doneb_rcv0 => ht_out_bist_doneb_rcv0, + bist_doneb_rcv1 => ht_out_bist_doneb_rcv1, + bist_doneb_rpl => ht_out_bist_doneb_rpl, + bist_pass_rcv0 => ht_out_bist_pass_rcv0, + bist_pass_rcv1 => ht_out_bist_pass_rcv1, + bist_pass_rpl => ht_out_bist_pass_rpl, + bist_scanout_rcv0 => ht_out_bist_scanout_rcv0, + bist_scanout_rcv1 => ht_out_bist_scanout_rcv1, + bist_scanout_rpl => ht_out_bist_scanout_rpl, + clr_rxpath => ht_out_clr_rxpath, + core_clk_out => ht_out_core_clk_out, + data_enable_n => ht_out_data_enable_n, + derr_cor_ext_rcv0 => ht_out_derr_cor_ext_rcv0, + derr_cor_ext_rcv1 => ht_out_derr_cor_ext_rcv1, + derr_cor_ext_rpl => ht_out_derr_cor_ext_rpl, + derr_rpl => ht_out_derr_rpl, + dl_ack_phypm => ht_out_dl_ack_phypm, + dl_ack_req_upfc => ht_out_dl_ack_req_upfc, + dl_ack_snd_upfc => ht_out_dl_ack_snd_upfc, + dl_current_deemp => ht_out_dl_current_deemp, + dl_current_speed => ht_out_dl_current_speed, + dl_dll_req => ht_out_dl_dll_req, + dl_err_dll => ht_out_dl_err_dll, + dl_err_phy => ht_out_dl_err_phy, + dl_link_auto_bdw_status => ht_out_dl_link_auto_bdw_status, + dl_link_bdw_mng_status => ht_out_dl_link_bdw_mng_status, + dl_ltssm => ht_out_dl_ltssm, + dl_rpbuf_emp => ht_out_dl_rpbuf_emp, + dl_rst_enter_comp_bit => ht_out_dl_rst_enter_comp_bit, + dl_rst_tx_margin_field => ht_out_dl_rst_tx_margin_field, + dl_rx_typ_pm => ht_out_dl_rx_typ_pm, + dl_rx_val_pm => ht_out_dl_rx_val_pm, + dl_tx_ack_pm => ht_out_dl_tx_ack_pm, + dl_up => ht_out_dl_up, + dl_vc_status => ht_out_dl_vc_status, + dlup_exit => ht_out_dlup_exit, + dprio_curr_state => ht_out_dprio_curr_state, + eidle_infer_sel0 => ht_out_eidle_infer_sel0, + eidle_infer_sel1 => ht_out_eidle_infer_sel1, + eidle_infer_sel2 => ht_out_eidle_infer_sel2, + eidle_infer_sel3 => ht_out_eidle_infer_sel3, + eidle_infer_sel4 => ht_out_eidle_infer_sel4, + eidle_infer_sel5 => ht_out_eidle_infer_sel5, + eidle_infer_sel6 => ht_out_eidle_infer_sel6, + eidle_infer_sel7 => ht_out_eidle_infer_sel7, + ev_128ns => ht_out_ev_128ns, + ev_1us => ht_out_ev_1us, + hip_extraclkout => ht_out_hip_extraclkout, --ww7.2 + hip_extraout => ht_out_hip_extraout, --ww7.2 + hotrst_exit => ht_out_hotrst_exit, + int_status => ht_out_int_status, + l2_exit => ht_out_l2_exit, + lane_act => ht_out_lane_act, + link_up => ht_out_link_up, + lmi_ack => ht_out_lmi_ack, + lmi_dout => ht_out_lmi_dout, + ltssm_l0_state => ht_out_ltssm_l0_state, --ww7.2 + mdio_out => ht_out_mdio_out, + mram_red_scout => ht_out_mram_red_scout, + mram_regscanout => ht_out_mram_regscanout, + powerdown0 => ht_out_powerdown0, + powerdown1 => ht_out_powerdown1, + powerdown2 => ht_out_powerdown2, + powerdown3 => ht_out_powerdown3, + powerdown4 => ht_out_powerdown4, + powerdown5 => ht_out_powerdown5, + powerdown6 => ht_out_powerdown6, + powerdown7 => ht_out_powerdown7, + rate => ht_out_rate, + rate_tied_to_gnd => ht_out_rate_tied_to_gnd, --ww7.2 + reset_status => ht_out_reset_status, + rx_bar_dec_vc0 => ht_out_rx_bar_dec_vc0, + rx_bar_dec_vc1 => ht_out_rx_bar_dec_vc1, + rx_be_vc0_0 => ht_out_rx_be_vc0_0, + rx_be_vc0_1 => ht_out_rx_be_vc0_1, + rx_be_vc1_0 => ht_out_rx_be_vc1_0, + rx_be_vc1_1 => ht_out_rx_be_vc1_1, + rx_data_vc0_0 => ht_out_rx_data_vc0_0, + rx_data_vc0_1 => ht_out_rx_data_vc0_1, + rx_data_vc1_0 => ht_out_rx_data_vc1_0, + rx_data_vc1_1 => ht_out_rx_data_vc1_1, + rx_eop_vc0_0 => ht_out_rx_eop_vc0_0, + rx_eop_vc0_1 => ht_out_rx_eop_vc0_1, + rx_eop_vc1_0 => ht_out_rx_eop_vc1_0, + rx_eop_vc1_1 => ht_out_rx_eop_vc1_1, + rx_err_vc0 => ht_out_rx_err_vc0, + rx_err_vc1 => ht_out_rx_err_vc1, + rx_fifo_empty_vc0 => ht_out_rx_fifo_empty_vc0, + rx_fifo_empty_vc1 => ht_out_rx_fifo_empty_vc1, + rx_fifo_full_vc0 => ht_out_rx_fifo_full_vc0, + rx_fifo_full_vc1 => ht_out_rx_fifo_full_vc1, + rx_fifo_rdp_vc0 => ht_out_rx_fifo_rdp_vc0, + rx_fifo_rdp_vc1 => ht_out_rx_fifo_rdp_vc1, + rx_fifo_wrp_vc0 => ht_out_rx_fifo_wrp_vc0, + rx_fifo_wrp_vc1 => ht_out_rx_fifo_wrp_vc1, + rx_sop_vc0_0 => ht_out_rx_sop_vc0_0, + rx_sop_vc0_1 => ht_out_rx_sop_vc0_1, + rx_sop_vc1_0 => ht_out_rx_sop_vc1_0, + rx_sop_vc1_1 => ht_out_rx_sop_vc1_1, + rx_valid_vc0 => ht_out_rx_valid_vc0, + rx_valid_vc1 => ht_out_rx_valid_vc1, + rxpolarity0 => ht_out_rxpolarity0, + rxpolarity1 => ht_out_rxpolarity1, + rxpolarity2 => ht_out_rxpolarity2, + rxpolarity3 => ht_out_rxpolarity3, + rxpolarity4 => ht_out_rxpolarity4, + rxpolarity5 => ht_out_rxpolarity5, + rxpolarity6 => ht_out_rxpolarity6, + rxpolarity7 => ht_out_rxpolarity7, + serr_out => ht_out_serr_out, + swdn_wake => ht_out_swdn_wake, + swup_hotrst => ht_out_swup_hotrst, + test_out_hip => ht_out_test_out_hip, + tl_app_inta_ack => ht_out_tl_app_inta_ack, + tl_app_msi_ack => ht_out_tl_app_msi_ack, + tl_cfg_add => ht_out_tl_cfg_add, + tl_cfg_ctl => ht_out_tl_cfg_ctl, + tl_cfg_ctl_wr => ht_out_tl_cfg_ctl_wr, + tl_cfg_sts => ht_out_tl_cfg_sts, + tl_cfg_sts_wr => ht_out_tl_cfg_sts_wr, + tl_pme_to_sr => ht_out_tl_pme_to_sr, + tx_cred_vc0 => ht_out_tx_cred_vc0, + tx_cred_vc1 => ht_out_tx_cred_vc1, + tx_deemph0 => ht_out_tx_deemph0, + tx_deemph1 => ht_out_tx_deemph1, + tx_deemph2 => ht_out_tx_deemph2, + tx_deemph3 => ht_out_tx_deemph3, + tx_deemph4 => ht_out_tx_deemph4, + tx_deemph5 => ht_out_tx_deemph5, + tx_deemph6 => ht_out_tx_deemph6, + tx_deemph7 => ht_out_tx_deemph7, + tx_fifo_empty_vc0 => ht_out_tx_fifo_empty_vc0, + tx_fifo_empty_vc1 => ht_out_tx_fifo_empty_vc1, + tx_fifo_full_vc0 => ht_out_tx_fifo_full_vc0, + tx_fifo_full_vc1 => ht_out_tx_fifo_full_vc1, + tx_fifo_rdp_vc0 => ht_out_tx_fifo_rdp_vc0, + tx_fifo_rdp_vc1 => ht_out_tx_fifo_rdp_vc1, + tx_fifo_wrp_vc0 => ht_out_tx_fifo_wrp_vc0, + tx_fifo_wrp_vc1 => ht_out_tx_fifo_wrp_vc1, + tx_margin0 => ht_out_tx_margin0, + tx_margin1 => ht_out_tx_margin1, + tx_margin2 => ht_out_tx_margin2, + tx_margin3 => ht_out_tx_margin3, + tx_margin4 => ht_out_tx_margin4, + tx_margin5 => ht_out_tx_margin5, + tx_margin6 => ht_out_tx_margin6, + tx_margin7 => ht_out_tx_margin7, + tx_ready_vc0 => ht_out_tx_ready_vc0, + tx_ready_vc1 => ht_out_tx_ready_vc1, + txcompl0 => ht_out_txcompl0, + txcompl1 => ht_out_txcompl1, + txcompl2 => ht_out_txcompl2, + txcompl3 => ht_out_txcompl3, + txcompl4 => ht_out_txcompl4, + txcompl5 => ht_out_txcompl5, + txcompl6 => ht_out_txcompl6, + txcompl7 => ht_out_txcompl7, + txdata0 => ht_out_txdata0, + txdata1 => ht_out_txdata1, + txdata2 => ht_out_txdata2, + txdata3 => ht_out_txdata3, + txdata4 => ht_out_txdata4, + txdata5 => ht_out_txdata5, + txdata6 => ht_out_txdata6, + txdata7 => ht_out_txdata7, + txdatak0 => ht_out_txdatak0, + txdatak1 => ht_out_txdatak1, + txdatak2 => ht_out_txdatak2, + txdatak3 => ht_out_txdatak3, + txdatak4 => ht_out_txdatak4, + txdatak5 => ht_out_txdatak5, + txdatak6 => ht_out_txdatak6, + txdatak7 => ht_out_txdatak7, + txdetectrx0 => ht_out_txdetectrx0, + txdetectrx1 => ht_out_txdetectrx1, + txdetectrx2 => ht_out_txdetectrx2, + txdetectrx3 => ht_out_txdetectrx3, + txdetectrx4 => ht_out_txdetectrx4, + txdetectrx5 => ht_out_txdetectrx5, + txdetectrx6 => ht_out_txdetectrx6, + txdetectrx7 => ht_out_txdetectrx7, + txelecidle0 => ht_out_txelecidle0, + txelecidle1 => ht_out_txelecidle1, + txelecidle2 => ht_out_txelecidle2, + txelecidle3 => ht_out_txelecidle3, + txelecidle4 => ht_out_txelecidle4, + txelecidle5 => ht_out_txelecidle5, + txelecidle6 => ht_out_txelecidle6, + txelecidle7 => ht_out_txelecidle7, + wake_oen => ht_out_wake_oen, + + -- cram section ------------------------------------------------------- + csr_hip_in_reserved => init_hip_in(1759 DOWNTO 1632), -- not used + csr_hip_in => init_hip_in(1631 DOWNTO 0) + ); + -- end of hip_top instantiation + + --/////////////////////////////////////////////////////////////////////////// + -- non-kits parameters ---------------- -----------------------------------// + --/////////////////////////////////////////////////////////////////////////// + PROCESS + BEGIN + init_deviceaddress <= int2bin(device_address, 5); + init_hipbaseaddress <= int2bin(base_address, 8); + init_portaddress <= int2bin(port_address, 5); + WAIT; + END PROCESS; + + + deviceaddress_in <= init_deviceaddress; + hipbaseaddress_in <= init_hipbaseaddress; + portaddress_in <= init_portaddress; + + --/////////////////////////////////////////////////////////////////////////// + -- Parameter Process Submodule Instantiation -----------------------------// + --/////////////////////////////////////////////////////////////////////////// + + test_in <= mode(1); + + m_param : cycloneiv_pciehip_param + GENERIC MAP ( + advanced_errors => advanced_errors, + allow_rx_valid_empty => allow_rx_valid_empty, + bar0_64bit_mem_space => bar0_64bit_mem_space, + bar0_io_space => bar0_io_space, + bar0_prefetchable => bar0_prefetchable, + bar0_size_mask => bar0_size_mask, + bar1_64bit_mem_space => bar1_64bit_mem_space, + bar1_io_space => bar1_io_space, + bar1_prefetchable => bar1_prefetchable, + bar1_size_mask => bar1_size_mask, + bar2_64bit_mem_space => bar2_64bit_mem_space, + bar2_io_space => bar2_io_space, + bar2_prefetchable => bar2_prefetchable, + bar2_size_mask => bar2_size_mask, + bar3_64bit_mem_space => bar3_64bit_mem_space, + bar3_io_space => bar3_io_space, + bar3_prefetchable => bar3_prefetchable, + bar3_size_mask => bar3_size_mask, + bar4_64bit_mem_space => bar4_64bit_mem_space, + bar4_io_space => bar4_io_space, + bar4_prefetchable => bar4_prefetchable, + bar4_size_mask => bar4_size_mask, + bar5_64bit_mem_space => bar5_64bit_mem_space, + bar5_io_space => bar5_io_space, + bar5_prefetchable => bar5_prefetchable, + bar5_size_mask => bar5_size_mask, + bar_io_window_size => bar_io_window_size, + bar_prefetchable => bar_prefetchable, + base_address => base_address, + bridge_port_ssid_support => bridge_port_ssid_support, + bridge_port_vga_enable => bridge_port_vga_enable, + bypass_cdc => bypass_cdc, + bypass_tl => bypass_tl, + class_code => class_code, + completion_timeout => completion_timeout, + core_clk_divider => core_clk_divider, + core_clk_source => core_clk_source, + credit_buffer_allocation_aux => credit_buffer_allocation_aux, + deemphasis_enable => deemphasis_enable, + device_address => device_address, + device_id => device_id, + device_number => device_number, + diffclock_nfts_count => diffclock_nfts_count, + disable_async_l2_logic => disable_async_l2_logic, + disable_cdc_clk_ppm => disable_cdc_clk_ppm, + disable_link_x2_support => disable_link_x2_support, + disable_snoop_packet => disable_snoop_packet, + dll_active_report_support => dll_active_report_support, + ei_delay_powerdown_count => ei_delay_powerdown_count, + eie_before_nfts_count => eie_before_nfts_count, + enable_adapter_half_rate_mode => enable_adapter_half_rate_mode, + enable_ch0_pclk_out => enable_ch0_pclk_out, + enable_completion_timeout_disable => enable_completion_timeout_disable, + enable_coreclk_out_half_rate => enable_coreclk_out_half_rate, + enable_ecrc_check => enable_ecrc_check, + enable_ecrc_gen => enable_ecrc_gen, + enable_function_msi_support => enable_function_msi_support, + enable_function_msix_support => enable_function_msix_support, + enable_gen2_core => enable_gen2_core, + enable_hip_x1_loopback => enable_hip_x1_loopback, + enable_l1_aspm => enable_l1_aspm, + enable_msi_64bit_addressing => enable_msi_64bit_addressing, + enable_msi_masking => enable_msi_masking, + enable_rcv0buf_a_we => enable_rcv0buf_a_we, + enable_rcv0buf_b_re => enable_rcv0buf_b_re, + enable_rcv0buf_output_regs => enable_rcv0buf_output_regs, + enable_rcv1buf_a_we => enable_rcv1buf_a_we, + enable_rcv1buf_b_re => enable_rcv1buf_b_re, + enable_rcv1buf_output_regs => enable_rcv1buf_output_regs, + enable_retrybuf_a_we => enable_retrybuf_a_we, + enable_retrybuf_b_re => enable_retrybuf_b_re, + enable_retrybuf_ecc => enable_retrybuf_ecc, + enable_retrybuf_output_regs => enable_retrybuf_output_regs, + enable_retrybuf_x8_clk_stealing => enable_retrybuf_x8_clk_stealing, + enable_rx0buf_ecc => enable_rx0buf_ecc, + enable_rx0buf_x8_clk_stealing => enable_rx0buf_x8_clk_stealing, + enable_rx1buf_ecc => enable_rx1buf_ecc, + enable_rx1buf_x8_clk_stealing => enable_rx1buf_x8_clk_stealing, + enable_rx_buffer_checking => enable_rx_buffer_checking, + enable_rx_ei_l0s_exit_refined => enable_rx_ei_l0s_exit_refined, + enable_rx_reordering => enable_rx_reordering, + enable_slot_register => enable_slot_register, + endpoint_l0_latency => endpoint_l0_latency, + endpoint_l1_latency => endpoint_l1_latency, + expansion_base_address_register => expansion_base_address_register, + extend_tag_field => extend_tag_field, + fc_init_timer => fc_init_timer, + flow_control_timeout_count => flow_control_timeout_count, + flow_control_update_count => flow_control_update_count, + gen2_diffclock_nfts_count => gen2_diffclock_nfts_count, + gen2_lane_rate_mode => gen2_lane_rate_mode, + gen2_sameclock_nfts_count => gen2_sameclock_nfts_count, + hot_plug_support => hot_plug_support, + iei_logic => iei_logic, + indicator => indicator, + l01_entry_latency => l01_entry_latency, + l0_exit_latency_diffclock => l0_exit_latency_diffclock, + l0_exit_latency_sameclock => l0_exit_latency_sameclock, + l1_exit_latency_diffclock => l1_exit_latency_diffclock, + l1_exit_latency_sameclock => l1_exit_latency_sameclock, + lane_mask => lane_mask, + low_priority_vc => low_priority_vc, + max_link_width => max_link_width, + max_payload_size => max_payload_size, + maximum_current => maximum_current, + migrated_from_prev_family => migrated_from_prev_family, + millisecond_cycle_count => millisecond_cycle_count, + mram_bist_settings => mram_bist_settings, + msi_function_count => msi_function_count, + msix_pba_bir => msix_pba_bir, + msix_pba_offset => msix_pba_offset, + msix_table_bir => msix_table_bir, + msix_table_offset => msix_table_offset, + msix_table_size => msix_table_size, + no_command_completed => no_command_completed, + no_soft_reset => no_soft_reset, + pcie_mode => pcie_mode, + pme_state_enable => pme_state_enable, + port_address => port_address, + port_link_number => port_link_number, + register_pipe_signals => register_pipe_signals, + retry_buffer_last_active_address => retry_buffer_last_active_address, + retry_buffer_memory_settings => retry_buffer_memory_settings, + revision_id => revision_id, + rx0_adap_fifo_full_value => rx0_adap_fifo_full_value, + rx1_adap_fifo_full_value => rx1_adap_fifo_full_value, + rx_cdc_full_value => rx_cdc_full_value, + rx_idl_os_count => rx_idl_os_count, + rx_ptr0_nonposted_dpram_max => rx_ptr0_nonposted_dpram_max, + rx_ptr0_nonposted_dpram_min => rx_ptr0_nonposted_dpram_min, + rx_ptr0_posted_dpram_max => rx_ptr0_posted_dpram_max, + rx_ptr0_posted_dpram_min => rx_ptr0_posted_dpram_min, + rx_ptr1_nonposted_dpram_max => rx_ptr1_nonposted_dpram_max, + rx_ptr1_nonposted_dpram_min => rx_ptr1_nonposted_dpram_min, + rx_ptr1_posted_dpram_max => rx_ptr1_posted_dpram_max, + rx_ptr1_posted_dpram_min => rx_ptr1_posted_dpram_min, + sameclock_nfts_count => sameclock_nfts_count, + single_rx_detect => single_rx_detect, + skp_os_schedule_count => skp_os_schedule_count, + slot_number => slot_number, + slot_power_limit => slot_power_limit, + slot_power_scale => slot_power_scale, + ssid => ssid, + ssvid => ssvid, + subsystem_device_id => subsystem_device_id, + subsystem_vendor_id => subsystem_vendor_id, + surprise_down_error_support => surprise_down_error_support, + tx0_adap_fifo_full_value => tx0_adap_fifo_full_value, + tx1_adap_fifo_full_value => tx1_adap_fifo_full_value, + tx_cdc_full_value => tx_cdc_full_value, + tx_cdc_stop_dummy_full_value => tx_cdc_stop_dummy_full_value, + use_crc_forwarding => use_crc_forwarding, + vc0_clk_enable => vc0_clk_enable, + vc0_rx_buffer_memory_settings => vc0_rx_buffer_memory_settings, + vc0_rx_flow_ctrl_compl_data => vc0_rx_flow_ctrl_compl_data, + vc0_rx_flow_ctrl_compl_header => vc0_rx_flow_ctrl_compl_header, + vc0_rx_flow_ctrl_nonposted_data => vc0_rx_flow_ctrl_nonposted_data, + vc0_rx_flow_ctrl_nonposted_header => vc0_rx_flow_ctrl_nonposted_header, + vc0_rx_flow_ctrl_posted_data => vc0_rx_flow_ctrl_posted_data, + vc0_rx_flow_ctrl_posted_header => vc0_rx_flow_ctrl_posted_header, + vc1_clk_enable => vc1_clk_enable, + vc1_rx_buffer_memory_settings => vc1_rx_buffer_memory_settings, + vc1_rx_flow_ctrl_compl_data => vc1_rx_flow_ctrl_compl_data, + vc1_rx_flow_ctrl_compl_header => vc1_rx_flow_ctrl_compl_header, + vc1_rx_flow_ctrl_nonposted_data => vc1_rx_flow_ctrl_nonposted_data, + vc1_rx_flow_ctrl_nonposted_header => vc1_rx_flow_ctrl_nonposted_header, + vc1_rx_flow_ctrl_posted_data => vc1_rx_flow_ctrl_posted_data, + vc1_rx_flow_ctrl_posted_header => vc1_rx_flow_ctrl_posted_header, + vc_arbitration => vc_arbitration, + vc_enable => vc_enable, + vendor_id => vendor_id + ) + PORT MAP ( + test_in => test_in, + csr_hip_in => init_hip_in + ); + + ------------------------ + -- Wire Delay Block -- + ------------------------ + WireDelay : BLOCK + BEGIN + VitalWireDelay (bistenrcv0_ipd, bistenrcv0_in, tipd_bistenrcv0); + VitalWireDelay (bistenrcv1_ipd, bistenrcv1_in, tipd_bistenrcv1); + VitalWireDelay (bistenrpl_ipd, bistenrpl_in, tipd_bistenrpl); + VitalWireDelay (bistscanen_ipd, bistscanen_in, tipd_bistscanen); + VitalWireDelay (bistscanin_ipd, bistscanin_in, tipd_bistscanin); + VitalWireDelay (bisttesten_ipd, bisttesten_in, tipd_bisttesten); + VitalWireDelay (coreclkin_ipd, coreclkin_in, tipd_coreclkin); + VitalWireDelay (corecrst_ipd, corecrst_in, tipd_corecrst); + VitalWireDelay (corepor_ipd, corepor_in, tipd_corepor); + VitalWireDelay (corerst_ipd, corerst_in, tipd_corerst); + VitalWireDelay (coresrst_ipd, coresrst_in, tipd_coresrst); + loopbits_cplerr : FOR i in cplerr_in'RANGE GENERATE + VitalWireDelay (cplerr_ipd(i), cplerr_in(i), tipd_cplerr(i)); + END GENERATE; + VitalWireDelay (cplpending_ipd, cplpending_in, tipd_cplpending); + loopbits_dbgpipex1rx : FOR i in dbgpipex1rx_in'RANGE GENERATE + VitalWireDelay (dbgpipex1rx_ipd(i), dbgpipex1rx_in(i), tipd_dbgpipex1rx(i)); + END GENERATE; + VitalWireDelay (dlaspmcr0_ipd, dlaspmcr0_in, tipd_dlaspmcr0); + VitalWireDelay (dlcomclkreg_ipd, dlcomclkreg_in, tipd_dlcomclkreg); + loopbits_dlctrllink2 : FOR i in dlctrllink2_in'RANGE GENERATE + VitalWireDelay (dlctrllink2_ipd(i), dlctrllink2_in(i), tipd_dlctrllink2(i)); + END GENERATE; + loopbits_dldataupfc : FOR i in dldataupfc_in'RANGE GENERATE + VitalWireDelay (dldataupfc_ipd(i), dldataupfc_in(i), tipd_dldataupfc(i)); + END GENERATE; + loopbits_dlhdrupfc : FOR i in dlhdrupfc_in'RANGE GENERATE + VitalWireDelay (dlhdrupfc_ipd(i), dlhdrupfc_in(i), tipd_dlhdrupfc(i)); + END GENERATE; + VitalWireDelay (dlinhdllp_ipd, dlinhdllp_in, tipd_dlinhdllp); + loopbits_dlmaxploaddcr : FOR i in dlmaxploaddcr_in'RANGE GENERATE + VitalWireDelay (dlmaxploaddcr_ipd(i), dlmaxploaddcr_in(i), tipd_dlmaxploaddcr(i)); + END GENERATE; + loopbits_dlreqphycfg : FOR i in dlreqphycfg_in'RANGE GENERATE + VitalWireDelay (dlreqphycfg_ipd(i), dlreqphycfg_in(i), tipd_dlreqphycfg(i)); + END GENERATE; + loopbits_dlreqphypm : FOR i in dlreqphypm_in'RANGE GENERATE + VitalWireDelay (dlreqphypm_ipd(i), dlreqphypm_in(i), tipd_dlreqphypm(i)); + END GENERATE; + VitalWireDelay (dlrequpfc_ipd, dlrequpfc_in, tipd_dlrequpfc); + VitalWireDelay (dlreqwake_ipd, dlreqwake_in, tipd_dlreqwake); + VitalWireDelay (dlrxecrcchk_ipd, dlrxecrcchk_in, tipd_dlrxecrcchk); + VitalWireDelay (dlsndupfc_ipd, dlsndupfc_in, tipd_dlsndupfc); + VitalWireDelay (dltxcfgextsy_ipd, dltxcfgextsy_in, tipd_dltxcfgextsy); + VitalWireDelay (dltxreqpm_ipd, dltxreqpm_in, tipd_dltxreqpm); + loopbits_dltxtyppm : FOR i in dltxtyppm_in'RANGE GENERATE + VitalWireDelay (dltxtyppm_ipd(i), dltxtyppm_in(i), tipd_dltxtyppm(i)); + END GENERATE; + loopbits_dltypupfc : FOR i in dltypupfc_in'RANGE GENERATE + VitalWireDelay (dltypupfc_ipd(i), dltypupfc_in(i), tipd_dltypupfc(i)); + END GENERATE; + loopbits_dlvcctrl : FOR i in dlvcctrl_in'RANGE GENERATE + VitalWireDelay (dlvcctrl_ipd(i), dlvcctrl_in(i), tipd_dlvcctrl(i)); + END GENERATE; + loopbits_dlvcidmap : FOR i in dlvcidmap_in'RANGE GENERATE + VitalWireDelay (dlvcidmap_ipd(i), dlvcidmap_in(i), tipd_dlvcidmap(i)); + END GENERATE; + loopbits_dlvcidupfc : FOR i in dlvcidupfc_in'RANGE GENERATE + VitalWireDelay (dlvcidupfc_ipd(i), dlvcidupfc_in(i), tipd_dlvcidupfc(i)); + END GENERATE; + VitalWireDelay (dpclk_ipd, dpclk_in, tipd_dpclk); + VitalWireDelay (dpriodisable_ipd, dpriodisable_in, tipd_dpriodisable); + VitalWireDelay (dprioin_ipd, dprioin_in, tipd_dprioin); + VitalWireDelay (dprioload_ipd, dprioload_in, tipd_dprioload); + loopbits_extrain : FOR i in extrain_in'RANGE GENERATE + VitalWireDelay (extrain_ipd(i), extrain_in(i), tipd_extrain(i)); + END GENERATE; + loopbits_lmiaddr : FOR i in lmiaddr_in'RANGE GENERATE + VitalWireDelay (lmiaddr_ipd(i), lmiaddr_in(i), tipd_lmiaddr(i)); + END GENERATE; + loopbits_lmidin : FOR i in lmidin_in'RANGE GENERATE + VitalWireDelay (lmidin_ipd(i), lmidin_in(i), tipd_lmidin(i)); + END GENERATE; + VitalWireDelay (lmirden_ipd, lmirden_in, tipd_lmirden); + VitalWireDelay (lmiwren_ipd, lmiwren_in, tipd_lmiwren); + loopbits_mode : FOR i in mode_in'RANGE GENERATE + VitalWireDelay (mode_ipd(i), mode_in(i), tipd_mode(i)); + END GENERATE; + VitalWireDelay (mramhiptestenable_ipd, mramhiptestenable_in, tipd_mramhiptestenable); + VitalWireDelay (mramregscanen_ipd, mramregscanen_in, tipd_mramregscanen); + VitalWireDelay (mramregscanin_ipd, mramregscanin_in, tipd_mramregscanin); + VitalWireDelay (pclkcentral_ipd, pclkcentral_in, tipd_pclkcentral); + VitalWireDelay (pclkch0_ipd, pclkch0_in, tipd_pclkch0); + VitalWireDelay (phyrst_ipd, phyrst_in, tipd_phyrst); + VitalWireDelay (physrst_ipd, physrst_in, tipd_physrst); + loopbits_phystatus : FOR i in phystatus_in'RANGE GENERATE + VitalWireDelay (phystatus_ipd(i), phystatus_in(i), tipd_phystatus(i)); + END GENERATE; + VitalWireDelay (pldclk_ipd, pldclk_in, tipd_pldclk); + VitalWireDelay (pldrst_ipd, pldrst_in, tipd_pldrst); + VitalWireDelay (pldsrst_ipd, pldsrst_in, tipd_pldsrst); + VitalWireDelay (pllfixedclk_ipd, pllfixedclk_in, tipd_pllfixedclk); + loopbits_rxdata : FOR i in rxdata_in'RANGE GENERATE + VitalWireDelay (rxdata_ipd(i), rxdata_in(i), tipd_rxdata(i)); + END GENERATE; + loopbits_rxdatak : FOR i in rxdatak_in'RANGE GENERATE + VitalWireDelay (rxdatak_ipd(i), rxdatak_in(i), tipd_rxdatak(i)); + END GENERATE; + loopbits_rxelecidle : FOR i in rxelecidle_in'RANGE GENERATE + VitalWireDelay (rxelecidle_ipd(i), rxelecidle_in(i), tipd_rxelecidle(i)); + END GENERATE; + VitalWireDelay (rxmaskvc0_ipd, rxmaskvc0_in, tipd_rxmaskvc0); + VitalWireDelay (rxmaskvc1_ipd, rxmaskvc1_in, tipd_rxmaskvc1); + VitalWireDelay (rxreadyvc0_ipd, rxreadyvc0_in, tipd_rxreadyvc0); + VitalWireDelay (rxreadyvc1_ipd, rxreadyvc1_in, tipd_rxreadyvc1); + loopbits_rxstatus : FOR i in rxstatus_in'RANGE GENERATE + VitalWireDelay (rxstatus_ipd(i), rxstatus_in(i), tipd_rxstatus(i)); + END GENERATE; + loopbits_rxvalid : FOR i in rxvalid_in'RANGE GENERATE + VitalWireDelay (rxvalid_ipd(i), rxvalid_in(i), tipd_rxvalid(i)); + END GENERATE; + VitalWireDelay (scanen_ipd, scanen_in, tipd_scanen); + VitalWireDelay (scanmoden_ipd, scanmoden_in, tipd_scanmoden); + loopbits_swdnin : FOR i in swdnin_in'RANGE GENERATE + VitalWireDelay (swdnin_ipd(i), swdnin_in(i), tipd_swdnin(i)); + END GENERATE; + loopbits_swupin : FOR i in swupin_in'RANGE GENERATE + VitalWireDelay (swupin_ipd(i), swupin_in(i), tipd_swupin(i)); + END GENERATE; + loopbits_testin : FOR i in testin_in'RANGE GENERATE + VitalWireDelay (testin_ipd(i), testin_in(i), tipd_testin(i)); + END GENERATE; + loopbits_tlaermsinum : FOR i in tlaermsinum_in'RANGE GENERATE + VitalWireDelay (tlaermsinum_ipd(i), tlaermsinum_in(i), tipd_tlaermsinum(i)); + END GENERATE; + VitalWireDelay (tlappintasts_ipd, tlappintasts_in, tipd_tlappintasts); + loopbits_tlappmsinum : FOR i in tlappmsinum_in'RANGE GENERATE + VitalWireDelay (tlappmsinum_ipd(i), tlappmsinum_in(i), tipd_tlappmsinum(i)); + END GENERATE; + VitalWireDelay (tlappmsireq_ipd, tlappmsireq_in, tipd_tlappmsireq); + loopbits_tlappmsitc : FOR i in tlappmsitc_in'RANGE GENERATE + VitalWireDelay (tlappmsitc_ipd(i), tlappmsitc_in(i), tipd_tlappmsitc(i)); + END GENERATE; + loopbits_tlhpgctrler : FOR i in tlhpgctrler_in'RANGE GENERATE + VitalWireDelay (tlhpgctrler_ipd(i), tlhpgctrler_in(i), tipd_tlhpgctrler(i)); + END GENERATE; + loopbits_tlpexmsinum : FOR i in tlpexmsinum_in'RANGE GENERATE + VitalWireDelay (tlpexmsinum_ipd(i), tlpexmsinum_in(i), tipd_tlpexmsinum(i)); + END GENERATE; + VitalWireDelay (tlpmauxpwr_ipd, tlpmauxpwr_in, tipd_tlpmauxpwr); + loopbits_tlpmdata : FOR i in tlpmdata_in'RANGE GENERATE + VitalWireDelay (tlpmdata_ipd(i), tlpmdata_in(i), tipd_tlpmdata(i)); + END GENERATE; + VitalWireDelay (tlpmetocr_ipd, tlpmetocr_in, tipd_tlpmetocr); + VitalWireDelay (tlpmevent_ipd, tlpmevent_in, tipd_tlpmevent); + VitalWireDelay (tlslotclkcfg_ipd, tlslotclkcfg_in, tipd_tlslotclkcfg); + loopbits_txdatavc00 : FOR i in txdatavc00_in'RANGE GENERATE + VitalWireDelay (txdatavc00_ipd(i), txdatavc00_in(i), tipd_txdatavc00(i)); + END GENERATE; + loopbits_txdatavc01 : FOR i in txdatavc01_in'RANGE GENERATE + VitalWireDelay (txdatavc01_ipd(i), txdatavc01_in(i), tipd_txdatavc01(i)); + END GENERATE; + loopbits_txdatavc10 : FOR i in txdatavc10_in'RANGE GENERATE + VitalWireDelay (txdatavc10_ipd(i), txdatavc10_in(i), tipd_txdatavc10(i)); + END GENERATE; + loopbits_txdatavc11 : FOR i in txdatavc11_in'RANGE GENERATE + VitalWireDelay (txdatavc11_ipd(i), txdatavc11_in(i), tipd_txdatavc11(i)); + END GENERATE; + VitalWireDelay (txeopvc00_ipd, txeopvc00_in, tipd_txeopvc00); + VitalWireDelay (txeopvc01_ipd, txeopvc01_in, tipd_txeopvc01); + VitalWireDelay (txeopvc10_ipd, txeopvc10_in, tipd_txeopvc10); + VitalWireDelay (txeopvc11_ipd, txeopvc11_in, tipd_txeopvc11); + VitalWireDelay (txerrvc0_ipd, txerrvc0_in, tipd_txerrvc0); + VitalWireDelay (txerrvc1_ipd, txerrvc1_in, tipd_txerrvc1); + VitalWireDelay (txsopvc00_ipd, txsopvc00_in, tipd_txsopvc00); + VitalWireDelay (txsopvc01_ipd, txsopvc01_in, tipd_txsopvc01); + VitalWireDelay (txsopvc10_ipd, txsopvc10_in, tipd_txsopvc10); + VitalWireDelay (txsopvc11_ipd, txsopvc11_in, tipd_txsopvc11); + VitalWireDelay (txvalidvc0_ipd, txvalidvc0_in, tipd_txvalidvc0); + VitalWireDelay (txvalidvc1_ipd, txvalidvc1_in, tipd_txvalidvc1); + END BLOCK; + + --/////////////////////////////////////////////////////////////////////////// + -- TIMING -- TCO/TSU/HOLD ------------------------------------------------// + --/////////////////////////////////////////////////////////////////////////// + ----------------------------------- + -- Timing Check Section + ----------------------------------- + + -- TSU/THOLD of pldclk + VITAL_corecrst: PROCESS (pldclk_ipd, corecrst_ipd) + variable Tviol_pldclk_corecrst : std_ulogic := '0'; + variable TimingData_pldclk_corecrst : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_corecrst, + TimingData => TimingData_pldclk_corecrst, + TestSignal => corecrst_ipd, + TestSignalName => "corecrst", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_corecrst_pldclk_noedge_posedge, + SetupLow => tsetup_corecrst_pldclk_noedge_posedge, + HoldHigh => thold_corecrst_pldclk_noedge_posedge, + HoldLow => thold_corecrst_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_coresrst: PROCESS (pldclk_ipd, coresrst_ipd) + variable Tviol_pldclk_coresrst : std_ulogic := '0'; + variable TimingData_pldclk_coresrst : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_coresrst, + TimingData => TimingData_pldclk_coresrst, + TestSignal => coresrst_ipd, + TestSignalName => "coresrst", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_coresrst_pldclk_noedge_posedge, + SetupLow => tsetup_coresrst_pldclk_noedge_posedge, + HoldHigh => thold_coresrst_pldclk_noedge_posedge, + HoldLow => thold_coresrst_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_cplerr: PROCESS (pldclk_ipd, cplerr_ipd) + variable Tviol_pldclk_cplerr : std_ulogic := '0'; + variable TimingData_pldclk_cplerr : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_cplerr, + TimingData => TimingData_pldclk_cplerr, + TestSignal => cplerr_ipd, + TestSignalName => "cplerr", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_cplerr_pldclk_noedge_posedge, + SetupLow => tsetup_cplerr_pldclk_noedge_posedge, + HoldHigh => thold_cplerr_pldclk_noedge_posedge, + HoldLow => thold_cplerr_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_cplpending: PROCESS (pldclk_ipd, cplpending_ipd) + variable Tviol_pldclk_cplpending : std_ulogic := '0'; + variable TimingData_pldclk_cplpending : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_cplpending, + TimingData => TimingData_pldclk_cplpending, + TestSignal => cplpending_ipd, + TestSignalName => "cplpending", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_cplpending_pldclk_noedge_posedge, + SetupLow => tsetup_cplpending_pldclk_noedge_posedge, + HoldHigh => thold_cplpending_pldclk_noedge_posedge, + HoldLow => thold_cplpending_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlctrllink2: PROCESS (pldclk_ipd, dlctrllink2_ipd) + variable Tviol_pldclk_dlctrllink2 : std_ulogic := '0'; + variable TimingData_pldclk_dlctrllink2 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlctrllink2, + TimingData => TimingData_pldclk_dlctrllink2, + TestSignal => dlctrllink2_ipd, + TestSignalName => "dlctrllink2", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlctrllink2_pldclk_noedge_posedge, + SetupLow => tsetup_dlctrllink2_pldclk_noedge_posedge, + HoldHigh => thold_dlctrllink2_pldclk_noedge_posedge, + HoldLow => thold_dlctrllink2_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dldataupfc: PROCESS (pldclk_ipd, dldataupfc_ipd) + variable Tviol_pldclk_dldataupfc : std_ulogic := '0'; + variable TimingData_pldclk_dldataupfc : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dldataupfc, + TimingData => TimingData_pldclk_dldataupfc, + TestSignal => dldataupfc_ipd, + TestSignalName => "dldataupfc", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dldataupfc_pldclk_noedge_posedge, + SetupLow => tsetup_dldataupfc_pldclk_noedge_posedge, + HoldHigh => thold_dldataupfc_pldclk_noedge_posedge, + HoldLow => thold_dldataupfc_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlhdrupfc: PROCESS (pldclk_ipd, dlhdrupfc_ipd) + variable Tviol_pldclk_dlhdrupfc : std_ulogic := '0'; + variable TimingData_pldclk_dlhdrupfc : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlhdrupfc, + TimingData => TimingData_pldclk_dlhdrupfc, + TestSignal => dlhdrupfc_ipd, + TestSignalName => "dlhdrupfc", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlhdrupfc_pldclk_noedge_posedge, + SetupLow => tsetup_dlhdrupfc_pldclk_noedge_posedge, + HoldHigh => thold_dlhdrupfc_pldclk_noedge_posedge, + HoldLow => thold_dlhdrupfc_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlinhdllp: PROCESS (pldclk_ipd, dlinhdllp_ipd) + variable Tviol_pldclk_dlinhdllp : std_ulogic := '0'; + variable TimingData_pldclk_dlinhdllp : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlinhdllp, + TimingData => TimingData_pldclk_dlinhdllp, + TestSignal => dlinhdllp_ipd, + TestSignalName => "dlinhdllp", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlinhdllp_pldclk_noedge_posedge, + SetupLow => tsetup_dlinhdllp_pldclk_noedge_posedge, + HoldHigh => thold_dlinhdllp_pldclk_noedge_posedge, + HoldLow => thold_dlinhdllp_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlmaxploaddcr: PROCESS (pldclk_ipd, dlmaxploaddcr_ipd) + variable Tviol_pldclk_dlmaxploaddcr : std_ulogic := '0'; + variable TimingData_pldclk_dlmaxploaddcr : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlmaxploaddcr, + TimingData => TimingData_pldclk_dlmaxploaddcr, + TestSignal => dlmaxploaddcr_ipd, + TestSignalName => "dlmaxploaddcr", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlmaxploaddcr_pldclk_noedge_posedge, + SetupLow => tsetup_dlmaxploaddcr_pldclk_noedge_posedge, + HoldHigh => thold_dlmaxploaddcr_pldclk_noedge_posedge, + HoldLow => thold_dlmaxploaddcr_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlreqphycfg: PROCESS (pldclk_ipd, dlreqphycfg_ipd) + variable Tviol_pldclk_dlreqphycfg : std_ulogic := '0'; + variable TimingData_pldclk_dlreqphycfg : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlreqphycfg, + TimingData => TimingData_pldclk_dlreqphycfg, + TestSignal => dlreqphycfg_ipd, + TestSignalName => "dlreqphycfg", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlreqphycfg_pldclk_noedge_posedge, + SetupLow => tsetup_dlreqphycfg_pldclk_noedge_posedge, + HoldHigh => thold_dlreqphycfg_pldclk_noedge_posedge, + HoldLow => thold_dlreqphycfg_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlreqphypm: PROCESS (pldclk_ipd, dlreqphypm_ipd) + variable Tviol_pldclk_dlreqphypm : std_ulogic := '0'; + variable TimingData_pldclk_dlreqphypm : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlreqphypm, + TimingData => TimingData_pldclk_dlreqphypm, + TestSignal => dlreqphypm_ipd, + TestSignalName => "dlreqphypm", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlreqphypm_pldclk_noedge_posedge, + SetupLow => tsetup_dlreqphypm_pldclk_noedge_posedge, + HoldHigh => thold_dlreqphypm_pldclk_noedge_posedge, + HoldLow => thold_dlreqphypm_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlrequpfc: PROCESS (pldclk_ipd, dlrequpfc_ipd) + variable Tviol_pldclk_dlrequpfc : std_ulogic := '0'; + variable TimingData_pldclk_dlrequpfc : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlrequpfc, + TimingData => TimingData_pldclk_dlrequpfc, + TestSignal => dlrequpfc_ipd, + TestSignalName => "dlrequpfc", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlrequpfc_pldclk_noedge_posedge, + SetupLow => tsetup_dlrequpfc_pldclk_noedge_posedge, + HoldHigh => thold_dlrequpfc_pldclk_noedge_posedge, + HoldLow => thold_dlrequpfc_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlreqwake: PROCESS (pldclk_ipd, dlreqwake_ipd) + variable Tviol_pldclk_dlreqwake : std_ulogic := '0'; + variable TimingData_pldclk_dlreqwake : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlreqwake, + TimingData => TimingData_pldclk_dlreqwake, + TestSignal => dlreqwake_ipd, + TestSignalName => "dlreqwake", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlreqwake_pldclk_noedge_posedge, + SetupLow => tsetup_dlreqwake_pldclk_noedge_posedge, + HoldHigh => thold_dlreqwake_pldclk_noedge_posedge, + HoldLow => thold_dlreqwake_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlrxecrcchk: PROCESS (pldclk_ipd, dlrxecrcchk_ipd) + variable Tviol_pldclk_dlrxecrcchk : std_ulogic := '0'; + variable TimingData_pldclk_dlrxecrcchk : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlrxecrcchk, + TimingData => TimingData_pldclk_dlrxecrcchk, + TestSignal => dlrxecrcchk_ipd, + TestSignalName => "dlrxecrcchk", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlrxecrcchk_pldclk_noedge_posedge, + SetupLow => tsetup_dlrxecrcchk_pldclk_noedge_posedge, + HoldHigh => thold_dlrxecrcchk_pldclk_noedge_posedge, + HoldLow => thold_dlrxecrcchk_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlsndupfc: PROCESS (pldclk_ipd, dlsndupfc_ipd) + variable Tviol_pldclk_dlsndupfc : std_ulogic := '0'; + variable TimingData_pldclk_dlsndupfc : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlsndupfc, + TimingData => TimingData_pldclk_dlsndupfc, + TestSignal => dlsndupfc_ipd, + TestSignalName => "dlsndupfc", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlsndupfc_pldclk_noedge_posedge, + SetupLow => tsetup_dlsndupfc_pldclk_noedge_posedge, + HoldHigh => thold_dlsndupfc_pldclk_noedge_posedge, + HoldLow => thold_dlsndupfc_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dltxcfgextsy: PROCESS (pldclk_ipd, dltxcfgextsy_ipd) + variable Tviol_pldclk_dltxcfgextsy : std_ulogic := '0'; + variable TimingData_pldclk_dltxcfgextsy : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dltxcfgextsy, + TimingData => TimingData_pldclk_dltxcfgextsy, + TestSignal => dltxcfgextsy_ipd, + TestSignalName => "dltxcfgextsy", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dltxcfgextsy_pldclk_noedge_posedge, + SetupLow => tsetup_dltxcfgextsy_pldclk_noedge_posedge, + HoldHigh => thold_dltxcfgextsy_pldclk_noedge_posedge, + HoldLow => thold_dltxcfgextsy_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dltxreqpm: PROCESS (pldclk_ipd, dltxreqpm_ipd) + variable Tviol_pldclk_dltxreqpm : std_ulogic := '0'; + variable TimingData_pldclk_dltxreqpm : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dltxreqpm, + TimingData => TimingData_pldclk_dltxreqpm, + TestSignal => dltxreqpm_ipd, + TestSignalName => "dltxreqpm", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dltxreqpm_pldclk_noedge_posedge, + SetupLow => tsetup_dltxreqpm_pldclk_noedge_posedge, + HoldHigh => thold_dltxreqpm_pldclk_noedge_posedge, + HoldLow => thold_dltxreqpm_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dltxtyppm: PROCESS (pldclk_ipd, dltxtyppm_ipd) + variable Tviol_pldclk_dltxtyppm : std_ulogic := '0'; + variable TimingData_pldclk_dltxtyppm : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dltxtyppm, + TimingData => TimingData_pldclk_dltxtyppm, + TestSignal => dltxtyppm_ipd, + TestSignalName => "dltxtyppm", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dltxtyppm_pldclk_noedge_posedge, + SetupLow => tsetup_dltxtyppm_pldclk_noedge_posedge, + HoldHigh => thold_dltxtyppm_pldclk_noedge_posedge, + HoldLow => thold_dltxtyppm_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dltypupfc: PROCESS (pldclk_ipd, dltypupfc_ipd) + variable Tviol_pldclk_dltypupfc : std_ulogic := '0'; + variable TimingData_pldclk_dltypupfc : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dltypupfc, + TimingData => TimingData_pldclk_dltypupfc, + TestSignal => dltypupfc_ipd, + TestSignalName => "dltypupfc", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dltypupfc_pldclk_noedge_posedge, + SetupLow => tsetup_dltypupfc_pldclk_noedge_posedge, + HoldHigh => thold_dltypupfc_pldclk_noedge_posedge, + HoldLow => thold_dltypupfc_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlvcctrl: PROCESS (pldclk_ipd, dlvcctrl_ipd) + variable Tviol_pldclk_dlvcctrl : std_ulogic := '0'; + variable TimingData_pldclk_dlvcctrl : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlvcctrl, + TimingData => TimingData_pldclk_dlvcctrl, + TestSignal => dlvcctrl_ipd, + TestSignalName => "dlvcctrl", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlvcctrl_pldclk_noedge_posedge, + SetupLow => tsetup_dlvcctrl_pldclk_noedge_posedge, + HoldHigh => thold_dlvcctrl_pldclk_noedge_posedge, + HoldLow => thold_dlvcctrl_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlvcidmap: PROCESS (pldclk_ipd, dlvcidmap_ipd) + variable Tviol_pldclk_dlvcidmap : std_ulogic := '0'; + variable TimingData_pldclk_dlvcidmap : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlvcidmap, + TimingData => TimingData_pldclk_dlvcidmap, + TestSignal => dlvcidmap_ipd, + TestSignalName => "dlvcidmap", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlvcidmap_pldclk_noedge_posedge, + SetupLow => tsetup_dlvcidmap_pldclk_noedge_posedge, + HoldHigh => thold_dlvcidmap_pldclk_noedge_posedge, + HoldLow => thold_dlvcidmap_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dlvcidupfc: PROCESS (pldclk_ipd, dlvcidupfc_ipd) + variable Tviol_pldclk_dlvcidupfc : std_ulogic := '0'; + variable TimingData_pldclk_dlvcidupfc : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_dlvcidupfc, + TimingData => TimingData_pldclk_dlvcidupfc, + TestSignal => dlvcidupfc_ipd, + TestSignalName => "dlvcidupfc", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_dlvcidupfc_pldclk_noedge_posedge, + SetupLow => tsetup_dlvcidupfc_pldclk_noedge_posedge, + HoldHigh => thold_dlvcidupfc_pldclk_noedge_posedge, + HoldLow => thold_dlvcidupfc_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_lmiaddr: PROCESS (pldclk_ipd, lmiaddr_ipd) + variable Tviol_pldclk_lmiaddr : std_ulogic := '0'; + variable TimingData_pldclk_lmiaddr : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_lmiaddr, + TimingData => TimingData_pldclk_lmiaddr, + TestSignal => lmiaddr_ipd, + TestSignalName => "lmiaddr", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_lmiaddr_pldclk_noedge_posedge, + SetupLow => tsetup_lmiaddr_pldclk_noedge_posedge, + HoldHigh => thold_lmiaddr_pldclk_noedge_posedge, + HoldLow => thold_lmiaddr_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_lmidin: PROCESS (pldclk_ipd, lmidin_ipd) + variable Tviol_pldclk_lmidin : std_ulogic := '0'; + variable TimingData_pldclk_lmidin : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_lmidin, + TimingData => TimingData_pldclk_lmidin, + TestSignal => lmidin_ipd, + TestSignalName => "lmidin", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_lmidin_pldclk_noedge_posedge, + SetupLow => tsetup_lmidin_pldclk_noedge_posedge, + HoldHigh => thold_lmidin_pldclk_noedge_posedge, + HoldLow => thold_lmidin_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_lmirden: PROCESS (pldclk_ipd, lmirden_ipd) + variable Tviol_pldclk_lmirden : std_ulogic := '0'; + variable TimingData_pldclk_lmirden : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_lmirden, + TimingData => TimingData_pldclk_lmirden, + TestSignal => lmirden_ipd, + TestSignalName => "lmirden", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_lmirden_pldclk_noedge_posedge, + SetupLow => tsetup_lmirden_pldclk_noedge_posedge, + HoldHigh => thold_lmirden_pldclk_noedge_posedge, + HoldLow => thold_lmirden_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_lmiwren: PROCESS (pldclk_ipd, lmiwren_ipd) + variable Tviol_pldclk_lmiwren : std_ulogic := '0'; + variable TimingData_pldclk_lmiwren : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_lmiwren, + TimingData => TimingData_pldclk_lmiwren, + TestSignal => lmiwren_ipd, + TestSignalName => "lmiwren", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_lmiwren_pldclk_noedge_posedge, + SetupLow => tsetup_lmiwren_pldclk_noedge_posedge, + HoldHigh => thold_lmiwren_pldclk_noedge_posedge, + HoldLow => thold_lmiwren_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_physrst: PROCESS (pldclk_ipd, physrst_ipd) + variable Tviol_pldclk_physrst : std_ulogic := '0'; + variable TimingData_pldclk_physrst : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_physrst, + TimingData => TimingData_pldclk_physrst, + TestSignal => physrst_ipd, + TestSignalName => "physrst", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_physrst_pldclk_noedge_posedge, + SetupLow => tsetup_physrst_pldclk_noedge_posedge, + HoldHigh => thold_physrst_pldclk_noedge_posedge, + HoldLow => thold_physrst_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_pldsrst: PROCESS (pldclk_ipd, pldsrst_ipd) + variable Tviol_pldclk_pldsrst : std_ulogic := '0'; + variable TimingData_pldclk_pldsrst : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_pldsrst, + TimingData => TimingData_pldclk_pldsrst, + TestSignal => pldsrst_ipd, + TestSignalName => "pldsrst", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_pldsrst_pldclk_noedge_posedge, + SetupLow => tsetup_pldsrst_pldclk_noedge_posedge, + HoldHigh => thold_pldsrst_pldclk_noedge_posedge, + HoldLow => thold_pldsrst_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_rxmaskvc0: PROCESS (pldclk_ipd, rxmaskvc0_ipd) + variable Tviol_pldclk_rxmaskvc0 : std_ulogic := '0'; + variable TimingData_pldclk_rxmaskvc0 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_rxmaskvc0, + TimingData => TimingData_pldclk_rxmaskvc0, + TestSignal => rxmaskvc0_ipd, + TestSignalName => "rxmaskvc0", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_rxmaskvc0_pldclk_noedge_posedge, + SetupLow => tsetup_rxmaskvc0_pldclk_noedge_posedge, + HoldHigh => thold_rxmaskvc0_pldclk_noedge_posedge, + HoldLow => thold_rxmaskvc0_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_rxmaskvc1: PROCESS (pldclk_ipd, rxmaskvc1_ipd) + variable Tviol_pldclk_rxmaskvc1 : std_ulogic := '0'; + variable TimingData_pldclk_rxmaskvc1 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_rxmaskvc1, + TimingData => TimingData_pldclk_rxmaskvc1, + TestSignal => rxmaskvc1_ipd, + TestSignalName => "rxmaskvc1", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_rxmaskvc1_pldclk_noedge_posedge, + SetupLow => tsetup_rxmaskvc1_pldclk_noedge_posedge, + HoldHigh => thold_rxmaskvc1_pldclk_noedge_posedge, + HoldLow => thold_rxmaskvc1_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_rxreadyvc0: PROCESS (pldclk_ipd, rxreadyvc0_ipd) + variable Tviol_pldclk_rxreadyvc0 : std_ulogic := '0'; + variable TimingData_pldclk_rxreadyvc0 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_rxreadyvc0, + TimingData => TimingData_pldclk_rxreadyvc0, + TestSignal => rxreadyvc0_ipd, + TestSignalName => "rxreadyvc0", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_rxreadyvc0_pldclk_noedge_posedge, + SetupLow => tsetup_rxreadyvc0_pldclk_noedge_posedge, + HoldHigh => thold_rxreadyvc0_pldclk_noedge_posedge, + HoldLow => thold_rxreadyvc0_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_rxreadyvc1: PROCESS (pldclk_ipd, rxreadyvc1_ipd) + variable Tviol_pldclk_rxreadyvc1 : std_ulogic := '0'; + variable TimingData_pldclk_rxreadyvc1 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_rxreadyvc1, + TimingData => TimingData_pldclk_rxreadyvc1, + TestSignal => rxreadyvc1_ipd, + TestSignalName => "rxreadyvc1", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_rxreadyvc1_pldclk_noedge_posedge, + SetupLow => tsetup_rxreadyvc1_pldclk_noedge_posedge, + HoldHigh => thold_rxreadyvc1_pldclk_noedge_posedge, + HoldLow => thold_rxreadyvc1_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_swdnin: PROCESS (pldclk_ipd, swdnin_ipd) + variable Tviol_pldclk_swdnin : std_ulogic := '0'; + variable TimingData_pldclk_swdnin : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_swdnin, + TimingData => TimingData_pldclk_swdnin, + TestSignal => swdnin_ipd, + TestSignalName => "swdnin", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_swdnin_pldclk_noedge_posedge, + SetupLow => tsetup_swdnin_pldclk_noedge_posedge, + HoldHigh => thold_swdnin_pldclk_noedge_posedge, + HoldLow => thold_swdnin_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_swupin: PROCESS (pldclk_ipd, swupin_ipd) + variable Tviol_pldclk_swupin : std_ulogic := '0'; + variable TimingData_pldclk_swupin : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_swupin, + TimingData => TimingData_pldclk_swupin, + TestSignal => swupin_ipd, + TestSignalName => "swupin", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_swupin_pldclk_noedge_posedge, + SetupLow => tsetup_swupin_pldclk_noedge_posedge, + HoldHigh => thold_swupin_pldclk_noedge_posedge, + HoldLow => thold_swupin_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlaermsinum: PROCESS (pldclk_ipd, tlaermsinum_ipd) + variable Tviol_pldclk_tlaermsinum : std_ulogic := '0'; + variable TimingData_pldclk_tlaermsinum : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlaermsinum, + TimingData => TimingData_pldclk_tlaermsinum, + TestSignal => tlaermsinum_ipd, + TestSignalName => "tlaermsinum", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlaermsinum_pldclk_noedge_posedge, + SetupLow => tsetup_tlaermsinum_pldclk_noedge_posedge, + HoldHigh => thold_tlaermsinum_pldclk_noedge_posedge, + HoldLow => thold_tlaermsinum_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlappintasts: PROCESS (pldclk_ipd, tlappintasts_ipd) + variable Tviol_pldclk_tlappintasts : std_ulogic := '0'; + variable TimingData_pldclk_tlappintasts : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlappintasts, + TimingData => TimingData_pldclk_tlappintasts, + TestSignal => tlappintasts_ipd, + TestSignalName => "tlappintasts", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlappintasts_pldclk_noedge_posedge, + SetupLow => tsetup_tlappintasts_pldclk_noedge_posedge, + HoldHigh => thold_tlappintasts_pldclk_noedge_posedge, + HoldLow => thold_tlappintasts_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlappmsinum: PROCESS (pldclk_ipd, tlappmsinum_ipd) + variable Tviol_pldclk_tlappmsinum : std_ulogic := '0'; + variable TimingData_pldclk_tlappmsinum : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlappmsinum, + TimingData => TimingData_pldclk_tlappmsinum, + TestSignal => tlappmsinum_ipd, + TestSignalName => "tlappmsinum", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlappmsinum_pldclk_noedge_posedge, + SetupLow => tsetup_tlappmsinum_pldclk_noedge_posedge, + HoldHigh => thold_tlappmsinum_pldclk_noedge_posedge, + HoldLow => thold_tlappmsinum_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlappmsireq: PROCESS (pldclk_ipd, tlappmsireq_ipd) + variable Tviol_pldclk_tlappmsireq : std_ulogic := '0'; + variable TimingData_pldclk_tlappmsireq : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlappmsireq, + TimingData => TimingData_pldclk_tlappmsireq, + TestSignal => tlappmsireq_ipd, + TestSignalName => "tlappmsireq", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlappmsireq_pldclk_noedge_posedge, + SetupLow => tsetup_tlappmsireq_pldclk_noedge_posedge, + HoldHigh => thold_tlappmsireq_pldclk_noedge_posedge, + HoldLow => thold_tlappmsireq_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlappmsitc: PROCESS (pldclk_ipd, tlappmsitc_ipd) + variable Tviol_pldclk_tlappmsitc : std_ulogic := '0'; + variable TimingData_pldclk_tlappmsitc : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlappmsitc, + TimingData => TimingData_pldclk_tlappmsitc, + TestSignal => tlappmsitc_ipd, + TestSignalName => "tlappmsitc", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlappmsitc_pldclk_noedge_posedge, + SetupLow => tsetup_tlappmsitc_pldclk_noedge_posedge, + HoldHigh => thold_tlappmsitc_pldclk_noedge_posedge, + HoldLow => thold_tlappmsitc_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlhpgctrler: PROCESS (pldclk_ipd, tlhpgctrler_ipd) + variable Tviol_pldclk_tlhpgctrler : std_ulogic := '0'; + variable TimingData_pldclk_tlhpgctrler : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlhpgctrler, + TimingData => TimingData_pldclk_tlhpgctrler, + TestSignal => tlhpgctrler_ipd, + TestSignalName => "tlhpgctrler", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlhpgctrler_pldclk_noedge_posedge, + SetupLow => tsetup_tlhpgctrler_pldclk_noedge_posedge, + HoldHigh => thold_tlhpgctrler_pldclk_noedge_posedge, + HoldLow => thold_tlhpgctrler_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlpexmsinum: PROCESS (pldclk_ipd, tlpexmsinum_ipd) + variable Tviol_pldclk_tlpexmsinum : std_ulogic := '0'; + variable TimingData_pldclk_tlpexmsinum : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlpexmsinum, + TimingData => TimingData_pldclk_tlpexmsinum, + TestSignal => tlpexmsinum_ipd, + TestSignalName => "tlpexmsinum", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlpexmsinum_pldclk_noedge_posedge, + SetupLow => tsetup_tlpexmsinum_pldclk_noedge_posedge, + HoldHigh => thold_tlpexmsinum_pldclk_noedge_posedge, + HoldLow => thold_tlpexmsinum_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlpmauxpwr: PROCESS (pldclk_ipd, tlpmauxpwr_ipd) + variable Tviol_pldclk_tlpmauxpwr : std_ulogic := '0'; + variable TimingData_pldclk_tlpmauxpwr : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlpmauxpwr, + TimingData => TimingData_pldclk_tlpmauxpwr, + TestSignal => tlpmauxpwr_ipd, + TestSignalName => "tlpmauxpwr", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlpmauxpwr_pldclk_noedge_posedge, + SetupLow => tsetup_tlpmauxpwr_pldclk_noedge_posedge, + HoldHigh => thold_tlpmauxpwr_pldclk_noedge_posedge, + HoldLow => thold_tlpmauxpwr_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlpmdata: PROCESS (pldclk_ipd, tlpmdata_ipd) + variable Tviol_pldclk_tlpmdata : std_ulogic := '0'; + variable TimingData_pldclk_tlpmdata : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlpmdata, + TimingData => TimingData_pldclk_tlpmdata, + TestSignal => tlpmdata_ipd, + TestSignalName => "tlpmdata", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlpmdata_pldclk_noedge_posedge, + SetupLow => tsetup_tlpmdata_pldclk_noedge_posedge, + HoldHigh => thold_tlpmdata_pldclk_noedge_posedge, + HoldLow => thold_tlpmdata_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlpmetocr: PROCESS (pldclk_ipd, tlpmetocr_ipd) + variable Tviol_pldclk_tlpmetocr : std_ulogic := '0'; + variable TimingData_pldclk_tlpmetocr : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlpmetocr, + TimingData => TimingData_pldclk_tlpmetocr, + TestSignal => tlpmetocr_ipd, + TestSignalName => "tlpmetocr", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlpmetocr_pldclk_noedge_posedge, + SetupLow => tsetup_tlpmetocr_pldclk_noedge_posedge, + HoldHigh => thold_tlpmetocr_pldclk_noedge_posedge, + HoldLow => thold_tlpmetocr_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_tlpmevent: PROCESS (pldclk_ipd, tlpmevent_ipd) + variable Tviol_pldclk_tlpmevent : std_ulogic := '0'; + variable TimingData_pldclk_tlpmevent : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_tlpmevent, + TimingData => TimingData_pldclk_tlpmevent, + TestSignal => tlpmevent_ipd, + TestSignalName => "tlpmevent", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_tlpmevent_pldclk_noedge_posedge, + SetupLow => tsetup_tlpmevent_pldclk_noedge_posedge, + HoldHigh => thold_tlpmevent_pldclk_noedge_posedge, + HoldLow => thold_tlpmevent_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txdatavc00: PROCESS (pldclk_ipd, txdatavc00_ipd) + variable Tviol_pldclk_txdatavc00 : std_ulogic := '0'; + variable TimingData_pldclk_txdatavc00 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txdatavc00, + TimingData => TimingData_pldclk_txdatavc00, + TestSignal => txdatavc00_ipd, + TestSignalName => "txdatavc00", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txdatavc00_pldclk_noedge_posedge, + SetupLow => tsetup_txdatavc00_pldclk_noedge_posedge, + HoldHigh => thold_txdatavc00_pldclk_noedge_posedge, + HoldLow => thold_txdatavc00_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txdatavc01: PROCESS (pldclk_ipd, txdatavc01_ipd) + variable Tviol_pldclk_txdatavc01 : std_ulogic := '0'; + variable TimingData_pldclk_txdatavc01 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txdatavc01, + TimingData => TimingData_pldclk_txdatavc01, + TestSignal => txdatavc01_ipd, + TestSignalName => "txdatavc01", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txdatavc01_pldclk_noedge_posedge, + SetupLow => tsetup_txdatavc01_pldclk_noedge_posedge, + HoldHigh => thold_txdatavc01_pldclk_noedge_posedge, + HoldLow => thold_txdatavc01_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txdatavc10: PROCESS (pldclk_ipd, txdatavc10_ipd) + variable Tviol_pldclk_txdatavc10 : std_ulogic := '0'; + variable TimingData_pldclk_txdatavc10 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txdatavc10, + TimingData => TimingData_pldclk_txdatavc10, + TestSignal => txdatavc10_ipd, + TestSignalName => "txdatavc10", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txdatavc10_pldclk_noedge_posedge, + SetupLow => tsetup_txdatavc10_pldclk_noedge_posedge, + HoldHigh => thold_txdatavc10_pldclk_noedge_posedge, + HoldLow => thold_txdatavc10_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txdatavc11: PROCESS (pldclk_ipd, txdatavc11_ipd) + variable Tviol_pldclk_txdatavc11 : std_ulogic := '0'; + variable TimingData_pldclk_txdatavc11 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txdatavc11, + TimingData => TimingData_pldclk_txdatavc11, + TestSignal => txdatavc11_ipd, + TestSignalName => "txdatavc11", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txdatavc11_pldclk_noedge_posedge, + SetupLow => tsetup_txdatavc11_pldclk_noedge_posedge, + HoldHigh => thold_txdatavc11_pldclk_noedge_posedge, + HoldLow => thold_txdatavc11_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txeopvc00: PROCESS (pldclk_ipd, txeopvc00_ipd) + variable Tviol_pldclk_txeopvc00 : std_ulogic := '0'; + variable TimingData_pldclk_txeopvc00 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txeopvc00, + TimingData => TimingData_pldclk_txeopvc00, + TestSignal => txeopvc00_ipd, + TestSignalName => "txeopvc00", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txeopvc00_pldclk_noedge_posedge, + SetupLow => tsetup_txeopvc00_pldclk_noedge_posedge, + HoldHigh => thold_txeopvc00_pldclk_noedge_posedge, + HoldLow => thold_txeopvc00_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txeopvc01: PROCESS (pldclk_ipd, txeopvc01_ipd) + variable Tviol_pldclk_txeopvc01 : std_ulogic := '0'; + variable TimingData_pldclk_txeopvc01 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txeopvc01, + TimingData => TimingData_pldclk_txeopvc01, + TestSignal => txeopvc01_ipd, + TestSignalName => "txeopvc01", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txeopvc01_pldclk_noedge_posedge, + SetupLow => tsetup_txeopvc01_pldclk_noedge_posedge, + HoldHigh => thold_txeopvc01_pldclk_noedge_posedge, + HoldLow => thold_txeopvc01_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txeopvc10: PROCESS (pldclk_ipd, txeopvc10_ipd) + variable Tviol_pldclk_txeopvc10 : std_ulogic := '0'; + variable TimingData_pldclk_txeopvc10 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txeopvc10, + TimingData => TimingData_pldclk_txeopvc10, + TestSignal => txeopvc10_ipd, + TestSignalName => "txeopvc10", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txeopvc10_pldclk_noedge_posedge, + SetupLow => tsetup_txeopvc10_pldclk_noedge_posedge, + HoldHigh => thold_txeopvc10_pldclk_noedge_posedge, + HoldLow => thold_txeopvc10_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txeopvc11: PROCESS (pldclk_ipd, txeopvc11_ipd) + variable Tviol_pldclk_txeopvc11 : std_ulogic := '0'; + variable TimingData_pldclk_txeopvc11 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txeopvc11, + TimingData => TimingData_pldclk_txeopvc11, + TestSignal => txeopvc11_ipd, + TestSignalName => "txeopvc11", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txeopvc11_pldclk_noedge_posedge, + SetupLow => tsetup_txeopvc11_pldclk_noedge_posedge, + HoldHigh => thold_txeopvc11_pldclk_noedge_posedge, + HoldLow => thold_txeopvc11_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txerrvc0: PROCESS (pldclk_ipd, txerrvc0_ipd) + variable Tviol_pldclk_txerrvc0 : std_ulogic := '0'; + variable TimingData_pldclk_txerrvc0 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txerrvc0, + TimingData => TimingData_pldclk_txerrvc0, + TestSignal => txerrvc0_ipd, + TestSignalName => "txerrvc0", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txerrvc0_pldclk_noedge_posedge, + SetupLow => tsetup_txerrvc0_pldclk_noedge_posedge, + HoldHigh => thold_txerrvc0_pldclk_noedge_posedge, + HoldLow => thold_txerrvc0_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txerrvc1: PROCESS (pldclk_ipd, txerrvc1_ipd) + variable Tviol_pldclk_txerrvc1 : std_ulogic := '0'; + variable TimingData_pldclk_txerrvc1 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txerrvc1, + TimingData => TimingData_pldclk_txerrvc1, + TestSignal => txerrvc1_ipd, + TestSignalName => "txerrvc1", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txerrvc1_pldclk_noedge_posedge, + SetupLow => tsetup_txerrvc1_pldclk_noedge_posedge, + HoldHigh => thold_txerrvc1_pldclk_noedge_posedge, + HoldLow => thold_txerrvc1_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txsopvc00: PROCESS (pldclk_ipd, txsopvc00_ipd) + variable Tviol_pldclk_txsopvc00 : std_ulogic := '0'; + variable TimingData_pldclk_txsopvc00 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txsopvc00, + TimingData => TimingData_pldclk_txsopvc00, + TestSignal => txsopvc00_ipd, + TestSignalName => "txsopvc00", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txsopvc00_pldclk_noedge_posedge, + SetupLow => tsetup_txsopvc00_pldclk_noedge_posedge, + HoldHigh => thold_txsopvc00_pldclk_noedge_posedge, + HoldLow => thold_txsopvc00_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txsopvc01: PROCESS (pldclk_ipd, txsopvc01_ipd) + variable Tviol_pldclk_txsopvc01 : std_ulogic := '0'; + variable TimingData_pldclk_txsopvc01 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txsopvc01, + TimingData => TimingData_pldclk_txsopvc01, + TestSignal => txsopvc01_ipd, + TestSignalName => "txsopvc01", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txsopvc01_pldclk_noedge_posedge, + SetupLow => tsetup_txsopvc01_pldclk_noedge_posedge, + HoldHigh => thold_txsopvc01_pldclk_noedge_posedge, + HoldLow => thold_txsopvc01_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txsopvc10: PROCESS (pldclk_ipd, txsopvc10_ipd) + variable Tviol_pldclk_txsopvc10 : std_ulogic := '0'; + variable TimingData_pldclk_txsopvc10 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txsopvc10, + TimingData => TimingData_pldclk_txsopvc10, + TestSignal => txsopvc10_ipd, + TestSignalName => "txsopvc10", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txsopvc10_pldclk_noedge_posedge, + SetupLow => tsetup_txsopvc10_pldclk_noedge_posedge, + HoldHigh => thold_txsopvc10_pldclk_noedge_posedge, + HoldLow => thold_txsopvc10_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txsopvc11: PROCESS (pldclk_ipd, txsopvc11_ipd) + variable Tviol_pldclk_txsopvc11 : std_ulogic := '0'; + variable TimingData_pldclk_txsopvc11 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txsopvc11, + TimingData => TimingData_pldclk_txsopvc11, + TestSignal => txsopvc11_ipd, + TestSignalName => "txsopvc11", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txsopvc11_pldclk_noedge_posedge, + SetupLow => tsetup_txsopvc11_pldclk_noedge_posedge, + HoldHigh => thold_txsopvc11_pldclk_noedge_posedge, + HoldLow => thold_txsopvc11_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txvalidvc0: PROCESS (pldclk_ipd, txvalidvc0_ipd) + variable Tviol_pldclk_txvalidvc0 : std_ulogic := '0'; + variable TimingData_pldclk_txvalidvc0 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txvalidvc0, + TimingData => TimingData_pldclk_txvalidvc0, + TestSignal => txvalidvc0_ipd, + TestSignalName => "txvalidvc0", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txvalidvc0_pldclk_noedge_posedge, + SetupLow => tsetup_txvalidvc0_pldclk_noedge_posedge, + HoldHigh => thold_txvalidvc0_pldclk_noedge_posedge, + HoldLow => thold_txvalidvc0_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_txvalidvc1: PROCESS (pldclk_ipd, txvalidvc1_ipd) + variable Tviol_pldclk_txvalidvc1 : std_ulogic := '0'; + variable TimingData_pldclk_txvalidvc1 : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_pldclk_txvalidvc1, + TimingData => TimingData_pldclk_txvalidvc1, + TestSignal => txvalidvc1_ipd, + TestSignalName => "txvalidvc1", + RefSignal => pldclk_ipd, + RefSignalName => "PLDCLK", + SetupHigh => tsetup_txvalidvc1_pldclk_noedge_posedge, + SetupLow => tsetup_txvalidvc1_pldclk_noedge_posedge, + HoldHigh => thold_txvalidvc1_pldclk_noedge_posedge, + HoldLow => thold_txvalidvc1_pldclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + -- TSU/THOLD of dpclk + VITAL_dpriodisable: PROCESS (dpclk_ipd, dpriodisable_ipd) + variable Tviol_dpclk_dpriodisable : std_ulogic := '0'; + variable TimingData_dpclk_dpriodisable : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_dpclk_dpriodisable, + TimingData => TimingData_dpclk_dpriodisable, + TestSignal => dpriodisable_ipd, + TestSignalName => "dpriodisable", + RefSignal => dpclk_ipd, + RefSignalName => "DPCLK", + SetupHigh => tsetup_dpriodisable_dpclk_noedge_posedge, + SetupLow => tsetup_dpriodisable_dpclk_noedge_posedge, + HoldHigh => thold_dpriodisable_dpclk_noedge_posedge, + HoldLow => thold_dpriodisable_dpclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + VITAL_dprioin: PROCESS (dpclk_ipd, dprioin_ipd) + variable Tviol_dpclk_dprioin : std_ulogic := '0'; + variable TimingData_dpclk_dprioin : VitalTimingDataType := VitalTimingDataInit; + BEGIN + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + Violation => Tviol_dpclk_dprioin, + TimingData => TimingData_dpclk_dprioin, + TestSignal => dprioin_ipd, + TestSignalName => "dprioin", + RefSignal => dpclk_ipd, + RefSignalName => "DPCLK", + SetupHigh => tsetup_dprioin_dpclk_noedge_posedge, + SetupLow => tsetup_dprioin_dpclk_noedge_posedge, + HoldHigh => thold_dprioin_dpclk_noedge_posedge, + HoldLow => thold_dprioin_dpclk_noedge_posedge, + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneiv_HSSI_PCIE_HIP", + XOn => XOnChecks, + MsgOn => MsgOnChecks + ); + END IF; + END PROCESS; + + ---------------------- + -- Path Delay Section + ---------------------- + -- TCO of pldclk + VITAL_clrrxpath: PROCESS (pldclk_ipd, clrrxpath_tmp) + variable CQDelayclrrxpath: TIME := 0 ns; + BEGIN + CQDelayclrrxpath := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_clrrxpath_posedge, TRUE))); + clrrxpath <= TRANSPORT clrrxpath_tmp AFTER CQDelayclrrxpath; + END PROCESS; + + VITAL_dlackphypm: PROCESS (pldclk_ipd, dlackphypm_tmp) + variable CQDelaydlackphypm: TIME := 0 ns; + BEGIN + CQDelaydlackphypm := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlackphypm_posedge, TRUE))); + dlackphypm <= TRANSPORT dlackphypm_tmp AFTER CQDelaydlackphypm; + END PROCESS; + + VITAL_dlackrequpfc: PROCESS (pldclk_ipd, dlackrequpfc_tmp) + variable CQDelaydlackrequpfc: TIME := 0 ns; + BEGIN + CQDelaydlackrequpfc := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlackrequpfc_posedge, TRUE))); + dlackrequpfc <= TRANSPORT dlackrequpfc_tmp AFTER CQDelaydlackrequpfc; + END PROCESS; + + VITAL_dlacksndupfc: PROCESS (pldclk_ipd, dlacksndupfc_tmp) + variable CQDelaydlacksndupfc: TIME := 0 ns; + BEGIN + CQDelaydlacksndupfc := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlacksndupfc_posedge, TRUE))); + dlacksndupfc <= TRANSPORT dlacksndupfc_tmp AFTER CQDelaydlacksndupfc; + END PROCESS; + + VITAL_dlcurrentdeemp: PROCESS (pldclk_ipd, dlcurrentdeemp_tmp) + variable CQDelaydlcurrentdeemp: TIME := 0 ns; + BEGIN + CQDelaydlcurrentdeemp := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlcurrentdeemp_posedge, TRUE))); + dlcurrentdeemp <= TRANSPORT dlcurrentdeemp_tmp AFTER CQDelaydlcurrentdeemp; + END PROCESS; + + VITAL_dlcurrentspeed: PROCESS (pldclk_ipd, dlcurrentspeed_tmp) + variable CQDelaydlcurrentspeed: TIME := 0 ns; + BEGIN + CQDelaydlcurrentspeed := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlcurrentspeed_posedge, TRUE))); + dlcurrentspeed <= TRANSPORT dlcurrentspeed_tmp AFTER CQDelaydlcurrentspeed; + END PROCESS; + + VITAL_dldllreq: PROCESS (pldclk_ipd, dldllreq_tmp) + variable CQDelaydldllreq: TIME := 0 ns; + BEGIN + CQDelaydldllreq := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dldllreq_posedge, TRUE))); + dldllreq <= TRANSPORT dldllreq_tmp AFTER CQDelaydldllreq; + END PROCESS; + + VITAL_dlerrdll: PROCESS (pldclk_ipd, dlerrdll_tmp) + variable CQDelaydlerrdll: TIME := 0 ns; + BEGIN + CQDelaydlerrdll := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlerrdll_posedge, TRUE))); + dlerrdll <= TRANSPORT dlerrdll_tmp AFTER CQDelaydlerrdll; + END PROCESS; + + VITAL_dlerrphy: PROCESS (pldclk_ipd, dlerrphy_tmp) + variable CQDelaydlerrphy: TIME := 0 ns; + BEGIN + CQDelaydlerrphy := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlerrphy_posedge, TRUE))); + dlerrphy <= TRANSPORT dlerrphy_tmp AFTER CQDelaydlerrphy; + END PROCESS; + + VITAL_dllinkautobdwstatus: PROCESS (pldclk_ipd, dllinkautobdwstatus_tmp) + variable CQDelaydllinkautobdwstatus: TIME := 0 ns; + BEGIN + CQDelaydllinkautobdwstatus := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dllinkautobdwstatus_posedge, TRUE))); + dllinkautobdwstatus <= TRANSPORT dllinkautobdwstatus_tmp AFTER CQDelaydllinkautobdwstatus; + END PROCESS; + + VITAL_dllinkbdwmngstatus: PROCESS (pldclk_ipd, dllinkbdwmngstatus_tmp) + variable CQDelaydllinkbdwmngstatus: TIME := 0 ns; + BEGIN + CQDelaydllinkbdwmngstatus := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dllinkbdwmngstatus_posedge, TRUE))); + dllinkbdwmngstatus <= TRANSPORT dllinkbdwmngstatus_tmp AFTER CQDelaydllinkbdwmngstatus; + END PROCESS; + + VITAL_dlltssm: PROCESS (pldclk_ipd, dlltssm_tmp) + variable CQDelaydlltssm: TIME := 0 ns; + BEGIN + CQDelaydlltssm := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlltssm_posedge, TRUE))); + dlltssm <= TRANSPORT dlltssm_tmp AFTER CQDelaydlltssm; + END PROCESS; + + VITAL_dlrpbufemp: PROCESS (pldclk_ipd, dlrpbufemp_tmp) + variable CQDelaydlrpbufemp: TIME := 0 ns; + BEGIN + CQDelaydlrpbufemp := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlrpbufemp_posedge, TRUE))); + dlrpbufemp <= TRANSPORT dlrpbufemp_tmp AFTER CQDelaydlrpbufemp; + END PROCESS; + + VITAL_dlrstentercompbit: PROCESS (pldclk_ipd, dlrstentercompbit_tmp) + variable CQDelaydlrstentercompbit: TIME := 0 ns; + BEGIN + CQDelaydlrstentercompbit := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlrstentercompbit_posedge, TRUE))); + dlrstentercompbit <= TRANSPORT dlrstentercompbit_tmp AFTER CQDelaydlrstentercompbit; + END PROCESS; + + VITAL_dlrsttxmarginfield: PROCESS (pldclk_ipd, dlrsttxmarginfield_tmp) + variable CQDelaydlrsttxmarginfield: TIME := 0 ns; + BEGIN + CQDelaydlrsttxmarginfield := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlrsttxmarginfield_posedge, TRUE))); + dlrsttxmarginfield <= TRANSPORT dlrsttxmarginfield_tmp AFTER CQDelaydlrsttxmarginfield; + END PROCESS; + + VITAL_dlrxtyppm: PROCESS (pldclk_ipd, dlrxtyppm_tmp) + variable CQDelaydlrxtyppm: TIME := 0 ns; + BEGIN + CQDelaydlrxtyppm := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlrxtyppm_posedge, TRUE))); + dlrxtyppm <= TRANSPORT dlrxtyppm_tmp AFTER CQDelaydlrxtyppm; + END PROCESS; + + VITAL_dlrxvalpm: PROCESS (pldclk_ipd, dlrxvalpm_tmp) + variable CQDelaydlrxvalpm: TIME := 0 ns; + BEGIN + CQDelaydlrxvalpm := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlrxvalpm_posedge, TRUE))); + dlrxvalpm <= TRANSPORT dlrxvalpm_tmp AFTER CQDelaydlrxvalpm; + END PROCESS; + + VITAL_dltxackpm: PROCESS (pldclk_ipd, dltxackpm_tmp) + variable CQDelaydltxackpm: TIME := 0 ns; + BEGIN + CQDelaydltxackpm := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dltxackpm_posedge, TRUE))); + dltxackpm <= TRANSPORT dltxackpm_tmp AFTER CQDelaydltxackpm; + END PROCESS; + + VITAL_dlup: PROCESS (pldclk_ipd, dlup_tmp) + variable CQDelaydlup: TIME := 0 ns; + BEGIN + CQDelaydlup := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlup_posedge, TRUE))); + dlup <= TRANSPORT dlup_tmp AFTER CQDelaydlup; + END PROCESS; + + VITAL_dlupexit: PROCESS (pldclk_ipd, dlupexit_tmp) + variable CQDelaydlupexit: TIME := 0 ns; + BEGIN + CQDelaydlupexit := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlupexit_posedge, TRUE))); + dlupexit <= TRANSPORT dlupexit_tmp AFTER CQDelaydlupexit; + END PROCESS; + + VITAL_dlvcstatus: PROCESS (pldclk_ipd, dlvcstatus_tmp) + variable CQDelaydlvcstatus: TIME := 0 ns; + BEGIN + CQDelaydlvcstatus := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_dlvcstatus_posedge, TRUE))); + dlvcstatus <= TRANSPORT dlvcstatus_tmp AFTER CQDelaydlvcstatus; + END PROCESS; + + VITAL_ev128ns: PROCESS (pldclk_ipd, ev128ns_tmp) + variable CQDelayev128ns: TIME := 0 ns; + BEGIN + CQDelayev128ns := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_ev128ns_posedge, TRUE))); + ev128ns <= TRANSPORT ev128ns_tmp AFTER CQDelayev128ns; + END PROCESS; + + VITAL_ev1us: PROCESS (pldclk_ipd, ev1us_tmp) + variable CQDelayev1us: TIME := 0 ns; + BEGIN + CQDelayev1us := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_ev1us_posedge, TRUE))); + ev1us <= TRANSPORT ev1us_tmp AFTER CQDelayev1us; + END PROCESS; + + VITAL_extraclkout: PROCESS (pldclk_ipd, extraclkout_tmp) + variable CQDelayextraclkout: TIME := 0 ns; + BEGIN + CQDelayextraclkout := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_extraclkout_posedge, TRUE))); + extraclkout <= TRANSPORT extraclkout_tmp AFTER CQDelayextraclkout; + END PROCESS; + + VITAL_hotrstexit: PROCESS (pldclk_ipd, hotrstexit_tmp) + variable CQDelayhotrstexit: TIME := 0 ns; + BEGIN + CQDelayhotrstexit := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_hotrstexit_posedge, TRUE))); + hotrstexit <= TRANSPORT hotrstexit_tmp AFTER CQDelayhotrstexit; + END PROCESS; + + VITAL_intstatus: PROCESS (pldclk_ipd, intstatus_tmp) + variable CQDelayintstatus: TIME := 0 ns; + BEGIN + CQDelayintstatus := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_intstatus_posedge, TRUE))); + intstatus <= TRANSPORT intstatus_tmp AFTER CQDelayintstatus; + END PROCESS; + + VITAL_l2exit: PROCESS (pldclk_ipd, l2exit_tmp) + variable CQDelayl2exit: TIME := 0 ns; + BEGIN + CQDelayl2exit := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_l2exit_posedge, TRUE))); + l2exit <= TRANSPORT l2exit_tmp AFTER CQDelayl2exit; + END PROCESS; + + VITAL_laneact: PROCESS (pldclk_ipd, laneact_tmp) + variable CQDelaylaneact: TIME := 0 ns; + BEGIN + CQDelaylaneact := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_laneact_posedge, TRUE))); + laneact <= TRANSPORT laneact_tmp AFTER CQDelaylaneact; + END PROCESS; + + VITAL_linkup: PROCESS (pldclk_ipd, linkup_tmp) + variable CQDelaylinkup: TIME := 0 ns; + BEGIN + CQDelaylinkup := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_linkup_posedge, TRUE))); + linkup <= TRANSPORT linkup_tmp AFTER CQDelaylinkup; + END PROCESS; + + VITAL_lmiack: PROCESS (pldclk_ipd, lmiack_tmp) + variable CQDelaylmiack: TIME := 0 ns; + BEGIN + CQDelaylmiack := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_lmiack_posedge, TRUE))); + lmiack <= TRANSPORT lmiack_tmp AFTER CQDelaylmiack; + END PROCESS; + + VITAL_lmidout: PROCESS (pldclk_ipd, lmidout_tmp) + variable CQDelaylmidout: TIME := 0 ns; + BEGIN + CQDelaylmidout := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_lmidout_posedge, TRUE))); + lmidout <= TRANSPORT lmidout_tmp AFTER CQDelaylmidout; + END PROCESS; + + VITAL_resetstatus: PROCESS (pldclk_ipd, resetstatus_tmp) + variable CQDelayresetstatus: TIME := 0 ns; + BEGIN + CQDelayresetstatus := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_resetstatus_posedge, TRUE))); + resetstatus <= TRANSPORT resetstatus_tmp AFTER CQDelayresetstatus; + END PROCESS; + + VITAL_rxbardecvc0: PROCESS (pldclk_ipd, rxbardecvc0_tmp) + variable CQDelayrxbardecvc0: TIME := 0 ns; + BEGIN + CQDelayrxbardecvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxbardecvc0_posedge, TRUE))); + rxbardecvc0 <= TRANSPORT rxbardecvc0_tmp AFTER CQDelayrxbardecvc0; + END PROCESS; + + VITAL_rxbardecvc1: PROCESS (pldclk_ipd, rxbardecvc1_tmp) + variable CQDelayrxbardecvc1: TIME := 0 ns; + BEGIN + CQDelayrxbardecvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxbardecvc1_posedge, TRUE))); + rxbardecvc1 <= TRANSPORT rxbardecvc1_tmp AFTER CQDelayrxbardecvc1; + END PROCESS; + + VITAL_rxbevc00: PROCESS (pldclk_ipd, rxbevc00_tmp) + variable CQDelayrxbevc00: TIME := 0 ns; + BEGIN + CQDelayrxbevc00 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxbevc00_posedge, TRUE))); + rxbevc00 <= TRANSPORT rxbevc00_tmp AFTER CQDelayrxbevc00; + END PROCESS; + + VITAL_rxbevc01: PROCESS (pldclk_ipd, rxbevc01_tmp) + variable CQDelayrxbevc01: TIME := 0 ns; + BEGIN + CQDelayrxbevc01 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxbevc01_posedge, TRUE))); + rxbevc01 <= TRANSPORT rxbevc01_tmp AFTER CQDelayrxbevc01; + END PROCESS; + + VITAL_rxbevc10: PROCESS (pldclk_ipd, rxbevc10_tmp) + variable CQDelayrxbevc10: TIME := 0 ns; + BEGIN + CQDelayrxbevc10 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxbevc10_posedge, TRUE))); + rxbevc10 <= TRANSPORT rxbevc10_tmp AFTER CQDelayrxbevc10; + END PROCESS; + + VITAL_rxbevc11: PROCESS (pldclk_ipd, rxbevc11_tmp) + variable CQDelayrxbevc11: TIME := 0 ns; + BEGIN + CQDelayrxbevc11 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxbevc11_posedge, TRUE))); + rxbevc11 <= TRANSPORT rxbevc11_tmp AFTER CQDelayrxbevc11; + END PROCESS; + + VITAL_rxdatavc00: PROCESS (pldclk_ipd, rxdatavc00_tmp) + variable CQDelayrxdatavc00: TIME := 0 ns; + BEGIN + CQDelayrxdatavc00 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxdatavc00_posedge, TRUE))); + rxdatavc00 <= TRANSPORT rxdatavc00_tmp AFTER CQDelayrxdatavc00; + END PROCESS; + + VITAL_rxdatavc01: PROCESS (pldclk_ipd, rxdatavc01_tmp) + variable CQDelayrxdatavc01: TIME := 0 ns; + BEGIN + CQDelayrxdatavc01 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxdatavc01_posedge, TRUE))); + rxdatavc01 <= TRANSPORT rxdatavc01_tmp AFTER CQDelayrxdatavc01; + END PROCESS; + + VITAL_rxdatavc10: PROCESS (pldclk_ipd, rxdatavc10_tmp) + variable CQDelayrxdatavc10: TIME := 0 ns; + BEGIN + CQDelayrxdatavc10 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxdatavc10_posedge, TRUE))); + rxdatavc10 <= TRANSPORT rxdatavc10_tmp AFTER CQDelayrxdatavc10; + END PROCESS; + + VITAL_rxdatavc11: PROCESS (pldclk_ipd, rxdatavc11_tmp) + variable CQDelayrxdatavc11: TIME := 0 ns; + BEGIN + CQDelayrxdatavc11 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxdatavc11_posedge, TRUE))); + rxdatavc11 <= TRANSPORT rxdatavc11_tmp AFTER CQDelayrxdatavc11; + END PROCESS; + + VITAL_rxeopvc00: PROCESS (pldclk_ipd, rxeopvc00_tmp) + variable CQDelayrxeopvc00: TIME := 0 ns; + BEGIN + CQDelayrxeopvc00 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxeopvc00_posedge, TRUE))); + rxeopvc00 <= TRANSPORT rxeopvc00_tmp AFTER CQDelayrxeopvc00; + END PROCESS; + + VITAL_rxeopvc01: PROCESS (pldclk_ipd, rxeopvc01_tmp) + variable CQDelayrxeopvc01: TIME := 0 ns; + BEGIN + CQDelayrxeopvc01 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxeopvc01_posedge, TRUE))); + rxeopvc01 <= TRANSPORT rxeopvc01_tmp AFTER CQDelayrxeopvc01; + END PROCESS; + + VITAL_rxeopvc10: PROCESS (pldclk_ipd, rxeopvc10_tmp) + variable CQDelayrxeopvc10: TIME := 0 ns; + BEGIN + CQDelayrxeopvc10 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxeopvc10_posedge, TRUE))); + rxeopvc10 <= TRANSPORT rxeopvc10_tmp AFTER CQDelayrxeopvc10; + END PROCESS; + + VITAL_rxeopvc11: PROCESS (pldclk_ipd, rxeopvc11_tmp) + variable CQDelayrxeopvc11: TIME := 0 ns; + BEGIN + CQDelayrxeopvc11 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxeopvc11_posedge, TRUE))); + rxeopvc11 <= TRANSPORT rxeopvc11_tmp AFTER CQDelayrxeopvc11; + END PROCESS; + + VITAL_rxerrvc0: PROCESS (pldclk_ipd, rxerrvc0_tmp) + variable CQDelayrxerrvc0: TIME := 0 ns; + BEGIN + CQDelayrxerrvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxerrvc0_posedge, TRUE))); + rxerrvc0 <= TRANSPORT rxerrvc0_tmp AFTER CQDelayrxerrvc0; + END PROCESS; + + VITAL_rxerrvc1: PROCESS (pldclk_ipd, rxerrvc1_tmp) + variable CQDelayrxerrvc1: TIME := 0 ns; + BEGIN + CQDelayrxerrvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxerrvc1_posedge, TRUE))); + rxerrvc1 <= TRANSPORT rxerrvc1_tmp AFTER CQDelayrxerrvc1; + END PROCESS; + + VITAL_rxfifoemptyvc0: PROCESS (pldclk_ipd, rxfifoemptyvc0_tmp) + variable CQDelayrxfifoemptyvc0: TIME := 0 ns; + BEGIN + CQDelayrxfifoemptyvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxfifoemptyvc0_posedge, TRUE))); + rxfifoemptyvc0 <= TRANSPORT rxfifoemptyvc0_tmp AFTER CQDelayrxfifoemptyvc0; + END PROCESS; + + VITAL_rxfifoemptyvc1: PROCESS (pldclk_ipd, rxfifoemptyvc1_tmp) + variable CQDelayrxfifoemptyvc1: TIME := 0 ns; + BEGIN + CQDelayrxfifoemptyvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxfifoemptyvc1_posedge, TRUE))); + rxfifoemptyvc1 <= TRANSPORT rxfifoemptyvc1_tmp AFTER CQDelayrxfifoemptyvc1; + END PROCESS; + + VITAL_rxfifofullvc0: PROCESS (pldclk_ipd, rxfifofullvc0_tmp) + variable CQDelayrxfifofullvc0: TIME := 0 ns; + BEGIN + CQDelayrxfifofullvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxfifofullvc0_posedge, TRUE))); + rxfifofullvc0 <= TRANSPORT rxfifofullvc0_tmp AFTER CQDelayrxfifofullvc0; + END PROCESS; + + VITAL_rxfifofullvc1: PROCESS (pldclk_ipd, rxfifofullvc1_tmp) + variable CQDelayrxfifofullvc1: TIME := 0 ns; + BEGIN + CQDelayrxfifofullvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxfifofullvc1_posedge, TRUE))); + rxfifofullvc1 <= TRANSPORT rxfifofullvc1_tmp AFTER CQDelayrxfifofullvc1; + END PROCESS; + + VITAL_rxsopvc00: PROCESS (pldclk_ipd, rxsopvc00_tmp) + variable CQDelayrxsopvc00: TIME := 0 ns; + BEGIN + CQDelayrxsopvc00 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxsopvc00_posedge, TRUE))); + rxsopvc00 <= TRANSPORT rxsopvc00_tmp AFTER CQDelayrxsopvc00; + END PROCESS; + + VITAL_rxsopvc01: PROCESS (pldclk_ipd, rxsopvc01_tmp) + variable CQDelayrxsopvc01: TIME := 0 ns; + BEGIN + CQDelayrxsopvc01 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxsopvc01_posedge, TRUE))); + rxsopvc01 <= TRANSPORT rxsopvc01_tmp AFTER CQDelayrxsopvc01; + END PROCESS; + + VITAL_rxsopvc10: PROCESS (pldclk_ipd, rxsopvc10_tmp) + variable CQDelayrxsopvc10: TIME := 0 ns; + BEGIN + CQDelayrxsopvc10 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxsopvc10_posedge, TRUE))); + rxsopvc10 <= TRANSPORT rxsopvc10_tmp AFTER CQDelayrxsopvc10; + END PROCESS; + + VITAL_rxsopvc11: PROCESS (pldclk_ipd, rxsopvc11_tmp) + variable CQDelayrxsopvc11: TIME := 0 ns; + BEGIN + CQDelayrxsopvc11 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxsopvc11_posedge, TRUE))); + rxsopvc11 <= TRANSPORT rxsopvc11_tmp AFTER CQDelayrxsopvc11; + END PROCESS; + + VITAL_rxvalidvc0: PROCESS (pldclk_ipd, rxvalidvc0_tmp) + variable CQDelayrxvalidvc0: TIME := 0 ns; + BEGIN + CQDelayrxvalidvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxvalidvc0_posedge, TRUE))); + rxvalidvc0 <= TRANSPORT rxvalidvc0_tmp AFTER CQDelayrxvalidvc0; + END PROCESS; + + VITAL_rxvalidvc1: PROCESS (pldclk_ipd, rxvalidvc1_tmp) + variable CQDelayrxvalidvc1: TIME := 0 ns; + BEGIN + CQDelayrxvalidvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_rxvalidvc1_posedge, TRUE))); + rxvalidvc1 <= TRANSPORT rxvalidvc1_tmp AFTER CQDelayrxvalidvc1; + END PROCESS; + + VITAL_r2cerr0ext : PROCESS (pldclk_ipd, r2cerr0ext_tmp) + variable CQDelayr2cerr0ext: TIME := 0 ns; + BEGIN + CQDelayr2cerr0ext := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_r2cerr0ext_posedge, TRUE))); + r2cerr0ext <= TRANSPORT r2cerr0ext_tmp AFTER CQDelayr2cerr0ext; + END PROCESS; + + VITAL_serrout: PROCESS (pldclk_ipd, serrout_tmp) + variable CQDelayserrout: TIME := 0 ns; + BEGIN + CQDelayserrout := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_serrout_posedge, TRUE))); + serrout <= TRANSPORT serrout_tmp AFTER CQDelayserrout; + END PROCESS; + + VITAL_successspeednegoint: PROCESS (pldclk_ipd, successspeednegoint_tmp) + variable CQDelaysuccessspeednegoint: TIME := 0 ns; + BEGIN + CQDelaysuccessspeednegoint := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_successspeednegoint_posedge, TRUE))); + successspeednegoint <= TRANSPORT successspeednegoint_tmp AFTER CQDelaysuccessspeednegoint; + END PROCESS; + + VITAL_swdnwake: PROCESS (pldclk_ipd, swdnwake_tmp) + variable CQDelayswdnwake: TIME := 0 ns; + BEGIN + CQDelayswdnwake := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_swdnwake_posedge, TRUE))); + swdnwake <= TRANSPORT swdnwake_tmp AFTER CQDelayswdnwake; + END PROCESS; + + VITAL_swuphotrst: PROCESS (pldclk_ipd, swuphotrst_tmp) + variable CQDelayswuphotrst: TIME := 0 ns; + BEGIN + CQDelayswuphotrst := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_swuphotrst_posedge, TRUE))); + swuphotrst <= TRANSPORT swuphotrst_tmp AFTER CQDelayswuphotrst; + END PROCESS; + + VITAL_tlappintaack: PROCESS (pldclk_ipd, tlappintaack_tmp) + variable CQDelaytlappintaack: TIME := 0 ns; + BEGIN + CQDelaytlappintaack := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_tlappintaack_posedge, TRUE))); + tlappintaack <= TRANSPORT tlappintaack_tmp AFTER CQDelaytlappintaack; + END PROCESS; + + VITAL_tlappmsiack: PROCESS (pldclk_ipd, tlappmsiack_tmp) + variable CQDelaytlappmsiack: TIME := 0 ns; + BEGIN + CQDelaytlappmsiack := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_tlappmsiack_posedge, TRUE))); + tlappmsiack <= TRANSPORT tlappmsiack_tmp AFTER CQDelaytlappmsiack; + END PROCESS; + + VITAL_tlpmetosr: PROCESS (pldclk_ipd, tlpmetosr_tmp) + variable CQDelaytlpmetosr: TIME := 0 ns; + BEGIN + CQDelaytlpmetosr := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_tlpmetosr_posedge, TRUE))); + tlpmetosr <= TRANSPORT tlpmetosr_tmp AFTER CQDelaytlpmetosr; + END PROCESS; + + VITAL_txcredvc0: PROCESS (pldclk_ipd, txcredvc0_tmp) + variable CQDelaytxcredvc0: TIME := 0 ns; + BEGIN + CQDelaytxcredvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txcredvc0_posedge, TRUE))); + txcredvc0 <= TRANSPORT txcredvc0_tmp AFTER CQDelaytxcredvc0; + END PROCESS; + + VITAL_txcredvc1: PROCESS (pldclk_ipd, txcredvc1_tmp) + variable CQDelaytxcredvc1: TIME := 0 ns; + BEGIN + CQDelaytxcredvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txcredvc1_posedge, TRUE))); + txcredvc1 <= TRANSPORT txcredvc1_tmp AFTER CQDelaytxcredvc1; + END PROCESS; + + VITAL_txfifoemptyvc0: PROCESS (pldclk_ipd, txfifoemptyvc0_tmp) + variable CQDelaytxfifoemptyvc0: TIME := 0 ns; + BEGIN + CQDelaytxfifoemptyvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifoemptyvc0_posedge, TRUE))); + txfifoemptyvc0 <= TRANSPORT txfifoemptyvc0_tmp AFTER CQDelaytxfifoemptyvc0; + END PROCESS; + + VITAL_txfifoemptyvc1: PROCESS (pldclk_ipd, txfifoemptyvc1_tmp) + variable CQDelaytxfifoemptyvc1: TIME := 0 ns; + BEGIN + CQDelaytxfifoemptyvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifoemptyvc1_posedge, TRUE))); + txfifoemptyvc1 <= TRANSPORT txfifoemptyvc1_tmp AFTER CQDelaytxfifoemptyvc1; + END PROCESS; + + VITAL_txfifofullvc0: PROCESS (pldclk_ipd, txfifofullvc0_tmp) + variable CQDelaytxfifofullvc0: TIME := 0 ns; + BEGIN + CQDelaytxfifofullvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifofullvc0_posedge, TRUE))); + txfifofullvc0 <= TRANSPORT txfifofullvc0_tmp AFTER CQDelaytxfifofullvc0; + END PROCESS; + + VITAL_txfifofullvc1: PROCESS (pldclk_ipd, txfifofullvc1_tmp) + variable CQDelaytxfifofullvc1: TIME := 0 ns; + BEGIN + CQDelaytxfifofullvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifofullvc1_posedge, TRUE))); + txfifofullvc1 <= TRANSPORT txfifofullvc1_tmp AFTER CQDelaytxfifofullvc1; + END PROCESS; + + VITAL_txfifordpvc0: PROCESS (pldclk_ipd, txfifordpvc0_tmp) + variable CQDelaytxfifordpvc0: TIME := 0 ns; + BEGIN + CQDelaytxfifordpvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifordpvc0_posedge, TRUE))); + txfifordpvc0 <= TRANSPORT txfifordpvc0_tmp AFTER CQDelaytxfifordpvc0; + END PROCESS; + + VITAL_txfifordpvc1: PROCESS (pldclk_ipd, txfifordpvc1_tmp) + variable CQDelaytxfifordpvc1: TIME := 0 ns; + BEGIN + CQDelaytxfifordpvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifordpvc1_posedge, TRUE))); + txfifordpvc1 <= TRANSPORT txfifordpvc1_tmp AFTER CQDelaytxfifordpvc1; + END PROCESS; + + VITAL_txfifowrpvc0: PROCESS (pldclk_ipd, txfifowrpvc0_tmp) + variable CQDelaytxfifowrpvc0: TIME := 0 ns; + BEGIN + CQDelaytxfifowrpvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifowrpvc0_posedge, TRUE))); + txfifowrpvc0 <= TRANSPORT txfifowrpvc0_tmp AFTER CQDelaytxfifowrpvc0; + END PROCESS; + + VITAL_txfifowrpvc1: PROCESS (pldclk_ipd, txfifowrpvc1_tmp) + variable CQDelaytxfifowrpvc1: TIME := 0 ns; + BEGIN + CQDelaytxfifowrpvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txfifowrpvc1_posedge, TRUE))); + txfifowrpvc1 <= TRANSPORT txfifowrpvc1_tmp AFTER CQDelaytxfifowrpvc1; + END PROCESS; + + VITAL_txreadyvc0: PROCESS (pldclk_ipd, txreadyvc0_tmp) + variable CQDelaytxreadyvc0: TIME := 0 ns; + BEGIN + CQDelaytxreadyvc0 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txreadyvc0_posedge, TRUE))); + txreadyvc0 <= TRANSPORT txreadyvc0_tmp AFTER CQDelaytxreadyvc0; + END PROCESS; + + VITAL_txreadyvc1: PROCESS (pldclk_ipd, txreadyvc1_tmp) + variable CQDelaytxreadyvc1: TIME := 0 ns; + BEGIN + CQDelaytxreadyvc1 := hssiSelectDelay ( + Paths => (0 => (pldclk_ipd'last_event, tpd_pldclk_txreadyvc1_posedge, TRUE))); + txreadyvc1 <= TRANSPORT txreadyvc1_tmp AFTER CQDelaytxreadyvc1; + END PROCESS; + + -- TCO of dpclk + VITAL_dataenablen: PROCESS (dpclk_ipd, dataenablen_tmp) + variable CQDelaydataenablen: TIME := 0 ns; + BEGIN + CQDelaydataenablen := hssiSelectDelay ( + Paths => (0 => (dpclk_ipd'last_event, tpd_dpclk_dataenablen_posedge, TRUE))); + dataenablen <= TRANSPORT dataenablen_tmp AFTER CQDelaydataenablen; + END PROCESS; + + VITAL_dprioout: PROCESS (dpclk_ipd, dprioout_tmp) + variable CQDelaydprioout: TIME := 0 ns; + BEGIN + CQDelaydprioout := hssiSelectDelay ( + Paths => (0 => (dpclk_ipd'last_event, tpd_dpclk_dprioout_posedge, TRUE))); + dprioout <= TRANSPORT dprioout_tmp AFTER CQDelaydprioout; + END PROCESS; + + VITAL_dpriostate: PROCESS (dpclk_ipd, dpriostate_tmp) + variable CQDelaydpriostate: TIME := 0 ns; + BEGIN + CQDelaydpriostate := hssiSelectDelay ( + Paths => (0 => (dpclk_ipd'last_event, tpd_dpclk_dpriostate_posedge, TRUE))); + dpriostate <= TRANSPORT dpriostate_tmp AFTER CQDelaydpriostate; + END PROCESS; + + +END trans; + + + +-- cycloneiv_hssi_pcie_hip() \ No newline at end of file diff --git a/Common/sim/altera/cycloneiv_pcie_hip_components.vhd b/Common/sim/altera/cycloneiv_pcie_hip_components.vhd new file mode 100644 index 0000000..5ee34e7 --- /dev/null +++ b/Common/sim/altera/cycloneiv_pcie_hip_components.vhd @@ -0,0 +1,1201 @@ +-- Copyright (C) Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; + +USE IEEE.vital_timing.ALL; +USE IEEE.vital_primitives.ALL; + + +package CYCLONEIV_PCIE_HIP_COMPONENTS is + + + +-- VITAL constants BEGIN +-- default generic values + CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns); + CONSTANT DefSetupHoldCnst : TIME := 0 ns; + CONSTANT DefPulseWdthCnst : TIME := 0 ns; +-- default control options +-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent; +-- change default delay type to Transport : for spr 68748 + CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport; + CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE; + CONSTANT DefGlitchXOn : BOOLEAN := FALSE; + CONSTANT DefMsgOnChecks : BOOLEAN := TRUE; + CONSTANT DefXOnChecks : BOOLEAN := TRUE; +-- output strength mapping + -- UX01ZWHL- + CONSTANT PullUp : VitalOutputMapType := "UX01HX01X"; + CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X"; + CONSTANT PullDown : VitalOutputMapType := "UX01LX01X"; +-- primitive result strength mapping + CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' ); + CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' ); + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) +-- VITAL constants END + +-- GENERIC utility functions BEGIN +function str2bin (s : string) return std_logic_vector; +function str2int (s : string) return integer; +function int2bin (arg : integer; size : integer) return std_logic_vector; +function tx_top_ctrl_in_width( + double_data_mode : string; + ser_double_data_mode : string +) return integer; +function rx_top_a1k1_out_width(des_double_data_mode : string) return integer; +function rx_top_ctrl_out_width( + double_data_mode : string; + des_double_data_mode : string +) return integer; + +-- GENERIC utility functions BEGIN +function bin2int (s : std_logic_vector) return integer; +function bin2int (s : std_logic) return integer; +function int2bit (arg : boolean) return std_logic; +function int2bin (arg : boolean; size : integer) return std_logic_vector; +function int2bit (arg : integer) return std_logic; +function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector; +function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector; +function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic; +function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic; +function reduction_or (val : std_logic_vector) return std_logic; +function reduction_nor (val : std_logic_vector) return std_logic; +function reduction_xor (val : std_logic_vector) return std_logic; +function reduction_and (val : std_logic_vector) return std_logic; +function reduction_nand (val : std_logic_vector) return std_logic; + +function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME; +function alpha_tolower (given_string : string) return string; + +-- GENERIC utility functions END + + +-- +-- cycloneiv_pciehip_pciexp_dcfiforam +-- + +COMPONENT cycloneiv_pciehip_pciexp_dcfiforam + GENERIC ( + addr_width : INTEGER := 4; + data_width : INTEGER := 32 + ); + PORT ( + data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0); + wren : IN STD_LOGIC; + wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0); + wrclock : IN STD_LOGIC; + rdclock : IN STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +-- +-- cycloneiv_hssi_pcie_hip +-- + +COMPONENT cycloneiv_hssi_pcie_hip + GENERIC ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : String := "*"; + TimingChecksOn : Boolean := True; + tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01; + tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01; + tipd_bistenrpl : VitalDelayType01 := DefpropDelay01; + tipd_bistscanen : VitalDelayType01 := DefpropDelay01; + tipd_bistscanin : VitalDelayType01 := DefpropDelay01; + tipd_bisttesten : VitalDelayType01 := DefpropDelay01; + tipd_coreclkin : VitalDelayType01 := DefpropDelay01; + tipd_corecrst : VitalDelayType01 := DefpropDelay01; + tipd_corepor : VitalDelayType01 := DefpropDelay01; + tipd_corerst : VitalDelayType01 := DefpropDelay01; + tipd_coresrst : VitalDelayType01 := DefpropDelay01; + tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_cplpending : VitalDelayType01 := DefpropDelay01; + tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01; + tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01; + tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01; + tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01; + tipd_dlreqwake : VitalDelayType01 := DefpropDelay01; + tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01; + tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01; + tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01; + tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01; + tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_dpclk : VitalDelayType01 := DefpropDelay01; + tipd_dpriodisable : VitalDelayType01 := DefpropDelay01; + tipd_dprioin : VitalDelayType01 := DefpropDelay01; + tipd_dprioload : VitalDelayType01 := DefpropDelay01; + tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_lmirden : VitalDelayType01 := DefpropDelay01; + tipd_lmiwren : VitalDelayType01 := DefpropDelay01; + tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01; + tipd_mramregscanen : VitalDelayType01 := DefpropDelay01; + tipd_mramregscanin : VitalDelayType01 := DefpropDelay01; + tipd_pclkcentral : VitalDelayType01 := DefpropDelay01; + tipd_pclkch0 : VitalDelayType01 := DefpropDelay01; + tipd_phyrst : VitalDelayType01 := DefpropDelay01; + tipd_physrst : VitalDelayType01 := DefpropDelay01; + tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_pldclk : VitalDelayType01 := DefpropDelay01; + tipd_pldrst : VitalDelayType01 := DefpropDelay01; + tipd_pldsrst : VitalDelayType01 := DefpropDelay01; + tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01; + tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01; + tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01; + tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01; + tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01; + tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_scanen : VitalDelayType01 := DefpropDelay01; + tipd_scanmoden : VitalDelayType01 := DefpropDelay01; + tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlappintasts : VitalDelayType01 := DefpropDelay01; + tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01; + tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01; + tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01; + tipd_tlpmevent : VitalDelayType01 := DefpropDelay01; + tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01; + tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01; + tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01; + tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01; + tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01; + tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01; + tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01; + tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01; + tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01; + tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01; + tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01; + tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01; + tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01; + tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01; + tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + lpm_type : STRING := "cycloneiv_hssi_pcie_hip"; + advanced_errors : STRING := "false"; + allow_rx_valid_empty : STRING := "false"; -- july3,2008 + bar0_64bit_mem_space : STRING := "true"; + bar0_io_space : STRING := "false"; + bar0_prefetchable : STRING := "true"; + bar0_size_mask : INTEGER := 32; + bar1_64bit_mem_space : STRING := "false"; + bar1_io_space : STRING := "false"; + bar1_prefetchable : STRING := "false"; + bar1_size_mask : INTEGER := 4; + bar2_64bit_mem_space : STRING := "false"; + bar2_io_space : STRING := "false"; + bar2_prefetchable : STRING := "false"; + bar2_size_mask : INTEGER := 4; + bar3_64bit_mem_space : STRING := "false"; + bar3_io_space : STRING := "false"; + bar3_prefetchable : STRING := "false"; + bar3_size_mask : INTEGER := 4; + bar4_64bit_mem_space : STRING := "false"; + bar4_io_space : STRING := "false"; + bar4_prefetchable : STRING := "false"; + bar4_size_mask : INTEGER := 4; + bar5_64bit_mem_space : STRING := "false"; + bar5_io_space : STRING := "false"; + bar5_prefetchable : STRING := "false"; + bar5_size_mask : INTEGER := 4; + bar_io_window_size : STRING := "NONE"; + bar_prefetchable : INTEGER := 0; + base_address : INTEGER := 0; + bridge_port_ssid_support : STRING := "false"; + bridge_port_vga_enable : STRING := "false"; + bypass_cdc : STRING := "false"; + bypass_tl : STRING := "false"; + class_code : INTEGER := 16711680; + completion_timeout : STRING := "ABCD"; + core_clk_divider : INTEGER := 1; + core_clk_source : STRING := "PLL_FIXED_CLK"; + credit_buffer_allocation_aux : STRING := "BALANCED"; + deemphasis_enable : STRING := "false"; + device_address : INTEGER := 0; + device_id : INTEGER := 1; + device_number : INTEGER := 0; + diffclock_nfts_count : INTEGER := 128; + disable_async_l2_logic : STRING := "false"; -- july2,2008 + disable_cdc_clk_ppm : STRING := "true"; + disable_device_number_mismatch : STRING := "false"; + disable_link_x2_support : STRING := "false"; + disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + dll_active_report_support : STRING := "false"; + ei_delay_powerdown_count : INTEGER := 10; + eie_before_nfts_count : INTEGER := 4; + enable_adapter_half_rate_mode : STRING := "false"; + enable_ch0_pclk_out : STRING := "false"; + enable_completion_timeout_disable : STRING := "true"; + enable_coreclk_out_half_rate : STRING := "false"; + enable_d1pm_support : STRING := "false"; + enable_d2pm_support : STRING := "false"; + enable_ecrc_check : STRING := "false"; + enable_ecrc_gen : STRING := "false"; + enable_function_msi_support : STRING := "true"; + enable_function_msix_support : STRING := "false"; + enable_gen2_core : STRING := "true"; + enable_hip_x1_loopback : STRING := "false"; + enable_l1_aspm : STRING := "false"; + enable_msi_64bit_addressing : STRING := "true"; + enable_msi_masking : STRING := "false"; + enable_rcv0buf_a_we : STRING := "true"; + enable_rcv0buf_b_re : STRING := "true"; + enable_rcv0buf_output_regs : STRING := "false"; + enable_rcv1buf_a_we : STRING := "true"; + enable_rcv1buf_b_re : STRING := "true"; + enable_rcv1buf_output_regs : STRING := "false"; + enable_retrybuf_a_we : STRING := "true"; + enable_retrybuf_b_re : STRING := "true"; + enable_retrybuf_ecc : STRING := "false"; -- ww12 + enable_retrybuf_output_regs : STRING := "false"; + enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx0buf_ecc : STRING := "false"; -- ww12 + enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx1buf_ecc : STRING := "false"; -- ww12 + enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12 + enable_rx_buffer_checking : STRING := "false"; + enable_rx_ei_l0s_exit_refined : STRING := "false"; + enable_rx_reordering : STRING := "true"; + enable_slot_register : STRING := "false"; + endpoint_l0_latency : INTEGER := 0; + endpoint_l1_latency : INTEGER := 0; + expansion_base_address_register : INTEGER := 0; + extend_tag_field : STRING := "false"; + fc_init_timer : INTEGER := 1024; + flow_control_timeout_count : INTEGER := 200; + flow_control_update_count : INTEGER := 30; + gen2_diffclock_nfts_count : INTEGER := 255; + gen2_lane_rate_mode : STRING := "false"; + gen2_sameclock_nfts_count : INTEGER := 255; + hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + iei_logic : STRING := "IEI_IIIS"; + indicator : INTEGER := 7; + l01_entry_latency : INTEGER := 31; + l0_exit_latency_diffclock : INTEGER := 6; + l0_exit_latency_sameclock : INTEGER := 6; + l1_exit_latency_diffclock : INTEGER := 0; + l1_exit_latency_sameclock : INTEGER := 0; + lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000"; + low_priority_vc : INTEGER := 0; + max_link_width : INTEGER := 4; + max_payload_size : INTEGER := 2; + maximum_current : INTEGER := 0; + migrated_from_prev_family : STRING := "false"; + millisecond_cycle_count : INTEGER := 0; + mram_bist_settings : STRING := ""; + msi_function_count : INTEGER := 2; + msix_pba_bir : INTEGER := 0; + msix_pba_offset : INTEGER := 0; + msix_table_bir : INTEGER := 0; + msix_table_offset : INTEGER := 0; + msix_table_size : INTEGER := 0; + no_command_completed : STRING := "true"; + no_soft_reset : STRING := "false"; + pcie_mode : STRING := "SHARED_MODE"; + pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; + port_link_number : INTEGER := 1; + port_address : INTEGER := 0; + register_pipe_signals : STRING := "false"; + retry_buffer_last_active_address : INTEGER := 2047; + retry_buffer_memory_settings : INTEGER := 0; + revision_id : INTEGER := 1; + rx0_adap_fifo_full_value : INTEGER := 9; + rx1_adap_fifo_full_value : INTEGER := 9; + rx_cdc_full_value : INTEGER := 12; + rx_idl_os_count : INTEGER := 0; + rx_ptr0_nonposted_dpram_max : INTEGER := 0; + rx_ptr0_nonposted_dpram_min : INTEGER := 0; + rx_ptr0_posted_dpram_max : INTEGER := 0; + rx_ptr0_posted_dpram_min : INTEGER := 0; + rx_ptr1_nonposted_dpram_max : INTEGER := 0; + rx_ptr1_nonposted_dpram_min : INTEGER := 0; + rx_ptr1_posted_dpram_max : INTEGER := 0; + rx_ptr1_posted_dpram_min : INTEGER := 0; + sameclock_nfts_count : INTEGER := 128; + single_rx_detect : INTEGER := 0; + skp_os_schedule_count : INTEGER := 0; + slot_number : INTEGER := 0; + slot_power_limit : INTEGER := 0; + slot_power_scale : INTEGER := 0; + ssid : INTEGER := 0; + ssvid : INTEGER := 0; + subsystem_device_id : INTEGER := 1; + subsystem_vendor_id : INTEGER := 4466; + surprise_down_error_support : STRING := "false"; + tx0_adap_fifo_full_value : INTEGER := 11; + tx1_adap_fifo_full_value : INTEGER := 11; + tx_cdc_full_value : INTEGER := 12; + tx_cdc_stop_dummy_full_value : INTEGER := 11; + use_crc_forwarding : STRING := "false"; + vc0_clk_enable : STRING := "true"; + vc0_rx_buffer_memory_settings : INTEGER := 0; + vc0_rx_flow_ctrl_compl_data : INTEGER := 448; + vc0_rx_flow_ctrl_compl_header : INTEGER := 112; + vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc0_rx_flow_ctrl_posted_data : INTEGER := 360; + vc0_rx_flow_ctrl_posted_header : INTEGER := 50; + vc1_clk_enable : STRING := "false"; + vc1_rx_buffer_memory_settings : INTEGER := 0; + vc1_rx_flow_ctrl_compl_data : INTEGER := 448; + vc1_rx_flow_ctrl_compl_header : INTEGER := 112; + vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0; + vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54; + vc1_rx_flow_ctrl_posted_data : INTEGER := 360; + vc1_rx_flow_ctrl_posted_header : INTEGER := 50; + vc_arbitration : INTEGER := 1; + vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000"; + vendor_id : INTEGER := 4466 + ); + PORT ( + bistenrcv0 : IN STD_LOGIC := '0'; + bistenrcv1 : IN STD_LOGIC := '0'; + bistenrpl : IN STD_LOGIC := '0'; + bistscanen : IN STD_LOGIC := '0'; + bistscanin : IN STD_LOGIC := '0'; + bisttesten : IN STD_LOGIC := '0'; + coreclkin : IN STD_LOGIC := '0'; + corecrst : IN STD_LOGIC := '0'; + corepor : IN STD_LOGIC := '0'; + corerst : IN STD_LOGIC := '0'; + coresrst : IN STD_LOGIC := '0'; + cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0'); + cplpending : IN STD_LOGIC := '0'; + dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0'); + dlaspmcr0 : IN STD_LOGIC := '0'; + dlcomclkreg : IN STD_LOGIC := '0'; + dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0'); + dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0'); + dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + dlinhdllp : IN STD_LOGIC := '1'; + dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0'); + dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0'); + dlrequpfc : IN STD_LOGIC := '0'; + dlreqwake : IN STD_LOGIC := '0'; + dlrxecrcchk : IN STD_LOGIC := '0'; + dlsndupfc : IN STD_LOGIC := '0'; + dltxcfgextsy : IN STD_LOGIC := '0'; + dltxreqpm : IN STD_LOGIC := '0'; + dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0'); + dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0'); + dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + dpclk : IN STD_LOGIC := '0'; + dpriodisable : IN STD_LOGIC := '1'; + dprioin : IN STD_LOGIC := '0'; + dprioload : IN STD_LOGIC := '0'; + extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0'); + lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0'); + lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0'); + lmirden : IN STD_LOGIC := '0'; + lmiwren : IN STD_LOGIC := '0'; + mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0'); + mramhiptestenable : IN STD_LOGIC := '0'; + mramregscanen : IN STD_LOGIC := '0'; + mramregscanin : IN STD_LOGIC := '0'; + pclkcentral : IN STD_LOGIC := '0'; + pclkch0 : IN STD_LOGIC := '0'; + phyrst : IN STD_LOGIC := '0'; + physrst : IN STD_LOGIC := '0'; + phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + pldclk : IN STD_LOGIC := '0'; + pldrst : IN STD_LOGIC := '0'; + pldsrst : IN STD_LOGIC := '0'; + pllfixedclk : IN STD_LOGIC := '0'; + rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + rxmaskvc0 : IN STD_LOGIC := '0'; + rxmaskvc1 : IN STD_LOGIC := '0'; + rxreadyvc0 : IN STD_LOGIC := '0'; + rxreadyvc1 : IN STD_LOGIC := '0'; + rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0'); + rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0'); + scanen : IN STD_LOGIC := '0'; + scanmoden : IN STD_LOGIC := '0'; + swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0'); + testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0'); + tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlappintasts : IN STD_LOGIC := '0'; + tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlappmsireq : IN STD_LOGIC := '0'; + tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0'); + tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0'); + tlpmauxpwr : IN STD_LOGIC := '0'; + tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0'); + tlpmetocr : IN STD_LOGIC := '0'; + tlpmevent : IN STD_LOGIC := '0'; + tlslotclkcfg : IN STD_LOGIC := '0'; + txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0'); + txeopvc00 : IN STD_LOGIC := '0'; + txeopvc01 : IN STD_LOGIC := '0'; + txeopvc10 : IN STD_LOGIC := '0'; + txeopvc11 : IN STD_LOGIC := '0'; + txerrvc0 : IN STD_LOGIC := '0'; + txerrvc1 : IN STD_LOGIC := '0'; + txsopvc00 : IN STD_LOGIC := '0'; + txsopvc01 : IN STD_LOGIC := '0'; + txsopvc10 : IN STD_LOGIC := '0'; + txsopvc11 : IN STD_LOGIC := '0'; + txvalidvc0 : IN STD_LOGIC := '0'; + txvalidvc1 : IN STD_LOGIC := '0'; + bistdonearcv0 : OUT STD_LOGIC; + bistdonearcv1 : OUT STD_LOGIC; + bistdonearpl : OUT STD_LOGIC; + bistdonebrcv0 : OUT STD_LOGIC; + bistdonebrcv1 : OUT STD_LOGIC; + bistdonebrpl : OUT STD_LOGIC; + bistpassrcv0 : OUT STD_LOGIC; + bistpassrcv1 : OUT STD_LOGIC; + bistpassrpl : OUT STD_LOGIC; + bistscanoutrcv0 : OUT STD_LOGIC; + bistscanoutrcv1 : OUT STD_LOGIC; + bistscanoutrpl : OUT STD_LOGIC; + clrrxpath : OUT STD_LOGIC; + coreclkout : OUT STD_LOGIC; + dataenablen : OUT STD_LOGIC; + derrcorextrcv0 : OUT STD_LOGIC; + derrcorextrcv1 : OUT STD_LOGIC; + derrcorextrpl : OUT STD_LOGIC; + derrrpl : OUT STD_LOGIC; + dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + dlackrequpfc : OUT STD_LOGIC; + dlacksndupfc : OUT STD_LOGIC; + dlcurrentdeemp : OUT STD_LOGIC; + dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + dldllreq : OUT STD_LOGIC; + dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + dlerrphy : OUT STD_LOGIC; + dllinkautobdwstatus : OUT STD_LOGIC; + dllinkbdwmngstatus : OUT STD_LOGIC; + dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0); + dlrpbufemp : OUT STD_LOGIC; + dlrstentercompbit : OUT STD_LOGIC; + dlrsttxmarginfield : OUT STD_LOGIC; + dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + dlrxvalpm : OUT STD_LOGIC; + dltxackpm : OUT STD_LOGIC; + dlup : OUT STD_LOGIC; + dlupexit : OUT STD_LOGIC; + dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + dprioout : OUT STD_LOGIC; + dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0); + eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0); + ev128ns : OUT STD_LOGIC; + ev1us : OUT STD_LOGIC; + extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0); + extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0); + gen2rate : OUT STD_LOGIC; + gen2rategnd : OUT STD_LOGIC; + hotrstexit : OUT STD_LOGIC; + intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + l2exit : OUT STD_LOGIC; + laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + linkup : OUT STD_LOGIC; + lmiack : OUT STD_LOGIC; + lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0); + ltssml0state : OUT STD_LOGIC; + mramregscanout : OUT STD_LOGIC; + powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0); + resetstatus : OUT STD_LOGIC; + rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + rxeopvc00 : OUT STD_LOGIC; + rxeopvc01 : OUT STD_LOGIC; + rxeopvc10 : OUT STD_LOGIC; + rxeopvc11 : OUT STD_LOGIC; + rxerrvc0 : OUT STD_LOGIC; + rxerrvc1 : OUT STD_LOGIC; + rxfifoemptyvc0 : OUT STD_LOGIC; + rxfifoemptyvc1 : OUT STD_LOGIC; + rxfifofullvc0 : OUT STD_LOGIC; + rxfifofullvc1 : OUT STD_LOGIC; + rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + rxsopvc00 : OUT STD_LOGIC; + rxsopvc01 : OUT STD_LOGIC; + rxsopvc10 : OUT STD_LOGIC; + rxsopvc11 : OUT STD_LOGIC; + rxvalidvc0 : OUT STD_LOGIC; + rxvalidvc1 : OUT STD_LOGIC; + r2cerr0ext : OUT STD_LOGIC; + serrout : OUT STD_LOGIC; + successspeednegoint : OUT STD_LOGIC; + swdnwake : OUT STD_LOGIC; + swuphotrst : OUT STD_LOGIC; + testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + tlappintaack : OUT STD_LOGIC; + tlappmsiack : OUT STD_LOGIC; + tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0); + tlcfgctlwr : OUT STD_LOGIC; + tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0); + tlcfgstswr : OUT STD_LOGIC; + tlpmetosr : OUT STD_LOGIC; + txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0); + txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0); + txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0); + txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0); + txfifoemptyvc0 : OUT STD_LOGIC; + txfifoemptyvc1 : OUT STD_LOGIC; + txfifofullvc0 : OUT STD_LOGIC; + txfifofullvc1 : OUT STD_LOGIC; + txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0); + txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0); + txreadyvc0 : OUT STD_LOGIC; + txreadyvc1 : OUT STD_LOGIC; + wakeoen : OUT STD_LOGIC + ); +END COMPONENT; + +end cycloneiv_pcie_hip_components; + +package body CYCLONEIV_PCIE_HIP_COMPONENTS is + + + + +function str2bin (s : string) return std_logic_vector is +variable len : integer := s'length; +variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0'); +variable i : integer; +begin + for i in 1 to len loop + case s(i) is + when '0' => result(len - i) := '0'; + when '1' => result(len - i) := '1'; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + end loop; + return result; +end; + +function str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; + +function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + + function int2bin (arg : boolean; size : integer) return std_logic_vector is + variable result : std_logic_vector(size-1 downto 0); + begin + if(arg)then + result := (OTHERS => '1'); + else + result := (OTHERS => '0'); + end if; + return result; + end int2bin; + +function tx_top_ctrl_in_width(double_data_mode : string; + ser_double_data_mode : string + ) return integer is + variable real_widthb : integer; + begin + real_widthb := 1; + if (ser_double_data_mode = "true" AND double_data_mode = "true") then + real_widthb := 4; + elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then + real_widthb := 1; + else + real_widthb := 2; + end if; + + return real_widthb; + end tx_top_ctrl_in_width; + +function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is + variable real_widthb : integer; + begin + if (des_double_data_mode = "true") then + real_widthb := 2; + else + real_widthb := 1; + end if; + return real_widthb; + end rx_top_a1k1_out_width; + +function rx_top_ctrl_out_width(double_data_mode : string; + des_double_data_mode : string + ) return integer is + variable real_widthb : integer; + begin + real_widthb := 1; + if (des_double_data_mode = "true" AND double_data_mode = "true") then + real_widthb := 4; + elsif (des_double_data_mode = "false" AND double_data_mode = "false") then + real_widthb := 1; + else + real_widthb := 2; + end if; + + return real_widthb; + end rx_top_ctrl_out_width; + +function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS + +variable Temp : TIME; +variable TransitionTime : TIME := TIME'HIGH; +variable PathDelay : TIME := TIME'HIGH; + +begin + + for i IN Paths'RANGE loop + next when not Paths(i).PathCondition; + + next when Paths(i).InputChangeTime > TransitionTime; + + Temp := Paths(i).PathDelay(tr01); + + if Paths(i).InputChangeTime < TransitionTime then + PathDelay := Temp; + else + if Temp < PathDelay then + PathDelay := Temp; + end if; + end if; + TransitionTime := Paths(i).InputChangeTime; + end loop; + + return PathDelay; + +end; + +function bin2int (s : std_logic_vector) return integer is + + constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : std_logic) return integer is + constant temp : std_logic := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + + function int2bit (arg : integer) return std_logic is + variable int_val : integer := arg; + variable result : std_logic; + begin + + if (int_val = 0) then + result := '0'; + else + result := '1'; + end if; + + return result; +end int2bit; + +function int2bit (arg : boolean) return std_logic is + variable int_val : boolean := arg; + variable result : std_logic; + begin + + if (int_val ) then + result := '1'; + else + result := '0'; + end if; + + return result; +end int2bit; + +function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is +variable dataout : std_logic_vector(data1'range); + begin + if(sel) then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + +function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is +variable dataout : std_logic; + begin + if(sel) then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + +function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is +variable dataout : std_logic_vector(data1'range); + begin + if(sel = '1') then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + +function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is +variable dataout : std_logic; + begin + if(sel = '1') then + dataout := data1; + else + dataout := data2; + end if; + + return (dataout); + end mux_select; + + function reduction_or ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '0'; + begin + for i in val'range loop + result := result or val(i); + end loop; + return(result); +end reduction_or; + +function reduction_nor ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '0'; + begin + for i in val'range loop + result := result or val(i); + end loop; + return(not result); +end reduction_nor; + +function reduction_xor ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '0'; + begin + for i in val'range loop + result := result xor val(i); + end loop; + return(result); +end reduction_xor; + +function reduction_and ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '1'; + begin + for i in val'range loop + result := result and val(i); + end loop; + return(result); +end reduction_and; + +function reduction_nand ( + val : std_logic_vector) return std_logic is + + variable result : std_logic := '1'; + begin + for i in val'range loop + result := result and val(i); + end loop; + return(not result); +end reduction_nand; + +function alpha_tolower (given_string : string) return string is + -- VARIABLE DECLARATION + variable string_length : integer := given_string'length; + variable result_string : string(1 to 25) := " "; + +begin + for i in 1 to string_length loop + case given_string(i) is + when 'A' => result_string(i) := 'a'; + when 'B' => result_string(i) := 'b'; + when 'C' => result_string(i) := 'c'; + when 'D' => result_string(i) := 'd'; + when 'E' => result_string(i) := 'e'; + when 'F' => result_string(i) := 'f'; + when 'G' => result_string(i) := 'g'; + when 'H' => result_string(i) := 'h'; + when 'I' => result_string(i) := 'i'; + when 'J' => result_string(i) := 'j'; + when 'K' => result_string(i) := 'k'; + when 'L' => result_string(i) := 'l'; + when 'M' => result_string(i) := 'm'; + when 'N' => result_string(i) := 'n'; + when 'O' => result_string(i) := 'o'; + when 'P' => result_string(i) := 'p'; + when 'Q' => result_string(i) := 'q'; + when 'R' => result_string(i) := 'r'; + when 'S' => result_string(i) := 's'; + when 'T' => result_string(i) := 't'; + when 'U' => result_string(i) := 'u'; + when 'V' => result_string(i) := 'v'; + when 'W' => result_string(i) := 'w'; + when 'X' => result_string(i) := 'x'; + when 'Y' => result_string(i) := 'y'; + when 'Z' => result_string(i) := 'z'; + when others => result_string(i) := given_string(i); + end case; + end loop; + return (result_string(1 to string_length)); +end alpha_tolower; + +end CYCLONEIV_PCIE_HIP_COMPONENTS; diff --git a/Common/sim/altera/cycloneive_atoms.vhd b/Common/sim/altera/cycloneive_atoms.vhd new file mode 100644 index 0000000..f8623e3 --- /dev/null +++ b/Common/sim/altera/cycloneive_atoms.vhd @@ -0,0 +1,8803 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +package cycloneive_atom_pack is + +function str_to_bin (lut_mask : string ) return std_logic_vector; + +function product(list : std_logic_vector) return std_logic ; + +function alt_conv_integer(arg : in std_logic_vector) return integer; + + +-- default generic values + CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns); + CONSTANT DefSetupHoldCnst : TIME := 0 ns; + CONSTANT DefPulseWdthCnst : TIME := 0 ns; +-- default control options +-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent; +-- change default delay type to Transport : for spr 68748 + CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport; + CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE; + CONSTANT DefGlitchXOn : BOOLEAN := FALSE; + CONSTANT DefMsgOnChecks : BOOLEAN := TRUE; + CONSTANT DefXOnChecks : BOOLEAN := TRUE; +-- output strength mapping + -- UX01ZWHL- + CONSTANT PullUp : VitalOutputMapType := "UX01HX01X"; + CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X"; + CONSTANT PullDown : VitalOutputMapType := "UX01LX01X"; +-- primitive result strength mapping + CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' ); + CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' ); + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) + +-- Declare array types for CAM_SLICE + TYPE cycloneive_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0); + +function int2str( value : integer ) return string; + +function map_x_to_0 (value : std_logic) return std_logic; + +function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME; + +function int2bit (arg : boolean) return std_logic; +function int2bit (arg : integer) return std_logic; +function bin2int (s : bit_vector) return integer; +function bin2int (s : bit) return integer; +function bin2int (s : std_logic_vector) return integer; +function bin2int (s : std_logic) return integer; +function int2bin (arg : integer; size : integer) return std_logic_vector; +function int2bin (arg : boolean; size : integer) return std_logic_vector; +function calc_sum_len( widtha : integer; widthb : integer) return integer; + +end cycloneive_atom_pack; + +library IEEE; +use IEEE.std_logic_1164.all; + +package body cycloneive_atom_pack is + +type masklength is array (4 downto 1) of std_logic_vector(3 downto 0); +function str_to_bin (lut_mask : string) return std_logic_vector is +variable slice : masklength := (OTHERS => "0000"); +variable mask : std_logic_vector(15 downto 0); + + +begin + + for i in 1 to lut_mask'length loop + case lut_mask(i) is + when '0' => slice(i) := "0000"; + when '1' => slice(i) := "0001"; + when '2' => slice(i) := "0010"; + when '3' => slice(i) := "0011"; + when '4' => slice(i) := "0100"; + when '5' => slice(i) := "0101"; + when '6' => slice(i) := "0110"; + when '7' => slice(i) := "0111"; + when '8' => slice(i) := "1000"; + when '9' => slice(i) := "1001"; + when 'a' => slice(i) := "1010"; + when 'A' => slice(i) := "1010"; + when 'b' => slice(i) := "1011"; + when 'B' => slice(i) := "1011"; + when 'c' => slice(i) := "1100"; + when 'C' => slice(i) := "1100"; + when 'd' => slice(i) := "1101"; + when 'D' => slice(i) := "1101"; + when 'e' => slice(i) := "1110"; + when 'E' => slice(i) := "1110"; + when others => slice(i) := "1111"; + end case; + end loop; + + + mask := (slice(1) & slice(2) & slice(3) & slice(4)); + return (mask); + +end str_to_bin; + +function product (list: std_logic_vector) return std_logic is +begin + + for i in 0 to 31 loop + if list(i) = '0' then + return ('0'); + end if; + end loop; + return ('1'); + +end product; + +function alt_conv_integer(arg : in std_logic_vector) return integer is +variable result : integer; +begin + result := 0; + for i in arg'range loop + if arg(i) = '1' then + result := result + 2**i; + end if; + end loop; + return result; +end alt_conv_integer; + +function int2str( value : integer ) return string is +variable ivalue,index : integer; +variable digit : integer; +variable line_no: string(8 downto 1) := " "; +begin + ivalue := value; + index := 1; + if (ivalue = 0) then + line_no := " 0"; + end if; + while (ivalue > 0) loop + digit := ivalue MOD 10; + ivalue := ivalue/10; + case digit is + when 0 => + line_no(index) := '0'; + when 1 => + line_no(index) := '1'; + when 2 => + line_no(index) := '2'; + when 3 => + line_no(index) := '3'; + when 4 => + line_no(index) := '4'; + when 5 => + line_no(index) := '5'; + when 6 => + line_no(index) := '6'; + when 7 => + line_no(index) := '7'; + when 8 => + line_no(index) := '8'; + when 9 => + line_no(index) := '9'; + when others => + ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + index := index + 1; + end loop; + return line_no; +end; + +function map_x_to_0 (value : std_logic) return std_logic is +begin + if (Is_X (value) = TRUE) then + return '0'; + else + return value; + end if; +end; + +function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS + +variable Temp : TIME; +variable TransitionTime : TIME := TIME'HIGH; +variable PathDelay : TIME := TIME'HIGH; + +begin + + for i IN Paths'RANGE loop + next when not Paths(i).PathCondition; + + next when Paths(i).InputChangeTime > TransitionTime; + + Temp := Paths(i).PathDelay(tr01); + + if Paths(i).InputChangeTime < TransitionTime then + PathDelay := Temp; + else + if Temp < PathDelay then + PathDelay := Temp; + end if; + end if; + TransitionTime := Paths(i).InputChangeTime; + end loop; + + return PathDelay; + +end; + +function int2bit (arg : integer) return std_logic is + variable int_val : integer := arg; + variable result : std_logic; + begin + + if (int_val = 0) then + result := '0'; + else + result := '1'; + end if; + + return result; +end int2bit; + +function int2bit (arg : boolean) return std_logic is + variable int_val : boolean := arg; + variable result : std_logic; + begin + + if (int_val ) then + result := '1'; + else + result := '0'; + end if; + + return result; +end int2bit; + +function bin2int (s : bit_vector) return integer is + + constant temp : bit_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : bit) return integer is + constant temp : bit := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + +function bin2int (s : std_logic_vector) return integer is + + constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : std_logic) return integer is + constant temp : std_logic := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + +function int2bin (arg : boolean; size : integer) return std_logic_vector is + variable result : std_logic_vector(size-1 downto 0); + begin + if(arg)then + result := (OTHERS => '1'); + else + result := (OTHERS => '0'); + end if; + return result; + end int2bin; + +function calc_sum_len( widtha : integer; widthb : integer) return integer is +variable result: integer; +begin + if(widtha >= widthb) then + result := widtha + 1; + else + result := widthb + 1; + end if; + return result; +end calc_sum_len; + +end cycloneive_atom_pack; + +Library ieee; +use ieee.std_logic_1164.all; + +Package cycloneive_pllpack is + + + procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer); + + procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ); + + function gcd (X: integer; Y: integer) return integer; + + function count_digit (X: integer) return integer; + + function scale_num (X: integer; Y: integer) return integer; + + function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) return integer; + + function output_counter_value (clk_divide: integer; clk_mult : integer ; + M: integer; N: integer ) return integer; + + function counter_mode (duty_cycle: integer; output_counter_value: integer) return string; + + function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer; + + function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer; + + function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function counter_time_delay ( clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer; + + function get_phase_degree (phase_shift: integer; clk_period: integer) return integer; + + function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer; + + function counter_ph (tap_phase: integer; m : integer; n: integer) return integer; + + function ph_adjust (tap_phase: integer; ph_base : integer) return integer; + + function translate_string (mode : string) return string; + + function str2int (s : string) return integer; + + function dqs_str2int (s : string) return integer; + +end cycloneive_pllpack; + +package body cycloneive_pllpack is + + +-- finds the closest integer fraction of a given pair of numerator and denominator. +procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer) is + constant MAX_ITER : integer := 20; + type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer; + + variable quotient_array : INT_ARRAY; + variable int_loop_iter : integer; + variable int_quot : integer; + variable m_value : integer; + variable d_value : integer; + variable old_m_value : integer; + variable swap : integer; + variable loop_iter : integer; + variable num : integer; + variable den : integer; + variable i_max_iter : integer; + +begin + loop_iter := 0; + + if (numerator = 0) then + num := 1; + else + num := numerator; + end if; + + if (denominator = 0) then + den := 1; + else + den := denominator; + end if; + + i_max_iter := max_iter; + + while (loop_iter < i_max_iter) loop + int_quot := num / den; + quotient_array(loop_iter) := int_quot; + num := num - (den*int_quot); + loop_iter := loop_iter+1; + + if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then + -- calculate the numerator and denominator if there is a restriction on the + -- max denom value or if the loop is ending + m_value := 0; + d_value := 1; + -- get the rounded value at this stage for the remaining fraction + if (den /= 0) then + m_value := (2*num/den); + end if; + -- calculate the fraction numerator and denominator at this stage + for int_loop_iter in (loop_iter-1) downto 0 loop + if (m_value = 0) then + m_value := quotient_array(int_loop_iter); + d_value := 1; + else + old_m_value := m_value; + m_value := (quotient_array(int_loop_iter)*m_value) + d_value; + d_value := old_m_value; + end if; + end loop; + -- if the denominator is less than the maximum denom_value or if there is no restriction save it + if ((d_value <= max_denom) or (max_denom = -1)) then + if ((m_value = 0) or (d_value = 0)) then + fraction_num := numerator; + fraction_div := denominator; + else + fraction_num := m_value; + fraction_div := d_value; + end if; + end if; + -- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round) + if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then + i_max_iter := loop_iter; + end if; + end if; + -- swap the numerator and denominator for the next round + swap := den; + den := num; + num := swap; + end loop; +end find_simple_integer_fraction; + +-- find the M and N values for Manual phase based on the following 5 criterias: +-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz +-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz +-- 3. M is less than 512 +-- 4. N is less than 512 +-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps +-- of the desired vco-phase-shift-step +procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ) is + constant MAX_M : integer := 511; + constant MAX_N : integer := 511; + constant MAX_PFD : integer := 720; + constant MIN_PFD : integer := 5; + constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz) + constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz) + constant MAX_OFFSET : real := 0.004; + + variable vco_period : integer; + variable pfd_freq : integer; + variable vco_freq : integer; + variable vco_ps_step_value : integer; + + variable i_m : integer; + variable i_n : integer; + + variable i_pre_m : integer; + variable i_pre_n : integer; + + variable closest_vco_step_value : integer; + + variable i_max_iter : integer; + variable loop_iter : integer; + + variable clk0_div_factor_real : real; + variable clk1_div_factor_real : real; + variable clk2_div_factor_real : real; + variable clk3_div_factor_real : real; + variable clk4_div_factor_real : real; + variable clk5_div_factor_real : real; + variable clk6_div_factor_real : real; + variable clk7_div_factor_real : real; + variable clk8_div_factor_real : real; + variable clk9_div_factor_real : real; + variable clk0_div_factor_int : integer; + variable clk1_div_factor_int : integer; + variable clk2_div_factor_int : integer; + variable clk3_div_factor_int : integer; + variable clk4_div_factor_int : integer; + variable clk5_div_factor_int : integer; + variable clk6_div_factor_int : integer; + variable clk7_div_factor_int : integer; + variable clk8_div_factor_int : integer; + variable clk9_div_factor_int : integer; +begin + vco_period := vco_phase_shift_step * 8; + i_pre_m := 0; + i_pre_n := 0; + closest_vco_step_value := 0; + + LOOP_1 : for i_n_out in 1 to MAX_N loop + for i_m_out in 1 to MAX_M loop + + clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out); + clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out); + clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out); + clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out); + clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out); + clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out); + clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out); + clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out); + clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out); + clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out); + + clk0_div_factor_int := integer(clk0_div_factor_real); + clk1_div_factor_int := integer(clk1_div_factor_real); + clk2_div_factor_int := integer(clk2_div_factor_real); + clk3_div_factor_int := integer(clk3_div_factor_real); + clk4_div_factor_int := integer(clk4_div_factor_real); + clk5_div_factor_int := integer(clk5_div_factor_real); + clk6_div_factor_int := integer(clk6_div_factor_real); + clk7_div_factor_int := integer(clk7_div_factor_real); + clk8_div_factor_int := integer(clk8_div_factor_real); + clk9_div_factor_int := integer(clk9_div_factor_real); + + if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and + ((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and + ((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and + ((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and + ((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and + ((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and + ((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and + ((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and + ((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and + ((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) ) + then + if ((i_m_out /= 0) and (i_n_out /= 0)) + then + pfd_freq := 1000000 / (inclock_period * i_n_out); + vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out); + vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out); + + if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and + (vco_freq >= min_vco) and (vco_freq <= max_vco) ) + then + if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + exit LOOP_1; + else + if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + closest_vco_step_value := vco_ps_step_value; + end if; + end if; + end if; + end if; + end if; + end loop; + end loop; + + if ((i_pre_m /= 0) and (i_pre_n /= 0)) + then + find_simple_integer_fraction(i_pre_m, i_pre_n, + MAX_N, m, n); + else + n := 1; + m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult, + clk4_mult, clk5_mult, clk6_mult, + clk7_mult, clk8_mult, clk9_mult, inclock_period); + end if; +end find_m_and_n_4_manual_phase; + +-- find the greatest common denominator of X and Y +function gcd (X: integer; Y: integer) return integer is +variable L, S, R, G : integer := 1; +begin + if (X < Y) then -- find which is smaller. + S := X; + L := Y; + else + S := Y; + L := X; + end if; + + R := S; + while ( R > 1) loop + S := L; + L := R; + R := S rem L; -- divide bigger number by smaller. + -- remainder becomes smaller number. + end loop; + if (R = 0) then -- if evenly divisible then L is gcd else it is 1. + G := L; + else + G := R; + end if; + + return G; +end gcd; + +-- count the number of digits in the given integer +function count_digit (X: integer) + return integer is +variable count, result: integer := 0; +begin + result := X; + while (result /= 0) loop + result := (result / 10); + count := count + 1; + end loop; + + return count; +end count_digit; + +-- reduce the given huge number to Y significant digits +function scale_num (X: integer; Y: integer) + return integer is +variable count : integer := 0; +variable lc, fac_ten, result: integer := 1; +begin + count := count_digit(X); + + for lc in 1 to (count-Y) loop + fac_ten := fac_ten * 10; + end loop; + + result := (X / fac_ten); + + return result; +end scale_num; + +-- find the least common multiple of A1 to A10 +function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) + return integer is +variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1; +begin + M1 := (A1 * A2)/gcd(A1, A2); + M2 := (M1 * A3)/gcd(M1, A3); + M3 := (M2 * A4)/gcd(M2, A4); + M4 := (M3 * A5)/gcd(M3, A5); + M5 := (M4 * A6)/gcd(M4, A6); + M6 := (M5 * A7)/gcd(M5, A7); + M7 := (M6 * A8)/gcd(M6, A8); + M8 := (M7 * A9)/gcd(M7, A9); + M9 := (M8 * A10)/gcd(M8, A10); + if (M9 < 3) then + R := 10; + elsif (M9 = 3) then + R := 9; + elsif ((M9 <= 10) and (M9 > 3)) then + R := 4 * M9; + elsif (M9 > 1000) then + R := scale_num(M9,3); + else + R := M9 ; + end if; + + return R; +end lcm; + +-- find the factor of division of the output clock frequency compared to the VCO +function output_counter_value (clk_divide: integer; clk_mult: integer ; + M: integer; N: integer ) return integer is +variable r_real : real := 1.0; +variable r: integer := 1; +begin + r_real := real(clk_divide * M)/ real(clk_mult * N); + r := integer(r_real); + + return R; +end output_counter_value; + +-- find the mode of each PLL counter - bypass, even or odd +function counter_mode (duty_cycle: integer; output_counter_value: integer) + return string is +variable R: string (1 to 6) := " "; +variable counter_value: integer := 1; +begin + counter_value := (2*duty_cycle*output_counter_value)/100; + if output_counter_value = 1 then + R := "bypass"; + elsif (counter_value REM 2) = 0 then + R := " even"; + else + R := " odd"; + end if; + + return R; +end counter_mode; + +-- find the number of VCO clock cycles to hold the output clock high +function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer is +variable R: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value *2)/100 ; + if (half_cycle_high REM 2 = 0) then + R := half_cycle_high/2 ; + else + R := (half_cycle_high/2) + 1; + end if; + + return R; +end; + +-- find the number of VCO clock cycles to hold the output clock low +function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer is +variable R, R1: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value*2)/100 ; + if (half_cycle_high REM 2 = 0) then + R1 := half_cycle_high/2 ; + else + R1 := (half_cycle_high/2) + 1; + end if; + + R := output_counter_value - R1; + + if (R = 0) then + R := 1; + end if; + + return R; +end; + +-- find the smallest time delay amongst t1 to t10 +function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 > 0) then return m9; else return 0; end if; +end; + +-- find the numerically largest negative number, and return its absolute value +function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 < 0) then return (0 - m9); else return 0; end if; +end; + +-- adjust the phase (tap_phase) with the largest negative number (ph_base) +function ph_adjust (tap_phase: integer; ph_base : integer) return integer is +begin + return (tap_phase + ph_base); +end; + +-- find the time delay for each PLL counter +function counter_time_delay (clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer is +variable R: integer := 0; +begin + R := clk_time_delay + m_time_delay - n_time_delay; + + return R; +end; + +-- calculate the given phase shift (in ps) in terms of degrees +function get_phase_degree (phase_shift: integer; clk_period: integer) + return integer is +variable result: integer := 0; +begin + result := ( phase_shift * 360 ) / clk_period; + -- to round up the calculation result + if (result > 0) then + result := result + 1; + elsif (result < 0) then + result := result - 1; + else + result := 0; + end if; + + return result; +end; + +-- find the number of VCO clock cycles to wait initially before the first rising +-- edge of the output clock +function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer is +variable R: integer; +variable R1: real; +begin + R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6; + -- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99. + -- This checking will ensure that the rounding up is done. + if (R1 >= 0.5) and (R1 <= 1.0) then + R1 := 1.0; + end if; + + R := integer(R1); + + return R; +end; + +-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to +function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is +variable R: integer := 0; +begin + -- 0.5 is added for proper rounding of the tap_phase. + R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8; + + return R; +end; + +-- convert given string to length 6 by padding with spaces +function translate_string (mode : string) return string is +variable new_mode : string (1 to 6) := " "; +begin + if (mode = "bypass") then + new_mode := "bypass"; + elsif (mode = "even") then + new_mode := " even"; + elsif (mode = "odd") then + new_mode := " odd"; + end if; + + return new_mode; +end; + +function str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "i n string parameter! " + SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; + +function dqs_str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +variable err : boolean := false; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & " in string parameter! " + SEVERITY ERROR; + err := true; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + -- set error flag + err := true; + end case; + if (err) then + err := false; + else + newdigit := newdigit * 10 + digit; + end if; + end loop; + + return (sign*newdigit); +end; + +end cycloneive_pllpack; + +-- +-- +-- DFFE Model +-- +-- + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_dffe is + generic( + TimingChecksOn: Boolean := True; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tipd_D : VitalDelayType01 := DefPropDelay01; + tipd_CLRN : VitalDelayType01 := DefPropDelay01; + tipd_PRN : VitalDelayType01 := DefPropDelay01; + tipd_CLK : VitalDelayType01 := DefPropDelay01; + tipd_ENA : VitalDelayType01 := DefPropDelay01); + + port( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC; + CLRN : in STD_LOGIC; + PRN : in STD_LOGIC; + CLK : in STD_LOGIC; + ENA : in STD_LOGIC); + attribute VITAL_LEVEL0 of cycloneive_dffe : entity is TRUE; +end cycloneive_dffe; + +-- architecture body -- + +architecture behave of cycloneive_dffe is + attribute VITAL_LEVEL0 of behave : architecture is TRUE; + + signal D_ipd : STD_ULOGIC := 'U'; + signal CLRN_ipd : STD_ULOGIC := 'U'; + signal PRN_ipd : STD_ULOGIC := 'U'; + signal CLK_ipd : STD_ULOGIC := 'U'; + signal ENA_ipd : STD_ULOGIC := 'U'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN); + VitalWireDelay (PRN_ipd, PRN, tipd_PRN); + VitalWireDelay (CLK_ipd, CLK, tipd_CLK); + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd) + + -- timing check results + VARIABLE Tviol_D_CLK : STD_ULOGIC := '0'; + VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0'; + VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit; + VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7); + VARIABLE D_delayed : STD_ULOGIC := 'U'; + VARIABLE CLK_delayed : STD_ULOGIC := 'U'; + VARIABLE ENA_delayed : STD_ULOGIC := 'U'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0'); + + -- output glitch detection variables + VARIABLE Q_VitalGlitchData : VitalGlitchDataType; + + + CONSTANT dffe_Q_tab : VitalStateTableType := ( + ( L, L, x, x, x, x, x, x, x, L ), + ( L, H, L, H, H, x, x, H, x, H ), + ( L, H, L, H, x, L, x, H, x, H ), + ( L, H, L, x, H, H, x, H, x, H ), + ( L, H, H, x, x, x, H, x, x, S ), + ( L, H, x, x, x, x, L, x, x, H ), + ( L, H, x, x, x, x, H, L, x, S ), + ( L, x, L, L, L, x, H, H, x, L ), + ( L, x, L, L, x, L, H, H, x, L ), + ( L, x, L, x, L, H, H, H, x, L ), + ( L, x, x, x, x, x, x, x, x, S )); + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_CLK, + TimingData => TimingData_D_CLK, + TestSignal => D_ipd, + TestSignalName => "D", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_D_CLK_noedge_posedge, + SetupLow => tsetup_D_CLK_noedge_posedge, + HoldHigh => thold_D_CLK_noedge_posedge, + HoldLow => thold_D_CLK_noedge_posedge, + CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/DFFE", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLK, + TimingData => TimingData_ENA_CLK, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ENA_CLK_noedge_posedge, + SetupLow => tsetup_ENA_CLK_noedge_posedge, + HoldHigh => thold_ENA_CLK_noedge_posedge, + HoldLow => thold_ENA_CLK_noedge_posedge, + CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/DFFE", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_CLK or Tviol_ENA_CLK; + VitalStateTable( + StateTable => dffe_Q_tab, + DataIn => ( + Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd), + Result => Results, + NumStates => 1, + PreviousDataIn => PrevData_Q); + D_delayed := D_ipd; + CLK_delayed := CLK_ipd; + ENA_delayed := ENA_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + OutSignalName => "Q", + OutTemp => Results(1), + Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE), + 1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE), + 2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)), + GlitchData => Q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; + +-- +-- +-- cycloneive_mux21 Model +-- +-- + +LIBRARY IEEE; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_mux21 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic); + attribute VITAL_LEVEL0 of cycloneive_mux21 : entity is TRUE; +end cycloneive_mux21; + +architecture AltVITAL of cycloneive_mux21 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + signal A_ipd, B_ipd, S_ipd : std_logic; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (A_ipd, A, tipd_A); + VitalWireDelay (B_ipd, B, tipd_B); + VitalWireDelay (S_ipd, S, tipd_S); + end block; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (A_ipd, B_ipd, S_ipd) + + -- output glitch detection variables + VARIABLE MO_GlitchData : VitalGlitchDataType; + + variable tmp_MO : std_logic; + begin + ------------------------- + -- Functionality Section + ------------------------- + if (S_ipd = '1') then + tmp_MO := B_ipd; + else + tmp_MO := A_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => MO, + OutSignalName => "MO", + OutTemp => tmp_MO, + Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE), + 1 => (B_ipd'last_event, tpd_B_MO, TRUE), + 2 => (S_ipd'last_event, tpd_S_MO, TRUE)), + GlitchData => MO_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; + +-- +-- +-- cycloneive_mux41 Model +-- +-- + +LIBRARY IEEE; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_mux41 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_IN0_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN1_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN2_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN3_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_IN0 : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01; + tipd_IN2 : VitalDelayType01 := DefPropDelay01; + tipd_IN3 : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01) + ); + port ( + IN0 : in std_logic := '0'; + IN1 : in std_logic := '0'; + IN2 : in std_logic := '0'; + IN3 : in std_logic := '0'; + S : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + MO : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneive_mux41 : entity is TRUE; +end cycloneive_mux41; + +architecture AltVITAL of cycloneive_mux41 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic; + signal S_ipd : std_logic_vector(1 downto 0); + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (IN0_ipd, IN0, tipd_IN0); + VitalWireDelay (IN1_ipd, IN1, tipd_IN1); + VitalWireDelay (IN2_ipd, IN2, tipd_IN2); + VitalWireDelay (IN3_ipd, IN3, tipd_IN3); + VitalWireDelay (S_ipd(0), S(0), tipd_S(0)); + VitalWireDelay (S_ipd(1), S(1), tipd_S(1)); + end block; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1)) + + -- output glitch detection variables + VARIABLE MO_GlitchData : VitalGlitchDataType; + + variable tmp_MO : std_logic; + begin + ------------------------- + -- Functionality Section + ------------------------- + if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then + tmp_MO := IN3_ipd; + elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then + tmp_MO := IN2_ipd; + elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then + tmp_MO := IN1_ipd; + else + tmp_MO := IN0_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => MO, + OutSignalName => "MO", + OutTemp => tmp_MO, + Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE), + 1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE), + 2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE), + 3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE), + 4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE), + 5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)), + GlitchData => MO_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; + +-- +-- +-- cycloneive_and1 Model +-- +-- +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneive_atom_pack.all; + +-- entity declaration -- +entity cycloneive_and1 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01); + + port( + Y : out STD_LOGIC; + IN1 : in STD_LOGIC); + attribute VITAL_LEVEL0 of cycloneive_and1 : entity is TRUE; +end cycloneive_and1; + +-- architecture body -- + +architecture AltVITAL of cycloneive_and1 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + SIGNAL IN1_ipd : STD_ULOGIC := 'U'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (IN1_ipd, IN1, tipd_IN1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (IN1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS Y_zd : STD_ULOGIC is Results(1); + + -- output glitch detection variables + VARIABLE Y_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + Y_zd := TO_X01(IN1_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Y, + OutSignalName => "Y", + OutTemp => Y_zd, + Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)), + GlitchData => Y_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_lcell_comb +-- +-- Description : Cyclone II LCELL_COMB VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_lcell_comb is + generic ( + lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1'); + sum_lutc_input : string := "datac"; + dont_touch : string := "off"; + lpm_type : string := "cycloneive_lcell_comb"; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; + tpd_datab_combout : VitalDelayType01 := DefPropDelay01; + tpd_datac_combout : VitalDelayType01 := DefPropDelay01; + tpd_datad_combout : VitalDelayType01 := DefPropDelay01; + tpd_cin_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; + tpd_datab_cout : VitalDelayType01 := DefPropDelay01; + tpd_datac_cout : VitalDelayType01 := DefPropDelay01; + tpd_datad_cout : VitalDelayType01 := DefPropDelay01; + tpd_cin_cout : VitalDelayType01 := DefPropDelay01; + tipd_dataa : VitalDelayType01 := DefPropDelay01; + tipd_datab : VitalDelayType01 := DefPropDelay01; + tipd_datac : VitalDelayType01 := DefPropDelay01; + tipd_datad : VitalDelayType01 := DefPropDelay01; + tipd_cin : VitalDelayType01 := DefPropDelay01 + ); + + port ( + dataa : in std_logic := '1'; + datab : in std_logic := '1'; + datac : in std_logic := '1'; + datad : in std_logic := '1'; + cin : in std_logic := '0'; + combout : out std_logic; + cout : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneive_lcell_comb : entity is TRUE; +end cycloneive_lcell_comb; + +architecture vital_lcell_comb of cycloneive_lcell_comb is + attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE; + signal dataa_ipd : std_logic; + signal datab_ipd : std_logic; + signal datac_ipd : std_logic; + signal datad_ipd : std_logic; + signal cin_ipd : std_logic; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (dataa_ipd, dataa, tipd_dataa); + VitalWireDelay (datab_ipd, datab, tipd_datab); + VitalWireDelay (datac_ipd, datac, tipd_datac); + VitalWireDelay (datad_ipd, datad, tipd_datad); + VitalWireDelay (cin_ipd, cin, tipd_cin); + end block; + +VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, + cin_ipd) + +variable combout_VitalGlitchData : VitalGlitchDataType; +variable cout_VitalGlitchData : VitalGlitchDataType; +-- output variables +variable combout_tmp : std_logic; +variable cout_tmp : std_logic; + +begin + + -- lut_mask_var := lut_mask; + + ------------------------ + -- Timing Check Section + ------------------------ + + if (sum_lutc_input = "datac") then + -- combout + combout_tmp := VitalMUX(data => lut_mask, + dselect => (datad_ipd, + datac_ipd, + datab_ipd, + dataa_ipd)); + elsif (sum_lutc_input = "cin") then + -- combout + combout_tmp := VitalMUX(data => lut_mask, + dselect => (datad_ipd, + cin_ipd, + datab_ipd, + dataa_ipd)); + end if; + + -- cout + cout_tmp := VitalMUX(data => lut_mask, + dselect => ('0', + cin_ipd, + datab_ipd, + dataa_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + + VitalPathDelay01 ( + OutSignal => combout, + OutSignalName => "COMBOUT", + OutTemp => combout_tmp, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_combout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_combout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_combout, TRUE), + 4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)), + GlitchData => combout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => cout, + OutSignalName => "COUT", + OutTemp => cout_tmp, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_cout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_cout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_cout, TRUE), + 4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)), + GlitchData => cout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + +end process; + +end vital_lcell_comb; + + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_routing_wire +-- +-- Description : Cycloneive Routing Wire VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +ENTITY cycloneive_routing_wire is + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneive_routing_wire : entity is TRUE; +end cycloneive_routing_wire; + +ARCHITECTURE behave of cycloneive_routing_wire is +attribute VITAL_LEVEL0 of behave : architecture is TRUE; +signal datain_ipd : std_logic; +signal datainglitch_inert : std_logic; +begin + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (datain_ipd, datain, tipd_datain); + end block; + + VITAL: process(datain_ipd, datainglitch_inert) + variable datain_inert_VitalGlitchData : VitalGlitchDataType; + variable dataout_VitalGlitchData : VitalGlitchDataType; + + begin + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => datainglitch_inert, + OutSignalName => "datainglitch_inert", + OutTemp => datain_ipd, + Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)), + GlitchData => datain_inert_VitalGlitchData, + Mode => VitalInertial, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => dataout, + OutSignalName => "dataout", + OutTemp => datainglitch_inert, + Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneive_mn_cntr +-- +-- Description : Timing simulation model for the M and N counter. This is a +-- common model for the input counter and the loop feedback +-- counter of the Cycloneive PLL. +-- +--/////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; + +ENTITY cycloneive_mn_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END cycloneive_mn_cntr; + +ARCHITECTURE behave of cycloneive_mn_cntr is +begin + + process (clk, reset) + variable count : integer := 1; + variable first_rising_edge : boolean := true; + variable tmp_cout : std_logic; + begin + if (reset = '1') then + count := 1; + tmp_cout := '0'; + first_rising_edge := true; + elsif (clk'event) then + if (clk = '1' and first_rising_edge) then + first_rising_edge := false; + tmp_cout := clk; + elsif (not first_rising_edge) then + if (count < modulus) then + count := count + 1; + else + count := 1; + tmp_cout := not tmp_cout; + end if; + end if; + end if; + cout <= transport tmp_cout after time_delay * 1 ps; + end process; +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneive_scale_cntr +-- +-- Description : Timing simulation model for the output scale-down counters. +-- This is a common model for the C0, C1, C2, C3, C4 and C5 +-- output counters of the Cycloneive PLL. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; + +ENTITY cycloneive_scale_cntr is + PORT( clk : IN std_logic; + reset : IN std_logic := '0'; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0; + cout : OUT std_logic + ); +END cycloneive_scale_cntr; + +ARCHITECTURE behave of cycloneive_scale_cntr is +begin + process (clk, reset) + variable tmp_cout : std_logic := '0'; + variable count : integer := 1; + variable output_shift_count : integer := 1; + variable first_rising_edge : boolean := false; + begin + if (reset = '1') then + count := 1; + output_shift_count := 1; + tmp_cout := '0'; + first_rising_edge := false; + elsif (clk'event) then + if (mode = " off") then + tmp_cout := '0'; + elsif (mode = "bypass") then + tmp_cout := clk; + first_rising_edge := true; + elsif (not first_rising_edge) then + if (clk = '1') then + if (output_shift_count = initial) then + tmp_cout := clk; + first_rising_edge := true; + else + output_shift_count := output_shift_count + 1; + end if; + end if; + elsif (output_shift_count < initial) then + if (clk = '1') then + output_shift_count := output_shift_count + 1; + end if; + else + count := count + 1; + if (mode = " even" and (count = (high*2) + 1)) then + tmp_cout := '0'; + elsif (mode = " odd" and (count = high*2)) then + tmp_cout := '0'; + elsif (count = (high + low)*2 + 1) then + tmp_cout := '1'; + count := 1; -- reset count + end if; + end if; + end if; + cout <= transport tmp_cout; + end process; + +end behave; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneive_pll_reg +-- +-- Description : Simulation model for a simple DFF. +-- This is required for the generation of the bit slip-signals. +-- No timing, powers upto 0. +-- +--///////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY cycloneive_pll_reg is + PORT( clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic + ); +end cycloneive_pll_reg; + +ARCHITECTURE behave of cycloneive_pll_reg is +begin + process (clk, prn, clrn) + variable q_reg : std_logic := '0'; + begin + if (prn = '0') then + q_reg := '1'; + elsif (clrn = '0') then + q_reg := '0'; + elsif (clk'event and clk = '1' and (ena = '1')) then + q_reg := D; + end if; + + Q <= q_reg; + end process; +end behave; +--/////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneive_pll +-- +-- Description : Timing simulation model for the Cycloneive PLL. +-- In the functional mode, it is also the model for the altpll +-- megafunction. +-- +-- Limitations : Does not support Spread Spectrum and Bandwidth. +-- +-- Outputs : Up to 10 output clocks, each defined by its own set of +-- parameters. Locked output (active high) indicates when the +-- PLL locks. clkbad and activeclock are used for +-- clock switchover to indicate which input clock has gone +-- bad, when the clock switchover initiates and which input +-- clock is being used as the reference, respectively. +-- scandataout is the data output of the serial scan chain. +-- +--/////////////////////////////////////////////////////////////////////////// +LIBRARY IEEE, std; +USE IEEE.std_logic_1164.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE STD.TEXTIO.all; +USE work.cycloneive_atom_pack.all; +USE work.cycloneive_pllpack.all; +USE work.cycloneive_mn_cntr; +USE work.cycloneive_scale_cntr; +USE work.cycloneive_dffe; +USE work.cycloneive_pll_reg; + +-- New Features : The list below outlines key new features in CYCLONEIVE: +-- 1. Dynamic Phase Reconfiguration +-- 2. Dynamic PLL Reconfiguration (different protocol) +-- 3. More output counters + +ENTITY cycloneive_pll is + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM + compensate_clock : string := "clock0"; + + inclk0_input_frequency : integer := 0; + inclk1_input_frequency : integer := 0; + + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + + + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + use_dc_coupling : string := "false"; + + + + lock_c : integer := 4; + sim_gate_lock_device_behavior : string := "off"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_window : time := 5 ps; + test_bypass_lock_detect : string := "off"; + + + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 0; + clk0_divide_by : integer := 0; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 0; + clk1_divide_by : integer := 0; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 0; + clk2_divide_by : integer := 0; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 0; + clk3_divide_by : integer := 0; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 0; + clk4_divide_by : integer := 0; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + + + + + + + + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + + -- ADVANCED USER PARAMETERS + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + + + + + + + m_ph : integer := 0; + + clk0_counter : string := "unused"; + clk1_counter : string := "unused"; + clk2_counter : string := "unused"; + clk3_counter : string := "unused"; + clk4_counter : string := "unused"; + + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + vco_post_scale : integer := 1; + vco_frequency_control : string := "auto"; + vco_phase_shift_step : integer := 0; + + charge_pump_current : integer := 10; + loop_filter_r : string := " 1.0"; + loop_filter_c : integer := 0; + + + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + lpm_type : string := "cycloneive_pll"; + + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + +-- Test only + init_block_reset_a_count : integer := 1; + init_block_reset_b_count : integer := 1; + charge_pump_current_bits : integer := 0; + lock_window_ui_bits : integer := 0; + loop_filter_c_bits : integer := 0; + loop_filter_r_bits : integer := 0; + test_counter_c0_delay_chain_bits : integer := 0; + test_counter_c1_delay_chain_bits : integer := 0; + test_counter_c2_delay_chain_bits : integer := 0; + test_counter_c3_delay_chain_bits : integer := 0; + test_counter_c4_delay_chain_bits : integer := 0; + test_counter_c5_delay_chain_bits : integer := 0; + test_counter_m_delay_chain_bits : integer := 0; + test_counter_n_delay_chain_bits : integer := 0; + test_feedback_comp_delay_chain_bits : integer := 0; + test_input_comp_delay_chain_bits : integer := 0; + test_volt_reg_output_mode_bits : integer := 0; + test_volt_reg_output_voltage_bits : integer := 0; + test_volt_reg_test_mode : string := "false"; + vco_range_detector_high_bits : integer := -1; + vco_range_detector_low_bits : integer := -1; + scan_chain_mif_file : string := ""; + + auto_settings : string := "true"; +-- Simulation only generics + family_name : string := "Cycloneive"; + + -- VITAL generics + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + TimingChecksOn : Boolean := true; + InstancePath : STRING := "*"; + tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_pfdena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_fbin : VitalDelayType01 := DefPropDelay01; + tipd_scanclk : VitalDelayType01 := DefPropDelay01; + tipd_scanclkena : VitalDelayType01 := DefPropDelay01; + tipd_scandata : VitalDelayType01 := DefPropDelay01; + tipd_configupdate : VitalDelayType01 := DefPropDelay01; + tipd_clkswitch : VitalDelayType01 := DefPropDelay01; + tipd_phaseupdown : VitalDelayType01 := DefPropDelay01; + tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phasestep : VitalDelayType01 := DefPropDelay01; + tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + use_vco_bypass : string := "false" + ); + + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + fbout : out std_logic; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + clk : out std_logic_vector(4 downto 0); + phasecounterselect : in std_logic_vector(2 downto 0) := "000"; + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic + + ); +END cycloneive_pll; + +ARCHITECTURE vital_pll of cycloneive_pll is + +function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is +begin + if (i_vco_post_scale = 1) then + return vco_min * 2; + else + return vco_min; + end if; +end; + +function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is +begin + if (i_vco_post_scale = 1) then + return vco_max * 2; + else + return vco_max; + end if; +end; + +TYPE int_array is ARRAY(NATURAL RANGE <>) of integer; +TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6); +TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9); +TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic; + +constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale); +constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale); + +-- internal advanced parameter signals +signal i_vco_min : integer := vco_min; +signal i_vco_max : integer := vco_max; +signal i_vco_center : integer; +signal i_pfd_min : integer; +signal i_pfd_max : integer; + signal c_ph_val : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_high_val : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val : int_array(0 to 4) := (OTHERS => 1); + signal c_initial_val : int_array(0 to 4) := (OTHERS => 1); + signal c_mode_val : str_array(0 to 4); + signal clk_num : str_array(0 to 4); + +-- old values + signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_old : str_array(0 to 4); +-- hold registers + signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1); + signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0); + signal c_mode_val_hold : str_array(0 to 4); + +-- temp registers + signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0); + signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0); + +signal real_lock_high : integer := 0; +signal i_clk4_counter : integer := 4; +signal i_clk3_counter : integer := 3; +signal i_clk2_counter : integer := 2; +signal i_clk1_counter : integer := 1; +signal i_clk0_counter : integer := 0; +signal i_charge_pump_current : integer; +signal i_loop_filter_r : integer; + +-- end internal advanced parameter signals + +-- CONSTANTS +CONSTANT SCAN_CHAIN : integer := 144; +CONSTANT GPP_SCAN_CHAIN : integer := 234; +CONSTANT FAST_SCAN_CHAIN : integer := 180; + CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0"); +CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2"); + +CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0); +CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + +CONSTANT num_phase_taps : integer := 8; +-- signals + +signal vcc : std_logic := '1'; + +signal fbclk : std_logic; +signal refclk : std_logic; +signal vco_over : std_logic := '0'; +signal vco_under : std_logic := '1'; + +signal pll_locked : boolean := false; + + + signal c_clk : std_logic_array(0 to 4); +signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0'); + +-- signals to assign values to counter params +signal m_val : integer := 1; +signal n_val : integer := 1; +signal m_ph_val : integer := 0; +signal m_ph_initial : integer := 0; +signal m_ph_val_tmp : integer := 0; +signal m_initial_val : integer := m_initial; + +signal m_mode_val : string(1 to 6) := " "; +signal n_mode_val : string(1 to 6) := " "; +signal lfc_val : integer := 0; +signal vco_cur : integer := vco_post_scale; +signal cp_curr_val : integer := 0; +signal lfr_val : string(1 to 2) := " "; + +signal cp_curr_old_bit_setting : integer := charge_pump_current_bits; +signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0'); +signal lfr_old_bit_setting : integer := loop_filter_r_bits; +signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0'); +signal lfc_old_bit_setting : integer := loop_filter_c_bits; +signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0'); + +signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true +-- old values +signal m_val_old : integer := 1; +signal n_val_old : integer := 1; +signal m_mode_val_old : string(1 to 6) := " "; +signal n_mode_val_old : string(1 to 6) := " "; +signal m_ph_val_old : integer := 0; +signal lfc_old : integer := 0; +signal vco_old : integer := 0; +signal cp_curr_old : integer := 0; +signal lfr_old : string(1 to 2) := " "; + signal num_output_cntrs : integer := 5; +signal scanclk_period : time := 1 ps; + signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + + signal clk_pfd : std_logic_vector(0 to 4); +signal clk0_tmp : std_logic; +signal clk1_tmp : std_logic; +signal clk2_tmp : std_logic; +signal clk3_tmp : std_logic; +signal clk4_tmp : std_logic; + +signal update_conf_latches : std_logic := '0'; +signal update_conf_latches_reg : std_logic := '0'; + +signal clkin : std_logic := '0'; +signal gate_locked : std_logic := '0'; +signal pfd_locked : std_logic := '0'; +signal lock : std_logic := '0'; +signal about_to_lock : boolean := false; +signal reconfig_err : boolean := false; + +signal inclk_c0 : std_logic; +signal inclk_c1 : std_logic; +signal inclk_c2 : std_logic; +signal inclk_c3 : std_logic; +signal inclk_c4 : std_logic; +signal inclk_m : std_logic; +signal devpor : std_logic; +signal devclrn : std_logic; + +signal inclk0_ipd : std_logic; +signal inclk1_ipd : std_logic; +signal pfdena_ipd : std_logic; +signal areset_ipd : std_logic; +signal fbin_ipd : std_logic; +signal scanclk_ipd : std_logic; +signal scanclkena_ipd, scanclkena_reg : std_logic; +signal scandata_ipd : std_logic; +signal clkswitch_ipd : std_logic; + signal phasecounterselect_ipd : std_logic_vector(2 downto 0); +signal phaseupdown_ipd : std_logic; +signal phasestep_ipd : std_logic; +signal configupdate_ipd : std_logic; +-- registered signals + +signal sig_offset : time := 0 ps; +signal sig_refclk_time : time := 0 ps; +signal sig_fbclk_period : time := 0 ps; +signal sig_vco_period_was_phase_adjusted : boolean := false; +signal sig_phase_adjust_was_scheduled : boolean := false; +signal sig_stop_vco : std_logic := '0'; +signal sig_m_times_vco_period : time := 0 ps; +signal sig_new_m_times_vco_period : time := 0 ps; +signal sig_got_refclk_posedge : boolean := false; +signal sig_got_fbclk_posedge : boolean := false; +signal sig_got_second_refclk : boolean := false; + +signal m_delay : integer := 0; +signal n_delay : integer := 0; + +signal inclk1_tmp : std_logic := '0'; + + +signal reset_low : std_logic := '0'; + +-- Phase Reconfig + + SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0); + +SIGNAL phaseupdown_reg : std_logic := '0'; +SIGNAL phasestep_reg : std_logic := '0'; +SIGNAL phasestep_high_count : integer := 0; +SIGNAL update_phase : std_logic := '0'; + +signal scandataout_tmp : std_logic := '0'; +signal scandata_in : std_logic := '0'; +signal scandata_out : std_logic := '0'; +signal scandone_tmp : std_logic := '1'; +signal initiate_reconfig : std_logic := '0'; + +signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n; + +signal schedule_vco : std_logic := '0'; + +signal areset_ena_sig : std_logic := '0'; +signal pll_in_test_mode : boolean := false; +signal pll_has_just_been_reconfigured : boolean := false; + + signal inclk_c_from_vco : std_logic_array(0 to 4); + +signal inclk_m_from_vco : std_logic; + +SIGNAL inclk0_period : time := 0 ps; +SIGNAL last_inclk0_period : time := 0 ps; +SIGNAL last_inclk0_edge : time := 0 ps; +SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0'; +SIGNAL inclk1_period : time := 0 ps; +SIGNAL last_inclk1_period : time := 0 ps; +SIGNAL last_inclk1_edge : time := 0 ps; +SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0'; + + + +COMPONENT cycloneive_mn_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial_value : IN integer := 1; + modulus : IN integer := 1; + time_delay : IN integer := 0 + ); +END COMPONENT; + +COMPONENT cycloneive_scale_cntr + PORT ( + clk : IN std_logic; + reset : IN std_logic := '0'; + cout : OUT std_logic; + initial : IN integer := 1; + high : IN integer := 1; + low : IN integer := 1; + mode : IN string := "bypass"; + ph_tap : IN integer := 0 + ); +END COMPONENT; + +COMPONENT cycloneive_dffe + GENERIC( + TimingChecksOn: Boolean := true; + InstancePath: STRING := "*"; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tipd_D : VitalDelayType01 := DefPropDelay01; + tipd_CLRN : VitalDelayType01 := DefPropDelay01; + tipd_PRN : VitalDelayType01 := DefPropDelay01; + tipd_CLK : VitalDelayType01 := DefPropDelay01; + tipd_ENA : VitalDelayType01 := DefPropDelay01); + + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +COMPONENT cycloneive_pll_reg + PORT( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC := '1'; + CLRN : in STD_LOGIC := '1'; + PRN : in STD_LOGIC := '1'; + CLK : in STD_LOGIC := '0'; + ENA : in STD_LOGIC := '1'); +END COMPONENT; + +begin + + ---------------------- + -- INPUT PATH DELAYs + ---------------------- + WireDelay : block + begin + VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0)); + VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1)); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena); + VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk); + VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena); + VitalWireDelay (scandata_ipd, scandata, tipd_scandata); + VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate); + VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch); + VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown); + VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep); + VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0)); + VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1)); + VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2)); + + end block; + +inclk_m <= fbclk when m_test_source = 0 else + refclk when m_test_source = 1 else + inclk_m_from_vco; + + areset_ena_sig <= areset_ipd or sig_stop_vco; + + + pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or + c1_test_source /= -1 or c2_test_source /= -1 or + c3_test_source /= -1 or c4_test_source /= -1) + else false; + + real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0; + m1 : cycloneive_mn_cntr + port map ( clk => inclk_m, + reset => areset_ena_sig, + cout => fbclk, + initial_value => m_initial_val, + modulus => m_val, + time_delay => m_delay + ); + + -- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed + -- in different simulation deltas. + inclk1_tmp <= inclk1_ipd; + + -- Calculate the inclk0 period + PROCESS + VARIABLE inclk0_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1'); + IF (first_inclk0_edge_detect = '0') THEN + first_inclk0_edge_detect <= '1'; + ELSE + last_inclk0_period <= inclk0_period; + inclk0_period_tmp := NOW - last_inclk0_edge; + END IF; + last_inclk0_edge <= NOW; + inclk0_period <= inclk0_period_tmp; + END PROCESS; + + + -- Calculate the inclk1 period + PROCESS + VARIABLE inclk1_period_tmp : time := 0 ps; + BEGIN + WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1'); + IF (first_inclk1_edge_detect = '0') THEN + first_inclk1_edge_detect <= '1'; + ELSE + last_inclk1_period <= inclk1_period; + inclk1_period_tmp := NOW - last_inclk1_edge; + END IF; + last_inclk1_edge <= NOW; + inclk1_period <= inclk1_period_tmp; + END PROCESS; + + process (inclk0_ipd, inclk1_tmp, clkswitch_ipd) + variable input_value : std_logic := '0'; + variable current_clock : integer := 0; + variable clk0_count, clk1_count : integer := 0; + variable clk0_is_bad, clk1_is_bad : std_logic := '0'; + variable primary_clk_is_bad : boolean := false; + variable current_clk_is_bad : boolean := false; + variable got_curr_clk_falling_edge_after_clkswitch : boolean := false; + variable switch_over_count : integer := 0; + variable active_clock : std_logic := '0'; + variable external_switch : boolean := false; + variable diff_percent_period : integer := 0; + variable buf : line; + variable switch_clock : boolean := false; + + begin + if (now = 0 ps) then + if (switch_over_type = "manual" and clkswitch_ipd = '1') then + current_clock := 1; + active_clock := '1'; + end if; + end if; + if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then + external_switch := true; + elsif (switch_over_type = "manual") then + if (clkswitch_ipd'event and clkswitch_ipd = '1') then + switch_clock := true; + elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then + switch_clock := false; + end if; + end if; + + if (switch_clock = true) then + if (inclk0_ipd'event or inclk1_tmp'event) then + if (current_clock = 0) then + current_clock := 1; + active_clock := '1'; + clkin <= transport inclk1_tmp; + elsif (current_clock = 1) then + current_clock := 0; + active_clock := '0'; + clkin <= transport inclk0_ipd; + end if; + switch_clock := false; + end if; + end if; + + -- save the current inclk event value + if (inclk0_ipd'event) then + input_value := inclk0_ipd; + elsif (inclk1_tmp'event) then + input_value := inclk1_tmp; + end if; + + -- check if either input clk is bad + if (inclk0_ipd'event and inclk0_ipd = '1') then + clk0_count := clk0_count + 1; + clk0_is_bad := '0'; + clk1_count := 0; + if (clk0_count > 2) then + -- no event on other clk for 2 cycles + clk1_is_bad := '1'; + if (current_clock = 1) then + current_clk_is_bad := true; + end if; + end if; + end if; + if (inclk1_tmp'event and inclk1_tmp = '1') then + clk1_count := clk1_count + 1; + clk1_is_bad := '0'; + clk0_count := 0; + if (clk1_count > 2) then + -- no event on other clk for 2 cycles + clk0_is_bad := '1'; + if (current_clock = 0) then + current_clk_is_bad := true; + end if; + end if; + end if; + + -- check if the bad clk is the primary clock + if (clk0_is_bad = '1') then + primary_clk_is_bad := true; + else + primary_clk_is_bad := false; + end if; + + -- actual switching + if (inclk0_ipd'event and current_clock = 0) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk0_ipd = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk0_ipd; + end if; + else + clkin <= transport inclk0_ipd; + end if; + elsif (inclk1_tmp'event and current_clock = 1) then + if (external_switch) then + if (not got_curr_clk_falling_edge_after_clkswitch) then + if (inclk1_tmp = '0') then + got_curr_clk_falling_edge_after_clkswitch := true; + end if; + clkin <= transport inclk1_tmp; + end if; + else + clkin <= transport inclk1_tmp; + end if; + else + if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then + switch_over_count := switch_over_count + 1; + end if; + if ((input_value = '0')) then + if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then + got_curr_clk_falling_edge_after_clkswitch := false; + + if (areset_ipd = '0') then + if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then + diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period; + elsif (inclk0_period /= 0 ps) then + diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period; + end if; + + if((diff_percent_period > 20)and ( switch_over_type = "auto")) then + WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality.")); + writeline(output, buf); + end if; + end if; + + if (current_clock = 0) then + current_clock := 1; + else + current_clock := 0; + end if; + active_clock := not active_clock; + switch_over_count := 0; + external_switch := false; + current_clk_is_bad := false; + else + if(switch_over_type = "auto") then + if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then + current_clock := 1; + active_clock := not active_clock; + end if; + + if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then + current_clock := 0; + active_clock := not active_clock; + end if; + end if; + end if; + + end if; + end if; + + -- schedule outputs + clkbad(0) <= clk0_is_bad; + clkbad(1) <= clk1_is_bad; + activeclock <= active_clock; + + end process; + + + n1 : cycloneive_mn_cntr + port map ( + clk => clkin, + reset => areset_ipd, + cout => refclk, + initial_value => n_val, + modulus => n_val); + +inclk_c0 <= refclk when c0_test_source = 1 else + fbclk when c0_test_source = 0 else + inclk_c_from_vco(0); + + + c0 : cycloneive_scale_cntr + port map ( + clk => inclk_c0, + reset => areset_ena_sig, + cout => c_clk(0), + initial => c_initial_val(0), + high => c_high_val(0), + low => c_low_val(0), + mode => c_mode_val(0), + ph_tap => c_ph_val(0)); + + inclk_c1 <= refclk when c1_test_source = 1 else + fbclk when c1_test_source = 0 else + c_clk(0) when c1_use_casc_in = "on" else + inclk_c_from_vco(1); + + + c1 : cycloneive_scale_cntr + port map ( + clk => inclk_c1, + reset => areset_ena_sig, + cout => c_clk(1), + initial => c_initial_val(1), + high => c_high_val(1), + low => c_low_val(1), + mode => c_mode_val(1), + ph_tap => c_ph_val(1)); + +inclk_c2 <= refclk when c2_test_source = 1 else + fbclk when c2_test_source = 0 else + c_clk(1) when c2_use_casc_in = "on" else + inclk_c_from_vco(2); + + c2 : cycloneive_scale_cntr + port map ( + clk => inclk_c2, + reset => areset_ena_sig, + cout => c_clk(2), + initial => c_initial_val(2), + high => c_high_val(2), + low => c_low_val(2), + mode => c_mode_val(2), + ph_tap => c_ph_val(2)); + + + inclk_c3 <= refclk when c3_test_source = 1 else + fbclk when c3_test_source = 0 else + c_clk(2) when c3_use_casc_in = "on" else + inclk_c_from_vco(3); + + c3 : cycloneive_scale_cntr + port map ( + clk => inclk_c3, + reset => areset_ena_sig, + cout => c_clk(3), + initial => c_initial_val(3), + high => c_high_val(3), + low => c_low_val(3), + mode => c_mode_val(3), + ph_tap => c_ph_val(3)); + + inclk_c4 <= refclk when c4_test_source = 1 else + fbclk when c4_test_source = 0 else + c_clk(3) when (c4_use_casc_in = "on") else + inclk_c_from_vco(4); + + c4 : cycloneive_scale_cntr + port map ( + clk => inclk_c4, + reset => areset_ena_sig, + cout => c_clk(4), + initial => c_initial_val(4), + high => c_high_val(4), + low => c_low_val(4), + mode => c_mode_val(4), + ph_tap => c_ph_val(4)); + + + + + + + + + + + + process(scandone_tmp, lock) + begin + if (scandone_tmp'event and (scandone_tmp = '1')) then + pll_has_just_been_reconfigured <= true; + elsif (lock'event and (lock = '1')) then + pll_has_just_been_reconfigured <= false; + end if; + end process; + + process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco) + variable c0_got_first_rising_edge : boolean := false; + variable c0_count : integer := 2; + variable c0_initial_count : integer := 1; + variable c0_tmp, c1_tmp : std_logic := '0'; + variable c1_got_first_rising_edge : boolean := false; + variable c1_count : integer := 2; + variable c1_initial_count : integer := 1; + begin + if (areset_ipd = '1' or sig_stop_vco = '1') then + c0_count := 2; + c1_count := 2; + c0_initial_count := 1; + c1_initial_count := 1; + c0_got_first_rising_edge := false; + c1_got_first_rising_edge := false; + else + if (not c0_got_first_rising_edge) then + if (inclk_c0'event and inclk_c0 = '1') then + if (c0_initial_count = c_initial_val(0)) then + c0_got_first_rising_edge := true; + else + c0_initial_count := c0_initial_count + 1; + end if; + end if; + elsif (inclk_c0'event) then + c0_count := c0_count + 1; + if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then + c0_count := 1; + end if; + end if; + if (inclk_c0'event and inclk_c0 = '0') then + if (c0_count = 1) then + c0_tmp := '1'; + c0_got_first_rising_edge := false; + else + c0_tmp := '0'; + end if; + end if; + + if (not c1_got_first_rising_edge) then + if (inclk_c1'event and inclk_c1 = '1') then + if (c1_initial_count = c_initial_val(1)) then + c1_got_first_rising_edge := true; + else + c1_initial_count := c1_initial_count + 1; + end if; + end if; + elsif (inclk_c1'event) then + c1_count := c1_count + 1; + if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then + c1_count := 1; + end if; + end if; + if (inclk_c1'event and inclk_c1 = '0') then + if (c1_count = 1) then + c1_tmp := '1'; + c1_got_first_rising_edge := false; + else + c1_tmp := '0'; + end if; + end if; + end if; + + end process; + + + locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE + lock; + + + process (scandone_tmp) + variable buf : line; + begin + if (scandone_tmp'event and scandone_tmp = '1') then + if (reconfig_err = false) then + ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note; + write (buf, string'(" N modulus = ")); + write (buf, n_val); + write (buf, string'(" ( ")); + write (buf, n_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M modulus = ")); + write (buf, m_val); + write (buf, string'(" ( ")); + write (buf, m_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + write (buf, string'(" M ph_tap = ")); + write (buf, m_ph_val); + write (buf, string'(" ( ")); + write (buf, m_ph_val_old); + write (buf, string'(" )")); + writeline (output, buf); + + for i in 0 to (num_output_cntrs-1) loop + write (buf, clk_num(i)); + write (buf, string'(" : ")); + write (buf, cntrs(i)); + write (buf, string'(" : high = ")); + write (buf, c_high_val(i)); + write (buf, string'(" (")); + write (buf, c_high_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , low = ")); + write (buf, c_low_val(i)); + write (buf, string'(" (")); + write (buf, c_low_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , mode = ")); + write (buf, c_mode_val(i)); + write (buf, string'(" (")); + write (buf, c_mode_val_old(i)); + write (buf, string'(") ")); + write (buf, string'(" , phase tap = ")); + write (buf, c_ph_val(i)); + write (buf, string'(" (")); + write (buf, c_ph_val_old(i)); + write (buf, string'(") ")); + writeline(output, buf); + end loop; + + IF (pll_reconfig_display_full_setting) THEN + write (buf, string'(" Charge Pump Current (uA) = ")); + write (buf, cp_curr_val); + write (buf, string'(" ( ")); + write (buf, cp_curr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (pF) = ")); + write (buf, lfc_val); + write (buf, string'(" ( ")); + write (buf, lfc_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (Kohm) = ")); + write (buf, lfr_val); + write (buf, string'(" ( ")); + write (buf, lfr_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + + ELSE + write (buf, string'(" Charge Pump Current (bit setting) = ")); + write (buf, alt_conv_integer(cp_curr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, cp_curr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Capacitor (bit setting) = ")); + write (buf, alt_conv_integer(lfc_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfc_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" Loop Filter Resistor (bit setting) = ")); + write (buf, alt_conv_integer(lfr_val_bit_setting)); + write (buf, string'(" ( ")); + write (buf, lfr_old_bit_setting); + write (buf, string'(" ) ")); + writeline (output, buf); + + write (buf, string'(" VCO_Post_Scale = ")); + write (buf, vco_cur); + write (buf, string'(" ( ")); + write (buf, vco_old); + write (buf, string'(" ) ")); + writeline (output, buf); + + END IF; + cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting); + lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting); + lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting); + else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning; + end if; + end if; + + end process; + + update_conf_latches <= configupdate_ipd; + + + process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd) + variable init : boolean := true; + variable low, high : std_logic_vector(7 downto 0); + variable low_fast, high_fast : std_logic_vector(3 downto 0); + variable mode : string(1 to 6) := "bypass"; + variable is_error : boolean := false; + variable m_tmp, n_tmp : std_logic_vector(8 downto 0); + variable lfr_val_tmp : string(1 to 2) := " "; + + variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1); + variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1); + variable c_mode_val_tmp : str_array(0 to 4); + variable m_val_tmp : integer := 0; + variable c0_rising_edge_transfer_done : boolean := false; + variable c1_rising_edge_transfer_done : boolean := false; + variable c2_rising_edge_transfer_done : boolean := false; + variable c3_rising_edge_transfer_done : boolean := false; + variable c4_rising_edge_transfer_done : boolean := false; + + -- variables for scaling of multiply_by and divide_by values + variable i_clk0_mult_by : integer := 1; + variable i_clk0_div_by : integer := 1; + variable i_clk1_mult_by : integer := 1; + variable i_clk1_div_by : integer := 1; + variable i_clk2_mult_by : integer := 1; + variable i_clk2_div_by : integer := 1; + variable i_clk3_mult_by : integer := 1; + variable i_clk3_div_by : integer := 1; + variable i_clk4_mult_by : integer := 1; + variable i_clk4_div_by : integer := 1; + variable max_d_value : integer := 1; + variable new_multiplier : integer := 1; + + -- internal variables for storing the phase shift number.(used in lvds mode only) + variable i_clk0_phase_shift : integer := 1; + variable i_clk1_phase_shift : integer := 1; + variable i_clk2_phase_shift : integer := 1; + + -- user to advanced variables + + variable max_neg_abs : integer := 0; + variable i_m_initial : integer; + variable i_m : integer := 1; + variable i_n : integer := 1; + variable i_c_high : int_array(0 to 4); + variable i_c_low : int_array(0 to 4); + variable i_c_initial : int_array(0 to 4); + variable i_c_ph : int_array(0 to 4); + variable i_c_mode : str_array(0 to 4); + variable i_m_ph : integer; + variable output_count : integer; + variable new_divisor : integer; + + variable clk0_cntr : string(1 to 6) := " c0"; + variable clk1_cntr : string(1 to 6) := " c1"; + variable clk2_cntr : string(1 to 6) := " c2"; + variable clk3_cntr : string(1 to 6) := " c3"; + variable clk4_cntr : string(1 to 6) := " c4"; + + variable fbk_cntr : string(1 to 2); + variable fbk_cntr_index : integer; + variable start_bit : integer; + variable quiet_time : time := 0 ps; + variable slowest_clk_old : time := 0 ps; + variable slowest_clk_new : time := 0 ps; + + variable i : integer := 0; + variable j : integer := 0; + variable scanread_active_edge : time := 0 ps; + variable got_first_scanclk : boolean := false; + variable scanclk_last_rising_edge : time := 0 ps; + variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0'); + + variable index : integer := 0; + variable Tviol_scandata_scanclk : std_ulogic := '0'; + variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_scanclkena_scanclk : std_ulogic := '0'; + variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit; + variable scan_chain_length : integer := GPP_SCAN_CHAIN; + variable tmp_rem : integer := 0; + variable scanclk_cycles : integer := 0; + variable lfc_tmp : std_logic_vector(1 downto 0); + variable lfr_tmp : std_logic_vector(5 downto 0); + variable lfr_int : integer := 0; + + variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0); + variable buf : line; + variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0'); + variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0'); + + function slowest_clk ( + C0 : integer; C0_mode : string(1 to 6); + C1 : integer; C1_mode : string(1 to 6); + C2 : integer; C2_mode : string(1 to 6); + C3 : integer; C3_mode : string(1 to 6); + C4 : integer; C4_mode : string(1 to 6); + C5 : integer; C5_mode : string(1 to 6); + C6 : integer; C6_mode : string(1 to 6); + C7 : integer; C7_mode : string(1 to 6); + C8 : integer; C8_mode : string(1 to 6); + C9 : integer; C9_mode : string(1 to 6); + refclk : time; m_mod : integer) return time is + variable max_modulus : integer := 1; + variable q_period : time := 0 ps; + variable refclk_int : integer := 0; + begin + if (C0_mode /= "bypass" and C0_mode /= " off") then + max_modulus := C0; + end if; + if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then + max_modulus := C1; + end if; + if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then + max_modulus := C2; + end if; + if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then + max_modulus := C3; + end if; + if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then + max_modulus := C4; + end if; + if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then + max_modulus := C5; + end if; + if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then + max_modulus := C6; + end if; + if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then + max_modulus := C7; + end if; + if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then + max_modulus := C8; + end if; + if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then + max_modulus := C9; + end if; + + refclk_int := refclk / 1 ps; + if (m_mod /= 0) then + q_period := (refclk_int * max_modulus / m_mod) * 1 ps; + end if; + return (2*q_period); + end slowest_clk; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + + function extract_cntr_string (arg:string) return string is + variable str : string(1 to 6) := " c0"; + begin + if (arg = "c0") then + str := " c0"; + elsif (arg = "c1") then + str := " c1"; + elsif (arg = "c2") then + str := " c2"; + elsif (arg = "c3") then + str := " c3"; + elsif (arg = "c4") then + str := " c4"; + elsif (arg = "c5") then + str := " c5"; + elsif (arg = "c6") then + str := " c6"; + elsif (arg = "c7") then + str := " c7"; + elsif (arg = "c8") then + str := " c8"; + elsif (arg = "c9") then + str := " c9"; + else str := " c0"; + + end if; + + return str; + + end extract_cntr_string; + + function extract_cntr_index (arg:string) return integer is + variable index : integer := 0; + begin + if (arg(6) = '0') then + index := 0; + elsif (arg(6) = '1') then + index := 1; + elsif (arg(6) = '2') then + index := 2; + elsif (arg(6) = '3') then + index := 3; + elsif (arg(6) = '4') then + index := 4; + elsif (arg(6) = '5') then + index := 5; + elsif (arg(6) = '6') then + index := 6; + elsif (arg(6) = '7') then + index := 7; + elsif (arg(6) = '8') then + index := 8; + else index := 9; + end if; + + return index; + end extract_cntr_index; + + function output_cntr_num (arg:string) return string is + variable str : string(1 to 6) := "unused"; + begin + if (arg = "c0") then + str := " clk0"; + elsif (arg = "c1") then + str := " clk1"; + elsif (arg = "c2") then + str := " clk2"; + elsif (arg = "c3") then + str := " clk3"; + elsif (arg = "c4") then + str := " clk4"; + elsif (arg = "c5") then + str := " clk5"; + elsif (arg = "c6") then + str := " clk6"; + elsif (arg = "c7") then + str := " clk7"; + elsif (arg = "c8") then + str := " clk8"; + elsif (arg = "c9") then + str := " clk9"; + else str := "unused"; + end if; + return str; + end output_cntr_num; + + begin + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val <= i_c_ph; + END IF; + + if (init) then + if (m = 0) then + clk4_cntr := " c4"; + clk3_cntr := " c3"; + clk2_cntr := " c2"; + clk1_cntr := " c1"; + clk0_cntr := " c0"; + else + clk4_cntr := extract_cntr_string(clk4_counter); + clk3_cntr := extract_cntr_string(clk3_counter); + clk2_cntr := extract_cntr_string(clk2_counter); + clk1_cntr := extract_cntr_string(clk1_counter); + clk0_cntr := extract_cntr_string(clk0_counter); + end if; + + clk_num(4) <= output_cntr_num(clk4_counter); + clk_num(3) <= output_cntr_num(clk3_counter); + clk_num(2) <= output_cntr_num(clk2_counter); + clk_num(1) <= output_cntr_num(clk1_counter); + clk_num(0) <= output_cntr_num(clk0_counter); + + i_clk0_counter <= extract_cntr_index(clk0_cntr); + i_clk1_counter <= extract_cntr_index(clk1_cntr); + i_clk2_counter <= extract_cntr_index(clk2_cntr); + i_clk3_counter <= extract_cntr_index(clk3_cntr); + i_clk4_counter <= extract_cntr_index(clk4_cntr); + + + if (m = 0) then -- convert user parameters to advanced + -- set the limit of the divide_by value that can be returned by + -- the following function. + max_d_value := 1500; + + -- scale down the multiply_by and divide_by values provided by the design + -- before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + + if (vco_frequency_control = "manual_phase") then + find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step, + i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + i_clk0_div_by, i_clk1_div_by, + i_clk2_div_by, i_clk3_div_by, + i_clk4_div_by, + 1,1,1,1,1, + clk0_counter, clk1_counter, + clk2_counter, clk3_counter, + clk4_counter, + "unused","unused","unused","unused","unused", + i_m, i_n); + elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then + i_n := vco_divide_by; + i_m := vco_multiply_by; + else + i_n := 1; + + if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then + i_m := i_clk0_mult_by; + else + i_m := lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, + 1,1,1,1,1, + inclk0_input_frequency); + end if; + end if; + + if (pll_type = "flvds") then + -- Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier := clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier; + i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier; + i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier; + else + i_clk0_phase_shift := str2int(clk0_phase_shift); + i_clk1_phase_shift := str2int(clk1_phase_shift); + i_clk2_phase_shift := str2int(clk2_phase_shift); + end if; + + max_neg_abs := maxnegabs(i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + 0, + 0, + 0, + 0, + 0 + ); + i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n); + + i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n); + + + i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + + + + i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + + i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n); + + i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n); + i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + + + + else -- m /= 0 + + i_n := n; + i_m := m; + i_m_initial := m_initial; + i_m_ph := m_ph; + i_c_ph(0) := c0_ph; + i_c_ph(1) := c1_ph; + i_c_ph(2) := c2_ph; + i_c_ph(3) := c3_ph; + i_c_ph(4) := c4_ph; + i_c_high(0) := c0_high; + i_c_high(1) := c1_high; + i_c_high(2) := c2_high; + i_c_high(3) := c3_high; + i_c_high(4) := c4_high; + i_c_low(0) := c0_low; + i_c_low(1) := c1_low; + i_c_low(2) := c2_low; + i_c_low(3) := c3_low; + i_c_low(4) := c4_low; + i_c_initial(0) := c0_initial; + i_c_initial(1) := c1_initial; + i_c_initial(2) := c2_initial; + i_c_initial(3) := c3_initial; + i_c_initial(4) := c4_initial; + i_c_mode(0) := translate_string(c0_mode); + i_c_mode(1) := translate_string(c1_mode); + i_c_mode(2) := translate_string(c2_mode); + i_c_mode(3) := translate_string(c3_mode); + i_c_mode(4) := translate_string(c4_mode); + + end if; -- user to advanced conversion. + + m_initial_val <= i_m_initial; + n_val <= i_n; + m_val <= i_m; + + if (i_m = 1) then + m_mode_val <= "bypass"; + else + m_mode_val <= " "; + end if; + if (i_n = 1) then + n_mode_val <= "bypass"; + else + n_mode_val <= " "; + end if; + + m_ph_val <= i_m_ph; + m_ph_initial <= i_m_ph; + m_val_tmp := i_m; + + for i in 0 to 4 loop + if (i_c_mode(i) = "bypass") then + if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then + i_c_high(i) := 16; + i_c_low(i) := 16; + else + i_c_high(i) := 256; + i_c_low(i) := 256; + end if; + end if; + c_ph_val(i) <= i_c_ph(i); + c_initial_val(i) <= i_c_initial(i); + c_high_val(i) <= i_c_high(i); + c_low_val(i) <= i_c_low(i); + c_mode_val(i) <= i_c_mode(i); + c_high_val_tmp(i) := i_c_high(i); + c_hval(i) := i_c_high(i); + c_low_val_tmp(i) := i_c_low(i); + c_lval(i) := i_c_low(i); + c_mode_val_tmp(i) := i_c_mode(i); + c_ph_val_orig(i) <= i_c_ph(i); + c_high_val_hold(i) <= i_c_high(i); + c_low_val_hold(i) <= i_c_low(i); + c_mode_val_hold(i) <= i_c_mode(i); + end loop; + + + + scan_chain_length := SCAN_CHAIN; + + + num_output_cntrs <= 5; + + init := false; + elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then + c0_rising_edge_transfer_done := false; + c1_rising_edge_transfer_done := false; + c2_rising_edge_transfer_done := false; + c3_rising_edge_transfer_done := false; + c4_rising_edge_transfer_done := false; + update_conf_latches_reg <= '0'; + elsif (update_conf_latches'event and update_conf_latches = '1') then + initiate_reconfig <= '1'; + elsif (areset_ipd'event AND areset_ipd = '1') then + if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if; + elsif (scanclk_ipd'event and scanclk_ipd = '1') then + IF (initiate_reconfig = '1') THEN + initiate_reconfig <= '0'; + ASSERT false REPORT "PLL Reprogramming Initiated" severity note; + + update_conf_latches_reg <= update_conf_latches; + reconfig_err <= false; + scandone_tmp <= '0'; + cp_curr_old <= cp_curr_val; + lfc_old <= lfc_val; + lfr_old <= lfr_val; + vco_old <= vco_cur; + -- LF unused : bit 0,1 + -- LF Capacitance : bits 2,3 : all values are legal + buf_scan_data := scan_data(2 TO 3); + + IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN + lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + ELSE + lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data)); + END IF; + -- LF Resistance : bits 4-8 + -- valid values - 00000,00100,10000,10100,11000,11011,11100,11110 + IF (scan_data(4 TO 8) = "00000") THEN + lfr_val <= "20"; + ELSIF (scan_data(4 TO 8) = "00100") THEN + lfr_val <= "16"; + ELSIF (scan_data(4 TO 8) = "10000") THEN + lfr_val <= "12"; + ELSIF (scan_data(4 TO 8) = "10100") THEN + lfr_val <= "08"; + ELSIF (scan_data(4 TO 8) = "11000") THEN + lfr_val <= "06"; + ELSIF (scan_data(4 TO 8) = "11011") THEN + lfr_val <= "04"; + ELSIF (scan_data(4 TO 8) = "11100") THEN + lfr_val <= "02"; + ELSE + lfr_val <= "01"; + END IF; + + + -- VCO post scale assignment + if (scan_data(9) = '1') then -- vco_post_scale = 1 + i_vco_max <= VCO_MAX_NO_DIVISION/2; + i_vco_min <= VCO_MIN_NO_DIVISION/2; + vco_cur <= 1; + else + i_vco_max <= vco_max; + i_vco_min <= vco_min; + vco_cur <= 2; + end if; + -- CP + -- Bit 9 : CRBYPASS + -- Bit 10-14 : unused + -- Bits 15-17 : all values are legal + + buf_scan_data_2 := scan_data(15 TO 17); + cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2)); + -- save old values for display info. + + cp_curr_val_bit_setting <= scan_data(15 TO 17); + lfc_val_bit_setting <= scan_data(2 TO 3); + lfr_val_bit_setting <= scan_data(4 TO 8); + + m_val_old <= m_val; + n_val_old <= n_val; + m_mode_val_old <= m_mode_val; + n_mode_val_old <= n_mode_val; + WHILE (i < num_output_cntrs) LOOP + c_high_val_old(i) <= c_high_val(i); + c_low_val_old(i) <= c_low_val(i); + c_mode_val_old(i) <= c_mode_val(i); + i := i + 1; + END LOOP; + -- M counter + -- 1. Mode - bypass (bit 18) + + IF (scan_data(18) = '1') THEN + n_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 27) + ELSIF (scan_data(27) = '1') THEN + n_mode_val <= " odd"; + ELSE + n_mode_val <= " even"; + END IF; + + -- 2. High (bit 19-26) + + n_hi := scan_data(19 TO 26); + + -- 4. Low (bit 28-35) + + n_lo := scan_data(28 TO 35); + -- N counter + -- 1. Mode - bypass (bit 36) + + IF (scan_data(36) = '1') THEN + m_mode_val <= "bypass"; + -- 3. Mode - odd/even (bit 45) + ELSIF (scan_data(45) = '1') THEN + m_mode_val <= " odd"; + ELSE + m_mode_val <= " even"; + END IF; + + -- 2. High (bit 37-44) + + m_hi := scan_data(37 TO 44); + + -- 4. Low (bit 46-53) + + m_lo := scan_data(46 TO 53); + -- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low + + i := 0; + WHILE (i < num_output_cntrs) LOOP + -- 1. Mode - bypass + + IF (scan_data(54 + i * 18 + 0) = '1') THEN + c_mode_val_tmp(i) := "bypass"; + -- 3. Mode - odd/even + ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN + c_mode_val_tmp(i) := " odd"; + ELSE + c_mode_val_tmp(i) := " even"; + END IF; + -- 2. Hi + + high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8); + c_hval(i) := alt_conv_integer(high); + IF (c_hval(i) /= 0) THEN + c_high_val_tmp(i) := c_hval(i); + ELSE + c_high_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + + -- 4. Low + + low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17); + c_lval(i) := alt_conv_integer(low); + IF (c_lval(i) /= 0) THEN + c_low_val_tmp(i) := c_lval(i); + ELSE + c_low_val_tmp(i) := alt_conv_integer("000000001"); + END IF; + i := i + 1; + END LOOP; + -- Legality Checks + + -- M counter value + IF(scan_data(36) /= '1') THEN + IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (m_hi /= "00000000") THEN + m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo); + ELSE + m_val_tmp := alt_conv_integer("000000001"); + END IF; + ELSE + m_val_tmp := alt_conv_integer("10000000"); + END IF; + -- N counter value + IF(scan_data(18) /= '1') THEN + IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN + reconfig_err <= TRUE; + WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work")); + writeline(output, buf); + ELSIF (n_hi /= "00000000") THEN + n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo); + ELSE + n_val <= alt_conv_integer("000000001"); + END IF; + ELSE + n_val <= alt_conv_integer("10000000"); + END IF; + -- TODO : Give warnings/errors in the following cases? + -- 1. Illegal counter values (error) + -- 2. Change of mode (warning) + -- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0) + + END IF; + end if; + + + if (fbclk'event and fbclk = '1') then + m_val <= m_val_tmp; + end if; + + if (update_conf_latches_reg = '1') then + if (scanclk_ipd'event and scanclk_ipd = '1') then + c0_rising_edge_transfer_done := true; + c_high_val(0) <= c_high_val_tmp(0); + c_mode_val(0) <= c_mode_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c1_rising_edge_transfer_done := true; + c_high_val(1) <= c_high_val_tmp(1); + c_mode_val(1) <= c_mode_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c2_rising_edge_transfer_done := true; + c_high_val(2) <= c_high_val_tmp(2); + c_mode_val(2) <= c_mode_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(3) <= c_high_val_tmp(3); + c_mode_val(3) <= c_mode_val_tmp(3); + c3_rising_edge_transfer_done := true; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1') then + c_high_val(4) <= c_high_val_tmp(4); + c_mode_val(4) <= c_mode_val_tmp(4); + c4_rising_edge_transfer_done := true; + end if; + + + + + + end if; + + if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then + c_low_val(0) <= c_low_val_tmp(0); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then + c_low_val(1) <= c_low_val_tmp(1); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then + c_low_val(2) <= c_low_val_tmp(2); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then + c_low_val(3) <= c_low_val_tmp(3); + end if; + if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then + c_low_val(4) <= c_low_val_tmp(4); + end if; + + if (update_phase = '1') then + if (vco_out(0)'event and vco_out(0) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 0) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(1)'event and vco_out(1) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 1) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(2)'event and vco_out(2) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 2) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(3)'event and vco_out(3) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 3) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(4)'event and vco_out(4) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 4) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(5)'event and vco_out(5) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 5) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(6)'event and vco_out(6) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 6) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + if (vco_out(7)'event and vco_out(7) = '0') then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + c_ph_val(i) <= c_ph_val_tmp(i); + end if; + end loop; + if (m_ph_val = 7) then + m_ph_val <= m_ph_val_tmp; + end if; + end if; + end if; + + + + if (vco_out(0)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 0) then + inclk_c_from_vco(i) <= vco_out(0); + end if; + end loop; + if (m_ph_val = 0) then + inclk_m_from_vco <= vco_out(0); + end if; + end if; + if (vco_out(1)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 1) then + inclk_c_from_vco(i) <= vco_out(1); + end if; + end loop; + if (m_ph_val = 1) then + inclk_m_from_vco <= vco_out(1); + end if; + end if; + if (vco_out(2)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 2) then + inclk_c_from_vco(i) <= vco_out(2); + end if; + end loop; + if (m_ph_val = 2) then + inclk_m_from_vco <= vco_out(2); + end if; + end if; + if (vco_out(3)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 3) then + inclk_c_from_vco(i) <= vco_out(3); + end if; + end loop; + if (m_ph_val = 3) then + inclk_m_from_vco <= vco_out(3); + end if; + end if; + if (vco_out(4)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 4) then + inclk_c_from_vco(i) <= vco_out(4); + end if; + end loop; + if (m_ph_val = 4) then + inclk_m_from_vco <= vco_out(4); + end if; + end if; + if (vco_out(5)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 5) then + inclk_c_from_vco(i) <= vco_out(5); + end if; + end loop; + if (m_ph_val = 5) then + inclk_m_from_vco <= vco_out(5); + end if; + end if; + if (vco_out(6)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 6) then + inclk_c_from_vco(i) <= vco_out(6); + end if; + end loop; + if (m_ph_val = 6) then + inclk_m_from_vco <= vco_out(6); + end if; + end if; + if (vco_out(7)'event) then + for i in 0 to 4 loop + if (c_ph_val(i) = 7) then + inclk_c_from_vco(i) <= vco_out(7); + end if; + end loop; + if (m_ph_val = 7) then + inclk_m_from_vco <= vco_out(7); + end if; + end if; + + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_scandata_scanclk, + TimingData => TimingData_scandata_scanclk, + TestSignal => scandata_ipd, + TestSignalName => "scandata", + RefSignal => scanclk_ipd, + RefSignalName => "scanclk", + SetupHigh => tsetup_scandata_scanclk_noedge_negedge, + SetupLow => tsetup_scandata_scanclk_noedge_negedge, + HoldHigh => thold_scandata_scanclk_noedge_negedge, + HoldLow => thold_scandata_scanclk_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + HeaderMsg => InstancePath & "/cycloneive_pll", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + + + VitalSetupHoldCheck ( + Violation => Tviol_scanclkena_scanclk, + TimingData => TimingData_scanclkena_scanclk, + TestSignal => scanclkena_ipd, + TestSignalName => "scanclkena", + RefSignal => scanclk_ipd, + RefSignalName => "scanclk", + SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge, + SetupLow => tsetup_scanclkena_scanclk_noedge_negedge, + HoldHigh => thold_scanclkena_scanclk_noedge_negedge, + HoldLow => thold_scanclkena_scanclk_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + HeaderMsg => InstancePath & "/cycloneive_pll", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then + scanclkena_reg <= scanclkena_ipd; + if (scanclkena_reg = '1') then + scandata_in <= scandata_ipd; + scandata_out <= scandataout_tmp; + end if; + end if; + if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then + if (got_first_scanclk) then + scanclk_period <= now - scanclk_last_rising_edge; + else + got_first_scanclk := true; + end if; + if (scanclkena_reg = '1') then + for j in scan_chain_length - 1 downto 1 loop + scan_data(j) <= scan_data(j-1); + end loop; + scan_data(0) <= scandata_in; + end if; + scanclk_last_rising_edge := now; + end if; + end process; + +-- PLL Phase Reconfiguration + +PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd) + VARIABLE i : INTEGER := 0; + VARIABLE c_ph : INTEGER := 0; + VARIABLE m_ph : INTEGER := 0; + VARIABLE select_counter : INTEGER := 0; +BEGIN + IF (NOW = 0 ps) THEN + m_ph_val_tmp <= m_ph_initial; + END IF; + + -- Latch phase enable (same as phasestep) on neg edge of scan clock + IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN + phasestep_reg <= phasestep_ipd; + END IF; + + IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN + IF (update_phase = '0') THEN + phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart + -- if not, next phasestep cycle is skipped + END IF; + END IF; + -- revert counter phase tap values to POF programmed values + -- if PLL is reset + + IF (areset_ipd'EVENT AND areset_ipd = '1') then + c_ph_val_tmp <= c_ph_val_orig; + m_ph_val_tmp <= m_ph_initial; + END IF; + + IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN + IF (phasestep_reg = '1') THEN + IF (phasestep_high_count = 1) THEN + phasecounterselect_reg <= phasecounterselect_ipd; + phaseupdown_reg <= phaseupdown_ipd; + -- start reconfiguration + IF (phasecounterselect_ipd < "111") THEN -- no counters selected + IF (phasecounterselect_ipd = "000") THEN + i := 0; + WHILE (i < num_output_cntrs) LOOP + c_ph := c_ph_val(i); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(i) <= c_ph; + i := i + 1; + END LOOP; + ELSIF (phasecounterselect_ipd = "001") THEN + m_ph := m_ph_val; + IF (phaseupdown_ipd = '1') THEN + m_ph := (m_ph + 1) mod num_phase_taps; + ELSIF (m_ph = 0) THEN + m_ph := num_phase_taps - 1; + ELSE + m_ph := (m_ph - 1) mod num_phase_taps; + END IF; + m_ph_val_tmp <= m_ph; + ELSE + select_counter := alt_conv_integer(phasecounterselect_ipd) - 2; + c_ph := c_ph_val(select_counter); + IF (phaseupdown_ipd = '1') THEN + c_ph := (c_ph + 1) mod num_phase_taps; + ELSIF (c_ph = 0) THEN + c_ph := num_phase_taps - 1; + ELSE + c_ph := (c_ph - 1) mod num_phase_taps; + END IF; + c_ph_val_tmp(select_counter) <= c_ph; + END IF; + update_phase <= '1','0' AFTER (0.5 * scanclk_period); + END IF; + END IF; + phasestep_high_count <= phasestep_high_count + 1; + + END IF; + END IF; +END PROCESS; + + scandataout_tmp <= scan_data(SCAN_CHAIN - 2); + + process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk) + variable sched_time : time := 0 ps; + + TYPE time_array is ARRAY (0 to 7) of time; + variable init : boolean := true; + variable refclk_period : time; + variable m_times_vco_period : time; + variable new_m_times_vco_period : time; + + variable phase_shift : time_array := (OTHERS => 0 ps); + variable last_phase_shift : time_array := (OTHERS => 0 ps); + + variable l_index : integer := 1; + variable cycle_to_adjust : integer := 0; + + variable stop_vco : boolean := false; + + variable locked_tmp : std_logic := '0'; + variable pll_is_locked : boolean := false; + variable cycles_pfd_low : integer := 0; + variable cycles_pfd_high : integer := 0; + variable cycles_to_lock : integer := 0; + variable cycles_to_unlock : integer := 0; + + variable got_first_refclk : boolean := false; + variable got_second_refclk : boolean := false; + variable got_first_fbclk : boolean := false; + + variable refclk_time : time := 0 ps; + variable fbclk_time : time := 0 ps; + variable first_fbclk_time : time := 0 ps; + + variable fbclk_period : time := 0 ps; + + variable first_schedule : boolean := true; + + variable vco_val : std_logic := '0'; + variable vco_period_was_phase_adjusted : boolean := false; + variable phase_adjust_was_scheduled : boolean := false; + + variable loop_xplier : integer; + variable loop_initial : integer := 0; + variable loop_ph : integer := 0; + variable loop_time_delay : integer := 0; + + variable initial_delay : time := 0 ps; + variable vco_per : time; + variable tmp_rem : integer; + variable my_rem : integer; + variable fbk_phase : integer := 0; + + variable pull_back_M : integer := 0; + variable total_pull_back : integer := 0; + variable fbk_delay : integer := 0; + + variable offset : time := 0 ps; + + variable tmp_vco_per : integer := 0; + variable high_time : time; + variable low_time : time; + + variable got_refclk_posedge : boolean := false; + variable got_fbclk_posedge : boolean := false; + variable inclk_out_of_range : boolean := false; + variable no_warn : boolean := false; + + variable ext_fbk_cntr_modulus : integer := 1; + variable init_clks : boolean := true; + variable pll_is_in_reset : boolean := false; + variable buf : line; + begin + if (init) then + + -- jump-start the VCO + -- add 1 ps delay to ensure all signals are updated to initial + -- values + schedule_vco <= transport not schedule_vco after 1 ps; + + init := false; + end if; + + if (schedule_vco'event) then + if (init_clks) then + refclk_period := inclk0_input_frequency * n_val * 1 ps; + + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + init_clks := false; + end if; + sched_time := 0 ps; + for i in 0 to 7 loop + last_phase_shift(i) := phase_shift(i); + end loop; + cycle_to_adjust := 0; + l_index := 1; + m_times_vco_period := new_m_times_vco_period; + end if; + + -- areset was asserted + if (areset_ipd'event and areset_ipd = '1') then + assert false report family_name & " PLL was reset" severity note; + -- reset lock parameters + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + end if; + + if (areset_ipd = '1') then + pll_is_in_reset := true; + got_first_refclk := false; + got_second_refclk := false; + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after 1 ps; + end loop; + end if; + + + if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then + + -- drop VCO taps to 0 + for i in 0 to 7 loop + vco_out(i) <= transport '0' after last_phase_shift(i); + phase_shift(i) := 0 ps; + last_phase_shift(i) := 0 ps; + end loop; + + -- reset lock parameters + pll_is_locked := false; + cycles_to_lock := 0; + cycles_to_unlock := 0; + + got_first_refclk := false; + got_second_refclk := false; + refclk_time := 0 ps; + got_first_fbclk := false; + fbclk_time := 0 ps; + first_fbclk_time := 0 ps; + fbclk_period := 0 ps; + + first_schedule := true; + vco_val := '0'; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + + elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then + + -- note areset deassert time + -- note it as refclk_time to prevent false triggering + -- of stop_vco after areset + if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then + refclk_time := now; + locked_tmp := '0'; + end if; + + pll_is_in_reset := false; + -- calculate loop_xplier : this will be different from m_val + -- in external_feedback_mode + loop_xplier := m_val; + loop_initial := m_initial_val - 1; + loop_ph := m_ph_val; + + + -- convert initial value to delay + initial_delay := (loop_initial * m_times_vco_period)/loop_xplier; + + -- convert loop ph_tap to delay + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier; + if (my_rem /= 0) then + tmp_vco_per := tmp_vco_per + 1; + end if; + fbk_phase := (loop_ph * tmp_vco_per)/8; + + pull_back_M := initial_delay/1 ps + fbk_phase; + + total_pull_back := pull_back_M; + + if (simulation_type = "timing") then + total_pull_back := total_pull_back + pll_compensation_delay; + end if; + while (total_pull_back > refclk_period/1 ps) loop + total_pull_back := total_pull_back - refclk_period/1 ps; + end loop; + + if (total_pull_back > 0) then + offset := refclk_period - (total_pull_back * 1 ps); + end if; + + fbk_delay := total_pull_back - fbk_phase; + if (fbk_delay < 0) then + offset := offset - (fbk_phase * 1 ps); + fbk_delay := total_pull_back; + end if; + + -- assign m_delay + m_delay <= transport fbk_delay after 1 ps; + + my_rem := (m_times_vco_period/1 ps) rem loop_xplier; + for i in 1 to loop_xplier loop + -- adjust cycles + tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier; + if (my_rem /= 0 and l_index <= my_rem) then + tmp_rem := (loop_xplier * l_index) rem my_rem; + cycle_to_adjust := (loop_xplier * l_index) / my_rem; + if (tmp_rem /= 0) then + cycle_to_adjust := cycle_to_adjust + 1; + end if; + end if; + if (cycle_to_adjust = i) then + tmp_vco_per := tmp_vco_per + 1; + l_index := l_index + 1; + end if; + + -- calculate high and low periods + vco_per := tmp_vco_per * 1 ps; + high_time := (tmp_vco_per/2) * 1 ps; + if (tmp_vco_per rem 2 /= 0) then + high_time := high_time + 1 ps; + end if; + low_time := vco_per - high_time; + + -- schedule the rising and falling edges + for j in 1 to 2 loop + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + if (first_schedule) then + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + else + vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k)); + end if; + end loop; + end loop; + end loop; + + -- schedule once more + if (first_schedule) then + vco_val := not vco_val; + if (vco_val = '0') then + sched_time := sched_time + high_time; + elsif (vco_val = '1') then + sched_time := sched_time + low_time; + end if; + -- schedule the phase taps + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + vco_out(k) <= transport vco_val after (sched_time + phase_shift(k)); + end loop; + first_schedule := false; + end if; + + schedule_vco <= transport not schedule_vco after sched_time; + + if (vco_period_was_phase_adjusted) then + m_times_vco_period := refclk_period; + new_m_times_vco_period := refclk_period; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := true; + + vco_per := m_times_vco_period/loop_xplier; + for k in 0 to 7 loop + phase_shift(k) := (k * vco_per)/8; + end loop; + end if; + end if; +-- Bypass lock detect + +if (refclk'event and refclk = '1' and areset_ipd = '0') then + if (test_bypass_lock_detect = "on") then + if (pfdena_ipd = '1') then + cycles_pfd_low := 0; + if (pfd_locked = '0') then + if (cycles_pfd_high = lock_high) then + assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning; + pfd_locked <= '1'; + end if; + cycles_pfd_high := cycles_pfd_high + 1; + end if; + end if; + + if (pfdena_ipd = '0') then + cycles_pfd_high := 0; + if (pfd_locked = '1') then + if (cycles_pfd_low = lock_low) then + assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning; + pfd_locked <= '0'; + end if; + cycles_pfd_low := cycles_pfd_low + 1; + end if; + end if; + end if; + + + if (refclk'event and refclk = '1' and areset_ipd = '0') then + got_refclk_posedge := true; + if (not got_first_refclk) then + got_first_refclk := true; + else + got_second_refclk := true; + refclk_period := now - refclk_time; + + -- check if incoming freq. will cause VCO range to be + -- exceeded + if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and + (((refclk_period/1 ps)/loop_xplier > i_vco_max) or + ((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then + if (pll_is_locked) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + if (inclk_out_of_range) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + end if; + elsif (not no_warn) then + if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then + assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_over <= '1'; + end if; + if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then + assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning; + vco_under <= '1'; + end if; + assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning; + no_warn := true; + end if; + inclk_out_of_range := true; + else + vco_over <= '0'; + vco_under <= '0'; + inclk_out_of_range := false; + no_warn := false; + end if; + end if; + end if; + + if (stop_vco) then + stop_vco := false; + schedule_vco <= not schedule_vco; + end if; + + refclk_time := now; + else + got_refclk_posedge := false; + end if; + +-- Update M counter value on feedback clock edge + + if (fbclk'event and fbclk = '1') then + got_fbclk_posedge := true; + if (not got_first_fbclk) then + got_first_fbclk := true; + else + fbclk_period := now - fbclk_time; + end if; + + -- need refclk_period here, so initialized to proper value above + if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or + ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or + ( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then + stop_vco := true; + -- reset + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + if (pll_is_locked) then + pll_is_locked := false; + locked_tmp := '0'; + assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note; + if ((i_vco_max = 0) and (i_vco_min = 0)) then + assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note; + end if; + end if; + cycles_to_lock := 0; + cycles_to_unlock := 0; + first_schedule := true; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + end if; + fbclk_time := now; + else + got_fbclk_posedge := false; + end if; + + if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then + + -- now we know actual incoming period + if ( abs(fbclk_time - refclk_time) <= 5 ps or + (got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then + -- considered in phase + if (cycles_to_lock = real_lock_high) then + if (not pll_is_locked) then + assert false report family_name & " PLL locked to incoming clock" severity note; + end if; + pll_is_locked := true; + locked_tmp := '1'; + cycles_to_unlock := 0; + end if; + -- increment lock counter only if second part of above + -- time check is NOT true + if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then + cycles_to_lock := cycles_to_lock + 1; + end if; + + -- adjust m_times_vco_period + new_m_times_vco_period := refclk_period; + else + -- if locked, begin unlock + if (pll_is_locked) then + cycles_to_unlock := cycles_to_unlock + 1; + if (cycles_to_unlock = lock_low) then + pll_is_locked := false; + locked_tmp := '0'; + cycles_to_lock := 0; + vco_period_was_phase_adjusted := false; + phase_adjust_was_scheduled := false; + assert false report family_name & " PLL lost lock." severity note; + got_first_refclk := false; + got_first_fbclk := false; + got_second_refclk := false; + end if; + end if; + if ( abs(refclk_period - fbclk_period) <= 2 ps ) then + -- frequency is still good + if (now = fbclk_time and (not phase_adjust_was_scheduled)) then + if ( abs(fbclk_time - refclk_time) > refclk_period/2) then + new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted := true; + else + new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted := true; + end if; + + end if; + else + phase_adjust_was_scheduled := false; + new_m_times_vco_period := refclk_period; + end if; + end if; + end if; + + if (pfdena_ipd = '0') then + if (pll_is_locked) then + locked_tmp := 'X'; + end if; + pll_is_locked := false; + cycles_to_lock := 0; + end if; + + -- give message only at time of deassertion + if (pfdena_ipd'event and pfdena_ipd = '0') then + assert false report "PFDENA deasserted." severity note; + elsif (pfdena_ipd'event and pfdena_ipd = '1') then + got_first_refclk := false; + got_second_refclk := false; + refclk_time := now; + end if; + + if (reconfig_err) then + lock <= '0'; + else + lock <= locked_tmp; + end if; + + -- signal to calculate quiet_time + sig_refclk_period <= refclk_period; + + if (stop_vco = true) then + sig_stop_vco <= '1'; + else + sig_stop_vco <= '0'; + end if; + + pll_locked <= pll_is_locked; + end process; + + clk0_tmp <= c_clk(i_clk0_counter); + clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE + clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else + 'X'; + + clk1_tmp <= c_clk(i_clk1_counter); + clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE + clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk2_tmp <= c_clk(i_clk2_counter); + clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE + clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk3_tmp <= c_clk(i_clk3_counter); + clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE + clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + clk4_tmp <= c_clk(i_clk4_counter); + clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X'; + clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE + clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X'; + + + + + + + + + + + + +scandataout <= scandata_out; +scandone <= NOT scandone_tmp; +phasedone <= NOT update_phase; +vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over; +vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under; +fbout <= fbclk; +end vital_pll; +-- END ARCHITECTURE VITAL_PLL +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_ff +-- +-- Description : Cycloneive FF VHDL simulation model +-- +-- +--------------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; +use work.cycloneive_and1; + +entity cycloneive_ff is + generic ( + power_up : string := "low"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneive_ff"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + clrn : in std_logic := '1'; + aload : in std_logic := '0'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + ena : in std_logic := '1'; + asdata : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneive_ff : entity is TRUE; +end cycloneive_ff; + +architecture vital_lcell_ff of cycloneive_ff is + attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE; + signal clk_ipd : std_logic; + signal d_ipd : std_logic; + signal d_dly : std_logic; + signal asdata_ipd : std_logic; + signal asdata_dly : std_logic; + signal asdata_dly1 : std_logic; + signal sclr_ipd : std_logic; + signal sload_ipd : std_logic; + signal clrn_ipd : std_logic; + signal aload_ipd : std_logic; + signal ena_ipd : std_logic; + +component cycloneive_and1 + generic (XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01 + ); + + port (Y : out STD_LOGIC; + IN1 : in STD_LOGIC + ); +end component; + +begin + +ddelaybuffer: cycloneive_and1 + port map(IN1 => d_ipd, + Y => d_dly); + +asdatadelaybuffer: cycloneive_and1 + port map(IN1 => asdata_ipd, + Y => asdata_dly); + +asdatadelaybuffer1: cycloneive_and1 + port map(IN1 => asdata_dly, + Y => asdata_dly1); + + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (asdata_ipd, asdata, tipd_asdata); + VitalWireDelay (sclr_ipd, sclr, tipd_sclr); + VitalWireDelay (sload_ipd, sload, tipd_sload); + VitalWireDelay (clrn_ipd, clrn, tipd_clrn); + VitalWireDelay (aload_ipd, aload, tipd_aload); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + VITALtiming : process (clk_ipd, d_dly, asdata_dly1, + sclr_ipd, sload_ipd, clrn_ipd, aload_ipd, + ena_ipd, devclrn, devpor) + + variable Tviol_d_clk : std_ulogic := '0'; + variable Tviol_asdata_clk : std_ulogic := '0'; + variable Tviol_sclr_clk : std_ulogic := '0'; + variable Tviol_sload_clk : std_ulogic := '0'; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + + variable iq : std_logic := '0'; + variable idata: std_logic := '0'; + + -- variables for 'X' generation + variable violation : std_logic := '0'; + + begin + + if (now = 0 ns) then + if (power_up = "low") then + iq := '0'; + elsif (power_up = "high") then + iq := '1'; + end if; + end if; + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_clk, + TimingData => TimingData_d_clk, + TestSignal => d, + TestSignalName => "DATAIN", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (sload_ipd) OR + (sclr_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_asdata_clk, + TimingData => TimingData_asdata_clk, + TestSignal => asdata_ipd, + TestSignalName => "ASDATA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_asdata_clk_noedge_posedge, + SetupLow => tsetup_asdata_clk_noedge_posedge, + HoldHigh => thold_asdata_clk_noedge_posedge, + HoldLow => thold_asdata_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT sload_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_sclr_clk, + TimingData => TimingData_sclr_clk, + TestSignal => sclr_ipd, + TestSignalName => "SCLR", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_sclr_clk_noedge_posedge, + SetupLow => tsetup_sclr_clk_noedge_posedge, + HoldHigh => thold_sclr_clk_noedge_posedge, + HoldLow => thold_sclr_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_sload_clk, + TimingData => TimingData_sload_clk, + TestSignal => sload_ipd, + TestSignalName => "SLOAD", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_sload_clk_noedge_posedge, + SetupLow => tsetup_sload_clk_noedge_posedge, + HoldHigh => thold_sload_clk_noedge_posedge, + HoldLow => thold_sload_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena_ipd, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) ) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + violation := Tviol_d_clk or Tviol_asdata_clk or + Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk; + + + if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then + iq := '0'; + elsif (aload_ipd = '1') then + iq := asdata_dly1; + elsif (violation = 'X' and x_on_violation = "on") then + iq := 'X'; + elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then + if (ena_ipd = '1') then + if (sclr_ipd = '1') then + iq := '0'; + elsif (sload_ipd = '1') then + iq := asdata_dly1; + else + iq := d_dly; + end if; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => iq, + Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE), + 1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE), + 2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE), + 3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end vital_lcell_ff; + +---------------------------------------------------------------------------- +-- Module Name : cycloneive_ram_register +-- Description : Register module for RAM inputs/outputs +---------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneive_atom_pack.all; + +ENTITY cycloneive_ram_register IS + +GENERIC ( + width : INTEGER := 1; + preset : STD_LOGIC := '0'; + tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_stall : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst + ); + +PORT ( + d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + clk : IN STD_LOGIC; + ena : IN STD_LOGIC; + stall : IN STD_LOGIC; + aclr : IN STD_LOGIC; + devclrn : IN STD_LOGIC; + devpor : IN STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + aclrout : OUT STD_LOGIC + ); + +END cycloneive_ram_register; + +ARCHITECTURE reg_arch OF cycloneive_ram_register IS + +SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0); +SIGNAL clk_ipd : STD_LOGIC; +SIGNAL ena_ipd : STD_LOGIC; +SIGNAL aclr_ipd : STD_LOGIC; + SIGNAL stall_ipd : STD_LOGIC; + +BEGIN + +WireDelay : BLOCK +BEGIN + loopbits : FOR i in d'RANGE GENERATE + VitalWireDelay (d_ipd(i), d(i), tipd_d(i)); + END GENERATE; + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (stall_ipd, stall, tipd_stall); +END BLOCK; + + PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor) +VARIABLE Tviol_clk_ena : STD_ULOGIC := '0'; +VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0'; +VARIABLE Tviol_data_clk : STD_ULOGIC := '0'; +VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit; + VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit; +VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit; +VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit; +VARIABLE Tviol_ena : STD_ULOGIC := '0'; +VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit; +VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0); +VARIABLE CQDelay : TIME := 0 ns; +VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset); +BEGIN + + IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN + q_reg := (OTHERS => preset); + ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN + q_reg := d_ipd; + END IF; + + -- Timing checks + VitalSetupHoldCheck ( + Violation => Tviol_clk_ena, + TimingData => TimingData_clk_ena, + TestSignal => ena_ipd, + TestSignalName => "ena", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_clk_ena, + TimingData => TimingData_clk_stall, + TestSignal => stall_ipd, + TestSignalName => "stall", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_stall_clk_noedge_posedge, + SetupLow => tsetup_stall_clk_noedge_posedge, + HoldHigh => thold_stall_clk_noedge_posedge, + HoldLow => thold_stall_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_clk_aclr, + TimingData => TimingData_clk_aclr, + TestSignal => aclr_ipd, + TestSignalName => "aclr", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_aclr_clk_noedge_posedge, + SetupLow => tsetup_aclr_clk_noedge_posedge, + HoldHigh => thold_aclr_clk_noedge_posedge, + HoldLow => thold_aclr_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_data_clk, + TimingData => TimingData_data_clk, + TestSignal => d_ipd, + TestSignalName => "data", + RefSignal => clk_ipd, + RefSignalName => "clk", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => "/RAM Register VitalSetupHoldCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + VitalPeriodPulseCheck ( + Violation => Tviol_ena, + PeriodData => PeriodData_ena, + TestSignal => ena_ipd, + TestSignalName => "ena", + PulseWidthHigh => tpw_ena_posedge, + HeaderMsg => "/RAM Register VitalPeriodPulseCheck", + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks ); + + -- Path Delay Selection + CQDelay := SelectDelay ( + Paths => ( + (0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE), + 1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE)) + ) + ); + q <= TRANSPORT q_reg AFTER CQDelay; + +END PROCESS; + +aclrout <= aclr_ipd; + +END reg_arch; + +---------------------------------------------------------------------------- +-- Module Name : cycloneive_ram_pulse_generator +-- Description : Generate pulse to initiate memory read/write operations +---------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneive_atom_pack.all; + +ENTITY cycloneive_ram_pulse_generator IS +GENERIC ( + tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns); + tipd_ena : VitalDelayType01 := DefPropDelay01; + tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01 + ); +PORT ( + clk,ena : IN STD_LOGIC; +delaywrite : IN STD_LOGIC := '0'; + pulse,cycle : OUT STD_LOGIC + ); +ATTRIBUTE VITAL_Level0 OF cycloneive_ram_pulse_generator:ENTITY IS TRUE; +END cycloneive_ram_pulse_generator; + +ARCHITECTURE pgen_arch OF cycloneive_ram_pulse_generator IS +SIGNAL clk_ipd,ena_ipd : STD_LOGIC; +SIGNAL state : STD_LOGIC; +ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE; +BEGIN + +WireDelay : BLOCK +BEGIN + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (ena_ipd, ena, tipd_ena); +END BLOCK; + +PROCESS (clk_ipd,state) +BEGIN + IF (state = '1' AND state'EVENT) THEN + state <= '0'; + ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN + IF (delaywrite = '1') THEN + state <= '1' AFTER 1 NS; -- delayed write + ELSE + state <= '1'; + END IF; + END IF; +END PROCESS; + +PathDelay : PROCESS +VARIABLE pulse_VitalGlitchData : VitalGlitchDataType; +BEGIN + WAIT UNTIL state'EVENT; + VitalPathDelay01 ( + OutSignal => pulse, + OutSignalName => "pulse", + OutTemp => state, + Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)), + GlitchData => pulse_VitalGlitchData, + Mode => DefGlitchMode, + XOn => DefXOnChecks, + MsgOn => DefMsgOnChecks + ); +END PROCESS; + +cycle <= clk_ipd; + +END pgen_arch; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.VITAL_Timing.all; +USE IEEE.VITAL_Primitives.all; +USE work.cycloneive_atom_pack.all; +USE work.cycloneive_ram_register; +USE work.cycloneive_ram_pulse_generator; + +ENTITY cycloneive_ram_block IS + GENERIC ( + -- -------- GLOBAL PARAMETERS --------- + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock: STRING := "clock1"; + port_b_read_enable_clock: STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + safe_write : STRING := "err_on_2clk"; + init_file_restructured : STRING := "unused"; + lpm_type : string := "cycloneive_ram_block"; + lpm_hint : string := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : BIT_VECTOR := X"0"; + mem_init1 : BIT_VECTOR := X"0"; + mem_init2 : BIT_VECTOR := X"0"; + mem_init3 : BIT_VECTOR := X"0"; + mem_init4 : BIT_VECTOR := X"0"; + connectivity_checking : string := "off" + ); + -- -------- PORT DECLARATIONS --------- + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); + +END cycloneive_ram_block; + +ARCHITECTURE block_arch OF cycloneive_ram_block IS + +COMPONENT cycloneive_ram_pulse_generator + PORT ( + clk : IN STD_LOGIC; + ena : IN STD_LOGIC; + delaywrite : IN STD_LOGIC := '0'; + pulse : OUT STD_LOGIC; + cycle : OUT STD_LOGIC + ); +END COMPONENT; + +COMPONENT cycloneive_ram_register + GENERIC ( + preset : STD_LOGIC := '0'; + width : integer := 1 + ); + PORT ( + d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + clk : IN STD_LOGIC; + aclr : IN STD_LOGIC; + devclrn : IN STD_LOGIC; + devpor : IN STD_LOGIC; + ena : IN STD_LOGIC; + stall : IN STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0); + aclrout : OUT STD_LOGIC + ); +END COMPONENT; + +FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS +VARIABLE c: INTEGER; +BEGIN + IF (condition) THEN c := a; ELSE c := b; END IF; + RETURN c; +END; + +SUBTYPE port_type IS BOOLEAN; + +CONSTANT primary : port_type := TRUE; +CONSTANT secondary : port_type := FALSE; + +CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width); +CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a; + +CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom"); +CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port"); +CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port"); +CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port"); + +CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1) + AND (port_a_data_width /= port_b_data_width); +CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1, + cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width)))); +CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width); +CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width); + +CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width); +CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width); + +CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width; +CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width; + +CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED"); +CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED"); + +CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0'); +CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0'); + + CONSTANT ram_type : BOOLEAN := FALSE; + +TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC; +CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0'); + +-- Hardware write modes + +CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR + operation_mode = "bidir_dual_port") AND + (port_b_address_clock = "clock1"); +CONSTANT both_new_data_same_port : BOOLEAN := ( + ((port_a_read_during_write_mode = "new_data_no_nbe_read") OR + (port_a_read_during_write_mode = "dont_care")) AND + ((port_b_read_during_write_mode = "new_data_no_nbe_read") OR + (port_b_read_during_write_mode = "dont_care")) + ); +SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1); +SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1); + +SIGNAL delay_write_pulse_a : STD_LOGIC ; +SIGNAL delay_write_pulse_b : STD_LOGIC ; + +CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read"); +CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read"); + +CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data"); +CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data"); + +SIGNAL read_before_write_a : BOOLEAN; +SIGNAL read_before_write_b : BOOLEAN; + +-- -------- internal signals --------- +SIGNAL portadatain_int : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL portaaddr_int : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0); +SIGNAL portabyteenamasks_int : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0); +SIGNAL portbdatain_int : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL portbaddr_int : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0); +SIGNAL portbbyteenamasks_int : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0); + SIGNAL portaaddrstall_int : STD_LOGIC; + SIGNAL portbaddrstall_int : STD_LOGIC; +-- clock / clock enable +SIGNAL clk_a_in,clk_b_in : STD_LOGIC; +SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC; +SIGNAL clk_a_out,clk_b_out : STD_LOGIC; +SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC; +SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC; +SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC; + +SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC; +SIGNAL clk_a_core : STD_LOGIC; + +SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC; +SIGNAL clk_b_core : STD_LOGIC; + +SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0); + +-- asynch clear +TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; +TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC; +SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC; +SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC; +SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC; +SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type; +SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type; + SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC; + SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type; + SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type; + + +SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC; +SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC; +SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC; +SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC; +SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC; +SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC; +SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC; +SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type; +SIGNAL clear_asserted_during_write : clear_vec_type; + + +-- port A registers +SIGNAL we_a_reg : STD_LOGIC; +SIGNAL re_a_reg : STD_LOGIC; +SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type; +SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type; +SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0); +SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); +SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0); +-- port B registers +SIGNAL we_b_reg, re_b_reg : STD_LOGIC; +SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type; +SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0); +SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0); +SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0); +-- pulses +TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC; +SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec; +SIGNAL rw_pulse : pulse_vec; +SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC; +SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC; +SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC; +SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC; +-- registered address +SIGNAL addr_prime_reg,addr_sec_reg : INTEGER; +-- input/output +SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0); +SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0); +-- overlapping location write +SIGNAL dual_write : BOOLEAN; +-- byte enable mask write +TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; +SIGNAL be_mask_write : be_mask_write_vec; +-- memory core +SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0); +SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0); +TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type; +TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type; +SIGNAL mem : mem_type; +SIGNAL init_mem : BOOLEAN := FALSE; +CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X'))); +CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X')); +CONSTANT col_x : mem_col_type := (OTHERS => 'X'); +SIGNAL mem_data : mem_row_type; +SIGNAL old_mem_data : mem_row_type; +SIGNAL mem_unit_data : mem_col_type; + +-- latches +TYPE read_latch_rec IS RECORD + prime : mem_row_type; + sec : mem_col_type; +END RECORD; +SIGNAL read_latch : read_latch_rec; +-- (row,column) coordinates +SIGNAL row_sec,col_sec : INTEGER; +-- byte enable +TYPE mask_type IS (normal,inverse); +TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type; +TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type; +TYPE mask_rec IS RECORD + prime : mask_prime_type; + sec : mask_sec_type; +END RECORD; +SIGNAL mask_vector : mask_rec; +SIGNAL mask_vector_common : mem_col_type; + +FUNCTION get_mask( + b_ena : IN STD_LOGIC_VECTOR; + mode : port_type; + CONSTANT b_ena_width ,byte_size: INTEGER +) RETURN mask_rec IS + +VARIABLE l : INTEGER; +VARIABLE mask : mask_rec := ( + (normal => (OTHERS => '0'),inverse => (OTHERS => 'X')), + (normal => (OTHERS => '0'),inverse => (OTHERS => 'X')) + ); +BEGIN + FOR l in 0 TO b_ena_width - 1 LOOP + IF (b_ena(l) = '0') THEN + IF (mode = primary) THEN + mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0'); + ELSE + mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0'); + END IF; + ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN + IF (mode = primary) THEN + mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + ELSE + mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X'); + END IF; + END IF; + END LOOP; + RETURN mask; +END get_mask; +-- port active for read/write +SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type; +SIGNAL active_a_in,active_b_in : STD_LOGIC; +SIGNAL active_write_a : BOOLEAN; +SIGNAL active_write_b : BOOLEAN; +SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC; +SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC; +SIGNAL active_a_core, active_b_core : BOOLEAN; +SIGNAL wire_vcc : STD_LOGIC := '1'; +SIGNAL wire_gnd : STD_LOGIC := '0'; + + + + + + +BEGIN + -- memory initialization + init_mem <= TRUE; + -- hardware write modes + hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR + (port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE + " FW" WHEN (dual_clock OR ( + mixed_port_feed_through_mode = "dont_care" AND + both_new_data_same_port + )) ELSE + " DW"; + + hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR + (port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE + " FW" WHEN (dual_clock OR ( + mixed_port_feed_through_mode = "dont_care" AND + both_new_data_same_port + )) ELSE + " DW"; + delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0'; + delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ; + read_before_write_a <= (hw_write_mode_a = "R+W"); + read_before_write_b <= (hw_write_mode_b = "R+W"); + + -- -------- core logic --------------- + portadatain_int <= portadatain; + portaaddr_int <= portaaddr; + portabyteenamasks_int <= portabyteenamasks; + portbdatain_int <= portbdatain; + portbaddr_int <= portbaddr; + portbbyteenamasks_int <= portbbyteenamasks; + portaaddrstall_int <= portaaddrstall; + portbaddrstall_int <= portbaddrstall; + clk_a_in <= clk0; + clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk0; + clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk0; + + clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk0; + clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE + clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1; + + clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1; + clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE + clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1; + clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE + clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE + clk1; + clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE + clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE + clk1; + clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE + clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1; + + addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0; + addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE + clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1; + + datain_a_clr_in <= '0'; + datain_b_clr_in <= '0'; + + dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE + clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1; + dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE + '0'; + + dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE + clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1; + dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE + '0'; + + byteena_a_clr_in <= '0'; + byteena_b_clr_in <= '0'; + we_a_clr_in <= '0'; + re_a_clr_in <= '0'; + we_b_clr_in <= '0'; + re_b_clr_in <= '0'; + + active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE + ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE + ena2; + active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE + ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE + ena2; + + be_mask_write(primary_port_is_a) <= be_mask_write_a; + be_mask_write(primary_port_is_b) <= be_mask_write_b; + + active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE + ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE + ena2; + active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE + ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE + ena3; + active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1; + active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE + ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE + ena2; + active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE + ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE + ena3; + active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1; + + active_write_a <= (byteena_a_reg /= bytes_a_disabled); + + active_write_b <= (byteena_b_reg /= bytes_b_disabled); + + -- Store core clock enable value for delayed write + -- port A core active + active_a_core_in_vec(0) <= active_a_core_in; + active_core_port_a : cycloneive_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => active_a_core_in_vec, + clk => clk_a_in, + aclr => wire_gnd, + devclrn => wire_vcc,devpor => wire_vcc, + ena => wire_vcc, + stall => wire_gnd, + q => active_a_core_out + ); + active_a_core <= (active_a_core_out(0) = '1'); + + -- port B core active + active_b_core_in_vec(0) <= active_b_core_in; + active_core_port_b : cycloneive_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => active_b_core_in_vec, + clk => clk_b_in, + aclr => wire_gnd, + devclrn => wire_vcc,devpor => wire_vcc, + ena => wire_vcc, + stall => wire_gnd, + q => active_b_core_out + ); + active_b_core <= (active_b_core_out(0) = '1'); + + + + -- ------ A input registers + -- write enable + we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe; + we_a_register : cycloneive_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => we_a_reg_in, + clk => clk_a_wena, + aclr => we_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => we_a_reg_out, + aclrout => we_a_clr + ); + we_a_reg <= we_a_reg_out(0); + -- read enable + re_a_reg_in(0) <= portare; + re_a_register : cycloneive_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => re_a_reg_in, + clk => clk_a_rena, + aclr => re_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => re_a_reg_out, + aclrout => re_a_clr + ); + re_a_reg <= re_a_reg_out(0); + + -- address + addr_a_register : cycloneive_ram_register + GENERIC MAP ( width => port_a_address_width ) + PORT MAP ( + d => portaaddr_int, + clk => clk_a_in, + aclr => addr_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => portaaddrstall_int, + ena => active_a_in, + q => addr_a_reg, + aclrout => addr_a_clr + ); + -- data + datain_a_register : cycloneive_ram_register + GENERIC MAP ( width => port_a_data_width ) + PORT MAP ( + d => portadatain_int, + clk => clk_a_in, + aclr => datain_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => datain_a_reg, + aclrout => datain_a_clr + ); + -- byte enable + byteena_a_register : cycloneive_ram_register + GENERIC MAP ( + width => port_a_byte_enable_mask_width, + preset => '1' + ) + PORT MAP ( + d => portabyteenamasks_int, + clk => clk_a_byteena, + aclr => byteena_a_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_a_in, + q => byteena_a_reg, + aclrout => byteena_a_clr + ); + -- ------ B input registers + + -- read enable + re_b_reg_in(0) <= portbre; + re_b_register : cycloneive_ram_register + GENERIC MAP ( + width => 1 + ) + PORT MAP ( + d => re_b_reg_in, + clk => clk_b_rena, + aclr => re_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => re_b_reg_out, + aclrout => re_b_clr + ); + re_b_reg <= re_b_reg_out(0); + + -- write enable + we_b_reg_in(0) <= portbwe; + we_b_register : cycloneive_ram_register + GENERIC MAP ( + width => 1 + ) + PORT MAP ( + d => we_b_reg_in, + clk => clk_b_wena, + aclr => we_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => we_b_reg_out, + aclrout => we_b_clr + ); + we_b_reg <= we_b_reg_out(0); + + -- address + addr_b_register : cycloneive_ram_register + GENERIC MAP ( width => port_b_address_width ) + PORT MAP ( + d => portbaddr_int, + clk => clk_b_in, + aclr => addr_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => portbaddrstall_int, + ena => active_b_in, + q => addr_b_reg, + aclrout => addr_b_clr + ); + -- data + datain_b_register : cycloneive_ram_register + GENERIC MAP ( width => port_b_data_width ) + PORT MAP ( + d => portbdatain_int, + clk => clk_b_in, + aclr => datain_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => datain_b_reg, + aclrout => datain_b_clr + ); + -- byte enable + byteena_b_register : cycloneive_ram_register + GENERIC MAP ( + width => port_b_byte_enable_mask_width, + preset => '1' + ) + PORT MAP ( + d => portbbyteenamasks_int, + clk => clk_b_byteena, + aclr => byteena_b_clr_in, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => active_b_in, + q => byteena_b_reg, + aclrout => byteena_b_clr + ); + + datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg; + addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg); + + datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE + datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg; + addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg); + + -- Write pulse generation + wpgen_a_clk <= clk_a_in; + wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0'; + + wpgen_a : cycloneive_ram_pulse_generator + PORT MAP ( + clk => wpgen_a_clk, + ena => wpgen_a_clkena, + delaywrite => delay_write_pulse_a, + pulse => write_pulse(primary_port_is_a), + cycle => write_cycle_a + ); + + wpgen_b_clk <= clk_b_in; + wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0'; + + + wpgen_b : cycloneive_ram_pulse_generator + PORT MAP ( + clk => wpgen_b_clk, + ena => wpgen_b_clkena, + delaywrite => delay_write_pulse_b, + pulse => write_pulse(primary_port_is_b), + cycle => write_cycle_b + ); + + -- Read pulse generation + rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0'; + + rpgen_a : cycloneive_ram_pulse_generator + PORT MAP ( + clk => clk_a_in, + ena => rpgen_a_clkena, + cycle => clk_a_core, + pulse => read_pulse(primary_port_is_a) + ); + rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0'; + rpgen_b : cycloneive_ram_pulse_generator + PORT MAP ( + clk => clk_b_in, + ena => rpgen_b_clkena, + cycle => clk_b_core, + pulse => read_pulse(primary_port_is_b) + ); + + -- Read-during-Write pulse generation + rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0'; + rwpgen_a : cycloneive_ram_pulse_generator + PORT MAP ( + clk => clk_a_in, + ena => rwpgen_a_clkena, + pulse => rw_pulse(primary_port_is_a) + ); + + rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0'; + rwpgen_b : cycloneive_ram_pulse_generator + PORT MAP ( + clk => clk_b_in, + ena => rwpgen_b_clkena, + pulse => rw_pulse(primary_port_is_b) + ); + + -- Create internal masks for byte enable processing + mask_create : PROCESS (byteena_a_reg,byteena_b_reg) + VARIABLE mask : mask_rec; + BEGIN + IF (byteena_a_reg'EVENT) THEN + mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a); + IF (primary_port_is_a) THEN + mask_vector.prime <= mask.prime; + ELSE + mask_vector.sec <= mask.sec; + END IF; + END IF; + IF (byteena_b_reg'EVENT) THEN + mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b); + IF (primary_port_is_b) THEN + mask_vector.prime <= mask.prime; + ELSE + mask_vector.sec <= mask.sec; + END IF; + END IF; + END PROCESS mask_create; + + -- (row,col) coordinates + row_sec <= addr_sec_reg / num_cols; + col_sec <= addr_sec_reg mod num_cols; + + + + + mem_rw : PROCESS (init_mem, + write_pulse,read_pulse,read_pulse_feedthru, + rw_pulse, + dataout_a_clr, dataout_b_clr, + mem_invalidate,mem_invalidate_loc,read_latch_invalidate) + -- mem init + TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN; + VARIABLE addr_range_init,row,col,index : INTEGER; + VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0); + VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0); + + VARIABLE mem_val : mem_type; + -- read/write + VARIABLE mem_data_p : mem_row_type; + VARIABLE old_mem_data_p : mem_row_type; + VARIABLE row_prime,col_prime : INTEGER; + VARIABLE access_same_location : BOOLEAN; + VARIABLE read_during_write : rw_type; + BEGIN + -- Latch Clear + IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN + IF (primary_port_is_a) THEN + read_latch.prime <= (OTHERS => (OTHERS => '0')); + dataout_prime <= (OTHERS => '0'); + ELSE + read_latch.sec <= (OTHERS => '0'); + dataout_sec <= (OTHERS => '0'); + END IF; + END IF; + + IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN + IF (primary_port_is_b) THEN + read_latch.prime <= (OTHERS => (OTHERS => '0')); + dataout_prime <= (OTHERS => '0'); + ELSE + read_latch.sec <= (OTHERS => '0'); + dataout_sec <= (OTHERS => '0'); + END IF; + END IF; + read_during_write := (FALSE,FALSE); + -- Memory initialization + IF (init_mem'EVENT) THEN + -- Initialize output latches to 0 + IF (primary_port_is_a) THEN + dataout_prime <= (OTHERS => '0'); + IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF; + ELSE + dataout_sec <= (OTHERS => '0'); + IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF; + END IF; + IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN + mem_val := (OTHERS => (OTHERS => (OTHERS => '0'))); + END IF; + IF (primary_port_is_a) THEN + addr_range_init := port_a_last_address - port_a_first_address + 1; + ELSE + addr_range_init := port_b_last_address - port_b_first_address + 1; + END IF; + IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN + mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0; + mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0); + FOR row IN 0 TO addr_range_init - 1 LOOP + FOR col IN 0 to num_cols - 1 LOOP + index := row * data_width; + mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO + index + col*data_unit_width); + END LOOP; + END LOOP; + END IF; + mem <= mem_val; + END IF; + access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec); + -- Read before Write stage 1 : read data from memory + -- Read before Write stage 2 : send data to output + IF (rw_pulse(primary)'EVENT) THEN + IF (rw_pulse(primary) = '1') THEN + read_latch.prime <= mem(addr_prime_reg); + ELSE + IF (be_mask_write(primary)) THEN + FOR i IN 0 TO data_width - 1 LOOP + IF (mask_vector.prime(normal)(i) = 'X') THEN + row_prime := i / data_unit_width; col_prime := i mod data_unit_width; + dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); + END IF; + END LOOP; + ELSE + FOR i IN 0 TO data_width - 1 LOOP + row_prime := i / data_unit_width; col_prime := i mod data_unit_width; + dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); + END LOOP; + END IF; + END IF; + END IF; + IF (rw_pulse(secondary)'EVENT) THEN + IF (rw_pulse(secondary) = '1') THEN + read_latch.sec <= mem(row_sec)(col_sec); + ELSE + IF (be_mask_write(secondary)) THEN + FOR i IN 0 TO data_unit_width - 1 LOOP + IF (mask_vector.sec(normal)(i) = 'X') THEN + dataout_sec(i) <= read_latch.sec(i); + END IF; + END LOOP; + ELSE + dataout_sec <= read_latch.sec; + END IF; + END IF; + END IF; + + -- Write stage 1 : X to buffer + -- Write stage 2 : actual data to memory + IF (write_pulse(primary)'EVENT) THEN + IF (write_pulse(primary) = '1') THEN + old_mem_data_p := mem(addr_prime_reg); + mem_data_p := mem(addr_prime_reg); + FOR i IN 0 TO num_cols - 1 LOOP + mem_data_p(i) := mem_data_p(i) XOR + mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width); + END LOOP; + read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1'); + IF (read_during_write(secondary)) THEN + read_latch.sec <= old_mem_data_p(col_sec); + ELSE + mem_data <= mem_data_p; + END IF; + ELSIF (clear_asserted_during_write(primary) /= '1') THEN + FOR i IN 0 TO data_width - 1 LOOP + IF (mask_vector.prime(normal)(i) = '0') THEN + mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i); + ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN + mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X'; + END IF; + END LOOP; + END IF; + END IF; + + IF (write_pulse(secondary)'EVENT) THEN + IF (write_pulse(secondary) = '1') THEN + read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1'); + IF (read_during_write(primary)) THEN + read_latch.prime <= mem(addr_prime_reg); + read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse); + ELSE + mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse); + END IF; + + IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN + mask_vector_common <= + mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND + mask_vector.sec(inverse); + dual_write <= TRUE; + END IF; + ELSIF (clear_asserted_during_write(secondary) /= '1') THEN + FOR i IN 0 TO data_unit_width - 1 LOOP + IF (mask_vector.sec(normal)(i) = '0') THEN + mem(row_sec)(col_sec)(i) <= datain_sec_reg(i); + ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN + mem(row_sec)(col_sec)(i) <= 'X'; + END IF; + END LOOP; + END IF; + END IF; + -- Simultaneous write + IF (dual_write AND write_pulse = "00") THEN + mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common; + dual_write <= FALSE; + END IF; + -- Read stage 1 : read data + -- Read stage 2 : send data to output + IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN + IF (read_pulse(primary) = '1') THEN + read_latch.prime <= mem(addr_prime_reg); + IF (access_same_location AND write_pulse(secondary) = '1') THEN + read_latch.prime(col_sec) <= mem_unit_data; + END IF; + ELSE + FOR i IN 0 TO data_width - 1 LOOP + row_prime := i / data_unit_width; col_prime := i mod data_unit_width; + dataout_prime(i) <= read_latch.prime(row_prime)(col_prime); + END LOOP; + END IF; + END IF; + + IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN + IF (read_pulse(secondary) = '1') THEN + IF (access_same_location AND write_pulse(primary) = '1') THEN + read_latch.sec <= mem_data(col_sec); + ELSE + read_latch.sec <= mem(row_sec)(col_sec); + END IF; + ELSE + dataout_sec <= read_latch.sec; + END IF; + END IF; + -- Same port feed thru + IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN + IF (be_mask_write(primary)) THEN + FOR i IN 0 TO data_width - 1 LOOP + IF (mask_vector.prime(normal)(i) = '0') THEN + dataout_prime(i) <= datain_prime_reg(i); + END IF; + END LOOP; + ELSE + dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal); + END IF; + END IF; + + IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN + IF (be_mask_write(secondary)) THEN + FOR i IN 0 TO data_unit_width - 1 LOOP + IF (mask_vector.sec(normal)(i) = '0') THEN + dataout_sec(i) <= datain_sec_reg(i); + END IF; + END LOOP; + ELSE + dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal); + END IF; + END IF; + -- Async clear + IF (mem_invalidate'EVENT) THEN + IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN + mem <= mem_x; + END IF; + END IF; + IF (mem_invalidate_loc'EVENT) THEN + IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF; + IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF; + END IF; + IF (read_latch_invalidate'EVENT) THEN + IF (read_latch_invalidate(primary)) THEN + read_latch.prime <= row_x; + END IF; + IF (read_latch_invalidate(secondary)) THEN + read_latch.sec <= col_x; + END IF; + END IF; + + END PROCESS mem_rw; + + -- Same port feed through + ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0'; + ftpgen_a : cycloneive_ram_pulse_generator + PORT MAP ( + clk => clk_a_in, + ena => ftpgen_a_clkena, + pulse => read_pulse_feedthru(primary_port_is_a) + ); + ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0'; + + ftpgen_b : cycloneive_ram_pulse_generator + PORT MAP ( + clk => clk_b_in, + ena => ftpgen_b_clkena, + pulse => read_pulse_feedthru(primary_port_is_b) + ); + + + + + + -- Asynch clear events + clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr) + BEGIN + IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN + clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a); + IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN + mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN + read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN + clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a); + IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN + mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + END PROCESS clear_a; + + clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr) + BEGIN + IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN + clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b); + IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN + mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN + read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN + clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b); + IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN + mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns; + END IF; + END IF; + END PROCESS clear_b; + + + -- Clear mux registers (Latch Clear) + -- Port A output register clear + dataout_a_clr_reg_latch_in(0) <= dataout_a_clr; + aclr_a_mux_register : cycloneive_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => dataout_a_clr_reg_latch_in, + clk => clk_a_core, + aclr => wire_gnd, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => wire_vcc, + q => dataout_a_clr_reg_latch_out + ); + dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0); + + -- Port B output register clear + dataout_b_clr_reg_latch_in(0) <= dataout_b_clr; + aclr_b_mux_register : cycloneive_ram_register + GENERIC MAP ( width => 1 ) + PORT MAP ( + d => dataout_b_clr_reg_latch_in, + clk => clk_b_core, + aclr => wire_gnd, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => wire_vcc, + q => dataout_b_clr_reg_latch_out + ); + dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0); + + -- ------ Output registers + + + clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0; + clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1; + clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1; + clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1; + + dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec; + dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE + dataout_prime WHEN primary_port_is_b ELSE dataout_sec; + + dataout_a_register : cycloneive_ram_register + GENERIC MAP ( width => port_a_data_width ) + PORT MAP ( + d => dataout_a, + clk => clk_a_out, + aclr => dataout_a_clr_reg, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => clkena_a_out, + q => dataout_a_reg + ); + + dataout_b_register : cycloneive_ram_register + GENERIC MAP ( width => port_b_data_width ) + PORT MAP ( + d => dataout_b, + clk => clk_b_out, + aclr => dataout_b_clr_reg, + devclrn => devclrn, + devpor => devpor, + stall => wire_gnd, + ena => clkena_b_out, + q => dataout_b_reg + ); + + portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a; + portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b; + + +END block_arch; + + +----------------------------------------------------------------------- +-- +-- Module Name : cycloneive_mac_data_reg +-- +-- Description : Simulation model for the data input register of +-- Cyclone II MAC_MULT +-- +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE work.cycloneive_atom_pack.all; + +ENTITY cycloneive_mac_data_reg IS + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + data_width : integer := 18 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + data : IN std_logic_vector(17 DOWNTO 0); + ena : IN std_logic; + aclr : IN std_logic; + -- OUTPUT PORTS + dataout : OUT std_logic_vector(17 DOWNTO 0) + ); +END cycloneive_mac_data_reg; + +ARCHITECTURE vital_cycloneive_mac_data_reg OF cycloneive_mac_data_reg IS + + SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL aclr_ipd : std_logic; + SIGNAL clk_ipd : std_logic; + SIGNAL ena_ipd : std_logic; + SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + +BEGIN + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + g1 : for i in data'range generate + VitalWireDelay (data_ipd(i), data(i), tipd_data(i)); + end generate; + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + + process (clk_ipd, aclr_ipd, data_ipd) + begin + if (aclr_ipd = '1') then + dataout_tmp <= (OTHERS => '0'); + elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then + dataout_tmp <= data_ipd; + end if; + + end process; + + sh: block + begin + g0 : for i in data'range generate + process (data_ipd(i),clk_ipd,ena_ipd) + variable Tviol_data_clk : std_ulogic := '0'; + variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_data_clk, + TimingData => TimingData_data_clk, + TestSignal => data_ipd(i), + TestSignalName => "DATA(i)", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_data_clk_noedge_posedge(i), + SetupLow => tsetup_data_clk_noedge_posedge(i), + HoldHigh => thold_data_clk_noedge_posedge(i), + HoldLow => thold_data_clk_noedge_posedge(i), + CheckEnabled => TO_X01((aclr) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena_ipd, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01(aclr) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + END PROCESS; + end generate g0; + end block; + + ---------------------- + -- Path Delay Section + ---------------------- + PathDelay : block + begin + g1 : for i in dataout_tmp'range generate + VITALtiming : process (dataout_tmp(i)) + variable dataout_VitalGlitchData : VitalGlitchDataType; + begin + VitalPathDelay01 (OutSignal => dataout(i), + OutSignalName => "DATAOUT", + OutTemp => dataout_tmp(i), + Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE), + 1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn); + end process; + end generate; + end block; + +END vital_cycloneive_mac_data_reg; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneive_mac_sign_reg +-- +-- Description : Simulation model for the sign input register of +-- Cyclone II MAC_MULT +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE work.cycloneive_atom_pack.all; + +ENTITY cycloneive_mac_sign_reg IS + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + d : IN std_logic; + ena : IN std_logic; + aclr : IN std_logic; + + -- OUTPUT PORTS + q : OUT std_logic + ); +END cycloneive_mac_sign_reg; + +ARCHITECTURE cycloneive_mac_sign_reg OF cycloneive_mac_sign_reg IS + + signal d_ipd : std_logic; + signal clk_ipd : std_logic; + signal aclr_ipd : std_logic; + signal ena_ipd : std_logic; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + VITALtiming : process (clk_ipd, aclr_ipd) + variable Tviol_d_clk : std_ulogic := '0'; + variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + variable q_reg : std_logic := '0'; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_clk, + TimingData => TimingData_d_clk, + TestSignal => d, + TestSignalName => "D", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => TO_X01((aclr) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/SIGN_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01(aclr) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/SIGN_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + if (aclr_ipd = '1') then + q_reg := '0'; + elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then + q_reg := d_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => q_reg, + Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE), + 1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + end process; +END cycloneive_mac_sign_reg; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneive_mac_mult_internal +-- +-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; +USE work.cycloneive_atom_pack.all; + +ENTITY cycloneive_mac_mult_internal IS + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_datab : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_signa : VitalDelayType01 := DefPropDelay01; + tipd_signb : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + dataa_width : integer := 18; + datab_width : integer := 18 + ); + PORT ( + dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) + ); +END cycloneive_mac_mult_internal; + +ARCHITECTURE vital_cycloneive_mac_mult_internal OF cycloneive_mac_mult_internal IS + + -- Internal variables + SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL signa_ipd : std_logic; + SIGNAL signb_ipd : std_logic; + + -- padding with 1's for input negation + SIGNAL reg_aclr : std_logic; + SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0'); + +BEGIN + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + g1 : for i in dataa'range generate + VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); + end generate; + g2 : for i in datab'range generate + VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i)); + end generate; + + VitalWireDelay (signa_ipd, signa, tipd_signa); + VitalWireDelay (signb_ipd, signb, tipd_signb); + end block; + + + VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd) + begin + if((signa_ipd = '0') and (signb_ipd = '1')) then + dataout_tmp <= + unsigned(dataa_ipd(dataa_width-1 downto 0)) * + signed(datab_ipd(datab_width-1 downto 0)); + elsif((signa_ipd = '1') and (signb_ipd = '0')) then + dataout_tmp <= + signed(dataa_ipd(dataa_width-1 downto 0)) * + unsigned(datab_ipd(datab_width-1 downto 0)); + elsif((signa_ipd = '1') and (signb_ipd = '1')) then + dataout_tmp(dataout'range) <= + signed(dataa_ipd(dataa_width-1 downto 0)) * + signed(datab_ipd(datab_width-1 downto 0)); + else --((signa_ipd = '0') and (signb_ipd = '0')) then + dataout_tmp(dataout'range) <= + unsigned(dataa_ipd(dataa_width-1 downto 0)) * + unsigned(datab_ipd(datab_width-1 downto 0)); + end if; + end process; + + ---------------------- + -- Path Delay Section + ---------------------- + PathDelay : block + begin + g1 : for i in dataout'range generate + VITALtiming : process (dataout_tmp(i)) + variable dataout_VitalGlitchData : VitalGlitchDataType; + begin + VitalPathDelay01 (OutSignal => dataout(i), + OutSignalName => "dataout", + OutTemp => dataout_tmp(i), + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE), + 1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE), + 2 => (signa'last_event, tpd_signa_dataout(i), TRUE), + 3 => (signb'last_event, tpd_signb_dataout(i), TRUE)), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + MsgOn => FALSE, + XOn => TRUE ); + end process; + end generate; + end block; + +END vital_cycloneive_mac_mult_internal; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneive_mac_mult +-- +-- Description : Cyclone II MAC_MULT VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_unsigned.all; +USE work.cycloneive_atom_pack.all; +USE work.cycloneive_mac_data_reg; +USE work.cycloneive_mac_sign_reg; +USE work.cycloneive_mac_mult_internal; + +ENTITY cycloneive_mac_mult IS + GENERIC ( + dataa_width : integer := 18; + datab_width : integer := 18; + dataa_clock : string := "none"; + datab_clock : string := "none"; + signa_clock : string := "none"; + signb_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + lpm_hint : string := "true"; + lpm_type : string := "cycloneive_mac_mult" + ); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '0'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneive_mac_mult; + +ARCHITECTURE vital_cycloneive_mac_mult OF cycloneive_mac_mult IS + + COMPONENT cycloneive_mac_data_reg + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01); + data_width : integer := 18 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + data : IN std_logic_vector(17 DOWNTO 0); + ena : IN std_logic; + aclr : IN std_logic; + -- OUTPUT PORTS + dataout : OUT std_logic_vector(17 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT cycloneive_mac_sign_reg + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + -- INPUT PORTS + clk : IN std_logic; + d : IN std_logic; + ena : IN std_logic; + aclr : IN std_logic; + + -- OUTPUT PORTS + q : OUT std_logic + ); + END COMPONENT; + + COMPONENT cycloneive_mac_mult_internal + GENERIC ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_datab : VitalDelayArrayType01(17 downto 0) + := (OTHERS => DefPropDelay01); + tipd_signa : VitalDelayType01 := DefPropDelay01; + tipd_signb : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + dataa_width : integer := 18; + datab_width : integer := 18 + ); + PORT ( + dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) + ); + END COMPONENT; + + -- Internal variables + SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0); + SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input + SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input + SIGNAL isigna_reg : std_logic; -- optional register for signa input + SIGNAL isignb_reg : std_logic; -- optional register for signb input + SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input + SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input + SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input + SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input + -- padding with 1's for input negation + SIGNAL reg_aclr : std_logic; + SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0'); + +BEGIN + + --------------------- + -- INPUT PATH DELAYs + --------------------- + + reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ; + + -- padding input data to full bus width + dataa_ipd(dataa_width-1 downto 0) <= dataa; + datab_ipd(datab_width-1 downto 0) <= datab; + + -- Optional input registers for dataa,b and signa,b + dataa_reg : cycloneive_mac_data_reg + GENERIC MAP ( + data_width => dataa_width) + PORT MAP ( + clk => clk, + data => dataa_ipd, + ena => ena, + aclr => reg_aclr, + dataout => idataa_reg); + + datab_reg : cycloneive_mac_data_reg + GENERIC MAP ( + data_width => datab_width) + PORT MAP ( + clk => clk, + data => datab_ipd, + ena => ena, + aclr => reg_aclr, + dataout => idatab_reg); + + signa_reg : cycloneive_mac_sign_reg + PORT MAP ( + clk => clk, + d => signa, + ena => ena, + aclr => reg_aclr, + q => isigna_reg); + + signb_reg : cycloneive_mac_sign_reg + PORT MAP ( + clk => clk, + d => signb, + ena => ena, + aclr => reg_aclr, + q => isignb_reg); + + idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg; + idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg; + isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg; + isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg; + + mac_multiply : cycloneive_mac_mult_internal + GENERIC MAP ( + dataa_width => dataa_width, + datab_width => datab_width + ) + PORT MAP ( + dataa => idataa_int, + datab => idatab_int, + signa => isigna_int, + signb => isignb_int, + dataout => dataout + ); +END vital_cycloneive_mac_mult; + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneive_mac_out +-- +-- Description : Cyclone II MAC_OUT VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.VITAL_Primitives.all; +USE IEEE.VITAL_Timing.all; +USE IEEE.std_logic_1164.all; +USE work.cycloneive_atom_pack.all; + +ENTITY cycloneive_mac_out IS + GENERIC ( + dataa_width : integer := 1; + output_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(35 downto 0) + := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + lpm_hint : string := "true"; + lpm_type : string := "cycloneive_mac_out"); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '1'; + dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneive_mac_out; + +ARCHITECTURE vital_cycloneive_mac_out OF cycloneive_mac_out IS + + -- internal variables + SIGNAL dataa_ipd : std_logic_vector(dataa'range); + SIGNAL clk_ipd : std_logic; + SIGNAL aclr_ipd : std_logic; + SIGNAL ena_ipd : std_logic; + + -- optional register + SIGNAL use_reg : std_logic; + + SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0'); + +BEGIN + + --------------------- + -- PATH DELAYs + --------------------- + WireDelay : block + begin + g1 : for i in dataa'range generate + VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i)); + VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i)) + variable dataout_VitalGlitchData : VitalGlitchDataType; + begin + VitalPathDelay01 ( + OutSignal => dataout(i), + OutSignalName => "DATAOUT", + OutTemp => dataout_tmp(i), + Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'), + 1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'), + 2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + end process; + end generate; + + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (aclr_ipd, aclr, tipd_aclr); + VitalWireDelay (ena_ipd, ena, tipd_ena); + + end block; + + use_reg <= '1' WHEN (output_clock /= "none") ELSE '0'; + + sh: block + begin + g0 : for i in dataa'range generate + VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i)) + variable Tviol_dataa_clk : std_ulogic := '0'; + variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_dataa_clk, + TimingData => TimingData_dataa_clk, + TestSignal => dataa(i), + TestSignalName => "D", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_dataa_clk_noedge_posedge(i), + SetupLow => tsetup_dataa_clk_noedge_posedge(i), + HoldHigh => thold_dataa_clk_noedge_posedge(i), + HoldLow => thold_dataa_clk_noedge_posedge(i), + CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01((aclr) OR + (NOT use_reg)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/MAC_DATA_REG", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + END PROCESS; + end generate g0; + end block; + + process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd) + begin + if (use_reg = '0') then + dataout_tmp <= dataa_ipd; + else + if (aclr_ipd = '1') then + dataout_tmp <= (OTHERS => '0'); + elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then + dataout_tmp <= dataa_ipd; + end if; + end if; + + end process; + +END vital_cycloneive_mac_out; + + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_io_ibuf +-- +-- Description : Cycloneive IO Ibuf VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +ENTITY cycloneive_io_ibuf IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_ibar : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_ibar_o : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + differential_mode : string := "false"; + bus_hold : string := "false"; + simulate_z_as : string := "Z"; + lpm_type : string := "cycloneive_io_ibuf" + ); + PORT ( + i : IN std_logic := '0'; + ibar : IN std_logic := '0'; + o : OUT std_logic + ); +END cycloneive_io_ibuf; + +ARCHITECTURE arch OF cycloneive_io_ibuf IS + SIGNAL i_ipd : std_logic := '0'; + SIGNAL ibar_ipd : std_logic := '0'; + SIGNAL o_tmp : std_logic; + SIGNAL out_tmp : std_logic; + SIGNAL prev_value : std_logic := '0'; +BEGIN + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (ibar_ipd, ibar, tipd_ibar); + end block; + + PROCESS(i_ipd, ibar_ipd) + BEGIN + IF (differential_mode = "false") THEN + IF (i_ipd = '1') THEN + o_tmp <= '1'; + prev_value <= '1'; + ELSIF (i_ipd = '0') THEN + o_tmp <= '0'; + prev_value <= '0'; + ELSE + o_tmp <= i_ipd; + END IF; + ELSE + IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then + o_tmp <= '0'; + ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then + o_tmp <= '1'; + ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then + o_tmp <= 'X'; + ELSE + o_tmp <= 'X'; + END IF; + END IF; + END PROCESS; + + out_tmp <= prev_value when (bus_hold = "true") else + 'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else + 'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else + '1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else + '0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else + o_tmp; + ---------------------- + -- Path Delay Section + ---------------------- + PROCESS( out_tmp) + variable output_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => out_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), + 1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)), + GlitchData => output_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; + END arch; + + + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_io_obuf +-- +-- Description : Cycloneive IO Obuf VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +ENTITY cycloneive_io_obuf IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_oe_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tpd_oe_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + open_drain_output : string := "false"; + bus_hold : string := "false"; + lpm_type : string := "cycloneive_io_obuf" + ); + PORT ( + i : IN std_logic := '0'; + oe : IN std_logic := '1'; + seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + devoe : IN std_logic := '1'; + o : OUT std_logic; + obar : OUT std_logic + ); +END cycloneive_io_obuf; + +ARCHITECTURE arch OF cycloneive_io_obuf IS + --INTERNAL Signals + SIGNAL i_ipd : std_logic := '0'; + SIGNAL oe_ipd : std_logic := '0'; + SIGNAL out_tmp : std_logic := 'Z'; + SIGNAL out_tmp_bar : std_logic; + SIGNAL prev_value : std_logic := '0'; + SIGNAL o_tmp : std_logic; + SIGNAL obar_tmp : std_logic; + SIGNAL o_tmp1 : std_logic; + SIGNAL obar_tmp1 : std_logic; + SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0'); + +BEGIN + +WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (oe_ipd, oe, tipd_oe); + g1 :for i in seriesterminationcontrol'range generate + VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i)); + end generate; + + + end block; + PROCESS( i_ipd, oe_ipd) + BEGIN + IF (oe_ipd = '1') THEN + IF (open_drain_output = "true") THEN + IF (i_ipd = '0') THEN + out_tmp <= '0'; + out_tmp_bar <= '1'; + prev_value <= '0'; + ELSE + out_tmp <= 'Z'; + out_tmp_bar <= 'Z'; + END IF; + ELSE + IF (i_ipd = '0') THEN + out_tmp <= '0'; + out_tmp_bar <= '1'; + prev_value <= '0'; + ELSE + IF (i_ipd = '1') THEN + out_tmp <= '1'; + out_tmp_bar <= '0'; + prev_value <= '1'; + ELSE + out_tmp <= i_ipd; + out_tmp_bar <= i_ipd; + END IF; + END IF; + END IF; + ELSE + IF (oe_ipd = '0') THEN + out_tmp <= 'Z'; + out_tmp_bar <= 'Z'; + ELSE + out_tmp <= 'X'; + out_tmp_bar <= 'X'; + END IF; + END IF; + END PROCESS; + o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp; + obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar; + o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z'; + obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z'; + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( o_tmp,obar_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable obar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => o_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), + 1 => (oe_ipd'last_event, tpd_oe_o, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => obar, + OutSignalName => "obar", + OutTemp => obar_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE), + 1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)), + GlitchData => obar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; +END arch; + +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_ddio_oe +-- +-- Description : Cycloneive DDIO_OE VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +LIBRARY altera; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use altera.all; +use work.cycloneive_atom_pack.all; + + + +ENTITY cycloneive_ddio_oe IS + generic( + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + lpm_type : string := "cycloneive_ddio_oe" + ); + + PORT ( + oe : IN std_logic := '1'; + clk : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneive_ddio_oe; + +ARCHITECTURE arch OF cycloneive_ddio_oe IS + +component cycloneive_mux21 + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01 + ); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic + ); +end component; + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +end component; + + --Internal Signals + SIGNAL oe_ipd : std_logic := '0'; + SIGNAL clk_ipd : std_logic := '0'; + SIGNAL ena_ipd : std_logic := '0'; + SIGNAL areset_ipd : std_logic := '0'; + SIGNAL sreset_ipd : std_logic := '0'; + SIGNAL ddioreg_aclr : std_logic; + SIGNAL ddioreg_prn : std_logic; + SIGNAL ddioreg_adatasdata : std_logic; + SIGNAL ddioreg_sclr : std_logic; + SIGNAL ddioreg_sload : std_logic; + SIGNAL dfflo_tmp : std_logic; + SIGNAL dffhi_tmp : std_logic; + signal nclk : std_logic; + signal dataout_tmp : std_logic; + + +BEGIN + + WireDelay : block + begin + VitalWireDelay (oe_ipd, oe, tipd_oe); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (sreset_ipd, sreset, tipd_sreset); + end block; + + nclk <= NOT clk_ipd; + PROCESS + BEGIN + WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; + IF (async_mode = "clear") THEN + ddioreg_aclr <= NOT areset_ipd; + ddioreg_prn <= '1'; + ELSIF (async_mode = "preset") THEN + ddioreg_aclr <= '1'; + ddioreg_prn <= NOT areset_ipd; + ELSE + ddioreg_aclr <= '1'; + ddioreg_prn <= '1'; + END IF; + + IF (sync_mode = "clear") THEN + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= sreset_ipd; + ddioreg_sload <= '0'; + ELSIF (sync_mode = "preset") THEN + ddioreg_adatasdata <= '1'; + ddioreg_sclr <= '0'; + ddioreg_sload <= sreset_ipd; + ELSE + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= '0'; + ddioreg_sload <= '0'; + END IF; + END PROCESS; + + ddioreg_hi : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => oe_ipd, + clk => clk_ipd, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dffhi_tmp, + devpor => devpor, + devclrn => devclrn + ); + + + --DDIO Low Register + ddioreg_lo : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => dffhi_tmp, + clk => nclk, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dfflo_tmp, + devpor => devpor, + devclrn => devclrn + ); + + --registered output + or_gate : cycloneive_mux21 + port map ( + A => dffhi_tmp, + B => dfflo_tmp, + S => dfflo_tmp, + MO => dataout + ); + + dfflo <= dfflo_tmp ; + dffhi <= dffhi_tmp ; + + +END arch; +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_latch +-- +-- Description : Cyclone III latch VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +Library ieee; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; +entity cycloneive_latch is + generic( + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneive_latch"; + tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tpd_d_q : VitalDelayType01 := DefPropDelay01; + tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clr : VitalDelayType01 := DefPropDelay01; + tipd_pre : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port( + d : in std_logic := '0'; + ena : in std_logic := '1'; + clr : in std_logic := '1'; + pre : in std_logic := '1'; + q : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneive_latch : entity is TRUE; +end cycloneive_latch; + + +architecture vital_latch of cycloneive_latch is + attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE; + signal d_ipd : std_logic; + signal d_dly : std_logic; + signal clr_ipd : std_logic; + signal pre_ipd : std_logic; + signal ena_ipd : std_logic; + +begin + + d_dly <= d_ipd; + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (clr_ipd, clr, tipd_clr); + VitalWireDelay (pre_ipd, pre, tipd_pre); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd) + + variable Tviol_d_ena : std_ulogic := '0'; + variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + + variable iq : std_logic := '0'; + variable idata: std_logic := '0'; + + -- variables for 'X' generation + variable violation : std_logic := '0'; + + begin + + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_ena, + TimingData => TimingData_d_ena, + TestSignal => d_ipd, + TestSignalName => "DATAIN", + RefSignal => ena_ipd, + RefSignalName => "ENA", + SetupHigh => tsetup_d_ena_noedge_negedge, + SetupLow => tsetup_d_ena_noedge_negedge, + HoldHigh => thold_d_ena_noedge_negedge, + HoldLow => thold_d_ena_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + HeaderMsg => InstancePath & "/cycloneive_latch", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + + + violation := Tviol_d_ena; + + + if ( (clr_ipd = '0')) then + iq := '0'; + elsif (pre_ipd = '0') then + iq := '1'; + elsif (violation = 'X' and x_on_violation = "on") then + iq := 'X'; + elsif (ena_ipd = '1') then + iq := d_dly; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => iq, + Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE), + 1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE), + 2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end vital_latch; +--------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_ddio_out +-- +-- Description : Cycloneive DDIO_OUT VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +LIBRARY altera; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use altera.all; +use work.cycloneive_atom_pack.all; + +ENTITY cycloneive_ddio_out IS + generic( + tipd_datainlo : VitalDelayType01 := DefPropDelay01; + tipd_datainhi : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkhi : VitalDelayType01 := DefPropDelay01; + tipd_clklo : VitalDelayType01 := DefPropDelay01; + tipd_muxsel : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + use_new_clocking_model : string := "false"; + lpm_type : string := "cycloneive_ddio_out" + ); + PORT ( + datainlo : IN std_logic := '0'; + datainhi : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkhi : IN std_logic := '0'; + clklo : IN std_logic := '0'; + muxsel : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic ; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cycloneive_ddio_out; + +ARCHITECTURE arch OF cycloneive_ddio_out IS + +component cycloneive_mux21 + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01 + ); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic + ); +end component; + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +end component; + +component cycloneive_latch + generic( + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneive_latch"; + tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tpd_d_q : VitalDelayType01 := DefPropDelay01; + tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clr : VitalDelayType01 := DefPropDelay01; + tipd_pre : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port( + d : in std_logic := '0'; + ena : in std_logic := '1'; + clr : in std_logic := '1'; + pre : in std_logic := '1'; + q : out std_logic + ); +end component; + +component cycloneive_routing_wire is + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); + +end component; + --Internal Signals + SIGNAL datainlo_ipd : std_logic := '0'; + SIGNAL datainhi_ipd : std_logic := '0'; + SIGNAL clk_ipd : std_logic := '0'; + SIGNAL clkhi_ipd : std_logic := '0'; + SIGNAL clklo_ipd : std_logic := '0'; + SIGNAL muxsel_ipd : std_logic := '0'; + SIGNAL ena_ipd : std_logic := '0'; + SIGNAL areset_ipd : std_logic := '0'; + SIGNAL sreset_ipd : std_logic := '0'; + SIGNAL ddioreg_aclr : std_logic; + SIGNAL ddioreg_prn : std_logic; + SIGNAL ddioreg_adatasdata : std_logic; + SIGNAL ddioreg_sclr : std_logic; + SIGNAL ddioreg_sload : std_logic; + SIGNAL dfflo_tmp : std_logic; + SIGNAL dffhi_tmp : std_logic; + SIGNAL dataout_tmp : std_logic; + Signal mux_sel : std_logic; + Signal mux_hi : std_logic; + Signal sel_mux_hi_in : std_logic; + signal clk1 : std_logic; + signal clk_hi : std_logic; + signal clk_lo : std_logic; + + signal muxsel1 : std_logic; + signal muxsel2: std_logic; + signal clk2 : std_logic; + signal muxsel_tmp: std_logic; + signal sel_mux_lo_in : std_logic; + signal datainlo_tmp : std_logic; + signal datainhi_tmp : std_logic; + signal dffhi_tmp1 : std_logic; + signal bdataout : std_logic; + signal hrb_sel: std_logic; + +BEGIN + +WireDelay : block + begin + VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo); + VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi); + VitalWireDelay (clklo_ipd, clklo, tipd_clklo); + VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (sreset_ipd, sreset, tipd_sreset); + end block; + PROCESS + BEGIN + WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; + IF (async_mode = "clear") THEN + ddioreg_aclr <= NOT areset_ipd; + ddioreg_prn <= '1'; + ELSIF (async_mode = "preset") THEN + ddioreg_aclr <= '1'; + ddioreg_prn <= NOT areset_ipd; + ELSE + ddioreg_aclr <= '1'; + ddioreg_prn <= '1'; + END IF; + + IF (sync_mode = "clear") THEN + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= sreset_ipd; + ddioreg_sload <= '0'; + ELSIF (sync_mode = "preset") THEN + ddioreg_adatasdata <= '1'; + ddioreg_sclr <= '0'; + ddioreg_sload <= sreset_ipd; + ELSE + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= '0'; + ddioreg_sload <= '0'; + END IF; + END PROCESS; + + process(clk_ipd) + begin + clk1 <= clk_ipd; + end process; + + process(muxsel_ipd) + begin + muxsel1 <= muxsel_ipd; + end process; + + + process(dffhi_tmp) + begin + dffhi_tmp1 <= dffhi_tmp; + end process; + + + --DDIO HIGH Register + clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd); + datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi; + + ddioreg_hi : cycloneive_latch + PORT MAP ( + d=> datainhi_tmp, + ena => clk_hi, + pre => ddioreg_prn, + clr => ddioreg_aclr, + q => dffhi_tmp + ); + + --DDIO Low Register + clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd; + datainlo_tmp <= datainlo; + ddioreg_lo : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => datainlo_tmp, + clk => clk_lo, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dfflo_tmp, + devpor => devpor, + devclrn => devclrn + ); + + + muxsel2 <= muxsel1; + clk2 <= clk1; + mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2; + muxsel_tmp <= NOT mux_sel; + sel_mux_lo_in <= dfflo_tmp; + sel_mux_hi_in <= dffhi_tmp1; + + + +wire_delay : cycloneive_routing_wire + port map ( + datain => bdataout, + dataout => dataout + ); + + sel_mux : cycloneive_mux21 + port map ( + A => sel_mux_hi_in, + B => sel_mux_lo_in, + S => muxsel_tmp, + MO => bdataout + ); + + dfflo <= dfflo_tmp; + dffhi <= dffhi_tmp; + +END arch; +---------------------------------------------------------------------------------- +--Module Name: cycloneive_pseudo_diff_out -- +--Description: Simulation model for Cycloneive Pseudo Differential -- +-- Output Buffer -- +---------------------------------------------------------------------------------- + + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +ENTITY cycloneive_pseudo_diff_out IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + lpm_type : string := "cycloneive_pseudo_diff_out" + ); + PORT ( + i : IN std_logic := '0'; + o : OUT std_logic; + obar : OUT std_logic + ); +END cycloneive_pseudo_diff_out; + +ARCHITECTURE arch OF cycloneive_pseudo_diff_out IS + SIGNAL i_ipd : std_logic ; + SIGNAL o_tmp : std_logic ; + SIGNAL obar_tmp : std_logic; + +BEGIN + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + + PROCESS( i_ipd) + BEGIN + IF (i_ipd = '0') THEN + o_tmp <= '0'; + obar_tmp <= '1'; + ELSE + IF (i_ipd = '1') THEN + o_tmp <= '1'; + obar_tmp <= '0'; + ELSE + o_tmp <= i_ipd; + obar_tmp <= i_ipd; + END IF; + END IF; + END PROCESS; + + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( o_tmp,obar_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable obar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => o_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => obar, + OutSignalName => "obar", + OutTemp => obar_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)), + GlitchData => obar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; +END arch; +---------------------------------------------------------------------------- +-- Module Name : cycloneive_io_pad +-- Description : Simulation model for cycloneive IO pad +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +ENTITY cycloneive_io_pad IS + GENERIC ( + lpm_type : string := "cycloneive_io_pad"); + PORT ( + --INPUT PORTS + + padin : IN std_logic := '0'; -- Input Pad + --OUTPUT PORTS + + padout : OUT std_logic); -- Output Pad +END cycloneive_io_pad; + +ARCHITECTURE arch OF cycloneive_io_pad IS + +BEGIN + padout <= padin; +END arch; +library IEEE; +use IEEE.std_logic_1164.all; + +entity cycloneive_asmiblock is + generic ( + lpm_type : string := "cycloneive_asmiblock"; + enable_sim : string := "false" + ); + port ( + dclkin : in std_logic; + scein : in std_logic; + oe : in std_logic; + sdoin : in std_logic; + data0out: out std_logic + ); +end entity cycloneive_asmiblock; + +architecture behavior of cycloneive_asmiblock is + +-- component asmi_sim_model is port(dclk: in std_logic; ncso: in std_logic; asdo: in std_logic; data0: out std_logic); end component; + +signal dclk_wire, ncs, data0 : std_logic; + +begin + +process(dclkin, scein, oe, data0) +begin + if (oe = '0') then + dclk_wire <= dclkin; + ncs <= scein; + data0 <= sdoin; + elsif (oe = '1' ) then + dclk_wire <= 'Z'; + ncs <= 'Z'; + data0 <= 'Z'; + else + dclk_wire <= 'X'; + ncs <= 'X'; + data0 <= 'X'; + end if; +end process; + +----------------------------------------------------- +-- Instantiate module to represent Active Serial pins +----------------------------------------------------- +-- sim_model_inst : asmi_sim_model port map(dclk => dclk_wire, ncso => ncs, asdo => data0, data0 => data0out); + +end architecture; + +--///////////////////////////////////////////////////////////////////////////// +-- +-- Entity Name : cycloneive_ena_reg +-- +-- Description : Simulation model for a simple DFF. +-- This is used for the gated clock generation +-- Powers upto 1. +-- +--///////////////////////////////////////////////////////////////////////////// + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +ENTITY cycloneive_ena_reg is + generic ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneive_ena_reg : entity is TRUE; +end cycloneive_ena_reg; + +ARCHITECTURE behave of cycloneive_ena_reg is + attribute VITAL_LEVEL0 of behave : architecture is TRUE; + signal d_ipd : std_logic; + signal clk_ipd : std_logic; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (clk_ipd, clk, tipd_clk); + end block; + + VITALtiming : process (clk_ipd, prn, clrn) + variable Tviol_d_clk : std_ulogic := '0'; + variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + variable q_reg : std_logic := '1'; + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_clk, + TimingData => TimingData_d_clk, + TestSignal => d, + TestSignalName => "D", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => TO_X01((clrn) OR + (NOT ena)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/cycloneive_ena_reg", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + if (prn = '0') then + q_reg := '1'; + elsif (clrn = '0') then + q_reg := '0'; + elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then + q_reg := d_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => q_reg, + Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; + + +--///////////////////////////////////////////////////////////////////////////// +-- +-- VHDL Simulation Model for Cyclone III CLKCTRL Atom +-- +--///////////////////////////////////////////////////////////////////////////// + +-- +-- +-- CYCLONEIVE_CLKCTRL Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; +use work.cycloneive_ena_reg; + +entity cycloneive_clkctrl is + generic ( + clock_type : STRING := "Auto"; + lpm_type : STRING := "cycloneive_clkctrl"; + ena_register_mode : STRING := "Falling Edge"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01 + ); + port ( + inclk : in std_logic_vector(3 downto 0) := "0000"; + clkselect : in std_logic_vector(1 downto 0) := "00"; + ena : in std_logic := '1'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + outclk : out std_logic + ); + attribute VITAL_LEVEL0 of cycloneive_clkctrl : entity is TRUE; +end cycloneive_clkctrl; + +architecture vital_clkctrl of cycloneive_clkctrl is + attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE; + + component cycloneive_ena_reg + generic ( + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + clk : in std_logic; + ena : in std_logic := '1'; + d : in std_logic; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + q : out std_logic + ); + end component; + + signal inclk_ipd : std_logic_vector(3 downto 0); + signal clkselect_ipd : std_logic_vector(1 downto 0); + signal ena_ipd : std_logic; + signal clkmux_out : std_logic; + signal clkmux_out_inv : std_logic; + signal cereg_clr : std_logic; + signal cereg1_out : std_logic; + signal cereg2_out : std_logic; + signal ena_out : std_logic; + signal outclk_tmp : std_logic; + signal vcc : std_logic := '1'; +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0)); + VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1)); + VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2)); + VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3)); + VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0)); + VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1)); + end block; + + process(inclk_ipd, clkselect_ipd) + variable tmp : std_logic; + begin + if (clkselect_ipd = "11") then + tmp := inclk_ipd(3); + elsif (clkselect_ipd = "10") then + tmp := inclk_ipd(2); + elsif (clkselect_ipd = "01") then + tmp := inclk_ipd(1); + else + tmp := inclk_ipd(0); + end if; + clkmux_out <= tmp; + clkmux_out_inv <= NOT tmp; + end process; + + extena0_reg : cycloneive_ena_reg + port map ( + clk => clkmux_out_inv, + ena => vcc, + d => ena_ipd, + clrn => vcc, + prn => devpor, + q => cereg1_out + ); + + extena1_reg : cycloneive_ena_reg + port map ( + clk => clkmux_out_inv, + ena => vcc, + d => cereg1_out, + clrn => vcc, + prn => devpor, + q => cereg2_out + ); + + ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE + ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out; + + outclk_tmp <= ena_out AND clkmux_out; + + -- output path + process (inclk_ipd,outclk_tmp) + variable outclk_VitalGlitchData : VitalGlitchDataType; + begin + ---------------------- + -- Path Delay Section + ---------------------- + + VitalPathDelay01 + ( + OutSignal => outclk, + OutSignalName => "OUTCLK", + OutTemp => outclk_tmp, + Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE), + 1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE), + 2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE), + 3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)), + GlitchData => outclk_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + end process; + + +end vital_clkctrl; + +-- +-- +-- CYCLONEIVE_RUBLOCK Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_rublock is + generic + ( + sim_init_config : string := "factory"; + sim_init_watchdog_value : integer := 0; + sim_init_status : integer := 0; + lpm_type : string := "cycloneive_rublock" + ); + port + ( + clk : in std_logic; + shiftnld : in std_logic; + captnupdt : in std_logic; + regin : in std_logic; + rsttimer : in std_logic; + rconfig : in std_logic; + regout : out std_logic + ); + +end cycloneive_rublock; + +architecture architecture_rublock of cycloneive_rublock is + +begin + +end architecture_rublock; + + +-- +-- +-- CYCLONEIVE_APFCONTROLLER Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_apfcontroller is + generic + ( + lpm_type: string := "cycloneive_apfcontroller" + ); + port + ( + usermode : out std_logic; + nceout : out std_logic + ); + +end cycloneive_apfcontroller; + +architecture architecture_apfcontroller of cycloneive_apfcontroller is + + +begin + +end architecture_apfcontroller; + + + +-------------------------------------------------------------------- +-- +-- Module Name : cycloneive_termination +-- +-- Description : Cycloneive Termination Atom VHDL simulation model +-- +-------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY cycloneive_termination IS + GENERIC ( + pullup_control_to_core: string := "false"; + power_down : string := "true"; + test_mode : string := "false"; + left_shift_termination_code : string := "false"; + pullup_adder : integer := 0; + pulldown_adder : integer := 0; + clock_divide_by : integer := 32; -- 1, 4, 32 + runtime_control : string := "false"; + shift_vref_rup : string := "true"; + shift_vref_rdn : string := "true"; + shifted_vref_control : string := "true"; + lpm_type : string := "cycloneive_termination"); + PORT ( + rup : IN std_logic := '0'; + rdn : IN std_logic := '0'; + terminationclock : IN std_logic := '0'; + terminationclear : IN std_logic := '0'; + devpor : IN std_logic := '1'; + devclrn : IN std_logic := '1'; + comparatorprobe : OUT std_logic; + terminationcontrolprobe : OUT std_logic; + calibrationdone : OUT std_logic; + terminationcontrol : OUT std_logic_vector(15 DOWNTO 0)); +END cycloneive_termination; + +ARCHITECTURE cycloneive_termination_arch OF cycloneive_termination IS + SIGNAL rup_compout : std_logic := '0'; + SIGNAL rdn_compout : std_logic := '1'; + +BEGIN + calibrationdone <= '1'; -- power-up calibration status + + comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout; + rup_compout <= rup; + rdn_compout <= not rdn; + +END cycloneive_termination_arch; +------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_jtag +-- +-- Description : Cycloneive JTAG VHDL Simulation model +-- +------------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_jtag is + generic ( + lpm_type : string := "cycloneive_jtag" + ); + port ( + tms : in std_logic := '0'; + tck : in std_logic := '0'; + tdi : in std_logic := '0'; + tdoutap : in std_logic := '0'; + tdouser : in std_logic := '0'; + tdo: out std_logic; + tmsutap: out std_logic; + tckutap: out std_logic; + tdiutap: out std_logic; + shiftuser: out std_logic; + clkdruser: out std_logic; + updateuser: out std_logic; + runidleuser: out std_logic; + usr1user: out std_logic + ); +end cycloneive_jtag; + +architecture architecture_jtag of cycloneive_jtag is +begin + +end architecture_jtag; + +------------------------------------------------------------------- +-- +-- Entity Name : cycloneive_crcblock +-- +-- Description : Cycloneive CRCBLOCK VHDL Simulation model +-- +------------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_crcblock is + generic ( + oscillator_divider : integer := 1; + lpm_type : string := "cycloneive_crcblock" + ); + port ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + ldsrc : in std_logic := '0'; + crcerror : out std_logic; + regout : out std_logic + ); +end cycloneive_crcblock; + +architecture architecture_crcblock of cycloneive_crcblock is +begin + crcerror <= '0'; + regout <= '0'; + +end architecture_crcblock; + +-- +-- +-- CYCLONEIVE_OSCILLATOR Model +-- +-- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cycloneive_atom_pack.all; + +entity cycloneive_oscillator is + generic + ( + lpm_type: string := "cycloneive_oscillator"; + TimingChecksOn: Boolean := True; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01; + tipd_oscena : VitalDelayType01 := DefPropDelay01 + ); + port + ( + oscena : in std_logic; + clkout : out std_logic + ); + +end cycloneive_oscillator; + +architecture architecture_oscillator of cycloneive_oscillator is + signal oscena_ipd : std_logic; + signal int_osc : std_logic := '0'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (oscena_ipd, oscena, tipd_oscena); + end block; + + VITAL_osc : process(oscena_ipd, int_osc) + variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock + variable osc_VitalGlitchData : VitalGlitchDataType; + begin + if (oscena_ipd = '1') then + if ((int_osc = '0') or (int_osc = '1')) then + int_osc <= not int_osc after OSC_PW; + else + int_osc <= '0' after OSC_PW; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => clkout, + OutSignalName => "osc", + OutTemp => int_osc, + Paths => (0 => (InputChangeTime => oscena_ipd'last_event, + PathDelay => tpd_oscena_clkout_posedge, + PathCondition => (oscena_ipd = '1'))), + GlitchData => osc_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + end process; + +end architecture_oscillator; + + diff --git a/Common/sim/altera/cycloneive_components.vhd b/Common/sim/altera/cycloneive_components.vhd new file mode 100644 index 0000000..9daafc2 --- /dev/null +++ b/Common/sim/altera/cycloneive_components.vhd @@ -0,0 +1,847 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, the Altera Quartus II License Agreement, +-- the Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Altera and sold by Altera or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. +-- Quartus II 15.0.0 Build 145 04/22/2015 + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use work.cycloneive_atom_pack.all; + +package cycloneive_components is + + +-- +-- cycloneive_lcell_comb +-- + +COMPONENT cycloneive_lcell_comb + generic ( + lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1'); + sum_lutc_input : string := "datac"; + dont_touch : string := "off"; + lpm_type : string := "cycloneive_lcell_comb"; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; + tpd_datab_combout : VitalDelayType01 := DefPropDelay01; + tpd_datac_combout : VitalDelayType01 := DefPropDelay01; + tpd_datad_combout : VitalDelayType01 := DefPropDelay01; + tpd_cin_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; + tpd_datab_cout : VitalDelayType01 := DefPropDelay01; + tpd_datac_cout : VitalDelayType01 := DefPropDelay01; + tpd_datad_cout : VitalDelayType01 := DefPropDelay01; + tpd_cin_cout : VitalDelayType01 := DefPropDelay01; + tipd_dataa : VitalDelayType01 := DefPropDelay01; + tipd_datab : VitalDelayType01 := DefPropDelay01; + tipd_datac : VitalDelayType01 := DefPropDelay01; + tipd_datad : VitalDelayType01 := DefPropDelay01; + tipd_cin : VitalDelayType01 := DefPropDelay01 + ); + port ( + dataa : in std_logic := '1'; + datab : in std_logic := '1'; + datac : in std_logic := '1'; + datad : in std_logic := '1'; + cin : in std_logic := '0'; + combout : out std_logic; + cout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_routing_wire +-- + +COMPONENT cycloneive_routing_wire + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_pll +-- + +COMPONENT cycloneive_pll + GENERIC ( + operation_mode : string := "normal"; + pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM + compensate_clock : string := "clock0"; + inclk0_input_frequency : integer := 0; + inclk1_input_frequency : integer := 0; + self_reset_on_loss_lock : string := "off"; + switch_over_type : string := "auto"; + switch_over_counter : integer := 1; + enable_switch_over_counter : string := "off"; + bandwidth : integer := 0; + bandwidth_type : string := "auto"; + use_dc_coupling : string := "false"; + lock_c : integer := 4; + sim_gate_lock_device_behavior : string := "off"; + lock_high : integer := 0; + lock_low : integer := 0; + lock_window_ui : string := "0.05"; + lock_window : time := 5 ps; + test_bypass_lock_detect : string := "off"; + clk0_output_frequency : integer := 0; + clk0_multiply_by : integer := 0; + clk0_divide_by : integer := 0; + clk0_phase_shift : string := "0"; + clk0_duty_cycle : integer := 50; + clk1_output_frequency : integer := 0; + clk1_multiply_by : integer := 0; + clk1_divide_by : integer := 0; + clk1_phase_shift : string := "0"; + clk1_duty_cycle : integer := 50; + clk2_output_frequency : integer := 0; + clk2_multiply_by : integer := 0; + clk2_divide_by : integer := 0; + clk2_phase_shift : string := "0"; + clk2_duty_cycle : integer := 50; + clk3_output_frequency : integer := 0; + clk3_multiply_by : integer := 0; + clk3_divide_by : integer := 0; + clk3_phase_shift : string := "0"; + clk3_duty_cycle : integer := 50; + clk4_output_frequency : integer := 0; + clk4_multiply_by : integer := 0; + clk4_divide_by : integer := 0; + clk4_phase_shift : string := "0"; + clk4_duty_cycle : integer := 50; + pfd_min : integer := 0; + pfd_max : integer := 0; + vco_min : integer := 0; + vco_max : integer := 0; + vco_center : integer := 0; + m_initial : integer := 1; + m : integer := 0; + n : integer := 1; + c0_high : integer := 1; + c0_low : integer := 1; + c0_initial : integer := 1; + c0_mode : string := "bypass"; + c0_ph : integer := 0; + c1_high : integer := 1; + c1_low : integer := 1; + c1_initial : integer := 1; + c1_mode : string := "bypass"; + c1_ph : integer := 0; + c2_high : integer := 1; + c2_low : integer := 1; + c2_initial : integer := 1; + c2_mode : string := "bypass"; + c2_ph : integer := 0; + c3_high : integer := 1; + c3_low : integer := 1; + c3_initial : integer := 1; + c3_mode : string := "bypass"; + c3_ph : integer := 0; + c4_high : integer := 1; + c4_low : integer := 1; + c4_initial : integer := 1; + c4_mode : string := "bypass"; + c4_ph : integer := 0; + m_ph : integer := 0; + clk0_counter : string := "unused"; + clk1_counter : string := "unused"; + clk2_counter : string := "unused"; + clk3_counter : string := "unused"; + clk4_counter : string := "unused"; + c1_use_casc_in : string := "off"; + c2_use_casc_in : string := "off"; + c3_use_casc_in : string := "off"; + c4_use_casc_in : string := "off"; + m_test_source : integer := -1; + c0_test_source : integer := -1; + c1_test_source : integer := -1; + c2_test_source : integer := -1; + c3_test_source : integer := -1; + c4_test_source : integer := -1; + vco_multiply_by : integer := 0; + vco_divide_by : integer := 0; + vco_post_scale : integer := 1; + vco_frequency_control : string := "auto"; + vco_phase_shift_step : integer := 0; + charge_pump_current : integer := 10; + loop_filter_r : string := " 1.0"; + loop_filter_c : integer := 0; + pll_compensation_delay : integer := 0; + simulation_type : string := "functional"; + lpm_type : string := "cycloneive_pll"; + clk0_use_even_counter_mode : string := "off"; + clk1_use_even_counter_mode : string := "off"; + clk2_use_even_counter_mode : string := "off"; + clk3_use_even_counter_mode : string := "off"; + clk4_use_even_counter_mode : string := "off"; + clk0_use_even_counter_value : string := "off"; + clk1_use_even_counter_value : string := "off"; + clk2_use_even_counter_value : string := "off"; + clk3_use_even_counter_value : string := "off"; + clk4_use_even_counter_value : string := "off"; + init_block_reset_a_count : integer := 1; + init_block_reset_b_count : integer := 1; + charge_pump_current_bits : integer := 0; + lock_window_ui_bits : integer := 0; + loop_filter_c_bits : integer := 0; + loop_filter_r_bits : integer := 0; + test_counter_c0_delay_chain_bits : integer := 0; + test_counter_c1_delay_chain_bits : integer := 0; + test_counter_c2_delay_chain_bits : integer := 0; + test_counter_c3_delay_chain_bits : integer := 0; + test_counter_c4_delay_chain_bits : integer := 0; + test_counter_c5_delay_chain_bits : integer := 0; + test_counter_m_delay_chain_bits : integer := 0; + test_counter_n_delay_chain_bits : integer := 0; + test_feedback_comp_delay_chain_bits : integer := 0; + test_input_comp_delay_chain_bits : integer := 0; + test_volt_reg_output_mode_bits : integer := 0; + test_volt_reg_output_voltage_bits : integer := 0; + test_volt_reg_test_mode : string := "false"; + vco_range_detector_high_bits : integer := -1; + vco_range_detector_low_bits : integer := -1; + scan_chain_mif_file : string := ""; + auto_settings : string := "true"; + family_name : string := "Cycloneive"; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + TimingChecksOn : Boolean := true; + InstancePath : STRING := "*"; + tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_pfdena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_fbin : VitalDelayType01 := DefPropDelay01; + tipd_scanclk : VitalDelayType01 := DefPropDelay01; + tipd_scanclkena : VitalDelayType01 := DefPropDelay01; + tipd_scandata : VitalDelayType01 := DefPropDelay01; + tipd_configupdate : VitalDelayType01 := DefPropDelay01; + tipd_clkswitch : VitalDelayType01 := DefPropDelay01; + tipd_phaseupdown : VitalDelayType01 := DefPropDelay01; + tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01); + tipd_phasestep : VitalDelayType01 := DefPropDelay01; + tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + use_vco_bypass : string := "false" + ); + PORT + ( + inclk : in std_logic_vector(1 downto 0); + fbin : in std_logic := '0'; + fbout : out std_logic; + clkswitch : in std_logic := '0'; + areset : in std_logic := '0'; + pfdena : in std_logic := '1'; + scandata : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanclkena : in std_logic := '1'; + configupdate : in std_logic := '0'; + clk : out std_logic_vector(4 downto 0); + phasecounterselect : in std_logic_vector(2 downto 0) := "000"; + phaseupdown : in std_logic := '0'; + phasestep : in std_logic := '0'; + clkbad : out std_logic_vector(1 downto 0); + activeclock : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic; + phasedone : out std_logic; + vcooverrange : out std_logic; + vcounderrange : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_ff +-- + +COMPONENT cycloneive_ff + generic ( + power_up : string := "low"; + x_on_violation : string := "on"; + lpm_type : string := "cycloneive_ff"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + clrn : in std_logic := '1'; + aload : in std_logic := '0'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + ena : in std_logic := '1'; + asdata : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_ram_block +-- + +COMPONENT cycloneive_ram_block + GENERIC ( + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock: STRING := "clock1"; + port_b_read_enable_clock: STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + safe_write : STRING := "err_on_2clk"; + init_file_restructured : STRING := "unused"; + lpm_type : string := "cycloneive_ram_block"; + lpm_hint : string := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : BIT_VECTOR := X"0"; + mem_init1 : BIT_VECTOR := X"0"; + mem_init2 : BIT_VECTOR := X"0"; + mem_init3 : BIT_VECTOR := X"0"; + mem_init4 : BIT_VECTOR := X"0"; + connectivity_checking : string := "off" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +-- +-- cycloneive_mac_mult +-- + +COMPONENT cycloneive_mac_mult + GENERIC ( + dataa_width : integer := 18; + datab_width : integer := 18; + dataa_clock : string := "none"; + datab_clock : string := "none"; + signa_clock : string := "none"; + signb_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + lpm_hint : string := "true"; + lpm_type : string := "cycloneive_mac_mult" + ); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0'); + signa : IN std_logic := '1'; + signb : IN std_logic := '1'; + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '0'; + dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneive_mac_out +-- + +COMPONENT cycloneive_mac_out + GENERIC ( + dataa_width : integer := 1; + output_clock : string := "none"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tipd_dataa : VitalDelayArrayType01(35 downto 0) + := (OTHERS => DefPropDelay01); + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_aclr : VitalDelayType01 := DefPropDelay01; + tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01); + tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01); + tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst); + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + lpm_hint : string := "true"; + lpm_type : string := "cycloneive_mac_out"); + PORT ( + dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0'); + clk : IN std_logic := '0'; + aclr : IN std_logic := '0'; + ena : IN std_logic := '1'; + dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0); + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneive_io_ibuf +-- + +COMPONENT cycloneive_io_ibuf + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_ibar : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_ibar_o : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + differential_mode : string := "false"; + bus_hold : string := "false"; + simulate_z_as : string := "Z"; + lpm_type : string := "cycloneive_io_ibuf" + ); + PORT ( + i : IN std_logic := '0'; + ibar : IN std_logic := '0'; + o : OUT std_logic + ); +END COMPONENT; + +-- +-- cycloneive_io_obuf +-- + +COMPONENT cycloneive_io_obuf + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_oe_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tpd_oe_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + open_drain_output : string := "false"; + bus_hold : string := "false"; + lpm_type : string := "cycloneive_io_obuf" + ); + PORT ( + i : IN std_logic := '0'; + oe : IN std_logic := '1'; + seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + devoe : IN std_logic := '1'; + o : OUT std_logic; + obar : OUT std_logic + ); +END COMPONENT; + +-- +-- cycloneive_ddio_oe +-- + +COMPONENT cycloneive_ddio_oe + generic( + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + lpm_type : string := "cycloneive_ddio_oe" + ); + PORT ( + oe : IN std_logic := '1'; + clk : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneive_ddio_out +-- + +COMPONENT cycloneive_ddio_out + generic( + tipd_datainlo : VitalDelayType01 := DefPropDelay01; + tipd_datainhi : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkhi : VitalDelayType01 := DefPropDelay01; + tipd_clklo : VitalDelayType01 := DefPropDelay01; + tipd_muxsel : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + use_new_clocking_model : string := "false"; + lpm_type : string := "cycloneive_ddio_out" + ); + PORT ( + datainlo : IN std_logic := '0'; + datainhi : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkhi : IN std_logic := '0'; + clklo : IN std_logic := '0'; + muxsel : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic ; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cycloneive_pseudo_diff_out +-- + +COMPONENT cycloneive_pseudo_diff_out + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + lpm_type : string := "cycloneive_pseudo_diff_out" + ); + PORT ( + i : IN std_logic := '0'; + o : OUT std_logic; + obar : OUT std_logic + ); +END COMPONENT; + +-- +-- cycloneive_io_pad +-- + +COMPONENT cycloneive_io_pad + GENERIC ( + lpm_type : string := "cycloneive_io_pad"); + PORT ( + padin : IN std_logic := '0'; -- Input Pad + padout : OUT std_logic); -- Output Pad +END COMPONENT; + +-- +-- cycloneive_asmiblock +-- + +COMPONENT cycloneive_asmiblock + generic ( + lpm_type : string := "cycloneive_asmiblock"; + enable_sim : string := "false" + ); + port ( + dclkin : in std_logic; + scein : in std_logic; + oe : in std_logic; + sdoin : in std_logic; + data0out: out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_clkctrl +-- + +COMPONENT cycloneive_clkctrl + generic ( + clock_type : STRING := "Auto"; + lpm_type : STRING := "cycloneive_clkctrl"; + ena_register_mode : STRING := "Falling Edge"; + TimingChecksOn : Boolean := True; + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + MsgOnChecks : Boolean := DefMsgOnChecks; + XOnChecks : Boolean := DefXOnChecks; + InstancePath : STRING := "*"; + tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); + tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_ena : VitalDelayType01 := DefPropDelay01 + ); + port ( + inclk : in std_logic_vector(3 downto 0) := "0000"; + clkselect : in std_logic_vector(1 downto 0) := "00"; + ena : in std_logic := '1'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + outclk : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_rublock +-- + +COMPONENT cycloneive_rublock + generic + ( + sim_init_config : string := "factory"; + sim_init_watchdog_value : integer := 0; + sim_init_status : integer := 0; + lpm_type : string := "cycloneive_rublock" + ); + port + ( + clk : in std_logic; + shiftnld : in std_logic; + captnupdt : in std_logic; + regin : in std_logic; + rsttimer : in std_logic; + rconfig : in std_logic; + regout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_apfcontroller +-- + +COMPONENT cycloneive_apfcontroller + generic + ( + lpm_type: string := "cycloneive_apfcontroller" + ); + port + ( + usermode : out std_logic; + nceout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_termination +-- + +COMPONENT cycloneive_termination + GENERIC ( + pullup_control_to_core: string := "false"; + power_down : string := "true"; + test_mode : string := "false"; + left_shift_termination_code : string := "false"; + pullup_adder : integer := 0; + pulldown_adder : integer := 0; + clock_divide_by : integer := 32; -- 1, 4, 32 + runtime_control : string := "false"; + shift_vref_rup : string := "true"; + shift_vref_rdn : string := "true"; + shifted_vref_control : string := "true"; + lpm_type : string := "cycloneive_termination"); + PORT ( + rup : IN std_logic := '0'; + rdn : IN std_logic := '0'; + terminationclock : IN std_logic := '0'; + terminationclear : IN std_logic := '0'; + devpor : IN std_logic := '1'; + devclrn : IN std_logic := '1'; + comparatorprobe : OUT std_logic; + terminationcontrolprobe : OUT std_logic; + calibrationdone : OUT std_logic; + terminationcontrol : OUT std_logic_vector(15 DOWNTO 0)); +END COMPONENT; + +-- +-- cycloneive_jtag +-- + +COMPONENT cycloneive_jtag + generic ( + lpm_type : string := "cycloneive_jtag" + ); + port ( + tms : in std_logic := '0'; + tck : in std_logic := '0'; + tdi : in std_logic := '0'; + tdoutap : in std_logic := '0'; + tdouser : in std_logic := '0'; + tdo: out std_logic; + tmsutap: out std_logic; + tckutap: out std_logic; + tdiutap: out std_logic; + shiftuser: out std_logic; + clkdruser: out std_logic; + updateuser: out std_logic; + runidleuser: out std_logic; + usr1user: out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_crcblock +-- + +COMPONENT cycloneive_crcblock + generic ( + oscillator_divider : integer := 1; + lpm_type : string := "cycloneive_crcblock" + ); + port ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + ldsrc : in std_logic := '0'; + crcerror : out std_logic; + regout : out std_logic + ); +END COMPONENT; + +-- +-- cycloneive_oscillator +-- + +COMPONENT cycloneive_oscillator + generic + ( + lpm_type: string := "cycloneive_oscillator"; + TimingChecksOn: Boolean := True; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01; + tipd_oscena : VitalDelayType01 := DefPropDelay01 + ); + port + ( + oscena : in std_logic; + clkout : out std_logic + ); +END COMPONENT; + +end cycloneive_components; diff --git a/Common/sim/altera/cyclonev_atoms.vhd b/Common/sim/altera/cyclonev_atoms.vhd new file mode 100644 index 0000000..713c367 --- /dev/null +++ b/Common/sim/altera/cyclonev_atoms.vhd @@ -0,0 +1,7686 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- This simulation model contains highly confidential and +-- proprietary information of Altera and is being provided +-- in accordance with and subject to the protections of the +-- applicable Altera Program License Subscription Agreement +-- which governs its use and disclosure. Your use of Altera +-- Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, +-- and any output files any of the foregoing (including device +-- programming or simulation files), and any associated +-- documentation or information are expressly subject to the +-- terms and conditions of the Altera Program License Subscription +-- Agreement, the Altera Quartus II License Agreement, the Altera +-- MegaCore Function License Agreement, or other applicable +-- license agreement, including, without limitation, that your +-- use is for the sole purpose of simulating designs for use +-- exclusively in logic devices manufactured by Altera and sold +-- by Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. Altera products and +-- services are protected under numerous U.S. and foreign patents, +-- maskwork rights, copyrights and other intellectual property laws. +-- Altera assumes no responsibility or liability arising out of the +-- application or use of this simulation model. +-- Quartus II 15.0.0 Build 145 04/22/2015 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +package cyclonev_atom_pack is + +function str_to_bin (lut_mask : string ) return std_logic_vector; + +function product(list : std_logic_vector) return std_logic ; + +function alt_conv_integer(arg : in std_logic_vector) return integer; + + +-- default generic values + CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns); + CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns); + CONSTANT DefSetupHoldCnst : TIME := 0 ns; + CONSTANT DefPulseWdthCnst : TIME := 0 ns; +-- default control options +-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent; +-- change default delay type to Transport : for spr 68748 + CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport; + CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE; + CONSTANT DefGlitchXOn : BOOLEAN := FALSE; + CONSTANT DefMsgOnChecks : BOOLEAN := TRUE; + CONSTANT DefXOnChecks : BOOLEAN := TRUE; +-- output strength mapping + -- UX01ZWHL- + CONSTANT PullUp : VitalOutputMapType := "UX01HX01X"; + CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X"; + CONSTANT PullDown : VitalOutputMapType := "UX01LX01X"; +-- primitive result strength mapping + CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' ); + CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' ); + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) + +-- Declare array types for CAM_SLICE + TYPE cyclonev_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0); + +function int2str( value : integer ) return string; + +function map_x_to_0 (value : std_logic) return std_logic; + +function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME; + +function int2bit (arg : boolean) return std_logic; +function int2bit (arg : integer) return std_logic; +function bin2int (s : bit_vector) return integer; +function bin2int (s : bit) return integer; +function bin2int (s : std_logic_vector) return integer; +function bin2int (s : std_logic) return integer; +function int2bin (arg : integer; size : integer) return std_logic_vector; +function int2bin (arg : boolean; size : integer) return std_logic_vector; +function calc_sum_len( widtha : integer; widthb : integer) return integer; + +end cyclonev_atom_pack; + +library IEEE; +use IEEE.std_logic_1164.all; + +package body cyclonev_atom_pack is + +type masklength is array (4 downto 1) of std_logic_vector(3 downto 0); +function str_to_bin (lut_mask : string) return std_logic_vector is +variable slice : masklength := (OTHERS => "0000"); +variable mask : std_logic_vector(15 downto 0); + + +begin + + for i in 1 to lut_mask'length loop + case lut_mask(i) is + when '0' => slice(i) := "0000"; + when '1' => slice(i) := "0001"; + when '2' => slice(i) := "0010"; + when '3' => slice(i) := "0011"; + when '4' => slice(i) := "0100"; + when '5' => slice(i) := "0101"; + when '6' => slice(i) := "0110"; + when '7' => slice(i) := "0111"; + when '8' => slice(i) := "1000"; + when '9' => slice(i) := "1001"; + when 'a' => slice(i) := "1010"; + when 'A' => slice(i) := "1010"; + when 'b' => slice(i) := "1011"; + when 'B' => slice(i) := "1011"; + when 'c' => slice(i) := "1100"; + when 'C' => slice(i) := "1100"; + when 'd' => slice(i) := "1101"; + when 'D' => slice(i) := "1101"; + when 'e' => slice(i) := "1110"; + when 'E' => slice(i) := "1110"; + when others => slice(i) := "1111"; + end case; + end loop; + + + mask := (slice(1) & slice(2) & slice(3) & slice(4)); + return (mask); + +end str_to_bin; + +function product (list: std_logic_vector) return std_logic is +begin + + for i in 0 to 31 loop + if list(i) = '0' then + return ('0'); + end if; + end loop; + return ('1'); + +end product; + +function alt_conv_integer(arg : in std_logic_vector) return integer is +variable result : integer; +begin + result := 0; + for i in arg'range loop + if arg(i) = '1' then + result := result + 2**i; + end if; + end loop; + return result; +end alt_conv_integer; + +function int2str( value : integer ) return string is +variable ivalue,index : integer; +variable digit : integer; +variable line_no: string(8 downto 1) := " "; +begin + ivalue := value; + index := 1; + if (ivalue = 0) then + line_no := " 0"; + end if; + while (ivalue > 0) loop + digit := ivalue MOD 10; + ivalue := ivalue/10; + case digit is + when 0 => + line_no(index) := '0'; + when 1 => + line_no(index) := '1'; + when 2 => + line_no(index) := '2'; + when 3 => + line_no(index) := '3'; + when 4 => + line_no(index) := '4'; + when 5 => + line_no(index) := '5'; + when 6 => + line_no(index) := '6'; + when 7 => + line_no(index) := '7'; + when 8 => + line_no(index) := '8'; + when 9 => + line_no(index) := '9'; + when others => + ASSERT FALSE + REPORT "Illegal number!" + SEVERITY ERROR; + end case; + index := index + 1; + end loop; + return line_no; +end; + +function map_x_to_0 (value : std_logic) return std_logic is +begin + if (Is_X (value) = TRUE) then + return '0'; + else + return value; + end if; +end; + +function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS + +variable Temp : TIME; +variable TransitionTime : TIME := TIME'HIGH; +variable PathDelay : TIME := TIME'HIGH; + +begin + + for i IN Paths'RANGE loop + next when not Paths(i).PathCondition; + + next when Paths(i).InputChangeTime > TransitionTime; + + Temp := Paths(i).PathDelay(tr01); + + if Paths(i).InputChangeTime < TransitionTime then + PathDelay := Temp; + else + if Temp < PathDelay then + PathDelay := Temp; + end if; + end if; + TransitionTime := Paths(i).InputChangeTime; + end loop; + + return PathDelay; + +end; + +function int2bit (arg : integer) return std_logic is + variable int_val : integer := arg; + variable result : std_logic; + begin + + if (int_val = 0) then + result := '0'; + else + result := '1'; + end if; + + return result; +end int2bit; + +function int2bit (arg : boolean) return std_logic is + variable int_val : boolean := arg; + variable result : std_logic; + begin + + if (int_val ) then + result := '1'; + else + result := '0'; + end if; + + return result; +end int2bit; + +function bin2int (s : bit_vector) return integer is + + constant temp : bit_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : bit) return integer is + constant temp : bit := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + +function bin2int (s : std_logic_vector) return integer is + + constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : std_logic) return integer is + constant temp : std_logic := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + + function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + +function int2bin (arg : boolean; size : integer) return std_logic_vector is + variable result : std_logic_vector(size-1 downto 0); + begin + if(arg)then + result := (OTHERS => '1'); + else + result := (OTHERS => '0'); + end if; + return result; + end int2bin; + +function calc_sum_len( widtha : integer; widthb : integer) return integer is +variable result: integer; +begin + if(widtha >= widthb) then + result := widtha + 1; + else + result := widthb + 1; + end if; + return result; +end calc_sum_len; + +end cyclonev_atom_pack; + +Library ieee; +use ieee.std_logic_1164.all; + +Package cyclonev_pllpack is + + + procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer); + + procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ); + + function gcd (X: integer; Y: integer) return integer; + + function count_digit (X: integer) return integer; + + function scale_num (X: integer; Y: integer) return integer; + + function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) return integer; + + function output_counter_value (clk_divide: integer; clk_mult : integer ; + M: integer; N: integer ) return integer; + + function counter_mode (duty_cycle: integer; output_counter_value: integer) return string; + + function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer; + + function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer; + + function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer; + + function counter_time_delay ( clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer; + + function get_phase_degree (phase_shift: integer; clk_period: integer) return integer; + + function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer; + + function counter_ph (tap_phase: integer; m : integer; n: integer) return integer; + + function ph_adjust (tap_phase: integer; ph_base : integer) return integer; + + function translate_string (mode : string) return string; + + function str2int (s : string) return integer; + + function dqs_str2int (s : string) return integer; + +end cyclonev_pllpack; + +package body cyclonev_pllpack is + + +-- finds the closest integer fraction of a given pair of numerator and denominator. +procedure find_simple_integer_fraction( numerator : in integer; + denominator : in integer; + max_denom : in integer; + fraction_num : out integer; + fraction_div : out integer) is + constant MAX_ITER : integer := 20; + type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer; + + variable quotient_array : INT_ARRAY; + variable int_loop_iter : integer; + variable int_quot : integer; + variable m_value : integer; + variable d_value : integer; + variable old_m_value : integer; + variable swap : integer; + variable loop_iter : integer; + variable num : integer; + variable den : integer; + variable i_max_iter : integer; + +begin + loop_iter := 0; + + if (numerator = 0) then + num := 1; + else + num := numerator; + end if; + + if (denominator = 0) then + den := 1; + else + den := denominator; + end if; + + i_max_iter := max_iter; + + while (loop_iter < i_max_iter) loop + int_quot := num / den; + quotient_array(loop_iter) := int_quot; + num := num - (den*int_quot); + loop_iter := loop_iter+1; + + if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then + -- calculate the numerator and denominator if there is a restriction on the + -- max denom value or if the loop is ending + m_value := 0; + d_value := 1; + -- get the rounded value at this stage for the remaining fraction + if (den /= 0) then + m_value := (2*num/den); + end if; + -- calculate the fraction numerator and denominator at this stage + for int_loop_iter in (loop_iter-1) downto 0 loop + if (m_value = 0) then + m_value := quotient_array(int_loop_iter); + d_value := 1; + else + old_m_value := m_value; + m_value := (quotient_array(int_loop_iter)*m_value) + d_value; + d_value := old_m_value; + end if; + end loop; + -- if the denominator is less than the maximum denom_value or if there is no restriction save it + if ((d_value <= max_denom) or (max_denom = -1)) then + if ((m_value = 0) or (d_value = 0)) then + fraction_num := numerator; + fraction_div := denominator; + else + fraction_num := m_value; + fraction_div := d_value; + end if; + end if; + -- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round) + if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then + i_max_iter := loop_iter; + end if; + end if; + -- swap the numerator and denominator for the next round + swap := den; + den := num; + num := swap; + end loop; +end find_simple_integer_fraction; + +-- find the M and N values for Manual phase based on the following 5 criterias: +-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz +-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz +-- 3. M is less than 512 +-- 4. N is less than 512 +-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps +-- of the desired vco-phase-shift-step +procedure find_m_and_n_4_manual_phase ( inclock_period : in integer; + vco_phase_shift_step : in integer; + clk0_mult: in integer; clk1_mult: in integer; + clk2_mult: in integer; clk3_mult: in integer; + clk4_mult: in integer; clk5_mult: in integer; + clk6_mult: in integer; clk7_mult: in integer; + clk8_mult: in integer; clk9_mult: in integer; + clk0_div : in integer; clk1_div : in integer; + clk2_div : in integer; clk3_div : in integer; + clk4_div : in integer; clk5_div : in integer; + clk6_div : in integer; clk7_div : in integer; + clk8_div : in integer; clk9_div : in integer; + clk0_used : in string; clk1_used : in string; + clk2_used : in string; clk3_used : in string; + clk4_used : in string; clk5_used : in string; + clk6_used : in string; clk7_used : in string; + clk8_used : in string; clk9_used : in string; + m : out integer; + n : out integer ) is + constant MAX_M : integer := 511; + constant MAX_N : integer := 511; + constant MAX_PFD : integer := 720; + constant MIN_PFD : integer := 5; + constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz) + constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz) + constant MAX_OFFSET : real := 0.004; + + variable vco_period : integer; + variable pfd_freq : integer; + variable vco_freq : integer; + variable vco_ps_step_value : integer; + + variable i_m : integer; + variable i_n : integer; + + variable i_pre_m : integer; + variable i_pre_n : integer; + + variable closest_vco_step_value : integer; + + variable i_max_iter : integer; + variable loop_iter : integer; + + variable clk0_div_factor_real : real; + variable clk1_div_factor_real : real; + variable clk2_div_factor_real : real; + variable clk3_div_factor_real : real; + variable clk4_div_factor_real : real; + variable clk5_div_factor_real : real; + variable clk6_div_factor_real : real; + variable clk7_div_factor_real : real; + variable clk8_div_factor_real : real; + variable clk9_div_factor_real : real; + variable clk0_div_factor_int : integer; + variable clk1_div_factor_int : integer; + variable clk2_div_factor_int : integer; + variable clk3_div_factor_int : integer; + variable clk4_div_factor_int : integer; + variable clk5_div_factor_int : integer; + variable clk6_div_factor_int : integer; + variable clk7_div_factor_int : integer; + variable clk8_div_factor_int : integer; + variable clk9_div_factor_int : integer; +begin + vco_period := vco_phase_shift_step * 8; + i_pre_m := 0; + i_pre_n := 0; + closest_vco_step_value := 0; + + LOOP_1 : for i_n_out in 1 to MAX_N loop + for i_m_out in 1 to MAX_M loop + + clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out); + clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out); + clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out); + clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out); + clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out); + clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out); + clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out); + clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out); + clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out); + clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out); + + clk0_div_factor_int := integer(clk0_div_factor_real); + clk1_div_factor_int := integer(clk1_div_factor_real); + clk2_div_factor_int := integer(clk2_div_factor_real); + clk3_div_factor_int := integer(clk3_div_factor_real); + clk4_div_factor_int := integer(clk4_div_factor_real); + clk5_div_factor_int := integer(clk5_div_factor_real); + clk6_div_factor_int := integer(clk6_div_factor_real); + clk7_div_factor_int := integer(clk7_div_factor_real); + clk8_div_factor_int := integer(clk8_div_factor_real); + clk9_div_factor_int := integer(clk9_div_factor_real); + + if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and + ((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and + ((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and + ((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and + ((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and + ((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and + ((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and + ((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and + ((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and + ((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) ) + then + if ((i_m_out /= 0) and (i_n_out /= 0)) + then + pfd_freq := 1000000 / (inclock_period * i_n_out); + vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out); + vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out); + + if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and + (vco_freq >= min_vco) and (vco_freq <= max_vco) ) + then + if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + exit LOOP_1; + else + if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))) + then + i_pre_m := i_m_out; + i_pre_n := i_n_out; + closest_vco_step_value := vco_ps_step_value; + end if; + end if; + end if; + end if; + end if; + end loop; + end loop; + + if ((i_pre_m /= 0) and (i_pre_n /= 0)) + then + find_simple_integer_fraction(i_pre_m, i_pre_n, + MAX_N, m, n); + else + n := 1; + m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult, + clk4_mult, clk5_mult, clk6_mult, + clk7_mult, clk8_mult, clk9_mult, inclock_period); + end if; +end find_m_and_n_4_manual_phase; + +-- find the greatest common denominator of X and Y +function gcd (X: integer; Y: integer) return integer is +variable L, S, R, G : integer := 1; +begin + if (X < Y) then -- find which is smaller. + S := X; + L := Y; + else + S := Y; + L := X; + end if; + + R := S; + while ( R > 1) loop + S := L; + L := R; + R := S rem L; -- divide bigger number by smaller. + -- remainder becomes smaller number. + end loop; + if (R = 0) then -- if evenly divisible then L is gcd else it is 1. + G := L; + else + G := R; + end if; + + return G; +end gcd; + +-- count the number of digits in the given integer +function count_digit (X: integer) + return integer is +variable count, result: integer := 0; +begin + result := X; + while (result /= 0) loop + result := (result / 10); + count := count + 1; + end loop; + + return count; +end count_digit; + +-- reduce the given huge number to Y significant digits +function scale_num (X: integer; Y: integer) + return integer is +variable count : integer := 0; +variable lc, fac_ten, result: integer := 1; +begin + count := count_digit(X); + + for lc in 1 to (count-Y) loop + fac_ten := fac_ten * 10; + end loop; + + result := (X / fac_ten); + + return result; +end scale_num; + +-- find the least common multiple of A1 to A10 +function lcm (A1: integer; A2: integer; A3: integer; A4: integer; + A5: integer; A6: integer; A7: integer; + A8: integer; A9: integer; A10: integer; P: integer) + return integer is +variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1; +begin + M1 := (A1 * A2)/gcd(A1, A2); + M2 := (M1 * A3)/gcd(M1, A3); + M3 := (M2 * A4)/gcd(M2, A4); + M4 := (M3 * A5)/gcd(M3, A5); + M5 := (M4 * A6)/gcd(M4, A6); + M6 := (M5 * A7)/gcd(M5, A7); + M7 := (M6 * A8)/gcd(M6, A8); + M8 := (M7 * A9)/gcd(M7, A9); + M9 := (M8 * A10)/gcd(M8, A10); + if (M9 < 3) then + R := 10; + elsif (M9 = 3) then + R := 9; + elsif ((M9 <= 10) and (M9 > 3)) then + R := 4 * M9; + elsif (M9 > 1000) then + R := scale_num(M9,3); + else + R := M9 ; + end if; + + return R; +end lcm; + +-- find the factor of division of the output clock frequency compared to the VCO +function output_counter_value (clk_divide: integer; clk_mult: integer ; + M: integer; N: integer ) return integer is +variable r_real : real := 1.0; +variable r: integer := 1; +begin + r_real := real(clk_divide * M)/ real(clk_mult * N); + r := integer(r_real); + + return R; +end output_counter_value; + +-- find the mode of each PLL counter - bypass, even or odd +function counter_mode (duty_cycle: integer; output_counter_value: integer) + return string is +variable R: string (1 to 6) := " "; +variable counter_value: integer := 1; +begin + counter_value := (2*duty_cycle*output_counter_value)/100; + if output_counter_value = 1 then + R := "bypass"; + elsif (counter_value REM 2) = 0 then + R := " even"; + else + R := " odd"; + end if; + + return R; +end counter_mode; + +-- find the number of VCO clock cycles to hold the output clock high +function counter_high (output_counter_value: integer := 1; duty_cycle: integer) + return integer is +variable R: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value *2)/100 ; + if (half_cycle_high REM 2 = 0) then + R := half_cycle_high/2 ; + else + R := (half_cycle_high/2) + 1; + end if; + + return R; +end; + +-- find the number of VCO clock cycles to hold the output clock low +function counter_low (output_counter_value: integer; duty_cycle: integer) + return integer is +variable R, R1: integer := 1; +variable half_cycle_high : integer := 1; +begin + half_cycle_high := (duty_cycle * output_counter_value*2)/100 ; + if (half_cycle_high REM 2 = 0) then + R1 := half_cycle_high/2 ; + else + R1 := (half_cycle_high/2) + 1; + end if; + + R := output_counter_value - R1; + + if (R = 0) then + R := 1; + end if; + + return R; +end; + +-- find the smallest time delay amongst t1 to t10 +function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 > 0) then return m9; else return 0; end if; +end; + +-- find the numerically largest negative number, and return its absolute value +function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer; + t5: integer; t6: integer; t7: integer; t8: integer; + t9: integer; t10: integer) return integer is +variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0; +begin + if (t1 < t2) then m1 := t1; else m1 := t2; end if; + if (m1 < t3) then m2 := m1; else m2 := t3; end if; + if (m2 < t4) then m3 := m2; else m3 := t4; end if; + if (m3 < t5) then m4 := m3; else m4 := t5; end if; + if (m4 < t6) then m5 := m4; else m5 := t6; end if; + if (m5 < t7) then m6 := m5; else m6 := t7; end if; + if (m6 < t8) then m7 := m6; else m7 := t8; end if; + if (m7 < t9) then m8 := m7; else m8 := t9; end if; + if (m8 < t10) then m9 := m8; else m9 := t10; end if; + if (m9 < 0) then return (0 - m9); else return 0; end if; +end; + +-- adjust the phase (tap_phase) with the largest negative number (ph_base) +function ph_adjust (tap_phase: integer; ph_base : integer) return integer is +begin + return (tap_phase + ph_base); +end; + +-- find the time delay for each PLL counter +function counter_time_delay (clk_time_delay: integer; + m_time_delay: integer; n_time_delay: integer) + return integer is +variable R: integer := 0; +begin + R := clk_time_delay + m_time_delay - n_time_delay; + + return R; +end; + +-- calculate the given phase shift (in ps) in terms of degrees +function get_phase_degree (phase_shift: integer; clk_period: integer) + return integer is +variable result: integer := 0; +begin + result := ( phase_shift * 360 ) / clk_period; + -- to round up the calculation result + if (result > 0) then + result := result + 1; + elsif (result < 0) then + result := result - 1; + else + result := 0; + end if; + + return result; +end; + +-- find the number of VCO clock cycles to wait initially before the first rising +-- edge of the output clock +function counter_initial (tap_phase: integer; m: integer; n: integer) + return integer is +variable R: integer; +variable R1: real; +begin + R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6; + -- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99. + -- This checking will ensure that the rounding up is done. + if (R1 >= 0.5) and (R1 <= 1.0) then + R1 := 1.0; + end if; + + R := integer(R1); + + return R; +end; + +-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to +function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is +variable R: integer := 0; +begin + -- 0.5 is added for proper rounding of the tap_phase. + R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8; + + return R; +end; + +-- convert given string to length 6 by padding with spaces +function translate_string (mode : string) return string is +variable new_mode : string (1 to 6) := " "; +begin + if (mode = "bypass") then + new_mode := "bypass"; + elsif (mode = "even") then + new_mode := " even"; + elsif (mode = "odd") then + new_mode := " odd"; + end if; + + return new_mode; +end; + +function str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "i n string parameter! " + SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; + +function dqs_str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +variable err : boolean := false; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & " in string parameter! " + SEVERITY ERROR; + err := true; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + -- set error flag + err := true; + end case; + if (err) then + err := false; + else + newdigit := newdigit * 10 + digit; + end if; + end loop; + + return (sign*newdigit); +end; + +end cyclonev_pllpack; + +-- +-- +-- DFFE Model +-- +-- + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cyclonev_atom_pack.all; + +entity cyclonev_dffe is + generic( + TimingChecksOn: Boolean := True; + XOn: Boolean := DefGlitchXOn; + MsgOn: Boolean := DefGlitchMsgOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01; + tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst; + thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tipd_D : VitalDelayType01 := DefPropDelay01; + tipd_CLRN : VitalDelayType01 := DefPropDelay01; + tipd_PRN : VitalDelayType01 := DefPropDelay01; + tipd_CLK : VitalDelayType01 := DefPropDelay01; + tipd_ENA : VitalDelayType01 := DefPropDelay01); + + port( + Q : out STD_LOGIC := '0'; + D : in STD_LOGIC; + CLRN : in STD_LOGIC; + PRN : in STD_LOGIC; + CLK : in STD_LOGIC; + ENA : in STD_LOGIC); + attribute VITAL_LEVEL0 of cyclonev_dffe : entity is TRUE; +end cyclonev_dffe; + +-- architecture body -- + +architecture behave of cyclonev_dffe is + attribute VITAL_LEVEL0 of behave : architecture is TRUE; + + signal D_ipd : STD_ULOGIC := 'U'; + signal CLRN_ipd : STD_ULOGIC := 'U'; + signal PRN_ipd : STD_ULOGIC := 'U'; + signal CLK_ipd : STD_ULOGIC := 'U'; + signal ENA_ipd : STD_ULOGIC := 'U'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (D_ipd, D, tipd_D); + VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN); + VitalWireDelay (PRN_ipd, PRN, tipd_PRN); + VitalWireDelay (CLK_ipd, CLK, tipd_CLK); + VitalWireDelay (ENA_ipd, ENA, tipd_ENA); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd) + + -- timing check results + VARIABLE Tviol_D_CLK : STD_ULOGIC := '0'; + VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0'; + VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit; + VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7); + VARIABLE D_delayed : STD_ULOGIC := 'U'; + VARIABLE CLK_delayed : STD_ULOGIC := 'U'; + VARIABLE ENA_delayed : STD_ULOGIC := 'U'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0'); + + -- output glitch detection variables + VARIABLE Q_VitalGlitchData : VitalGlitchDataType; + + + CONSTANT dffe_Q_tab : VitalStateTableType := ( + ( L, L, x, x, x, x, x, x, x, L ), + ( L, H, L, H, H, x, x, H, x, H ), + ( L, H, L, H, x, L, x, H, x, H ), + ( L, H, L, x, H, H, x, H, x, H ), + ( L, H, H, x, x, x, H, x, x, S ), + ( L, H, x, x, x, x, L, x, x, H ), + ( L, H, x, x, x, x, H, L, x, S ), + ( L, x, L, L, L, x, H, H, x, L ), + ( L, x, L, L, x, L, H, H, x, L ), + ( L, x, L, x, L, H, H, H, x, L ), + ( L, x, x, x, x, x, x, x, x, S )); + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_D_CLK, + TimingData => TimingData_D_CLK, + TestSignal => D_ipd, + TestSignalName => "D", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_D_CLK_noedge_posedge, + SetupLow => tsetup_D_CLK_noedge_posedge, + HoldHigh => thold_D_CLK_noedge_posedge, + HoldLow => thold_D_CLK_noedge_posedge, + CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/DFFE", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ENA_CLK, + TimingData => TimingData_ENA_CLK, + TestSignal => ENA_ipd, + TestSignalName => "ENA", + RefSignal => CLK_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ENA_CLK_noedge_posedge, + SetupLow => tsetup_ENA_CLK_noedge_posedge, + HoldHigh => thold_ENA_CLK_noedge_posedge, + HoldLow => thold_ENA_CLK_noedge_posedge, + CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/DFFE", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_D_CLK or Tviol_ENA_CLK; + VitalStateTable( + StateTable => dffe_Q_tab, + DataIn => ( + Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd), + Result => Results, + NumStates => 1, + PreviousDataIn => PrevData_Q); + D_delayed := D_ipd; + CLK_delayed := CLK_ipd; + ENA_delayed := ENA_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Q, + OutSignalName => "Q", + OutTemp => Results(1), + Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE), + 1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE), + 2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)), + GlitchData => Q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; + +-- +-- +-- cyclonev_mux21 Model +-- +-- + +LIBRARY IEEE; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use work.cyclonev_atom_pack.all; + +entity cyclonev_mux21 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic); + attribute VITAL_LEVEL0 of cyclonev_mux21 : entity is TRUE; +end cyclonev_mux21; + +architecture AltVITAL of cyclonev_mux21 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + signal A_ipd, B_ipd, S_ipd : std_logic; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (A_ipd, A, tipd_A); + VitalWireDelay (B_ipd, B, tipd_B); + VitalWireDelay (S_ipd, S, tipd_S); + end block; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (A_ipd, B_ipd, S_ipd) + + -- output glitch detection variables + VARIABLE MO_GlitchData : VitalGlitchDataType; + + variable tmp_MO : std_logic; + begin + ------------------------- + -- Functionality Section + ------------------------- + if (S_ipd = '1') then + tmp_MO := B_ipd; + else + tmp_MO := A_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => MO, + OutSignalName => "MO", + OutTemp => tmp_MO, + Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE), + 1 => (B_ipd'last_event, tpd_B_MO, TRUE), + 2 => (S_ipd'last_event, tpd_S_MO, TRUE)), + GlitchData => MO_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; + +-- +-- +-- cyclonev_mux41 Model +-- +-- + +LIBRARY IEEE; +use ieee.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use work.cyclonev_atom_pack.all; + +entity cyclonev_mux41 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_IN0_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN1_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN2_MO : VitalDelayType01 := DefPropDelay01; + tpd_IN3_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); + tipd_IN0 : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01; + tipd_IN2 : VitalDelayType01 := DefPropDelay01; + tipd_IN3 : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01) + ); + port ( + IN0 : in std_logic := '0'; + IN1 : in std_logic := '0'; + IN2 : in std_logic := '0'; + IN3 : in std_logic := '0'; + S : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + MO : out std_logic + ); + attribute VITAL_LEVEL0 of cyclonev_mux41 : entity is TRUE; +end cyclonev_mux41; + +architecture AltVITAL of cyclonev_mux41 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic; + signal S_ipd : std_logic_vector(1 downto 0); + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (IN0_ipd, IN0, tipd_IN0); + VitalWireDelay (IN1_ipd, IN1, tipd_IN1); + VitalWireDelay (IN2_ipd, IN2, tipd_IN2); + VitalWireDelay (IN3_ipd, IN3, tipd_IN3); + VitalWireDelay (S_ipd(0), S(0), tipd_S(0)); + VitalWireDelay (S_ipd(1), S(1), tipd_S(1)); + end block; + + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1)) + + -- output glitch detection variables + VARIABLE MO_GlitchData : VitalGlitchDataType; + + variable tmp_MO : std_logic; + begin + ------------------------- + -- Functionality Section + ------------------------- + if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then + tmp_MO := IN3_ipd; + elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then + tmp_MO := IN2_ipd; + elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then + tmp_MO := IN1_ipd; + else + tmp_MO := IN0_ipd; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => MO, + OutSignalName => "MO", + OutTemp => tmp_MO, + Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE), + 1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE), + 2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE), + 3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE), + 4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE), + 5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)), + GlitchData => MO_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; + +-- +-- +-- cyclonev_and1 Model +-- +-- +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use work.cyclonev_atom_pack.all; + +-- entity declaration -- +entity cyclonev_and1 is + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01); + + port( + Y : out STD_LOGIC; + IN1 : in STD_LOGIC); + attribute VITAL_LEVEL0 of cyclonev_and1 : entity is TRUE; +end cyclonev_and1; + +-- architecture body -- + +architecture AltVITAL of cyclonev_and1 is + attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE; + + SIGNAL IN1_ipd : STD_ULOGIC := 'U'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (IN1_ipd, IN1, tipd_IN1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (IN1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS Y_zd : STD_ULOGIC is Results(1); + + -- output glitch detection variables + VARIABLE Y_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + Y_zd := TO_X01(IN1_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => Y, + OutSignalName => "Y", + OutTemp => Y_zd, + Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)), + GlitchData => Y_GlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; +end AltVITAL; +--------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_ff +-- +-- Description : CycloneV FF VHDL simulation model +-- +-- +--------------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cyclonev_atom_pack.all; +use work.cyclonev_and1; + +entity cyclonev_ff is + generic ( + power_up : string := "low"; + x_on_violation : string := "on"; + lpm_type : string := "cyclonev_ff"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + clrn : in std_logic := '1'; + aload : in std_logic := '0'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + ena : in std_logic := '1'; + asdata : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); + attribute VITAL_LEVEL0 of cyclonev_ff : entity is TRUE; +end cyclonev_ff; + +architecture vital_lcell_ff of cyclonev_ff is + attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE; + signal clk_ipd : std_logic; + signal d_ipd : std_logic; + signal d_dly : std_logic; + signal asdata_ipd : std_logic; + signal asdata_dly : std_logic; + signal asdata_dly1 : std_logic; + signal sclr_ipd : std_logic; + signal sload_ipd : std_logic; + signal clrn_ipd : std_logic; + signal aload_ipd : std_logic; + signal ena_ipd : std_logic; + +component cyclonev_and1 + generic (XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + tpd_IN1_Y : VitalDelayType01 := DefPropDelay01; + tipd_IN1 : VitalDelayType01 := DefPropDelay01 + ); + + port (Y : out STD_LOGIC; + IN1 : in STD_LOGIC + ); +end component; + +begin + +ddelaybuffer: cyclonev_and1 + port map(IN1 => d_ipd, + Y => d_dly); + +asdatadelaybuffer: cyclonev_and1 + port map(IN1 => asdata_ipd, + Y => asdata_dly); + +asdatadelaybuffer1: cyclonev_and1 + port map(IN1 => asdata_dly, + Y => asdata_dly1); + + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (d_ipd, d, tipd_d); + VitalWireDelay (asdata_ipd, asdata, tipd_asdata); + VitalWireDelay (sclr_ipd, sclr, tipd_sclr); + VitalWireDelay (sload_ipd, sload, tipd_sload); + VitalWireDelay (clrn_ipd, clrn, tipd_clrn); + VitalWireDelay (aload_ipd, aload, tipd_aload); + VitalWireDelay (ena_ipd, ena, tipd_ena); + end block; + + VITALtiming : process (clk_ipd, d_dly, asdata_dly1, + sclr_ipd, sload_ipd, clrn_ipd, aload_ipd, + ena_ipd, devclrn, devpor) + + variable Tviol_d_clk : std_ulogic := '0'; + variable Tviol_asdata_clk : std_ulogic := '0'; + variable Tviol_sclr_clk : std_ulogic := '0'; + variable Tviol_sload_clk : std_ulogic := '0'; + variable Tviol_ena_clk : std_ulogic := '0'; + variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit; + variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit; + variable q_VitalGlitchData : VitalGlitchDataType; + + variable iq : std_logic := '0'; + variable idata: std_logic := '0'; + + -- variables for 'X' generation + variable violation : std_logic := '0'; + + begin + + if (now = 0 ns) then + if (power_up = "low") then + iq := '0'; + elsif (power_up = "high") then + iq := '1'; + end if; + end if; + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + + VitalSetupHoldCheck ( + Violation => Tviol_d_clk, + TimingData => TimingData_d_clk, + TestSignal => d, + TestSignalName => "DATAIN", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_d_clk_noedge_posedge, + SetupLow => tsetup_d_clk_noedge_posedge, + HoldHigh => thold_d_clk_noedge_posedge, + HoldLow => thold_d_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (sload_ipd) OR + (sclr_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_asdata_clk, + TimingData => TimingData_asdata_clk, + TestSignal => asdata_ipd, + TestSignalName => "ASDATA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_asdata_clk_noedge_posedge, + SetupLow => tsetup_asdata_clk_noedge_posedge, + HoldHigh => thold_asdata_clk_noedge_posedge, + HoldLow => thold_asdata_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT sload_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_sclr_clk, + TimingData => TimingData_sclr_clk, + TestSignal => sclr_ipd, + TestSignalName => "SCLR", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_sclr_clk_noedge_posedge, + SetupLow => tsetup_sclr_clk_noedge_posedge, + HoldHigh => thold_sclr_clk_noedge_posedge, + HoldLow => thold_sclr_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_sload_clk, + TimingData => TimingData_sload_clk, + TestSignal => sload_ipd, + TestSignalName => "SLOAD", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_sload_clk_noedge_posedge, + SetupLow => tsetup_sload_clk_noedge_posedge, + HoldHigh => thold_sload_clk_noedge_posedge, + HoldLow => thold_sload_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) OR + (NOT ena_ipd)) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + VitalSetupHoldCheck ( + Violation => Tviol_ena_clk, + TimingData => TimingData_ena_clk, + TestSignal => ena_ipd, + TestSignalName => "ENA", + RefSignal => clk_ipd, + RefSignalName => "CLK", + SetupHigh => tsetup_ena_clk_noedge_posedge, + SetupLow => tsetup_ena_clk_noedge_posedge, + HoldHigh => thold_ena_clk_noedge_posedge, + HoldLow => thold_ena_clk_noedge_posedge, + CheckEnabled => TO_X01((NOT clrn_ipd) OR + (NOT devpor) OR + (NOT devclrn) ) /= '1', + RefTransition => '/', + HeaderMsg => InstancePath & "/LCELL_FF", + XOn => XOnChecks, + MsgOn => MsgOnChecks ); + + end if; + + violation := Tviol_d_clk or Tviol_asdata_clk or + Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk; + + + if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then + iq := '0'; + elsif (aload_ipd = '1') then + iq := asdata_dly1; + elsif (violation = 'X' and x_on_violation = "on") then + iq := 'X'; + elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then + if (ena_ipd = '1') then + if (sclr_ipd = '1') then + iq := '0'; + elsif (sload_ipd = '1') then + iq := asdata_dly1; + else + iq := d_dly; + end if; + end if; + end if; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + OutSignalName => "Q", + OutTemp => iq, + Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE), + 1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE), + 2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE), + 3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)), + GlitchData => q_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end vital_lcell_ff; + +---------------------------------------------------------------------------------- +--Module Name: cyclonev_pseudo_diff_out -- +--Description: Simulation model for Stratix V Pseudo Differential -- +-- Output Buffer -- +---------------------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_pseudo_diff_out IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tipd_oein : VitalDelayType01 := DefPropDelay01; + tpd_oein_oeout : VitalDelayType01 := DefPropDelay01; + tpd_oein_oebout : VitalDelayType01 := DefPropDelay01; + tipd_dtcin : VitalDelayType01 := DefPropDelay01; + tpd_dtcin_dtc : VitalDelayType01 := DefPropDelay01; + tpd_dtcin_dtcbar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + lpm_type : string := "stratuxv_pseudo_diff_out" + ); + PORT ( + i : IN std_logic := '0'; + o : OUT std_logic; + obar : OUT std_logic; + dtcin : in std_logic := '0'; + oein : in std_logic := '0'; + dtc : OUT std_logic; + dtcbar : OUT std_logic; + oeout : OUT std_logic; + oebout : OUT std_logic + ); +END cyclonev_pseudo_diff_out; + +ARCHITECTURE arch OF cyclonev_pseudo_diff_out IS + SIGNAL i_ipd : std_logic ; + SIGNAL o_tmp : std_logic ; + SIGNAL obar_tmp : std_logic; + SIGNAL dtcin_ipd : std_logic ; + SIGNAL dtc_tmp : std_logic ; + SIGNAL dtcbar_tmp : std_logic; + SIGNAL oein_ipd : std_logic ; + SIGNAL oeout_tmp : std_logic ; + SIGNAL oebout_tmp : std_logic; + +BEGIN + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + + PROCESS( i_ipd) + BEGIN + IF (i_ipd = '0') THEN + o_tmp <= '0'; + obar_tmp <= '1'; + ELSE + IF (i_ipd = '1') THEN + o_tmp <= '1'; + obar_tmp <= '0'; + ELSE + o_tmp <= i_ipd; + obar_tmp <= i_ipd; + END IF; + END IF; + END PROCESS; + + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( o_tmp,obar_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable obar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => o_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => obar, + OutSignalName => "obar", + OutTemp => obar_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)), + GlitchData => obar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; + +-- oe + WireDelay_OE : block + begin + VitalWireDelay (oein_ipd, oein, tipd_oein); + end block; + + PROCESS( oein_ipd) + BEGIN + IF (oein_ipd = '0') THEN + oeout_tmp <= '0'; + oebout_tmp <= '0'; + ELSE + IF (oein_ipd = '1') THEN + oeout_tmp <= '1'; + oebout_tmp <= '1'; + ELSE + oeout_tmp <= oein_ipd; + oebout_tmp <= oein_ipd; + END IF; + END IF; + END PROCESS; + + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( oeout_tmp,oebout_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable obar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => oeout, + OutSignalName => "oeout", + OutTemp => oeout_tmp, + Paths => (0 => (oein_ipd'last_event, tpd_oein_oeout, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => oebout, + OutSignalName => "oebout", + OutTemp => oebout_tmp, + Paths => (0 => (oein_ipd'last_event, tpd_oein_oebout, TRUE)), + GlitchData => obar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; + + + +-- dtc + + WireDelay_DTC : block + begin + VitalWireDelay (dtcin_ipd, dtcin, tipd_dtcin); + end block; + + PROCESS( dtcin_ipd) + BEGIN + IF (dtcin_ipd = '0') THEN + dtc_tmp <= '0'; + dtcbar_tmp <= '0'; + ELSE + IF (dtcin_ipd = '1') THEN + dtc_tmp <= '1'; + dtcbar_tmp <= '1'; + ELSE + dtc_tmp <= dtcin_ipd; + dtcbar_tmp <= dtcin_ipd; + END IF; + END IF; + END PROCESS; + + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( dtc_tmp,dtcbar_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable dtcbar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => dtc, + OutSignalName => "dtc", + OutTemp => dtc_tmp, + Paths => (0 => (dtcin_ipd'last_event, tpd_dtcin_dtc, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => dtcbar, + OutSignalName => "dtcbar", + OutTemp => dtcbar_tmp, + Paths => (0 => (dtcin_ipd'last_event, tpd_dtcin_dtcbar, TRUE)), + GlitchData => dtcbar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; +END arch; +--------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_lcell_comb +-- +-- Description : CYCLONEV LCELL_COMB VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cyclonev_atom_pack.all; + +entity cyclonev_lcell_comb is + generic ( + lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1'); + shared_arith : string := "off"; + extended_lut : string := "off"; + dont_touch : string := "off"; + lpm_type : string := "cyclonev_lcell_comb"; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; + tpd_datab_combout : VitalDelayType01 := DefPropDelay01; + tpd_datac_combout : VitalDelayType01 := DefPropDelay01; + tpd_datad_combout : VitalDelayType01 := DefPropDelay01; + tpd_datae_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataf_combout : VitalDelayType01 := DefPropDelay01; + tpd_datag_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01; + tpd_datab_sumout : VitalDelayType01 := DefPropDelay01; + tpd_datac_sumout : VitalDelayType01 := DefPropDelay01; + tpd_datad_sumout : VitalDelayType01 := DefPropDelay01; + tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01; + tpd_cin_sumout : VitalDelayType01 := DefPropDelay01; + tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; + tpd_datab_cout : VitalDelayType01 := DefPropDelay01; + tpd_datac_cout : VitalDelayType01 := DefPropDelay01; + tpd_datad_cout : VitalDelayType01 := DefPropDelay01; + tpd_dataf_cout : VitalDelayType01 := DefPropDelay01; + tpd_cin_cout : VitalDelayType01 := DefPropDelay01; + tpd_sharein_cout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01; + tpd_datab_shareout : VitalDelayType01 := DefPropDelay01; + tpd_datac_shareout : VitalDelayType01 := DefPropDelay01; + tpd_datad_shareout : VitalDelayType01 := DefPropDelay01; + tipd_dataa : VitalDelayType01 := DefPropDelay01; + tipd_datab : VitalDelayType01 := DefPropDelay01; + tipd_datac : VitalDelayType01 := DefPropDelay01; + tipd_datad : VitalDelayType01 := DefPropDelay01; + tipd_datae : VitalDelayType01 := DefPropDelay01; + tipd_dataf : VitalDelayType01 := DefPropDelay01; + tipd_datag : VitalDelayType01 := DefPropDelay01; + tipd_cin : VitalDelayType01 := DefPropDelay01; + tipd_sharein : VitalDelayType01 := DefPropDelay01 + ); + + port ( + dataa : in std_logic := '0'; + datab : in std_logic := '0'; + datac : in std_logic := '0'; + datad : in std_logic := '0'; + datae : in std_logic := '0'; + dataf : in std_logic := '0'; + datag : in std_logic := '0'; + cin : in std_logic := '0'; + sharein : in std_logic := '0'; + combout : out std_logic; + sumout : out std_logic; + cout : out std_logic; + shareout : out std_logic + ); + attribute VITAL_LEVEL0 of cyclonev_lcell_comb : entity is TRUE; +end cyclonev_lcell_comb; + +architecture vital_lcell_comb of cyclonev_lcell_comb is + attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE; + signal dataa_ipd : std_logic; + signal datab_ipd : std_logic; + signal datac_ipd : std_logic; + signal datad_ipd : std_logic; + signal datae_ipd : std_logic; + signal dataf_ipd : std_logic; + signal datag_ipd : std_logic; + signal cin_ipd : std_logic; + signal sharein_ipd : std_logic; + signal f2_input3 : std_logic; + -- sub masks + signal f0_mask : std_logic_vector(15 downto 0); + signal f1_mask : std_logic_vector(15 downto 0); + signal f2_mask : std_logic_vector(15 downto 0); + signal f3_mask : std_logic_vector(15 downto 0); +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (dataa_ipd, dataa, tipd_dataa); + VitalWireDelay (datab_ipd, datab, tipd_datab); + VitalWireDelay (datac_ipd, datac, tipd_datac); + VitalWireDelay (datad_ipd, datad, tipd_datad); + VitalWireDelay (datae_ipd, datae, tipd_datae); + VitalWireDelay (dataf_ipd, dataf, tipd_dataf); + VitalWireDelay (datag_ipd, datag, tipd_datag); + VitalWireDelay (cin_ipd, cin, tipd_cin); + VitalWireDelay (sharein_ipd, sharein, tipd_sharein); + end block; + + f0_mask <= lut_mask(15 downto 0); + f1_mask <= lut_mask(31 downto 16); + f2_mask <= lut_mask(47 downto 32); + f3_mask <= lut_mask(63 downto 48); + + f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd; + +VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, + datae_ipd, dataf_ipd, f2_input3, cin_ipd, + sharein_ipd) + +variable combout_VitalGlitchData : VitalGlitchDataType; +variable sumout_VitalGlitchData : VitalGlitchDataType; +variable cout_VitalGlitchData : VitalGlitchDataType; +variable shareout_VitalGlitchData : VitalGlitchDataType; +-- sub lut outputs +variable f0_out : std_logic; +variable f1_out : std_logic; +variable f2_out : std_logic; +variable f3_out : std_logic; +-- muxed output +variable g0_out : std_logic; +variable g1_out : std_logic; +-- internal variables +variable f2_f : std_logic; +variable adder_input2 : std_logic; +-- output variables +variable combout_tmp : std_logic; +variable sumout_tmp : std_logic; +variable cout_tmp : std_logic; +-- temp variable for NCVHDL +variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1'); + +begin + + lut_mask_var := lut_mask; + + ------------------------ + -- Timing Check Section + ------------------------ + + f0_out := VitalMUX(data => f0_mask, + dselect => (datad_ipd, + datac_ipd, + datab_ipd, + dataa_ipd)); + f1_out := VitalMUX(data => f1_mask, + dselect => (datad_ipd, + f2_input3, + datab_ipd, + dataa_ipd)); + f2_out := VitalMUX(data => f2_mask, + dselect => (datad_ipd, + datac_ipd, + datab_ipd, + dataa_ipd)); + f3_out := VitalMUX(data => f3_mask, + dselect => (datad_ipd, + f2_input3, + datab_ipd, + dataa_ipd)); + + -- combout + if (extended_lut = "on") then + if (datae_ipd = '0') then + g0_out := f0_out; + g1_out := f2_out; + elsif (datae_ipd = '1') then + g0_out := f1_out; + g1_out := f3_out; + else + g0_out := 'X'; + g1_out := 'X'; + end if; + + if (dataf_ipd = '0') then + combout_tmp := g0_out; + elsif ((dataf_ipd = '1') or (g0_out = g1_out))then + combout_tmp := g1_out; + else + combout_tmp := 'X'; + end if; + else + combout_tmp := VitalMUX(data => lut_mask_var, + dselect => (dataf_ipd, + datae_ipd, + datad_ipd, + datac_ipd, + datab_ipd, + dataa_ipd)); + end if; + + -- sumout and cout + f2_f := VitalMUX(data => f2_mask, + dselect => (dataf_ipd, + datac_ipd, + datab_ipd, + dataa_ipd)); + + if (shared_arith = "on") then + adder_input2 := sharein_ipd; + else + adder_input2 := NOT f2_f; + end if; + + sumout_tmp := cin_ipd XOR f0_out XOR adder_input2; + cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR + (f0_out AND adder_input2); + + ---------------------- + -- Path Delay Section + ---------------------- + + VitalPathDelay01 ( + OutSignal => combout, + OutSignalName => "COMBOUT", + OutTemp => combout_tmp, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_combout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_combout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_combout, TRUE), + 4 => (datae_ipd'last_event, tpd_datae_combout, TRUE), + 5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE), + 6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)), + GlitchData => combout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => sumout, + OutSignalName => "SUMOUT", + OutTemp => sumout_tmp, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE), + 4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE), + 5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE), + 6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)), + GlitchData => sumout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => cout, + OutSignalName => "COUT", + OutTemp => cout_tmp, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_cout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_cout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_cout, TRUE), + 4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE), + 5 => (cin_ipd'last_event, tpd_cin_cout, TRUE), + 6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)), + GlitchData => cout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => shareout, + OutSignalName => "SHAREOUT", + OutTemp => f2_out, + Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE), + 1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE), + 2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE), + 3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)), + GlitchData => shareout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + +end process; + +end vital_lcell_comb; + + +--------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_routing_wire +-- +-- Description : CycloneV Routing Wire VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_routing_wire is + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); + attribute VITAL_LEVEL0 of cyclonev_routing_wire : entity is TRUE; +end cyclonev_routing_wire; + +ARCHITECTURE behave of cyclonev_routing_wire is +attribute VITAL_LEVEL0 of behave : architecture is TRUE; +signal datain_ipd : std_logic; +signal datainglitch_inert : std_logic; +begin + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (datain_ipd, datain, tipd_datain); + end block; + + VITAL: process(datain_ipd, datainglitch_inert) + variable datain_inert_VitalGlitchData : VitalGlitchDataType; + variable dataout_VitalGlitchData : VitalGlitchDataType; + + begin + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => datainglitch_inert, + OutSignalName => "datainglitch_inert", + OutTemp => datain_ipd, + Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)), + GlitchData => datain_inert_VitalGlitchData, + Mode => VitalInertial, + XOn => XOn, + MsgOn => MsgOn ); + + VitalPathDelay01 ( + OutSignal => dataout, + OutSignalName => "dataout", + OutTemp => datainglitch_inert, + Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)), + GlitchData => dataout_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn ); + + end process; + +end behave; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +LIBRARY altera_lnsim; +use altera_lnsim.altera_lnsim_components.all; +ENTITY cyclonev_ram_block IS + GENERIC ( + -- -------- GLOBAL PARAMETERS --------- + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + ecc_pipeline_stage_enabled : STRING := "false"; + enable_ecc : STRING := "false"; + width_eccstatus : INTEGER := 2; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + bist_ena : STRING := "false"; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock: STRING := "clock1"; + port_b_read_enable_clock: STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + lpm_type : string := "cyclonev_ram_block"; + lpm_hint : string := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : STRING := ""; + mem_init1 : STRING := ""; + mem_init2 : STRING := ""; + mem_init3 : STRING := ""; + mem_init4 : STRING := ""; + connectivity_checking : string := "off" + ); + -- -------- PORT DECLARATIONS --------- + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + nerror : IN STD_LOGIC := '1'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0'); + dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000"; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); + +END cyclonev_ram_block; + +ARCHITECTURE block_arch OF cyclonev_ram_block IS + +BEGIN + +inst : generic_m10k + generic map ( + operation_mode => operation_mode, + mixed_port_feed_through_mode => mixed_port_feed_through_mode, + ram_block_type => ram_block_type, + logical_ram_name => logical_ram_name, + init_file => init_file, + init_file_layout => init_file_layout, + ecc_pipeline_stage_enabled => ecc_pipeline_stage_enabled, + enable_ecc => enable_ecc, + width_eccstatus => width_eccstatus, + data_interleave_width_in_bits => data_interleave_width_in_bits, + data_interleave_offset_in_bits => data_interleave_offset_in_bits, + port_a_logical_ram_depth => port_a_logical_ram_depth, + port_a_logical_ram_width => port_a_logical_ram_width, + port_a_first_address => port_a_first_address, + port_a_last_address => port_a_last_address, + port_a_first_bit_number => port_a_first_bit_number, + port_a_data_out_clear => port_a_data_out_clear, + port_a_data_out_clock => port_a_data_out_clock, + port_a_data_width => port_a_data_width, + port_a_address_width => port_a_address_width, + port_a_byte_enable_mask_width => port_a_byte_enable_mask_width, + port_b_logical_ram_depth => port_b_logical_ram_depth, + port_b_logical_ram_width => port_b_logical_ram_width, + port_b_first_address => port_b_first_address, + port_b_last_address => port_b_last_address, + port_b_first_bit_number => port_b_first_bit_number, + port_b_address_clear => port_b_address_clear, + port_b_data_out_clear => port_b_data_out_clear, + port_b_data_in_clock => port_b_data_in_clock, + port_b_address_clock => port_b_address_clock, + port_b_write_enable_clock => port_b_write_enable_clock, + port_b_read_enable_clock => port_b_read_enable_clock, + port_b_byte_enable_clock => port_b_byte_enable_clock, + port_b_data_out_clock => port_b_data_out_clock, + port_b_data_width => port_b_data_width, + port_b_address_width => port_b_address_width, + port_b_byte_enable_mask_width => port_b_byte_enable_mask_width, + port_a_read_during_write_mode => port_a_read_during_write_mode, + port_b_read_during_write_mode => port_b_read_during_write_mode, + power_up_uninitialized => power_up_uninitialized, + lpm_type => lpm_type, + lpm_hint => lpm_hint, + connectivity_checking => connectivity_checking, + mem_init0 => mem_init0, + mem_init1 => mem_init1, + mem_init2 => mem_init2, + mem_init3 => mem_init3, + mem_init4 => mem_init4, + port_a_byte_size => port_a_byte_size, + port_b_byte_size => port_b_byte_size, + clk0_input_clock_enable => clk0_input_clock_enable, + clk0_core_clock_enable => clk0_core_clock_enable, + clk0_output_clock_enable => clk0_output_clock_enable, + clk1_input_clock_enable => clk1_input_clock_enable, + clk1_core_clock_enable => clk1_core_clock_enable, + clk1_output_clock_enable => clk1_output_clock_enable, + bist_ena => bist_ena, + port_a_address_clear => port_a_address_clear, + port_a_data_in_clock => port_a_data_in_clock, + port_a_address_clock => port_a_address_clock, + port_a_write_enable_clock => port_a_write_enable_clock, + port_a_byte_enable_clock => port_a_byte_enable_clock, + port_a_read_enable_clock => port_a_read_enable_clock + ) + port map ( + portadatain => portadatain , + portaaddr => portaaddr , + portawe => portawe , + portare => portare , + portbdatain => portbdatain , + portbaddr => portbaddr , + portbwe => portbwe , + portbre => portbre , + clk0 => clk0 , + clk1 => clk1 , + ena0 => ena0 , + ena1 => ena1 , + ena2 => ena2 , + ena3 => ena3 , + clr0 => clr0 , + clr1 => clr1 , + nerror => nerror , + portabyteenamasks => portabyteenamasks, + portbbyteenamasks => portbbyteenamasks, + portaaddrstall => portaaddrstall , + portbaddrstall => portbaddrstall , + devclrn => devclrn , + devpor => devpor , + eccstatus => eccstatus , + portadataout => portadataout , + portbdataout => portbdataout , + dftout => dftout + ); + +END block_arch; + + +---------------------------------------------------------------------------- +-- Entity Name : cyclonev_mlab_cell +-- Description : LUTRAM VHDL Simulation Model +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; +USE work.cyclonev_atom_pack.all; + +LIBRARY altera_lnsim; +use altera_lnsim.altera_lnsim_components.all; + +ENTITY cyclonev_mlab_cell IS + GENERIC ( + -- -------- GLOBAL PARAMETERS --------- + logical_ram_name : STRING := "lutram"; + logical_ram_depth : INTEGER := 0; + logical_ram_width : INTEGER := 0; + first_address : INTEGER := 0; + last_address : INTEGER := 0; + first_bit_number : INTEGER := 0; + init_file : STRING := "NONE"; + data_width : INTEGER := 20; + address_width : INTEGER := 5; + byte_enable_mask_width : INTEGER := 1; + byte_size : INTEGER := 1; + port_b_data_out_clock : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + lpm_type : STRING := "cyclonev_mlab_cell"; + lpm_hint : STRING := "true"; + mem_init0 : STRING := ""; + mixed_port_feed_through_mode : STRING := "new" + ); + PORT ( + -- -------- PORT DECLARATIONS --------- + portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0'); + portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1'); + + portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + + clr : IN STD_LOGIC := '0'; + + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + + portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END cyclonev_mlab_cell; + +ARCHITECTURE trans OF cyclonev_mlab_cell IS + +BEGIN + +inst : generic_28nm_lc_mlab_cell_impl + generic map ( + logical_ram_name => logical_ram_name , + logical_ram_depth => logical_ram_depth , + logical_ram_width => logical_ram_width , + first_address => first_address , + last_address => last_address , + first_bit_number => first_bit_number , + init_file => init_file , + data_width => data_width , + address_width => address_width , + byte_enable_mask_width => byte_enable_mask_width , + byte_size => byte_size , + port_b_data_out_clock => port_b_data_out_clock , + port_b_data_out_clear => port_b_data_out_clear , + lpm_type => lpm_type , + lpm_hint => lpm_hint , + mem_init0 => mem_init0 , + mixed_port_feed_through_mode => mixed_port_feed_through_mode + ) + port map ( + portadatain => portadatain , + portaaddr => portaaddr , + portabyteenamasks => portabyteenamasks , + portbaddr => portbaddr , + clk0 => clk0 , + clk1 => clk1 , + ena0 => ena0 , + ena1 => ena1 , + ena2 => ena2 , + clr => clr , + devclrn => devclrn , + devpor => devpor , + portbdataout => portbdataout + ); + + +END trans; +--------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_io_ibuf +-- +-- Description : CycloneV IO Ibuf VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_io_ibuf IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_ibar : VitalDelayType01 := DefPropDelay01; + tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_ibar_o : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + differential_mode : string := "false"; + bus_hold : string := "false"; + simulate_z_as : string := "Z"; + lpm_type : string := "cyclonev_io_ibuf" + ); + PORT ( + i : IN std_logic := '0'; + ibar : IN std_logic := '0'; + dynamicterminationcontrol : IN std_logic := '0'; + o : OUT std_logic + ); +END cyclonev_io_ibuf; + +ARCHITECTURE arch OF cyclonev_io_ibuf IS + SIGNAL i_ipd : std_logic := '0'; + SIGNAL ibar_ipd : std_logic := '0'; + SIGNAL o_tmp : std_logic; + SIGNAL out_tmp : std_logic; + SIGNAL prev_value : std_logic := '0'; +BEGIN + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (ibar_ipd, ibar, tipd_ibar); + end block; + + PROCESS(i_ipd, ibar_ipd) + BEGIN + IF (differential_mode = "false") THEN + IF (i_ipd = '1') THEN + o_tmp <= '1'; + prev_value <= '1'; + ELSIF (i_ipd = '0') THEN + o_tmp <= '0'; + prev_value <= '0'; + ELSE + o_tmp <= i_ipd; + END IF; + ELSE + IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then + o_tmp <= '0'; + ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then + o_tmp <= '1'; + ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then + o_tmp <= 'X'; + ELSE + o_tmp <= 'X'; + END IF; + END IF; + END PROCESS; + + out_tmp <= prev_value when (bus_hold = "true") else + 'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else + 'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else + '1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else + '0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else + o_tmp; + ---------------------- + -- Path Delay Section + ---------------------- + PROCESS( out_tmp) + variable output_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => out_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), + 1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)), + GlitchData => output_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; + END arch; + + + +--------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_io_obuf +-- +-- Description : CycloneV IO Obuf VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_io_obuf IS + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; + tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tipd_parallelterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_oe_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tpd_oe_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + open_drain_output : string := "false"; + shift_series_termination_control : string := "false"; + sim_dynamic_termination_control_is_connected : string := "false"; + bus_hold : string := "false"; + lpm_type : string := "cyclonev_io_obuf" + ); + PORT ( + i : IN std_logic := '0'; + oe : IN std_logic := '1'; + dynamicterminationcontrol : IN std_logic := '0'; + seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + parallelterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + devoe : IN std_logic := '1'; + o : OUT std_logic; + obar : OUT std_logic + ); +END cyclonev_io_obuf; + +ARCHITECTURE arch OF cyclonev_io_obuf IS + --INTERNAL Signals + SIGNAL i_ipd : std_logic := '0'; + SIGNAL oe_ipd : std_logic := '0'; + SIGNAL dynamicterminationcontrol_ipd : std_logic := '0'; + SIGNAL out_tmp : std_logic := 'Z'; + SIGNAL out_tmp_bar : std_logic; + SIGNAL prev_value : std_logic := '0'; + SIGNAL o_tmp : std_logic; + SIGNAL obar_tmp : std_logic; + SIGNAL o_tmp1 : std_logic; + SIGNAL obar_tmp1 : std_logic; + SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0'); + SIGNAL parallelterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0'); + +BEGIN + +WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (oe_ipd, oe, tipd_oe); + VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol); + g1 :for i in seriesterminationcontrol'range generate + VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i)); + end generate; + g2 :for i in parallelterminationcontrol'range generate + VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i)); + end generate; + + + end block; + PROCESS( i_ipd, oe_ipd) + BEGIN + IF (oe_ipd = '1') THEN + IF (open_drain_output = "true") THEN + IF (i_ipd = '0') THEN + out_tmp <= '0'; + out_tmp_bar <= '1'; + prev_value <= '0'; + ELSE + out_tmp <= 'Z'; + out_tmp_bar <= 'Z'; + END IF; + ELSE + IF (i_ipd = '0') THEN + out_tmp <= '0'; + out_tmp_bar <= '1'; + prev_value <= '0'; + ELSE + IF (i_ipd = '1') THEN + out_tmp <= '1'; + out_tmp_bar <= '0'; + prev_value <= '1'; + ELSE + out_tmp <= i_ipd; + out_tmp_bar <= i_ipd; + END IF; + END IF; + END IF; + ELSE + IF (oe_ipd = '0') THEN + out_tmp <= 'Z'; + out_tmp_bar <= 'Z'; + ELSE + out_tmp <= 'X'; + out_tmp_bar <= 'X'; + END IF; + END IF; + END PROCESS; + o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp; + obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar; + o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')) else o_tmp1 WHEN (devoe = '1') ELSE 'Z'; + obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z'; + --------------------- + -- Path Delay Section + ---------------------- + PROCESS( o_tmp,obar_tmp) + variable o_VitalGlitchData : VitalGlitchDataType; + variable obar_VitalGlitchData : VitalGlitchDataType; + BEGIN + VitalPathDelay01 ( + OutSignal => o, + OutSignalName => "o", + OutTemp => o_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE), + 1 => (oe_ipd'last_event, tpd_oe_o, TRUE)), + GlitchData => o_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + VitalPathDelay01 ( + OutSignal => obar, + OutSignalName => "obar", + OutTemp => obar_tmp, + Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE), + 1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)), + GlitchData => obar_VitalGlitchData, + Mode => DefGlitchMode, + XOn => XOn, + MsgOn => MsgOn + ); + END PROCESS; +END arch; + +----------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_ddio_in +-- +-- Description : CycloneV DDIO_IN VHDL simulation model +-- +-- +--------------------------------------------------------------------- +LIBRARY IEEE; +LIBRARY altera; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use altera.all; +use work.cyclonev_atom_pack.all; + + +ENTITY cyclonev_ddio_in IS + generic( + tipd_datain : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkn : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + use_clkn : string := "false"; + lpm_type : string := "cyclonev_ddio_in" + ); + PORT ( + datain : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkn : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + regoutlo : OUT std_logic; + regouthi : OUT std_logic; + dfflo : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cyclonev_ddio_in; + +ARCHITECTURE arch OF cyclonev_ddio_in IS + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +end component; + + --Internal Signals + SIGNAL datain_ipd : std_logic := '0'; + SIGNAL clk_ipd : std_logic := '0'; + SIGNAL clkn_ipd : std_logic := '0'; + SIGNAL ena_ipd : std_logic := '0'; + SIGNAL areset_ipd : std_logic := '0'; + SIGNAL sreset_ipd : std_logic := '0'; + SIGNAL ddioreg_aclr : std_logic; + SIGNAL ddioreg_prn : std_logic; + SIGNAL ddioreg_adatasdata : std_logic; + SIGNAL ddioreg_sclr : std_logic; + SIGNAL ddioreg_sload : std_logic; + SIGNAL ddioreg_clk : std_logic; + SIGNAL dfflo_tmp : std_logic; + SIGNAL regout_tmp_hi : std_logic; + SIGNAL regout_tmp_lo : std_logic; + SIGNAL regouthi_tmp : std_logic; + SIGNAL regoutlo_tmp : std_logic; + + +BEGIN + +WireDelay : block + begin + VitalWireDelay (datain_ipd, datain, tipd_datain); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (clkn_ipd, clkn, tipd_clkn); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (sreset_ipd, sreset, tipd_sreset); + end block; + + + ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd; + + --Decode the control values for the DDIO registers + PROCESS + BEGIN + WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; + IF (async_mode = "clear") THEN + ddioreg_aclr <= NOT areset_ipd; + ddioreg_prn <= '1'; + ELSIF (async_mode = "preset") THEN + ddioreg_aclr <= '1'; + ddioreg_prn <= NOT areset_ipd; + ELSE + ddioreg_aclr <= '1'; + ddioreg_prn <= '1'; + END IF; + + IF (sync_mode = "clear") THEN + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= sreset_ipd; + ddioreg_sload <= '0'; + ELSIF (sync_mode = "preset") THEN + ddioreg_adatasdata <= '1'; + ddioreg_sclr <= '0'; + ddioreg_sload <= sreset_ipd; + ELSE + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= '0'; + ddioreg_sload <= '0'; + END IF; + END PROCESS; + + --DDIO High Register + ddioreg_hi : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => datain_ipd, + clk => clk_ipd, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => regout_tmp_hi, + devpor => devpor, + devclrn => devclrn + ); + + --DDIO Low Register + ddioreg_lo : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => datain_ipd, + clk => ddioreg_clk, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dfflo_tmp, + devpor => devpor, + devclrn => devclrn + ); + + ddioreg_lo1 : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => dfflo_tmp, + clk => clk_ipd, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => regout_tmp_lo, + devpor => devpor, + devclrn => devclrn + ); + + regouthi <= regout_tmp_hi ; + regoutlo <= regout_tmp_lo ; + dfflo <= dfflo_tmp ; +END arch; + +--------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_ddio_oe +-- +-- Description : CycloneV DDIO_OE VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +LIBRARY altera; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use altera.all; +use work.cyclonev_atom_pack.all; + + + +ENTITY cyclonev_ddio_oe IS + generic( + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_octreadcontrol : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + disable_second_level_register : string := "false"; + lpm_type : string := "cyclonev_ddio_oe" + ); + + PORT ( + oe : IN std_logic := '1'; + octreadcontrol : IN std_logic := '1'; + clk : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cyclonev_ddio_oe; + +ARCHITECTURE arch OF cyclonev_ddio_oe IS + +component cyclonev_mux21 + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01 + ); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic + ); +end component; + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +end component; + + --Internal Signals + SIGNAL oe_ipd : std_logic := '0'; + SIGNAL octreadcontrol_ipd : std_logic := '0'; + SIGNAL clk_ipd : std_logic := '0'; + SIGNAL ena_ipd : std_logic := '0'; + SIGNAL areset_ipd : std_logic := '0'; + SIGNAL sreset_ipd : std_logic := '0'; + SIGNAL ddioreg_aclr : std_logic; + SIGNAL ddioreg_prn : std_logic; + SIGNAL ddioreg_adatasdata : std_logic; + SIGNAL ddioreg_sclr : std_logic; + SIGNAL ddioreg_sload : std_logic; + SIGNAL dfflo_tmp : std_logic; + SIGNAL dffhi_tmp : std_logic; + signal nclk : std_logic; + signal dataout_tmp : std_logic; + signal oe_octreadcontrol_tmp : std_logic; + signal second_level_register_tmp : std_logic; + + +BEGIN + + WireDelay : block + begin + VitalWireDelay (oe_ipd, oe, tipd_oe); + VitalWireDelay (octreadcontrol_ipd, octreadcontrol, tipd_octreadcontrol); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (sreset_ipd, sreset, tipd_sreset); + end block; + + nclk <= NOT clk_ipd; + PROCESS + BEGIN + WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; + IF (async_mode = "clear") THEN + ddioreg_aclr <= NOT areset_ipd; + ddioreg_prn <= '1'; + ELSIF (async_mode = "preset") THEN + ddioreg_aclr <= '1'; + ddioreg_prn <= NOT areset_ipd; + ELSE + ddioreg_aclr <= '1'; + ddioreg_prn <= '1'; + END IF; + + IF (sync_mode = "clear") THEN + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= sreset_ipd; + ddioreg_sload <= '0'; + ELSIF (sync_mode = "preset") THEN + ddioreg_adatasdata <= '1'; + ddioreg_sclr <= '0'; + ddioreg_sload <= sreset_ipd; + ELSE + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= '0'; + ddioreg_sload <= '0'; + END IF; + END PROCESS; + + ddioreg_hi : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => oe_octreadcontrol_tmp, + clk => clk_ipd, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dffhi_tmp, + devpor => devpor, + devclrn => devclrn + ); + + + --DDIO Low Register + second_level_register_tmp <= dffhi_tmp when(disable_second_level_register = "false") else '0'; + ddioreg_lo : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => second_level_register_tmp, + clk => nclk, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dfflo_tmp, + devpor => devpor, + devclrn => devclrn + ); + + --registered output + or_gate : cyclonev_mux21 + port map ( + A => dffhi_tmp, + B => dfflo_tmp, + S => dfflo_tmp, + MO => dataout + ); + + dfflo <= dfflo_tmp ; + dffhi <= dffhi_tmp ; + oe_octreadcontrol_tmp <= '1' when (octreadcontrol_ipd = '1' and oe_ipd = '1') else '0'; + + +END arch; +--------------------------------------------------------------------- +-- +-- Entity Name : cyclonev_ddio_out +-- +-- Description : CycloneV DDIO_OUT VHDL simulation model +-- +-- +--------------------------------------------------------------------- + +LIBRARY IEEE; +LIBRARY altera; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use altera.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_ddio_out IS + generic( + tipd_datainlo : VitalDelayType01 := DefPropDelay01; + tipd_datainhi : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkhi : VitalDelayType01 := DefPropDelay01; + tipd_clklo : VitalDelayType01 := DefPropDelay01; + tipd_muxsel : VitalDelayType01 := DefPropDelay01; + tipd_hrbsel : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + half_rate_mode : string := "false"; + use_new_clocking_model : string := "false"; + lpm_type : string := "cyclonev_ddio_out" + ); + PORT ( + datainlo : IN std_logic := '0'; + datainhi : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkhi : IN std_logic := '0'; + clklo : IN std_logic := '0'; + muxsel : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + hrbypass : IN std_logic := '0'; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END cyclonev_ddio_out; + +ARCHITECTURE arch OF cyclonev_ddio_out IS + +component cyclonev_mux21 + generic( + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + InstancePath: STRING := "*"; + tpd_A_MO : VitalDelayType01 := DefPropDelay01; + tpd_B_MO : VitalDelayType01 := DefPropDelay01; + tpd_S_MO : VitalDelayType01 := DefPropDelay01; + tipd_A : VitalDelayType01 := DefPropDelay01; + tipd_B : VitalDelayType01 := DefPropDelay01; + tipd_S : VitalDelayType01 := DefPropDelay01 + ); + port ( + A : in std_logic := '0'; + B : in std_logic := '0'; + S : in std_logic := '0'; + MO : out std_logic + ); +end component; + +component dffeas + generic ( + power_up : string := "DONT_CARE"; + is_wysiwyg : string := "false"; + x_on_violation : string := "on"; + lpm_type : string := "DFFEAS"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_prn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + ena : in std_logic := '1'; + clrn : in std_logic := '1'; + prn : in std_logic := '1'; + aload : in std_logic := '0'; + asdata : in std_logic := '1'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +end component; + --Internal Signals + SIGNAL datainlo_ipd : std_logic := '0'; + SIGNAL datainhi_ipd : std_logic := '0'; + SIGNAL clk_ipd : std_logic := '0'; + SIGNAL clkhi_ipd : std_logic := '0'; + SIGNAL clklo_ipd : std_logic := '0'; + SIGNAL muxsel_ipd : std_logic := '0'; + SIGNAL hrbsel_ipd : std_logic := '0'; + SIGNAL ena_ipd : std_logic := '0'; + SIGNAL areset_ipd : std_logic := '0'; + SIGNAL sreset_ipd : std_logic := '0'; + SIGNAL sel_mux_hi_hr : std_logic; + SIGNAL sel_mux_lo_hr : std_logic; + SIGNAL dataout_hr : std_logic; + SIGNAL ddioreg_aclr : std_logic; + SIGNAL ddioreg_prn : std_logic; + SIGNAL ddioreg_adatasdata : std_logic; + SIGNAL ddioreg_sclr : std_logic; + SIGNAL ddioreg_sload : std_logic; + SIGNAL dfflo_tmp : std_logic; + SIGNAL dffhi_tmp : std_logic; + SIGNAL dataout_tmp : std_logic; + Signal mux_sel : std_logic; + Signal mux_hi : std_logic; + Signal sel_mux_hi_in : std_logic; + signal nclk : std_logic; + signal clk1 : std_logic; + signal clk_hi : std_logic; + signal clk_lo : std_logic; + + signal muxsel1 : std_logic; + signal muxsel2: std_logic; + signal clk2 : std_logic; + signal muxsel_tmp: std_logic; + signal sel_mux_lo_in : std_logic; + signal datainlo_tmp : std_logic; + signal datainhi_tmp : std_logic; + signal hrb_sel: std_logic; + +BEGIN + +WireDelay : block + begin + VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo); + VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi); + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi); + VitalWireDelay (clklo_ipd, clklo, tipd_clklo); + VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel); + VitalWireDelay (hrbsel_ipd, hrbypass, tipd_hrbsel); + VitalWireDelay (ena_ipd, ena, tipd_ena); + VitalWireDelay (areset_ipd, areset, tipd_areset); + VitalWireDelay (sreset_ipd, sreset, tipd_sreset); + end block; + nclk <= NOT clk_ipd; + PROCESS + BEGIN + WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT; + IF (async_mode = "clear") THEN + ddioreg_aclr <= NOT areset_ipd; + ddioreg_prn <= '1'; + ELSIF (async_mode = "preset") THEN + ddioreg_aclr <= '1'; + ddioreg_prn <= NOT areset_ipd; + ELSE + ddioreg_aclr <= '1'; + ddioreg_prn <= '1'; + END IF; + + IF (sync_mode = "clear") THEN + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= sreset_ipd; + ddioreg_sload <= '0'; + ELSIF (sync_mode = "preset") THEN + ddioreg_adatasdata <= '1'; + ddioreg_sclr <= '0'; + ddioreg_sload <= sreset_ipd; + ELSE + ddioreg_adatasdata <= '0'; + ddioreg_sclr <= '0'; + ddioreg_sload <= '0'; + END IF; + END PROCESS; + + process(clk_ipd) + begin + clk1 <= clk_ipd; + end process; + + process(muxsel_ipd) + begin + muxsel1 <= muxsel_ipd; + end process; + + process(hrbsel_ipd) + begin + hrb_sel <= hrbsel_ipd; + end process; + + + --DDIO HIGH Register + clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd; + datainhi_tmp <= datainhi; + ddioreg_hi : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => datainhi_tmp, + clk => clk_hi, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dffhi_tmp, + devpor => devpor, + devclrn => devclrn + ); + + --DDIO Low Register + clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd; + datainlo_tmp <= datainlo; + ddioreg_lo : dffeas + GENERIC MAP ( + power_up => power_up + ) + PORT MAP ( + d => datainlo_tmp, + clk => clk_lo, + clrn => ddioreg_aclr, + prn => ddioreg_prn, + sclr => ddioreg_sclr, + sload => ddioreg_sload, + asdata => ddioreg_adatasdata, + ena => ena_ipd, + q => dfflo_tmp, + devpor => devpor, + devclrn => devclrn + ); + + muxsel2 <= muxsel1; + clk2 <= clk1; + mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2; + muxsel_tmp <= mux_sel; + sel_mux_lo_in <= dfflo_tmp; + sel_mux_hi_in <= dffhi_tmp; + sel_mux_hi_hr <= datainhi_tmp; + sel_mux_lo_hr <= dataout_hr; + + sel_mux : cyclonev_mux21 + port map ( + A => sel_mux_lo_in, + B => sel_mux_hi_in, + S => muxsel_tmp, + MO => dataout_hr + ); + + dfflo <= dfflo_tmp; + dffhi <= dffhi_tmp; + + sel_mux_hr : cyclonev_mux21 + port map ( + A => sel_mux_lo_hr, + B => sel_mux_hi_hr, + S => hrb_sel, + MO => dataout + ); +END arch; +---------------------------------------------------------------------------- +-- Module Name : cyclonev_io_pad +-- Description : Simulation model for cyclonev IO pad +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; +use IEEE.std_logic_arith.all; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; + +ENTITY cyclonev_io_pad IS + GENERIC ( + lpm_type : string := "cyclonev_io_pad"); + PORT ( + --INPUT PORTS + + padin : IN std_logic := '0'; -- Input Pad + --OUTPUT PORTS + + padout : OUT std_logic); -- Output Pad +END cyclonev_io_pad; + +ARCHITECTURE arch OF cyclonev_io_pad IS + +BEGIN + padout <= padin; +END arch; +-------------------------------------------------------------- +-- +-- Entity Name : cyclonev_bias_logic +-- +-- Description : CYCLONEV Bias Block's Logic Block +-- VHDL simulation model +-- +-------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use IEEE.std_logic_1164.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_bias_logic IS + GENERIC ( + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_shiftnld : VitalDelayType01 := DefPropDelay01; + tipd_captnupdt : VitalDelayType01 := DefPropDelay01; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks + ); + PORT ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + captnupdt : in std_logic := '0'; + mainclk : out std_logic := '0'; + updateclk : out std_logic := '0'; + capture : out std_logic := '0'; + update : out std_logic := '0' + ); + + attribute VITAL_LEVEL0 of cyclonev_bias_logic : ENTITY IS TRUE; +end cyclonev_bias_logic; + +ARCHITECTURE vital_bias_logic of cyclonev_bias_logic IS + attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE; + signal clk_ipd : std_logic := '0'; + signal shiftnld_ipd : std_logic := '0'; + signal captnupdt_ipd : std_logic := '0'; +begin + + WireDelay : block + begin + VitalWireDelay (clk_ipd, clk, tipd_clk); + VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld); + VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt); + end block; + + process (clk_ipd, shiftnld_ipd, captnupdt_ipd) + variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0'); + begin + select_tmp := captnupdt_ipd & shiftnld_ipd; + case select_tmp IS + when "10"|"11" => + mainclk <= '0'; + updateclk <= clk_ipd; + capture <= '1'; + update <= '0'; + when "01" => + mainclk <= '0'; + updateclk <= clk_ipd; + capture <= '0'; + update <= '0'; + when "00" => + mainclk <= clk_ipd; + updateclk <= '0'; + capture <= '0'; + update <= '1'; + when others => + mainclk <= '0'; + updateclk <= '0'; + capture <= '0'; + update <= '0'; + end case; + end process; + +end vital_bias_logic; + +-------------------------------------------------------------- +-- +-- Entity Name : cyclonev_bias_generator +-- +-- Description : CYCLONEV Bias Generator VHDL simulation model +-- +-------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use IEEE.std_logic_1164.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_bias_generator IS + GENERIC ( + tipd_din : VitalDelayType01 := DefPropDelay01; + tipd_mainclk : VitalDelayType01 := DefPropDelay01; + tipd_updateclk : VitalDelayType01 := DefPropDelay01; + tipd_update : VitalDelayType01 := DefPropDelay01; + tipd_capture : VitalDelayType01 := DefPropDelay01; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks + ); + PORT ( + din : in std_logic := '0'; + mainclk : in std_logic := '0'; + updateclk : in std_logic := '0'; + capture : in std_logic := '0'; + update : in std_logic := '0'; + dout : out std_logic := '0' + ); + + attribute VITAL_LEVEL0 of cyclonev_bias_generator : ENTITY IS TRUE; +end cyclonev_bias_generator; + +ARCHITECTURE vital_bias_generator of cyclonev_bias_generator IS + attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE; + CONSTANT TOTAL_REG : integer := 202; + signal din_ipd : std_logic := '0'; + signal mainclk_ipd : std_logic := '0'; + signal updateclk_ipd : std_logic := '0'; + signal update_ipd : std_logic := '0'; + signal capture_ipd : std_logic := '0'; + signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0'); + signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0'); + signal dout_tmp : std_logic := '0'; + signal i : integer := 0; + +begin + + WireDelay : block + begin + VitalWireDelay (din_ipd, din, tipd_din); + VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk); + VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk); + VitalWireDelay (update_ipd, update, tipd_update); + VitalWireDelay (capture_ipd, capture, tipd_capture); + end block; + + process (mainclk_ipd) + begin + if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then + if ((capture_ipd = '0') AND (update_ipd = '1')) then + for i in 0 to (TOTAL_REG - 1) + loop + generator_reg(i) <= update_reg(i); + end loop; + end if; + end if; + end process; + + process (updateclk_ipd) + begin + if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then + dout_tmp <= update_reg(TOTAL_REG - 1); + + if ((capture_ipd = '0') AND (update_ipd = '0')) then + for i in 1 to (TOTAL_REG - 1) + loop + update_reg(i) <= update_reg(i - 1); + end loop; + update_reg(0) <= din_ipd; + elsif ((capture_ipd = '1') AND (update_ipd = '0')) then + for i in 1 to (TOTAL_REG - 1) + loop + update_reg(i) <= generator_reg(i); + end loop; + end if; + end if; + end process; + + dout <= dout_tmp; + +end vital_bias_generator; + +-------------------------------------------------------------- +-- +-- Entity Name : cyclonev_bias_block +-- +-- Description : CYCLONEV Bias Block VHDL simulation model +-- +-------------------------------------------------------------- +LIBRARY IEEE; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +use IEEE.std_logic_1164.all; +use work.cyclonev_atom_pack.all; + +ENTITY cyclonev_bias_block IS + GENERIC ( + lpm_type : string := "cyclonev_bias_block"; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_shiftnld : VitalDelayType01 := DefPropDelay01; + tipd_captnupdt : VitalDelayType01 := DefPropDelay01; + tipd_din : VitalDelayType01 := DefPropDelay01; + tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks + ); + PORT ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + captnupdt : in std_logic := '0'; + din : in std_logic := '0'; + dout : out std_logic := '0' + ); + + attribute VITAL_LEVEL0 of cyclonev_bias_block : ENTITY IS TRUE; +end cyclonev_bias_block; + +ARCHITECTURE vital_bias_block of cyclonev_bias_block IS + + COMPONENT cyclonev_bias_logic + GENERIC ( + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_shiftnld : VitalDelayType01 := DefPropDelay01; + tipd_captnupdt : VitalDelayType01 := DefPropDelay01; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks + ); + PORT ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + captnupdt : in std_logic := '0'; + mainclk : out std_logic := '0'; + updateclk : out std_logic := '0'; + capture : out std_logic := '0'; + update : out std_logic := '0' + ); + end COMPONENT; + + COMPONENT cyclonev_bias_generator + GENERIC ( + tipd_din : VitalDelayType01 := DefPropDelay01; + tipd_mainclk : VitalDelayType01 := DefPropDelay01; + tipd_updateclk : VitalDelayType01 := DefPropDelay01; + tipd_update : VitalDelayType01 := DefPropDelay01; + tipd_capture : VitalDelayType01 := DefPropDelay01; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks + ); + PORT ( + din : in std_logic := '0'; + mainclk : in std_logic := '0'; + updateclk : in std_logic := '0'; + capture : in std_logic := '0'; + update : in std_logic := '0'; + dout : out std_logic := '0' + ); + end COMPONENT; + + signal mainclk_wire : std_logic := '0'; + signal updateclk_wire : std_logic := '0'; + signal capture_wire : std_logic := '0'; + signal update_wire : std_logic := '0'; + +begin + + logic_block : cyclonev_bias_logic + PORT MAP ( + clk => clk, + shiftnld => shiftnld, + captnupdt => captnupdt, + mainclk => mainclk_wire, + updateclk => updateclk_wire, + capture => capture_wire, + update => update_wire + ); + + bias_generator : cyclonev_bias_generator + PORT MAP ( + din => din, + mainclk => mainclk_wire, + updateclk => updateclk_wire, + capture => capture_wire, + update => update_wire, + dout => dout + ); + +end vital_bias_block; +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_clk_phase_select is + generic ( + phase_setting : integer := 0; + invert_phase : string := "dynamic"; + use_phasectrlin : string := "true"; + physical_clock_source : string := "dqs_2x_clk"; + use_dqs_input : string := "false" + ); + port ( + clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + dqsin : in std_logic := '0'; + phaseinvertctrl : in std_logic := '0'; + clkout : out std_logic; + phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0') + ); +end cyclonev_clk_phase_select; + +architecture behavior of cyclonev_clk_phase_select is + +component cyclonev_clk_phase_select_encrypted + generic ( + phase_setting : integer := 0; + invert_phase : string := "dynamic"; + use_phasectrlin : string := "true"; + physical_clock_source : string := "dqs_2x_clk"; + use_dqs_input : string := "false" + ); + port ( + clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + dqsin : in std_logic := '0'; + phaseinvertctrl : in std_logic := '0'; + clkout : out std_logic; + phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0') + ); +end component; + +begin + + +inst : cyclonev_clk_phase_select_encrypted + generic map ( + phase_setting => phase_setting, + invert_phase => invert_phase, + use_phasectrlin => use_phasectrlin, + physical_clock_source => physical_clock_source, + use_dqs_input => use_dqs_input + ) + port map ( + clkin => clkin, + dqsin => dqsin, + phaseinvertctrl => phaseinvertctrl, + clkout => clkout, + phasectrlin => phasectrlin + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_clkena is + generic ( + clock_type : string := "auto"; + ena_register_mode : string := "always enabled"; + lpm_type : string := "cyclonev_clkena"; + ena_register_power_up : string := "high"; + disable_mode : string := "low"; + test_syn : string := "high" + ); + port ( + inclk : in std_logic := '1'; + ena : in std_logic := '1'; + enaout : out std_logic; + outclk : out std_logic + ); +end cyclonev_clkena; + +architecture behavior of cyclonev_clkena is + +component cyclonev_clkena_encrypted + generic ( + clock_type : string := "auto"; + ena_register_mode : string := "always enabled"; + lpm_type : string := "cyclonev_clkena"; + ena_register_power_up : string := "high"; + disable_mode : string := "low"; + test_syn : string := "high" + ); + port ( + inclk : in std_logic; + ena : in std_logic; + enaout : out std_logic; + outclk : out std_logic + ); +end component; + +begin + + +inst : cyclonev_clkena_encrypted + generic map ( + clock_type => clock_type, + ena_register_mode => ena_register_mode, + lpm_type => lpm_type, + ena_register_power_up => ena_register_power_up, + disable_mode => disable_mode, + test_syn => test_syn + ) + port map ( + inclk => inclk, + ena => ena, + enaout => enaout, + outclk => outclk + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_clkselect is + generic ( + lpm_type : string := "cyclonev_clkselect"; + test_cff : string := "low" + ); + port ( + inclk : in std_logic_vector(3 downto 0) := "0000"; + clkselect : in std_logic_vector(1 downto 0) := "00"; + outclk : out std_logic + ); +end cyclonev_clkselect; + +architecture behavior of cyclonev_clkselect is + +component cyclonev_clkselect_encrypted + generic ( + lpm_type : string := "cyclonev_clkselect"; + test_cff : string := "low" + ); + port ( + inclk : in std_logic_vector(3 downto 0); + clkselect : in std_logic_vector(1 downto 0); + outclk : out std_logic + ); +end component; + +begin + + +inst : cyclonev_clkselect_encrypted + generic map ( + lpm_type => lpm_type, + test_cff => test_cff + ) + port map ( + inclk => inclk, + clkselect => clkselect, + outclk => outclk + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_delay_chain is + generic ( + sim_intrinsic_rising_delay : integer := 200; + sim_intrinsic_falling_delay : integer := 200; + sim_rising_delay_increment : integer := 10; + sim_falling_delay_increment : integer := 10; + lpm_type : string := "cyclonev_delay_chain" + ); + port ( + datain : in std_logic := '0'; + delayctrlin : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + dataout : out std_logic + ); +end cyclonev_delay_chain; + +architecture behavior of cyclonev_delay_chain is + +component cyclonev_delay_chain_encrypted + generic ( + sim_intrinsic_rising_delay : integer := 200; + sim_intrinsic_falling_delay : integer := 200; + sim_rising_delay_increment : integer := 10; + sim_falling_delay_increment : integer := 10; + lpm_type : string := "cyclonev_delay_chain" + ); + port ( + datain : in std_logic := '0'; + delayctrlin : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + dataout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_delay_chain_encrypted + generic map ( + sim_intrinsic_rising_delay => sim_intrinsic_rising_delay, + sim_intrinsic_falling_delay => sim_intrinsic_falling_delay, + sim_rising_delay_increment => sim_rising_delay_increment, + sim_falling_delay_increment => sim_falling_delay_increment, + lpm_type => lpm_type + ) + port map ( + datain => datain, + delayctrlin => delayctrlin, + dataout => dataout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_dll_offset_ctrl is + generic ( + use_offset : string := "false"; + static_offset : integer := 0; + use_pvt_compensation : string := "false" + ); + port ( + clk : in std_logic := '0'; + offsetdelayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + offset : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + addnsub : in std_logic := '0'; + aload : in std_logic := '0'; + offsetctrlout : out std_logic_vector(6 downto 0); + offsettestout : out std_logic_vector(6 downto 0) + ); +end cyclonev_dll_offset_ctrl; + +architecture behavior of cyclonev_dll_offset_ctrl is + +component cyclonev_dll_offset_ctrl_encrypted + generic ( + use_offset : string := "false"; + static_offset : integer := 0; + use_pvt_compensation : string := "false" + ); + port ( + clk : in std_logic := '0'; + offsetdelayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + offset : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + addnsub : in std_logic := '0'; + aload : in std_logic := '0'; + offsetctrlout : out std_logic_vector(6 downto 0); + offsettestout : out std_logic_vector(6 downto 0) + ); +end component; + +begin + + +inst : cyclonev_dll_offset_ctrl_encrypted + generic map ( + use_offset => use_offset, + static_offset => static_offset, + use_pvt_compensation => use_pvt_compensation + ) + port map ( + clk => clk, + offsetdelayctrlin => offsetdelayctrlin, + offset => offset, + addnsub => addnsub, + aload => aload, + offsetctrlout => offsetctrlout, + offsettestout => offsettestout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_dll is + generic ( + input_frequency : string := "0 MHz"; + delayctrlout_mode : string := "normal"; + jitter_reduction : string := "false"; + use_upndnin : string := "false"; + use_upndninclkena : string := "false"; + dual_phase_comparators : string := "true"; + sim_valid_lock : integer := 16; + sim_valid_lockcount : integer := 0; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10; + static_delay_ctrl : integer := 0; + lpm_type : string := "cyclonev_dll"; + lpm_hint : string := "unused"; + delay_chain_length : integer := 8 + ); + port ( + aload : in std_logic := '0'; + clk : in std_logic := '0'; + upndnin : in std_logic := '0'; + upndninclkena : in std_logic := '0'; + delayctrlout : out std_logic_vector(6 downto 0); + dqsupdate : out std_logic; + offsetdelayctrlout : out std_logic_vector(6 downto 0); + offsetdelayctrlclkout : out std_logic; + upndnout : out std_logic; + dffin : out std_logic + ); +end cyclonev_dll; + +architecture behavior of cyclonev_dll is + +component cyclonev_dll_encrypted + generic ( + input_frequency : string := "0 MHz"; + delayctrlout_mode : string := "normal"; + jitter_reduction : string := "false"; + use_upndnin : string := "false"; + use_upndninclkena : string := "false"; + dual_phase_comparators : string := "true"; + sim_valid_lock : integer := 16; + sim_valid_lockcount : integer := 0; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10; + static_delay_ctrl : integer := 0; + lpm_type : string := "cyclonev_dll"; + lpm_hint : string := "unused"; + delay_chain_length : integer := 8 + ); + port ( + aload : in std_logic := '0'; + clk : in std_logic := '0'; + upndnin : in std_logic := '0'; + upndninclkena : in std_logic := '0'; + delayctrlout : out std_logic_vector(6 downto 0); + dqsupdate : out std_logic; + offsetdelayctrlout : out std_logic_vector(6 downto 0); + offsetdelayctrlclkout : out std_logic; + upndnout : out std_logic; + dffin : out std_logic + ); +end component; + +begin + + +inst : cyclonev_dll_encrypted + generic map ( + input_frequency => input_frequency, + delayctrlout_mode => delayctrlout_mode, + jitter_reduction => jitter_reduction, + use_upndnin => use_upndnin, + use_upndninclkena => use_upndninclkena, + dual_phase_comparators => dual_phase_comparators, + sim_valid_lock => sim_valid_lock, + sim_valid_lockcount => sim_valid_lockcount, + sim_buffer_intrinsic_delay => sim_buffer_intrinsic_delay, + sim_buffer_delay_increment => sim_buffer_delay_increment, + static_delay_ctrl => static_delay_ctrl, + lpm_type => lpm_type, + lpm_hint => lpm_hint, + delay_chain_length => delay_chain_length + ) + port map ( + aload => aload, + clk => clk, + upndnin => upndnin, + upndninclkena => upndninclkena, + delayctrlout => delayctrlout, + dqsupdate => dqsupdate, + offsetdelayctrlout => offsetdelayctrlout, + offsetdelayctrlclkout => offsetdelayctrlclkout, + upndnout => upndnout, + dffin => dffin + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity cyclonev_dqs_config is + generic ( + lpm_type : string := "cyclonev_dqs_config" + ); + port ( + datain : in std_logic := '0'; + dqsenablegatingdelaysetting : out std_logic_vector(4 downto 0); + dqshalfratebypass : out std_logic; + enadqsenablephasetransferreg : out std_logic; + postamblephaseinvert : out std_logic; + dqsenableungatingdelaysetting : out std_logic_vector(4 downto 0); + octdelaysetting : out std_logic_vector(4 downto 0); + clk : in std_logic := '0'; + dqsbusoutdelaysetting : out std_logic_vector(4 downto 0); + postamblephasesetting : out std_logic_vector(1 downto 0); + ena : in std_logic := '0'; + dataout : out std_logic; + update : in std_logic := '0' + ); +end cyclonev_dqs_config; + +architecture behavior of cyclonev_dqs_config is + +component cyclonev_dqs_config_encrypted + generic ( + lpm_type : string := "cyclonev_dqs_config" + ); + port ( + datain : in std_logic := '0'; + dqsenablegatingdelaysetting : out std_logic_vector(4 downto 0); + dqshalfratebypass : out std_logic; + enadqsenablephasetransferreg : out std_logic; + postamblephaseinvert : out std_logic; + dqsenableungatingdelaysetting : out std_logic_vector(4 downto 0); + octdelaysetting : out std_logic_vector(4 downto 0); + clk : in std_logic := '0'; + dqsbusoutdelaysetting : out std_logic_vector(4 downto 0); + postamblephasesetting : out std_logic_vector(1 downto 0); + ena : in std_logic := '0'; + dataout : out std_logic; + update : in std_logic := '0' + ); +end component; + +begin + +inst : cyclonev_dqs_config_encrypted + generic map ( + lpm_type => lpm_type + ) + port map ( + datain => datain, + dqsenablegatingdelaysetting => dqsenablegatingdelaysetting, + dqshalfratebypass => dqshalfratebypass, + enadqsenablephasetransferreg => enadqsenablephasetransferreg, + postamblephaseinvert => postamblephaseinvert, + dqsenableungatingdelaysetting => dqsenableungatingdelaysetting, + octdelaysetting => octdelaysetting, + clk => clk, + dqsbusoutdelaysetting => dqsbusoutdelaysetting, + postamblephasesetting => postamblephasesetting, + ena => ena, + dataout => dataout, + update => update + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_dqs_delay_chain is + generic ( + dqs_input_frequency : string := "unused"; + dqs_phase_shift : integer := 0; + use_phasectrlin : string := "false"; + phase_setting : integer := 0; + dqs_offsetctrl_enable : string := "false"; + dqs_ctrl_latches_enable : string := "false"; + use_alternate_input_for_first_stage_delayctrl : string := "false"; + use_alternate_input_for_multi_stage_delayctrl : string := "false"; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10; + test_enable : string := "false" + ); + port ( + dqsin : in std_logic := '0'; + dqsenable : in std_logic := '1'; + delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + offsetctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + dqsupdateen : in std_logic := '1'; + phasectrlin : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + testin : in std_logic := '0'; + dffin : out std_logic; + dqsbusout : out std_logic + ); +end cyclonev_dqs_delay_chain; + +architecture behavior of cyclonev_dqs_delay_chain is + +component cyclonev_dqs_delay_chain_encrypted + generic ( + dqs_input_frequency : string := "unused"; + dqs_phase_shift : integer := 0; + use_phasectrlin : string := "false"; + phase_setting : integer := 0; + dqs_offsetctrl_enable : string := "false"; + dqs_ctrl_latches_enable : string := "false"; + use_alternate_input_for_first_stage_delayctrl : string := "false"; + use_alternate_input_for_multi_stage_delayctrl : string := "false"; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10; + test_enable : string := "false" + ); + port ( + dqsin : in std_logic := '0'; + dqsenable : in std_logic := '1'; + delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + offsetctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + dqsupdateen : in std_logic := '1'; + phasectrlin : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + testin : in std_logic := '0'; + dffin : out std_logic; + dqsbusout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_dqs_delay_chain_encrypted + generic map ( + dqs_input_frequency => dqs_input_frequency, + dqs_phase_shift => dqs_phase_shift, + use_phasectrlin => use_phasectrlin, + phase_setting => phase_setting, + dqs_offsetctrl_enable => dqs_offsetctrl_enable, + dqs_ctrl_latches_enable => dqs_ctrl_latches_enable, + use_alternate_input_for_first_stage_delayctrl => use_alternate_input_for_first_stage_delayctrl, + use_alternate_input_for_multi_stage_delayctrl => use_alternate_input_for_multi_stage_delayctrl, + sim_buffer_intrinsic_delay => sim_buffer_intrinsic_delay, + sim_buffer_delay_increment => sim_buffer_delay_increment, + test_enable => test_enable + ) + port map ( + dqsin => dqsin, + dqsenable => dqsenable, + delayctrlin => delayctrlin, + offsetctrlin => offsetctrlin, + dqsupdateen => dqsupdateen, + phasectrlin => phasectrlin, + testin => testin, + dffin => dffin, + dqsbusout => dqsbusout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_dqs_enable_ctrl is + generic ( + delay_dqs_enable_by_half_cycle : string := "false"; + add_phase_transfer_reg : string := "false" + ); + port ( + dqsenablein : in std_logic := '1'; + zerophaseclk : in std_logic := '1'; + enaphasetransferreg : in std_logic := '0'; + levelingclk : in std_logic := '1'; + dffin : out std_logic; + dffphasetransfer : out std_logic; + dffextenddqsenable : out std_logic; + dqsenableout : out std_logic + ); +end cyclonev_dqs_enable_ctrl; + +architecture behavior of cyclonev_dqs_enable_ctrl is + +component cyclonev_dqs_enable_ctrl_encrypted + generic ( + delay_dqs_enable_by_half_cycle : string := "false"; + add_phase_transfer_reg : string := "false" + ); + port ( + dqsenablein : in std_logic := '1'; + zerophaseclk : in std_logic := '1'; + enaphasetransferreg : in std_logic := '0'; + levelingclk : in std_logic := '1'; + dffin : out std_logic; + dffphasetransfer : out std_logic; + dffextenddqsenable : out std_logic; + dqsenableout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_dqs_enable_ctrl_encrypted + generic map ( + delay_dqs_enable_by_half_cycle => delay_dqs_enable_by_half_cycle, + add_phase_transfer_reg => add_phase_transfer_reg + ) + port map ( + dqsenablein => dqsenablein, + zerophaseclk => zerophaseclk, + enaphasetransferreg => enaphasetransferreg, + levelingclk => levelingclk, + dffin => dffin, + dffphasetransfer => dffphasetransfer, + dffextenddqsenable => dffextenddqsenable, + dqsenableout => dqsenableout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_duty_cycle_adjustment is + generic ( + dca_config_mode : integer := 0; + duty_cycle_delay_mode : string := "none"; + lpm_type : string := "cyclonev_duty_cycle_adjustment" + ); + port ( + clkin : in std_logic := '0'; + delaymode : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + delayctrlin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + clkout : out std_logic + ); +end cyclonev_duty_cycle_adjustment; + +architecture behavior of cyclonev_duty_cycle_adjustment is + +component cyclonev_duty_cycle_adjustment_encrypted + generic ( + dca_config_mode : integer := 0; + duty_cycle_delay_mode : string := "none"; + lpm_type : string := "cyclonev_duty_cycle_adjustment" + ); + port ( + clkin : in std_logic := '0'; + delaymode : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + delayctrlin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + clkout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_duty_cycle_adjustment_encrypted + generic map ( + dca_config_mode => dca_config_mode, + duty_cycle_delay_mode => duty_cycle_delay_mode, + lpm_type => lpm_type + ) + port map ( + clkin => clkin, + delaymode => delaymode, + delayctrlin => delayctrlin, + clkout => clkout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_fractional_pll is + generic ( + output_clock_frequency : string := ""; + reference_clock_frequency : string := ""; + mimic_fbclk_type : string := "cdb_pll_mimic_fbclk_gclk"; + dsm_accumulator_reset_value : integer := 0; + forcelock : string := "false"; + nreset_invert : string := "false"; + pll_atb : integer := 0; + pll_bwctrl : integer := 10000; + pll_cmp_buf_dly : string := "0 ps"; + pll_cp_comp : string := "true"; + pll_cp_current : integer := 20; + pll_ctrl_override_setting : string := "false"; + pll_dsm_dither : string := "disable"; + pll_dsm_out_sel : string := "disable"; + pll_dsm_reset : string := "false"; + pll_ecn_bypass : string := "false"; + pll_ecn_test_en : string := "false"; + pll_enable : string := "true"; + pll_fbclk_mux_1 : string := "glb"; + pll_fbclk_mux_2 : string := "fb_1"; + pll_fractional_carry_out : integer := 24; + pll_fractional_division : integer := 1; + pll_fractional_division_string : string := "1"; + pll_fractional_value_ready : string := "true"; + pll_lf_testen : string := "false"; + pll_lock_fltr_cfg : integer := 0; + pll_lock_fltr_test : string := "false"; + pll_m_cnt_bypass_en : string := "false"; + pll_m_cnt_coarse_dly : string := "0 ps"; + pll_m_cnt_fine_dly : string := "0 ps"; + pll_m_cnt_hi_div : integer := 1; + pll_m_cnt_in_src : string := "ph_mux_clk"; + pll_m_cnt_lo_div : integer := 1; + pll_m_cnt_odd_div_duty_en : string := "false"; + pll_m_cnt_ph_mux_prst : integer := 0; + pll_m_cnt_prst : integer := 1; + pll_n_cnt_bypass_en : string := "false"; + pll_n_cnt_coarse_dly : string := "0 ps"; + pll_n_cnt_fine_dly : string := "0 ps"; + pll_n_cnt_hi_div : integer := 1; + pll_n_cnt_lo_div : integer := 1; + pll_n_cnt_odd_div_duty_en : string := "false"; + pll_ref_buf_dly : string := "0 ps"; + pll_reg_boost : integer := 0; + pll_regulator_bypass : string := "false"; + pll_ripplecap_ctrl : integer := 0; + pll_slf_rst : string := "false"; + pll_tclk_mux_en : string := "false"; + pll_tclk_sel : string := "cdb_pll_tclk_sel_m_src"; + pll_test_enable : string := "false"; + pll_testdn_enable : string := "false"; + pll_testup_enable : string := "false"; + pll_unlock_fltr_cfg : integer := 0; + pll_vco_div : integer := 2; + pll_vco_ph0_en : string := "false"; + pll_vco_ph1_en : string := "false"; + pll_vco_ph2_en : string := "false"; + pll_vco_ph3_en : string := "false"; + pll_vco_ph4_en : string := "false"; + pll_vco_ph5_en : string := "false"; + pll_vco_ph6_en : string := "false"; + pll_vco_ph7_en : string := "false"; + pll_vctrl_test_voltage : integer := 750; + vccd0g_atb : string := "disable"; + vccd0g_output : integer := 0; + vccd1g_atb : string := "disable"; + vccd1g_output : integer := 0; + vccm1g_tap : integer := 2; + vccr_pd : string := "false"; + vcodiv_override : string := "false"; + fractional_pll_index : integer := 1 + ); + port ( + coreclkfb : in std_logic; + ecnc1test : in std_logic := '0'; + ecnc2test : in std_logic := '0'; + fbclkfpll : in std_logic := '0'; + lvdsfbin : in std_logic := '0'; + nresync : in std_logic; + pfden : in std_logic := '0'; + refclkin : in std_logic; + shift : in std_logic; + shiftdonein : in std_logic; + shiften : in std_logic; + up : in std_logic; + vsspl : in std_logic := '0'; + zdb : in std_logic := '0'; + cntnen : out std_logic; + fbclk : out std_logic; + fblvdsout : out std_logic; + lock : out std_logic; + mhi : out std_logic_vector(7 downto 0); + mcntout : out std_logic; + plniotribuf : out std_logic; + shiftdoneout : out std_logic; + tclk : out std_logic; + vcoph : out std_logic_vector(7 downto 0) + ); +end cyclonev_fractional_pll; + +architecture behavior of cyclonev_fractional_pll is + +component cyclonev_fractional_pll_encrypted + generic ( + output_clock_frequency : string := ""; + reference_clock_frequency : string := ""; + mimic_fbclk_type : string := "cdb_pll_mimic_fbclk_gclk"; + dsm_accumulator_reset_value : integer := 0; + forcelock : string := "false"; + nreset_invert : string := "false"; + pll_atb : integer := 0; + pll_bwctrl : integer := 10000; + pll_cmp_buf_dly : string := "0 ps"; + pll_cp_comp : string := "true"; + pll_cp_current : integer := 20; + pll_ctrl_override_setting : string := "false"; + pll_dsm_dither : string := "disable"; + pll_dsm_out_sel : string := "disable"; + pll_dsm_reset : string := "false"; + pll_ecn_bypass : string := "false"; + pll_ecn_test_en : string := "false"; + pll_enable : string := "true"; + pll_fbclk_mux_1 : string := "glb"; + pll_fbclk_mux_2 : string := "fb_1"; + pll_fractional_carry_out : integer := 24; + pll_fractional_division : integer := 1; + pll_fractional_division_string : string := "1"; + pll_fractional_value_ready : string := "true"; + pll_lf_testen : string := "false"; + pll_lock_fltr_cfg : integer := 0; + pll_lock_fltr_test : string := "false"; + pll_m_cnt_bypass_en : string := "false"; + pll_m_cnt_coarse_dly : string := "0 ps"; + pll_m_cnt_fine_dly : string := "0 ps"; + pll_m_cnt_hi_div : integer := 1; + pll_m_cnt_in_src : string := "ph_mux_clk"; + pll_m_cnt_lo_div : integer := 1; + pll_m_cnt_odd_div_duty_en : string := "false"; + pll_m_cnt_ph_mux_prst : integer := 0; + pll_m_cnt_prst : integer := 1; + pll_n_cnt_bypass_en : string := "false"; + pll_n_cnt_coarse_dly : string := "0 ps"; + pll_n_cnt_fine_dly : string := "0 ps"; + pll_n_cnt_hi_div : integer := 1; + pll_n_cnt_lo_div : integer := 1; + pll_n_cnt_odd_div_duty_en : string := "false"; + pll_ref_buf_dly : string := "0 ps"; + pll_reg_boost : integer := 0; + pll_regulator_bypass : string := "false"; + pll_ripplecap_ctrl : integer := 0; + pll_slf_rst : string := "false"; + pll_tclk_mux_en : string := "false"; + pll_tclk_sel : string := "cdb_pll_tclk_sel_m_src"; + pll_test_enable : string := "false"; + pll_testdn_enable : string := "false"; + pll_testup_enable : string := "false"; + pll_unlock_fltr_cfg : integer := 0; + pll_vco_div : integer := 2; + pll_vco_ph0_en : string := "false"; + pll_vco_ph1_en : string := "false"; + pll_vco_ph2_en : string := "false"; + pll_vco_ph3_en : string := "false"; + pll_vco_ph4_en : string := "false"; + pll_vco_ph5_en : string := "false"; + pll_vco_ph6_en : string := "false"; + pll_vco_ph7_en : string := "false"; + pll_vctrl_test_voltage : integer := 750; + vccd0g_atb : string := "disable"; + vccd0g_output : integer := 0; + vccd1g_atb : string := "disable"; + vccd1g_output : integer := 0; + vccm1g_tap : integer := 2; + vccr_pd : string := "false"; + vcodiv_override : string := "false"; + fractional_pll_index : integer := 1 + ); + port ( + coreclkfb : in std_logic; + ecnc1test : in std_logic := '0'; + ecnc2test : in std_logic := '0'; + fbclkfpll : in std_logic := '0'; + lvdsfbin : in std_logic; + nresync : in std_logic; + pfden : in std_logic := '0'; + refclkin : in std_logic; + shift : in std_logic; + shiftdonein : in std_logic; + shiften : in std_logic; + up : in std_logic; + vsspl : in std_logic := '0'; + zdb : in std_logic := '0'; + cntnen : out std_logic; + fbclk : out std_logic; + fblvdsout : out std_logic; + lock : out std_logic; + mhi : out std_logic_vector(7 downto 0); + mcntout : out std_logic; + plniotribuf : out std_logic; + shiftdoneout : out std_logic; + tclk : out std_logic; + vcoph : out std_logic_vector(7 downto 0) + ); +end component; + +begin + + +inst : cyclonev_fractional_pll_encrypted + generic map ( + output_clock_frequency => output_clock_frequency, + reference_clock_frequency => reference_clock_frequency, + mimic_fbclk_type => mimic_fbclk_type, + dsm_accumulator_reset_value => dsm_accumulator_reset_value, + forcelock => forcelock, + nreset_invert => nreset_invert, + pll_atb => pll_atb, + pll_bwctrl => pll_bwctrl, + pll_cmp_buf_dly => pll_cmp_buf_dly, + pll_cp_comp => pll_cp_comp, + pll_cp_current => pll_cp_current, + pll_ctrl_override_setting => pll_ctrl_override_setting, + pll_dsm_dither => pll_dsm_dither, + pll_dsm_out_sel => pll_dsm_out_sel, + pll_dsm_reset => pll_dsm_reset, + pll_ecn_bypass => pll_ecn_bypass, + pll_ecn_test_en => pll_ecn_test_en, + pll_enable => pll_enable, + pll_fbclk_mux_1 => pll_fbclk_mux_1, + pll_fbclk_mux_2 => pll_fbclk_mux_2, + pll_fractional_carry_out => pll_fractional_carry_out, + pll_fractional_division => pll_fractional_division, + pll_fractional_division_string => pll_fractional_division_string, + pll_fractional_value_ready => pll_fractional_value_ready, + pll_lf_testen => pll_lf_testen, + pll_lock_fltr_cfg => pll_lock_fltr_cfg, + pll_lock_fltr_test => pll_lock_fltr_test, + pll_m_cnt_bypass_en => pll_m_cnt_bypass_en, + pll_m_cnt_coarse_dly => pll_m_cnt_coarse_dly, + pll_m_cnt_fine_dly => pll_m_cnt_fine_dly, + pll_m_cnt_hi_div => pll_m_cnt_hi_div, + pll_m_cnt_in_src => pll_m_cnt_in_src, + pll_m_cnt_lo_div => pll_m_cnt_lo_div, + pll_m_cnt_odd_div_duty_en => pll_m_cnt_odd_div_duty_en, + pll_m_cnt_ph_mux_prst => pll_m_cnt_ph_mux_prst, + pll_m_cnt_prst => pll_m_cnt_prst, + pll_n_cnt_bypass_en => pll_n_cnt_bypass_en, + pll_n_cnt_coarse_dly => pll_n_cnt_coarse_dly, + pll_n_cnt_fine_dly => pll_n_cnt_fine_dly, + pll_n_cnt_hi_div => pll_n_cnt_hi_div, + pll_n_cnt_lo_div => pll_n_cnt_lo_div, + pll_n_cnt_odd_div_duty_en => pll_n_cnt_odd_div_duty_en, + pll_ref_buf_dly => pll_ref_buf_dly, + pll_reg_boost => pll_reg_boost, + pll_regulator_bypass => pll_regulator_bypass, + pll_ripplecap_ctrl => pll_ripplecap_ctrl, + pll_slf_rst => pll_slf_rst, + pll_tclk_mux_en => pll_tclk_mux_en, + pll_tclk_sel => pll_tclk_sel, + pll_test_enable => pll_test_enable, + pll_testdn_enable => pll_testdn_enable, + pll_testup_enable => pll_testup_enable, + pll_unlock_fltr_cfg => pll_unlock_fltr_cfg, + pll_vco_div => pll_vco_div, + pll_vco_ph0_en => pll_vco_ph0_en, + pll_vco_ph1_en => pll_vco_ph1_en, + pll_vco_ph2_en => pll_vco_ph2_en, + pll_vco_ph3_en => pll_vco_ph3_en, + pll_vco_ph4_en => pll_vco_ph4_en, + pll_vco_ph5_en => pll_vco_ph5_en, + pll_vco_ph6_en => pll_vco_ph6_en, + pll_vco_ph7_en => pll_vco_ph7_en, + pll_vctrl_test_voltage => pll_vctrl_test_voltage, + vccd0g_atb => vccd0g_atb, + vccd0g_output => vccd0g_output, + vccd1g_atb => vccd1g_atb, + vccd1g_output => vccd1g_output, + vccm1g_tap => vccm1g_tap, + vccr_pd => vccr_pd, + vcodiv_override => vcodiv_override, + fractional_pll_index => fractional_pll_index + ) + port map ( + coreclkfb => coreclkfb, + ecnc1test => ecnc1test, + ecnc2test => ecnc2test, + fbclkfpll => fbclkfpll, + lvdsfbin => lvdsfbin, + nresync => nresync, + pfden => pfden, + refclkin => refclkin, + shift => shift, + shiftdonein => shiftdonein, + shiften => shiften, + up => up, + vsspl => vsspl, + zdb => zdb, + cntnen => cntnen, + fbclk => fbclk, + fblvdsout => fblvdsout, + lock => lock, + mhi => mhi, + mcntout => mcntout, + plniotribuf => plniotribuf, + shiftdoneout => shiftdoneout, + tclk => tclk, + vcoph => vcoph + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_half_rate_input is + generic ( + power_up : string := "low"; + async_mode : string := "no_reset"; + use_dataoutbypass : string := "false" + ); + port ( + datain : in std_logic_vector(1 downto 0) := (OTHERS => '1'); + directin : in std_logic := '1'; + clk : in std_logic := '0'; + areset : in std_logic := '0'; + dataoutbypass : in std_logic := '0'; + dataout : out std_logic_vector(3 downto 0); + dffin : out std_logic_vector(1 downto 0) + ); +end cyclonev_half_rate_input; + +architecture behavior of cyclonev_half_rate_input is + +component cyclonev_half_rate_input_encrypted + generic ( + power_up : string := "low"; + async_mode : string := "no_reset"; + use_dataoutbypass : string := "false" + ); + port ( + datain : in std_logic_vector(1 downto 0) := (OTHERS => '1'); + directin : in std_logic := '1'; + clk : in std_logic := '0'; + areset : in std_logic := '0'; + dataoutbypass : in std_logic := '0'; + dataout : out std_logic_vector(3 downto 0); + dffin : out std_logic_vector(1 downto 0) + ); +end component; + +begin + + +inst : cyclonev_half_rate_input_encrypted + generic map ( + power_up => power_up, + async_mode => async_mode, + use_dataoutbypass => use_dataoutbypass + ) + port map ( + datain => datain, + directin => directin, + clk => clk, + areset => areset, + dataoutbypass => dataoutbypass, + dataout => dataout, + dffin => dffin + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_input_phase_alignment is + generic ( + power_up : string := "low"; + async_mode : string := "no_reset"; + add_input_cycle_delay : string := "false"; + bypass_output_register : string := "false"; + add_phase_transfer_reg : string := "false"; + lpm_type : string := "cyclonev_input_phase_alignment" + ); + port ( + datain : in std_logic := '1'; + levelingclk : in std_logic := '0'; + zerophaseclk : in std_logic := '0'; + areset : in std_logic := '0'; + enainputcycledelay : in std_logic := '0'; + enaphasetransferreg : in std_logic := '0'; + dataout : out std_logic; + dffin : out std_logic; + dff1t : out std_logic; + dffphasetransfer : out std_logic + ); +end cyclonev_input_phase_alignment; + +architecture behavior of cyclonev_input_phase_alignment is + +component cyclonev_input_phase_alignment_encrypted + generic ( + power_up : string := "low"; + async_mode : string := "no_reset"; + add_input_cycle_delay : string := "false"; + bypass_output_register : string := "false"; + add_phase_transfer_reg : string := "false"; + lpm_type : string := "cyclonev_input_phase_alignment" + ); + port ( + datain : in std_logic := '1'; + levelingclk : in std_logic := '0'; + zerophaseclk : in std_logic := '0'; + areset : in std_logic := '0'; + enainputcycledelay : in std_logic := '0'; + enaphasetransferreg : in std_logic := '0'; + dataout : out std_logic; + dffin : out std_logic; + dff1t : out std_logic; + dffphasetransfer : out std_logic + ); +end component; + +begin + + +inst : cyclonev_input_phase_alignment_encrypted + generic map ( + power_up => power_up, + async_mode => async_mode, + add_input_cycle_delay => add_input_cycle_delay, + bypass_output_register => bypass_output_register, + add_phase_transfer_reg => add_phase_transfer_reg, + lpm_type => lpm_type + ) + port map ( + datain => datain, + levelingclk => levelingclk, + zerophaseclk => zerophaseclk, + areset => areset, + enainputcycledelay => enainputcycledelay, + enaphasetransferreg => enaphasetransferreg, + dataout => dataout, + dffin => dffin, + dff1t => dff1t, + dffphasetransfer => dffphasetransfer + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_io_clock_divider is + generic ( + power_up : string := "low"; + invert_phase : string := "false"; + use_masterin : string := "false"; + lpm_type : string := "cyclonev_io_clock_divider" + ); + port ( + clk : in std_logic := '0'; + phaseinvertctrl : in std_logic := '0'; + masterin : in std_logic := '0'; + clkout : out std_logic; + slaveout : out std_logic + ); +end cyclonev_io_clock_divider; + +architecture behavior of cyclonev_io_clock_divider is + +component cyclonev_io_clock_divider_encrypted + generic ( + power_up : string := "low"; + invert_phase : string := "false"; + use_masterin : string := "false"; + lpm_type : string := "cyclonev_io_clock_divider" + ); + port ( + clk : in std_logic := '0'; + phaseinvertctrl : in std_logic := '0'; + masterin : in std_logic := '0'; + clkout : out std_logic; + slaveout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_io_clock_divider_encrypted + generic map ( + power_up => power_up, + invert_phase => invert_phase, + use_masterin => use_masterin, + lpm_type => lpm_type + ) + port map ( + clk => clk, + phaseinvertctrl => phaseinvertctrl, + masterin => masterin, + clkout => clkout, + slaveout => slaveout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity cyclonev_io_config is + generic ( + lpm_type : string := "cyclonev_io_config" + ); + port ( + outputenabledelaysetting : out std_logic_vector(4 downto 0); + outputhalfratebypass : out std_logic; + datain : in std_logic := '0'; + readfifomode : out std_logic_vector(2 downto 0); + readfiforeadclockselect : out std_logic_vector(1 downto 0); + padtoinputregisterdelaysetting : out std_logic_vector(4 downto 0); + clk : in std_logic := '0'; + ena : in std_logic := '0'; + outputregdelaysetting : out std_logic_vector(4 downto 0); + dataout : out std_logic; + update : in std_logic := '0' + ); +end cyclonev_io_config; + +architecture behavior of cyclonev_io_config is + +component cyclonev_io_config_encrypted + generic ( + lpm_type : string := "cyclonev_io_config" + ); + port ( + outputenabledelaysetting : out std_logic_vector(4 downto 0); + outputhalfratebypass : out std_logic; + datain : in std_logic := '0'; + readfifomode : out std_logic_vector(2 downto 0); + readfiforeadclockselect : out std_logic_vector(1 downto 0); + padtoinputregisterdelaysetting : out std_logic_vector(4 downto 0); + clk : in std_logic := '0'; + ena : in std_logic := '0'; + outputregdelaysetting : out std_logic_vector(4 downto 0); + dataout : out std_logic; + update : in std_logic := '0' + ); +end component; + +begin + +inst : cyclonev_io_config_encrypted + generic map ( + lpm_type => lpm_type + ) + port map ( + outputenabledelaysetting => outputenabledelaysetting, + outputhalfratebypass => outputhalfratebypass, + datain => datain, + readfifomode => readfifomode, + readfiforeadclockselect => readfiforeadclockselect, + padtoinputregisterdelaysetting => padtoinputregisterdelaysetting, + clk => clk, + ena => ena, + outputregdelaysetting => outputregdelaysetting, + dataout => dataout, + update => update + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_leveling_delay_chain is + generic ( + physical_clock_source : string := "dqs"; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10 + ); + port ( + clkin : in std_logic := '0'; + delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + clkout : out std_logic_vector(3 downto 0) + ); +end cyclonev_leveling_delay_chain; + +architecture behavior of cyclonev_leveling_delay_chain is + +component cyclonev_leveling_delay_chain_encrypted + generic ( + physical_clock_source : string := "dqs"; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10 + ); + port ( + clkin : in std_logic := '0'; + delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + clkout : out std_logic_vector(3 downto 0) + ); +end component; + +begin + + +inst : cyclonev_leveling_delay_chain_encrypted + generic map ( + physical_clock_source => physical_clock_source, + sim_buffer_intrinsic_delay => sim_buffer_intrinsic_delay, + sim_buffer_delay_increment => sim_buffer_delay_increment + ) + port map ( + clkin => clkin, + delayctrlin => delayctrlin, + clkout => clkout + ); + + +end behavior; + + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_mem_phy is + generic ( + hphy_use_hphy : string := "true"; + hphy_reset_delay_en : string := "false"; + hphy_hhp_hps : string := "false"; + hphy_wrap_back_en : string := "false"; + hphy_datapath_delay : string := "zero_cycles"; + hphy_datapath_ac_delay : string := "zero_cycles"; + m_hphy_ac_rom_init_file : string := "ac_ROM.hex"; + hphy_ac_ddr_disable : string := "true"; + hphy_csr_pipelineglobalenable : string := "true"; + m_hphy_inst_rom_init_file : string := "inst_ROM.hex"; + hphy_atpg_en : string := "false" + ); + port ( + iointaddrdout : in std_logic_vector(63 downto 0) := (OTHERS => '0'); + iointresetndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointckedout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirlat : out std_logic_vector(4 downto 0); + iointdqoe : in std_logic_vector(89 downto 0) := (OTHERS => '0'); + afiaddr : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + cfgtwr : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afidm : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiwdatavalid : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + avlread : in std_logic := '0'; + phyddiockndout : out std_logic_vector(3 downto 0); + iointckndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointbadout : in std_logic_vector(11 downto 0) := (OTHERS => '0'); + cfgdevicewidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + cfgcoladdrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointdqdin : out std_logic_vector(179 downto 0); + scanen : in std_logic := '0'; + afiwlat : out std_logic_vector(3 downto 0); + phyddiodqsoe : out std_logic_vector(9 downto 0); + cfgaddlat : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirdataen : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + phyddiodqslogicincrdataen : out std_logic_vector(9 downto 0); + phyddiodqslogicoct : out std_logic_vector(9 downto 0); + iointdqsoe : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicaclrpstamble : out std_logic_vector(4 downto 0); + phyddiodqsboe : out std_logic_vector(9 downto 0); + phyddiodqdout : out std_logic_vector(179 downto 0); + iointaficalfail : out std_logic; + avlwritedata : in std_logic_vector(31 downto 0) := (OTHERS => '0'); + iointdqsboe : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicreadlatency : out std_logic_vector(24 downto 0); + iointwendout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + afiodt : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + iointcsndout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiorasndout : out std_logic_vector(3 downto 0); + phyddiocsndout : out std_logic_vector(7 downto 0); + iointdqslogicoct : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + softresetn : in std_logic := '0'; + phyddiodqsdout : out std_logic_vector(19 downto 0); + iointafiwlat : out std_logic_vector(3 downto 0); + iointdqslogicdqsena : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiba : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + phyddiodqslogicdqsena : out std_logic_vector(9 downto 0); + pllavlclk : in std_logic := '0'; + aficasn : in std_logic := '0'; + cfgbankaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiowendout : out std_logic_vector(3 downto 0); + phyddiockedout : out std_logic_vector(7 downto 0); + cfgdramconfig : in std_logic_vector(23 downto 0) := (OTHERS => '0'); + aficsn : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + avlwaitrequest : out std_logic; + phyddioodtdout : out std_logic_vector(7 downto 0); + ddiophydqslogicrdatavalid : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + avlwrite : in std_logic := '0'; + afirasn : in std_logic := '0'; + plladdrcmdclk : in std_logic := '0'; + phyddioaddrdout : out std_logic_vector(63 downto 0); + aficalfail : out std_logic; + afimemclkdisable : in std_logic := '0'; + afiwdata : in std_logic_vector(79 downto 0) := (OTHERS => '0'); + iointdqslogicreadlatency : in std_logic_vector(24 downto 0) := (OTHERS => '0'); + phyddiodmdout : out std_logic_vector(19 downto 0); + pllaficlk : in std_logic := '0'; + cfgtrfc : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointckdout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + aficke : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + iointrasndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + phyddioresetndout : out std_logic_vector(3 downto 0); + aficalsuccess : out std_logic; + ddiophydqdin : in std_logic_vector(179 downto 0) := (OTHERS => '0'); + iointcasndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointdqsdout : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + cfgcsaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiockdout : out std_logic_vector(3 downto 0); + avlreaddata : out std_logic_vector(31 downto 0); + afirdata : out std_logic_vector(79 downto 0); + phyresetn : out std_logic; + iointdqslogicincrdataen : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiwen : in std_logic := '0'; + globalresetn : in std_logic := '0'; + phyddiodqsbdout : out std_logic_vector(19 downto 0); + plllocked : in std_logic := '0'; + phyddiodqslogicfiforeset : out std_logic_vector(4 downto 0); + iointdqslogicfiforeset : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + iointodtdout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointafirlat : out std_logic_vector(4 downto 0); + iointaficalsuccess : out std_logic; + iointdqdout : in std_logic_vector(179 downto 0) := (OTHERS => '0'); + cfgrowaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiodqslogicaclrfifoctrl : out std_logic_vector(4 downto 0); + phyddiobadout : out std_logic_vector(11 downto 0); + afirdatavalid : out std_logic; + cfgtrefi : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + cfgcaswrlat : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirstn : in std_logic := '0'; + avlresetn : in std_logic := '0'; + iointdqsbdout : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + phyddiodqoe : out std_logic_vector(89 downto 0); + iointdqslogicrdatavalid : out std_logic_vector(4 downto 0); + avladdress : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + afidqsburst : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + iointdqslogicincwrptr : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicincwrptr : out std_logic_vector(9 downto 0); + cfgtcl : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + ctlresetn : out std_logic; + cfginterfacewidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiocasndout : out std_logic_vector(3 downto 0); + afirdataenfull : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + cfgtmrd : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointdmdout : in std_logic_vector(19 downto 0) := (OTHERS => '0') + ); +end cyclonev_mem_phy; + +architecture behavior of cyclonev_mem_phy is + +component cyclonev_mem_phy_encrypted + generic ( + hphy_use_hphy : string := "true"; + hphy_reset_delay_en : string := "false"; + hphy_hhp_hps : string := "false"; + hphy_wrap_back_en : string := "false"; + hphy_datapath_delay : string := "zero_cycles"; + hphy_datapath_ac_delay : string := "zero_cycles"; + m_hphy_ac_rom_init_file : string := "ac_ROM.hex"; + hphy_ac_ddr_disable : string := "true"; + hphy_csr_pipelineglobalenable : string := "true"; + m_hphy_inst_rom_init_file : string := "inst_ROM.hex"; + hphy_atpg_en : string := "false" + ); + port ( + iointaddrdout : in std_logic_vector(63 downto 0) := (OTHERS => '0'); + iointresetndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointckedout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirlat : out std_logic_vector(4 downto 0); + iointdqoe : in std_logic_vector(89 downto 0) := (OTHERS => '0'); + afiaddr : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + cfgtwr : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afidm : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiwdatavalid : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + avlread : in std_logic := '0'; + phyddiockndout : out std_logic_vector(3 downto 0); + iointckndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointbadout : in std_logic_vector(11 downto 0) := (OTHERS => '0'); + cfgdevicewidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + cfgcoladdrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointdqdin : out std_logic_vector(179 downto 0); + scanen : in std_logic := '0'; + afiwlat : out std_logic_vector(3 downto 0); + phyddiodqsoe : out std_logic_vector(9 downto 0); + cfgaddlat : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirdataen : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + phyddiodqslogicincrdataen : out std_logic_vector(9 downto 0); + phyddiodqslogicoct : out std_logic_vector(9 downto 0); + iointdqsoe : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicaclrpstamble : out std_logic_vector(4 downto 0); + phyddiodqsboe : out std_logic_vector(9 downto 0); + phyddiodqdout : out std_logic_vector(179 downto 0); + iointaficalfail : out std_logic; + avlwritedata : in std_logic_vector(31 downto 0) := (OTHERS => '0'); + iointdqsboe : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicreadlatency : out std_logic_vector(24 downto 0); + iointwendout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + afiodt : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + iointcsndout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiorasndout : out std_logic_vector(3 downto 0); + phyddiocsndout : out std_logic_vector(7 downto 0); + iointdqslogicoct : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + softresetn : in std_logic := '0'; + phyddiodqsdout : out std_logic_vector(19 downto 0); + iointafiwlat : out std_logic_vector(3 downto 0); + iointdqslogicdqsena : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiba : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + phyddiodqslogicdqsena : out std_logic_vector(9 downto 0); + pllavlclk : in std_logic := '0'; + aficasn : in std_logic := '0'; + cfgbankaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiowendout : out std_logic_vector(3 downto 0); + phyddiockedout : out std_logic_vector(7 downto 0); + cfgdramconfig : in std_logic_vector(23 downto 0) := (OTHERS => '0'); + aficsn : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + avlwaitrequest : out std_logic; + phyddioodtdout : out std_logic_vector(7 downto 0); + ddiophydqslogicrdatavalid : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + avlwrite : in std_logic := '0'; + afirasn : in std_logic := '0'; + plladdrcmdclk : in std_logic := '0'; + phyddioaddrdout : out std_logic_vector(63 downto 0); + aficalfail : out std_logic; + afimemclkdisable : in std_logic := '0'; + afiwdata : in std_logic_vector(79 downto 0) := (OTHERS => '0'); + iointdqslogicreadlatency : in std_logic_vector(24 downto 0) := (OTHERS => '0'); + phyddiodmdout : out std_logic_vector(19 downto 0); + pllaficlk : in std_logic := '0'; + cfgtrfc : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointckdout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + aficke : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + iointrasndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + phyddioresetndout : out std_logic_vector(3 downto 0); + aficalsuccess : out std_logic; + ddiophydqdin : in std_logic_vector(179 downto 0) := (OTHERS => '0'); + iointcasndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointdqsdout : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + cfgcsaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiockdout : out std_logic_vector(3 downto 0); + avlreaddata : out std_logic_vector(31 downto 0); + afirdata : out std_logic_vector(79 downto 0); + phyresetn : out std_logic; + iointdqslogicincrdataen : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiwen : in std_logic := '0'; + globalresetn : in std_logic := '0'; + phyddiodqsbdout : out std_logic_vector(19 downto 0); + plllocked : in std_logic := '0'; + phyddiodqslogicfiforeset : out std_logic_vector(4 downto 0); + iointdqslogicfiforeset : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + iointodtdout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointafirlat : out std_logic_vector(4 downto 0); + iointaficalsuccess : out std_logic; + iointdqdout : in std_logic_vector(179 downto 0) := (OTHERS => '0'); + cfgrowaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiodqslogicaclrfifoctrl : out std_logic_vector(4 downto 0); + phyddiobadout : out std_logic_vector(11 downto 0); + afirdatavalid : out std_logic; + cfgtrefi : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + cfgcaswrlat : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirstn : in std_logic := '0'; + avlresetn : in std_logic := '0'; + iointdqsbdout : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + phyddiodqoe : out std_logic_vector(89 downto 0); + iointdqslogicrdatavalid : out std_logic_vector(4 downto 0); + avladdress : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + afidqsburst : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + iointdqslogicincwrptr : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicincwrptr : out std_logic_vector(9 downto 0); + cfgtcl : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + ctlresetn : out std_logic; + cfginterfacewidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiocasndout : out std_logic_vector(3 downto 0); + afirdataenfull : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + cfgtmrd : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointdmdout : in std_logic_vector(19 downto 0) := (OTHERS => '0') + ); +end component; + +begin + +inst : cyclonev_mem_phy_encrypted + generic map ( + hphy_use_hphy => hphy_use_hphy, + hphy_reset_delay_en => hphy_reset_delay_en, + hphy_hhp_hps => hphy_hhp_hps, + hphy_wrap_back_en => hphy_wrap_back_en, + hphy_datapath_delay => hphy_datapath_delay, + hphy_datapath_ac_delay => hphy_datapath_ac_delay, + m_hphy_ac_rom_init_file => m_hphy_ac_rom_init_file, + hphy_ac_ddr_disable => hphy_ac_ddr_disable, + hphy_csr_pipelineglobalenable => hphy_csr_pipelineglobalenable, + m_hphy_inst_rom_init_file => m_hphy_inst_rom_init_file, + hphy_atpg_en => hphy_atpg_en + ) + port map ( + iointaddrdout => iointaddrdout, + iointresetndout => iointresetndout, + iointckedout => iointckedout, + afirlat => afirlat, + iointdqoe => iointdqoe, + afiaddr => afiaddr, + cfgtwr => cfgtwr, + afidm => afidm, + afiwdatavalid => afiwdatavalid, + avlread => avlread, + phyddiockndout => phyddiockndout, + iointckndout => iointckndout, + iointbadout => iointbadout, + cfgdevicewidth => cfgdevicewidth, + cfgcoladdrwidth => cfgcoladdrwidth, + iointdqdin => iointdqdin, + scanen => scanen, + afiwlat => afiwlat, + phyddiodqsoe => phyddiodqsoe, + cfgaddlat => cfgaddlat, + afirdataen => afirdataen, + phyddiodqslogicincrdataen => phyddiodqslogicincrdataen, + phyddiodqslogicoct => phyddiodqslogicoct, + iointdqsoe => iointdqsoe, + phyddiodqslogicaclrpstamble => phyddiodqslogicaclrpstamble, + phyddiodqsboe => phyddiodqsboe, + phyddiodqdout => phyddiodqdout, + iointaficalfail => iointaficalfail, + avlwritedata => avlwritedata, + iointdqsboe => iointdqsboe, + phyddiodqslogicreadlatency => phyddiodqslogicreadlatency, + iointwendout => iointwendout, + afiodt => afiodt, + iointcsndout => iointcsndout, + phyddiorasndout => phyddiorasndout, + phyddiocsndout => phyddiocsndout, + iointdqslogicoct => iointdqslogicoct, + softresetn => softresetn, + phyddiodqsdout => phyddiodqsdout, + iointafiwlat => iointafiwlat, + iointdqslogicdqsena => iointdqslogicdqsena, + afiba => afiba, + phyddiodqslogicdqsena => phyddiodqslogicdqsena, + pllavlclk => pllavlclk, + aficasn => aficasn, + cfgbankaddrwidth => cfgbankaddrwidth, + phyddiowendout => phyddiowendout, + phyddiockedout => phyddiockedout, + cfgdramconfig => cfgdramconfig, + aficsn => aficsn, + avlwaitrequest => avlwaitrequest, + phyddioodtdout => phyddioodtdout, + ddiophydqslogicrdatavalid => ddiophydqslogicrdatavalid, + avlwrite => avlwrite, + afirasn => afirasn, + plladdrcmdclk => plladdrcmdclk, + phyddioaddrdout => phyddioaddrdout, + aficalfail => aficalfail, + afimemclkdisable => afimemclkdisable, + afiwdata => afiwdata, + iointdqslogicreadlatency => iointdqslogicreadlatency, + phyddiodmdout => phyddiodmdout, + pllaficlk => pllaficlk, + cfgtrfc => cfgtrfc, + iointckdout => iointckdout, + aficke => aficke, + iointrasndout => iointrasndout, + phyddioresetndout => phyddioresetndout, + aficalsuccess => aficalsuccess, + ddiophydqdin => ddiophydqdin, + iointcasndout => iointcasndout, + iointdqsdout => iointdqsdout, + cfgcsaddrwidth => cfgcsaddrwidth, + phyddiockdout => phyddiockdout, + avlreaddata => avlreaddata, + afirdata => afirdata, + phyresetn => phyresetn, + iointdqslogicincrdataen => iointdqslogicincrdataen, + afiwen => afiwen, + globalresetn => globalresetn, + phyddiodqsbdout => phyddiodqsbdout, + plllocked => plllocked, + phyddiodqslogicfiforeset => phyddiodqslogicfiforeset, + iointdqslogicfiforeset => iointdqslogicfiforeset, + iointodtdout => iointodtdout, + iointafirlat => iointafirlat, + iointaficalsuccess => iointaficalsuccess, + iointdqdout => iointdqdout, + cfgrowaddrwidth => cfgrowaddrwidth, + phyddiodqslogicaclrfifoctrl => phyddiodqslogicaclrfifoctrl, + phyddiobadout => phyddiobadout, + afirdatavalid => afirdatavalid, + cfgtrefi => cfgtrefi, + cfgcaswrlat => cfgcaswrlat, + afirstn => afirstn, + avlresetn => avlresetn, + iointdqsbdout => iointdqsbdout, + phyddiodqoe => phyddiodqoe, + iointdqslogicrdatavalid => iointdqslogicrdatavalid, + avladdress => avladdress, + afidqsburst => afidqsburst, + iointdqslogicincwrptr => iointdqslogicincwrptr, + phyddiodqslogicincwrptr => phyddiodqslogicincwrptr, + cfgtcl => cfgtcl, + ctlresetn => ctlresetn, + cfginterfacewidth => cfginterfacewidth, + phyddiocasndout => phyddiocasndout, + afirdataenfull => afirdataenfull, + cfgtmrd => cfgtmrd, + iointdmdout => iointdmdout + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_phy_clkbuf is + port ( + outclk : out std_logic_vector(3 downto 0); + inclk : in std_logic_vector(3 downto 0) := (OTHERS => '0') + ); +end cyclonev_phy_clkbuf; + +architecture behavior of cyclonev_phy_clkbuf is + +component cyclonev_phy_clkbuf_encrypted + port ( + outclk : out std_logic_vector(3 downto 0); + inclk : in std_logic_vector(3 downto 0) := (OTHERS => '0') + ); +end component; + +begin + +inst : cyclonev_phy_clkbuf_encrypted + port map ( + outclk => outclk, + inclk => inclk + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_output_alignment is + generic ( + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + add_output_cycle_delay : string := "false"; + add_2nd_output_cycle_delay : string := "false"; + add_phase_transfer_reg : string := "false"; + bypass_output_register : string := "false" + ); + port ( + datain : in std_logic := '1'; + clk : in std_logic := '0'; + areset : in std_logic := '0'; + sreset : in std_logic := '0'; + enaoutputcycledelay : in std_logic := '0'; + ena2ndoutputcycledelay : in std_logic := '0'; + enaphasetransferreg : in std_logic := '0'; + dataout : out std_logic; + dffin : out std_logic; + dff1t : out std_logic; + dff2t : out std_logic; + dffphasetransfer : out std_logic + ); +end cyclonev_output_alignment; + +architecture behavior of cyclonev_output_alignment is + +component cyclonev_output_alignment_encrypted + generic ( + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + add_output_cycle_delay : string := "false"; + add_2nd_output_cycle_delay : string := "false"; + add_phase_transfer_reg : string := "false"; + bypass_output_register : string := "false" + ); + port ( + datain : in std_logic := '1'; + clk : in std_logic := '0'; + areset : in std_logic := '0'; + sreset : in std_logic := '0'; + enaoutputcycledelay : in std_logic := '0'; + ena2ndoutputcycledelay : in std_logic := '0'; + enaphasetransferreg : in std_logic := '0'; + dataout : out std_logic; + dffin : out std_logic; + dff1t : out std_logic; + dff2t : out std_logic; + dffphasetransfer : out std_logic + ); +end component; + +begin + + +inst : cyclonev_output_alignment_encrypted + generic map ( + power_up => power_up, + async_mode => async_mode, + sync_mode => sync_mode, + add_output_cycle_delay => add_output_cycle_delay, + add_2nd_output_cycle_delay => add_2nd_output_cycle_delay, + add_phase_transfer_reg => add_phase_transfer_reg, + bypass_output_register => bypass_output_register + ) + port map ( + datain => datain, + clk => clk, + areset => areset, + sreset => sreset, + enaoutputcycledelay => enaoutputcycledelay, + ena2ndoutputcycledelay => ena2ndoutputcycledelay, + enaphasetransferreg => enaphasetransferreg, + dataout => dataout, + dffin => dffin, + dff1t => dff1t, + dff2t => dff2t, + dffphasetransfer => dffphasetransfer + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_dll_output is + generic ( + pll_dll_src : string := "vss" + ); + port ( + cclk : in std_logic_vector(17 downto 0); + clkin : in std_logic_vector(3 downto 0) := "0000"; + clkout : out std_logic + ); +end cyclonev_pll_dll_output; + +architecture behavior of cyclonev_pll_dll_output is + +component cyclonev_pll_dll_output_encrypted + generic ( + pll_dll_src : string := "vss" + ); + port ( + cclk : in std_logic_vector(17 downto 0); + clkin : in std_logic_vector(3 downto 0); + clkout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_pll_dll_output_encrypted + generic map ( + pll_dll_src => pll_dll_src + ) + port map ( + cclk => cclk, + clkin => clkin, + clkout => clkout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_dpa_output is + generic ( + output_clock_frequency : string := ""; + pll_vcoph_div : integer := 1 + ); + port ( + pd : in std_logic; + phin : in std_logic_vector(7 downto 0); + phout : out std_logic_vector(7 downto 0) + ); +end cyclonev_pll_dpa_output; + +architecture behavior of cyclonev_pll_dpa_output is + +component cyclonev_pll_dpa_output_encrypted + generic ( + output_clock_frequency : string := ""; + pll_vcoph_div : integer := 1 + ); + port ( + pd : in std_logic; + phin : in std_logic_vector(7 downto 0); + phout : out std_logic_vector(7 downto 0) + ); +end component; + +begin + + +inst : cyclonev_pll_dpa_output_encrypted + generic map ( + output_clock_frequency => output_clock_frequency, + pll_vcoph_div => pll_vcoph_div + ) + port map ( + pd => pd, + phin => phin, + phout => phout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_extclk_output is + generic ( + pll_extclk_cnt_src : string := "vss"; + pll_extclk_enable : string := "true"; + pll_extclk_invert : string := "false" + ); + port ( + cclk : in std_logic_vector(17 downto 0); + clken : in std_logic := '0'; + mcnt0 : in std_logic := '0'; + mcnt1 : in std_logic := '0'; + extclk : out std_logic + ); +end cyclonev_pll_extclk_output; + +architecture behavior of cyclonev_pll_extclk_output is + +component cyclonev_pll_extclk_output_encrypted + generic ( + pll_extclk_cnt_src : string := "vss"; + pll_extclk_enable : string := "true"; + pll_extclk_invert : string := "false" + ); + port ( + cclk : in std_logic_vector(17 downto 0); + clken : in std_logic; + mcnt0 : in std_logic; + mcnt1 : in std_logic; + extclk : out std_logic + ); +end component; + +begin + + +inst : cyclonev_pll_extclk_output_encrypted + generic map ( + pll_extclk_cnt_src => pll_extclk_cnt_src, + pll_extclk_enable => pll_extclk_enable, + pll_extclk_invert => pll_extclk_invert + ) + port map ( + cclk => cclk, + clken => clken, + mcnt0 => mcnt0, + mcnt1 => mcnt1, + extclk => extclk + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_lvds_output is + generic ( + pll_loaden_coarse_dly : string := "0 ps"; + pll_loaden_fine_dly : string := "0 ps"; + pll_lvdsclk_coarse_dly : string := "0 ps"; + pll_lvdsclk_fine_dly : string := "0 ps"; + pll_loaden_enable_disable : string := "false"; + pll_lvdsclk_enable_disable : string := "false" + ); + port ( + ccout : in std_logic_vector(1 downto 0); + loaden : out std_logic; + lvdsclk : out std_logic + ); +end cyclonev_pll_lvds_output; + +architecture behavior of cyclonev_pll_lvds_output is + +component cyclonev_pll_lvds_output_encrypted + generic ( + pll_loaden_coarse_dly : string := "0 ps"; + pll_loaden_fine_dly : string := "0 ps"; + pll_lvdsclk_coarse_dly : string := "0 ps"; + pll_lvdsclk_fine_dly : string := "0 ps"; + pll_loaden_enable_disable : string := "false"; + pll_lvdsclk_enable_disable : string := "false" + ); + port ( + ccout : in std_logic_vector(1 downto 0); + loaden : out std_logic; + lvdsclk : out std_logic + ); +end component; + +begin + + +inst : cyclonev_pll_lvds_output_encrypted + generic map ( + pll_loaden_coarse_dly => pll_loaden_coarse_dly, + pll_loaden_fine_dly => pll_loaden_fine_dly, + pll_lvdsclk_coarse_dly => pll_lvdsclk_coarse_dly, + pll_lvdsclk_fine_dly => pll_lvdsclk_fine_dly, + pll_loaden_enable_disable => pll_loaden_enable_disable, + pll_lvdsclk_enable_disable => pll_lvdsclk_enable_disable + ) + port map ( + ccout => ccout, + loaden => loaden, + lvdsclk => lvdsclk + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_output_counter is + generic ( + duty_cycle : integer := 50; + output_clock_frequency : string := ""; + phase_shift : string := ""; + c_cnt_coarse_dly : string := "0 ps"; + c_cnt_fine_dly : string := "0 ps"; + c_cnt_in_src : string := "test_clk0"; + c_cnt_ph_mux_prst : integer := 0; + cnt_fpll_src : string := "fpll_0"; + c_cnt_prst : integer := 1; + dprio0_cnt_bypass_en : string := "false"; + dprio0_cnt_hi_div : integer := 1; + dprio0_cnt_lo_div : integer := 1; + dprio0_cnt_odd_div_even_duty_en : string := "false"; + fractional_pll_index : integer := 1; + output_counter_index : integer := 1 + ); + port ( + cascadein : in std_logic := '0'; + nen0 : in std_logic := '0'; + shift0 : in std_logic := '0'; + shiftdone0i : in std_logic := '0'; + shiften : in std_logic := '0'; + tclk0 : in std_logic := '0'; + up0 : in std_logic := '0'; + vco0ph : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + cascadeout : out std_logic; + divclk : out std_logic; + shiftdone0o : out std_logic + ); +end cyclonev_pll_output_counter; + +architecture behavior of cyclonev_pll_output_counter is + +component cyclonev_pll_output_counter_encrypted + generic ( + duty_cycle : integer := 50; + output_clock_frequency : string := ""; + phase_shift : string := ""; + c_cnt_coarse_dly : string := "0 ps"; + c_cnt_fine_dly : string := "0 ps"; + c_cnt_in_src : string := "test_clk0"; + c_cnt_ph_mux_prst : integer := 0; + cnt_fpll_src : string := "fpll_0"; + c_cnt_prst : integer := 1; + dprio0_cnt_bypass_en : string := "false"; + dprio0_cnt_hi_div : integer := 1; + dprio0_cnt_lo_div : integer := 1; + dprio0_cnt_odd_div_even_duty_en : string := "false"; + fractional_pll_index : integer := 1; + output_counter_index : integer := 1 + ); + port ( + cascadein : in std_logic := '0'; + nen0 : in std_logic := '0'; + shift0 : in std_logic := '0'; + shiftdone0i : in std_logic := '0'; + shiften : in std_logic := '0'; + tclk0 : in std_logic := '0'; + up0 : in std_logic := '0'; + vco0ph : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + cascadeout : out std_logic; + divclk : out std_logic; + shiftdone0o : out std_logic + ); +end component; + +begin + + +inst : cyclonev_pll_output_counter_encrypted + generic map ( + duty_cycle => duty_cycle, + output_clock_frequency => output_clock_frequency, + phase_shift => phase_shift, + c_cnt_coarse_dly => c_cnt_coarse_dly, + c_cnt_fine_dly => c_cnt_fine_dly, + c_cnt_in_src => c_cnt_in_src, + c_cnt_ph_mux_prst => c_cnt_ph_mux_prst, + cnt_fpll_src => cnt_fpll_src, + c_cnt_prst => c_cnt_prst, + dprio0_cnt_bypass_en => dprio0_cnt_bypass_en, + dprio0_cnt_hi_div => dprio0_cnt_hi_div, + dprio0_cnt_lo_div => dprio0_cnt_lo_div, + dprio0_cnt_odd_div_even_duty_en => dprio0_cnt_odd_div_even_duty_en, + fractional_pll_index => fractional_pll_index, + output_counter_index => output_counter_index + ) + port map ( + cascadein => cascadein, + nen0 => nen0, + shift0 => shift0, + shiftdone0i => shiftdone0i, + shiften => shiften, + tclk0 => tclk0, + up0 => up0, + vco0ph => vco0ph, + cascadeout => cascadeout, + divclk => divclk, + shiftdone0o => shiftdone0o + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_reconfig is + generic ( + fractional_pll_index : integer := 1 + ); + port ( + addr : in std_logic_vector(5 downto 0) := (OTHERS => '0'); + atpgmode : in std_logic := '0'; + byteen : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + clk : in std_logic := '0'; + cntnen : in std_logic := '0'; + cntsel : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + din : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + fpllcsrtest : in std_logic := '0'; + iocsrclkin : in std_logic := '0'; + iocsrdatain : in std_logic := '0'; + iocsren : in std_logic := '0'; + iocsrrstn : in std_logic := '0'; + mdiodis : in std_logic := '0'; + mhi : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phaseen : in std_logic := '0'; + read : in std_logic := '0'; + rstn : in std_logic := '0'; + scanen : in std_logic := '0'; + sershiftload : in std_logic := '0'; + shiftdonei : in std_logic := '0'; + updn : in std_logic := '0'; + write : in std_logic := '0'; + blockselect : out std_logic; + dout : out std_logic_vector(15 downto 0); + dprioout : out std_logic_vector(815 downto 0); + iocsrdataout : out std_logic; + iocsrenbuf : out std_logic; + iocsrrstnbuf : out std_logic; + phasedone : out std_logic; + shift : out std_logic; + shiften : out std_logic_vector(8 downto 0); + shiftenm : out std_logic; + up : out std_logic + ); +end cyclonev_pll_reconfig; + +architecture behavior of cyclonev_pll_reconfig is + +component cyclonev_pll_reconfig_encrypted + generic ( + fractional_pll_index : integer := 1 + ); + port ( + addr : in std_logic_vector(5 downto 0) := (OTHERS => '0'); + atpgmode : in std_logic := '0'; + byteen : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + clk : in std_logic := '0'; + cntnen : in std_logic := '0'; + cntsel : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + din : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + fpllcsrtest : in std_logic := '0'; + iocsrclkin : in std_logic := '0'; + iocsrdatain : in std_logic := '0'; + iocsren : in std_logic := '0'; + iocsrrstn : in std_logic := '0'; + mdiodis : in std_logic := '0'; + mhi : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phaseen : in std_logic := '0'; + read : in std_logic := '0'; + rstn : in std_logic := '0'; + scanen : in std_logic := '0'; + sershiftload : in std_logic := '0'; + shiftdonei : in std_logic := '0'; + updn : in std_logic := '0'; + write : in std_logic := '0'; + blockselect : out std_logic; + dout : out std_logic_vector(15 downto 0); + dprioout : out std_logic_vector(815 downto 0); + iocsrdataout : out std_logic; + iocsrenbuf : out std_logic; + iocsrrstnbuf : out std_logic; + phasedone : out std_logic; + shift : out std_logic; + shiften : out std_logic_vector(8 downto 0); + shiftenm : out std_logic; + up : out std_logic + ); +end component; + +begin + + +inst : cyclonev_pll_reconfig_encrypted + generic map ( + fractional_pll_index => fractional_pll_index + ) + port map ( + addr => addr, + atpgmode => atpgmode, + byteen => byteen, + clk => clk, + cntnen => cntnen, + cntsel => cntsel, + din => din, + fpllcsrtest => fpllcsrtest, + iocsrclkin => iocsrclkin, + iocsrdatain => iocsrdatain, + iocsren => iocsren, + iocsrrstn => iocsrrstn, + mdiodis => mdiodis, + mhi => mhi, + phaseen => phaseen, + read => read, + rstn => rstn, + scanen => scanen, + sershiftload => sershiftload, + shiftdonei => shiftdonei, + updn => updn, + write => write, + blockselect => blockselect, + dout => dout, + dprioout => dprioout, + iocsrdataout => iocsrdataout, + iocsrenbuf => iocsrenbuf, + iocsrrstnbuf => iocsrrstnbuf, + phasedone => phasedone, + shift => shift, + shiften => shiften, + shiftenm => shiftenm, + up => up + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_refclk_select is + generic ( + pll_auto_clk_sw_en : string := "false"; + pll_clk_loss_edge : string := "both_edges"; + pll_clk_loss_sw_en : string := "false"; + pll_clk_sw_dly : integer := 0; + pll_clkin_0_src : string := "ref_clk0"; + pll_clkin_1_src : string := "ref_clk1"; + pll_manu_clk_sw_en : string := "false"; + pll_sw_refclk_src : string := "clk_0" + ); + port ( + adjpllin : in std_logic := '0'; + cclk : in std_logic := '0'; + clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + coreclkin : in std_logic := '0'; + extswitch : in std_logic := '0'; + iqtxrxclkin : in std_logic := '0'; + plliqclkin : in std_logic := '0'; + refiqclk : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + rxiqclkin : in std_logic := '0'; + pllen : in std_logic := '0'; + clk0bad : out std_logic; + clk1bad : out std_logic; + clkout : out std_logic; + extswitchbuf : out std_logic; + pllclksel : out std_logic + ); +end cyclonev_pll_refclk_select; + +architecture behavior of cyclonev_pll_refclk_select is + +component cyclonev_pll_refclk_select_encrypted + generic ( + pll_auto_clk_sw_en : string := "false"; + pll_clk_loss_edge : string := "both_edges"; + pll_clk_loss_sw_en : string := "false"; + pll_clk_sw_dly : integer := 0; + pll_clkin_0_src : string := "ref_clk0"; + pll_clkin_1_src : string := "ref_clk1"; + pll_manu_clk_sw_en : string := "false"; + pll_sw_refclk_src : string := "clk_0" + ); + port ( + adjpllin : in std_logic := '0'; + cclk : in std_logic := '0'; + clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + coreclkin : in std_logic := '0'; + extswitch : in std_logic := '0'; + iqtxrxclkin : in std_logic := '0'; + plliqclkin : in std_logic := '0'; + refiqclk : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + rxiqclkin : in std_logic := '0'; + pllen : in std_logic := '0'; + clk0bad : out std_logic; + clk1bad : out std_logic; + clkout : out std_logic; + extswitchbuf : out std_logic; + pllclksel : out std_logic + ); +end component; + +begin + + +inst : cyclonev_pll_refclk_select_encrypted + generic map ( + pll_auto_clk_sw_en => pll_auto_clk_sw_en, + pll_clk_loss_edge => pll_clk_loss_edge, + pll_clk_loss_sw_en => pll_clk_loss_sw_en, + pll_clk_sw_dly => pll_clk_sw_dly, + pll_clkin_0_src => pll_clkin_0_src, + pll_clkin_1_src => pll_clkin_1_src, + pll_manu_clk_sw_en => pll_manu_clk_sw_en, + pll_sw_refclk_src => pll_sw_refclk_src + ) + port map ( + adjpllin => adjpllin, + cclk => cclk, + clkin => clkin, + coreclkin => coreclkin, + extswitch => extswitch, + iqtxrxclkin => iqtxrxclkin, + plliqclkin => plliqclkin, + refiqclk => refiqclk, + rxiqclkin => rxiqclkin, + pllen => pllen, + clk0bad => clk0bad, + clk1bad => clk1bad, + clkout => clkout, + extswitchbuf => extswitchbuf, + pllclksel => pllclksel + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_termination_logic is + generic ( + lpm_type : string := "cyclonev_termination_logic"; + a_iob_oct_test : string := "a_iob_oct_test_off" + ); + port ( + s2pload : in std_logic := '0'; + serdata : in std_logic := '0'; + scanenable : in std_logic := '0'; + scanin : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanout : out std_logic; + seriesterminationcontrol : out std_logic_vector(15 downto 0); + parallelterminationcontrol : out std_logic_vector(15 downto 0) + ); +end cyclonev_termination_logic; + +architecture behavior of cyclonev_termination_logic is + +component cyclonev_termination_logic_encrypted + generic ( + lpm_type : string := "cyclonev_termination_logic"; + a_iob_oct_test : string := "a_iob_oct_test_off" + ); + port ( + s2pload : in std_logic; + serdata : in std_logic; + scanenable : in std_logic; + scanin : in std_logic; + scanclk : in std_logic; + scanout : out std_logic; + seriesterminationcontrol : out std_logic_vector(15 downto 0); + parallelterminationcontrol : out std_logic_vector(15 downto 0) + ); +end component; + +begin + +inst : cyclonev_termination_logic_encrypted + generic map ( + lpm_type => lpm_type, + a_iob_oct_test => a_iob_oct_test + ) + port map ( + s2pload => s2pload, + serdata => serdata, + scanenable => scanenable, + scanin => scanin, + scanclk => scanclk, + scanout => scanout, + seriesterminationcontrol => seriesterminationcontrol, + parallelterminationcontrol => parallelterminationcontrol + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_termination is + generic ( + lpm_type : string := "cyclonev_termination"; + a_oct_nclrusr_inv : string := "a_oct_nclrusr_inv_off"; + a_oct_pwrdn : string := "true"; + a_oct_clkdiv : string := "a_oct_clkdiv_20"; + a_oct_intosc : string := "a_oct_intosc_2"; + a_oct_vref : string := "a_oct_vref_rupm_rdnm"; + a_oct_test_0 : string := "a_oct_test_0_off"; + a_oct_test_1 : string := "a_oct_test_1_off"; + a_oct_test_2 : string := "a_oct_test_2_off"; + a_oct_test_3 : string := "a_oct_test_3_off"; + a_oct_test_4 : string := "a_oct_test_4_off"; + a_oct_test_5 : string := "a_oct_test_5_off"; + a_oct_pllbiasen : string := "a_oct_pllbiasen_low"; + a_oct_usermode : string := "false" + ); + port ( + rzqin : in std_logic := '0'; + enserusr : in std_logic := '0'; + nclrusr : in std_logic := '0'; + clkenusr : in std_logic := '0'; + clkusr : in std_logic := '0'; + serdatafromcore : in std_logic := '0'; + scanclk : in std_logic := '0'; + otherenser : in std_logic_vector(8 downto 0) := (OTHERS => '0'); + serdataout : out std_logic; + enserout : out std_logic; + compoutrup : out std_logic; + compoutrdn : out std_logic; + serdatatocore : out std_logic; + scanin : out std_logic; + scanout : out std_logic + ); +end cyclonev_termination; + +architecture behavior of cyclonev_termination is + +component cyclonev_termination_encrypted + generic ( + lpm_type : string := "cyclonev_termination"; + a_oct_nclrusr_inv : string := "a_oct_nclrusr_inv_off"; + a_oct_pwrdn : string := "true"; + a_oct_clkdiv : string := "a_oct_clkdiv_20"; + a_oct_intosc : string := "a_oct_intosc_2"; + a_oct_vref : string := "a_oct_vref_rupm_rdnm"; + a_oct_test_0 : string := "a_oct_test_0_off"; + a_oct_test_1 : string := "a_oct_test_1_off"; + a_oct_test_2 : string := "a_oct_test_2_off"; + a_oct_test_3 : string := "a_oct_test_3_off"; + a_oct_test_4 : string := "a_oct_test_4_off"; + a_oct_test_5 : string := "a_oct_test_5_off"; + a_oct_pllbiasen : string := "a_oct_pllbiasen_low"; + a_oct_usermode : string := "false" + ); + port ( + rzqin : in std_logic; + enserusr : in std_logic; + nclrusr : in std_logic; + clkenusr : in std_logic; + clkusr : in std_logic; + serdatafromcore : in std_logic; + scanclk : in std_logic; + otherenser : in std_logic_vector(8 downto 0); + serdataout : out std_logic; + enserout : out std_logic; + compoutrup : out std_logic; + compoutrdn : out std_logic; + serdatatocore : out std_logic; + scanin : out std_logic; + scanout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_termination_encrypted + generic map ( + lpm_type => lpm_type, + a_oct_nclrusr_inv => a_oct_nclrusr_inv, + a_oct_pwrdn => a_oct_pwrdn, + a_oct_clkdiv => a_oct_clkdiv, + a_oct_intosc => a_oct_intosc, + a_oct_vref => a_oct_vref, + a_oct_test_0 => a_oct_test_0, + a_oct_test_1 => a_oct_test_1, + a_oct_test_2 => a_oct_test_2, + a_oct_test_3 => a_oct_test_3, + a_oct_test_4 => a_oct_test_4, + a_oct_test_5 => a_oct_test_5, + a_oct_pllbiasen => a_oct_pllbiasen, + a_oct_usermode => a_oct_usermode + ) + port map ( + rzqin => rzqin, + enserusr => enserusr, + nclrusr => nclrusr, + clkenusr => clkenusr, + clkusr => clkusr, + serdatafromcore => serdatafromcore, + scanclk => scanclk, + otherenser => otherenser, + serdataout => serdataout, + enserout => enserout, + compoutrup => compoutrup, + compoutrdn => compoutrdn, + serdatatocore => serdatatocore, + scanin => scanin, + scanout => scanout + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_asmiblock is + generic ( + lpm_type : string := "cyclonev_asmiblock"; + enable_sim : string := "false" + ); + port ( + dclk : in std_logic; + sce : in std_logic; + oe : in std_logic; + data0out : in std_logic; + data1out : in std_logic; + data2out : in std_logic; + data3out : in std_logic; + data0oe : in std_logic; + data1oe : in std_logic; + data2oe : in std_logic; + data3oe : in std_logic; + data0in : out std_logic; + data1in : out std_logic; + data2in : out std_logic; + data3in : out std_logic; + spidclk : out std_logic; + spidataout : out std_logic_vector(3 downto 0); + spisce : out std_logic; + spidatain : in std_logic_vector(3 downto 0) + ); +end cyclonev_asmiblock; + +architecture behavior of cyclonev_asmiblock is + +component cyclonev_asmiblock_encrypted + generic ( + lpm_type : string := "cyclonev_asmiblock"; + enable_sim : string := "false" + ); + port ( + dclk : in std_logic; + sce : in std_logic; + oe : in std_logic; + data0out : in std_logic; + data1out : in std_logic; + data2out : in std_logic; + data3out : in std_logic; + data0oe : in std_logic; + data1oe : in std_logic; + data2oe : in std_logic; + data3oe : in std_logic; + data0in : out std_logic; + data1in : out std_logic; + data2in : out std_logic; + data3in : out std_logic; + spidclk : out std_logic; + spidataout : out std_logic_vector(3 downto 0); + spisce : out std_logic; + spidatain : in std_logic_vector(3 downto 0) + ); +end component; + +begin + + +inst : cyclonev_asmiblock_encrypted + generic map ( + lpm_type => lpm_type, + enable_sim => enable_sim + ) + port map ( + dclk => dclk, + sce => sce, + oe => oe, + data0out => data0out, + data1out => data1out, + data2out => data2out, + data3out => data3out, + data0oe => data0oe, + data1oe => data1oe, + data2oe => data2oe, + data3oe => data3oe, + data0in => data0in, + data1in => data1in, + data2in => data2in, + data3in => data3in, + spidclk => spidclk, + spidataout => spidataout, + spisce => spisce, + spidatain => spidatain + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_chipidblock is + generic ( + lpm_type : string := "cyclonev_chipidblock"; + ID_VALUE : std_logic_vector(63 downto 0) := (others => '1') + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + regout : out std_logic + ); +end cyclonev_chipidblock; + +architecture behavior of cyclonev_chipidblock is + +component cyclonev_chipidblock_encrypted + generic ( + lpm_type : string := "cyclonev_chipidblock"; + ID_VALUE : std_logic_vector(63 downto 0) := (others => '1') + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + regout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_chipidblock_encrypted + generic map ( + lpm_type => lpm_type, + ID_VALUE => ID_VALUE + ) + port map ( + clk => clk, + shiftnld => shiftnld, + regout => regout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_controller is + generic ( + lpm_type : string := "cyclonev_controller" + ); + port ( + nceout : out std_logic + ); +end cyclonev_controller; + +architecture behavior of cyclonev_controller is + +component cyclonev_controller_encrypted + generic ( + lpm_type : string := "cyclonev_controller" + ); + port ( + nceout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_controller_encrypted + generic map ( + lpm_type => lpm_type + ) + port map ( + nceout => nceout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_crcblock is +generic ( + oscillator_divider : integer := 256; + error_delay : integer := 0; + error_dra_dl_bypass : string := "false"; + crc_deld_disable : string := "false"; + triple_adj_err_correction : string := "false"; + quad_adj_err_correction : string := "false"; + lpm_type : string := "cyclonev_crcblock" + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + crcerror : out std_logic; + regout : out std_logic; + endofedfullchip : out std_logic + ); +end cyclonev_crcblock; + +architecture behavior of cyclonev_crcblock is + +component cyclonev_crcblock_encrypted + generic ( + oscillator_divider : integer := 256; + error_delay : integer := 0; + error_dra_dl_bypass : string := "false"; + crc_deld_disable : string := "false"; + triple_adj_err_correction : string := "false"; + quad_adj_err_correction : string := "false"; + lpm_type : string := "cyclonev_crcblock" + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + crcerror : out std_logic; + regout : out std_logic; + endofedfullchip : out std_logic + ); +end component; + +begin + +inst : cyclonev_crcblock_encrypted + generic map ( + oscillator_divider => oscillator_divider, + error_delay => error_delay, + error_dra_dl_bypass => error_dra_dl_bypass, + crc_deld_disable => crc_deld_disable, + triple_adj_err_correction => triple_adj_err_correction, + quad_adj_err_correction => quad_adj_err_correction, + lpm_type => lpm_type + ) + port map ( + clk => clk, + shiftnld => shiftnld, + crcerror => crcerror, + regout => regout, + endofedfullchip => endofedfullchip + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_jtag is + generic ( + lpm_type : string := "cyclonev_jtag" + ); + port ( + tms : in std_logic := '0'; + tck : in std_logic := '0'; + tdi : in std_logic := '0'; + ntrst : in std_logic := '0'; + tdoutap : in std_logic := '0'; + tdouser : in std_logic := '0'; + tdo : out std_logic; + tmsutap : out std_logic; + tckutap : out std_logic; + tdiutap : out std_logic; + shiftuser : out std_logic; + clkdruser : out std_logic; + updateuser : out std_logic; + runidleuser : out std_logic; + usr1user : out std_logic + ); +end cyclonev_jtag; + +architecture behavior of cyclonev_jtag is + +component cyclonev_jtag_encrypted + generic ( + lpm_type : string := "cyclonev_jtag" + ); + port ( + tms : in std_logic; + tck : in std_logic; + tdi : in std_logic; + ntrst : in std_logic; + tdoutap : in std_logic; + tdouser : in std_logic; + tdo : out std_logic; + tmsutap : out std_logic; + tckutap : out std_logic; + tdiutap : out std_logic; + shiftuser : out std_logic; + clkdruser : out std_logic; + updateuser : out std_logic; + runidleuser : out std_logic; + usr1user : out std_logic + ); +end component; + +begin + + +inst : cyclonev_jtag_encrypted + generic map ( + lpm_type => lpm_type + ) + port map ( + tms => tms, + tck => tck, + tdi => tdi, + ntrst => ntrst, + tdoutap => tdoutap, + tdouser => tdouser, + tdo => tdo, + tmsutap => tmsutap, + tckutap => tckutap, + tdiutap => tdiutap, + shiftuser => shiftuser, + clkdruser => clkdruser, + updateuser => updateuser, + runidleuser => runidleuser, + usr1user => usr1user + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_prblock is + generic ( + lpm_type : string := "cyclonev_prblock" + ); + port ( + clk : in std_logic; + corectl : in std_logic; + prrequest : in std_logic; + data : in std_logic_vector(15 downto 0); + externalrequest : out std_logic; + error : out std_logic; + ready : out std_logic; + done : out std_logic + ); +end cyclonev_prblock; + +architecture behavior of cyclonev_prblock is + +component cyclonev_prblock_encrypted + generic ( + lpm_type : string := "cyclonev_prblock" + ); + port ( + clk : in std_logic; + corectl : in std_logic; + prrequest : in std_logic; + data : in std_logic_vector(15 downto 0); + externalrequest : out std_logic; + error : out std_logic; + ready : out std_logic; + done : out std_logic + ); +end component; + +begin + + +inst : cyclonev_prblock_encrypted + generic map ( + lpm_type => lpm_type + ) + port map ( + clk => clk, + corectl => corectl, + prrequest => prrequest, + data => data, + externalrequest => externalrequest, + error => error, + ready => ready, + done => done + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_rublock is + generic ( + sim_init_watchdog_value : integer := 0; + sim_init_status : integer := 0; + sim_init_config_is_application : string := "false"; + sim_init_watchdog_enabled : string := "false"; + lpm_type : string := "cyclonev_rublock" + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + captnupdt : in std_logic; + regin : in std_logic; + rsttimer : in std_logic; + rconfig : in std_logic; + regout : out std_logic + ); +end cyclonev_rublock; + +architecture behavior of cyclonev_rublock is + +component cyclonev_rublock_encrypted + generic ( + sim_init_watchdog_value : integer := 0; + sim_init_status : integer := 0; + sim_init_config_is_application : string := "false"; + sim_init_watchdog_enabled : string := "false"; + lpm_type : string := "cyclonev_rublock" + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + captnupdt : in std_logic; + regin : in std_logic; + rsttimer : in std_logic; + rconfig : in std_logic; + regout : out std_logic + ); +end component; + +begin + + +inst : cyclonev_rublock_encrypted + generic map ( + sim_init_watchdog_value => sim_init_watchdog_value, + sim_init_status => sim_init_status, + sim_init_config_is_application => sim_init_config_is_application, + sim_init_watchdog_enabled => sim_init_watchdog_enabled, + lpm_type => lpm_type + ) + port map ( + clk => clk, + shiftnld => shiftnld, + captnupdt => captnupdt, + regin => regin, + rsttimer => rsttimer, + rconfig => rconfig, + regout => regout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_tsdblock is + generic ( + clock_divider_enable : string := "on"; + clock_divider_value : integer := 40; + sim_tsdcalo : integer := 0; + lpm_type : string := "cyclonev_tsdblock" + ); + port ( + clk : in std_logic; + ce : in std_logic; + clr : in std_logic; + tsdcalo : out std_logic_vector(7 downto 0); + tsdcaldone : out std_logic + ); +end cyclonev_tsdblock; + +architecture behavior of cyclonev_tsdblock is + +component cyclonev_tsdblock_encrypted + generic ( + clock_divider_enable : string := "on"; + clock_divider_value : integer := 40; + sim_tsdcalo : integer := 0; + lpm_type : string := "cyclonev_tsdblock" + ); + port ( + clk : in std_logic; + ce : in std_logic; + clr : in std_logic; + tsdcalo : out std_logic_vector(7 downto 0); + tsdcaldone : out std_logic + ); +end component; + +begin + + +inst : cyclonev_tsdblock_encrypted + generic map ( + clock_divider_enable => clock_divider_enable, + clock_divider_value => clock_divider_value, + sim_tsdcalo => sim_tsdcalo, + lpm_type => lpm_type + ) + port map ( + clk => clk, + ce => ce, + clr => clr, + tsdcalo => tsdcalo, + tsdcaldone => tsdcaldone + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_read_fifo is + generic ( + use_half_rate_read : string := "false" + ); + port ( + datain : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + wclk : in std_logic := '0'; + we : in std_logic := '0'; + rclk : in std_logic := '0'; + re : in std_logic := '0'; + areset : in std_logic := '0'; + plus2 : in std_logic := '0'; + dataout : out std_logic_vector(3 downto 0) + ); +end cyclonev_read_fifo; + +architecture behavior of cyclonev_read_fifo is + +component cyclonev_read_fifo_encrypted + generic ( + use_half_rate_read : string := "false" + ); + port ( + datain : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + wclk : in std_logic := '0'; + we : in std_logic := '0'; + rclk : in std_logic := '0'; + re : in std_logic := '0'; + areset : in std_logic := '0'; + plus2 : in std_logic := '0'; + dataout : out std_logic_vector(3 downto 0) + ); +end component; + +begin + + +inst : cyclonev_read_fifo_encrypted + generic map ( + use_half_rate_read => use_half_rate_read + ) + port map ( + datain => datain, + wclk => wclk, + we => we, + rclk => rclk, + re => re, + areset => areset, + plus2 => plus2, + dataout => dataout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_read_fifo_read_enable is + generic ( + use_stalled_read_enable : string := "false" + ); + port ( + re : in std_logic := '1'; + rclk : in std_logic := '0'; + plus2 : in std_logic := '0'; + areset : in std_logic := '0'; + reout : out std_logic; + plus2out : out std_logic + ); +end cyclonev_read_fifo_read_enable; + +architecture behavior of cyclonev_read_fifo_read_enable is + +component cyclonev_read_fifo_read_enable_encrypted + generic ( + use_stalled_read_enable : string := "false" + ); + port ( + re : in std_logic := '1'; + rclk : in std_logic := '0'; + plus2 : in std_logic := '0'; + areset : in std_logic := '0'; + reout : out std_logic; + plus2out : out std_logic + ); +end component; + +begin + + +inst : cyclonev_read_fifo_read_enable_encrypted + generic map ( + use_stalled_read_enable => use_stalled_read_enable + ) + port map ( + re => re, + rclk => rclk, + plus2 => plus2, + areset => areset, + reout => reout, + plus2out => plus2out + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity cyclonev_mac is + generic ( + ax_width : integer := 16; + ay_scan_in_width : integer := 16; + az_width : integer := 1; + bx_width : integer := 16; + by_width : integer := 16; + bz_width : integer := 1; + scan_out_width : integer := 1; + result_a_width : integer := 33; + result_b_width : integer := 1; + + operation_mode : string := "m18x18_sumof2"; + mode_sub_location : integer := 0; + operand_source_max : string := "input"; + operand_source_may : string := "input"; + operand_source_mbx : string := "input"; + operand_source_mby : string := "input"; + preadder_subtract_a : string := "false"; + preadder_subtract_b : string := "false"; + signed_max : string := "false"; + signed_may : string := "false"; + signed_mbx : string := "false"; + signed_mby : string := "false"; + + ay_use_scan_in : string := "false"; + by_use_scan_in : string := "false"; + delay_scan_out_ay : string := "false"; + delay_scan_out_by : string := "false"; + use_chainadder : string := "false"; + enable_double_accum : string := "false"; + load_const_value : integer := 0; + + coef_a_0 : integer := 0; + coef_a_1 : integer := 0; + coef_a_2 : integer := 0; + coef_a_3 : integer := 0; + coef_a_4 : integer := 0; + coef_a_5 : integer := 0; + coef_a_6 : integer := 0; + coef_a_7 : integer := 0; + coef_b_0 : integer := 0; + coef_b_1 : integer := 0; + coef_b_2 : integer := 0; + coef_b_3 : integer := 0; + coef_b_4 : integer := 0; + coef_b_5 : integer := 0; + coef_b_6 : integer := 0; + coef_b_7 : integer := 0; + + ax_clock : string := "none"; + ay_scan_in_clock : string := "none"; + az_clock : string := "none"; + bx_clock : string := "none"; + by_clock : string := "none"; + bz_clock : string := "none"; + coef_sel_a_clock : string := "none"; + coef_sel_b_clock : string := "none"; + sub_clock : string := "none"; + negate_clock : string := "none"; + accumulate_clock : string := "none"; + load_const_clock : string := "none"; + output_clock : string := "none" + ); + port ( + sub : in std_logic := '0'; + negate : in std_logic := '0'; + accumulate : in std_logic := '0'; + loadconst : in std_logic := '0'; + ax : in std_logic_vector(ax_width-1 downto 0) := (others => '0'); + ay : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0'); + scanin : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0'); + az : in std_logic_vector(az_width-1 downto 0) := (others => '0'); + bx : in std_logic_vector(bx_width-1 downto 0) := (others => '0'); + by : in std_logic_vector(by_width-1 downto 0) := (others => '0'); + bz : in std_logic_vector(bz_width-1 downto 0) := (others => '0'); + coefsela : in std_logic_vector(2 downto 0) := (others => '0'); + coefselb : in std_logic_vector(2 downto 0) := (others => '0'); + chainin : in std_logic_vector(63 downto 0) := (others => '0'); + clk : in std_logic_vector(2 downto 0) := (others => '0'); + aclr : in std_logic_vector(1 downto 0) := (others => '0'); + ena : in std_logic_vector(2 downto 0) := (others => '1'); + dftout : out std_logic; + resulta : out std_logic_vector(result_a_width-1 downto 0); + resultb : out std_logic_vector(result_b_width-1 downto 0); + scanout : out std_logic_vector(scan_out_width-1 downto 0); + chainout : out std_logic_vector(63 downto 0) + ); +end cyclonev_mac; + +architecture behavior of cyclonev_mac is + +component cyclonev_mac_encrypted + generic ( + ax_width : integer; + ay_scan_in_width : integer; + az_width : integer; + bx_width : integer; + by_width : integer; + bz_width : integer; + scan_out_width : integer; + result_a_width : integer; + result_b_width : integer; + + operation_mode : string; + mode_sub_location : integer; + operand_source_max : string; + operand_source_may : string; + operand_source_mbx : string; + operand_source_mby : string; + preadder_subtract_a : string; + preadder_subtract_b : string; + signed_max : string; + signed_may : string; + signed_mbx : string; + signed_mby : string; + + ay_use_scan_in : string; + by_use_scan_in : string; + delay_scan_out_ay : string; + delay_scan_out_by : string; + use_chainadder : string; + enable_double_accum : string; + load_const_value : integer; + + coef_a_0 : integer; + coef_a_1 : integer; + coef_a_2 : integer; + coef_a_3 : integer; + coef_a_4 : integer; + coef_a_5 : integer; + coef_a_6 : integer; + coef_a_7 : integer; + coef_b_0 : integer; + coef_b_1 : integer; + coef_b_2 : integer; + coef_b_3 : integer; + coef_b_4 : integer; + coef_b_5 : integer; + coef_b_6 : integer; + coef_b_7 : integer; + + ax_clock : string; + ay_scan_in_clock : string; + az_clock : string; + bx_clock : string; + by_clock : string; + bz_clock : string; + coef_sel_a_clock : string; + coef_sel_b_clock : string; + sub_clock : string; + negate_clock : string; + accumulate_clock : string; + load_const_clock : string; + output_clock : string + ); + port ( + sub : in std_logic; + negate : in std_logic; + accumulate : in std_logic; + loadconst : in std_logic; + ax : in std_logic_vector(ax_width-1 downto 0); + ay : in std_logic_vector(ay_scan_in_width-1 downto 0); + scanin : in std_logic_vector(ay_scan_in_width-1 downto 0); + az : in std_logic_vector(az_width-1 downto 0); + bx : in std_logic_vector(bx_width-1 downto 0); + by : in std_logic_vector(by_width-1 downto 0); + bz : in std_logic_vector(bz_width-1 downto 0); + coefsela : in std_logic_vector(2 downto 0); + coefselb : in std_logic_vector(2 downto 0); + chainin : in std_logic_vector(63 downto 0); + clk : in std_logic_vector(2 downto 0); + aclr : in std_logic_vector(1 downto 0); + ena : in std_logic_vector(2 downto 0); + dftout : out std_logic; + resulta : out std_logic_vector(result_a_width-1 downto 0); + resultb : out std_logic_vector(result_b_width-1 downto 0); + scanout : out std_logic_vector(scan_out_width-1 downto 0); + chainout : out std_logic_vector(63 downto 0) + ); +end component; + +begin + +inst : cyclonev_mac_encrypted + generic map ( + ax_width => ax_width, + ay_scan_in_width => ay_scan_in_width, + az_width => az_width, + bx_width => bx_width, + by_width => by_width, + bz_width => bz_width, + scan_out_width => scan_out_width, + result_a_width => result_a_width, + result_b_width => result_b_width, + + operation_mode => operation_mode, + mode_sub_location => mode_sub_location, + operand_source_max => operand_source_max, + operand_source_may => operand_source_may, + operand_source_mbx => operand_source_mbx, + operand_source_mby => operand_source_mby, + preadder_subtract_a => preadder_subtract_a, + preadder_subtract_b => preadder_subtract_b, + signed_max => signed_max, + signed_may => signed_may, + signed_mbx => signed_mbx, + signed_mby => signed_mby, + + ay_use_scan_in => ay_use_scan_in, + by_use_scan_in => by_use_scan_in, + delay_scan_out_ay => delay_scan_out_ay, + delay_scan_out_by => delay_scan_out_by, + use_chainadder => use_chainadder, + enable_double_accum => enable_double_accum, + load_const_value => load_const_value, + + coef_a_0 => coef_a_0, + coef_a_1 => coef_a_1, + coef_a_2 => coef_a_2, + coef_a_3 => coef_a_3, + coef_a_4 => coef_a_4, + coef_a_5 => coef_a_5, + coef_a_6 => coef_a_6, + coef_a_7 => coef_a_7, + coef_b_0 => coef_b_0, + coef_b_1 => coef_b_1, + coef_b_2 => coef_b_2, + coef_b_3 => coef_b_3, + coef_b_4 => coef_b_4, + coef_b_5 => coef_b_5, + coef_b_6 => coef_b_6, + coef_b_7 => coef_b_7, + + ax_clock => ax_clock, + ay_scan_in_clock => ay_scan_in_clock, + az_clock => az_clock, + bx_clock => bx_clock, + by_clock => by_clock, + bz_clock => bz_clock, + coef_sel_a_clock => coef_sel_a_clock, + coef_sel_b_clock => coef_sel_b_clock, + sub_clock => sub_clock, + negate_clock => negate_clock, + accumulate_clock => accumulate_clock, + load_const_clock => load_const_clock, + output_clock => output_clock + ) + port map ( + sub => sub, + negate => negate, + accumulate => accumulate, + loadconst => loadconst, + ax => ax, + ay => ay, + scanin => scanin, + az => az, + bx => bx, + by => by, + bz => bz, + coefsela => coefsela, + coefselb => coefselb, + chainin => chainin, + clk => clk, + aclr => aclr, + ena => ena, + dftout => dftout, + resulta => resulta, + resultb => resultb, + scanout => scanout, + chainout => chainout + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_ir_fifo_userdes is + generic ( + a_rb_bypass_serializer : string := "false"; + a_use_dynamic_fifo_mode : string := "false"; + a_rb_fifo_mode : string := "serializer_mode"; + a_rb_data_width : integer := 9; + a_enable_soft_cdr : string := "false"; + a_rb_tx_outclk : string := "false"; + a_rb_bslipcfg : integer := 0; + a_sim_wclk_pre_delay : integer := 0; + a_sim_readenable_pre_delay : integer := 0 + ); + port ( + bslipmax : out std_logic; + dynfifomode : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + observableout : out std_logic; + writeenable : in std_logic := '0'; + readclk : in std_logic := '0'; + txin : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + regscanovrd : in std_logic := '0'; + rxout : out std_logic_vector(9 downto 0); + bslipout : out std_logic; + rstn : in std_logic := '0'; + loaden : in std_logic := '0'; + lvdsmodeen : out std_logic; + bslipctl : in std_logic := '0'; + observablefout3 : out std_logic; + scanin : in std_logic := '0'; + readenable : in std_logic := '0'; + scanout : out std_logic; + writeclk : in std_logic := '0'; + observablefout2 : out std_logic; + dinfiforx : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + tstclk : in std_logic := '0'; + observablefout4 : out std_logic; + observablefout1 : out std_logic; + dout : out std_logic_vector(3 downto 0); + bslipin : in std_logic := '0'; + txout : out std_logic; + regscan : in std_logic := '0'; + observablewaddrcnt : out std_logic; + lvdstxsel : out std_logic + ); +end cyclonev_ir_fifo_userdes; + +architecture behavior of cyclonev_ir_fifo_userdes is + +component cyclonev_ir_fifo_userdes_encrypted + generic ( + a_rb_bypass_serializer : string := "false"; + a_use_dynamic_fifo_mode : string := "false"; + a_rb_fifo_mode : string := "serializer_mode"; + a_rb_data_width : integer := 9; + a_enable_soft_cdr : string := "false"; + a_rb_tx_outclk : string := "false"; + a_rb_bslipcfg : integer := 0; + a_sim_wclk_pre_delay : integer := 0; + a_sim_readenable_pre_delay : integer := 0 + ); + port ( + bslipmax : out std_logic; + dynfifomode : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + observableout : out std_logic; + writeenable : in std_logic := '0'; + readclk : in std_logic := '0'; + txin : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + regscanovrd : in std_logic := '0'; + rxout : out std_logic_vector(9 downto 0); + bslipout : out std_logic; + rstn : in std_logic := '0'; + loaden : in std_logic := '0'; + lvdsmodeen : out std_logic; + bslipctl : in std_logic := '0'; + observablefout3 : out std_logic; + scanin : in std_logic := '0'; + readenable : in std_logic := '0'; + scanout : out std_logic; + writeclk : in std_logic := '0'; + observablefout2 : out std_logic; + dinfiforx : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + tstclk : in std_logic := '0'; + observablefout4 : out std_logic; + observablefout1 : out std_logic; + dout : out std_logic_vector(3 downto 0); + bslipin : in std_logic := '0'; + txout : out std_logic; + regscan : in std_logic := '0'; + observablewaddrcnt : out std_logic; + lvdstxsel : out std_logic + ); +end component; + +begin + +inst : cyclonev_ir_fifo_userdes_encrypted + generic map ( + a_rb_bypass_serializer => a_rb_bypass_serializer, + a_use_dynamic_fifo_mode => a_use_dynamic_fifo_mode, + a_rb_fifo_mode => a_rb_fifo_mode, + a_rb_data_width => a_rb_data_width, + a_enable_soft_cdr => a_enable_soft_cdr, + a_rb_tx_outclk => a_rb_tx_outclk, + a_rb_bslipcfg => a_rb_bslipcfg, + a_sim_wclk_pre_delay => a_sim_wclk_pre_delay, + a_sim_readenable_pre_delay => a_sim_readenable_pre_delay + ) + port map ( + bslipmax => bslipmax, + dynfifomode => dynfifomode, + observableout => observableout, + writeenable => writeenable, + readclk => readclk, + txin => txin, + regscanovrd => regscanovrd, + rxout => rxout, + bslipout => bslipout, + rstn => rstn, + loaden => loaden, + lvdsmodeen => lvdsmodeen, + bslipctl => bslipctl, + observablefout3 => observablefout3, + scanin => scanin, + readenable => readenable, + scanout => scanout, + writeclk => writeclk, + observablefout2 => observablefout2, + dinfiforx => dinfiforx, + tstclk => tstclk, + observablefout4 => observablefout4, + observablefout1 => observablefout1, + dout => dout, + bslipin => bslipin, + txout => txout, + regscan => regscan, + observablewaddrcnt => observablewaddrcnt, + lvdstxsel => lvdstxsel + ); + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_oscillator is + generic ( + lpm_type : string := "cyclonev_oscillator"); + port ( + oscena : in std_logic; + clkout : out std_logic; + clkout1 : out std_logic + ); +end cyclonev_oscillator; + +architecture behavior of cyclonev_oscillator is + +component cyclonev_oscillator_encrypted + generic ( + lpm_type : string := "cyclonev_oscillator"); + port ( + oscena : in std_logic; + clkout : out std_logic; + clkout1 : out std_logic + ); +end component; + +begin + + +inst : cyclonev_oscillator_encrypted + generic map ( + lpm_type => lpm_type + ) + port map ( + oscena => oscena, + clkout => clkout, + clkout1 => clkout1 + ); + + +end behavior; diff --git a/Common/sim/altera/cyclonev_components.vhd b/Common/sim/altera/cyclonev_components.vhd new file mode 100644 index 0000000..b4d3955 --- /dev/null +++ b/Common/sim/altera/cyclonev_components.vhd @@ -0,0 +1,1599 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- This simulation model contains highly confidential and +-- proprietary information of Altera and is being provided +-- in accordance with and subject to the protections of the +-- applicable Altera Program License Subscription Agreement +-- which governs its use and disclosure. Your use of Altera +-- Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, +-- and any output files any of the foregoing (including device +-- programming or simulation files), and any associated +-- documentation or information are expressly subject to the +-- terms and conditions of the Altera Program License Subscription +-- Agreement, the Altera Quartus II License Agreement, the Altera +-- MegaCore Function License Agreement, or other applicable +-- license agreement, including, without limitation, that your +-- use is for the sole purpose of simulating designs for use +-- exclusively in logic devices manufactured by Altera and sold +-- by Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. Altera products and +-- services are protected under numerous U.S. and foreign patents, +-- maskwork rights, copyrights and other intellectual property laws. +-- Altera assumes no responsibility or liability arising out of the +-- application or use of this simulation model. +-- Quartus II 15.0.0 Build 145 04/22/2015 + +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.VITAL_Timing.all; +use work.cyclonev_atom_pack.all; + +package cyclonev_components is + + +-- +-- cyclonev_ff +-- + +COMPONENT cyclonev_ff + generic ( + power_up : string := "low"; + x_on_violation : string := "on"; + lpm_type : string := "cyclonev_ff"; + tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; + tpd_asdata_q: VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_d : VitalDelayType01 := DefPropDelay01; + tipd_asdata : VitalDelayType01 := DefPropDelay01; + tipd_sclr : VitalDelayType01 := DefPropDelay01; + tipd_sload : VitalDelayType01 := DefPropDelay01; + tipd_clrn : VitalDelayType01 := DefPropDelay01; + tipd_aload : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*" + ); + port ( + d : in std_logic := '0'; + clk : in std_logic := '0'; + clrn : in std_logic := '1'; + aload : in std_logic := '0'; + sclr : in std_logic := '0'; + sload : in std_logic := '0'; + ena : in std_logic := '1'; + asdata : in std_logic := '0'; + devclrn : in std_logic := '1'; + devpor : in std_logic := '1'; + q : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_pseudo_diff_out +-- + +COMPONENT cyclonev_pseudo_diff_out + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tipd_oein : VitalDelayType01 := DefPropDelay01; + tpd_oein_oeout : VitalDelayType01 := DefPropDelay01; + tpd_oein_oebout : VitalDelayType01 := DefPropDelay01; + tipd_dtcin : VitalDelayType01 := DefPropDelay01; + tpd_dtcin_dtc : VitalDelayType01 := DefPropDelay01; + tpd_dtcin_dtcbar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + lpm_type : string := "stratuxv_pseudo_diff_out" + ); + PORT ( + i : IN std_logic := '0'; + o : OUT std_logic; + obar : OUT std_logic; + dtcin : in std_logic := '0'; + oein : in std_logic := '0'; + dtc : OUT std_logic; + dtcbar : OUT std_logic; + oeout : OUT std_logic; + oebout : OUT std_logic + ); +END COMPONENT; + +-- +-- cyclonev_lcell_comb +-- + +COMPONENT cyclonev_lcell_comb + generic ( + lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1'); + shared_arith : string := "off"; + extended_lut : string := "off"; + dont_touch : string := "off"; + lpm_type : string := "cyclonev_lcell_comb"; + TimingChecksOn: Boolean := True; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks; + InstancePath: STRING := "*"; + tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; + tpd_datab_combout : VitalDelayType01 := DefPropDelay01; + tpd_datac_combout : VitalDelayType01 := DefPropDelay01; + tpd_datad_combout : VitalDelayType01 := DefPropDelay01; + tpd_datae_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataf_combout : VitalDelayType01 := DefPropDelay01; + tpd_datag_combout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01; + tpd_datab_sumout : VitalDelayType01 := DefPropDelay01; + tpd_datac_sumout : VitalDelayType01 := DefPropDelay01; + tpd_datad_sumout : VitalDelayType01 := DefPropDelay01; + tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01; + tpd_cin_sumout : VitalDelayType01 := DefPropDelay01; + tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; + tpd_datab_cout : VitalDelayType01 := DefPropDelay01; + tpd_datac_cout : VitalDelayType01 := DefPropDelay01; + tpd_datad_cout : VitalDelayType01 := DefPropDelay01; + tpd_dataf_cout : VitalDelayType01 := DefPropDelay01; + tpd_cin_cout : VitalDelayType01 := DefPropDelay01; + tpd_sharein_cout : VitalDelayType01 := DefPropDelay01; + tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01; + tpd_datab_shareout : VitalDelayType01 := DefPropDelay01; + tpd_datac_shareout : VitalDelayType01 := DefPropDelay01; + tpd_datad_shareout : VitalDelayType01 := DefPropDelay01; + tipd_dataa : VitalDelayType01 := DefPropDelay01; + tipd_datab : VitalDelayType01 := DefPropDelay01; + tipd_datac : VitalDelayType01 := DefPropDelay01; + tipd_datad : VitalDelayType01 := DefPropDelay01; + tipd_datae : VitalDelayType01 := DefPropDelay01; + tipd_dataf : VitalDelayType01 := DefPropDelay01; + tipd_datag : VitalDelayType01 := DefPropDelay01; + tipd_cin : VitalDelayType01 := DefPropDelay01; + tipd_sharein : VitalDelayType01 := DefPropDelay01 + ); + port ( + dataa : in std_logic := '0'; + datab : in std_logic := '0'; + datac : in std_logic := '0'; + datad : in std_logic := '0'; + datae : in std_logic := '0'; + dataf : in std_logic := '0'; + datag : in std_logic := '0'; + cin : in std_logic := '0'; + sharein : in std_logic := '0'; + combout : out std_logic; + sumout : out std_logic; + cout : out std_logic; + shareout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_routing_wire +-- + +COMPONENT cyclonev_routing_wire + generic ( + MsgOn : Boolean := DefGlitchMsgOn; + XOn : Boolean := DefGlitchXOn; + tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; + tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; + tipd_datain : VitalDelayType01 := DefPropDelay01 + ); + PORT ( + datain : in std_logic; + dataout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_ram_block +-- + +COMPONENT cyclonev_ram_block + GENERIC ( + operation_mode : STRING := "single_port"; + mixed_port_feed_through_mode : STRING := "dont_care"; + ram_block_type : STRING := "auto"; + logical_ram_name : STRING := "ram_name"; + init_file : STRING := "init_file.hex"; + init_file_layout : STRING := "none"; + ecc_pipeline_stage_enabled : STRING := "false"; + enable_ecc : STRING := "false"; + width_eccstatus : INTEGER := 2; + data_interleave_width_in_bits : INTEGER := 1; + data_interleave_offset_in_bits : INTEGER := 1; + port_a_logical_ram_depth : INTEGER := 0; + port_a_logical_ram_width : INTEGER := 0; + port_a_first_address : INTEGER := 0; + port_a_last_address : INTEGER := 0; + port_a_first_bit_number : INTEGER := 0; + bist_ena : STRING := "false"; + port_a_address_clear : STRING := "none"; + port_a_data_out_clear : STRING := "none"; + port_a_data_in_clock : STRING := "clock0"; + port_a_address_clock : STRING := "clock0"; + port_a_write_enable_clock : STRING := "clock0"; + port_a_read_enable_clock : STRING := "clock0"; + port_a_byte_enable_clock : STRING := "clock0"; + port_a_data_out_clock : STRING := "none"; + port_a_data_width : INTEGER := 1; + port_a_address_width : INTEGER := 1; + port_a_byte_enable_mask_width : INTEGER := 1; + port_b_logical_ram_depth : INTEGER := 0; + port_b_logical_ram_width : INTEGER := 0; + port_b_first_address : INTEGER := 0; + port_b_last_address : INTEGER := 0; + port_b_first_bit_number : INTEGER := 0; + port_b_address_clear : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + port_b_data_in_clock : STRING := "clock1"; + port_b_address_clock : STRING := "clock1"; + port_b_write_enable_clock: STRING := "clock1"; + port_b_read_enable_clock: STRING := "clock1"; + port_b_byte_enable_clock : STRING := "clock1"; + port_b_data_out_clock : STRING := "none"; + port_b_data_width : INTEGER := 1; + port_b_address_width : INTEGER := 1; + port_b_byte_enable_mask_width : INTEGER := 1; + port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; + port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; + power_up_uninitialized : STRING := "false"; + port_b_byte_size : INTEGER := 0; + port_a_byte_size : INTEGER := 0; + lpm_type : string := "cyclonev_ram_block"; + lpm_hint : string := "true"; + clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none + clk0_output_clock_enable : STRING := "none"; -- ena0,none + clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none + clk1_output_clock_enable : STRING := "none"; -- ena1,none + mem_init0 : STRING := ""; + mem_init1 : STRING := ""; + mem_init2 : STRING := ""; + mem_init3 : STRING := ""; + mem_init4 : STRING := ""; + connectivity_checking : string := "off" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portawe : IN STD_LOGIC := '0'; + portare : IN STD_LOGIC := '1'; + portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); + portbwe : IN STD_LOGIC := '0'; + portbre : IN STD_LOGIC := '1'; + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena3 : IN STD_LOGIC := '1'; + clr0 : IN STD_LOGIC := '0'; + clr1 : IN STD_LOGIC := '0'; + nerror : IN STD_LOGIC := '1'; + portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portaaddrstall : IN STD_LOGIC := '0'; + portbaddrstall : IN STD_LOGIC := '0'; + eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0'); + dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000"; + portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); + portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +-- +-- cyclonev_mlab_cell +-- + +COMPONENT cyclonev_mlab_cell + GENERIC ( + logical_ram_name : STRING := "lutram"; + logical_ram_depth : INTEGER := 0; + logical_ram_width : INTEGER := 0; + first_address : INTEGER := 0; + last_address : INTEGER := 0; + first_bit_number : INTEGER := 0; + init_file : STRING := "NONE"; + data_width : INTEGER := 20; + address_width : INTEGER := 5; + byte_enable_mask_width : INTEGER := 1; + byte_size : INTEGER := 1; + port_b_data_out_clock : STRING := "none"; + port_b_data_out_clear : STRING := "none"; + lpm_type : STRING := "cyclonev_mlab_cell"; + lpm_hint : STRING := "true"; + mem_init0 : STRING := ""; + mixed_port_feed_through_mode : STRING := "new" + ); + PORT ( + portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0'); + portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1'); + portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0'); + clk0 : IN STD_LOGIC := '0'; + clk1 : IN STD_LOGIC := '0'; + ena0 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + clr : IN STD_LOGIC := '0'; + devclrn : IN STD_LOGIC := '1'; + devpor : IN STD_LOGIC := '1'; + portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) + ); +END COMPONENT; + +-- +-- cyclonev_io_ibuf +-- + +COMPONENT cyclonev_io_ibuf + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_ibar : VitalDelayType01 := DefPropDelay01; + tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_ibar_o : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + differential_mode : string := "false"; + bus_hold : string := "false"; + simulate_z_as : string := "Z"; + lpm_type : string := "cyclonev_io_ibuf" + ); + PORT ( + i : IN std_logic := '0'; + ibar : IN std_logic := '0'; + dynamicterminationcontrol : IN std_logic := '0'; + o : OUT std_logic + ); +END COMPONENT; + +-- +-- cyclonev_io_obuf +-- + +COMPONENT cyclonev_io_obuf + GENERIC ( + tipd_i : VitalDelayType01 := DefPropDelay01; + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; + tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tipd_parallelterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 ); + tpd_i_o : VitalDelayType01 := DefPropDelay01; + tpd_oe_o : VitalDelayType01 := DefPropDelay01; + tpd_i_obar : VitalDelayType01 := DefPropDelay01; + tpd_oe_obar : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + open_drain_output : string := "false"; + shift_series_termination_control : string := "false"; + sim_dynamic_termination_control_is_connected : string := "false"; + bus_hold : string := "false"; + lpm_type : string := "cyclonev_io_obuf" + ); + PORT ( + i : IN std_logic := '0'; + oe : IN std_logic := '1'; + dynamicterminationcontrol : IN std_logic := '0'; + seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + parallelterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0'); + devoe : IN std_logic := '1'; + o : OUT std_logic; + obar : OUT std_logic + ); +END COMPONENT; + +-- +-- cyclonev_ddio_in +-- + +COMPONENT cyclonev_ddio_in + generic( + tipd_datain : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkn : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + use_clkn : string := "false"; + lpm_type : string := "cyclonev_ddio_in" + ); + PORT ( + datain : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkn : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + regoutlo : OUT std_logic; + regouthi : OUT std_logic; + dfflo : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cyclonev_ddio_oe +-- + +COMPONENT cyclonev_ddio_oe + generic( + tipd_oe : VitalDelayType01 := DefPropDelay01; + tipd_octreadcontrol : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + disable_second_level_register : string := "false"; + lpm_type : string := "cyclonev_ddio_oe" + ); + PORT ( + oe : IN std_logic := '1'; + octreadcontrol : IN std_logic := '1'; + clk : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cyclonev_ddio_out +-- + +COMPONENT cyclonev_ddio_out + generic( + tipd_datainlo : VitalDelayType01 := DefPropDelay01; + tipd_datainhi : VitalDelayType01 := DefPropDelay01; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_clkhi : VitalDelayType01 := DefPropDelay01; + tipd_clklo : VitalDelayType01 := DefPropDelay01; + tipd_muxsel : VitalDelayType01 := DefPropDelay01; + tipd_hrbsel : VitalDelayType01 := DefPropDelay01; + tipd_ena : VitalDelayType01 := DefPropDelay01; + tipd_areset : VitalDelayType01 := DefPropDelay01; + tipd_sreset : VitalDelayType01 := DefPropDelay01; + XOn : Boolean := DefGlitchXOn; + MsgOn : Boolean := DefGlitchMsgOn; + power_up : string := "low"; + async_mode : string := "none"; + sync_mode : string := "none"; + half_rate_mode : string := "false"; + use_new_clocking_model : string := "false"; + lpm_type : string := "cyclonev_ddio_out" + ); + PORT ( + datainlo : IN std_logic := '0'; + datainhi : IN std_logic := '0'; + clk : IN std_logic := '0'; + clkhi : IN std_logic := '0'; + clklo : IN std_logic := '0'; + muxsel : IN std_logic := '0'; + ena : IN std_logic := '1'; + areset : IN std_logic := '0'; + sreset : IN std_logic := '0'; + dataout : OUT std_logic; + dfflo : OUT std_logic; + dffhi : OUT std_logic; + hrbypass : IN std_logic := '0'; + devclrn : IN std_logic := '1'; + devpor : IN std_logic := '1' + ); +END COMPONENT; + +-- +-- cyclonev_io_pad +-- + +COMPONENT cyclonev_io_pad + GENERIC ( + lpm_type : string := "cyclonev_io_pad"); + PORT ( + padin : IN std_logic := '0'; -- Input Pad + padout : OUT std_logic); -- Output Pad +END COMPONENT; + +-- +-- cyclonev_bias_block +-- + +COMPONENT cyclonev_bias_block + GENERIC ( + lpm_type : string := "cyclonev_bias_block"; + tipd_clk : VitalDelayType01 := DefPropDelay01; + tipd_shiftnld : VitalDelayType01 := DefPropDelay01; + tipd_captnupdt : VitalDelayType01 := DefPropDelay01; + tipd_din : VitalDelayType01 := DefPropDelay01; + tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; + tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01; + MsgOn: Boolean := DefGlitchMsgOn; + XOn: Boolean := DefGlitchXOn; + MsgOnChecks: Boolean := DefMsgOnChecks; + XOnChecks: Boolean := DefXOnChecks + ); + PORT ( + clk : in std_logic := '0'; + shiftnld : in std_logic := '0'; + captnupdt : in std_logic := '0'; + din : in std_logic := '0'; + dout : out std_logic := '0' + ); +END COMPONENT; + +-- +-- cyclonev_clk_phase_select +-- + +COMPONENT cyclonev_clk_phase_select + generic ( + phase_setting : integer := 0; + invert_phase : string := "dynamic"; + use_phasectrlin : string := "true"; + physical_clock_source : string := "dqs_2x_clk"; + use_dqs_input : string := "false" + ); + port ( + clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + dqsin : in std_logic := '0'; + phaseinvertctrl : in std_logic := '0'; + clkout : out std_logic; + phasectrlin : in std_logic_vector(1 downto 0) := (OTHERS => '0') + ); +END COMPONENT; + +-- +-- cyclonev_clkena +-- + +COMPONENT cyclonev_clkena + generic ( + clock_type : string := "auto"; + ena_register_mode : string := "always enabled"; + lpm_type : string := "cyclonev_clkena"; + ena_register_power_up : string := "high"; + disable_mode : string := "low"; + test_syn : string := "high" + ); + port ( + inclk : in std_logic := '1'; + ena : in std_logic := '1'; + enaout : out std_logic; + outclk : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_clkselect +-- + +COMPONENT cyclonev_clkselect + generic ( + lpm_type : string := "cyclonev_clkselect"; + test_cff : string := "low" + ); + port ( + inclk : in std_logic_vector(3 downto 0) := "0000"; + clkselect : in std_logic_vector(1 downto 0) := "00"; + outclk : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_delay_chain +-- + +COMPONENT cyclonev_delay_chain + generic ( + sim_intrinsic_rising_delay : integer := 200; + sim_intrinsic_falling_delay : integer := 200; + sim_rising_delay_increment : integer := 10; + sim_falling_delay_increment : integer := 10; + lpm_type : string := "cyclonev_delay_chain" + ); + port ( + datain : in std_logic := '0'; + delayctrlin : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + dataout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_dll +-- + +COMPONENT cyclonev_dll + generic ( + input_frequency : string := "0 MHz"; + delayctrlout_mode : string := "normal"; + jitter_reduction : string := "false"; + use_upndnin : string := "false"; + use_upndninclkena : string := "false"; + dual_phase_comparators : string := "true"; + sim_valid_lock : integer := 16; + sim_valid_lockcount : integer := 0; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10; + static_delay_ctrl : integer := 0; + lpm_type : string := "cyclonev_dll"; + lpm_hint : string := "unused"; + delay_chain_length : integer := 8 + ); + port ( + aload : in std_logic := '0'; + clk : in std_logic := '0'; + upndnin : in std_logic := '0'; + upndninclkena : in std_logic := '0'; + delayctrlout : out std_logic_vector(6 downto 0); + dqsupdate : out std_logic; + offsetdelayctrlout : out std_logic_vector(6 downto 0); + offsetdelayctrlclkout : out std_logic; + upndnout : out std_logic; + dffin : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_dqs_config +-- + +COMPONENT cyclonev_dqs_config + generic ( + lpm_type : string := "cyclonev_dqs_config" + ); + port ( + datain : in std_logic := '0'; + dqsenablegatingdelaysetting : out std_logic_vector(4 downto 0); + dqshalfratebypass : out std_logic; + enadqsenablephasetransferreg : out std_logic; + postamblephaseinvert : out std_logic; + dqsenableungatingdelaysetting : out std_logic_vector(4 downto 0); + octdelaysetting : out std_logic_vector(4 downto 0); + clk : in std_logic := '0'; + dqsbusoutdelaysetting : out std_logic_vector(4 downto 0); + postamblephasesetting : out std_logic_vector(1 downto 0); + ena : in std_logic := '0'; + dataout : out std_logic; + update : in std_logic := '0' + ); +END COMPONENT; + +-- +-- cyclonev_dqs_delay_chain +-- + +COMPONENT cyclonev_dqs_delay_chain + generic ( + dqs_input_frequency : string := "unused"; + dqs_phase_shift : integer := 0; + use_phasectrlin : string := "false"; + phase_setting : integer := 0; + dqs_offsetctrl_enable : string := "false"; + dqs_ctrl_latches_enable : string := "false"; + use_alternate_input_for_first_stage_delayctrl : string := "false"; + use_alternate_input_for_multi_stage_delayctrl : string := "false"; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10; + test_enable : string := "false" + ); + port ( + dqsin : in std_logic := '0'; + dqsenable : in std_logic := '1'; + delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + offsetctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + dqsupdateen : in std_logic := '1'; + phasectrlin : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + testin : in std_logic := '0'; + dffin : out std_logic; + dqsbusout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_dqs_enable_ctrl +-- + +COMPONENT cyclonev_dqs_enable_ctrl + generic ( + delay_dqs_enable_by_half_cycle : string := "false"; + add_phase_transfer_reg : string := "false" + ); + port ( + dqsenablein : in std_logic := '1'; + zerophaseclk : in std_logic := '1'; + enaphasetransferreg : in std_logic := '0'; + levelingclk : in std_logic := '1'; + dffin : out std_logic; + dffphasetransfer : out std_logic; + dffextenddqsenable : out std_logic; + dqsenableout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_fractional_pll +-- + +COMPONENT cyclonev_fractional_pll + generic ( + output_clock_frequency : string := ""; + reference_clock_frequency : string := ""; + mimic_fbclk_type : string := "cdb_pll_mimic_fbclk_gclk"; + dsm_accumulator_reset_value : integer := 0; + forcelock : string := "false"; + nreset_invert : string := "false"; + pll_atb : integer := 0; + pll_bwctrl : integer := 10000; + pll_cmp_buf_dly : string := "0 ps"; + pll_cp_comp : string := "true"; + pll_cp_current : integer := 20; + pll_ctrl_override_setting : string := "false"; + pll_dsm_dither : string := "disable"; + pll_dsm_out_sel : string := "disable"; + pll_dsm_reset : string := "false"; + pll_ecn_bypass : string := "false"; + pll_ecn_test_en : string := "false"; + pll_enable : string := "true"; + pll_fbclk_mux_1 : string := "glb"; + pll_fbclk_mux_2 : string := "fb_1"; + pll_fractional_carry_out : integer := 24; + pll_fractional_division : integer := 1; + pll_fractional_division_string : string := "1"; + pll_fractional_value_ready : string := "true"; + pll_lf_testen : string := "false"; + pll_lock_fltr_cfg : integer := 0; + pll_lock_fltr_test : string := "false"; + pll_m_cnt_bypass_en : string := "false"; + pll_m_cnt_coarse_dly : string := "0 ps"; + pll_m_cnt_fine_dly : string := "0 ps"; + pll_m_cnt_hi_div : integer := 1; + pll_m_cnt_in_src : string := "ph_mux_clk"; + pll_m_cnt_lo_div : integer := 1; + pll_m_cnt_odd_div_duty_en : string := "false"; + pll_m_cnt_ph_mux_prst : integer := 0; + pll_m_cnt_prst : integer := 1; + pll_n_cnt_bypass_en : string := "false"; + pll_n_cnt_coarse_dly : string := "0 ps"; + pll_n_cnt_fine_dly : string := "0 ps"; + pll_n_cnt_hi_div : integer := 1; + pll_n_cnt_lo_div : integer := 1; + pll_n_cnt_odd_div_duty_en : string := "false"; + pll_ref_buf_dly : string := "0 ps"; + pll_reg_boost : integer := 0; + pll_regulator_bypass : string := "false"; + pll_ripplecap_ctrl : integer := 0; + pll_slf_rst : string := "false"; + pll_tclk_mux_en : string := "false"; + pll_tclk_sel : string := "cdb_pll_tclk_sel_m_src"; + pll_test_enable : string := "false"; + pll_testdn_enable : string := "false"; + pll_testup_enable : string := "false"; + pll_unlock_fltr_cfg : integer := 0; + pll_vco_div : integer := 2; + pll_vco_ph0_en : string := "false"; + pll_vco_ph1_en : string := "false"; + pll_vco_ph2_en : string := "false"; + pll_vco_ph3_en : string := "false"; + pll_vco_ph4_en : string := "false"; + pll_vco_ph5_en : string := "false"; + pll_vco_ph6_en : string := "false"; + pll_vco_ph7_en : string := "false"; + pll_vctrl_test_voltage : integer := 750; + vccd0g_atb : string := "disable"; + vccd0g_output : integer := 0; + vccd1g_atb : string := "disable"; + vccd1g_output : integer := 0; + vccm1g_tap : integer := 2; + vccr_pd : string := "false"; + vcodiv_override : string := "false"; + fractional_pll_index : integer := 1 + ); + port ( + coreclkfb : in std_logic; + ecnc1test : in std_logic := '0'; + ecnc2test : in std_logic := '0'; + fbclkfpll : in std_logic := '0'; + lvdsfbin : in std_logic := '0'; + nresync : in std_logic; + pfden : in std_logic := '0'; + refclkin : in std_logic; + shift : in std_logic; + shiftdonein : in std_logic; + shiften : in std_logic; + up : in std_logic; + vsspl : in std_logic := '0'; + zdb : in std_logic := '0'; + cntnen : out std_logic; + fbclk : out std_logic; + fblvdsout : out std_logic; + lock : out std_logic; + mhi : out std_logic_vector(7 downto 0); + mcntout : out std_logic; + plniotribuf : out std_logic; + shiftdoneout : out std_logic; + tclk : out std_logic; + vcoph : out std_logic_vector(7 downto 0) + ); +END COMPONENT; + +-- +-- cyclonev_io_config +-- + +COMPONENT cyclonev_io_config + generic ( + lpm_type : string := "cyclonev_io_config" + ); + port ( + outputenabledelaysetting : out std_logic_vector(4 downto 0); + outputhalfratebypass : out std_logic; + datain : in std_logic := '0'; + readfifomode : out std_logic_vector(2 downto 0); + readfiforeadclockselect : out std_logic_vector(1 downto 0); + padtoinputregisterdelaysetting : out std_logic_vector(4 downto 0); + clk : in std_logic := '0'; + ena : in std_logic := '0'; + outputregdelaysetting : out std_logic_vector(4 downto 0); + dataout : out std_logic; + update : in std_logic := '0' + ); +END COMPONENT; + +-- +-- cyclonev_leveling_delay_chain +-- + +COMPONENT cyclonev_leveling_delay_chain + generic ( + physical_clock_source : string := "dqs"; + sim_buffer_intrinsic_delay : integer := 175; + sim_buffer_delay_increment : integer := 10 + ); + port ( + clkin : in std_logic := '0'; + delayctrlin : in std_logic_vector(6 downto 0) := (OTHERS => '0'); + clkout : out std_logic_vector(3 downto 0) + ); +END COMPONENT; + +-- +-- cyclonev_mem_phy +-- + +COMPONENT cyclonev_mem_phy + generic ( + hphy_use_hphy : string := "true"; + hphy_reset_delay_en : string := "false"; + hphy_hhp_hps : string := "false"; + hphy_wrap_back_en : string := "false"; + hphy_datapath_delay : string := "zero_cycles"; + hphy_datapath_ac_delay : string := "zero_cycles"; + m_hphy_ac_rom_init_file : string := "ac_ROM.hex"; + hphy_ac_ddr_disable : string := "true"; + hphy_csr_pipelineglobalenable : string := "true"; + m_hphy_inst_rom_init_file : string := "inst_ROM.hex"; + hphy_atpg_en : string := "false" + ); + port ( + iointaddrdout : in std_logic_vector(63 downto 0) := (OTHERS => '0'); + iointresetndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointckedout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirlat : out std_logic_vector(4 downto 0); + iointdqoe : in std_logic_vector(89 downto 0) := (OTHERS => '0'); + afiaddr : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + cfgtwr : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afidm : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiwdatavalid : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + avlread : in std_logic := '0'; + phyddiockndout : out std_logic_vector(3 downto 0); + iointckndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointbadout : in std_logic_vector(11 downto 0) := (OTHERS => '0'); + cfgdevicewidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + cfgcoladdrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointdqdin : out std_logic_vector(179 downto 0); + scanen : in std_logic := '0'; + afiwlat : out std_logic_vector(3 downto 0); + phyddiodqsoe : out std_logic_vector(9 downto 0); + cfgaddlat : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirdataen : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + phyddiodqslogicincrdataen : out std_logic_vector(9 downto 0); + phyddiodqslogicoct : out std_logic_vector(9 downto 0); + iointdqsoe : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicaclrpstamble : out std_logic_vector(4 downto 0); + phyddiodqsboe : out std_logic_vector(9 downto 0); + phyddiodqdout : out std_logic_vector(179 downto 0); + iointaficalfail : out std_logic; + avlwritedata : in std_logic_vector(31 downto 0) := (OTHERS => '0'); + iointdqsboe : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicreadlatency : out std_logic_vector(24 downto 0); + iointwendout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + afiodt : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + iointcsndout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiorasndout : out std_logic_vector(3 downto 0); + phyddiocsndout : out std_logic_vector(7 downto 0); + iointdqslogicoct : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + softresetn : in std_logic := '0'; + phyddiodqsdout : out std_logic_vector(19 downto 0); + iointafiwlat : out std_logic_vector(3 downto 0); + iointdqslogicdqsena : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiba : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + phyddiodqslogicdqsena : out std_logic_vector(9 downto 0); + pllavlclk : in std_logic := '0'; + aficasn : in std_logic := '0'; + cfgbankaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiowendout : out std_logic_vector(3 downto 0); + phyddiockedout : out std_logic_vector(7 downto 0); + cfgdramconfig : in std_logic_vector(23 downto 0) := (OTHERS => '0'); + aficsn : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + avlwaitrequest : out std_logic; + phyddioodtdout : out std_logic_vector(7 downto 0); + ddiophydqslogicrdatavalid : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + avlwrite : in std_logic := '0'; + afirasn : in std_logic := '0'; + plladdrcmdclk : in std_logic := '0'; + phyddioaddrdout : out std_logic_vector(63 downto 0); + aficalfail : out std_logic; + afimemclkdisable : in std_logic := '0'; + afiwdata : in std_logic_vector(79 downto 0) := (OTHERS => '0'); + iointdqslogicreadlatency : in std_logic_vector(24 downto 0) := (OTHERS => '0'); + phyddiodmdout : out std_logic_vector(19 downto 0); + pllaficlk : in std_logic := '0'; + cfgtrfc : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointckdout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + aficke : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + iointrasndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + phyddioresetndout : out std_logic_vector(3 downto 0); + aficalsuccess : out std_logic; + ddiophydqdin : in std_logic_vector(179 downto 0) := (OTHERS => '0'); + iointcasndout : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + iointdqsdout : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + cfgcsaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiockdout : out std_logic_vector(3 downto 0); + avlreaddata : out std_logic_vector(31 downto 0); + afirdata : out std_logic_vector(79 downto 0); + phyresetn : out std_logic; + iointdqslogicincrdataen : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + afiwen : in std_logic := '0'; + globalresetn : in std_logic := '0'; + phyddiodqsbdout : out std_logic_vector(19 downto 0); + plllocked : in std_logic := '0'; + phyddiodqslogicfiforeset : out std_logic_vector(4 downto 0); + iointdqslogicfiforeset : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + iointodtdout : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointafirlat : out std_logic_vector(4 downto 0); + iointaficalsuccess : out std_logic; + iointdqdout : in std_logic_vector(179 downto 0) := (OTHERS => '0'); + cfgrowaddrwidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiodqslogicaclrfifoctrl : out std_logic_vector(4 downto 0); + phyddiobadout : out std_logic_vector(11 downto 0); + afirdatavalid : out std_logic; + cfgtrefi : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + cfgcaswrlat : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + afirstn : in std_logic := '0'; + avlresetn : in std_logic := '0'; + iointdqsbdout : in std_logic_vector(19 downto 0) := (OTHERS => '0'); + phyddiodqoe : out std_logic_vector(89 downto 0); + iointdqslogicrdatavalid : out std_logic_vector(4 downto 0); + avladdress : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + afidqsburst : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + iointdqslogicincwrptr : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + phyddiodqslogicincwrptr : out std_logic_vector(9 downto 0); + cfgtcl : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + ctlresetn : out std_logic; + cfginterfacewidth : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phyddiocasndout : out std_logic_vector(3 downto 0); + afirdataenfull : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + cfgtmrd : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + iointdmdout : in std_logic_vector(19 downto 0) := (OTHERS => '0') + ); +END COMPONENT; + +-- +-- cyclonev_phy_clkbuf +-- + +COMPONENT cyclonev_phy_clkbuf + port ( + outclk : out std_logic_vector(3 downto 0); + inclk : in std_logic_vector(3 downto 0) := (OTHERS => '0') + ); +END COMPONENT; + +-- +-- cyclonev_pll_dll_output +-- + +COMPONENT cyclonev_pll_dll_output + generic ( + pll_dll_src : string := "vss" + ); + port ( + cclk : in std_logic_vector(17 downto 0); + clkin : in std_logic_vector(3 downto 0) := "0000"; + clkout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_pll_dpa_output +-- + +COMPONENT cyclonev_pll_dpa_output + generic ( + output_clock_frequency : string := ""; + pll_vcoph_div : integer := 1 + ); + port ( + pd : in std_logic; + phin : in std_logic_vector(7 downto 0); + phout : out std_logic_vector(7 downto 0) + ); +END COMPONENT; + +-- +-- cyclonev_pll_extclk_output +-- + +COMPONENT cyclonev_pll_extclk_output + generic ( + pll_extclk_cnt_src : string := "vss"; + pll_extclk_enable : string := "true"; + pll_extclk_invert : string := "false" + ); + port ( + cclk : in std_logic_vector(17 downto 0); + clken : in std_logic := '0'; + mcnt0 : in std_logic := '0'; + mcnt1 : in std_logic := '0'; + extclk : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_pll_lvds_output +-- + +COMPONENT cyclonev_pll_lvds_output + generic ( + pll_loaden_coarse_dly : string := "0 ps"; + pll_loaden_fine_dly : string := "0 ps"; + pll_lvdsclk_coarse_dly : string := "0 ps"; + pll_lvdsclk_fine_dly : string := "0 ps"; + pll_loaden_enable_disable : string := "false"; + pll_lvdsclk_enable_disable : string := "false" + ); + port ( + ccout : in std_logic_vector(1 downto 0); + loaden : out std_logic; + lvdsclk : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_pll_output_counter +-- + +COMPONENT cyclonev_pll_output_counter + generic ( + duty_cycle : integer := 50; + output_clock_frequency : string := ""; + phase_shift : string := ""; + c_cnt_coarse_dly : string := "0 ps"; + c_cnt_fine_dly : string := "0 ps"; + c_cnt_in_src : string := "test_clk0"; + c_cnt_ph_mux_prst : integer := 0; + cnt_fpll_src : string := "fpll_0"; + c_cnt_prst : integer := 1; + dprio0_cnt_bypass_en : string := "false"; + dprio0_cnt_hi_div : integer := 1; + dprio0_cnt_lo_div : integer := 1; + dprio0_cnt_odd_div_even_duty_en : string := "false"; + fractional_pll_index : integer := 1; + output_counter_index : integer := 1 + ); + port ( + cascadein : in std_logic := '0'; + nen0 : in std_logic := '0'; + shift0 : in std_logic := '0'; + shiftdone0i : in std_logic := '0'; + shiften : in std_logic := '0'; + tclk0 : in std_logic := '0'; + up0 : in std_logic := '0'; + vco0ph : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + cascadeout : out std_logic; + divclk : out std_logic; + shiftdone0o : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_pll_reconfig +-- + +COMPONENT cyclonev_pll_reconfig + generic ( + fractional_pll_index : integer := 1 + ); + port ( + addr : in std_logic_vector(5 downto 0) := (OTHERS => '0'); + atpgmode : in std_logic := '0'; + byteen : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + clk : in std_logic := '0'; + cntnen : in std_logic := '0'; + cntsel : in std_logic_vector(4 downto 0) := (OTHERS => '0'); + din : in std_logic_vector(15 downto 0) := (OTHERS => '0'); + fpllcsrtest : in std_logic := '0'; + iocsrclkin : in std_logic := '0'; + iocsrdatain : in std_logic := '0'; + iocsren : in std_logic := '0'; + iocsrrstn : in std_logic := '0'; + mdiodis : in std_logic := '0'; + mhi : in std_logic_vector(7 downto 0) := (OTHERS => '0'); + phaseen : in std_logic := '0'; + read : in std_logic := '0'; + rstn : in std_logic := '0'; + scanen : in std_logic := '0'; + sershiftload : in std_logic := '0'; + shiftdonei : in std_logic := '0'; + updn : in std_logic := '0'; + write : in std_logic := '0'; + blockselect : out std_logic; + dout : out std_logic_vector(15 downto 0); + dprioout : out std_logic_vector(815 downto 0); + iocsrdataout : out std_logic; + iocsrenbuf : out std_logic; + iocsrrstnbuf : out std_logic; + phasedone : out std_logic; + shift : out std_logic; + shiften : out std_logic_vector(8 downto 0); + shiftenm : out std_logic; + up : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_pll_refclk_select +-- + +COMPONENT cyclonev_pll_refclk_select + generic ( + pll_auto_clk_sw_en : string := "false"; + pll_clk_loss_edge : string := "both_edges"; + pll_clk_loss_sw_en : string := "false"; + pll_clk_sw_dly : integer := 0; + pll_clkin_0_src : string := "ref_clk0"; + pll_clkin_1_src : string := "ref_clk1"; + pll_manu_clk_sw_en : string := "false"; + pll_sw_refclk_src : string := "clk_0" + ); + port ( + adjpllin : in std_logic := '0'; + cclk : in std_logic := '0'; + clkin : in std_logic_vector(3 downto 0) := (OTHERS => '0'); + coreclkin : in std_logic := '0'; + extswitch : in std_logic := '0'; + iqtxrxclkin : in std_logic := '0'; + plliqclkin : in std_logic := '0'; + refiqclk : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + rxiqclkin : in std_logic := '0'; + pllen : in std_logic := '0'; + clk0bad : out std_logic; + clk1bad : out std_logic; + clkout : out std_logic; + extswitchbuf : out std_logic; + pllclksel : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_termination_logic +-- + +COMPONENT cyclonev_termination_logic + generic ( + lpm_type : string := "cyclonev_termination_logic"; + a_iob_oct_test : string := "a_iob_oct_test_off" + ); + port ( + s2pload : in std_logic := '0'; + serdata : in std_logic := '0'; + scanenable : in std_logic := '0'; + scanin : in std_logic := '0'; + scanclk : in std_logic := '0'; + scanout : out std_logic; + seriesterminationcontrol : out std_logic_vector(15 downto 0); + parallelterminationcontrol : out std_logic_vector(15 downto 0) + ); +END COMPONENT; + +-- +-- cyclonev_termination +-- + +COMPONENT cyclonev_termination + generic ( + lpm_type : string := "cyclonev_termination"; + a_oct_nclrusr_inv : string := "a_oct_nclrusr_inv_off"; + a_oct_pwrdn : string := "true"; + a_oct_clkdiv : string := "a_oct_clkdiv_20"; + a_oct_intosc : string := "a_oct_intosc_2"; + a_oct_vref : string := "a_oct_vref_rupm_rdnm"; + a_oct_test_0 : string := "a_oct_test_0_off"; + a_oct_test_1 : string := "a_oct_test_1_off"; + a_oct_test_2 : string := "a_oct_test_2_off"; + a_oct_test_3 : string := "a_oct_test_3_off"; + a_oct_test_4 : string := "a_oct_test_4_off"; + a_oct_test_5 : string := "a_oct_test_5_off"; + a_oct_pllbiasen : string := "a_oct_pllbiasen_low"; + a_oct_usermode : string := "false" + ); + port ( + rzqin : in std_logic := '0'; + enserusr : in std_logic := '0'; + nclrusr : in std_logic := '0'; + clkenusr : in std_logic := '0'; + clkusr : in std_logic := '0'; + serdatafromcore : in std_logic := '0'; + scanclk : in std_logic := '0'; + otherenser : in std_logic_vector(8 downto 0) := (OTHERS => '0'); + serdataout : out std_logic; + enserout : out std_logic; + compoutrup : out std_logic; + compoutrdn : out std_logic; + serdatatocore : out std_logic; + scanin : out std_logic; + scanout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_asmiblock +-- + +COMPONENT cyclonev_asmiblock + generic ( + lpm_type : string := "cyclonev_asmiblock"; + enable_sim : string := "false" + ); + port ( + dclk : in std_logic; + sce : in std_logic; + oe : in std_logic; + data0out : in std_logic; + data1out : in std_logic; + data2out : in std_logic; + data3out : in std_logic; + data0oe : in std_logic; + data1oe : in std_logic; + data2oe : in std_logic; + data3oe : in std_logic; + data0in : out std_logic; + data1in : out std_logic; + data2in : out std_logic; + data3in : out std_logic; + spidclk : out std_logic; + spidataout : out std_logic_vector(3 downto 0); + spisce : out std_logic; + spidatain : in std_logic_vector(3 downto 0) + ); +END COMPONENT; + +-- +-- cyclonev_chipidblock +-- + +COMPONENT cyclonev_chipidblock + generic ( + lpm_type : string := "cyclonev_chipidblock"; + ID_VALUE : std_logic_vector(63 downto 0) := (others => '1') + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + regout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_controller +-- + +COMPONENT cyclonev_controller + generic ( + lpm_type : string := "cyclonev_controller" + ); + port ( + nceout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_crcblock +-- + +COMPONENT cyclonev_crcblock +generic ( + oscillator_divider : integer := 256; + error_delay : integer := 0; + error_dra_dl_bypass : string := "false"; + crc_deld_disable : string := "false"; + triple_adj_err_correction : string := "false"; + quad_adj_err_correction : string := "false"; + lpm_type : string := "cyclonev_crcblock" + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + crcerror : out std_logic; + regout : out std_logic; + endofedfullchip : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_jtag +-- + +COMPONENT cyclonev_jtag + generic ( + lpm_type : string := "cyclonev_jtag" + ); + port ( + tms : in std_logic := '0'; + tck : in std_logic := '0'; + tdi : in std_logic := '0'; + ntrst : in std_logic := '0'; + tdoutap : in std_logic := '0'; + tdouser : in std_logic := '0'; + tdo : out std_logic; + tmsutap : out std_logic; + tckutap : out std_logic; + tdiutap : out std_logic; + shiftuser : out std_logic; + clkdruser : out std_logic; + updateuser : out std_logic; + runidleuser : out std_logic; + usr1user : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_prblock +-- + +COMPONENT cyclonev_prblock + generic ( + lpm_type : string := "cyclonev_prblock" + ); + port ( + clk : in std_logic; + corectl : in std_logic; + prrequest : in std_logic; + data : in std_logic_vector(15 downto 0); + externalrequest : out std_logic; + error : out std_logic; + ready : out std_logic; + done : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_rublock +-- + +COMPONENT cyclonev_rublock + generic ( + sim_init_watchdog_value : integer := 0; + sim_init_status : integer := 0; + sim_init_config_is_application : string := "false"; + sim_init_watchdog_enabled : string := "false"; + lpm_type : string := "cyclonev_rublock" + ); + port ( + clk : in std_logic; + shiftnld : in std_logic; + captnupdt : in std_logic; + regin : in std_logic; + rsttimer : in std_logic; + rconfig : in std_logic; + regout : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_mac +-- + +COMPONENT cyclonev_mac + generic ( + ax_width : integer := 16; + ay_scan_in_width : integer := 16; + az_width : integer := 1; + bx_width : integer := 16; + by_width : integer := 16; + bz_width : integer := 1; + scan_out_width : integer := 1; + result_a_width : integer := 33; + result_b_width : integer := 1; + operation_mode : string := "m18x18_sumof2"; + mode_sub_location : integer := 0; + operand_source_max : string := "input"; + operand_source_may : string := "input"; + operand_source_mbx : string := "input"; + operand_source_mby : string := "input"; + preadder_subtract_a : string := "false"; + preadder_subtract_b : string := "false"; + signed_max : string := "false"; + signed_may : string := "false"; + signed_mbx : string := "false"; + signed_mby : string := "false"; + ay_use_scan_in : string := "false"; + by_use_scan_in : string := "false"; + delay_scan_out_ay : string := "false"; + delay_scan_out_by : string := "false"; + use_chainadder : string := "false"; + enable_double_accum : string := "false"; + load_const_value : integer := 0; + coef_a_0 : integer := 0; + coef_a_1 : integer := 0; + coef_a_2 : integer := 0; + coef_a_3 : integer := 0; + coef_a_4 : integer := 0; + coef_a_5 : integer := 0; + coef_a_6 : integer := 0; + coef_a_7 : integer := 0; + coef_b_0 : integer := 0; + coef_b_1 : integer := 0; + coef_b_2 : integer := 0; + coef_b_3 : integer := 0; + coef_b_4 : integer := 0; + coef_b_5 : integer := 0; + coef_b_6 : integer := 0; + coef_b_7 : integer := 0; + ax_clock : string := "none"; + ay_scan_in_clock : string := "none"; + az_clock : string := "none"; + bx_clock : string := "none"; + by_clock : string := "none"; + bz_clock : string := "none"; + coef_sel_a_clock : string := "none"; + coef_sel_b_clock : string := "none"; + sub_clock : string := "none"; + negate_clock : string := "none"; + accumulate_clock : string := "none"; + load_const_clock : string := "none"; + output_clock : string := "none" + ); + port ( + sub : in std_logic := '0'; + negate : in std_logic := '0'; + accumulate : in std_logic := '0'; + loadconst : in std_logic := '0'; + ax : in std_logic_vector(ax_width-1 downto 0) := (others => '0'); + ay : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0'); + scanin : in std_logic_vector(ay_scan_in_width-1 downto 0) := (others => '0'); + az : in std_logic_vector(az_width-1 downto 0) := (others => '0'); + bx : in std_logic_vector(bx_width-1 downto 0) := (others => '0'); + by : in std_logic_vector(by_width-1 downto 0) := (others => '0'); + bz : in std_logic_vector(bz_width-1 downto 0) := (others => '0'); + coefsela : in std_logic_vector(2 downto 0) := (others => '0'); + coefselb : in std_logic_vector(2 downto 0) := (others => '0'); + chainin : in std_logic_vector(63 downto 0) := (others => '0'); + clk : in std_logic_vector(2 downto 0) := (others => '0'); + aclr : in std_logic_vector(1 downto 0) := (others => '0'); + ena : in std_logic_vector(2 downto 0) := (others => '1'); + dftout : out std_logic; + resulta : out std_logic_vector(result_a_width-1 downto 0); + resultb : out std_logic_vector(result_b_width-1 downto 0); + scanout : out std_logic_vector(scan_out_width-1 downto 0); + chainout : out std_logic_vector(63 downto 0) + ); +END COMPONENT; + +-- +-- cyclonev_ir_fifo_userdes +-- + +COMPONENT cyclonev_ir_fifo_userdes + generic ( + a_rb_bypass_serializer : string := "false"; + a_use_dynamic_fifo_mode : string := "false"; + a_rb_fifo_mode : string := "serializer_mode"; + a_rb_data_width : integer := 9; + a_enable_soft_cdr : string := "false"; + a_rb_tx_outclk : string := "false"; + a_rb_bslipcfg : integer := 0; + a_sim_wclk_pre_delay : integer := 0; + a_sim_readenable_pre_delay : integer := 0 + ); + port ( + bslipmax : out std_logic; + dynfifomode : in std_logic_vector(2 downto 0) := (OTHERS => '0'); + observableout : out std_logic; + writeenable : in std_logic := '0'; + readclk : in std_logic := '0'; + txin : in std_logic_vector(9 downto 0) := (OTHERS => '0'); + regscanovrd : in std_logic := '0'; + rxout : out std_logic_vector(9 downto 0); + bslipout : out std_logic; + rstn : in std_logic := '0'; + loaden : in std_logic := '0'; + lvdsmodeen : out std_logic; + bslipctl : in std_logic := '0'; + observablefout3 : out std_logic; + scanin : in std_logic := '0'; + readenable : in std_logic := '0'; + scanout : out std_logic; + writeclk : in std_logic := '0'; + observablefout2 : out std_logic; + dinfiforx : in std_logic_vector(1 downto 0) := (OTHERS => '0'); + tstclk : in std_logic := '0'; + observablefout4 : out std_logic; + observablefout1 : out std_logic; + dout : out std_logic_vector(3 downto 0); + bslipin : in std_logic := '0'; + txout : out std_logic; + regscan : in std_logic := '0'; + observablewaddrcnt : out std_logic; + lvdstxsel : out std_logic + ); +END COMPONENT; + +-- +-- cyclonev_oscillator +-- + +COMPONENT cyclonev_oscillator + generic ( + lpm_type : string := "cyclonev_oscillator"); + port ( + oscena : in std_logic; + clkout : out std_logic; + clkout1 : out std_logic + ); +END COMPONENT; + +end cyclonev_components; diff --git a/Common/sim/altera/cyclonev_hssi_atoms.vhd b/Common/sim/altera/cyclonev_hssi_atoms.vhd new file mode 100644 index 0000000..7392485 --- /dev/null +++ b/Common/sim/altera/cyclonev_hssi_atoms.vhd @@ -0,0 +1,6299 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- This simulation model contains highly confidential and +-- proprietary information of Altera and is being provided +-- in accordance with and subject to the protections of the +-- applicable Altera Program License Subscription Agreement +-- which governs its use and disclosure. Your use of Altera +-- Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, +-- and any output files any of the foregoing (including device +-- programming or simulation files), and any associated +-- documentation or information are expressly subject to the +-- terms and conditions of the Altera Program License Subscription +-- Agreement, the Altera Quartus II License Agreement, the Altera +-- MegaCore Function License Agreement, or other applicable +-- license agreement, including, without limitation, that your +-- use is for the sole purpose of simulating designs for use +-- exclusively in logic devices manufactured by Altera and sold +-- by Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. Altera products and +-- services are protected under numerous U.S. and foreign patents, +-- maskwork rights, copyrights and other intellectual property laws. +-- Altera assumes no responsibility or liability arising out of the +-- application or use of this simulation model. +-- Quartus II 15.0.0 Build 145 04/22/2015 +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_8g_pcs_aggregate is + generic ( + enable_debug_info : string := "false"; + xaui_sm_operation : string := "en_xaui_sm"; + dskw_sm_operation : string := "dskw_xaui_sm"; + data_agg_bonding : string := "agg_disable"; + prot_mode_tx : string := "pipe_g1_tx"; + pcs_dw_datapath : string := "sw_data_path"; + dskw_control : string := "dskw_write_control"; + refclkdig_sel : string := "dis_refclk_dig_sel"; + agg_pwdn : string := "dis_agg_pwdn"; + dskw_mnumber_data : bit_vector := B"100"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + aligndetsyncbotch2 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch0 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch1 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch2 : in std_logic_vector(1 downto 0) := "00"; + aligndetsynctopch0 : in std_logic_vector(1 downto 0) := "00"; + aligndetsynctopch1 : in std_logic_vector(1 downto 0) := "00"; + alignstatussyncbotch2 : in std_logic := '0'; + alignstatussyncch0 : in std_logic := '0'; + alignstatussyncch1 : in std_logic := '0'; + alignstatussyncch2 : in std_logic := '0'; + alignstatussynctopch0 : in std_logic := '0'; + alignstatussynctopch1 : in std_logic := '0'; + cgcomprddinbotch2 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch0 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch1 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch2 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddintopch0 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddintopch1 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinbotch2 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch0 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch1 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch2 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrintopch0 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrintopch1 : in std_logic_vector(1 downto 0) := "00"; + decctlbotch2 : in std_logic := '0'; + decctlch0 : in std_logic := '0'; + decctlch1 : in std_logic := '0'; + decctlch2 : in std_logic := '0'; + decctltopch0 : in std_logic := '0'; + decctltopch1 : in std_logic := '0'; + decdatabotch2 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach0 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach1 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach2 : in std_logic_vector(7 downto 0) := "00000000"; + decdatatopch0 : in std_logic_vector(7 downto 0) := "00000000"; + decdatatopch1 : in std_logic_vector(7 downto 0) := "00000000"; + decdatavalidbotch2 : in std_logic := '0'; + decdatavalidch0 : in std_logic := '0'; + decdatavalidch1 : in std_logic := '0'; + decdatavalidch2 : in std_logic := '0'; + decdatavalidtopch0 : in std_logic := '0'; + decdatavalidtopch1 : in std_logic := '0'; + dedicatedaggscaninch1 : in std_logic := '0'; + delcondmetinbotch2 : in std_logic := '0'; + delcondmetinch0 : in std_logic := '0'; + delcondmetinch1 : in std_logic := '0'; + delcondmetinch2 : in std_logic := '0'; + delcondmetintopch0 : in std_logic := '0'; + delcondmetintopch1 : in std_logic := '0'; + dprioagg : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + fifoovrinbotch2 : in std_logic := '0'; + fifoovrinch0 : in std_logic := '0'; + fifoovrinch1 : in std_logic := '0'; + fifoovrinch2 : in std_logic := '0'; + fifoovrintopch0 : in std_logic := '0'; + fifoovrintopch1 : in std_logic := '0'; + fifordinbotch2 : in std_logic := '0'; + fifordinch0 : in std_logic := '0'; + fifordinch1 : in std_logic := '0'; + fifordinch2 : in std_logic := '0'; + fifordintopch0 : in std_logic := '0'; + fifordintopch1 : in std_logic := '0'; + insertincompleteinbotch2 : in std_logic := '0'; + insertincompleteinch0 : in std_logic := '0'; + insertincompleteinch1 : in std_logic := '0'; + insertincompleteinch2 : in std_logic := '0'; + insertincompleteintopch0 : in std_logic := '0'; + insertincompleteintopch1 : in std_logic := '0'; + latencycompinbotch2 : in std_logic := '0'; + latencycompinch0 : in std_logic := '0'; + latencycompinch1 : in std_logic := '0'; + latencycompinch2 : in std_logic := '0'; + latencycompintopch0 : in std_logic := '0'; + latencycompintopch1 : in std_logic := '0'; + rcvdclkch0 : in std_logic := '0'; + rcvdclkch1 : in std_logic := '0'; + rdalignbotch2 : in std_logic_vector(1 downto 0) := "00"; + rdalignch0 : in std_logic_vector(1 downto 0) := "00"; + rdalignch1 : in std_logic_vector(1 downto 0) := "00"; + rdalignch2 : in std_logic_vector(1 downto 0) := "00"; + rdaligntopch0 : in std_logic_vector(1 downto 0) := "00"; + rdaligntopch1 : in std_logic_vector(1 downto 0) := "00"; + rdenablesyncbotch2 : in std_logic := '0'; + rdenablesyncch0 : in std_logic := '0'; + rdenablesyncch1 : in std_logic := '0'; + rdenablesyncch2 : in std_logic := '0'; + rdenablesynctopch0 : in std_logic := '0'; + rdenablesynctopch1 : in std_logic := '0'; + refclkdig : in std_logic := '0'; + runningdispbotch2 : in std_logic_vector(1 downto 0) := "00"; + runningdispch0 : in std_logic_vector(1 downto 0) := "00"; + runningdispch1 : in std_logic_vector(1 downto 0) := "00"; + runningdispch2 : in std_logic_vector(1 downto 0) := "00"; + runningdisptopch0 : in std_logic_vector(1 downto 0) := "00"; + runningdisptopch1 : in std_logic_vector(1 downto 0) := "00"; + rxpcsrstn : in std_logic := '0'; + scanmoden : in std_logic := '0'; + scanshiftn : in std_logic := '0'; + syncstatusbotch2 : in std_logic := '0'; + syncstatusch0 : in std_logic := '0'; + syncstatusch1 : in std_logic := '0'; + syncstatusch2 : in std_logic := '0'; + syncstatustopch0 : in std_logic := '0'; + syncstatustopch1 : in std_logic := '0'; + txctltcbotch2 : in std_logic := '0'; + txctltcch0 : in std_logic := '0'; + txctltcch1 : in std_logic := '0'; + txctltcch2 : in std_logic := '0'; + txctltctopch0 : in std_logic := '0'; + txctltctopch1 : in std_logic := '0'; + txdatatcbotch2 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch0 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch1 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch2 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatctopch0 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatctopch1 : in std_logic_vector(7 downto 0) := "00000000"; + txpcsrstn : in std_logic := '0'; + txpmaclk : in std_logic := '0'; + aggtestbusch0 : out std_logic_vector(15 downto 0) := "0000000000000000"; + aggtestbusch1 : out std_logic_vector(15 downto 0) := "0000000000000000"; + aggtestbusch2 : out std_logic_vector(15 downto 0) := "0000000000000000"; + alignstatusbotch2 : out std_logic := '0'; + alignstatusch0 : out std_logic := '0'; + alignstatusch1 : out std_logic := '0'; + alignstatusch2 : out std_logic := '0'; + alignstatussync0botch2 : out std_logic := '0'; + alignstatussync0ch0 : out std_logic := '0'; + alignstatussync0ch1 : out std_logic := '0'; + alignstatussync0ch2 : out std_logic := '0'; + alignstatussync0topch0 : out std_logic := '0'; + alignstatussync0topch1 : out std_logic := '0'; + alignstatustopch0 : out std_logic := '0'; + alignstatustopch1 : out std_logic := '0'; + cgcomprddallbotch2 : out std_logic := '0'; + cgcomprddallch0 : out std_logic := '0'; + cgcomprddallch1 : out std_logic := '0'; + cgcomprddallch2 : out std_logic := '0'; + cgcomprddalltopch0 : out std_logic := '0'; + cgcomprddalltopch1 : out std_logic := '0'; + cgcompwrallbotch2 : out std_logic := '0'; + cgcompwrallch0 : out std_logic := '0'; + cgcompwrallch1 : out std_logic := '0'; + cgcompwrallch2 : out std_logic := '0'; + cgcompwralltopch0 : out std_logic := '0'; + cgcompwralltopch1 : out std_logic := '0'; + dedicatedaggscanoutch0tieoff : out std_logic := '0'; + dedicatedaggscanoutch1 : out std_logic := '0'; + dedicatedaggscanoutch2tieoff : out std_logic := '0'; + delcondmet0botch2 : out std_logic := '0'; + delcondmet0ch0 : out std_logic := '0'; + delcondmet0ch1 : out std_logic := '0'; + delcondmet0ch2 : out std_logic := '0'; + delcondmet0topch0 : out std_logic := '0'; + delcondmet0topch1 : out std_logic := '0'; + endskwqdbotch2 : out std_logic := '0'; + endskwqdch0 : out std_logic := '0'; + endskwqdch1 : out std_logic := '0'; + endskwqdch2 : out std_logic := '0'; + endskwqdtopch0 : out std_logic := '0'; + endskwqdtopch1 : out std_logic := '0'; + endskwrdptrsbotch2 : out std_logic := '0'; + endskwrdptrsch0 : out std_logic := '0'; + endskwrdptrsch1 : out std_logic := '0'; + endskwrdptrsch2 : out std_logic := '0'; + endskwrdptrstopch0 : out std_logic := '0'; + endskwrdptrstopch1 : out std_logic := '0'; + fifoovr0botch2 : out std_logic := '0'; + fifoovr0ch0 : out std_logic := '0'; + fifoovr0ch1 : out std_logic := '0'; + fifoovr0ch2 : out std_logic := '0'; + fifoovr0topch0 : out std_logic := '0'; + fifoovr0topch1 : out std_logic := '0'; + fifordoutcomp0botch2 : out std_logic := '0'; + fifordoutcomp0ch0 : out std_logic := '0'; + fifordoutcomp0ch1 : out std_logic := '0'; + fifordoutcomp0ch2 : out std_logic := '0'; + fifordoutcomp0topch0 : out std_logic := '0'; + fifordoutcomp0topch1 : out std_logic := '0'; + fiforstrdqdbotch2 : out std_logic := '0'; + fiforstrdqdch0 : out std_logic := '0'; + fiforstrdqdch1 : out std_logic := '0'; + fiforstrdqdch2 : out std_logic := '0'; + fiforstrdqdtopch0 : out std_logic := '0'; + fiforstrdqdtopch1 : out std_logic := '0'; + insertincomplete0botch2 : out std_logic := '0'; + insertincomplete0ch0 : out std_logic := '0'; + insertincomplete0ch1 : out std_logic := '0'; + insertincomplete0ch2 : out std_logic := '0'; + insertincomplete0topch0 : out std_logic := '0'; + insertincomplete0topch1 : out std_logic := '0'; + latencycomp0botch2 : out std_logic := '0'; + latencycomp0ch0 : out std_logic := '0'; + latencycomp0ch1 : out std_logic := '0'; + latencycomp0ch2 : out std_logic := '0'; + latencycomp0topch0 : out std_logic := '0'; + latencycomp0topch1 : out std_logic := '0'; + rcvdclkout : out std_logic := '0'; + rcvdclkoutbot : out std_logic := '0'; + rcvdclkouttop : out std_logic := '0'; + rxctlrsbotch2 : out std_logic := '0'; + rxctlrsch0 : out std_logic := '0'; + rxctlrsch1 : out std_logic := '0'; + rxctlrsch2 : out std_logic := '0'; + rxctlrstopch0 : out std_logic := '0'; + rxctlrstopch1 : out std_logic := '0'; + rxdatarsbotch2 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch0 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch1 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch2 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarstopch0 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarstopch1 : out std_logic_vector(7 downto 0) := "00000000"; + txctltsbotch2 : out std_logic := '0'; + txctltsch0 : out std_logic := '0'; + txctltsch1 : out std_logic := '0'; + txctltsch2 : out std_logic := '0'; + txctltstopch0 : out std_logic := '0'; + txctltstopch1 : out std_logic := '0'; + txdatatsbotch2 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch0 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch1 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch2 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatstopch0 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatstopch1 : out std_logic_vector(7 downto 0) := "00000000" + ); +end cyclonev_hssi_8g_pcs_aggregate; + +architecture behavior of cyclonev_hssi_8g_pcs_aggregate is + +component cyclonev_hssi_8g_pcs_aggregate_encrypted + generic ( + enable_debug_info : string := "false"; + xaui_sm_operation : string := "en_xaui_sm"; + dskw_sm_operation : string := "dskw_xaui_sm"; + data_agg_bonding : string := "agg_disable"; + prot_mode_tx : string := "pipe_g1_tx"; + pcs_dw_datapath : string := "sw_data_path"; + dskw_control : string := "dskw_write_control"; + refclkdig_sel : string := "dis_refclk_dig_sel"; + agg_pwdn : string := "dis_agg_pwdn"; + dskw_mnumber_data : bit_vector := B"100"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + aligndetsyncbotch2 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch0 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch1 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch2 : in std_logic_vector(1 downto 0) := "00"; + aligndetsynctopch0 : in std_logic_vector(1 downto 0) := "00"; + aligndetsynctopch1 : in std_logic_vector(1 downto 0) := "00"; + alignstatussyncbotch2 : in std_logic := '0'; + alignstatussyncch0 : in std_logic := '0'; + alignstatussyncch1 : in std_logic := '0'; + alignstatussyncch2 : in std_logic := '0'; + alignstatussynctopch0 : in std_logic := '0'; + alignstatussynctopch1 : in std_logic := '0'; + cgcomprddinbotch2 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch0 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch1 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch2 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddintopch0 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddintopch1 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinbotch2 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch0 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch1 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch2 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrintopch0 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrintopch1 : in std_logic_vector(1 downto 0) := "00"; + decctlbotch2 : in std_logic := '0'; + decctlch0 : in std_logic := '0'; + decctlch1 : in std_logic := '0'; + decctlch2 : in std_logic := '0'; + decctltopch0 : in std_logic := '0'; + decctltopch1 : in std_logic := '0'; + decdatabotch2 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach0 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach1 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach2 : in std_logic_vector(7 downto 0) := "00000000"; + decdatatopch0 : in std_logic_vector(7 downto 0) := "00000000"; + decdatatopch1 : in std_logic_vector(7 downto 0) := "00000000"; + decdatavalidbotch2 : in std_logic := '0'; + decdatavalidch0 : in std_logic := '0'; + decdatavalidch1 : in std_logic := '0'; + decdatavalidch2 : in std_logic := '0'; + decdatavalidtopch0 : in std_logic := '0'; + decdatavalidtopch1 : in std_logic := '0'; + dedicatedaggscaninch1 : in std_logic := '0'; + delcondmetinbotch2 : in std_logic := '0'; + delcondmetinch0 : in std_logic := '0'; + delcondmetinch1 : in std_logic := '0'; + delcondmetinch2 : in std_logic := '0'; + delcondmetintopch0 : in std_logic := '0'; + delcondmetintopch1 : in std_logic := '0'; + dprioagg : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + fifoovrinbotch2 : in std_logic := '0'; + fifoovrinch0 : in std_logic := '0'; + fifoovrinch1 : in std_logic := '0'; + fifoovrinch2 : in std_logic := '0'; + fifoovrintopch0 : in std_logic := '0'; + fifoovrintopch1 : in std_logic := '0'; + fifordinbotch2 : in std_logic := '0'; + fifordinch0 : in std_logic := '0'; + fifordinch1 : in std_logic := '0'; + fifordinch2 : in std_logic := '0'; + fifordintopch0 : in std_logic := '0'; + fifordintopch1 : in std_logic := '0'; + insertincompleteinbotch2 : in std_logic := '0'; + insertincompleteinch0 : in std_logic := '0'; + insertincompleteinch1 : in std_logic := '0'; + insertincompleteinch2 : in std_logic := '0'; + insertincompleteintopch0 : in std_logic := '0'; + insertincompleteintopch1 : in std_logic := '0'; + latencycompinbotch2 : in std_logic := '0'; + latencycompinch0 : in std_logic := '0'; + latencycompinch1 : in std_logic := '0'; + latencycompinch2 : in std_logic := '0'; + latencycompintopch0 : in std_logic := '0'; + latencycompintopch1 : in std_logic := '0'; + rcvdclkch0 : in std_logic := '0'; + rcvdclkch1 : in std_logic := '0'; + rdalignbotch2 : in std_logic_vector(1 downto 0) := "00"; + rdalignch0 : in std_logic_vector(1 downto 0) := "00"; + rdalignch1 : in std_logic_vector(1 downto 0) := "00"; + rdalignch2 : in std_logic_vector(1 downto 0) := "00"; + rdaligntopch0 : in std_logic_vector(1 downto 0) := "00"; + rdaligntopch1 : in std_logic_vector(1 downto 0) := "00"; + rdenablesyncbotch2 : in std_logic := '0'; + rdenablesyncch0 : in std_logic := '0'; + rdenablesyncch1 : in std_logic := '0'; + rdenablesyncch2 : in std_logic := '0'; + rdenablesynctopch0 : in std_logic := '0'; + rdenablesynctopch1 : in std_logic := '0'; + refclkdig : in std_logic := '0'; + runningdispbotch2 : in std_logic_vector(1 downto 0) := "00"; + runningdispch0 : in std_logic_vector(1 downto 0) := "00"; + runningdispch1 : in std_logic_vector(1 downto 0) := "00"; + runningdispch2 : in std_logic_vector(1 downto 0) := "00"; + runningdisptopch0 : in std_logic_vector(1 downto 0) := "00"; + runningdisptopch1 : in std_logic_vector(1 downto 0) := "00"; + rxpcsrstn : in std_logic := '0'; + scanmoden : in std_logic := '0'; + scanshiftn : in std_logic := '0'; + syncstatusbotch2 : in std_logic := '0'; + syncstatusch0 : in std_logic := '0'; + syncstatusch1 : in std_logic := '0'; + syncstatusch2 : in std_logic := '0'; + syncstatustopch0 : in std_logic := '0'; + syncstatustopch1 : in std_logic := '0'; + txctltcbotch2 : in std_logic := '0'; + txctltcch0 : in std_logic := '0'; + txctltcch1 : in std_logic := '0'; + txctltcch2 : in std_logic := '0'; + txctltctopch0 : in std_logic := '0'; + txctltctopch1 : in std_logic := '0'; + txdatatcbotch2 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch0 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch1 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch2 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatctopch0 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatctopch1 : in std_logic_vector(7 downto 0) := "00000000"; + txpcsrstn : in std_logic := '0'; + txpmaclk : in std_logic := '0'; + aggtestbusch0 : out std_logic_vector(15 downto 0) := "0000000000000000"; + aggtestbusch1 : out std_logic_vector(15 downto 0) := "0000000000000000"; + aggtestbusch2 : out std_logic_vector(15 downto 0) := "0000000000000000"; + alignstatusbotch2 : out std_logic := '0'; + alignstatusch0 : out std_logic := '0'; + alignstatusch1 : out std_logic := '0'; + alignstatusch2 : out std_logic := '0'; + alignstatussync0botch2 : out std_logic := '0'; + alignstatussync0ch0 : out std_logic := '0'; + alignstatussync0ch1 : out std_logic := '0'; + alignstatussync0ch2 : out std_logic := '0'; + alignstatussync0topch0 : out std_logic := '0'; + alignstatussync0topch1 : out std_logic := '0'; + alignstatustopch0 : out std_logic := '0'; + alignstatustopch1 : out std_logic := '0'; + cgcomprddallbotch2 : out std_logic := '0'; + cgcomprddallch0 : out std_logic := '0'; + cgcomprddallch1 : out std_logic := '0'; + cgcomprddallch2 : out std_logic := '0'; + cgcomprddalltopch0 : out std_logic := '0'; + cgcomprddalltopch1 : out std_logic := '0'; + cgcompwrallbotch2 : out std_logic := '0'; + cgcompwrallch0 : out std_logic := '0'; + cgcompwrallch1 : out std_logic := '0'; + cgcompwrallch2 : out std_logic := '0'; + cgcompwralltopch0 : out std_logic := '0'; + cgcompwralltopch1 : out std_logic := '0'; + dedicatedaggscanoutch0tieoff : out std_logic := '0'; + dedicatedaggscanoutch1 : out std_logic := '0'; + dedicatedaggscanoutch2tieoff : out std_logic := '0'; + delcondmet0botch2 : out std_logic := '0'; + delcondmet0ch0 : out std_logic := '0'; + delcondmet0ch1 : out std_logic := '0'; + delcondmet0ch2 : out std_logic := '0'; + delcondmet0topch0 : out std_logic := '0'; + delcondmet0topch1 : out std_logic := '0'; + endskwqdbotch2 : out std_logic := '0'; + endskwqdch0 : out std_logic := '0'; + endskwqdch1 : out std_logic := '0'; + endskwqdch2 : out std_logic := '0'; + endskwqdtopch0 : out std_logic := '0'; + endskwqdtopch1 : out std_logic := '0'; + endskwrdptrsbotch2 : out std_logic := '0'; + endskwrdptrsch0 : out std_logic := '0'; + endskwrdptrsch1 : out std_logic := '0'; + endskwrdptrsch2 : out std_logic := '0'; + endskwrdptrstopch0 : out std_logic := '0'; + endskwrdptrstopch1 : out std_logic := '0'; + fifoovr0botch2 : out std_logic := '0'; + fifoovr0ch0 : out std_logic := '0'; + fifoovr0ch1 : out std_logic := '0'; + fifoovr0ch2 : out std_logic := '0'; + fifoovr0topch0 : out std_logic := '0'; + fifoovr0topch1 : out std_logic := '0'; + fifordoutcomp0botch2 : out std_logic := '0'; + fifordoutcomp0ch0 : out std_logic := '0'; + fifordoutcomp0ch1 : out std_logic := '0'; + fifordoutcomp0ch2 : out std_logic := '0'; + fifordoutcomp0topch0 : out std_logic := '0'; + fifordoutcomp0topch1 : out std_logic := '0'; + fiforstrdqdbotch2 : out std_logic := '0'; + fiforstrdqdch0 : out std_logic := '0'; + fiforstrdqdch1 : out std_logic := '0'; + fiforstrdqdch2 : out std_logic := '0'; + fiforstrdqdtopch0 : out std_logic := '0'; + fiforstrdqdtopch1 : out std_logic := '0'; + insertincomplete0botch2 : out std_logic := '0'; + insertincomplete0ch0 : out std_logic := '0'; + insertincomplete0ch1 : out std_logic := '0'; + insertincomplete0ch2 : out std_logic := '0'; + insertincomplete0topch0 : out std_logic := '0'; + insertincomplete0topch1 : out std_logic := '0'; + latencycomp0botch2 : out std_logic := '0'; + latencycomp0ch0 : out std_logic := '0'; + latencycomp0ch1 : out std_logic := '0'; + latencycomp0ch2 : out std_logic := '0'; + latencycomp0topch0 : out std_logic := '0'; + latencycomp0topch1 : out std_logic := '0'; + rcvdclkout : out std_logic := '0'; + rcvdclkoutbot : out std_logic := '0'; + rcvdclkouttop : out std_logic := '0'; + rxctlrsbotch2 : out std_logic := '0'; + rxctlrsch0 : out std_logic := '0'; + rxctlrsch1 : out std_logic := '0'; + rxctlrsch2 : out std_logic := '0'; + rxctlrstopch0 : out std_logic := '0'; + rxctlrstopch1 : out std_logic := '0'; + rxdatarsbotch2 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch0 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch1 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch2 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarstopch0 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarstopch1 : out std_logic_vector(7 downto 0) := "00000000"; + txctltsbotch2 : out std_logic := '0'; + txctltsch0 : out std_logic := '0'; + txctltsch1 : out std_logic := '0'; + txctltsch2 : out std_logic := '0'; + txctltstopch0 : out std_logic := '0'; + txctltstopch1 : out std_logic := '0'; + txdatatsbotch2 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch0 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch1 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch2 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatstopch0 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatstopch1 : out std_logic_vector(7 downto 0) := "00000000" + ); +end component; + +begin + + +inst : cyclonev_hssi_8g_pcs_aggregate_encrypted + generic map ( + enable_debug_info => enable_debug_info, + xaui_sm_operation => xaui_sm_operation, + dskw_sm_operation => dskw_sm_operation, + data_agg_bonding => data_agg_bonding, + prot_mode_tx => prot_mode_tx, + pcs_dw_datapath => pcs_dw_datapath, + dskw_control => dskw_control, + refclkdig_sel => refclkdig_sel, + agg_pwdn => agg_pwdn, + dskw_mnumber_data => dskw_mnumber_data, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + aligndetsyncbotch2 => aligndetsyncbotch2, + aligndetsyncch0 => aligndetsyncch0, + aligndetsyncch1 => aligndetsyncch1, + aligndetsyncch2 => aligndetsyncch2, + aligndetsynctopch0 => aligndetsynctopch0, + aligndetsynctopch1 => aligndetsynctopch1, + alignstatussyncbotch2 => alignstatussyncbotch2, + alignstatussyncch0 => alignstatussyncch0, + alignstatussyncch1 => alignstatussyncch1, + alignstatussyncch2 => alignstatussyncch2, + alignstatussynctopch0 => alignstatussynctopch0, + alignstatussynctopch1 => alignstatussynctopch1, + cgcomprddinbotch2 => cgcomprddinbotch2, + cgcomprddinch0 => cgcomprddinch0, + cgcomprddinch1 => cgcomprddinch1, + cgcomprddinch2 => cgcomprddinch2, + cgcomprddintopch0 => cgcomprddintopch0, + cgcomprddintopch1 => cgcomprddintopch1, + cgcompwrinbotch2 => cgcompwrinbotch2, + cgcompwrinch0 => cgcompwrinch0, + cgcompwrinch1 => cgcompwrinch1, + cgcompwrinch2 => cgcompwrinch2, + cgcompwrintopch0 => cgcompwrintopch0, + cgcompwrintopch1 => cgcompwrintopch1, + decctlbotch2 => decctlbotch2, + decctlch0 => decctlch0, + decctlch1 => decctlch1, + decctlch2 => decctlch2, + decctltopch0 => decctltopch0, + decctltopch1 => decctltopch1, + decdatabotch2 => decdatabotch2, + decdatach0 => decdatach0, + decdatach1 => decdatach1, + decdatach2 => decdatach2, + decdatatopch0 => decdatatopch0, + decdatatopch1 => decdatatopch1, + decdatavalidbotch2 => decdatavalidbotch2, + decdatavalidch0 => decdatavalidch0, + decdatavalidch1 => decdatavalidch1, + decdatavalidch2 => decdatavalidch2, + decdatavalidtopch0 => decdatavalidtopch0, + decdatavalidtopch1 => decdatavalidtopch1, + dedicatedaggscaninch1 => dedicatedaggscaninch1, + delcondmetinbotch2 => delcondmetinbotch2, + delcondmetinch0 => delcondmetinch0, + delcondmetinch1 => delcondmetinch1, + delcondmetinch2 => delcondmetinch2, + delcondmetintopch0 => delcondmetintopch0, + delcondmetintopch1 => delcondmetintopch1, + dprioagg => dprioagg, + fifoovrinbotch2 => fifoovrinbotch2, + fifoovrinch0 => fifoovrinch0, + fifoovrinch1 => fifoovrinch1, + fifoovrinch2 => fifoovrinch2, + fifoovrintopch0 => fifoovrintopch0, + fifoovrintopch1 => fifoovrintopch1, + fifordinbotch2 => fifordinbotch2, + fifordinch0 => fifordinch0, + fifordinch1 => fifordinch1, + fifordinch2 => fifordinch2, + fifordintopch0 => fifordintopch0, + fifordintopch1 => fifordintopch1, + insertincompleteinbotch2 => insertincompleteinbotch2, + insertincompleteinch0 => insertincompleteinch0, + insertincompleteinch1 => insertincompleteinch1, + insertincompleteinch2 => insertincompleteinch2, + insertincompleteintopch0 => insertincompleteintopch0, + insertincompleteintopch1 => insertincompleteintopch1, + latencycompinbotch2 => latencycompinbotch2, + latencycompinch0 => latencycompinch0, + latencycompinch1 => latencycompinch1, + latencycompinch2 => latencycompinch2, + latencycompintopch0 => latencycompintopch0, + latencycompintopch1 => latencycompintopch1, + rcvdclkch0 => rcvdclkch0, + rcvdclkch1 => rcvdclkch1, + rdalignbotch2 => rdalignbotch2, + rdalignch0 => rdalignch0, + rdalignch1 => rdalignch1, + rdalignch2 => rdalignch2, + rdaligntopch0 => rdaligntopch0, + rdaligntopch1 => rdaligntopch1, + rdenablesyncbotch2 => rdenablesyncbotch2, + rdenablesyncch0 => rdenablesyncch0, + rdenablesyncch1 => rdenablesyncch1, + rdenablesyncch2 => rdenablesyncch2, + rdenablesynctopch0 => rdenablesynctopch0, + rdenablesynctopch1 => rdenablesynctopch1, + refclkdig => refclkdig, + runningdispbotch2 => runningdispbotch2, + runningdispch0 => runningdispch0, + runningdispch1 => runningdispch1, + runningdispch2 => runningdispch2, + runningdisptopch0 => runningdisptopch0, + runningdisptopch1 => runningdisptopch1, + rxpcsrstn => rxpcsrstn, + scanmoden => scanmoden, + scanshiftn => scanshiftn, + syncstatusbotch2 => syncstatusbotch2, + syncstatusch0 => syncstatusch0, + syncstatusch1 => syncstatusch1, + syncstatusch2 => syncstatusch2, + syncstatustopch0 => syncstatustopch0, + syncstatustopch1 => syncstatustopch1, + txctltcbotch2 => txctltcbotch2, + txctltcch0 => txctltcch0, + txctltcch1 => txctltcch1, + txctltcch2 => txctltcch2, + txctltctopch0 => txctltctopch0, + txctltctopch1 => txctltctopch1, + txdatatcbotch2 => txdatatcbotch2, + txdatatcch0 => txdatatcch0, + txdatatcch1 => txdatatcch1, + txdatatcch2 => txdatatcch2, + txdatatctopch0 => txdatatctopch0, + txdatatctopch1 => txdatatctopch1, + txpcsrstn => txpcsrstn, + txpmaclk => txpmaclk, + aggtestbusch0 => aggtestbusch0, + aggtestbusch1 => aggtestbusch1, + aggtestbusch2 => aggtestbusch2, + alignstatusbotch2 => alignstatusbotch2, + alignstatusch0 => alignstatusch0, + alignstatusch1 => alignstatusch1, + alignstatusch2 => alignstatusch2, + alignstatussync0botch2 => alignstatussync0botch2, + alignstatussync0ch0 => alignstatussync0ch0, + alignstatussync0ch1 => alignstatussync0ch1, + alignstatussync0ch2 => alignstatussync0ch2, + alignstatussync0topch0 => alignstatussync0topch0, + alignstatussync0topch1 => alignstatussync0topch1, + alignstatustopch0 => alignstatustopch0, + alignstatustopch1 => alignstatustopch1, + cgcomprddallbotch2 => cgcomprddallbotch2, + cgcomprddallch0 => cgcomprddallch0, + cgcomprddallch1 => cgcomprddallch1, + cgcomprddallch2 => cgcomprddallch2, + cgcomprddalltopch0 => cgcomprddalltopch0, + cgcomprddalltopch1 => cgcomprddalltopch1, + cgcompwrallbotch2 => cgcompwrallbotch2, + cgcompwrallch0 => cgcompwrallch0, + cgcompwrallch1 => cgcompwrallch1, + cgcompwrallch2 => cgcompwrallch2, + cgcompwralltopch0 => cgcompwralltopch0, + cgcompwralltopch1 => cgcompwralltopch1, + dedicatedaggscanoutch0tieoff => dedicatedaggscanoutch0tieoff, + dedicatedaggscanoutch1 => dedicatedaggscanoutch1, + dedicatedaggscanoutch2tieoff => dedicatedaggscanoutch2tieoff, + delcondmet0botch2 => delcondmet0botch2, + delcondmet0ch0 => delcondmet0ch0, + delcondmet0ch1 => delcondmet0ch1, + delcondmet0ch2 => delcondmet0ch2, + delcondmet0topch0 => delcondmet0topch0, + delcondmet0topch1 => delcondmet0topch1, + endskwqdbotch2 => endskwqdbotch2, + endskwqdch0 => endskwqdch0, + endskwqdch1 => endskwqdch1, + endskwqdch2 => endskwqdch2, + endskwqdtopch0 => endskwqdtopch0, + endskwqdtopch1 => endskwqdtopch1, + endskwrdptrsbotch2 => endskwrdptrsbotch2, + endskwrdptrsch0 => endskwrdptrsch0, + endskwrdptrsch1 => endskwrdptrsch1, + endskwrdptrsch2 => endskwrdptrsch2, + endskwrdptrstopch0 => endskwrdptrstopch0, + endskwrdptrstopch1 => endskwrdptrstopch1, + fifoovr0botch2 => fifoovr0botch2, + fifoovr0ch0 => fifoovr0ch0, + fifoovr0ch1 => fifoovr0ch1, + fifoovr0ch2 => fifoovr0ch2, + fifoovr0topch0 => fifoovr0topch0, + fifoovr0topch1 => fifoovr0topch1, + fifordoutcomp0botch2 => fifordoutcomp0botch2, + fifordoutcomp0ch0 => fifordoutcomp0ch0, + fifordoutcomp0ch1 => fifordoutcomp0ch1, + fifordoutcomp0ch2 => fifordoutcomp0ch2, + fifordoutcomp0topch0 => fifordoutcomp0topch0, + fifordoutcomp0topch1 => fifordoutcomp0topch1, + fiforstrdqdbotch2 => fiforstrdqdbotch2, + fiforstrdqdch0 => fiforstrdqdch0, + fiforstrdqdch1 => fiforstrdqdch1, + fiforstrdqdch2 => fiforstrdqdch2, + fiforstrdqdtopch0 => fiforstrdqdtopch0, + fiforstrdqdtopch1 => fiforstrdqdtopch1, + insertincomplete0botch2 => insertincomplete0botch2, + insertincomplete0ch0 => insertincomplete0ch0, + insertincomplete0ch1 => insertincomplete0ch1, + insertincomplete0ch2 => insertincomplete0ch2, + insertincomplete0topch0 => insertincomplete0topch0, + insertincomplete0topch1 => insertincomplete0topch1, + latencycomp0botch2 => latencycomp0botch2, + latencycomp0ch0 => latencycomp0ch0, + latencycomp0ch1 => latencycomp0ch1, + latencycomp0ch2 => latencycomp0ch2, + latencycomp0topch0 => latencycomp0topch0, + latencycomp0topch1 => latencycomp0topch1, + rcvdclkout => rcvdclkout, + rcvdclkoutbot => rcvdclkoutbot, + rcvdclkouttop => rcvdclkouttop, + rxctlrsbotch2 => rxctlrsbotch2, + rxctlrsch0 => rxctlrsch0, + rxctlrsch1 => rxctlrsch1, + rxctlrsch2 => rxctlrsch2, + rxctlrstopch0 => rxctlrstopch0, + rxctlrstopch1 => rxctlrstopch1, + rxdatarsbotch2 => rxdatarsbotch2, + rxdatarsch0 => rxdatarsch0, + rxdatarsch1 => rxdatarsch1, + rxdatarsch2 => rxdatarsch2, + rxdatarstopch0 => rxdatarstopch0, + rxdatarstopch1 => rxdatarstopch1, + txctltsbotch2 => txctltsbotch2, + txctltsch0 => txctltsch0, + txctltsch1 => txctltsch1, + txctltsch2 => txctltsch2, + txctltstopch0 => txctltstopch0, + txctltstopch1 => txctltstopch1, + txdatatsbotch2 => txdatatsbotch2, + txdatatsch0 => txdatatsch0, + txdatatsch1 => txdatatsch1, + txdatatsch2 => txdatatsch2, + txdatatstopch0 => txdatatstopch0, + txdatatstopch1 => txdatatstopch1 + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; +library work; +use work.CYCLONEV_HSSI_COMPONENTS.all; + + +entity cyclonev_hssi_8g_rx_pcs is + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "gige"; + tx_rx_parallel_loopback : string := "dis_plpbk"; + pma_dw : string := "eight_bit"; + pcs_bypass : string := "dis_pcs_bypass"; + polarity_inversion : string := "dis_pol_inv"; + wa_pd : string := "wa_pd_10"; + wa_pd_data : bit_vector := B"0"; + wa_boundary_lock_ctrl : string := "bit_slip"; + wa_pld_controlled : string := "dis_pld_ctrl"; + wa_sync_sm_ctrl : string := "gige_sync_sm"; + wa_rknumber_data : bit_vector := B"0"; + wa_renumber_data : bit_vector := B"0"; + wa_rgnumber_data : bit_vector := B"0"; + wa_rosnumber_data : bit_vector := B"0"; + wa_kchar : string := "dis_kchar"; + wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm"; + wa_clk_slip_spacing : string := "min_clk_slip_spacing"; + wa_clk_slip_spacing_data : bit_vector := B"10000"; + bit_reversal : string := "dis_bit_reversal"; + symbol_swap : string := "dis_symbol_swap"; + deskew_pattern : bit_vector := B"1101101000"; + deskew_prog_pattern_only : string := "en_deskew_prog_pat_only"; + rate_match : string := "dis_rm"; + eightb_tenb_decoder : string := "dis_8b10b"; + err_flags_sel : string := "err_flags_wa"; + polinv_8b10b_dec : string := "dis_polinv_8b10b_dec"; + eightbtenb_decoder_output_sel : string := "data_8b10b_decoder"; + invalid_code_flag_only : string := "dis_invalid_code_only"; + auto_error_replacement : string := "dis_err_replace"; + pad_or_edb_error_replace : string := "replace_edb"; + byte_deserializer : string := "dis_bds"; + byte_order : string := "dis_bo"; + re_bo_on_wa : string := "dis_re_bo_on_wa"; + bo_pattern : bit_vector := B"0"; + bo_pad : bit_vector := B"0"; + phase_compensation_fifo : string := "low_latency"; + prbs_ver : string := "dis_prbs"; + cid_pattern : string := "cid_pattern_0"; + cid_pattern_len : bit_vector := B"0"; + bist_ver : string := "dis_bist"; + cdr_ctrl : string := "dis_cdr_ctrl"; + cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask"; + wait_cnt : bit_vector := B"0"; + mask_cnt : bit_vector := X"3ff"; + eidle_entry_sd : string := "dis_eidle_sd"; + eidle_entry_eios : string := "dis_eidle_eios"; + eidle_entry_iei : string := "dis_eidle_iei"; + rx_rcvd_clk : string := "rcvd_clk_rcvd_clk"; + rx_clk1 : string := "rcvd_clk_clk1"; + rx_clk2 : string := "rcvd_clk_clk2"; + rx_rd_clk : string := "pld_rx_clk"; + dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo"; + comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl"; + bypass_pipeline_reg : string := "dis_bypass_pipeline"; + agg_block_sel : string := "same_smrt_pack"; + test_bus_sel : string := "prbs_bist_testbus"; + wa_rvnumber_data : bit_vector := B"0"; + ctrl_plane_bonding_compensation : string := "dis_compensation"; + prbs_ver_clr_flag : string := "dis_prbs_clr_flag"; + hip_mode : string := "dis_hip"; + ctrl_plane_bonding_distribution : string := "not_master_chnl_distr"; + ctrl_plane_bonding_consumption : string := "individual"; + pma_done_count : bit_vector := B"0"; + test_mode : string := "prbs"; + bist_ver_clr_flag : string := "dis_bist_clr_flag"; + wa_disp_err_flag : string := "dis_disp_err_flag"; + runlength_check : string := "en_runlength_sw"; + runlength_val : bit_vector := B"0"; + force_signal_detect : string := "en_force_signal_detect"; + deskew : string := "dis_deskew"; + rx_wr_clk : string := "rx_clk2_div_1_2_4"; + rx_clk_free_running : string := "en_rx_clk_free_run"; + rx_pcs_urst : string := "en_rx_pcs_urst"; + pipe_if_enable : string := "dis_pipe_rx"; + pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl"; + ibm_invalid_code : string := "dis_ibm_invalid_code"; + channel_number : integer := 0; + rx_refclk : string := "dis_refclk_sel"; + clock_gate_dw_rm_wr : string := "dis_dw_rm_wrclk_gating"; + clock_gate_bds_dec_asn : string := "dis_bds_dec_asn_clk_gating"; + fixed_pat_det : string := "dis_fixed_patdet"; + clock_gate_bist : string := "dis_bist_clk_gating"; + clock_gate_cdr_eidle : string := "dis_cdr_eidle_clk_gating"; + clkcmp_pattern_p : bit_vector := B"0"; + clkcmp_pattern_n : bit_vector := B"0"; + clock_gate_prbs : string := "dis_prbs_clk_gating"; + clock_gate_pc_rdclk : string := "dis_pc_rdclk_gating"; + wa_pd_polarity : string := "dis_pd_both_pol"; + clock_gate_dskw_rd : string := "dis_dskw_rdclk_gating"; + clock_gate_byteorder : string := "dis_byteorder_clk_gating"; + clock_gate_dw_pc_wrclk : string := "dis_dw_pc_wrclk_gating"; + sup_mode : string := "user_mode"; + clock_gate_sw_wa : string := "dis_sw_wa_clk_gating"; + clock_gate_dw_dskw_wr : string := "dis_dw_dskw_wrclk_gating"; + clock_gate_sw_pc_wrclk : string := "dis_sw_pc_wrclk_gating"; + clock_gate_sw_rm_rd : string := "dis_sw_rm_rdclk_gating"; + clock_gate_sw_rm_wr : string := "dis_sw_rm_wrclk_gating"; + auto_speed_nego : string := "dis_asn"; + fixed_pat_num : bit_vector := B"1111"; + clock_gate_sw_dskw_wr : string := "dis_sw_dskw_wrclk_gating"; + clock_gate_dw_rm_rd : string := "dis_dw_rm_rdclk_gating"; + clock_gate_dw_wa : string := "dis_dw_wa_clk_gating"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + a1a2size : in std_logic := '0'; + aggtestbus : in std_logic_vector(15 downto 0) := "0000000000000000"; + alignstatus : in std_logic := '0'; + alignstatussync0 : in std_logic := '0'; + alignstatussync0toporbot : in std_logic := '0'; + alignstatustoporbot : in std_logic := '0'; + bitreversalenable : in std_logic := '0'; + bitslip : in std_logic := '0'; + bytereversalenable : in std_logic := '0'; + byteorder : in std_logic := '0'; + cgcomprddall : in std_logic := '0'; + cgcomprddalltoporbot : in std_logic := '0'; + cgcompwrall : in std_logic := '0'; + cgcompwralltoporbot : in std_logic := '0'; + rmfifouserrst : in std_logic := '0'; + configselinchnldown : in std_logic := '0'; + configselinchnlup : in std_logic := '0'; + delcondmet0 : in std_logic := '0'; + delcondmet0toporbot : in std_logic := '0'; + dynclkswitchn : in std_logic := '0'; + eidleinfersel : in std_logic_vector(2 downto 0) := "000"; + endskwqd : in std_logic := '0'; + endskwqdtoporbot : in std_logic := '0'; + endskwrdptrs : in std_logic := '0'; + endskwrdptrstoporbot : in std_logic := '0'; + enablecommadetect : in std_logic := '0'; + fifoovr0 : in std_logic := '0'; + fifoovr0toporbot : in std_logic := '0'; + rmfifordincomp0 : in std_logic := '0'; + fifordincomp0toporbot : in std_logic := '0'; + fiforstrdqd : in std_logic := '0'; + fiforstrdqdtoporbot : in std_logic := '0'; + gen2ngen1 : in std_logic := '0'; + hrdrst : in std_logic := '0'; + insertincomplete0 : in std_logic := '0'; + insertincomplete0toporbot : in std_logic := '0'; + latencycomp0 : in std_logic := '0'; + latencycomp0toporbot : in std_logic := '0'; + phfifouserrst : in std_logic := '0'; + phystatusinternal : in std_logic := '0'; + phystatuspcsgen3 : in std_logic := '0'; + pipeloopbk : in std_logic := '0'; + pldltr : in std_logic := '0'; + pldrxclk : in std_logic := '0'; + polinvrx : in std_logic := '0'; + prbscidenable : in std_logic := '0'; + datain : in std_logic_vector(19 downto 0) := "00000000000000000000"; + rateswitchcontrol : in std_logic := '0'; + rcvdclkagg : in std_logic := '0'; + rcvdclkaggtoporbot : in std_logic := '0'; + rcvdclkpma : in std_logic := '0'; + rdenableinchnldown : in std_logic := '0'; + rdenableinchnlup : in std_logic := '0'; + rmfiforeadenable : in std_logic := '0'; + pcfifordenable : in std_logic := '0'; + refclkdig : in std_logic := '0'; + refclkdig2 : in std_logic := '0'; + resetpcptrsinchnldown : in std_logic := '0'; + resetpcptrsinchnlup : in std_logic := '0'; + resetppmcntrsinchnldown : in std_logic := '0'; + resetppmcntrsinchnlup : in std_logic := '0'; + ctrlfromaggblock : in std_logic := '0'; + rxcontrolrstoporbot : in std_logic := '0'; + datafrinaggblock : in std_logic_vector(7 downto 0) := "00000000"; + rxdatarstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + rxdivsyncinchnldown : in std_logic_vector(1 downto 0) := "00"; + rxdivsyncinchnlup : in std_logic_vector(1 downto 0) := "00"; + rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0) := "00"; + rxweinchnldown : in std_logic_vector(1 downto 0) := "00"; + rxweinchnlup : in std_logic_vector(1 downto 0) := "00"; + rxstatusinternal : in std_logic_vector(2 downto 0) := "000"; + rxpcsrst : in std_logic := '0'; + rxvalidinternal : in std_logic := '0'; + scanmode : in std_logic := '0'; + sigdetfrompma : in std_logic := '0'; + speedchangeinchnldown : in std_logic := '0'; + speedchangeinchnlup : in std_logic := '0'; + syncsmen : in std_logic := '0'; + txctrlplanetestbus : in std_logic_vector(19 downto 0) := "00000000000000000000"; + txdivsync : in std_logic_vector(1 downto 0) := "00"; + txpmaclk : in std_logic := '0'; + txtestbus : in std_logic_vector(19 downto 0) := "00000000000000000000"; + parallelloopback : in std_logic_vector(19 downto 0) := "00000000000000000000"; + wrenableinchnldown : in std_logic := '0'; + wrenableinchnlup : in std_logic := '0'; + pxfifowrdisable : in std_logic := '0'; + rmfifowriteenable : in std_logic := '0'; + a1a2k1k2flag : out std_logic_vector(3 downto 0) := "0000"; + aggrxpcsrst : out std_logic := '0'; + aligndetsync : out std_logic_vector(1 downto 0) := "00"; + alignstatuspld : out std_logic := '0'; + alignstatussync : out std_logic := '0'; + rmfifopartialfull : out std_logic := '0'; + rmfifopartialempty : out std_logic := '0'; + bistdone : out std_logic := '0'; + bisterr : out std_logic := '0'; + byteordflag : out std_logic := '0'; + cgcomprddout : out std_logic_vector(1 downto 0) := "00"; + cgcompwrout : out std_logic_vector(1 downto 0) := "00"; + channeltestbusout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + configseloutchnldown : out std_logic := '0'; + configseloutchnlup : out std_logic := '0'; + decoderctrl : out std_logic := '0'; + decoderdata : out std_logic_vector(7 downto 0) := "00000000"; + decoderdatavalid : out std_logic := '0'; + delcondmetout : out std_logic := '0'; + disablepcfifobyteserdes : out std_logic := '0'; + earlyeios : out std_logic := '0'; + eidleexit : out std_logic := '0'; + rmfifoempty : out std_logic := '0'; + pcfifoempty : out std_logic := '0'; + errctrl : out std_logic_vector(1 downto 0) := "00"; + errdata : out std_logic_vector(15 downto 0) := "0000000000000000"; + fifoovrout : out std_logic := '0'; + fifordoutcomp : out std_logic := '0'; + rmfifofull : out std_logic := '0'; + pcfifofull : out std_logic := '0'; + insertincompleteout : out std_logic := '0'; + latencycompout : out std_logic := '0'; + ltr : out std_logic := '0'; + pcieswitch : out std_logic := '0'; + phystatus : out std_logic := '0'; + pipedata : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + prbsdone : out std_logic := '0'; + prbserrlt : out std_logic := '0'; + rdalign : out std_logic_vector(1 downto 0) := "00"; + rdenableoutchnldown : out std_logic := '0'; + rdenableoutchnlup : out std_logic := '0'; + resetpcptrs : out std_logic := '0'; + resetpcptrsinchnldownpipe : out std_logic := '0'; + resetpcptrsinchnluppipe : out std_logic := '0'; + resetpcptrsoutchnldown : out std_logic := '0'; + resetpcptrsoutchnlup : out std_logic := '0'; + resetppmcntrsoutchnldown : out std_logic := '0'; + resetppmcntrsoutchnlup : out std_logic := '0'; + resetppmcntrspcspma : out std_logic := '0'; + parallelrevloopback : out std_logic_vector(19 downto 0) := "00000000000000000000"; + runlengthviolation : out std_logic := '0'; + rlvlt : out std_logic := '0'; + runningdisparity : out std_logic_vector(1 downto 0) := "00"; + rxblkstart : out std_logic_vector(3 downto 0) := "0000"; + clocktopld : out std_logic := '0'; + rxclkslip : out std_logic := '0'; + rxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + rxdivsyncoutchnldown : out std_logic_vector(1 downto 0) := "00"; + rxdivsyncoutchnlup : out std_logic_vector(1 downto 0) := "00"; + rxpipeclk : out std_logic := '0'; + rxpipesoftreset : out std_logic := '0'; + rxsynchdr : out std_logic_vector(1 downto 0) := "00"; + rxweoutchnldown : out std_logic_vector(1 downto 0) := "00"; + rxweoutchnlup : out std_logic_vector(1 downto 0) := "00"; + dataout : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + eidledetected : out std_logic := '0'; + rxstatus : out std_logic_vector(2 downto 0) := "000"; + rxvalid : out std_logic := '0'; + selftestdone : out std_logic := '0'; + selftesterr : out std_logic := '0'; + signaldetectout : out std_logic := '0'; + speedchange : out std_logic := '0'; + speedchangeinchnldownpipe : out std_logic := '0'; + speedchangeinchnluppipe : out std_logic := '0'; + speedchangeoutchnldown : out std_logic := '0'; + speedchangeoutchnlup : out std_logic := '0'; + syncstatus : out std_logic := '0'; + wordalignboundary : out std_logic_vector(4 downto 0) := "00000"; + wrenableoutchnldown : out std_logic := '0'; + wrenableoutchnlup : out std_logic := '0'; + syncdatain : out std_logic := '0'; + observablebyteserdesclock : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_8g_rx_pcs; + +architecture behavior of cyclonev_hssi_8g_rx_pcs is + +constant cid_pattern_len_int : integer := bin2int(cid_pattern_len); +constant wa_rgnumber_data_int : integer := bin2int(wa_rgnumber_data); +constant wa_renumber_data_int : integer := bin2int(wa_renumber_data); +constant wa_rknumber_data_int : integer := bin2int(wa_rknumber_data); +constant deskew_pattern_int : integer := bin2int(deskew_pattern); +constant wa_rvnumber_data_int : integer := bin2int(wa_rvnumber_data); +constant fixed_pat_num_int : integer := bin2int(fixed_pat_num); +constant bo_pattern_int : integer := bin2int(bo_pattern); +constant wait_cnt_int : integer := bin2int(wait_cnt); +constant clkcmp_pattern_n_int : integer := bin2int(clkcmp_pattern_n); +constant pma_done_count_int : integer := bin2int(pma_done_count); +constant wa_rosnumber_data_int : integer := bin2int(wa_rosnumber_data); +constant bo_pad_int : integer := bin2int(bo_pad); +constant clkcmp_pattern_p_int : integer := bin2int(clkcmp_pattern_p); +constant wa_clk_slip_spacing_data_int : integer := bin2int(wa_clk_slip_spacing_data); +constant runlength_val_int : integer := bin2int(runlength_val); +constant wa_pd_data_int : integer := bin2int(wa_pd_data); +constant mask_cnt_int : integer := bin2int(mask_cnt); + +component cyclonev_hssi_8g_rx_pcs_encrypted + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "gige"; + tx_rx_parallel_loopback : string := "dis_plpbk"; + pma_dw : string := "eight_bit"; + pcs_bypass : string := "dis_pcs_bypass"; + polarity_inversion : string := "dis_pol_inv"; + wa_pd : string := "wa_pd_10"; + wa_pd_data : integer := 0; + wa_boundary_lock_ctrl : string := "bit_slip"; + wa_pld_controlled : string := "dis_pld_ctrl"; + wa_sync_sm_ctrl : string := "gige_sync_sm"; + wa_rknumber_data : integer := 0; + wa_renumber_data : integer := 0; + wa_rgnumber_data : integer := 0; + wa_rosnumber_data : integer := 0; + wa_kchar : string := "dis_kchar"; + wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm"; + wa_clk_slip_spacing : string := "min_clk_slip_spacing"; + wa_clk_slip_spacing_data : integer := 16; + bit_reversal : string := "dis_bit_reversal"; + symbol_swap : string := "dis_symbol_swap"; + deskew_pattern : integer := 872; + deskew_prog_pattern_only : string := "en_deskew_prog_pat_only"; + rate_match : string := "dis_rm"; + eightb_tenb_decoder : string := "dis_8b10b"; + err_flags_sel : string := "err_flags_wa"; + polinv_8b10b_dec : string := "dis_polinv_8b10b_dec"; + eightbtenb_decoder_output_sel : string := "data_8b10b_decoder"; + invalid_code_flag_only : string := "dis_invalid_code_only"; + auto_error_replacement : string := "dis_err_replace"; + pad_or_edb_error_replace : string := "replace_edb"; + byte_deserializer : string := "dis_bds"; + byte_order : string := "dis_bo"; + re_bo_on_wa : string := "dis_re_bo_on_wa"; + bo_pattern : integer := 0; + bo_pad : integer := 0; + phase_compensation_fifo : string := "low_latency"; + prbs_ver : string := "dis_prbs"; + cid_pattern : string := "cid_pattern_0"; + cid_pattern_len : integer := 0; + bist_ver : string := "dis_bist"; + cdr_ctrl : string := "dis_cdr_ctrl"; + cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask"; + wait_cnt : integer := 0; + mask_cnt : integer := 1023; + eidle_entry_sd : string := "dis_eidle_sd"; + eidle_entry_eios : string := "dis_eidle_eios"; + eidle_entry_iei : string := "dis_eidle_iei"; + rx_rcvd_clk : string := "rcvd_clk_rcvd_clk"; + rx_clk1 : string := "rcvd_clk_clk1"; + rx_clk2 : string := "rcvd_clk_clk2"; + rx_rd_clk : string := "pld_rx_clk"; + dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo"; + comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl"; + bypass_pipeline_reg : string := "dis_bypass_pipeline"; + agg_block_sel : string := "same_smrt_pack"; + test_bus_sel : string := "prbs_bist_testbus"; + wa_rvnumber_data : integer := 0; + ctrl_plane_bonding_compensation : string := "dis_compensation"; + prbs_ver_clr_flag : string := "dis_prbs_clr_flag"; + hip_mode : string := "dis_hip"; + ctrl_plane_bonding_distribution : string := "not_master_chnl_distr"; + ctrl_plane_bonding_consumption : string := "individual"; + pma_done_count : integer := 0; + test_mode : string := "prbs"; + bist_ver_clr_flag : string := "dis_bist_clr_flag"; + wa_disp_err_flag : string := "dis_disp_err_flag"; + runlength_check : string := "en_runlength_sw"; + runlength_val : integer := 0; + force_signal_detect : string := "en_force_signal_detect"; + deskew : string := "dis_deskew"; + rx_wr_clk : string := "rx_clk2_div_1_2_4"; + rx_clk_free_running : string := "en_rx_clk_free_run"; + rx_pcs_urst : string := "en_rx_pcs_urst"; + pipe_if_enable : string := "dis_pipe_rx"; + pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl"; + ibm_invalid_code : string := "dis_ibm_invalid_code"; + channel_number : integer := 0; + rx_refclk : string := "dis_refclk_sel"; + clock_gate_dw_rm_wr : string := "dis_dw_rm_wrclk_gating"; + clock_gate_bds_dec_asn : string := "dis_bds_dec_asn_clk_gating"; + fixed_pat_det : string := "dis_fixed_patdet"; + clock_gate_bist : string := "dis_bist_clk_gating"; + clock_gate_cdr_eidle : string := "dis_cdr_eidle_clk_gating"; + clkcmp_pattern_p : integer := 0; + clkcmp_pattern_n : integer := 0; + clock_gate_prbs : string := "dis_prbs_clk_gating"; + clock_gate_pc_rdclk : string := "dis_pc_rdclk_gating"; + wa_pd_polarity : string := "dis_pd_both_pol"; + clock_gate_dskw_rd : string := "dis_dskw_rdclk_gating"; + clock_gate_byteorder : string := "dis_byteorder_clk_gating"; + clock_gate_dw_pc_wrclk : string := "dis_dw_pc_wrclk_gating"; + sup_mode : string := "user_mode"; + clock_gate_sw_wa : string := "dis_sw_wa_clk_gating"; + clock_gate_dw_dskw_wr : string := "dis_dw_dskw_wrclk_gating"; + clock_gate_sw_pc_wrclk : string := "dis_sw_pc_wrclk_gating"; + clock_gate_sw_rm_rd : string := "dis_sw_rm_rdclk_gating"; + clock_gate_sw_rm_wr : string := "dis_sw_rm_wrclk_gating"; + auto_speed_nego : string := "dis_asn"; + fixed_pat_num : integer := 15; + clock_gate_sw_dskw_wr : string := "dis_sw_dskw_wrclk_gating"; + clock_gate_dw_rm_rd : string := "dis_dw_rm_rdclk_gating"; + clock_gate_dw_wa : string := "dis_dw_wa_clk_gating"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + a1a2size : in std_logic := '0'; + aggtestbus : in std_logic_vector(15 downto 0) := "0000000000000000"; + alignstatus : in std_logic := '0'; + alignstatussync0 : in std_logic := '0'; + alignstatussync0toporbot : in std_logic := '0'; + alignstatustoporbot : in std_logic := '0'; + bitreversalenable : in std_logic := '0'; + bitslip : in std_logic := '0'; + bytereversalenable : in std_logic := '0'; + byteorder : in std_logic := '0'; + cgcomprddall : in std_logic := '0'; + cgcomprddalltoporbot : in std_logic := '0'; + cgcompwrall : in std_logic := '0'; + cgcompwralltoporbot : in std_logic := '0'; + rmfifouserrst : in std_logic := '0'; + configselinchnldown : in std_logic := '0'; + configselinchnlup : in std_logic := '0'; + delcondmet0 : in std_logic := '0'; + delcondmet0toporbot : in std_logic := '0'; + dynclkswitchn : in std_logic := '0'; + eidleinfersel : in std_logic_vector(2 downto 0) := "000"; + endskwqd : in std_logic := '0'; + endskwqdtoporbot : in std_logic := '0'; + endskwrdptrs : in std_logic := '0'; + endskwrdptrstoporbot : in std_logic := '0'; + enablecommadetect : in std_logic := '0'; + fifoovr0 : in std_logic := '0'; + fifoovr0toporbot : in std_logic := '0'; + rmfifordincomp0 : in std_logic := '0'; + fifordincomp0toporbot : in std_logic := '0'; + fiforstrdqd : in std_logic := '0'; + fiforstrdqdtoporbot : in std_logic := '0'; + gen2ngen1 : in std_logic := '0'; + hrdrst : in std_logic := '0'; + insertincomplete0 : in std_logic := '0'; + insertincomplete0toporbot : in std_logic := '0'; + latencycomp0 : in std_logic := '0'; + latencycomp0toporbot : in std_logic := '0'; + phfifouserrst : in std_logic := '0'; + phystatusinternal : in std_logic := '0'; + phystatuspcsgen3 : in std_logic := '0'; + pipeloopbk : in std_logic := '0'; + pldltr : in std_logic := '0'; + pldrxclk : in std_logic := '0'; + polinvrx : in std_logic := '0'; + prbscidenable : in std_logic := '0'; + datain : in std_logic_vector(19 downto 0) := "00000000000000000000"; + rateswitchcontrol : in std_logic := '0'; + rcvdclkagg : in std_logic := '0'; + rcvdclkaggtoporbot : in std_logic := '0'; + rcvdclkpma : in std_logic := '0'; + rdenableinchnldown : in std_logic := '0'; + rdenableinchnlup : in std_logic := '0'; + rmfiforeadenable : in std_logic := '0'; + pcfifordenable : in std_logic := '0'; + refclkdig : in std_logic := '0'; + refclkdig2 : in std_logic := '0'; + resetpcptrsinchnldown : in std_logic := '0'; + resetpcptrsinchnlup : in std_logic := '0'; + resetppmcntrsinchnldown : in std_logic := '0'; + resetppmcntrsinchnlup : in std_logic := '0'; + ctrlfromaggblock : in std_logic := '0'; + rxcontrolrstoporbot : in std_logic := '0'; + datafrinaggblock : in std_logic_vector(7 downto 0) := "00000000"; + rxdatarstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + rxdivsyncinchnldown : in std_logic_vector(1 downto 0) := "00"; + rxdivsyncinchnlup : in std_logic_vector(1 downto 0) := "00"; + rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0) := "00"; + rxweinchnldown : in std_logic_vector(1 downto 0) := "00"; + rxweinchnlup : in std_logic_vector(1 downto 0) := "00"; + rxstatusinternal : in std_logic_vector(2 downto 0) := "000"; + rxpcsrst : in std_logic := '0'; + rxvalidinternal : in std_logic := '0'; + scanmode : in std_logic := '0'; + sigdetfrompma : in std_logic := '0'; + speedchangeinchnldown : in std_logic := '0'; + speedchangeinchnlup : in std_logic := '0'; + syncsmen : in std_logic := '0'; + txctrlplanetestbus : in std_logic_vector(19 downto 0) := "00000000000000000000"; + txdivsync : in std_logic_vector(1 downto 0) := "00"; + txpmaclk : in std_logic := '0'; + txtestbus : in std_logic_vector(19 downto 0) := "00000000000000000000"; + parallelloopback : in std_logic_vector(19 downto 0) := "00000000000000000000"; + wrenableinchnldown : in std_logic := '0'; + wrenableinchnlup : in std_logic := '0'; + pxfifowrdisable : in std_logic := '0'; + rmfifowriteenable : in std_logic := '0'; + a1a2k1k2flag : out std_logic_vector(3 downto 0) := "0000"; + aggrxpcsrst : out std_logic := '0'; + aligndetsync : out std_logic_vector(1 downto 0) := "00"; + alignstatuspld : out std_logic := '0'; + alignstatussync : out std_logic := '0'; + rmfifopartialfull : out std_logic := '0'; + rmfifopartialempty : out std_logic := '0'; + bistdone : out std_logic := '0'; + bisterr : out std_logic := '0'; + byteordflag : out std_logic := '0'; + cgcomprddout : out std_logic_vector(1 downto 0) := "00"; + cgcompwrout : out std_logic_vector(1 downto 0) := "00"; + channeltestbusout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + configseloutchnldown : out std_logic := '0'; + configseloutchnlup : out std_logic := '0'; + decoderctrl : out std_logic := '0'; + decoderdata : out std_logic_vector(7 downto 0) := "00000000"; + decoderdatavalid : out std_logic := '0'; + delcondmetout : out std_logic := '0'; + disablepcfifobyteserdes : out std_logic := '0'; + earlyeios : out std_logic := '0'; + eidleexit : out std_logic := '0'; + rmfifoempty : out std_logic := '0'; + pcfifoempty : out std_logic := '0'; + errctrl : out std_logic_vector(1 downto 0) := "00"; + errdata : out std_logic_vector(15 downto 0) := "0000000000000000"; + fifoovrout : out std_logic := '0'; + fifordoutcomp : out std_logic := '0'; + rmfifofull : out std_logic := '0'; + pcfifofull : out std_logic := '0'; + insertincompleteout : out std_logic := '0'; + latencycompout : out std_logic := '0'; + ltr : out std_logic := '0'; + pcieswitch : out std_logic := '0'; + phystatus : out std_logic := '0'; + pipedata : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + prbsdone : out std_logic := '0'; + prbserrlt : out std_logic := '0'; + rdalign : out std_logic_vector(1 downto 0) := "00"; + rdenableoutchnldown : out std_logic := '0'; + rdenableoutchnlup : out std_logic := '0'; + resetpcptrs : out std_logic := '0'; + resetpcptrsinchnldownpipe : out std_logic := '0'; + resetpcptrsinchnluppipe : out std_logic := '0'; + resetpcptrsoutchnldown : out std_logic := '0'; + resetpcptrsoutchnlup : out std_logic := '0'; + resetppmcntrsoutchnldown : out std_logic := '0'; + resetppmcntrsoutchnlup : out std_logic := '0'; + resetppmcntrspcspma : out std_logic := '0'; + parallelrevloopback : out std_logic_vector(19 downto 0) := "00000000000000000000"; + runlengthviolation : out std_logic := '0'; + rlvlt : out std_logic := '0'; + runningdisparity : out std_logic_vector(1 downto 0) := "00"; + rxblkstart : out std_logic_vector(3 downto 0) := "0000"; + clocktopld : out std_logic := '0'; + rxclkslip : out std_logic := '0'; + rxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + rxdivsyncoutchnldown : out std_logic_vector(1 downto 0) := "00"; + rxdivsyncoutchnlup : out std_logic_vector(1 downto 0) := "00"; + rxpipeclk : out std_logic := '0'; + rxpipesoftreset : out std_logic := '0'; + rxsynchdr : out std_logic_vector(1 downto 0) := "00"; + rxweoutchnldown : out std_logic_vector(1 downto 0) := "00"; + rxweoutchnlup : out std_logic_vector(1 downto 0) := "00"; + dataout : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + eidledetected : out std_logic := '0'; + rxstatus : out std_logic_vector(2 downto 0) := "000"; + rxvalid : out std_logic := '0'; + selftestdone : out std_logic := '0'; + selftesterr : out std_logic := '0'; + signaldetectout : out std_logic := '0'; + speedchange : out std_logic := '0'; + speedchangeinchnldownpipe : out std_logic := '0'; + speedchangeinchnluppipe : out std_logic := '0'; + speedchangeoutchnldown : out std_logic := '0'; + speedchangeoutchnlup : out std_logic := '0'; + syncstatus : out std_logic := '0'; + wordalignboundary : out std_logic_vector(4 downto 0) := "00000"; + wrenableoutchnldown : out std_logic := '0'; + wrenableoutchnlup : out std_logic := '0'; + syncdatain : out std_logic := '0'; + observablebyteserdesclock : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_8g_rx_pcs_encrypted + generic map ( + enable_debug_info => enable_debug_info, + prot_mode => prot_mode, + tx_rx_parallel_loopback => tx_rx_parallel_loopback, + pma_dw => pma_dw, + pcs_bypass => pcs_bypass, + polarity_inversion => polarity_inversion, + wa_pd => wa_pd, + wa_pd_data => wa_pd_data_int, + wa_boundary_lock_ctrl => wa_boundary_lock_ctrl, + wa_pld_controlled => wa_pld_controlled, + wa_sync_sm_ctrl => wa_sync_sm_ctrl, + wa_rknumber_data => wa_rknumber_data_int, + wa_renumber_data => wa_renumber_data_int, + wa_rgnumber_data => wa_rgnumber_data_int, + wa_rosnumber_data => wa_rosnumber_data_int, + wa_kchar => wa_kchar, + wa_det_latency_sync_status_beh => wa_det_latency_sync_status_beh, + wa_clk_slip_spacing => wa_clk_slip_spacing, + wa_clk_slip_spacing_data => wa_clk_slip_spacing_data_int, + bit_reversal => bit_reversal, + symbol_swap => symbol_swap, + deskew_pattern => deskew_pattern_int, + deskew_prog_pattern_only => deskew_prog_pattern_only, + rate_match => rate_match, + eightb_tenb_decoder => eightb_tenb_decoder, + err_flags_sel => err_flags_sel, + polinv_8b10b_dec => polinv_8b10b_dec, + eightbtenb_decoder_output_sel => eightbtenb_decoder_output_sel, + invalid_code_flag_only => invalid_code_flag_only, + auto_error_replacement => auto_error_replacement, + pad_or_edb_error_replace => pad_or_edb_error_replace, + byte_deserializer => byte_deserializer, + byte_order => byte_order, + re_bo_on_wa => re_bo_on_wa, + bo_pattern => bo_pattern_int, + bo_pad => bo_pad_int, + phase_compensation_fifo => phase_compensation_fifo, + prbs_ver => prbs_ver, + cid_pattern => cid_pattern, + cid_pattern_len => cid_pattern_len_int, + bist_ver => bist_ver, + cdr_ctrl => cdr_ctrl, + cdr_ctrl_rxvalid_mask => cdr_ctrl_rxvalid_mask, + wait_cnt => wait_cnt_int, + mask_cnt => mask_cnt_int, + eidle_entry_sd => eidle_entry_sd, + eidle_entry_eios => eidle_entry_eios, + eidle_entry_iei => eidle_entry_iei, + rx_rcvd_clk => rx_rcvd_clk, + rx_clk1 => rx_clk1, + rx_clk2 => rx_clk2, + rx_rd_clk => rx_rd_clk, + dw_one_or_two_symbol_bo => dw_one_or_two_symbol_bo, + comp_fifo_rst_pld_ctrl => comp_fifo_rst_pld_ctrl, + bypass_pipeline_reg => bypass_pipeline_reg, + agg_block_sel => agg_block_sel, + test_bus_sel => test_bus_sel, + wa_rvnumber_data => wa_rvnumber_data_int, + ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation, + prbs_ver_clr_flag => prbs_ver_clr_flag, + hip_mode => hip_mode, + ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution, + ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption, + pma_done_count => pma_done_count_int, + test_mode => test_mode, + bist_ver_clr_flag => bist_ver_clr_flag, + wa_disp_err_flag => wa_disp_err_flag, + runlength_check => runlength_check, + runlength_val => runlength_val_int, + force_signal_detect => force_signal_detect, + deskew => deskew, + rx_wr_clk => rx_wr_clk, + rx_clk_free_running => rx_clk_free_running, + rx_pcs_urst => rx_pcs_urst, + pipe_if_enable => pipe_if_enable, + pc_fifo_rst_pld_ctrl => pc_fifo_rst_pld_ctrl, + ibm_invalid_code => ibm_invalid_code, + channel_number => channel_number, + rx_refclk => rx_refclk, + clock_gate_dw_rm_wr => clock_gate_dw_rm_wr, + clock_gate_bds_dec_asn => clock_gate_bds_dec_asn, + fixed_pat_det => fixed_pat_det, + clock_gate_bist => clock_gate_bist, + clock_gate_cdr_eidle => clock_gate_cdr_eidle, + clkcmp_pattern_p => clkcmp_pattern_p_int, + clkcmp_pattern_n => clkcmp_pattern_n_int, + clock_gate_prbs => clock_gate_prbs, + clock_gate_pc_rdclk => clock_gate_pc_rdclk, + wa_pd_polarity => wa_pd_polarity, + clock_gate_dskw_rd => clock_gate_dskw_rd, + clock_gate_byteorder => clock_gate_byteorder, + clock_gate_dw_pc_wrclk => clock_gate_dw_pc_wrclk, + sup_mode => sup_mode, + clock_gate_sw_wa => clock_gate_sw_wa, + clock_gate_dw_dskw_wr => clock_gate_dw_dskw_wr, + clock_gate_sw_pc_wrclk => clock_gate_sw_pc_wrclk, + clock_gate_sw_rm_rd => clock_gate_sw_rm_rd, + clock_gate_sw_rm_wr => clock_gate_sw_rm_wr, + auto_speed_nego => auto_speed_nego, + fixed_pat_num => fixed_pat_num_int, + clock_gate_sw_dskw_wr => clock_gate_sw_dskw_wr, + clock_gate_dw_rm_rd => clock_gate_dw_rm_rd, + clock_gate_dw_wa => clock_gate_dw_wa, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + a1a2size => a1a2size, + aggtestbus => aggtestbus, + alignstatus => alignstatus, + alignstatussync0 => alignstatussync0, + alignstatussync0toporbot => alignstatussync0toporbot, + alignstatustoporbot => alignstatustoporbot, + bitreversalenable => bitreversalenable, + bitslip => bitslip, + bytereversalenable => bytereversalenable, + byteorder => byteorder, + cgcomprddall => cgcomprddall, + cgcomprddalltoporbot => cgcomprddalltoporbot, + cgcompwrall => cgcompwrall, + cgcompwralltoporbot => cgcompwralltoporbot, + rmfifouserrst => rmfifouserrst, + configselinchnldown => configselinchnldown, + configselinchnlup => configselinchnlup, + delcondmet0 => delcondmet0, + delcondmet0toporbot => delcondmet0toporbot, + dynclkswitchn => dynclkswitchn, + eidleinfersel => eidleinfersel, + endskwqd => endskwqd, + endskwqdtoporbot => endskwqdtoporbot, + endskwrdptrs => endskwrdptrs, + endskwrdptrstoporbot => endskwrdptrstoporbot, + enablecommadetect => enablecommadetect, + fifoovr0 => fifoovr0, + fifoovr0toporbot => fifoovr0toporbot, + rmfifordincomp0 => rmfifordincomp0, + fifordincomp0toporbot => fifordincomp0toporbot, + fiforstrdqd => fiforstrdqd, + fiforstrdqdtoporbot => fiforstrdqdtoporbot, + gen2ngen1 => gen2ngen1, + hrdrst => hrdrst, + insertincomplete0 => insertincomplete0, + insertincomplete0toporbot => insertincomplete0toporbot, + latencycomp0 => latencycomp0, + latencycomp0toporbot => latencycomp0toporbot, + phfifouserrst => phfifouserrst, + phystatusinternal => phystatusinternal, + phystatuspcsgen3 => phystatuspcsgen3, + pipeloopbk => pipeloopbk, + pldltr => pldltr, + pldrxclk => pldrxclk, + polinvrx => polinvrx, + prbscidenable => prbscidenable, + datain => datain, + rateswitchcontrol => rateswitchcontrol, + rcvdclkagg => rcvdclkagg, + rcvdclkaggtoporbot => rcvdclkaggtoporbot, + rcvdclkpma => rcvdclkpma, + rdenableinchnldown => rdenableinchnldown, + rdenableinchnlup => rdenableinchnlup, + rmfiforeadenable => rmfiforeadenable, + pcfifordenable => pcfifordenable, + refclkdig => refclkdig, + refclkdig2 => refclkdig2, + resetpcptrsinchnldown => resetpcptrsinchnldown, + resetpcptrsinchnlup => resetpcptrsinchnlup, + resetppmcntrsinchnldown => resetppmcntrsinchnldown, + resetppmcntrsinchnlup => resetppmcntrsinchnlup, + ctrlfromaggblock => ctrlfromaggblock, + rxcontrolrstoporbot => rxcontrolrstoporbot, + datafrinaggblock => datafrinaggblock, + rxdatarstoporbot => rxdatarstoporbot, + rxdivsyncinchnldown => rxdivsyncinchnldown, + rxdivsyncinchnlup => rxdivsyncinchnlup, + rxsynchdrpcsgen3 => rxsynchdrpcsgen3, + rxweinchnldown => rxweinchnldown, + rxweinchnlup => rxweinchnlup, + rxstatusinternal => rxstatusinternal, + rxpcsrst => rxpcsrst, + rxvalidinternal => rxvalidinternal, + scanmode => scanmode, + sigdetfrompma => sigdetfrompma, + speedchangeinchnldown => speedchangeinchnldown, + speedchangeinchnlup => speedchangeinchnlup, + syncsmen => syncsmen, + txctrlplanetestbus => txctrlplanetestbus, + txdivsync => txdivsync, + txpmaclk => txpmaclk, + txtestbus => txtestbus, + parallelloopback => parallelloopback, + wrenableinchnldown => wrenableinchnldown, + wrenableinchnlup => wrenableinchnlup, + pxfifowrdisable => pxfifowrdisable, + rmfifowriteenable => rmfifowriteenable, + a1a2k1k2flag => a1a2k1k2flag, + aggrxpcsrst => aggrxpcsrst, + aligndetsync => aligndetsync, + alignstatuspld => alignstatuspld, + alignstatussync => alignstatussync, + rmfifopartialfull => rmfifopartialfull, + rmfifopartialempty => rmfifopartialempty, + bistdone => bistdone, + bisterr => bisterr, + byteordflag => byteordflag, + cgcomprddout => cgcomprddout, + cgcompwrout => cgcompwrout, + channeltestbusout => channeltestbusout, + configseloutchnldown => configseloutchnldown, + configseloutchnlup => configseloutchnlup, + decoderctrl => decoderctrl, + decoderdata => decoderdata, + decoderdatavalid => decoderdatavalid, + delcondmetout => delcondmetout, + disablepcfifobyteserdes => disablepcfifobyteserdes, + earlyeios => earlyeios, + eidleexit => eidleexit, + rmfifoempty => rmfifoempty, + pcfifoempty => pcfifoempty, + errctrl => errctrl, + errdata => errdata, + fifoovrout => fifoovrout, + fifordoutcomp => fifordoutcomp, + rmfifofull => rmfifofull, + pcfifofull => pcfifofull, + insertincompleteout => insertincompleteout, + latencycompout => latencycompout, + ltr => ltr, + pcieswitch => pcieswitch, + phystatus => phystatus, + pipedata => pipedata, + prbsdone => prbsdone, + prbserrlt => prbserrlt, + rdalign => rdalign, + rdenableoutchnldown => rdenableoutchnldown, + rdenableoutchnlup => rdenableoutchnlup, + resetpcptrs => resetpcptrs, + resetpcptrsinchnldownpipe => resetpcptrsinchnldownpipe, + resetpcptrsinchnluppipe => resetpcptrsinchnluppipe, + resetpcptrsoutchnldown => resetpcptrsoutchnldown, + resetpcptrsoutchnlup => resetpcptrsoutchnlup, + resetppmcntrsoutchnldown => resetppmcntrsoutchnldown, + resetppmcntrsoutchnlup => resetppmcntrsoutchnlup, + resetppmcntrspcspma => resetppmcntrspcspma, + parallelrevloopback => parallelrevloopback, + runlengthviolation => runlengthviolation, + rlvlt => rlvlt, + runningdisparity => runningdisparity, + rxblkstart => rxblkstart, + clocktopld => clocktopld, + rxclkslip => rxclkslip, + rxdatavalid => rxdatavalid, + rxdivsyncoutchnldown => rxdivsyncoutchnldown, + rxdivsyncoutchnlup => rxdivsyncoutchnlup, + rxpipeclk => rxpipeclk, + rxpipesoftreset => rxpipesoftreset, + rxsynchdr => rxsynchdr, + rxweoutchnldown => rxweoutchnldown, + rxweoutchnlup => rxweoutchnlup, + dataout => dataout, + eidledetected => eidledetected, + rxstatus => rxstatus, + rxvalid => rxvalid, + selftestdone => selftestdone, + selftesterr => selftesterr, + signaldetectout => signaldetectout, + speedchange => speedchange, + speedchangeinchnldownpipe => speedchangeinchnldownpipe, + speedchangeinchnluppipe => speedchangeinchnluppipe, + speedchangeoutchnldown => speedchangeoutchnldown, + speedchangeoutchnlup => speedchangeoutchnlup, + syncstatus => syncstatus, + wordalignboundary => wordalignboundary, + wrenableoutchnldown => wrenableoutchnldown, + wrenableoutchnlup => wrenableoutchnlup, + syncdatain => syncdatain, + observablebyteserdesclock => observablebyteserdesclock, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; +library work; +use work.CYCLONEV_HSSI_COMPONENTS.all; + + +entity cyclonev_hssi_8g_tx_pcs is + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "basic"; + hip_mode : string := "dis_hip"; + pma_dw : string := "eight_bit"; + pcs_bypass : string := "dis_pcs_bypass"; + phase_compensation_fifo : string := "low_latency"; + tx_compliance_controlled_disparity : string := "dis_txcompliance"; + force_kchar : string := "dis_force_kchar"; + force_echar : string := "dis_force_echar"; + byte_serializer : string := "dis_bs"; + data_selection_8b10b_encoder_input : string := "normal_data_path"; + eightb_tenb_disp_ctrl : string := "dis_disp_ctrl"; + eightb_tenb_encoder : string := "dis_8b10b"; + prbs_gen : string := "dis_prbs"; + cid_pattern : string := "cid_pattern_0"; + cid_pattern_len : bit_vector := B"0"; + bist_gen : string := "dis_bist"; + bit_reversal : string := "dis_bit_reversal"; + symbol_swap : string := "dis_symbol_swap"; + polarity_inversion : string := "dis_polinv"; + tx_bitslip : string := "dis_tx_bitslip"; + agg_block_sel : string := "same_smrt_pack"; + revloop_back_rm : string := "dis_rev_loopback_rx_rm"; + phfifo_write_clk_sel : string := "pld_tx_clk"; + ctrl_plane_bonding_consumption : string := "individual"; + bypass_pipeline_reg : string := "dis_bypass_pipeline"; + ctrl_plane_bonding_distribution : string := "not_master_chnl_distr"; + test_mode : string := "prbs"; + ctrl_plane_bonding_compensation : string := "dis_compensation"; + refclk_b_clk_sel : string := "tx_pma_clock"; + auto_speed_nego_gen2 : string := "dis_asn_g2"; + txpcs_urst : string := "en_txpcs_urst"; + clock_gate_dw_fifowr : string := "dis_dw_fifowr_clk_gating"; + clock_gate_prbs : string := "dis_prbs_clk_gating"; + txclk_freerun : string := "dis_freerun_tx"; + clock_gate_bs_enc : string := "dis_bs_enc_clk_gating"; + clock_gate_bist : string := "dis_bist_clk_gating"; + clock_gate_fiford : string := "dis_fiford_clk_gating"; + pcfifo_urst : string := "dis_pcfifourst"; + clock_gate_sw_fifowr : string := "dis_sw_fifowr_clk_gating"; + sup_mode : string := "user_mode"; + dynamic_clk_switch : string := "dis_dyn_clk_switch"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + dispcbyte : in std_logic := '0'; + elecidleinfersel : in std_logic_vector(2 downto 0) := "000"; + fifoselectinchnldown : in std_logic_vector(1 downto 0) := "00"; + fifoselectinchnlup : in std_logic_vector(1 downto 0) := "00"; + rateswitch : in std_logic := '0'; + hrdrst : in std_logic := '1'; + pipetxdeemph : in std_logic := '0'; + pipetxmargin : in std_logic_vector(2 downto 0) := "000"; + phfiforeset : in std_logic := '0'; + coreclk : in std_logic := '0'; + polinvrxin : in std_logic := '0'; + invpol : in std_logic := '0'; + powerdn : in std_logic_vector(1 downto 0) := "00"; + prbscidenable : in std_logic := '0'; + rdenableinchnldown : in std_logic := '0'; + rdenableinchnlup : in std_logic := '0'; + phfiforddisable : in std_logic := '0'; + refclkdig : in std_logic := '0'; + resetpcptrs : in std_logic := '0'; + resetpcptrsinchnldown : in std_logic := '0'; + resetpcptrsinchnlup : in std_logic := '0'; + revparallellpbkdata : in std_logic_vector(19 downto 0) := "00000000000000000000"; + enrevparallellpbk : in std_logic := '0'; + pipeenrevparallellpbkin : in std_logic := '0'; + rxpolarityin : in std_logic := '0'; + scanmode : in std_logic := '0'; + txblkstart : in std_logic_vector(3 downto 0) := "0000"; + bitslipboundaryselect : in std_logic_vector(4 downto 0) := "00000"; + xgmctrl : in std_logic := '0'; + xgmctrltoporbottom : in std_logic := '0'; + xgmdatain : in std_logic_vector(7 downto 0) := "00000000"; + xgmdataintoporbottom : in std_logic_vector(7 downto 0) := "00000000"; + txdatavalid : in std_logic_vector(3 downto 0) := "0000"; + txdivsyncinchnldown : in std_logic_vector(1 downto 0) := "00"; + txdivsyncinchnlup : in std_logic_vector(1 downto 0) := "00"; + txsynchdr : in std_logic_vector(1 downto 0) := "00"; + datain : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + detectrxloopin : in std_logic := '0'; + txpmalocalclk : in std_logic := '0'; + pipetxswing : in std_logic := '0'; + txpcsreset : in std_logic := '0'; + wrenableinchnldown : in std_logic := '0'; + wrenableinchnlup : in std_logic := '0'; + phfifowrenable : in std_logic := '0'; + aggtxpcsrst : out std_logic := '0'; + dynclkswitchn : out std_logic := '0'; + phfifounderflow : out std_logic := '0'; + fifoselectoutchnldown : out std_logic_vector(1 downto 0) := "00"; + fifoselectoutchnlup : out std_logic_vector(1 downto 0) := "00"; + phfifooverflow : out std_logic := '0'; + grayelecidleinferselout : out std_logic_vector(2 downto 0) := "000"; + phfifotxdeemph : out std_logic := '0'; + phfifotxmargin : out std_logic_vector(2 downto 0) := "000"; + phfifotxswing : out std_logic := '0'; + polinvrxout : out std_logic := '0'; + pipepowerdownout : out std_logic_vector(1 downto 0) := "00"; + dataout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + rdenableoutchnldown : out std_logic := '0'; + rdenableoutchnlup : out std_logic := '0'; + rdenablesync : out std_logic := '0'; + refclkb : out std_logic := '0'; + refclkbreset : out std_logic := '0'; + pipeenrevparallellpbkout : out std_logic := '0'; + rxpolarityout : out std_logic := '0'; + txblkstartout : out std_logic_vector(3 downto 0) := "0000"; + clkout : out std_logic := '0'; + xgmctrlenable : out std_logic := '0'; + txctrlplanetestbus : out std_logic_vector(19 downto 0) := "00000000000000000000"; + txdataouttogen3 : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + xgmdataout : out std_logic_vector(7 downto 0) := "00000000"; + txdatavalidouttogen3 : out std_logic_vector(3 downto 0) := "0000"; + txdatakouttogen3 : out std_logic_vector(3 downto 0) := "0000"; + txdivsync : out std_logic_vector(1 downto 0) := "00"; + txdivsyncoutchnldown : out std_logic_vector(1 downto 0) := "00"; + txdivsyncoutchnlup : out std_logic_vector(1 downto 0) := "00"; + txpipeclk : out std_logic := '0'; + txpipeelectidle : out std_logic := '0'; + txpipesoftreset : out std_logic := '0'; + txsynchdrout : out std_logic_vector(1 downto 0) := "00"; + txtestbus : out std_logic_vector(19 downto 0) := "00000000000000000000"; + txcomplianceout : out std_logic := '0'; + detectrxloopout : out std_logic := '0'; + txelecidleout : out std_logic := '0'; + parallelfdbkout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + wrenableoutchnldown : out std_logic := '0'; + wrenableoutchnlup : out std_logic := '0'; + syncdatain : out std_logic := '0'; + observablebyteserdesclock : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '1'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_8g_tx_pcs; + +architecture behavior of cyclonev_hssi_8g_tx_pcs is + +constant cid_pattern_len_int : integer := bin2int(cid_pattern_len); + +component cyclonev_hssi_8g_tx_pcs_encrypted + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "basic"; + hip_mode : string := "dis_hip"; + pma_dw : string := "eight_bit"; + pcs_bypass : string := "dis_pcs_bypass"; + phase_compensation_fifo : string := "low_latency"; + tx_compliance_controlled_disparity : string := "dis_txcompliance"; + force_kchar : string := "dis_force_kchar"; + force_echar : string := "dis_force_echar"; + byte_serializer : string := "dis_bs"; + data_selection_8b10b_encoder_input : string := "normal_data_path"; + eightb_tenb_disp_ctrl : string := "dis_disp_ctrl"; + eightb_tenb_encoder : string := "dis_8b10b"; + prbs_gen : string := "dis_prbs"; + cid_pattern : string := "cid_pattern_0"; + cid_pattern_len : integer := 0; + bist_gen : string := "dis_bist"; + bit_reversal : string := "dis_bit_reversal"; + symbol_swap : string := "dis_symbol_swap"; + polarity_inversion : string := "dis_polinv"; + tx_bitslip : string := "dis_tx_bitslip"; + agg_block_sel : string := "same_smrt_pack"; + revloop_back_rm : string := "dis_rev_loopback_rx_rm"; + phfifo_write_clk_sel : string := "pld_tx_clk"; + ctrl_plane_bonding_consumption : string := "individual"; + bypass_pipeline_reg : string := "dis_bypass_pipeline"; + ctrl_plane_bonding_distribution : string := "not_master_chnl_distr"; + test_mode : string := "prbs"; + ctrl_plane_bonding_compensation : string := "dis_compensation"; + refclk_b_clk_sel : string := "tx_pma_clock"; + auto_speed_nego_gen2 : string := "dis_asn_g2"; + txpcs_urst : string := "en_txpcs_urst"; + clock_gate_dw_fifowr : string := "dis_dw_fifowr_clk_gating"; + clock_gate_prbs : string := "dis_prbs_clk_gating"; + txclk_freerun : string := "dis_freerun_tx"; + clock_gate_bs_enc : string := "dis_bs_enc_clk_gating"; + clock_gate_bist : string := "dis_bist_clk_gating"; + clock_gate_fiford : string := "dis_fiford_clk_gating"; + pcfifo_urst : string := "dis_pcfifourst"; + clock_gate_sw_fifowr : string := "dis_sw_fifowr_clk_gating"; + sup_mode : string := "user_mode"; + dynamic_clk_switch : string := "dis_dyn_clk_switch"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + dispcbyte : in std_logic := '0'; + elecidleinfersel : in std_logic_vector(2 downto 0) := "000"; + fifoselectinchnldown : in std_logic_vector(1 downto 0) := "00"; + fifoselectinchnlup : in std_logic_vector(1 downto 0) := "00"; + rateswitch : in std_logic := '0'; + hrdrst : in std_logic := '1'; + pipetxdeemph : in std_logic := '0'; + pipetxmargin : in std_logic_vector(2 downto 0) := "000"; + phfiforeset : in std_logic := '0'; + coreclk : in std_logic := '0'; + polinvrxin : in std_logic := '0'; + invpol : in std_logic := '0'; + powerdn : in std_logic_vector(1 downto 0) := "00"; + prbscidenable : in std_logic := '0'; + rdenableinchnldown : in std_logic := '0'; + rdenableinchnlup : in std_logic := '0'; + phfiforddisable : in std_logic := '0'; + refclkdig : in std_logic := '0'; + resetpcptrs : in std_logic := '0'; + resetpcptrsinchnldown : in std_logic := '0'; + resetpcptrsinchnlup : in std_logic := '0'; + revparallellpbkdata : in std_logic_vector(19 downto 0) := "00000000000000000000"; + enrevparallellpbk : in std_logic := '0'; + pipeenrevparallellpbkin : in std_logic := '0'; + rxpolarityin : in std_logic := '0'; + scanmode : in std_logic := '0'; + txblkstart : in std_logic_vector(3 downto 0) := "0000"; + bitslipboundaryselect : in std_logic_vector(4 downto 0) := "00000"; + xgmctrl : in std_logic := '0'; + xgmctrltoporbottom : in std_logic := '0'; + xgmdatain : in std_logic_vector(7 downto 0) := "00000000"; + xgmdataintoporbottom : in std_logic_vector(7 downto 0) := "00000000"; + txdatavalid : in std_logic_vector(3 downto 0) := "0000"; + txdivsyncinchnldown : in std_logic_vector(1 downto 0) := "00"; + txdivsyncinchnlup : in std_logic_vector(1 downto 0) := "00"; + txsynchdr : in std_logic_vector(1 downto 0) := "00"; + datain : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + detectrxloopin : in std_logic := '0'; + txpmalocalclk : in std_logic := '0'; + pipetxswing : in std_logic := '0'; + txpcsreset : in std_logic := '0'; + wrenableinchnldown : in std_logic := '0'; + wrenableinchnlup : in std_logic := '0'; + phfifowrenable : in std_logic := '0'; + aggtxpcsrst : out std_logic := '0'; + dynclkswitchn : out std_logic := '0'; + phfifounderflow : out std_logic := '0'; + fifoselectoutchnldown : out std_logic_vector(1 downto 0) := "00"; + fifoselectoutchnlup : out std_logic_vector(1 downto 0) := "00"; + phfifooverflow : out std_logic := '0'; + grayelecidleinferselout : out std_logic_vector(2 downto 0) := "000"; + phfifotxdeemph : out std_logic := '0'; + phfifotxmargin : out std_logic_vector(2 downto 0) := "000"; + phfifotxswing : out std_logic := '0'; + polinvrxout : out std_logic := '0'; + pipepowerdownout : out std_logic_vector(1 downto 0) := "00"; + dataout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + rdenableoutchnldown : out std_logic := '0'; + rdenableoutchnlup : out std_logic := '0'; + rdenablesync : out std_logic := '0'; + refclkb : out std_logic := '0'; + refclkbreset : out std_logic := '0'; + pipeenrevparallellpbkout : out std_logic := '0'; + rxpolarityout : out std_logic := '0'; + txblkstartout : out std_logic_vector(3 downto 0) := "0000"; + clkout : out std_logic := '0'; + xgmctrlenable : out std_logic := '0'; + txctrlplanetestbus : out std_logic_vector(19 downto 0) := "00000000000000000000"; + txdataouttogen3 : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + xgmdataout : out std_logic_vector(7 downto 0) := "00000000"; + txdatavalidouttogen3 : out std_logic_vector(3 downto 0) := "0000"; + txdatakouttogen3 : out std_logic_vector(3 downto 0) := "0000"; + txdivsync : out std_logic_vector(1 downto 0) := "00"; + txdivsyncoutchnldown : out std_logic_vector(1 downto 0) := "00"; + txdivsyncoutchnlup : out std_logic_vector(1 downto 0) := "00"; + txpipeclk : out std_logic := '0'; + txpipeelectidle : out std_logic := '0'; + txpipesoftreset : out std_logic := '0'; + txsynchdrout : out std_logic_vector(1 downto 0) := "00"; + txtestbus : out std_logic_vector(19 downto 0) := "00000000000000000000"; + txcomplianceout : out std_logic := '0'; + detectrxloopout : out std_logic := '0'; + txelecidleout : out std_logic := '0'; + parallelfdbkout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + wrenableoutchnldown : out std_logic := '0'; + wrenableoutchnlup : out std_logic := '0'; + syncdatain : out std_logic := '0'; + observablebyteserdesclock : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '1'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_8g_tx_pcs_encrypted + generic map ( + enable_debug_info => enable_debug_info, + prot_mode => prot_mode, + hip_mode => hip_mode, + pma_dw => pma_dw, + pcs_bypass => pcs_bypass, + phase_compensation_fifo => phase_compensation_fifo, + tx_compliance_controlled_disparity => tx_compliance_controlled_disparity, + force_kchar => force_kchar, + force_echar => force_echar, + byte_serializer => byte_serializer, + data_selection_8b10b_encoder_input => data_selection_8b10b_encoder_input, + eightb_tenb_disp_ctrl => eightb_tenb_disp_ctrl, + eightb_tenb_encoder => eightb_tenb_encoder, + prbs_gen => prbs_gen, + cid_pattern => cid_pattern, + cid_pattern_len => cid_pattern_len_int, + bist_gen => bist_gen, + bit_reversal => bit_reversal, + symbol_swap => symbol_swap, + polarity_inversion => polarity_inversion, + tx_bitslip => tx_bitslip, + agg_block_sel => agg_block_sel, + revloop_back_rm => revloop_back_rm, + phfifo_write_clk_sel => phfifo_write_clk_sel, + ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption, + bypass_pipeline_reg => bypass_pipeline_reg, + ctrl_plane_bonding_distribution => ctrl_plane_bonding_distribution, + test_mode => test_mode, + ctrl_plane_bonding_compensation => ctrl_plane_bonding_compensation, + refclk_b_clk_sel => refclk_b_clk_sel, + auto_speed_nego_gen2 => auto_speed_nego_gen2, + txpcs_urst => txpcs_urst, + clock_gate_dw_fifowr => clock_gate_dw_fifowr, + clock_gate_prbs => clock_gate_prbs, + txclk_freerun => txclk_freerun, + clock_gate_bs_enc => clock_gate_bs_enc, + clock_gate_bist => clock_gate_bist, + clock_gate_fiford => clock_gate_fiford, + pcfifo_urst => pcfifo_urst, + clock_gate_sw_fifowr => clock_gate_sw_fifowr, + sup_mode => sup_mode, + dynamic_clk_switch => dynamic_clk_switch, + channel_number => channel_number, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + dispcbyte => dispcbyte, + elecidleinfersel => elecidleinfersel, + fifoselectinchnldown => fifoselectinchnldown, + fifoselectinchnlup => fifoselectinchnlup, + rateswitch => rateswitch, + hrdrst => hrdrst, + pipetxdeemph => pipetxdeemph, + pipetxmargin => pipetxmargin, + phfiforeset => phfiforeset, + coreclk => coreclk, + polinvrxin => polinvrxin, + invpol => invpol, + powerdn => powerdn, + prbscidenable => prbscidenable, + rdenableinchnldown => rdenableinchnldown, + rdenableinchnlup => rdenableinchnlup, + phfiforddisable => phfiforddisable, + refclkdig => refclkdig, + resetpcptrs => resetpcptrs, + resetpcptrsinchnldown => resetpcptrsinchnldown, + resetpcptrsinchnlup => resetpcptrsinchnlup, + revparallellpbkdata => revparallellpbkdata, + enrevparallellpbk => enrevparallellpbk, + pipeenrevparallellpbkin => pipeenrevparallellpbkin, + rxpolarityin => rxpolarityin, + scanmode => scanmode, + txblkstart => txblkstart, + bitslipboundaryselect => bitslipboundaryselect, + xgmctrl => xgmctrl, + xgmctrltoporbottom => xgmctrltoporbottom, + xgmdatain => xgmdatain, + xgmdataintoporbottom => xgmdataintoporbottom, + txdatavalid => txdatavalid, + txdivsyncinchnldown => txdivsyncinchnldown, + txdivsyncinchnlup => txdivsyncinchnlup, + txsynchdr => txsynchdr, + datain => datain, + detectrxloopin => detectrxloopin, + txpmalocalclk => txpmalocalclk, + pipetxswing => pipetxswing, + txpcsreset => txpcsreset, + wrenableinchnldown => wrenableinchnldown, + wrenableinchnlup => wrenableinchnlup, + phfifowrenable => phfifowrenable, + aggtxpcsrst => aggtxpcsrst, + dynclkswitchn => dynclkswitchn, + phfifounderflow => phfifounderflow, + fifoselectoutchnldown => fifoselectoutchnldown, + fifoselectoutchnlup => fifoselectoutchnlup, + phfifooverflow => phfifooverflow, + grayelecidleinferselout => grayelecidleinferselout, + phfifotxdeemph => phfifotxdeemph, + phfifotxmargin => phfifotxmargin, + phfifotxswing => phfifotxswing, + polinvrxout => polinvrxout, + pipepowerdownout => pipepowerdownout, + dataout => dataout, + rdenableoutchnldown => rdenableoutchnldown, + rdenableoutchnlup => rdenableoutchnlup, + rdenablesync => rdenablesync, + refclkb => refclkb, + refclkbreset => refclkbreset, + pipeenrevparallellpbkout => pipeenrevparallellpbkout, + rxpolarityout => rxpolarityout, + txblkstartout => txblkstartout, + clkout => clkout, + xgmctrlenable => xgmctrlenable, + txctrlplanetestbus => txctrlplanetestbus, + txdataouttogen3 => txdataouttogen3, + xgmdataout => xgmdataout, + txdatavalidouttogen3 => txdatavalidouttogen3, + txdatakouttogen3 => txdatakouttogen3, + txdivsync => txdivsync, + txdivsyncoutchnldown => txdivsyncoutchnldown, + txdivsyncoutchnlup => txdivsyncoutchnlup, + txpipeclk => txpipeclk, + txpipeelectidle => txpipeelectidle, + txpipesoftreset => txpipesoftreset, + txsynchdrout => txsynchdrout, + txtestbus => txtestbus, + txcomplianceout => txcomplianceout, + detectrxloopout => detectrxloopout, + txelecidleout => txelecidleout, + parallelfdbkout => parallelfdbkout, + wrenableoutchnldown => wrenableoutchnldown, + wrenableoutchnlup => wrenableoutchnlup, + syncdatain => syncdatain, + observablebyteserdesclock => observablebyteserdesclock, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_common_pcs_pma_interface is + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "disabled_prot_mode"; + force_freqdet : string := "force_freqdet_dis"; + ppmsel : string := "ppmsel_default"; + ppm_cnt_rst : string := "ppm_cnt_rst_dis"; + auto_speed_ena : string := "dis_auto_speed_ena"; + ppm_gen1_2_cnt : string := "cnt_32k"; + ppm_post_eidle_delay : string := "cnt_200_cycles"; + func_mode : string := "disable"; + pma_if_dft_val : string := "dft_0"; + sup_mode : string := "user_mode"; + selectpcs : string := "eight_g_pcs"; + ppm_deassert_early : string := "deassert_early_dis"; + pipe_if_g3pcs : string := "pipe_if_8gpcs"; + pma_if_dft_en : string := "dft_dis"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + aggalignstatus : in std_logic := '0'; + aggalignstatussync0 : in std_logic := '0'; + aggalignstatussync0toporbot : in std_logic := '0'; + aggalignstatustoporbot : in std_logic := '0'; + aggcgcomprddall : in std_logic := '0'; + aggcgcomprddalltoporbot : in std_logic := '0'; + aggcgcompwrall : in std_logic := '0'; + aggcgcompwralltoporbot : in std_logic := '0'; + aggdelcondmet0 : in std_logic := '0'; + aggdelcondmet0toporbot : in std_logic := '0'; + aggendskwqd : in std_logic := '0'; + aggendskwqdtoporbot : in std_logic := '0'; + aggendskwrdptrs : in std_logic := '0'; + aggendskwrdptrstoporbot : in std_logic := '0'; + aggfifoovr0 : in std_logic := '0'; + aggfifoovr0toporbot : in std_logic := '0'; + aggfifordincomp0 : in std_logic := '0'; + aggfifordincomp0toporbot : in std_logic := '0'; + aggfiforstrdqd : in std_logic := '0'; + aggfiforstrdqdtoporbot : in std_logic := '0'; + agginsertincomplete0 : in std_logic := '0'; + agginsertincomplete0toporbot : in std_logic := '0'; + agglatencycomp0 : in std_logic := '0'; + agglatencycomp0toporbot : in std_logic := '0'; + aggrcvdclkagg : in std_logic := '0'; + aggrcvdclkaggtoporbot : in std_logic := '0'; + aggrxcontrolrs : in std_logic := '0'; + aggrxcontrolrstoporbot : in std_logic := '0'; + aggrxdatars : in std_logic_vector(7 downto 0) := "00000000"; + aggrxdatarstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + aggtestsotopldin : in std_logic := '0'; + aggtestbus : in std_logic_vector(15 downto 0) := "0000000000000000"; + aggtxctlts : in std_logic := '0'; + aggtxctltstoporbot : in std_logic := '0'; + aggtxdatats : in std_logic_vector(7 downto 0) := "00000000"; + aggtxdatatstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + hardreset : in std_logic := '0'; + pcs8gearlyeios : in std_logic := '0'; + pcs8geidleexit : in std_logic := '0'; + pcs8gltrpma : in std_logic := '0'; + pcs8gpcieswitch : in std_logic := '0'; + pcs8gpmacurrentcoeff : in std_logic_vector(17 downto 0) := "000000000000000000"; + pcs8gtxelecidle : in std_logic := '0'; + pcs8gtxdetectrx : in std_logic := '0'; + pcsaggaligndetsync : in std_logic_vector(1 downto 0) := "00"; + pcsaggalignstatussync : in std_logic := '0'; + pcsaggcgcomprddout : in std_logic_vector(1 downto 0) := "00"; + pcsaggcgcompwrout : in std_logic_vector(1 downto 0) := "00"; + pcsaggdecctl : in std_logic := '0'; + pcsaggdecdata : in std_logic_vector(7 downto 0) := "00000000"; + pcsaggdecdatavalid : in std_logic := '0'; + pcsaggdelcondmetout : in std_logic := '0'; + pcsaggfifoovrout : in std_logic := '0'; + pcsaggfifordoutcomp : in std_logic := '0'; + pcsagginsertincompleteout : in std_logic := '0'; + pcsagglatencycompout : in std_logic := '0'; + pcsaggrdalign : in std_logic_vector(1 downto 0) := "00"; + pcsaggrdenablesync : in std_logic := '0'; + pcsaggrefclkdig : in std_logic := '0'; + pcsaggrunningdisp : in std_logic_vector(1 downto 0) := "00"; + pcsaggrxpcsrst : in std_logic := '0'; + pcsaggscanmoden : in std_logic := '0'; + pcsaggscanshiftn : in std_logic := '0'; + pcsaggsyncstatus : in std_logic := '0'; + pcsaggtxctltc : in std_logic := '0'; + pcsaggtxdatatc : in std_logic_vector(7 downto 0) := "00000000"; + pcsaggtxpcsrst : in std_logic := '0'; + pcsrefclkdig : in std_logic := '0'; + pcsscanmoden : in std_logic := '0'; + pcsscanshiftn : in std_logic := '0'; + pldnfrzdrv : in std_logic := '0'; + pldpartialreconfig : in std_logic := '0'; + pldtestsitoaggin : in std_logic := '0'; + clklow : in std_logic := '0'; + fref : in std_logic := '0'; + pmahclk : in std_logic := '0'; + pmapcieswdone : in std_logic_vector(1 downto 0) := "00"; + pmarxdetectvalid : in std_logic := '0'; + pmarxfound : in std_logic := '0'; + pmarxpmarstb : in std_logic := '0'; + resetppmcntrs : in std_logic := '0'; + aggaligndetsync : out std_logic_vector(1 downto 0) := "00"; + aggalignstatussync : out std_logic := '0'; + aggcgcomprddout : out std_logic_vector(1 downto 0) := "00"; + aggcgcompwrout : out std_logic_vector(1 downto 0) := "00"; + aggdecctl : out std_logic := '0'; + aggdecdata : out std_logic_vector(7 downto 0) := "00000000"; + aggdecdatavalid : out std_logic := '0'; + aggdelcondmetout : out std_logic := '0'; + aggfifoovrout : out std_logic := '0'; + aggfifordoutcomp : out std_logic := '0'; + agginsertincompleteout : out std_logic := '0'; + agglatencycompout : out std_logic := '0'; + aggrdalign : out std_logic_vector(1 downto 0) := "00"; + aggrdenablesync : out std_logic := '0'; + aggrefclkdig : out std_logic := '0'; + aggrunningdisp : out std_logic_vector(1 downto 0) := "00"; + aggrxpcsrst : out std_logic := '0'; + aggscanmoden : out std_logic := '0'; + aggscanshiftn : out std_logic := '0'; + aggsyncstatus : out std_logic := '0'; + aggtestsotopldout : out std_logic := '0'; + aggtxctltc : out std_logic := '0'; + aggtxdatatc : out std_logic_vector(7 downto 0) := "00000000"; + aggtxpcsrst : out std_logic := '0'; + pcs8ggen2ngen1 : out std_logic := '0'; + pcs8gpmarxfound : out std_logic := '0'; + pcs8gpowerstatetransitiondone : out std_logic := '0'; + pcs8grxdetectvalid : out std_logic := '0'; + pcsaggalignstatus : out std_logic := '0'; + pcsaggalignstatussync0 : out std_logic := '0'; + pcsaggalignstatussync0toporbot : out std_logic := '0'; + pcsaggalignstatustoporbot : out std_logic := '0'; + pcsaggcgcomprddall : out std_logic := '0'; + pcsaggcgcomprddalltoporbot : out std_logic := '0'; + pcsaggcgcompwrall : out std_logic := '0'; + pcsaggcgcompwralltoporbot : out std_logic := '0'; + pcsaggdelcondmet0 : out std_logic := '0'; + pcsaggdelcondmet0toporbot : out std_logic := '0'; + pcsaggendskwqd : out std_logic := '0'; + pcsaggendskwqdtoporbot : out std_logic := '0'; + pcsaggendskwrdptrs : out std_logic := '0'; + pcsaggendskwrdptrstoporbot : out std_logic := '0'; + pcsaggfifoovr0 : out std_logic := '0'; + pcsaggfifoovr0toporbot : out std_logic := '0'; + pcsaggfifordincomp0 : out std_logic := '0'; + pcsaggfifordincomp0toporbot : out std_logic := '0'; + pcsaggfiforstrdqd : out std_logic := '0'; + pcsaggfiforstrdqdtoporbot : out std_logic := '0'; + pcsagginsertincomplete0 : out std_logic := '0'; + pcsagginsertincomplete0toporbot : out std_logic := '0'; + pcsagglatencycomp0 : out std_logic := '0'; + pcsagglatencycomp0toporbot : out std_logic := '0'; + pcsaggrcvdclkagg : out std_logic := '0'; + pcsaggrcvdclkaggtoporbot : out std_logic := '0'; + pcsaggrxcontrolrs : out std_logic := '0'; + pcsaggrxcontrolrstoporbot : out std_logic := '0'; + pcsaggrxdatars : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggtestbus : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcsaggtxctlts : out std_logic := '0'; + pcsaggtxctltstoporbot : out std_logic := '0'; + pcsaggtxdatats : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0) := "00000000"; + pldhclkout : out std_logic := '0'; + pldtestsitoaggout : out std_logic := '0'; + pmaclklowout : out std_logic := '0'; + pmacurrentcoeff : out std_logic_vector(17 downto 0) := "000000000000000000"; + pmaearlyeios : out std_logic := '0'; + pmafrefout : out std_logic := '0'; + pmaiftestbus : out std_logic_vector(9 downto 0) := "0000000000"; + pmaltr : out std_logic := '0'; + pmanfrzdrv : out std_logic := '0'; + pmapartialreconfig : out std_logic := '0'; + pmapcieswitch : out std_logic_vector(1 downto 0) := "00"; + freqlock : out std_logic := '0'; + pmatxelecidle : out std_logic := '0'; + pmatxdetectrx : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_common_pcs_pma_interface; + +architecture behavior of cyclonev_hssi_common_pcs_pma_interface is + +component cyclonev_hssi_common_pcs_pma_interface_encrypted + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "disabled_prot_mode"; + force_freqdet : string := "force_freqdet_dis"; + ppmsel : string := "ppmsel_default"; + ppm_cnt_rst : string := "ppm_cnt_rst_dis"; + auto_speed_ena : string := "dis_auto_speed_ena"; + ppm_gen1_2_cnt : string := "cnt_32k"; + ppm_post_eidle_delay : string := "cnt_200_cycles"; + func_mode : string := "disable"; + pma_if_dft_val : string := "dft_0"; + sup_mode : string := "user_mode"; + selectpcs : string := "eight_g_pcs"; + ppm_deassert_early : string := "deassert_early_dis"; + pipe_if_g3pcs : string := "pipe_if_8gpcs"; + pma_if_dft_en : string := "dft_dis"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + aggalignstatus : in std_logic := '0'; + aggalignstatussync0 : in std_logic := '0'; + aggalignstatussync0toporbot : in std_logic := '0'; + aggalignstatustoporbot : in std_logic := '0'; + aggcgcomprddall : in std_logic := '0'; + aggcgcomprddalltoporbot : in std_logic := '0'; + aggcgcompwrall : in std_logic := '0'; + aggcgcompwralltoporbot : in std_logic := '0'; + aggdelcondmet0 : in std_logic := '0'; + aggdelcondmet0toporbot : in std_logic := '0'; + aggendskwqd : in std_logic := '0'; + aggendskwqdtoporbot : in std_logic := '0'; + aggendskwrdptrs : in std_logic := '0'; + aggendskwrdptrstoporbot : in std_logic := '0'; + aggfifoovr0 : in std_logic := '0'; + aggfifoovr0toporbot : in std_logic := '0'; + aggfifordincomp0 : in std_logic := '0'; + aggfifordincomp0toporbot : in std_logic := '0'; + aggfiforstrdqd : in std_logic := '0'; + aggfiforstrdqdtoporbot : in std_logic := '0'; + agginsertincomplete0 : in std_logic := '0'; + agginsertincomplete0toporbot : in std_logic := '0'; + agglatencycomp0 : in std_logic := '0'; + agglatencycomp0toporbot : in std_logic := '0'; + aggrcvdclkagg : in std_logic := '0'; + aggrcvdclkaggtoporbot : in std_logic := '0'; + aggrxcontrolrs : in std_logic := '0'; + aggrxcontrolrstoporbot : in std_logic := '0'; + aggrxdatars : in std_logic_vector(7 downto 0) := "00000000"; + aggrxdatarstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + aggtestsotopldin : in std_logic := '0'; + aggtestbus : in std_logic_vector(15 downto 0) := "0000000000000000"; + aggtxctlts : in std_logic := '0'; + aggtxctltstoporbot : in std_logic := '0'; + aggtxdatats : in std_logic_vector(7 downto 0) := "00000000"; + aggtxdatatstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + hardreset : in std_logic := '0'; + pcs8gearlyeios : in std_logic := '0'; + pcs8geidleexit : in std_logic := '0'; + pcs8gltrpma : in std_logic := '0'; + pcs8gpcieswitch : in std_logic := '0'; + pcs8gpmacurrentcoeff : in std_logic_vector(17 downto 0) := "000000000000000000"; + pcs8gtxelecidle : in std_logic := '0'; + pcs8gtxdetectrx : in std_logic := '0'; + pcsaggaligndetsync : in std_logic_vector(1 downto 0) := "00"; + pcsaggalignstatussync : in std_logic := '0'; + pcsaggcgcomprddout : in std_logic_vector(1 downto 0) := "00"; + pcsaggcgcompwrout : in std_logic_vector(1 downto 0) := "00"; + pcsaggdecctl : in std_logic := '0'; + pcsaggdecdata : in std_logic_vector(7 downto 0) := "00000000"; + pcsaggdecdatavalid : in std_logic := '0'; + pcsaggdelcondmetout : in std_logic := '0'; + pcsaggfifoovrout : in std_logic := '0'; + pcsaggfifordoutcomp : in std_logic := '0'; + pcsagginsertincompleteout : in std_logic := '0'; + pcsagglatencycompout : in std_logic := '0'; + pcsaggrdalign : in std_logic_vector(1 downto 0) := "00"; + pcsaggrdenablesync : in std_logic := '0'; + pcsaggrefclkdig : in std_logic := '0'; + pcsaggrunningdisp : in std_logic_vector(1 downto 0) := "00"; + pcsaggrxpcsrst : in std_logic := '0'; + pcsaggscanmoden : in std_logic := '0'; + pcsaggscanshiftn : in std_logic := '0'; + pcsaggsyncstatus : in std_logic := '0'; + pcsaggtxctltc : in std_logic := '0'; + pcsaggtxdatatc : in std_logic_vector(7 downto 0) := "00000000"; + pcsaggtxpcsrst : in std_logic := '0'; + pcsrefclkdig : in std_logic := '0'; + pcsscanmoden : in std_logic := '0'; + pcsscanshiftn : in std_logic := '0'; + pldnfrzdrv : in std_logic := '0'; + pldpartialreconfig : in std_logic := '0'; + pldtestsitoaggin : in std_logic := '0'; + clklow : in std_logic := '0'; + fref : in std_logic := '0'; + pmahclk : in std_logic := '0'; + pmapcieswdone : in std_logic_vector(1 downto 0) := "00"; + pmarxdetectvalid : in std_logic := '0'; + pmarxfound : in std_logic := '0'; + pmarxpmarstb : in std_logic := '0'; + resetppmcntrs : in std_logic := '0'; + aggaligndetsync : out std_logic_vector(1 downto 0) := "00"; + aggalignstatussync : out std_logic := '0'; + aggcgcomprddout : out std_logic_vector(1 downto 0) := "00"; + aggcgcompwrout : out std_logic_vector(1 downto 0) := "00"; + aggdecctl : out std_logic := '0'; + aggdecdata : out std_logic_vector(7 downto 0) := "00000000"; + aggdecdatavalid : out std_logic := '0'; + aggdelcondmetout : out std_logic := '0'; + aggfifoovrout : out std_logic := '0'; + aggfifordoutcomp : out std_logic := '0'; + agginsertincompleteout : out std_logic := '0'; + agglatencycompout : out std_logic := '0'; + aggrdalign : out std_logic_vector(1 downto 0) := "00"; + aggrdenablesync : out std_logic := '0'; + aggrefclkdig : out std_logic := '0'; + aggrunningdisp : out std_logic_vector(1 downto 0) := "00"; + aggrxpcsrst : out std_logic := '0'; + aggscanmoden : out std_logic := '0'; + aggscanshiftn : out std_logic := '0'; + aggsyncstatus : out std_logic := '0'; + aggtestsotopldout : out std_logic := '0'; + aggtxctltc : out std_logic := '0'; + aggtxdatatc : out std_logic_vector(7 downto 0) := "00000000"; + aggtxpcsrst : out std_logic := '0'; + pcs8ggen2ngen1 : out std_logic := '0'; + pcs8gpmarxfound : out std_logic := '0'; + pcs8gpowerstatetransitiondone : out std_logic := '0'; + pcs8grxdetectvalid : out std_logic := '0'; + pcsaggalignstatus : out std_logic := '0'; + pcsaggalignstatussync0 : out std_logic := '0'; + pcsaggalignstatussync0toporbot : out std_logic := '0'; + pcsaggalignstatustoporbot : out std_logic := '0'; + pcsaggcgcomprddall : out std_logic := '0'; + pcsaggcgcomprddalltoporbot : out std_logic := '0'; + pcsaggcgcompwrall : out std_logic := '0'; + pcsaggcgcompwralltoporbot : out std_logic := '0'; + pcsaggdelcondmet0 : out std_logic := '0'; + pcsaggdelcondmet0toporbot : out std_logic := '0'; + pcsaggendskwqd : out std_logic := '0'; + pcsaggendskwqdtoporbot : out std_logic := '0'; + pcsaggendskwrdptrs : out std_logic := '0'; + pcsaggendskwrdptrstoporbot : out std_logic := '0'; + pcsaggfifoovr0 : out std_logic := '0'; + pcsaggfifoovr0toporbot : out std_logic := '0'; + pcsaggfifordincomp0 : out std_logic := '0'; + pcsaggfifordincomp0toporbot : out std_logic := '0'; + pcsaggfiforstrdqd : out std_logic := '0'; + pcsaggfiforstrdqdtoporbot : out std_logic := '0'; + pcsagginsertincomplete0 : out std_logic := '0'; + pcsagginsertincomplete0toporbot : out std_logic := '0'; + pcsagglatencycomp0 : out std_logic := '0'; + pcsagglatencycomp0toporbot : out std_logic := '0'; + pcsaggrcvdclkagg : out std_logic := '0'; + pcsaggrcvdclkaggtoporbot : out std_logic := '0'; + pcsaggrxcontrolrs : out std_logic := '0'; + pcsaggrxcontrolrstoporbot : out std_logic := '0'; + pcsaggrxdatars : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggtestbus : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcsaggtxctlts : out std_logic := '0'; + pcsaggtxctltstoporbot : out std_logic := '0'; + pcsaggtxdatats : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0) := "00000000"; + pldhclkout : out std_logic := '0'; + pldtestsitoaggout : out std_logic := '0'; + pmaclklowout : out std_logic := '0'; + pmacurrentcoeff : out std_logic_vector(17 downto 0) := "000000000000000000"; + pmaearlyeios : out std_logic := '0'; + pmafrefout : out std_logic := '0'; + pmaiftestbus : out std_logic_vector(9 downto 0) := "0000000000"; + pmaltr : out std_logic := '0'; + pmanfrzdrv : out std_logic := '0'; + pmapartialreconfig : out std_logic := '0'; + pmapcieswitch : out std_logic_vector(1 downto 0) := "00"; + freqlock : out std_logic := '0'; + pmatxelecidle : out std_logic := '0'; + pmatxdetectrx : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_common_pcs_pma_interface_encrypted + generic map ( + enable_debug_info => enable_debug_info, + prot_mode => prot_mode, + force_freqdet => force_freqdet, + ppmsel => ppmsel, + ppm_cnt_rst => ppm_cnt_rst, + auto_speed_ena => auto_speed_ena, + ppm_gen1_2_cnt => ppm_gen1_2_cnt, + ppm_post_eidle_delay => ppm_post_eidle_delay, + func_mode => func_mode, + pma_if_dft_val => pma_if_dft_val, + sup_mode => sup_mode, + selectpcs => selectpcs, + ppm_deassert_early => ppm_deassert_early, + pipe_if_g3pcs => pipe_if_g3pcs, + pma_if_dft_en => pma_if_dft_en, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + aggalignstatus => aggalignstatus, + aggalignstatussync0 => aggalignstatussync0, + aggalignstatussync0toporbot => aggalignstatussync0toporbot, + aggalignstatustoporbot => aggalignstatustoporbot, + aggcgcomprddall => aggcgcomprddall, + aggcgcomprddalltoporbot => aggcgcomprddalltoporbot, + aggcgcompwrall => aggcgcompwrall, + aggcgcompwralltoporbot => aggcgcompwralltoporbot, + aggdelcondmet0 => aggdelcondmet0, + aggdelcondmet0toporbot => aggdelcondmet0toporbot, + aggendskwqd => aggendskwqd, + aggendskwqdtoporbot => aggendskwqdtoporbot, + aggendskwrdptrs => aggendskwrdptrs, + aggendskwrdptrstoporbot => aggendskwrdptrstoporbot, + aggfifoovr0 => aggfifoovr0, + aggfifoovr0toporbot => aggfifoovr0toporbot, + aggfifordincomp0 => aggfifordincomp0, + aggfifordincomp0toporbot => aggfifordincomp0toporbot, + aggfiforstrdqd => aggfiforstrdqd, + aggfiforstrdqdtoporbot => aggfiforstrdqdtoporbot, + agginsertincomplete0 => agginsertincomplete0, + agginsertincomplete0toporbot => agginsertincomplete0toporbot, + agglatencycomp0 => agglatencycomp0, + agglatencycomp0toporbot => agglatencycomp0toporbot, + aggrcvdclkagg => aggrcvdclkagg, + aggrcvdclkaggtoporbot => aggrcvdclkaggtoporbot, + aggrxcontrolrs => aggrxcontrolrs, + aggrxcontrolrstoporbot => aggrxcontrolrstoporbot, + aggrxdatars => aggrxdatars, + aggrxdatarstoporbot => aggrxdatarstoporbot, + aggtestsotopldin => aggtestsotopldin, + aggtestbus => aggtestbus, + aggtxctlts => aggtxctlts, + aggtxctltstoporbot => aggtxctltstoporbot, + aggtxdatats => aggtxdatats, + aggtxdatatstoporbot => aggtxdatatstoporbot, + hardreset => hardreset, + pcs8gearlyeios => pcs8gearlyeios, + pcs8geidleexit => pcs8geidleexit, + pcs8gltrpma => pcs8gltrpma, + pcs8gpcieswitch => pcs8gpcieswitch, + pcs8gpmacurrentcoeff => pcs8gpmacurrentcoeff, + pcs8gtxelecidle => pcs8gtxelecidle, + pcs8gtxdetectrx => pcs8gtxdetectrx, + pcsaggaligndetsync => pcsaggaligndetsync, + pcsaggalignstatussync => pcsaggalignstatussync, + pcsaggcgcomprddout => pcsaggcgcomprddout, + pcsaggcgcompwrout => pcsaggcgcompwrout, + pcsaggdecctl => pcsaggdecctl, + pcsaggdecdata => pcsaggdecdata, + pcsaggdecdatavalid => pcsaggdecdatavalid, + pcsaggdelcondmetout => pcsaggdelcondmetout, + pcsaggfifoovrout => pcsaggfifoovrout, + pcsaggfifordoutcomp => pcsaggfifordoutcomp, + pcsagginsertincompleteout => pcsagginsertincompleteout, + pcsagglatencycompout => pcsagglatencycompout, + pcsaggrdalign => pcsaggrdalign, + pcsaggrdenablesync => pcsaggrdenablesync, + pcsaggrefclkdig => pcsaggrefclkdig, + pcsaggrunningdisp => pcsaggrunningdisp, + pcsaggrxpcsrst => pcsaggrxpcsrst, + pcsaggscanmoden => pcsaggscanmoden, + pcsaggscanshiftn => pcsaggscanshiftn, + pcsaggsyncstatus => pcsaggsyncstatus, + pcsaggtxctltc => pcsaggtxctltc, + pcsaggtxdatatc => pcsaggtxdatatc, + pcsaggtxpcsrst => pcsaggtxpcsrst, + pcsrefclkdig => pcsrefclkdig, + pcsscanmoden => pcsscanmoden, + pcsscanshiftn => pcsscanshiftn, + pldnfrzdrv => pldnfrzdrv, + pldpartialreconfig => pldpartialreconfig, + pldtestsitoaggin => pldtestsitoaggin, + clklow => clklow, + fref => fref, + pmahclk => pmahclk, + pmapcieswdone => pmapcieswdone, + pmarxdetectvalid => pmarxdetectvalid, + pmarxfound => pmarxfound, + pmarxpmarstb => pmarxpmarstb, + resetppmcntrs => resetppmcntrs, + aggaligndetsync => aggaligndetsync, + aggalignstatussync => aggalignstatussync, + aggcgcomprddout => aggcgcomprddout, + aggcgcompwrout => aggcgcompwrout, + aggdecctl => aggdecctl, + aggdecdata => aggdecdata, + aggdecdatavalid => aggdecdatavalid, + aggdelcondmetout => aggdelcondmetout, + aggfifoovrout => aggfifoovrout, + aggfifordoutcomp => aggfifordoutcomp, + agginsertincompleteout => agginsertincompleteout, + agglatencycompout => agglatencycompout, + aggrdalign => aggrdalign, + aggrdenablesync => aggrdenablesync, + aggrefclkdig => aggrefclkdig, + aggrunningdisp => aggrunningdisp, + aggrxpcsrst => aggrxpcsrst, + aggscanmoden => aggscanmoden, + aggscanshiftn => aggscanshiftn, + aggsyncstatus => aggsyncstatus, + aggtestsotopldout => aggtestsotopldout, + aggtxctltc => aggtxctltc, + aggtxdatatc => aggtxdatatc, + aggtxpcsrst => aggtxpcsrst, + pcs8ggen2ngen1 => pcs8ggen2ngen1, + pcs8gpmarxfound => pcs8gpmarxfound, + pcs8gpowerstatetransitiondone => pcs8gpowerstatetransitiondone, + pcs8grxdetectvalid => pcs8grxdetectvalid, + pcsaggalignstatus => pcsaggalignstatus, + pcsaggalignstatussync0 => pcsaggalignstatussync0, + pcsaggalignstatussync0toporbot => pcsaggalignstatussync0toporbot, + pcsaggalignstatustoporbot => pcsaggalignstatustoporbot, + pcsaggcgcomprddall => pcsaggcgcomprddall, + pcsaggcgcomprddalltoporbot => pcsaggcgcomprddalltoporbot, + pcsaggcgcompwrall => pcsaggcgcompwrall, + pcsaggcgcompwralltoporbot => pcsaggcgcompwralltoporbot, + pcsaggdelcondmet0 => pcsaggdelcondmet0, + pcsaggdelcondmet0toporbot => pcsaggdelcondmet0toporbot, + pcsaggendskwqd => pcsaggendskwqd, + pcsaggendskwqdtoporbot => pcsaggendskwqdtoporbot, + pcsaggendskwrdptrs => pcsaggendskwrdptrs, + pcsaggendskwrdptrstoporbot => pcsaggendskwrdptrstoporbot, + pcsaggfifoovr0 => pcsaggfifoovr0, + pcsaggfifoovr0toporbot => pcsaggfifoovr0toporbot, + pcsaggfifordincomp0 => pcsaggfifordincomp0, + pcsaggfifordincomp0toporbot => pcsaggfifordincomp0toporbot, + pcsaggfiforstrdqd => pcsaggfiforstrdqd, + pcsaggfiforstrdqdtoporbot => pcsaggfiforstrdqdtoporbot, + pcsagginsertincomplete0 => pcsagginsertincomplete0, + pcsagginsertincomplete0toporbot => pcsagginsertincomplete0toporbot, + pcsagglatencycomp0 => pcsagglatencycomp0, + pcsagglatencycomp0toporbot => pcsagglatencycomp0toporbot, + pcsaggrcvdclkagg => pcsaggrcvdclkagg, + pcsaggrcvdclkaggtoporbot => pcsaggrcvdclkaggtoporbot, + pcsaggrxcontrolrs => pcsaggrxcontrolrs, + pcsaggrxcontrolrstoporbot => pcsaggrxcontrolrstoporbot, + pcsaggrxdatars => pcsaggrxdatars, + pcsaggrxdatarstoporbot => pcsaggrxdatarstoporbot, + pcsaggtestbus => pcsaggtestbus, + pcsaggtxctlts => pcsaggtxctlts, + pcsaggtxctltstoporbot => pcsaggtxctltstoporbot, + pcsaggtxdatats => pcsaggtxdatats, + pcsaggtxdatatstoporbot => pcsaggtxdatatstoporbot, + pldhclkout => pldhclkout, + pldtestsitoaggout => pldtestsitoaggout, + pmaclklowout => pmaclklowout, + pmacurrentcoeff => pmacurrentcoeff, + pmaearlyeios => pmaearlyeios, + pmafrefout => pmafrefout, + pmaiftestbus => pmaiftestbus, + pmaltr => pmaltr, + pmanfrzdrv => pmanfrzdrv, + pmapartialreconfig => pmapartialreconfig, + pmapcieswitch => pmapcieswitch, + freqlock => freqlock, + pmatxelecidle => pmatxelecidle, + pmatxdetectrx => pmatxdetectrx, + asynchdatain => asynchdatain, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_common_pld_pcs_interface is + generic ( + enable_debug_info : string := "false"; + hip_enable : string := "hip_disable"; + hrdrstctrl_en_cfgusr : string := "hrst_dis_cfgusr"; + pld_side_reserved_source10 : string := "pld_res10"; + pld_side_data_source : string := "pld"; + pld_side_reserved_source0 : string := "pld_res0"; + pld_side_reserved_source1 : string := "pld_res1"; + pld_side_reserved_source2 : string := "pld_res2"; + pld_side_reserved_source3 : string := "pld_res3"; + pld_side_reserved_source4 : string := "pld_res4"; + pld_side_reserved_source5 : string := "pld_res5"; + pld_side_reserved_source6 : string := "pld_res6"; + pld_side_reserved_source7 : string := "pld_res7"; + pld_side_reserved_source8 : string := "pld_res8"; + pld_side_reserved_source9 : string := "pld_res9"; + hrdrstctrl_en_cfg : string := "hrst_dis_cfg"; + testbus_sel : string := "eight_g_pcs"; + usrmode_sel4rst : string := "usermode"; + pld_side_reserved_source11 : string := "pld_res11"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipcomin : in std_logic_vector(37 downto 0) := "00000000000000000000000000000000000000"; + pcs8gchnltestbusout : in std_logic_vector(19 downto 0) := "00000000000000000000"; + pcs8gphystatus : in std_logic := '0'; + pcs8gpldextraout : in std_logic_vector(2 downto 0) := "000"; + pcs8grxelecidle : in std_logic := '0'; + pcs8grxstatus : in std_logic_vector(2 downto 0) := "000"; + pcs8grxvalid : in std_logic := '0'; + pcs8gtestso : in std_logic_vector(5 downto 0) := "000000"; + pcsaggtestso : in std_logic := '0'; + pcspmaiftestso : in std_logic := '0'; + pcspmaiftestbusout : in std_logic_vector(9 downto 0) := "0000000000"; + pld8gpowerdown : in std_logic_vector(1 downto 0) := "00"; + pld8gprbsciden : in std_logic := '0'; + pld8grefclkdig : in std_logic := '0'; + pld8grefclkdig2 : in std_logic := '0'; + pld8grxpolarity : in std_logic := '0'; + pld8gtxdeemph : in std_logic := '0'; + pld8gtxdetectrxloopback : in std_logic := '0'; + pld8gtxelecidle : in std_logic := '0'; + pld8gtxmargin : in std_logic_vector(2 downto 0) := "000"; + pld8gtxswing : in std_logic := '0'; + pldaggrefclkdig : in std_logic := '0'; + pldeidleinfersel : in std_logic_vector(2 downto 0) := "000"; + pldhclkin : in std_logic := '0'; + pldltr : in std_logic := '0'; + pldpartialreconfigin : in std_logic := '0'; + pldpcspmaifrefclkdig : in std_logic := '0'; + pldrate : in std_logic := '0'; + pldreservedin : in std_logic_vector(11 downto 0) := "000000000000"; + pldscanmoden : in std_logic := '0'; + pldscanshiftn : in std_logic := '0'; + pmaclklow : in std_logic := '0'; + pmafref : in std_logic := '0'; + emsipcomclkout : out std_logic_vector(2 downto 0) := "000"; + emsipcomout : out std_logic_vector(26 downto 0) := "000000000000000000000000000"; + emsipenablediocsrrdydly : out std_logic := '0'; + pcs8geidleinfersel : out std_logic_vector(2 downto 0) := "000"; + pcs8ghardreset : out std_logic := '0'; + pcs8gltr : out std_logic := '0'; + pcs8gpldextrain : out std_logic_vector(3 downto 0) := "0000"; + pcs8gpowerdown : out std_logic_vector(1 downto 0) := "00"; + pcs8gprbsciden : out std_logic := '0'; + pcs8grate : out std_logic := '0'; + pcs8grefclkdig : out std_logic := '0'; + pcs8grefclkdig2 : out std_logic := '0'; + pcs8grxpolarity : out std_logic := '0'; + pcs8gscanmoden : out std_logic := '0'; + pcs8gscanshift : out std_logic := '0'; + pcs8gtestsi : out std_logic_vector(5 downto 0) := "000000"; + pcs8gtxdeemph : out std_logic := '0'; + pcs8gtxdetectrxloopback : out std_logic := '0'; + pcs8gtxelecidle : out std_logic := '0'; + pcs8gtxmargin : out std_logic_vector(2 downto 0) := "000"; + pcs8gtxswing : out std_logic := '0'; + pcsaggrefclkdig : out std_logic := '0'; + pcsaggscanmoden : out std_logic := '0'; + pcsaggscanshift : out std_logic := '0'; + pcsaggtestsi : out std_logic := '0'; + pcspcspmaifrefclkdig : out std_logic := '0'; + pcspcspmaifscanmoden : out std_logic := '0'; + pcspcspmaifscanshiftn : out std_logic := '0'; + pcspmaifhardreset : out std_logic := '0'; + pcspmaiftestsi : out std_logic := '0'; + pld8gphystatus : out std_logic := '0'; + pld8grxelecidle : out std_logic := '0'; + pld8grxstatus : out std_logic_vector(2 downto 0) := "000"; + pld8grxvalid : out std_logic := '0'; + pldclklow : out std_logic := '0'; + pldfref : out std_logic := '0'; + pldnfrzdrv : out std_logic := '0'; + pldpartialreconfigout : out std_logic := '0'; + pldreservedout : out std_logic_vector(10 downto 0) := "00000000000"; + pldtestdata : out std_logic_vector(19 downto 0) := "00000000000000000000"; + rstsel : out std_logic := '0'; + usrrstsel : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_common_pld_pcs_interface; + +architecture behavior of cyclonev_hssi_common_pld_pcs_interface is + +component cyclonev_hssi_common_pld_pcs_interface_encrypted + generic ( + enable_debug_info : string := "false"; + hip_enable : string := "hip_disable"; + hrdrstctrl_en_cfgusr : string := "hrst_dis_cfgusr"; + pld_side_reserved_source10 : string := "pld_res10"; + pld_side_data_source : string := "pld"; + pld_side_reserved_source0 : string := "pld_res0"; + pld_side_reserved_source1 : string := "pld_res1"; + pld_side_reserved_source2 : string := "pld_res2"; + pld_side_reserved_source3 : string := "pld_res3"; + pld_side_reserved_source4 : string := "pld_res4"; + pld_side_reserved_source5 : string := "pld_res5"; + pld_side_reserved_source6 : string := "pld_res6"; + pld_side_reserved_source7 : string := "pld_res7"; + pld_side_reserved_source8 : string := "pld_res8"; + pld_side_reserved_source9 : string := "pld_res9"; + hrdrstctrl_en_cfg : string := "hrst_dis_cfg"; + testbus_sel : string := "eight_g_pcs"; + usrmode_sel4rst : string := "usermode"; + pld_side_reserved_source11 : string := "pld_res11"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipcomin : in std_logic_vector(37 downto 0) := "00000000000000000000000000000000000000"; + pcs8gchnltestbusout : in std_logic_vector(19 downto 0) := "00000000000000000000"; + pcs8gphystatus : in std_logic := '0'; + pcs8gpldextraout : in std_logic_vector(2 downto 0) := "000"; + pcs8grxelecidle : in std_logic := '0'; + pcs8grxstatus : in std_logic_vector(2 downto 0) := "000"; + pcs8grxvalid : in std_logic := '0'; + pcs8gtestso : in std_logic_vector(5 downto 0) := "000000"; + pcsaggtestso : in std_logic := '0'; + pcspmaiftestso : in std_logic := '0'; + pcspmaiftestbusout : in std_logic_vector(9 downto 0) := "0000000000"; + pld8gpowerdown : in std_logic_vector(1 downto 0) := "00"; + pld8gprbsciden : in std_logic := '0'; + pld8grefclkdig : in std_logic := '0'; + pld8grefclkdig2 : in std_logic := '0'; + pld8grxpolarity : in std_logic := '0'; + pld8gtxdeemph : in std_logic := '0'; + pld8gtxdetectrxloopback : in std_logic := '0'; + pld8gtxelecidle : in std_logic := '0'; + pld8gtxmargin : in std_logic_vector(2 downto 0) := "000"; + pld8gtxswing : in std_logic := '0'; + pldaggrefclkdig : in std_logic := '0'; + pldeidleinfersel : in std_logic_vector(2 downto 0) := "000"; + pldhclkin : in std_logic := '0'; + pldltr : in std_logic := '0'; + pldpartialreconfigin : in std_logic := '0'; + pldpcspmaifrefclkdig : in std_logic := '0'; + pldrate : in std_logic := '0'; + pldreservedin : in std_logic_vector(11 downto 0) := "000000000000"; + pldscanmoden : in std_logic := '0'; + pldscanshiftn : in std_logic := '0'; + pmaclklow : in std_logic := '0'; + pmafref : in std_logic := '0'; + emsipcomclkout : out std_logic_vector(2 downto 0) := "000"; + emsipcomout : out std_logic_vector(26 downto 0) := "000000000000000000000000000"; + emsipenablediocsrrdydly : out std_logic := '0'; + pcs8geidleinfersel : out std_logic_vector(2 downto 0) := "000"; + pcs8ghardreset : out std_logic := '0'; + pcs8gltr : out std_logic := '0'; + pcs8gpldextrain : out std_logic_vector(3 downto 0) := "0000"; + pcs8gpowerdown : out std_logic_vector(1 downto 0) := "00"; + pcs8gprbsciden : out std_logic := '0'; + pcs8grate : out std_logic := '0'; + pcs8grefclkdig : out std_logic := '0'; + pcs8grefclkdig2 : out std_logic := '0'; + pcs8grxpolarity : out std_logic := '0'; + pcs8gscanmoden : out std_logic := '0'; + pcs8gscanshift : out std_logic := '0'; + pcs8gtestsi : out std_logic_vector(5 downto 0) := "000000"; + pcs8gtxdeemph : out std_logic := '0'; + pcs8gtxdetectrxloopback : out std_logic := '0'; + pcs8gtxelecidle : out std_logic := '0'; + pcs8gtxmargin : out std_logic_vector(2 downto 0) := "000"; + pcs8gtxswing : out std_logic := '0'; + pcsaggrefclkdig : out std_logic := '0'; + pcsaggscanmoden : out std_logic := '0'; + pcsaggscanshift : out std_logic := '0'; + pcsaggtestsi : out std_logic := '0'; + pcspcspmaifrefclkdig : out std_logic := '0'; + pcspcspmaifscanmoden : out std_logic := '0'; + pcspcspmaifscanshiftn : out std_logic := '0'; + pcspmaifhardreset : out std_logic := '0'; + pcspmaiftestsi : out std_logic := '0'; + pld8gphystatus : out std_logic := '0'; + pld8grxelecidle : out std_logic := '0'; + pld8grxstatus : out std_logic_vector(2 downto 0) := "000"; + pld8grxvalid : out std_logic := '0'; + pldclklow : out std_logic := '0'; + pldfref : out std_logic := '0'; + pldnfrzdrv : out std_logic := '0'; + pldpartialreconfigout : out std_logic := '0'; + pldreservedout : out std_logic_vector(10 downto 0) := "00000000000"; + pldtestdata : out std_logic_vector(19 downto 0) := "00000000000000000000"; + rstsel : out std_logic := '0'; + usrrstsel : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_common_pld_pcs_interface_encrypted + generic map ( + enable_debug_info => enable_debug_info, + hip_enable => hip_enable, + hrdrstctrl_en_cfgusr => hrdrstctrl_en_cfgusr, + pld_side_reserved_source10 => pld_side_reserved_source10, + pld_side_data_source => pld_side_data_source, + pld_side_reserved_source0 => pld_side_reserved_source0, + pld_side_reserved_source1 => pld_side_reserved_source1, + pld_side_reserved_source2 => pld_side_reserved_source2, + pld_side_reserved_source3 => pld_side_reserved_source3, + pld_side_reserved_source4 => pld_side_reserved_source4, + pld_side_reserved_source5 => pld_side_reserved_source5, + pld_side_reserved_source6 => pld_side_reserved_source6, + pld_side_reserved_source7 => pld_side_reserved_source7, + pld_side_reserved_source8 => pld_side_reserved_source8, + pld_side_reserved_source9 => pld_side_reserved_source9, + hrdrstctrl_en_cfg => hrdrstctrl_en_cfg, + testbus_sel => testbus_sel, + usrmode_sel4rst => usrmode_sel4rst, + pld_side_reserved_source11 => pld_side_reserved_source11, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + emsipcomin => emsipcomin, + pcs8gchnltestbusout => pcs8gchnltestbusout, + pcs8gphystatus => pcs8gphystatus, + pcs8gpldextraout => pcs8gpldextraout, + pcs8grxelecidle => pcs8grxelecidle, + pcs8grxstatus => pcs8grxstatus, + pcs8grxvalid => pcs8grxvalid, + pcs8gtestso => pcs8gtestso, + pcsaggtestso => pcsaggtestso, + pcspmaiftestso => pcspmaiftestso, + pcspmaiftestbusout => pcspmaiftestbusout, + pld8gpowerdown => pld8gpowerdown, + pld8gprbsciden => pld8gprbsciden, + pld8grefclkdig => pld8grefclkdig, + pld8grefclkdig2 => pld8grefclkdig2, + pld8grxpolarity => pld8grxpolarity, + pld8gtxdeemph => pld8gtxdeemph, + pld8gtxdetectrxloopback => pld8gtxdetectrxloopback, + pld8gtxelecidle => pld8gtxelecidle, + pld8gtxmargin => pld8gtxmargin, + pld8gtxswing => pld8gtxswing, + pldaggrefclkdig => pldaggrefclkdig, + pldeidleinfersel => pldeidleinfersel, + pldhclkin => pldhclkin, + pldltr => pldltr, + pldpartialreconfigin => pldpartialreconfigin, + pldpcspmaifrefclkdig => pldpcspmaifrefclkdig, + pldrate => pldrate, + pldreservedin => pldreservedin, + pldscanmoden => pldscanmoden, + pldscanshiftn => pldscanshiftn, + pmaclklow => pmaclklow, + pmafref => pmafref, + emsipcomclkout => emsipcomclkout, + emsipcomout => emsipcomout, + emsipenablediocsrrdydly => emsipenablediocsrrdydly, + pcs8geidleinfersel => pcs8geidleinfersel, + pcs8ghardreset => pcs8ghardreset, + pcs8gltr => pcs8gltr, + pcs8gpldextrain => pcs8gpldextrain, + pcs8gpowerdown => pcs8gpowerdown, + pcs8gprbsciden => pcs8gprbsciden, + pcs8grate => pcs8grate, + pcs8grefclkdig => pcs8grefclkdig, + pcs8grefclkdig2 => pcs8grefclkdig2, + pcs8grxpolarity => pcs8grxpolarity, + pcs8gscanmoden => pcs8gscanmoden, + pcs8gscanshift => pcs8gscanshift, + pcs8gtestsi => pcs8gtestsi, + pcs8gtxdeemph => pcs8gtxdeemph, + pcs8gtxdetectrxloopback => pcs8gtxdetectrxloopback, + pcs8gtxelecidle => pcs8gtxelecidle, + pcs8gtxmargin => pcs8gtxmargin, + pcs8gtxswing => pcs8gtxswing, + pcsaggrefclkdig => pcsaggrefclkdig, + pcsaggscanmoden => pcsaggscanmoden, + pcsaggscanshift => pcsaggscanshift, + pcsaggtestsi => pcsaggtestsi, + pcspcspmaifrefclkdig => pcspcspmaifrefclkdig, + pcspcspmaifscanmoden => pcspcspmaifscanmoden, + pcspcspmaifscanshiftn => pcspcspmaifscanshiftn, + pcspmaifhardreset => pcspmaifhardreset, + pcspmaiftestsi => pcspmaiftestsi, + pld8gphystatus => pld8gphystatus, + pld8grxelecidle => pld8grxelecidle, + pld8grxstatus => pld8grxstatus, + pld8grxvalid => pld8grxvalid, + pldclklow => pldclklow, + pldfref => pldfref, + pldnfrzdrv => pldnfrzdrv, + pldpartialreconfigout => pldpartialreconfigout, + pldreservedout => pldreservedout, + pldtestdata => pldtestdata, + rstsel => rstsel, + usrrstsel => usrrstsel, + asynchdatain => asynchdatain, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmread => avmmread, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; +library work; +use work.CYCLONEV_HSSI_COMPONENTS.all; + + +entity cyclonev_hssi_pipe_gen1_2 is + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "pipe_g1"; + hip_mode : string := "dis_hip"; + tx_pipe_enable : string := "dis_pipe_tx"; + rx_pipe_enable : string := "dis_pipe_rx"; + pipe_byte_de_serializer_en : string := "dont_care_bds"; + txswing : string := "dis_txswing"; + rxdetect_bypass : string := "dis_rxdetect_bypass"; + error_replace_pad : string := "replace_edb"; + ind_error_reporting : string := "dis_ind_error_reporting"; + phystatus_rst_toggle : string := "dis_phystatus_rst_toggle"; + elecidle_delay : string := "elec_idle_delay"; + elec_idle_delay_val : bit_vector := B"0"; + phy_status_delay : string := "phystatus_delay"; + phystatus_delay_val : bit_vector := B"0"; + rvod_sel_d_val : bit_vector := B"0"; + rpre_emph_b_val : bit_vector := B"0"; + rvod_sel_c_val : bit_vector := B"0"; + rpre_emph_c_val : bit_vector := B"0"; + rpre_emph_settings : bit_vector := B"0"; + rvod_sel_a_val : bit_vector := B"0"; + rpre_emph_d_val : bit_vector := B"0"; + rvod_sel_settings : bit_vector := B"0"; + rvod_sel_b_val : bit_vector := B"0"; + rpre_emph_e_val : bit_vector := B"0"; + sup_mode : string := "user_mode"; + rvod_sel_e_val : bit_vector := B"0"; + rpre_emph_a_val : bit_vector := B"0"; + ctrl_plane_bonding_consumption : string := "individual"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + pcieswitch : in std_logic := '0'; + piperxclk : in std_logic := '0'; + pipetxclk : in std_logic := '0'; + polinvrx : in std_logic := '0'; + powerstatetransitiondone : in std_logic := '0'; + powerstatetransitiondoneena : in std_logic := '0'; + powerdown : in std_logic_vector(1 downto 0) := "00"; + refclkb : in std_logic := '0'; + refclkbreset : in std_logic := '0'; + revloopbkpcsgen3 : in std_logic := '0'; + revloopback : in std_logic := '0'; + rxdetectvalid : in std_logic := '0'; + rxfound : in std_logic := '0'; + rxpipereset : in std_logic := '0'; + rxd : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + rxelectricalidle : in std_logic := '0'; + rxpolarity : in std_logic := '0'; + sigdetni : in std_logic := '0'; + speedchange : in std_logic := '0'; + speedchangechnldown : in std_logic := '0'; + speedchangechnlup : in std_logic := '0'; + txelecidlecomp : in std_logic := '0'; + txpipereset : in std_logic := '0'; + txdch : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + txdeemph : in std_logic := '0'; + txdetectrxloopback : in std_logic := '0'; + txelecidlein : in std_logic := '0'; + txmargin : in std_logic_vector(2 downto 0) := "000"; + txswingport : in std_logic := '0'; + currentcoeff : out std_logic_vector(17 downto 0) := "000000000000000000"; + phystatus : out std_logic := '0'; + polinvrxint : out std_logic := '0'; + revloopbk : out std_logic := '0'; + rxdch : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + rxelecidle : out std_logic := '0'; + rxelectricalidleout : out std_logic := '0'; + rxstatus : out std_logic_vector(2 downto 0) := "000"; + rxvalid : out std_logic := '0'; + speedchangeout : out std_logic := '0'; + txelecidleout : out std_logic := '0'; + txd : out std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + txdetectrx : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_pipe_gen1_2; + +architecture behavior of cyclonev_hssi_pipe_gen1_2 is + +constant elec_idle_delay_val_int : integer := bin2int(elec_idle_delay_val); +constant phystatus_delay_val_int : integer := bin2int(phystatus_delay_val); +constant rvod_sel_d_val_int : integer := bin2int(rvod_sel_d_val); +constant rpre_emph_b_val_int : integer := bin2int(rpre_emph_b_val); +constant rvod_sel_c_val_int : integer := bin2int(rvod_sel_c_val); +constant rpre_emph_c_val_int : integer := bin2int(rpre_emph_c_val); +constant rpre_emph_settings_int : integer := bin2int(rpre_emph_settings); +constant rvod_sel_a_val_int : integer := bin2int(rvod_sel_a_val); +constant rpre_emph_d_val_int : integer := bin2int(rpre_emph_d_val); +constant rvod_sel_settings_int : integer := bin2int(rvod_sel_settings); +constant rvod_sel_b_val_int : integer := bin2int(rvod_sel_b_val); +constant rpre_emph_e_val_int : integer := bin2int(rpre_emph_e_val); +constant rvod_sel_e_val_int : integer := bin2int(rvod_sel_e_val); +constant rpre_emph_a_val_int : integer := bin2int(rpre_emph_a_val); + +component cyclonev_hssi_pipe_gen1_2_encrypted + generic ( + enable_debug_info : string := "false"; + prot_mode : string := "pipe_g1"; + hip_mode : string := "dis_hip"; + tx_pipe_enable : string := "dis_pipe_tx"; + rx_pipe_enable : string := "dis_pipe_rx"; + pipe_byte_de_serializer_en : string := "dont_care_bds"; + txswing : string := "dis_txswing"; + rxdetect_bypass : string := "dis_rxdetect_bypass"; + error_replace_pad : string := "replace_edb"; + ind_error_reporting : string := "dis_ind_error_reporting"; + phystatus_rst_toggle : string := "dis_phystatus_rst_toggle"; + elecidle_delay : string := "elec_idle_delay"; + elec_idle_delay_val : integer := 0; + phy_status_delay : string := "phystatus_delay"; + phystatus_delay_val : integer := 0; + rvod_sel_d_val : integer := 0; + rpre_emph_b_val : integer := 0; + rvod_sel_c_val : integer := 0; + rpre_emph_c_val : integer := 0; + rpre_emph_settings : integer := 0; + rvod_sel_a_val : integer := 0; + rpre_emph_d_val : integer := 0; + rvod_sel_settings : integer := 0; + rvod_sel_b_val : integer := 0; + rpre_emph_e_val : integer := 0; + sup_mode : string := "user_mode"; + rvod_sel_e_val : integer := 0; + rpre_emph_a_val : integer := 0; + ctrl_plane_bonding_consumption : string := "individual"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + pcieswitch : in std_logic := '0'; + piperxclk : in std_logic := '0'; + pipetxclk : in std_logic := '0'; + polinvrx : in std_logic := '0'; + powerstatetransitiondone : in std_logic := '0'; + powerstatetransitiondoneena : in std_logic := '0'; + powerdown : in std_logic_vector(1 downto 0) := "00"; + refclkb : in std_logic := '0'; + refclkbreset : in std_logic := '0'; + revloopbkpcsgen3 : in std_logic := '0'; + revloopback : in std_logic := '0'; + rxdetectvalid : in std_logic := '0'; + rxfound : in std_logic := '0'; + rxpipereset : in std_logic := '0'; + rxd : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + rxelectricalidle : in std_logic := '0'; + rxpolarity : in std_logic := '0'; + sigdetni : in std_logic := '0'; + speedchange : in std_logic := '0'; + speedchangechnldown : in std_logic := '0'; + speedchangechnlup : in std_logic := '0'; + txelecidlecomp : in std_logic := '0'; + txpipereset : in std_logic := '0'; + txdch : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + txdeemph : in std_logic := '0'; + txdetectrxloopback : in std_logic := '0'; + txelecidlein : in std_logic := '0'; + txmargin : in std_logic_vector(2 downto 0) := "000"; + txswingport : in std_logic := '0'; + currentcoeff : out std_logic_vector(17 downto 0) := "000000000000000000"; + phystatus : out std_logic := '0'; + polinvrxint : out std_logic := '0'; + revloopbk : out std_logic := '0'; + rxdch : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + rxelecidle : out std_logic := '0'; + rxelectricalidleout : out std_logic := '0'; + rxstatus : out std_logic_vector(2 downto 0) := "000"; + rxvalid : out std_logic := '0'; + speedchangeout : out std_logic := '0'; + txelecidleout : out std_logic := '0'; + txd : out std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + txdetectrx : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pipe_gen1_2_encrypted + generic map ( + enable_debug_info => enable_debug_info, + prot_mode => prot_mode, + hip_mode => hip_mode, + tx_pipe_enable => tx_pipe_enable, + rx_pipe_enable => rx_pipe_enable, + pipe_byte_de_serializer_en => pipe_byte_de_serializer_en, + txswing => txswing, + rxdetect_bypass => rxdetect_bypass, + error_replace_pad => error_replace_pad, + ind_error_reporting => ind_error_reporting, + phystatus_rst_toggle => phystatus_rst_toggle, + elecidle_delay => elecidle_delay, + elec_idle_delay_val => elec_idle_delay_val_int, + phy_status_delay => phy_status_delay, + phystatus_delay_val => phystatus_delay_val_int, + rvod_sel_d_val => rvod_sel_d_val_int, + rpre_emph_b_val => rpre_emph_b_val_int, + rvod_sel_c_val => rvod_sel_c_val_int, + rpre_emph_c_val => rpre_emph_c_val_int, + rpre_emph_settings => rpre_emph_settings_int, + rvod_sel_a_val => rvod_sel_a_val_int, + rpre_emph_d_val => rpre_emph_d_val_int, + rvod_sel_settings => rvod_sel_settings_int, + rvod_sel_b_val => rvod_sel_b_val_int, + rpre_emph_e_val => rpre_emph_e_val_int, + sup_mode => sup_mode, + rvod_sel_e_val => rvod_sel_e_val_int, + rpre_emph_a_val => rpre_emph_a_val_int, + ctrl_plane_bonding_consumption => ctrl_plane_bonding_consumption, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + pcieswitch => pcieswitch, + piperxclk => piperxclk, + pipetxclk => pipetxclk, + polinvrx => polinvrx, + powerstatetransitiondone => powerstatetransitiondone, + powerstatetransitiondoneena => powerstatetransitiondoneena, + powerdown => powerdown, + refclkb => refclkb, + refclkbreset => refclkbreset, + revloopbkpcsgen3 => revloopbkpcsgen3, + revloopback => revloopback, + rxdetectvalid => rxdetectvalid, + rxfound => rxfound, + rxpipereset => rxpipereset, + rxd => rxd, + rxelectricalidle => rxelectricalidle, + rxpolarity => rxpolarity, + sigdetni => sigdetni, + speedchange => speedchange, + speedchangechnldown => speedchangechnldown, + speedchangechnlup => speedchangechnlup, + txelecidlecomp => txelecidlecomp, + txpipereset => txpipereset, + txdch => txdch, + txdeemph => txdeemph, + txdetectrxloopback => txdetectrxloopback, + txelecidlein => txelecidlein, + txmargin => txmargin, + txswingport => txswingport, + currentcoeff => currentcoeff, + phystatus => phystatus, + polinvrxint => polinvrxint, + revloopbk => revloopbk, + rxdch => rxdch, + rxelecidle => rxelecidle, + rxelectricalidleout => rxelectricalidleout, + rxstatus => rxstatus, + rxvalid => rxvalid, + speedchangeout => speedchangeout, + txelecidleout => txelecidleout, + txd => txd, + txdetectrx => txdetectrx, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_aux is + generic ( + enable_debug_info : string := "false"; + cal_clk_sel : string := "pm_aux_iqclk_cal_clk_sel_cal_clk"; + cal_result_status : string := "pm_aux_result_status_tx"; + continuous_calibration : string := "false"; + pm_aux_cal_clk_test_sel : string := "false"; + rx_cal_override_value : integer := 0; + rx_cal_override_value_enable : string := "false"; + rx_imp : string := "cal_imp_46_ohm"; + test_counter_enable : string := "false"; + tx_cal_override_value : integer := 0; + tx_cal_override_value_enable : string := "false"; + tx_imp : string := "cal_imp_48_ohm"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + atb0out : inout std_logic := '0'; + atb1out : inout std_logic := '0'; + calclk : in std_logic := '0'; + calpdb : in std_logic := '0'; + refiqclk : in std_logic_vector(5 downto 0) := "000000"; + testcntl : in std_logic := '0'; + nonusertoio : out std_logic := '0'; + zrxtx50 : out std_logic_vector(4 downto 0) := "00000" + ); +end cyclonev_hssi_pma_aux; + +architecture behavior of cyclonev_hssi_pma_aux is + +component cyclonev_hssi_pma_aux_encrypted + generic ( + enable_debug_info : string := "false"; + cal_clk_sel : string := "pm_aux_iqclk_cal_clk_sel_cal_clk"; + cal_result_status : string := "pm_aux_result_status_tx"; + continuous_calibration : string := "false"; + pm_aux_cal_clk_test_sel : string := "false"; + rx_cal_override_value : integer := 0; + rx_cal_override_value_enable : string := "false"; + rx_imp : string := "cal_imp_46_ohm"; + test_counter_enable : string := "false"; + tx_cal_override_value : integer := 0; + tx_cal_override_value_enable : string := "false"; + tx_imp : string := "cal_imp_48_ohm"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + atb0out : inout std_logic := '0'; + atb1out : inout std_logic := '0'; + calclk : in std_logic := '0'; + calpdb : in std_logic := '0'; + refiqclk : in std_logic_vector(5 downto 0) := "000000"; + testcntl : in std_logic := '0'; + nonusertoio : out std_logic := '0'; + zrxtx50 : out std_logic_vector(4 downto 0) := "00000" + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_aux_encrypted + generic map ( + enable_debug_info => enable_debug_info, + cal_clk_sel => cal_clk_sel, + cal_result_status => cal_result_status, + continuous_calibration => continuous_calibration, + pm_aux_cal_clk_test_sel => pm_aux_cal_clk_test_sel, + rx_cal_override_value => rx_cal_override_value, + rx_cal_override_value_enable => rx_cal_override_value_enable, + rx_imp => rx_imp, + test_counter_enable => test_counter_enable, + tx_cal_override_value => tx_cal_override_value, + tx_cal_override_value_enable => tx_cal_override_value_enable, + tx_imp => tx_imp, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + atb0out => atb0out, + atb1out => atb1out, + calclk => calclk, + calpdb => calpdb, + refiqclk => refiqclk, + testcntl => testcntl, + nonusertoio => nonusertoio, + zrxtx50 => zrxtx50 + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_int is + generic ( + enable_debug_info : string := "false"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + cvp_mode : string := "cvp_mode_off"; + early_eios_sel : string := "pcs_early_eios"; + ffclk_enable : string := "ffclk_off"; + iqtxrxclk_a_sel : string := "tristage_outa"; + iqtxrxclk_b_sel : string := "tristage_outb"; + ltr_sel : string := "pcs_ltr"; + pcie_switch_sel : string := "pcs_pcie_switch_sw"; + pclk_0_clk_sel : string := "pclk_0_power_down"; + pclk_1_clk_sel : string := "pclk_1_power_down"; + tx_elec_idle_sel : string := "pcs_tx_elec_idle"; + txdetectrx_sel : string := "pcs_txdetectrx" + ); + port ( + bslip : in std_logic := '0'; + ccrurstb : in std_logic := '0'; + cearlyeios : in std_logic := '0'; + clkdivrxi : in std_logic := '0'; + clkdivtxi : in std_logic := '0'; + clklowi : in std_logic := '0'; + cltd : in std_logic := '0'; + cltr : in std_logic := '0'; + cpcieswitch : in std_logic := '0'; + crslpbk : in std_logic := '0'; + ctxdetectrx : in std_logic := '0'; + ctxelecidle : in std_logic := '0'; + ctxpmarstb : in std_logic := '0'; + earlyeios : in std_logic := '0'; + frefi : in std_logic := '0'; + hclkpcsi : in std_logic := '0'; + icoeff : in std_logic_vector(11 downto 0) := "000000000000"; + ltr : in std_logic := '0'; + pcieswdonei : in std_logic := '0'; + pcieswitch : in std_logic := '0'; + pcsrxclkout : in std_logic := '0'; + pcstxclkout : in std_logic := '0'; + pfdmodelocki : in std_logic := '0'; + pldclk : in std_logic := '0'; + ppmlock : in std_logic := '0'; + rxdetclk : in std_logic := '0'; + rxdetectvalidi : in std_logic := '0'; + rxfoundi : in std_logic := '0'; + rxplllocki : in std_logic := '0'; + rxpmarstb : in std_logic := '0'; + sdi : in std_logic := '0'; + testbusi : in std_logic_vector(7 downto 0) := "00000000"; + testsel : in std_logic_vector(3 downto 0) := "0000"; + txdetectrx : in std_logic := '0'; + txelecidle : in std_logic := '0'; + bslipo : out std_logic := '0'; + clklow : out std_logic := '0'; + cpcieswdone : out std_logic := '0'; + cpclk : out std_logic_vector(1 downto 0) := "00"; + cpfdmodelock : out std_logic := '0'; + crurstbo : out std_logic := '0'; + crxdetectvalid : out std_logic := '0'; + crxfound : out std_logic := '0'; + crxplllock : out std_logic := '0'; + csd : out std_logic := '0'; + earlyeioso : out std_logic := '0'; + fref : out std_logic := '0'; + hclkpcs : out std_logic := '0'; + icoeffo : out std_logic_vector(11 downto 0) := "000000000000"; + iqtxrxclka : out std_logic := '0'; + iqtxrxclkb : out std_logic := '0'; + ltdo : out std_logic := '0'; + ltro : out std_logic := '0'; + pcieswdone : out std_logic := '0'; + pcieswitcho : out std_logic := '0'; + pfdmodelock : out std_logic := '0'; + pldclko : out std_logic := '0'; + ppmlocko : out std_logic := '0'; + rxdetclko : out std_logic := '0'; + rxdetectvalid : out std_logic := '0'; + rxfound : out std_logic := '0'; + rxplllock : out std_logic := '0'; + rxpmarstbo : out std_logic := '0'; + sd : out std_logic := '0'; + slpbko : out std_logic := '0'; + testbus : out std_logic_vector(7 downto 0) := "00000000"; + testselo : out std_logic_vector(3 downto 0) := "0000"; + txdetectrxo : out std_logic := '0'; + txelecidleo : out std_logic := '0'; + txpmarstbo : out std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_pma_int; + +architecture behavior of cyclonev_hssi_pma_int is + +component cyclonev_hssi_pma_int_encrypted + generic ( + enable_debug_info : string := "false"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + cvp_mode : string := "cvp_mode_off"; + early_eios_sel : string := "pcs_early_eios"; + ffclk_enable : string := "ffclk_off"; + iqtxrxclk_a_sel : string := "tristage_outa"; + iqtxrxclk_b_sel : string := "tristage_outb"; + ltr_sel : string := "pcs_ltr"; + pcie_switch_sel : string := "pcs_pcie_switch_sw"; + pclk_0_clk_sel : string := "pclk_0_power_down"; + pclk_1_clk_sel : string := "pclk_1_power_down"; + tx_elec_idle_sel : string := "pcs_tx_elec_idle"; + txdetectrx_sel : string := "pcs_txdetectrx" + ); + port ( + bslip : in std_logic := '0'; + ccrurstb : in std_logic := '0'; + cearlyeios : in std_logic := '0'; + clkdivrxi : in std_logic := '0'; + clkdivtxi : in std_logic := '0'; + clklowi : in std_logic := '0'; + cltd : in std_logic := '0'; + cltr : in std_logic := '0'; + cpcieswitch : in std_logic := '0'; + crslpbk : in std_logic := '0'; + ctxdetectrx : in std_logic := '0'; + ctxelecidle : in std_logic := '0'; + ctxpmarstb : in std_logic := '0'; + earlyeios : in std_logic := '0'; + frefi : in std_logic := '0'; + hclkpcsi : in std_logic := '0'; + icoeff : in std_logic_vector(11 downto 0) := "000000000000"; + ltr : in std_logic := '0'; + pcieswdonei : in std_logic := '0'; + pcieswitch : in std_logic := '0'; + pcsrxclkout : in std_logic := '0'; + pcstxclkout : in std_logic := '0'; + pfdmodelocki : in std_logic := '0'; + pldclk : in std_logic := '0'; + ppmlock : in std_logic := '0'; + rxdetclk : in std_logic := '0'; + rxdetectvalidi : in std_logic := '0'; + rxfoundi : in std_logic := '0'; + rxplllocki : in std_logic := '0'; + rxpmarstb : in std_logic := '0'; + sdi : in std_logic := '0'; + testbusi : in std_logic_vector(7 downto 0) := "00000000"; + testsel : in std_logic_vector(3 downto 0) := "0000"; + txdetectrx : in std_logic := '0'; + txelecidle : in std_logic := '0'; + bslipo : out std_logic := '0'; + clklow : out std_logic := '0'; + cpcieswdone : out std_logic := '0'; + cpclk : out std_logic_vector(1 downto 0) := "00"; + cpfdmodelock : out std_logic := '0'; + crurstbo : out std_logic := '0'; + crxdetectvalid : out std_logic := '0'; + crxfound : out std_logic := '0'; + crxplllock : out std_logic := '0'; + csd : out std_logic := '0'; + earlyeioso : out std_logic := '0'; + fref : out std_logic := '0'; + hclkpcs : out std_logic := '0'; + icoeffo : out std_logic_vector(11 downto 0) := "000000000000"; + iqtxrxclka : out std_logic := '0'; + iqtxrxclkb : out std_logic := '0'; + ltdo : out std_logic := '0'; + ltro : out std_logic := '0'; + pcieswdone : out std_logic := '0'; + pcieswitcho : out std_logic := '0'; + pfdmodelock : out std_logic := '0'; + pldclko : out std_logic := '0'; + ppmlocko : out std_logic := '0'; + rxdetclko : out std_logic := '0'; + rxdetectvalid : out std_logic := '0'; + rxfound : out std_logic := '0'; + rxplllock : out std_logic := '0'; + rxpmarstbo : out std_logic := '0'; + sd : out std_logic := '0'; + slpbko : out std_logic := '0'; + testbus : out std_logic_vector(7 downto 0) := "00000000"; + testselo : out std_logic_vector(3 downto 0) := "0000"; + txdetectrxo : out std_logic := '0'; + txelecidleo : out std_logic := '0'; + txpmarstbo : out std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_int_encrypted + generic map ( + enable_debug_info => enable_debug_info, + channel_number => channel_number, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + cvp_mode => cvp_mode, + early_eios_sel => early_eios_sel, + ffclk_enable => ffclk_enable, + iqtxrxclk_a_sel => iqtxrxclk_a_sel, + iqtxrxclk_b_sel => iqtxrxclk_b_sel, + ltr_sel => ltr_sel, + pcie_switch_sel => pcie_switch_sel, + pclk_0_clk_sel => pclk_0_clk_sel, + pclk_1_clk_sel => pclk_1_clk_sel, + tx_elec_idle_sel => tx_elec_idle_sel, + txdetectrx_sel => txdetectrx_sel + ) + port map ( + bslip => bslip, + ccrurstb => ccrurstb, + cearlyeios => cearlyeios, + clkdivrxi => clkdivrxi, + clkdivtxi => clkdivtxi, + clklowi => clklowi, + cltd => cltd, + cltr => cltr, + cpcieswitch => cpcieswitch, + crslpbk => crslpbk, + ctxdetectrx => ctxdetectrx, + ctxelecidle => ctxelecidle, + ctxpmarstb => ctxpmarstb, + earlyeios => earlyeios, + frefi => frefi, + hclkpcsi => hclkpcsi, + icoeff => icoeff, + ltr => ltr, + pcieswdonei => pcieswdonei, + pcieswitch => pcieswitch, + pcsrxclkout => pcsrxclkout, + pcstxclkout => pcstxclkout, + pfdmodelocki => pfdmodelocki, + pldclk => pldclk, + ppmlock => ppmlock, + rxdetclk => rxdetclk, + rxdetectvalidi => rxdetectvalidi, + rxfoundi => rxfoundi, + rxplllocki => rxplllocki, + rxpmarstb => rxpmarstb, + sdi => sdi, + testbusi => testbusi, + testsel => testsel, + txdetectrx => txdetectrx, + txelecidle => txelecidle, + bslipo => bslipo, + clklow => clklow, + cpcieswdone => cpcieswdone, + cpclk => cpclk, + cpfdmodelock => cpfdmodelock, + crurstbo => crurstbo, + crxdetectvalid => crxdetectvalid, + crxfound => crxfound, + crxplllock => crxplllock, + csd => csd, + earlyeioso => earlyeioso, + fref => fref, + hclkpcs => hclkpcs, + icoeffo => icoeffo, + iqtxrxclka => iqtxrxclka, + iqtxrxclkb => iqtxrxclkb, + ltdo => ltdo, + ltro => ltro, + pcieswdone => pcieswdone, + pcieswitcho => pcieswitcho, + pfdmodelock => pfdmodelock, + pldclko => pldclko, + ppmlocko => ppmlocko, + rxdetclko => rxdetclko, + rxdetectvalid => rxdetectvalid, + rxfound => rxfound, + rxplllock => rxplllock, + rxpmarstbo => rxpmarstbo, + sd => sd, + slpbko => slpbko, + testbus => testbus, + testselo => testselo, + txdetectrxo => txdetectrxo, + txelecidleo => txelecidleo, + txpmarstbo => txpmarstbo, + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmwrite => avmmwrite, + avmmread => avmmread, + avmmbyteen => avmmbyteen, + avmmaddress => avmmaddress, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_rx_buf is + generic ( + enable_debug_info : string := "false"; + cdrclk_to_cgb : string := "cdrclk_2cgb_dis"; + channel_number : integer := 0; + diagnostic_loopback : string := "diag_lpbk_off"; + pdb_sd : string := "false"; + rx_dc_gain : integer := 0; + sd_off : integer := 1; + sd_on : integer := 1; + sd_threshold : integer := 3; + term_sel : string := "100 ohms"; + vcm_current_add : string := "vcm_current_1"; + vcm_sel : string := "vtt_0p80v"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + rx_sel_half_bw : string := "full_bw"; + rx_acgain_a : string := "aref_volt_0"; + rx_acgain_v : string := "vref_volt_1p0"; + ct_equalizer_setting : integer := 0; + reverse_loopback : string := "reverse_lpbk_cdr" + ); + port ( + ck0sigdet : in std_logic := '0'; + datain : in std_logic := '0'; + hardoccalen : in std_logic := '0'; + lpbkp : in std_logic := '0'; + rstn : in std_logic := '0'; + slpbk : in std_logic := '0'; + dataout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0'; + rdlpbkp : out std_logic := '0'; + sd : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_pma_rx_buf; + +architecture behavior of cyclonev_hssi_pma_rx_buf is + +component cyclonev_hssi_pma_rx_buf_encrypted + generic ( + enable_debug_info : string := "false"; + cdrclk_to_cgb : string := "cdrclk_2cgb_dis"; + channel_number : integer := 0; + diagnostic_loopback : string := "diag_lpbk_off"; + pdb_sd : string := "false"; + rx_dc_gain : integer := 0; + sd_off : integer := 1; + sd_on : integer := 1; + sd_threshold : integer := 3; + term_sel : string := "100 ohms"; + vcm_current_add : string := "vcm_current_1"; + vcm_sel : string := "vtt_0p80v"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + rx_sel_half_bw : string := "full_bw"; + rx_acgain_a : string := "aref_volt_0"; + rx_acgain_v : string := "vref_volt_1p0" + ); + port ( + ck0sigdet : in std_logic := '0'; + datain : in std_logic := '0'; + hardoccalen : in std_logic := '0'; + lpbkp : in std_logic := '0'; + rstn : in std_logic := '0'; + slpbk : in std_logic := '0'; + dataout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0'; + rdlpbkp : out std_logic := '0'; + sd : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_rx_buf_encrypted + generic map ( + enable_debug_info => enable_debug_info, + cdrclk_to_cgb => cdrclk_to_cgb, + channel_number => channel_number, + diagnostic_loopback => diagnostic_loopback, + pdb_sd => pdb_sd, + rx_dc_gain => rx_dc_gain, + sd_off => sd_off, + sd_on => sd_on, + sd_threshold => sd_threshold, + term_sel => term_sel, + vcm_current_add => vcm_current_add, + vcm_sel => vcm_sel, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + rx_sel_half_bw => rx_sel_half_bw, + rx_acgain_a => rx_acgain_a, + rx_acgain_v => rx_acgain_v + ) + port map ( + ck0sigdet => ck0sigdet, + datain => datain, + hardoccalen => hardoccalen, + lpbkp => lpbkp, + rstn => rstn, + slpbk => slpbk, + dataout => dataout, + nonuserfrompmaux => nonuserfrompmaux, + rdlpbkp => rdlpbkp, + sd => sd, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmread => avmmread, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_rx_deser is + generic ( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + channel_number : integer := 0; + clk_forward_only_mode : string := "false"; + enable_bit_slip : string := "true"; + mode : integer := 8; + sdclk_enable : string := "false"; + vco_bypass : string := "vco_bypass_normal"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + pma_direct : string := "false" + ); + port ( + bslip : in std_logic := '0'; + clk270b : in std_logic := '0'; + clk90b : in std_logic := '0'; + deven : in std_logic := '0'; + dodd : in std_logic := '0'; + pciesw : in std_logic := '0'; + rstn : in std_logic := '0'; + clkdivrx : out std_logic := '0'; + clkdivrxrx : out std_logic := '0'; + dout : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + pciel : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_pma_rx_deser; + +architecture behavior of cyclonev_hssi_pma_rx_deser is + +component cyclonev_hssi_pma_rx_deser_encrypted + generic ( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + channel_number : integer := 0; + clk_forward_only_mode : string := "false"; + enable_bit_slip : string := "true"; + mode : integer := 8; + sdclk_enable : string := "false"; + vco_bypass : string := "vco_bypass_normal"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + pma_direct : string := "false" + ); + port ( + bslip : in std_logic := '0'; + clk270b : in std_logic := '0'; + clk90b : in std_logic := '0'; + deven : in std_logic := '0'; + dodd : in std_logic := '0'; + pciesw : in std_logic := '0'; + rstn : in std_logic := '0'; + clkdivrx : out std_logic := '0'; + clkdivrxrx : out std_logic := '0'; + dout : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + pciel : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_rx_deser_encrypted + generic map ( + enable_debug_info => enable_debug_info, + auto_negotiation => auto_negotiation, + channel_number => channel_number, + clk_forward_only_mode => clk_forward_only_mode, + enable_bit_slip => enable_bit_slip, + mode => mode, + sdclk_enable => sdclk_enable, + vco_bypass => vco_bypass, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + pma_direct => pma_direct + ) + port map ( + bslip => bslip, + clk270b => clk270b, + clk90b => clk90b, + deven => deven, + dodd => dodd, + pciesw => pciesw, + rstn => rstn, + clkdivrx => clkdivrx, + clkdivrxrx => clkdivrxrx, + dout => dout, + pciel => pciel, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmread => avmmread, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_tx_buf is + generic ( + enable_debug_info : string := "false"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + common_mode_driver_sel : string := "volt_0p65v"; + driver_resolution_ctrl : string := "disabled"; + fir_coeff_ctrl_sel : string := "ram_ctl"; + local_ib_ctl : string := "ib_29ohm"; + lst : string := "atb_disabled"; + pre_emp_switching_ctrl_1st_post_tap : integer := 0; + rx_det : integer := 0; + rx_det_pdb : string := "false"; + slew_rate_ctrl : integer := 5; + swing_boost : string := "not_boost"; + term_sel : string := "100 ohms"; + vcm_current_addl : string := "vcm_current_1"; + vod_boost : string := "not_boost"; + vod_switching_ctrl_main_tap : integer := 10; + local_ib_en : string := "no_local_ib"; + cml_en : string := "no_cml"; + tx_powerdown : string := "normal_tx_on" + ); + port ( + avgvon : in std_logic := '0'; + avgvop : in std_logic := '0'; + datain : in std_logic := '0'; + icoeff : in std_logic_vector(11 downto 0) := "000000000000"; + rxdetclk : in std_logic := '0'; + txdetrx : in std_logic := '0'; + txelecidl : in std_logic := '0'; + vrlpbkn : in std_logic := '0'; + vrlpbkn1t : in std_logic := '0'; + vrlpbkp : in std_logic := '0'; + vrlpbkp1t : in std_logic := '0'; + compass : out std_logic := '0'; + dataout : out std_logic := '0'; + detecton : out std_logic_vector(1 downto 0) := "00"; + fixedclkout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0'; + probepass : out std_logic := '0'; + rxdetectvalid : out std_logic := '0'; + rxfound : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_pma_tx_buf; + +architecture behavior of cyclonev_hssi_pma_tx_buf is + +component cyclonev_hssi_pma_tx_buf_encrypted + generic ( + enable_debug_info : string := "false"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + common_mode_driver_sel : string := "volt_0p65v"; + driver_resolution_ctrl : string := "disabled"; + fir_coeff_ctrl_sel : string := "ram_ctl"; + local_ib_ctl : string := "ib_29ohm"; + lst : string := "atb_disabled"; + pre_emp_switching_ctrl_1st_post_tap : integer := 0; + rx_det : integer := 0; + rx_det_pdb : string := "false"; + slew_rate_ctrl : integer := 5; + swing_boost : string := "not_boost"; + term_sel : string := "100 ohms"; + vcm_current_addl : string := "vcm_current_1"; + vod_boost : string := "not_boost"; + vod_switching_ctrl_main_tap : integer := 10; + local_ib_en : string := "no_local_ib"; + cml_en : string := "no_cml" + ); + port ( + avgvon : in std_logic := '0'; + avgvop : in std_logic := '0'; + datain : in std_logic := '0'; + icoeff : in std_logic_vector(11 downto 0) := "000000000000"; + rxdetclk : in std_logic := '0'; + txdetrx : in std_logic := '0'; + txelecidl : in std_logic := '0'; + vrlpbkn : in std_logic := '0'; + vrlpbkn1t : in std_logic := '0'; + vrlpbkp : in std_logic := '0'; + vrlpbkp1t : in std_logic := '0'; + compass : out std_logic := '0'; + dataout : out std_logic := '0'; + detecton : out std_logic_vector(1 downto 0) := "00"; + fixedclkout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0'; + probepass : out std_logic := '0'; + rxdetectvalid : out std_logic := '0'; + rxfound : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_tx_buf_encrypted + generic map ( + enable_debug_info => enable_debug_info, + channel_number => channel_number, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + common_mode_driver_sel => common_mode_driver_sel, + driver_resolution_ctrl => driver_resolution_ctrl, + fir_coeff_ctrl_sel => fir_coeff_ctrl_sel, + local_ib_ctl => local_ib_ctl, + lst => lst, + pre_emp_switching_ctrl_1st_post_tap => pre_emp_switching_ctrl_1st_post_tap, + rx_det => rx_det, + rx_det_pdb => rx_det_pdb, + slew_rate_ctrl => slew_rate_ctrl, + swing_boost => swing_boost, + term_sel => term_sel, + vcm_current_addl => vcm_current_addl, + vod_boost => vod_boost, + vod_switching_ctrl_main_tap => vod_switching_ctrl_main_tap, + local_ib_en => local_ib_en, + cml_en => cml_en + ) + port map ( + avgvon => avgvon, + avgvop => avgvop, + datain => datain, + icoeff => icoeff, + rxdetclk => rxdetclk, + txdetrx => txdetrx, + txelecidl => txelecidl, + vrlpbkn => vrlpbkn, + vrlpbkn1t => vrlpbkn1t, + vrlpbkp => vrlpbkp, + vrlpbkp1t => vrlpbkp1t, + compass => compass, + dataout => dataout, + detecton => detecton, + fixedclkout => fixedclkout, + nonuserfrompmaux => nonuserfrompmaux, + probepass => probepass, + rxdetectvalid => rxdetectvalid, + rxfound => rxfound, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_tx_cgb is + generic ( + enable_debug_info : string := "false"; + reserved_transmit_channel : string := "false"; + auto_negotiation : string := "false"; + cgb_iqclk_sel : string := "tristate"; + cgb_sync : string := "normal"; + channel_number : integer := 0; + clk_mute : string := "disable_clockmute"; + data_rate : string := ""; + mode : integer := 8; + reset_scheme : string := "counter_reset_disable"; + tx_mux_power_down : string := "normal"; + x1_clock_source_sel : string := "x1_clk_unused"; + x1_div_m_sel : integer := 1; + xn_clock_source_sel : string := "cgb_x1_m_div"; + pcie_rst : string := "normal_reset"; + fref_vco_bypass : string := "normal_operation"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + x1_clock0_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock1_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock2_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock3_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock4_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock5_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock6_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock7_logical_to_physical_mapping : string := "x1_clk_unused" + ); + port ( + clkbcdr1b : in std_logic := '0'; + clkbcdr1t : in std_logic := '0'; + clkbcdrloc : in std_logic := '0'; + clkbdnseg : in std_logic := '0'; + clkbffpll : in std_logic := '0'; + clkbupseg : in std_logic := '0'; + clkcdr1b : in std_logic := '0'; + clkcdr1t : in std_logic := '0'; + clkcdrloc : in std_logic := '0'; + clkdnseg : in std_logic := '0'; + clkffpll : in std_logic := '0'; + clkupseg : in std_logic := '0'; + cpulsex6dn : in std_logic := '0'; + cpulsex6up : in std_logic := '0'; + cpulsexndn : in std_logic := '0'; + cpulsexnup : in std_logic := '0'; + hfclknx6dn : in std_logic := '0'; + hfclknx6up : in std_logic := '0'; + hfclknxndn : in std_logic := '0'; + hfclknxnup : in std_logic := '0'; + hfclkpx6dn : in std_logic := '0'; + hfclkpx6up : in std_logic := '0'; + hfclkpxndn : in std_logic := '0'; + hfclkpxnup : in std_logic := '0'; + lfclknx6dn : in std_logic := '0'; + lfclknx6up : in std_logic := '0'; + lfclknxndn : in std_logic := '0'; + lfclknxnup : in std_logic := '0'; + lfclkpx6dn : in std_logic := '0'; + lfclkpx6up : in std_logic := '0'; + lfclkpxndn : in std_logic := '0'; + lfclkpxnup : in std_logic := '0'; + pciesw : in std_logic := '0'; + pclkx6dn : in std_logic := '0'; + pclkx6up : in std_logic := '0'; + pclkxndn : in std_logic := '0'; + pclkxnup : in std_logic := '0'; + rstn : in std_logic := '0'; + rxclk : in std_logic := '0'; + cpulse : out std_logic := '0'; + cpulseout : out std_logic := '0'; + hfclkn : out std_logic := '0'; + hfclknout : out std_logic := '0'; + hfclkp : out std_logic := '0'; + hfclkpout : out std_logic := '0'; + lfclkn : out std_logic := '0'; + lfclknout : out std_logic := '0'; + lfclkp : out std_logic := '0'; + lfclkpout : out std_logic := '0'; + pcieswdone : out std_logic := '0'; + pciesyncp : out std_logic := '0'; + pclk : out std_logic_vector(2 downto 0) := "000"; + pclkout : out std_logic := '0'; + rxiqclk : out std_logic := '0'; + fref : in std_logic := '0'; + pcsrstn : in std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '1'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_pma_tx_cgb; + +architecture behavior of cyclonev_hssi_pma_tx_cgb is + +component cyclonev_hssi_pma_tx_cgb_encrypted + generic ( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + cgb_iqclk_sel : string := "tristate"; + cgb_sync : string := "normal"; + channel_number : integer := 0; + clk_mute : string := "disable_clockmute"; + data_rate : string := ""; + mode : integer := 8; + reset_scheme : string := "counter_reset_disable"; + tx_mux_power_down : string := "normal"; + x1_clock_source_sel : string := "x1_clk_unused"; + x1_div_m_sel : integer := 1; + xn_clock_source_sel : string := "cgb_x1_m_div"; + pcie_rst : string := "normal_reset"; + fref_vco_bypass : string := "normal_operation"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + x1_clock0_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock1_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock2_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock3_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock4_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock5_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock6_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock7_logical_to_physical_mapping : string := "x1_clk_unused" + ); + port ( + clkbcdr1b : in std_logic := '0'; + clkbcdr1t : in std_logic := '0'; + clkbcdrloc : in std_logic := '0'; + clkbdnseg : in std_logic := '0'; + clkbffpll : in std_logic := '0'; + clkbupseg : in std_logic := '0'; + clkcdr1b : in std_logic := '0'; + clkcdr1t : in std_logic := '0'; + clkcdrloc : in std_logic := '0'; + clkdnseg : in std_logic := '0'; + clkffpll : in std_logic := '0'; + clkupseg : in std_logic := '0'; + cpulsex6dn : in std_logic := '0'; + cpulsex6up : in std_logic := '0'; + cpulsexndn : in std_logic := '0'; + cpulsexnup : in std_logic := '0'; + hfclknx6dn : in std_logic := '0'; + hfclknx6up : in std_logic := '0'; + hfclknxndn : in std_logic := '0'; + hfclknxnup : in std_logic := '0'; + hfclkpx6dn : in std_logic := '0'; + hfclkpx6up : in std_logic := '0'; + hfclkpxndn : in std_logic := '0'; + hfclkpxnup : in std_logic := '0'; + lfclknx6dn : in std_logic := '0'; + lfclknx6up : in std_logic := '0'; + lfclknxndn : in std_logic := '0'; + lfclknxnup : in std_logic := '0'; + lfclkpx6dn : in std_logic := '0'; + lfclkpx6up : in std_logic := '0'; + lfclkpxndn : in std_logic := '0'; + lfclkpxnup : in std_logic := '0'; + pciesw : in std_logic := '0'; + pclkx6dn : in std_logic := '0'; + pclkx6up : in std_logic := '0'; + pclkxndn : in std_logic := '0'; + pclkxnup : in std_logic := '0'; + rstn : in std_logic := '0'; + rxclk : in std_logic := '0'; + cpulse : out std_logic := '0'; + cpulseout : out std_logic := '0'; + hfclkn : out std_logic := '0'; + hfclknout : out std_logic := '0'; + hfclkp : out std_logic := '0'; + hfclkpout : out std_logic := '0'; + lfclkn : out std_logic := '0'; + lfclknout : out std_logic := '0'; + lfclkp : out std_logic := '0'; + lfclkpout : out std_logic := '0'; + pcieswdone : out std_logic := '0'; + pciesyncp : out std_logic := '0'; + pclk : out std_logic_vector(2 downto 0) := "000"; + pclkout : out std_logic := '0'; + rxiqclk : out std_logic := '0'; + fref : in std_logic := '0'; + pcsrstn : in std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '1'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_tx_cgb_encrypted + generic map ( + enable_debug_info => enable_debug_info, + auto_negotiation => auto_negotiation, + cgb_iqclk_sel => cgb_iqclk_sel, + cgb_sync => cgb_sync, + channel_number => channel_number, + clk_mute => clk_mute, + data_rate => data_rate, + mode => mode, + reset_scheme => reset_scheme, + tx_mux_power_down => tx_mux_power_down, + x1_clock_source_sel => x1_clock_source_sel, + x1_div_m_sel => x1_div_m_sel, + xn_clock_source_sel => xn_clock_source_sel, + pcie_rst => pcie_rst, + fref_vco_bypass => fref_vco_bypass, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + x1_clock0_logical_to_physical_mapping => x1_clock0_logical_to_physical_mapping, + x1_clock1_logical_to_physical_mapping => x1_clock1_logical_to_physical_mapping, + x1_clock2_logical_to_physical_mapping => x1_clock2_logical_to_physical_mapping, + x1_clock3_logical_to_physical_mapping => x1_clock3_logical_to_physical_mapping, + x1_clock4_logical_to_physical_mapping => x1_clock4_logical_to_physical_mapping, + x1_clock5_logical_to_physical_mapping => x1_clock5_logical_to_physical_mapping, + x1_clock6_logical_to_physical_mapping => x1_clock6_logical_to_physical_mapping, + x1_clock7_logical_to_physical_mapping => x1_clock7_logical_to_physical_mapping + ) + port map ( + clkbcdr1b => clkbcdr1b, + clkbcdr1t => clkbcdr1t, + clkbcdrloc => clkbcdrloc, + clkbdnseg => clkbdnseg, + clkbffpll => clkbffpll, + clkbupseg => clkbupseg, + clkcdr1b => clkcdr1b, + clkcdr1t => clkcdr1t, + clkcdrloc => clkcdrloc, + clkdnseg => clkdnseg, + clkffpll => clkffpll, + clkupseg => clkupseg, + cpulsex6dn => cpulsex6dn, + cpulsex6up => cpulsex6up, + cpulsexndn => cpulsexndn, + cpulsexnup => cpulsexnup, + hfclknx6dn => hfclknx6dn, + hfclknx6up => hfclknx6up, + hfclknxndn => hfclknxndn, + hfclknxnup => hfclknxnup, + hfclkpx6dn => hfclkpx6dn, + hfclkpx6up => hfclkpx6up, + hfclkpxndn => hfclkpxndn, + hfclkpxnup => hfclkpxnup, + lfclknx6dn => lfclknx6dn, + lfclknx6up => lfclknx6up, + lfclknxndn => lfclknxndn, + lfclknxnup => lfclknxnup, + lfclkpx6dn => lfclkpx6dn, + lfclkpx6up => lfclkpx6up, + lfclkpxndn => lfclkpxndn, + lfclkpxnup => lfclkpxnup, + pciesw => pciesw, + pclkx6dn => pclkx6dn, + pclkx6up => pclkx6up, + pclkxndn => pclkxndn, + pclkxnup => pclkxnup, + rstn => rstn, + rxclk => rxclk, + cpulse => cpulse, + cpulseout => cpulseout, + hfclkn => hfclkn, + hfclknout => hfclknout, + hfclkp => hfclkp, + hfclkpout => hfclkpout, + lfclkn => lfclkn, + lfclknout => lfclknout, + lfclkp => lfclkp, + lfclkpout => lfclkpout, + pcieswdone => pcieswdone, + pciesyncp => pciesyncp, + pclk => pclk, + pclkout => pclkout, + rxiqclk => rxiqclk, + fref => fref, + pcsrstn => pcsrstn, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; +library work; +use work.CYCLONEV_HSSI_COMPONENTS.all; + + +entity cyclonev_hssi_pma_tx_ser is + generic ( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + channel_number : integer := 0; + clk_divtx_deskew : integer := 0; + clk_forward_only_mode : string := "false"; + forced_data_mode : bit := '0'; + mode : integer := 8; + post_tap_1_en : string := "false"; + ser_loopback : string := "false"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + pma_direct : string := "false"; + duty_cycle_tune : string := "duty_cycle3" + ); + port ( + cpulse : in std_logic := '0'; + datain : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + hfclk : in std_logic := '0'; + hfclkn : in std_logic := '0'; + lfclk : in std_logic := '0'; + lfclkn : in std_logic := '0'; + pclk : in std_logic_vector(2 downto 0) := "000"; + rstn : in std_logic := '1'; + slpbk : in std_logic := '0'; + clkdivtx : out std_logic := '0'; + dataout : out std_logic := '0'; + lbvop : out std_logic := '0'; + preenout : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '1'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + avgvon : out std_logic := '0'; + avgvop : out std_logic := '0' + ); +end cyclonev_hssi_pma_tx_ser; + +architecture behavior of cyclonev_hssi_pma_tx_ser is + +constant forced_data_mode_int : integer := bin2int(forced_data_mode); + +component cyclonev_hssi_pma_tx_ser_encrypted + generic ( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + channel_number : integer := 0; + clk_divtx_deskew : integer := 0; + clk_forward_only_mode : string := "false"; + forced_data_mode : integer := 0; + mode : integer := 8; + post_tap_1_en : string := "false"; + ser_loopback : string := "false"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + pma_direct : string := "false"; + duty_cycle_tune : string := "duty_cycle3" + ); + port ( + cpulse : in std_logic := '0'; + datain : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + hfclk : in std_logic := '0'; + hfclkn : in std_logic := '0'; + lfclk : in std_logic := '0'; + lfclkn : in std_logic := '0'; + pclk : in std_logic_vector(2 downto 0) := "000"; + rstn : in std_logic := '1'; + slpbk : in std_logic := '0'; + clkdivtx : out std_logic := '0'; + dataout : out std_logic := '0'; + lbvop : out std_logic := '0'; + preenout : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '1'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + avgvon : out std_logic := '0'; + avgvop : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_tx_ser_encrypted + generic map ( + enable_debug_info => enable_debug_info, + auto_negotiation => auto_negotiation, + channel_number => channel_number, + clk_divtx_deskew => clk_divtx_deskew, + clk_forward_only_mode => clk_forward_only_mode, + forced_data_mode => forced_data_mode_int, + mode => mode, + post_tap_1_en => post_tap_1_en, + ser_loopback => ser_loopback, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + pma_direct => pma_direct, + duty_cycle_tune => duty_cycle_tune + ) + port map ( + cpulse => cpulse, + datain => datain, + hfclk => hfclk, + hfclkn => hfclkn, + lfclk => lfclk, + lfclkn => lfclkn, + pclk => pclk, + rstn => rstn, + slpbk => slpbk, + clkdivtx => clkdivtx, + dataout => dataout, + lbvop => lbvop, + preenout => preenout, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmread => avmmread, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect, + avgvon => avgvon, + avgvop => avgvop + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_cdr_refclk_select_mux is + generic ( + lpm_type : string := "cyclonev_hssi_pma_cdr_refclk_select_mux"; + channel_number : integer := 0; + mux_type : string := "cdr_refclk_select_mux"; + refclk_select : string := "ref_iqclk0"; + reference_clock_frequency : string := "0 ps"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + inclk0_logical_to_physical_mapping : string := ""; + inclk1_logical_to_physical_mapping : string := ""; + inclk2_logical_to_physical_mapping : string := ""; + inclk3_logical_to_physical_mapping : string := ""; + inclk4_logical_to_physical_mapping : string := ""; + inclk5_logical_to_physical_mapping : string := ""; + inclk6_logical_to_physical_mapping : string := ""; + inclk7_logical_to_physical_mapping : string := ""; + inclk8_logical_to_physical_mapping : string := ""; + inclk9_logical_to_physical_mapping : string := ""; + inclk10_logical_to_physical_mapping : string := ""; + inclk11_logical_to_physical_mapping : string := ""; + inclk12_logical_to_physical_mapping : string := ""; + inclk13_logical_to_physical_mapping : string := ""; + inclk14_logical_to_physical_mapping : string := ""; + inclk15_logical_to_physical_mapping : string := ""; + inclk16_logical_to_physical_mapping : string := ""; + inclk17_logical_to_physical_mapping : string := ""; + inclk18_logical_to_physical_mapping : string := ""; + inclk19_logical_to_physical_mapping : string := ""; + inclk20_logical_to_physical_mapping : string := ""; + inclk21_logical_to_physical_mapping : string := ""; + inclk22_logical_to_physical_mapping : string := ""; + inclk23_logical_to_physical_mapping : string := ""; + inclk24_logical_to_physical_mapping : string := ""; + inclk25_logical_to_physical_mapping : string := "" + ); + port ( + calclk : in std_logic := '0'; + refclklc: in std_logic := '0'; + occalen : in std_logic := '0'; + ffplloutbot : in std_logic := '0'; + ffpllouttop : in std_logic := '0'; + pldclk : in std_logic := '0'; + refiqclk0 : in std_logic := '0'; + refiqclk1 : in std_logic := '0'; + refiqclk10 : in std_logic := '0'; + refiqclk2 : in std_logic := '0'; + refiqclk3 : in std_logic := '0'; + refiqclk4 : in std_logic := '0'; + refiqclk5 : in std_logic := '0'; + refiqclk6 : in std_logic := '0'; + refiqclk7 : in std_logic := '0'; + refiqclk8 : in std_logic := '0'; + refiqclk9 : in std_logic := '0'; + rxiqclk0 : in std_logic := '0'; + rxiqclk1 : in std_logic := '0'; + rxiqclk10 : in std_logic := '0'; + rxiqclk2 : in std_logic := '0'; + rxiqclk3 : in std_logic := '0'; + rxiqclk4 : in std_logic := '0'; + rxiqclk5 : in std_logic := '0'; + rxiqclk6 : in std_logic := '0'; + rxiqclk7 : in std_logic := '0'; + rxiqclk8 : in std_logic := '0'; + rxiqclk9 : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + clkout : out std_logic := '0' + ); +end cyclonev_hssi_pma_cdr_refclk_select_mux; + +architecture behavior of cyclonev_hssi_pma_cdr_refclk_select_mux is + +component cyclonev_hssi_pma_cdr_refclk_select_mux_encrypted + generic ( + lpm_type : string := "cyclonev_hssi_pma_cdr_refclk_select_mux"; + channel_number : integer := 0; + mux_type : string := "cdr_refclk_select_mux"; + refclk_select : string := "ref_iqclk0"; + reference_clock_frequency : string := "0 ps"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + inclk0_logical_to_physical_mapping : string := ""; + inclk1_logical_to_physical_mapping : string := ""; + inclk2_logical_to_physical_mapping : string := ""; + inclk3_logical_to_physical_mapping : string := ""; + inclk4_logical_to_physical_mapping : string := ""; + inclk5_logical_to_physical_mapping : string := ""; + inclk6_logical_to_physical_mapping : string := ""; + inclk7_logical_to_physical_mapping : string := ""; + inclk8_logical_to_physical_mapping : string := ""; + inclk9_logical_to_physical_mapping : string := ""; + inclk10_logical_to_physical_mapping : string := ""; + inclk11_logical_to_physical_mapping : string := ""; + inclk12_logical_to_physical_mapping : string := ""; + inclk13_logical_to_physical_mapping : string := ""; + inclk14_logical_to_physical_mapping : string := ""; + inclk15_logical_to_physical_mapping : string := ""; + inclk16_logical_to_physical_mapping : string := ""; + inclk17_logical_to_physical_mapping : string := ""; + inclk18_logical_to_physical_mapping : string := ""; + inclk19_logical_to_physical_mapping : string := ""; + inclk20_logical_to_physical_mapping : string := ""; + inclk21_logical_to_physical_mapping : string := ""; + inclk22_logical_to_physical_mapping : string := ""; + inclk23_logical_to_physical_mapping : string := ""; + inclk24_logical_to_physical_mapping : string := ""; + inclk25_logical_to_physical_mapping : string := "" + ); + port ( + calclk : in std_logic := '0'; + refclklc: in std_logic := '0'; + occalen : in std_logic := '0'; + ffplloutbot : in std_logic := '0'; + ffpllouttop : in std_logic := '0'; + pldclk : in std_logic := '0'; + refiqclk0 : in std_logic := '0'; + refiqclk1 : in std_logic := '0'; + refiqclk10 : in std_logic := '0'; + refiqclk2 : in std_logic := '0'; + refiqclk3 : in std_logic := '0'; + refiqclk4 : in std_logic := '0'; + refiqclk5 : in std_logic := '0'; + refiqclk6 : in std_logic := '0'; + refiqclk7 : in std_logic := '0'; + refiqclk8 : in std_logic := '0'; + refiqclk9 : in std_logic := '0'; + rxiqclk0 : in std_logic := '0'; + rxiqclk1 : in std_logic := '0'; + rxiqclk10 : in std_logic := '0'; + rxiqclk2 : in std_logic := '0'; + rxiqclk3 : in std_logic := '0'; + rxiqclk4 : in std_logic := '0'; + rxiqclk5 : in std_logic := '0'; + rxiqclk6 : in std_logic := '0'; + rxiqclk7 : in std_logic := '0'; + rxiqclk8 : in std_logic := '0'; + rxiqclk9 : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + clkout : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_cdr_refclk_select_mux_encrypted + generic map ( + lpm_type => lpm_type, + channel_number => channel_number, + mux_type => mux_type, + refclk_select => refclk_select, + reference_clock_frequency => reference_clock_frequency, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + inclk0_logical_to_physical_mapping => inclk0_logical_to_physical_mapping, + inclk1_logical_to_physical_mapping => inclk1_logical_to_physical_mapping, + inclk2_logical_to_physical_mapping => inclk2_logical_to_physical_mapping, + inclk3_logical_to_physical_mapping => inclk3_logical_to_physical_mapping, + inclk4_logical_to_physical_mapping => inclk4_logical_to_physical_mapping, + inclk5_logical_to_physical_mapping => inclk5_logical_to_physical_mapping, + inclk6_logical_to_physical_mapping => inclk6_logical_to_physical_mapping, + inclk7_logical_to_physical_mapping => inclk7_logical_to_physical_mapping, + inclk8_logical_to_physical_mapping => inclk8_logical_to_physical_mapping, + inclk9_logical_to_physical_mapping => inclk9_logical_to_physical_mapping, + inclk10_logical_to_physical_mapping => inclk10_logical_to_physical_mapping, + inclk11_logical_to_physical_mapping => inclk11_logical_to_physical_mapping, + inclk12_logical_to_physical_mapping => inclk12_logical_to_physical_mapping, + inclk13_logical_to_physical_mapping => inclk13_logical_to_physical_mapping, + inclk14_logical_to_physical_mapping => inclk14_logical_to_physical_mapping, + inclk15_logical_to_physical_mapping => inclk15_logical_to_physical_mapping, + inclk16_logical_to_physical_mapping => inclk16_logical_to_physical_mapping, + inclk17_logical_to_physical_mapping => inclk17_logical_to_physical_mapping, + inclk18_logical_to_physical_mapping => inclk18_logical_to_physical_mapping, + inclk19_logical_to_physical_mapping => inclk19_logical_to_physical_mapping, + inclk20_logical_to_physical_mapping => inclk20_logical_to_physical_mapping, + inclk21_logical_to_physical_mapping => inclk21_logical_to_physical_mapping, + inclk22_logical_to_physical_mapping => inclk22_logical_to_physical_mapping, + inclk23_logical_to_physical_mapping => inclk23_logical_to_physical_mapping, + inclk24_logical_to_physical_mapping => inclk24_logical_to_physical_mapping, + inclk25_logical_to_physical_mapping => inclk25_logical_to_physical_mapping + ) + port map ( + calclk => calclk, + refclklc => calclk, + occalen => calclk, + ffplloutbot => ffplloutbot, + ffpllouttop => ffpllouttop, + pldclk => pldclk, + refiqclk0 => refiqclk0, + refiqclk1 => refiqclk1, + refiqclk10 => refiqclk10, + refiqclk2 => refiqclk2, + refiqclk3 => refiqclk3, + refiqclk4 => refiqclk4, + refiqclk5 => refiqclk5, + refiqclk6 => refiqclk6, + refiqclk7 => refiqclk7, + refiqclk8 => refiqclk8, + refiqclk9 => refiqclk9, + rxiqclk0 => rxiqclk0, + rxiqclk1 => rxiqclk1, + rxiqclk10 => rxiqclk10, + rxiqclk2 => rxiqclk2, + rxiqclk3 => rxiqclk3, + rxiqclk4 => rxiqclk4, + rxiqclk5 => rxiqclk5, + rxiqclk6 => rxiqclk6, + rxiqclk7 => rxiqclk7, + rxiqclk8 => rxiqclk8, + rxiqclk9 => rxiqclk9, + avmmclk => avmmclk, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmread => avmmread, + avmmbyteen => avmmbyteen, + avmmaddress => avmmaddress, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect, + clkout => clkout + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_rx_pcs_pma_interface is + generic ( + enable_debug_info : string := "false"; + selectpcs : string := "eight_g_pcs"; + clkslip_sel : string := "pld"; + prot_mode : string := "other_protocols"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + pcs8grxclkiqout : in std_logic := '0'; + pcs8grxclkslip : in std_logic := '0'; + pldrxclkslip : in std_logic := '0'; + pldrxpmarstb : in std_logic := '0'; + pmareservedin : in std_logic_vector(4 downto 0) := "00000"; + datainfrompma : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + pmarxpllphaselockin : in std_logic := '0'; + clockinfrompma : in std_logic := '0'; + pmasigdet : in std_logic := '0'; + dataoutto8gpcs : out std_logic_vector(19 downto 0) := "00000000000000000000"; + clockoutto8gpcs : out std_logic := '0'; + pcs8gsigdetni : out std_logic := '0'; + pmareservedout : out std_logic_vector(4 downto 0) := "00000"; + pmarxclkout : out std_logic := '0'; + pmarxpllphaselockout : out std_logic := '0'; + pmarxclkslip : out std_logic := '0'; + pmarxpmarstb : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_rx_pcs_pma_interface; + +architecture behavior of cyclonev_hssi_rx_pcs_pma_interface is + +component cyclonev_hssi_rx_pcs_pma_interface_encrypted + generic ( + enable_debug_info : string := "false"; + selectpcs : string := "eight_g_pcs"; + clkslip_sel : string := "pld"; + prot_mode : string := "other_protocols"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + pcs8grxclkiqout : in std_logic := '0'; + pcs8grxclkslip : in std_logic := '0'; + pldrxclkslip : in std_logic := '0'; + pldrxpmarstb : in std_logic := '0'; + pmareservedin : in std_logic_vector(4 downto 0) := "00000"; + datainfrompma : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + pmarxpllphaselockin : in std_logic := '0'; + clockinfrompma : in std_logic := '0'; + pmasigdet : in std_logic := '0'; + dataoutto8gpcs : out std_logic_vector(19 downto 0) := "00000000000000000000"; + clockoutto8gpcs : out std_logic := '0'; + pcs8gsigdetni : out std_logic := '0'; + pmareservedout : out std_logic_vector(4 downto 0) := "00000"; + pmarxclkout : out std_logic := '0'; + pmarxpllphaselockout : out std_logic := '0'; + pmarxclkslip : out std_logic := '0'; + pmarxpmarstb : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_rx_pcs_pma_interface_encrypted + generic map ( + enable_debug_info => enable_debug_info, + selectpcs => selectpcs, + clkslip_sel => clkslip_sel, + prot_mode => prot_mode, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + pcs8grxclkiqout => pcs8grxclkiqout, + pcs8grxclkslip => pcs8grxclkslip, + pldrxclkslip => pldrxclkslip, + pldrxpmarstb => pldrxpmarstb, + pmareservedin => pmareservedin, + datainfrompma => datainfrompma, + pmarxpllphaselockin => pmarxpllphaselockin, + clockinfrompma => clockinfrompma, + pmasigdet => pmasigdet, + dataoutto8gpcs => dataoutto8gpcs, + clockoutto8gpcs => clockoutto8gpcs, + pcs8gsigdetni => pcs8gsigdetni, + pmareservedout => pmareservedout, + pmarxclkout => pmarxclkout, + pmarxpllphaselockout => pmarxpllphaselockout, + pmarxclkslip => pmarxclkslip, + pmarxpmarstb => pmarxpmarstb, + asynchdatain => asynchdatain, + reset => reset, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_rx_pld_pcs_interface is + generic ( + enable_debug_info : string := "false"; + is_8g_0ppm : string := "false"; + pcs_side_block_sel : string := "eight_g_pcs"; + pld_side_data_source : string := "pld"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipenablediocsrrdydly : in std_logic := '0'; + emsiprxspecialin : in std_logic_vector(12 downto 0) := "0000000000000"; + pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0) := "0000"; + pcs8galignstatus : in std_logic := '0'; + pcs8gbistdone : in std_logic := '0'; + pcs8gbisterr : in std_logic := '0'; + pcs8gbyteordflag : in std_logic := '0'; + pcs8gemptyrmf : in std_logic := '0'; + pcs8gemptyrx : in std_logic := '0'; + pcs8gfullrmf : in std_logic := '0'; + pcs8gfullrx : in std_logic := '0'; + pcs8grlvlt : in std_logic := '0'; + clockinfrom8gpcs : in std_logic := '0'; + pcs8grxdatavalid : in std_logic_vector(3 downto 0) := "0000"; + datainfrom8gpcs : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + pcs8gsignaldetectout : in std_logic := '0'; + pcs8gwaboundary : in std_logic_vector(4 downto 0) := "00000"; + pld8ga1a2size : in std_logic := '0'; + pld8gbitlocreven : in std_logic := '0'; + pld8gbitslip : in std_logic := '0'; + pld8gbytereven : in std_logic := '0'; + pld8gbytordpld : in std_logic := '0'; + pld8gcmpfifourstn : in std_logic := '0'; + pld8gencdt : in std_logic := '0'; + pld8gphfifourstrxn : in std_logic := '0'; + pld8gpldrxclk : in std_logic := '0'; + pld8gpolinvrx : in std_logic := '0'; + pld8grdenablermf : in std_logic := '0'; + pld8grdenablerx : in std_logic := '0'; + pld8grxurstpcsn : in std_logic := '0'; + pld8gwrdisablerx : in std_logic := '0'; + pld8gwrenablermf : in std_logic := '0'; + pldrxclkslipin : in std_logic := '0'; + pldrxpmarstbin : in std_logic := '0'; + pld8gsyncsmeninput : in std_logic := '0'; + pmarxplllock : in std_logic := '0'; + rstsel : in std_logic := '0'; + usrrstsel : in std_logic := '0'; + emsiprxout : out std_logic_vector(128 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + emsiprxspecialout : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcs8ga1a2size : out std_logic := '0'; + pcs8gbitlocreven : out std_logic := '0'; + pcs8gbitslip : out std_logic := '0'; + pcs8gbytereven : out std_logic := '0'; + pcs8gbytordpld : out std_logic := '0'; + pcs8gcmpfifourst : out std_logic := '0'; + pcs8gencdt : out std_logic := '0'; + pcs8gphfifourstrx : out std_logic := '0'; + pcs8gpldrxclk : out std_logic := '0'; + pcs8gpolinvrx : out std_logic := '0'; + pcs8grdenablermf : out std_logic := '0'; + pcs8grdenablerx : out std_logic := '0'; + pcs8grxurstpcs : out std_logic := '0'; + pcs8gsyncsmenoutput : out std_logic := '0'; + pcs8gwrdisablerx : out std_logic := '0'; + pcs8gwrenablermf : out std_logic := '0'; + pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0) := "0000"; + pld8galignstatus : out std_logic := '0'; + pld8gbistdone : out std_logic := '0'; + pld8gbisterr : out std_logic := '0'; + pld8gbyteordflag : out std_logic := '0'; + pld8gemptyrmf : out std_logic := '0'; + pld8gemptyrx : out std_logic := '0'; + pld8gfullrmf : out std_logic := '0'; + pld8gfullrx : out std_logic := '0'; + pld8grlvlt : out std_logic := '0'; + pld8grxclkout : out std_logic := '0'; + pld8grxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + pld8gsignaldetectout : out std_logic := '0'; + pld8gwaboundary : out std_logic_vector(4 downto 0) := "00000"; + pldrxclkslipout : out std_logic := '0'; + dataouttopld : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + pldrxpmarstbout : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_rx_pld_pcs_interface; + +architecture behavior of cyclonev_hssi_rx_pld_pcs_interface is + +component cyclonev_hssi_rx_pld_pcs_interface_encrypted + generic ( + enable_debug_info : string := "false"; + is_8g_0ppm : string := "false"; + pcs_side_block_sel : string := "eight_g_pcs"; + pld_side_data_source : string := "pld"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipenablediocsrrdydly : in std_logic := '0'; + emsiprxspecialin : in std_logic_vector(12 downto 0) := "0000000000000"; + pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0) := "0000"; + pcs8galignstatus : in std_logic := '0'; + pcs8gbistdone : in std_logic := '0'; + pcs8gbisterr : in std_logic := '0'; + pcs8gbyteordflag : in std_logic := '0'; + pcs8gemptyrmf : in std_logic := '0'; + pcs8gemptyrx : in std_logic := '0'; + pcs8gfullrmf : in std_logic := '0'; + pcs8gfullrx : in std_logic := '0'; + pcs8grlvlt : in std_logic := '0'; + clockinfrom8gpcs : in std_logic := '0'; + pcs8grxdatavalid : in std_logic_vector(3 downto 0) := "0000"; + datainfrom8gpcs : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + pcs8gsignaldetectout : in std_logic := '0'; + pcs8gwaboundary : in std_logic_vector(4 downto 0) := "00000"; + pld8ga1a2size : in std_logic := '0'; + pld8gbitlocreven : in std_logic := '0'; + pld8gbitslip : in std_logic := '0'; + pld8gbytereven : in std_logic := '0'; + pld8gbytordpld : in std_logic := '0'; + pld8gcmpfifourstn : in std_logic := '0'; + pld8gencdt : in std_logic := '0'; + pld8gphfifourstrxn : in std_logic := '0'; + pld8gpldrxclk : in std_logic := '0'; + pld8gpolinvrx : in std_logic := '0'; + pld8grdenablermf : in std_logic := '0'; + pld8grdenablerx : in std_logic := '0'; + pld8grxurstpcsn : in std_logic := '0'; + pld8gwrdisablerx : in std_logic := '0'; + pld8gwrenablermf : in std_logic := '0'; + pldrxclkslipin : in std_logic := '0'; + pldrxpmarstbin : in std_logic := '0'; + pld8gsyncsmeninput : in std_logic := '0'; + pmarxplllock : in std_logic := '0'; + rstsel : in std_logic := '0'; + usrrstsel : in std_logic := '0'; + emsiprxout : out std_logic_vector(128 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + emsiprxspecialout : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcs8ga1a2size : out std_logic := '0'; + pcs8gbitlocreven : out std_logic := '0'; + pcs8gbitslip : out std_logic := '0'; + pcs8gbytereven : out std_logic := '0'; + pcs8gbytordpld : out std_logic := '0'; + pcs8gcmpfifourst : out std_logic := '0'; + pcs8gencdt : out std_logic := '0'; + pcs8gphfifourstrx : out std_logic := '0'; + pcs8gpldrxclk : out std_logic := '0'; + pcs8gpolinvrx : out std_logic := '0'; + pcs8grdenablermf : out std_logic := '0'; + pcs8grdenablerx : out std_logic := '0'; + pcs8grxurstpcs : out std_logic := '0'; + pcs8gsyncsmenoutput : out std_logic := '0'; + pcs8gwrdisablerx : out std_logic := '0'; + pcs8gwrenablermf : out std_logic := '0'; + pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0) := "0000"; + pld8galignstatus : out std_logic := '0'; + pld8gbistdone : out std_logic := '0'; + pld8gbisterr : out std_logic := '0'; + pld8gbyteordflag : out std_logic := '0'; + pld8gemptyrmf : out std_logic := '0'; + pld8gemptyrx : out std_logic := '0'; + pld8gfullrmf : out std_logic := '0'; + pld8gfullrx : out std_logic := '0'; + pld8grlvlt : out std_logic := '0'; + pld8grxclkout : out std_logic := '0'; + pld8grxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + pld8gsignaldetectout : out std_logic := '0'; + pld8gwaboundary : out std_logic_vector(4 downto 0) := "00000"; + pldrxclkslipout : out std_logic := '0'; + dataouttopld : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + pldrxpmarstbout : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_rx_pld_pcs_interface_encrypted + generic map ( + enable_debug_info => enable_debug_info, + is_8g_0ppm => is_8g_0ppm, + pcs_side_block_sel => pcs_side_block_sel, + pld_side_data_source => pld_side_data_source, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + emsipenablediocsrrdydly => emsipenablediocsrrdydly, + emsiprxspecialin => emsiprxspecialin, + pcs8ga1a2k1k2flag => pcs8ga1a2k1k2flag, + pcs8galignstatus => pcs8galignstatus, + pcs8gbistdone => pcs8gbistdone, + pcs8gbisterr => pcs8gbisterr, + pcs8gbyteordflag => pcs8gbyteordflag, + pcs8gemptyrmf => pcs8gemptyrmf, + pcs8gemptyrx => pcs8gemptyrx, + pcs8gfullrmf => pcs8gfullrmf, + pcs8gfullrx => pcs8gfullrx, + pcs8grlvlt => pcs8grlvlt, + clockinfrom8gpcs => clockinfrom8gpcs, + pcs8grxdatavalid => pcs8grxdatavalid, + datainfrom8gpcs => datainfrom8gpcs, + pcs8gsignaldetectout => pcs8gsignaldetectout, + pcs8gwaboundary => pcs8gwaboundary, + pld8ga1a2size => pld8ga1a2size, + pld8gbitlocreven => pld8gbitlocreven, + pld8gbitslip => pld8gbitslip, + pld8gbytereven => pld8gbytereven, + pld8gbytordpld => pld8gbytordpld, + pld8gcmpfifourstn => pld8gcmpfifourstn, + pld8gencdt => pld8gencdt, + pld8gphfifourstrxn => pld8gphfifourstrxn, + pld8gpldrxclk => pld8gpldrxclk, + pld8gpolinvrx => pld8gpolinvrx, + pld8grdenablermf => pld8grdenablermf, + pld8grdenablerx => pld8grdenablerx, + pld8grxurstpcsn => pld8grxurstpcsn, + pld8gwrdisablerx => pld8gwrdisablerx, + pld8gwrenablermf => pld8gwrenablermf, + pldrxclkslipin => pldrxclkslipin, + pldrxpmarstbin => pldrxpmarstbin, + pld8gsyncsmeninput => pld8gsyncsmeninput, + pmarxplllock => pmarxplllock, + rstsel => rstsel, + usrrstsel => usrrstsel, + emsiprxout => emsiprxout, + emsiprxspecialout => emsiprxspecialout, + pcs8ga1a2size => pcs8ga1a2size, + pcs8gbitlocreven => pcs8gbitlocreven, + pcs8gbitslip => pcs8gbitslip, + pcs8gbytereven => pcs8gbytereven, + pcs8gbytordpld => pcs8gbytordpld, + pcs8gcmpfifourst => pcs8gcmpfifourst, + pcs8gencdt => pcs8gencdt, + pcs8gphfifourstrx => pcs8gphfifourstrx, + pcs8gpldrxclk => pcs8gpldrxclk, + pcs8gpolinvrx => pcs8gpolinvrx, + pcs8grdenablermf => pcs8grdenablermf, + pcs8grdenablerx => pcs8grdenablerx, + pcs8grxurstpcs => pcs8grxurstpcs, + pcs8gsyncsmenoutput => pcs8gsyncsmenoutput, + pcs8gwrdisablerx => pcs8gwrdisablerx, + pcs8gwrenablermf => pcs8gwrenablermf, + pld8ga1a2k1k2flag => pld8ga1a2k1k2flag, + pld8galignstatus => pld8galignstatus, + pld8gbistdone => pld8gbistdone, + pld8gbisterr => pld8gbisterr, + pld8gbyteordflag => pld8gbyteordflag, + pld8gemptyrmf => pld8gemptyrmf, + pld8gemptyrx => pld8gemptyrx, + pld8gfullrmf => pld8gfullrmf, + pld8gfullrx => pld8gfullrx, + pld8grlvlt => pld8grlvlt, + pld8grxclkout => pld8grxclkout, + pld8grxdatavalid => pld8grxdatavalid, + pld8gsignaldetectout => pld8gsignaldetectout, + pld8gwaboundary => pld8gwaboundary, + pldrxclkslipout => pldrxclkslipout, + dataouttopld => dataouttopld, + pldrxpmarstbout => pldrxpmarstbout, + asynchdatain => asynchdatain, + reset => reset, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmread => avmmread, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_tx_pcs_pma_interface is + generic ( + enable_debug_info : string := "false"; + selectpcs : string := "eight_g_pcs"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + datainfrom8gpcs : in std_logic_vector(19 downto 0) := "00000000000000000000"; + pcs8gtxclkiqout : in std_logic := '0'; + pmarxfreqtxcmuplllockin : in std_logic := '0'; + clockinfrompma : in std_logic := '0'; + clockoutto8gpcs : out std_logic := '0'; + pmarxfreqtxcmuplllockout : out std_logic := '0'; + pmatxclkout : out std_logic := '0'; + dataouttopma : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_tx_pcs_pma_interface; + +architecture behavior of cyclonev_hssi_tx_pcs_pma_interface is + +component cyclonev_hssi_tx_pcs_pma_interface_encrypted + generic ( + enable_debug_info : string := "false"; + selectpcs : string := "eight_g_pcs"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + datainfrom8gpcs : in std_logic_vector(19 downto 0) := "00000000000000000000"; + pcs8gtxclkiqout : in std_logic := '0'; + pmarxfreqtxcmuplllockin : in std_logic := '0'; + clockinfrompma : in std_logic := '0'; + clockoutto8gpcs : out std_logic := '0'; + pmarxfreqtxcmuplllockout : out std_logic := '0'; + pmatxclkout : out std_logic := '0'; + dataouttopma : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_tx_pcs_pma_interface_encrypted + generic map ( + enable_debug_info => enable_debug_info, + selectpcs => selectpcs, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + datainfrom8gpcs => datainfrom8gpcs, + pcs8gtxclkiqout => pcs8gtxclkiqout, + pmarxfreqtxcmuplllockin => pmarxfreqtxcmuplllockin, + clockinfrompma => clockinfrompma, + clockoutto8gpcs => clockoutto8gpcs, + pmarxfreqtxcmuplllockout => pmarxfreqtxcmuplllockout, + pmatxclkout => pmatxclkout, + dataouttopma => dataouttopma, + asynchdatain => asynchdatain, + reset => reset, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_tx_pld_pcs_interface is + generic ( + enable_debug_info : string := "false"; + is_8g_0ppm : string := "false"; + pld_side_data_source : string := "pld"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipenablediocsrrdydly : in std_logic := '0'; + emsiptxin : in std_logic_vector(103 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + emsiptxspecialin : in std_logic_vector(12 downto 0) := "0000000000000"; + pcs8gemptytx : in std_logic := '0'; + pcs8gfulltx : in std_logic := '0'; + clockinfrom8gpcs : in std_logic := '0'; + pld8gphfifoursttxn : in std_logic := '0'; + pld8gpldtxclk : in std_logic := '0'; + pld8gpolinvtx : in std_logic := '0'; + pld8grddisabletx : in std_logic := '0'; + pld8grevloopbk : in std_logic := '0'; + pld8gtxboundarysel : in std_logic_vector(4 downto 0) := "00000"; + pld8gtxdatavalid : in std_logic_vector(3 downto 0) := "0000"; + pld8gtxurstpcsn : in std_logic := '0'; + pld8gwrenabletx : in std_logic := '0'; + datainfrompld : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + pmatxcmuplllock : in std_logic := '0'; + rstsel : in std_logic := '0'; + usrrstsel : in std_logic := '0'; + emsippcstxclkout : out std_logic_vector(2 downto 0) := "000"; + emsiptxspecialout : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcs8gphfifoursttx : out std_logic := '0'; + pcs8gpldtxclk : out std_logic := '0'; + pcs8gpolinvtx : out std_logic := '0'; + pcs8grddisabletx : out std_logic := '0'; + pcs8grevloopbk : out std_logic := '0'; + pcs8gtxboundarysel : out std_logic_vector(4 downto 0) := "00000"; + pcs8gtxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + dataoutto8gpcs : out std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + pcs8gtxurstpcs : out std_logic := '0'; + pcs8gwrenabletx : out std_logic := '0'; + pld8gemptytx : out std_logic := '0'; + pld8gfulltx : out std_logic := '0'; + pld8gtxclkout : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end cyclonev_hssi_tx_pld_pcs_interface; + +architecture behavior of cyclonev_hssi_tx_pld_pcs_interface is + +component cyclonev_hssi_tx_pld_pcs_interface_encrypted + generic ( + enable_debug_info : string := "false"; + is_8g_0ppm : string := "false"; + pld_side_data_source : string := "pld"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipenablediocsrrdydly : in std_logic := '0'; + emsiptxin : in std_logic_vector(103 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + emsiptxspecialin : in std_logic_vector(12 downto 0) := "0000000000000"; + pcs8gemptytx : in std_logic := '0'; + pcs8gfulltx : in std_logic := '0'; + clockinfrom8gpcs : in std_logic := '0'; + pld8gphfifoursttxn : in std_logic := '0'; + pld8gpldtxclk : in std_logic := '0'; + pld8gpolinvtx : in std_logic := '0'; + pld8grddisabletx : in std_logic := '0'; + pld8grevloopbk : in std_logic := '0'; + pld8gtxboundarysel : in std_logic_vector(4 downto 0) := "00000"; + pld8gtxdatavalid : in std_logic_vector(3 downto 0) := "0000"; + pld8gtxurstpcsn : in std_logic := '0'; + pld8gwrenabletx : in std_logic := '0'; + datainfrompld : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + pmatxcmuplllock : in std_logic := '0'; + rstsel : in std_logic := '0'; + usrrstsel : in std_logic := '0'; + emsippcstxclkout : out std_logic_vector(2 downto 0) := "000"; + emsiptxspecialout : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcs8gphfifoursttx : out std_logic := '0'; + pcs8gpldtxclk : out std_logic := '0'; + pcs8gpolinvtx : out std_logic := '0'; + pcs8grddisabletx : out std_logic := '0'; + pcs8grevloopbk : out std_logic := '0'; + pcs8gtxboundarysel : out std_logic_vector(4 downto 0) := "00000"; + pcs8gtxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + dataoutto8gpcs : out std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + pcs8gtxurstpcs : out std_logic := '0'; + pcs8gwrenabletx : out std_logic := '0'; + pld8gemptytx : out std_logic := '0'; + pld8gfulltx : out std_logic := '0'; + pld8gtxclkout : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_tx_pld_pcs_interface_encrypted + generic map ( + enable_debug_info => enable_debug_info, + is_8g_0ppm => is_8g_0ppm, + pld_side_data_source => pld_side_data_source, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address + ) + port map ( + emsipenablediocsrrdydly => emsipenablediocsrrdydly, + emsiptxin => emsiptxin, + emsiptxspecialin => emsiptxspecialin, + pcs8gemptytx => pcs8gemptytx, + pcs8gfulltx => pcs8gfulltx, + clockinfrom8gpcs => clockinfrom8gpcs, + pld8gphfifoursttxn => pld8gphfifoursttxn, + pld8gpldtxclk => pld8gpldtxclk, + pld8gpolinvtx => pld8gpolinvtx, + pld8grddisabletx => pld8grddisabletx, + pld8grevloopbk => pld8grevloopbk, + pld8gtxboundarysel => pld8gtxboundarysel, + pld8gtxdatavalid => pld8gtxdatavalid, + pld8gtxurstpcsn => pld8gtxurstpcsn, + pld8gwrenabletx => pld8gwrenabletx, + datainfrompld => datainfrompld, + pmatxcmuplllock => pmatxcmuplllock, + rstsel => rstsel, + usrrstsel => usrrstsel, + emsippcstxclkout => emsippcstxclkout, + emsiptxspecialout => emsiptxspecialout, + pcs8gphfifoursttx => pcs8gphfifoursttx, + pcs8gpldtxclk => pcs8gpldtxclk, + pcs8gpolinvtx => pcs8gpolinvtx, + pcs8grddisabletx => pcs8grddisabletx, + pcs8grevloopbk => pcs8grevloopbk, + pcs8gtxboundarysel => pcs8gtxboundarysel, + pcs8gtxdatavalid => pcs8gtxdatavalid, + dataoutto8gpcs => dataoutto8gpcs, + pcs8gtxurstpcs => pcs8gtxurstpcs, + pcs8gwrenabletx => pcs8gwrenabletx, + pld8gemptytx => pld8gemptytx, + pld8gfulltx => pld8gfulltx, + pld8gtxclkout => pld8gtxclkout, + asynchdatain => asynchdatain, + reset => reset, + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmread => avmmread, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_refclk_divider is + generic ( + lpm_type : string := "cyclonev_hssi_refclk_divider"; + divide_by : integer := 1; + enabled : string := "true"; + refclk_coupling_termination : string := "normal_100_ohm_termination" + ); + port ( + refclkin : in std_logic := '0'; + refclkout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0' + ); +end cyclonev_hssi_refclk_divider; + +architecture behavior of cyclonev_hssi_refclk_divider is + +component cyclonev_hssi_refclk_divider_encrypted + generic ( + lpm_type : string := "cyclonev_hssi_refclk_divider"; + divide_by : integer := 1; + enabled : string := "true"; + refclk_coupling_termination : string := "normal_100_ohm_termination" + ); + port ( + refclkin : in std_logic := '0'; + refclkout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_refclk_divider_encrypted + generic map ( + lpm_type => lpm_type, + divide_by => divide_by, + enabled => enabled, + refclk_coupling_termination => refclk_coupling_termination + ) + port map ( + refclkin => refclkin, + refclkout => refclkout, + nonuserfrompmaux => nonuserfrompmaux + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_pll_aux is + generic ( + lpm_type : string := "cyclonev_pll_aux"; + pl_aux_atb_atben0_precomp : bit := '1'; + pl_aux_atb_atben1_precomp : bit := '1'; + pl_aux_atb_comp_minus : bit := '0'; + pl_aux_atb_comp_plus : bit := '0'; + pl_aux_comp_pwr_dn : bit := '1' + ); + port ( + atb0out : in std_logic := '0'; + atb1out : in std_logic := '0'; + atbcompout : out std_logic := '0' + ); +end cyclonev_pll_aux; + +architecture behavior of cyclonev_pll_aux is + +begin + +--empty + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_channel_pll is + generic ( + sim_use_fast_model : string := "true"; + enable_debug_info : string := "false"; + cvp_en_iocsr : string := "false"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + reference_clock_frequency : string := ""; + output_clock_frequency : string := ""; + enabled_for_reconfig : string := "false"; + bbpd_salatch_offset_ctrl_clk0 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk180 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk270 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk90 : string := "offset_0mv"; + bbpd_salatch_sel : string := "normal"; + bypass_cp_rgla : string := "false"; + cdr_atb_select : string := "atb_disable"; + cgb_clk_enable : string := "false"; + charge_pump_current_test : string := "enable_ch_pump_normal"; + clklow_fref_to_ppm_div_sel : integer := 1; + clock_monitor : string := "lpbk_data"; + diag_rev_lpbk : string := "false"; + enable_gpon_detection : string := "false"; + fast_lock_mode : string := "true"; + fb_sel : string := "vcoclk"; + hs_levshift_power_supply_setting : integer := 1; + ignore_phslock : string := "false"; + l_counter_pd_clock_disable : string := "false"; + m_counter : integer := 1; + pcie_freq_control : string := "pcie_100mhz"; + pd_charge_pump_current_ctrl : integer := 5; + pd_l_counter : integer := 1; + pfd_charge_pump_current_ctrl : integer := 20; + pfd_l_counter : integer := 1; + powerdown : string := "false"; + ref_clk_div : integer := 1; + regulator_volt_inc : string := "0"; + replica_bias_ctrl : string := "true"; + reverse_serial_lpbk : string := "false"; + ripple_cap_ctrl : string := "none"; + rxpll_pd_bw_ctrl : integer := 300; + rxpll_pfd_bw_ctrl : integer := 3200; + txpll_hclk_driver_enable : string := "false"; + vco_overange_ref : string := "ref_2"; + vco_range_ctrl_en : string := "true" + ); + port ( + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + clkindeser : in std_logic := '0'; + crurstb : in std_logic := '0'; + earlyeios : in std_logic := '0'; + extclk : in std_logic := '0'; + lpbkpreen : in std_logic := '0'; + ltd : in std_logic := '0'; + ltr : in std_logic := '0'; + occalen : in std_logic := '0'; + pciel : in std_logic := '0'; + pciesw : in std_logic_vector(1 downto 0) := "00"; + ppmlock : in std_logic := '0'; + refclk : in std_logic := '0'; + rstn : in std_logic := '0'; + rxp : in std_logic := '0'; + sd : in std_logic := '0'; + ck0pd : out std_logic := '0'; + ck180pd : out std_logic := '0'; + ck270pd : out std_logic := '0'; + ck90pd : out std_logic := '0'; + clk270bdes : out std_logic := '0'; + clk90bdes : out std_logic := '0'; + clkcdr : out std_logic := '0'; + clklow : out std_logic := '0'; + deven : out std_logic := '0'; + dodd : out std_logic := '0'; + fref : out std_logic := '0'; + pdof : out std_logic_vector(3 downto 0) := "0000"; + pfdmodelock : out std_logic := '0'; + rxlpbdp : out std_logic := '0'; + rxlpbp : out std_logic := '0'; + rxplllock : out std_logic := '0'; + txpllhclk : out std_logic := '0'; + txrlpbk : out std_logic := '0'; + vctrloverrange : out std_logic := '0' + ); +end cyclonev_channel_pll; + +architecture behavior of cyclonev_channel_pll is + +component cyclonev_channel_pll_encrypted + generic ( + sim_use_fast_model : string := "true"; + enable_debug_info : string := "false"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + reference_clock_frequency : string := ""; + output_clock_frequency : string := ""; + enabled_for_reconfig : string := "false"; + bbpd_salatch_offset_ctrl_clk0 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk180 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk270 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk90 : string := "offset_0mv"; + bbpd_salatch_sel : string := "normal"; + bypass_cp_rgla : string := "false"; + cdr_atb_select : string := "atb_disable"; + cgb_clk_enable : string := "false"; + charge_pump_current_test : string := "enable_ch_pump_normal"; + clklow_fref_to_ppm_div_sel : integer := 1; + clock_monitor : string := "lpbk_data"; + diag_rev_lpbk : string := "false"; + enable_gpon_detection : string := "false"; + fast_lock_mode : string := "true"; + fb_sel : string := "vcoclk"; + hs_levshift_power_supply_setting : integer := 1; + ignore_phslock : string := "false"; + l_counter_pd_clock_disable : string := "false"; + m_counter : integer := 1; + pcie_freq_control : string := "pcie_100mhz"; + pd_charge_pump_current_ctrl : integer := 5; + pd_l_counter : integer := 1; + pfd_charge_pump_current_ctrl : integer := 20; + pfd_l_counter : integer := 1; + powerdown : string := "false"; + ref_clk_div : integer := 1; + regulator_volt_inc : string := "0"; + replica_bias_ctrl : string := "true"; + reverse_serial_lpbk : string := "false"; + ripple_cap_ctrl : string := "none"; + rxpll_pd_bw_ctrl : integer := 300; + rxpll_pfd_bw_ctrl : integer := 3200; + txpll_hclk_driver_enable : string := "false"; + vco_overange_ref : string := "ref_2"; + vco_range_ctrl_en : string := "true" + ); + port ( + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + clkindeser : in std_logic := '0'; + crurstb : in std_logic := '0'; + earlyeios : in std_logic := '0'; + extclk : in std_logic := '0'; + lpbkpreen : in std_logic := '0'; + ltd : in std_logic := '0'; + ltr : in std_logic := '0'; + occalen : in std_logic := '0'; + pciel : in std_logic := '0'; + pciesw : in std_logic_vector(1 downto 0) := "00"; + ppmlock : in std_logic := '0'; + refclk : in std_logic := '0'; + rstn : in std_logic := '0'; + rxp : in std_logic := '0'; + sd : in std_logic := '0'; + ck0pd : out std_logic := '0'; + ck180pd : out std_logic := '0'; + ck270pd : out std_logic := '0'; + ck90pd : out std_logic := '0'; + clk270bdes : out std_logic := '0'; + clk90bdes : out std_logic := '0'; + clkcdr : out std_logic := '0'; + clklow : out std_logic := '0'; + deven : out std_logic := '0'; + dodd : out std_logic := '0'; + fref : out std_logic := '0'; + pdof : out std_logic_vector(3 downto 0) := "0000"; + pfdmodelock : out std_logic := '0'; + rxlpbdp : out std_logic := '0'; + rxlpbp : out std_logic := '0'; + rxplllock : out std_logic := '0'; + txpllhclk : out std_logic := '0'; + txrlpbk : out std_logic := '0'; + vctrloverrange : out std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_channel_pll_encrypted + generic map ( + sim_use_fast_model => sim_use_fast_model, + enable_debug_info => enable_debug_info, + avmm_group_channel_index => avmm_group_channel_index, + use_default_base_address => use_default_base_address, + user_base_address => user_base_address, + reference_clock_frequency => reference_clock_frequency, + output_clock_frequency => output_clock_frequency, + enabled_for_reconfig => enabled_for_reconfig, + bbpd_salatch_offset_ctrl_clk0 => bbpd_salatch_offset_ctrl_clk0, + bbpd_salatch_offset_ctrl_clk180 => bbpd_salatch_offset_ctrl_clk180, + bbpd_salatch_offset_ctrl_clk270 => bbpd_salatch_offset_ctrl_clk270, + bbpd_salatch_offset_ctrl_clk90 => bbpd_salatch_offset_ctrl_clk90, + bbpd_salatch_sel => bbpd_salatch_sel, + bypass_cp_rgla => bypass_cp_rgla, + cdr_atb_select => cdr_atb_select, + cgb_clk_enable => cgb_clk_enable, + charge_pump_current_test => charge_pump_current_test, + clklow_fref_to_ppm_div_sel => clklow_fref_to_ppm_div_sel, + clock_monitor => clock_monitor, + diag_rev_lpbk => diag_rev_lpbk, + enable_gpon_detection => enable_gpon_detection, + fast_lock_mode => fast_lock_mode, + fb_sel => fb_sel, + hs_levshift_power_supply_setting => hs_levshift_power_supply_setting, + ignore_phslock => ignore_phslock, + l_counter_pd_clock_disable => l_counter_pd_clock_disable, + m_counter => m_counter, + pcie_freq_control => pcie_freq_control, + pd_charge_pump_current_ctrl => pd_charge_pump_current_ctrl, + pd_l_counter => pd_l_counter, + pfd_charge_pump_current_ctrl => pfd_charge_pump_current_ctrl, + pfd_l_counter => pfd_l_counter, + powerdown => powerdown, + ref_clk_div => ref_clk_div, + regulator_volt_inc => regulator_volt_inc, + replica_bias_ctrl => replica_bias_ctrl, + reverse_serial_lpbk => reverse_serial_lpbk, + ripple_cap_ctrl => ripple_cap_ctrl, + rxpll_pd_bw_ctrl => rxpll_pd_bw_ctrl, + rxpll_pfd_bw_ctrl => rxpll_pfd_bw_ctrl, + txpll_hclk_driver_enable => txpll_hclk_driver_enable, + vco_overange_ref => vco_overange_ref, + vco_range_ctrl_en => vco_range_ctrl_en + ) + port map ( + avmmaddress => avmmaddress, + avmmbyteen => avmmbyteen, + avmmclk => avmmclk, + avmmread => avmmread, + avmmrstn => avmmrstn, + avmmwrite => avmmwrite, + avmmwritedata => avmmwritedata, + avmmreaddata => avmmreaddata, + blockselect => blockselect, + clkindeser => clkindeser, + crurstb => crurstb, + earlyeios => earlyeios, + extclk => extclk, + lpbkpreen => lpbkpreen, + ltd => ltd, + ltr => ltr, + occalen => occalen, + pciel => pciel, + pciesw => pciesw, + ppmlock => ppmlock, + refclk => refclk, + rstn => rstn, + rxp => rxp, + sd => sd, + ck0pd => ck0pd, + ck180pd => ck180pd, + ck270pd => ck270pd, + ck90pd => ck90pd, + clk270bdes => clk270bdes, + clk90bdes => clk90bdes, + clkcdr => clkcdr, + clklow => clklow, + deven => deven, + dodd => dodd, + fref => fref, + pdof => pdof, + pfdmodelock => pfdmodelock, + rxlpbdp => rxlpbdp, + rxlpbp => rxlpbp, + rxplllock => rxplllock, + txpllhclk => txpllhclk, + txrlpbk => txrlpbk, + vctrloverrange => vctrloverrange + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_avmm_interface is + generic ( + num_ch0_atoms : integer := 0; + num_ch1_atoms : integer := 0; + num_ch2_atoms : integer := 0 + ); + port ( + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : in std_logic_vector(89 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + readdatachnl : in std_logic_vector(1439 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + clkchnl : out std_logic := '0'; + rstnchnl : out std_logic := '0'; + writedatachnl : out std_logic_vector(15 downto 0) := "0000000000000000"; + regaddrchnl : out std_logic_vector(10 downto 0) := "00000000000"; + writechnl : out std_logic := '0'; + readchnl : out std_logic := '0'; + byteenchnl : out std_logic_vector(1 downto 0) := "00"; + refclkdig : in std_logic := '0'; + avmmreservedin : in std_logic := '0'; + avmmreservedout : out std_logic := '0'; + dpriorstntop : out std_logic := '0'; + dprioclktop : out std_logic := '0'; + mdiodistopchnl : out std_logic := '0'; + dpriorstnmid : out std_logic := '0'; + dprioclkmid : out std_logic := '0'; + mdiodismidchnl : out std_logic := '0'; + dpriorstnbot : out std_logic := '0'; + dprioclkbot : out std_logic := '0'; + mdiodisbotchnl : out std_logic := '0'; + dpriotestsitopchnl : out std_logic_vector(3 downto 0) := "0000"; + dpriotestsimidchnl : out std_logic_vector(3 downto 0) := "0000"; + dpriotestsibotchnl : out std_logic_vector(3 downto 0) := "0000"; + pmatestbussel : in std_logic_vector(11 downto 0) := "000000000000"; + pmatestbus : out std_logic_vector(23 downto 0) := "000000000000000000000000"; + scanmoden : in std_logic := '0'; + scanshiftn : in std_logic := '0'; + interfacesel : in std_logic := '0'; + sershiftload : in std_logic := '0' + ); +end cyclonev_hssi_avmm_interface; + +architecture behavior of cyclonev_hssi_avmm_interface is + +component cyclonev_hssi_avmm_interface_encrypted + generic ( + num_ch0_atoms : integer := 0; + num_ch1_atoms : integer := 0; + num_ch2_atoms : integer := 0 + ); + port ( + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : in std_logic_vector(89 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + readdatachnl : in std_logic_vector(1439 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + clkchnl : out std_logic := '0'; + rstnchnl : out std_logic := '0'; + writedatachnl : out std_logic_vector(15 downto 0) := "0000000000000000"; + regaddrchnl : out std_logic_vector(10 downto 0) := "00000000000"; + writechnl : out std_logic := '0'; + readchnl : out std_logic := '0'; + byteenchnl : out std_logic_vector(1 downto 0) := "00"; + refclkdig : in std_logic := '0'; + avmmreservedin : in std_logic := '0'; + avmmreservedout : out std_logic := '0'; + dpriorstntop : out std_logic := '0'; + dprioclktop : out std_logic := '0'; + mdiodistopchnl : out std_logic := '0'; + dpriorstnmid : out std_logic := '0'; + dprioclkmid : out std_logic := '0'; + mdiodismidchnl : out std_logic := '0'; + dpriorstnbot : out std_logic := '0'; + dprioclkbot : out std_logic := '0'; + mdiodisbotchnl : out std_logic := '0'; + dpriotestsitopchnl : out std_logic_vector(3 downto 0) := "0000"; + dpriotestsimidchnl : out std_logic_vector(3 downto 0) := "0000"; + dpriotestsibotchnl : out std_logic_vector(3 downto 0) := "0000"; + pmatestbussel : in std_logic_vector(11 downto 0) := "000000000000"; + pmatestbus : out std_logic_vector(23 downto 0) := "000000000000000000000000"; + scanmoden : in std_logic := '0'; + scanshiftn : in std_logic := '0'; + interfacesel : in std_logic := '0'; + sershiftload : in std_logic := '0' + ); +end component; + +begin + + +inst : cyclonev_hssi_avmm_interface_encrypted + generic map ( + num_ch0_atoms => num_ch0_atoms, + num_ch1_atoms => num_ch1_atoms, + num_ch2_atoms => num_ch2_atoms + ) + port map ( + avmmrstn => avmmrstn, + avmmclk => avmmclk, + avmmwrite => avmmwrite, + avmmread => avmmread, + avmmbyteen => avmmbyteen, + avmmaddress => avmmaddress, + avmmwritedata => avmmwritedata, + blockselect => blockselect, + readdatachnl => readdatachnl, + avmmreaddata => avmmreaddata, + clkchnl => clkchnl, + rstnchnl => rstnchnl, + writedatachnl => writedatachnl, + regaddrchnl => regaddrchnl, + writechnl => writechnl, + readchnl => readchnl, + byteenchnl => byteenchnl, + refclkdig => refclkdig, + avmmreservedin => avmmreservedin, + avmmreservedout => avmmreservedout, + dpriorstntop => dpriorstntop, + dprioclktop => dprioclktop, + mdiodistopchnl => mdiodistopchnl, + dpriorstnmid => dpriorstnmid, + dprioclkmid => dprioclkmid, + mdiodismidchnl => mdiodismidchnl, + dpriorstnbot => dpriorstnbot, + dprioclkbot => dprioclkbot, + mdiodisbotchnl => mdiodisbotchnl, + dpriotestsitopchnl => dpriotestsitopchnl, + dpriotestsimidchnl => dpriotestsimidchnl, + dpriotestsibotchnl => dpriotestsibotchnl, + pmatestbussel => pmatestbussel, + pmatestbus => pmatestbus, + scanmoden => scanmoden, + scanshiftn => scanshiftn, + interfacesel => interfacesel, + sershiftload => sershiftload + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_hi_pmaif is + generic ( + lpm_type : string := "cyclonev_hssi_pma_hi_pmaif"; + tx_pma_direction_sel : string := "pcs" + ); + port ( + datainfromcore : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + datainfrompcs : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + dataouttopma : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + ); +end cyclonev_hssi_pma_hi_pmaif; + +architecture behavior of cyclonev_hssi_pma_hi_pmaif is + +component cyclonev_hssi_pma_hi_pmaif_encrypted + generic ( + tx_pma_direction_sel : string := "pcs" + ); + port ( + datainfromcore : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + datainfrompcs : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + dataouttopma : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_hi_pmaif_encrypted + generic map ( + tx_pma_direction_sel => tx_pma_direction_sel + ) + port map ( + datainfromcore => datainfromcore, + datainfrompcs => datainfrompcs, + dataouttopma => dataouttopma + ); + + +end behavior; + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity cyclonev_hssi_pma_hi_xcvrif is + generic ( + lpm_type : string := "cyclonev_hssi_pma_hi_xcvrif"; + rx_pma_direction_sel : string := "pcs" + ); + port ( + datainfrompma : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + datainfrompcs : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + dataouttopld : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + ); +end cyclonev_hssi_pma_hi_xcvrif; + +architecture behavior of cyclonev_hssi_pma_hi_xcvrif is + +component cyclonev_hssi_pma_hi_xcvrif_encrypted + generic ( + rx_pma_direction_sel : string := "pcs" + ); + port ( + datainfrompma : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + datainfrompcs : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + dataouttopld : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + ); +end component; + +begin + + +inst : cyclonev_hssi_pma_hi_xcvrif_encrypted + generic map ( + rx_pma_direction_sel => rx_pma_direction_sel + ) + port map ( + datainfrompma => datainfrompma, + datainfrompcs => datainfrompcs, + dataouttopld => dataouttopld + ); + + +end behavior; + diff --git a/Common/sim/altera/cyclonev_hssi_components.vhd b/Common/sim/altera/cyclonev_hssi_components.vhd new file mode 100644 index 0000000..cf9a5b0 --- /dev/null +++ b/Common/sim/altera/cyclonev_hssi_components.vhd @@ -0,0 +1,2242 @@ +-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +-- This simulation model contains highly confidential and +-- proprietary information of Altera and is being provided +-- in accordance with and subject to the protections of the +-- applicable Altera Program License Subscription Agreement +-- which governs its use and disclosure. Your use of Altera +-- Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, +-- and any output files any of the foregoing (including device +-- programming or simulation files), and any associated +-- documentation or information are expressly subject to the +-- terms and conditions of the Altera Program License Subscription +-- Agreement, the Altera Quartus II License Agreement, the Altera +-- MegaCore Function License Agreement, or other applicable +-- license agreement, including, without limitation, that your +-- use is for the sole purpose of simulating designs for use +-- exclusively in logic devices manufactured by Altera and sold +-- by Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. Altera products and +-- services are protected under numerous U.S. and foreign patents, +-- maskwork rights, copyrights and other intellectual property laws. +-- Altera assumes no responsibility or liability arising out of the +-- application or use of this simulation model. +-- Quartus II 15.0.0 Build 145 04/22/2015 +LIBRARY IEEE; +use IEEE.STD_LOGIC_1164.all; + +package CYCLONEV_HSSI_COMPONENTS is + +-- GENERIC utility functions BEGIN +function bin2int (s : std_logic_vector) return integer; +function bin2int (s : bit_vector) return integer; +function bin2int (s : std_logic) return integer; +function bin2int (s : bit) return integer; +function int2bit (arg : boolean) return std_logic; +function str2bin (s : string) return std_logic_vector; +function str2int (s : string) return integer; +function int2bin (arg : integer; size : integer) return std_logic_vector; +function int2bin (arg : boolean; size : integer) return std_logic_vector; +function int2bit (arg : integer) return std_logic; + +component cyclonev_channel_pll + generic +( + sim_use_fast_model : string := "true"; + enable_debug_info : string := "false"; + cvp_en_iocsr : string := "false"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + reference_clock_frequency : string := ""; + output_clock_frequency : string := ""; + enabled_for_reconfig : string := "false"; + bbpd_salatch_offset_ctrl_clk0 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk180 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk270 : string := "offset_0mv"; + bbpd_salatch_offset_ctrl_clk90 : string := "offset_0mv"; + bbpd_salatch_sel : string := "normal"; + bypass_cp_rgla : string := "false"; + cdr_atb_select : string := "atb_disable"; + cgb_clk_enable : string := "false"; + charge_pump_current_test : string := "enable_ch_pump_normal"; + clklow_fref_to_ppm_div_sel : integer := 1; + clock_monitor : string := "lpbk_data"; + diag_rev_lpbk : string := "false"; + enable_gpon_detection : string := "false"; + fast_lock_mode : string := "true"; + fb_sel : string := "vcoclk"; + hs_levshift_power_supply_setting : integer := 1; + ignore_phslock : string := "false"; + l_counter_pd_clock_disable : string := "false"; + m_counter : integer := 1; + pcie_freq_control : string := "pcie_100mhz"; + pd_charge_pump_current_ctrl : integer := 5; + pd_l_counter : integer := 1; + pfd_charge_pump_current_ctrl : integer := 20; + pfd_l_counter : integer := 1; + powerdown : string := "false"; + ref_clk_div : integer := 1; + regulator_volt_inc : string := "0"; + replica_bias_ctrl : string := "true"; + reverse_serial_lpbk : string := "false"; + ripple_cap_ctrl : string := "none"; + rxpll_pd_bw_ctrl : integer := 300; + rxpll_pfd_bw_ctrl : integer := 3200; + txpll_hclk_driver_enable : string := "false"; + vco_overange_ref : string := "ref_2"; + vco_range_ctrl_en : string := "true" + ); + port ( + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + clkindeser : in std_logic := '0'; + crurstb : in std_logic := '0'; + earlyeios : in std_logic := '0'; + extclk : in std_logic := '0'; + lpbkpreen : in std_logic := '0'; + ltd : in std_logic := '0'; + ltr : in std_logic := '0'; + occalen : in std_logic := '0'; + pciel : in std_logic := '0'; + pciesw : in std_logic_vector(1 downto 0) := "00"; + ppmlock : in std_logic := '0'; + refclk : in std_logic := '0'; + rstn : in std_logic := '0'; + rxp : in std_logic := '0'; + sd : in std_logic := '0'; + ck0pd : out std_logic := '0'; + ck180pd : out std_logic := '0'; + ck270pd : out std_logic := '0'; + ck90pd : out std_logic := '0'; + clk270bdes : out std_logic := '0'; + clk90bdes : out std_logic := '0'; + clkcdr : out std_logic := '0'; + clklow : out std_logic := '0'; + deven : out std_logic := '0'; + dodd : out std_logic := '0'; + fref : out std_logic := '0'; + pdof : out std_logic_vector(3 downto 0) := "0000"; + pfdmodelock : out std_logic := '0'; + rxlpbdp : out std_logic := '0'; + rxlpbp : out std_logic := '0'; + rxplllock : out std_logic := '0'; + txpllhclk : out std_logic := '0'; + txrlpbk : out std_logic := '0'; + vctrloverrange : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_8g_pcs_aggregate + generic +( + enable_debug_info : string := "false"; + xaui_sm_operation : string := "en_xaui_sm"; + dskw_sm_operation : string := "dskw_xaui_sm"; + data_agg_bonding : string := "agg_disable"; + prot_mode_tx : string := "pipe_g1_tx"; + pcs_dw_datapath : string := "sw_data_path"; + dskw_control : string := "dskw_write_control"; + refclkdig_sel : string := "dis_refclk_dig_sel"; + agg_pwdn : string := "dis_agg_pwdn"; + dskw_mnumber_data : bit_vector := B"100"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + aligndetsyncbotch2 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch0 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch1 : in std_logic_vector(1 downto 0) := "00"; + aligndetsyncch2 : in std_logic_vector(1 downto 0) := "00"; + aligndetsynctopch0 : in std_logic_vector(1 downto 0) := "00"; + aligndetsynctopch1 : in std_logic_vector(1 downto 0) := "00"; + alignstatussyncbotch2 : in std_logic := '0'; + alignstatussyncch0 : in std_logic := '0'; + alignstatussyncch1 : in std_logic := '0'; + alignstatussyncch2 : in std_logic := '0'; + alignstatussynctopch0 : in std_logic := '0'; + alignstatussynctopch1 : in std_logic := '0'; + cgcomprddinbotch2 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch0 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch1 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddinch2 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddintopch0 : in std_logic_vector(1 downto 0) := "00"; + cgcomprddintopch1 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinbotch2 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch0 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch1 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrinch2 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrintopch0 : in std_logic_vector(1 downto 0) := "00"; + cgcompwrintopch1 : in std_logic_vector(1 downto 0) := "00"; + decctlbotch2 : in std_logic := '0'; + decctlch0 : in std_logic := '0'; + decctlch1 : in std_logic := '0'; + decctlch2 : in std_logic := '0'; + decctltopch0 : in std_logic := '0'; + decctltopch1 : in std_logic := '0'; + decdatabotch2 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach0 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach1 : in std_logic_vector(7 downto 0) := "00000000"; + decdatach2 : in std_logic_vector(7 downto 0) := "00000000"; + decdatatopch0 : in std_logic_vector(7 downto 0) := "00000000"; + decdatatopch1 : in std_logic_vector(7 downto 0) := "00000000"; + decdatavalidbotch2 : in std_logic := '0'; + decdatavalidch0 : in std_logic := '0'; + decdatavalidch1 : in std_logic := '0'; + decdatavalidch2 : in std_logic := '0'; + decdatavalidtopch0 : in std_logic := '0'; + decdatavalidtopch1 : in std_logic := '0'; + dedicatedaggscaninch1 : in std_logic := '0'; + delcondmetinbotch2 : in std_logic := '0'; + delcondmetinch0 : in std_logic := '0'; + delcondmetinch1 : in std_logic := '0'; + delcondmetinch2 : in std_logic := '0'; + delcondmetintopch0 : in std_logic := '0'; + delcondmetintopch1 : in std_logic := '0'; + dprioagg : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + fifoovrinbotch2 : in std_logic := '0'; + fifoovrinch0 : in std_logic := '0'; + fifoovrinch1 : in std_logic := '0'; + fifoovrinch2 : in std_logic := '0'; + fifoovrintopch0 : in std_logic := '0'; + fifoovrintopch1 : in std_logic := '0'; + fifordinbotch2 : in std_logic := '0'; + fifordinch0 : in std_logic := '0'; + fifordinch1 : in std_logic := '0'; + fifordinch2 : in std_logic := '0'; + fifordintopch0 : in std_logic := '0'; + fifordintopch1 : in std_logic := '0'; + insertincompleteinbotch2 : in std_logic := '0'; + insertincompleteinch0 : in std_logic := '0'; + insertincompleteinch1 : in std_logic := '0'; + insertincompleteinch2 : in std_logic := '0'; + insertincompleteintopch0 : in std_logic := '0'; + insertincompleteintopch1 : in std_logic := '0'; + latencycompinbotch2 : in std_logic := '0'; + latencycompinch0 : in std_logic := '0'; + latencycompinch1 : in std_logic := '0'; + latencycompinch2 : in std_logic := '0'; + latencycompintopch0 : in std_logic := '0'; + latencycompintopch1 : in std_logic := '0'; + rcvdclkch0 : in std_logic := '0'; + rcvdclkch1 : in std_logic := '0'; + rdalignbotch2 : in std_logic_vector(1 downto 0) := "00"; + rdalignch0 : in std_logic_vector(1 downto 0) := "00"; + rdalignch1 : in std_logic_vector(1 downto 0) := "00"; + rdalignch2 : in std_logic_vector(1 downto 0) := "00"; + rdaligntopch0 : in std_logic_vector(1 downto 0) := "00"; + rdaligntopch1 : in std_logic_vector(1 downto 0) := "00"; + rdenablesyncbotch2 : in std_logic := '0'; + rdenablesyncch0 : in std_logic := '0'; + rdenablesyncch1 : in std_logic := '0'; + rdenablesyncch2 : in std_logic := '0'; + rdenablesynctopch0 : in std_logic := '0'; + rdenablesynctopch1 : in std_logic := '0'; + refclkdig : in std_logic := '0'; + runningdispbotch2 : in std_logic_vector(1 downto 0) := "00"; + runningdispch0 : in std_logic_vector(1 downto 0) := "00"; + runningdispch1 : in std_logic_vector(1 downto 0) := "00"; + runningdispch2 : in std_logic_vector(1 downto 0) := "00"; + runningdisptopch0 : in std_logic_vector(1 downto 0) := "00"; + runningdisptopch1 : in std_logic_vector(1 downto 0) := "00"; + rxpcsrstn : in std_logic := '0'; + scanmoden : in std_logic := '0'; + scanshiftn : in std_logic := '0'; + syncstatusbotch2 : in std_logic := '0'; + syncstatusch0 : in std_logic := '0'; + syncstatusch1 : in std_logic := '0'; + syncstatusch2 : in std_logic := '0'; + syncstatustopch0 : in std_logic := '0'; + syncstatustopch1 : in std_logic := '0'; + txctltcbotch2 : in std_logic := '0'; + txctltcch0 : in std_logic := '0'; + txctltcch1 : in std_logic := '0'; + txctltcch2 : in std_logic := '0'; + txctltctopch0 : in std_logic := '0'; + txctltctopch1 : in std_logic := '0'; + txdatatcbotch2 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch0 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch1 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatcch2 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatctopch0 : in std_logic_vector(7 downto 0) := "00000000"; + txdatatctopch1 : in std_logic_vector(7 downto 0) := "00000000"; + txpcsrstn : in std_logic := '0'; + txpmaclk : in std_logic := '0'; + aggtestbusch0 : out std_logic_vector(15 downto 0) := "0000000000000000"; + aggtestbusch1 : out std_logic_vector(15 downto 0) := "0000000000000000"; + aggtestbusch2 : out std_logic_vector(15 downto 0) := "0000000000000000"; + alignstatusbotch2 : out std_logic := '0'; + alignstatusch0 : out std_logic := '0'; + alignstatusch1 : out std_logic := '0'; + alignstatusch2 : out std_logic := '0'; + alignstatussync0botch2 : out std_logic := '0'; + alignstatussync0ch0 : out std_logic := '0'; + alignstatussync0ch1 : out std_logic := '0'; + alignstatussync0ch2 : out std_logic := '0'; + alignstatussync0topch0 : out std_logic := '0'; + alignstatussync0topch1 : out std_logic := '0'; + alignstatustopch0 : out std_logic := '0'; + alignstatustopch1 : out std_logic := '0'; + cgcomprddallbotch2 : out std_logic := '0'; + cgcomprddallch0 : out std_logic := '0'; + cgcomprddallch1 : out std_logic := '0'; + cgcomprddallch2 : out std_logic := '0'; + cgcomprddalltopch0 : out std_logic := '0'; + cgcomprddalltopch1 : out std_logic := '0'; + cgcompwrallbotch2 : out std_logic := '0'; + cgcompwrallch0 : out std_logic := '0'; + cgcompwrallch1 : out std_logic := '0'; + cgcompwrallch2 : out std_logic := '0'; + cgcompwralltopch0 : out std_logic := '0'; + cgcompwralltopch1 : out std_logic := '0'; + dedicatedaggscanoutch0tieoff : out std_logic := '0'; + dedicatedaggscanoutch1 : out std_logic := '0'; + dedicatedaggscanoutch2tieoff : out std_logic := '0'; + delcondmet0botch2 : out std_logic := '0'; + delcondmet0ch0 : out std_logic := '0'; + delcondmet0ch1 : out std_logic := '0'; + delcondmet0ch2 : out std_logic := '0'; + delcondmet0topch0 : out std_logic := '0'; + delcondmet0topch1 : out std_logic := '0'; + endskwqdbotch2 : out std_logic := '0'; + endskwqdch0 : out std_logic := '0'; + endskwqdch1 : out std_logic := '0'; + endskwqdch2 : out std_logic := '0'; + endskwqdtopch0 : out std_logic := '0'; + endskwqdtopch1 : out std_logic := '0'; + endskwrdptrsbotch2 : out std_logic := '0'; + endskwrdptrsch0 : out std_logic := '0'; + endskwrdptrsch1 : out std_logic := '0'; + endskwrdptrsch2 : out std_logic := '0'; + endskwrdptrstopch0 : out std_logic := '0'; + endskwrdptrstopch1 : out std_logic := '0'; + fifoovr0botch2 : out std_logic := '0'; + fifoovr0ch0 : out std_logic := '0'; + fifoovr0ch1 : out std_logic := '0'; + fifoovr0ch2 : out std_logic := '0'; + fifoovr0topch0 : out std_logic := '0'; + fifoovr0topch1 : out std_logic := '0'; + fifordoutcomp0botch2 : out std_logic := '0'; + fifordoutcomp0ch0 : out std_logic := '0'; + fifordoutcomp0ch1 : out std_logic := '0'; + fifordoutcomp0ch2 : out std_logic := '0'; + fifordoutcomp0topch0 : out std_logic := '0'; + fifordoutcomp0topch1 : out std_logic := '0'; + fiforstrdqdbotch2 : out std_logic := '0'; + fiforstrdqdch0 : out std_logic := '0'; + fiforstrdqdch1 : out std_logic := '0'; + fiforstrdqdch2 : out std_logic := '0'; + fiforstrdqdtopch0 : out std_logic := '0'; + fiforstrdqdtopch1 : out std_logic := '0'; + insertincomplete0botch2 : out std_logic := '0'; + insertincomplete0ch0 : out std_logic := '0'; + insertincomplete0ch1 : out std_logic := '0'; + insertincomplete0ch2 : out std_logic := '0'; + insertincomplete0topch0 : out std_logic := '0'; + insertincomplete0topch1 : out std_logic := '0'; + latencycomp0botch2 : out std_logic := '0'; + latencycomp0ch0 : out std_logic := '0'; + latencycomp0ch1 : out std_logic := '0'; + latencycomp0ch2 : out std_logic := '0'; + latencycomp0topch0 : out std_logic := '0'; + latencycomp0topch1 : out std_logic := '0'; + rcvdclkout : out std_logic := '0'; + rcvdclkoutbot : out std_logic := '0'; + rcvdclkouttop : out std_logic := '0'; + rxctlrsbotch2 : out std_logic := '0'; + rxctlrsch0 : out std_logic := '0'; + rxctlrsch1 : out std_logic := '0'; + rxctlrsch2 : out std_logic := '0'; + rxctlrstopch0 : out std_logic := '0'; + rxctlrstopch1 : out std_logic := '0'; + rxdatarsbotch2 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch0 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch1 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarsch2 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarstopch0 : out std_logic_vector(7 downto 0) := "00000000"; + rxdatarstopch1 : out std_logic_vector(7 downto 0) := "00000000"; + txctltsbotch2 : out std_logic := '0'; + txctltsch0 : out std_logic := '0'; + txctltsch1 : out std_logic := '0'; + txctltsch2 : out std_logic := '0'; + txctltstopch0 : out std_logic := '0'; + txctltstopch1 : out std_logic := '0'; + txdatatsbotch2 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch0 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch1 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatsch2 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatstopch0 : out std_logic_vector(7 downto 0) := "00000000"; + txdatatstopch1 : out std_logic_vector(7 downto 0) := "00000000" + ); +end component; + +component cyclonev_hssi_8g_rx_pcs + generic +( + enable_debug_info : string := "false"; + prot_mode : string := "gige"; + tx_rx_parallel_loopback : string := "dis_plpbk"; + pma_dw : string := "eight_bit"; + pcs_bypass : string := "dis_pcs_bypass"; + polarity_inversion : string := "dis_pol_inv"; + wa_pd : string := "wa_pd_10"; + wa_pd_data : bit_vector := B"0"; + wa_boundary_lock_ctrl : string := "bit_slip"; + wa_pld_controlled : string := "dis_pld_ctrl"; + wa_sync_sm_ctrl : string := "gige_sync_sm"; + wa_rknumber_data : bit_vector := B"0"; + wa_renumber_data : bit_vector := B"0"; + wa_rgnumber_data : bit_vector := B"0"; + wa_rosnumber_data : bit_vector := B"0"; + wa_kchar : string := "dis_kchar"; + wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm"; + wa_clk_slip_spacing : string := "min_clk_slip_spacing"; + wa_clk_slip_spacing_data : bit_vector := B"10000"; + bit_reversal : string := "dis_bit_reversal"; + symbol_swap : string := "dis_symbol_swap"; + deskew_pattern : bit_vector := B"1101101000"; + deskew_prog_pattern_only : string := "en_deskew_prog_pat_only"; + rate_match : string := "dis_rm"; + eightb_tenb_decoder : string := "dis_8b10b"; + err_flags_sel : string := "err_flags_wa"; + polinv_8b10b_dec : string := "dis_polinv_8b10b_dec"; + eightbtenb_decoder_output_sel : string := "data_8b10b_decoder"; + invalid_code_flag_only : string := "dis_invalid_code_only"; + auto_error_replacement : string := "dis_err_replace"; + pad_or_edb_error_replace : string := "replace_edb"; + byte_deserializer : string := "dis_bds"; + byte_order : string := "dis_bo"; + re_bo_on_wa : string := "dis_re_bo_on_wa"; + bo_pattern : bit_vector := B"0"; + bo_pad : bit_vector := B"0"; + phase_compensation_fifo : string := "low_latency"; + prbs_ver : string := "dis_prbs"; + cid_pattern : string := "cid_pattern_0"; + cid_pattern_len : bit_vector := B"0"; + bist_ver : string := "dis_bist"; + cdr_ctrl : string := "dis_cdr_ctrl"; + cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask"; + wait_cnt : bit_vector := B"0"; + mask_cnt : bit_vector := X"3ff"; + eidle_entry_sd : string := "dis_eidle_sd"; + eidle_entry_eios : string := "dis_eidle_eios"; + eidle_entry_iei : string := "dis_eidle_iei"; + rx_rcvd_clk : string := "rcvd_clk_rcvd_clk"; + rx_clk1 : string := "rcvd_clk_clk1"; + rx_clk2 : string := "rcvd_clk_clk2"; + rx_rd_clk : string := "pld_rx_clk"; + dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo"; + comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl"; + bypass_pipeline_reg : string := "dis_bypass_pipeline"; + agg_block_sel : string := "same_smrt_pack"; + test_bus_sel : string := "prbs_bist_testbus"; + wa_rvnumber_data : bit_vector := B"0"; + ctrl_plane_bonding_compensation : string := "dis_compensation"; + prbs_ver_clr_flag : string := "dis_prbs_clr_flag"; + hip_mode : string := "dis_hip"; + ctrl_plane_bonding_distribution : string := "not_master_chnl_distr"; + ctrl_plane_bonding_consumption : string := "individual"; + pma_done_count : bit_vector := B"0"; + test_mode : string := "prbs"; + bist_ver_clr_flag : string := "dis_bist_clr_flag"; + wa_disp_err_flag : string := "dis_disp_err_flag"; + runlength_check : string := "en_runlength_sw"; + runlength_val : bit_vector := B"0"; + force_signal_detect : string := "en_force_signal_detect"; + deskew : string := "dis_deskew"; + rx_wr_clk : string := "rx_clk2_div_1_2_4"; + rx_clk_free_running : string := "en_rx_clk_free_run"; + rx_pcs_urst : string := "en_rx_pcs_urst"; + pipe_if_enable : string := "dis_pipe_rx"; + pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl"; + ibm_invalid_code : string := "dis_ibm_invalid_code"; + channel_number : integer := 0; + rx_refclk : string := "dis_refclk_sel"; + clock_gate_dw_rm_wr : string := "dis_dw_rm_wrclk_gating"; + clock_gate_bds_dec_asn : string := "dis_bds_dec_asn_clk_gating"; + fixed_pat_det : string := "dis_fixed_patdet"; + clock_gate_bist : string := "dis_bist_clk_gating"; + clock_gate_cdr_eidle : string := "dis_cdr_eidle_clk_gating"; + clkcmp_pattern_p : bit_vector := B"0"; + clkcmp_pattern_n : bit_vector := B"0"; + clock_gate_prbs : string := "dis_prbs_clk_gating"; + clock_gate_pc_rdclk : string := "dis_pc_rdclk_gating"; + wa_pd_polarity : string := "dis_pd_both_pol"; + clock_gate_dskw_rd : string := "dis_dskw_rdclk_gating"; + clock_gate_byteorder : string := "dis_byteorder_clk_gating"; + clock_gate_dw_pc_wrclk : string := "dis_dw_pc_wrclk_gating"; + sup_mode : string := "user_mode"; + clock_gate_sw_wa : string := "dis_sw_wa_clk_gating"; + clock_gate_dw_dskw_wr : string := "dis_dw_dskw_wrclk_gating"; + clock_gate_sw_pc_wrclk : string := "dis_sw_pc_wrclk_gating"; + clock_gate_sw_rm_rd : string := "dis_sw_rm_rdclk_gating"; + clock_gate_sw_rm_wr : string := "dis_sw_rm_wrclk_gating"; + auto_speed_nego : string := "dis_asn"; + fixed_pat_num : bit_vector := B"1111"; + clock_gate_sw_dskw_wr : string := "dis_sw_dskw_wrclk_gating"; + clock_gate_dw_rm_rd : string := "dis_dw_rm_rdclk_gating"; + clock_gate_dw_wa : string := "dis_dw_wa_clk_gating"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + a1a2size : in std_logic := '0'; + aggtestbus : in std_logic_vector(15 downto 0) := "0000000000000000"; + alignstatus : in std_logic := '0'; + alignstatussync0 : in std_logic := '0'; + alignstatussync0toporbot : in std_logic := '0'; + alignstatustoporbot : in std_logic := '0'; + bitreversalenable : in std_logic := '0'; + bitslip : in std_logic := '0'; + bytereversalenable : in std_logic := '0'; + byteorder : in std_logic := '0'; + cgcomprddall : in std_logic := '0'; + cgcomprddalltoporbot : in std_logic := '0'; + cgcompwrall : in std_logic := '0'; + cgcompwralltoporbot : in std_logic := '0'; + rmfifouserrst : in std_logic := '0'; + configselinchnldown : in std_logic := '0'; + configselinchnlup : in std_logic := '0'; + delcondmet0 : in std_logic := '0'; + delcondmet0toporbot : in std_logic := '0'; + dynclkswitchn : in std_logic := '0'; + eidleinfersel : in std_logic_vector(2 downto 0) := "000"; + endskwqd : in std_logic := '0'; + endskwqdtoporbot : in std_logic := '0'; + endskwrdptrs : in std_logic := '0'; + endskwrdptrstoporbot : in std_logic := '0'; + enablecommadetect : in std_logic := '0'; + fifoovr0 : in std_logic := '0'; + fifoovr0toporbot : in std_logic := '0'; + rmfifordincomp0 : in std_logic := '0'; + fifordincomp0toporbot : in std_logic := '0'; + fiforstrdqd : in std_logic := '0'; + fiforstrdqdtoporbot : in std_logic := '0'; + gen2ngen1 : in std_logic := '0'; + hrdrst : in std_logic := '0'; + insertincomplete0 : in std_logic := '0'; + insertincomplete0toporbot : in std_logic := '0'; + latencycomp0 : in std_logic := '0'; + latencycomp0toporbot : in std_logic := '0'; + phfifouserrst : in std_logic := '0'; + phystatusinternal : in std_logic := '0'; + phystatuspcsgen3 : in std_logic := '0'; + pipeloopbk : in std_logic := '0'; + pldltr : in std_logic := '0'; + pldrxclk : in std_logic := '0'; + polinvrx : in std_logic := '0'; + prbscidenable : in std_logic := '0'; + datain : in std_logic_vector(19 downto 0) := "00000000000000000000"; + rateswitchcontrol : in std_logic := '0'; + rcvdclkagg : in std_logic := '0'; + rcvdclkaggtoporbot : in std_logic := '0'; + rcvdclkpma : in std_logic := '0'; + rdenableinchnldown : in std_logic := '0'; + rdenableinchnlup : in std_logic := '0'; + rmfiforeadenable : in std_logic := '0'; + pcfifordenable : in std_logic := '0'; + refclkdig : in std_logic := '0'; + refclkdig2 : in std_logic := '0'; + resetpcptrsinchnldown : in std_logic := '0'; + resetpcptrsinchnlup : in std_logic := '0'; + resetppmcntrsinchnldown : in std_logic := '0'; + resetppmcntrsinchnlup : in std_logic := '0'; + ctrlfromaggblock : in std_logic := '0'; + rxcontrolrstoporbot : in std_logic := '0'; + datafrinaggblock : in std_logic_vector(7 downto 0) := "00000000"; + rxdatarstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + rxdivsyncinchnldown : in std_logic_vector(1 downto 0) := "00"; + rxdivsyncinchnlup : in std_logic_vector(1 downto 0) := "00"; + rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0) := "00"; + rxweinchnldown : in std_logic_vector(1 downto 0) := "00"; + rxweinchnlup : in std_logic_vector(1 downto 0) := "00"; + rxstatusinternal : in std_logic_vector(2 downto 0) := "000"; + rxpcsrst : in std_logic := '0'; + rxvalidinternal : in std_logic := '0'; + scanmode : in std_logic := '0'; + sigdetfrompma : in std_logic := '0'; + speedchangeinchnldown : in std_logic := '0'; + speedchangeinchnlup : in std_logic := '0'; + syncsmen : in std_logic := '0'; + txctrlplanetestbus : in std_logic_vector(19 downto 0) := "00000000000000000000"; + txdivsync : in std_logic_vector(1 downto 0) := "00"; + txpmaclk : in std_logic := '0'; + txtestbus : in std_logic_vector(19 downto 0) := "00000000000000000000"; + parallelloopback : in std_logic_vector(19 downto 0) := "00000000000000000000"; + wrenableinchnldown : in std_logic := '0'; + wrenableinchnlup : in std_logic := '0'; + pxfifowrdisable : in std_logic := '0'; + rmfifowriteenable : in std_logic := '0'; + a1a2k1k2flag : out std_logic_vector(3 downto 0) := "0000"; + aggrxpcsrst : out std_logic := '0'; + aligndetsync : out std_logic_vector(1 downto 0) := "00"; + alignstatuspld : out std_logic := '0'; + alignstatussync : out std_logic := '0'; + rmfifopartialfull : out std_logic := '0'; + rmfifopartialempty : out std_logic := '0'; + bistdone : out std_logic := '0'; + bisterr : out std_logic := '0'; + byteordflag : out std_logic := '0'; + cgcomprddout : out std_logic_vector(1 downto 0) := "00"; + cgcompwrout : out std_logic_vector(1 downto 0) := "00"; + channeltestbusout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + configseloutchnldown : out std_logic := '0'; + configseloutchnlup : out std_logic := '0'; + decoderctrl : out std_logic := '0'; + decoderdata : out std_logic_vector(7 downto 0) := "00000000"; + decoderdatavalid : out std_logic := '0'; + delcondmetout : out std_logic := '0'; + disablepcfifobyteserdes : out std_logic := '0'; + earlyeios : out std_logic := '0'; + eidleexit : out std_logic := '0'; + rmfifoempty : out std_logic := '0'; + pcfifoempty : out std_logic := '0'; + errctrl : out std_logic_vector(1 downto 0) := "00"; + errdata : out std_logic_vector(15 downto 0) := "0000000000000000"; + fifoovrout : out std_logic := '0'; + fifordoutcomp : out std_logic := '0'; + rmfifofull : out std_logic := '0'; + pcfifofull : out std_logic := '0'; + insertincompleteout : out std_logic := '0'; + latencycompout : out std_logic := '0'; + ltr : out std_logic := '0'; + pcieswitch : out std_logic := '0'; + phystatus : out std_logic := '0'; + pipedata : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + prbsdone : out std_logic := '0'; + prbserrlt : out std_logic := '0'; + rdalign : out std_logic_vector(1 downto 0) := "00"; + rdenableoutchnldown : out std_logic := '0'; + rdenableoutchnlup : out std_logic := '0'; + resetpcptrs : out std_logic := '0'; + resetpcptrsinchnldownpipe : out std_logic := '0'; + resetpcptrsinchnluppipe : out std_logic := '0'; + resetpcptrsoutchnldown : out std_logic := '0'; + resetpcptrsoutchnlup : out std_logic := '0'; + resetppmcntrsoutchnldown : out std_logic := '0'; + resetppmcntrsoutchnlup : out std_logic := '0'; + resetppmcntrspcspma : out std_logic := '0'; + parallelrevloopback : out std_logic_vector(19 downto 0) := "00000000000000000000"; + runlengthviolation : out std_logic := '0'; + rlvlt : out std_logic := '0'; + runningdisparity : out std_logic_vector(1 downto 0) := "00"; + rxblkstart : out std_logic_vector(3 downto 0) := "0000"; + clocktopld : out std_logic := '0'; + rxclkslip : out std_logic := '0'; + rxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + rxdivsyncoutchnldown : out std_logic_vector(1 downto 0) := "00"; + rxdivsyncoutchnlup : out std_logic_vector(1 downto 0) := "00"; + rxpipeclk : out std_logic := '0'; + rxpipesoftreset : out std_logic := '0'; + rxsynchdr : out std_logic_vector(1 downto 0) := "00"; + rxweoutchnldown : out std_logic_vector(1 downto 0) := "00"; + rxweoutchnlup : out std_logic_vector(1 downto 0) := "00"; + dataout : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + eidledetected : out std_logic := '0'; + rxstatus : out std_logic_vector(2 downto 0) := "000"; + rxvalid : out std_logic := '0'; + selftestdone : out std_logic := '0'; + selftesterr : out std_logic := '0'; + signaldetectout : out std_logic := '0'; + speedchange : out std_logic := '0'; + speedchangeinchnldownpipe : out std_logic := '0'; + speedchangeinchnluppipe : out std_logic := '0'; + speedchangeoutchnldown : out std_logic := '0'; + speedchangeoutchnlup : out std_logic := '0'; + syncstatus : out std_logic := '0'; + wordalignboundary : out std_logic_vector(4 downto 0) := "00000"; + wrenableoutchnldown : out std_logic := '0'; + wrenableoutchnlup : out std_logic := '0'; + syncdatain : out std_logic := '0'; + observablebyteserdesclock : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_8g_tx_pcs + generic +( + enable_debug_info : string := "false"; + prot_mode : string := "basic"; + hip_mode : string := "dis_hip"; + pma_dw : string := "eight_bit"; + pcs_bypass : string := "dis_pcs_bypass"; + phase_compensation_fifo : string := "low_latency"; + tx_compliance_controlled_disparity : string := "dis_txcompliance"; + force_kchar : string := "dis_force_kchar"; + force_echar : string := "dis_force_echar"; + byte_serializer : string := "dis_bs"; + data_selection_8b10b_encoder_input : string := "normal_data_path"; + eightb_tenb_disp_ctrl : string := "dis_disp_ctrl"; + eightb_tenb_encoder : string := "dis_8b10b"; + prbs_gen : string := "dis_prbs"; + cid_pattern : string := "cid_pattern_0"; + cid_pattern_len : bit_vector := B"0"; + bist_gen : string := "dis_bist"; + bit_reversal : string := "dis_bit_reversal"; + symbol_swap : string := "dis_symbol_swap"; + polarity_inversion : string := "dis_polinv"; + tx_bitslip : string := "dis_tx_bitslip"; + agg_block_sel : string := "same_smrt_pack"; + revloop_back_rm : string := "dis_rev_loopback_rx_rm"; + phfifo_write_clk_sel : string := "pld_tx_clk"; + ctrl_plane_bonding_consumption : string := "individual"; + bypass_pipeline_reg : string := "dis_bypass_pipeline"; + ctrl_plane_bonding_distribution : string := "not_master_chnl_distr"; + test_mode : string := "prbs"; + ctrl_plane_bonding_compensation : string := "dis_compensation"; + refclk_b_clk_sel : string := "tx_pma_clock"; + auto_speed_nego_gen2 : string := "dis_asn_g2"; + txpcs_urst : string := "en_txpcs_urst"; + clock_gate_dw_fifowr : string := "dis_dw_fifowr_clk_gating"; + clock_gate_prbs : string := "dis_prbs_clk_gating"; + txclk_freerun : string := "dis_freerun_tx"; + clock_gate_bs_enc : string := "dis_bs_enc_clk_gating"; + clock_gate_bist : string := "dis_bist_clk_gating"; + clock_gate_fiford : string := "dis_fiford_clk_gating"; + pcfifo_urst : string := "dis_pcfifourst"; + clock_gate_sw_fifowr : string := "dis_sw_fifowr_clk_gating"; + sup_mode : string := "user_mode"; + dynamic_clk_switch : string := "dis_dyn_clk_switch"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + dispcbyte : in std_logic := '0'; + elecidleinfersel : in std_logic_vector(2 downto 0) := "000"; + fifoselectinchnldown : in std_logic_vector(1 downto 0) := "00"; + fifoselectinchnlup : in std_logic_vector(1 downto 0) := "00"; + rateswitch : in std_logic := '0'; + hrdrst : in std_logic := '1'; + pipetxdeemph : in std_logic := '0'; + pipetxmargin : in std_logic_vector(2 downto 0) := "000"; + phfiforeset : in std_logic := '0'; + coreclk : in std_logic := '0'; + polinvrxin : in std_logic := '0'; + invpol : in std_logic := '0'; + powerdn : in std_logic_vector(1 downto 0) := "00"; + prbscidenable : in std_logic := '0'; + rdenableinchnldown : in std_logic := '0'; + rdenableinchnlup : in std_logic := '0'; + phfiforddisable : in std_logic := '0'; + refclkdig : in std_logic := '0'; + resetpcptrs : in std_logic := '0'; + resetpcptrsinchnldown : in std_logic := '0'; + resetpcptrsinchnlup : in std_logic := '0'; + revparallellpbkdata : in std_logic_vector(19 downto 0) := "00000000000000000000"; + enrevparallellpbk : in std_logic := '0'; + pipeenrevparallellpbkin : in std_logic := '0'; + rxpolarityin : in std_logic := '0'; + scanmode : in std_logic := '0'; + txblkstart : in std_logic_vector(3 downto 0) := "0000"; + bitslipboundaryselect : in std_logic_vector(4 downto 0) := "00000"; + xgmctrl : in std_logic := '0'; + xgmctrltoporbottom : in std_logic := '0'; + xgmdatain : in std_logic_vector(7 downto 0) := "00000000"; + xgmdataintoporbottom : in std_logic_vector(7 downto 0) := "00000000"; + txdatavalid : in std_logic_vector(3 downto 0) := "0000"; + txdivsyncinchnldown : in std_logic_vector(1 downto 0) := "00"; + txdivsyncinchnlup : in std_logic_vector(1 downto 0) := "00"; + txsynchdr : in std_logic_vector(1 downto 0) := "00"; + datain : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + detectrxloopin : in std_logic := '0'; + txpmalocalclk : in std_logic := '0'; + pipetxswing : in std_logic := '0'; + txpcsreset : in std_logic := '0'; + wrenableinchnldown : in std_logic := '0'; + wrenableinchnlup : in std_logic := '0'; + phfifowrenable : in std_logic := '0'; + aggtxpcsrst : out std_logic := '0'; + dynclkswitchn : out std_logic := '0'; + phfifounderflow : out std_logic := '0'; + fifoselectoutchnldown : out std_logic_vector(1 downto 0) := "00"; + fifoselectoutchnlup : out std_logic_vector(1 downto 0) := "00"; + phfifooverflow : out std_logic := '0'; + grayelecidleinferselout : out std_logic_vector(2 downto 0) := "000"; + phfifotxdeemph : out std_logic := '0'; + phfifotxmargin : out std_logic_vector(2 downto 0) := "000"; + phfifotxswing : out std_logic := '0'; + polinvrxout : out std_logic := '0'; + pipepowerdownout : out std_logic_vector(1 downto 0) := "00"; + dataout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + rdenableoutchnldown : out std_logic := '0'; + rdenableoutchnlup : out std_logic := '0'; + rdenablesync : out std_logic := '0'; + refclkb : out std_logic := '0'; + refclkbreset : out std_logic := '0'; + pipeenrevparallellpbkout : out std_logic := '0'; + rxpolarityout : out std_logic := '0'; + txblkstartout : out std_logic_vector(3 downto 0) := "0000"; + clkout : out std_logic := '0'; + xgmctrlenable : out std_logic := '0'; + txctrlplanetestbus : out std_logic_vector(19 downto 0) := "00000000000000000000"; + txdataouttogen3 : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + xgmdataout : out std_logic_vector(7 downto 0) := "00000000"; + txdatavalidouttogen3 : out std_logic_vector(3 downto 0) := "0000"; + txdatakouttogen3 : out std_logic_vector(3 downto 0) := "0000"; + txdivsync : out std_logic_vector(1 downto 0) := "00"; + txdivsyncoutchnldown : out std_logic_vector(1 downto 0) := "00"; + txdivsyncoutchnlup : out std_logic_vector(1 downto 0) := "00"; + txpipeclk : out std_logic := '0'; + txpipeelectidle : out std_logic := '0'; + txpipesoftreset : out std_logic := '0'; + txsynchdrout : out std_logic_vector(1 downto 0) := "00"; + txtestbus : out std_logic_vector(19 downto 0) := "00000000000000000000"; + txcomplianceout : out std_logic := '0'; + detectrxloopout : out std_logic := '0'; + txelecidleout : out std_logic := '0'; + parallelfdbkout : out std_logic_vector(19 downto 0) := "00000000000000000000"; + wrenableoutchnldown : out std_logic := '0'; + wrenableoutchnlup : out std_logic := '0'; + syncdatain : out std_logic := '0'; + observablebyteserdesclock : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '1'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_avmm_interface + generic +( + num_ch0_atoms : integer := 0; + num_ch1_atoms : integer := 0; + num_ch2_atoms : integer := 0 + ); + port ( + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : in std_logic_vector(89 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + readdatachnl : in std_logic_vector(1439 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + clkchnl : out std_logic := '0'; + rstnchnl : out std_logic := '0'; + writedatachnl : out std_logic_vector(15 downto 0) := "0000000000000000"; + regaddrchnl : out std_logic_vector(10 downto 0) := "00000000000"; + writechnl : out std_logic := '0'; + readchnl : out std_logic := '0'; + byteenchnl : out std_logic_vector(1 downto 0) := "00"; + refclkdig : in std_logic := '0'; + avmmreservedin : in std_logic := '0'; + avmmreservedout : out std_logic := '0'; + dpriorstntop : out std_logic := '0'; + dprioclktop : out std_logic := '0'; + mdiodistopchnl : out std_logic := '0'; + dpriorstnmid : out std_logic := '0'; + dprioclkmid : out std_logic := '0'; + mdiodismidchnl : out std_logic := '0'; + dpriorstnbot : out std_logic := '0'; + dprioclkbot : out std_logic := '0'; + mdiodisbotchnl : out std_logic := '0'; + dpriotestsitopchnl : out std_logic_vector(3 downto 0) := "0000"; + dpriotestsimidchnl : out std_logic_vector(3 downto 0) := "0000"; + dpriotestsibotchnl : out std_logic_vector(3 downto 0) := "0000"; + pmatestbussel : in std_logic_vector(11 downto 0) := "000000000000"; + pmatestbus : out std_logic_vector(23 downto 0) := "000000000000000000000000"; + scanmoden : in std_logic := '0'; + scanshiftn : in std_logic := '0'; + interfacesel : in std_logic := '0'; + sershiftload : in std_logic := '0' + ); +end component; + +component cyclonev_hssi_common_pcs_pma_interface + generic +( + enable_debug_info : string := "false"; + prot_mode : string := "disabled_prot_mode"; + force_freqdet : string := "force_freqdet_dis"; + ppmsel : string := "ppmsel_default"; + ppm_cnt_rst : string := "ppm_cnt_rst_dis"; + auto_speed_ena : string := "dis_auto_speed_ena"; + ppm_gen1_2_cnt : string := "cnt_32k"; + ppm_post_eidle_delay : string := "cnt_200_cycles"; + func_mode : string := "disable"; + pma_if_dft_val : string := "dft_0"; + sup_mode : string := "user_mode"; + selectpcs : string := "eight_g_pcs"; + ppm_deassert_early : string := "deassert_early_dis"; + pipe_if_g3pcs : string := "pipe_if_8gpcs"; + pma_if_dft_en : string := "dft_dis"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + aggalignstatus : in std_logic := '0'; + aggalignstatussync0 : in std_logic := '0'; + aggalignstatussync0toporbot : in std_logic := '0'; + aggalignstatustoporbot : in std_logic := '0'; + aggcgcomprddall : in std_logic := '0'; + aggcgcomprddalltoporbot : in std_logic := '0'; + aggcgcompwrall : in std_logic := '0'; + aggcgcompwralltoporbot : in std_logic := '0'; + aggdelcondmet0 : in std_logic := '0'; + aggdelcondmet0toporbot : in std_logic := '0'; + aggendskwqd : in std_logic := '0'; + aggendskwqdtoporbot : in std_logic := '0'; + aggendskwrdptrs : in std_logic := '0'; + aggendskwrdptrstoporbot : in std_logic := '0'; + aggfifoovr0 : in std_logic := '0'; + aggfifoovr0toporbot : in std_logic := '0'; + aggfifordincomp0 : in std_logic := '0'; + aggfifordincomp0toporbot : in std_logic := '0'; + aggfiforstrdqd : in std_logic := '0'; + aggfiforstrdqdtoporbot : in std_logic := '0'; + agginsertincomplete0 : in std_logic := '0'; + agginsertincomplete0toporbot : in std_logic := '0'; + agglatencycomp0 : in std_logic := '0'; + agglatencycomp0toporbot : in std_logic := '0'; + aggrcvdclkagg : in std_logic := '0'; + aggrcvdclkaggtoporbot : in std_logic := '0'; + aggrxcontrolrs : in std_logic := '0'; + aggrxcontrolrstoporbot : in std_logic := '0'; + aggrxdatars : in std_logic_vector(7 downto 0) := "00000000"; + aggrxdatarstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + aggtestsotopldin : in std_logic := '0'; + aggtestbus : in std_logic_vector(15 downto 0) := "0000000000000000"; + aggtxctlts : in std_logic := '0'; + aggtxctltstoporbot : in std_logic := '0'; + aggtxdatats : in std_logic_vector(7 downto 0) := "00000000"; + aggtxdatatstoporbot : in std_logic_vector(7 downto 0) := "00000000"; + hardreset : in std_logic := '0'; + pcs8gearlyeios : in std_logic := '0'; + pcs8geidleexit : in std_logic := '0'; + pcs8gltrpma : in std_logic := '0'; + pcs8gpcieswitch : in std_logic := '0'; + pcs8gpmacurrentcoeff : in std_logic_vector(17 downto 0) := "000000000000000000"; + pcs8gtxelecidle : in std_logic := '0'; + pcs8gtxdetectrx : in std_logic := '0'; + pcsaggaligndetsync : in std_logic_vector(1 downto 0) := "00"; + pcsaggalignstatussync : in std_logic := '0'; + pcsaggcgcomprddout : in std_logic_vector(1 downto 0) := "00"; + pcsaggcgcompwrout : in std_logic_vector(1 downto 0) := "00"; + pcsaggdecctl : in std_logic := '0'; + pcsaggdecdata : in std_logic_vector(7 downto 0) := "00000000"; + pcsaggdecdatavalid : in std_logic := '0'; + pcsaggdelcondmetout : in std_logic := '0'; + pcsaggfifoovrout : in std_logic := '0'; + pcsaggfifordoutcomp : in std_logic := '0'; + pcsagginsertincompleteout : in std_logic := '0'; + pcsagglatencycompout : in std_logic := '0'; + pcsaggrdalign : in std_logic_vector(1 downto 0) := "00"; + pcsaggrdenablesync : in std_logic := '0'; + pcsaggrefclkdig : in std_logic := '0'; + pcsaggrunningdisp : in std_logic_vector(1 downto 0) := "00"; + pcsaggrxpcsrst : in std_logic := '0'; + pcsaggscanmoden : in std_logic := '0'; + pcsaggscanshiftn : in std_logic := '0'; + pcsaggsyncstatus : in std_logic := '0'; + pcsaggtxctltc : in std_logic := '0'; + pcsaggtxdatatc : in std_logic_vector(7 downto 0) := "00000000"; + pcsaggtxpcsrst : in std_logic := '0'; + pcsrefclkdig : in std_logic := '0'; + pcsscanmoden : in std_logic := '0'; + pcsscanshiftn : in std_logic := '0'; + pldnfrzdrv : in std_logic := '0'; + pldpartialreconfig : in std_logic := '0'; + pldtestsitoaggin : in std_logic := '0'; + clklow : in std_logic := '0'; + fref : in std_logic := '0'; + pmahclk : in std_logic := '0'; + pmapcieswdone : in std_logic_vector(1 downto 0) := "00"; + pmarxdetectvalid : in std_logic := '0'; + pmarxfound : in std_logic := '0'; + pmarxpmarstb : in std_logic := '0'; + resetppmcntrs : in std_logic := '0'; + aggaligndetsync : out std_logic_vector(1 downto 0) := "00"; + aggalignstatussync : out std_logic := '0'; + aggcgcomprddout : out std_logic_vector(1 downto 0) := "00"; + aggcgcompwrout : out std_logic_vector(1 downto 0) := "00"; + aggdecctl : out std_logic := '0'; + aggdecdata : out std_logic_vector(7 downto 0) := "00000000"; + aggdecdatavalid : out std_logic := '0'; + aggdelcondmetout : out std_logic := '0'; + aggfifoovrout : out std_logic := '0'; + aggfifordoutcomp : out std_logic := '0'; + agginsertincompleteout : out std_logic := '0'; + agglatencycompout : out std_logic := '0'; + aggrdalign : out std_logic_vector(1 downto 0) := "00"; + aggrdenablesync : out std_logic := '0'; + aggrefclkdig : out std_logic := '0'; + aggrunningdisp : out std_logic_vector(1 downto 0) := "00"; + aggrxpcsrst : out std_logic := '0'; + aggscanmoden : out std_logic := '0'; + aggscanshiftn : out std_logic := '0'; + aggsyncstatus : out std_logic := '0'; + aggtestsotopldout : out std_logic := '0'; + aggtxctltc : out std_logic := '0'; + aggtxdatatc : out std_logic_vector(7 downto 0) := "00000000"; + aggtxpcsrst : out std_logic := '0'; + pcs8ggen2ngen1 : out std_logic := '0'; + pcs8gpmarxfound : out std_logic := '0'; + pcs8gpowerstatetransitiondone : out std_logic := '0'; + pcs8grxdetectvalid : out std_logic := '0'; + pcsaggalignstatus : out std_logic := '0'; + pcsaggalignstatussync0 : out std_logic := '0'; + pcsaggalignstatussync0toporbot : out std_logic := '0'; + pcsaggalignstatustoporbot : out std_logic := '0'; + pcsaggcgcomprddall : out std_logic := '0'; + pcsaggcgcomprddalltoporbot : out std_logic := '0'; + pcsaggcgcompwrall : out std_logic := '0'; + pcsaggcgcompwralltoporbot : out std_logic := '0'; + pcsaggdelcondmet0 : out std_logic := '0'; + pcsaggdelcondmet0toporbot : out std_logic := '0'; + pcsaggendskwqd : out std_logic := '0'; + pcsaggendskwqdtoporbot : out std_logic := '0'; + pcsaggendskwrdptrs : out std_logic := '0'; + pcsaggendskwrdptrstoporbot : out std_logic := '0'; + pcsaggfifoovr0 : out std_logic := '0'; + pcsaggfifoovr0toporbot : out std_logic := '0'; + pcsaggfifordincomp0 : out std_logic := '0'; + pcsaggfifordincomp0toporbot : out std_logic := '0'; + pcsaggfiforstrdqd : out std_logic := '0'; + pcsaggfiforstrdqdtoporbot : out std_logic := '0'; + pcsagginsertincomplete0 : out std_logic := '0'; + pcsagginsertincomplete0toporbot : out std_logic := '0'; + pcsagglatencycomp0 : out std_logic := '0'; + pcsagglatencycomp0toporbot : out std_logic := '0'; + pcsaggrcvdclkagg : out std_logic := '0'; + pcsaggrcvdclkaggtoporbot : out std_logic := '0'; + pcsaggrxcontrolrs : out std_logic := '0'; + pcsaggrxcontrolrstoporbot : out std_logic := '0'; + pcsaggrxdatars : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggtestbus : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcsaggtxctlts : out std_logic := '0'; + pcsaggtxctltstoporbot : out std_logic := '0'; + pcsaggtxdatats : out std_logic_vector(7 downto 0) := "00000000"; + pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0) := "00000000"; + pldhclkout : out std_logic := '0'; + pldtestsitoaggout : out std_logic := '0'; + pmaclklowout : out std_logic := '0'; + pmacurrentcoeff : out std_logic_vector(17 downto 0) := "000000000000000000"; + pmaearlyeios : out std_logic := '0'; + pmafrefout : out std_logic := '0'; + pmaiftestbus : out std_logic_vector(9 downto 0) := "0000000000"; + pmaltr : out std_logic := '0'; + pmanfrzdrv : out std_logic := '0'; + pmapartialreconfig : out std_logic := '0'; + pmapcieswitch : out std_logic_vector(1 downto 0) := "00"; + freqlock : out std_logic := '0'; + pmatxelecidle : out std_logic := '0'; + pmatxdetectrx : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_common_pld_pcs_interface + generic +( + enable_debug_info : string := "false"; + hip_enable : string := "hip_disable"; + hrdrstctrl_en_cfgusr : string := "hrst_dis_cfgusr"; + pld_side_reserved_source10 : string := "pld_res10"; + pld_side_data_source : string := "pld"; + pld_side_reserved_source0 : string := "pld_res0"; + pld_side_reserved_source1 : string := "pld_res1"; + pld_side_reserved_source2 : string := "pld_res2"; + pld_side_reserved_source3 : string := "pld_res3"; + pld_side_reserved_source4 : string := "pld_res4"; + pld_side_reserved_source5 : string := "pld_res5"; + pld_side_reserved_source6 : string := "pld_res6"; + pld_side_reserved_source7 : string := "pld_res7"; + pld_side_reserved_source8 : string := "pld_res8"; + pld_side_reserved_source9 : string := "pld_res9"; + hrdrstctrl_en_cfg : string := "hrst_dis_cfg"; + testbus_sel : string := "eight_g_pcs"; + usrmode_sel4rst : string := "usermode"; + pld_side_reserved_source11 : string := "pld_res11"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipcomin : in std_logic_vector(37 downto 0) := "00000000000000000000000000000000000000"; + pcs8gchnltestbusout : in std_logic_vector(19 downto 0) := "00000000000000000000"; + pcs8gphystatus : in std_logic := '0'; + pcs8gpldextraout : in std_logic_vector(2 downto 0) := "000"; + pcs8grxelecidle : in std_logic := '0'; + pcs8grxstatus : in std_logic_vector(2 downto 0) := "000"; + pcs8grxvalid : in std_logic := '0'; + pcs8gtestso : in std_logic_vector(5 downto 0) := "000000"; + pcsaggtestso : in std_logic := '0'; + pcspmaiftestso : in std_logic := '0'; + pcspmaiftestbusout : in std_logic_vector(9 downto 0) := "0000000000"; + pld8gpowerdown : in std_logic_vector(1 downto 0) := "00"; + pld8gprbsciden : in std_logic := '0'; + pld8grefclkdig : in std_logic := '0'; + pld8grefclkdig2 : in std_logic := '0'; + pld8grxpolarity : in std_logic := '0'; + pld8gtxdeemph : in std_logic := '0'; + pld8gtxdetectrxloopback : in std_logic := '0'; + pld8gtxelecidle : in std_logic := '0'; + pld8gtxmargin : in std_logic_vector(2 downto 0) := "000"; + pld8gtxswing : in std_logic := '0'; + pldaggrefclkdig : in std_logic := '0'; + pldeidleinfersel : in std_logic_vector(2 downto 0) := "000"; + pldhclkin : in std_logic := '0'; + pldltr : in std_logic := '0'; + pldpartialreconfigin : in std_logic := '0'; + pldpcspmaifrefclkdig : in std_logic := '0'; + pldrate : in std_logic := '0'; + pldreservedin : in std_logic_vector(11 downto 0) := "000000000000"; + pldscanmoden : in std_logic := '0'; + pldscanshiftn : in std_logic := '0'; + pmaclklow : in std_logic := '0'; + pmafref : in std_logic := '0'; + emsipcomclkout : out std_logic_vector(2 downto 0) := "000"; + emsipcomout : out std_logic_vector(26 downto 0) := "000000000000000000000000000"; + emsipenablediocsrrdydly : out std_logic := '0'; + pcs8geidleinfersel : out std_logic_vector(2 downto 0) := "000"; + pcs8ghardreset : out std_logic := '0'; + pcs8gltr : out std_logic := '0'; + pcs8gpldextrain : out std_logic_vector(3 downto 0) := "0000"; + pcs8gpowerdown : out std_logic_vector(1 downto 0) := "00"; + pcs8gprbsciden : out std_logic := '0'; + pcs8grate : out std_logic := '0'; + pcs8grefclkdig : out std_logic := '0'; + pcs8grefclkdig2 : out std_logic := '0'; + pcs8grxpolarity : out std_logic := '0'; + pcs8gscanmoden : out std_logic := '0'; + pcs8gscanshift : out std_logic := '0'; + pcs8gtestsi : out std_logic_vector(5 downto 0) := "000000"; + pcs8gtxdeemph : out std_logic := '0'; + pcs8gtxdetectrxloopback : out std_logic := '0'; + pcs8gtxelecidle : out std_logic := '0'; + pcs8gtxmargin : out std_logic_vector(2 downto 0) := "000"; + pcs8gtxswing : out std_logic := '0'; + pcsaggrefclkdig : out std_logic := '0'; + pcsaggscanmoden : out std_logic := '0'; + pcsaggscanshift : out std_logic := '0'; + pcsaggtestsi : out std_logic := '0'; + pcspcspmaifrefclkdig : out std_logic := '0'; + pcspcspmaifscanmoden : out std_logic := '0'; + pcspcspmaifscanshiftn : out std_logic := '0'; + pcspmaifhardreset : out std_logic := '0'; + pcspmaiftestsi : out std_logic := '0'; + pld8gphystatus : out std_logic := '0'; + pld8grxelecidle : out std_logic := '0'; + pld8grxstatus : out std_logic_vector(2 downto 0) := "000"; + pld8grxvalid : out std_logic := '0'; + pldclklow : out std_logic := '0'; + pldfref : out std_logic := '0'; + pldnfrzdrv : out std_logic := '0'; + pldpartialreconfigout : out std_logic := '0'; + pldreservedout : out std_logic_vector(10 downto 0) := "00000000000"; + pldtestdata : out std_logic_vector(19 downto 0) := "00000000000000000000"; + rstsel : out std_logic := '0'; + usrrstsel : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pipe_gen1_2 + generic +( + enable_debug_info : string := "false"; + prot_mode : string := "pipe_g1"; + hip_mode : string := "dis_hip"; + tx_pipe_enable : string := "dis_pipe_tx"; + rx_pipe_enable : string := "dis_pipe_rx"; + pipe_byte_de_serializer_en : string := "dont_care_bds"; + txswing : string := "dis_txswing"; + rxdetect_bypass : string := "dis_rxdetect_bypass"; + error_replace_pad : string := "replace_edb"; + ind_error_reporting : string := "dis_ind_error_reporting"; + phystatus_rst_toggle : string := "dis_phystatus_rst_toggle"; + elecidle_delay : string := "elec_idle_delay"; + elec_idle_delay_val : bit_vector := B"0"; + phy_status_delay : string := "phystatus_delay"; + phystatus_delay_val : bit_vector := B"0"; + rvod_sel_d_val : bit_vector := B"0"; + rpre_emph_b_val : bit_vector := B"0"; + rvod_sel_c_val : bit_vector := B"0"; + rpre_emph_c_val : bit_vector := B"0"; + rpre_emph_settings : bit_vector := B"0"; + rvod_sel_a_val : bit_vector := B"0"; + rpre_emph_d_val : bit_vector := B"0"; + rvod_sel_settings : bit_vector := B"0"; + rvod_sel_b_val : bit_vector := B"0"; + rpre_emph_e_val : bit_vector := B"0"; + sup_mode : string := "user_mode"; + rvod_sel_e_val : bit_vector := B"0"; + rpre_emph_a_val : bit_vector := B"0"; + ctrl_plane_bonding_consumption : string := "individual"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + pcieswitch : in std_logic := '0'; + piperxclk : in std_logic := '0'; + pipetxclk : in std_logic := '0'; + polinvrx : in std_logic := '0'; + powerstatetransitiondone : in std_logic := '0'; + powerstatetransitiondoneena : in std_logic := '0'; + powerdown : in std_logic_vector(1 downto 0) := "00"; + refclkb : in std_logic := '0'; + refclkbreset : in std_logic := '0'; + revloopbkpcsgen3 : in std_logic := '0'; + revloopback : in std_logic := '0'; + rxdetectvalid : in std_logic := '0'; + rxfound : in std_logic := '0'; + rxpipereset : in std_logic := '0'; + rxd : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + rxelectricalidle : in std_logic := '0'; + rxpolarity : in std_logic := '0'; + sigdetni : in std_logic := '0'; + speedchange : in std_logic := '0'; + speedchangechnldown : in std_logic := '0'; + speedchangechnlup : in std_logic := '0'; + txelecidlecomp : in std_logic := '0'; + txpipereset : in std_logic := '0'; + txdch : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + txdeemph : in std_logic := '0'; + txdetectrxloopback : in std_logic := '0'; + txelecidlein : in std_logic := '0'; + txmargin : in std_logic_vector(2 downto 0) := "000"; + txswingport : in std_logic := '0'; + currentcoeff : out std_logic_vector(17 downto 0) := "000000000000000000"; + phystatus : out std_logic := '0'; + polinvrxint : out std_logic := '0'; + revloopbk : out std_logic := '0'; + rxdch : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + rxelecidle : out std_logic := '0'; + rxelectricalidleout : out std_logic := '0'; + rxstatus : out std_logic_vector(2 downto 0) := "000"; + rxvalid : out std_logic := '0'; + speedchangeout : out std_logic := '0'; + txelecidleout : out std_logic := '0'; + txd : out std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + txdetectrx : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pma_aux + generic +( + enable_debug_info : string := "false"; + cal_clk_sel : string := "pm_aux_iqclk_cal_clk_sel_cal_clk"; + cal_result_status : string := "pm_aux_result_status_tx"; + continuous_calibration : string := "false"; + pm_aux_cal_clk_test_sel : string := "false"; + rx_cal_override_value : integer := 0; + rx_cal_override_value_enable : string := "false"; + rx_imp : string := "cal_imp_46_ohm"; + test_counter_enable : string := "false"; + tx_cal_override_value : integer := 0; + tx_cal_override_value_enable : string := "false"; + tx_imp : string := "cal_imp_48_ohm"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + atb0out : inout std_logic := '0'; + atb1out : inout std_logic := '0'; + calclk : in std_logic := '0'; + calpdb : in std_logic := '0'; + refiqclk : in std_logic_vector(5 downto 0) := "000000"; + testcntl : in std_logic := '0'; + nonusertoio : out std_logic := '0'; + zrxtx50 : out std_logic_vector(4 downto 0) := "00000" + ); +end component; + +component cyclonev_hssi_pma_cdr_refclk_select_mux + generic +( + lpm_type : string := "cyclonev_hssi_pma_cdr_refclk_select_mux"; + channel_number : integer := 0; + mux_type : string := "cdr_refclk_select_mux"; + refclk_select : string := "ref_iqclk0"; + reference_clock_frequency : string := "0 ps"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + inclk0_logical_to_physical_mapping : string := ""; + inclk1_logical_to_physical_mapping : string := ""; + inclk2_logical_to_physical_mapping : string := ""; + inclk3_logical_to_physical_mapping : string := ""; + inclk4_logical_to_physical_mapping : string := ""; + inclk5_logical_to_physical_mapping : string := ""; + inclk6_logical_to_physical_mapping : string := ""; + inclk7_logical_to_physical_mapping : string := ""; + inclk8_logical_to_physical_mapping : string := ""; + inclk9_logical_to_physical_mapping : string := ""; + inclk10_logical_to_physical_mapping : string := ""; + inclk11_logical_to_physical_mapping : string := ""; + inclk12_logical_to_physical_mapping : string := ""; + inclk13_logical_to_physical_mapping : string := ""; + inclk14_logical_to_physical_mapping : string := ""; + inclk15_logical_to_physical_mapping : string := ""; + inclk16_logical_to_physical_mapping : string := ""; + inclk17_logical_to_physical_mapping : string := ""; + inclk18_logical_to_physical_mapping : string := ""; + inclk19_logical_to_physical_mapping : string := ""; + inclk20_logical_to_physical_mapping : string := ""; + inclk21_logical_to_physical_mapping : string := ""; + inclk22_logical_to_physical_mapping : string := ""; + inclk23_logical_to_physical_mapping : string := ""; + inclk24_logical_to_physical_mapping : string := ""; + inclk25_logical_to_physical_mapping : string := "" + ); + port ( + calclk : in std_logic := '0'; + refclklc: in std_logic := '0'; + occalen : in std_logic := '0'; + ffplloutbot : in std_logic := '0'; + ffpllouttop : in std_logic := '0'; + pldclk : in std_logic := '0'; + refiqclk0 : in std_logic := '0'; + refiqclk1 : in std_logic := '0'; + refiqclk10 : in std_logic := '0'; + refiqclk2 : in std_logic := '0'; + refiqclk3 : in std_logic := '0'; + refiqclk4 : in std_logic := '0'; + refiqclk5 : in std_logic := '0'; + refiqclk6 : in std_logic := '0'; + refiqclk7 : in std_logic := '0'; + refiqclk8 : in std_logic := '0'; + refiqclk9 : in std_logic := '0'; + rxiqclk0 : in std_logic := '0'; + rxiqclk1 : in std_logic := '0'; + rxiqclk10 : in std_logic := '0'; + rxiqclk2 : in std_logic := '0'; + rxiqclk3 : in std_logic := '0'; + rxiqclk4 : in std_logic := '0'; + rxiqclk5 : in std_logic := '0'; + rxiqclk6 : in std_logic := '0'; + rxiqclk7 : in std_logic := '0'; + rxiqclk8 : in std_logic := '0'; + rxiqclk9 : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + clkout : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pma_hi_pmaif + generic +( + lpm_type : string := "cyclonev_hssi_pma_hi_pmaif"; + tx_pma_direction_sel : string := "pcs" + ); + port ( + datainfromcore : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + datainfrompcs : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + dataouttopma : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + ); +end component; + +component cyclonev_hssi_pma_hi_xcvrif + generic +( + lpm_type : string := "cyclonev_hssi_pma_hi_xcvrif"; + rx_pma_direction_sel : string := "pcs" + ); + port ( + datainfrompma : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + datainfrompcs : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + dataouttopld : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + ); +end component; + +component cyclonev_hssi_pma_int + generic +( + enable_debug_info : string := "false"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + cvp_mode : string := "cvp_mode_off"; + early_eios_sel : string := "pcs_early_eios"; + ffclk_enable : string := "ffclk_off"; + iqtxrxclk_a_sel : string := "tristage_outa"; + iqtxrxclk_b_sel : string := "tristage_outb"; + ltr_sel : string := "pcs_ltr"; + pcie_switch_sel : string := "pcs_pcie_switch_sw"; + pclk_0_clk_sel : string := "pclk_0_power_down"; + pclk_1_clk_sel : string := "pclk_1_power_down"; + tx_elec_idle_sel : string := "pcs_tx_elec_idle"; + txdetectrx_sel : string := "pcs_txdetectrx" + ); + port ( + bslip : in std_logic := '0'; + ccrurstb : in std_logic := '0'; + cearlyeios : in std_logic := '0'; + clkdivrxi : in std_logic := '0'; + clkdivtxi : in std_logic := '0'; + clklowi : in std_logic := '0'; + cltd : in std_logic := '0'; + cltr : in std_logic := '0'; + cpcieswitch : in std_logic := '0'; + crslpbk : in std_logic := '0'; + ctxdetectrx : in std_logic := '0'; + ctxelecidle : in std_logic := '0'; + ctxpmarstb : in std_logic := '0'; + earlyeios : in std_logic := '0'; + frefi : in std_logic := '0'; + hclkpcsi : in std_logic := '0'; + icoeff : in std_logic_vector(11 downto 0) := "000000000000"; + ltr : in std_logic := '0'; + pcieswdonei : in std_logic := '0'; + pcieswitch : in std_logic := '0'; + pcsrxclkout : in std_logic := '0'; + pcstxclkout : in std_logic := '0'; + pfdmodelocki : in std_logic := '0'; + pldclk : in std_logic := '0'; + ppmlock : in std_logic := '0'; + rxdetclk : in std_logic := '0'; + rxdetectvalidi : in std_logic := '0'; + rxfoundi : in std_logic := '0'; + rxplllocki : in std_logic := '0'; + rxpmarstb : in std_logic := '0'; + sdi : in std_logic := '0'; + testbusi : in std_logic_vector(7 downto 0) := "00000000"; + testsel : in std_logic_vector(3 downto 0) := "0000"; + txdetectrx : in std_logic := '0'; + txelecidle : in std_logic := '0'; + bslipo : out std_logic := '0'; + clklow : out std_logic := '0'; + cpcieswdone : out std_logic := '0'; + cpclk : out std_logic_vector(1 downto 0) := "00"; + cpfdmodelock : out std_logic := '0'; + crurstbo : out std_logic := '0'; + crxdetectvalid : out std_logic := '0'; + crxfound : out std_logic := '0'; + crxplllock : out std_logic := '0'; + csd : out std_logic := '0'; + earlyeioso : out std_logic := '0'; + fref : out std_logic := '0'; + hclkpcs : out std_logic := '0'; + icoeffo : out std_logic_vector(11 downto 0) := "000000000000"; + iqtxrxclka : out std_logic := '0'; + iqtxrxclkb : out std_logic := '0'; + ltdo : out std_logic := '0'; + ltro : out std_logic := '0'; + pcieswdone : out std_logic := '0'; + pcieswitcho : out std_logic := '0'; + pfdmodelock : out std_logic := '0'; + pldclko : out std_logic := '0'; + ppmlocko : out std_logic := '0'; + rxdetclko : out std_logic := '0'; + rxdetectvalid : out std_logic := '0'; + rxfound : out std_logic := '0'; + rxplllock : out std_logic := '0'; + rxpmarstbo : out std_logic := '0'; + sd : out std_logic := '0'; + slpbko : out std_logic := '0'; + testbus : out std_logic_vector(7 downto 0) := "00000000"; + testselo : out std_logic_vector(3 downto 0) := "0000"; + txdetectrxo : out std_logic := '0'; + txelecidleo : out std_logic := '0'; + txpmarstbo : out std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pma_rx_buf + generic +( + enable_debug_info : string := "false"; + cdrclk_to_cgb : string := "cdrclk_2cgb_dis"; + channel_number : integer := 0; + diagnostic_loopback : string := "diag_lpbk_off"; + pdb_sd : string := "false"; + rx_dc_gain : integer := 0; + sd_off : integer := 1; + sd_on : integer := 1; + sd_threshold : integer := 3; + term_sel : string := "100 ohms"; + vcm_current_add : string := "vcm_current_1"; + vcm_sel : string := "vtt_0p80v"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + rx_sel_half_bw : string := "full_bw"; + rx_acgain_a : string := "aref_volt_0"; + rx_acgain_v : string := "vref_volt_1p0"; + ct_equalizer_setting : integer := 0; + reverse_loopback : string := "reverse_lpbk_cdr" + ); + port ( + ck0sigdet : in std_logic := '0'; + datain : in std_logic := '0'; + hardoccalen : in std_logic := '0'; + lpbkp : in std_logic := '0'; + rstn : in std_logic := '0'; + slpbk : in std_logic := '0'; + dataout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0'; + rdlpbkp : out std_logic := '0'; + sd : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pma_rx_deser + generic +( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + channel_number : integer := 0; + clk_forward_only_mode : string := "false"; + enable_bit_slip : string := "true"; + mode : integer := 8; + sdclk_enable : string := "false"; + vco_bypass : string := "vco_bypass_normal"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + pma_direct : string := "false" + ); + port ( + bslip : in std_logic := '0'; + clk270b : in std_logic := '0'; + clk90b : in std_logic := '0'; + deven : in std_logic := '0'; + dodd : in std_logic := '0'; + pciesw : in std_logic := '0'; + rstn : in std_logic := '0'; + clkdivrx : out std_logic := '0'; + clkdivrxrx : out std_logic := '0'; + dout : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + pciel : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pma_tx_buf + generic +( + enable_debug_info : string := "false"; + channel_number : integer := 0; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + common_mode_driver_sel : string := "volt_0p65v"; + driver_resolution_ctrl : string := "disabled"; + fir_coeff_ctrl_sel : string := "ram_ctl"; + local_ib_ctl : string := "ib_29ohm"; + lst : string := "atb_disabled"; + pre_emp_switching_ctrl_1st_post_tap : integer := 0; + rx_det : integer := 0; + rx_det_pdb : string := "false"; + slew_rate_ctrl : integer := 5; + swing_boost : string := "not_boost"; + term_sel : string := "100 ohms"; + vcm_current_addl : string := "vcm_current_1"; + vod_boost : string := "not_boost"; + vod_switching_ctrl_main_tap : integer := 10; + local_ib_en : string := "no_local_ib"; + cml_en : string := "no_cml"; + tx_powerdown : string := "normal_tx_on" + ); + port ( + avgvon : in std_logic := '0'; + avgvop : in std_logic := '0'; + datain : in std_logic := '0'; + icoeff : in std_logic_vector(11 downto 0) := "000000000000"; + rxdetclk : in std_logic := '0'; + txdetrx : in std_logic := '0'; + txelecidl : in std_logic := '0'; + vrlpbkn : in std_logic := '0'; + vrlpbkn1t : in std_logic := '0'; + vrlpbkp : in std_logic := '0'; + vrlpbkp1t : in std_logic := '0'; + compass : out std_logic := '0'; + dataout : out std_logic := '0'; + detecton : out std_logic_vector(1 downto 0) := "00"; + fixedclkout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0'; + probepass : out std_logic := '0'; + rxdetectvalid : out std_logic := '0'; + rxfound : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pma_tx_cgb + generic +( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + cgb_iqclk_sel : string := "tristate"; + cgb_sync : string := "normal"; + channel_number : integer := 0; + clk_mute : string := "disable_clockmute"; + data_rate : string := ""; + mode : integer := 8; + reset_scheme : string := "counter_reset_disable"; + tx_mux_power_down : string := "normal"; + x1_clock_source_sel : string := "x1_clk_unused"; + x1_div_m_sel : integer := 1; + xn_clock_source_sel : string := "cgb_x1_m_div"; + pcie_rst : string := "normal_reset"; + fref_vco_bypass : string := "normal_operation"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + x1_clock0_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock1_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock2_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock3_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock4_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock5_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock6_logical_to_physical_mapping : string := "x1_clk_unused"; + x1_clock7_logical_to_physical_mapping : string := "x1_clk_unused"; + reserved_transmit_channel : string := "false" + ); + port ( + clkbcdr1b : in std_logic := '0'; + clkbcdr1t : in std_logic := '0'; + clkbcdrloc : in std_logic := '0'; + clkbdnseg : in std_logic := '0'; + clkbffpll : in std_logic := '0'; + clkbupseg : in std_logic := '0'; + clkcdr1b : in std_logic := '0'; + clkcdr1t : in std_logic := '0'; + clkcdrloc : in std_logic := '0'; + clkdnseg : in std_logic := '0'; + clkffpll : in std_logic := '0'; + clkupseg : in std_logic := '0'; + cpulsex6dn : in std_logic := '0'; + cpulsex6up : in std_logic := '0'; + cpulsexndn : in std_logic := '0'; + cpulsexnup : in std_logic := '0'; + hfclknx6dn : in std_logic := '0'; + hfclknx6up : in std_logic := '0'; + hfclknxndn : in std_logic := '0'; + hfclknxnup : in std_logic := '0'; + hfclkpx6dn : in std_logic := '0'; + hfclkpx6up : in std_logic := '0'; + hfclkpxndn : in std_logic := '0'; + hfclkpxnup : in std_logic := '0'; + lfclknx6dn : in std_logic := '0'; + lfclknx6up : in std_logic := '0'; + lfclknxndn : in std_logic := '0'; + lfclknxnup : in std_logic := '0'; + lfclkpx6dn : in std_logic := '0'; + lfclkpx6up : in std_logic := '0'; + lfclkpxndn : in std_logic := '0'; + lfclkpxnup : in std_logic := '0'; + pciesw : in std_logic := '0'; + pclkx6dn : in std_logic := '0'; + pclkx6up : in std_logic := '0'; + pclkxndn : in std_logic := '0'; + pclkxnup : in std_logic := '0'; + rstn : in std_logic := '0'; + rxclk : in std_logic := '0'; + cpulse : out std_logic := '0'; + cpulseout : out std_logic := '0'; + hfclkn : out std_logic := '0'; + hfclknout : out std_logic := '0'; + hfclkp : out std_logic := '0'; + hfclkpout : out std_logic := '0'; + lfclkn : out std_logic := '0'; + lfclknout : out std_logic := '0'; + lfclkp : out std_logic := '0'; + lfclkpout : out std_logic := '0'; + pcieswdone : out std_logic := '0'; + pciesyncp : out std_logic := '0'; + pclk : out std_logic_vector(2 downto 0) := "000"; + pclkout : out std_logic := '0'; + rxiqclk : out std_logic := '0'; + fref : in std_logic := '0'; + pcsrstn : in std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '1'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_pma_tx_ser + generic +( + enable_debug_info : string := "false"; + auto_negotiation : string := "false"; + channel_number : integer := 0; + clk_divtx_deskew : integer := 0; + clk_forward_only_mode : string := "false"; + forced_data_mode : bit := '0'; + mode : integer := 8; + post_tap_1_en : string := "false"; + ser_loopback : string := "false"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0; + pma_direct : string := "false"; + duty_cycle_tune : string := "duty_cycle3" + ); + port ( + cpulse : in std_logic := '0'; + datain : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + hfclk : in std_logic := '0'; + hfclkn : in std_logic := '0'; + lfclk : in std_logic := '0'; + lfclkn : in std_logic := '0'; + pclk : in std_logic_vector(2 downto 0) := "000"; + rstn : in std_logic := '1'; + slpbk : in std_logic := '0'; + clkdivtx : out std_logic := '0'; + dataout : out std_logic := '0'; + lbvop : out std_logic := '0'; + preenout : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '1'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0'; + avgvon : out std_logic := '0'; + avgvop : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_refclk_divider + generic +( + lpm_type : string := "cyclonev_hssi_refclk_divider"; + divide_by : integer := 1; + enabled : string := "true"; + refclk_coupling_termination : string := "normal_100_ohm_termination" + ); + port ( + refclkin : in std_logic := '0'; + refclkout : out std_logic := '0'; + nonuserfrompmaux : in std_logic := '0' + ); +end component; + +component cyclonev_hssi_rx_pcs_pma_interface + generic +( + enable_debug_info : string := "false"; + selectpcs : string := "eight_g_pcs"; + clkslip_sel : string := "pld"; + prot_mode : string := "other_protocols"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + pcs8grxclkiqout : in std_logic := '0'; + pcs8grxclkslip : in std_logic := '0'; + pldrxclkslip : in std_logic := '0'; + pldrxpmarstb : in std_logic := '0'; + pmareservedin : in std_logic_vector(4 downto 0) := "00000"; + datainfrompma : in std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + pmarxpllphaselockin : in std_logic := '0'; + clockinfrompma : in std_logic := '0'; + pmasigdet : in std_logic := '0'; + dataoutto8gpcs : out std_logic_vector(19 downto 0) := "00000000000000000000"; + clockoutto8gpcs : out std_logic := '0'; + pcs8gsigdetni : out std_logic := '0'; + pmareservedout : out std_logic_vector(4 downto 0) := "00000"; + pmarxclkout : out std_logic := '0'; + pmarxpllphaselockout : out std_logic := '0'; + pmarxclkslip : out std_logic := '0'; + pmarxpmarstb : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_rx_pld_pcs_interface + generic +( + enable_debug_info : string := "false"; + is_8g_0ppm : string := "false"; + pcs_side_block_sel : string := "eight_g_pcs"; + pld_side_data_source : string := "pld"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipenablediocsrrdydly : in std_logic := '0'; + emsiprxspecialin : in std_logic_vector(12 downto 0) := "0000000000000"; + pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0) := "0000"; + pcs8galignstatus : in std_logic := '0'; + pcs8gbistdone : in std_logic := '0'; + pcs8gbisterr : in std_logic := '0'; + pcs8gbyteordflag : in std_logic := '0'; + pcs8gemptyrmf : in std_logic := '0'; + pcs8gemptyrx : in std_logic := '0'; + pcs8gfullrmf : in std_logic := '0'; + pcs8gfullrx : in std_logic := '0'; + pcs8grlvlt : in std_logic := '0'; + clockinfrom8gpcs : in std_logic := '0'; + pcs8grxdatavalid : in std_logic_vector(3 downto 0) := "0000"; + datainfrom8gpcs : in std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + pcs8gsignaldetectout : in std_logic := '0'; + pcs8gwaboundary : in std_logic_vector(4 downto 0) := "00000"; + pld8ga1a2size : in std_logic := '0'; + pld8gbitlocreven : in std_logic := '0'; + pld8gbitslip : in std_logic := '0'; + pld8gbytereven : in std_logic := '0'; + pld8gbytordpld : in std_logic := '0'; + pld8gcmpfifourstn : in std_logic := '0'; + pld8gencdt : in std_logic := '0'; + pld8gphfifourstrxn : in std_logic := '0'; + pld8gpldrxclk : in std_logic := '0'; + pld8gpolinvrx : in std_logic := '0'; + pld8grdenablermf : in std_logic := '0'; + pld8grdenablerx : in std_logic := '0'; + pld8grxurstpcsn : in std_logic := '0'; + pld8gwrdisablerx : in std_logic := '0'; + pld8gwrenablermf : in std_logic := '0'; + pldrxclkslipin : in std_logic := '0'; + pldrxpmarstbin : in std_logic := '0'; + pld8gsyncsmeninput : in std_logic := '0'; + pmarxplllock : in std_logic := '0'; + rstsel : in std_logic := '0'; + usrrstsel : in std_logic := '0'; + emsiprxout : out std_logic_vector(128 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + emsiprxspecialout : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcs8ga1a2size : out std_logic := '0'; + pcs8gbitlocreven : out std_logic := '0'; + pcs8gbitslip : out std_logic := '0'; + pcs8gbytereven : out std_logic := '0'; + pcs8gbytordpld : out std_logic := '0'; + pcs8gcmpfifourst : out std_logic := '0'; + pcs8gencdt : out std_logic := '0'; + pcs8gphfifourstrx : out std_logic := '0'; + pcs8gpldrxclk : out std_logic := '0'; + pcs8gpolinvrx : out std_logic := '0'; + pcs8grdenablermf : out std_logic := '0'; + pcs8grdenablerx : out std_logic := '0'; + pcs8grxurstpcs : out std_logic := '0'; + pcs8gsyncsmenoutput : out std_logic := '0'; + pcs8gwrdisablerx : out std_logic := '0'; + pcs8gwrenablermf : out std_logic := '0'; + pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0) := "0000"; + pld8galignstatus : out std_logic := '0'; + pld8gbistdone : out std_logic := '0'; + pld8gbisterr : out std_logic := '0'; + pld8gbyteordflag : out std_logic := '0'; + pld8gemptyrmf : out std_logic := '0'; + pld8gemptyrx : out std_logic := '0'; + pld8gfullrmf : out std_logic := '0'; + pld8gfullrx : out std_logic := '0'; + pld8grlvlt : out std_logic := '0'; + pld8grxclkout : out std_logic := '0'; + pld8grxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + pld8gsignaldetectout : out std_logic := '0'; + pld8gwaboundary : out std_logic_vector(4 downto 0) := "00000"; + pldrxclkslipout : out std_logic := '0'; + dataouttopld : out std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; + pldrxpmarstbout : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_tx_pcs_pma_interface + generic +( + enable_debug_info : string := "false"; + selectpcs : string := "eight_g_pcs"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + datainfrom8gpcs : in std_logic_vector(19 downto 0) := "00000000000000000000"; + pcs8gtxclkiqout : in std_logic := '0'; + pmarxfreqtxcmuplllockin : in std_logic := '0'; + clockinfrompma : in std_logic := '0'; + clockoutto8gpcs : out std_logic := '0'; + pmarxfreqtxcmuplllockout : out std_logic := '0'; + pmatxclkout : out std_logic := '0'; + dataouttopma : out std_logic_vector(79 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmrstn : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_hssi_tx_pld_pcs_interface + generic +( + enable_debug_info : string := "false"; + is_8g_0ppm : string := "false"; + pld_side_data_source : string := "pld"; + avmm_group_channel_index : integer := 0; + use_default_base_address : string := "true"; + user_base_address : integer := 0 + ); + port ( + emsipenablediocsrrdydly : in std_logic := '0'; + emsiptxin : in std_logic_vector(103 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + emsiptxspecialin : in std_logic_vector(12 downto 0) := "0000000000000"; + pcs8gemptytx : in std_logic := '0'; + pcs8gfulltx : in std_logic := '0'; + clockinfrom8gpcs : in std_logic := '0'; + pld8gphfifoursttxn : in std_logic := '0'; + pld8gpldtxclk : in std_logic := '0'; + pld8gpolinvtx : in std_logic := '0'; + pld8grddisabletx : in std_logic := '0'; + pld8grevloopbk : in std_logic := '0'; + pld8gtxboundarysel : in std_logic_vector(4 downto 0) := "00000"; + pld8gtxdatavalid : in std_logic_vector(3 downto 0) := "0000"; + pld8gtxurstpcsn : in std_logic := '0'; + pld8gwrenabletx : in std_logic := '0'; + datainfrompld : in std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + pmatxcmuplllock : in std_logic := '0'; + rstsel : in std_logic := '0'; + usrrstsel : in std_logic := '0'; + emsippcstxclkout : out std_logic_vector(2 downto 0) := "000"; + emsiptxspecialout : out std_logic_vector(15 downto 0) := "0000000000000000"; + pcs8gphfifoursttx : out std_logic := '0'; + pcs8gpldtxclk : out std_logic := '0'; + pcs8gpolinvtx : out std_logic := '0'; + pcs8grddisabletx : out std_logic := '0'; + pcs8grevloopbk : out std_logic := '0'; + pcs8gtxboundarysel : out std_logic_vector(4 downto 0) := "00000"; + pcs8gtxdatavalid : out std_logic_vector(3 downto 0) := "0000"; + dataoutto8gpcs : out std_logic_vector(43 downto 0) := "00000000000000000000000000000000000000000000"; + pcs8gtxurstpcs : out std_logic := '0'; + pcs8gwrenabletx : out std_logic := '0'; + pld8gemptytx : out std_logic := '0'; + pld8gfulltx : out std_logic := '0'; + pld8gtxclkout : out std_logic := '0'; + asynchdatain : out std_logic := '0'; + reset : out std_logic := '0'; + avmmaddress : in std_logic_vector(10 downto 0) := "00000000000"; + avmmbyteen : in std_logic_vector(1 downto 0) := "00"; + avmmrstn : in std_logic := '0'; + avmmclk : in std_logic := '0'; + avmmread : in std_logic := '0'; + avmmwrite : in std_logic := '0'; + avmmwritedata : in std_logic_vector(15 downto 0) := "0000000000000000"; + avmmreaddata : out std_logic_vector(15 downto 0) := "0000000000000000"; + blockselect : out std_logic := '0' + ); +end component; + +component cyclonev_pll_aux + generic +( + lpm_type : string := "cyclonev_pll_aux"; + pl_aux_atb_atben0_precomp : bit := '1'; + pl_aux_atb_atben1_precomp : bit := '1'; + pl_aux_atb_comp_minus : bit := '0'; + pl_aux_atb_comp_plus : bit := '0'; + pl_aux_comp_pwr_dn : bit := '1' + ); + port ( + atb0out : in std_logic := '0'; + atb1out : in std_logic := '0'; + atbcompout : out std_logic := '0' + ); +end component; + +end CYCLONEV_HSSI_COMPONENTS; + +package body CYCLONEV_HSSI_COMPONENTS is + +function bin2int (s : std_logic_vector) return integer is + + constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : bit_vector) return integer is + + constant temp : bit_vector(s'high-s'low DOWNTO 0) := s; + variable result : integer := 0; + begin + for i in temp'range loop + if (temp(i) = '1') then + result := result + (2**i); + end if; + end loop; + return(result); + end bin2int; + +function bin2int (s : std_logic) return integer is + constant temp : std_logic := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + +function bin2int (s : bit) return integer is + constant temp : bit := s; + variable result : integer := 0; + begin + if (temp = '1') then + result := 1; + else + result := 0; + end if; + return(result); + end bin2int; + +function str2bin (s : string) return std_logic_vector is +variable len : integer := s'length; +variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0'); +variable i : integer; +begin + for i in 1 to len loop + case s(i) is + when '0' => result(len - i) := '0'; + when '1' => result(len - i) := '1'; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + end loop; + return result; +end; + +function str2int (s : string) return integer is +variable len : integer := s'length; +variable newdigit : integer := 0; +variable sign : integer := 1; +variable digit : integer := 0; +begin + for i in 1 to len loop + case s(i) is + when '-' => + if i = 1 then + sign := -1; + else + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR; + end if; + when '0' => + digit := 0; + when '1' => + digit := 1; + when '2' => + digit := 2; + when '3' => + digit := 3; + when '4' => + digit := 4; + when '5' => + digit := 5; + when '6' => + digit := 6; + when '7' => + digit := 7; + when '8' => + digit := 8; + when '9' => + digit := 9; + when others => + ASSERT FALSE + REPORT "Illegal Character "& s(i) & "in string parameter! " + SEVERITY ERROR; + end case; + newdigit := newdigit * 10 + digit; + end loop; + + return (sign*newdigit); +end; + +function int2bin (arg : integer; size : integer) return std_logic_vector is + variable int_val : integer := arg; + variable result : std_logic_vector(size-1 downto 0); + begin + for i in 0 to result'left loop + if ((int_val mod 2) = 0) then + result(i) := '0'; + else + result(i) := '1'; + end if; + int_val := int_val/2; + end loop; + return result; + end int2bin; + +function int2bin (arg : boolean; size : integer) return std_logic_vector is + variable result : std_logic_vector(size-1 downto 0); + begin + if(arg)then + result := (OTHERS => '1'); + else + result := (OTHERS => '0'); + end if; + return result; + end int2bin; + +function int2bit (arg : integer) return std_logic is + variable int_val : integer := arg; + variable result : std_logic; + begin + + if (int_val = 0) then + result := '0'; + else + result := '1'; + end if; + + return result; +end int2bit; + +function int2bit (arg : boolean) return std_logic is + variable int_val : boolean := arg; + variable result : std_logic; + begin + + if (int_val ) then + result := '1'; + else + result := '0'; + end if; + + return result; +end int2bit; + + +end CYCLONEV_HSSI_COMPONENTS;